From 1ef262d62712a480b1e0275113030b42651d85f8 Mon Sep 17 00:00:00 2001 From: "copilot-swe-agent[bot]" <198982749+Copilot@users.noreply.github.com> Date: Mon, 17 Nov 2025 03:55:49 +0000 Subject: [PATCH 1/9] Initial plan From 922236c5a12f9e932f22d5a0c3817b8a5c3aceed Mon Sep 17 00:00:00 2001 From: "copilot-swe-agent[bot]" <198982749+Copilot@users.noreply.github.com> Date: Mon, 17 Nov 2025 04:09:27 +0000 Subject: [PATCH 2/9] Add comprehensive help descriptions to Kconfig files in libcpu and components Co-authored-by: Rbb666 <64397326+Rbb666@users.noreply.github.com> --- components/Kconfig | 93 +++ components/mprotect/Kconfig | 140 ++++ libcpu/Kconfig | 1252 ++++++++++++++++++++++++++++++++++- libcpu/aarch64/Kconfig | 138 ++++ 4 files changed, 1616 insertions(+), 7 deletions(-) diff --git a/components/Kconfig b/components/Kconfig index 0b9b3ab9d0e..c30c2cde19c 100644 --- a/components/Kconfig +++ b/components/Kconfig @@ -3,27 +3,120 @@ menu "RT-Thread Components" config RT_USING_COMPONENTS_INIT bool default n + help + Enable automatic component initialization framework. + + When enabled, components marked with INIT_EXPORT() macros will be + automatically initialized during system startup in proper order. + + Initialization levels (in order): + - INIT_BOARD_EXPORT: Board-level initialization (pins, clocks) + - INIT_PREV_EXPORT: Early driver initialization + - INIT_DEVICE_EXPORT: Device driver initialization + - INIT_COMPONENT_EXPORT: Component initialization + - INIT_ENV_EXPORT: Environment initialization + - INIT_APP_EXPORT: Application initialization + + Benefits: + - Automatic dependency ordering + - Cleaner code (no manual init function calls) + - Consistent initialization across components + + Note: Most RT-Thread components rely on this. Usually enabled automatically + by build system. config RT_USING_USER_MAIN bool default n + help + Use user-defined main() function as entry point. + + When enabled, RT-Thread creates a main thread that calls your main() function, + allowing traditional C programming style entry point. + + Without this option: You must manually create threads from application + With this option: Your main() function runs in a dedicated main thread + + The main thread: + - Runs after system initialization + - Has configurable stack size and priority + - Can use RT-Thread APIs like any other thread + - Can create additional threads + + Enable this for easier application development and familiar entry point. if RT_USING_USER_MAIN config RT_MAIN_THREAD_STACK_SIZE int "Set main thread stack size" default 6144 if ARCH_CPU_64BIT default 2048 + help + Stack size in bytes for the main thread. + + Default values: + - 64-bit architectures: 6144 bytes (6KB) + - 32-bit architectures: 2048 bytes (2KB) + + Increase if: + - Deep recursion in main() + - Large local variables + - Stack overflow in main thread + - Complex initialization requiring more stack + + Decrease for memory-constrained systems if main() is simple. + + Note: Each thread's stack is separate. This only affects main thread. config RT_MAIN_THREAD_PRIORITY int "Set main thread priority" default 4 if RT_THREAD_PRIORITY_8 default 10 if RT_THREAD_PRIORITY_32 default 85 if RT_THREAD_PRIORITY_256 + help + Priority of the main thread (lower number = higher priority). + + Default values scale with priority levels: + - 8 levels: Priority 4 (middle-low priority) + - 32 levels: Priority 10 (medium priority) + - 256 levels: Priority 85 (medium-low priority) + + Lower values (higher priority) if: + - Main thread needs to preempt other tasks + - Time-critical initialization in main() + + Higher values (lower priority) if: + - Main thread is just coordination/monitoring + - Other threads need priority over main + + Note: Priority 0 is highest, maximum is configured by RT_THREAD_PRIORITY_MAX. endif config RT_USING_LEGACY bool "Support legacy version for compatibility" default n + help + Enable compatibility layer for legacy RT-Thread versions. + + Provides deprecated APIs and compatibility shims for older code, + allowing gradual migration to newer RT-Thread versions. + + Includes: + - Deprecated API wrappers + - Legacy component interfaces + - Backward-compatible behavior + + Enable if: + - Porting code from older RT-Thread versions + - Using third-party libraries requiring legacy APIs + - Gradual migration strategy + + Disable for: + - New projects (use modern APIs) + - Smaller code size + - Better performance (no compatibility overhead) + + Note: Legacy support may be removed in future versions. + Plan to migrate to current APIs. if RT_USING_CONSOLE rsource "finsh/Kconfig" diff --git a/components/mprotect/Kconfig b/components/mprotect/Kconfig index 82348cbd9bb..714a4b218ad 100644 --- a/components/mprotect/Kconfig +++ b/components/mprotect/Kconfig @@ -4,25 +4,165 @@ config RT_USING_MEM_PROTECTION bool "Enable memory protection" default n select RT_USING_HEAP + help + Enable memory protection framework using MPU (Memory Protection Unit). + + Provides hardware-based memory protection to prevent: + - Stack overflow and underflow + - Buffer overruns + - Unauthorized access to memory regions + - Corruption of kernel data structures + + Features: + - Per-thread memory protection + - Stack guard regions + - Configurable memory regions with access permissions + - Exclusive regions for sensitive data + + Requirements: + - CPU with MPU support (Cortex-M3/M4/M7/M33/R52, etc.) + - ARCH_MM_MPU or ARCH_ARM_MPU enabled + - RT_USING_HEAP (dynamic memory) + + Benefits: + - Catch memory bugs early (development) + - Improve system safety (production) + - Isolate thread memory spaces + + Costs: + - Context switch overhead (save/restore MPU regions) + - Configuration complexity + - Slight runtime overhead + + Ideal for safety-critical applications and debugging memory issues. config RT_USING_HW_STACK_GUARD bool "Enable hardware stack guard" default n select RT_USING_MEM_PROTECTION + help + Enable hardware-based stack overflow protection using MPU. + + Automatically creates guard regions at the end of each thread's stack + to detect stack overflow at the moment it occurs. + + How it works: + - Configures MPU region below stack as no-access + - Stack overflow triggers immediate MPU fault + - Exception handler identifies the overflowing thread + + Benefits: + - Immediate detection (vs periodic checks) + - Precise identification of overflow location + - No runtime overhead (hardware-based) + - Catches stack corruption before it spreads + + Requirements: + - RT_USING_MEM_PROTECTION enabled + - Sufficient MPU regions (at least 1 per thread) + + Recommended for: + - Development and debugging + - Safety-critical systems + - Systems with limited stack space + + Note: Requires one MPU region per thread. Check NUM_MEM_REGIONS configuration. if RT_USING_MEM_PROTECTION config USE_MEM_PROTECTION_EXAMPLES bool "Use memory protection examples" default y + help + Build and include memory protection example code. + + Provides demonstration code showing how to: + - Configure memory protection regions + - Set up stack guards + - Add exclusive regions + - Handle protection faults + + Useful for: + - Learning memory protection concepts + - Testing MPU functionality + - Debugging protection configurations + + Disable for production builds to save code space. config NUM_MEM_REGIONS int "Total number of memory protection regions supported by hardware" + help + Total number of MPU regions available in hardware. + + This depends on your CPU architecture: + - Cortex-M3/M4: Typically 8 regions + - Cortex-M7: 8 or 16 regions + - Cortex-M33/M85: 8 or 16 regions (configurable in silicon) + - Cortex-R52: 16 or 32 regions + + Check your MCU datasheet or reference manual for exact count. + + Usage breakdown: + - Stack guard per thread: 1 region per thread + - Exclusive regions: NUM_EXCLUSIVE_REGIONS + - Configurable per thread: NUM_CONFIGURABLE_REGIONS + + Formula: NUM_MEM_REGIONS = 1 (stack) + NUM_EXCLUSIVE_REGIONS + NUM_CONFIGURABLE_REGIONS + + Example for 8-region MPU with 2 threads: + - Thread 1 stack guard: 1 region + - Thread 2 stack guard: 1 region + - Shared exclusive regions: 2 regions + - Per-thread config: 2 regions per thread + Total: 2 + 2 + 4 = 8 regions config NUM_EXCLUSIVE_REGIONS int "Total number of exclusive memory regions added using rt_mprotect_add_exclusive_region API" + help + Number of shared exclusive memory protection regions. + + Exclusive regions are memory areas with specific access permissions + shared across all threads (e.g., peripheral registers, kernel data). + + Use cases: + - Protect peripheral registers from thread access + - Mark flash memory as read-only/execute-only + - Protect kernel data structures + - Define shared memory with specific permissions + + Example configurations: + - Peripheral protection: 1-2 regions + - Kernel data protection: 1 region + - Shared buffers: 0-2 regions + + Note: These regions are configured once and apply to all threads. + Set based on your system's protection requirements. config NUM_CONFIGURABLE_REGIONS int "Maximum number of configurable memory regions for each thread, excluding stack guard and exclusive regions added using rt_mprotect_add_exclusive_region API" + help + Per-thread configurable memory protection regions. + + These regions are specific to each thread and can be configured independently + for thread-specific memory protection needs. + + Use cases: + - Protect thread's private data buffers + - Restrict access to thread-local peripherals + - Define custom memory permissions per thread + + Calculation: + NUM_CONFIGURABLE_REGIONS = NUM_MEM_REGIONS - 1 (stack) - NUM_EXCLUSIVE_REGIONS + + Example for 8-region MPU with 2 exclusive regions: + NUM_CONFIGURABLE_REGIONS = 8 - 1 - 2 = 5 regions per thread + + More regions = more flexibility but: + - Increased configuration complexity + - Longer context switch time + - More memory for region descriptors + + Set based on your application's per-thread protection needs. + Typical values: 1-4 regions per thread. endif endmenu diff --git a/libcpu/Kconfig b/libcpu/Kconfig index b089b61725c..f3f50ffbe34 100644 --- a/libcpu/Kconfig +++ b/libcpu/Kconfig @@ -4,73 +4,395 @@ endif config ARCH_CPU_64BIT bool + help + Indicates that this architecture uses 64-bit addressing and data types. + When enabled, pointers and registers are 64-bit wide, providing access + to larger memory spaces (>4GB). This is automatically selected by 64-bit + architectures like AArch64, RISC-V64, and MIPS64. + + Impact: Affects memory layout, data structure sizes, and ABI conventions. config RT_USING_CACHE bool default n + help + Enable CPU cache support for data and instruction caches. + + When enabled, RT-Thread will provide cache management APIs (flush, invalidate) + and properly handle cache coherency during DMA operations and memory management. + This is essential for high-performance CPUs like Cortex-A and Cortex-M7. + + Typical use cases: + - DMA transfers requiring cache synchronization + - Memory-mapped I/O operations + - Multi-core systems requiring cache coherency + + Note: Automatically selected by architectures with cache support (e.g., Cortex-M7, + Cortex-A series, ARMv8). Improper cache management can lead to data corruption. config RT_USING_HW_ATOMIC bool default n + help + Enable hardware atomic operations support using CPU-specific instructions. + + When enabled, RT-Thread uses hardware atomic instructions (e.g., LDREX/STREX on ARM, + atomic instructions on RISC-V) for lock-free synchronization primitives, improving + performance and reducing interrupt latency compared to software implementations. + + Automatically selected by CPUs with atomic instruction support: + - ARM Cortex-M3 and above (LDREX/STREX) + - ARM Cortex-A series + - ARM Cortex-R series + - RISC-V with 'A' extension + + Benefits: Better performance for spinlocks, reference counting, and concurrent data structures. + No action required - this is automatically configured based on CPU architecture. config ARCH_CPU_BIG_ENDIAN bool + help + Indicates that this CPU uses big-endian byte ordering. + + In big-endian systems, the most significant byte is stored at the lowest memory address. + This affects how multi-byte data (integers, floats) are stored and accessed in memory. + + Most ARM, RISC-V, and x86 systems use little-endian. Big-endian is common in: + - Some PowerPC configurations + - MIPS systems (configurable) + - Network protocols (network byte order) + + Note: This must match your hardware configuration. Incorrect setting will cause + data corruption when accessing multi-byte values. config ARCH_ARM_BOOTWITH_FLUSH_CACHE bool default n + help + Flush and disable caches during system boot on ARM platforms. + + When enabled, the bootloader will flush and disable instruction and data caches + before jumping to RT-Thread kernel. This ensures clean cache state during initialization. + + Enable this when: + - Bootloader leaves caches in inconsistent state + - Transitioning from another OS or bootloader + - Debugging cache-related boot issues + + Note: Not needed for most configurations. Only enable if experiencing boot failures + related to stale cache data. config ARCH_CPU_STACK_GROWS_UPWARD bool default n + help + Indicates that the stack grows toward higher memory addresses (upward). + + Most architectures (ARM, RISC-V, x86, MIPS) use downward-growing stacks where + the stack pointer decreases as items are pushed. However, some architectures + like TI DSP C28x use upward-growing stacks. + + This setting affects: + - Stack pointer initialization and overflow detection + - Context switching and exception handling + - Stack boundary checking + + Note: This is architecture-specific and automatically configured. Do not change + unless porting to a new architecture with upward-growing stack. config RT_USING_CPU_FFS bool default n + help + Enable optimized Find First Set (FFS) implementation using CPU instructions. + + FFS finds the position of the first (least significant) bit set in a word. When enabled, + RT-Thread uses hardware instructions like CLZ (Count Leading Zeros) on ARM or equivalent + on other architectures for fast bit scanning operations. + + Used internally by: + - Scheduler for finding highest-priority ready thread + - Bitmap operations + - IPC mechanisms + + Automatically selected by CPUs with FFS support: + - ARM Cortex-M3 and above (CLZ instruction) + - ARM Cortex-A series + - ARM Cortex-R series + + Benefits: Significantly faster scheduler operation (O(1) vs O(n) thread selection). + No configuration needed - automatically enabled for supported CPUs. config ARCH_MM_MMU bool + help + Enable Memory Management Unit (MMU) support for virtual memory. + + MMU provides hardware-based virtual memory management, enabling: + - Virtual to physical address translation + - Memory protection between processes + - Demand paging and memory mapping + - Separate address spaces for different processes + + Required for: + - RT-Smart mode (user-space applications) + - Process isolation and protection + - Dynamic memory mapping (mmap) + - Copy-on-write mechanisms + + Automatically selected by MMU-capable architectures: + - ARM Cortex-A series + - AArch64 (ARMv8) + - RISC-V with Sv39/Sv48 paging + + Note: MMU requires proper page table setup and increases system complexity. + Only available on CPUs with hardware MMU support. config ARCH_MM_MPU bool + help + Enable Memory Protection Unit (MPU) support. + + MPU provides hardware-based memory protection without full virtual memory capabilities. + Unlike MMU, MPU works with physical addresses and has limited number of regions (typically 8-16). + + Features: + - Protect memory regions from unauthorized access + - Define region permissions (read, write, execute) + - Prevent stack overflow and buffer overruns + - Isolate kernel from user code + + Common use cases: + - Thread stack protection + - Peripheral register protection + - Code/data separation + - Safety-critical applications + + Available on: + - ARM Cortex-M0+/M3/M4/M7/M23/M33/M85 (with MPU option) + - ARM Cortex-R series + + Note: Less flexible than MMU but lower overhead. Suitable for microcontrollers + without MMU. Enable RT_USING_HW_STACK_GUARD for automatic stack protection. config ARCH_ARM bool + help + Select ARM architecture family support. + + ARM is a widely-used RISC architecture family for embedded systems and mobile devices. + This is automatically selected when choosing a specific ARM CPU variant. + + Supported ARM variants in RT-Thread: + - ARM9/ARM11: Legacy 32-bit ARM cores + - Cortex-M: Microcontroller profile (M0/M0+/M3/M4/M7/M23/M33/M85) + - Cortex-R: Real-time profile (R4/R52) + - Cortex-A: Application profile (A5/A7/A8/A9/A55) + - ARMv8: 64-bit architecture (Cortex-A53/A57/A72/A73) + + No direct configuration needed - select specific CPU type instead. config ARCH_ARM_CORTEX_M bool select ARCH_ARM + help + ARM Cortex-M microcontroller profile. + + Cortex-M is ARM's microcontroller-optimized architecture designed for low-power, + cost-sensitive embedded applications with deterministic interrupt handling. + + Features: + - Nested Vectored Interrupt Controller (NVIC) + - Low interrupt latency (typically 12-15 cycles) + - Thumb-2 instruction set for code density + - Optional MPU for memory protection + - Optional FPU (M4F/M7F variants) + + Variants: M0/M0+/M3/M4/M7/M23/M33/M85 + + Automatically selected when choosing specific Cortex-M CPU variant. config ARCH_ARM_CORTEX_R bool select ARCH_ARM + help + ARM Cortex-R real-time profile. + + Cortex-R is designed for high-performance real-time applications requiring + deterministic behavior and fault tolerance. + + Features: + - Tightly-coupled memory (TCM) for deterministic access + - Error detection and correction (ECC) + - Dual-core lockstep for safety-critical applications + - Low and deterministic interrupt latency + - Optional MPU or MMU + + Common applications: + - Automotive (ADAS, engine control) + - Industrial control systems + - Medical devices + - Hard real-time systems + + Variants: R4/R5/R52 + Automatically selected when choosing specific Cortex-R CPU variant. config ARCH_ARM_CORTEX_FPU bool + help + Enable Floating Point Unit (FPU) support for ARM Cortex processors. + + When enabled, RT-Thread will: + - Save/restore FPU registers during context switch + - Enable FPU coprocessor access + - Support hardware floating-point operations + + FPU variants: + - Cortex-M4F/M7F: Single-precision FPv4-SP + - Cortex-M7: Optional double-precision FPv5 + - Cortex-A: VFPv3/VFPv4/NEON + + Benefits: 10-100x performance improvement for floating-point math + Cost: Increased context switch time, larger stack frames + + Enable if your application requires: + - DSP operations + - Audio/video processing + - Scientific computations + - Graphics operations + + Note: Hardware must have FPU. Check your MCU datasheet. config ARCH_ARM_CORTEX_SECURE bool + help + Enable ARM TrustZone security extension support. + + TrustZone provides hardware-based isolation between secure and non-secure worlds, + enabling trusted execution environments (TEE). + + Features: + - Secure and non-secure memory regions + - Secure and non-secure peripheral access + - Secure state transitions + - Protection of cryptographic keys and sensitive data + + Available on: + - Cortex-M23/M33/M35P/M55/M85 (ARMv8-M) + - Cortex-A with Security Extensions + + Use cases: + - Secure boot + - Cryptographic operations + - Key storage + - Secure firmware updates + - Payment and DRM systems + + Note: Requires secure firmware and proper secure/non-secure memory partitioning. config ARCH_ARM_CORTEX_M0 bool select ARCH_ARM_CORTEX_M + help + ARM Cortex-M0 ultra-low-power microcontroller core. + + Smallest and most energy-efficient ARM processor, ideal for simple control applications. + + Features: + - ARMv6-M architecture + - 32-bit processor with Thumb instruction set (subset) + - Minimal interrupt latency + - No MPU, no FPU, no cache + - Very low gate count and power consumption + + Performance: ~0.9 DMIPS/MHz + Typical applications: Sensors, simple controllers, battery-powered devices + + Choose this for your BSP if using Cortex-M0 based MCU. config ARCH_ARM_CORTEX_M3 bool select ARCH_ARM_CORTEX_M select RT_USING_CPU_FFS select RT_USING_HW_ATOMIC + help + ARM Cortex-M3 mainstream microcontroller core. + + Balanced processor for general-purpose embedded applications with good performance + and energy efficiency. + + Features: + - ARMv7-M architecture + - Thumb-2 instruction set (full) + - Hardware divide instructions + - Optional MPU (8 regions) + - Atomic operations (LDREX/STREX) + - No FPU, no cache + + Performance: ~1.25 DMIPS/MHz + + Common use cases: + - Industrial control + - Consumer electronics + - Motor control + - IoT devices + + Examples: STM32F1xx, LPC17xx, EFM32 + Choose this for your BSP if using Cortex-M3 based MCU. config ARCH_ARM_MPU bool depends on ARCH_ARM select ARCH_MM_MPU + help + Enable Memory Protection Unit for ARM Cortex-M/R processors. + + Select this to enable MPU support on compatible ARM cores. The MPU provides + hardware-based memory protection with configurable regions. + + When enabled, you can: + - Protect thread stacks from overflow + - Restrict access to peripheral registers + - Enforce execute-never (XN) permissions + - Separate privileged and unprivileged memory + + Configuration: + - Number of regions: Typically 8 (Cortex-M3/M4) or 16 (Cortex-M7/M33) + - Region size: Must be power of 2, minimum 32 bytes (Cortex-M3/M4) or 256 bytes (ARMv8-M) + - Permissions: Read, write, execute, privileged/unprivileged + + Enable this along with RT_USING_HW_STACK_GUARD for automatic stack protection. + See components/mprotect/Kconfig for detailed MPU configuration. config ARCH_ARM_CORTEX_M4 bool select ARCH_ARM_CORTEX_M select RT_USING_CPU_FFS select RT_USING_HW_ATOMIC + help + ARM Cortex-M4 DSP-oriented microcontroller core. + + Enhanced version of M3 with DSP extensions and optional FPU, designed for + digital signal processing and motor control applications. + + Features: + - ARMv7E-M architecture + - DSP instructions (SIMD, saturating arithmetic, MAC) + - Optional single-precision FPU (FPv4-SP) + - Optional MPU (8 regions) + - Hardware divide and atomic operations + - No cache + + Performance: ~1.25 DMIPS/MHz (CPU), 10x faster for DSP operations with FPU + + Ideal for: + - Audio processing + - Motor control (FOC algorithms) + - Sensor fusion + - Real-time control loops + + Examples: STM32F4xx, K64F, nRF52, TM4C + Choose this for your BSP if using Cortex-M4 or M4F based MCU. config ARCH_ARM_CORTEX_M7 bool @@ -78,38 +400,223 @@ config ARCH_ARM_CORTEX_M7 select RT_USING_CPU_FFS select RT_USING_CACHE select RT_USING_HW_ATOMIC + help + ARM Cortex-M7 high-performance microcontroller core. + + Most powerful Cortex-M processor with superscalar architecture, cache, and + advanced features for demanding embedded applications. + + Features: + - ARMv7E-M architecture with 6-stage superscalar pipeline + - L1 instruction and data cache (configurable 0-64KB each) + - Optional single/double-precision FPU (FPv5) + - Tightly-coupled memory (TCM) for deterministic access + - Optional MPU (8 or 16 regions) + - DSP instructions and atomic operations + + Performance: ~2.14 DMIPS/MHz (up to 600MHz), 5 CoreMark/MHz + + Critical for cache management: + - Must flush cache before DMA reads from memory + - Must invalidate cache after DMA writes to memory + - Cache coherency APIs automatically enabled + + Ideal for: + - High-performance embedded systems + - Vision and image processing + - Advanced motor control + - Real-time communication protocols + + Examples: STM32F7xx/H7xx, i.MX RT, SAM V71 + Choose this for your BSP if using Cortex-M7 based MCU. config ARCH_ARM_CORTEX_M85 bool select ARCH_ARM_CORTEX_M select RT_USING_CPU_FFS select RT_USING_HW_ATOMIC + help + ARM Cortex-M85 next-generation high-performance microcontroller core. + + Latest and most powerful Cortex-M processor with AI/ML acceleration and + advanced security features (ARMv8.1-M architecture). + + Features: + - ARMv8.1-M architecture with Helium (M-Profile Vector Extension) + - TrustZone security + - L1 cache (optional) + - Optional single/double-precision FPU + - Optional MPU (8 or 16 regions) + - Pointer authentication and branch target identification + - DSP and atomic operations + + Performance: Up to 6.2 CoreMark/MHz + + Helium benefits: + - 5-15x performance for ML inference + - Enhanced DSP for signal processing + - Vector operations for parallel data processing + + Ideal for: + - Edge AI/ML applications + - Advanced image/audio processing + - Security-critical applications + - Next-generation IoT devices + + Examples: Future MCUs with Cortex-M85 + Choose this for your BSP if using Cortex-M85 based MCU. config ARCH_ARM_CORTEX_M23 bool select ARCH_ARM_CORTEX_M select RT_USING_HW_ATOMIC + help + ARM Cortex-M23 ultra-low-power core with TrustZone. + + Energy-efficient processor with security features, successor to Cortex-M0+. + + Features: + - ARMv8-M Baseline architecture + - TrustZone security extension + - Optional MPU (8 or 16 regions) + - Atomic operations (LDREX/STREX) + - Low power consumption + - No FPU, no cache + + Performance: ~1.0 DMIPS/MHz + + Key advantage: Hardware security with minimal area/power overhead + + Ideal for: + - Secure IoT devices + - Battery-powered secure sensors + - Payment terminals + - Smart cards + + Examples: Future secure IoT MCUs + Choose this for your BSP if using Cortex-M23 based MCU. config ARCH_ARM_CORTEX_M33 bool select ARCH_ARM_CORTEX_M select RT_USING_CPU_FFS select RT_USING_HW_ATOMIC + help + ARM Cortex-M33 mainstream core with TrustZone. + + Balanced processor combining Cortex-M4 performance with TrustZone security, + ideal for secure IoT and connected devices. + + Features: + - ARMv8-M Mainline architecture + - TrustZone security extension + - Optional single-precision FPU (FPv5) + - Optional MPU (8 or 16 regions) + - DSP instructions + - Atomic operations + - Optional cache (Cortex-M33 derivatives) + + Performance: ~1.5 DMIPS/MHz + + Security features: + - Secure/non-secure memory partitioning + - Secure function calls + - Stack limit checking + - Co-processor isolation + + Ideal for: + - Secure IoT gateways + - Industrial automation with security + - Connected consumer devices + - Secure bootloaders + + Examples: nRF91, LPC55xx, STM32L5xx + Choose this for your BSP if using Cortex-M33 based MCU. config ARCH_ARM_CORTEX_R bool select ARCH_ARM select RT_USING_HW_ATOMIC + help + ARM Cortex-R real-time processor family. + + High-performance real-time processors with deterministic behavior for + safety-critical and real-time systems. + + Common features across Cortex-R family: + - Low and deterministic interrupt latency + - Tightly-coupled memory (TCM) + - Error correction code (ECC) + - Optional MPU or MMU + - VFP floating-point + + Automatically selected when choosing specific Cortex-R variant (R4/R52). + See individual Cortex-R variant options for detailed specifications. config ARCH_ARM_CORTEX_R52 bool select ARCH_ARM_CORTEX_R + help + ARM Cortex-R52 safety-critical real-time core. + + Latest Cortex-R processor designed for ASIL-D automotive and IEC 61508 SIL-3 + industrial safety applications. + + Features: + - ARMv8-R architecture (32-bit) + - Dual-core lockstep for fault detection + - ECC on caches and TCM + - Optional MPU or MMU + - Virtualization extensions + - Single/double precision FPU + - NEON SIMD + + Performance: Up to 1.6 DMIPS/MHz per core + + Safety features: + - Redundant execution for error detection + - Memory protection and ECC + - Built-in self-test (BIST) + + Ideal for: + - Automotive ADAS and autonomous driving + - Industrial safety controllers (SIL-3) + - Medical devices + - Aerospace applications + + Choose this for your BSP if using Cortex-R52 based SoC. config ARCH_ARM_MMU bool select RT_USING_CACHE select ARCH_MM_MMU depends on ARCH_ARM + help + Enable MMU support for ARM Cortex-A processors. + + Provides full virtual memory management with page-based address translation. + Automatically selected by Cortex-A variants. + + Features: + - 4KB/16KB/64KB page sizes + - Two-level (LPAE: three-level) page tables + - Virtual memory for multiple processes + - Memory attributes (cacheable, bufferable, shareable) + - Access permissions (privileged, user, read-only, execute-never) + + Enables: + - RT-Smart user-space applications + - Memory protection between processes + - Demand paging and swapping + - Memory-mapped files (mmap) + - Shared memory between processes + + Performance impact: + - TLB (Translation Lookaside Buffer) misses add latency + - Page table walks on TLB miss + - Requires proper cache and TLB management + + Note: Automatically enabled for Cortex-A. Required for RT-Smart mode. if RT_USING_SMART config KERNEL_VADDR_START @@ -119,21 +626,89 @@ if RT_USING_SMART default 0xffffffc000000000 if ARCH_RISCV && ARCH_REMAP_KERNEL default 0x80000000 if ARCH_RISCV depends on ARCH_MM_MMU + help + Starting virtual address for kernel space in RT-Smart mode. + + This defines where the kernel is mapped in the virtual address space. + The kernel typically resides in the upper half of the address space to + separate it from user-space applications. + + Default values: + - ARMv8 (64-bit): 0xffff000000000000 (upper 256TB) + - ARM (32-bit): 0xc0000000 (upper 1GB, Linux-compatible) + - RISC-V with remap: 0xffffffc000000000 + - RISC-V standard: 0x80000000 (2GB mark) + + User-space applications use addresses below this value. + + Note: Must be aligned to architecture's virtual memory requirements. + Changing this requires recompiling all kernel and user-space code. config RT_IOREMAP_LATE bool "Support to create IO mapping in the kernel address space after system initlalization." default n depends on ARCH_ARM_CORTEX_A depends on ARCH_MM_MMU + help + Enable dynamic I/O memory remapping after system initialization. + + When enabled, allows mapping device I/O memory into kernel virtual address + space at runtime using rt_ioremap(). This is useful for: + - Hot-pluggable devices + - Runtime device discovery (device tree) + - Drivers loaded after boot + - Flexible peripheral address mapping + + Without this option, all I/O mappings must be established during early boot. + + Impact: + - Slightly increased memory overhead for dynamic mapping tables + - Additional TLB entries for I/O regions + + Enable if you need runtime flexibility for device driver loading or + working with device tree-based systems. endif config ARCH_ARM_ARM9 bool select ARCH_ARM + help + ARM9 processor family (legacy ARMv4T/ARMv5 architecture). + + Classic ARM architecture used in many embedded systems from the 2000s. + Now largely superseded by Cortex-A for application processors. + + Features: + - 5-stage pipeline + - MMU for virtual memory + - Separate instruction and data caches + - ARM and Thumb instruction sets + + Performance: ~1.1 DMIPS/MHz + + Examples: ARM926EJ-S (NXP i.MX, Atmel AT91SAM9) + Choose this if your BSP uses ARM9-based SoC. config ARCH_ARM_ARM11 bool select ARCH_ARM + help + ARM11 processor family (ARMv6 architecture). + + Enhanced ARM architecture with improved performance and SIMD extensions. + Bridges the gap between ARM9 and Cortex-A. + + Features: + - 8-stage pipeline + - MMU with improved TLB + - SIMD instructions + - Unaligned access support + - Hardware divide (some variants) + + Performance: ~1.25 DMIPS/MHz + + Examples: ARM1176JZF-S (Raspberry Pi 1, BCM2835) + Choose this if your BSP uses ARM11-based SoC. config ARCH_ARM_CORTEX_A bool @@ -141,54 +716,279 @@ config ARCH_ARM_CORTEX_A select ARCH_ARM_MMU select RT_USING_CPU_FFS select RT_USING_HW_ATOMIC + help + ARM Cortex-A application processor family. + + High-performance processors designed for complex operating systems and + rich applications (Linux, Android, RT-Smart). + + Common features: + - MMU for virtual memory (required) + - Multi-level caches (L1/L2/L3) + - VFP floating-point and NEON SIMD + - TrustZone security extensions + - Multi-core configurations (SMP) + - GIC (Generic Interrupt Controller) + + Typical applications: + - Industrial HMI and gateways + - Multimedia devices + - Automotive infotainment + - Edge computing + - RT-Smart mixed-criticality systems + + Variants: A5/A7/A8/A9/A15/A17/A35/A53/A55/A57/A72/A73 + + Automatically selected when choosing specific Cortex-A variant. if ARCH_ARM_CORTEX_A config RT_SMP_AUTO_BOOT bool default n + help + Automatically boot secondary CPU cores at system startup. + + When enabled, RT-Thread will start all available CPU cores during + initialization for symmetric multiprocessing (SMP). + + If disabled, secondary cores remain in reset/low-power state until + explicitly started by application code. + + Enable for: + - Multi-core load distribution + - Parallel task execution + - Maximum system performance + + Disable for: + - Power-sensitive applications + - Asymmetric multiprocessing (AMP) + - Single-core debugging + + Note: Requires RT_USING_SMP to be enabled. config RT_USING_GIC_V2 bool default n + help + Use ARM Generic Interrupt Controller version 2 (GICv2). + + GICv2 is the interrupt controller for Cortex-A processors, providing: + - Up to 1020 interrupt sources + - Interrupt priority and masking + - CPU interface for each core + - Distributor for routing interrupts to cores + - Software-generated interrupts (SGI) for inter-core communication + + Used in: + - Cortex-A5/A7/A8/A9/A15/A17 + - Single and multi-core SMP systems + + Mutually exclusive with GICv3. Select based on your SoC hardware. config RT_USING_GIC_V3 bool default n + help + Use ARM Generic Interrupt Controller version 3/4 (GICv3/GICv4). + + GICv3 is the enhanced interrupt controller for newer ARM processors: + - Improved scalability (supports more cores) + - System register access (no memory-mapped CPU interface) + - Locality-specific peripheral interrupts (LPI) + - Message-based interrupts + - GICv4: Direct injection of virtual interrupts + + Used in: + - Cortex-A55/A57/A72/A73 and newer + - ARMv8 (AArch64) systems + - Large SMP systems (>8 cores) + + Mutually exclusive with GICv2. Select based on your SoC hardware. config RT_NO_USING_GIC bool default y if !RT_USING_GIC_V2 && !RT_USING_GIC_V3 + help + No GIC interrupt controller in use. + + Automatically set when neither GICv2 nor GICv3 is selected. + This may indicate: + - Custom interrupt controller + - Legacy interrupt controller + - Configuration error + + Most Cortex-A systems require either GICv2 or GICv3. endif config ARCH_ARM_CORTEX_A5 bool select ARCH_ARM_CORTEX_A + help + ARM Cortex-A5 energy-efficient application processor. + + Entry-level Cortex-A processor offering lower cost and power than A9 + while maintaining application-class capabilities. + + Features: + - ARMv7-A architecture + - 1-4 cores, in-order execution + - Optional NEON SIMD and VFPv4 + - TrustZone security + - L1 cache, optional L2 + - GICv2 + + Performance: ~1.57 DMIPS/MHz + + Ideal for: Cost-sensitive IoT gateways, industrial HMI + Examples: Vybrid VF6xx (Cortex-A5 + Cortex-M4) + Choose this if your BSP uses Cortex-A5 based SoC. config ARCH_ARM_CORTEX_A7 bool select ARCH_ARM_CORTEX_A + help + ARM Cortex-A7 power-efficient application processor. + + Most power-efficient ARMv7-A processor, often paired with A15 in big.LITTLE + configurations or used standalone for cost-effective systems. + + Features: + - ARMv7-A architecture with hardware virtualization + - 1-4 cores, in-order execution + - VFPv4 and NEON standard + - TrustZone security + - L1 and L2 cache + - GICv2 + + Performance: ~1.9 DMIPS/MHz + Power: 40% lower than Cortex-A9 at same performance + + Ideal for: IoT gateways, set-top boxes, entry-level tablets + Examples: BCM2836 (Raspberry Pi 2), i.MX6UL, Allwinner A33 + Choose this if your BSP uses Cortex-A7 based SoC. config ARCH_ARM_CORTEX_A8 bool select ARCH_ARM_CORTEX_A + help + ARM Cortex-A8 general-purpose application processor. + + First Cortex-A processor, designed for multimedia and mobile applications. + + Features: + - ARMv7-A architecture + - Single core, 13-stage superscalar pipeline + - VFPv3 and NEON + - TrustZone security + - L1 and L2 cache + + Performance: ~2.0 DMIPS/MHz + + Ideal for: Industrial automation, multimedia systems + Examples: TI AM335x (BeagleBone), OMAP3 + Choose this if your BSP uses Cortex-A8 based SoC. config ARCH_ARM_CORTEX_A9 bool select ARCH_ARM_CORTEX_A + help + ARM Cortex-A9 high-performance application processor. + + Popular multi-core processor balancing performance and power efficiency. + + Features: + - ARMv7-A architecture + - 1-4 cores, out-of-order execution + - VFPv3 and NEON + - TrustZone security + - L1 cache per core, shared L2 + - GICv2 + + Performance: ~2.5 DMIPS/MHz per core + + Ideal for: Industrial gateways, automotive, network equipment + Examples: Zynq-7000 (A9 + FPGA), i.MX6, NVIDIA Tegra 2/3 + Choose this if your BSP uses Cortex-A9 based SoC. config ARCH_ARM_CORTEX_A55 bool select ARCH_ARM_CORTEX_A + help + ARM Cortex-A55 ultra-efficient 64-bit processor (ARMv8.2-A). + + DynamIQ-enabled processor for modern SMP and big.LITTLE configurations, + designed for power efficiency and AI/ML workloads. + + Features: + - ARMv8.2-A architecture (64-bit) + - 1-8 cores in DynamIQ cluster + - Dot product instructions for ML + - TrustZone and pointer authentication + - L1 and L2 cache, optional L3 + - GICv3 + + Performance: ~1.8 DMIPS/MHz (better IPC than A53) + + Ideal for: Mobile, automotive ADAS, edge AI + Examples: MediaTek Helio, Qualcomm Snapdragon 7xx/6xx + Choose this if your BSP uses Cortex-A55 based SoC. config ARCH_ARM_SECURE_MODE bool "Running in secure mode [ARM Cortex-A]" default n depends on ARCH_ARM_CORTEX_A + help + Run RT-Thread in ARM secure mode (TrustZone secure world). + + TrustZone divides the system into two execution environments: + - Secure world: Access to all resources, runs trusted code + - Non-secure world: Restricted access, runs normal applications + + Enable this when: + - RT-Thread acts as secure monitor or trusted OS + - Implementing secure boot chain + - Running in EL3 (ARMv8) or secure state (ARMv7) + - Providing secure services to non-secure OS + + Disable when: + - Running as normal OS in non-secure world + - No TrustZone partitioning needed + - Booting directly without secure monitor + + Impact: + - Changes memory access permissions + - Affects SCR (Secure Configuration Register) settings + - Influences interrupt routing + + Note: Most applications run in non-secure mode. Only enable if you're + implementing secure firmware or trusted execution environment. config RT_BACKTRACE_FUNCTION_NAME bool "To show function name when backtrace." default n depends on ARCH_ARM_CORTEX_A + help + Display function names in backtrace/call stack dumps. + + When enabled, exception handlers and assertion failures will show + symbolic function names in addition to addresses, making debugging easier. + + Requires: + - Debug symbols in the binary + - Symbol table in memory or accessible + - Additional processing during backtrace + + Benefits: + - Easier identification of crash location + - Better error reports + - Faster debugging + + Costs: + - Slightly larger binary (symbol information) + - Increased backtrace processing time + + Recommended for development builds. May be disabled for production + to save space and improve backtrace speed. config ARCH_ARMV8 bool @@ -197,69 +997,351 @@ config ARCH_ARMV8 select RT_USING_CPU_FFS select ARCH_USING_ASID select ARCH_USING_IRQ_CTX_LIST + help + ARM 64-bit architecture (ARMv8-A / AArch64). + + Modern 64-bit ARM architecture for high-performance application processors. + Represents major architectural evolution from ARMv7 with enhanced features. + + Key features: + - 64-bit addressing and registers (can also run 32-bit code in AArch32 mode) + - Exception levels (EL0-EL3) for privilege separation + - Enhanced virtual memory (48-bit addressing, up to 256TB) + - ASID (Address Space ID) for efficient context switching + - Improved SIMD (Advanced SIMD / NEON) + - Hardware virtualization support + - Scalable Vector Extension (SVE) on some variants + + Advantages over ARMv7: + - More registers (31 general-purpose 64-bit registers) + - Larger addressable memory (>4GB) + - Better performance and efficiency + - Enhanced security features + + Processors: Cortex-A53/A57/A72/A73/A75/A76, Neoverse, Apple M-series + + Automatically selected by AArch64 BSP configurations. + Required for RT-Smart on 64-bit ARM platforms. config ARCH_MIPS bool + help + MIPS (Microprocessor without Interlocked Pipeline Stages) architecture. + + Classic RISC architecture used in embedded systems, networking equipment, + and consumer electronics. + + Features: + - Simple load/store RISC design + - Configurable endianness (big or little) + - Optional FPU and DSP extensions + - Hardware multithreading (MIPS MT) + + Common applications: + - Network routers and switches + - Set-top boxes + - Gaming consoles + - Embedded Linux systems + + Variants: MIPS32, MIPS64, microMIPS + Choose this if your BSP uses MIPS-based SoC. config ARCH_MIPS64 bool select ARCH_CPU_64BIT + help + MIPS 64-bit architecture. + + 64-bit extension of MIPS architecture providing: + - 64-bit addressing and registers + - Backward compatible with MIPS32 code + - Enhanced performance for 64-bit operations + - Access to larger memory spaces + + Applications: High-end networking equipment, servers + Examples: Cavium OCTEON, Loongson processors + Choose this if your BSP uses MIPS64-based SoC. config ARCH_MIPS_XBURST bool select ARCH_MIPS + help + Ingenic XBurst MIPS-based processor family. + + Customized MIPS architecture optimized for mobile and multimedia applications + by Ingenic Semiconductor. + + Features: + - MIPS32-compatible core with enhancements + - Low power consumption + - Integrated multimedia accelerators + + Common applications: Handheld devices, e-readers, IoT + Examples: JZ47xx series SoCs + Choose this if your BSP uses Ingenic XBurst processor. config ARCH_ANDES bool + help + Andes RISC-V based architecture. + + Custom RISC-V implementation by Andes Technology with proprietary extensions + for enhanced performance and features. + + Features: + - RISC-V ISA with Andes-specific extensions + - CoDense (16-bit instruction compression) + - StackSafe for stack protection + - PowerBrake for power management + + Applications: AIoT, storage controllers, automotive + Choose this if your BSP uses Andes processor core. config ARCH_CSKY bool + help + C-SKY CPU architecture. + + Chinese-designed processor architecture (now part of Alibaba's T-Head). + + Features: + - 16/32-bit RISC architecture + - Low power and small code size + - DSP extensions + + Applications: IoT devices, consumer electronics + Choose this if your BSP uses C-SKY based processor. config ARCH_POWERPC bool + help + PowerPC architecture. + + High-performance RISC architecture traditionally used in embedded and + server applications. + + Features: + - Big-endian (configurable to little-endian on some models) + - AltiVec SIMD on some variants + - Strong memory consistency model + + Applications: Networking equipment, aerospace, industrial control + Examples: MPC5xxx, QorIQ series + Choose this if your BSP uses PowerPC processor. config ARCH_RISCV bool + help + RISC-V open standard instruction set architecture. + + Modern, modular, open-source ISA designed for efficiency and extensibility. + Gaining rapid adoption in embedded systems, IoT, and AI/ML applications. + + Key advantages: + - Open standard (no licensing fees) + - Modular design (choose only needed extensions) + - Simple and clean architecture + - Growing ecosystem and vendor support + + Base ISAs: RV32I (32-bit), RV64I (64-bit) + Common extensions: + - M: Integer multiplication/division + - A: Atomic instructions + - F: Single-precision floating-point + - D: Double-precision floating-point + - C: Compressed 16-bit instructions + - V: Vector operations + + Examples: SiFive, Allwinner D1, ESP32-C3/C6, GigaDevice GD32V + + Automatically selected when choosing RV32 or RV64 variant. config ARCH_RISCV_FPU bool + help + RISC-V floating-point unit support. + + Enable hardware floating-point operations using RISC-V F and/or D extensions. + Automatically selected by ARCH_RISCV_FPU_S or ARCH_RISCV_FPU_D. + + When enabled: + - FPU registers (f0-f31) saved/restored during context switch + - Hardware FP instructions used by compiler + - Significant performance improvement for floating-point math + + Note: CPU must have F and/or D extension support. config ARCH_RISCV_VECTOR bool + help + RISC-V Vector Extension (RVV) support. + + Enable RISC-V Vector Extension for SIMD operations, ideal for data-parallel + workloads like DSP, image processing, and AI/ML inference. + + Features: + - Vector registers with configurable length (VLEN) + - Vector arithmetic, logic, and memory operations + - Predication and masking + - Auto-vectorization by compiler + + Benefits: + - 4-10x performance for vectorizable workloads + - Efficient memory access patterns + - Scalable across different vector lengths + + Applications: Signal processing, multimedia, ML inference + + Note: Requires CPU with V extension (ratified v1.0). + Select VLEN based on your hardware specification. if ARCH_RISCV_VECTOR choice ARCH_VECTOR_VLEN prompt "RISCV Vector Vlen" default ARCH_VECTOR_VLEN_128 + help + Select the vector register length (VLEN) for RISC-V Vector Extension. + + VLEN defines the width of vector registers in bits. This must match + your hardware's vector implementation. + + Common VLEN values: + - 128-bit: Entry-level vector implementations, good balance + - 256-bit: Higher throughput, more aggressive vectorization + + Larger VLEN: + + More data processed per instruction + + Better performance for vector operations + - Larger context switch overhead + - More silicon area required + + Check your CPU documentation for supported VLEN. config ARCH_VECTOR_VLEN_128 bool "128" + help + 128-bit vector register length. + + Standard choice for embedded RISC-V processors with vector support. + Provides good performance/area balance. + + Choose this for most RISC-V vector implementations. + config ARCH_VECTOR_VLEN_256 bool "256" + help + 256-bit vector register length. + + Wider vector registers for higher throughput in data-parallel workloads. + Requires more silicon area and increases context switch time. + + Choose this only if your CPU supports 256-bit VLEN. endchoice endif config ARCH_RISCV_FPU_S select ARCH_RISCV_FPU bool + help + RISC-V single-precision floating-point (F extension). + + Enable support for 32-bit (float) floating-point operations in hardware. + + Features: + - 32 single-precision FP registers (f0-f31) + - IEEE 754 single-precision arithmetic + - FP load/store, arithmetic, conversion instructions + + Sufficient for many embedded applications requiring FP without the + overhead of double-precision. + + Automatically selected by BSP when CPU has F extension. config ARCH_RISCV_FPU_D select ARCH_RISCV_FPU bool + help + RISC-V double-precision floating-point (D extension). + + Enable support for 64-bit (double) floating-point operations in hardware. + Includes F extension functionality. + + Features: + - 32 double-precision FP registers (f0-f31, 64-bit wide) + - IEEE 754 double-precision arithmetic + - Both single and double-precision operations + + Required for: + - High-precision scientific computations + - Financial calculations + - Applications requiring >7 significant digits + + Note: D extension requires F extension as prerequisite. + Automatically selected by BSP when CPU has D extension. config ARCH_RISCV32 select ARCH_RISCV bool + help + RISC-V 32-bit architecture (RV32). + + 32-bit RISC-V implementation optimized for resource-constrained + embedded systems and microcontrollers. + + Features: + - 32-bit addressing (4GB address space) + - 32 general-purpose 32-bit registers + - Compact code size with C extension + - Lower power consumption + + Ideal for: + - Microcontrollers and IoT devices + - Cost-sensitive applications + - Battery-powered systems + + Common variants: RV32IMAC, RV32IMAFC + Examples: ESP32-C3, GigaDevice GD32VF103, Nuclei Bumblebee + + Choose this if your BSP uses 32-bit RISC-V processor. config ARCH_RISCV64 select ARCH_RISCV select ARCH_CPU_64BIT bool + help + RISC-V 64-bit architecture (RV64). + + 64-bit RISC-V implementation for high-performance embedded systems + and application processors. + + Features: + - 64-bit addressing (16 exabyte address space) + - 32 general-purpose 64-bit registers + - Backward compatible with RV32 software (with proper toolchain) + - Better performance for 64-bit arithmetic + + Ideal for: + - Application processors + - RT-Smart user-space applications + - Systems requiring >4GB memory + - High-performance embedded Linux + + Common variants: RV64IMAC, RV64GC + Examples: SiFive U74, Allwinner D1 (C906), Kendryte K210 + + Choose this if your BSP uses 64-bit RISC-V processor. if ARCH_RISCV64 config ARCH_USING_NEW_CTX_SWITCH bool default y + help + Use optimized context switch implementation for RISC-V 64-bit. + + Enables improved context switching with better performance and + smaller code size. This is the recommended implementation for RV64. + + Automatically enabled for RISC-V 64-bit. No manual configuration needed. config ARCH_USING_RISCV_COMMON64 bool @@ -267,43 +1349,199 @@ if ARCH_RISCV64 select RT_USING_CPUTIME select ARCH_USING_NEW_CTX_SWITCH help - Using the common64 implementation under ./libcpu/risc-v + Use common 64-bit RISC-V implementation under ./libcpu/risc-v/common64. + + Provides unified, optimized implementation for 64-bit RISC-V cores: + - Standard context switch routines + - Exception and interrupt handling + - MMU/PMP management + - CPU time measurement + + Benefits: + - Code reuse across different RV64 cores + - Well-tested implementation + - Consistent behavior + + Enable this for standard RV64 cores (SiFive U74, T-Head C906, etc.) + unless you have specific custom requirements. endif config ARCH_REMAP_KERNEL bool depends on RT_USING_SMART help - Remapping kernel image to high virtual address region + Remap kernel image to high virtual address region. + + In RT-Smart mode, move kernel to upper virtual memory region to separate + it from user-space, similar to Linux kernel layout. + + Benefits: + - Clear separation between kernel and user address spaces + - User applications can use lower addresses (0x0 upward) + - Prevents accidental user access to kernel memory + - Compatible with standard executable loaders + + Memory layout with remapping: + - User space: 0x00000000 - KERNEL_VADDR_START + - Kernel space: KERNEL_VADDR_START - 0xFFFFFFFF... + + Required for: Full RT-Smart user-space isolation + Note: Increases boot time slightly due to remapping overhead. config ARCH_USING_ASID bool depends on RT_USING_SMART help - Using ASID support from architecture + Enable Address Space ID (ASID) support from architecture. + + ASID is a hardware feature that tags TLB (Translation Lookaside Buffer) + entries with process identifiers, avoiding TLB flushes on context switch. + + Benefits: + - Faster context switches between processes + - Better TLB utilization (multiple processes' translations cached) + - Reduced MMU overhead + + Without ASID: TLB must be flushed on every context switch (expensive) + With ASID: TLB entries for multiple processes coexist (efficient) + + Performance impact: Can reduce context switch time by 50-70% + + Automatically enabled for: + - ARMv8 (8-bit or 16-bit ASID) + - Some ARMv7-A implementations + - RISC-V with ASID support + + Note: Requires MMU with ASID support. Automatically selected by + compatible architectures. config ARCH_IA32 bool + help + Intel IA-32 (x86 32-bit) architecture. + + 32-bit x86 architecture for PC-compatible systems and embedded x86 platforms. + + Features: + - CISC architecture + - Segmented memory model (legacy) or flat model + - x87 FPU, MMX, SSE extensions + - Paging and segmentation + + Applications: Industrial PCs, legacy embedded systems, virtualization hosts + Examples: Intel Atom, AMD Geode + + Choose this if your BSP uses x86 32-bit processor. config ARCH_TIDSP bool + help + Texas Instruments DSP architecture family. + + Specialized processors for digital signal processing applications. + + Features: + - Optimized for real-time signal processing + - Harvard architecture (separate program/data memory) + - Hardware multipliers and MAC units + - Low-latency interrupt handling + + Applications: Motor control, audio processing, power electronics + + Automatically selected by specific TI DSP variant (e.g., C28x). config ARCH_TIDSP_C28X bool select ARCH_TIDSP select ARCH_CPU_STACK_GROWS_UPWARD + help + Texas Instruments C28x DSP architecture. + + Fixed-point DSP optimized for real-time control applications, + especially motor control and power conversion. + + Features: + - 32-bit fixed-point architecture + - Upward-growing stack (unusual characteristic) + - Single-cycle MAC operations + - Fast interrupt response (<50ns) + - Floating-point unit (C28x+FPU variants) + + Ideal for: + - Digital motor control (FOC, vector control) + - Power inverters and converters + - Solar inverters + - Industrial drives + + Examples: TMS320F28xxx series + + Note: Stack grows upward unlike most architectures. + Choose this if your BSP uses TI C28x DSP. config ARCH_HOST_SIMULATOR bool - -config ARCH_CPU_STACK_GROWS_UPWARD - bool - default n + help + Host machine simulator (running RT-Thread on development PC). + + Allows running RT-Thread as a user-space application on Linux, Windows, + or macOS for development, testing, and debugging without physical hardware. + + Features: + - Rapid prototyping and testing + - Debugger-friendly (use GDB, Visual Studio debugger) + - File system access to host files + - Network simulation + + Use cases: + - Algorithm development and testing + - Application logic verification + - CI/CD automated testing + - Learning RT-Thread without hardware + + Note: Timing behavior differs from real hardware. Not suitable for + real-time performance validation. + + Choose this for simulator-based BSP (e.g., qemu-vexpress-a9, simulator). config ARCH_USING_HW_THREAD_SELF bool default n + help + Use hardware register to identify current thread (thread self-identification). + + Some architectures provide dedicated registers or instructions to identify + the currently executing thread without memory access. + + Benefits: + - Faster rt_thread_self() operation (single register read) + - Reduced memory bandwidth + - Better performance in multi-core systems + + Examples: + - ARM: TPIDRURO/TPIDR_EL0 register + - x86: FS/GS segment registers + - RISC-V: Some implementations use tp register + + Automatically enabled by architectures supporting this feature. + No manual configuration needed. config ARCH_USING_IRQ_CTX_LIST bool default n + help + Use interrupt context list for nested interrupt handling. + + Maintains a list of interrupt contexts for proper nested interrupt + management, especially important for complex interrupt scenarios. + + Benefits: + - Correct handling of deeply nested interrupts + - Proper context tracking in multi-level interrupt systems + - Better debugging of interrupt-related issues + + Overhead: + - Slight increase in interrupt entry/exit time + - Small memory overhead for context list + + Automatically enabled by architectures requiring it (e.g., ARMv8). + No manual configuration needed. diff --git a/libcpu/aarch64/Kconfig b/libcpu/aarch64/Kconfig index 5429751d3a1..222052a21ff 100644 --- a/libcpu/aarch64/Kconfig +++ b/libcpu/aarch64/Kconfig @@ -2,24 +2,162 @@ menu "AArch64 Architecture Configuration" config ARCH_TEXT_OFFSET hex "Text offset" default 0x200000 + help + Offset of kernel text section from start of RAM. + + Defines where the kernel code (.text section) is located relative to + the beginning of physical RAM. This space before the kernel is typically + reserved for: + - Bootloader and device tree blob (DTB) + - Initial page tables + - Boot-time data structures + + Default 0x200000 (2MB): + - Provides 2MB for bootloader and DTB + - Aligns with common ARM64 configurations + - Compatible with 2MB page granularity + + Only change if you have specific bootloader requirements or memory layout. + config ARCH_RAM_OFFSET hex "RAM offset" default 0 + help + Physical address offset of the RAM start. + + Defines the starting physical address of system RAM. On many systems, + RAM doesn't start at address 0x0. + + Common values: + - 0x00000000: RAM starts at address 0 (some SoCs) + - 0x40000000: Common for many ARM SoCs + - 0x80000000: Some development boards + + This must match your hardware memory map. Check your SoC datasheet + or bootloader configuration. + + Default 0 means RAM starts at physical address 0x0. + config ARCH_SECONDARY_CPU_STACK_SIZE int "Secondary CPU stack size" default 4096 + help + Stack size for secondary CPU cores in multi-core (SMP) systems. + + Each secondary CPU core (CPU1, CPU2, etc.) needs its own stack for + initialization and exception handling before the scheduler starts. + + Default 4096 bytes (4KB): + - Sufficient for standard initialization + - Handles nested exceptions during boot + + Increase if: + - Experiencing secondary CPU boot failures + - Complex initialization routines + - Deep call chains during CPU startup + + Total memory used: (Number of secondary cores) × stack size + + Note: After scheduler starts, each thread has its own stack. + config ARCH_HAVE_EFFICIENT_UNALIGNED_ACCESS bool default y + help + ARMv8 supports efficient unaligned memory access. + + ARMv8 architecture can access unaligned memory addresses (addresses not + aligned to word boundaries) without performance penalty or exceptions. + + Benefits: + - Simpler code (no manual alignment required) + - Network packet processing (headers often unaligned) + - Reduced padding in data structures + + This is automatically enabled for ARMv8 - no configuration needed. + + Note: Some embedded systems may disable this for deterministic timing + or to catch alignment bugs, but ARMv8 handles it efficiently in hardware. + config ARCH_USING_GENERIC_CPUID bool "Using generic cpuid implemenation" select ARCH_USING_HW_THREAD_SELF default y if RT_USING_OFW default n + help + Use generic CPU identification implementation for multi-core systems. + + Provides standardized method to identify which CPU core is currently + executing, essential for SMP (Symmetric Multi-Processing). + + When enabled: + - Reads MPIDR_EL1 register for CPU ID + - Maps hardware CPU IDs to logical CPU numbers + - Enables proper per-CPU data structures + + Required for: + - SMP systems with multiple cores + - Per-CPU statistics and profiling + - CPU affinity and core-specific operations + + Automatically enabled when using OpenFirmware/Device Tree (RT_USING_OFW). + + Enable if you have multi-core ARMv8 system. Disable for single-core + to save minimal overhead. + config ARCH_HEAP_SIZE hex "Size of system heap" default 0x4000000 + help + Size of system heap for dynamic memory allocation. + + Defines the amount of memory available for rt_malloc() and related + dynamic allocation functions. + + Default 0x4000000 (64MB): + - Suitable for application-class systems with RT-Smart + - Supports moderate number of dynamic allocations + + Adjust based on: + - Available RAM in your system + - Application memory requirements + - Static vs dynamic allocation strategy + + Smaller values for resource-constrained systems. + Larger values for systems with abundant RAM and heavy dynamic allocation. + + Note: Actual available memory depends on total RAM size. + + Example configurations: + - 128MB RAM system: 0x4000000 (64MB) or less + - 256MB RAM system: 0x8000000 (128MB) or more + - 1GB+ RAM system: 0x20000000 (512MB) or more + config ARCH_INIT_PAGE_SIZE hex "Size of init page region" default 0x200000 + help + Size of initial page table region for early boot. + + Reserves memory for page tables used during system initialization + before the full memory management is set up. + + Default 0x200000 (2MB): + - Sufficient for initial kernel mappings + - Covers typical early boot requirements + - Aligns with 2MB page granularity + + This memory is used for: + - Initial MMU page table entries + - Early kernel virtual memory mappings + - Temporary boot-time allocations + + Increase if: + - Experiencing boot failures related to page tables + - Large kernel image + - Extensive early I/O mappings + + Decrease for memory-constrained systems (minimum ~1MB). + + Note: After full MM initialization, regular page allocation takes over. endmenu From 0978768baeec1e455359fd267a2655694a7083b3 Mon Sep 17 00:00:00 2001 From: "copilot-swe-agent[bot]" <198982749+Copilot@users.noreply.github.com> Date: Mon, 17 Nov 2025 08:48:41 +0000 Subject: [PATCH 3/9] Enhance Kconfig help for finsh and dfs components Co-authored-by: Rbb666 <64397326+Rbb666@users.noreply.github.com> --- components/dfs/Kconfig | 287 ++++++++++++++++++++++++++++++++++++++- components/finsh/Kconfig | 233 ++++++++++++++++++++++++++++++- 2 files changed, 516 insertions(+), 4 deletions(-) diff --git a/components/dfs/Kconfig b/components/dfs/Kconfig index 23799d1b44e..bc92c698c9e 100644 --- a/components/dfs/Kconfig +++ b/components/dfs/Kconfig @@ -5,16 +5,72 @@ config RT_USING_DFS select RT_USING_MUTEX default y help - The device file system is a light weight virtual file system. + DFS (Device File System) is RT-Thread's lightweight virtual file system. + + Provides unified file system abstraction layer supporting: + - Multiple file system types (FAT, ROM-FS, RAM-FS, NFS, etc.) + - POSIX-like file operations (open, read, write, close) + - Device file access (/dev/uart1, /dev/spi0, etc.) + - Mount points for different file systems + - Working directory support + + Features: + - Small footprint (~5-10KB depending on configuration) + - POSIX API compatibility for easier porting + - Multiple file systems can coexist + - Thread-safe operations with mutex protection + + Typical use cases: + - File logging and data storage + - Configuration file management + - Device access abstraction + - Network file systems (NFS) + + Enable for applications requiring file system support. + Disable for simple applications to save ~10-15KB ROM. if RT_USING_DFS config DFS_USING_POSIX bool "Using posix-like functions, open/read/write/close" default y + help + Enable POSIX-compliant file I/O API functions. + + Provides standard POSIX file operations: + - open(), close(), read(), write() + - lseek(), stat(), fstat() + - opendir(), readdir(), closedir() + - mkdir(), rmdir(), unlink(), rename() + + Benefits: + - Easier code porting from Linux/POSIX systems + - Familiar API for developers + - Better compatibility with third-party libraries + + Required for most applications using file operations. + Disable only if using custom file I/O API. config DFS_USING_WORKDIR bool "Using working directory" default y + help + Enable working directory (current directory) support. + + Features: + - Each thread can have its own working directory + - chdir() to change current directory + - Relative paths resolved from working directory + - getcwd() to get current directory path + + Essential for: + - Shell commands (cd, pwd) + - Relative path operations + - Multi-threaded file access with different contexts + + Memory cost: ~256 bytes per thread for path storage + + Recommended to keep enabled for convenience. + Disable to save minimal RAM if only using absolute paths. if RT_USING_DFS_V1 config RT_USING_DFS_MNTTABLE @@ -33,36 +89,138 @@ endif config DFS_FD_MAX int "The maximal number of opened files" default 16 + help + Maximum number of file descriptors that can be opened simultaneously + across all threads in the system. + + Default: 16 + + Each open file descriptor uses ~40-60 bytes of RAM. + Total memory: DFS_FD_MAX × ~50 bytes + + Increase if: + - Application opens many files concurrently + - Multiple threads access files simultaneously + - Getting "too many open files" errors + + Decrease to save RAM on memory-constrained systems (minimum ~4). + + Note: This is system-wide limit, not per-thread. choice RT_USING_DFS_VERSION prompt "The version of DFS" default RT_USING_DFS_V1 default RT_USING_DFS_V2 if RT_USING_SMART + help + Select DFS version for your system. + + DFS v1.0: + - Traditional DFS implementation + - Stable and well-tested + - Suitable for most embedded applications + - Lower memory overhead + + DFS v2.0: + - Enhanced for RT-Smart user-space applications + - Page cache support for better performance + - Memory-mapped file support (mmap) + - Required for RT-Smart mode + + Choose v1.0 for standard RT-Thread applications. + Choose v2.0 for RT-Smart with user-space processes. config RT_USING_DFS_V1 bool "DFS v1.0" depends on !RT_USING_SMART + help + DFS version 1.0 - traditional implementation. + + Stable version for standard RT-Thread applications without + user-space process support. config RT_USING_DFS_V2 bool "DFS v2.0" select RT_USING_DEVICE_OPS + help + DFS version 2.0 - enhanced for RT-Smart. + + Advanced features: + - Page cache for improved performance + - Memory-mapped files (mmap) + - Better integration with RT-Smart processes + - Enhanced POSIX compliance + + Required for RT-Smart mode. endchoice if RT_USING_DFS_V1 config DFS_FILESYSTEMS_MAX int "The maximal number of mounted file system" default 4 + help + Maximum number of file systems that can be mounted simultaneously. + + Default: 4 mount points + + Each mount point uses ~40-60 bytes. + Examples: + - "/" - root file system (FAT/ROM/RAM) + - "/sdcard" - SD card FAT + - "/dev" - device file system + - "/tmp" - temporary file system + + Increase if you need more mount points. + Decrease to save RAM on simple systems (minimum 1). config DFS_FILESYSTEM_TYPES_MAX int "The maximal number of file system type" default 4 + help + Maximum number of different file system types registered. + + Default: 4 types + + Common file system types: + - elm (FAT/exFAT) + - romfs (Read-Only Memory FS) + - ramfs (RAM FS) + - devfs (Device FS) + - nfs (Network FS) + - tmpfs (Temporary FS) + + Each type registration uses ~20-30 bytes. + Set based on number of file system types you plan to use. endif config RT_USING_DFS_ELMFAT bool "Enable elm-chan fatfs" default n help - FatFs is a generic FAT/exFAT file system module for small embedded systems. + Enable elm-chan's FAT file system implementation. + + FatFs is a generic FAT/exFAT file system module designed for + embedded systems with limited resources. + + Supported file systems: + - FAT12, FAT16, FAT32 + - exFAT (with RT_DFS_ELM_USE_EXFAT enabled) + + Features: + - Long File Name (LFN) support + - Unicode file names (UTF-8/UTF-16/UTF-32) + - Thread-safe operations + - Multiple volumes + + Use cases: + - SD card file storage + - USB flash drives + - Internal flash storage + - Data logging + + ROM overhead: ~15-25KB depending on features enabled. + + Enable for FAT-formatted storage devices. + Disable if not using FAT file systems. if RT_USING_DFS_ELMFAT menu "elm-chan's FatFs, Generic FAT Filesystem Module" @@ -161,6 +319,29 @@ endif config RT_USING_DFS_DEVFS bool "Using devfs for device objects" default y + help + Enable device file system (devfs) for accessing devices as files. + + Devfs provides /dev directory containing device nodes: + - /dev/uart1, /dev/uart2 - Serial ports + - /dev/spi0, /dev/i2c0 - Bus devices + - /dev/sd0, /dev/sd1 - Block devices + - /dev/rtc - Real-time clock + + Benefits: + - Unified device access via open/read/write + - POSIX-compliant device operations + - Better abstraction and portability + - Required for many device drivers + + Essential for: + - Device access from user applications + - RT-Smart user-space processes + - Shell device operations + + Minimal overhead (~1-2KB ROM, ~100 bytes RAM). + + Recommended to keep enabled for device access convenience. if RT_USING_DFS_V1 config RT_USING_DFS_ISO9660 @@ -172,6 +353,31 @@ endif menuconfig RT_USING_DFS_ROMFS bool "Enable ReadOnly file system on flash" default n + help + Enable ROM File System for read-only data stored in flash memory. + + ROMFS stores read-only files directly in program flash, useful for: + - Static web pages for web servers + - Configuration files + - Font files and graphics resources + - Help files and documentation + - Initial file system bootstrap + + Features: + - Very small footprint (~2-3KB) + - No RAM required for file data (executes from flash) + - Files embedded in firmware binary + - Fast access (no erase/write delays) + + Files included at compile time using romfs generator tool. + + Use cases: + - Web server static content + - Resource files for GUI applications + - Read-only configuration defaults + + Enable if you need embedded read-only files. + Disable to save ~2-3KB ROM if not needed. if RT_USING_DFS_ROMFS config RT_USING_DFS_ROMFS_USER_ROOT @@ -194,6 +400,32 @@ endif bool "Enable ReadOnly compressed file system on flash" default n # select PKG_USING_ZLIB + help + Enable Compressed ROM File System for compressed read-only data. + + CROMFS is similar to ROMFS but with compression, providing: + - Reduced flash usage (typically 30-70% compression) + - Read-only access to compressed files + - Automatic decompression on read + - Files embedded in firmware binary + + Trade-offs: + + Saves flash space (important for large resource files) + - Higher CPU usage for decompression + - Slower file access than ROMFS + - Requires ZLIB for decompression + + Best for: + - Large resource files (fonts, graphics, web content) + - Flash-constrained systems + - Files accessed infrequently + + Not recommended for: + - Frequently accessed files + - CPU-constrained systems + - Files already compressed (JPEG, PNG, MP3) + + Note: Requires ZLIB package for decompression support. if RT_USING_DFS_V1 config RT_USING_DFS_RAMFS @@ -206,12 +438,63 @@ endif bool "Enable TMP file system" default y if RT_USING_SMART default n + help + Enable temporary file system (tmpfs) in RAM. + + Tmpfs provides a RAM-based file system for temporary files: + - Files stored entirely in RAM + - Very fast read/write performance + - Files lost on reboot/power-off + - Dynamic size (grows/shrinks with usage) + + Typical mount point: /tmp + + Use cases: + - Temporary file storage during runtime + - Fast cache for processed data + - Inter-process communication via temp files + - Build/compile temporary files + - RT-Smart /tmp directory + + Memory usage: + - Grows with file content + - Files consume RAM directly + + Automatically enabled for RT-Smart (required for POSIX /tmp). + + Enable if you need fast temporary file storage. + Disable to save RAM if temporary files not needed. config RT_USING_DFS_MQUEUE bool "Enable MQUEUE file system" select RT_USING_DEV_BUS default y if RT_USING_SMART default n + help + Enable POSIX message queue file system. + + Provides POSIX message queues as files in /dev/mqueue: + - mq_open(), mq_send(), mq_receive() + - Named message queues + - File descriptor based operations + - Process-safe IPC mechanism + + Features: + - POSIX-compliant message queue API + - Multiple processes can communicate + - Priority-based message delivery + - Blocking and non-blocking modes + + Use cases: + - Inter-process communication in RT-Smart + - POSIX application porting + - Priority message passing + + Required for RT-Smart POSIX message queues. + Automatically enabled in RT-Smart mode. + + Enable for POSIX message queue support. + Disable if not using POSIX IPC (~2-3KB ROM savings). if RT_USING_DFS_V1 config RT_USING_DFS_NFS diff --git a/components/finsh/Kconfig b/components/finsh/Kconfig index 67a50a28d7e..e8b507868da 100644 --- a/components/finsh/Kconfig +++ b/components/finsh/Kconfig @@ -3,95 +3,324 @@ menuconfig RT_USING_MSH default n if RT_USING_NANO default y select RT_USING_SEMAPHORE + help + MSH (Module SHell) is RT-Thread's command-line interface (CLI) shell. + + Provides interactive command execution for: + - System debugging and monitoring + - Runtime configuration and testing + - File system operations + - Network diagnostics + - Custom application commands + + Features: + - Tab completion for commands and file paths + - Command history with arrow keys + - Built-in commands (ls, ps, free, etc.) + - Custom command registration via MSH_CMD_EXPORT() + - Authentication support for secure access + + Typical use cases: + - Development and debugging + - Production diagnostics + - Interactive testing + - System administration + + Note: Disable for headless embedded systems to save ~8-16KB ROM. + Automatically disabled in RT_USING_NANO configuration. if RT_USING_MSH config RT_USING_FINSH bool default y + help + Internal configuration for finsh shell support. + Automatically enabled when RT_USING_MSH is selected. + Do not modify directly. config FINSH_USING_MSH bool default y + help + Use MSH (Module SHell) mode instead of traditional C-expression shell. + MSH provides a more familiar POSIX-like command interface. + Automatically enabled when RT_USING_MSH is selected. + Do not modify directly. config FINSH_THREAD_NAME string "The msh thread name" default "tshell" + help + Name of the MSH shell thread visible in thread list. + + Default: "tshell" + + Change this to avoid name conflicts or for identification purposes. + Thread name length limited by RT_NAME_MAX (default 8 chars). config FINSH_THREAD_PRIORITY int "The priority level value of thread" default 20 + help + Priority of MSH shell thread (lower number = higher priority). + + Default: 20 (low priority) + + Recommendations: + - Keep at low priority (15-25) to avoid blocking real-time tasks + - Increase priority if shell responsiveness is critical + - Must be less than RT_THREAD_PRIORITY_MAX + + Note: Shell executes user commands which may have high CPU usage. config FINSH_THREAD_STACK_SIZE int "The stack size for thread" default 4096 + help + Stack size in bytes for the MSH shell thread. + + Default: 4096 bytes (4KB) + + Increase if: + - Shell commands use deep recursion or large local variables + - Running complex scripts + - Stack overflow errors occur + + Decrease to save RAM on memory-constrained systems (minimum ~2KB). + + Note: Each command execution may require additional stack space. config FINSH_USING_HISTORY bool "Enable command history feature" default y + help + Enable command history buffer with up/down arrow key navigation. + + Features: + - Recall previous commands with up arrow + - Navigate forward with down arrow + - Configurable number of history lines + + Memory cost: ~80 bytes × FINSH_HISTORY_LINES + + Enable for improved user experience during interactive sessions. + Disable to save minimal RAM (~400 bytes with default 5 lines). if FINSH_USING_HISTORY config FINSH_HISTORY_LINES int "The command history line number" default 5 + help + Number of command lines stored in history buffer. + + Default: 5 lines + + Each line uses ~80 bytes (FINSH_CMD_SIZE). + Total memory: FINSH_HISTORY_LINES × FINSH_CMD_SIZE + + Increase for longer history (up to ~10-20 lines reasonable). + Decrease to save RAM on constrained systems. endif config FINSH_USING_WORD_OPERATION bool "Enable word-based cursor operations" default n help - Enable Ctrl+Backspace to delete words and Ctrl+Arrow to move cursor by word + Enable Ctrl+Backspace to delete words and Ctrl+Arrow to move cursor by word. + + Provides enhanced editing with word-boundary operations: + - Ctrl+Backspace: Delete word before cursor + - Ctrl+Left/Right Arrow: Move cursor by word + + Improves command-line editing efficiency for long commands. + Minimal memory overhead (~100 bytes). config FINSH_USING_FUNC_EXT bool "Enable function extension home end ins del" default n help - Enable function extension home end ins del. + Enable extended function keys for cursor movement and editing. + + Supported keys: + - Home: Move cursor to start of line + - End: Move cursor to end of line + - Insert: Toggle insert/overwrite mode + - Delete: Delete character at cursor + + Provides familiar editing experience from standard terminals. + Minimal memory overhead (~100 bytes). config FINSH_USING_SYMTAB bool "Using symbol table for commands" default y + help + Use symbol table to store and lookup shell commands. + + When enabled: + - Commands registered via MSH_CMD_EXPORT() are stored in symbol table + - Supports command name lookup and auto-completion + - Enables help command to list all available commands + + Required for most shell functionality. Only disable for minimal + configurations where commands are hard-coded. + + Disabling saves ~1-2KB depending on number of commands. config FINSH_CMD_SIZE int "The command line size for shell" default 80 + help + Maximum length of a single command line including arguments. + + Default: 80 characters + + Increase if you need to: + - Enter long file paths + - Pass many arguments to commands + - Use complex command pipelines + + Decrease to save RAM (minimum ~40 chars recommended). + + Memory impact: FINSH_CMD_SIZE bytes per command buffer + + FINSH_CMD_SIZE × FINSH_HISTORY_LINES for history config MSH_USING_BUILT_IN_COMMANDS bool "Enable built-in commands, such as list_thread" default y + help + Include standard built-in shell commands. + + Built-in commands include: + - System: help, version, reboot + - Threads: list_thread (ps), list_sem, list_mutex, list_timer + - Memory: free, memcheck, memtrace + - File system: ls, cd, pwd, cat, rm, mkdir, etc. + + Disabling removes these commands but allows custom implementations. + Saves ~4-8KB ROM depending on enabled features. + + Recommended to keep enabled unless implementing custom command set. config FINSH_USING_DESCRIPTION bool "Keeping description in symbol table" default y + help + Store command descriptions in symbol table for help text. + + When enabled: + - 'help' command shows detailed description for each command + - MSH_CMD_EXPORT() macro can include description parameter + + Cost: ~20-50 bytes per command for description strings + + Disable to save ROM if help text not needed in production. + Keep enabled during development for better usability. config FINSH_ECHO_DISABLE_DEFAULT bool "Disable the echo mode in default" default n + help + Disable character echo by default when shell starts. + + When disabled (echo off): + - Typed characters not displayed (useful for password input) + - Can be toggled at runtime with 'echo' command + + Normal configuration: Keep disabled (echo enabled by default) + + Enable this option to start with echo off, useful for: + - Security-sensitive applications + - Non-interactive serial protocols + - Automated test scripts config FINSH_USING_AUTH bool "shell support authentication" default n + help + Enable password authentication for shell access. + + Security features: + - Password prompt on shell connection + - Configurable password and length requirements + - Locks shell until correct password entered + + Use cases: + - Production systems with console access + - Security-critical applications + - Preventing unauthorized access via UART/Telnet + + Note: Password stored in plain text in firmware. + For strong security, combine with encrypted communication. if FINSH_USING_AUTH config FINSH_DEFAULT_PASSWORD string "The default password for shell authentication" default "rtthread" + help + Default password required to access the shell. + + Default: "rtthread" + + Security recommendations: + - Change from default in production systems + - Use strong passwords (mix of letters, numbers, symbols) + - Length between FINSH_PASSWORD_MIN and FINSH_PASSWORD_MAX + + Note: Password stored as plain text in firmware binary. + Anyone with firmware access can extract the password. config FINSH_PASSWORD_MIN int "The password min length" default 6 + help + Minimum password length in characters. + + Default: 6 characters + + Enforces minimum password strength. Increase for better security + (recommended: 8+ characters for production). config FINSH_PASSWORD_MAX int "The password max length" default RT_NAME_MAX + help + Maximum password length in characters. + + Default: RT_NAME_MAX (typically 8) + + Limited by password buffer size. Increase RT_NAME_MAX if you + need longer passwords, but consider memory constraints. endif config FINSH_ARG_MAX int "The number of arguments for a shell command" default 10 + help + Maximum number of arguments (including command name) that can be + passed to a single shell command. + + Default: 10 arguments + + Increase if you have commands that need many parameters. + Each argument slot uses ~4 bytes (pointer size). + + Total memory: FINSH_ARG_MAX × sizeof(char*) config FINSH_USING_OPTION_COMPLETION bool "command option completion enable" default y + help + Enable tab completion for command options and arguments. + + Features: + - Press Tab to auto-complete command names + - Complete file paths when using file system commands + - Show list of matches if multiple options available + + Greatly improves usability and reduces typing errors. + Minimal memory overhead (~200 bytes). + + Recommended to keep enabled for interactive shells. endif From e6166a17e9f27b40f6466289f9d44e63665cc1f1 Mon Sep 17 00:00:00 2001 From: "copilot-swe-agent[bot]" <198982749+Copilot@users.noreply.github.com> Date: Mon, 17 Nov 2025 08:51:35 +0000 Subject: [PATCH 4/9] Add comprehensive help for lwp and net/sal Kconfig files Co-authored-by: Rbb666 <64397326+Rbb666@users.noreply.github.com> --- components/lwp/Kconfig | 293 ++++++++++++++++++++++++++++++++++++- components/net/sal/Kconfig | 151 ++++++++++++++++++- 2 files changed, 438 insertions(+), 6 deletions(-) diff --git a/components/lwp/Kconfig b/components/lwp/Kconfig index 4a83405d8a0..62848a5d806 100644 --- a/components/lwp/Kconfig +++ b/components/lwp/Kconfig @@ -3,12 +3,61 @@ menuconfig RT_USING_LWP depends on RT_USING_SMART default y help - The lwP is a light weight process running in user mode. + LWP (Light Weight Process) provides user-space process support in RT-Smart mode. + + Features: + - User-space and kernel-space separation + - Process isolation with MMU/MPU + - POSIX process APIs (fork, exec, waitpid, etc.) + - Inter-process communication (IPC) + - Signal handling + - Dynamic linking and loading (LDSO) + + Benefits: + - Memory protection between processes + - Fault isolation (process crash doesn't affect kernel) + - Multi-user application support + - Better security and stability + + Requirements: + - RT_USING_SMART must be enabled + - CPU with MMU or MPU support + - DFS v2.0 for file system access + + Use cases: + - Running untrusted user applications + - Mixed-criticality systems + - Applications requiring process isolation + - POSIX application porting + + Note: LWP is the foundation of RT-Smart user-space support. + Required for running user-space applications. if RT_USING_LWP menuconfig LWP_DEBUG bool "Enable debugging features of LwP" default n + help + Enable debugging and tracing features for LWP processes. + + Debug features: + - Process state transitions logging + - Memory allocation tracking + - IPC operation tracing + - Signal delivery monitoring + + Useful for: + - Development and debugging + - Troubleshooting process issues + - Performance analysis + - System behavior understanding + + Overhead: + - Increased log output + - Slightly slower process operations + - Additional ROM for debug strings (~2-4KB) + + Enable during development, disable in production for performance. if LWP_DEBUG config LWP_DEBUG_INIT @@ -16,56 +65,231 @@ if RT_USING_LWP bool "Enable debug mode of init process" depends on LWP_USING_RUNTIME default y + help + Enable detailed debugging for init process (PID 1). + + Traces init process activities: + - Boot script execution + - Child process spawning + - Signal handling + - Shutdown sequence + + Useful for debugging system startup and shutdown issues. + Requires LWP_USING_RUNTIME enabled. endif config LWP_USING_RUNTIME bool "Using processes runtime environment (INIT process)" default y help - Runtime environment provide by init process including boot scripts, - poweroff, shutdown, reboot, etc. + Enable init process and runtime environment for user-space. + + Provides Linux-like init system (PID 1) that: + - Starts as first user process + - Executes boot scripts (/etc/rc.local, /etc/init.d/*) + - Manages system lifecycle + - Handles orphaned processes + - Provides system commands (poweroff, reboot, shutdown) + + Features: + - Boot script support for auto-starting applications + - Graceful shutdown handling + - Process reaping (zombie cleanup) + - System service management + + Required for: + - Complete RT-Smart user-space environment + - Automatic application startup + - System lifecycle management + + Disable only for minimal systems without init process. config RT_LWP_MAX_NR int "The max number of light-weight process" default 30 + help + Maximum number of processes that can run simultaneously. + + Default: 30 processes + + Each process uses: + - ~200-400 bytes for process control block + - Separate page tables (MMU systems) + - Individual memory spaces + + Total memory: RT_LWP_MAX_NR × ~300 bytes (minimum) + + Increase for: + - Systems running many concurrent applications + - Multi-user environments + + Decrease to save memory on constrained systems. + Minimum recommended: 8-10 processes. config LWP_TASK_STACK_SIZE int "The lwp thread kernel stack size" default 16384 + help + Kernel stack size for each LWP thread in bytes. + + Default: 16384 bytes (16KB) + + This is the kernel-mode stack used when process enters kernel via: + - System calls + - Exception handling + - Interrupt processing + + Stack usage depends on: + - System call complexity + - Nested interrupt depth + - Kernel function call chains + + Increase if: + - Kernel stack overflow errors + - Deep system call nesting + - Complex device drivers + + Decrease to save RAM (minimum ~8KB for basic operations). + Each LWP thread requires this much kernel stack. config RT_CH_MSG_MAX_NR int "The maximum number of channel messages" default 1024 + help + Maximum number of messages in channel IPC message pool. + + Default: 1024 messages + + Channels provide RT-Thread's native IPC mechanism for LWP: + - Higher performance than POSIX IPC + - Direct memory-mapped communication + - Zero-copy message passing + + Each message slot uses ~32-64 bytes depending on message size. + + Increase for: + - High-frequency IPC between processes + - Many concurrent channel communications + + Decrease to save memory if channel IPC not heavily used. config LWP_TID_MAX_NR int "The maximum number of lwp thread id" default 64 + help + Maximum number of thread IDs available for LWP threads. + + Default: 64 thread IDs + + Each process can create multiple threads. This limits total + thread IDs across all processes. + + Typical usage: + - Single-threaded processes: 1 TID each + - Multi-threaded processes: N TIDs per process + + Total threads = sum of threads in all processes + + Increase for: + - Applications creating many threads + - Many multi-threaded processes + + Decrease if applications mostly single-threaded. config LWP_ENABLE_ASID bool "The switch of ASID feature" depends on ARCH_ARM_CORTEX_A default y + help + Enable Address Space ID (ASID) for Cortex-A processors. + + ASID provides hardware-based process identification: + - Tags TLB entries with process ID + - Avoids TLB flush on context switch + - Significantly faster process switching + + Performance impact: + - 50-70% faster context switch between processes + - Better TLB hit rate + - Reduced MMU overhead + + Automatically enabled for Cortex-A (recommended). + Only disable for debugging TLB-related issues. + + Note: Requires CPU with ASID support (ARMv7-A and above). if ARCH_MM_MMU config RT_LWP_SHM_MAX_NR int "The maximum number of shared memory" default 64 + help + Maximum number of shared memory segments for inter-process communication. + + Default: 64 segments + + Shared memory provides: + - Fastest IPC method (direct memory access) + - POSIX shm_open()/shm_unlink() APIs + - mmap() for memory-mapped sharing + + Each segment descriptor uses ~40-60 bytes. + + Increase for: + - Applications using extensive shared memory + - Multiple processes sharing data + - High-performance IPC requirements + + Decrease to save memory if shared memory rarely used. config LWP_USING_MPROTECT bool default n help - ARCH has the support of mprotect + Architecture has mprotect() support for memory protection. + + mprotect() allows changing memory region permissions: + - Read, write, execute permissions + - Guard pages for stack overflow detection + - Memory region isolation + + Automatically enabled by architecture support. + User does not configure directly. endif if ARCH_MM_MPU config RT_LWP_MPU_MAX_NR int "The maximum number of mpu region" default 2 + help + Maximum number of MPU regions per process. + + Default: 2 regions per process + + MPU provides memory protection without full MMU: + - Limited number of protection regions + - Simpler than MMU but less flexible + + Regions typically used for: + - Code region (read-execute) + - Data region (read-write) + - Stack guard region + + Limited by hardware MPU region count. + Check your CPU MPU capabilities. config RT_LWP_USING_SHM bool "Enable shared memory" default y + help + Enable shared memory support for MPU-based systems. + + Provides shared memory IPC even without MMU: + - Processes can share memory regions + - Requires careful MPU configuration + - More limited than MMU-based sharing + + Enable for IPC in MPU-only systems (Cortex-M with MPU). + Disable if not using shared memory to save ~1-2KB ROM. endif menuconfig RT_USING_LDSO @@ -73,15 +297,76 @@ if RT_USING_LWP depends on RT_USING_DFS_V2 select RT_USING_PAGECACHE default y + help + Enable dynamic linker/loader for shared libraries and executables. + + LDSO (LD.SO - Link editor, Shared Object) provides: + - Dynamic linking of shared libraries (.so files) + - Runtime loading of executables (ELF files) + - Symbol resolution and relocation + - Lazy binding for faster startup + + Features: + - Load executables from file system + - Share library code between processes (saves RAM) + - Update libraries without recompiling applications + - Standard ELF binary support + + Requirements: + - DFS v2.0 for file system access + - Page cache for performance + + Use cases: + - Running standard Linux binaries + - Modular application architecture + - Shared library usage + - Dynamic plugin loading + + Essential for RT-Smart user-space applications. + ROM overhead: ~10-15KB for LDSO implementation. if RT_USING_LDSO config ELF_DEBUG_ENABLE bool "Enable ldso debug" default n + help + Enable debugging output for dynamic linker/loader operations. + + Debug information includes: + - Library loading and unloading + - Symbol resolution process + - Relocation details + - Memory mapping operations + + Useful for: + - Troubleshooting loading failures + - Understanding dependency chains + - Debugging symbol resolution issues + + Disable in production for reduced log output and smaller ROM. config ELF_LOAD_RANDOMIZE bool "Enable random load address" default n + help + Enable ASLR (Address Space Layout Randomization) for loaded binaries. + + Security feature that randomizes: + - Executable base address + - Shared library load addresses + - Stack and heap positions + + Benefits: + - Harder to exploit buffer overflows + - Prevents return-to-libc attacks + - Increases security against memory exploits + + Overhead: + - Slightly slower loading + - More complex debugging (non-deterministic addresses) + + Enable for security-critical applications. + Disable for easier debugging or deterministic behavior. endif rsource "terminal/Kconfig" diff --git a/components/net/sal/Kconfig b/components/net/sal/Kconfig index 57d9e7215ef..b4edbebcd45 100644 --- a/components/net/sal/Kconfig +++ b/components/net/sal/Kconfig @@ -2,6 +2,35 @@ menuconfig RT_USING_SAL bool "SAL: socket abstraction layer" select RT_USING_NETDEV default n + help + SAL (Socket Abstraction Layer) provides unified BSD socket API for multiple network stacks. + + Features: + - Standard BSD socket API (socket, bind, connect, send, recv, etc.) + - Support multiple protocol stacks simultaneously + - Network stack independence for applications + - Automatic routing between different network interfaces + + Supported protocol stacks: + - LwIP (full TCP/IP stack) + - AT commands (for cellular/WiFi modules) + - TLS/SSL (via MbedTLS) + - Custom protocol stacks + + Benefits: + - Write once, run on any supported network stack + - Easy switching between WiFi, Ethernet, cellular + - Multiple network connections concurrently + - Standard POSIX socket compatibility + + Use cases: + - Applications requiring network connectivity + - Multi-interface systems (WiFi + Ethernet) + - IoT devices with multiple network options + - Network stack abstraction + + Enable for any application using network sockets. + Overhead: ~4-6KB ROM, ~1KB RAM + socket buffers. if RT_USING_SAL @@ -15,19 +44,107 @@ if RT_USING_SAL config SOCKET_TABLE_STEP_LEN int "Configure socket table step length" default 4 + help + Growth step size for dynamic socket table expansion. + + Default: 4 sockets + + When socket table is full, it grows by this many entries: + - Initial size: SAL_SOCKETS_NUM + - Grows by: SOCKET_TABLE_STEP_LEN when full + + Smaller values: + + Less wasted memory + - More frequent reallocations + + Larger values: + + Fewer reallocations + - More unused memory + + Recommended: 4-8 for most applications. menu "Docking with protocol stacks" config SAL_USING_LWIP bool "Docking with lwIP stack" default n + help + Integrate LwIP (Lightweight IP) TCP/IP stack with SAL. + + LwIP provides full-featured TCP/IP protocol stack: + - TCP, UDP, ICMP, IGMP protocols + - IPv4 and IPv6 support + - DHCP client and server + - DNS resolution + - Raw socket support + + When enabled, applications can use BSD sockets backed by LwIP. + + Required for: + - Ethernet networking + - WiFi with full TCP/IP + - Complex network protocols + + Enable if using LwIP as network stack. config SAL_USING_AT bool "Docking with AT commands stack" default n + help + Integrate AT command-based network modules with SAL. + + AT commands provide network connectivity through: + - Cellular modules (2G/3G/4G/5G/NB-IoT) + - WiFi modules (ESP8266, ESP32, etc.) + - Bluetooth modules + + Features: + - BSD socket API over AT commands + - Transparent to applications + - Supports multiple AT devices + - Hardware offload (module handles TCP/IP) + + Advantages: + - Lower MCU resource usage + - Faster time-to-market + - Leverages module's TCP/IP stack + + Use cases: + - IoT devices with cellular connectivity + - Low-power WiFi applications + - Systems with network co-processors + + Enable for AT command-based network modules. config SAL_USING_TLS bool "Docking with MbedTLS protocol" default n + help + Integrate MbedTLS for SSL/TLS secure communication. + + MbedTLS provides: + - SSL/TLS encryption (TLS 1.0-1.3) + - X.509 certificate handling + - Secure sockets (HTTPS, MQTTS, etc.) + - Cryptographic primitives + + Features: + - Transparent SSL/TLS layer over SAL + - Certificate verification + - Multiple cipher suites + - Session resumption + + Use cases: + - HTTPS web clients/servers + - Secure MQTT (MQTTS) + - Encrypted data transmission + - Cloud service connections (AWS, Azure, etc.) + + Requirements: + - MbedTLS package + - Network stack (LwIP or AT) + - Sufficient RAM for TLS buffers (~20-40KB) + + Enable for secure network communications. endmenu config SAL_USING_POSIX @@ -35,12 +152,42 @@ if RT_USING_SAL depends on DFS_USING_POSIX default y help - Enable BSD socket operated by file system API - Let BSD socket operated by file system API, such as read/write and involveed in select/poll POSIX APIs. + Enable BSD socket operations via file system API. + + When enabled, sockets can be used like files: + - open/close for socket creation/destruction + - read/write for send/receive + - select/poll for I/O multiplexing + - File descriptor sharing with regular files + + Benefits: + - Unified I/O model (files + sockets) + - Compatible with POSIX I/O functions + - Works with select/poll + - Easier application porting from Linux + + Automatically enabled when DFS with POSIX is available. + Required for RT-Smart user-space socket access. config SAL_SOCKETS_NUM int "the maximum number of sockets" depends on !SAL_USING_POSIX default 16 + help + Maximum number of sockets that can be created simultaneously. + + Default: 16 sockets + + Each socket uses: + - ~100-200 bytes for socket structure + - Send/receive buffers (protocol stack dependent) + + Increase for: + - Server applications with many concurrent connections + - Applications opening multiple sockets + + Decrease to save memory on constrained systems. + + Note: Not used when SAL_USING_POSIX enabled (uses DFS_FD_MAX instead). endif From 560deecceca8141319a2975c4181909d02d3a84b Mon Sep 17 00:00:00 2001 From: "copilot-swe-agent[bot]" <198982749+Copilot@users.noreply.github.com> Date: Mon, 17 Nov 2025 10:04:41 +0000 Subject: [PATCH 5/9] Add comprehensive help for POSIX layer Kconfig files Co-authored-by: Rbb666 <64397326+Rbb666@users.noreply.github.com> --- components/libc/posix/Kconfig | 417 ++++++++++++++++++++++++++++++ components/libc/posix/ipc/Kconfig | 105 ++++++++ 2 files changed, 522 insertions(+) diff --git a/components/libc/posix/Kconfig b/components/libc/posix/Kconfig index 8a4a3843cbd..cae76f7af46 100644 --- a/components/libc/posix/Kconfig +++ b/components/libc/posix/Kconfig @@ -5,51 +5,223 @@ config RT_USING_POSIX_FS select RT_USING_DFS select DFS_USING_POSIX default n + help + Enable POSIX-compliant file system and I/O APIs. + + Provides standard POSIX file operations: + - File I/O: open(), read(), write(), close(), lseek() + - Directory: opendir(), readdir(), closedir() + - File control: fcntl(), ioctl() + - File status: stat(), fstat(), access() + - File operations: unlink(), rename(), chmod() + + Benefits: + - Source code compatibility with Linux/Unix + - Easier porting of existing applications + - Standard API familiar to developers + - Better integration with third-party libraries + + Requirements: + - RT_USING_DFS must be enabled + - File system support (FAT, ROM-FS, etc.) + + Enable for applications requiring POSIX file I/O compatibility. + Essential for porting Linux/Unix applications to RT-Thread. if RT_USING_POSIX_FS config RT_USING_POSIX_DEVIO bool "Enable devices as file descriptors" select RT_USING_DFS_DEVFS default n + help + Access devices through file descriptors like regular files. + + Allows opening devices in /dev using standard file operations: + - fd = open("/dev/uart1", O_RDWR) + - read(fd, buffer, size) / write(fd, buffer, size) + - ioctl(fd, cmd, arg) for device control + - close(fd) + + Benefits: + - Unified I/O model for files and devices + - Compatible with select/poll for device I/O + - Easier application design + + Automatically enables devfs (/dev filesystem). + + Enable for POSIX-style device access. + Required for RT_USING_POSIX_STDIO. config RT_USING_POSIX_STDIO bool "Enable standard I/O devices, e.g. STDOUT_FILENO" select RT_USING_POSIX_DEVIO default n + help + Enable standard POSIX I/O file descriptors. + + Provides standard file descriptors: + - STDIN_FILENO (0): Standard input + - STDOUT_FILENO (1): Standard output + - STDERR_FILENO (2): Standard error + + Allows using printf, scanf, fprintf with standard streams. + + Benefits: + - Compatible with standard C library I/O + - Easier debugging with stderr + - Standard input/output redirection + + Requires RT_USING_POSIX_DEVIO (device file descriptors). + + Enable for applications using stdin/stdout/stderr. config RT_USING_POSIX_POLL bool "Enable I/O Multiplexing poll() " default y if RT_USING_SMART default n + help + Enable POSIX poll() for I/O multiplexing. + + poll() monitors multiple file descriptors for I/O events: + - Wait for data available on sockets/files + - Detect when writing won't block + - Error and hangup conditions + - Timeout support + + Use cases: + - Network servers handling multiple connections + - Monitoring multiple devices simultaneously + - Event-driven I/O programming + + More portable than select() (no FD_SETSIZE limit). + + Automatically enabled in RT-Smart mode. + Enable for I/O multiplexing applications. config RT_USING_POSIX_SELECT bool "Enable I/O Multiplexing select() " select RT_USING_POSIX_POLL default y if RT_USING_SMART default n + help + Enable POSIX select() for I/O multiplexing. + + select() monitors file descriptors for I/O readiness: + - Check multiple sockets/files for data + - Wait with timeout + - Detect errors and exceptions + + Compatible with BSD sockets and standard POSIX API. + + Advantages over poll(): + + More widely known API + + Compatible with older code + + Disadvantages: + - Limited to FD_SETSIZE file descriptors (typically 1024) + - Less efficient for large numbers of FDs + + Automatically enables poll() (implementation uses poll). + + Enable for applications using select() API. config RT_USING_POSIX_EVENTFD bool "Enable I/O event eventfd " select RT_USING_POSIX_POLL default y if RT_USING_SMART default n + help + Enable Linux-style eventfd for event notification. + + eventfd provides a file descriptor for event notification: + - Create event object: eventfd(initval, flags) + - Signal event: write(efd, &value, 8) + - Wait for event: read(efd, &value, 8) + - Integrates with poll/select/epoll + + Features: + - Semaphore-style counting (EFD_SEMAPHORE) + - Non-blocking mode (EFD_NONBLOCK) + - Cloexec flag support (EFD_CLOEXEC) + + Use cases: + - Thread/process notification + - Event-driven architectures + - Integrating with poll/epoll event loops + + Lighter weight than pipes for simple notifications. + + Enable for Linux-compatible event notification. if RT_USING_SMART config RT_USING_POSIX_EPOLL bool "Enable I/O Multiplexing epoll " select RT_USING_POSIX_POLL default y + help + Enable Linux epoll for scalable I/O multiplexing. + + epoll is designed for handling large numbers of file descriptors: + - No FD_SETSIZE limit (unlike select) + - O(1) performance (vs O(n) for select/poll) + - Edge-triggered and level-triggered modes + - One-shot mode support + + API: + - epoll_create(): Create epoll instance + - epoll_ctl(): Add/modify/remove file descriptors + - epoll_wait(): Wait for I/O events + + Benefits: + - Scales to thousands of connections + - Better performance for large FD sets + - More flexible event notification + + Use cases: + - High-performance network servers + - Event-driven applications + - Systems with many concurrent I/O operations + + Required for RT-Smart. Recommended for server applications. config RT_USING_POSIX_SIGNALFD bool "Enable Signalfd " select RT_USING_POSIX_POLL default y + help + Enable signalfd for receiving signals via file descriptor. + + signalfd converts signal delivery into file I/O: + - Create: signalfd(fd, &mask, flags) + - Read signal info: read(sfd, &siginfo, sizeof(siginfo)) + - Integrate with poll/select/epoll + + Benefits: + - Unified event handling (signals + I/O) + - Avoid signal handler race conditions + - Easier signal processing in event loops + + Use cases: + - Event-driven applications handling signals + - Integrating signals with epoll event loops + - Safe signal handling without signal handlers + + Required for RT-Smart signal handling integration. if RT_USING_POSIX_SIGNALFD config RT_SIGNALFD_MAX_NUM int "signaled The maximum number of concurrent firing signals" range 1 20 default 10 + help + Maximum number of signals that can be queued in signalfd. + + Default: 10 signals + + Limits memory usage for signal buffering. + Increase if applications generate many concurrent signals. + + Each signal uses ~128 bytes for siginfo structure. endif endif @@ -57,62 +229,307 @@ if RT_USING_POSIX_FS bool "Enable I/O timerfd " default y if RT_USING_SMART default n + help + Enable timerfd for timer notification via file descriptor. + + timerfd provides timer expiration as file I/O events: + - Create: timerfd_create(clockid, flags) + - Set timer: timerfd_settime(fd, flags, &spec, NULL) + - Read expiration: read(tfd, &expirations, 8) + - Integrate with poll/select/epoll + + Features: + - One-shot and periodic timers + - Absolute and relative timeouts + - Can be monitored with epoll + + Benefits: + - Unified event handling (timers + I/O) + - Multiple independent timers + - Compatible with event-driven design + + Use cases: + - Event loop timers + - Timeout handling in servers + - Periodic tasks in event-driven apps + + Enable for file-descriptor-based timer notification. config RT_USING_POSIX_SOCKET bool "Enable BSD Socket I/O " select RT_USING_POSIX_SELECT select RT_USING_SAL default n + help + Enable POSIX BSD socket API for network programming. + + Provides standard socket APIs: + - socket(), bind(), listen(), accept(), connect() + - send(), recv(), sendto(), recvfrom() + - setsockopt(), getsockopt() + - getaddrinfo(), gethostbyname() + + Requires SAL (Socket Abstraction Layer) for network stack. + + Enables network application development with standard API. + See Network -> SAL configuration for protocol stack selection. config RT_USING_POSIX_TERMIOS bool "Enable Terminal I/O " select RT_USING_POSIX_STDIO default n + help + Enable POSIX terminal I/O control (termios). + + Provides terminal control APIs: + - tcgetattr(), tcsetattr(): Get/set terminal attributes + - cfsetispeed(), cfsetospeed(): Set baud rates + - tcdrain(), tcflush(), tcflow(): Terminal flow control + + Features: + - Raw and canonical mode control + - Baud rate configuration + - Character size and parity settings + - Flow control (hardware/software) + + Use cases: + - Serial terminal configuration + - Raw mode for binary protocols + - Terminal emulation applications + + Requires RT_USING_POSIX_STDIO (standard I/O). + + Enable for POSIX terminal control compatibility. config RT_USING_POSIX_AIO bool "Enable Asynchronous I/O " default n + help + Enable POSIX Asynchronous I/O APIs. + + Provides async I/O operations: + - aio_read(), aio_write(): Asynchronous read/write + - aio_fsync(): Asynchronous file sync + - aio_suspend(): Wait for async operations + - aio_error(), aio_return(): Check status + + Benefits: + - Non-blocking I/O operations + - Better CPU utilization + - Overlap I/O with computation + + Use cases: + - High-performance file I/O + - Database systems + - Large file operations + + Note: Requires careful memory management. + Overhead: ~200-400 bytes per async operation. config RT_USING_POSIX_MMAN bool "Enable Memory-Mapped I/O " default n + help + Enable POSIX memory mapping (mmap). + + Provides memory mapping APIs: + - mmap(): Map files or devices into memory + - munmap(): Unmap memory regions + - mprotect(): Set memory protection + - msync(): Synchronize memory with file + + Benefits: + - Efficient file I/O (no read/write calls) + - Shared memory between processes + - Large file handling + + Use cases: + - Large file access + - Shared memory IPC + - Memory-mapped device registers + + Requires MMU or MPU support. + Available in RT-Smart with proper hardware support. endif config RT_USING_POSIX_DELAY select RT_USING_KTIME bool "Enable delay APIs, sleep()/usleep()/msleep() etc" default n + help + Enable POSIX delay/sleep functions. + + Provides standard delay APIs: + - sleep(seconds): Sleep for seconds + - usleep(microseconds): Sleep for microseconds + - msleep(milliseconds): Sleep for milliseconds + - nanosleep(timespec): High-precision sleep + + Based on RT-Thread's kernel time (ktime) for accuracy. + + Benefits: + - Standard POSIX API for delays + - Better code portability + - Microsecond precision + + Enable for POSIX-compatible delay functions. + Automatically selected by RT_USING_POSIX_CLOCK. config RT_USING_POSIX_CLOCK bool "Enable clock/time APIs, clock_gettime()/clock_settime() etc" select RT_USING_POSIX_DELAY default n + help + Enable POSIX clock and time APIs. + + Provides standard time functions: + - clock_gettime(): Get clock time + - clock_settime(): Set clock time + - clock_getres(): Get clock resolution + + Supported clocks: + - CLOCK_REALTIME: System-wide real-time clock + - CLOCK_MONOTONIC: Monotonic time (doesn't jump) + - CLOCK_PROCESS_CPUTIME_ID: Process CPU time + - CLOCK_THREAD_CPUTIME_ID: Thread CPU time + + Benefits: + - Standard time API + - High-resolution timestamps + - Monotonic time for intervals + + Required by pthreads and POSIX timers. + Enable for POSIX time functionality. config RT_USING_POSIX_TIMER select RT_USING_KTIME select RT_USING_RESOURCE_ID bool "Enable timer APIs, timer_create()/timer_gettime() etc" default n + help + Enable POSIX interval timers. + + Provides POSIX timer APIs: + - timer_create(): Create a timer + - timer_settime(): Arm/disarm timer + - timer_gettime(): Get timer status + - timer_delete(): Delete timer + + Features: + - Per-process timers + - One-shot and periodic modes + - Signal-based or thread-based notification + - Absolute and relative timeouts + + Use cases: + - Periodic task execution + - Timeout handling + - Watchdog timers + - Scheduled events + + Requires KTIME and resource ID management. + Enable for POSIX timer functionality. config RT_USING_PTHREADS bool "Enable pthreads APIs" select RT_USING_POSIX_CLOCK default n + help + Enable POSIX threads (pthreads) API. + + Provides standard threading APIs: + - Thread management: pthread_create(), pthread_join(), pthread_exit() + - Mutex: pthread_mutex_lock(), pthread_mutex_unlock() + - Condition variables: pthread_cond_wait(), pthread_cond_signal() + - Read-write locks: pthread_rwlock_*() + - Barriers: pthread_barrier_*() + - Thread-specific data: pthread_key_create(), pthread_setspecific() + + Benefits: + - Standard threading API for portability + - Compatible with Linux/Unix applications + - Rich synchronization primitives + + Implementation: + - Maps to RT-Thread native threads + - Full POSIX thread attribute support + - Detached and joinable threads + + Essential for porting multi-threaded POSIX applications. + + Configure maximum threads with PTHREAD_NUM_MAX. if RT_USING_PTHREADS config PTHREAD_NUM_MAX int "Maximum number of pthreads" default 8 + help + Maximum number of POSIX threads (pthreads) that can exist simultaneously. + + Default: 8 threads + + Each pthread uses: + - Thread control block (~100-200 bytes) + - Stack (configured per thread) + - pthread-specific data storage + + Increase for applications creating many threads. + Decrease to save memory on constrained systems. + + Note: This is separate from RT-Thread native thread limit. endif config RT_USING_MODULE bool "Enable dynamic module APIs, dlopen()/dlsym()/dlclose() etc" default n + help + Enable POSIX dynamic module loading (dlopen/dlsym). + + Provides dynamic library APIs: + - dlopen(): Load shared library + - dlsym(): Get symbol address from library + - dlclose(): Unload library + - dlerror(): Get error string + + Features: + - Runtime loading of .so files + - Symbol resolution + - Lazy and immediate binding + - RTLD_GLOBAL and RTLD_LOCAL scope + + Use cases: + - Plugin architectures + - Optional feature loading + - Runtime extensibility + - Reduce initial memory footprint + + Requires: + - DFS for file system access + - Module support in build system + + Note: Increases complexity and security considerations. + Enable for dynamic module/plugin support. if RT_USING_MODULE config RT_USING_CUSTOM_DLMODULE bool "Enable load dynamic module by custom" default n + help + Enable custom dynamic module loader. + + Allows implementing custom module loading logic: + - Custom file format support + - Special initialization sequences + - Security checks and validation + - Custom symbol resolution + + Use cases: + - Proprietary module formats + - Enhanced security validation + - Special loading requirements + + Disable for standard ELF module loading. + Enable only if custom loader needed. endif rsource "ipc/Kconfig" diff --git a/components/libc/posix/ipc/Kconfig b/components/libc/posix/ipc/Kconfig index 2bec2077546..c295ad7143c 100644 --- a/components/libc/posix/ipc/Kconfig +++ b/components/libc/posix/ipc/Kconfig @@ -7,11 +7,52 @@ config RT_USING_POSIX_PIPE select RT_USING_POSIX_POLL select RT_USING_RESOURCE_ID default n + help + Enable POSIX pipes and FIFOs for inter-process communication. + + Provides: + - Anonymous pipes: pipe(pipefd) + - Named pipes (FIFOs): mkfifo(path, mode) + - Unidirectional byte streams + - Blocking and non-blocking I/O + + Features: + - Simple producer-consumer pattern + - Works with select/poll for multiplexing + - File descriptor based (can use read/write) + + Use cases: + - Parent-child process communication + - Shell command pipelines + - Simple message passing + - Event notification + + Buffer size: RT_USING_POSIX_PIPE_SIZE + + Enable for POSIX pipe/FIFO support. + Essential for shell pipeline and process IPC. config RT_USING_POSIX_PIPE_SIZE int "Set pipe buffer size" depends on RT_USING_POSIX_PIPE default 512 + help + Size of pipe buffer in bytes. + + Default: 512 bytes + + Trade-offs: + Larger buffer: + + More data can be buffered + + Better performance for burst writes + - More memory per pipe + + Smaller buffer: + + Less memory usage + - More frequent blocking on writes + + Typical values: 512-4096 bytes + Adjust based on typical message sizes and memory constraints. # We have't implement of 'systemv ipc', so hide it firstly. # @@ -28,11 +69,75 @@ config RT_USING_POSIX_MESSAGE_QUEUE select RT_USING_MESSAGEQUEUE_PRIORITY select RT_USING_DFS_MQUEUE default n + help + Enable POSIX message queues for IPC. + + Provides POSIX message queue APIs: + - mq_open(): Open/create message queue + - mq_send()/mq_receive(): Send/receive messages + - mq_timedsend()/mq_timedreceive(): With timeout + - mq_notify(): Async notification + - mq_getattr()/mq_setattr(): Queue attributes + + Features: + - Priority-based message delivery + - Named queues (visible in /dev/mqueue) + - Blocking and non-blocking modes + - Timeout support + - Asynchronous notification + + vs. Pipes: + + Message boundaries preserved + + Priority-based delivery + + Can be used with select/poll + - More overhead per message + + Use cases: + - Process communication with priorities + - Event notification systems + - Service request queues + - RT-Smart IPC + + Requires DFS with MQUEUE support. + Enable for POSIX message queue IPC. config RT_USING_POSIX_MESSAGE_SEMAPHORE bool "Enable posix semaphore " select RT_USING_POSIX_CLOCK default n + help + Enable POSIX named and unnamed semaphores. + + Provides semaphore APIs: + - sem_init()/sem_destroy(): Unnamed semaphores + - sem_open()/sem_close()/sem_unlink(): Named semaphores + - sem_wait()/sem_trywait()/sem_timedwait(): Acquire + - sem_post(): Release + - sem_getvalue(): Get current value + + Types: + - Unnamed (memory-based): For thread synchronization + - Named (file-based): For process synchronization + + Features: + - Counting semaphore (value > 1) + - Binary semaphore (value = 0 or 1) + - Timeout support + - Non-blocking try operation + + Use cases: + - Thread/process synchronization + - Resource counting + - Producer-consumer patterns + - Mutual exclusion + + vs. Mutex: + + Can be used for signaling (sem_post from any thread) + + Counting capability + - No ownership tracking + + Enable for POSIX semaphore support. + Essential for POSIX synchronization. comment "Socket is in the 'Network' category" From fdb16a407f379d892b381f2475d5bb930414ea4e Mon Sep 17 00:00:00 2001 From: "copilot-swe-agent[bot]" <198982749+Copilot@users.noreply.github.com> Date: Mon, 17 Nov 2025 10:06:50 +0000 Subject: [PATCH 6/9] Add comprehensive help for PIC and OFW driver Kconfig files Co-authored-by: Rbb666 <64397326+Rbb666@users.noreply.github.com> --- components/drivers/ofw/Kconfig | 130 +++++++++++++++++++++++++ components/drivers/pic/Kconfig | 171 ++++++++++++++++++++++++++++++++- 2 files changed, 300 insertions(+), 1 deletion(-) diff --git a/components/drivers/ofw/Kconfig b/components/drivers/ofw/Kconfig index 5d6f12bf9fb..e893a839f62 100755 --- a/components/drivers/ofw/Kconfig +++ b/components/drivers/ofw/Kconfig @@ -6,24 +6,154 @@ menuconfig RT_USING_OFW select RT_USING_MEMBLOCK depends on RT_USING_DM default n + help + Enable Open Firmware (Device Tree) support. + + OFW/Device Tree provides hardware description separate from code: + - Flattened Device Tree (FDT/DTB) parsing + - Hardware discovery and configuration + - Platform-independent device drivers + - Runtime hardware detection + + Features: + - Standard device tree bindings + - Property parsing and access + - Node traversal and searching + - Phandle reference resolution + - Address translation + - Interrupt mapping + + Benefits: + - Single kernel binary for multiple boards + - Easier board porting (just change DTB) + - Better hardware abstraction + - Industry-standard hardware description + + Use cases: + - ARM/RISC-V systems with complex hardware + - Supporting multiple board variants + - Dynamic hardware configuration + - PCI, USB, network device enumeration + + Requires: + - RT_USING_DM (Device Model) + - Memory block allocator + - Abstract Data Types (ADT) support + + Essential for modern ARM Cortex-A and RISC-V systems. + Enable for device tree-based hardware discovery. config RT_USING_BUILTIN_FDT bool "Using builtin fdt in kernel" depends on RT_USING_OFW default n + help + Embed Flattened Device Tree (FDT) binary into kernel image. + + When enabled: + - DTB file linked into kernel binary + - No need for bootloader to pass DTB + - DTB always available at boot + + Advantages: + + Simpler boot process + + No DTB location dependencies + + Guaranteed DTB availability + + Disadvantages: + - Larger kernel image + - Must rebuild kernel to change DTB + - Less flexible than bootloader-provided DTB + + Typical use: + - Systems without proper bootloader + - Debugging and development + - Single-board configurations + + Alternative: Have bootloader pass DTB address to kernel. + + Enable for embedded DTB in kernel image. config RT_BUILTIN_FDT_PATH string "Builtin fdt path, will rebuild if have dts" depends on RT_USING_BUILTIN_FDT default "rtthread.dtb" + help + Path to the compiled Device Tree Blob (DTB) file to embed. + + Default: "rtthread.dtb" + + This file is included in the kernel binary during linking. + + Workflow: + 1. Write device tree source (.dts file) + 2. Compile to DTB: dtc -I dts -O dtb -o rtthread.dtb rtthread.dts + 3. Set this path to the DTB location + 4. Rebuild kernel (DTB will be embedded) + + Path can be: + - Relative to build directory + - Absolute path + + Kernel will automatically rebuild if DTS changes (if build system configured). config RT_FDT_EARLYCON_MSG_SIZE int "Earlycon message buffer size (KB)" depends on RT_USING_OFW default 128 + help + Size of early console message buffer in kilobytes. + + Default: 128 KB + + Early console (earlycon) provides debug output before full console initialization: + - Available during early boot + - Before full UART driver loads + - Critical for debugging boot failures + + Buffer stores messages when: + - Console not yet available + - Output faster than transmission + + Larger buffer: + + More boot messages captured + + Better for verbose debugging + - More memory usage + + Smaller buffer: + + Less memory overhead + - May lose early messages + + Increase for detailed boot debugging. + Decrease to save memory if earlycon not critical. config RT_USING_OFW_BUS_RANGES_NUMBER int "Max bus ranges number" depends on RT_USING_OFW default 8 if ARCH_CPU_64BIT default 4 + help + Maximum number of bus address ranges for device tree translation. + + Default: + - 64-bit systems: 8 ranges + - 32-bit systems: 4 ranges + + Bus ranges define address space mappings: + - CPU address to device bus address + - PCI memory/IO spaces + - Different bus protocols (AHB, APB, AXI) + + Each range describes a memory window mapping. + + Typical usage: + - PCI: 2-3 ranges (prefetchable mem, non-prefetchable mem, I/O) + - Complex SoCs: 4-8 ranges for different buses + + Increase for: + - Complex bus hierarchies + - Multiple PCI buses + - Systems with many address spaces + + Each range uses ~32-48 bytes of memory. + Set based on your SoC's bus complexity. diff --git a/components/drivers/pic/Kconfig b/components/drivers/pic/Kconfig index 448818fab7c..d04942e7488 100755 --- a/components/drivers/pic/Kconfig +++ b/components/drivers/pic/Kconfig @@ -4,6 +4,33 @@ menuconfig RT_USING_PIC select RT_USING_ADT_BITMAP depends on RT_USING_DM default n + help + Enable Platform Interrupt Controller (PIC) framework. + + PIC provides unified interrupt controller abstraction for: + - ARM GIC (Generic Interrupt Controller) v1/v2/v3 + - Platform-specific interrupt controllers + - MSI/MSI-X (Message Signaled Interrupts) + - Interrupt hierarchy and cascading + + Features: + - Device model integration + - Device tree support (OFW) + - Multiple interrupt controller support + - Interrupt routing and affinity + - Statistics and profiling + + Use cases: + - ARM Cortex-A systems with GIC + - SMP systems requiring interrupt affinity + - Systems using device tree + - Complex interrupt hierarchies + + Requires: + - RT_USING_DM (Device Model) + - Abstract Data Types (ADT) support + + Enable for advanced interrupt management with GIC or complex IRQ routing. config RT_USING_PIC_STATISTICS bool "Enable ISR execution time statistics" @@ -11,35 +38,153 @@ config RT_USING_PIC_STATISTICS depends on RT_USING_KTIME depends on RT_USING_INTERRUPT_INFO default n + help + Enable interrupt service routine (ISR) execution time tracking. + + Provides statistics for each interrupt: + - Total execution time + - Minimum/maximum execution time + - Average execution time + - Interrupt count + + Benefits: + - Performance profiling + - Identify slow interrupt handlers + - Optimize ISR performance + - Debug interrupt latency issues + + Requirements: + - KTIME for high-resolution timing + - RT_USING_INTERRUPT_INFO for interrupt tracking + + Overhead: + - Minimal per-interrupt timing overhead + - Memory for statistics (~40 bytes per IRQ) + + Enable for interrupt performance analysis. + Disable in production to save memory and overhead. config MAX_HANDLERS int "IRQ max handlers" depends on RT_USING_PIC range 1 4294967294 default 256 + help + Maximum number of interrupt handlers supported by PIC. + + Default: 256 handlers + + This limits the total number of IRQ lines the system can handle. + + Typical values: + - Small systems: 64-128 IRQs + - Medium systems: 256-512 IRQs + - Large systems: 512-1024 IRQs + + Memory usage: ~16-32 bytes per handler slot + + Set based on your SoC's interrupt controller capabilities. + Check GIC documentation for maximum SPIs (Shared Peripheral Interrupts). config RT_PIC_ARM_GIC bool "ARM GICv2/v1" depends on RT_USING_PIC select RT_USING_OFW default n + help + Enable ARM Generic Interrupt Controller version 1/2 (GICv1/GICv2). + + GICv2 features: + - Up to 1020 interrupt sources + - Support for SGIs (Software Generated Interrupts) + - Support for PPIs (Private Peripheral Interrupts) + - Support for SPIs (Shared Peripheral Interrupts) + - CPU interfaces for each core + - Distributor for routing interrupts + + Used in: + - ARM Cortex-A5/A7/A8/A9/A15/A17 + - Many ARM-based SoCs + + Requires device tree (OFW) for configuration. + + Enable for ARM Cortex-A systems with GICv2. config RT_PIC_ARM_GIC_V2M bool "ARM GIC V2M" if RT_PIC_ARM_GIC && RT_PCI_MSI depends on RT_USING_OFW default n + help + Enable GICv2m MSI (Message Signaled Interrupts) support. + + GICv2m provides: + - MSI support for GICv2 (which lacks native MSI) + - PCIe device interrupt handling + - Doorbell-style interrupt delivery + + Allows PCIe devices to use MSI with GICv2. + + Requirements: + - RT_PIC_ARM_GIC enabled + - RT_PCI_MSI for PCI MSI support + - Device tree configuration + + Enable for PCIe systems with GICv2 requiring MSI support. config RT_PIC_ARM_GIC_V3 bool "ARM GICv3" depends on RT_USING_PIC select RT_USING_OFW default n + help + Enable ARM Generic Interrupt Controller version 3 (GICv3). + + GICv3 enhancements over GICv2: + - Better scalability (supports more cores) + - System register access (no memory-mapped CPU interface) + - Affinity routing for flexible interrupt routing + - Locality-specific peripheral interrupts (LPI) + - ITS (Interrupt Translation Service) for MSI + - Support for GICv4 virtualization extensions + + Used in: + - ARM Cortex-A53/A55/A57/A72/A73/A76 + - ARMv8 and ARMv9 systems + - Modern ARM SoCs + + Requires device tree (OFW) for configuration. + + Enable for ARM Cortex-A systems with GICv3. config RT_PIC_ARM_GIC_V3_ITS bool "ARM GICv3 ITS (Interrupt Translation Service)" if RT_PIC_ARM_GIC_V3 && RT_PCI_MSI depends on RT_USING_OFW select RT_USING_ADT_REF default n + help + Enable GICv3 ITS for MSI/MSI-X support. + + ITS (Interrupt Translation Service) provides: + - Native MSI support for PCIe and other devices + - LPI (Locality-specific Peripheral Interrupts) management + - Efficient interrupt routing for thousands of devices + - Scalable to large systems + + Features: + - Translates MSI writes to LPIs + - Device and interrupt ID management + - Interrupt collection for CPU targeting + + Required for: + - PCIe MSI/MSI-X on GICv3 + - Large-scale systems with many devices + - Modern ARM servers and complex SoCs + + Memory overhead: + - ITS tables for device/interrupt mapping + - LPI configuration tables + + Enable for GICv3 systems with PCIe requiring MSI support. config RT_PIC_ARM_GIC_V3_ITS_IRQ_MAX int "IRQ maximum used" @@ -47,7 +192,23 @@ config RT_PIC_ARM_GIC_V3_ITS_IRQ_MAX default 127 if ARCH_CPU_64BIT default 63 help - Recommended to be based on the bit length (full bits) of maximum usage. + Maximum number of ITS-managed LPIs (Locality-specific Peripheral Interrupts). + + Recommended to be based on the bit length (full bits) of maximum usage. + + Default values: + - 64-bit systems: 127 (uses 7 bits) + - 32-bit systems: 63 (uses 6 bits) + + LPI IDs typically start from 8192 and can go very high. + This setting affects ITS table allocation. + + Increase for: + - Systems with many PCIe devices + - MSI-X devices using multiple vectors + + Each LPI uses memory in ITS configuration tables. + Set based on actual device count to balance memory usage. config RT_PIC_ARM_GIC_MAX_NR int @@ -55,6 +216,14 @@ config RT_PIC_ARM_GIC_MAX_NR depends on RT_PIC_ARM_GIC default 2 if SOC_REALVIEW default 1 + help + Maximum number of GIC instances in the system. + + Most systems have 1 GIC. + Some systems may have cascaded GICs or multiple interrupt controllers. + + Automatically configured based on SoC type. + Users typically don't need to modify this. if RT_USING_PIC osource "$(SOC_DM_PIC_DIR)/Kconfig" From 7179ab2e03daadfedab79347481440417a4f7dac Mon Sep 17 00:00:00 2001 From: ruanqiuqiu <1364421550@qq.com> Date: Fri, 2 Jan 2026 12:00:21 +0800 Subject: [PATCH 7/9] =?UTF-8?q?[Feature]=20=E5=AE=8C=E5=96=84components\dr?= =?UTF-8?q?ivers=E7=9B=AE=E5=BD=95=E4=B8=8BKconfig=E7=9A=84help=E6=8F=90?= =?UTF-8?q?=E7=A4=BA?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- components/drivers/Kconfig | 4 + components/drivers/ata/Kconfig | 17 ++++ components/drivers/audio/Kconfig | 19 ++++ components/drivers/audio/utest/Kconfig | 6 +- components/drivers/block/Kconfig | 5 + components/drivers/block/partitions/Kconfig | 11 ++ components/drivers/clk/Kconfig | 9 ++ components/drivers/core/utest/Kconfig | 4 + components/drivers/dma/Kconfig | 7 ++ components/drivers/graphic/Kconfig | 5 + components/drivers/hwcrypto/Kconfig | 107 ++++++++++++++++++++ components/drivers/hwtimer/Kconfig | 11 ++ components/drivers/i2c/Kconfig | 55 ++++++++++ components/drivers/ipc/Kconfig | 18 ++++ components/drivers/ipc/utest/Kconfig | 6 ++ components/drivers/ktime/Kconfig | 4 + components/drivers/led/Kconfig | 12 +++ components/drivers/mailbox/Kconfig | 12 +++ components/drivers/mfd/Kconfig | 9 ++ components/drivers/misc/Kconfig | 28 +++++ components/drivers/mtd/Kconfig | 10 ++ components/drivers/nvme/Kconfig | 12 +++ components/drivers/pci/host/Kconfig | 7 ++ components/drivers/pci/host/dw/Kconfig | 10 ++ components/drivers/phy/Kconfig | 8 ++ components/drivers/pin/Kconfig | 5 + components/drivers/pinctrl/Kconfig | 5 + components/drivers/pm/Kconfig | 25 +++++ components/drivers/regulator/Kconfig | 26 +++++ components/drivers/reset/Kconfig | 16 +++ components/drivers/rtc/Kconfig | 45 ++++++++ components/drivers/scsi/Kconfig | 10 ++ components/drivers/sdio/Kconfig | 21 ++++ components/drivers/sensor/Kconfig | 10 ++ components/drivers/serial/Kconfig | 18 ++++ components/drivers/serial/utest/Kconfig | 22 +++- components/drivers/smp_call/utest/Kconfig | 2 + components/drivers/spi/Kconfig | 93 +++++++++++++++-- components/drivers/thermal/Kconfig | 7 ++ components/drivers/touch/Kconfig | 6 ++ components/drivers/usb/Kconfig | 7 ++ components/drivers/virtio/Kconfig | 22 ++++ components/drivers/watchdog/Kconfig | 28 +++++ components/drivers/wlan/Kconfig | 69 +++++++++++++ 44 files changed, 825 insertions(+), 8 deletions(-) diff --git a/components/drivers/Kconfig b/components/drivers/Kconfig index 3ffa4c3f83b..e91d8d29c4f 100755 --- a/components/drivers/Kconfig +++ b/components/drivers/Kconfig @@ -1,4 +1,8 @@ menu "Device Drivers" + help + Select which RT-Thread driver stacks are built into the firmware. Each + submenu groups related peripherals (IPC, storage, networking, etc.) and + exposes their own configuration knobs. rsource "core/Kconfig" rsource "ipc/Kconfig" diff --git a/components/drivers/ata/Kconfig b/components/drivers/ata/Kconfig index 4b5cee5627c..8b034f87b67 100644 --- a/components/drivers/ata/Kconfig +++ b/components/drivers/ata/Kconfig @@ -4,18 +4,35 @@ menuconfig RT_USING_ATA depends on RT_USING_BLK depends on RT_USING_DMA default n + help + Enable the ATA core so AHCI/legacy controllers can register themselves in + the driver model, allocate DMA resources, and expose block devices to the + RT-Thread block layer. Select this only on SoCs/boards that actually wire + SATA ports because it pulls in the SCSI translation layer and requires DMA + support. When disabled, no SATA disks will be enumerated. config RT_ATA_AHCI bool "Advanced Host Controller Interface (AHCI)" depends on RT_USING_ATA depends on RT_USING_SCSI default y + help + Build the generic AHCI driver that maps HBA registers (ports, command list, + FIS receive, etc.), handles NCQ, and bridges each detected SATA device to + the RT-SCSI mid-layer so filesystems can treat them like disks. Enable it + whenever your SoC implements a standards-compliant AHCI core; disable if + you rely on a vendor-specific ATA engine. config RT_ATA_AHCI_PCI bool "AHCI support on PCI bus" depends on RT_ATA_AHCI depends on RT_USING_PCI default n + help + Allow the AHCI driver to bind to PCI devices and fetch resources via PCI + config space. Required on PC-class hardware where the AHCI HBA is behind + PCI/PCIe; boards with platform AHCI (non-PCI) can leave this off to save a + little code. if RT_USING_ATA osource "$(SOC_DM_ATA_DIR)/Kconfig" diff --git a/components/drivers/audio/Kconfig b/components/drivers/audio/Kconfig index 48770ac0f0a..f028a053f3b 100644 --- a/components/drivers/audio/Kconfig +++ b/components/drivers/audio/Kconfig @@ -1,18 +1,37 @@ config RT_USING_AUDIO bool "Using Audio device drivers" default n + help + Enable the RT-Thread audio framework so playback/record devices may be + registered, DMA pipes allocated, and ALSA-like controls exposed via + `rt_audio_*` APIs. Choose this whenever your board has I2S/TDM codecs or + PDM microphones; disable it on MCU builds that do not process audio data. if RT_USING_AUDIO config RT_AUDIO_REPLAY_MP_BLOCK_SIZE int "Replay memory pool block size" default 4096 + help + Size in bytes for each block inside the replay memory pool used by + `dev_audio.c` to stage PCM data before pushing it to DMA. Larger + values increase latency but reduce IRQ pressure; shrink it when + RAM is tight and the codec tolerates smaller bursts. config RT_AUDIO_REPLAY_MP_BLOCK_COUNT int "Replay memory pool block count" default 2 + help + Number of replay memory pool blocks. Raising this allows more + outstanding audio buffers (useful for long DMA transfers) but + consumes additional RAM = `BLOCK_SIZE * COUNT`. config RT_AUDIO_RECORD_PIPE_SIZE int "Record pipe size" default 2048 + help + Size of the ring buffer used to capture samples before user-space + reads them. Increase this to prevent overflow when the recorder + callback runs slower than the DMA completion interrupt; reduce it + on memory constrained platforms. endif diff --git a/components/drivers/audio/utest/Kconfig b/components/drivers/audio/utest/Kconfig index 36922b390c2..aa06c6745a8 100644 --- a/components/drivers/audio/utest/Kconfig +++ b/components/drivers/audio/utest/Kconfig @@ -2,4 +2,8 @@ if RT_USING_AUDIO config RT_UTEST_USING_AUDIO_DRIVER bool "Audio Test" default n -endif \ No newline at end of file + help + Build the audio driver utest cases which stream synthetic data through + the replay/record paths. Enable only when running the RT-Thread unit + test suite; it adds test hooks that are not required in production. +endif diff --git a/components/drivers/block/Kconfig b/components/drivers/block/Kconfig index 865df5e1241..68b3b3587f9 100644 --- a/components/drivers/block/Kconfig +++ b/components/drivers/block/Kconfig @@ -1,6 +1,11 @@ menuconfig RT_USING_BLK bool "Using Block device drivers" default n + help + Enable the generic block-device infrastructure so storage controllers can + register disks/partitions and the RT-Thread DFS layer can mount them. + Almost every filesystem, SDIO, SATA or NAND driver depends on this. Turn + it off only on firmware builds that never interact with block media. if RT_USING_BLK rsource "partitions/Kconfig" diff --git a/components/drivers/block/partitions/Kconfig b/components/drivers/block/partitions/Kconfig index 6df5e715f55..0705ec737b6 100644 --- a/components/drivers/block/partitions/Kconfig +++ b/components/drivers/block/partitions/Kconfig @@ -4,9 +4,20 @@ config RT_BLK_PARTITION_DFS bool "DFS Partition support" depends on RT_USING_DFS default y + help + Parse the RT-Thread DFS partition table (vfs_part) so a single block + device can be split into multiple named logical volumes. Enable this when + you use the DFS tooling or `mkpart` scripts to carve flash storage; it is + harmless to keep on because it only activates when the table signature is + present. config RT_BLK_PARTITION_EFI bool "EFI Globally Unique Identifier (GUID) Partition support" default y + help + Add GUID Partition Table (GPT) support, allowing disks formatted on + modern PCs to be recognized. Required for SATA/NVMe/USB disks that use + GPT; you may disable it on very small targets that only boot from DFS + partitions to save a few kilobytes. endmenu diff --git a/components/drivers/clk/Kconfig b/components/drivers/clk/Kconfig index c13ccbf2591..7fb19e6a5e2 100755 --- a/components/drivers/clk/Kconfig +++ b/components/drivers/clk/Kconfig @@ -3,6 +3,15 @@ menuconfig RT_USING_CLK depends on RT_USING_DM select RT_USING_ADT_REF default y + help + Enable the common clock framework so SoC clock providers can register + themselves and consumers can obtain `struct rt_clk` handles to manage + gate, mux and divider trees. This is required by most complex drivers + (MMC, Ethernet, display) because they explicitly prepare and enable their + input clocks before accessing hardware. The framework relies on the DM + bus and device tree clock references, so disable it only on the smallest + MCUs where every peripheral runs off the same fixed clock and no driver + ever calls into the clock API. if RT_USING_CLK osource "$(SOC_DM_CLK_DIR)/Kconfig" diff --git a/components/drivers/core/utest/Kconfig b/components/drivers/core/utest/Kconfig index f39fa9c8a03..4e18a6f7d7d 100644 --- a/components/drivers/core/utest/Kconfig +++ b/components/drivers/core/utest/Kconfig @@ -1,3 +1,7 @@ config RT_UTEST_DRIVERS_CORE bool "Drivers Core Test" default n + help + Build the unit tests that exercise the driver-core (device model) APIs, + ensuring registration/probing flows behave as expected. Enable only when + running the RT-Thread utest suite; production images should leave it off. diff --git a/components/drivers/dma/Kconfig b/components/drivers/dma/Kconfig index 7bf9d5930f4..7f347452ecc 100644 --- a/components/drivers/dma/Kconfig +++ b/components/drivers/dma/Kconfig @@ -4,6 +4,13 @@ menuconfig RT_USING_DMA select RT_USING_ADT select RT_USING_ADT_BITMAP default n + help + Enable the DMA framework so DM-aware SoC drivers can request DMA channels, + submit descriptors, and share controller instances that are described in + the device tree. This pulls in the generic DMA core (`dma.c`) and the pool + allocator used by slave/peripheral clients. Select it whenever your board + has DMA-capable peripherals (MMC, SPI, audio, etc.) that need offloading; + leave it disabled only on targets without DMA hardware to save code size. if RT_USING_DMA osource "$(SOC_DM_DMA_DIR)/Kconfig" diff --git a/components/drivers/graphic/Kconfig b/components/drivers/graphic/Kconfig index 5ce0835743e..1c0abcb0cd0 100644 --- a/components/drivers/graphic/Kconfig +++ b/components/drivers/graphic/Kconfig @@ -1,3 +1,8 @@ config RT_USING_LCD bool "Using LCD graphic drivers" default n + help + Enable the RT-Thread LCD/graphics driver framework so display controllers + can expose framebuffers or panel pipelines. This pulls in the drawing + helpers used by GUI packages; select it whenever your board has an LCD or + RGB/MIPI panel. Disable it on headless builds to save code size. diff --git a/components/drivers/hwcrypto/Kconfig b/components/drivers/hwcrypto/Kconfig index e5748c998d7..4e0c61d1492 100644 --- a/components/drivers/hwcrypto/Kconfig +++ b/components/drivers/hwcrypto/Kconfig @@ -1,165 +1,272 @@ menuconfig RT_USING_HWCRYPTO bool "Using Hardware Crypto drivers" default n + help + Enable the hardware crypto abstraction layer so SoC accelerators can + register cipher/hash/RNG engines and high-level components can route + requests through them. Select this when your platform provides AES, + HASH, RNG or big-number engines and you want to offload work from the + CPU; disable it to keep the image lean on chips without crypto IP. if RT_USING_HWCRYPTO config RT_HWCRYPTO_DEFAULT_NAME string "Hardware crypto device name" default "hwcryto" + help + Default device name announced via `rt_hwcrypto_dev_register`. You + may override it if multiple accelerators coexist or you need a + deterministic node name for auto-binding. config RT_HWCRYPTO_IV_MAX_SIZE int "IV max size" default "16" + help + Maximum initialization-vector length (bytes) allocated in the + generic session context. Set this to match the longest IV your + hardware supports (for example 16 for AES) to avoid truncation. config RT_HWCRYPTO_KEYBIT_MAX_SIZE int "Key max bit length" default 256 + help + Upper bound on key size (bits) that the framework will accept. + Increase this if your accelerator supports longer RSA/ECC keys. config RT_HWCRYPTO_USING_GCM bool "Using Hardware GCM" default n + help + Advertise AES-GCM authenticated encryption support. Only enable if + the hardware can perform GHASH + counter mode internally. config RT_HWCRYPTO_USING_AES bool "Using Hardware AES" default n + help + Enable AES cipher acceleration (key setup + block operations). You + should only turn this on when the SoC AES engine is initialized + elsewhere in BSP code. if RT_HWCRYPTO_USING_AES config RT_HWCRYPTO_USING_AES_ECB bool "Using Hardware AES ECB mode" default y + help + Allow AES ECB operations. Keep it on unless your hardware + lacks ECB (rare) or you want to trim dead code. config RT_HWCRYPTO_USING_AES_CBC bool "Using Hardware AES CBC mode" default n + help + Enable AES CBC mode helpers when the peripheral can chain IVs. config RT_HWCRYPTO_USING_AES_CFB bool "Using Hardware AES CFB mode" default n + help + Advertise AES CFB streaming cipher support if the hardware + exposes it; leave disabled otherwise. config RT_HWCRYPTO_USING_AES_CTR bool "Using Hardware AES CTR mode" default n + help + Enable AES counter mode processing for peripherals that can + increment counters internally. config RT_HWCRYPTO_USING_AES_OFB bool "Using Hardware AES OFB mode" default n + help + Provide AES OFB (output feedback) mode wrappers. Only useful + when the engine implements OFB directly. endif config RT_HWCRYPTO_USING_DES bool "Using Hardware DES" default n + help + Toggle hardware DES acceleration. DES is legacy; enable it only + for compatibility with existing protocols. if RT_HWCRYPTO_USING_DES config RT_HWCRYPTO_USING_DES_ECB bool "Using Hardware DES ECB mode" default y + help + Support DES ECB mode if the IP block offers it. config RT_HWCRYPTO_USING_DES_CBC bool "Using Hardware DES CBC mode" default n + help + Enable DES CBC helper functions when the peripheral supports + feedback chaining. endif config RT_HWCRYPTO_USING_3DES bool "Using Hardware 3DES" default n + help + Enable triple-DES acceleration (single/dual key). Required when + interacting with older security modules. if RT_HWCRYPTO_USING_3DES config RT_HWCRYPTO_USING_3DES_ECB bool "Using Hardware 3DES ECB mode" default y + help + Provide 3DES ECB support if your IP implements it. config RT_HWCRYPTO_USING_3DES_CBC bool "Using Hardware 3DES CBC mode" default n + help + Provide 3DES CBC helpers for devices that offer feedback + chaining. endif config RT_HWCRYPTO_USING_RC4 bool "Using Hardware RC4" default n + help + Enable the RC4 stream cipher hooks. Only rare legacy hardware + still implements RC4; keep disabled otherwise. config RT_HWCRYPTO_USING_MD5 bool "Using Hardware MD5" default n + help + Register MD5 digest offload support. Use this only if the SoC + exposes a hash module with MD5 capability. config RT_HWCRYPTO_USING_SHA1 bool "Using Hardware SHA1" default n + help + Enable SHA-1 hashing acceleration. SHA-1 is deprecated for secure + applications but may be required for compatibility. config RT_HWCRYPTO_USING_SHA2 bool "Using Hardware SHA2" default n + help + Turn on SHA-2 (224/256/384/512) acceleration. Select the exact + digests below to match your IP core. if RT_HWCRYPTO_USING_SHA2 config RT_HWCRYPTO_USING_SHA2_224 bool "Using Hardware SHA2_224 mode" default n + help + Provide SHA-224 digest routines if hardware supports them. config RT_HWCRYPTO_USING_SHA2_256 bool "Using Hardware SHA2_256 mode" default y + help + Enable SHA-256, the most commonly required SHA-2 variant. config RT_HWCRYPTO_USING_SHA2_384 bool "Using Hardware SHA2_384 mode" default n + help + Toggle SHA-384 support when present to support TLS-style HMAC. config RT_HWCRYPTO_USING_SHA2_512 bool "Using Hardware SHA2_512 mode" default n + help + Expose SHA-512 digest if your accelerator implements 512-bit + compression functions. endif config RT_HWCRYPTO_USING_RNG bool "Using Hardware RNG" default n + help + Enable the true/fast random number generator interface so the RNG + peripheral can feed entropy to TLS stacks or secure boot. config RT_HWCRYPTO_USING_CRC bool "Using Hardware CRC" default n + help + Expose hardware CRC units and allow selecting supported + polynomials below. Useful for communication stacks that need + high-throughput CRC calculation. if RT_HWCRYPTO_USING_CRC config RT_HWCRYPTO_USING_CRC_07 bool "Using Hardware CRC-8 0x07 polynomial" default n + help + Turn on support for the CRC-8 polynomial 0x07 (ATM/SMBus). config RT_HWCRYPTO_USING_CRC_8005 bool "Using Hardware CRC-16 0x8005 polynomial" default n + help + Enable CRC-16/IBM polynomial acceleration. config RT_HWCRYPTO_USING_CRC_1021 bool "Using Hardware CRC-16 0x1021 polynomial" default n + help + Enable CRC-16/CCITT-FALSE polynomial support. config RT_HWCRYPTO_USING_CRC_3D65 bool "Using Hardware CRC-16 0x3D65 polynomial" default n + help + Enable CRC-16/USB polynomial (0x3D65) support. config RT_HWCRYPTO_USING_CRC_04C11DB7 bool "Using Hardware CRC-32 0x04C11DB7 polynomial" default n + help + Enable CRC-32/IEEE polynomial support for Ethernet-like CRCs. endif config RT_HWCRYPTO_USING_BIGNUM bool "Using Hardware bignum" default n + help + Allow hardware accelerators to handle modular exponentiation and + other big-number math (RSA, DH, ECC). Enable when your SoC + includes a crypto accelerator with public-key instructions. if RT_HWCRYPTO_USING_BIGNUM config RT_HWCRYPTO_USING_BIGNUM_EXPTMOD bool "Using Hardware bignum expt_mod operation" default y + help + Provide modular exponentiation support (RSA decrypt/sign). config RT_HWCRYPTO_USING_BIGNUM_MULMOD bool "Using Hardware bignum mul_mod operation" default y + help + Enable modular multiplication for ECC/DH operations. config RT_HWCRYPTO_USING_BIGNUM_MUL bool "Using Hardware bignum mul operation" default n + help + Advertise raw big-number multiply support when hardware can do + wide integer multiplication. config RT_HWCRYPTO_USING_BIGNUM_ADD bool "Using Hardware bignum add operation" default n + help + Enable big-number addition helpers when provided by silicon. config RT_HWCRYPTO_USING_BIGNUM_SUB bool "Using Hardware bignum sub operation" default n + help + Expose big-number subtraction support if available. endif endif diff --git a/components/drivers/hwtimer/Kconfig b/components/drivers/hwtimer/Kconfig index a1755ba0e6e..f9c74bcf3f6 100644 --- a/components/drivers/hwtimer/Kconfig +++ b/components/drivers/hwtimer/Kconfig @@ -1,6 +1,12 @@ menuconfig RT_USING_HWTIMER bool "Using Hardware Timer device drivers" default n + help + Enable the generic hardware-timer framework so SoC timer blocks can + register themselves, expose capture/compare features, and provide high + resolution timing services beyond the system tick. Select this for chips + with general-purpose timers or watchdog-timer reuse; disable on systems + that only rely on the software tick. config RT_HWTIMER_ARM_ARCH bool "ARM ARCH Timer" @@ -8,3 +14,8 @@ config RT_HWTIMER_ARM_ARCH depends on RT_USING_HWTIMER depends on ARCH_ARM_CORTEX_A || ARCH_ARMV8 default n + help + Enable the driver for the ARM architectural timer (ARMv7-A/v8 system + counter). This maps CNTFRQ/CNTV registers into the driver-model so the + kernel can expose a precise clocksource/clockevent. Only useful on Cortex- + A/R platforms that implement the generic timer block. diff --git a/components/drivers/i2c/Kconfig b/components/drivers/i2c/Kconfig index bb4c90dba82..5a344a19a94 100644 --- a/components/drivers/i2c/Kconfig +++ b/components/drivers/i2c/Kconfig @@ -1,20 +1,40 @@ config RT_USING_I2C bool "Using I2C device drivers" default n + help + Enable the RT-Thread I2C core so both DM aware controllers and legacy bus + drivers can register `struct rt_i2c_bus_device` objects, and client + drivers can issue transfers through the unified APIs. Select this on any + board that exposes an I2C peripheral or software bit-bang bus; disable it + only if you never interface with I2C sensors/PMICs/MCUs. if RT_USING_I2C config RT_I2C_DEBUG bool "Use I2C debug message" default n + help + Print verbose I2C transaction logs (start/stop, address, data) to the + console. Helpful while debugging board bring-up, but it slows down the + bus and should remain off in production firmware. config RT_USING_I2C_BITOPS bool "Use GPIO to simulate I2C" default y + help + Build the generic bit-banging algorithm (`dev_i2c_bit_ops.c`) so + controller drivers or the software I2C backend can drive SCL/SDA pins + directly. Disable this only when every I2C controller is hardware- + assisted and you want to shave a few hundred bytes of code. if RT_USING_I2C_BITOPS config RT_I2C_BITOPS_DEBUG bool "Use simulate I2C debug message" default n + help + Emit timing-level diagnostics from the bit-bang implementation, + showing whether GPIO toggles are happening as expected. Useful to + diagnose board wiring or timing issues, but generates a lot of log + traffic and should stay disabled normally. endif menuconfig RT_USING_SOFT_I2C @@ -22,10 +42,19 @@ if RT_USING_I2C default n select RT_USING_PIN select RT_USING_I2C_BITOPS + help + Instantiate one or more fully software I2C buses backed by GPIO pins. + Each enabled bus entry below lets you choose SCL/SDA pin numbers, the + exported bus name, and bit-bang timing. Use this when the SoC lacks an + available controller but you still need to connect low-speed sensors. if RT_USING_SOFT_I2C menuconfig RT_USING_SOFT_I2C0 bool "Enable I2C0 Bus (software simulation)" default y + help + Create a software I2C bus named by `RT_SOFT_I2C0_BUS_NAME` + using the selected SCL/SDA pins. Disable it if the board does + not wire up a first soft I2C channel. if RT_USING_SOFT_I2C0 config RT_SOFT_I2C0_SCL_PIN int "SCL pin number" @@ -50,6 +79,10 @@ if RT_USING_I2C menuconfig RT_USING_SOFT_I2C1 bool "Enable I2C1 Bus (software simulation)" default y + help + Enable the second software I2C controller and configure its + pins/name/timing below when multiple bit-bang buses are wired + out on the PCB. if RT_USING_SOFT_I2C1 config RT_SOFT_I2C1_SCL_PIN int "SCL pin number" @@ -74,6 +107,10 @@ if RT_USING_I2C menuconfig RT_USING_SOFT_I2C2 bool "Enable I2C2 Bus (software simulation)" default n + help + Optional third soft I2C bus for boards that expose additional + GPIO pairs. Turn this on only if you really route the + corresponding pins. if RT_USING_SOFT_I2C2 config RT_SOFT_I2C2_SCL_PIN int "SCL pin number" @@ -98,6 +135,8 @@ if RT_USING_I2C menuconfig RT_USING_SOFT_I2C3 bool "Enable I2C3 Bus (software simulation)" default n + help + Same as above but for the fourth software I2C instance. if RT_USING_SOFT_I2C3 config RT_SOFT_I2C3_SCL_PIN int "SCL pin number" @@ -122,6 +161,9 @@ if RT_USING_I2C menuconfig RT_USING_SOFT_I2C4 bool "Enable I2C4 Bus (software simulation)" default n + help + Enable the fifth configurable bit-bang bus if more GPIO-based + channels are required. if RT_USING_SOFT_I2C4 config RT_SOFT_I2C4_SCL_PIN int "SCL pin number" @@ -146,6 +188,9 @@ if RT_USING_I2C menuconfig RT_USING_SOFT_I2C5 bool "Enable I2C5 Bus (software simulation)" default n + help + Enable the sixth configurable bit-bang bus when the hardware + exposes yet another sensor connector. if RT_USING_SOFT_I2C5 config RT_SOFT_I2C5_SCL_PIN int "SCL pin number" @@ -170,6 +215,9 @@ if RT_USING_I2C menuconfig RT_USING_SOFT_I2C6 bool "Enable I2C6 Bus (software simulation)" default n + help + Enable the seventh software bus; use only on complex boards + because each additional bus increases code/data usage. if RT_USING_SOFT_I2C6 config RT_SOFT_I2C6_SCL_PIN int "SCL pin number" @@ -194,6 +242,9 @@ if RT_USING_I2C menuconfig RT_USING_SOFT_I2C7 bool "Enable I2C7 Bus (software simulation)" default n + help + Provide an eighth configurable software bus if still more GPIO + pairs are required for isolated peripherals. if RT_USING_SOFT_I2C7 config RT_SOFT_I2C7_SCL_PIN int "SCL pin number" @@ -218,6 +269,10 @@ if RT_USING_I2C menuconfig RT_USING_SOFT_I2C8 bool "Enable I2C8 Bus (software simulation)" default n + help + Final reserved entry for a ninth soft I2C controller. Enable + it only when the design needs that many bit-bang buses; leave + disabled otherwise to save resources. if RT_USING_SOFT_I2C8 config RT_SOFT_I2C8_SCL_PIN int "SCL pin number" diff --git a/components/drivers/ipc/Kconfig b/components/drivers/ipc/Kconfig index e0411d29b48..a0a85a6739d 100644 --- a/components/drivers/ipc/Kconfig +++ b/components/drivers/ipc/Kconfig @@ -3,23 +3,41 @@ menuconfig RT_USING_DEVICE_IPC default y select RT_USING_MUTEX select RT_USING_SEMAPHORE + help + Enable the device-layer IPC helpers (pipes, message queues, workqueues) + that many drivers rely on for buffering and deferred processing. Disable + only on extremely small systems that do not load drivers needing mutex or + semaphore-based IPC primitives. if RT_USING_DEVICE_IPC config RT_UNAMED_PIPE_NUMBER int "The number of unamed pipe" default 64 + help + Maximum number of anonymous pipes that can be created at runtime. + Reduce this to save memory if your application uses few pipes. config RT_USING_SYSTEM_WORKQUEUE bool "Using system default workqueue" default n + help + Create a global system workqueue thread so drivers can defer work out + of interrupt context without allocating their own threads. if RT_USING_SYSTEM_WORKQUEUE config RT_SYSTEM_WORKQUEUE_STACKSIZE int "The stack size for system workqueue thread" default 2048 + help + Stack size in bytes for the common workqueue thread; increase when + queued jobs perform complex tasks or call into heavy subsystems. config RT_SYSTEM_WORKQUEUE_PRIORITY int "The priority level of system workqueue thread" default 23 + help + Scheduler priority assigned to the workqueue thread. Lower numbers + mean higher priority; adjust relative to other timing-sensitive + threads in your system. endif endif diff --git a/components/drivers/ipc/utest/Kconfig b/components/drivers/ipc/utest/Kconfig index 00d8c61ed9e..40a6be2be25 100644 --- a/components/drivers/ipc/utest/Kconfig +++ b/components/drivers/ipc/utest/Kconfig @@ -4,9 +4,15 @@ menu "IPC Test" config RT_UTEST_COMPLETION bool "IPC Completion Test" default n + help + Build completion primitive unit tests to verify wait/notify semantics. + Enable only when running the IPC utest suite. config RT_UTEST_WORKQUEUE bool "IPC Workqueue Test" default n + help + Compile the workqueue stress tests that schedule and cancel asynchronous + jobs. Useful for validating driver workqueue usage during development. endmenu diff --git a/components/drivers/ktime/Kconfig b/components/drivers/ktime/Kconfig index 170271c222c..b68e9e13039 100644 --- a/components/drivers/ktime/Kconfig +++ b/components/drivers/ktime/Kconfig @@ -1,3 +1,7 @@ menuconfig RT_USING_KTIME bool "Ktime: kernel time" default n + help + Enable the ktime helpers which provide high-resolution timekeeping APIs + for drivers and subsystems that need more precision than the scheduler + tick. Disable if the platform sticks to coarse `rt_tick_get()` timing. diff --git a/components/drivers/led/Kconfig b/components/drivers/led/Kconfig index 462aa0bac04..cc6bfb7b0ba 100644 --- a/components/drivers/led/Kconfig +++ b/components/drivers/led/Kconfig @@ -2,6 +2,12 @@ menuconfig RT_USING_LED bool "Using Light Emitting Diode (LED) device drivers" depends on RT_USING_DM default n + help + Enable the LED framework so on-board indicators described in device tree + can be registered and controlled via `rt_led_set_state()` (on/off/blink). + The core parses LED nodes, exports sysfs-like control via IPC, and lets + other subsystems (for example triggers) manipulate them. Disable it when + the hardware has no controllable LEDs. config RT_LED_GPIO bool "GPIO connected LEDs Support" @@ -9,6 +15,12 @@ config RT_LED_GPIO depends on RT_USING_PINCTRL depends on RT_USING_OFW default n + help + Provide the GPIO-backed LED driver that maps each `leds` device-tree node + to a pin, honours `default-state`/`default-trigger`, and optionally + applies pinctrl states per LED. Enable this for the common case where + LEDs are tied directly to GPIOs; leave disabled if LEDs are driven through + a different bus (I2C expanders, PMICs, etc.). if RT_USING_LED osource "$(SOC_DM_LED_DIR)/Kconfig" diff --git a/components/drivers/mailbox/Kconfig b/components/drivers/mailbox/Kconfig index 9531d3a2dd3..b2387224899 100644 --- a/components/drivers/mailbox/Kconfig +++ b/components/drivers/mailbox/Kconfig @@ -3,11 +3,23 @@ menuconfig RT_USING_MBOX depends on RT_USING_DM depends on RT_USING_OFW default n + help + Enable the mailbox framework so multi-core SoCs or remote processors can + exchange messages via hardware mailbox/FIFO IP. The core registers mailbox + controllers described in device tree, manages channel timeouts, and + exposes asynchronous send/receive callbacks to drivers such as RPMsg or + audio DSP clients. Disable it only when the SoC lacks mailbox hardware. config RT_MBOX_PIC bool "RT-Thread PIC Mailbox" depends on RT_USING_MBOX default y + help + Build the PIC mailbox controller driver which exposes RT-Thread's + platform interrupt controller mailboxes through the common API. Select it + when the firmware runs on platforms where the PIC provides mailbox + registers (for example Sophgo SG2042); turning it off prevents those DTS + nodes from binding. if RT_USING_MBOX osource "$(SOC_DM_MBOX_DIR)/Kconfig" diff --git a/components/drivers/mfd/Kconfig b/components/drivers/mfd/Kconfig index 0b12ca42ba5..daeab7a52c8 100644 --- a/components/drivers/mfd/Kconfig +++ b/components/drivers/mfd/Kconfig @@ -2,9 +2,18 @@ menuconfig RT_USING_MFD bool "Using Multifunction device drivers" depends on RT_USING_DM default n + help + Enable the MFD framework so composite chips (PMICs, southbridges, etc.) + described in device tree can expose multiple child devices (GPIO, RTC, + regulator…) through the driver model. Required when your board uses such + multifunction ICs; disable to save code if every device is standalone. config RT_MFD_SYSCON bool "System Controller Register R/W" depends on RT_USING_MFD depends on RT_USING_OFW default y + help + Provide the syscon helper that maps register banks described by + `syscon`/`simple-mfd` nodes and allows other drivers to read/write them. + Keep enabled on SoCs whose reset/clock/PHY drivers access syscon regions. diff --git a/components/drivers/misc/Kconfig b/components/drivers/misc/Kconfig index fd092760991..aa57dddcad6 100644 --- a/components/drivers/misc/Kconfig +++ b/components/drivers/misc/Kconfig @@ -1,37 +1,65 @@ config RT_USING_ADC bool "Using ADC device drivers" default n + help + Enable analog-to-digital converter framework support so MCU ADC channels + can be exposed through the RT-Thread device interface. Required when your + application samples voltages or sensors via ADC. config RT_USING_DAC bool "Using DAC device drivers" default n + help + Build the digital-to-analog converter driver layer. Enable if you need to + output analog voltages or audio waveforms through DAC peripherals. config RT_USING_NULL bool "Using NULL device drivers" default n + help + Register a `/dev/null` style sink device that discards written data and + always returns EOF when read. Handy for tests or redirecting logs. config RT_USING_ZERO bool "Using ZERO device drivers" default n + help + Provide a `/dev/zero` like device that returns zero-filled buffers on + reads. Useful for quick buffer initialization without touching memory. config RT_USING_RANDOM bool "Using RANDOM device drivers" default n + help + Expose a `/dev/random` source backed by software entropy or hardware RNG. + Enable only when you supply a randomness provider. config RT_USING_PWM bool "Using PWM device drivers" default n + help + Enable the Pulse-Width Modulation driver layer so timers configured as PWM + can control motors, LEDs, etc. Required by many BSPs with PWM outputs. config RT_USING_PULSE_ENCODER bool "Using PULSE ENCODER device drivers" default n + help + Build the pulse encoder (quadrature decoder) driver so incremental + encoders can be read through the RT-Thread device API. config RT_USING_INPUT_CAPTURE bool "Using INPUT CAPTURE device drivers" default n + help + Enable input capture support, letting timers timestamp external pulses for + frequency/period measurements. if RT_USING_INPUT_CAPTURE config RT_INPUT_CAPTURE_RB_SIZE int "Set input capture ringbuffer size" default 100 + help + Number of samples buffered per capture channel. Increase to avoid data + loss when interrupts arrive faster than the consumer drains them. endif diff --git a/components/drivers/mtd/Kconfig b/components/drivers/mtd/Kconfig index 384d002833e..7448596d2fd 100644 --- a/components/drivers/mtd/Kconfig +++ b/components/drivers/mtd/Kconfig @@ -1,13 +1,23 @@ config RT_USING_MTD_NOR bool "Using MTD Nor Flash device drivers" default n + help + Enable the Memory Technology Device (MTD) NOR layer so SPI/QSPI or + parallel NOR flashes can be registered and exposed to the filesystem or + FAL. Select this when your design stores code/data in NOR. config RT_USING_MTD_NAND bool "Using MTD Nand Flash device drivers" default n + help + Enable NAND flash management (bad-block handling, ECC hooks, partitions). + Requires platform-specific ECC support and is needed for raw NAND storage. if RT_USING_MTD_NAND config RT_MTD_NAND_DEBUG bool "Enable MTD Nand operations debug information" default n + help + Print verbose details for each NAND read/write/erase operation to aid + bring-up. Disable in production to avoid large log output. endif diff --git a/components/drivers/nvme/Kconfig b/components/drivers/nvme/Kconfig index 83c731c0af9..1e993484558 100644 --- a/components/drivers/nvme/Kconfig +++ b/components/drivers/nvme/Kconfig @@ -4,6 +4,11 @@ menuconfig RT_USING_NVME depends on RT_USING_BLK depends on RT_USING_DMA default n + help + Enable the NVMe driver stack so PCIe-connected SSDs can be discovered, + command queues created, and block devices exported through the block + layer. Requires DMA and the driver model; disable if your platform lacks + NVMe hardware. config RT_USING_NVME_IO_QUEUE int "Number of I/O Command queue" @@ -11,12 +16,19 @@ config RT_USING_NVME_IO_QUEUE default 2 if RT_THREAD_PRIORITY_8 default 4 if RT_THREAD_PRIORITY_32 default 8 if RT_THREAD_PRIORITY_256 + help + Set how many submission/completion queue pairs to create for NVMe I/O. + More queues improve parallelism on multicore systems but consume more DMA + memory and interrupts. config RT_NVME_PCI bool "NVME support on PCI bus" depends on RT_USING_NVME depends on RT_USING_PCI default y + help + Allow the driver to bind to NVMe controllers discovered via PCI/PCIe. + Disable only for non-PCI environments (for example, custom interconnects). if RT_USING_NVME osource "$(SOC_DM_NVME_DIR)/Kconfig" diff --git a/components/drivers/pci/host/Kconfig b/components/drivers/pci/host/Kconfig index 0b7cd2662a6..2c6dbba5521 100644 --- a/components/drivers/pci/host/Kconfig +++ b/components/drivers/pci/host/Kconfig @@ -2,12 +2,19 @@ config RT_PCI_HOST_COMMON bool "Common PCI host controller" depends on RT_PCI_ECAM default y + help + Include shared helper code for PCI host controllers that follow the ECAM + (Enhanced Configuration Access Mechanism) layout. Required by most PCIe + root complexes. config RT_PCI_HOST_GENERIC bool "Generic PCI host controller" depends on RT_PCI_ECAM select RT_PCI_HOST_COMMON default y + help + Build the minimal ECAM-based PCI host driver that can enumerate devices at + a fixed base address. Useful for QEMU/virt platforms or simple SoCs. rsource "dw/Kconfig" diff --git a/components/drivers/pci/host/dw/Kconfig b/components/drivers/pci/host/dw/Kconfig index e76011b3871..1b20ba93821 100644 --- a/components/drivers/pci/host/dw/Kconfig +++ b/components/drivers/pci/host/dw/Kconfig @@ -3,11 +3,21 @@ config RT_PCI_DW depends on RT_MFD_SYSCON depends on RT_USING_DMA default n + help + Enable support for Synopsys DesignWare PCIe controllers that appear in + many SoCs. This pulls in common init logic that handles PHY resets, ATU + windows, and DMA operations shared between host and endpoint modes. config RT_PCI_DW_HOST bool depends on RT_PCI_DW + help + Build the host-mode glue so the DesignWare IP enumerates downstream PCIe + devices. Usually selected by SoC-specific configs targeting host mode. config RT_PCI_DW_EP bool depends on RT_PCI_DW + help + Build the endpoint-mode glue so the DesignWare controller can act as a PCIe + endpoint exposing its own BARs to a host. diff --git a/components/drivers/phy/Kconfig b/components/drivers/phy/Kconfig index 92dcba8c4e3..14158febfcd 100644 --- a/components/drivers/phy/Kconfig +++ b/components/drivers/phy/Kconfig @@ -1,8 +1,16 @@ config RT_USING_PHY bool "Using ethernet phy device drivers" default n + help + Enable the Ethernet PHY framework so MAC drivers can negotiate link state + via MII/MDIO and apply vendor-specific fixes. Required when using RMII/RGMII + external PHYs. config RT_USING_PHY_V2 bool "Using phy device and mii bus v2" depends on !RT_USING_PHY default n + help + Opt into the newer PHY/MDIO stack (version 2) which redesigns the PHY bus + representation. Only enable this when migrating to the new API; it is + mutually exclusive with the legacy PHY support. diff --git a/components/drivers/pin/Kconfig b/components/drivers/pin/Kconfig index 2520897834b..1c4ec556ba6 100755 --- a/components/drivers/pin/Kconfig +++ b/components/drivers/pin/Kconfig @@ -1,6 +1,11 @@ menuconfig RT_USING_PIN bool "Using Generic GPIO device drivers" default y + help + Enable the generic GPIO/pin driver interface so BSPs can expose pin mode, + read/write, and interrupt capabilities through `rt_pin_*` APIs. Most + drivers depend on this; disable only when building extremely tiny images + with no GPIO control. if RT_USING_PIN osource "$(SOC_DM_PIN_DIR)/Kconfig" diff --git a/components/drivers/pinctrl/Kconfig b/components/drivers/pinctrl/Kconfig index 536049b1b58..938543be4b4 100644 --- a/components/drivers/pinctrl/Kconfig +++ b/components/drivers/pinctrl/Kconfig @@ -3,6 +3,11 @@ menuconfig RT_USING_PINCTRL depends on RT_USING_DM depends on RT_USING_PIN default n + help + Enable the pinctrl framework so pin multiplexing/state tables from the + device tree can be applied to peripherals (I2C, SPI, LEDs, etc.). Needed + on SoCs where GPIOs share multiple alternate functions; disable on simple + MCUs where pins have fixed roles. if RT_USING_PINCTRL osource "$(SOC_DM_PINCTRL_DIR)/Kconfig" diff --git a/components/drivers/pm/Kconfig b/components/drivers/pm/Kconfig index 0ed83510d49..b4f0418a5a3 100644 --- a/components/drivers/pm/Kconfig +++ b/components/drivers/pm/Kconfig @@ -1,39 +1,64 @@ config RT_USING_PM bool "Using Power Management device drivers" default n + help + Enable the system-level power management framework which coordinates + suspend/resume, tickless idle, and device low-power states. Required when + implementing sleep modes beyond simple tick suppression. if RT_USING_PM config PM_TICKLESS_THRESHOLD_TIME int "PM tickless threashold time" default 2 + help + Minimum idle duration (in milliseconds) before the PM core enters + tickless mode. Tune based on wake-up latency vs power savings. config PM_USING_CUSTOM_CONFIG bool "PM using custom pm config" default n + help + Allow BSPs to provide custom PM policy hooks instead of the stock + configuration. config PM_ENABLE_DEBUG bool "PM Enable Debug" default n + help + Print suspend/resume decisions and timing for debugging purposes. config PM_ENABLE_SUSPEND_SLEEP_MODE bool "PM Device suspend change sleep mode" default n + help + Permit PM to change system sleep mode dynamically when devices + suspend; requires board support. config PM_ENABLE_THRESHOLD_SLEEP_MODE bool "PM using threshold time change sleep mode" default n + help + Automatically select light/deep/standby sleep based on idle time + thresholds configured below. if PM_ENABLE_THRESHOLD_SLEEP_MODE config PM_LIGHT_THRESHOLD_TIME int "PM light mode threashold time" default 5 + help + Idle time in milliseconds required before entering light sleep. config PM_DEEP_THRESHOLD_TIME int "PM deep mode threashold time" default 20 + help + Idle duration required before requesting deep sleep. config PM_STANDBY_THRESHOLD_TIME int "PM standby mode threashold time" default 100 + help + Idle time before transitioning into standby (longest latency) + mode. Increase if standby exit is expensive. endif endif diff --git a/components/drivers/regulator/Kconfig b/components/drivers/regulator/Kconfig index 99bfdac1e86..3566660fcbf 100644 --- a/components/drivers/regulator/Kconfig +++ b/components/drivers/regulator/Kconfig @@ -4,6 +4,15 @@ menuconfig RT_USING_REGULATOR select RT_USING_ADT_REF depends on RT_USING_DM default n + help + Enable the regulator framework so power supplies described in the device + tree can be registered, referenced, and controlled at runtime. With this + selected, drivers may obtain regulators via `rt_regulator_get()`, request + enable/disable, or vote for specific voltage/current levels before their + peripherals start. The framework depends on the driver-model and ADT + parser because it walks the same device tree phandles. Disable it only + when the SoC has no controllable supplies and every peripheral is powered + permanently. config RT_REGULATOR_FIXED bool "Fixed regulator support" @@ -11,12 +20,29 @@ config RT_REGULATOR_FIXED depends on RT_USING_PIN depends on RT_USING_PINCTRL default y + help + Provide the "fixed" regulator type in which the output voltage is defined + entirely by the hardware (for example a PMIC LDO) and RT-Thread can only + toggle an optional GPIO enable pin. The driver parses standard device tree + properties such as `startup-delay-us`, `off-on-delay-us`, `enable-active- + high`, and also applies any pinctrl state before asserting the output. + Select this when the board DTS contains `regulator-fixed` nodes; it is + safe to leave enabled because it only instantiates devices that the DT + describes. config RT_REGULATOR_GPIO bool "GPIO regulator support" depends on RT_USING_REGULATOR depends on RT_USING_PIN default y + help + Allow the framework to emulate simple DAC-like regulators using GPIO banks + where each output bit selects a discrete voltage/current point. The + driver reads the `states` table from the device tree and programs the GPIO + pins accordingly, so peripheral drivers can call `set_voltage()` and let + the framework choose the closest valid entry. Enable this when your board + uses GPIO strapping to select regulator levels (common with analog muxes) + or PMIC power modes; otherwise it adds no runtime cost. if RT_USING_REGULATOR osource "$(SOC_DM_REGULATOR_DIR)/Kconfig" diff --git a/components/drivers/reset/Kconfig b/components/drivers/reset/Kconfig index ccba5757505..e3c73449482 100644 --- a/components/drivers/reset/Kconfig +++ b/components/drivers/reset/Kconfig @@ -3,11 +3,27 @@ menuconfig RT_USING_RESET depends on RT_USING_DM depends on RT_USING_OFW default n + help + Turn on the reset-controller framework that lets platform drivers acquire + reset lines by phandle, assert/deassert them, and request pulse sequences. + This mirrors the Linux-style reset subsystem and requires both the device + model and flattened device tree parser because controllers and consumers + are linked by DT properties. Enable it whenever your SoC has shareable + reset gates (RCC, PRCM, etc.) described in DTS; otherwise peripheral + drivers such as DMA or watchdog blocks cannot safely leave reset. config RT_RESET_SIMPLE bool "Simple Reset Controller Driver" depends on RT_USING_RESET default n + help + Build the generic MMIO reset controller that toggles bits inside one or + more memory-mapped registers. The driver supports active-high/-low lines, + exposes optional delay-based `reset()` callbacks, and covers many SoC + reset managers listed in its compatible table (STM32 RCC, Allwinner, + Synopsys DW, Sophgo SG2042, etc.). Select this when your DTS describes + a `reset-simple`-compatible node or when downstream controllers reuse the + same register layout; leave it disabled if you rely on a custom reset IP. if RT_USING_RESET osource "$(SOC_DM_RESET_DIR)/Kconfig" diff --git a/components/drivers/rtc/Kconfig b/components/drivers/rtc/Kconfig index 9dcf7cf529b..08ccd1cf7e1 100644 --- a/components/drivers/rtc/Kconfig +++ b/components/drivers/rtc/Kconfig @@ -1,32 +1,77 @@ config RT_USING_RTC bool "Using RTC device drivers" default n + help + Enable the RTC core so hardware real-time clocks can be registered via + `rt_hw_rtc_register`, the kernel can keep wall clock time across suspend/ + resume, and applications can query or set calendar values through the + `rtc` character device. Turn this on whenever you have a peripheral or + PMIC that supplies timestamp/backup registers referenced from the device + tree; disable it only on chips that genuinely lack RTC hardware. if RT_USING_RTC config RT_USING_ALARM bool "Using RTC alarm" default n + help + Spawn the alarm service defined in `dev_alarm.c`. The driver + creates an RT-Thread worker thread that reconciles user-space + alarms with the RTC wakeup registers, automatically reprograms + oneshot/periodic alarms, and raises callbacks when the hardware + interrupt fires. Enable this if your application needs wakeup at a + given date/time; leave it disabled to save RAM/CPU when alarms are + not used. if RT_USING_ALARM config RT_ALARM_STACK_SIZE int "stack size for alarm thread" default 2048 + help + Specify the stack size (bytes) used by the internal alarm + management thread. Increase this when alarm callbacks perform + complex logic or use libc time conversions; shrink it on very + constrained MCUs when you are sure the callbacks stay shallow. config RT_ALARM_TIMESLICE int "timeslice for alarm thread" default 5 + help + Define the timeslice (OS ticks) granted to the alarm thread + when it runs at the same priority as other time-sensitive + tasks. Lower values make the system more responsive at the + cost of additional context switches; higher values slightly + delay alarm handling under load. config RT_ALARM_PRIORITY int "priority for alarm thread" default 10 + help + RT-Thread priority (smaller numbers are higher priority) of + the alarm management thread. Choose a priority above most + application threads if you require deterministic wakeups, or + below CPU-intensive tasks when alarm latency is less critical. config RT_ALARM_USING_LOCAL_TIME bool "Using local time for the alarm calculation" default n depends on RT_USING_ALARM + help + Make the alarm service convert timestamps with `mktime()` so + alarms follow the configured local time zone instead of UTC. + Enable this when alarms must honor daylight saving or custom + offsets; otherwise keep it disabled to avoid the overhead of + repeatedly converting between UTC and local time. endif config RT_USING_SOFT_RTC bool "Using software simulation RTC device" default n + help + Build the tick-based software RTC implementation (`dev_soft_rtc`) + for boards without dedicated RTC hardware. The driver keeps time + by accumulating system ticks and stores values in RAM only, so it + resets to the compile-time default after power loss. Enable it for + simulations or low-cost MCUs that still need an `rtc` device node; + disable it when real RTC registers are available to avoid two + competing time sources. endif diff --git a/components/drivers/scsi/Kconfig b/components/drivers/scsi/Kconfig index ba221880c73..c437a13426e 100644 --- a/components/drivers/scsi/Kconfig +++ b/components/drivers/scsi/Kconfig @@ -2,18 +2,28 @@ menuconfig RT_USING_SCSI bool "Using Small Computer System Interface (SCSI)" depends on RT_USING_DM default n + help + Enable the SCSI mid-layer which translates block requests to SCSI command + packets. Needed by AHCI, USB Mass Storage, and NVMe drivers that expose + disks as SCSI devices. config RT_SCSI_SD bool "SD device on SCSI" depends on RT_USING_SCSI depends on RT_USING_BLK default y + help + Register disk-type SCSI devices (direct-access). Keep enabled unless you + intentionally drop support for SCSI disks. config RT_SCSI_CDROM bool "CD-ROM device on SCSI" depends on RT_USING_SCSI depends on RT_USING_BLK default y + help + Provide SCSI CD-ROM device emulation (read-only block devices). Disable + only if optical-style devices are never needed. if RT_USING_SCSI osource "$(SOC_DM_SCSI_DIR)/Kconfig" diff --git a/components/drivers/sdio/Kconfig b/components/drivers/sdio/Kconfig index b0c28869db8..6bcef1bcb79 100644 --- a/components/drivers/sdio/Kconfig +++ b/components/drivers/sdio/Kconfig @@ -2,31 +2,52 @@ config RT_USING_SDIO bool "Using SD/MMC device drivers" select RT_USING_BLK default n + help + Enable the SDIO/MMC host stack so SD cards and eMMC devices can be + enumerated and exposed as block devices. Requires the block layer and an + SDIO host controller driver. if RT_USING_SDIO config RT_SDIO_STACK_SIZE int "The stack size for sdio irq thread" default 512 + help + Stack size for the SDIO interrupt handler thread; increase if your + controller driver performs complex processing in IRQ context. config RT_SDIO_THREAD_PRIORITY int "The priority level value of sdio irq thread" default 15 + help + Scheduler priority assigned to the SDIO IRQ thread. config RT_MMCSD_STACK_SIZE int "The stack size for mmcsd thread" default 1024 + help + Stack size for the mmc/sd management thread that handles requests. config RT_MMCSD_THREAD_PRIORITY int "The priority level value of mmcsd thread" default 22 + help + Priority for the mmc/sd management thread; tune relative to other + storage tasks. config RT_MMCSD_MAX_PARTITION int "mmcsd max partition" default 16 + help + Maximum number of partitions to scan on an SD/MMC device. config RT_SDIO_DEBUG bool "Enable SDIO debug log output" default n + help + Print verbose SDIO/MMC driver logs for debugging. config RT_USING_SDHCI bool "Using sdhci for sd/mmc drivers" default n + help + Build the SD Host Controller Interface (SDHCI) compatible driver. + Enable when your controller follows the SDHCI specification. endif diff --git a/components/drivers/sensor/Kconfig b/components/drivers/sensor/Kconfig index 976e6a7f236..6b9541efb1c 100644 --- a/components/drivers/sensor/Kconfig +++ b/components/drivers/sensor/Kconfig @@ -2,14 +2,24 @@ config RT_USING_SENSOR bool "Using Sensor device drivers" select RT_USING_PIN default n + help + Enable the sensor framework so accelerometers, gyros, temperature sensors, + etc. can register unified data channels. Depends on GPIO for interrupt + pins. Disable if no sensors are present. if RT_USING_SENSOR config RT_USING_SENSOR_V2 bool "Enable Sensor Framework v2" default n + help + Opt in to the redesigned sensor framework (v2) that updates the device + APIs and CLI tools. Only enable if your BSP/drivers support it. config RT_USING_SENSOR_CMD bool "Using Sensor cmd" select RT_KLIBC_USING_VSNPRINTF_STANDARD if RT_USING_SENSOR_V2 default y + help + Build the shell command helpers for listing and testing sensors. Useful + during bring-up; disable to save a bit of code. endif diff --git a/components/drivers/serial/Kconfig b/components/drivers/serial/Kconfig index b031c68b6c9..d52c4b3f463 100644 --- a/components/drivers/serial/Kconfig +++ b/components/drivers/serial/Kconfig @@ -3,6 +3,9 @@ menuconfig RT_USING_SERIAL select RT_USING_DEVICE_IPC select RT_USING_DEVICE default y + help + Enable the UART/USART driver framework that backs the console and TTY + devices. Required for shell access or any serial communications. if RT_USING_SERIAL choice RT_USING_SERIAL_VERSION @@ -12,6 +15,10 @@ menuconfig RT_USING_SERIAL bool "RT_USING_SERIAL_V1" config RT_USING_SERIAL_V2 bool "RT_USING_SERIAL_V2" + help + Select between the legacy serial core (V1) and the newer buffer/ISR + design (V2). Choose V2 for advanced buffer strategies, otherwise stay + with V1 for compatibility. endchoice choice RT_USING_SERIAL_MODE @@ -22,17 +29,28 @@ menuconfig RT_USING_SERIAL bool "drop new incoming data when the buffer is full" config RT_SERIAL_BUF_STRATEGY_OVERWRITE bool "overwrite old data when the buffer is full" + help + Define how V2 RX buffers behave on overflow: drop new bytes or + overwrite oldest data. endchoice config RT_SERIAL_USING_DMA bool "Enable serial DMA mode" default y + help + Allow serial drivers to use DMA for RX/TX to reduce CPU load. Turn + off if your SoC lacks UART DMA support. config RT_SERIAL_RB_BUFSZ int "Set RX buffer size" depends on !RT_USING_SERIAL_V2 default 64 + help + Size of the legacy (V1) receive ring buffer in bytes. config RT_USING_SERIAL_BYPASS bool "Using serial bypass" default n + help + Enable bypass mode that forwards data between two serial devices, + useful for debugging or bridging. endif diff --git a/components/drivers/serial/utest/Kconfig b/components/drivers/serial/utest/Kconfig index aefb162b8b5..2478ecc5548 100644 --- a/components/drivers/serial/utest/Kconfig +++ b/components/drivers/serial/utest/Kconfig @@ -4,33 +4,47 @@ menu "Serial Test" bool "Serial Bypass Test" default n depends on RT_USING_SERIAL_BYPASS + help + Run tests validating the serial bypass feature. config RT_UTEST_SERIAL_V2 bool "Serial V2 Test" default n depends on RT_USING_SERIAL_V2 + help + Build testcases covering the Serial V2 core (buffer strategies, DMA). if RT_UTEST_SERIAL_V2 config RT_SERIAL_TC_DEVICE_NAME string "Device Name for Serial Test" default "uart2" + help + UART device name used by the V2 testcases. config RT_SERIAL_TC_RXBUF_SIZE int "RX Buffer Size for Serial Test" default 128 + help + Receive buffer size used during V2 tests. config RT_SERIAL_TC_TXBUF_SIZE int "TX Buffer Size for Serial Test" default 128 + help + Transmit buffer size used during tests. config RT_SERIAL_TC_SEND_ITERATIONS int "Number of Iterations for Test Routines" default 100 + help + How many times each test loop runs; raise for stress testing. config RT_UTEST_SERIAL_QEMU bool "QEMU Dedicated Test" default n + help + Enable extra scenarios tailored for QEMU environments. config RT_UTEST_SERIAL_POSIX bool "Serial POSIX Test" @@ -38,19 +52,25 @@ menu "Serial Test" select RT_USING_DFS select RT_USING_POSIX_FS select RT_USING_POSIX_TERMIOS + help + Include POSIX-style serial tests that rely on DFS and termios. if RT_UTEST_SERIAL_POSIX config RT_SERIAL_POSIX_TC_DEVICE_NAME string "Device Name for Serial POSIX Test" default "dev/uart2" + help + Path used by the POSIX testcases to open the serial device. config RT_SERIAL_POSIX_TC_SEND_ITERATIONS int "Number of Iterations for POSIX Test Routines" default 100 + help + Iteration count for the POSIX test loops. endif endif -endmenu \ No newline at end of file +endmenu diff --git a/components/drivers/smp_call/utest/Kconfig b/components/drivers/smp_call/utest/Kconfig index fc9776027c2..85123bb63b7 100644 --- a/components/drivers/smp_call/utest/Kconfig +++ b/components/drivers/smp_call/utest/Kconfig @@ -4,5 +4,7 @@ config RT_UTEST_SMP_CALL_FUNC bool "SMP-Call Smoke Test" default n depends on RT_USING_SMP + help + Build SMP call function tests to ensure inter-core callbacks work. endmenu diff --git a/components/drivers/spi/Kconfig b/components/drivers/spi/Kconfig index 37a6a9b943a..77673372873 100644 --- a/components/drivers/spi/Kconfig +++ b/components/drivers/spi/Kconfig @@ -1,21 +1,42 @@ menuconfig RT_USING_SPI bool "Using SPI Bus/Device device drivers" default n + help + Enable the SPI framework so hardware controllers and client drivers can + register SPI buses/devices through RT-Thread. This brings in the SPI core, + the DM glue, and the optional software backend. Turn it on for any board + that connects SPI flashes, sensors, RF chips, or display panels; disable + only when SPI is unused to save footprint. if RT_USING_SPI menuconfig RT_USING_SPI_ISR bool "Enable interrupt-safe SPI operations (using spinlocks in ISR context)" default y + help + Allow SPI APIs to be invoked from interrupt context by guarding + transfer state with spinlocks instead of mutexes. Enable it when + DMA completion or GPIO IRQ handlers need to queue SPI work; leave + it off if every transfer happens in thread context to slightly + reduce locking overhead. menuconfig RT_USING_SOFT_SPI bool "Use GPIO to simulate SPI" default n select RT_USING_PIN + help + Build software (bit-banged) SPI masters that toggle GPIO pins in + software. Each bus selected below lets you pick SCK/MISO/MOSI pins + and an exported bus name, ideal for simple sensors or when all + hardware SPI controllers are in use. if RT_USING_SOFT_SPI menuconfig RT_USING_SOFT_SPI0 bool "Enable SPI0 Bus (software simulation)" default y + help + Instantiate the first software SPI bus using the pins + configured below. Disable it if your board does not need a + bit-banged SPI0 instance. if RT_USING_SOFT_SPI0 config RT_SOFT_SPI0_SCK_PIN int "SCK pin number" @@ -40,6 +61,9 @@ menuconfig RT_USING_SPI menuconfig RT_USING_SOFT_SPI1 bool "Enable SPI1 Bus (software simulation)" default y + help + Enable a second software SPI channel for additional + low-speed peripherals when dedicated controllers run out. if RT_USING_SOFT_SPI1 config RT_SOFT_SPI1_SCK_PIN int "SCK pin number" @@ -64,6 +88,9 @@ menuconfig RT_USING_SPI menuconfig RT_USING_SOFT_SPI2 bool "Enable SPI2 Bus (software simulation)" default n + help + Optional third soft SPI bus. Only enable when the PCB + routes the corresponding GPIO pins. if RT_USING_SOFT_SPI2 config RT_SOFT_SPI2_SCK_PIN int "SCK pin number" @@ -88,6 +115,9 @@ menuconfig RT_USING_SPI menuconfig RT_USING_SOFT_SPI3 bool "Enable SPI3 Bus (software simulation)" default n + help + Fourth bit-banged SPI bus entry. Leave disabled to save + resources if not wired. if RT_USING_SOFT_SPI3 config RT_SOFT_SPI3_SCK_PIN int "SCK pin number" @@ -112,6 +142,9 @@ menuconfig RT_USING_SPI menuconfig RT_USING_SOFT_SPI4 bool "Enable SPI4 Bus (software simulation)" default n + help + Provide a fifth software SPI bus; adds static data for the + pin descriptors even when unused. if RT_USING_SOFT_SPI4 config RT_SOFT_SPI4_SCK_PIN int "SCK pin number" @@ -136,6 +169,9 @@ menuconfig RT_USING_SPI menuconfig RT_USING_SOFT_SPI5 bool "Enable SPI5 Bus (software simulation)" default n + help + Optional sixth software bus for complex designs with many + discrete chips. if RT_USING_SOFT_SPI5 config RT_SOFT_SPI5_SCK_PIN int "SCK pin number" @@ -160,6 +196,9 @@ menuconfig RT_USING_SPI menuconfig RT_USING_SOFT_SPI6 bool "Enable SPI6 Bus (software simulation)" default n + help + Enable a seventh software SPI controller if more GPIO-only + buses are necessary. if RT_USING_SOFT_SPI6 config RT_SOFT_SPI6_SCK_PIN int "SCK pin number" @@ -187,57 +226,99 @@ menuconfig RT_USING_SPI bool "Use simulate SPI debug message" depends on RT_USING_SOFT_SPI default n + help + Print the edge-level toggling performed by the software SPI + backend. Useful when verifying custom wiring, but it slows down + transfers considerably. config RT_USING_QSPI bool "Enable QSPI mode" default n + help + Adds Quad-SPI support to the SPI core so flash drivers can switch + MISO/MOSI pins into quad data mode and use controller-specific + QSPI ops. Enable this when your SoC exposes a QSPI controller or + you plan to run SFUD in quad mode. config RT_USING_SPI_MSD bool "Using SD/TF card driver with spi" select RT_USING_DFS default n + help + Build the SPI-based block driver for SD/TF cards (Mass Storage + Device). Select this when your design wires SD cards to an SPI + bus instead of a dedicated SDIO host; it pulls in DFS for the + filesystem layer. config RT_USING_SFUD bool "Using Serial Flash Universal Driver" default n help - An using JEDEC's SFDP standard serial (SPI) flash universal driver library + Pull in the Serial Flash Universal Driver which speaks the JEDEC + SFDP standard, auto-detects parameters, and exposes SPI NOR chips + through the RT-Thread MTD interface. Enable this for off-chip SPI + NOR/QSPI flash storage; disable it if you rely on SoC-specific + flash drivers instead. if RT_USING_SFUD config RT_SFUD_USING_SFDP bool "Using auto probe flash JEDEC SFDP parameter" default y + help + Parse the flash SFDP tables at runtime for sizing, erase + commands, and quad support. Disable only if your flash lacks + SFDP and you prefer hard-coded settings. config RT_SFUD_USING_FLASH_INFO_TABLE bool "Using defined supported flash chip information table" default y + help + Keep the built-in flash info table so chips without valid SFDP + headers can still be recognized. You can turn it off to reduce + the binary when you know SFDP probing always succeeds. config RT_SFUD_USING_QSPI bool "Using QSPI mode support" select RT_USING_QSPI default n + help + Allow SFUD to drive flashes via Quad-SPI instructions. Requires + a QSPI-capable controller and board routing. config RT_SFUD_SPI_MAX_HZ - int "Default spi maximum speed(HZ)" - range 0 50000000 - default 50000000 - help - Read the JEDEC SFDP command must run at 50 MHz or less,and you also can use rt_spi_configure(); to config spi speed. + int "Default spi maximum speed(HZ)" + range 0 50000000 + default 50000000 + help + Default maximum bus frequency SFUD will request when + probing flashes. Keep it at or below 50 MHz for SFDP per + the JEDEC spec; runtime drivers may still lower it with + `rt_spi_configure()`. config RT_DEBUG_SFUD bool "Show more SFUD debug information" default n + help + Verbosely log SFUD operations (probe, erase, write). Enable + when bringing up new flash parts; keep disabled in production. endif config RT_USING_ENC28J60 bool "Using ENC28J60 SPI Ethernet network interface" select RT_USING_LWIP default n + help + Build the ENC28J60 Ethernet driver which talks to Microchip's SPI + MAC+PHY and registers a netif on top of lwIP. Enable it when your + board uses the ENC28J60; otherwise it adds dead code. config RT_USING_SPI_WIFI bool "Using RW009/007 SPI Wi-Fi wireless interface" select RT_USING_LWIP default n + help + Include the RW009/RW007 Wi-Fi driver that exchanges frames via + SPI. Requires lwIP and a matching module connected to the bus. endif if RT_USING_DM && RT_USING_SPI diff --git a/components/drivers/thermal/Kconfig b/components/drivers/thermal/Kconfig index b993aafd82b..5e655f3a65d 100644 --- a/components/drivers/thermal/Kconfig +++ b/components/drivers/thermal/Kconfig @@ -2,6 +2,10 @@ menuconfig RT_USING_THERMAL bool "Using Thermal Management device drivers" depends on RT_USING_DM default n + help + Enable the thermal framework which registers sensors/cooling devices and + lets policies throttle clocks, fans, or regulators. Required on SoCs that + monitor die temperature. if RT_USING_THERMAL comment "Thermal Sensors Drivers" @@ -22,6 +26,9 @@ config RT_THERMAL_COOL_PWM_FAN depends on RT_USING_REGULATOR depends on RT_USING_OFW default n + help + Build the cooling device that drives fans via PWM and regulator APIs based + on thermal policy requests. if RT_USING_THERMAL osource "$(SOC_DM_THERMAL_COOL_DIR)/Kconfig" diff --git a/components/drivers/touch/Kconfig b/components/drivers/touch/Kconfig index 6542ac4219f..1938e0b6b20 100644 --- a/components/drivers/touch/Kconfig +++ b/components/drivers/touch/Kconfig @@ -1,8 +1,14 @@ config RT_USING_TOUCH bool "Using Touch device drivers" default n + help + Enable the touchscreen input framework so controllers (capacitive, + resistive, I2C, SPI) can register coordinate events. if RT_USING_TOUCH config RT_TOUCH_PIN_IRQ bool "touch irq use pin irq" default n + help + Use GPIO pin interrupts for touch controllers that can signal via an + external interrupt line instead of polling. endif diff --git a/components/drivers/usb/Kconfig b/components/drivers/usb/Kconfig index 3af62ab03e2..a6d243b4a59 100644 --- a/components/drivers/usb/Kconfig +++ b/components/drivers/usb/Kconfig @@ -1 +1,8 @@ +menu "USB Drivers" + help + Select USB host/device controller stacks. CherryUSB provides both device + and host implementations used by RT-Thread. + rsource "cherryusb/Kconfig.rtt" + +endmenu diff --git a/components/drivers/virtio/Kconfig b/components/drivers/virtio/Kconfig index 8298ff75beb..1657267c3cf 100644 --- a/components/drivers/virtio/Kconfig +++ b/components/drivers/virtio/Kconfig @@ -1,6 +1,9 @@ menuconfig RT_USING_VIRTIO bool "Using VirtIO device drivers" default n + help + Enable VirtIO front-end drivers for virtualized environments (QEMU, + cloud). Requires a hypervisor exposing VirtIO MMIO or PCI devices. if RT_USING_VIRTIO choice RT_USING_VIRTIO_VERSION @@ -9,35 +12,54 @@ menuconfig RT_USING_VIRTIO config RT_USING_VIRTIO10 bool "VirtIO v1.0" + help + Use the modern VirtIO 1.0 device layout with feature bits in + the standard registers. endchoice config RT_USING_VIRTIO_MMIO_ALIGN bool "Using VirtIO MMIO alignment" default y + help + Enforce strict MMIO alignment handling required by some hosts. config RT_USING_VIRTIO_BLK bool "Using VirtIO BLK" default y + help + Build the VirtIO block driver to expose virtual disks as RT-Thread + block devices. config RT_USING_VIRTIO_NET bool "Using VirtIO NET" default y + help + Build the VirtIO network driver to connect to the hypervisor's + virtual NIC. menuconfig RT_USING_VIRTIO_CONSOLE bool "Using VirtIO Console" default y + help + Enable the VirtIO console port driver for serial I/O via hypervisor. if RT_USING_VIRTIO_CONSOLE config RT_USING_VIRTIO_CONSOLE_PORT_MAX_NR int "Max number of port in VirtIO Console" default 4 + help + Maximum number of sub-ports exposed by the VirtIO console. endif config RT_USING_VIRTIO_GPU bool "Using VirtIO GPU" default y + help + Build the VirtIO GPU driver for virtual display support. config RT_USING_VIRTIO_INPUT bool "Using VirtIO Input" default y + help + Register VirtIO input devices (keyboard, pointer) through RT-Thread. endif diff --git a/components/drivers/watchdog/Kconfig b/components/drivers/watchdog/Kconfig index bc85a68bf83..eecbf2e4b90 100644 --- a/components/drivers/watchdog/Kconfig +++ b/components/drivers/watchdog/Kconfig @@ -1,6 +1,15 @@ menuconfig RT_USING_WDT bool "Using Watch Dog device drivers" default n + help + Enable the common watchdog device layer so watchdog-capable SoCs or + external supervisors can be exposed through the RT-Thread `rt_watchdog` + APIs. Selecting this option allows watchdog platform drivers to register + /dev/wdt style devices, lets applications query/set timeout windows, and + integrates watchdog notifications into the driver-model (DM) probe/remove + flow. Disable it only when the hardware has no watchdog or it is managed + entirely outside of RT-Thread, because the system will no longer be able + to arm, feed or inspect watchdogs during boot and runtime. config RT_WDT_DW bool "Synopsys DesignWare watchdog" @@ -8,12 +17,31 @@ config RT_WDT_DW depends on RT_USING_WDT depends on RT_USING_RESET default n + help + Build the driver for Synopsys DesignWare watchdog blocks that appear in + many ARM and RISC-V SoCs. The driver maps the DM platform resources, + exports the 16 preset timeout levels ("TOPs"), supports optional pre- + timeout interrupts, and automatically toggles the associated reset line + through `RT_USING_RESET`. Once started the DW watchdog cannot be disabled, + so the driver only gates the peripheral clock and pulses the reset + controller to keep it under control. Use this when your device tree + exposes a `snps,dw-wdt` node and you need either reset-based system + recovery or two-stage IRQ/Reset supervision; otherwise leave it off. config RT_WDT_I6300ESB bool "Intel 6300ESB Timer/Watchdog" depends on RT_USING_DM depends on RT_USING_WDT depends on RT_USING_PCI + help + Enable support for the watchdog integrated in Intel 6300ESB southbridge + chipsets. The driver binds to the PCI device, unlocks the dual-stage timer, + and exposes the 1 kHz heartbeat window (1–2046 seconds) through the + standard watchdog IOCTLs. It can optionally enter "nowayout" mode when the + firmware locks the control register, so be careful when testing on shared + x86 hardware. Select this only on boards that actually contain the 6300ESB + watchdog because the driver directly touches PCI config space and assumes + the LPC reset registers are routed correctly. if RT_USING_DM && RT_USING_WDT osource "$(SOC_DM_WDT_DIR)/Kconfig" diff --git a/components/drivers/wlan/Kconfig b/components/drivers/wlan/Kconfig index 59ad948bcac..92abc25ed9b 100644 --- a/components/drivers/wlan/Kconfig +++ b/components/drivers/wlan/Kconfig @@ -1,154 +1,223 @@ menuconfig RT_USING_WIFI bool "Using Wi-Fi framework" default n + help + Enable the RT-Thread Wi-Fi middleware which manages STA/AP interfaces, + connection profiles, protocol glue, workqueues, and debugging hooks. if RT_USING_WIFI config RT_WLAN_DEVICE_STA_NAME string "The device name for station" default "wlan0" + help + Logical device name used for the station interface. config RT_WLAN_DEVICE_AP_NAME string "The device name for ap" default "wlan1" + help + Logical device name for the SoftAP interface. config RT_WLAN_SSID_MAX_LENGTH int "SSID maximum length" default 32 + help + Upper bound for SSID strings stored by the framework. config RT_WLAN_PASSWORD_MAX_LENGTH int "Password maximum length" default 32 + help + Maximum length of passphrases saved in configs. config RT_WLAN_DEV_EVENT_NUM int "Driver events maxcount" default 2 + help + Number of event objects reserved for notifying upper layers. config RT_WLAN_MANAGE_ENABLE bool "Connection management Enable" default y + help + Turn on the connection manager (auto reconnect, scanning, CLI). if RT_WLAN_MANAGE_ENABLE config RT_WLAN_SCAN_WAIT_MS int "Set scan timeout time(ms)" default 10000 + help + Timeout for synchronous scan requests in milliseconds. config RT_WLAN_CONNECT_WAIT_MS int "Set connect timeout time(ms)" default 10000 + help + Connection attempt timeout. config RT_WLAN_SCAN_SORT bool "Automatic sorting of scan results" default y + help + Sort scan results by RSSI/channel automatically. config RT_WLAN_MSH_CMD_ENABLE bool "MSH command Enable" default y + help + Add msh shell commands (`wifi`, etc.) for management. config RT_WLAN_JOIN_SCAN_BY_MGNT bool "Enable wlan join scan" default y + help + Allow connection manager to trigger scans before joining. config RT_WLAN_AUTO_CONNECT_ENABLE bool "Auto connect Enable" select RT_WLAN_CFG_ENABLE select RT_WLAN_WORK_THREAD_ENABLE default y + help + Automatically reconnect using saved profiles when link drops. if RT_WLAN_AUTO_CONNECT_ENABLE config AUTO_CONNECTION_PERIOD_MS int "Auto connect period(ms)" default 2000 + help + Interval between automatic reconnect attempts. endif endif config RT_WLAN_CFG_ENABLE bool "WiFi information automatically saved Enable" default y + help + Persist Wi-Fi credentials and settings to storage. if RT_WLAN_CFG_ENABLE config RT_WLAN_CFG_INFO_MAX int "Maximum number of WiFi information automatically saved" default 3 + help + Maximum number of networks stored for auto-connect. endif config RT_WLAN_PROT_ENABLE bool "Transport protocol manage Enable" default y + help + Allow protocol modules (lwIP, etc.) to register with WLAN core. if RT_WLAN_PROT_ENABLE config RT_WLAN_PROT_NAME_LEN int "Transport protocol name length" default 8 + help + Max length for protocol identifier strings. config RT_WLAN_PROT_MAX int "Transport protocol maxcount" default 2 + help + Number of protocol backends that can be registered. config RT_WLAN_DEFAULT_PROT string "Default transport protocol" default "lwip" + help + Name of the protocol backend used when none specified. config RT_WLAN_PROT_LWIP_ENABLE bool "LWIP transport protocol Enable" select RT_USING_LWIP default y + help + Register lwIP as a transport backend for WLAN sockets. if RT_WLAN_PROT_LWIP_ENABLE config RT_WLAN_PROT_LWIP_NAME string "LWIP transport protocol name" default "lwip" + help + Name exported for the lwIP backend. config RT_WLAN_PROT_LWIP_PBUF_FORCE bool "Forced use of PBUF transmission" default n + help + Force PBUF-based data path even when zero-copy is possible. endif endif config RT_WLAN_WORK_THREAD_ENABLE bool "WLAN work queue thread Enable" default y + help + Spawn the WLAN workqueue thread that handles asynchronous tasks. if RT_WLAN_WORK_THREAD_ENABLE config RT_WLAN_WORKQUEUE_THREAD_NAME string "WLAN work queue thread name" default "wlan" + help + Name of the workqueue thread. config RT_WLAN_WORKQUEUE_THREAD_SIZE int "WLAN work queue thread size" default 2048 + help + Stack size in bytes for the workqueue thread. config RT_WLAN_WORKQUEUE_THREAD_PRIO int "WLAN work queue thread priority" default 15 + help + RT-Thread priority of the WLAN workqueue. endif menuconfig RT_WLAN_DEBUG bool "Enable WLAN Debugging Options" default n + help + Enable fine-grained debug switches for WLAN subsystems. if RT_WLAN_DEBUG config RT_WLAN_CMD_DEBUG bool "Enable Debugging of wlan_cmd.c" default n + help + Log detailed info from the command module. config RT_WLAN_MGNT_DEBUG bool "Enable Debugging of wlan_mgnt.c" default n + help + Debug connection management state transitions. config RT_WLAN_DEV_DEBUG bool "Enable Debugging of wlan_dev.c" default n + help + Trace driver-level operations. config RT_WLAN_PROT_DEBUG bool "Enable Debugging of wlan_prot.c" default n + help + Dump protocol manager operations. config RT_WLAN_CFG_DEBUG bool "Enable Debugging of wlan_cfg.c" default n + help + Trace configuration load/save. config RT_WLAN_LWIP_DEBUG bool "Enable Debugging of wlan_lwip.c" default n + help + Print lwIP glue logs. endif endif From 0f0e8c1f341b6ebe14446bf9da55f7fecabf8b40 Mon Sep 17 00:00:00 2001 From: "copilot-swe-agent[bot]" <198982749+Copilot@users.noreply.github.com> Date: Tue, 13 Jan 2026 05:48:49 +0000 Subject: [PATCH 8/9] Resolve merge conflicts with master branch Co-authored-by: Rbb666 <64397326+Rbb666@users.noreply.github.com> --- .github/ALL_BSP_COMPILE.json | 12 +- .github/copilot-instructions.md | 175 +- .github/workflows/bsp_buildings.yml | 2 + .github/workflows/utest_auto_run.yml | 6 +- .gitignore | 2 + bsp/Copyright_Notice.md | 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27 + .../ra/fsp/src/bsp/mcu/all/bsp_io.h | 465 + .../ra/fsp/src/bsp/mcu/all/bsp_ipc.c | 148 + .../ra/fsp/src/bsp/mcu/all/bsp_ipc.h | 60 + .../ra/fsp/src/bsp/mcu/all/bsp_irq.c | 310 + .../ra/fsp/src/bsp/mcu/all/bsp_irq.h | 238 + .../ra/fsp/src/bsp/mcu/all/bsp_macl.c | 2050 + .../ra/fsp/src/bsp/mcu/all/bsp_macl.h | 164 + .../ra/fsp/src/bsp/mcu/all/bsp_mcu_api.h | 87 + .../ra/fsp/src/bsp/mcu/all/bsp_mmf.h | 141 + .../ra/fsp/src/bsp/mcu/all/bsp_module_stop.h | 389 + .../ra/fsp/src/bsp/mcu/all/bsp_ospi_b.c | 77 + .../ra/fsp/src/bsp/mcu/all/bsp_ospi_b.h | 39 + .../src/bsp/mcu/all/bsp_register_protection.c | 120 + .../src/bsp/mcu/all/bsp_register_protection.h | 63 + .../ra/fsp/src/bsp/mcu/all/bsp_sbrk.c | 104 + .../ra/fsp/src/bsp/mcu/all/bsp_sdram.c | 199 + .../ra/fsp/src/bsp/mcu/all/bsp_sdram.h | 37 + .../ra/fsp/src/bsp/mcu/all/bsp_security.c | 563 + .../ra/fsp/src/bsp/mcu/all/bsp_security.h | 33 + .../ra/fsp/src/bsp/mcu/all/bsp_tfu.h | 218 + .../ra/fsp/src/bsp/mcu/ra8p1/bsp_elc.h | 583 + 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.../KSZ8091RNB/r_rmac_phy_target_ksz8091rnb.c | 105 + .../ra/fsp/src/r_rtc/r_rtc.c | 1729 + .../ra/fsp/src/r_sci_b_uart/r_sci_b_uart.c | 1821 + .../ra/fsp/src/r_sdhi/r_sdhi.c | 2350 + .../ra/fsp/src/r_sdhi/r_sdhi_private.h | 260 + .../ra/fsp/src/r_spi_b/r_spi_b.c | 1237 + .../ra8p1-titan-board/ra_cfg/SConscript | 17 + .../ra_cfg/fsp_cfg/bsp/board_cfg.h | 13 + .../ra_cfg/fsp_cfg/bsp/bsp_cfg.h | 63 + .../ra_cfg/fsp_cfg/bsp/bsp_mcu_device_cfg.h | 5 + .../fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h | 20 + .../ra_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h | 516 + .../ra_cfg/fsp_cfg/bsp/bsp_mcu_ofs_cfg.h | 4 + .../ra_cfg/fsp_cfg/bsp/bsp_pin_cfg.h | 212 + .../ra_cfg/fsp_cfg/r_adc_b_cfg.h | 13 + .../ra_cfg/fsp_cfg/r_canfd_cfg.h | 22 + .../ra_cfg/fsp_cfg/r_dmac_cfg.h | 13 + .../ra_cfg/fsp_cfg/r_gpt_cfg.h | 21 + .../ra_cfg/fsp_cfg/r_iic_master_cfg.h | 15 + .../ra_cfg/fsp_cfg/r_ioport_cfg.h | 14 + .../ra_cfg/fsp_cfg/r_layer3_switch_cfg.h | 19 + .../ra_cfg/fsp_cfg/r_ospi_b_cfg.h | 26 + .../ra_cfg/fsp_cfg/r_rmac_cfg.h | 13 + .../ra_cfg/fsp_cfg/r_rmac_phy_cfg.h | 32 + .../ra_cfg/fsp_cfg/r_rtc_cfg.h | 14 + .../ra_cfg/fsp_cfg/r_sci_b_uart_cfg.h | 16 + .../ra_cfg/fsp_cfg/r_sdhi_cfg.h | 20 + .../ra_cfg/fsp_cfg/r_spi_b_cfg.h | 18 + .../ra8p1-titan-board/ra_gen/SConscript | 17 + .../ra8p1-titan-board/ra_gen/bsp_clock_cfg.h | 75 + .../ra8p1-titan-board/ra_gen/common_data.c | 263 + .../ra8p1-titan-board/ra_gen/common_data.h | 77 + .../ra8p1-titan-board/ra_gen/hal_data.c | 3962 + .../ra8p1-titan-board/ra_gen/hal_data.h | 184 + bsp/renesas/ra8p1-titan-board/ra_gen/main.c | 6 + .../ra8p1-titan-board/ra_gen/pin_data.c | 451 + .../ra8p1-titan-board/ra_gen/vector_data.c | 111 + .../ra8p1-titan-board/ra_gen/vector_data.h | 160 + bsp/renesas/ra8p1-titan-board/rtconfig.h | 434 + bsp/renesas/ra8p1-titan-board/rtconfig.py | 136 + bsp/renesas/ra8p1-titan-board/script/fsp.icf | 970 + bsp/renesas/ra8p1-titan-board/script/fsp.ld | 1098 + bsp/renesas/ra8p1-titan-board/script/fsp.scat | 1113 + bsp/renesas/ra8p1-titan-board/src/hal_entry.c | 33 + bsp/renesas/ra8p1-titan-board/template.uvoptx | 218 + .../ra8p1-titan-board/template.uvprojx | 424 + bsp/rockchip/dm/Kconfig | 24 + bsp/rockchip/dm/SConscript | 13 + bsp/rockchip/dm/adc/Kconfig | 6 + bsp/rockchip/dm/adc/SConscript | 14 + bsp/rockchip/dm/adc/adc-rockchip_saradc.c | 527 + bsp/rockchip/dm/can/Kconfig | 7 + bsp/rockchip/dm/can/SConscript | 12 + bsp/rockchip/dm/can/canfd-rockchip.c | 1061 + bsp/rockchip/dm/clk/Kconfig | 36 + bsp/rockchip/dm/clk/SConscript | 33 + bsp/rockchip/dm/clk/clk-link.c | 210 + bsp/rockchip/dm/clk/clk-rk-composite.c | 51 + bsp/rockchip/dm/clk/clk-rk-composite.h | 191 + bsp/rockchip/dm/clk/clk-rk-cpu.c | 278 + bsp/rockchip/dm/clk/clk-rk-cpu.h | 87 + bsp/rockchip/dm/clk/clk-rk-divider.c | 595 + bsp/rockchip/dm/clk/clk-rk-divider.h | 52 + bsp/rockchip/dm/clk/clk-rk-factor.c | 61 + bsp/rockchip/dm/clk/clk-rk-factor.h | 63 + bsp/rockchip/dm/clk/clk-rk-fraction-divider.c | 370 + bsp/rockchip/dm/clk/clk-rk-fraction-divider.h | 95 + bsp/rockchip/dm/clk/clk-rk-gate.c | 109 + bsp/rockchip/dm/clk/clk-rk-gate.h | 32 + bsp/rockchip/dm/clk/clk-rk-half-divider.c | 182 + bsp/rockchip/dm/clk/clk-rk-half-divider.h | 126 + .../clk/clk-rk-mmc-phase.c} | 87 +- bsp/rockchip/dm/clk/clk-rk-mmc-phase.h | 48 + bsp/rockchip/dm/clk/clk-rk-mux.c | 159 + bsp/rockchip/dm/clk/clk-rk-mux.h | 57 + bsp/rockchip/dm/clk/clk-rk-muxgrf.c | 85 + bsp/rockchip/dm/clk/clk-rk-muxgrf.h | 50 + bsp/rockchip/dm/clk/clk-rk-pll.c | 1546 + bsp/rockchip/dm/clk/clk-rk-pll.h | 144 + bsp/rockchip/dm/clk/clk-rk.c | 169 + bsp/rockchip/dm/clk/clk-rk.h | 107 + bsp/rockchip/dm/clk/clk-rk3308.c | 950 + bsp/rockchip/dm/clk/clk-rk3568.c | 1488 + bsp/rockchip/dm/clk/clk-rk3576.c | 1839 + bsp/rockchip/dm/clk/clk-rk3588.c | 2166 + bsp/rockchip/dm/clk/clk-rk8xx-clkout.c | 203 + .../{rk3500/driver => dm}/clk/softrst.c | 49 +- bsp/rockchip/dm/hwcrypto/Kconfig | 5 + .../uart8250 => dm/hwcrypto}/SConscript | 11 +- bsp/rockchip/dm/hwcrypto/hw-rng-rockchip.c | 565 + bsp/rockchip/dm/hwspinlock/Kconfig | 3 + bsp/rockchip/dm/hwspinlock/SConscript | 12 + .../dm/hwspinlock/hwspinlock-rockchip.c | 135 + .../{rk3500/driver => dm}/hwtimer/Kconfig | 2 - .../{rk3500/driver => dm}/hwtimer/SConscript | 7 +- .../hwtimer/hwtimer-rockchip_timer.c | 180 +- bsp/rockchip/dm/i2c/Kconfig | 5 + bsp/rockchip/dm/i2c/SConscript | 12 + bsp/rockchip/dm/i2c/i2c-rk3x.c | 1375 + .../dm/include/dt-bindings/clock/rk3308-cru.h | 387 + .../include/dt-bindings/clock}/rk3568-cru.h | 8 +- .../dm/include/dt-bindings/clock/rk3576-cru.h | 1151 + .../include/dt-bindings/clock}/rk3588-cru.h | 12 +- .../dt-bindings/phye/phye-snps-pcie3.h | 22 + .../dm/include/dt-bindings/pinctrl/rockchip.h | 232 + .../dm/include/dt-bindings/power/px30-power.h | 32 + .../include/dt-bindings/power/rk1808-power.h | 25 + .../include/dt-bindings/power/rk3036-power.h | 18 + .../include/dt-bindings/power/rk3066-power.h | 27 + .../include/dt-bindings/power/rk3128-power.h | 19 + .../include/dt-bindings/power/rk3188-power.h | 29 + .../include/dt-bindings/power/rk3228-power.h | 22 + .../include/dt-bindings/power/rk3288-power.h | 33 + .../include/dt-bindings/power/rk3328-power.h | 21 + .../include/dt-bindings/power/rk3366-power.h | 30 + .../include/dt-bindings/power/rk3368-power.h | 34 + .../include/dt-bindings/power/rk3399-power.h | 59 + .../include/dt-bindings/power/rk3528-power.h | 23 + .../include/dt-bindings/power/rk3562-power.h | 37 + .../include/dt-bindings/power/rk3568-power.h | 37 + .../include/dt-bindings/power/rk3576-power.h | 35 + .../include/dt-bindings/power/rk3588-power.h | 74 + .../include/dt-bindings/power/rv1126-power.h | 39 + bsp/rockchip/dm/include/hw-decompress.h | 40 + bsp/rockchip/dm/include/pinctrl-rockchip.h | 183 + bsp/rockchip/dm/include/rk8xx.h | 912 + bsp/rockchip/dm/include/rockchip.h | 86 + bsp/rockchip/dm/input/SConscript | 13 + bsp/rockchip/dm/input/misc/Kconfig | 5 + bsp/rockchip/dm/input/misc/SConscript | 13 + bsp/rockchip/dm/input/misc/pwrkey-rk8xx.c | 115 + bsp/rockchip/dm/mailbox/Kconfig | 3 + bsp/rockchip/dm/mailbox/SConscript | 12 + bsp/rockchip/dm/mailbox/mailbox-rockchip.c | 575 + bsp/rockchip/dm/mfd/Kconfig | 19 + bsp/rockchip/dm/mfd/SConscript | 18 + bsp/rockchip/dm/mfd/rk8xx-i2c.c | 187 + bsp/rockchip/dm/mfd/rk8xx-spi.c | 148 + bsp/rockchip/dm/mfd/rk8xx.c | 1088 + bsp/rockchip/dm/nvmem/Kconfig | 3 + bsp/rockchip/dm/nvmem/SConscript | 12 + bsp/rockchip/dm/nvmem/nvmem-rockchip-otp.c | 1037 + bsp/rockchip/dm/pci/Kconfig | 11 + bsp/rockchip/dm/pci/SConscript | 15 + bsp/rockchip/dm/pci/pcie-dw-rockchip.c | 1645 + bsp/rockchip/dm/phye/Kconfig | 9 + bsp/rockchip/dm/phye/SConscript | 15 + bsp/rockchip/dm/phye/phye-naneng-combphy.c | 1482 + bsp/rockchip/dm/phye/phye-snps-pcie3.c | 432 + bsp/rockchip/dm/phye/phye-snps-pcie3.fw | 8192 + bsp/rockchip/dm/pin/Kconfig | 4 + bsp/rockchip/dm/pin/SConscript | 13 + bsp/rockchip/dm/pin/pin-rockchip.c | 596 + bsp/rockchip/dm/pinctrl/Kconfig | 11 + bsp/rockchip/dm/pinctrl/SConscript | 16 + bsp/rockchip/dm/pinctrl/pinctrl-rk8xx.c | 392 + bsp/rockchip/dm/pinctrl/pinctrl-rockchip.c | 1763 + bsp/rockchip/dm/pmdomain/Kconfig | 6 + bsp/rockchip/dm/pmdomain/SConscript | 12 + bsp/rockchip/dm/pmdomain/pm-domain-rockchip.c | 1878 + bsp/rockchip/dm/pwm/Kconfig | 5 + bsp/rockchip/dm/pwm/SConscript | 14 + bsp/rockchip/dm/pwm/pwm-rockchip.c | 613 + bsp/rockchip/dm/regulator/Kconfig | 5 + bsp/rockchip/dm/regulator/SConscript | 12 + bsp/rockchip/dm/regulator/regulator-rk8xx.c | 1236 + bsp/rockchip/dm/rtc/Kconfig | 7 + bsp/rockchip/dm/rtc/SConscript | 16 + bsp/rockchip/dm/rtc/rtc-rk8xx.c | 424 + bsp/rockchip/dm/rtc/rtc-rk_timer.c | 397 + bsp/rockchip/dm/sdio/Kconfig | 5 + bsp/rockchip/dm/sdio/SConscript | 12 + bsp/rockchip/dm/sdio/sdio-dw_rockchip.c | 461 + bsp/rockchip/dm/soc/Kconfig | 19 + bsp/rockchip/dm/soc/SConscript | 22 + .../driver/uart8250 => dm/soc}/fiq-debugger.c | 27 +- bsp/rockchip/dm/soc/grf.c | 311 + bsp/rockchip/dm/soc/hw-decompress.c | 392 + bsp/rockchip/dm/soc/io-domain.c | 698 + bsp/rockchip/dm/spi/Kconfig | 18 + bsp/rockchip/dm/spi/SConscript | 16 + bsp/rockchip/dm/spi/spi-rockchip-sfc.c | 1004 + bsp/rockchip/dm/spi/spi-rockchip.c | 1295 + bsp/rockchip/dm/thermal/Kconfig | 6 + bsp/rockchip/dm/thermal/SConscript | 13 + .../dm/thermal/thermal-rockchip_tsadc.c | 1695 + bsp/rockchip/dm/watchdog/Kconfig | 3 + bsp/rockchip/dm/watchdog/SConscript | 13 + bsp/rockchip/dm/watchdog/watchdog-rk8xx.c | 188 + bsp/rockchip/rk3300/.config | 1664 + bsp/rockchip/{rk3568 => rk3300}/Kconfig | 12 +- bsp/rockchip/rk3300/README.md | 55 + bsp/rockchip/rk3300/README_ZH.md | 56 + bsp/rockchip/rk3300/SConscript | 16 + bsp/rockchip/{rk3568 => rk3300}/SConstruct | 0 bsp/rockchip/rk3300/applications/SConscript | 9 + bsp/rockchip/rk3300/applications/main.c | 31 + .../{rk3568 => rk3300}/driver/SConscript | 0 bsp/rockchip/rk3300/driver/board.c | 17 + .../drv_uart.h => rk3300/driver/board.h} | 10 +- bsp/rockchip/rk3300/rtconfig.h | 603 + bsp/rockchip/{rk3568 => rk3300}/rtconfig.py | 9 +- bsp/rockchip/rk3500/.config | 67 +- bsp/rockchip/rk3500/Kconfig | 29 +- bsp/rockchip/rk3500/README.md | 74 +- bsp/rockchip/rk3500/README_ZH.md | 65 +- bsp/rockchip/rk3500/SConscript | 2 + bsp/rockchip/rk3500/driver/Kconfig | 6 - bsp/rockchip/rk3500/driver/board.c | 23 +- bsp/rockchip/rk3500/driver/board.h | 9 - bsp/rockchip/rk3500/driver/clk/Kconfig | 15 - bsp/rockchip/rk3500/driver/clk/SConscript | 16 - .../rk3500/driver/clk/clk-pll-rk3568.c | 403 - .../rk3500/driver/clk/clk-pll-rk3588.c | 727 - bsp/rockchip/rk3500/driver/clk/clk-rk3568.c | 4791 - bsp/rockchip/rk3500/driver/clk/clk-rk3568.h | 116 - bsp/rockchip/rk3500/driver/clk/clk-rk3588.c | 3292 - bsp/rockchip/rk3500/driver/clk/clk-rk3588.h | 151 - bsp/rockchip/rk3500/driver/rockchip.h | 22 - bsp/rockchip/rk3500/driver/uart8250/Kconfig | 3 - .../rk3500/driver/uart8250/serial_dm.h | 29 - bsp/rockchip/rk3500/rtconfig.h | 36 +- bsp/rockchip/rk3500/rtconfig.py | 4 +- bsp/rockchip/rk3568/README.md | 55 - bsp/rockchip/rk3568/README_zh.md | 58 - bsp/rockchip/rk3568/driver/Kconfig | 59 - bsp/rockchip/rk3568/driver/board.c | 179 - bsp/rockchip/rk3568/driver/board.h | 27 - bsp/rockchip/rk3568/driver/drv_uart.c | 366 - bsp/rockchip/rk3568/driver/rk3568.h | 122 - .../libraries/HAL_Drivers/drivers/drv_can.c | 10 + .../libraries/HAL_Drivers/drivers/drv_gpio.h | 51 + .../libraries/HAL_Drivers/drivers/drv_qspi.c | 34 +- .../libraries/HAL_Drivers/drivers/drv_sdio.h | 2 - .../board/CubeMX_Config/.mxproject | 16 +- .../board/CubeMX_Config/CubeMX_Config.ioc | 124 +- .../board/CubeMX_Config/Inc/main.h | 2 + .../CubeMX_Config/Inc/stm32f4xx_hal_conf.h | 8 +- .../board/CubeMX_Config/Src/main.c | 251 +- .../CubeMX_Config/Src/stm32f4xx_hal_msp.c | 376 +- .../board/CubeMX_Config/Src/stm32f4xx_it.c | 114 +- .../CubeMX_Config/Src/system_stm32f4xx.c | 890 +- bsp/stm32/stm32f407-micu/board/Kconfig | 184 +- bsp/stm32/stm32f407-micu/board/board.c | 13 +- .../stm32f407-micu/board/ports/SConscript | 17 + .../board/ports/spi_flash_init.c | 32 + .../.ci/attachconfig/qspi-flash.attach | 31 + .../board/ports/drv_qspi_flash.c | 17 +- components/Kconfig | 2 +- components/SConscript | 10 +- components/dfs/Kconfig | 6 + .../dfs/dfs_v1/filesystems/9pfs/SConscript | 11 + .../dfs/dfs_v1/filesystems/9pfs/dfs_9pfs.c | 1186 + .../dfs/dfs_v1/filesystems/9pfs/dfs_9pfs.h | 247 + components/dfs/dfs_v1/include/dfs.h | 7 +- components/dfs/dfs_v1/src/dfs.c | 7 +- .../dfs/dfs_v2/filesystems/elmfat/dfs_elm.c | 7 +- .../dfs/dfs_v2/filesystems/tmpfs/dfs_tmpfs.c | 2 +- components/dfs/dfs_v2/src/dfs_dentry.c | 13 +- components/drivers/Kconfig | 7 + .../drivers/audio/utest/tc_audio_main.c | 45 +- components/drivers/block/blk_dfs.c | 6 +- components/drivers/can/Kconfig | 8 +- components/drivers/can/SConscript | 4 + components/drivers/can/can_dm.c | 45 + components/drivers/can/can_dm.h | 65 + components/drivers/clk/Kconfig | 6 + components/drivers/clk/SConscript | 12 +- components/drivers/clk/clk-fixed-rate.c | 80 +- components/drivers/clk/clk-scmi.c | 411 + components/drivers/clk/clk.c | 2143 +- components/drivers/core/SConscript | 2 +- components/drivers/core/dm.c | 44 +- components/drivers/core/platform.c | 18 + components/drivers/core/platform_ofw.c | 12 +- components/drivers/core/power.c | 311 + components/drivers/dma/Kconfig | 7 + components/drivers/dma/SConscript | 3 + components/drivers/dma/dma-pl330.c | 1045 + components/drivers/dma/dma.c | 133 +- components/drivers/dma/dma_pool.c | 48 +- components/drivers/firmware/Kconfig | 9 + components/drivers/firmware/SConscript | 15 + components/drivers/firmware/arm_scmi/Kconfig | 23 + .../drivers/firmware/arm_scmi/SConscript | 21 + .../drivers/firmware/arm_scmi/agent-mailbox.c | 176 + .../drivers/firmware/arm_scmi/agent-smc.c | 200 + components/drivers/firmware/arm_scmi/agent.c | 177 + components/drivers/firmware/arm_scmi/agent.h | 36 + components/drivers/firmware/arm_scmi/bus.c | 84 + components/drivers/firmware/arm_scmi/shmem.c | 110 + components/drivers/firmware/arm_scmi/shmem.h | 23 + components/drivers/graphic/Kconfig | 13 +- components/drivers/graphic/SConscript | 23 + components/drivers/graphic/backlight/Kconfig | 22 + .../drivers/graphic/backlight/SConscript | 20 + .../graphic/backlight/backlight-gpio.c | 135 + .../drivers/graphic/backlight/backlight-pwm.c | 569 + .../drivers/graphic/backlight/backlight.c | 231 + .../drivers/graphic/framebuffer/Kconfig | 14 + .../drivers/graphic/framebuffer/SConscript | 19 + .../drivers/graphic/framebuffer/fb-simple.c | 381 + components/drivers/graphic/graphic.c | 1495 + components/drivers/graphic/graphic_primary.c | 381 + components/drivers/graphic/graphic_simple.c | 295 + components/drivers/graphic/logo/.gitignore | 1 + components/drivers/graphic/logo/Kconfig | 37 + components/drivers/graphic/logo/SConscript | 90 + .../graphic/logo/logo-rt-thread-clut224.ppm | 1597 + .../logo/logo-rt-thread-white-clut224.ppm | 1597 + components/drivers/graphic/logo/logo.c | 216 + components/drivers/graphic/logo/logo.html | 243 + components/drivers/hwcache/Kconfig | 9 + components/drivers/hwcache/SConscript | 15 + components/drivers/hwcache/hwcache.c | 139 + components/drivers/hwcrypto/Kconfig | 4 + components/drivers/hwspinlock/Kconfig | 15 + components/drivers/hwspinlock/SConscript | 15 + components/drivers/hwspinlock/hwspinlock.c | 319 + components/drivers/hwspinlock/hwspinlock_dm.h | 125 + components/drivers/hwtimer/Kconfig | 4 + components/drivers/hwtimer/hwtimer-arm_arch.c | 26 +- components/drivers/i2c/Kconfig | 6 +- components/drivers/i2c/dev_i2c_bus.c | 2 + .../drivers/include/drivers/backlight.h | 73 + components/drivers/include/drivers/clk.h | 205 +- components/drivers/include/drivers/core/dm.h | 12 + .../drivers/include/drivers/core/master_id.h | 2 +- .../drivers/include/drivers/core/power.h | 47 + components/drivers/include/drivers/dev_i2c.h | 15 + .../drivers/include/drivers/dev_mmcsd_core.h | 6 + components/drivers/include/drivers/dev_pin.h | 1 + components/drivers/include/drivers/dev_pwm.h | 8 + .../drivers/include/drivers/dev_sdhci.h | 668 + .../drivers/include/drivers/dev_sdhci_host.h | 310 + components/drivers/include/drivers/dma.h | 16 +- components/drivers/include/drivers/graphic.h | 367 + components/drivers/include/drivers/hwcache.h | 48 + .../drivers/include/drivers/hwspinlock.h | 180 + components/drivers/include/drivers/input.h | 153 + .../drivers/include/drivers/input_uapi.h | 67 + components/drivers/include/drivers/lcd.h | 33 + components/drivers/include/drivers/misc.h | 71 +- .../drivers/include/drivers/mmcsd_host.h | 25 +- components/drivers/include/drivers/nvmem.h | 81 + .../drivers/include/drivers/power_supply.h | 277 + .../drivers/include/drivers/regulator.h | 4 + components/drivers/include/drivers/scmi.h | 1092 + components/drivers/include/drivers/scsi.h | 1 + .../include/dt-bindings/input/event-codes.h | 360 + components/drivers/include/rtdevice.h | 45 +- components/drivers/input/Kconfig | 36 + components/drivers/input/SConscript | 32 + components/drivers/input/input.c | 405 + components/drivers/input/input_power.c | 130 + components/drivers/input/input_touch.c | 453 + components/drivers/input/input_uapi.c | 399 + components/drivers/input/joystick/Kconfig | 7 + components/drivers/input/joystick/SConscript | 15 + components/drivers/input/keyboard/Kconfig | 13 + components/drivers/input/keyboard/SConscript | 18 + components/drivers/input/keyboard/keys-gpio.c | 163 + components/drivers/input/misc/Kconfig | 12 + components/drivers/input/misc/SConscript | 18 + components/drivers/input/misc/button-e3x0.c | 115 + components/drivers/input/touchscreen/Kconfig | 8 + .../drivers/input/touchscreen/SConscript | 15 + components/drivers/ipc/utest/completion_tc.c | 35 +- .../drivers/ipc/utest/completion_timeout_tc.c | 44 +- components/drivers/ipc/utest/workqueue_tc.c | 36 + components/drivers/led/Kconfig | 13 + components/drivers/led/SConscript | 6 + components/drivers/led/led-gpio.c | 2 +- components/drivers/led/led-pwm.c | 303 + components/drivers/led/led-syscon.c | 186 + components/drivers/led/led.c | 29 +- components/drivers/mfd/Kconfig | 13 +- components/drivers/mfd/SConscript | 3 + components/drivers/mfd/mfd-edu.c | 332 + components/drivers/misc/Kconfig | 12 +- components/drivers/misc/adc.c | 4 +- components/drivers/misc/rt_drv_pwm.c | 2 +- components/drivers/mtd/Kconfig | 21 +- components/drivers/mtd/SConscript | 6 + components/drivers/mtd/mtd-cfi.c | 1336 + components/drivers/mtd/mtd-cfi.h | 166 + components/drivers/mtd/mtd-spi-nor.c | 98 + components/drivers/nvmem/Kconfig | 12 + components/drivers/nvmem/SConscript | 15 + components/drivers/nvmem/nvmem.c | 548 + components/drivers/ofw/base.c | 1 - components/drivers/ofw/fdt.c | 8 + components/drivers/ofw/io.c | 1 - components/drivers/ofw/irq.c | 10 +- components/drivers/ofw/ofw.c | 21 +- components/drivers/ofw/raw.c | 2 + components/drivers/pci/endpoint/mem.c | 1 + components/drivers/phy/Kconfig | 8 +- components/drivers/phy/general.c | 7 +- components/drivers/phy/ofw.c | 2 +- components/drivers/phye/Kconfig | 9 + components/drivers/phye/SConscript | 3 + components/drivers/phye/phye-generic-usb.c | 232 + components/drivers/pic/pic.c | 10 +- components/drivers/pin/Kconfig | 8 +- components/drivers/pin/SConscript | 3 + components/drivers/pin/dev_pin_dm.c | 17 + components/drivers/pin/dev_pin_dm.h | 38 + components/drivers/pin/pin-pl061.c | 357 + components/drivers/pinctrl/Kconfig | 11 + components/drivers/pinctrl/SConscript | 15 +- components/drivers/pinctrl/pinctrl-scmi.c | 485 + components/drivers/pinctrl/pinctrl-single.c | 384 + components/drivers/pmdomain/Kconfig | 11 + components/drivers/pmdomain/SConscript | 18 + components/drivers/pmdomain/pm-domain-scmi.c | 134 + components/drivers/power/Kconfig | 2 + components/drivers/power/SConscript | 11 + components/drivers/power/reset/Kconfig | 39 + components/drivers/power/reset/SConscript | 33 + .../drivers/power/reset/gpio-poweroff.c | 100 + components/drivers/power/reset/gpio-restart.c | 100 + components/drivers/power/reset/reboot-mode.c | 105 + components/drivers/power/reset/reboot-mode.h | 27 + .../drivers/power/reset/syscon-poweroff.c | 104 + .../drivers/power/reset/syscon-reboot-mode.c | 115 + .../drivers/power/reset/syscon-reboot.c | 104 + components/drivers/power/supply/Kconfig | 35 + components/drivers/power/supply/SConscript | 24 + components/drivers/power/supply/emu-power.c | 379 + .../drivers/power/supply/gpio-charger.c | 346 + .../drivers/power/supply/supply-daemon.c | 179 + components/drivers/power/supply/supply.c | 694 + components/drivers/regulator/Kconfig | 7 + components/drivers/regulator/SConscript | 3 + components/drivers/regulator/regulator-scmi.c | 206 + components/drivers/regulator/regulator.c | 65 +- components/drivers/regulator/regulator_dm.c | 19 + components/drivers/reset/Kconfig | 6 + components/drivers/reset/SConscript | 3 + components/drivers/reset/reset-scmi.c | 129 + components/drivers/rtc/Kconfig | 62 +- components/drivers/rtc/SConscript | 27 + components/drivers/rtc/dev_soft_rtc.c | 309 +- components/drivers/rtc/rtc-ds1302.c | 256 + components/drivers/rtc/rtc-ds1307.c | 643 + components/drivers/rtc/rtc-goldfish.c | 270 + components/drivers/rtc/rtc-hym8563.c | 767 + components/drivers/rtc/rtc-pcf8523.c | 538 + components/drivers/rtc/rtc-pcf8563.c | 673 + components/drivers/rtc/rtc-pl031.c | 294 + components/drivers/rtc/rtc-rx8010.c | 637 + components/drivers/rtc/rtc_dm.c | 61 + components/drivers/rtc/rtc_dm.h | 24 + components/drivers/scsi/scsi_cdrom.c | 2 +- components/drivers/scsi/scsi_sd.c | 2 +- components/drivers/sdio/Kconfig | 10 +- components/drivers/sdio/SConscript | 41 +- components/drivers/sdio/dev_mmc.c | 121 +- components/drivers/sdio/dev_mmcsd_core.c | 288 + components/drivers/sdio/dev_regulator.c | 262 + components/drivers/sdio/dev_sd.c | 42 +- .../sdio/{sdhci/sdhci.c => dev_sdhci.c} | 1539 +- .../sdhci-platform.c => dev_sdhci_dm.c} | 82 +- components/drivers/sdio/dev_sdhci_dm.h | 68 + .../{sdhci/fit-mmc.c => dev_sdhci_host.c} | 184 +- components/drivers/sdio/dev_sdio_dm.c | 157 + components/drivers/sdio/dev_sdio_dm.h | 39 + components/drivers/sdio/host/Kconfig | 22 + components/drivers/sdio/host/SConscript | 24 + components/drivers/sdio/host/sdhci-pci.c | 113 + components/drivers/sdio/host/sdio-dw-pci.c | 100 + .../drivers/sdio/host/sdio-dw-platform.c | 110 + .../drivers/sdio/host/sdio-dw-platform.h | 19 + components/drivers/sdio/host/sdio-dw.c | 3265 + components/drivers/sdio/host/sdio-dw.h | 362 + .../sdio/sdhci/include/sdhci-platform.h | 66 - components/drivers/sdio/sdhci/include/sdhci.h | 677 - .../drivers/sdio/sdhci/include/sdhci_host.h | 345 - .../drivers/sdio/sdhci/include/sdhci_misc.h | 70 - components/drivers/serial/Kconfig | 6 +- components/drivers/serial/dev_serial.c | 5 - .../drivers/serial/device/8250}/8250-dw.c | 44 +- .../drivers/serial/device/8250/8250-ofw.c | 211 + .../drivers/serial/device/8250/8250-pci.c | 169 + .../drivers/serial/device/8250}/8250.h | 16 +- components/drivers/serial/device/8250/Kconfig | 14 + .../drivers/serial/device/8250/SConscript | 23 + .../drivers/serial/device/8250}/core.c | 259 +- .../drivers/serial/device/8250}/early.c | 8 +- .../drivers/serial/device/8250}/regs.h | 2 +- components/drivers/serial/device/Kconfig | 12 + components/drivers/serial/device/SConscript | 25 + .../drivers/serial/device/serial-early-hvc.c | 34 + .../drivers/serial/device/serial-pl011.c | 417 + .../drivers/serial/device/virtual/.gitignore | 1 + .../drivers/serial/device/virtual/Kconfig | 17 + .../drivers/serial/device/virtual/SConscript | 39 + .../device/virtual/font-uni2-fixed16.psf | Bin 0 -> 10804 bytes .../serial/device/virtual/font-uni2-vga16.psf | Bin 0 -> 10804 bytes .../drivers/serial/device/virtual/psf.c | 105 + .../drivers/serial/device/virtual/psf.h | 92 + .../drivers/serial/device/virtual/render.c | 661 + .../drivers/serial/device/virtual/render.h | 60 + .../drivers/serial/device/virtual/virtual.c | 789 + components/drivers/serial/serial_dm.c | 8 +- components/drivers/serial/serial_tty.c | 6 +- .../serial/utest/bypass/bypass_conflict.c | 39 + .../serial/utest/bypass/bypass_lower_run.c | 35 + .../serial/utest/bypass/bypass_register.c | 39 + .../serial/utest/bypass/bypass_upper_run.c | 36 + .../drivers/smp_call/utest/smp_001_tc.c | 36 + .../drivers/smp_call/utest/smp_002_tc.c | 32 + .../drivers/smp_call/utest/smp_003_tc.c | 32 + .../drivers/smp_call/utest/smp_004_tc.c | 37 +- components/drivers/spi/Kconfig | 5 + components/drivers/spi/SConscript | 13 +- components/drivers/spi/dev_soft_spi.c | 2 +- .../drivers/spi/sfud/inc/sfud_flash_def.h | 1 + components/drivers/thermal/Kconfig | 6 + components/drivers/thermal/SConscript | 3 + components/drivers/thermal/thermal-scmi.c | 170 + components/drivers/virtio/virtio.c | 15 +- components/fal/src/fal_rtt.c | 42 +- components/finsh/cmd.c | 78 +- components/finsh/msh.c | 42 +- components/finsh/msh_file.c | 50 +- components/finsh/shell.c | 18 +- .../libc/cplusplus/os/cxx_Semaphore.cpp | 16 + components/libc/cplusplus/os/cxx_Thread.cpp | 46 +- components/libc/cplusplus/utest/tc_atomic.cpp | 49 +- .../libc/cplusplus/utest/tc_smartptr.cpp | 15 +- components/libc/cplusplus/utest/tc_thread.cpp | 31 +- components/libc/posix/io/aio/aio.c | 2 +- components/libc/posix/libdl/dlelf.c | 6 +- components/mm/Kconfig | 7 + components/mm/mm_aspace.c | 2 +- components/mm/mm_memblock.c | 9 +- components/mm/mm_page.c | 25 +- components/mm/mm_page.h | 5 + components/net/at/at_socket/at_socket.c | 11 +- components/rust/Kconfig | 26 + components/rust/README.md | 187 + components/rust/README_zh.md | 191 + components/rust/SConscript | 28 + components/rust/core/.gitignore | 37 + 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| 421 + examples/test/dma_test.c | 146 + examples/utest/configs/smp/smp.cfg | 10 +- examples/utest/testcases/mm/mm_api_tc.c | 35 + examples/utest/testcases/mm/mm_lwp_tc.c | 36 + libcpu/aarch64/common/builtin_fdt_gcc.S | 20 + libcpu/aarch64/common/psci.c | 23 +- libcpu/aarch64/common/setup.c | 108 +- libcpu/aarch64/common/trap.c | 3 + libcpu/aarch64/cortex-a/entry_point.S | 8 +- libcpu/arm/cortex-a/gic.c | 343 +- libcpu/arm/cortex-a/mmu.c | 2 +- libcpu/arm/cortex-a/mmu.h | 108 +- libcpu/arm/cortex-a/start_gcc.S | 97 +- libcpu/risc-v/common/trap_common.c | 24 +- libcpu/risc-v/common64/SConscript | 2 + libcpu/risc-v/common64/context_gcc.S | 35 +- libcpu/risc-v/common64/cpuport.c | 129 +- libcpu/risc-v/common64/cpuport.h | 4 + libcpu/risc-v/common64/encoding.h | 2 + libcpu/risc-v/common64/interrupt_gcc.S | 23 + libcpu/risc-v/common64/mmu.c | 362 +- libcpu/risc-v/common64/mmu.h | 9 + libcpu/risc-v/common64/startup_gcc.S | 106 + libcpu/risc-v/common64/trap.c | 164 +- libcpu/risc-v/virt64/interrupt.c | 148 +- libcpu/risc-v/virt64/interrupt.h | 9 +- src/Kconfig | 2 +- src/components.c | 5 + src/object.c | 10 +- src/thread.c | 44 +- src/utest/atomic_tc.c | 30 +- src/utest/event_tc.c | 31 +- src/utest/mailbox_tc.c | 37 + src/utest/messagequeue_tc.c | 38 + src/utest/mtsafe_kprint_tc.c | 33 +- src/utest/mutex_pi_tc.c | 31 + src/utest/mutex_tc.c | 31 + src/utest/object_tc.c | 542 +- src/utest/perf/perf_tc.c | 50 +- src/utest/sched_mtx_tc.c | 49 + src/utest/sched_sem_tc.c | 53 + src/utest/sched_thread_tc.c | 51 + src/utest/sched_timed_mtx_tc.c | 47 + src/utest/sched_timed_sem_tc.c | 49 + src/utest/smp/smp_affinity_pri1_tc.c | 28 +- src/utest/smp/smp_affinity_pri2_tc.c | 27 +- src/utest/smp/smp_assigned_idle_cores_tc.c | 55 +- src/utest/smp/smp_bind_affinity_tc.c | 23 + src/utest/smp/smp_interrupt_pri_tc.c | 32 + src/utest/smp/smp_spinlock_tc.c | 21 + src/utest/smp/smp_thread_preemption_tc.c | 27 + src/utest/timer_tc.c | 33 + tools/building.py | 4 +- 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mode 100644 bsp/rockchip/rk3568/driver/rk3568.h create mode 100644 bsp/stm32/stm32f407-micu/board/ports/SConscript create mode 100644 bsp/stm32/stm32f407-micu/board/ports/spi_flash_init.c create mode 100644 bsp/stm32/stm32l475-atk-pandora/.ci/attachconfig/qspi-flash.attach create mode 100644 components/dfs/dfs_v1/filesystems/9pfs/SConscript create mode 100644 components/dfs/dfs_v1/filesystems/9pfs/dfs_9pfs.c create mode 100644 components/dfs/dfs_v1/filesystems/9pfs/dfs_9pfs.h create mode 100644 components/drivers/can/can_dm.c create mode 100644 components/drivers/can/can_dm.h create mode 100755 components/drivers/clk/clk-scmi.c create mode 100644 components/drivers/core/power.c create mode 100644 components/drivers/dma/dma-pl330.c create mode 100755 components/drivers/firmware/Kconfig create mode 100755 components/drivers/firmware/SConscript create mode 100755 components/drivers/firmware/arm_scmi/Kconfig create mode 100755 components/drivers/firmware/arm_scmi/SConscript create mode 100755 components/drivers/firmware/arm_scmi/agent-mailbox.c create mode 100755 components/drivers/firmware/arm_scmi/agent-smc.c create mode 100755 components/drivers/firmware/arm_scmi/agent.c create mode 100755 components/drivers/firmware/arm_scmi/agent.h create mode 100755 components/drivers/firmware/arm_scmi/bus.c create mode 100755 components/drivers/firmware/arm_scmi/shmem.c create mode 100755 components/drivers/firmware/arm_scmi/shmem.h create mode 100644 components/drivers/graphic/SConscript create mode 100644 components/drivers/graphic/backlight/Kconfig create mode 100644 components/drivers/graphic/backlight/SConscript create mode 100644 components/drivers/graphic/backlight/backlight-gpio.c create mode 100644 components/drivers/graphic/backlight/backlight-pwm.c create mode 100644 components/drivers/graphic/backlight/backlight.c create mode 100644 components/drivers/graphic/framebuffer/Kconfig create mode 100644 components/drivers/graphic/framebuffer/SConscript create mode 100644 components/drivers/graphic/framebuffer/fb-simple.c create mode 100644 components/drivers/graphic/graphic.c create mode 100644 components/drivers/graphic/graphic_primary.c create mode 100644 components/drivers/graphic/graphic_simple.c create mode 100644 components/drivers/graphic/logo/.gitignore create mode 100644 components/drivers/graphic/logo/Kconfig create mode 100644 components/drivers/graphic/logo/SConscript create mode 100644 components/drivers/graphic/logo/logo-rt-thread-clut224.ppm create mode 100644 components/drivers/graphic/logo/logo-rt-thread-white-clut224.ppm create mode 100644 components/drivers/graphic/logo/logo.c create mode 100644 components/drivers/graphic/logo/logo.html create mode 100644 components/drivers/hwcache/Kconfig create mode 100644 components/drivers/hwcache/SConscript create mode 100644 components/drivers/hwcache/hwcache.c create mode 100644 components/drivers/hwspinlock/Kconfig create mode 100644 components/drivers/hwspinlock/SConscript create mode 100644 components/drivers/hwspinlock/hwspinlock.c create mode 100644 components/drivers/hwspinlock/hwspinlock_dm.h create mode 100755 components/drivers/include/drivers/backlight.h create mode 100644 components/drivers/include/drivers/core/power.h create mode 100755 components/drivers/include/drivers/dev_sdhci.h create mode 100755 components/drivers/include/drivers/dev_sdhci_host.h create mode 100644 components/drivers/include/drivers/graphic.h create mode 100644 components/drivers/include/drivers/hwcache.h create mode 100644 components/drivers/include/drivers/hwspinlock.h create mode 100755 components/drivers/include/drivers/input.h create mode 100755 components/drivers/include/drivers/input_uapi.h create mode 100644 components/drivers/include/drivers/nvmem.h create mode 100644 components/drivers/include/drivers/power_supply.h create mode 100755 components/drivers/include/drivers/scmi.h create mode 100644 components/drivers/include/dt-bindings/input/event-codes.h create mode 100644 components/drivers/input/Kconfig create mode 100644 components/drivers/input/SConscript create mode 100644 components/drivers/input/input.c create mode 100644 components/drivers/input/input_power.c create mode 100644 components/drivers/input/input_touch.c create mode 100644 components/drivers/input/input_uapi.c create mode 100644 components/drivers/input/joystick/Kconfig create mode 100644 components/drivers/input/joystick/SConscript create mode 100644 components/drivers/input/keyboard/Kconfig create mode 100644 components/drivers/input/keyboard/SConscript create mode 100644 components/drivers/input/keyboard/keys-gpio.c create mode 100644 components/drivers/input/misc/Kconfig create mode 100644 components/drivers/input/misc/SConscript create mode 100644 components/drivers/input/misc/button-e3x0.c create mode 100644 components/drivers/input/touchscreen/Kconfig create mode 100644 components/drivers/input/touchscreen/SConscript create mode 100644 components/drivers/led/led-pwm.c create mode 100644 components/drivers/led/led-syscon.c create mode 100644 components/drivers/mfd/mfd-edu.c create mode 100644 components/drivers/mtd/mtd-cfi.c create mode 100644 components/drivers/mtd/mtd-cfi.h create mode 100644 components/drivers/mtd/mtd-spi-nor.c create mode 100644 components/drivers/nvmem/Kconfig create mode 100644 components/drivers/nvmem/SConscript create mode 100644 components/drivers/nvmem/nvmem.c create mode 100644 components/drivers/phye/phye-generic-usb.c create mode 100644 components/drivers/pin/pin-pl061.c create mode 100755 components/drivers/pinctrl/pinctrl-scmi.c create mode 100644 components/drivers/pinctrl/pinctrl-single.c create mode 100644 components/drivers/pmdomain/Kconfig create mode 100644 components/drivers/pmdomain/SConscript create mode 100755 components/drivers/pmdomain/pm-domain-scmi.c create mode 100644 components/drivers/power/Kconfig create mode 100644 components/drivers/power/SConscript create mode 100644 components/drivers/power/reset/Kconfig create mode 100644 components/drivers/power/reset/SConscript create mode 100644 components/drivers/power/reset/gpio-poweroff.c create mode 100644 components/drivers/power/reset/gpio-restart.c create mode 100644 components/drivers/power/reset/reboot-mode.c create mode 100644 components/drivers/power/reset/reboot-mode.h create mode 100644 components/drivers/power/reset/syscon-poweroff.c create mode 100644 components/drivers/power/reset/syscon-reboot-mode.c create mode 100644 components/drivers/power/reset/syscon-reboot.c create mode 100644 components/drivers/power/supply/Kconfig create mode 100644 components/drivers/power/supply/SConscript create mode 100644 components/drivers/power/supply/emu-power.c create mode 100644 components/drivers/power/supply/gpio-charger.c create mode 100644 components/drivers/power/supply/supply-daemon.c create mode 100644 components/drivers/power/supply/supply.c create mode 100755 components/drivers/regulator/regulator-scmi.c create mode 100755 components/drivers/reset/reset-scmi.c create mode 100644 components/drivers/rtc/rtc-ds1302.c create mode 100644 components/drivers/rtc/rtc-ds1307.c create mode 100644 components/drivers/rtc/rtc-goldfish.c create mode 100644 components/drivers/rtc/rtc-hym8563.c create mode 100644 components/drivers/rtc/rtc-pcf8523.c create mode 100644 components/drivers/rtc/rtc-pcf8563.c create mode 100644 components/drivers/rtc/rtc-pl031.c create mode 100644 components/drivers/rtc/rtc-rx8010.c create mode 100644 components/drivers/rtc/rtc_dm.c create mode 100644 components/drivers/rtc/rtc_dm.h create mode 100755 components/drivers/sdio/dev_regulator.c rename components/drivers/sdio/{sdhci/sdhci.c => dev_sdhci.c} (73%) mode change 100644 => 100755 rename components/drivers/sdio/{sdhci/sdhci-platform.c => dev_sdhci_dm.c} (58%) mode change 100644 => 100755 create mode 100755 components/drivers/sdio/dev_sdhci_dm.h rename components/drivers/sdio/{sdhci/fit-mmc.c => dev_sdhci_host.c} (55%) mode change 100644 => 100755 create mode 100755 components/drivers/sdio/dev_sdio_dm.c create mode 100755 components/drivers/sdio/dev_sdio_dm.h create mode 100755 components/drivers/sdio/host/Kconfig create mode 100755 components/drivers/sdio/host/SConscript create mode 100755 components/drivers/sdio/host/sdhci-pci.c create mode 100755 components/drivers/sdio/host/sdio-dw-pci.c create mode 100755 components/drivers/sdio/host/sdio-dw-platform.c create mode 100755 components/drivers/sdio/host/sdio-dw-platform.h create mode 100755 components/drivers/sdio/host/sdio-dw.c create mode 100755 components/drivers/sdio/host/sdio-dw.h delete mode 100644 components/drivers/sdio/sdhci/include/sdhci-platform.h delete mode 100644 components/drivers/sdio/sdhci/include/sdhci.h delete mode 100644 components/drivers/sdio/sdhci/include/sdhci_host.h delete mode 100644 components/drivers/sdio/sdhci/include/sdhci_misc.h rename {bsp/rockchip/rk3500/driver/uart8250 => components/drivers/serial/device/8250}/8250-dw.c (87%) create mode 100644 components/drivers/serial/device/8250/8250-ofw.c create mode 100644 components/drivers/serial/device/8250/8250-pci.c rename {bsp/rockchip/rk3500/driver/uart8250 => components/drivers/serial/device/8250}/8250.h (73%) create mode 100644 components/drivers/serial/device/8250/Kconfig create mode 100644 components/drivers/serial/device/8250/SConscript rename {bsp/rockchip/rk3500/driver/uart8250 => components/drivers/serial/device/8250}/core.c (50%) rename {bsp/rockchip/rk3500/driver/uart8250 => components/drivers/serial/device/8250}/early.c (95%) rename {bsp/rockchip/rk3500/driver/uart8250 => components/drivers/serial/device/8250}/regs.h (99%) create mode 100644 components/drivers/serial/device/Kconfig create mode 100644 components/drivers/serial/device/SConscript create mode 100644 components/drivers/serial/device/serial-early-hvc.c create mode 100644 components/drivers/serial/device/serial-pl011.c create mode 100644 components/drivers/serial/device/virtual/.gitignore create mode 100644 components/drivers/serial/device/virtual/Kconfig create mode 100644 components/drivers/serial/device/virtual/SConscript create mode 100644 components/drivers/serial/device/virtual/font-uni2-fixed16.psf create mode 100644 components/drivers/serial/device/virtual/font-uni2-vga16.psf create mode 100644 components/drivers/serial/device/virtual/psf.c create mode 100644 components/drivers/serial/device/virtual/psf.h create mode 100644 components/drivers/serial/device/virtual/render.c create mode 100644 components/drivers/serial/device/virtual/render.h create mode 100644 components/drivers/serial/device/virtual/virtual.c create mode 100755 components/drivers/thermal/thermal-scmi.c create mode 100644 components/rust/Kconfig create mode 100644 components/rust/README.md create mode 100644 components/rust/README_zh.md create mode 100644 components/rust/SConscript create mode 100644 components/rust/core/.gitignore create mode 100644 components/rust/core/Cargo.toml create mode 100644 components/rust/core/SConscript create mode 100644 components/rust/core/rust_cmd.c create mode 100644 components/rust/core/src/allocator.rs create mode 100644 components/rust/core/src/api/base.rs create mode 100644 components/rust/core/src/api/interrupt.rs create mode 100644 components/rust/core/src/api/libloading.rs create mode 100644 components/rust/core/src/api/mem.rs create mode 100644 components/rust/core/src/api/mod.rs create mode 100644 components/rust/core/src/api/mutex.rs create mode 100644 components/rust/core/src/api/queue.rs create mode 100644 components/rust/core/src/api/sem.rs create mode 100644 components/rust/core/src/api/thread.rs create mode 100644 components/rust/core/src/bindings/libc.rs create mode 100644 components/rust/core/src/bindings/librt.rs create mode 100644 components/rust/core/src/bindings/mod.rs create mode 100644 components/rust/core/src/fs.rs create mode 100644 components/rust/core/src/init.rs create mode 100644 components/rust/core/src/lib.rs create mode 100644 components/rust/core/src/libloader.rs create mode 100644 components/rust/core/src/mutex.rs create mode 100644 components/rust/core/src/out.rs create mode 100644 components/rust/core/src/panic.rs create mode 100644 components/rust/core/src/param.rs create mode 100644 components/rust/core/src/prelude/mod.rs create mode 100644 components/rust/core/src/prelude/no_std.rs create mode 100644 components/rust/core/src/queue.rs create mode 100644 components/rust/core/src/sem.rs create mode 100644 components/rust/core/src/thread.rs create mode 100644 components/rust/core/src/time.rs create mode 100644 components/rust/docs/1.tools/README.md create mode 100644 components/rust/docs/1.tools/README_zh.md create mode 100644 components/rust/docs/2.applications/README.md create mode 100644 components/rust/docs/2.applications/README_zh.md create mode 100644 components/rust/docs/3.components/README.md create mode 100644 components/rust/docs/3.components/README_zh.md create mode 100644 components/rust/docs/4.modules/README.md create mode 100644 components/rust/docs/4.modules/README_zh.md create mode 100644 components/rust/docs/5.rt-macro/README.md create mode 100644 components/rust/docs/5.rt-macro/README_zh.md create mode 100644 components/rust/examples/Kconfig create mode 100644 components/rust/examples/SConscript create mode 100644 components/rust/examples/application/SConscript create mode 100644 components/rust/examples/application/fs/Cargo.toml create mode 100644 components/rust/examples/application/fs/src/lib.rs create mode 100644 components/rust/examples/application/loadlib/Cargo.toml create mode 100644 components/rust/examples/application/loadlib/src/lib.rs create mode 100644 components/rust/examples/application/mutex/Cargo.toml create mode 100644 components/rust/examples/application/mutex/src/lib.rs create mode 100644 components/rust/examples/application/param/Cargo.toml create mode 100644 components/rust/examples/application/param/src/lib.rs create mode 100644 components/rust/examples/application/queue/Cargo.toml create mode 100644 components/rust/examples/application/queue/src/lib.rs create mode 100644 components/rust/examples/application/semaphore/Cargo.toml create mode 100644 components/rust/examples/application/semaphore/src/lib.rs create mode 100644 components/rust/examples/application/thread/Cargo.toml create mode 100644 components/rust/examples/application/thread/src/lib.rs create mode 100644 components/rust/examples/component/SConscript create mode 100644 components/rust/examples/component/component_registry/Cargo.toml create mode 100644 components/rust/examples/component/component_registry/src/lib.rs create mode 100644 components/rust/examples/component/log/Cargo.toml create mode 100644 components/rust/examples/component/log/src/lib.rs create mode 100644 components/rust/examples/component/log/src/logging.rs create mode 100644 components/rust/examples/modules/SConscript create mode 100644 components/rust/examples/modules/example_lib/.gitignore create mode 100644 components/rust/examples/modules/example_lib/Cargo.toml create mode 100644 components/rust/examples/modules/example_lib/src/lib.rs create mode 100644 components/rust/rt_macros/Cargo.toml create mode 100644 components/rust/rt_macros/src/lib.rs create mode 100644 components/rust/rt_macros/src/macros/app.rs create mode 100644 components/rust/rt_macros/src/macros/cmd.rs create mode 100644 components/rust/rt_macros/src/macros/component.rs create mode 100644 components/rust/rt_macros/src/macros/main.rs create mode 100644 components/rust/rt_macros/src/macros/mod.rs create mode 100644 components/rust/tools/__init__.py create mode 100644 components/rust/tools/build_component.py create mode 100644 components/rust/tools/build_support.py create mode 100644 components/rust/tools/build_usrapp.py create mode 100644 components/rust/tools/feature_config_component.py create mode 100644 components/rust/tools/feature_config_examples.py create mode 100644 examples/test/dm_graphic_test.c create mode 100644 examples/test/dm_hmi_test.c create mode 100644 examples/test/dma_test.c create mode 100755 libcpu/aarch64/common/builtin_fdt_gcc.S diff --git a/.github/ALL_BSP_COMPILE.json b/.github/ALL_BSP_COMPILE.json index dfce1fbb500..6d503086dd2 100644 --- a/.github/ALL_BSP_COMPILE.json +++ b/.github/ALL_BSP_COMPILE.json @@ -73,6 +73,7 @@ "asm9260t", "allwinner_tina", "ft32/ft32f072xb-starter", + "ft32/ft32f407xe-starter", "mini2440", "at91/at91sam9g45", "at91/at91sam9260", @@ -248,7 +249,7 @@ "nxp/mcx/mcxc/frdm-mcxc444", "nxp/mcx/mcxa/frdm-mcxa153", "nxp/mcx/mcxa/frdm-mcxa156", - "nxp/mcx/mcxa/frdm-mcxa346", + "nxp/mcx/mcxa/frdm-mcxa346", "nxp/mcx/mcxe/frdm-mcxe247", "renesas/ebf_qi_min_6m5", "renesas/ra6m4-cpk", @@ -258,12 +259,13 @@ "renesas/ra6e2-ek", "renesas/ra6e2-fpb", "renesas/ra4e2-eco", - "renesas/ra4m1-ek", + "renesas/ra4m1-ek", "renesas/ra4m2-eco", "renesas/ra2l1-cpk", "renesas/ra8m1-ek", "renesas/ra8d1-ek", "renesas/ra8d1-vision-board", + "renesas/ra8p1-titan-board", "renesas/rzt2m_rsk", "renesas/rzn2l_rsk", "renesas/rzn2l_etherkit", @@ -386,7 +388,8 @@ "SUB_RTT_BSP": [ "qemu-virt64-aarch64", "raspberry-pi/raspi3-64", - "raspberry-pi/raspi4-64" + "raspberry-pi/raspi4-64", + "nxp/imx/imx91" ] }, { @@ -396,7 +399,8 @@ "k210", "wch/risc-v/ch32v208w-r0", "wch/risc-v/ch32v307v-r1", - "wch/risc-v/yd-ch32v307vct6" + "wch/risc-v/yd-ch32v307vct6", + "gd32/risc-v/gd32vw553h-eval" ] }, { diff --git a/.github/copilot-instructions.md b/.github/copilot-instructions.md index ead5d3e1c18..d772775c301 100644 --- a/.github/copilot-instructions.md +++ b/.github/copilot-instructions.md @@ -6,6 +6,8 @@ RT-Thread is a real-time operating system (RTOS) for embedded devices. When work RT-Thread 是一个面向嵌入式设备的实时操作系统（RTOS）。在处理 RT-Thread 代码时，请遵循以下指南以确保高质量的贡献。 +**When reviewing Pull Requests (PRs), you MUST check all items in the PR Review Checklist section and provide feedback according to the PR Review Instructions. / 在审查 Pull Request (PR) 时，必须检查 PR 审查清单部分中的所有项目，并根据 PR 审查指令提供反馈。** + ## Code Review Guidelines / 代码审查指南 ### Language Requirements / 语言要求 @@ -26,21 +28,162 @@ When reviewing code, provide feedback in **both English and Chinese** to ensure - Follow RT-Thread coding standards / 遵循 RT-Thread 编码标准 - Maintain consistent naming conventions / 保持一致的命名约定 - Ensure proper code comments (not documentation) / 确保适当的代码注释（而非文档） -4. **PR Title Naming Guidelines / PR 标题命名规范** - - **Specify the module or keyword / 明确模块或关键字**： - - 标题需明确指出涉及的具体模块、子系统或关键字，例如具体的 BSP（Board Support Package）或芯片厂商名称（如 STM32, ESP32, NXP 等）。 - - 示例：[STM32][I2C] Fix Kconfig parsing error 而非 fix:I2C——Kconfig修改。 - - **Clearly describe the content being repaired or modified / 清晰描述修复或更改内容**： - - 标题需简洁清晰地描述修复的问题、添加的功能或修改的内容，避免模糊或过于简略的描述。 - - 示例：[STM32][SPI] Fix buffer overflow in SPI driver 而非 SPI bug fix。 - - **Format Recommendations / 格式建议**： - - 推荐使用 [模块/厂商][子系统] 具体描述 的格式，确保标题结构化且信息完整。 - - 使用英文描述问题（除非项目明确要求使用其他语言），以提高国际化可读性。 - - 示例：[NXP][UART] Add timeout handling for UART receive。 - - **Issues to Avoid / 避免的问题**： - - 不要使用模糊的术语，如“修复问题”或“代码优化”，需具体说明问题或优化的内容。 - - 避免使用不规范的符号（如 ——），建议使用标准英文字符（如 - 或 :）。 - - 不要省略关键上下文信息，如 BSP 或芯片厂商。 +4. **PR Review Checklist / PR 审查清单** + - **PR Title Review / PR 标题审查**： + - Check if PR title has proper prefix format / 检查 PR 标题是否有正确的前缀格式 + - Verify prefix follows pattern: `[module/vendor][subsystem]` or `[module/vendor]` in lowercase / 验证前缀遵循格式：小写的 `[模块/厂商][子系统]` 或 `[模块/厂商]` + - Verify title describes changes based on modified files / 验证标题基于修改的文件描述变更 + - Check if title is specific enough (avoid vague terms like "fix bug", "optimize code") / 检查标题是否足够具体（避免模糊术语如"修复问题"、"代码优化"） + - If title lacks prefix or uses incorrect format, suggest: "PR title should follow format: `[module][subsystem] Description`. Example: `[stm32][drivers] Fix UART interrupt handling issue`" / 如果标题缺少前缀或格式错误，建议："PR 标题应遵循格式：`[模块][子系统] 描述`。示例：`[stm32][drivers] Fix UART interrupt handling issue`" + - **PR Description Review / PR 内容审查**： + - Check if PR description provides overview of modified files / 检查 PR 描述是否提供了修改文件的总概 + - Verify description explains: What (what changes), Why (why needed), How (which files modified) / 验证描述是否说明：What（做了什么修改）、Why（为什么需要）、How（修改了哪些文件） + - If description is missing or insufficient, suggest adding description with modified files list / 如果描述缺失或不充分，建议添加包含修改文件列表的描述 + - **PR File Modification Review / PR 修改文件审查**： + - Check if PR contains multiple unrelated features / 检查 PR 是否包含多个不相关的特性 + - If PR mixes multiple features, suggest splitting into separate PRs / 如果 PR 混杂多个特性，建议拆分为多个 PR + - Verify all file changes are related to the same feature/bug fix / 验证所有文件修改是否与同一功能/错误修复相关 + - **PR Commit Review / PR Commit 审查**： + - Check commit message format (should follow PR title format) / 检查 commit 消息格式（应遵循 PR 标题格式） + - Verify if commits are properly organized / 验证 commit 是否组织得当 + - If routine changes (style fixes, minor bugs, docs, typos) are split into multiple commits, suggest squashing them / 如果常规修改（风格修复、小错误、文档、拼写）被拆分为多个 commit，建议压缩它们 + - Important commits (major features, refactoring, critical bugs) can remain separate / 重要提交（主要功能、重构、关键错误）可以保持独立 + - If commit messages don't follow format, suggest: "Commit message should follow format: `[module][subsystem] Description`. Consider squashing routine changes into one commit." / 如果 commit 消息不符合格式，建议："Commit 消息应遵循格式：`[模块][子系统] 描述`。考虑将常规修改压缩为一个 commit。" + +### PR Review Instructions / PR 审查指令 + +**When reviewing a PR, you MUST systematically check the following items and provide feedback for any violations / 审查 PR 时，必须系统性地检查以下项目，并对任何违规行为提供反馈：** + +#### Step 1: PR Title Check / 步骤 1：PR 标题检查 + +1. **Check prefix format / 检查前缀格式**: + - Extract the PR title from the PR / 从 PR 中提取 PR 标题 + - Verify if it starts with `[module][subsystem]` or `[module]` pattern in lowercase / 验证是否以小写的 `[模块][子系统]` 或 `[模块]` 格式开头 + - Check if prefix matches the modified files (e.g., if files are in `bsp/stm32/drivers/`, prefix should be `[stm32][drivers]` or similar) / 检查前缀是否与修改的文件匹配（例如，如果文件在 `bsp/stm32/drivers/`，前缀应为 `[stm32][drivers]` 或类似） + - If prefix is missing, incorrect case (e.g., `[STM32]`), or doesn't match files, provide feedback / 如果前缀缺失、大小写错误（如 `[STM32]`）或不匹配文件，提供反馈 + - **Feedback template / 反馈模板**: + ``` + 🟡 [PR Title/PR 标题]: Missing or incorrect prefix format / 缺少或错误的前缀格式 + + English: PR title should follow format: `[module][subsystem] Description` in lowercase. + Current title: `{current_title}`. + Based on modified files, suggested title: `{suggested_title}`. + + 中文：PR 标题应遵循格式：小写的 `[模块][子系统] 描述`。 + 当前标题：`{current_title}`。 + 基于修改的文件，建议标题：`{suggested_title}`。 + ``` + +2. **Check title specificity / 检查标题具体性**: + - Analyze modified files to understand what changes were made / 分析修改的文件以了解所做的更改 + - Verify if title accurately describes changes based on modified files / 验证标题是否基于修改的文件准确描述更改 + - Check for vague terms: "fix bug", "optimize code", "update", "modify", etc. / 检查模糊术语："修复问题"、"代码优化"、"更新"、"修改"等 + - If title is vague or doesn't match modified files, suggest a more specific title / 如果标题模糊或不匹配修改的文件，建议更具体的标题 + - **Feedback template / 反馈模板**: + ``` + 🟡 [PR Title/PR 标题]: Title is too vague or doesn't match modified files / 标题过于模糊或不匹配修改的文件 + + English: PR title should specifically describe changes based on modified files. + Current title: `{current_title}`. + Suggested: `{suggested_title}` based on files: {list_modified_files}. + + 中文：PR 标题应基于修改的文件具体描述更改。 + 当前标题：`{current_title}`。 + 建议：基于文件 {list_modified_files} 的 `{suggested_title}`。 + ``` + +#### Step 2: PR Description Check / 步骤 2：PR 内容检查 + +1. **Check description completeness / 检查描述完整性**: + - Read the PR description / 阅读 PR 描述 + - Verify if it includes: / 验证是否包含： + - Overview of modified files / 修改文件的总概 + - What changes were made / 做了什么修改 + - Why changes are needed / 为什么需要这些修改 + - List of modified files (optional but recommended) / 修改文件列表（可选但推荐） + - If description is missing, empty, or insufficient, provide feedback / 如果描述缺失、为空或不充分，提供反馈 + - **Feedback template / 反馈模板**: + ``` + 🟢 [PR Description/PR 描述]: Missing or insufficient description / 缺少或不充分的描述 + + English: PR description should include: (1) Overview of modified files, (2) What changes were made, (3) Why changes are needed, (4) List of modified files (optional). + Please add/modify the PR description. + + 中文：PR 描述应包含：(1) 修改文件的总概，(2) 做了什么修改，(3) 为什么需要这些修改，(4) 修改文件列表（可选）。 + 请添加/修改 PR 描述。 + + Example format / 示例格式: + ## Description / 描述 + This PR fixes the UART interrupt handling issue in STM32 serial driver. + 本次 PR 修复了 STM32 串口驱动中的中断处理问题。 + + ## Modified Files / 修改文件 + - `bsp/stm32/drivers/drv_usart.c`: Fixed interrupt handler logic + - `bsp/stm32/drivers/drv_usart.h`: Updated function declarations + ``` + +#### Step 3: PR File Modification Check / 步骤 3：PR 修改文件检查 + +1. **Check feature separation / 检查特性分离**: + - List all modified files in the PR / 列出 PR 中的所有修改文件 + - Group files by feature/functionality / 按特性/功能对文件进行分组 + - Identify if multiple unrelated features are mixed / 识别是否混杂了多个不相关的特性 + - Unrelated features include: different drivers, different subsystems, unrelated bug fixes, etc. / 不相关的特性包括：不同的驱动、不同的子系统、不相关的错误修复等 + - If multiple unrelated features are found, provide feedback with specific suggestions / 如果发现多个不相关的特性，提供具体建议的反馈 + - **Feedback template / 反馈模板**: + ``` + 🟡 [PR Structure/PR 结构]: Multiple unrelated features in one PR / 一个 PR 中包含多个不相关的特性 + + English: This PR contains multiple unrelated features: {list_features}. + Please split into separate PRs, each focusing on one feature. + Suggested PRs: + - PR 1: `[module1][subsystem1] {feature1_description}` (files: {list_files1}) + - PR 2: `[module2][subsystem2] {feature2_description}` (files: {list_files2}) + + 中文：此 PR 包含多个不相关的特性：{list_features}。 + 请拆分为多个 PR，每个专注于一个特性。 + 建议的 PR： + - PR 1: `[模块1][子系统1] {特性1描述}` (文件: {list_files1}) + - PR 2: `[模块2][子系统2] {特性2描述}` (文件: {list_files2}) + ``` + +#### Step 4: PR Commit Check / 步骤 4：PR Commit 检查 + +1. **Check commit message format / 检查 commit 消息格式**: + - Review all commit messages in the PR / 审查 PR 中的所有 commit 消息 + - Verify if each commit message follows format: `[module][subsystem] Description` / 验证每个 commit 消息是否遵循格式：`[module][subsystem] 描述` + - Check if commit message prefix matches PR title prefix / 检查 commit 消息前缀是否与 PR 标题前缀匹配 + - If commit messages don't follow format, provide feedback / 如果 commit 消息不符合格式，提供反馈 + - **Feedback template / 反馈模板**: + ``` + 🟡 [Commit Message/Commit 消息]: Commit message format violation / Commit 消息格式违规 + + English: Commit message should follow format: `[module][subsystem] Description`. + Invalid commits: {list_invalid_commits}. + Example: `[stm32][drivers] Fix UART interrupt handling issue`. + + 中文：Commit 消息应遵循格式：`[模块][子系统] 描述`。 + 无效的 commit：{list_invalid_commits}。 + 示例：`[stm32][drivers] Fix UART interrupt handling issue`。 + ``` + +2. **Check commit organization / 检查 commit 组织**: + - Identify routine changes: style fixes, minor bugs, documentation updates, typo corrections / 识别常规修改：风格修复、小错误、文档更新、拼写错误修正 + - Identify important changes: major features, significant refactoring, critical bug fixes / 识别重要更改：主要功能、重大重构、关键错误修复 + - Check if routine changes are split into multiple commits / 检查常规修改是否被拆分为多个 commit + - If routine changes are split, suggest squashing them / 如果常规修改被拆分，建议压缩它们 + - **Feedback template / 反馈模板**: + ``` + 🟢 [Commit Organization/Commit 组织]: Routine changes should be squashed / 常规修改应压缩 + + English: Routine changes (style fixes, minor bugs, docs, typos) should be squashed into one commit. + Commits to squash: {list_commits_to_squash}. + Please use `git rebase -i` to squash these commits. + + 中文：常规修改（风格修复、小错误、文档、拼写）应压缩为一个 commit。 + 要压缩的 commit：{list_commits_to_squash}。 + 请使用 `git rebase -i` 压缩这些 commit。 + ``` ### Review Comment Format / 审查评论格式 @@ -59,6 +202,8 @@ Example/示例: // Your code example here / 你的代码示例 ``` ``` + +**For PR-related issues, use severity level 🟡 Minor or 🟢 Suggestion / 对于 PR 相关的问题，使用严重程度级别 🟡 Minor 或 🟢 Suggestion** ### Common Issues to Check / 常见问题检查 1. **Resource Management / 资源管理** diff --git a/.github/workflows/bsp_buildings.yml b/.github/workflows/bsp_buildings.yml index 2dcd147b19b..4cfd33eb385 100644 --- a/.github/workflows/bsp_buildings.yml +++ b/.github/workflows/bsp_buildings.yml @@ -234,6 +234,8 @@ jobs: wget -q https://github.com/RT-Thread/toolchains-ci/releases/download/v1.7/arm-linux-musleabi_for_x86_64-pc-linux-gnu_stable.tar.bz2 sudo tar xjf arm-linux-musleabi_for_x86_64-pc-linux-gnu_stable.tar.bz2 -C /opt /opt/arm-linux-musleabi_for_x86_64-pc-linux-gnu/bin/arm-linux-musleabi-gcc --version + echo "RTT_EXEC_PATH=/opt/arm-linux-musleabi_for_x86_64-pc-linux-gnu/bin" >> $GITHUB_ENV + echo "RTT_CC_PREFIX=arm-linux-musleabi-" >> $GITHUB_ENV - name: Install Simulator Tools if: ${{ matrix.legs.RTT_TOOL_CHAIN == 'gcc' && success() }} diff --git a/.github/workflows/utest_auto_run.yml b/.github/workflows/utest_auto_run.yml index a5880e847bf..df56f699d5b 100644 --- a/.github/workflows/utest_auto_run.yml +++ b/.github/workflows/utest_auto_run.yml @@ -48,12 +48,12 @@ jobs: - { UTEST: "RISCV", RTT_BSP: "bsp/qemu-virt64-riscv", QEMU_ARCH: "riscv64", QEMU_MACHINE: "virt", SD_FILE: "None", KERNEL: "standard", "SMP_RUN":"" } - { UTEST: "RISCV-rtsmart", RTT_BSP: "bsp/qemu-virt64-riscv", QEMU_ARCH: "riscv64", QEMU_MACHINE: "virt", SD_FILE: "None", KERNEL: "rtsmart", "SMP_RUN":"" } - # - { UTEST: "RISCV-smp", RTT_BSP: "bsp/qemu-virt64-riscv", QEMU_ARCH: "riscv64", QEMU_MACHINE: "virt", SD_FILE: "None", KERNEL: "standard", "SMP_RUN":"smp" } - - { UTEST: "XUANTIE-rtsmart", RTT_BSP: "bsp/xuantie/virt64/c906", QEMU_ARCH: "riscv64", QEMU_MACHINE: "virt", SD_FILE: "sd.bin", KERNEL: "rtsmart", "SMP_RUN":"" } + - { UTEST: "RISCV-smp", RTT_BSP: "bsp/qemu-virt64-riscv", QEMU_ARCH: "riscv64", QEMU_MACHINE: "virt", SD_FILE: "None", KERNEL: "standard", "SMP_RUN":"smp" } + - { UTEST: "XUANTIE-rtsmart", RTT_BSP: "bsp/xuantie/virt64/c906", QEMU_ARCH: "riscv64", QEMU_MACHINE: "virt", SD_FILE: "sd.bin", KERNEL: "rtsmart", "SMP_RUN":"" } - { UTEST: "AARCH64", RTT_BSP: "bsp/qemu-virt64-aarch64", QEMU_ARCH: "aarch64", QEMU_MACHINE: "virt", SD_FILE: "sd.bin", KERNEL: "standard", "SMP_RUN":"" } - { UTEST: "AARCH64-rtsmart", RTT_BSP: "bsp/qemu-virt64-aarch64", QEMU_ARCH: "aarch64", QEMU_MACHINE: "virt", SD_FILE: "sd.bin", KERNEL: "rtsmart", "SMP_RUN":"" } - # - { UTEST: "AARCH64-smp", RTT_BSP: "bsp/qemu-virt64-aarch64", QEMU_ARCH: "aarch64", QEMU_MACHINE: "virt", SD_FILE: "sd.bin", KERNEL: "standard", "SMP_RUN":"smp" } + - { UTEST: "AARCH64-smp", RTT_BSP: "bsp/qemu-virt64-aarch64", QEMU_ARCH: "aarch64", QEMU_MACHINE: "virt", SD_FILE: "sd.bin", KERNEL: "standard", "SMP_RUN":"smp" } config_file: - "default.cfg" diff --git a/.gitignore b/.gitignore index 9da95424d23..101a559ab55 100644 --- a/.gitignore +++ b/.gitignore @@ -1,4 +1,6 @@ *.pyc +**/Cargo.lock +**/target/ *.map *.dblite *.elf diff --git a/bsp/Copyright_Notice.md b/bsp/Copyright_Notice.md index 7a805d17719..59358aa5ffa 100644 --- a/bsp/Copyright_Notice.md +++ b/bsp/Copyright_Notice.md @@ -325,6 +325,17 @@ Path: - bsp/imx6ul/platform +### imx91 + +License: bsd-new + +Copyright: Copyright 2014-2016 Freescale Semiconductor, Inc. + Copyright 2016-2025 NXP + +Path: + +- bsp/nxp/imx/imx91/drivers/sdk + ### imxrt License: clear-bsd diff --git a/bsp/README.md b/bsp/README.md index d78584f143d..1b77f596260 100644 --- a/bsp/README.md +++ b/bsp/README.md @@ -33,28 +33,29 @@ This document is based on the RT-Thread mainline repository and categorizes the #### 🟢 Renesas -| BSP Name | GPIO | UART | ADC | CAN | CANFD | DAC | Ethernet | HWTimer | I2C | PWM | RTC | SPI | Soft SPI | Flash | SDHI | SCI | SDRAM | LCD | Other | -|----------|------|------|-----|-----|-------|-----|----------|---------|-----|-----|-----|-----|----------|-------|------|-----|-------|-----|-------| -| [ebf_qi_min_6m5](renesas/ebf_qi_min_6m5) | ✅ | ✅ | ✅ | - | - | ✅ | - | - | ✅ | ✅ | - | ✅ | - | - | - | ✅ | - | - | - | -| [ra2a1-ek](renesas/ra2a1-ek) | ✅ | ✅ | ✅ | - | - | ✅ | - | - | ✅ | ✅ | - | ✅ | - | - | - | ✅ | - | - | - | -| [ra2e2-ek](renesas/ra2e2-ek) | ✅ | ✅ | ✅ | - | - | - | - | - | ✅ | ✅ | - | ✅ | - | - | - | - | - | - | - | -| [ra2l1-cpk](renesas/ra2l1-cpk) | ✅ | ✅ | ✅ | ✅ | - | ✅ | - | - | ✅ | ✅ | - | ✅ | - | - | - | ✅ | - | - | ✅ | -| [ra4e2-eco](renesas/ra4e2-eco) | ✅ | ✅ | - | - | - | - | - | - | ✅ | - | - | ✅ | - | - | - | - | - | - | - | -| [ra4e2-ek](renesas/ra4e2-ek) | - | ✅ | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | -| [ra4m1-ek](renesas/ra4m1-ek) | ✅ | ✅ | ✅ | ✅ | - | ✅ | - | ✅ | ✅ | ✅ | - | ✅ | - | - | - | - | - | - | - | -| [ra4m2-eco](renesas/ra4m2-eco) | ✅ | ✅ | - | - | - | - | - | - | - | - | - | ✅ | - | - | - | ✅ | - | - | - | -| [ra6e2-ek](renesas/ra6e2-ek) | ✅ | ✅ | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | -| [ra6e2-fpb](renesas/ra6e2-fpb) | ✅ | ✅ | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | -| [ra6m3-ek](renesas/ra6m3-ek) | ✅ | ✅ | - | - | - | - | ✅ | ✅ | ✅ | ✅ | - | ✅ | - | - | - | ✅ | - | ✅ | - | -| [ra6m3-hmi-board](renesas/ra6m3-hmi-board) | ✅ | ✅ | ✅ | ✅ | - | ✅ | ✅ | - | ✅ | ✅ | - | ✅ | - | - | ✅ | ✅ | - | ✅ | ✅ | -| [ra6m4-cpk](renesas/ra6m4-cpk) | ✅ | ✅ | ✅ | ✅ | - | ✅ | - | - | ✅ | ✅ | - | ✅ | - | - | ✅ | ✅ | - | - | ✅ | -| [ra6m4-iot](renesas/ra6m4-iot) | ✅ | ✅ | ✅ | ✅ | - | ✅ | - | - | ✅ | ✅ | - | ✅ | - | - | ✅ | ✅ | - | - | - | -| [ra8d1-ek](renesas/ra8d1-ek) | ✅ | ✅ | ✅ | ✅ | - | ✅ | ✅ | - | ✅ | ✅ | - | ✅ | - | - | ✅ | ✅ | ✅ | ✅ | ✅ | -| [ra8d1-vision-board](renesas/ra8d1-vision-board) | ✅ | ✅ | ✅ | ✅ | - | ✅ | - | - | ✅ | ✅ | - | ✅ | - | - | ✅ | ✅ | ✅ | ✅ | ✅ | -| [ra8m1-ek](renesas/ra8m1-ek) | ✅ | ✅ | ✅ | - | - | ✅ | - | - | ✅ | ✅ | - | ✅ | - | - | - | ✅ | - | - | ✅ | -| [rzn2l_etherkit](renesas/rzn2l_etherkit) | ✅ | ✅ | ✅ | - | ✅ | - | ✅ | ✅ | ✅ | ✅ | - | ✅ | - | - | - | ✅ | - | - | ✅ | -| [rzn2l_rsk](renesas/rzn2l_rsk) | ✅ | ✅ | ✅ | - | ✅ | - | ✅ | ✅ | ✅ | - | - | ✅ | - | - | - | ✅ | - | - | ✅ | -| [rzt2m_rsk](renesas/rzt2m_rsk) | ✅ | ✅ | ✅ | - | - | - | - | ✅ | ✅ | - | - | ✅ | - | - | - | ✅ | - | - | ✅ | +| BSP Name | GPIO | UART | ADC | CAN | CANFD | DAC | Ethernet | HWTimer | I2C | PWM | RTC | SPI | Soft SPI | Flash | SDHI | SCI | SDRAM | LCD | **RS485** | Other | +|----------|------|------|-----|-----|-------|-----|----------|---------|-----|-----|-----|-----|----------|-------|------|-----|-------|-----|-------|-------| +| [ebf_qi_min_6m5](renesas/ebf_qi_min_6m5) | ✅ | ✅ | ✅ | - | - | ✅ | - | - | ✅ | ✅ | - | ✅ | - | - | - | ✅ | - | - | - | - | +| [ra2a1-ek](renesas/ra2a1-ek) | ✅ | ✅ | ✅ | - | - | ✅ | - | - | ✅ | ✅ | - | ✅ | - | - | - | ✅ | - | - | - | - | +| [ra2e2-ek](renesas/ra2e2-ek) | ✅ | ✅ | ✅ | - | - | - | - | - | ✅ | ✅ | - | ✅ | - | - | - | - | - | - | - | - | +| [ra2l1-cpk](renesas/ra2l1-cpk) | ✅ | ✅ | ✅ | ✅ | - | ✅ | - | - | ✅ | ✅ | - | ✅ | - | - | - | ✅ | - | - | - | ✅ | +| [ra4e2-eco](renesas/ra4e2-eco) | ✅ | ✅ | - | - | - | - | - | - | ✅ | - | - | ✅ | - | - | - | - | - | - | - | - | +| [ra4e2-ek](renesas/ra4e2-ek) | - | ✅ | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | +| [ra4m1-ek](renesas/ra4m1-ek) | ✅ | ✅ | ✅ | ✅ | - | ✅ | - | ✅ | ✅ | ✅ | - | ✅ | - | - | - | - | - | - | - | - | +| [ra4m2-eco](renesas/ra4m2-eco) | ✅ | ✅ | - | - | - | - | - | - | - | - | - | ✅ | - | - | - | ✅ | - | - | - | - | +| [ra6e2-ek](renesas/ra6e2-ek) | ✅ | ✅ | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | +| [ra6e2-fpb](renesas/ra6e2-fpb) | ✅ | ✅ | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | +| [ra6m3-ek](renesas/ra6m3-ek) | ✅ | ✅ | - | - | - | - | ✅ | ✅ | ✅ | ✅ | - | ✅ | - | - | - | ✅ | - | ✅ | - | - | +| [ra6m3-hmi-board](renesas/ra6m3-hmi-board) | ✅ | ✅ | ✅ | ✅ | - | ✅ | ✅ | - | ✅ | ✅ | - | ✅ | - | - | ✅ | ✅ | - | ✅ | - | ✅ | +| [ra6m4-cpk](renesas/ra6m4-cpk) | ✅ | ✅ | ✅ | ✅ | - | ✅ | - | - | ✅ | ✅ | - | ✅ | - | - | ✅ | ✅ | - | - | - | ✅ | +| [ra6m4-iot](renesas/ra6m4-iot) | ✅ | ✅ | ✅ | ✅ | - | ✅ | - | - | ✅ | ✅ | - | ✅ | - | - | ✅ | ✅ | - | - | - | - | +| [ra8d1-ek](renesas/ra8d1-ek) | ✅ | ✅ | ✅ | ✅ | - | ✅ | ✅ | - | ✅ | ✅ | - | ✅ | - | - | ✅ | ✅ | ✅ | ✅ | - | ✅ | +| [ra8d1-vision-board](renesas/ra8d1-vision-board) | ✅ | ✅ | ✅ | ✅ | - | ✅ | - | - | ✅ | ✅ | - | ✅ | - | - | ✅ | ✅ | ✅ | ✅ | - | ✅ | +| [ra8p1-titan-board](renesas/ra8p1-titan-board) | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | - | ✅ | ✅ | ✅ | - | ✅ | ✅ | ✅ | +| [ra8m1-ek](renesas/ra8m1-ek) | ✅ | ✅ | ✅ | - | - | ✅ | - | - | ✅ | ✅ | - | ✅ | - | - | - | ✅ | - | - | - | ✅ | +| [rzn2l_etherkit](renesas/rzn2l_etherkit) | ✅ | ✅ | ✅ | - | ✅ | - | ✅ | ✅ | ✅ | ✅ | - | ✅ | - | - | - | ✅ | - | - | - | ✅ | +| [rzn2l_rsk](renesas/rzn2l_rsk) | ✅ | ✅ | ✅ | - | ✅ | - | ✅ | ✅ | ✅ | - | - | ✅ | - | - | - | ✅ | - | - | - | ✅ | +| [rzt2m_rsk](renesas/rzt2m_rsk) | ✅ | ✅ | ✅ | - | - | - | - | ✅ | ✅ | - | - | ✅ | - | - | - | ✅ | - | - | - | ✅ | #### 🟢 STM32 @@ -88,6 +89,7 @@ This document is based on the RT-Thread mainline repository and categorizes the | [stm32f407-atk-explorer](stm32/stm32f407-atk-explorer) | ✅ | ✅ | ✅ | ✅ | ✅ | - | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | - | - | ✅ | - | ✅ | ✅ | - | ✅ | - | - | - | - | ✅ | - | ✅ | | [stm32f407-fk407m2-zgt6](stm32/stm32f407-fk407m2-zgt6) | ✅ | ✅ | ✅ | - | ✅ | - | - | ✅ | ✅ | ✅ | ✅ | ✅ | - | ✅ | ✅ | - | ✅ | - | - | ✅ | - | - | - | - | ✅ | - | ✅ | | [stm32f407-lckfb-skystar](stm32/stm32f407-lckfb-skystar) | ✅ | ✅ | ✅ | - | ✅ | - | - | ✅ | ✅ | ✅ | ✅ | ✅ | - | ✅ | ✅ | - | ✅ | - | - | ✅ | - | - | - | ✅ | ✅ | - | - | +| [stm32f407-micu](stm32/stm32f407-micu) | ✅ | ✅ | - | - | - | - | - | ✅ | ✅ | ✅ | ✅ | ✅ | - | ✅ | ✅ | - | - | - | - | - | | [stm32f407-robomaster-c](stm32/stm32f407-robomaster-c) | ✅ | ✅ | ✅ | ✅ | - | - | - | - | ✅ | ✅ | - | ✅ | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | | [stm32f407-rt-spark](stm32/stm32f407-rt-spark) | ✅ | ✅ | ✅ | ✅ | ✅ | - | - | ✅ | ✅ | ✅ | ✅ | ✅ | - | ✅ | ✅ | - | ✅ | ✅ | - | ✅ | - | - | - | ✅ | ✅ | - | ✅ | | [stm32f407-st-discovery](stm32/stm32f407-st-discovery) | ✅ | ✅ | - | - | - | - | - | - | ✅ | - | - | ✅ | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | @@ -340,11 +342,11 @@ This document is based on the RT-Thread mainline repository and categorizes the #### 🟡 Rockchip -| BSP Name | GPIO | UART | ADC | I2C | SPI | WDT | -|----------|------|------|-----|-----|-----|-----| -| [rk2108](rockchip/rk2108) | - | ✅ | - | - | - | - | -| [rk3500](rockchip/rk3500) | - | ✅ | - | - | - | - | -| [rk3568](rockchip/rk3568) | - | ✅ | - | - | - | - | +| BSP Name | GPIO | UART | ADC | I2C | SPI | WDT | HWTimer | PWM | RTC | SDIO | CAN | PCI | +|----------|------|------|-----|-----|-----|-----|---------|-----|-----|------|-----|------| +| [rk2108](rockchip/rk2108) | - | ✅ | - | - | - | - | - | - | - | - | - | - | +| [rk3300](rockchip/rk3300) | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | - | +| [rk3500](rockchip/rk3500) | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | #### 🟡 APM32 @@ -415,22 +417,22 @@ This document is based on the RT-Thread mainline repository and categorizes the | [swm320-mini](synwit/swm320-mini) | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | | [swm341-mini](synwit/swm341-mini) | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | -#### ⚪ N32G452xx +#### ⚪ N32G452xx | BSP Name | GPIO | UART | ADC | CAN | DAC | Flash | HWTimer | I2C | PWM | RTC | SDIO | SPI | WDT | |----------|------|------|-----|-----|-----|-------|---------|-----|-----|-----|------|-----|-----| | [n32g452xx-mini-system](n32g452xx/n32g452xx-mini-system) | ✅ | ✅ | ✅ | ✅ | - | ✅ | ✅ | ✅ | ✅ | - | ✅ | ✅ | ✅ | -#### ⚪ W60x +#### ⚪ W60x | BSP Name | GPIO | UART | ADC | Crypto | Flash | HWTimer | WDT | PWM | I2C | SPI | |----------|------|------|-----|--------|-------|---------|-----|-----|-----|-----| | [w60x](w60x) | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | -#### ⚪ Allwinner Tina +#### ⚪ Allwinner Tina | BSP Name | GPIO | UART | SPI | SDIO | |----------|------|------|-----|------| | [allwinner_tina](allwinner_tina) | ✅ | ✅ | ✅ | ✅ | -#### ⚪ HC321136 +#### ⚪ HC321136 | BSP Name | GPIO | UART | I2C | |----------|------|------|-----| | [hc321136](hc32/hc321136) | ✅ | ✅ | ✅ | @@ -440,7 +442,7 @@ This document is based on the RT-Thread mainline repository and categorizes the |----------|------|------| | [hc321196](hc32/hc321196) | ✅ | ✅ | -#### ⚪ Amebaz +#### ⚪ Amebaz | BSP Name | GPIO | UART | WLAN | |----------|------|------|------| | [amebaz](amebaz) | - | ✅ | ✅ | @@ -541,6 +543,7 @@ This document is based on the RT-Thread mainline repository and categorizes the | BSP Name | GPIO | UART | |----------|------|------| | [ft32f072xb-starter](ft32/ft32f072xb-starter) | ✅ | ✅ | +| [ft32f407xe-starter](ft32/ft32f407xe-starter) | ✅ | ✅ | #### ⚪ Fujitsu @@ -760,9 +763,9 @@ This document is based on the RT-Thread mainline repository and categorizes the #### 🟢 K230 (RT-Smart) -| BSP Name | GPIO | UART | I2C | RTC | ADC | PWM | SDIO | HWTimer | WDT | SPI | -|----------|------|------|-----|-----|-----|-----|------|---------|-----|-----| -| [k230](k230) | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | +| BSP Name | GPIO | UART | I2C | RTC | ADC | PWM | SDIO | HWTimer | WDT | SPI | GNNE | +|----------|------|------|-----|-----|-----|-----|------|---------|-----|-----|------| +| [k230](k230) | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | #### 🟢 Xuantie (RT-Smart) @@ -837,17 +840,17 @@ This document is based on the RT-Thread mainline repository and categorizes the |----------|------|------|-----|-------|---------|------|-----|-----|------|----------|-----| | [ab32vg1-ab-prougen](bluetrum/ab32vg1-ab-prougen) | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | -#### ⚪ Core-V-MCU +#### ⚪ Core-V-MCU | BSP Name | UART | |----------|------| | [core-v-cv32e40p](core-v-mcu/core-v-cv32e40p) | ✅ | -#### ⚪ HiFive1 +#### ⚪ HiFive1 | BSP Name | GPIO | UART | |----------|------|------| | [hifive1](hifive1) | ✅ | ✅ | -#### ⚪ Sparkfun-RedV +#### ⚪ Sparkfun-RedV | BSP Name | GPIO | UART | ADC | I2C | SPI | WDT | Timer | PWM | RTC | |----------|------|------|-----|-----|-----|-----|-------|-----|-----| | [sparkfun-redv](sparkfun-redv) | ✅ | ✅ | - | - | - | - | ✅ | - | - | diff --git a/bsp/ft32/.clang-format-ignore b/bsp/ft32/.clang-format-ignore deleted file mode 100644 index e22a659aa9f..00000000000 --- a/bsp/ft32/.clang-format-ignore +++ /dev/null @@ -1,2 +0,0 @@ -# clang-format ignore file -/libraries/FT32F0xx/ diff --git a/bsp/ft32/ft32f072xb-starter/.config b/bsp/ft32/ft32f072xb-starter/.config index 08f289c3ba0..bfd613718fb 100644 --- a/bsp/ft32/ft32f072xb-starter/.config +++ b/bsp/ft32/ft32f072xb-starter/.config @@ -731,6 +731,23 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # HAL & SDK Drivers # +# +# FT32 Drivers +# +CONFIG_PKG_USING_FT32F0_STD_DRIVER=y +CONFIG_PKG_FT32F0_STD_DRIVER_PATH="/packages/peripherals/hal-sdk/ft32/ft32f0_std_driver" +CONFIG_PKG_USING_FT32F0_STD_DRIVER_LATEST_VERSION=y +CONFIG_PKG_FT32F0_STD_DRIVER_VER="latest" +CONFIG_PKG_USING_FT32F0_CMSIS_DRIVER=y +CONFIG_PKG_FT32F0_CMSIS_DRIVER_PATH="/packages/peripherals/hal-sdk/ft32/ft32f0_cmsis_driver" +CONFIG_PKG_USING_FT32F0_CMSIS_DRIVER_LATEST_VERSION=y +CONFIG_PKG_FT32F0_CMSIS_DRIVER_VER="latest" +# CONFIG_PKG_USING_FT32F0_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_FT32F0_STD_DRIVER is not set +# CONFIG_PKG_USING_FT32F4_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_FT32F4_STD_DRIVER is not set +# end of FT32 Drivers + # # STM32 HAL & SDK Drivers # diff --git a/bsp/ft32/ft32f072xb-starter/SConstruct b/bsp/ft32/ft32f072xb-starter/SConstruct index 12634e699d7..e8d348fbf3d 100644 --- a/bsp/ft32/ft32f072xb-starter/SConstruct +++ b/bsp/ft32/ft32f072xb-starter/SConstruct @@ -14,8 +14,27 @@ except: print('Cannot found RT-Thread root directory, please check RTT_ROOT') print(RTT_ROOT) exit(-1) + +def bsp_pkg_check(): + import subprocess -TARGET = 'rt-thread_ft32f072.' + rtconfig.TARGET_EXT + check_paths = [ + os.path.join("packages", "ft32f0_cmsis_driver-latest"), + os.path.join("packages", "ft32f0_std_driver-latest") + ] + + need_update = not all(os.path.exists(p) for p in check_paths) + + if need_update: + print("\n===============================================================================") + print("Dependency packages missing, please running 'pkgs --update'...") + print("If no packages are fetched, run 'pkgs --upgrade' first, then 'pkgs --update'...") + print("===============================================================================") + exit(1) + +RegisterPreBuildingAction(bsp_pkg_check) + +TARGET = 'rt-thread.' + rtconfig.TARGET_EXT DefaultEnvironment(tools=[]) env = Environment(tools = ['mingw'], @@ -31,6 +50,7 @@ if rtconfig.PLATFORM in ['iccarm']: env.Replace(ARFLAGS = ['']) env.Replace(LINKCOM = env["LINKCOM"] + ' --map rt-thread.map') +Export('env') Export('RTT_ROOT') Export('rtconfig') @@ -41,20 +61,13 @@ if os.path.exists(SDK_ROOT + '/libraries'): else: libraries_path_prefix = os.path.dirname(SDK_ROOT) + '/libraries' -SDK_LIB = libraries_path_prefix -Export('SDK_LIB') - # prepare building environment objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False) -ft32_library = 'FT32F0xx' -rtconfig.BSP_LIBRARY_TYPE = ft32_library - -# include libraries -objs.extend(SConscript(os.path.join(libraries_path_prefix, ft32_library, 'SConscript'))) +rtconfig.BSP_LIBRARY_TYPE = None # include drivers -objs.extend(SConscript(os.path.join(libraries_path_prefix, 'Drivers', 'SConscript'))) +objs.extend(SConscript(os.path.join(libraries_path_prefix, 'STD_Drivers', 'SConscript'), variant_dir='../libraries/Drivers', duplicate=0)) # make a building DoBuilding(TARGET, objs) diff --git a/bsp/ft32/ft32f072xb-starter/board/Kconfig b/bsp/ft32/ft32f072xb-starter/board/Kconfig index d24f7daee63..ae5b45aa747 100644 --- a/bsp/ft32/ft32f072xb-starter/board/Kconfig +++ b/bsp/ft32/ft32f072xb-starter/board/Kconfig @@ -1,5 +1,9 @@ menu "Hardware Drivers Config" +config SOC_SERIES_FT32F0 + bool + default y + config SOC_FT32F072RB bool select SOC_SERIES_FT32F0 @@ -21,27 +25,30 @@ menu "On-chip Peripheral Drivers" menuconfig BSP_USING_UART bool "Enable UART" default y - select RT_USING_SERIAL if BSP_USING_UART - config BSP_USING_UART1 + choice + prompt "Select UART framework version" + default BSP_USING_SERIAL_V1 + + config BSP_USING_SERIAL_V1 + bool "Use Serial V1 framework" + select RT_USING_SERIAL + + config BSP_USING_SERIAL_V2 + bool "Use Serial V2 framework" + select RT_USING_SERIAL_V2 + endchoice + + menuconfig BSP_USING_UART1 bool "Enable UART1" default n - config BSP_UART1_RX_USING_DMA - bool "Enable UART1 RX DMA" - depends on BSP_USING_UART1 && RT_SERIAL_USING_DMA - default n - - config BSP_USING_UART2 + menuconfig BSP_USING_UART2 bool "Enable UART2" default y - - config BSP_UART2_RX_USING_DMA - bool "Enable UART2 RX DMA" - depends on BSP_USING_UART2 && RT_SERIAL_USING_DMA - default n endif - rsource "../../libraries/Drivers/Kconfig" + + source "$(BSP_DIR)/../libraries/Drivers/Kconfig" endmenu diff --git a/bsp/ft32/ft32f072xb-starter/board/SConscript b/bsp/ft32/ft32f072xb-starter/board/SConscript index 866799a6bb9..0119e7c9c99 100644 --- a/bsp/ft32/ft32f072xb-starter/board/SConscript +++ b/bsp/ft32/ft32f072xb-starter/board/SConscript @@ -1,9 +1,6 @@ import os -import rtconfig from building import * -Import('SDK_LIB') - cwd = GetCurrentDir() # add general drivers @@ -13,15 +10,6 @@ board.c path = [cwd] -startup_path_prefix = SDK_LIB - -if rtconfig.PLATFORM in ['gcc']: - src += [startup_path_prefix + '/FT32F0xx/CMSIS/FT32F0xx/source/gcc/startup_ft32f072xb.s'] -elif rtconfig.PLATFORM in ['armcc', 'armclang']: - src += [startup_path_prefix + '/FT32F0xx/CMSIS/FT32F0xx/source/arm/startup_ft32f072xb.s'] -elif rtconfig.PLATFORM in ['iccarm']: - src += [startup_path_prefix + '/FT32F0xx/CMSIS/FT32F0xx/source/iar/startup_ft32f072xb.s'] - # FT32F072x8 || FT32F072xB # You can select chips from the list above CPPDEFINES = ['FT32F072xB'] diff --git a/bsp/ft32/ft32f072xb-starter/rtconfig.h b/bsp/ft32/ft32f072xb-starter/rtconfig.h index c70b94fbb23..96b6fe40674 100644 --- a/bsp/ft32/ft32f072xb-starter/rtconfig.h +++ b/bsp/ft32/ft32f072xb-starter/rtconfig.h @@ -265,6 +265,8 @@ /* CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */ +#define PKG_USING_CMSIS_CORE +#define PKG_USING_CMSIS_CORE_LATEST_VERSION /* end of CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */ /* Micrium: Micrium software products porting for RT-Thread */ @@ -379,7 +381,10 @@ /* end of Device Control */ /* Other */ - +#define PKG_USING_FT32F0_STD_DRIVER +#define PKG_USING_FT32F0_STD_DRIVER_LATEST_VERSION +#define PKG_USING_FT32F0_CMSIS_DRIVER +#define PKG_USING_FT32F0_CMSIS_DRIVER_LATEST_VERSION /* end of Other */ /* Signal IO */ diff --git a/bsp/ft32/ft32f407xe-starter/.config b/bsp/ft32/ft32f407xe-starter/.config new file mode 100644 index 00000000000..42d883d3520 --- /dev/null +++ b/bsp/ft32/ft32f407xe-starter/.config @@ -0,0 +1,1434 @@ + +# +# RT-Thread Kernel +# + +# +# klibc options +# + +# +# rt_vsnprintf options +# +# CONFIG_RT_KLIBC_USING_LIBC_VSNPRINTF is not set +# CONFIG_RT_KLIBC_USING_VSNPRINTF_LONGLONG is not set +# CONFIG_RT_KLIBC_USING_VSNPRINTF_STANDARD is not set +# end of rt_vsnprintf options + +# +# rt_vsscanf options +# +# CONFIG_RT_KLIBC_USING_LIBC_VSSCANF is not set +# end of rt_vsscanf options + +# +# rt_memset options +# +# CONFIG_RT_KLIBC_USING_USER_MEMSET is not set +# CONFIG_RT_KLIBC_USING_LIBC_MEMSET is not set +# CONFIG_RT_KLIBC_USING_TINY_MEMSET is not set +# end of rt_memset options + +# +# rt_memcpy options +# +# CONFIG_RT_KLIBC_USING_USER_MEMCPY is not set +# CONFIG_RT_KLIBC_USING_LIBC_MEMCPY is not set +# CONFIG_RT_KLIBC_USING_TINY_MEMCPY is not set +# end of rt_memcpy options + +# +# rt_memmove options +# +# CONFIG_RT_KLIBC_USING_USER_MEMMOVE is not set +# CONFIG_RT_KLIBC_USING_LIBC_MEMMOVE is not set +# end of rt_memmove options + +# +# rt_memcmp options +# +# CONFIG_RT_KLIBC_USING_USER_MEMCMP is not set +# CONFIG_RT_KLIBC_USING_LIBC_MEMCMP is not set +# end of rt_memcmp options + +# +# rt_strstr options +# +# CONFIG_RT_KLIBC_USING_USER_STRSTR is not set +# CONFIG_RT_KLIBC_USING_LIBC_STRSTR is not set +# end of rt_strstr options + +# +# rt_strcasecmp options +# +# CONFIG_RT_KLIBC_USING_USER_STRCASECMP is not set +# end of rt_strcasecmp options + +# +# rt_strncpy options +# +# CONFIG_RT_KLIBC_USING_USER_STRNCPY is not set +# CONFIG_RT_KLIBC_USING_LIBC_STRNCPY is not set +# end of rt_strncpy options + +# +# rt_strcpy options +# +# CONFIG_RT_KLIBC_USING_USER_STRCPY is not set +# CONFIG_RT_KLIBC_USING_LIBC_STRCPY is not set +# end of rt_strcpy options + +# +# rt_strncmp options +# +# CONFIG_RT_KLIBC_USING_USER_STRNCMP is not set +# CONFIG_RT_KLIBC_USING_LIBC_STRNCMP is not set +# end of rt_strncmp options + +# +# rt_strcmp options +# +# CONFIG_RT_KLIBC_USING_USER_STRCMP is not set +# CONFIG_RT_KLIBC_USING_LIBC_STRCMP is not set +# end of rt_strcmp options + +# +# rt_strlen options +# +# CONFIG_RT_KLIBC_USING_USER_STRLEN is not set +# CONFIG_RT_KLIBC_USING_LIBC_STRLEN is not set +# end of rt_strlen options + +# +# rt_strnlen options +# +# CONFIG_RT_KLIBC_USING_USER_STRNLEN is not set +# end of rt_strnlen options +# end of klibc options + +CONFIG_RT_NAME_MAX=12 +# CONFIG_RT_USING_ARCH_DATA_TYPE is not set +# CONFIG_RT_USING_NANO is not set +# CONFIG_RT_USING_SMART is not set +# CONFIG_RT_USING_AMP is not set +# CONFIG_RT_USING_SMP is not set +CONFIG_RT_CPUS_NR=1 +CONFIG_RT_ALIGN_SIZE=8 +# CONFIG_RT_THREAD_PRIORITY_8 is not set +CONFIG_RT_THREAD_PRIORITY_32=y +# CONFIG_RT_THREAD_PRIORITY_256 is not set +CONFIG_RT_THREAD_PRIORITY_MAX=32 +CONFIG_RT_TICK_PER_SECOND=1000 +CONFIG_RT_USING_OVERFLOW_CHECK=y +CONFIG_RT_USING_HOOK=y +CONFIG_RT_HOOK_USING_FUNC_PTR=y +# CONFIG_RT_USING_HOOKLIST is not set +CONFIG_RT_USING_IDLE_HOOK=y +CONFIG_RT_IDLE_HOOK_LIST_SIZE=4 +CONFIG_IDLE_THREAD_STACK_SIZE=256 +# CONFIG_RT_USING_TIMER_SOFT is not set +# CONFIG_RT_USING_CPU_USAGE_TRACER is not set + +# +# kservice options +# +# CONFIG_RT_USING_TINY_FFS is not set +# end of kservice options + +CONFIG_RT_USING_DEBUG=y +CONFIG_RT_DEBUGING_ASSERT=y +CONFIG_RT_DEBUGING_COLOR=y +CONFIG_RT_DEBUGING_CONTEXT=y +# CONFIG_RT_DEBUGING_AUTO_INIT is not set +# CONFIG_RT_USING_CI_ACTION is not set + +# +# Inter-Thread communication +# +CONFIG_RT_USING_SEMAPHORE=y +CONFIG_RT_USING_MUTEX=y +CONFIG_RT_USING_EVENT=y +CONFIG_RT_USING_MAILBOX=y +CONFIG_RT_USING_MESSAGEQUEUE=y +# CONFIG_RT_USING_MESSAGEQUEUE_PRIORITY is not set +# CONFIG_RT_USING_SIGNALS is not set +# end of Inter-Thread communication + +# +# Memory Management +# +CONFIG_RT_USING_MEMPOOL=y +CONFIG_RT_USING_SMALL_MEM=y +# CONFIG_RT_USING_SLAB is not set +# CONFIG_RT_USING_MEMHEAP is not set +CONFIG_RT_USING_SMALL_MEM_AS_HEAP=y +# CONFIG_RT_USING_MEMHEAP_AS_HEAP is not set +# CONFIG_RT_USING_SLAB_AS_HEAP is not set +# CONFIG_RT_USING_USERHEAP is not set +# CONFIG_RT_USING_NOHEAP is not set +# CONFIG_RT_USING_MEMTRACE is not set +# CONFIG_RT_USING_HEAP_ISR is not set +CONFIG_RT_USING_HEAP=y +# end of Memory Management + +CONFIG_RT_USING_DEVICE=y +# CONFIG_RT_USING_DEVICE_OPS is not set +# CONFIG_RT_USING_INTERRUPT_INFO is not set +# CONFIG_RT_USING_THREADSAFE_PRINTF is not set +CONFIG_RT_USING_CONSOLE=y +CONFIG_RT_CONSOLEBUF_SIZE=128 +CONFIG_RT_CONSOLE_DEVICE_NAME="uart2" +CONFIG_RT_VER_NUM=0x50201 +# CONFIG_RT_USING_STDC_ATOMIC is not set +CONFIG_RT_BACKTRACE_LEVEL_MAX_NR=32 +# end of RT-Thread Kernel + +CONFIG_ARCH_ARM=y +CONFIG_ARCH_ARM_CORTEX_M=y +CONFIG_ARCH_ARM_CORTEX_M0=y + +# +# RT-Thread Components +# +CONFIG_RT_USING_COMPONENTS_INIT=y +CONFIG_RT_USING_USER_MAIN=y +CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048 +CONFIG_RT_MAIN_THREAD_PRIORITY=10 +# CONFIG_RT_USING_LEGACY is not set +CONFIG_RT_USING_MSH=y +CONFIG_RT_USING_FINSH=y +CONFIG_FINSH_USING_MSH=y +CONFIG_FINSH_THREAD_NAME="tshell" +CONFIG_FINSH_THREAD_PRIORITY=20 +CONFIG_FINSH_THREAD_STACK_SIZE=4096 +CONFIG_FINSH_USING_HISTORY=y +CONFIG_FINSH_HISTORY_LINES=5 +# CONFIG_FINSH_USING_WORD_OPERATION is not set +# CONFIG_FINSH_USING_FUNC_EXT is not set +CONFIG_FINSH_USING_SYMTAB=y +CONFIG_FINSH_CMD_SIZE=80 +CONFIG_MSH_USING_BUILT_IN_COMMANDS=y +CONFIG_FINSH_USING_DESCRIPTION=y +# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set +# CONFIG_FINSH_USING_AUTH is not set +CONFIG_FINSH_ARG_MAX=10 +CONFIG_FINSH_USING_OPTION_COMPLETION=y + +# +# DFS: device virtual file system +# +# CONFIG_RT_USING_DFS is not set +# end of DFS: device virtual file system + +# CONFIG_RT_USING_FAL is not set + +# +# Device Drivers +# +# CONFIG_RT_USING_DM is not set +# CONFIG_RT_USING_DEV_BUS is not set +CONFIG_RT_USING_DEVICE_IPC=y +CONFIG_RT_UNAMED_PIPE_NUMBER=64 +# CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set +CONFIG_RT_USING_SERIAL=y +CONFIG_RT_USING_SERIAL_V1=y +# CONFIG_RT_USING_SERIAL_V2 is not set +# CONFIG_RT_SERIAL_USING_DMA is not set +CONFIG_RT_SERIAL_RB_BUFSZ=64 +# CONFIG_RT_USING_SERIAL_BYPASS is not set +# CONFIG_RT_USING_CAN is not set +# CONFIG_RT_USING_CPUTIME is not set +# CONFIG_RT_USING_I2C is not set +# CONFIG_RT_USING_PHY is not set +# CONFIG_RT_USING_PHY_V2 is not set +# CONFIG_RT_USING_ADC is not set +# CONFIG_RT_USING_DAC is not set +# CONFIG_RT_USING_NULL is not set +# CONFIG_RT_USING_ZERO is not set +# CONFIG_RT_USING_RANDOM is not set +# CONFIG_RT_USING_PWM is not set +# CONFIG_RT_USING_PULSE_ENCODER is not set +# CONFIG_RT_USING_INPUT_CAPTURE is not set +# CONFIG_RT_USING_MTD_NOR is not set +# CONFIG_RT_USING_MTD_NAND is not set +# CONFIG_RT_USING_PM is not set +# CONFIG_RT_USING_RTC is not set +# CONFIG_RT_USING_SDIO is not set +# CONFIG_RT_USING_SPI is not set +# CONFIG_RT_USING_WDT is not set +# CONFIG_RT_USING_AUDIO is not set +# CONFIG_RT_USING_SENSOR is not set +# CONFIG_RT_USING_TOUCH is not set +# CONFIG_RT_USING_LCD is not set +# CONFIG_RT_USING_HWCRYPTO is not set +# CONFIG_RT_USING_WIFI is not set +# CONFIG_RT_USING_BLK is not set +# CONFIG_RT_USING_VIRTIO is not set +CONFIG_RT_USING_PIN=y +# CONFIG_RT_USING_KTIME is not set +# CONFIG_RT_USING_HWTIMER is not set +# CONFIG_RT_USING_CHERRYUSB is not set +# end of Device Drivers + +# +# C/C++ and POSIX layer +# + +# +# ISO-ANSI C layer +# + +# +# Timezone and Daylight Saving Time +# +# CONFIG_RT_LIBC_USING_FULL_TZ_DST is not set +CONFIG_RT_LIBC_USING_LIGHT_TZ_DST=y +CONFIG_RT_LIBC_TZ_DEFAULT_HOUR=8 +CONFIG_RT_LIBC_TZ_DEFAULT_MIN=0 +CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 +# end of Timezone and Daylight Saving Time +# end of ISO-ANSI C layer + +# +# POSIX (Portable Operating System Interface) layer +# +# CONFIG_RT_USING_POSIX_FS is not set +# CONFIG_RT_USING_POSIX_DELAY is not set +# CONFIG_RT_USING_POSIX_CLOCK is not set +# CONFIG_RT_USING_POSIX_TIMER is not set +# CONFIG_RT_USING_PTHREADS is not set +# CONFIG_RT_USING_MODULE is not set + +# +# Interprocess Communication (IPC) +# +# CONFIG_RT_USING_POSIX_PIPE is not set +# CONFIG_RT_USING_POSIX_MESSAGE_QUEUE is not set +# CONFIG_RT_USING_POSIX_MESSAGE_SEMAPHORE is not set + +# +# Socket is in the 'Network' category +# +# end of Interprocess Communication (IPC) +# end of POSIX (Portable Operating System Interface) layer + +# CONFIG_RT_USING_CPLUSPLUS is not set +# end of C/C++ and POSIX layer + +# +# Network +# +# CONFIG_RT_USING_SAL is not set +# CONFIG_RT_USING_NETDEV is not set +# CONFIG_RT_USING_LWIP is not set +# CONFIG_RT_USING_AT is not set +# end of Network + +# +# Memory protection +# +# CONFIG_RT_USING_MEM_PROTECTION is not set +# CONFIG_RT_USING_HW_STACK_GUARD is not set +# end of Memory protection + +# +# Utilities +# +# CONFIG_RT_USING_RYM is not set +# CONFIG_RT_USING_ULOG is not set +# CONFIG_RT_USING_UTEST is not set +# CONFIG_RT_USING_VAR_EXPORT is not set +# CONFIG_RT_USING_RESOURCE_ID is not set +# CONFIG_RT_USING_ADT is not set +# CONFIG_RT_USING_RT_LINK is not set +# end of Utilities + +# CONFIG_RT_USING_VBUS is not set + +# +# Using USB legacy version +# +# CONFIG_RT_USING_USB_HOST is not set +# CONFIG_RT_USING_USB_DEVICE is not set +# end of Using USB legacy version + +# CONFIG_RT_USING_FDT is not set +# end of RT-Thread Components + +# +# RT-Thread Utestcases +# +# CONFIG_RT_USING_UTESTCASES is not set +# end of RT-Thread Utestcases + +# +# RT-Thread online packages +# + +# +# IoT - internet of things +# +# CONFIG_PKG_USING_LORAWAN_DRIVER is not set +# CONFIG_PKG_USING_PAHOMQTT is not set +# CONFIG_PKG_USING_UMQTT is not set +# CONFIG_PKG_USING_WEBCLIENT is not set +# CONFIG_PKG_USING_WEBNET is not set +# CONFIG_PKG_USING_MONGOOSE is not set +# CONFIG_PKG_USING_MYMQTT is not set +# CONFIG_PKG_USING_KAWAII_MQTT is not set +# CONFIG_PKG_USING_BC28_MQTT is not set +# CONFIG_PKG_USING_WEBTERMINAL is not set +# CONFIG_PKG_USING_FREEMODBUS is not set +# CONFIG_PKG_USING_NANOPB is not set +# CONFIG_PKG_USING_WIFI_HOST_DRIVER is not set +# CONFIG_PKG_USING_ESP_HOSTED is not set + +# +# Wi-Fi +# + +# +# Marvell WiFi +# +# CONFIG_PKG_USING_WLANMARVELL is not set +# end of Marvell WiFi + +# +# Wiced WiFi +# +# CONFIG_PKG_USING_WLAN_WICED is not set +# end of Wiced WiFi + +# CONFIG_PKG_USING_RW007 is not set + +# +# CYW43012 WiFi +# +# CONFIG_PKG_USING_WLAN_CYW43012 is not set +# end of CYW43012 WiFi + +# +# BL808 WiFi +# +# CONFIG_PKG_USING_WLAN_BL808 is not set +# end of BL808 WiFi + +# +# CYW43439 WiFi +# +# CONFIG_PKG_USING_WLAN_CYW43439 is not set +# end of CYW43439 WiFi +# end of Wi-Fi + +# CONFIG_PKG_USING_COAP is not set +# CONFIG_PKG_USING_NOPOLL is not set +# CONFIG_PKG_USING_NETUTILS is not set +# CONFIG_PKG_USING_CMUX is not set +# CONFIG_PKG_USING_PPP_DEVICE is not set +# CONFIG_PKG_USING_AT_DEVICE is not set +# CONFIG_PKG_USING_ATSRV_SOCKET is not set +# CONFIG_PKG_USING_WIZNET is not set +# CONFIG_PKG_USING_ZB_COORDINATOR is not set + +# +# IoT Cloud +# +# CONFIG_PKG_USING_ONENET is not set +# CONFIG_PKG_USING_GAGENT_CLOUD is not set +# CONFIG_PKG_USING_ALI_IOTKIT is not set +# CONFIG_PKG_USING_AZURE is not set +# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set +# CONFIG_PKG_USING_JIOT-C-SDK is not set +# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set +# CONFIG_PKG_USING_JOYLINK is not set +# CONFIG_PKG_USING_IOTSHARP_SDK is not set +# end of IoT Cloud + +# CONFIG_PKG_USING_NIMBLE is not set +# CONFIG_PKG_USING_LLSYNC_SDK_ADAPTER is not set +# CONFIG_PKG_USING_OTA_DOWNLOADER is not set +# CONFIG_PKG_USING_IPMSG is not set +# CONFIG_PKG_USING_LSSDP is not set +# CONFIG_PKG_USING_AIRKISS_OPEN is not set +# CONFIG_PKG_USING_LIBRWS is not set +# CONFIG_PKG_USING_TCPSERVER is not set +# CONFIG_PKG_USING_PROTOBUF_C is not set +# CONFIG_PKG_USING_DLT645 is not set +# CONFIG_PKG_USING_QXWZ is not set +# CONFIG_PKG_USING_SMTP_CLIENT is not set +# CONFIG_PKG_USING_ABUP_FOTA is not set +# CONFIG_PKG_USING_LIBCURL2RTT is not set +# CONFIG_PKG_USING_CAPNP is not set +# CONFIG_PKG_USING_AGILE_TELNET is not set +# CONFIG_PKG_USING_NMEALIB is not set +# CONFIG_PKG_USING_PDULIB is not set +# CONFIG_PKG_USING_BTSTACK is not set +# CONFIG_PKG_USING_BT_CYW43012 is not set +# CONFIG_PKG_USING_CYW43XX is not set +# CONFIG_PKG_USING_LORAWAN_ED_STACK is not set +# CONFIG_PKG_USING_WAYZ_IOTKIT is not set +# CONFIG_PKG_USING_MAVLINK is not set +# CONFIG_PKG_USING_BSAL is not set +# CONFIG_PKG_USING_AGILE_MODBUS is not set +# CONFIG_PKG_USING_AGILE_FTP is not set +# CONFIG_PKG_USING_EMBEDDEDPROTO is not set +# CONFIG_PKG_USING_RT_LINK_HW is not set +# CONFIG_PKG_USING_RYANMQTT is not set +# CONFIG_PKG_USING_RYANW5500 is not set +# CONFIG_PKG_USING_LORA_PKT_FWD is not set +# CONFIG_PKG_USING_LORA_GW_DRIVER_LIB is not set +# CONFIG_PKG_USING_LORA_PKT_SNIFFER is not set +# CONFIG_PKG_USING_HM is not set +# CONFIG_PKG_USING_SMALL_MODBUS is not set +# CONFIG_PKG_USING_NET_SERVER is not set +# CONFIG_PKG_USING_ZFTP is not set +# CONFIG_PKG_USING_WOL is not set +# CONFIG_PKG_USING_ZEPHYR_POLLING is not set +# CONFIG_PKG_USING_MATTER_ADAPTATION_LAYER is not set +# CONFIG_PKG_USING_LHC_MODBUS is not set +# CONFIG_PKG_USING_QMODBUS is not set +# CONFIG_PKG_USING_PNET is not set +# CONFIG_PKG_USING_OPENER is not set +# CONFIG_PKG_USING_FREEMQTT is not set +# end of IoT - internet of things + +# +# security packages +# +# CONFIG_PKG_USING_MBEDTLS is not set +# CONFIG_PKG_USING_LIBSODIUM is not set +# CONFIG_PKG_USING_LIBHYDROGEN is not set +# CONFIG_PKG_USING_TINYCRYPT is not set +# CONFIG_PKG_USING_TFM is not set +# CONFIG_PKG_USING_YD_CRYPTO is not set +# end of security packages + +# +# language packages +# + +# +# JSON: JavaScript Object Notation, a lightweight data-interchange format +# +# CONFIG_PKG_USING_CJSON is not set +# CONFIG_PKG_USING_LJSON is not set +# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set +# CONFIG_PKG_USING_RAPIDJSON is not set +# CONFIG_PKG_USING_JSMN is not set +# CONFIG_PKG_USING_AGILE_JSMN is not set +# CONFIG_PKG_USING_PARSON is not set +# CONFIG_PKG_USING_RYAN_JSON is not set +# end of JSON: JavaScript Object Notation, a lightweight data-interchange format + +# +# XML: Extensible Markup Language +# +# CONFIG_PKG_USING_SIMPLE_XML is not set +# CONFIG_PKG_USING_EZXML is not set +# end of XML: Extensible Markup Language + +# CONFIG_PKG_USING_LUATOS_SOC is not set +# CONFIG_PKG_USING_LUA is not set +# CONFIG_PKG_USING_JERRYSCRIPT is not set +# CONFIG_PKG_USING_MICROPYTHON is not set +# CONFIG_PKG_USING_PIKASCRIPT is not set +# CONFIG_PKG_USING_RTT_RUST is not set +# end of language packages + +# +# multimedia packages +# + +# +# LVGL: powerful and easy-to-use embedded GUI library +# +# CONFIG_PKG_USING_LVGL is not set +# CONFIG_PKG_USING_LV_MUSIC_DEMO is not set +# CONFIG_PKG_USING_GUI_GUIDER_DEMO is not set +# end of LVGL: powerful and easy-to-use embedded GUI library + +# +# u8g2: a monochrome graphic library +# +# CONFIG_PKG_USING_U8G2_OFFICIAL is not set +# CONFIG_PKG_USING_U8G2 is not set +# end of u8g2: a monochrome graphic library + +# CONFIG_PKG_USING_OPENMV is not set +# CONFIG_PKG_USING_MUPDF is not set +# CONFIG_PKG_USING_STEMWIN is not set +# CONFIG_PKG_USING_WAVPLAYER is not set +# CONFIG_PKG_USING_TJPGD is not set +# CONFIG_PKG_USING_PDFGEN is not set +# CONFIG_PKG_USING_HELIX is not set +# CONFIG_PKG_USING_AZUREGUIX is not set +# CONFIG_PKG_USING_TOUCHGFX2RTT is not set +# CONFIG_PKG_USING_NUEMWIN is not set +# CONFIG_PKG_USING_MP3PLAYER is not set +# CONFIG_PKG_USING_TINYJPEG is not set +# CONFIG_PKG_USING_UGUI is not set +# CONFIG_PKG_USING_MCURSES is not set +# CONFIG_PKG_USING_TERMBOX is not set +# CONFIG_PKG_USING_VT100 is not set +# CONFIG_PKG_USING_QRCODE is not set +# CONFIG_PKG_USING_GUIENGINE is not set +# CONFIG_PKG_USING_3GPP_AMRNB is not set +# end of multimedia packages + +# +# tools packages +# +# CONFIG_PKG_USING_CMBACKTRACE is not set +# CONFIG_PKG_USING_MCOREDUMP is not set +# CONFIG_PKG_USING_EASYFLASH is not set +# CONFIG_PKG_USING_EASYLOGGER is not set +# CONFIG_PKG_USING_SYSTEMVIEW is not set +# CONFIG_PKG_USING_SEGGER_RTT is not set +# CONFIG_PKG_USING_RTT_AUTO_EXE_CMD is not set +# CONFIG_PKG_USING_RDB is not set +# CONFIG_PKG_USING_ULOG_EASYFLASH is not set +# CONFIG_PKG_USING_LOGMGR is not set +# CONFIG_PKG_USING_ADBD is not set +# CONFIG_PKG_USING_COREMARK is not set +# CONFIG_PKG_USING_DHRYSTONE is not set +# CONFIG_PKG_USING_MEMORYPERF is not set +# CONFIG_PKG_USING_NR_MICRO_SHELL is not set +# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set +# CONFIG_PKG_USING_LUNAR_CALENDAR is not set +# CONFIG_PKG_USING_BS8116A is not set +# CONFIG_PKG_USING_GPS_RMC is not set +# CONFIG_PKG_USING_URLENCODE is not set +# CONFIG_PKG_USING_UMCN is not set +# CONFIG_PKG_USING_LWRB2RTT is not set +# CONFIG_PKG_USING_CPU_USAGE is not set +# CONFIG_PKG_USING_GBK2UTF8 is not set +# CONFIG_PKG_USING_VCONSOLE is not set +# CONFIG_PKG_USING_KDB is not set +# CONFIG_PKG_USING_WAMR is not set +# CONFIG_PKG_USING_MICRO_XRCE_DDS_CLIENT is not set +# CONFIG_PKG_USING_LWLOG is not set +# CONFIG_PKG_USING_ANV_TRACE is not set +# CONFIG_PKG_USING_ANV_MEMLEAK is not set +# CONFIG_PKG_USING_ANV_TESTSUIT is not set +# CONFIG_PKG_USING_ANV_BENCH is not set +# CONFIG_PKG_USING_DEVMEM is not set +# CONFIG_PKG_USING_REGEX is not set +# CONFIG_PKG_USING_MEM_SANDBOX is not set +# CONFIG_PKG_USING_SOLAR_TERMS is not set +# CONFIG_PKG_USING_GAN_ZHI is not set +# CONFIG_PKG_USING_FDT is not set +# CONFIG_PKG_USING_CBOX is not set +# CONFIG_PKG_USING_SNOWFLAKE is not set +# CONFIG_PKG_USING_HASH_MATCH is not set +# CONFIG_PKG_USING_ARMV7M_DWT_TOOL is not set +# CONFIG_PKG_USING_VOFA_PLUS is not set +# CONFIG_PKG_USING_RT_TRACE is not set +# CONFIG_PKG_USING_ZDEBUG is not set +# CONFIG_PKG_USING_RVBACKTRACE is not set +# CONFIG_PKG_USING_HPATCHLITE is not set +# CONFIG_PKG_USING_THREAD_METRIC is not set +# end of tools packages + +# +# system packages +# + +# +# enhanced kernel services +# +# CONFIG_PKG_USING_RT_MEMCPY_CM is not set +# CONFIG_PKG_USING_RT_KPRINTF_THREADSAFE is not set +# end of enhanced kernel services + +# CONFIG_PKG_USING_AUNITY is not set + +# +# acceleration: Assembly language or algorithmic acceleration packages +# +# CONFIG_PKG_USING_QFPLIB_M0_FULL is not set +# CONFIG_PKG_USING_QFPLIB_M0_TINY is not set +# CONFIG_PKG_USING_QFPLIB_M3 is not set +# end of acceleration: Assembly language or algorithmic acceleration packages + +# +# CMSIS: ARM Cortex-M Microcontroller Software Interface Standard +# +# CONFIG_PKG_USING_CMSIS_5 is not set +# CONFIG_PKG_USING_CMSIS_CORE is not set +# CONFIG_PKG_USING_CMSIS_NN is not set +# CONFIG_PKG_USING_CMSIS_RTOS1 is not set +# CONFIG_PKG_USING_CMSIS_RTOS2 is not set +# end of CMSIS: ARM Cortex-M Microcontroller Software Interface Standard + +# +# Micrium: Micrium software products porting for RT-Thread +# +# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set +# CONFIG_PKG_USING_UCOSII_WRAPPER is not set +# CONFIG_PKG_USING_UC_CRC is not set +# CONFIG_PKG_USING_UC_CLK is not set +# CONFIG_PKG_USING_UC_COMMON is not set +# CONFIG_PKG_USING_UC_MODBUS is not set +# end of Micrium: Micrium software products porting for RT-Thread + +# CONFIG_PKG_USING_FREERTOS_WRAPPER is not set +# CONFIG_PKG_USING_LITEOS_SDK is not set +# CONFIG_PKG_USING_TZ_DATABASE is not set +# CONFIG_PKG_USING_CAIRO is not set +# CONFIG_PKG_USING_PIXMAN is not set +# CONFIG_PKG_USING_PARTITION is not set +# CONFIG_PKG_USING_PERF_COUNTER is not set +# CONFIG_PKG_USING_FILEX is not set +# CONFIG_PKG_USING_LEVELX is not set +# CONFIG_PKG_USING_FLASHDB is not set +# CONFIG_PKG_USING_SQLITE is not set +# CONFIG_PKG_USING_RTI is not set +# CONFIG_PKG_USING_DFS_YAFFS is not set +# CONFIG_PKG_USING_LITTLEFS is not set +# CONFIG_PKG_USING_DFS_JFFS2 is not set +# CONFIG_PKG_USING_DFS_UFFS is not set +# CONFIG_PKG_USING_LWEXT4 is not set +# CONFIG_PKG_USING_THREAD_POOL is not set +# CONFIG_PKG_USING_ROBOTS is not set +# CONFIG_PKG_USING_EV is not set +# CONFIG_PKG_USING_SYSWATCH is not set +# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set +# CONFIG_PKG_USING_PLCCORE is not set +# CONFIG_PKG_USING_RAMDISK is not set +# CONFIG_PKG_USING_MININI is not set +# CONFIG_PKG_USING_QBOOT is not set +# CONFIG_PKG_USING_PPOOL is not set +# CONFIG_PKG_USING_OPENAMP is not set +# CONFIG_PKG_USING_RPMSG_LITE is not set +# CONFIG_PKG_USING_LPM is not set +# CONFIG_PKG_USING_TLSF is not set +# CONFIG_PKG_USING_EVENT_RECORDER is not set +# CONFIG_PKG_USING_ARM_2D is not set +# CONFIG_PKG_USING_MCUBOOT is not set +# CONFIG_PKG_USING_TINYUSB is not set +# CONFIG_PKG_USING_KMULTI_RTIMER is not set +# CONFIG_PKG_USING_TFDB is not set +# CONFIG_PKG_USING_QPC is not set +# CONFIG_PKG_USING_AGILE_UPGRADE is not set +# CONFIG_PKG_USING_FLASH_BLOB is not set +# CONFIG_PKG_USING_MLIBC is not set +# CONFIG_PKG_USING_TASK_MSG_BUS is not set +# CONFIG_PKG_USING_UART_FRAMEWORK is not set +# CONFIG_PKG_USING_SFDB is not set +# CONFIG_PKG_USING_RTP is not set +# CONFIG_PKG_USING_REB is not set +# CONFIG_PKG_USING_RMP is not set +# CONFIG_PKG_USING_R_RHEALSTONE is not set +# CONFIG_PKG_USING_HEARTBEAT is not set +# CONFIG_PKG_USING_MICRO_ROS_RTTHREAD_PACKAGE is not set +# end of system packages + +# +# peripheral libraries and drivers +# + +# +# HAL & SDK Drivers +# + +# +# FT32 Drivers +# +CONFIG_PKG_USING_FT32F4_STD_DRIVER=y +CONFIG_PKG_FT32F4_STD_DRIVER_PATH="/packages/peripherals/hal-sdk/ft32/ft32f4_std_driver" +CONFIG_PKG_USING_FT32F4_STD_DRIVER_LATEST_VERSION=y +CONFIG_PKG_FT32F4_STD_DRIVER_VER="latest" +CONFIG_PKG_USING_FT32F4_CMSIS_DRIVER=y +CONFIG_PKG_FT32F4_CMSIS_DRIVER_PATH="/packages/peripherals/hal-sdk/ft32/ft32f4_cmsis_driver" +CONFIG_PKG_USING_FT32F4_CMSIS_DRIVER_LATEST_VERSION=y +CONFIG_PKG_FT32F4_CMSIS_DRIVER_VER="latest" +# CONFIG_PKG_USING_FT32F0_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_FT32F0_STD_DRIVER is not set +# CONFIG_PKG_USING_FT32F4_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_FT32F4_STD_DRIVER is not set +# end of FT32 Drivers + +# +# STM32 HAL & SDK Drivers +# +# CONFIG_PKG_USING_STM32F0_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32F0_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32F1_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32F1_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32F2_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32F2_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32F3_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32F3_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32F4_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32F4_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32F7_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32F7_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32G0_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32G0_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32G4_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32G4_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32H5_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32H5_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32H7_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32H7_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32H7RS_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32H7RS_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32L0_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32L0_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32L4_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32L4_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32L5_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32L5_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32U5_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32U5_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32WB55_SDK is not set +# CONFIG_PKG_USING_STM32_SDIO is not set +# CONFIG_PKG_USING_STM32WL_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32WL_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32WB_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32WB_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32MP1_M4_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32MP1_M4_CMSIS_DRIVER is not set +# end of STM32 HAL & SDK Drivers + +# +# Infineon HAL Packages +# +# CONFIG_PKG_USING_INFINEON_CAT1CM0P is not set +# CONFIG_PKG_USING_INFINEON_CMSIS is not set +# CONFIG_PKG_USING_INFINEON_CORE_LIB is not set +# CONFIG_PKG_USING_INFINEON_MTB_HAL_CAT1 is not set +# CONFIG_PKG_USING_INFINEON_MTB_PDL_CAT1 is not set +# CONFIG_PKG_USING_INFINEON_RETARGET_IO is not set +# CONFIG_PKG_USING_INFINEON_CAPSENSE is not set +# CONFIG_PKG_USING_INFINEON_CSDIDAC is not set +# CONFIG_PKG_USING_INFINEON_SERIAL_FLASH is not set +# CONFIG_PKG_USING_INFINEON_USBDEV is not set +# end of Infineon HAL Packages + +# CONFIG_PKG_USING_BLUETRUM_SDK is not set +# CONFIG_PKG_USING_EMBARC_BSP is not set +# CONFIG_PKG_USING_ESP_IDF is not set + +# +# Kendryte SDK +# +# CONFIG_PKG_USING_K210_SDK is not set +# CONFIG_PKG_USING_KENDRYTE_SDK is not set +# end of Kendryte SDK + +# CONFIG_PKG_USING_NRF5X_SDK is not set +# CONFIG_PKG_USING_NRFX is not set +# CONFIG_PKG_USING_RASPBERRYPI_PICO_RP2350_SDK is not set +# CONFIG_PKG_USING_RASPBERRYPI_PICO_SDK is not set +# CONFIG_PKG_USING_MM32 is not set + +# +# WCH HAL & SDK Drivers +# +# CONFIG_PKG_USING_CH32V20x_SDK is not set +# CONFIG_PKG_USING_CH32V307_SDK is not set +# end of WCH HAL & SDK Drivers + +# +# AT32 HAL & SDK Drivers +# +# CONFIG_PKG_USING_AT32A403A_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32A403A_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32A423_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32A423_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F45x_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F45x_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F402_405_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F402_405_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F403A_407_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F403A_407_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F413_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F413_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F415_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F415_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F421_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F421_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F423_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F423_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F425_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F425_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F435_437_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F435_437_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32M412_416_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32M412_416_CMSIS_DRIVER is not set +# end of AT32 HAL & SDK Drivers + +# +# HC32 DDL Drivers +# +# CONFIG_PKG_USING_HC32F3_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_HC32F3_SERIES_DRIVER is not set +# CONFIG_PKG_USING_HC32F4_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_HC32F4_SERIES_DRIVER is not set +# end of HC32 DDL Drivers + +# +# NXP HAL & SDK Drivers +# +# CONFIG_PKG_USING_NXP_MCX_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_NXP_MCX_SERIES_DRIVER is not set +# CONFIG_PKG_USING_NXP_LPC_DRIVER is not set +# CONFIG_PKG_USING_NXP_LPC55S_DRIVER is not set +# CONFIG_PKG_USING_NXP_IMX6SX_DRIVER is not set +# CONFIG_PKG_USING_NXP_IMX6UL_DRIVER is not set +# CONFIG_PKG_USING_NXP_IMXRT_DRIVER is not set +# end of NXP HAL & SDK Drivers + +# +# NUVOTON Drivers +# +# CONFIG_PKG_USING_NUVOTON_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_NUVOTON_SERIES_DRIVER is not set +# CONFIG_PKG_USING_NUVOTON_ARM926_LIB is not set +# end of NUVOTON Drivers + +# +# GD32 Drivers +# +# CONFIG_PKG_USING_GD32_ARM_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_GD32_ARM_SERIES_DRIVER is not set +# end of GD32 Drivers +# end of HAL & SDK Drivers + +# +# sensors drivers +# +# CONFIG_PKG_USING_LSM6DSM is not set +# CONFIG_PKG_USING_LSM6DSL is not set +# CONFIG_PKG_USING_LPS22HB is not set +# CONFIG_PKG_USING_HTS221 is not set +# CONFIG_PKG_USING_LSM303AGR is not set +# CONFIG_PKG_USING_BME280 is not set +# CONFIG_PKG_USING_BME680 is not set +# CONFIG_PKG_USING_BMA400 is not set +# CONFIG_PKG_USING_BMI160_BMX160 is not set +# CONFIG_PKG_USING_SPL0601 is not set +# CONFIG_PKG_USING_MS5805 is not set +# CONFIG_PKG_USING_DA270 is not set +# CONFIG_PKG_USING_DF220 is not set +# CONFIG_PKG_USING_HSHCAL001 is not set +# CONFIG_PKG_USING_BH1750 is not set +# CONFIG_PKG_USING_MPU6XXX is not set +# CONFIG_PKG_USING_AHT10 is not set +# CONFIG_PKG_USING_AP3216C is not set +# CONFIG_PKG_USING_TSL4531 is not set +# CONFIG_PKG_USING_DS18B20 is not set +# CONFIG_PKG_USING_DHT11 is not set +# CONFIG_PKG_USING_DHTXX is not set +# CONFIG_PKG_USING_GY271 is not set +# CONFIG_PKG_USING_GP2Y10 is not set +# CONFIG_PKG_USING_SGP30 is not set +# CONFIG_PKG_USING_HDC1000 is not set +# CONFIG_PKG_USING_BMP180 is not set +# CONFIG_PKG_USING_BMP280 is not set +# CONFIG_PKG_USING_SHTC1 is not set +# CONFIG_PKG_USING_BMI088 is not set +# CONFIG_PKG_USING_HMC5883 is not set +# CONFIG_PKG_USING_MAX6675 is not set +# CONFIG_PKG_USING_MAX31855 is not set +# CONFIG_PKG_USING_TMP1075 is not set +# CONFIG_PKG_USING_SR04 is not set +# CONFIG_PKG_USING_CCS811 is not set +# CONFIG_PKG_USING_PMSXX is not set +# CONFIG_PKG_USING_RT3020 is not set +# CONFIG_PKG_USING_MLX90632 is not set +# CONFIG_PKG_USING_MLX90382 is not set +# CONFIG_PKG_USING_MLX90393 is not set +# CONFIG_PKG_USING_MLX90392 is not set +# CONFIG_PKG_USING_MLX90394 is not set +# CONFIG_PKG_USING_MLX90397 is not set +# CONFIG_PKG_USING_MS5611 is not set +# CONFIG_PKG_USING_MAX31865 is not set +# CONFIG_PKG_USING_VL53L0X is not set +# CONFIG_PKG_USING_INA260 is not set +# CONFIG_PKG_USING_MAX30102 is not set +# CONFIG_PKG_USING_INA226 is not set +# CONFIG_PKG_USING_LIS2DH12 is not set +# CONFIG_PKG_USING_HS300X is not set +# CONFIG_PKG_USING_ZMOD4410 is not set +# CONFIG_PKG_USING_ISL29035 is not set +# CONFIG_PKG_USING_MMC3680KJ is not set +# CONFIG_PKG_USING_QMP6989 is not set +# CONFIG_PKG_USING_BALANCE is not set +# CONFIG_PKG_USING_SHT2X is not set +# CONFIG_PKG_USING_SHT3X is not set +# CONFIG_PKG_USING_SHT4X is not set +# CONFIG_PKG_USING_AD7746 is not set +# CONFIG_PKG_USING_ADT74XX is not set +# CONFIG_PKG_USING_MAX17048 is not set +# CONFIG_PKG_USING_AS7341 is not set +# CONFIG_PKG_USING_CW2015 is not set +# CONFIG_PKG_USING_ICM20608 is not set +# CONFIG_PKG_USING_PAJ7620 is not set +# CONFIG_PKG_USING_STHS34PF80 is not set +# CONFIG_PKG_USING_P3T1755 is not set +# CONFIG_PKG_USING_QMI8658 is not set +# CONFIG_PKG_USING_ICM20948 is not set +# end of sensors drivers + +# +# touch drivers +# +# CONFIG_PKG_USING_GT9147 is not set +# CONFIG_PKG_USING_GT1151 is not set +# CONFIG_PKG_USING_GT917S is not set +# CONFIG_PKG_USING_GT911 is not set +# CONFIG_PKG_USING_FT6206 is not set +# CONFIG_PKG_USING_FT5426 is not set +# CONFIG_PKG_USING_FT6236 is not set +# CONFIG_PKG_USING_XPT2046_TOUCH is not set +# CONFIG_PKG_USING_CST816X is not set +# CONFIG_PKG_USING_CST812T is not set +# end of touch drivers + +# CONFIG_PKG_USING_REALTEK_AMEBA is not set +# CONFIG_PKG_USING_BUTTON is not set +# CONFIG_PKG_USING_PCF8574 is not set +# CONFIG_PKG_USING_SX12XX is not set +# CONFIG_PKG_USING_SIGNAL_LED is not set +# CONFIG_PKG_USING_LEDBLINK is not set +# CONFIG_PKG_USING_LITTLED is not set +# CONFIG_PKG_USING_LKDGUI is not set +# CONFIG_PKG_USING_INFRARED is not set +# CONFIG_PKG_USING_MULTI_INFRARED is not set +# CONFIG_PKG_USING_AGILE_BUTTON is not set +# CONFIG_PKG_USING_AGILE_LED is not set +# CONFIG_PKG_USING_AT24CXX is not set +# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set +# CONFIG_PKG_USING_PCA9685 is not set +# CONFIG_PKG_USING_ILI9341 is not set +# CONFIG_PKG_USING_I2C_TOOLS is not set +# CONFIG_PKG_USING_NRF24L01 is not set +# CONFIG_PKG_USING_RPLIDAR is not set +# CONFIG_PKG_USING_AS608 is not set +# CONFIG_PKG_USING_RC522 is not set +# CONFIG_PKG_USING_WS2812B is not set +# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set +# CONFIG_PKG_USING_MULTI_RTIMER is not set +# CONFIG_PKG_USING_MAX7219 is not set +# CONFIG_PKG_USING_BEEP is not set +# CONFIG_PKG_USING_EASYBLINK is not set +# CONFIG_PKG_USING_PMS_SERIES is not set +# CONFIG_PKG_USING_CAN_YMODEM is not set +# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set +# CONFIG_PKG_USING_QLED is not set +# CONFIG_PKG_USING_AGILE_CONSOLE is not set +# CONFIG_PKG_USING_LD3320 is not set +# CONFIG_PKG_USING_WK2124 is not set +# CONFIG_PKG_USING_LY68L6400 is not set +# CONFIG_PKG_USING_DM9051 is not set +# CONFIG_PKG_USING_SSD1306 is not set +# CONFIG_PKG_USING_QKEY is not set +# CONFIG_PKG_USING_RS485 is not set +# CONFIG_PKG_USING_RS232 is not set +# CONFIG_PKG_USING_NES is not set +# CONFIG_PKG_USING_VIRTUAL_SENSOR is not set +# CONFIG_PKG_USING_VDEVICE is not set +# CONFIG_PKG_USING_SGM706 is not set +# CONFIG_PKG_USING_RDA58XX is not set +# CONFIG_PKG_USING_LIBNFC is not set +# CONFIG_PKG_USING_MFOC is not set +# CONFIG_PKG_USING_TMC51XX is not set +# CONFIG_PKG_USING_TCA9534 is not set +# CONFIG_PKG_USING_KOBUKI is not set +# CONFIG_PKG_USING_ROSSERIAL is not set +# CONFIG_PKG_USING_MICRO_ROS is not set +# CONFIG_PKG_USING_MCP23008 is not set +# CONFIG_PKG_USING_MISAKA_AT24CXX is not set +# CONFIG_PKG_USING_MISAKA_RGB_BLING is not set +# CONFIG_PKG_USING_LORA_MODEM_DRIVER is not set +# CONFIG_PKG_USING_SOFT_SERIAL is not set +# CONFIG_PKG_USING_MB85RS16 is not set +# CONFIG_PKG_USING_RFM300 is not set +# CONFIG_PKG_USING_IO_INPUT_FILTER is not set +# CONFIG_PKG_USING_LRF_NV7LIDAR is not set +# CONFIG_PKG_USING_AIP650 is not set +# CONFIG_PKG_USING_FINGERPRINT is not set +# CONFIG_PKG_USING_BT_ECB02C is not set +# CONFIG_PKG_USING_UAT is not set +# CONFIG_PKG_USING_ST7789 is not set +# CONFIG_PKG_USING_VS1003 is not set +# CONFIG_PKG_USING_X9555 is not set +# CONFIG_PKG_USING_SYSTEM_RUN_LED is not set +# CONFIG_PKG_USING_BT_MX01 is not set +# CONFIG_PKG_USING_RGPOWER is not set +# CONFIG_PKG_USING_BT_MX02 is not set +# CONFIG_PKG_USING_GC9A01 is not set +# CONFIG_PKG_USING_IK485 is not set +# CONFIG_PKG_USING_SERVO is not set +# CONFIG_PKG_USING_SEAN_WS2812B is not set +# CONFIG_PKG_USING_IC74HC165 is not set +# CONFIG_PKG_USING_IST8310 is not set +# CONFIG_PKG_USING_ST7789_SPI is not set +# CONFIG_PKG_USING_SPI_TOOLS is not set +# end of peripheral libraries and drivers + +# +# AI packages +# +# CONFIG_PKG_USING_LIBANN is not set +# CONFIG_PKG_USING_NNOM is not set +# CONFIG_PKG_USING_ONNX_BACKEND is not set +# CONFIG_PKG_USING_ONNX_PARSER is not set +# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set +# CONFIG_PKG_USING_ELAPACK is not set +# CONFIG_PKG_USING_ULAPACK is not set +# CONFIG_PKG_USING_QUEST is not set +# CONFIG_PKG_USING_NAXOS is not set +# CONFIG_PKG_USING_R_TINYMAIX is not set +# CONFIG_PKG_USING_LLMCHAT is not set +# end of AI packages + +# +# Signal Processing and Control Algorithm Packages +# +# CONFIG_PKG_USING_APID is not set +# CONFIG_PKG_USING_FIRE_PID_CURVE is not set +# CONFIG_PKG_USING_QPID is not set +# CONFIG_PKG_USING_UKAL is not set +# CONFIG_PKG_USING_DIGITALCTRL is not set +# CONFIG_PKG_USING_KISSFFT is not set +# CONFIG_PKG_USING_CMSIS_DSP is not set +# end of Signal Processing and Control Algorithm Packages + +# +# miscellaneous packages +# + +# +# project laboratory +# +# end of project laboratory + +# +# samples: kernel and components samples +# +# CONFIG_PKG_USING_KERNEL_SAMPLES is not set +# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set +# CONFIG_PKG_USING_NETWORK_SAMPLES is not set +# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set +# end of samples: kernel and components samples + +# +# entertainment: terminal games and other interesting software packages +# +# CONFIG_PKG_USING_CMATRIX is not set +# CONFIG_PKG_USING_SL is not set +# CONFIG_PKG_USING_CAL is not set +# CONFIG_PKG_USING_ACLOCK is not set +# CONFIG_PKG_USING_THREES is not set +# CONFIG_PKG_USING_2048 is not set +# CONFIG_PKG_USING_SNAKE is not set +# CONFIG_PKG_USING_TETRIS is not set +# CONFIG_PKG_USING_DONUT is not set +# CONFIG_PKG_USING_COWSAY is not set +# CONFIG_PKG_USING_MORSE is not set +# CONFIG_PKG_USING_TINYSQUARE is not set +# end of entertainment: terminal games and other interesting software packages + +# CONFIG_PKG_USING_LIBCSV is not set +# CONFIG_PKG_USING_OPTPARSE is not set +# CONFIG_PKG_USING_FASTLZ is not set +# CONFIG_PKG_USING_MINILZO is not set +# CONFIG_PKG_USING_QUICKLZ is not set +# CONFIG_PKG_USING_LZMA is not set +# CONFIG_PKG_USING_RALARAM is not set +# CONFIG_PKG_USING_MULTIBUTTON is not set +# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set +# CONFIG_PKG_USING_CANFESTIVAL is not set +# CONFIG_PKG_USING_ZLIB is not set +# CONFIG_PKG_USING_MINIZIP is not set +# CONFIG_PKG_USING_HEATSHRINK is not set +# CONFIG_PKG_USING_DSTR is not set +# CONFIG_PKG_USING_TINYFRAME is not set +# CONFIG_PKG_USING_KENDRYTE_DEMO is not set +# CONFIG_PKG_USING_UPACKER is not set +# CONFIG_PKG_USING_UPARAM is not set +# CONFIG_PKG_USING_HELLO is not set +# CONFIG_PKG_USING_VI is not set +# CONFIG_PKG_USING_KI is not set +# CONFIG_PKG_USING_ARMv7M_DWT is not set +# CONFIG_PKG_USING_CRCLIB is not set +# CONFIG_PKG_USING_LIBCRC is not set +# CONFIG_PKG_USING_LWGPS is not set +# CONFIG_PKG_USING_STATE_MACHINE is not set +# CONFIG_PKG_USING_DESIGN_PATTERN is not set +# CONFIG_PKG_USING_CONTROLLER is not set +# CONFIG_PKG_USING_PHASE_LOCKED_LOOP is not set +# CONFIG_PKG_USING_MFBD is not set +# CONFIG_PKG_USING_SLCAN2RTT is not set +# CONFIG_PKG_USING_SOEM is not set +# CONFIG_PKG_USING_QPARAM is not set +# CONFIG_PKG_USING_CorevMCU_CLI is not set +# CONFIG_PKG_USING_DRMP is not set +# end of miscellaneous packages + +# +# Arduino libraries +# +# CONFIG_PKG_USING_RTDUINO is not set + +# +# Projects and Demos +# +# CONFIG_PKG_USING_ARDUINO_MSGQ_C_CPP_DEMO is not set +# CONFIG_PKG_USING_ARDUINO_SKETCH_LOADER_DEMO is not set +# CONFIG_PKG_USING_ARDUINO_ULTRASOUND_RADAR is not set +# CONFIG_PKG_USING_ARDUINO_RTDUINO_SENSORFUSION_SHIELD is not set +# CONFIG_PKG_USING_ARDUINO_NINEINONE_SENSOR_SHIELD is not set +# CONFIG_PKG_USING_ARDUINO_SENSOR_KIT is not set +# CONFIG_PKG_USING_ARDUINO_MATLAB_SUPPORT is not set +# end of Projects and Demos + +# +# Sensors +# +# CONFIG_PKG_USING_ARDUINO_SENSOR_DEVICE_DRIVERS is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSOR is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSORLAB is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL375 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L0X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L1X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL6180X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31855 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31865 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31856 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX6675 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90614 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM9DS1 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AHTX0 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM9DS0 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP280 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADT7410 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP085 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BME680 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP9808 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4728 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA219 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LTR390 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL345 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DHT is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP9600 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM6DS is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO055 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX1704X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMC56X3 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90393 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90395 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ICM20X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DPS310 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTS221 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHT4X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHT31 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL343 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BME280 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS726X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AMG88XX is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AM2320 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AM2315 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LTR329_LTR303 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP085_UNIFIED is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP183 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP183_UNIFIED is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP3XX is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MS8607 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3MDL is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90640 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMA8451 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MSA301 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL115A2 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X_RVC is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS2MDL is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM303DLH_MAG is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LC709203F is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_CAP1188 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_CCS811 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_NAU7802 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS331 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LPS2X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LPS35HW is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM303_ACCEL is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3DH is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8591 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL3115A2 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPR121 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPRLS is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPU6050 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCT2075 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PM25AQI is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_EMC2101 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_FXAS21002C is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SCD30 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_FXOS8700 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HMC5883_UNIFIED is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SGP30 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP006 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TLA202X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TCS34725 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI7021 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI1145 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SGP40 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHTC3 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HDC1000 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU21DF is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS7341 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU31D is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA260 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP007_LIBRARY is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_L3GD20 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP117 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSC2007 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSL2561 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSL2591_LIBRARY is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VCNL4040 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML6070 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML6075 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML7700 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LIS3DHTR is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_DHT is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_ADXL335 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_ADXL345 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BME280 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BMP280 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_H3LIS331DL is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_MMA7660 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_TSL2561 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_PAJ7620 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_VL53L0X is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_ITG3200 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_SHT31 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HP20X is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_DRV2605L is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BBM150 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HMC5883L is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LSM303DLH is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_TCS3414CS is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_MP503 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BMP085 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HIGHTEMP is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_VEML6070 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_SI1145 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_SHT35 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_AT42QT1070 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LSM6DS3 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HDC1000 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HM3301 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_MCP9600 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LTC2941 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LDC1612 is not set +# CONFIG_PKG_USING_ARDUINO_CAPACITIVESENSOR is not set +# CONFIG_PKG_USING_ARDUINO_JARZEBSKI_MPU6050 is not set +# end of Sensors + +# +# Display +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_GFX_LIBRARY is not set +# CONFIG_PKG_USING_ARDUINO_U8G2 is not set +# CONFIG_PKG_USING_ARDUINO_TFT_ESPI is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ST7735 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SSD1306 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ILI9341 is not set +# CONFIG_PKG_USING_SEEED_TM1637 is not set +# end of Display + +# +# Timing +# +# CONFIG_PKG_USING_ARDUINO_RTCLIB is not set +# CONFIG_PKG_USING_ARDUINO_MSTIMER2 is not set +# CONFIG_PKG_USING_ARDUINO_TICKER is not set +# CONFIG_PKG_USING_ARDUINO_TASKSCHEDULER is not set +# end of Timing + +# +# Data Processing +# +# CONFIG_PKG_USING_ARDUINO_KALMANFILTER is not set +# CONFIG_PKG_USING_ARDUINO_ARDUINOJSON is not set +# CONFIG_PKG_USING_ARDUINO_TENSORFLOW_LITE_MICRO is not set +# CONFIG_PKG_USING_ARDUINO_RUNNINGMEDIAN is not set +# end of Data Processing + +# +# Data Storage +# + +# +# Communication +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PN532 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI4713 is not set +# end of Communication + +# +# Device Control +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8574 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCA9685 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TPA2016 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DRV2605 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS1841 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS3502 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_PCF85063TP is not set +# end of Device Control + +# +# Other +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MFRC630 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI5351 is not set +# end of Other + +# +# Signal IO +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BUSIO is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TCA8418 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP23017 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADS1X15 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AW9523 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP3008 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4725 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BD3491FS is not set +# end of Signal IO + +# +# Uncategorized +# +# end of Arduino libraries +# end of RT-Thread online packages + +CONFIG_SOC_FAMILY_FT32=y +CONFIG_SOC_SERIES_FT32F4=y + +# +# Hardware Drivers Config +# +CONFIG_SOC_FT32F407VE=y + +# +# Onboard Peripheral Drivers +# + +# +# On-chip Peripheral Drivers +# +CONFIG_BSP_USING_GPIO=y +CONFIG_BSP_USING_UART=y +# CONFIG_BSP_USING_UART1 is not set +CONFIG_BSP_USING_UART2=y +# CONFIG_BSP_USING_CRC is not set +# end of On-chip Peripheral Drivers + +# +# Board extended module Drivers +# +# end of Hardware Drivers Config diff --git a/bsp/ft32/ft32f407xe-starter/.gitignore b/bsp/ft32/ft32f407xe-starter/.gitignore new file mode 100644 index 00000000000..7221bde019d --- /dev/null +++ b/bsp/ft32/ft32f407xe-starter/.gitignore @@ -0,0 +1,42 @@ +*.pyc +*.map +*.dblite +*.elf +*.bin +*.hex +*.axf +*.exe +*.pdb +*.idb +*.ilk +*.old +build +Debug +documentation/html +packages/ +*~ +*.o +*.obj +*.out +*.bak +*.dep +*.lib +*.i +*.d +.DS_Stor* +.config 3 +.config 4 +.config 5 +Midea-X1 +*.uimg +GPATH +GRTAGS +GTAGS +.vscode +JLinkLog.txt +JLinkSettings.ini +DebugConfig/ +RTE/ +settings/ +*.uvguix* +cconfig.h diff --git a/bsp/ft32/ft32f407xe-starter/Kconfig b/bsp/ft32/ft32f407xe-starter/Kconfig new file mode 100644 index 00000000000..029e5afd21a --- /dev/null +++ b/bsp/ft32/ft32f407xe-starter/Kconfig @@ -0,0 +1,13 @@ +mainmenu "RT-Thread Configuration" + +BSP_DIR := . + +RTT_DIR := ../../.. + +PKGS_DIR := packages + +source "$(RTT_DIR)/Kconfig" +osource "$PKGS_DIR/Kconfig" +rsource "../libraries/Kconfig" +rsource "board/Kconfig" + diff --git a/bsp/ft32/ft32f407xe-starter/README.md b/bsp/ft32/ft32f407xe-starter/README.md new file mode 100644 index 00000000000..181d7cf9317 --- /dev/null +++ b/bsp/ft32/ft32f407xe-starter/README.md @@ -0,0 +1,53 @@ +# FT32F407xx-StarterKit-32 # + +## 1. 简介 + +[StarterKit-32](https://www.fremontmicro.com/down/demoboard/index.aspx)是辉芒微提供的开发板，使用 Cortex-M4 内核的 FT32F407xE 作为主控制器。提供包括扩展引脚等外设资源。 + +板载主要资源如下： + +| 硬件 | 描述 | +| -- | -- | +|CPU| Cortex-M4 | +|主频| 210MHz | +|SRAM| 128KB+64KB | +|Flash| 512KB | + +- 常用外设 + - LED：3个，（PD13、PD14、PD15） + - 按键：1个，（PA0或PC13) +- 常用接口：串口（PA2、PA3） + +## 2. 编译说明 + +StarterKit-32板级包支持 MDK5，以下是具体版本信息： + +| IDE/编译器 | 已测试版本 | +| -- | -- | +| MDK5(ARM Compiler 5 and 6) | MDK5.38 | + +## 3. 烧写及执行 + +下载程序：使用 CMSIS-DAP或者J-link等工具。 + +### 3.1 配置和仿真 + +工程已经默认使能了RT-Thread UART驱动、GPIO驱动。若想进一步配置工程请 +使用ENV工具。 + +## 4. 驱动支持情况及计划 + +| 驱动 | 支持情况 | 备注 | +| ------ | ---- | :------: | +| UART | 支持 | USART0/1 | +| GPIO | 支持 | | + +## 5. 联系人信息 + +维护人： + +- [FMD-AE](https://github.com/FmdAE) + +## 6. 参考 + +* [StarterKit-32](https://www.fremontmicro.com/down/demoboard/index.aspx) diff --git a/bsp/ft32/ft32f407xe-starter/SConscript b/bsp/ft32/ft32f407xe-starter/SConscript new file mode 100644 index 00000000000..20f7689c53c --- /dev/null +++ b/bsp/ft32/ft32f407xe-starter/SConscript @@ -0,0 +1,15 @@ +# for module compiling +import os +Import('RTT_ROOT') +from building import * + +cwd = GetCurrentDir() +objs = [] +list = os.listdir(cwd) + +for d in list: + path = os.path.join(cwd, d) + if os.path.isfile(os.path.join(path, 'SConscript')): + objs = objs + SConscript(os.path.join(d, 'SConscript')) + +Return('objs') diff --git a/bsp/ft32/ft32f407xe-starter/SConstruct b/bsp/ft32/ft32f407xe-starter/SConstruct new file mode 100644 index 00000000000..6fe97243cf8 --- /dev/null +++ b/bsp/ft32/ft32f407xe-starter/SConstruct @@ -0,0 +1,73 @@ +import os +import sys +import rtconfig + +if os.getenv('RTT_ROOT'): + RTT_ROOT = os.getenv('RTT_ROOT') +else: + RTT_ROOT = os.path.normpath(os.getcwd() + '/../../..') + +sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')] +try: + from building import * +except: + print('Cannot found RT-Thread root directory, please check RTT_ROOT') + print(RTT_ROOT) + exit(-1) + +def bsp_pkg_check(): + import subprocess + + check_paths = [ + os.path.join("packages", "ft32f4_cmsis_driver-latest"), + os.path.join("packages", "ft32f4_std_driver-latest") + ] + + need_update = not all(os.path.exists(p) for p in check_paths) + + if need_update: + print("\n===============================================================================") + print("Dependency packages missing, please running 'pkgs --update'...") + print("If no packages are fetched, run 'pkgs --upgrade' first, then 'pkgs --update'...") + print("===============================================================================") + exit(1) + +RegisterPreBuildingAction(bsp_pkg_check) + +TARGET = 'rt-thread.' + rtconfig.TARGET_EXT + +DefaultEnvironment(tools=[]) +env = Environment(tools = ['mingw'], + AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS, + CC = rtconfig.CC, CFLAGS = rtconfig.CFLAGS, + AR = rtconfig.AR, ARFLAGS = '-rc', + CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS, + LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS) +env.PrependENVPath('PATH', rtconfig.EXEC_PATH) + +if rtconfig.PLATFORM in ['iccarm']: + env.Replace(CCCOM = ['$CC $CFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES']) + env.Replace(ARFLAGS = ['']) + env.Replace(LINKCOM = env["LINKCOM"] + ' --map rt-thread.map') + +Export('env') +Export('RTT_ROOT') +Export('rtconfig') + +SDK_ROOT = os.path.abspath('./') + +if os.path.exists(SDK_ROOT + '/libraries'): + libraries_path_prefix = SDK_ROOT + '/libraries' +else: + libraries_path_prefix = os.path.dirname(SDK_ROOT) + '/libraries' + +# prepare building environment +objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False) + +rtconfig.BSP_LIBRARY_TYPE = None + +# include drivers +objs.extend(SConscript(os.path.join(libraries_path_prefix, 'STD_Drivers', 'SConscript'), variant_dir='../libraries/Drivers', duplicate=0)) + +# make a building +DoBuilding(TARGET, objs) diff --git a/bsp/ft32/ft32f407xe-starter/applications/SConscript b/bsp/ft32/ft32f407xe-starter/applications/SConscript new file mode 100644 index 00000000000..5efd37ed23c --- /dev/null +++ b/bsp/ft32/ft32f407xe-starter/applications/SConscript @@ -0,0 +1,9 @@ +from building import * + +cwd = GetCurrentDir() +src = Glob('*.c') + Glob('*.cpp') +CPPPATH = [cwd] + +group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH) + +Return('group') diff --git a/bsp/ft32/ft32f407xe-starter/applications/main.c b/bsp/ft32/ft32f407xe-starter/applications/main.c new file mode 100644 index 00000000000..f9919d8538d --- /dev/null +++ b/bsp/ft32/ft32f407xe-starter/applications/main.c @@ -0,0 +1,30 @@ +/* + * Copyright (c) 2006-2022, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2022-03-02 FMD-AE first version + */ + +#include +#include +#include + +/* defined the LED2 pin: PD13 */ +#define LED2_PIN GET_PIN(D, 13) + +int main(void) +{ + /* set LED0 pin mode to output */ + rt_pin_mode(LED2_PIN, PIN_MODE_OUTPUT); + + while (1) + { + rt_pin_write(LED2_PIN, PIN_HIGH); + rt_thread_mdelay(500); + rt_pin_write(LED2_PIN, PIN_LOW); + rt_thread_mdelay(500); + } +} diff --git a/bsp/ft32/ft32f407xe-starter/board/Kconfig b/bsp/ft32/ft32f407xe-starter/board/Kconfig new file mode 100644 index 00000000000..3ffe9bb91fd --- /dev/null +++ b/bsp/ft32/ft32f407xe-starter/board/Kconfig @@ -0,0 +1,59 @@ +menu "Hardware Drivers Config" + +config SOC_SERIES_FT32F4 + bool + default y + +config SOC_FT32F407VE + bool + select SOC_SERIES_FT32F4 + select RT_USING_COMPONENTS_INIT + select RT_USING_USER_MAIN + default y + +menu "Onboard Peripheral Drivers" + +endmenu + +menu "On-chip Peripheral Drivers" + + config BSP_USING_GPIO + bool "Enable GPIO" + select RT_USING_PIN + default y + + menuconfig BSP_USING_UART + bool "Enable UART" + default y + if BSP_USING_UART + choice + prompt "Select UART framework version" + default BSP_USING_SERIAL_V1 + + config BSP_USING_SERIAL_V1 + bool "Use Serial V1 framework" + select RT_USING_SERIAL + + config BSP_USING_SERIAL_V2 + bool "Use Serial V2 framework" + select RT_USING_SERIAL_V2 + endchoice + + menuconfig BSP_USING_UART1 + bool "Enable UART1" + default n + + menuconfig BSP_USING_UART2 + bool "Enable UART2" + default y + endif + + source "$(BSP_DIR)/../libraries/Drivers/Kconfig" + +endmenu + +menu "Board extended module Drivers" + +endmenu + +endmenu diff --git a/bsp/ft32/ft32f407xe-starter/board/SConscript b/bsp/ft32/ft32f407xe-starter/board/SConscript new file mode 100644 index 00000000000..359e1e9a3c9 --- /dev/null +++ b/bsp/ft32/ft32f407xe-starter/board/SConscript @@ -0,0 +1,17 @@ +import os +from building import * + +cwd = GetCurrentDir() + +# add general drivers +src = Split(''' +board.c +''') + +path = [cwd] + +# FT32F407xE +# You can select chips from the list above +CPPDEFINES = ['FT32F407xE'] +group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES) +Return('group') diff --git a/bsp/ft32/ft32f407xe-starter/board/board.c b/bsp/ft32/ft32f407xe-starter/board/board.c new file mode 100644 index 00000000000..41b06ac6de7 --- /dev/null +++ b/bsp/ft32/ft32f407xe-starter/board/board.c @@ -0,0 +1,153 @@ +/* + * Copyright (c) 2006-2022, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2022-03-02 FMD-AE first version + */ + +#include "board.h" + +#ifdef RT_USING_SERIAL + #include "drv_usart.h" +#endif /* RT_USING_SERIAL */ + +#define DBG_TAG "drv_common" +#define DBG_LVL DBG_INFO +#include + +#ifdef RT_USING_FINSH +#include + +static void reboot(uint8_t argc, char **argv) +{ + rt_hw_cpu_reset(); +} +MSH_CMD_EXPORT(reboot, Reboot System); +#endif /* RT_USING_FINSH */ + +__IO uint32_t uwTick; +static uint32_t _systick_ms = 1; + +void IncTick(void) +{ + uwTick += _systick_ms; +} +/** + * This is the timer interrupt service routine. + * + */ +void SysTick_Handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + if (SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) + IncTick(); + + rt_tick_increase(); + + /* leave interrupt */ + rt_interrupt_leave(); +} + +uint32_t GetTick(void) +{ + if (SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) + IncTick(); + + return uwTick; +} + +void SuspendTick(void) +{ +} + +void ResumeTick(void) +{ +} + +void Delay(__IO uint32_t Delay) +{ + if (rt_thread_self()) + { + rt_thread_mdelay(Delay); + } + else + { + for (rt_uint32_t count = 0; count < Delay; count++) + { + rt_hw_us_delay(1000); + } + } +} +/** + * This function will delay for some us. + * + * @param us the delay time of us + */ +void rt_hw_us_delay(rt_uint32_t us) +{ + rt_uint32_t ticks; + rt_uint32_t told, tnow, tcnt = 0; + rt_uint32_t reload = SysTick->LOAD; + + ticks = us * reload / (1000000 / RT_TICK_PER_SECOND); + told = SysTick->VAL; + while (1) + { + tnow = SysTick->VAL; + if (tnow != told) + { + if (tnow < told) + { + tcnt += told - tnow; + } + else + { + tcnt += reload - tnow + told; + } + told = tnow; + if (tcnt >= ticks) + { + break; + } + } + } +} + +/** + * This function will initial FT32 board. + */ +rt_weak void rt_hw_board_init() +{ + SysTick_Config(SystemCoreClock / RT_TICK_PER_SECOND); + /* Heap initialization */ +#if defined(RT_USING_HEAP) + rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END); +#endif + + /* Pin driver initialization is open by default */ +#ifdef RT_USING_PIN + rt_hw_pin_init(); +#endif + + /* USART driver initialization is open by default */ +#ifdef RT_USING_SERIAL + rt_hw_usart_init(); +#endif + + /* Set the shell console output device */ +#if defined(RT_USING_CONSOLE) && defined(RT_USING_DEVICE) + rt_console_set_device(RT_CONSOLE_DEVICE_NAME); +#endif + + /* Board underlying hardware initialization */ +#ifdef RT_USING_COMPONENTS_INIT + rt_components_board_init(); +#endif +} + + diff --git a/bsp/ft32/ft32f407xe-starter/board/board.h b/bsp/ft32/ft32f407xe-starter/board/board.h new file mode 100644 index 00000000000..b8611133be1 --- /dev/null +++ b/bsp/ft32/ft32f407xe-starter/board/board.h @@ -0,0 +1,57 @@ +/* + * Copyright (c) 2006-2022, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2022-03-02 FMD-AE first version + */ + +#ifndef __BOARD_H__ +#define __BOARD_H__ + +#include +#include +#include "drv_gpio.h" +#include +#include +#include +#include +#include +#include +#include +#ifdef RT_USING_DEVICE + #include +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +#define FT32_FLASH_START_ADRESS ((uint32_t)0x08000000) +#define FT32_FLASH_SIZE (128 * 1024) +#define FT32_FLASH_END_ADDRESS ((uint32_t)(FT32_FLASH_START_ADRESS + FT32_FLASH_SIZE)) + +/* Internal SRAM memory size[Kbytes] <8-64>, Default: 64*/ +#define FT32_SRAM_SIZE 24 +#define FT32_SRAM_END (0x20000000 + FT32_SRAM_SIZE * 1024) + +#if defined(__ARMCC_VERSION) +extern int Image$$RW_IRAM1$$ZI$$Limit; +#define HEAP_BEGIN ((void *)&Image$$RW_IRAM1$$ZI$$Limit) +#elif __ICCARM__ +#pragma section="CSTACK" +#define HEAP_BEGIN (__segment_end("CSTACK")) +#else +extern int __bss_end; +#define HEAP_BEGIN ((void *)&__bss_end) +#endif + +#define HEAP_END FT32_SRAM_END + +#ifdef __cplusplus +} +#endif + +#endif /* __BOARD_H__ */ diff --git a/bsp/ft32/ft32f407xe-starter/board/linker_scripts/link.icf b/bsp/ft32/ft32f407xe-starter/board/linker_scripts/link.icf new file mode 100644 index 00000000000..ae5a7f57f86 --- /dev/null +++ b/bsp/ft32/ft32f407xe-starter/board/linker_scripts/link.icf @@ -0,0 +1,34 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x08000000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x08000000; +define symbol __ICFEDIT_region_ROM_end__ = 0x0807FFFF; +define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x2001FFFF; +define symbol __ICFEDIT_region_CCMRAM_start__ = 0x10000000; +define symbol __ICFEDIT_region_CCMRAM_end__ = 0x1000FFFF; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x400; +define symbol __ICFEDIT_size_heap__ = 0x200; +/**** End of ICF editor section. ###ICF###*/ + + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; +define region CCMRAM_region = mem:[from __ICFEDIT_region_CCMRAM_start__ to __ICFEDIT_region_CCMRAM_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; + +place in ROM_region { readonly }; +place in RAM_region { readwrite, + block CSTACK, block HEAP }; \ No newline at end of file diff --git a/bsp/rockchip/rk3568/link.lds b/bsp/ft32/ft32f407xe-starter/board/linker_scripts/link.lds similarity index 58% rename from bsp/rockchip/rk3568/link.lds rename to bsp/ft32/ft32f407xe-starter/board/linker_scripts/link.lds index c720509d9a4..cbe152d39f5 100644 --- a/bsp/rockchip/rk3568/link.lds +++ b/bsp/ft32/ft32f407xe-starter/board/linker_scripts/link.lds @@ -1,111 +1,124 @@ /* - * Copyright (c) 2006-2023, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2017-5-30 bernard first version + * linker script for STM32F10x with GNU ld */ -OUTPUT_FORMAT("elf64-littleaarch64", "elf64-littleaarch64", "elf64-littleaarch64") -OUTPUT_ARCH(aarch64) +/* Program Entry, set to mark it as "used" and avoid gc */ +MEMORY +{ + ROM (rx) : ORIGIN = 0x08000000, LENGTH = 512k /* 512KB flash */ + RAM (rw) : ORIGIN = 0x20000000, LENGTH = 128k /* 128K sram */ +} +ENTRY(Reset_Handler) +_system_stack_size = 0x400; SECTIONS { - _text_offset = 0x20000000; - - . = 0x20000000; - . = ALIGN(4096); .text : { - KEEP(*(.text.entrypoint)) /* The entry point */ - *(.vectors) + . = ALIGN(4); + _stext = .; + KEEP(*(.isr_vector)) /* Startup code */ + + . = ALIGN(4); *(.text) /* remaining code */ *(.text.*) /* remaining code */ - *(.rodata) /* read-only data (constants) */ *(.rodata*) *(.glue_7) *(.glue_7t) *(.gnu.linkonce.t*) - *(COMMON) - /* section information for finsh shell */ - . = ALIGN(16); + . = ALIGN(4); __fsymtab_start = .; KEEP(*(FSymTab)) __fsymtab_end = .; - . = ALIGN(16); + + . = ALIGN(4); __vsymtab_start = .; KEEP(*(VSymTab)) __vsymtab_end = .; - . = ALIGN(16); /* section information for initial. */ - . = ALIGN(16); + . = ALIGN(4); __rt_init_start = .; KEEP(*(SORT(.rti_fn*))) __rt_init_end = .; - . = ALIGN(16); - . = ALIGN(16); + . = ALIGN(4); + + PROVIDE(__ctors_start__ = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array)) + PROVIDE(__ctors_end__ = .); + + . = ALIGN(4); + _etext = .; - } + } > ROM = 0 - .eh_frame_hdr : + /* .ARM.exidx is sorted, so has to go in its own output section. */ + __exidx_start = .; + .ARM.exidx : { - *(.eh_frame_hdr) - *(.eh_frame_entry) - } - .eh_frame : ONLY_IF_RO { KEEP (*(.eh_frame)) } + *(.ARM.exidx* .gnu.linkonce.armexidx.*) - . = ALIGN(16); - .data : - { - *(.data) - *(.data.*) + /* This is used by the startup in order to initialize the .data secion */ + _sidata = .; + } > ROM + __exidx_end = .; - *(.data1) - *(.data1.*) + /* .data section which is used for initialized data */ - . = ALIGN(16); - _gp = ABSOLUTE(.); /* Base of small data */ + .data : AT (_sidata) + { + . = ALIGN(4); + /* This is used by the startup in order to initialize the .data secion */ + _sdata = . ; - *(.sdata) - *(.sdata.*) - } + *(.data) + *(.data.*) + *(.gnu.linkonce.d*) - . = ALIGN(16); - .ctors : - { - PROVIDE(__ctors_start__ = .); - /* new GCC version uses .init_array */ - KEEP(*(SORT(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE(__ctors_end__ = .); - } - .dtors : - { PROVIDE(__dtors_start__ = .); KEEP(*(SORT(.dtors.*))) KEEP(*(.dtors)) PROVIDE(__dtors_end__ = .); - } - . = ALIGN(16); + . = ALIGN(4); + /* This is used by the startup in order to initialize the .data secion */ + _edata = . ; + } >RAM + + .stack : + { + . = ALIGN(4); + _sstack = .; + . = . + _system_stack_size; + . = ALIGN(4); + _estack = .; + } >RAM + + __bss_start = .; .bss : { - PROVIDE(__bss_start = .); + . = ALIGN(4); + /* This is used by the startup in order to initialize the .bss secion */ + _sbss = .; + *(.bss) *(.bss.*) - *(.dynbss) + *(COMMON) + + . = ALIGN(4); + /* This is used by the startup in order to initialize the .bss secion */ + _ebss = . ; + + *(.bss.init) + } > RAM + __bss_end = .; - . = ALIGN(16); - PROVIDE(__bss_end = .); - } _end = .; /* Stabs debugging sections. */ @@ -142,5 +155,3 @@ SECTIONS .debug_typenames 0 : { *(.debug_typenames) } .debug_varnames 0 : { *(.debug_varnames) } } - -__bss_size = SIZEOF(.bss); diff --git a/bsp/ft32/ft32f407xe-starter/board/linker_scripts/link.sct b/bsp/ft32/ft32f407xe-starter/board/linker_scripts/link.sct new file mode 100644 index 00000000000..5d1e3e6c008 --- /dev/null +++ b/bsp/ft32/ft32f407xe-starter/board/linker_scripts/link.sct @@ -0,0 +1,15 @@ +; ************************************************************* +; *** Scatter-Loading Description File generated by uVision *** +; ************************************************************* + +LR_IROM1 0x08000000 0x00080000 { ; load region size_region + ER_IROM1 0x08000000 0x00080000 { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + } + RW_IRAM1 0x20000000 0x00020000 { ; RW data + .ANY (+RW +ZI) + } +} + diff --git a/bsp/ft32/ft32f407xe-starter/figures/ft32f407xe-starter.jpg b/bsp/ft32/ft32f407xe-starter/figures/ft32f407xe-starter.jpg new file mode 100644 index 0000000000000000000000000000000000000000..444e0ac9f2fdf6d73271bfabbafe5fe34e5e8cfe GIT binary patch literal 831855 zcmb@t1ymeSvo6|$yOZD$90DY0a0UqO8YID;;O+wi8{8#Wa3{EXa19U$?hxD|_#J*Z z|2c2n_11fL-92$@dkpw^>006;Wz|%S$myEc$zOt&4 zq>Q}8KRV!O4ejkeBLDzkW9#gwDkVmxrL9ASyaph{UYNiOfXdL=$zD`hSsrEr{QLb` z{!hD_c^(}ArdXfH8X`#yp!35~;7!H<^>dFf;6HZ%TM5m?)X5mua}V20jqM$sVUsn1 z$uw@x_Rn%COeS!IO$sKbKg;I-l)pdAM*oz5{KH0FRUBsX8zxg3TNuK|0R4r@EJpuL zZ~oupe_a=50-(RQbh7_!=s~5-`F!|)w>g`-!~6gMaXWhtM@w@HXDU(HDw$Hr*c!93 zP;tCve+K~1YyQuxo~!(0EkQ3v{-XCcu|L9~p0H6wXCR)>fbd00(=JUjyYbAy9>77(5r96TZ-0s`z0 z0pWR&e~kb;3l0GuX7&HOJ#_-OC`cs;Pw*gW01g)fj|+PG0Z_s|XvBYx{m&(Y9m7UP zL_$VEMMH-f)ZqYdAlSqZ{xKa`uMeyrK)^-Bd&Mq_gs)sTvhiBlIpx}_uFlbzSLSj;KN@`k8ZeD&tVNr2ObxmzueM4hYb9c{=-oE~U!J)~i z>0dLmzvt%H);Bh{ws-#Q?wy{UUtC^Y|Gl|=_6r2S|7*#ff5Fe~|KS%d%r7_u1b75w z*c!t+-JT6_5fERoBjJgvAR9X1Q*-#E5QxQotLj3f;Z!{#G;;ij_JWpcjqdc>wSRc_ z|IM+0|0B=-%d!9XH4k9GgJ2&XJT4#tJnWn)c|QhZe$UMIQ)NB^{s8yPrW$=tSzCG@ zV=6eAH;?M4$o8Q7Q9Z!?`?$Ay3lbKG`#OZ<#0Psz68qbI$uQGkC-1GQ!7b$w`UMny6J>q|QYM@qeqw>5LHO5e@&XzBZ%)AkMw+}tw%GX=Wp8R@uzW&v zoZsSjkh!kcZGc}=`u75+%<1ojmV9gfXf#leR+ihcHsdIbj!))B5n{O84M8|lvDSLL zoY%`z2GQRBGJ4;GMY@nL7qN=-_b^=nW^8%%HrhOuEQHmP^P!g4J zBgJ~2G+>zgz^;?SaxuQm42EDgOHDw5k}3%Dv4EHA0p8UpOutcgA2P6WhC3K zCqPIfkxwl)WV`{cmIqt%zLyj^*VhO_g!`R+oZLySs!c?v?s+Lae4l`PWYG`SSSvGM zKL~dCO~wx)7bBl!qre$#W@aYRi5OlIT!IBmCg7+y;-{|)r@HZHqj!|havOF=0dWZ> z|34zkZ-tPzz&I*utDe|H5!j+P$_NA+_po=B=gu9tAVyw3@{%j$?E9k53(7=*n>71~ z-)lPR-V?MilSqUuCgj63)QQ&UhTjuu$z^ZWr z85GDEQ};aNhVxldi;sVFFF*t~{celkx_y3XW19tB>uEsStzXuT%EEh)(CMhK*ocs2)v?-`Z!Q#Qk$}%W zlmG}+Bmlv0*frvl+cvdcr5HHn~S^t387c~7k7?w3Mu&r>kk6W}}z7{u>u5}DvI)2YRF zt?o=hSYLsZs!AqZ?wNI<8Z5lG$_S=`CyIU;sy7hKCW;KER}mPSzO_9#E9uS~pCQvb|?xy&F)ne&n6~Dm$h5QNYc(Cv4t_oG;~I0^Ozkk{cx!g~+jerW{U6^_~ow z%p3|-26Qm-(FFKd6ci5yV2SQ9wDCjG7;_-B`i(2mXC?dB3#X4RhQ1rVB15H>D|Y=i z6A1V|=NANX!N$}X?^Z-a-v_>qR)YeglWGUoszZ|SQLl4kkmvFh59Z+8Oc#5%x-deK zKCW(*E8#k@SVzDi`3NY(fgs5Fm=h1oQh)$xiktXTk6k4JNMZW8k3;qde!fX5L?_2R zUY0*|EqI#kyHkvprg@(q5q3xxcI$@?Jn-X>lf~=T@%M71g!eL?6x%s}iSx+u*FyX+ zd_FLhHhd{(n4u)A+e~Vy2zvtRYeBo$;_NwCMJsCBHRoKPkq)!r(|$(ke27&xRdF~w zLp1k8KN>K#1yLrSWuuGDYddy};$3zgE8`5wQY}l7eueT32QlBrb~hEHvFoqIq>vl$ zS-{mCgr~l=b{QasONlQlgU9AI0SfCBL$;ZVx4*5X^5vWQOV9JPP{_JwqgLR6395;v zY^8~XFSBUTJw+Qdoif39J-fOS(pA|IsjGU22>wm%u|i$SDtreXR*f;&Z(|%jjPL|f z-w{le2hYAYk-;HhG08?B74PJKUp-yUGa}D?f0N55?d6|HvoF6`dj57Oc;}$7as!M@ z^zmWBVCVRqP93@eC6fE1uVjuXbk&eHZZWFB7g3nEwYA8d4fS#DrU*2Pk!M6UdpP8rSxORttH6^c5JGZw#mq%BxIb>d2kO^5%j-0o>;&Mplc^_QpGW9VIkQ|7mNjE+5S1= z9A4c?Yr$}pq-4MEx92&eOf*NRkNPNSs{eMg;o1UTA&v)%B4#*oN~xl;gEmO>S=iB@ z=D=FC-h-XmK*S4bQq=MV9N1`D!Ja;WB-E)e6J2vX+BX!MLpPPJO6x1{6J*tDHOXQU z9pm6AMTnh*E|X3S>R$A`Q-;@BL`3T`%Qr;&ZD=gl$Gu=4OA!btdaRoC#ZZPfEM1x~l0c>v58m zjQ34PZ!+x5<9q~qRG{cC;&;WgK3||f!cY~{hYVC=VhmC)|BO#2%(8fVeV{Ssoh#=C zXon%cD|qWu=$o5g1mPNyHAQ>YJed(6?u3Aa!q~1ZidvvKS6n2CCbZO;xQ|`C+|r&9 zZ3xHw+bVQc#``7_(2RaXV>oDf;K!nVeP#be%!Ii!igOY|6@dfAR(@+avLO1|oNQwz zL2>{RBj(>lL!8a%Fvy&@+Rm?x6q!U@AE)X&;%RbSqWOxYV*X70DuMOfA(PoX z_MJ{u7Yb*z6#>^=7!Fu;K;GnCb~e05=KP(?hsm7gfTfLxyX>C3QyI*PEJmLC8ad2v zHa+Wabv4W3G#+$QQWg{|$`A*1vb?}2pi;*(VM?E_R&7^uK{@P{Yxs;M<@N)ZZ0oSK z)XR#d0lN1-v{W8@^jIh9RGw>Ci#lMG_MOD%?yN^ng=LZ^I?7&kzQsU zOcQ|Y**r7#UQGHc*%N>&I3sh$Vi!Jh`#VsygXkAI5)>l?DSLj6ysAuuhyBRh0xvaH z51fN=OUmAhY}5@IRh)7vBP6sa2RR&51e>nQqDQe+Tju@>1z`!QA`T3SMlPVLtYpM@ zq6GW%WkHa`E2D*ney+IkW{8ZVk|2riud^O0D&k8npzPxlP&58f!yNTjmi@lJTp0h* zT1fV>>bJm04?M5bm}tK z*weQbgw(Ug_}fQ9=^0HqmfDiRRM>ITYpBREp4W#uvLWycWS(jxR-O@eX~^ckN6*Av zo`8NSuHeO}-VO?DrJ>ie{tE;xFQ+cES?-AUNh#1Mb-vd(^$*Ah-)o$bV1?gKb;37L zTp(r{#n#Pp;G7;xQ=2~GiBP}VMc9kWV1sF9EsydZDxUKxrN;8p_wp0)FD>vj7VOOaImcn;$ry%f8K!w#O zD1ZFlG*2oTW+Wj6;4Nb(Z`W;_JG@|gG^`Ke=+v*{E`I?}&S3#srALw(_k5dKkZkQ& zbK`eeG{182sQ+LE$TJk@gHSu^Bg-Ghx1NBRLS~+|YZ&6sGRoWz2(03}E(IYWNr~uu zf?ajOdG3k{M@mPwRYghVc3KkmxB2NdZ2D4LQJYTyv%6lWS~tbLAAbzMOMqe_x{|e} z1V7;`mKmO@Bs!m;jq>*2;f5z89LB$6i%cl+@!zuS>vY7f3z0-3;gGYu90&=tlPq|D z0_yb|@KqbQ$QO;j*v@n4pM-Fd>pHBSA1X<_@}y|mRdhjEy%JPQfFu3w0LCmNq%wH| zZi`EMoBI? z0#yo-Z~%mSoAMa`My<7H5qnErZgqn)Qkp1A6gEfjOL6$A%6#4(WO9dIO=KEwDo6hF z`#*3Wm4xIU=d+d{B-mqp)Sm!;Am^^yX{sTgqauO4T13ZKDk7cfo{tNJh9`rZ zc}XXki?H*(_;&?>+(D*{Xl5KgxVkZ!uatsu&0DfV6@@zPpotH`Ci8r-0G-{pMztq= zlN`xxuS08c6eSn(D7Y!)J@Du+2i_AM(@dpb7mi5xF&mWjV0ca%>c-i_Ff1SgFG!+n z@5mn|fdJ`s8pvZoRs&<3n{TC5k)!ez@P`1ri^$-`^#rmrMnRX2{a)Zh4wMndNk*P{ zRR2fpNYUZYLAj+dd)%;bzt{cHckh?@LBD+^`aBzj{%+?F)8E|#CmD{6-l{&PJEDjU zC{T+dXjML-mvESk1Kv~?)*xO_7q(5GKy>tszvL<%SmaZd)crm#oA86YzTRGu2tH6t zn03ZE3*B8wbEYoiqos~nf=IoK>k%t!6NB(gHg>F^)$8BFRPH@%A_tdtEak9!v0v!M z>1@O#^1|jHJ&GiOohVg)y3y6CLoEtoHrj(c$_kcp)g`RnANKF-_p)I@0>;K^WmJdR zD7^aVa?N_jyi=bi_fh=%8)zwE#}{V>nbzTGtiPIlGQp9=`pxm5h;84{F9h_tXl@}1 zkK6y8FVb)AcM#FD02#)vJpt|K&N+RZIhd%5Sbl6)5$VWD$7Jzu-c*Eq*;Q=L zI@~f^xZ<5YQ9FK{jY^?6 z_ETrsR%D6%4(bM-V>l|6YklcwGGxt)nY+Pq*8!w=LY!l(IjJk*iHY;H4VjHB7Pdv0 z*HfyOi0MOhv6=YrV`mBIdWYqRUhGy$Vx(+NfVRbcR--Iz^1Y6-jHYW+f0$!;HZ@(u zlp*gO`dWG6@_PqP-g|n>D=&aI6R2w1-XMNG3g|@4m*-Yn;kb-n*@xqG)LZ^!InO0k z5VlrD9os=8T}dmqznbWS)}ITOU)yd*P(J~gRuA)wZ83N6PpHke66ET}>j2ZY-s_?v zY5|<-B%&+iw|7$@jc&VT@ZHMtbup4-F2XOMlE(pz=lC+)^)x&mz>dnkBbxE8o0 zeu3`C_FDgt@AtN*Q-i@psRPj#R6SfC6aAFSAw8?WZ(KI#9qk%x>iwdb^lX4sn@+77 z*Fl)KbGW0Q2TNWO}XBw7K`v(@{&wx*&9oH0a^% zOOu`9at#S9^_F*PuCUMdc^&*}>~cVFYO|)Lv7x$NsXD99%yP5ojzfSfJ;2LJsioS6 z`Ra(%;cCCiX{YUno4&P_+E3BaNWw2UL)~Xbv#(T56X(g2_)+ys9THsQMt?eRTFQB*EIep%NSc>OXiW0y|Q;vN2H~8Tgudt z%gYXr?Sw-u6TwHMn*6Z#VY0jfsbp3X>@4C62 z%B#qCwXYOAtv0xL>NyrIZ@=ISj5GzWy&G^+1|M_mu`ln{OUHrHLKE&TUvtwHdVYu)Z2cnym8_ZR!RRsEX2Jpq!0V_1C4PatAdA;p&(- zVQvp>o(N39eN=ElPNL^9UGa7d8jSFou9hcHC_6Y%|J2d5 z@zvd&9J@`x+TPw{w_gXS!OUByVGg3H6r6U@OPNc^X5lwbO-_;2An(r1-c;?LiIvom zPnF)FDF>)hk4zRg38N1ibPGJ%al`=w^ zdLvs1d}ChBLY3;bK}tw*@L68aveUICjb-So^6qqd2PhzAW(qP!@QhV(!k4O>F7DSj zRQz-!FsKi<%Hapauu}m=NYrO2kZv?==qlSB*NV8NMr#THT&1_>fQs^0|`}|NU@t`A7 z7p0Myyv@?}P2s-igxXnK@>%XMO~KC(JTQf1?*$Bjd?lUsb^a`zQ+}YYG!yxZ9uXBn zrqvQrXujRLlnTI*cRm_ufU+E5RP*oJ-Ic3_{p)?y5Rv_#&@f1JVD<8%_$uotYba<> zxK0R}4^0x4Pt|>#YI>N&_S4|mPFAw32%4vhh-?x>FuZSuf@NxhB)O-)nm_z+)WV(8 zoyzcQU5Ct83B4jLuy8K70V6^Tz~b27ln+Y;tb!myj6k-%=tWKdcyj_F&kmlCXjMJb zyC!ygCbTR0=v>Kg%jc-@A{*JStP9rVq$Fl6!Zg0e7~#?3mM=YI#7jeaaR>!`m@g@H z6l+VTeJuD<|Kvb{DhUE*5Ntz?08JP{8MEP_OvBef01q?^28q=TU~DafDyQ(7lO>`E zJj+JRvklpmlU~A}Z0ZbvnIjBbQf3fSCs{%d0g2G7;ib~NjUm^qp{ zfa`b%z!8{?LCfeTb0%mvegkqu_7sE19C3*9Ts;TlNMcDNK$MK<<0P0J1)Og+QYPR; zcRKQEOOO>8ClKBJ`4G}6nl5s{>L&_XVWRshY1;T%$$WdjKA8CQhq2LtH1cd31BJuT zJH__eg?K74(pmrX?MT7i08)V#_+HMwYqQeY?MDW1GXJdCV$D%^!>f%_z zSXhyikV8rUBbicP2e3t1y*!?Ws-p06C4dCOQ{;?k&!_TvA@ytZJID-Yg-^h6y}(b1 z&3AibM@b7fT1pE5K7g0j^$FlB#IYH}W>{(C;W?B1^JrJ-Idu9ml*

V)k~s&BwaX z^46zx3D!nlHPl8DB)J)P0=~|m^7Q+ji1dha{me%ij>q4A_%C}%KF^0gj)`DgPRIA9 zP14N$_STzW{q*rq(q!;!;Zz&y_qMbV)ry^xq!uynJYGTtt?$%+ul&{TZn)OR>M-|r z|9r2q9!}5yGE(?;GY@UuWFF-%j%6x>oOj25@O%39ypx8YT02yWX1CzhcLiMq7V{s` ztu0NhiKI6)hz2i>2Wih_vate&W`4g(Bv9$Gw8nuhGfuEr6um9Uod6J3%?Esim4Ac1 z(2`_mp&!8c%4|aKNGd|l#A!a;wKb+YbY+7Kj6ewIyS*}3=7|9>>{2#_v+}tqz=2yv zz&=#)s>`quG#xb!a_-;apKG6G;dK$j_+_2N_U?uM^iFentQaLfPZ9&|1??pv0q$qB znE640%*t5;VAvlWvGyEm`;l%FnxI>z!rHJPUiAm!{mbmNjDcAz&sqb;U-_@gd8X8t6` znLey3lSUX^7q-=n<~$U)8$1EsjBtiN0A%6gr;d622YJ;uN1MW_CGlbLiD@2V;P zUb`?C2}yvlKAC9^%d|MiOuZ6LtWNg)lE;#CtA4tHGD)Q!2VovUKd2AbgL7zBYeB@$ zf%?-&{_d-$9)3Bzb>8%_H~f&lbq3>JSmqKoM=|`R2?h-$50!65s93)nIm-t2NU zH1JUCEXFv>mOP-1u_vRbooT>WE5ywsho%cNvy%xM;*n z)yAeoS?%m)Pdi>@E@~MHt%O7o2)=wO!V|E+ZS5hoh)ZS$At#RGKC?BPW2fXS9*XwV zeql22JGG-*xvcorvI>=PMsrm)x+ciF<&Sbl&-uH|oU(*Qa3?3&f>qPJX}QSg94g?qc1=@DMr{yIEnP6Q_aMq%3M z5rsTr1`cM4z;>Qu`( z1~KD6Rh-|}a{ER_s0#ej`6ojC!S$h!hYbzk_f{YzJRO_ekF8Gk;OLruY#Eru59A|) zivEt@*R5AxY?foosL(!ksJ`Zd)AlEO&*Jo}WL z-G`w%KUVVwVS{-kk$2vjx#(J~K@p$L>zwiFdb=a=ry)uk+6rVKg!F#k}*Zl}xSd6|DJVSa7eglTaMXQ04Zy7@enlRHtADF(`5MmC+#mD}V)Kcxg@*r9SHFNX2 z=z+QH>SQE3nQ_RNn{J%IxLt_}q;m|`d^PRf-UC(z1~2hF##ydTVQgoNVb86}Olwt3 zjgnLGLf!}TyHZnlqel(pR2?RaW##$?Z*;&I(4;fWDfT_=n^ECqKL+QYVuV{nF8xcRW=p8FhLkCT1eHzD zQ!oiCRoEO(m<%lwIi{?M&w}X(jQ%KLoxI7LH)O6?V}}p~h_>7Qe`+86XoTcjZL9->vjR3uPY5>CAVYM;eg{lt98bURoCntl57f8z5@kB z6uy4poI)y!+Q14C91Bp(v@4e#MR4jfx6SkJ8DWdKU;GaZ_{DX!xa8>{D`rNxPa6}H zAqX33!RcA<%7`&vAnx1GRC)M>50eEPYsj?9_giQZ6o^#bbmX7D!!9bQRJknv!`GKX zmMJBh3@b5UP`fDp@0Q^(9SpeV=fg7)fLM%&5F+AN$foAJH-azjEm2VeeC=lPlupd>-yoQ+PP z=Eih1q9Rk&e>1YbD zr}B9|G^x77w*$KxUuy6N`}j|xfRofKKGx`>;#eYklW}kOG)JcRT$5WY%eY*6N9o5} zATQ3*@|*t{wqk7_frgo?D4FZ1qt1BvJwxu!oxbMds6k$kVaD(M{w*-MT{@w?7UH<7 zz&R`jQhc5G>GuF7&!R2zNhNB{-#Iq{S`b54HzLb-#N^gP% z+0DI9U-rGe>-Z~nk0r64Z=q$teYox0Z&a9RtIJ>spSFI`4!9?;Z*2n)m`ld?2iCeizMS41u#sJbo3n(3xdBxf&|eqW0p6r*S;1*`S0Vvi=t2}f)l=!C z7Fm~u-z~>36r1rGjmXf(c~pwYHNGlP|(%SW3J)%YS)m|xR(WB-{4#SbO zU~e=5zk4A@NsJ!~aB>Ec^*gT`aYZBBHF1@j64-Oawf$&7KIT=0Wh7>JRJc~C^|*id z3I2SKYEG$BZ~JpI?uA@d&G&iMP|${O0fgNs0#9D-bK&TY9S!-uC7bZn=gIKlpw{p& zOq55`7u>0It^Txic(F9(r-ZBif2?#x@4mm#O-#h@HYBh-Ki!fp*aT=H?3n6`FKzgCo() z0Q|@ARa8*xP$OXXj~sp&anvfav?e}v*%Thp<0-J}Ie~bStdRMJj_oM-tWWjx;nE(b z)}c^B=K>enOx5YmfS>!Q&dZ-I2vJM1@ny^}F@C8HP5owUSxiO~mIigY9)fWiBdBx- zP$3SaOv8wWA6U!FiQfr)?4?+_&^AVnHnKvQH%+#gMgYz5>{wlu*JfHIwvVaGiE&gV zB8F5j!WBW!1iVLPYAPI3qHpD*eJ_HSXC$H{BYe+_7r68;;TE;JBlfL1FwXfthel7P zQXVg9E3Wz;?vY{Vq5(RW z#c5TNcy$9rTrR20K7EpL_>$&s8WT}I9~o0v&j_Ng^JlTOqj)fB!Viu@$?4o!E*08r z_;VfY!c3%0)4S#2jjg2PY&#V5Er~mZM_cwNtPN9oXHdF)7LPrt@Q0BO?p zPlO-Wy+X8cA6rj84lSi^FAf-l1MzpsgXqoHt z+>tucWQ*xKRY2zJZ1_V*R0{O37L^pM+mq^{YiWtL^!BvP0gOolhna5}1ECr8Uk9~} z)7Fuyx0x{Or7yQ*cO*nC8=4#2IifG7-x@lBU*sh%6ALckhQzvIAJaGtj_V1ylpv`G zmC-a$k;v)4O*PT%yx$G}8I^15=0u~TJxYr5Qxdu1oDel`-PMb)5;~vv<43PYFQAj; zPMfKfJEcAsANuaySmq_`7xrWK{4^R=N-o;XH#1Gc#g%cFEag;5n#gdz{y{D?6FTCb z4I8HlbZxUIHfo|o6;oY4c&nZ${psALG&f&Fj|Fa3~#}Ukr&PLQ?2pQT?Ds)t4nE+Fxh#M}^c-8L`B&ud)L@@L zeEO8ufFc2?UyL^!c3c2)60ce<*Q&kze*8%LcydHmec;w%8Ge`b_kq&t zA8#Jv_hx@>wKn>E$@?Gt;^jq%g~?*Tr-dPoe!KTSM=93Ke_z_wbt?_=F(6~6Pf+^3 zr=ftPKPIjppO&tbx27id>F`lr46P1`pc(s4_@UY)U$?W?3%6@@q^8Kcc1p=N|d~{;jg~tM6VPhF*5mV|SyoXVrbo@`!*Dz$4I^ zlXr*WCmZY7VO%g&`sYK+jEgo2IX^>leG+P_ahxU|zic0S=otDNz74@?K2^JQuG_pr zr(J4?3H-n65@ENV>h1|-l&^(4z1I_Lk0ZR))1##fpTm<%SPlX1h_}x@FYn(efo#N_ zcp6x8G)PJg(8lS6eUO^a;{dd7Q!OXga43qg}5Fd#TW;XrIzKw+?N1G=iYT%dn zROTzxnKD9FjeG3-YHN$R~y*5qut&J)J}Ur>$}v7^liV$NkFC3}H;QCSpMIXm}6$_=crE0^0B zc*m5`B%JZ!4tTECE9Zv=W#9UTC`texKF5Kr;?4+Z$zhkg#8`s^_uEG@1CLh^qkW#X{emF9Se9|xpspVf7c$(*A{m;6T<)VCRbN$I zDrH1;BCZz35!LyHxLlMG$i}{E&y`EOvkgAR7OpWea@~7+P8xJCZuhT$Q!sm?>Qq-W zqvb5o=2_yZn8nG8=pn4NQyw*OLnd~Oh4;)VPI&!*2Z4O4i{*;5Ag$qqE4Lg)?*Bt0CXtY zCrKJRS$<^T)VQ;+&!hV|kxAS(l{;O##B-+{EM=l%SFFX6(bnT}|I6>Mr4Wa(-x~g} zv8ijn+KWfOGj70#Ybrs6D@duSSn%qRg$LPT)cZ$AZPeG2$6aqwxpBefFRuHn`;0tF zvf5EWgL{!v13b4+a!Sm?S-aDqOJ zRIs_z`D^xgC_K6r>H5C0UUy(qK~7#jF*U()_Lbk43u86a3PRmEg~2BvDA&U@rIF1l zjBd{dYF9_(tHnAw!$agD`IE*+aq$;wg;71-PvI%S4(|{$^OMT7+T(dI*_M&8)fLjE z&JK6v@12x?iM2gD4wY7S$;2rGy`3!iaT}4U7y@^%#;t}I-jDBTc;)UU>4x~#Lhh&q zh=QXdm+#v4CTmsJc|VPu;PR1fY-ZZ~THU0ISg)Y=5KVpU%4D@<3rQip;~&|9e{5$a ze8{Wi&AJnR#5sOh{mJ)G-SR4=@S)X9{lP5D{x(tX&#l?boU1`XIbkGZ|8c0;@+PP%ig&Nllqob z?~zuMsD$H-BAzc@@DQ^5+Fh4QtJV$MsU)MFjK9r0>85N@-K2@m8H zC7YB&o|A9)=^y399Ulb0=$%fE(*bL0CM)N~&v3eTM(c(tx@jgM+%KF9+pRyqDKxm58&`{J&Wf7aq*qya%> z3rxsHAxSOZWtR43#(Nc$HDI8H8cX z9(`Rbuwe`%+>{LI{O2U1P5&|D#?Ps+Vkd}8UX;60!;5IbvOqq$vcrW-S>=JN9hG?H z>UX>wiVuaF zDVO3iH}YR&v975*%P89KiDMgsS+Xp?z~99;@s96;arHhf?pWCSoREvm_0QAGYyvQN_N_0s8k0aC3QLeH= z>zLGB)gXh+b9$OcW}IeG6K$b8SU7bZePPjnzfIAqE@E!ee<=L98uS=-*KS4t@=}`G zoMB7jy(Fk<4(h?_M?-Rg{`#diQfALGDN~}G#WGGxUOw9)yM1UFK1O=o#T5a#e8wO5 z{PU)~@?roFy9x>ae%QV9CAr5oK}Hr9KnR%211VkEeN_7eK!%_Huh)B_uL^Bu>K8zCYYWRow@XpN}@OwTG5dR*AiO z4Ow0j!Xv$zw!DleQ$Z6NSFOOioco(3h)M;sw>fX@U=HpBNd1mvf}Li5aaji84XwM8 z(N|OoAE_N#Lm5_^Lc1DSddj_xgfK)vBkE@!I<;Pj5(xy!0|8)HqO^@kY@LQnd;&B( zw>tQZNG0fbjp#K60jKD`Bmoyyic3^UkyqqJaEr-q=mc^Oj$|6d$iDCcQdNd zRyY0LQ!#HoZEqmg{K^T7>%d`G#;N4M5iQTQKPLBiB1%_DarEbseGW;{B5w25)L+7` z564H-UAg+2N1$>B?BfjOpHmWzWSnYouTQ}!2ftM|6S^4O6fcv7`9|(|?{fF7B~m_r zxRbox#PM_~8xBB=qdMmuFkCd5K!7_`M_k4d*x>50p=4I8gfvxZinPP-mS-R@&?My z`bO=Pt#I9B#+%d2&W5x0o$JgwxNKq=U6eVa^v9~nA=lUHMh0`ITijXaIc^)avoWR! zypQuT2#)?OL+0?<5fO*|@=rJ0cyu|tH9A{X4V2?q_IXbc5w0RnQhz+gS*QT@n zc*U_RalYjGpcFC-qp0eVLJ39I82%>Y^NQFdDG6j zB0N=Z`%Xq1T5r$39e_RL3BA+Tc*we!;hkJ~#O*WlRTuv1QWEj-y6|U*=_vgPr*#^9 zSIOH|sgwF+71-lzsN{Ym=P&STZ2EHV{YEaxiWf|Lt+nn29=^d!|7U;b<8a1@36A4h zUKwJ0+r&d>MQTVVZRj>jZ6L~VEj%0{TOAX zr~tDZ?6G5ruUsW8HoX&bFHvBSvxEAbva$v~WSrVg$+^HlT5{z@TIG7y9Q+1P^7@;D zsZ+3DDQ5Ivy_t|ZCI5XV{USa3zY5v+{C|UN*1kp~Tev07M+G<6737z=qqy5{4mDYq zYSzcIHj__mbulm7_sd=giF7?;G`TP9!@KiX5+G{p_e=;vg~Esl@wx{snWJxSGTg0B zD@TuXW*+NBNOB&+y$!wAmi&Iaqofc-v?=~0VcK$1mPNYWc8U;_`Q#Qcup75qegb~ix8Y2!o-vQf=mkhRE2wRlUf>2fC%yA4W0<%na#u+9J8 zpa1WBXOG?3wO!lJ^SoZ?>v$f=m4=i=M~CyoYsu(Vvh(#($Mnlb`|846Z{)CkO=&Ty zOQKuP`-u76!LmxleN)6LE_qzt8 zjc{2W8X;hI5IY7vd-K9keaIkcL$G@>3^&Z9FhnmSAgk@--Tt_VJ**F$*T#);M+iq~ zYz(!!zi(-(pFSCh%SlhpOA7}!)-2XYS#npB`2f3u=QwK%Y{pl*NKn1{gZy!#%N{#n zFW-B+Ip!du(e<$!TnQ$15q9m(ll!vzpEf*E4bICu~k zKe-B+OEN?PV{1luRbd9x0l?pT>APXMbB-P=Trnm_wRPMvEEaU4V#C~IL#AXTpdURbBQjQ#a3o{acx>!ktF2KqKkWvNB-*HPR(t;i8uEL_z4dH%{R}QKCAn^zx7pQ%2P^hpB&4V zkoMyDS;}W|l7r=EINMb_&VPW(LTBEbB+R657QsO1ebI%D`d@Y4NYH ze~Ha3wL9d{QU~e+zwc$`PFBX0$z%q)YjGcUl?Bp@6S;gJ^#u?9Yz=h9=+cVea<8Yq ziY8^26A)ONvWc~%qsiZY{&a-Dd0W^`Ckp!c_tq=kPYc)Hg=y7?w_kU@$fA*V)lAgT zvLT|CK7vjDdJvaWP~d33bn)v>{r}Gbi2jdU6hi&A)%~8yJ}o}=sBk4KYnteHhwdvX zkMooFUy*^WO}fB3Cn;{EtjDipxm^|y=36gly@we-uB-o4A6ZrnkTOlF@JizVAt zG|D#|C@}u|Tq%c|igN6!qj|$E`SLj*M*FXt%+C5c-5s**JkMo{&wyu7H!|<)3$!D} zW`F#a8a$Pm#IAL^tiG-MKp7fOA_!J_=p zsduJY^OS3(mDZ4FMoQvroBY$9N(`J+{WRW$u~B%&!iB#ZJFP3IZecO3Jh&Bzm@ON* z?_w-cZ}p9|cXmryo-ZZ;Oy-G54rjM})Hq4awBUx1Vu_W+l99OqJEwABFx1t*A|2b z)&A3qNZFz_9J8+t>;@=r&(q-cvfdG>kY-yJGImx#dHF$#Df`scjOWuMNAV?he6qi< zhv36{vTW|qtcxKZ@6GrSIc+y|6ELzSP~B%*_KkT^b$|9(K(ds4vlUzzy50b0ZFz+( zM$1f`pOEg)1u>!Y<3W%22ya>&3qn|B1M18R2LyP5{N)QwWC`KY>~ovEhYTn&bQC5Y z^{MMMYOEJ}4->CE(E|3}yzvkG#HL;Na?!!mUx4XZ4_nAOAYkNbv7t{IfFGN)Hy2=F zE0!DtTu7IXmB)ifaG7l&tXfM0CKWZeks6+jTnq0D7YCAHPC8j5zSf+1l=K=6I0*`A zNp;~59UsRZ7xznOaQIC1HWfrO`s3`>p6u5}=S9p3jf%<=40-$fvA{P|0m4rMA9FW6 zt~&Y3&C8ppA$>i$6YnArAc@O_e_Eq5%ufRM`~xg>8Ky~mJye?pS3Ad+m;6jJzZ-o& z`eEzIkYn z8Dg5dL61<@T|W57pfvOQSscjL*%mz8#8$fXcQKRE!he7#cYgFA+8&MSP{QFegIMhy-JeYMKZUdw+G*+@k zkYK>;&S6>$d<(WHAEsWz_$YBTolQk+#(K@dx_J_)OMTi7`_a4@O0m{4fA4IMlG}C% zJp4C0bd2CW&FdA#BoAtR4`MRk8(~5R;DXIv=n?T9!VHRRc%H?00-j+_%Vf*UvR9)z z+Zsn34n(T`tyTVF%8$zcS0#$jaYIQ1ygmny-{M(^#s&}ze@WZ;Sh%RI`X}^^hWX}N zKc}EG)>++nU;os$c)55BI2d+EFcDZ&gdIBpjnrZM30H%GX_(f;28#CZ=(k-)#8ZOd zj`MGJhrA09j*r6`ZH$X_x?p1w1W91YCeCmCJ<=S_Fz%bJzIjx?KFW9h@;XRLKZ7g` ztRQoxe=u2)%^L+T%LaA5PY{6 zzDcM-DcsdB<=A?F)f!m(CH&)b2$mOI&6xT}WC+?_-^2RrIsE+KgW=_2@(tzuUd*-b z<>5f7J>vsoW4mkhgiQ`rtwzP0&kK)~qZDZg5G;Xb^hT8ZEI2R>Purw+Ue^c@V*h)u zkJ}FfTQ85267Pn%CIjR^x+=CKQ}?)54-U0^QlQTn|yV}0cjsl2+WYE#Dn z3Ll%RCxv*Y1TIu8svG;VA`x!!PnAu(vwX{(Urn}{Z)(Jv(qnXU_S0|K2R)uG@l>37 zg#4M@TbVa+WXkbMtMx`_k3US+-}>eIA|4%}NYsZmddDW+wNhneWUx7`gerQJMQ+NHq8bQt zoBy8O?Mvu)r%aTHHpzv&+U{=#`|*95eG<<-TZmc;A1di~2EPT&8kO_ea;bc3Np$^; z`jyr1Z(1s|#_Y#p|Dq*rxhe^x{`+Lyr}D58AuczN8! zXmP;xR-ED4CB=%2)n_*Jhso!6UvsC^rtEJLwG5IG>^u|U3bO~)S$STS^|x5uqVJuL znBMEReAOr}8=1-@{R}m-mNZ#3ynRficsz4N@Sj7tpOBNy6OhbXygl2~{q38}Jxq(b z@#dKE&FvTdXbWn5(S%%tCxH{zS%b&?*lr4!(%D?FgjDxqf7N`UvbxS6~Xj8+*c8`Ad`em5hm>@DPG>DG*lO_zEYx*xq1>`SY;=;-;_i>yzj z&oO?@4%qi0@h)95l8QiouP|MBBmJ3q_RzU+N}On{uE@FM?xz`e?VJih#7j(5I51NyP>YE;KjNWC1L>)o=$w<_WGC3m5`ASSRKT)v zTyZc9rd=sa$Q;hSOYit@Y&Q99XHQcGC$J);_ZFwgQMZ)`-Uu_jP+S11!DR= z=_Y~F*=O`iOz?H~PUEe2uebgaHI`xG?|hW>5&nrF&404V-SVH)@-^;aQ8%03B6=0xKnn8!brjmdF@c zt3s-znDQg(n}@QxajwdaWsj4FwLpED$r{aCt=nyK-(I^4vo(h*+}n?;9I|y}4;L+C znf7#DOww&Rbv|Mtiki4fZUzh-3%aeG`o1_K@t*9{e*mTA(+^plm5cySy%|%zrdG&> zpS>&RZGcC-fE%rdzFosIk(30C`!ld$LnG0acSSh0qH(pK>|WAz5C^}I{>LQ^D&LOX z`$X-!+Z#I2D!z0onAwPpVk02y$1l=2WzHI%Fc+P;wETt+wA?t!^#3&-wf-+Y@BJ-J z)&Iit{!6`3p#R@aQ+=_o{y?$!KYL^i;r0JDCW-bBTWL8X60}R&GoLM;EdH5LNY`*X z`2kzK@B0&=!7F2Ko?}JlTc*fibz!#u&~UEgYCKO$RXts6@?9vm58b`2TvB z5L2CeNMDE}zjddokKu+cV>;Y4H(|sFe5Bpv90GcrC|~4#AFXAm@+jm%#!=k?TaW`; zgB8b~sukImbwv12PXw5rJ3Tyyb+0Y+7ntZzIKX4pxMYcm|5Q1t?nmDU?8Ya`9OIx#5xG(F63NGxg>py-f?FlNJ@C1G} z^u%ZX1KerL_Ri;{qR%s~{(>c!nBOZvhfg!JIdk}YjfSOJ#1YM{4VIm4#C;bmEz5Cl z+tF;>d^JFV9`S`8S>I?a;73d;kehp6g02W4+kx{h9~)eX?B5L^GqExL-V+yx^JjQ+ZSQtJ8*#imOzX3y!{X<+#4A&gb?&q zmXkyWlM#q5a4>v58_IYjapMnX#dHqg@9iP$Rh^MLliHs|MU}(1`rWhgn!R`6HbInF zBcyk)21z`fkJG;FY;{|b^31KG(4j1b*!n96k|=J2d+nA0vUaNuiCT*3;<^&}@NT)5 zhojHx?yhjWID`WpdrpKPSg&=S>v^O0+#%R8x_-3kGwQe(L2cTN$m12`|Ntc{SZLE^v%o=nFEc#-m;sB=VF(1f7zXSkGMTa>!P&dhsB3WE+d>V6!L!KCn(IP#!A{BsF1EbW*L~_mMhi z><~IRmwD0#z)WsEZJfI(^7dSD=LMH?!>h+48JMAtc2NdCxSM!qRC(_RCHgmJm$T4Q zO=;7*hb`EuLisSEg@s3EZQ|1c{2x z$Jr0{^}H!FEhtKDvpCuE(TJHOq^jho@Bb?8EEt*QSm8e#!c(y2o7e$qg{^=x3jvx9 zMgzC7`#XbN^!!lrGZJXHk{^y7^Cf4k4|I<&XgS)eDLgl+=E=&`MR_XJ9zwc;S=w;! zmX(*7)wV@>QFeJ(R8?u%-!~J>r?NRq%4s43=qokmkp2&#fRW%A{M4l}SCYtQKW$hzV@DnG^XWev)rl{<%(hs5o;(^zaH>xg2RC?e zj4Be+KZHTTKAfHVMzUk{HWelcc;jzF0gNB|r`n{-uqjg1~7kZ3CpDRBU%scipt62N6b6INd0d@gz*!w&`IL4%EB#03@;1kQhY~7tCJY#&wMu$vm zO@s86S(_C$*?z0nzF6T-y1s+wnFI3y8JLm86vp$Al)Yxw*eW~TR(eU*S zG=`H5V6OKD6w-@D`~y6ka7IP6Ba(`X`fyT^qO2u*td!bPW5^52J#1JAVDX{wLXooHlb;YNpT=M#_vool9=b`<1T}h zGIhYx6XVR7j}~(Up>UFqTNWQt5E%Y068+P6Gmzf|-*>v;+E^Le?p@A?OTj<&nd^eF zxA?A${aHPL(0Dp?s+!{xibtKm8}}L;TpVT1ONFJw1I>!%h{~O{L3ZrKKe2MVvl+&^XL>_d~*zoVLwxha(5; zI9iS;O~<4Gp@@_MTF=BXtr zyt-hS&GDtI0r!W8Ay3Ix3|Op%l(-+oiP|G*Bd^snd^g8PFcF8(8C5tlZ1X5p1;PGm z!GP6azoeMm1LKQ>8%kUMWadU$u8X)EbOMs&b47xBkv9Xu7?)Ohj<(SlEbVpCppvBs zBOnDD#C*x862rt30g@hl=XO_C{{SjIZQ+{gBYZ0_QJXS|&AH3PUT_Mf)0vuk_!Rvb@|CM^43*)PjxcJFp`36m; zfFT4O-dJD^F;TL$#bs|?9c`p-aeov!?>jJs=V4M6XPizP#YeQ(-ai+Ow0fqR8k3N` z`cq%NdJmHN>J@%`rbYY@^MG?vgt73+BQ8vn1<((HeN*HU+6k;PLFaC)C|-9Sd6<9@ z`t=4YH7kBA+jr1}`eJc-i2h50R~6$YT8UbjDCM+C7k%r49RU>Px{JZ@-sQJe&T#ZHMh~zmp8Y5F06B2EL!OKa&hzb8d*~&Wa>C`zwwEz zB;ID;MHVfT5e-CAosYiwP1rN&>hrRN6Eq0_W=iQJ$466!>-&<__ylL%MAXWA!3QSN zEoTDeJXE*3*Yy}G6w`I9?1Kv(R(Uz-<3ei1iz$z^tXiP8DOGMlLbS4xzi7An@HC_- zggy8^)Cv}gzNAGv(srd6bO+k?dHr2Dv8=D2+TyCzt#9STTL$D32G;l#39N==m1YYP zCbPg*Xx!d)^KPW-EhuPvgt=EzF-lBh`tB?*bmR_!$RtZ)xCYTf{`$ z?ORdm#mpow6gw>k==V`#k}=LYR6}$MeK#wO*n`C&DeT)?%nRg@9xAcXL~nM7Qjqbs zl>OH{fjhh7L|1b~EGmjPKs5e70mV+eF$6*93m@Y$38_Bd#b-e%73XED`dN4uKYTF) zJ&>d~Q+7yjC|l<*+i9y>3xBO$(OTt>Y2;@uO`d5AV_8SYovHFe;5V{LvdbSzB0sq92&9jCI8=M(=uL$#TGH>>7q+uztp)UZaf8&68m z76dn!l`UeeEuKDHj<9DKrR6C8lJp9>-J4giAALJ1Fw?c|{*wq4!#P>6iL}$=`qL*C z=}N@Ba+MON`DyH_&(nVv{8+VYK2-N*pY4>1zjt+Nq_Qhf#qeo+*yi^B1v8dE(d5(i z;nu13nWh^dpM>f8?vlhOL|6LnI=-f41TIbSQ%W!zs}32F*b!f{!|<>G zBZLxv#gCHE(D|dSAkT~PzOm>gUB+Gn39&Y7)WJhU)xICKTK(pMTvcH$9 zFx%=$tXYvylr)z~WJZb+`O&Av8&T3uMRkLwxkGC#{TLdKsy`yK-=rlC&_=#91)%g2 z3SN2VEp(Nv+UptiwC!n@32rxf1+Y_lv|Qx6 zdck9R5U^eT#i5hgjmkR0)p7o^ygW$A7G#wzuBgA%kV&5aD-B33HtMjO>NfdGopR+K zwU2%~_bfcov>@fLpMODjd^kUm4<4fvI zQ!OIa$f*v+jqd$1ce+)3`fk_I8i`D{h6g2GnW(GXf)-nZGtuG4JE*{5W6vG0@I&8&d5sNscf|cZ> zx+=dl=Y^@_#5QxiK^L@UeneC}PVT7Qo5Neog5tL4a;e|wCB^TWrT!ZkWo1Zj*=jEu zJuwhW-cBDWg_SDmd{NI-yfX?#j15UW{VRs|dtW(1K718LC-x+DXDpA%b9uP4?DDxx!L$N+T>)Ll;?o-ocCbqAdeR&_giGCQ6=IZxtkMW~I>2Xp9$P6naDu>VY z5+XI4j&-Bf6_ET(fq$mFi7@w*OipeT;ucCBiO4LBcfKB(irE#*8h7^{Kj^qW|6mOr zd&#qSD@Z3Pad(`8^xg}4U;Q=bv)mVFdzVV0gR<-BQZ9R^d*z^BM-PHq!@vXntk!8c z&|XG1!}HOqRCa1jl1ld<`C>(uqg;?N-I%R&%!oNO$J15bn@B3t*oQd2l3qdfa z*e|EU<&GHj=Q%c8%No#D5Z=Yx+JzW<3=GIus_+eZ2b^_c7Zz=M;NAu)$LjIJ` zxALq|=LHLvCA>IM#7-B@$&){y-R=|c9}`e`Q%bIV5!4!L33v#3)%Xmk#DCxh<4(~6%B;Fi$;wbrsd&%7xsNvw%uxZ^ymM@Ov6i%&oJGv8#(sG_@5;z; zLz}baZ){{^on_5)hr)nfvs3WKyBj;-DuKhwr4x|h_YPsHlM@ZNqh!B2mPx-(T%j}0fjbb5ca!rrN8)e$5Pc3E${|l|B5sjeM_*CqaTb~KQ<8S zQ!KGDwfB#PeIMd_O8F7KpDIOY@YQpR;xd&y5?+o<($nu~1OVSEm{Pi>pvd2Sc61*e z!P(qmKK}=(e|1aFow9%X%p!alJN0qbRoWL>NGf}K*+O#Te^89v zy!oy9hCM=Ovess6h0W;cQ;{)6hDWAvIJzfIyC+wN!ajBlaeE1-1BwMi+vmJRmNI_) z>Kv{HF01UT%giiUr)+R~h1dw1M|kjC$rawu>b?-){`RCn)yihaIjwYagT+5l!!X6D zRNgV|sLV-t!kp6IBJ!h17DoOrF-yxEyX!JoURze9UF|PNq~sE+Gj* z!s%Ercgjr0jG*mEL!nMBmh!ggUnchN8RTUpe&ctQt#$~_-n>wE;X ze(*N!_>HZJ(U7$@L%MNa(Y$h-g(cYAE4SPb&|lwNS*`rBb*fAV)F<*y?e21MGgo2B zmXSnr+jPExV~{x&4Z`Lsf+0I^$?lfmTYHAYokg8Za*(%L%OvjC{(IxSdM|;y-8{50 z_bq=>ohNQmznmSSc+^mD`?^X<&)9wTcVjCPBXaq1j8TV31s*Ro!sPcQb;7oeeyPuq zBXh_pJ(zi(Elv$GeV&~&JgfT0V7dE;WdgHkY?rq<(bg~X&wQsbeDQYqp#t)arFX(z z*8uN{T@wj@thjEEB4)Gi*Xi~#B9}X#*$D2g|CfZ3L%6rY@4=AlA3})WBn3)!jTZjy zHp!p~I0@8RjR>oX3f-iMU&jdqR0P&`v`(`F3}uZ1mv%gt8$Wb#xm=VFftjHlo=~e5 zHtmK=q;r>WOq*PN1WvD*=Bw>S27j4`Na^wr&nhW%A(@16(jm{}GOh>k(M85jYeUKG zN`D=U1y^tEfFKLao4+_h?fn>`=YdL0Sf-3l?O`q2h15-f$Y(n7^m~HR*Eu0%JGSDR z<&S@vc!Psj!QFn|`Cqtl5C^6rH{gJPNjwNctAf&DWpBGbE$r}c<}q>wH|^~gTiQAp z9uoc2sq)OA{?NYO|%-QF#mgq`)p*t<-BeI^7X5_BIEm~DrDib|<2 z@Nw@-=g3{POJ6PbXN2X?=a{EiCVYP)-*jHyGZqCw8qfC`xiR?~y!(?CReSGmprS)6@6V1uS=lQu{ZU`qE z^SAi0o~%Y zgpBdz5e_!RwYJD^s(E)c;ZnO+c#VZMVrWl1vV1cX!xA7^Y%2yCpvlOke&owjZ?pB4YH2ydDBnGXRZHznUCo`2 z=OrUAgp)T-UVL}dn|{p9L1R&Fj}#nd%}Qd6**X8n35}sREwxu;%;KG1UnK4*TUPj6 z+VIdI3IUEVJcpARRiGF{DMCK16!FR6P^QEyS;=Zode>(A_6g7gFQ?P*&3D8uzGQK= zr;#{6n zi2hJ?UbA{9Wlb34&d$iGi>mmO^{o|qQol78Y}CPdH@R~jW3fax4^poTfq$2{)Ht+% zp1lsei^)~2s+toNr=|NK(wv2R``0TyujtL^k{?&xP4!kZ^Id^q>SS*%z|oU_G4RC$4Pmj|bATC62>BYEh6|xL$D@vF1#FT42 zy;O1rH%)=UFdtM`AdS*5JnmQi1!yK1lO0w6f?(hqK@oX>4XGAa@EM2^S%bvM#TPpy zAumTB_OCw~)wt393#K3-N|p!P^ZXeL6@7(d0M=6=3r4>y3xvuqa@~}Mysw*Jvr1=( z3h8YtE7g4&qZM~Bm5rE!Kzd(BbQRA*PeJ5ONJ^!ms%4C}UKso@bGpg!@1T&@=5_Cg z6S;ecH7ZQiT$iNb>*r08YB+#px3=q}xBMMgzIj!O0+FRggWuWNYcEYTnk%KqWGriGvzm8B(|nKQu(Ez`L(0 zFt^{P_V^2}AvJylNf`Hg2!d?MhYf36){~|#i^t9i54XP5$o5}Nw3B6Dk@BZu7D~DC zbc6RAKSg;0&Jy_aV)IH8-{SH}1_4bszKbv`zrAMYR05!^@M@buk8GO8ytJ9p` z2DE;-^^8A(K>e|`L#gH1P_o^ee6I*HK@I3(4eI&tk^%}rc=cB<{8jlYOc*Qd9>x}b znHr=(*5(RHgCXCq-QAb*o5!ddoO^}3{+6%JLv0skWDe4I*GrZu0apY@R-SP!Wb z?l7f+JU8VWKaaLJ-H6r@`JhND)d2v`!l?qpZdhIjN8lM(?KuTzgBbQWS&^BG@v+&+ zFQtx5k$6p9x}dHy(EjZ6p2=>H^8)dDAYtP;hpIQ6l6!+P?`RW5Lb_VDdpH?kJ+S+9 zMmIMH_9{-=UTF;7iM_*hBavH_Ki5NC6wuG+eLvCHl%$Sb$n9U?!fIN_=A&V(HqL^L z@p@DJW4Ap8h;_?A5B??yblqrcuxXIpD7!+s!ejkQR+O9|-FQ*veT}b9{{Wb6gA@)! z11EA6IEIBBFHC2W430=M`UkKwzt%t!mUMR<^ad7>CBA`z>BS9n4FmlZ*`Q%%=8>?Q zb-iR*+_~Cohx#nG5-3CIF#(zGi!9%WQQ zjV$3=G%_gG{pLk|r-}JHOfZT|FCNlDZS95{i4=Yt865V*I%Qdk;i{*|&Q#b$693k^ zhqi0eI+7N@GN*(#@nl@$I)JYH$MTQ&9hnqB?SdwQC<$H!dVk;h7afd&P{S<{qmeI| z{UUPMXR(w8Q3!~-f}$a?}*X4Rfa&4Gec_zejeS?m4__UiPB2hP(syjmZk%NU?U z!IPCjpBDen$9B73lo}Ozs}r?%94%%DJkISWyQX>L%0b=S`p(^9wDDmh=togbEf*n$ zYze4gS7E^w1Iq_rpNHs?_|Z(WJ+)aB75=n%XE!)bzS`FYhmq1J7@|pZ>Ef zHs7{Q2*1$Q3Qy{b+1LvaUtK)4V`$jqjBqcl1l(X{7R=O0T88IOHC%0IVp z6Bba#<{MSp^zTB~&XJz7927V+SN0vYqnDIMVM=|2hSJN{(@{frGdw2!;WO+rKa;HY z*@BjU)ep768~y>$+SzF_YL0};DAz6;zevbYEAXpRGj*vKf~$kM-5Zc<{+j*9IeAC*c*2ly@HyeIc7pWb ziEydHN98x7)wh8hZA@F4RG8T*;Pvw#u)4m(fltE!05u>P?6WO1F@%vi_*4+e!M_2d z86*{N=E~ZpvGYXg1p^=T_KMBnboJ511j=LWig1hr5Q5(&G>8HCHuy$8)H0PVq7M?* zAQuu~X`_LUEAsdUSRz9^&R(#oNh)KekZYPvO@SecV?AhhldK=7o2#l>epLFWG;+MZ z*@>L(k0J>w9<2|w$B?Y29IzJf%%T#LXIr+?vtd~?DOfvjl>e1;QR(?vuHt%0j6ypX z;LK2a;IZ0@-ao(q^v3M}rs4G-WRZ3q@xhKS0J@=x%bb@j`$Yw+?bwIbt{oyanunA< z*J9Ra#Pgdvl&0l$?LQK=OI;1diOSCHN_LfV;#X6_gtFR!1q%U{OU9kY3U}#4$!mo% zx_)}Fz~8N-m5=NGpvRR+g_P@UhDh}&?%$Oz?*lL9&_)|xb^~eb*J|#pR6-h7c@gT=6; zB0{SnJgDj?Y>OVPpTBJ z5%N1|K8qBwE@{wApG}h?=(p2{!a7e;GTn`+v-ruTV&6PQzwoN#yQHTdBiXq>yJ|jx z=#ah2dBv*YT$BT>H?f0%R8Z7=Mk5wCUoL}^qP(&8$?VUL@?l)kl3wSif}ajx4~pZp zX5_$xnq=Z#C5k4$>NC8<$q773TiN%@n73D&O$k?kg#^V6xeB+-4s|D})BGL0Z+1R_ z-RCaVV#L=;yHYH|Ud3acKo6toenI2$Bo6^VP-(D%VFdQRBpPhe6pXn-;zCfN#pM#% zD4TT0m}@=QLp|&7H8C38$H^*V2PWK$rfId84?J09mHQ>o&xV{yuC57aLx``$|I|;| ztW3}vtg5%H(;pn$Mw}v@U>+qt$EEPa(*b52C(>gGu9rM4Dxh18?^}y_n&kz%+n0=% zxOzyyC0--RV%xZa#=y4&)NURIuryBuKzy0PY9W!)g?3=%_jg=%(DRx4yCkb86h#{1 z0Baza{R(;%h$8FEdZ-Z%p%yP+$lZ|ax`9#!yh~NAz(i~u3`LLKvrE`>A7K6JxboVr zn!RkQ1(=@iL#{ZRjDM}&)0*SsFHGZa!1Gw~CR`4Pnz!dg z&I0yXXx}qvr@eQnDnnVO;5)abuk3}3EIH&^zTaH?BJ^=lJAZA<%+#33oQv$Wy2@Ab^ zUcKVu-*NP(`Y)cnenQ;-YuVz5^wr+iy7mQ;Mo+!knG@ycO&%9?Lg%|SYj>KhH=slT zJQ-bHUX>cpn~}u?4VD|Fp5)v(b0U1GHNpBMV$hv{E->WzH_otu>L$70yL)^^H zEKw>k38##{{~sGdZqamry?5e9i$t#K_AcJHC?32!+pluflW^aqWK@uaS+d24^7V5rMK9Xkm*%UOdZxe-ZNE} zmC!n~a{@IGFWriF^Vl0rY^?)rUHtU3_e;sA4_rtVW9(i?$@Sk3l)q|4bSBoM%LFcl z?dX_P*75Eba0|c_{?xnFXc8cqw~23~6g6anz9)9EeXgsn>XtH36np!zE`;|fS4)rR z%2|R!d^X%75nA8kbTr&hBjh@LiLX6em4WpJiD4Qyz_&4Cop5TbKQ1h11ygN=gm<5? zzgdqZ#kLeVe`MU=NH$1Ow)&K(LDg1EFmhCL38e|g)ru|%2oi3RB)5B7E`@0=jE2$e zUk^Sv*|^KUD^H_9*cHaSJ_;>T5wvvf{09(4BHKiN>Yc~_1F!+J)0IN-lBnOn1u?YB zIdB2YD2{^=*JA?=^?#aT^n3MSHB1p$O+W6oLd<&TMZ=LY4& z6nCG&>i0#8SS%NRBMEt@H)NYTzp9rR$0RlFklud){B*w!jeJ?G})nJc?`6 zI--TXh{F(lJxTb*^x{U9>Js-MPcKE!xutrgI(Fb9`LT&7UEX7jVY@L7L?pXT3rBtD z5@#A%2L8^%pl29YPwJ;H0!iItT$GmBx8i#n_iiwMe4smRt))&84$Inpur~V}Tl^qv zRZ28E7Ncg};7n(VInkh3$?AC*^#aQ;6*Ld7=KGm|9|w|eT@i$%s5SK`{{UAakUlL8 z?dwIh8)0>h)1fokQaKF05|=aDF_^4kA8L5bkjn3j;q<87<7tEfF=S{7rX%Q$SQnqf zTAy&3o!IGbPQHr8H7(xa`hS2r-orIl*2k%Rv|;a`w)dj~;|TMi{{ri03#ASKnF)C~ z3I>l22o`!d_c0hk!dE$bA%o-MH(sW0vk3Fe_`~frq?F|kaXj$9;x=v`KMf;tNrd+S zzno?h4+4>CdmH1|1i7oflrny?VEqB7F`OMl|Mp}s2_Y|^90Z4#BVK|dWZ2)Nc~CNa zLn3S_a;IsMVczQ;p20o)#X zgT+3B?R_1Hcu><1sO{RqHTs3WFUor3Q}fG;NbwU^+lnPX=B>)KFwlfMD4V)9Z1c{`XE8~C{I?dgfG4ik+%HrJCvls)meBe;#BHs3)< z{IA5GdWbi0!HB}QA#T2z=&1k_nWiZFiMbvw)A%xT6_(0Q`HdB{ zUVguaAbrlf(9hg)UcN=S4mnCg?V`P=OI`;(nZ`fz;hEHA%-#UshYa|Nzo$*bQEUv@ z48}#ewNRPEFX)lP2v;|TyqbLQ;hX~O+1HwEIKv&p*Ps zrZ3l^#=cm&qcs?Pw6%nMjhycqsSh1>ok2S82NBn5BtP_-!^ISwN_-NIK;OlV5BbvX zO2=&@@UK~~nYV>hK+rBc`EHA!`ZD~#CJMR^rqNBx2F9q;}06H^1mllGa?-wLa$0_Z+}1Um6=gZVu&6zYsxy_@z8Cc z;6I(kfdwDJf<;oP5$OLPO@Jqt{^a& zX#TTr2hv&gVX=7kMv`C-A{$|Ifd}UtwMZ1+{{L7y%c!=xE?PsOKxu&j#U*XAQmnWW zD8-8vcXxMBaCd8q7m7Q@wP^4ZcXua92oUn#eD~ge`ExSP80Vb5*IsMRXLc&3Ie1Wq z!dv_5cWRyOCmR18+c#$sCf6Gm{B4!K9yzpwcw$=z6nynr>1T7Y$l;X3eHO_y7fvCe zYc{ERT_`j6e$;{3(Mpsqx_4NJAFCu!vtd|gk-n*w4Bo&VC;Cc|S@U25UVf&=ixVSL zrv*vv|A|{x0lT-SD)8|9jZU>UmycVoepa9EP=x`qN{6*1h6cYwg8?_bbvyXA+|QeV zEPb!%BkmC^On%lSjwV>sCJHI;@FOiLLduev1wrotG_gcWocoE5d4Gt1wzJhTizCJF`fHfLDG}qRqpbBu z4c@L!Ub_dk%uigu!<}1Lo~HiIWC=T(W?{PRzbIM@?Y7iNQWFW0q`Kx`FSQ`g%ADd) zCw;0AZF=V%Dg2hYskGn4j_%6v$i>skmE>gzOSTXFx)9kO_wDCy!?Ix%4 zMlX$rxem=amf2Isv$Oq{PU`_|i34n};Q~Bo)A}~Qt<3q)naQU*t)e!c#Ve&xTkb@} z1c{X$_=r(Q?-C_ja{LpUa(47k^F7U}&wE-4_9n=I(}WUm?wbngiG;A#qv<1Jdw-)@ z7N=A9wksuzyboB$b6huwb1shEJm$z(6U2_?Yno;}6R#GMjU&7VJU&ARuDu3T8dCF3 zTQhgFr=`D2sb9s%XBi}L$p-O^IqEpTq)t>u*C=6y-mm&LyX+n!y?P-z- zd1OH1!f*$wWykGN@6m^tSdYKxh|Ik;hvlw$^5u02Jd9+$-M7(GbaifF@XzJe_#$bs zC|lrW2Z+0?4bk){h~%>?rnV}L;J={l%Bp{DXh>73EFf&;Pm;pFsj=89UOu=~@)sEl zgC=ydApKyoJ)|gJ-x?PR-#>a8zh5#?1&aUr3t_b>{^HvrgZ)fy9m4cO+t z`zaU6YK1P4WAz1c%Oss0tItY$+QMmZ-bzkA^zX{xhN0UIcEwD zqGp_>4fTaFx!yT5#w0PkA_8sd(Az1`^^U%2v3~7LAeuiV*b9t~`-PN3fQxNkFy)@X ze>rXGRy7b*BS{>?zo=Q92Uii%hMW_f?5!43GA6?sb+&y@Sz&Q-i!NARB}{OrhrILo z)=56W5fhSo>w*dqIn)18o&KHuTR?N-)*N0elW9%qg^*dO(39q6&(MDuVPJC4{5L)Q zfEZ&cSf@YT-?-h+YXCQ+4gS!9+gPR>1>c~AN&<+3?N zE6Ai>RrtYEm6+0_QJ_9dBB|8jdviV}iUyH-(YH=`nc9)dHb5c3%SS<-J1a+T>y0hf zL8D2u%}%;I_QC9P=H&+=%H^W8kR!bZ&2JR*Aq3aHJ(@K23nCd1{?l&y%g;Oll~sV# z3057yS<0Pe-_>tn5nI&*j%3SP!#zBAo9SuTye7w3!hJ4sWsp z0l$8q);8LAGhuyOOHxvqs|5@|Y2TH}v@PC3T=>hScp|CqsimK@;?UwcE-@ zy4QR0(kz)6+R|YmVS~0G1#rMT4l|w|sziaZ0dWSR6qgsV1yN^2C7mJFwV|PU)!FED ztnF}1tdv$9hG+-x7C(+X<%X4EvlLZpjWFZiY}12MLL4oqZaJ)C5uUj6kk z(PDP{M;JB@s*|@hqqr^{9+6+gUpGR6qxGlIX3j7#Ql+;a3!+CgG!3nAd1@7J4xLh;v*J z=sv|4IU_XddGA)vy(MvAzd3PKW|d~=@T-P|kjJU(>>=OEp4Uhf{V|ir2&afCd44HC zR-#hp&VcweXPja-zm|u2MbLtDA_mbxKmMkO@rR4VmkDqfBI}Y0!f3t+G3o1)+w^KA z4V0a(F2x;Dim*-te4;nq@8+alygdPT3_Knv&hJJk%yY`_X?M@QzjCGm#$hOzt<@e z)zF|%WX5vzin5EFWsZ5cLbV1ol%rYur>5nba)y&;bpijylZ`* zskA_%=)P#HvU+#GCnPAsT#32cmGXgzF~_YHk+z@!LCF;3g5AJ)9w26bKiqOokyGg?103V)m5x1P>FA8$jWI?(G;R6 zzP2!;Pj;7eboZ3CJ^X) zp}=Ig!B8JjtA#(-7ehWeYjZW|`VYa3Ol*H-IQszNUbO=>ZuBOFikv5+Sf?aDApEBn zlzQ6RH7LT)8-H-Qpk@fVS38Euf<=QhNOoyq$cdBYhw~;F>2^u+wv+LR77Qy;2gXOC z^ALXFA;K;)ciZU(X{(E^AE_kss{(MRfdbbQ;P$_asbut?F}7Rzor{~W^d`3Kk@K0)cX!Ufbxrj2+C2=97t=D_Mt~;YDMeYO7_+vS2-xP%w%Pe zOu@_O*(E72KAiVIP8fj{PN*M^E2T!sK`Ze2o+Y3g8B z9Vf5twIAdknNu?lG61#*vB#zAORGfV;AP&wJrvy-sPR0)r=NiyoAP4fTfockAr3p|L+vOQ@x}MgxK7PU^CqxB#%&roqBr>PhB5KjiXrm%hiN z+iBV@-{P=tl;9HWTwBmcZz^^)b{?Se3;OnjoKS5CJ6f3Bci%qD7P^F6Ho}i?sI2`y z?tYWBwVyinxB!btYsl})?v?>X5Bxw}SA=3%y*2fm^s9w>0C&b_A96}J!3@W2O;+jo z(%NTC&+*(eCX_w@<+XUL|T) z{N^uogdZ%m%&x9*Z!2qlZzgtqq>EG@Epj`S<<;*uXQHtA#Zfc6wv1FC%oinX{4fSw+^Q(@o z-hNAy^Gr@^@LR0b$HFCn+|GP`&=M`6QG$E;R8%`ND4dm>E%nDcgT0$tho`ha{v9qV z&@2$YlY7(2LhoOoS*=5Z!D08?f6g*_)rAqU3J0x;pR0s4cZnxue5Em|D8&eW)_Nms zwoOQpIP<8Np!qzK=_We+nO+HrNa4*;EbE0hAqOXw5hl^}woo~>#jRX4ut5?O>8qjk zR3K*a_yskq-2!Z(7A~d7&Rzp=V`sHG2~594XC0yo16Lk1Q?rLGgft5Ool`BO z0*M1#-Js>qPckM$bX^u8Am|Du;r3_p>guBOd#uNTST%sayGZCmUZ+kuXd2KY`1i>L z4np)^rol}wT?U*;2LO$#@n#DkPDJS-Y~}E*@MzuBM@Qc)yiku?rwz=*vH9`!3!34N z653ByC~jZg9fF?Ii!H9m2b`9z3tZ$Ygr3V~rApKQ_n=dm;kwB>|KMyTKKBYCiqvg{ z{zoBvcKZ8(zu+laPhxtxF$mxeYp!Oa67=XGhoAC3q?pu$i9IKl<@&mm{ftEAn${AN zP_ei7_Y{5THQXOY5g`Hi*|Tj^g>babV^QlHed^;llrEv4e z7p&7~{Vn5bU$Jae{$Y>`jzFnk5W3>|3@ORy>T~xyb)fNFxy6J3%ulL_4&fGBA~D_x|FEpCpHNlCt6Q0Y^m zEkh{Jp+HW;#)k>5nQ9gXtJwWrBmMhz)g{5L7>|^}fKC*3n;*ZCUbT65rhL2%e$sc- z3Ex=Tjb*_L{>Cf4_2Dz%;^k*69*jYa_@YWl=UhE@hA0oe_IUq{=8Qr+XC+6fF(;_1 zM(lO%vVa0R(6&qKU@IFQ&|ROQu%&zNhfH)>XyhWCs6a%?wmAv^MnQh4n3M~?-39EK z08uLXZXCzQ29|Orqi(NCsca|BWOg{>hsU*rxUcs@@8Y%MF)Yo{g@PE zLI}25WBEFJQ816xsX$6h3m`7OvZF1v6AKqfDF+8A1D$u9T=5$X7m1y8=&pbjq6_As zaJgQMo+=B`6D&yJuG(E4OR&PMON-VhVs2I}`$iXN%+f%sMBK@39~Ti9{U(j{F=c_I zPhH5M9U@ZYvOtTc`fjGB!)4XJB?i>goEVpbgC{3WsaN9LNJ^mFe;Ce9O?){`WE?~> zTwH0V5k;%GT5J87i?p;lWC4LC&*ZT)UrE7hGSBC=>X-YIF@!cPbqE4OOyA}JRGOAJ ze$EE%p>3Ddu<<YeMRFhB%cHmO+;>vN{D{o#tk9SPERupB2Dk5kQps!^Q zV(qeJyM1sssAIs+(=0AL?reJZEyPr1>ZUfQXEV0}^U=Ug03RXv9|mrx3l&4WjdFO% z11RGr;|USghk6lcg%k*64GhTGs5Ts0LI&67Oz8A2Ag z7eWzvju6mh=Cv0IX%7a5oAJixPk=H)&qLJJnRE4zCqV=Y|Mg93uC!`%%AXh)E5@6n z!JudVVYq{O3dJt&lj9IY$&KX|Sag5P zn6)n>qJr}G(@h;sba_cs!ftO!?DRb$_}8{^pP<;ep`92<3%?E4T;8*Aua{3^_Q#$f zT>?1J^^cgK9~K#xr4t_AWkwQxe!0B_&6NJ?W><2Qw_68^MYWHdrQg-sPj9%3n;qlF zUQ0k1I=n%+YA)+gj&VGU>MDd`x`tg4E-pi|40HO zL}_$=X$C|Jh8;SRekvT`3n43ek#3%M%nD>bcd|DBV!e~`mw~D2OlT;c1>p+Q=Q(YITd>xZcv)|T^`M_Wh(G_dWuT}*zzI# zTOh_3@}jRDs@Z4r$zy^A_tC<&Qu9q*Y<(c|^u0Vvmgd|)d0Kc_mt>>I0uzD}jRYz( zYjl&DwNzpu&C*81^B?-R%1b@Q`Ta1c1+iWuQrYTJlbkqg=oZmtNeg-;*tS`03Zi%V_%)B(PacXbnidNo z`VWIa4EWUbfM4X}pPyZBD=B$I%9b$E_zVo?t8}2e&s>cnieM=gp=k|G;t`-hokP3y zUDtKnusKFvUS)icoCtdQZZVMM3}=a5x1!We_*}F1ynR2c!_z9w%_6gR)4VaA^(!84 zDCHkoT5pt>`nl7$uRLE1r6TZna244*XnEpP#-j_%-77=oc64VXYt!EbPfQBcL|4>d zJ0Bs9WNZ`};v-W+OWYNXbVtRh)a-0s4wH|v^f@alz*aT6<{e4!Xfyzm@Sxg<9MD2B z2z?A^d}P5C&(UC}04CswL_%h4jtwZz;fP-OvM{4A1SSSta&{y06mP+Gf zv1JoSqt+H{Ib+kxZLb|)>|LXn$@a9j$@2&bgr%2{C@36yD`p6@2^H1MH@du6Q15I| zU*wg$mR%HLq~Cm4Kr^E*6`^qtJ)vN`gqNGwU4ugrFdF6A8ouH@$D?Jf^<4YA_(m%wT7W0iT;lZL61!KEPdc6K%Xk*V)sn3p?#(v z3zeXV(_GKVKB(z*KW|9SJ-rC*eRSqTk<$A@gg-4Q0K{_JQ{ijeKiG~NjpPPD6R+v{ zJyt3|6`X)2|EU3u@UnccI5C+#7;<>*iCU*X#B7;R%Jv&wT23SM?o6MK>%n zVfJQsyGN}1U7#u=3T7~{yb#yT=$q+6jFunFKqR^Xn*|=Ua%WbOJ_0!BvE~1-A3W!wKpNbT2;Iw~=n91UvXu)jyg z4vIpv??ZAhLsYL8*1JbPsmI1ixPNn2E^$wjt?D(xvZ$x3xqy2hpcSZbKqI&h8lR;+ z4qrBEiREZirCt83$d5`0a(mu1Bl-;YymQbAlFarqYt`kP#~~CEQX11}O~aiM7VHi( z1*1D=SzQwL?#iAbWlDE3MUT6&`-28&-^g2o6uCbdDNkFuC2QUd3nT5|0x-yd{cGKz z!u7?if)1AyXp^5!FMw1ZF|+B@+w&T1C++7@9wp4w~3mkd4J6gr^d`ZsJeIOClOq>^_R&L}Cv%j3UI#zd0 zwZPq%D2+{x%gRghax-s%8R;7{+QF@fM?#p1WRt2jy1MjS_^P!}6dPOW8ycwtPpEKM z<QW{9v+>D+fpH-J zr!=y#9V2sc^YgTBbzFTe$ROIB#SZdy#>q5q^J_KOoT(AW(RC_A`KYy|xe~o6_#LKX z>kb=yy^LDAP+wm;)`@OUh-fHOj_~7pgX8h^;k|ly+5RiEOP*UZR)%-z-jm^VSe_!F zRPp4N&5bjUtC8&%1&wz0-Nib4f9ka?a$DtB;QQv~3gz-G&f)tw{H=~mcp=*li?m7Z z1~Td0&z+x{FWUU6UnKw=mLL|zWBex@s+I3h8+IWUru_v;(}k^b`+00m!nNQgr^b6& zam;TvwvZ`mm0-e*SL(+P;oL_HBr;CVr)kO#K9CTErHV}+ELYik`+T#VU-)Mr3-?aF z=dF4jkupn5u~WYJ54+tfWTA=G@$~HMtcDWH%ZX_?c3qbCR8JLq`hPp2L=9^vZK?cy4;0{@nesa0ypPP2kvxM4}$ z-~5MRm{_32HpceEv(DW4141v>!B&=|=q%o%#b(FMK4F7R%-?ds`SomX$3A{s?Xb3 zhkfpq@Ise0>D+~+P})=sA-kGDTrU)YT_bcI-R8?dQcx*=&Pgj7Ic)vJ9IMB z40<9-ysEdhRNXJ-LGyEfgy^HJ`oHJ5^o^LGQQHn)5get|L9^;xwN67Uo!^8>9%F zm*4^TjYi_(x260na)ywU6(OLykr;j}1KqVAG207DGBK=`()Z0~!`QDSS!&o;`$s+$ z4OeBSv30+s7lKl~S*tt*eoUDQVJyeUdqGQWquZ}dT7C>I9W5YVxS*R{?>U-Id$NZN`FV*>$U^$s9g98VC_`H1 zH)wtkdLZKGlY))RVVWufuTChOMuskKMhF5*qd*jZ*Ma_Zm-A&}!?()XD>+umO{3>5 z^t0Ba>8w(Np5R~80Y0Z_*(3HH>^p?KalYxN`6W1cVHS`cfG8ZoAsu0BOukBIEMxqIR-+GlIMVjL}gCSooopDlN~z7Y4H%_D?q|J({9 zRk$1qv2ZFr5|K&wuG4#~_l8W3Dh9*qM|>XJKYn0rB~H51L{qZ6dKNF_-@;^zkE_JT zr(Zpr8To%UVzEUay|r)9$t1X)Hl@SPe2-1JV#q(zb=p-gmbrDR-i#r*E;7+l%)aM`JsfxZ7UNxk}OTKE3dT>=4Y& zrWQ9AJcI0S1cS>@)_VxSPCya>8PbBf@@vBgQKXaS_h-^2b^h6@l{q?cW-`A6c48N#^E(7vo8lQ-SOfok0dr^|(Y32MZ% z7IG7uZu}!P!&QV*zk+)`#7lgJJ*9C*zW%dVU*#Q!CV;zE8T|xnb?s{(m64xvtm06^ zD3Tv}Z4%zKVNYz=<&OIapIbQ^y%@-5mkoa8at-v*Bcirjk~-aBazh-JsE>${ZP6s+ z6XjCL`Aod4Q~AQ!_v2a?U$h=qcZBHJ&`6fW2$xz3-XmhYQS-bNm5d@+9vsCRWaZ9S zNa|lNT8pNjq(`i#QPdPYZQ@IxHd4K>^!z~`!K_L94$$!;sx8an`a`o^=oH;ElyIl& z&g1iEbOPrATa2mTu@|W6aRJhWCjXYx6ARFP7;kP?f>cQPhF%zX$KTgi?CCv;=ww3* zIo9j9Tijy00v6{TPK-#7DOP!APGh2%E(QZh zw9BnlZ!0$zfBVZ8m5Z4?NB(reRxUsK^O4&nSM2CV$wkfaCI=^()AK*(G}%hF@Xwtu z;NdI)<&w6pz>|3(5eMhq+^dsv1G^)RM0fV)H(ZV0Cx%TW4e;;Ap3_uY%}F@!i^918 zTO_wup6FaL+4KjVL3?+QO$&Rt-HQ*_cKUnK-^XaqSz#F!yr8eHT@v7?wL_ zA^O%W4QbvM>=!L8bRr8Ln?0{(;A7fCE9@@BxT|+HA|!jZht-6ZQ-@%H+QgYvIqZ;C}zRQZS&EoVmS%!AM_V=IedoD znbhb0K%*vN@x?MJGQbuQQI;eH!;jfBQ5^P`{GLDq%Xb3Rhv z+Wx}@M{)&Ob)B$yH)GS8iqZPw@K{dswcM4^gC>8X{{2*f0EJfKp?s@spvVCo+mJ#@ zV!0!KwLtDU10g9*UEbGtj-a-6Jo5q6_=fKO2f2Sl^Fwdb(P|G8OmC& z4e$JV$?Y&(zBCvO!I@>?E$Ao?eErfJ@T(Ox%UEZ*jR zA-r(T8T~3)&%|*B%36nQ?HGJuC)aU&ctr*n?QnV7v+Nnf(aWh4g~1^FABMO?9L&z3 z2X{k1nJ#lJ*KLyM$Jn4J3R}B*+Os6^%t>UOA8?6=-vJ{67MpYNPNwK(31O9t=*^Co z4Xpqdv)kM!>`g__7}Z?;n0wfOE-QB?D`{KIoiE@0S>Vc6PxIz=hbOP(L!BLNMF&&a zL1LGVZ7Y0#+XKnY)WV%wVcK{r`!gaIOe~GRC<|Xo9A#CI;h+Z?Pb2O4_Vmyu|~m(vJ;w&V+=ngdebO zShhAo0$I0{76I@o7^+OrH-F2!eCys*QuT6uUH^CY5=)xNvtGMmNR$!%kTAt_su!<_ z%J#cE5davtcbVn1|Iq}A1*2W4L)7lLMBPYVP8Bpbj0LR8j-tfjlX4FY6hxiLpCVg3 zHi88oY)vExG#fB*G=zUQOZwtB#ee5^3Bj(%Y7C~056k!8LpK}@N^-$`vRYZZ5t^&G zN5)GqiY@v-o4G8iFuoH%Yzl%#_J0kQHa%op?Ww=D8=!9!t#YvHBd0-~8Xe8SpdSdq zA$psEjpwgD=znzMn`5~uOjV84{zEq{)&jk=WKO(eSa5~W31behez@oSE)1u9YvrWv zRaS0u+b`P%%Y^Lt!NQqeu3dj9gY#7U#82QN=$CBpw1q1rPPgq4ba-S!mDM}cw4rg# zQyY=5smGXgkkm=MneG1VdO&}zJAo$UN7$Oh*f1RO^{!S1adLUrYl4Tg;tDT8bQBzS zv&B-DcK+jgB0OEOtE+RmT3vtVyLB}h@*(|$ zbg&sqWqs?$)PZx%8~ozNLJKLnlTYs}0;aTATeLG~gi$2iicV-4cXfxdRhG}gp{G@~ zY+v-E%2=BGIMtH|pfZ)BB)%(>vtn2<3N1uHxq?{`Q)Yrq&Eko_)$y9{@%-JdcrHrA zklbqI7uY{-l#N zxnPa^o84VgE>OniWJTLiJm`I{_}*=EQjM;jVOQCLXUvU3*qDJbSzq*iqUC0%6ODYa zlt!jTN}^|CiaXXC{{})6#fGS@KqHhr%8l&x>qBVddfI1Xvwu0HDUnRjlDCL1=|!i= z)u>|Dxm~Lp9iRUVrg32jmU^4i*SJ0J6}QF|$ni3lLbZol%E+1g>b6lp0BnK%Y1i}b zO}W7r5!vr0N0{T2;X~JLV`GUtkXoS$GbQo^<{S=}lX~d4tnMhE&0ePY+AXqID>C?FXyKSI=j_6-4H5+{T=kCxgi=NFg{V@|1)TDuIdKZmdKq|G*z9~QCZ2WBw z1T>(U?%7IgPdzvNybY0yHxT}tjk6@!*Z|fMU|sZKc1w2%UqJ zR6hyFOW)nw+F}WO-&#mM@r`QKe;D-~g-gZ=4M-1Q6Y+iPFFJ3;h)Xj}rCra0f@yLu zeJkAwgZ9!tr$Xa6_&!e(&0+}ANDOcXj?}WuH_>HvXScp0FrN#NsPu9QLs+7`9&KO% z)Qh|A9-`xi#Dt)2m+%L^dG{ZdO8;R*dw<#}A97=A>wmZFRXgFbVgq+x0Nd0OAgSlP z9J=VYy4gl5B+%ushhCCiotvrIt1*#RBvpT5|5A<&XACRG=Tqko*1_~%0cWc4!OK|+ z53%_>5Ctdkq|TT_01h4~eiFQ?^}qm=5NJWe5jwoIajxZBu;?^dS&<1K3M4+Fv=(WP z*xURM<254go00ZTzXTe?_|5~pd^x^<)NdT&9bU-}EdKWT46>@K|8xbL|6aE0Yw>qs zQ0wN<^Lf1go}K}kY*97&{ZCnG&;>&GA+TMi^us;Z?41dQEMd{sOF5S{&RqOpKlLm8 zC;ZMSiRZo)ecJwzK`>p(_j2DN>3kiuDfv&_)9a8EX>=omylV;alFtb2AVZ{FMy zJ(ia4Tl8@(K2<=_%kT>o7-#IV zM74vR$9p-lVpBND%Gz$_g+b5c{aZa-oV{3T~&*gCw*@7>@A;7Jdua87T z6By+G1b^YH{zRtJZ`}pj+d>WFnWbS{SQZhYHw0zzAM|WRhZ|0FDY9iicX=7QVRS|` z+j1cP)|>nRdYVXOH_yF!uZS7C)pKfNgA0$7`MMij&$1d4ndx+4v&TV3>vkgzRck4B z(MY1K5QXO|B4H>tBNa9Ofrx(0H1O(h3ds?hyR)78NBUcdU7Nwax}M02}19axCo&qTPBsk5-63*~A;8!9iIP z+zdpj_WR4Dx=ao+zZP|Q&aGDNB8iT&9(pz*r+aAj7%+q{pZqBAH4Ic*WPiQNC(=k> z>*nIx=d%{l>WK~VT0mzq+9M(^@A^S+=bJV#Px|^5r_s0ru3G{*%SnESxCucZAH30=v157 z`zOH(9x_)e&3?)9xbt+gI0IjynzqrDoPSfOm3+KplIN(HZ39r(i+?rfON`UXxs@r) z&3Siz71s){Hg~^u=ROui@o!tV_W^l3(1pznFyPcG%ZNrbRZFN7Vc=}MnY5v>r&yF< zs(6jZhuCk=%|2&e32%M6U>DV?Hc%q9%OiZJ*mcl1mYYV;;PTOnjxA=I?;!61E;Fh5 zjyLf=6+=^?^>c8erfLTgYAnids0>1hb8VusUFcf1qEviZ*?O_>SYWl;PMrD#f=a7$9;Ed5!nKO9^RkP}6ZPr$?HuBRjc#9xawDRlihJ2|vNN5$ww$=R7QYL}UEOs< zlEJ|F?$9C!{M2JtbrszaFmJmK#@LzvY)k#G-|kU;U@M$$3!=XRWbM&8v} zy|qBz)*PNDQaMj%UQG`@7@RmTF#p1rIQ)&TMc|&55Yn8wp(Ycr;M`#u-Hdnk1XR3* zp3%KjoH>_DrBOIttSWosoR&Y|O7I!aOOGLyl6J5RkTMti#2S6$aMJJcD7v^RjPG*c z^4r9as)21kx^v@HoUCxwtS!?ojPTST%m|tgXi2)YEAc8kd71CeN`nvkSsw1r!#rVT ziqsbH<~$F#NT+@7?zV6msQ zo%1LAn=H>uo=$<574(?W+;(t?2b>LhY!Ex}A3J+iVz`QNR=@ zI67rKTAZEKjjj&nbk6wS3HJVn@d^mHE_5_+?`&578ox-F~i*e3GY!h+gxXF)>+%j)ML3*1BLHReK*j9caC-%PkdhvWDjmWgW&Lc zAWsef^hd<~1+8An|3u%nQT3v;D=(7}tkTx#Wzbl+eI22h>f^l9yv~3oPnWcL;1fvH zUcIkqTDq@vdewX^)?_r5!2_s{W2|M)V;V^TTeUzt&)) zB>oRc#&d1lWVUm^T|Y9i-xHtozI#Z22eS6|?HsB9S!E!mjL?$Uzj>vM$v|bpGlaKH zA%rnort_gJyASZAg}H{OJAOCapQn*2>4yo`31khR_;;be&l5crrOmNeZ>RWcC$y5k zMfaR>{>ZIZJ|2sF$Hj1t-*alR1?b&L3NvbiMwqIg#Ak!8z_vt`%xa?p_5%LsyJ&8}Y@snTDo zFgd$^l1N8)4d!+e$R<6Kx>7w%DD-n31wOi!&pqAEJ~;CGdwm!zZD?5qA(0`780UX>66+cA0IelE(Gh?2byo#iWctC*eZXM%Q&pU;B0guWMa1vB$CcW6-~58J&$1nN|A&+Kp^T|O zmNhGwOK;kMV!v7S&kfq=YmRaz{{l!jL}Hma_Lc_Dj1R@z?eD=S}=t zj!)wSCa_u?(hDoH>?4YM@L#dzxI1*GWA-*_`33syNv$lP#FypC;wEg7fxg{^(Qki; zF5c4XB`t)QXa>4c!8A>G^H1X(^G(*!M*hl!^d<%8^iQI?4fThT=rSUSL3_-uD2~S^ zTlxhKNNePM$%y)OLU;IGt@kBYFcOz#VjD_|-c-3u06&{P1Dif62Pr!}aw18J zcGU4ii;^s-Ay#iU zpCD3D{gm665wS`E4s6oJhDkpesX8o2Bzd!O&wC7Isqzk?x{@(^;;y~8Y+5Eg$xA0N&KwQ=qi)ndz zU;Mj!XI5789uL~B+XkF$ihyN~>#ZBCd^fqb{fh&c{~aV|xS|wj6;n&RSSb73Esu?6 zgo2wQkM+y3TbC-rqyVq`~cymFRL>ZqK!IN zAY*U1QyW;iHh)^Z!d%PlQcQj-(dA^0C~ge#j^6q9of{2fQpr$|8K)2gIK~RvDU6c{ z%*G_C;ob1}6d9gmUXGE?eta+x98D`wk{<#elo~^-ZE;@B>$v#rN;XU~;mGf|1TEOC z#hi-HZP~p)N>eUdSv6QQ=pGY2G8+uv%`rvei=g_`4Xp+ak8uRv>q^Qr=x;?qb>U>-3d%`aUqG6B&sY&?@vbnh89Ew!?WC3a> z^JFsPhS&c4Ooboxg4XWfvGRG(E#$A!4w1S#%U2~<|t6S!2aWaHHqH9bC` zh0m{8bjwfzI!=e`f+P2@7B?W}a>VYOfvKM*MUX`Wd>Bu_M{$?)s?zR`wwcqRC*gdq zPV|HAs$d&Ci7RTL!6G4j>~C>RCftPco6mgfuuB~^5Es+`{8hnKb}T05sH=T?RnK1E zX=BMt-g$`;XxsAmcCdlPn5O3qraOG-+=!k|4a#_lLyl4qJ?Ds$hNyjvSewi&cd#q% z8f=ZoyFflkuak#r9-EhRsgEHX67oCuEgwnHN zsc<5j(OX(kb@KWBB`cz&$OV-G{~a_ID3SrKwa?-pt6`qGXvEv0&JtMZ0vL$aoGaeG z^>-V@@KAr3wQ4*JGpvjM>6ik7G76)>`k_#*xtmty>f+`c_;*fgGrySU<;NHOr{e~P9C%k3HczQVXI6aV*cP8yGb>Wv-Q zs*ZBxOpD^Q<3?m1d72RTTJMu(5~vO=kSzA|wA`5`Fgkj^y_@jb zKyPZ6J+T{qAi)=&P+H$GSy)R%wMzsf(q@Wt&!cEnMc|Fud#vWb(ytzPLX!$vx@EKZ zj2S<3ijc#I!iAqd=(Fqpcf79`1mbpj6TRct69`**qFvaTt8)G`T!m*9_({xk;S_kP znD8G4J{Zyo9@j>X({Iil@=1}p52#XaiY@Sh2W*PAx9l9(c|zs1nNY-N#KaZ(2FCf_ zX9q~+o28WM72x${9ePdB1>|f(&o&v{EKV-c0Nh;v7N7x1#727CASE_dLiBBIYXYa4k4MeRdaf+i_<9pvRmA z-zt8-*gVLXp?*V_yX`{i8#N>nGuJ6oVeBB-AaQx;PWrq%K$>Drk~a~@6-VKBi*h-2 z@(V2b+oi~UjUrB$MhhcFwMHd%41r`Ehthfe32DP1f#auY<42X|$i)deGo0KvD5-Y_ zqcLRevj22L6%11yo-wiOX_AbBOmXCkhDnqNR+L-||B3jyjZduz2Niin3z`3tH(Dha z*b!o=L>U|I#WTGL0$=`7M>_zy$Oh3u2BSySLjb`H`XoWbj%3+%Aw?|oUE4z|^%j+R z(caA@^mCqm|CJC98LpnBc zu(99!yzl!j=Wx!>&hzYhf3N$xK9{6L6C%#3DW1`+!6B|OanqJP^xAkEwOeCwYwqq1 zAWyz{YZOvx$iT1|2<}M0Uc4CA4H{f6#(gYSdoQ{>5(8!fFK3=EU7_57j@T#>YY3>9 z<51qf`2VPoO3)e~lG@fEG_nY?$`f=aNtFH8mxkQ<%yK7@4?JCuDq z)CapO*~zc?ix{&)2Q~|VFa!?jPVD(MGceBCS$o=tInkHvvhB%y`8@Q&k8~{w?7~2o z-hX9AH;Mk?fGNsG$u`0tU?4qB>#A}$A%H%KS7Tu}w=+*Zi+nw<*uIe;Z`QIc|5kd( zKS%1}$aj6N4iXFH1|XzZ&xiS&Qd0kh~_ByD-rqu%Y*(!3XMQ= zf5|MId#^ThQVc3~M?+M=?he@WYVq5z8z#l=nh-WW@BMgy1ILB3)@MPT>ujHCtrb_4 zTDdjx%6X9L=pRz8O7UHNqs`b9wTOEe;v0EY#v!7kqqCD`__OHU(uD2SKhS4otho`N-f9KS#K_#p#)Bxd`!HEtS^>*NA3(nu`O^FC%xRFg}G!jTZVg<@x9geUb{L%1i^5%1$Xwjg)klE zsv${P%^&fXaII#Izpwt@?btVS>qUlS*1ekpC3(M8T%K%2@GbeYCm0MBAlKjD)8bs^ z*P$ThT$R$gcGbDp@W9I;o0OF! z^2>dniD>x#<#Ai=$C8|9V4Q7KJO1?zgtf>?6&|q^?nfHAK}0{9{MUqsMfqY4|D)2( z7K~owx_cXUDMhp5G8bROl`yd9n-&oM7nw2dEK%FL?%Bf>>))$r>=K!+QA-zud5*D` z?LDh)N{=&AK$1k&aueaYm-f+L`E_+{ZFT9}`Zm?*7DCOZVaxgLb*N}H8FwRh8!3Ww zPr6^W$%?v?Z|z8)TcVzz;QM^c-RJ(|lWXltlzVQXMbI&DJw^(cBmbkq@E||E223^N z*W9VnX9>gY+EC`ebqX^u*wUWdnxw`#W#_xnkb7F1b+;i17_Jh`4ID2=UZj_l@!RBP zn2SDJcB|aF@gFey7+zPPXIR3ioxhCZ_AxnpI9SIwt0;1Nboj5--)DReUug~21nnB_ zI?Nqc7ku+zHH;*ryyZqR-F3n6AcGp<)wcr$-}xZWC5fpql{#Y$p9%qGu-) z0~d9=332eUJ8!gUt}xk-rR^M&Jqf?l8PKg8ziMWZU8-3P|dqI{3!j8#o9X@eq~E&|>7X zQdUHe-L|qY3vyC-zemORQ)yTEr}4vw$eyC8g;Zh8$MlL-0L5 z(3)cw)n_%x)0P-dKG+$8hFZcp?L+PScg`hun&GzW%hCknW(B@RR*j`I(^5b;e-Ubo zKV1=tZFg#q1TnRMD%_NuV_HC1&LhMFO|5tEozxws-3k7wb3eT92@_tfq}1G~gpDov35qVg0!VNJ9yb2(whe9g&hC}S^!ltq;X5}g9DwhR`;bgQ{d|8ugO+TF1EA^wBk+SXqraB;1A zes&vn(gA^Pjb2N@^a>XCvG?NdPO&)sb8*>nP7nxhN1@XZ5mD*Y*3|2RPL`-3G_&Bo}e?K*`*pj7d6FhuNHgSd{RGj z$;|n$((5ZKY`C9w07jecK;$$EN6EmS`RbXho!a0F`2|}i#q3B=i$6btJoxp8lT$I~ zPOZ`r_Rl((iqix3vDORmvmXa;2JgtTgkM2wDrCnXAE`;Gh+EUw3ITFQaIHZ~*sxPwaP^j7_27zaPsP&bC2lo_Q1c19R6s9YDe2*n zWJkHOToT`rN{!xQ8{rBR&d^Y~tg&n5Ma2vhDr`gPH%%-~QIOBv^yOpPh1>1SzC%0) zslJD|&Gwwl-fzz{;{-5GJhi_;6(GiTr;%CQNg^R2hN9#G=7qAEyYj0|3lsdSiUX%6 z^a+p%krs%IuKV|lv5yJi1~q|PCxKkL;YX`*oq|iKG&`!nSlU% zL44_#RzqXfOc|TNHB%PNW*AewlKKXef*jX>F#O}diiGd`+A@dgg!RFCBD!)pW#M1h zo6@O3%6d&wCDa!wpzI*;m|hX*!9gO$I)yuBe=m9(`)XoNYoocq;iLRzPL@wc@bn?q zMoz>S&=tYkWRe`SmEZo@pfp=xyvaUhy?5_m15^Y13~Wjp=(WC69-tjjXvZ72wTnW;jOA9) ziZ;rF$9Ota>U`uYh1snsu02As<*7S=Nhv4RktD|69ikF%{{A}1ryY_8TTaYmPbPV8 z0$$B(1ndTIw*@xnDsMBD19eFvsvcr{!|q8r){l$1i|;ly$5l2g!A7^T3{oqJB~O8u z?FVHN^V}Rbi)WlW1LVYE9rd)SqG%Xi`V*1jITE$l#eM#Arp_)&Vn z{p4`hXIBmsMv6j#H4QCwhn#+$F~RwZ#~DU#0tWFeXyiA5Y}>%<3iw<)d;O+r6;~E` z&i&S6T8;gFR_oJd_n4LkI`pzD!MgP$7iDw1Flljq43{@dgL`wo)X!2z$^zq-Z(pR| zXlcCu_j)(0-L8$tEf|eiF}$4o0( zWBg$Blx|?Y13-8UuiR~fr-hLEA+n7L=cY--3d+qxk}+A7b_E>0R0HYGR@MeNC@sQQ zvVCl8r+l-Nn_F^gf?`&0>|Si2?-HFnNTS4o6-acIL~h5BUtsN45@yz2&cA8sqGc%Z zh1d=?-`D_^O>P|QK`!136rCyG3Bx2oz5s;C_C^(fs!*X(vR=8hP-TFO%lP7wm8CAz zg9srLYGDm(COM_GruXA2#v)iifm3iLzsdIjuaV z9n@n%rplXQR3h&>0T+W#ZG#yc@i(?z4Ypivs#JyQ&=2P>PAkl10U}{&cnO{SizzUI z59*S&YYvPK)5dof<>L88wb6+97n-dX44u37xaYNmM<>%`Lt=7Xk#?!tGMrPv50Xc3 z;c2SO8|Zk)9&wp@@&q0A?_0Dpg>qB{3R4#6j1V_MfO!!P=p-^t)29L@-K{r7E6hbQh_H?BgVSAP96_kb z;umo(Hwd~XUx)>SiYNG`o+Y+zc3>dAgRgr%MK_LeeZMJ&9rKjaW;__IEA3bsMJGZR z7Fp41ta^B~4t~8iHvlXE&zueqS=?PZ)op584iTcoQybn^Lc--x; zc4wNf0&b?I{BrcO+utsK>J8G5%=RYJN1#Vdf9grhFlpGc$%U!+cUT;ZF#ZjYx9tlt z(06pFOMqN_a(sHxNV&!gz1aH$9M_**On*QXWUUJ);ZQ;M;9|hYslrB(G=b1>W}r^; zIrbqVZ9!|bU^^~r7$EMh(`2ZamvxW4_Z8Po7&ZBiD&A8o3kT+OEeGrrZ^>qa2es5; zVM_*wuq@Mz3^EhYaim#xAs|$N*~q1pwQNpb`Iv$nNN2UzX|emkm+QPmK(KRc~f=8cLd*TyxI&=e(BxwQTgVk z@WgZTLX>j6T5;=Xd7YGwc$^vRY%IKhr*!rSe*b;#{O2al85%0sjo!C&Odgy;ozY&W zOls=jOUDXlkC2N{eo|5Y0*umoB+%qgq0%_CB~Bi zws@O2{PkYt%ul3TDb3Ax{pVAyZMx4KAM&#v@8lhoCw8G<#Y8gJsC@bXl*Op?ensTD z(L#g{0POcA^1|Ph%oY7t;HIE`n@=$DGW^%9tC^Nhu#a5DrL&fatMJqIn|}&7xt->$ zB=V9hD?d4;r0OB(FO<;+YT1S6u7knf9;tXk^*bKqKbD1i;v*{m%+wN~5X68Y^4^Jbgi9N~j;7pAe8>y{3xywZy7G8Ft? zA%UCs&!cDQ4OW9!yIOqBE^+m~?@XDTw4yHE0=;ce!M1q;KWJ&2hOW-bhToQc9@ zt&7cm>JzKMNJ(KeG7sl~!Veynjgm3r>6;yuu>eXrYPR&lmu~|ft_9J2GBh)vo#n$Q zyJdd&7kPlmDe@^@!p$53mi3$XwGyo0M6&J#=0f(~Ni5&*A4ggoJ#gUsN6P)5eLU)~{&w8D25EsJ9w_p>26k;U!Qn6e z(J1x}e{gYr{jb?uOEe$B=I@P^c-fb8s3Y*U;Kso!wOcJ;kxyc0^Wqk+9aF7W12YU=a_#p1(yjkZ`>-&R*q)jzB* z9o})#LifAR3@ERj-CjNHRN(z?`j$kj{mC zM_YS%m!p9Z(?~~oT7UEe9!G%nPzFMIhYGuB+D1)U0-n{?J53>IHw_m@bZd1MwXM5c z1#|8hGHsaKXpa<%pc7n)%i1T^-$G!H`4@VDs0cW2LiR%RRf^%W%HwAe!tusStdYE5 zZ?!Tk^0^Q8^8|&OmT^WRjXC5K*K)-1`aQWEmZ~QiE4F~G*ioMRxgBfpIex7z)Y6uN z_>#2SAkUH7*Z}{!2zL#kzR!j6<^-0bzPJ)L(rNy-j!y|@9?AOjec~Yhq5#zZih3>+ z2NcdgKDMzCOgoXp-n>~76UfG%P4@Puo^5nOBAX|Dcu9NpD%jnqv6O9aCI99?TnnsxmAa;E>_GJ_z! z=n8m7;uQGTn)c3LQqpk`qg5Y$g zD9$x>Z*mhcF){A%O|ZQMOaD=cGu%&p_PFb6&v3uTv@owk2$hR=Qs6jd>#4h8UO^7$ z`Rgv-?Qg#QVr)nCyjB5x!I^*al{a3=P(?a9VY&EfC9U0!PEfA;Rxwd}Q`BJp4KVO@I|bv4%) zosoQ7^=~o5fBR)y$2)xvI>q)s>Ks*!VXBL+BC{b7hg*PML|{@Vmnqi2zZ_n+VBJaA zx+#Q#%21@nWdhkQnj@7XDD&k-75oArpAj|*>OQDiGF!_x@Senx=h>v$m zVs1pMnmT*}c6Q;HBNt^TM?=TB#{C@!k!>U*J=-)%-A z^ZXG&T>@Ul2dLkZCDFPr|0dqOn68C{z-m1aw&$BUh!~HnNh3bq5aT^N{&%KfM%QM+ zO*AD4zmqopY4X!zo2{q{%NJONC5xi24}SoeOJ#I9S)I$Pw{(mBG~jU;*VXSZ*XH=X z$al97U$VXCpPvfam8FxROj~A&@@!uHRhyvy!m5|)yXP$ipCRR!A8oD7HcvUy{B;BT zJ>bO)tFD{C1ZI*De^y!?xp{szF>YQEqL?r%DYmqGT?n+bP&est_UhUf6aSjoqQB=$ zC;rWR{h8?J%?b8fGz!YC*N^hF%QOR_v!!#Ey2&sP?`QV}k^TxtG}GCtTk|%99;N1% zTPHuMy&HF$C2$U76MQs?#~8oZrqCvjp`xkOpJgY6vL!W=`;5*C#|Ais%Cs55|2D;k zZMUV{FnsklM$K$VFqVEP+@c|^XF@pp{gp;ryC&)KjE8@;Uw{T`))6V<_6T|Zq8NtS z$W9Z34LY~E`A3Gmo^ipts79&&kGy`5F7a0cgq%#d=6MKj$uHt9@|bylWcT=%Y(3o4 zgYZ|l+h48yRyW_#gIq7RT`b^WdDdH$yKAV-_U+fuC^ZRLZAe+6lXL zRjZem`x>h1Lo3LNww}tb<%5kE(`)A3k~L2>8FPfGqiQd8g5#*JDTk>oRaEYa_m(D& zyGp2x$cWKJcmFAId$HLOey5CZ4LF#qkRDc1IqA^3Q0|AO9Dxeq103eOuglRGM6N zZd`b~bd{I1{^*j)OU0AQ+1#5m3aGY+7Djk_)m{fH{(>d2jSIEv@S2EXz8bzz0LVN? zzb1A42vFB0yB@=Vew&-;Iv2lGZZq70(wco^xb0vyr4HZXAx>=D4vvu7@F3zl&~;!( zh%XY$fvP#?7@fsgwe0Ocge zN2KNg!I2V+Ff(tdcd6g4}h?)AE$(r7JYGbc1_=5fAN@c}h!V$+FP?XY zGMw*0r4|#2ncLJ8J!u09yC;7hbUAi9$Ll)!t{xii!&XHrfe7y)(2!Z=ZJb_vyAEY6 zPTrn`UHNd`V`0n4zd6aYQGef2N@dcUr-qUswUmJM`kjDm`XH~D6U4m&b@=^JI$5W} zHGuI_AkLnjn(5Q7p^x>c;`dK!)GnOM@nmD-SZ#rFh;#M*D?U4>Ufte>zKW~%*=vl2 z$98@E^|&S_2l>$tZH4dl%#BVxyBY5DeEE37=DGJYb)hikRJu`;U&gl0&E+U?Z)be( zu3#>>HS#z%c={?i!Nb4dxvnKsgXLGw1Iu4zVwDrmj$8KB*f|;)&05AoC9%rwaRClp zP;SB!()Mzw3WP0`1#cU5J)M|q6gkhujA51*&?;m92VP{GrHm_S0}TC`++P7b`jMc9 zfbRWkq4$ZK07cNBqy3VKMp2+|AgvX_EcLZ(eUw-hET@VpmG_5J!Qyo!&EKUO+nr52 zLYO3XAksEE0DN@gu1{+FrLdwgwx2e46~=j)r;a&!Dl17pe7< z7#1YpZ{mnmlOc|*`W+~#`DLfG?6Zo|@z>OIeXsHuGda@yXhpIaF{;G46Y3BotH?zxev*)qs z4M{SK?`P7p4Rvozz3&XL4AEp>xJE&!Jb~$4k|v6s8as3+#X+E_DY~KfeP({|9KFl9 zAHbKeQ0>Wa^txW(_}%We;s%UgG&aFV0I4PuFMc1P#eZ)yWn4-Jv>B^pYS_j#$vmj% zXdDX>b7-R`8Ec4qq>;tfj_dK0e-^Q}Bs|6Ez*?;=pqK0V0Bn)e!NTzy8 zWZFHB876aKjM=-ym#LkvgWmq5zk7xLXSs}+e=o8)_VvH2G4F1^I7joTksyhRQj}Pt z1ovd$8B~+Xo%?>Z2%;zPLB;Tx{74uLkTA@B{-*%YI^7!F)2B_BxLoE0KgSZR{+^bK z7rqXA6^dim=`hM1m)Ypp*cGxgvyqxl#nJ6s^Q9L56fbH>-p^cqRGJy|#oNC0);yRvUFixHpqEx3ln$I$bOU+*yD&@{64*So3ydga?7rS=}*$j+-#p+8>O zIDMi5>m6mcJOHmy+pXb2$A=S2g1|j+AfE?I);+PWODMv`kZ3 zl?SbF+r}>8jZKpzG2B>5>G(PCKf@16&F?@cHj;ckM%M>Bbm>mQZb0gx(7b=Ne`}xp zZ>kd%ycH@B>ol7)oNRZ4vEQC}q5T~3agaGNvVF8Ffci*wDYczwn9o1Ilve|y8v)Ft zc0=|DhbN5}S$CTNoYw7=c;h>3#EMX&}^Lr@nm zfoc&}=+}xkeu06TSP{cH{Iqw#0!^~vEHLqUpC)C0mq-j3D~ zxJ*yOdI@nAN$grzJ+tk=R3fX=0t?bMCuDi^?=xeswojCl@@!ow$V-tY@UOy0}5{kIE zLcV%Y1-%~ld1WsRKaJGBNQcUHI`L;a;BrAk&$-@3#>s!L^(A!mG_0T8`;V&S%^`}% z!SfaKRVt_`bZqefp#(UcT@&JLWQYkXe^mHz5XQho%U#p1zgi2-Y>2wXn%HG3>-X?`D5xIvrNwzAH+G3dn1G5CR}*w+s79u#snxV67$MNQKBAS4@{oWxK}(ccyB#Sjlp&4rWykUjal#BzZ3}SCb(D#Y%KDQ za`br3SyEpGX0>^9JulJg4qv4LsIF*Iy=_-USPKQXTCqBOdrnt%HmP=R!nak9@2-5E z#5jHRdi!)^=L#O-xQTTLJeo$vo6hf5Lsfw`0>P$uI3X98yURw<#9lq%0kWc;TefVF zW4H|S%OhQ$sPHC+z4We6BZEUu8ib!GGwHif5z1J@N8U>w*cp$=^PO*Nzs-HWydUBI zc6sl1QqRpb6Cv}_cgW39#0Y^GcNx+9=GRN1hX%fi-SKVjwdP7qF}I0Tkh92E+sZ9WTW+PM<*OrWk8gcj$Px z{$mH}tGV((*gIH4p_Ehm{y6(9KF4*}b?7zsxPQba@V>T{!;xmN zI+PxY1~=wp7i=2Y0H2@#&REi-hYVM!N6F^c7Ndq#oZ!K}N9v6iA8#wKzExZoZW+NH zEnXV0@@;h{0eM9Pb&wtQSv`=qmDm$Z`I5Al5ivZMo+_A}Q{48n-9ypT&{#}L{a)qc zuP7Dcl<~n0+Oo6wJ|ma;o==I1_3ej;xV@sEmNwdqI+r!_ z7P@IYx6G~n`ureIoq-)ZZrjQkWE3i==R8}@JdrZ`UT|-4@K~V+=DdE+t@iH6#~qsD zz|vn2bJo7&ALraqpl(%?d$rN?vH4{6Xrw5(gcGUETC>rrZ)c=kgrGDQYwLGu=GIm~hgb18DuE=m+zYoQJbrSxY-K_J`DA-7yncz$Na?gC-zUQ8hLqhL&67oOa&O14odV5bsdMX#E8(wrV; z8c}E6(0+iF1XPg;*fD~)<36Ig4z@*{c7Db$gYy%z273`cVLiuBg z-A9ek6eljj`9ckTjrpmvbY-6QTH9)jKUy%-CtY33{`VI)R&*9gpY`%}@aG)&kvOp9 z>cspwgD(FuLFu#uTw5M0JZY*oIYEMSwG)iC-rz{4yZ)(-;4_+Y(;>Ax#1(v!d(52W z2N4uEGD114X!OxOv+l|QzpLY#RtCExvnNi?f~9lBf>d%s!e>lUXam7!&zSzz5_KS0 zafN#O$MB1+cgE0g&D8*GJ1Bob4(K?x+Gz8?=;eH~8a_;OwrK--Bu#Jd-Cy;l(RYhF z)r#lD6u=s!Io%>s?z(i%w^iQE+A3uVa=hIw0E&0 zSFYK}6o96GskmP8UaUlg!@luHwBC$;gT6aazA=^^JS8NUHB*CYHR|P8C4OI&BOViA zSnw`wNU^jBMS-wagLQa_D`Ot8cNjVKCz;q(VZjk;aioz?4W^MOX)YBnKQ4`}YYLS! z#?PjqufTQU-};dZ8q=vD34_9PyvniIbw2OeD%EVEdVy0;;3wyi-Bb&WaIVujnb)#s zBGb4&Y#n>8s#ta!_Pp(FAKc;%dnmxm|1^|Z8Sr`* zn2D*&VZQhe`*bsF!Hxv1p%soSoec>cOnIR=>IQH+c{{cBf%o^<_Q?m@Hr(FRJ4bq! zy}9&$RC1wL#>9~o|54r1lxy`;+#Rj7Z~eTCLMDXeUXxs(l2GBpy2~uSnyA;4!CJeG z)}H0OkK^j+GPU9>;M})W-U)00T`L914zjmqk6tOEHShu54?}ec0TI4)fjAF&gGp|* zapsf71}{PHXNS)5tXi{tLA=vrgARW3LNI-z$ZN#Q^=Vtg#bPqn5;Tj$E+#vaZl<<# zx6sPR8tG2HkwddHSy%%JSG&>dO#uj%qXI7aj4#E!XeK@0q@OR{e+U`}z%4?>X~I`7 zl6>db;`u<2iC0Sk-wt1~j+D67D9^!s@94vq#I0cT`at)mxK@Sj=wtgT)`ZMlVpZ!SH2$G?%OFe{(APYzY@ zF-S(K1dfnd?@+|umY7>qtI1|#yDb7@bDJe!Wr3!h!)Wj%S&R?bC;pcJ`cHg zuhP}18Kb~DP^4`=@FNGl3>{u#XpzV5Gg)mw<%pMX34oDG2Y+NCh-qnOmN>R_{hF+t zp6r}`z0n(@royGub7 z5Z*cfwF99(H4cco#E7crc^9Led(`V^XmQg0B{5h-!cKp%`W-bXbL817tPs-B>u1aN zXco3oLIH0s*Y*SbN{c0T-l#eCE+83JKAo9nXGksx2m31Jj%!Cm_v4jM+%wd#+1_w_ z_iW3@v$z=^aVvKglMr#NT2)Fbr{v>Il|8$Pjtmu_UV2TWA<33L2E>n4j?~+qb9Wg} za35i}OiNuXcX|R|#3pbuMZ7D+@tXG73H3*1ewf`xIR?umI`eX;=JRcWHl%{QW4&7F z70xFOwseIS!n1oaY!zC{^{)mAM8}KH+zK%2Tgf@36{Wx7Ib|`}g>HPi|0<=Qbk|eJ z=T!d%G-YQ`+Ow+Iy-Lf>JJCun>{1^U?=2|R>ne9ISB~U6^KaEXX2>PzDosBh)dJVD z5{3q`kBI5LAHkES92}XkuCiNMx8rK(JY6mwn2Aq5c@d!0QQq-m`AGKfmWhtrZsW}> zgMG{Nq9q6!j?_mm>6W5C8jifO%2*%QiKZk<>OwP+fBo+c#50N zU%96J<<`Y1@7pF_KDpsjqp`{(W&dQY-xJ(A(<@<bXk+`$Ufek=`g&xx(bwQ2w2@ zM9C}eK1!d{iImfl@iO;Z49B@gtXE~&R0-H+(#cR+D zhX8{M!NT=T&P@}yP5AHC$Y}+ZAnNZpWa(zBy=p%kh2t;WHDlL`*mK=8S00hVbC6f+ z6PR}qxdQxe_^v(^+n+bf%E&w1HP1v1C}X?*Vf*$?**x7Gn7;?o+U~+8fu4848`Y)? zk3-NuH{Z8LH zVlH=}+{P6X>R?);mXL&k2+NQ59Hd*i#2!^1X=mDXP+wJb?XA;6XF!2SzgL zIF9MAl3a;U=_~$6pJE^1)qdxTbO+K|`YY{WzU_3ORu}ndYQQ9vdo5ICa<_%6fC%c$ zm?Z1q;(QE+*D&+*LzEIGe(*5#$%C4&cce^f@$P%=GnPFtrd`ia_Z2t;8IUu>&+xeh z)4o+OR1ST8cK!B{sA=7$N6mwZ2QyyGY$-RhmnB7QE$J{S0|xJZ6ofRM!@6^yyX=zW zLj#Esc6hb!75%t&XF#&!PEC=3FE@jkwt?ubHhMsPLd84s+oP9bd3Lc$Bk@ybDcCsG zT@^jJ%i5E`M^)b2&;4Ur7x6FgH8+E}9t5hOw;>S}5M^wX3?(j*Ucq<%2!A37pc+cF zh!ElO0;35i;~eXpkB^5(!jj%98kZX-Hk7gy8+s-yuHVZZyfX3p%Yh%AsXWoY6FeHI$Fgjua2pX9%QymS)mgXSUvY+XL~d(Y~`JM}Nh5ZgVIo zEv9}>6i6erYmLj!S=)oI0eWqhQXD0lMYmW_HNH3VNtyz3?TxlaYY-d`a~+8~*WPi* zuXp9v?thkLV74Fvi^fGN;F)Q}u2rnS73D zNGOt*F0y6Y>D$8*`ZQM3mN6#s$^8PqKD-q>J=B%%k5%p9e=Xi0O8N1wKhQ_3nC>Q!SZ+V|~$t`oJZ@fji2;gDOKK=C>z%HRyY==SdD)RaLSY?+MjY7GiVm^ao(PM{; zl#8;&_}sLAw&p}pY{4uU2-zisJ^EA6a0~hQ<=5%^w@fzWUr8x!F1E>-iQEck1Rjc< zd5aSd36xrI)LZY~THVyuXO2g=*l68%bu=UYSQZi?8%9$*VC z2PBpnh}(hIDN}rBrhLcx-Z8uZdKo&fbhE_~%5CAEi;(P)Z6jn;viJ*DB13gf+L^z! z83{IhXt|vrv#DY5i%n7W>4(Dm-dz$G3`};DZhsm-=zqLBfzc`8sr^eGPW>ZzI^k{gW zX%$+QM0P-Dl8jJlS0`j+5-#%@Bdk>|yXAS>YmY{Dtx>zw?Jt%ShHH1oO!&P!7wMt0 zgvVO{QRVfMTY3PtC!}(oLOMuZK{iJffvh&23aom^io6 zGZ1BuX^0(GnWHV!ea8!$|I@FzJ8%%#KNM`6(C$9M9XPn+kH9zT;i1_-UHR`wKP}(l zIE=F)l1#-3u!Uenx;cG^*cn)eA*KmEHf${|A<9K2vhoV!`g@Nu?vCsBEc-JzvtDCq4vOw zCeEl!5)ITInAFPAjy^7;Hnd*0$M3S8rxa(AE|xGdcdIiWu4y08@E5QVW^zxX&T}>O ziC#zA))4W(a>M;s!-o*%dzt0}8b0j7D9#b#vd)SQ>!dCZ3&rYMcE#QA7JVT|pYgJ; z!TO8%#c99af}$-RZFAEm>zQtw6d%Q)!q^TkLD*YIopZ{;Lo;^UPy0_sc+;3&$M1+0 zUz_m`x%`0q_6FPfv?PKyiY2m-CiAc6n-x1m{iK8^_FqQSrJ7xfo2Rvj;yoVD9*h{x zH_7TewCquGIkz&K1Vrw?O-#vXpOsDYp!=Qbk^-)4IaW9*5E?1qZoFc_{MI>hO;PYl zRLeKhfOo-@7JkSgC!v3TZ~0x4GbqWq{j`aH**|X`RA||{W6B}(u02cFy8#gQMWy)q zs;q@%gAiuLzy8!BvcIlHuY4DEAnH_RaXx-dhv-Q{Ot1uqX}W2Zz(EO{hJZ&^Y0|$P z!+epzNwVlOo*HqZLN`r%R3nr#ibj7%-}A8Gd#)?Fpfa?TGc}R{*{fe+J>`%)Nz}=b zJc20n@3wp@L;g>zr$bfGQuR14CP=z|9F>Q597x>2-s$u`Hdfg6S0vYnwVo8HE< zO5^h`?A)=CSK$@|DRh;` z)0!QJgcPT`IPopYs@zvY^!+ry_>tv3W*w7!l4{bI?i?2#!i}DQKQXYrp5K(Qm(};% z@^|RAr7Y@J0r91@I)~o~?b7DE^SI+y(u_DN<63{WdH;yfF}4;iDfFkgVfsFhRx&8Ocv7;T1rYRIMV;e2>&``czC zN&&*RqZ{ti#-OjSMS{!Rp@`t?Xjdi9sy zu_jSnGLVS|-1rClL769i1-mXM($(xL^rtlO|18Oz+T9auXh?T^rF}gUEa$`Boa0{# zM2e~W>bb4|KD1a2LYX#xzli1(xpX&KW#2R0h|k^7L*is@z}jsQIcaWzTGbP39W}4o zqe7l=ZIFFlVT!uVUrcOZJi7O9In{VK$_@VpIj3Dv*6OS4L$D(u&T_e`-&4zFl|7V} zD;fEx_mrE0M`;8-L_D6;24$+sU@d7{;uc>N^(E{B_(6pAwJf&qFaD!$n3$!fw@G*D z9gOu5l0nZ58Q9@@ri0Rt)(UWl8z^q02tIhC^PJt{C2i01Ll)fWs~_ z=K&W2V?YjX0wr1!e;gHWopv3P1TW$-T^QOstPg;jPr{kZL%}#hi%zVn%7Vq?Lko-> z6YUvYK@74*V@kki{NwFQe!8j+0VWM&NU9v=jazgQ&@Ey0Ws~pz{us9yzF?F&cVVAM zw7Bs6!UpCCs9WwB=Y3ReGPJ(%b8%3(NDM~UEwoV=uPz)hBT@v$5f0PUz8)CpXRL?* ziwUm3hnuGC*u7Kr^o#8`yTgk<(NqTy?*07JQS+4b)zx>Qvp~v%O)TV>Od!R#SqrPo zL}3$idH-+}T7SvJsjDF*ndoC?dNY7&>Fm&2aNuUr|NnvZ5M+SjJIlL;xd)H|?on;p z{^cOEktq5sU7E45uBcj7KxpvXLR_e!53d4)EA&6A8NAaO@C! zZrU6ux(thKc@e#prAgPplp~re-D`(0muNYIz($!Nj)7FmtA4`mcJ21yGl4eXgZ#<@ z_U5XgV65#d1WTV?WWCKTn{e`{)>dw9K=9zL=$yM_SfHxccpL5_`cCTH3MgS$LO^Q4 za%)`EiyBrLHNAAJWW&A7Je8J5_SpPTVXtW$AUh3h3V*LoK+-P1EUQ{}<`-xe0SHa2 z75yJMV#^N{0NC2+lXt{RRb&rhHWqekbIJL2EkWXET4R6|SAIRymOK-?XyPO?RON!D*8qY>SH9rV19{=;w#bm%hZ>nPYuR{=cD>+^dsu8M87*5XHqVP^5Xhq{}pHCnZAhH#@ zVtPTcKS4`6ypEwnKGRr!dS&RDn>(;&Und0gD5{B(wTVl39kpwL72Ouv5o(-)Jl(=Z z-s4(zgMK1W;&1*>{ewwv8Rpg&2&ffdAFD z+;^of@LOelFSCpsBcn<$*K$RPBzK-0&l&uz*c#j1zmlri%bm2r;C8(ssmJEI_^mgG z^}YXaD$B7`B3*;R+Ls?oPZYfl(E2r#A>5phUYw~Gbg#!5zi%-J6E5N(vNf3$d4^q&i#n`Du`o5UMlCUfT6(BVpI98{Q6gwcOGIYP8EU98k0ZK;w|#7?~~0oPPQNH*vIkqImh0<|L`-%?SxOT zxBHmJ-rO1jalb(1BQptWQ?>FzvlGfZ33qCk@&(A*lsk1zzZ)#eRvdc>qLs0s4TkT3 z( z`w{Hks{j`DIRK$#X*wb4%Lg&TPnWr?eue*B;1S(b+hcERZm^4m#Ch}IVQCKP4^dx!o=$~Pp>-b9Rwbg1dkBeCN%trTIj#>#i z_$mSuh{HN^Kh#3na=JN5tat779v+R1w@QHJ=1dww=0+N(2>^W?Y|BhoHz%Vcq zn=o46qEvLtKl|O7jkSGt37i5^k9k*q8X$Zyxu8@%`lQ1V+r|y!Iad3$)5?@x+K{jM zAJuGEoQBHy(*wrxKkL-Ls^d}miRzQ{kHR{kf#_HL$qG2gQ3dAC1pj|jB$dlC(ihYJ zQGNdbXIlsigWMQ_6weWZ;44!{W&G$K6OL3mUT;QLsO*uel;n`zyFcQ9pKH$BF|-fZlKD^JVA{Y&Qd1xpPQ2s)}fGy zMj7ru5%Vh}CdvZ$xBVD{{fy2TPW0M~ix+{WH{ZY4lef|6yg^m7_BuRXNL#xNtotoy zmI>BgR1vpv$#T5V3<)w6;;~22KX{?uAaH#%XVFhAyrd4S;x{kdLTK2i!~@}}iJ=(i z9}doD6IO;D58+uWqqoMXR z>~&R7i|_lOTa4}w3$h~u0ZZ_da7CqcMhlKYZ$-+$cPW+32!7ektd?Jr%HRy~Z zfPZas1FuWn5`Lr|qQUPAIvR*}lMC;f6~a;UPN_k-B^%6zJGCR?E&mJQKK+-<7WeRR zo=-H*Fp+`POsno($6Pr&s-ONr7jFb4hP(pL3Fka!z?IFo|44+rCqoso^gUo2+vXv(~laVKyeFr@78gufN2~9Oz^esP}_! zx%_#qKMUJ?4;9EQ6%VY8j~}It^pTOQ`@alAY`Y-d8`oKcOTj)Nn!_A)X>ihSiKMzkH<@;5z!5vTSPcij z@OI|#Vd#7ByD2>y-%!*X+iMkOKg?Yebv7VdVR1&k+uvuPZ6+mk8YdPRT#}deHktmu z{c>PKh1-LQ!S`xz2HIeX3-Z2p#s>l;=&$^Kt>J>-xXu9=c*iDP&yzla=&Id8FE`#s zgR`aih@M&6(}?_g=Sd$}WcmUpo%eqA`#>6S#$9s8JqS|BaQdW01%wfk+d(Oyld*^5 znW(BeIM_WoD*n#G`MRd!OQM%d#{n=amw2xH45qy{!Skd2BWJ~b<8J(fOWIxv2U^cH zLk19atH01>J#r%9t)Pu;qv17RlrO*i^eX5P7^XlAm3eDkZbDiR^|S|ql?iurauW?d zLDIE9gY-k`T0@BHU=M-F!9Y=eL(qdDf?&5HW<|&K**P z(c6Z0r?e#GmTR`XI9)y}=Kigug+rm4Ez!I^x?ciWhPQfAN8sHwns1tU?)-MkIsq)$ z+a-|Y+*;^20y*`U2p=w7eji=V6PwaM4hM)mU^TQsH=20iK$_nqDtNBz<%3m}h^xFS z;Fn-MHn@cA#ru^}U+3dSl5g4CwTu?GLleG-J=g@SRkbUkBZ&bw;vzMt?Uz>Gr_*3X z+<3l9Rkv-0>4C9#;X<;^@p$r5(xd*|?0^AAm~B+4a&O5>ZP7u~CBOZ(9Jod|ioMP_ z{BFi@&0V(dx(J$8-KJ)s;2jg z`00pV&K;{oRzaQ;e}%i$H$|@J+CklN{t@l6&`!l)6T#xbg(c?myBAE^rS0&{p~j?C z`yUFJT>e+Qia~Qbec>q9TY$A31X{;Z+7QDQP9FtutXfhuH%fYHse6+YP>Ni<_ftmn zZQ{xDh`I%7^nRSi;L6uIZ`6waT4lZy;K=)zXEJTdOx-oyXF(!Xb2dsiYx(;$UaFWn#qPwJ1_Y5Sb#au-m>~fRo)27vZ*Cx(r z=xVXICqA|?HU8s=zOkeHG=p=o&>4m2 zFmo$#Sf8xj%z8@}cMGRR>WkRW7F&u5VWr>%rRK!}B77>1@aQJtT$hH>8HMRqzg)o6 zdsmi=#o-sj=PK3C%5%~0*cW1Y*q`{YGvdN63=@q1wmL9t5S8dp0qi=6Y)CSs8_A+X zWl8*0B_*JrtvHCpiVB|u8vMf<9~kgxm2YZe_UuSgp`SG?4fZUFNp--O45vE`d)w)ksD~7b;Uf z^2(iGgcT*K89doFJC3xAAkq|}NCZB(lppCTHwTH-YL(0n7OW0?4YVW-Bs^EhiNAMG z7T*y2JJ0?(Ha2{r?O+P(Or6lqaZ>=110(tuFJfCwH;`nD&fccM0u#Z8?w}&AbxWGe z;75hoH8&Yjj$&!nX2y#xW4EI*XUzs|v>u{~ZJuXU1`jkpY-|Y^-{UB7wf#0N9NC`RG|(vkdeu*UmA-kj0{yg7{yy|Sk^-|8Sl3PV z9A_SP4YifPU7Hsqwm4LZxtSEqdwmqz%{2Ry7Cs9v0O#t?on^|$q{7XA)*Upu(~v$= z6M7up|HcRraY%Od!>4LV7}*mD_{w=xra<`-wW6lV6rYJk7)=H%Dd?3EGk!`rYT3j{ zOVv&|Hk4RIiR=xe@5x=b*pQBKg;$Y-bx}MmsGuOa2_YEV$rtu!#JuV5h-N`w4Uu#5 z*7`OHCk)bhuqYh?;esr#(%#gIw6h0mM_xba#-_LPPffiWD=pZsuQwM0fpl{TzY%N% z@dE=e5~bVg{>`{vx6qkQ9@BdgT{zjZ>b&RV|2&O3I5e+@lTYY#%3>p@@sg~7S>K=e zn|G5ETQ}u|$H7!H65s1u(RI0Z>&D3s63s0IF9KByU2JLN3tjw37{ELcD$mYWa>Rid ztNb?^Ah^g95&h5HFxv$-x`EcdOacMnW~P>wmL5vqAtV2hFrGsf8aC`t5?t{z1o26c zv#7HhwJ!3F%<=ns&0l-ss8fACxo$NmXg%S1XdhlRcKa6aUBgl4n)~Bm-<$MS7bx1e z8*xuT8eO%aTDSpV0Ec%k#;%GWW;k2=>PS zN9Y~hr=`5T05+B1=06JT-fT-YS#~#){NYqMroA%1eg|0v*6I>n;jz$a=>)v|#zDv{ zA{P%^UJ&B?tnSsYh*ta9D^WFYk0(hG7?85W$#QTDY-FduFlQ-#$a zns!c4UNtrn?+y-qCmTXJF?mF^Cez-c_9;@s^Hy_1Js(OuYzHkHc|UnemOY)h z*$#HEAdH-vIup4J?eUKG?q32`^7&q_CDbj36i-#7&_v%pC1IS72~>PYljppl;R{We zHI~Bq)2Q1TC$G{s3cdK(vZXH;X~9Bf6LVv`R1oByz}-;^k^?l$Xoj=l$L z8Izao`^niar_+Jy{v+8Xu1Oj?pap&vLe$t=oPWU*@$K~D+;HYUk`2%`x9R?sT5mQl zfkvP+0lt?)+#K~Ii9ev%gxQUf9-_yMxD<%X?HtGPxqqw6`!kNF?)w8aFm)V>pX{r) zaErjkc&!UQf;_`>g}IYic9*(v$ZK(ZFzwr_{|0Y45fA0M`)cw1&K~iIa7BjF zBkKC`Pl8aA$2E2n?NpHQjN&e2wDBLX>W!O_B=az{d61-*I0+KIksiePl0;a2nSTLG zdP;4G(-lfM?7UXTznd-)GX+zlgpgku`ri3}N?hr8=L&mwGoRR6V4L{GGiz>&{VBi^ zj_yB%`eJwJ%Irb_~;PE zb2d!!;#OiFTN;{J-+~YH2c9Jmox$~FU5eg>2jeKf!kDbW>)@b#{PPJR1%bliP)SOG z!5s2C(N81~`hz!g4Z+*P?RCE)35{UpI*ud25p!m3A!Z4INShAFzTBT5nXx(9S zCa_OyNV$Np$&Vk&ZD$?GjnQZl$K+6-8NV2HqQB^_@Qe`gJ1mV2z%e_P@6khKa6;(% z|458+nRH1W4YOtn&8drng?qI_jsKBohRr_UN){g?pT7yf?>+ZS!m&&nnNj>%(G}Vm zEkW*>G&d)!=4=~%OooXEpTwesc3%YC+96rX)e)HeVn5JEot54*-l{|%Y;g0F2sRwO z0z?zdc2E=C3?`^|RdJ?{3{4#&SuQ|+LcX{+WEX$6?-ELD>+$!<@NPoZORA|{cO2~c zBV-`3xFaEQ5g0}wI}kxp>UJ|#7_+hbnH6&7!hxX7f_j7HGM8=?$$!$sS{c$1Tq?B! z&li##7stlQ>p)5OU5krcJ1$FX{3bsZGXV?d%o`#&oLBJ z^#Dy426ulzoSo!R0(%rp?hypRU8c%H`Qo&CzroVi4!N?O_cLn`U68>po8T#I#7$oN z3vi%M6FR;P)lw1+D1RG#ps2%V=a8Xp&q6CCJSp1A`p?Shqs<>$rX_iy_hgTa0yT zyp}#3M8CkGh~~kH)!p7qUV>@OIbL9QfcR{^pF)?BXec?5$A-9UjxPimOtWLfaBh;X zNr};mNAOn_a>-g0|I1=rF?UVwKT!iYvZZI04VD~T*1M4q3qi?QMGYFfXW|FWhJ%EJ z&$ui2xnQRa$KGr@w@xhMPw!iQGU>e;sk+yEg-AL<&@$ezG+6`w9s3jp33{a!>4 zdJ9eaZSXBy|1ch9*jsJ;G(S-Ss_1iC1BZ@AJ)|PC?S}lh3^llK}L_2;(mk&#Re+p}5Gp}o1 zdDMkq)~!FiCSUv42%}CLKJJ+ zZq9L-_Vv5d>N;ZbduK|fLQ%NuS|if5mT7s`pZXciOW8~}@$ZVx87|&&|19T^;l7B* zNn?YSi7F6JqaR#jkyt6D*S}2b-O2WhFj-e$S5q^&nft2g)8xjLn6>RP=)lTNQqif0 z$!6FijY&J)V%Sq+YbP}!BwIjk+;G~52IN#kDv=RZpD(%i%q2dcQzsH8Q|x0bei$Oy zu9Wh=QO$QVF>mZep5Qf`dpWphP7lKyBV2(Ms?6s~4}5pR*Z6>L13jeXT59zoMBg02 zKKh$TB8c&YPmFGjuIC==jdFx6+}axx(EWf5abZL>w1xvqH^#eHKYjQs_7&C7 z$|V)_)w}0YJCRxqwPAm)7FG+k_f0=4M?@-qB3J4U#Z?mDf-zlz@v#V{R8a9H&wGFN z6wVU}?J3}>CxU&U8|yrjt@XiWzT1wLa+nQD;&K+=?*#^EqQ?pgS%1#J)VTvrPfZ)~ zqYx*;(%h>5VH=U!Do}bPXVirC7*g8iZetkV(xZ2^WH-KKm^L;72yszv%kq6V;i?p` z+bImuxTb}S6Ax`gye@_+61}rw1V?vw$x+6&7h|X`CR&XH))%lA5`zwRUaE(!M}+ZK*0Q1e2rNRwL`Q)U}t&49DdN#7yp$>^zgPfJ;uA&pE?DUQ3r|c;%l2+h+|Sf+S4zr~X&BRUcGMK$r4676p~0 zQ#JtMR`STZc#DZ&xa{>d)rHn2mvWG$U89c?3*FbE)8&MXHyu?YyRHQq4mMTrMum{| z-hfG5_P8e9mXT7$Ux?^%`M1no0>czM-K1NpPO2@5fpM1yn0sx{mYmwaoPN-uCr zRimCR7z5N!6llpPXKWiJZ7^|`7Pf1;R5^Py59-0kjjgKK>SUyNxqLA5Q+W6v$$M=z z!h@gof$MhAPz2pMGJ;99Ky{-zWZH%xV3qy+`V9?kZc2&tCY>l_wt1V~wf(&JyQzN|s_e>>Zn5&S*9j$!+$aQKBgYs5??s?+e{gKmo88BDio%G%ta z<+VIyB%_?%of)s))_(K5oy$qPclPtWUkou?T5ACg$wD|X(nsu8O8k}_y~g(h{KmmY z-;Jvo{=Jqy^cs4vy`Nx$gZt)L1?yq95aHbE257^C7)eS%cgAu$2j(0sbix~}J{jiU zKqivXQmGxVk|^pTXWI9-IgblVdb`TW+tle<0%zo=!^>MJl8v$zt8U3HI z_m6U3c%}-4m1-^(*?kWwu)NBxmQGXM>CB;u(b@ShQ)xTlGs~4i_&!W0j>{cGcoLox zI-&O>Ljg6tN5osAM4KYeuw{CK+@&O`2{LgnP}M}{SlueS94*qLBrqkR8wsWM$-FLt zPs6c>6DLXanfz-s>g@lKu(S4t6!PMq?rgB;hHXq5tn-E+x4Pd;&TwT@bZ62ai{wtF z)pKW8i(fF!eMp_=_UD0Zjt79fYlAzo&#-%p%6MrDp$q7^61IP!0+RwLK%L5;q7gm1 zQA+fa^$c}KUhY);52-i-j!v9=?uoH??YTvxJ%clL7uko4e3}n-|M*70@;Qq z=Lgq&k|9AKR@$oEj=2L0Q=7Qb9NZ!qNT{-K!=wD2PB|K6w+6W~t}DW5c~y1vw&3ml zh+^B}(P~j_6gM>2HnTPE4p&>dh-LJpgib-2jhRBC&z3J2aX>mgwhQh4&t8*6|`n7{dwiKYHWy#my zZliZHZVVe75?=_&sC9V6zT#x1gy=v!Ur4F}7y8!fv+YZZQcySQnjcaU6bCsF#wf2* zwqpB2q)-gabq(ZwPziRN_7wa-%TUfaV7-5WHLl{3#S@TQGH)uVb+j>$#S!nE*V=Zk zPb&S$qnBU#@spIJq)}&Pm*HI_1j9604Rp@eymI&LsV_Ft$(Q2~1 zaBI`Q!~O-#bZL9re|=q4d9P)NtI8|?A`|4NQO2B8f$J0xS+-X%LZ~H$j?OSvUuQXE zOs6He$tl;9SdA4Q^y(ydKFsDcZK$iUEYb=}az3@A>E{T2HuctZit^2aC$fZ*fvytX zxbCIsxd~HZ&IbO>=Kxa}2B?vyx%oAIRzY_^{@0I@#4LeZgKT+5W8Z^CNu8U+otkrs zZA-J9h9uu)zr5k&(c321*4JWS*8|C@`O?*J8P#|Q(U|OfBr9R;UpK4WM>{wBUgWNu z(9Y>yzcnk&_)%aJxOr9ynVrO54I6;Z_I9dkK&Xo!^WvRKji`(kkS`3mN3)CVA8UyH zxmj;WBijcSQjRhQH7~XZRk({}aGeg@jVA01sCF?}yJW&AK4wgU{WKyw8(eM5okUGJ z!@b=-^70?(XoVzJl@>@ZuTU=dbaw3&!F(#oc?<>Ub!n`OnbtTxim;8SkZ94xz*lm zyac9nd0qI(d_oP98Y9`;D&C$__HJs=uO7kOT$MPROmi{QFN>NDm4FLaI%;UYc{MG} zF$Ig8Z=I_1Ng0W^mUGL+l>MuK+26s=t;5L&zX0uPncam%`;RwIaE6a&jT29l{h^@Z zg=D*?#I^(P{=q%7(T_!n@#)aAee6C*!gw8sb8A{q?MCXGZ!d{iV|ovh<;rgQd=MkRfR%toY-U_DJ z;=x8AE{c~}7_kT`TiUdiQqXABz9>e^yj+!P}}k+d|ALPOF?l2Qt(k%6|9%9z*l zA{Iff++jQi?&;}FT3RlcCDN@fli0sWwRg)+f1?x6&so=&tj?LFe{e(&v0bW5`A2a@ zW8P372$~N#i*Y($on)Ntp9uWYp%KiUV?as;)8qzwZ0a@${+ zlgEs{HmO^3vcG<7>z1~=RP-|v&~lXET<+=SMs6{XaJSC6)Fao^&6f1et@-J7p~ok> za(72EH2>W0IzHHHY)D}_SB#)x-_>S_AE#doS3ibke{uB)tv&;SZdj(-Vb z=T7vFn+@j02*Ra4<7g`ZlFPdgyt~!F$RHNa_#G2Iz&0~$y4)M0IQw;@WK*l@$BG&F zwEw5lGTBHvXhL6kX|>55WZuK{yd55WMHm|*k1deWl$5t~kg@r4W;Eu(M>?|mJ9_7K z?^C^3kMG?{nSYoeEyK7A)hr>UQ}DPKIEAw9kYS$;<^CC}Pi+Hbb9uPlZo40VYLF}! z4=d)C;mv8yJ2c_A_PF3eKhB2f^_ltc0jXJ~S8qS0tKpW%R{140_8D6?JNU zC!sAXaAxtbQkh!c6)wd_ZVrC=dj4E-0_87y$zC`gQ;D=vCWvXCX=Y`BNH)-ie zAAi}2k}L~7obkGQERoSJf)VdqGVA%)Jw9pWSSM|Z{Vs|F%h!ILiqVx_d$WDbB+ zWC6eu8-5e$ghuo<-{aJRkU~dmphZwW7T?Eq&nK21d(4-4lhS|A1-iv zydt}Njq#jB_FBDkrK84>n{e5lIGnzF_>Y|i+T~b0BoZuJe$dV`Ct*xjoM4(nIc&(1 zxxWtdCgLt=OFmR-Qa!0l#``GX6+h{f@{LJr=jstXHno#6P+*q6r`G3839A9W%x?vz8CtOpW$_95b;ET%bgJ%)P=^I<9Iiy$%7#{ zPv~Xe;NQ{sU3SMOaC&+l}p8&OC#Re)O4(sZ|RQQKWEFC zxspZ~znc<7I3zGYrVzErK9O%ga)Jzm_P zW8ZmR*XF=CfemC|Te&O2Prbv?fV|Sb!FT6T6c*Y28Mf%eqJh`&afq<2{PvsD>l5YfapP zIt1mb3pqe!FfU3LA5ekoJDR(oLz}$XDzu?eHU6~hrRuT+SZG*>c4*UM!MN~iV?0#b zxCcqu&e(^24AxSnkW_@eZybfeniSPj@FC^XkUPWxwC)j15P669CS5XN0cDICOMOVvTe?xcfYh;}X(IJsHDoYzgXLS|yrGEF90t-sfxy(V@=-GO}MyQ}dke#rB+s?kK zIIxf%tvP@tOf?H;dS)xxwlrQQBV^s-bknbG#0piVQMVBvh_hCD4ntEo3RDD76kMC& z4sd_?QHYECoyJ_sa|$xumenTDB(L9-hhte{7gI`^v$uB%L|%SkOA6t!OXugQ%t0dh zDX&$1$Aez#c%D^!o6Y&VC-f5%mrQV9rP&auUzyH5YmhDf(_-0`^s1oFqw&Q(T_STT z{C^S2ydaUcUYo=A0$QH!pSU(wO~&TJl=s!#olg|_L-Ji{6n{Vu+q9KT&Qkr(G-BgIDd{o}-#x?UgN#K{4(a+Sno}Gr zrPc6MRBNr6mQY#hb!^Ac;E~SWp=Y~G3riZJT#Z8;B>sl0-Io7a=CW)PEwnsG|!b;jT?N?V~!| z?eHzvQbycey8yc1 zr0;*1jI`~;Yd5ZI%Za52GM$@DqZ#LgVAN|(RVbM3jafPkrT(gXknL8YEU_?mHMI87 zchSOYxoZB1`z^D=f+X?np8jFq__Wge!z>TIt#On8r9hj;U5cC}zixzD(yb?BeOIpo6BT``u@ zOXImVNFZe4in4|>dJYBKocmT`;);2`>ES-GI zVdLA1&$7S$-ow%_mWZOkBpj)%-2i)mbqPn7dAqyZGm?nU^&TO)?&FX#(9f44an%Yt zFa{n}LLv9$e0;_PWEgh*lian09_p|hmgZCiWwvtfygjq6zETiPk^(_E;~65D zwdEDD0fY!c_dk@qR%CsoEILD&C;@g;tUjNH=ql}a^n7l|EzSc}U?N}HStN$pZ#%U! z&jdR{3yULtU_9LhQ`zMEdRju|g(>euTLoiHbtkKX)lf@S6nk>S8X0Y!3zKP){J+5( zYx1CHKMvJ1j`Er{<{{|EUw_;P6a}jRoY%KM8VJN#^milc-SJQE&4R@BF@Ub10pBQz zOYY{TsUrz&!uu$a0UySj({l>?q|VN9_EEp4Vhbm^^WN+(hMl@b7pLh;sTxrVQ5+Lt zPa-JJty^VcBtf`zJ&MDim{Z-{V6sM*3`4wm5gTOB(ZIJjZOnKV`y;%NO|yGMyO`4) zjZ)_Q+sul(I;U*MDjk<^yRf{AK_{d|WKHP~k73d}HMK!(M!b}V#Dvr7gw7rVcG=U| zR>tCrVh2-!8_@THev6)Ju&$u;cr_LxTjjbg;j{2WXU0{MQL6dmo(b|ei^Y2GoDp4& zb-u}xV11*EGu`l?lhkDdqt?>#!Y-+G|5V~5i%c~+U4ArijyYrxs4VKN!tt<*+(pv& zadjw$Zy%LquEBdZF2}hfMA`B+zzG@|2Fb*GUB~`Q+{N zvj*M6mX=>~f=TAB4<~{{OX5YxCQV33iJk}|l6s05xUNI?oP5Owere7LFXE1jR!}Ta zI!*UuYAXZ2UYbuHQRp+W2@tTl#kOFhVg6$r!`@<*gmRC{5yLfYR59Zr@?K=O&M$;iN#EakP*wWj8m2>;Y)%@50`!aR-aYFnb#<7nticP<&SJfqWf z!?2%re7^+9*<&5`CN2-&319ypJcHLyS4|HVn}_z};;9SmD4AwwEmS_beMrbmvOH{7 znQbV2ooG7Dn9i+w_~i2-UI2_2pT1yG<9D?#AwqWpnRGo`j=?MKan|YL>aId5U`0_g zDXf&Jxn>M)nK(;$15cZg`B2MsIkC@afGKX54HcYcGNdxkP*+T6LY(V;)i5WmGAHZA z(Kod1h8eNft9?%xStYl0&vodC$e*GeRykw4Pn|+~ZlH2D%Cf!3ogq7;pzCku^3l|p31(ZWnMH$g zT-7A$VxnWnz>AeP>xdZP=aXj(yiRrq_w%nF=4gERaO<0ON?WxVyGial!w$%xydAQH z5%#_&drgJKM-JV;Oyg8w`DBB16r?nLFI^b+JYVc3R$YCoV%TA!aw%c` z#Is^@*V_}&x~k1M-L>4WISjK3+!$|d)8~lUEkw&C{<6r?@g7G?a~YrhL+KIk&$v{M zR+N~1ROg`V{{ZND&BV3>-fpIZt_K7jFwz3&wCI=3y_R-h)wzC%JjOlV=SF&TDwxrIBg8@5O6V?y=YzKoA@9ek z-&Wx6R5*)&9+N<4)oyPeED;`jwFoX`Q`05N^q~PnL^x7Ca@@x{Osr$=D{1j$ak|#& zgf#FOXUVu^>y>a*@lwmU4K3%TKZ@jfj*oiLQ9w*AaphK(gQzCI$%fnUR$rVREf`d$ zdSYQH^?u~TDfJx)EkxzvFXO~pw`+@4yJJ(i!5_zD%5LjEz!@82PNL2d9`1F<7s8yw zwWdCt1*0UdSI{kl2N&z^q&WRqDC1sCCAj#S@7M6LmCoq`l3-Dn(E@Ytd zsp9sIHc8FrlRYaQmuRd-sldtH-*fcS$=HJPrE`ERK><&J6J4*m<035$AvNKxi_rQ2 zo|5N1{re&eu;>jG#QWeh){qfId{*&iU^jsp^h_hj1sggX*?O%q^bFt4KGaghgj?E( zC`2#4``c>jt@O*=dqXS4S*w)Zd$otx*j@qZ^En!&1i)SY&qM=Zc0vyVe!4paxXq@i z=Y#TU+Dya~yu)$ELo+>^1+eWvep6GnK{P;{6KjPY`~EZ5DVO;iB=}rLV04vi{YGH_ zgq*02tee>OOtI%U@Os)#Clm&+py}VtN>+uD>P~Gm=4?P0UtIO^xvonaNAbn2zD^7y z-x*c7EqVYfRbstK#JhWzCe)aZXzpc(CO`60(@}JZe4t7zFujv5T-JwKU^BFLlZ>hZ zzt3`R_S%0;v32$@=L>}OU;-82HKUsKZDcpA(cm8nfdak*2Vq}hU=cskC+GL|kZY=< zMRC6Zt=Ya9*DXT&0`XTCUZX5~Wi0Y^@iJ{x0@EM(dM!TyBQIm|TVblK7ThuEIXTCwtlL4~5|LsmFmn;_;dFH`G zx!mmba@4D)Z^*ICvy;8Z4|l`|u}wB|qTtnrC=OibFi-bv|MT_ZWDd`MzxcfiRf!t(F(HBl^Q zcex@ltkbwqWZ{abErdUr0_9+O4=)GmRqv97IM0Q>D|v>;h=`Y@c#IqGi?G#Zi5 z0A0&Akf49uHl3&&!ZEC1bQPKWrqVJCkn&y1WEd_uRz6V@W!7ghdesn3XFrYg3ZI!1u`P6(bQ`UexiCz^$ zNLRwD(i60F2Qr=>K#4aMY-gK1Ioh1@S%Dxm)AixCHl%`&RUW4)IjHOFG6&6#OzZ+l z35EdXR^FUUB9I6;PEd3?T0iuZ;N;sK(@Zo-5KxSm!cI=$S+OwhwTnaenr6M z7G~u?lBgn#Vs2!ikB>{akU}TZZsEGuu9fQR|jAzj-*^c~u{da-sCXGHbD#znW&!vN zn3$MA!kofg;RX~4(2+wIztfY^{%b=$_<6CpQ(A;^Yj!*Er7+mCGXk(s%*4{7-urR! zT5VK`3|CxS92qQ*=0wfrm#Lsrx(LGQJ*y8fkj(u0THY^A`{FDazNZ2LHwm7}>PvpK zg&tt?ghJvWw}avBS@dD!#Tk08Lu1;h+ar(Uh}SRj@6zuo#PqdZ_r3MG`-T)Lc}D*Y z@v;2mt2+o)#fmfUW|KjWe{s`B#tQl%ANQ7YI?obJ(-wF8DnUy-EX_1IGM$pA?bW|< z;T=e3$$B(>)VXdXLr!Nz6%7o8e3ew=PmI_ZS&pdS&3A&A1_&syJC%5O?U85aCbVThmMUZ)j)ef_~iNXBWT@bqFCL- zgT}m0n>Noxs5!BbYcWPcH-hahIgAF2AAvK9?+?mYOWX? zbhmdt{yWT3)8rfaJD&+ZI^(Omn0DQHN?beYVRo?L(-M8L75VQmMsPOIoClBR28^7F zmzL!_1?SSe;*wW^bUDWsY+Ca6QDeHiZJM#hZv=HX=L?eCPNo+y(3n}&Pe%lorM&mWEfOpSnR;;)VlR~D$|NqBShTD#v8@t!C(CBgpbp>imODV89a_OU+d zNNM~Jv>@wp?crkbVo+qvVff))Tl--?R|0MFvyAzrkXizdOe3$4R$a8AzRwn9#KXWq zH?#EoqA$+z8rZpd$58c=xp`QjZKp-aZjcXqYH%kA#9uFyb}5A4cx4(!-PP9LW6b#; z-5)tU2o_d*;1B(IGS?${zu=0a zak-5-_)fsE*fl9*n7(9c&W~DW20_0*SNAL4Kqx6y9S3vi&|zlnIOO zIIg1n5~o~}R_I6Tr_kPz0PKxo_0%AjEg%k3zw6y@+lEM*^IMq^NX1Jf^dZ=xYsob? z4IS)HTvM@0sLL1`1-lOQQAjt~{aQv|1@bQa&+wljt-eMDJIMb>i75X+l*lJD?7mU` zlv|F79H8#)r0hQvTP_mkXZO zvCLiu3VL~lGEf&9Ov4=GvF7FmTUu^f?S-?9#FPK_s5-~gc4LNod2X$&{LzotA8PM! z9YrT^6-~Rrd{Cto6J5~R0e?{z|BBj@`EJ(wG%V6>R#=BlU$kYinOu=qN2-CpG=H!8 z%NwtDO~TV#xgb(4Xpr4~fJ1Cz2Obvfo1LAt2%1ikHOJZUJy$#Z8;hkSWevZ%tvz*o zn*HzJOEOY`nTyjL)%NOu`0AgLzY&~V|3*nbDo}6c&LR`Vt?1>~Pu`0S?z~!y*XVth zPUn}b;z*TGk+`6-&1upXd`ab{e17$z+RE~6ec!ka93I^@-(Arvf{n_J*HzqS0CvBB zb$|VHe=G(PN#mM3h+N%ddkpxI&l$R>{wJu63r*PE#VVJf%a{wUZpu&5Aw7 zb6)JV78=yY8+rrJp=r)*e{y?DX1(|0Ge%o(ip--5X#%2U9|CTDfRmf2j^zhz2uU#t zPMe$UWfX36B*v59!Wku{o;k`2=QdMHRvqWn&!(8lKMO#D{-)qGtXkR4$`d$25x?Bh zn!gS^V2{}tZ2>->%TzDo(if~&H!NQ>7S32JIef<^)BcHN)4H{{r)}z{zp7DKpMljH zvu#s2ZBEJ?rz0V;VHuwNFj6aA{-i zsLGJ^jqx#C(;CEZbQF65Z)m>Fs=E6!C`5`w;b6;39XfzHGV@qg4&d^abI7`~%J*eY zn|0w?GM8rc{*Pof@Aj;0+Ik_A-J|a0$|2RK7r;Wf{W<*r{BB;|Bbu*CKOnzUc4K%PO8Lpe718vofbvcyoH&zH}8+y4hVYi_yxA&!c)!GvGPaNdczmRhIBSz z?Zz!-z>%Sleh|3m4?NyZ%Y2}H2ISImQ7;g0bHzlGBy`RklVYoQ=C!zN5@lV}08BRS z3jh?FO>)dyw_hv84*y1Sai=Zr+!jb<)l)`g41Ho-AYI@dt=ZXZ;@$a7Z2^(|3q&p- zurIiMG!KFa-gzRs_^;~K=2fmHNnc&v3|uO}?fB>n=LSRSk&9d{u!%QV8%!z8$U5fu zOtr6&Tl5!M)S8>s5VpA!wvA;DwVnHKawP)4M_|nMglQ_wT#pj@x;dyiQjFZW8=_4r z>jp9eqK=HZO{-fj^C=mZ$JwWC3rW-hd_Ue)c|z9@%&&vAGQH|&|2_W+(_mjEw9kxC zQ{&dR*n z*U%Ba)B0bSst^3Gni;k$d20Wg>7Gs!8lY1=v^qI86KXc8O8Fk4vE#^%BhzR1qsgz1wjLGah zFFNzV`~6eCkTOWm;(jmsU!ODLdHh8{YzV4;i6z0+ziRN4lExD!PN8whE5&Ob3!(#7 zglVWSy2hQ4icC~&Zq$>T$#eMReqoi$cKnC{sCH{S5=c=@j3@wml^&q4l|ca;NP1_l z-E?}I%VF1XDADX{9e!c=%|lHSgLsUCn&ARAs2RWl{qKp{kMXUg!CGJns7@GbZBWrq1)G<1~%xqQv7wS@w(1lgic#s6PqE2^x-{p6Rj;#J=G8 z&8b7PprHvFbDYD@ zhnT0D=r#kjvs{oT7Y|gPFqi>ltE1{o(6phvr!7XiCsqc|!hrTs1y9z7y>NjNdZdt=ZV( z(L83h8FH#RE8%D*1b z_DSC#wKv_H-DDb2W`<3{MGQnYbuim*L?qVjA6>7K?r5~yowLFa1xF=+alP~C{B+Pn z?tp0s8w;Z=|N4Yqw^Q64m2O(JPtZV?=m(VKE(H^JtMPt5kBBR8BeY)n@NR;c9w>3i z-TCE~5(;x=lTb^xKUbq@y2eO9S@Qa;(oTrEvz1N#?8qss&94gLu(=nx>eF(4!ox9E zLBjkU!>)XGkmFrda8&?rn)-|KgQ7!?Q!GUtdg~immm&={B_EZO z{Q*}Ph!YxC(T(%5(A@D;PD_o+9Fn~<_t-U?S$heMx`cgq_s*s6moHvw^Pd7+%#26m zVIaora%0wjjS8MVtVSh38pIQ*(t@Pc2GsmatILP0HccMyrr+DGamcEwr^cBN47V|I z`ab&a)4dy!^Tpv&#%A^C2Gjxr=^0Tl{;(L{qw{w(msGLeoT#T!^FgE}D^yc2b11Me z#zXd|9zIhcHvqkWrJrWyaK~7(?8li{qh@2aW;%_}kSI6F1Vp_Oa2$P=X;;Iw?#zPC z%`xoZ2CEPmFj48PySesCs+jtYNMgyY7Z^7o2L2P(*++}~{|(_h9^j({gXIfOuH7`7 zSxsFk*gw+mn*^I2rub2;p!!oPVrHMsSH<6V7R5Od>t1uEy6`kh|0+~>dHPGF-_`X* zqP>9n^(-EGf7V4Kp%*6Wj+zX3MQ`^fmGkKATxAlBfgIK=fQHo)fX>02EZwRpQf_+@ zHX;CM2r&r8_hCQp_iMr0;BUvW>S$`=68HVSb>1{+YskrK&HSktM?iJWDFufGqL z7W6cqy{8Epe7vu-&iQKXWf8+H;%6u0SwVYP8PtwkU**-Qn$sIGMb!wZAO~2CQO!-} z`=djiezf1%pKFI-I2tv#a8^$<^j?7X4bnP%W=b3rQ)T3IF+sm2s@ z7A~HK6yZ>+1p_IM>{3?Pt@%D-ciYC&AolM|5Fhi7l;7HUg^h8@0s&N-Y zNr`_^WtwQ8+n9NIIrP@!)K}yF{NwS%it6V#HtMH@mK(11|OS`y{zC)zUToCZVd0FHZp>5^CTG3&d%oIkX>zjmId{YG%XSjfY@a8Vd*xX0kB-~gQ7ClZoc_i>sw9D#NA#+!dn3b~S7 z`dvw9(SBGxK(x%SBlhVlI{Xpj^K@!q=b7e>N_+6Cg?;I%3;BSevk6=v1{#j!uR9O# z7C4>Bu(i33BIkY9tr8@}3h^-1N=sw0f;ohbY-M7_QtWtN%-ilCT_wajpOkS{t|voz z5Ds4vXj{3tXRtub@A*y6=CHexVDWpI$Zl)ftQvEmcQ7!6jX!7RJIGWX%|%fQH@7BO z6eCi0oj5cp_t{1D0+-uIjCphQOmxj#WZt4!Pb?H4nQ=uBsW&uT38fND&pj=eB zas)e7zo{ejw&ItQxH=7C8Q}%FVY&sY5uOKH+6?HPPtPU-kDbK)W+<3u*A(verPT({ zv+N?07B#V3wmWt$9(dNaTN_3{evGjC!R-##IFdd{Qb;J@93pdhhQJT6&;=HPN?bNVA&zBDa3Esu^07bL2%0 z%W8w%23ceze~;@pj?QO<@8Q(W?@Sc>TIuhrUC60DvbO`$-mP+Z_C9Z=-YNKx%f|_5xp1tMw7um7$`FDCLV^~$_A^jv zV%JiF~8BUXQ-LIxH;D*0RcQsdIZ4$e1d3mk5yq-1QiU=7TV)sZP#y z6nA5_6|1?2cOJKQKxk%t^oMavi<+YNoe2~OsA=0q0_$#u6@&6H;&LxuERE1~^r87{ zJTqU<#K1ETgzrOR)CR&+NLJu--=9+os(TN;-|I|HA{^f*)Wv=bACcbM(Yj&Ml_m~m9xdf?-<4{A20TuGQK{DAz z^BaLbBe~J+aG1iux=+pW4tS)C$aRXRi>C=3BD)buE|Lj77(Rm=;qJe)e6SfQk^ku8 zcNks_3m~e;MA)C>|1x|4d>`&-Wq_-SpNkjDJELbs7&IY=t&DL&tqE%x*eP`-uOrR2 z49lrYKIGLOly!8xh%h zJFgQV33?h~uB6))l}UUmTf9r=FWRKFg|5jwiaf(Y&Kn+Viae4qkz$yvh1I~jl@F~1 zeRe43CM!yYM&nTHO1t%$e{>6x18EZ9(N1AnJKpcwVs1TusLW>lBF>YY_bbZ(sE)Mr6@`RQUU2HJ4& zZLax%ewWJ=4gcs8b!KC0LRN{(h)O$e6gUgsZ3MN)!=!W9aOsF5J`@ zP3)tv7;AP=&*)Brx?sX&KYTzkf`@i)OR|2T5+DnpwSW~aZXgHgLjF11rwI`CYisi} zGY9=s-!Mo&vwO`fR1FhvAmk?-sB>|8Vd{!B}uYKuGGENyAluQ=np;Ze{*_g z_zFFE#Jxxj&z6d~cScV%+M`~}-~bHNGvBsgSH^+(k+J~B(Gxg(>pK61f+M$^U+=^$ zHHs*Z*tY(DC6zn!ZoG_YUZraOqq_l8fhkZWCTI%bZ7xJ`98|j^9Ar9fAm&_NiOX}=l2~pwGsZ*cOo>)gJg%@HGTi6 z?(KXwcc#8d}S=Ek#$RZhc{{ixWV1JD!e_Nm1sp=aTtP6eYbo6Onf=@SXR_H= zFMZfU&K4qQZ_J#_LM0m*S;8oqQ02iMRJ@DeEKP;_pp$I*q@KuuL&fb$3HE4r&P+VX zi`Jj?v>7aFk>@|icm>cpQvhchjnyX%?Vs@Jb`3PRo^Y3xpRYRT7j?OcuiH=bejVp@ zh|;g1^w%AOq$Hwbk_J~CT3rPBX1TXplFmS36C?Z#HC-B^q-XTi->u=l1ry<5(>MDq z=hF#R_rb#$dIR0?1ROGnCYo3m>}*Y8z-uI=p>S3eOK@**u!9Yf8Wn<64Oufbb2!#n z=I8eGm;e0r&7?=>*dd2Du)U}qpL=C|GSm@K4{#EQ(fnL{Y${OS^dQob+C*6wH()uam z(t>m+7N>Sflcg!0QPhn+{(MKmM+T+f%rqZeB1fK&f5}JI3SeF*~y z711ncrqPCU7XGP4*a(D4&y1LWZ(JeH#FZ*1Xtd2A>5B%ug-W^w_;_Re=V&W2t(~%G z-}M5BX)tC(w;HH5F)VqzbXp1Nuhgi^7R7Om6lJ!v`_cY#9IsiE8LtGeS@4<#`4!{_ zlAwB>)$YJOt&(6D8@>_pUm^E++WD{n{ABNiur#Ddzn?O^sZhIh3}Bcf7GTRYKcgU1 zIs1a7A%Ztl_UuzTgm5|#E}LRRh%bib3z%MNYIh`y>Ap87j1=ph((CTe!g*r zFu1^>Wp2o6l6b@(7tr1^W>{ik2)RggX(mS#nQ%a+xZZl^P!vVKfe@sLZk{$LH9+V+ zj~zxdk3-8|%QVT1z2$rb>^zgL@t{EpDt=b;bgUoAuZ32({v@toPFVWDq=`VoiAR6H z-5AbJ86U*OPIX#8hC>oO-6tZ+x^tM{kOf_ zisiR$U5s8nK<*Uf*1C#pYTX-L4+F{^Y*<9k*nB+>k_-iXc3uk4>CrKck!>|vesg-g zT#&TAuT^RK_5Q?f}e0asJp?B8;!#ko`xk1a2mU$npZGMsUxDEZLK?1%bG z3)x*Tr}Gzj27N2p>Gj&!Z~1>bvbG!^Zan{(OV_0KN}FF#^KGU~YTfotd9kqCg4VB0 z8~Ie8*#QUJB#IgIF@f{LmF8B!8;PEY7Ko5#3Aj4$-kN6)4Y|GrwSN(L_sr)M(n_$3 zqZ$!{`eD)qr(>q3jibul4nyB#f9d#ee{~vKlX(XnDvsplvM!)W2gCU`5v=XbSWHq0 zM`xi05gvPF+L*!Rd}l$zRrDO;`?^j1lXSVS_l&i8#2 zIgUU(8Eu>%$s5iI@h;1{BFq%-gqKK=lzaE!bHyoo4f(oS^k!#e5o`|7GeBjqWAtdR zDp~M>x3x2X_JDVkXf}FeWLRJ{pho~&kn29NGT~_cc`L;iCi?C5-Xq8ECiFCWtwMdy z&%!LcX}x+ni&IXcX^?ZUOs{Ba z>&x7;uHPHUh?Olr1GKK$xh1s4%llFv#8Q<<`@=blPPV5r?rdyFAo{q{;e73U#0Bgh z1QRp@hhX#)nW+pUO5AMM!dj%gCpZ*$@bmG*HhVq#vWoiBa4lf% z{|>q2jX?_v^b9N-Pn;DQ4x9Ebl zh|3b_A)-RWipn2FW94moCfOvJszu)*Zf!blC;4lEX&-3=}5;6J$M5eFQD6$trCQ^#k+ihi7Ae0IkmD^pL@ zb;bh~i_z2EPj=~|{ zG(rTH?YwBhIyIr_lJcsdOW(fnO6DT;gJS#PmIa^z<+;7SNY!3A(XmU%vP`|W^^s9^ zuf%__SDL!un0Huyoy^KRs^*THOQb90uzonf34nxY#cA-AdoN29Ov8=&3$gBRdoJnV zkIQB>5~yNVDR8Oqfi}X{qq{e?DzR=~2KAYFXIIB|5>L@Pm9b*f_npHm%L_Mho+>;fo9tt z<_UT5examVQAVL&sL)ZJ@RQA|mzQ@A7}ldbXl&BJ7dlUOf)ZEf&|+A9PVmntzhKb& zlYbpUuvkE#n@PXVTCH}ZiGza3}ID_+fTUNi3wYXSQEs?IgNh_X+Yl(pEAVMYp z^1XBljOT^kX&{Ux=J$ak#gWPCetdRKQyNwr-o6(K>*U(h&Pw39=`+ibFsVc2`WRk$ zXOA#OQaHku)q&`NN&OIM3EMVAgat4WU3T7u+j*t zZzS@kA}z40EUHc>^XhQKCDU%YeX~E{o-yLgjt-TXY)OBUv7$l^r~qxfo;+;9MpZ9a zJ!qSO8dfj=`0S&TJKbG^BdvOPxn&#gj_m%)iupxH$BMDI@Q?11jr5(0JAYwLYwyoE zqC+{0svg{P?64GU(>K32?bo0iK(^2mT*HL(o`wKc8}Y1RZwHMZ+Sj^X$}zqDE5?03 z64RXswR%tWC#&GCVjY|$G^X~bFPdP&6J@QA(xK=gwcGIXeY;{tvJc*gsa@?(%z`L* zwn9>Xhjshu#b=(EB|WBts|NfuZf3C8bTGKy3~)FFuk1DwneLNo33xz3vOG?;#(@OU z8*oDWmhGx%uus>$Mf1RT(T6f&IU}rLiNyU(pHC*^@VRAqGmxJ$CjhCBM2DLXq9?Wb z0uo&vM1EzJZRl8O<>kRiL|QAZlZVVzWfyKu0su{)yh_yC3C|yF%_`C^HBCqn{VTEz z{Re!a^bH&%?jm(^n58(FOxd5s|HP}q%Vu2)JHhN8daFqRNNwLOLRoBLfD z1}>8~M`P!%=Y9%5C$2IygRBcEO_RzBSn}hyy_|WSYqXb@8bA)?ER_dxzw!I)BpP$e z)Fq-@$H+sfQR47QgVfrusf#+hX=>RmYhey&4QI#@1dlghc$NxR?vdoADU;znRTr|# zyCaCa6O+BCCa>O4O3&Y%6i`!sC->{w!3%4NM`B_`@)9B#91>BAAR7f+mwKNLrk`Isl_%+!0TFk}ClnC18QIgT&~`FuES2s1lXzq|{PJ-$ zOFyjA9%_5`t`WmdeF`YPM=#86EvphHH)!JIpephW<)p(ji?@Yr!%ASu^;6iQD;lMM zXU}MUc=CMA@}&03;nz`zYf5(Lq}cQF+4KxWuI28|-02@xGL{3=b@8VK9dvJE|5p30 zi3i#rJB`HHByqAx{I^B`8Qz5YOdaRhi(*OnR~dJvG>eG9>lohJc>nHCaBW}OdU!X| z$E%5|Gl?Hm`jiU0)1LJFnl=QV(>(F@Ck?$3G+x_aVC0c*oOBOKt-q8tP5a6HN|;-v z_R3u1WBzrPjr42(<%mzFz8Fu9jGPUIX&1%cFS-RQJq62s{zvyI;5cJnV|IiqySEd_ zWM@x5r2QK78o%jdP|6sTU;x@io&FfwIozpyAU&gFMj2t`B1I; zU-!F?OD2z8hq~y1>$Y|S5|1I6Zs7y`h;5d}^KE^R(d$nKFltsRImu@o<8YiEsjX;} z4aA;4$T1cO5l*&vCJ$Tt{fH(O&1K}Lbz^SRA-e3?!6$PT9Qgf!4zKMp4f9jg_onPP zIPIJG`Nzn{)Y02>QS7UfkjjU926)T(2{y0aEDa|fBab*Kw>L_>Q>$FVe9Z|Zq`s^r&b`JWiGE}1W* z08=AxM=AS;r!tst!AX3F8MGu%sO-O(*A!%=^Y*Ym6N^8w{}mzpp2hcLd<64X?gj6G zhf=S@{?QrBQ2J)_-kp_u)Gcj7&`qr&e~aYMjxbl0(5lAiOt1q~ml5L@UR(FHzXrgQ zwijhsKe!_zv@6^4=EO%hofoViICc6vsQ4&@DnpY_cT7=ZRL*RGw;2T|Q*--~J+q;Jpb8zeA-&U=x-tYcH(fAU5BY$9^glmg( ze5WSR;l(*$`%XoCU0h{v;?<4oC8XbG^pil=-AU2^#sq zCV+D3JdIRMq7;T@AIWV?y0w_ij-)eCEmgpEN-I-`r5;{&iL+LWCOjEG9&m<3jz1TF z_BQj+>=kcm?|kKKTr1$3$@RVE=&1UJlgpRf0QDjE)Dov(pXp)-AALXExy8>>lEyCb z{6=9MswwrPsrRxM3usG=#2*(V9JSz!b~0xV6KXbJ!?I(EL3)Y$Rs+inq6WX|hEp18|Rq?Juv{s6nbOh5YYI4sxZ)(=K zL^v~kcte9??Vf)O>gNCb{Xj|m?7A|Scs@ebArY>+iAUwjKM8X3tNPNcy5wYUxu-nL zocA*AiQ{f@?_RV*WdZ(C{p-Q|It?%E7h%MN&JF_E>@lPk2PG;_E z-dI?W84LOBJp6J%XooTCiEoLhMCr^cVY$ZX+&8m1_AZ4A0yh8kUp9QF8?*JJ`ZY;t zg?s+y^X9ad{@QHqvA}@6;p!~Cl44pBSj{COsO-4HSTXft>|dTueQ!H|zh&JY>Raa0 z;yXh@>T7>fJSlGt&ej=5_JNH~(2J@+E z!}az_$dQKI1DXB}>@hIkX7d&{{jD_(DU+N(hKJZFp+rU?X z)8v22Ef>cH`N|GIv3=7)y?=C=JKy#mYu-K<3tfGsa*2_j>HjCVKHn?jwvysio2dJL zfi9+j7n@eKa1{&z9FwuY)?GW_$uO7!CzmXP57B+EOp&Wr0P~8bb2=GeaQ%w_-$~veiFD}U)yYt0D#g7%lv@sAka^s6nT$C9Mkyz&U)BJFQb~4 z`_qBvjZ#+^6F(9swB2q~>gXks=i=xtZxJ+@XBVp9%JsA3wBhf~?*9L!zTBbee_omx6jv3TWlbXMw&%{x14>+tn3kmEFtN+aY=O_I{7K+KuTz?IRK1uqDX1wN$Dzkrj}pBf5p#K|VE}d0CF5E0j5nJ@zdL zyWDKrvgrfEq`ccbRE(6I@k_WtgVnspU_o9@>s=5R)wkgNUmHE$%VWKN`41C-%|ZyN zihNm_3J8_(BqSEX<;ndc!fQoR(AzdLKmN5bd_oD}yDoSo*GFR+-E0bspU^+EYTg17 z9wHY^Y+3|EF=BdJ@6SFisRjBG#*EByi?5NFy0n=(BIWw`@2>GOE(=cYL6gllP zZCs7av{F%wLoqvr!%b&sm&x(E;_jL)$&Zt2d>JhiCz{`;eqhD_{FC|zdY)no``!AF zZs&YWxZ(X|QC;N(5Nj}qY($gT&=jb3<-q*72)MU;1bl~s{#^cT#vGe&moq}%$M+k6 zh^Zx-WF(QTUy{H5w!&AD%9JB*JrB7rFIntZ3>+@s$$ilNtR;WqgP#R^*pPbTgBM@o z<^qQXy|+JT=2*}l?`^lOWX$LE(ZmAC&KMplcqPrzJkiOkw-?U2OLZkxWMr5A zm;^aj)fbs6p@&~TpL>lv}o818A4U@jM%<8#mG^ZRPL^i&KBdvV` zgur!f1aID&u&Bk59i}O79c%VyfyQ^8g_-#QkG|E}j4Z+hy zhijFqXSnlo)ZbO}huE{@=C|EWXFgmHl6=brj=6iT<1@`ftFhxT*cfpxaiieO4du^h zvudv@ou#{+tL%@PbZ3hfYx1=ou?@*?sR+24z z%O!wcx%Y041;O%bO#+Ij5nmk0HW*U51Q{Atno@jpuG2@*xkgKTF`!xnOl*q)W ztQ!S>zjSB(9j86)*;~DX4HpDK_c7T@d@a45pE%hQnUP54A~N(Q+^r{arc@ca0YSoP z*PPMGkeknPB%o&3*@x;9d~bQI;*~wv4jip3a_##AJ{%N9R#agr-<1!ePO$B1y@PT^ z1A=$-ZE26N%x!Z&nnk3p$lJfZ))usfwI=4%wCot|M&hR{0it{nVC3= zRtN!X`0C3CxPWBjvnX?*QR(809#WC(m|FD|i{zKh_|;;MZ{ClgYZg0j>iGG|Z&);X zxAapL=`kuddI%rl5gPhn>%d`5e5N=s;AsfAg7|1^nulIgC&Bg>Gt+O|BUFaoQ;{kw zfld6d&@GLH_kwfK={13!ORg_fPyJ<|KdyIKymO2DC;i^nuhh>iu5%@!k>`PJj1UC3 zvz-IR2dp(KtSHqsb-5)emj4Q)JDtY)!Bmz_U z>CPfq&pw|4t7kV%TnQuDkf__&DdPE$4l56^R}V*h?oI9}w=bml=vJB**k4%meMwb5 zQ}ZUvlbXpPWuP|(98`C5$OjjDvd=()@3J6K|4lM~yMFZsX+t^x>fYLJj*s61W9CH; zRuxC-gL?dhwg~#n5=geL(j%YBrQ^iG2Rb&PIi9THZbCAY&guJYf^_WJfhUt1nnvAH z9`fnbiImqm&mW4Hm0dwEH0^eY;o_Uzu8GQohOVXJk^a-apN1_qTrU**!61>_fi1pW zqv7b&e~aKSBKJMveKE6}n?WBR;)T9K-W*uQOQI3b4Y0aTloOi@-*0|VjO}}9{?tph z-H`G7dHe6jgWlM_-)q_V>s}UUl0gCaDbW>ozA-)qi{gUbnodkRhgO=A>u? zuAPU~j_>$|4f}HXRX_8@slB*hhHSo$S}8>|%g1RbL9mzvgDc_2aE|rt!3$}hH(}?# zp=SL)q|K=UKGZ)C`O$(AVKk#UktjgqX?JA`WHS=)($Pp$4%`{yh^FFk>S zWu?c5Gj)UNI?j>19<8ZcaDoDZ+nDdp8akZkP&X0#9v}gVtoDcL*k}IxSB6(=y@lS z)3a73uuW7SG&^dgMav-(o2W`9~|p=<5g z6aW09E3qmVun(7C7YFwJM_1$BEGd_8{2xz2cYqo+ za7V`5|Bvlxsk>|z`I>3>MS9zpx1SEJNfvuBwB7=VG{5Yscg@;5`kcu1D;o9ybdS#d zfx&NME8h?#5XvIU=cff*#X;&T2lYK5L{8+2=@CT0%cB=qx%svO14ouJ2-ogI<`TB= zJ-SzlU-fQP#yuVB*kG8fIYf}To{eV@UG9IJre3X z(q{%A)Sn%SG@lw)nYz8^oxNiJD$GWhUg!qXdwBOlst?vm$O$$&gLYo7#KHMDKwKJW z=KYd9Na|JPxTnOp_Oa)rs*6#)^7{-rw2j-&_|UK`qLK_C_Y8hdVA2%3cNnecjaUGk zQ%6W{Fmi+NhtBh}W00nd9T0&+${L3;hC5;hAt!p5lQ2)nuXy?FRJm>dx0O;Va!Bbkj;g)6osgj?I1+oG-S zPp@S>{^sgmKCJktI(Fb(i8da=jbx+WNA3htZbA*)Kunj2*E56DxcU&hO6{T-^A#^Q z+c#=Z5I})zZtV8%nBg&tt!K#BimL z{ZQk~5Nbs>!|Fq@dtGc+7czv&`GYVz@?^P>n%$t)E!yuiW;L+5wc@SGP1!S_ zBP$w<3AWa}4`|Mlp=$UlJ$}5XpQvdkVaqskS^VMkx)I)inU~TBHp0^GFNXidi-!fC zI9~J*QIh`)YG=GE^V-5YJPJ%Si9hN93IbfjfF!7B^@d7$d*oPLV??l@>61L%UA@$} zn@^05LSrZiz|@!j_tBmxAZoJCu_mr1A8{#=O7d4oUrWhIBMIKorJZ+@Xi}c*8C3F+ z=z#hL-=3}Z>J%e)RP0TtW4^$C>+Ho-N5TE5`Eyp=`i2iOwBQHC;ufk8F{~HD-+75# z2*mNbFalId@;f{#QN9N**r0E$-To9O+!#7h%du@15y%YB6*8uCA21!fNBeNyfS;=2 z*>3V_>-54`&1yK2(npg^KjpZ-^=PuOjl<`WPp!fJjH%U+)vM9-wv^JD_I6)6;qKb7 zGdgPG*+-N+WxZ1k3MKsQ|CJT-iL5|+G6gg65?RiTT7CO$a_xIl%1?$>uu*+#lHp6^ zKnVXbY!2QyP#Pvs6-~JdHJXp|;2+WaVpdW1!uYn$EsGD&=v@9FBF_#0201@g30Pe= z$oBz;PY>&Hs&o~tn|6~N^l4M4_{~fh&*tTMmx*cgeSxlxR~KGJ;ZXVcnQvlPZl)MD zq}^Vx{9bp&JoP3b{}!kWG#55#O~znn6ZEVoM&Yqtuq%iMsPBZqH+p_Vu6~}45(T0n z&C$ZGavnYKQSiSARhG+-odO>HoEHMB7pzw)x5#+x-i{CWJ@^MR z%G(R}i2fM>5m%`>$^1g#@0*D8mM@}`$y_v6ZEPVIJ8Vv;wze`RAA5L;>^>(}vNg5pflJcCv-{hyM-YiI2Hun_~DNOtQk4~&pW<89?O(w8UFGycsyVVeIn)=<~?Xpi(!UHwy-Q+BO`)NBjvpXjpBFfn#iXVl zO0CSkztB&muVMN2`ifLj+kK_US9_Cs$-C+(5vnmkqGlg3)Ft5I44Rc5V$G#J%d&o| zEbqXqBky0CGSQXX(gVxz7uS@Cp}vP^HWn|sgXKq=Zt7p_MCqxx%xf21jhoIE%H3i8 zM$r8|5f!uPfEWO!>-+DaG-`wyFBV9omhs-Oyy0_X zNMrGkOgIE_kn;y%YK;VecUW`f6u(k?a=kquXmP3aPy)&rnxvMkmi=TaDJMc8B&p(W zm&}X9liLggzoopO;^P8-drbnr#{(VkYbXa<-n;~N8l!N8^9m!CAz4S196Br>)RpNz?EVr zt3Yp>TVvl$WJ3zuz`RuTb=FMN?oFTdj5&}4+3OQ+45*dtw!7AlEooM7X!7JV?2=FK zDI$4WU6R*pf}9>+Ho2NSvwD~F^S9?azAFp^MnTUmO<#E#(gB#GpYM)YpM8S~hesZh z9Ef`Ow^ff$|&D}a0XYW-Ejmbsh{21e5!tLAN{#7CAyzkIa{qingy6-C!y+>n<=V3 zsPnZNaJI_iM$N2RjV1E|nnbL5gL}3XM8#my`4wv~!wgF7A004vL6_o95>UR%DHuX| zr=}i+i!&FyWPtAN{cX49BG}T>{M%Qitpqa`Z;`tD&Q;iY$SJcr-P5>IGbuX)vQvqT zU4bt!feDALBg?XFDLt)zM`KCK$mM@@*3-5m!Ip$ERR-1nOq^s>=dO3T7Ev?2_SXyI z!+|eK+&a>j^a)$OL=5QDg$srk+D(N33k-6)S-{bm54go=$>ia?yWZk|K)uazw{Coh z%u0PS#*;p19}~VGQhTO?DCkI4GPBT-YkZ~3Bwrq#K+y{~o*V$N!M(;V&fki)AxB~1 zY(`IY(`Yuos%os*Et$SHYM;&y-b?!{9U^sOOwS#47qwDSB1dpbNPv51FpvRL;7m*i zzC*BEOGlV!*%I)<4)`IiHK^e@7-><0icD?+`=fPoDz-UK-bs5sMKQa%ZUbDKw5h{d!ycLzVxuTC$q9S=-WO=KEjh8tJ%9bVrS&0$T;YEoIH`wl=C zf1wOJWoZi#7AZ0l9`g#sWFSCp@rMRtQQMv{h4A;k*4bWdb{oFaE2waxBKq_eiCp$gzw&JG z->~PW&&rxx4vwx?JTW%DJ$7>R`C#O_i`^oYArcnS-t^p_q}F)r+b#bJ(GRT9v|d?0 z7akn*YGZ2@B`nIkNq#tQK2?<)j&>3`PRY(-Y0S)!;#$I2_zbn1@D>xyM`8`^5F#5+dm5^Hp_-_R6Da*)Skq6c)qP9^-~bC{j=8K{s@8EQuLf^1-P_s? z@jUX(1~vS+R9DejknrCZNzbOuy1D0&(1$r6 zymztxdSMjqIYh*}txT3J%KUEI>#Iz@CtsgLemDhRzLX|m{=K@`F2brXD3QoB)lgU| z(#hY<&$b?w@z<%DD$ByNz8kx{ajwgWe2`6bGiYPGdkm)Erio-OT>s#sk72l)Rdg-!&qDE6=x%Wly zdpqLZ;Pe{mfxwfoYb_W`58I6s1d}kx$@ZwD;2J~2lb~&%!saQSw<=j?0dI@2=@A>w z`i-*;l5x+n?+yL&TiT2acul<>SZ2wS>rtPXxYqD4%y+q+I3KHpYfCS}~GmwIA1XRdxO(Z$d?J(U4oyz;2dL#&x?n7VfY6 z{(^d?8HQtPWNY;}4}OoTt<#J+zoV@PJ(CsH$&HQ68X4@1b;F}_lnllFGBJu+2ov(H zw}WN9L`65x)ZKd*#c~I4Qmfa+nXE)+Dmo1a5=#sYzjF+vfN->FBO}A{8+k(}2Vl&S zE+I<e8*d0=*=Z zr=PpuzMNiTT+<(>z->y)Jwm+dWLzL`xipR&NRoY*EZ0K%r+gVhtEh^-!rH(b`8$dU zsx;Ag(JR|)zhA)%ZRkJ4R;9SSe6)k855c6+WB?Np=l0=}l|AA3O=T-8!Hl4Z_%vMU zh2XxfqH0A#z+DtslCq*aU%7(lmVARGN=)J~Nl-^3R}X~nhs9lT(OnJvuI5%K_0J{5ddYD=#mv zq_&YHfiY3uG%+j<2Qsi#kogx(@*y@9H^y{AGakyO9B!H*lW=%!de>!39K z!{9Dlwv5_$V}<=$&Rw!KApj`9&H~RVPgF8S;0Va1KHw5{CM#eYmPIBYeY2-!FcIIy zW#&8o-mZIp_MF*lYBEnfCl~!(QdcEDGSeSiah3CXkYgA61(Td zc=GBm;YP>SC@KJw7AXUj1{PT4h^MG;M92U#u~jn{y4fs{pZC>=arxJ06Ej9p`faDk znTvs{1v%bmLH0Wth#$%1G#d_sQ!d$?pDO#J)rfi$3Ds?(XWQibg( zxq2j+J2U_0SgoVoz^yBjU8*Ow=)@z2#z4JtR%9TJfsJ=+69Rmih| zw|8)$3Mx)fr0RdIC!!LzsgUY*8q<_(VTSELm7`;@yvEv93c@Trhg1Mq3l*Re`73L&Flnko?5*z; zR&Umb%1L@Gb>w)K9VM#;Wo2=ROC0?JApA;Z<&v8 z8^|U>mCDKr&eO6!VQVCaZdnFqQ`Az>Ri-+hsTCqi)7iWB+tFCiJjkBF;7q+d?VsLU zOEs$Z)7X)`BRCtEhI#~B7!&tdLapR1OZ{$lB-Zyi_$SnCs4jbAzK->HhICjxI2&z> z3*+dlaRV!w1;{2gr>6dWX{<0GXYO42_0RtB*NN~900*ViDHeWg(gKJxsW%BT$PbPi z=)oj)BvYS8hvt>kLUI4+Q};ab2J`rY_69)b+AXki+wDdM2)=g0{9;GhBg^+@*9JzC zf6>dxvKR6F*n%u2^y_nVyC{+6h!V^i3S2xJKd>El*iL-0JRCDbGpX>o9KhuqyQ@H6 z=pY6Rh)bAL+V;4hAfm^c+Qz6)bx?f|H$SE%mt`$!`_)tyaC*X;_So>29W*E>J8)r) zMn7hwtt+WH?5C7^mwEr~ZhIwaq6MXw^ou-T{(^aBc4GO`_@O@BGGjo3O(_gJJUbua zX&j&j(x#A(S*D(>F%pczO%j8TzIpz!>GSRWb|Lf>#=jmk5WHAAH*mG8j8gLcSd=PS zdRbNU;mLOr|KDTCB`OebRaWJ4Iz&Ef-v2{zdAkCyo{G0}dag{K6%Fz(kGKPhkU2aB zVh;yL`m76vf1V9rdDy^p^27>nU)UEz&!pInul0WQjknuOl$By*{ycTbTv&)_Fe}D+ zoV@x{I6uNjn?ZPIqQ%dfDAOQSX}q-vwhxXs&VBKMrEBnm#;A`in_SJSFJj5R;5;>& zAQRL|_HJ4&)UT25%fNqs2jPcze2zVC#s9L&h{)9|sU2EKrd|XBHx^i`7qQ-4>8xa| zd?Rc#C@&y4KlyBXA|SU$X0k`&Z?~K^?XptQKRO*UHGneGVFk-4l&%NQ#NDk`>YH@h z$U)`RGs*whDVXn=*v3vBo*8KWv~#ZbN7u~xFgnfAG3x&)I?K4G-ZzYcw3L9Pz*I`5 zM5JRV($dnUfYb;Pklp|#Bn6};B&8)bnn?~&Kw6rOk{E1A3>f?U&;QlloEPV_bI$YJ z&wXFl_e%ICS&Wz>jU_OxyJ?1XD^6c{7l!!53Z^|+v@)F;c(fx_sz3j(gaxvHel#!M zEXOLgcz3!a-S3%HV&QD*#O;RmCWt__exNT4ZenoI=*%ckvgy!EDTJmr8zN44t z6riM+mg=SaiTNB;_bbcD{r8eRio7NC&F$Q&%`|)8e~uAyPdaApwWjW9`|rv2BQ&3n zvg{o(hg6Z-=&&8LW8h8ptkNyB5F4zQ}cxlsw^LWed24+OqB= zyEw`WcP$ZJsob2_s_M%317|)P+w!NnVeD z^3K{d4VUMXez>KtdGm&Y)v)mS`Z7^u&MRQSB@c2pPoXGg%48aAc=|GDgg#AEFLKv! zfXva(gE9a9H*{d?0;a9bkvo2b(L@}*ZfT{JMXK71+k!9O4 zDWd21PJ96*>%KWisg7VYZ<#&$FtzXL(t?=Qtl2yhbKJ6APG+}4e#rfMEwn>ib^&m8 z!lw^kC6B$xA_PG31czS&-N^<9fancMJH{H{z}b9ksWe75FTsaDzjw$<(|BKuN&k{5cSl=z$G zj^8yK_cK#Hs+u&F-PX+efkR$Bl%o8LRsE;`cBMV!>{%v{7i+Ci1~z-)9H-l_I~%=F zsjdH!h1NaTnQAU?X$u!I{SL8tDG?prADy(wq)V;xE*W-xq_OGa!GVm53}Tcgyn7bC zI-G2kbttS9-9!9F-cCN<+^nw~&Oh>FJ~F&^C*dt`=j0pQvkU7c-2Wa$%N`D^RkMVzns%f`*K0Yj(SRcl-8 zx^Ijtg>Es^DCJP>^JnWWq#wVj{7F-JI$2&nV)b22#hc$kchvb?kNM#hVh`0{`T9@- zJ9B#ZsM8x+ylArN&bW1p0-|*q?tZLylQhtQIJ%wd2>r=LA;`WDfLg}v#wM4vm8C+M&%oYnmCO7y$fCe+$euN<8RTQrt7~cc@@yd9!oi~PR zhG;cby0<9RY=ONeFMSJQ?^dM+^3x6t-tS4K_KWN}EuzcokRak=9a)87h&O z?i?UpJS>^cdr+G^kmd`*uuE+y(r^SBH)`nRIA(T2T1XUJX^Cy4yc8My_cAfSwKp98JO`{`GuU+AkI*!Xv{gvV8hVWe)`exari zMn3AK1AT0+=UxuV`jM48m;{^|2_swok*UocvyYMr0~x1=2ZQ>7-%q~DCzt1FKJ`-! zo)rDMny`3keDx(@oO{(uLxd;>W?j@N3PPHzeRXVYo1(axYf>fmXrD0xVr6!Ev#8Cx z21(C*0toD&FJL|Tom9A=eIY6PmH78PFs5RHO&!q-XWkUJ4x+JH&ihsb5uEHs-F;y`!F%0`|wRx}-Z)iOYcK;J_tB@y1{U@9zn z6nEG0%ohkv!)wh^WoCYFiy7U+*?vaT7!-^dJPISSesY5t&@v{h0Qb zn$cTB%Ig6?cm2d<#o8?M-Z&~=7dVK7*F!>D;!lz+`nyGD>)=RM$VK8pcUzU6`c0ou zKVJbIu}FdI)oJ}$GcwjUWHsEhX5kfN$vQVDd+0P@S{X2fyWQdCn}4AANzuY4V||2f zerd;FZ?D?xZV*=D8i#m6@ZMx=&GRhQCHv=(#tfcpm8GF?N0+o@d`?fJ;e)6i$q%Ha z1zY9BXfla@n$eeY?825Ba6juwA;JR2`7`z$n(8C`>*EU99;YxmEG{@asT>lom@0Gh zK78eOIo+c6L^7iDJ&Jt|YWv|Zv4gDRNnJI1JO!Q-17vG(;@Q;ZCF<9ZH+t&S-37a! z1^#4n(dJ!SlOGzUWY%Sh_XmF*%HDB%>((FnFS-U3mC;}G1Wj(#5 zcQ*O~R7)&1O;6xcQVqRSlxvms>6=#tov**3hfRCt5lDwl2(Uz`5yIE`AVzowWFud9 zMZHJXs{=lg=#raTYP5#&WrF!nXN3(W+O5vR7eI}cOn~Uo_MJ*Z9Bwic@}2nIf^8td z(R%UT+j{vWU(a6!;w%O;ho0zI-WwmzkeMJzqh$)?9-ndY6c31b!8b%nHQSZK-A6Nk z1*!bPCK1-hP7wc`=;)BJ(4=tjA6W_DTeA3qB;LH$JJF=)ba_1t#M;4XVT2z&nHC)j zp*Ql|)hQcFkqtWE1Gy4_ahxg;wA|A?G4wE~;`wwhZ;dYPOD#_xbiJ}vM0 zz4Kci1J7kFMmT95#7-2N=>!1-!-d%1OrCcMC1O0!Qp#y&13I*E9KTk6z$R%Zc;|B6 zf#UQq@g!e!Wd!yA<>bJp4jjnqGPtjP57c)LEKUCBn$ql8!=)3^Wl9h(a%yvxEw*y1 z8S^;hDe{w6Get_SqttjAQ|@1SHXv(t??CnWT$m1iY_|_E-()4ocs&mqJQ(DAj!4rw z9VkyvX~c!Uk*{x4Ry!-?C6a%2%U#8Cqu-Y;E-l)66tDq?i0gB`7v)(29xBzJ;8(4x zib9+Dd0~`SIsWTP*|i&meR5e+cle&xf03Gl^GjZ}lH`K!hDu`$BalsDqEOzya_tV0 zLT#L!LNBU@*_K|4UXvDv+OKUTKVunukuVERAyNQRgt$VA<1T895{Quy<-lQYYbfZw zVE%d0)MdHi>J>uf52HjqZGDQ27-SQ1UR{Jmr8x_7txTR;s40eJ10+}u3D#w3zLPwaDxm( z;w5t99O8-MSLwC8EBA3($<6r|N&#MM-szP<-n0%)oW!P+gEliz1by4SD!oU?KD4LhLC0-x}QyX(w`~=w6^XH0rx=sP)eJ%YqG2Z%wr{q0SqLXt2!&TMQbq*wJXGspft{AVfNHlvFhW#8Zc>coh>fsuV*N*Km zU6@U>K@6*NqNtHSU65_s8{b1P`5dZNf|$>NZ)GewuuwGLbTWt)%GywA%@ zW7u2&*p>JGxTh(P2#Ws8Z+C77O`}hp2~lb)nZ=0smpY%;{FhMmGBfi86VmDO!Mgb( z*NPe?e%eCvabVKh(|B2~u}STnct)CPzVR#(KUamlL2wa}-QH&pCcH12UnGR~!B~mD zYpe7>Xn8=fov*6gaviJl$2hn|H2PR|Xc7xDwxi@6GGeTPglis2Q97v(MyT)r)<=s0 z`R-+)Bgx$@UY4{QZSD}yGua%p(|lE(d?m_#tQ6ajdx3GUJ9GxScXqUWTC!W#CN?(? z^*2eU>9`1{>5LlxKK8BD;VClv)S4uBJpLRSaDZL&Ve#MzJT=cM=W9182oSx}Xy4@q zmNlbGV`l`#@N+pbf>#78FCZ3nj$yf;<}sM!{JIIxDt%AtS;hNbo6e(w2olZg>nUZi zOABco@M$)0_Pg))U@4=&_T;mr4qSKSId;IO_TWtfr+^G=(urEIzgudlfmUXSKxB*w zv(uj_rH~g}T2LFSneie;_%`UAzhl&=_skrCJ^5!!F=Jua&@LMb=cg#$CYlpoXvU`R zn&Q8-K-)geFd99O%PgY)L&nwj(uutZQU-J1 z^?iWjqy7y}NFjBF(8Q~96A&Qw&pc8`bJ}nv-;A5&m+;GLgm>eE;3kKtPEO38BqhKR zKLgzih{mbrV@AV|=^Q&VP57)U#O0pm>j@oQIAkC6oZ=1aQ= zW1#mTX7y3cSOwDDYoBtIZ)K+|Hi+N9W{P#&ZICS)G6v-(%@p#1T@L9N2})XxIG3;P zkb2votUfvW2e^&gf=aah(=AaqNeTa*XMY9U%~x0#Gh$v8oU9eHcgql;5wV5Vs2%LEuZjs)ys1f15Oiq?I_8jHMHa2ry7p%2HkuWg~sl2&X_+52BaPI|Q z3&C4pUPe=O<3I+c-sh2C6-D!hS5lduj+Bu@zKV9|`j3pd>gSgLrRws8#_!yMQmG+{ zCqpN-j(JX|=lJ(#8RTw;Rmm`N8;SQrG~fC5I_bn&vUCc7zv?)7|=&+hlBthwxA7ocUCZ(@G?%{9rB3U_mRG*T^84aHKqzs zetg7G*<94pSsh9pZgmU;oK59_>t40Mo0uMzs-P&734-QkX8U5g-VgM?o(5ujfQ2`J z(BX>99Y6J)$uh?sMu*)AFM^0)CHQ`A*S?5jA#FLEm}{>EnsZax@(@^8^;(iOK=TdW z=0BE#MB-0sL1>W#r--MSh8zP7Y$H8C*2`7)V%sJTykzFFu8*`-nq%&lh%l6fhRz;4 zfm}+2zTfxby>x4bXmmA;Q=Ldvc~fD`Mz+`m22zeTJje&aDDGjV@?hbiuG_-yXyg2dUp5YUOz2r!8^%}4pC+<>=?HuJ?Gf2 z5U35;LmNi+SHkSBqG34N^1cG;_8V#Y@L(Kd zV8PiULCiR2M#iznidvIei+z+=U&y$Z-e4`*HSX&~5lfP&shxg?nx{ms^qwt-cGE~0 zLG$VDUoKZ=Cl$pLcC7g-g#@SGyHIRyUD38j@tOqlD|_n&{#r<_Y)rq>qC#{jeQR0; zXtGv**o~U&w|{>hqr|A+*r8xLVaj@}SH_veYS7Sd$FNt}l+>zqGD-dv!vUVZ+N1 zImg#zMS3I`!&OkKRnQHeT_EUU8xkx;uCS{k?Rqdu57T>Q4etckC~g(*s9C*J&b0}OZV3PO zuAxVy0KQ%zpDFWk$nuO`v_sx!ta~2zfrp5A_8-}+u_xTa;|lfs_`)8(w|aq2#rl7x zr{K>@!i|9iQ>&N%{v>qb>(Z};t{gp98iBjW|Bv`VO_>erQ)@|jPk`*Lw$dkSd`vjo z;R2(?oc|$;);4jvwwe2AfMu_$4N9QxyE!v11;9MS(e> zVuU7Ryaup&IxqxTADqg20YtpV1zNFU>yfe|88?$BeH4UpN_*sc>lKK{tvFa>so-!O zpZY&i zugk+k?SvQpJZyP?X~wg#7`P%;uf`lko{Rr!_y^eMyR$VLALl=sh#ZQyfrDeObwA1L z%dI~(&rYf$RJ#eX0Qy?Z@+vU1VwcYva=!;Ji5YxfPgqsY8k8e(PI}uXCYX&1^t@YQZ-vNlW_KEjy zu6AGyQc+f%97bps8pmjaS4sB*_?HtK=6RdJOdiLFzuyfrQ6`;@)662pfl1SNn+?|b z#{;Nl`anpY;_cZAl$YSVvY`{@{+Zjm7A0iOEaMIZXd3(bKm zGWhd}+R|Ww-Cl0+zJ$hu zx%n-sh@wCv{8h;V4=D{yzNsnRA(F&R@T5JKHyvn!EvyI#ychfsFuc9`INVM=2d?aT zw?*>*$0ICM+QZtSzc3NWrfgBKC!2(;_(2j)*Pj$C{v;SOJv%PmS(`!j$mPzsPbK@N z>MeX>ax-&$0V5%G4Z_}x2ST8bIAkAILMaD3Iq3!M-8Qg^K3Z0PY?Efh#hZ=K5VNkx z)I)MFm(BG1R1iFRM%;5fUHM(Xd#}O$*y;2!{gC?JTOd{sFjqIHn*+0O!<4e!H$skB zvr4GZRPoH(?|98Aoj1R=WxpriD|@RHH#F)mJRNNC+)T@=Qo|ZG2LuWA!4e&=BVF$+ zi?7EK#a0))Z%u9yQtnG z^=Z@w;%oWNT;`cvBkG>Ks-tBq4d^~a9pqFLlaCw#C9l$`N`=|t0|%7Cwa|Z&9SM4b z0QOe>JGIIRq}bqhVgOxpExd%ZvNwWsm5fqcMXgdp`{!1e@rbsy&_j9xcp&6&=Wmfq zzO8DG!f&>8STo!^ZgXd|waE0`L5uD(<1e*N(=ebdFppRxKIoVUGyJ+I8}csWtq+fa z_sjOy;6LYz;puDCj&ov)7F!O34)c1pxWgV06QRQ@jU;Xk2JK#eV~F>Ke$^~6u3fvp z*8cu}eNy_~02Cb-Mxa`kj9FmrOVaBnDa~{`xz>bP{&PGrB&98&qBo-4{-86+4y+k*Q+A1 z3;hs@J;)UEY$3S>BO30|n`_?WRlTGs!Xp!n7SNpJ41D6_+5hsLF!K4y_&f~FU*V3? zw+1$xnQ1XQV7w>Jgs*Vq*wXfz78K-uZRt!~L>yoiV8;RpH>PML8(`rK$EoeMs4`9G zp;!AxMfx+XKM1R6^_jO=@W7jy{pijkEuGr7qn7*^?Op6Le^T$lPqCAW4#W|ZV@9C9 z4H~&a(lTBHMS@u*|1YW_CrDaM%D|S0H1OY~zdXo=IqeTHKyFcTRoFs2tsgU-=j?^? zE8oEjU{-rp--p=M%|{7Cpy&0QlV0@Z1Zm89fF#-Oh_YR=wB|l1Xi-Cl1{=Ir5Hfd~f%iG>C&;}lYhz!nOnb4fzF)=XM29v_8`!tLZmJRjZB0gKOz~v z5YyK`dV7@|FpJUhnx(`w2FVSqFoAD&a&`Dy+@0!&@&qha2FVhx{ zk{XZMIcrb(0H+Omf*v(E)Sf~6A$BMA(?OP7iNvO_q`kxoezFRWw4u>;LGg57V4fH^ z?Unp)SSUw}CJm;zoA>~|v95xY&Na3jE}4F8RosSCbN(11XVmy_Xqf$djqL-as=lOe z>*Wf!EncC&6@aKU6B9_?5;Nnw{mM=G2}ex~WHcUAl7ZDCTmBa2Mq2caXs<8B{7e*N z2F%vE3-`7B$$!|PLD&oTO~|y z%ID;Evg$2H{TH|=h-ohJE71$u@3XE2JK}ZMcRl7UUtdx?x14G5NfqQP>^QI_{YMs@ zRe3l`x*5)_7TO>t$2PwkScS;B^!&*p{x(1MTiKMrtfRI>+U2FRL6=|-eab3RPpn66 zxnAYYBo}u1d0<5UZ~(1k+0dHbjx~qk>;C$yly{YWzCpjftGV`T8!CN1Wgl@9+E3eI zW{}IRS{ew6k@6*Hss#DVpVkJO+i}dw?~j&Omo6;^r*fZX@?O5%YO)r!dvqahqn`7@ z_!f83=bTIh@b>r9vnr2&2|41dL7nv?hb)(^jZiF^eX7sP7OVbhUWU94?Jx34u#WiY z?$##K_@qnA3=h#(-nH3TsrGZgweOz&4+p|2@z1O8I^H)r)Ko25XlLYK`DuV?n*QoP z?UFiLia3Zg7xpG6-cuOiYH^K@Da9IxKc@|@7%vJ*A89PVrg*twXNo3l1A zg9HS>3J@=VpC+aCo!$M!lx;jnTVvB@0%-7D<7$f$Qr$nJ9B+B!dlc#-grnvxx`D6n z{eFw-vKGCoX|_&#=wH-xN%RY`qFjjbj~#DT+dM0ak^G3iZ$r15*?z&1JedVQodkCf zJFF(pelD$-x$V7c>hpE?h0)g~2({!>9Y3IKYTIoCC6T%Aa?XWhPu2u1hC*I6M;6Dp zkm&_4-B@qsHLJF4-n;ZtH_#E8WZ_U6z5AR+ybpDj5qEO85v#E=*C3RcyAYlKNA^^D zl~*NQZsm<3H+z?2cdXE#=?14dOU-Jk%vEIvXD8o%c?C?wqq_xXCetO|`WjSMm@fD) zR`TXjb%rsOABQIDH!miaZLM`=3(;5!EOm(hu^b!nO5lKexYBIh2A93x$bsqw996#5fE71U352h zlg$%tdGrFRQr!X&)|=ZT*V0nf$qduK4=p3F_+x7`>`dG3 zHt6O0Y85n6qL_QOD zYNX*LQRmHs(502l^3I5UcSYNG2VPh9v|P<`CN=y&IB z)}3a$GW~nx7nx!m#iu&&pJ41gwPzIG;xoT=E~mx&Ni{>F@Kr!%(o;P~m3?rNpd4ua z?5%g}0{PggHJJl~LhOvEAfM_qM`bNSjB(R&e8lqlOuF5SvSRv9i1GJW!+#%6z5K&| zw$8-f2G|bUUgF|)2mbTQPtRm?pG|^u9=zvGZ5x|Fb*ZvQ=MieKUM}#d@}oQ59pPuv z_g}T#zBHoAzc2C)h1AWV+gao;`=g>SPo`)g&sxM6y3PKOY+Hogl2y@kX85+R8iQ0- zexEP6=o?+nt3M~zW3t~~t$vd!l;cx6xpKQE?E4<&c~WIEe9XJHboNG%xy`36hDx{8P5y&`J47Z-pn81@*1vv>mlO}qKufHx9Ed@hphw$D?>kmanU z87L=*U;mL2+2;xukmx@r1PLNwGuauSVDc1gGwRVfr>tnDmefH#+?hwE* zaZ^yX_zImwGLxjATn0cgNmBS|KRsLQ8F9h*}! zAX8wJjl{;h5Qr&^C2<643VAJX7kF6=@C@s>#Vp)w{I&MzixZ(*gG)EpWdF4(ArTnA zt(80Q+UQMoGeJj1FkV^x^*7yCSTD7(+`+E}1Ca|&)^;}IMH-0_R z4Y7k}aXwvB%5!s|CXt>+a3WMxm05c&+|hVAv&_;p)^jt_;Go*MJYt5v0xODVle504$JkF|;D0TFCibX-0LJy^A~SzTsZ z^>6ImIIZXDcH$A2&^w$Xk^hCcE(=!>U_D?qBzi_wW&BW>5OfPH59}hD(kUn}hiO0% zN|FHbRw@_g_f*NJWZclyD~8x7kC_afFbdz4oZdp(2?3Gc{Svcdo7Su>Th&snaQAe|6t>qoghfYg{IjfC zc$AjX1cMRDl_}FYa=~d=HkyUc0hoW0eH>;+SpYMt*K^S?h0IM|-f1zh{sqWv#quJL zUs=BW8gTE&CjdwGoKO$w&4@;XoLbvm4hwNWq7A)^r~G7n5QSMj2(U>ge%%tL!}Yo? z@%~E+Pfxb@DGC9~jYq3vT|wP$m4Wg+O>VW0PSL+ui~ej=HC%b{*^lctIJd@byS~(o zOtog|+rHYk6S;<|Tb%zhoYAhCt}HoXL!E6`n=EHLm8n$i&?M^xXJ!|X&!JE>tidlTOxL#`R1Y2pY$gN zCEfMvS)G%`Qc(lkh$IwJW^~jg?hkG2UunDWvGi}>mc=4mzqkSqNP#{7RBnYm=JfV= ziZr!B-}88;ST6bFwkYwN5${eat!VEhLl!e(lgLUgjv`%%kbRgW1EDIV97(Q7r$IfQ^)k=&CXmwsk)h9TI1fx zF|~~&FmT592F>T8IU`kRh;In>xG}~DdzOS(7#IVj-6f4_uby&m>rhY5XxWKmcPLiZ z&ZMx;$BbIV8Tqgf=uNINyRTdA71DLGuOWeA8vf@5Neg><9&0@DSYL739&;2lKQ^7Q z5hX((+3tj5KOe3Sb0th*s=;xY{C5DKYm)gK2ICGKY*@w0+vv&(1>%pCEcd5-<)ddj z*BJ$=xX*``&0Q1WhrEOf81rs{Jf6Q26FN>$@Bq>MwXklwlV>pX((zSyJr zUbfqAMd)h%P`v@mqgpw`)|Ms8)?HQjqXoo&WGj3>T2%H*^~}x2jY8hB)3#h;HiMSO zZ{Dg3x%;dM9#6X>(6t(CPzAo;v1R|vspVtfk7d2LZ1T0V`>#IGbsx2(pX}>DZPcTF zwZJv>w)FVgdx*rK=WnW)x@$3GTHk7KiPxyT)>NTBVN4mz+@j;Apb}gcN%lxI82Y1N z%frCbz$0J5|B~rCgO`zF{Os>{-l=!4MzRE>9x^M`tMVjHERnP3$p1C)wa(Os&Q5Z7#+{`lXaPyC3w-)BBzQ$lOs=AlLOuZi`d(pL?tD8@DDW9|{T z873-=#N*RauQKibd(=70%!429Q}~O(rCzUgKwMo{eq1(l7dAW4se*`fxRm`KoX{I_ zp*OCGH|7wfy`)F4mD$r~gT(;_4ywfCY7{_@oSEY0ufxvZn5MLT`BAK87MnA1PW;@{6AzvOcrbot5FQ`(Wg;xDy& zz|Dt)DP%!3eMn~FeW2xGRvwMMr1RfX8rADF@!(nR7x$AH5t{?K84V~;Qc&?3*0aU+ zD{?gZ!1liLUjc$QErQY-I9Ac&M+$3@h;7Ss;Q&v0MagbvrRQnZ1H`*Gdc5`AW}>Y> z6K@0?k3ydh(^ENCe~EgLOgOIpt||r;0I7J=YA*|cUf|pRjKQ(rq)pQiJ zx9dIH_Fa|(Yd0MMW|DcYS@K4hCk~E490|Wzg#UY56})Lx_e7x8`l$RRJ#R9d3Z!N7 zakwt3e}!SXsR4>|T1PUe27z97S&0|o9w>bKR!3GcuS8GN*G{V| zf&|ti_w#UPS_C;D4`4+KU(uTc!|>PFK%fGuya20b>SS|@W5UUDL1)u7Czz>-iq|id zkOHZesG4O`qjkRheP>PuvX6{*;6Dk1K86CRX1Gr?$B{)rhW()H0pS*x0;H#zxfOAl z|4yPr)d?2nPQstXE=jR>E>!R!4A4yLfyIUtCWq-<$^>a?Pxzc9f%>ek5b1c1f6r&V zJx}ya=JeC#ndiS`tOnD)sbM19{*qGsADKINf0cm^e{sQO_3*1kv;2Gd6PP zKDtaEID0ulIs#gfN4V_u|9a)*{3Q0olFb30Z6hE@wPVnM!h1cvziBr_B5A!=6)>}F zWj!VRYR%kTIAVPI8|Awxj4SVb3nh%Lciv0s~GEZ@z@ZJ8;#?Fd74~mTVY~ z3Lh^Sc+%k4&8HHjmg^dc(h*;Sgpq(`%}p|%UkJC=aVZNV$cU3FFst-IV9c~)pW6Z= zl{znwZ!8lp*79%>#l!7<D*iZNlb`uGIDgTXDFS79WC*>U|Bt8_4r2 z@)NZgup1`rKaQ7zf;T0AiTA)qM|EirK~kl)P%}vAJ>V0~yJzd=E+g#l(<^8V51`=& zK|VNi&u*BM2MVuh=2nps7MLs zMAiRIt*X1KM%!E?JAh4NB2*S`AsOgz+0gqWIo$k3FKqQ3dRy7`YUC$g8OqSv1#gL6 z2ldZ8zaXEr@e2QZ1q-zIEM)6`Tyj3!{a})Tb}4eL_TDyL_M`~Os`}8DxkUq03mUV( z6&Q7#nnKJfx~^Ce)ye4VdwB>7YJVsGWwZ<;f!fQi%HNJ4GC3LpCBbTfT}U>N013~p zB?Ox(7qY2Jca3Zhgxqma0i&-^HiD0=5zd52e9oFFaJ9k5v$rrz{3P<6Cqf|r2a7O! zn!-XT`z}?upX5|Xj5d+{5JsuZh>>LfWGFu=69qdqgD}TAaO-*Ti%rOdzP>xtNnMS9}5}Kj1y8kViHu%+ymFpx2Lmq9LVE#U^(@Zdt}_v|R+bYJ)F* z)If?55W`8wvG41fzp5-zTfIYn&c?y{&}irw3HX*0a3W}cOv-+#9i)zSBk0rQUa?JFEL8mwI8$ zzo9flW?V~RfZYQ=r#}0e_`sCrE33u|^@80?Yq*Wl>S>)j9-~^1QNlhw3YXUL62NkgIV)U^0=x<4sMSTD<`A0! z29Jj?ylAsGE`6s-GT0ValYLwyhrU*?0Pl?pc+o2Y_pYtUa>D$1VeSG)PSx%&aC01u zf)X`2BT#fL8_XhhsRos_3G3|;ugf1M|Tse0cwT(eE;ystc0PH;tI%O)kNt27^XacXV9m@#}4 z4)jJZwE7&b-|o_wm3hr$5&igUzKw-InUkIRYrOS68U2@rYbjCulxbF2&n?GBLb93} zWfQxA#JdCX#+&>(e?!3!0f96KZ4)jz@JKR6+0F~7s8GGk*YyN>bVqqc{i?O8uYKPW ztP6RgHmX+*KkE-2RXn&@HTWGSR6ck_FjcoogTy?~Z?Z-GN2bE%mporL)yLui zcQS991R^81d$N*fqKGmQO- z78cP4GC{!r-$0<`zU6c=oGif&wp9~s`V}SP{pG?zHn{Q@ znz+YZX14X&r;{I*%LP8AeREr#alYFH!7u|xaX!RH{;$F1t2#A1TNj)S9eU+S)T<}a zIvWS;bJU$W_5G10^jptro5SYq?{OsYY4yXBkQ^l8+Rci%FbhaI!OsL&+RfC4%Zl=M z>r_DhsTFC9KiU|~vr1SR<=@HA&NPabT}xjL17E?rZ-+4h6X$KTR;)7nn&b_FPtT;i zWf0VdML)EBZ+7;~lViz>hA_YG=|Altubw>8uhevmoU`sPk=8wQQ__4yte z%LKgL`MaOeQj1(Gg0Ywy!=s_pL{?;qTBg!Zo6BXNev7CT%OSUokNj&9f8UtJ(8>>r zqF!EAfZd+pVHoCtai*aE$olyi@Ua6*so;dHzQ#;kdRURQnJw#q?LB*4t^r(MNi=J?UrkHoMB5Er2gjR-fj4x)!QN{^E3ryjnIc+;`S zHC$sCGN;y+A?a@?ZA$t*Gxe@IIH0C$^K(S_Ac8k?yvuW3C9z#N-P0ck7yFZer^5F2 z1Pg!DTC#ldDHX*hIumbh&6}3j@p};gNDbUgL^6GnNs`IIHRiIM6K--W%jKFIc9{b2 zlP$`EQ&QlP9K@${$K#v;;{XasW-e%bI(dz4n!9hgoXjevbMkms-MdwV0~cLMf3yUx0aL;?Cd)F%(2EK`Wq?~_Gpes11Uv)lP$cq%iWqX($0pE zO1GZW5gAc+g$0AayCbUO9(!-WHbsyH=G0wsRXzjxEFwfU%v{D5Aax~U+ivHp8s^-r}C!7o8-U^e^iP>EoiRMpl zzb*)n=MGc}uiB3GMg-Zrogz4bf_GNF1?6&6Ha^c8926{281MtmdIK39d5)^Xxzvln zf=tw}xO&d2=)~rjs%j&;-h{ZcwRE>%(o0~VMzk~q%~uaFYkIyjG1Sz4@h2iRubmRH z48|E$+1`ueqX(i%GsSVNdJI&<8Gn)Y z4RS5(%*W}{B&geGAFE`;*EqFLLU7>XOqcKjieDFgNHlX;~>4P9=%f z`hA#5CnLn8QG48ySyM4mV0Kg<*^udZQk$fTGMLC*I5hruu)md5Gk`JBU(P)i-<$n5 zhVQ-K`Rs2+cf#lWN*ezSkF6PokO5rvT$OvPoo}pC2fEs~FfUG2 zc6aqkWtJ8oHug`vB)rA8qdz)ofn~%I{>ug{r+N<~zaI73M>yF_{rKkC)v8lBS|dBC z*Y?~i2qm=`v!DM>Vbr(Ec9g19(giwnbWZoq^lU0}kZV>S7jJbiTEk|o?s-j%6~TbD zG483F?`?nHbgT8Xs&A$c&Cs|4b#-|bRevB5?C7~9vEE;OozdQF zaPHP;B2>vCC&hcF0J}5uEE5YAesJM6LOQ^bU;aq(_ZV$K*D~>+hGhQ#R!|~Jsu^~IQ`qtjJ)u@Pp%*seqOaEcrp?rq z2dyTeJLl+9RCEv1)RWsDlh12hV|mSBotRsfB1W>(GZ2ZWC&GW6e>Y%!@qUzL*ZT9E z=Al&!a*=N4X5(@X%g~E)^=8Ma#aoQR+6SI>19lk-pP_-M6@g+GsGin>-A zG3CyY3ePPo&lE&tl5VqS^!#Ax`tzGgiP6PNk+%M^(uqs@Ss;fvofVfqQU6)Mt(aU) zpJ{W!uDIb@)a?Chw?zuG&5M6R8?2Rcc{A}gby%i<`)D>Zk-|Lwf)fj!(7c@!hK2cI zq5cR6r-^>d#9+uhfcHxlI=`R}VfZQb^RYBps`{N@mTT9v%KyjFc?PoezHeNsXloU< zN3@i-R%_2hhg}r4S8J0-Y%yaLwTqV4R=ZYhwfCsKiJ90tp$H=1|M~sj-v!7e3-D+G&P*9D9>&Ud44A6mJMj^^j5$H<)tX!3~iN37KO5*PB~6py(XyF z`c&e!;qg)rdWC*v!PNBP=8Ga0q8&^BKo1GGk$4BZ$g)r3m-tH!bMWG(&6jhY<#LBh z$;#rMUwba*pPdi#-)TULm70%VFS*fL2*^$-aQgHrmGEYtN^&gXeo{qNEeQvvAbwcmgjw8Z^**P!Ys^m)@kQ-h?VyCwg7*}Caek?uaqm7ZGpmL?Zmb3@?wvrO=ZUJ7TYrU%b~ zE!M?=I{B*Y+84pCmQKk0o=r87M7JKF#+82lOYohtHqO_x%rsGcY318z zZ-E5hSsuLJ!d2~sHU%L7xgdh8n9iD8BdTr1BA4QUOzd)}E7haIDli2$GZeFOk6-1o}eF_Idb`%kwUizAy<#ahTf(Ms7Y1Z?E;~z2_~%Jx~ZyhPaRl%gg{ShhkVA z$+$8?d|=b?GtK&J!5~W;!$eFEbYVUN z>8sfDUO43r%$OyJnwv zch-kVJ=x6E4R+lDTk4S3MT43gS=WuP#1lg&j{Km#a!RM}#i?C}a z*DDr+$Y+wvf88Qv)ZJO%kX)#&?)cc_#1(7{QJRym?yryITf;~1t_jzIB4sQ2^#FN+ zpPu(dTn_G4x1niktL=Qn_p6&a9mYqUgU=}H#}{rw1cSP#)ouRID4N@G7?fVAbmUu zI9klZqHT)q7Bf10K=q}8$1-CS(I&-WN+Q6@)&*k@*GV%=;og$l5aqbqYI*H)tgF@K zDO?Ko_ic{4I?KN;^Lg~u`=zwj$X|U@0pvaR_8y-V&Gnei zL}2de8^Wt><4E#tzG_0fY5mJ(rF^36at@x>8ZE-^@709&!Cd>PU|S%bZcFM@Axrg{xH5DeE;+VnyS|h7*Y8f=kB1Kx$+h15<9Y%N0lC38HaTfc z8w8b%GAii zDC#xfUBzF!3aq?(;7ZWOCx7R(qCCVaIv7TFC6Bl1jF zoLb)5tsCDtpFzbAE{#$*r>LJllyvh-HmW=9<2pTb*@|0~>NYNu{}l!{9w@Q9{R=-?;GXL{XuC zIk$ezQkj2$>q@Xh0E9|eb>vd-RRz(DazuWng6Q zpivRQ7MO7*xz{R&uaY-Mu1-(=i)RGxPs@KKiQZ@2kg@+rwwnJVxnOI|G1m5A2Mr4K zCLpa#cV!j+iJDmKoWr5=q9UV|xs2TLR<{WPQ{p9b7>CT>H!8nOcj{k|E1IjKt{43h zmTQp?@JKe19yp49t*{$Oxx<_a4qX%ZJX@bC&b(b`h8&1D06-f zVM$7K^C_tLKyGvcpFU>LBWYgw^Nj1F=k?B2{~XnC(&8P1DEhpFZyf6$MSqjKM7X{G zW#5vbyaoUB%5!fD$X}S@HKbcqpMT3NBfTwvFi!jC*~hzToiwVwVPt8;l-OU^0YX>> zYuFhyJbT^i=lJ!Di{fUf$t#Yo1F>ZOqV{3)@fz0C=mf_P@RoId65mSj^zK;}6+wsN zC22u6%ZM3_bniv?Letc76?x#>mr2K)Wy+M&B=iAfUPNvz%^!4zq3Xmb^aCkAWZ=j{ z?sH`7q|R}WXm@=3VsMhnL4$r45Y=ab6V7Z5&v1P3)-NW>oI3x{IICN_0}bQnN2(Uu zuZ$+b?72DU-Q#Kx&Q{0?a95`6F0F=u$b`>7+E+853H0zrmTe^RnKcVr1g*bYn@vj*l@cpqM2=Y@>)AYmsTzp| zKlqu!4V8h<2CvV)U)r_Oj5ljwj%eq0eeJ^u@HGhK&Ls-)W<`V%G=0!l3h#>ArJhh$ z{0JhsXnC4k;$6J!y@E+iCt# zo4P*{vCtt&B%LUg5MtF8h;DgOOZk1;HvWS>B43H-D(YaZxTwu$bY2fI7Em?2b+pZ3m@?0tw5m-;xB_GFWYZqS?O!`GP4lv~h0?m%P34kRC? z;#P7WGacSt!(YyTx-)p*0`+nlj-lIEDy9(o3))J7O)mQQVHymaG>*F)ztv(;^re*H z)$G5e7i+_r=!`6_PF?r*uDwZ5w$6UxDO~~Eh(LQ5ZS5${5$K+WCpJEedhL`AMgl=Onh{{X8!EQBB!>VCWId6R6zw%aVm4Qv;;$Th5tc>GeO zh4PZD{1;t}^fikrY9D^583`&efz=YGstI^V(ozeG;(n zEA)UeGWGSBz-2Cp&mU9>0-)Qw#=WGV--{eTfBRU7wG(v!Urpz*4vx^f7MMn^7TdO= zn+R6#>L6%!1b5Qu?{v^ilS3!-9PJM08LEA!LaRxI7)4C$O@T_R)WjN?08{8^e<07UDr!1NypKQlf@+q%;p>F@rw7~M>M4G-R|j~`ByE{C|TP^k#$_?7$%DKG1gU9o6^PD=)-x* zBK6;rk&toTr&={we;&_Ee?PcmO=5<^6lPtJ6_LqpCualZ9v3J4<2L)VG`b3vGLO_9 zRc|HTh_uwu+ld^-8$4R5Ppm9?7W2(3hMw*R?cZ*X{`QW8sQHFjScUu}v^M$t_F1ZD zeZ-NlC*|-98?j|5GxHnPbvMPilHVUh7f(`2HtiEWxg~mSu%~;h&bD#t6iy&*=e{~a zAwlkQPD1BZA8=%IJm7XrvuDY6dQO=?5S&|!liV;LzcyGv~!z{ zSf#e^tXpZSo{z!v1K;n{11F(JI$T{)Q#n zf&AkVvzivme#Ra?Z^}Hqw?sW5E@9uoeMYqN?Enn2$wVt9aWRu4;@$MWG9K0OHXAwk z=MSf5LBfZ^!uwaq*>=L-epYS zmsU_QvgZv=`G zRI#hrqn@lNFk`GWJz&G*D@Mb<{J7m&Nh-cl| z1-QV)=us}G#)7gEM_KJNgQSAp3RiC*VjI!a`q}JB8}9C&5)OVqjVtVZsHs#lm=(Ls zGh0(s=G;^5#58Hy?4rJ&LuO+{8eAWHx{Wr74enezT!Pc6>c0i1^t5Gye3JHp&qz?T zu9;8$Hr0g7A8~lL^JMxOaCXNeJZ8O-p6EyAYX07Nmrc)ckkuYFk^O~f`;|3?!~}5u zv{bK~IJH;41L@C6Y4Xp#0D_+@4m`0Cb?i#FNZ2yhxchaIRER%$YVU+1WP#e|4w#U7 z4Z6+=yhmVya1tr~St=);<%K0gICg{r0=#`-J_Sy1$&bN<_g&F58sY3SQoF&U*n5f) z%2P`+sISHyXBeT9d%0VgIn=a{i+olW#?t(;uP08tOpss3dZtY?5DWzB0*Q3;wBBnO zOq1Qd29eo;6ZHOEID@2;g^IJvMwQ3lfpywbW|r&W0E;Y|Rx(;v;s{Y1`|qQ_*az%Y z50^~!1fNYtEvJUY#6$S+Hw)zRWpm*kutoK+X;mL-hpuSn?R#VcT9fP9nCgZG!@!@L+VD6o^)F<{^h~Uvzx&#?~8P3`eSW=iJcHJs`Xz7k@ zMMN_M0l?Zj*_5J(#J9_GUVJl9yCjAM2^DAvfS;Yx1qw@bDM(5X=YofHUn`QSV_$GJgZ{RpsN;n&6*Pdt z#R=i9H&dfgU!A4d_GglhPGQQO%BVM=aAHzL<9xgJLQ? z_in}Py0`_nFSjhH;AwxU75W_f+;!fU`C4EeQJ^hd;e>yYJy3*iQ=i)R6ywXs#DY(H z<2++Q+`lB2F!4QQ0P?#cuawB`|7r?p2bmx33GG>#XRGfvH`JeQHZMVT^4kM~`s4`E zcGmVO2xYkl1fboxhz0Imc>U#**D!&%@n0a*Tdk1Mi9hC2uUvm2?c{l7%m{-aaWVQvOzK5+Z=pQHlK1%2^?LxY<@pF9P6 zG~6WqKocj@u?NFsXb+|?ydDq##sU)q7Gkn;*{@}b|42q}L>+{A>dFt?xTy2sR0c4- zN$PR87VhwGyhx`4DlKEEel0Ei&&UUSqVL}SFCL^#4{1{ozCs=NP^wRx?(evhtT8^v z6Fb;Z;myHxzQ>g1kV5I|!24BUAjNOP$}H#){}&7-igwxFk~@ezSsj_!D48uzrND&1kv72F3$zd|``9uI za~&=<5OV0Pt^@Afp&Jhl4-aH%FA>KAClPBsIceyb(pV-Q^XFB!FI4rib}ZV~Xi|wnbb+V>SsYOo(P%TMRG{$mOLbo2Y||gf@X;Wrqy0TBr73=n{%lnFm|*_oRq6$e$2@f^Wr4Z`1U{l95IF0y*#iU}82>&O6}C4RiUx(O(C`55 z-zs^Aym`|+rZRq>kyKsYhJX%LhU|05&lRj1EvlmDe;tjFmLb3@zs@I|w*h?wM+M)# zPN~2<)4Zl-a$UZQlI~8DzUAM$X{*VP?ZZ{Wt>IwNU!QC?f_tZ26N{Q|oQ*~T8*aKK z1Ht{5BZ_RSX`IOJ*u>W`?vZwfH^s!3Uqq1jUPgXvL!N6%n-#}Sywina?#X-*cFKAP zXhCly^Bk6GYbMw0;wau1nY?NMK7s))H;ML}6U!-)-Yg*37GkIU324;J;*b{O1pZYJ znNitHaq+IGP$`wsmoK@io5r^vFo2#@v zg~?6@^mf~=;q3Af$FhrS#0bgz1O zF^xt+v5m8st-gLwD4fAGaNLsXJxSXJ4CG@*-K#}J>lvw{1yKuj@`5VTXZK&i{P~z~W zf3`$qOh(?PiNxw>UrU4KleM#r2?}rRKCa)AN z?IRn#TSa{Bc5j=4xhq?S7TFACqX#{$8y|n8#RiWVK0=qtBSJALAq1(SzQ&0wi?DKU z+9j3;aM|~L*<{wXTTO=9s-@;G`G2FG5!LGSO^~ot;);0gothN(b zxKGIokd*h?V!r;kmOyl^_64;*!K*K*Hjn38R(DoD(LQ@e0ueOaNIBp{SKP+K4J)y< zol7_WcA?wC{dqhw6`wO7M4@yZ^_F?c7qFxnC|Di$qi%pC+*;*;!_6lr%SsUfgQ+&I zH@Cb#iYSHuA;C%6QHMGryx|3ATegnW>qV}_cx(6ulf{h_9Vr1-v6I<@7XSnJGOH6l zAAROMK~NQz7b?axr~+urL5UNsp5yKAMQdr+5lw`&>}mezVpf62 zwKM07=j%HLxy<(wy-CFjd#H}Fe*vi@KZh8VV`E6Pxu#G5K`PsN6igHzm5R5R@VaiQ z*3bN87*!C!P|GTqt~RH7_t1u+e&XSMTqJ+EcqS_BLJv{{2yYpsB&E*!A`c49OL%>B zU&enoJo|wa!Mtu`XuUz;$ESX*=|`d!u##z*t5@WizrRK3)J9=NRwvug!KjuWYfIuO z|DQH;y!ZAUYR~+xBaJv#gRLt~u@&lgvMZKdA}j9OVb0nSr4uSH*4x%C zWUSg)d2;wsan#E`?yvXypU3%+X|G3RMBvTT|-^IL8B3L%|SvM6!xlSb`=tbT+Kz+d&eE}HG!DLX~XKOW9x{_SWwp< zFmihP^(vDYwX7ivEC}7Ins%G+ex^{Z_UGM5Szgli+%J@0UNzQ$=3nfDW z@}BwxY;q;q4u1hJ6D}!CqYN-L#d7^%`jZR6nww~UtbF{#r%N@CTzhcXzZkpsVxnfC zBJA`qrwqSm+yK4y>qa#n`IPLQ)M*R~9-VL`B1U~@X}_z79g!bx)t??qlulci3&Fe3 zGQ2gWYNi#%-;<=cZEc!e`JMi{O#euHfO~S>?=?1Ecj+SV8#^0Yi@XO!l&p~DRR^eB zM%1TzM-iT5(rSB%S$WGf;eLJ#mFF{jbx-erM0hgiseZ}p74wGi+F=_81>nXk*1TL7 zrxog9Dh8riD%YkP*N)cgyko7b@yLjEeRT9o?Y2<^e{EI`zc3jpUV%(J>SUp%?npb_1z5k)JClChFzKI2E_r z^7W?e$VI*q`mouUmOMXx0z>ZGDeL&EX?sF~r3@fC$|4#j~Zntx)k2OuT#RThS(!>NiC0Y?S&Qk-^ump9yKslki% zMx4*EzpzzmkNVcs7?CP~R;TjoC{<$Fl%aP*Fh_mL!DfGJ!|)rP*c_kCopPJn>vang zE6#cT<6kI+Qoa1fWuNCps!|%_kM-xaS{xR)&$W+t`s|{3yH8k^vAM-OWv<3&+{>Rz zTR}-96J?o)ry4@jO@U|N2I+mMi1H-UZb!wVP9^b#+O4jG-=W2Dd?=bOqw#6`KNS_ z>(T2fWhEhxck71(qw)rafxWOpk1NmDEj5zIx8zm$-z4ZPEC_1cO2MKQMhmj!4=yaW z(q~o;uDFU}w^GA1{8;LLH{9`~Z0$w)qBV8D?b|_%vu(die%$x?8n0DTKjobJ zrztkmXHEKZ0zoK#Pydw1`~63LMut*{na;dW6CIc`Fcc~Q zAc5u!VGakjJFUu`MWnx{KfcGd{@~0kq+EQ>551#&> zJ$nJrv!D2V-u&F8YFcbY(>!HT78{#8>_}65*2(*94plbT?5En#?Ll5EF9k0~elXcH zI6pTDsB-F4X}x+)>CTvX{xx(&Vf$wO;VyA`>j8Y98g_GH3i+Lg(!Bkxu8J-CsA_TE3i;GD31IXY0cq zG`wmVdgnyzzL%bkQ=^BMta(J*2fsqKGi$-d`tSZlou@j4l2oNDzywyZARw~fOyzab z@0P-gq|2sN4f!k0wTkf7Xu=bOcqwxoWs8sD58Ok#8Di)6qB^D}B1N2q?f*=iva_xm zn_x6$?xHA@I>c!A%m~$*g0r&Uh7YFd$2D&y&ngW`dVQo3RlQoeyfn<+zMO7N=A9HS zNHML(nTb9%R{~v{EMC5D>2o5%ENHLfcaA$&YIvFxj&-oHnmKbm@O+^qX}zAiyalqHA%WsK$HTLVs}BngU4w*k-rhdsFAS4_9M3U)1CJ!{xfg#CB>7JroE zT`L~Q^KFNl(S!-nq+>4MRsB26=V4lR<4y~?b-2a{w{WF9T|T_;k9H1yvZ-W@BKs+V zv>+y}|B>uQ%wEnwLpP6UTu18}^VWTgMrC&JV`P$6EI078C%`b6%z+v>^+T|Gp-I@d zeHz)dcmBxdmJ`u#eH^nVKL2}P=l|btUJJ#ho`C-&!HH|*Bw9FUi}I@>as{5mAH_mL zu-RJ^w_i7mvTi%oB-HTULw2@if^Pnk|KZ%XtTI)xGf^bC!}iz_7-^OwQ z%u?L&-d)Q&2!WyN4c-&dCGrVb<5i4}gBi2U_E_+a1yVwNBcdf9S5ZO97EBoHY~jz2 z-d?O6q!Q?G@<^NoV(RHBF0eQgvV$?%(kxZaPrW^zR>Bg#Hd+SLUVRCuLHr;Gv_FZ1 zjr>vK!y0E!_-ag6WTRaZM^{f_cP2&Kn27FQ?huK2k?nz9_LD|=j$y}#n(hi5DqUogZW3%_unn<;brOj3o_O)auoA+aEtS2cL zQ|-?AvtGPh6yB!~z?VDrnQQL+{k#2pBT||)VOY;)?g4^?eWo_61)F_gbD9GM=xA08Aq%4($)HAyPYT@C%QKvb%-eI#@vu zBYQ#h%ssS>4x5|y*jb<_a+kfKY~5kg6k0~URFLGd|GA52xpjQ(G@kVZHcexkwjDvx zFEqkCnM>);f>9qRM(PtDW;vOvu2KD6LI%yMWgE>Q0KFOil?tHR4M-n@uG|vWd^s_K zVN4b9Nb10{=)73lK#YLDoq6xi7ZP0Cu=ZUF?1nh6q2X~EWEqz_7X4^d0qGNvAJLb6g+yAuVEX2kF9~12HSvY|%HeMp@n7{iP zdj*3dkt^x1USa7KV>GX|)xeYZk%YJ3P9FKw%Ydyker>q9JQEdt+N>CxolaDM>b!ez z<9<2o&kofw_vZfnB|`4&YGy%3(Q~VtF0vEOx1~HT@7^!{Za4T?e)at{)%c{4<~|=I zrwl*Gl&EQ`XiEY3y$oROCv{gyA74ZzR@!gsjQ`opo0hoMSkLUGPCbF0=b)DjRb=A= zJ(e&P=e2Q~*;QE^4$Kdn%))A0GUCO~T$0ub!~g9msP}crO5?zdGqW=@)k`RO^$8!R z36AertveJ6ap7%`N;js_v*Hn9HK)4Ko_f6nX%|== z2Sjj3gJ@7o$jOQvO%CfOEUH#F}2m$mMkye%$fu34s$|S%_yg!Mo$EyDv+t z9V?wuGO4gjWh>$T1|$SLGH)-h4z;!SUp$4(+^`hcLDs_CMex?zc->U~c=2I-3{zV< z-r(xZq>%grU|_RRb9T9$&@``ci}uCvcuLM#KS>z;~KCPXXBlA7tTs%0DzGn z=-v(+GNjoUjW}h^HXS^z9sjFbm$PIXQ-E^jp;8`EVq16>uC|mF2e>aRKN0Wxzr{_h zRA+T*MaP# ze;+L+@H@0$rhMMSt}$hZPr?hGOw5-;#l1tt{E8VziDQAlW*E`t1g8xg&mdvIa zNrl1)pkh;MT?M|go%g?!C*Bq)NheGGusQA@J!~Hx{^PeYmrAt3sT|x`TWB(dF=IH- zvd10AM3>AQi~R(?dfjzt=Uha)A6URlCW@P3Ry(KQaV#VbO!WfCznYm*7B~nvP->_l zYj*j7Bgr5Qqp4v&arAFVc6W;y_{r^B;9}uAk04e+5VDCIWAL|Z8c#L3WOS>oa4XlEs?&;%(6e=G{)5>oYw4#N1h*F0U$+QJ0}4Pi-l2BVkoIEN|1gDB zUicZJL_pY^_J||>y!6wDFMb{XD}7~=V>a)jsjVS*RcL5JpLV`m}#d;?MPCYQHpHX=PS+9;IOvLJE8LB zvVdEdv<>)Ars(4egNclekQz|W?Xu<>18-Kh{#W@7!Z$6Y6;dAj^6+18RZN z4~FCKNgJj(v#A7nr6B}4w2{1Z5fm(gBU_0W2or8ry+lkF#9HxwPk87J`@+vPMv#uW1U29_7k*~Cb|b!X!=YgUe79)J!mi{oRuQ(7wxLRB~Vd^C<6U8 zB*t=%7F`P%)D#?%Wq6bSNX#ca{VuF@XZaMIFRc1FnRw{eAYE!T^`sZaK<13xQ3z8Y zRRa#3;s=MWS>B^2pV`n(6ymr*%7xINuclY6_bknU#r0+@WcI8RM^i2FrL7)UxPP%4 zS(6s#lJ((ucoM$t?Hs3&P8Yip7GMnAzE!;1>UVjDtLF|}Tx0*Pt)0c`&@#iH0w0Ke_$$gQXa> z)H9IDZoa|D8EHoCgLYU0bw5SA2OvpTBRM4&BrhACTl;P)0Et0L+yf6dLJ;Tcv#-3p zZ%(O*#C0e`cudZ=uJ7tCatS;X=9TI1Cvn|}nk>fu9weTv^rbG|4U6pc(=G0L!d3H~ zr-%oeW9di*`E-s6;`BX!wb97>(DNc$buKS@lp}uKF_4#FHUS194A0DKY}%$J?)dXp zI3~R)EZD(#<31*YyB^wG_D|QwSOz_xjQOJJ1B~aX66g72%nkI=BJ|s+*uSzzS4Og@ z)tsStw=UPdKqq@_rG%&TzlXFDS@eaf-|+_MH$@;}Ep$Sr(!1+qFdsPO${tX9bJZ3s zne3YI?{DBJjGDaDedr%!|Hbt)u->}8kbYjV$MXiSf<+x^VY}j~=6q7?zQJ8dFDN6& zF$Tts9#-AfK%6lFpt67&>#(DQ`#fvRaUPG+v2uFR>8dq#l`QHJ!k z#$A6e^H<_O_<&so-G*jzVMp2+^RFD4i9Gep225hLG0|HptncOLj=hq;NO4j7p0X7~ zv%&kU77hQ9vRGz2A(}JyTwaLxAp$O<9HXLOwOp_8!qYf@MOkj3?yf@&*c3&^{?zla_BY z1t^V5ziU)!IB+S(KGSJXwrQui9|$HmPyDN(^$)-gqFd;naQ_DCZMh@r`PiR=eYTH7 zzi|%zv|c%~=4ZSF%AB1I0_l~6|H~PO!+#{q#uD*eoKnj5*qJn77UZ1Z{4lnlM$%=W zl>9}N*yb8Pse-^UJH{fdSOd4xXThcs(Wut?#6lDw=Q%I2lr$=_+UkFj!to^l>g4;8 zf(aIFF0F8PJ;Zl%qw2psh52o#%J0*ojmilD`&@0YswY(_Y3`WxnVoGx=C71}gALhm%FsJ1pA4F3 zAN^IXtB8*XYB<9Xc~^HdGJF|?iwC&Gjw|%+K!kOKuu!?YQb0kEpo@xch1>22KE+e(B#Rfdn1aA#)4+{_M5eX`A@BMNPQY19QoO) zc%%e1`F|ujF~ak4>Bqtos#Ys4a`hf8dy}ikSRyapH^&4gk)Yeud87sA4fi+y?OM>R?=>jm8lr?CEz0y?8(OvCdcA-pO-c4WmvOZ&^Q~# z(td`uaw4o%aiAc7>(wI)=p8@!&qYMy>ETCo2r?(XBEkw81%V>RBSnI=RarDODSeQa+$*KC(hs-q(Vr<)qUp?9)a zNHI0ql23bwTZt9|g6jNbFe~@xw~6dc+GIN>aR3Ye28+$%dNP$sYv zWfjWY>`V5S*faAkQhr9vIgvD}CxKvir|_?-UYM2OBe@_pX%a5qcVq31<(hwI>NWo( zxd(Yc1QS$d2o$TxU|^yvgE75*iloIOHF3mWM2;5VG|r<396$8Zw1XB+2YGE7IVj>G zlH=)y3fRfBaD2+@3O!=2`>mtJo#qDo4>*;DFwC^8;57fW==1QUPrs}*C&XZ^8zX85 z$A|HGQlC65$sNvQ^|atQMlUA+Rc)! zbjK(}EZ`@`Z=om7w5d3C^Ee==`B-N0P+M0`X0zd1#$;AIP5ZX~(tLHy^INIA-~7`M z25$|YKP4;~1qqaiPmgiA;_OaT;bczZyZz+f1^HeD_g}crv~f4v75CLl6CHKs$$k+2FF4oW)`tQU!XF$s)t~iBg#aEWtVkoY*W$y{N3z4x zP50_5#oR~b#PG9{k4l{CNU!9sb0DjUhOJMCqri5?H}wyK6Ca=T+NZ&^CIe3yH)IF9 zKlPQEzt#kxb3#U4)*e=_0cIG}Wn`y_D@OB$Qr4&8ecgp&cNpjiM;fQTc~zG~?}Qc- zM!et9fSrkz3$8=(r0^dS{?eXSbd2Jq_s&*v_U)q~5L%=Sa7Ew4oNWJ>*G0}E2LM1~ z+b|klhOq23`KVJ@FfJ+e>Jj=IZ0);8cj&DzD)Ab0T6(S<0P>9l^cjRT(#Ai27zi{( zY5|cWNh>4%^9pgGt-3e&O!Li7{jKe+`|>(0H~q?14>AR0=#3KE7yi(a+7DwHAxs4bG?<-J{Mq%5+xHu=}1p<5uO;xJUNyC|r0M%NYeR}xO8GCmI)0UFG3}~61i!g14HVVJt@Wa2svVKP23Kh*Ow17O=(sHZ+cT*?!lk5lRX zV&ZRtV>}GQPOT_OMSf(P(YRCb(ZmKCEoqzO`-4sr{`T%6KSh3EFmVNheb*KQ!D=DH z53r%=ZUZi9{7Me~>53}e6&ul6mA?@m@;-_$WMa*%SziEl-|vRfW0RMq_wId~1r%9W zUF3oU(uQ^(f>G(^l+v&LgWETFf(Cp`w(EYx*-|HWB}e$PXdd5%i*P$u4wdv6L#zVk zd$S6L5)jt_d#3~~9X_R7HWXjj>wB0lU}k|Y)Jv$hSgz)Z9$};)vA)0ekIE8|Dn(3L zP_^L-<0Rtg2ylEg65NI}#I$|R!)eEyM%RmeO|~)?S{smiU$4u=E&Z0{(oe1mytT3! z;tl5~tMW}}^fo24M% z_Y;T+{VQ1~iw9wJG${pPCv-1=_cfH>v2fr|5=yu)!}1>q7*pMBTU=HVT05vKdX948 z{l`PtY|-|5))I8R4CFc*76y)he$#eCqQHX5eHQouT)ozBoJf?X+-v)4>}hF~v(Uc< zp`IXBgZ+$cm)=)E2g%*wWGM{YamAnJyP)t*&)}=jE3LCC%vqlJ_NJu zI2P~vE_FG|+NF>0%p`=0$2O6CUpSV)-vBh^zRbY{AhJf*Fp?mI(E#+@G@}7q2z$e5 z!}`~%W2?9dl{gwE>?bbBJdq z`~8m*4!p1ns4}mWkNg(D!jokS8!OQlG8BwnkK1|Vt#7Tn2`q>v4+XDD^T%9HQ+^(b z+MVN$F*ter)McfxMK9rgr7nI%W?>>U+J`e`|05R&wS~_3?arFvIp{Xu>t&opY(Z+c zQg~ImW+$?ISa%eS&N>41wtYXE?>xDZJNu1S^X4-2Dn!CN`Uw6Di*c=Z&^M&Ur43u% z_saP@b92iD+XHSrG-9b2RGq1aACdveto1Lc&lD`Rt7bvUiPO2&DT8py2P`*Vilx6t zW2=u{ zFRxL+g%sM{8|$-Sbsd=c<4NK%X)>igiYdL_}ltyGW~$3 zD=TXEg=FEj>^l)VR9rFKR{U(d@6JtQRzi`Rv`qQHCX7L+eu7o70tUD0=GS~X+`p@- z$ZEF>lRrvyaL#MFX-&zI_G*^IqeMpuTEh8q&8YQWjaSyT(|;tqf?b6Y>ZplLo9WcY z40I#9YPVPF6@q`Q>1%wgov09>%MSVLZ)PbnbX%b zZ&+6P`HVXF=<`Qe6d;(_wHdp~?MlPwE8+uAUX8q~{}% zhI_P}=14_vVV=O)$o-PSrRIi0&rI|AjIMGD^TYzp!v;m&MH(7v=N@RG<=*8RfW}sp zxVwb#V3#g=Nit2a#wf8-B;ojj1y+@fc< z|9mHvWY>yK(9sKb9n8hL9!f|0!?vEeNy?g~jjU5qLdY`KF+;ZO zA!L_b_I)=PYeLpx?4wAw8Ot~^GoRo2Uf1sr|8ZU8%z4gvp7(vj?NQ~Z<~z8Hv0E<-7`lHrnHL9F7ZP8%WhBM6%#32p83$bIB~5o~e}$jPm6 zV!L8ansSDq+kY~>zxIiwH0sPRG#gX$Cj(hT@;f>kE^e!vcFQt;jbzh$%BZ#LXf^z8 z>onkxUwz}0hJgp8Y$o2`C7IggqbXh4F?ltkcl{xCwy8Z6W2R5kk;!>Kc6$RCdYAXz zsnq<6?XuGpq&6Q6a^W7P+nR8ANS~vQ!+MKvZH0h$^X<;et?s$u7cJaaX6XBZDR&+7 z$3_LduY+ECTo?^6PJKvR9vnz-kNG%6eMXbR$sVM}6j-U+J(fRz%i@ltq)?65U0!AP zZ!v3d56_{tw4vtuR)ev?+P^6NE)vlX`FnRWMNWA0r1)TE<4Ml@AW)15GC47p70XB# zMUr~7%s$jto8+XOM)Tzis0v<<@IX6_spheA=niSNbe9ag|LdF~G`HTx@-|rgT=!Ac zd)dhDf!n|g-$gM;Y?ja0Tn65)*`%8l{(n5~p6^Xop8K3c@2T~9;#$O8Fx~Tp7tS+G~GxXl@z%P%vB>vf<7_&|6r`wkM8#W&ve&EyOZ<1r$ z<+xYKWoLF=;UpIC(e~8g)BAhTGtvq^bu@Qf2*yA50uoO&SzSJ}v|$2d-mwfamM45g#q_tC4~}g&j=4v*JCH zt!`dx`uV<9#7*up@nY;qZFZpqY1^zN#tb-y{3BoH+~_pp;ydsFE!HykNJ4j@+L5@SgA1hzikpWaYD z0JmoyB#OzP^I4Xjb$$55p++t2VbVX-_RS|*vG#)45zrXY4dp>766x9`K6VHyj#&F! zUE0XhWqUssR-S4eG9&KqjQSP;83d%H%7Uwu*j9f*iFbB3u)ohM>5-=rd#d`h5hkjlKdW<94x&7iv(N0 z-T)Z?Vn6Gym2#ia^iodu|!omNk}X5Pwby6leAJh z1+ORVHgG&D8L!)X+3t5CEtiK(+sWL3hbX$pid!4DT|s>(Ld^4FMK|pJ>Z%r&%E$T+x$?wQm_B5BC-~*uyj&!T5pY)X0XLA`VO4_F# z12rY|y=$0x3{^C>w{k0yw$A9rl3kj;aZ$j0-e6ePUUq_(=v?G~M#q!wUxE~bUgaNgi!A9}|5hrglMvy`xveR`DZ>c?jl_3lq5GRA z(m%VH5pHN=bCmoM6yjI^a9SxdPO_pQCe!1hb?SSafyc@(E-^;l*?d`Dyqdt$QX+!S z;&%O*pY?PyCA-oWZMQ-&mH+6qn5Ovs?^+E!?Uwl#6{)w01_#t$c!_Qhy|D(w5ipOM zrW!{X)*zvF52js_O9g+~#|xA?NGIfQ8C>JL_{qRvoc$Hs}gh^e*Qohdry z#0upm0-z2H5xIX>8m;v1hEVXT1q-O!UB3r)mA@<^9s)dAeVO(C%)9+-#=q->=W;Ys z=m-TNu;msF^*-rl7waEX&)fluX%khFibL~i-6TuRYHeV^lWeP{oPS8!8wgYMP$ysRdAZOy+z%EJzy3^!#Pm`_$GPTs&7 zf`74@H2(SKoSpA@y<$`_MdWCIR04PJ7#gfv`s)R!NW2SUU<6xy0QK3zl?sohy<-*T z9zx-l|B=;h|#PUt!`!h7W+;t63e z%2mmHzB`*(mPZRuKn=7l$9+rIN88TZyFLAh&+ z^35R`zp{%yQ$r5(hc1GPp*VC6ynXu8U5}i`vgun(E28Y3u>zjfJHO?EpY+_8?3Q9t zy3$D7ufalqkYs`Ea+fY{g2W(b{_?}xO`RWsJFWIpr)G}+X$;yf+t`c8d{7l37`r0D z=TgIXOoOI?VIyEH-6Ia73b~btGw&gX!~1zgLd#tOWbO1fee5mC*aZ z;i`KG&NRY15I8P(1sg>}x}b4kY--3QU zC9fe{qQ4L93kAx1wd4SUz;cvB;*m?h4vB89=ET%S7J{dao_)a7BwaV^1@hjSaRzl*~4-BZjn+-0XR~|Bl~k%sBB0~z<6H}_6{xAVF{Tl=?=pB>^!m;%8R%+j9OP`2^hz;C497GAVn0p zq6%ze62~RXgHA@tq6-)t#30QxdA%(VcF0 z6Q9SH{yO3Mo5^vjIZdEMo{79(Ht@jdW37fNU;OHM{T;vEN4WfogS3H>l&hXvTa`wB zGp0~Gm3!gj4et1fy3pLB_jzX>%&q3I{KsZG{1NeX;du~moT-{VG+<|3;f z)Q_&A^`WcTP!26Hk=KvnLMRa-W`yvZ_I1d)Z)CXyybzY;`$0*_dF+h>&Ti?~#n=zO zZl#J`7C7vtqn$yoR#@4l=B~2MS2mW5uH{A%L9^D=#u*JxwuEA0W4@D)p^Vb=A1!`| z*ScdFy*iQhFdF1=z185^Q|h=;sWTWzZiaEZI~u8cW&PEiHJg-$;cU`gWKQ6>kGHW{ zKoK6xI<9Rr5-_Xq@T#wbX!p1bi9VyjSq)7B%9=Vq>8fa{c=8-a)y=R7Ng>55VBFXD z5@BDcoShRD2-~%oC8SZyk$@>X&c@~O7BO9ZxAL*K|Md{<3x)SepJ~&bMt^s5%7aYh z4)hVzV!JL;XS?V-bJxvdgi}Dl+X)hbcJ}Wv8)!qr46~wIDbmRnKi^D! z&V*X8gjKJA?7HfC0g%{0l_yKV;y_1IhixDp%_y4|ssXJ8)cf?bC*kL}#GInOlzg@l z=eV_FbK`7&{lIWisj>d);3fWI28n5`dZ_iexwp4+ca6nEIe**s@COGt)PQ+c>PPfy zDx?9`4Q`UC1I@XtWbJhph#qkuktp3)Ug3o0{Mg8%HMG1TF!K3t;;?9nN$VYOrwZ3l zDw}h%T23i*b{;L!@wyV9^~tBUx)ltuX5!K!_Rw$LW4G6XZes!xiTk}2i)RGzS80p= zTpQ&Z#rqo@N5{#vk(tTQpJEK_A8#~vpsTuru;4p79`r-?=Ei_Y+UA~WUO$0Bex7JJ zgbiV#b!9e9r_EC7Vju1qu6s&F?5f{Cp*cq-K-<~=X@b8D*A)d#Q{L)%(7$yfEmA{% zwR-N*WD;S#Di5~h;I%5x?ryQHRtj|Ih^dWc_Lh5SoFo-%JyVbzK$6zSd7)8G3byTE zR_))PZ+pr5;7#{b{H%0)g>`uZt5NlNcg6AW{ZBl z{oFh4pRDIsTs5H{r8-(D<|ko3$|@>qK|f!o@-e$z?4jdd(2}bqV8h6-i?@)F7;_>l z%G-U%mhqItm1Z(|xjCl1Omu8Z=vn?ezh@sL-Q$UppVBXeW2O?&FQtv7T?9gnTIz^- zX+79wNNr3nF0MGlU&Cix@OjeBuIEFKJzCg7(i~X^d{8CSalZgnDD5)E1gG z1?;+SYRGVw-$4r;vq!mO)uZC>4D%2j#e|BJhy1NC^`J5=J2-{U~Vhz5S zQ5cjkS-&~;q^C`D=D4d|!$-c(R_Ndk%k_N$pxz)9lduZClzS0e5=zX?`9_D{*?GzptZbr6 z00lo6rslZILQgYaI8W#ZjZxKofJ_6wmiwS|W*Pz&q;dc;_dy=}{=g&WL?G9IFc{w9 ztDNjoxMlU}k<&PMMpcjX=lVB+Z|Uz}*=1v$q#?NGG!*@=~ z;7~c$EB2+sqjm}*znfG=0t3zE+8p$IgZ=qv;7WNA9kL|=_KGo+1169cwM#^>aM%^V z9&Ao$Uvn)?v&vEBiuR#d)YTu?nmN6JdI^Tm!h2Q|Xfnr{?MC6Glvz&WX_3xM6K(?L zs?(|gQ>psUh2UQnX$U`H{_Ktml)Fm^oPXpdxGC*(8xRY60!Zy^(ohy>=_)@j)5(3A zjjkkv4Sl=^&wO2%o$o%>*L`#==LV$;<#-0c>8)W0%H1Kul@EMNw*$=Ec_I;Pm43(t z%&gbjwxX_#!ycIjo8GPM&AKJ8yVncqO#!yF=FB8Bn$}<&&Dv`c=tu&u_2Tg38i9Pt| zUhafLW@;W(yw%%R5%8t+8Ps&y)MO%sQF0pEb3f$P?|ss+{YKW9KviTO@La1hPOABzP*++UBZCly$(Vh(0(Ri0W$kF z8`4a>CXX`Z>rBT_b;-t>52@S?jszGU*1wNK0%QHh-QuL$tUX`Dm;gf=M+ z_R2?QsPviAxyTdK%)QE4o^DxHjRW_oL+|DGs4EO)giTOYhs`^QXC)?E<>YP(d+wTV z$etD-5U#~%`TUPczlE4<`3Wl}$H(D!Dy<(>-VI6FhK&SzLqEwhv@K5Qf zSMvBXLdQg}DloRP~E!;A{T_8-c)z%#I_6Rp(hu4=J*HTLeQ)Ynw zs%>CDHis9m)QZB#>?*J9WFRxYIpbcrg%2|e?8N`6>JS{zA8^4o{PUS+lLP|S{%M%5 z8$qs^t_d-2n-HgYo;az!?y8pIPJOf_i&+?W{cG=e9yHw7O1P-d3A}Mbh>(ZComCb` zb0C~({glAy^d89Az~L`8WJc{6rFU=W9zdnY>nNNKex-+EvaMU+Fu7OJb!AK8k38I? z*yzG^{V?;a8y-Ag%bG2M6tHbdmOXJWfqa1=u!cCju$R6D7B7`s0?C!Yx2I>Cog>cj zinD*OiBeuBdD)b`LEzpolsV;GA~X-kM|NExCPX5X*4!_RyA-%Qc0MpD(7v-8N>57kh6I8-TCzhDM=4zEDiS zW?wGvgLUZyW<3}8>ObZOTb}kd9gQ-nghdPwxvudJ({A*UzHZv5 zP}b~RMLYJeJWT1;4z~=SJAB{qoIk#Ey-n1iVh$1o%I=uTZ#k4MeY z4?@hKQvYa4p^#UUf>|Hl1EkE>nCU&`ZSz9pGZNdb+Jl7Mb;8x@@B=Lwz*%WGL1EtX zu=*3!<%0}TeLG1KM*=4&G7f|HXl8Z|pkK-5nVj`Uv=l2X2KN~)K0lLpT=E6DuKkLO zEskGa!NbU0m^Ezpu|Tqy(^_t*C}!eH(1f1sK>nzr4keGBLv#DgjgtMnxfe<| zl=sGz)ly3jv2fo70OtoER>-&0Fp$PVh+v0Cj29k8yWH>b?T>OIs>Imk{g_IYXE*PB z0s|xtu`3Yhh+IWlASZLqg?6X;1T4q!r2RfPdn$Jin@Lsydh(p#54w0Mx&#V~Udt@EPJ?alhpo;$K;-3;vVH~dD@G6cs5H6%P9-f3YKzZW$7n|BEKQmr5 z|D067w>krfTw$P!kbQuKHB{&dt74o>{|dW?S7lXPp;OZk_7xYa7B*1b@#MYrfSn~I z>)gI^`}J<>0cv$|CG-|q5xfxoKp>vJ`g}8ZFn9~$a)xptEK&9Li$f=D#g>?aJ&ddU zMcNz(`{hmxDr0}qR=|HWm`XNGTLadN#ooqRNG?#_ye)MZR^QMbOviq{Z|UMT>?@?s zw_DnDK9l4NXrDp1Kn)ENp~WzDBpqjL!SroW=R8xH!kk8zJ*vC>aGlB|;G~>+1|7zK z5xY5F=*;Bt=CA(SLfkb~t#;eU_2(}Yq&h9GR7~04rM~O%@>*SjVY;pn86uTNQGNCp zywEub;=?xrO$Y1Qw?oHFaAY&WUaKcKjts-T7-h^Au*1D z|A??&$Nn>IN1|z8>VnVywA&@#?XyjHN(Qq5UH+xhE$%g2Eu@YfCUZLG=L|NRKBNdZ1-||kq8ZoA0|hNwLn{O!C?k1~sP$Fus~Usj zcxJ1P;Cc?*nyq{oo)}jVBbQme+#;b-i#Rn?08ViZS83HfRfj7$e4u8xeF8WP4M zH-BEMYn#Cha`W5fY1g}#fmKQW;(+qi6(+#i7I69sFg%-p%PMbT4##~foKkt?>_a27 z*!G)?Q06NQ)gKXxNH$>a@X16&wo}76^U`0_uZ=@$Z}MKnX2O#x$+1W!@=vnyv^RjFt`uz92(Tsj<1}%Ncsk5GnzACa*3=OMv0sTMWm>LN8+h*P=C9Zb` z4K&|EW07P|yIuTl*3+Fh0j=B?!{kbgFYSb=! z{bJ+~#g&#b-29$UB=In3@_20*B&f(a+9T5)71=rm{eyZBBd+#f>rYp zmr(zJKBO|xQ8AqPt37uR`2FP)x?^BvI=XR0-o!G;n^N(C&u4H&zW z<7MJi;VDp30JV@e?&VI!5fkB^4ED#>G`X{gz{BM(YX$0^Bf$N{FF-h*<#*kmni2O~ zTiC?fv&X%ymIUN0sq9$yQfGE!Qt5ibXV=udcv7)` zJdcNpd~SQ&pz54yu+7GL+Eb2g@pz_R*ksOy&<#b2vmpi@bGYQq-5F4`#E^JLW8>6yO=G~G^joVv^>57N#!IlBP-lQ6<9U3JKI4K!S&Qgp= zvuYB6li}kX-2nca@h558Nr9Tzsey6IVuuf17%~M?NtzKZc~fMA0;_otdC`qqsw$Vv zk%-bLs}R%FtI1=9yS<*~e=B#**krBn34Oiy`Ee0D7YrnBRwE`y?Zh zJ;~(;X?0+|h{nh>X+IH=9F;HoKimDRo!dYOTS!d;L(Ybsx%e zH#hZ30=_DrY4ov?t)c7rqxpq?@7ZRblgiAzIPyzViS6fJen{nXS2wu22gjUZ{u*2Q zb?fZz(=#)=SzNnykC!5UMH>I7=2*Mu7i3u`9ryH+Dd_886>+mM@0y5CR+>jc^;_Qy z7w(?md<>6rAa2Fs+z%3E2V_HAkfRbynSh&!8+W#CgpBR zv|JAh4Sc%*<9of8j>nv6Q1ZjKw~isxEZC7%v;RGh&*?j?v5Rv(Xxz4uNOKpg{_$mN zuu_J@xYTA460Uew3Wqm4!J~5SoxK#Y2{g~&vP!Ao*DXBtzGfYhPr{*dgmr2Td`Rbm zZ!8Tm;~cp69ZQu9@|$*@jr*Th6Mh9SmP)Yrzv-1OjJVN{u~|4&nnobE#*5W98s#76 z;+m6|VU)bT!)^G#OTGPmPf_1!r_GN$d`LM0EphBaHt7$)P)^T*)j}4FM|sQ?DGUy+Y?EafiwL^R}kOSp-jiG2iOj8SAD~$xmA7o%VOJ+?PDg`9u7B9&75N z3~A;=pLR5I*jO(aE6#qDdD(ms@h65Y<#5ZusW{uzguj2R%mGV;X?7leE9JRd%W#2$ zY-C9zi#4$`ffYIQUm3^S-s)w)xBf&+x>gwR*RrIwrE}7L>P^$NvA?QQEPm^SE&GE3 zG^-q%=qau|9=gEzpfWyPq|Gll*R2}nbI?t$F*{Oke2dWgwSi2itSl(OhlvRvY$}`(nUY^5US10s`zU^uf zKmT|#Qvb4h@O-dnhD(S@+8bKJkW|rfpZVv~bFG6y(KHp$SCAQtURd$S4gKPD2Pj}qZa-_nf;E|Lbipy~z3G{F$vh}YV4?{^-bsnr*LfR1w~eLSj&M(Y{ZPzR%PU!>EDfB8m0ZwBdEHk?Eb<4W z!95gVNs#E~Sr)6qBA{^lLcIbzFi-#YJYVIyw#avVNLJ_xG^P`ED;IRJ&tun2W8o;A zFDZ`jn+kFj+Iv>6C<c5D zp#(0<59*KHMuyN1Z35fcGDum3SP(!7!<7sL8(z2WGbJ<(Gm5A%0(Z+rL@$NLb(**U z3&wXE*#*z%Yut>peqjd)r%({69%z>kAdhd}>0GmfyDBZ%5KeiRHeFM=@}I_Kg$%i- z(>6`nr3557%c88$kvma61_&O4*C2`;3Tj8f!u43iYHnv3=g|mlvGboroPg%_9}Y*y zE!C0s1kEsxKPnl5WvuPA|C+Gup@I`CCy5akwN|nFU}eq7nHr#C4osYBgSg0?1q>b% zdJ5}PYDLHFMmH-zcD}dqfYyn5grx>tVKV(lap29=XxmS%#}$bjaq-UyH#N7bQvBP@ zY0va1NoeQiO78RJYoS1Ok31aDB7fhQd&{JvCaBCc<(}ciklIg}(5+c?hCCpthZzq= z^RNxD#kX;PQcQ?J3Q+QoDrKBPpQ?>{$Fv)xDHE`%5;A8lrt2~m?Z~3I&2Of*{Gm3P zQeBvYbl6;pwa*|MgNNNueh^F-D0xmFO4ycKE2^4OZ{29 z`l0^?hBNETLQc41&Dvs`ZD2eE&Ao@b1e6#OuV`KQNp^hgNcZ!vFgKC?^V?JO7aqqi z_AhjMdDpY{cI`%p+obBW^^@L~uFInYT2S-ARMMKxu4BDTIsL2xN5;9go|GdAJ))50 z0G>ymXk@blUv)VgsHk)DLKMUQ+*|wgrj{r}CvEw|j9ucNmw>m!3u}$&G;8o*_VsJ; z@w_uF%cLA{@cQ|j+n|l3(m1L|v`Z6kSw#>2b`9)5l?aw|KT1#5BQktERz0Hd4&CL5 zij6G~KY#0%|6+i}(dBQ*c^D1C7!|}8PrX4MZ|kezS4K~Qd^Dd)TY1$bNP5qSM5lk_ z!H+I(6+*JSSrpzHs_=Igii?2dV~-kHgNVbY)H zeaJFbbw&cGKObDSb6HWZnP9ku)#Ihqm{P=rVDi0LSDBd|YqPqKxFVeXE&5k@)6Dn1 zL+Xd8;}z6-XdP?z8hldY2@$$FmMJKoeVMJ_RijXY*x=uRY6h(Y4p{sL8y>Ir?D8&mT?-@}zxKsh8*g3ytsMgOzos)wT&qV03CQ2~xutcBy7 z$oYG}!lhFf_>@K#=Br6I9&tB3V*iR93|1TBMRntOD~F`6yk;lR-%HrCece=0DxTC` zg=iGKZfZ!XX>q(K=d?`vhqAaHu=t+Exlmd~G&#QUF^xlFy#J!9=t@TWyD8fwSg}GD z{M!j5Y5YJ^EX!lI%6WfT)nRG=)dO{(O|7g~bw#i*S&msb$1fIZY2V|X6Ng822U!l^ zn`%F!PYp{ci~TkyuEXwm8<+bbfO*0yIvG|lfwhwt@ZWW4$?g|lC@MCdnf$|@7c{E;DTLA`1o0z7Lq<{dY zlTR{8<9~j6mUj5t%;Mtmt@mo^-0kgnyj2!(QU}lC*A~4?wPm7X4Q$qhO4aPICuvpI zQi{4H$oGIy0;f4}Ml|ZnQJK)-AxdF}8>eO89qn?OHhz(9IBCAe`^5X}ebG@*ulV3Y z*iVUpT*i4aD42c7qYgp2y)&g3#v^mtkymW}oQIhb*0^FCmvUW@NF#EoNNfK*z)dIHT>?nSB+LIB%f4o1mq zEm3vJ#{2_SCJ(ZgzJd|N<~Hg}s51=bh^Hh(S9TyzNd;AqD{p@~)!QsvQc{l6Wkf#k zR$?4EF7dpiyU;`T$qQC<8v#}re6Sn*`T+ljDh5n0Je2IR4_Y&Jw|&X9`t|BAAnudA zqUmBozDS8gy+emk32 zQg?mE@k?g^81I)|9=pRQw0&Yky_88Lx!RKoiO^W&4WQnrY5I6>rEk6OWK3~X?Q{!i zAp0^QJ63nh6S;-&ctS#g|BgKn1DYk{$yf0p?%qmM2jl7NW$D7=HajXYpX>Ogv|4Hp zX%Sx@|F62145p~&7W!Zu^$> zpF5m=*f?=WM58ONPlaPWPaMI&e$P@ExwbjpZm0-i?`Kx z;`kg~9A^!b>!#!j_}^R9LvuYk10sdtMy3QhO|BYnD0^;eUOr^Kuoh%G@ zc9r3w+tE{;DWrcE{X_#okXYpjQ*x11tPWLCv5K2Gm}PlTarMKkj$hJa^qzyj1Jq3z z;W1k@L>S?5_P?5hUWlN5@`EP8!k0Udu-#3HU72g+PK3K$_~C0XHZPG?ADK)O9(TpV zZkhE~xkYZi2Jan1H(9H}zMk}pay}u`iT&Qn=$k?(_XRzs1F#D#tZ4gv4#Zu8a1=h1 zMa}l{f<@CUZI-xprCuNLFZ{=y(j*RIXtpGJ?Glk5Trl+)&ty81yv92Nc8l6optrf^ z4YMfA>01{0*})?9f+u5Mb|J*=wXQ}G!iH*Wv+7A%FpYO8Fm|N% zkH?qv2VrBuGBJVAw)mM*plfQjWH*xPpYZ)#lz}Rr*csz9N7=YoK%>f3@!ac&4}zbK z2xmPRk&t>y@aL_*KS^dcjexVU{|%cHf=WmH>%e$~FbGk$qcVC`y_eJ<-TJi>Pkt4V zyvV#cw^dW6_d@q>bt`%`$LtJt-sUDeq06+rE2@#|+b9 zCl+}^@)KXBOu)|ZvX{KS@R9khIps?Y#?b$Cm%lPL9o-Tjf z7pyi1c%V%Qga0&8bjnnjG_%@B^XM6FX`VB10Ahs^)4!ddAR87*_dy(Hf^?5qIxjcP zp!&;q-0%<{q=_-o}A68 z+_?qN^<-ZPb<90awhe*|T4XqWq>7IcHb#s?F}Y4ev6FmGxy=x3#$es|o?gjYuw)p) zRF-wYmhyFN%8ktAzdquzx@5B35To8-@3*WJ;}D+C3%8G#J~mn{8OUZLg%T2CIxZDZ zhqR7+xeuIyk$Ui<@dpUjkaR4^ ztYIqtwHZ05LgpLn>!-VgCVR@m1^y(J3FiDYL353ndj$&w5r$VxI|1hyG~_aVt6wvvYI$f zcWN#mb>H$S-QC|c1+-$nvXDwyPNl{sA{Nm~PhveUIMb^-O2~E(Z-z{k(x$yb`9i-p z*xwt@LKGeZ`c%^FXqXjmuL`%nKR24&$HXVPzE`)f@JWwyXnk52gXTf_H_}E?+2(C; z3iUKLZvLaff4J0Nq2zSDy6MwTq@QliPpH$?JE+>&n5#}eDzFz)s!8z4y-%#aD|Wps zr~fb{yk(qvOJcnvY{+K!rE1`Ywr45&POP^ocsRmV!Fui*tS#^$**@J-T6FrGP$qT$ zqU1u!qfz$ri+Y#)`Of|>ZdMn`k|j5FM5R*9ZnvD5jAi_LOP66ND->7ZLhJVB@JRY+ zj>}zk8}AoP3g^g7u|!_ z$;#@TzMkJ5r9oN-WeBkuP9E#;US%uYRwvX-rHFoAg|B)&ExJ2k&REDT@TH0YmIl4& zS3L=hhty*uc7GA%vR5lnz00B#9j}S$;61#}|E93Sur~E76t~`<=DuggR@Vd!Nu0!t z>JXVoZ&Sxfxl>vf+x|Qj((7+CPhz&}vZlywQ*LvAK6kJm*|?9B)+a0{7yW_oXo&-; zUXu9-SqbAQrIyL%SuN|4k6(=F_;@cQJQ;QUyH6bK&k)Nn{fLxC+#}K_1YL?adoTkp zYMDGv;T3+iX!m?MFFrWlIB4P}@fsUH*&FB~n6CQv{6|CYd@9kcsf@)GJeg^fE-3qp z19xOM+WQ~}`v=%92nN)MayX~Sva6S?{7^lgjPb3?+Y^60mi+@nKRm#PZf?^2V#el1 zRq}J!b?z}7o)E^h0rcv;k~->wOP3O%sPlVOWyR>)sBIEYj*>$Dp|C%FTc-62&IE@$ z+0EtCk{zMFMftESYvq*Fdmp7>{qZarHgODwnsUQVCBhIWFq$OK3Va}fws5Jj<=vmw zA7`IM8?a)>5!m13VD*)NH2_;@i&trr?`4a?HHUSvzn$$J2sDrfi%ihZQ!Pbb)CDHm zj0oH@5c>p44`{HH`iZ>$Hb*=cHoGzaGT?^sJhN3i{f}*a;Fs^YHAh~k^GaSM+M!v? zh(Su7x|&b$@`FrCsc7evt3Xs~)%fx{FXt+}x(+Fh;7u4nHKKYJ1YAYH5Al4`dttl0 z-9TLVJy)$-;a{#S&e+SLTejDuD#d6o>7$oiwA3MVDrWP45a%Bd;U_jagJURhs;6 zf*gb&rH6i8hN>B-g?T@+FW%C+nlYd$$(oC-CcU`*I~AVbA>_kmcxtLgLS#I+uDJEw6J>rTU=KHwMpzd2D0e8dw$-VfFDg>T7hRX+u zp=Y-yU0{)}zF^o;ZGI$RR`#}AO}r&Gpaj?D%aX*e5%0X0(+w6T7#+SJ+^{ z%Eu1t>V>U+2OKsE?xf_BUH9X#?mjGxPCuO~cGu>JYae$@IV_mDj-PPj zpHsaEvS^8){Mt-puq@nVMALczN{H5MDtqBwX(;fKV|>*2V>>xsf_D=zwgTOb)qcKq zlSk>Y5{;QpXHj+DjY-gy@#$Dd*~aIl7hX|sB2K?^H9vRz0`}vKd(=?Zd}0T4pF~d> zdC$D+Vsg8hB)aJ|kpjYM>G!1}I<^A^Yn4_D{XQ8?16HR%j5I6-%Yxqwv*p_QAEvE1Dh<_zE6PJ*1jsU$J2cW+O1DF)z#nwW0FM34(Z zKgmd9QfP3FltGQ^mTw2-C+PY>ldmYBE2d&$^m1l2qQKWRf38jtD_Z%uOP$jB>Yxh> zZ0WI3s*WM(}87J9%NB|cN|o!BNM2X&Q{riL4P(UaD4=yyUVl=i{Q?= z(f;!|&f|y;>}!3PIwltVAB|b!q7T<<>e3;)67#(*%N(4ZJ44;d=h^DD`fo|u(Q#bOJx)wpskvS=y0SG5N1%i zb&|`f$fCAj@yhx~J-=&3V!yBfu69_|ar%4bopJDK!Ps>fY!KW5nh9WZ6VQHhI09A& z`H;HQu(Qf8?(}b!rygh(1c`OWh3Up}1+)&)+2>}o$LTUC5M4-8K(c$W&N__E&*!f+ z%Ts~5bG^)|@ zLQNd+gg$+MU-$8{MywI5Z z@>a!Q^*!m+VoC<|#s0hw_2S@}I(Sjbw621B7>LFqn1+fGp?y$@^DO2O8Ya#vb5#8D ztSQMtfBM>o(d)V%$!CFU5GKH)$Lc9RG;&9#VeW-(`>QCOp&$dUe}~{#{SvtMAB`Z| zL0*8Ym2}mk@Gog6BTL)YKc;8vc$5ti9-E?~Br&f9q<+0#m9VifMP-$ybZUwCeQ=K! z7Nq2AG5ZCsT270%{M2B=%j%e$Mg`<#*idrtwkGPIo5O$G2*tVFs#3rzomvv*Nd*K5 z`HD2@7U@_qHFY#G+&{)6hN?%K611;(@^(gDd4_QZE10 ziKq_#6QF(#%lr;CBMY~o{|6kYRcp~cHbe``aZp#rSGRi z2hN&9*s$*|GY2%LOa8`1)8>)i!s!=!AYZvoO$k=ArUPJj%!KU%z$#g&#ZM^NRl=h= zfToMT;7z7VyZa4uzaOY7T-^BlaZFo6wVFq zPeNsu>{VtZduAOfBq3yvQz7GIg{;F78JR^iltX6LvG<-KWOIz;oMX>(jN@>|`}g{M zZ@>TD+<19;p6BCwT-W{bvKb#wO5*-TZC$ykq+ zOTCkyw#&F?%OREq8Hu@P@mBSRL-xR72Eb=VI%MlN%J0msS%-IEwDuB+MLoj_|6>*a`o&-gW$6ya>?j?T8)5>6q-8 zQt}<5t}Eap!tjW-$_2*_Sm}N1s435Sen|KJfQ)$p#WZW-t3RmJ^S&-o)_^KsNu_&q~uUV=E(9ynCs1nR%Pa81!4@QFsVHe z4dH({FY2Jyf7y0k?cUiO_KN?xqfi}iTbSKF!6~An*zR_uoUpM!DLwpJ+gKiDyMHWp z>wLB@vfxs`19%T^iit zL0p;6vwc2mtCDGKPLaDOd0Gy9Rr2a^(8|H(tF<+o?CB|n-H}qIEQMm09Z|snGyl=F zzU>@*X-GaR3(I>7*5Wh1vO9k+Z+I|fFJ7S+9AEoiL}GPCo68MBmbA**m}=~U zSqbrv1MZ{mADHsDy{?sPCC6BFUg-D?x-dq`!XwaYb2mbS*^m1#3Iw(QmbDnzv-236Z^OKNb~2< zsA7%HRT;*VUAy!}TH*7%FLdelea@%&yx}V1Dt=${8lQ|-A%>!f9egwkanBU<QW5 zGDtM@_rT+wSW%uiI3+Z^e80dMQfTkwQSh1tg?!0vnyEK-KQ6ibNTIyDL4@Tu zh9PBXSIg8!Cp2a__f|4DEGKG*15%KyXI8U6>Hp}XKkOM55zV*zc>_NLdCvSbbg6?a zJ+u}WwDQg!KVdOv^7oTSFIcwa*%yBrq}jMsuek7?W(LntRATH?T;%*!O|8Vr(qNX<8e=q%CTlHiDYI9}{7z_jnV3WC`?k5~ zzxrji2N&UX>&GoszqXyss#A`a=W5?tO|+A*-TMp}>aD@zl$g<)h;wGeKCZkXULW@Q zyLmU>X;x#wq-wmzHW&HL(UA+R6`Ca6xM`Kn$ zYZ|i)6_NRTYvfG1`40g_)m2Y-SmEg|2Ht`c$>gJZmolhr5q1Db1Q^Dk_#4ym?6 zaZiKDQa=;TIw1CQ;x@7s2wRt^gF#{MWKsokTeM+XFC(_2^v`+rj@HMeKXe!5qZ>A9 z2PUd3$^)vz3yv)uZSSTRtAFKjm247}*WrbPmyKw(e+em5&i+~WNxiJT@Ng08h-kBRFel%BweCys?JXeuz%vYs#uM zDD3y*K!}+7>r)kiFU`k3kykd2T}*rZ?iVt8-&Qdf%*+1R8?Z}KqE`(`I>bgYa(Z($ zG=k-GbpE4RDz^0&{itb$|CAlu)akyF5j8+{@GE1OUje* ze;zmG|D@h<`HYPW{l{QYoo3Tk(2V0 z!GE&cYvI8UZ|s@%zyEL8sd>_hw-iGHXtA?q3Pc~XbU`R&A9N>Qgr0wAcB1$J5AAA_ z^Jy?O@I0L)oCaLncZJVhb&#YZ?EkR7z!E|I9p*5X>#jJ-L_>4hWZy?SrykZwgK+J* zb#O0>+%ix~SAPLP*TC@%PO)!kDspFT>lPmwg_X&=H=z3XT<3Ry#2T}2_#aI~$CElQ z+d2TdGP}n}`FKgM<)0BYht9h02E54b|08>dY=kIEkuqRBF~_-mAlu@;pua@5dZ6t+ zqyszn$y!zE53>gFkE?!j<R6bW9rB9$>IqnSKAj%O$-GSDw+;S{#0E@s_7F3= zE()n9{GA-idQ|^We|aD!s^Zauy=%~gi2Z#(ONr0+uOv?pB*qa;DmV3y9pVEpdBNkC zui*xgZyHS2$+85eb+uY>?$&o1y61YV9GT58F!TBY?Sg|KVB>TJf{*yq!4aWIzMs|= zq5dE+H~7_%mZ~vzs38pUGh*oWs@%czXIiW8qat>5-VTy=iHi6Xk!4+rY{6Tq*Ln?^>3hvTOT)kAAx+fJVGo-ndmxBp(BYEII)jcrGMMIdu3SWru&UqVej=tNMR&}*92%Erzpzj-X__q^%)G! zdM%9DHyx8zdw8Iessl_r_f8K@MdkqYlD&V z^^OYooTL%x8pxSs$_u@PHxJh6=L;MlKsJl(6Pokv#quL%wC*9Y_5d+ocD~)b3Afby z*T2qNHkx~&QP= zhS5%21dX__oxDa6I!F(;w}_6Z#S`bFzg2v5Oht z$K(V2=`IlH?PU?nj&_6nf>^uMno}C~JQUw`K7SU$dxB^|v+*iui`Cw|AF$vNHWK)D zH&gg2Ic>B9lScVJz1Wykk`m6EaSKy&#CwF#gkf!Q^+&@Bf%TcIX@ zpk{@hUli>e%dwF;ccs=Im0f>nqJO=*VI4^w2Gv>jNHaN1YBTM?_yYj+WgK-L0%jz} zS^c{!b3Z%P=VIdelMsFz&Kn#%yt{SgYf!YYNwkcQS%1zZu_}igMzCtlnD4 zXt;^gX6pR;WKT_S{pe{QRaTfaz((d;0P)?MNqdiFj_ezDQUI}TI_XwR>cOL%VbSwT z34{CLMfjSPRG`2in&3@L#KY0nQBeC8;j7d!A(0lqN0|Z=Mm`{zUbnGb)^jb5Yl!oR zLR)I?1iS|9o@z2|YeH@L9za_G(!(I|XO8XeDxd8no&LrxT>vG53->z!*T4m-JWy!> zJr+mOfl#ke3gUVZ+`$i?_#`2h;b>FNr8Y!DMZnBhR+zi5%=^gwVb&mP?87&6!})pM zFnKH^vkC6esGNtb6G3P}V6FFROZS7Mj|v7b@X>+eMfXpg3go>NzcJ2_^<8Vm`7v}f zr=>x@%_Vm_LU)pOYw7g+CT{eI-WzkEHCE&JAmHsdf8%J!=FxuIoz2#8+@=2>a&rrohQ1jqyZO>#P@T@Ec za?56*HSLw=S(9YKRP*dFl~~>>QP_1+s$JMb%I4oSrJcaE`iFYJET~vlw99`USyg@a`TO7Ksdcr*yzEuu=}lz#|xV z3?cirm(@OF@-eE$(G)dEatiM%?<8|&PnVr|>Gzu(R<&eKSBLV<-KOZ7`JGn!je#E@ z!xGzX;X) z_J5bw7vu$QH7L$mme~?6L*YzNk;~VK1$n_cR`{4&3!;VI_(mIE;Am~FAz|WPkuwwE zbiHZg!rI*)2@KONP-P+rV9EsJGqPJ&c2FEU>IS_UV{x;~SGi|G!5@@Hgw~JWH%rO& zQuW%U4q=3F3L-**I`URq19uSlx|OcN9nLN-eN1sP1X542VtDad-`+#sv>RWpavo*s z@NAU1hgok5?{0DLNihOZC9ElZFr+io0nR-$*8hc1`^(A$0LR`k_e{C{cfs9;YiAtH z)FZKDfr-q&NS3dH>No ze!}EWfaHR|X>(CZ0bHEV{BS><6MzD>OHar^orCbIX85thy>`i9br3J?6*21kVVa|b zp*V)CV!IN}5uhXTj^{=?fsM>DK=?`w{1q%o$Rb`QJ%UR~Wv^{Dw-Hj&iO#+)-hoEp(m7LZzzrqv z`5y5*nMlmYi}))fiJxzEgIhIy&Rpvj$ZksgjS?0$zIkJ=wq7xfT8# zF~5bF%5`HLmHC%7Qw*1vLNdzT#`nW`G^yF#%#}5{;U^t1QqT#=v|XLdM|3MATT=2g zJ$~ty^|?ADJR10}*Hdq{rp%z8W%o~~W@Zs}MirtfARDGc8K<=Gpgmn2hfS>3Y_>e* z+l$8OeM>)q!v(N%Bk%tGCAwo}!axr~h&rmx4E&hjE5;-$S9@?h(g*=|4Fj1Q;L z3-QlFciSPw-ZC=MX4CdVNe|e_$b zM+Ke1e*vy8<|Aiv*kP&%(PY+vE#Ic zPeijNQTfTYiE((gUbqldvn$_yS+KD^ZO4fCEwI?QsM5;yV>eHUK+-C0j4eM=4#o(3 zm28a>MWtMW3u=ckBcRt)|&%+ z1}iqtC-;@r$nr&7=a%ca1qS(I)ysyZ4ZyThw|k&HONjoDMpk$;qg_G9A=$-B~K zFz`KnE;!^tcyf?J<=90_A3+4}W z;x{4=pUNx*#PN3H!hMfNcD4ivCLdqJPo~z^B`y z-V6r`U7qAN^~vgqvz)3E2L)5|b_oPj(Uy&n3T^~AR>@D5a&p{y2*|I1MQh>~U6SQ< zjN0ec3SUOYx*cs6T+*BV)AJu6yqrCwAPY^z6neq9QlTOBiQorarDCSPJ!LZMt;Wwz zztk`rTuAZNvLQH~%o}MH=6VJi8)oU@SmSO$f_Yx<*nbXRL|A_s(-Wl4xe~fIMHTs% zO)_&vr_yhIRoALIdo^7#yYB+KeuRDZ&-$}xbFW=oWGf^3QNR|5#rTPqk;PQ&{RoR< zro1f3>$iuVV+pO+K^REmw65GCI76h7+7e_4@dH}$xg8Or zS2>FFTx3zvffmZT;Nf81nnpFQ+c*QLA@0qQTkVI_vkfKSc=+z&ZPdIPi!E z7LQ^hKSK6v<5j-A6@*}w)S=SV%W|tiT07ZojJAEh?NIT;&cFlIgZiUU@g4OY{Rj@C z!a8s`>DKUpWB3Sz7i_n=Ltnu!IF7M0Tscc?wcY04)`> zd3;+msS#uvn#LpA&{X?Q-%2IKe$tbICQkP@gf$_)|3@QZlv_7;Q`D!KaUzl*VLybb z0ry?DWS!FtEXYu!a?r81uUNw%8xGL>#8le*Pf#@spWc2G$S`tOB$ul87V`Vdr(=3O zf3RJ5Km3%mq9g;#tsu;31V=~&|IE-;6|M>_$0EXqeON)CiUH%n+R7v3LHCRXgSL*^ zIp4O|gL%hX=d_y^X(6QUDk^V@Y)skGqdPj9Z$d84TKdtZZLuy_UI0XRs2NM-*FQq9 zzBFxUjTn}@)*4=Ssp9Pvm~v%)LQ5AtplLlP%mi{Bi+574ny70Ll=lgsSV$mM;w#T| z#IpSsE#Kwg#|WQ+dJ;AR94J0uNq8U=&Y{GGdpffRY(Ln_%M0E|aC)gNhgi4!Gc4Dq zSg-ON&1&r+$!?@@s4^_Y=`wMozy|7qS4PFP+9`+a3EServ$F_Z?4<`)6Aq3|LGgbc zS<(Gvo3ieL@o7qOM`_;;hIbx4yawbahFR+Hy7dx4$-I@I6&)ed#{)ktND2$X!bK65elSC8N8ebGm6ei zTurx}etldU^v<>qRjl?OjT&NHmWkRgbUV7o0F0NetB)(xd)=IT5DzugR5$r)nXS;XNne!Oli%M)h-6gFMwQmwLjbL0q4No#1CA(10)A6L+B*(S6zP<=y zq5&a;xKuQ6r-mraiE;{(kZ#0RPd*$EGe zJ?XgOsb2K{#iXWg{-THVheD{||OH<2{C~&Pk7JktMkQlZP1EX1R#HVLNwxPpC6RG&k|gSG2GyT-!9Ucd znaEA-9=fu5C_NVIcBM0vot6w4jbJ1;bapUkzQ8G(-e`>L6AUaM8$_I3*TP9Jj{#n%A0H9 zG`#4-3Tdb!7U4B|)n`g%YQfR7rlCH{x4y$-4DZG9qWwb#EGB1~OD!#*nZIqoRtm8d zMocaX5`A!|kBP1&!{r7THR_$6cI_$Sw$iqw(1=ou*i_jXW01^?Ge59Jup6c=ZtpTl zVGDJsmD9h}2-|U$I?jUqT{~6xak(p3`tK1_yZxodQLVG-pspq1K5bFFYJze&qaL0u zUYYph%PC_|>5HOZ*S*)*_K_NwqF zc+4^ewLhCV{Xq7TO)l5waoCh9@o=(g2vYdzY{}POp1&kaB(=7*H108g{K2=NY{U^P zkZuHDISzO0Q`HvC+_7wHo;|pM>xg^#ulA3(to-%CTJJZcn{oc!H}-kxB(=v2Z9K<4 zKI)rFD?XxQ=3W|n9X9KkmR2eJ&?&g87Ll^dr#K8~yv)s}QTqXKCet!c^xxAKgLxl> zEF+^I$rhUe`9e&-izKwjzw&_u}>&D+H4M#fjaz`*aJS3 zm7Ws&A=q8(A>jrX!2wmfkv#WXst{%08W|u~wl~%x(hj&GqMGIgeei5u--m$dHLuI- zPQCWtl&as=vzHy>G6ne4l#{SMXRGF{K7dJL9bdkSko9K!raV>A_al9*LojmS^+d1s zGnDH&i&Smu)Gd$)EETxz*MMTR`Jk@#03s7GLo(f}12O7i?GqP-P z;HJ_A!kMuNZz}2*Lun|V4{CX5Rk>!>;U9_&X*Zb5dW9%@F!|w?a3hl|hsCbmrXyo$ zr!$=SQ9o4%pYjcNYS7v?p#(_`@m8kTsr==0tZRnGv^g2_seNK#syV@C-*vK&>(aB% z<%g7?6R54Dtzx$)v!Xpvz!U}gNAmAQ0opw`kpp`jE`azy?YhAVzgIU1H);l=daZgD zo9deL61HAtAChEtQ&a=Yz^+6M0-90^TFJLNjq7mlNG^JaJLmz13PcbZ9-B>rtB*pe zzE`4{tju?Xg?Ks{iZ?y85u(pD5I6K{c>_5-?FUu+d}tRVVmo2XWZ^O}N-`*KMCn*KPMK)b&%{ z47FE=*^_Pv_NKSyqfPptM4N-OsaIT)ed$(PnaRtv)#`(Dfz2=5eWtL7^&a3%rJFoR$Suoo<(=W-L&CO+$J)2 zqTK1WOkk6YBEi0cNWh41Ys?-Ql3vXTGGY>!`wk)Mrt#8sjV_Gz6_{^s{HBy@@MwEx zlEcf-1^$0EEeM53ZI$3U5jwwFaVyJhZC6BYhpTWZiap{o6nK{lY>84m*&w1cUdqfE z)Eml}P$5>Cefo5AT=YBk(bRkMGG@_W(KjM~l4+N2$PIMXY@av8pOh|zSsnQ(3;I}* z97hZNZ)QT`y5A)oUxepyl7ulJMxxB{N<*AxxxdbMnI_xHgNm`0M0?2alHH6NI>Czc z5JM~cQ|j@k%gYiYb{ZPmfv*_LOZ}P+9cZFr5i?u^;yfC`Mx6r+?Wos+M^XKDsk>ew zc=i8ijJ=wD;sSk=3C$*Pg}tMINY1Lfi{y zFP^BGi81Vxw}i|;t#|T0^1PmE&|^A&*o*n_j!9G}z7vakPTd^rW z@VzpQ<|lg_asHUK}YRI1WQV_!N^( zDBqxT`A%D3EWBEAlD#{%N8e_YwO<+*Raeq7$fvdfHQ+G1b}i^bJS-lnfn(}!@F?n* zu8`H#EjMDz@+v@fvAg`?5nuJK61kwtt%)CNAVpI^N20{|PpFdkn3vhqP zs7-#*TdCKCLe6PC+P!P^_=glizT^^0;#g9p_pTVGH=ad;Ap1Lj; zg&n>~p(goE9z>DSCf5$yt>>G9iXqzmZc>1-n|{#)${IAu6Gne7Bq?6D&BLoJ-l(NG zSP_g|6k9_&M847Y-*Rjta}D1!yGhxir!QSt!sa&%?m8Rf$btm)= z_4}`mQWloGPSWc4lb=`hq|K>`W}lFMh>y*+ix9Ps-cEX8rI?bA`xk0OI!aToY$pa4 zCh8}<97&6YU9%2ZqrC@8hK{#izaZ?(^oQaiEa8s-|&%1d3Vbsiinf9K(Qp!~C0 zJJ)mj)s#&21BXZL*;BLyZuFfk`jd;i>Bb%n2E$7&0a&~eY1pb}a`!I6FG%7)8pX@h z>an1|s81E1sAuit71)-^k6Fd(!wI+V*qfbLl4~(qZ|v zR$dI>qsYiJzM3bhuU`jVA1+8R78?EY__SKr*Y(2-ue2MI`w28#0wcnNpE2tqZ7tKh zGBSI9lrKdcxIOQ$g~VmA2d3ki_wrCbWjwM~WkU-82pQj3{5NFqAYq{4^WrAM@}UP% z;hJ7MW5$MR!KTWWs`g}htX32S<}aaabnkvzyzeTjNTIQ3Xi{ zI&u0iBb7&Ef+tX@U|{2v2VwSO&GaWbeWtAsEPu4=KM&yx+#5-59YX3X^S*STtds9# z{5=mGUa$>zHfoAmU+c;=TxU`kPH~d;u1jft7v%^xZkUQKPQ1_q+zjcvQ)n%A4y@3V z%F}IiM@lmZ7$kk>QuN+8XDwTUP?{>1_cKVX-Z!Yl#a8ZJ*_ZmvBCvDMaH((HhksIE z5=vftRB_@uqTOeeDz#ZTlBlX`^3t9mYBm=)-*;*Dy(cz7d^xz1wr?*=KmAwbZDUu#iy)N?P@dZQW=;768iqZ z>8!}3li-mFSCPOD^H==yQAtw(4;t(@N-dfTH|*L^|EPZNFWk?{*>{07W-N8sC6Z$dR-4(o;QkM=T5rcFvu={s&+m-x4RF% zcJ_|D*lfyLjs0srPi9z%I9PW?RVwP=LalSIRcVx$j@-jQ_pSj^(uJUzwe?ost(qSc4_WyDfCwG@r(ovgCPjVO* zZ`hDC7hMO=JDV;v{kE+B*V4k#c~dbZW8O5i#z$ZJs>4}yxj(s9g>gH*B^wvNjg$_Jz`R1i^Q0>T~`1B)_yGpECd zmzjUb?W_v9I)eg!_LuuR+|b~SBqJV$V`+d7#wlF!gMcwmg0kFRh~~a?{kHx zvcgz*o-o~EXM2!JtqV88DH7h-5)FWQO11<|P=zO?SYM=}aiadQ$jxdaQFgy1R;jUk ztDax`YJX_LtoadA25uVRGorCtv^;%Jkba))Q!)j=r-(-S6A`z8q@2k8v=-u*XIalC z_f{=9N8n%oE;s~fF>(^PBSEeQsX{`yjd&_QB^{#)2s;tC4Vn3n(M%7p0`$II!hSI4bnEY=N%QFUK-^RS?K zMT}>#zhjC9>T+<&v~tJg;Do+xNA(qjXyq(7ZHIqrs{JN9AFW4E%{}4((_SPm&B+O( z4&N=3BEAT!IgPC@2BFYS}nJrd3esIzA^t;cfp}`ynW73(- zB_3WP$T^mI)6i=0&)B`PD~yd)oF^2fG>DOMNIe`0Oo5bNBj&&y&*~TVb4GQz_qRk)kMAB*&YVRpGRMTqq8*N0FdUS$VmCc{d`@EL1JYFh=a56mv zS>wtFvGTPl>qQ-aFX!)B;^U^q*0$N**HGh9qoQEDzPe=4)1ZaBYZ#0w@D;_<_G!e(kB+$lwL#*=32L34*A zj}OP8@|a6yb-YE@DPEcXOz);uuSBx)7wI}NmD`Vw+is87H9Oi3e64U=mbkhhIQGwa zf+}9yG}#I&HZ9h@;NWOlZ}0Mr*<(zH2J!PmT4uO6bM`yaTw}d^k5;dlhEm8z6=FhD z8e&4T49)yb3m)IC zDe88%l)Tr%CK(U{5K)P85BAgMhFVXa?D_OQg+9b(WalDSUZTB(ZKe-cs@ldVn&H3N ze^K5=2rd#YA0J63$h2BQ)E%5WPEYImnM$8ZG{*OjG-e`Sh)Vw8J0BpdNf_JrH`fO# zLNB!drF~6@6-VGj-iQ}=*<493h>^qH2-@Ua6Q19P6&7}%Xaz#shlhO8$I1bJ4e&&VOBI`sm#GYYFaTNvb!A^ifJd`e>Cr)V4s)G zBNYkw#T|8dJw;D;^&EdLUHVCg+nLa2+LcqpO*a35syr8;OuF=BN21^@H4WC1jg+z0PT9gtuW1S;a_kzCCza zQekPz^E8AubLkmeJc^#2Y00a;P_}Zm)wPO0 zFf+Y*%lRJ9McN&wJ?t36=0~y|&Zjq=zn4$o&{O+ndN*=5=GPaW562pfUQR(A_8WIE zrAEpB1mZ=8&zh$GS|^I+{mfBVDGY~5a(xwyd#`!ZAEQ!dL;ErnIP$fmTH1-S9_~|$^g|#c4C}>I(nf&@dHM<>FL-ubYD}37dD&M+}Bma zO3&32uzd}W$Scikpkcjj44}(UgPGP_UI)?@#|HLBe-L*^K1Z2K3s$~Qf7i;q@xyvQ zs9Ttg>_W^X$wK*X4Lyz!Ok8X$7#H1pfFUY_F33$BqY|_QKCWxnw|osXqPY>GJ$>jy z=JGL~R6;C>_8<$B^S1b&;v2f8x%;dW3z3wsiw^vybK-Alu(=-$c)OX?-aw9ly7#3r z=u`0gQKyr@B>5^P*|Jqo9F+uR`Au}|6E&J3KW^YEZ!nr>%va+XVbr_rKvo3Kr+2{{ z#>5XK2O{#2?J^{Sa|UP)|0&!lBn`-ynF}OUC%nqd;Hznq6zx}EmNBI;`uTJ zWN*zck)i57g+Bg0M%PMnLkIXr@4FV_7~KXO%fz3;BH6aS`0Y_*=ZGvmezXEKk1l0p2Yqpx-_PC`3>x z&GXC*1;w=5=Xp3uwzt(EdaWcrYlf(aB{{Ey)qtVoa6Sa_w1W~wm1u|xls4!&7oR$U z@Xm zMK{E2-p0=n)wiW@T@LiJFr7Ny)0II#!hi8mKz4mjKg>8q)MzUbThQQsSaio#H14z; zo>YI{IMFqsY&$W_2bx0wd5nD6aO=rg5Q&qD1nh1M(7V$Sf@Hf&e7B)+pR_2ZBNE7e zjIs7%Mr6k-6CSx#w^ezd!^{5eItpMlb4SAUiU3vGxScjQ$P6!$S2PcO%x6_l;JA5y zQr^&A>cUNE7#112u3aeCS>^gNkMRc|rhg*C#DE*XyNa-l0TjfY9(7PG^)6JRV`6u8 z^28?|RMVe`L0yY{Xygx-4GatW#_YVGdB}b>{WSDD0ZtS@NNg9}($*r5pkW`7E=W`y z)BxvsP9oiz*^&;FHmn`IW*zmfhGnAG|4+AE#0y?t&Lg(HAbctMv>(9@6>KBEaK`dz z$^%7UZSbB4VOT9bK`xS2<}%d~>HbMZQUlu5{d1R9S92p}gK(h-Ai*uaV;&`|273g><2@~F$_j-KuG;K~IBmQWUPP8UWXmst-;kP&pjV1nGgR`HcF zzF<>JJa<&Pid}H@ir&uxbR8br98rFEu-N0gKe2X786JkJG z@kzKPLBewG2ThRI$$Cvvh)(9R@>ge~U+jziai@a(O{D&}e3&QXsv@%AfDm5s)~IAu z_f8~1chF6fCjY2YOE^ZGZ(Bb2EvXlo`6XH732(B^TAi?i744K|EsFRkkn>Cd+@o%y z*pM>{+DN_e*fWXG<7fEE_9maxH%z&!Ib`b}8#B>4-`ew@6|l8y<(1gi_XtSV-sx*T zjn@QYMyzhho^X0u*iCOVNV#3~qc`*MVOL8Qefr`0osdfky-}thbQ^Gz^nQ;Sizget zNsw<_ekod4o$UW!ZxQImk|bI7pf15DP~b*KAd?3LqXw2AuTAE}rT zb)R(7WP_FSq}ui1#6HysnYNhhn=kTg=!BB<^!-@!!!-fHUxT$Q+*gYC^TVOe3)U>} z7Cr&+0@A+=>_MDYI&+2@R?3ywL#_|+EH(V08A5@RwS3i_)G-C39#TM|Hit`S>S)m` znv79?Ub>Dt*Dp6*ey};16?jka_sZ7;e~XwZ?vYOaY+sORf26cx{iD%v#nC(3bpmdy zPwKHr-dgs{`G2;u0r6-Pbd79;=k8~VLDg7yebv+mm7y{O!+NPgiIyRG5MvX;H|NXy zi@H4gpYMNs{d~y~(X}S|&LZcD^&z@e0LDwC{xTK?N~z zp-rmDESbNkbsSKTF`%*TtUng`V!+Lz@Z_A7BrXk2^lhE{jiVLI`1(>sXBX zg3Onzirjv52<#bw^`3?nd(Un1a)Sr$U^8QByM*zFCSctpIOis85R`x?P zxDP&mKu{tY6>T*T&Ifi$1;h?hJpD8}xlC4c8nGuaX|<|X(~&MCpE5w-#@I7k`|d;^*!>$w&Y}INiz)7cR6TRsPZH{`{gs5!io2I{*_Rm& zke4Duh5WuZURs6k7n5l)B{}z4QhvNDE6F75(~^tn^6>W=C|TO-t}yKKQO`suR`#vp z8Li`bhW7;2s?Ca*55BAGCZ=_pZNmwHUI7|JgU&K~~HRs_ct*lJ$Qj~&#YT|MefI0^dj1m`zFKeqAx2png| z1Le<8Zlo;3#O;m;MHPm5Hask!h8-(Ccz$c!*^~D=H1S6RE`bvA1*@7O+scGS#R*?0 zvtU>l^^7kJco*R!-i}|5cnX`SjS&?-J?{{;(+iiio?J{ORr63*AcVN5_<;`*cUYtb zmakEM)e6UEb52183l@7;yh2$NhDiFs<>p8mtHG6{^_Mus%+!0!+Ga^VueDSPDdVsN z4xo(#e2qGpEr)aQsDNq_opC=@-xst$D1h*d#n(YVbxFuY|FhXn>K$AJ0*4(4o$cwk zu3OV<$5L0&U-aCbVajpAz+bp{OG1sh7q$w+IWU3dA%s7aoEP92JNN)wbm&2R?T(iI zPB&F7vFrTg_`AdxpMuLQbwk7a17iOi7U`3p?lnCPwSG@*z*e-8te~d&FMGE!vh+k4 zn)(~Bj$xW>6-75iOtPlB3EX@=arnlzutn~xouO^J*N_|y=b+KGZOom2ehuPv2VrLc z4PUu61%pbr;MXEJK+!j1S|P%z<#F$&D{gYXeX}%tNIewoNxE}_m~jky3gF%xBf^ET zh%OX|XJ~zf7bTu5g#(hO`D|a{#LuSGRGbTU< z^DEF7S@qGownhcMeS?H52rLCV#%3T5R$U^l%~ojoU^|XR@k0%97}*ry z<2P08J9hgVPEhXIJb$M;nz@(qJl6T`CCTg){OO*eGa3R$GGcxRv(=$kh*{{pj--uh zT>Wo!h+hAfwH^UK%}3Y+FZpyhq3?}F{|h|N_eM`va%M|iL&upQCvH0`aUEdMtO)s_ z$7+{?6Vxs;sFKv$Vyf!?A4TUG&eq?DaZ0Q9s=aqrQ8jBtt2L@9tzFXA-nD}eqxPmK zYP43BNbODSy+??>H;EZU{?B<{@bW&hqovTezf%Vd3@HKvu*7&L42@Z(@ksvgXKWtHATmtb11O|sBJhdbe+1-@aUhuJ zc9fzvR~S4;BrlPO#xQN&r8D(8uUl?UgSEEMZ!SlOjp2l6uRW8vyi4yAKf`?PK&vu( zy?L2US)#w+2;CdH7@!=$x{)v{eE|z|E=t$4aSV~Kw@vZ9Iix>Tyk8MJC5NH~}x z;MriOT5C19jeP9I97twYcU_tHNpvZZiGao#;S%v5ff*X{_m?$~f~q8aHQ+WS;ccR? zb|C@TOPy#~8oz&B{6#-#Tk$$Tq~Nb4o7v7+J1R&A#Vzc$=;0=7m)@h2yOO=Hp}a>5 zH#-ZT$ngxrhf24NKn6J=Xa}K-O5yu~T%iLC&|GQv48^{3-PeHeA;b#b!>Znkpuq{E ze_TJr&s1P2@lA-mN-!Ee+8N@`CAw-Hso{a2%HYel%A26Pq^`+a-vj1Uz}hjm9k0 z?luw;$b_TS_Ar65VvEMG0~h<9vYAkM?-&Qwh1{iIu97TtG=Kd1By%FrAW;-P zdH)gbbxvDI&Np@-Ig{N_MnRSVo_OnEwUb(+$~b7<3urIs$bGpOJkub%>^LJ1q% z0j?4{7+kT%6!=AJts^MRhF2$xcSpV77o=S6h7o6wKYJJiz2f6zL1c_JIJ}UW02+^< z@cSd#1|C~rtg!39dGT2QHnDOyx6|JrvVqN7ms2D!8T$K2n>U{=^wg4{qxl+{rUBMW z@UNKt_rzn2XsHo|73uBO0xH|(TG@lSV#w!S!#b=vTD^}_LjzxfPXhIT3{ z(r-0-Uzu%hd0LuZF(G!mzB-&}96W&8yy>2|YlmjfffA&F2vTpX?>SdAQ%V<`s4sEZ z+r;PXTu6pn#?E{kX8s3ZViAo_`@vnPDqsk9(uQ@h;#));8=fa*cqEu!Ka&1tux$Ai zYl|mE+%UA?XhWTVkUutlFgCexJJJhjeHV&tgG73C`qGGf@z2CZx2+Vmp>>YK+lXMF zU@=P)l{L$2+Msr(kPa)a{|H_rz9`Icaxx~?0u3nU)kJnwJ1LcJ!-bls8DD(au zWKST^j8v4Av-qotTJg-_ZHWSe+~YsAClt0*M#F0osS*u8?A%eH065+@fVd?^%LD6+ z-i{BHfWTf%cq%cTwi~9&JLiRnM4&0ZA*(*-W^4-aC#ruqD{lowgSplLLJB$w3nqKM z{;&2s=!*IpxwjqEW~l@+K+mKooy?UP)e8IDO9ZDL@wlD5zW=P9CtRttE#-o%GU2ta zXJna|(Yq%5{@yy%%LnX6!dvh24YcQ~PO{qZ{I>--LunOp+~XI)p}>u{XK4FB0v|!tIEU=;L^Vr=66unPFW^W6T@$FFWdz7{RB^*^~B1VBg_p--@|Je(W`eBs(143Nt*slI89<0j#E8%Nm}U^x$~ zn`jUA;AXZQlzNdyB6eey zY)w`Oozf??2zA37IBWa81B$9BmQTcV?y^4rFHPEC z;spW2o$Mjo>imBM2ij&Y&|A61i}tMA@kP|%hd$a1H1-gXlf77=I6A$K_1NrSVEn`y zQT$4XVF7oE;VAIA@JZU1?6!MLahjBQs=ytEHd=Kl7;V%Nf6z@Ne9rW_rPp-Ks-iJ% z1(d-aKPE@S7SuPQv_Bw~O?d&%XUb4h+gi`6BXEh|>k2pnYYLu4o`8n+a+tj(_T zZySAo^B$NagKXt`XIg(?C0u~|%@!Os+4mp8UNfJ~Z~uD6@z~6sP_T*Vg#s5kP(8zZ z_bRF1X=}BxP%-o#k$R+!yLu+w%{BZKb{(=93^#Eax-gWLbYQ&B9t>P{&UYSlAyLq_o|{8CxIKFAPZoCf z4ak$S^_*W{`p1l6qjredfS8ZD#p~|SJ8q55s?{w5EyGh?#)UOM82bcTqEfcs%E`gu zx`xRl6)`FyPbyL0UEcn1?@arnHz=iBV%BqUiPUdP;p-hE8j&>lysv9k&w4$vDG*%2 z+YzWXzaLF7QB&12)!l6RLHLU^L-{enIB189KkU5QV)9_q(JW3)q*EGamVd`J4N~#1 zU**;~s<;;y*M2RONpHQD^s{l(CD$+bs zslvJ(N@YoYrW^r#^BjBZ*N2;$QiJN59T;&jeDCkQgn$cSYj5T%6DleZv9*htBQ}3F zQ9--%d>HTg+n_{MTeo%wmrbd;gF`Rj>YEsCX+asE#*l{I>@i8|j-W>id*oC#umat} zubDn#>93z8TWuJ+R6xdbUrN?v(WEq~@2-bvyc4GxQXh_YVv`r+V+Xeey@^ zSq++!{>?V>+wVy3d^*n}*{g1p5&)PJW>}M>NtQBEL5=HW=Xev!5L;e|TDO zWo2_*?OhI+-UpH(hBBjf6^<9RC;9CFbj^D!E3%Tjy+)h3+w#Vl@KF6}{$w^bW2%v4Ibv_}zCK=ZF8ns0o3dG^ z<$CC>wnl$j>h^JvCR}*4?qn@|fis`0(0+g1q0u0Ehq6TaJcRH!=|`tw?+MSoGbzH6 zIKh!~+nNwxadCv6p|nO_PqM^S{P8No!U9(J?bu=28L3XO-{lwbowZ3Ta(0J&649yC zx3prp&h}2V<5-wML)GbolTCX*hlSxmU}~^<)Jn+FVzGSOQgQK%nW8;~$}}HZkiyS% zmOQFY$I#l@Q1=|tvl7$O!MAz|!|iW<8FG@O+!6R~)C`g*7NJmvoCS01dK1te9$ypc0J0GP=-56M-^e_8cw+oy#DZ_>Ic1h{3e)y&{p9iC0EVPR1z&DS=mcQx; z!$Q~LZi0gyfhR$LTyewF(5i{S_rJuJF23Dr_l1a34pkWWJ{~>DZjb{YF{isg%LL`a zGak3Ii3VAAD0BDx1Uewc@hq++AUl&7v3-gs12{x)u{`mbV~Q%d5gEUJ1bWpl9Sdv; zJB<$P77%nZ^VI$|U&msCGcU!d%^qhezWGA>R`W;>L77G^J}~-rK;uZ>r~w-okSXQZ z^Eyaw)Zua+C%xkfcHPps7-YQfkPZupNx*4AUQA(Ulm{j9YdfU7{)6qnD|5siD`Ypd*?pl z$N9h9EX*+SB)}%^^D1rg%3p@7#yjeMMwXRkTn}d*#uO8TQ7rR;x|9c`h>HK)ljiTh zf|)KGLD5hl@vgQoPJ!SHcDOZ%O4-{(;`bIy8x;yjW^g8-)~SeUjZ%YV+}W?>{0FD+ixONv_6Wosb9t^EeY zoKrV@2R&OM{Gk8!+v0bw@k<=tDFC2-h6Z;499H$7W#&1oXhF!sW(BVj(jx6ob6M_P zzhm7)U7q97Tdj$h?Zfk%Ctz${SLRICx@_H8jmUX@6=N&sjI@?qLK4~QUzo=oZ9|2T zL~)DP$P*)AoV-<3eChtpdV}Gr0&9rCiGdi1u^o50^< zYxeKJ4IiP8g0-uFY_fF)M|&>CfJU7by;MKc_69(whQWk=U^I%h?(D;BO7@pteD8!4 zIvTn$xv_arV5G(HuWN(3Cj1pw5@L{R+&_$eK3)v52y}@z_px<9UhRe#yXs;|&bctM z7kjrk(lDxOKc*Nj(RX@}-vT0P(Xx6Lr7BA3ZXtdSMyia@FE`&+*Ja^*J0||k!DO3j zPu>$(ivA3W0n;Cj5o1Hwm{guHZXK8h`i|DPHzE?6js7Ue6t8i(@1&$jEK4`auGE~* zkpwr~Q`Mb&3)kDrzJk}_vg?i@-|>pwmiw=(I@`g8345v+fVLwf8F~*eAoAX510MLP zzgSoQHKhs%)7I4A3ot9xBBN!U6+yg70>>%b&lXvVq9i;8TH3YQDLs^4`5bE;l0^& zxB=5&lUmCYhU=z*XO^$CMfs?+FHX!8V!DvVndQ}~SqIg)(Y$6R<(8G;)wp*W08I4e zO|nS%-1>+l5^gld$rLWJ?B6u=$G+@zOdW0XwAP$CCf$|n>^lmads|*O$ z2qM}|Esv~jzU9>)X9`NGdrPJ)fog_8zhp^&tj8zrlVgVXy0jcLZJLg>WUP*<1K zkD(7@*Li|BgW3_?=(w9~O-rB82$?m~KII=qW1u;km&6Gf|C}sy?CjxvUy^sM6bjPn z$)3vRoNJeH99}+rw*L?Q&dxII@{UX`_3thCza7zzSUUOOsn1D5vMn!sT|0lHNX884 zou4>waI|$Ou4Menf@eFi&;AJ5%;VI=V0LpRC}VUi{8^N zA5+(|sLFH)6xOAiYd;3YVog`fcD|G?Kg_kV^9X^oBUrH2qKM*(nwB~COy}*4&%Ftf zLj1NRyB7QQMfcBc{A&kI3+GKc^4P6t2+P^lWIOjqX^eO441b2Su?HCYorOlt~dd*sjRgjawlA^$R=*tBVtGDi@3)+c>Ti>fXBxNL{U zIPw+u3I?7~Tmt>*nY{qUuzOOs)2itcDXoM4BNIm0(Kg4Ut%TJUk1qL$2v2jZc2igc zLTY}r#>A1_T`*~5?UgynA& zU4L8KKNgSuw!VwyXiI*eS?E`)Z;0SA?iHGwRhG3zmX)QY*SN+T)*m%TMDyf*IgqC|5AI^jVE``evcPWly^Y$8KlqVrnXCt&YPn_Q zmr7Vjl$&}t!M`l%vCb=PEVwVX#Wg0Lw@sk#%!i*{9m>*vXP~b?BMopbPlR_Mf z9!~x&`)u&hyx>N0z9P4&+H>EOlOKDI@$YG)Rc6MiV5DT^e?dhsPIv+IQkHm>{$iJr zMu}40cOC`u$h@KG@3(!o%hD@tRIm**XM^~i85$;b1b`Nvt`^7s=qV?(?pd$){&nc& zlIl(sp)u=^Hol-OZOY+r=`kASe$iUV&3s(L#`rP7C z;;uGN)Sc=mo`m8TR3iO>V!y|s&q~AIasH~8(F=Y6c=Z)B(i#r{5TeA3OZV&R)NfB=5 zUR>2>cL2anB*tM^(d#R=J-7O&>kLb&)+-=32$vpufps)Ws^3eT4B}z*F;t^*%23*d zCaU0}*~14K#(&8i|Fzk>QUe&Y+d{k~R!eh2(QWlm;RWVdRp?7>7=;@)ZOB)z^@>dU zp_Tj4+q8ZacyK-8wmyB)?%jCmAA$Ovk8~jGv&i>_!;XYEcWR0M_*5sQUby!3;gr2>C8$J~4fhl)fUat9T#hSimMF); z^j4{*A1hM(Te_`22B6vp)p1u8H%6z9`Mqvy3X9+_RFi0JE|H5t3T=DdY`IDm`6K}+ z!8rne4Xvce7a@KIB3Z>lJQJei+d>}Wg&+WrvRa;|fys}m#=W*u%fYt#hbBeH9ezR< zW$Svcz7fYQ|3zg5E;{JDN$FuVLi-i*NWd=&Reus?iJxnzop#BG!1F#3@lQkzxryC- zLUJecQ8pzhBhn-o;UeHH)ZS<+GAaygZ%UFby{Xrd8XtL&N^j#IVziNw{NeY1-cZF9 zmzYaxseWJ4y*m1jU@5yPWm2vHSu>yQyQZ&+9Li&^=l}*@A2)nOTon`!%#18 ze}l?EDSM(E^Tg}EfRsM$ zYF@egG>-}rWzbh;xSNXW=C>;KOHe(2-L>-L6e$(+kKkO0X#e&4pB(B!g6HDbp>O^Y zik{OnlNzWd99zyLtDdB?r_8r7I&_Fs^k1n3><}KfZ4&-_Bv&k<{DmW4ILOvjUuCV} zqv|mkd%OxC_ZZ1++h5Sv=4Tk9i*htmh@uYtfoWTW;wyi;;US$1`Ina}Nz0rT>MemW z;*p@0TvYGD{JL)3wRb*7|5yv_hzXf*&n%c}rINu*$ioLyxvXm6QqQ45NaSi;$Dw2Q zg~ijDE>1S2bT&~JE5DJY8iqPzxvycovwSk*1J`#euD1@`(aqxU-Lxt@=W;2Oz(}UJ zc=apSg+=YDL0&5IwEhJ(cYB$%1K^w~BZ248H;9KWAg+uknYGK|nZ~K-@4@cjgx1I% z7u^Q;R7USEysjh~NR7YWuG1@xDGaGyy|1tFOgKK{*|0|@1HK9FAPj>$rf0Tb!xcbv zkfK$bCWJRZ`GbYi*V^v>j%^|#0-F{gbuy^dpHe9&V$h>s&IE@n|8S+onofMX%d^L; z`0Vvu6kB@^2S%r)&`zFmCZg2A$SJj(n*E8v=nk`A!zyj$m=Y&-q_H@q)6zy7ohS45s!FANPnmIK4-KdHdLF|O zYBaW4{0~n+o5L=6X{7%EQIX)0GBB{XvQM)`K%KJrFCKR0cgOOWr@p2G5@n zaNgR{J|>bN+|L{*qp%I06fEfgdG|7psBoqhFwx}dgWv?u6B2XP;P+{mLun@yHVtIf z9{Y$ItufdAJL@L!G8zD_X0|!}T8}()r5McVlueHonG9tAgqMNR@Vg}F--dh9NRAP@ z`s4nJ1Sc;dlnDZ-8{JEkVVwc=dh6Lm^Y7DhaZ%>Sov-Er{2!PoeX8x#umiXM(K{#s z?(WMAqRre0cX9-|J(_Un-J5!n9FBkZ7cDZ=gCiB|E`5MR40^2NID}_Z;YOdmiYN9M zf#<|TS#yoF^lWRIfhdRJgyA&F68&8A?;<*ahNh%mP*oLnNdAFY!5k^up7bKo(wDGq z1j@3@Nd7PuM2csC(COaa$)TN)GM6|{pfFp;j&Lyr$M%N5m~50sKL?tR%Ec5lpkEn)x$*vl|m2KCY0?lC4R6l z-tp6o6|D(){hZj5Kl#IaPt#hQ%srmQUh4QT4l>$u(?SoBQALxXWIGbQdsi5#(g z5@z8B@u(x2%tg)yw8t9gD^TZf{R@=GNR2P<2!?f4j8-%yY`G- z|Ba{vw7^b>L~pS06707A?XSRld#(4!q=C}?1J+1;0w05F899 zRQ-v4y$s}i%6+%JeQi&Ow8)a4!rjYYFbhjxW+x7x`Ed+#))Fx+IC^gMh z#O+fGs@muqYyH|pva98l8%E0SKY|`aY^yLP+MbTXcFiZ@xF*ZLshIM@Yf4-&N5J^v zV(E+IKR#x}@@P1#d39z$Q5cOtvq)iil#75wt4xdrz$#G| z)MGf3B8X~-1>1~NhT`+bs5AG4+e%|ohPt=Mf)B#e)D&KX$X}FewdZhS(qnjL1jf!T zCTh&?A8a^VKA+JkO6Rg>A)(KSP_(Ja2Ua=_ulz@l0S5-JzZ1>RBND(Q_QreU zh{Q~Mo|d{5g)c4Z)}J2Zb~kA^`abo-;C|uXGP~T2=k7bBkR~le@0t|ZGzxd}K?C(F zy8vmy$GF-V{9(q}wE?F1^O-=F(CG$pz=9e-13=?~=Qq-`huv&k*rvKBI>MYwec?cyjEAO7H&&)G*;iBs(gFQ{>B) z?2kj(l`e+VpC4Lmq9fKQK=fyeS_Toi&K%W9vP_FV^CsQ> zJx05?BHbWM4$+$2h#Wcd4=hsl$^wuSEsg64y|Tp|5;rh-*Mb4)tRm=)&p6m@e;7S} z5ZA5q9G=?F|57`68K%*PA~3wtfn2LW21R&^YH{9 zfS6{-nNSR}1EEGQUI9^AAX3OX&DNPsjQLWM>mSWk`)2CW-MV29&btL#ifK7oQHugs zF^}-aC4Gn#kWCYq)*Po)hiuk!6m2ao+q+IHWEb!FrB$-j$6}O63?lGkW{3erNcmH9 z*iS-kG$Ks@YFnR+Q+)udy51(h9w&7ukACS3x=Ql(|M__K?s8}f`0cJH&DhL+J<;QD z&LI!X|Ed(E)V%*fqEzw;UD2r*$E*~8ZLpBHGBV#G&zR=<^N&Mgc@al-R*M0wie&IY zOKY?u7Blf1`wL~ysq|<>bJli9S8nqk^E1#o3b9Lt(us%FKtFhX>GS&hv;5z@lMih# zvyjkO=E?G5lAv_nmhSz1e$9Mr*AL(xc1fAjw##*f*|+#Ah}vX1H9GwC%dv5^Gt#L* zl-C4OK2@2L`b9ojN#3Tl2{Is-{nsHd-97FN8F|~K`Vv5*`jwL;d9y~rSxDV+;~|lYd11Ij z&SL2>B0SE>*Wo>#enT9F)L?U$uOS5q@6Z- z#a#)M$?~$OkNx=SRF+pJRGtlsN0yzdaD9%~OW3k`!&L!3e#C&1$cQqxy*#`pY0cIu zqk9qFC14VB?^NE3_2NGM5l$>ood6rW8XCitt{l(`0TgI>Ijl+Gy&rfGx>I!Vfab3( z&BrJbsoQS{>VHpVU{=e~AhJNJz)@6BDBO{f9#U-9GSdt$u;&kl)vg3ew_#4#kK4Io zbMJe_QFrL?*BX(H^C#{rb2!SKQ;Yb0t*c)ST^5ah+U#M$oyJx5$C;J8^2x<{ClfF82h<}8ITKcUW2}-HosbJ5ry(YSJ?~w8Jhn%pm+wPK*Tot4T6x;gw}sU{DVn0+B<2~kR_ha0 zbklSFt`vZ;0-)o&^jN3)`R94Ntl8s}UW1X<0AFQnm6`2(k8GgVWm~ke0F-~`Tx4z) zQyk7aiP}FvId$s6#D)~CHRev%iM`6zyO1#ASSCZ(-gqcS>D;hgMVbCm=(dJGE>|}2 zykuxPJ0SoKI&=n-o|UQ4ZK0yjTQeY*nAFyJH7kM2fwtd!-0UTBWhL`zgtwD8bNdEz zB)1yW4Y~_i?}bsjG%J*$_Dvh&ddjUo9~K;u+|oww=k9;7t_{19Tq9^44db(lRb?^P zIfNGC_fG#^FzmF_Vx`gP-7`j}b)8D;ovcN0Yj=z}%Gg3NeaDhKT#t{VcT17V@&4OQ z_#qoR_)(>zWtXX9otp30Uj%yI9XdW7UAfy}Nt2~zEi|=y%}d8mg}8UYFXuq*C9w0- z<81Ih`RszkZho~dlVQmpwg(AZZY9ASa}b-g&K29J9DBv}Vw};pD+;%2!8{GT!QO2` z(x8Z=2)j^EAMLR+pN=NI+5Sbkpz4Hmz*7O&A>?FRRoD-|h=WP=^*MW_QHQFuE=eW{km{kcUY!1btR2nU6zaTR=xTb-oy4qDER*mO#tds{k5*y zCS`+SgMQ4b+&h4Ce&C9o@rxS}BKp`{{rj2s)1n-dG4H3@j~m;?4E_7=X8Z#6%p2E8 zH)ngB_g$U#%2X#q-O^XgghtS?s*i5z0Hcx|yVD~7wC&?NPn+YdUC>jj+0e$zRr}5 z&lL`L&y)~PpccZk#r0SgGFHN`jYc`6bd0&m47FNkS=h)r%?zkcuS=V5LylNr>Mb|T_` zTs2>i7xjy!$25q0s;D{qXl+))&EBn*zv5#phG^uj(<|kMKPJN;HT=yyPgz%R$R|W2 zB)`iRUymSlo9kWwwu%=+l8>Z|Rd%#JjKhB(6;hy8Uz$hB!-XtHN9de?++C#$gV+qM-Fyqj5{IIhuH z^W8QxJ|r{wF!0?np|N;@f~>~6U{BUhrj#>@Z^2@2-c{Zz=465T*jbUa!8vblNvax& zIAlciOVv<2+7!?;v!}eNte?`!7b_{)OEOjewacsY`2_)0XNbi0+k4$bsYUxI!ybjt z1+whjzGk+E&zZlc?BohAJDV)iorkLbTrA2EjKjAM_n8!ZLhesgmwT~gkxVvg7xyr3 zohznAQdXEtqM74=Y;g57TvkpRjv6-ska!cvvaOBXF)RKZ-yJ!{x5TxVmKJSVgNK}I z6=r&m%hYu8h4DKV(*1j=P>o5GQHNTjtkLI=VbOOU{IJEu{|Mr|Yf&vdxsF9~cb4qv zwsn$sQw+7^$OyhzlAM+63|#nUKiVTblG?Y9wrQ(x`NF2x;0^Lp7`wMwn_H^%L%tSa zcj4{FzVGN-GW$frMEFYU2?xd`y|mbV#nI5C`NA)-=#G{MdM>puq(8dz>y3HlQTmIp2;}OwB9Vqn zGDFhZyh|5nt_ta!&_L<_<#ISj%$|O0mP=jwJ-U=Wfu`)Nq;6M-#^H!47oqx)SyW+s zPNwaA_9F1p#R_ej)KZLrO)RQ*qxXMzQ)b8Kvv@Q2SheR-wa(0-HcU-Xi`}K2oS6d6 z+VW%nM6p-FqkgBmsrO2xhn{LG{n6oul$XakCHWB^T4W%G?eiR{ZJoX0B}*>fM^`c1 z{|3}atBoWIvEa8e@DxMGLwV22q`2;~i!JhM{tXhYbrl9+%sF%|TISPgwQKEeI5GU7 z;v{H&UvqW5{DVoAeTCgGk)-VbhGV-q_xa*%+y+P-$y$(%@SMc)c%cBcdd#I z-8V)h-)0(G*Zbbfr!%KiW_*Z7KP^a59bHv0~M+mNOv#N4SL> z)}Wt1?H=Rh%%6)`@7v;MBG{>(iM45Bl-Ih&yxi#Atd)@8Hj&(4%X+af-}%W05lR)g zf!`({dViiZ5_+7Ebx;Y5SQPLWxl8cyJA?AaNA%&3o*MhTU$^e^jh8mlcN1x&6P02} z2>$vg@V#5|;$HPcS;3RL{6f@Z?0jSdUR@ze%l$E)jlTQbEJ`;>$!9D}3?GAJ`{NPk z<&6rFJlfIv#{A%%JI~%7epo7gpwk^>$NdadcE6jzYQaLc>&bjKH*9^ya#;#nR=%RE zV5PsE9DMTXxvRAT$HjObn#w%pW3X=8=DSO8dyyfzFJ^Li_xbsc_&=ufag<)+fFWH? zV_i3Oh%dl8i(-m&>j7;R#ev6Is5+nCDO;#Rwgdw5g?7`&s!(mL;L4^>=os(iRA`5k_O%lmu4X)%l#*;?H4?p03xg(*vLWtw8-#SCF23L zY1g@BrPvE%ANneaQf>k+C^7@5mzvVy_g!E0es(%ZQkW&4E7ec?;%wdKVT+^_MZS5=Xn4fZS9&w93j~FMI*{z6jE2Py z{JJy7b!C-vj;#H*A0MGSH9a9{Lv~LWY8&nSogLcvhA4^n!wH0I)kM;swpJwup(J7P z>zcUz`9qJX6;6?-+H_tY$?BAwSHHl3+xyFw8)q|D0+Buz#p(V32q>g@*W~!L$sL75<;KGB`L2?^No=kjp<~{Np9mJ` zqkN~kZ<~O0l_99icz0%>g%X^5T{*~b>u+~a_BUMZ+|pt?!nDWbU~w+PNLEiv!rwrX z&uC8SX?F1JC4(CjZd zZ5GTa0f^yZt)}E!LB!yh9WAKP%K7VH3dpD_=2dv9DEuOdIGz93{EPg%9;qYL4`}-m zdTD=`U0^!Qd_O!9Di3fo@bX`l8B!s&*ZWegJEBzQRW7dG;#yI?^-d_wyDax~j3{V1 z0o+rT)dSJ)cP^u*P;-mkc?$Z_dLJ_S5}Usg_e^SwJfJ|WwsH8|2&>%@AG7`ae{!&9 zDkWdJ^4{JY;s%Uim`9=UzU(#UuZAq$smEN7^9$nFMP7Xic^eFUBYwyMF!dP_*<=T< z%#8_rhUGk3TJBc9+g#f+E$XuQsIleimZQmPXkBL0dg2`_AYh~$I$erK<}!X`bi7O8 z{yK|B9j{2b;@*^N2k5gX0{K6@d90|85izYZd%+j&4-uVaTV~S{`M*;7EAlU| z>Tk%gIZ``|)G}_7_cJN`m((kJ*+WZ=4TfMcWl(I%v$9|MXO9Af>fu{1ROs5N-1NH- zt#KQiTJ3cI)YQjG*!8Op9QIoyZv%jw*EsP`JVzb!h`Tv+WH>J8x51!nM*P#~=ZGjp zzV*ReR&1MAe7|+bq#oveIIS?~iyU_>atP4)RQq&sF&Gc7W}8rsWVy+rYVM^_Xk8!- zu^yIiltT{VR1T<0)%8!zYC`%(U+*bbwl$}Vmxr+Spa%dSA$y0$Q*#9_a8&~Px$w`^ zUZA;&Wz7j!+9CJ(59OtP&Oe@PZ+_GzHX2zH!&=|CL1fn>x>&>lA3=3$FlmVO-)F}h zkeE)So>mc9m!q%{UO1HGtE}QH3O_W7&a+HPwzO_aXY9Rz=?_an=13Z)j>K7FozV#w%^30CQ6h-YT5gYcR2+QHqAj+S#<7*VKH8a0V+Q`oEB;G3 z4{Hj?xN4&6<9LZazEfX35s*BPg%MfbEJ6SV2vVVLAVT@o%wa1Jn4oPpGgJ4`s5mp1 zLbwY6;z77Zk^U?OT(%mjWl?++%G{dydnr_vhzlhwg>L;e2C-eW(tAk1ikOSRlWElsDKZSUlJaNYI@|GWWO+HU9E}IF1(z3@@6OKFC;be@Np*(8;cQ^sbpT& z+t&w2Pp*cJ=mvt+?64#l-7XA-l~j?-tqkI?H^n3BW$VK}NVyo*Pno;)(g+zE3>LzV z1j^5}QU}f}(_>vR3TE=79XH@uzv2!K-LAyl@O{lGOD6r<&N4BxNP17YZ~TcudQB~X z`8WZL_&;$JIi8Ff)jPRZci!#G7Y8fLLUpPzOr3KZjmFCD0bX?4(%}pA!m0ep ze96K5@3~|)N1mjsdFEySG10E10Gq<;7T&C{Oa?ib?*Wsa4-08xTK<^WPpG?oa>oa> z;B!b5gO+zH22@sGbzs2S|92Y%GC{z-V8S*Va2)8aqEV?j0?bKlls2 zPkrN4U;7E{g`bDr!IR8G1?sVw{N2k&WCV_j7pt`ffkbN;)>O}=sDm=+gBQ~2)V|!a zklFr0?SO^dfN;DRpH46p7Sw4P4ThAeqYo@VXpYtJXVuRB>b4q`!=;bmTUDKk`j6lI z`SS0MyW40?(H=iiD|!d-)*Nu72{p&Auj+;=(_&EAPdEv5_%lItm#JD1%DZBF;kheu zhkuHQ3#UP|O8NLHqva@g0yLL!@g1ETjAw(0yqp3#iNaQ;YZJ<)k1Ei6APNW5Sp63= z*{xnJ)fG5gQk3N0U8wmgC{$$Kv5g)Q+WCn3>ye^Ismbow-p!=V*Kgz6Ixqda%gbSN zbzMm^rb^eJPv%s7j}1anJZpA_wj0{7*Mw-oBwG*#^ zkq(;;`~Zwm0Nf zxQ4^IhWx64EoaYHH-o<%7L}3lJ!M1_5sPQWrkEkilg%wH#y!^s;kN1T(%h1A|7`?% zT?iHcgH=+74NKyFDR(E%vXGW$Q6qVYZNK~oTHWM)x4Afh_lfHdsb(y?Yzw{9@RZZy zo?$bdaDJIgsyPAI<_$|e>Fx%KuFzDMubxV!mqvI}rT>ewz)Y=_kW&?mdZ&_Z@16Oc zy4tks^O`e8#>|(`c|O`Ee{g>OgUUZAb;|wyPN4WA?kNU#@fLG`QpWzbe2|Vv5Cv_F z1d9=>w^p6l=&S;h)di~n|H~zKzH$gt!MFl^F*7sGe6ZaTX{1ABbi4|aEVnwb9D%#Y zRY^@q&(W5#=Z;|IWOzA0-Rl3OJR#JQDq;{x`JtNF_ty(!}-dA}rvpw|rA7NWgs&xLQ z%lr7*{osAQcBiI)ls!+LKuT+Cv8U9}g=ceOb)TzH#*%z+C&2yrprE5`)?3Xc zg+n!eLL9qWAEld4{F;FmBtCa@h%XFLXZuSlNt<1a{Q@28-Ip!eQOyupHuJt2RVR9| zs#i0Au5`1aUEIZXOuB3F1T&OgN4^GVx@ym!9eMso@VCo33Pt;jCmQ!P>GpiBMMwkr z8v4F*!d)|YWOdHZcB4w}R@-fvOS&!6g5VZ#AN~N-p7k2RVgjj=&__eBffc^lLGcx` zgSEIzJd(8BAw8}{O*-k%;f>xa>gtsz)UhjJ95?UFdi3IMvk$icPw?swtAaC-t};KA z7rVGlJ!iST-3^Y&0(Z1k;xh`dxyJIEY*{ykfFI4s5_w5O4dR@>Rsa-He{Z8&Iq;J} zu$D~Kx-J*aw5|pdu-pl7;F2fxkjKta0kWMN^X9J{h82h(RWzw>d&ug@AOQ`2yO?Y9 zCrkpK)Edw&6r(4PQUHlo*y}|5x{V_-XSgXk8AJpg-TJvE$^hj-H)){(QFY{j>n}8& zsiSwgp{}FT;9nB3sD@dX+%x9(;V(AWW&_Q45MTF)Eq+Uwuj!7a7pDqO5>mA_U0tVc zFOf#Ckx~iwb`!jc_F1#HzaCiEw@&ivS@W^ktx2jq=Pn4R9C+SNqO{*Z?3A!s{^BP} za+WF;z1)F_12o&s>ScCn`(2aTPL*amGGWn_uPnJ9+p~Y9#FCGFOfbC}qUlZM=v|WQ z@mOX!Gk){Z?ZLP7q<%xOr{ZQ}pV_|O&u^a1wsJr*1k?_hRhN?@<< z0ONS;Oc~+$)QeK^wJRmU;R<$vOwd4&q}=#J?a|u_XJA@DkZp>6h7&+Hy&gZ$J&e=W zty%oMwSUld(sQ5t#y}3r9ry(IqQQUB)PI+`x%Htgi374y($znqV&}rhE?HtTBq)#Q z2Z6{@fbE)0Ou(v{2qnF-wyp7usMBGt+FL4l3a-I3#HcRoUZ#_zJ*lB44G=nvO~8{0--zupO}yd?hH7J6-;CkZi}buq~fmN%XF%1N{z;HuoYPYkR{FYX|;%r)4snbwazmY@{OWfilMg zRChfl(i2R9HFb08xE>ZO>Uygsp2he-lFmA+$^Y%+APR!Ql#pgB2r4Dr%%Y@3q+?2l zw7`V1DM&~P2q-m?k{mTUB&Q-F&BzVu+Q`8+zR&$T&mWuve{l|MyFZ`z^}b%OA0yge z&&#=u}Vv{HoPCiwi>Ex6`Ht7LH;D?socdOtrg+9m7h8&+fYXsh8WyXeWT zg+$@77rpI%(r;<9xa*Iw;Kl#wwp}S!wEU$dt zs?7FErDwk7>o*lltr(UckX?8zdQj(Jwx44X%UqlErFv4cs5R5fr8-T9l~SYUf8<$l zMw19pj^z8atFeT?A%eR>bRMdT=pq=3u#8TGKPu}h`e*37FP)OUctse; z67}mvr^P#HN9OK(O*yJNITSw>xxlb$C{A!qsC+#j)ZLRl@pLEvKf@5nu+i{Uw;Yt_ zow&-Q{Afsl>HwGS;0x~A2K5rxqqK?62YgMV$E<&<4KA+E(jocIN+FAhDB@G-Rm3Qm z_zWGn0D1+#qOQgrrGBddC_|*N)PbCfEh|37{NW0|7D~4Cm8m)$2npyZRWF@f**{R9 zDBpq$0@7}P-ioDi0_ZbANzEJZpkW0KrA1_KDv`g7-P2kkBcwjLbjrhvVRpdh62tQO zhMamC`f$`|N7U3i3cVgtoY2sNj^-68|5t_abkU$#lW^s`I=$bdT<PrdxHbgKCUJwBDWO|i=%vTxP^|Npz%3Sr?HM5uVNN5SH1YLk&NI{iO77Y*@eUebilTaS=k>m)JW zPB2NO`6sv{tbn`!Z^S(z2eeobC}b`1=jBMxCT>tVWR>%$h1}g_R2I)+;V6cy{|?>$ zg2FHI3_&O2jB718_ckfv)Y_8vP0dC*P8tVr(m$l|Y;P|Oo`|}n1!4KBUkQEsG25Y~ zg40|FhM8WLd=jdK@0*R#ue@JLrM|q}AumGYHFi+_7h;hD`p~teyy3%%uz*h02ztTU zc<08dSp-z(wCu+6EuQtE>#2iei(bCTsLPo_Xs*7Jd>i|)h{q((l=HIp=n4y$UPQw0 zU0jXs6cAw8;f7q(oX(fGzex=45zo1@Y^?$p3%N;Be_-P4oBUZ)&=CWm~Ye6W*+nEb-ZPf7fxEY3R+@u2MI!9Y`mCDF}psJQa(bb|BRVV*~@HVZv5DLn|3}S zN-eq{JCBwf#Yj5h>kHWu&~|eRZrpNjRDEK+|H;}}*S?T!TS}CPKmUuo{}VXqy%I9D`F?Et?znw!S= zdrnp_-F!`Vsx(DTHgdK5FuI-?I0w|#Zn>Ew+1q7douZ?y(s+LT#}kru3SDaMIFH5~ z!cW(H6fU#tK|dAIA4&_rc}dWS8H+K|P<n&qsHIg|9RWH?x#;e_@jTVHFwW_ ztRO@kW-0UgzNXSI8mj3xO;WAO>>kdmOmI+ye*bHvNF{%>-gkC(0nO?)W;d9tXBPkB zej}&FtMBBi+D$d-sDIx}QKPC@Mj*>Vx20r}^53^I2=e}YA1F$2r9`{WQm030Jdg)9 z?cb`13Cjmp^c4Px-+1vH>D`0xxNQ1APn&t|L%YRDF8|658C~P0SdOBjDtW@z-@Sps z9Fow*%X$=5suXSaH+fuwneGtmU%l!RGZE7qayHm;$>9740N7Ty#r#YK+=*+C%GxGu z=$nRMk^Q{;XS?fGpdyclj~tG@M}O=05fJ&qeujmvFTsl40VIhHb{^magpP{!!#H^v zVg0BRw(SSxTxt|l8yNSbCXfYv5;OW#ns z)Q{d4R4?yM8f5wf@LK|)W}3-2YWFWJiFo+`7VAj?8GV`G@Z^A-dl>?c02fr`78kvF=(fi1_{+!( zZ&rIda4kJx)&pkDE-Trr)yk^`mbuwoKT)~iSf_7O;&tgYc!KIV_7S0$d^VMxmO`V}NS0k>E>91(($ zfwEGhhp)wQ+vp%;^2<{2H3L`8XQC+Xub8E?d`rEqu%^=czvI z51*pq6S`Al4~IC`WexLEg~KhK{{1`WKF>>LT13YRU9HWWpw*$cY}JZ#DsUy?Ub2=k z-K}5arTn&hVH&p?&}0xr7bd>+SVwEZOn!mi9s6_q!0JCbzW|Z%_x_ZPX@iQbNl5~0 zAF-X>%o5HRB`fl#ie(OugJVseo;)V~5!+Vc*Vfe%!1-sRzWMKD<9) z_i_Gw?hlF6#Ee^Qsv^oLa%AkY*q4&0<$MVT@%~O@*G{DyIR2wMcNxjI(>?esB5uv! zA~vzCWDyCr6G35LHaHjxYX=Ug@cOKY1GNE1=oY18y1%Q^(nS(#o}~GCY$xNy&t9K$ zpB5WB#8p$QB*Zf!#Y2O4X9DX4FHHo8wx;uc&eV4k!W?ATU<~FhJT%aG&@M z62C2f-1Ny-aq3G(2kLG)FD*IZkDi1l9OO&4FUquc-3_9>16@PU0tZ{uA}BUGg0w%CB9*!i@-L{LwKLZw25 zEPId0$#0B5S!IZarst zSDk-M=QYCZ?UH}yv|eOuNaXt)-YK@mzBf+{+x%-_^(=isa+=J=OJ9Mpfk}GrS2+P3wPq}hiYOxtxO4hH_Lk3Ix z04~nC-xLG>tDg@p1MoFB206pAs0_bK!G~O)^$jx24)wRAt87olv%0)SA2-$1KW>Cw zK4vcat(P6xwLg+Q>`~$#eCrq`!acHl<%iOf;+-mmVEbI1zXw_RWuAWDtv=TKKWR$e z(QJX-rJHW-_;RDBefXhO&Li3-6WziaOvg1Ea+&|Uw?!D9-?Xx_Gt4g#r!*z1-V*@# zrR=PnS0v&dDU>VSH+qL!{&0HrB*M-j`et^o#wU(W`M(V_PWzlPaDN?n`d{|8u&5>7 zzX#h7cem;lgYO>sbv31_2;?3H_bL*?9vRfvjybfA?cBIO$#D=}eA&~+6f=ggGrF{` z$@8L)={HPZ_bHa)y1DaNxV)Ye_fzw>mX33}MKL)OU;m@KOSdMyI3B1*lU=aSy<@jM zs%>ZV=X~uuF9R+IcM9L$u{)IG{dcDPl?|mjiwiyqx6^XY z-}nGN%Ix~ucOraI1Msm-9ONi<>0NTm42#Mu-mFg^kT-oIwD`LvSajcYQ$N_$_o%;l+oMxv~hX+Vd2X#`cDFK0e|d*+(VIiJY1G@=iQOie_F!3=>F>@1wbkfqXkv`b>Vla?Qj;XuIE8Y`>|TcB zEZAo+ze~QNGT`8$XhedNL6bhPSwaf51ys zo#58_Ua!@HZ;k4Exb2*bk;qM=BVSezfpAVUa_o484DmRHcsiWoqeM#%QklH9n?H|LFaY&|Ih$_0QJ)pCUocSju&OF=p9i^{Ynst}5el{`va;{g)AoT{Ct3I;CG066cGV48re4bSXGqEof9Z~T->ry%kP#TwgH zFZ)u4jnUVLUcurS(X8tF`#8ZtZKgJX7|@VwHO07xRdaY<*^hBHIh!=mRs*>>Yy1kI z$8ya+D})}0{*Ug36)4_1tTp&9(l4b2wisYfK9&DCYf!bVW?7Td{x&zQ^;X3f_Jl*7 zA*Sw-A42x&Sj=eY`@a|s>F1dDf_j%N{&FV@ z$0y*4v!?6g`pnEyC@8*Q|0U;`~k7!$e`Ga=#x-xzu%o1p2t$FwVV}m z$u*nV;X3J~A)k{`E?=X|g-l6_)Z!(9NRjL_-v0ryJ*1h*-vG_uNGk)uvmt|`6jWTu z>o|03BCtd~Mn|tsM&^;YT5j)4zP9)fBgiW`C4jgYGnSwQOE%5>3A6c;kt-fMX;}54 zaLl#A^2G=4TU=QeWwz)YHRavj*;R76&4&NX3EyjJ z(S*SIJ5Vv7FPN%@tz7Z_2z*9N1)zBz_t#cm&|QyPWI9AA15SZ5Y^KKee5%yvA{jriBl{8N zz9k)CbH|F@e-t#LDNJ@*!0$$%Ny4}Z=4nD%l`z*H>x#ZFg6ItC&zHSp*D*Dnf0tB# zFIKXJJuxQV)8*KV{z*SMOO@`VSCa`gWU6MWYq>1!`3CmX7;(Qs z+-Dk!-T4~!;buJbhum44_}u6j3%z%_;#uDUV>0t{Qj&K!2z@GO3n4yDu;YaQyGxh=Y0C@S>(CmXt&Q0i zE1Ra*X<9+Kz&$*?m>NpDaG-h(MUgz~ujX$YD8*_fmq0&UIZWstsEe5Oq8q7c+d7XT zT0d2QCLwFZ&$A%$pS_%LYWF6{tGHGmjY1Jkjd76fT()8O4Fcp6oRf?Szz?WO@=f;U zY7jXaaz)!P4G#qCf&;pPdA@uz_!?xJ_CrJbC&V3`2ZATz12hUlig4bxZzl!q1=Oak!Q*5{bBBY zyjFM#tDqXeSWD&$hY-skA@6fe2B<@bnbtb#uV12x%E<3c~YiSZi@2oICb)%zhQi)eXt=? z;el#4hBjuZZ_g%2hOaBnjD-aC!fAz;3C7kV5-yMRFgg^qgfD8N%aCNQgh|tuFHfZU zCZo((C{IXIIex)!G$Tvx`U5r7-c%a;71 zU+ruTz}uE~-=7JSl}L=(PR)Do99nChkIARpd~j5z|5nhh>6lX?&@uT}3HWkuAQtk+*(XwJbLYodvxM{gl) z7_X;PKT=Uj6VSiBc<+5hRiVyc;f^V1!pYq zXIPi{AHRUt_0y|X&x*eH_O{LS2l@=3lr3F`690lZA&Z}ZlGa3Y3;b(Q!yu=@^`;yJ}HG zxgbD-p3!gVH$E7;%J3hZ5RjeawwsXO01*3`C*)3wf~Qx$&CE1naDiQ6&Q*KlVADL5 zrmr`lAl)!K^&0oUVTQN*T_WZHyPZbSqH0f8wBKGsNRpv=H>Mt%#HJ8CISN-XpIqiC z#L?QSRG%KwR@iZ>LF1t!+ZCFL&-VuKbK1tN z>mj0L^o@xk*|xLRHa*8GSFjN>4s1)P&yxqpB`6a)dI?SCM=y5JQ8oV-k1K?Naf96k zhEjt8%&6a!D`D03vW$z$D(lcRa2+?5eUtDX-477JR8b-o*z;?GBJAFJ1|K1WBP*Bc zC%g)xjWf1N|B$(_a!&c`A@aGFCUb?j78+2}UeW<0`9$zlviOhF@LuOKYk)-(9%6PBY>0$8)W9pC?lC3R( zd~yJ}G{xCAAyv6DJ2`^0`93r#bMYm1*{18sug;Gnp*a>kEt1@w5Ki?#yat1*p=&pv zMNB0}*XgGh1;G;>5S*8@K}yi)6A+las993&@WHNZmjz2zOD) z5rsrs+ZC1MZ_-z&P%KfCxoIb?OXPeEiQnk0oV;6k{>n?teFmW)78@2@hD&x9T|hrT zXZz9;P=Dmpj3aa;0XQx70QZ+dU%sy;5Lh2|g-8`}iB4{BN1(qfOI*JHbEay4Amo$t zz=g2EyH$F1h)k+8tr+PF<{;}lZ6h^okx1WWt*rFl1Xiw}U8}B1S^va3a)JATzQC$f zxh#x}I?x&F=!Nb_7U={87S3#>&btrWzs(2^Vt=yB@`vf%{qnr(1qBK-P+*v#gChIw`mFMVoh_!6aFQNtJriSjHMbEs=f*jbWXHHIC1y@U6EXIFj5*c9W? z_@>AF4<~=v-&u|b&UgMl_|{v+B%3|wxl+xZy?#I8)mO>iYS5#5|7%K~r6eJdM_*P> zwY3c~Xm;@_k}u03d_#QNxw#u?S2#XQCnXvLht`OkUbPmwp?Gh@{-)j4^O?4}*W1np zhZyz23h$qRzV_<7bH)V}eO})GW+0yZPk%4`Ee%pgXO`kzFU~GF8gZnvdi|s7Xk}&J zhdd}WqIu(!hw)YS8h5_04LJq@zY#cw*LHIk-ZXp&+{^UNbC&5zy;F1k;AGt{ zSPexYBI853V{VwN@is**Zj+N;{z<`h`2G8i;aYFV zr?CPbT6|80>Upi1)}Y%cruXVVJ>@(Wcq4?t7Vw%$m1N|P^aZ|Fe|6zva_q8?LMXq= zt%##Qp){PFLe#aC9?_E}$ z)u#V|)DWwX6_vrtY+PqoshHe3s5ZF@jZx?Dd_%D#n|6J)j*<6*c1f1gmF*FmApHlG z66%CJgda1aIM~e`P*mgLL&=_s@Vkz+%i9SM|sNgnS#_?WGK);LH|Vqu+iz8&%A+HG;@M~0{l=O3S(_xv zzboRCT@N`4OBbB;{w-b4|2>IXgU4~^^9;Vh7TR-MiDt_7!&T=ScJyWo`B{8ZzRPB0 zEIgUHsT_yCk$XGeh2>E|pPb!=+V>Y7x-TRpPc+%}tyn$NR4)`s?z9c8pj~^!)tYqU zm+4+^(^rry(fSMG3Sy$U`k^DFc5W~$;`jkDW5(|HY7rmrl6-~%@k*|mUUIAhLP%n^S+()!@*T1ar>tGYQK?d$>fAn(lUob0md_1Slr zC~dXxIHp*A!hu7p8ASy#V9!iWCJA=}ddDPnXVN4Vm^c@`!`pG?S6^9QdY)`e*m+~~ z>cxfgg2h3hjtX&0JZD#_hGY{`f1l7*;5F9{hIQa~yAAdGGBd*AkCW}Q`U9boV)ZSi z4R?29EnKM$rYKwRbjDIpF(K))2NVQAy!d;-?5#J5LxjXyJoKDLreM$04Fq3(_~t<7 zZ>JZAKOWtCJX2MAH=?Bk4|&y*bnR593(XA!;gh-rgYknIB*;TA@xC)jk}Yw7&@yoI z8V4qxCAR3|N+9%J&dfO75^qU-iuntK?0TlnW{7uI@x7O#)%!nryq(WSgohr0(?XfH zYVnakRpa>?Q2AsJf<_weWiLb)ZwxFReTFh4b74w9sFLNK3*v-v8wX zhMo=GuA>*B!RR@+R^H-uNcAj)nBexY{wrKW!F?yZZ2nhBY>gM2_9ML(x}&L(@#lKI zvwm~n#08=mAhQuB7$-oyjd2Y>6c^ZA-M>>sq6vlVd4*KXRubp2CTLVN&Y(J(wIT}s z`REHh9_IYB6MgBgCi})|L-%)u7t@ew7W~_Pxhm+H4mxBff1vb?*wNQJ)KJYFfUnM2q}vFZk43iR)U^8p zvpK9^F9PU3bvEuJU67qta23(-{a+xiP@aExmTn!4Xu*dldQ=U}I1<3{uT`zpA9dS% zn&x9US@If%BN=86(4#(N;i0Ws53y$!PDJb8?b*S&rGwQg|S&zwW0-wdcfq{I(q8sG!ISP>kXQ07Gd{D!^) zPKvupGRufLRPzctRoV5*k<8nRc-5~xGc*_xEO4+;A>$Vs`eP0NQ(e7s-iS%tY2L^gzkCJFrlubrc&$L#@00Ci!rwBUT)3 zSUeQ$^D@uIGb76-7boHZ#ps$VzkAuZbG9RXD1L;XCBO}d`%3~H*Szbtg#^VG`wDJ) z$#}J*w>{C-m&!TTu}?-Xs6O$3rq^$rzQVLdZAK>6RoIVUu_(?1L$;0KUuAmuFM)oH zB|a+-%0_vdp37Gp7riw+kerq1_G258*1!S|)8c8T_Gr9P;o{0@`yaj7YmXC*ZY1dW zYy8@^oyXv3K(V-;5`vd-51&w)BO&Y|Fv#q=N=DhLYUUMpUZvTvm6XI>8sA3@tmqcs>%GQ8^TgEu_(jxC^Fz8i3jW-e zsMGtT<^OhPQp$zrww}^`@bm>wvSM_JYaiL~8&6+9xP}6i76T zY9U}P4=`ija>GoF)?P1Ql=Xv-=X*eXZ4SX5lMcgZc>aae_zFoX04+Kz%yTw>j4gN@ zj=&5B&oaZs3Cd!B<<%(SE_GFtfl>7%uh+SqyPKo_ybnA;i;lf^1=n$^CiHgYJUd>T z{IE2Wt2y8Uq(qA#6X+ux44&hoJMJTy@~c(js-3WYj01y2qPZU35o3E0>Dfi#N{qTZ z`$#U!gqVdj7hyP#nUoM5qbV`i1Tt70dF0?HH1AE{xFv~DgXPYC|3|M`;9dJ4T{3+I zXvU^z{>CVR1LpW+{%VIIz-8uXzp)Mm9aKEAL088;9xF<}!?xuLxqEOuQC#}SAG$Sk z1u+ux({A+%d9M8PLAeuZ_QwP8XGj9#KJebs0t^JS0K!BLMHzSz6#|z}b>?EK0`03* zdS7Uqc+Pd>fFk>;-T;+Yw|t4@2Nzc6FaBAKz^cs;cYFjltFCsbq2Hbw|Hu*RQq911 z)cqU@Oxh0fZQrfNx$Nzt4&pul#H7|Tee%miG;n^$Kzk&i*oH}^WGbhj6!Nm01$Qmd zX>B{KSdTRlkD2?I^+ix>b>Hmywl3CXfdIiM^_HP=!d*x@sxd`y-CimR9BqFW%0u4o z%gknnx@Ck&Vm|5nxpThPX`MHepMEMkZzMP0ew!8!asPtgKf^)zsiqWzP1X8RP4NQp zLb3(L)SG4}g}}PIySrV_I#ZX>@Jv_kS$|$S-ehgF8+vBWaO8s}A-ld3hx#ssfh~YP zI=DO7Rp)F%xfeI>_#d6l2%L?qa~JVP^U5R|9r${JKn$!HYzcjX81)R!@Z$86*#84_ zSTWKxc^grIFg%-Sze&rhn?oK|lF~on>QjkXOWtKZj>Jvf@q=VqMdA9ro_f{#ivQ?* z7~ABIoM|NzhyT%$#b`-gKJ@EC_W*mET0ZrnAqT~z05UDaF}{P=DlE2?0c2*BQ*np! zTa0PDtMxw+3FJHl=_~(B3-T+AzfZe0CoB)e6)|`N*LF zn+|q3SKb=#C=D+yrEw-UDh)SJvli?80g{fxg1R>#; z(blWPQ12{~=&p`&mA$=wNP-W6zr^Vmqu%u>5w`xw+ZVY`E6O%W+@S6~? zj*m*!Dh}8n<}L9h=taZ~n3?KGvfk}#=bVr_w6nku%&HzvM7S5u;WqfFdI5rsp4yqp zJ^kYCQ-3sH{Qfv2+tU2zO-jmLcE1$26XBz=2?bL^f@kk(Zo!MOLsU%q0tlmQObvJV zI}~G#D+k`ahTG)NNl$3!MllQTt&O9pDg`#4){u|#Y7ba?Z@7&si4JR2$D2d?K+~q( zV4kh=Z{yU!Lid|XR;?tBf$V05*$i3zuwcoNXwkW0S&5kFd36ftEz-@HeCzCsLSzmq zyj9B)J*%DMS2`e6fO|e6%cZT$&e))nJjDo+z7${2q_Diw$em~sUh>Q7)c&|36Njyh z=+TZ?@iX>rYd4@>8Apgx?-HZCpo!qC*X(2h!@xP$%hU5M#?f*~HC7X-t-~crV}N># z*^LuYtZ5zHRo5toZgQ*I=Uq2+5Lb+yTbggg8(HSRcE)w{S81A)fz;>x9H4Mo8ST!D zsvv|h^@L>J{d44&;VcY42k)b(h^(URwGgp3uwd&?5={nGVq9-rpl{;(jLRl4RkG;~H=vBUV$Kge|P z5?c<5((Of()*V&Qhk!Qtwyf<_6mF9Qr`%Jn%KQ6Xboqj?^{cH2i^=61eLckMQ9}^R z>Uw_%Wj>Cqshd!86bwL3G^qtgbmJ7-)9~96<6$6}+P_gVDmjo=pyk_{E^_y4LKCp9 zegO^Fa~8?$nZKTEqN^^T(()c|D8IF22;<3wRv1cdw8bR zc>ZVRiaEW$6gD6Is2I$|%7V zOq4t+))!2RP@DBhU$K~zAG!QXJh41%&8%rANJ@5v&s?!_Px+z+)3EvL%6B-$uH`*p z4Mv--?!%QF5xnIe{R_gr%D=E9jc88y=2ESE(WJWx7L;d0=EBcY|53zdPAZ=85_SO# z)fwHI{q;r?DydcVOnA~|EKuLMaTu+TM$GPXGLP!fxwx?W%TFAecsN15MufbDdo9w` zOvqtn(2XmGf_0gJn7)Kyd{&NIYw}c-Q#!l$x?WmR8{7m4JCvdTt>F~+JTD0w0XW?Q!+ zIXH3|#dbJX*WIhnb1CB!G0@3OVYH?<$F56#Swp7^E^~FR_ zP#5CDC{@n69AG_b%8ndvb3b|uwO>zfesxqkb5cHaYj$bnuHRd~`VLtIV*&V`Ch`gC zu1^fWl}lI>w8Cr-2zMFcd-7pG&v}mUw-{K|O zHQIMA{Rmf7PL%(Oy?oVRW{T;dF+(=xDN~XMlKl|G4tJ@=*kj{bekF`#(B*g$-l;rW!Os_1yc$pG4b@^1mm}9fX%W z>tkW3%XKuV!O6wqUOS_WJO3#1nV&Bj3!jOaB1sCPTGN(&HAafAAE?1mR+5-sU*l8$ zqXX4>Mk((k+;lxe8v_^Yz&G3rweuyeK{}_Pq`;}?SC4}|LgJRdM41zF?%u)(^S^-^ zwNI^~@68)b-i^iVo&y%wxTzem+DUky#H~v3O)Md|gyXh)!lZu__!Fu^83_#UUWBQY z-b%66^AzcP`o!#kfUlqJO3AlrEij7nckjDS7Uh8urPzZRURU@02D9$eCNZ51~zM};47j2TGnR6eHVIOJ%1s0VQ@Bh-At07-V1+W%Xs0wkAcO`?v_v4 zFFy(dE*B|JmO5A_Dxw5rIQFN#>Yl545|@tR#tznQq^pHmo{hQ~#IU@W-N}w<7>%WU zqeWTI{ZE4tA%|-n^-xWUylJ&P`Kfw}%lB|~rDD%#s=R@aaX3alu&5Phw|dq2b?k-H}Cy!A4b>$#U#?;e!6~^T!8$9V#d>%jGK2{ zO=F^D_QU*oJ#e?`GcI8MS#K{F)xJ)7$eIa1D#h+z-5mJ_6SA4HQye)HS7@os=+}O@Sx6O08W^AW@&M#;c{#ItK z8ytiQG<*nUn|@Si1??;)BXkqyN?^x#<>Hf3uQDsXlU+Dl#w6!=e~y_?4kav`9(iJT zG@qW?K376$=P`aM>Xw~SsdD$0`12z2Hsn2Jn9&Jwy|s2UTY|&mC^fG>;`jTN@r9B{ z+o?83%?|xuj-?B8fPfKGSW@*?`#1WfxYM?9<%4p5n+o^W6n-_E78qc=4DA)=vU*^< zs8k6nQ~b& zer6t&IW@2AqZlSGTjLgFJSK$~CUQvn(MQ?bV)B*3pvMb?RN>{H;z>G%genMATnQQE(SVd50XW zR2}rQ(znWH_NMBEmGqX%TkyU5$(tV|Bu9SABwaB5z$*{i>^|3!rIyuSWter!HRPQZ za&)IvgBIn~!437iRZ&@0dqZaA(nbQ1ki zyb&@hS-xR@syc;|l2je<#{DM$yK_3ss1TW3aqZi$d=J)=%?u6>&hik6Y)-6ER2_S_ z32|)H+9-~(nrkTQjb!mam`_KF?m>kepV!q_q9d==DG<(tR|D=PY|rnaK6!7ky1+_z z?Gi($cd3PA(!&q@LR}usYtA#U&@E5k)JhJ0q@Om{RMpo|45IdTp}#nMKOa`^{$MRw zKi$ay)JtMZiXr(ECTD;knv46Ni2=#D? za{)QzX!ZGcxsyql8*rBG`skR(BXFI1n*m^7!CF-+tf3MmQVHd9xLF9RH%s<+!A`VN ztiJS>qNF0XiLzHKT$qm7Ee93Un;9w3;nj&e(uJs+WAh9hlbnJ1KU?)MMK88c*EVOe zh3?3qn%1~{#X~hUyK6gBvwHrDPgZ0NV%xvHmHC!oM#NC7ANVb|ReM^Umu{XdqY)OY z(S-~1dW>ZbsWkM{mNs|CYOO!Mq-@t&^VN7MxF#+eF!ZLwd?d$LjjSFpNPR^;S&=k& zb}O&N{dLpQ?_Q)+fXEKkqn1K{|61Ustd+XI*81)--3GcRao|_agM~n&^8eA@q#f#Sn{Nk#YxP+ay-Wn0?am6uCeCCg z)Ncvp=TF(W?-Z?j-+0d3ST`74guF|)avs;J9AR=^EBBG&{bF5V79kw0-!VC1s)Wz$ z=5i2Z=I_uWzmFGWyDT^UZr#X5ijt_L z>#rDp=hRe$p7GYn1A%Z~Lpsf?L8aGN+wJ`)RR(cU%m2|Ka$mIvF<$=thD)Q4RrM$E zVf7HSV@wJml-&CIz9~5gh!V_^aip*G2jp%{ZzZKmTR-s9w$<^+tQfm{>_%C-%i?ys zJFnNqta|dGr9yh;aX&`&Rt@^NU#65o_~<$nx7p4YqI|$N`c$9R52*AQIL`Iiu1-X# zJ??d2e5QwQIV_|+k}Ea3EEOVk&yD_x-Bd~6SCmX2-K_Wtuv;Bo#ssXCT-E*YZw+xB zXwB)n^>uuWTkF1a`(G6=-Jt^c7O;%!`azh4?7X!030|*xJ(j|-BCL9k4m?r+t?eJR zSMtk=q0`p0%ejRC*papr$O#iJjAA0i9a&R_vm@VL`w8>$~traDqZ;eh_X@A%HEdFLz^+{P<*q^%(6q$Q8?`gsn z)RBSj-#P^fOg5~`#^4@%GxWS=S5`rT$Xi9&u49gO6Zao%h5kqPc*4t+6?7+;tQX*epd_$I5VU7h&seNqKNa;>?1udVGcJHadX z75#|~qw`MjY*1wil-+)|>5X^XPiz_87KFnlhW3zz-3~buertmjOTP|eUv;sq1#hA8 z|Iw*pfuB4o>|FF-j{8d1byR(4_vgj(p#OL-1>F555o~m!=Ly@y+Vho~+!dlOsb4)_ zG)KVs1CKQwO)%-GctX-?WVQZvxR=CB(YG-L5aJD>*_U`G1xq4`7WxGvzt5gLGq6Qx z&c>qcC9f{DZxyM|ICCC^PTGKW=mPhcl~Bstku|c#%xD z^CHy;0DH|mf3A2d#mG@<$Ft$VmY?5^CqTq8(MXkQ^AjYC{wYE{g=7cLWkp8DTp zCb%HEqyqn}Kj(Mx!bpogircm|`}fpba%!*q)(+G9SI4T&tN>z$VRgrDG)D0k82(nOI$xg5>Gr!LNQL%s65`+`eB?o^M_hM@o)2u3 zq8x>gCce!>$N`?NK^g0dqau5XCHS@99QEV393{Wb&f7jafq(870-ap~<15(qJ0U>! z(0d8?!kEWhQ!)d8lrLG)*bwowx~(R612<1FD*HF&-KXR~#i6UV(pIoj=>VWvS4MXA z4HbWjD^I@iz0hFB@U4gL3_kHVBy{6)$z@mn?8uz}`-Y`~dp3j42|=B&+u@cxQ&|2C zAsUh|X>m7(3Y0El+PTN67956Ob-owyW#8=IF00ozoBwUBrF^>5%+cI52>cr5zebfc z9?k03HoQ-LEutB~sQ>6H8+O|H$eBYn^}`DKqN5o8?-Q?MOrFrLnN3RJVCDJlF zTox`-b;;r+{s*L;XgohMZq(iWTD10f9lelis?HV-D2Ych{fO&5nE zRgKb?7N$*)vi<_qL8RT-q0-nPl5gEQ5@)@kALzb^o?eC4ZVmc!MZLktP>t)zj)cv* zpw+I;;yTssI!`&P>R(Rqtw8S+9IV`Cj&bvGJL-N*luejFGmG)16-8zA95644Jbr)1 zN4-uTW?P2J)C`Gs9uXj;8?(|l&t!=@?UEiH~s4``x z9mpEP(`Nt*i4Zp};eP=!BaBIlh>B^KcDJS_C3sQgIHsmIk_s{96Ibe94Mks4z(p~Y zRbMB)1r1f>ldi7wJ@YtLH3jy%WM*1PDMoVk#lX|cc)axzP&0`}XiS!iBy~ZFsn!Wb z_mM$WPd1vor}*DdSrNxnZa{;>L`d3lC!VgFj~;+HHy8L@A>Z9KFOD!){6}{Y`=Jt} zb}_#>T|<_XmqH)R``k&c^$Fm%%vb`H0{XTi4&z4##E z&GQLm^GXTo8lJ_5Z19KJGrPsnBb+fM_ORm${5)A7NzCts@&?*WwaSq;Eoo_opcvJ` zVtmd+8we)=22U$qH70rI_!h`we(JUMs=fE%P}{#R;1c17ABsU?puG=(*;7(90!$T~ z=x~`FKcL<5;!-ywiFF?tEO?T5YZ`bdVUgH-GueM`RCZfph?AWQfSIRvf#oY-+D;mU zaUOQY>S;FIS^{@0ap%qm7jN0rPelAZw-hnbkv_x%e@0HLuwComR6xZc*}(+3s#p7` zTqPeqd!?A0wW%~OOxoF2j14)T>E#Y9q7K=qd?rn90GbKxnqpKn@(}5gHHm{v!83hO z7hLS%r&^N!OdeU=*iS#PFi2T(AjtUsW{K%anv=QFVv{qf3mV~SA#aCKcwuEda#Vj| zf>uWCK^%yMjMgEhC+E907go@=b84;TtimGbkVU!T|2#p{ApC0V7F>=nBWT2{{s8!& z<{aa0>2jUV9M8X6{*jLEoIh+S^OS)AEZK(=7A}$d@yJN3=OP9A-ukGpa8vbpeY?ir zx;9h2vDcpOTN+^Ay`yih!5m!dzSev{&qCEELIL|1P7WAoa|KE==;qW_xOPIX?W$Xq zyO$KNoestyA4P2W>+;QnLwO~ACKXovjk0s*S3X+Xo~0e4BNnbIfN^4GWc`A(Vd#~E z9N^o>?c$J@5hm(Q)#kUzzYxH`xIT1dGr0t%at?-tnv$UuI#_;hNbCF!Qa)Uh6da{) zLda@?T_00udL3qAP@AY1ulse8u`eKDH5FQkV$y_o4v|ic6FRtN@biU`*mgemTsAv? zpbYw&Coo2&&Rxjr|2R4ezoy@}i=(KB5(3gOr4<2@&RMiL5v4<NHN!sQe~MQhTnF0>EZfmvNzEC4)+@L)Sw zmr93&#TVGE*88~CH9+XG;MvZhAB%$5()0Lo_O6J0K7ieJqRn%XaAeh&^t+>FX=j)u z+x|Rll#>l!B?@)|&rkJSB*qjr5~i?VGb}vnl=G4h$W2=ml|SWac*v$;vanQ<>{jJ5 zI?>|ejH>FJ^x}G(+CZX#j3zP>WhWC8!PYqpzP#N4d5>ygmf%|%nqbcec-+(ntp)Y%&PIT zp9@F8-84<^4@rU{!Yj`t>Ln&y5@R~pf*B114M<<5#lu!4>j)VRmtf;Pvf$jQD5X}% z_=%JKf!A$OV-ex(U4dh+0Xz3Ax9FBb6IX6q$N`p?J9RLG?Qy?~G$9n-2I^_vO!@7k zP!OIIyQQt&c#`2oT_JTT+w|sIqU+sQ7m(`%8Y?c32{oo7od!IB6)ytfA8Td{e|t;vm$8(o$cK?bAG)*y@AwoG2Ji z2NWKiL*J^5%|XGUm6(1LRVGJLix!=ggn*OgZNpR=xaQHZrc}<8>Xx*{vF~bff6hz0 z$x2xNy^BXxgoxWWXdAgT(z=xQrU9p#39_ItJwwUE%cE4LCPy4n>&N@mE?2H!p5zq9 z9v;E#PFipS5YJV-&R_X8JmgF-|pvXruX+1JEuBL5D*56i=sQ_tk$Uz}g7h6)V@ ze)oCn9b+F|TAzVW2rnTIw$s+(+T)QOi|JkM%$0=DJe@p3q38|HA(588q>Ru6aI#jqbO;Oh0SP#b(%juQ_v&*^NYx$g;DaOi^#Bix z@i~AW=TJx<2h~8jIv5Bw&#+rDQmc_bLCRs6v|<1#cJ@L)-co9ax!H7er|^NXNWCTK zTS4_A(={l(6BN%On1_TUdXBSVdnoR@&mQ821I`My|W8^icHF{?YK;tBvRE6v-WujZ%MNMTzFy^ z^7xV0tvWPO%*ly3OKj5Fk;(T4%8*<`iAI;Q!Na1!9YDVmOqa$%YMwSV|HTr3nv^^ z_iS`v%5KYNEn`95@0a8{G>kz-oZxtjw(H4ZRr3OTl;S-{hNiaz)G~ZbsjKb&Kq@0W%X@toB$f8Cp^Z}oQ5BV165*A2}8zM~U5SXwp-dARmwZ8>E_#LRyhAne) zxa(oGgFjNeK5T#V;_9MHBSWG@9$0wKLOc<%+9^?=#`I>^>RQ}jvj_au+9@U_MvauK zLaki}b9VA@;^@h~$>HGebSnfhJrUiF#Ch6iwYmlvt;{xTx#6?bx8X7E0>HHaoFc2& zd^dR3Aemyy zWq#igyiazJ~^H-+W8q{QMogW2Cj{kCmKTDbI5?O^A%Bm>QJ|If4wG!R4;G z!GcWc2WRoF?EUK>VhkDC5=3GM9^NZ5gplmpbxY~hzIu8%YjNRKE;onUe6JeO$xLC{ z4>A*DG-{?cb?a>YtBtHssl9UHa0z$>f%*|51dVw>eCAQ)D+c=9E->eU4to{$K328$ z$Qi?=8#DV-0KuF!j9`P6y6Pr?QDeQz;J%z%bs|$_FJ+%kyOM&)-U`h$(Z(wmhy*=p z7oLVfF~(cE+JcH`rrIZNopvAk-JE7SJ^*-#Y$}3C0M5XG04pJM^se3^G6RaZTI=T{ z#ef@=C)Bk_pCTz8PFqbbt#(`Y&o`!G&WHL}S(F~&T6%%$Vj!+n1iO2Tbf_Zam6{iQ z@uF3gj`o~siqN)o|CIDHezPvW$noc5f=6Zs|A{kog*51H;1g0DnI$m#{8 zW}bS_G1I)na}L;I43zz&XoB+vKo9`Gm=Ie|0HI*LdnAh-0XJJGC%6^xNRw;)hq(QB;51*(xv9!<86{!XKSws2Nlt_T zrkX3jU-j*iAGdosFlW)ur%eZSu~Bd_n&id&DW24QIO#Sd-JG(ptU`c9;FNnR@z7 zy6GZKmx(ypKL3V&C=UIKln1t3wlKuMS10aX6sQvHW=%dOOHf<~|>y zwFs4iX~2b{i~2k0e2d=T`m*6jSmY{w;up-pzS7-n_B7_^Y=n`E0o|mjj?e;ybNgLk zL}^n)u&0wn!)o913naev3Z?B+tNmHd*wL7X@+ zX2ft5as0>OOan$aBWjzU+#BO^({a;^OQ}|vMok>9f?6H%tM#(`aP-qdaU#Dzb6rBU zR;q)~O8;U;5QH7R%Za3ll{#E#7y!|N?Zu-Ed@g2xV7GdoADT=k3FRtpmIpBJGa_oE zV%Et!HpldT`|8&|Bw6$T@pKs5Zm=8yxd!9*9WvCg!@5R^9$@%mJg4saBGbKl8Xxb= z5AdXte28}me~{uaJlDej_pfT6g=u#SM}Vm9U!6~XH@u^DdbKHBr4F98rWw3@+t|fC zBCJI-sw3;^3yuVip4J>DPsk!Cx*;BH4-0D-CD>qVdXKrOkT=?}Fl4tAk7%rFU1Rb) zjuZJ~G22F4e$8glFHbOX@Z5Gf^1Lw!(`AP{L{*e~{3dcV&k{doLc%>E4Cbl@yZ)Q; zR{Rgeq&Ybqn9C8HPu5(7sC+~}Q*EhZmJ16@aFIx}UfmtNZzoRuGqR2$k{|c@s0H+!OA8-vNQ^BJ2>+zuZb|IYF59M`tquO%D0nVk|=#Jn8#ZRA}$W?IM zb$rwRuHy9VMm5IiA4LXZqQqHIWT4+qBlbXnTmrk-I9arXJd3lRh2USq6VFfnQJ9&R z6#E8?YCJ*OU9tHR7W(}Jo(gRj_6>MR%2K+5 zV+EFqwD)lZn>Dy@#6Zv6K*hOVllPmlp+U7#c9t7|IUWdHeNA_hlBzApH(g=2r9|}s zV^6+=#kPW!f^|V{sdxL;qZ2!_$;uB;#!s0*v!a$ED#;qMMnkpZpKeo^8kJj+7rz@&blMdEP*$?b>V8$ z4DhEEYXOwzuQG=U3oA<%gthBt@6wj`-y2U4vwY1H*xW4!m3}!85gX zO&lf6tE)S|QWLf8C{r#;)tBF4n^OFVA>nYC$>JUX0jeR7uiRv~+6}oL_%vqQdoW8q zi>MRy!@Td^&JHVtG zZ;ACGni(X5dpqV4@@(*pGx9AD++Oc$Z5fP`=!FvHnbL5&Hp{1@aE+C5K|>mVo86n^ zyM6y3g{t>GUbNeui8jG?oPOFOEC;I#ybuHBNU=ovOIcr6yiZ$BZ+-UFDJA*ezL-FZ zBF+bSb;;BqYi;Uei0mIX)5?KtUqwHHcIU-x9nf{WLQDGH`W|}$zGJuzx(ja&3Ru$! z)O5ApMC>nD8>%Y~Y*fW9y==GQjkvRAKS-HBp2t8?SED@W$ulWYjsO-i9BOt}k^HH0 zTi*@R*0Sl|;XkF!O|EWIErIHDFeKRJ8!4G=4pP=B=;}7h3S$j+BVVDYS4V6^d!XEK zS2h_XOtC1%GTBY_#^xF>^C*!Z6p0aczhoK0S?J*+I~UqTRswZ!88}ad9TkbG6IJYG ztS>U*@tnky!O*WVeGgU4TXDzPYxx(y4*42+I?5foN~JX8QW@fh&oA>ToKh!~>l-LJ z@eR1uIIzPHlV1PQz{iQ*R%YW{li2}>tm;Zt0HeEfR~FvP`SAv!X!8EsBEJ2%cz27E ziyTZTdNm4GH5L)f=F5q9#j!@r0bK4t1$bWogv+EmTSVc>g7^i`J<#z++}x(0k#s!Y zJNJ?_p>Lsb?8>3iXRd%~1%+QVBlqK1Yg|7Q@0ac5-0^~5UG4G)S&nDY(-HI)HAJnN zXRX^GvKXYCjjb=%{Ox~Q^nr8FG1;XvNaFGiQD-Vx&Vj5vQ}@R!fMoD;$`eN8Tj`jY z<>*uIA15=n<3oj*PfMkw*xsTj`~8$%`V{gRW($h2pj81X0EfDQxjk{-4X9F$h{`wX z-%0-^ULX^kj&GBx)AJowK-i7}5aWV{X6cRr_zp;C#+jwB%+)0iAO@|kF1ma)z2>9G zMiECkn7Nex>HB-u3R!MW`}Vzt^q2RH9wBs3iF?g)%gN64-&$3H1yOUu0Q}1eOFAmM zAOJh-dUwT_=Mpj{@OU>{VXo{$WA>&cpZrzC>i+Q^svE5xePk&@G!%-4+*L=r!z_z- zpEy46UYQ-eVs+PJ;OYx%U(IFNjGI0;+A9comx8`??+K~cp7&UAY^yYK8G?+lurL~c zmHwXZ3;5mRP7`spn5G(<9XRM=!Aw}hs}g>m$y~gIv7DH+38}`H2~HGrv}m{%9Oq?X zsr7iAToROjp8U#h%3o+T(KXI)LFRB17M~Hcae64h7PKE50fG`J`V#F!Ti_rA)EM#` zOdueM))Ok64%LKyjT4O1`#Cr|^;GnQ{gGA7to^{ZuJ50@3AXpV`(FpXzz31y0$qy< zuDT$`VBT%ST+i4Y!iEyGl<>^Ud6z8STFpmRIoLZ;4xU|Ao6H}=tHZ?r>(>6v;2tZlf3Vbo6q;7egoD&3!Y!&dSSQ5-BiH&@v z=?YB=XFGSX8EB_>OdDN&Ix7wO@>%r#XcCT6NP|DQxo80@E>2HIY)L0ab1(N!n&j(e znzsC!U9Z=@vHpnqt--a5r*b=;MIlk5!&($oAJY_y@9Pv)NJNccxhPaj_07kI)pe0k zWG>%Q-OIaV!Rko^U7Tve7pZesR~iEq{zmNrs5Yd^{ARN72axB5TSK!zrT&$9 zn8JaQ^6y2*%-bs_n2%qt)yehWck%b$oBWBRP0OH-yQPsgHQHR=hGecHeo3T#-X&FN=|P*fBq1_Gt7 zi|e7yP4hCic0EQUUk+b!1|jI8;MW7yrmS#OeIsC0MUha?v_D z|2E)=3N`ZqKT(n>@NIZXIK#$Llz`xoB90i$kb*jki%y+WtDf;3 zk^O!&b>w#n|J6!`-Rf^=#RbD7abf`UwF; z(w%kd29XjS0e`!M+DmbQxe8Mjr1|otL+)-d8>7;g7=G@nq8+zL8n%9DEWCrW_R>BK zLMlLoyl)b6(iYNM$sQanda(t3!iMT}SuT6sI+rREl=b@OkW=O{Kn9XVn!Ny4|E$00 zwAFDYdd>-22MG%UvAts_$p^sG_U&YA6cRH=XmgFhb3$+Co@5X zGEfvMV5?)`$e3=rVz%mWT)s=eeFAe!nt25j&V^4DX{R#IvNKDqz!^l zLRN|Fe!*JwI{@WT{l}vqecS7i;~XWtvch?GrH@{W{OHo@Jm;5!RA%@J{Q6Ao#|J;( z@(0x4G*W-ByJPmw__?`>>8RIr+1qXh^;Ms6DGOso1s?t^VO|c*%g3661;sn)A%@|N z_jhn@Egzd%8^T2eLLXH?1zMlU;=j`viE*9kVRp=)t$f(sakp~eZ<*?S%l!WH&gjnL zo9KkCIjAd!*^}A;wV}AH*wG`eJ@@JeU6w>cUCjE%Vgh^3 z>SVq~_(rXV(d+T_=&cz$i#Rt z^bM*2$IPJ!;zRZM41T5EQoR^|Qs~GsViQm@ zgx{m8`Mms0lFm*%uFU$3eGl`LquDhoyd(NRup>dF1-2hXOPW+Oo*LofQ!dT4Xwdw* zXB_Kzr9yC;`NPz*k)^LJj0(=2i`@CuICWT7X2oPUrh-xBd1|whliK!hxuBglYVSAi z)UTwpZnll9FLi&EZB4C&NS;d9HqSaskyMUm{|HSn8dZo>`VDq{8q6ryfS)w&8@!(4 zjhH-m&{|qLm=tTu(2o*Ht4S8gDt~!_wj}`pHU$o8RU;)Tk#72X`s@j8Xuh9iX15k0)5bf6lVSx` zF?x)STG}^ll#lgH7ItTimu}mYs8&FNR9rpnv7#C2#pNC)yBs`uqP4TYzO#Bp{L9(J zBkjhgrPGN3j)ph)WUt&r2Y6g6+HzU^;n|r;JTopw?3T+UTu4tlN^>e!xkF3Sm%Y3* zwpCq*Yj(X?cxM>{MEPFT1_G$UVp-V`+*hYe1?M;RLWYgCO$kW#)N4Nv9JD{lj8hfa zyPNL#uPzc*i`04A+&6X*hV}Ol#tTF2Po%Y?y_J7HglZV zI$I*t@25sxkZZ4`Z#ZSn=5fb=uUv3wjvKS284avldGp8g!uDrNt#%{Y)4f12@{_Yr zeI07<-B-8K`L&DLT#kqw zO4ruyn@_}`Hc7rI%Kn=n@})WyMtwXr{FQAH=N~`6i~acd?t$p39J7gL3$`FJLjOh4 zk|X(1tKIUIbZ9~Q0`)DG()ZSFP17zPD{BHS;}zXHn(L47h~BvQukJgu`MCFWiIMBn z)_8+x(N1mHecVGy!B6uiJ5QMw9N+BfsoOh`B&2#3OV9qipB~gT|Lvx7*sZR|J5UAF z5w?cR^}#d^D{*(v;sK9_as9$9-kqWRAs;6PE}!v~&BZ@$D4N9=m1pwhL!u%t+Je+D zUW(CTo-JrQsuaL9z~?KdO0=gO=HRT=YeyIXx^AxAK*x>&y1KHZ`pJ;@&ZEF{wh@W) z!?OC=3^D8Q(aB|s5tHcqH9~*mG=#Vg_eMNIO&3Xp%eJ90WmL%>zNm;~YHyu~I($My zY3Fx>9IipG{P(b#mHnOm8kt!aEx9P=Gp0nrmHRAYHJ;+hhK42oL)_LTkI6@Hf0ju4 z{K$Q8^TEeprngVyhBgY%->d(HAC*wfmJU5i;Giwm!hY0kIQ_XTBbxW3UTuIfJSp0^ zb6TI$Tfoliji2czxVxf{L8hY6KyBboQWH#JjIa_l7XL}F=? zY7EqPSIIF>>D=7#h#ujMdWp_uF5!A~_7}PyA#af4dBY0!@u3qzfblRjk2b!8cT-+@ zn^(8JxGTj)rcY!rFGK^O6HE_Wwub-ZFcO*hZFns1i1>q+9EksGK3I8EoGko-N{(%i znE;qiu74Q7=X7bpzBnSb#phvpi~lH2OC7~mw1)?Y=^+%A6pv*^1EhaaLFxv_D9`8O zUz~mTN8#tRAbOJ{2!7c_a{B)Q#_R_kf=`zrv)@)dCu=B%skc=A6ZvV`xNes%!c=Hd z^PFwNs6mdGm-nW+c`6!KE1XWg^MKg-662OjCmEV~=34(e{N?X!PgOS(-Rh3dFzlt> zO4lDhDumT0^80j_IiDx^33&&KIC)yVpMUl8=(z-&^4@F3??5Nomah zx$uD@#S*&0O~;vUe0J@d)ldV(f?Q{i_N>i>|Eup9*myHjJXW-`afa>JI|! zm)=tcL_!ZrEdFC*-spYe z-+_aA*uzU9RKvcd18UiEsyCCa(lhAoK8cjM-%1VWSUiF9iN@nZi2&|2II069 zok4t2Sggyh>1g%$@AC>n#VaiZFlV51XDkYA=elTze}xt5D}P9PyEmAtVG(9o;ul)s zsW?uB@Z3o}%M0w?+r4rP>onk#7m+P=4lRNaTwnk6r3!7Q-)7CJGf2QlDf2!<%6Z0% z=$k#!>t0!gFN!6=cABKmf&BaR8G>jrK@#tWRco#vvU4gSx=&*E%Zc^$S4?Pi$CMSU z3WB2pDG0rl!3#NcYT>2Nt!gJ)U;Hw(zotdOpkDa&@pn6l$NwnWOEZDp*XW*tI?x2R z*y*qE$Idqm%zDz&_){X%$yP`9ow}{^nF~?k4Q@vGZ)V*&s$eHL+gqSd)*E)WgF&k3 zzk9oUR%iYO6FC$eHp|);bq%Tx0$5ug8jNcd;Jk%W@-n@8#heuG4?t7|fsf0elD=Ql4jk#yTl4&s4b@TfkGhmkt6C;mMCbtx5+eU*2;}^40D!r^Vru3U=wx-QBCk zmE%&vb(}#uW(*9rk%|lHmPhD#qwi@OZju*4NKlM9U4YJ2{<)J8N-YiC@9m4WhNQAj zDyc(yGWbur>#JkrE2F8)83b`0qz8Ck+l96=BjE^m?<&`ZjDOCebO)7##Z_=!Z9Ja= zXxsJ}vcX&|Ez2?8fq@ zM}x=))gR0FHem30#v?FC=0w;lWak#E7Oyz4X10BA&d$pnxwVXdBVyFucKB`%3(v8C zZTvtb&RJq;}t~u!$uh(TR5YF}sj&E`T6E4wYUl?ZDNu5C^bxN6J8K;gJd9!ZcrYC=>8EE3x`WbJZ54^xO7x<=aSHYcfEAg> z`l*)pK*?Oz9Ovn1ySP?WWJicZ;7!66+^@ra6~>(R?SSW~*CJv?lJp(UG<<0tesD-T zo9ha&eHNF4ywHZCf#RsK`G9^WhwEdJz;=CM)^k>1{Ze@RZWk^Y+d{0xje zcos&ba+f>_suPcBzt_irO^n-@qV+*;R!Uix?kLPGIw;n;R&(k6qY%Z-O*Xr;MeAy( z$#x(KTy|qQ)j(_QF#<7+WbF9ALcNe9TCvG8 zClBel49a%#3i07ZM5Ydd3D31af!~CS5!vwD4de%l&6@?$UIIhHix(%91VSt%OAYX& zJk1o0u(-8*5gD!&$!6c)6D0FJkEctLU~m8pi%PGw3Y~NJ_lpC`YUWKO_N4#pipz zHQLjO7(48r8E}0aIGnZl;0ILcvs7D*<+^rd(yZhozX4M`T*tA3Y9W{&r~}-~j4v~0 z-FL#WO!chX!w#E^W5bsRV#V28pIzIv9=f^qv>GF9=nD3A6FKTYuJ+Xe55CXefc`mt z0zDEG>0|6&6@bm_Rk?z-h~YHER+JVyurl=BDct6_V zdp}t=GSS7CtuhDX4)Rm5`K6>GbLQy|vQkR_YdlK|#Gg)wDk`vYkKY&Y*>#(y} zup(2-qn58_xpD+PBrN;ER~+Pqr;H0CD&pH9S06+fE{xsYd~m;6-~IKYn)Qx&i|WEK zEZQ7v5Y3Cr32D_t{!m1j!Fyl{#^$joVXtyMWSHZ#kJT;Hn5RZ>Su)IJj%LP+*|rcW ze6TJsQQV`LNQ;y0q386y-J8uu$SCg!(hGjmjP+oie+hQZZi~za^q&Y2A zg6BZB^!r7qRT@XcK(|FCnBjmd9H>cv+u#CvFYIEW7%5kJ!b{O9vt0!PM6LtfPqE>e z{14Ye!WD0bq!Ferp}U9%4EN;|qBX(j=dKLT4N|653$@Y%Bvj3}96bkjxdy}j7gT-o zTPb^-$Tipd&}<_`4OE>$Rt=NpHXtWEt}cv@tqC@)xq^IQy(=s@a8C}qN(Uf_o{?GF zF5h>A6AkhaTIt5n@lF!DtS^LZ5%0a14HkzZ&RO-6pRgB2hjwn@5FL78X9yw;Sp+Dw zG}}3JKr6CPzY0B;w3T=Y_)aPN=h~$rW&+#n4682rj2y6ikK&*73boi}Liprk8IHWk zAGN;lXF$6?72q1YA4|r}Ggem}w=GRT`1r9eIb`@$49BP%n7PzM+;o}+HJ3EZ3mfV% zoPjAyd@j~jNdq3Hwb#pXtn+iST)EZH`zRHac`kgps%Gy;8Lav#?p(ww{ zw_1$@G?o(w^EW$Ga(&*$HNBnZTWK#On4w3+p8*Y*28LhH6FHo>#Jo=ilz$6m8FRdK zki?ALT;VpsmlFhh;8m>vnIMXMH|(uu!bV#|jFaNyxYr)ve!bsp0T{9kk)An`7FeJy z*{+978-5ZmtBtdbM=1+(${wY>&fe;|5M7kwe7bPiZ;Q?qYz6iC_Za&|B0J(v7z3BN zPZF6N#M$LX>V`kjlWw#p;QET90OW-QA_bk^55MNCZa(!BcOwV6k<*QzwK8d`4hZ5I z)AZvU`fw#p=ZVpkKj&s@PiSA7yxMb+whff)9I_OMr9IMlFe~t}B~#rhd1Mz-@*C^u z#6e+o-RfSYNQm4401x^MA_z6~e?Q>4fg5y_`HXm#M>*xK#ul9Vw^0nb)=TX zm7UDf&G6Db-qd878oBKtUvRuj)~jwe9s9Alj!-fsA^cLFkkajqU=3FiKp%z!7!%nZ zTD}3E2iWr2%GtBzA7bR$E$!(A(XlLskfkkhra>3Dw!Z*v1ha=HjNo{dor#XCjHfS9 ziuM^lM8#eukujR<;bHroOk-SgPDse&5Iz>DJ;Q*yR&J&vXH!wI+rC=#SA5k`Gpk|g zdO*VAm&vd|OjlUPLgB63LfsJ2#W63p zQaeH2-Js=bN$7BjcQlsEp`_hakI+&@u3A=68OB#p&ih9r-#07@Y?Po^&j2PcX&Q`*~TkDQa!og!6{BwrB`<^vU56>JH4`eruqjxisC?wjjO=?ajgOHgWvf%N-Y|$D6+*F+*Kl-`7!1cC5z= zd}77x(&YxPH3M@hD+L3;d-Bi83e;zLcw3vvhcZ~pNXFf2K^0s|Z;J|!oA~e%FLVo* z`}eiA^4W0T17OA*o^5+IzGG?=S4XZno~wZcRX%D~==GjyN^d6orN8LfLo}B^739hj z(_$Jp$CE_*cpF|X`JUgiM1eWP@{{6bE#Li^uPyDC{j!u} z1s?8HPcUY^!eSCrJayxX4{W%SgBzt~f)X0vwT$l=yr1bnLGnue$44)dN&;;3-)sDt z4hOeZI-q2kQlSvA?Y9+(1gZ)*{7HVT%FI=>c~sHMMR_Dx)YnRVEWVYs|BdhDL}H=J ztRFF&xOeK)-!90p+5-!3u4x%^wW%O1LTcV#wwCGS)`Sw8Dv0!m^WZ|m!w9fs)_iK=A}6n8Jx{wOg0s0{9b|5m;VzV{tUyH{)Qkj$tla6R>PX3+-Q zA9JE^{j(5C8d5ridrplPaj!=2{^Zs8rQ-yW$5W7Apb8-pb;!1x*&og6aA6UtBycG~ zSnOHho~X^bUQ=JIxerD7X;N(_KmV-_tFd?#DEpTnf~T3T?HAHcK~w9k#_igv4I$8nNJ8gg!&7l-QecB(T=GD^d~Gmq`kF|LI1~rS=};H5G1i^aQjK zGa67xMVm{W0D)RT;(a++2p}y2^fxU%>PCU0xo=Ka$D%@FhR5UPr2Ldo)A*x54GC22 z6)%uu7)zXw8csH`h_IQ>8rE&R)dgoE=o0Jdh zI!Y`l~wkV6SL>!^rY^m)f#@r~%l zyyxRZ<0~rLsR_tVeh-pU$yCGNYm$q<7?$*Pgqm`n8~vL6p5Bh*idj#>-~RJhz1?J` zJ(U#N&S)GwkyAGp(khZ=lR95!Yd|x9?vV^REybrx zYL=B}RRwiv%lJCe?_}Q0gxY(uB(IM6GEUrDE;E7VfF1~B!S^iWh>)qmDY9&!LUa2) z3+-axqm|tk-Q=?umFb`;=2Pj)B=I`UvKUgr%&?3e7ZpFd`U&$fxKBHPWPvW~&i&;6 zk^C5^+P0L@MLPT`P;B-ZBAgdD_soKCjI)@E+Y8N3&RuiWSM@%l|P$#iaFo4 zVx^84LY_S`T_&)0%{^c1w4C!gVc?M!0LXm#HW%MPqa8IC5#9)$Q3S9pOKc8WWg^2GQ`5n3Y9!sp=I$)!q~s?g;0D*EEIWuU)UhGcz-u50sgO2R@+D{L~G)WA2z~R+}(#r?XdL zh{*-od-pvkK;$yA_%D>NvfZ?-zB$HpAhGS(H2+ItZ{{q$HrrpNqD?!DBoswxmm*S6 zqGq;Y=K4A~Pk>Zfz2Z}j#i6ET8}e9!v(1w$$1el4ueQeN7xgQv1%Xj2aAc4;D!Zjf zovx;|$KSJ~#-!q#=VE|?;ll7Wkb)*Eik<)I?Jd#C_9ns^R=Yb}a;8-z80c!wxdn>g z5rr`Ba17v8H{tPy=0R{w&MtUkr5%i;+K+2KjFR3d1KSs4w){W_vxg`12PY+Bht!+T zHO5Bb)@HPkwn^~~+{n_!ST?{)*5;#&t8Ms70Cn@Q90?@sPQ9BV%3RboIC%Z244G7@ zYe#AJ%k5bh`kEgbPpQ!Q=IPc?Npt(py}>E@&qW+~?#;VOi!9!b7n?N{6Vq3Nh#7c( z(o=#OpPL{J_N@xJEsR@d$%;D?KuH9|$_fRd>OC%=+ppcr^`em-h8#ZG`>H1QNO5kP zTtEs1JOJ07GHrjrcl=444JejrL8u^5$PjSXw>8QV@t5N1Ps=x7mFl;WObwm+N*>7S zUCa&V^(bBE?r;0G^G7z!t8px@E}%`Q57F`!hGdw8LVf>Hq$k2u>cKw0WxJs)pxcg< z_U*zryQGpqI>Uk=8=K>P+wKm1h7&Hf6XmC74{XvkCWcMw;thuRG@wHfW7BRys*+kk z>{7*bW?~<)yELyOE~DPDv)i1EQN^5CX{s7Me%wlZ%Qvx)N2v~{;Kaetvcf-gBJ2g| zJ<(Ou@2zcGOicg-b1TS>;yo;SMWlW_&;yXx6vW^~gka8;JO^3X?P$wDT%7EGe@BKy z?k@_?x^z{}@62gU)&{l%D=x-JkM^}45bogGAo@UOXjm`$yN3wAgII48Ih# zm4#eyz4e%mJX-X1`5C^#=SFHLj@#tLOzQ)w6+vv;ap4`iIVCZWTl|=z-BMBC%|$ZEEg+brU3?SRLSh zJ*khY6MZzAXNI$_`Dss!E;%Ln?@q4xO8o$LXXcx8Pr06IW_m>|E;Go6`>T{WF13oMv8 zJtp||w$nAl_RiH`%%(d5xm1S8`4)Uy+@Z^p8>(K>MZ4`nb=A|-P>}W%QJH3rm4)MV zG-scc<>N+CckkC~E?ge9p5?D?mw}8V_0EbI&OFb_(hjFEIb@U(JKqz8#L)jW^?c{> z=tmg6Y0AhaFoSrYDl+KmWe@0%3h#@;BEbDzLxA-M(^UiMC4}_X<|o?Me-A!yM-5uA z3$gtfD<^18lKXd+175D?!>p`n%@VnA_!sz?V=&@Hk4!R<5_{)^_kX{iX%{(ptnpb6 z9iVex)Yd|P_uZ%WPn&Y?<$S9=`MIp6$@2^eeJ7si`Ay{>LX#?n$oEspUwSrk@nnqg zcF8-x@?ArUfjtA_b(TjeGHO>iPhA;r#46MF(xDRvq<^5;VKqb#EV}n4%;{#Jgtx|C z|;L4d`b%ysO_3> z9LoODJS!QdGY@PTxWsbtq85MBAt3;3{#^xo=`H5zz{@D;dtMu7)}&|VDs^)L%lUeJ z4ACC}IOR*WYu4zKVlhl_hokqfMAFxxu6wgp%WTRS=X00u96p(D7n)37Sn@}c@ggYi_-cnT*zu5czC8lLlgROh zZxu1%A>6+%kP^VO7~*u`N)W6&{bEsb5Lz_9GxiDHZ`}2*lJA4bLW7mcDSMvz*nzkh zB-;W!OtPFRKlB{XTwsx!*+=l*b<|o;nW#B`XK*wO5U{~I(=iq%OPExbUwy4c%GCHg z%@(K4)(O{&3g=aAs<%@IsXoqcBsbsGsJ7#*?IV}WuxwDTRbs&7xgVJPF^1z z54D&daR}nBZuOp}b`v|vFul=|q=4Rb%o-}*t=gT~DOvBHyz=`|RjB;4F6+{J&Qsbx zJQ>XR94QWa^#$+9J3qE^F)Qis#+79KV1CHKO|=MZVVBmHx?|A|o348x^XmrbdJO@P zeGwx;sIX~NZp;bhN6>4BKbw6Hey(?7HjvF`HP72^dL@e2SbpBFDxaBVRS--0kOZ^q zbjcjK+jIB#4;+=pqkp#B-{C*-(&VpGoVD_IR%^34uofrowoKu zg=m89u@?3ww|vFJehmz?LONhCgFNMB4b+Hu5(m~PkJ1D~m_{lY+WLREdli^Co^{Xs zdiv7iS0xqYlEHiTYi|~pcC&A)e?AcTN3lPT`s$Llx52pp<2ZJ@J@Rz8fw8xowl)H_ zGJ^g`p%%x|`7mJ4PkJjVP{0yE5=44R)4sUWAJY92ncZhik(B62k)>BRDFvZ18e_f~ zLeui;CW)_ye6!9{qL$b(Zs(pV4^(MTd5DW&baZ!Y)|7cvG!~!#^+c$O%Yd_FRiy<5 zeWKl_z|t@+HhDYa-uWwFGjZphkM!amOS8wGzWJ?czk8M6T8vCskFQ;WU#XeOq(Da0 z*-4XDa(FT?>f)G0H18?$YAk-I#PpeG^IFX(nn=9{wVxktcHScn+Z0N5u9z>{zeC4M23%V8 zgD|5Rg#`JZI%10RqZQqge~aew?QJ$Qw-9&ebNLkX(O`pFv3mfU}4H{ z5f?|N4a-ZTct$N7Q!%Y7rDT!f|5QC(x&H*DUCP~T_?v%o;FbPqM3N2iaG&Ie+I)Z! zr#AAOF6qu)O)}U~TPYn~bvs2n!n%pCU28|CP2h$AkpVR-OYaRcis6nV!rC3kB zQXid63hP*DhEel!HUX)hh}|vynq=*(3G7U^Zmd%UZX9cEk#8I8JKALazP73hvH2u- z-quH3%Tt(xmAYi505Y%wnbAGHmLDUi&?YxfbNeeF zj(X^B%U^w~YHg~+{!IA0M#u3;$nyEP=biG6zcnVMU-TxqT)<~DPv1oJuK#9AyXhmx zd^hE{M$z9-Kk#%<&!j~s#P}pMX`Us>M9@A^Ik^IPdnp?B%;V$K7$uhmzd7sN>4@0R zgSR3%bxJa$c|K_^e`lOZT%EtE7dI~%{#DU`PwCnY<4EFv!Mf1bJ>V+H0haLLY5IAi zRPFqzV$Je@c-~GSTwgFSk$0I%olaG#T)p$x+4b~?i2ww0a#QkR?m*E*Ez;r5P$M!D z=P_*njLJmjf|LK_=sX;${{BBsib@FC<0hm+$jZD*$R>M-?2OEd>s}*!g(CA-Rx)m~ zGOsn0!a2($1t1+o?M z6m)^JG?>Xf=j}z& z(5qLWZ?1qpK?AU;TXtLe8!w8sc7wdA5J$uBI(|lZ6i`1Km3Hx*_1mY@?<-(<)9D_^ z2I6Dq3Z){Lje_qWkF|$cu^Yk}Wd}n4lbv_AxNF{UzO@^?uUVpymDFin>q5536a+uY zy3>u#UY&euD#HBQS;$NI-!7mU+`dIkksfkVscYNw%r~6Ee1&rIpK#hETqFNe9>|vY z=llw18G~osN9|P7e6%0n2qPd#Ha$g_J4K%=VN83mOK!D#%X-D5nL@#lDv;2-_7P!%)UG61gI7kqE+-NNulp9On|uOpYVVb$+M8LD_wz{nnBmv zxtY{71Uvh`V0;<4lcs~;Ryn4I><#j&(A+Dd^(eko+90(4AH~iX_4^>MBG;eIfxyO- z;o_q_Colf$$6qSxyD=C(w;0JY0P58^+*7+`e>eEOSHBeHKU?0JDk!+p(%p2j_SII_ z0Q^>hkCxZ9K1@_Q5Mufl!ExwV3*k0&7;rCkQf}ct-iUHC_(f z^(4G9k}(T=>D#Ye@kEi9pLISnNr6{41Qh9C{Ijm*_alDSzqc1>^JdI*j2DGic>bdR z?OemWtU;r-iOV{^CiK(u)x)^_PaiR+%osa40^3M=3vCS`O zT|q@Dvun1r@8DJSc5Ytk zJp;D>-yHuS9Q=7H`qH}qx5pZlSip+HWg=F1Xssspm%DOm?U<#L_0_Vy9VXI+wTmZT zH=`*nT&(hk-sd-~2YL0MC)93_)Nyh*+k^;u&yIcvjmY+irG&s5uHwpBk0`CFPez~F zYT}qrYjQEtvEBO7FtM@uUU*Gkj|U?|Qp;U$#njt`z;h1tvi11B)~|Sbmm^-fFIs*_ zk3BX)cifZVuz#8oUq#jqpY9Rz%((H%J&~_9CsSLlg_&~F-)S@l{ZeMQY=Jug#@4O$ zIag%~!WnfMw`*CUIf<$6rZ|lu@MXJ`jxWChV^K*$)T$B}mZrll4pp0ySW!7?4aw4; z9R{qKfTO-eb3HD(#c+8jrRVedm81aRebacq9ixkW;rXyTn9CQkbv~`6tvYQ@4eep( zrg277Yg7r3mPaR6j?5a}=qaBAA?<1qdn~v=M_sIeSu)_-{N+TS#PaP^(-6~|qNlIq zYFnlr-?}V6)(13OJSVEf5FJ$v0sX2CFwJy{r`ROy)wDpHGL1r!=`>@{V ztWI!E-}@H9Rff6pE);icC;W!Z7VRnG4kWdUv#qkoWe;)qukJhAjG``f`S!mh0qU-9BM8x;4$oRJ1`PZc{<>!c zr7zeb=OQi_VE!Y9&)VtP>Wmu&n#8?IjgD(p7*;_R1J9gz{inb}#N(JiYavvfZ%%dpw4We8sed91BY1T=utUORAsWAnvgCO6u3JrA50nsS3-Bk>VT`7pR_j~H~ zqH2hnRc=5*UEdwhn4o^S?Db&}66L{rjDBTv@J<{7UgUz=FSo}e3u{df7?FvV;Z;eWy9`uPt znOTbM?zSmR!XA-K5^cw?rBqgodaTaxSa`4IY|Koliknhqh4rdXz}b+zflk>K%^3?D z8z?KwnZvM=g~u#dE3>*v03pd-0`Jg4t$b~06HZa`z+fw%@0B+3w?FfQGwWHP-SJEVqun@4LN*m+n^ zJY@zjR&336sr^T{+$kd0?2W@PTh;{Y?SjXmhZaaMfyUFi%9!))04_!lDi{FDeh7Y~ zrkGKH^3Ml&FxJXJU5*C%HiuMvS&DLkCxU*#ld!naZaBlXWk6L~Gm*`zsmAr*RLf8H z64Ix)!ezG@h9tM_>cBU^EBOdsxU1d!w#Rsv_h2`MN=@RMI7NI;?Q*(E;~N zgFXwljdBG8Z~9@o4Uqe6bAkpC6B zrg)5$Cu9>P0F{j+2EhQy=;rhsQf9&HRa3{8>`czpRkmcwz8CyOnMt?t690t{l>~A> z20)BMp|d1r)s=%tW!X`p5kahn%xlN2gQ5^SLDJ0$PGy?;xXbjaN1CrcXZKw4RhS)8 zetemr=uukRc5lMJ103U$&`Z9PLteVL=;YdQEj5%#ju7NoPZYd^5FpMXQ?LFn{s^Z( z>>Ne$QEY2xVWkBDq~oqFSp(&lgH+KOY+7|m!-*6upiHT(v}tJdq`tLHPz(QxNf z<{i$G)Nczd27To_tRY5U(LdCdbvBXD>>4^HK>iBz=8rxlCITsPvoS>kD&k9$D<0ef=Ouy0+gKq{FZFK| zvM>uF$ulUW*1^78FMnDzy~Nm>-evAxO(|)+i$6;OVov?KEl0ak6D*GbAWv38mEnn} zQNQ*BL2dI_6Vpt0D2)Yfcee!GEg&F~sMknNNHgXmoKw_G8Ki;NUx9bGKA!EcV{hSo zywrQn#1-!}dBP?4>~GEUg9lxdzptG~*yY}DbSgs^<>`lBW8GXt!6D`aY5{J0W0nkw|>L&RfB(djzP{RjM1N>;W#t{jQ^^TLTDqi(JBq4vf zd-}Wzb+XPczy5O7WS6y8S1E;C_Q}S^;iVq^$lROOm?z4bS5-@?f>^*_c{c|sAU}y_$JmYi{8TRBwQU&3Z{p!@Oo^^qQ^5icmG{yJBxnAKlVoA!9h}#x6 z`Rl&7=lu}tmK=xtanmo4A^^OPH$O!n@;3g;xv!SlgH9io>by5N_$?p?;B?X9A%9a- zI6qB{sqW_m^~od{3l=77dS&fiwSA;9wA<8(5KWgOPQDA3#cM=!aP=7e$n0IBV$8uv zRdQ!37)QT5bP7qh3@5A-one5WjZ;(#aMS~FZEZ>rkDhXjr^2)8td|qDqIUW@p$`=6 zf5&sKcxrNFHyZry^%!bnfyxss@cbCF9zVHr-=!;ikRHQG z+uH76pnQPK>2<67+QO;Vx9JaK7twtEQn@hUL{uLWJOjH*x`NPt`Fgg+j%Z^CmGd~_ z-Qwk{RB)=*@x7t;A*MIftg@lUZmyhnjoARb^}=snYRJ@W%-v`iBj{z*Q@qFD-JNdZ2t4GGxGT+ z%{q$*2A)KwB)!CYmPV0;i1H-Y*^}}?;lzIxo+QuWie#Q&_963)-!FLuS|54B@--Qj1yU$GlCty-_{RcVn6d|{`n}K)G7DIeN9_Ix0=tEc_XbCdqVv@9*B&qN5}{kd629UC04ml?StN!=H>+` zmSX4=ivYxsS(o=s_aM_IjaX@2XC*Q7)~1G|m3WJn$uZZ@(W=}Y?CVMS>T;*c^UPgK zY=ES@N0+}H#@sN;0_De)?MjF4J;699U=M?z3wT95(|G?ZBi(N^C71es(3n)1zAmoW z{mJL!OWrU&zB^g3Ua+)abB%wjhk$Z(67+AjTxkDQF3i5~DEX~~(pe#e2J1?-4gR}r zN6=|;#3Gs8w1NF5jH_K)6jx9Y`@w5pN;~%_>iibWK&nf`#b1y3KyY{2axC$}ut#?m9Z}c$!X_bHb*^ z@IJ;XCx3-pTbOf~mko!CI+~z3h;X=MEUdnM}gPO)xP`+chmoz zUm)BNsFZcdv@9^Y0T{>EEdmhCf9Rp}Wdf!K z6Xlr*@Rle^j5zIH5M|2^yha!K>TE#13xE!dQ#A3z1Xqky2hP^~sPNHD7f9EU@ateV zT;2lBZDO6Xh^lVD;wtLP?iS+MFj?Vbw!YT@trciykW8i~wQ7G)`HJopIyI=LtJ|}; zlTRTBBQzVzrI`4*zxYoAs}b#hRePqcMF_WVW7lQJiR^42Cn*wa-mNw^^fZ3@n*Ma< zQK)^f+zE1GG_mb5&Lxt}?T)%b5+f>-hf#MF>Apfb6xqrlQNZimmLBY{Z9e1Bw)$Ma zC*qe*f6wVWvieqF4nY_zyXO~*Ma6<|D}xABD=uAP(O}#!=o7$Ez!oPp9QYrF^^{YM zM`G}wxRUoQ_G`Z)tDb)P#YJJHH?oqSKT4O|4&$Gwy%aN?t|WJ&OR`x@uhRQsA5uQ> zJ4h(L)?B6e@d`EVrh;D%k+~b*P}vukIYK6$IubzNA?c!z=CztW2}CT+&e$=WfTJ(W+Tk~$9)vlZWc#W7ayN?Jy-gX1cn_t)ENb)yq3vR&=87Ut zcD9QB8)7)#P%_CV4A8hi8LgypYUCOEbhULEBQ?nr3ynAR7@qZ=pCETK$Tu{Ia+_W*yO6|wcsz(3P;BiDbPBVRl)k!Q)H6!DG7fvogsaskynOWh`Zm40kaG>1c#Up` zx&J7vaPUrW46gzq6yK%i9nYze`1ZKc^v|Ek7tvWGnHy-$RVRP9S5I<{WBT{(#>HYP zkh`xNB4?IpZD_h?cHCUt+}IN)dRZt04DYTypa}DLsPU1ZPmJT=`DGOOk$Y41;$<4q z+{QiFa4I!k7qMmc!}5MQxM6+D#%gUmSAU`q+%1?<2FiyylT^HAPw!rSJFXv?@JFEw zP2?O0Xs{;LfZWJrFWf?Eew{CHi}6EL5>HRf#q0x+EO`dRQwN@#$AC%q(LvEC46M4& z&dsRFx1!Dk=6kQzo(z>p`L!s1_*Sxsctfse?eJ@&HGlIMN4BHZg?Md>) z3uB}b+P@Pj*&|S!<-;pG;e!_-K*Qw+NGYPkuv1XoAHO{Xy;pJj8Q-^0L*TL4pIQ2u zr~OUcXM@8X10O%A{ACH*K&6VId!@rT4`}nC=J?LXG^)TMv!ArO#kDc*mK`h80cwAa3OB&E*n&u{_E!lIuld z`W^Mw#SaUPGvV=h9F)=_@8*# z$ovV-m)Avv@fmJxG<#}yjcb>oM*}!Vp**6~?>;bz{RUH7$a_bBnQYO<$`#i$Sq>H^ z3Pb+3_ zJ1!zoAr_^zm)j}vGRG^|n_V|6=0ctJ@Vj|+UF(SOeX(nmZIyoCKRyjb%3M>dYh-lv z3k|4P=h_bcf1+*(q|_z>0AfcgK6L!HWV=-$(tuYx4vCGU&$>suD5e(y8ng=5>pGR8 zXTzJwWlcL9(!x>vLWF6g9~hrBpM|OUdc0U6KcUD`g9ev?TZeg zG@GZTZR9Eg)TSG()Od=kPon~+mQPRYs+w%S`R~d3C%>t2|3lQwRteKNBZ}`rD%wfJ z%huf%k5ajFqN93ZS zpFqyK(F$7=t$-WBOO&KFbM>!a0`0qd&jrMW3LvR&Ij5+`}a$R=QbIe|iT*Yeqh7Z%jE1_B?zqSr)*w_Qq_1 zQ5&PJ1nQo#rEShU)D1i!Gchpk6x@qZVq9Y;;XM;$efo>pc&<6dMwRLv1k$8JX1gS} zQ4Ie2SLb9;)suNz(-+S}G#9bi2YTMa**k|{93R7{J_suxs83~>Xe()fug?>_M*Gkj zv2DEbt`{1o@@n6{^vo}&o_k+a1hBKAISr3Lm}!uw$V2__L85(+3bqwsEa}b5dZ{MU zwSlJURO;5=@+m&_VEKLb?RLS2_sOGiZFisj$SB`>rNuuEaC@010A!+H@bV~vtV9N& zFv=%GB!e00J+{6j{;7LeYAraKSghc9mf3`7NsYY0-)yGxDtdaDlViHR*4D`lsqycH z%lj$n$rdb9-`IV`CHG!*KJ*WbJ2Bx5Ywa#EP0sSw^XvL`rXhCu+)2+uy}|+%i{SW{ za%ceGaa=e#U^A!Z5@;rOv}%cW($Y!V)JBK*Vnsa#Y0h)@NRpx6r6heq=Hq7`WhaBQ zza5ocW@y#}B{e`SnkZH6siReJ1DZ-HPvveyG`io3^VDzoJO)ci9|4tt11+RYoaA5s zDdE?EgH=KEYZ0J5(gxPL@EzG6nb#n=)`&aFtG9Y3g~;X>j{s~U6_&#@5_9_gyy4{+ znDTtDOqxs4!rp17@UalEisVlo1XOU6@*P;ehpldluS$Os_Xn!)@2u+)SK5bLD47vW z>Sl*ki0=3e?Z%f+1t{c3gc0#A-8a?6edbm{o6^Iga~dqt#kKN9XOj2WZ#=PDSM_`l zh(DiZkm%C&!pD5BHqYX~D0}Z%UaaSRco`kam|+>=hgLqF7o5sDVt- z(&Nf@($QtvvC^aYF7ksZ|3Q}&{Julb=Q5M#U`~-I*tJ<%zTX)w=oY7I4Ogm*~1t$IxW z3~!ajQu21)N@|?Wo5W{Tck7`b?}El^*_@ikk!zlXCz0Aau5T-x8?=F2bE3^ey?I%? zNN1Cci<*A5xvI~Mrl;R+2yFOK<EnZtf?D!b9bt~IqF?%Z&_g^+|l ze+4k8*hnPO{Ox`0Ot;bKbmL_}755S<=70)U3Jbb8$1ZyFegv*3J{I z-s+UYx32Fd66z`M`%XtK*~}7m+J?48_;I6QpD@^;mtR+Vh6mI7y-3rcVWy+HtxZ$d z>XcBoN?tVjIu{)u4Mm+1ggjg6)+y}g6X1qLO}+4Fx?Nf|u8V(RiuS4z;RP{X&s;mt zJR7bV6yl*NalJyjwZY2jYbyox_zh4gLg}kw+_!(PIMzSvzHr}`C*^p~e93S%&8+T$ z;gKWNWeZw$B56Az0$KH(BYEhh(jR&?cb~O!Jvb#b!wQx@rSbkam3`IsmJfogoar;D zS6tv{y-UviLI=1Lt~D*q%~fv3IJOd%GruERGsQb#ffqB2*|oSf7?-*@?gCidS4@}#-J|~~US;*NPC}9c zxPodX_XWYt`dPGnbrc#N(kXQwXeOh zak2E%X>PQPR@5KH$36?8aIIF17?ah%r3Vvjqk>cNE~nP<{t1c`qdy~)_j0xlq|Kqa zC9akZcJr26HF`0cW`o8HYbBWDFZ9mK9q7fclSR|KSI4C(1&7OlCI;_dQntj7?yt!J zIK9nZj|--XvOs~DiLEUE(;<3ATx)rGONL=vb2TmyiQGCpwPXxtvoIo-M;6{&2;~ka z4;fAN{|%LP&J03BEl-n~OL|gejx_SFQI$$jCc?ih{zviJYC#?0dT4&0&|RQ8&@LU# z8<{1~GgT%M^5XD=EX&P`ux&YMPaX3GfMLKT$9?0y3g!uE1s0GSRPH{BMsFdUh%etY znlt3bDz5mU!{zB7&+FDtqIV2iJsK;o%)g+(wF2aCnretC39q&qFDslordl=E0XtFKj= z7bliD7&$iZDMA+dCu*`%%>_BkcKQuXfGwc2;w%>98f3<(RS}jHg9)-Z!if$z8{I2w z1CP%CM~3N**~X&fM6oF|VzmV41dK-H?zR+zP9ONUHlS~W>UNPq@U|qfp*NhC{KPTuD{OV{L=@DvLUZtiUf!% zzQws?jLB&6L^iq(RHo9Q|I?(Z*Arl?$1qyBv91P28HNnQGcsvJI&x$SRG34 z4T;(NI}JF7FF4-RHMrgqZsc=5GSve|H2p_$vE><{TG9(#7#&p0tn|dIW%)GpBqv*+ zdqKg$_cV+9LccA~{|w%Bc{?w+f9F4nf?CRKX+r#NN1_6~t<0!S9u+y%3^Ph%se6ya zJwN`-1?;*vyeh->g8rlUB0Sp$&?W;9p+-WR;oP2FbE9QV!!wpN?Ds7db$2WTe|57$+wrq90;c3xXdJ#=Kr$ zJ?aU0=QU`=I$coW_0{_puC;DRTZ+C}OFl-p0B8zp;Q(=iya$8KnGSD2nL>`Z@`n8C z7|{$h_~_4d2P*n7iVCiX>d$*jeCt^IkMGg|Nr!Disp-;gN`T>F$!PjnrnBiE`8;u< zt6^$oMlf|UtTa5=W}M3l?;YG2v2&|9944=8=c<@>eYY^L8y;-!P= z?zNnyMdT+53uv-~YO|mNCE$XdGrL zw#4{tWsjc{moME_LVs98WfQ55L1LnZUdR`diWWFEsWIE9bCao-_hQp z`~X~~|9pPT?8dQz=nPlxR|XUA7gFh%@`uA~^ud+3ljQp(`dIy`=#lroUSsr6AvE(# zZ9+^gg|N>*WSL@=R-s!-(NR%I#?!6pX5w_6p z+p=Se2&ZuuSE5;00oe_%q9Vna*XHJ|Z{g_5^T__wc$bdE1?E!A`yqSbCBhpFbec{c zKU9@Y5c8ryJXg~-y1UBn@pfN-!TNYPW=OJ_(K`eUtVZWft5{D?$abLRTQVPO$Yt~I z1^j?#UG_^wUyZvdQ#!pY-go{UA zr(#o?8njsO%@m*cfKJJI;wO{~kx6QQD`-{hs#_W(;>l6BLO^M2)a`H08bGBu%BTRnB}>bkgU!041g1J!Q6kd=0;*VNL>YQ>@}NW^C{ zcr)iT``*ji#Dn|xw;i}8lsr}!Rl8-_0xw`i8RtQXf6i@gj6&a;591xX)wgZrHv&_J z90z?u-zCiiaQadmYp-l%`~BGI7lAs-M%DqT%<1!%RvVKJ@iCaj{a9dV!OdHDu})N+ zCxJs#*`ZwcTREkD%?E5-L8(<9M>=PgcR!%LJSW?no7b+~q${G@vx~63LO^|Y)h&i3 zs>_1_z`pj1DuD484N{rHIvFHN7p{n}9P=NuU$$OGz~l*MSh1v%$riN|l3Z=9!36Kq zLR?n(9!Z>UxV0ZDuORv6Gd|A~9kS8SO+qpi6#n|PQqD9N_a~M3M=#;TqlK0RNYN1{@2vFF|j`h!sEUB z4qEA;AdL6C#%UzZtgDBh5g^uu;37QTJ`1VM@dk#Cu@aD`eZz9@C6=@tg#e*hmOhB^ z>6gnwWge1rGeH}}z=n2fqYo9%)#VI67S`41R%Xy%N%dn*{XT>gEppJ^c#7q7q>IQ% zcQ$yn07Sq4US@wRIEh+GG&QZCy;f?+0rBgSPhPMSnlH3t`HR+Hz~9SaAHbBKbgjH_ z(Iq@v8I-(#$=5b5mtu#}2UT=9-k6vburpne_1Lv4g2 zS`^$cTP;o)6!-k%KlBc|Z!Lar42?+Z6kb!HY)Q&5nw3$~d`=IZ>AO#pg*HygIw`y0 z5B;|NYD-@x&#^5_uwX>}vTN;hXC2{l9awfDX%dVSGKRu{E^AS4Tn^B$pq`z@7cLQi z(?QJdocVnASPrzuLewdlM=-$tkRMa4FO0d9rF7+|kR|KY8A3>00@+Sk4*GmX(UJHZ z>WZIDYLS5BPzEzC0Z#}~omplvWbpNcu3L;FF$QVpF&eklqOEC6`ZyE`7Me#k`6jDe z0%@0>P~k?@PlD6eZ5jPLfy=ks*#6Bd-KFN~^(beG6rPsr{DT*X7p6SQRPCLht8~$n zFG)yiW_9w=HBTu)$+R(%EH0}H37WVg^)cnEXhMT(Y$xtAtH-fhww$%(o3wCkSnN&Z zPh*G#P(urx?=n~FMWXjdT0+7(%;cZMTHtZzB_ey{x6RV#CMIzzzGfxm=gN>)uG;~eW>vn^Kcer@9&AHPqs z=B=Y93Rdc;{T(DCP|JqE#!$3ySBAMDEQrMHeL8@5LdBdga6o?S^q^>AeA{f#N4xOb z%Wg9x?GFrIl}0I4|t_W=$#|wn8J!4bs!z_Ua5dM5H!`sya*emu_ipj+C|Ieu+-v*7i~9vG{uGG%&eD&j%WQX z{#29k>tmPe>-nd|jzovx~$RT_6@x*OX}+OOIVy`^VakfFE# zQEZ>jry(|kEdTczZb52#V2t>blnecMCK{#%#^46`3jYWXsT16;Jtk z>0n3DE5NE+69!jlI`t_@s<_eA$Nab%RFUfUt#aA;tlfHKE%o8*VTUPAo5#r4jG1qf zMw7t(FniukJleH*&?6Wz3&aE+t&r1j4IOQde%bBjH}yqjSyL&blsg+U2H6d|kQk4; zT{Ol~D}@DIfX)f4;}x*Xx(#DYG+U`6?uCKBkfLFEZUxtXHxj=!_7BE8fpQm>Rl&K$ z9D9T@sEr?BCXx2FF%<1rmQ-96Pee0%U=HMYvNC~fl@Ae1Fb&85RXX#Y>e~vOl_a+URL?qgYab-8Rw; z!KKU#n~(>E!A?gqvprqw$ zQNV3_j}VPf5Mx+^^5MM7zPh4i6SYa2(~9`cd{f1V<57a% zEzlgIG3|z{VKr4XcYeP73^>;RX%W2& zCZSe7n|v#p)Vai7wgI&mLoApb1j(q1{-oFJ zh0yF6uS|?>eiGy@-9zjK5VdXGLG;RuTL?CQ;mAce=vn?X`u^lW8xv$z4bPLAjTvP! zSDq7DZK_G;GoAl0n8HMJr^>H&FWNOh`tz&Y6E#RR1bU` zyhjM_)-HE9O;@m(SGHuNwFsZjP7L0ebVa_sOa=s+Xtv!sTu>*17WM>sd&d7kow?QX zF_bI#Mh_@iOln=zQeS50MHYL?(~Y<*Rl^uq*86=+7{(5LZ}l{C9L5J> z+CJ?(vS@17zXQ=TC&dtzHV{6Pzs!zQ64+z2$f@@yeBM!OjPw~Kxt&T-h%*eQyvsA& z(I+u8_u5Ls-`h3NbRgfOm$HhWVbd*wMF5oKp0v_E9&e)AZi5if^m^q69rwhGI4;LB z5Q>}LkFfd{^hRrwkAdRkq$*2&RvLK9>n#srPdv3%XO8Dypkc_OrNNTzz{lW(hrk5( z`03NTD{JqJ9vt!9SxavumJ=UAp8>zeG~nvA98HtlcE4^p7Al7glOjxNBx2fPOD*+F zM;~eW-fv2o6Nm^@S3i+ko818I6;?uotS@T;0a?ByW)i(f&@d+CIMp;y{M9U4Sm-MG zYvulA{wal&chI$gtGC`1w0h)wqiaq-OtmPKL9|~HHu3ZaYO_+mYi)cvq+jmspLn=x ze_km#d@zBTJWKuE58_A3}Ne zur{nNzn75hh9}%8CjjcE9x(N`l9Z?`2)rkW9R?glDrcI^c`!h2N1DwZhkr!%2 z{v>N*Rrwc2{Ojp@F#Dv6nYHbL($9eC)>WfTsm(o zWZsK;9lT7YSLsAy%8p(EMo0J&i6m#ed2q|DZ?&sQ@hxMFJ=eDbi{XX;bSb54Mmr7VH`7fZMhz%eLLFK1N z0V}#1?XtX5gc=O-Aa3cwbO5N~FCoh5q~Ya#zzs3Z|{}@y^j}ETI$Z z^v3vvW_v7xA-A&kSbQ;EqT^!L*eQ%7=}W=Cty)Z*y6O=N*PqR&RIRST&*eD}KiN#bC|KmL&!aESwc*hPcIEtMZW-tU0+WLx%Gg(s*-6zf;6{)azHLqWROuy%{B z9%^er4tNs^mfQi&rFg!CTH#W}ff*V8@yEQw!GNOS+n`Jj?DCcU)KhB$1$UYtigd@; zM5x7usA_0R{&ae_8vr?5<{-0XPUMO`F1vjzDu<3 zBsF~SM2sVvKDb@!!Z_l*E9gtG2lull{iOSH1OJ49yssP0pl-ofY*x6xccc-?j{qaf zjVWB=8+SkRG%*}IaK^6(%$_}NBhv#%^X07enStqBM3p%c2kzGxd%2+ zx=?tE_V;mIX(L?50;LBy8aNSq$ijpM*<=w#ISj#5tbzo_cs@Sd2Qk^G3669(%dCA$ ze!_L@x5MVdH-onC44Ei5#N0gAZ1<7~+76*fY-8K8qxXb~k;h_tmy~`_9bg+9@B%f% z@PHBvx3SV;_j=fy;Kx=lb1@#UfS3ORChJFyBJYm!dr`#zdyqcuE6J4b{B4T@_R_J3 zrjvZHK2aU_IC~{bze}DW(tm)}xByqN_FVBpeEOHh$C^)(y`lOMIYU~*0i}b&>Xa~v zq~lQ|i&7UKy^+nq+Yn=IUehN%S^Tu4A(wNPX^Ikf04uv&>4sy|B6Q#kYsGlYkrDP| zP@76-yirFRn|#~q*B>sUH+T=IsG57`}IaPLUk7%0U*34N}vKt1+c*ine#8`VuY``(g zrnuN>sRJ5aPmBY7G$v8_jUR88bE}CqBmaTOZg=|MP9y?qOvuOPbM*sZr1Hi<+V!4$ zzn!*}g3APq>#wyW^^A1A+&t&`+k3IGAEP3FaJ)zHki1tBG4Ys#7{DjdA_$IG7KQ3F z6cPf@j9i+=6~#S`hETHs7J*4UZ?nV^VtfVa$;L9P4eMbx0iY;e4m`LWG)FX0R=O-v z^m74PoeX`bBza(X=dnQ0TT)?P*0CS3yX&ApC;OC=rbK7h!*@g*d)CFn1g9Vvon9fx zmJI_kJ0_2UN0Tj1#OEZ#*Iq`?8_07}Hq-lFk9}|3+F7eU>bUVnq(Yxm1K5~!9!o7Y ztn)ckdmds9AlD12xPy=n2pl-oF2r?3rX16ceXrW41%Q~w#NLq0)%X)TR`*|ig58I_ zngdUH?)V6!2i(|3uN$n$DD+CUlY~FeX+IEXh)_|`^HEuyDNUBqcl{zx8BZw(jyA9` zx9U6cYoerc)Lg}V1A^?pq`H8p;C*t`kDz9RFmK1NTau-7$X8(c?I7`UZ!cl)|85xYTkTIEC~Omw38LIQvSn z#-S1crTE?P7R?`ooW4%mo1E&1@(wJWiDQh_oJ*5R^6iv+iZ$ssu5$j<8*j`8Tp|Sg zNJs4w`k)mFP^|mq|89G4U|paZ zu{|DKRL}AqmvNFd<~z9Fd+$JzWA*#4n6xmc8o(8ZoQ}suvEDW9Da`L%zVC=9b>Fl4I_=Y6R?{CCh1LIBT={vGhI`{Ti<6wx zs^iN)7m{;*K$klv1DqpWDb?mJau>N)LdydIGNlTv^B@3hnEiqo^ z!@ca#H{Rda1IjfQ6q$*- zr7S|IG2%3-FAFY%$eK)u>@g{1Uu#Oge>d$nZ|H^D66$BxZX)q9)ZsF<4rnE&noqQ7 z+J9B`tgtqRFn7z&$Y(Y{&@av;7JfFGf1-fjO*_mBo$!qgKRh4^AiGl;Jd~dj&av0` zVSSiOzwUZvjlpRj>iSz*UugSNrA$sEJ9c z-p&D@TF2KKYJUPAw4&cx_O#r-R|0QkM5JaYs;=1mHR~{P%M6L_dVxFX{oSdZt39k> z+SK?dy!Q;^AfAzGlp{Bv9F7G$gX0m`frlWJ36RQ<>I#OJsdJlQ5$o>V7oNuHm>IAZSUonU3o9US@RjZW`O4N zHZ_*AuXGR)q%o6wEtiv>eorbhY!^Jp)vM34)(r5lS_F3$0I(3BS^1jU>T42J>sJ94 zW6SJ6WK@eP2F|=i7H%8A*H(9BrpwUA%3uawr(VUP@}me{Yp0^P({o$8AwrrfDA;L6 znvPauY$zvCajvZ^B5*j-=dKX%vvw+>FBM2u9x#9!X|e3N?3g8KyIp=Nd>TcR?KlnW zwzkne?5@1~x0zKka%lCcUw*54x5wK*((f{T`>4w9H-_1D-khBolgW{Wv)o%%ALV-1 z_iPfiW8+r(gX&AckSzp&bSd9$o~^30QVQv}AlT{Q-|iJd9QJQ`k!G^`>)z{f3A`5Y zRrtB~K|Z0EP>vy@xCss2vSbiGrnzX&YWXr|WK}Ka#xXGtn<7oe{i++L+Y>%=qfc6V zVr^ntYL0(!i#FdD-0~$wi{WcOw&LN$v9XQT!)!KV_Ehax#$ulBu(~J7i~BTLZt@j5 zdWE29sF_mbHys49ZK=L{`(`3wOrnj6L42e%v);Gc+gkD{K~)PVT#E&JerX1*2xn0r z4uK@ejQM?+Z{9HHs^+c1PXCXhvkq(OZ^Jl=eh6CO?A|vZCC7H`0}gsW%#(0 zeaGN!Q|tG?kdWs`<5IEky5JxJWj53n~9YUcA!w+L=JdGsHNN&d=LZ{_)KeJbaD z)a@bs1}$Cf81?JJr6AlxXfnMNZ^kO}O7nUoL@1-VZnleicLE>vTWASRWBK^XH;S?) zjKWQMd1r6@yGtO@XKm&N*(F>$#CVT-sf-nGMTE6-2*;w@S4N!H>duscc+x3bx=cwo zx@0jgQ-_0%kt&J7*o$-DCj1@fYxIK&I?!TL1;M1sy(de*FN`i&5&Jci34ngR_q_g8 z4uLHGQ&bDIA9+yIE~zcfbpb@>wdcSBAFNarVt%tUO`ipbDRT$NF4*yQgwT#4O-`Z#c;v<5w^k%Ge$>smJKj;w!x!SO;Kc@|08)uZOYL(d$}Ae)zVa_ zeI_65UbdkAt|A7Op-Zpy^pu-os*UqjDsPStkz$r_NoBF%YsZ=*GDM=oN+lHhvZQ$Yc&XMUwc9OUh@A)4nIO`+H~HW zm%fuyg2p{&kHv9GT0o7RXf@4bK z!SepNSl%vpmL$liL#x@>*z8B^8f{*U47HNV?=p{swR;{R^v=}<gsd7M?L*Do>L%M66FdT~p}tlazgZ#HcINcSuZ&6aEP9!@3%Mi!wU z4NH{Pvj&UIHY-dd_7+L&m?vHJfr$Ni%)caQT?Q9G0kvE&m(PgivdKY}gb!KFtT)X1 zaDHvVTsKzi)JkeFY~UAk*5$NH+{(!PMU#hre@kL^vYYIpCsOtKqRw^|?&2*Y-lk!%v#=q{KX z=ZxVZJ+gFz74Nnww?*P=CRX|cfJ7~gsMI)7lS-;%$N`^=l^Vl&kmc1Qb%*}p8m z#YRf|_N4nN1nv7@O>NSexp&1Fq4S?kTYboAH$EXa{a=G-M)_KY-3_3chK-6}nphQS zw?1cPBzHl-%}prWd*6Ndh|J+->y)zGPpG(m+r#EL8D05@+0YHZ1M*`-UM9lv#KK9| zPm#&l*UxMcs{6v}-5s-)KDKq)AXHVu<=9?V-2}oJ;hXG|LbDhK%#kh(A@NiR+JlJt6R#`7(5xzta)@6_VfBF0F(5HF*gN_C*O zx-@HogiITyHse1GMNuv%wN}QXq;*{JoYDip{sI zZG97Wi=0z{Mp9M9%T&y>)M8ZGLhbMRsFjB=-&Mi1%b04v>|fF@Yc5J)21#avoUGE z$JT{8w?=r2O|kPanQv2XHB1*rDVeJ^w8eyzA!~HKtXQGc(2L=(Aq~>Lmm!OPNgrv1 zM#1nAuQIe)U$*%ljKv8ww}sQ66}8F_UviKD-kQyib`t&NjO4LwGule#J>XSJ;||(`41y zIC|%`mVa{el=*&hXT&v+p_3xmh~f`8Qe(c?@Rdv7OCDCeI@Bd)qcZoz8ncL>Pt8n^#q z6h9-Iq3g3Xdh=(u#$udF@>kB)GR?vtPQXIYOabKKckwy2p*``Bb7h^yh>OQNgVz?J zcS&n2tf1P=9ael1I-PZt#E43M`?C--FwE=m=J?%&6SaxVB@PWKh12^LR=6R(7XS6d za`T-kP!P1nO33#=lECuX5S|sZ#3W2PY%!T6ar5WZKzs0N z`rCu)u_UDf>^Q^ko1|54thEm-n_$ZKyC&`K&P|KTdL@9c=g`MXB@K`Hup6k`W9~FiHv;{zP3yKM_e?S3 z7pFAU<_Y;b zCgl0eI*X?zYSiI|Ol=?7=*;#*^RUlc6dywYP1iOP6K_Iq<`nuSjf6r+NYpArTVBpF7s-imPk$rprJG%_ zK<6#II2Qrblg8uXeKhVog0Xay|2cr$Fzd zKIM2pNE|~sIih|{a?!sGe_FljzNm?_o_6nG`U%0uU+GCyT2M-(ByVt9OL@A5INKhu zbgux**YJ=&C!sVT+u>hZLn@nKZ7TA8>Z<-B3xFEfvv}BeMeWRCc5|8#QlXVBI`T8k zM53{ybENyKbbb|Xw@)PXKYEMNU9EQr2ts9tfLNStjUvxVVpWwko-6`9{IB}`ODa!@ z+iFEGk8hKZ@nyum!g*>!#1M$NiJhh~af6f>mw>mT3@94QT)72NavbJIsqL9Rs^^mKs_P?{1q$#!^c^|3%@n zz6Ec}zZq`p%&+ zf6Z4-zD@JOTMCTo?ot|e3SAN|)auga6)apeCAC3z9^k}p-q%4_JW@~wkvpRmU;dP| z?kQ9|eCgQRVtzpVXn4FhO#eI#^HSlI8d@M2z1aV5Lz0}mXGs2X9>qG8{IRXHJ2@Wo z1k<=ul(K`9V?m77x7|s(u8pNWJyfYE&-HozulvdzdA`qHNqB|H|I{TEtT5~9BX%3I za4>($Ip#anXMlm7-oG{0IGksanfp(bBF~>~`z#*!3eOHBuwm`vQS^6mDPB&buAuWU z_)Og|<`o*oqDCJIk7#I@*JmLMarzNNx$6uUnOsrC_y7-o7q+wcQ^)h$_%K&2L$Huc z4`Rx~X*xWLy1JD=u~@xEL4oa(3FnGo?K2;bFdGkV6ro18CGw(pV}kjy^hT4xN;qJW zv5U*FKLXpf1H5l~fCw@j2(XeTc#{CGQP+KcCgid%OO_zU_Pnkmuvd#mMa4`5p?Wi% zPE%n>1$q+SUw)2gZ^`)`{#=lqWV>vr6W}tD!(^_FUtoql`G`>Wgi2h0?a)Ui+5mUY z4{vi3w>6_0qx;}SH~406P%w?P84=1cu9IvzcOV^)oAb`rXRz8qfXZ#en@SyM|D-JG z*Q6T%Nqmjb)7V|6v!~@ZXnOC<=e~bIH+S#OtKM!O-^e{wUc~uC2%tXCe>04l9#8aMlDbSr+-5S+R3YZ&$vP zD!82b_-oWn@8NrZa*nTS7IRLxtBE_r3`V&AbPVHdq=X%CU1#Yt;N5lS#oi^88i^^a zFF!kwU)J6@hHkJa8$yF(-raBZe(REBY*X~_gGJQ~xubv$+k|PjMpc5tvz!%Ns2Ohy zm@-t6IGHDo5sg6qN5U1l7RrG4vV)mL$##iP6QqzU&)A>dnpwEc(`F8RA0?Oq5e}UO zlLAvZohgt2L9g?=1$2|}6u(qu76y%n0rceuNAZWQFjR9Kjaqp;zrbtS9*N^Th3a7l zla}-~#GuxfG+mOpbBNnHBiTF4H;bz)rP=dd6ls*cK1`0o)#~w`GI^CHunXM!2w`jn z2SVE5RQ}bt9dP{xCZyfTh{%RjKZwvRT^j7MF%f;xG@=vYCwLXE(DGgNZy&)Kx5L&f+Rm7g)I^&`gS1CmQ-zbCgI_jaH{1vu>yeOu zco=%ezt0q(S&iQ|hz8aaF&%c*1S3pnnIAHlM+fctA;jTTZENG#{z*P1=9moAPsf-R zfP^gRxcLIg!({nh@@|EBK%dE0{;o_bZ53u)~ zu1?)LToDzV@Zog7YtdosyV-Zs{?1QXa#KV00nfE2?)koCs<0k4;!XUJRRe~YhD>G+ zmYj6yF!u6sqRTBArN>3imRnkAl{E%8e*e(Vs6nnFL@n4Fdtn1iq=hi!11g$B{DZ3x zFz3++(ksf&v{m@2pp;u1<$vtuSj)NlLYC{va{IJ2*+TD0swoBcxnV8)51^LQaD}2_YRQx1+X z2LypI%v=yJf|E#jE!O8%>K}xJ_lre==3-><;FU+kg8$oxy!GZRnmVtqe_*a3VF;yvQuHvQT}qs3+xtzw0n2kZ(wIW_`< z`v--`7$XIj~<{g~EHD%-Q|p+@(g%gR$E5M@?W8mxyuv$Jkh($h~iqXxc0u0(@^7QlHm3bHVznrjnz%M&0BFZKu z0NeiCw`ISn=|-`AG1Kz!@Qy1?*XP62_k$Xm!Bi>i@uc}XuP3TVmnA(HJfMt;{wVpI zX$dE3X0;%Y(ctpCh^ac)hfZuHl)T>O%ri?1?1rAtr|%_6O+^43Ey*{jL-tdwVI}A{ zGxvRu1NeUp-mbigbnKXrq_O?z`48&W`vAm)IqYCfzT-4VxDWPlAd91=idMP2nl)t- zCK=fef$Au=4odwMf^_5Ps|i{d_s<-&bM%Zd8y}pHMZFIsVCzixa&U|!J$iu!CD|`& z|n`bsp}XHK1<-ysJ%rjYnf=Kz#9Nq^q3{k$)Ea|7e;=Yb zVLy~_kHO#mtReTsiRsiA^^)c5G6}xhUu&Lxb{`k~lnAq4oEW3x8ezJVdos?8#2ay? zs%1GxMus(XOeR!mQov7s<+ztiW$C{GN+L)I*nkd{`TH5;3sCNN{4e)sY|H{P8=| z_iXn#y0NllW&bibHaOG*e*q6gomA0KQ9@Oz9}fOcNC`CfIgcV*FJh3$HK(kPgz3D- zY^78$IcJq*mZayuniWAgoV*KX`nVY-FGvO;_xBkb-d7PP0iPvQFi}~k_#ZDVK{o_h z7A#cVhZJM=kK0->?`%qORd9u=%zx{-b11f%XUv69PLO6(ma85?;@u1mx5o7vf?BN; z`pbmpCM^_g1h*j4WaF=#Kg$}Le{+L5WUOx5tlgYDVH0KY^L{`4S1HhddEVcp!Div{QS!BV38I zB%XLdCjntZ8_b2-tR-iez9l2_j35(DHbT}K@!@DP(6W&fK1s8%b`Qd(Ea?Jw2ioOK zeefQnFO)Oq(Qck=;s|;V_x@tOBG?aLeF6IojQ)p;W+Qz>#**fog(xX$)d5}DlX!F; z8&J}VfhakbrCG4mj$PE*3kctbiFGY-3Hf1ucGc zSy9wBbhgyBKx0egjGr0YFdt~uX$21%Pz+o)NBC&L-RKc%>i6!#GhZ^KB^I)LW(0E? zBl7FdV*w^Lc)*>8m&FM}=L3l;`w57ov8Kb+xMv4`4!G(Izbg&r?E@$#x;yJl;8Bt? zefb`d8(#p$E*WEt@`F%p1oIT^xq)?PC zNH%)CxnGRJzZo@9+7DR1c$~9*^P%LqD$TJlWoo-(i|lK?>%$*0LhJ<+OO+Zg)9wp$ zdW330K4P`ti?1JN4zonRnWa&p9Dl!)W4s0?2aa0qFez#SL%zTU^CE?p&uWlYoJBJEWs|W2rLw*`H06~=H3G5<6l&5dIhxD8P zh!WYjvf!1HQ&Uf)sdZyyf&4VP$mnDKgj$kMX+tu&2ZNpK`B7l1P#OaF>}IDsGk)B# z9i!Rz&4nN(7AxY=m0L37kb%0r9rGjkPfA4XQo@a$kGk%Z|Mb2rJ^e#Ea~3Z%)7!k< zAm`5+Mui^*loO4~14nGc$yJHy^||bQHl%*R=1|k+hNwCG`T44UsF>foZscVfPZ+;0Hjd0AJVW?>k({ubScQ4+QbE z*q@I(9%JAy!quR;46l9H{G%L)1vDMFDu3xs9P30{8#7D9xA5{1USHRDi4xvjS9i$< z%iw9T3Is7s{km&ne$=`?`A$aQ*mhjwNCfpKp>eL*x>XZf-S!VJKX@$!RQHb_#pN?_ zS9Xcwx6nh;nsYFjQpSH-@>7A=U$$A!u=xZ=rM`JxFYF|3|Ge4$<-^NP);#Fa zuQT~9gAKBrK?~co)`jh?i$1jGfzXw@KNwZrKYk0`ufit;rt+`be$KMpmtw(u1^Qz< zZ1OI+wA3PNM)zUm_%i(VGC^y~-8b+cpN~3Ct~K59qUF_vcSK$8a(X@} zEN@q4Abm_h^^r7gJ@`4$Vm!hgmZ5o>@VQ69x~MQF`I%ttN~ztcFSyX~^~mk579&A$4KoUHA9Af*Gb(|05v^X2D~; zRSTP{qDPkjDu>RM>EYv&BO5vLjA-BhP~Vk?0!IS;xyoQ_tkjSd&*WiAds`4UlR^0E z@R&EhQ7$@_olJt^k=u7FdA90gZ^(iJQZzd(2u<0bv*VC@s4dtwr>yGXF!!z1-uK=I z?TxGXG~zUz3v`d5fDdpF!<<;cF$c?LvmLDBoj=T}XO!={QE>^Cmi+8SIz9Ii6 z)UOHSWM(-~$z;Ct?WKp%oeC+B%}FOAKzb?>`b+ zCY@{}3|&@M;%ctU3}#$PIa%0R_UqFdwSqV0c;Mp1VfbATzyCJcFTxr~OT0P9(b+k* z+Lcx)%z|QrA>3tAx9&+6s6D-#w#Q0f_%d z`WHa=5d=0&aI+3q;*K~vbNw#(Cr(BN@heOKq2=EPx1AR<8j&0K0QgF}= z9^FOzc}_afT*FnK9{)nbU3U#vJPVt@mb)@Ogl}hF{=N)Fsuju39 z!<0r4?`f7;3~dN-_!R$KSt=@L^{zi`&vTQMPosP*{OiYqJfzLFDQx z*i_0vw1l4Xq3J(HE`#_F$5<{47!Iy_6KuAB*wKXr^{ryrMV&QelnzWu6;2@ z0MZy{7xkG?)8F@jMBYM7k6fty2}b+V1#q0W#e#RDhzY(`6s&=jtTgkB?(jq|!Kv_p zbJw3woEdfPR91HMjDN=nggxH4&U$s5hSqbfA^!k^IU2}kanne@%M!}|4Ien9BgXh* zzTWh<-Hd@G$x?^>P28%yiqI+Gkt!X8e9k8)a#zQ8iTXo&6q6E*cA7G!@)@1dtjsMe zR+Qlm2{*&NI-A5->KlXi(C}FJ?Nc!pN1WMtPYAW@96{IBy$m1L8_4>R(@+9K@f$ zR~oF^;JCjp;zF&__DhlLnM8TIh4(4f^y~W0?&C2qvZ@v7#6NF4+oA3m6)NG&f@tZYmw4V)~15f=& zGWqfjASzqx+3K`AQ;mv!PV$i?Y0-{bBaCWf?l(Z0yM8^4{+}OHqJH0pWwimZqlb;8mgnLUH~!MScU!3BP2!=MBMJic zU9{fp*#W(7Qyk*&+>!Pixb}UAgn7R}DzzaQTcQ10qwPC%PW3Zi0uyGsH;;6}X3{$Z zG_4t7-r6?1p%xpbaxm7Pw)~rnQR7Gg^vXlxXh{Diy-f;W@GTzd{UV#eU&{Q0SF*at zozbz6vTFCZY@-B*0&rm8lVR(}e0%u$=Oz7F!>u(~mhj(L`NRez*R;W%Ufoi#wY;ro z4;KecW3j?{;5|g?IqxxpHXR1t1kJ}%gbU0)NPa#2&{Yxr(iLG8%kDyRp6AcIM775A4DjWCER zW**Prdnej=J!YrxT9Eu5_vX%J7!HMe52QYXb1pD$qIOn5jFo8d?`I^m>U1w zpidK9GSkq>cXPVXRl94_FNms-gY?7DQ9HA*u;zn0iG=wt=8@4z_~7kV0ZzzAX9t4M z6a7g{S(ZNSlki6RanR0Wf$B0dvYcus&klI6>@we2@40%<=i3VBpN`LjQR1o|;%hPP z17m{82Tp=m@6?!{+XL}Uq0zs_9&C{h#T3h838FKwrzc{e{OVG2&%b*IB@hFu;Ll^^ z2053YlP4?wVtprvhfmvD$7Ke0wGbugn55Ow^JI6lilVmcNjO5i8$3Mk5xo!Le3_|m zz1F9~r$_JI)>;)8#Q!3f{uY*dp;MPvE+Vpr&72q$-?mwn~! z-+oZ&(~Subd_~^_+wxFj`7?B3AkUZuV@z9AA=~{WzqScAvMkp;Lo3|cR?E3#& zMuAl{10(K--Gn9zZ-kXShIN1AjWC)dK9Mx%g>%FQysi-Mv8BX0Z zAjiIK?}Bmb_Cn1?p<&wb_NE#7kj*U9+Jowd;@6NeF?|G_c$pw-AlGc{6-~kRSNp(3 zfqb3+$6GS~d?tg zGT`+;#LKPQW3?HptDE6}%Sjovz8{TQOuEWg3aPc#*Tdt?bqyTCkD>8i9=kgy59a_E zCe|bjVTLRI6)>ck6yhdN$xtY)TWZb_TO@xuw@g~;J>T5i=Hx1td3{4JG5>e#^VV;k4#Q0Vy*Q_`jbQQX3iQt@6S8^O8?->l@jPp3m8xk{cI@6_NPsHQM zy^bGSB)e?2N+-YWf@h!{=cdgZf2;csvzGJakT|U54pwcjRo)vjm=*87EhgGY*Rm1Pc z-F{kCVe&<^pu``lE9I0W++4H!(A*=>d;H@|ucTtBc^Q_FkK1RuI&bIfwU1wSB00AIW}^;xSq z_Ne0%eO-Pd)346L1)DCmMelrNW}E_x6LDofom2mvXJq+cGH9RqW_x}=`Dnv)Hs5408<5JpEtSIuQYQBmsi5@a8boJKaQy4oJQb;gB)?1tVl4>_APRg_zrE-kGtjz9SGQz~^7P*}be>AtPk9VwpJ^u$CF=STN^)N_mznXEx z$DO4Wz@<1muvULk_9M`zYewbT{4&0hk@ti$1JZaK5O^hJJ` zyF-=P{-Gnz!3Waf8p8^7)zdNtgR3Tl#fI#9=Bf&p-izozP3v6mNscVZVaO#hx_A*I zYNcGLen#<^o^d8(c4Oy#X^zvM^${O2&SwI-5@z#O-0-HR zEFAIgo8~ze#t;??a3}i9KwID&Fed4#iwl3ttZU(9V+=6X3WC{!k>xKEJmLX9?HVMOz9`&`nLt>$tC)KJLw^$pT7!%M=G7t2Qdy#uX6_OYjG*>?d&J}0m zBd;B_o4eqSA{XMOs<}znh`!${x+MN}PG1I~cXvD{%*(F-#WoLvfW*ncG1$XgcboPm zpI&xO)+eFqH-G+RGe97O7G^0#w?mK0ei^H`$xcIh+#DJyM0>j4g{J@YW^ei_pq`}u zMMIC_owY;ew2ZR^?lGIC*=~wJwD`!~0LsH5g43KNWL(-6T72P7?osyVIQhM$c67ht z!t#of+_Rm#sFUZdPsP&a-5kjnS5arhk465RvoO(Cp5*q5d(O)kT|J8$m3scmY-Qok z2W;!6N3eLZS0I~5+vGW{a#8mA#-O>rXpqWrvgGQ!02NGc<>E2|D(t;8H^wq6 z1@&g)!U5r|oL9`^QXO+UUSzIXZw{}t*fvAtiQc5vVe(R|&a&3q`qoBHd?fqI$6$^> z&8!)6YQjnld+@BkuRgp9VY*ts8xW;>^)&af&_+k)RYQikX`>2 zF}ybx1nJR{gXU_jr`5y3z0luoe6%F%At;FpDbuoWjw- zq?%eycjkA!I#u%gyn>_AQt)nJ5RoKQw6VjE%GH7)FNfoInnu6|DU%pM-YWmO)jW*w z2wNT5SOEkR#cO2@y=e;Bb|mlh|CYivB6NqUY5Mq6O41wS%3x7U4i7KZJ-S1+Y=;HJ zS3l{dc3B;LC`y-;71{2||6qD>k|KfRnRavNA=|ro!_Oh9WvqUH+X)C78L`ow^^I|7 z4R!$Oj=Zu>R>{5^on8)2Ujz6RtWm)bw7EVlzJ$pAgw|+R1oW5qR?@7YPKtCQSs(I( z7!Fb-1OTgitAAY_$vqr&%@{Z^3}yN`SqZBmNEA6$hn1OGS-4)QcjOsuoQR-J1ss<7 z-?LL~Y`c#F3JicMm&n=6xC7@11rASpp*K@>*Alz#jC*swt{>D#Gz932G#m@B(MT@H z-{?U2FZ?e2jD`jiuca0Fg&fDn!Vvm66>N2nKI6)wzp76%=V+?1_q-L#*w0@`gD7UH=(R;)WuGLai zc(QmAqp;P^lz={LFI1aeAZ~^-`X2#_Jk)2N0Z67|<#}K9i@AoeAU)#rl#Gyr;GZND zxw7Gn8=Q$l5n0;=o%J!Ye%8#)5B~1mM3-|hkKK%Bd73}wBzHU`CW4HQlM6yud7DcT zX#xfE+4O23=KZ7&(dl2MnhaKljWB+!jjeWbwaqfPalQS)c@+>K-J-m1ujGpq1xY{5 zvlF!L!EE>4?yynvD#c#RXBrD{`x!ty#`idT*JwbTEBvAbMgKA`Q!&c9Dw|d+a$#nB z9TLdu$UySSv9KSAdVV`!r}CndDR`1e*!qvKrdH59{1wW-=W41CIZiW3F_8$4YYB4) zFHxzlh#l~vfBaG4>w8Ab;4%tZ1g}Coc<12*V##Y%!JGxqE&==}Kh}s2UgYU9aLTqw z;xw0IyKf{d=*2QfLb9=Lj9t3Y4mPgEA7C9&@P5D+OR<_yM$l*^4qy@+reWz@>FyZ7S_E8kSXOBhBCGV$TuX4Ou@3!vL8O%>-@+_9e)k~{! zUUVP|CS3HrxHV?j$oNY=izHym%4-~is5AMH3CoWgJh}aoisa%cSK^9L)#DY?-7Y>X ztk+4T#IdcZy~OD}GQ*q}Y?6lQA^`{gL2W<*Z0v=RM{GG>f$|oOYRgsZHu>V~=jA8}5<|9r4Dq zY@PRVMD8;#58VxX#yJHe#Q)# z(|Yr)=#p%V#0O4(CZFG59{=7$F!3fsKw7{rRkpuEN4dAewxlSlTz^CYsR4tzX1tDZan8#X1WG&5MZ#BKcElJ~n&bcy=f^e)&A zE7fzESBuWoP!U-?yZt^~8^#oakY4R4-ZTC!;om!C6g93_BYf`br=gVnZms>~-fE>3 zJ~aK@A)&*wa0kqC)L3!HtQW1`5FTV?xJ908Z;=Mc%`)y=fvUB(U}@trrnj&UHm16} zzf)-)iw|vEVBKGVUxKJD#!CGC`c9TbF9bWGhEXHSS}3?hFlE^|a_Q(czVzvG)^@ZT ztnonL@yH44sSp;8{F-T;MHl08r#a=9`Ld+MrkMt3{pl9mtN~`d)MvDM+x0oM4@y%} zHoM{QwLIiM5{MZ>vMb>)utLFy;aaB&Hf6!4`0rTA!2F;Fz8(FT03pw$aiz;Fu(BM? zcaFO~a*ySh`CHZUhUXCY-k=3@Os!-B%d3Flf6%ifbbfCuQKawsd+B4>XCjEE^pb;R zxD)6UBoey@oO1 zji?JI!-#z%iU&*MODplyeLT0}coh`Prh7h60Kpp9VCv4-nOK-{FnN%){;W;>o!{AT zbw-$@7=i*9h;K(KS&AW(KZh#e%?H|Ce?Q1;MIYU9;+RY3PDwH;Zlrbf5-!$Ck4w5y zL!-b9PysnWH-RKShM$ha2UvJ?BPW=C&nzcP*{pJIj5)Fq$Uij^OaolP57mwTQF$vc zqbq(@loLK;QzE`dnO=dVzz$nM@NV8%gjg?})nXUSC=Hz2{rh^15lV|z0FVkR9ST4Z zS#OvWHD@UlYiO!AJstk@eOW;T{=9<;D50$QTbN6+nzN1amHrOhRwB_uZ4{rC zb+I;mJIMGDGkWm{y?tD|PsENWA0@S_Xjc!b2CkYv5@wDTT9`IAd~ze5=Oa!=R7BFk z%mIo5--TN70TGkRrcS^1RyjZd_}uE?my@U2^mo@(sw1j=magJQjP=|lg3Fj4juE!h zaQ79mxa~up-8rFeoB6NXqArOlW;h{BYe&Yz-G^e#f69x<)7et%WK9^g_{u_xhKtbb z>pYE}1%q5t!`Yeqx1yY+=QbMVkf;@NORUUh=Ui=-e{;Y1qS?izG)NTtU_7>P(uSY) z&SGU{&#RHVr{rbN-CUZ$@JB}omYq{q>@uUodSAHAu0XH?4 z++lN*XC2L6aPOFBOW=BU$a7QZ(SCx-0aRo)yP9T zdwU1=QO3dgD%iP7yC9L>vn{&Ek84tXHQQ>-A=E%XoT<&`MX@Y?VVbMb+OVT z_RC}Z@xj#U zLd2X2(TA{;W*XUkb)Q5EG3M$`PrIdkQU*?UM7Y)FX}|FjsWj{cw?9ctB>WO@KlJ7c zYQMd|_)0os&owm3Solw;2DG@jtrPz3;zu$_DE{Ju$8$MViw0vaE$OZAAB@n9H$cZp z&*sh%8=AR4FVwrQN63E4afM2As(deW;tKzdL?t%A^dAiL6RS9_SbWRT?YFP2Vr}-f8mP_RprLnzc(=|U%T40$!^>fSN^LRc-W|7O|8!gMMOv2WY7w}g3hFDj0R*>1~LYvYHkU6RpqMJ zt1J;IJCVBHc=SO29ikvwt9C9_XomyREg(pIi0Fhb7GH&|Y+w5coSjw2WKCVEU8jLv zIVp3a3V^Iy0|I#sGaJ-XFz)>zg-c~6nB)59^|yE+mNQbne47^SZ#xy_wK48XzXxG( z{+&u3gJ2A4-@cKoCfsdCZdH3f5frsp)8(a+tB_xp(!TSEtV3#l|UW z)|Z5w{e)iGxUU_ISx1y|pbf z>o_SFdln#*;CyM6f$+)7eG{^Ia|6NKM~1D6A6&hGy#}xakO+>@=JoShtY)k-W$BvZ z98m;P*A%Z3)zOxCiUIk4M>aaiK4M!g3S+&4H-0wj0`t)UNmQ+dGli2(qlV=PT0iL3 z@g9h|;&R6x9`(tk0aF;>v#{#bMP4kZgF3aX&cjQWGG&`tAVKLQ!Ce2~Q?+ zpa&2Qfu@*Ld~?YBcc`CtSlEy(0Xq=dL{OQM;g%fIpAj{6oihJAUwJz3TEY6w_WSqb zrsXWc!1d=~2@JS5tN}16a1O%R{-14mg_LbB2%R^ZkM<7XAH3Y%F&3g&Y#5E^01Q8} zJp!v1ZX2~JuA97~j$D44!0pH5BgO`>dy_D7aqd22?kMm;K0+Uv8yy||)+fMPI!2k| zM_-V~WmMVio>)Fp>rZOB_1mq9!GF_F=OVchNzBn#J$_z{%=ggyCw5>G|LPm~>5z5a z*s!ML2p71+ID#5EKCtIbLg30A3}bkJH$=$?8zQeB@z2PxHcZ;LBz&pbw%wKgU2&t; zVtztVZ|7kn9j7EBJN5Ra*_Oc=9z*K@irQ97O6{YW7$pgU7RV41DKDn6u&A72?5?)3 zHNW7c;$5W;w*3$x$;FQUk#rVrP5$rO2SHFNi;kg`N-5m~krn}wE|DB59S$ZTNSA=p zNJ~t*yBjuOG9<m2oqqfYg04xgS1qU82e3U4^r z@S@L3&Hj{Z;aQtdaH|fxP)|{uwKcAen~u4(sCnP)EEz zLE?fb;TSU&c3l{EsztF%^$gw5{KxOxWegK@+k6Wc7C=Nk$(=@2=o7S)ZAaa#qa!tk znj&C)Jb*29%fnnIwZNF~FlWOCClg{=1xHF+{<4ov0MJyDJf*Bdg$i0Qq0iXpb05-T zk}}`xfpSA=U>Ee4Z20YXs4br9!Vv!krNlkwFn?+)EID2OT!i(r7t8U~{R0*o7qUx6 zqK>_2hdW*UqhwRGPz3ntYd|o+O2;-g5ETIu$udNW>oKBXXA>!LC42g5#_8vs^nm1g zwTDv&TS@6nA*-F!T%zF1dvR-5x$)8qnJbUOUB|sbcu`qsOTJ3Y>96e1{9aPz{B19Q z`_~e6ZP%Ogku>n}UmD@)t7|^pVdJE>;*%BG4#WF# zo<$=ZFKFYRdvI_#v2vvoGqIDl3Od!Ek@uA^?IIHAuP81xa12o$ewcY2D)v9JCU8A= z&bIqz;Rx5(&i8L-$d!BfTV0gRnk2)ILV)gq> zFB2kcc{ox-(=RM86wHYXgG%@CCh-ae7)}ABxwrT?h(!p&A3LDeBpgm@$Uzq!xAmZD zgBg3jGyf~+aQKP4s~M3QCfv(2WOIA4d*EhAZ)2nDUc#$s1GjCC&3KM5WC5HUpV)d~ z3su2IaxvmF<9r3dRDZgpQBWthbIIJutb>xsyVdb29qJE{$0_T6Xz)l=G0TU#(T@XK zQ{AN^jtzK7Q-+e^nUj?G1J`sw{i{*v`!tZsT_&mTvi6;+H}j+#8k$WaC*>cQE(u1V zbshh3$+QqNaf#=9#yG&K8t%8O*M}ZzhLvawG^8S2b2VPIwd*Db)=2-p)B2Pije%=( z%vz3NwK`J>9x=tg`Y~2F%*ro>6Z1I$EObfFdK=A$%8_KVWrmf3-gQeS?u$@Ksx&Xh zb10M44QLFvdUF!x&nF+Tj1JWvMXBg@+(AogvIYw{@Cj0TtWOE>kcEdWwTDiwNVGO0 z`A~irNAx>cHc`HV`Y9H_>E!RNPK#grk+G*Rpd5z^A-u>!%a+W>fI$en6HgVHz%*M z9kVP(nlp`&lT9o$^+R?^5CNJNoKHW+Uy~ld53J7sV2Kzm&DL|RS5@$a!&N}!`|VEP zPHl7^H`~QY)G%~6G@Ut_pJipg5Po5-`K|Y~ zC1M(6e%Qc3WBH=(t6c6<7*c0ml5x(5Xff0>-AM)=LpO&xBEWS*N)Lz`il%#@CAJo> zhj~aZf&HfZ9f&jdz0aFNVBAUCxNYuam3r@dtE2+ZY?bKet9*%~elQwm6Po*)bu`5h zc6zOxxcI@#KKjX4&znT}g?Avx`l^Zq3I&uuN7r0CtMD^ZVl7^^*Sxc_6~~zIjT-IY zyJYsw!MH8|+VaNh6_cD|`>ZP|BvcRsy5UTS`A!VbXsm0p`I7Rj${mQCHnXXe=h9MY zEKw?euKKKB>~%Bsu3s!O4-w?}697r+Mokz~bJ5Bmq~iCeJ0;l7Ra3Y`iZH9g(Oc}8 zoR;df`Zu4jan+#!#*|AYkzexSPYG~5*OImky$iZI>aYWTllYn-^Wbh>5B@Mn)yeyi zb=qK|Bbs!J2Y8{w7VJ=`NsAYR7kK{MkdWfhfI_GWagf8c(!7UHJ<3X64SJAa?-+t| zJswz^p?bdr1BG%y6@cI21#w%I=(koW*a;g}dXV#bSMFR zvv+ss5mX;xF4ojQ;pYP9f@~KLX`G9O=!d%)?7F3gHZ&r7I$iJXGxeQRKO0O2#urv@ zNZtb;G7~G7I8A$~J17BKQAQm5+sE|?al)?EVYO~0uAkgEUq(*k8z{Xnit9g85 zsq9fojXE=LJ+mW@f%ph~kh`Y$Yw14sAxpOcjo6;{810 z9>QTD>YVsMfy;Xlq+2#Psx!hkeiJxEqu0SVcEHz{dTN)U&)V^c5mzPu!=Fh>yFP8n zKJyL=2zc5NJqi6N{Fx#wX`6Z-G&mgt0zoaniKM5*nh+D4?$)RQ4ZC-UU(Pt~>CImd zsRu+;-18UgzL7cI6d*Xbu54cokXY}j5DW3J7qvLOk89oa9YAa}>zDEMr2E42ryVyd zh^3qCcNtQe7B}jus&qcSxy|s02Rl48O&L1d%^|VM3}v48h2MrUb`k^Vwj(bMN|dQG z*KGv!wQ59!?a5V@8Pl0JN%uzK*Sp?WfD_QkKpqtrPl8D)!X1=^_<7XG$)i2jATKOQ zmG9ty+cp7WkLv#;Qwv{^Y;Q2qoPWirjJ?(foqTYp^z7q6RUZGmRL%Y&wHj|cY&v+z zV3T5A={B*bw~KZ5YNzSXCr_VE25Cez2r_UIE&8R{ z!kQ!ZvW8NAjQXOyAk9xL79ph=V^&^2O|-^{pqyLx-mp36!mc_^tQB-2b9+_tY4PjA-GAz}Q6Dfq|Kj2B`eH||xej8{iI6wNP zxi`56zIb}M_g8)`-rNyT+^=(FYw$QL(c&q+?d^iBEOgh-&)^6+W0w;#zl!Ps5DHA8 z7b5y{Gt@AsWG%l2`wz8c)7NS85{xtSd8~Ip)q>lO^-h8a^t8 zm!w>yCEyZD~4_JOLb@Rqm@~nPGa0 zvIf?MKl0tOCLw>*T>G% z0kttLzLb@;T&EZyg@Ivz6JIts?5%J7MucVKT~CwHgal#aiUz$$OU%L3^=l3 zX*{M;^e)<3$o!3o9^Xny#S3J^uEs-!4az<12nja7&FXk>m{S$v`I!=%X7RJmMONXC z;g9#v*)}DXgtdoIma{dEbB%P8+lf;_mO}EI-m-6AilBG)CE^0BPvbu9)bdC-cLIB+uiP*kcz=`Yve15xrXDUFkCx1h~o;(Z%+B3W1l z;bLsVd&FTnnGPOw&bu*Lz1lSr=lk+f%)~Wh=xmZqANSW;ibRoSBjoeI0$u+Ph;xXxoab+MQi8U3|Fvlo)Uz>K7zmo%1rHfHz_CK&N6GuUzX}V`sXpd0QdZZmPwj|CS799Z?6QUCW6W9kfW(e~f8H7hIpRhC(tePxX=&tZtw1TL2o0+i={O8`?uOCgc>y%VbI*85NP|jo+=8Zvq(kb$>+FEL8mA{UKM<^3A#cpB z%;k~=KabnjB$8RqiDZ(WPl@U7 zg1JeQgwBD5LDY4~+aOxx@=wF9j?|Mk1|y6sT9|5SlUiI&3FN`Nu%AvEeVaSV4Kc<} zyVOnwOSe`0O=1Sd63YX9cKn_Et;21ozynlh?qF8QBmjkSS=(K?V0bpm%3!K8D$cfvi#Tu*}uK0(`&K! zIIE($q6)}3dcANeA0n?8?Urf{T4B`$_g%L`yAqms40EeWI-*}cMALZ{KOLJ5i+?0R zcJM*3v4P1)Ap^NfzTnI@z8Q`-@*tP2t=zNbnR|^`C$PIdcw`Z@ozQXA_>pYGnD@ML zap$Hdeflj8!3M(QdnhWObF`uXTl~v812z3as%)J-7d2U|?&E6T5zm2FX7W6M8Wilw zdDND>NVlD2DyjXRDE|89;dNO;O*iRoWw~#)smoJy^Fh7=w)mSK?E)zV^%290-EyNd z0Gv=$X{AfJy}M=Zdw5{A@b~G(F!dhLD_5ga*--Az^e=4w*@ZjC{ys~czYMm=H_Lgv z05#T`V#?#vwt|?4dC-=S%dK}}@lI-()~@o_Vze<5+Z4k(f$x**7r$Fg1G}5_cctMp zpRT`nxx7BGM&KKz7kV&BYDFosdCyXJUy98>&rpj{2}#7f&-Z72mhl>_O{UX&xc_j# z|F8{$JsXf*QQUQ9iTI`ERqUFlmjnAyy4wJw*Cc#lBrdK~{V-szAf(NG!&2yn zd^6mItis^~%?fb;yGdiC@h+A(Ye#tch$B%&W-rUXCWA?ju*_wlXx&G&{oWbb(WDf) zFn_*0_}0J=2!^D`Ii5QoeEh)bg+x{RECeU4#Kq-GP02ST)CPHm+;|vx{8U+jJoB!3 zTtKSe=ZV@}(u*gI*>X98PK)S%JXmpLhrtt4| zDS;e2d<6n&HtV6=)moxa2|>^f3wKGsJyFo7dU4NMJI|iRlfywHYk}~IHgDsstid=_ z`C(&EhWO>}c#4&>)VEdmMf8dqWxRh?QltJoB<{!1ist96*@MV^pBPc?oSExp`b^HB zMW0+F^RP+!kIX0(2wv$mPR_pp75mLFj+Z5$cH3bqm%Q+-P{deCiNDK`{`T9C3^R)d zm=}*>y++Fn5hTz}K9eudS4kft&ayASMwBGUYT=0=`=PSX-j)pzqWb&YqLZ`287AsE zl3xj}>iCqrljH$_pQ>B_DpK6^EG;qpx#?Jj%*ZIV+Lw;rGT084*htxg`TB@;{HI+uOsV%Ox zNpMjOUid(JhTte+D~JFlq+I zg)f8Z%ry*Kp}lLA?J`(-!?G?kFw^@xxIKO1gX&9Pyw%`D9s@2Rt09w3BVg1XsSJw`e($4|lI;n??Zbpf2F%;2FeQ87Z>{~6z z=`+}MyRFu@xurJagS=U;h|Zc8#qUb8`$wyZf;_+%UDx28mt1pD*n0Q9r9ft7yFS=LJ?4lE!T4PhH(V=;A#GMCpkX0F_I@3$}J+ z@j<5Pg=1k^LxqI*(m-Lnvc(~U1sbj&sDOYd&Tue?cRS}tgW0NVaqxk5K`X%l?H5e5 zKkrbb)mNSxZ=lHWf<1DmPm*>@(eKZjBFDF>8~@ep&m2pKoy`R&S*K40j;|d>Us_bT zWEoAtAs84(pg+N#&0Tvz+>;V%HbI!s-ncD2aG7;%B?{55$E>dLkb&nqURb6w8Wl0j{P2(cLQ&`PWMc$^W+u15x*rl zH#N~FS-E%Z)-sXj0s?(=mDTv?k`XTz)Zv9Yzt+_Mx>?2V$BscQx+J-Ff+s1BsO?^Es#=mSsb&k~B}p0|jJ3){N$ZrP*$t*>L0=%p!UA`)-F1#t~sazw34K&yAh zVc^wvCVwSG8O+34L}uQKeVyjO1^dCfmF}4Z3J|i8>cCm#x-2-Df&XG*Wo3-^k^y}X zpga!F3%M{6EPAAq7uW1ZQm<&NO~<(oun9z*R#xj+;d0>#2k^I=9umXzd^5}89u9)< zW4DRj?Y~TZp-lktzaxCf2D3V#7j2SH4zOOp3Ie-DEs<3Y|>b`9odtDs2kc5d6)E!=bRVJJHapVWbm{fBesCB5RN-jK9ioT zKEk@wTLJxDe8?jO*)mo;L9f6~dvz9H2Z1Lcy;SYG{F2>%pL|hcmjx*iD2k-Nh;HkX zq+j(Ipv%R2`2=Z4bj5=Q06{80F!u=ds@ugs^}das9K4ksjOqMy{;L!nO~yO9Bz?)*1G9YKTt#;(_;G zU6uOE`lgf;?S`veOLx&ti5@-eZ8JbKtR?U5BZ_0afi_w?9L`IEQY(xAvg(YEk6t;QbAg!|lua@O9L_4_pA&j@IGcRJr#)KNB+|=*Y4ZXpeYOCcaK!)YdvC8d1wwcB*Rj5QN z{zo>=Xug=@n8s?gO__LeQbllNq?k%(<7{~0hpM3D(A>YT(%e4HCBEt&X!51KHgBa* z<-c@(Ov@w-O5D{Pl4kv5A~P7Iz{URYdbqCCiv30K2y3zj4_D(M*Hc``K}Ot%YMNPI zuN|%TW8|zoR9$X!N<8ehc`ok9>vH-=JU(la z4`FJ`5-EhUuzDz+!DtY}kqVYO5lvX3w~5R;%)QDde5>+fV1PM~ZVfkkJy&<_!w_?~ zgr14yyWv*cTluy8Ylj4L7z(>sTy7Svj6wuIiCGTRT6mC$Ee`_`qj*fUEm9d_mr9+U zI%&qU+mlQes(LAo+YPMP?@;wv@*HZs???vtd&v?7PxmzD4Rs@4h06yn88&{pQv~+C zT?DrU!Y35j`;vFh^J7jbBwD`NAL~eu|9vd^7k03Ov%qp@9%SOc8bD&hKep$Vz$0#jJYh^^S4V!bJ2uk z3d;8yT=PdDAbH8PI}GS)=nY<(U-ZkpDuMW5grzmZ=l!x}oW%7oR)YItU-@tGnL_7< z!s@(+#4Tcq=fB~)5ArX(c2*hxBeP9MO6oGKyS2d&nB6g+3?p6Kvx#MEVDh~cCeOy* zW+2Ncm(+E(-@U8w<5CB?;T#_Iwd=kgwlVZOX$IU#m5%jX^cm`=jP4;qd9c$l*0Qru zhxJH=f)=FW@+q!*Av;iap%U{!<>HS(=YM1wKmQ~90Uw)D$j=nI_1@>KQ}(i4Aca#j zKkq-XnkT|*IU7#0+p!bsZegP%zi;ft<}jg`H7Wc<9^Lzt5v@X*XPZFQBS3w^xXh$O zCnrq}@us-byMfBz+0<>xR|xl-7643bPj=L{3F+T^^wd@g{-)$Oeup#`eklr>}9U(wavbUSkc{P>LH!pIjX@Y;qOyG7tEzh)88!ttFjg55FhZB70-_EazQi`sVI z^Yl@{lws?1nYI)w6{{*!GI`)S+3qEs#j|vbP1`Z-n{7lbUiPsj-k>hIyL$~yHpxzH z+w3p*noi7AIMb4{!6D)q$45FccMZF33VTG5DEBJl{qW`lbS*1U@j1rig4uw9lEC}* zYwphpUimJS8T-Wf`X@`)Lv3yo?`+u`#Nn&zUuds|Hl_v94K5~WE*QD{IWLVPM1E4E zDXqjloa`K^%-A4KAD7HC-7NC0|6s_{YHb@pJ^n0T?~7x*S9wULQEgkjeUzqeQ)AQO zU{%Myy)a6qhC#cf6>(T|5~9tRcz9dn2(*G;LN1Hm2+{SuWg#}E zvH7y+YCj&kpgsF@?lpSz>{yD!DgX3ctC#<(%Zs-r{?y=;ky{~Hmcut?D=Z^GVYU=t zGWP!n<=;JG>4Da4j**N;0+RzL{cLFAQ4+lsftmVvrHJytfS1?{g?A@c#UL1wP!p@z zr&y6YCd-vxh8dN7dR8p&8GVgvdYVbjU9mO{5#jTjB<)NB&4dDxdCzfOg`Sl==Z%d_!sCa?UdCf(hqrZ|<{I4%Hd7)~Yn!ql z9EbkWrsLvVLD)2N3blm?AhbI>=d*^@1G1oh9ZC3t$>&pN;@H%H$B)Q_I}w&Cd6f;o zHAZf=IegctK0=}2jSzVqGR_QLkesZLW#udhv5ZpC$nx6Oa#_Nc6}tdXe%hFP+LDB#?1)TYJ9Nv*yK>mnoa|)IztCp}omo)_YhQ zJG|(CHF!?6p?m)dG|a^_cj_KWnPaJx>CVBwCGU{@Bq_!C-f*p3;*57+)RVC=oVufOpo{CrzTJyy zq+2OhS!M74=cxg1BxULXuuK=IDrTwOHh&{g^fY!9L#`%Yp?r;ebJJ+oQ zHSuS$4vl~P+CN(>s>_@4eaV5wBA<{c=^yM3Pvt4#x+;nTHAuG(7za%55*?9*PXIDU zcz=fFW|OWSVCkK7XVS_XP1FqdsID-$oi+8Ll)5Q&RzEO&m~>0G(&ks6h^Q#o&XdZO z8CMryl<*ugF`*1&qTyEp=UNPIdafqMiH0xDm;$FnKsh}UfIIClr1&HJ;N&YPoNE=VSraxy)t zIej|(1?-R^qdAQw1W#PYJJ#cw*98U(Mk{x0=o=DjFbAsxw#6Q!^PWm5=g?8-w|{HI zH$vd~|Lm;C@jismIRzbj>^4^P6YzPU(iLDhWbe5nocd#9h+%)x;6j#7v`|4~OVaBG z2ChYcRA=1br{Kl*9Me4!5A8vESB#Bz7%mDukWdhae&zd5_FkbJo z!sCmFdRRqfqdA4^6)JcbW;N<$0MV$^F4>6e#ypy>a%eKeroVfW$GF5l@S4afLEeqq zBWMvTas7mtt8Y*X7`_b4Fl42w3lzqc>iSR#KyTg4iVh0}EiDCx;;V!=()3>^9t0^S z|K;YsTOB9!pF#-#&C4 z;o&e!qEx{$&_Te=hopx~=6Wzp{;kq)wgta`e8qI3Bn9IV_@`eszw}(RCHquNy_Kw$ zd@Ds6^qorzSVVd+qJ~L#dWD$1{)k!F{K|$muz#>%xhp81!_bu`GbJmS^{;aMY`^_N zNeAyUWGy;(DU2D39-QX1azzH_>D_k5Ee9T-88p@&3!6Xo;K}K@CSO6lIJM4N|7(7d zZEOp6Pi_4`$x0^INwto&IJc3KePN84_i`z|cc>OYp90=KUvu*9O;ocOfn^U;R4oBJs?h35*N|L z6O+q!VTohhstvHaYA&-RE)BuuEzpZvvY+B>m-=oU{Eh$U_*w}MuQ+KjIOP9kvT1x= z#5%-CHJdb?b@`ci^8@~`DXRM&oCW$0nHY@^SQjGk&64;No-ebVgJ^fqK%PPaipx}U z%zRgj`}&=m%w!yECi`4jOzaM$*FTRAzt$7@x8Ntop6MNHm4DbWQ0xbQ{?dTgilS(5 z9!D2my<5x-f)@EEgqddGc=}+ufnG=HT8%7Ul$dK_o_|C;N$n~!g=0O@2OdoI#hK%sJCFzByoUrq6j=g4Ar7G;sV!K_F z{3*rXOw!GsK_zkGp!ahSMe9%?xPx&6+;mmF(s-cqVi8mmD$t^l?sF;kGG0zxD$U;uW6P4ThHuR}LLy8u?D-5^@7bTuJ?b^DgR{sm9MUIh+SS%Q9 zkhIX{4tNwH`5&{~ob}=)zTd#UxjputL0_CR*yNzSL=DKgcErgK^NVl;v%tl<-+1-mG2WFjwI7_R>L zWzR?EEtU8U)IP(0VaZ-}f0s}bE}x*iBVfVi@w2_=B(2gahrJ%M;S1mFCp>LHx_3Q- z^3O}U*>Gx@g3#WgBX+-^0jKIM63`a4|BsBQeiCQHHCS*rMmjMRc}x7RlBcz0X!sUq*?q(@DslFL=})^d z1vR*f1jc22K2Pe;y=E%HbY_U+UA^0#S!RW{VE@n_0qya+HSXz<9Ex{%CA|TY&u@@U zI)Q)e#+jZG@mTR{2>QheYa8-Xb)6{# zNMBCxzVD9_V5u0=fe{6EJihQFqhiXYHXGSBX;ZD0+l#Ut@-wQo3xv;-I>im$%`c2+ zZS>QP&k^%eSxpCDzA^neNFP?-*P;wIPWV{=SrsBVObFR&s)ccr$uT*7`g_eBJ=EdQuGd6QzI+dgpI=XU=c!8la>9x6i za%E>S)8W3}QY{G);!f@_Gg}QwhtF=BQ1J+wmz%*NA6v2!RzI!W(WBgHBFF_qNPwb4 zZ_YMo0${PTzF?2Pm8uYq#J`p+B*F_l$#@4l!`Al~F~3_*29O;KZ^WYz-m=RnDI+ph z&MiL^r!MKVot{MwWlSv1t8nhzK-{&g(mAf3Ugo5@gUq_r2d*uZp^Hk~IM6;G&(jB^ z=rG~W#8X?~RRiz6!C$X>DGKFIg=8EBQOdjx7^TsQA!lb(_RsOTko+-Xqn>5j_%NaD z0rw*SwE^P;H+f{(^nuv<9EFAnVc)(1guDJGA~=C82y}U`-m;jJHp&sJQJe=;*xI6o=<)kH`ej`GDE z*&tT;FV?27U6K($P=%FQ?8MZp{+M33xnr){Y=GidIlh_gVf?7hU%kcPk0w=@Y7*&I z(1k>xJjO9*&4wHbCJq*gVlOYv-9hKzeNQ5;GAFA{P2 z7z;}3W(KTeS9Y3Rc!78Yt&kx2Z&TA9T_2IETq)qn)Ts`vw@G@{)mqykrao3X*m^Lk`uFf(r|iFM zLLdOPyLNf2K5M!kU}Z_U*t}gh@@P~H21WI)=(=nPA~Mwfx?x#w(LbWt1uxzs-JB1= z`5(O^w&KV2bamDxG@JA8AcT2VF`%fRUd?yFt!H==>$NqBl03I6aLyz>!lgIm|5#P7 zgt2iOHNT-D2-_UwcJF+Ii{kVSbnpy>gqaQy3|EAyX^;RjqDQ^pfk!s>NC_|%T0^4g z&-!nk@c?-V!^kM|)ba608}nCrN)H1K*YgKMcnI1=K41-iZ+AO?Zg96TS;#k@2$pg? ztgmWZo>RDq_lM11=wDw=G+*t{r*>iU?+o~1y^{eiS^bj&ab+en4({nHHcS)rzbj4@ zGTsWiLZ%=(@AZ>daefPN)vg4RYhc;{Q*cyk1%wUFveXwBQn)o>A@I(91UrYS3F-R0?#S8Y)BePZ zCWw%DE;Z`g@YhL&rQ>B5zaZv*=fzEOZqeE+4l&olIUmU1PgNdWTk!cq?fC&$)(;$O ziAflz2Mb7BoTS=jTT4dzWpCrQt0DzuKd#7hpWR)=+Kh45}Kk= z&LYTLG{jsz2@(XPF8_2L0;aMGW&H`}_6 zZ?#DnlZg1Yc9&Ozaa}Q-tYe36_D*>%0NUx3RmVKdj?~1>Ue%fHR>sN6;N#~vM#kbn zeXTD1rHA4%bH(#q8{dzfdJJ=3cj>_`7CU76eq&`hGEWjiFV(;LF|n7D*Ri0MKA1gr zBtz+Kq`6+ea0_6b{-6QVS#uWDJD=5z&;4a!g{J~ZrD>ef>&=6(>mB&HP+v1H2dV?zAC(-*8Nkd0V{ZuP{UH zSGtp$;Hi%r%|kC4piWvnC23gfjxo(|UaPXyc_Dt5;v5bZ(u#I{_MYoL9MPd`%=aS${JVvo40~wkd(Zj(J0vrf-}ZUrlg@i4#-XeTg~yml z9;*+_!V*~V#UFAuIy~_aJZHRFWEuUWJIgGAc7rd|bb}m1cS5MY0Bg4FV>AV2e(?5b zpa|41plVm&bi5d%#Z$d`Iv38Y|GPXP?2qE7cjF=@WyB{dt8cm!1yOj-j;^{?D#(L` z>@%19iGkHtPAau+^CAx$T1aCEq{fB&B<9OF-$1;0ipwjR0y-L+MX1jG+SOIaLY7mc z1QYVazd_Ygahf_YP%`CvZ%JV4hY*noPB|dr*m1$L^y4Ul0A=ltVLygb)mo3Xut~2UK zHGjBj4x{he@W_4-VJWjrnQ}#zF6_gh>=612Uv%yqx@`$^HbwDrSKa!>tJ!Tv;Lx7L zfEX=Yn%|>|N%}2*(dvyq-4CwG>T|)*SySta_7I`aW%mFI^Wo~se=!uIXXHD|tW9Zp)qBQS zFNg@Y?nb3i+KP(-=U*qUU6FoQpnf+0vVhX(F-}aGwuGRGI8sW5y_0v!p0#0#8sA3k z@9FYhcdE=Mae}TXo6`Z06gW^nZ2GJIBlAG>)h*iWokwb$-(;S0^;;TJIf^A4s>kiJ z_*PpCFdHN>aEw z%T-dEf>3 z4CS7=4x+pIem3yf&x>v_;UkjvomRe&*6_qyR%n?Yjv!dDFkar6e4SIF`>BppXaENg z&?*@$DVXBm6+l%~3W?BrY!6@=#h09-WR8-|OZb)(8VE|S#~xZ(Wz1@R6RVN+IdrD* zpcX6q)~GA@_=~;b9IPc9U3=K*ZdCm2XI&yMSjc}S#TDFgKL5d3!y)g@LkC%=X8m=9 z_@4P0TWOIHgl_PQpv!N*(*|<)b@~4VwT4;vGJhql&oOzA zn1^toKLqmHwh3CPNWc8G9ku_&O5M!<;+_Rs<)KB+VEHepo$W(axXUNs3q>;z&jU}V zhIu<~%SwKtGG~Ca3t4Ddd5Xm0-M+CcR>Jr@H_ceL_nMa#nKcjQMLgc2-0ZE?h3l5G zA67dn?`XS$wAz|lGj{wmJ-_$ZCj+CKRAM1PWfO1-Eg$~GR2IvmrsA(!)Rxkl%By#hyxt6~(^OQ}G{NVl_ z2)9={E%Ndzamh%vw9rs2Eh=l`i+FpXFc6^BQZ6D|FkkidXG=%k3PJBQ;2OgT#iF_UrQP4^*2vwBWM?qjjy^+8%5{FYKE}} z&+Rv^k9(7ka0))Z{roPhH9pk0A2dNvF5fz7YSfp11{>=9`ag_OUHzTzruSlA)8^so z*TW9k;}H|T(r}E=&7Lm9;i&I;< z9NM6iTEZAyl90I%uT@aaW%jk_2$8LMuOLq-Y&Io5v7&veN7q8Z89&J zCN@_?sqt?}Vz|yru^lBToJb*N5FZdF`n~VYwrM*VtHt5Z6Wc@|8%YuZuTl-wM7bpZ zvzgWv^xr(C(gNgI-`<6PI~Kbp-ao-6_|g17+l5LEQh zU^TiEbtr-y`w}E{`PizZC(jU!=p)O#$5 z>{u>#V!^?VU2Mk!zlT48Q9vp1Gyn(}Y67?pFg8QF zCPQrbF$w^~|4!&Eb+kyrejSUSR@rAQrcodM`wmgS6a3;T8&J8r6S`|phhrN-Va-aw zxyrx>i7Ro@T32K}y^>qDb9|^--7%LGv|%_Kdrh!BB~9yt2UmKob6BNDyt zy6io)GPO=vRlDHIekVLpx}xgFu|Xkt_%BKW(OUVc9d8qDBQ=4c8Uh=CB|76!-NrB-CT84sptuIzJzEZH#)E7u0S8CKh3) z%9ua<9fYF#(K^DU0za)a-N(gq`^}(^38g;*#7bE3k_+`7JQn8Y8IyOLs0PCuyFZ_Y z(m6S1qMMS+b?>g4qOni2WpY{V1q33u$=EJWh`spOJxpGa69)E~iw5tJ%QslihVZaZ z3u@5$Q#^8AWLCQsU6AtA?qQvh7zwr7G@W=!Qyi!>pd^X3!6ZgIPruA3q8;)Kz5b9(lEwhdKhrhAEvlB96*^op8xU2{(UCw zx5_|zwzE+0lJ^(^hc}oih;sy-SE2kTA)hy#HXaWh>Th$32_CGXVFVcQ6RzKQo)4Eh z9d+7G*}+=h64BRpWIpr4J~{2DSIcd6L=mOvYj5fyrMn%0XidqlC%JE2L2dbGT>8*^ zxuZ+Tfd_9~S!8y70&JS+51XrH^xd4^{X+z1C?wp*karmSZ526`=DCBRZ~Xl{gk5uxm#Oo`sh_ zIPd@{f`Iq|iaL9`yTZAEy)bp2s8{o$^8WerL3-`hh0ovB{v-7HMSoWQfmM(|Sj3Cn8DJL_3j%`I=ts6B?(vSyP3*u z(R%pn31@u~0m4N~lDiV^9^QlV8*z3KKk3D@PP;#WZUS0rcS3$`!cZlCe8B%dGWtsc z42*pz^d3%h$oWm#CAT@@2hh7|WGe-4jzIv7C~70G{O6bv#nF?E>pY#pO(ig!;-Btru3I<87d5u!A${5mXyj zo&OQA*?_{k1b*V;xt;)jL_pU~;>C9tpW=t-ld~^9dEb8@XI+_~$Gz8tk8XJzde_s& zR|w>}8X7M62?zH|j8EFVnfIM!DMXwc*crCZxe1Sj^t;l=>$@Keb5_#5+8nR27Ta46 zai(xwp&4J!$aun+)8q7oUX#rDdfEhPR+ss3Y5M6)_|T2Dg{vG?+so0aKbw}kR5V{a zdg9r(g~ly+XZ6HCzr9e&^P}d-Yal=Uk1Y0-91x+m&Fbfb-4Wz#^E$47k2|9GH%LM7 zk?#1+Gr546xt%minmf)vmn|Z%kPfdjCC|;UFxEdPuA3;RxQ~-WTQ)Jo7WwVfUC@bt z?-@L{LuD=Qz)@D%F^?wP(I~_CrPhsJEPoqW?S&ASFdQ%Oi`&Ra{huxPndK>b?pw8F zC(pob3$$`-F;Q$}VPc$t@n0n_O{Ib8id7V}Y{=8NV2^-tP|I2qF9i<{GzjT9-J$O| zv;Os%$O56`CFL6lA2%qHs>!^-jXSA?ncr3=13%Hwr^gBLCdV&Xj=&vnpLHa;T*l!D zRVgdZ+a_lB^vtjqbaNHFm9ondA9MgZ)KP+xcpKih+rgoTk;&Ma>w+UQvj!MpKLB|IhaQU*qWM1%)ED;jiuRyq>b5BU7jsZ zN}^KhI|>-uw&hKJp>{))imHDHE0rI2)UPh7ZK0`OFsstUW5DK@5kyvOr7pWN4A^0r zs)4X(+dRon51PL^krfW9aLr#(uPs%|3O6Juibe?wt+yB|V%3B@0u470DJgbhy_U&= zl}Gy!SF$?L`OJ6O6m)+F$*WspZ@(n|B!8$qAAP>vn`LuAhrOwwwtl6j(~0NL#*9de z92^=8KzL_-XJW<5Wb}l%as`J&IWC{z)FbdHbz)e_$n<(bDCtpv;N6a=Ky92(FXgXo z_rqdgTn=^kIvu96wPl{ZE&+r`!xHj7gBMd+Y1p^>4C3Tu4p>&M#um_5U_X%V(~-A$ z>=&o|!ML3}Z9G~a4aN9x{zv~tV3IDP^&!#rYrGw&x8UhGA+8nayGrx9VT;cSN98St z+DxpP9j%~AEk`^U(`sOfKc`51M3MjY=SqhROQKW#utDz-OdCpDO}ExF;^iV1NL5dh z-tkt8R~yBa?v6WEXr}pHzY4QlkUZWMXG1qifQKnj9@g##Z zFQ0=wM85c3|Ds*+U(lN^Zc8tZnb4o zGU`_7M*kM;`AJo^T9)E#H4|E<9`kkq(@lkBrF1*Jtd*%vQ4elA#k?h==`mww(zB31 z*Fr*9FGL6glP~|r(s}q({r~Tuh{_5f^OTXY_vVnS6qW38k`#_ZvW|6*2+7JW>yW+Y zv1eA2y^nqDad6CoN0Ll+@b#m^y%2H|{ABsuU zMlM!2j-J$v`GfGW^hL2OXQ8X8D`$h1 zWIZ+fkek)oK%CPBcTBK~pF{5pj=cTQ1$oSU^f<0pm}NZpyX78mw_<%LE01=VdJ(2R zULvBYpWnM?BU^p`rK*URjk_x6Xy5v`MX#NY46FUGqzgtz7t3{PS&Hm%jsM8tDM#gW z5kog0)Gb|^Dw$N23Va(XXwVmZ?)4~I--m&J>7%e~=NT@*xz3v-+u9l+o?BRH^7@$W zyNY~^O^6`0yM&F_Ml@bqD7bcmiY2T1Q>Lv7#p!`31mJPUfHGs zO_t_YTH*s-Ob0rGLW>U-PD)nCI7ZhO%tPO|K#uLV)f12*F9!`-)#iQbiGgGcZ~P`F zf4ZIewYCW_T^A&aA4VvY2z=AwFq^}-|Aq^6v~M*O?a{`x!+Mck9`a-Bq6T9z zvz5#gFIt-OYkkrrJ%LQ0GDr)eDXyu`vzD(HHqFmD)_KPFf*o^NY9RViX}!g2+tk$8 z^NWd4{?qZ@=BlX3X_@du$Sd+U45RhPuXM}PDvsIxOF(|tkP43I?GpaOk(X0JUO40o z-YI`+lmaVx5 zB5MzOL~)Fh!jNik?f#>G|ODm3P{8HetlE)Ap7&| zY89*>;*;B*R6{`T;bF^okFIYP(hMk~iBnY@eqzLs={U4zflux7N$HZQa`b(M`Ptsb z+p}f@oZ#2YW7Z5u-{>o+ws1Y1U$bVVNMj2@-_TiJ`%Ey|2-z<^7JYAaqR^>R1b_AS zPZ&G$@&0d0{*|f@UTb-`xdYhMpenlb^U}KD zSxKQ49cXc@xKzu<6$)R@Oz5=3#{(+>)>amR>+--vB!a6M-xiviE-t2xvbW3caQE^I zmCE3F|I*oxw8ub~p;k+Xa+EFa0&`>FY{qmV94F&Sj^Jj~+InTPAm9JUa?CMD`B3YmKDIYjDeA;i8ohc;sAUZ zF*gZ1q_>OE=U^Au3brfA)a zj52v*F3tV`VAomb@|VA0Y)Qk_SDBe?vNw(p`-$V?u^NP$mZutbG!S_B-B@Jf*qELa z9Kc6Fs@FISpwk2ETjGs>P7FTF&3N<~EKZ-1*iD+aNZD>XcmbKI*3(?KL`^qdms*LE z8}JlX%|TtjdwfocNdS%IOAkP+iblhh3sQ9_T~w@XuTUGvoPIl6HnFimvK~!ge*SBc zrvMV28bFeEZnwd>u4)JhQY@B@hjhl_mrJBRy-S{Q>Ko8f*@*GE0O>`kvoN>EOd|A|z zLvvH!G-z;cB|pOeI)j8kuS@_r;t?Ua%n9(Y8J?O(Hgo!1711MW%J%%Ve*LxNZks?P zkgqSYA;!dscf7cT4ceNUfyHx*3Dk!_LAEHj_p6QPlV|T(v;&#b{C~BU;N{v5R(?0u zeK~ez8_I!l)J!Rvg<6KEz8L4(rui)0|M45uYUuq(m@c=b^>RQ9aSTxIcDxMmzdPyA zPZf);2MSn!WGTI5=U6L2NQ`AQHE*=d96}TE3;@A{i!cThLAm0?ez$Rm68Vh7H4|PoLZGevEK%Vx2k8Qg|%q<++>hViguqkOPm}i_CVn&3t{>2(@v|p3G{P5 zjj?7?+7t%j{hey9iFmV5CVQL6em_5-Qjw)=Et=2byC*I3VsoL<&ayfOAsN;G%dvxGcOtqU}dGR z!)+LaG)161>pEeA_pmL}nuK8SFRn7kTeT6twlND$OU2LWdjg(_R?Xzr%b)decZlHG z0xb*d^={l!gS=pX94`AM#3`UvO>`~Ibpd0b@J=n3bU2DDNzClI7Z&Ii==Q2R|If9h z4E2@xm^>fi&QP;#>4309kJ$^l*U7dU?9>>v|A&J*z)o(wlk!@N*(}IWZ<^NExyn;v zsWNk3W@2PuJ156aT_6_mCYyiBomhMh++u@%ZR;0pvK9Tk0bxWs(RwVeQ-i)<318fs zqS{<1aVNN>#Z1#p862``!^wr!%0 zmt9;e&o-_+@~R3ZgH@PMxs1W||B=B6?W;t!1ClSZJ6AIZ(1MTMC81eelJK_8E_&b|Xm@Uxr1GhAG7$U&dBdNdkhOH> z=-IJ^Q3W&dH0v zE8jK#@Qs^}BJND7$Ys^#*qO5{nNe_*`3$JZ1Q;&2w&fB~U2T}M_wThvvuUmpKI#6s zLw;U;se^PO8W1$F^R_Y{zR&JlTlV-UMV;uS-n*22T;6?Uv?SOy{|T#y>TDc$F?HGB z^{*g8FCL7QVn;mE-}8@u`A+>nQpQJ`Y=*WyT5mgGClP)k8?R3qd97qnvSDjX#>FF) zkTT5h&u}Kb9iesrv{2rXb)|q88;%@vKNpx#(I{|4z8ia^O-W6e7JHa>@y_%_>+<&Y zR!Mocyk?HnR;y?YOrS|Y&ddLDW1&sD##(Gd*0#{e=wHf%#E{>*)4i?-xO3_@!3KV#{v%q3by(+7C@}X$87izKr25lWwBeWQb|2^8V7Q2oIOt zXC&xYRpXVk1hNUg=y*1)Mm%?n8yk`abrP1aJYv_FmhhtwTWae7{37g0>$4p; z-1TU@TB!^jHil`N#8W@InxSmfODh+u&es3hUOhGmqc16lVB6-_T+#WQM^+xrbkApf z=GV?~d5oIaW-a&*NzMN{Aw1jP6Yu)PU-Y2bqJE-T|KQ^H;1*F4Puo%vx}f@a`T+(>xTE{A_EgvxtuIt1LtVnT_Mm-_y~lL%VJMaEWM z0zHz|T0I79NUl||#gQAy+FiEcBW8DlQSNa+Fw!3mXG|-P=d!q%P|sNSr+988t463h z+iB}pc-vYEvY=G4PTq1CvgI?m@Z9$eu@gUfS}OcZ$(M&%;2%1bM0{DYoxDv>D>U<3 z{%y7TEXbI3HmD@Q8U)8vDi#FBWD3QygM^O?^zNp39e#T9A!VJSa!RW;Hn%^Pldpj? z@%p=t|HyVs4w4S?#Txa)%|e*5 z=GY%I$ZD6vbDmb6lk#3vOdA8xn&o~9BMcQ1FrrXPfOLM^%BN%-6|7f$6?Zr|IyIFx z{#>qx;=Ju3Kd2e9f@Fn%SO(rzL}hSh(cGvWw2vlYyh3Yrk1~2YL+c*k8VrINnh`GG<{ZyI@9P~hD_+-%r9YE zi`DWSFl3h+PlFx)y0aD_u2ltg$R2-%m0EAy3!xGCD`{fm7I{_@cn%!8+xTKq{{lmD zSE~ZR`qDR>+8efn8!jiH=oZGhNFt5bU+X~GTb#xDYa-holHn9th|}{Mi{=uS)- z{I{Q|(y$^cYax5CAZnSlEGU8__`KZWwy}b3||e3KP=6r zYt$^4>CskcvQPZNJk#Y+yw#&OXqiH`coj@iLv}o0COBsK-y*!k18rxVS4kyWxTvyt zJX?E`MU#`H%^xwBlH=lfyU=xou5!Npg^nj#nsPVG(X&g2UyYW^zaATY1#^-(;L5*^ z9N0d>QIHCP8&61%qtHJd=od%vAJq+fZJYr+>43_!Bp%c%FwX6=K6)G__ZOqg3Ef#n zdMrGXe}3v9D0K6itYMtI;QON>cSsnL9qA|zLX0jli2;`n{Zc}8M~X?MUm?M8dGBi% z{QcTTomp{1qa9LwFSqjKFsxMl1jUV*?Okr`RF0V$I@O$%odt(|f-H2dfT9{nJFXnW z$EGywG0y@)$HK3`Yk32!(M(la$1zQ+Q1(ZD? z+U13;M~`76zeEKJ(J<*zp0QV7iV}9Z7g=P%9MIMW!1iKu~=!F<)Vs5C~5 zxm8s+bLA63J24}c1aI~9^nd$bl`Nc++c@~uSy+43J1F+{Sh*1QrZ(iG-(G@=cVd=D z8PROrzA2A-sd+%DcZng06n}M^yiR-v`FWZD{Y*k|%<`e=n<3J-E8!zPY)>A9bc^#K z)WeDs#cZWiv3=RBsEiaz*^Ov<(p3xgz))H9j9*F~law<5QgV~4S)6R0K}$1aIJi;w zBp>T;YFo_WdOR~ zEj+McVFNIOU1P5SwDD&kn613+`#v?xa;x#X;N=rtmIUUyGvo7az{H4=L}9ACcnRy0 z2dBr53W~fNmoBp|$Xoxfat&$FD3DQzy&=Bvn-dD-1KL^8?pd=lbYe%=_V>Eth9aAx zk;}!I=+@L1ZByc_^_3H{15X{2pk^$u27k|!E#8d3YaQqbc{-B(VjNJ@MFsWaPK66( zjQrdl6pDDA#ogy(2T{1k?6rLIwVG0T#>$-AJ-Q{Y^ao`!zM`AcG=BK;Ac?~10bJRq zT&CJ<)Gt61t?GWs>sg!9V+}S8_p}vJ%08wB!2^9MEHQN5gN4fxwguaUc{hti+Yy`p<+E;6o3Y1&^zcReQ>s{HUKmGWmX>EQ8iu(PlHcy3ZD z7slNH=JKm~6emM{q@5*UrRd{Uqcc}HK;}`gQ`NT$KhmumdplabX6q&UnH>dnJ58i? z`BNg!xLNqlV;<&d3{YO`nP(xhiTdH}slr@BKD`Rq0*lnCx=|1PA*o*V+JydsC$9~9 z-OgcbYbPtER!twO@Yh38h2({fm`|w*V-7bVKCexFC$>dbU^{}HE7`M)N_W+9H zTUUr-6ybp!m$((S*oou&lqb$fpDNVwR(K+s>a#`)iLd|0+E&^b3;Lb22Z(Z8tdupz zUaoj!TE|Wh;~DT=W67X5J@6wyknz0y;R(Xs&s*H)AY~?(x))jLB~?_LDu)l9rDn1G z{MB8w!?sn_{cC0#?)&FKnseVkLJ2ip%nKi|#WCp4!j_lB)+vHMbaFs;Jt)BKEj#qh z>a~9@1_lN~QL`BMW9Sft8Dw@*vp^lwT3Bi$VLYb6{w`E)*S$TH9>u`8Ikdo3}ATrfp~mj76`f z^Pvt)YqqeDr977lMH|bs2Fp}1vQ9-gr=hKJ@}Gp&yzVTH*Q-ZEFi%>Yn0TA*AH+f0C1qd=9n>2#PmxDMv7Ijd-gubYHVp(X%>>JK^s3@4((r zF&~W4>}a5fh0_IuDDXajqx15kUSThdlhSw5JdE~e)F@0XsLAjS{5`j!^(07tyre`1 zCcu{-ceA6eRiwS``_G+C;eW@Ms_xb?FT(UjXJETH6GybD!k3_N*R}W5E#4%dgN2CY zcL!L9DLzv?YgT?)u6u6pCmS!9n*#2E_|4@~@VvO4PZM6+e#Ggow!%OLwA@-Hd!UW$x%^A~vy_38l7ZZ<3!bF66R@(o7UVqp37wJt^GYwS zUz(Y9sywo1n5n7a2hI*ol(cbMDwnYQoB8d#bqII5F4vCJNWg z!82tx0iSyHzkowRGY5(+@48|<26CcC(&(pm9Y$=?+Knw!xV47o3j8TgSjS|X9=K>W z>;x|aD#5^7N@e9pwNhmrZ#!CVCFAtoeVHby=5vTi_gkl=v7OO=_;7pNIqnYPS*Qrh zWk&$ndP_66)c)@bZoCW!thw0tXx8bbvxP#^6Ka9!lU^r0xm)RCzX#^siy1S~K0Q&X zxax|*8OD~&VG0h?&Wnaxj+)bWnOIzMpA}PULvb<(BL8h|t+%V}WJJJyCF!o2Xf{>U ztQtCAnx9$o>piJv`xlucj>w35=gGm17fnfj9rb5z8){wZsnPD~*OlFhH+>`5;cw+> z{)KV|)W*}##W+n@jT7Yy&m*v^Lfcq#dfv-BJqo-V^~D)?>!4fjjmJw%U3p*C9&AgW z#{-DpSd4z)mg8EmiUObT!{Z{h zi_m;GA9wFlm=OOs?zeUC9d(OZ$s@Z;8SEMfwW6(bnyERKyiId`o|9+g18Q)}cC!bpHmSmr*-jD4iD-x_<5(vn?6q)@g>**F5 z{D8sj@D}0s;jD8UPfpQB-I+Ax1F7Geirb7L&|RDqD16hU{Sbt)c`4paa{{-$nn=(x z=esc@a;1B5>m0Kq#g)<18hDl8ItIma8n;FN-8;o_-nH1%S9sPl&YBFBI95=&FdgJ| zl{L|tV@Z&pm8(k>A>wJhBVnynh3px>o1T)Kypb z#IjtlznlNU#l^)F+RXPna1P)xub`9;6=FuxC?E}x>e?ndU{#C6>)0fBrqo4y^at?X zkY%8Sf7;x#xz}V|&-gHCm+$-?yJ>pPymIniOamcVbdlu_u_iVCC zAGuh!$9_HwLCiq>pGIh2(Kh zJ{%tv=Mbpzsi&X9R?d1*v&9Z*`(W^3dUIXcaXRIu`(f+D3_&x(ctoRvvJ2W>l6I&`W9$BB6%6V^dA}LzwO48p|CYeYp~_) z-vGvlpaub$s?(WT2#rodZL4$Jr$TX+mm&@dCUXArSHcK{`KSv?=VlO$mdxB zzO7$7n3v&V_HmC!K3^>jDiVwLQPaxH1GS&=Y_F0H427SdI#XifuHTi6Yb*6<$AeG9 z2(r*Ji>+FVBpl-6B-t!neKyZNjQwQ2?FHBt_IB{B`&3?zJp%)wU6lRC+#t)9hj5)L zz5h_AMrRO3*UAI;{tdaQ#M=}Uz_39X z`=aWx%}#&@VtsJ-RYe^C!KMx$6GD_QU>tp8kCK^NIOC{w%?%ASBfR`$jMfFHD2=rLN0@m~6 zrG>ZVntbL8u%UEQF?cDcqveoFQtjBc+UCveLcWjI{+F-j$C$E}bZSZSwY8TCb~tn~ zQg6byFy!as;)2zT2+|95<_5eO_@LM#;qN*>9kRg-p!Y7qiQ_T@n%a(>FN7P;Id%D0 zGLRORZ7;@Tn#u!7%8nwXlY1cYx%u8t--{OR2T^_hP8j@{^I@TlSH&JnXQ>^gZ*36p z)_#KR%>>8eO#=n0MzT}y4QeNwA!w98cmWy!5X8Ej=%_y$APct`VIUn62cJ%D! zUrZ^0G>NKXC;GVe7^t$U#Y>piFS$D2mkv26l##HL0Yo3%;&9tqO_{SriDryG{nlKw z3G3($Hku=Q3*zK#g*oM;v0tI*~}_SeHwlA)e@QR z@VrXIv5oL-8w~eq0gU+oshAf&Z>2b><}_OyEzf-6L8{X7RC@n@e^*M*P ztVxl#3JQYvt_dG6uEd0T28eX{6wS}eqPvT8`hm?_T4Uo{LTqoGD)flYvX0H0E#o=y zPl^X{MvT(6pAL=y-ng#i>YrpslA#LSLV*hHon)n(T8e)}y13gj7_7$V{b(;eGU=ml z-kB8wN^6NHeLJS)YDRW~w44-`EWxhAZzwX9d9HhSLDwno4(j$$tJRRpqC0aw-M0$k zO!GBKM|ad;6R>Vt`OOu8RoxD(O?-k29_p`&c5-;u1be1yyb|v)biK+!@ehsCq6X*v zH$TnY2UUd*le|M=^%6rNJil^`B_RK*0&Uc9u3UFF-g_5Elf^`4XS^W!=PdI^u4Czb zU1K=;j|CU%`$va~YA0U$KZuuR`c2wj-y~Gv1pkp=yf2>TFJZ*Jz@;nI30V80@>xW5 z#d!TPjb{THbuOmBkBAMKH~M=yhhR*_za)??#1A3g{ccTaCn<#2c_m?W82NUFGM2ExH@VWQCz{qJH*2PYBgB#Nt&+apQ{N5V88FQl!Vw25!*-BmPzV z_$y#ZKZ)4Ec*ON#11MgF4aOK%{|=iDBgcm->lCbVF^Zvzw+_3@;N{D>gqPD!ht;9nhc2pu1V~wqu9?&3pq0ekyWJ%cJ@E)*P4&43GiCE z=PMv`8!fDBm~Y+Q!rAk99Fv0->Llsxp;QOea&Vl|X}5P9rHUOW$VE+PVW*+K5^ow> z>Vc%$)JYfAZ3+fErOkO{2%`lNzL9|2Eq1Dg({rShXu50}F0R7oJ8Suj)?!CJw!yWA zzSUgi8g$tIS|g-KxrJsaw3rm@Ry4bDW9S?x(}{8oVtj;)YHdC&KIKyg}YVzcOj zYAoP(e&Xsc3il$cwBs&!=!E7;N0j^Q8&pLaPW}`{4ye0oOug6FgR@jH&T>I~-hRvS zKkw)^xi@^>F6rH%APeQxwfX>KUv$!t>2?iSyd#dm>RZ29fa_zUGJd&EGCH2xa!Ko5 z?U7MVJu2#RQ!AOg9i_B!sSqW@EpJdi=Kdd<+7$S7c6Wlm+6?|B0*YER8!DXLQR7ys zS|z|x>w-Ay{0B8?Rq0oz&Q4C4{8KNQaty-XDmB$8gJdW(=9m)SGFYrIA)cxqX9io3 zvabyu6dVfM5CQL3ri{jzG$tL6(*SM0-z$^!QSy#b#BW8ab)!-{!#WO3c-HHox_j^H zn1B|j0l_~vPcG5c92ctY>a9U9`tMZsdDFEgMAT9v=#^sPYK)#w|F1A}>qCam9qW!; zfV)L});)KSJu}VakINk1eEmTA>xZ}H3a@B={m<4#^U2M13O4Yi@Lw&p38@iLYA+wz zIo|NAWe)WA(Ng7O@ex7mCbo8e$X$>fH2l%;ogaIBsDC{S$k`kS{rjhTB3tKq8&b5W zjd%(Cht{)P3=xvu-d-fR^u*wqZ3C;@yREmz|M;IM?x$?H9?#pzGfkHzFtav#Pg7V` zUHzKIuB2@89gwn9Pby*3e1(Ufrj}ALwH!m0ezMbU`Zzec#e}Ze zc}Idpb+t9t$Gj~BzK`D%!_x$P^SZ@=>-%AE9qvc(QVo~iO{}|`<+{o)kRcZcZ7A-% zpV97Au-WPy^B@w($J-WH9OvGyj7ak+eRN`NVM=Xe{nXJG^x=qEGhjx~zx&=sCRLS) z3bS9qa@Kgw-HB8umIGo@*^z#8KGENcLZQ^hpAMN{wk3Y77w>o<)mcqmWnL>Ce;VEO zf*P7n$Tu40A4WUK05OhjBQvK~cYYY)W`LBsYnwn{OIbAwHLg$8xcRv0$yWY(DHGy-l=f{) z*6e{HB?-Ue(-pucZ_-o;>Ep|*Ta1dO7!N)XF z%jI1l)&Z3%lE|10jhlG-hwOe4=<0dpHt*cNG*0Zx^&XC;lghNL37)k}(Vaf_>B!0J?im-#HQxk;Sk#2?H zhdM6&jfjGTYPI-Z1Zj)5W@{I@^C_LlI9u0d1$6@>A-}3mH+5@8-^g8A3rXj*m}9FYDr>Ii^`+p)8+U}&?GU{ z&*}m+0Cc)osW@Ub1Pz#Bh@_S9#z{e(HCEKH7kppePRcTq;`Yq&Z|YB*N3~e@?#g-DG#a_3aD8Q=Qa0)2g~2pnhju<8T9X zdm(+4XZym#=2R>=yapB8IG-2qENj^!XAQHji?kwUU%Oss4sjIcvtlYtTcX%j zD3L{Sz7DNN|j>G+5vzd+zM+sjsgP}G5k+sJh>#7a8t)4G#u{7jDnYK<3kslmP zl}=9nBMas~2%4`sl}kZqIpn49L2%N&j6aEA{ijvN1@37yzi*8BcJV~s7ieu-Nj3)5 zVb?B`Pu)fOja$b726pf5$2K&n*%xl@?Mj;Zi~H6t(s{xJb(CX*J0Wmj#kDTBvD==P zgIu5m*^R}-8F$l2`^dtHaI#sH*ejJ z;|jZC+*nYQvU&;!a?d}QawuvtR?Z{0eS#jj9$qDtQ&v`i6B`_P=DeVzZX+#(Z{^d)fW zNLYcA<0@rJCWf(ld3qJ!Q=UU;g5b-(*-zoFuQ*)L?aDR4Ywk32ZINz{+&Ge@ndnMM zE2^x%JwaHxG@RMacof9#*R?w1uRKbdoMM;`)Ud<6u>;2--tF}PZ4nvxwR2zNADqvg zR^8SsyE)(gDTeFnvm6lQLCpT;eg{4nO3~yiXpeVk{_zG39&FXXI}2q9P1)HVs_Yst zylj#^3EO2@OGVAf+M1YgoUjHdTQrlg|n|7D8k+-<2mr1imMjrCK; za>o}spLmo5Vzt(p)a(c8-A3E)Po1_9Ch~Ny^_`Zo*MEC+XLzUL4H<-cmT&x%20F- zoG6HmdaNpM6e7dGt8Fr8HzT$it?5B|1Q{{hg)E6WY=KyfeoMn&y^rZ(eX**f1F_jh956cvEyKzHL}>I5)_Qf?;74ABvxAI`Hm(sMC| zOK-G|z_|*0fftbkwiQk$Fj__aqcS;O)9MX!Kb4VKh+HNo^v5)1HlBGB60rtg;g>df zDObU~)i#(O-9CX_@Syr519WcM2b)U6x5dPN*gA?{Nc$qo=YE^b%J^9lDOK~GxGL!M}A{<3g*t?s%F%o9@DiOmsc02h1}kn!6Kgh z?nBD1D^Z41XHmMX(!;O6_EhGO-Efx6`}Qec2$30x_!X!UXGjSrt@rlTk9(vxoz}e;cBU`G@&I>Km1D-F-^|r7LziL(YKg zR?bLTZ5LX;&1wR}#*@aA$BBx4wna0=pfQE5Q>%9kfO zqfY-A;)wc}B0CF0cqJPfs8RZdz4A! zBn*aPGld!_zC<`lO*aLIJNVEjX-k2Vxye`@dcr=YPr6??UnGavs{naQDr(lp4u#2M zBu3Byeme0_C*-ezYwJGwP908MI>GZhNkYh3Q59u$DRnqe^7OrCgM}olAR;*9KQb}J zvx1L$Rt$gtBMU`H0W%JkA!tFUt^PZRZpY4I!m96x7U*WaqQxh)Dqb}y!9%*N|REzimE{}(T+Dzn3{6F{VL)rqs^9K zX6Mx5Kr9i<00P>x@Tl%6E!@wI3A83O5022&m-cx{P2T)DQHt{Y#_G&jswFU?Lar0k zHcTdnf_RXWo*j2J?CzExxITL-30~n|&#~sYj{1gV~Y9S%Wf3`fzx9?QPUet9|6Z zsj;>y1AHzF)l;+31Z8!<4$Q3&8u25*&mY3w5nZ-cJ<^5Xl z4ktAEx&}3v3qE`Lf?$ky?*`vS@B`UP2)nH1J~JWv1)e9XcyZc%bCM&mdwh4e#N?2X z_a+$`^VLGaXjKKM3c)f-x@!)X*9(5qc5v02YUkoydhcLuRS8{xIPpYovXJp#Jox_G zcK*WkVr$2#{)7Hr4woz;P1(FutfI`Nr8mfF6dTuJF(H;?R5wJ=|2~rG1xsIFJF)yK zN$oxn4E$OCh(QT+(rBYLYPk($Tht>j9>t?>l&LH1P7@*o~YN>gx?P?-Tlx!TzagWE_Apcho_9Cid$pd!ci!l z+di46AElu9WFw@sGrdD(28`Yw+NkVc!U_zYTDQ#hyR9*Z5y{rQk)Ks8ohXp`*; z-BkJp?pD>;(K7dNTSC!%eWw`_b8vf=YW@Tk)w+Ua@fg}fRPt!-n2cXF2n|>=> znUkK2RP03Qd@Yu;SWgiN^T^z8g?TQsqQp>vDe@rWS;`tsFx;Wan&ry@KAVkn~doRts z*HEb80gl#AHJn?_ECcDq4bCpbbfKLSYlC|v)E9dj7hlGXgD%%=n_&W1RsOdof9$2~ z^lIO|{fYhkNRBP4%Y?>*nj7z!dZ~XJ#Lnm1j(hYP=@AiN7&CTUJ}4ehl7y@)-#zlU z^PbLYycxA9ug2CAfhvO@w_zh`#J{NtVZJk*_O{nl zS>{vEHmj;R_*AFdwU>W*_w|w%&-<)DLNWINMwPERE^me_F834JR^Nbob(U17BHvs5 z)qa90WG!Ylf?7qWi$ZeqW(m!YQ#I1(7oU9JJ=`&yBJr^&777c*p_|{yX zl6y+Lg0HSj)}o(3zJO|*y?o5~=DRZO6wjLqKR3BtVP59%z7%~W*^Lx`5z3n{p&49t zvA3U#rStv;ai*2y$q5oH=Uc$Dg&(#CGV%5Ps(D%h-K4A~*r#`N^8H-H5FLTaj$Kav zXhQku5XdRT!ol=LiTM*wazTN>c9!$l%NvW_G^f2VS0lEEqRom}VPW?ib-+;16oK~0 z&}>SGDO-?kDpgv%nX8t6!d&PW_HxYQoXIc1=1f<23C|MJy;Ja&xho1da?K3SoN$Q) zwN3d>tz4rpk0E-^x4#c3@vFdoR59`GE4d_>&Xl#92)`Cn_0g4bD?=mGpT79JHC6; ze@T;9aVS#||EgyEUCJnlcunrd_|=+AlaABYzQ3kJ`SNtl%_VCcosrlRPHv`&r14CU z{LjyUq^9DG5o`lY`chjj*#u=qFCw!#p86t4KdRT+o0@Yx|I9R62##*ML6F@=zs3tY zW$=&R^W*l`8picoZ0*wXNcYk*fK1$q=0e~ZwvM@--Y&Kk2b~p3exWYc2i-mg z4?;Nz~Mz+FFMWHXFJD8>} z<$mjFP5ySf9Bemr0ap{jzLVZBZa$cTy>@8jNu1g5%7x$Wef*Fd=#`TXRiX3DvVz9i z*kE=tp7qgkmam;x#3r$e)fcBsw(2T9infJWu3I|lJNk; z@3+8Cz-0Zxa5uG|eYI`M((<###E8b5BHwB<<;ldH6weFzey>G(UOG6WM9^cnX0(s; z%>7Zvj~;q+_})W`h|wCE+Tqm*<7*h8?wG5FB5H_76>Tq|NUek7d?h2Jyiru4MKF+);1{9)`^JEne8Wo1ZW%Vgj4KV)G zGKbW2w-mO<7AjS^mqj(Zd?RA+IIQ2@ceXj5JY9e0RMn1H?Fdkfa)rvVPFkF%mTkM+ zY}c|@RRPs5R?MHon2Soj9Cu)gthT3;mDCEcJF_z)t}dQhqblHEmXgv|>NA`yO+w$u zR%TxZJUCV5!8q;@QzqR2Hgd9sLwIt_Vt4lfsZH-%aYwmQ{|`{Y+N=l3?9U$@rb+a* zBZ(@|oS@W0)5d6Z19uYj)|grKr+e^sU(Yf%4YhPw!1ABtzLOZvevgZs#=c|*O4_C$ z+Dh~fuiXR!X;kxug^p7Ug-$8Cv6VtIKXJd)vr-zMQ~2xYhuX=G53)*klknfq`)>1r zCAet)riOW_NByO<9g{8wOY^OqVx2g+MyjomWp(u%iUU3@3w8D%@*y*u7*2~hr;DOa z_aXz5{oF%CV%3nwaVDKU__nzN2DTXXt71|X>X&Ek`SUmqMqxl@%#Yl2v+BtzuogYO z-AVc4@6pYDS?T-oryoQ9puZWMbGuny_$RZa#1kML$w=2wY$wj5EW4;6XsVxaV;>2h z)LIP74wU_3k>2<>j=c;q=jM2WF@526SfL6wP#JQ|5eP6j@$k1cL}-uVPAIq|B`nYD zOs|Ix?hCpvB==g_q-F_ZPg~i{&A`8nIWx(mE)Xl`x)Z!uVwSI5PE-`_mm`$F8l#<9Su9A%H&L$f7_)b>f}F4cj2zMZ)~jSjHkrosrv zUZ2m4^^pj))R0hW&C3rp4@jx98yOXDP|*l*l1XJR6-d^uW8`d8pbyfVF83vifuKz5 zqnzVylC=(kt^UHE913Y~E_ypd2Lqt7q`v0EtNR%WT@ z&R05@1;B?RDxsERMrFq*iMRH)D zoL|Jw@#xmXL65tK7F(esYh+SgNI%Eh|B>m&Hc6-j%ce{@Pp--p`wle9y&Y@JBI6PZ&vHG!2qS;v33^R2-blFGPLBh~>V&_+n)5asHkAvCfc?`@Z^J zjA_{FgpD~-(WU>;wIP(Wd(?RB8EO4P5*I|9&!-`|IEB0R*I7`_YXJEuV{DyE7N`^ z^=MOLlL2iv#8@H9``g}}o^aSi5ac_Sos+Dose;K4Ls{9#s>P|SWoHRk)iJ^EN+znf zm~S3e!t_Bqy5Ezkns40wE&W>&x24XtmY5q_h*Enu_Vst!vZ{ZRMl)$`BA@CfPvpOt8stxhGe0`dj;UBV$fTnhZq|S{ z>fU}v)@Lgr&^9QHpCaA*qDydF8h8K6hV_c8qR&@*KI}T#2KiP0v0nc9ec|D>>UUhG ztGz@PxhcJvWwtM_uz@b$-~J|JbOUK4RpH5hn`SFxxKK`$ag(dht*wX_Z*wBKh;zPU zV+eX*V3y%96#1>;YBS$Z7-#QXK-yEff?}foV1*l=uZaHXQQR??-V;CM@jg{3brhY? zp>0th3d_CXeN&nNB07Gy*huz2I;3y@kL*)x{Z&f+Bz%R+@akHtPJ^PiS^)zo7-EGO zfE?Zhn}d&U{kE)5TLL=(gb5%dN4;)O>aJnm%|Unj=WxR3BV9Il5>Ga8;P=!q-@ z-SagfGNTRDcDg{QwS8yx!(DH(H&lE)X~#KaQM?rnX}$Lpb&P_-DhFKP?pW#=e^L7~ zGXkWSNA{qm&g!}Q5|Ygd?zN84BXXHwZ&{dVn z%S$DHm#b3GHWt#r!<&orCddw@c)wus7=`7rueBU+>q9P4~bSSB$ zwB$gP5RsBjCC3~{4;YM)E&%~0MY^S%(FjO)!$#*uj0t1kcfaHP2cBcwaqoKW>%7kE zbNZ*)@Gn7JcYFUMVz|tG=#sJ4Qm_c*RL(gV(fV!DoOJxl)|h8ZruKLDAoCt*FPk1& zKLR9;4B~bsw8o!OIjH4{}w!5$7fAr z0(rdW<8bL^Il-hW4JIIeApAxTzX(U^im?QZvYPZ9EA$LiLG55<=2T(>$=HX-m#c!O zayL&pg>tgIt8++k^jDh#eYw*!XBi17_ z>i<^fuOIB3tSuV-3Cv=Q!>xF;Q=+Y@G>wW4u3B484NA$n*=Z8+#5k!*X(bEISzc`Q zhbrgs%w;O|C2j3+gFf{?@)F|4y_D2~O`!xhXzYWA02}Iq9Fb{J(Tk!+CjUIaJ>0)f z@p0Slj&3!iucd+L$c_19wL(j_<=A7=zNwcHR+0v-jMowA-VgZr>b?xY;-Vg0sxhZ0O`TgL!GnFyA6#2&Uoc{?IdUt=+ z&n8Nl6)QHFe`G!zo;sh)mFeWmMk1^Tt+jZk?7ZN4JoIN*8berIt=n7)x{LiL^(Ez) zF<*UFdFUpE&PZHNKYLJs$aAgLQ1`w4w7KMYZ2yu^F49Uvf35%|;`DC%l;3;ifT%TosbZ)Cm&;XQ-4tHLV*e_LF2ITuDG+(A|7ohfKO!3~_=1?5S8cSj zB$%V5KfH@iWAsZ9E9Am0>a!In!%nRT`nr};@~{~N<8@0p$Guh88pQn`JVm}F7O-0#K1WCwB;^Tei)h-mvl0rI|uMI;Cmt zrUm=C;DFOX7#+}GgD@s0IebDk1*_Sq|4jU%fBrF^rFuk{V_|g^%{5?-PjSSUJ6uI^ z5?m2}A$j(y^+=A{L>zhNZtV!2vChWR|#n~=iU22H$Pd**xni!r5u z`K_x6f(PP@Z{MWa=3(^FlcdznaiG`S??!)UnTitV3e?58^omtFPfuFu`sG$g`~pki z$nXTaV|?YP;4w7Dc%-1Z;dsgieOl(B0r3aY|Adf6Q6SbR7OpluBHux`*9^ov%UrIA zaMj)7JNeWtEQ-E}wsnT?0!R?%P$jl6gC^?JTo22!_c5bf(4SgOGKiKJi&qyZrT=_} zxWirHh_`|BB*X*$Au4Qi!MhZq z?-Rz8oh##Jt%3v{V>Pe2uO!=Q%{%IqBGS`Zb!esRf=+WtHu%KbVj+RA_2xyNi>?dN z$V>%()Pv7V>;BuVEW%#X;cVa=-8xmw@4gc~YHFG{$?6GLLOXJgckk|IR0;z?TpvFj zv)gA)kb*W!3#@4R&F3O{2FnOTc@gTWNpT%R?KZ-Y8aeYBR6_V3QR{d{STEZRfCBe+ zVpBHf$pm-P{qeq<$G4ZG1uWzq#OIaQcDz(@&(W_kQPRgk>I4zpEgVMMii4xR`au{) zp5R5=iQc*EPF-q`ik=BAKQm`5H#wJF0V_su6?YK%nj3d~Oe}*Oc3o4o`wJ(NDL;jB zr(C7gQr-_(<)ojIarB_2%sV`rg+1IC2PVUM+%`x8O0Xm*QO~AR-?rukZ~f6}5|p!x z_{7--^J$F-sHF_ZUpB=Du`J7^py_)jIMmE079wiUZ$Ur!)7B)rMdR)!U33F_wZO>I z3f8MZIJMWZ(+xw!IFhNSWk#DXm?b8l{K5G3pIDilu3@^{VWJ%TSeId}B zNUKF~p+A5UJbf7n<%nB@K~q#}`&sl6PQm$WnETxri2e77o}4dR6Ql~o5R>7wLmSi= zLmMoGX?XsO7qfDpMlbd5m{XGc_Ys=(bLlz1rYPIij%ny2+d}`(G_&x&rb$cD*$BIt z(#J%)){!x;>7Wu*8(7a6s&J^Wv1QtBrrl`63%m~oeZJu})mrZ{Eg97O6#1 zT9>ybd_3t}>0GH^#M8pY9tV)WxwcL1OkiGib=Gaw_~@}9{C$w)1D@n-zmcak5!-e! zUi^iwW9O$XeCn9?)=t1v+-$;)M)I7%mycrg<|~zbBL5LVZG)tX`39B`vqjz%$j8;X zO!{#N_gDSW=LhhpX5|O!i>y#NC;h2muB?VG;&wLV&hP$~3G6~NR9>?ED^fSR^V(}% zEO{_8Vq3=bKO*1HxI-cRwvNu)ShZ$V2F7HS#_5X>Ap4xRak@9JVhR~#Lp7iLSe1TI znWA3%dJlsJWbs~aOtqdk`VWR14(KTWf7v=)3{YzAkc>ls?Jzba8d9sDgQwO~=E5BsVQe zLW}jcqGFU*rt2;wH>?y*&efuo@Sw?#L-qZcrc8Lx~>q59F%w?A`O4I{E|ZJ!-pq4 zlHZA$B*MA`vSxLeAdS;V5lsFD7ln;W&Rs0s#s>obi8+W*QY3HYZCBm?l2;^&WZc$8 z9DDBfITzp>IXWV{7_!?h{|QfY`%Rh6d`Sy+xLG*bgt1?fOXW|Xs5H^j=VAGjtmW}` zxYqLd5V7_>M}yQ04Wr`29IE*X1wb5(UU&m*aU%g0i5SH*KDKaVCL8{M3yD5;2SbknP9c7Nc^zLi?*ercoF{mftsjc}`rEV34*)bT%zYtx18w z=T^JOheE8p6`p_#utD=f{|wzQMM<%MMzjBjev~|JL8N6M`&l2&e`)7&5{OasMo_RR znONfgCOA&lFT8XS+?V`J@81@zy!*Ym(qtM+N2rhM3qev7RZ^=jKtR+sbt*-F$pil8 z8?Dy(_jFr%b@AMQ0f!X+(!~|XXXjSORQGaKzVt|MujaOSQP;J}Bkl+}Ulp0GZ)ZLA zb^t*|zpCENx$F-}9gDszlN_PkH&ftKzLf5BGwY(nUlket=}V3ul4CJuv?*6hW)BLz zS4bg}n;JdUVK7Q>vC#jBC@z+5NU%XPQ6&9mW0=vBgXj|830;xC+Fs66WxYJp?5;a6 zn7fZUUo7fu0fg&68oh-Ul`?4a=qk(RLWs3T%!@NG@DfIatg-M#_R>w#K zHjsUEX+lOi)-pD6jlSG)=BkiSxeV%ZP`gpW)|kIC2+G(7>Av zzB-agSExm$a}IOutT4E$!R(Fr2NoIh!PhU`5X6^rUN*-VRWY;1tyvfa1gV;-K684J zsq_x~Y;IX=4t&ZjoRKWVVvJYNQ#O4+sOT`J4elyWYcg(J3QvsmW_D_?Yeuc^q?1_Z z)*X#jQxp&39!k7^n6@VwV(A;L_~9p(v?m4FDiS`jAZ&w*1~)IJr#-?vw%dy2aCndqS!? zQiR9e@5=N{nN)}FMxSxeti_~2*K^TZ8RnTTaA8mHfYu5jDABc zOQH6bi?HCG9Ounwsi4<3+!?3u{ZQzf&crD;{|V}g09A_Pz(^760Atj6grdcx3<-_0 zgBo$SBf^S-^FN2_`XkaAfq2t_lfLRLn`5^k$bUrrbG6v=K6#_{a7D>-oe~?Y#=Cj1 z5lANwnJypEzAVX%rb=94W77@qWNHE8OsdwfmwBDBi1ftt zKBgs~B!NU}#?+4uXqu?CvmNG77bWKWu^LkrJf|bunlF)OVVK+7U+uDJYK8hK5vVL( zUBsD`44lr(%C>m+oUf!p$24|DB$YB3=u|%8)90UzO zhiwXkC~A5E7$N6csGWR21~;HXNf`O}m~BUzoWx}D1Q|Wjp>@G1s*3J2 zpDXImha8F6*?0fxrgg`fEU!~_(s6|l@&oL#pkFTXr_m=mxTW~9;&OHFmeegC_tljT zdf={Zf(s8ogP(=ffl~`-6Y|i$-LwZj-D9a`Yak#9c=t#*o$l^KZ6wLGn?EKuBA4C^ z#sRT2n1OOsK|K5UceJG1MzGePn?QNBFmI9pqx(k;z2)ql{Y21GG|lFbvLF^#3emO( z{h2rLaO180W?@A{{r>)wngr0+x7)Bzn${--P7yj`<)N_z3?SHv#fF#fao$IXtjFTC zN;0XG2d?dBF3DDgD9K+iTlYSm582DDhj-nN_qM@W_!Aj4%bPVh*wWxAs-=jxt;zrQ z`){m2+B2UIC1i&m>Nt*}R$obLZwJVksS-osB6q@?x9oQl-`u9$h6XWFS&twtcKf$4 z{g!oG2T}_5SzD$sPAQmJzb`D+W0|@M@LJ>I3g@q;IE!>M^jHhDv6E%u)8;w2f00ML zJ~%Rpw)dOuyLFda;@jwUa4Aj+?KW8XOqiNrNhBjTb0L&DR8>v6Yu70T!e7iW!4*XC znkQ!y!jyTCY{}Zk-6*FB@%bu1oy&tx3d^@4<1wygrcT=^jR>+`{ANSwI)`*gzB55Z zqDK?Ik~-Jr|FbYgbh0-Bq?uT&>x}C3f@@p4{cP4 zQ482lluh_d5Nxp_P?=1<7q1>@S|mqETNH&CW59l=IMGDk-rJk2&??e`D*0Am5G#8qQ<>meu+&~LffhLZSf`9_~GkCDY1GHw3yuq%tYk_4A8%zn* z9_qT5NPf6APF1##=Al&5su`#b_%Q25%EmEnSa)LGGtnO>bXx<3q1DCi;HLo8{I%^< zUTjoMZyBxmQ#8ROW;1g-s=XExryonA67KBAUl9KzAS9tOD3dria6On2&pmy7Ies59 zjp!gqoRLo#iw_#t_aCOnhn@38X;KWnYq%ZQ&yhg+_RvHcf`TMkrt44d6C8rieEBoo zSk0E5lX~)ujMPb0UR+ggx@}N*N^wQm5T>|MfZ5`RplAD6EbI?nR~)+y9Vb1*9bOt@ z#&64UerU#Fng~48l(&wHj?1=J?(e6@Z_23HcV;adn^of zYqK%lO+(wZXwhvaIv%AgUuR&v#**cE$I>@q{WMT$M>pK2wzwYu$=;)i?^W{r zcZh;v46r}Y(}RRujVeWfLXZ#UkF+uD(OOGQ8c;h5sTp!F<7I{13%1up5Tmh3GyqW@ z%`^K^mkz3eu8#9&2-8hF8uhCLT}gO7&G+Pe@SHNHjlqs(2W|m(IK}e6Xdq-sa|BIG zbR%qNogH_sbg(v?^CW7M8DkSxAqa}e|A@F;b{ag zewZFMw!~R*O$_Z9MfIJ8Rs|3$wMTSO{S(S^OE9NB80?#d-#E$7?v55DV!wd^Xx# z)$u}iyZ~6J8&=<*5mZyYFK=A#j>0@p|2ioD8$UMd0Js4hs<7w87w|wuvCCxLi=N0k zC9ud_(Tyya{BFBBpurX^vP1BaEs9t7fgIvmh7+;LI&ndFT4B`hnmB2(6Lu+34;TE4 z>2%VPz9T9>n;7I&yZ#1O*sifbs~z;sw5nU{aW*TV>gtsEC z`mq5D{mf5wTOpy`Zn6y@6bK!}l-{OP6JW9kF?Ps1t#5HZ$SuB*URKYFv6>IMAp;G@ z-vT~P&u>W2FdiwN7q+MG{lKxnTk|Q0tt+jCe`REz{_baw_w@FNyn6c_;G^4M zhJKe?0x9m&1Ily$zBalTSU1f0kBFB?rI??O6I*ek!`iDmiEIhoE_nFHuDw2G$B#Ui zGWePkQn2j*TQa}Rl&4jM$CkQcxiTi9xkBf4GInV=iJ|F3VRC$|N zYIImBWPbp(30NqS47~Xa2~Y^dYI0!^C{NL{PDYVHMCH;~9_{69(RYCH!nb%v5LMyb-F@tUVjOFo3QZMeZshME!6>dH;t7z)XY_QyLq;LRetVn;_K8d<8O6w zVJB4X1}-$k1?in{&D$e&5=2{uIjlvK%OUdkm`#m$ zMCD1=&i+AR{z+JZ=F?-so+s?>u;^~*{p^n-b@5u|UME{)qs-D^^r?OGjI@$s|HF`{ zxmxLR%bZGq_lP{@)1$?*g@vo0G)@(wGM_cpon7QI1 zKJ!iUXvFo~G7~XzfYN?X7IvU>V((rX*Oi-7ebnywWSQUlDEpV#_0%A|(1$6AHpLPx zlhrEveLjb^qaCm?R3gzZy3FJ89njlP^tqL)u^h?LK|A;CD19F-l$rNvL$OmfZXW)+smBJV;=zLhb zf80R0^e(=7C#wnW~fAt+Dzw$p{$>??4~$ z8{H-yhOoS7UA3XXN1}Dbd%hW2@-iV62a>>anNq(}LIi5l^TFAfgxImyo=e-wK>wmj zvgX`AK1ZXujJcOhOur=mBNFyOhaDPHWb-ec>^2xrL9zNG^$b2Oosec>QF{*JpJdXy zG;1#Dr@tVw`Yml!7kdx!`>w?wZ8&_8!R|{n5$S;sFz-K@xTpT7nFAJHgANvE3YdAW%X zf{*~ccE5&ORoiCX*zw<8PE_ zFc^1^sipyKq$jOVHeA}(WoRcgHKfrxK10y z8r6S25!M6-D;HO}uz}@oHyx)}MQsoHl3oB(?b_3ZUxcMOErDy2-E6#!Z8Mg*8Dm8kwlKyh%6wyT~ z-zR7Cv>m+x#>m&y4eWED-!=Ll+?ktyAT#KtaQ{krI9uLXq$u)z@bY1_z{n2!@~Ul| z#LWf4%2iRzw>r2~pDhAzpBKe=>fCgvjwa+vM2BX{1ALzd zfo?buFjYG)!9$2Uu)EVTF>`-q_Q9W4<}?-gdqgl~!zKKPFf)7-c1gGlt5he8!skYE zPZDp_Ithe+O|TQu7C{^Rf1?)?;PPM?yYr0YO-r4nIJ3a6^jTJ;9hO)q7>Ox`aT#4C#BglBHMF?>4(WBo4p@Xpg+@vV`oBl|j)^ z=G)4kd;9Bm@uE;>Y%ysZR8Z0FCx@gi+9!Oo1q!_Pg>X8PErdJ-p7=cb=b61)qr%y- zk-MPQO^4G*U4?t=(!NHB5o32>5!9i?&CV7C75jeY;~CpVmX_a1k*n>xtwS^tw6CGz zH^89bPLA936J;*QbgyiX;AEvT59n%*3qYf2#{gJn^fd2j67nn_VW>*!mXM@{e7ZL_ zRR}t93kB3y{zsJ1Zc~6Y>9V1LYM})-)5CD2fJjAIWGov+pe*81>gA^Gb!B0>rjMcp z{fNnDq)3ZN98T%R6?;gKysIDJN0#~tEO$n1Tkje-LBFU5BNL-r1Aui{7t)xWDe38n zmA6NH&)-a)Gc!kjUio@};CUk+uetUg5kFjc!w;Xr6aqEdywMRF%wbE^pJt_PCw784 z|IPR0K|UEEdcji&(T(k-J~A<7+h*%MD-K0VFDq@M$B*>n zZG()+E6hC;dh3pYA|b|OTnx^P*3YIFXqfg{pH8JsAjezcAs-JXT4~?s+WL)wwsfP` z?x2sy!@b5Smn;s3rGRWkAH8gu_}~N$4~OVnM>pZ<0T?8Tw8tVbA&3^8-b*I+6bkS| zf)Cp)@PIAv58J%|-mvcW+;jk5*UoxrRn>FRF2l3g(KQCg zXPc&BXJ<;9I~{Ep;5_5@C5#-ZjXKG!VqyMpW)|VMr~Csav|DNS_O?VAEz_2VmH9_| zYE(aOmqmwFFeWU}9|s`0A|omh)wB?oG1!p}HUnt>F3hJg>$890voig6dl#uDATAH6 z%4EC1MiRIT>;K2Bs)R`Mid{f8rFT~l2m^4@;tV!+;JUcyf1!G0C@d;6 ztU-hnksjav`U6tIjUM7b<)ReCT$P`5PZXOh@oTfwc~Ohd_a>Zo%PP~N5~J|KI7zHc z36{P$mswE~DWpw9-PCW~kkZS#6Xs#QW1;QoeiPB!7=w6V&U3T%oN*7)`2>A+EP~AD zJ5}b|GY14K^Xw_pqVa98P3>xSY|yUh3{+Ms<4a9iQ?gLW`=qTB?$_?&%p_U3-HqIM zf=Jg+DjOfZIv;@}tml$ps=QAh0bva75;;;+L5sO*JHz6<5*BZoiR3jQBnd)lT`9Rr z(-Rko%bA-I;V1#j&-wcGyQUUcL)CexLLp=g`3g0=%pY4|bMTzSHMy(iW0K^rm8W-u zMb*WvX-W=I*po-|u73%nzWTksEA!hn3R9e84do995@InuY6k)*;QM7I2+nq3ErkxM zL%?EERv;}n9bw7CN%QB^odcLZJoWftwPp)ma+!hfT=FuqPmcL$(%>yrd}p@j2Osam z2Ow+v95ytiroO0QMcO=B%C^-@wohMc#)-ex{+8lQ;26`p%08|ctZFDTZ@AWoXq;1x zZ=$?CfsfVEzX377U;g{cOCejeo29aR)7hY(Ti}+X39xI{Gj;g`P|w zOZd7-+Th#WjM1-my6A&Vx*@LtUf9e&h8FeMy5$m^kU0b;`bUony;*p)$56-9Pd_G%q8j(Qi&T+D+D_7@bQmGBK% zLN{j_SZ>z&H{|akCGiV47oxM}wnfLtqowflOxInyRiv`Ma(&H0WyKwlcbni!`<-?D zuBSP{)2DVHd`0S;RKZza!SI%pxnI+TjFKJIQMO>+p2TkU^jIaipA=`ymZq;CL^riJ zLyFbDpYQ;@XKuxljE}z#d6N$e4)aKyC(}URXLvVHvv@7qr|6?n(USYDwejcsch7iI z7Ct{q?svBnuA`KqL!}J<^(9GW(VgIYO5(w1>ID4A_h#F-w3k-tU?;cK&)1>w7C|3c zyhDnTw$U|isRa&aSICkih#OZP-Dh;4KDDR(Dmirfltf+o%f~+@i3}-z>7=eN#Z+<@ ziXO)v6$Jk*T#SCMysyL_K&&$jUNFVRtVXzcQ%nXHp5X5ej)g5Vj1YwyW!KK7^DcH3 zmwvcfC!GkD{GWG4uL<$bdTEDvyQ3^s`^kqui~q$M9Sm zS0XGAWIUJ5o6YPpWa~eL-^ll@HWa*12BomcELB987i^Oo-Vs<>PheuaEZ`2TdQ9*eh)J#-i;cUV863 z5@VfLoJY5Sow~>D;BZs)vgJP_4ZQGt3?a$MzbdJ$dbs>HefKVr;8tMDEd$MX#{T0# zm*v-J^SxRrb9jvMlSK&JWMNyz8u-}!e*NG(Qgfn1oOIcuwQ%ctc)Jjr3);Lh5AC@L z{?lI^Whcst)UW$;@%RKBJDil%uYB`r%C@lsEgQz4X@K>=5(x-!o%$hdLqSR;>U{8uAoT6A zJsDQNT&@FAu?US`Q&k!So7UGl9XA?pft?pzPgvOXNa=oo6lp62Y=&Q2>ku!%D@X6}>lyvTWGU59m5Fp4`kO zkO^wYZOo^FuBj>-W!6McU*6zpo2SSRExb)Dk=Xc zg%})Zl`bp|(VT3ZgR2iGZDm9mgc<+ne$zT5-?ei&B(UlpHt%bZ5#fV4}7S9=ixa#(O&F8X9oRwv! zDjbBIeu4D6dD9w`G0tL%NiUShUmh-GxJ8{PN|!@mn83EswYh1;r*$gxWn_G1)|x|B zMrFrQHCWL-v6)jSS|e~xPp&9Cd)N@97DNW_*80isPD#f5lie@Vp$m5p*bgfI74@Ml zVd8b!liVCWt*zn2o?6)CqUasiFU_=QH`>D;A)S#x(A#dhjO~ZVRWfQEIF&}(_J`E0 zO)~N{$IBMW-|uC&E(88NGK2Q=wWGhS*I|PkBXh6qK?&&eJ{oGALR;vm^^EY=Dv;y* z4{(O@^wtmj80mNA6JD{wTk-PGK$v4)!;fkfQS&7s3qQRhZ_W2Ztm$}>sc&y#O?ro% zbf~o!N*aXo$;qab%!^;qmG`A7zB7-o)%uRGtOJgx(*DwDp^d*l}hbK;u~TJg)O!B^k0VR~sgY&xoZRPef z6oj-FlWqdeJM?H@a?c0|Rhi-tf`mej>O+piyzE8w8WIkv>|g@2m#YmP@}un z45n$xnp&KcW$fMuj)k*M)qov#~n-g9Ds&wW!t65)_~-{?4eIw2te!0UyrW zm%T1F3H15%DTuk3NkFn@d6cZJQe~wcwHv8uv$=X7b4I*Ty_nLivbwmqI)u?4kMaMe znEle=^Qhxr3F6z!fzLuD#%(h}GKb~@QQjkD7cg>&fmkipPV;M2;Y^&z-$^TL^o3Pf|-4UHr+_i>4MJk|y}+ zu0c>6{N}@`8andz?XPO677A{R1(fYGE_tk5ScvrZO&?|`vhsSazOE>52Zc%9@C+@n zvp6n{v?Ux+kx2#8nB;Wlnsiv%U7a^A-p}-(hwa0_$}tK$7uEJC>Qs^2%CtNI%r79V z^JoFbV;S{wU$4(@0FwWRzLuo@rLHDKveUIc6By8LbECj&>olR_FV2?^>8#90xE2ic znj+RPh#sDsAqs8hzDPOZaL8IVQpBwve!tzqVdIuZZ&FchlMuHzS;0O1H%<0s55jME z=Cr^-ji^L$s~(O$L7*IUojdVN_l>2c}$bUlQ{C7V=#Z7-t|;Zj%(4E z&=Juq@}Wjv&2);57I!8h#^cw7(9j$~KbkKCDH}-zRtGyXas7Xmv(aa!S08Bts)mHbY31> zI`T{V%XKP6G9bH55F>sxz1QEZ-z;rsNaRuk_5lAzt#@&W$ovVfr)Fj*X%X4FigFg# z&9fRmWy5^j`5cll--l<#`k~r-Y6&0pGit4zZJ$$ME*@VE^z*H9DVuzHCi-DoZ~mz z?l6DXkYUb`SbIk;cX>>zgQ}o|$oBiFK42J#=1}j2FMt?9e6^2QHWU*Ijy^|9h)9Y+`1Ws9|SQ&SslG(F}E z+BHKFgn%=G4sT;Oa%l$Odto;71i#vLPQ25VSLFkpXa}Mk-E6)6`{zA#zcqfXFGJ0+ zr)Z~Mr2c$62oX*PQJ>bFgzxZ_lEjp@`QV zydKDRK#p_aKA;2R8}o`62W5=MtdF#fZ63TmV~Q6B406u{v=@bWN<2dLHu)ndp}nG-a^mb2d%?w z^`B$6(ZdRfQey-}m|Mcb4>If0D|{hO8gVT{a?68??$%^z!#8x0y1skTuw#jj>?MP! zm_3p?z=!+-AiRD)qyhXXV)|b8#N*2$)e!7_A*}o5R#PS>CE3ETz)u1qKa0Rm4q|Ly z@;*z1dR24WCJ7U;E{WkhL`{qJEtd|u9fSt1Ta{~syMrE2es2@(WR6{TU9wKCkb#of zucHO0M3>9N74=BFuU(s`4%O7}kABx=7RejV@;oD`t-lEVJ;um_gLR7b_ZdZ{w~2|& zmYnxxGA$_dG5Y_=@m>UgAE(r0L#2?Z75zX+m`87qi3R+$nj7v9`=IpE9;<<1*&z_D zAFLxp#@a33PoGE~ws5DdF=ta6sFNBgMgUY*ILmLqi$EBvp!3PT&*zq$-j{xbn$-@? z4nwZ%@i1xDW%IqB#bXD!nVT@OJ;`pm@5V#kz38U=*B6_hEuE26*jn{tl7|FVaJz=MA+ST z4YB<`AEX0vsYa=@=_Knj3w?M##&`JL%-$;C|77^aT>xU%88%T|5hpkuKhMo&Ds2lo zNb;bHw!PQ)p5+rn61C^kE*1nq;RtFVVtuK3H;p&TyHXQx^e@Qra(Mu>lh$;b{~U%; zh2$Q?dZs1_&e375GA_s4d^1c#>QX755nGxU&UG~wq2o$A%l}YUeCwuU)WbY0VWcpL ztZSC$i5$DNNwjDfdb3N!36zV$KeKQm%vvVksgiiQ!~{ws>z?lSGHQgwJ!NZH{g(zq zO}uq}O32PG(1G$aH>A96k@>^YH-GP5!^Z9pqjx(g6Re|6&7En-r|H@=21|0}8oR=i zt1Dbu;F*m91$t{U@6GY}p@++CU~Zw;ZsIFYgO=!%M9Yq@iQhq?QBYZQqn7d%xIXH5 zQ?L2~HoNR;3rAQ|-d3W!3g?vrJ{AZ!GBKL<=IHl1UbwSc+;maBOE|7VVE{sx9xE}htS6hYq7>TeRBrZyZeWr-?BZ{%p?t95bx}U^Ur~qfiDPHetTamxGQ}<5>M8hw4JHze$^YLo?u>UQL3$DK^N~BV zK^)j=lLq<1oG|I~o>I5ct)B}!wv3zK=^8?)`k^+6(@<-kX=R?*DERSbbC=e^XsJ^Q zjgki=qN$#x*1bS>Fz1G8UQ1NtgAGje5fA3kZ3vzkM}(DR3ahuF?nZF94YXRCaM9yF zAf6eV8=&7O^Phuvj!hEQ82#?Ls}D1X^VTss>IgJ*JvSX9ltjSPp5~x9$V$@6W34TkIaiEjLrBh5S z0chm|eK0NBPP{1=kwc7aLuc%G+7Wbf-;h-PSgj;Y%B9YV!sJE27o?*e`VoIoFp`F2 z*PB6W-qxACiTZfSBPs%!a;|9p&1Bu4XBvUbCPR9}g`+pYlYwtE2#zdm91o&8_A`Da zhZbwIVMC15Y{r61)CoGRVV^SZtQ&XZ^eL|lwl)4Sr_}|oLV3h)p^wcY{5|{}fS|1P z1-fmL_S!71Z_@AktJiupwGet^DUgo!-g404UqN|SK?{}_qkc>{`f0@O@$rqg*+E(^ z37*Fq$BYG`nflxhmj*Hsr;)}%e3R`u5`~3XDZtQO!iyrA)2kcy%}YPG4(C=K)Cark zz0OQ{A;7*Uv%0_@1@VDWuw^H!?b0++iUEi~gLC^UH;yl_7nqWMgnaD_e!;Slfk@!V zcqb}@?;s*JKzRrY`du-tNzO_WW&({U17vVZ!Ji@KAZ5I$RX)e{@d>Q{eCx~%aFJJ_eL z$Ea29X3Hz~ohLeUnPIuRzBJ}R(JTn#oyAN){&jnh!+Q&yZ# z6S_LKs`IgPtD2v`CaNd}^AjQiQKD8VKS$6klJpX8x<8jOUuLB%bxr2@e&2`;wX7C4 z44t{!o-G>Ts(D3LmQz38f2o%?9A@0EjpoACp>2+OQKy!-MV-oox^;+7NJLVR_OG$c z3PXj8uoiDoNWOz^fyJq{wP!^Nnrezjn);20WYyJD@%u$<$Bu$T#E~lQafWd#86-Uy zBWz%aaimPPvpXBMt^a`DXQO=ETGH zxA)tOW!O_sLLsX$q3m&1P#W-Rr8LYvE60rlR8ycW&0?^^c(`_FIDNZy+5mpU4uOTK z*L`(-n{D~1(S8TTT98+3y)L5<{8iUoKvCyJAUm~^Gt1^5Ji1#2XPNfGGyCM*0i3Fk z$%bPpw%O&-eOc^0Q+hgN#3^hw@3;T@8(4LJ)mSG2Oa46b*D(>n5GZ;(agDW$Y%D91 z$N2B1CH`dBxuPbe_)J}xPEHrPMw_ENkX~Vk+yV3&gIXO=X#T}1wgCnF6 zQ@1A{CDt=>1iqpZs}--C*sIyYTy+0(aZxCNy~&SSZF$>$Vsl4zGza?Wwt0Jt{zuk_ zd;gAxzk6wKVlV}LyYXD>1KvD4nP;6N&O4Si;0P?!9Zcu!d&Bk1j4ApIcG64dVV2fN z|Hcna>6*}2q`YU`>3n+Qhu!CUh|a3S>E&)ucT>;bEmKW7Bb^B!7;^m2ziA!%egDXo zJ!M0(Xubsa2q|h^pveAzu>Z*id3yOCGxf684$#q>CcRXaeGW`UzUyh1qB3$W_ZmUF}xlTkNbxvry1p$ZyanSA+~`xmyZ6+=z{Ol2XX0D8UKbe>6HXYPynTbrrbz?X;#>Ehz28 zO30m;0+w5SMuMrux^7{3qgMwO*y&d;dh#&Q@gd3Up&UUz{VIO;;)U0Phr1`;`OG*r zTO4j2)CANCKj|-&U`LNh#7OB1B)`zAnJ3HIJNBTiPsrPcY$WcAS5kgYGuSB~-d26T z(OS!?di4)-qShg8#Ber&ONx2SwWO5kIP7eP z$%JFarsimT+4g%DF|%#*LR6~EvQ*pAN7nX%uSIjcrxvkmR%5st{}AcFFkcsI$=S>O zhWEt;oxXj&maFk@5+{>rIyv=t=I{K|zv@Qg_IJ&N2nAmwm99G+_FE_{-<}1Z)v?=H zZ64_0yc&aF{j{@LjMR7%QJDFYlu#oPs*aA_53twLo@=TUb%I2HoclAmtp2n#yha86 z_?_=X8vjtqx%uXbqj?*qU6me#%%|&Uxv?sN0p=g9tg2UjOG|>)eW`o%`;s-7Dn@~( zDkZ*AJ;IHm`Z2Nc3!R(~rX^q$b5GAw+}2<@8QC3a`1Ma2-g;Sm<6da~QLP0V`>;#- z&gpSgxGPxF)zACVyZT3`De0wO(i;Qm13xlv-fEm^l4kQz$y{xmJUZ7J?TBQsY|C{K z_A*e(KN``;J92CbDgrcCi^MX7O{>JQy4@ji;yx79Os_A;I+8>M$DG1e;t+!sc_GsB z!^)XSbGFV2)>pk>nE7NR1f~@O7YWAF=RET=vA>}BBDN#me!lr~(La}E-3Jcqo6AN4nnV7vJ@>@3WiO_w!!jY+)lPnDIuea4g5*sg%FE+c)PPtYJ6je<1+F*DDW zbff~z^hkoOJO(2FdSiT?jv`JFhcG&j5w;^2wh!&lGtyxG%2#r)OAFYtZ>4V82uih0 z1_&@2%?9w>7Mvc{NK&3=p;7vebIv*+Txfn3u)^S;+m}7xy$zbjdDN6n7h)9W?w-Vt zIosuTiH!dhAu+^Zo`HW*h10jZ)nq=}=>D?SpQYe4OjP}GWX|2E^CU2J#$E_+Vmr5J4TtJ^)RYy>q!pf?;};ieqM!d zrlCrX@NKC)P)T|bA#SsY6RoTCAlIXTGln)rQ_g4m)p;7cL}TwEsd2kqir^ca*6yY*o;rtJyEYYoychnu zA>?jw+2o=Fcpy9FmH>kiWyjl;BvniVrk(1nQFZCN8z9TRqgL{wFeVUG^q;-r|z-1TODzdB^dupZKH3J z@!=kp4e7sN&EX14Lzt_$Y}9F+OAzMV$Lbxa#+~f3RI)nsD=t%ZO^uz+T(liB4L@!UCQJnyO~B;vV^Z>+0MwAMR#<~+*l#FTVLGR zf;EOY!t>_`&xW_qk0#hDLb)^(P>Eg6upS@pih1;)pW3IQcWw}{qLqs}wZ3DBA0O9uid` zRM4bq86+|XIXcgRFE=%%>1CK=kw?&#ddYn&*V${H3zoB9wcJPw+{VBao#xliLSrCQ zpdTiwISW>eNZ2X{e73n1;O>shlq8b%%k2JGumgm!Zp6^F8{8c`h5cBgKc#I`_Ky_+ z8tDStcUELSRt32VkYB*$)!Ek2r4okh?i&ZF`!64!*JUFBj07^8j}T!qcP5S({c8|a zQKkm4biWlQT6ng%;Vw3wB4~*_BPN zLmq!{dpR6-R9AuYV%jI`Qhds7m4wEmoW)vYLDXh=@x3nzOl_>Iqz&(Kg9m0VFG|uP zb%HmR8+gs_w-(Mz>z6rO5TW)2(9X2?SuMg}4@SdpO)DGW;yV%*Y>4)yj`JvCO_* z8yk_cCFSVyTiw5+uOvbm4n8|hAQkpY13M+Lp-WjRI!vG?Su94r2GVn?c&weAnTEoz zM>^=gOdDRTm)O&}{(xx|aWn~eu^*j?M>3L4dQtLoE@UVv(Imr~Y)KgOADDzc5(sSW z&;I;Vc-OWnApOEiJ4X8A)NE8Np8L-yqVAePHi?fdm64Fj9&FfyQmH2+*GxEr#UJYh zEKDJpeHSoEhxa}db0n>22?x$NN6RTymV6+zYseB6-%{8JM$dz*)`F5?`%>vo)ps-3 zpKtSp_+Y5}k*|ZdfRahAwIO>ClrTxO4yuNdoSw0;N9y^w^2i+g90A!y)8+p8TQ@(T z-9jpl|D$mUuGQ5zrv_17*y1~i^B=6U&I@R_f2d(<5Wz-pP_3ruk&{=)c-ZJEeiMI= z9JwWQto|-QyQZLZ-8&76GOV&D;HU)8OjNaL!}zg)+i}}@jbs<^FtM-)bhQTbO~##N zEsq^s+Q18wp|s;vzYqZx~N~Yqnc-?QpcynphOe6Gub6e0%EEN*e-7_oB1e# z={KP7{0~^aK7W(%zh&)o@JE!-G?Ql@cysD&rk1$tW;=Y0Ml9yrDp(dkU{<`(tq^?ipBqb$h_h&_1M2fCriEyL^MR zlG=4$+dE`+!~n?=jL$=RhmC=qe= z;^^`7I)AUcHOeqOrxj((CwP}seC!BF+A5$_d7^e-XG*zXZjmD^M(a-yR%uQBUmY5| zn!C(3jo~I0_GATd`Oa^DXpb>;GcB5Fp$QbsjIIh6HY0~2#T}Lm)j##h=!?6mYPN>= zI64Djhg|KkK5wQHne(zedxK4GKnxro{r#uL+EEn%&x;yaZzBvhmw9GJ8wovCEQ&@* zvQ^hD2{2^$A+S<=*smk&Dlq12+7s)OD`zT<{UyG9GJ)ou{m2?bB>AKlm;EizF?u#M z@XhMdi-iG45C*!oFStN%?9M_78}7JtrFcF{E;AiZ+c3;Ziu6^#7>H%4!SH^fm;)yu zQTGY4{H=yauwc)F>A!Uh%l3;>bs?*HVKq0K??^hVT+ozkG-fyJ+D#O+j+5{rmUcky zHm5Q`+sodBRR^0IHsb9sj4uQAEZJEmo;6nUcW68mlwU}FN{W>Wc`k3T*(Nerd_>h7@na`v+i5f&UXU_|OFR7_Bl@fN79 zca7O_B)U}mQsI@Be^0%W$D1y_wym@&aLwcPUcP_VQ{E@lmscY~st2z#LhcMaGv&Sf zq@(doWT?4?*Eyu%(l6`pH2Kb5;)SgcMGfo_x>f}NBG|3hoJ}*7ZPT2g7Vs-QyWDH3 zlv}u@GW8&HqGW#>4En0=YggPuOr_2~`b(#l(FG&E3W645r0 zDaCeF_ngGl0K47T>gB^B|<3$7LGqum3Xjn}=D8t%x9?Ggg7wLEh z$1b$&>U?M&TdwI3D;$uHQ$hAJrPA8Dv&j6<)4pBGoU=sDIezR0*-IVj0?#6@ZKI?~ z(s3Be@PN`mKOZkJe_D`Cb9^+0U29WEPt)OB`^wg9Kg@dg*3K$G-Mg<=#YL!#Mr570$)2 z7Rg4->HdwYMBAjoQ1Wj`%67EDH{p9I$T&Ek{qGqs)wL`Cyk0|WIasw1)Yv(b#BGyO zfCojg523SguEmIVcc!I*rPJF}PHM6jaWcF!r+keTz_tcJZ@F4Bg+Q!`OW*1w=4rF#v4@g(?Sx204}TlxM-VmgR}K2T(V9~o$>c~ zTE`C>;ssL8IqPQPZG*hY#WxC%BOnDdA(twJwGfAPuVf$h-WgSy*@c+qP8cKngTjF9;u$X4t@I|@-L}R8_$H41{lVBRZH?GUhoZ7aX0Kc3xf%-ALNkH5Flt+9 zLY-TsRMNyZ<#62x?cv8k28u@fD7A^r9`a<_^jdp!&MU@ep32LU-wrhc%gfWlWlpjp z?k?N?gJrrbzKsqxz81Qx5z{DK&_bU|=4pE1ZyK6r!~H~D$c5iL#>|=L^E+I_)jng| zj|?81A?&t#tW(Sg8|Uf~>6Oz}3#+6{?t`L=Mqg186<;BxR$U4DtQ$fl`p1c0{`B`P zr~#E~fxD&KyMoMJd^6AMyM!}@+8+$3mU-r1X}8V_Hf1!s6qm-X?n;+CrIXbAJg23B zv*L$e6z9!z-0YLg@t<~m(J4P)@lZFt6g&!gchTl)@yrtC)3pqr#TK7F02!D6$v!jj z9Jk(90e$t34;{@xdbl*tNXTExo!oN4eM>|8Dvc2w)RC*88&GbP#?(Gs9PdAk;E*sP zahkME;AS1K4ETt=4nbQxH(zU2-jABZzQzIxzR3{IBeEJd;6YtE9xptG<*n8IiC!z@ z*uq})hs2>R1ck|;LIkR_75OEKqq7!vFZ^HiK}rVg%~ShEKDQCVhmrmijP48K zD?xFN{~f!kySBo#LauXY823u~6aXt9hq#@;Z95Iqm2t;kDf`fzFB z8$L($;Z7noq=To{e#cg8+M+?f6 zovILc5F5GJW@0qkjlg4{HymkgY^wYdCeEC5s7M^r9NUym1>yk45|GVf6b^1YFe3Zc z&{4SUPv3#KsGPfPYxxrXvT&umtMBM;z<_j|K;Md}g}cK2uiu3Gh4c9_7I-@V4$Hhd1x1 zf1g;?!K_vy^V}KwvjO@%cK2BkMGnLb#zrDErl`E5T+|K6Y-4CmjnmI74)S-bd%XlA z(zQ)mm#X@XnkPTRv&pjeR_DDOU_cSJ9Gg!aQ>e0RWJ$~TqY<$_#2u33w@%&u6M!M< zU3r5;)%Y*pAa}&?9*Uzdr?Td%1qWLUzC91oBM*=trsStN^~jjX-Pq;6h;CvmT$D+BSn+gQn$Jk zc-V6s`o~5JO^fb4yS)mnarw3_z_vQHGrEYP>#+e(kW+~SyTabkx1pBNlxF}Lx%EwJ zft-%BlB~%y!EUf!nr>C1@q?TxL+TxgR{PP|YhX4$xZwH6zhRD7q%y*Za@{C;l0)Iz zKKp{b9TasF8jv_x6eCgD+AOJh%U(yJP(o^@qj2Ez%PdhHiOsLcKX2=S$NdHCJ}m|p z_jTQyqHwN?EBzvgB>{G^Pr;!}#T*YB7MFSOsnE@~0Q#iWJFCa1T6ph2E@$TOTjQw- z8p3epHee9(Hq->H@^KisN?UT><8i{m!ElH`N7MMH(Z#0l;5ym!G&#^N^i1xek~i4_ z!EY%XiI}R;N;oa1GM<0l1}@@nngJ^`9_@R@wPc2YQ*^JSBEdDfLffxqGjue~EvTwv z7?G?neXy*mp7PNd%JU5@N464#5EGA0$R}ryg0-HK2D(j{wj6}Ug{F&%`^VTgHA|<} zVg7|W(Yu06k0$RgUCoizd>+IaD`ZG=Ja!--5{DhgT0{f9H&Y*p0Uxk71y{!#ny_1K z*XsuF(;G4IET;cJC#C5M#R(LOD@-y}P{cruG3CH~veQO9=}+aLSP-$1z$v}@5hY4Q z_ACI8AvYkV^7DckpKxj6g2ueh70HSwbTWERDWr)0Wt5{hb@&)@z4`nz^@=-)alNaB z?7ilV6MoRzFo&_(@gcDBTy7@6Y=U+xYm5K>lCC!_-0+@Z9XxjDkn_&rjpW!j-pz&l z+sG?GmQxKGaXN(;80%p%G$GwRgT%oDYPFT#9CfH_7!=ELIk%y!q-2r`^%}`wk|$nw zz>%H$10g_^pW_?rL0<35?c!{kh8>;p&rPL?woOabefY-?onRQw@3Ma2@>PiXV|#^B zOn0kF={eG1_j}^Sj&PUQWPl66mkR!L@psL7cTL{}H0wq?ayb&a)%a%Hh0TEs@kfC%&nE{@>UPVC zeoxLzvEFP68Z?cQ&3PauxGLFsZC`+V?ysO107-Z~QmpxzKWy?q`t)|S1)h`3;D_t& zm}_@>rlY=Mc!{%YI8g5i6_T>@6#`(^E^M(XzHkkrXMLx!6yaRAzT_8lXU1^3^D2$2fVoW}-P7@6mzZa0P$K0Sexap(7S0Z!@CAo? z>N=yd$BWco=}dkxrmjv>T5_KWTPtsJSt|))n#Bv-u+=ddTNR2GiCR##J?9Bq-4`7m zPPLRt&Gu!w31g;tEdhkulQT#TcX=VrA~R~L#8^#YEafIjVD7`KnWh3Y&{1A*M^sL; zZ3@=ye4l~{d1~n;Fn;5t_aYfg-0y|3t3C7nY)AHckf)_$nRGi}awauPgERKbq@M z#b<@}TT^3f5D!vdX&N;(vi-&KI^p^PP;u~tC|c}I(j{m_RgmlYaV07PQ5Z&I$2Z(a z{sFG}#F51+uw%O9#!fEj_xL(pLVu0nS^fXSkn)nElM-qV)SO6n3$4kWb=%N2lPho~ z;-YL>^y<>vrgoiJ>7_e^GI=(0>vwG2OOr0x4rwf`DNIxNi^!3~y?hi1FIAcHB)XO}N>cRu)NXGMO*xjQr{)-}~~1}K}Ar%ns1MPtO)R#+8s zLOub0#&NMzSZ7UDp$M{DxP&!;Y3g@@PJob`hLK;r2T;sjjG1=AOa?gOg78eziIf05 zgu6VmOe!0gfI)mSe^V)8^TC1N;q4Y#GRK2DzX!o@K23St$B}Jj$GUN_C3GD1Uhp>1 zE2)@F@g}g`xLx?xe_R7lBQP3wLdS94kafnjE=AbI=&-u(ROVp1weze(n82_6*>sPL zoyIMy@Z3!_DWH{y$t!9B9LlX(S>RU>=%Uj6oI3(H0kmmGrY z8X>71g$aTxBom5-3M#`dYy{N^2tUS-vEknRX#iPoV&{{4s)rZ>QhK;1B=#`g046$G z$b2y7Qch7JNusjxwmq-$(DK=4#|DFwlg953VevT$jG``yzw8fag8V2JWEb#8{HHFG zYdoj>_U8+pw2}G1N^lViT%_W}+U80R78in~;HsL@7peM=3Ox2X7zp3Q8pZ0j&EU^J zBB3KTm+K^pX8d;?R{6*kDD9ccd{Mq}!*2v3j97xu#zspAe3wKB!EHze z&@NUZPopRs640@B=U1-#zJ(R_$7hW0)yK4NIx>t^KSF>OKc^dPI9+_mqJYSGE+(|= zxw3V=+e>{0te>NN@JNZqZ4%w?b3-qI#+3i9J3sB2kxeTJM-e=3$ARS7t5Wl6_2mN* z18x712LBH64khieNdYw96Cz#dw>;l^vHnMs`HGeID>@Q4#-ICoR4@@N6p!vytB!*G+(-eXcE{bkzv{zjn=>AmJN2e9$ z2a5FnzUT(&b{3&tx9_?_0W~+Z*(5X861!1+z|GVD&p0X#*wGxEYen9?fZ4 zPu1c*AN`Q5-~OdyjKj%O7V%l4=YU8!d}{3FJbgRnomD%H}rXXhDO zuhUWZ$ziu=Vm?*FCCFhxwAp7557@{Lk9Hsaih6y&f5k5l-yTGETFaRPau$`8cKhd zzp-9X_w$^4Z6nedebu9joA~0Js8t^*Mxw9fgUPcdt*F8s$I-&wU-axiHPAG}ww^j(=38lpTnl*3M z#hv!pNUvRFOEcv90`z!Ser4V?=BaRz=mtNX6bW@-k0Av(HM|PB;09FAaTwh8CfXZK ze&=o@0H8&20hP7Jd{$CVt!$GgI7KGYKl9RDKbrt5o9)R^;&9LDB{WI1>2h;+L(17> zq68Y^N~9*0-%_r9!z{JeD)N1UW}UKx@m!6iT$4MNA#1LwKQkm-5*dy&&R{?}( zK`z3Ysth*?-dT8F8(%$Vls=UsY%ZPh;=Gk2L*m%<2t=|W-PJFx71{c!Y4GrAeUCq( z%WtQV4dt9oeWI~={u!80r7yW#P_NI*Gc74TYyIL3t5Bx4g{#N+B{q!>WNQvz6#zT z3`DuHKUfwdM^`L)G&UH~&FdmV`(8h+8~wEM`{p}m1_94qAiwT7ju`u`pKk>FCyG>O zI@@f%aNbc7tk8d#zeUT$CwJ&cxyIK(Y~u-qv*!spO_>}|;(kgJOkT}?>u6)!9jfJ~)Wr%6ZWohC{EaC?Fup3wSwy(2t0`A9E@M&59IF2&- zGFV8qxf3Jo1ULlW5njkJGfWCznviI!aqgXc=Gk6bU$bbnr4m!;98gwPQ0z`J@!0js zQpyGNbgi;#AG|Vog=s+|&io>mbdy$zg;8A`WPyNiTg#cIyvrE5pc0Q<<9Gh4yGhG7 zBTy>#9H^Cc38$;8J9dl`qYnMnH`soVmfq94vEwL*2}tYm z85j7#YQLgS1A0{~^1$CShAlKD{0v^uv;R8(lQcK={qa+M?qd_azV}ZHEG=egl>ei7 zGzytJofCk>vGEdZ_eqWe7G5qC+kjT&oC#Ym@|lCO>uDZ^k?e)*5#JJaAf`>m!v;XO z%Nm_u>nw>`&-x1mi-!P+?Cs?I15;k(-3vlKNs+9&!m}80tto*n+F-E_i5GJeQOEp0 z{Vi={JI1zO)CX+-qtPOd5tqkZHG@`JybZm4O-_v(Bam{ANh>XOeA=neh^r1#U>18= z_46kh7FurAm4vO-N$hiq9(I0(8*y1c^(3((ILMYie_eWCQn{{oY=O-RN!CH!&^pf# z+CuntePq=acKpUe*`ht?B`X-ptu6^a)sM2(ce=9taOBv1cQ9V>om;J6LMg)QRqgF8 z{YdM1IX$aF^>LrLxw#;l5u#VSWb9jiCh;hVQ-9oJMv*Hl(~%a@_iLzIRI}h5|6q$5 zi*;G+?*|S5TAkMZ9Of!8bVRvBmrfGc#rWak7BTIWOYR#&U(*Q6NBEoy6DQG(dV`CT zU&gcTs_Udp)jb90YnlVIUg*&vi{zS zPet0M97DQ%`VL5L*sm#)W`m*TDRH(C7=Kq7v}Dg47)80;Q#!)J1uz%p;{s(epKJQ{ z_iyEn1E83H>ecOsbKR%*omr_&y8I3c*-?*Ck7(^KTz~h4E`1>PaH{=rBiD}Q1V*bA zT2sA)rV7u9=4$88?@k)3x-;!QJIaa(}r9?ag>U5vm zCdQ2O%5eJEmy}+!W#NWA%Xaj{r!S3D@=Ee+l@cVK$>9o};@=Xh7gbZ~CfnY(xEIIl zcjvl{W|Z44R&%4#T>NTtNe4xyhV&XApV47~Fl+Knkr}upzDoVpnC7IZA%r>D_Qdyb z2AXuQ{-Tfdp~vyEG^S&w*>l1P_Gu+Vkgwj{eb@PC$-abdS!+B7@_9S-{f5z`q<6`i zmnhF{jCPaWfW(3JO_nj?TOG;I45#3VPHW-DC&p6?CesmN-c0k$gBMnYPxP0*^Fl@= zl&xy3|MFKh3#jay&HPQ*9!tNOE)FktzM%J&N8|7Fg{|>QlJTc-3BJ!uttKoUr|vP6 z%Q`$m-zi<8vx_)%Je(7Wyk4`H?W9otDt&?MJNjtaY0A{(uct6!pE+svxS$N0mAh>Z z*Ch$mViEE&(-)Jt@LMoZrw_-yT~V_U%0ET9L$9Hco>Mi^gg7um|amEgWLAc|(ya zGpt?UKS|i0(@Mi=)$Ew4-i^7P;k%%g7W z^Z&%t{6jQvoJJ2pM~BMxO^D%rKCxJUjpVPr8J>0L#we@;kNkUGjC38 zlsuCF`-W`=|I79dmc4RsMfy%P(3tHJh)@9g^Zz%}ywES_^O zrk>7tN8}y^Zea`8s%5~V$%q5@Y>uU$11-bm*rsOji}=&KM}PZhf)F>*6J>>tGq zMu#Njb)n9}^cN%k<>X=g>|WTGRq=V?96q=1QbRSc;VDB`q ze^p4lqc2%&k|#^I$TuHl7BhQn!nU}0XVTm0@R?cW3BQ7{5>HjJ<6%urt?MKO#IHxS z|Js;6@=bjw5BsH+(^3CMU~URcYgpLL-(XC52xz0!ui(;ox_iu~`{~~~oKxE+b;Vwb zxACw}##8f79fH;5Znkj?30#Y1iQ?$vMyBzOLadFr># z8alExCe$NXo*gRI*Z?{dr{u{ z`6RGiePkqa`IGB1&(t2bj0fMVty`@p8IuLhKu&GwZ#CR--A|nkiC^t#nqiPp4XPw` z+LCXa&F^~WR-(ZSzalPRrq!o3V{UlNq&q@cz-)d|GvsBq;{wdt=eLzZ4{x%4=z;jH zN&8!Y1>l#h>52~^ubI6W_ZVx7SZ?7h+wyusJDU!+{)jX;wa4k4FwUj@o5@pdt}L2% z3m4YGa7t&&%f8`BK6|H4<5#af8ZRHj^}~6p^j}Sxa=^gzr#&M#HtxpVj&8-+oo+QiLn=n?79GkKtPw6rc7o zWv4&%hQU{4HB-gsNCb8^If9~;qp&pmjTbhcL9Wu)(qXs(WI0ymzIoK{vPkFTEB9S# z%Q$LdlktYz^}R{zjd1oJNs)=dAV!+2ssY>L%Ct*jpuXJAI&*lbfJyn9m6Ji^I{W)E z@XHU}Ql&p>$L@tAHCGwi`@4IT-F5a!`-WUUDU6d~qA6**bHiS}}oI#&^FS z{*`XHPcPeQ{(aT5PqF>E71!;=D^avSCYA~A^&L{+`(D;tDaIk+4qSeB!7`paid(GGe4yd%rp{ zM3128Wg4P?cG~8nbi`LZTP$2}YhBR4XX5A)(?6y2PQKw+f$oTNdU`(Tq+>%YDwpPr z+xGkmT&9d%w{|IW)mEBgXXP@L^_v}HCU zWhGqmyt9iB?%70+USmrT6vXWjb%B@=^!8uAYCy2oP6}ACZ=G2rL>#;&x4>pX1;G5-8g16>Ot1$~dck zBTQJNWSi!n8!y_?<9B7^CoN7x7V8DnabOp4eae-y#G1F|W!5-%@2f#egY){AC1>IM z0kt;nDoJ;;P=X|ZfrS7iN?de4%ts~T5XOWuacIUnD4&=33k3cQw#Cc88-&EJr{I*q zwrtIb`jVyeA{_5b%pJsMfOz4ZJ`fw&S)wKcD%^NpM*8#UJK?1%yM$Z$ot1)M!K&39 zH*z)}%d5S%&qmJH>md2oH1L#l zgM*GurZAeMiyGI1Z3(E()vB6@JzqauB{%Bl8oI?ynikMzL50nR{$A=*BU_%S1*_u4 zzOm7JQhCQI;@Oa8@~2C?b?GWsx}$@v2bFLuai9Vl z^e%|lDSW_b*=7|xRJm^S1wrfc&*G$qEdjxenSBM8X56kt2U^rr>Z@gqu{2$Yg>=4; zxXPiVq%J;56(T$1%Ol*TDe45!TgYYq@E?_>J69L9YRI7^0DDF8zN77+WfJ{UOUmcN zt1*@Xap9Sx*#sD9?JqWF|If?D9JqQ3llF)2rI)OYUn{<3{X2fw>jxwOgl^v%yA-vS zEGvC=vqqjV=urISQm$@;{oWSN1g92u-1mavbCA8IdaM%?$r1JsBqxtVy_ce>HLB-T53 zm3-32g?=4eZqccUXs?`k1{*&EhrI`JRR4vBB79ryuZ2*qV>nJ54b>` zYplpvK*Uq^L{j7C($8+vJzG7!V5#h&oL^OJYHM`j_o`9SumBc}xC9@3%HH;|Gwh%K zu7EMGh~oyTd2Wg9Xh|$7@;pjsdQ+C{soMiK?G2IVR)nb=Q7vQYS~NSVrE$%F;3_qcLa( zu}zjs?@#kk409&&aFdd)@4vOPO`EqSqJTD!#`cXUIQ=?wU~TU0`j`&vngZf&0!5On z0A}GI;L|dQ<1vA~GvQ@;$2N_%RXVIz!${YTUPLmYn5LYS)8Q>)jH#KXiqC{)k7 z)Y|B0`uxD1PI=U9KJbP5gW7zA-hEWa72wE*7zQBKCJ>vQiCDKdFae!e4kQ-Kvv?u_ zcG^~1Z7PSqsBVd&i-sWGv{{j*ugXgQq#Pr^Bv z9A65DH%`8^cY8o=N?48IL-sDr>+Y2HIc7OPCjVws*~ydQYMGN#tSf5|~ z;w$@Ltdu6?$Lwmy;IF&Bh<{Hz4$HP?cjcO1MZbA|*=3PI@O`&5tJT4d6JN!$C@M{FnbZ*M$>G=;QTab!47q-!^gZS3>3hz#yyS!+9I*p|? zApg1k{Cu!wY2(F)yo>DsdUIyyvK0MdXI9%8;`TaSQ>oT={=zrrq%YNlmqU+N+!AoR z@u|;RY~z_027h1WzK$rEoX~QjkoB&F;}JNO&2haCQT!YI z{&g>FrL5rXxO2)&OJSI>ZL!C@g%F(aM|zdASn=Jn8=ZuA|IyGm)Z3+YzOkLPc*vk= z~Jc1 zJ*0nh0Ge&6+vgCse;D%GUUKM%>gN=T2o216J;cM44L8v1ctuSU^v1G#4#GmE-CSWP zZOc8KJ=n2no7%|5<4@S7EEL>~64t-aB#}(cGm##%=RmLo&ah{8nR^LhHX4JxFU0Y?!V#H!d-nLr~Y{|;sRm_ zuqwp~D2viJW#|Zl* zePLk+-ns|G5saWrM&GIEyGWSj*HD+*<~m!tLv6Rvs$&KX2*(-Ckw zHD~t~#vz-;-aw!N*PBvfRW`cs`X>UpP+Y{J&av1o&Mg&Lr9|Thg$W31N^g!8VcF~S z@a^C!Q~wJ3B&tqcIthpU<~?uNU3dxU4#F|%Vu&Yw5WvpV4@2Pb!{+ApPW}b=zeY|P ze!(;hM-yVc4s6(Eoe3u^M6CH%^xjlHzZcHMgE0gcRUn8f_GRAF_W#Aho`RD7^(B*Q zX7d!vN^6Gd#X>2qFKBSq>cNaY(A;I_x!**SBn%xvU5W*bWK**)5AM+W60>c~#NT#w z7M(9S`N;hCAu_nOFJxJkRr!>S5ZlWDB(Q^n2MCu^OQ0a2_&GSX7sxV`|FV;!<84Z0HwhZB$cqTiQ@o{5!!Mp*a)UgO&z49m-X+OsB0VO`qiE zu)@;+*NH}xi=P1~eboSp_dH*NZ3{_!q9^Z(yu7o*4GyWDav)vI58QnT4u=>$IvDvE z15Wz=h*g*#wg~|@?_b^m%v=PD0gGc0NI`?oU|NoDZN)kemb8@Pjl2bW`oRdn9 zbEqU{4#{blQ9{lk6tSGi`7m=HhAGD!wwUAOeA*mln0 z&(NP>t((*vyYtf!Eskb6$58#<`?2p9f=^vBzIpsyNa@Zl1p$^Dq^hz_`7 zQ{&~%#jp9-5H%$p(ArAwpC;i@hMm<<7E}pd|@TV zquyJ9;JAvLn}Q4R=h%&|rAh4ZNj%}R{6MBXJRoG-E%}z&pWu7KF2S$Ud!4Sdv(a=T zdJ$*gw*eY9!kk=`P)Jjyesfv;>WR>6L^WPsf7{I%rJkhf{>U82rwnLNaQp@+G5?W) zo#PhGXI?v8gf+}{E<#w6T6Jz2LAD@Is%Gajeukx|B}PC7&u&wS*# z-2Q20*5Rjr2` z9FfawxE%Hgw41t9l3lCHv0on8zbq~dccU(H%6Vz>v?lX)^jT3Mv%uitt#jm%&N&gF zm)q$abDN6pHIL_?GWv>E5eFK%#c~(3?2=7Npb+x`EN}GupkkWD@i|p6wHz)iNs+i2PUR=-q z=qvFL;4MDu>Ot84Bu|$zF-zNaSvFSr44dxTe$BpRu}S+yfxE7&b|d( zoWqJYaDOmdjvm=^H!PoXK3pv?Ke`(_qDE6KrUCa#X)f(KsUdn%2&8k0&~V62Vxqy3 ze|AJ0GKf!%X$wErY9DTr6%s0Cx4n`ZF36eO3S^C&$|){|nT#Wo*r?n#IGQ4fhwexP{5WgxkVM`82uQe0hDVfyRr$((BIi`MSj(X=06Bls zB^V>A(YD@bpE{VmlSCX#AiTpBNmeO%Lb5ejeBLATG69lBIidq^YQ%FhjgN zO>YsTlh>YG?iiZVd1LI$8t#1sXZrnzoS?kCU)b4Kce`0UclI|lz3^SlmYY23>7UCl z>zsXcuijKTIs7NHj)P+rvFa=}%%Hi&)75Cq?^M8)J~w)>(cgJKt?;29Rwe(ZSzWNq zr_loU@`7q9DR6IsRAZB6xlg8RFCxLIwmqB7-WwJdto4nA1+_Me52hz942of=C|`Do z5{YDaS#j5d{74>w7rcYXw$9HS8mNJ>a4n$oSY+$E4pI*lxJq(ku00hNrDI7eaY}RCRD>CBnS2<3P&C%cHt)o`77d!v zkoPY?ty>0EgTjYe;^T(Ld!xUFnN50(E8;Ecn#P={8C^K~O;QnZv9sKEgXgWi4ec(~ zY~fzP7izGX&yD67(M+QOZfM+-6Fi>QlTw^IFh-Mo(Y>q_mtf%8!NvMgASXNTm;Vp5yg|Ydl*W0n<51Jw@#~ zn&gXeO+*g9b&^@x#vH3ZIDe`+`?OXXIUJ{abAYGWD_cw{*uTDS>6Jq7N2bYE?Zura zG*ccx@o{=Inm?*>OPp6&g)AS}3O=9ZvJh(h42X*4pRJ$-6^+x3LokD`UhxfY`>r%I zm{Nj=X;%X0&wsTrNyR!cB`=B>?Oa*^C#q>A^0(Exh9*k&Suo=^A#H6P6eYeMO{ZY= zMpnX*V7fr4UN*p3Y+N>bLrU@T=GZA5ICF5B{)Ck;G7tU2F0hSZ4YvuH2Bu?h{%#czH=c5~(= zRMgAw4o+*F2_lv_@jbDoMve237|}1?#Q~hQRPhfC+Sj#T{?Ztp+Bc%k`I5AW!kcGQ zdH%@R#0v_~^uRV2%@m)SbGArd_pa$MW=^GlG7A~rysv0{;sloYJEz^{^eJS*+C61f zpwWZzV9Swr5fmjX`O4+GfE$B2DeRA#ALE*K?E@yt7pg7y?)iMJ=eu`BSC058-qf3^ z4Qb>!{qd-DT@hx3ugpumYf;hzVXt-ls-{5m4W&P`#n-~Tv))ByXp`ld*VQP4@GSZW zU{r9(020izIIi@Q`8|1cBXsF~IRZ{>0+XIGLy}-|Z=m=AB~TzD%ULFDtN)%zg<)bzz`W#QOvFg?9AyW|<1rh32n6j4A#976)X5EBh<1b~LH2cGQnLEr{@E<=l?Ni< zwHYK_8^)g0$kA`t&VKusg!E0`uUf}a9#ZQ7tX`A|PwT7WNPJ}d%0#;$2y}fMW;7LI zZ+32JJpOI^=;d5~%>l#T7dA3!!4VV|l6CZfnSez#&_G^r=3jd>eWas&7~_$p_o<#yr)_g77054Ot@bR)Kmf-nc|HEf%A35(^8s<20n(ruDm!r zQ$A*Q?tzl~v7I>|vH->7YTg(rcBHqdhX`x4ONFEdP$+@2K|xGIO;hg!T}NQ!jC+@X z&BFKF31YS`mVfiK&q04Lok<+!*n~MxeV?mO%whVvZ_c^>@>kM=VVo;4o~(ShCW!x2 zLBxu0(WhNBFLu2*KlR6qyY^hdoKv;{CK|F#=K#)?Q|k|oROPBE6`ewp{vWi5N4qv* zT}bld#Hs^rV2(3{7Sd9oI%DVfTK&mM-N#x8%|b*B;6fMX{^J+wYBDZUsefYTEdH*I zKseKxfS6(V?1Mw+9{EM$rVMuD(qDCo^ZBOc_~rntz1ZMDj8izAldKwlARz6B&>fRI zSc6FyO!1CarL$EopLM-n=gmA4{Dhe-vbe*rL1!YLqhyqU$51gmZ$51QhSJKuia%zR z!t*VDP_y1Pr*UV{Su88v8z=}NZ8z4c%?kLQPNO*^^t>3QZ=Yve_8$r`N-~2b}+xlrvnk*sUGmc7Q4sVG5a@25V+x&^}V~C zhlonZ3Bw;PC72pjmbBY%LB4uiKjMb=Y#7BKKAS#zYG9|Wc=i@!MhY8)Gc;m8sW*(7 z`fj5eg{}_^-#6pXjW^|`U^}JN*;q}Om)K;ApZ8w;StUj_uaqY3EzWIKkR>^|)^m7B z!#z%yV2_hup8#R+8rq~|Z)WP7@lxs9UhC%6trvcCT(<>9zFPPH#~=V#he1xu0R}`% zkKIlJ?Ilp%cheX-6w=`V6LU?bq~MA(S=5BQX4@g#;VcrF9X6K^j}Khwl-rt1~8syRZbfKw+v!( zg;=~LP)eT`mamJjqeh5CN>ELS@&Zs3Z(hRM=w!l6Wl)Gg?5q_s=q!c3P&c~wzH};O zr8k?KhytoIEj997R2W!Y{vu7Lwe`bJ2SCSzapd(T6q_t9zCc}+W4PV1$W#I21h|pK z6xeApO&M?@oeR54MOn6|6YR(hZQ}Ug+H6Y38EJ>zJ0E0vP@HFfZ!_N?gjt?=(Eq~a z$a4uIK>8ZZxdQ6kajf#ydHe;*c9+o2Ab2Se^Ea4MX$Q5nNc9RtA53$U`T@3UG{gVs zo$aF3QsRb_Fg0tj7|Rg@7frPTimZN5iLLlb9+gDnyf-Km>cXd=?T!me4SL@%(n#bg z+7(vH2Wl}Hg3(eX3msrT(#{n_%P_~YEhI#zSu#;TR^(~o!jJa0&oScQt^D0b50CU~ zZQlmS^X9>>lMk_Iu4(xQm@JnOuGB}6^IoW)eD*M$@ipqr_3R=;tsmAKs++)4?raa$ zVd2!d8-AU-6aYXE+c`aj|50!Ezk^yaw{;RqR6+SefRV{E4R||%ZEZOI0#4gH%HS#R z0R%CL!UT%cIu;f~9EGbV{7U_^)y+uR_>aY;@wl=zz}w&+Yjc$~s_~|-QTL)IyL(b} z<&E*J8=n>c*{)T~cVQlhCm^=9kMW72`Y;-tZMXnFqzY#+(zr^ZnJUjB^JQ+i=7ae) zf8gK*H!u3|e+-WgcABl?8#1-BiyO)>xbX}>oAAp`E{ow4yGP?g-(GefWr`#v>yddE zZ#@crsAb_MJ|hJ5#<)2ywKPnCY@<9#bHoVY7~V8>z)5$ zPOIwUq{AX-`OvikstuVtpTv!>1);dh9j}A0#Hg`D4x)(xsVdRr2#W6q-VoM7_2(0t z@~noZ`C&KJ99rK=GaWu&IJW+W-traPgGpA`T|-5US&=QhMaBlQPBQk2)CbR2W zyuthwmVdl%c_<_kS4nsclFC-XC-UfEOY^;MVCZgKghU6fWXbFBxP1vgDInm z3W-SZey)vh^?&%~gtWd4N*UERti>HeW;P!icYUA68E?G?*nOX{oj;hpNBrg*x%B+W z2bHGq?Q2^R1SH(rCIwNSfiatW0+(?cm|TmvowN)oyLx4Js`Lo{=CeEYpxW;QAR@d4 z3*U%kQ++tH@8-E(Zvn2I@}XDv4It!)M^qryIGIeqVmzglT>!);YIkzm=g&RHOS_b~ z3m942jLQ7Xd;i(E|KeVoV)v}zxH5}Zrd2a(C^et38UQZ%PTrA?YjX1mXnJNcE(G5| zUyqiOf#lVXwle3hK7r;?_MVcXKk>^W*HRo!73xO$8g-WDuQS~z*5;?`*OLs2eTny~ zkOMAe<*WMAJOx4J{7!?l6)c z@OT}xv34CxAd&AI$jmXVI=+;IK&z%0IgmM*U+km-d|tzKv}R|2pHx&>w80&u`nENB z2ye}TeljjgIG2_jBoORZJ|l}{EMHs81FLBcqz(;3iu94w3vXX%J{)2wJ09oviukGj zbNx?3NKZo#Xj296DVg*t(Rg>a`;0z=MQbyv6~}9vfvNJ&n{_vPd1mG;{ZEu$ZzrF} z;u0YzL!_4p)WtUIUrN6KH=(&@cFx8m*WM~`POU$?0R}Cn~I@T-NF8ChvBm#KSfa3n3@{K@Tjv`s5IDd^lv_+|*(%CelnSENoqx+!2S3-)m<3t7`_y$GT)}BGLUd`v+=S~I$kA(QBcN!kHB~I)pxW_y#w>Gc3eh| zU|fSDwMV}`?xCQ{ruud_0?*6Olo#aOeXGr{41L|!T1R$^oqO^pI=gi0Z$%3xchdga z&;&EJ@%r8a!Ni&ph?Zze^_bts#yEWxK;bg4v#DsSXbpLw{z>rr!C(M?>Y5f)ROsyx z?=5)&{dbw!MY%!*ZWgv++v!SkHP74(pqj44iD53aJ;h04d&zph2{{8>AG5H+-7HC_Xu{Avi$-xzH{u!1Rn)?_tt z`2~~Eteza%&^xB3>%uU*&^*y!4?S|Qg|7hZ>sM<#{7W3dK08dQzL{qp)FyHVD|vs*8CcLFvXBo1cVh?;>q$O%zXA<1p! zxW{7>Nxxb-%LLDy8VMiNm9FB2uWAXzS-ws+8Mo7P@s_DD{C34Wg-b=#=exBmF^LO| zdNURBd_rSY?&6yD0D`RaP=3Pj(UbGI7U9h1k9NYvm4?M`0kv7iTd8splbTLQ$!ffX z4!b^v5>p0YqyxVj)buI zBWp8XVg*FE9!TC9so3)N&kB@r$?`Av;R?8^jlo`F99ZKQfc^xeoIt^$Gq(9J;KQBb zE#6J7J!1l{Oe-t2*rwn6$LijCrt{2It>*;&{n&TIjk^pRN$%SRW_DOxQgO5k|HEMY zejDQ}31Ehquv*1QoxKzbTwnq48cbTB4suv_j=;$R%GON9HoG;uGq_C_{b-1C$qmP(Wo$m(4A>j zR=lh6?ep|ij8K{r=WNWs_qdibxo*cCN4zM<682)8N4{wf{6 zNBpfk=+&`10Icqrbb?V_wia%5HdKFHVkx1EQHj3p&f-WPz2^0KnEku+9)Ru{YO>zG z#{Pw>bg$L&&2f925@};3yGp>}YvH$08~;Iu=drTdW=)OJJ;54eQy1R;vx+y!=D!=9%q4Ylx{x?7I*HT6;W4MMK=M@8# zzxmvTsCv6rtpfvns|K@lRKxF)wY!Ta^KbVVmsueBQ}z}37(c?!=CAYpA!#2o^u|yo zwFBwad}H1&NspTD$4m~Sga^AoOrMPJ6iOMPaX;E(XKF4{?!?G!U(iq#Ce$E$5g`(b z;4G(yNUH=Np8OYqO~U1EB}`Hl-)sza`}~+xA<#D=Ckb$Vc-YhnN1lecoV^6}xEjjz#>LSWMPGsoRQn z#|fF{TpH#b7ks{3Ex#`ZXFf}7N7))#{US6{Dp)i!ZN`};-ePisBb;>UL$@o41fjo7 zgX?Nima*=j;8S+gJ&wnz-Y!f zWt-t{4FVzG==^dcljD_E+F!JltGIL-5)yX+R6i;A;qLyjpM^`#F@cIiQR z1&u$yWAsu;ENZ{emVV#io28}k@I~Gut2b|q4Bs#uXuN4Jp@yD_Qum0<38AG_-4lb_ z#?gJ>3VXA%ehMp3{3W94hri~f=i6P3Z#+`{O@O~@s`{%vX=*P zo2k|%orP}yUN`hhZXJyreZAP^r#UFppY%YZhmz1L0>jZp}_14CkCRlp(2Yh-t%zo z7z~)bO=6Cu-=O(Y#}+HZ7MY`H#`6iy503#Apmh%=83YC5o6gMWPW6oinYA^y_<4-_ z#J7w472&Y|99xK0Q>OD#xg}Ip;!1Q>wGs$FR=NGTveaY#Wqz{UV&6+~vn%<5*G=x4 zxlutq!mQNj!WoCZRD@CeIG+<;++*QD1+I59N$lQM0`{-e`rrvj6 z7Q4Thv0LwlaJ76t)4?<(EwEtTD<3;|0hxx=;)k|aHdMRr`pYs|)Q9YFc${5O_>9@z zak8LFz&N!d#Ym_ae?E&R&8$mv9dj<@+}CC@yuUD6A-x%(0tWG6UD{xG*EE&N3duqW z{#$eq!;vD@vLL;0b$ZnUh&KVu+B&V#kEksRE%Iz;A(v|#(?Kr*_)3bwbc5mcuZ>N+ zR%Z}NI14~3BupG)vQ5+-*a@mJKlk9T^F&*%mnwLXQpvq6y>G+j-szpu$v+Cj1V%mlcUHGT#N}K^6}4JV2Bu=7ATTl(T)qd zLg%8sn&8=cI_jyM;5c8{%Bv7#H}MHr!4(G|%TvT#JOhcvT@Kd9WS4}AdNp!jW3`sy zmkSy~b9U^vYid1?vH%oK4W&*h4v=Sjz!K#nH2A8hgvG;Hn)dt*2R1luuoW&g{%=Cw z+j*>_Fp7mo^`+d|lzHKM>*smOP9&gs1FA&@%@t5BEKq4|q!a6C%zq5LO3Q63v!bLW zf;;EhSdS1|Rv~67@v+LbEwc#)0c<}7;k=kCdp9)K0U*eBo0SKY!A~GS$e&*vng!5n zdmfCwNx6a|tYDW&fk91She3m|!(93tzgO`*ddi~HiC2qrqy26ihNc|2Kq#4SN>SfZ z+tscI;Bn|d*HTQ55QnRvm)`GWCuf)sb%{i_0RUJOUb`k`ysb0 zxk7ANP6&*wv$KBZ0jN9Q}rI4uY3kOdNAG?gDg#~_?2@?t4 zn*^x(jf!6t#3HJ{^v6?}s~!Uqa0#f`Q)=MLqFE?X)-~F)T}9>XTHtJm;XQ}nwGGp9 z3*WiNcIn`8;NhUTM0`2Nn5~^PnZLk zk)vN}1Eca!X8!Y`TI9(b)3Q1rv0U}<%~9fk+Ys{3{7wW?JHC16ladpgsWU`_-)91~ z&h7a=pLv_IQoQ0+8g^dm>}p24aD5%w*WE6sH2)>Ts4}QR(d^oB$P?z7%hdMYF8~6I zxK!!xiWuo$RUoy$49v1%KAFz)FLNCI9%k&itnaFP;$_-zb-mmjM8(=s8{xxnCZo}i zY{0ctV>ZAB99%=yXTP6$!20%wv)GRv$DFJ%oeTuL#ZAG1Vb9~J zDnIGueaNYF-zd4L(Rf<#%1#Wc{y<&Bz2`#b{J{Yfu+S2EYIZ9uxV%-l9fR;0;iOKHO=hs-r{=bxN0!Dq@QbZfb+#Ly(l>~A~j zg%0%tQ{fB&^tQ>j-@||UnC|Bhwj8-swcYCK$7!|CHv{Vl@5|IY}y_E?6%H;EfC97izz8zCY8ozK$ z{#?VP(%KhV!x+lOD<8OIuRD@G?;NiqJ^6i=tApzM*JeX`c3pNSC6nHJL(#i~STjVz zLmZGY{37!CiBC7_hjCobLMwLEpFN%O7d zts8ItZWpgu9Vyx}zPh$uUxa)8v7V=0G!g%}6&=0>LEow^yD0*_C7v+D4tb_t!q_yn zjSj4?e`|kBU7~M3b*g5o()HwOMZtguq5qewKKz-^wZ1bAuaOOCu(Loe1fuB>ztR>^_pxmQ`)V_jf1IViP zN}aQh=L_ohh}m$_3qO{sUjg6tBkj1+B7^Ji#W>}{{21@`=<)r2FVFe@q#AmC44(t~ z_Wl$J(xN)@b%ZkcUrLA5XMChKZd#T-{BgT8mtf1ESUg z6ZzSSG^K2tu3fgjbPn}>dlt)hP_?ViQWDL>BYmxuC$kj~zja!-U8z7><#ZHsy1DSX} z#3zymT!DnkCo6X3aGsy*apE0H0E8dfd<4O*ToNicTts>cdv-;r%#gSeGe_iz)(|Ly zP*jdHdWG1@o=Q$JHAc?3s!iEskU0u{?Q{dA@P#FYy>Fcr)}*no2x%^=DjgcVPgZmf zo65w;r}Z@^lT>ecwIWt@;`3c|r`D$Y_+?M=k*%_R{vr8gN3+`GeQZdtr-9u)LTmJA zh7)95NckX9eNYdR$**5bl^ms*CfMBdN`0F1A~(%`*Z%9FdTQrAY?bkXDdHl{3QxaA zVLm~)QJyvPxz|wLD`mZESTc{`*0LE1b>>I7i8Xte@=wRD$7b^N-{FP;*>S*=yW3P z_tZepR2pIC)^22N2uYxZPZPkiM7G}7P?0ZL2gChOLFQlWI=yc-HjoNbHevlBTg}&k z{qpwz0!o?uARH6A8~Q&jqQ4ML*l0Hb`&S4eP)5@>QO(TAz_} zFJ!8qouA(o}tT?(J%6cg*OdN*nLY$15co?7{EAIQ(AD0LshUT_VDiq-tD|Z zw(tGrUGVqP8|iBjkDSXZkJju9m*Yw{9K|PaSStY7w?L4N^CzpI^W9Uj7D}ZJ*rSV$ zN2X2q&ZZ=#D9?Y#<<#PHlv{8b@`W=qQ9+27w0d+TAfcj?FfxCx)2=NX_nJRepAVW&8=AEKg9Shswq0CT= zW#bQa!a`26YA>I8H0-*(#x0VX(3$@j9!w~W1x$J5+)l@yO738$08OV+ey_JYR`JX2 zyKH_U^{yCnEYPHew~8(dPhz`O;0zP3Qs82_PfF?%YTi+mc9uCTc&U#HWqLLD`(Gba z*^$bizPh7ZTl@E4)mD!wh1`?X&;+a5SElEm@{`K5Cv>J31+w5and5Dq(p^?43I90t zjcjXk9-KTR7)PNbcgkl``X}G%>Uay=4EY=eTv`s-v>>XqC5buZNiu!8sy>F|YDf7r`lr`xZ4>>SKIjhAfiq74X(aq13M!X3! zZzP8h5cPJ{R8TmK4nqAZTG10yQ{{uzU_gFfTlUF{+)4es3?+8^u)wL z{dX?w9p;YBC#!&`-gY)8TTU9e_k{G{6vxBGpc&7{Vaf~Hice8w`6vyxpNv5jh5;*^ zBalOi>#0{&@Q=_4BN2((=9Zg3*k+u%bNETyRsS)t@^<5yS{M ztc4l9hhrSv_MJ=7V=(0x;-Xx4MV@@K4s^h(cKJ?$frFYuO8^>S)f}xK3sj+VoUOjO zzr}07cgl#;rNa|6>`H{3C@qBlzHtYFhgR0{66jp6W;Z8>Q2aWfHQlNx=pniX^Kd)Vo~slmK>6Ocl)-@wI6IgF&?801a= ztk8E02gBFw>wRXZUd!tqVV(wLtavjb4yp8sAP!m9FA_@^FsiE1c11^PGq-Yk7eFIy z!!Ec1{dGNvFvE*!*rOJibJZier-<4l8ix}i&74?~b+t}h_$I|pbd zZ!{w2wId|W>+RiZ&@|=qIoo9t2YsK6L`VMVC+oiaP}6yhSRx;b_SUp`I{LVf1X&=u zyi+(auYP$14Lq{m(2n(>3(ZiU+X2D?F!Scr;bc@&Oc)oG=B1F zZZ@KKjJi@rNZ`=?A!^7Xv>{&+n?aiS)gk*!P`H&m2t{|Rj`7-tmtF3?hZPE2oFO|F zp0Ly;Q3j}Q43@avgk>TF6AIH>l}mk&FOs!CNw+v6pRi0P-(zb2Dsmph^amL72vq>h zoODtu*LvO0TmJyBx5K>kP9_z-F!wRT>JPAmT?5#|It<_lE1c|u2`nt;wCw1B%H&Vc zP5@#9Dj7vHdRaLfM?r%;+T``)RQkmbo}`~ZT1@D9_8EEL$2@R+FgUXFK%_cHn2IJz zKN`CcVNZQeTE^HJxb6}0_4|$JfKC^wEg@^ZdFSP-2cxt=QW(*{ve0=!n|DoEv}r_Z zu++Xk4oP_rd+!1p!0s_h{0G{dAUZ zko+|*A?o1|1qX#$2NsRNAFi*4x=+H&l^73)<9g#ON7oUOO1?KU5DL~OJ`UlLu<(ZQT#`G-I(#zZ}fIFaycGY_aJn{h^qm>dsN zEXmdhKd3b&;C4<@dV^t&&Qp`{{hEKz*nUH=LZA4F^?~}yl?`DL(oXN(|8gVIQ8>aAs-9>{(Aa>S%u3B$ zg&acX6-EkZ9f92H+}$6(1Y`G{ll#0vJdAZ=nhxvEs|{P=J+0mU{2IXiue(orzHp!8 zq`3zi-aFAk3`wuKwTsj4w!4hx;%)t(b^N@roxwB$zgksFtulT8_}gjIPgTm#rH-*m zA4yGG1OgYX|AWf3Z?4QIhJ6?{F1Klw3>B~-M}9+s8E!oFlCrrb2Q_%)+bg~L^k--21wa-Z z6Gw2Dt_H0KEBBTPr!c?xFvo;mvFqBvkgg{X?4hsLV-^NYe~V4RhhrIzBA${~dQB5d zhGYeZyj}ffTJ&W$tzQR?Fxv|IX~p=UqGch2dnW0Z&M;iuT5eV#p%!J1ACMAr7rmpc zj!~4h*{X6tc5dFyt7cR`m|K4$y!A9J?4ar;eRAad&&*GM4$yaHE})6u$E(v9!~5w8 zSaG`lcv#oV0;Q;z&P44jx}8?!&nU6@Gw|UY%x;+l*qwP8Gmq`Ay0U)UUXxF4=`b#E zKW>|&7*DjS5?%gd_`~0NC+r_T&Fi$KT>!e$rF}&M%}LWIZ8s?ocg$V2B|x1qcJK=D z2l86yaypShUqXng{3KWZix`qVw6-D-B+FF~%cM`4RGLqDRL)<2KL^vxL05zU!zN_m zN}|?v8f=_qcCJ1ZYPYkX{Yi-s5(i3esj0VYkmr|KGH}Vp8N6fYWKImXcNt)wfAkLQ z0}ZA~C4Y<~>hjt4bB1eoq3twG7hC40*0GpokuEgn%fYVUSj zq&ZJKA*=@@%XpqQjOSR-=af$q+kxZxLnuv5|m+!{=sV z7;_gNR_tlI0qbz+Egx}(Zr0oR{(z5Gq{*pvj>avuAc8SE@D`%Eka20H)92=j?I2oW z^`o6GLMkA8*Q$zOk)An`&Usl8jFt%XDRJ%s2F9p>;i@L6}sbg#p{s$H$r&=yz9~(TJiwZy}CGj zZw1~DgpWiiy}RS@8L*&4gcr;Tj+{mCz;8lZh@RyE!RVNMmK1@A+XY%;4&dj<@jC3< z#|P%~RhvkXYp<4k4NmJ0&4N^z6L-Z4oND02sqb~1rNGenPH61f{QFdzQpzki6vLjujFK(h(Pm+<7%$aN~dAZ$cSjCO*^6bj2y4k!6iyQ%QyV* zU%M#I#@CnP!$YGBFp-rG=+j} zN7k0)OS(=u3(i5R&S4kr6G6-sp-tpE`bDu51(-?;3EgGRK&`|Qcai`n)s}QevqMI> zJkN;%sb}!?6#1Q(cPgc<>%)C1`;uQr*MwT1Fe9m>D~7ms*7as?_bJ23bBWPEp{}+Q zNZ6X4L2@8Z<>5uPxsi*<91CCU%+SCN4=`Pzk;sQm_YdH)Xt06LcOX@6=>ZL*O&LD@ z1k*XW4C+0ZXMk384ozg1fPw%FaG^J<2!|pDmkh? zT(oA)M{1|CUftMuc&PkmEM{Ymzc-+5z97;kAS#6-~o(4fEx=^4S-{wQhzO; zN}2UpQ-c=n`nyUouQYBrvd>+HUx$Jye$;xuBw?6=ITsXSNoK2z2`z%=5xeFvINVf3 zoYB@li%*=aT!j(-m0+(93L>6F%`l)MNVmPYJ3}CqVO@|4os#}ity4$vM;dAvFeLBC`D=HTqG~eBk@VN1WOp zm5v%$?js}76~40)6G|Hvp-S$8O50h6dL80ni*pqWK6?;ryPF{(&*5`Zo3=W?9)5X2 zwtpuEI<0zY$q1WM>G~IMGTKA4-9Q8*<%&M1HGT;~;Rmx=nff?;gU3;0U3<2DjPVb1 z@#d?A%bijOKb}o~)skogx2gv%^E77q2+d4B092b?amYXw?zV1fV#)>;<5IPS`_D%sE#r+~(Novl&($`H=kZ z3Sw57GN>P`QGFs9cKt8&?A32Rp_S|WsS=6VrGp`1FVDvmSD@0amYrpMH0w0?#QeTe zJJ%nj3Xu-@^)b0tOWBFG%CbueaxwgN!^&Mrv)R9O)B%|#u{r77dI-&$Ic9NGnNP;` zeZ7#{hRwKheeGC){PB?kR9v{X^(KsUWGAstu3}5$T<*HnVF3SdJPbkd3{vB#LQV*jxWz+>C7?Sq0|xM>!~=k z!8Ke)*jV0kYODVmn(^BE1bw|dP{gO_9Z=~fAT!L&Pq;D1S96l9+!geKd@6vHj9+P& z&-{t_82@Ya-cP<&+$`6qr-tGAtOCFdoZ;9!((|u5@`K?Oo;c<~(Y?A3vAjfNvZ9Q> zlC-QAg|2CLdZ3>uoqwtBrp5BZKCSJ=@4^S!d4FfAiuUy_Q5yy=nvLk~Q zX5xEkPP46mbZ0uY?~jruujz!8IVbhUI$a{wBu#k+ZgwxrlW*=GD2VXE+^lTym77{o zMQ+9@T#ztHn4#v`Dgh4;-i?MNzULMlDF*ivKsaCwY^L~(%$snasoI+YuKuMy7*+wY zzneF$#Uj`3Q_mlb5oR2rd22N(_w;m2*|;Hl`hn*R|N^852$@i=r_1P zXK-WEVpDxQA^BdZ>dc&ba4Ua#`eD07TRX^s>mk6s0FBR2gmF3nmh)pzV31c2io0Sx z@d__Ky8lgo|9)J#eo|XtyW~i#=6suKm+-l!iI;I*o(o^dLW4PxCCG-{fNhQ)QRqywm-ov7=V_#z$}R&A?oTOIusF>HBdogvf$ek>^K*@k3Bu3 z)B)Ta)U0ymw}ZA-;-S8o?zrwT?t+B4bBE=Ig9@UGTGl-^Tk7w!Af#(%Dz{PM|v$hB$Q`NLb zLBl(b@7z06zQMn5cS`6yEtSlX4Ug1Nc|@E#9Sjb$y{wFC;IAuoh0IH=9&$V1|~XjVXsKE{RMOB4|d$1!$_(vX||$j z5_5^43wt#x?F!@Q3$g1t>NyaeJrECF97Xm=MOX1~H&R`V>KgA%&zLsuT34?q_x_!B z&)O+ys7VBix9~_3iDEZwX`Ob@hjoS^xj@=og5q=f?@{Idi36vtq9CEhZ+5rJC10>S z-@N0-RFLwr0Gi3>-9uSzET z`M*ytcus%+e8q3=>G?KPeL7_8fy0pNQ`ryy$IyAlL;c5b{Gw1+D4Q#*e%YBBCzX{@ zvd<{{T=qKiMD_}y$jZ)2#@TyhZ^zkZ6Yk8zxqjdOJ^XR^z3=z?dB0xo=d&&iK9Hy? z<2&6?Q0iWMi2hK$d&yTdu~x%4M0JmfgN+TG404lBmFT`372T|6pi7yWFC0<#``4f4 zT+iZt4<)u&6I#r%Zlf>Te(jhE6FjmwKV@5SY zq}!|XPQGayp8r61jQ@dPHKi=*hL+r49O*TYdx0}*2Ac2NxVFg0gim6hEqshO4$%)g zef)WwJ-_@C@f9bYnf!7Q}PVn+}n4MqPp0**^paY`L(C>SfTqXBP)rM~)R} zmSQfjEzymcXGp^bZrN>?7&I(OgLcLMEWfZ~UbR+52WFYzO#Z*>=evAnz&ZaVLK05M6 zT7I728Gr>!v1#Y!+~0c&4u|m6guI%T;=O*^JNNx$7*XyZKU3%;VD5^>Nws3ta~$p7 z>RTF_*LQke)(r6U#K{DyQtr_DeL;qTRn9pj2usEMYx!?f>SfOn!w!6DVud5|d?g^) zVTawTud0o{E52#P@|3)`RPALq#cRR^1|R;>k4WbJ{_#q1s@0C5NyyT0B|dgm@D;1L zHw_j0+RF!xxzZG?@ViP|Hul%dcOrqcT}Sfm-sWUzhX-65&BYV)_vy&8YDy$LwtJO6 z5=&OT{U)~xiIYb!fol$ehRgD|F)0anCXKO^495Kj0MkUXJDj9CpxV~NY)1lI=rPCf z*9fa!?mluXVN$fZS|6u`DZl=u*A_Sa_TAb$B8c31lg5qoCjLaxK_-sP&5=*6P}=s7@Z$~Nf^nbB3PVq3<0kTkb1l_}NE!i8>=6wyd~(a2MCsum6F za5LZvar2(|2lCjExmvFts-`et`;xsH?9)5LgltzsIv~TBZt@VoxZ%q-X%oFba3Z}R zugaC%d%_L3jKiweFK$tc#izi=;e#yanP zv<$>n^N`ZS$hT&v-p|3m*s<)OHLk7;wj-Qz zz#1HwfppuSneZtkEvuv1xwFy;e(_X%aVwRe12>VKAgapRj?7>wjo)M zp^EYbAzF>CK~=LmGPfAdIoK9HtY$7irS^d4A*$01+P=i5K<#)pds65<{?1LupQ_pB zJV9dogi3W;aGR~Z3fi|9#m;iWKXh+U>z%g>^g5Muv+ zT!A6S0ukSXhXN1&pPg1VoWIX&y>L0OPO2;zhcEc$^*}%Mh?|{Gy)I&~H!gSM7nD3M z(ykH-Kpt>?f*`XRA9|{Ex7Efuiu+-8-4uyy2bdOkEM4<|H98c8c9isp+~3PiU4uj8 z7yV0Q-*tbsc7x;Fy`|G_?iu1*q3 z(8r%=c|RK}O;_2m-l)u6zD3L10GTF0(h>-6fv;Uep8mNGqUsUES9FOLk2#$vp^85* zsNdS_(LS=M0#hkCu9$&Wx@sHt^R4pD%maQb-Y+(#et(ni{m1r&@5ih8fvSX%PVW&b z?}A<{jvlnzWA(Bx?~EgOXW~>St)&%?R!9{A#XF}LCUU63JeS9Q=wn5XRy+@`cp_|_ z-Q#7~G2gw4HZT=I&s9u?(r!QrMfdf>Fhl_~i1hhMASr6h&@dva9so2si`1pt>^d}vg=3WP zRmM;I+O#&x;!E}VwLsqEii!9+-kv}fLh?#{xCt`YGuq7eOck%dWTEn5#@;fxXG3gr zCJ|II?0km+Sb#UpWb+vhRI10{g);RY?(GrVZ$D@xJ4iX`HUirOw#UR`Em$7c z<_%m0uNX7UCi%1C$jwp7O&)tvoZIl+HP!+c*&#Ia<@I{A9Wk9v#xNL=?hN6WMsvK@flWX3T z3Kyf4dB9at6W(56#?R54Nn@?eU;&M=DzrpY_*~_-JRwlG0T&lwlvi{%nEt@~3vUp; zO7)@KCIefmm9(8yOp{Rmu78%3?uHdCljVqv&7(xsbMq^&W2?3x2Eto331J8vbfEZB z0*>^zV&Q!B`2)m)R09fp=dXWN*1`@?v$oU08-|zjeL@xlgk9{sW!pn}7T!HCTwS_@ zaPO9z#B?XO*F~b&@1=lYK(XhvYLzbBk2?X&7u9oP*p25Cjc2d21%QTRb}BzHUVrXP z@paKJ`7LA0AEm7sY!C$A-0=8`S*sXdaxbsc@Jn*_Y+|$CCQ1Qq=2vXA{qsed>YgU4 zdJh}ON~FK-&Ym4$gEM(gT@d8xYq*9?72XLpx?Lm)aylWUCzHO zaODK_5#bqOEENB-#m#72GjHA~@%k_ILuIo3zA7&ZFF*1Y&~IXTUDu@6IFW~_DU(8p zOw?-TkqhB2S5qv`?G@|FGenv$VV=!*U$B=Ya-=T^@MBUb6OY=m7WQ!`=DF+GrrN&z zn%ZEv!Mo{jkw1ZcUO>gSZiM%;*%xnS=@46%C&SL+!_8m$MHBIhSX}yjjg^u}1n$e@ z+Rcb;+M;|r`zEs$Hm%sbNC^ja|Nk~>K02S2Cm;tjVNV#J4@=a6$i*C&56yL0>?JTd zv_#8;E(pghn-G=S6xjPOzt_GAQ9m6_q_Y%_|58jY@~6DgBP~2^3X6ZH%zrfl|k= zmCP%Xz%&m1+KeXsWu?2XN{WqkVH-Qrk3Sw_%o9lEuG5RVp~+A8z7BY7?@up52_ef{ zA0!8w*%|%ym-k*@{T}RA>JzGcoheZ1qO-3vFS`YDyL>2IeKV;$@H(^%+L?Ocor*=? zbjaFvg?<~}zSm?mGNZx&qaG|t$r((3o6hU3(;fDC#=+MUs55->w3EizmOWf@&zmn- z7>|&5=3-oilIqr=MsbIKaedV`q?Bu z(W6fX^47%=uTO#5-w(KG}eYG-qNN4vvsv06qh-@dnLnMh`v z(|%006JlA|5BXsI;RfQF;-k$_-LqGCx+-s1KX1PkEsM4>gx69hiY~uY>S4Ko^^{dA zTYr%!14H$}IV$LemTmq&(5Pc7^6VS1WvaNd(aFG2OHMH(-lOe%Yx0)&rt#uBkQWQsR@;m9ndtq?;a>C2U_C8hiTH(qc>_Dd>j` zJNCaYQV>@k6afLk>xl>}o|8bMxI*sgYvkf?8VXE}0QKC8c_mDL)mjR-Dc)%9lI}RL|*cc#Wu7_^P6)#0PT_ z&Fakl8kznVw^@Qxj;~+LOEs#sAS57=-m`lgeN$48yVo<{oCPU$EogFwOT}OR-S>ca z-}ibM#W&|9cdRn0;oVXoZ>Gs!>v}c`1kal|_Ol1oOpNKuzk1HU^ZiHGKKN~BsgFRA z++4I0bw!M178gRG(*QSIk-sEeSvc3{D=Ks>-)CvGFCw%i&i8X-PiuffM4ATm)RJM2 zpxU;uV0Wqg@CAy=RN59Ta_|`VYEWLEH&h{Cd-HXDu;W(H#-2GU$NINn-@@HVcPmx~ z1QoSUh#FY0tMlP+Idc+D%q5eFO3iTvK{5&wx#o*YT;AO}Hjv8o{fTjbe;_p+X{q%_ zi3cU+MmhnqRRZCgD)T4_Dd-VNgKnpEOh06SFH~RUn2%p5sa*C%H`_>-7^c24;+IR& zYEDi>=7qR+dA+W1p?^cP0OCM`XUc3%D^t@Mw?Gs*%toqm$u6g()ooZ}@s*Xwg2rkM z$P2=Ni+T49VTf{R2}Zc+uCLkdO>M_rV1<38*wAb z%~1JB-bC;nM78zEiZ$wssT!l&nRUZAu2obt;TnxY<4!|tUvvk9M(&(xXMVH}10vX? zCw*nWm|Z&YE-*e#YOyu4++lNb;0SoMqruU(NZ$}P(D4hS0sxWjF$zysN|a9YeK?~` zZK{ubFDgT<1V7B)6orkNisXB*IA7lxw}*ggsb%6k_vFs@*fYi&Llp+pZQdW54tkv* z#W#3Alq$x{W8)(rbY}jF(l=d*Fz3*Rja?@Vo^Ew4ryzXop_o9(JZW4w6n$)?n3Wa%-0wbT5QgSRa# zihrP7TbD^$4_h}IgPwoA8jHAV_`Z$)DR&8fd}#FuJ0f_X^S{E8LaFA#z`Nro&`Q|7 zD9uv;TvzjW&R{cKl0|gI5Ab)Q3${+DgO55dRERwC&6bA(3s;Rlp%t2*_mFnm_pH_pc!H!Qi|wXz zEtm=MZ=1&VM4TK?0K(nwo0_T9FQetcL>)kooq~nAw9ckIi>-80wYiI4Y`5`GfVT(* zZ|tn9P2C8K{bBN9N^0+s<9nCi4Z$kt$P*C??YBBA7L8FySC5{Qy-V*72kvlq?+fO%`UFGL0E@rIK+D>bUYD^FX z1sx1elf)K0ZSo;rIzRt}%Z2?!pfsdo7@l&OC)*SlQOYH0FY?qK-5YHZUO{W=azXSt zmR^k2kRQER=DKKUm?vZ7ebTMtnyVD%=+WnxJ>hSLJz#=rIFlRq3B<3Iq{E*BwxDs< zjm}OlKCGI*M$vFy%tpO4?JJC9{%P8}f+wEdqK4TwB|djs=Z9KgLZ*iw$3IZLO|}t3 z%h6le%U2O<@+Ib%U9Xwk3+EQQO9`E3hf-zc2hd68xsEfL+y6j6pu2Lv0m$U26(XI>H6?wW z!tWT>8W`|~OWAp)mch)alU5eOqZIg;59sBP_W%6~wqSJV)vY<)FFRx!YQWzh#_6xC zH7$2p1NCU=Ayhce|xxv9k)?h@DKEi z;Auy}R~G;wQ%+oInoRWDzL{ctv)!!eihM|n%JZ`q{y4A2bfPN{n0iouXBgQE zODY6>+-IMTuhI-ZDPe!%QG!cx(#zmZwhhLs4rXCdmDx|uYgdNA(>f#{N* z24!ui5Q|Udjc`rnze9D z-Fe?jLnjwkv$@3j3W-aA-IB~7?;tn~{-S&WdG-AYQStOD>WyQoqv$M#&zR@Mv?p9o zLpDJfw_otH?4XTu+uRr*wmoMYsVTvsD1Z^N+uu_K52Bwk5h?EZdl1aam6fq|Mw{>J` z;k1?*wta_EyGx2Cb4lq1FqejXg)h+jVPr*3U=YEpr&D(do3h#wI!HuM6OaR8frUgs*gAE#5KrMOgiT<7u)z`?S~8|xSuUeF1yfz{I~Jir+hg2*lJB5 z=Q5AW5n9v#YAaJ<#%m7|_vi}qk>Z$xPGPTAgStZxXGW;z<37gud6rQAHCsuRfs^vjmQz|=r-Bf@tFVP`mI{cF7DO6Iwr9CQBI?CEG^cYCLayyf z50F>>9^VfXB)nYO;{(nsakb@@R&g3mh2uerl}Ky);Ld~`!k7O@{DkIJfj>k~5hT0M z)#pI6&+f|yj5}rjKw1!fM8;%*d$Aj&=BN`uo;P@gIc8PKU(4ro2nrkxWSiUjGloCc zo6cfaa-vSPsk%z@muc&lI@lA=iKGb76=sM~3I+N70};jlf!ZMMxRU2{vH4)=B=ud= zHo(6wgDTBhoFXc3F)bf_%B75*&{7bvU{YxLOC&<&B=jv-9xiP~}3_z|n%O#H!V!#C)nc77J zUMD^tJuaMHdW8#&f9ElzYT5ZrmEr60<+s~w+}+oHPHbn@{Ax`D(<78trgO76dK(;@i_eF5^#fwhd9E49GhMOMP|73VN8olw*Le1u;o zH)y;k}30>X-&G#m3WMpm5la2x)JT z!}oTI&bF>R2wBp=g%t*@3`t;9BNU7k#&%d3G}eaP=~7rk8LQRcK0)Hb6PzS@0KnhM z4v{0o>D(n8b){{_op^s8y3swq2M(`}N%~Yhgi9eMGv=jJ5PNW%I@|vAGWi(M(zSG)@ zTn9xyU`qFR?(6Dzz>PQX4>VI3IQI`!CDRSJh(T6~MjNiYXh=zHp}>QqnxHF6d$HtQ z2JY(U?Lx@6hurZ0suT6T@#()I-xq9RxRAKC2HK693TC*}E(}8MK{!c<=z|Xrx11zG zD;9lP=x`Z{(B7{Y4iy+{<&ljkCHeZW8d=K=LM1-jl-({$*fHz}v!aV;-VaqKSr+8B zKN7tV7=R((BjjHy6Q7NxjHorX)Yp60roT;b7U;iYE@P@myyes0e(;n_rgsFBei}rW za+Ty3!LRvxg}a<{Q{bqpO`htyl}Pl4SvJL@AAIhqw+L>n+ywrZ+87E3q|%cf(Ombl zr^@~9N-V&%1a~dn^&gq?>v4vO)`+vak>3B^QggUUyvkHs&cf(?I)*Q3_R498mkivb z&qKh~izk2;Q{Y=rR?$4jQ7re{qj$kcrvFeE*P*zKV&l;6b@9daL^6WL2I#v+( zL-HP$9&im^&ZRKX5GS*DV7CUw{tR$z8IVay3gV{!7ghcLQ8;wHeyX;`Fyhr^k z48?4aB^;B<_(TUrW$6?a0L?3pjQf06u zTttSzC_(dOV{J7U{tu*i1-Cf$9rwu4?7+O*zpT*|7GV?MBj#0G$u|Sqw(scI3TGX) zkhO9@@_Uj|h5 za&Ifit)={>3o&AUja&M=UHVXvy9Dph_p$v}ZE6}v%oTij1e2;sy}ZOuHS?ES5ijYW zF)WUFV{`g%c!-*#AE)qP|3IJJi+fSdJuT8#z(NF(7ktMteO-(Q zouYa>W4gVw7ATuXxmD3FsAvR~Evfb;OQ3A!e7J(IXx&}(4eeQvEvUG9(;vjLl+RM6 zU2U9CS&hcYT~r!jz#|C?%za}9?!QuD-yGx)Eomj(#8RZ6IuT%=r-l<7K!wOIZ(c(n zdsRE=&aW_qJjWg%68pMS;V)>c!J-d#a<99e?Tyvr{#!EN4*RbpNJAj^3sl7MSK+_x zOD{8x3&y35&G=MT-|#3UZP;$3kMnBKp}|tqWd+q|(ietFxw90PHeD6qk)uavn&M$9$&?SF@cuPT#LSBzi@xh_jzy9 zRsYU@wM6k~XA|C_M6neA^^~P9(cr#|y6o<`;bv-_`7VihDcqSXVh|!Y@!*E){GFEA zDvRv2AREp0$}h1>gXa;Jtee3B@S{eoY3ggjrgr^vQX#bVTjh+KDZnH4|XXWg}aS&jRyUlIxdRS36zGFeBtkjb7|&euUg7iBLEf(KIw_L2pqLM|GiuZW(kf&B2PzRIUDsQyUovyj65vp2_7okjSQ(T zESUO#%|}kjp8ui#bo@XPXub3V;b9Hdi>#G+=2jXP3pk410nUU`4Ybv>M0!_ylNChuRjl0ju8*>=(SE-A=V!`_fi-1C zTPd0305PoThR>>|{&Z$LQLS7$fn3?HNJAV1tvYdQR^K*NEXcjX&56I!q{Ut4;mP5D z{=3(P=9;>7g8KRw@3&96_CkCvz;Pl{{1d`8#ZpxFM)%7LU_7x4=l0p}?*67XpNhrC zk~nHf9dWZ#T2_NVm{)7MkaZvRaK8BVxzQzevITTpsu`(S*@#z)akQI0ktYa@HL=;h zuN-q+4!N%7(&iIcN8eLqj;QF=AQqx~w7W6;T=wLd z!J@afQH7T}T@B_Lg${|VC#=T{LZ%MCyVUwW&wD(*xvkq?ZjX`b4$bYxDsf_r98}+~ z>_S%yXPR2uoKti01~wnf(IiGLKOM0x*PZ)mJv&F2kRHU$#(j>HVHd@1aF?fqktD ztP1Aa(^&dSl#9=%Lx|hU=-q{(G7L)(GTsTiS&N7KR8VmQL?@I(6^P8`m%Ch7eSG=V z?}$z0m>{urG=0@8{VCt2G;rH~p8t zePPzp=puwNGrL|h;k*HDj5TfzeeqyFJ|EgH3~bu9jymE-I=cb zfdtH3YIaO4qW((J(s!~@=WVO${1(o8PP5E^n!T4XZbnx+D>djKXI57B7mz%>3I0#y zosV!6Lw1{qBR~F7!m42Z(OK}Z5;e?ZuLXtOXaQE7vtb8V4tc@f*VAf76`m>Yrh&dS z@m}RXN<6Vc4m!7>vkgP<^GZ0L*t{WLxBCoJEy<2G7`|z#!!%-J6HBdLTc4-}8A9`E zh;iDrN{u5DZ3!XX(k1SByA9ogpCfrwG|4~Iwn>X&tE$8502NjZG@VO?o-R5=<@j`J zEz&w6(A-7mC1~)l^h0%WV-udg8d#0tOI+M$_Y>E8;%$BZxUKX`$$Ux(a7GeTtIJYQ zRq3{q&bh|?x~dW!V3X86W_HQPv)cv?yJ=;6nU{OoyRaz7)dvGy@rpl(3Svv=&FwKa z)`v65b_9V2X<}ab$Hw|z2hd*;DSD8-bd^B51EyxIau6LVGw58|sS0UH{*#QC&MDBW zAcVh#fa8q(Lu-xW=cG8nU*tA%L*AhSymFwD(+-`siL5+nABW_>!Brl+|~vf^VcS# z01?zdjpczs9b+%^AI;d-hqApZPr0iol8PNz!vC`>Vb$JE2NKjU_!6SNP3dLYDR#Hh zaC+}Fz^W7DczCWm!!|hfN4;mmsiP)$OyL?<^G*IXp#8Wv{q(51ZvQ0T z=6CZN6|l&wWNfq`Vf5D>q}lVPHH$Hb@{zOX=Aela zql?eYeWiX6xbJ0-(@JOxd$ROTnDKV|FnQQSg4!?A#wK6e+}27&EfHuWYNg-CR0_Q;uB(8HCYX1IjX*TuA`zF z&q-YK{25CZj}1^PN1|-TYtrG#s4%sdP8(z}h=z20?RtVH=V!CIt>Q*K$eXF+*uSC9vkr|NnUH)C2>qjUSVksXzet<4dQpi zukrR@TYl`xsn5YNc53H>pShVUcAc{mB5{^lQRW;FeA+YCq_)EKY<#sJVxE&f&$V$w z;Wn>=t1*kgVRH%m)XiuCs(iViIv8Wx(_5sMO?_cr0keYNf;R5FHg#gpjO4*iQH=GY z+m>p-_)3Cr*7WUp)B$G=C(+}MQ#a{b;5|6wQz9}sVC84?rxc9hdS1fZ+M*cuIYh^ME}2 z9R7Wdx`*{-E>o?tys&3f6_^||c9JaV=dKb=fBp;w1uWz$Ub3G(1U5+_(TB2j_*UKY zPahs~QlY=EPJdR7s7%xtU?Bb^CbZpVK=+#lJ}G){9~qWUw5`;p&=JLLc@H1MgS+ zEzuB=dakt?_*Cp;D@s-xwFO1LLyH>szJhIYZoXd{{%V2`os)!r7lwa@)D?>+_e+i!YH0mnV-wKDaz}*P{TZX-qzbpbGV_HPw zDwa9P(KFjDM}RH$Pt{{kJx3}CBBsn~IJ`uu1ha_Cy7Bjf7TnHG%3{ta=@yb3ijSyP zS5Sr_IkUrJ6II$k9=9m@z5~GLFw)9b@2A@!A`HKGc1rePAbM(r=4WfA6RdLG$jZ!nhJ)vn6y1FGg1^ob< z-0l){^KFB|YpyXmX+%rBU5{vF=HqF}R;Hbc+AO;w0#s9+U_RF=7tk6~EzHSDR-2;U zME~Km91OtIAOeJt?oO<9F*ZYs#3Nhng*Q#X4bD`9x0=YVl|;j>DaVjC&TUztNB)6? zZkS`f34+3cpvf1n*?=qMeN|Pd%xOba4Q`a}8y@=f59Hh8ivN(sPGYscFqN~2`T*eW zR5jQf4@91hdkU(&u8*}%dA0vq?_G+i%cK2dEbfS(Jf?qMh$^fs@^Rc*^u{+=Ky3@6f?Udx# z={u@i&EAZbPmLX~j2rOHn4&@wLji61s@b!DZy!L`= z`K)`!UklqOc@UY#oKa{oKowfkXy3G}5hq^v-RYSImz&(7U^nr3QQ$;FLAq-ZvLm)> z!ts9kmB^F#%+r6>t|vqCm=cVa=xanHP-(ZZ{9CxHRoa~CCzRj zQ<`A&119|d;9N*_!krfV8Nxwx|GC|zbW#@Q?K=>M2JzvoIrYn=(-yo;>~RG>q0FUhc zk~H_M+8c(Z<9!`7q{I@mr^i+IGo7X}L-Akmy8i5hZ{_w%sP(e=P|rLr z3ZoEc+E=oB)0Vd}#mh$I_n%-2FI5ApK0b7uzbRg%5s4pJMSpC1g6HU2WK7Z|l$6cw z{vy~}B&qnNTpIJeY-6fs-V&cgZz7`<#7hX87E=`-WfsPlJ|9{ms;{6|5LHemANM*G zmwOuBBUVqd{==Hq^35HVPI^ZF_jptgiJf?j(0nO_(7_tETihj78OV8em2td5OL1&m z+N{(z4t0kUeYC8Ro6WAkbHcfuKJqyhVB=B-4rXzNrbdvc38@y91T(DW;hPgpYN4Xa zW*9&;b9WX4+kG)5Z5{C#Zt8R@MVpHfJfvb7l^76Z{!G}|$7U?u?A#x*@?~W3A_2=m zeD&i;lr)DjkKByTq_&snNId>8fq~D8)I=crcA8-nkpnN^fvE@vrr347DS`_!dt(d| z%t8R_vhiiG@O@iMJ??~lc-v70u?_Ik2bq?3Cb;CExa!Y3L3d0xUH-Bu)! z_8+I?D(5x)9gM?F$|Zxw2Tf+ASZSQmVegK{1Ku)9p`w1e@yB!&ptT#<+_$3&)`G-< zsdTLQ=k=M3v|IrYn=IQ}<|MnChYr@7$=;mJFB(z)AVjZD&&xkqNELt_MAX%zRJC}d_8O3;(Ho8s$B9ip7C6F z;1ufU{2KM??|k371`3={X)0}h{CoeX6k>HQt}MWN>t)DES%AQf9;$w#oN=b6T6f6F zD9nv3K(Mn~iDM{$hGP6|@N03HpU+!Ht{GrEbQ(+tc!*z-sD7dMCG8rfMf_#%{_VEL zZgMS(0lsM$;M1s4Nl`MQ{Af)) z^>#GeFQ5oIYp%UH%+Tk?f0JRvQ+%J#b6#*+3yQsd;X*Bt^X=9qLwh*VMer%)QjH*Dgz5xx^ROH5fh7uat`GbSY2Wkjo@z@cYgcAC$P8hJWMS0MhEl!Q%i07Cr?Vb+|BTo z#tTb?=bgTracIqna;XgO7dV?zlf}H#+MUp^P6=cQbqQ!$$oFxA{_0#jW^VZ`#G_)i zLK_+3ThR{u#G<>FSekh6=6OLRaa^H0T?WSY8nvS3d?Z3>Y-V#m$zHbGlW)ee5+qLR z8r4{kw*%=-?~ngMRuT*izNrRyn#3 zLDYxUfseVp*k1!@j7wkASsh{=pD+$hxsifMdYyKc|GA^BR^Bg9!O6S#&>N!N&F-(D z>98`<)hz8ajaz>>1hjhoZYmx<1q)cT7iqXQSdojZMDSM;CSU!|<~aRKp-rb=Rx+^r zpS7);S^c>x{E>0ahds|8MSHSpcgg#C*Mr0~hACGKxD{1CJFwCe1-|w*s0fpClz)mo z-m}mh&qfQC@rg>udp}6E^QV(d3RYh|DM0~CW@WkLWt#r8by8{n4o%Mrqbii z)Gx-{3}R>^Rvor%oTf{*@HE8hO$-3*2vv2^k`j))=O^2i|3Fah+x{OKSs{+am&9LO zH*^y*2Zm9O9MJGf`EC>UPKu15d(5XMlco&L{+mI$ z(N#NC!<4n03mU`e7-!6K!#Ne)Sf}u()o&9+buFJ`&%&$`?;R|>^b{YM;K)xZTdC_! zb@rwvv#lG?A>r9BwTjuO6R%l(aWERT1LJ=A^I!K3*iQ?bz&ev*p10hMjGL_xCP$V} ztPR`N-21A@d@sh)Qj#Rrn*Mr%wl}Qhzb)5$Y10&>k)&>c8Dh8lM~ZwlN?#i47*3l* z+8Yf`c=^#8AA8)L+XUnh*@^dp{=a( zQ{HtOYpxdt!Dfl!H*DgE-s}a<5`Tu4P5M%NRdC16X{GAn=xVtqu&qI!bwgN$?h`U5 zo*r%6-?sdT>$j>AuU00-{L@t9vz6(JSDxfgHa#ioZ~c(uo$k3Zo1Px=KxuwtAuzer zCV-VolKRwNK_hiHlvQ}o2&0<+vm(;-{?80Cf9xYn{(+Q|L274I{ReZz zdsjQ}doo#l>Zd&K_I!Jfc9NgOR4r^nSjLD(La__wjU_riV6S`Hts5Gv4+E#D_*|@5 z#28&iz6#3dS-mf@fVqq8nLV8?QWDMc_{04*n<`fnJSSOqpn{GOs5M?oZn5`R|3jnv zcbTcJxUdc`qeHoM=HO`A0r$>6(6uoeCO=Dv?C~>@JZcLI5Ey?DwF7lQW!{h9OkBxZ zpMqWvjr=MP*BUQlrmbyv#K`l#xwCf`1WlDQNBpm{0(<;3i>Fcm)J1$W;s2bKhBIaIO?61Tbw%x%Zl ze{2w>A?mN`G{u+Mqcwla<&o>R+Cf9(WJ@JsbjV*=^YZgumrhDd(ETb@OG7hhVv1uw zws!g>YHk~U^f4}MD{8N1_iObKo#<_|-Uhc9x-hS0RI0DeECa9dROBwbyLmuqKxPl+ zBu_#vD(Kv$7knV#WfdC5zcbzTDvt0}S6z_NdizyDEH&$J$B&Kb z60O*9i}qcbNvg+WyjF+-K0Jzx>GgQFF*~ooZosYo3gVdV2nVyT#6)js#zA(l^>Y=s zrFx@#Kl$^PAYnV~S+i31C-?L4c>xvm)c|caIs~}8W|uQzDH?wQB)1vK3`31kM~Z|h zlPrBOCe10sZgC4aa1BWEQ(k*YU65bO01-YN1Voe=gYfx34xnE}@AcvZ=FNxd zM5-p?ZPC1G{!jQK|BXrhohq&pfvJyl9QN<754#3$B>k3(;g_*5$#lhwoQbso<3|IDq9~>YO2%M^o&HfxKvjgj=zzN z6;(+%)yi8yeaow)aC_RxG@lR$-;0z2W2{d333GXb5dBnaR+nH_WD7&>v=R(_%O8f9 zDvW`!1dbYbzYr<%=M_@6s%-l0mvBq@aZW74CJE7d?eZ0HhA>=Nx)EPlb)D$P;-#*wIk3}UGG*$3>1h#7%l$nF)Ov)MQr?>-Y(ytz5!0dNZ9bh> zhuesU7tB`~8<~7Izf_;#JUT_p3p$vjuUPZ#@fp(R(1P_wPg?H^PiOpe5H5W1={;Z) z6R(|8&EZ_spAIi5a7iELpR8eia;uQCz)M6s$2PWX-rNThgKJJnDp2;S^;O*X9#OfF zCFwtAFP(2}qRqY?!kGq|8r_5rz=%>br{R}Km2ji!ruXI9Ouk7-O zlLhfNf2C~;G1GIgN2AgVl(4vF~h}prmmxcbOrvWH_LWL!9wLObmgBQq;?xjlkPQ5Z`e(~?bp5T+fsZxAhMthVkZCc%{Myqdoz(72~&p# zJrk*+tLDu3a^(s{l~FzIPeP(`KPVOR$&XlkGMCVuoI>MOc~|K1L-JbOASSSqb9ZHc zzvdUtX%B9S53AgS%ME7~Tf~dN!%>JAhMBxAD(^lMM~!ox9(}S!d0YyL-as_AJFjS2 zUYdkIuTF3ClA{k1=4okYxHLXWeOg`D=z1;F?iu=`F_FhopX+J2%jaqfjNvqdy9Vu{ z#qnxt9T&S9D)garKMxgk@U8T(Ugf1~1tKw}Ws>#Ws~>8`Y1vRFI|K8b&M1bZ$%HxW zuLltqBtOPA<3AK1d4W=g|tRHxoL)Tzp1VuQ+3 zZx*jj7Upuc(;84)>?vWr_wXzFRTBW^J>(RDs+uU{twXf}QF|pirR4 zlbG%gS&WnJ1!9KNAcgt<)c-Se=HF2N|NEaJDkNmzDqE!?%h(yELSm9Kc9ks#laRqM zB>NVMvW>Fu31c_elYQTpnX#`k*0Ig&`+T48FP}eP&YAN(&*gEy?$>p@sM5hB;~i&T zPc+w#n>!GGA3I(OlVixQuXCJiy^~y4=O8AXUc&z&ENgG949tv_zp-(c0|7 zWoHRAs8sv+AWfk~lAy!E_~@yG)b=_5J}ZuaibdMsX#L9~v^(YXz|4IDODdn&7I3-K z4+Y>v#ZB)#|KY|vAJ?R>jiXt|+T&YsrSs76MsSL{k6-4YFtCq6l#X8V7soW|7lD_^ zTiE%&@hXG*>fzHmR@N?xWZMqvj$Iv%TT5tEcyBrizJS>bCRtA zI>lCpFNe@fC5YpS52Npt96t6ci<$5UL>JaRMNfrZf5y1{A7}%%+;-wX>jmzY%T6*-v#h&%js!q2EI5I~0CRT_u}8 z>$rzHp1n8Qh9m8lPGBa-4&o`?8@So?mi&5yjW=RB!CQ+XDJM57qJY@<`qO>t7}-<= z8Hu^bsSW%~T)+EJj|F@hOE!A<6w3@@mn+w+zm@wFJ(G7Hf2xio;-ZdCs;GAJt*;D5 zx#5ygUVom#C-J|ro5~cegS=7nn?|KU4;OL7#k*G$C)JWWlQuUVt!0 zmSYXP)YpRCgOcx=@)7*>_m+1B3(3hC>aEa@6#XSXRl+bOq{-0(ft%SE_c^Pkz{BLd z(O{D5g)eLxk)H1aQn{zAo`Nykl+(f^d5V1r7i=SYKB((TPJjmRsD=j6`X~R`4a&np zg5U65f9nOre&)6=V6>rS*}unW17_e%C!@9;%TvjQ5ou3}>#Ogk<&$kh9k22-Ph~&z z;-f+R+1W>DMW=OTniUd;(LeFI&mF_+|f6#vZ1*L~-E)1>i% za+P$;rx@h_8Dsml-_aEU=5ZO}DJcOGSEexxe(n*=^eT5Bwqyilz5V;d=@A1zU7$7A z>KfJY1k;(dR<@oFp@Op|*ZDtmlB+C613ULLM7lYD<3UiDh8j$ib@@S*aGE@8U~*T& zzA*XoeB53JYb``y@`PXC(rL~Fi1Pj3JxLO_yZrvW@_H1uSoQH>ixWcBU;$ycH6m;v z;(NZ{Rb*Jmtph?a_wSpl%qhD(g|HT;U3Mauo(329ZETBvF73BK*us&Sw7$6t`|-_U z{M*=brrMVS$|g=hgQ6ia<2QBlbv1?Is94j={)~i&fhn#%1tk;6c04foyJEscEU4S$ z%$E1R*SO-%P`H1~@Do^y+q)}4zRte_D=u6dQ2yIzc6M;-jDf>+>~<%_DG6B@_qa$ zr#T}0V+rK%o}@m%VTiub3-ad7>ZJ?&Q8!FF7oFetQ>xDer8j1tc%T`m7_tpXI=mi2 z-nFi!C>|K6*8T^IV0uJve0-;mefpLOG5VVA-}&@h2XVX!Wtai ziV?Xlxc()TVq|SHao=o8T~Oz?V^3PQX;zL1o)ljWQJbAkO5Lpq&&!iPtw^N{Z5Tf^Q5I%~JH9 zDW=S8Z~BqcEwqdL2cYFsg4UOdm7>Qz)-JC9Da}%oBf}1Asp7`kXLzU`l!-m#N6oLY zdOM+%Y!Jm-4j@h7-wIER9oU^U_zRr6oaI!2@1n&j$-Olh*3+h_C+e^VX zbw&4f1#@j1$nPiJS#C==Wo8b2*w22h1)SELeennT4_e(lD+J84DrhaBxE&wv^Y|-4 zQr)!DI(U}-_rPAX+-79_g>k?ZswR>_RU|CsXRUm2Yhicfj)k-&fP1DxxAlOam6z+r z^s!AU?cAx}86NKt3t|d6OKW7IB27j#-)?#qbL;&ki$~vKS4hB(>tE;T0 z40VA`c9Gy8_n}Pd)|~sr+%1Zu2~E&Xr}8A-!H4hj#;ar>u={@1&)|@Y|Fev{ee$TE zb=Ag{;!90w!c=$#Umv@>uLov)Il3p3W4`*!jOV(-^$vlZo1qDA-ab|2(cF#wQi;%0 zwyao1*=efPUmK{xcG*YmWvep)_tf+VV;>u9O*Zhg4xOXlTc0r^RmL`@NHe2|aO!K{ zAA;PbLmu{#M#)QOgdJDWBi@fi-R79PcrbeIL=I)uj0CL+JAH_EAoqMPqj$N`^KI^H zXGc%^t@N^U(%@nd>cGz#{d~Pwu8myxuN|WisYQJIqq?W-Ut@;!H7=dyahd1*is)*G`S&GzG7CdgIA2vQq{H$&k^DW^#U4~{Lx|bqhqZKK4|WgVDS$e_IC8)Zp_A} z+RYf~Whw`8dh9TH`r!!`?O0IS7Fxdrv6w*{n zKHa7^sp%JFwl0}I9pD8A+_5!u<888O^D@?3S&-u@GjdPlFqfS9D%e1ovh+ zb^moj$1AGeLC5?uw^e=N?#xxd!pM;2rk|W{B;4DRk^z`p?JS)x)onlWI!r4Jq56qu z)IvWklmAwf>8SDY@p?qM6}Gu%fo#8=jqq$+1v?#QB`f4RRdKBHiKnDJShv7e)A}2R zbMDF>bPaGoTdc47vQ4n^J0JB5oDjV+%p`f&WxSyFfQ$FE4FGo< zf1O6)TsqEUh z$Aj(avSaW%Oo)$j@}42)ZHIfoY>IjG9bN{*#m>nq_dZ0l|He@+%zSOFN}dark5<$V zSW9B^lAZ1;D8zKBit;q^Zkrt@mUkBF5?MK{vp&SHt3n+4NSlT#KmP;e#aw+)3rLrY zqiacSo7wu|I4?N^*ALD?IC|F1=~iMH7oYRfIc{(TsDQ1TH-Aj7%!*M;!-0`)S9r?9 zn(>n!zr3cu_8ZorQVGr{bFH(YE^oTp^bWu(?V~Ff!FzfMg8K`1mBQa_`P!FZA5&PO z4t}qtb5zy=ULiG$w#+pSJuk+Iq~LQf)xuYA`GQAMkMS{{EZoh<9t!_~oCZ8xq>h#L zm4>7L=mve+VDtf{``NT5<4PL&%gB3Br?C?3b3NqM8E+PsxH}|bsbqQ(wFGniZM-X1MW3I`^2uIr^ zHe%B6E3EQoM$PW`J&W%Xw>cdRo!qt(cg|j@Xli$tX-gm00M)#Gxe@z@MOlZ>I_-Cw z|CV(y9#n*gqz!V3oU2jd{NW1pQp5o`sZKP&AiPn7r&NVaZOFEF6eSLnij|MQ9Hv}} z%XP#d5RT&6nO)~9mSDRge~mS_5D*sB5srvW2x8LC_5tM z$)7Z0D1Rp2i>$o;=Rc4Ip&F7@NR6OTXSKMaI9?7*r$Z|{v!}d$Yy;B4#D~o%?k_jc zf+eQ2=5uSGr`~>OG1A5jqjeS2mdQ{r!HhMHigP35h`Fo#(I3W)&20x%J;}}YhZc>a*ZV6+!d6uAqfM+N7CQ_DZ5Czemjt&0Qw1To*XN5Qi{O~0oj<&{aZbq(;A<1BlozH8KwvEKM8mx`P3pHTj2><4F4 zMGWsTh1Wl_VX6OJ7JPcv!Kl;&@<|=&%fIjD-~tYsd5j*)8-MtZLG}AJTcd$(*GH8} z;T7JKj4-Lebr`#)zGqB~TocqRxr4@j=>ibzL1qmWm3~QkVlpTeCG8=_xKp6#T|6PL z;Ny>rFbqBL9GD)(Eh}~1URbK>4ZI6MUT)&bs-5WwbEq2P?}`{)6^U7z-n9(FA0ijtuwpNl6Zr|UIKV@#4+S`@x<&=v+j z=d|C6s^1YbG7i~Nf2Klf)cc>TimZbn|3Pxp>KS~F7*(;t)?;>ew|N}>*PmLULPk6 z7OB}VWFNvm<)>&;>2T-x)8n_&Be9IH_DjC#|F8yH1z7gmy1Be?k$w)W$qyC!Qa^K7 z4b}j0HFR-XYjT45THKu}$M_cB@3wSNziEPR&+E2_y65mj=M-l<9b7EF)8U$6X8q=V zH((U^$$z#VJZY{e(+jJ1_&9w4yU`r3M>A< z5Jvj200xm*@H?nV*LRYTsa3aoY+gwO>^5m?ojuTGP>cDog4<4rbIiyOame`Rtb}H- z*YJ1hux`XK)Zq+E{^q!Aj_DY$Q8vg_gD1^+N6MGC#33rZZjh+S4O;W(+h>)2rJsu) z<9R)m+?%VVlEzvN48U`2DAt#NWk~oO3OJ|_B6blUR%*E#vaJCT24!|Y&#vXpafGa2 zddf+bCooOty$0D2N1rAO;&tYOcz8PI5roJ; zqV{&0sar>IkpIi?-@9Z9;dBBvH}m83yx7mV%K9WvwfesaX}{FLxiNPI>d=5B&Surx z$87TJ)WEG|GzI%MyvXbGRc+f5{b&{H*!#GZ<{XHdw-UON zdaLcc-}6X;{v}xSY;S~;TvXw|{p8v;1gI(VelU1K%c#E;Rl8I=Y_@q{rgqE__mY9( z!pOP1Ue^)=arN%Rq>UEBc8LG=#t~s+X}~t5PVd`ZwEw@B7dwq2Z{_0Km0XL2Zrm-) zx9<$cx*EK&bx7jSV|&@wU)bq#HZ_NYAgLlTD}C0CYyN_xizB%aON+BG2vWW<(8di! z@3#b~+^FRkHBR4rYVUG;I8oOndaCFtdHSrDq6u>Gbgi6#<)8Wvxwxh`lQgNZKPUWG zi(RkNnnp#ek8MM@*(R&Q{O>x(t?9ZDi|L;COTTg1okYdL*dC-eT0{=}CQn{2Vn2vq zs`?uHI3>a?^U#5SY+3coVgIA9-y(A2rDsQVHeiBf!|#I83!X1$HZ| z(wIB1B2#?r-T`yK0{l9>O9JQ|{DNzxQv27Tt{Fw;9`u$P>OP-!| zqD|9X_td58VrxQf@TuLExO~8vMvinkmMX{|oHI5m(7Ku+_OTZQT3C2ffATo8RrunT znqC3=9)~>4k zVu>XLb^&cm5$sN9Z4A;I77u$;zWP2pCMT4ZEb;Vs%)-ITMuM{;Rs`S^$~F-@i|b+Y zb%mB12Q1H~VT9tx7ZA!X$0Ro9qgr89csZ?InAN#LI6VEbBfbI+EuN(Q?o}>!l|z2m ztm7|Uu;3C(9rAn$FsusKF;pG#h~1XaD#IHiQW}UYjprs9-qIqC3r>wJBQyz=Kr=OI^QX59EZE@#OTbAwPCK%wS>a7m|Tyj_OjwtK# z6cJDm4JeV-M+18U?%Q9pY=|`mM*;%aYh?@AA8&C7v9oN2ej-htl0wEjT+!asn6cHg5`+YB8p-Y4CeXcBn# zS`a9?**MH!HN%8J^i1zES1GDQGO*o#mHE08awJKdQMSiZS}%cHW$qJM3{aU5JKvAd z6B|#-p>4i%j4Nfjc30B)t>$!*_v|k8e|{m9zP~G#Nf1=n*@f3N3`>dBH4cl_+lCvo zEbG+<74TzkP#vXjjETtH?dK4=!BNsY4q6s2C0XMeFAa;;k)?xOT$U4cOHP&P6|dZ% z67GyR&2A(!gpJ`2K^7^0x9n`u!4C?8N}zp^eXmb64Qh&J*^oSoRG)sLs-^l(Q*lkZ zXOS`ZU<*Zvs`Qi)>qhLy(T|UWZ2gr7zlRIV-<_{owvHEObCJtK`F2|VO&5CoRak1f z($eM_z5;ki!@1|KRV0#^s^bV!#`bI_FF3ci!4?jAr<- zZt&Hnoa#np{ENP`a(nOJBO2#%DFGj1#XDB7N7UVSk*RdHGP^#l+YS;Q#NVUwuDPM5 z#x}Rr6mo7e`|74FNGOrA{YYeMQd?S0Inxe4Gz;h*H~GzPV;t&}@rRBn5(Qo8Ax9il{* z-n=>v-C-GQ6jthYhKdQ_3#PKL*L61XKCzvg8LBf8@`aR_~=bn zg-w)@K3ak_M^Ak`^epj~{29k%nez&o_pZpb-;>-tiJdIhuNln#HPXm^iXK^*-KvsB zLw#3kH!(e$cK7i{{6o!Q7=}x?}b`6i5d+gU1u8y z)_)vc=R4$Ag|Gr~Sw;ERoiBkz8HBCy(Y7j^H}K`xUM;KE8h@$c_-vx(_R&2)OUMs# zZ{|r~tdue6^w0Z8Af2!(5nt_J=X!@W%|1^}%-np~!64t9rz}#%84vL_>G*s##PuSN zC|{gdjJWBGbniBh$1~Hrcf_Nn!(UvufKoahEmG+2I{0|_;JtU}0;#45=xvoX(C>V} z_)mrQviL%$BbWY|BQGiF<1M=CvIc$QW@%PxvLU^KNo>n;YbH3?dj`B^w+0RunU(3A zA=V0TrO?=5Y`4oP45@h@mLIekCJtBz%+|a_LUC?Ejvgv**rW*3oAisKM#bBfDvN4$ zx4{WLbroM#U|>8Y0CxLSOJdv2Qao`0TyMof>Ha*m+HIy!*II^86Rh`=_%JZ*%MIP> z-gP~VL1kR2vWS3jG%SaxX^G(iDg0031tE}=r4tA~T#AE5@at(;Ko!Vl<1l0MvkUWw zuTH%uV$0$Cs`k4}1C8QuC&L0Qp2$<{jod+(uUGe~rRm>O=xgo^xWpRbxHYd=2q6nc zFY+Oyoo`+uSYHd-m0!KVC^IqJ+4tT4=xn49d`W5fi)p2c5Q|H(nlv$7JD7GI^Qs+^cVqbHKG)WW26{!Ke2 za-F^oVB9ow<8d|Rb~VQ3AY$1NhT8Jc1nJ0Q-m4}~+(T#Is6W`WzasPYCO({xEuVH< z3aAS|GFkSf-JsZKq~H96524ARJZC)r3Qe8J3bPk6E`HDWbEy!d@vvi?`bN=BlY37! zr5rWKLE}36_Q+1Ap3)KU^dpVQGa)is3l@l99B6_%28LWsXSml=Sd%`a7l8@GGrQ#S z`TXNtA z3%aLCZPHhs9y+=VNNIMack%PYzhHlIsR#*%gtJC8@>#%spw|BF&8}-))@3O&j4@t1 zXy#}gPy|}$OxOd`GF>%610x<&swb>e9rV?$V`FSARaZ^1zRQzvWWN8_f^DIa4J2cuF-Z8cfkxJ}MK;g|7YB!o4c?lo7vaW;>el;;i7J&QVd;+447)M@=9P zrCITziZpATgboc>9I99(?llD-(sD@(E#om`CO4{Q%6gptr>RNcs@(tFi@dlhlP1vs z23<&Q#!M5DsX_Y@E^bpz*JhqV((@C30sGaFZ_YbNCmBbg{Sm5y!fWc32tD7hGZZgSB*t*(}&UhrqD-hL`AL19d2}5U>PS+c$u^i^8mIDA>`A-J1OdjdV?_HkDUr{^<9Ed7~ z-qN*staMLWyqoM}pPU$v4A1_uxb#`*LHfLxdXGoP{RVR1r@c8g1a~KfG0KyB(4){z zT-?)BHPS~Ght`0>&t`#|7tTwH1vhMPH1n={^)mxVN zT}MXo*_%@n^OgeL^SR@97Xz>3j+Q7FhEB^KGkRb852RFLqx%ba`7O)a<1!)P-y{5H ziOtu|^$~S*UpOP{7k~;IcQXYu=p=;6&ur^#V|38X%`vx|_GaP;T~RpxZ>G-)^n=i# z^5L74S&>tfq4tuQ3ABeHj+dq=xQHCAW$LQ?Zsw=ZKG|n9S{b*n%I+ld9qgR-lp*0C zz3Z1kHa=UVUm^C}2>;BZ9IXq<@?NzmTS|+widT+@eMD$>7ACcjNq>WH=`{Wo2 z8LXyGVLd3I9ug)PTc8uWZKKhcTofy;Hhxwa4JU4vG(Ktpx79=p->DbleTQw3ToGmf zrciFeSU3b=A)#tXF!ETdi~WeTQAJG0#$;&7#sV1fHM*i(H+fb@GNj>I;FQ}$K; z%$gXF)$7l1_qDaoHGCTjOdm*>`quSDTD{Wgo_EI#`m+MVjZ>Dq(zR6t$EqCsCJD+M!b8UJUzL(9SN&W1+G7 z^Zk^=C;I6Pg zUz2wv$J<){&9WXpytC|BDpyX%g%Z_eS)NaA`U{am(s;}DZs*1zT#S7cF21RXdR%u` zq}Q%Sw4&$w)K0*1=B*}e#!u0gG#rF*mD`6j2QH|rQIfRy;rf3d(Ac0x2XVigqQ3cO zfF>|iT~9s;f2}x6)ACZWgbGYeW_ z8ziM2ur^0m)KZ8Gs|HUliRtkTV~5)ECve za2VENVQ#W&>=Rg*q!*WZl&oL9ppoguJLl&$IHToqof&??4cs2>&KUN=RH58yS2t@# zg*~oN#8USgm>3-+G3+qSyeob0X1XRQz0ucPkZ*|u!`C3GIuP@3$s?zH8De3{GGgsm zhj%SE&lB(!5V~D*OX)R`$x1r!Ah;U`9gi+Xu*idRo8BEvx^#7Le+LKufXegPDvPf_ zv#I^?T=uF#;g_)jXjz(KNRp|P_d>6Q~AbRL)7hUqg z-AYRtv_5CUM=DSRa8M06;?wPe3h!T4^1R=zq94IH5hInwsNC6M?U}pMJZmY{u3Rsd z|KQE2#+Gc3EhlWhN<)wDUTE58j=o%}=F70dgI{Wq-!vS3{m691WmNy-BPb zC0`5PCcHH!uO0VBdpalcWo{)7o$!t1wq>cHJ1-vvNB%p!(rxk=jSq1yb>32YWS32K za$&NruN}Y>_<#3%{$NP@iCWa#c443M=@CAFeEIx%X!-}Mw}^`}%dRi;+;8b1wEGVP z-xmz8zk+o5rkW`*kC_dgvJpG$8MCJ9!St&v(TNkBE*zUePwz~);95kJK_|#&{FOa@ zDWejnZy2uChpU%L6vumUT`1Iv*!JnKYBdkyontyZa_A?tY0N8m|PQlMj9>hG&Pqjish4eZ~LwS6tHo_x!3L#7>Nrp8o3F z()YCrKcS;_ABW`MK`9a$J7!oU^emry4AZ2kv5$0%N}XwTzWAz^&%Qw?b9>Nz`E$pJ z`OP~m24vT4^^mmXiI%MCDdEdb?&GVoH;3nI0NQy3@6Qh=FVonX*>(=h*0uqs2aEZ) zt)JwPnCJpW?nEC_4?-;Gdx5pRl1P2x0r~N-{7csymmInh=(;(NcndI1YEawi3Vpl2 zNdMbwW}~TAC(rsT`l8Y$8b_pEiWWXwGkt$u7tfg3pUGT!Nm%VNK(_&?`rBvUiZ<#c zeIeLbh%l?=w0hfSV5+8e6Z$Ya# zw>Zb}4lh7s%Y6jBx{2EC&g48{JTdU^h0j&k^#w|SPqppl$M;gaH{b>%9=m=>pS}<& zarX9W%&`QC(kG{mR0p6?I}*x*9EvSRk)EWo4I{tGSr6JLl~AQ7Csidk&9#61PGuQD zU?{g}BWkZn>S29`>zcxeY?vmQQ#e=lSqgV++PRDR69cER5aa895~ZaWd+bD#bH}CDk$$anr@9EuDLK zZzv06Cn)0?>4E7M7|UEum!ql@1%=@Qd$6l3e4~X~Ht>-ooksJF(V$hV4~TkVF#w4y zba^n&_@ci2>le;R*uU^pKRfsR9yB8X=(UAZg+UZ5hy7*xa;z=2A!pfzDDmb6ovR@- zw;kpF*exVrpPV^SLNb}0hMXujOTyl3ITMVxKf{KCsPK1CkE~JMgDA z0h02mF-15;UYKEpb`{^BIi{vtn1gjX~YDMrQ;yzDs4M(DSZaAIXYvq7aD@^dFkLbXeqNC5*YeHh6#OoEw{w{Rg(xC>x%e z0UH0HoOs2Fk+9Y6`%^v%~*l}5w)iBk~3Z4gSJsv~t^d;QLN$tY)v-cJ&@+-j) z1Vx@I__a;04q>u9OYsX-_>Y1okH6_}J+jIYcgfJaj6Py^0Fy zo#cOMR3Yyc-32tcD_Wd-RbUAd)XE>0>*Xlp*B|&z5}NpWss|hYx?#)GpqnJ@(Kd^> z3wE=Nzp-UK0ROb=<83X|@)AlC)h`#hn-%j2opPeP0#CK z5GMey(eL)>-l3Dy=IUfr-zc65Kc8WxDkMQ&B*(pQYQhk1(E3Io(I$&-f+5A%%gZYd zcV)mJ41}9@XBZ;c7nL;T6O!%eMl?lw`h7rrG7n##)}7pVY(B(*&jR{ntt+jtWYU2R zRkFx&$1ibdh@cRZJ8RMX?_cBN6xS%3s#vUdM+3m8#R3+=UqGi&n&QcI+5u7T&83rZ z`+1tB;^ShZ4uajGD~^%XZ|W;fB>GTwzawnFMx%nx19+Ouu3-5CK|- z_#xY@`2pfVdFufs`=E>%{oee*ksa~vv*bOChjj}bcis3D!ToT6ufhU-6Al4$H)}{z zqWop>DQ!s~hYWsea5dl%jJqIlgl3coOuEN2e(_^Xc^I2fVyBGrWYaYV4am~@da0%00r>(~lF-#GGt zlR`I;|AD}#f86)`($GM{ z?PCa7l2)WwkhGzr{l}>sX zTgHrUO@hDneDdOQQ@Zmee8GkiQ7 z9JWeRSSJBk_51lBQRR{X*HP=Z65N<#N#OtOxb^+<2JXs-{}<|_=zM!m!Rn9W0xUE zvodve`J5rBS?@@Q10ve&-q7F01-p^^@ed4i#OD&QK6yE_VJz!?*L3g6OqsT3zZ_Lf z=}_2xsKj_HRk*!6)Wf{YOFmwKa6_Ao31#=HYoHI}e=D~kI@jSu;_DL6>&UD5nwnj% zOEq07EBAi=3k-1>zhdWbBkAj=RfURxr^+?Rrn8m#^i=V$odMzQba_R8ql>#;@IO$l z(hMA4HRFt6E8CsxuG8r35Ueh_t+Oww>RI#9P+>)EhKW^zWznrpKnSsWLVDC1TljQ$ z>f7hfcHs%##^-e?<(xC-XUzq))h~)i*im@XI>M6ij}Rlix`H-PJ6tc4yLN7KnVaeT zoC7_(+++h#!TNEQ<^7hQ#!0J{_=tQ0B+Kj*)_$l$e(FyTs&wPXEyq!q!Jl{5@mS&@ zH@seNzF322X-q=F$14x|}NBsEgUe?Z|B=QxnEx z{;qgzDjE;&{YAqmbcTcVl7!-vdPRa#?-}fQU7sR1BVM^w`YUNfPxahg)0wl}Je(FQ z!fB&q4}Y;VP~OjwXKnWS@Dxpq<@#cR#D&nIVm+T@=Bv`<^}+>f1`&#ksvd)Wof$Sc z!(yXF6)Dtu<)0`_%cO_iYh=-!-hzHU&Q0teTU6i}PtjDD{&~sWvlIYj*FISK5Du`FZIs&3BRH*3A42F$_m3*$k<$Nd*>?O7VA`XS8$M1M~FY|rbmq1;B3 z$yq`p`RaclHi3m0REbS1-)Jm?F$Cao2wFOMN#06?vP_N3tsWcMfI~ol{?}m6r6EMN zY>&>jK+J;2_F=zfy=!gn6p^iaq}(MHUn(n4>N}bt(izAui81midV)qKxCmY8SB+Jd zd_A^M>{kpJ^D>yDMPBk%g~V?m0=^rmM$nKtx_r46p; z$=53XFvn?~O2*&OyNG^NFoOz|KjVH##s=TrOg^A(TSm3H-O>XiX6|GEdgXN4Vrq>Jy`Z{X@_BmQ6DQEXH}Lsjz)oe32&P1J*7 zBg={XMep;BLA3TtcGfCt_f*b-E4COYwIyjDCWRG8wM>@^IOD{^<=gJ)CFaAe76?#pmwMy&iG5zXOlo&SK~b{bu#5$wuwc4s(i2wJVOQ{|{;&I>j>?6@j4LtvE-rT=4g8O< zfRR%83c9nPH%~H7bEj>1dfdz!_Q*x1zhfvRh7RvWzX{kRJA~~6K169x!3PLG4Lwu1 zK3BiR#ZiNx!0n)?b;Hsn9w#4YopBdZC3&l3wwGN)l@2p5qF)oe)nJ}3oF!lH;tmYM zHn~v$(q^&CgM}03+IG&J?(1nH&w^%uj`h7e8?txj% z^0Og{p;kFFjNMxCJFZLDYaM^G9saY4*svY+tnrjQDHgUO?;VFk%+(KIVIl11dh z6EpiI*g=;62z|VEuJr>P(l^UYm*?g|yCsgmYX5q!*d#%_KBUc~!B-2RS`nbf8s<_8 z?YA}Rua%y?cF5Ng@raQ2grqZkqZY@_=eeJE>C<|MR`1*M10iqY=U!CZvoOg#Vz*ME zlg!_m9SPa3IL;dN!6ne+yxh2lW^YwZ$p}QZzPr;C1sy-+=y135EMA2_^NU}SL_~?Q z+vEurWLIVvHx%zp8W)UmkAj!Y0nTW4RDtph-3*Y0WBQGcEbMDt28t>kAuofuZ5|tK zZ5|ed7gzcgvN$<<9WRRH3)t_)Dlyh8XxW|<*}Ytcb?=%T5+mK zE(G^S?@NwVHfV}{)Wsc{%twHlhOO3C9NAg8rk*8V%HrdFKiXC&_8 ze!god_{}iCSyc^&$*JdkY{3-p1v8!{3Cv12_Mh< zN!)>+BXvi259od1-h@H2`Clf+_9ZdXk~l8n z&4=`!B7*_Y%l?v@@zk-_=LVqf$m?>TACLc6qA>3^rY_laeMkIT>m{C7j7uXM7|xzl zD+LPk+wNw)JYJ?KoqsmHFnqDME!V+-fo+E|W6;*4|LeGXZW8re-c}%JC*kx#K^Obq zI-S33xj#7j=gf}^OqD&3KF1P;zJ|S%sf$YYi+-#7Z}vPpQ7zTm60|3AifE+LDJGEk zFLW|)2Jw)1ORg*k9xBt*@yBg{tQtw)Ef4JP# z1q~7YeWh;R7sGvOK*ome>q6wb^HJu1fGz5YUi@$>5Qdnsybs;-p{>)*Mz=R3DXf1q zq{+~jidbIi38AA+n!_nwD#)CA+nb=}JS#=6fOE4#rq-5jwX`vg56r)naM%^@>X-q{ z2!UwELMqnOob>|Au+lN$TueG%nGOeQuszkK+EG*qmRsq-4wJ@>!V;o{#3?MJUkNUH zt;h7qe)zEL2qmWbhE#m&!MLRCT>Az+awv~gM|x~84sd-{Se zvC)ZoIG-X2KM1Dy<8x5{q&7aT+-yfmcEguN7n|ys-isw4c9b38#Kq=*k8w-Twp5rL z-p4SV+EQKS+xSF}6C)AX0i3Na?A8121_<~wYRZX<)pbv5psXtMkqdD>`)_vZWfhl^tEi)!}-@7UbZBiILnt%<_T^s~6ey90|XpL3S2PV6`K zW|riPk)J$cS?5r7x=6-#Gy2-X`1?Z+0ja)ZNz?t<^G~y+H)IG3)A#C59e9zgmzn zjS62r+*BkpnNW?0O+K~Ek{O69eNP0jSiv4&Im~AnCDPEYUtVHxZW`*_b!(|H`YiMm zlD`6=WGHssWh*r3${+vkAc}Xi`XU4Z(vXonq4gFp0OWHVN-q|g+PS@@^UiAN? z=sf(X{=Yb`h%%C7&y0MFOR_RA2}zO^vTn(`E^b!V<%;YTLfNvi_Z~MpJ1(w0?lrRS zHLi>6_WS()fctp3*XMKI@AEpZ^L(iTW@YaUtUwe+1R~oU)(v49#PaCB9AU!!I=KI; zHgx8L!fba0uQS)Fsi3Gf74H>Fa1rSvMHOrsDU$4YSSkhj)}C0V-FjN@Mtpn!nS`56 zuWS6Du9abX@oOSzF{L&)_9=s}=HxM~KOAURJesga%bnD8S$EFdc6i+&y@D4e%6+)K8 z-g~kvpNP5k_`sa@0}WMJChALqvFO{bKgVarMT@5oZkA17Ps;L&DfDLe)OG#nQUf3n zQac6+{@LFH9rcR@_3lb?t9v;e%dIsuobhaVRp}LL!QG+KK@N8~Z5&2{IOaBBlTQz( zi%`UUMtOY?OOY^afm_(~i66vaJ&IKzxb1Mp7pGQY6E9^A6KLMc^3naYax|0c9@#GG z9dADnwt65>uuKkFMsaN4Fx~Q1i&8e%v!-e>XdXo@58u5g=U~bx z1P`FR0_a3;0L0>=rUvU1vs-T;;y|sjwU_Xr70W1AlH-)Vc{lf~S^uJ@*m0gB9yPy# z?n~%s=L;=2R#>W5Zb^H2iz++- z_K6X(7kbA0JwhZv?hoCZ(z8_ih+|IK-KzkDVyiUM@mrsmu&Ve`6jA$+=$HgTy}8xO zI4|)oUt}}^a8*{@RfzU=XWWEIJ{y;da^W0#myX$*=))$G3Qfl-Y_Ky(m=tIyr)g@> z69nGHkMgizy+LQ0cVjivH0lP%G*5Z55|QqWyqrTL(6wHhg8zRW`^!@N9l*Z0M`F> z9dhxW({1+?_o-$E`<~7_FD{MlD{35%Ng1X)wmCI`Bl zc?}yQas7|h7HO?jdRKQxbN0=BpI21s!Aj;XS~Svw{aNFVhE?L4M8EI;N1^$<@Rzz2 z2K1}&%ibez$|YRl?eJbP#=@?WDRA%`Kzhrpf4pK>H$po7wRpAcHWO}co(v{*7YT&d zdK+*2vXV0*Zi^4Tc|QFk!SElIfSFUattgitf|pSoWK&+q9-m(k)~aXkUO{5*K9MT& zhP*+);M4BOQ#Rh~=)bJo&1*5;M8C!STtuNRv>wg#jO2q|c)Mjqo5Ef3xz#V58nl;s z;J+!`;KU`kNYz@4xNoZ>TnvxUKFgNP^jom=QQ^Q@H~``YS=uhyj4s0Sn#vNh#V@)H z=l4G?qNCE-SF+nIdmp^2l#VIh)gC|Z_0oJs&=EZR+hX1H zYhM9Ke(dvCKkWoVEshe7J*Fvqh{qFegRoQZ-MGsn?8u#Fv@^)Yy5G}jnYIzV0p89A zx5k`2C|0VqiNzRWM8kj@)*T}c61S?V^Jx{sHAx1~b~p=ypm0}@RtpDoT&m)Yy(kez zK@YA=<4|_9{qVZEUG2Y`E0E|#uCyJm58p#lNp(UGpA0uTU3fUY zL5e#+e-)-fs-Y>+L&{J@ab`_XD(c@jCvIJ)|3Z^(f2p!;BgK|%I>mpJ@G60%gM|kt zIUNby+`75bfN}c6T(jBW=Ft=qXbAu4-tpSndM>tL>cD_!;UdL6^hBMMl+OaAnH$cS zDw23O-Jn0kkbTR?MD>kp!t*{V?w61(9!GeE_Xi7aFt#FuWzWT9+jQtI_8XRF(Er_a zMTz1iDEhZ(iu-@}L?WBc{h}^>{YJyHm_TJJU;>@a=Z0v6z~w!3ox|0O)yg^Kprw-G zp{~OvhbR}W@W3>;Cln=An0}M{3M8hTA26gz*zYJ%L}AEpkAJ<@D(1lC8XdbQa`V_pOGCv!9L1tzlLm z1YwxHl?f)n*@p9ba(RFYDZOqg7T2}ny1oeA@yYzH=seAnbH&TWqWRFwD*O3$(@USy zv2Bii=WTX-qkUNn&a|HhFm+la3yJ;8!OEnen`nDgIKJOQhFBuun%I|Qu|N!dN050k z6>t~vurBP`Bw2-h18d)PwcmXBx?r~jWK+IxJz@B&=nnz8CIstRe2wYA*?on&+=~jl za_4A*obb7}BQLRMF)8;SRUo-!yw!x-5zK;ean`TXJg=Z3SvGNT1KSbTE-w{A90^fv z5Z%dtRQCHjb@Suk?(+2t?b)hHY+Ro#vfwc6_pqUXZxPyzFDG)64!c@{ZjQsSd66txh zm$8~ZRGYf!uafaF@yEbc`n;vGbL1`f_qazx$PijEugRAV+q{w5&v*bk9$kPS`Oy?Y0C@32`I)B35G)|Vp%{P_WGASa{z6+!1p4IxcH~u4b5p{9 zAjUhhI`4#!Y)@qOGJkoZXam^2`*2b*AOvWIOF}}**;!;tMW+IGE$%uAtW~4kIC<=M z3REe-hr$WZ-fvj{q)+~R&d|$^-1RztNa7*7kuIG-1VE)$SI{a@?65g5Gv?e57==Kg z%ln@ItKeeflwYX_pYgs?L#KZPmwTb^`e~IK1!l6mw9`U}TiK72Me$QcwoAQX#CUvY z5JKksX}}=x!SV*1EM|oH3f~(}Mb;vBof+-^S zrC_z|BwQ!>s^?Oa*-P&C6eSL8!g~lYzJD1o>Lgpj*2^Afv>Fwop6!1&vVKa6y(e3iyxe!cWM1TZYv!?AZ z^-w#^=$S54!l1yH&08TvE;cj4-4^WV%+6mWg>DqzK=WE(=n;r#c`340HGknQt){%3$w`+)GU$o-ANEoRpdM?K{JJI+m zUF!FV;;{JR@m*sIMysYCzY$Va-rj$AeDUGC$=|CpC51!80iR?|^cSX&sm`a9IZcx) znzDmGHX|jD{u29XznA18B*ygxMwz~ zvs6G@G>!<0&Xl&Y)G>9tBM(;`Z9T9rcM z-g_wl1t($t;xrx^d0-TGPxzplxz2OeReB^5=9SP8e*9sO$R~fwzcosFWrOF0X0|@3|3N|NN;n#RMIG@gp}Xb@_xg!TIjfCvxvE1ZUoOT^FUyMq?S zs>7btezTbCfUWxk%`UpgLkVBF{X)AGd0wSY?WL#MF6IkanQQsGd)YOI{+Rkbl`2`r zty^W^rgb~FssT3`_%7d;W|f;NZm?Q+BdhC##nSO43&=-@i@k^1eJZ$AC*JZ=F|tFt zehL#TO!e{5G7qhbXlNjsRm>z0JO(KKlb1UsMBY@^%=a#BOBDdzQ@;40SHvlILK~6J7OvF)q3HJPGa_d0DRz8X{9Y z^!{V6ulLv0%P`uWodWos*}Jv7{7L~ll?XG)KC(*Hu>lQA= zaO--^>5E&!<`m)Azq2>9$vu?CH7o0BAx_Pl#4;5dzua(F=j-c&gd^$HIJZ(=@^Q=@ zBeRd)A=sZLKbiM94oXpU=PP%7Eb<(s60}Bl_pK|V!p_} zSINAYWR60FAPVgwxuRjC&_{L1&N)Q4KDZjXZD|s$B8Gn>7k7OL+I|fmO%c#%KNH}X zi=&-}EO5yd?Md_WNz0V>Oue}lcJi%ZwGtbs8fAF_ypiurJz{vy>2NM-D{Zzwekgy6 zCx1fsu|i-R7)5Tl*wxITEJE-G+pPJU+)F*G&zVG^D%iynE86{CB;l{x6j%Ju82FhNZFtwF;-R04bjyLW(JqF(V_H0-I2oQ3y?}W`F~UmUS!r@Y+pCW zA`oSdbr!;Pr<#scNaO%`vT!i=L)9FpW>KFlBk5Y!5 zRN6SG4}o9LyiI8YCSDP?bRCF+Ul;|IjCAU{*rC7Phs%7!OUIgS#95Kv|0MHIzE2_x zfWts_=4IfQ8D+BG>n&*e$Z@;O+0J#_@MqU0xs2afFC1iL;N}1Rr98yP7G1=bY^gEh zcPa5D%sVlr+KEp+qV!Ow=NALWr3eCu3K5KxBHcyqSQh=5_g2;?^_4@DPt2Dm-~o)= zYGO6e@kwW!Sgb<*B};mZdp>EIy6g+1{K%Z;s(H674hmCIBYTZ9Enr!zHoZ6;H&8D&a7Euafj|NS2of7ai0 zGYy4VNo5n<=x&_fimLkGKO{&8|INy*T`ys)l&)FZ#g^i`woy*}{+&HaD&8W=lBm{G z*PthK>nS_uu5YvIPIk6E^RBUh+T}@Z*ux>6>f9h()AJ?(dqVoq@dD!^W@Hy04EN;x*5sF=doV{Ja*y z2okh$MZ2N2GdosD>~+(-NUGDhm7ii*=0IbOWC*9j&w1CzC+Q}C`^dM_b&5zP%eY&d zXxr9@y~rBcW!E!G-D$&eM0-C@>gsR;H#5&>LadLF;w0<{OrgIs1njvwO9}5XyX_!b z0|xRa1%crI3ov{U{Af)@KlIC-xH$n}qEjNH`3#YQeCb?gf1B`ZBkP|( z+N6r0&ja}vx_3tf&{KgDWO;OLjG5{SNA8a)YsLSmi-Ur77`^(lH;I@OzeD@omv-4#z;HHD?NFee zxu-zsN8I!hu`(dwH882?&=jZuHi+2z93gdKefkF67RV~hu6S6GdDpo#5I=rF*-q zCE2xS#Px8utv08pTE)xybbxMOK?xuW%buo=G*l^&D{A4!=f$qS0mrP6;}YvXDre^x zv`rVWAYtP*WJ9|g$@gW}i{!$iideNf2xihKfv3BfBeE58uIi2K!~_Tsgh`*|c;HdV zzQe;U%}JgPFNdw31!=!ec%Zx?EKq6xdNNBiZ~Tkb175Z>%)k;aaQf1cL<>kd8spEC zu)U-x?6&?reN(_oPq;Tm!T9`^y+r;@nMBpl^%%@-_kd?1HzYiM%Z{=y>G|a>nLC1^ z&0n63{ugWdRVn+GRr`Ad>mO}?L=oWa@gJh!pgl3mbD5aK^3CyskHTz z0k^fBg`eI=j}bXn9`vzq7v29RLN$*YQIjS66Ha#N2*KE?3IfN=Fsn+u|JQZ~l6!9d zC4HXGKYhZvqp<6HcRW9EKYIQs_6kxRS&8c56aEFRHrY9;@D5TAtL3MztcsmobSTR` z_z|hVbyKMvJG5Hw2IPL}ZbGX2c3D>-OqPEauUurevHRcT4}naM&B0kDMY313Buu>H-DG>gfx> zdkKTg76P4H4Wv_Q7X53sFh<4Mxx|qh9yPb@!L1WqYNAu+cV4#S_;pzMf%YR2LpKdY zA(VldNI=gL{sk)73RDM7g2ag!{6gJnW!wvG5*V+bs}FXX3tGqS+_k^`V5ymkbpnGu z*;&Hd6N5;sgs3h7_5fDW7IWwlM>`h`>@wzw&g&_ehDOQS@#M9HWI6qr*O2&Ww6=P8 zlF8pnDbGZzT`NK{*rZ-@=8d-^-i7H zH{|?P>p)eA(Zv^p+zPP1o+Ut0Kv-hbfLCBzpL#RvCP<={XN6-IIJ=TNrOL&}n`}NRNgc2r7#l%H^Va8h<&Cjl5SfxI(_M{A_eoK<|0}t$Uy}g>$MX0gx*E4M+ z1rzRI*FGO?SqV)Rq#49~OL+XGkLoVim3A!imI+#b{vXv_NZdcFn{pX4UG+**pH(E} zyzNuPfuY5s3>5pHAau^j@V4{Zi#1)keA#g?>a#L@%1#m?igyW)s&imH@eFNVAoT4=AarL z@lYRP>qYGT35K0~QGQh?18|NlqdMV?f4OaAc8sTPgH{`w$L&Io^Cu!jgyhbR1lqkG z?>2r)=&gT#_GvX!tr{(hn)UkS<$JVQ{L}-&t>a3=MEv$9%@Dm5v(Q438zH^4q&0{V zs2$1qIgOE>gly)U{qcVjH zGE#*QDD;*;!723RRe#^V?Q;|iR|o=R>K}AwHUlLG5(p&NALt6K=1w`s`l1H6LJO42b}|*DjM!cdXrH zKJ%W)Ed&)^RlEz@J&QD#PR-0ACP$P_-eKhI9cwpbbpN$&;eT{ZBsqcW&WoGs5kmgo zy;w$v?olgiiby}-T@MrIp1W9RCzU6@e&sAQi3`j{46^nd4ki>u(3I}{z*m0eN$_@1p&-sro< z#8lQ4+X0@6c1Oqg67`0k4^R$pJ7;eugo7{xskD!rufIn6NfqIQS~ZDAZJ0XvOzsMg z8Pv=w?0O7-YG?uGWn66X+Q=c-j~8)zA-?5Zh^foqp6gP(g>PjyTFi6yDR(R)D#OSj z5^ul6YE;A&k#&7*CgVC|!Cj+8TPMwL@BwiEa?Eo&b^paARz5(WQo2fvitx4X;Zb>z zPwlQ(5BJ9yA5VcOvM$nX-%CDBAQ8%)^f2<;*}V$HnQ=5)_9Joe)}-fPjPhf2s%c$` zK7HRvD$%-+Vg0|q%to6QBl%bZroZg<6fS&z?HNtOwf1vM7_v^jAlP+|eJNFeuaE2J zf7`pYaW}Tjm?M#uE>2D=syP-u3Yg)7ur^?br#3MkKPS}WZ?5fcjMfi?DQRJ5c57(k zS7!J(Ubb?s&Oh-Mcsg587>WBZs}LdxaQNhw^_5-&slvNE1^Y%*fgRJor85>Ob<^|S zK^=kwfruli9XOS@?h1POTv?_yp8HJ#k89&y@`+y>;_GHaTE^xuRaXCIY6&=;Ev&fi$Se}F)sx6h_6&5iah*<01F28!rTu=w>)x#lEf*BNi9F~;*- zPqazwbMqlkzfj#iNo-3Oe6>RxF&j7^->%Wl# z8O(;}x-HsP|Mr=wJ6B&pV>GM|e*M=YFmORg@sLVdieHt&Bug`Ji&$+E@6Z@t+h1KB3 z8;~m*a4?Dd@%V|XmmOqa(tMHD?HhO?Ht}TW;}hSkf#x!#roPbmxg^@M2_stVys;}) z&mv_Mxm>IN-Vl8Zm8^vd)%)b0t5h#Zesql)fcd?sn)ZG3}msjMvg&#&zc0upe47#)?69JP$8vMKGTP?yK{+ z**a&#*o&CPA?A)je?>nZYRQ&;2+rh!8R<2SA2ZqZ78UQ9Le7Qsn4WeTBi>(%A2ld@ ziAHE)zs1iEc5|!#Fy*W4{25~t(#T^ktXSecH!WKU3HVFqJT#2+k$uS}G=grG$v0$ykb7!JRE(kz))Vrk|mZ!=I;G^V2E z{=ud`Qi3|P<5yYKoH_CuDae4iy%4k!dOWORHJA21)hAoT#>T5h+SB~p`3_FE9q3SX zwCmt?mN5DIz>a`}%rEIIN2>0nchHSTa!gNwzUQj}yrheob4p`E;AzuOSx|}T{L|#r zn6_4!O9TItLl-Yb+i*&q@78*s-b8kF(|1V~P;n2j&e%5U(!G?xBN;%}zChuPPCouxXOV@rzkb4j0MOPW|*N^@^Mt!Jg{aA;l322AJ3Cz%h0 zCp|LsUIXzukCBT?KvyO@=*d{T@Z2wT`#6T9OL}QR)cEl>D9D{g)mUiML8;3KN z9r1M6g8Nglu;9XN4yCtqFjuJEAA`H%@jOzrUgxjZtoXRieP zwdLSJ7hFB6h(|iCekQA8-cJevIhOLbl3)9@w)p&z>3;h3;+25onah@+{5fMhPmH|Y zqnigE?Rrq20n2Q#MR0Ji72mmzsoX!Ru2FU<#y6(yV)!I9D%VWbeR1%+^}Tk8L2@AY zCPfu0k0+hHX{;3wJy>Ajal`eWe()nKwRvB})M|_Qgx_QdETlBQC&Q+IWlIsrjk&+WNNY|_Y;K*op!w6R(3GcEtPF|$jIshkyd!0F29mVDvgfxf*({-E1L-V zPVy;tQvM?-KiKqzzP)~J^o8TmoZ+fLTjla6OymW_MN}=EffUu9T`N6Wx~T-3Bz}U) z(3!_*3E!EOw+izs?h9U2cc5O&n%TyJyQO9}aLl1~dRbSN2I09|9~QR**a-45@@e33 z!7KItQA3smTBniCdsGhx(j$rcq`P9f3j{DRWK8Xnw@J4^O<`m^9|;09blpW1;RQ=a zR=uB4nX-{Ix$sK#p6yHf_>+ji&{qsj>Q-8CG9LlHYe2Ze%-loJs2%0qOm0{8`+E!y zpS9jJIg`8SkdlkZz>q5!V&5J#U;oh-M$DNYD`J;uDU%d-`~>nALIGRBIM?$NrUVBp zk4Q&^?8q15ur~r^KQ*|^QX0hTx%6hD)3E#DK=q_EiLX|4=Upj$C~IJ81Nn>W*-S79 zBSXq87yj>Oz>xwZzxt$VqhP9^%@4c}C+n-g|DCs$=sXQG8i%WOU6ia`sLSk8W70fsHNDOGx@vjVGkyn838N6bZ zgokSp-aAxo5wh4Mt7Y9wtlmbcM3Q8d3wL>P5h67Zda?n2DnB1)P`0$~+iYceZKrI> zusH$udqYK=muW_kHZC+iPYIN6rAXk&AVQJ#@>N%(f=4U)kJqwp)CmCku`q$Q$$`S^ z|Bvdw_t@5kf{$nC#Fc%t*qzC=-1&f&qw-R z-cK`D<;+FiJH_=V(Pm}ObCK^K!jgSoPbXt1Xoj9%e-x?;>y?e8pV>;)0>o_>BHZQI zVA-t2rzZUU%dvG;%VmI()T#-TSyVE&;80Y%CGBWt&U(*2xYe`F>HN~37nt)X!>{v% z!ZU$*5Fb^-@o9Dk0EXU&L6%K|W%YfB-kftd@b>Gox*0kkmU^&c zJQh_$7xUQGd`Re76Xz@dopq4n_J)~~%Fd0+^rVJz?;^xq0z+T3WKo_sTC2+0k}Tzy z-&L?QtJ<5zdAMF5zxZUG<)%jbHO`7;1RD+&450;>TYwm`5*9^~A?aw3%bJ%!co8Ol zY75gxk)Ey%7d%~OnT%5`amNElKS`fFAGd{M3WzKL{~W-9m+FiAjJ%}vmHob1-{G=uipYqsNvNt{8G-f7-9fjS7s|K%pb5pwEfjk@ zc+{(~C-nREWj>*BpA{1GFY-h#eyA`3+}Y6(grz5e9(aI}0Vx-V(RJ68E%K@=CwtKPqAA5v5l$GtY1!o_j1`etBl^ncx20 z)4)hAE#Noa~E!K9!>^L$Wg0hTqM^q$ulssmk|qL zc6X#ZpRed}ecVqAX!z8F zsK&ANkb%p-(HJht{F28t<^~^Z5};8}hq8b7jEda}&OSBQ#pkbQ+<#xNARWOm@TL1v z#ejS2MK;L*XGy0Ggdp;$8dFBh!(}-~XPyNx-^d2zy35F`TuSKWhfS@uCATo`Qr#tH^KSsAT*6)1Saj3&4ePF9b`1jId zdKt=bfE6jY<0T-~&NMYlJ`}iraCW>6d8YRfV`Y)hQjOXd*7?$C*(Jg_!R*Fb9Q_|I zHt7$o)DCWClPpaT)@W);a8`cy*}_2dxciE;^Bd>l$Ld}Jrs-eoo~wK1mL&NyYrdd}DF{xw`GxfX^2aff;watht=S5!;dv${fZ2e^#0 zTS`_xk+q?jw|1EVm2m)1WOL;WLZVsS5}4t1z3bCA>iIa(e#$v|D7O_LsQELXOYJ}W z1~IFPN#UG_n24`Ic0NNGW?gnPFZGo4zBr;=?+H+`pbWP&$FO>ZWYgs=6~9*_Rg7Py zT;2rejx-IV_~opfw!5`$Vz`RX*2l7mMH}!8FBS6;%msj(GF0a+jKFmH8i%+$+v8A| zm+ppf;Wwg^8CjW4GV;Lp~X{Ao-g1kIOjEq%dbwaz!k8uF6v1xl7$H%>;H_ zXgNP-xYDNr%&n+U%rE>_qbY1f43)~CZdXlsZom0(Og1!?pl_dTE|fhL5|Ik$02ENIp$2}wsU7wDiQ2)n)2N>G zi>z05%Ldexy%n9?UrVIKer)?zgzdT9X{f20s@)#6tHdBcKl=d5b>aC?di672s^|kB;hd{U*-nr8j%$iIQwm5+Z_6F44ee?*6@# zX|NL>z>83qKUrj(2qUHhstH2JlhH>{G}rb$HsgjtpJS<-s}nbLH98}xmgG!39Q z({E!RM$eneMXh%5JV9;O&Qt{kOF6lz4-AC;j5NgdJ5hMaFG80dlOnS3LC;LW3)1B? zyqp97%x%e340;tlZFJcG@+Bus&G-?%a*Ko8f|V>wsw&bcMTlYaVC~eTh61rH*Syol z8J_~ZiIy8BUIhvFZ^hRoy_v4*fx8!wL8KuXZvDtKz!|p0A(1D=o@9S}iMML#zKh3< zE-ei3uDo3Ra%(SqmF@?mM=ZRc2@mfM^4Jeo($mcLR_H!?;KS-2^ZuTbQ-x$GUFw6- zDLilbPqzmN`GY=Ugn%}`k;rw13^IUQCj5p##_IC-fc`DDL-u8Yh7hY;06j|V>+QCxS$gxuh2YSL38|U=i6rsQcK4_S=?p*_|EPM5 z%`^D12J~bf{A!G7>5X2erQQ?yA;fA}!5rzAk%UOVKPp#2pYN#{*mND^qDO zIL-bY6#iaxoTb6PmhfgyHat*|W@JWKR8 z#=Mx=-9cN8bq%sL?9C0!Kx=-77(*Ft#~58_i*A+Oku4urS_*Bp549x~0&oxj#$&() z3_^qnd8q4ZcS)Tmnu!oJf(8E5yq`Ze7Z#vbq8;Zlp2tzl1zB@$iJu5a+zb$zLfJ?K zsc{gbqCDYO0;W)S1F0}D2ia%&oEkr%tjdf{&H$~nRaUh%HC^W6GgVq-K0@xLbFTU0W(LfG2H0*0+rfmzuJQ2;Nt`!3IW^l<#fN?dT6if|6B85LOvnSQ4x7$c--ZW`+e%MZJZ7LQlC9}f2a zw1ynzJ|KLH_4(PShy11FxUBdxA(;ZWY?v{CpZIIxoYL{3KS2NU$<+H1c0ARf^Fv-uIl$VHIr$sGe^J^lNV4nYYQ2W%9|TTZ2+8Oy z3}{6-9Rd^xw|t++5TrCFq$DK^1+}Xz-V{mEr4XTC?}k3Q<&*A%30HwE$HgtNz$v1L zYa}Rvj_61dC2(}!L*1gVN_8trAp{6?7Uz0gQl%2vuVSYr!u#d_7XQ$-c^A_GD~&T6 zYgNgzYoDympkKVbro-sl^W#S`o{kM2)-A>tOaCQF(e3vIl0X|qP@vGi#*1~BplT{U zuj8cxQMLvQqe#GhDzIe&U-6e(Nx$>kY{6T&AC^^T(fh^B=ZD|-Ar+r$%x44(AuJT^ zSaGRhXASQUUI8}R-ZRhacWPq6yGGc%YJ#&!2gJ+9EzIojao><+MR^$`w{2M~q&X}R z!tbru(;OERvQX>QejA{JfjRqu;T7_;ai&w=1P4xt(a{Up%5r)tL4Y)sp&GrMbrL zzaJvh5PI*?73OHN*h(BD*#d*Oj$&+QAX~-*U({5i)G_$n-Z13bjvjjA7wx4+@OG6k z-AHp=NHoDa{!Zg}N{_Hw{JO;{(BY=6CQ?$o7U|C#h zmR2fDgPFChCl-KW%FBp7wlb%S{@qnp)T_wy&t|9bCczJ5bSLRj8j{9p1KmC|pZY=I zr?_29wWMWaR0=;U!KEV4k$b>fr}GiIr@1|`5S9#$J3VSW2V4dO0_OKc-&rcv5fkk3 zxO1If@3`bqQ|%^M{p@)>uh#>;pZQ-OuW|i8-7n|Z9~_q?mB$V~t*z7=AKx;%Q;+~n zRrW8M;U9+|HzNS}EPb~-u_QOJE2rW%S`M(zDyHW)c|rPDR1wkx_kgAyjCREkMK8z9y^YE>}y_FYD7wKdGH8P5W$p zzwoS%NlIDu8$Gwbzb)N6mtPmY?1c6>F}D9gaJx>c57#N%J?rPpr($2BZ2^cj|Xy@0pub(`IrPQV_UWLC+;AHHb zF;lPB6gptOclQLsfr4HzcgtI;j>(SBBzf-Nd?Og#!ydji3u}RXY&H63b#*#X0-(J; z_`+;P1m8m3OZ69jG65npVa-7%kAe=LHjf{*(d)9o5#L?P^6R2@fEfC22NXC{-fnu~7h=R82lt#L$FS!+J617-r;7RgC_2n<8d*{2y#?k5 zyQG=cF~rDpL#ngFJeXW&A4adA&u2W{zt7B%_~;(^ghPqeN57{KkkMhrd7Mm0Vg&XRpX>=kiwC(61bK zmTc$UTI8EV*3*97zDTk2$PlqS(AnPu`DA z@yX3TEcMg}yzd);3C2E~Ikt8w8jLsO^X)Y~7Kjq4X$Wh50(w8O7CN{>58Eyh3HfqQ zX7S1!X@NoZanp_X$X|(Asa0bPIbq8fGMswQwVT|A0?( z2;~W~#tQO=1yqd>ear*3n@|x0jwMD1Gr$>}p#|9?y3akSiVC~&jq>LoRjWz7NdIgX zlr7gDZ@u5y_jFR0iMfkAsXf=f#L zh*7}y3e@lW9uHQhFNUtC-6O9*Uu!u{^=f}h@Gw%7BkL;Sw*Lw&hVB)~FWU-=$!eKs zh6YX+1?z*DjytwnKr9vp;kLnYWyQM?g_kpvTwm;SLgOU3Vd;YftlSoFDyY zYH<0I1bvrYpT_TsbzzNfbEL3N6N|VS7%|ZvZHrY6m?PU={P4`0A$E20KY&p8VYyTc z^O1J*&=cR9&8qGL?R-hI$5dZ*dzGT&e5uae&?_q3fjyYdDt8glO8te8&QWp|0+SS8 zv%kJ;QyH{zuy=V`S8s50(rEcNvf>0 z4UF|WJS}Alxv0K;&?t)%xHA9u?0e8H9$wBF_0y{-)WIZ7HHohdxEHl2{c!Bh`~DW= zVxl)O={6?xv_o6@vXUK&rxj>MuG}OQu2is-!nEuDAo%3kOX^aq zd{P%EnyvQvtXl#lR@Hw6R~u{Eb2@aK^zp$;NLTV5n@4w9@f%O^p+8mlu=NRqS|l5j z!1*gdCF4AG>O$&BvKf#!p3)0~e)rg?AuD+Of4ETruF%<)riL8U@LmXa@DCEC4y_m!nz8Ix%2i6q_S*s*DL zIR!gP1*KLQ#YlO@?#gy%e_TMNzo3&Vqzr)h_gd+kSEN`d7!>cm9H~{Gzd^~pCYN==&b2gO>)fQqPhpWC!jAXtd6T*!mv zAHGY~b11_Mi45eqHQt5fE`t95_fUSD^+R@+W?3J9i3Rq|FB90SZWBj|NHg+JQkxGR zhokEOU-6CuI-VOUhB%%RQj$ILec?RG+^V7OfZJh)MmkM`b}?!w?FRLs(jU5&y&Pv) z9zvJ&J$HVPtu5LtW-ooJAzpN#yK|-gYH*&ts#*Ig2}F>`VRbsP=*jGO`7*eCMgHHH ze_5d%^k~)ML6L6`AOps4lr_XPLSYxi*S-hI)uonJ20Z(|evMM)wS8#qY?~%TZqq+1 ztE@eA0Nr1KTZnfAgHCR`j!DcK={sAe#pbmf%Yv`6vT+}+u*u zM+krDzS;A1cMEnX&;h9y>jG&=#qILpWr(w+62h}B8C0~&8@%JmtGJcnqoH;EWTW;R zn&-mC^b4l(i4&LNumUqBMB&Ow$dk$oz!SNgov1gW-<#$m?y{e(Q~~j&`r9r&OQP*P z(^X-`Dra3^>idY+%bO(yZuvUduyj5e{PyYZ<@;3EsrJ{cs4p^)P>})Rm2Ct}+)<0a z;=WK@e2S4gM)_5x$4ABU89rn)EFlGmApcg7zKIU#12;U&uGbq@Q8E;suP-ET&jXjF zIigj#18N3Hb4ShokE!zvXY>8rIHhQ%Ok@d!FaVX`q$@NfP2yn5t_jjs%L- z5-&_>cY}T);x#DAT4Qx%B}zf@n<;#l}2^g{9x}EWD3Pi>cgWqvQ+hbS|_a7AB5B})#TUd%1qj5aWI zz7NR|nG4DudYCgxJ88{68qXtyIz+#hp!!PtJ3K!7s@8hLGXPX2`G=1VyC@aFXclrF zy&GCrT(1^yebzu_R1BEGv}=Cs2}vc5zqjAJznG!e^gf`*-h1z5Cz)D|H)0&HvV}Hcm7O{7d@%tN6Y*Z z#C5KAe-zyplj>}c`W8;o1Bx5{dvw>62C?++IfxeiL0+Amt1F)|MU1M7&d>~r@lWp~ z)5HNh_#+h!ww;#|{b$@)3(5vgtam)~rjajC{HMsdEN_`tymfu;#BpD&jB5!^xLpQ#UVrp4G#1P;gnO+@w?;-8AFUUJ>jUYZlk)F|&atpnmT=2Z&r2`S_!3 z@6qC5J5y1Ym`Nmls4gHqg6V!k^0Nx-nd~`37oKcCp75v*RvvE^H+et2|a8KVJJdm%8U8W8E9=h-H{}Nsb18% zJLy-t(`2ooM5{7XQs(nh&8~6m+BMA!D*|ow-eEiTU04zA7)sE)(Bm>cTm46 zQw!?)fN(qSo+Hcef014KWc)_@FprBxwGCr>r}c9Dr_*cz6h_n>O`G|JU># zAH2YH848e|_}|@_Q)q4&X6`ovxMaJ6HzmnQr5_MO6$l%Pxlq)%HO9BQr(L?hwo1Mv zIIve>N>!t*w}Wm29pnDNZ;VT=W}SJC`5DgZXukxT4{Dy_@9pqPkM??9N78v^y9ipS z%REfFdWg&bzgz+DDdY!rt`1V6K;h%u}~IM*E@+ zA03p}KQ-EcH}l9f-cX?Kzbn=ICWvm|i)HQvAFUFwI@JOUb+Pjvt;#{Mul;}4)|UoD zO&Qy!-*@pzl{iG{_?i_b4|40q1w4Y9hBIXq8&^3_X~OMKIG)TDRZ)FEEo%XD?sCiN zv+m&tB4~_Do1#gio4#MS@v_4&{AuOA!sX57Q@&I?nGH*`aZWcX`C=Yr zJ}H1xOmk|_HRc$1=i|$;Z!a>*--oz5{*8sd>D0UZ4h8o*EeNDL^$IeG>3=bF+vB_K z{Ysd&PgaC7=a^D$fz--i9{$s;1;67IR4D7R_Pn7j&vFzBWAUZa}M%at9SE| ziQWQ}2X&a(S_xMAr_-Vwc>LtRgCmKQH z+AxK#?%UB0fLF;$%0ZV9;9lmou7@w>b8>zRLRi^yGHv`;$|wT)cxTzn!d3e1n6T80 zYd*~~vjN*j?E4c@D#?5a4<|GBL0VG{uCpXlkBYw5*SV-0zg_Kt!KcKJ(TggtwGqMo zWzP7=*tFEr?I7hZyLmlzj2MrAM`P3m#$xYwOz6k12EPSO-8Lu7b$7#QP$+$dos!?0 z5)OMEQTKZ*mY20XgbZb9kvsGfMAAhk~T_`%ezt#wc z(TpMu@464KA6D-BElzh7MF%j75cN87%Yd-&erC$4{Jd}l0=g2ygFCYfy*@n6+52MI zS{KuOch3eScIL@lSZee>w^}3i$F>?Hg{iIev3T;5aUVLc!09TiJ;^XXo8R+Op`ujS z49Fd7cJu8ML5}zrQA>Yj8E%dui*h>aLJiY7Lpn;8rLr(S%v$#v)9!&Ge}d23>W$4N zU{zk)P0Kup{Y5(GIOBplhq~h?G>G>tke@KcEOQ`teKSWwglHK3bv;^b&`2IAC;g*9 zAI94f^r9sR>j9*PN-%fpoFv4 zma2a?h+DX@F=6szqi!IV!T3)go>rut-d0^@+q|z|t81nqK#2HM;nYKFd z`pKg;6sio4JK(fxg&(_eDvGS?^jB%kB~i3D%-PhnSli`0b(&2{&K_9TeRK-=srIb! zb7j7E9E+zjcIxMdC!bqb8RrY7AxnmTHD1+_ChO&$3#KpBXMvkWK_-Q^O-j7x8qX~5 zxVe;ptwVYQrhOdSqt5T)TkAy~zSyUGQv7?9cYn@vRynP#vOVXY#%E7UZEs7`^4khy zqK9>Bo_B1GHv2xBrlihz1L;$?oS)sOc)fs{Rr{o{;Qmba>bOwS+E`x@J>zjT_%qMJ zl~n|-KsYH9E>8b!O1dKVMU2r*1@^G>>YvxSMgVpZw|n41=tFXVNdI`N_IK!OCLGP6v(cdJ}>)v zJLlqioe_^o2W}*-3KMQP%uhL^n;`7`iJa{H8H4R@owO?H8l|j zzY=R$iXyi`T(W6mJcCQJ?+#i^^H!_u?v_zw(W{n5l>dhD^3uE!ewfJbmHe~1(VFnq z=yBhKbK&IZj`{@Ox2lDQhHj!>RV3B3x<~SiLAtDj7@Z_7-pTX4k2iKceW)A_dKz&y zZMM_!+Itzy>24=9WuN^TiBC(d)#UTw@92v^EOOGk^>QWn+sHrjV&)rjX!T#QBRvZ> zmB_~_5drGRnrIKZ?qwpK6Be?1bH0D0- zim~aOW)HAc*#690%$szEucmr|?J}->;^bB3ZV|+p%GfnI@cJ{2`kvyMQ9zJ*o%==q z;;&L1#xmQ{SlxdcUW{o z13@9GVL`V~;B)^LoZAC!W1|OX^bYJq{d`>L+ml!x@#HNQwymJLe{1xm7n9PsNIug) zrM<36eu>uStu%$a{jthcxE{b`-!3X1%|v%Q%GmR5DaW4&%7yJe*6ZB$e?c1Wf<~)p zC_XYrIF(?oAyfU2h;)NRk$FW8P}Io-S`RBa(t4#j>jS=r-?uU0)Y6*qN9mT;t z{#K~ibcvOM*t8^-faAA!y&D#rGXr`}2A!{->r<~YA*b^$WeADoyTe$w0d(fhSXF(F zWPl0nFpy$f+B>cv9?J7c@vHQh2%#6ep>zgVKsghp@uj_;y)gf9`l&0-M=kM2^89yH?Iqu4Lu&|qWamp*&!XPegiv}uIk{1F=h*H z3077aZrgX5{%m;v*ByIZyM;*W3tIB^tHhfGKfF94XccG-a$CPc$XYAngz7Y6Q#yDD z>zYRJpiZ84kxWrt32JA}2YchEBMu;TU4~g$U=KP_8QbDwhtIA%A;Z-lVB?ybUma&m z>!^dpUqF#NQ)R&oLx>x}D}7)Nm=6^}Wx$#yAJf*-$!LuZ>;?@>o_)Voo+$hS`Eg^& z;>%67@3a$nx(TE^tB`I5ehz}-fRFsXC+908rH0qTUepCK-+yk&Z}PK{!~pMwZjvyL z0pAf(+WGivrfhu_14Z~=u%pLxysCnfzYE92<}wdfcff};+Wzue1Q$W}vAQcFTW`b@ z(I=f`{Tx?KUeKVJu)N$%lGSZL0@s0?8c3`~c!tYjGRGpxfRMP(%tEl+>^qf9tW#C2 z?srmKyi};l6g5NgrdyK`2m(7c>p7tWm*2Nc0~?2pF%q2C0$VW%s^GrxYeHF8Q~&m+ zc;7jtu$t*az~1{Vj?^1<0q1hAwie&K+4 zOgp15K-c8OO{tZgLZolWz8NX(uKAa{e$)qk&(G0CSw<+aoY)5sSqG-#J8cbhavn*0 zZCv{>wVrFb$RB!6ix0v6Jz+QJ@N!XhmDFg~E-`%KF`8<+mq*X-U}L!m5|g|EnpyUykLLX@uWQkZDAOR04% zc$va$+Tcytxb~7=bX?_kG@*P&Z@w&5<0UL{W`oPwUr*3a{dP`jV4v zsn%!vrEdnmm>rC@=<9$T7RsF$x5YDWfquuXzoDMUF`4h>y3%FwB2^B#KqrxebQt2{ zO-H@c^>+s8GAj#R(q7c`Lr|4@=s7_j@hH$pQGY`nG-rlWKNtLP~Y1MDjN@Y zSzfwFuYil9T(1isBR;Ub1zTaUKF3J}Df>T`{YgbtsN)MRSZR?9GDqC#5tOWA6AW%p zDSpeWHTqDKiyzxqnnN3XAmkzY%rr!*GwoqY9VA&1wDmSdt*}uyw z;jJl(LI~DLduy~D{DQ>ip>{Sh=!63g)K7^=MEPBrT?AbhmG2wLb?wF+VJoMrer*6m zn7Ke*8OlAO&JC4`yy+3d9Xq)61-Br+XmkF-^>KBXg+0>vC8~!#9m$mc!U`jVwYH3= zIt*@@m0ozJ6LDpa_3l@#8g%2m2VXg3_~S(o^r}yr?nqvDqsC1bQG^>|3ollHe^eG# zMNIzZpRl$WM-K*@o|~CZ1I`#xh}D&-(2<$$%c8^pOL<8tTRq7Xm-Jy@)U(J!@sm!x z!3y&L5N_E;zvnah653^2+6`v>@Cy1(|oQK(Jf3v@vCpL|g5a=kFs1I*anT-yf9qM3e7VqNYLHYBpxC%ZCp0EJZKJ;k2>d8}`E==$^g)0Y{-Aw7k5ZAQwLhf?i!-Qk5& zw|yJGv_Us-({1mh)BLHRD^YTpn|C#dlD+ERq6Tf#8GkR>#E>sdGzA6dgnyiRd+rDE z=w7tbR{Vi{p{LeU)_QB)i8Hd=WI}8=+be4RaKo0$s-#@?-8q?dmWbIyjX!3O(ikcF^*d!gZg!WP_s?Ne-t^2|4|$d z`JDe1exqj@1(Lmg`+;csGqV+jB|=Pp-j@zUoU}mvOIAH-O{Z3XLx_*;`<&mKtbxM} z@AUk==>%`tm&0PbJZXbh36@L2&Aq7O;2I2PLOsXqpdHuDmaM0>YRm?=Yk75$t`Ia| z%~tt<;=9Vnh4@!fB<8Xu8|&Uk9Mx)knzu&dsnZ+XhekzblmBoL0N*3j#3P2hU@04>39IcRIggFH^@JN<^Iml-f{0fxpMf=lIZ` z-R1;?pz}$KWirCUl+g zUEuZ(nW70u1|&MR6S9aZ&}V+?*|ng@awC5FUB;(J?gNVWh<2AuXP6__ru?=<(xN+y zbhMXb7Yk0@qzK7>1!~4JtICLD(`r5`$CfQXn|8ScM8zZo2J&*!#Urrc%THw=qA?`l zVo$sK*!_ouJv3t!|F7xdiHR&Kg)MNl|;yQpLT|%0=xv62+Nm4^8gOXyeUl1 zXZG&J)*>L!?k1gZcD>c=y$4wU+f({3%Hm0zB_ziHNxdfCc6Np9cHPsGa1-vll`G+h4Il|4h%A-^9V%|HG}fu1#2 zSfS8x2k;hxR#W~PxvN1#drp^CrS3U?e`^O`3h+a)r&~ISI(z1eW~P&Rdmrzp^SS4c zZ{eW12o~V0ffJi98~O@m;LR+10BS3CbfG~0c?7cB>T}?jgV^0S15WN~FH%(q8U|D9 z>?C_seV0B~bVypE8Jo4P@!nq6F4+0uz3?YSi}Z9)WTh&Kl~!2JXCc*U&Qy1?B=B>(RLQdV0IK8tYoliNtzoI;89*aS zh>!@5(|G?M1&1@=jmr|K0Nk23h6HZ-DY=TX@s09dP_y&x&!q@YH~Gc*L0H}PZC-ty zRDJ*k5u?!}WR9+gV|^Hj1>s|`tHkH2PF^xJJe983t+({sC8$xg9H0=z2dO+Vh#CSL z-jPs4G$O!{@LtnUUJu}x{iE<|HxAjyoJ77o?GR&V%RMgCXu0%z^0V~6e3YX=rsT1; zK9@`16^g518WIx$L)39!VTIWO1i}FX6ZF+(Vaq4j7|)&^PjhCthDqc1kkM}*H8vE* zydJD-s1xXlCqt0*rzU;T9avGKs_>)jGzZDo(6T7^H~pnJB}9VGY4cwq5%0f3}oqo zLnKQ#v`C|A))eNwXv+K;ZVU^_3UpZ-x~W8op2_#Rf)|?Co~Qc}%}6>}i~Y|;9jNNK ze*qXDh>J{C6;i!}Nl!SWoj2b-#(PUkOhRO+mosiR_}T>jmcKu!>|+L`kv{PH#63m8 z8U}q*`C%Hdl09rBw#yPSE8%c+yF9b??Jj5e(SD_USNs9(=>2Ue z!Li>$=Mjp86`Z)%Wmm+5U_bo3$sVTkdCXVrs~!eIXE6a{-4QOjHdJ@@7Z?@=Sgxne zUMjWdI;-SkBwwwLZ^$55PTeDX~>q~EeFeH z!2YB-x6}T?RIJ9UJi79%6>zS{I<~g*I407Jt3@i0?Ph)Cl>3i@F$gq2 z`#8I-(w#(1G9`OUAT~Kzpk*RD!A$2$@jGC=smqX=n{u8>)#l3?AMF`aIM5ea5Gp-r ze6@Qc<)gRN?@mCqy(+8-(X&P< zuYho;KJJ34L5xp=!nlm<)Ttb`Ag#H&S%36|qK@WZ?&gyBt~jH~_6|nP5-6P6Q}9X! zTa4imO8-$jZHcK1x7;8fvj3t>=BE64N7r-L0$wVI+FIi0Sm@V)H$;)biD9J2IE`NZ zC~LRgoXIXqY%AUq+mrhjk{5fLCM_~9{qJP61vlDj?-m8cVpTtR!aw6cn4=+SE~xQk zrN(Lr_d&tgU^stYG8PE{?XqC$@w0`uv8n&Ay>^6kG*A9X-0^B)E89&qhDCBfwD>}%3VoCuakpPeoz2nI19iPtBDU>6MvX}el|2p{Jl9YzU6 z<%N5SpL*Jm`HY|H)}TPxc7qM9%9E+_^ypY0$d6q-5rvmP2ZY5N!&S(HD z2P|l1%c8iu{&98vdHP-BoZWzB*{f z>YF6UJPa&_@Aaa$U0Rx7rW7tsQK+UJ;>Jg8mD-<}x+|9#$pz+;`8)HLQT;DJS6DeI zjCtDzR%Pp79t^bieO;5-O7bd8L4QGAn6-XLcoAF*60Znsmm1t?k^FMr_A7G(OQR`w zdrSK*>P#W$L9tao`=>B1`JCcePNRD~=+U|LzXH%%McTNH>r)f;ucc0H)j>fmUTXeB zX}j32#)U=xs(R$l2b%5R>$B znUVIfF!?y*6ISKHSmsf8P5p)K^WECoo09QG)et#T=wX zs%vMsH?Prrq4=kQSIx2X)F2-3ak_I)Loh!{5ld{x@qNQF@$4o4vVIk#oi)&r)~VKa z%d6hUutwqqjr~(kE&ipN31~RM$#c^kIVeNlt5AgBf!_N5`^D;gxi?1=@A{ue@wht_ zexx)Q!pJr9mwxb)vwN$SDJFHC6)z&0mg4Jz~S!pMn!ZMmy z(^^ZuD4yOHEEn0HgTj!aI-hx_pJi>4*=#uqh??Y4Zlf=z!MPZX!JnjOMjJuOv+?_- z;pl*sqfC@A@sY8{pI0AvQ{&0^DKx?lp&;&nGuSii?)v;Sswjr}fVnP}zkr{}_r#+HA_(9orevIpCUgFyz}H;n%JbitxA6ow zF(25nZ)V-M0a@DxCk^c#aGD$)m%(KP^a=%q%AUp29)aqOC|&`19WlaHm#?^l z)Qg_7;yXDy-GtBKkZ}8rcON^5j|C6=nF#1>ltCS~Kz)@sQEE3-C#z=BL*vG&mp~*W z66k)GAxy~eFDQl@Uw}1S3r>jXE3?m5T4{TI%Lt7D{BwTzC>$bIJ{^{xKs6YlF(sMo zbjh}PBQsptoH_nK3U6aT3}~&`1~Vg8i!}IF6P?2fWO>EcE>ky4UZ1hN&kO#BelmQY zBF$!q%S=}_iK3!5qOYhiE7%AY2!uswBo;_wH9K}1D5k7hHelaA(D%A1a`9aL9D$2m zMegG;H5iZ8vV4E%w7*NIi={!#UHZ%$o?UmZbGS1PL{vy;k1}Zj_jv^ zx*=u)z=Ui@Q5!-odym8g36(LR-94lxzABxn!7sP;c67_gXWk8rb$p-h3|k?#V}y1n6ch4^&iE;c_P6ATQ`^4x0+I@cV%WS z;wyh2LTZ0wA)s_PCB*upQST1iOk)!9maG&praXH^ZA==lH+B*V|$JJqWx>Tx-_{!FpTgtDeOUJ&R?aTd-qLHy80hS7~@Zs)d zgkApYNXYII!zY^j-XGK>nv6c$SXci@d7gnSphF;%H1%&tjqA2rUmjoPs`7fQuiOB3 zl{ZjbDy4+xzKg%4zz8AiVY>rIN%`&@dc$ArLb}xUa`w0#Fi;UjIcHt78@R&B*yzys zo{w23>vRyQQ4l_YeFp_$ovaDE)xj41tWd)l5_3dOsA7EVfHKp!buQPIt|p)6khI@v zRY8JR9p45Xw@?x}Aw+Q!^<=$U8gn$5>F$k%;WzeEJ^UUQe^Vac_BNB|vbk9GefLta z4;;@Ou$*0C3FRdK;hEYd5E@wB@nTwK{@5o`BO4`Kf6&I9yMeMT^~dg~Q#n;PZtzF6P@aO{McfQFSTXASK0{((O*Pmv@bisyEMjcg3+L|L2psJ4 zdw=Kic2__^#0pdfTQq}SASwHhF#NCI5b4nbR+Ij9Ri{^{n-pP zr$PkB28BGM!cEa*u+zE47w9u!k2i%0eDB|ID>x0myKWmSw;<_=)C>M+X!SSmQE{5e zTuG*w@P|KF2DqM^9E)!i-6B+wud|dB4EypBu@M{*qtZ3-j3A(nlC95rB?ZI}!68E^BfXw`&vps2Otz(B)8BXN?%Xv9h6$ISNDKx+I^lz@o^-Vo%X zI6uov9u2ZsS-~3l#M;qLB3z582*-z0&!-x?4AcB?BvUV^MU-3}!JhRB z;;d|8_7p}DG=xq4NX*wBv0)|qNl0F?-lSLx+>({_ByR-9w~>A0r;Gs5GL065B7}X`Pi|#eZ113nbE4NmxGNsjf7}LYNh<) z1O;VTol-t+=r4?MbkVIIb;8=#3mBGM!Cv<#DZu!K-GZzY8ks{6Bx;Vb3fVHi<=j5| z;x4Pq*KGDU)EOtCE_LPed5p#{+wz=M+5V2GJG~Fs$wAUm1J@JL%y|&It`UcT)Ba#a zE3Q9pUFT0xrzUu;m(O%TzIoP&)Rd06_&Nnq`c??AJa=@pNK?>Pvi-{1hbU!U$R%GF zBMQ3v2D_~*{xGJUgA_8MyDuy@S5g{O>9J=& zE>_|JG*}(KF)ASZmY`?jHt{pv>e>+sA*pJCiA+FnG`uEBmLe-X>Aju!ihS%4@@Bdc-}@Jf>vB-rBB zWN}Ydymxw_ypP~xmPp7F`bNYr;IS&a_hij@KqDT|{JH8#PjIL*ru45nC_AX{7@xF! zO)gjK_ttbmy+|)z!S6i4H+d|2AX&B}3)LY=3wnfh#gcq$l(Nic5KW4k{l>xw{w9mq z9dvy*gs4Sm)_>(P34A)HCi;~_{{CcB;ARK!+oP8=&l8E}WZ<*0xdaChlm>>5poD$w zdzmYeSh7pCAB~M1gXBl)Kt7HK7)hI4mdICxbAupZ{P8`vrwg`RMBGc;GIfmFRu2Nk z?6QaD-QK7s_mhQFHQaoX^0d3FTH9KCW?i#egzsu-Ox?C% z!9B5VYK!SNc7gEaIw|%hUlrrLczv?i{cn-;-`ZDZlgsq|Cr~-u>-k489Q3$adii{_ z-3i#gcp%hbL;bX`SCMXG4W^wpFn zG9VjAmOZ|zfmRuhKV{if9m+9WuL`;tJHTWnG4o^nzXr$>KiglHL5M+3;ZTjqH?k~ z65$Et+tsDzB#rUT1Z^K#tsCDbom&v@w-O7fckb~opEb0474`Zp?)8}0tTCeM7<&p_ zZpJo9XCQ4ZEQVf@g}SYFr^vU%S&a8@40~0M-5mb|&(*X{)$d>Ql#MyFVT-Ey5@R86 z>$z#97=TPMmrGi_)umRBSP-y^XESXFgpR$0br=US2jBOv&uovCW9UQSt@SVBAAZcn%-`R7Lnx zP!5^e>?iH)WRy~3mUY|A)GM3>r%ySAs~hq~WtfuxWJD$F0Cb`7&8M7hnfZEw0nv1t z885pCdaoFD+ciKHbwTJK4CR1@R1)%yu$R%>)*=gxOo57u;({qOEdNnN&Y@afg3+Gb zx+z^R>y4bacihYyC+;+AcL}#sOFiP7rW^{6J{!D6u0LMAxH zqEYCVqq8p_$mCg`CZ}2$7a7NxY0nCMG_G|OI8&$@rwF6mvF23ldC)jPlYLoMLh#X> zDO-e_XAI?)e@iyg#h#;a_0{a48p2IcDIpp^WOj$>zzugwJr3&^Z7!fZHsG+k&Qm zW$@s#>@T^ZK{4^5VJ(d-sQfb{dMSjJPxGOe>~G5baB-@AW$RxO$5s&TL1b2P=Oap3 zOPtKOewqdOD(HgYOgZAC&ga_}rVDLeFD;X1`fOW$l!Jt4)o>Pa`HjHw#(M-{7_(gG z*c7)l^IxKzee@@aeDMXRnz^uBtebBXORrU1Ye6&|qjK)nV5D--zpu-yFR8?Xm!leWttsLdkJF=(Xv|dO^7@Ufj|-)6)HD*+X%2 z;YrVzm@1V9e13gch22MrCB?y@2%c%z99xAUTZ2O?mOLIG$=XLqyOqn(;sD*I9$S|R zKIpsT(zj9G57A%qHkY?d<0K_^xeErT!weUnv@G5BBkh*Kda_FUD;M_Ais%52w~lPj zUs)XkVX23{)qAWXD#$?WwNfdh%EL@!p>R(KFYjU8P5`fx{uZljw8w0#(VI?z$v?e1 z;~A$EOjlh1tLvyfz~LL&HTNoxQh(2>JcFu%uoYfYT1eH^Mda zf~h%CQnJ-b7KxbBV~9|H|JJ=6Y)_5XDsTMNr*SysgXGm*lOS;ahZ@uU6+nx zrqK`W*MHl1UlfYp$0Ln!H}edn2ZY+OgMAXHal1i$XSW!J`Ua0!5-^Iz20# zmIJ#I!@Kx>;2E>;8j*`*-)fUV3k9+c6)WgJaO*^(3{mrn39ZhnjTEAJ+56C*c1P5O zZyUV15UU15tA(zj@;4YPvdXNL#K0TTA3?^%g%U1C;pO}y#J9PTO46;eXeKj;&{RwuB~LJ zz>U|zh7pq)*8S@>_bmLwpc>Si;r8+>}1DLxLG%_Jcj>{RaOZ zr@L}Tqq(lGRc!HcE``-;Hp&z&UQMGAI0yE!tQemXWb_e1qy&#vS592Tem|1ZA*+G%I1O ze}ejPz_q%M(d~j?A`Q+%tY~h0(0jCC%U85^#2IY9DQVcpjjzERXiEw;aVo#Y+(zCr z(WGX{XpLDAiPA7aK#HyaigFj0Hm!$S7dwm03+flgU^|Co2v;r`_4&|mv*vAfBVLFl zJqe+%RLopK482i0p8_O<{d}Sd$qE;rta_)ylH`PC9x{&Wp$Bt%IK9F>QS5D*;rL@~ z8=gCM@|5olV7B;=q9dtCq!m|@+Hy-u&X}3dIuI(7SZUCzeA!)JIiVYVm-pwffPjja z62n_9`PQ|uG!3@X6`DnNYb4U=_Fm4J?`6(j??un|$*}-uo$*XP$3@hDFWyh=R@uE5 zRkYk0h;4{LOJ!$?DCR6G;{GsZSRX309=H}L_tqR}!Roap)*G%@W(doZF zIj|z$8&Y^T!(DgEQ_<^&gY+q<PG2jUgogb%7CXLIojCv3mej9j#c+Jq@yS^`^nxHTU?E*i|+_{Y!Rj}slbRH>t`g_Ey-(^^cat2x05C?9RCBPa=K4S#SM<5&fPv7RMa_ zY(MW-yRQ+WE{=fwl9oGS-cdMC)%n>KRP&C`YSgB39am4gjy#Bif7i!$VrubrBAxI| zFU0{nscHM;*8~+SN!_vKQJCTWMB*MMO4gCoDtLT-Apj~j9?j?% zaToV%0!Rfnyo-c!_Ae!2jDqaH^X50Qp zp$@}tk!~8AbWTUUj!aZmwP;0kc%8*T?}UZ|c2yIS2DSwU=2}>1Gy?G3?RB`7eTbla?6ap#+7T~% zDn-yje`@17@vois;hF^B;WB7UR_V(M`NJk%`tC8LG7q_gjKtDyiIRN~R2 zfHO{1)!fGed>F5A;g&bo%w>Tau*;DWqc;;hZ?m*)7?CnQ)X?I5S}*eQGA5|9`wuLxsi_=bG&3sz8<%;LPn!^)+&$9w0m;MU$H8=$iC?2yWZ--D?m#WF9W z!;&a2nAcX2OOUnMs0P(*mBFTRAjpnG4rnh7e^bjlWNX%^m&?^h zw3}RyzS65xH>US-55?A(&=`rDvob2hv6?Vb&rb8*A&jkemWLbm&dLN^yl^ygX{4Oj zIvRsP`#lu#Wqlslf>|2PU#+=*3;fxk(}X5rUpGi zBhf@9UgNfWi{uHrt<=N@cod;Sx(YOCy(=PLn<07{h2y}3igp5xINj*7aTvfbl~?dp zXfAL05c%U%7GZYlJ|SjRJ*RhUka+lft;3?9r$S0vt zqXQdJ*mE;%BoG{r8sFpNpEgctnQ{^C&P6ll(=)KDZexvKTEE<-?L{NfBRx{phhBQ& zR&4yU1AogAP0{k@e7^gXrP{N4Z9)w(Vi%tN!r+}2dmZ}bOHqoFyo^h|LHv`Y}b z6Ge;#P1bilm`7w}-C}DRnQ>N`zsD>l??w(Qq z)s$Q_nZJTYg0Ci1j-loRHP;UIzXdH9kpo5X9J5A2Ul-7etBWJ--+r}Eh?)=NR7iWZ zF?^iAx85c1INOBwEM%JX@n`1S4vqFy=Wl{P@u`MH3vS9Z<-;Z)2<{^jOGa0gU6oWu zq%KtrL!lwqQE_H^lJ2C};mTkSbL$kfIax4E65n}wcM;kiD3y!0Q#aXn;sY7p4vp$i zXyA;ml{Ze-V5qALV2+=>yA2c{l5g#CikfFVfw%iCFWCNgFl%l2fqTXD1vib%mEpTp zrRgu4vGMWs5qAks40DGxC{2J7RY(4iHa|cz$ zJ7?@{H#0tfMDnR$U$7b}?{$T1aP-jaii=d0&h5;4!7sQZhP^t+%kGz1&6L63Myb9| z_(%B_U03w(U(A{@lXfJo1P>+@2wCeU{VOmqYr*lqmj?=~Tc#5h;nuKfxR?CRE8_2| zAGj|~znnr(VR)N%LjRqCZ$-L9Cg$FSXgSuntodBG>ANmG^Zhkoo(#@4T3mDIVX@Ob zzA>T9;`F37t1kzQ7;JdgL4gzPOZD6jc3P+HH41t`M*GkYii`hps{VbGOX6dZEYix1 zk?mGLd%?AaXIRmGB@#dG;qwWo_*x|Wo<{S^;1QPxKRsF0IylR+86_u8X#=5BfcM<# zXx-#V(AStpclS_5(S+o2|1Q>7Vidt^7e(_^0<9c;Bt0y6e>idtK^NSxsxh=sB_A1! zVC~XhQvuWO^sqx)Nk;#MKVv_5=A0jUw|MBC{2xW<;ZODdM{%+$D`c-SDzYg{+(z2D#G_Xl|RJnsG6_xt@i?{l8V zg8f!`hA-$Xz#pQ*!XtYap|m7~8YiI>ZvaOtWNhZZu8`;Qd2tRMJy|$=^QQEJR6~aJ zf8X89awU%ze+^I|e+u^0?hmP7g;HKhy0)w}A~BD#tva~a1M4!PXGcdfsglg?8n}jS z`a64gifGj;C4BR5JC+o0x^zrU&6IBZ8P(%ID{ncYO@Pp0=&Oh}ICCP~_2qp*Y;D)8 ze6~yHELaF^&LBIh}aGg>3IpHl(^QX>~wlFlci?T-gm+$g;oDJL! zK)7){4nFiLB(~gon{maZLoDa3Yi5TI+?g@6z|m9kYilI6cM-*-zKiPzFZMRXX8e|{ zdBI?7YnOwA>Wv!~i%$#fTeZ3Pn9l0CukRUY_=L_p2vY05dyT4Mcpq-{My%acpvE=O zL*&7jqg*IM;B#u{W7;m*D*{kJYv_beEECP>bhtBrBpHXN)S(G=b7*exyz6oMA1;@i z5%7qsx$hFX<`74$U^U7?MW`TttT7zO9kCd0JpPy+Q@#aB;ILU-y2JN@U+-LgHw0SW z6d3Y8IzdTfk@eBw!2L(VAR}BA%q?L-=0_5KhH<)mqJS-6qSdd}byZxsslTtUN~;5EOwEJ?vl+_xLFRhgCP3IfW#saW%Bn%}Dth%F7!{ylQTL z*{Wb3aG>FzVSas)hS{hanR74t4dwFJb%jUr!4?&E&xV)_C%DK@vOOLb%6&PHX%EJ> zZiv0do^R?NY~koOL4#`qiNGO5+#00gy$+mHoywovdMxzm$A4xVDA-5655Xq(S1hVV zp=_1VSJ<=iIM_P~;J#++0^#(@*WcncEy+m22`+trEZKl#ibPK^(SHwCt)7lS zO%rQtBjI%~Q2#dj!_^4&*hCO4zJL;H3GfNeH^$1~-snqauJ5jFwu$uJWruT4i+{h1 zYz{25IkE~vLN+5#a5r{1d(9Z;N)Y3BIvC+@2g#_Jd#3zRP(8?QN zD)X1aeD?Psl-m=?i=2Qz=DV%mC3q1$yLQ0SL|FwX8UPrZ7Ut_sThX#kag?5 zAvAT3JlPU+xcxWf2UmZ==W*!1Nj~_`e-sI8*G~C$O$qHdbG+*e)Fk*)Hi#Dq!XkRn zcRKT#*`J=Xaj=fL)py8EE!VLH{|4O^g-f(Gi1Lg&c_|CjxOY4p+(KFJqTD5~{1|Qo z=>p!}{a4p02eN$NXK4aA{09A7vH}9xtX1;{Ym(A;MZew_wBmI{QaL#K7a1_ zR2v^j9^RK)t~O3$#!px=i|MW8IV3U;<*2Yd5o-n)dWVMjO?GFX`Z_c9ZUTsrI)$fd zmrSlGMj%FRZS~!QVFBizU>yf(-Y;oQG;(F48A)Q!ZM`Cg9B$iaIFJ^eo~Lf=j@jvF z>C*0OH|@+Td8{(@q4oi6D>v*~ZNU$o@;G-DJ=c;Q1yqT^?Rhbd3meV{{S~8Zt-tK< zBy5fY!;$&qb!z{4GHZkW-K`nKXU2JmVDMWv9bNKJ zCe!bSj$Ycbsy-i6n+Sur99yI`>Wtnqh)zt?y7Qgy#QX@VdTAoRTbFfNvJRWL{TL}h0uC^V1h52K77;OKG(Dauv477#U{{2gTd4+1wy+#W*Jm8 z!afMD2`h>ydP4~dQx@K0#K`=mAs-%3T3v^n);75XSKK`ltxTyFPNYPw4o1 z{tNJL72$OR;Z9j=$$u1%ZXnLgv8I_kS=}ZqKak5)QuRcl#6XQ?z!7GQHIH$ZZpsrJ znf}|OY;GjP3p8%-hV}aN?x}CViFn|%v<{Ifkag?7)YojEZ^{Fa#ZayIq4yQmup(O$ zf+RIF8f9aIho8NK)z*4mq7{iZre|5~ZyYx~xTYgUt> zr~<6XSk<>(^``TI=6~$8l_lUFj%h!C(-G6olf#n;i*=?yK$-We?e+20w`hLh!Eknf zKQ|DjXY`@Ax7l0=OIvdb7rjmFwz9Ka)#TeIt3LiGKW0Ooz=)FHI|HM!S+`nh<(;Wh zxMDx5%L<5dkfh0K)Jm8a3?ulf&xTW=3E9J}v;5@bmZ9bO`n6 zM;YqADuv14?1H~GK8<_vz@RV6J8H>jaTC8cFL##slGF{X9q$gejiVvr0K(7(L5tdH zEE&wy+sNY@<~F^N=<{&#@<)VfIub>fdGn(6P*+M zx(O9Fz-sxEzfe0q?XKfT#oXu7BNJONjNrQdlEi+YVE+-XYvzRS&0{yt0;Xm|1^k;Y z(riOhlGb%W)pcJyb8ITuw6&H!~wK0H>0x}{?WBzt{ zQ5y3$=&B88;-IpuN~OxjpqL@Ee5J9U&qpekw&t})sYaGVw&l-zi8m>NVLZ?`6>-)6gvrQYVJ{GKtD`&iAR24_Y~FA+|! zCE*f{>2x|7XsO(&(~%p^X@XOwyx80w3s82BC(2ap#R4|v5AXYxi{0!4R)o+XGirwQ z$cu$zkJ_MwL6&Sw(Ok+j!1UuF{?B|z`asJK1>o5zgJKPuyyR`g{-im*>jDUjq!ip? ze4)y5lUL{GarVD(@suxOUFW(uP=BIVoQg^DH?99DZp(R?O;S^}JPtr;%oEL-s((4A zJopvcU%59f!-v{euMct-QUwv<8 z6hxiEgo6@aMR&3IbH>Q)i*-exR&lv+%W5+X{7QfY!Im7Yilw7^B#>`u z3rn|xp1Y&A8DNaq;&dn-$zWh=ne99_1|<4AdEe-N6i`~F)AHZp1C4eBAKDf||D}x)<814^=M2$qwu|d&mBR11 z=Dhbf5|$~tP#XkMF?nU>z7i+$gfy_Tk3fCh|WDZlWH#@^2r?&7exXE z2@LNeOLU}`cLLY23K!!$qaF&$8~cfu@kO3`J`_6tQTXAWud?I(ft7l3v|?vLLVjvi zvUJvLL2ot>Zu*GwH?z&3g+IM9u=U)6EB=zKV`@vd+O^m1-Q)@H4Q3SmU@XLiK10% z$>R9HICsB>!Te{ZW${CG$RlSAW0a9Rkw9K3xJs6G3x6=>uTOF_d|N~Gcf9{Vb*y}e zl|J;+I$l&^>TU7$I?A+Pyur5^yGSGAMAlLK%O*Wf=`LBESl=IL>l$yDUMM6e_~$6k znlJpFa<(h5NI}9!t(bhYB-dj-A4V2tyjR{ zokUh($NQ(7b?@*U#pPw(xEJqfI{CUF@OEE;KJlRMYe9jD7Ht4&-5O`ItK9zxcG^q0 z>=ciC1YB(hob9Y(UjRHjDl{^oOBl_JlGre-6ohv@QL*#~_LZ#uhG?i#5%1&PdQ$Cy ze@7eN1QW~`z)zoozJqwfmsVA=JGg~DTV1>sRyVR%%380knJ^djZD&=**R#U1w#NPq z`?J)5i}maSs6#K-RMW}RA097QuM%P~@Tov=!I`7W2ihx>c;SzzlNVeJ#NU|pLlE@C z1zyRsC$s*RBb<3yFFbZer1VG!$&#-t zZyXv*GFHo;+{1e^xhFsiJE0f|HI*TRYb$X^__v=jg+K>OgP+A~73D+D`+K-~WE~x05RY14dMl*`z`O@LQ(tC*{NJ`C;h6-XZ45 zg2w0%Ft&N^NqIO^kcsiUANbmv7`;E%m?vls)ct!&oVVBto>LGTaOD{BOFO7Cp%I&d zj$Xs~VkI`%dj}GyzQmKN6qa$)TClmtC41o}o7wsx6IGmn%ZAyi)&_#K? zHMA;dVhH2<$1PkO_o7^?)1Mz{8U1be`I9dnzp_LgS8zXK|94gkE~r!dVHkqn)a@Z< z*E9#ceTI>TGrB07X4aRpw0+XUY^FhzHY*U1rqtKV)fvgGZmk`GF_K;WIB5;Lx6?vX zLer-~*5X$tOxp6i1usRfg3wE8SLra)i9MpgwkwOCU;%g^4R$Ua(y<=en6vT1l8N%f z-CD(9uf?pFjg1-Z2kO$)XY9vDG0jJW7iVAysu-Wvk~WH7i1~A(Mh&I&-8L$H_8 z`5dNW#P>Ez;}&Kt1a^S9RNd>vzJfV0uxlY);M`koN{IQkg^{3*h(>@EXexRzgv^`e0LSJ zlGd+REm~4;syCabND;$m^EQmwRqAa}gr%n)Geq^Of~MUO2vZ?tvIp9>NCDL^o-gzI z_JWl(O4cL=HFd~Tk3G_v8SFCLs(vPQsF{^ZtpD~ES*BD@p1sIS>0y2rXJ)H4V0FvZ z+UZI~Z_}3U+rF9+=)<>!X7rlC-YTmE_R<)8Q&|jN0|UQpPVD5@j6ZL?JWGBN;gwAn z?}w3CFGt!68%)a$&Sh>6bQHT;D4CFoz3033Ey9#_u=Z|Hm0lW2C&$@`H|sOaL@1Al z(IMus?jL&S2q)k6)%fR{Dw;11eZu4+r$FG)($?BY^4FvxSj<~UF++iiGFR|9PSSUf z$2kr{=2`NX;rCGEpyyDwSXTEr@CyG@-FMczXktiTOt@IbwSx3p=*ZcYt|Jqq%Niq& z;P_C<5{=4}9}+2_sUnTTC#pLXW7LGc$;=v(i)m@SeilhSMr>b9Z8E;#LWq3ykZR?P z;OA)t@OG5D?ZZn;w!cRoj)8lb`|Ig%TttrfnN1F=B0giECY7A9%Fy9FC9+#_G=s|x zgZwSJTxOupB(AxtrOusd8-RE(a@Fqb9rXyrTlbV}P=m2*qLuw* zZLnRk`m59rUHAL|?xLMAB?P!Rdq42YgM>#T;!b1LL8tN?Ft%EU{JU5Fd47ebL((zl z6`A!ex<@b~o6xpd8!4-Y&7v%+qiey6aV#tIri9eeXrEeMukz)#F%Rm6+=|tN!K6+$ z#q6@~3DbJy{wV^mf3JV;xeGS}{*-^k6`uSI8SH?{4@xB6a{`i!9*kkV-$1r*3xN-9 z_vx!g{CO?c*UxTG6-`YE5++COC;<>+(5v6;Toev>lv zMO*%3TgU(hN}VVwARP8`X%(zEB05<8HYbL+O`xdxELqVu4T4eUCG@{&9?$JvykKun z0B^*8wI@noEEZCOI;_LMPo`cS)4N;;*|?(a8%$Zy-ujD6c61BpN%(2u3E`K2{IA;d zZ&QL}wlmlE{San1iai9;6ef_*rqeLv7pD5|n&{ByKm*JQbmlzrbj*PpsvRz*?Eht2 zxINipD;Q(O(dH!lPzPBXl5YH4yL?THHm4{EW;^R&&=}UB&s!O_+u_4xp?qm>%>gf2 z3l_J)2~;6eo4!GRjkX-kZgu#`BW>YenRM>%81a=sqAD5mw6Qhn zyuX9Ly~AsP)s2Pn+wvQ1l{hX;qB5P#Asv6ZBQNQ8Y$)B&^N@P_^!&>kZR0*QT{CvK zX-0)no3^$_xH%!d`VEjWUmasc$>l&#eFd?R3-a+B{5*g60zC8w6tY?u;N*eFvOLm10z*3-+(D{yXPy*6@*W>94x<>~)Ht?UVAA(guOb`j))1e|5nO z3F$1q>s4vMi>{A3z?UnYGtcsk>pjRr(&Ao^gY#(YSLC-&56|D>|M6cthM;n93=a!W2~l&M4-r_2iD4 zng~M6BYqNIhbjYW1*e%|^WvnB8P~&7w?5}MD%cwdhW+Zf8Llbjd^ZsrTh#{ z77M+0rfTfb+brEg^(NCeJ;LTm=Ih2N@g6KW zvCw9Dsk^YPPLdiwkq<4EZLEcL*EzNPoq0Eh5ic-qobwAMNxYdZ$DR#%#m2*l-6H8V z18stXbqk7NrLGS^pxTTQH@jQyt-p`=+&J~Kf9i0n*#Zq>1&5QgEkr0`1e&WUWv`H4p&IIgiwwIqX^bW|w%Gn26*=Z;~IzbzKQ{YUA=> zd9tM6JA+~UOP=6O(7(k`(_{qp^0&SV3}zn;@$N)h00=O>#>R-o=2yhcaqFrz4=p~*+1R5r7zLR zsBS#-)mpdrS~>Ve*A+CoE=|w4OzM#a-xy|}bNaM14)nU!IkfXrhb5m)-rCA}bt{-l z3e$CIoyQ(ixUB`|6AP8_qpFO97Q>Is12^?kNsS)t^-=Tv8jT4np7+1L@qDh*|SkFh?P-QN<7iH#s7onELXm% zu=*{c#Awf5g*NgP97CdincXhl&i_-OqA`#)f6-q-cVS*@vD-4WVzFalV}$})xKRRO z$?2yZaSGuem=|~=T$o;ejUi~!_)W^sg;!~s5MMb12)7Q?3{faTT@dE_bf(#e)oSmN zvQri5i<`dz1C@twmkd=Y)SsQy{F&v8L2-Z&QhobB3IwRAfE`nV9FX8{zH{5blw#q3^KWocS#lmY$vmIvYN-#0-( zR8bDZMtl)LO4-)Ib}3r<@tR&c@#=pwiuLg&n08Ec$8XtM5>aCnyC?Sx9pl!$hpQ)I zui@d`D3)B_oj&1$P4)}kOSjQtLZTiHIM@23C%%UXqZN{?@+3^=C7W^p!A8Q4zW1Ns zcM_2ss4rvxw}2h@hHNZ7yatiN@v6$ku)lb29PqH<$Hbzf^!ibp+FjyZp#AHVd%bn` z@Sw1>Da}EWFU`6&x6aw?d-_|-_#qvoVZ@O16~e@8oaEfJ8$PfjICKef_cY9EU~$h1 zif8?2l%C!W3efD^1=X9Y2`@BB$Ji(Kd-AxskEAMjn~AnqS;+C0s& z&9QaVlsoQ9)31Zv|C9MHOixL?+u_}tWh)l1Umgi}!b{A;%l%l`Szmq#xK0bUJKo-s z@>D!jT1v_IO_2D$yAiL@{53ZX7(9*s!0u6CbG}Yjm$p80O=Exlwj>_3KFCz%0lc-ueJ8wwJ8*q~3bF_Ben z**fs5#a(p{qeOq}Zeh+q*ls|9!+#Vlf+t6p*?=p9<|U~SP-GSX{|1=@U~=kT-VJK) zFStsS-K2+b@1jWah2>zNSkJ7q?Dz7uFWM~*&5@dB6py4txYZ?n7ixFfN_p3?%6DFx ze#*(HAr#~SY?%V0sNL-dU2(h>Eib>1ViFeoiS#v`7f?&=a3pw=UzpD{7^uke8U4P7 z${x=y!~a!PQxH-TqJDF`?a{jzJ|XYwZ{t!uOpNBve5-<SRWUB9ZfGRs zD>)}TxzWx*dB^MZS<%dC0YVAP8%yRAk*=OLg&&=!cUWDEqINFK5jOY&8w zwsWN^UMHoHQhL{m$rL1b4{x9yE&QLBRh`W6rKFUCQ|Lrpvu_XK|;z@omfKame+p;&^{=b{C(e zG}L)FvBUb;irn1Pf%wo`^C6;m3y{D=wMuBVA^jv3onro;7a89P3ZOUzyZbRPHo}rV z&VbYE6Wbc+NiW%QTz$9CZaa2i|`sF451o(Ph5Q8Dq9EkjbfN_E(nXhrUF}gIl=^a~Hs; z%KLlgIOrWvADlJ%VTd|86KGVn8FTghHY#-YQ+=AY@qlB>Gl2-c&0S4dg5~a7>sn@S zi((>gWB~=?L5zw6%xOUOA_4c=-z9*Sq0_f9AV`EMX_6)hdIE%r_Z*Q0Mgf za)wbygOX}{8=56-wRCzy4ed~3{tzi8_8L#2;ak;X3*29iOFPw!OuFAQZ3iN{EnTUN zl{xR#KHSfx-KLYjltdd{B~M&rVcIK+N?ioDb(2CuCvaRQY8LH+Try|$CPg}?YLEV; zg@z5RG=64%xRjCjNHnfbFlM51#9Ko1QD|^s+9CHlNXDjL$Gx9nLsyA+t{%qfJ#3n$ zp?v1^kdq(xvisY}m*>g-dB}?L`?odT1cnG&S&GY4nr#Xvr8MzREpn%MGR7z!oqn6X zbN%2!P3sZU)yl0mFE;y-R<*}v^G8Un)%PW5%n_WdK=lM~7Us>9XLNbJo$RO2d<7Sn^aEvBnKhXqj>WSGCfR87&NxpH%}1*XV}_rHXTb3 zD<8-H^aeEp47Z;vP~Q58y0P+v+Typl2drfWFXTaAz zLU3YKfG5(fC_+^cEf@!U!*2+hCE1p;-xmKxe(u>^?O7mIoUR?rVF9P{<>;b@a4x5a z`4EV%sYbdVbfZgZP`zmu%yFPOJ)YCBjnPsP|CfDPfY1F5R&I^;DEc@5=yJv^69K7>b*ro7U|=)GFskn@+D+XrB>e;j+q%> z4A4&t7FKI6xI>G66?FX@g9PQ6bxZuf25;zl2GwZc8u%;YV`?P!G zY3ay+6wf{1HSv4DNIEd#|H%P}?IuAw&*XlivlU#$&4NR;e3Nh*^lp}i80aACm!=x;469sw)Z<}>Fv*DT{-yPHxU4nDkSP)GKrd*R`al$jTs?D|N3mfa(IML4= z+b^-0dQ!jW@Wj&TJEn&YNx|U`-oBjXY()Ec_tUfP*(PQbuZGaf)A@DpLgu(9EE!E* zp42>T8QwRMiC<;Jk6@v;hdJnpn?#>W=QyZ%F*u)&R6^z+6Gg(M{A#XjpgeR&U-aAT zpPS(#B<1N1o;f8LNj?5}+|ls-Sy;Nkbvv#$p0Ts-K}19gYtW1BertQe);g%pc0Zp3 z%aIs-KVX3;d9LZMNMH!{;dr{1nppD>3?mn-_&zL_$XFCUYR5{zs<5G%qyM95Ry?5D zfO7_c2L(C10Q`w!z5>=fS9@jF7!}{u*~w+JSga@gCo}YQJLn^eq;EK5-2(Y$5IsJg zP;*I7)FGJS;OLf4thIJCsV1D4Xn^f*jqK8^+Ow{OHPy-)D!|Sjj5*^Gio;#N}H?Eg)uLTPYB7G(c2F;8L-k>RMZg2~@5ctC3 zekj})oedFY!K9BJk6&yI-hJJWvX4`}FO)3z@5~5G?nOu&HMLKvn1Cyxu7pH%0V*3p z5bKRrG4e)OL6u`o$cqccR{oZr&4wb|moMf=p4<;?@d>WieguDryd3V)131PnY@Pn2 zupodgZ-!5ScsEH=J>mo&-lH4Dn*_K+3kvo@ytB8hs||aY$U7#i?PAe{I35_;#(YP? zrNjrMlhOhIY-veBJ@Dd^WuYvj{4VYF-7P`}77m)*glo6VN{OW@NuDM?n;nEO&T5Nh ziv$|(8GVY55A9&j|MJyBv(&;`*8}XqiYyaxZMs8+YO5odD=BP&tqUJ5Tvsp@%ezP{ zb+rnJEVpv$kS_^P_V^$Hfl%LLF@F8VZ!gTy9U0N9Ae-`eS2y$7Dq&S;Gcw84**BNT zC&X{pF3rqL<#^_SqloYOvD>ykMGurOnC7S*;+9m0l=jVp-{N&l7Fuf_2z>n(FZ+F+ zsi+z$QQ{zRLok;up?0EU>_!;+nf28V{&ry%SNfEetLct3xc@i{lD~aAcsZ6E!~0BJ zNvKHcFPFX-OM}sKjlwL?!>1oMd*vuF)uYi|+zfPe5i1wRTGf%7reVRHGjMDCC0wC+(72IzCU?N=LfT! zd-ph&Q5mV2-MZic{c`i!M+Tp1nLU$cim=fl0yFwQ3d|a|vtO`L@E{eN^BvaUnU1AH zm#)Ek)QKU4`b~X{E?0k_2MdGfObjbHwB3GI^EnDSd@JrF_&cy?DNX zSpa62EW8>i=Jc|FH>h`zQ`r-69HIEPIL++B2Of^XREhVlCXT7SRNo^`oPp>-+F`-> z%@t71#}jP9t$4E&UTbMqYyb8ce_pSrvX&D|<3J<>^zGd41{QFQl%w&b8@zzImPkti z^kQek@ArLX9ZzA*hxSb!gyap?XV%`8yu|Q}Yi|$gZa8#a{&+rv3g*>8NNb(gBVlw1 zpzW8wg;dfdjUHvDhtlJu2lDK-31IYRq87xrX2Ow=g>}BA)$VE8v?RR4G?<;QqYh4) zGbHUleBf7cCW6!21EIW8ZdP_#-*O5FXTXqap}rkU#3H7Ru8=3mEQIfylAOSad=B9j z&O(sAyaSb%3I8cb3;f>~o{hL;dyncCnMn4IzI7{`m5B!e0kFU=^PdG=;a3R=H1fR) z4X$_~n=_Woy9)K57hUj^j;ccQ9x;P2Y?GHU?6s8;#&PtYku93m1SOlNmGB&;8eV;` zPf|J0)|X6YGJlUku9ubJYMPw(`p4V5j)z@pxpPu|C7>g0ux~F6Z47mOZkk|MV(~FK zv{hjtQvFtY9->1jQt+$?Da8LMMyKnR_s6 z{RCYP{EAjfk6o{==Wz{~Bzn#I1tY{29>%Llx~A>6^wsO7f!l1S)$hJ$KxhPwIfG%1 z4jjrwJAs0{?qV~|Ts;5I-~{WAu(^~}mz$$OID=Q(?hR3epCIDdClczkgVfqk9&6at)#J+c$H9I44Wnay&k56wZ3Pm znv(I&Mx~|tX+=Z-<4mtBEu;#?luwlNgIL~v1x%T%GID6iQ1(T;C3>Mb(I}A_VdbW< zW%OGLWl{J~R5A(uaXvf|sGWWi8egjdx_q(IusB#`^fs`J8Lph4Q4PLl@lOY3@9uEf zHmvJylTrx$%n0Hc{Z>}MuFKhE&5Nu2j{@>SlE{s4<8gl+eB)W-y}G2N2w}e(BSrGH z{Z&KV?Cs8u#za#bzR2I@ZRTACn-@3e%^!gotbjvIzIQ7g6WwNS3f?T)#!)`GDs5()tf3bD!Q@HF($3mpoT%^`K*3Dz@=L2e5n zf+9m{lKyH$o&tJ6S0ElFAWlq%=HV|_+uxd2WBh0?)H&J|2g}=OCvTQ4I zex7@dUda7r0OD5tN+;Eyqhvc3QXUliZhnnfg%ij5th>EEIL8{75?$*0YM*tO_TQ+6 z#rD<0i~ymnfQtKz6#wXu;gUH6J>rwK{09z=)9Q_Kl4^(3QwLjLSPvhTy?nv6Qp{z# zKOTf!>ctx0+T1isT3Q%fpf0dQdFI1xvWZ8y>tXp9tG9w$XZ_CXb1}dX*tTS0=bU&` z)11u7nZ(Nn`|IAjOka!)&qCEli233HX4&c?~aTs&6(70bta>$V8 z35QHL#$4bxV$6tHr(vIC>H&@AltO+k4%7jw?=lWrSZ|(BuleoTfpX;;-0H68DNO(k zvWou7w`2LvO&?j{MnMkxi*>j9`YG8kAWCDiB?vJsxEMNs@`#O7kuKAfxF*NXHDvih z34%lX&iRkx{VE?XuO2q=eby~b;r@V#*2>GCx%&l-tSdqm_A^b(lyUCW=q8iB2b|^8 z5h_yWHle*Tg(pu&(jH#j&n7Am*3hoj@Ps0&MXnd--Csev4ztpJ>m{f3dTFiSl}mTc`=k3q_AU z+eoTSFaJ>(EaCDVvTJ7~$KrzgG2byD6X!1&&tnEJwmzVh)W?{YM|7*-qqx{MCDp*} z73P}*r~adGhh2-8uah@)1a_7y1(%Y2>UYFPcbMhvCh)VQM5s&|81%g$^~oa+i`8x@-Dq^bZHOJTTYb0N zzJJ}DHWlbE2ZULLj=D<_@wvZ#T)LUy*={0aZIZ4oC=vgIl;F`N3&?HN;d4DV+X%ju zI~aj@>}bD&mMu;@c~(Zmj00R=?XzqhhYjrdcnlKfr=x@cLLD0^Uao+{sMw`|8>%TC zBMp`H^u%=C#6=Z{qpyk=|-A{p0-5p$HxVHK?1xho_G+2O;F&$ zh%0+a724z8pM5hA-*4$#Q`T(=Cts#GPGgfB&SJDJ^j>F5BA1S%_yChvVm#ptd6&N_2@aHKjFQ5`^I2V&?0(QrO1yM3OgjqZrUpSa$ zs@)?5dZQ(UR9o*vDP&)WBo9RQIhdq3IV2^Kn+d(o7q(iWu!Ptr(+H0yUh7Z~y2}@A zj79X#zE$yEbaK*LvgeId8H3Sa@FeFiao|-Fr}3s5xlL83*BigBidL;n$F&U+fxrTfBu*+S3IzairUrmoo zxE_zM>HQ$c*>n|i8|$1bEi!$2@>n&cc7~%#T7q@t;pQK@BpDI^@khgSb>Y)%Tq=6F zg2D8?R-ZCN>29{QtCd|!hnd$4T3IU~@6c;Mfuh$^go{sG0 z65nz$)m;@F0Pn2D02SyTd-wCqWb9qDF7oE41Wj58GE22i@Od<=ICLcSCOr-2tw)?^eaEsuX1gjA7kH2nq207 z0+;L)aerK={H_~<-z4<_&FrX9v|1##cO!5h5NDvqF~=?3Yk2p*wEttB*Gb=%p3qa= zSl<>7^&f-wZ!)72`>cNOhDi^swNQVIU>jawGjXw?j3`yy5k)<{0KGUPKLl-J!4+oJR2Omh*eTK!yJC^L2o7YdM<749> z`KW7|H^KkQ}l3 z=k_O%N~rs-JP9%oCDF^_0?fKi@z+IL`7omKh#k1p$V=@?~PJr`de97_tU-nW=Y{J&qY7A$ z_bGT z3Fpbt7eY3G(5|ZTcASOv>T=i1(Z@D4x4u}rq7>G#z5}m~3~BrVU_8BU(oDcr&QSOI z5j|846x*+XEe?8pZ}+mEl!vbl%l`Y8Tuu)DH;047E*jWTq}j@H0AuJ3EtG>U+(Kz-QHl$`_e^|80taKtp5WtB8N2ww~CioKxZ zSIkU}OHh+e+Ol*5)EpMgaa_Bd_IgF=tp}~9 zJR@nKVbx}NWc!PFU{W!k)|?le+x|~Tz}i_`{e{nOM5&7Q96B)SNx#H{wcqFLlFR0e zFZ9wZDOWy3c>l}Ku=*|E>7;Ne`W=?>g`vD~N7)Rl2NT7~uIN3E8Z>x+u)Bcjo@*&j zm0aZiA>Yur-1+s+gD;A#;ihQy8)a$FL|vYyiGTjA!^?{(L_lW!sXwr{ebg4ud@$VO z8H7jB5u!tmJZ>+aFz&{*gBp!*9|ZJ7<5CmnimrsGvrdcgtX zjHP+K_`GRrOkCyAn&kKI2dWaM3Pv};ik<%2lYXgXuKHVDG0R_M`&5<0<^KVLHT5@~ zRH^hqd+{#HSYu&TWM0zWCgS=AIha;eX4`z%ffH5z)U~79!3AZ{c<^yGSS9QWjX$iaAf^-g0@)WQ94t>TwzyE3cZnM$WM zS0P=ZqAl?>DJl4cVFcf*&|IN6Si-sB?z4Xwz5t?FVyMn#iU7;)^Ln@=*xxMPN4 zGQ%1~zx2iPOnjU2bJ&1*ty_1AqE2YZjL31SMe|q_(m@899)%# zWwoeb?Smot0=wC(eAE!MU7kc{Hm~IK!!X6s?x-oQc&V2eUcILig-*K#HLlzs9iW%R zxCY|AL2~jgBKU0VonP9sboXSjG({OnbF&$QR3g>p%4<+Td))3~ZS~mh;@v*F8NX_~ z>KHZ3HakrISwcq(qD=FxeevG0rL}8A@S8g-`nTKp-kA z2^81cp!Umg`-r(aX+Gv@7LRk1{hVoe{>;;4;WACi^T>zQN3 zkznk9rPICxqM^F4vQszUDS70NF0ILRsFq!69^4u^Xs=S};IHnG9g`{ys=5E6-&OdC zjoH))wy!y94=gdelUm`Zu!FQ15@uuBBMO9XnTO*Cle=V>dt(oq*}RXJmVa)K8sH-C zNl0Foh?6=jSB_5N3Go~}UA6H^opE<60c@FP+l#N(Ft4hqOB8U{ccL^NeZ9WW%Go-# z7+Gwm#icH%^uzbS4YhkA@{*JtI;Mq5hwheHLx0A$xHX;ZEwsY#5AEHV#K;V3yas}j z?!H#8>0{pX!_r@_$?Bbubt1%a^kN=cLPRr_6u=D zU2`&#^5HsCc4h6Meudtnmb4cl$?+rS>{F=306pv19qpg3Ywz19*TW4GCy(mr4%{_9z>`iw;QpaC*+sWlveh`CmoilL3I@lEQM4XPS}w z#jK=4U5A@%$m@kV7f!|A?lcR0EcMwKg>`o5%B#84F=?HamWGB#X5TQ8LVAFAYT-}+ z`*xbh%m;<3s|n+p_d}fJX*-Maq$obxjrc=gw{$GZQT+=-?F%!I2Kx`cGV9+yL5jnC zH3X1gRb<@lIgc*g&C0{_S$@>DJkj2kUv6IEo^BGOM~r)F*OgzZ-BQkqySaq%P}j{X zAaPFsi6|+JvfYdF7+AA=jZ~9F(A2v%_7S$`zK1>Ehc|meirHN7^@JAW!Icf$d!ebW zqU3VXE)9=m1q}Dmn*2CT_e1^=X|`Q(k!IES)MrfEF`hQ_#|Z>y-D-LvZ#>^juem{b zcQW9!X9bFzd7Uhra7_&f`4){Fm6aa;jSQKeMW~oc#g^~12#CzNHx0Ce?!#FJDeAi8 z?o4EOZGTmLs8r3!#LGKD6%;eRdr<4Qb5JsikcN~h1~w?ylMbE||KtXIrB4Ps`qu6< z%30MkwVI81-^}#BPap99tMue1s{X#T+?dtDXeFqCsWvO{k6tjCcQLG;POyt9VE8wA zr^cd7=^M(Wg(teU!=EN)Agp5ue=1d4?i^)$@y5je=~Ve7RJP34?ZPWl_1UUq-eLZX z-KutO~p2}i< zwHmRS%FhtF#pT78{D>27qn@!t2_F}t=G9J|bc9@u(TnLp#G>b$o>^noKhiYoT8rH@ zZ}%=%J1cfuWWfQ~N=K;oPzJ*K%D(;T#M87t{$mtcwHWMacG)MK6=-ok%cE>muFRrz znmgs@W52ftj9y3O--`%QVe}&z)zzm_Sq;}#d6lxYe-78NwQZ_u*3Jyb0)F!@rAp=B z1YgtX1)JW+uK1E(w!6bZpsw5tb48{vK)r!S-W=&~cZn;Wq_nMMPPI{ z)FalI<)x#}!|xC*ahtE_#0g#>T|*E*{-bDwIo8zV{Z@DEIH{WGxwGrzLcTwF%hCYD z5m%qZ*j?Z{1QTdJtL@x?CkWidiGPP*2?8O@e_YsAVRQF7@-s+Tu6ZV;TY`j(+8yYf zA7uxGssRChED~diQ@0@0R}h44ny_YB>v!HQc*p}X{Sqpuc1C|jBYBH;iH$2&hm!h@ zz}%r?0Yf-F0k%%O*p7IEa~_y@Zzna0Vvbj%;KZ*A5#niz;X?Dgym4<%Of|Vxw%Ox1 zVUYqiX1lI!ijiW%4S_7$;=r2Zche6Y=4*svY|yp@F8=*-bw>~?bQAIe zjuE6>hEn~HqAQPQ`v2n!sf3XGswhRseQ%X=Bvgu=tDJM@9%ie^%^V@bD)%vR%QbQ* z_m#Ql3XRP%W5@UR`TgTBd+f8%=lyxVU$58mawj~s>8p(!F#fyVFzK0Q_WAXnm+f=t z+a0^l-l**yf}YXK+xQWKXs&~t)4fYUom_EE$n522tBmfDs5povF(V>a3aSn)h9|mk z2yxxnjL$|{;y74;yVsh!OD-OPKOrufOwhE0sRm*?G~+2$cPCXF`Pz=-MOei?!+wVZ zY%z5A{gn<@JW2I?$NYLp`$l8MCpg!t4fcA`zfcA+fL!dtV_SM7Z?V7J5X#YF)E$>$ zB+p(GG5qr%)9v2*emvHW!3mSpBY8){oxUu%%N7|_z^=)yTA}(IA?#cI<8ON!!fz>EKwWR9&R z<=b`~lks&{YDuP+qVJL^!oNO?v}CDg2R@D(UJuhE{k6c3gv(ALu-_cKA*dIK|{ps z!rArwhKZ@8=X=Y-6;TDQzqk+WIO+lQ)sjPTB{RMJU{(lpjiR(oU?`6sXrq{C!Z5XE z4n=N3KpjLf-QoQA{vK`q81pFL5t%FM1Q|}#yfo?-lD(i3-xy|N$=>oVKJksLMAs9F z+g`9#^|`RT2_Xk49_<8vkQjnLPjb()|58=j2j+$Wy>Rqr?xdRK+1GgX80TXZzA$ z;}%=nxs%+wUYNvBcIb-dO}4oB7_V79WZ$#KCmmGjHW?}6^gnSUN1_>_vUEWHoR80S z(Zq=TAz6`*1qn)kJKiP~#R?0;A4MI432!e?9$uF!U3DPTNBqZ>|2(UwQtj`_2A=Vi zxZAPFwb%`ka~xZp_|%)X*{#!R^Frni2N^UMPqplYaI{@@J#w)$zPefJE`9Xmx8ir+ z_KrVo2ur{~P&z%Nra$_M-8aS9gyA5#>vHW#D**30t%#Rn@Qdk_ngJ@H0YmEFX}VzPF?iSVE^vqs!1g`G1>@Hi}qAhHdtqanWtT(!{ zSo__|7MQjQh*}Q$Jvvgi6ll=qn4H@U2$1RF{hgvOzrj2i15WT)jz4|o4&Y!ZhG#$e z$S0 z4NWK0DEMQ4qBlx4j5QmuEV!u5wyFqt5Ntm_<1spW>PDgp`%p)XhFGbHr|CM5FA`_; z(9=%RGeeOFu}6jGxof!k}dxp2#fruHVmmGS=ootk1_yNBig8 z{8}4FHLyzLQe6Grr4kNs%C@~@k?aS%XKXg1YE{7=4Mz>ElkKh_1v@mpa0F5^NZuxo z{fBYJ%jEO``#X~@mjiqX=mx0}KOi1PgVctlDl_J%b1wt1I2RtEj&jjB)lY&Fbaa=R z2?|EU-|1NqX3{uM>#-}hKPsJCt9iGo7P#uN$9eQKOXp6t{p?oYasTPtjuMfw2SH@@ zF-!sd6L{%clU&Oi1I_~KEjtzN`?*&0qN&Y1x~2jE*mFDrcczRaCrB}-v1c=%2c`j; zdF9subQF+;|EdEHFj&!JC}@Vn{!?5=XIEWIY{GPAyWxoY;S6&`a^snvkATU^nZILzMUwXHM-K*Csx19gVQJ=zL=ZuUS7v)k-Rg8+-K% z{W<@^vyZjTkUhxq>2I)bv>A_vp4+S%^_#|A`HDnLvl~iWS(b+#EJBffw17=?|hCaS1CMOp4)xw zHd!16>3PL^uZm&sbd+6usO4M8*T{buM0BMy75d%sYC-t5Q8ZAxfO35uN^X63FdC!LjMK_=l^1yBiU!1U$B9t|M~@(v4}lgepq(5`nG3) zXSexIO_S#yXp5p;G3#!Do2sJfBF61?0mis7MUouY1jLGcBw~BI8;C$Ubc(0ewgdEy zi9{xA*Avzzi{PH)QxW1mw!3c`7bvGWc-xUIG$T?te(~R3sv}Jdq?RR-2)Q_A>>b5W zt%}ua&>yK--fJ1Kx-Q5eko6cSC4*lCp^2G{1%@P1y1g+Rmn`*hTPmD4yswi$0x#Sc?%EXLAo z@Lb{I+!RkL7>MV2K%DJNf@LpbilPm|JrL?@Xhy2%r4a8N!PuLTSyPdZFBmrg68M9G zE`|c!bqwpOAV>jsfms+rG!uFf+~*4bvI2HQ!roDBSL#raa9fZ2YJv6cg}B*{vma0C zn7t7iFc9q9P%R>j;|p8=A9*v}i58==QEZ4A;7_G6QZ}OX3&vRqk>6y;W4heozv(@A3QYj%Rrbf~wWyQ=)gwC$TW-&!W+P5#u z6Kkk@$f27r1e}sV`1sqsXX@9zpGs?*EIewFH)b7vs(n~so^)>aSyKATH=ztMH@xT# zT}7LeN0jGG{zEt8|0F+t(@2xKy*!fJSyX2j*LLQk@8gxChfFDI*A4WJ4BYA@Zp>_P z@mX0Ooqo=eI*rSiiz8h9AG0AxAVv-y;m3IMLjeb zqOctO2_xO%5jth}XVsAD`oodp8$oNy*8>~i_hWA~S4djmJ*i?*M> zfTqk29hqIp@`XniI3%$$K}^rAp&T^U1S)mQ)Tye-TAD1rRl#HoxqOW%U*=x2sZa_< z;Il0XtougmWIfu6v3Du5P?s1UvHQcDAJZ4)!C{QYw zc4wnH7`pUQq!$DQnBRGm%$DBcT#={#V{#mhSUAO)Xr2mS@>H|Gn{S28x5c%Pr+oAj zk*NfsbjZBr$4#WTjva9W&tFA~BICvxAW9{9Y)VH9evNt?ejBTXS;p|=cGZ#>jq;4w zzx9-Si0!*C1!da>2d@u6RA4SoCv`aRyUg%sL>_2}Ww%+Ra3#6nZHsv+)B?ziDzIZt zCYL!d+D@Skr5h_tfrBM_;Q~FMCW1G^nXMe57}se5z?oC-u2o5sMbE4(L!x+p1B#PB zpFdrmtaW#NnaI+R8`$uJS!o3Xp{tg3bvN+mE)qHCbWN`DHvpf6P4`yLpdb`w_hk;| zZe`fFBOqNTBKrktI$Yvs5I+vv>8B!X1LTo5=00<2uE)Mx|D)`&vd+&*x*v=><63UjfpB?V@ZD;k0<+U@`yF4u`=HfrIx9=lZrGk(Au z`^<6HN5>SmPnI3`@>j8wUeQQ>H0n6+ePxu!T4?rdo2N4cBdPBwV(NQ4$Ys}poVJ4f z^J{@u7yAzBYAH~X>7|k*(0O88!<*(>z{Q+&XZenZ&s51@BoFA6b=+$NFJk1R%UW)0 zD?ORstpB}c@|&o(@`FPDJ^Jn0R<|%0y!yZ6D@kA=bL#p}n>ccFq#@kym0bCz&o6_z z^4KV$ly_Y$?Va#%ZUChoU!X7I~a<2Qk!&Ut(Ev!tFflJdwvG|vZ5O#gXr6) z7YI`LsHSc)qPdQ*!Q7k7zZ@o$!onkuDj-iN+eA(|y8uJ1(;_Mi?Zs6>s7+iAcpMuYw(z%|d-%|{}!{?)UPmrxB_8L-KISRvlTh63G-CrNQ1 z2n1}0kW(ju)Zw3@bi~Ipsu4|?_?rhJ{ZAwmYuFgMwfL9>Ca{)oeZPHgcJhnbRzmYy z|BB#WS5Ex^3v_M6zmB|C60pwShryqh zjDb>s7ffa+rexN+G);c1p{$idzt7kS%B|#_mg?v|`A%6v>j7Mdg(CyP2m9-^y`HijLq3SpGt>mxv*hM=r@B4LS-?LlD_M;am z-iD!!*&7}u?7s`(p?>ya&hzWj{F0tEN2(OO1QHPW$fhr!RYJuj%Y6nCDK9YUPI!Tr zkM$bpvYV1)&6XA;YpwY+CG?R8Lt_x(3+pT95V|~D_;Hq3Gsf5K?)Ycm1OIJd#1ZQ_Nw~&Bt0*^I*-3_!FS52tZy{@j+i!xT=AZ*5 zFSbH{r^qKA-RoKVFo0HAcYNdX-c0OlWnb&6@r71X8tHg?)1bQmigdto#q&$x0zDfl zKu_+7{Q#bS*@8dhgS=)tTel)|Pc8)2Au$`;g%t!zy4qiwXcO98xHPItP4$95Jn5ZX ze-~l?F!u6`6(#X734b#U<)rxGZL%p#3Q5NsQO% zX{Di4wr^+qda2S`)Y%?O_o5esu|vBte%ud1=>|R;i7_tjh~;BkQFfX?4Ez0u+SMx# zl(Q1PXv&SFu0gw&R@n{^yR(=jp@#REwXzDtPucFamm^k&Gvuu|h4~BcvqEVbB%bHdozk3%jk~@bFBuN=nWx~H0_88oS)S_z?Cy~q6l*=y3D|?*Di2>e}&m(LL z3RFGDoV9*KkWT>hI%8l#LO_kw{L|a(GGmnMmd`n_$Hx2o%FG>N+g~!s$-qsH`ODce zPWA&NLpd93)az(DVjKx7NP^rqAr_IpG-~O+fXPEHKp}sY^{a~N@-c586bt=mls?S_ zUdwo8>_;>sM@I5x7>~%y7ed)>truaHCe0&jrXa$HK|)J%>X6m>)E=%&r}kE8VZgVc zwu8W)$oJT)(WVsvKbXae#SbR`LF^NhS6Vq*5SSsBTAq}tfJEsi!i%+8m-k-FZ;a-Q zW`~TV&><(WT<^fOj{wi24Vw|U$WNRIZ?V4%g51Em9&a7kDDs5{NW6oH9kklAv!hP~ zlJN%S=XI1+PoM~Nm2ls2YP>B`Gr~6b6#f9XkkV~y;|B$^jNWBohbxvulZj~2+!vT$ z7NYWYY;~?A@E=_=#bz;!RkX8g=XC@Gb{Of6-~nP~p$d|j=Kg8Ro@cVflBl$KxCsbD z$1Nzyt_#%m-TOX&%-jgz6t`jUC_yObQullj z4Pi$wpF`#c3tT!yGN*(y*x9deDfED6it9VY2@1=PZvFZ(G(k?@~2%M?H*%tvb%_`d%Qo$BC#oP(94*$>_XQ|cjf3U2mQ43J?a2N_tG5}B#S-* z&lVN$nVuKCX4YANsr!C+z5a~O$dbc5AcB?`?5!~4(%p8RgoC-)LESgrS2Eyv-`wVppinMC07KWVJ|0Rk&JC|{1E)?Ua-Gjk;UOinLiqxL`8sbq;2&4SIK${d)@F1pp6I11h`a-Yj&uxVt*1tlRum0+;!me2w(SPVj zN)WNMtLPg2xL#_TV>_zLa``FzA?YX%M#G_D$B31{(oRC4xc2-VB zrWbB<(|xwT0(a-!EhGEKDT+hxu=>eA5@V({R9$#z3q@O?_keP<%o;A*NSx1zY0<`) z{qRtY8=!*@S1#IPa$5USW-jo^b=JOJR$CJHSwfXUt-a7v@#QR0taC^wDC8+}dcCcm zo`dw1!1)0(r>Y5T)doR;INMIH2MJTWp-Zg>c>5^CFO@+7gBNnvP>(bvm(Uk4>k?iE zIj6r$Q9lKdhZ~Kw2rPs7w?p`2=w*ejTA=SwCCe$GeX5P6ee9dCs^?-O1vMa7%6vef zn>aJ+TK7Vc-_1tYs?+$t-+%dy@R{Ua!Mz??T`fq?McD4os@Xq_L)9?TWi%lu(k!Ra zaqfOtv?v2;Xa^pTT6Sm+Wo7B&?QWe3Ho=TGcvf7^^y6NA6)K(<=Z7BzNr=G&EXK;E zje#gZScYuyOUa>?%Mdj7H%AB`&#JY*#?Eo#KxYF^KQox*^6<~;>jlL!H-&JZpSNX) zRQ4U#;BwjKR3?E1f!1-qaC!kk;1vzD=5H@RO8>0mO?u5?U@{KIhhdCwGx-%|miIBz zHY^y|jkhH}sBIS%5>ysmB;3EqK{i_Xvuc^9F<_#dljLq<_L%a@!>ewQPf_jL@W157 zM187G=V_f+;3bIy156rY{Kos;f17W5-FsIHpCu+t9OSi6m*u-5t~JcNlk3Oxel{JC zZ5+`>8s;hxTa-cHePp3(Uv7{iROhb-o1j?P=&zK?7qEl5*L04|!*fc>_n*$FFWv48 z1jm&3HYC*;=?)l1`LNNg87)(nC*>U*qZ?x!FPxc4ou$sRUau@sfi_vrQ9KL;b^&WQ znS@)A+&Lh%88)Lr?t)L&x8B~=2#t& zIZ?~@1}mgcm8Tj0djo)ae@%;Q{d6Xp4uG2PO=8Uc&AajCKaq~F`*);l7=N3<`_Too@rzH1+G@XMrZx1VHHxh4?*q89)7dC zx3HOcwW=oTUSLDcdF?Bpi0Q7^|1mANYz_Nn5cB@N29!Sqr9DTfuJz==`XYXB(SE=4 z-&b~co4(Z8>~czle4u6N&Si-9vZLyhLY(=Ro`ZXvy}Iz$*Lz6-7Cmcqbsk2EV6esrhwc(_WF3fHMv{Q}E4ti~Ek;%6?wr$n4IN zYBeeuw&T{_TCi3(Szi#g!bLGrrLda?IsTZGBiv;nq(3;;*JZU3=kw;ZnYXj1gpB_b z=19FZIgvHv(%LGSe(}p%+s8b|+jDcSS!E!ElHBrKuqm~WaXld39p9s{Iec1V8;_2T-ld^fMPQQzZ z#`&7f(IKbI>(J58i5#4Ig=U;+&y6{&zixaP%$k9_FPcIJzs~~#G$Yu8&wCBSK9pGW z4y@v>f-xv*I3Pg9GNeCHs4eSdgDle=9o>8hl}YKz_0AQAhsxXa`FW(_}{C z3V}cCbCzATl_!queOc+3yVjyfWBT>R9E;1bkAfZ?8L5wFVO?I=K>f_L=Ih3csMSM( zr*gl&RjauEy_(y$zp$WX@4KsqP^TJU)A$hxN ztyJNcwOwhzDaKdg=M?0hl3Bi5|K9nUl;1~<9ag4$sekC{c1jwOZArhcB~0G#skH6I zi<+4tn)=$|QcshwuSglI= zrCc(5*UdTd5A#qr*F>0%XOLaoi!s`@*G(L)hszuRKIIG6g1;IZ*ekC^ef`3jY941a z@?{FH`3kdW^#=lVc|0MRJ`Z_V)6@e**l#VY|Cnti*zYJ@xK=>jB12{hW#dHLi`UwI zB>BJI{>gRMMqH@1VO&SK!YwFJEmz9;T=WE{VsWr>!tZDIRqXtealltZdo{}#cEGMr z{4iC*g_ir!azka7MF({q33=^$x}xZM0cO6i;p>e3BF@US8hS*=&6Nq;bb$^GKb?BZ zba+tOvqEKm$cvlZ)R*9aMwyP)+B93e(D`$@k-g`XbS0mSd6aFvTD?|J9#TA}^d5oS zS259)Jn8JyBeFP!x(JKvw5F$LFVAXoc$>y`x+Qnwuc!nDZr&8!>u|`t#CTq7H`)H{ z-Hwjtt0HSRes<^S8~hCacjez|q*gtdj-AXZtye%mA?{+bH2C`G)|Mq>!s@~2bl#Tz zuG<>74Enel_$JR7RxWhfOv=Ia+_ic|_x{*>x%$G4JY!~(=e`d5AhgGTRMF?D#^L7f z+BdG%H%zSL>UlF=UJAYf>!sR0KXtrIYSMvacP4Ls$U63Sim~cP=&^1r#-2#xd9ksF z;FJV02k9WbR_MZZbS42X{S0%?n6a2JE zvZ>Bk~{s6j3+U;5t+`2yT_hd1V#(S;hsXAEM*5zo4I(48GShRvs$9s1x zaQ+p({%%9P)QY|~UP{`lFi|XzWQ}?k?pxL8Bw(~--S!+|OL=w+q+RnAd!vzknEI!(73m2W z?D9}BC4T{I9K;T{8fPfNg#WlI!L7#f8dI0n+t9AYF_m)Ymx)_9@AVY7#|zF@xG#wb zd&_oD35X^PRl5}WMPf?eO2^#b59mrQj(%hmL-TPjd_gRtnC&xrIZ}oqVMkoADqi@F zQ-};eaof!y_ST2*S7n$_n40Ptc=ITOH4nPO#+TNDY3z9S_H#Ti37PQEACrvG7z9GS zi(oGX^`Ef>^VIS;`?N0zp zw%7(5??|W7&1X%mgcI~Rm?hpKWBKd1zhe|LqlxEeALQ+vADV|4tSGGPrvPqX(C5n) zs7m_T>dPPRe$I(CdzBkLR>imisNK0}%J_k8a3osr)nu)z_$ zdw%0?)7Qc54AibAJ_uGwWC+k65*I!;rRU)7q7v=`uRHix0kqNST?-QgsK7MBN#0fYK!gm4&fnX@cF9%5-Z(gP8Tci+r$=iS z&(7+SMk`dlf@;~-E|^B*rEFK$v=ajxnE6NsD3yWA_uyKy9)+1ji}C-PkxN8?BvC&b za%G6R(TdxgCYC#mwK2*wqKwMfZD|iOp7&RG%|>PDQYc?p%)W#{sDpwPWxH zy2%``??Q6<*}}IJ?IGX@JdrD=vMvGKr4@mz&r`?MaXdxxs5C`>RiGW@zFu4PV!LI8 zZ<378yXOB}OgIMDJD!z)68Y{z5Ndea1?BgwA9P4T5K-~XDe85RQ+<(i}hb9ycost^I;R?$@q$O%R| zDR7{rIY+2Wtd3YXPqxXk41f4r~e{SvLUf=<&xQmtrDDgDdCr)PmdlVum< zHjy72TI$NsH1a%v7S>LDWFG_>3%=wgILERX@x6N*Z|Hk`s$cKoUsI^;996n&@f6Zo zA`()UNzVmcNeBgI9b9!t7MNdG79^&{e1!~*HUA7$82HGZX^iDbDLp&F#BC-dwch4M z|3cFR|7)fiQsVR}mai&Y#RW!oZ`D;s;)e@N zmFIU5lPo2JTtEpTx%UWH{2>&#}+E zor9qz6?v)oEBRb*=w`V))*4FH*u4EC2vF5(!vAxI{o$z|w9ELL;>c zAu62KG`n@Xcl9oN%##-%uH~^Yi&56GMhYMe#4mAqdI5lL#WT1`=x`7VY`hcA?Oh9? zW*i3hh0z_}D3C-$v$oe;s?IkKvwr}CrK0XQhlK409z%;CX<$Vn5yTJkrx+|_V|2oT zkV{CePOqkb7XC+7sT%dR(ZBaHHzYNG_sZnIJd>Onq7r;<1^!z@61;3n?;BduSON~; zKTT3Ubl%z&!U$I8;pxXlE92XDCqj_z&1)kxFZq>M>jU|Z&JLO4&z@d`{S#hqKTBiS7@vD49};4j3V-?*Hrt)iH0K!Xv#EH4IXC1n zTW@#1F}@cTA8^@`)BOlc<{^3IydvIP?{d2zMe1lguXR)Hm)Vx=-a|0!*G|HK#IF1^ zy8AXVVo_L*Aq?|5;3FRRDo!NqWwRQ3{-ozFaR0DPZC2Fg9pCuEHSUe;wFR8~QitN4BQ#6>?uY(~{cM7ejvaqAQ*!ZVU*zSNDI5q4Y?z!g-eR-Fb&&!zfKB81 z(+3+>jVWs%=H7Ve+YLnY^=r24mMvuv)7~);Hh%wjdA4>lJz`k$^al3JYhHuCwUT}~> zq@4gRqAZLb#Gx7@7ny8gkKdVcSD2}^iDZo7=8JwLNH%0WczIV;ECGcr#~uGk+Z+e-U6Q<^(5(kK3?zmL5zht zh7deAs*;4TaUANDLNBC|*FK?My?eHrVC48$IWe=_ixT2Wll!_^W8~=)gmF`QJO>r_ zoCCo|my`J)q`Wi~`DA!I!X?qCPuO~Xu}k(--((#J=k0;9D~0mkwEtu3t@n#%+Rw<{ zHcN`Tx$$`GN!IPV9V{0O|J|j#J`X&tpJlST`d+i-b^6{&ZIE)eRHE_e(PHTdQtw)~ zzR5oC)j7TI2ZBtNclbLMAF~^VMgKqXiyEK0gQmM-*4-rb7Zm!;$2{-8kN_#PUl?H} z*v{pMCX8PUu(_k5A^8vM)Vnc=ye}c9ioOU~sH*OOco2htbikz@IU~`H8~RF&G64KP z4Db>?;0wlhtRQTRYDLv2SIb9pRI8T3JHEd?8bs=VaY3=!QZTjm5}aiXl3zD*SfoFC zmTf624(ln$+soiX8_@IoksOTf6M+xe4@u7H{yCC{lc^APn6eKGfPGZ(4J35Y&Dd`l zTQ(Ta(uT^_gzz>-GnHK{EkGJ6V^TP=W~o&HkNsEk|7VU`MkeY68j^?B*WO6R-qSRP2m?RrA=pVwV5ygONxA1grqe*5ab`du3hvP+ zINc^f;U9YQGTfZ>=$>++Ro}B}y=xQ7g5O>boL_s)+Ai?|+3^_b2I%Vb=xC70EJbo@ zIvndF!SjGrX)vW@P)6aoalM(8Q=hx*o8{SVcv&&;VVQ={=im!!pI70-)Bwa3pjkyz z;V>6+66GA;PQ5F{GLoiF+}SpoY;kfs5r`D%66PCWBM`3qwjkAh(LT_3kx&~myKa?b zpcKFQbzs1&p>=n)nHA12ePOyjp|ZgaE4j**2&7*EY?SaWFfkD^fvYsdEK_zN*}&fm3;S6A-(gr?Yk_}Kd&pP&wnQGrAe~{s!~lz4fpBa;aor% zJ3@X6Koq}9R0(wIk$Mfm7il(B9as@Qm1a+jMY_+>D;ZKJChOVi$s31J{}^c$hr%;9 zvSzgpu9}G6m5vii6GK?ohP*#p`9y`RndR;uh_lZrg~ize=hAY*>)z+naJ^#r45)i> znL-rCvjEvRK5rZG!D0JHr&x>6AR>td*suND2Fm=OS_bXAxQ2EtPur!fjg^Fj%4M_J z#bt2(Zk_j8OhG}RNl}!K*VG0htb#GTfgFY$J3y3ZXGq|m5SE3%+a!nfAP`^!yCR3U z(Gm(|na&z{lO#IHZq z14}}IaD{r`$_CN(I41yfi7{p`MYNpR^{RZ4()38UocM5L(GHof96WY5#sNT*by_-C z47wyl;RcjoPbwz>po3Xke4MCS+vyf)E`Z;PWsY&2Q03q`yAle$mBp{N>x1-M#gO8I zJ+`niTIbG0b$jzuzD;*(4gUiZ_wklL(I{lK0NErXh9OM(#dYS-JZ!jwT(c!0Kt2iU zDXWu8*&EDnGS|5K?#)-hS2YRC-shkoj#0va9siVu93e?6Lp8ScdDJJy*~dbMxpN*aT%v!w>!^>_EV+spl3`$dAi zmqB$(ed~8cj&wptSU-tyc2FMC+GwvaCEQg?uN-uoKRvv2>9_t_e03dku1BXDUeja1 za`KopIoM;`#EX+xgYAoIfxj5P28MGr2~N@M_Otlj8Nl>h+v}pQ!5PfV+~Dg$jsejh z^jY;M2VXefPZrjhExmP`M(8GExvzN&tu3aRi^oz@XtY|o4%vzC>JHsE4|E{ zcZA(<2u1rO-W^_hA{D{&mNs)xD0?Qp2fVVhcUE-t{M%WslckV@FKjg*G$pnTn4S-| zcL_CS6pn!lp1YF!1ou`*WoJMs47kr7ZVlFZX-xc!4LZ!0mmNL`>G&Psi)*|zb)J9X zWD_$uX4Ia#*0H@!qm;hQ!4OawGtIt@lK+^%V`X2NHgv@4uBSb9K_{Lp{0o;pU)Ud3 z1*Mfz%6^K=j_4qlI1tG5vvx3%7H{^<>am|dT6?WP9#V1alreT9n1%_YR z9;YxbdFiZVEj)Q@;iPXW|Mz5fc{r*?mTE!+jWdKOygze66ky=M8c5Fv-852<2Hl2@ zzfj8+0^W6fb`iP^_3?hoAZS4ZnaeJ|pE}^7-#`o`A1#5qwudR#dZXb&L|<@1;Nm4Y z)m;>_7LwTVJfHwaDZS!O{(G=lhpZK>9XKn#zPa8YJs5y`8Re&~(7RhgDKnTnfLx?V zcLM>3(s6LjOJfw5UU9xgcRQPVO&_BjQq%=ChSYB^#jm%mP%M|RXA!fD94+irW*R@m za%nLfT-y+*b625z5hqEmBCS^ixtF-3ol^-~kw3l}j;FrqM*T?_D(reP_ksK3m&|yN zL+u-u@s}z^=Jp{HGyx(whGs>Iv!H+WLlzGq};Skfua{s1c7DX1L%`!Q&B;onC;uBT5s;- zk+6?T7wux+Y}RCtA#TDLLn27d8Omtt3FVK>`+ssD?fGa=P0FA=xgq#D%iTDT8DUGg)s`ApkCkv zokd$`ZPR&vEp}DI`k*xml$%}qI;tA@X9kWUdUwayMVBu8(ReT6;A_m zzwMOa{x9%oDgxI@o^G4+gc}3x5arr*2iMsx+-{shwryP#F|t*j@aI|RC&pxYOuc9u z;*sNqj?uC=FI$Uonge2>s5eST&xVCr_ z>uv zS6(&`BuPTV`&aU#g(xb<-(Z#Zv&fg7M!f}$UMsI!ecF*D?yOv~-nbkN0mHuf$BhP; z-Tl^^=XPXhZaF%oC_#pJAnH!+O5g!?lx23KoIM?1(gNBNLbX{n zpogTtkne8q)sA0}eZC?pDjQBKJIE$)BxNUvRU2k^w(++z>xeNfj2{Xx=t`1Wk0IUtAe_AD+1sIXAz8f>%xYUj$RM_T0;io}YoBdzh`r-$q3YpMf>VZ6 zLD&EP9dv?$)^)c4ZMFu!S{e}>-PZlG$qT<++vD9`kt!_Qd;Dl`QSP_e(|@-s-yiJt0e9q}^@$W% zsUG8ID89r{{Z&xZ857{oj8}Gh5Z#lM)mnTGNGn?hx~Vcgtw*V_*(Xd5pGfuLVn0^c z*yR5|=nzG8lVH^DHffS47Im<#;Z^ZquHKR%4yomnxp)?Zi^@XWGd$nehsWNlGdmBv z$MM`MK-Z{u;oS8v34-KfgX2L5pkAPV5S1L3DvI7f665O1$@E0-MT(9;nCS(K$D7Zr#MoQ6Gr?L{xBQGtW3c7x;O-c0 zVz4duqUzr^Wm3`4VS>RVTNi{&aq`S16ctyc>mg z9y42eQ!i8C>A{Ya_+O^}^^=IpZcWYxRr|-4MGo{*tjn~Mr#d-|-ddRvG_dMgpLNO` zGvC@+X0cdX`BOGE)B#GBMl1>^Bn;!^SL+(zPeU55HeO_e%+1a8t+9Q)-TYm%M;UPa z1}qq>!0!*!+280`g=yxB1j`*tL~BjuIb#%Go`uxDqg_XPQ+eQ8xeiV~gN0 zk|+q!f)H4>dBtOZP4<9Zb;xe{xWru{-f_(9&VNi^f#?5$^7pft_7|hj)e4bqER^xi zMIpHAvbzni94HP(6J9NBy2CL$wVDTmrt2fKcf-WGJAc<0ogch;Zxfo8O{WVT|t607NUB%0!W<#|GUV;Sw!M7N0vg< z&23E7&<+JHp_t2oNoxH1(t`7Y2u;Mq;%S5!g-w6*@<^@Oh1pYYehR7#u-P<=pX<+= zZwMRFvi#==M2upg62gxf1SE(CsAyihZ`E!=$}}rsMD@F>W&y%212(sfT%SSsA_=*y z-pdu8D>0$c0o-nEMtk*^Y5SHREhMVT{43ahV7>pwtxO&Hg%=w-FPTXS* zxZO@>K&&R=x~T9WYGxXb$b7ZL0a;!^;rYYO(Om*fcvrlcoDEVZu!u1SuIcSYv%(6! z#UK<%D1&EG#aQKa^^8$H!K1u~wTK1}tQ>0P8MbVlIw(`%>?qr^m!CMiK~M=(@8p*Y zs#qM_$mfG!Q*O$A%QBKe>i8no_H2io_}TO^;v4>Xn0?Dx(0>qyUmL zYI*+u1ew^;>*g3c76)an1*u2B-n7Syh9@dQ&;SLa?bJZnGM3$ddJnLruBLpz_tln( znI0g1)mvh|mA@TWzgud2VL-Iu;WtIeTV>*RaAvCD1P}{jaEd7g>Ecbf`61lz!?eGN zrPb@O{c>TZLx?aes+%ZHzRzGIt|u2LB_Re@bakpzw>aK1kO{$yfU4J76C~MZT2rid z$qV7J(CvE`eArjCX|G*Kf1Be(T2D=%Hr1o4YRmaOcV5d&dS(>qWboDa#j8Oi-{x3l-u<3#XJ&Z`;5& zo)Rxpfb4Y^3Z<2}=Lzl}-4@;{z=Na7PtKL+&3-!FTQYZXaNoiIA*k+zE9e_kSgv?f z?!dkB!bd@^N7E9s*}BJtY(R~@(i_her)tIvSDZS;M%8RRF1L<2;V*5sRr`-g>veo_ zl*4bQH;NxPFY)(4bplA0T}b|b*&OfghO8Vyr;4YiXILrwtZ`VWfUIE5Dew(Vj}=Kl zN$CLBHlS+wK!A z8QsZNGFr!;yqgR~TaTJ}8<-d@Qv#$C`1dv9sLIuVS8T|E^vJSSg8H+1kP0RD`(}t4 zIdlu-KW({7HvaQ$R^pHwVQYzoneL6@dY6s+g-xL1m{6@u$-U9NVMgs#RAim3m|jnt zPIIb>iN3&(L=CUFU{Yr`a>WA}T<;gs1dCzB}m^TSWlHdvX9h`uWL-o0;EKC2;K4Vrv~ z*leEUwtBk_kPF|jeE6d$B(WKGX&?3Qe>`3FTa)eE2a%LUI);FP($YCmX#o}K7)W=+ zs0~EA1OyZ$q>+;DE&%}@B@Lr{BgSBZ=e@tbynn#9+XY?2Y+D?P9DG$!tDp_KqHcasu@RI&RVvOei%*3|DW1 z=Za-Ly^AhxndIHe%1n`-sc+E97C*20kX4#(5A-v+*|EE)>9kq(!97C$Dm7xhKO8^g zVq=nj#p^nUA#%#*)Uk4OS~7-4iby&sY9imy1~7f_5P9p6DnKxq(eh(1xnOnN#i3-+ zsK!RINY#t8WZpu3b@Nhjn#AIclDb}~!rR%C#ls<9Cs@ciK+t$08mti2+&)zdK<|;54&!hNCZ*r>P$3$KREL8tNypo z3`U>0SL-fIzm^{&4f-{8F8mzIKg)wwnn-4=f2p{qJr0$J9Wo3#cjc5g)ha$eR)Xla zN_^#=&i_IttXJ7{{fA_5GS)qD{APK4w!v>Ke9L^l?mN`(x!ALfQd7Ic$bYJJ;I%yYD7sR3aH;S{+Q(yyju{;atx7a9HA1+$HtgllGxaY& zOoh#t3FIBMWqNXN*)tgSgr)h*mJ|)lOo!T&?GTUrk3IB6}&%Q*yk_n zlr2?yvPSboOef5)SsO2hX06Xo8BDvCKmkd=pHWP~Z?cis&h|f>GakEp@aN2A`;w@9 z6$v~TH<=dQ6dQgxj`{Xe5NSrnL&@8_mwRD8=>wP4zK=F{HD6FkECXgmqqFn(@tmVe z^-sd$CO?T!5lk1H=n1l!-xMGH+2VBy5V)quo<#Js95;+Pw3FVgY#kxZa;|gdqn>cRJF8ax|9By)`z<;n+Hk<(2cv$-d>Mef0*H}i)ChD6>sfkBXFg4_8)m_wj^BiROb4H z7U>tIK*nOO5-UfWEd27~Pz#T{KB_Xi+-+1(ve`$=R-vP%%Q5!g?Sfi}marRam@2Zk z`FboSFde-wa7WN3s;xEGj1c^ZnzcZmMQ}B%#?Ln!bSS-lNxh=~^@=-S(=e*)$sQF| zapLZ2{5^ll?0}u5f(DVpf}c_MHBwC;#VBa9E_p9)hsmV{P%NZ(TiG^P@qCz%Sz~4?9ug{iFL_8O$E)(0fgC*rGIN^A%C%c^vkEk0}F}h1Z{D# zVY{i*xKbRc#0 zj?W_=?x$tLj7Dai2xQY=JlF;K_}nY7Y|tzCyLm>=`V+DJ1k&GmrgJl*en;8^rV36A z9+7@@Oqm?C`)c!C+JU7UnYO)r4&SS-_L_p2N<;kOtBi2^x*5;MG0=XEQ|i0cQHElA zBw-5Kbkz&H@;QTLIzbDgcbcxlp0B)AA~Vj;%}F$zzUY(&QDKcN8=EveBwK&;cnGI1 zc!;fk{7Jo`r0VsPKW^*g%<;NQD6dYM+eOn?$tHbsxn2Im7HcD*TIYQ(Xr__V!8l`4 zf7U%EM8?TMLi@heMdBY%pf0dmy0~;+CP+h#-XuHFu5$1 z;!)y~YN2|QSpEX3BR>kM1scRHRoSaPalXWP>WWVre5vx)=42JBv=CObq5AFF*}%X$ z^CtNzV6%qiLQ9}g3ab>$3q5JW?=$N}G0Pi@{zge3Z9m0NNfHjKmzzo53|3(h_}#Q8 zKCp0WzImM#ODW=Ctz=ru=P-3nnQcaIGxNcjZs|XQk~{$iE?1~x0<}@xvD+gEGjviz z8u0uAmRm$MMdx@QyYU1yOZZsrM#e?8sP5eRsqW@;6CvK*YqRFK+ii=Ni+hQzzeXPu zho79zsLcN(XPeTQa_w#+PSx`$TUF;X<4|+&~$o1ZpWrp6kj~feBw$jocHik;&1gT^^Fro z=Q-3kriwu`j<_jxLipw0&*x{F&1Ke!mEgT%SJEB5!76oqo!~yw?I}v_=3vboSwi&K z<@IGvX_tZ{OddOhDqSb-6V!`Z_*j8VBth+SJ?*4l-Bo7Q@JLzpQ2LX#OW(X{QU9ZyKVg{Kn0yaK&ze$RH^6&fFpfE#wHlw7^ zWwNcU6M}6Z3bFEbW&T;onnXAd1I1d27e&%gggl8K@PaZJU|rx9ONzI0ox#yb8*eH0 zL)x7@pVwHr?A^FvLa~DDpn0ER)2*E1xx*RIfGEv)kxORD?WIv>KNDIavn!o~_I|2X zJ||URX5_5`cCNqq_9@l^y||9gnke+D8s7jDb;lIR2zyByd2>G6Vw2O$^x$2y`esB2 zhQ$$pk1aY?pL*|Y}g7XZm7IUU4Hu_mcs3U#>uqcqFsQi!Af53u3j-G}wlfbm8*Yi05yB(%K8VUV~@vE-Xnw#i3|m zX`)F2mN4Ey1}D%x7z5C^_9)*A;Jf4HrwzUE&k;vY!5g!4laE$H(1>p32LE6VQnJiDl5P-Vp6lGiYQ%67tk!BVs2(AW7PR(EpsAbb}DR-_ZbZ+~&@^)}XPrBYksLu5@qxZxx z1p#XhQ8Co8Vq44HozH<~vN5h(E1qen4=jHY z=pDGF@sEZRtaV949Rdbu|G16UvnJ;U(0sJi=CHnYo$?&p%2UtyeYTG7jg$Td8(_x0 zr+TFag2h-LJvjAVfV@G!(|h}btH|cGNqv2Tm2aPQ(|$KN!ks#UOlt5nDCK#M56t6g$xkFmNzUb4Cm3F z*Y&eibvDP_8+$E*RtzUnPq4Z1eX*8EWBHMj_nm-M0M25fQ)w*( zgsH#Pd8_HFxea*N)Q4;6EG_syC`uHntOFKax+~M4Y`-!GP0P9AtKpW~s4QW-3;(Rg zCluz=0gBtt=XbVw%WI}5li@@#&Ja&TLk;7@&+^Q1RlZ+RseH7-4mj^3YeV+pUbWYR zL}4(W@etxQ5Y4_RNw-uBUDsE~BLFFbk>{@cAbUHv9o8}_>l#o~19ugc84PMp2DWqsfKm4!8)%y? z$4T${8)iXHc-q^Rl@@7)cq`=CgB&^oiFf)y$ytUqMUHGcJrG8xHca<}cnw71lwC{v z^!)Q$rdx~YADbll37fXI2Du*KhiXUD=((Tsk3CyQc2U5xDw$HzypGVC;WK$(7q8RS+Tx;N)#AiLHu83#H5h z*bH|TCeaW13Av@k@^aSC@4Os+DoaFk^=`tQ@K*%cuz&`x|FkU2 zDtzb(u>4s?juv8JMb?zLxh2Q{cU3RTe*`?8@b#*hAK0j8D89dkJa(`E^mz>>cD4M4 z(*}E4VYu7+XZI*R7NQ#2e3IBg0-#<*BoN&?U>gX7aAyA`%a}ZsjxCz;)5GqMQZ;(hfEPEzlrq=8woDQ< z-(}Wd&8i|eK{mN={;}KP!Mq9IPBhVp(f;tDDC3?Hh*Hto_B!;NmrT@gQT-c=&fg5Q zk^kga50Y}zu~Pi8emV-;J?YK9tjgzv=fs^C9RYNvqYUE$1gsp}hP+pC=N52{&cAp` z5s}N7!nS7U1nhYC*TzBCl}w-Md0R#m=>p4F%!@{!)TgfjI_HKQ+xh+zRBP`M!L!tV zfPLqs)qe#4!&@V^#r@qs3bsq%*<7=o+XIxQW4H9hf8eg!O1v6u%?ohb)%zeCz9;o& zmU=gN{&p|KS>ETDKT#ipWM=3>)X+lSMBC5Zj)#2)XT`uo*K>O`c!s(YW51hnVaf4e zv&K{pz**aD_(#25laJ|?N#ke#0CnRsIu%gEYxm@=mcKg#`U2?UzDVwTLcFD_jg zSZtxZr>L~U@x46+w3^sTx3M{)IUznOA=xwbNL#}C-?vZ0sS@w{N8klc`MOg}IyT!Q zk|&w(jp;R|D!!X39m+?4A=yRJ0R=L?Hb?gf(;peLf_8ir-f?-;n3Df{WrdHCc}!Za zq$b(4cgrt(Y~3bE1W}k*vQPFYaw+OIIj-YwKU{c( z0awLQBVd_T#g5@*@G4jZBp?_Jk-f=v>$($SfYsSpjU`^tSK)1B)R{S0r!BfZJzxd>f*Egx% z8QR`9Vqe*xj>JdFZND9;1;R3wH}8HV8=XK=z%`g4HX2m{e@u(xgrZg+_N_Z zcnveW3hou78H{t(kH8C;Y|+_vBx>XoeD)~p$m0usrO4am?PD8}l2=Te3WgzW?EHM>;zPPm zic;P9ee9z3On2^J$|Vz%bbFw~1k;`xb}vojEawXzJ$(uLBPM>jb6(kyjz5iqJsY42 zBACmabuoFLOO)<&7XHtmN~P-9?e5@*NqT%fmySVH;GeqRi-j;+2LL+kD5kd8vXq;*ke1=pn~jb?+Fpl2fmF-LEe_`{J`16>W(QD#W1)q=ZpgAeY)D&EGsJFa< z;j`5zc`Lcd5^l1OuHYaV;e{~XPiM(`TJ`SBV9~QH0}=JRn@Od!m3>fNL>OO-dw1p) zem|f8?j6#Qw76WKAtmQ>?mL=27w7q8bCWc;4Oae-8VXFvwhg#irIN}?&TxpQKH-1Z z{={+*UvF302=4aGM}^kL%y;{<3l)CvoxG^lACTASjw#TVz2H>uzs`x=cZPAHm7{$Z zVD0O;B3!-MM2mIqi^rpFwUlI1KgsRi0U{kAAYEG|9XT1xB@B$SVAMM-d=SENktkK8 zD7QAQ4vFZ`gmI@TRnGcL{HApCecfL4N*|gSrVv+QQb}LCE)R}j&B0kW>^)SFk*vPjezxyXVddN_5=q zqD|}JdH|y7FhE^<5aKnlc4d$k8#jvknPU5Gx8KW$i7d2(9i+E1ABmwq%D#EfFE&K3 z$XT{ur=j@ZyYoVB#Z9gA9Z3~d75)#MU7zn`91Q&gg#B3hz$tg77uVxl9vjEXj6BHP zx#IhD+#k6)2PwmDom3t@n0{b4T_dGZw%4ZUUpp>2+f=_q$Gapm&Y}C@V@ziHvZbH! zQTpK0*|JbG!`^fD)=IaXPvcOl)5RdtD_(wovCcqD^@p+7e@-s6x06`TjV;Mcb;wqR zg`2Vilp5OuQ4{|WbcAlRCZv>77^77N7Tc$DC*R=YCpnLk*V(J6Z}^ywiW;)wds#z& zg_W7h9uHSNHAz3e@^zz=gz9Y8byj_wy=SwfWklBhd*t3QZ>M=@+hWN8myU>W$3Og{ znOc$*#k&U0Gq=7?O0M%ykobS^JELD}LukJgp1sP@@h4&yy#G;6gDSk|M5VT~0y}4! z1_V@XZ7nr1HM0R_>oU3Yu`*D&cE%>5#0$LKMyitFxJ}lmR3q<^!uOd(0D!Ff9Q#o3 zA|y%WoTo`Ih9_*5wIu#^dXbBQnF-HT)l93(gM&f)J^2Pt=h^0}%@$rV-aa~D z|NL?Nr-FUNy{?^7yeit`BN)I0$n^5Dv+O58P(uSGvZ@~{Gh_;mRGp397-LnRe>-Lp zh*F*kZ{!2RWfkZ8x~o&G@J4% z=u63Y^GxWQ+u#a3Jy3K&j}{zrRQ+hq2nR8$P3cCu>fUn)SCP~PnC3l(c8M+6H*=kP zyNOmM#P-$Y^NC@&VFuTtIGgSqKoJnlAhXhrRagrS3qFQWEdBsej`0U*`l}}SAD)V1 z3S~wKR`CHgSAcdodEwRoNbR_5X9(I`CGMc{6<^lxPf;5_W62-Dvg?)z|ar^rXrnc$E>>gucQYq=+$*)5Zdm%-ZHH>owAN6ANbcj0@R zuSs`uOOcOdKG=RLlk@m?D|J43I8L3-pAf=arBsvz+-#rA_M8cyvssyySXd@@8+kXvq>#{$W5uD z!H-?wUhfDkc}%J~vspjWq6i-@1?I}`7aebasprm6TeTfQ86VM*rvxNxmHj+BnGSja z$$gHHjJ1z5(-MuqXc1hE^)0kPqalrTonPJ~&pb&<6^#yd4#$41skpg2 zk#F6aPcxr)?{)^%s2*E_kfeejhvJLPzSzWZ!e38GLa5E0X5;eRTRKuf?es_cnhI@m z1{-jI`EMfqu&{D0xcl4LY#fuXS@MbS4AiC$FD3}xVm{Kr89HZVn!a0Q?|Anj-`Imv zn&}c{BPS}*Jm!BsBq#+y5eptKRUNw>L9EVf`2?ggZl_5D32Sp>*Pok7-%w8}I#@lG zuQho7?EJEVcJlG(`KGe<*d_9<`ip#;+J^2pAe#Cz$<6wM$3pzOx)$xg#(Ou~mgvsz zu=6nu8wvw*4XxVEgbn`kM;+}00ILso`f{->qFs~B^`vV`sFbM|n%S2t+B)s4-kSQj zC=&8!dFxl2x;v-28o`PhwP4Im_PH6DDI@@)yjo*9Xk7%Q844<_4Deov5blcbw$_wp z9F@#9{dt_wL#wOawk-Nl5*}qqh&FX$Q_DoH18^e9U`Cm%y4o+)XnnVSYMZULeS{x? ztWME1d{>f$LnbFdm_kg7#jeiVg*6tx%3UT3+6=&{l*OaH25o0I@d^7(%RS111wymC2%VA9d?+Uqp5d;f$WTC#8F zFOXr1tC+=`!V5h%>}uZ%Rn#$Nr!Nt8*?&D$B2xU+xzhbSSPvG2Ij<=IuVq+rp)8U= z!X%*$&;V@@hW$KRH@qlw%uc=G?2&I-!=hP6UEGUH-cRlI33l0c^FG_0y}*P4|E+rt zeN*?9&GYVch#7C3&>Y6|CL_9j-h5IP07XNnyM!V?MR%bGt8O!X{JSciLfi=jZ>1dU zJp;8`O5L>H62L|+2~jiERVC2qA(+VY{cI2r2Kp*i>M$G;U0vg=Xev)w{nJbNn=*b#tS z<2VsuxufQlcfAhGzWPwnTkz(O?sK3wy5)Vg5TQmNa@tBuqBKLRyCT1^;yIgIGG?|Ou1$1dXlFVbI_ zBy5Up2UxSCmBps=XU?zi3{@)!muwuFhHov3BPOL9JjZ!|@CcGKYS-UUBRSb=etnap zOt6qI5#l_1@r>lTnRAfZH^@KY$lAQ2uC<$DKuBK*Z*n-YzzI5nY9|x*!lnKrAa#4w(i9_(nci22@!VV{PYXnjO5+I5m$h#xG;!em!o94T@Q?>+-7{_1 zME!}sRc=HK!}tqV+qsF`M>nl_UgSLcD?}G7w9BiaX?J|Pp0O+V!?PMetQn33+dfFw z>jhj(04DQSjB++3OMV=BwP~-$LRvdnqjecC`menQMmx)3&Io)-W2|%1PoC@{?yR+ULkLN|<@j__T;YfSbYOEwK(LsME_nvL*nN7~4 zm#=$&5|XmWNu}o9d5Ahx=BopK_<~AzKxDgY9&r~{S|DOeY9Gq-VN@T#c8242 zQw~c?M15R4PBg^j=S^fLa;O_81HBx)maajQ4wYCJLfc>6&L9*aj;?6T1biA^6!0H` zg=H*qH5qibOVq_u6!8FEQnx@*40`7%~%|QfzZj(_HC%+PM5;*g2kmFOBeH)M>bDo zp*~x|=Re=Q}XmNb{Q67DOybucLD25Z) zf-Rmay%-|xJA>Nj%({!7lyrVFGt+zU^?f|_*#yZ^dsDTivRBje9SbPOA%{eT7^fFY zjg}d2lv#cIp9>2~X#L;^cIaQo;h`)qcaN7jW8y`3%9^Y24XTPe%h>fjX2dvKaS4~aa(oNKVpQE$>Mx3fSwd87yHm&}U8$K}TOMmP6 z^>Tz4y{FYoqAIuiZSDBk<~x1zk9OfUhed?{5roWD$X=+&I{ZuA{!-4dvGhUd+K3eS znZ750fI4vTH1GGEA7!ESl335i7tBw*OC0*`Nz7V8kOV1cCu`J9tR7gVfg=P|Fx&^> z>Sx@_&GE272ft0y#8*!rCVbL*tN|%md~ygfqB%wL_|l zrjLL$C)Vd?X8-2NQV}9Yyh+iWucr%8+u1};@~+9%gq~F*RRPeom#tUnN^NrzUgh(q zd>BI`#KE>gy2FQ+U*#RHsPJ}*-DOT;#e*9blkEI@0X1@_FA741t0WQmi2t<`E{B)w zY0@z@{rID4g|HlP$6m$Pcntk~w-0k=GW9(onC9&>qov)aS!xP0Y;2C@{o^50gz8G- z?wWQBi9d+RH;XYR{Ln+!E4f>pGj#IjhaR@KSb4q+KOcNI>u3C|E^6V|UY=v}<=h7nwan#O{eOFydw!U4X_teh zdi#kAIP+H`Vnu7ckoWb~jqLGbdm%T^wa>G+l2#PnBx9)vY$Tj8$A~2zxOW`P{JXd| z_S*0>*DK7p4^>X?S6Y@g-L8mWWa>iS#lzL|af}WN{VaMkf8@b=g|}0HkA#Jp32&gy z4aX}l_GHuDI}N6=%&n@i{WlGjxWwNIfJJ&Z7 zsjjq*BTd$5i8F!bYSLtNhgFsr%#{Xz6$bDy5i+&;M~&t$R}-a`wA`M^=Bg>XCPsAc zECg@9CP{3p{$}cwIK{1!;=VCvi0LgmZhV~b#;tOzsS%#O6X}19cTv`PE7)Eb;N5g7 z_WbD>%V{21Yp!9sk$t+iNu_X;1!2X^atVauU}#tN-wZOP*buKpDjvkgPk#A66gcj~ zmbR+y=`Qs+Je9}j5R=%bCQs3H{f$j1wZ~7U-tBb+hxAu&!l5SvvzSZ&aW}@Ix-pp( z;?0wY;UIz?#Jx$ukP4}~eVUA?(x>-*OFO0n@7J}af3#AMG^bW>thg_}SfLXbggAse z5@6n;fTe$xsya-Kb*r{+isy8&$Ogvni$8bg7##g&Fih9>d0tXO?Y_b%hWCaV5Qm>p z(iJpcLrEF!IoVvymR(+UM=1!)|6#2zt_#^0B)q%DTqw>-?ZU4={hQt_8_s0xOs^gf zs$1GS2=MXXtx^VGu7nRc6ujQ@7;>^?JnA0|OXj{fJ8_)-l?xyf*eQdBlgr29viKTDEE znZ5B>PiQDrWMxmVk(C_NWFBaAso$h6L^i6}$Z;Y2gGg_xsv){7$v0`|-3-V4@-iXGce;_0 zMDhoDHVe`lrKT*_publg z3t#09AqIu34Pvx&q}6&@6HsBnXmjSohSmEJW9-lb60`9pvQ z1pZAiy9c(o4t`3S7l*}R5~fR%L`fb`v6{G!w%R0s>P@LNF2_TFK4Eex0o&<@WeEe0 zKt8V5iv-WOqH|~V-_BADF)}Wy?+3(pJ;VYjD`fG`D}pG-?zoPJXyv&+HtB9_jEP?< zLg)mHpgy^BS3n<_D>p0{oD7^KD8mP62(i&UY#CpjZ+T}f#^26bXdialHsW-;QmMVb z_|rjH!17XdyhAwegWSF1A!MLbnCtgC@BUZgxZKvG#cP8vvJHnpbHIX05<-A7iUgKY z$+0{Z=;S-}TOf}!NZ)Zzy>I`^p;#OK%&P!K6NPLu^I;x#rQ;T-E+# zslm?ORGu0(tMCzyxzsxh1BNEI43d?cCD3`vhnuG@JD)v`>ojV^y z9uWUz?e=%sS`Ju`j%dug2TdNxRBr+9plrV9Tx4#l}CFSLayYc`qpkaS3=|(q$GpQz`15yNS+s3$= zsSjgxQ}`Fz1I~K!k6AeFO96_61J%{O5sNnfUP1?5?9C&CF^R@>J=C#7f<&DB*zL^H z9NfgN3XK9EtOO-SwSowCfzWB*kcZe|KU8)fOyWaDve71E{(oIwJ-BguNB-X6+Q>dVJy7Xob?{r{dFVyEu`+3(H4Os zT2^i(TvyG@G8X5y*ImaIj{`$D*5|^y?L=c2c8(aU@Q)FSQfoE$_paq;&O@J={S-k? zKj;KlH2h(I zyukiiN!)ma4;v4T>vlYuuOHGY+;jE=6aQ1a`Q(F_0ozm?MP&$Tj4pL2-X0H|vu%5H zCJ$F|It=)m5?58`(co1IG~MV`B_9{BR7AffN^Cv&+y!hptY z(Da|gcQ=5KIMEKhL4nPvjQS!hTm$R%Bbg?V88rVK@f%)1c;+yhw~49h)r%T(Q_R#9fKTU3`Pm!J z;9uIz1Qwx9j?qqfP14k$)9MzQd*NhMXj@*oUJ<(bTcESI@IP6jCGW zFb1uyX8b826=#?LdL_4_xEEf|$?y2M?zwctFQV-=BdT>xE*+b}#jo*jd-u(=_G(zC z%N$_wyzGUL<7L*diV$9BE`b@}2I*W-ZSswXI=AZ?$2T78ojFPVbp!G^tFH4AMAiP`LWj)FibPwHoIXkvLr@C-I1^ns<#lvGR73OW@|)8hUtuCe~CY&H#xc#@bBX#BGUHLQN?xnNIyN;TuwCr9(>KH(37fu;r?aYzV>9 z9-OVi&d&zbBN}_;r=xG!Hhpn&q<5rkX3P&9#dd^e_^X3cFUhKxYVaV2>F@>^IL90z zX;%2aLrE7wesAJ&P6hE;jSO(g-946yJto@Ah*Pr(BN6asPih>Qlv+#ZZTWCY_YGO; zY$PKnmh%mUjabPyspwR@ijdye0Lm`th$PvY2^>$59XuDjNrKE-gxpJG-)zx{PP27=$=QYdA;mJoX(F->jMjS^h-QVDoXffG#_w% zsuX!BW5nGc$fH)=g*vh{N1Kf?OpJc)`Oz!CqdZM`b{Tn2Wjbll*r5@V!HP6|-eCps zh%|_96_|+m5(KZ5QvBIHL-5%qNBVL@q{WIJ(3jfrNjXB$|3 z<6}|PXyTQBZ<;xPimx+mi)Vo{ln_B5wuj>cM8uo>=-v0SpL1K9GImFhV z=o1`i@et-)8ewlCKv#uz(zv~?a83YRIRA6&wEdCNP?iias7*6KrO$LV;-sNdI>wbD zMh>9@_EVY=d6rmP&OlERT>+vq7j*|VMRp(d*)p>a8Hvex+2c?4Iw zRpG!b(L+~HpjvFULGpmSkTugB^_4;vr(ASd3H!qF=Z++I;Se8Da8&Qk9A3a%CKdEK z+35nAg%HaFyEWL|UHd@~rbr}z6tZlVb2K~>ZaQT2H~h|$05?$@=(nEf=ly%_K}Qc- zxIX{-&YCGhi~qZ3EnsFxTPC6YNmt{QL3k-~|5!Mm05b;{>1>WyiPPodue=Ei=auGa z)KqAQTL(omV`Ilh2Yu_|SMOVU#xqrF6US8P>1i5Gq8_imO)=vQ5+NLSN|gUY)&KT= zkZ&2EaRKRA*Te4UtpnX7SK>FN|JtKl8_q;DN4dcQ$``!GI_dOJ%2XFAO7GEff<@p@ zYIc^CU)Bfm%2EdgoR{!rfSJwR6Q~@Wq*^k}Z`>4EVDKG;x&qy2^ zpz&Ao>jwQnv(eK^rgbat?=gY2)@ESY?XHqPRf;;O;OE${IG%%UQboEoy#>LI`-yA9 zHpu3rnkuQsA;dOi3@(8Vh21+%{I@z$}%@B1;gcLhl=wOiQ&qH!rzdS%&fKaG%G@?xgto z({h8#-LhrNHCPC=WK!!U^Y*FpDuHX)1Lsv{UvP9AV}h~*x+L?v&ZF418?7~s(?wOm z(Fx36*xdw}D~g%%BnVbad@g-yI7hc^x-?Wjzw#Vckj`RfLGzun{aqV_^9ra5&5UOV z7_fYR4Mh2w4uzC=3i?=<;R zx~>vG@38ht)w0GGJi(fL_R1v+6%>KK`8=LeC#uS*d#}0mv#J;FXDP)pIUwn)_F}_a z>TG{0CAC&~LH)TIQ$xtmw+Lu2C@!R|2ETa!pe6|j!o`)lC`d-}Km5dnM}|FW$}mX} zaNrEDqLUB*nX7=C@riU5Sda)$`cO2_Ai$TnT16npGPiAR>vLZELb1As@@SI#T*}~1 zG;SU=(U6iMMiCzVjE(1YZS{&K?!4F20@L)|pC@0qRpmwM5?#{g?;D^tcky4!4TPSr ztl6i81$O1X8I)C1^%CFeH*Y_xn@e7aNbRtxcJ58rSfE~B0?wqaSAnwptQ#qBdCPF6 zAk#5RY8g*z@(JfrX+2iCjXPodd}(Q#34e2QkA4Q{X(>3=%98FqV?C^B`DXB?S?o&1 z)$>`|68$^E5m};6AAs>p-zDGBBM*^oLsK})PbQt1POR!%h#d$P4AUBBAdO#qfAFIG z39FuxQ`H};_yIPf*se!Flz?U8hQ~dqI+A8!?5tqdbT$5=FKQy3SIu8Ll+U`zV&X5) zM|JK|a?a#GGRkyQFbeDoT`YeE)@LA(5?~Ul;dkNAf`agH5bZ5B^d3&N!=*^Ld693r z+K*f>y<+j#eX+U}UVj$u2%(auTVW{stDD$c))4)h_-^O!h+J-T=@CPbgdkR*bj;rD?Olhks&=YwXIDT5ZZpjZpEDPxj0nC0VlZ6C5#3Sz(1^lHf9td zI71+s4~nfoF$0mPC-MGyG;64)(qdDZr(*+Yiz!Tt{%s~}vyxx8C5B#FrAswSTK+~* zxk4Y#^~ix8K{O%WXyzf0*lw26n}#k1$TBn@nUsm9UKrM!#UfcHd*gsoIv-&B*+%0ZW?=6 zThJ-C9mluFd;5aV`9A{mF8Cliz^mAF0kUyf5+P}7q z>Najf=M-5r)}zRz=G*qz|FL{@T}=K=Tm7lvQX!1A8T;Bsw&>Vtw;2;)8Y1Q*&bq1H z<6e{Y;kW)4ZvbDO^X~1Gi-c1~lWB-xfQ>-lg+jFOmtV5a%n~+O2YpP{iawQM?#=fq zHbuBqxYJgR2qufAeM|XPevWt1-5di7+$%hab>}e6f)Ai|dr&<>pI-;P=i3o!?{CY4 zIi_BC|G7!k);8DiapEE>F~fBj(YRIqGhZwH2_qIEQF;v+w!0&qjQkUY?_Tz&qBgO5f{TTzAigBX?esPWD1g zt(mD1Q)U~=#rQ$YzZb8WmKHwSAu%W#z%l14%o8`iw9Uv(4@*C{tW`YmwNG{8&%1j> zL^qQA(P)xOELXJA{MBDAJANt_@PmBM^qH?`!!c2AeuT}|(4tR|V8`zwu8kH!jqJ5p zKitz={>!}jfRAmLJTr4wltzOqeEqCZ($Q1fp`Bj6HFe!in8|+dyhYfy-uz8O8zIwo0i?wGR_$o^rkTDk-Hd@3t8w?#U#XKTH?^WfL?e4tbK+tXmSU=iSA&1(!KkXkpYpUj=|&616`S640v! zQPMc$^oC*bGnxHftIk=G35g#5!uD~95t|j3^Wp3){0uf3XK?_h2=S|QyjG8vv{0e{ z>%r}&>QDHI8a@kuLVzoS@*8ros%G%LucNk@5=cT4{#KH3y0l+3(tYp(XqAfY(_vi9JB(EZ?eACvV$p2snKv*NJgM3Q zK-&`YWA$h`NzzbfMn=F>BoN%SMR)f|Dp=pdDU*^?g{?e6tH(4ZL5C!KgEz{n>d`Xm zhF?!>4&UIOQt5OZ+s%ClKL8G;bHcOR*zd5hEc1QQ?zMs}|DUx>y>iWIYxebzzCIZ; z?ofMoy6|i7UwNT!G8QxG>fQKP;ub;>E};usk?y+E!@{B*N!TS$ySFXP>203Z&G*TT zXCP+1b;!TzQFqWSh3Lj2`EOBocOe*!Gt*gz_no@OzFz6p{gi7FPpAKFdNOGreE<&@A_&oq@k&T@uuU`!;=^oU2lM^j0jz!j~qWM-=@znFUM^L z&4L2b%6zYz8g7sCDNf)~MZF(>j>uFZcz<+t<1*g3xWnVYAAta|P2O_mG|7{_Cpluxc3lZdO1vUd6A}&EoIB0aNnQ*M#Xrs%fV? zp1`2FSwo6F8O&v!CSLjKO)Gm^edwTUpHnuZ@!N-AcS&}WR=MzE41>ddM{Qr~U`^I< zR43y@43J=ge+TmKycmkG`sxhxfjp}Ca&!AySNWy0{p zj#-f>k$7P^#wCwVCpPCn>gFA^S!Cpxkga6)XIraJgqYRC=nZ%>=>EBqDJbmPqnApl zL%zwatREe0+V=O@N+#44%#Gi>jh^Zo)+GQNm1l6+g3|+7AcEA2?3>XnFNXRi(w`KN zdvdM`ui1JuPS2}cK0IhaO&;dpCVl3ZPuQl)?}Ph^!nJq+f&&lJoih@_lCTWpr1{#j;@lEM7LvS&Lh6` zN(?Vh{;^&)3mr*}yqQi;jBOj9n-w<2wpbvwiffAbt;K`N%9r96>THY8Ykyc-5uW$p z%fr_aZ&HUDDBE&XcAW6C`0`Zqy>j-L{HHmcY5vNM1bBT#|8OE>X&BUd=|oFElgb`N><+wt%(~wc^Scb zY0)i;XvJnNdPICPwXm~yWe@8j|M#u*KYkw@vy?`%@~tze9UP7?W{bTvmkv5FS_D4RqC z1tR(FCv3r?5P@QrL3v-2L{#PS(_?+c@Qzr2b>uu*&ycc{pp)x_&zzKi(6Qf?7cf9N z$UT>@egs-K$CUo~@;>P<$@*JwcK0Cr(vD7T&i~`+Ec}}K-!?u3L^?z|q`yj+D6xqs zji@LMlad(SxhdTU2nYyM0Rf2-qe~hDL`IM9hK(2_ea`Rs1Gd-BcFt#aT-WtBo#vH| zs;M_Xp6{6$y)qljpu6=xE?$CeUx%tAVM#$~7VG61`%I(dKG$~_5s?pxEfKF-GoIgK z+(?v>x|bs0`6i}+Cu~TA`gaRkpnW+EzRd4($$`>4_`DKAlrv5uqHkoW}AJq5a*FS8s%rS@4eD8>5=YHVLJ&0A_NeS=a<>R%i6UUybsq3Ng;{n#={a32Z8@r0G z*(GM!!YGzK*C&Vqr}BtbvU6JUoLlE1@qVJkPKPGu|6%V|oLyr>Owr;(%@0@%8+&SO zzB|xu?DiKfT3QAMd|rL+RT}~9dTMJ~t1`8_J@wBf^o_VpLv+ZB8HxyqiiBUe2HZ-NV{Z2QaC zsKxw++_Udar6t1Ti;1+m#>r^px=56rb zvoDEXUXUJ?i7h6oktx)<8h?DjMLO*EyJ0+ZwWDWCk|wCtm~h$A$m#Of_#T6We7pE> zap%81tE(}$$N(iK6=*~6()3H6w8g5wQt1FV9Qz_LAgl*r1Nw9lQcr`S8AaQTSwFLkHt{v z%|A1p?kynF4bj}i#R;<+tO*uo>RTW;RC;z}TA(UgP3UK0iq*qeiqk`a97@gTli+kIT$h;enLk?r_}C}z}1?)5Fr%tI&3-;#na>C9RNk}>;U;i55o`G8QEiQiNzunBc@54;OeYKx`mFedhrE_7i7iMARXg%U8 zVff;awf_rnp?v48{&Kx{f--q+Bxm%5Tdl>@#^{l2S5wkXwewg^+K*7`IoX%9S%R!o zSaVOTc-s`lk_GZG1S9jX|L2P>jp^ArbQJ7@3M_+&6@&*`#6^X8qj5HH~D zm>NU(9mD#1iUZt!wxb-n4|1T{mzAUykTvg)M8M zX9_URmO6Sy1J}Q+>vgh=#@wF+i?#ia4y10_ zo5Beyk!9fpEGkFdl{@mnA!qSl(-~(s<^rG7P$_i$yG+N)aQkyr%onsUay97re>vn zUX#qzQP8;i;58k^b1%!V#Q+ZdNF=XG%-u^xPm;at`jR1^{RiB=cQ?vHU>8C}f%Y~A zm*#*aD7(pUK>iMve+wJ`;FR}WfHT%Xuj6L>-H$ivT^&ffTcy(7!rQ7jT<=Omp`3eh zjPhT}LPSfb8Hs5Z_gu!A?K}Qk!2W#5i&tE^yfB(UaJAVElho#v`TKRSm`)TfNk(1M z;qM14n#hNAc5pN_p?i`6W$)Y_5g>4PXE|f{1lQCKVZBtlcnHk#j5^ywp%lGc+|Xq{ zV$@YCo?gA3)d)Gwd)Rr(3%eS=By?++oEX)dm94=LojDACmBf|hTf*aDKH|l0mi3S) zl1cu%Yr;2@&TS^pLXs&SiIx3zUh3CIbKSo*!0mdV`BzeT({jp6Vb(V6A7~O~Fann) z2I|2~CZA_`V*HUn3Sh;IUQx_Gqw9h0@1(m+pD92Uiy!rT8i6~H%0K%}q}edlg30V- zo^BD=Omp@C{+jHjh8fzV*gg9R^qK|orZP!z??KGs%cRq4azCtOw6Y#YWc5{cE48-K zN7F7axUIJUr;AZ2CX7}jg)8lqZ0k;->e?pvwm`~$pgpe+lYGa{T>SoY}l-Qgdi zoyspM;=o+NP(0)plEuuC(I45a_$IgDCpgtlj4)Dj7|C!a{nnQ|7WuWelTr7pYAjP6RGQ>#E{Ch-uH^%o)wwkBZ4%F)JEk!ds27MTU zk0NfIpl&+>QnB03cep3x#LK;dtctd3ckX3PXqJtLq%62AwckyD212pXrY0f5?AQSo z6dBVK{E*WSbFyNZKf5YTzVF>o2-OA2waixfc_7j4^=OUD?;k?WDJrtD_%gbQ-ysOg zTw2w?4;>i=&th%8uMpZ3mdCCU;+e;7dzDu?SJ@Z*K>mTfIL_deei28K{zR(@8mZg% z0#S2gG0@?W-lpb_3xiHvK%t6K}la@~V4|iDd;>p{>E?Ferx{;?Av{Uuq`pFy#eup|U zeRPB;GI8y1_urWLf)#^Qiy}SSz53sMl#{#C-m9Pj3QdCJsVH=>Z%(tA{5g5LhiEhe<`NKOW<9Nb-O!P zX(hzBMA%Ag+K)xzm#w<2AH_e-_y2*Ov4@?KCPENUa&}i6Y`^!Y%Of!ZD@cUHY_Ijq zVWF3&-`nHT&^Hgs_O>2#yG5)jG^P#OQR@hy3gIW+{_XrDCsB#3(P4MfR2MyAt+9ncG*7QIClIr21u#j~=QA$@nJT>IS`?C6?&LLaO^-4nC*aK(<(J;X=N( zVNQBq37A+Ns`lz0U;E&mHy>i1lGr|0$*BL@P+m2fY$HMCo0*lEm{E!{ikIZGrs{_HN-RDo|EgpALp=c7VJ%nUMUFiK@k&io09~6S+Sdx zOO*A;GqIP)6L+&j0}KbN#JteMV=QMeTaS4LuZ5~Eo>iGCx~3pRsNCIqc_#p}&ZxK? zo~ugllhiY@54Qwe*&m|f&>}6V#-Up5msM|im2c37y!33(SmRQ$D* zwTFNY&AtuG^f0d`Avw`t-I14VYrai^(;SzTQus@Iw=f;d-$>GehvowtFKq<#CNO!f zp{dP+e(+9^`Je54nVJ`D@#M%z;XeXXl!lh=e*G}@<-Ria z61pz4k|}%dmAqO*J!m19;<)T{%>dg{W2ipe7K6DShaA)nHt_K#z#A_g0!bH+X3ZNx z1pxxoJ<0l{Ugjzt2M(D8`XL_uB0~2|R+^!;tE_Rg%UU%DDaL1p)A4(x?;d`o z%+-uat63fZ)4|azcUkGaEnz{uTpTe%l1=xVlq=IXr7^jwU=}+a>(!%(t#iZ5wBxrX z$zwF1>cC5iWB2@+cwUhtKGY6!VqJA%Fte!?jfbbPrJp28nbDj}0`A2sQdPI_0wgX( z-r3c0M|-;GObZlO@h?&>QI}0KHlwaiKu$96(Scjtq#Fc~csy7P$kuw{u}RO|15%&0 zS=*I0Wn!PTOTI~=q<+7eNwtrRu8_UwUavPP-S^2xHv-~P=f%B0_(H}aTfez0*e>sT zD0;sbm%5bHvk(Di$LV)oNCL78KMvM#?|-1g*1INU2iHt{Df8n#_f~Icy^9>NhDE!K ze1Dz!G%DaJ>GJITKFn8=D4|~)fX%}4Q~yUTYjr=a)OdoNQEbXZFK-NQ2`>Zq#-(f! zk`De0S*=&tj)-X$%IGdMCN5m~6LWO@T_5?FL2Fggi-UNx{{D#)7ND8l7&vSme$eWL zt4oTCK88|UcS3H%!Djw2f*~=a)MDCyrWbO{yQQ%=#!TPF%Y_0d6-!Z9-_Rf?(!hi~ zc9W^Pro0}tl>K|nxQ(csFI+AY_=UW2Eq|#uYEO(=nUihD@4#hn<+T6 zc#}FS!?&(GKN5crw6~JuQAzVJg)T}dttTH;vyGX@#q93e&M*kN_6xYR{wOQZi}rV7CUJv21IIAP=T3 zBmVe+@BHSMv-W7WmPNMeWZ-JX+N8X3|A;Us>Qp~7Q{DjJHA}h0En@7ceP>I zKP1F^x|_yW3f+`@T$NZh>W8V$p%jX=vFay{1&^<%CG>FX(>xS@FVFvRQS?j2ikucr zxz;O>7v21=%yb&u(xx|_FiYwZ4j$hjdk*U4-7uDgvX>V%MZLCqS z74RYVQ;!a%Qw=ine8?kTU$!V_MIllK6?saM|Gpr5e+P6s<)KKKif6Zxn2g8a7x`N# z{-`(Br82ixIUK|a??1Nc69hWeh5#qRp~hObyG=5QjNErsvM6HGkC6L1-`taLzQAaf z3e+bu|9&6T6I6NdVtP)8bWfA71`UxPt7FQ1bkB?z;B%9_FN z6mAZc&Q5~Hm1~XU&*HB%^eq0^fleb1!!PUmd_@c0_9d`5>(dDyn!1d;3(${mm?h{~ zG;|k_+IwfOMTv}`QU!2P!oo(a@t%_k%6rrmXXti zz_x~AkF~dATiiZIxR!xtVXHDZ*~VRY&1y6;7`iCgaS#az2@;cVqlAz6W?<`saG;-t zt%S4YGT;lt%bSe?P)^Vri)~Hl2R3SkL)Qty*@VBTrbP_FZB6MFWzhr{^SXMTQJmS* zmo{>MUIL|uj{^_!LbtdPVS%VXAAU`9X+{jguV3`m@zUg(-TnKuEq>Szk*`hrIemUv zQjzz>Ll3!NGz>-CcMFY31an?U!$&MZIJ=F=W8$U85|SJ~1HEx+vA)A2KKhp&<9xiO z{15b>hMnRE38ZpoyoWJ@8!S3>p+uyjpI*?aAgWy0z`K)!VI2L$>cuMw3_WYG#L;l3 zNK|Q!(9ynkPa@~|g9B-n-P&gq9#E+{Q-A#>k?=kAp7w^p)z>y_`q;+YJ?>AX@P|Z$ zqWhPrYA%y{lgBF`{@l$mxHeOVrF>a??w5<1zD7>26>${*K-fC+uwQ+F!0N>%FYh6i zI+yi7@NzdlxS8j-)aUBj7T^R(A~W{xJKrC8+xuXYbdBaDWVatRZF)V(i&okSWKC42 z|Nb35#LJzw@CqP|H~h$59(_J0c`BEYrPs5_@TDbHGOIkcT0MQQ6x|lydS|qi<5Fh~ zvE%^%{SU+}TXe}wOkIjN@;Qj~RA6P&aPt`Ygl8%V`BBM^)#Mf~x9L{ku>YVD2`0V% zn`!}TqY1Wg14PFZ?MaFAEHxpo^l3ZgkoB!qpBM$OO%bey4q z(dd=6V$}~!>3m$dc>Ik?g74MOwR9DJ(M+K$WSisbPta`9dug^6QiCPgS5zA!gZI_c zYChA%SaSrHY+3#{z6bOPN!V9GlH`}(IJV?W0F%f zAk5VlW+g0thswaiPfbtaeW-6OSKnKmws^WeA7G#o7Lje&#+Vl@Men>3 zjY!K#VLPWc^-kHAHLJ}guqAv-&eU69P_*OoN}Qz&%N_5WzBC+hvuRA^d^pH3GiV9y z3-ib+-ioZR6oLPNv5Nb6jhREb@KX zYak8bJ?5d5zXXuKTZ8b=x{~e;CXvup$-4FqlI&T)tMOr~EtQ4}dM)p6X+}A0{5492 zfyG8p8Lw=couk7@`q<^@Q~Qo28E$&+Ygovbub$qWoQCjL7X?#ZCHttQ7!d;gwu_`5 z4wTNU;OhHO_XIV9_`t(5rW}Bq>CR;v zmE_lnk?Z4-OXu#32Y`OA?0*zrP^^DRX~+yya#7t!dmf83&XV_~dCxevRoSHb;Ith#o}!-s^g^h0j+ z&B@!EYSPs2XL0(xOVAQzRm*J2cYvHY)U15F4mB%qKJlz@SKq5N+z0>Z>wBt|&N#Lt z<&*9ZNnAC-OFyDfqLKk`HR0o;d!qs!#74gP;P1^rxEPSFO4G`pqy-4lV_lvOLYBDk z@3O&_U+0@u2@RaJ`9+X-c_a|XUJbd_m2(RP;vgj@G=Fym%Li2B zhnYzb-8^!{_C*UtaoFN%ba^m0s%+3VX&FM}=*uIGe-K^n!D;5`r(~!u;`h6po*Q=D zwyfU)T&i18&evEO6GjnQo0 z#A4^@QZd~uuE_22&3jy(t5w{2_dV$-m`RQoc4zPu-L33+-31!k@m8@dMU5UP9g-qg znZpnTfN2th0RuwQeIG=XKA=g#aor|FL&nxyX^Er3-fq+Yc8jBZJPW&iq+>`CN&@&K zC;zsx;^{A$VZUo&=32Iu z(-Ak&4?ETF8L;%aKmG@5h3yPaQJ7!&()#rw#gQ_}ApTnPEYd3RwJMm;RMw@LemLd&=GuWwRY zJ?2efwWJ~z^F{`n`XneUCuRqEO1I|3;pGdjTxxP*KtL&1a#jg}Y8&x+uoSkAL7{F&x{ z`QT*~@331BFE(#cva6V`9WQHfJ>Y5cpcOQ3L!UY`^z7uoQfbL8x{Y$b24->)ERDB5 z(2h?L+XJ&Yon|~$U=y;LIpf$ssZMw}8P+XRWC9qrx~`cPLBv~ss3o3iheEu>;g*X6 z9kEG9a?SFCBaVJ~ZCVY|iQo=HX7e_SYCHibOqmFfcZ-pj&GUfr)MP%+6 zgTPY_DxMXJ(>#C-jNT|4O0W!W3Gg6KJHXb>Rx-grQUJeT>XL!fw- zZ_&E-&d8-3*%9{V`L{5swAD3=1a0P@7oZ zaCr+i&3cUWxXpzt(kFyB(LXn@BsR>|G0eeS1T6|61FGasu1i}>uCEaE-3eSyDdf2DTAeP1Pq2XL%s5I zW2ZRrVWcNG!x{o0qKxKE?1G7p z$$sf66G_XBbCTy%6 zlH=X-Ch<+93a6nCVvqBl$or3fwHwr~R@%-drHjnBMxGRX`wmnfe{SuhVwzMu|8s`w zrBLeqSu|Sb;{Gd&FkPxqifowTX}@Jc>Pk9Bf8FBMX;|u;Uy2q=cVL$Z|EK{!(V~3R z=`B)Dakix+R=ig9l$|>4wT*10kUzI)kdcndzUOa+aq>>hf*57^o8BEi+Bymm?kJwH zOITr!J&oTA+vcNkw>Q|=t{~vIT9Jz%9tWTu;5@{SZ6p_YXdX-JXxss*pnSv032N3s z=Q&N~R@fd>!k?{nu>j@uHX1-Zk_EW0GC+`FwSLD04MwpI_AHQ*B!1Is@ zJ{k2N%j-T_`ezQ|!HcKuMay7=t6J)J^y7L10m;{I1|3|nTiB36M)N6HR>IJ4u56uX z>OSO$Wwi6IPbNyatG2fJ4eyRCsP6T7(avk8Ao8e-$4*QM>djq4(ihyQNBFF+M6?BSZPqLk=Sn6HO_n zLt2ozgD_(~x1U1Isd|M^MpC2gz64;BcfxeuRjL0JZq%`LH&gOLU&(fZ+{`zzCr!OY zvORmgGgR5X1VE?CBM&kVRzc2K_tC;JL4Nf^SF$Q0=b0Iz>x!0m@!2Fc&%=e8Rmhq! zT_c;F0`>0cM+->bra80 zazBiLf`MzdeL<=po!|ILU-(;yjk3+}7=d?Gc|S;oNw;*-F6tN)$*-}ZWxa!E*+H5i znkVvqRK3LXHk!r71dm8*F>s$spTcdg>9{K;{no04C<)BUTi*dTkM%tBL2qSe@X47M^`90M&mOtixe+DS`6B-zcfEVB+<-I6xovNK*A)h zeuFjwofWJmG+yv01VNQDFRE0mTesr<{*We0+;CSi+0yM1?bc&=tzV`CDa*ed1wZQ0 zexr?0J9_tC-i_T5lx`^1&Ex(quv66445nN4TVs&v$yXz7$+M@JM{6CidYEunoJ* zE6%*se<1N&k9sGXah&9zJg57Y?^&hyU?|)w%6e=Y8$3n@J+u!U_3hn?=eYxapRLWY zIeT*AczhJdqUhH<*)P7o7k)oJKNH>eA7~jYZ+f#8|&D|1h8$`S~b2w)>v$xmtx_mHV!FU4Ae7m4HBvWTG0BhKKuo(0O-y2+NBJ!)nG6A`D%;P5Po9Q- z+*Kq+I;EP6+y5}xYP6euG3%dr0nhs>^xITV8HB4$-Btk=)c-AGRiBjS)VqJH3;H0T zXv@j;(2iU8qJh6E<fr0KDwKPF0Sl6X0TAMm^XK5bosfd z__|WOK(nk5U>(^D*fhfHh#b=RAMk3Al{TEeXcxQL<9ZG3IMP4tkQwdU#)>p+*u zC2X5FadJ3laZke0KFmPaVcNFpCD+?0PxIjqQOPcHJHxk~;L$DXE?2!D6Q?J>U> zcv{=*KCu7inb-WICgMyX5lrYM{A$E?&9k&sG*wjm4Su$)A_>KhO}e?_+j$absO)u$ z?NZ3--oJln{q^Xm9AK%z$4=KV+yYDKsNzjl-!ujWG%3j-;2qp-3uwctT$Kt^W3d`<$pb< zmOFJ?YKnGQ_nL$lHj{fFe8aW^iU|Ip^Dn+P`9+Ubx_l?jeH;8d#H4jf`epmY4%h+& z9|?Hf?gwAN4iHh8F1dT|JK;E=BS{s4(Z*zqMC(F{#T<+H#RR3uX~UzUM}N#-Hl-|m z?vLO2;*H8j*dN4%E&YkXD|I=#I0guRSe&j|t!at=EF5Ib?x*uborG(ZVR|nSZrGR> z9$xv2TMPA=7_37?EEBnq#MglXZxQuqy5UNKTQ_vZX!&^oF4Q(vcLb<=BQ7A(`4cy^ z0H;QF?E}PCI`RmQY4sqc;{8@2-ANG;IyfbuW~l3O3F?5dd$;XgnLP^-0|u|&1A4;S z7|fteAK{N^cdO7pP`?C`_8$le=lcixTP9kPFgANV$YWVSf6jegJ34b=JsEaB!8Dpt>(xt2qW{^36Z4F( zN61HZ^^JBnwo#q*vo8oqvByv3E z`qwr4-U5K!zCH?y_#^YlE>8VuxHLZJpsS4u#yZb8A%Exg?2f|ZUyFsgXmtjydujqC zAL3KvJuK-9w>`JTYR@xz^{I`?!Tt(LI491k8=hk!36TiAWUY z@MRmaY5jG&MI&zZRM*GsGZu)CiMArd*nOsLm>CDMpjAY_ye!`g{6VGZ>p8MmBvN03 zu)!&UBoQ!b?w3(8w;N(+!xv(dJLY6nj@4rSJm~fb|Q*YcPBZ zObC9Q&e+}rHVxIn*0YPm+Fh6YbebF}+Wwy|py-xOEh{$dbjJ0vK5}a1$eaZm7Gb_f zmsT$lO~YmjCh}hDNn-iAu5#7ew>}JCE2)mYLwjCQCC~S+?R}D1R#dv|$&z5Gl<8$K zIMv!Y!?b+LD0k(@tlp0jS>Ji3s4@mOb!0011h$8G`|hZ|d()xbo%!;ya(oC(!ut(b z1ZdT;bW!7w5uNl&(i~79OsD0~#++7>tQ3G8{NF9l_r3~UUw!|xYw?gmyMvfx&(l(> zhIn_DV1s?E?E7=#?{nAOM{%I96^|B2yfJciHm;seB3F?GpaADw=EUU?%=aeJ0hvfw zCELkje@mf}H&0z{9&K?tiyW5P#cIZg(Rq692TjCF_e+Vhi&qy}et)kBC;@`T4|Qy% z>;(P#RA7Cs%}QiTCZGRv%=RRxz>03*err9s(IgSj?KSB&P;t*CU$?Ui^iFkYhVxnC z3#0qJ$mg)Xayvxp4p2(P`y~s%NN{BHxo>Kpz@V6_2+Fkjtw^G^4ik8gezFAwgE}=v zZp;7((TB9}4;>rC_w_;!fcCn646!1i46c4!S&7q#1|{k0{Vd$2?MQM{h30zAY4Ksr z7xD3vnb=IN+Q#ob^eL#Oy(&O?H zBj__WMsv0D(cwmkhPS4W0GZ#gY3azE?PYTO343wA$u0~jbF~ZG_4hoL z<{SGODbn%dX|by`0Uo);VeKEq66&NEi_4`ybpu@i%Qz^&Z2yB4=o%-_r}y;ul?vS5 zsX-^y-;VU^@ZMljqHR24MjMnpF!mlK4Wi4g|7JBt9eN0o9sUDJcVfs~Dj@wE^Plux zU^MdqsW1EJ%7OIpSr>@yEdYiq`fZWOC-8Pz+sa)SsUb=bSga<=P8s|1a0)kyQp4QwuCtSH8y6`g*I#+#M|S)I!@1iw?I#b z=!viM^^bkF*6iCNSWP9J?O|IAmry;^`@ynHZqt)1kOXDtwyOW|vpn*6fE+@m$CFbs zH^AMY$CtSK^iadeZgBLz-N1tvEK@*aVo_fVKgD`{+Ou8Y0!}8VH6oRaRt0~aE>4P@ zYMW~A7b=Ov+F8MI zD~LrXSH~|$LVDwd?Yk6tZwXA{5STJUo#_t9F}bfyRW!TTP>T3G;ecMX5kZb>)U$^tCzKjRK!!LrwbaB^aqLbuj6 zy;{+*N18~z!)L%)2QwNdRiiCDHvLZx@1-Z4rU0I z|3Sxj;fH^qx5(+#rQzsKe}K`o7eHuX5qDJzj$VHzdKlwD2MJ(3FDjvO8Fi6$)W~rd z4hPFzN)f+ZNH_#4^ytT(La8tLB=@NCHxG<3z-$S1W4pi9Kkk>Q&s^hzS$`w{TOI%K z3NyKTgEBNJYSxXzw8XgQ6VBq2$2;K-==#SKqc{8ifyzAtrM8AmcbYjpR!~#OuE|`9 ztFNs$0Gl!|SF;zcS{pIFqfSJYV2Pn_;f?{G;9ixo>UX#JslCY-8jpetfOn`_ZQ}s5 z>0JoyEKoHof*<%p3E{*NeERxnPaD(aZCsLC^H{JF?ppLy=$1%rni|C`yU&blFUZk_ zj<;kN*u8i{v|S~3%yLod)E`2>ak&r79=()rX0#&O|9LEes`26wiE$3ra3m*W|L2fR zm4N)h1J^iq{a%~Hfg|P0wg`;P^{rUWpP zcz84_FUEX_e8@M^78B1^V;f$1p?)SNn@WjoOOUIzn#*N!zDARTJi1B09CJCL;^!kZD5}*6j1HZevbO1=ynE zW5H+2_!K>`UDnp#5Bqw}uNk}P_?k}hnvSI9l`S2v+B$OU`Ww$0s=*drjW)@YFNX(V z3ar?|Xytp02+G+_ziSA-xlk8pi1a9@71Wa2fBpAn=nQeA%MVY~UvdkpS%^k5`e>O- z()!bPrbAuv6w&LvA>uaIxW3^FASZ0`A1FbY?*h>GEe-GWUr1c4SB*m)EJS)07HHZW zkyA4(Jl}#siiykX9aG&(##_lGMULCFBSwj<0W!buk8gxEQ{yxi%fFSO;@Xx}5$z_3 zcWqc+%@NLD8A$;}!}uTM7u=&*;m}r>=5xJzivBUVv$l{A7buCAx}}Wv13(OfJ?$Qz z;XcvR=|JLM>4(E5GM2xz(YJD4Qrx?$bad?%#vJW0OqokgL)MaVfG1w1Z7mHH5Y;YD zp-a?T+(8ik6X}@IkGxjE8)oA<2)tMz96N4_d%esLw?6}Ip2chBna^~HlUI6z=bZQs z-xq2iv@-0r%66D@n%lD5-s@`>d{h!x9NxLW1}ym9u(HelK%FeLL|}qz)^jdN zfJ7*3`ODgunh~A)%Pzy4^sAKDu}eBib*F8f5D2=s9R45dWw1Yy+Qtr7N65rUIkt)f zGmnaxIW)h;X{3{!}@)tVei1i7v0rPfxU_6HwxE zWP4SnH3ATUVg*IB9bPB$AYW}m!xF+4y` z>onjMU_=$1{VCy7^*5Ky48@3y4)Gh1Tfxt&$HB_*4k)v{Up)?$C}-w_#@lz!Y27lB zK;xGFAWNnW-ZWv>uI7G6{#s`(K5jAUM9_GP`>h!L^03E85#Hi0(5Cvm^r7?jLv@Oq zsR`-MQM%a@5P4o4jTX*3JE&BVzIhG1x8oHl;ry-)Ut zWGtL>zCxIq+w?IN)+rr|(4Syr*8a$!ey>$-m_DNDr{Wts+cNu>gR9^c&^Brj1HR)3 zW+C3bPz8E1Y5{TbSJ5z)A~} z#I^(oC*Z=`xANvq>4AHQhBzmcq@}0*rUv+;a!lp#_TPS+pa31M<9(nkX5}-oU4M8)iJ2S#*opJ*c@i1H5Wk{KhRN7ul{Xw_X6#A)H+HYpuB?nm_kk6m9f^ z(&Vd#!AGO`@q~5-FCb8UWwM9w2f|U!@j_|kLh7dRHHhfGPqre$(hLO0C0}FOxO|@k z4}W;{^lE;1dZY8%sEV&eNNQQ2c^j?#9OTW^IqFx4B56K0Em1$olEJ(E!sOz|1y5Qx zGD>lM&KS|rclG4~QO5`knF7w4dT*DuEnno}mS0kZIbxFjWQ=;cYyISZ=Ri`+OR;Nl z+=FayIzt^)D4gZU_V^#jBp>;wIjIZD1%I@?J#jvqq^v{;t(P(mmcivB9f4Z}_AaYt zw{D)gzQHrAu!nwne#6l13;~P=77Dvv7xqgTTKtC-m2ZP%IJG3Z-9BVBDG2xK;rDtP zJQwz*Dz4EK{9yZWdFnGmgFxK#Cn?&$l36aJ?htspKQs}HuF?e8LND*sKKTdIgPAY4 zJ{oTy%p0t6nFcVi#peJ?!`h!ndU5A^Fh0NsN4`ut>w=f4OD5XFy}3@_er3r&Qks1%3rhZbRF5!oIV~b=r<~n=dcHd0T9{9~vuApu{BkMB=?c8})Bii> z-fQ2*zDKC_&R2NLe3yxNrJbGZaR_(|t1{mvABgB^QI(MR-dtZd#$T^-L;ZR@?e)=C z7U+tI>kU)Bvn(ol^@OmwrC6KeS*>0*FHq8R>!Pr}+{v35Qs|%Ys%Eal^58@?}j|wM6>I*=pTv<9JVh)F0H0zNv|_R~|9+k5bW614e+A zVMeD)*sfPR>1fC+hhpzFFC+Mlm>UCrI7&QgelU!gBi>3uifxBz#FyuE%`{;@Q4=Rh z^pVFL*S*euKK3?4#`AG+8RDTd5p%v_C?z>WJNx$xm;Jr!zbyc0r?A^nV!UaJhuRe8G#XPBrhz8M}!na+l6K@EM|3W=%7p7`o-#D01ZUn^mmA;LA2Xc z_WR$VUli6%0@?BNwRO_|VI5f3a53kN?g#?%9Uw;fBu!op-SdoEyl1Y#qmbLMNFt8_ zc%C`TP78oY&+#?)7RRN=ggbo^C$aS9vRhm}IW%d3ONwq>6t86dl+b(d@KQ8?OzxZL z{kZUYtnUFRezNwG=_>m~GCnIQe%A(XnX_bzn+&rZ^R_{}JB8v>V3Qgg!U=SO7AfXu z3WIF>Y;}-(!ysNseaWt~m;hi!YUk@(3aH)WCsT1Z^)U@*4a!=Mt$GGMtq{DCp&L<4 zS<5RpA+b%ie<(yASGQOb)ul6p(8IfR?Ick;De6baTli`Il^dq!h8aziA2(_3uf^yn zq_Ic1EP$)WP3PJv8Br5 zF2I21IU58mx$L4IupTt0`HW1O;?1#|nqgEDLf#+Ph3 zvHC%#IfQc<{_K?OL>e0By`UhIty6ka;j!Ds6|4iUTcV#%akP~|bjU6?p{dM#rAxm2 z0|}fNO+s<{;;x!Me7c`e*MKw%Mb}wmKgFtze2WQzV0#4UUKiq{D zUObtiC#x>zk`a>VT;n)6qCEg}6-f{ue$dokHT)0eeC`HLjit!d>6rhUxsl}2Sy);ttn4fq1AvIC(M5uAcq8Z7y6`o8ZPhx(}e2uM3&AkG5;ER)xQP$XBv6NWgO+wDs`Fb%Q;TT0TfCee1% zeJZk$C?JjsKAx4&_;dk1-2U0kI;}A31)6w|i(FwP5-sBukASyOJiW>U=%=@DLS{IZ zRwWZn7YLp)(#QP!txo{y(j_z1fZZAMk6aH&!;y9E(%g<58GjU;&~U!6buF zKX&3qH?+u!q|;cYR=N2P^qRx6*pVwt>Pg}5&oZ&;yOK&zgBQPm=yTwF*8@m2vIjwl z=nw(^jprv%Tm+0CWK}y5pp?fgZ1ktDS+DDFH0rYlbB^utRVQhU9bai^;PzvS44;DP zrb>5?)*y@d5Hw4*e9oWZkfjhK9jPbI$NgyAs>AR9l}Ar9FegXT+*}UmRkgU}tBkm+OOdHEp9xJ{V5#O>wjLR#*B`Gr+c_7jD$XP@d;i*^!)vjxX1_!~cpZo}{q}I;GLxM$_i1pM*tp z{MURlz41@xq9}@`ps?#8_Ww9K3%4fUw~Y^xP)b0Mo=T~dbc02Slqen2B_%arFa!bV z5)crkQX-wBM~8I7$PEPP4Pi{!_I;n<`w#3m*m$1nzOVB20aeFCg4ZP1W`>$(&>#rKbX2fK+O5oDFXCn3@{`2>lZ`Mdh zp!gVSuMFuKc+;pZ6HUqT)if1qOo*<6YT&5G>np80x(n>5p6TC-)>?UG6LD{YV)B)m zEUu~;lmFb)*reIh>eu=o><;szj+^)XfOtR(AXB*23+I3B8JrU<gUyYv&U5@&p)w<}(uKf6Z;t7?5+V`}oZ`^&< z5|e3&UF++nMKg*MemMFCVf{t{&@-REi4I$AJErn=gFNqBM!s&ATAZr0y59h_Tl40p zS@Ar+vw%@#e<4>UW>5aE_|>@Ovaxp?0Y8rXS+S-;&bxbRjjYdxaxrCS{0t&~l{7?LkMGMRsEb@|Q3_Dv_a*NxRpYlQLa-N>`OJVw*8`FwCg7eq8?ZS%ei`rXq zyBUfLqJ`47p`(8lQYp-hXzesp_we7{@+jyv^-BNTqx_c8YZ0B9HhUz5&}>cBVkpgy z*(niGgE9W%xu%!iE-HAk^EC6=;@0uc;H-I6R@Jty`PHa{{SJM_pDwSbk9KBlg1xI8 zotQ;FJ)i;^A=+kSwrB6U9`1BB-+ngv$nllB#UHi#+YsT_+-s$wKD9mb>w6^S*XGrt z2X^&MGnI4nWvw1%snV5l_hiKk#+n=Q1ugAjGB>Z&xP$8DzTGsSwB{c@KEL{KL+kYB zki+a5M1rBJoEHcpgwVwi3sYVg->`jzrDeH)WUSl`lQcl5;6LQ9_C5|Dlw5w& ztflseLh5Pp6H$zm%0eF=0jo3^;h7Gh!4uczhV^Bf+=obq?>Mh#qH4Ivhm zPrlF6sv`g$6=f#AW7Yi#|guoK9A_Kq)#Og=Bo*+O7px12bJ5FgMvAYZI2h5P`eiER=De{6Bv;^U1m2v zfqPlJ;Z`pB#Ten2I+y8+K=PLPE z`SO3i%@(4$=zCbhHG>p2Ykr2{{11%^^Qgb zqDic*EP*T}R>}|U9nVM_s9F`Tb}4{#-`TZlE|%ISgzsO! zZ?;^mL796v&(xvu%lf3`qL~_v#C!jmu1G;BOL^~I5ew3sMyE4~31{?~B9>+E$+ER& zi8S!=w4M&(Pb+L$Qfj2v%tusL+j?sDrp1MmS15+RAjZa7{}>D%y8@;|T6_D^9pcSRK!&tab1$D8G=^~wL55c%2Z zx0@WEx$k75WehkJ&hnMcoqgV0AQK^TdTaKU2{*h#M04M}! zL)y%P0cm}%Q*XLu4|pSADK^lX3gU3d2V6Y~Av=8qH=2WmvI3EkmcLS{dK*T07v+8@ zfhfHU_zNMu8-oXz?yc)FovQ9gKIl`bPfZpEABeIW`NlmchSL5~yH0t|g9tmDZ?`}R$f>vn;oXy1$J0o@oyZy5&)k0UsJ z8qJ4Ope)uxdA#Th1H_x26K7|2Cwvyt$tR|%Lv$=U0tII|6TDOTuuxw=-Y(aC&_^n$ zLy6YEi-mHcn3O)8<#tlHWp#9JWx2R?bAvLnbk{~V^oN!8GY81D?8%TYhwyf_FA2_= zB)AiAkIY~QLW^9!rfHUY$NJAcYR*Vsu67z~MiAUo6~?;~OmX7>PK%~xz&th(t7Wn6 z-EF13C!M~xdCQsObgX#dt_@xHa2~`v&k19Ndn7(Kp%!9Jou*ZsbJ>1pX72AR_0I;K z$Eo-QD_VcQTgMQUHU5qoz>n|}!%10Ho!o!a=^MpFf_glFrgLkk2>6Cfk_{GfU}3&@ z9t3yzA8(QJTo$v=-mZ1YzDOQGn1bofJOc+Y0^sWldQ%N7A|;iUY-Q) za$Y0?2e*)N z7R+L81LJXjIUqME_ucEb=%WMpJ~UMUoM{QWLHHKqnBBJ}q3qc3DVi9#P_#N7uJuYz z>6q}OT_OGBcy=LUpqJdQimp&hbw6;4=`{tTY@FfWe)%^sAcmjlOxW$)YLWX21W4)L z?Y@|8(og??0oB*t)~+B6CNyUS+(a8i=B~3##YI|v1*JZw?$jgTHVtU?aO=i-Xtocn zTD|Ylm)vHRVhwGTe5l}Q-9nj!s~ZXeGQlcQ@1tIt1Gj-&=p2l3sjDGsjcU)*he%lSJOmomn=Xj*tG;Z-46b;8TD@x zX!vU+8e#X=H)$e)R36=mUa0HZ-FjU3Cke4Cl_>jin3s*Y!pH-v%R=6eg$VZxmxDG8 zx7a%g&@e8$n@?z3_I>fLG^F%30;ivcqn_GH7s-+vU^=}&KGC3I`xxp>sIA^rXZjCh zhy1uORqn22QoG3=N;oaHR+Dc)up16?7^UU^kP7`$aCX9!01d`IpyTxdM}z60E=7bW z>v_*J0C&IBhrj43joge!i;MG5-HG!V*rJZei@tJiwT7qZreY14S7Y}AUQ|o&x232O zSEF>d;R9rK@C}0UfEq1Oz0i4k-97unHHfQ1jqQd(NLJIH`V_SHW-Wg@Iw4tMXA3A- z31=bb1z}UVf#*Vv31SH(t&8^76!W^c&U;s%4&1VliWj@E-wTw-u8e*iI7qcRem$fd zOGy`Bz(T6s#-0s!zi!38&27rWj_BdQv5h3DW1Abjn0)y@zizR)oW$M+eo=4kEB{pZ zluW-stqEgjgIf@ZUND^+8&qXh4GdM747gn9SR1S)M3Gs%nfEUm=i2Afbj2{eT(q7W zC({bEJi+OIV{Y;#Wjmxz9VPYmHO(X40=#bKMHFJ$Y)+0&M#tMfrgJRhnDEnY0} zmgwBix_i|`+(6Jtb{YloFvle~GG>>2^cJ9N^BXs8qEQfv;?ydXEHb4iLe#gm#4zP- z3#)`=nES2u-;%>x>B*2-!9KI~V=|V9=#JJ%IkgvQjIrLo05Zp`w88tN*>l5T?_Qmm zpvg%;E-r?lEWB*H-e72C;m=DL{COAdYyl5#wOk6{l2Vp`vvOVuV|wB^CpJy}*Q)JE zY}j5)n0PVo(w`?6C-eT^ol)`YKX!6KxLsnH6p*Sf<-DCX;4x3;_GrreV(R?bz6)32 zduXes^UX%rCtb#|O!z8e$A6&AkmFtxuD3xRqE=ayX=9*}qp|=es)~w_U*i~6Lrh0Q z*5d?{w|$TgDyIg06sz6l8t?s%(H?j#eIh**j~#Q+{M$eJlTmM&pV##Yo%#(OKgq;e ze*R94P_a7AyNucsiz6 zN`fFnb+Qz`Xv>h}oA)DtSLIxIqQP-+(>5=8=Qj1u8WLD2Z)AH_U%C+ab*_KeGqyAE z+mZ!AgG{jOLw27OuVZGJi zax`$rAkwN!$HUE?0Dx0eU-ZN0gmu%IMJCTD=R&pdY=N&gJ=kavJcd`3np4ikCC8c6 zD^1@F!c_^p4;+wS*lt?CshyC)xOBn0dlbJo{C1H1#pZ^OwgbC&(z<>=s!?ghO};lV zOjmOQO&G<4QvW^rUG-RXpf?w2WB*+T_iXr#0OgZ~t2JCp-MFWy?teHC=6Xe{w)UUEU3&=Up}rwE zEk_*9nsDOu%_uj!G(RAx4a$2w%<7T>5ITs@I`4w+@kn3H$Jc+7`;%vg73_EJGmB6P zfm_TZ>qZ;0$=^Lca;22rbmROQO+Ve=SN9(%AWSWj%W{xk6vr$h$y+x-Etfkd`S11$ z|38-Jfx~?7cv#~ZkeQdC(GQ=>PY5)RZ$6&%%jVYW^XBr@yNui^<&VFh!3PiyCAz%h z3T_d~DBs#ka9)QZEJUva_z4yTQ&)RPe%A`iDy-Jd;4Hqu#GQk4*_8m z_B3i^)|OXIfkA5B47a%#)$d0XY?`g~jBanrE}>LkI^1Y;gC@W(c5M~Oqw0-8$$+xC z&PG@sSZ8XNMo+Nr^GOjxLpRu9H_WwE$0Nj9fOtiIw`RI(hIWd8WSv-#*6$WjjBVXf zI~a?a=?-z}T3?dZorVFY2^0+f5!;jj^e+q^-p7#cjoD%EY_#04j+pv4FtE15`~6zt z%lEDV8Dw(}Bc<`AhK^sa`Cr=%{vxXo{C4p#*NN5GGWoP zk+k^J?yAy0zS|2hmusDO$h|;gu$n4C|GcMD1=rsgJLrv~K{w?9Z}=WwPlZNn`;D4z z$ATN0^v(T#>&$@ib{`7fJifW7UNhJ;kq|CR%ITzpipQD|(75vckOcV;P-_?)0-w1$ zpW~;b#m*nOx0>d;G+8zTdR}ysVe5P6g0PS{qerd%{p zLx-mw@yjZDfC6Q?EUTx#n5L~fERpysu_|UrD)Z8@?eU-m$P#&DIpI*a=VV`vcM1^5 zSyxLk(ZP*jk9OyQ4Rq=UgGMU}5tei*12#Ng5|)3%pxZkJ%oEN@UiMS(N?C??=eoqI z36XyxnW4&s@S9q=n6rTQ!2m7Erq5~Sj8}N#lDA{B`Au)?Gc)%_7i|3otV@D{s6{Xa zw%j+d1K%*Vl)yP(Hwed#e?uzmyh&7S$2rzOQmwZqUQ9{MuLl%b!t1VCIEVt|!v)cW z?{48tgausn;5s8z0{DpA^WhIXTGt1d-pj!mV23o#s3^5mja!s{U!`RYI#GwXG8iPzkda&ZSp8;mBSRM4o)Agkc zOKfSBKP=XUWnLZ4U3beuulU>Ne<%&|`ag(z3*b1KT1bWlkxCur!|xE4<|<^@6Jd1| z#G98|O|1l59Fy&wxF=1d?67D>bXGy@%5<05_X1+s7zufmRA8pDrLnSR$0nmE1^>he4J1$+NE^Ng`)`@t`z z%Y&QJbvkId=c3G~bzGg2L`(>k7*+M&PSKW5g4U%gQMoN^VBP$a7Wx^X7jG4ug{quq zR}M2bx@+cb9ynV2vrX>Ls`AIiK0@hFFbl+68wLtrP-j{hF4N^uW3!F7UpQ_R26^0; z7|j=dJTw~9oTRJOiYv+u>Ov-)vXdDJ{Tpp@rv}mLoK=l%ty5?lyh7>+m2#mDC#&ujp0yZHIlE?S z^EaO{4*!8f%fm8W5=zS$OrMJZza7f9`*7Qx3+i&fOnhOcD2lM6sEAPH71ye0z*{?D zyy~E~Xa*jLCB6y^a?X2V_8$n%Hy3{IV~k)ZM>81p`KpeyrnutmfU-~4{|a$1+xH22 z%F;?bn+DU%uSg~8j>{h0u!CjJyQE^IbMV(&7n<)qe4Yhu&-YJU*hD`#&`LVNYosdw zv*-R;FEa+GKWJn^8RNaNSX_1&oK>@x>5%GDd4GYSYy^8Gg1B=^GPx^1Qv3@&mR0hz z&SEIO>g6*Tx1e{B38OhRX($5%jy@msrnl6sfLams97=ibN-#gY;n+4SV<|k5TgN1& ze0cxU=a>^V%$x7z*s|R$c~{Hgrm5AaB_+JO!$8`>M2W0#$W>+NekK|D= zcK%U~-FnC%+wP~R*Gult+(NyUh~@2%b3p@U1J*%)-=H*;M@7vu-1rFKnS~J{&1M0i z+!5s%+Ze=P`0nj5j&3MYZar-g?cFx*Eh-zDw3jjYKLOZcuHN~f#O3{gG>C*@j2;a> zmXz0S%)Q^lM_=D!@AYDm2j=Q(Dll}X<)2esK%99_e24jrED-X@FX+IvZSZD5j`41| zvsQ@5CgR`{Gcr?Q3E}eS9n1O-V%TcCA0}ay;LP=~?ro+O11ibv@&QtKnM`x`hh=qN z3Dym!>D^%BwbsQA;#ml25qB~(&N<0hto`vun8u?dZyC&QayOu{jb`lDNo)CX46nBc z+6V(`H|SJ7hAZ~NS$U<@2nNvEjj;_a=oQAPMOFgSHP%*)M)tjF{9bTTB?n zt7g-7JakNwfQ0W&Y-GjpmH_6J|3D2i2kN*&Q=PXrZA!8+OjPc!Uscl5d4XM*r3i>) zd+kU8pXuuO^2myS%m3$<+k2Idko@r_{cJbyeNJsiMmE)({VE}N2v>F=S{J#0)W zYP=@TKZ#p=Mxa%!(Ej*RfSDY_sHzdhM}9!cOm3R+@V>Mx;!as|fNNuu^Zj^WT~*!M zqSO?(-+aO8&#UNMiltuqgHf%TK0z*4*sP50t*xWGT|2@BB@Lojk##0Q_*G-i;$`|D zgLvzfHiOH<0j>G=zh+Y#EWrtsnlz7ZbH~niCh`fBzASvex*RI}QlKQWr^IR=cLBb> zA=58}>b`XvzkFddVqo;_uWU-(g|f@a`yv?sBe0Ck)p+xpZ#>_%yYR5uz9noOkrLFM zpU#=~s@;AP@*dHLilITb0npe+x3?wYZyK5##nQir7JsS=>qpAsnc{q4cIr#m9p4l) zoL5>iw2ulW3LgnVSTI_wGh<6f?RfKCj8MpDWKIu;FsvqCg=L5On6~|8X@qmY8R?KVq)mnXYTjrCRKbq5p)KRQ|g_hABc!bx2k$diK z<#!g>ie1!GE30W24bY)Ds#VN$lgFb*R-;P)fm%JzDTv`40_dBUKch;;e9D zU_J1bVx9de=BE~g?q|qATnd2z=Nzvq7CyExwREx*qTMeF9w=}yLeVaN% zNnaU@f$9TRotR&`(xj}Hp&uKT93?*yMNW^+u&YP#l95pRnccs-Ud5i6dOALx9S)04 zng2ixgsi_d>DrZ9ClYmo*)0e~%B0Ps^D4iu#K*9h))F|(?Z>h~@H-2`zni+*;df6t zj^i%}@!lCGp2Gcic_mC*LU*$agwFNS6^3jS1Vc>sc49kk?dBe~>-nNREG6y&F>Lpf zaMK4;eThN+E^_Y$ld8(_f{2)jU#^?+znH|9G_~v=@$nWzg3J@Nr@3D?T!tVN%!u{H z^f=C%eBZN^n#=1L`chEbecUmoh8u zTbWDz&R^NrG7YZsY)KrXZ9M)XKxn}XQtqiY1eY7Txl@m47TUUVr@c0MJU|I^3mQaQ zxOCs*5A;pBq!INXytm4Q!cLHz>-gsc$5O&8s5Z{oa&gmWyHyf*al(BM1zV!S2PI>k z_ZHusgk3`c5RP{#o9*ex6N;;>u5h76N*-fa*~ zX2MqYN@II$ncevwW@Cc-z|2IA$+tv%lug;q0-IRs+yd{Mn{o8+Tl^wg0w)nmW6)8U z8*h;A)&9!|E#8A?AY$6NAISE+uj z+#4L3*vU>o59EjPN!K|W4dRhcG(t^@vReIA95ZSZ;Y0JDQ!i)GQPv!!xGappe2c2> z=3t-aTlnF6^najwwGR~N2G|Fatb_deFI=jnso;DVyFU~vL4wO_a0vG(eVx;skPvWR zfNUbXlugbLhH=lCK!n2n`ek>+C3ilFDKY<5RiTagWtqOzP@KHJ(pj}7frMS|3)$&O z`M@=v;7Qdk*PTiM1~{I zCT3rqrB^h4&ooy);aD_$-t7K${uQG~ihr0ah{vQ{6%mYxH|;K&pD?xIjfyhII+po5 zp)b87uMi0*ds6%lVQ&3y544%zJ-@Hw?G;?@gp0|*K7Zy=1Z4xpWL9hH^IaQp1Lk~@ zJ(}fcQrn_=`FN)G_`G&i3Hl zdd=55LRb}4IhjtCo^WnDZAxb8b#r_tCTW{pPcTN09zoZaF7Zp*G{0$jTTclW&e)xk zs*FbjmkklTNdn%6)N*zQ83d#=e(X}D_@xCi?L4Zu1Vf65x1CRP9)RXzv^(N!O zRO-Ghr?sc1*n2eKzA+uh{B=QxB{TkRJT+)PIWt9;7~N&4HI}S&Jh%!=898ZHZnzZF7T@MOP0oH&8Z9_?0<8YXc<`%v$N{=0z(A^0A{f| zs@zn*;1#Otqxb6^Dc?lC2fv9z?-Yi;Qi^4_8!{fvELxtt`EWXjHO*1ov*_!#r^|U2 z-nhPZYZ}bx_SVqu@HMLK9lfi3+qb9gf< zV?t%NQgKD|Vao-hdr_UF0Oc2dnvQ^xK)X_81 zZVvqJE3c`~H((bV(<@9hx3c`>cr7I!|`dWPXbHrInMSMrAsZI#qkxNjHpgt zf&2$rJ7wdMI~h|XPa{&yEvftH9Q&4CNJxtTyQ0;KB(DYTwEF8qJEJP6!qW|#I3AOS z8jiVskMD4#djPTi(3UD!wb&O&ds3cKcH1iCM&cvPaFXa4u@i zqhE4$eLpQY)Qrj%E14{9)D<~E*V1q(6zX;tTGk#r4t`%ryES`kH5~S%IQ}DE)W`Cp z!DhS>gsLKo<~5b!@6Y+8}HES$V$Ig zNa@RFbQ^&hdsoeFFLLuB0$yp7Jil6?Adp`OF>GC-4R?6NI?#m5|1u*>>Zm08{d04x zA@-_9zwKqLc1$(1n6UqT%;)%`n6twJ-qg^CEN@1cxLYAJ5ZI)vKKTlajYqqn^e@EWp^#kIs#Qw7={9kn*)mI zq(bObWg8cCH*atytRYUUhk|bTeUu3J%PW%$&&Hx}vWlY*>s=1YPmYe`bBS(t&rIg0 z1+Ko~T@Bm+O1-Qj)|%dEycMwfx2UGRir!)nnCtqn@K8-vW^5T$>c~ov%aHmn{?V)h` zrfu$OQ?|bR)q_EzE2Xxs^!q1 z4B&PHGbmK92o9}qUS7T?Jy(_cYgpTXm=~2vP;^ko@gq_nWr>h_f>#N1$_DiEAGx-y ztRC}rrg5+C&c8sq*3W{5(S&~~#h^E+VKJ>8xHc(}QnR%BlW@F_<=a z3g|IZ9w;RmR4)EwS+#s~jRv3p&$ z#$dBOqF>kMF_I)cA_<8$Kvf(w`6nSOL3UPqO3;v`v8o(&{u7Z(QNf~Y9f)VePQ;nB zQMBC!&OCLA5V^8uxy%2eF4j1+K%`!Hx$5q5?4KJU?6L?*E>$JDoSTq7PZmj#O&Q91 zVb$;zT4hWyR^885dI5Hv5nKoe&2gNq{-sfbva%m=olIn>8^I+vP^8bSc!epQY$d!` zQ2JEqhfnk0JgR-#ji;`3&$UT&`?i<9;!(3#VtK1YE`(nHVt*JVhw#q!A(p!moE486 zm+b4ZwWhL|Mdh;>60WaENvvvj;?#1gq{76;GhOg{nmc+mvx!M%dl?Nr*5Awc-@dFK zH)vEiiXeIraKStUtk~l$f!BFf&2jUtA2M$196^F(pYAF1EcEZb`|<4^O-301z|-KR ztG<6jO=oSn#W@J32Cvg~CJ7U-<2ehSvPup52E;r(AD6b}uwJc`iqIF^{43BC%pC{p zjXOd{tE8@zD~{cBuwAeoZYz2T{2U_t|28P`<1-_$niZ#_n>}ehCNVx zDwP0vQ|e_E%7xp6kvXuz;b8<7cP8kJlKyyH&1m{pr`$1d&VhLKasxV0N; zX3mryJpI#Nyx+{={B0&r4fJE&Ae=$PN+DXWYo`}pddl@YL4V{_(+yep4FoLAF$Ubg zv>IHK$MLHZ1zbT^DZ^g;Q9CJ+gW~V+2=aZ$YJ{~o=svJ@| zj(ZTq$P_1TNm;5On}%cU9jn;oQqkorE8e}}SP2mIQc9Ye2(^1=>G2X>i)r;vmbrA} z1yU;vke1cI9pABA@d7mIQnyk)zQOn!d!0AC$Pe>}=(g2kwgS7(mvbFa>M7`d{u8|W zzHF3~2Zro?@LnA@ct0Dxc&G5bPpZ`8S_C}}>F+CZll?w<)-qS}Eyz#Tyo$}Q-w9RGzdeRRWfH0}knJ(#j zEs%3ISS)Qd%z?QYP}=-KvWqv~YfQP(UpnD} zUZ>J2?RODP)sso5&i@ZI-DO|S!L2D>pkR;yrd44@SI3e$3B}kQ%&oX~-;D_t;!`BS z({)W0+it@>x7AitFYg)Zz%qKG>vG%tmjBO+PK%liV)vh!>WMI>Jo^Aqx(MGH{^Ga& ze!t6U$5&Saak+z%AGX4z4W2Had@a-c>@=De=cO~OcswCgU*Pj~YlE+(ftSK+i-(+< z;tN(FKZ*JzDxN!jYV~aNvm!S~8C#G=`sPc=0!Qg+@V)HwZ)!Q?BFg$nPVL%toPP1B zIa!XkOiTF>A9W3NkAdC+-v;yNfrtp-Xb_V{%&*^fT&}Z8FSyd>zC9P5H|btZUmEaH z+WxtCyWnY5LC)YpB}gMUP*?g*;_zD8=ckdy@A$0XzZ$$f#I7ZaRn9kw0+X?9wjolZkn1lwvo`AU%0ClF5eIMc zgy$n34!`{&aH2T&{~U#(Alqf{jo_6h`Qe7X>m=Utjley)Ew&nv`!{lbj$AqsnNsOt z{ZHl9@m-TNqd*FC(Xzi&YNfg~gz6r#nR;aQ)h3r>l=|T96AHH6s&d5-J0ZpvL1VXA+wc;rme`b^P&8QB(5{7o77F`^>mmh72ThD7PGy}7QISzBbQO#o2Cpg$o zh(+(`o9r7Aapq2$S@YgGwFAhUJ$fW_{L)0Yze11a_Rn$~7M z%g<00`{8(E6rtQyT_ru=F@lx=5|9bNC}?1cUt=N|ZF(@#xxu;Gh1S?`q;veUppg8^ zhKOE#0*ih)Ds}8#O-8fGL!Y)ZZQK$6-9yp#eiKwu+wo=ujBDw-ko7Kj@mU1S)i-Iw zg;H&)%Az5|G8t}srjEAlJ-$LTp4K{OyyT|s1cwiE-2@y*$A`9;22lOU4+|!(Z3(`< z4nl?UpZKo6x4=V&d!lN?4Wyp_?JUPAU#i;n16!$4FnhQhkPIMS+eA+!%4Y#+T=E@) zO7x7H5GmKY!D`tpcj2PCcC=?USp8&P>0e=wEh|vw&I|5SXKJYCf^2FL3~(%azj`qf zAE1)e+#E#f;>UhB&*i3a*yis$nMGa$?MA!AoLEz79QyJ6Q_Cl0b^ETd-Xf8V z%kHsUXIq1s0Gg9i^#==Kz%RA9+>O!#Uc&4dn{W;W2~$FSaFK67aM2PVofUa)l}@jc(AL%|u|$R{H!?E;=<}f@ns<;s zRD=t!?*U~?#QT+y0S3BWvV@X%&Xu*#EXu(yIb3E1FD>7MO+^OQgH;GAg@jRv?SL(U z+Y%^vkj0h{DE)5A!@6voxW}tlVv=sGkYXFYU8q?J#S%#s=iBj|I3NwSDjMEuSy!}A%EFYv5_sS4I}7U_{`V1O@VhFZXzFtR0R4viPAK=%CB9|%|9oo9?zW2DqlNhuw0j>?ZHjm=1)=j74x(_!=xku)>jsZ%EogB8 ziW%VeNG!6?I0$3#p*6fPM4}QCYiqS)w&&Aj*v*tpgTiOQRvk^w4>@tU>v+3*($@tv zb=;*Ac^+1Gd>FjJL@+o|<4bpf0SUUz2Y=5!Oa24Fy&@4Z@7Ytp3GLh^ z6$mxv<{4Oneo7V3>Y#+%Z`Gp>@-+w}HG|O|+ip}RHNk;GGu-h}(GB%0evex#b^_;1 zWj7hbww6RsWTrI=@BMWW%-5W}l`#{c_POfluZA}lBvxbUEXnWr^k1}wl0m{*;KYU5 zmFby7ST+%A!qmt5yQ*?7a96GkvYR&cvfT-oSrff4%&2UyXtkuQTFEP37`jfokDexJ zUQ^L28^f*-90qJKrK~YT^J5nhbLd;cD;p?18TMnW_wT*FRNe4?H2AF|FCol(P-z`6 zoanoeg3{{dQbNS4XjiGogZuJ6D<&_$N_CJgV`DZgOfIz!;CCPPxGi zW!j9z!03kO-g;Y>?=t#OsN)U{XxPT~vzQ4n`-X)3xb(leSeO2F1^~(pRUv#f>n>dB z=hwlDsT;P?Ls!*2qYhB%;1y-)a-s9>hhLPW%&G&blUh$($?p) zr^J=@u=J6`^#4HiI=CmE%6zX(IhMB|F=8$88@$=W4ez#sXYRHA)xwaGl+?L_&UqeL zoubXnKw*dT*xiY4I44oWLw2EmBErNl;lsR`+)vxR0&tUE6K4F_FJVkDZEZO)IEAs+ zEo3e4raZg>b}(4H=%y3~q>kWVm`f-o;83CmA7m>?ko!Oxh90RW*ItS9-+3T^)o?h! z#9fLQFk8{?g8i$HB-mZPA&R$U7|yo~I^CGsAk@w0$OoYyU1qZW*AIQ)yiWgTVUh$L zo6;>W^*|t5&dSu(h;)s$SeirijeEtj?H<^SCo`S>4x6qHdb!D!=tI>wO_wK{g+&S( z@3eicrzcJ6f6uL7KLJ4LB(J+`@%~KL9#@7>g6p&L9m=3WxEtg_QW4Bq&mOyvBN!XB z-YdRNtX4}A@pJhRt#i0!uVc>bF<+94BXVOs*9Rmbo2H4Hq;wSstVT_g2*wF6BAc(kV$!f(iO`GAk6GxK3I5{ZX1dUvY%v zi~G8p?er4w=9zH66H7cOt3&(B=2bkH<`?i2Kh&%U%e2in1WIQvPOo>0VKvh{zq_uf z5klD;G3y^XAGU-k_k;^(_2`Z{^q@XcY+-levu--L1XH7%(C?GCRjZ;C7}m7Jv&)a| zFNCW4B&nzq0+bn7<^KLNMY!PstvHq_SqTjzC3gxzGSKG{0p;&KaFo4D;+4Yq*zSbg zt#s`Q*?X^I^K^1en=j>xQ`;io>O^>R;!s;3hW;5YnXV7p^8dn0_?J0+Uq1mK zaBHH)-BZj!0dn^2<*lCZ`_8;v>OdI+Q+Io$$3(y)(csRTwHr7cD_mQT(r3#5K!RA2 zTi-rE&z10<65rY8LUUq>T$2H5@3|rTgYN8#uCxFa`LnNKuS!6mT zDIJ5W_boN824tPa95ByGcBCYzNhd3TLHR*&46o_Sxz8X-|I8Qg(8AUwy)@Gkjqu3u z(bma2f+R-Qjr!&3`f|z96R*@xDx9Q#C)9)FzaJHOa(OD zHmq-m2OfEBXChfdPT+k;1`K1P&%xJx{z$IV_q4)decCh1(&ap>=VE*l4QWo9y>V5T zqv@HEsnhZi?*pu0i@A{Ii)3G0d7=raQkLn1($SY(iD=P)#Q+h#9>rs!Bzp&v$jB-3 z)&%`6Fn>Z|9pB5RK3vif3j4O=Q2+UX>I&ETF%Q8}`=P$3$yzsHZPYmK4>oaE$G!wu zPc9JuO%%GDoSN@r(&$SPfIw(3hP;ix;DQopo<=U zJQg=Iw_bdXD7@>lT*CQB+7=ja^=yaZDM3HixCfeIHnm^JIT@Ppr}#Yr+gTD^FpTwA z+__*8;debuP+wqfjlkK7y|V0?yyCwo(W^HC�@adnOV!9@|F2Ik1|K)ahj5WJw!0 zrnvBjRyGYG>I3jNF1>iUMbU9%1D;x<%`HL#4|N+9PwHSVp+MY+k} ziY;IKScqB85p0gLbp2R@ee&L#2VN_mLKMdOZJK0kro_&x$^&ta}zsm(p z1~hYQN^-^kSJH8`X!Y61$fbs-*EmpmIwBx9m38-F$=evOMJ1O5J6xbS;TOHNHaCfya;5L)=bJ242JSFtF46HH+pqc1r=?PWc7fZ^kSz~1 zs2H-cUqC^4zp>6jfc3ictFhMNsNW05WNb3kYx8&3NI$2m_$D0hI<%a@dWBYYZ~ZzD z2}xnL-e0E@BMZ8!bBd)To-%|EsNbkK$hc%@qV0F_4C2cuy7uc~Jmy3jL35`mu5bwG z@qr_+x9e2^9G+~z=7i79YALrO821^j?Q^NM0H-FCknJzsm|6dIF}S_hsQ!@E{qENa z3jJYNR*g4(_S!|Zct9*I@hbI)qYXVaVe8+ z^t>)D>tuz5(E*)8koKzv16-xi5=8zD??iPvsH}WH9TPoK8|%`i&iN<&VN2BG&U<$A zr-#q`G_^){q(#%R4KmhM*89De@(gB($~Z<~p8#V}@kF~3DI8_WS{2_DJ5Wt=|U;lD&5{hYn=_41SKXk;y zn~N}@diB>^e@jabXGmdV;)vWWXmtCuWlgm-p$(_C(Ue^bHAfPzZK%gtcqetrx|>Q8 z5dG@Rjbh+ejZ>$?$F~eUC7#cSu@0GaPW~93i4A%^IHUxE{=+Hv=gt>jN)hidmASVv zwt?f%dMkQ3l=iqlb6k^E=TjTOnBE94(KG}}BPDUbkGd44NA`&W&+bg)1q0^8hf6_UC z@;|4S`$}uG35})XiBK{D?lM6bYpFquZQLfZskr_iz$%o%i=1x>{&dJa1}BBj#4e9mVQC{Xd${JDTdp|Kp^htWY+$qR32E=0(|| z2-%gr$-21i4cX&{P{NJunOuACkiD;Yuf6Xzt{d+C{NCR`et+L{+;i@^*ZVb|ug4>C zlgD+#)pNdUC7{>lPACS*qwInirHa|yT(O7j=4+YW?Q)fao{8vKs5^b(){A2xB5(OE zRnC4`m4AjFgP0v5gw33k>e+S$=|_k>sTG|*wn}-CLOYs_b2}WB_`$dgx(8G zeKfksaABl_uw<-vAtcfamJ+ zr=ZOAq&HknHOL#p)@e+D6mxen`>phl{HgZNwTdT_eS4bimC^7j#!Go!YhnPNPXmX7 z*R+q;SXo^fRXWoH+$~|FX)wxzzNBUOoYd~kMtX9aau7h6b!Y;PE@#L3u@h18-ZXSX zTJE_+X~j;JIzzZOXYFM6lGR@xUEzbfZ@v3RxPqekDnF4GUP^g#5rv2^C>}4k$~^HS zvtEt8^e38L@Lp=*D?Znaxd5L*Q2p!h*W+Tj;^Dnm`C!2n-oU4Q1we=X8_{PI74^5} z7p}L3^LW#2=W2gqQ<@B@z=`VQ0<#Q^2tJMPv{kdFV-Yl4yh2m3`vAtt6~y!a&N+Op zc^PB{@E*2J9TX~oY}sJpp>sNn6F1e?R~ZHj)&W`>HNkxp1!93r=#JK~!?=h!eqU>D zH}DHBEQPeXeWakcFdcy7^m%-`Y^eXE@DTsBBt`67Dd)bFA9EK&4MsyDwdZ}G)Q5V? za6=!o{g2l5wq9j`)9GiPf?UW`Hn(BdoZC=YQQbD-%hWLT#a-A{d`o4FDAaRh(eStv zaQi&1Nq&^pyZRzlT=;|g#%t(?WvY@ORTh3EQq zigD8xAwE3;{^|1FGG!@Rbx)YY<|w?Yy!7SDkmyRi2{Omh;?`rR7%4V)bOnF)a}TKN zyYE!%Jx#mx9%GLvBpLCv?n?8j32_d$ao7#x#rH+Q?HMDjuM9WiNt@YqtfgI-#hEZ3E3e%s$t44SCpk zXfnx%LOs#Y*w9*9vl9!T91EIJ0hQaZkU1dK9ZUC!ZMLgGN%tQ`l}%JDyK^gJJ#foo z2~~QRyS>b=QAJMly$B@#fgTDETxg;dcP_1`lBr6F@!M5hqzpebzS*2FV)|E*209n% zgi65K{d5lMJDN{i$5w_ZgKCITSQcA*z)@ano@af|BFsst?sMx7N7W@ z>%U(>X=b%VN++bv?8orC*w9azeNgoj+L&uoHrTWoFGJ2g5xCSvEjpU`b4#YZLaqs~ z`tVPSY3k8`3x$=PJr^ntkwLrA7>N+JHzc`z-Y{9B2io2?PqK1F zD!k8l)0f7mM8hNOBFgouim5ze$HnvR0(SJH7LYLUDeKEV+R?13_xsl2rVILFq)4bJ z7#0=7KMZ!2%So0Wdh|wSnYWZI3@s?6oBtKMIxAMqicrFd|HKtm%tvR6L(L(<(@y z>+PHrTr)q~KkZSMPDQ;8917tqd`4wEbAtc?A?#cFGjB?MfNQ6$}~m` zEJ224VRvNbpFfG3I56g?q8Hhrg-NqmYK?H~dBiE;qnFRzUk%YPmzm;d`91$RT_>GT z7H@RpYZftelVa4uoS)?`g}!VY8ivN1KZx#SqfQpI;Bs0XM%8`pE>t*U=2}8sTSTVW zH#nH8M#McG!B|n)ZWC%vhSrButmK}4i1{p>^E-ALyVm}D#Mwc^PDEz1mUBGS$!-6K z*#oX;f4(VBapg6HS*8CzV9pv^7gtqbJEe7{d7U61h~_5aC!u|l8`b$p{lq)80X`4f z*KOa0X2evKClM?RPH)DKUUZ8{g!z7jJ_nQ)5`MhMfD2CWnhQXmnl_yGtKgdo2Bj&`%&@OBi~0lqURvp z?w#g^{@2>i5o!i{Qy)gu@$|=#^j^-Yn%dv7pgo{I*i!qJDgL8u&*;RMQ^G({* zylTf9)C43}G+a8tom5!S)e2DYl;j8Sd6|6n6&KL1mcSL)p5pl(#Lv0yAgh{|tWOR{ z1lPXVP2Sw%j)1)Fs$I5}A$Q?rop-f~%2y6XZif6vQSM0TUhu{x&Yr2IWy<4vCg*l- z|COq>qKY z%LnFhfBIM5p;TfwcKNDI*xHqIEsYb(BsEPi!3SPhb$sF8v9C8R-QZc1paoPj`SH_z z^1deH9PXTN!Rz%(Eu}Iypc-k8hIp&R{m#EH5kuOc4l@;H*6PpbAOA9NwYZm1oAWMibvZ%-09aJslEcy@*XRqN}c2z-`~sb z?NVv0Yn!_IVP1NwWca@2W%~kmb-ZKdM2e}dD8oOg3#YP!6;GjYNDf;7e(=&>*G_OZ zOc-wI_7EijY+A=}Pesc=@LEP2suf*5wRt~^dqh_vwi z`2bNMct!9eShKEf(r<9lnjl;TxLt}C{v|YVpyTr%$!$?!>ldv~9IG;2=!0DgU)aTV zF7hw(d(&O^kpL9bKHs>aYVnpoC)7L!x7frX<|%#~Dc6`radFb)xTx-0WVwXyDWo|G z5psUzdCHzJwD5x)TI9v}Ygb?42lxt1#+roe3YeZ&Y1x7FnMUY_;7a{Is45eCpfRGy zmO2r=?DPBS%DM9A-&Yg%OwKrmepAdyT)vzsUsLceDOt3#O$<+5EL|n3oy!?>Qbu*> zz6ie86ZD0A)fOBR!$0zssKc8Dw@J)<{o9YgGOop!G@E7L zXGvm2&kaqCFn!Y(u1AdlqzTiFr9!rIRY(1611m`rYn5Z*sM6w{rCSr}x<-iVes(3v zFG8*>HlVGHv(V;OMG#3qYAb%pZ_YM1T$k@0;2J2Cp!kbF?8XA+vAgfnvm&{P>V`g- zyLAH$PeKDXL5~5z$hiW+)k>t7Hy%!CUDp%a)^@W;%mKeOPDaDb32jgyG?17AAUEm&S9eOuLgGCA@lD zYap&$qvX*B{B8ZV9pUa~^^12gJG9@%x6AVJmKMX7;Y<}^+huOpP#ug8AP|FYlX=8DTzS;Sd-7W+%0*iTW`a_L zndy3&p+7?OeBKMazc)~1xY>G+UJfTGxj!r$NruV7#(0^DgLqzXE(o~G71P2x(V506 zwB@Z*`&eXDX;Ay=OZond9|D=tebVbNK4NJ|U_p87D-V&d!RK|kX zPIZSAFgBr=>Z_i&=C;`y_lLi^=9l@i*48pfov|1M3rD|GVT=6y5nw*TqZ>720J`lT zplOxu(!($^TRO9ze;x0wEU4w_8sD*^e@oow z{?Rs3!cvE1BYbBMYisqhxPz5Fztyu3eK=;{U;m>pz1mPb+>a#3?E0=?=ZlZ)^@u`c8~0hpe@V zC4!krg<8+No~Q`b-~OLHMEr6%X7BTvkygoZAR3my z3}+`6c7a(=!CX6Jftds8N@}9ea)+!;P+_=TLsRn3)(-mn5Wy^MdH>0$M3Me`-d_;q zejrYfc;s);-q}6(D1G8gd6T%k!`K}D-{w(e3g+pDHCDRy=+hrZ_a1O2H=G&IBr4NE zHHh#FSzzNCzS?5YnFeBPw!w<(_Mpp=VFxu|_eD-qCu}JK4bqjZ%1UTVI__eDQq)y6 z7z0l@T?APXRq>HL0T{$5MdS^rG|?BySOdP}J6?uthM-zWgAX>@AM{=B$r+98Oit-7BMgH0 zqo^)7!cAqSqLfCiCbp1vWwblo>i85BznxEHS={wG$#L)ce0{w8#3M3{+DVVUak23) zuFGv4H}GL@k6v?iPUKG&lv zc6N~ekWjvXUO9N#)Z7m4{iqz!iof3K|0Y56C8y74!#?g>@9=ZPa7(!6jFg#g)9P1cA=M?~g$hCGO&2>cwlDf1u2 z=5&)m!Z}dOH=E+wUeC006V3ZNV0Y@n1ou(GJQ1s3*^)Oj1#|T6(^St83jqG^OKW2y zWFTkl@vt1Wxw4!2&u@?Ttk!p;;e9%Lxz`?>&3fMbAoq7zCXL-?yH~Op}RM1tabZTM&Z;dBI=p%@8`<7^bpkbWdu_>JJ2|uIo>o z19+9IXk#1n@k%gL*wWop4M_iE&Pzf)_z~a2%pw@4zxcf8!Ww$TTH}!8erER1e#Mv6 zk(aNHZGfl*=c@O|HttK)2&FbG9Bz3#>MWT8X1GZ;|FDI2HT({78^0$wk4Rh+e&9U; ze3^Tj7xgs^J{at(u%-|JgPr~qXZR6*TR-WGEz)|DQuQ2>uk+*ck6VoF0{LodEPeSe zkX;jnavWDaaw&uqST?WeMBk^Sndb`KJv8z}{FUr|!~dKjQ8JRZb#mQA!cxCeS|-AZ z@73`zV^H<&Qh8n3v?K}pD^H$&$XxO+0{|t(%S2()@W)eHQu;F7*4My4OwRl|VPV3g_%ViR@pt&k8qvB!nX$e4%sS ze^p8!+l>o8y^Zar=*m25*m9D;CagTN^wB+ZB;`Mf=|Vx&&GILR-{C3Om#8s%%3h>Z zW{V#Pj_X-*Z#%U+j^)38RB*adP!t>XsGL2{v@^dk)3#1$v^EJ7ExNMEJ#fQ>>nkE? z@W_tM8m21@FaC7&V|wK4XY*fe9If6LU#RZh+@um+mDD1t7S25)ADCZ^2AgW)E-Xfy zA7Kv}7a@Zx4Z!Iqt-&2MrVaXLL%gjq0^l^=(Rh2i$V>2GqKQLKCqQ>gV^iP~Dp%gf*3f7(? zb6u+7is2EUYks7cipsnhqez9?W*bRT!vOO4q~Y<_^3fQsfrT6a4+ z(Ywny1f*6CeZ68wCNDi2vT$9+&7nBf!+#gw8Wa(JuX%%w$kK&f6^3BVu zq*&h}n~R`{_V*Sq&?5y~XUe|ggPzE`#ZVgTE;+~)P)GWLkZr8cM_3yQ=OFn0gH@ZD zC58s#&kIdR=kzWx-=ZXQIE5P~p7(0}N1<);>nCr>FMH4qeCB;!GuvvkpHq9{AG4j$ zGDE>#Gj#7}qy(t1S;`9eOj)juMbX-*I0p$J;O`N)E|u^bZT}Ok!`YNYpo-snWwU7_ zrczU1vOcmUh^a$6wq|m3vS%(>41J=&mmL>vff`)&0I{tej5{rljw= zc9CxUlq#h@Q&16fAYr2^=jz2qdN#&k>(PD&-oQ#ub&2 z%kv}Q$mOp8D8!JvrN>n5K$0^b!^lcB*sS;^Dyh0}*LD0h?&6 z(oBSLFI=hum|b40IVhYIRij5UZ$^|^LXVK1ga|DbW;lmga`mrIR9rREVqs;vYRyj}18mdMYpCBAQol6;7vgllY2uQs>weSwbQ zpO`AXq+#>BPlp^Ko2Gm=6K%iYzdy8I&7@j*SI<#y!2H;gaf_}wJm-bv;Ur?ZO$+|^ zKZ-d7L5`H;CWT-kkGIOpd*tLnRYor*F^e}DK~~O55Q379@OOx!Z25NX)hL5Ri#TcD zhGWg_<))ngiba=-Kq4s`b{h~sLK)!ba2?P2`5q)q8Tpkz-UttNBDfcnE<6K;-{BN zGny~;Y#MI{9GoK5HTUcj)oAe7^N*M%xk zVz2ofegZ>1=Vw5C-8Sz|nAa2Ns*9wrV{~Z%vlg}i4rRY zG(-b+O>q4Tksly9IHH#PZ@>&?&Bvu^p3|&VGz8_N>FROKs)8R=eu)TP2pY#e#-(f(v!{6l1=MZKO+^G zpYX7z8S(CWzk9#Xmt>BV_gXM9QdOJd@+Ua8bY)~4ojduy3;b4_JqV#ppMtg7i@ah8Ix(`rjMarpRo!Or@ zh_IUOg;m>t_yJn!WNDI0EGFCqA*^z zV;b*_yb62Vac|O>-lYBGIV`DoM@Xe%T{+Y@aj6igi%Vg&Gy^28Tl3lF*VD4gXIE8J^JpJ33aA z5P$@3)J!IF14FR_Z5S5FI8>Z>m*&kpSzjw{cq6Srpd77Y~+d z7ebKTt-#b-S(!YN1}xtgVTwczw4N(AszXnHPGC$?`~6nug(+?$b5>i_(MDnaT=GhU zwOVY+m7Y73K~cR3CYx<}a(*zbi!hCo?wmzK;*1iY3a#2NE=p?|W4 zS1zyoZt&T-`O@Va*@L*^j{#{B6>@T{)4-Tl`SEQlw9UZPt`3ilL7cF#pg13qUD<3~x_CDWc2=6~R|85KC<40tk@g5R>f# z=~s@WkkwAFrKL>TxTM1Q9bI=8xn2`#)l{(1^wFzgMn_W*MBORL_sV_`Vh=C#C5;VO zT^mH4XpdGU52_Qvt6Udyl)aq}!FK*i+An3oU`DaH@&G-efZedvAzG-*QV6yOz9Bs? zDSnZQwI`_u?V&fjoGWeu;vLQQ7MTOC`il57Myw6fJ*`3JI6}hfr;Etu_`*b=onTpSp@9n|pW3>@ ztHIr#${p^fOv*r#O_iTOPOYv?dFTfw^M(IM5%Q9HGpny7xQ%h^+&zD|&UT|&!QnzFygAb!@ZDIO zVi`l}vGi)=n;Ll0p_)BVqYo+GPOGm%ae%~zcl?C9VJ|yPeuUeLqibTN^kWB}emha& zmr5&JrwU)1@N7~0m1|bLa(*PvZ2wjVe$8Tjc%E1Ei2%v-Cj#qp1QXI=4KQ3?sgv^aK{pob2=2V;?R?P++4TBpiY zQ9ec@k1_tvVML9nqI&MGOn}djmu+*fYxGya&75Twkc`LwRIn3wjMY= zDz02pzlrn}Mh9tn{cDmR)r2=lPz=O=cO|LBbEn4c-(6J{qPS*a6WvCidM2=!bn)~6 z>`M#SN`@Invotd(wxkw~R?ecJ3afDHS=c;UDu@lSzwg#;mFL_>dHJl^`Fv8w5QWpc zn<1@Wy!c0`{j#^lquC5M|B7f;cquglUdiE=o>u091RYR%t_=PU&_^DK)egudWe**U zS!qmM_M=&welj=8;l3bowt0AUUf7qQ%IM0ekEuFv?Z>0Bl<)FhnX*7Ji|+okt#i zT<_T%Vk-?ST|xV|pMd6O2x?kiju^YRqHZc9(TX!;OSf?&y#}`~AL5a{4Q=+GAJJ?P zm*8Bk!)x;vuwhnf0Yop;P{V`f?9LF?gZH)J1D1npwa{V7Sc-oJ!=!|&P{3H@=OqvC zeQHKWHt!XV#j}&r#qU3M2D6jpce%9fS(mR%EwY-N^t)>qtXo%syW3)MvrxGygFVcJ zoJ9vd6jMjE^(iEeWb^#4!^a<6*Ti;tbnv5}#|_l|ZJ;QsAdje#@|%r3%XFP_)GO4H z1>*rT4YsRG*EN;b$@pFdi>>yREQGu3S1?XdA5g)T6?*2~!uV^xV(7=GG@| z*#J4IWZN0?b}M58c^K4G*MmE08J-!3;=~h_ACf1s`P^;xWxy16Ny7`V${YUP@<`F_Hu#uls``mB9cbK5ZXI!?cW?5ItxvD>LPX&WfLo*0x~K(oegp#oJHopJ;ZvFP+x>@{@N&bju`ETWad4Es zGE+?tok@H|79gc4KY$pQ*H{Vk+R(J#C%PPWPcP9nOe@l_ev`gBdTJ3Dy+1v$bHn|9 z(gS*-cw1`v@E!{2&M?0b`&;k%@gFsf@?t*=T_0;UhA}g-0}psRL^6NDmkHg z_)5f~n6x-Iq}mFv@l!J8VSc%epYWMLg`WEWdRDLeyOM&DszBEwr&XKO`)dM~sAa`UZX~Mc6OONi_8LU!B^?_s@I&kB9Qg zXOJhn<1qjmh%87C1RWVTawB!;UyxHtQpj5(ww#9l8 zM5~qA*H9L2`*%a5?T*dhLS2toiWun^5*H!^j#SQ>UPWX~g}*buAE<5lSAsahw5w_7 z@?7dmLixUqb(uiSKpHsoepv@xshE))L7BdexLSF~WJZ=&Xx_$Irc6b_Lo@BhrLcjl z1XrMRaJiThAG_*XSyW_b#&oe?(DQK@pFdTXLrkA#4&6Azb~cX8cnr^jpPjwp@Gs`= ztxk5mf%bO1ox44}^{L|BvypWRVefKFTH~f)Rdtce>rcY?m#B+>(9POTn#kQMwd9Wy z4X97fKFx6yos<-edzHL$tt0-S+Jys3Tzw)?l|RD$je`vz^6$-l=l$`AT8?)2ewjZY zty4HJy37SM8u?J5k;KqX!D}mP(^>RjYUJx^mt5*i(sqjIzv(X~ zjd_oFI+&z1`Two#{kW0o#QeO?IWf@V_L`Im4wfoeCL0|s%LO^tSZ+#25*qCF{-(XU z<)2pfvNxx}>dqbh)XKajj|49FXiz@I8&^S)>%7Wnpe@M`F@iCsn_+zVCeJnH%v*k) zdNiY0>dd=Q*jnYTXMOqEm*B~sGj|W<(knE|A<{Y3c)iYfGGrz5aK9=#zvXP~u(E0-;iT(f)Nm)vj5!M$G*` z#HGH?j(?gM6}BZGkqOr+~3#*vM=-d))3Bfn<(j&;%7m1@~lIxf1spo|{HRC@f_slyDB#oM1kWyT-ZIhI@ z!8+RyLxf+u4(S}s7|KJDO(=_>goIgasw?Hv3=4#LnSx%F;l*~ zy6$2$IY*zc+^jp4$}L5d;<>hL1VnUA{lnzB*%7CEZoOPZG;%y8$u1e9@#bl$wQU0a z8Bbaq_w=x6K`M?)yKbY;prwa1^o{MrgACnz*u0m1u}E6(j&R;u#GCWtbI!ltUyb`| zX3(2^$DADw9-XMO!+Z zJia6=d|NP6L?=sbHKW|Gh?py?`LcezZaaC`C~(>v-EB?i@_-pVTH#d^_5x?a6HCQ1 z$O3F!L$k#EiqdZkc8r?~2P19Za%ghimj%_UVcm|?tu>?^R#zq6-dC;+<5mCx^7g4; zy(qaV&n-2CR;-~lXd2j*i&k*1(IskD zj@Qu&G@LW7@R%Q~;bc+*t{$u5;rVJ+17lGNb|;m?i#BiCCjU3BXr|nllx7L=@qWyx zm{~t4u}0Y4wt;Ok(=JDm*=1IvGtK`}Tr3OEbf#sqO(`0eEIK#(Tys7gLfJ7;KY8hs z`DNz8&krp$Pti}we%m&*ej1#pyJ0sbJQ9I|T7T+f0^T7DQ&@hG9g}mZMZD*?%GJUH z2xe9SFLnJKEBgxiBiRhA%>!-MSd?YqgV#4RXAnf2mBKhO=+dkf2a2n)x~V(APrZNc zQS}3e`MMI}uj`r;A((8m*KPR}y715`z3Zq9{l1tTk1k9>qbIXWS}8a zc&?(-Q(1S<(?7buD+Ed5LkbOK}0h% zTu95P{YUYSx8+X)x3a_A9gx_X9Vn;|e`h+ehdQ#-_?s8^9d7>|R2@}cUJVh7#IFM# z;s=?)SdDc>qm|l0=SVFQq*n`T)OdA>Cdd|;>q{#)yy@MzmhIrsJ5S$?VGS4 zuW05nmT|#=MV9&1Pb&RFzyBrl-XOWQ4XlY*~;0ZL3tL^AzpgTnysdJ!j9J4 ziGIS0_07P69fu-lytTJ(T8dTyfC06R`7j6SxvfeRK>ko~TR#$+W+MJsv{2tb5AW-HXpJ;I{5UxRh(y+ z^}R@oa%E5S;NJNsZ>vG)dy($SPJ}3ptBziW=msUt4jbxA3tRke@taWj31wE7w(FIZ z()27Axao%AB5-uMRF=Bi!TzCWMSjLZ$C%d9_*-uk0H~Z}6nT*Y?B;R9bQ3%_sFNm*5plz*I2a3Nj2E|#>zNh<3mbT zos3eNvcsBb_22t3e&xw?q)x zcxzA+UZSe#_3J?*X1}h*?wdpGK`?ET-ZQAZM z+gz1dVUtM8<{NpJ_wj`Zz@_sAl3~l5lIU0j0htm7@*uE7!^u-olQq3+v*&fnMuKML zga5WnNjxg{3JEYT@-&#^@)6#muk|XTQ&|o#+anC3BGQtXhD@<0EjjAB2CKAl6>Ig* z=1;Je9iUX!4KM*xFe zy<+CO;7xXcE4goe()ERRoE;dPRy;ZGcD^&G*Hsel2z+3b7XEAo5MFiuj}1@BzLe!p zRd3zpHPD~ZJGgSKUpZVFjAk1|4^H4KY|W=~YgN2Ye$Y2Kn)-Et;6cA4f<9=-a~^;9 zWYHAuERam=8*dTU^KE!JuQh-OqUf$){acBGuOMeZHNe`CqJf&s!v6=r3ua$$eVhdg ze9idJNkcxMvK0O<;l=iH4WfOwef9#JP@bOn)9aB6$1>{k1Zo*gO^8+Put|hHvJ3+4 z4=&^HtZd8In`o>YfjJ4l5+Kgt33(EP%8%v{#b5L=P;PQe=6k^9kN%XAM>rq3Ki#AB zg5mmjfK=6^Jg=vBeWkr^wf!SKG*62;R#WavP^E$-;=`!d$4lAs9M$UYW`4}tx)OMI zRx%TxF_P?_S3zBJHhWv~&0)CpYYqQ7-)UgZ9;TE$7BD3dVtty|c5nD4A45@3E_nsh%6xU$=Gs{!w{{ zY;5@W#U~kP<)#Tnp^hc=CIQd_G+c)bPt-nRFxG^nK4E@)Jd3Hb^)wp)5w)T5B~zoV z9WtWxO@HfeUvx+Bh_&FAj{5r#M6}{2fU~y+cZa74qRLK)u#&FMKhM*r7!Uj1l5jnH{}9Y(`JSk0HyocqJk*JkMu{$uo7XQ(5kB;~~dC-1Yf z&AMggjQ+# z*Ir`i0_7p`b*njrxRwdcEK^b{D8g>L)Wy?pp#^Ke?7E~#3|&RUE(ta!uJ*JsDFTdw z7XM&K#)v+Pm6n}E2W7xfu8JD}yI&~ZnX2Ym=aGf9HAz}$_r~?t6nP`z8;4W z=x$MSm%ZSe=&XFOpPeaH3MntwTNtT1SWM+-PM=M_p(T-6xcR5~3A&_ohvEE#xS(+> z$-;o4!-d~IeVB%UpD*pKvx@y37X@nn%@r0_cwsG$I08u{q z*1``nYyk$!T4LQeIgGj`>XD=C$~M<^^1NxVmc-eWKiZ%OJ+TCP-mJCx#fJK+w`Lv! zN_?*sKe{MJ~}v0#qsMA?X)_M46&5akU@&qO}2Hj>FSw%d&JmQ@Ns(!^k7u71*2D_r8DeQhx5am~U z%JUW=jBmzI-JFBe;}UGN`Un*%CGUc)&Ka6b%bbF2Vow_0<30DXe(WqMjw-$?cFyJ{ zrd-G@ID2A2EEa=-{=d4MZoN1R%(YVdd$&dNK3c8mlRjUPGM3neOTi-cT`y>@ps(?5 zd%(V(fm8-ONLX}$;~-WTFN95#=n9-`-M}nbwa$=|ob%>KV#pny7i4${ImSkd3>0C% z1p3-$cUMK)P@BEFBN0zJFb32vL5$tY5zF+7Fh$1;H7I>}H*1oreWhwad1H^%bgSiW zr3{Jhl(8$_b9!?!o@~B|L}g{*^wa1v+RH@4T;73jW7`tou=LS zG@CzPaTjGjdaTdUXJjqyej&F&{sU%Kqy-pg=Fv0F2CE9Chn$yBNk!t~Vo>7(*yQ_@ z6d%uW9nEyl;#+|e{VN+B{?H(p4gm9A9LjE)Hghvd)QzxKfJsa@ODRydqC$5n4+p*ya9ye z7e-JUTx3##g)Z(GE8aOm>mmu8X+yC^9Ju)oF}7RZNzrZQ^hhdQG~lwZ-eDA$+NSmR z#wTLO_koI-bD>EFhIZ9;z3!%6@ao=_6*H*7#r?~NxCWv(j<0(x4S}T&>qIU=3Lw-& z{G8vfj9Vx}x7>X|hhD;1Pgck{p&e>X)Lj9ixv*@AR%!?mo4--u=Wc4v>3At7URBJR zQCmrX6N%X?X!yL#@x1F=l+onWE88hP3nebY7!5Wfs`>ojK*yTGXJ-{>RV%AiCFRy{ z)TY~Ph}3m7<;^VDkibF5h0eT8=?Y0teWbk-P1W^_2e#W$J0oT;y!#L&y_De7%H-qb z-|s1=^=AErHaObX^+xV^D-~=)ejO3s{0=in!%spgE6p!(T>y5#^a)Wvt~D-?OR&$; z_h8h^^WcwHa`TdUzF`>Ifru9u5(Dbq7d;(`kdHXF+73|WN%Cw~$JrQty<=seN%!Qv zPmtQtCQoF6!#vB|8GK7skX#7b+-g2I9ra*35IFJwDk? zy(O*TDqOlXqGBNtWZ-oh?b41E;6n-(OzqWx?<%H%b8 z-$9)CfXFFbij&q=?C<}N8n{dC4X`W`5vw!N0+Z#Kl=ik-c-KY#VnLi!GZ@@6m>~DH zT0t?XytR!&^X~6|0eiQ@dHR?oZ(YLUjPV{R`Si4eh|y;NQ1CC&;ob!YF=uVfpvZZY z+kKMl>f)Qwi%S-^OMIz(3s99MN)LKcLXA>kJmk^V>yHYyz)XI$H4|k}Pe+&Av(7=~ zBR3xygSLVy_HMm;;ApDNrfZmPNX#h~k5qiIj4K0rPSDkzm7emQPmuSFF|w?ycdeJ` z1gEZ4aw2rA$ki#Ers_f^E+ZRlulc$oE9txS6uENJ?vFM8k+DQK;zs{AbBFip1;WZ* zJop=uMw$Eg6Md#z!|KmGqZx6Q24>*tVNpd89N0&ZVAu#a;K$EU!ZH zhBz?}N0*b=;v$cinV@%x$M3jk+roLJQ4}9Mpz>9Z&)4BuPS|rd>LK%_H@fK*VyiVV zXa?6^#MO6g@4-wZM}4amD7CYHC_Q?hm}#|~a+BT{I?x3(6Jh^RXx1|rueMb=Q79vy zq+V9p7(!)VE?2c7{CG?Aq5et!4A&VWQLE>vBN#(Rqa1wvi%uyX8cSOq;geE=E}piq z%ixarBR;Z#QA+q9x*szeZQnM?XY9w|K*WngGrB#dZDN9hTGxh zbO0~ZV3qVtA1_vdYw7m+wn@6o+aEUYF>(Sii`NLADmbsDxz;8!|1KKXsDPAqvYIc< zjChxJ(9wI#9!|kLT7X-TUSMLJD4eh?E{BeXr$U|KV4blx*Rg@d6+%p$-}RUWoeSmA4OMva_c;FKuGP zpprQ~Pvjc2ci!p`hf6ajoN6Qi%8@?KsO~Hi-ASVjDO2Hfg&Q;i!r?YPuz`#LXU<84 zqo>ylo4N3x`3G*y+5#=mOc=d-apAnw#gXASpCsid&&P~&N5b1<3|_q_AC>J^Yp&3% zFFBe-66Slh6Jq}UEatVC^>1sh>OEhojPMnm z79!{R2$@w$`!g8vIHvNi?cM~zz-OpqLZW;SFjl3M@&@cK{Khx#iq?n8ADfN4961B! z;n$O;C&+{#XHq86AG#&On05k(b+xfs9AK93WH4t;o5M0%{@FKW4vXNJ%K%In<5@Kv zP%jq97u4i)D4LOy{Tv^3;C_(%$8q|Bl~Yy$E25h{HiIK31i-ucKmH%_62%f#%!n_}b~Ja>tdX=U)7>sm$k>OzD&eo&r0B#vRSgpY0N z$f<_lxjI68_4v{fJs5Mz$yyf4I))|vR20jw?)>n&U0Q;Jy1th|km`gD6OgFL0q*o9 z3T$=)v6Q=Gn?ye$&@D9dWmTAPf@k}Z*o2~E$zZsx7|k)PPtjf=b}iT_)%b>e-O^$V$gR$$xqr52|MD z@uRSG0aHtTXzTosg6C2&LaBZdd2%PN1U95B9lvUb7wDu#jR>d`Hvxf7#AY&u;|NBD zSK`7HlHAn|V>R3JD64R&Bd+=txTL(f*{O)Dz;?sBvW4|25;GJ`&)2hivB-N;7U zy<}!PqI}cq6#(tK-}(#(M@+PnMfCLVpMMf;)sfFs{%cE-*leUfyaKDgbR`wH-rWY% zU8-Zm8JDE9^DD*Y^wz(GO1p9eV2zl1UoBH5CCi+zF-A61<9B;)7&py)LrkV^?{f9F zy!Y#6SKQpE&OY4-)19_`%6{5}Fve>%`__9zp0Su)x+JTM1<14KUTZp4Tt2<2w&+hMH!{}N0x^^_Lh;<|}{AxUYx{hiS8Hq&Y_hvMvNApkoA4zB7 z*VO;EaT*Z>=>`!Hm68&W7>KllA|N>sq(geZ=#&oW7$F^#7~PFXNJ>ac$3_m=_I=Lp z_526yaL)PM=f1A%eFbvdw4Idm<*HVHn`6#&aWYDjjH|;Oo^l3r65u3oK#+zMqj>ij z$~%X_-*COZ=L#3xjgmNaID(}A6^{T!=XBI!n!>Rwm$tvxC1xL808E%&jWY-Nq=>nT zJez-GviTgy(&p0ds+CDK%-XxbG5mY5MONH>a*w;GP;L~sryKw80ZVr%<}+n&TVwV@ zA69jcB}c28=~sP$S#{`3!_TH3JJiW>NmLUii2w&-7HYLA%zSWMF&!2R!x@W7T^eYIL0zRcqQ*!>{R5hTW;uqOJMshLg-F~Z3>aw`dlJY8HAVWwdOp3- z^C>oh1Zn)1U~OL>yQ!(AOIvA6`InXxlsalw42tIDV%_a9ne0)Z1!bC*LzvsHdcom0+-F-ke^$&8=o`_d1=aIi@n!1P<$BF)%6CS(3*ExT&Tj|A|I9tw)noYYX(QLsb64}4I zi9I)29-`Yiad}*^qBPL1vL;rc7p713mG(*X2+{XJJ4&}WuXU@CxAD5-|5UWy)pzOE zGFjb*N!cMK<`0H+r1$u{w4@ff$30ThcW2+hsC1CRufga{c0W+#%i@sU!4v0S?A>#Q zlV>RRd#AL4vZ?07#Znm?5lz|@FHJd1Cd6(G-~8)@GTHH=rhCtWpOtFTOa0FSi;APyag7-?R;1wv8C5z1z86_b{-g)-_ z>(7DYlvQS}#^Vobv&#Q&D?3WdF(HPjXN4^USQ)P}B*V}t&w7?X_d^e4Di-4;QTxZa zOm7DzIW@SPH5R^R|NWL=E5WXR~+gv-nopGtNA}`gV^Z z<;^m02C(@1K*+ry^+AB_eDs$Mk8}+2`;gN-51};PUk|ZYacn>3#_fz861{QeSw+i# zj%3Vu-?4@70?$s+cyl^PbmUiZ$hFOc$=(ASY-h1|++ND7)}6hI;aNjPMRYR0R=f&l5GevUr61k=tD`VLBN#0U;Oe0&aua5HS zj15Tme%V7wCNEEium);E1^oTH} zW{$UEKRnjtFLy(D%=r)ir_R~=duameI|dYMsp#XTFB(s8qN{{A+0_yJ0gsskFWH}v zKe}cxS42c?5BX%his`m|WnUrR3b&6hH=Z=Wz+!3zX2tX~ZBNb}KS|#jHkG>;u z2v9WUE;!%qE$h>}kc&!!p#?=m{)9@xpx(eoviXhbvNe$SQTeD;CbO%LJ@v_SMH`x)x>LdOLdXu?7L`!5@pnCS0w;NZm>cn4vtG|QntBcjEN=V)QayO z&oH0vgL(5ROFkew04k8uhKd+E6WilLbain}Z=lM&e%_uSkD&hc%qe{zD6*|g6y{F9 z!y(-M(kOWzx#-As$~UG@i>`z%5SGC;5;mgpr8&OGYW?yeI| zVLk9FD3b<8?)TXj`PF+E{i^lM&$!8Xq1^J%^|L3o_qU!sIs9rGv7OBAiL`>bj12o z`G+fLpEolda)lU)_|e4vCC?Y*a_ywDsoY?#bZ)*e=GvgQ*mmH9Md!it;(iwsstdMJ z!>t+Oe8fEs75vnUtc|(gYjP0Af-ym7*>1vPIJjpq;A$P0rZb1^lyVQJ zs!(}w332a1U@*F23y8B_Z;WdKOKf|T=;1)yX(W^v_~fEk#K`}a<@>UfHw1Te4YGH! z?o5BvtX5*r7CH=S=O&eA<+z7t{|@!S=3<_0F`!zIbU~yTiA~r;^Zsf`{)`r*4TB_1 zuuPfT2f45vu&oOtF?$*#2V1_iyst}r*10ot$t-m-ZjyhnDNMxMXh=Kk$`?(b?#fo3 z)P^V-`TU&np4_nCG)%AYTqcnXojUA8bNH&Os(eMOqSeD4?Q1iPKXxgN$9Aii`!77&(gn8IR6DoW6%=&CzjMs3_2 zVn#E_F5$rf)F9Y@_-JN>GqOt_odx`MGK|?=hm!sJSTuZlZhh+Vp7@(N!=qGD-oYc7 zI6t#l&yXTd?p90>wx;93`hR%AFa{|11}IAY(TuF4WhGhwGW-sv-N};6B0A>g!H)P2 zAF*e*e2@g8kdioeG9HdmP)XFD`LvQrI`R2AlSMq%kIkk{@Ol4W#!Hrn@zt!2EL&@` zGIjZi)}9IP^JTs=jei3(9&Qb|MuP2p!REOFE+;tk4+Vb#B^UW(7snheW0PmODjUT% zqb8P3Za5Tojh0+u{8YgmY543`N_N>d(DVMePpA(LRi0h6{T9?5-ygdH-rdr2GyWgq z@Z+T`5xMd-P514jj|LAAbG3Puk6O8Mk&Dt2q|ul0O8vK=RGGp=YoUWy4d-y_>CYXV zv(qOxb6al7h-Q44AN=#!kCFz^>+dKEc}8q@2i0a%v;Ut)@KVhD<&kCT&-4xXQGrYf zMZ)kCDq~bo^cn!j-NfG-0sIdyTaj$tv`_^vS9S*T?gZl9wMyeI~q{c~5#iJ#Y^Q@$xFgP?!+I zhIXdRLEiOp(z$eT3dcAF^4eFiUC|zpTwQ`1WR;wP)leFbgT# z=w>0_WHYM|s+3AkfsTv*)SDUW# zy459CCvSubkxB2HdbgIEnw8&=BD!MdZ~OKw+JaKfKPY$3rj1GW1E;&39pRXutc(|N zpA5GJ+b%r-{+@IQVfH1DQQu`&`r&uq{nVR@&F?;5nHa$t$i{sw3;rD-NEA2$NQ}_y z<8%D2cF?yo`5XFkD*`q+bh9fBn{1uHxkSEE*rGL(&p%_nlKLN>U{GWAm$1JxXDI?gxE{+F z&?%uNO)WVBPi&*NF5x*xF*h-6(Dt9n3sO?JZ}>C)JTCLeAOEPbV)K#>y|=t|P?Dw3 zOFBI4)#)-u1qw_X)JEDvCIXc&2Sq<4RB04tn@*~tlIs4$>oTa;xHfz^^wpo5`kc-M z|L#f9*G>-wdZT%D-emj_zDBc>t9ZG=_J-*0zY;XtpN-~LII|XlcU$S71HI;VrNP{s zzTNk;3S- zfexjFfCGhfu6Ugj#eZ&-8hB8R!hxD=D&-nYX(E@2E%=Jk2YP^#C`zh$xo`ZX=Vf(b zzb&2>o-Rp;7(OdtimC>=$$WULsMoUj38JA#%}VJZLTJHRVmr!3E99|j%S2d$r$LV- zV*;f=wOi~p-ST1mx^MW9z>?@Dw)meWrGNsGvz_;Qq^jest$kf-4wH zwfm!gdjG(E1umZf)tc0-vvMwr>?#<7Kf;+$tS<}jpGaXPBy5wdx0ir;qqn(m>{Ww# zjfC~V@S$>O{kspCH)wVt*w*P1NI|n|G8#bVscUl+;G%u3-iXNLP%edtli4z87B_|Lo5ceMT)2^50E<+Q3Kz1d1l)rYlIAvL6 zW^vqGSrKVYPK34n&HAhm2fs-zb1;rf3~;QpH*5xKdn`p)jMj{_=NAlW%bxEY{!BjL zw;IZqK&d8Pjs;Pp56w`FUnOpwmDARuC63(>KhB?6l0JS4j`Pam^ zu3z&rFZMOY8UOjB4Vi@c>$3Vg6U7?Jc(l*gcl4Bf%D7`8M^%BlVqzP`OX);9$*5HgpreMY^^?5EAzE;g#t`@In z~pzk25KX*i7{-xOE9IQWTJxBO!z{*Td}bx#2qtfM)j^{(4Z0vOhP34f1f zMbd79kLfoBgZhE7L;UoClJf>TF-B*LlM#J7NVeXM4|zTMIe|Xo-5iHB11-N=pTu*Y zOjvTvIJy%VyJ^_N$qWzf5`?&es2mqweRy?}>Q#22UW;}dNM~e?@5E(Ps1QjSoRzQC ztBw%4eBh(Q??K1von7+F72C1UHmMTcZ{b4%#X89It8dugZo52^Rh{MY4R|#48A@hd zwFhXCSfjuRVx&`St>-^7nYQ&bsyIBxGug zt#%NDe+R-;ryE;__FXtmPRXp8E?}~Thxr-E#C|YRi!+J@Ouv_{GXTtr%|klC+_N!> zx41XCm3TjJ7{@lp{3u6%{v9EFnO(?=K!GmH>WwLv=(NjdU5R&c;)c%Bc~3qKvi2*A z^U4XC(17B^-RDQyYR+|F{fC>|YTGwJiypwmbh=|XcrP&zV9MN_uXN-$hhsZ#O1p~Z z{~dd?6WfHKfS2r{uIWIEDD4%i6(t^vUwb z>tDat`3^wCIgV7+K){pnsI>-2=u{l02Q4od#++VylrCfFW>$7wX;#LrYtk2^Ush7x zzU|=PAF9b#){iG;mGpO9-u9mD(~g%gpggQVaSnjcPx*R}xv$JnszbzRX5UR%#BJ2j z7&si~VUMI$n2t*-kPaIWr)mGSMd+Ga6Q@Cel^opg9w;Aa!0w)s|KHp3-^!^bZ03-(OsC6w( zO>7cSkuVvxL>1ok$o`=YN@)`uFDx7xQVb<&n5_*3Lxzo$RTmcq8Jo6a9YtVAe@s1x z9DiMQlIkGPFy!4P<56nia3Rz(YU6`n#^9J)kY;<70v7H$^8TY2d4QFAkkHVUZkF}a z`lX^t=7(uKEsx!pvOj8@2?xmp4AbpPk548a1c8iKbKrL7&lfQCKp=B$gOe5g>E;4N zw{KjUd+S~0>hGX2PB$`qT0s;lWwD$QHe8JXp{lhkgVuGT1L?u+7}>ehvCf2@iKQ(= zq*JdNOKqx$3~{8L{tr}Qy4}C$8XF%2+i|~*RgZ@6?4bB4+hb*W!RyejN6;5jwSov3 z{o0Bd;8yH!i_D`)6b{Al07VlkqvZGA%gLCmm=+00GJCBAJy@S7DFV&p(X+Xg^cg)) zVsjUppd>YSif{-G$JEL^^Jz9c3qmz#A$tG=Tgv zMlxSCbzH(1fDyB1zPKTaGuMLYl^Nkm`5lhOSt_j zzoUf?E|13oUk=*{Qw+%4EvmwGX+F-3LE{XXiZ?$a8B!gQ-J5Ufq3^NzU0gqJPlIIx zHrn+YJCWFPRRKcdY5LJSp)%K7WLaagRtwKY^ZssTCK|rPE{$`uJq~gCY=Pbk{?ub($W}?Qu2}FSd0;2gs$nDo4Ldd{GLw|syXhmbF$?vrM34LAXTHhY$Y85;%YaUq4 zZdLGI$;;Gl&U&iTK}})F`C_~M`HrP&HuKr?<*LDB-1~J$c`H?T%+{aQt&*fK;PrtF z6&Y88==LAbvaOPav`IWrIl6>~RhVA-(2UK_<)TRBA$$u@|slaSod=Wi!x{`bZuKnCWO zVJjM4sSYyE51Pfen(NhS+0}a2o=j#M^kDOFOs0xg%P=B)@9SItCxz^TosD0N8-NIC zwH8bQ3e47249KpCN|R+!=xIv7&TOscjoGEzz?lfUIcVe1z$IwCbUqrnXoL}LnsqAi z`nnCkwnL01&2=XJ!|R_8mg^qG(IPXartF*AWXzXMU)7}a5WU0ugXcEHKOz7XuS189 zy-$!a9qc!*zCYiO;wGr#JAObFcX1f+ZAPU!?IgiyUtEV^Es6TY`-4)(7LM=*$I62i z(d1gm%Q|KntdT2%8UK=5*K6*;i9Pebo8TU^+x}L^@+#i zhItk8^lD-@P{^U8^dOK%i%^|~dy=7;{!XpSLW(OrSaxQZMHYpw(rZsJYN`x(qh*>! zg?^!w9`xWuCK~-L{Ad61$I5ah?9lx0rV3i!ujp_v=wXNdhO>jZQLT8;1E?s+GiB|U zFFO72Aj@ASSs{ZSc0sllVVrbb((Qg!p|@&$xZ4Ghn<-BYQ>bup^QtmPfBX%Ux6nOs z5?>x!WmuDe&CB`60m2sZkhVejk(IO;e=B#-OGI#!KVDdFx-Mxx+VxzeK_V(#3le((_)^#m%t>RArJ9eV{*|CVL>Oe3GRajds9 zNeGE7z?f-WdfUyz`Jj{V=u;Gp|ah3>x9a88Zlv_vD|Xgxo13Z6grulJA=n z9A#on#EM6^PfSDMPmU^nhJ-4}5)S%-LL?FwH8(k9yr}9RL2Ag1W0D_>_VcJ#K%n1L za`}~MV$O2bCneK0fA24=%z)R^sY)xe`1NuqKdw#z$kvV|0*k{K!5z{ zy){%*Na-Q|@;=xb==58M9sjNRqg)7y+PXg4JEZ$$NdzN4tznKWUmr2`IE&eH3UbmS zUssL5SZ>*gw@85L?EEAbFIdUT?2o_at5}#T{yS#%uEjshMz3iBBTW|c9XhLe4-PDs zmpGy}_=EAM#laDHTcC?8Az9$-IQSLq9S3fKCMrO6tGhRr_%K#D@;c)uDfk4*$;_$`B>{)uW*?HybULDi&Cvc^AO=X4K|LD2A?Kqu?`4Ti{0?Kt z<20D|@c9o<-iJfWlj9NUS2tDHvp)_hcX~R+M`1?`ss@ZK9-<`Y^snP6TujgWVzf%y z2|F6me0QFXuT&8008xIPgD$GS$_f-E#Pz$2c=_kF>f?fB%@wm!6@vBk{0>9TlE9Hw z3A7m!xN!|KwjdZVD6(UQ{oh2W>`NidW4@mRzM-kj#a&W|`TPTy-RNi6gZ9E5S{pg6 z0OzQS&CJ}yjN9nPloiY%;$b-Dv>0@8Ie%rRGk@)>0nNVE9`I!C9XiT?L*}x-8^inR z^I$rxT;rgi$W+0mcZ5$M*doEv*jeTeRkqhh7taUUnq~osOBV5hW!ufC51n1x+$mruQ6BRGPYdPxbnKP`q-}Pl|-sIU`_Svq|dK6Jzp8fWJR+)0C6a+2tS5UIyi= z{`fxzTU^G&Ro?Fl29&4<9h(J>y|aHgmhb84`S&;*69>B=nqhd5jG^+vkalHs11fg~ z49OU1JI*lJV7;mIRKT_YU|5ZXy z{_bk_Nrbinuz{&FT3&&*Fm}z|d(&r1E-8(eT+Th(g$Tq!=!%mWTrWS_R6)!n#= zXz7Q?*J6J>fOrrzDCQ6B{OGg)YV+@kG~pEr=5moBuQ$wIzFNk12h8|mjTT5LxWevJ z!Z6H1&CCT>uF^vLOy*OC+4eRS@~VKU0<@m*G78@5;{C{L66njYZ7Ie zBWW(H{;VKlnnWVUf1`&D{;rJuAxnWjbZBO&+H&?4egJlX{d;iWt{XHW`^E8}7}a$J zM*@ChiR>CM>jcN_#Duld+@$ZcesytNDJWAH3h#zZuEp>RR zl0F(xE*hmw-plxlj?K@Idev^(=wmvq#KNDE?f7LjEMARg(%U{6dxn6{CoS8%s9KxN zX|>w^<#I?rbWdJc_UcJHlaSzvpuws?XTt#CnGNdXL($>grK5PJ?qwg4`$Hmi-54|F zn&tyiUz;LkXTBev9ZR1ruh5Rmvichg=JjXc|9Y3cqSN$1*3{&$h_k){dD>mIyi?+r zrvyu6d4E)#cf+@nFlzE?1hF({+(U!6PE@mZAE;dI6Gi7Y{*F%2CEw~!Bf1Ff>wg{t zo5Ax?F$IR>V_GVKFJlim&*#oc8`mSszIId{`ac18SQGA4Ck>>np4E4OydlfS2Ff|w zy~?dwufDzaP+)n$kbOk|M(c%?5Gz+=jr^P0^|#9%_KbIrX!R)!MCz;4C-K=B9^~p* z@HHlgY_I*0{twS!>v8b&*s+9o52+x94nl3^4%m()Z}dO?j8ucoSr<&hzh393LrS8- zTFUg;F);>&Zhz_E&{OR`1h4Z(-RYJdlmd;E?0!L_^{b*=pSS08L- zszf@VD6H6^Ctke@*<>y^=L%o8@|nna6F_a)e?Ke_a~r69lQ;C@S&AZqVjQM3(jyx$ z_LxHbK4s4e%-C!`{wJF>NK*EG{JZZmh7p{Qts3Jy3MB!lFC>A+c&|sBU3u$*9m11M zQ`DWF?T>?>@UW_lB}A1vR4MvA8#)r!eM&e`5{moMv}@ee>Z>h59I5kS1$6hwyCzHE z)H6WDz^fsWAE;#lHL|U|8IJ#RS>o>u>U*)`;7Bpw7Fi(M?(Yu8CN3uV8Q`^cCU2rB zJ1c7jF}6SJ8%10iW98TvN*yQhZ`1P9lU<4PLpF_S5X zWtU$bXx>?NYOdFoAGdRxOn>E;I$hk{HY4o(WJdg$`GSA6Ix}Z)HllSax#PMz{*@W0 z=5N^?Ghnz|c>gJ3XZxQzU+N@qGnjWCrR)CrYpO{gp6@xoGv?Y#2j)L;H;A7^O0Y$!Vt;3ciF0X4j^~2OmV&@jbv7aVZ zhjf3$J~RIh?>NQV$e&Mc91m>fesHy_P_msM)i+*&&26lvQe^RVReEP?y11A90ymM^ zKVw>Vo`;}2m#84asnjl+A5hyHrq2vxa~wT``)ME7ptO5++*RF7huVeWvH8jIlLeKF-E9|XwFQc~N_jH=2BQ^fq`>+*ecJge&g<-3L{b~W7`L+v zCM*nWiklr{fxbs?kF*nDG@9)uUi1W68;5{dvdAcWtn+8 z03qeBLCZ#3N;begJbyRQ!&uc*Z7j-F)&oP>jF2DCId+`fzbF@ChF)$5^kORJQ!34> zY^9iS`YoJLw4EqM=J$(x;|D-^&0?X)FY7-%osR8)JJ37KF&Kgd=_i1rjDzrQ7#&CD zAcIg<6r*kvY=G7T;;Pj&-KZtb%9sHCpN{*bCTlw|ij==Gz)pIC68$iRXnpSxy+Sjy;4WLnz$ZDw@1@5a>7+S2+X;zV|Nph-Qh=mi_c2O56HzHVZi zAo{xJHnMEJoA5A@YsLvtWzXGhiAKvO963 zqaNk;H@}cB{o24gJD}#W;e}0evfxj3X6{fWeu_kmzPZLxiE)9CuTsmH=T&s&Uj2s` z?*LUmCju+Hg#_q36srMf$qyc5W2X6Tv_B`D69pUuPCiV^9*jZMfj>h$m-S?ufc&Ex zGw`en4;q&OJ5vkst#WkKhrxvGim?2skQu4kFhita0>Jhwb1;_x94i~*^StRZI`TX- zPkz5Y9bK}1(H>tC?pN*`r2j%Xrk{1FMl1C2xFx`LC5B8P>00mCV>8KLm)-l2ixB0j`(uW- z)kJYd;znhg_8#LE(F;CZ_kmOA^fk5FRIoRSb;N`b@TA&m91BbE@41MTsY}#bVKv!E zIp%%}thvq)q$=_)O^zr^k;)xPYus`(HprK>PS(EwqK-26S{cYKP!MSU>j| zHhMmKDYc%g3#nQ+?CbYMx%R;*5LD6JLm*PY+EdrmLE{}*xxKu2l-5~LBMSld*CJ}3 zQe{=!5d-3oAy@m9{i(pQ)yG}4^@bYgn~kdath-{Y5l^7RB=B!6MrO$>q4;%?GQj78 z?n0ojlKQnPnUIyiL{L0wp}LG& zv7*omHawM$uv3L^TTEN@iVsFOL923*3c@DoUG8S4g1vuH?!8%Vz0$WIXkLAD@%O2; z`OK5XlaT9KzMcBCUvOqV_)Gnis@bnNDmhYzV%d16B#xB?zYpnWKOonBIJ)fowa2!4 zsm;;_zjkY%#K%|%>&VW%lX`#0Izzvky;|ep>|WVkm!F0xG?!bFPUTyk4}Nu>#dlu-08Hp|jH8_bN3k zxzQ8O6|2{ga;zIUbmVtySY_`fo*eog-U=Q5OOKa2-lO9Iq<1gc;K!s$D8v046rtv% zESqVc>LFORo6_wM%6#TdMuuV%1oqcTYIgq<(U!WTgt+oq z!Eus4x`WJvbAR&ZCwy6+wxuQhB2k%SU6}8()e=`~y>|Y5^TTgp9@G?A<_6pV%TZTZ znu6+$t$Lez13J%#*wi1aW?7`FhD|kU({T)w<{FMNPK#%3jU{yit#W!M8sjMx*?e}1 z_CP0Glys!@5N2#dgZvNQsTs+yPnMIEMUyf^ZC9+s@gG03pi)dA)qpsq$jQt~Tm0el zS&#rZZRJ|uP2o!~iITpXc;4ur)wUk=JTK5G5`=Xy)XL<)94R2XCVDsFw*TQD@5H(^ zTZ~_~)y>p?2ef7M;#A>*DCr-=%3Sqfhcprc?GcFHYSrs@&5#A3$-P$wS;`4dmy1NU zB&WDx76eI1HIcFDw~hVRXh?33%ggf7XB*dDG z?!Cy3=?^~H;{v7a7O#j;@z-KYi}1vFv?ClL$&3#re#psp0z_h2di~ zm6U37j!N2yR>t}85$^cf7NX$pU-Rd9JLcat(6w@Pik`RTXZEU}(aY`$*3aqWkoF`bRuol2F4N32n|gdRHy zVuv^S#WlR&ommN*o=as?zgH@dEC$GGc8Xn$Te!^6W3hNz4cyT_s7$+R+l0gPV z$SQ5sFm8ZC5n7(jF&M8+?>nuG2m$UL|E5H&r8|D)s=&X@IDI{!JJkXGynj<1Ox7g` zhOoXT_UvZm>km+eij~JDiFj<^eEbiubnW19#K}ugy75MWvHST)nCMGWdg+O2xdb}_ ztQ)pO{-GV13}Xn$)1Z2@g#kg^D-aNJj{yJ5jir4S!B*Gigrg&mu-Lu zVm~)?NN@UO^-I`Q)}X2GZDEhQ?2l^I!9X5hUlWX*5)B;p0oVTueEItV7M^NHzHYfW zi8d^NG~Yck$2Ohz!;ndrcO*goR=W!mnW1z#k%0tg-#fy<$>uhn9`NGVu6s+knKe$_ zOU-f@)WWes^SzyOPeRFAL~luAhJA6r^%P$#rFPD7SVSCjrikh z@Sq&1R}xUEf!C4F66d;Wq!7k-V{Pf>$pe|IKBVy1A4QF&C{i-O&?&cgX*9F)T2p&-rH#?XcNY|3Q0K|dyO)~mgPOEppPhO zQJGFxPnWWgDSAK=*B<5~cYUmP=L5Okd=i1uxeA&IvIP<0hL%K7i!JE$buh(?-yJ{% z&zzKIuvSC1sOhI7^=o-`I{d`v-JrtR3?*woB)qF62o9ez&al9R!zh_yk1db=Y4C<7H$ zxU3ExCnd(&u_DjEhm%d*8&carR#9zk%Ha3S!F%lcPZ8GV<#z6-Vg!GVJ@Z7tl=fHI z2B~grBFh8m|C~ROvE9cbr?a4x+DiD=mm+%L_`IQk@=bQSWd03Fw@lyEue!{#+?^Th z1@4}3(Q!n8J9JkjKFT#xj)JgSS&9h`L5;?2jz*u zk-M9d(bZc>?Ly=MyQm2})m7|oK>!b@Vmr@smXKB6f zVGbJ)DelA3p!+ujX?p@?^UdUS9{d#Q;(#hO5leJOEEJqXGpkOzm1Xq4T*u_8GSj0A zQM+$Yxj>n8F-o&18{WT0hOxn>cW?!ip{q0&T#l;&f5vO%(Y~u!gBBWDsKO1(CPv<|P*{0Z{A%~8xo%hFSH}yc^seInJw~>t_b^Xe(b8MO#7ip} zP!sxeoe-t*AKn#Yq0HnzJO&JT%H{_}Ak4w)v1BHabTs1;4 zua@i&Q=%T&kh!$A;6mQpE$x|6exaAM?Rpgmtt|TyKp8B;hIuB74t0fYE)Hj|ZG(YA z+w_Ld$yc%3#66tnlk~&#g}&=@Plh*ahonBCf_m5JeKP=!5BF&4PnH*mTvl(Cz~Pmp z&0pG~*TcSL8Y>}ym>X(BW-ag{?Wj4M6eN{B|wHwUOD>27}afWkX ze8r$ekE>ksBG6Yq@`5AMt0x5oz$&7zOK&d6j#o!8^>RP^7Ix+R9x$!?9KQ*sF&yY( zOoD&WYHDo7wAB2n^pqDhrEp=!a~GTMRs>nMxE^C@;pY2;K@F;3x3#p+@E=PZXBzHq z{dhnAhwb(n-U71ft#W)R{|Y$)6HZUoVfY?19&RQ3mTl|s;W&xy=o&-54XXL;j_$e+ z-1L{)=>&eQM<3%%Y?zBun$tf@HLH-N?$<8ewxDQHbj+PmJxty8m4N_<2rNe~XsAN< zjt8nVCn5Yw27Z4(JgzQ*Kf)@%13v~YC?elPn0#+$<*$PUxdovZO)=jZ5-x-uqwtaE zG;C;TZOJz&M5ycp`rp4@_<)7U>RE2637lSCLZ6G1el^-5n(I8M0Wh!2+L^97tP z`89pllSI-tr&TNyD{4IoFax=cuk>eX23Q6NHjE5hAL}uZu1$9hVDor8>sn^E^3OD* zOX@ARZ>UG4in0pIwh|ZNBimyNZ{fyy)tX^qn zVH2+fVmhne`eMkAFlpfv!iaS;g=y#W3XhCsrfq&0+qu5;cD?4ahdNfCcfg6GBba<) zX^!0#1`hYv?;IVG%Nz2Y-w2QMU!eU-8a$>vBDoJuV=#`LA!d3TYdt1L=fO!(vft?< z7xsh(b!itCzLe?CjN>8>-c3GSE%9CqXNhunkMtK$tf+~yaS~qAq9wm9?_nGloCC!n zh??(^4o)P)Y=RP~Cz0YO#*fxj3xUR>o>=?)%Ls?Q@=zT~0f(A1hEUxVAC*>9Jz}X% zp*H|{zC9LUKKSr2=l}rLU9~Y8Dc((D+>3+{o3kUky4^Ni@rF^FeOId@KmdAmrJBUP z(f(Jt?#vg6b0aNghjVagrW%@y`pL;8>xG4XD+2*G)hZgwbK1l|g1yV7dqa%eLl_ zzUVxkwQ2Me#WK|mF&!%bjVmf z$SqiRUZi^#GR!TW-S&f%&)AOP6}lwA3~-5GN$%xiUvLz8uU7kC3Ib0mnB}*_z!aubV)Ah)Y!L`78XHH z`!i_Gmi8vg0$|5qt14B*WFqyS`{H}F7r=jNS!qJFjSXn{Mm|&Oe`T|k_*VRr^gtW7 z5umr}T_%(}zBA~Nm2jFV<(f%DRR?$e-MyaM1_1ru%#y}+sBf5=+4#(ye2S1@7q#Wv zjo%U|RJie-^uwHDGriW>G(B9Oz^MjU;ZaQ)Nvc6L5DGJ$Ex}idWRghxJ_6=kLI!*u z+FVM+^>B==JyJuC{W01DgrSp=pm(|n`h$D&(Qtvko9VKGa2LcHI1Fa%Vmxg2`LsGb z=;uV^ikS0!#xZm=r!Eco53hriCk`%43vK`-l?8>bd|HvG$M}VTb6w;}7Igc&IhTyS zZ1~{jQY!;&kqw)q^B*N z#}j#gPWMEfLtY+uHLGEUsMEG02$`;G`8QRM=p{q6PpKe7WAD${(sY;yLo@dt{OvAL zFFg1U?>-#EjZFrK06|UWg;gi*(~&jzP_ocll+S!CXZWq)WKr z`Zd8ffY>>c{jb(x0+iZdpoVWmf8zuQ3JUD8mRvZmS~5ZwPLs2gITz+rSaJ9CJM?QY&Q&Rccnlwftv-|hU<1@~Faw^S}gK99Xg!j^Wl zq8r{J3s{&Pk}CzjKN}tMh17NlL=U${2XIAg4AqcIC1_p};_zzBxjndAG8?=z@yL4a z3Rqqo3n;0)sZ__izNCu-v%9~Vtzx=Q`kGigjz*5Z)}$e~=IxjJxxs-5{w=rRE#050 z>FfDbhvSdr&aX(57p?}-PGmr@1ZBOP2QFMINPj-MipGgmJw9-6wVr%ML*R5xRx=(69uxVwtkfV|NAv?z6@B`O+~k4AyPe3dn|nU# zcvyb5Ws{+hf1UZH>{fA--?S`w=X2Ri_*Z3q{0n!Y*4Z_D+>pjY3{Ng_dE->}1#3s> zw@Ut5(X-1mE{toG2&dBcNiw@FEnbk18c8(CLVs&hY5)5p>7TRUvT_iRqhL6ZXC{lvtAK?xEJG(_F4HEEBrz9<+L5a+EP(VCtk5Cqs_ZPBa!1)@(0HQb}QDlF(%&ah-R{F zyJSAT7dutq5h&Ib#d?C(2e=HK0y(q*Nmt5*rXku-^Xp;IC%r#a5l(m-Sz3YtW4 zGmZWwE_merA)h7JN5RCTJZ1Sy($DqnIJfNj+wVhD&;N)eTgTpYBblT^zn6A&hkTao{%p-Mruyh;rT} zMGWX#bsf3sH+)gxeNkK{f3fTRoS@ZQ`eIz-&DXfm?&TUhiN4(Q|6}Pa{F?m!Ha-MF z2?^;M(n@!Sq97t5-JsGSEiiI~bO{JZ4n#syx;q9U-3_B8288HvY&< zhWWQBjHOmOGWulxfVjQQQ|G?MP5Vq1yz{fWs+NBgVA$EvUORabsOceZ>Yq&DFBl^! zC`b)uZaxb7S09JWkfQU~Y=Z=7H0rR_S(xK{u;I?|M;*=At&9)iieO|AqqoNIA2jK$ zGH}_V$DO)oDk~e*<6A=_#{%@iB`QaPl8tH%_On3i9WxSgg^!Y%4X67X7ao_B_`QPy zFL2r6wn_Fn+;~G&zYkhSWZm2E@pXzCZY&_HkIs~uVs)5e29PcD&-%}XKGLm*75v2g zNm;Fr8+D!7Prph&srxOkD-GyjqabrrgrQxBa}6mj>TXpB4zb0G1^LSO^0$k8(qW;`%c~mig3R=@kQHHlMT4ROg(Te%i1-x_opm~!r`wgv z4-U&so_h&=jf87Ou8)hs)Q!sSoTU$I9C0qIi5bP~PQScsx<0dN*znLB-&n8JomBh` ze}xik@ngCBmi5JK1A^?YX*s?JY(7a&9;G>tt`gPx0*+HvAe&tdkNn-hfc2|RG!7%@D5?Da((QzEg)UR) z;j=s?Qy0~vHf^Q3ij<=1nlu?49yUQQ%;;A4eBnxQ)^0nTo${_*NkzW^v7`Qv2xFuS zcE?D34-`*I9X$ZpY_3YE>S(O;fcM?|@X)(*ckNCt|6AvtpWw*kE!f3?Yi<+ViW2ip z^l)j2EmAgZ8ZS}%#4e>8$ns7sa3LGa^eR;sgt5oX z=&L;P5&fv{S@l4sx&_Aw?NOCCIo;cchmszPt9!Eu_M#mMC9h7LlH&$qC`2DDd@ZKk zd=p7FUKH#KbtIf__k?zp^=botGWf=T-nYHyoo;4_j{yg=hRHaI8YS1Wa%1EAL5;Bq6EjaQ5frrk%O=MP_g8TN_iB*ae0ue=S)hFEw2b zb3P=90cU0Syz8%hobx{X?v*tpT)nY*vbutjHK47$v_uQSr1oZN*dZZdJlyJWAj|1A zyp=r8JKN8D+2yfbxUL3?7qjl`36b|wO7t=V{`LTlP;#butifz zJsn4AqBtX95ci1~@7`>H)EX9NsQt(Z^_%DQH2u@@zaDK1vGWGAUxKaBf|(S9Q@x^> zH2DY3^~m?aDi{kRu>;55$7dwob_91GqsFQ4CM)}22??^kSNoP{vIHEJmnB)B#=MtY zviyRQ3t@#Ayx!Y4_HSq9kHv9FAm3G++_lzYK zW-eD$c;)AP5`BDfNu8=a%|(azJ5rR+{j%D0u3g9$LH@|^itcfOE7xE5<$fAbIbxKV z!ZY-Uj)vKH!8ug$$#?Vby?TT14I523R9fLB@kH~x&e2t8s zpXQZNx#h+hXvmAlp!oV;^|9P)=in*j`Bf2FVIHG6dVLrpcI!LI+frXlBf3zm8Ji~z zW`~OG6V}PTM6ES^Od+a}7s#G#NPaxAmbYMQ^~@P(tZ?6ha2}7|(A2qlN`GmvF#QS< z$5Kbw{Dxr*UHC;33nT+>^{}1f$6?K=$B!k*$RJ#6zTtJj*Z#MXH9fp`A0JUDLiT8O zkW?I^{54~-1G)}opG8C58MNK~!~Z!b(9!=qij~Wr!F|r(-lzfPsqfJU66Isdh{+Wl z8<%9s9R8hKJgkpX=dbMi8@d?)tH*8x?)ebuEz|t1%`HO1gsP4_V!!{^=WyNpN6xd9 z&0SQ=gm1&38SS!ey(M!wZc4Vlo}t?w-SxyAA9+!x_sb^J3pSO#M@<>h%yREWUv;DA zoAu$z^W?z;MP`i_%EmD52CHdt5j$pHcnJ$%zG#F9Ds@GVZ1HdY)A1q@Zzv7k7Q>-| zHxsYx2mNj(-i@S6`LS`Z3_*(Qxz_vFD*y8H*6Q(wlODauxTjorVqdJlR~9SL^p7b03DXOU#icnJ>6FbfvMinki_&UH#m?&#%E zLF+ky7vb4(v;Z4Xq4k->KiK{MK--mpVwP~Y|BK&8YUr?22mF749_V!U37Fpl*x`th z>CcsKZVrKrjGc+MGrQ>R(E3cunZV zyJGm;K$R#khHJ{hN+5@sb{jv>;ogiOXq5-$Df)DbVS##Vt+_P%vHPQyM`^Oc(JmaE zi5;c)Y@Si$&$nEbfSz;aDRw+#DM-YI{(Cr}*>mkR@iBz`o%&X_>F)>ce98B9;s=92 z%qL@X>-<8_m;CSxuy`&9ox?kPn{f54 zG1w#df|_&BOHf#B=1Lq-oU%SaJR}(x^OO>;BeOkFt16lri`37N@yel9QvMw)hSUECQZj849_T%JFTnn~cCAYSKk;9iu;cMbzfHwQQejTisQwx4+G2Z# zqT{3P98y%)w1d6bsEb{avqIN#H$7Y;aqcL6$Ub>%foYj7mOz7LMAW3?Pj~}`2>xZI znGR`2w|E6XhR3xsxNWJXJv~=|tc@--%^-$>?LW|Ex$c~_K-H`{T`E!sd1DPghIsJ} zm>wbkiL1o@IgbM8y+WVCqzC_jN>hdQ8Vk;)RH~DE0=(dEmp`)kw%*3b0ZpLx{~nlv zR^sd+rU-%y_9C6d4*@1LIyK|GI9`DUslm^IKqu&RREV% zx!*+Q=?twBPj-4 zvz}0&5X>9su{okZcciD15AoS0uX{01*NAMi!7E6P{#4F*ZH9KeOH(B1D}{`s%kO^H z1CGC%b+pa7u68;N zE7#tA!SHpwPD$JZtJI`D>H=WdDv}3}qYf+?PRBA()=1&Se^S2J#u;y?xO(9MjG>+X zk_5$a^tC*~+B4fZB$MVfgqGqE4JVOfb+;OU_?V|<0Pt2OSPb(~o9qx=x857zB4vgd zxD{|{(`8aH#qmw#L-@ZpIRl#FY zS!;msO55e29p81@JdX~nZMI@u2p+X0Zgp@y5$`Y{c`#hl*tMzd!dvuZ8cB|)n1 zA(|#r6AJ#Fe=57VuVsdtM@r((Hx-Z$yE z7bxkQD)=z|>pgYYiqYoy5s;f+%)KF??|jf0wIMVBJicSr&U}9oS$|F7$Gc>C z9lIF9gi4jbQp>%UD+}s2M$X<)!T0V%(05qp({&s%hkXIW46S-PFcycZdx1&Vies_w z214;T7L4ivFe5ZP9n7EC9jL@)o5u^}elzvE6|-1$UG=0Pcwze_^>4ZAXXk)rE7btu z!A%2J^9H4|h!SaQ}6@^gkH%^Nf zYjhC?lHopLFId1>21n1uE*8aV9&GdxnlEx>R=-Z!~VCok? z1Oz2#$kYElSEoSQE?>R=u;RmUTJ5QLsQ^|P%n*`mgkO-Ij&JOR2h(B=X0cp|RVze$ zuqa9^&KJ?OJdGglr*tVhgict!K#PU6{cPkjpqWy=POcGN9 z0!SejHe>d<=kaQcCcFdRYw?rn;yi#>^Gj?#ZX6h%4s<2TOKpq;dQQDm(j^!G@@A`F zKo_Uc$=|bARW<{gVoSxrkA=)m$jy_PU8^&iHfO#*Q1T9>xod6LyA=zbZH+ogLMd&6 z6Xhv4vpb%FsR9*dr%VDh^Ot_t(lHhtr+SfoGE;7Cjy-n36WVs$>{$yxf5fp_VL&$9r88mCq%+Ai%K`f0 zZK*MfJQe;%#_)T;!xOlFfxx#iTTwPcuMCCZahW^EKq-U;AN-d~DaQ3+&1|@`f1aXy z^GCZOC_`CV=0wULj;Tbz=pf|XRumFYLWt8yzopXY`WJ5@Du|cHTm$)UjMl_HI%TzJ zu&Gqsj!)k^(jdn6_Na2mz}LJap-49;xazt@NAcB~1zkpE-ZK4MfgZWeR7J)7B~)89 zDW=_iGwGi8U0Nk1^(BxA$OFTGqQ@Bt3)Q8y<;}TJCjwtaTmebzP~T&5_ZKZ|VypxrokG6o8xwwWCEECS4?_ z_O3G668Uzl9$?>~sIAED?&_g#Fme?X3F2hHdAbZYs`Sv?P}qs_GDV~%NpJom(H|f_ zXE(Tk58SG_zVdQCiFR=n~BB>8{Wc-$3ocXqgGn&B)j?9Vp=T%Z$^d zSX1J=Zj$v!6ZGN}owI(`*DmWO$?nHIWNL>D5ibwN=4+Scr+rsWJ(|;WEyuDa-Sz;V zMUdt#Kkg5V3Sbmh(_?^y6Hp{i4N>dwe1h5wmp33xmjK60%JK|+4|JocRo^Vi?u(yX z9dH_}W)_ypAj;r;Uq#5b*%h-+h!YE>n6GS?LRD|B$8<75@~*TjRF{E|?C$6PMeeU1 zVh&;p*@>^MJtpw%`fN{gQv{G76j5rur$njvAN-R3FMiA9sf(3Ir68g(`Br^m-W+vm@ zi3$y4}ne@>}-Yfr~H;n~_W^aEFaW}N; z(X3V^$0bPV>m{W_%yvAwdp0A91z^R3X))m=7+ z?PO^YbSZI}anv0LoY~dTHE|3EQ9Z5sDr1T+w$RLbojRSjB}D(656KrppaUg$l}2?C z-<}1QB&?>yeWd~pROS0+)7TP~&1*v6q$()!9SLC82$KAsCye@;RZcJsQ?KVAXiPmD zSwF8H_k*ACu*i5|4-efI-<Jv?2P!by7*FUF1gsqMNr7)$!7=i$9E@G81osgJ zThr3j5_OpBU(P?5R-H{(2Y&#nhNwmmH|Q{Vj2Hg~gyN(caXN7>RacWWCS8i!Z7R#(9l{~aR>aqU#l0}!C z_<+u5-q(@+b=wyxn^N^$%UJlOb+4&!6nj^r6-NE@t4BuzW;#u34C8vO9dZLiDv@)8 z0(@4JLdTY?A@K+3v#&v&PB@!+gvH&@eUj&X;%jF3ysb9wujTI!uDU{l*)y?fKP=bp zstmt1E>s<784%=2kAi}~K@KN<>+nX3Bl2zA^dDcYeDs!dz9KF|JQ6 zy{Ql46CviezkrcNwoYMF!JK!e>la`jXM$de-A- zGHoVdK@-bwijN)hn@Ta2!FcOfZHzh!+HJ|*g7HH+_rAlZA)=z%#oSx%W9kjVK6g&L zReaABut_0W3;a>pV*CD$bvFLIy!EXV?r$CBWHYEF9O@)Q1QFY`j}ZdyEMKPkg4t2K zxmzd9|7uA|0xX2|o5Gj^23wQ+os^?_7*?m+1Gems4)ZZW2)9J6&`)eIM$DyT0rCS` z|4&{UA-5`LSrfX=&FflO@cS#AT@cSa58mMkrm_Ws9Lq_OtvuaH_?Q$8a=e3g&RHk@ z;%Xg+IFwkrf|DL835 z9SrVocHGJ}Cs#fvAu)JO+;vUuO87+GNRUfS4o zMm0=cx=~|gFz8l2!Rm5>^@w--fzMzU9j`zC1&i{brNB#LxgSYLncxJ@hKf3nXsy+vO{7wEU}@41>J`q%JW8=^aI zU4zGA)ZP{nijQG2rr9jU|3=E8z5LLcM?p;V_|wy|SSThL;bLu(sykh8&n2;J*YrRl zBz9d;BoP+X5x8S}YP|)Es<5B0cO!%h9+`@?w$96oR0{lUoJ{?`T0ro+uX=@SoxKkK z%5rPKl6Sgczi6(Ww;|z~y2(YQ`GJ(FWcAPOlvf)~`xg~S6u8OxJX+LAIN-jDbba59 zVt1YMmYlQiYzleEoiy@sTblPHj}LSwe=8Bnfu*~340OkMc%fPB&c=HJ)he(dJcK2Y`b3UhA3usVwO+GmMpB)G7#x4E+_)^rq`1fjWx3({3x_o+dKJa>k5`R&Bq^H8`1CKNHgID)ua@3*2c=_@ij%tFUhnLGG@*)L6N z@DnI<*m3rI(QeD|ZEKfQnSmt7AX|wcFbKmZ`l`$Vv)9u&Asp>!TH{yG!_Y$<&uLN8 zLfmBvx|2LT>4ipuX>c-FF^p>+qZD%T=pi6a$yP5d)x1CSnX17dObH! z>c*;@avbT9%fVNZYsN`YI1o%5ywpijhjQyvfcArl#DlC5w3!GJ2YEik9fygmw3P4A zry9TIBW&_$a8&RrlpKtwc$Fmrk@Z01B2HrH^&|$k6X8ZtXGR{(A4MbYFg4WbCyll}7w__}aI7qxJX9 zrkUrTk5RYC5KV`wK6u|OmjwD4Rv{ZEf>dU`-jHd65E*v&NYR<><$ct#)Ix8<0K$*n z@DBXxXBnRV-ylg4f7 zaO1o5QlJ(bNYIo}Ip1v7&c6Dh6EU6P1JYdyo$E>lFS2Aponc{|Irs?A!bBimC2{vj zg+s&n)4QrAGvWo{)9X9dicH--(3HNj7uO{yga2{{CkVN<0GmG!QIMGbb}&p3VgyS`R3 zwQ#~jUw>^k?l!)Pe16P}|4i;OcB5$JorM;h^7}j+n#NsevFKK-uJ8}q{yVlX@tI`e zA31AIdgrg6^zq+{{W7E)*DMALp5TY%Mu5n~h+G>d<^IFhc$=A}n%Fyyv?pLt@21K0;fi|4 zjpLTtr^-PhG9Au_1KWhmG)P5t)W`=utu2dtanwg{C316AvpC=j{HaYTbhJ^*% zC13lbw~cprgR%MVBUQf(8r9FXGPZ0~9$BFJ6ve-;t{r2}rVQOl&Qilz^EqNM&_klU zb_2|J%18!FTx5NGbs_#+g~-Wz?5Z}k;Of@Ggpjy<&>e4MF2u^- zNT+p~o;k-_LbLt1Cm!qU`@a$Q+S`3W1|NT?%c)yWXMqxq-&Eb(ng@(Dnc_VQyB6&i z`(`{oD}Hj{fc7a(opfpA9pv?~nmFG1%qU`1Pc0p;M=VgaOtH)#z^#KDMrx%fc=h?a zzM5VdF|5)kK&01G1&?=7zCVAv}cE!^>fF_ij!(V{_O_iqL#*{@!Y`&tZ6kRhqB)F zqa_flUOLZ1pHsiOL#dXeKU!_k3PBEd6PEiiz8`{0|3&s2cL$Fa@cvCro)`+klojek z9vq*TcTKw-*#hR#h-DE~Ia2?*XU<~WomY(0{I!%(&4Vvs$9K<^Yb>0kmWr^a-_!49 z1!s2&n^OrtxXQ=Z)M#0uU&43uF+)DEx-;e}MZSA8KR6h`HN|!-(9uJ&_A~tR^%m*V zxDTbv4)0=+{oLq(-(L!4XS-_?0JcLDU&-(Uc7U3#@UGPE_S)ayL{VFo)QV8AnT@@b7*v?#YC*i`m55z(4pE6x;9 z&Raj*G^q@|8`ke)%c90c9pDHSmHnKLq7l(A8%887lh{KIqro~5?Bv{$oq8El+(asP4!t8mfL`MIY zSPh1{{QG&$da~k!_Eze(6>%zJd8L)4g`$JxrdA0?v-1yw+YpG5TVGq8wAHy3= zxFSF0)Ub$*5PV`82YAtQaL4E_M2)BhGI-5O5ty{f&l3)%0y zJx+g6>5b4R56R~j;;OSQp^_dA(m6$KWptayaL5&(2Y(T_+PpCu&f|ONR_WwXwmr<> z1PYxv@v``j3v-aSo8CZ@GNVrb2ck{&#B)&;#ThzXg(^&fZ=qCOu%ToYm);981=p+ZkzuHDhw*Y zLqvyvsd;oqzfz>(fv%(aW;U*Gj8;BAF1S{KRe(djAcFuBrC20{nCMap)obyKM z3xDRatV7zm{0G`hY!~3t%WN@)_pVa`)G=}*Ot${%eC!d>*yBH<-=2aS{G(m(m|p7U zDxcPvD(x^!^A3#W%l%Mny1%R1WtcYTscM!el7$FngH&72%Bxo~*!XQT=B|D@+T-Uk z8%g_m6CW?aTH&1V@YnFYsIRpkJWiBh(cf=vSsi1S4ZIrRyF2O|XbEpu0fq;n3C&x<(LX%sayG}EH`_&)hqwkO*YiT~i=)G8wVG(;Bf`M(i62dOo2!fuZFi?V}-!wFoP1QBVIwebe) zTAD$v6@Ha$R_?f)mZpI~7+}D!R*s>a_qgAph|LX`5u|Jk zSqGJ_HLNIyzN+}$l+_f|(tBnUdzJw1wR}2XCBcCF9KwImwWi7ANhE_UpAA&}_ti}G zxmk{%*@Gc-Qby3;v1r}j7HKNV@wpD6jTZPob)?M&tNi4Dpo>=7^SB*8KTmQUG5hnX z!tM+`6U=n4l;p|IiWw%oXCswi0T=~-d4eUuR|cCwdtMZ1K$la|v5^uz85UC#v`f-T z4yVUo7jIH3pp4hdg6B!5H*oZ&=yLEfj76(7aCoQTw5>+o)p|2QI0Y)|ydy8U#a>8o z@Q@x6!s-(5+)Rac82)5Noi0z|7l90D0zYl!Gf!%w)1T%SV(|cSw~TO1 z;gMhY6Dcn^QMEs)(dUmewoRYZCon&_-CfP zpe0bl{*) zcvF5-$&793EzAE+)c~ja5yaaU841JrW8VsWEmL8QtXfcGH(L>20{LttuZ2i_vdtdK zQV;AD)u)`u`(80ukTcE_U&=IwZ_Q!v$UGZTQ0?*~Pc43! zL*N@`#ddL+=dvs#<1trCP#*mh9+fi9pstj4il&Qc0o{ZeXU&^A)VCyiJknUvS0GV= z?t|B(&DXXjT^*5!uea~wAFY2Px-|9VZ5C zAHi_!`9+UPxYehY2+Rp#X@>p>vaplbhPh2IJA>YMB%#T~*Q6F2Y#D}M?&JOgiQ_ra z!v(*oYRxd?c2-4yAtHovo>iHd|yK6|$H6DzRq%FLzlkK^sw zM%s6G*Ea|%wcLbBk3;8tmilgikQbk`0 zmb4`HFHyb`c^ytRvbS|AI(TMUm?VHUTU&E(%3O~eP>uCXI9a*AMFY;UE=TRf67;vJ zcCW4KFeTE9RYkY^5^&%v$dgD{@Er&yXzf(F%SGH-YlRmVi+w(H*rMISuMAd$R1YZ1 zqqLK}lj3l~sL_mA+%rgq5zKhL!MRZ4xNPc8PI1BGd~L26k!T%swEiHKqK3v6j2Uu> zfX7IjfU!pNRqZAy>w&x{&TZ?=D~H_170EF+jScZRYNXaA_XOoDj3m)w6=xdaYaTo) z;89>|T|ypJ6j}Uh+RXa^JLWWNYv}s+vW?G5ZVXd>T8u~A^#h--9~{-{nuN{;tJS5( z2z@G4LR}Y)q!Rr0s*|{Rcnii_VVYb{Tb1HlrI2DM@J7eC8>kGsd_vgR7;iT6JinPh$mzCO)HH%+`h$1pu&Sk(xD82 z;LQ`V1SYh`U7om$Id|x-(t)8y<1VoHRl)r8(;!yoD}rNA`~d^oH}5>kn^q{a0{CDb zR8T@&>(Q4&4}sp{rK^Zbr6}m*%9B8mQb2E)1A+(9>l-Iw?IhNW*?1m-$4#_LIn{og zmF1uG_TI*uf0FBx1ZKxpi-j*RawVfE*rs4X1*Q#cI~Sd**FL5 z$rG=0Sh)_D`*bPN$W%H@FCx$kJepPAc=s~UB@Cs5I*rqqL!toKSvg`E#<1eNWLMxJ z)JGnfBLD7riNn5iOQj%tZDTB--R+CU3&E%zyVY$l<9{IA^%z+hRMVi)V%;WBM1ulU zZBmdEScSIPjS-3zxM@W)75?c%OS*LXo zET;kJa12k?`e9dHHB$Zl<$529Hl->Ya5j;8Yp5zMS<=sZxIGgn+|fmK6X02igbhd- zGpA2_TkzUZEm+Jg+*+~3NL+LtZF$>e9c48YPFC|29(X#zGVl0;$MfVdo2O#%rK>ML zFy24cFiqWz=6M`l)86Ei8o)%?wy3C^90=|BM!J5D=sdkZm1aL%Xu8e_Z7}+FSJvgc zg{Y3eF{0p!tj9`=)34{(tnjhmEH7(>_HtAIgveldSt2W#Xi+xO;L|IQdNlxDVT&7s zHt_?`j=e9{3rCo^ERq~?Exw(>}TtLAgdo_AD>boG^wucyH;c_ zalgH_7P*Ry_mjN%fGi|Ui%2k-{-vl*ZyYN@i z;fH3hrRL0sX1L?5GIqVai1kl&{SQxj4t?*R!m~9wXq?|1k9zq-a+Yc0dZ+v5W(N0AJEoZ`*qCI4E?d*BI;dXrW0PYQWYN=tCaimKj|wia_9TwmzDjXvcy#-)0^BY z`8t1+T-DvFu`%?`+1a02x}&)!BVBD5!dYTs)&8;#Qg`Wlt!9Q%4rI)q`nPG7{Wk2S z(crHY^%1o6(I<@CUjLpwmMbK+ujZj<9_49q3NTPj>+be6Y3`PhNEMHxy-N<;eh-py znh8i{kB}K=Ir#FMBCuD6$epNzkVwK0oy38ZVhj6u?bE%JRD9o4>0?7jTFK0Ks#|y? z^H)?!Y!De!XkVY}G;P1#hBi7MkS|hy zoJIqYMz>8t7%b5FHPL}G)*-S7=xUAV?!UsHQUm|023{(*DL_?8n!L!QD&7GUGJA$x zdo?;=ny#fpTV17Oqsf0@Dc(w~HTeU(L5?0Z$pn;T26=gJpjIaFmCMiZooyec^1q+g zfj^@CTUV`uhFSluWXwF$ERg3^ytY0S!`F9wyxyLrA#SI*6OHq30qz_s-Q17aF;;y} zKHD_E<7sY~-vL2!Vgw~dYmNI_wOdrpGH2_wLMT?UH1J6|ercIo^E*PZ#D*)0>M(g3 zH-fpwtU$wqczrceIU09=Ynm93%^>1guF#8r_UE3APhAYc!RS!ts|s^dyZz#-B>1XX zH{(Y~hmkVbgJV4W`|jHNmIJ3RC<`IkeW-(w*MBOajq#hqJgkZt?L+Ht6Q2HzdtEo3 z{YI{EEH6>Jgo*F>X>d&OfiB+xBTZFF`O~|Va+}yca_=L?-xvl(LW--sH`-#%aI^$a zN|5|MesB02UH#LC=eHg=hMq#*IedOrV8GS4$`8Y26?ar-w-M&X)A z1U6#vr{^h#9X%7tfBK>1&0^WEam9t&JzT!Zc8+ zX!0R_{p&QHvr)#k;9=-yUFD9{^o4uV#P1Kx5E z(JtUDTqo)z!wO;AHlZX|4uI{3J9A@H7cHkm9Vm@5EGc%xJ^Ow8YPPZ{uci=_HTLw= zNxpsS+Ay1k$=d`bwEa><6$=~_O-_9RaCmaPo4rH5yx{yb95>8^h z-AXWKeX_LiSC-PKcPPn%vX00m(NXu>2iC+@CO%c7l6jiJri&2IE4Z3QERFu`<*zr@ zf9UUN$$kb9IiQ;)bRcFNT7k*#ySYD@Ojv_(E?*9kQkSB0{^0CypT+w;&(6?*tu=5! zU4H&3uc#DIHywXS783QjMLIGGGQEpKY(L?||B*(^d|92LWZi|~A?kC{(+gW4l>Lq3 ziS|xlRxek%`~7)nVoSQ=(=Mrflj0>>s=pe;b#=74*-v4P;TdS6-8hE|_1}Gb#jzMX z8Gm;l6lj3rfipJsr~9IkdWFKy4&MsfLm5^yDw^K=24%o1{q2u9ZgsF;cd?h?1d%{t zjKQgMKUJXdDY7`MaPX!+)v=RRvUas~<^HY6`S7i(WGX9x^{&ij30mgvtIZr?reFf1 zLsXOV{cw5UbCib7R?T@=nl~!=5A=6lcIm%4qgKVrQcLH@^~5%q2!z@9I5u6aVJ^5_ z*Bj7<0QVt6^EkH>QU)wgdlupwoF3HsXAdH~C|={~I``x})Aucf^4(Dqgf>u8j04Td z2b2LAHh;Uc&2dI^4B)QOo)p3@dzZJyBSq6FN71<(!AL6cCH+034s#PKXG;6%9Zo6CMPGc)UDbFyIi{l53>U8_W8 zc@5L{3!CXj>4#d*52g&Q>Mj4`^E-%bgFW=a1>nPM#yi@VV_JBX=fB`ZoN?@N3A%f6 z-=N>k!l!A5)}u1xL%wg09aS50C%0Tk^~pnfSt|PThiDJ3)=x}@Fh((}ya8w9XAwN{ z@1bM?N_E$y=H0Kdp-)m9S6kU zY)TZ|gASfuCVou41iy*seir+44Uf!8HvBu zSrH$2-r^Nbc^j8?KCaw(;>+m%9(=CPO6Qt4^73bXuMU-QB*bSPjCNNHwqzM~v%efC)G97= zd<`;x`7xfghP*?WvGLzHn+-(uk+FU3dY-cfDB%nDTX$8y?~z+?rAbKt1f;wkHO>m) z2oc!hkzO4h0I3Q5sAI6Owi$aqs_ne%AYZQ$#(HW@alkWjBW78w@GiR#p5QV#@9)V_(%Kh;gec3lQII~ zF;TwK>wJQn*ye;D!gbIUvw^nYr<@f^*mK>FDm}S1>#-|D-x6Z>^1hG1N&b+E5lQOS zfAL^>*Thr1^I2~nFPIai<$zb@I>V|;Zt2vP>2(g$H1%+ow%hQUE2}#{XNAgwuH*Dz zeWpdV|JInNyvuF6+Q~|t^j5?~lH|92Duo&bHYa_5EI1+svudiB8qA`@wRbjbp2%la zpq$Fxe=l1(pn1z%&k&L;#Lxzl)BT&DyStm->fTR(WPEn&qm95DqxP+q|0kN_!m2LB zGj%cgaZtEBLG_=XPi_2}yFc-Mg}h3M<4J(muhqNuVcQ+?bopUoYkK-a{Y$ygfc_+V z+W>nT{`ck*9p%y1nRL~eT8;DV3Its?brVMdx)aFGuVC>{mTd|S__=3~V1+7Wqa`Cy z+MlSOW4Uf6kA)SOVSO2WG#KAGWav)3QCzEy)`FwMa|jsSBVP!x|av9 z=pTj05``?gQSSw~(zHry{H8@(INeOhtk?I^jZ4%wt2>Q9lK&nE@MC+c3gxAyilvgu zM~WAX9fkK%MP(hM)1Xo5txAxWY=5`2KtKh=?`Ko`WXUuzM0rP`QYQ&`xC9tSjxuB$ zkcaye=3@N!7Kob1rQ;KEnN@9Ou{O8fyD;eeX6gDEWwF1D8`0-8jGLMb9SQYk2e-#n z?B)qdLrY`YC`zn29!vUrCVBs zdb4Rk{gSjq*EjgKlW5Z{JTa2=JKa1@L(u;DnRRk+3moB0k2E{5EVf3ixFBV!+2$RC z!FKNCzeKYB$qePcXN%_D8d-4qw9<{pkRg&M-73JP$-5fTko7#A$V;<-9XHm= zrRu>XNn{xrA}E0yx{P}Nu4$F1Q_$b&`Q}M9ltP>Ztk(ee`!8JxSEH@(Cl-oRq!8jQ zRN%3>^ZmYLcDtY_u_)ZozQC>m;}LspZ{*S!#9S!EhNV@)CJa5TYQ_1Y^|gi zLh!#XBF(SDfa?{RrzQ^~vJ%l@1P7QT^Zk?{g&wdG4}3J|^?HPM$quXX*^*N$`pj4oS@}7+$$;_m8MqZ)An0?a zTt>TOmt&Ay6k0I&(kaG4`HC=G{W#%~I+I%LO12xN`MqF^NYZ4J^PrFqKj-Z2#~Gr} zEpuA6a)lccm-yb+ZS3Gb9lN-9=;fAPUK%SG%hpr}iPI-ag?R!1HOs+aB;YBYeC zpte9N*4gb+>Fio*v7kDoA;?}2MOg6buyrxCAs1@YiXtp_`AA{*b3UbhEIK>{&lAK< zOs*>C!oU_jG2Qo7WPV!0g8Z+-&CDvVaQcyR9{I1bL{E=>y*AR&jwU)A!$j4MIGRRm^il*Y4J-@#9xY8bWx2%VNcKWvg=q6E9 z!gZ0;hBG|zQcH%k$qE2k%S{k2;Hf_ofxXd{^4>de^r=ns47!;nDV65O%O^=TmnS|X zsC@wtduv1zZ2kj59(5%c-7VQpJd?8c(`Hs(secZ?8X$bJ5g~)@&L>qLw$F^=*HY(6 zadzv0o=HROaf3lXa!dnRP77_{>IC!-7l;r}72wjb_Vq7$@GMxFJyr(WL3`9*z?Pl2 zyitR!BfVq4<~eYb31S2RMk6m*frR3MiL|Z+e(MN}s{c05`%(x??Z=E;0#h3i{jY?U z@K0ZzeV?qGQbBc+p%1IhIsJFF|3fMqng{*#wqzC<5&NI0?AJ%2-`)&DSEDxR*wuT`QuBCbA-3I z?+ylw!?;eM8GluDhw`Au#XwT0U8HRot~bNmvz#>V3}V$_H;fOf`4ST1ZF2 zxDL%P5OZq}xE+xkp!l5|yS$s-WN}t)bVIyLYI4_YJ>JX!r^`Kl!{hw_$={TtBg3V*LCpY?+;y{A&>rXD!>4;<>f&F*-fOg$!|4YZm3_g+*=p- zGt+T@bro6xI&JSil*tVac`2(p-$b9AmGr46@`kth>&u}1Ja5vq-0hS$IunK%{jMdx zAY5xN4q{j!g{4y^pQZEjrMpJWhkcO!!NABmT$af1Y&&ETAr+8A2vYHQr1o`QAs>@g zn}VzLyzR1c)dXxlsacfw&i;}M8kHG+ZZiIA*hP#!WW$!}55(-V7o)i8vLo5otn2_m z=;*TBx7FdFAL#|F#921ggeH{4u^3Ab8?%68t zi?C=+CX3##&2j>uhEzkflQwRR?zATYG4>>1pBx4&1LJY31JY^$~MrLWYEIrBx`%y zX4rRmZwx!Pxu&|$jdjMjRL0aEhF|)`w-|lm^|7A%)0XaDxX?4;^KR{Ys7&j)E%S9D~j1M7u)>m{en=@T(i)?oO^$IjD(-hq} z)ndN}<(Gw-u#V0Gy9Q0szxX|Rn4RaK_RGN}@o9qQYCFIUSW`*QTY!7u`|TX>qv&o5 z)j=6PnXsAc)h;T8`ADbe=4D~N9nFGrtV>)aicW6YHB6x$_pFTu+tQEMo<7(|Zv6+^ z=83=X`46NYFQS1T+J)@zs>B#JvbZd3A@t2Id_R%J?wF#CG`P&#c0tv@-?GeyBz!x z5EPK-{h>7ATSkx)|9+G)uk#-$<#Hd(xA)~ugz|AgpWwxH;&*y^wE3ObT8inA% zH=c~{GwzA9D0AfxF*C<2WZ{}s<>@dpLl(B*f5!=)Tm#ZMf4MP=-?6(S8r7?N_)`KO zj;eE+?Zn*rCZac6=w@#*Oy}ygl_@^5tdjl1k)ubyM?KqkiJHD=*e4qF#o#KEX@?|? zqbyw$Wpx4zv^Py^EfU;TwX6<%;=h||!R**H`Tni2Kb1VMD*CFYhMSK*|8eLk-nYch z@vZ^lrMhUHQ?{>nD)}U_8c7LH;xQej)Q`ohHT3Q_Mh|Yzx3j@9N_>c@hqN2e`m0IyzZ1zs**KxR#0;wNfV@La_HMzeDXjjQg7Y43J;l3_85(HhPcvj88o) z#TJHU>R}HG^X&DXe;J%SUzrwe-)~>p4;jL07azs&R(^FGZw8fIcnYKrIaS|_nXO3U{*XJ>I8i^CtTX7(AyLtp3Q=Tsba!4uySJb&xddtFEJ|5u z4^!ro`JF*{GqpCE`?Wf-wEgxEm&&}h8@o?R9NB8v6T<4^2%8)bq7yAt3GfwU=rAvB zpCj$Xnscu&2m2}r4vo(k{sNl{#Kb%VpKgh5?XT8NRsjHN1k2#{WgMe%^EmmZ(Z7nL z6zIw4*dNxyK#&_OcOVzP}grs_|8bQM(=Dr~~ zVO-LtEN5YOecq^_?)T2a;jj5sIJ*V7KFUC>`wIVF1chMRd*=E(<0G>!o3tI3bg7v7?tD{zNbP2~TUv@Rdr-^k ze~Id&kDgczEm7lPale;qH$&7$+!?!teMeVbkXpEcc4 zyn{7u!%>(S=9-x?n7b`&TVaTM(x+<1ZnBn zj(DH(Yv23*E74B1LeoG)J_j*r4L6)ZaPCy?$};5qaprP~DW~u~X4_v9)Ac)>^ZO6v z*LD{>+W$}(aTgZd+s?rlM{q8QRrUTNamcac=so?SC3tfGj!~_${2*HK8&o57rKUM{ONRJ;}v}S>+T8zD&IBliuTR#wSgG-mcEXpsl;}hh|6|$x5JYSjVL9w)v!THBF zx$3)gVlLULI2#O;y1DXuQjP0^(&);2)cT!busc0#hsIm%1g7OqYck3BIiEgRs(l4a zI~hK+YX(7&{)rv=hP%$@!m^*ret*t%RfXb-OQIr!Y@Bl@Q$#YYN8fn^{&>+M{YW+V@mncLX6VLLm-#eRo z%vFNOTkz^YT53Y|s;th#GiAF^Fgw<)%A;7p?Fb!6bi=<~aSJu8@6?G{x`UTqEobjV zG81%Hb!hOT8s-XK!meZTPkhgIwZzZ0Go8D-R8d1;Qhqf+nqAtZM^M~toP=xm^wrTw z6jO^iE_kpzqoJyKQsOX#oy*^0nMq^BU~bHn2GRj#flFa^ zy5^w~DQ0%LY*>bRmjb80!;kDfeyw?s_J%{tucay;8Y3$R!G#wo|8%Zp7Iz+s? zSITSc1V2e%-hN#Y@P~@0$d+7z1Bnx;MsS(oJEa|^%b6mNL2rX3^kYAuYwj87UtAlS zVf{2m)f~(8n>79(i2Mvt;a}G5@0ha^V;p6_kcLB53gyHQ%iZ9BQv4)d+T+t-j&XA<(}+N?WI=kV;Qlq2MxbQPb*PF8E3!#7o*xqxt9R8k@r4~shIwa z%Jg*S)_mjmW*Gk~xEo9e=d`Yg1}B z)CZ^%1 zZYr*2lnocgpN41sq3Rn`_4j>yeKT5KvW#QzAG2eXrr*5`0Dlv;9Qb*XFGAHP@5kH) zPIxGY|BWhbR4w4NxAzv6B=;;=r}Z`ZY0*@swpIu_DICt**$!|ohfPBnhXaZ_*G)~# zmQjl1VoxuWcddN?ylo}Lo|#9NI#x`c|oce)xp z*^HtrtnQl|wE#kTT932M@oTfT~W9QMtw5lV8B9^=k4jCyASo0V*0*%IjgM2XHWwsS61_5!1LXc_oxs?*Z% zCU-z&6kBL=S4~b!i|$Q&wQ9f1NWRGCy(m{2{>b zSCEvB>^$e8!9OvBymqWe`mn+E-}JCpkLbh(5SYw!Z;Z*galX zioF)x6V$h=UamrwXTmP$YFi}Uh8r5}RoxLN1qNoCi;2Dm?<)nYlu%z} z_|8?D7(AJGl+0=SZUxF_G-DdQt+KLZ{fuaSS-r|)kUc5&GuUN4^E@|CiuVH%d8S%? zu|R*jakqaw3*psdi$W3M$s}6K`>ISW;qo|0h$Qs-{$z_*k=c%HYUHP3=#^%V zJaE+K8)eOv`7{_K+)u@Wp}NOMbZ%z1*x&77gU>03*89?l`i)YjxBcBsQ*7Hx6}Dd{|IL%PDP7&tez$EZ&PM7?$PpDi_ux$4VvmW*oY#!d%=mZ$f7#1<1yd0 zG>8d7x}6!$M9k%!AtHmzMQ(xteXLzwnRNr`O<7-Kyfyo>;9h0e$y>=_N57QTe7yJE zOmEZYoR`l(Tt--nsdOscaZl*{wc6|!?t%(!=dN8}Y42{7wu$)yRsfW1@S~RW9I)>dWrW|=P^KO&?R`qjSc&6+6KqjX`9m( zF#m4p6uorce{|sV90uUUfaA_jq^?C=TQT#KVm_XzZ5!r0EEPTSG_#%e;~dG;ql0Q7(+nMA10Gj5iZhcRp89tiXVAXT?@Da7T^6B zddvz;vHu(%k{`t5AO02~R2dcwi#0kP9^q)I@-9A!%7Hj^ugQ2G}5jW0(Nt z#-=jp9Es6~2~^FKl$7jGSg|UqMT9MKC7wW}Y(s4A8x(x{1Jwhn474CCk00U_=mL@r zB^tU?-S$ugw`&Z=)`OLH9-X{0dLh$4^pLy^8y7(m#JPpGaAf2^0j6q?|;{URAB5$_H*sWIHfTgaecDxjAUG0ZpiY(XsA{7GoS(4&icZMs9k%*4 zfcxh>J?dOyzFlp-VxlFT`cQ4GCRy-UfG;1hj-(rw}rFweRu1t!|2&AAO47?BGWZAAp1k6 z1ObQ+|8MJ!pPRuj#9ql0?v1yY0q5@ZqV;QQc4XJv)kU*oHN5ua%ltpm-tCJU^Q1HY z3RzhM2b!s`cZ z61CR*>|v^EUwq}J74n0iV#5e#f)TF02Nh|}M)1N_@Y42K)6}Bo+*Z*u5fTmGGYzZ% zRH{@4aG_({@`~NSIk)59b=-d*`u6jV67;zuIbs-f4RIUU32p~=^yaLsupii$dD^&~ zGooSK{q!C$cR8oaDmvDktAu*JbI#;Y=6;(ju%prs`ODG+sSfXq4?{8_?Y}v9 zqiPXBs}CiiT!fG9)54;KIIkx2g_k~#KY4fJCZ26I8wkWU-$WDH5W{WP@x{Q8vw|N3 zf(X=D_D-Ve*%zSZ{y7VdeU-f*brbJ#Ij@ZMZJBrTcXYRR;i*%npzQTLD`q6X7b7SO<9TfRqi&RE@XbYdC*L$NwISF)enhb1J;^e{A}E=7CrWmbYpnMQb$Wat-YEcX}=m+7=tVtTkrK_ zBrtUwO%mQ>>q#^-70ykLW0EK~y!L;fUfI6bf*zN+B(LIGe71A+yVzsVWWFXB`Pekc z^BDs7P!Q1M{#sy>_(M@-SD>-!3tynu>9!IC)nrY$ReI(fqK}PBssvoe+={F)@#Q}7 z{c3FA=OTP_C!5(VpYcTt)myRbsPBC|9q}90|9EqYMx2v@g|!Hm!TV!Jfl!O?54bdz zJrrow^*cU8gk97ksU1FUnZYL%Yl>gQjj4cyO18*ODy!R9R{kYR#Lqr3OjdIdJHZ>HKcej5!C z6@C7JLjc>S!9V+iJkF;Js%Cz##;#Gz?5XEmZ}twYT05{oY5ek! z;_-Ad|Jm(0ajI9SK>|*RmTbs12NP@yK8bkp_R+QPHNlp3m8*_#el>lOdiH_mjB{Hf z!nELX-;`)b^V7`&hijV&6z@Rar#5b!CpF$w2xj?wCHLtzs)_jI2wJX#a6REJH7|_` z$lj)P$i7>n_u}sTkFUKGU zP0Ryv**Bm|z0%sICz^u8?B-0vc@|Hlz4fF~JSFWOXJey}I&2tZNK`qr%l6SdY@MYhf_Ro)N>m7FkWlDFsmuZ*h@=}dxozJefVf#w$1SUU-a+*jc zAE_1cQBeVV>BJDc)|JKWtH%|;;CEK> zqhtlNb=)E6_nYVn+WB0CC%Q`{VlBSuU`Fyu2?aZTkVBM){dSRKKgmR$cx8QMf6v3} zZdKbKw-4_UPj)ii7a70C_D7yv(CIE-zunL8!C*M~`S+=wf`Gc`%l?LmnpY&WA_ZcM zMcxIww)#H72gAs=E&CP4Fw+GV`C#qnlTgL9)l{r-pfhX-gSvmr^M%QfA6Rqamob}r zjo72BHPya&CKzJEswy!=6Tl73 zSW_uV!^Gz?;rppL@;(S-iw_1#PfY4W)w+Eqh{H8kxku@TBkql(-+Yfb|EL1l^C@F9 zStzCQHeSTV?^|CzSG{_^!=)07;f0uB!#i}s6V10!H{guEWtKYtz>|hh?QF%L=!VBn z9^61MsDEfQd z<{_)R=TR+&{+^h_Yuo3>`@n605S^~d?`Uy`UCuP*r|#zmb*gYu_%yJU1N3;Pd>pR&%g+P>GgN-?zjO-4=*IxVTZl`v${wBN7fTXc{j(HxV` z|2L3YLE+K*dP#7IXPDgxmDS@{)8cJ0w)$>KJS@aLsN!TvI7sN6F%Au29F+l$BvF)y~-bFWe8N; zDul;W1@0#$=Zq5&o#V?tl)}3_Ki4LXE9CS%tM&VzUmBbGG}bdEiu(?`n|)W*Kk}t& zbv-dAA3YrK=HuINZFSyuo2_{EABb7;vEx5G*Y@}Sfo|&5W?h7F$BJx1!jm&DQqJXV zD*TMcQB}r-6vhbT$;259=YedkofwCF$6rULx_=!ik-`p2vRE=@N40 z7*iSV=8|)f9l%3ezT5(0DOxv?H+MInsqc$Fg2*9#QzwwUFHwq*XXl5HRi)yTM+MI> zNM0|%1FNWDMMa!jjHHXd>cppw8gqwy@2Ntzsy>e$17-#t-f(x5*eemZdizMpCty$G zT1X04Z4B^QcW3R=ct=QO^z|a|tcfX>nbH}n9rKeE3r^VOdCpDFHWj1pE>TjGPmBxvn zT6tOGjofcucHyC*HHVY_wucgm&j9WtUc!8kW34|^NSRZt#uvx23nw{L=^WQIWxydq$VW?9)o_9_j-|KBI#`|& zL-g-yS1b_Iw6n9SU+MzYtKyS7r+pX+hDv4$<#)A>*OK8qi&~d5J-zI`T-+T! z9p%ieO&0pb7ELw6olEacmi>$EX?rSbI77JmdUqdV+M;szfqM1i=L{?1 z{Gryn_C{nT|CqTaQ1$>WRRQQySmq|(c0jS8^72{Yg9>)7j3XsmX%;`!wmKQb$tX_o z2==^x-T9lb$(;2RwYRtirH09!-NV-x67;a+_@tHoUdSA!^)-Te%G6h9(yiJ|r9kEK z?T%u_faK2Lj|OopuEvNH5T0BUFNrg@#-&8B(35v$Y~-(wGQnJzdoM-4*l0c}+O8KX z8(Zp^kGXSXsBO78`S6kdiYJO0!9jS5*Q!(nu&~*5Q!U(Ol3)G4eXA?}xA44pUPDbY z+C0Ka?S4dZ2W;W^%QGBmu06(@9-!U!Sqb1Z0T+qUc#GFsd<3d0JhVjtOWxOnC};SR z{Ulsv(22{kKJ7v?dMg+0#r+@1_e?#N4^+P~+S?wE;#Ir_Gw+o&FO*kz=Xs_kq~konmyya5tE~bO)gp*Xba@V_Lp<#Ei*~#`?4j0^e^~+No!QfP zv>zLk(us@zVLW7JmBZQcs7>RGSLVw{`sCQE$g zqZ48`ZhrK1gu1?e&7!?KKGqTI{CW(o&8fc^k^AP3XAF(YCV|zz56W>m-%h=_4WVuk z#x%F8s7>$oy7;)be~e;%79Fu>OMjFI9}d~zNy@Taogm+A$LqG&-FP1Wyxg5=FCz@t zixk^&`>2toSlTmPV%4FE({#2dF*`YJrEHp=9btMvxiwRGQd#MxPI!w6)%xTZy?RKk znM>{YeOEfRXxrFj#GrH1vwu#`IL#4RTbHVsgb{tvZR}@#)>a9aiNK^s4Q?l|fGSvf zcUJlbO=L?n_DoCv0gaqDMMN7YDnNE_PVXZqQ z==Wj9pw5itoM7YXb)Sd9l7sPS*Qn>Ph4BDGUKa0$bJoVkibfJ>aWZk_vz@`$Q?=H? zKYk^*>ZxpwVMfqY*Wbmba-OGwciLZ~xog(_S+Zhqk1#X2u)$bMYhs<5YcbHn=g$ zK{OXCE|Eqx$nTk`kuB!Sx(&Tifn3S<3uq68KgZFy&2`G#U@Yu&;CGIn$zFfe$$YdJADb-Qc^e(uG~%+l?7#^a5$B4NBah zMuJ~*zK8`lJ4j6zd`X@z>%^;YI9lDi9t3fand_Vcu4d_HPobZE^XK;y0@B+PXG#e7 z$gdzhWn>(g30sI?3&wFf+Ane&7H0SSggv^6>nsYL6}NEP`-WU9BkKKbPVvITWrE+2 zJMpjkcdfpM<_75AssZ=-yBmg7z44s9G#F`a4~?HrtKx}kMK)`gKY3D&f0IjM*Xh!Y zW9(7jVA>^pO(w=}KPprYW$I6Px_{nLxt5BFqv}J2_MnmxcO5QVyNLqVkv17Rgy1&{ zEjdUW)_J|=KC${#fsS!bIH5`mCCb}yXj=1-zU841$4&p~=$i&)1O0`q2444HQh-go z*3fTx6Si39tgIfB1+dVQ&idX4#QYNRh!pEvQX}9c~`rz2@?a?SkPvQ2i$KlX~!D zW5ghsqQ*&F{u}&DL$3@QHN)&!dehAV1B3zSr{(<6;H{j#JWLRY>+cmql2fTCMbJNp z6xlzn-V|=VvWUk594niwiA;NW|AEw!V?221vH~BH{|wMKZqdC(V;75f{iKt(p`>S+ zkv+p_Xn~zJ26FVM1p3!N)5g!@3%9E{rN4e(x&KERjh(fe3kR}$k3hDdYfr5;LaW|* z6i#eEucCM?qdzJEOba(|lYOC@4!p5u)TiV6_54C(pZ9Xoy>CyMDykZ%+JRvFS&vB>zZqfucho(B{m;Bi!&eY?XY1|XSRYtR1{g5Y# z_fg4k*k;3_5(Kqlrgi;e461qnpB;SNCjruK4oXG9Y&nBsi0WKUb)#zdK zVe8ivW(PYON#nK4`nZasdam~^l-IC;3bLmz6i#{@XL!Pt7Uk-BOfGo|)$AqV=!xkdRws zyghyr$iH=-{KwU%zE$%zuGZgsUnl9eqo+XFx`?Ww4?{khoWfke4CWJ(V~*$bi3_cL zsPB$v(|kI#l8f^f<*x48PbL5sh`OEsYNJH=+0)vURI{R*)YocV(y0sfxEuy47Oz|C zUP9uB&o(qO!^jLTU5mMS4I@EKN3#u= z{_i&1UE2vd;KxpgEyz=6@>;FW7Zn+%H~A}8!;A^!nII|T=|X0 zOpLo?ex=hBCv`X8Y*ZE7zVuL;>Pv9#TGO?u9%CgVLHO}kp zqh|dmmBqWCBOIktsyM9#7O1%wYw(j9AB>V_!&;}@^qg&%X}dOVUo`^#QIB&b-T=va zk(VR6#fux<9C_dJ9s7$}8z3PNtS;@8b$o^sy^>P|5JAo{BtQ5|R=f}tZ zwxAI9#M%q7to{$~Jkc^s8X3hBlXG2Z5{i%7!!__v0RP|v)2Ul(clTW?lbQ zYsuKluE-g$Ch+E};y~n1=h4VYrVdU#dlo9F}!!5f{ zL1SJofq8>J<-z;UiCTxf zLoANl^v}DgwtHK$bc2#@(f<6EtR4a|c$^AAkA=g{S(fyJdmI z)h`W>3Jy%yad^d@-?!d=G=z_e32fzMO~vnJ)_1ZCiERc=8tZ$mYWnBcM9qR2*q@F- zN1U&@7`o&|eQOI+B@-ax%t5_+&Aw#)_d(jy>J3;$RdU{BSG=13tgf`* zIEk{ziR)m%;Km2U`O`FJsF_eR*>B`K-|3miNa?jw51sOl)m!XR#@+|j`*eSApI2(7 zTBRF#nXu5ccmJw@nm5L+?X73!#+i_#M$*9B*cBG+)tbENPzVP7mrpUV&(la=6wBRh z48_Jc;I^P_=ydpVjGAPlyp5fwLpE0x!+U%C=ME#+R_IbUC9N^~RDaqeUNHPaerAu! zt-AYkfav_A2H&_+uF!ICm0sTxx4%?{(P1=)z3<1I1tx4?vd+z2#LyizV|07EH@cZs zwI9k10k(Mvd3oEtLH9CPc<)WTb;q1vdGg2)Y)ad7<@L;1u($@}b(%@E^znCBVlFG90tGk;aAtZ__sPbcnojolD#%3{ zrX};;;!-gl`|_l2ZFF0=_Or@bBGpr#_g}LT10350I^HQgDB4y2{>RtHy9w^&!^B$C zB=^ou-*DXa8Jqf$zshTd!d;8~!^ri!3gR09)865aD|Itm)613pi}=NrH>fz`d8?GT zBd%=up=X`BK5B6SME&-O9 z;HePNXkpGXth#*EWOal8S?mvtkJqje&-%rGAnmj`X&Ja5kE9dcE)5paod!K3lKltz z^~cC4C*Q4*3U5+O$f#|RP$lq#dCpn_QC9%IB48WPRhXK?=FiGo{X@m6Nt7_Q=Og0% z&)?`ARR+GuT=pPN^9RKkFD_$sKdH4lYDt}~L@Lf)LGc24Cv+KJzl#Z}CzYY^y2Tzn z<-6^5l0&cgwjKg#KG0b6WKAF+`zVs~76TRH(VlaIZOrD+92(tf1R*{;rEB0BF z%oP);Bd5i7ttG&Pq>07u2ZV@Ny!}}*9?*8KQ{%5+X(C3K zYYwAG;;3*G`TBUp!b~cr?W^s*V)Xq#w|%I zzIe`AY-Q!JE<<1jd|^h^#%lpbybByZ8IaU~E12{@Y)Z#HfJk*}`{#sP=7gTH`;y|$ z+eFj*jjhfyT(@HHTDMr=i|6AB4A_CX>EMN?3rC^>ee0mc`W!Ba2sys8d`$!td;9h| zzLiu03y^DwEhUXX=p@}fFFnAQVi<41Hnqki@7L?Xs<-?;_l^ZWEcp7U=eW$q-}RK7 z_2?iHha%C+;2>u)_~no!B$ zgI10J9qtXMb0!4);y(~xKn!mw-SPcO2`)B9VzzMZ+E~LV;V4_=rRBf({7}{5yB898 z6}5RAjJ~wK;vqc8KgO8?3M&3SvJWtuLVKVbh|V@zz@C2-1`t$?G7f{$nZpnJ-}8^> zB)`Im9jgwl@U|y|0`6TokQSR%J6oT3FIO*j@xJr7p0{7K?=F(G4jNx@6b!&5c_Q!i zc#kjF9VI9YyD0Ld@&4YAv43!UMWV)C*#Jt~OSn34df1ZyVqJy2<#$cD?*!;1Tx<1^ zVJn+;Y_EI{BLwvFiun8QD!oWZ_|(0@PY8YMPh19Czg+O_SN=NXqzNl1G40b~DEI;K z8$mmp2Adk!Cg705)^w1}W7pCg?P6KJnj&bpFl+FJaxJc){W{c1=f*r~9ECN7L@To3 z-(IQXZC2tkSD`f9NrSj%ZJbbwnNR5IPb{&x4IOs+AjnD!D@)<{MeVg`FDL*|^e7^+ zy~`0KF=Xc(MfPowI4r`y4Y9e1EcFlE)FDkYZ9)tb={-KlQWy~9njgz z{%lFy=Dsk-ni(-^a|Zi^;C5oy!Z1RdjpkCra*4&FcUxLaY{x{vm$O#f$+03YB85km z>w*#3_qfVn=nc5(+VUKE$NyAyM`SFD1#rJSgug7@k!?e-#z$VJwC3%YxwIw@@j3MF zVSAQ7{Z!}r#Upwr=xr2;7zQjp0<#;5#uIn^8t?0NrHYtsr-ZxY!sL3!@TuK(W;0P< zv<;uGY7@zY62xaKhsJtq9!wf%1HUUWvXxkdwEz2Qpmtd61F-ax3ZZ86f? zinz+3NVm~hkBKu%oOLIJ4ge_M#eXY>>tlIGdj!Af^rT$tJW+{rmh+F+v^~yK)M)Mc zN*^qhbj+*~2-kTuO8stnUE4!tZ%X=!X5za(g^PXdj1ALh-i4&BX-{n|DWLk{H7xUY z4C9|8r(aRVv6-$?F$r05f{II9Ln?lZ{j80*wr*CK)AxZc+G#*`wFypAhpy#3>No4^yk4-wyF9-lS#~v?xt4J%OhwP2_s}F8Vd-Uh*2qid8 zM^;Z5x9)o6=9kZ0L5_!;CpSF46oi-G;c^IAT~&0G=;xI>KZ^I_RnDPrSk@n}XzLER zhaL?>U#DL;ubY|#l4hy9(m?J_@Ak<*CUg+1-sMvX!D#1l@zcXkv3h!Q_sbnQV}>Q* zV#%tPnW0dG2&yNYV&bjQ#Bt#+rX9o7dRJ5M7lbG!z#ilYNSED#D(hQoA;Z@7*=x@l zQLi4GE^jquIVGi~5^0S?;bWSv$o1q^KgNtFGq?X-PrKbPbKebZ-pd$Om)4tHLxIL| zC^uAlYsTgZQ7!Sx4BuRuwS1A`-S!|_sa{CvKv`5V@W7qlLAJUIlT>fmStM!h@IjCB zR5+Q;isIQQZk1y``RRyJiRhG z2qF4lkCnK_G(9o8U{tA@YAN2vq6dKFJo(YS*fcSVy}OybkSI4>qIbp| zRL~E{PF3DzgB~r7%I6m1x_n=;#2CGg4X|fk*y375&u_izT@g55hMDPqFH`dQkh7Hx$v-iE+c0nc6FQ>*D`Jrf{LONev|N;TwXa}9djXEzM0@f&!QIz z#qds#!3TXQk-nUequ%Z};?kI-N!o(J8((yqkhK9+_*5g=7NQri|vaQOCu&N zPq`FS_;FN$1ZBain+Us@bn*5t($mGbTC!2?L*9M#x7CQ1N5^U0=fOZc{cRk< zVA?Nar>?Fkx$x5BgVkbn+p7xdhquVLqf9yP`I|1J*&BNsDsQAci*0!D=hEPhFH=BT zZ?!KI2mkZ)$L3$<>Y4C=o*qPwKYbUaBjK2GJcp{cQq1?JyUT{rrTnPvu4N+p+cQ|f*-MCU&-dokvffyk7YA7l>Lt!7_I@Srp5X6lb@qX*%Ng;g zdY@GG!~qvt3+4nN%`^XN#a(5(l|z&Y4$?xP=ODFrjQk(zo%?cBN8k3o?dtZm2v*Ix z?X#V+#RqAosuM$kfminnjfW9Gyhh^Jz=3a0j83%9wEwWpQl#y{% z&y>jHHCE6<-$wQMpZ!e09w-kOUYL;yl28rQt) z69Y6k%K4YNF*!?hX-Zy`Y`&tfNFdyAQM@|)jF0pZVhibQY5{w#GEbkE3%2vp8kfO+ z$KK#7BVG2pv^xmPJmyBavb-8QWq#OiAQo^B<1;3U}@ zRaZP0ENZ9AyLnnP>!*jAy1H<`*|z-4RTm|gvl+xGePF`ERh*}Cct&y)LK`YA>ltAM z66+RxKpt{v6<)Iavm2vjxADd^uaV+-#DT|0wRZ->Mo`TsE1Yv`D$DdWtZz-ZXW>1^ zAUKWyhI$-B4?)Glt1$*8$`qyk9ysgc<`nx@oW+yJtTe{_$z0eN^-v0KHme* z;S;GRZm;aF1TMz zrz+zZ!{Mrq0k-uBF5LChNFl>azkq_SRk<`;x=)N8t8Kj#NLOf#AA3(FCqey>>nE8z z_{deJ)&HaEEaRH`-#0#_8<7SX3W!RHG>%OSLPQXxOGG3lAR;BOA>FBBDFv6VoUjOX*zeF*txLKpe$>O>pX0)Zy z;(lzT<>B}BCHbAJdx-nZz&Lo^5~D7`tXFag7~l!+Hfn-<-%RvzfmBpcR!aELiajV1 zH>$>tiGRehR&wx>R1v);qJ3)=8bv(|yD z&7h{_S%aG|wFKh73vwCPQ=4j1YYGL@QQ7ACX%wpcayW0Ma&s~X1+y(Wy)2P>c5`5! zcDEN%Nrcu;067@d$7)fyz!vQKGEoexTCzKWYT04uB#%a?HQq|rd(roFfKth31fhyw zdR#Sm1{Qmcr4qbd9cbXndAU%Z@$owE7v}fFn{Ki6wm@~c!`aqImW}=E6C?NHCy)UV z6ZW2AzLpdQFQVERDi?kKDFI%OF;V!FIskSKBvxjc%r!(^m_ZldL-Ug->wLnmhk1e2KN|pjG7c3&Otx3Ah6_)~`#EI-k6&PQdj>wiD>(l4A}e;ubW@TCYbL|7=hAGO z+Mh%tDCR+&G2YzaWEH%D@#NZ+yua7_T;!+uj@us6tQJ;sh;IKX;R2`qc01igSshY3 zRNM*7i2!@+qL1=`oFMSLfn1e`|LI`!B17w};G(_A=0p_cTMXn?+hQ1o^uDE59< z!)xXE=?zX&=WQ>N=dx-)Bc~Wfdb5?K!?GFxU{1)VJCLhD#j)0wfwk`fm;e-xg$sSD z!)lsTkR%2EqqyX!ujxdXPOaY{CSjFxu~2S5PCSyJjYoDN*fGc5S&<6xax=VZXPaCj zb~JBoNx4e2Y~&(Q9MYPKOgdtJlVOtdSn zmQsQ;Wh3V|qRl>MreR_trdlm2AU_NPXoa^z4J$-u*+lzRn<-T?@n{&P!T=9lJMzBcIaQWai#rf))x=LLC&2+mznQE8OFGo`yMqjoS&R`@~ ztb19*Skter{|3`uhfU>hl2RQcY8;YtW{0o!SErICTkqV^jj(1B_&^(58#pqLEaNbzA9Rp%Ec%lF@OvIapA}M72-7?nG{|()6;kf5|N=~4%Dg%4SH+W+-xqV7L37WYUbeLLw@+8M`nMyc^p8jUGZ+HWBq_R|w*p|B>8Cpv*F7iw0 z=j7%Gy5?zcyYQ>{soaJsTL$v`_ijn=<6FO9Ztol4n0hZY zMSjG^#x8@?jxvtBKxW>iOwk_bmbm(4p3>2Fv2OB@uEYpOkZ83rB(k)AatTr;ceg{+ zP$b$f_-%mNzoOSY4;D2L<{`Z302;6N66sfGOX8()KzAcnIKQ7-6`rGdzYHUpFp!zLe45HMgDz%w3D7A^PyA-AF4C$owvT#x^D zQPV)^PM9q{HZ*#V%~ZYAqkJ2{>1vJqS?Y+sG0M7qCZ8uc2wGR#&0M}4k>u{TtlIxV z2jtgueKW7v!WvqkI!(=*l-JYZoPOE~JsUN#BmwD6QQar4eQyRGZNRI7kR7ZN@ zL3foscBS6BkZ{txtGl^^iek82$71r&3N!DIvlgVpQ4wbMped36iH@8Tb-pb&3O@_A z)+~8nfomXXZ{1^G#Z5NtR=k&7I4t}0prq)lbCg*EqXw*T#9`UYky+dVAJ?bvL`d_` z%;YF;xt5S{oSNfK(@=Of4_5=vb=V#G)?8?MT|+qQPkG zO|`384H8ZhBl;~0a#?M$cySp$A@DHQy%xyxv2>b~VHMMDY)L5ZTM&!AS@C5)@=sH9 zlMi*S!E)78nh$%gGB@m30#q3HmkoN)UoP(6x-RypHf-p3U4OE!yzqiS|ruC zj$pSay{=hWt9Pi)fco979B*gD)HdKgO0W%M{%TVUKRMw@08}`kx-Twe?-H+x)+ZGR zoo?C z0kg)(r=^~=xD(A0&hpJVZ#s7S0;RGJBEUxu4EbZd?)k+HL5-%0)XmtYW_nWWJQvhO+cd+_m1VePfx8n3{9~`Cx7m03S11vCj!xsYODvdVnDzzX`NY zkJ-#nxi(}Qe0~4~g1Z0IzyA;wOTXu2vVB#h@r^>JCTbQAI0T2>N5nE}w7kpkohC#ujf?{(83v5~{%qfo6_R-uAK4s}nNX&kw`iK}Q=p}p z{7yL8b5u)AS!|{4Bi~o20)|}amB9fbyb14*wePdKl6Y*4S*fD=8b6rqZTC76%1!O%w+3aPC{*#73m^gmEj+&>$VhTQ_Gfk zMc!ar{PN-kXzM=PNBF%%+`uOv_o)zlD~_^;r;iiwbL*=r5mm)g+M8n*ttA*474#(@ zk#MTY9DMnig+(-pdO=%PM&>{2_-gcy1wh5|PuI$1dj*ABr^?^U%evyc4+SoEae+S- zqp{~9e!T_DPR)q?(d1H8+vDVc_nD376&7=d``*XBD||_vZ9bB{Mgkv<@Up|xCA9ni3Zj4HMrbWe8LM6;W67Vmz%q=DQD2ovX zLCJf!XqBDw3MrD44a`JRxY?KFoajaB-L2e9o%F1&AVxjnH~L;-E&V5#E$3UcoHy@B zvkA7&oBO!8I`el6xmd6QL4SHgo_FLvd||YgTo(PAq4HkOQ$g|06ee;hiTaaqitMXm(_chD7r>C1Sr)W^d7G44(O9v+?;j`yro51TH%422GqHGAV}hx z0J;bHvp_dZu&+Ml1GuFd%w3#Nl z!b@&3$R>3#QDEA%_S~P*XbRS5seRc^Utjzxzy^GL?Sq8lh9--?gI?=C-#8yJhkuDx zA?FwK2bkFNjLNEw`{+hRmwbMHd&xbK`{#D*ZfQ6;d@`xSlx@+3G*&U zDTvkOD@D)VD0Io^OX3tuCTeE++MUwf`+-Ogh)zP^J!}>!x%y0BJ?EY>q)%5hTo+qr zsmQ2W+I~9v@{DH?Fb_IV9<}3d*G0I-wQ+jd#%SZ5Fjl`pnn2&>8U0uX5Qdo9ID3Du z2j=sR$AvnaC4c2K33Mg^(YAfp+6l25Qv?PSF#3&YEzNyq@EX zX;C+MUHkr3!j5J(V=kNKUA>^dg2aNxU%^JN?=cFzJ(tTfu@#D0R^6dcnMhP&zw<0% zT3-*eWPa;0FgN<)1?^Ri0{IA} z$DWa3h*9f0?tU=-cEN!(!39sym+5AX2PJa(8w(>=yess5ia0q{oBozdQuT zTGPQCRymQKvat8<(W#j~D!dhOKlxn4Y%qD-arRj1nfeqozTBqj_bIxG#^>>)KeGqr zhr{3FaZw>H>LK#{sRra5R`^&#T!ePcUUY%2Zy5Zgq8W z&+Eq3!!lI;sa6dCF;hZ9)-Yf-Q|v)95Y@`@*U*Z=u7EWL@Sj@dr=g{p_jFltu^Gyt zce)xQe%#Z4d$;2>siR`|0ZQ?p1uKS|0|MP$*^r&jh?4$ms{yN55bUP-8r;XU4wbUD zh|<4~_RoAXtjI^&%8+fthN(ky_TuQOZIN->-R(m!g0HvhTGl}nHVl_VO7$~9=|-Pt zG08_UUzIAWvv0->{QliiQX7K&uN1$;KE$-__% zpcEU#j^VmO$MoyPC-ww{x!1&SQ+Fw>xe)4p-5Yrj9dX;^u<__RR{Xa?T} z&X|Mjg#8CXWi}I6tDdO9dIY1r14@E2ekilrIHFEq8LIa47gZ_vB*@{LwPJ6pvCwJVY>Q%Eto#G5m|YzSBleD zcz%`s2eDsll((PLxNo%@2pY%VhDE!yx&lY3#4xvqw$h`ng9+ExSrV|YUdgqTCM@T{ z?*&Mmq%;ZaBHgl?F!#qSjWajG89&jJJVhzaj-0S?(!7wVsZ9fNWa2u2qQ`e7? z?$&`lp7L;p9ugnh2&lX_I`1)$^7%Vhu#hZ7k&dC|?03v!AW{>ofl}8CGe>6F&)!dE zJ#0WTJ}5y3wDI8`i!HtFyDqZ=4mB15sN-JuNW&>{$-Lt1WUI{sOH1SsCIc&^b;Ren zI1li=SPxVfpH=Q1j?eVh?olxFFE!YEkC>lhm9_Yej?a7^d^9);#}(j2Ncn9Hz^|k3 z{J!0(5J~~-J`M-6OrN@A`nx{&N4>3^ZGD=rhJ-uW`!YYeV(L6&?!ti@rv=)1z1Cq! zj2i307#bM^qF^l@Osa4x4X3oG^bp$0s8~%sTUPwhJJz_ zk(pEn6(dq%6+6U{e4T6Hkah+SR$2?Kb;&C_T&8VvK8}*VmTH=Og5O*(6Q;V9~_n4aayb?c_yNciI*1(k7ND--B)UzZMjOQD_CX4&m zY0)P+i_xZo{L;%!AHR)`UYCniq|E%F>X>j(rUKTT^kOCBKJ+W-A;`AxK3q*8_M@7W z`$|nxK!2SH`<(}`0x$YjF0yGK1TMVRVs7;1Q;&b(;yk?Md8F#Lo0@&p87_21NoeXZ zyZXaUTsF&}#jWf5JO|PnCr85kpGXfe6PXhO$Yx)`ne6yxpd~kMq|WbLF?S4po=)8H z-k*wG3!}HqG5}?xr%oo`7KFWK`uT@!=v2)14(RHqpg}o+!+xK3RUx~ zuuKi2k427ia;NW;GUDU?**a$_uD(f2Ze!hgNA9v__&})savbF!@I;FBXe5pL=EcKpT&QaJfgLh*Ic{g zOI|rq6&ZBgj4=it>|?2NHT0P-u_2^=^Xt&Ex;Vpzxx?IvZtin=9Tv23G?pei*qv!; z{CR7Dt}+M3yo(*&9=YW8l#HvF#V{*t9A|MmSXTI zS>RUYS|6P~KA9oBt(%yM?k3oG@%7m@M85nX&E4GY@GjcJ;JhlqqW(t-ph@hSowc@O zV)qNc1X_|ucx4VWF7v{E7 zxU`%f{jM=k`mmi5&JzjOihUFArN#Q>2P~vLic=29&7P*&3j1)GA0z&Sr_XN60&t?< z>35`k$P6;nJmM9e|8=>iCFUbpZ~^Jjdkj?_lef@jFnxT@|9dAXLN0$#VYzviLYXFAUFi(B=hq5I2$jBRr+Kraji@W;LdC$QDRoXF88z^Xp+C#6U1IQke#oXz`T73c9q9KeCVB` zUrsceFgFQa-mS}d3jD=amIpbHbgL^DXE)Mq1AAB}iy=lE<&tR|$`36AtP41Oz?gSbVS9O9Y6V!2e4I5OBDl z{X5$K2nZa%+qgRN+Ug$bZOHXj-!u6gzPO<8U;H38Yn;~^7zqc``44M*-I`NE>Gc8L z!gue7Z?Dg{w!J%FKltY2WmJ`sWjj%VX!1>o^0)8tfn6NlA&dUDvLghLb#BLQ zLj_yKE*LPD>fHx~C4v!e{q{|XN|-JXr{}wU;0R74=ny4>6V>zV(XT|XjbN5lii>!s zHO!A!I;sH7E{Z;?&q^%(1Gjmjh%MM>$k+}e8jerPzU#mHCRwnN_QMMpcEaMgmo6B| z=4XEG15NSB9HHYHao-sA3C$WQ$nlN5Z|#FPJW=i^KX~;Hk+Ww_S*!Ee_rZvEw^0p~ zyU3IU&=E^?I)K&mcbR{8dEJc3Onqzhh)fJsZ7h%LK??q3Wj0^x^=In1d8pJtDVz@v znQVtkhfHYsohJ-m_n~^IGER%kCURrELJudmR-e^`F6a)~aM_BTlq>cM3Qp1#=QBfT zs%)xtlv?iD9nl@B#yIZ)gYXr>t)}@!wNp}wA2vC=nRC*So>lTd4Q)o98;G-1*~~Tk zd-8)D1Q-bj;LuE_M$L^H%)8J^`}2eh7HYA76?(OJ8w^0%TG?A&YY0o-qrMPHQ4cz| zNIKch9u$i+uvS_`Obb#4ZuD=gW`v1y{?hATirlF^USjQRu3MOJCaRVytfq{{tlw1~ zr3N_@ZJN3D@QB-olXR&2eK%vSh^RdSWwUhifS+M+eaWSgRi=$T+CbC+6HHj@g78lp z$vhb}CwpN26t@a-h5@?QYHG>2>}9!`@dYVA#bWV{2L{d>1X%+WTfv9sB`yVJ@>?w; z$xUvJ8|5lS`b&MWXr6DfGV$SaE+*TV4=_F@Z|h%Zjrwe-(nu&I%kHV@JJs|%7w8t7 zo31W@58$e@u;^w=Y$%Me%oT2oj+IR%nc?REI0q-b1eZz5YQ6CbFKtE2YUA@0Auo)# zGOn-EFPnM4*?(HgJ1LK(+Xvg9(ERMbJiX_LnE7kG2~NJ%^MbM@ozv#GE($((23x$g zZrL9!hBq!IzQ8iIvr3kR{;*q9H85&S(XMW=;H*ccN%M5{IGq&oZQte;oRzuhD&N|&b%j@qs5)g zwW`TOlk(cCMrd);-6e;(gD#KPTaww*DH)9*+bh3ipW$1uZnbno_SI_;JwLYOu0B=J zJ~y*V<(DrE{A;z>pCT^Fu+cWA zw5QYmgluLMLK|iW7;@i&@IY7r?UC_8Q-Pl<-Us>1L@YGrY1Qmi(K-43$5Dfo_x&c7 z`^8Qx#^b`FlB5hNIma_=I`8vma~?6uKuTy#w2r%cVBA`QhBCUHRRSTj=bF8AD*~yS z-oW*1@`=Teo6B%E6T#hD@dkbjW87m*mYM_`)YrAduQ;Wgs^Ma8T?lM&8}xz@bF5KN zPQLGPgy+uWe)7!ZD~HLD-QCDDB$J<3rld3huGOAp-0e#Kqa(MId%81o;fvYEb>Owu zTbRY3;|EcNaxtF=hm)alm}sOuqw><`b6js_nx<%d@^VXduRkj|<}h{M32}8Me|BQp z`5iSQ(+9UyoxB#x<1$@b0-iD_Kc$?ghPB&@LNn|4N|yZ#|Ma5{-s>GEb8*wKga6C& z_;z-MB$m5Zm&NbV_}ghYpXG#21NK_0mtC2v`zO- zTxQhqzw)@Xf$UXd=+bzLL2$X{7y{9c_366*f$?e@D%wzAis`QS@-MigihpC8_j|*$NHU4iktbT6Mxgm-ujh56Tr5P*AT8P{?SriZ-Nck+bJ+t{yikW;bAzya)(Yv`HWuA&0GEux{y;88y*ixna&Rlqi$yO=Y zA1842FtxL7nvyn#?&M*o$U4|eds%yc=4SVxs_t`R8A#}(UUL#Z1a$)cmCli|q-56u z4Z+`{XvGS%UYu2T;!fXIC}Mvsl{kSuP#yUrBY%TY2)^|mb06@VYT+Hx#MafmzfOzs zs(#!5fyPT{iJvTAgfaZ4Rw+KVww{dH-@i0|`NQe!wJ9;$2D75y{>Wz^?7Nkb+OPAMK8_m z>!HgoaDpNx;Z)92Chmqa`km@M8BV`hJ8Vu4B`!A6+$3M{ZS}WLqvJQ`VJdy^zSlge z3Zo4efldHAQC&-s+0e%=b03bIS>GAUE{L$Z70f+s70G){CH-84L17-uc;$PW!xpKt#xs^`i_Mhb&VhQ^u)mnwx_Y%rBVmaQI@LIT(e{nsO zx?yrOtC{yQgx8ZcVZ?>HCpfHpCNp-JRn9cu_VucJ$Mfi+ytoADJ$uIMCz( z^;;%3zr9|~Ik5BL^Gw|i^qU4l^usrQVq*FmY0E4h34mJTX&z?NzBY{4>JW>J`jbS6 zxiHX6vEj?q>f|XC21xjGQ)Q5C8O{gvgHBPe>K(+`?vPdxIQO%X%(wNG;g9acM+e2$ zX&vcYeh*}-Ur7^ z@mEwl16@#RY1_q$IXagTvB{r!yvM5c^;JWE7mf)f@1e*X&#rgCMa|7pEvAezz_O$Y3wr^o8b zPy?fuVFK?8rXk8}OQ6)ylCsVc__;0Y%~Ts)`{rjC%2?S;Bj@D<<2)NoUjowcr&*Qu zvbn+gzbo!T_T{Vvlf~xC3nnSC)26jv*0)n!c2lM|#;GG*R%Ye3dDnfTu|h8l<{8SP ziXaJ3y_q{&ohL2na9Y%sK{_?5tOv^~I#a4+i!SoY6!vw`Pb1&I+?$hjv$rdHAXuUXYh=bz$HEr|!WOHnxd{jJD$!4jDp*iEcJb%i}nfJ}#^^xuz3bCFpFQ+)2 zCY;xOx2`TNI~mJz#L}zJ=Pz}-_SJ~QZh0i{A5?WxUGp*ER0^cIu9-~>f2X{eWufh> zbL-FTXN%^~*UCkN<5JEl#M1O;q;8t5EFZ{~3`Up9O0CHVX6)B8J8oN8T8cZ})3}ki zNT2?-qud^dZdHAuDV;qvBe%~y#9XCQbq8Y4vEEF{vbC>kse&@wRj1$lPEmaSaP4zy zyItw>03VLtSrl&mp(?GgV}-k1^|PUGnF3iy;X#bMNlnZ`bn@aW#+X08*ItSJ=8oV_ zv0+j$n$2I%p%Q-917O@Ku|S*dVInx3Og){Umh^H$-qSgV4vDl&R4qBZF&}2Lq$>Vz ziOith97Yt)V$5F%M^@MQ%JhK*{eRG&R1ACSUr!N=cgqa?fBEfND9USHsemVn>5}En zFHmdj-*q`&+?A$&mv2wL2~=0{_TFr9F-S_sp%c>FZhe12^BKXL%~}ZMs!ZutA=)S5 z>})bMd;K=i;RAD)nj*Z-pEortezsk0BZ*r?wK(=x?FQ7L+U~^|Tl)7qMS$M*c?R}e zv!qo%&pOydfrB!IF)Tmxb!Y?s{Rg_f*CsPr?vY{KuYTvyr8dg6ZN}ZvURZsEQPZ#X zV|qOYJ7@r?$~xDU6(3b&#-bodOiiB^WSV@lAK>O*TZ4TaS-Z~gz>&B)y%9;b9w9o+ z5dTfW>b_rh(ac z<|j~)D8{~r82{RLx86snVneHJ+>78J28y}pC+WC{DZWLLMq1(|Gjb^pSwj&_n9&%* z11Iv0>NzN{pW@6?pMru}Ry5In?Yp0bt!hr|kIEP;MLS1~#?hbTrD=4N<-1iBux*MK zRGpUR7%$C%F#wI#U{@ndL5QSl*;eCp8NgzEVDEVE zsl8#nWKBiQZ zJec|)=urdaboXRI?k4(gC+pGROLy8)ne=}ZvNaJ#c#%buwh#)#m3EQG)1N)cAztC0-RO)r{{R-bFxeR!mRyO2#xC;cUSDz$H_ikarr&py#4?q|fB=G)mj(#IbO zmSyT#YaagL_De`enxmR@mK>RMeG88o(mF~odh!|;qJDR!K!o~&%gBK)ap5?UVAsYBsq6q4<)Bi1-^%MSext6pX;`X3K-CoJiXFQoAvUQDANa6ODAtpLfi|~2M5aiv5?R9T^ayj zjAk8uD@Gv)S+;kn7*^~2rdyA2t8C42;f$W|WWlrE_^n$6hqGibf6*!zl*ikAt)Wv# zm*9E2HnSRm!p2k+73TaneOj!rc6sO#9JX|+ex1Fe$faWgMeMA!1aco0UO?Y?p0xc6 zO;#ri>rQV4+@S=9(KQD<2l8^tZU}vJxWe9p(NRYwbd1Rzb_m#~dh2VV;{9*SM_1(B zQDDkdzHlE!d@FJmap<_iBlKx|vN7wblb8*;9$p*$aaNtNR`o=#1$< zZY|O2#sv;@=xyC0zn%c#{>U289_q{RNHW0IPk=JiVsh;GmEaV34z{l6wEyE<*yH!C z>q$V8aFJYVghp#l7Gay{KzR&khna8jd6*Y!qkx$Bpz8@(zhQ9<&w#(nOV8l14nKCq z-)8@TxIv^yqHY~qknOhru+!;Umyk8v#uQvgpKdRJeaMGX={@=;{@0AoZ^2o#7W(Pt zC&v5X8%nA;xd6f5FNa2pYq@S$;M_x9+LB&$c(ZhP2bd>|N(+QQ$bl4Zr)CBs>!6 zzy=G#z}^jyqb%TuUVSN^d;;t`)U7G{8!Z<#sJF$(ggPSR&dJA##IW*LsJUryOPd1apLj>o+iV!KE zEJ5yXrvj$OD}?%`M3o^MjH95k4Gh!X>hP(@a-GqYtI7y{%NWlnU@&uBuO$tv~I}bo`!t?udLo)eVX8!^1 zzrIKBXHQ7Kf`28$-~tKh4CG`ODs8o!DOgjJ((|&HLG*C=*U8cH!pL}|K7qrAgW_Z(0P&4zhYumh zBRXI-P+{++E;H`VtS~cDd(asx-;On_1h)=G^teZxpqU}Dt_}C@Ij0=KTOphT}juI&Nvnh}24!_4C5>=OAVQcD62!pEb5UbhUGp)(=)-;dp8EtvGKb zcNbDKczrm5Y4G-4Q9A|-ir5#>Fj5-w4RR4s05=Iwh*G2qBs`145y4E#LeRrM?jhu` z#=%4%+jY}fRrN_7=**j`!*(B8-eaL*$3%L;rfk-dZBibPmBzY|WY|nfBT@s}W&1>% zsJA&P1B3UrAko3enOXRtPQ_>;heZ|M&D&mt^VlUZ9*8J>;42|^jDXR zapCw?%qmU{s~gfEkQ1Z_jH1}1kD2H3F6Wx#Qlg=^bw>Us)a2CEhM0z`vkJ_```rT` z6$RjS>$LHD&#B?FFvt3M&TL>%)~fDSPR_p3D(A}f%gJNS*OQ0lEYURsbYo()bs%3b zky{)ccG%=D9ocpre~ubW$t4dWDDfrP`@r8J(pQ=SbeZ1H2y>|y8D%{`*NLn)j`0JpBl+=*>$nKKmvjU~lPuX7hz90b8tNvcUP=Jz;+=FeB24Ah zB>mU1?w7RKelk7K4y3Lp6+l?+QPQz6FqG0et#ce+zapI0t+;YCmD9HbLQ2&V3)0f~ zn3hJ75l}IP#NUbQSX~N2y@(({ciQW%dtuCe8kH(6KLI=BY#ZO4$P5b8!{?{s-K@cC z@1obN{g&cl$cOgm@FD=>{*d$q>59C%%cU|JLJ%eD{jQw3$!+#_sx2#@^oy3_*SFvX z#@b5dc^^vJ-=4s0*D2YK%DZ+ChWP^(dg`L_V_lUVbeUCed`_S1l-J6S0w{sR8<$9- z%f-i$Q+&gf@h6b*$dAJoA=YIeB-;dV0I_yd?qs$#{vH2(5XOu6WIRV4?_b?OOT4;G zW{|PTb27_Y?JT2Ne84PCFw)FIhsH_e|5_@v;i#})91HO?wngg!>Vmv8tY^__&*nuz z-rn}B$xZ>jB*Wi8_Z-+VYf#;Et4oLBb8dpkHjl7>KmY?7gu$o^tm-FCAc$^3QM}JuT+AGl zVI~)!WQT-)Da8xow)Lh`b?%#c9}9gQVyE^X7`A|DZ;YM$kT)QG>^bf?px(-cOC=d#{dgam$Q3U zn_w$OI_xHvtDyv6zjCy%6K!EZ%A|W_Ui5mH-D^}PT(cj7$O9aj7+2)sjXOGuW~72P zHq+haA5AL7J7lW%?^oz{w=64;8!G^{GU!vQ%1rna$ItJI(6*nN-=!2sBOMcBC4rQA@&{uw^D#at zPeb4i0l>)`jL*>*I%=$Kp5p>pvQB|i;y-PQq}Fy+DpVS{6@K27K(LjEZd4{ez6DhQ z#;?Gr_f;grLbow~_1ARm-F%q#Ar04mLZZXBEJw z6|Y1QKuUqqIN9s+RaYF!7uZxY7G-U?`+*+ir3#M&ZlS*jc`Oar%lC{v}F z1I>Ujki$Mj@C<%nLu<^)izOHbYPF`pMgw3hz(xeT8s?SIBj3JQfVOF>H=t59(+woT z3Lpte4A{T9C9oe|g-iBDOn1Dwy)Cx7_5SC2DzZ6yWGxKK+H{10SiYQ?{h9XxhdI=S>?F?R!& zp$-#;3&x9LkDs()0djZvXT=^JaV@L>-;07m2Y0a4=)*GMzMZwV76BbDdMw?6A3jjv zyRqVAy2nL3$=58%qe#KJERH{kj3x*{Kga4CUmcraS%|rZw&-J~oI(G*wfI{|J|Yj+ zwY#M~v`rps-|fox7>OF=_m+O?EZt)zF!RPiN-|fyQ-fziz)sYP$CjqO&7p$hS+&$h zd8F(r*-9Px(t6B`$Q`%V5LmiS`hkEzzc@OgSJ`ykF*&_nsqY_6Zuhw5h2ip&mK7hY zOq(y?ZLy0SRsTQ(g3+QXD?b7|qA%<+&B|0M(LHf^Y7+&n>RyqtvR~Rf^JzaD5zst$ zL#;~hS^7`D(=z@l2}{iwQ>5F})xPXEPa3)=o~k&Pjqouh?D@ zFJeK2aZKbnL{8Me%YMA3(MdHJ48s3m{v=AI(R^Fqn)WA1D$f5t<=FEOj(lC}!jEkN zT0Qj_(QOTW-}@`w9`eq5HuEMv_CRar4}S@TKy=A-Wp^YXa_9QmEWiC8XY+@JnII2) zEvk?-j|FrTgAOvH?P3qD@JVq46+HpRR!&(aVMZA1z*ta6@;=kJg&dwi| zaq-h!d|m-DyXJ)dKs@O`DcXkKaoD$CwxYk2g=(V!@iQy*-1Zh`p^A2ixA4#I*c;b> zjEu*J^h#Lj@ZEy#=%xQaQ+yz_$B;N9HQZMteJNSQvh_8+nyPBaSe@p9CjiDTDWT}F z>qse(-!nE?GF_@QzNampl4ZxR{^zZ#8Fc{fwvLN~5qWr?Or@{Btx0zJz?655r7b zQw4}5p-b{W?iq_u{{x*4mfbnKUon1?6=iA-5F&UtoV>?~)K9fB-@jqcgBjAnhcW~E zT1q)#r5`(!lyMSI?%Hz$TM1?hGlN?8TJUFu>P*N|}@_7jJ4)=X(pFFD#b8xouOROJUFrw)f>;suCq`}}z7hQuvjJjwcpk9ll+Lnu6LFU;6#Bu6uk@ zH!n3<)w;QCQuBQ1-tfC-XWBLH9_K4PgQX6YOXiQA9#g=qYEv>9r$@?qTg;xEu9$&q zlE1IXc5I&jc^aqZ))O9Z(=CVK5U)f!Dwf={ibr^9s_|7TosYWTuY0@XWY+y#iNh$O zb0=vh4?jt#Z_s-fjLpHeQ}-nRZ{Ao`GommxHx(9)q7HJ(v}&A8I&K&w*HSD%B50C$ z<59szcfCb8ImZ}he@{R9+R=tenDE#6Y}g-McU&WJZTH?DUx39MUXa0;So)4qJVMZW zF!C#=42TSEwlfqE(bil$7=D}iYElK{bhS=D3E;sF z#ZNfc)AB-9CjiN6@(&{f)hk2$rqZQ{<=YFJqG8L;iQr~69+lRt2mDz_i9Qv^X={pc z2jq@RUvEy)X;<5-2p6*GuKobuBhM|Rt%MfAne(_fC<}ldWSef)#n|>-GVZjAVv@h$ zco52tz*r^wevd4CVyRcIa@qUyC$4IzjLULQ#jfrs zLomyM`Fc5ZkT&i&SU>2D z1;{q$uxtpIk0J!{8js#?9O$qvkfS)Xrh`iD)-Se2*`Rsv(_a;C@!#4JM(Syy&Zy=N zx#D2apI8}pt!~!fbp?y^_f+nf*tv2oj7mMml2hKj-lT(tAiT%}$g2DVU?F4MX$D}R zk}u{C`AV7Eu47KREN-L-8g3jn+VfjGp2UX({))_=1_vmU02hi?8z9+!A?%U&c|&wbZA z8`yfOx6}FEnQ2od+F&&LSLys@=hkP4w2rnYLD>m&Ml)?9T6v*2m@=Ww!Exo5?v{$d|AF3&EhtDntgkBe-ue%u-KbN! zFt)B8B_GnXJredlCOx*?Epn?z&*QJNxcTJ~?E>@Cwe|DZPtsRRiJWn3nIRq` ze3Yj6Z(PilSHpFJDNayKzHi#pv0@Pw?GA+1=*%l~P!{6-*-gA~!4jN#oms3`TcNB3 zAbF-)bm`^b3 zD`z>h2Q?V;4z9(Gb|yasKmJlHb4Gu26Kfu;p~j*E=KeDMyxV0*wCl4)m}O^?nK`xT zw#5ms3{~1{TCOg5}v<1)#Ym@S7nWk zT;&uhMC!c${#2u%^BXT`=(khFNTUBQ@02c;ly2(?YkDFr+Va7RN#ZI4P|bmv-cAB& z-2F*xkhcf30?q4N5tiUXej`0rF)E|}9)FETx(nwxUwjy5b*(K9v)`M^lGFo7E!%c| zR#@Qh_NbIPI^DK-@qr46J?GecRezV$Y*KORH{f>-AWl-xJdzcp;Z?i%sCpMY`coz| zXezX|JK}Mn<(!r;*uBTBW@a*YW*icFQX~#22amJaJQFzP9d^5(b?j z&lTCS&Wgw;wJ#AKa_czGah39=B#lV4o$@JG8BW55+{o&8zCcl`4ZQiljYLw(A z=b&&o?V6D^3)%PD61LDeRB0n_uFkEncG!Y%{!$lpXUU_Y2zJU+4>?2ISEyp~OXYj^ z*@VZwggGCK(${H^UWomR1|rh$tcR$II2zg5(Ne>wa?awI83x@ z&S)LvY;t}DETSsnEzviU|1}G;OW)h{e_*uSTHTE5c9pdadnXe6)Yg2#iCrm?@zW3U z6v5Xhqa5|CPY}<;SNp?USiz*vuZ0q?Dj9I-X+r-+Rs@-|tCvRI)!uqimi#1U5LRZd zVQ&Mman12g;nh-$Pa61FQt!58+Qd~O66QH=%B9Z?GL6>#^ry(Bs)L44J-W5zpK!st z@%p6x{Ezi!^Su5M=HY;Ze^zy7d(6*7PBQ|Jw%O#v_@}&RU0rDscU?L!|M8&A=_}tU=gqp-;m^T0E!$6Km7T^|!=G zNHe@u-Zr=SX515rr<3u$P+MXP6)Yv*R2NEo@%c{B1zHXgV?HV6w8%=X2hnH`X?$?L zisq#-H$9}*+E$X$to(7aZsp<}p>$=mW@rw1$?sE>W&=w=2;HScN(Bf@(G|+yt8$Cg zwVPZits1(go&GG2eogM=i4VtF*`;0b(?G(bJ~GxM@W>ZsS!Q|jD(6XnORJUgPpHj{ zl#nHvGg{92S@aCE;%H3gum!R=eoef6&t)#$BTr@p5bEhco==`8M@aMBxh4NC(~qI| zGmj><=O;zuGRK+U=E0BBm`~=RIZC&EcT_7&_f1a*Jw$8G*wYRFeA7Bt8_If;97h_r z?qtR{edheZLG%!SQ(x5S1s|7w+HInqN{KhyOMTeIzv!+Q&X?xNIpmf5`nY#95$6uA zZ>^r3bsQDH+)-}aRbl)ORKF9uwCkpNZbq5V_J)Dj6O2+fupKXdK<|(UI362BKXZw{ zH`?z9CdpD|gumqHJ(>8T6oYMI-nsa%i{NBEhmw`W`Fr&#%Re*j#SsPT-&PQ#N+(o4d))7tlG+wJ=3gQDkj~J?;9IHn!JxlG$-ZC z6l(3q-V7@mi)YVm@pPwTQ~1?p#jrNU_M19o25y}e@HR9}@~RbLb6!sGNMo$Q)N>YKNU z^oeFu(4UbvwbarCoo`$w60T`uU<34vQ8 zNJ76Wm-9FB=D%=c{`-aJSXB-g@$$M0frgL;8;d|JIK)HKgKT3K&j^Cs;E?MtG9TvN zt}9E#OP3dU47k-V?l_*iextDpGhT7ae2iT>HN_xV8VNH~ z>>0jMBalVMr7pATRIs2J^n2wX_l9JM>W8_@ADdY__wJIJifjF$?*C23nynu3^rMjK z)+gGDw(gr`MNJHQX9BL&0#{jJx>xU%&*I@^HZ7xf>)=49%%^k1mBRyQrCmdQvFgnN zVMTkOoG|Ek8#{1-QX4)rmn2t&mMl^32fNal@TBp?zvgP)S9p!1&&3(^Fd1NM;S6@1h@xWzQ>=M>?%;RTYDPQFQ=4)Aj`y1q4m3(i|w#iX?69BiR68 z&CbEM_zn`LOyERlMY38&J{gy+ayijXx+TK}1-d3sGG+VLG>nmr9CpCY9|FqE{0r3d z_?I`pAyP9^ zR?YY0>!8m)8P^`jBxBXeP@|LhoJ75mPnt@@(n=)SN$BI-=I0rqi$VCSiwgPO5jX9H z{_?QId~#_dykjS@n+=^{TMZHM`YEou5n1i(>ue`bQ(l<*wBfV(Cnq&ZXJz5$vV^ZY zNRqQs>UDo}-JkD&N2u9EENQ-Qs(?_)=3^zm#?$$&)hV7s&LdN-g0XXqo0E>8M-ExZ z-)YThsNe->do!NoCA{;s*Y)?O;xMKR$m@3XxKIH_e-o0=}i&2O-Txyhjl|~e4a0Mwh@~ZxA5f0 zIQ7V+8D9GU4u79uqZx`n(tPRf%3PXbb=KbZ$?Ll#WS^IALr9Lerv6-obrV=Hgl{m; z^=3;F2W38hK%DJc$Vx{+(bPaBm9UQ9wbbZ*dCj5|;?m0e;}!EaJh`16^H&0R7fe?R zri1BCD~c955qKxaV&GMhLq-o~Cg!XzlwHJj{PoHDB#oC=X>ulE{1q@5#x4vm^=r@6 z@*7ML6=2Xku`e%G(d_0BP&j{7X9QSuKk$72<8{U17WoI~U8sZ%A+S5vSul;an4=&O z|AFZFC)&6z_mr8!dYHYQ6n$G%C$16Q)ac!&dO%^q4FoSJKg?Uo{sIjQDAnnm@$xf{ zQ*_SV1;B>N(^dNAc?UJk6Z7(44W1zvo^lp)1ho6%fyC(3en(L3rgQS0-7L)wv!`A? zHYB_>f{43h0wz0T`)2Nn35z`gN{{4e*n0?UZPT_!ak7eT6Xiax-A$n}54T@+JKzP& z5c&;T@xNf*9FuEPuDleS#KB(&dO_y(%^%}CNcqV~A_I}Ejgy-yI<9Yt1rP}*f{!*c z5_ZiL$P$Z|b~5NEz9{Mt=muT*>=Z)HcruK0cjXmK=7cnFSFR#kJxHb0yNH6PVv~i- zN-V9g!N8T>n1{kZXCS1KCQsbd)B1)j59?~Q7mw5h8G4ElrgzQf zvH__=BP=dwYB>nsjJp@UegXoXWNG|3E+j#CtGE{eQ|9eJ77ax{c**iYwbTtxyK!R= z`W5+z7#8>Pa`y1z0HYYN7G(~^PhvEMbz$mQy^-KTC(Byz@HUA(X|IGiNBRy1o%%_e zmT#a^A@9y#x|_Foj|DLX{(gky8)Cw&cbfMBiU0L&T=TgbrXUB0x`3&(j_wV-3{nukR+;&HQ~jUPe6Zwmx=WXrMfrV_wWcvvVyJ91f7Kl7=1S3b{_NTA&Hzj46W+87+J&L>kr`#c-P!pFZ*{GM z=a1{PyyJRC3n0E>HR;;*TtNe407tG*!(35|*XyWD)&c_?N*%w1+&Cf5Md&IAU~_CgXup2=hR_MY zyl7vDQ@?4#EBu1#;jBG>wzzEobg9ye3+$2C1UC8P_w z;ADRDvxU5nu&^NLQ!z^*PcO|!c0<1+s;0l^z?|2dwU#MW-Q9Nrj|NZBwLHUr5!e&U zgjMQxmr;&?;7UZl=zQ3#@mes~Tf*3%(K5U`Rwmr0HTBuolshwm3cieODs{LyPPq@C z-6OA}&OLG6>u_KRx5C)r8T>bB!&~Gq;B~uiNHFRd;QFA+Ew4Q<5ettxH z23WnCJ}hWxRJ?Qai@erZMV3X5gUTI{;o<4wsL*`u5P{<5H56t)`|&hW!4zPNOAWEo zIfehcY`b+UAui+ZwbrBD4D}h~hT__svH&FFC4di9Lk`kyuB~wH8>2ne7_R&c_=2e6 zY>Px;=7SxhRDCmrVKvHpu2=E-Fx;ZZYr45%kgqFx=$e!;2Co!7m@dY<&p=#|(UuJB z!M*av-;%nG0U&Js@=fi-2E&F}uPHvVAu;MdukC!cn^tkc&Qr7PRb=?P)s|Tf6(TMK zrlqANsA8zYj<2LJv4*#M;@^HD?ahp|Q%js65`PbVE`L)9u@ZJ&r|oQyc;(aHe}pCJ zzPgD`<_|-96fLZDp|_gcC5!0j!a&6C4FqKyfPoGGd_~9uN`UnFH8l#xI^-+(Z4e#@ zaQ_EVRRK?)2Nwln5bLo>@)eOlu7AcV0MVr+bRW=a?DN)}`)kjh&JbDX3s3DNw1ME| zzN6h9!WhxDt=2y6r1j8m%I`D2O|HvT96fJ&bWxqt;gs3qaUBnM?PJ>O$_DQHF%AN$=!^MWtjG9LDH(nRHvz zHZ*_bKyxLpx7Ut#)#9+%LWD6e*#ch*oC7a8C5e_63lUr4t3iGk+O2v|53)KuN4nEI zGpkOjPs^M;jJIA(w^3dX9{_Y-$6&%8#b;EjQfG=^hafTjn}d z`mp}mnp*gR!~t`q%g}#ytT81p7@0B0uRqhf}OU*1lqQ<4}-=I^jn;G?`2>>pC?Pn;E|+U8vgb zYpcX@f(!vK{E~ozaXzq_!aU!cB7-5-O2@x`!{fGB@GSW5b6-VB$z^8%%lfC~N(+GJ zzD1lyhReCO_%SEsy5>spJR(cO)pIFOHk)==d{CTb9gzW1ii4ow@_19=8M)>LS0fIt z3^j+a>p|EK{%*hU8>jPMqTfYicdlkPpm^rLcISWyc5ST?&1f%kN{*o3{}Nb3gr6{R zY^oT*GGzwk-kQ4$ooOm{h8oPDnC<5KCETQE5Ueg|iEM6))EK97C^Sh%Edcj0$N}mBUEb!?eagbr;|ftzrfcoitkA2o&bjD zn`pOeeElo>(wvT2wTnyqvuMau73QoHlMjmJbSJ=zldd!gZbs`#h6|M?3o8q89fn8rANYcmd~nY4XH zI7*As$BM>0h%t1osOf5X0Jw zd7WR5rSiZ#epy=@&chppg?6x%0! zDv)Wgu5qrT7__k0T?EUyFk1DRZ0iS2HpK=quf9=6=KeGL2gFVc7d9?HRVQDXN8&>P ziqN;w(H~mF&Q05{$ST%2aUAOFF6 zKbjvSS-%8fI8BDUGNGM{oT1gBSE{gvIn-POi6#tPxn!f?xbPLP{{x9m6vHF~5cGJe z{RE&Pz$Q#L$Q*i7(S06PZw8I#68aj->iL*1PA^dxlK%-zy+zV*LHi?~*vTsv`aUYe za^J{0@SnYQnWB3~JvP5cuR0}s15*(O#q=&OM^A|46E%oNsf&Tr+LhV_@h;fapqhce z?&9xv+~MJ0c-^wvO)=N-MZ12-N=>`c0hUK5m2_*sIIw3K1z3J3rXvR(1jPdq&U*)W zsQ}pNWJpl(C!2Ju*{6Ya8-vZYt4-sg@%#<_zpe*mxQ`8`vZ)dbvO4ge+r4n0#Avq?67RM^^?|#3^k#ONaTA)GQ6rNXRA<9loxM#}|Z3gez?J+L=l1hT}| zbW-{!Zxks21-fCJlrm4&5(D*=%ZS(mzC!*v{L++mN$a1?^U{n@UA-W1x!(u8EGDM% z!44|@uj-~M=34kN^QjaEf*Qu)e!|}arT@JbIJ(9id?Fun+aJpFC%XPRIdR?CDl9x8 zM1qx*;-r)7SKFcM!cGSl_k<^$&1Z4lU@36C3ik}AJcDdOGF`WX>>O;!!`iQPm*$nv8g7AM z!Iq^!WHNylcN?ac?W3bH3$vCoH+cE-*RFg;tzVPMr3wq!{+NvM63ANX4SR_VEP_|o z4M;r(u-`6@!~2(@6U59{LzS0`S(43un0#$zVt0?7^2Uz1C#2u4;4amWqXQ{BQFhrk9wvWvC zEE{N%obhUBJ{6^cbRI=#G5cpKk7<@Uq@iwO*>0!EsW|!Cs`9LJi9f~n9G+L8oHe@w zxwPNS%rj{b#TreM4(t7t{QzKSnwxP~&X!4*^vZXAy4Uz4tfuiis3=QThf3MT-!m;z zpNvgwqe2b*=+OH2iZ&7@(yqzQwZ;iNfj~hh^y|vK-x#I#hyu*;f1s#BEPu4?;lW3= za5>jBpWTyAiDuHqxZi#LJ6~v}ajn?d{wDR!84FJAZM+3*b?`x2z&CIAr;J^sR@dh- z-v=*ROLyDnk>^3U$0#(hD><&zat04Z4I8OkJnd;JTsYN9uf8a#Yf>x-T= z=02eDWSdVE&F=f(Z7VXc__m=ROc9?3V|BcCeBJ%J*kjawtx&>bjVVX-E z^CE8D9Ncjsy+DIl6TBXF>RPaAO}vR***<#zV~8PCTvK}bZXa~y9u-m!OFMr;paA4s z=MI%{BA>{v#r{>GYk>s!v^RUy)s=xbzf9zZ{I8^>W8(DSPvuQ*TQ}JdoACgQQ}=3Z zTnIXl3kO%jZYPsA`>!Ex@lE3w43@rN%csgBINUk^vhiAe&*8sanxg-mf23B$N2Ui* zf1=2GT`5ienVyHOgK4_oO%6FYt;O7>rLZ5kP?JitdQW_(WrqF+JGj)dxdDFgR(Cw* z_KG$~ikFZ#*x*dEZ<_qp!F{a(RQ1olBVHLkli`hBX!`bEqjj0mvKROE_bi#7TK*CN}uZH+c7JzLTiEwwzsg)&3ihOgVq_Wx0Kw0dqM*d#>Ji3f}vL zM6JH&Q(f+3kv-=QqFqzLmtL#jBz&&CyW?)Hh$I(kpSRP@|9O#{Zxf39pyagUuJyTL zsC6WRZR@k9tFzA#PXu2?=wS@K;%o2JFTWR@kNxjx0rQ@qsee6p{r5{W`^aR{ACTTYcjuc6}S8_mSB|&yKTonbc2yX@GQ3R?ZtVo&$HSihy8toc*e{ctA0cKxF!Ily zBKj)JU5}jCn@n7+xPzEv9@s%La#EYyn@U*6&x$wOM37hwfy;V26 zHpxu-%HPiN{EGrNtCq@Ed)b?QB%PJ?zqtE8uOVwjidc`d6n ze!ydv>gSmxk>irX#be$H@|Y>%D(Q&&r@{OBOJzc%l+UQV_P2TCJ*{HZ#aDHw)WaKI zyE)Um(yV7u3)uUc3Zwzq@KWA#`K{gLi#87EB&*COU0hgQc{c0iz2Vpe-W6$6VK za!KLiI599Y^+`1fa(aywGS$m(SW5Ah`1tiE{K%wUV$W20Vqpg1tw7kF)qAU}d4^Q{ zC;E1w>w-LgcP2hL2KLi6(Y1PUCx_2}S|`e<#)syobMcD_1(#;04@^`33{%ruTW#b* z)VUVJJe*jqfoD6)(;jmU?&@rBdudXAxrhJO8`~Vl6+FnkgFX~`_^jR|W$Ru@qXVxX zi^UFPC;yo%Oo8)nsS_22aH>s>TN|LjobmM;pLbqRh|)Bm{)0$Ztb-?;1evk?{bXvN zGG0RE`tfI;@)VKUfcdZ#x+l#8JMgWxxhwrVF5ke+fkdZx2r}g2{bSi{U`L7Caj0n7 zWa-y#5P>ojwaaTh{zw^-`2k3x?-Ev9|B}!$A$AOb(W|gFrG^Wqk@yZDl)F+gQGEX^r@Pss{NG>|yo9^tg_~wFZJ|7!!Wz+y;2%Xh zmbh2VYI5Qv13O_#aQQRZV7;9^4QWNmyG5*PYce?F44A5Z6MB#4TP0Tpy)HnPj@a;W zbD#I06boBA30AJVAtrvMAJP`$Cd&y&>x6rEZq#tp8$){Fb+VY67%~)p5YPiqZ5E~{ z?;76Xp5KPdo)<1d3ylvEKNYMy`;cqT={pQN!9vY2;2vpv*O#-Fj;0vm7ux(2xP?_oOb#6@X#t|gJI+W$Bz`FJMcBRUjP0s==^H$ zDszpq6QF(2BT=6`)nal;deh|QUlj4sMEXrfxT*22prQU-?f@Jb){9_m?`aP=&1xi< zUSRx5=)kCFzhmmx{>^1rZB<}vxysbRmyy+2aceIkzwerbbm8^ddgDg91Iz%3j|JiS zuDb|kgYd%TLC(H|!tZ}neELfgPLP%Fvw~XA%J~{@4*qVyM>?Z8yn8|RnHGmA!!)~x ze6L#kCw!~(7<6T7pbyQmppKp43B2+ilI8kYP@qdIF?;{@ietwp&Q>y2Z_S!%S5x5$(`vOP2XKKwA(+sQL(Kcn&^`JF!*)f^`o(@1Lk zJM2+#O=+u4SK19B=;F90wdotPvdz+ZgjG^(qwt9T?2o%dpfg2%6-74CUOCLN+*H$z zCbekD_9|MuzqHwN8aCRBDBiBGK}2$iVcH^q;l!@zYWs^QPa>eE$W%uMP9bB($#xCM=I1_$$4pe+Zt)dhZ-pkc?y~JcYX1rJNonqk#2ku{E&!Y zichN96r(Qs6{|;fv4S}Q)^)K@NZnS8%0fL?g0bb{d2?1fu}{R(XoA@do8)0m+aR&I zDQWroMX$2w4I~^CJ1qgef{#q9l=`1{U~CR{<+MMma{eQk7bf?*Y>IJD_H64nm9;^e!Pe{IZ|QSNBMi$YP{20J25>^1v^4(G&IQf7h1TU zHKc3@7y?p}!ncU(8Aj!9oDKk7Mi+t8 zfPcsxg;cK;6k?{idtuLc2W0pB=vA1;wq9>=c$B{UKO52EI7$9}`$3G&P zdR1?5R`7(E?h#Qs3)My>A-&xmf_nt4bNj+1=T0{WWfmNwLz#af@PUuOXeWXbZveNE ztY4)(wX3PBX-Rv`ArL{)y5Vw(-HIhMz>hOpR%RWj5Jya`l-NdVxdBF=7Ywx@aZ zD}=7?iO=eW5;E+eE65ZGIhb;lv?@xr315EpE`o}OxAK$Pn%f)8Y9@elzm*%c)*cGD z_8b)~quG#sF=}S%$b0Q!wR)yQT3@Y`(M$Q@{E#rpMlEi5Nt|# zqpG0EUs!&h^%j5=?jnG^T~os7f1oN+bTzhp!?pV;%tCsca0_?TJ*&)x^T!Zo>_t2? zi5LFOYgzl+{@7wOGj=Y}=nx>4D;Qx!fBz3nhjT9Cucin zD_2)iT}!)2M&8Ok=`VsOe@6`KPZ~JqM`)Z7SYAPyFl4SlQj>#mn{MSvT%VW<_}^np z!3KI26iBqn#Rd;f<3OS_#TOqon-x*#9e00}$xD4`5FAUv45@e5S>lxPL` z0f|1?-jqU|zt&VTdF}16{s;Qm{K|5x7yfFXnMW|1<+KsSGX^})@{qOYW4sTR87+oA zA>6weNiOh7?}5;M#A|L)8=-b3Guibb;q;Q#FLJsM7kQ6AhRMB8Xt0vHiTN&&xWn&U ziX0wPh@}R7x@wO&ZKX8C1SS*@IFH7_G=UG*mg*KW9#vP<*c>UYaAfvIWz(agO5Nr& ziOGu7z3gQ(m~FVQ|inNjaY2{q5h6ij0ZVFD)1Hb+_Y}hT`sX*e5V!*jRqLK3L|;T zP?$rBy(xdU<=kIf7%DZyuFl5;{aKXG@xrO#*$?No_s5%`=GLAC_<(K{k}mRfXxrZn zXcq9T&a`v3uQjdlAMn-(Jwc70M~~${tzqCgZT|M;KT!MhH7ncQe}#OSLxX6`ctDK* zR%-~}sf^bj$%~QL0MuJ7h_|DI*|ehwoJ^W7-slE-M|K%g*d+qmK%h(4Z`>>=Z^Dm{ zkni->dP^)s#>ZU!S^WaUoh}{z@AV_EzsZI>#PIy(ehXt7bBWwJ3a_2#K;UT8uV&9= zh|x2(wtdh1mbT*bA!B9X*|a@JI8g_G_!oHf^1nz{bp#r0`|!=LyVOOBVUiF?a< zyo#q2aFz<>4V-rCyf;&yN}$24Ufrwq4O)>EInx+m;Sftzr0M$tDM%L361>p99hg~) zEhJEGA#hel-_Xkt`*K0*SYvtVChEY!?u!Tifjr^y$N}KpZr8RTDw%^t`1Ec5U;HF_ zegOYA=v30Tn$~!a2w(AL?oY{=LFX~}5NcNac5nmHX00s$t>ycR6UAzh`5<5KFR|^r zbQBYjdc2-G6Ji;ZMMRQB@(!7V`9e|I&gQtdi7d&0;e;ZGV179n08HeSdb{%PeqE;W zS-O%&wg#N9*HovS#=}_|!{I@gdIvvc15MUV`~g8~J>2^7r{6b@Lo=o0fz?wih8A(8 ztxUGDX?0dsEYc#IM^d;FeNLF=M&P}Wz(RfJtn0hHSGEk5i+nd7dLR>9VrR zXSm&^_2WnW`BOl&be^8?lOl_BW>e4$T#UM5gdVz%UI1I9V?ou_p``y~$xKI9JIvn< zhkD_M*QMS{#Pt^eP8n${KCTS0>f$UZr- zE3oM{`bZGWw4RwhiWLpq}4v?XsK- zaf07*ix{~+6=-xIc&WP{uZ!+=qON#$E{|L&kqO&C#)cIjJ-_}3auyM@FvOg)v>2@K zxGc0*0*c95`(b}ev?p;tcBd~PR(o3Hb1P&kZ{u<{)<;7+s)viy#$W{bQI-=wxA!-$ z07!FJlH7B%_xV&@vJ#zg{i9-7L=JKlOu%*>51aYPk$QE|Jjpl zL+_XkIp3qSA0!b{b-SCWIc4naYge?SfmST#7IU^u@LKamwFS)tQv0}eR+4+*4$(wl zLGu?Ac9YvmPKnAiY*lNQCph> znktRRroxC@$({p2sq79x#*LVNQ-^Pl>ge}nQrV$74_-VX>8SCt!4!=3s_;`3QphRY zb{`*p@aVxC=BWq@LhY$V<$8=lSG;nrlVe>;wAZd~x3OX8hH}8?;*ANhx^A71T=X!R zcf)}GCeBKQOV(4+YaK~P=PMi-b7hY>?pAC{y4FK^9O{9gJfp&qJpU(G?z|;ihHhGV;7k!<_wL z+ydxA^Wn#zE9!$}1WHQlU4^DEG~WtaootDeeNrxt);bU?I!~J%5ql zofmB5P54C%zudR{X~`^E1dW5iByCULPkJ_gr%t$@K3OEgo+F#q0CJ`69*!2Xq9pOM znhS*Me^|L*u68)KXqHg1EZ3--)R^w}?Yxh+9H_v6OG6lNbGpzUS=`nQN~GTA!8ea2 zC6&qXw76WXLLVDve^74o#OXg<@l~H++tRhQ(NrLMqQ7B5(y?-^+#Iv}1;K0W3rAgk zQmMhBc<{BnbgEROgFGZkQ3o!$P|(Psd#E^Mzh?JF^JmJ37f)%QpR5M8iE?pZTtm+| z1z!G&|CrAHg+BrDr)_Dx-8GH~S8X&+xNC-!=$>5>u!dlwow6Rx3}@yp(lALr1;#| zRXFTCv)cKUvUbo~pp?~H-1^3i0&p_w_O|gVn<+VGSnTIGYK>5^HXH_h+`DM6bB%^+ zqTuwnL}<_oJN76_bYtcy^@UDP=;+`;a+(AeFME^~zv3)EaP$O}h-4vnI5rGLiUd@x zJ1EB4p3&RgYvpc2IayuD_T{lCp1&sG80STxmEusDeYcH#LTZ%Ef$M(rjL?b#+VObG zTrU>^G=+Tj;)ky9iww2SiZyO{c+lLAA|$% z(sUF0vF#pS8w>5Sq}WxK!4zRN!xVW?u3=40|J--4>*nWmP|XfZvLY3~A|LCs&?qi9 z$PVI=D8yIiwg>;%>XO}1z-Wg1u>V{;Iwer3p`o@F%b%9dMJ=llO;w_Qm)C~H=Cbr~ zGz?OM`09B?;v?U0f~zLRnXUJCBw$7X;;q`EID7P-g}{`s2iD5f^Y+G9c6Eu{jWOra zPphyOKczfv$<{gQT#0o)qUKG>?BnLP91i*>vL&)c`;_QuOAW{XJ($`x88^lK=gJ*Pu% z7~~%K;5LXP+U*Q^u(9@jO0(ON^zOag+%B)%B%k3M3qq*&m^gYBw!3qRG(LF2Yc3pJ zXCRG_B#>A1wWvPiBN3qDtEQRhZLvH)Tix9<4oS1mZkeC`wxU_IvMP2<=glzWaJt|QlK>S!ju_?nZ@K+dk9{c4l zd@Vpp;PWhnN|tENyyoAOgfHLXF0Lligh}_b4uR^tGVSh#=kvh)2QLTND3t{|rUdju zd@^S8upPo$?4OxITU(K1UFd=_=JWkX9>Hy$UtiTxZ7YgSnO)1{J`O^;2Xl(Cz+f248O5kRTd7D za{^KRT1W}}m z|JFY@>fp>ST9`WuHZbYydr3WD8`31p5#R)UHIZNQO(#((16D@1ED6$D)3>qUi>F(37jru&4a3gE-}=Q)zk)M33Y5f% z@82dRQG91r=-6#SS&|dyo!ar%ntvi2+{h2U4}h+?AVGJ*#x^WtZ5hR9n@Dlkk>gD5 zw1?Rf(|)y3ryrw3MQ_a#cEB%t-G^LnCyW%jx;cIPmahMg-3^^qDUEcN2SZ-PFJ&(} z6h5WXjhzQLEnY6}8U88WAJ4GQHRujINV1YMg@@CJgci#4E||Y1n!nfvKTkVeA$pf8 zzPRURt^j&+r)&b#hY_yLKO5e_sLENL-6Q&yl2R{?^r31p{AMLAxtr>B72x)0N3d|sIAIU+`LUEv!1HYup)yhC*WbTx&6#G$ z4W12y^joeO7kGOd-S>XZ^Cv%?qn*f^5<-6bII*{Pw+u(e9^w6a@T_3TY{=$LwNIY& zQ`W3I)(^Et*LCZ)(>R>yM=+27K9)!vQekBanG!eaOPXi&F^0|3XI!rt(-sL&eRGVB z@wWr@mM0Iz)9QY5YHK#5tm+hL>vsB>pJ#lDKkxwmX<2>E7IHo8&ATXht#34bUjeq# zf%+nG*61QsEFtFIW5G6$IeEO|zz_aZrB1_ypZD9 z>r$trFRBWg0Ln*P;m(TJJvrn3n)Zp;1E>i45HSAg|6P~aNmDQ)j4R5r=Q>71liRDCNo@0n?})eecbM z!h#>UF1dQ5S!ORqw z=-CoQKhR|#LBZNUJ#ux*u28O^f~&=(2T$Y zc+>RE#%r?#EYd~aj9WScP8w&4Oe>PCGvmHy<4D%q!w+Cq08@Tvw)==w$MvDmVXom6 zvM_eVIGlF5i|GYbsN84L1ss}9vXh?$$m3!!-1SRAlv3;1u2s3H^9aZxU9fTeqfuFs z7;6OecKhUHH~GikN>vWIqXHqUaNp*Ne`BX-j6KRZcZjqN_T;yVOfCBg^#y|YyoyPZ zwDYEadMy7OHJe|l34EPz*f;=8Vv2^^HH!mrw22y!OqZupQzs&Gn7l0av=nSX#8eeg zzZ}H0Pa)TUm{VZq4_sWAiHx&Va9GOu?m1=kqksVugv)lT^pQcj-vbeeqnRoxr_2;= zb@t#PoNb9_a*a(EO9;Os$M8sQ183S)&afUD?V*EUaQuIZ_1(JSjm2Sw7n68K7JjJo zfp4R-ZstD2nk*ReyXMtUO=|}?eb%tKIx?a~$}VqDo+}pxrN`Oh{QK)?F@>QG@{x)t z(l4~SW9}(dI7qGovod4~Zw84FsX-8%o0+}Y_|dzIcozgU}((-2OZqJA9f7QOjNa6(ZIYoO7D zMTWP$DKhs-@1}cEB59TDI6hpoAevJ7INjsD-TSRWi1$xgMfYt8lOn*?-Gw;?px#;p zAP#;zc)i+tk?82HzsMc)u;CH$5sc}+2I+zIh8yT4^3ks^f|F*4X`c5%7<*zGim*Wz z7r8#c>~M|W{k$>#PZxf>5Vt&!RLfY~Xmu_x_(;bpzUeWdN1Bj)YJDMZ6jS^xMw*g- zL_<&2ZXL}uqWAALLq|!^kJlQnla?ZXS~+;(=XesuKR=QbRjT>)oQ>(e`(nORjaR)i zK{q7OW&x_^{szjfsGxc|WmREc8-t2ic;z1Z^J?t2CT2T|#Dz$wa?_*Kd%-t!Ja9n8 z058`eC0tyeAs4@f)Xi|$Z?5U-san6c2Ad-4H5cywTcWAn$#rR()zyX4DSh9^wsw9| zbQIEKY)$he3(iFlVs9#bB(~G<%>F^SiSIR@`F@VWWef z*phCd<1}P8Z1B3)%pNWLCneLc?S#02w2e9{g_Tni`loIBrr?(u?bp@HGI^_IQ`5by zTUepA)*5DUb?4&cH+%Bd^h0iJ@m2CdRUsnemQOYqv2Wq5@>i0m6vi+{lnTxI_UaC+mLuV3`n-JxEAme}Y}%vxa}RUCUkOa`K%X7l4$VwO>z2ES z*s(ZqK6&gd_wn{CC}b}edHW`5cK9X|h%Hjcap}l+_jcu`F50yg? z!+C(KsNCi`@5R;Kqi;SBe5YBV_|z(H$8xr2fHj;`VzdbGG_>PHrK{oVkh$v4EZK>j zwAoh}X7uB=RmOQe61s7z@3Wti&Tc&hKfiIu7)PKL{W1F;TuPG>0SbLt^b;`c!a;Po#83~sL5o8e!XA3kn-MGhW{cCBrH{sg zB@xF6Z;D86IclRm+W)`h#yIi>;2Ac7AuZUPuH5&@E| z2JivZf|Any4ntTMkI{cL>yX)-X3!g~@}S1-r(%w{-wW@%K8xVErH~~H@ZVtOcdd;M z6_Q5_Zs^^~3p-vO)4FIeh3B8y2o0|F-`U?_?+miEPnj)0B26}(0}L2Yz)!USeed2c z-}pD@EEt`^q`W=Zf$`Yu7q|~s#uBbif(*B0vRB`PjA*1r-O`Lp+JgX(NlzD&rakZ- zR^&J+=edKmt$42SH!XuX|K|XIuyI(&+rc zud2v&x$pL$;rbKRh8Y2cMuP>nQFnH(58>U1!0_@j z&BxMzM9iRp0<3>5kvkxVv99{)kLb^#_YLudWPvf}%W~K1=M+tCi^qTe5rJWkh0(IE zfnP2Vn{Oc1j-A}h-gfjqHj!=L4zBDQ5YJXI=D?NP^uZteQe-3i;G&!p^mWyQ=>h?e zhUwZfOj|TGeZ>Lit?+d3`gd+_yq_kT{Qgc6nJC&x5aY3^pUJ@4Jx(ki$4Gm#ga<7(cnm1aLXD?6^tr2cA^5kSS?)!ebIPncRf z5BuhQT0SB8rD`_C!{D~cBkosZhZXPEtM+dM-e6X$%J%3c*o|?~l37nEDNYyvM%gf! zv3}{D9A(dOxks_Ni5`zh3ii)^_bcQg-j;of%`VQ0v+ei?kmq!KdIsbZO+{1Q|D&m| zUNS6`LlHleDL=U!;#u(cftjxHz+q?NxRV*9Sx|Sa1r)Aw9sS$=8g$Kn(>iK0)6s82 z=^GaMOfymmccz&a?UIa^`-G@<)4VpQiwj09{3CKNBoZzw8nKfwnxm_K7x~rRFOoNI zI}V;#IEIWq$bQU|u&N&-8t`7(_)HXFnF7z3bBD=^Qf*YI{`?hnj{kpacBf0H6S=~Cpn--SLw7mN9E!&Epi3fLu83#W^og?9SRWPxyu5cdw zQ@?J9&L=py@(0>1{gs+Coqfc{HeR-aK3{T9L~oVHGRhRPnBc z{`VEn`AAa&7$q=xNRE+C!Woi*v&UlPur`y5Rm$Pl{!qemk6nuC%Ykpj$}=0>X=bx=W*$>A~fOB--pfa6j8@Iyj|4*m%y#QofGoCYe8LvOEgWBxcg9sl-o!J!-n2A!+xrp+15n6 zvY7-Yg;CQ0+V5Q;Aw%66J<1+duyYkZJzngD+DRVYK9=0@TcN|w*x5E1 z+fWGFx2HOm0s7KPEJcll5DY;ljR~{RH>GdE&bC zl(aKQhpso@dcuGV`XBMkVUqKtNZeVi%s-;eEwY-S826Q1&>UggZ4oB#%Z$mXcFn5R zpG+&WjL_Toh9Q92i~NYB#jN;+D3ov-o*(uO2T==0fm3ap`b4;fnnfb(&j!^_HtzDN z%O|TNjkadb@{C6mzXYy-6h@rhIe@dk1aYI-5Sb&2Wz4)NDgExl!1723MPTYs;M}x&%E5shmLBxc10rRnr*l$a)0)O_G5=t z>Q&7gK_F+Uu(KVArZc#1`+%YdrUSkWB;M{cc1l@@S$ue#IfycYei+paQCV6sckf)ii15ybEtsl!dTr*KMRmXQ4`eOQXbYxwyAevxKW+6cdx>Ag zQ-_DQ8bYVmg7h%%g9vK)gOT+E&>$1i4y%?}VQT*OV#Mn^SJe~q7snJ27SmE(?rR@z zK3%gx{?to2$OXdt`tx6)zLz+q#GZ|ddet@)!Sk_I8W`O-8_YekF2RaIe@maAIuD;* z&LA1NA=UC6_48DxQGI!R`Y^fBOw9AQy5b^3cyULw%3 zQmS}AxMre1k;wu;#EHoxa^-vfR_6NOWW6`KpFWz-d)dO97fi{q7H8B4zSHhlfwSrV zpqOc6dv#X-F{rH1YuJ<`WZO?EJVK1+gLl&OnbLnZIRu91g$}E(xLGWFUn?4k`|4<_ zP*285eqJ{mmXkxJh8w^Fg;i(f+Uj6nCWIZT>yx-Io3%+6_%TA2n6qGH@yWMC&{l7y zwr4{2k;N3=%u147;cbEX>)Q;C##9_|$u;00gxO%a20t~7O+>?V(5_}OvBs^@DgN^I zJPEU>%y@d6KEz$T_q8rmpc}!0R|3bu*_>p3`<8Hl`q_aBQiKCbzUsiQ=p+*cR`vvc ztJ6vsOP<|&PG2r(A427AGl0a4q)W~FWZpyj-8 zBrnI&lQPiCF6WR@V3TK=;Mv_{cq`C8173lcGv}1TQQ<1v@_|5}f@6XM;A|(;f@#BM48sb`{p~K@2?qBC?U7e&BE;!fZw~LaX$$({$i~>2JLKeyMocRk4skwgc%|pwz z_CmF5Dp4}Y!-Rc*h~yqr4UKM)6ex~R@#j*>CF&>R+lcvbLa+be@4dP>Smd9K)}LeA zffC1XBVU#^rarjDZ`WQ8NWi6@s>}QQ=mOeQLGOt-V^U>F z<1x{Jutbt9r>sW;XK!61r7Xq&&C61$C9Jef@PuhX4RMHV{T4Y^1W!eOik%Axq4>?VK$zy1oB~}*F9t2 z;XKj8`wi^gj62VaA|GvIE6Mj0CQIK%+a-SBjTtbPJ>m=L>0!(*6dLvzE)OG$Nc|Xn zY3SSfqFPpU+wFBjDE}8RrS?F>gtR8n*3`FA)$Cf0J2Y#KA=Q>xZGmSf&2h0Dg3rJ) zd<`M=1>+qKnwkD)@ipU_nC-Y$QpC{I$9rzih}vBvKzT?NWqMH3(-Un;^rDwk;;Gf+ z(R1yHS9PP-7wTc$N_OBxQ)AQ)c>)DmPbt1KH-}{}N#nTp$Kci$tK~%ECt?@CNU#NS zww2_;wd=qK+A?Ztc^|v$Eav<%=8q+M-Bj>q)MOR0G2oD8^s=qNHb5j}L(b+{*dTXT z`CzIpV`U4qT=~8=N_o|LG?nY!PErg}gJ<(W2D?CNaQqL9#tAV2Q$eZoP{)m_xgqeq z*}GP&V}{Q*GinK+m7~TY48F)3U!)o7RVRKt>A5JSi53MBm55f zNt;jsXheYa_JKftY(Kq8&!5iRCuSjI?XRjE({J{Fk(ED{{LFVCQsJv@w59#_li>GL z%dT)kw)la3iSzVxahuAd?}HHg>z300HZvQU1v1l9Kh*=o~Yyz88E=a2%K;)7>0|8OpH;Ec&n?Mz^W^Z|Zj^k=3t8?R>oKmxRII=y<@sFs$Nk8jX*wXC-<$EKg z7R%;AjepH8e*PnRNOQQM&;kgWT%W(Qq^y!}CZ9~-pug+=WaxB^NX#sCie#6~ZeXssgoEw|?Z>fPSCm zP($>S)l5JOYqX+r9xc3n6YG|NC3?ZHSD_OsFucZM@;JHRVAXzQR z^G)KxeYN8d?qCT@TeA&; ze`rA3!!z}nvp~u-Ob6s~Yi&DQ_Dy=p)i2E{B;%f`TlV*&J+`9kpKTO1Gw3+N~(K1Hzj;G!>v@_K>V$l0OMDua`Eh0n{)WkZNlD z?G&H22f{6~L4a#We@^*FM9-c)b@!U|vGSdbY+dNq0NRi#tYYM` zr0avKi*vkMDoTCus=SFgBkn_E6K^^*nS5lnid?ArScFTqH*Q{`1j1VpMR8||io+kc zMx$R{4V77IK>{0U`2{dppzuW>QAtPm>|I;f^qnIXuCyiop0MaE9GyHE4z9MQVLWLl ztmYSNX0J(>;e7mRK&?Yk(XeXr&~M__`t3(RVI_j&d(o5`>F1${UD9>(Qmw6dzu4^E zyaDWvXR|(u2d%l)%mm{zj*_Y_xG>azjRRa4QT!e1q<4E~MT+oqS~s&OR6SZ!?i=t< z8O)XMNII;nNA?burg$|Z1_OXozlx~#@PzJ@s>MT*FOi?)62v_B49XAC%A~y-M@ezM z#S`9lTe!?`c}|RmtwbHhWz;!j3q3R`ptfK0Hpv)ke@-Gf6`^e6J??SWLdRu@wjabz zYw1~LVQFdZ_SUK}5tO@U7Ij_~#>`B)0ij+tCz)d3jMtz4Lq&SPD%l5(zGb={+y6!723A%D1Rjb86JzOEmB@mJK;2tw_Pq=m)~83B5*h;|`6 z<^&PfwHC#$7uU{5 zBst7CwI(2W*!kiS(PG5hS$zsJ8$20*GDPX?^@6dY@s~r~K-K+(C|~tiC${JpDXaJJ z-qME|1M4rNc$KO`B7NFAtp@yER) zd*4!~T|CU7Mm}V2s2g8pZn^5hYQW(+D4^1R#q}L_D~ab`(Cyd2P{Wr+I4(KgriF)r zZO~{k>!3R6k6dQR4E3zj8F}NU!2pBHn$xY)uT;#|Ooq?aG8zIHl2Jd>*3x{riII9* zl=5lY{Y^}Dns=nA_c?s`EQ%vpAicHi1<&N_THB8=dRl+Zi|HEtsB=3VQV^Jg$rWb_ zPwLFQJssj^BPuJcTpVi|CuTkSxsbX~I*PT@%3IlZc-@ee6Iozz`fvrYm!#{pkb8FJe{U>9~!!_sPMG z|HI;0Lh_{_u$;1F8AL@#dCr}C5hP0izcRc@Tr zcNIUEM!Iw-lugga5D^-b>{oG5n)c%{6X$k-#sJLVWce(!KbsO~Rse;V)lJJknD;0g z$ogz}9JMJH{MXO+Da$4>2-ncV34!-589~1lAAiar{zt^1$rDF&d9*KZ`2Zm4g(!04 zG8imqdYhWCEN=^Hb`2Y2jB@0PlO;H5utx5Mc!1beI(n1gGeP1=)C6IGnPFCvjZQiN z-sUlY6t}<^AruHVA^SC61i1tagJaq%RYW6!dls+#K8@0A-sATGXMre*rqz$}pSolN zESKSMRmC)HN`sftuMbA^71x|Fn*@jTIxKkq%qsz-#tW=;_^C$37-vL*>R6PF!;+lr4_(>;czknab3xZocme)Uk;0gy)fVdNC2cPexyon;n zK&R2^@pzsJ+^8N_q^}5L(D^mj((Lzg&;1!8ci3D&!c=oeI_bCOD%3nMSqLV8Nd6;C zfbSte5x{&R;umn9t$)9X68@Yba^QN+@%K>gNE)v)A9XPjciVbHZrwI%GrM!~D$BTFVFLuxC z$P7etZ<}~&|50<^xI|d5f);sQ1FyZ|${2!Z7@UXQEoX?YX3-)zk*4Sd1=0ai-SlfY2UCWtp~%Df zF@F8nL4Rg%$9ei5!PhU*>~F1Uzp^L5-#}vi5mh4(_|ZU{vJne&nF1^dp>?kyw^yOs z*CG}zNWJ=$gA>y+-aTHc+G=O(JD*f2Kmtu$XIbELhnp{FCZ-}d=)*9MXz&-^L=4EJ z-7Sz475dF{=k?gNIDEuq;D4mkk7G|EpBpo;rFY}Dv9j?*aDW=xuiVAqmZ7&_6{194 zf5y-ALmIeidL2)zGL)QY0LQpNB^$fuTJZHpL=&jL?0N>=nWBZGr8T@#5iVs7ygB+&f((UJ zmspQozlVLGOF0QZ)Dc3<^=f1zfL$a1nu9Q>C~*^s_eUQ^b=|24Q|@wcW8K3KjSv)u+~1q>3x`#HUIFVBBNyK^9i+L}OkO8P|Fd z>6SmqH@W%}Bk>xi_oAiVyWz!Lb$lFNbhVEzpz5Qrh_J}f!;TqYyVjPrtm3womd_(X zeJy-ne;;e|9y`y_|96wkCDW%gq;{uSdG#Jl@xR39z(g9g(LgR?FlzyO3R9CvV=66% zBu|*m66VyeEa4Nk6!U_4BTfvaeX}@yPNz5v?)zZN6LG02gZ_bMd#`aBD01I1U3Mr> zQ^GThb&Pv`clnRX9;@wkWkMAqOJM|20|X>*OQzpcmwuMx?$otQE-LB;ypvQWuG!|^1se{VuGg2-rV7&f)w6daqtbO}o9y*4JCI8X z#|?ra;QvYYC~b@IQ<&k0q7@_-Y;*Msq|P|C_`T`ti^gOsS@0JsY&#;-$wt8OAJKgw z&jNFBQpl34wm(;BUKVeJe^U$9ovz{StcAbbS75CMd;XMGiqD#^{B-;)l-YX(2I667 zQ%GuTtoN7ShcT*z`$s@eP~h*h*qyMesA6-wY(bLYnk4m!o5X0yCnCNa{^s+lhgeQz z5`QM8o7!c*FF^$0%KO7|Rfpd-*M@uoApI0$HgCpx*kc*AwmX|6^Zm9kM!d+Cb))YC zf(b8dLPp=){4o34R~zIK9%&Gl^m(B{>tw2R;LVxKyNzPX7e@*>7vzA zCI-X;7q9E68%;|bXBZZj(%hHcDQRoO&TL>Sd5mk*&I(=S*3L8C%(MtUF57QAA8)T- z&Hn{OlrzSM{ZMJlb$RAC^p8gpot!{bOk_)IWfbhZ?`V>aiWQl|L2o`_#s0ToXScJJt} z`O1iuO?8`hd~H@c8_^}R<~01t-$;|#9s<|w9cQp$o<=!J!Q4J~;;bST5{YCKY`4so z=)#cYdRIur-Xz$C2CMv`0V=}kapby!Q7@$aBBGrK&`Ay&F|V*; z{`>(DRUa^u(_A+H+|;UZ(u=g?(di$|bZ*AMOMI;3WJ*GtgXi7c_QBl|VDl4;^pEY& zt8i+&7G`}JD;;^eBKM;7a@|B8gtEH~)BJ29T07;DAifyt4N^kS_bH*?82p0qV@@=t zI`232ajLoUtRD>#``%QcD;^%?r0;)FNAX`Pp%hKgU9Me3c{>Oyyb(H)6z9I~J}`0b z_lh%^7Kof&{L8LZ(?m~fJ?2RHWv#`|@8m5N@>9w$nqu7 z$=koi%$2QoF~Oc;)#AEP4@S|#DIWm7W#g{+JgQx3gRJghE|wG>_lE5A*ajuqA_7gE zx+#C78q~BFh2%lHR6>f}7;mBbs zl7mG_A4kOa)+0QThPM1%XYY54DiZ;e^*xvbC(_4e9|6C=YWzH~Z0Xa8hX?F$-3cFj zf~Aujmo`35;8b}z3Ddqw5Qg{h^+rF`ClW}sbjH3}w=8>%b6wwz=rvBrwEEq&+W)3z zjrMB(Gw$jH4GwLG6yaL8U(amUY9s2OYDc_{jvkJk<}6{oO2IM@-h)1PWHWVez(!eN z;JVQsBYDD6M;w9Q%Y($$;hcMqcSUy*?`O(c-E8Wbp8wJQqzL2>z#P}R;(`BZc3neW zp=4oneU<6=s!(_Ge=m&qJk(Yzd=&W_uvC`xT@HEiuDq$Pqgv0?tUAaQT8+dt%M^ld zK$wdIQp^w#5Ag8_F60DgpW0gDljnB!f3WYU} zDqu1PmvErRDQYz6{P!Muzcyk@Eybasj#hZNEM1yf`$K?V6()8tay=ZV&$myjB}4?Tu4oye1KZ zx7d^cHz(87@tW@`0%<}l!u{KxLz4f=vA&}t(WD9(Vw@s-wo01BtMP-HY;MWPVJm$6 zb@l_Ol8{5@-PleU+xPOx+w!yOAs6stjdh~aK^>XH;B#bnGhxX^v}a1!tO)Vp+q^0| zoaDM+HqdhI5{x1_O+d{1+^BkYQKqvkC7NuuV{=p$@4)yYk~5g z#$38_{hP@Fd#0~K5$Rh_aSjVCmI7*gR>7{^Dbv^-GH2}JWC72S_XHeCC?#|PTQuiO zWC-#O_B+D93NN6;=(lk{YWm>#F5*7h{Aj+^p<++gUFJh*;f=O&#mFbo!sxljwFyE4EB*y!AP)nFWYjI#@xJ z!Q`G8DyY!>3IME&fbfxY+KR?PLDQcsl-rjNnBzX!8Y*UE$c{HUGX}ZU{Q9=TC%*4l zK12D;NnMD14`B1lWuVJz@qQ<0 z-=T4M_&#lkBdB)9`uU-^g}Gm&CU;EVtH9xIkaQ%F0Dm>F%*59|YtV_oBOo1>-7YFEfxvDPk|C? zqj}mzVG^jU*%Q0NnXbdrlbJ*NA>bF++W-gdAc7(G@tu`oW{D`+Uj~@V4uH)jITv!W2tF@O+uW&@b7HeKA~C-VWa-V9 zw`U-3Dzq@sL~M?FU40lO4*>lNKE%Q1g=A{L4T zoWIbmcLkh(C0S6@D>Gakj4m~P&hDh`%#|X1OS;uBkBe!7BXKa8)zz6}vi)9vvgO$u z&{Y9f|7@?j(EVe#HFa(vpmKJtNAKN%iHQ5%xIO0cuy)=<6$eBRIM>FE$^Guko_pyo zxS8id+6eNXI7hLb*j<07^30epEtO$Q`$!z3+;*#(Q}vzcn5RE~YKazRp=F?c`cJaR zMVXg#ycyxShnUkn0dU>(;yBjy8oatvyoBXVsQ5dwZ%pTJGGi@N13q5UE3?p|AWM*& zblr$W{V%XQWkW};xQ!oo5Ap5AkuUq!R;-Uukglg@nj+kM;d+e9#C z4)32D1`%U=tIexz31^N%sTV5w3(L;T-LPX}KN@qt@{%_%4T&f09rhm-w>Yo~aJsw|l%&jq`r<6&G1U z!$b3&PXwA(Klbbww9XtFA1424ea4>#wrsFGw{MO1a8q1dhFWyR6VdqcXx%f{x+s4p z4*o=tw5VvHcsMNDza4EZJ>1s?=#_*~3m=W9C42Ucsbug@>_cgG6b@(sgX`gg>mdfB z(X=T5f;0>T9L_Yy83>a9nSKAl6gOrQ57J68sf-YD_>kpohr+11wW>2*35j>Ebhd7lFSoM z{NQPz{!xSRyJTGOzIwX#kZ{Y+0NJhpg@MqWr%}X$xaH=nJC!@`d`r^ql;)N%5q{v0 z;Ber;z_$QBcQ)!0OzFd3_@;3hO_t@y%)$Mb*9M5{7=Q~`%kXrHLYg3$H)}&{r*yKP zx-efH*%L8w!wWagSk7vbnrY90Ko+4d3I;JW7x7X6o(-LLZeL5=uTfjX%G2He*2sx-#x_}CZg(u13TL?oGR|dRz5i}s@}kL48l&B(DyZ|>#|8Fd z*Lz6o3;fqrBAyq6%h-O7nM*+w-bG0ke{7ewTOXx-=t4miO-HgBZduU-;?$u&kU6!= z${GctVj5zrq97nNE(BenuGNWEjZAc{x0{*PH5PFrth)M4qeS%?3S^e@!H*IdPn42d zxP`@6i<~DrAHyuM?gN2~x902`>M(~%eitZ6q|YczxdhIQ^Ol$Sa0yXBmVwGMP6pxx z?=3HBRGy+=PCaq_?ijmlHwTu?OSI9fn`qZ^(e=JdK();-Sv;Fo&Q~PwAM{=pq;m!9o zvE0}D0S7w<@4tjx*J^N5$j{O_=%&5SrlnaoA1_Kfhp`4UcKpw`U!sxm#l5ZKdvT74I01Z|h8V)CIphjrh1P@S+0cPYpB>L+xLrf)w{ zQIOK9&{TRqfB1@Z#ClbfcQfUzh@qQh{}J(LeLA9%wL7LnkJ)8p)(CIwKibmnDKjP& z&@>>qzpZ7=nY`4h6dmH9uCOh*V+-;;zo@8jt6&RvNtOjyfS#8z)rU$ND))P+DNPib z*3aEnxB2639PRe0#J=Z(pC5n+E$)rckJd z->l@YzX~7is(qM08X$WSC(*m?ci1=$249kO3aK=N3 zQBOhKBQ|6-f1T0!)V;c1&$s`V?YEHbFg(#@{?_Ze(120sOOLzelwJHX_(voUhhHbm z3bhDoZKrJ%s%=CtREw(JO+^0<{B`?Cg6X&V;~xH%oK|AL+dSD6dok*-D4ql))sh7i zs(SG`5?@jqNf1Bye%$wne{@7C-r(56Y>a?i4l`pzq#4>FE}in-oY+4Oo<@IV)&ClGir^$M zrFwMGhkb9-RWk=NhN4~M`3gt;$tLQbQ?&Ss)x)jbXb*Xy!>o)acj3Eu8i0|tzx@v2 ziMQie*NzgURyj{0RA3Z65POW*#`GB}G7@HHg)+AG_E()iH+okFM1U1wn|cR^CJv^9 zxgLDX6uzMZau&xS`acNHr(Hz!9xngTX31dXkb@*Q^#`6pTlte`DVDLb=9iKwO{p+g$)8Lt*;329@Cq}MM|I$ zp>Gcmx1|~ll<%A&#zz7iVzZxW-)iNHk4QeX2g6f4ik+!37UaBiW{&T4@aGvm7kzq0 zON^B!_sW$IT!0`sQ~l&jy`lkT*;Du?g{KHVveLtMMV`+xy99E`K+&L+p{ zU{AU`>9H3>cj?tI)G0Pa(5;h!(Z|C)E1Rbt; zKunt>Ln*SIXI;CCP7mQ4dE&-uWo4BZZEBt>1xrVLCT8lPGTz0J?d>S+=)I;*>6HAKy-kRY9LB-kwCbXDa@*&EK!bK%BNtS29ZH<90a3>i0Wbi@}bq= z%qYs@@7+|w!A-qYtWFu_Nl>JYj@Pzc!|cJqkv}u7wtG+zrCNW{NEAsYFoz87hpxWC z0%15HbYaw7L{lD=y$8;UX^dEJa%6iY3q(nd+MfoX^nv|idzF$ffMAzg{oQ7I)9NE| zMB~&&*)EPY>kx-v<}wB6v!6_z?y;XwANmFr8t}$QlWE?&XDGAjI^;(4{92AM2uuY5 zXrU?un4SZOa~>{H9kcyW>HWkVy{eWOpY$1Fn16ulJ5PjX(IR6KEF$I+&#E{D$>rYh z6`>kFunNZ0V(bYNf35|gMuV-5k)CVraY{fJ9IZ%+H^Y4XDdHyVLqlIw%j6$Px~a*= zEUb8_fV+}jKLyuy?eFE`wScR&!pq{)*9E|2D8i7XBz7W!z&%ldS~PK9c`$#N`1@mW zC1X*jy??MAUr@GT6;$ zuM9#9MGUZgUL-L#*_Eo*bln!o$jncEVRv_MUut#rhz(cV-9^iX3j-2@hK6WJ@nQhM zS)4$zgDLKV+>s9m`p}s1QVJ!}x`|2$Uj6!JsiNIyc@K3pPSjMaI|XVm>VsXueu&zO z5G6+?6re_d-=E{Yscff3KO&GrwaozdGCt2iHYnozwgo^I>HHBon;uj~o+RecoyO7) z+AhkxrY6j_P7EoypF^v0_tD0kk8tiU>aonRuI^Rkf-vcIZT1uH+SVD#2;{z}U=eGu zVG81KoUz*T2mF^(E%Jc$TELl&DIUAnO|veARjqI8WSo~+wqEUDVZchfx>S2(|J^Kw zzLmm82z(24%hn!T3s|sF!Dq68=OpwaVIrFdcbSXl#%*kX7eTMF6CXPTaT5lCdNg=b z%pB6IclEzaqvxIM4%Ql0k);vu`8;$L&2Nf%F-JWJ96vJjACc`5C(P@Yq8uJRqvY_Y z^N~E^_G}?m?<0Y3$Md%y)s;nO6|c?MN$}wBVQ~Ai*Y&ofz&2qGSrAy~KcLBhPeK?v zr2)!q$eKu`QXQmk7-nBFfLRgXK@0g<0=<8dU8{PGDBDgg=OWA2^8tS@`I}Gwi0mQJ zfFb}7NDt0II3(77unEvy9LBq%5pm!0>V?@L>ZqX0_VsPDX zplZ+92b5J`WUKl*jC#7761$O6tMo7hOp!YZye63#CeMm?XY7&anYQsGScDX7H{~&}NC%4fVa%~8M;d0maAQ5nmDZKQ0z^PKCBIES) z6XBxdXIoz^YK(tyxNLb&H-m<`D1kM%BTNH!Y{LS28-@yCqV?QX=P%{dfTh&?+0 zT6a@|SDZ)QmVb>+qd{e^Jq+<=@K1*`%%Adw%1}7W6Rkwe8Id~G#|y8`5FZZ>B7O@D zBFL292gw<`J~--Mt+$UtIJ#5f<-)ox@68#R*8dX1TdWVxpeKcMDF=FAV#auEU4K-r zoY}tu*2)5AP(3Lb8^jL8{$=BhuwA_$T&{|NTW_C8xp$Z?GBr@{IqK*VehcfjjHBZE#wvH-VP=JAT?QD@F zy+UL~YXaxN*#S591PEzWzA3W0DNq!{Rq0_G|1_oP_sc$6Hw?$p>$J|wn{Bii zFTD`S7+>zLZ}2yf(&njSd^JGy&a!w7;89Hsb|BC|4jn1%EfyYz$?OG#xThp3tD-hu zwqc91(2GL;_~L|&t$b*DGJ;m z9St)<3+bT~``D3GP?f$F28?|J3k2sTB;~=S}4f z)fLDBIIw2?*T|{P@S8fk9cCNte;@?Z0sg%Z8X%5Va!rq8ui9Dm{g*Zyqpz+)Yi+Hf zw@IY3H5L|#y7?1QPsSQwRt&A^Dm@{}qds6G2~a}4RKjjp+%1}Pf9w+88`e}QH7}b3 z>@BlTkMcX4Py(O&#l^d3w`t ze@S~e-*;to_q!<-W@jtcnufV z*P-G&fZJacVY>4vX0W(KV3^}OAVX7Dx|6>yf+|M)$4Q<}m%Aw%#r-21jdG*@z}8ob z(^+$m?tFx8w|t80Du6w*knLs0?3)%xY+*ro-V44$y591X{!fDMUe(t&f-+<(y?Y>3 ze{c{iY46D*v`zz?{S_vxcV3iQxU>_g*S&G$vy983sh5}g?j&23DM@H4iDun=W)V#G zOd)Eh%5<8r8u{`zI$ClM?bAuFPJXGa`rCa2A97nZT zvNNGH*O7=e>ITpsGPCu3m@;OdF?M}5_MFZ2A_VU&T%sQ8rd!O|j#cr8PZGO6;rk(8 z5c`e9$dBD=Q`s1a?%3~-Xzd6Z!W|W-OMVqe6tTS(`DOchYDM~3=|>4(8~0|TDvV3K z1&HP3eDI_1tr@vw1<&irvnbyq8X#e{#bWN_oY@o0tGD}>_H3AI@tPSg3OH6(CB6c3 zTP*1supJR!fu79*tCJWmc~{p${N;R=V1A<%W=!6eVZ^WJ87DM9i5N`}-NJg=eio*| zD(nDncJa`Tc|^;`?XI{Ufqa2)_bB?{1s7*k0F35vtrSjR#@e|qxxX*Fx<>({?&MuK!QM3|s= zTm`=r1BcO(wxTt@mIjw$nlgM~yxK4uky`|F#wETB;t7z-=I)3YV_;vS!%=EAOi3y{ z*weNtSz186cgmlep})=m62B;~g;h7k%rt>eqAEb$zkaK!l`VWF-QG)kmxdC)H_ns8 z%J1%-{iSMQr)w?C@>Zrcgn0qCxN*0gZ8WHSr_~;i`^3ICp(lH!Ph_A$8b8Ex^~(Wn zj(>-{%@mGio`>JrsoVK+(lI;#(P~aDH_&OZcEa{Q;Xg7;t$&|BRSP%;FHHAAxZv`5 zT};*f<=Ret04xBl@Vr7I)}3{{RW~k{Ltk4W-N=pOMM({{*0;lhn5zqen@~7|W9eK* zag5@VyO3+`8)xXQ>uB3-<90`o(X|MCtc#pLimQgbocWWXfavw}HixSB&npVIcD6=1 z_86I+IsA8Nd;3xawshRQolg5&zcDl95Bxq(0Q=@V00%roAo$a!J~?-KDB{0J^S}yF zKPt?DE$>IUr@JrjJpo2?F$0ZJ8^taWnB$bZG!QKN9*OaPi7|`?_mf+<&en@?LJ_Y- zc%yHBZu0I6Vx9PwDfITykF}IB_$T6b9hteT)^rE^h_I2+DslGe&tjXaYvwP3eYm9Z5~ z>wU`JSiR}S<8gE~iG8yc2^3h4M+>{M(=;S-!praslVjT6Gu zowH%b!-_0mTDVN?V(*F+Q|wLGdI$BMX5A!{o8DK_8{`;j_wBoA?(dstl{V)M81VjV zA#Tu}1wP^LKd*SNb7US4b{4uReD|)zhnWol1y(R^#lTUgP}0)^5Jj#_JdrnYD^*mT zD*QycbnpK-I?I5jySI;z5JXBqr5Oqe(%mCOy1ToC5z?bkq)R|LrMtU3rMqK<^hP=I zet!SwEiX6D*}1N7d{WB5#QFDxVU@pPFwwb()R%@XO9SxO-msJFV~WRhCbPVK?U8Tx z*%Ac7R@BZOV8q{Ob7qRsU$-6#NOlmr^&^Qdk~~-~^VB22!g4)S@52ERJ4@{yoWBUf z78rgdNhc~mOL5H2OU&`|Czp>Ji9#0|0b0*aeR(cko(H~t52mp0Dftipb&W%+(Mb<) zWh87?R~?Jp*aer1Vm~m|tvO@=VA-K-d^7R>De)m276ay&&#*Xiy$iT5yK8<-_&w`x z@~sQ+jD9{_@lu4>F*qetBlf+7SOM&|_i@hT|5fP@xsP8)KX;n0{|tPDE1MOB$=eB8 zmlPgJ_^X^XbwW@T!)|c}M-fkyi^}C|ZyZ7uEdP3YT^EQ&Jm}=t9nRQUsMpPNdDIZU zcHDBGAbhFpjlH4)!mQ0A)t|d7n(n*2r3Bst>mGlSjh^W!D_TBKW;567 z=l432)DikQ7G1)gZ8}8qnUcHbuSCT_tIQ9*s_|En|F~n=u#F1?dCz$&L|0xXC@dHw zcLfs^7=4Q$14W$mg7+KEoY)GUm8%n`jpyS`{w_4J75#u%eJuQ^IOpI{1a50>i+Yz< zS7`Lb(;3oPQ(*f~hYMZ(!mCkM^cU#wdR~k)%q$Dfbc7O{UgM;S$CawY_I*Fe<*yg= zHCH7L$zyt?3bXUupeV2O5XOc?ZH-1o)-y>PGvh9OPz5N-$EW0-Hh1WVd8b05@P2)L zOYomw+zPB?ofrWmOO2g5i{G16W&=AFdTICCHk0e}=#)a5lyVFEg(kBTdFJBPzS=jU zMQNa8o9UdE@4Pdt=X7T5WBG72|fFs_k)(u%bQ zF;w2$w=>ruR|wo~CKSM?YNv^rpoYQcRY((_rl{`WrW@#+M$lY-0dms2y9 zajvCG_yc8YVx!mzHiFP#(Ze**=FEPhXG6%-z7fq;H6Ope=XmT{d7v9cfg>te9*LDT zbwrVsjKAy#wpnzzrvH-ZLvDVYcEB_KZessTiC?R=b%s5cyrDJrAfx(}k+;bY65J4J zn>LvE`t-yG$nazqiHfJbtE`j~?M!Kj=aIDaW>0nUflR=3mRDp)A)TK4bSd7Z z^a<3 zQCk7t^;p^YN0ti3gGzq|gIQxHfuV0!(Y<_Z4BvaHcC|Zc;RoP)Z4tbDd|@3ZiWMoH zpr#^38CS$~x!2MIIUEx*0N1XG|63KfC?UA3qO6;ywvT}L<-xL&cF;0pU9s^pEY>e zw;BCwxEC|LUzFgvkmc!POMT3KYnV9}{U{Ux%C(>(&sW1XIui5JVq<6s4Ar&F;@xxk zdWzBte-AASp)r@%+~VKRP*v>I2u&jSdOX^0^E}`M$af`repg;9r}~@!an;?z1G5nH z10x%Khe0rQilrEUeFF}T>ACp9hU37IlD|{CfvSF3cK*9Tk%XnD|4dNKO zZvlHn3(b$8R@@s6Ff+^h&+xXT$&-(td=|Y*rJQLFVxIR8^QV#r4s9EI`9ZFCzn`mG zMNAMT=1a^SG*y74IGb9#>So=b?qACDuugY@--CR2p5-4Z?r&Sa#+9t#VT6Tx$51wX zvxYe!si#(7&rtEr4l0QgGea$$tUe~mrTfjrNB;?((uny>I00C*&vI3|$?OUAhhamq z)<0tbp}CM>@OaJN9c8J<rDpx%f~DnQg8?8KBI4UD{4AMm#sf_y}inQDJoMXQTt4x*(8@5f>9|4hvVl~<7c zv~+N38*s}aK*Th_yNL8rt`fjl(fvQC@JB$WGc?#6c*F zgZZ5MN3DQ*cHk9bWh<|YJ1pL)R3f;jkCANi2t_(h2 zNffGZzb5AR)eK8blG4$*BuoDWlmuh%=!9N_(SRE2RfbqK?0qaqU{us%szlKwi-oF- zv<^!u#2;949HXWY_d7)cRnc89ulxe!r`sW=4}yq-6&FrS_Tf5yozo&nP-_ zGI9nH-%TW8PpfAj(DH_2njLua#LzJf{|<44D!i$!t8Gboe!wxP(3JApN^KtxU1Fyu zx!*$_r9vh2!>m2$TL#s$`*P^Yspzu@iFQQt!-wo;gaInxB-Z=iBDa^C6qP9_J$y|k zjty`ikkCGodOQ%BsCS*dtvC$8Zy*f$`enuMiXtgNG|C-!dw;xeK;#1h3`@W@QE>91 zj;4k3&5Ye2)YApSC0CtHl!xy$IGK1~k8bFs@#$GB3xQA(3|4&)bSoF%Wne-l|RXwRRo=lkoS<4D~!J*Upl`Q5IB}dZ9q)t z17lP6C)Z|h{cp?+I7>qXQeqfr*nSoAmJS&_T7w<@xMma}w(uLlf(|D68y0Bhs3t*; z(C*9w08+g8|A9`4ympkh8FY}!nT3O>14aIKtNiFe8K`Bw!2uCcdd4Bvpa~}Ldzbs( zw17Zfc0xODn3K}Hh|KopkF=!UTX9j*+Pj833%jwmz#zn0b|Cf&w%Xq*f;f$-C>w0L z;q(4oozSlzA5?o9{$cS{w0{blcUz3m_U^2>@ou689LfU=d6d+Jewf>sS9We(<4VQp z*&;GguVG^a~5hVA*h$um*^N642VsiJ*i*~mQf*4$|BFC4cjVV^a_YJa%}(!z za+I-0R-*cm8}}=T3@V@bNHub~*CAX&G*{0NM%HInN44~3H@6uU0>{RQd7)2}>c=6> z2H1T`uF97}#q?+7)OJ@>l1`uq4z#~moKN1W*qp_9WA@!N=`xQOQrf`%ngbX38X(`| zPvEcw7zY&z{hc*6qj#^j{KZ&7ey7MY=5P0}{KrT}S98IyuaABF2~@}Oxj#Nk`D-Cc z+k*qG>9YXv3*pT-)y-?oasBjOqCK{UY}Tx8=6vl4g@-h6zh z2jP$@4A5^a|Kv{%G&r$6RD zU{lgK)wilBy1`$J+w+G{wq8EOt~-l^$Bh;Ty2zxqSaG+XFEYe--^oOh4jymM{Q|1U z$gn4fY`!EsR&$$3gI70iQUXE_5q|-~TOEpzn(Qx;{(m4xLmuSPzi<Fw*< zSVirYauJWW@t{rG8FL{&G;GIWJwO(Cm7v;)@mE9-G+P>f`;kr{n@_F{;D${uXv}n!^R=;*jWH6zOif0|K zQ4MU10gZnxc}r_ShvuJ0EymPjy6oZNZ^{?6hLHgTCd3H*r#4C3vCB~j28hMj2gyQc z7IQPS!$h}sp_1ibZqKRX{TOo)bJof2hnDbmPq?4ckkCyPaQe&ik>}CnCQ2Q|mA@In zMI;=2LEkqRM>dev7-Q1!Rh&(vp2k#tsTqd!ZDPeNoL&KdYQ}YF>0!XKg^3s+lN zeMsh4AMxZt#PaRz{kc@Su%}F|RT-5%XnK9edhbrn|3nlCwFbU>XZ@$4m7++|50LSq z0cw*TPkqv`2MKhRSl*@;>h{JAMJ#|JTtaux~LY6j{M z9dw5LshW}RbM1_=r`dv&igu6(xkE*CzwB9Rd8DcZiQ+bCF#vYjy(qBJp$*;EiD)N6 z;O=--fCnO>6~fyAVfCkY4UG*>g?bHZHGN)m($(E@^e5?=YDti>z85<-Q~pc}TjM%A zU17eYaBB8meVrKlC#qwAF60YJ*>d->GLP1VI%e+ha4Tba+!$%*dtJn@)|l9B2QdXy zqS>}UCpW4{T!rXw7urNe@!=B<>h(74>OPZebXGZ5rMe|9O3oc9v)Ri@@)W?`+qwXg z*mpkn)kI80B37Kf{RblO|L99!JtHFFiPRp`o^~v#M@&XPkZz|#Ge1z)x9HlivVi~Y z>~Bk2%oczGUN2liIlehlRZ&%n45jfg(DcitxL8*r2$h* z+~k6P*O*5E_NY|77}ghj{~ z^r?FhOL)T6?g8(W&dKdP9nj6z@Wc3H_7+2*fUj*Hj9;~Bwq3GfWT!(+V&>F36(bBD zzc)K>iGN9N7B>7pSCUeIN&rGKAl4=Ohw;0|EMG995&&lVVwaczT!w>Kwsr+*-r>xL z8vp7;1U-#{0&{7e%;n2h(qEO2Ko7$+z;*W%j8F@SSFk`t_9l6#CyIS(MU@q7S1WT< z?1k#1E_eR*5JrOQ0{YX>g99i;c%j>|JVsFcx-pjH}o zKMcLU28=h~Nc!pwP<9jhKoPSK^l+l?J$I^)A7Kz^e=x~1i-=4KN8iwI@8g*rzaUMouoce+_~V5pLie7b76t^3VDDL zw+UBJOeH0=sP@r0u^E&LumG8(sQ$Fwh{o+rvxo~i5#j3jgiXp~7&AXccbNC~Mjz;#{ z5&2M|lD!_E86CAb_U#nrv!yqELY6*28P#_1<$t!K5zeUJPVcIWGpjVpl&1EoiNIO@ft$ z0d=#NN?2fYL2$6CG((=($TJp;LepNT&ED+YdmZD1~nGQptRbaDlTc0wLaJ3cs0 zr4M$#L%gZlQc~D%3NMGxivSx!lR@pf z>&eh_wv+a;zwa78S$#2Y4LQ}Y_Q+9-A#fx#KpT8o@p0;;{oBOC{aCg2D2nJ5bhvX* zI1oe7nJ^x%d`Ksa;~ZHHYDNbARPtlKmx0ChJqav|papD?tFtPPi(urh$hj3;NX7At z>F#|Z6vPXy@ao^7uCAWh3OHrPcErJW-+5~1nyojvMYPj}_19y}o2(%^{a|c8sNUvo z!A%T}?WNWApsM$YYDG_#6GAE}{^|Mj`*d|B!H`VH-6rA2n1<=fs%=JDVpx2ydT2Zt z2up})$f2Zc3#x71E0n?n1^h~v#6~Oa{3$~){$sJmQX8 z^dmjF-hO?dm%pHvx5vNnF6?rV${D4d2FvbClRSM|pUtzPZ3IKv=U%J@?U;P0MmL7# zPSsGo8=Gt%09n|Hf~Ft13x-YOJ=O$ll3l%Bpkrj9Kcr_t->yzg6xU%1y&G>4(@8^G zjZCgZp?p1|#R3zA@P+oqzFr~vQ1yG22sQ!&A`OY}tet^G5RjK|sqzWN(pA;0k;cu^ zY`cQhHah_-gj7c@Tc^jFAlI&Ju;gs;YKJpf>|B~ffI&yVfs_* z`?AcmJCy*v?yk9wWq##GN1m$vHF~#7u5`~$WB&!yN%e4bi3EyjD)DdcoPMsIE0`qD z9>~bP-=9-g*!~ZMCPm5hrRm`7=2@d#&xnyXYXhJL{~1DSm@C zjqEDmecDkZ|aVDFmn*_^) zQIopl?qb9UtJ>nPh}u48xYN&c;@O6M?IVq7`MczT{ko0+vEQ-bMHz z)K(wUdxk4~plkJc&42pM{;lU39r+W*Wfh(+pZ~Ll7Q}w07i2Q{K)I^R+YKPnYtJ5>tvgK z&_O&w%*O^IcPjYEr)>Z6FAnp9D9P}+;|95eciPW)V#BXV5iuzM%kd!xONUO7i3cEK#=OLCKgzp4f>k*WoXCVe zq0R)SB2@g$4Ui*g6-?KiJs2PV=FibrIe$c0@cFPe-^)4>4u%7~^AOc9wJ>4B_L-+K zch-l}3z5+aX>(5I5`h)m7CNeLCf>fdsM9T{XcgbZPWp5yRH{ehhq{8J#a;u5UWoL) z2qtbqMioRx9&rlp?ZP=5z9$U7f*8pC+H+_yn2!q+>s4^g%De~qQoo|`x54;Ew*HJL zwJJU3xa=l78vMr8pG!1tr}@TYG&z3$i4%xXoMsNuf2g1`;|K1nor570LLTsIn1y~r zw){PI6i?!Oz0bf;Hml(DFdLO$c^R=ONUcr+|K+so-YO7#Z$5(In}`JB40oi;{=|I~ zZxyOjO&NkENniV$xDg$H*RhxV&sUDFI_%Rb#40>1P|SvXWl|x+*3tY81%G5!brmOu zoeW(z>R((ya92co75uz=lF*lGz96*MSZD@F_(G3sd7Ns;Z=$6~xq^Eq;CuEUEE(@% z!VF*cfFirQv!dc9{ele7l^|moC(KW{us3q#^F-J$O36TZfmqCG4GM!lpYLjEaqe=$ ziv%lLvV?!pOP5{91RZz(2RhafrgBLi(u(^9W$VDfS&`H8qJ%y;1BW0+||_lW)g0ze!cxh3eoFJN}!=F`fSvUur3bMw%SHy!{bHl40@MSQwPjdj*lP zTh4kjEF2@+J{MOwPrkdTmy)#5PYb`=sox6cYoaUi4&!((PF<%uXvyMrP)e@~-6f)XEonTXvqDxYt=K+^3(L3Pn3g z279uY-K|>UX4F^wZYJxJjqSehkXN3Xs3tnNQwl7R#;j;y;9bTYtLHE9lPFoyr#?g>y!VIvB4gf1B?hRRbq*OuuJWKd8Mep?{(G?D#wLAJ3w)wH$Ya#~P4A#D+u^>6S zyJVlin>x1*@%t~0*G3%5^OM=Z3O}MN9Z9D6gtQAf{tPL`kCHoPt?*$2-oymZ6=>S> zA4XYgd)S}W#Is0|k36~&Jdr0J|H#1sywUgt9eV|9Q%cUyF6GkQ)eidDRMxPY7MfV{ z=g(Q}f6tHi!2-^trP&I9#BNP?s3pSd+mi+y*v0CAeSa)$&Myh(M+G+i)!l}L`BOr;4zS6E;y7!GuPx`eIaekN-ovh4K+(8BS?K^+huDLcakPtAG&Wj9{}t3 zwn5}-*Jm`Ah&cKt`D;Ayg(^d|{N+7qRSxv)5 zf|^f$i)*@V1zo>O)@oXn()OeBe&4S{7?^P6BR(B_@Xvcqo^zatFk1pu1r7RBfz9D3i7w7M>)k+rd%{x6*DWA`oSv4*LlSdBprTo-&G6G* zczaE7w|S#d^c>p!Dy#&*K55a_s40chDM#Vuo7=zMFD4p8pk7%Q%f9@jtDNgT+kWD~ z&xN1f)ip3XP-n>5lo&4m$yk;1#bLeXiS&D=_I$iD4l>B;>Z{B~KVVC4B8{%(o;xvl zBY+iivdLqbKxM;{yh@&6T2>-uWa$FtgUl489>RF5ctVgH4`k#x*| zO!5dMnaWrQ^rbm3;`&*x_a7*6=qK)tR;~?lP^~S)*ZZP-*|a}C z#Z8RU1f@+$cbYw{4PUuKtMP4tA`mytV3|I}GzCZ8!ku1AB^+`UdWjCe8moL|0Q zpHyxxuJ}QsVxMH;%8kLz|6-`)Q`k6EXn^~3@C70Z?OgkFIR7&3clNsH)y7&|9sf&_ z0yQSz6KTcj&Le_ccVVG2bkwh+mDea9XsOVysy4+?jGbAIT{i4A#lq1I1BnRx3*Yp= z*r7|}~H~U0WCbt8jBkyT5{B~6qK%RTyE5-LJ zYINxM@6_UTOEg5Cj2HL2IJJ+FX0$(%uCeGh3ymnjU0bFV_ zrrmX0p(<>JKe*gJTM5CJZD#-8vSH!uRRXgt>+U7VuGUJbMjA?EdvQR?shiZ>zbX&M z{;cAI9x*JR2?il7uF^yOzPI(YLxtvU!jvAYyz>4E71Y$s=S<~BDz(o!teG2lvBiCE zBm0(FPKc5AnS8TOEY?Bfb>*s|zL3ERl+X1`ox%rP>86+Uc-=Pwi7h9xkg^S6*@BSV z@=N~CLOMW0g=CM8jbe5G4G+LiuXS7JTL#Qa;mMgpnfwpPkS;;GMApQ-dZ}Q&u@;Gt zxbP8ch#Y;q+-`yz*4kgH0|pEpw7UdnWZAZ86A*Y+TWENee!9@QM)Q0gn<62=cBhN) ziSAh6qYFto@bqD3ERxznHDZ5ryyq9aN8`IA|~ArI>ufZ-2p%VYU#5+hdfK7d7A*WaPgr6(&RafZt@Y&rV!*X@!4Krv9xTwBALz?U;5 z9H$JUHN7Cz&v_~KR%OT8=tG=sp`Ff4$sOFX`soS-zwwS=!04W}1>V-!kJ(sb z8t@6)g}B~4+1xHmH_{KlgypHhp3{m&$V~_ZFd;U>vfk71AtxhzO?KbML+_GTDo(T> z7HUHTazhxSQYeRsFq(@eytOi1W0|WHfJsHadG4x(jjigyff&OfzkM;5S(5yiA|7UP zBSSMUIrzl0=<8XmKUTgzyr6HqUp+IgEzGP(#nfI}3S#LYrH?`y{>C1crjHMeb-GLg z8nb{6<75YB))<0Y91+um#04UtKPI-{PL=1gyW8@fFFClsT%yq&4@#MsPCP$iK8bW7 z84!J+trrUy0}w_bG&m^og5~wdO(NS80K@%hO5A_sF%@{2WqsY!*`K2b>XnICbczd6 z*Nk1Lzjk_cOha2o;a^i~$Itgh{N1vli2`pPK_J<3U%S$27cEui^TxgHa_Z{%mg+l%)awbs042 z-=Mojp2qJO;YB{+qC>IES3CBq9A*)9Q-LpvGG65ggW+e1C4#;j{b_UXh%#$)-wjI8 zt!92Bxz;6kryY_r0FT5L)@i!W&8-Jusmowsj$Q_;0fQdQnO*O(9tia)orB;l5uA%( z5@b3E#HjNws)F!f)+>Q{2<{A>bukiqxyPVR664*UqL4}nvFqnu=$#)K3B|e7K!vZe zHe>BlUtLjqr~P6mc_`IXyxQ{2!ODmI6+H9N+@fxtAS^B+5<`19`qcGtrA4&wLm*H6 z@!qUsxucrq2qikU;cSD~qUOA#JJxolzdO~73WqOBZHD6uBo`kccI8K-xt0^wU=HeH zblU^1#vd|4OdQ?EY30aNOA<$>0hc3TjT~{>_l=^0CtD4rSHnjFMSL-b-@{Jx;qMls%5=W8>$h*3C*vR{X1rS1oc zu000&bHe}=bM~nYLZe<%z(aWv$+6UaCFf2T*4TlOC1&LQvxFf;wq@ee3T>UEW^^mF?FPI`&4eAxC~J7 zdVq0@oOP_cf>@6kRkvo1KJ{9*&z?JE3^?2HDAEX8mT?^7Wz4~&a?>X??pH9-cZMQM5 zKsV(vqjBJc0cDS`U!Mv6 zjDZ3@5E|)Q7rv~*a@OnpXx@&qSf1*mHwmocnSWTc6}(=CXsZjo6fZp`sT!Nu5r8-= zf0rmCVI934#rl*L5-3)>xk7l8g23(}3^c)f5`mh$W=PmM=%4&%g6B`QiVEnxl=YRs z(|)3xy{;lUa`{uq@twnzIqLDU4Kv~&Vb~_we;|uhgUP6@mytW;*@4$!6eB}$S51K^ z>4GJa`wM@ZJI%H5>(3YR5v4|m}-knXbOW@3`eZ*6xuIF zV4_jIn2#U~t7>Oid5UIO;ZbrkFccc{f-=DNm1;r$XAi{Q3l>!jbU`zf3a%w%^zmyS z9R0mawL^;VI zd1D9IadlCSPqSKS`^%>H@3&jz=;AkI3pFmAZ|RNKkS6H2>IB6y+uFW`cu_KvKV|Gd zPi>vJ{(#tz)ye1k2BDo-f@<6T*Bbzakq+pvxK&Z>!-59%O-FzlDwPj+AAu}E zkcvcTCO#%LoP%vQUjc&ai2u6>S5!FM=hPD}6U8&8Bq@Wqe#~70ppy$p-fpuZU-R+e z0{v~t&RE}KK6@DZezea~D7dFC_{=a!ISrcr9dAaC{r=3LY9WwThaR1f3?AXq^oO4$ z>M}+wkt5!Vfnjc@O6@ua|B6pWE;`)rxCFl(hoGpF`RYH=6HW`j`WxFO9SC^&G?h&* zVg|oPWh2h;HDnQ_->w!LfuB`_{+rgugd5?i2BQ1(wb(nTNz(LSkbG1k_~H%KlU9kZ z9tMYbWp|S4lJ%rMXgFj*I^6l~A$zzxZfEvpv-MMAUVhMHkp=Ph)#kSn^l%9Fw$`#C z%6r-C_S!b(9y_jUu;NR(y}OU#SKZ}NpItC>_Trr?`kJJx14FodWqB2gO=Fi<8txK) z`!t^fIE%YfC%6xXneT^!Qnw*M{?jj4u2Mb(8#_lto zNnIAuC(|-uZh^cBP(q)h%*3V9ez@NV=HTNbGs(gC$%-SMkaxg}??vWq6vkTYfn3xu zkoyH0(mqBi?ryCGO8Z!95@w&`W_A>U{Ivp1?`cwG9v*`3A|iB0<{U%GxuZw`SyhU~ z6L0kPnGA>~P_uTD9zph63&+r=cM%|$?$BXo_XIFo?tiH{?FcV~5ia#wwfP1Ex`!lrrnv-KS(pi=wrY5)Jh`({x+E36oT5_h9`{wFr76 zElg(+DJB9-_$l#Xv&WBqB^KWnr|>Au;kqeWWSs3#&tWZHx*&$x;0rKTIpl znCIxCgPkpptO}(_Dk*_2D$Vk`xtWT2y(-m$n-WN34AX69F`ohJ?`YsceT$lK3hqLr z!JsNg@^$V!*V9@wH{4_pGLPfQNE;F|%yj?+R5~{4> z`CF+#u1hfSxrZ2Bd(TtG(&K~b*KUMd4(@?=tjNlt!s!igf1}bU^|8%3Y@^JT;;hFB zlR6_W5RhP3V#U#ZvH;>Uu>ua|p?vZ?*@HV(Y(-x!|4@6VbzW1VedI$@$`kASAYqmc zHJ-BtxWF`=fiBXW{4k^Gs?f2y=g)J{aS9;#aEntjp_0|xFqM30Prq|URIrtl(28oE z0AzFQ~ES*{Cwt#yQjd=m#b~2q1fHW z$kD0Jwn?X=U?R=US}{at(Pa(EbY0P24eLL22=>G@X66}@}%dQHChS3r@0TM&9=jzTqHy>IrXpyZ{oVE1h1U; zQ8R2ehCA&*<@S;2zC0n6ei%w^SrJNxPsgF6)kIA0Q%4jQCTa;bk0{cvT@;vee z*$V+fw?{^dtmNL#7oqwKmFGMHRZX%p{bLkEw3zXtW)tG)rzS08xFXPd&SNoz%0HAp zODDB$mRRG|eobc@LKWD}14`*_k=A>eQr5l=h>w80Oi>8y*OrPWg z>EpcpvC=(-rE!Zr1ioUezDn z-9v}-kW}}-MoOM+$%*eRpqhit3W2wnGy=Sym=|b6j#s94;L+AUqjRXIyGJ{Fu;i_J zpac~SFo1+s#a=Ogn`Lx0nVmeri-+ai7@@d|Tm6%YdXkQ$bDjgE0f=bG`^o%4{KvAP zcRl985%ZnN<2Uwspx*(gC*MU&*v56!!4MEW<9kYZU>+F<{s`8n!fB6fq@Qt@oz9)T zdX!OpnwZ$1i5cFU?@Y|#Wz{(`hJKprhc29VB{~XRvO}u#q{_9ak;05m)3(4T`fYfm>O)qOu(Hd{fqrY7Ezdv%L^1l1?j4JI zOuiF@+sHktF)fH$iYl+42!rOgRY{6d{o$l5kqCz2d}wHuqr1W?D`w?ym%hh0HqH0M z@W(`7jH}9cl7Lq#+v7SC-xZoAJW@~kNrA-waw?&i{uB-iNnfY?X;D~S*UUV@!xs-E z?;oY5*c-df2Fx1|#K!yiv%ErC4?R29YU58`SMxf}uVY2@6WfNGl#&*t5-fKfawxf% z>k{-yj*3*8f9MVf3mBG1h>U4Lkfa*o#48XLMLvie*_kRh>XUVv^vT2a_O zZAl#GV$wCrlvPkl{Tb^bk&6G%8!;Ai9}D!xE1(FCmKUP0#N$BuRYgo5wDL5KP+2Zu z&)MiJW_Yu&(3Y+w3qF?@-3G_nNfxnorrtaX>mr_NoZJES?8lo!anhGY{r%z#+t5FAJRR~LNkeMJMPmu)ms<3Q&DCw8st`)K?}J2p|BKDr6&lpj zMb$%8;NqlL_@3Kv+17xFcKW*#+_-X`l>YJ|$v1kcf>~Gt6#-STS zisrEl8kxB%Oi$5wNS>HGjAK<)-pTDpF2nj4d2?lWgvJo&7tk&u+limY9?5)&^+r~w z0&6HB?|yqJbHr2;9KE_O!FrmMhvyMPY0%ivES+raT|xyvG@58C8F4ZPD|O5@h&@;2 zi{?Ap;cpI%ZAUW$h+tydRP*(?2Ke$jXB$ogPypfd+d0o9T18dj=%(){q)g}%upJr* z|7B^An%nzUXJ!wmU^T{kK3r+8eK~&@wHNPbs$9KtjPOjD#25Hq2K5lN{Ph};q~4D% zG?{2jdU=!vL0pPdcx+4m<WJAcOqHpji->WzTPEm?hdHx+Ssw$F;NIMdps5)xukv z=21W$JdjmZBwZWAPy9UFd+GNG2=79$^wc$1qU+S#t83ax4EA$nLTMq9_CCMst60J3 z+V$FBGi=uFT^#}R21;zF$b&s?3vtR7ogfGIG6k#|cN5$Xd6ui&h>a2tx3O@Q`?32< zKb-wiRK%oKjCtB%vej?9Hz|CGzaGWr$xfdvO_Gs3agtEnXt92en!|sLsm@R|gG9$w zL*Js~v|v_!-O8ZN7EUlKNvdS+EM8(&7zYm$4PwiyShrI>%lA zHypz=^K*fL<&DflUh4A2m995L1#-mP|H=B2-c0GQc6}}m&Sa&+8I8-DCu+VJeq6G` zW)a-46OZS<6oU+Tr?S(1!kU^O1Vt?hP8r{8{|8ECS=RL1Qs&om@WKqt*Z1jv#Qo`f ztBJKcx|*g&$-b_t!c%y(-J|z{iE*n+I|qw9XH1S}pE^E|R9#;FofmY999#cKeQ@O4 zrLslHVf>#nzHc2hOXh)ZJ|_!!z9%$cZ}>3wC6w@zrgSYWko?zcYfekg{j@ijw}l_H zpQt=?UbIFJE@cVOYceFQ3EEvMsr~w8p!@;P_t59Xm65c8)CHWgepc+0u(x&lv4#Ze z+;j=wQDlfcyKsmGi^H0igRpQdH^5UZCsfs8tm+1S9?3BBOi1M$` z;sx>Ns`|>@G!|dMTQRl?QH&HdkLgeJ8B{=V;NaSwU!!OM)01x#q1x@@6$DstJTn43 zE1~^$^>{EpdQ%}hB}$4XxA|3!tc}DI(?;{8KV4Eb(?$n)P1eDj-77F~qIzM|I?wYP z_Ta^LVnntMS;@Ew#}mvl@Tvbm5x=vuvsov*cn2OJt(?c+J~m`6#{SU}r=5_?3WMR) z+uTnos$7AKB5C_y09}Hrc32hvgtTx<_SJX}6+B!2^Thn5p++$+^UM?RUw!2^cr?YT zVVs6CKf0i{WU$LE?ybdj74Hgc5|m+G|2A%?@AEkc4YEaYXeL2N8)FSH2v!KoPd7l7 zaQj-*cwWeIe(w2&Hf7#v^)!wXe^d~<2{bC-RHlx^1q~}y3*zn8xh|$vdL55DmkSrJ zx^#>mPK+*a`VTG&YrSG-T){TZAe6s%>dt=V{}PqHU9o;v=4k_t&aL$+H#zE43|Url ziT+;E_SIsDni*~-s)yJ9de@>tR7u|2C`uPzXuxwMF}Js{Af)WLvrfF@rWIAHINB^c zi1Cucd2-?Rh0H&ViwYgeRS)lb4d1SSnbu$Ga%i$lF@Z0n(Gq`UV3CO?(tXqjQlg`c zvWZC)*GhUO%h5!6vBoGcbUR=*eEAX0)P{PPw|e>|!QVjYSox@wMq+E+dcQSQ3w3_) zRJ4@p_s<1)ZPGG08J@}hE8u!dA2NJBAU#2dfy^1`9g|3;ifsPFnb~jCX?shPcUkzI z%j-DGS>lafDCezz#G4Wt-CcNAhuv&k%=6==c_B;%JifhEXTc%GtNf1?FSX=uo6o!# z?EZ|o^k~A#E9`$Ya5;?NXQ;Z7cd}JCx6f{0m|Mgx>43L42{t7I$m7=$vJmDu13en4 zcBkj>Ww9eVSNc_zaOoLEjlVKtywQrMObnk3#@IixU7KXihh7BJ6;b(U^0$V!wIoTY zot~>qRetizmGehT@Z&{*0F}GXGnv1(S^K%12u8&51LU^?)KqIOURkA*xr+a#5@n0j zdbWJj5&CoV;NdIuKtY54dqJi(K!?9BaWLPIvr9&`AwJq*{nDJ51cFaS zrAz8w7}q(NC924)QnFkb44#RZ`MJ^PssI0~r7r zw6=9?N`@_lVxUU-;xOY%1m#G-Eore9YK&~*#m%JCniAD|Km0=DNpEj~_1molJ!sK) z%TPB?w$Ppkyyh-#XA1llcX^jq?z-pT_$h;-_!SxhhQ-Hi0|t?q(*1WTs(ZnF)PJJm zCjML(q&D(R4=)kYT!F@ntppGEetxth0+2~v0+mSma3sYpRBs7AoC{t{p5yL@a462cm_HK#_$@5npsCD zT{&BgL1}hXWj1VtWpyd*`X>%H?bckp{6sqNrUOkqlUZ$Pd|b=y-1%|eo079dfEti3 zmB5T$2xJ@eltvRgjhfX2*rS(jf>~N!$LEUb~ z1@vzK1ZmB-kX5s!6(E3+S*mXxP# z8AW)a%{ll6k%7~Jd1PcFT8uWDKdmGL;UDU0n}`|LWaKB?nl9Gt1uPDGUZFY4S$XPM zQp$)}dX}lLt#C1#T@r}?T7~LutY=9EN28es{Gj>q=)xpm+Gz9kE=F1kq$iih#34&v z+g$Ra?Az3RqG0LJh+!}pM$T%Qt@A3~ED#R-m60){j`tHHTR?|j{dg`9T411{$8>*M z0M9gB8`DP-q;o%%(f$V-CLmdMH&tnpUz`tE7o0Bi(JT^HS(Xg zSD~NiJ}8;gucV)d<3by5JzTAjDJ1286G}xHBu+^=l)Uqrn%@*i^@<(5R$dC*`GFR@ zj%N`ks}}^#o9~8KIWm!@?}ckxhII>^i&F$6$;gL?j|Z8=;o||_j{%dfmBN{0Brt6n z1jNq4kZP3vm|leLpBoZYw{H$wa! zXkm(LZ%@>=hFp$w9Nq(z18Scax|rXkFJFRGuqzA_sfUL5VAoqyn9lmEAgw7Ivcv4r zQX_pKK8Indn`3>xn?EWO%cqNJb@Vvon7dmCF>`3oI+NHc+GqdeQ5t$q2>l1j_TKT; z*#2FqJH98~bCWDq;Q~Pv;p8 z*Z)TQ(GxX#H(El}sL_WcdJvKjJ%VUK^lp?OdJrVaAbQkb^xh_-_g+V@GwNW>@1Fm? zYuy*Kcwu49IqS^x-Ot|pV^{upXq*d+*Qa@xS3(`?;gRSRg}kVc-LN~vj#eLe1u4Ha|D?GWa{koJ-W3AR7{=p{xXqcGT2&! zFZu`A2#`U9#foYgaT>FJLqU>Q!i)F!2&w4AL?_Mn`>se%(x7H5spsch;Z*1;d|>F|qR6Da?eY{;2e) z)a93>06AA{Al;Ufkr`%-H#s92v7on13Y3ipx_upa*b;nhx=Uoe|D@@0lCI1sGor&p zZ8!Kko~9D2ED6!V#0*)!*v@@7z*(h>OLbu@W&g_VkIa}5-yQK&&ljp_)gt-%sTbyh z*Hy~USJ2haWct~6p~uCsdz3rzTQo`DFo%su&uCoUD67YT3C*vxV)Hf5v4fl7?WKe5 z(!h&rTN1EI2U?aMt2`XHac_XH!VUwuU%A)iJNmOh5ocVczCkrwRqsz`kISZT??C=? z^i{%kyKW7DpkE&FJSm(W4CmDid{*sv~OzV3F;x+9YH zYoSbnk9>Z_=%=?K?-RO_x;jc41r4&*Q}?fnRHjJ#TPLerdFrN|*MK~db&aPukvPO- zlzt<-ShZ@!QoV%L+#*P6c#Y`jLQ&w&RC(fUq3p2r;%dJ$Ut=?De`9T+e&JNU+m2X8XiB@Uh1yUU-Tj>=TfXjD1X9nG`5m zK4>#r>zn_Q%gAT$aP+4_;{`za*!=Ws63#kX-O=1JUTE;v#rR2zb-N-zfp>rZ&Wo7I zUVnzR0^upBP)5)aUXDG|0Rgw&&$!#Jkm~E14~n^2+p4N-QW_~=sT;@*$Gf=0Ff(Kgh`t_dl$!rL>G!i&Xu!$f1iAkAVCY54uba7rk*udMO`oxO}+T zX?esN^kP+&lYj|PthFtAvG};iRL5eAm0S9FWpj+^z-cg=e0-EEVKaMXV#K>H zuYH%VqtL=$^n5DitS9Ekhl+47{RD&C3iJ;J)ioL? zj|eYcEi7OvO!8Co@RGgQr^@2*~CtubZ$`7BiU^Qf0kvS*3>j| z+uTk&=0r1@Kh-W_VZhmt&H5_Dy5l03JWZRbUe8VXr&8jlsMK(X%zABa#Po10# z_D#$_8{e1|IkN82aqtdI$V%hu2z<*P&`Y&JVEd@pgVn4auT@&!_HQT0M|new!6;fp zfaApc^Uk(OXK&M_$*ZWD5NVgHKt&%bz6DXNdhtP8MW$@!xY6?|sw*aMj`=df!F)&j z?imQx-VI;83nHDP$khU&(Z(*3@?$E;(tj}Q-=INlWAeoQHvcCh_xV+dwA!oNirIaE z_(FJZvT|&N!=97-B1;!94ZO^*#14s~!<#Z$aB8RTnDX3Hi!V0+7f~q;C(|!qbTmF8 zU;VuEhh1>EYAcfUXYnm>Qp?}KIp_69D-t>Dw%1U~>0O%L3i=+Z2fj56BLSYv`9Z(t zGZtKr%LcDVCTjU+16A_X3?1qoGuR#Uw$}duwN$}kptFq8myvnVBZ@=$dk9t=< zZ%;Ci(&sRPatMx|q{+JQIwez+=)>~i9-)yn^Ce!@&**Yi$gR;uYJGMz)PK}~U;|fU zy&CrjCEg}7MMJ}n@CzPr`yyWJ%I7Kx+_k;Ux%`Z&oa5u5@?pQmm#`f14D64(3&ob* zyu53o2Vc5ksv<_Q`VH255s5LlPe>le(0S#)AY!tQk3S*C|K|}L1U!OTa)}j>KlOTB z5WL*4FIznlfSx`CO6!>ZIT{{b{|9=@A+dPn)e{IYb4s&nf93K9Nc))!PIlP8n-N@m zCf^5c{15a-a5yt~JYO!G3O2Syhh+0Ce#1W(t*AATx5ELSW>3nKzMpqR5R1QuP6C|xsXLNITJu1Yy- zbRGd_k3#AawwurVcs~}CCKZxka3L#SAw1AoiYA{UZ5xQDPEGk9Gw6M2ct+q5GgSj{ zF<6RcUc-D(fL-~;+YmBaJ!L-xQkmvOZg`yM&4;=)$a1neWamFnl`)Eq_-4B<6_Exl z{STy6hxe+4Fpg5Oq|iE9=OIY9jbtM2|8a&n+V6sPd1Oew$>PWGVa0dxFN;I;WiD7*6}29&By_})4L zmTQrJ@Oq3W=BLtbiKET!uMiI4-qH!(g$P9WCsybw)0Tim2^t)$OPbhxE`A@31qs-% zexs@~0cmv1g0B)!%k+W&9nfKY_O2Yup$Cb#i0iizfL(8O2V;*vk+>QK@tFvdP(pX( zzF&5Rw5y%yMn-gnK!O`jlxbnbaQ4R~?zuN{6Px~tBO%}&IjW0<{Q0kREwE>JALjQ` zEQ_Euc39fQ&Q-W&w@$!@J8oPK5th@{4sHjWpOR&+Vd>4sDeD-aV&52c+Y_EJW8ODL zZ#25D(Zhkox5mMvDZ&4Ms$_sdpoo2=;K2~SKFruVV(BOKNsl$gPub}lqUc3WgUaf^+s3E9_;c>GpbYH@Ghl@JB6 z`|*5I%Wd1!4dp{#-2SD$=23BTj6Vrq0*kEWPii(GWsf@9&En_`=$$I>cP8Xw( zB!wk(6I2Ey(vHsFFB_pFef zv7t577+Ng+$4Qy_cMT?pBh^MRuBUfW#X$**CWa1aJQ@a$3GI2v2SoHpb>USeVdezqPz~MevIlnE3HoTV$UCr_X1|8Xt$Ftax!&Rf zIbNVIKUm4Pqen>&6R?)Z>MK6k^Z6i{e@clPGqTgw&V;hfZae1=QXh^;-OS=iVzY|W zP?%i+xJOm<0hewVF_e5ahZKej)zRHS;pJ2nw`ZHX&q0QMxx$^(k7I5ckMEooWij5y zn^-T5e-T6cJ|zNQV9TIQL}9-d%nR{L`9D?CQs8o)8@e4Q^)m9@yhJH~El4nB;B)kY4h zrQ_^}dxt=+)CJ<^;dgO?67u-gkzlKaoHQV*U$Ed4zK*$DYt!p8f)TU_jE4KG{Y2ib zM&6jQSbhN-q~>+JT}6Z@cuD__n=L*LtQKbOf8vgZO4Ho;c+H)Kx0H1!z;wNs(ZV#U zIM4@r89R2#_GZQ6SmVZKGT(ACL|{y1HAR^c9_=oki=54vbjM$J3lSGv_}$&2fn*;B7-(7e&Z8oR9 zc9l}Cfc_WI%im90J=r`Atv(c-epaNK$+ZaIGeE3_2>*E{_dY2+eDF=cU-Pn5CIkuG zNJLLp;Kd-`(yTK5mN}xx@5Im<$sV#Zi@kl#eqSl7-EphgZ4U#@Ikm?(j5jLTB)`bx zCeK|9_ARw}6@b!v`8t1B`63ro(gmV~J1$v6UcM%cD;c$be|SIu^0%hLvz176nf4b; z?ELUMG?}E$EY9sh;T7QzzFa<3o-!}NYrGJW!bjtc9I!e(SydTihr&2ZR#GDB#Nd|= zNMl4SbXYfuIt$i5#iC|39wtD(bD`+q{btf_ppl16nVf@bGvqtsO5)KX0 zwfTO39(KMJ@9hd9Z&Xb1SonpG$HkW&R0S0*_}%A|fA)#(j-P(kBPx=j^@xWjDJHPw zxALdQ=Z-TAD$M2x1rV{0F>Yw`S? z3axW-OZ3ONom|5`a9y~!cWltEC!475;2{Xr&a~%xsY90(dqw~obVzOU;(XXowgY9o z@3sCk=_)tL^}LBEK}TJGs&1OAwK7zFvbxgvalDf!6tL8_ z|3FlG3k<)Y8zvp|^WX)jy$r+B)y_qwiwYza9u`rDa?K@xBjgSl7qn1SwQD3@ z-o0@R&y@du`{MQ9Yi5!6Rs)utr|OU5O_gVUQruL;)yMoY^=@c7OPi)b75T}GI#$?; z zdt%Tt$a}Wf_QrH?=0+GGUYzdFKXMd&evs=l|JK9932wW4AizNoy&yMF7-ez zy*f`n5oZZq_~nld$By3)T_EZ6L{iqw?S?bER-~sCWba2CV-+{Tw~aML(H{=6n2~^2 zM6s^q7)U>*6~?wwn{jO9n{Y0xS$U~cBiul5C1EI zuRDKW_SUqb_?oGES{sJHd4yPhmu3hPg+Y$A!PH$uZ87+$!OxdB@zafLB_QlP!oMt_ z1mk@`Dl0{=uL8dyhl|}Mg@%ast4-qo>%Jz6XG1?ex;lpR@XG}HpA#1?; zJ^=^T-ss%-=lvkAqGRQ4$B{bsBBQ^oLcycip+>!cE<+`(wo%3!!OW+q=# zJpYI%S>xK~W{jZjYn`{1D=*CI_11Nak9{$lt%q?t*LXzXao-!U<~Siotzi6Sd9sI7 z=axrCGv^;N1hEUx*_>=>2Wq9|l`B&@dC=x0NMGhv_ppgk(3WW^Nd5wQul4D1HTqyKuP zz4YWu(dTX8wTeWH%FrPn)_re<5!jT1hgvoq1RJdfuk?k6W+`9crS>cT z&uFjNp5{h8tNfao@GRymNHxzv!d>g^I}*RCv)5tE2>;&akPC$H^Jv@8YgT`^RJwkd zM!$&O3at)Wd2E{+D_BJfUOzhdpB`a#_ebbuPA#5 zG?3wIgT8{mV_L9en38)!R6T7ktB-PO1~PD#b?8h%HH9=j-m5An3PHvDIo*Rn_JuCR z2bvb8(c)QgIO4*@ld73At}a9sz06wpu9IB$z3;BSmvkIo&s7&*kQ=%<^_G8(V0ET41hk$YmI1mC>=~&x{7R`C z_r)%TU%Qj&tSoJ0u=yM>aKQt9G zk^p`q=*4H-OCGRE7FAoKS&mDpj^>$WXXkE^z@|bP2~0wnwCuKKaF#96f=G+)%MJ`G z=gz;-nRK)W*`XWj5Rn-1I8de};gPJ1amVXdEVai6X3+0-v137x?Log{`2Y990}&LO zz7B`==L(2@)2oua7$H_?S{oy(Y(MV~|ARPq#&Pew%=cP@iS0uOzo`C2>ArYDW9Pp5 zdFf~Mofr_TNUvGo!Tk|=@~MF!h5{DarGZphV&j5mA-%!lFnJNYC+=%C0@W zs_X~N&6sRmDy1L4*Paqm6>1cugcYCWk_mIp8GR-=D>VAIuEA4GPm@n0Bg4nMm}Lk{ z{orM;;<-IF8ugSa{f(T@WfAmfC4^gGFieGcFC#p_AD23ZLG~#Eox0$KaT!G?)mr&@fD zB#uIB_o4yp{G-tqGd$=pUZzWncrNF;-E}ry~{VKX`xs}0L9`;iFoA-8y zIB@1E%%Sv31nOh!MH8_+C77Px70IW;q^Q~G^LVFz*BplDwtnyX<%N|&pbTP7x;08t zv@*CFVCad41A>VvieybaT0sw8hD3zanOpb39--|*X4ke89emcoBzre+{|)k*j1-N3 zavCgda-(Sds_n;X7lQ@TOkt@Q+6_q0>cZlNQWTo6pK%2;CE{t$Xg=0zT)I$LR8_i{ zehGDin_|+x9_O9$Mrz#pX+gi@UGg1HuR#~Uh}D`fjL#+Xu26y2XTwxS?PeWEh-v6$ zgi^Sy8}kww3>t_lR`mRnJ$3n_AD+zQ(s`YNBYloCGQzOl>h9w1qv??im9`39` z*?cpQ#?z54P|806PCguYu9xs`O*UuzLxCsHZD=S!!Lfn&Fvhobm~{&}o=A#Gd^20P_~>W8vDyoLL{XZkfRd*1H=9eGb+Dj= zTvU{j2-aZCE67ol+DQ(Gt6A$zVV_g9m_D!6p}?XCeUs828rZ3Q!$(B10q3wAATt8g z$Wi5EjZuuf6drvnC%vLf4mTtKh>#NF4UJf(2y}8r-9X7z0@x&$eEW|b<_a!R^!C^U zCaD(o|3K0tJb)eT6UJ&CD2n=k(c8!&z^bG5;<2J=!LH_J2b6C^pFXDJ4Jy7pyyUrk zGHc<76`gZ;bp^L49PeJb1Z(Vftfj0H1QMWWJ3H7EG%FVE+hx$g9ld&#_KY25fwpMw zo%NlF^F&IsLmelJGaeW(>|K7EEY0Jm(BFa7S+lgjpVz@?qtrV&WHCBbSn{d!MF<6^ zK^LtGNP3~?u8d}w9(B}|NpP7n5Z+GF9p*K#T&zx77wWuc&3UHGc5+yO!dXV=5FFR# z5aFhPLldbI*Dg*b$8xNd3k_Cni|rJN;F3O_chVP2m@&T6C^F{Z1i*q*9VmUh@Mc7p z9!v1>C5~@~6Ag~T2Hi^UwezA!s){iQuGG5?{zvewA(ObY%Kt!Kyv9fGhzLTOjuJoI zML}#j2m>AOvJ?c-l#|NUXh>XT$0uPvbThO)N7L*vl^$s8>PvELVus>RYq3T^Fb79n}%j`8$;!ja&Y?yK7Y>IZV^Zv&3 zbgPBTv?=MbPQ% zz2}hKSVBvG3>^$yssxRe2CuFXeF`Q?oF`sk%rOFO}^d?6XgV#@kzMDPQwVKvIK2NK6<$*4rNpTT|5&Jg4{ zD0lM3Iw{q5VzYgLsJnkvTxOGaladVNn|PRAjOCxkiC|WHpiDSU-!tHsU|+9kdS;q? zbXIqH2^k$J7?=+F5H`}PGii!Fuvy*)|FF)fgW9i#7(xKJ-+TQH0yLrv!V#!$d#f?m zljl3xld@vGzti)y*>?K7;Z0fydMv>D-hs zDl^XtX2ygc$TK>&&Cf8gqnw#?>X85r)i<$Rf5HzY>K@R5=s>ye@pi=w8FO#m(94~J zwLsOtQmQbq?FH}!7AGrvFc|~Fe_AAPF7_Fa(pc=@5_<1cnT$ugsbUw*CDr4g;*r7j zy$ki-8`X16ekIXGf*z%N(Mg>Gcz6XsnsjG>J4?Bk29DK&Q)ywKt6?Purh~c5Trwif z9&cc=^$zHhDTbszb-1U8%t%vua(@TFOA!^YrC>zVSpa1!R5o42+`BwU&W-k-qV z(Tg)7`15>=q59v2+$9k84s>xxCrdXOZ8Z2w;aTVy3Le4Tp=$!XIva9IjS4~iRM4r% zdC9}Cu%C(~dj1pe=v0qt6qVwxh^hF3*uM}B5G)G{OLYg)mExE5yU!ipFGEAAkazYn znLhp*kI(249>eV6WiaBFD;%+4f4)qbSjDVQlW3?jKX=xz_eAm@Kqe|uokW33@Q zQ*6HOuvUwH8nyWiyXU!=fDl+knv3>j&Nfeb&izzRr)WyjU>Bb-VqA}vP-@9->((aF zbU(XS1RPv?tjq(R?5dYk<{*xZO#htqZzeDGLkJ!TW)!21N{avN{1B%OO;D-}qX8G| zj|dv@zZnjB(uAC-kZO(^T{n+Zhj1sQvb(MP5m6CRR}46>{I$WgT~Dlxl`y7Jy`9jw zWJXHjMFq!S8X+-MP)A%ObnVBd9w25EB;bH}wfx&r?%f~5eyYp(&I8NQ=^K8yTf$fM zJTq3eoey2n-34- zybF66|Ex~cBjg_L)`Q_vQ*Afl`aHJK z@=sE%=95G1XVpwt0qEhP18iiQ!gMf{hu}@^y#qSuB|%Teee5culXS_I$-{=|yonqM zv!#-jMlbfj;Vk6Rbaa*aS5IIS@o217*1^67HY|*KTJ?(Ql!|^Kd%Dw{rQ29(oFl2& zzJcNN#mlSoh7Gds7MstYh3_p|7M!F0HiW2h-6~G;xOuGN$x1aiJFEp{OV6)4-BFp? zo{C=lJ?<|i&o43*U8gr?WU&Lv0aoV^%1>P(?RAmDAg(+dt^cJ@%GNIEPunquXUre zF7T!qEtCCIE9=RbHJ}u@46Bm9i7m^UR15z-uK?pi>wUG@d!ueuY_fR$<@;J>ql?&i zF3~h}o!s|}64SU>2idA_?+V6SSnpO{JG$lGmPZS$%PFNb&f?vG(5HHq?B=@+ZD9lA z`qV$;$tq`0*L7g4>bI(c$`ewp3A_oWk+!h$Db&mC8}ACgW3Yj?eud*JxqqO#)`ngm zvEOkZ<0eVGB&(u|sRtX6MWnJ0;iivy8=6{z|H%&JpafQNBXd6CeikBh?W_xVr&SuqMhN5cT9hjG z857p1WZw7ZI-av_$iswt;KzZ;BH41&VSF;d^!k9?`z}jsTIrv7F8SCDrz9Mj+p;oV zwzJladpW5)xC-NXFK?1hH4XHh$#P5&xB7efa3c>{;#kaU{fu5-0i`kOW*Em_~IYUSL|fK+YRBO2<>p$4=5wXmwYsldk1y%H#FhJbTx9(&pQ(HQZA!=nfI# z#TqM$@7s2vt@A;Aa&I9%OfvMHO^DviA8jWwJ@-pFn-CwI%GfI0jd*DTz*RSg`xo=3JP` z$eTze8);+2w1I1)^V=|f)Ez0N%_^-4K+>Bt88o;Pq1+Bva~ z-e1B9_Iht#&$@bh`f8G7^~?MoF1l+BD%OnBnmR&W^R{Wjfmtg}(Q$b;T0z};Te_og z(cGy$X?di;sG|L`amq3%`7|Bk; zCT{)Ce(C2(PmYC$8esE)JwMF{+&H6L*G95qlGiqyh?Iljr#6a#l|i393|yesn-GDg z5bP;96~r|kdAGLthRvHZCg4fe-Pqo);{(6`;rzuy5XIzi+D>lCwZgr*fRu@}=bb&F zqYZ6p_fMW6peCR~C|e{ad2W??(_WunT0I^8-vM$cC6Rx`e$Q6IyZZa!RKIrkwD%)F zMSoBF5t1itG)iiGIfx_!tJq3BW<`xXJ$)|3KhRD?n--oi0W+OdZ43w)XcpdAVIL=c z^-c)QIP3EN!otGuN1BcTf!#;OT%xj@th;<)(5G zkdIz2r(7~V(!)mg1t5-yaJ3p%;}ya{TLza=xUb5TBSS&;(u0on7m;lz$kUT>)o)OS z#81Gig=xOdcB#l@5m@Cb6zBv9J|P);PtB+StCj6;FbmMy?Jf?r}JRx z=8b1(b9pXha2ri91t`0-Qjkgp*6=cNE!-pcX^?Oq>=?8`XL3qHwz zsesq)$z#Z!KggL*UzzCtzYHRT$7q4V?>Ul^VY;V-SB*y#33YfMLNsLm_apqgo|4~R z5i~Sh)BQ$p(zsFec7iB%A*5fcNm7Oh0ewn}1CRmnyE~Ni*yBx%NJ@9ke`^&3 zQdgU96Nq3YL}*+?MjzH4qOzw2LV{PB?YFqlR&|AuUrVlT|gEFc?sO zFLKUCui#%}G%dvM_gUagI_8b#V`Rv%pd5)A0~!pKRMZ~+r=i@ zTkoRlrXlrJhk-`=q^8J^Ux&n2NBlvz&w*RAClT|ws#}zJ9{U(I+I7N&dELVzKP+7E z8tZ_Y$@A>Ir_b0eePqn@(}!f#LJs%8KpBO&03wfuU+7z-fU5$ihuF9gktbw;-} zM8h+kJxtPcRIJd_1!-k$pS9uE8ZWedGlGQGD}d_wr`@6nt8hd}hg}YdZ+a(`suGyt zEFPh^E`L_7I5N`gvmDi3g=u5@rs5@?!y=Te;|sz^@LdL~A-sVEw-mvPN)MWyGM&Ne zkK*a!UHr2hb(T?|Y}H;1*6@n!`WNbKwdPWyDCcQ5&9&=Sro45)NNuH zE8?XIXN5OS8R<_R6~_hEB&fXu{1{G!pRZ<==uuRM4YwZwNWs`RfEtj;kut8a^ZQzA z#29baPl$>HvI>oxs+l#dq#LQUe+t}5fFtx6wimYGt$@0Thr&W?qmIm7*H5T??ey>R zJFFL-<$F{N{|!Uz_h=@1xrh`R`|76`L*sL;>Cse2!naSchIiQt#_NlEF$-5ASW6Ey zU-to;tjFRB#&5$1Z4?DxG>z9q>ZRBm(FBeUGU$@o4IL#w%U4MPpWMZIVqNaS0f*oN zkPGm^(XE2QD(lU9u;3gaPQDpuYbRLR?pI8)u2C!EsPksaE284Wxd^_+p<&O-($OH$ zxnSa)Pd|i66#N{Wew1@768H%HJ@XbM6Ua0ZD9d-`aqFa77Dxk4pmv1NC~)FDS!@%^6%@(a$tM&BZ6o(Iu8V%o)l}a$ zBHZ@=12IT7x&Sy?ForKWeVrH>&V<3eI0e+(L2nw#Vc!j0r#x03ASvEhUfQed)1(GoAnOG#Z0M z=xp%z^v!X-P)enT?+(&%5ANz(A;_Gs94r`z4JrcwI}*orZTl`Ej$5C)n9ooEJkwOFUZz!xPOM2p;>H`DlO8>wccgkh?gn4%){I1N~*+4DPL> z^9>&I^?93e_*bfm$VprNrIvs|R81Y%YwxpJRyAdaSRSC)|F5`Qb>r`QbWXqP!eYOY zFnpqX;-Z~8kbTnST#ssHb?-7G?$W?K!d?GETRq_+UYme9WC_>yJzBc|BTf(Xo^f_!a+q$!|TnQ|jh1s-d4{r0~`l zH|@{YGaA!Dl|fcT5%_dU5_92~wxefS1|`pY%p3DTnOKvP^&9y%r6!U+s$Y)=lcI-N zzGd47GX_8OrMhM8v80EO`vny~11huxR(&BR)y|W4S!z8I51Zto~d*ZcKs!^>HjwZJ7b2nAS`Ggr2?qg;dUL*Yi z+&{}2*Ivz5!F5@MhqpGq9&drL@sY(Kpvx+FAcX@ z@p^S~l0v`P{&>hbRj1SHTr)xo9bZ|Py9=(f{Q7X(>t~<}ahs1FW%1ex_2P5ZuYawW z8q*e}gcHmFd>1S^xCc^e8F9SWX+qKoUeH4p#{{yjFB81N#FpDb7=*A~zY1}+MT;xn z{yd=!5&BAcq9|zj{4S}(CWiro=z`HU-u-MB3VhUr$^7LT+p|K7jz2*RTwGUNIE!iq zY366FFc%o~37d(mE>93%N7ih?O;3_=vh`MS8KonghMqX6i$3mtgvuVwmaU+vb zvr#=oBbU!~Jsy_NAW8o4g=awQAG!N9Y5&^?GLtfT<>MZaicBAtC+?p4%!nP0oMs#o% zz!uorSdhSp-QzFRzPJ=8o@LZmB+K^8eG`1l?0?L}!#qlFYxk;%zovOqyPNS}VxR6wsG_=;+EY$W7sewp6CjR85e&9_L zf8ehZ_1c`M4dbhET8?0P$lY^(QNG2x9}+e6t(N+}7eNW9+na?;{sO#BjgjN06o>|T zwj=~^1a>i1>8pn2zu)kM#Z7@;V7HIvxEi)0Y-rd5J<0Ap4TjYnNgo7;&?xh54^(;` z+xX$VU2a_q5i`vQYI;edbj5pPq|ENSWJKPmi@@Fq2oGi5u%Y+fMjX^!6Fzu=^zklx z@YkJJ=3wlc;~cNFcz$KYjH|vu{I7;sw32?pMZ?30zPcfiTrsWfdR%y07S)U0oji`1w(ca~mR&lL_Q{$Ub*{lMV)+`IDAu6;h2l6`ZHl?%ovL zrHIcO9CjxO8beT#pnX)9Gv4QLg_G-AWy;gu|3E@)N&WsTZVh4tz~N4$t~!P6BmR9p z-W^Wh;B#R5`I(6Ft@@ra+n{oJ?{AbITg%s&#`{mX25?|OP!Js@K$v`h1tEfWTJ}2+*%#>{B~Ys zC~kgKs558BNFm@!(1&4DUccvTNM;hL=Nh5975OEyeJkUz*6Pj*QFc>k@BXN_8aFdG z-ukskbh=`kJ5~hUD(%}v5gV9HPw?!R+z-acvk@eCTmGxK8l9wLY01==Z)NwuXbJFq4W`BPc8TIC?vWAw*2j+S#Hwrd|4E7o z`{{`;@8OeGeSNL(ZlAr-8o_l}U-)h&9mUPks=E9m6aY&+KR7S*FRy>FB$XY%m1*7& z8TaDH9sUQhoQY-fBCwX%11R?s1340JLKq^saDS@=9vib4O~)64Ciliu3<~Z>J?yaud z=Y0Z$c0Syc7z-+-MJPKW%F9_?t##@mcG%#qHPcz`n%r=~L-g(Qt3<6_{(ZTN(db9X z0WE^QUeqFcNBY4-3{U)%R%3))rAnL_okb&x0~!y%>BzuTBR(Yt<({ffB*ASPn`$R* zYXIdmKH}T7Gtz!r1}SoHyWHH&xNv%_?eyB<7n%LT@y&q8c8U$&GP%TUZEI5rDU}18 ze90!Vo&gbWve8}EQ+I;D#*5Gt!!`EaEEJXbfsX`9pBK$9nvZ11)-?)W(0{9$Gj}+# zE8S}jTX|QU?NB!NM14UP-$6cLqr5T)=^&}mYLL#sF(bLlYMYgo@msrej{l&QO?n?R z&=R@p=tJ$85t!lC|5NlPIK_uy_r$2VmuFqCv5X}aBX`Lful|B1Cj!vcBIjI1!3MYb z$2{Vn!x!p=gyF*8qDKLejWgp$wj0W&O8Iz*;V%>^F;P9I@X9<7+XBp6pjaW{<$_Xa z;h&C(+5z4yat~#q!jntybfqf4^$rRI#W;25TpW$Yb88Wv%`%^1eP?ww7;d85TzAX! z5x$Ro+M}O}#vRYr-Q>Q4k_jXKW>&tMFO!1X-n)g7q5-1* zpN~Rq^H%N$UetV1;dOs3%bHn|OVOsg>{*sfT)EI6;Xyg96!7uZcDR;<7`3c;K-aV3 zOzJG!D{c66pu~81d(k&xj>+o9K{V+Vl5NKMJngF5Y{l2l{6jT=`hs=C!dAT*d9Cx2 zd3=5T?_GumtGhVKKhvJtUkNOBEe!t(XR?(=Ugc7z7^2N!vg20G0MGKh7r)JE#86tP z$Ky}`fdWqjb2zvs;kVD%6+gOBY=3S4m{X$ZlG4Y2^ablAs5XO@6!{or-CfT}<7l(= zj%oTRPmTSOlB&W6GyO^G2ltd`%N_0Q3vexP`ZSq`XN`v*@E?RKGxpY6D#8l}iWdg# zzdXvn)Z^Y3oBYh3{o8(FC7vTQ=;3mE-g@S|-lA7e2|J2*{yW=@NT#I6sFRa(sY6-= zL)yCz#@XP&6!z9%i7u+1E9^iKB>5uz>hdK^LcE9j>aGdAc)@cpK~I3nTA6$t>)^0{ zTQ~^^Q~L7sc|SFXb`}vq`?38-1}+Au?e6e!%%6!<{5BZt&cqfBpo~1p2?4kECUJn5=K&XP+R)%ACzbK?LK8*KWc2xR=EyrP-#F( z;x&jb9t`tOZL`?>PFW6%-_=YAPkSb6Y6lMFw>wVy5oM6Z&9fv8%+MgARxSvun^K znJF-)*&j@)vDdUxe#g6xfd2>DDZ%b8{0BOl3ifoiJjt0!p#~I1y(z$pC^8F3jQMBz zl#s2Gf?nv^AQ+>9x$d>_%s3sr~+k1Nki%+^JWe-{YF@>Jm$q0omgQ&B1DnOK< zNd{YB2;vM@!r)yTCyScvm)jf+S zf8+dqEXqGf&M3pl${o-9FCPz($tB$(c)+2yGa@m0pzA>#?2O1M`HkGd3lReG<&+fH z)!5K~c|z{i2l9(T5E%!vU~)tM1Bq{)LN^(!fU=gJg38nnOc!uf*_|w5=sPH5&oFAX z7s+g0uu@7;ayQ6=(>?!1tMvzA_inU-RIo|_Q+SG=oW9TlP3c_B>>qN{GX; zGR`^5<{b0HIj7(C`Tp_yga2H|&2@QQuh-*we>@&DaISSxJ>0LNpkVKXtgxc4rhHWu z-%A4b1|uSaz+^tN#?=VHC%x)Tqj%OotnAulueg$A9>r{Kr`D8av-|T0QrgMv*)F`M#H&k?Aw!8wsYz zJt#St!iC&9u zBtkLONY_i2vyPXk2C@X#A-8jW@q-U9Zmg%fQEq(t-fyWpi}~-CjwTiFJ3qR}yp?cA z0uOx*S|u!FkrrK@Fu+R~m|Gso3(bgMG71`b{#r#_=v&Q41({T_Bk3Tfr2#WiT_oF9 z)U`K^Y#5J%amjvAkAO$53@Po;;M#BYkAMXvy((Hg+@$;MCWqog zARl;ui>Oa%uV3Bbqa|L&K)H8W=~BMR8fu5BDM9t6B#UxY-grN3Eo6jk+ZA0xh#Uo& ziOsb3eUBqGTC~rXDSCJcKtkkN(zVuTzh89k_o6`ohl_1D7IkwT8|SO}ckhB?Anrw1f`%m#n3}eHG+3rk==+YNp<&N9n7# z_~XKcLu1n>$~^g4ygtpr5EXUJ%%+8@)N0D}?+Ke{K?FdlNFFwx>$AndO$vrR`UvA+ z%mc|vxQU*-q7%8E4ik)_Z8g!Ma}kCJ<%z~N@uoh*s?}x)F!Zj`7~atBpiLaC`~k*AkqAD*v`&E){KIMjwT~~e3XYqp=-#B)~Lkpb2&#!o`sZAv3sAmf6M3Ed z%E9iwqz9DWFZpz&Q zX<$WVDeM`U7QzB5X+?BGgD`E6UR)J=p`are`!q4TiyBvYqa~JTq55LJ9DwLL+Hq@$ zRR%&**%OJ=Cd%CoGXHer{qV1n{0@%%o9w&qH77z&L-U5bsP*vnV}~)3Ec37Cji-sG z`1;{UPL%AnMT*zM$s>|ucd~{Oe+^|5Ok}T-dJDRjbNMuKetv)+znX^&{Ei&Czd$rZ zsTwwZ3-9=;CrQ+;^RRlS6`sysf4vB#fjAEtoD`c<7bDNXc_jeCPCUG2@Z(35;p@(%J@bd(FuOnhB3XwRW4hHDyL zQa~KC2J;%~yUf~Qwq+w+cJ5qH=Xk;8s2_M+5&=4y2o?PTSty3k6C()OXrI)J^BD32 z1ZHh98v`C$5jYwiw0A1^hkCa3P0hz?q z=rzt@>^eNb6@|s2{<~dbhMODs>(bN7Nb|T7`Y~r2v1=!YH$U?uM7ZLh&a<^jGuzNs^Mdn+2ZP&a?wZHj=0`q;?8n)g3UbL=PrW22lL=9d?B5K| z|AC_4^w{q+T!wlMfC{j*9`b9rrYfA!8ly!@@5}lqr#=rTu?6_u@}iXC{6tGUhBnHP=$>B%IKYeD?vQq;H6;mvzMf--=A6c>wg7jVAwwt&AG!#6|DS%LKwOFe=LbS6K-AbV2yL(FSJ`=zEEN?iff0C0w&HvH+4b#Ql|SVWV(Wn-SR zCr#hd1i5sDpR!7G-`0G891p?pr1#@QEuhT7XsO%r=o1*%=&CqSb@3>)C~b72Fw62+ z5~s9~Mi%o8`b9_T%7~Y^^YzC;B{&m!y1G)rNHbBX1=sn-CxNZUXfhAYPSkX47;gx+ zH>6`+%)MR)`P}(H=@&8^p>!6-M4qza#7*soT=IqM!U<*Al4Kyolo~;@*6HfR2gbQp zZ1ue1tV(IvIpk*DX5+W9u#Tfg-1u;)t?E(WJ_a;Hfg**;6P$nq&l&E7@AwbSyiexa z$!|jv3PzOw^!f_DUY+uE^%SsZN(M z;rGF<+NeI+?A0Qf2_usLF&b75Zwfbb>-*nML!0;du3h#5n#E^@VV~5JPPYBZS|YR$ zZ~wMWVZ8~^!aB0qhPz*#^!6?WMBUg{Fy{}cb9`oUg_{CpYMYj^SB^7XpF-F#`UBG_ zFT8{tG;u%xAD<#TpVp^O-$D;}cVAEQ+i}aH;HlcGTX%zw2r$pP6z552g_)n)+1|&$u zaMvlm$XNh#j7lB2ifr#f3?IhlR~5Y}7Kys1UkRIvg~9%W1*KaIg-AN)EFA2Vr~BKo z#^GYu*@mZlxuwn)33;%>Y_MEQlEKkxIlqP8`68(99TuYBy%JiynPxTHUI4% z*}1Jfv_8JZ-c&UJA+Q1XEIfuNybk5@_y=M?En(de^Q{ue6=;!PYLFRcfpx#3XK#Dx zK6Oa51iB3s-8)RSzY=+cP=2;ZXn_%}r@j6lCE%`*_`IHoxat(@SZ_PC=2@6eqr_LS zKhok4-b&wR4^rYy_!KS-EHRK2`0mk4L?lMM~T8oRnY@pa}qO-rhi>#5iKBrr; z`7?_}L5F8IH#r)2p47)Jy@*r`c0@z>^9RIHy77Q+Z!ml6#ilnC;N|!&7v(2@>I+nH zl(dt{Jw9CFvZOYt19k50;s*p>%=ldZp`GY^u)e@&jLf2i*@_=XmUm{B_I|{y-DG=w zGc)5<7j&Glg+*5s}N|Kx`O{?1Faff|X1fQlTi!a`>u z3yb%P-_3xhC|~z&JKwFyAGvUP#&NS0O%e}jp^jn%i0pc~O^;9}; zANz(mt8_(G-7i+mqMM(;zMx%hrZ?(P1!k@Zpzym!tqZWDGIP%f%QxgLt04 zX3~i~4B*dmq4s5c(bnTEdKluBo^yGO^N0`}ifY##p|c;6CyO9eA$Y!Z=rGK6SY5Ca z=TcU?WyfCt{n;eZ_|mY;r0j=u$m1V8E&ZC50zCk2&45GIW1|*V`mR< zV;zX;?6b0=m)VoP??Xx_O$KVV1-hSH(?HnWziOxNC@7rKGBniaq9jPg;x%%1UT^5P ze(PDNJlz`x*M+T{({~WxBmCD;^;|V$ul1%Vd99R@IuE*cP-_z8;TNBKp09Z3d4UrPt-@t>@mS{k^*vWbWQ|C3t4b2Oc`W{N=#o1+szE)c z-*v$D?a@o7*jTU@|7in{+l&Ku>xt=VJR5!;`Z} z4y1v`QAi$R-29xRdrqp zJUBJn3!V1lWbDGG_!iE=b6QCI1K>6_Rl4iW{6dme>_8=f%Z+mA12J}uqh@ypz7%!# z1mLqHI&dY4s$y6=$I$^syxdt?rOgn=i$+zZX^YM3&8k-Y7inQ8`9Ox&cZd0Z^`AV8 zP1Nfc2 zORt-ix?D8|(nWKtZuI)G760N)75#CYSog)1k|(0(O5xUsBX#wYuDX;8JCAPU8`48M z$(_UB=?8z9RDH1n6z8xrqd~MkA)tCmr}=T#{iSEW^|3%&GfU3Fn|y`%-?*{LGOO|0 zwC5Ib)?o>=nFjSaMOwGOii)*;5xMgci5ve>tM_}X^zBQQRb}QH>u6kTUd%yw?kbOd z+)^!7FXWu8BVkTO!q^R&1m4m|)M*^WoYN3Jf`8W7Zg3x`KHvYm9C!66uM$=c<>WgL zmV(^oix+!P?z-c9x+(X|<1U413kW;Ytt2Rpc)1H?M)-05Csf}g^acZuh+5CV>SvsJ z`N)`1KSdJlVViosIeBCe(^DR>6_FMGlwqMTT2B-O4}+{{O>>njB1fRL+LeiU7W8heFv+@DIyYpbDkc9vwcp2LTcn$FV%m&sJ@jOlQ_RnsZ_dgJ0zcCxvxD zH!a9~fTCzkGLh(WZFHYrz9au&{8cTL&o9c=f_i(K9R?fCAX<;5tVzygvz8V&$Bz_S zz9;nzo}A`M0?M+X>ai7uFK=BjybMhD{7CKR`7I@^B7ie@sVUi^FK?7}D?sNhq$SNA zhVD&ch^KM;`n7gm6R%$8aq)Q#n8YR+jiN7_FY)m5Gq;I!z!@rMel{>+WRWpF)voY80#CSCO8FeVk)lb7LdXVct zgv~q8(c-H!4Mg*5MQdQYY;D}_S(~_ZfG1WT)ws^yo|TZ;Q`O}y7e7n9TC|ZkpJ|hU zKF&d)HF$2?G2(MO@OHuegBUf3F|hiDJ&ng}JFfL|l|*w6YL3CW>L>UK%s{sfmsb6< zQs-$}FvKx1vft_#iwm$EP5!Ibz>88Ua>#%kNSN%Nvf zFL0xk`@jyEHV1W*G9F7R!qAihj|q!t`FJlCnVF&tqo}GXvHuczvKw&&4L(b@4i2-4 z(3!2rCustfilJCj@{j*KdTgX6@uZ> z^HoUGCv7SrypB>PmYLRsUc@RGSf~;Ig+!)X2*a`l66h0S*J1r&vt?Zl1H- z9KLwA)R*TV=4BS$Q9P%A869e_U9}x5SGgAoO}4jfX_gco*CS<-^$bfg|w}!jS zw$<~o?XFTLW3^CwYu|c4k2XMWZ{IfgSu410lb)hV`LGzJcH3cgzme10$bgKmv`$P? zOw$Q_Q%Y%tJh=q7Sq{}AV9Qn`bU7PGA@pg5CDQU(_0yJ@Qn8J4P_WIoJ4WuOloxrp zVd-PwC^t4%ts&a6$)mQ)HrV_*jx?6nxP1XMcZhEuzwG^qwRG%CJnz;0+Z?jF^r;=* zo_@r`WM}|M9DptE4aV#MElV0Pch2YwR~X7Tm_VT@|v{{Tpr{kyVI>Ee1n z!JYD|h&RQS&{k60WJvM)%Q9}H7GMBBCRgu>|6Qk9tdv+V@CIa%nn;uHJ3)C1~ zvLR1vGN?!%p)oxrF#jS->oUMuqw)q~@HSfLLza>dE_6=0QwlmbX8?NDPmLzlapv2_ z;>c$76zeC48Z`b#%ek6`8w}e+ESpw?8aor`A2KtZh)s+5wd7oW_dmI;>cc*#_${0P zDg^3JUf+LW@&$W?bd1c;@^62uqc7U8)i+?)dxc_qwRpj{qOc>fjbfPiDB%Y#C{bXy zNZm2x(t$XC1gR`DQfEGpbQueCcyTq#c2(M5VK@}0MqhOQlXb>`EAt=49Itln7QWEqDyG+vJ7pWaB|>mUb97N{ zO-zRVml+pgrY`S0yA>W!kIuJpit>&8?_%~RARW#~52Rj6z5@e!dM^bQ$}6hpoFwcm zW8(;>crGpccgotGz#v+Iy30n(W@REX?VS@BMy zCFma459-_T%&)aU5j0qE9GtT6sj7WQHKFsYDBHY~EtK4j=8^jHyk}wNocIs4{jqZs z7U`V$Df&9Ug3fi_9GZbd%}|p_v*Y(57TmSpl(Cui&1<+8GGn;J{K*u@TmodfQ%me5S_G@h085pR$@m9Seg&VUx1XQ5W8LLM=Qv6D?=KMy#O zKD61>1}9)L;u^wVz6KQMGN_FpF^lI zrOnOErFtN%Y6;f06?G$KOeZY)e_;vyVp-RB^DiN1hO+|#w!zC#0PPsQ4E7G-mLoRX zd*0s)jretg#Wg-GiGEI>`NamW#>pmDn7@N!gEyjng-qkVdLJK@dg5~>nD<~0U-EqY_|-dYhNa#RV7Das59Gcgh`m;VZyM{2;#$+o#(1{}21q!l z@tGJsTsE@gKrKyN0oA;JlsQ%>^W``@7gE1872DplxcLR~h`@%;h+Dl&=!Z!Wp8>)_ zxIdodRXZ0AJ*{M#+h2y5Xw~g&*xWDcvGy4d23aXaf+wP9q9pB<#5B4p37ApaBcKoQ zjD*~!KZdz3zs|!nBn=81)omzdqSdPj2uz6T)ysR~w+IZSw`WdDl9d4}mRU7Qxc07Z zBcckvxDVURRyz7I)0%j}Q`I+x;X_QATH&5&tfz35v@EzUJ!X~Gq9mPYXPW6eh-oVo zET%Zc<`eeuY>)6yvT@~5((eqBn@hbm<;>x1O9L2zO>k5*3W7J zSQnnqBY!$Xt8bA$M2auj6Fp{5CLT^7wE3`mAl(3Awu?prHriOqsl=$Q%G;(NOBWxQeyi zHNHNIitT2uf`Xz*+U3N&R84O~quXa1gJe1DvCw5;Dsz@W7_JYFJV4C>z@?$3r{Q=n zT=XklP@*s+1yS;Y;^rS_irsw3o+#cf0*n|CohL$Z!}>F-Y`|ms4DYE~5sX2OhR*$M zjs9`_l3Pgj@k4p`>~E^v=A-U?bpt4y=-1{{PH#pd#v6mB?XQRP5(h2xH~iX4ygm=)KP+IF|Ni$ZJ?*V0diU8!4fhX>A^Z>2j6nL@RDems zUmIlcDZQ;se*=t)W&*uo|CH?JEclu~6{}W5F>9h{At~)!d=+HbX`IT%(~4@7j_@#o zK198dN1{<}MfSQqvnOBM>$z;r4GW;Tm>GvJ9LP|hNl*PoHgdK0=apuzBpx8^CbiH} zl((p^(_rf`{4RzhI!tE9+jXLC{dIBk=}x`&)VrZ+nVl{8D~oz9lRqI^Z9Uup!{AWR zD32}*R<;A-to-VtqjWDc{nVMO4CoWMnw&JnA8I-dk}14=CbXIT|7WTUB~x7H&| zqYj=qw{A@n?fogCDp+H;i>ejb&(e2gmJ%rUdi8)^#fXjd93>5qF0K((_SH=8OT|V0 zl{@l_idXbp(l|oCZUkI|yS3S;+5xKvkbYo?A1lGtkL4p``y{Yxf#c}OYD~Z6o6h`Q zO`KfAyj3N!b)<&fM%o}n;Hq#{iqa4@5I3TWy_SO?KC2|O;su{1RZfGGUf`w@9{zXh zTlH3!E{MM_dNoY@^{VT+D^=`@g3|);UkrSK4c$4+qfJ!8d!7x?w1GJ+w*oo;^rMX^ z*ZVh<*uEInSPTDpuwpM+&B^pxn`1$VI{9xH7V%{YfTVBugtK|#4zW+l@X26Ct|7%$!*)}2dL3Rkd`JuAIj>fgI20aej;^a36aC~b!18`tF$_gODT)wu{S zz0k0SVQvS!-?^G-mUPgxcL!A(|FZv%*|#rQYvW6JQhpg~89BMc3$F!4&xy^q676CU z)Wa=H)>9EOi%?$yZJ}m8mg-=K$NP%XlwaAKs{ z+5TuRL;VbsxoVlU5U{_a@J}s%2ZoBFi62sy0g7CTYK4AT0~`uBa1|wOUeyWVYCf!)6iQHx@fqRvnyzVL9l;KiLo0 zs#$fP*1nqB5oGf4)7n?o9WyiEyjPp4QL0%UY2q=JuMjubYyFa^TAS*pI0!I>ib7Y9@qvIC zpS)qd>&wBE!%;U*eVBGoJ=|7vQ_0?^G(>0sYkBRs+QtzFt-fEu1#fkuzkLbBqg&1O zJ;^5D)5c&;OmBpDWX|$Th_o^n<&*KwiqsK@ff=s*4AZXhL2-vVxXvV^8L6}0J#?(G z=dni%3~4#Va9j6=3VqJX)*8+@BOdT`sPbTn_|_A?&?(sBejsdrwts8zX}2cHyThv6 zj!W~ysspmei=EdB(WJ?!;%g<}%x^3Qfj{cv%}r~KBv)iPoZj>xAHKKAG3ux8G#FpB z0I!09x!;ghI1SdG!H!U3NifAJSfSbr+#FD+E9Qe8hZs6%v=*n_+^=Bwho#S;GQwuQ zg=PgnsKedx(8nEE9fB7wLpO|$@nBe|cbdp`(`w*d=UIlQcn8~K_T_Hf;gEZE&sYX; z8bwkH<}8&>uFI2r?J94Z`cm@xe|jVx)yHhE!*#u0zjq0>MZFtY0<2_gb8@@(*T*qZ zlte*1bzSt$~z`CB&S zdTW6jq)%3}+YWWh!$>6pz@jt5k@6tD@*7b;QYbO!Lr5YbSMs_kX)mDh3s$V!y#mKO zxG!4nZKoen3W!?D>FZf^r;syc9}X4j%v8C+Nss80v~eq zCIKA^ULLp|-14zCQ>1aI;Ak{5py5gSV-GETkwHClMx~4~mz;!>PmFDC_iUiCqDVoi zmnQ{Z;$h|7X}_s?o`9F*^X}Q-;(mrUzxq<4#|?i>yJM&}HcG4(<}w9tcX(weJ`Lub ztBpb*-dZ3iBN6@tbDK__>iKxJHZ}!zZ)g6C>0=_Z!aiG8LD=C7rCpoPu`3i4_0rjI zb^iPs1j|`za2RA=`A*EmE})XPzW6z#E)Sbhna9_in4*Co0w2yuTjL zl@`ad{Ca^U$vf1%Jb3ENgH#^L8TCl)5Zdmy}Xf7Qp5A5u!2pC{YtOK zABmSSR}8Tn2}@3-DzvBm^Qr{(^hJ_2fx zKthxV;rOh!?7`k zIrZOO)k*ut9)!RKhpnA|(dbOQO73UA(S_x(>kZkrO7ed9_QBtLI8U?Uj=H^lCFsR< z2Og34VN}?^)4yx6lmA^(q|O_7SpW%pZtz?5ci%2_>N~uOLW<{u1}!uMvqI`ys-!8@ zl+)F7B47p}i<_Zwn0yDIJXSR()g@YbNj!U=r<-~0&Ltk1X%(q!N6izWYI5d}7(egv z3n{(sRlc;yLkdG}h+d~S15_MM0jKf%g6>1=#W|t3OY)FeYBfA1j)C89HZdrv=us}W zhq9y>9*OACjOiRC?Aq{_v>P<@|982%W_7T4s)sSt6{H(e$<+8|wXlEE(Vry$-^_~4P_0^41YY|;}VOdJ|aql{#<@?BsYyc_Z4xv7n=AL z(^p0Ja5OLX#gB-1&!1#kg3sux0O1%HrB4XMT*Z~72SjmNkuXB{@E-^rGyr#E@A>v4zcG&Wd zt)VxUvhQV&>L_wKxbdge2ry%~4zO&&Q+m$dsow^cSMn`e0Xk7k$?zc~0TfIdQS0b+ z1{05}IR-pd#Vmj4F9odKXNZsRlGQ$!4|k(lSAG{YJQ$M5eJ@vU&$#$YUtxK_QFrO~ zvj_LIIvy8NZ;y&KZpflG0a_Gi0^`Go#yjBRR-5pQn;4&Wr-u4%yL5pUtBUO(L|a}m zXRiEpLL6Ut{0b!T``i2bG{l1Vy|2-Y*du)Qx2B&ZOJ{s^qvgT&MmWAvsau4@hst3* zVMcRa+U)~*wVIt1#T5PDD+dcRS*=~O&zFPvN?3WHM$^wwAXJlspfBWL@1QjA%YC?0 z3$vl=WOqr`s*V5+y_=c{6Z6tzn~=A13-o#jMVK=@X?dLWD~}(|mFT;-zfo1G_i+|K zK>j|QM^#I{BmGp5HturO?4(qq4h6MyKV|rMZ2|GH?@#@>pVtCyy>-Z|Zy;G%D;{Q< zv#w3Kp<_p(RA*SZxI54d6pt94!3cNu=AFrv-exd=V8bR}cQ$Fy zS+3jRx~lhtr?o~y`2zi^t@`%GTz$m&LOQitTp$PYA=d1<9WkiU&ZNaAEAnlR?IV>I zen!P@o0So74R-Yt!1rLVw)k{F=@<-2i^N6^-CYLUQ5X>7jTc_m(v>>r)hz@hUJS2% zA--)YD0yAzVtzk^$Y@4Oo+?(J15#t5qjavyPZV6`QSTxv<}*J21JQ*REkyk!+4tkU zTm7qtYPUkYs!~`AcXER`opfmZ?_k4RJ7K1?k^x}_)+^>CkqkeDIX^d;5|UT6M>nzn zN*vQ*yDNX*x)U;Usu-?T11Q~Za#J-DyM!P-yZN|@gm@|03{eYwWK$KB-%t5CH@ac* z5Onw9Ot(W$Zi2DL^Yc*cUi~svKezn0mr_)L`0e|=0|xPuS`hs(cjx6KnPsBK-%0 zR_(Qp$>=SP-L{Ak;As1}E>Y#CATs>tt&^s#Uk#ZiDAKGl7;j&zdK+1-d(sY2CvxSFvT7UkjZ0nqv89M+o?(|f~!(3L)iuz0P zc>f!2d9iYbvb0kuk7Ox_YoLRP<>(g>?u+=@wxCvFO$Z|WU@)LYc8T;fX z&8&C9u!(jg|R@BFfy9-+CbTx*7DSgv14Ky1>yZL6%2E)5hTW;Q{Gf#-8@m@9n7A*BXP2 z+HL&AJCxw3Ew+rbMZAXq*%ENQ@yai2i^ub4nvi#2%HIyJ)-LSuvX_`8BQdhPw~?RH z)$+}V&pR$2&)252`KnR(2i_tiV~ygEzg*;WBs6S;UpsfszA+NF*lDeW+;xXSGVAjL z<`YlG#R!K3tiyO(&6k^&6ZKoJ=E|~>10F@Q6bV(koGzKNS&NSb#Bl8?5&3jdW^+!K zKa~bwRq2FqC))xqgRx>Ncqgh)O7ZiIoYYB0b33Y-j2cl8=7CZo^QUHs+7-6Tqpqcb z1dkBvqA=GgYvKMjty=p+C$H_;ZNo}9GHP4FaK0A_LS(rV^^!39YPFoIxCR@W)y|U2?a)^{ zGu!WuDmAg=yr;eQ5YBF~mtiByRj~@+DmvOhru2%W>3zORC;gC@UjEELEFRwTLF$SP zSN!EGa5CrS$p=Juyn z0$-jxv0N*!prvl@L=hn`nnNU*t=eIK+l;gXH$wU~Fg>8A>b0#YaJ(a4B(uRj*g|G6 zUGtu`l>+g&{rydsW;w-%M!Ow8x|QAh$oF|L0o@H7n{Sf-aeQA**e}VI=Jg_L!I05<>A_=f>c}Iwe5eah zO|^3kz<<>=R-mZ9<5JK6&0?y7s1IXf%HP`r&f4ey_g#Z7uapSM(HQ1WF8;rP3>`@G z^`*r3Ba5tvFwWy5C)R*_8vKPZdt%crw*@4zLL1=AjroEdH0tRvmqiN#ZL|JTrT%l> z`imDA0kvFr#a}5so)tIKG&xUHz3|ua)?oSjZPEzj7@Vo)ru+eNw4{WXWnm${H)2mQ zndhgxvSvRJ|A6!}uT_$obZkG*m&~U8EV=YOP6?8nOg0FxNL3fYzmghC7+vZU_dPf8 z$aDOAV|QG(R+!}dc!2e(8gzbJUsEMXkcwB65;SeE4a6Tiuv{UbfkfS_LiYt5JqD+z z7Z5cfKb2n1&+^?m_QiD$yB0NDPf%|F_@LEa|0gOw7{SyIwFu80DCd<(X15>LB0Xcb z?QHE+f7f4>2qDhdwxL!0U!*R(t5F>h$@Dp=u0v6aby!T)a7H?W;jmr5jiiEx3>!{y zSXgT$H`T9b)XSQ*-iP!ap`H$c{Kn(i1qMvV4%9qPm(L8Ei?~m(+Zn zB^XvH{!(gF{-H>?7fkg=wo5(X2sU^rb@qT%qAGW(8Ey!rC$w~I%LgJ?J1k10Bxg37 zzp7UW63k?P9_1xu()EF;dX zjwb(5lwj5W`aKcHjy*nkbQ-4cXfR1JhXWFH=r9hHC^1R4{)z|cumLih;K-p zp%vehCfhGLYa8XVMktu*ynGzHPwVwZ@2iM2i1lT=KIqEg`kSUXfVLxo2n=-uriX-D zJoQ-^{&ELM$Lw!R@I)6(C5HYW3(K?Bw|Pq3a4>6^6ucfUd{gwQ^;@yywc$Yd0S?k9 zq8WOh!>F+UeVAl!C0}$sv-0T0+r0+;?$1xy+yEz>u{*T(prjrAE}RVqJxiT=0|Ohj z0h;u?>_J{GywH+*zERz;?|=3yo&Ad%eoI?Zce3n}B}o~wCEVev)9TXhc2e2vnfS?TQXXa%Ugoh10fx42%jo@js|Z-M=&O)H(|OAF zYYD%d`}3`Ae_4>KR{y@*^fc=S(DDrH7Vfx5Em6&vK~gO&7fg76bi%tn!OI&&IlM?w zsXHoCV3sT&qTJEWtk~bfWSuSaYO|>19y*M{o|CA9<048C3a~y2(jJgy@Opp52~)j9 z=OWWnhK47f6VG|N8A0Z1noZNt^imHX#2G?uBd^&;SaxQ2oKxKjj3xY}{!O)FO*$rd zbo1XVT<7&gRXQ(~MfDz$&1f4>o%u!{Xz;lLt{aN=3I8)MQYBf+^S+%eA$D+pBEuBt zpY<}(`dEbAe^h8lT)GE8s06Mx?$d)k?{|7rO{`8)aoB-5CS43 zj0I*&j1E*sI9ZDH8!bx~%e~N49raOa`mi1`1;p)1S;#4ToFGHjW3hRqoU~Ivy1N! zTkqVf#jl;^&Wg)M#gu?gGZ<)-7JviPQ{Pg8y&_%DTh3z8^El*Y8 zt=sLBJCS@i=-59{x_xU#GTarWKCg|BJNp>bxV@CJu#>g*yAl~bnkpkMGccd2bA9c1 zjSx4J9T?4J#AG_ZH`(vYtsE}?d4laDIrF~vLj<3>`rLH*YXTYzU!p|hXQYP*)!G2N zfJwv?Y>1Bvr5#QJDHnp zPkUhNxX4=!8~t3xmDzO^(&S1TH(H|;P`A==)rp30`Rkjur_YSGH7#}y{cqkF;a}ll zB{e3MY@)vojtdp}{GkUYpZfLrrA?O>(75&wBq-1B^}@-9FL!`@W}^Ta*wO5FF5OwA zHYgh2i13#`sL0Zv>VFd{g6D0;>_0!ZM0s!a4-6Dl7rSpr9{lhNX&7fm-8CBo#YAgt zgqhcLDE-!1s*0e)TcfXau1iJpQAUdIDDUNQW{iSac0%P)3ET__uWI22JEteT&ls)0 z7pNqWc?&l;AHOKEIR@y}(mYjnEGoh@$Ol_Vld`@8b+d!$HsCqob%${U# zPOv`ITNxZbq`~)Ji;_5vTI-(JOO1Q<)blJ$ zOT>F~8w3bm5G#9*LalP)uC-PL+f9n3_9K$zY@fR(FU>I03xc%7`rh3)E>dcWBBWf3 z?(p4=(xmF{krwC@kZbXypGs$bc4c}4kPSYADv08wX?BVr#Fa~`qttoAH>1EeVO zjeRiJsGSmF2yZ=Hd~3S#G^Jk#5h*$EgH6{f?VLH;2N+-Bo}OZJXEVKN^WEZwQm`t} zHf3$cjf4e6F$70F?$PIwlIyk5(_PF7$r1oJKCb_3ZjUaB|sf*5kpg_2Nl=r@j5fZXqvW9yC-`mUB z+die@t@sCW`Q=O8Jz|*m`@G2&FEh__aeNu*U{4T*?9tZU`MyXfCd+gd{sWD)n*5Cd zc+1E~wL?Hty4Gx@KuxVsi+9Dw+`CMjU(K7SXo+X9M!4x$j8tCp=O`g6br`0!MWQ7_ z*aYrKMo##>YHZp-!rCc3rMJ%+AJt5@{P@c9fttf?@}5@okM3`#vHSL&kPg?q415z7 zngMqN-~^B=Q_YTjYee3#mz2g#pF6tD6NpiskCju&$R4q3to~(lPg+mcQhr|R@*#Ny zLJjD~YYWt8jq}92c!6;YiAYw!^#R2&{?)^-7^7=P!_Pi{o)u3`1TD-M-L(^!Lx7^g2^1Ebf;jRnVh9Flwv^{TTpet8X7~=QIBU@sY)Y$48|}*^h91 zd&?LjGjCWpe7~3G_|>>t%o}IMxTN^NLSK7bqBkBoDxq~&Ov>IVt> z^kQxFh<5O1WgC{QARb|J9E)Jt{9M0{9Iv){gxNI=3^_?jgts(OX6G{A-MBBb!J8mQ z5)0?RSEb;A*?{JyEn)22?RhLgMeq5DDb4P|}P!sV6?sTjly&_HUG$jNXM?aSWLXpJmYj-U`mNe$}L5(DK_jLKz#w}X{V zn|?Gc4`Zr_cHt@iYYCSj$^geSz7esHQYR3O-3xobmvH3>3vF+2Pk0h-d>e*gMlu~F;Ql+~}v za^$nm<|%>L-$WlSwi@>5>EMhei^|&vTUy(^bXJ@@y1EOOCxj$#HFt8TKsD{04UGL> z(W{VY5Wrp!2yjaJ2Wo?)sA>YPOeelu3k%Cr5o~d;cr#SlS=*z&v~h*SB80h1x9~f7vE`kfs9^}$cJvc%J*}IhQ~u(?EqxhXPMRCcSN*Oj z@Hs$?0JCthJxlN!nWh|L5jjpOsVA}$YS%w(wzQ>B(ss7v9?Emy`CG{SR{z`A6Iios z|9_Q@XOx6h+=q|hV%6eDA+4}?58YK;u4j(8cX!aUiHcHIc|NqOKjlM}PqTR^Cz0kB z35^sivUQ85=`zGtyNa1sWGQR;Wy(o4Qjkv|oiM82ciMcFsHU^8j5G1^W;L|wV=3Y}^7BWZ<*I}|zv z!hPQt94cE=H&y4$boO5hDE@xIu(@y}nai#5(@j0qNP)^|b{E>W%pm2H#$-6cuTiDofyfbOQ0!>-rvz>lFbY@%c zOj6Q&7)IX5J;Z_;cz6&^pUxY&iw46@w5t~-eza6vq_*sLw6l+P0YZJ#*5(O9F3qcQ zppoy{!0WTX#_+|3@TFn!Usv9!81S0fuKzdd%@XrImsmXq=dOHyv(rydG3qMp@Wpf0 z9^@}O@iDnh#Y<=Q-}Ku5C1FYT`lvDB(G^ArK@>4;pP<~CvWDQjPiWx`-bLgm??f#*YP$XC z0K#AdUql{Fdu1lsTyf^R(LHEXt3 zI^K#}ZPnh@BDPvVBwBk@MN5g=YNST&QMIYPsgcmyBxVrl@A-Ux|3251>q>IYdCq;` zuNAAX2eF2uU$hXfRlLJPnLBbN01s@bJa_lZLFVOIXsxN`&6O;?WB zZ|ic}fr~5W^12Wq?fVwG^0y2%R6=;JbuOWwAz}QhbLGxfBGc@HJOZrmZw+2XGx3l` zU&5YZ7pT_?M(@*jvp#U<0D#=`P^beO*S%4w=}m;&if0$*l;eS$-$ zEZakS^K=MU^|1%9_RZ!B(l4iCE%i0>38q;6K0<|<8c~V^+yMis=AF4*1b$s+wD6Un zQd2Rh$AlD)9S-nmzxlAgiJuh2`_X3nPVU{%o_MeK+b=kAXa+%Du2U0h_9UR5&qCaS zjeK_+P3!i$?>@F)38377$65tusylgc?@%NXkFCW zK&~FKVLT+g$X;i?S`wvX(-v{-^ z{nzgNS>3kVKjF8DBw>mP!fpL~L+WPq&dpcu4#qFy7=Jl#?Aer7lXyhN+o}awl6u_x<6(npw-n3(8u{v-n!a_Xd_e3VuV{3gTZK?d-}7ZfvX> zHD>ul7gSZ%KKd_3`v%>0lZ4-EbB)ZuW~HP<*$OKE^EcVt)V8G>0`$gHMGBoE$u(e) zgF!~sg!Tvg=mL;0(&vP&bI242y7L4~hb?!{aMGxMMW=Ywvt{|qME1@N+ht2j|CcZeHW)$Q$pO+OiR<(`oO66*& z8%(6`{e!e*LE;x*JT^m-hpCr) z@bz!u+srNAV!)EPV<@I9|L5>L9bwKF8>4d3O^;46iZdSqbU6ZC_OH-45>vBv_VHCIrVL;vrYizR8-@}*BH#3~O6+Xe%w0Gm)Gg!+!{2jmz zBF*L^`?nevA}_$xSKUxUt<@uW--)i@J1Tkq{&C$EqT&An(al(^koU&%HGy{`NBmqu zY73Js%LjLoDI3Ctx2MssljA5x1>sW(4=30xu?3Us!wdH+$|XP7L}6!C<#6TdQyX`w zH#zvWnm(v3pG{{n$`$|NGl>C)U?ltPODu&vg+fpNfQ>y{Qws#c8vQ;I+Y)@NtbcBz zY80~^^9L0+Ti@C{Zp(E&mMZm-LVI(*%X2z2Zv6+6ubi6?PL*c!-3P4K+`gW_sdBEe zo^?u3TidQPuKl|Ek)u7}J;m47&1O@P_hVYEiDJf+566`>H4~DL=eZ3CX=;5ZrAh?n zGsW2BV8fq{2GJf0a`8&f$19Q3OtXbN{Zpyv2^C%4r&33rQ}1^_J?*0#k#~>8gN*J6DEc$<6Lam(uk>{|L!Tj4TuW z-#8t%LOB8ZSWMZ&yq<3Zit%c{a5?8{+e+M875vN&N&?8#0%TojabJcyB7bwpKb>v+W! zlS5lgWxcw7Zi0%o@|-S9g*s>t-d`1H^sUb$1nss#5oZ?0;kew5r+wE*MdZ2SQ{RQa$_C72JfHU!m8}S-Y?x%Eig_~=|~=; z?KGxYeJax(TUn$btJ@Q9cgw05+)!q=v!kk=HxF<6Z(5#Ps>bbs*`_)q!LPct{zX7~ zkf-PUij27ftA-?!p+2!9IUpbYkzwiFEic8OE-5ZR+VeiQ>N7fy`Sn1Uj?T;;MpD5| zqR;Vui@le7WKzE-k6_s35(_ETruu^%t}ROGm{ZxP!8m60vwOi_m8~|*##pU_K}0rm z)Thbx&?Sq$$4`;#m0F{G%z7%H-6_1M(v=R$&J%yMH@<9q9PCM`JkTKS{MXQRGH)rl4(K04*Rd+wPl^I{DN zYU=#U5>so%cA>-Nnu^hw&9m0#W3ELWQaH*v?`3QAxPn-9OBR@z&ke-yNKS{!Hw6iB z9y}!SXB2)ddh(R&q^-*1k80IN*CR$|g$oY}vMgzGcDfh)4`*;Yz z^bVSM5PELD-gr0lq0PB9tuGJVeBIkzBNW7FEwl3~TnszU{2E-m>7$MYB$e?U#&sME z&VkSO+o~-STWY-Ovumh6mzudel=hV?81!=SFFOUmhp{9B+M38ciH>6GFNRX0DF*Mm zux`Oe`Sr(##=iZ(Ej2Fihp=QCX zLwE(kS`@|uaX08vYl(e@S$^Yj=5+{hkK;;KycI}GvVhPbA$SY@BJ!ts_m{DC_VvII zzvrZOpNHJPL)Gofgua5%)b=@dX$d@dXy98uZ|x5kg66Qz@T|As(S zzx@v_R@5veZ_){iB~SkkGk&s;Or_QBwB1(@oZu16JIJBUjRBs0q@ooD&}4HU*!KsW zEMTtx*gBvTyjWNC3wqr;_TI&8@3sN-u{Ej;{NU4QDWBjX%LS|DS|TeiM|yK8}U!=E}ZxGR))_uZ@Ug5 zRX?qWl{`fEqxGJLKVQ!=EL}`k|8X00qNkhzn9)uxYuf?SG%wWj!wbMXj0=Rkvi=!# z;5A{=cMKt(a9#L7##$?h9^?;_SC0qVhs1#_4p#HFl6~g?6X^Yanci;UxVF6Rn_%uZ zM*3^#Oy^*#Vlw0+Pkvw4X4$$DZ49;lIK9dnVv>yh=t~wqI-oF~;mCK1xs!>z?iBDA z+b{HzO=VxQ>7cnbFC;e5s&g>k^zIAOY=gIVwyS$-d-{>Pff=#d^^xa%`lp&=*K)@n z?8wZ23Ay(Vq&{hjOhvWdyNZrOat7zqFLED?^*fU?te))s1pKI)eS>j>($6OmkBi7g z(-s|PNHipStoQ8Wu;}V~fH2Py28&w$!dnG=nqyq6-OY#)w9@Y`jyK?P_NPEdTSRLX zsoU<@CXZOy?Mf#})y9{Nv$ih2c^P^B8{CQF!&QEC8OnebiG=MAS~x0fM|0*WG17LzVth$K5b$ zvAXrW&XtQipir9d<9S|)a2~OQJbU??lG~=LE)8EZCgl-J@gALOD2)cfR2_!&6_Dt6 zO#i3tmCtSWo{FO%#ESA8Ov<}(xZ8z{g7<}?3A#3Xy`l8_q?DX~!1pXO))p$LMRuaz z_oA$yO|X37_ua8_&1NRDB)*rIj^gdgH+Kw2=mkh+;$ly}=s~0YyjSoK((+{bNsSm= zV_J8)5zO}zJ9ZfVcEzBjZcJge;_H}nh1)NgO%}&nG0U36Doj1-v-MllhaJZ@(MLA3 zCdc2$E_1mIhjCSe?4$hh6VyugBefsMlQhYP-D;Qt%K7aaOwOxKOEp`pMtH`+-aer?%ujVU5jLm+h5t@Q-__5nB$qe_c3x;)~-Ej+SM|W^-GZJcH;M0 z+332<_lGZPAt9jXbztI9sP|#yabol;(2RLfhPgD%60(R@c-nh?ah4XAnu$HZNUz*@ zK+#$A+M(@Pn-fZ$B9KSGgj4I0wj5ZW$fYWrF5&hf+t`||3N^~%k8yj6&1Si}J6Dy5 zBN33`Z!m9VTjl%#K}O5Cm8sA#c#+suS9_6HZH5&7_o(G`H1_s0ucFPs{~{q>loUaO zEt~Z5hiWxr^S|2_uwBjNv|TNo4m>*x+9sNh`>T>3(kDH{OhUr?!DRNm<5puHJHhO2 z@blQHh8*zKi;t~(1|Bn0$m11;K8O%BPCD5pjI3Fmu2Z0myZ^$?5jZQ*VRBNq%=r}g`osJ%ex`~zL% zDdSN-hr8NRblN*Hb>|@XFb);Er?BJQlMUFSh1K*VC=7=mp|ikVaI z=z_8$j7kvPM8LSpVu@+%43W)Z2#s_{<0Hylg8YvyzFw3ik@?hSH#={NVy}Ki!gkQ0n`L}I=n!8t^olm zHzVXNRBu_s#9y%;>wlnw{t&fqODm4y^6~WeBlOQi7Sa+xucpva2CEU&q`Lyc5&9(s z&eJAoOGLS8tY!P^ez41aO2^=7yz_1LCPEDYI4Fzi(JpJ}~m z|{w z4(4(R{5Ud$o$Rd(TeR_TOU{>5jS-5v)YF$D1^+?cADYClu1|GlvQ@Y9mZpuMvp3`K zFWP}OI&?L7!I}v;u7)EW0JT|=KOqs{lc;`e)8EU|S&(|tt;Xs>XXe9f3oZ8o;glZ- zlXp}41p_c+sJSTY8kxQN_`g=#7!6{C3cO)CAZe3WPd2K20QsO33Ci#H_fC8o*sf$` zB)on{P6dpQC4AP?JkCQOg`t{4(fuLv&tE@00OhrER%rNoaNPDctU0{3(02J(f-Q+Q z`mCg!=B2GnGWu=jGx|+UAkabOxR;cLbHT8XFO4)imaUsBG{0KwGVjjMW+nyYf9>ZH znUwk-b}3Svy$Mx4_8kR-gstH`wrBleD@${aJJj!y5{uzO-2q4r1XO1M^)p$1n(t50 z!c*-ljzMpA{=B*@>p3{T1&IJIS1^qp!Q>%HfC%})>k)_Ga4VSGK+l@HWJ$k(I{X7^ zZm=NY&z~WrFFwB_8KM9mu798|G+%o$tTF617qG@$;nO=e)BeI!)23hk)aFU_Nf^A9 zakxpf+N>t})r_^C6Hco4Kp`B*zkv&-!Ugg}LOjmwLjMMD>XZSbFT;)1_O^4-e+=?Ex|HmUtQr`6^Y zy+AQFLHtJ>?`|_B7_X-DblOmF0->edHX(nZ;fldT-xoD|Mvn|Qjjn+7Amt{=0p-p} z@yWf+XKgW)H?miIU&Dl7_{Ddk4Hw&T0ZRa-Q6wvJ34%3<$sR=L6r!{y~ zeurACiYOiO4^+ppQ$CgD;ZXZTq#-;v@t04XgGz{ax4|kG`Kk)8psoWvH@uP%=~y!F zTuZq#ez+8Mx9r9(#}PiG+TUjioie$PQq1I;D}*)r(#2{)&>WAbI&{_AtU5Jm_&BtR zFj&_WYy)hAu%qBbJ}XDV*@Bs_TjMr{GR{{X;bq=HTjC=EsRohm$b~izb!tnp76H;@ z5E|GVSk#rd#8w^|rEngs{txtD2A{YJAbt-M-RU;Ux7!aNMoiByUMK!Z3~dg^7ft|* zipP(Es+gl1Hzhqu80IQRBE9-n6{Yju~?7B!X&9b+pe+-48D6Y-PCTxkW2E*n8 z_(~R*p5K)2w&5~$deyIT;qnaIqH{CmwnN>=C)PS2h5x8Z->={y>w=TomNOx|sysNb zAZ0{dg_IbKy1H~lUd4u4+t=gkZ&K0%_V;uy>h6F2_PBIr1Mdx+Y8!^u>&W4Zzh9T7 z>EK*H0wdx}*0b4(QfPvsF_G)%y~8YCp4G8GZe}%GC2vw*$8$#xzTtT@cRBeB!i`{Y z3=jPQNIvzG327&tyvHp-gmf$W6h_MD;`w&Q-=M5JJz8+xstymqmud(6_9Y72g0xK& zK7dPh8$nN+#bOgZ=V=C?$J@Na(r#hJ2;J45dHc^zw6|=bspVI-8qLgNK1X~FtV*SN z`TYxZ2tD=vAJ_8kRJ8Yyu|WHg$or;|p*xRZxeMd$mAZQuZgTdrD!A((r~)A2eC0h{ zt3IR(XW-%P6;QjQV7tcZ>79}G#5F!7Nf{vIX+(?i+umCnYe@Sc;{DMr{B30XWI(yG z9tJFObWQikTVY{hm%C}V+jomKW;lI@tzkm{!}uT6N9CnXmlHxbdK7{mB)MPCQ|~S- zlMH!8wbAuoUhp$^3%Mr)!=MXVAI4f&+e-`DNBHkDkG|LoIgZuVusbHFMj(wnet0@B zm%pZsoe6c~v{LC+y1@MFU>JR{W!|qe34+z;y2!WG-}E`|N$Yt(DKNN_8MU)wzk2K9XXt+7 z;}}Gp8G-z~6FkG%d2cKGjtY}sO@#Qsm%Db2zm-%XPZg3lede_e*E!55?9HUyQ~XkG zSKbbRwTmE2YbP#?1>^G7Wi3PHrTu;R^LNd54bBFpcRUz(J4nAhKXob34f+QBX>7>Q z@_E0yl;ouvr`+WVZHBLUW|e9hwVuCzZuThF!`_h_fSZt7%c^h|t0J=?#M&`--LYHo6*UG?e!r$PpD~ z!wg)~sAv>zI!eE^#k-;#Ig-3>EXlq^bSz*OaGW+> z16We3D*#?v;l9LB3Y#7nx0_g8n3-n^TXLxR&`%R@-)-{CwphkArMC<5ndtujD9m~i z>74{QiJB4WH*5y;7FqPCDeM+5vv@BNJMO4AuM=Hk=&ut2=c>*X&w8EUSAH!!`^w)* zs`|IFkCZC6lpu_)!eo7*;zGi8a1fw%oizbuTnbxY20)M|NTe$w(#=1uo5H?4zxn$l zJ$X2o{Wp(S&m6r#>8FbZ$}O@^-9^?OLX3!7eo{)nyd>3}sblcN90FFp!P17)HJ(&Z zSY5X1^$kjHCHaQB6#U7!HkJsOl^8xJAj2OBgS`9ROS|qJ*m^XKPV4;IPK*bUY@^8<>t!W~a#aN?FQRX)LdN7`V}J*kPYh zrhX^w=KUA`T3?>CPEo_S}RSF~T*T(irWO zaevrul)|c4qD8Y;aE)b%DBmE6D_X-8_?!Fx3~-Ccv-8h$vh4{i+B801KdpPl2ywh_ z;9-84Nbd~T3ev_OtpR)kIV&qZqhN^9IWw-H>hmQw5o^HgOmNesPENePVz4*1fA|G` z0bJI7?|F|8VoAE=zpABo`Pk+Uv8e{6C*^(E9#o6fEs{2KC3doFH!cDmM!ZWHtQFm$ zOa>Xk`mX&}+JAJj79J=2K=-xY()p2mU9xW4jz;56P;@o%$9!-<=;&%TNARm(lf3 zJZqkchfL>^d(A52`ncY@_jlN_+}ZXecl?OMc2<>fUev3nS4(jZ|)pMcrn zSdkWhFX5&t@fZec=NFr4!-bm%PSfTRf9GyxiNrv&O&uYQsSY&E;)o)i^4qo95!a42 zvyl@Np2pfHfQjCo;W3A`l72XWc!&ps=N3D>)HChh2vjR{$gl>&y*smGJZxSTg!@?!^}WPB4l%Wge>t_ zV3mN74$=LMn+Z)tdY04@<}XT_{Bh!niLPe{ce%dRwZLVM-oL zs^lzw+0#U^OY7i1o2IiPLq7i>Gzz(5{g8IBrTjQw!GP6NQHaQFe!uxY?-P9>!sVsM z<(WCl1$e~p3!?mVjNshaDXQA1$*Jj@K>cC)X!#O6cWQgaIYTPNQAiZb>P+kQVpDE7 zgH`#RB^DczNjq70T$t&wagmYw*? zP+56nheeC=ya=dBsp5T}a!Kh9^X%M49T;a~u6aNNFi*CwXLsU|OAw1T5Kjs;aSL{X zOBAJ@JRr1%Hw(CcWSxfJinTP?Sz9lNJtxdU zo8h7v^bf?k)fjX$J}ueTuBw|{n4#ngmq{{Zk#5AjA5mhS8&ec{Syr2IJ}H6H?_O-zOfkGUZ*FxDpo=Nk78egkrPW z1=_(EKgHwaw4jcy@w$=EZGShuX}oaWuFDo2moAt*#Ku5aob}pX5GqQA8ZNUfXLam; zfJRhUZdmhIwZ;fsDVjdwlb74{mvc6_K>L^?@>f}!{mLZ4rlUK)1Enc0h5CY?qN9aj z!D(-oq`Lf;_X8)W>g=UMc6YIwjiU;7U!DDa`RM4lX>Ml(#|r%xF&#d)+E|33yHaN7 zoz11%U}e_p)w_hhNsX5NfvXw`3})aZ>T8D9jgh(&=>LeQ$a2?1@!qhJ0si=Ez2PDD z`zG(Tg#Qd`UPQaRO>31VyhO?poMHL1J>U9XVT!K0b866kf!G9srY4Wj3^rRQZG>vo zn~(@q^W)^%r)kBMt5{;q=izkukvOg2N8h;8kb=tPEv?~sR%E%l_r5wU=CBHdnk;^A zUTvW{vQM!>V$@uALqS=#Qe*wJyeXD0tsizcllDWJkjXben|v@l)>rHVWU5iWyG~6?7Y$Kfkbyg#EtC=VhN%^xN@#WqF1Chg07sB`o?QiqNRQod6nB{sJ&=!NG zqn=CqiU$N3nNeNrSzdc__W@5vPq;jb%FnqcB`zy!hTZ9P)P0j>h=+v%Tr$$GB|u!| zAiMOXr;>+*hPuR?L(L*x5!l=Xg(4?2h9)ZY^BKIGTRV{<#j6R~>_}24s%8`cN1m=uu(TNV zY#!DacYM6|e9X7OcYV34sgD0N2o>LRVqiHjjl4~qhnopaGqe%1zXn_+!|Zs=o|!50 zb12mFC2OxQA6S9j6s($@1cm{Y3GU?TJ8Ib4GQC_Geib0zk3P8po$z}aE0jEa(Q zOBB@0s$+kuvX+5J_cxpwfZ_HS=Z9^l1%rzK?rHRt#n!F9-a5~oJN@uG!MCUnjC0(J zwhSj&CN5ltmFemp9~R&7`yW^fGR+4hzB>Q2CB4LZD>p=_o+pk1?VZkYfowsD6r=Tn zD}TNZ-%~}>HLsZc0|DMC1nEBy_`N;HAl~FnZBv{@34IRPS@C=<*x;ZbDUNFTZ_jwB zp7S;>iyf1>mGntjui!sW)BJ__sVS+!Aq~oj6t}n&K2PK_zmpdyk^WZ$l7hru7(2HS z_mnOI|ADs4ZTg41Uo89nl8pILe4p2i-#@m-8${xvN%b(2A2(8gu8I(}hFCc80SKk6lW}1LZRzF&`EdXWE1u$!U@6w8RQ}L&Y zuYK-^f%mch##2mp{IKi=AbN4Q5FKAeMIvv&piE@p^T!DD$)l#V$u^v1BIPzDtWl$& zvI!XS7@U&oF_4SmW(ZE0FbvG-y4}QosPmGn@WWA!wO<{5m!X$S=V5^nXcvBKinhE!9+S0uT9qUaH@6%=5GukjEPdlVnkrGqzMA-%nRqsH7fRzxfD zI{Z_w{amr3$FBfpunF*6;b7^Ny|DVZC&jqPqTP)8EnpNd+Ogs>?}BeFMI`GG(z_db zqH0>ywPM?gEwzik2_<{?3cmW{H8It*eZ4pnnyAi(R?(g7-?_i__cmmznCwsbih-K| zqAh>GJj_^;qlakU9atBJU7PS=A5($Y~$b zaRdqDJ;%~v_oQ1xAgY5p`ga)zOA+3B-YZNhvC+I1(U{y1W|q5-H~UnlzXM#xyCh5n zT>qdeZBc?G&Km!sn zfH(>cQs|Q)@!0WveGmD;bT3UWs)V;(UU$}nox15QN9Z>kcP0sS6b>~*oJr?I29p&) zXWA}NN>I42`UJig{)LFjTM=^i9{I8YnEh1@A0Lxai(r+%VHpX@_Cc3->Kdy?%gQV8 z|3JPYbdYzL?dK?a?~iL(FS+HcD<^W1dMt=NQPPNq6)q=<{@*rJ?)xWIzpf5C#J4?{ z5>^7vwjMZ+P0r&S8ruv-nzFLapKFL6V)_?MG$vK$N)%HoOa}^`wcTjvH%=Z8G{=ZX zeQ?TJ*)FS)30j`sEc^g~2+J8L0ZYd}6E)G`bC5GE{_;uEb#?#~zc!ar)GIS&_Iwe)kTc)ZhjIm#7O2QWhQ4i29icr!eag zB6UX7O(tscDT9=smD48AGp4ljBL+WeH6cDlJBYAtB}6n~X4896)c}x(Vzn`|fpJbP zabj=O@uIp?Xw-$Ko0XdA)@c!a=T9_C_3&FLHWvu*D^j0V#p#%) zx5Ag>!0wP_?wAfQKFWsi!&@`oKjihL6ap^D8|Tc)#faM%Uw0}Spg6-#FV{^7TeYL$ zBg!?c@TRHvbf`e?!Os0Q3rWatXfB*itmyP-m z$l1a?;E4Yv7YYP)+!nc%pQ!6w%J()Wu{#sU@VQuYqB5uRS^D!Gz^Mgb+0G0xH{4*F zVlA$kWkPjMxZyt>f;)qF@6LsyY zFZw+F}l7*L;!2~7l41YQ8+*+27`j# z{y3@LBs4u7+x{`BV3Eo#P)gku*F#}UEdTOh6!B{G{_f}O8B~050Kvf^#+sXCm4|pi zG|pPKxmpF|EL{eNX4pF^+dXjea`UcOFc`6?m_GAHC!nz=3C)Zv=!9&MNp(Tpx;ZJd z3k(O`2W*;b@1?nH%pTonoMgX3Dbt_VdNKHerRndF^VsDtC>P+>$CC9qg*I^y7moSb(eHFO zpT1{~EJwyt`bG54FC%~V|EPp8|G94Q0XjN_O3nd;E)o&oH8^-htZR>?aX2hU+WRrb zmV!ftG(SH!EcAiQWfaXiUUZIk(BE}v1imqRSc9|y@Rl7&Xd*}ZBFpG@GkcObS&*0> ze#iu6aXuT4=5*`OiMS{HY~#j9M=_O4{!5m_+m$#poipSTQUL*wUkjbHB>5VDT3S_!6(gGGBPpf?cHi9Z;m(-(C=$FftO|55++??NHD@$)nd&t{-Eu|B@~0gI z>Tj@a)YUDM$_*upYr4S5A%)R<8tqr`^~1jNW3;?Eo}zP0jd%gSnt=9p`Er@iRS z4<$_p5UOz=krZLdZ)mN&y2M1YrrTE%UpGaH=#$|X=E0I4g`IuX5aXiaVhq|>o!SmO z#Hax);9d-blwe4no=us?wub^JU3yxQSMkeQOfH+kSG*(Eglg2z9gbzwkdQZlNZg^le=Uq zqOlE0V;5m@?8&fSMs@DnE%&>}+6$NxOST!}P&4!|?p&^GcYCU^&?`1P?s><9oiahW z5voOK3sqMqK|8EP39F0OYFfvAhNI4cD+-F^6_=^zPo{jRPKSveFH$;zqDmAVvDS40 zY_SRj2-gCms(&!GIY5ATN^lJ?jOR{cxGa0g;D-9-nc4Y+k0_Fe()Q3>?u|CV?Ih&w zZ$uk_tHi!j)7R`@K8W*R(piSGI=_AVZC#zMsX6m`!`ODwd!@Q$k>u$8!qdWsGfy?| z4I(oUUgxv`n9hU?+BnbWh4#cUg=mXB(M{J*B*&qYL1d4cHoN^ffDG~FKhSl3HmyKQ z3)UH@0o0wwheDif@CkIw^@!`I<8m&^S?-;X-P#iNx>Z_`0(DpX{(N24&(qTAl7|rH z%*1mUULUVZo*(-B7Sbm5wjepz@~+k9b^-t@em(@1Fx{TANPXC24!WSfsHE_d9xqG( zT$&liNr#Yc7d~9U#8_WW#IMCuu7|q}+IOFIf2*7;Oc7Xo(ix{~+Vh@{Xg!WMAc>iD zp(D`M=pDxun>kiK(KeDDp}(iAjRB)7jGvs4KgIkiSDP^Ll$Cg|5pLVB9Fk8M%;vyF z?lcfHe=hP6hEk;8tG>a^ko<(?c@&1j($5BW!(=|4U)_0y7v7h?<+U$e5a8blp5r?H zPWnt3z!!BW0$6Hn7ztCRn1_c}A>^k#tj|P~UmGQ72+i{i#9e*HKzYZh`$*Qyu@HAiLC{kG3&Aj=w&0)11YeEHO|fY&f~_ba@pUY>20= zM5)iqEh;}5i%1^&6YkA=1!nWA!&f~#Xr8=``!KJ>I@q_fw?uflg}w~;J3r1Lg|4s| zSd2*^#0c+)ZedZ(OI-zUw4TnO^XyF*rfAuc>oPwXg$R1VW<>R^u4&*hG6G*FapCr2 zcF8w!U~cja!r)|2VokZ3>t3^24vb?U2o+Ff&C0tGYWZK8atbHV?nvui`L9E^e;lYOOo>?E>;>`mQr0iH76X4x~FV0?uvh2yF~} zpi|FRs(F*cOlh=6DIhL&fAtAf>c?GL3&7Uv+65D(56YHv@eSp?H=o{R>_3+taecDc z0O!WkE_i1ITPncRnbs&4xpy-p^L9a8sYEN{gYGw~H_24OJkUf4;aP997-T2?+z|Ei z8Vx6f3&p7kdwu*(xTY;*TJQV&<3BG!)Y@MB=ambZEgw#oV;*JqD@ zp48E415#CE{p4CxZec={bNb$MZ#<_dp_?+JSM#}7Hp1o$PE&+De*PBWMhe0?Q6OXu zlF>J3BD|GJo@6ANrxfNZ%_O@n?h@cBL6b6gL;FgWWJ2flR>Kc(8O|cxLn-XTaZrYy zaS+~uH6R^nUWMmQpU4;?};CXumF6s>aK=amn*Z-hX`>UUBaBOdmMu zHJ7MElubmw27W0910IkRXkYNTE~ySr-??Dltz1?sc$qTveoJFymFRZJ5+HAX;~M-p zq;{q|U|~7|Wrd`L_Z+)TsEfj1jkmY*HII`NQO2OtxWUlb>Lz>yCD9m`R2V( z3!|TTlHT`sa)jC>p$J;GK(GYz9+yZRSvcd>uA06W&_r!bZ}ubzltGLoq52NGLT`>RYTcyt_VZ_)iceSo`tYg}Q{oV-aBT4#AwNNwo+ zb$N$A_Y3b~ux1Am@|{o-ih<274DJ?`TIqQdJDn(Y-z|ztz1-O9`Iu9fd&kmzUYZ^@ zKdtudB!g3?Y}<&=?`Zz;DwS>=!6m5Ua+{M~f_l3TN-FheX}g5rf9yfr>oACEyVj~| zNjlq=rYAod12`7{K#U~euG_ex{oPy+zT96$Z%dNCa^Jtpk({w_z(5*kSHC*`59A71 z;5fDN)VGb2?U&EXg?~(+9WFUdBktBc3yN3Ogx_;ytda9dNzro;Aud1zMh^eFCY?3M zF;b+2H%_Nt{6M+6d%jT!nJMCry8At ziJ=?`fI&9PN08gF0OX^8T~x$lGa<}Qa~ctt(k;O|t=TIb=GQ7B<;=?|8WVkG4&;&V6cH7AY~?v2$92CAJ8 zz|^D2vi@W-LKvEka%W@tgI&CXg+`;;_v^dF7{Z_lo<7tA>If#?@n{#9zPvp}wj*{! z;{eA>^3%Y4-Pzda*vxZ z*IgQ^$6+626dSnRJ>d#})8B?U)Ws!!OcuZ0YoGn#_}WoqkH?&W9w~hVHPf+TiKHD@ z2mnfUO?^Uod^5D+|0ZPf-{(&4R)1d|Ytqc$cu zT9=fJTcU;|!K|>P#kr-k!qa+vo~%9UYatzNY_8EUTV{N>UU973Uys8~mnP_)*DY061HfS`T2PRn zpPu8=s{VX=UI$RCSGg6W?Xzf$1^L9OGrJ|ncf6-x+_M_q-ui}kOoz9lsM)I80876j$X&w+9$ca>6T^no~ybDMTdWwhOXGN@A+=}TMvIr0Rv>T2obUhB0HtQv2gNZ3@K)DTx*>D@BNkd!f2iT87YW! zh1TO30)sk_4f5AgHD)IiC(TWo*CxfTK<3mpIlj&!l*h0JS2S^3Ix0FYJ~08vA)0LW zS#Gz>^!hHiG(u#IsuGbk$b->^YYr7!M%IBu9WtnD<6+oxe?6NTP1zm}O*ZWano#>r z;C;o9x zs>u@_3&!yHr!SpLTBOJ3Pn%LQ9>E)9s`YO#ovkAoHnQnR@%bBQXPXE#M?_WuC_ONf ztUUF#Do%>a@4&4lG<39dk-`lRv9Xwk4G48(!cD|%g$~K>n03wL4wBA_$E*^7c(h8B z9s@N8mMGpq5hwNGP)ww~4$94pt{O&3h4b**#%LPj%DP|XAZ_~)W#;LF)APq0Qz$Uh zc`31xGcr?BOp}E97BBjnt?gCZ@6)ezAdtAuEf6#4r5`5nnp&QFPqcAjmGkkXsXiexd;r+QVJqW99D z679}omdnG@HSQUspRx-6E~&i=ST*filPQLj!~Q!S%?VpXuKV;CQ?T7Y+;O6kn?SP- zW2-n1BVL=#rI4_9PAX08ZcNMzb5f*hhOrUfu5aJFQCk>DY9KH<1+Ib}9hHh5u^&^{6O^1O z(6I0H7wyT5pP;WXbJTjjcfKKb$90E9GyOXse5t~jQlzpOy2ZYpU~0J`llJkcDfNjiQ8dtR%UF2& z(B;?TV_y|dC8jdud+hwOWDTT#0tHJ9i=mq99ye&Jhma2cfrfIRbVz;}{m=x|8A_M% z$7hd0`|VQ12GLxCuQm60uTtE_T`4NC(3N2qkXA*FzFvi>mnapa`&Wl0Cz4=4%IU`(u%AL zj?ln!XFpv1+4nA-w(iPNu|u=j@aMSYUH&zm|3}q(|Fil2Z`@STVN_M^QMyJn2qE5xWhQWUKs)Sj_o6I)v)YHwn1i5fxVeP5sN{lopZ{{X=w=XGA^`8uA* zag?#3&vYBCMTv?K)z4*HKO4rYdN0@Lkney?>A+Njfv88 zzPN3i62o6t@pVb#4$adsQVR&ctBJw3P?IM+NWU+@f-Vygy7+|iO-$RT+;}$xbfB;% zW%{1O5*}@V_^oL%jkSlJ5}`d0o3f&d0Hx0c3Jvt2a@Zr%3vK@l4q4LuVnSNmQP)nE z`=ewx6dLvdA)~exO%x4i>YsZsb=g=}$~EbhE22lIMiWFDZV6rGWWks8u<-5f1QC`j z+I88iU%V+V?ILl6@D{%G)5dv?Pa`*ABqjCUlIUwEl(xs+5>tc9OQ6@FeP=`Gzc zo|?Irhl2-E^9XH^5Vrs_1iL!cEwxPVWXU_>v8G#gsHps`Zgws(thG1ut?;XRcf&{p zlG8Uk#Yqnvrg^xQsAM{V1XBvfc^VuX<|Lxx_yP_ry;u9Vr(ep-=~=wVy%rRnL%y+% zX$(B8VEilaotYDE<{Qzw!Q+TBcrg)R>t{r;3s)U+&|!1nmtChFsI$IxHL=E8BU`ng zwb>8?TRh4dNfrEIsvqQ~RYc+~Kl~N!Y^!>FAnZLFJiV($xW7tm#(9%q6sbEVdRis| zfs*L}{qtufd?)izF`;egT4hzMZ}P2aMK1f4Ld6eXk8`Y|UMa79F&jLSPRH$o5S30x z<#?1HUy$=BYANXDe@*Yhc!6pPLz%t;%VB{}CsJ zzTY6CIJRgd)bFIl+w%ux>mrA=kYHC6qs5=^XN_d$?{cE16h(h|@GW@zxNRNn3!IdS z`WW1D&h-Dc4U)uhd{?AH4n`kZWY8;C{nmI^l1SQb=DbhAUsUz0Y}o?pq6LD5Y#@u) zUkT1oK_1fyUR3D5%zO^-HQK&BkKn>_L@A9n#aK3d-I*(j+yc344Ik%v9+>}+;IyJ_ zU*g6oO-3EX`CwYXv>>4}u>v;9&yEZu%hWFaz*)TDr|5Li@rLA} z`zn>mKDxVUr}al%>|J>U_PV?gZwsZSh?8sm(?cXD0~9#Icl(uD<(577yEIkTc7-&&LVtUXfr&5{_UafW$LDs zJ8>|(=^A|xA=VbX8+=e%NICf({@ytg-Y?>Jz1NX{zVpI zi4ZY~ihzP%mW}q&db0DxI|U?(XHv8HjPaF`5|2_BC=Enw)r#h#u_qXH%WAH=pxCT- zZ$m~xOs?P4xhmjDLw8vIsMomh*cshWRUooon~n&OIONOkXNb6)%-{O+TuJHN97J^S$P{)O$f6 z0*TQ9Q)jBI+I(C)lJ<^Vn5ty7r1(2a*@w7=Pg5N)>U8464aaw6XPMP|@}<$He7;XX zD_g}L+?)0Ad)Wev8lv`>pn*AfF(&j?N}-uNX`QX?c@C|K%`f|tJlYX9nBm3WlwD={ zi1>da;Sx$(Tblnf!ru`j`9GXOdy#f5jO$0d;El)LFjr{O$E?`_!X@X1#dX(3NG)v3 z(ib5kGEV{<3zMC)hAa(c6MYu$o1lhM25U=If2B>(6L#m4W3Ca~&VxSWZYD&fO+YNP zx=ydSaKLYq0A-SeG~zh^Ewb@&tBJ!xV2YbeMILlYLT5GPalm@7={g@IuEBJNaUk&n z)76OU0sD8HsKJ^^=1y$p>4ed2?mHmiJ+(YqSX(J*ykZe>xYxej_1y-gle^ylM1!Ad zoR_<(vCfg&wG|$^ZsKIied~K(20H80&KzwnGud#(2o$LZh zNH@2&+`vQ$$(K=vnlHka)GZCK-fdql!#W@CSl#nM#1roTHiJkEZrzOGkC{iWu2qao zt$`GB@W^sgu_5fhrnWx9+tL)n347SdHV#Cr{u^MSNm(iAD1(|HgLlT$6t_7(KCSImOS$3gz9V&AWFji^gML44CqXCaFxtB6hv&gN2ILpcD3s8UJ zR?g?Spwvxj%}L1K!?gXg9;eBF5r2R3YI2mRaN3v?obg~_KA~b2#=(zgULEGa9M)x+ z6^>RciS?mkS;}F^s`2-?K7Q2cdwMbqvB7cn2W`bEJBfJo=L%w%3RdPjwE7-8DBp59 z4xH;uDVd+0H+!ey$v-(1Yn>?lhJ98bdwMaK@wyDeNZ=Z45F>HU4BF}!V_=uiK1C$3 zG)FJL!D{p`I0-ajdtZVKnVws$H-3Cd9{R!MBi;w1KY64mvUKutuX}cp6hPibYjd2s!zaIJD(b*eowVJQ!3uT>Fl)GZvzBERa>~V07 zLLNi;i;8D|Z5rHk6^Ym4BHmxpT_d(2gNRwmjv`_&vEA1Nlws}uxGy^~Z?IisC-vpd zxi^qkVwYlPXNvj3AmxoHN>!le&Jf3_hDYG``ayD7zzXjd7mPVzeTf{;YrNt^7MRW! zwN*6}1?%8KBnrv1%3gS2APEHPc1uB>bL3itY;1oU*li({f1{*AC0*pF3Bt<{ECLGp zJ6Um4wE;r`t;?SnL{2E`{65e2-xNx@m*kaesV{wsXzgStyufNE0HXA0C*u@EuXqLw z5*~HKV3)pm%cT34zZb3?kY&VwQ@Qyc34j$-_AZn90!^Ke8+h+L!jsW2T4^u`2GXWGsUZs3w*yHyF@1azfEljx z4QHSNZCriu2O<<%$68EH4#ITyMr~LI7>|;{&mjK+aD~FHhvVf+tm;M!RXfnXt`{`RS079hvB;97otDJ1rsJMxTfB(g9w=ag#wJnNsKrXDDvV z5s-?di996JyPO32gn^}dV^YeonOWxmOeCov)5Vg596U=}@bk<|<>63QAkkhNM=#0auI%B!R@`A`WQNj^6R~)$-PH z(Yr|Ya<34D|45#YT$T3G})maP?t;I;nPx~mN-he)wKV=O089Q7-bKFF~DOGB#Xo`ESN}J zQe*ksq~o9!7Ekh=tJz8ah~JED)M92h6*vH22|#Y*DY5g$IDs%l@ik?(3(aNy35bRp z?lIC$64O}p5xObh3f+KROP^PBVg&Y=fqr*p?0I}478*@pw?Vkfxdt(G0&+F|vs(^t z-~m34&cEW!$^0bD$x`A`;41~9~1EK2tN~ zIbM`;`#DGvrU<0lZk6Up0#io=NziSa+4DZExmWn*^!S{8W~8w4N-?SdIhf$i6)~ib zj|}!NnqNw}&Jiv0FE9&<*G(Z9YDpe_IDF?%0#m-uQvP5yM~krAzBMj;+77u4o6sdsF{@oAd4QK#M`^jex zBv>7=YLAVKP4ISF)IWCZ8U_*sXkU<=!S8hA(ws7MC1_LzaMU-*vt5woqlmJIX*)A_Gx zA`=u}QBEp1byO8?^}_J{872NCsXZcOMj>i^hOJIjAI4dK3vl{m%CS?M;=~ewf!}?| zJ6y~G-zxgHMZnrBB@Ci$k1_X%3Kf$+&!xaF{<-VndYN8&t6r=1mMy7O)CWHAG>hp2 zLu|x*ksW0 z>^_bV&tWi^uyUK}7oSv#&B^uPaULz@b&+BS1|F--MsQq1Q##c;anLo#=wpd-`Tfe@ z&ffV{NssljJbhp*eJ`nivu7a}dA0?cH7DMhE|$mo9L@07` zb0rv>eIm9OV_|!(Rekqo-t;y(dVdE4V+!pvBL0-89Yjz7eJ5==;5CsTg!hTV)Hdr$ z%e1G?|CBf~>X9fqRy$;qA_=`c`yk3#f>E@9H*pI_>|ivm>Ao7SB@p0WsEj%1SnhuR z?w`&Vd^ZM}sy*^{PFhg=Z1qRWg{M>t?p>x1@Yk+Ejx{9lj|iDNFAY3)lyjO{ zzlh7uoy5~(I^2XI2KkGUH>HEBI>s`TsPyixhlppLz+zDh{5Z$HBldvYzz-=>h4%)x_G^yu?zU!gwDK<*963+SdLL&X*EqeTyvKt~}vcPaz?&hkPKH? zuDV^=iT#*m;yiQx{<;n%;-bt5(2MY8N{HdAh#^6Db;xQiC0Fkc&BBgZa|3!Ee5@|K zEJ-E45tDyp^~%Mp-i5P^@Rvb4Xf95L5uG z^QRGIcJ%7qgsMQrXGBhI-PNTLzW168p4kNSayCu+i4}qVXax}l5{DS!!v*?8cvPlN zmPrZRlMs`VIef9u_o^FHJC<`y)zvo9PFc@mf8N$xlLOKZj5%kT&dg%Yc5$5HQU+ws z#!I*H_E*f%o?%>nF5KR`9P+dUN54o4u6Vao_Y&=SN7$p|W-rKz`2i_D2b;MX69-~) z@juUHYlkfT83Wn#-X9dG@{%Vu1D>yG4|iCOzdw(G=d+mM3`g&l1o22S7Fd$p=|g_KuD$_4u{?aWV9j7QW0jTO8xmHVBD>7MJgb%%h*IavZks~ zaOg7p7DNd9`V0=Zh1+?4nBvv-aR$8z8iEGA>#Q;QFNDv#Z1%~5X*p+e`PsgjwVS9D z*|`=*D~?F3ekC3H>vC(L!h@!N^;+vJIC@+)LyUTPH|viXd(x;7Lw93y%q@wJ1>w2r zxDvtx|9-2R$mLm-{y6c$+=6;}Kh91K)zSjG*MU9EuIcwEw+k8WpIBV5gPEOKMa$p9 zQRD;feBzkLTT!30>u8!1D1G(%w}xx4MGwitU-Cff!2bxiuTFLF*-l(#*3_~=4Gs}y z+fWxjsv)eY^m-^)^D~G4pxk@Au3*51aJ4P3&#%iXTU0QSnVYs*%;*v5dj1OD(IR`~WMkZSmUBo8|3V5-FI9+X+< z)0#1&Y-m4qp-Z3R8FKU_$6Wd3+`hs@$!uxll{@1mLHd~NA`qWCMjH#@dP6`}4nb7; zf$*3sU488o;#ixFDrM9}lJgNLjF`RyjISs%uamCSiKBCB`EP6RN2{OXM#VBK(PDd> zCYgP=pW8DtF`=0ewxT$LU!f|_eAUO5fm^wc4_tS)PWSR}Qa$@$r)AN+4R#X^lsoQLKXZ^}}I>P-c-iYhzmMa`d|Gq3!TKRzLu zKsJm1xZhE8o2m3jL?iFtUAnex`V@`Agq-=0y;CL45qjD;M@E%`UQv!+qPmu;Aj)_t zj6p2NgX;nxg9p2zN)yi()nDOt?J>a#?3yFNpEMsGCXMs3dW}>#}Njr|wO zU$*OYfjq93P)Q+hoRVMY5R``g^>wDt^3CtKeEu99_)21)$Zy<30jSGACyzh<-~Bgj zHax49S5x*?KeP62C;A~)8zqUzCe`t=BG_}4vHjyI0luSlr6k`Jt`8%U z$?X$=OR1hpUSzGN`3Hql1?eJ_8pzkLl+rF5rPtG_zdQPEXUeLl>YK1-p<{ZdQ-=d~ zqy{hj8D~;r=1G;0r{QoSd2aeN@1N3FkA5=qjE}WKX$K!HIpBV>ZOKuT!2bX#&*C6f zx6eIxfBeerni7kRNEV)IZ0DVmRfPzItXO?Af!3Z*C-^EU51Jhfh$!^S7mB8W@0$gX zslE*sw^#hANij_)9B&?YGjR0= zpn>{?$tMT{K4fJ%ap?&@EpRR5#$X@a?5^j$2=cfl%FN{R!0&QRkXqP3f)q^*(7tvH zOP(3;h=uhT#Gjpk9!*KX9xm=A6z)vR`+mpAZy>}({tnkVz=H32N2oB(FaH7h8PIc# z7_kVT*&^w_0VDp$+3&*uu}Udr=4<$s+ND;mqtoaB@w1pQO6IqRqR}!3gZLy{J3*G?mFiB$PbB z>!2{gRlI3)G-~ApA&tu%fW>&@VOA3e$a@3_BG8*V(9`WoFz_}Lfm*W1s$sgQR2*iH_qb^Gh)Clr&c>`gnV3;!$i zfY#|%&H)bwJdxFD1;jOF_1catswZO)_8X;_f9Qn%Ufxk8+YkzL0WlHG<^ZC}CCN10 z!dwe4XJ5X<@(oSU8S(HUxtzR;}i{)7M78x-TJEHv^k5L&(J|X!J^zmkA2{S}dU{p^bPy#}K#ZKF|3T0kgi2 z1jYn=z%lIQSUW>W1&x2e$ldXa{_Lrc>HT0_@N?+?wYnj8@jJYO*Tf?bR>C&sCh`kZ z*$(`IB!YF@Z}F37rit$zRs$xq2i4C^m9b2FBN?EP zDY6Y_sFN6@%M(8MYe?x;|K-V6wA9ElAqe;UTb!@a3|j7M$|cLyL$R5Pm4h~>Podn+ zYBN?ydajF7;LEHPiHg8GwP1-=jbSk98O~PZ&3L-Lr#3yeq6ohxtT;bvrSC zGoXZ}mR-x43Jc}rj5Tr*IbOC{@SeJDwhjLY%vGk%jkAcID|gwI`=(V+uB5|#z2W_U zSMD_ud-B&|Ty5MX|fQoyD4Ff^-mCBkHaqRLHE-ygBhb(h{n=$o@)B)!d1Y^PM)?Y z32=Nn{)LX}D`gn_*F;|;3)IpYLXO=tz=vPM%N@Hc1?9%gm2tXD-fal1|B)3if^Nz{ z749)wkt0I{4C^LEzGF1MxqUn{x`?ChYG{00HsDZDzyEqqT}%@aKas|?mUqERSFZ^=4;r6Jh%k#sG739B4Q zfUYH(0m%%p$;g(T$(+O! zz7cIQ%Fh(?Z`ZA!k#B3AlzP}mr*Vg$qm|97cj6=rg~R3K#icRr}CiiZ%5;vs+)$91+cE zmVuhoMpOgqlz_K|p)rq~f7TT{A zQz5;H6g#FS87Y!->TucBN0H$wY|*uMs?)2Ui2ZIgfAVj}2Qd!A^MQ~*pbiiVn91Md zhDg(KUCq4QR@*a%i?;IKChe&QWxsb`mI#aiHz!~VG~@sL0pA0wXiO|I9z82%w#yNb z4BrLEJSEcpIqW6I>}AhoM6zw#<9(s_C6OEE@8{>4K84{1f-c{hTPT>-HBS0|_29=2 zdt@r_<--Oqz^xS9=qNu-oSKQL!+`P7yerEIO4U8J0Wv_YKIL&FQ^;O%n z@bcTKu{qs1gnf&{r1g8^+0wf&kdesj@n<;!cr$dLolaBhl%iy*vp71yCaxOk#NEn6 zufuG4BUg4aCvAbcN@md8^4)eW=afzI+0q1S8@uJ)BZj4zr=g9mXdw=VXG}f1Bq-JBlt=emG8I+$He#stJ+n*yA}7w zM)Gr!_P{N(nW@tbOC?&Z&M9{Y&uR{*R?f2=$(MDty6pbis>JH&q6~2MP(#z!jJAS+ zgoB`x}Gqb2{ z4TQjiTY>GXRspKpC+??dMPTA>y-=Yff0YEIu%A1n^9wuRB6Ef2K22sCeU-h>;QG-M z1j$}z+72U&@R@vWl?@-D1&av1$=Jm4svqChwqtc9q{pQ?q>uLwrv+B*L zDbD&IuIahItIt=wA5>GquGP;Wm$7Gt6^n5A-q#A2Up9BT1P27aYiTe(UJo~k@=m;- zYwTo&((SM`5xCA;eawo}Ts_)VF{p?0o$%F=dlYmdd*WB!`Uapcq(gg`nemDOtL8Z} zeMU>~0;|Zgb}!#_%`eVZ968&1_OAQBo&!d6*rg84yq?EE?!)OSDHPdW&3tj02WI9W zJJ|5~_1d5!{J6ha_0zwzECIlm2UCL=9ad#A@ca|-&QMGHIrjDD3RwmNJ%nl9aqSp7JgYdDUltCM>Sq7hg=#Gk%K zduLb*e%Ag(XZcA=&5E~~rpe#zb>k%w6y7=5Z%J(I*)l6$tWVVysl;(^5!`mSge;A{ zQ`QDP(sFd)6vEX$>5$fQxs{;EV~6O-S3!`# z@uB*ZZ|$1dE#)Yf)+d-u`sjSMb>NFueGmU#17B@Kc@)m{Wzj|{YLq(9Mh^ka@}THr zg+P$Q%QYs-_)%K4$lB=N_8^w{_?|XqHTg|7XO)zzXVhP8T?jsf2|G&OZDoQ(a zkoX^o{J*NeK=+HA#Psd^Y2&q=YwtxHB~hRlAUX&h9w|^Ja50%TLw0?%?Od4`*nyTK z?0oOER-PODpTK{!iO@AT^^k}pG=+}K0hnMqeyTH9EH3s$z@SFzT6-~RYUQ#|^#rlW zdWNi%wnAzR@ZN2(aFO@LGY$CfOzj#F)foaf&%fOTt9BzFo?2NO)dZ+KOhW__?o_R-@YpcwN@~?p}XL3g#Z?N-iR$ zd*UDL%D4K(?=iW(!c@lr4He#d5;XG0ki_yqPqIC{ap6A7=_}cPBqCpFl;@=Ot#0@% z$B?a3q?AF-nq-J~Yrp9EmvDch-jCUc18P@Nx%((pBm5EEt(egsg@WFDQCzv-$aW1> zt@2SMq3i_3anMbI79NH3vSR8?|DkJdUw{wp<`Bs22^z?kB8-_Gr0y`py>6ADSUxg| zfOum)dVxY!oK{@B@>)^r#7L3*GgS1YV~-GmY^T)$xZms%gwSG;z|~016t;c({4?IZ zdaW~r+2Tip^A95)=YWgGz~r|EB-tyU3mIN-w#tCg#(^jXa(DkU;8@+~mudn8Ruk-6 zL3ZLplAJ=k+3UH*jaEI-8d(ZeEZoWqC2;{~@>Lt$i?kvc{`k$1iS5!8{x7SFx5WA9 zK=3KCf%IGvN(Z$wxGR%hOt{h9c07Me${;SNm;UtE765X*o&hV@63`<5h$BmkHCdbL zo>C3DijyC*F!LGycA}=qUOIA8SoY+vsXsq_reHm%UX$HIT24qmUhMkpBYROwcEl`& zn%S_)k->YWts34|vXw+`Tc0pthZ$H_c%!5c{RYSJIv-?^=rM;a!>q0NzgaRADBAdMYR>9PK- z6uX(jqg9iJ{AR+#!xK+(1vbWSU4ewY?L!@DBO_D?E+CwDvuVO=*Tb_0I2)FGlk^Wn zX!lRCvaze-e-wLx>RY|*8fyE z{R9rAuuU)T)Dr0Mf}bGewFHH6{Xc%3%~gEYl@PWEw}|%$0&m#LVKHWY-T#rKo?c8! zXCLsq_&skr^q41C-_zu^vaoe(w`W7}E6P1o7krKj@&*Sd2rX*;Z*X#;(9_zO?j@RE zgSF4d5$@&@y-}wY$t4tWuo!fQ5QSYAS6Axj=(DkIYHx`aEHJF&)eU3#C~r*#r1MR4 z)+w!-5iGHzzg|D{p1((Hfz^gzNkQTYm%me6uGc-hTW#@#%8{wLnIiHuE)ADR7Fg?EKSXYJ++i@T;|O8hHT9s!c`y?B!N z)6Slu>pZ=9xaFzuZDfZASo+B>$U$IS4x!(HONS*8AK^{j;U4CcEIL_o=xRrY;lyTr z1y>yG*#3|#HXr=rnV#yXUwhDbA751w0P7Ee_QDf`U~#s8_46M*-9;1ySgAKPsxa7v z=e?z~Cgk7cprtG$Ip?H+=o;J%9pt=M^$c)f_Flr{AkO(_jRp3C@jDre8Ghlc%;aNo znjsbINxEmLxQyakZeSzpMRol@v_u6<4d|*fZB)Y%m4fc|7qRG4x5Ce@WrhPeFeDfjl3Sl_^;^fMFtM%;~SI+~g71oORTLOiR z?u}Dq*QL?~UW6i7A4*iEukPNj-V8uzv>j`)yHph_yS7Y7-OYWO_`*I8XqY)n!maf^ z+*YnXm0O&r>duzlWWRk86rTij@?iPU(SLGfk}5#~#m(XHd`*!YFN2p`V}4aoTsW+1 zOPAoJ10Im>&LIZG7}15@eV|k~ zW47~9j7RtbY3mwK%K((+U&YvE+PsE`zZ-d_^SY$m#e-Y}j*h^x%G20q{QvN$dYq zs}!~1Yge0#>3H;Uc1M~2^I0-b&K$TdXr_FRvilckb4x0;=kWNDj_TvUi0smx8&Kfb zI7S;s6it23^(U`pz`Q5~ekB4iYHY-B6)nGCXoc-78E8}e30!ob48rSuQ4{Ar@ZI?0 z%K&tK`_c#E7`y9tpl#9>!bY5J&4Kou${B)Wn@sjT-`@<0JByV-ziw3~L#uSjE<9^o zQ%$n3^)$RH*spsY|CFIJZ&HBaC&9lI!!W@&Jok=s1vfX&+o&H)fAI%Z<7u(II=J^{ znQ=f#BJY%6(_?TE`RBf>C*hlN#A9p$$3SOH%t}*uVJahtam-?U^6fb*^$31Y?r0o= z)WE9iN^{;J$hT>Ow`3BvyD#R`EdLb=4VS58*Ug#g$PH@p6opd4aSv^T0flAfZNqEb z!xmx|-U@@Fd9|{D+LH@;Jeec-HoHjw*sIL%@aQj}hefj4zwWs=CM)W8B{#~>jrzR_ zoycAwaylc%5nJ(oiU%1lW86rZ%BOxFpBo7z&fdy(_Nd-`vfP%G<0bp^CTwCF4)LQ2 zB?H?;y4%;=-U9YK*kAZq%`b1)L3%ib=gG*zZxLw1)_A7f6wV|@LXk1%+xH%8r=AxH z{%1fqi|F7N^YW&BKAa$F>sT3UiF;}`QY=Kg*+Y(6QJy`tGBPT-K;DI=% zuodZ%rJ?JosQT-K-~M1=?sOSwJssd=3*a=IKpeD-tSUbsJe_o}4rSOiZnao9macQ@ zd=xJ$a^S|F5}_kmRHyxv)Icf(d`U9`+6(5~Nd5cng8nQSZ^7B^k&uPx9Wtk7n%ik? z<;y@8Ti|z>^<(;2zL=;VMb&1vaLe z^8pY)`jA5QG+4$-q`gIi*Vk9)!Qkh97Sy|HpJhrs?CcV+v+Aa-mo^ZjM(kbUo;>kj z>@4{JdW3H?zS1kX6d=3i2v7zvn2=G*^@H;R4DLQ>(%g9;yKXpV`@=_< zZ%@zUTE2HGO#kyJe!|XoPP_C3ULBA}yMtaCKw^unX4cN+Cx~+Mc!#}r%G8H$?Tly8 zJ4;Ie$;*0;%|gE1@6DIgFzo53Us73Z*FCL7iOV3V>s*NLm86BU70rRK<|LxszEDEd z8PoBi_uw`dO7(|7clFHI@Hp{a-f^Ikkbw$572s1982~}FZR+`}_m6-dcl+_)e6ded z#GZ3b-rDwW?(G{!qzBE@S)sFYOI1J)iq(Ec8J^Rmwmxz-IxR#L;hy0vT=#xZk&$(X zEm?7egbY{x@~yAx0IuWcc!u^nz!l_h@L~NwL7kZ0iF|-tf#cppyQH^Ux$`mJ70mCd z%NG0lZc-6VFx%ll{PihTCJE~B1z(F@Ga3t}1Ix2o;K!Er07>aKh{1VKoj8*%FTsd&NOA$~VXPe?-F z>@*K+8k1c#OzC%%2_)%PTM@gpfik?Zs4H-cBz{^i}_b4WH)kyVoa55Os=8(bwa**zyd z_^-krYuT@GEJ|i=S3PT9kJU-}iOw(m;!#faI3mUWrvph zr>|Vw2-ud9KGZX}+bg7XN@VsuZM~u|V{csOUBa_8z3cpTk5%aXchz4|*veB8#T;>W z$JNbw&VK_O$Tj6KjxOsvSMaj}ya&z^gX%(jBC_HHB0_Hi6tf(rErcHMIYgzb?^H$bI^kaQ}iKMV?5%Z@X{-u+ZV2p*6_j0NdDL7`! z{aTKhwE-92fqF<@wy*2}SU%Or3>Z;&);BdeZ&7*>g7UkWFUQR1qq0u4c)0F|-4M52 zn*3g(^|-Bd=pJY!Z?jRj>Vw3xeG5GqdaRk%KPab6NQB0HB~3UiJ8A1;de({-xE(}8 zvHi;Qt_EEw27HOR2mM}E1w>;~Zw2d@75WD>FQZ>p)-Y}b%L%L6jdWEu?87Y}Ntu> zo;2-47uu3{R?lEQUh&&~)uY<%8lE7*>tqNgrb^dv{1h=a-hI!?xv6gF{ES7Q2fV0h zZu-M5l^--GPnWn^^g6=d(CXv7o9RB}#Up1 zEIqpZswiZ$0)+ldM}eeatoSy}bc8#^-+$#7fm|SZYjXd`kTD`U}l%4(IU-Y2VU_4ARDR&u5 zWmaG7H$?s*#Wmn)8fBJ>A^czq`RXQja#GY7mqzBwMf>)0+=Iu#NV+?6KpQj(wqZO# z?nU0VZ@IgX{KJ8nkfhESS6ywf!f3iicK!!i<&Ar8XPn6DjT)WsI}>vg&yEdR5ARp% z+Of`jlM=V|ABnhb6T!A`n2>->Rgwpe8{)~dz-j;y>)JvNnvB;j~Qnj-r~ms_CpjZ z?}B|0A}kZw;j8J37_PMO(?UJJ)w6AN-Vr;>C;`}({+pAa@V(Xt@|Mes&$T+oEjAL( zjJ0zLSer@1&=;HSnR-({#xd8sZ4>x7_7irxRQnr@h{b>(G#nko&y$Gf_|8 z-iUs7{oG1ZMXhhSR6%9$C&TuX$!$+6FHL_9?u*Z;SHFWpv|ju>kKM?y7f$r#l6%yN z4DLNoHCsxO_v6v~e36mbwDcbSO({URSZFj6k>9fI*}su9_&H?PKHYSbEP}PPLdJQ2xp61XKm1v#)Gt5t9V>_94Cz@Wk}WP8 zfbU|#?+t`|e&FFtms%m+{pkKw@|59(0|xe)6V}-pzRt#0oBVO54?o%kZ=qRA$D8uV z8}}Of$=E(qcPamjXVv|vl-BEM7Wm@8)zL6=lWf$}f(GfCSDXAS@fQzu5%74z$mhB} zi;q%Ix?>{)Ezm&l-E@_cPl&|sNnq-OnOO;r80Ga*@2{J`e>2VLV<4naOZE*tq-fJp$uQ6z<8i5VA`P~re z|IZYA<@+OGQ{m^lKDNIxzsRijy7*ZF5WnO)Lz6c!2ru$7;=Qa+UsbYHFt>_n@)J6% zlAoK`y?UGlSs|XvXT?vyikR9mjZ}s8vE=Nx+H}^`)f-PRxD9ww#Ro7|vTK=`&xoAt z#h!kDt0!}%rpG_Fe|J!+m&b8A{z(d3{{gS5thl$cwdCW60tA<0h!VIUhOhhc#y1WZtaevOIEJZ{~_dU?up_pFfb8-Az#M&mwk8dImNRJ|gBL^py~QTLYRa1hVrv;ANF ze;ob%aOf&GG?#R{YUTTzZ3%t3kFbrkcGTr&{Wqo29&Uk(U#;`RKp#S4fl$3v>Km8L z4a4T|$@+3VGj)*-@z2||?U^VraaSGTiqi%qx({JshJkOKXPrsGRs5e@r}FbPJSn1l z{_tp9GhfVK7Z?SEBW(V*Yj~{E(%`*6-3 zc;su0;$StPL)+vF|J`GOX4Jk@6g2oI?CAF{L;3u9L(Bdhw zmJy1{eMel>#Mx!)(l5+az>!;i>s|KtWRws+|9EzCAYtz*ul(Sr%4bOmFL7d#1g&Dr z#saC1lDPc%&5>mT@19#*aRD!{R?D2{9t549EHTCO?ZwLM-v3r2t|1xz`Ju%&AO6bLY_8)4W-Nc_#A1!{Zh15`CmkB9#q_ysWTM^X5BKHM<;&8Pk1r z2Eub6DCQod%TTGZ6f?x}Ftd$P#Ka(^+Q5J{!@ny6~1v>rV+oN=ww{-vuU1KNukarBCh5X+=os${|to z9UF-F!i3*QEIgvn4YUgW#3W(Bte7_Btz!d}(=0lfgtD{&{AeX6xMZy1fVTfKs433y z9eWI#jLRR5B(cRu@AZr~oXa0YRVz0kVbUSNnoDl!#WpP^jo&~FxYpx@ex=GpyM4M{rvRe;|IqZ-QB6Mn`#%VR zN{N)@P*PHnP7!Hggn%^CFb2{CMoUPCfP$2?lr++v0@5&Y1L@ev0b{T4{r>#U@4ub1 zo$c&CcRb^|9#>86q=jYxh-|OZF>C}gPRGr&H6h7b}7u~ou5?%D)g`k{%UVB_ou?9Ey5BH7O2*ZN1p009r zn(!04qmCIul3yv0t#*I9ef;^5Td|$b;C~R$y zjUC-ljFj?x4J=?YOiT>zh+O@6zgUX z^Utj$jS*KIU51R_ZE4Cw2Zf`Uv*INNEd=M}8DS{MS8s!Qj8;lV28!87Mt+)%vM}MJ zBT-_DUr7Xx71c?t6zB=@sm1E|Nu*>Aw0{1mnD8&i3@)Q=R3&J;e_c?`#Si1Z-C%5yFw|(?(hi&--Of9ywnyMGhdwxrtKz z=Y*r{f4iK?1cFsD_Q`%F&Tq`j$TWxkwM`Z7D8_k>c`<=wyjNbTHB5P%c0Sa`5Q=}l z=1q9E9WkK&?qUb>e&qVOg1qzpvZdu-0Y25{#8(g?J36ccz?AFg+>HqZ$lqWc3H|fD z|D%{2m0r(`{k`R*+mo*+SUtoe@hZ*nkR#CPBBbeP?Fh69iJt2KM)`8-A(CYZa|(Zf z3eR9;A3%xY;|&2b9so2~!u1ZTYnXfucP*Gylf8vpeZQ^q06;)7jN|ZZ z{_0y;H=et*sLVK`vbDKLXDGe;N0$<`VD| z8GfNC2)#1U{lC}KM=_V=q`Jzqgq${7pwckqak23#8xd(As z?lILsM+-KfY>=U+lZG(9SMQa|N3{i5mB|`)L|`&z7W*u~>$ien?@cgub)JHQCH+nZ z88$u-mfAeu-mac`JnL67q7+iqZU=`p=7@oaRrYE#$4S>GW{~xGc|YaoAr{;^X)_p(@IT((#_@f|F1@CxhzAMN{RhB*yOMb%scxhWe#jj!zEE&H%B&qXJtsJAo z&%POYe|hYHm&oG;hWH!#pz_XP9N}=4{R$=W<9cdq#G$&ozZ;J(qx?Hdew%!bm|B>D z&MSK<-B%!O{OIlz>?D%n=aPxXGNn{p=2fCaow-7v|Ls@vP8*DU5mmAH@@V4igLX)l zg;)pHJs475HE}5UmsPHr(>6GFq|H~iJym~3SnS!$EoY-k=`RscV=YeE34uFeVN;v= zO~`T21WKnr2P$NbNbOzuB(chDGaC~nsF#XXmM@a{f0BaufzYCQ>l6_uuX)()SN z_G$lF@2RrorV)77fw|gadW;yGC-Caq5DnSx|U+?R8Hiy7))H0wZnNycTinq;|t zbX1oI=K78>6Nh{(Sq+gP^DG{A*8TOdox)?f`SYeDUZ=|E;fv7Jn8P+tq-iJN-t=yU zulT%9t>9SNzq+s{UCHIjI?ihMVLXk6{XAPhQsKWPMo~gtZkZ}3J&i~At)AcY=Z#JJ*t}#>ad4h<{F^V=G_-BWUF<4 zs~<1$9U2WUEqGe|MpG&009HAbaEhNlU)6~=P5=7i^O3y1_SX@qyT$W6V}7#Xw-$$` z?)_f$9fDasaoqL32|kI;$fRBlqPQyLI91ULHh@paY#v|{^6U;p(8Y?XRhj?D3oOx< zp=`|bO8-N%j5Hm>nSX#G&jexpNw&hcoAb!SxX^yHh9|{ym?uU3qT2m7y~3qBNC79s z&^T#6$X43~c9Xu(p2pGbZ70jJX++}m87AA&$i;uszuTk|fD=wvl|l(n8cCh}Z1_NO z7{GnmFpED6D#3axNA(6#qUSQ4)<-iS&}V|*Tr*rBho%JX7fjmBUO4-fA^G1&e0fSo zDDm=+iXy7LpwCF4HZapP;ByLDO6;$@X2PJU_HaO>lqekO$=lSFs+T+B*5Gj^SAHeb zVA33?Y^K@jks6#3b)&0!KVnGaffoneV`bjTdR+~Lf}4r>^*OOfyTLF)?Gqx&kUPL% zKKYLTAqFzS`d03aS+_h(Rihkcv8fq%x6E7RM)xs^kbLS}FS}=r)Rv=wzqrwMWn-CF zCniKT$tD2$H#45kUnIlH7zYnaI!^##&?zVj+xaQ~GrINpfKKJun2N7iV?*V9mgzOe zh9JnIHTFUUJH7rUt+PgSf*SVHQf--Ak)Z~wR8VeX*C$zoNJ zZV%up=nojX!QP2@51cI;mS~asN;A+zhWGGbyZOa4Cse$x%Nvc8T>lPHv^&)3!XJC) z@#-CVAg~4{CxZiTTUgXe_x-GuBz)CnP5QWc@8b5SKH~az8+$`%KY4a}7>~Izxc!0W zb(9yH8EYNO$MR88i2dQsKW212Ix0*aB1)MT4Dk#NO|=vhRy_OZs&3Djnwom7H*=#P zGTz&R7wbgp&bfMBnJ|jU$?m4ARTxpr`-aJE8u=m<0dv;3YDLs+M>5xB8=ow1HOm-F zG9v7`(j7|W00$h+G;%PagBw4y$~cL0bI4o6nyR2xKf{dzA*lEl-tB~2zot!0Z9MI_ zN57DAMtoEbD%|U=3+~FL!7l?0I?7z0-dw7Egnc<$sUJk$ricRFhdltW?!g4|UN zx?8xIYu|pN{gQE4W!6gDgR}#3O^eM!GrXDv+!Dbd{v|!ZA*&P^`bv!DdQeRh{!ukW zRTNM)L{>X^J0(&(ud)JbzF_QS>+Qr5IH6ucFOhUIA zOp!?GgqP@SGA?MFhayQIqz+Zy(^2^M=lf}hq_HFE&RVw^mH}10z;W>b7!rpA4PZo@ zs+*|vMHU)A+a}>xw(skMUKcZ>Kqqm-_~^T50l$v$$}rx0Zrn_ zO45NuPr0<*PpCR{-C{3th|Np$^K;ii*oGqq@6xbBt5RwhdGP%sG!t|+aRX~B&b0kJ%Fh(Io|J#mQD{^^xj`<#w*u7?jOsI+ zDZBp>5K!`8m}29^)(~sJ!jraxhl*y;q1%EfW$kVHv~ng+NkF|3!5gc75@zz6V1x5| z{tz4y#Eu{H&*(d*g#BDYQnqv=f~n82UWw6DxTjN*DPjSs_{iV}`~(xsR$m7rXlTpg1@d26!ppX_i-F`l8>P=jrYzU6=w#@Kk{-WZx z?8)ro(ekFj&PT&AET8RZRa>8Yr;p;*{3lKqT5_+)XVnFrE|($ziN7JWxhr+UzMMnY z${0FaO>#%X{d>Tv#SdSjJ6}w{Cf9FPy)?N`Ey;N{{z5N$x{6>U(f{!;Nfy8}SpJ<< zG2Eqyr15VTHpRPr4mX; zF#B~+?0kbFMhP{M5NyXkL9m<71c7lNDbk~_i$(u>KPg^bv0pj|#KOlkN`!Zf{wQ}n z)*qpKVFBM56}`LgjxRZM*Qk>2&5+t-0hw7zx^JcgDS7k+UaUXQ*hzGxc2qn3gDppX zlqkJ-aYbyJoBvFacoQf0d#j1VZPij-n=y%U8C3%{*Zwiu>}gf8UA4@1UP2yisJi@o zUQv_sJE7V4>Y7>a<$opQl`q)C7+bDSE%k70Ul)T$EE{M`*0;X>WK}#{qQz$a{LU&f zTE}z48x-UXUnzYPrv5tN{2;?~&w}bUUikb*%eZhl=qb*x6`fvIT)e4IpPj$7Y)Zn2 zKe!~41j^hq$AQUCPa>WR=iAT@_MoZYyEs2g?Eiw*a1svd``LQE;J;#I3^~W9sTvXX zHUeP=^kvVjsTbrmBv_2P!5w@3z2&NWQbtO{dLs7};scccGi@x!tvmPucC;r`?xGN3 z6wBb%_}9GtIp-%@AKR5U5f@^sZBjYNmT73Cp&jYv6oVCPe2a6dWqrvc^pA_}l{RdH zyCV(QcPO9^11=)a!)S|=;+>X~D7aV^w)WI`)~mE3HW0W|gZ+5Yc?+-J>}fpSltL(8 zX+yTJ@`j=1If4H3e}iixqWS=Q2EwxEAzT_m&c-w+P@k=D+T7CI#IS}iyfExB7T{{eJG|ZfN76*o#cKnj(4x3|D ztUYXe?o0Pr4%Q!#doYb5)t##W_J>~LqTr=Qb>jP{rBUwo|sD{oA&OU50yr9$2l^b>B59UQk`WHr}q zih5o#+SL=dV}YLk=v~1`R9KZFY0X$5^ya;IK_1*V7u?Wd|4mj@>`fBQ%c8>8_&*Uh z5r~pCv6DCBQ=$pl#!K!z9a?X>O9BYb1`mQ>Y*59=;zZyyts8aLdus}RW=)y3EPF5T z^ce1+Maq@Ue{E796WF3D%x)8BGX^Z_LWvnW?(c<=dn~zHJ*`@Un@zT9-AH30$it)b zxegKZal*fOSMSt@Rs2F->8Ci7#|t8wYy~l8E?w6~J&2Z_Ro*Gtx3$zI*y6jIT~tR? zx*@RZm}_e-b=%ql!JL6%q#+>h3z(RK(RRnd zETjlx2<91Hk?21;I~!BU;A58Q)YxFqm5CNuJRW!Mu{f9dFz7ke;xziMYoD{#!f(*E zxKte`)xEp7!k-J7oDOcjC^gw^V#HlPnA5=grTAqMM93DkHKy8LneaCJ%8+`7X<_>@ z@ue)_{0Ti5mVF^qz;;#f+tNy6tM%n`zN@amBGc(nW!|LJv?Krdmn9l@N!yRvzR%l1 zA9ML!UTy}7UfGf=(fyg<{g=m+w{KWcS=9LD(Tmji694u>&gZ=L17P<7h+aS`Q56AW z7gy`tqhex)Ch{jB@fYI+UB?!F0bZjoSqJ~lL(7&`H){wLk8^u*kP&a03XOj7*_fmv z*H0E-<>8|Ej6BZs?aB{kF9=+Q7M3zVz2m_>5#MV|w{yN*e+du!sCMljmS5lK;EM#@ zw5*0}H{zSYMJ93l65Q_&@qy((wd6Q-{=DLu&%~JeS%RBmb)#uvram%~NBpygVpNCa zuyLZQB8J(`#j=al2caY^S}j@yLJ^=wPZ z4xk}JR|8A+7z@T+)ZN^8oMdMFrpO-6;$k<%m)KL8u4SMrPdTfMCk1kn_&oX8J)-OdKyvB%y?x8uE)#9 zKIzt(pBbt#neX(WQRSWm-HndhOG+smAD7lk-L}@3e^La>gNDlyAytM1Rh;C~nOTTAk2tP6Vea1&kI%wFCsOZHbO1ZdML zKl72)Y?v~7ixIu|{-^O+0};I$nN65n`~EHn%T3b2Vv>;vWC%rI?2qqYU%EtXcAa>? zNVO3Df%UWfHP=89QVxUSUyF!*aQqK&= zhZDNNufe2SKETQp>ZTW`()m z=GIF9m&#-s3OI5b1%)ETR$kku^ccuS@`C+0Vhl}KUt2n7;JF)pfG#i5!19qP>+7@O ziwzGqlKp`4k1HIkWIkhFAAvDyTD9|~5kkAYw5TC07^0Hd)f5P&tJ!{S^kBTbK)zut zxJSUEvVJ+>3y}dy!^8!au;jI>o zeT4v^%lYJM(gL+q`s-RuKra2T`rkSOY1|yUeod}s)H^K+W$b5E?8H56%Coad%^rzs zmy~@A+R%y29_F{SRuv>H=VQ>`d~D9ms~ISqL%baYeeq|$$xvP*-pk-6^u+qTS`R5- zUXowGIc6=^+njfKU$_beF`W5f@T+AO_rx}bb(TYLplg%PHoj{)kWcNrlU69hsR|Ye zW$vfew9WuX_3<55Y-*SIqpbtlo;x)J%a@{rf7To&#;@Pza8DjGXrm8mlu&Z)yU{`2 z#H~tS?JSt7P9pd9cUn|pt2HaYKO8%VXAkSM>L=~c1GOe{s(sXE8e7jE*>u5v(UNS( ze71=lo`LHYV>2m?UY}?zV>z7_i%g+=n0s6{84o^g`;Hk)?-LR0lnsd{w*)a>Xe)E{g5 zJALMqmpor;gKj%x+R0}==t;OSM%MpyK_J7#r=jHijYGKXJzx zcCk9q7X+Gy%8LE4Sdr_D7IH0t+-e)gC9<5p562nbc@0X`_$9Uy+}mQ<~eUI4FtHxnVRz#%>U?>HZ*VjE>&EaLWB=RFwzKpoBJt93MW73 zB`4pv3ENj*x!Z71?%ts}_pM_aK|<0$v=t&{N_7yg00i~DTwjE%lc#4GWon_5&$ERD zn!82B8J@t{ZRb5d6k(^k8XNs5A^?*$3QF}p0YahQZA3p&CLTSnA+PV;Ys1d^)o|=6 z0zGYkUTz5r-)O=H=3(88pqf1`hv)ly5}98-2&Uh>BM|8bmprR_Ewe^|m3ZIKgbl5R zgY?AYqO)GgQG05+jtxor(eVF?r`E;%Gc58k%DCP=Xq(w`wm6{cG8m zQ~5AkY?1Y1<`T&B?MU-B2!`w}#>L51C3-{65JQdhRoGuq3rM`5$OJt*D+ z&zujFRmexcD6a}lhrD`(L~lZg?jclaS3UY}4=9U6gm;4;qIvoPHFXk^a5iqVYrDI3 zW;<|!15|y47|w^!{0PdE6kj4o>R;ww4wsq}1yL!X$|*c`FkERfa}tR5!5HoiN9xDO z!uZG0udjWJcQZ43K{N=9Y=6Mql0%Ozr!6OqN}nQanqpHk6ER&@DfkzrL%=7sRR!zq zLy)u!M&QfPTl>hh7(or=H4CRlfxz&L*ZZl2Mkt!!%_&`G&pClG(?ufKgf;#Q&zFlL60%NNJM4@n2YW`-*54HK#$PpJ(*Hb8C7`I zTUzx)P@%`&697CCmX z&B>~M_^{qibC@dDQCWZuSDz{26Q`J(u!DYADNOyM;ALcLgRG{5MX8`W+Kb?(=r_TT zUpWZqOPz@E0$W3!0V!@Pco&tFY|N?CdF(MMtXwOjA0gQ>cV_&wd2)SLjQ2l+y7N*Y zXlKBdpC6Zdc1{#yMQAZjp=tW)=q#6R#du*45jwju>3S}bvis=I`%&@_idXM8DHkp) zZJ3?Au+IM%&1>tQIG)e>=%eSDJ6p)y|Dt)d0f=l~9vK~xw}MF)$4rp-{k@=ig8#ks z;2dP~tp!x{x?OcHgn6ZN83^p9t_6zaC1lE(j=ezMJhamIKSBwjsU6T=v9HY-VGw zm%-y`8MQNfnxFg*U_tYy)qO>s&d&)u+PIpZTBG80YNJDCnGgPJR&V@|pbIQ^D)7lI zZaeNA2iXNh@QhEk*-&vA_DDsc8b(b~&#Tb|+j5$*H#PqeXf0jMzW5&JeVD+9FD<#z zIDfT$C_sR7PL4DKrA7UI+z&tujijdBY^7YQG$UgCl1gup#*80jE=z-^Ty1Y;-)aGK zn+li9<6DS~PV;k~#k}F)!RK*ud|KkNg!Djk`LX)BnCSt(+-Dz^>JuBn#&X}PEG;x< z_Nl|Nnr`aA>p2$x;Ow8=IkvpjVYU``!YvM~|5u6S5GQI+O@f!5@sf1C-)!gl)_`^^vE8-G>eV3YE3nHqf3{M$+4-*-|+wuXEc_<{vxN+%}3 z;KSpltYOQFsA8wkqO!4Vu3wx0#z6?YQV~ZOM{Z?huxM<1??q3dyTORp;6^3|`}HF| znh-ExWWw*}{r!CO@zaB!^W>8^=cS8e4ssK3XLc!V&Ij8G-bl#8w=ui=6~qJg$FyrA z64~{8QL+RIG>VVn&y|%E9~hn7I_<^W8ycFBosQxZQgIq(^ra3{w14noE?h=_upQ1@ z!_>#dIrC5VpOe3m=~Ds`52?Xj3;qoX-D56IovYfZ4JQu8nZ}Qh1sqvmkzDs{Uxd3OgE2u4(%8E#DEEX6U#we-+YUVWKW(bqnHTtkL__uGT%y$N;&* zBnas3cLmq^|IYwDs!K?v6gu|Hz83zDpI+yp+We34lLoaD^sC&s7?K6upP|won?%X zi35&{skqFyC>MJH+G$8dpQ4~^@$yWLt8(oNqov>M30Try2!NsIlN;Xxb9}$Q-D-xD zySJY^#<0Ii@IWx`GDA``B8i{qWZT~}+;Ys=o-FG{Wq3}42*h;3T#j{9xhghs|dW1&8o|Ztj0?Vo(as z0f%%!EUPPT$^~1UXbP@v!(%o_t#>d!^sID-og6!!R~kVN=ejhjsKs%&X%jO!I2sp)=fU$O_NM26K4n)>RMoiwO?2==0;OtTPg~~bA))HmzSBhK-}WO2m!21) z+w_kgcX5zj=~r6&0D!qnd}B$aWG82Es=>wqMn7zqyOa8@ZHiAq$ISl#alcRcwXXuw z^&y>yJ;*j_pz)yvej&K_He!?7%t<2mas5JrjGvBL-OuAML^;wbK;THwDo%R_z~BmF zc`pxRk%^!262M3Hgem0WoS&FA+)=EA|x zrE~A%9$;w-@Z$;;!2l{Kx|0=84Ojcy!E9l%wj=)pBOF#O>^6B^WwNEnq7G{%7^x!r z^@LOdcZ{9h=%j*MVG_fE=)T0LRcf^P;d}&O6(Gk3qE=qMX$4d^ioY20RxDn{fAqOS zM@e`fjRJspfW!Ya=w6#SrnT23C<5r_?*ok2T2Y(FyH37-p_VV;WbJoCJodKP#(T;o+`y5Wt^Qv#DNP z6yNy=sg*tHB@8`yHK>6b#4tp|4KRysTsNS-on}cq z?U0_G{oNCf!N*%|SK1;!e_Q;~5^GUNIYv+!U}m=unK4_JD7v4!faDHa{u7MSl)W=| z`J^D?_t{h059ie)34Z3ylEa6q9l*g1OLzim0;00)3$XG$F9^K0!3|O%lPhtALNc>! zkbxXzhoeHD+W$VM*`xa`mz8vB?n4T>X0y~!*#G&1ik+vP@W^^dZWmeK4UgO;PYU{0 zo>YJx z5VM0ah*Ou?iZe#^Bq$2$#;Mo=TdwE2WuKf|cQp!pzcH;X>XRXCflmV`9Od5oCup2vgwb$2Y- z8{BW258)OMnKpi}^{cuSKb}huDy>D9YoiGh zq0)JI2F&4azoJNkx|u(G;+@}Edn1!4-2b9lqlMjsWOdPcyHytILO2<_kMr!-67P=+ zjp76En?2b6?tLZ}Iq(Tsq5>;hi`;6{BIJw0uFrCqD zFI|Nxa@vsrQ2p+M``iep3a&PJw_7x%+XebBstYgHXwWROYau%QO_4n|g5NtOH`_PU z1rUo-MHGv+IC@)>?B?HGQQXFQ-+vV3-4fF{;2St}+r55W` zOHNGV8k?w$d0+FzGMEv<-<*{{9)@?tX0(5n(Z zPtTH}C$pmMs&BqDc9XOhneEJz2e&r9S-+t%@)D-r@3@Omjly{&`L9G*0(x7%m^5bj zl2O;HEeSHmc_a{Vkb6|_$J`KIT>s8B!6vU)+L&N-129H>a$?=I-_K>F}^w-q=yjD(W;%l@FJvsLuB2XBW!uq&Z% zARbV0SAnXHqZs}X+m6DZE~e(yu{G6BkiuOB+i_vNxl_D_{O{^NJn#R+O!3;8Q75P5 zv8)@dt#aR1ogW&C%`x|~5xj&b+RZcLsUbR3@_)%*9BE7EYM}b3J>BaXs;>!6QTE9{ zAeJolQ0DjeWhFGxKxNr5yZMJ@lZB6iAR)k^3_GhHD~X>}?>b|dUtv(FpKJ1VC|hv) z1@l$cQq^dl=E+k3dsr#N^y~|1ocweIH19bP4-v7^AcOml4+O*Go>L9I2l!Wk)Hj?z zn)<+WAo9lg59FAh*}asc(iMc~rVsV=u2jT_MIA`q!bUk)+{Qo|f-n3I>TP7}|^RSGBVn zrv+xX7_|xQ?0uA=$c3o~9rX-C{)*(e+J?eZd#}p;=1j$bYf=-!rTE>(G4YuDY@$Hl z>}+BKYNo=hE*(2&R8s z^pMYe@^8o_dM?w?*Ppl-M@Bu&Bw*te=@unGf|_wYA9f9FPNLf^E9()zz5K} z&C;7pvm$&$@$AlTz9%z;dPjkxu7$-~sltPvt`I;wsBrq${`ckC_6!SeWoI>{)-N0d zZde>uWh2DoANz2eRjY&}jRy8>VuQniX@0Hsx+6nvnRkrqOvC{pM5hz~Mz+K{I4<8% zHfz`GMkmn2F85BA*wY5LS9J$4{7E0KFX!C4y=USAI9D4;3~I1^#@~_gmoaCs*SBwc zNq!5*fCz(R;heS8=b&f{M)W|uTd;646k>yF4OG(gmA5b&(OQv6xGm4$cz)k}CKyXb zCO`PqjOux4>V!r`qu|7!kE$Gxt9%bvMP+$H+upvv{p$ks+#7)F5Zf{~0vE?ffsx!p zo&W}L=05_6oxGpw9n(fUYYW-1r?tnQk)(WbG#Xng$uqu?w~rVit4|)+mfLGT`_p0h$KT54`w3*H zd}7h^O{k7@XM=Aq2)At6lUzf*tQaun|iv7fC2`Oz*Ten651VLporgL_si$ zDK&92Jmpj85DgQ*A9cTLB{69l_9+b^s;#xiu|3*)-bScP{bFz^kI1kdYOlp~!TYs# z$*i&GWuMys)rO@8oCv5af^i?Pm+Qi0I1Q{f5)|#fm5Op)(wnY=Zr3+XyRE}rQev{B|)A&XhfcM(gqvK z77s0Vp7)UJqtAKPgkdXU(U3S!;aB48E0usxNr$%*pdnp|F0+TV8n%YAuA`w>z%zEk zX)a=S&*NS9OyQx~3BKWe`%O$!OVR<1A9n+6{MLjojaW-z;oA6d42uLs zloMyd>pl;kL-`d*Ggft7AqoLlL60e5B5QpV)hqjxfMURZycIq_z5i&%67eK{$$5+S zR4_z~+tw7R@KnfPCg2=kxMX>E|g zh|7)J%fSgIb-yANZ$bTc?Y2e=e!fI&_^)#$v1o^GlcIV(XOoQR69^Y5l5gY?+Z)Y43>JlhE@a9|tfHfrFs61z4yAD)-XA+=xCFo?-QlFDZ`rG^pPdpoms6| z2T_#&kh4q30G@wp%XDFlsQumNq!dV>UAXUFRIcvf)fnn^2-Z$meGe^oq*mm^LUejo z2@oXMijX(_OTEDbtNY?9IL=91n46&9`IF{EgIR0ypUX)^GaYv#@oU<1k*#?`KjuGs zQf7O9u*V1(0s}3P0~~PotO#E4;NORghL={R{WOEqO$!NB9}3#GrL20E?@g(&8g)EM z7b{UT&iVi>9M3QNP93jLfb8+`Zi(phrgTJH(`5Bxrs^l=cie29l6ZrOg+1w!McA}n zP5YGBiadUHqrGO<>}^v`&yB$wxuDlz=RLR*%I%@(Jf6R9@(3|^tQjE+A)CDsb&l?8 zz2Zn*NzL49Q~iKk(c7C=)Ks4G9u*`(-RR8;ejgbVa1>g3YpwvJ`6eK_sZ8L9 zj7iV0>OoB`8 zkRR<+M}x86S^3Cvs>jYWJCDp)cYI>JZUp6YCoA8}uCaUce?@(z-nsDauWBvZmnIF% z>a(EHd{)_6H&R)*qRbqbqsEaMWr8)$Ac^YqhV*L*Vu#oem%3J-?P1Y(#8!f zpIoQ6qv6TT7GIBzaH^%sC{~d1G#nVKx%DD0BfXk3dJU!T-atE2{@IWiWpXrGr-q+Z zRI2SK?Pa=!;`z*+SJ{4bHZnQYOXe^>2~dW}S0^SkxUWC5P6-xQuO|LSipE0kwPH$+s01LKYJtzQ^(=cYTWi(X4N?^gRi zgrTY1M6#oJpia9+nfx%%UWr^P+y|=2Hany{3^DPE>({AjG)L>#zy^vzbULx5;9!xe za}FIwA<}vp?uMkIb7lf6WUivl=+64h`d`zeUr(~&;pxnj2RXciIa1SyJTm}*%?Za* z?vz6V^%LD+;vapV--IDXJ*^qOE$kFB9(oc&6q79L`4h`$8c(E)?t!!fPMHq6mBE1I zH`<+#J*Ri(Mm8T0rZsyW8sdy@GmxwzZdAs=4fPUf6pPf7(2UYBJ}O2x{A(oSe5CPd zzm4#ni!4+);;;b})kz^(g@58Ck!e!kl-Xb5AG^yS+yqE}hz|tRdOiCIysj@l*`TYV zg^R*_nZSLlFLfN+&>i8(Ll3EX<>nkhuAziwyUBUU?F9apNE{FvFIckIbgdGLTmg2B z?dV)Hv`UFDZRU95qdW7@$yD!dda=ZRGGfnk&2=gTNI46uylnKdHfts3VCP=2C6%+_ zqpZ(`+CD0Up>6Aixl#3<Eb+n z{q`H_w3MxZf0i$6H;zCW)$9AhG){AkphvP2=*!+94)LZnn~vr=F^mIOs`i@woAzl= zPP)h4U;K6M0)6YA^mamnphz$UR=>+1sK9eFbBesn_I~u7Tx^d{9DPmxru{Np8$mSGR&Uh)zW?kbK<4U)T6yVcALN7nSKYdNCOpMF0eOxcy`E- zY;TH&+RRjnRTJ~JG`#%YlcLH;)f}Jr#k=aYIk?}4jd8w%8e8VQ#^j8UFO*gMP`ct2 z@8*t*<#&3k`;{vhoSN3f?wxnPG7k&$Hn+huSmYL(?czE99*O}1--4d&xFn~L7RKi_ ziCIqUAA&CYXH0-rQ0AwzNo1ni4{Z2G^(UNaURL&_RfIZly#`*Vj!e0U5Ro6#}WqvgG3N<6$(&s$x_uft$ie&@;%W`fV z8-Wh*kx-y)_$tJiV}8HwT?WE3#$<$=bCi}~YehOFx8GzyeD=umJ85Jd+BL(ex+u4g z!bly{7$M4FVjqRNWfFXi<>dKL8w& ze6Le!qvlzay>QNa^u><}wj-xO`}K8k#x#IRqysGkfnZrSv6tW&So>!_i}Ufc^P48Lyu>m!+nn!h46_ zaG?a30NJAo2RM^`;RA_@U!8P4b3a&$eYs0B4|K13aK>2QD4Zh!DW2JY6yMIJGJSEM}WJ$<N4 zVL!)+UU|fLCL`*f3O9F3POyd)rti`w>2rE>IslAH#FxM!cl+Y+CMF`?rDYBG27pN_F&&2G+bh@P|1Iq)FU3cB0Wf zd##jcYk#5vo+#5Vw}xVSFD`3cILsX1Icf-#l6j=i)Z8+Tjw94yB7`3y*2h zZ03r6t`OkqAlg-sr+e6M_duJX1KPJ+_37fkP^W8sqmt6|8BdjVu!%Lx^Fibxn72Ee zy5FmNF=hSwVG39eJQu@TsSyV)=K;`VnriK&Q|VzN=TC13aKULZ*4NhY&3dFfplkwF z90)DEt9Fl=W-7a(CeC-lByO9OH9&_b-%PtA=tzpBY6&Tf%);s^!wGjh4OFj_*5Qj? z=VipvPbk$WDeuX7s_#{h&IHrQ>aNqHixcon+x;e)4hEjZ@U?9CQ2*DX)QoX;4wl9OWL$`~=Sm@++798epy>4(03oAHWGHK`!iim#zhlG>&eaQ5<@ z6`=EYg(;Td+a(qaXF2Vdfk9KW1n#NBs}!=*ijAg*8JZDG!DOF0ad~S>Qo7S`o2h%A z${wh^P1H03NNfMtH`iNSCdYOiY(7vbc^5qq`nzTGdM38MHd4~;#4}FcvD}opd^V>H zy)-De&VRGNL?Xe@`%fJqq9Sbs#pn-Ouwf=X)d!?HP*g`BihUMx6|&N)^d#%)9rfPt zrDNZ&*~pRiR{Xc^Fq+eRY)JLzxgXo78AjLZ1Xf!{>CR@%TqU=;~&~$1C(!nDpD-17n~vWHjV$rk*j{OAYON_-snaj$okDvEAm2~Xo(Z1i&AgEhyuxRH>H z?rK9cX*ir;;nUMb9p>Ts&y1w-*m$n^OA(<%DYO8&%3#mEUJiE>RoHV`Pu$nU@;Go07EDpke#eyz!R0WoPF>` zkhaxZfo3B{GPyFp>zTRYK72sD_bG|@AERq*5bBUcg~6^=2o_LDkMPB zZUkqrQ{D~M*EbBaP`xq`_Ae~Hsoj70KI!@Wb$!QoE`;G-$J&V1G$r}Zx5*vkyC7D; z$`H9qgdrC6MBdzF?Vbm`@uUH>FhN%aBq($Dv>fmwmPDMlMR*CU%=+NPRxa{TMrX#G zxtexgIsuq?!#fAbnx_}egOdBe7ttVC%cE5)^oz`=b- zmQg8A0be$b8s=V8u#eY$N++d`aD(l}*(z(fUiZNcz)C#Z7c=Wgzx0J9+=;x}IPNx`!dhAw408$ULj4Nd=vKJR>t4PfYD~xqn2hwxpJ^7s|lCku>nCa9Z zYC8|f2M;(AquX8ok0B2O9mdHcZz51L^y|p6b^&S&K_bz6tA|frQPm@o>DYaH1{*#5 z!OAiu?5u&o$d?^x1-5txkC*0H$6loNkoY@tg~?aHv8dVj5CYygHca|)@ZH>oD&7+n zZ{m@ z-v)oYFXqh1sD5S+=cXw%u(Fp7K7R-xK3Ax6cu>dQ>^_wIb|TgAk>|PSI6ni^rP4RW z9bT6^KcD%0!1XsH7Uuwcmq@@|rY22Lib;(W)_^W({P!&Bu9ytny2i#wI(4E3=>cpB zyKWrofntLL&Oakui*`SMZj+t>RCA%hQpTytE!8{d^SBxmepz*s zZ7XsH9vWMr5F&Iuk6-IplmNVtha?Qb@tv-!$Qs^8{(RPni0ciYr}f7sfn-d_l1K{# zgpfYbRgA8JrDzpW?fIpnu%_=QEt%TlRvrF%0?Peo{8#+M4-Z9_<& zw70`ZPU}K(3RolVkEz4F+zD!9Sm(X)HwdjzpFCG<&F|$STjKOLqUU9!;ZR3^UwU5W^@C@S z#|$=QO0QliJ-d^7rn)Vf>z2ZM><2+}`%o!!`exs=dgFS9%c1X8LocY%V3lDZz^3Ge zb%iQd*hBt0xOcaiFtDA?muwoz6!5?&BOqMWSHF8C#_T`qf0xW;Cui|k>gc|wON|`d zfxxm0QHnX}jae(%SCI9h+P9$Dez%L!t}?9};w9xj1KmB%U^jXnBh(m>H2wD)giO9! z8|u^I(tm0g1V}>7L9w{n6Q|#vmo~SE?Y|T?G7kKiOyMIiC2|T2--&f#;pG+P z*A-MQ#E$cI$PcWUQ#SoEexCIYKA2?b=_wz@(EXBqdWL|}uV@b_vwX)#-BJ?R zfLfz2?N>n6?$qR;L_cdGC%mBQnoWA7J!^pl^Yh;!?288G|Jo!nx(!T+=l$z{%vi1> z0*o6fm~k{!^go6k^cjRiG*JN;>z8PyMb>GqTGzZYs*uP&&a$;Nz$Rst(J~g{U4zJA zxxp#;>qbU+9IZ`OEtLPZ-kA(_Oe6mJqY~@&B*#Wzvz>M@xQ#CKTV4sE; zn(Y21Z6&v;D;nLU;)y7eHcSHo4MFt+`NK(*AugP%-#Lw`S0FoRI;t>=sD zgQ=})6{WG9rm_+V4y+(s4cIZ5DoDVvQ=cDGPHZRhCo=lb-=ez)LM{nkBL>KOx!OAO z(D!n9AePfc9~GHbnR}Nb+PT_=c-pCIq!|;Ee~#>MR`U$aGmya5r1kqQyJ7F1go{3X zZD}9q+$_K>NdAp$i3BxN4352m<{LH4MLH0MVrv`fKgdT}K*m-RmxY~}$jOx-@m`S=;b?bL;ELP&1im2ti+<(qSwMZT{P&DXZ{ z)eM({1F1cMelp{Kj47yO8iOV*{5zDb)y}DE-H4R-gk*EN*C`m>E5teFi@9uTJ0Oy7 zz~HGOnyUSg^-|7)hsqEF;&WR{UqjP`Sc&}TA_Q)4pw^dFrbiRNwa#E5@lUEe5LIMt z?()O!AHXnu%gloOFUsFhyp1__n#{XI<_n z(6o0yqc4(9T+TX?AXqe#($RU&(=pX7u);)wairsQkC74q0JKPj*LEo$O^?B_ukFAL z3%&WQl?kaDT2)F}k6ym~=NGUwzsj7krD|`!tc7yT-toM*9jE%5){o4j#T;Q?PVD)D zSght@X%fo|hO4t1NWPj{*^zP^J@$U}K|G5?)dXM&)?E>kTFs;Uuh~T17yL0ex@*61 z!&Z%?`Sr5v*~Mv-r|&#;A8+P3|IBu`diq-Vx)x_K6Hx{?x{W6~~)!Rk- z(HH75Kb=LRvSAAx4P`rUUr2%Uu(8X5@SY)3nqhU72swZQU7p$f!j{HYV|>&|dy%_o zPA_HR5gb5~ z>)c!)cg0<$GrGt;DTtZr)4bl)Z1k)jtL;D%t27;lIP6jHJZoEd1)u3WKHmr{cb(&Y*M7~g7)HMt zwe&h=+swFW+RGzN+%1sRhm+l()#rqxOzSsCGM4@6*ihhJtb0Yhgo^tu3lUJ)9bV>2 zyHiZOrwN#Lj=ARDL+-<)uhM7dng6*7g!&9x>2B%U zlP>P7E8>U%%}IOqUrt|-XB@6Jx*K(A)0Um2v|Yafjt&y4XH7qj%0mbiE^eC13^c;c z?j>hF_U!lZL$j3L&k>LJagv3@pje^w6uPx;g!)v}C@GEy8KizR`R9w3zU5(%XhzIUr76nRr+g)kVK(al$-T6S&Mmdr@{C zqC}bLfpWWAMW5)N82cQXZAjKfe#NuC`Gjb_{eo6*A^+fI-80rJpPL1c^^mzwxqEvc zhf{OfF_>fkrHbull^lb=2U`rwc0D6s!k^KR11*>`sN0C{P!_lx@7-RQ*U-xHSlZxt4?p3oFq&4O8=?gxx)d7NnS_v56c{z1?O+wyPuV1JrBE_4%05%WjvAI(Wd7X zS260G0-pyI4?LAk796YCE-+ExUST(icNgmSe*2A8KnNAr%ye2W58+<6q{0ZhKw3rB zw!%M}1c113Ri&M#6dMGk$v?(^aP5|ZqzYR72CUv@hb4k%W#0(B4oUv9m0DlbxGEoQ z0{4nQeBn_Sc#FF9^EC4AZoRf$@QtLg3QewGi7yNS_NDt9rq@_U`}#haKk0Jrm0MQW zM6(>kyF>J*q`sI7P2){=3L34gWbge93_)5uc#0*MeMWU?I>vPo%p#-@+0LJIS30b) zM5oUUZ*31;Pcu(aK1!|NIj;fwf|26%E`GjOcB-rGkNoV4#f15}tC>u?z36U84lcQP za6zQaSw2%MX*AxKIW*uJanht%Q(>YW#cN6R(W}8uN~&vqGc1D_h~{4_NNYLwEdfp8 zZ93o@g<=0=h(2ud>006;RalyS%!}W`acr{qxlpo0l;;O)Vu;Eki{g+=tJfRI+_8S1 zSF{S(DC0 zk^`a-dF3^%y3?`k$t87`P6?QLqZ${pu$RuOQF#7yz??Io39kY&ZUialufO0gpsFSf zIe4o9L(#SFBjarsZG%5Qzc>DT_Aj!=d%>(EqI#Z!y0VVEJH5M0lX3IQ5q?m8d7ZC~ zm^xD8;x42V!FVo>`A?ORPFhDAB(`pd@!7;Qg=gDO!n|Fq=k!aSv+yu{Ez-`7XYEp1 zOX1>7A%m}`~VTv8r|7xVQvmTKS3mbCNQ>cwENuYNM66WfLsFe-0{}<=lpMwqQ<8R`1w)&qn zcT|Gds2*L<$31+}k?r?p?51`cp`0+YAav9Vo8~5~lJ?%-e@{oxDq8t3iGOI!lBI?j z`WR2pjLE{rq=e~f%k%esMUXzEiXHR%C5XRGM!!!zfBQ@$7KtH%80KdYYNXym(q5+} zGNnu}BW8PNoSH7q2`drKgob!dgQrI<9>zf;Vg+ zhsrHo`JB>!xQEDe|GAj+_VtsQ_~uE(3nGY3-f~iiZ%o|W1n!u5Fi)2)8~3}2u~42_AfWSCp=M~i8usVa==fBY?!FK3OQnZ{%P}6OO{1$Gff#% zxA(%FUdAoa`T(QD@X*Wb7lQs`H~=Wlh_xcoi z4T`Dp4@qNWCgg4GSk(cWhqFSZ>NJ6+&FZo2V8e_OpGo)QGD=n6Jy8GoR-y&Hqj~bs zhF^C=!5#99RFx??99v*BZ@pkZ5L6x1^>g=p%VCY>V&V=u>{o|6;aAZFRA-{Yc94Hz ziTN*@HVG87ZMYY)y;pyQzcTS-w`;rE;KjMAW_5y(jyQ-lq`=@JnB3`bxL0J#00Pzt6!I^)a{f@|7^%^S$LLm3T886>c5&%7> zaRI|aE|`k5WqjpbNh0WoO`bMuK}s-7>CdNszYWwVCq)AeZ!WcjkuH@?JtfV{lXs7D zBQ3_+@ky$ z2)S1yEoe;qL`%#pFsR%~aWf}Q=-F6oSZoTb?X=aQaX92@IR0?J8JkG3$o_HphhQ}dYoW!I+--KBXX<9V_r>+X zSPIX`KG%sxF>)AH8_+!hq85LLuvNBRopXv*XJjqKEV$IVpgFb`VvKVQAB5;w2!0Y? zId_}e<;+`Uj1-mSL<(_(I!hwrM`97$iiLP-sutT1GKMA`~q^; zDkwQPG9-E+U8B(q6Wj+#XiXZ@hE~NfOxQIqvH~GLe+JFtM5(BzhtN6b&Wi!XXsf zDRoKUWqR@iYA{~Em7Pzq!qofbfx1>A)OsE6y`O*bB)}Em9UC?xd}$JoVFp{wNoptj zC%g%;+tJ3~(1uOoT{l{rjjfnxcr;=$bEu0Oe87ioM;hNEF%-~+J?b@LK@MY!GKtGV zR@a5N-Jh>JP9F5_>e3po{_-1%&hqR=h4DeVjX2;+1hH;5(E+o`Rx`q))GZW?%H&RB zW&Jnhb<|AUTB(rB8EPM&BxPCBPf~Bw5=}Av;9E$a;H#X55T~c>6;Nz2OU345s{LA* zkYvO3AupobQ2eATz*IG-?+MSB6t2&&lI}B(W}PNbgYoD{$i;bzF{u|rv|%)!Qs*Z^ zuTTLSh@yy3<1;&^GpN_#8s`+j6%yr zR9|J4mod-myMMXr5Fqu~b**cwAqa5l)ru&wy1DY_2`wG`>{{ z6pM0|j!-ojyeJF4QuyZww|8lj;w!Jin>ZssBR<3}a#ZXIj3z~*WEYz|Ls>Mzn{+3hr|m@&)FA%JX&R>0ctzs{A*r;$nb@aGh?(5+t(3;QPmT6bpx`Z>m$mM;8491{ z@QgY{I_fE1i64S|$6fWq3Atc1;(b5Wt69O+*q$E4)+HHJtNYjOUxAln>@LthUWk{&A;tgt!Y1vfZ^Yj>9dA9E=1FT{80Qs}BNo zL%E@dm(+M7CN?XKKlDf}tR8yeY%9tl4|4RIj+5K@`ZGDK^Gl+et z%)a8s)1Q8j$e^__se>IMn+GpSUE&5c_b4emGzcI4(ZIKVQP9lkFA+s+E^2Mq78eZq z#c9$|ekVe^w*RdR`sX{ea8L}Md$-O;JGxSj)wad=M z3TKUh&U5m7yZ-9j^(5xU#}0Ums^TU|us9ZnXV32TS&Z2cqP=V2NSXY6v}2|q z9pMEJ?*>ff4GEw)%j9>hF63*S8lIheo{{n+JFllIY{&7F3qqf+hiTRyewO?2r=E%d z#pDXPiko>D*O<01?x7@;`_*3%+gX3o_Y`v++lBc_=N1WC_@~Oqfq{(mk z;E#9riWi4i9uNGgHthBvg4H*xIGjmV-|1V#Y-C$$(>e+&4R6G&uCOBO=vH5oOL&T{ zETi4n-v)AxTe`&k)?wBtk=M|rKuH;qtsy5507o`-0nEXhPc$?Y%bE%|=(z_|93C^eeEyETgFy9Xc9ZDqrxI;5bV-=%TB5u(-}2Jp zNC>_q#iuAQGv%fm!{E?x5Ni++P&~2&$VH9_l}E`qdlchr4;}`INk?(`xdRcc*r~g| zi8rKrisvCUZsd~_xMbhunG{rqwdf>N>ogT%0L%r#dejK|`N;zfhYm}}X7>ssh1Rz& z+Zo%Wcj4+WW3jwGnSHkZF`R(|dM({pS|Gub75-4x@GjB1ZD4qU!Du6NQ^-olR4oaf>^95)qpID;@Mcb0T>dofI(8R@IQVH zxdySn9u73Pe8`Vt&JBH!Bv+G^lG?#E&PgPkA?eE zj@;Mve&b?azU5Am_){C>$m7N|eco~)M9uwQZF|y9DSdsU*dJU6?$^mS^m5%hCnBue zb0_g7o5S{;@4Y=9qH=0i0kP4O0ut1Fy5hhMQ`DuUFzD_Gq_QFdE1 zD9@-L%W3xH<(RuP7QApk2#In$b7H4p#A&&4@26uH%&WnL!Fn$?`o$bhPu+mzqe}+& z7;+PW!E5 zQMBC0ii)Yq;KP7LpdeA;oS@HPHZ-xmQO;IXshe(`{ZiY?4gkHhEJ+F{SxTZu`74!kOw zhq6LmTSMBsKTn+Ef^y;N;c*Pr_mx!yb#H!I=)!FnnT{}H_VZXAe!F)?b@1+uh-Qd+ zx#e`P=F$K!!P47#7jON?VEP}!Zq{Kkn*kb3JM#+pnlGd!7^JxF@E3F4tCSf9t8WJwmq808SNI%+sDDs7pW1;9Wd2c$*Pxn9r?cM0+E6~ z$&XL%PK!{UYz~BgPHA?yNRQ{W6e2FFQB@T4wfm~W_A85(Oa1GRYX$!pF7-5oFvhSU53{9ax>io4a2yrynA&$1u|3fGTra^qr{gH`0tU@gQZE0vzz`Sm@ zlVW%B$mW-GR$tPdx>6u&rA>4X+6J(33H;^%F>p8=+q6DSdGh$erynAD?+ZSgagZ51 zApkMyb&gUOU2~>>hsCItypvN{m!%YK->#HuZFE(3_M+(U=-!_l*_S-P|hWLA(gfrurC{i6wrW$i0J;-V3+H$-R2)dP9N9y_h8QC7LJc!9Z7# zX(0h8u($-z?po5Qt0v3qqdf6?+d{lcKj-YV&!O&?Fn=p8jgHr!f2Qo2d<3Zjcea7G zrU07TPeCBcMg(mi{j|2FdB4H~@v$jY9hIuMd=d%r+XekK;}-pJmI7(Y>CK z8-`Q$HS|8xX=|L66wR80Swv(;{v2@oz9t?V7HlTyD%H;C`|6+7);jYtnCoC5R{hP_ zxy{q2z9wjmxQDGC|Qr8RzIWwO5&S9 zy;}<m_d1=${QEmG8AbjQ0kdpYrj4KM?uwy?qM}n(A`uP#n%-(Nqf3`a z2gX}Vg4nwZjm>7l2~O{Z5PNx>9Og3F&Zh4pRd%5F;Z`Oe58VarnG(0e1kc}t6<_hw zKNh^&7<;mKqG;Y;BO1RKv;F?vBxo_2-WKxx_(pB)kA$~+YmEwjaocZR)z~cS{0hl> zjYvr#+<@j`b2G0tDBWdXdUF5!@yy!P>(hdqZMJc)ezkDdNF3!PRue8BuID zlr^Iz=_>zaR?b#N+i-lMB5&oJhQDNSQSGah?$Ub@wfK3cQ*fOQUpJTA-cYuOnvfY#eO$Ch3%)%QT>%44K|Yk zJ8b*J#3J(}F50}+Tm1a$g~){Pr3bn9louo>{BmSXVjqOTiAj)=ppLq+qE9*BPr|>K zzcBnYk|Jc`_x0lHy1BP5V(KD-i@$d~&;b3setYeK_-f>WuAoY3d*{y<_1Y2O2&@&F zf4*C%{&=SA%)J(7X2uIX8$BLcc<0%`c##C}&ofn4>+DobgD@k=jXmmgmNUD~_Xw30 z(1$Dk;x7CSNxqoYmC|$jrp(L)li8#5;aH9sgP_;G7+XI1ApPa?O|0hoOkk6G#k1zG zMu=SV|P1!em!;R=%=_PO5phBdc!D)!~cndBGqg>L$JBb+*aZ+%Cn~R+E@gb>(Nj}7U`!rv@IKeV{VUnS|dneNX zAlz*uZOB%L%~Xt4d7tu8b2R|7XhfB0_#{k1cX76gE*UvQ`V1j?Td3d*YXfB>|FuiEpV)RWqzJYmow#wDNoFKG z5Wg%ux$A!&>~rBC_#M}_kwX+3=pJ6TX`t|T$dE*_NDnb;z>3=P)mfGg`<290re`cS zRww}MtmY~t-%6HT?CI&ASl+aZ*z@x7x*NIHlxlkSuUf!eeUX!yIbeS5&16g5i$kdS z-%J7vP&K!@o-e5GJUV%(m4B|~?8{`t%pcukH<~_aq6bTl_2nCQK31>dE+tu*u=|j8 z=|!>=L&`yE*z})h%!aK@J;^|^Ekxb%+?&jslKa;Zgk%me!-hWHwbYE>T(RbC(dC}x zl1*pfHF8y2AAo1ZD(Lg_5gsM>!&i7O7zj9U4QvR3Q(3ZWWri!g9OdUPoZQJy zh3UI}r>8>fpfN#>-N|7{o{4(L)Ln92wu=RxKXut&7N3l_+1tKVK}B~Rk3>nyD+~X< zNrhHwmF;w7*@0u-hC^U+r|%HL1Sk{Y-q`kpk&V>Wvx%$AbAy?1lUuhtfMk=%lRGYd zy9gN8uQp22l^7%sJdPih$$u2^T(s@AJ|j-y_qgHnQsmYl7u)P{Ei9j!#c!k5Jy&52 zw+vB*;jX}kSFLXW{F@lZ_gwY&!&4$|8MOtrB}FM4H`dJ}ftrv}2DiF(@`Fw_eZ4nnYfnMA-TH&p@0~HyYDliZMElpO^67 zMX^{>lONTO?$+;JSuntFC9`f~ljkf0-75;uLR6KF7{2`A`s}Z(4}@x>I&;NGX&S}m zn(b~?(4FI>nEEDL)Q(!8mPmU1+txnuNV~u9TVDpvgszPvR0^ocy3`J*QtAtfh9o+D z+zO=BYw7T)`CN7n&HgEeO>It_xFO5aX+J+8qEY>kXf|+yriZf*`W{SXyqr2Th>ZPu z@-*i%@5>MU7sZlXs}k{SR^7*qku#ker`caNf+|#N;Tcw$zB}T#>neUoR%`~kz?X~` z|CJZ8XY^1?SG@3TZ{ah&KJy0nn0gJR7cy)zt*RbH^Vf2`+*G<&1vk$#Y*=fA0kF4JzfmuyfhZAN114PQK&C}^HcHIihj|Ecca`~C8;_Nr4oj2ds=65nH%YT(+?DlkzvmQ3$lP9nC4-Y`)4n zarC{tQ@f75QQI=Ps{o10Y6rL&FD#oqFT#J$Ig~9fnlH@j-u$5!%^^A=_gN_0wLRYM z>wv~y1kI;#o*MsjvY=_2W>`wqHE~|<%n*HPAl9Jv&@&@3Z+_X&!wPN$kl-)+6w{zh zqckp|=D=begvFP;nm20iJ+%EZW!{t+cDK3&U>t{c(Rs-Jkp$06&X$0K)7=ArJHao$ zxFzetcN6Mdc=u*-%nG&%yw&KtuV$uH;?ih&kb7^8CSMCr=eK$4$!%dt_3XLq+`#v! zW72k`$T>6gb4uE8O64zK%%%0L#&8V6glOp07v%T_NJ(=vVxMo%c2_qgUvO-^cbI6+ zd0{JI>Vg6)s$HtCZ34k^qTCZuVwm6EQMYxHZC4mbdbei%wDNDQ%#V>E2F%;PK$8f! z!tW(&^6R>My}R!`cWXBmBUx4H;&vRtX`Nj@g=qa6V0_o1$~6f?*s(HdBBy^Tp+0&& zDlILgF09@zmhfvc$&>T7g?#T_YY~uZ@!($8VK$Tz#s`ok_Am;|5gg89o!DA{?IhXOJ#qJ~k=oV2eObm6f+dV{9c0=qvSwxp+|g+U065Psn+l1LG>&2s>c@h; z`DNBt+galr7tTx?y1oB=*k7>-=@9~)_wJNgD#cCo#M=>Gqj(VtWRqC));lhNfda0B z^>$sHuXuRj@Q5(!cNe6fOHh$iFBUn5O`hlOT7u(CzT= z*Mbg*ao6635G44A_zw3DSX#mbKwh4LEh~Wzx6%YR3j*k(s@%zSr=En7$ilHY4cWE9 z2}y+F^s#0!RzC_YS4;Y&&anwgtMwFG8p4loQ$0KAw`MB8I3v`&%Hfc1effKXoQxup zZl8$MY>h;Q7bHqfK79Wnc`7}hAOT{a7A-%kpQdmWYv$*Zq7+n;@4^1;+u1MizQT}Zm;aG%dV+CGl)kq9gaG7^`OTGA*fCy zH#O}GZ0@wUE18$3PWJndL6>NyCKgzKaHGA=W|B69s{IMyknGmNVnmMpi&;vER)2Rrtw z4w>3r4d0KBMQ+8z6K_fzKh~&76_cg z5aKkG0rK`U*+hO3(uJ+eNTMkaPJL|1w)sx^0~ol&lQH5wXH&EE*gqdqAh9)G=>#l; zQ#3*iZ^T1Q58?kFkR=rlzzf8apst5x!NDMFx`>5+O`Klkq2e=IwuwArU~KH)kc`30gK!PtteGH(|O+eCH^1IQ#>MpjzTXTZ}14zS>NuU^|yK zgd`_+-{c@3*@+unZ#rpaP4;0DK|f}o4Vrx5z`k8hLOrgDI5Xgs8*Fm*a+plhsiAFR zXs@tXV_V>wmekb)<^LFh@@1NSzp>2$DcrDIl9hY*E%flNGEwYoD31=v;h>;Ud4#tQ zXZe`n4v;uH{v2ZrXP70|OidEz_4ll-{}_BHN-usNVvrf|(Aj&J+}WN@y(9t$mJckb z0yt8Sa=aoW@yED7UX#9f5d-j)onBki56r(}44iw^nUeJB0jki>Mgf)y$e7QQ6Od*x zdre!Kdr$VQyYv24hCY31=0v0pB5$?utX}R85R^zt6Y@?Oel|TeD-f0h$W#rDuy-cE zdxzl7Ub3|@FCHA5a9zJ_=-fHbas3`k>VP*$DB)kfa+w%JV6r?bn?ssi!#r_xM|T(b_>&sHVnbQJRU2zI@VdO3YM&gRnT} zjF$RJ5O7MatO^%%Q4Ubm>1gl(>coh~Sueb&P+wFW%uPF2(@ZPtqsb&k8;McMsfLG8 zmQ6PZV|!S>)C;_-$+G|f2Syc4v(a`4Y2t=73I>#-d;P7lb8t@jLoi9$TW+GM5K!Hy zQJ-x3)8{lVG2${-?$~6kYfkAGOl8_m^ivH#?TTrrdKo&jlmOz(Cf)7I6U|vPHIx1; z#g(-fU5$|ZyPv$9o>EGrz)rJeFP@ei9we)Oq{4W=Q%?5|N_=PTQ*w2?g7x~C=i}DZ zWxUfZKei6uS3EMdPB=Vgqx;tZ>I#}IrWo|?L0nNWW^0V_2_#=P1FfUf{`51>fod*` z9EI>mKlOfyyjUAs17J;0%7LHMnTf%N6;G6Aq^XgU!+dQ_XWeN|UzMT{EwWssep>}FDWzJx z%=bpx+0Fw&$X6&@;*2yGDuKENCM8;|oSq3Q3}5Nn)`f{m(SlF3T-n~W5ysta>OvA5 zuQJ#DRnMR}QJY~T_CI^w6k8V3QgK-*s#d`UYN#?EyD4etM8#1eaqZ!Rhql*7)g@Qf zHAOZczp$scC||vU5~;6_A9F|r)hP)P8TQ`6X6^qmbe5k+UkXH#-Xq77&e zBHqTHsGFu&*OZwM>yegN^TFu(J=qJGN(kNx*?HSro%=*fKY1msPv`FG+q_G5B+qT3 zP)1T05s`oL7hw$VI3{StG0p{oK`u)&(>wK#a7`&it#DeG_YU^eu&ka#|7z~x7wP0f zIUj`|ER<5Sfz&nof4j}Y)5rp+Y6VJbkmt6s-QQUnJ2k!}l6Wdd$obs?*<)BW(*F!g=`+n`m6Fs`~n4RUR%3hU=RST(e8 z@TX~c$2{LV@j8c3pM%L9W%jjfG`~+yUht^R_yUE^hj6XFj2dl0F3Jy@*qn>-vdG@h zghe#Qa0mpqao^Qpz({9zUz1xL@$xF$lasOMNec@EqV?WjuF(L&aiU)`2kjXtJ(ifm zuTP@kW|4ekPVNb*z1RI=W>5mhN0DOQ#YwX%Z1j!-sRWyCG`ml6oVfJf;U1h_j3xQ# z(=p$4wlr*>8?eF7i znwsdX4>gsRak%k*H7)H2AZ&{P&}Hz2yRb&Q+4g20y9{Y_HimX-g)W~@>8We9JI%y< zzEd@Sk@6dHeFACiZ#s|e4PA>RM}0ie-#qru@UnYDDBm)0`TEzczHWL>0v@FpT2jTp z;1zn#o6jsEDyP8pYcGLC-!J21)oN{Is#S-KsPPRW98S#Nr=<-Ujp_;j+;i1}A(8iZ zq6{o)O0^My&s?i%7pg;x=J<+Z-c<0mbbZI;NN(VfCtM z{U)hB>(Z$V*GmY=7!=pR9ndXl;0j84plWO?bXVVCss3yP!f<}V*|lEP(MZ+rAjz| z2w{l(3|aY#=6bzC(;_?SpA5*}0e>)2k5M5YZ0tzM#D|S)?wZU9hxcjkx$#fGHPfEh z*S|i^LAmg6B~qZZxZc?2g(e`S`LdYMro^V&2=%s6&owlJ1lXco*Wf;RF#yiv`h;$r z>Hbk=0Op0aYo8Jc5)qIu`Lo?B}RLV^qV$OAi~JyAD>r^ zs;mcSbInJm4aggLYKRvVp&*{ADh7aIsE!wEc`Ts%9kKjphJMysfln(*)Jwl%lzfbePxOa`&iar+?GW$}W7Dss6#_ zP(gjMl05HEq%;DznMm;L2tlIQX_}-0+shMoZ;)-n1;({KJ?xU?fs$}t)>FliQ7sbb zwS=4k49_RP#wZTg@w4;#ArGAT{!E2?o|wbuem~7Q#gxk3`x)+aM{HlgxbQ-|bLCTu zDIdefhRe;{K|l&iALaWD?F|v|h2??!=+u&#lk0I;TsF#RMx)PzmHi}j{_KjRn0j}l zh?*$#+@~!Yc>LOol7#0f1r&3J}lGxX?Zl~B7$Qq_#2j5?hZHGsu8xig`-_D zprCE|ZKuAHxjWo#Xd3woFrSTF0cyrucXZa4 zkc50B;Br0@+CQB%azJw0#I~rVjc)6_t5BBwl{vPhY=8JD@5Na*R6Xio@0I z3Kv?rb9u3G^zL%^R24hfmGF7~4w}RcIu2J4jiU=w8^32!%6;$!P!P3hrYB&{khIwL zeyVDRTDcYow?LDPX#=^ks&YEe0SmO3VjmNFcXhd!~vu^$e(=f3XidtK386{%7|*QH|l9!&R`)Dbjn7rbDS@->aEcD{cl1e0vq zayCLlq8{FOpry6yKLE>`Y*MUOHAS4l^$$8W177+}4;j?xjoIM9{C)Hh-=X}flnw6D zPqD;Z(%l>caN*~Ws8WwTLfrQK81EncS3hXPXgjdD(0hHHKZe;O$a*0U=b>{|MU+6L zdTnAXa?#?+OabGNVttiQ%))!$2Dtrq(hUgaI4BC9CV!yCPfO^VS=iI+OB((MYW;l4 zzT^~QFPPgYHsO3v=7!=cJN8tt^CWkeI$_NNr_?7(a9`?ozJ^z{at=QvvU zZ&7l8ZhelUvuBR4>lL{>8`XGV`3p5t2ONIoy=#vGw|mlUxFZMGtF?Fk{xxy{aFtP$ z-=qllE#n$g|L@$SCS;S~Mln3A>n>zZKX(PoWcQ5+AZ=yjV!wwzx#58H;5 zON9wS;&;upJ8^IR3Q=-a8|Tq7kbAr9TRPtQv_;o{R(F>lR4F^SLAP>;Nsgxd0XHYP z5M{3}^}!p*Z(^V~buH&_lWfSke3QQJI;J{p+~DWseKkCkH3M zCiC(o)UuK_sF5axMYi`cT1S!hr!vFZly0imuOZ)!%8Ne-8oD z*yxKn&$e=${K{!|#!Bqh)MPD?>$fPw2(zi0TVy{YCc#aHy|_gboG4Mk6=sO-=$DFL zEGW8gh?9qN4dClwYzA+elH*$6Pf(xh9e&Z7j57I(VLf>XeEDyPav)&$V2D?R&ZX0X zPx^YLp5hMUdgv|%paTyYPhnKQ2(<`HLOi-#p#%xPVl2%{cJ~^3Y{ok`x_qoB{e+?2p@1U zAk5>$&65XL$!CZPbr3NJ!mIKn_h9I)SGZ@$*uMYpeSQ->w=2I$GnypG(7&^6B+%fM z2<(9vBkJ8gW-Rz%5fko#P!nXYEB{4QWM^4609iaS<&~x3yzhg!-L%AtcNyIqlK?xy z--8)F(Mfb>HduxM&eP-?LDMsFZwv<}Kyj3aFIl4Z0Cp{%tCqtEW}+Xi0}+G0ipxQ9 z?AHVG3~cJre8Z*Y=DAwvfpFic&=*X!?XR9^KGUYzpR)Gu`duMaNY|eLp3~QjP-Q?q zgua>l^$&y!9!fPDDB+CYjaY=zs+tB2z>wQ&59WZM@WZo=ipE5GhkUu;X8VZ@93*YF ztx-k{N}(iJMQ2FL?t7(_22?iaq@B=;ixw|u;Qi8EXIbQ!2nQsQ>#qqSIDh=;RlN;H z0kH&T)UGJGZcT7&d`rAr?ar1b&h+6<(&L2xOh<*p4(UCPKN}H5VFwHlCYUhpKH0fS z>zk(0D`IA!r>`abv^UbRrekBZBy!j6yZ>F0OE@4js9(hp?>3H>*#U|U0~4=w1afrnejXYc!*w_;MF+_s@p&x% z1F=fB9U$W}D#rcdtR!Fs3O>AcuL`;6o$eWqz~&Cg!z`}qTcI)5mWW={OPiMD!6}N% zrw>EJOyq1#SZ`^++uXRBrhjM8fg#M7FbRw$5IwIlyn0?AFB_5+fMn--(U6-~8*SK$ z6BfEE#h=QS6?rZp79NvVC3Z%+iyiu_OJ^-IL+ee7Y7X^Ui@kjg*sVY5`ySZE{s>X* z=&%$Y@fpEM?app72ktC}#7VFjl=ZMI;2MRZxt9uGIK4{_ekL9he;9D|Q+aXwECIY; z((y1fIQ8(=ReT=>w>QIf=3ZX9KhEEzyGQ4hxu2lu6Q?YCnS20;xCxhsyTDjp5THQK z$VC(hfk`H!y_tw%Sa5QWM2#NJfS266%fnXhXHmbTm?(ufV5{DVB$f88{#7v z^`{>^vKfTZ$(L283jUo0I?n0cb(80>ye;5w4}Z&|M*HEhU4Tf~a~(())SBy2z;Wwg z_u08t;gU_SFx@l<%4j#3M8RX-I4Tb9&YR2Me;=eAM%jzB14xQXRfxrOnEH(l>@3~` z7awP1(AND>0nRM-`D-Q`VZ`uwV@TUK?B4`3?mjN=7<5l$xKFj@#{HXIy;p=pn#}6Y@H^>f>UV$=o{>06MYYJwX>yGF} z`ObW_jyx=Bv32vunbL_WdafN5(=Ps5@@34G73OlveCqQqZo@Kdn|4nqbI7|Z2z)jl zI=bKWCqmKnX^}UU)X9ba8Bil5{{3xY;)*tH2fg&(F+aAxcKGn63f`Y1<(iJ$EuZkc z-SoIpLHLYlj(LCP0~sH~7Z6ykXDJKP`a8rqo0e(v91XMry@iaz%Qd2;gQ>S3X%~E2 zq?eZ0GhE@{_?h(3FX{NoXh#e$%sF?eDcl~gL2bl2WPXt?*Pt{&O;e+iwBh+WTr#KqOZRSSCxADuQ!o8DqMv_?8Ca%|aaK$xH&DNJjncOP> zK%*dl{j{+_|1mdO?HN}4Km=d_aEIB=hTTOS?vLAvZdqmgT>(UL`5$cmKq}&De;dAn zeCHNhNx<&Jr0Rhk9eh}~9)jT$nHQ9S{f(&<;XqPv!Q}yYX+K9STJ>(-G6XRa40Duj z)_1-!G$AL+*)yi-6-@k($I&}tMQRkDXze`=PPi)-SB!OS5b4XS91o!liqqxyQF;A> z^D9zG@#kMk>wt^=x$SU~OLh-F6+-lS-64CJPG`@YvJMZxPp=uvIK*nI>Z3jJ z(_=6Bqv(q2q{uB=073l|JSo4~4y6loE(;@9BO}=0xxLwSKMPv~Tbk-JBSdFrZDobM zmU9Ob_mvm7iaRbvBanDy1^h@Gri6y2k`57^c(~*hg1O>qHT=0LN!49aQ}E_PR?9}5 z@xY6&*uC@(x5H95riuJOxs-TS9qQWSp9T?5Ks~G0CqOh_RJ%tg8?;^lq!rE9wt)FI zh5XHyG{|53n~pI}KdrT2a!(s-%YTmmMoD<&#{qz=ahMub>mxM0+Q!ich)M;UWIc=e z`xl4mNYI)7VD!U}?5v?o(osn}`zll+f~nP9zXWg*KQxJI-qWR_4UKZY>aEPEmAq0h zo;l^1yxk!AsmC_l5BQdVEq4@WiE?;fPAJ5{cy^?h40w#_Gst?1(NMW-U*B{I`&l_v z(j%gG&PItWeGW_>4%dl5Gz{x*sob~I%j_>9Wq#;8L2+cs0ppTjuFpnnS3N`<(HhJl zEkWw(f2=EQk5wfW)W%ExoG;$41RnoUgyM?p0ovm*rOPn2V*E`$6=t-1bH#5UGdj+mf0Hht%gzE@5JNB}v_yUa)E`G<<0p{+xP4Z{ zkGy65Ui5DMBGGA2X6yL#RRoW&YYO=1m{#TJR$K4VC{oG4>d8JJi>K96Df3 z5-@P7Bv`KFW4kuBT@U58v=DClJWpizI={h!r&YoJm+}#a1)N0d!;9Xn^G{4*T%y?16+Z!sPd;IZK1palSB(_yaLOcdaUHkvEZo=xj^ z%3Ekze$w~$%(tw@7`90TssoRT1jW@?qc@7p?I&Z9$H=OUqG)pAa%d z)i>MAYP=u&k>6bYz|a=)AMs9p`E(n{p?nSB_36LY+-Pp!VNWgN&->$0=+HV`;09(V zi9IP3L~fa8fqYh-quaqBfz)J7)!d~w%E{$GnWxJsY$tdBGGXhvh;G}~p7k0p)CFiK zL7QfY+Ah3(892I^cU{op6rFwS3!ivw>;iuJ#yZZ*PlX9lRT7|@;k7ib4@29lgN{il zRisBAYdx|J_dVVTKY6M%bNI|c$o1M%p$EJwbmHO1>C$tCkV_h(yB}^<168=p3rA*Y zd6pB|lw^TsjlCI6|6D=`UW+Y~V*D@``?$eP~FPa7hhi=FyQ4||0ZT6k? z;bwOo8JCujH*U*)8sf=X+B?v#C6t*orRHj|4U~U?@Jj%>HSml1kG4iF?h^Lv!D@U_ zKoBZ5s!t%VqS+&=vrCWb+kW0U|ZCAz9*1WJAC9oM2d z-t`9_+OIG0=y``Q=}iwDA7Dk~Mg!&Ry{-j0fDukxMoGF?s8;gv4HD0i(;ZQP@ZUdh zTO6rrsESIQ{)7$7wHF`_@N7H12f-D>Ww#=?Y%VQbQ_Cw;KX)Lsu=YTY+tqPolI2z4 z=g{>FE}eji1;;k5VH0|q0ePyjVrdO>RQduOdKAeW_@9^ebfBx)JOXhvR zD)DXT$OEd4MShfgZp7oR#zjbP)Tjo?o5-4^afIcAy9wdN5YUZ>#yD&ZC^!mk9C_hgWlP+zE#MVevIG%3p9REC`2e{+jC3>aF9fYKhdz|uGvo?v|2TK z3unCcmi_VJ8?&aMdfZ#ArfEKj*L`hCxji}%ZPlakc?2k|=>cT+UI2X20(qw@iTH6z zru62W-s}F#u_Xf%W+bNWaLWEH_gUM9vR(GBI{T#%_ZhL0K%S#7OpWV~_hbhb-BgIT z76aS@Jh{MxCvAm_!gB#|Mu^(qnQ&9&X|YF89Gd)c>__BdvToz+9_oOyjA-W*0Q@P= z3nzz6dqMbxuEm5?x<`TXING!O6w=?WZY_BV*Bm}44Oc^g^gl{^Y6GdyLzC{PaYJI^^0Cq{AlbO-Hbt;q6YiezpjkPKT$d z(1v*l^UkW$Oy6w;R$+h(UxyQzMB8|>tyy&DOG)(zX59JOnQ67?sF2g`_kBFdf5ORb zNdrT5C^s30hq5-vGf+T8A8D9l%^1WH%8rABObkeGS}9jM-Pihl{gwu(UtZ-i0Mz65 z4AC5GG*ZmcVZi)0%Y8aEAoRh^HXWpEbVgn z(4iXMS-`)%Snuda`cb>Ac)92QXeO8J+Zd}TETr)hHXislUp@%~PxX!6H*;glU1dx< zei4V>eXc#MRWTc=hLg}^se#ZZTg@@;F$L><+qiy7`g?MH>x zfw#T?f%uuP&E8{w#z^NX6)X4k)SD_yh0wGv6*F1As?|ZFAY_$~$rITxY_qsIkW=Ja zV{)>3us?l1uH;gPIxJ>z^$xBoR_)$4p9CSf24D=i6_3ztEcS?@6P*gE9Q$%_K4?m$ zh|DR;D9AF5UysZByo-m^5gpMb(O{N?*IhW)!^q8$Hab>J>x4@Hz`Hb zm?cfXT8Ztp>H_Sua^v(ZuV4`5romZ+SiEL)8m~m(bO)W}&b0pHUh%nBXhPRwj5m?R z1;eX=P?Kuu!=B}P*C7cJQU~F>fzhhIJ9y@oV_ezh%groFpppSD_9UW)WT!V)1@kbk zd`InGxqnPHLRNp<3wZX~6X?MgBi4yQR zgK75o>E0aGpK>Q#y^>62@!eSYay{F!c&AG$sWnx}{sNEa|FDfVVuRQtp2r_Vh~S)d zv(z7D{eXu)jSiYqCAT~2=%b(Rkw$s*ktQ!D@C|5>N3TgnY*i^!HOQK%b-bdOKtE9y0w zH_fX4XxRHL`?(&wGWVdnRYaW``^!nSM*O(6j(4tW~D<7`Mp>JRQ+RBP+5E9?+Pb5;I`5Bfv z;#g3c@D$bS6+^31vw^AahT0znBP~lDd9s#ugWx-it$HqMR&R?eW&PI~64dw>3pJ)- zFz=HCgS8<(+PRYkQ{YfCTnHF1QA2y4$?%To6ng|N6-UdrJ!&ueWaUQUCFIuwKKz29 z_Eqz?qTqIg4i_V~J#W^{@~S@}BcgO1ii+~9M!?oP9KqYthCLb;8@h8Ss3tTW_6jdy z$PL~h^l=?pd>s^0zP7jV4-|ZncZaK;O6aP1@y#!={q-4o-B)y#6L-kA>)Wp17#;AWxNJkTZ>E#LRK2wG+Gepm zP1VbFI#{o7h`uD%iO5MXuXJ5w<_BQl>Wl=aN!q#I0q2n-(Z8et!i;9M&||6k2g-u> zD~rF};<6oEGaTJq9C8-N*uB!Zto};baqa74zwy0v9L$8!9|cbA6T(n!edWvfgE%CK z_GK1je=69A{FRiPV4kACsTMD1Vj)lhOr6Xx6tWJE-29M27NvQ2gg(^r5!C+=Gi$mn zZqAtUT@_JpK1|v<@KyP)!i8r8@;n&&dodF!|BF(^>6g0m2G&nWK532F+fQ%oYu3j@ zmKKFhl}`CBGo@@Iv1WtZn9ZDrzbX`TVoAuUXXxEf{0H)yFXShjlA}kO<3Tp*mx10m zn3PPMa7aAodRjKZtC8xMfj2!Abee^8u<$(=X(9jJU0{&-iJ?N;8_Cf-kHdKnA<%6Z}%8&bK3FFdXhH0f2Bi1G#KSHTmQwOi7YOMg27 z^M1xG7^Q*(0}eggf1owr1=}DU6J4oH*(BfQXFd*Mk&oGcaX+EF#!^4f4rDjy2w`S*G5X;Mf+Z^W~a8)4*nnRBY22h-I-ujx3ep zsL71yNeq~cSm9eUUg>_`%gS9`ozY$L)<3snXc&YR6DxydVEeuT70QPZ`tg%q+AW- z9cf99$msLMyQPo5%G4L#aF_(vgB~(U-!xN}|5Tf10_3kI;E7BrXMX;D$iJB0;QthO zUGXJeFxSHTFI_+0h@Gut*4+13b&nEAtz;C4q^k_zE+?O^fB`3On2+UYbj>tV zN_0Q_`WoC2p>RjchmxYh`sy3-J92L0&gi9s=atYlRo|;3E0~B@JS1L>MERKi!$Uj{ zX|tm1&ZcN-+L_1-v6}ajz2Lf{B|HMg0{($;Vk7+5-PGim6j%-( zf*|jn0Ul8>)%hAN8fTHW&MVcQrwsUt&6V1^x_};c?(qazeky>!q=cMALoh>$A*7Hp z-dqGq)ZwsEG5}WsyB)BvSH*4O+6y`^m=OUB_`eGaM;q5B?kK%BlpcP^dYYP>cD7d= zF}c>$l=T(nS(xJc#7kCG>izfYW!{vtqze9_f>=8w}|SO zuig5T77kCgMn1YD?MrDh|5N8zCSw}E_VpNq^qs7SRN-R@+PzgETc2BfH&o;Gv6UI*+@+~qYc^h;2tWzO<3{$v^TX%w7@;z^khC#cy1iS;$|z> zf0mBVy^2?5z`7u$=t`1FO#18ZQZ0D>UU_*7&72}?mxt-{!o44=t5VqLTGCV;mur$I`{ZS zDZoSj@jBG#ABZD@l4u2lN)-;Rl6ACWC6mI`Q9Exn`eNi$HY9s`jd3hX4QtIQr6w5J<7*>N&haV{q7d;iCus9S7@&3(LN zdQOgy6xB{IfDQAy9rm;;1`eR~?de;)6)xfg2Iq;l-p$0lKt|p!eLQ?(V(dp z1VtgANqev=D!Yhb$F9jug-idxnApOXG zr2}gonU!3VsK-4RRhJ!W*}5?e1bhXVZ;59P0J>` z5Ch)LQvwV<8NbE=_SA=8CwR@AH>mM$7fa2bu2>(bgo|l)%!Jux;=Gx$;V72r zN*+BOahqrZrUzycO1Of0Q9FRn5x2^BRVw+Gc)ixP%g8(2ulX4=M$`A_OTPz(YVKES zS7oX$wRqxJTVCA8QFY2bLjKOYJ_8*I)Y1#8XFgj ziy{q<4kF?45sZX*)Iv3~)dFvA@qwhwD7)&(`2>FZKIARgi1>*)W zcQIxihtH^1_oX>ceDrz82eiGSxKla$Vg~92y|y|* zoxWy6!_O*=ZBpChw86r_z?L6CG{jL30U>oez`393+@59JgL@mnJ=Z8v>T12;U!Sz9KG3MewzSvVfaSr2U*1ujhy+syDq~1Mr^u;mg!b~lGTms^BEHo zYBZ3xzFTZ-5EpQ4q{?q}d}u}0U`-RGlVL^@dGk1Vj^BN2(KP4p$fyuWWZ>%tO9A0< z-`cpRzGRGVMb)F|c^d3lrosYIx?KF4Je1wd+RUYfJ-Eba3^wk71X4#^u~6bI%0cLj zfFsG%$#{oW`|f%~x!AY%Ag=g0?@iee<$HP`))@|OC@Bp`BoiXEy%UN-l0%r0E|$}6 zXnTVa>?drgoCCbRZf9<2?7pD)oq-dKP4N%{fA1~6HHgBLm_=Kdrl1$be)~JjE7pZ5 zEFbyn?XkvsnRJL-uXT5v9)W4s9?!QK(4h0uPA(lEZByu0jrVPAJuSI=;L#r;Q@A?%p^Dql?<_5tcF1%i~J4==z zecEXemHXo)Af?{t&JI5Ey>j@B#|}eWW7FF9kdMB&6CY|S>HK^u#A3t$@>G=`eis%< zfQZ-}a8vu-92>oKvsZg0RX1q_9EhU#=q_C^N@n2udi}dI*CHINO2KFQmb<&R)6E=P zYwwk=;89k zfBR`=-*oBC$-TrV=nch>M8eZMKBOnlSR*4L9t8 z-N7g!n4j)GNdOX!mP|(JGzMrca6b;`vok;~`+eZ9$Tu$`7XvcuqU{|n<-$}K!$NT5 zh@gTWBVZbWwuzcxU&$+`-E=Qr2~7VsO<#yG&*F~Q0e^5UFdBPOU>T<>0)u4tm@H{l zZnMGNyHY4d^wLJtzbyiUXyrZzNSRJL+95sSHo?peJ5t(Ucc05J9<8t8QjPp=Ez9k~ z#PWf+%8w&f%-c}bs&)1n5cQ0&$GOC|U2&s=2W@N!L^JZzv zBHrpAah6hjghd#(^~}AFx*Zb8R!9Y0Q7s}R)}6i$WW>Z8Ehb%fVKktTYfW^p*nk$^ zv@*7AiHh7O6fL&jOE-d)IEBB14>NY`sp?6?Ypf(;(kwR20=G4E1tKty4o&UpqG;$u z(YuG{Z5?#Y6W)9}Xj*PJubT*_)xPqpnm!818io{E3K1IwQraloe7=nb`trpE2Bm3| zpJm2&CNO12*cLg$uC)rB3z4V}E+q+2>)9|}9Qz1TvJjmhpU%wLieKD!oG)!>Y|#~X znl1AeDo<%-hU}E$1!`(F>Z>oRDzt3&yvZ66b=mBWdTkpz=z>7^o ztcwkXQ=)$6Kmvt6?sGoRp*hTmOC1o!!2N zxQOUFH+B2(h^HQ|`@C`LEQcwbwjk}?>7p%RTx{SnLn++Nh)pWKj||dc`Tkz{g|O*J zQjjS1x3TnB8A-&FtM`4PVIl;UY652DABb719*z>k2{%<1@_y`}+e&(1ZSmMg?XoMg zCqSrZBjUFQA7In5M2!*eqPfZ5mD{;#=oQb6eUaJ!{o(O?iWAe01DnSh)-e6O^}^@L zciw1x(Dgi*v_Lj<43Lns-1QY=in+THn@Vf^69Dx+g1){Qmi#HuD!nyGlvF zo430yr&r0Ya{5>S%dZY@G(JrB(P)C>EVpj!oV*=SL0P?Xdez$MAy;2JME31u>r-R= zP)Q4H(3_vo%)kMdO>X3%!|ktMLx!6frQu5Xl5CkNd9Po;G!lv;sCZNM!+z^MGO~fs zNIWN)pW3;Y(nt9@i~x$;omn{#B~|e2wcici zRl1Jw}~=J-0`qrZ0RSM03zALtv~rSgT8PqepV z{z&&@I2tB|2JQK$93Ng##+|INYc_{(@`@X!KZ~>2>&%r0mH6wndDyxeoZJiHvz1-C zGt`2iEH(M{x@(1bZ6E!8dCM0JDK_eL(Y!V(Ke5B{7?i5BE&jR9R@cRU>Kf%U%uHud zp15xQ*vc|-5GcwfVtGx-2mQX3!fm8ip~JGyWoHc=>^J-*4tGAD-f2laol-)-_I&m^i<5>M%CqTyPK* zd;*)E{2h#9cpt&I4P^qZU02W{dtn@O=(m|Qj(0Snjbcthj;*ORSm*w$=MMLlI|~16 zewR9bUUq5R`GxQsr&MnxJ02K%^)OCMTXc(j*HHX-c4x-Mtmo?X)jh&p$4YlLYg*B{ zKkO?oyZgk#Tg35NU)sUl+0na?L6?>( zM8=-9wShja4_bnmIJ;eSyrF7ZEh&McPjq-g^x#WYskm`RjeXueqL}Y!}`{B8}oT?fls5v z5C$KWMNVv?MlN79X3@1%m)p}{V+Z>*8Fq1WsnZOWYwYBF&KRAN-fN$V{Zn9| zzUg#CymA)K(O#i7W|rMI@GoiE{L%%$yXbeBV{`w`S`w;WRZ+#~Q^?qREHFMidE}RZ z;XCyM8s-HjSNd^VD*|-3dl~~$p9vb8Sc~MVrh3SR>(^CfFCuhnvr~%Z1;NHRc}O{) zC=wx$9VtPL50MayatGm#vu#RizH_2(VX&2QfhRfwTR(TD%{?2!%p|_xv=J*3Co9%- z`GHb2m7OuOw^m7~^#iB|$xa4xCq}IYk0-zfFmBfic=W>4X(45tgsL*%7l7JB8sBQ} zpNs@Kd4JHPo6 zy?yWinHKq3*7c&dq6hWDdxgs&($ULLIqNakDie^ota`ov1=4+$C0u!J$XcxwwU_L` z^J3MWu=qkd{-M9R4-KaRyX!Zop*uf?wZ=M_F3bvNpI2tLrVd1ziN>QQ6pV|Jc9zd( zP=!vxZmwj~=}HCn;jgTV75QYbKcmZck>0UVtC0HDRU9^dYLq)BlzNV{sP9&G3zm( zOEu)@?z_qBZpgT-YOCEVMiNHhlpPfZ2oM?k)@*!`SwVnO@QZG5HX4jP(ZHq&g@p%P6yspeMIZ7ApBvi+$#P1 z=!1{v4KO;QGM{3+(R74xmfq=n$`iLvQbLD;iQ)o*&T5@kbM z?5zad(yN!Pkl(hPoXcZD9NaHr-@5xEAsz^>MmP$d9L%TI-PTjEdO4tg7iTM}u{LrH z2`1MNCt-E3X|NQly)BySdYHJ*%Yvqi?@>X6V=mI_!f`f_XWJ%BAHBhqJpGbo)B0d} zw?L(IwP^$`mwo*_m<#k{ek21MZHBW<4(N3pyx2lWC9+@S7K+6Xbt`&Td!2ni^Vb`G z_M4+zdUI0r-%A&4OZGg%PU=jNgouU&7Z_yig*UklvOTfvzmDw)cJ``$Lr+KBuSZ!w zf3E8d+iRc>IqhCR#LclCajF^>{)zm)#s17kPDs?T3+GE)cyNB<660hsO#Vz?$lTI?iR>G$h-Bcvv_%_8-yj) z$k#9l$#^%4mObl<%Chh-@twx!Ox(AAjo%Jj>P|7f=8klUR=Wn_+4dtujgEGmC8%oU zUHq+kSJgIL@q>j*a4zTI@OFlU>1XZtFkB1Ysr!skT-VP?@DMx}$|M!RMHq3Qu>DQA zL~SL!6(vnB%o?_5ICsyU5PA}CC4>z#@N;vHhHmx<)dJpmLi+mn3JqdaG|*;oM)jrI zT_g~tJu~L%B@&{!ylVOs=E?QFH0xu1e6P*4n#kH7nE5R*$vdgvi{nc#TXEP?5ZY(A ze#RA>_W8(q>DOC+nWd$tB5rott4_Sz*B)u08r$j#UV9|Q^yD)K*0*LT-RKbfj4i3w+sBhlMehknNe(JoT-D&l z>7YfqF<@@|aQ*U4aZ%27$RuUPGxIy@jw7M-?{|klASHfljPiBY*{qpT;cAfIqg`F0 z*SeJ0%4@ekbD-VGu95~LV+At+HwwSpKQ50Lf%k^P6eP~2q4 z5$nQ(>miDR9pI0CUHKq|CgN9X&~bMWRrxwY9=N(p{7ZC{0(~f6o(>a1axj3;J+~p5 zrO~5CjYDVCw#jbgQ}TEn4o5tL4p_tiB1d_eEGAza=re~;M0~BBzc<8SRzNHQir;!I zeiR&`Kh;w;RK0GNrnM*DuZ@Yc%Lb>!O5_ukKSHVVL(>~9qH{F%I7m6pT2|ry_W6-z zY*Xs5a>z3rf=QFBf?sCRazZysnq~eN-InoK|26iFB3yBO(fJbuZaO8Fq<{CfIR{%} zXX*42f=O2^Hz4~aEsPgGUFI34y!KUDsUvP;`X?y8)FsIvv zMYqrKb&u|^&eCp6Uw+(FjgUV_M<}kz_hgKDWvs^jkf}LW7c9ZTM=nOHaP%`k@bw(0 zy?#)L$ zP|6xc7R7e3r`mQH{5F}~DmZE!J0-Q9{1-}}{oLjkwuw1q$u%GN_NaXjdr90i7qgs$ zeny6xfkhO-eh2o70!5dLLcY>cQT`cg9eTfdOQK|#}=(dzQ>bK1LLFQyRwzje@gmEAMXk5{~qHBJx;3q{_`K`UFqp38cR#lAJGqr zFqFm69EsNBr|b_7CMixxId+MrwK|wa1GUE+cPMN2UCE!M= zq9v`hpfknVWJd7uk1bLG&m3Cyl#0+t_K7Cxh%dNOt+K+x4-!DR>;B2;j0&GwK0sa` z#&B2wYRzm%<%93R)NE;qqsNEFH*UZGb`ceR@7Wf|R*Ek`5>uZFzw4$W#7W^&>BhjT z&TsOV?M@Yi|2H#rE#Bv(=VbEaJ0eK**uKl z^d4u)q?;!ikfd<~Q~pb-A$GMpbNHfzb~dx68?b?X^=<#Owkuxfz%A9gRijmq#i8b> z1Akk`0u&3>qdYURAA%22pBM(*=B*vr$GM1Aw)58jxDD*Gh~baJ?CAdg^`KNJc5>|+ zytPj_OlLNX1rTdQ0h@{N8X~AG@4~PGqBh})&+j~Xivq@U3rKH-(-cpkd~VTy(!hLs zA4*BvTy5WI2-KI|{owY=Vej~en=?I}p9zK5QRCY0wHY$1$tZN&p5J-qo7&el6~F_e zK)diK6vU^4-B+}XIIZl!2#2&>HQEJ0Xno$j2vb$B5zNb`Cm)`Fj}czTExQy7donY5 z;gDXx$Pdx{?BW@2e#!WIjrfwFeQ9koTuTV`26B=y4AI0u7xtvK`RO&=ug!A{|3Jnx ze&5%m6B$fKb}wD53C?IY!@A93?CKMEFck3eH=Q?xESpfABYtq@$%G;a?Pz zNeWhwXe;H85jqD%*pB$0e;{Wh1A984oW;Ha1l%?To^h0c1;T+)gS+PsjGC=I*%NIU zTXE8spV_genCg+Z1VQ-mR=D^PsTgaAAzmOKA}|Cdq58N3DH$-yK8$v2h}ka9|Ka-j z=Q8C7zMRNf;4kbJh*r=y;l$SihkUjdeajl#LK>c~({&mx2M9!%Z`u20ZYrdGBQg`n zT}l$+)F(?13y`~8Bg%no6@Th0x%W(8{MX~9%&e`-mvhA(W{(|B=n=tI0TEtmsyOr- z#9^Rnh^@IQantxSO^8@F)7riFmd7<%d!v15GMwhr@u)E$BW|pYQcpvnuf&1K=n}M1 zT%Qc~1{`(wAIKFPkLPko?vX=^{2_uF0_jZ8jE)ah?`A+}nDk-)Dbb~gx8H65n8NU5 zl5p4a5>hu>(#(+F=#+^u!NK+&Kks(UFQ;~%Qjw;ig5$UUUOJ~s%w;$fn>^i#GJh{d zE(mu~QzKFn!f|V+K<1#>$WD(GpzOR{Ip;L)JTp`(L#4#SASQ1Gul9ybH@nB*}YocBlAA3#rdP*36? zU#0Eq$$Id&!xFypptlC`p^RCi^CsIjb;!?;O7hPeb;VmVpZig|?+X3{eV~Reni2O- zTZW)mBZlAph!W~P?y!)iMX2i<7r_!B<9h};kU_K&!4ESbnYxWHzvg|<^Q_dGY*rL_ z?>8D5ZM9g^w77p(3b7m}iOd5uE$EWhF=CZ@b_-|NU2W%KRQ|#>m$5b^bJ_3%sP^mR zGe1{+b-wB5Zp2f?@5jG3EX{$Z5-^b60Uyg>T;W{s99PMGJW~B@`>;4Tx0=W#Zf)Sq zUKYDr!Z1wbX+J`vZ==$gY1(Jja=j;2S0>PGIApaBTZp&77AL+7tRn#pRhC7aDIvOQ zyIsJv*>;zCn&Siac-o&|EUozRJ$3K%tbNtV@!o5vuev+FQh23$VSn$~s@18u(}^=% zb@Um@UonIkTtxz4vl5ChV=N_tAr9KyScke;)_i~ih0_{_62tr_Zbk9|B1QXz1A26#2RKgi;VhE|Y?eqh#qMcS2b$15o=u| zb+F%i50OTLlhjvHlSVnIx&QGGT~pA(Ag>X-)iJ7}FR9?`*)<)g;==bqqqqXB^nSOs zs^v@xPaivhdk9!YLq^E%L3`He9@e^u|FLx5@oc^C|EF4Nrl>vAmR4(Tst8r9ilVhg zYt*Jz1tCi9RTM2HZS5MN_KZEMYVVoE9+j9Ok@xp}evjY(=kYih=iK*oU)SsPd`*IX zW$*Am9EGX8=Fj>u82Sy0cpAO@PekXFHqXGtr{UXF;_uQ2kk^1x@Ak5>s{C_ zK0j8M^0=B3mSHe!D_$%E=r2AC#*fy!XDBd@QrtY$=?@cGFE-j+es5r^d(&f`D3m~Y z5OgFo*Q!yp|cEW3-Q}rr-BUi3s+5647T*?ibWwkjv2G6@K ziXtOd`3cCe0aXF=-*JN9vl)Ny_bZ^<*p2c1^~Aw~`AjF5=ZWc)tI6)i&9f=?-@bbL zb?LUHo~sbG!bX;X*uS`TR*N~(lTlT15(L;56TD-TgnDvmo~9erj@7x3w^SfKZI;rb zu7SP~htnLqmZ9()JL!iF@ zVl(CG#hKPj#mUOtfng&`r((YqIH6rr87*pv78SK*OOUG({>Do|NfAQVgd;v1E0_$E z&}ClYMR6$`is~o+(`xmtAjFTb#=dCcbqFEz1o5D^`Woam-QhMPALQWg$vi*{NC+d5 zK;ps++i}{Elt;~a%$jeu(<0OmFB)VD7+!y=bfkLy)=JnXb=OW=OY2yfZ9w(g%vNPf zh^sT!J7Ie0XAeyr>J4%B<}2Q1xVxo~-PaBeEeh6kigHLxvWTUz-&1|_K3y$?2aBhu zxuG*SzbbcwGpb$VAAc9l;h1gnd5PhTT^(wjX&(FkC|V>Sf7?K(VRs-&0MlqqnPd8E zsKT7BI3(k3lsvSLEHieJQ|N7&`HJQcX1bk>GikTkf(=ID;Mnar$tq z(xc90IrPb6gDfw&-;uLaMOc-~^!OnAP^hM*JhUgzX91Ck5(Y3DEkiz~-KU@9opl-n zh9CV$v7SA%E0<9aIQF3C{l=eEJoBtlAacl0pFd_w+tFiZ)SWKL+v6hOZ}#u2GlC%5 zVEn#$>K3c*e8G+3cQ>8SKBC!l|H;^}Y$J=Ug$G4Vk66>){r{toz%aVm?Q)CN8fgeD z?wI{nQwmE{E)SFIrCoHgqb9(OYtqQHb?y}g($uD>7zHa2|1B9CgEFR4)^k&i`uSHb z9ey``6`T3jBrAAC9#)DW{I}*JJUaPK zb(`%N5z~c5#@K)BhIj6x>gz<_U$+_65Sr^eJ1;BwHQs9Ce>F`&gV`?Qj@ePih}N~A z?J2E(%SYA?m_}VMBTool}oYnHXBSN2d=f{fS zG%rA!|Lx7A7g#EQBY8Uccr$d|46Sx<+&5Zuvka>`)F}QVA`}F4E_iM$nS+rQ|1HR)@-m}LYbGf~do~+oqzzgMfZ@M%S#mW}IqDhO3 z4vE=3>bVkkT{@d(N_jw}7U#riuXHqVNjxMcsM7Y_i?d2Fea-nR=xDzAMXe{-p@5y^ zxGuNgjoP5K%z<4?4*4JR(yt;`hW$Gq)g%kcTn+XxxEt~2-74?bcpLWFWoxNS+IW67 zQGYAdD{ENO$;-r^#y$T?$`k+7vx2+Pqaw~bJvL!ePJnT&{D^3&b1=tx8kmZ zv;G+%2YkP?WZAtwbW2jQQ+)tla$uRoZA^R9dQmD%k@qmD)k|IEG^J;4;`|tG6cYN-KF$mQ9gnxK{XOm)8H&2O(L4C6$ zh#bOulL)>)rMr9oeq(C9@{}BQ>^vU*5mINUWU<-g;F^HMv0Z2Zpqe|soxj922&29n z_jmI9x9L3{RH`g3u)St4HT|eO?9~i#X4rqtvp@>L_lRXIs2uw;{V_;LnPIySA>Jif z0sG6oA*MGb#=c3Zpd#J8)|M~Wluj; zjQ6bFW+TTrAvbJeX>GC#^_5-Z2|Y{3e(HRC;AM`t?1IDx)$5-zE4oU8hA@lvKZn0P z$zyaM4hFXEv|Pun7eX71&0EWI(C$HEqX`2}b&dLa3dGeHLvM`i%;Jh_tG=iaHS{mP zu>Opa@FrKWA9K;fSG@gwy8W|ikuH_X3s&#Flo5F(RK*l2WWp{gY~ziu)5pdEA?P1HqAdZIRmTR+{A z4s}l_dAccx7W%qYhp37D}6&WR?1fmEIZ4K9p;@`Jy|cX92;%vO!^V zZh4`)QF>kDn!@wt?~e`LvNuhq141CtWd7!vT7A}j>NSEb&ebh_QtBadjD{z z&hx=3H4~frRfM1tsIvvWuqgj00p1%to#E$NLg47WNNku6cBl~<3}tX>dBPEW-y)-N zbw&dnD$x^|$Ju~4B4jYO28-8wkgQf0h$2BJHp05M8l!ELx?ZSSj}0Bkw6Np@SPaY0 zW6CPnQj&z9FJON?TyVEs|JoZM@^P6r&3W8oO;gx0X<$AfV@ZuW_}ND{TbA}Qm?jp? zOmN?C2GA@C{wnMu*RgG*6~%MjJe=TL=cx-39K17nNT_q~OfV|CPV7-t}~6xF4`Pdg)l%)97+(li5rj_VFn>qbsLUC63^&*sA3 z8eC!PvV;zqHsabg@}0bcLXd=%-gl;XoYfQmUbjt4?4!r#?_;A6O=4fWmkb4Y#vcQk z#C8F~P`4^0p&NZbBa|SUMD=vq^T5mhTwq-MxG%=CMS^k9Hv+>JeuaY&!?xkRIzmM_ z=pkQE(ZE-JSsjTb3*s)<$!!6F#d;+q6;xw`dy^%kMoW8cv###BhPVR13)NWbZFCtQ zs7qC1#<3l@hF}rB%Dov!GAh&I?`GPkteR;3B9P0XaEtwSrbu4KFtn^Ek8j-5-}{D5 z5{EXSEtIb>2Aje*?FpY;Fiw4M^lADxRJR@Vl1mc)&flS4 z)q7Rb0g5L)o^-lSX%y*&Sh0z2*Oc1+t5$1+y%g?Hnbr1EJoRtj#N2InlO(_qK_20+ z!+ILpWLl~CcK?~+(1qT9uM@E|H9m&cUX*M)cQ=^nK-6X>^B?roRJ5&-ZZ+rSpobY@ zGNA=KI6~UQKHaa�QBzgOqiSDSxbQ1eNoA$C1y>2nlqH%Ok+Cau>z1;y!=1448^Q zJ%#iJzQ;41-=jvg=iUF@CmC6&``vQDQ<+jIQqGXoMfC>0beh8s4@!`DjSoFIP5Kn) z9wrYGe`u`u=bqrKWOoIHL=?;d{YXrvpG-GHrdxoX{ys8I?~xA!j~yfGtYe={|^4SQhy;CdwkgWnPegPGMcPaXk>4(*Xyd8(m)t>cQLi zH3P!Lrwb+lE|?S{1u%Ea8z8Wc+LVTR?QSSv^S(9hzodnE;8`m&cx*8;>?A8D-7n}1 zEB}U94L;HysI}otzT9cYo|xe`!^M}IepbF$SHpGJzkg8aYq1g z-z*8pDa1e$$$Zd9Sc7k#%8;K50Eg{cyMkwlzDjc8)zfMVw=pYL!I5j7K@Jw$x39Tx z@$=L+q<6L7A*f>xZtSew{MY)BzpWB#*fTLwx>c|A0n!pZ^cSA}z$VYt2oYiZ60i^) zb#X7Zc>^s}ZkWR4-U)CRylLSUXeQOx|Newe_~N(UjiATrp3)2dJ_Qj5SJe2JDzJ7j zr)0%x*iG_->AGQ7%xRA6H|Y4t6OH`dZ@Wf%-n`8fg*l+5r;i5(_hzXz1=uzNgCB1< z%>T{t!!Om@(G!>*`8i^G`1y!(^@RdMKC*9VY@y6rhp1a=!rqCt4CCY*gkKXDwfezl z9V;wIajPCMt3>SqK}XJp?%%`WJWq+|sWcZ#-!p}rtwTqzug>tTB57e)CzXw}6_O-c zUt)-Dt_~^cK#+F81QR0cM+kJkbyo}hm{mY`@%y$Ke=cBZ$j$&5nm2Z;UFH?KU*Ze2 zdzJo`u9iKrF_>3*ooJ+8qW?xS9RX#bX~6ZLLXbe*k|et_je^IV2>l8<-BNaOf#f) zX^sYB6Q2AWNW0r(^5*d`!7+xnO}!Mb&*j$P-HFF#lx#Y;B79Zrs5M^Q?+f}XWqe0c zxCf80+*G2`6}X}XPLibPU@x5uUrogK7n(TCf|fQfw&9E5 zKQEwI)kH{YX=Tj8+S#+PA4&OMkEm&Or@scOJqz1h6*&?i)5R3il4+s#2hOC(ush}k zACmJN{hq*&opbykVHfJM50-CcT#dUIS6!g zVHUXhKpDldE$zSL%W-lgLA=A2WbqLH@*I4$_aPWw(SL{(=X(*{0-BsDBAEuL3bk$u z&VTDieHHmrr6J_d6np9Rx;oe3LwLBEP@B`rP%VSJsx3CTZo(BPSk}$$SZKG@`yj%d zlgA6xzGFKql8bMtb$BoA%h!BdXV(fCdP+v@EHg!3^|0>l?pvl5tA&GQKL)b|PmWpk zNyP{)q>h~T(r6+agmtd?Ot3xgQa?Rii(k%Wv-ULo5UZJ_qmtSdA3WkY8ymV zq%Pad3Z$stK4zPQJ9KGbA2FPAmMmz;)ODx8!Wn_<*5?6dQJzqWt)|S7$6Aln_E$3l ze`v^JH7QAU3&)zGf?vd|S)4wMflj{aqom4PNqJf{{>_UOfxOpzF3ZF6u+iQp@+k3A zINgQ)QOp4XdDi@#Jv8xZ(gsqEPHC ziX;bOSD1jbD1d*5*X#wMUn-}q<}J9)=K-8G*vxBS>a$e3W)}`p1D2)=ZIZyd$O_!+ zMX%ip;2z14KWbq(nnPI*EzYHLGiTu9(~pXGKc79iAb*TfE0^0GqNnh3;3ZwvMyb9~S!ouy-n#N?U0rcDR5y(^ECPqTt*Y*^* zO+R4YKBpQg1+9*t6>#ejloDCv%^oAtA1)0Y1hW>VKujBe-8i}KL zuBsKZk_93idK1^iKYd^*e`fB_1K6^k9?P}YdF)5eVk>X>T$q53YHaB&OSjLo;2D$y ze;tNj*Mb35B8FZhP=^}2V1a$L4p4c7gSVx~;n{JjA$?K5-5R0--R*)&6o=E(CsU!378LI1#S`o2ed`qeXp*Ncd4Z-fKVSAxk7M;iT<+1y z!D*Se3)T4^{-(Ys1|Iv`w{qpC+%Yy0wC`Riyr1{l!iWs(v)bT^;ROaaoK_%$1%zeq zCafN~>au$@$#nP5PY0>xr;3N2iLZ{fZD`aN2>|*zFN&esRlM20`RPD?3@R2IhCfqa8b;_ndW`@Q$l zmni>{`S7T?)&M-HbD1gOWt$e>J3*8r_+CQDxa;5U-WQ5$

N=>y!y+*f|mtvqu)k zPiK_vpx9d<;j*-+P!0PeJD|_WO0+y2*@thvS(dniL2-~c%5~A+vCGu>9?I5{s|2Ls z%$Ql3tOEPdCV$f#Qc~D^(lg-4j3;DaSlv&vqc*Zcl^S}NBrvr}elE7|^uzZ;LO!#P zMTYHL>`(ZvMswY4x;;m^vx0jLnN44X?+xLI=(FT7HcLWQPoOG5EhvVG622F2+ls+i z<@R%Xgm+H~b2M|_Z*rt4nQfxTukUeqdGF`ou&ZYg?UdvpAhLzVHLzI>*)wuunGn)@ zW&+K6KE3d)wV_6aQ65_P#`jm*!e9%fe0pt3pK!`P2QhTlj!PCozkQ)NN>YABC@msA z&p7rJzrHzjVk2dQX=;0w|M$Erjnjc5Stk1sJWo9B$Ak8zevlM#m2H0cR<5d)lmAY3 z^*OYv^>pr_nj>@sKSxnG$5wZ)8!F?@9cGzkPAv#2LNO4h6vF*`g_X;2S7?gaI1HRm z&^G++9jc}0X>Y-D`zwwOaVt46#O!zzmw=(^Q4#38(13Tf{6`VrKolZBUbBbhtI9Edc%O#vKOTcT4z6ZFTk7WaQMpQmQziB8`(pNdS;L)<~4Hf8nClA5t12`j= zkzUKE&}HoDzoUQ89oF8H3`G>N$+RjWyGVBTWtLjN#%9B4r%S!iEn~h(w4F%GWLOzT zeZ7RioF~Kh6%u6+sG)hg=oONvp8kD8-;9Bft{t-tf^c$o;ZF0QENb4~hVfe#+AP88 z{bbCfV^tjHt=4s6ueZL67pC!g8S=j&7Jxg{Pbd9U0eGNZ6R5QDUSYQgc3A%0dqo{< zuJ+S2R{6IEz3nnmDZiSgdLs(iZv*UF!%~Dk&gao3w92>J`cq5J|6o&7-67T-% znA?T=OnZz-YUd?{;L0$|#rbZ*99>C%y@)v=|G{wnb^MA^v#Xcq>m>VRt=CNz|9o2b zMD|knmPwKmtsrIezqa93D82#!^XuYfVz3II@Gn0NgB@$Z5`0QWcAqYayFl}9Q>xbqpIz9GT*3T~lmEzEJ#sIs zS_WjdST=$RyGY+NH9NLv(w_kbBnK=x7dTvSx~U3{)oP8C_|WIA+Q?o{%(dpGx`Fz_=|h;v(jUH#Ie?Si!^FR>!@}2sU zIpfN_9u{~|AhDh|Q+|%_U3HbyRZO7=ghz<)%w^-(k)CLM>le7rkME>Dbgl`v`r4Pqcyq&#hStOUAiJyzxQ>#r>kTW)M9;B!{)Zc4D54Zn zM!NTD)YIo5tlAE|Q(u$_|MSkCCZjYCYhDtXR^hzxPN|cTDAk)Y*hyt0T>fboo;?F; z`M5TCxF&=G!wVk~=H!QGTZRY5>15|s~aCOzH1ESk=f_|+a4&-y+(l?gtFEKXg5>Zb33A3gIiccQvPG%qPs{tUshNU z!KX+IH9!9^p-4LMhFryBiiUN5*fio=e-1ZcMcb$#{U={@DNl2<`-Vz}*?}UYDf_X} zyP8Mzmk(-Fm|eL)`fguVc>UBRcGzf9Rszt9d)HF-8*rUrSa32w1)eMHL(sfaZv6o% zgpIm|_=F^Ycs^E?(mT&KThktC+*q$~yC8Gt&#w%d%0IMp+JAnuLdbNQc%Z4n5Al$Q z4pYYE_7*j{W55XzkiWi&?k|)@k!JlT(Z7!?I|SIz1z8c2{=Ei9w4y|ih~?sc6p5C6 zHg5yWiZ@^)MC)Bu1>AHKevTwnXc)A*!W=e0zGfJ&P_6W#I%0OQvsmwzz(-!xC2`-b z(C!yaoG36vo9kb#SZtP0fdACTU34P7ylYPo`=ILNLusbB+Q#ndBPrRB-10atn~sg6 zWq^!G%GITpSTb7Q&%6Wj%mIfif;hPwUTxST;^L5`pzp3jG!f;mB?P@AGXl9bG-Q%9bOPZ7bS_#1z++%nTc307gCyxL;FFrtW{Cw%B@vV0DFz6APPJXf|WO`UX~QG>7Q0m82U$kj%|9IiGGflKWMW9+|zrkj#1 zbn)-XrOxDt6?6LuSxDRBu6SVn3uV`RU4Q+Lw6?&O$P$Um^H%nZk3Ag|O5IlOo5rT5 zhdJ*RX+y7!V?>k~+M*)NX;2NWZmac(z-nZnnNL`$a9KPP{#GLPU$g3Cz+T#U~&K;L7jhRNz*OQ5h{d(jZINP zfon6XJ9iGCV{(ctktrTRScAKdkt4{&;L0z!?$ahh049Z>P0)NVBJU4uIN+d> zwh#bv1_1yAr_bwf>}}r^diNQ28ZH=n>uM!sG=+x*8B!@n1ZAT4&s26LN|oLwo+E*& zT!hTlkOY`u)wj%%-eb!*iD|*XuI#lVIqz|>|KeQtY~SOdQYqU!zHCG}U0&hxNbfaE zk}E%O_Q$!3I!NE{X4tF?I@ohApC=@o>a^xfcY1mjS5Mz-r~)5OD`c9PlGJJNNYTp_ zhzn{i1kKT1Fxq~XP=h{;tRu(~x4mU^w(c~wr@+3&y!*)eZ{yc2s7;kSY~nu(N>$0F zh8WmgOo_l$YpST}MXlW&%4@07Gww6`v!`-M`~sl~pMcihJ1gAI-b`tI+8pAp6u)h0 zkmc;+EhlFChT_wED#jjaq?MR=@-&8k=Pi04tUdMn z8|}?g z0gN0^#!f=DUrsrU%ZBp8U30CBIufybQVa1U|I22Gt6f9`2f)$<Fkc)#x{yZ-)9CG8LCtx+-`& z@t0LOIed*w2b(0G^pA!IdG8$%t)UL5NqAIG8@NM$#uuvBk)>NS2Q3PsQ;6NPun|g= zJ78D-RbGH(jBuZAmxKA?6#l17wbAQue>6EhJ-x)`zpvuhmtVP<=viNH&D-J_DuOYb zqv;^C5j=@Tq+mkm>M-|^8cr*fG2>s9g9BYB-Q{N$%0(HHC%j2w?S72N*AC4%j9*nKTZH<6KrrdLw4Ac zYJw&<2N45iB=hbb{1`0XlKi=ocekznC9A9ni_BGDnId%3A7r9^doDpP@UoPsOyD+s z^tTwzBT4zFe(yaiutXqlTt>PBNRw{;S^xb=z+c}x&HC3fqsx`U6DJSE9@Rj zLn&pSwE}h<$MK<(LqEE|TdA$0=zE!s)?aaU*UgBR^E8=i%n=IwhF%EtEffHQ$i7L7RG^^&)c z%9oY5r(k;D36RylxuIoqZeUh9r}$89%{HZg;iLj8*mx#I?oUp~D>8X?IXJWK8!!mr z2!o8yW1aF?$F*8sZ%@~Z(8~4CwD7t9+;H&YVY1R5e+1A@tRL2U$6LO3bFj?=z1PR`N*s3n{ zPN;%WE4SxTa)z_$D@X0jAoKg(p1hu9ZeqI8l_wnatIB4v4L-m4cH^l3F|t`D>YeBCVDTpPx=#I)r|>dN+@wUN;oOj&;gX@{+wbnOc8oEtl%FF_Kh|iyYe8`j35#pWM3Svkf zdhM`z#8U`DY=t37)B%lzP}TI;g$eriu)57b*`t?;5#D`KGp<#jc~AO&S>bRRox3)MH z1*Y4DF6;N%SFjSXl`r3VAFHtFuR8cx(YxT_GPc8Q3wbd1EY%AFhogA=O#cJk!EX7}KcD-3G_cS(1P`p(G^ zr9Ys{Pi9h>m3d=NnLg8HFmCxX`BrOF_B>S7^Y?<>&%Q$%hNtx!eqa6jgEK43T|!ly zelQO{ws7!w&}j+;%2vn!}xIlBIJ}kcUV~f`TVr!^-`8 zs8i9CJLC1+j~~|u`SbFaH)c$O|X10M%PbQfOmewwX8!~jo~O?t?gW2N(cja z%%EJVKFpMlBA3SF2m6gd!RHfC>#MU)KN3O|i@~%YIjzn;r;-@@!_ioYnPJ3SgYu(6|_?^{hxyIvRXKhuw zv05<+9h_Z8VJ;AD(Q}+qzn+nVy3pksvBZ-2N_WXT+1~8^AbzUIwc0utC_gx>D@EG8Iz-v()|nYEWXo8a|j3!bZ2Wl^N^`F z^-vQ2D3k3}xRjTQ7Srx+ZjY$|K+*K#Q zE`*yo{f{D?M8z=wOi4AyzN(fR9JkhduGwRtg_bm)3!NRBs<5+Zz#*dQR<2cke2t@y zEVEi!8u_uEBKI#&R_dH(N6+W1^^)+MXI;3fM36hMXMvb2*XsGx<=rw%!^8>g-n}W$ zqPiLKUnBcyT0Z!gZO|((j+E>Y_Xd7?LTVv&qC?8HT^vV~m>>TiMPCE0XJt{76GkUa zFH}Q+it~npOQNozRhV6NxKa*5F7%!uC)Ch{FmU9W&HjbnWt3pm$)YdXuph*kd^AY) z`&EK$e6N|k_pr&RGRV0cU@yJQ>inQ&vsB+yYz;*`$B)D@7O37+clPb*_MJ6ntg&gK zD60;{6cF6VRFkSgTdFE!Fgt98K%cD;?r&*jaYWJ7kICa<=Ba-_+RO*}U+E#L1@1c? z&IFjGajD)Sgn2V-7B4~-x@Hu7x5ETmn_Dg99(rLk({?6wow^MU)`aWVXBF&o5w9dY zWhG)&!428de=j7WF8H%t{H4Ax5HeM)tlA^!wX^^IyD#9te*U?I>!q)Iu-N}3&Y)J6 za>6~Ga#l@zMRYb9G-IOczQUuWtRCp;!(Z}-{^lQrC+k?#ztLSQ=L0C^z49#XpL8~cL zRu)^!Tvku28mlM8y#MWc$ceQ0t9r91@ee#+%@}464XmB5ImUYGW5AL;wgIo^An-Y42K8Pg?HAIpGR#CCbOjG_Y<6>HTW`;8` zlL}XW%3Q3Im3@0XHb_spJBI3}#VM7$I>Ctts)x}|2;(56ch1A3NUrwwSzTebs=p{} z7K^n_<6kqCdYwzAi;OUc_4Ce16}hi~NSe5==VW?Z>$??tWs6fDcXu$W8@IpZUe>fP z+~X-b^|__p18x_dwe+T+N%`|6=*;oRb=Z{|*%T^5@B+H6y$}PsKD)i|S5z^T-r`2< zEbHAk`1Wu8!rBR@0B4$;Pcp+HW527i;u=1Xg-A-%Vou|pwJqAw!?HwwsU1mZd>{LK z8TaFJX)1w(T^*){PIm4U;FFgSBy2}(4Vj?h8yzdK2a^^4OAzBa+>06@Y6WZB9v9fj zTMEuBDTorv9-L`~1N}ZmXk8^t8~3=s+g5;3TF@5LlN{N6zXP#eCk^IF z$l9tCdj|%F-C@4uo@TsOYA8NN9iJ5wAi+pdtma1bAR@x9>ZhDx~WT7OKcg_lm!A0L{AmpxQEfI z+^33bCBV@y45?vS1ePrFt%+8}hO96JfTXz5<8FBcK7>dQR<(EyKvXG26&Q+tTegl^ z;frJIcv9$GrL76mo0z=ZisfB-c@^p`ry%E3DZUPXyoQ$`!G<9h>60_R8+5%WWn%(8H5n=BrsG`iWl<$EjGd`HpoPY0%^Zle%KWh1KI+I$>ADQj zVxND~%wKCR_7Cy4QJC%{yWm5k_zO@sS$IrYeU%8T&?`LaII)=&e>ljUI~wt07#(}! z4Ln;HyPLHZ;(~WH^X{-=rIH`dBqy;PblD2yqL4k_5x~;UMKW{xW@+t)V%;wfVASiH zPfCn*q<2ZPrw@2ZNzWT4(o3Oo0tXQwr`Gtu7?MIE6wzTTfNSW<0o_=l&ke>}r|F3- z6x6)17EV&s$H87YxRu z`*TI_GIUoudI#?xmqDmVkWrM2o*g~35xO660O}0*0aL_pL{S&WhFWeMPAhsQ|Kjl& z_Ey=W%Zs)(Afd znXbmR&GY@jcw9l__}lgSKjJA0h0HD#PRdoZ%PzGKEf>?vE_p7d`SYj9`R8I3K~tL~ z7?6Ym$ev%efJ?}AZ;r^SK-~}s7}tL;rA)#teU>Oab?)cCrEx+2H6%Q!i-XU_Uv>_G zcwGz(jUgCEN=POEsT8LUahU&qP22=Oq6D<;;UhWE`xjX5T$J4Z*Jgw#Q1YAarxQ#u z3sI48(Gi==OKDR%)j{PnZE0bURJeN%K4Ab5+1#w^bkiC)l zYu*YPSCpy~qVcNuw+90qFgrn~)b+=s%P$C{y+w3Tq8O3xsnFR#UtXvIy32-8ww~LP& zzDzz{OwDWMji<=MEG1}Q-lV?2qAQj1yqq!U12XP3{AtAH!(G5{i+oGikHRxtef2Nf zUWZTZx%+@vdF$EYi`B0T$xZ!)Neu_3T!uLHS^5B)3T~L5K>eEOmh^ANkQXTW1DfdM zI$3<@mCjAlXr{ds!t!uQT2@+7jgzKNOUozEtun9g4S#LK{8dG&4eXVw)yWrz+~GB+GJ@wR@*#ndKO{Ldg;6RF-ZJ{8d{K~d17a{A%ZgxhO zC8PYq559_>E21nt*S+oMfJW^nl3}IWvM4?)pqWm$uj3eiX=L z@F@P>cmMZS)*=&m88%8S3Vhe&`d_E^Qh3nvePZcnpxo7MO!gz36wqD-Hxr*Sf zYy(nxN~GChL(x~P4aXFd|E_ z;1a9q8(tVRzWzlaZh?LOGJ>=3tQ>StFg6xv? zq!!x&fOl5iaOyF8HlNP-* zr)ox=`z?ggIjRj|X{M(|ec7sZ|BW?%(SdYaG{lm{K>d)0s?JT9eYWBL>iuRkJKf#iiH_-8Auo1%?P*5+OT7E$e71B-Wn$Hj!PB34>yCfb9lLzP2CA=Q z|AQ5?ORXz~`-&tdzeqPudU}MqYF4@!bf@cf)ZbBx!hl6DX)Ay^V@r7}7=w6A-R1Ka z(p4b}b9_Zb$c}#@$h>I6Jgid=UU(>1<}qvddEPhtZ=KNnLB!*i^HalYbwKiT&+yp`(Y!3D*X(v#w;CcHyAF!w4c!L|h6iRg?-d*j;G5Bk)q8Vj{ zRS=N1i$g}M%0u(De@*SF0^~#SI>Y;J>?47$^lo|nKAA39kNw1bOfyp?daQl+rs!MM z*9!t9{4*xO&{;ty!#Z7+ynIieQrGOd^7`Psgb;B=iPi7KB!;Rc-4|gnJxB zw_o`mS3Xpv`@$}ge9QB)Mj3)uu_Bs0sU4R^e5j8&x|GoQk3t)aYRE(7GSVBj0i|}_ zamo$Xbh-9I^sp_Xvtg6^QKwvanXFg)YLRB}-(vi3Z(u5O5JunaH6$?~Z{p=JJWCb; zHtre}?nO!zKNo%`0`g|~iiijzhBlP=LU(mo?*(3^?c<~aZhg4Ps;rG?fY+7489Cn$ zP!c1MFhPRG>Lt&q`lKqOwaYXaJl@XdwtQWm=GiayGwvSwajQY^pF{V8?0@Jlyceum zb3lwBVpqV*n)ur=rRLK@csVlq?$Pnd)QRp1xT3)PE4P8;qCJD8cD*J=s2ov%AWJw{wcB4ue~4#qYq`wBW>2l@AFAQp^rY?wN6;~8 ze?yKffjbdb@8ZDGum?eSzdi*isC^d??^ZMUixc*`0 zmVOJ9!+GheIaGt48!8#z(d;IJ5Lua*5^b$B_W9x_+d#+kLSY`hnhxjn-(xL+nw?Hp zHwu7vDnv;p1riIPC?DGuw5uvV)UT7-)!A&^VAm<^q8<4=5;5IQGl5zyUSU558o!a< zWtd9^{S@QI87hIH!a_=;ThvQi)asuxH^agZWZ^($TKAtjc1+58g1~7Vrc!1}Qmd&S-)x?4}a2(`Z0k18rFq>d%$vfYT|zB}?JG!@ZPM3SwJ%LftOfdb@OP zCl21ZX8qB?{Ro6c?K|Q7G0Qc;2#&!8&QixCk{e1}KiO)BLF|b!bv&5g4}m@}f6BDT zQvC2#ZV$!!>hdRv4>#0{VhKn|u%*Roy8L9CWF{G)&i#lFVWI>iZUfE$6*_fq!Xe|)ljUBdM`f-T z?-1XX4Srlq+H`LYhtw<1i)Iaa{Cq`6%5S->Am17;$OJ6G`8_kjvgQ9#4A`%NiWQL! zVLV|Ya9*+~G_cE73OBMZvkKW8TGDtnAtxe|HMx#>+B(hfz}5Z`l&SkZohhHQFX$>a zsss)P7NZFMiGd5Coz%{OTj>X^*W_r8k%+$qN8{i);z`F_p@v`-qiUQ+`FC;;e++N`&Hx zW*uN^@&nla!usByfSE}_1UpLG>3tt3QRBJZN`~d_8Pre38J4Wgcr4z=R55csY!{ zahX*xJ(z?V)e42rmdLsV#2tW(`N7>Zh{`1T34_&Y9ve;@A_XPyDQR~V9P5oKfxQIY zLy}sRJijzfJ660^1f#D^zL*~08Eb7|)(aOjmfYEq&j{$;p#c?@!9573;!lBr%j-h% zzdfOq69Ol48PBA>#zk^+UW8T5lBf7ZrzsHKh+oCgm3!-U()0_Uxr4l|? zCxg2d4gXQpk0iBL*1E zN)@u2zXI}VRluf1g*`ywSK^dI0q?m`PykathJLc;MKb*#tIsbTo_{MJe?TL2rnhaO zd{=CraC_+tqSMNQuR*V*vUBL>llC`&7jwxtgf}6dN#_0x-Y8yUXOpUgc&h(Bc#^{(#>F6RrFBsbi#reumTY zAjRG=I3PfML}t;(gSzA|0sww>Ao`IC+;&R56~O?_^JE$;p>oOa>}|R2zQnD&UpZ&9`{re z!ghr0h(aA??$P&vS2>9b18CwQ)b`twvx;h?lf;TVFSF!Nn%Pf1X@|Ut!+%;ifMFtk z4cjuXHpINJBV6jIU2}NCy=pdpkrV6I>K?@fxGi$@KYh)=CxjAqVj`JpIo|qinlGS zD|>zMXxH{uC?RAQTL?nY2SD`%{BG~lKLYjjO&Yiu$ZlbMv-r;*EB$xxK14Uj;3oE#b_Q~rmu!qjf zI3Au%m5G)Lc*?W8igd7A_YMSrs@Nkm;m6CIMwj;1k7wB-1czjxn@}2N0q6>|5FS0h zLi%1;6VQ4Sm~c5kT9$?!QkY2^0*d>jcYwYwB@$I^Lrhn`P*q3Y0yQ&X%kJ-#`5uk$ z%Q2C^te+W_y}_wlP8c4|U;8A?DC1af@v03v+S1t(>I{1k-}L^AO?K@;Y}_Y(=Hlph zIecppp%^6~W9*^PHA1Tc*cXM0yn?yyho1;^zu z1LRRlr*o$xWyWO_b6%uCeB5Akkm_xs%I$PA0JIa&E)U>?rf@lbH*Se>+Tbt{(YJE^`L#jb?SC?_vEX5 ztyGiZGkO4fd_VLa>Z3Eu{IimjW8&7Q_8ah@9Ld&cdM_C%K#ka6gRAFsV3c}Tq#wiL zrt|_6p$F^gLZmhDX|a4eI=OGRdT@Iox2lhBpO}4gCQE3-Sp@p=A`t&tS^uC9zkaMw z$FJ+w&>|@;We2))9m$9 ze7zzz9-8HCU57sBBiRL+Vt&LZ(E;SG{?@T=^siaKPr(pEaqj=SRER8AiG=+BVr_2PN# zBe_>QB!7}|OAVlMu7=bG90|+EYJfanDtLE0_yodwVb@y)W)NzMkj}f@j@jCg=D`+H z2FY2}@G*fy>ZzUGH2X&1?*L+l27XmU`Au?k&vqshU~rw3^GGYQe<~uaTQzoA#rG%O zH&{RX3P;Zk?=$^_hX=?m%Xrt zZ_!I_7}t&#J%kkc1#DiuIlA&h$*OMVSLXM4knU63)6OlPDSne6x18|S(R%!s{la?& zuIOCXeyTA7x^&!N9FmH9j}5c9j)dS~+=c*oNcY;DDM@V{bUsgR>efi4jL!WcGDTb7 z3LwGf|HrsuoCmLg*)lXtUmIQmmpe{SEJ|?p{3JZO)4{B#!=3#WO#AcQDys!IkB&SZ zPS?BI4IBD+75#$tE68Ko_0{nHiul{P?SlT^Z<4g09m@I;^Sg@Q_+EM84GhOA;;7Qr zf*0X?ym6MkarSoTas4F$+A*bxe`jvS);(!0l28e`z*s*gSQs>f-K>o;90V4U4y{~v z3qq|Xvn`h0N`kk2O?u86&Yc=c`dm`Pp!Z}bD5Ed4Vh97co-D$w?!y)Hd zZH)S>agN&GKXq2q-o`U_pMQs_Qdr?z^d&St*e;KoSn|E4ry&VRK61Yt`?!G^LX~;& z)NY$r5I-+9(Cz)%j{Of_9-eS_%{2CkMV7{-F4Sm)F0k719qKYlem2-4rD^d_SV0b8WX^Ay1S-;Zgx)Yr#Z}L`SiJOW z%cf`nYzSCAA}UU~N(N!>nqTR8_v_)z_a~e_W^i>|y{~AQl6?v0WE(Cp}6` zjU#Bu9h6#>`X2?6(zy(7w7JPW^hlS%Gq2}331T?uuF4q|;~#%Ws`wb4 z&Dr)v28kV%wzPg7xSN$tJl0>Jh!xhjA|u%6p#Q%DAN>ZmzTIEAMV2G{`$1R?K}v(Y zQ`AbUT_IOt0UNRR*zI9SJw{AuH$_S)SRghnXn8mgi?b(#+2$k=1DhJdZ4}odC%3`> zX`I|E@~5eW;xOlA3RRDOo1EnP93})#{r1?m$n+W76OzucXTx3CXzVPl9=Heeb*S`5 zD&?-+DXv`IhN`>RX7c6qsy1*s39K$C=1ekmeKjY!RYyg)~!sV>_ptC={qpa3{aew|0lI3mN2hjfPPv$7{{qj{ z!L_IJH0mOJx`ZFH&{r0cfENfLfLr*d_eOtZ5L5-Sh;So!mBnojznmRD#X(!- zg5nJX%}tJg?MPT5G6**~GraSL@SVX~O<27P75ShvGs#L!!iS~z0?BeZ`FS*YDjno} zd^3)Qe_H^edOh!+)@0dVI2N3nC2mMxNvVEXR;J8PwXX4PAKCMZk+M9kS!4+SjT(UQ zm^qO>;{CXo2z)XoX}rB zH>+3>!6V*z@+@B0g{ABVFQP0`-MlYaM>uCc>xu}6}L zGI1~7%1H+oHG&V*=2n-VU{c4~-BNcSOV^7$%i~3sCHu#l>=^N4Qgy6>E7h-gp-dvA zi$Tem63FkIVXa6j1}t?6=;B~E`FgYR-MwAM=JQZY3aZ70>&co;yxVuG5p*-F%d!PU zH=Y-&LcnzBLV>Ve=FP?qd(TvM4{tOkO+v|y?Yl8tR!{6v729;uWVL%)jF_f1;QPM7 zzA?M3$g~~je4V5hIP4i)b0j_XocuP5U!6zwoq$(apxlI5MEd2>ENI|PvuNW=w%DWs zmy^4h!TIwAUtPUACKKl4fC7zoA4W2tQo8EDpQ_zjgdlofC$$rRH=2{pD)2n>Vf4m= zK_pV;O3nDKN9G;RwSF|Mi!*JH#xOvq5n>`;l^lYh?Y4d zrC4~0=R+kh+WV%K$e2_>x=~Nm?W$y-ML3@;IeOqX9CwZi5`_@t=@PXoS5hdJhoO&U zdW3vbfdu+&2=Un>bB(W)#g)>!YJyq|eoJC(SBV!9YP)-~jZIfOu?Zq&$ zBW@E#%dTuO0wiK*DGD!IR-*dpWTZ85O6tsa#os}Q=a|liM;Ytc9QX-d3QXt!t7G${ z;NxbqJ68oI^_^S>kw=Scw$dLUbcmjJsrT20!A5{Du`wBxBXLZx1bXE{BwI!mB-|hr zh$$7KWN#Q*3asJehgkvIPC|slFl+mrtR@IK!hW^U86Rq4E#@b<> zVpov{Ekx-6vItPAGl5hEg)ZPwmj7q#=;5sY`uXjn0=vs2+}1Y}8eyZR;Y3>>fB1}-CcaSC^aoIdrh!(oAlTfHw&Rh zXL&6DTo)C{sp3Rx|`!%Y^S0}z4jc2#Zv@0Gx|54@SumI4}G;o zVK_s;#$beGR*qECrLZ@bBl=DjyXP6xX~Bi4WHGiO-+vS2!XEZcHkx#g);M1UBsOxm z49INeF*e{Fkqrpmz<4b1U`O3K2h^!kR!)b7Sv2T{Z(I@@XoeNc12eet<~yapL2s*U z?Kpm1kTBnq>Qek~*6A*@M(Er#*7uhd6j%R#5*n2dy8$q+ek07G7@HOGA|Dq!JoPPZ zxET zQLAwU&9au(5HIA}JzML#^IIx(-SpvAZHW(rq|xqJdYcI{^VR|*;U~f7( z3?CQ9mC{nWnXjW4^2hQ@F&{g;wmpPmtWmZEoiB`vyJZvm1xY)CeU*GZ79 z0t!okKv@Mxy!P|CjnReS0{caKkDA&PwTI98LN)l+?hJfv(Rx9Mi(r03K;fk$YGI*^ zSDRlEdSKTP(p}=Fzira(KGZa08*@J2H^D0Y{`zU)rc5p)H?A&^;L&MVML4bnZ!PLF z@@1G63u zadn53J{g2xWb7}2&v0*i`fg&9Ry_0TPR<~wj`*=2zB%YwbrsRmA4ypT(qIFe@sa>L zUW^H7>Z0n_XA66U!R#A~%x5+0FL8c&-8b^$d7QYS&%d1C6DL>BK zcPf%yaTiL&l91gMa<*X7^I02l`)A`{(ziCg#t@y-U~bee=JsIYExOfJ0twf}(d)3Pu3@twyd5 zD>*`ykhPxhxq}Q~=pz*9Bkmd(KPjz*EwAaGpgMBZc=kcf`{hKM-%B=BnFd`@!b=(c z4A82aZe^O`sKi~5nnvusvw{V%o=~3W_*X_?oeApOmBhE%L8|(KKcMi?rh6#PYbK9R z|N7&Y!h3H;94(6S@^3Y<8+Xd6x{?xxb&}U6 ze+oa|ATY%Y1iDVGvu?v`GH*lKd*$M=0<(y%(Prq&FKsi{eSPw-!{_)s`}EsB&|I?Q z=mZ)1qN+q@MEZJu@!7-n%HbFa2fNM{#}BeQF%u^z!OiNBXeD-NwVZaDXtqNI>#VTx z!Dh6b(MozSu%0# zE~U+SSJ}{lC#b&f#(JaO-+q&5s3+$@5&T-ub5~nECSZ>92CTnqyh2Q$4HC8Wfq?6y>!|UaZQ) zR0>41%7Egrcf`A?N(=M$Q3VQx*;y$4Yx=t3ddh<-{}6-99Kemuu=H>n%%B_y8XY=_^T9p zoQkv#sLToI_U!U4XEC9i-GI1*3;Ug>5Np9)g$o8>ljX`8TJ2WAq7YE(?ffS;*=Dy! zT3V+0St4XYQ4b03DIL6O>rG@94gstZ9mQ zPS+y89k1>%BBXk2i09Nl_VG-;7!)3bUu4_zUZMOJdc3byk}tqqCX`AQ`-pO9<9V{@ z>)Pi!Qmb_>d#GP+?@S(vex~I7E*BK2HW!fXaa2@l`-c*QdY0bZ_{_LE?9$HKG-5`% zDaA)O6&jmP91~N^3Ls~TV|J(bg#z461On#3PIm_b<1Dra5hux+(TrGLDL%Jzzm3Vy z>zO$vYEfMMCD;Ekmr5a zHnq*yvt^9huHWUq$(sB&^i)>{^yhit89mvXF4AC#Kp zh~J?-ch)g`Ab+>sNA+MY$UoJ8LC2SRnG|H zHB|cNL5X6X#Q({49_ve*^c`tM!TZ|vBBv}Vd+jME2(1BNQ<&XS{7;t4Yh3Iptzx}Q z#TY)P{S6^M` z7QU^so!k8&)4!q*?|T|ABiq+&Y&{plv%wWQLvv+sLoe%Vo$T4MsEcz#{a!+ar`}a zvG$Sl5A$+WuYooY#^uf!yp4pT@Eb!v>wtxr;ka(eF6Kd2_r<}{3mldYFs#j?G5gW|ku*_6>du5ln|%i>3* z7Z%#ezNK|T&4OVAYODD%S|+@;j2@0rgbYob=DgqU-3my*czxl2xVHo2p3#X4t*NdH z`*hN3ggwqiU86X)InEk$w!HX`vR8Xhb_|K-S|~l<&8#KX4=IvRA@kb*4aWbYxCSIyOzkO1+7tkS?Jo8SArbGGiLfM! z{(Y=B9oIiO$ojF?d5n%DD9lw$JTMv;+gq=9Zru@%o`wZ{PpHnlY!ttoRjypIh-VBc zLs)yeN6Xi*_MGBKe@*la>aNK0=JV$Rapm%57v($&b&z6clsP8T| zSH$P|D`1e1&<=|v!Iv-mbgz&Uh)k1i5DtX=Hk$1D||{j|L#fU9G2B@ z3`MW-cu6;=k*(=HF$wQJ|GRN;x4IaS)NX~)ADT5A(-=LB>i-a_7N`5;;2Yux&31qE zCkomFPMmyC^`u*xPKBFI&`XURy;0Q4!-nPus>K%v;bmufEkF<+OA83~Iw>*xjT*@5 zhAGk8*DWwlxKDA_C6v$D*D1UEnslj*0 zUVqe;0srII3#?(k>++EFfh-$B<+6HI4R*Q=Z)s~T{c}R;)|Oms^|F?uJCdDY>u{@~vXu4jdyB8&XSM8t-wIb5biKeahVz+d$<2h_2=-T8hQ?Zvi zAG~fX#bGT3yivruZ(L7Q0fV5%1W9gcH5LtaK*YTj z?x^9T8l(ti}Eq^Sd$SjL3XY)Y5-ye@yYC8qYX$cwWvcgU=@1DO)Z0=W8m z;aeO4x{d`H(W92!(P#;yA0nl@8k}@E4H`#NklG(y;G99_L^6!L&dq*)Ugqb>GsB4bt z^F!rcodSOsY)xp+GB5jaEHM8K*tB(4&~+qU!fSh<&CJcrE|_UEG}V*@CsL|~TM8yC z9GFYnb|`wP=1@7-wY+!D{G`wn&J6=ry)Am6;c{`^*hoJyAgV;+wf%zJ*Dd4U;Q^jz z6qN1I=liP=rl+8k-11#l_U~d@(pDmRue3&q<;>kAyjh$mk6(5{ld1;R+14r}F4f9w|9uw;y;s+O?Wh9m^5bOH*O^@n+UC2Id8_ zM>9dE=&Uxl)Jyc50{VvKs#MNB&UUdeh11GyX&jwy9F~1d3rH$e5$s$HUZ9>(x(|eD z*W18mJ&92wt6`X2=;cZuAmy)Yzu~hN^xHu5G1goBdSECZ=$xRqcmh@%$tjxy*jSoWm%O6ti*Ib_a zT)(_uHp0RcC;X*vxX)usTdCleLhmc0XIF6#in-Ybe|l46w%hMcM%NC#<;ka-eeL^t zeExMXO7qV1TZq(NIy~e$@(}?Q4APpvBHs}KjB})df_n>H=S*l6Yj<~Dp3IeQozrV- zGL(gaYu(7L+j|2K=YZMz{lABU-l^@-XmIQYt=#hN4RKx=;&py5r-XJ04{^5qfNbds ziV4Xi272lLuUcnxp^d2k!nSrtX6K%}DpVWzaLPgE@ILM+-i9NAHJ|RZ)NLk=k-!N@79(x08 zr4n6i{?c~zZm(Rtn{_p&m^tmAQL(Ky}0}~DPd#MGe+*0 z#JSbjvv*FnhSs|6y`I9)HM4hB9#ohn?5}T`f-9XqF{{RDr|u3?5KM?`+oPq6Nz2zQ z-MHlRTC|1_y`SF7+n8mJ){v}=*l)KY^`Jy@aIjz=MW+4><7%@_KaI{hk3~U-K`(~Y z#R&ei8QF=$!LCd7+AlAJibjj7s>wr+VlO5ICpgwrZTkEGr^PH+i7~1fx7jqea5j_F zu`e2-5{WlCenH4ll96XUUnS?IwMKE+Ca<{xAK_n?KQVjz7*Y*uxJYGTR>hGWZL-fj zNU`X%beH9vV{&p?h32s{<7VTRx`Ty^C<-Y#zYOS^-hULlv%r1Iso@-nZ@IE}0!!NX zW7XGRtNd_e7=un?ANX-2MK8))r8l^Sd-lRn913~_$2-1c5TTyGVX2&1N)(I*xm|WhlQQXWcPtIO8t{BQRq#u@wB{BM+Y=9(mw@~eTE)kS zPRv?rw15B9Wi&|hxoTq@#@^{!bMl&G)W~#hlj(kSN^%Kr@+~{8UXs=Ea?Udc- zW40Hqa39wecy2%_inu6}G1JoD|9Va#e{P_RLRS%$JfnU5bTvO2#Ch{7^9mhc zIu?I?j9C^D1S74$h4TQQ;IrIfqnEzfb3FU1(UGo0>V1DrkXEz<6DxHnwX{9x1X#)* zKz*MjITC`&H$f@}VOfJXxEH1XEnS$Gm|~fodFC1X8gWEUEPGgGh?^7SmY_eAgebF90xfAEca zeu(|+a}4U~LnsNIy4BbqjkqqdKu;6ijyp_qU3J>g(fQ)9bGXE@hD?CRCeO zYEIh`I83C5G@BRS9UG;UWwhPQW*s5vy~E4l=tou`YLDlFQ~OqQ2IErU*L91X3*V_O zDL$7^nc(+$z0(i}6V-N=+C8HBUY+20+a^)mU1Fj=F3(_>OE;jgnqP ztbEZ?9!`;FdRjv3qhVH@Jf{cTiwI#KQ4+mH`x z@&-p^U?P(CQ<$~Zv1Nl=trc33P^UqAAPIzg>*cLYiMq7eU&!h&T2^q6{_Q>fxI*7n zO`-S93f~jfV#BHsEa#6q&y)%!yM*XpnOtFdy7Ri}69sSUm*H!ylW|~{pgzUFnTllG zI>9NS44m#Re$<^7-DB?qq0y)slW_|MiDcsEIlFs{(|*@S-41FSH)q=VZ%$QiR2$o6 zvro7UUN%Kw^v0bmxkF(iv?Om-kwM|>eY<0Y#)K)AgQ;U2X0lnDptY3KK21_7+9GT* zQ~*U=`lCD19>+8KSw0Ne8F1kYEb`T@nYsH*E66!l6hS8{2C)TYA@kT9q*`{S>tpf| z8Je-2k3`IO_THs44Axt+y;^k%T_r|5@>{q7DGfG?;7~y@!X0+03;7;D9O|)eFOvW7 zOlQYr+d=oZ9(F)H-$&-~lYNC&V_1UVc*h{9MY0{>^7zl zl(t@PuyQ_mRNS?d#r`%@nlK#3k8Miv`I=nItGp-hS?8}2SGNp03dMy~n_9=#j~wnO zDaz|;EKP7f8`<3xU8+w_xN2jCzOR=O5k4|ekkqbpEk?zT3lk%0O{J>m8ouWfvQAb+ zSDo(_+W8H(auLEh745+cEW0|g^b}GWXXpl_37H54vNtECeX^WiV=z{ZW1G^CwN}N~ z^r|C5#b0f}7!3?Yr@EEyH>XUy4?+=jv9F{fk3jUU(zbptjJRV<=T3c6nR|%VpE4UG zT`jVIWv6)&wDdlA3pPz11HZU7{2#?7k*z$fw33zzQ?8a+!5%g?V^naZqzIk)c(b-m zMeqAc;{n%u^>A&u$<1~V^c|GgYRa^}oAuWDu=mk0cRvnGzvXQat{`TW{cv1Ttjb8+ zS)`#UwPPDicYSLW8DF|TwA{Np==DGq1@o_&r|U?kiE}Qp_by29$x^EHb`(9La1t5a zzi;`->hTr4yM;lePHo+&1Ni~syt7d(#`$*ZczH}*Snj0o<*dpG=bBSNFA3VD-=|2@ zugK-hXF}!UA^}McD0(F^ zMe5Et3kD!`s~e+FW(N|`Z~~kQ6?}VSy@|-$n(XMZ9&>9=yF>Pl;c)7u&-v*ipn>1L zg&W7#Kp4{>L#iw}U)h?P>cpwVJB#EJm5N=8Hw`e=%J<`i`uUu&;~H98f6^)bPAW*| zZjAvdS`#E~h(E~&@1qxFL~t->$cc6{V`00A%0ms;_L9JLc#33)xiRqT0JqzMsOFV! zH|HYqriMJbW(Xt=j?nA0+lT7oFnOzGJ<>@SztileuyV;?m$wmbQwE0)Uh zQ_Fo#>+=n^eWIy!_>r%?#VDD@o_w3&hA#XkU5uNnLOjkFb31RhOwvweDc<@L)E9-maNP z9~$!pH{1mY{sAXbqz~Z8#YKSmI#>!Q$l`_>m1*Mer8A?HCA#!3!KfNlmS6m7Q*@b> zM&8(11!+Qcj{)dlfp#&#yB=-$F@@nU{t|m^-0+sys2c9~B9n(h#M>Ru*`oV04kE`V zjx3@ZMGLaDL-?T>x^cry090$#3Ol)AB)YSsQ|j!?RTV!!t?9x%m$M{X zJBzTv?M3=MG9$eP6mteM23aGdR4)0dv@NnIu;X}L-?r3^h9(!=8L->sT0A3~T5R;{#Uhduxxds$n^ewG zUCL50SYR1%R$mr!4kvRGyN9EWK8{FI6GG}r?J8_9SFDeVNwVBXd?C8x6CBDE*APk3 z3!vWP=yDj59{}g&;Y&bg+aj$nQUe5!D45_mi^fQS6XT&*P zE2F)3TX{?nC%Eq6Kv8!TC{5mpWGLrsD;FjMu&R^qbhW#%_M?)^g;A1S*Ux z5XsxrO1R+-=@MfDTS<}R;;uvDTBT!wt=yg1uL7<9Mj$mY^gh>>f&`j>zsv7Y<-~QF zvk{eImc^nM?g7sl{laJ??#c_1Y?=5eecAy*Yq`%vuyZ_Egjm?C%7qsxNC-nH{ z>Ml9KUY|0wO1n30$GP_7-d6TMc|Rxo?r*xx{xgO|9hQ)$ZwcW!SrgdZ#NU}z;8u71 zlEE7!R%-x9>GsvIXZv2gn7E%xMka;qW z(aUJh|0vjMMW_reGFq!!bC?jlokY#|csQtXF2fleZiS}Ib$>Hci@j5OV5-q3iYcJe@u+ zt$iE*!OOZzM&op2Jh-L;NwoR@T7`2uuA7sd5<+9B#iI!&ZN{vX@}9I+!WAV=jw1f9J~ zz6(?jCgZ|+{Q}N*XeE6<_mVctqW8S#Ecz^R@R{S^A=*l`vxWLWQuMo6)U^R7Qg7_M z{F~T+SKEG3=z!9KR+Wn;31X?=0E}a&W7io_S^eU3BSB!8EPrM&HGx~Ku?TT$wj+Sd zy-;Dol-x3H^*se)GZS@u?NYkZtUstZhX^=Cl0 z4@s9l+UW@Vtabt`=$F3XdVLr0=g^~mu-Ki3k3E!7Vg7zqfH6p-Fv?xv!k#rzfwJDp zop%GToKO|IO=PS;Fqi_+5E&rjm7{Iz7DyX1T+>&4xCzp#N1 z*BBb84Yund2nI`WktAsxmc>r#8liz-r*8bGTLnsP9c}j7MZcwuguN(rQ0jKU`M!$Z zZpI|4dGLtGULU+bJvjAqFq_%w6M^5dFpd37QuT{OwLf!1IEpB7soQa>I5RAu9ld`P z^-bv0Ud#2Spiv6MN+f@!7kWtT8mQ)1Th2T2C%v(127q;^r-s$ah~(K(zc9ScNPGKR z<9na7g$1^2<{!GettPatirn(?x;P?{bVzD2-`P9PkD<|jP7N8fE1)=^<&!pW}9`aP(II^Z#vMi(TSTbxi3@vMakBaxEl0Y<4L zj1V*=vkf==b@uR)fYsb^T#A}Vw1?p6w@3M<&)Rq&=3h!R_slSh6gBej}%jo|#5=TW->~K2iPI)9!<@u^e)XoAd%N@oofk zrgon0)hK_;((LSjC);1APkH+>i?;&01@EE%-Y62Ui8e`uPzR;Izo(;X(NmK4P-DPl z?@5vXJx1whbUwLlHq^H&nKo#+(6r{AaPfMQOM(fR8ZcUhMZU3@T3`(9P#;;+YEd&& zBN-|?#hTulQyzLQ=_)sr?2Ge->k*C)OQzDbmkk#r92*4_AL&JAFUzjCd@9$iar`{9 zVD(F(i{VoXqj)0i^OObLvq&XVn`rR6f4r$yz2_Myu(~OY3 zQrosI?$n>m@|I|$)R)Qdr|B&AMHp592zH8j`@FWz?ZTLlUnmisr;-jtfE)@j%}7% z9op$(le&2)4SLT02M2MMFPAX~zaG5?BoXDo-8ECK zni05lbeYUcpfwsFF1hkTgYA=uk{MJ})sb(onI9X{^il{cbTR zaB^0--I#nhDsCr`Vk6p>4a~>-3PF6l$zL`&s(Fq!?d4=~^Ym3u1b8CvU!_XYO;>EI zURwsR&lMJrvCn_`^jZE#VdTPWdA`e5rc_ko_Q zWpIO{FtvvYLfOLtrMW!Y#hA_EP*##i8B&y>l#J8T4fCTQQk!!Fu9Zbu++t@Ax2Lm= zm2ZmNuD|nBQ<3(7sWGkVn9Po)ru9bzK3ey#Sx&a#Q! zbZl>(=az+;uGLuq!I=1N=K0gV+-lI@BEwtiHN~Vp#;^`zaTrO<#(yEcTpw1kYH3*VNC%0*|DaDSO0M_7zJH zI_vo|2tvK-mF=i-B^Dq8cbaeZrXz7)D(g1sE4zNrZ0TA08MG${JY`)uEJz8WdZ(F6 zk8uhbhqewW+d$t{dB3k*nK0JA$n=yt4kz9Hv8{s|a7I&jEkhf+?d`C%t%~-Xpmc$j z_+2@18Om^Us~)5ql;&si{^4nMunc}?_#g#j!iCp z5Smany5SiJ%F9{))ZVUcFk{(#coD7i@*R+)R}S`;14&C4)Ut>$~s99VWy)#uKh zLtArk%8)sGAL4oDzA?lgZm?uORF*I=Edj3M)MrTnKDO@C>gs+F^;B+_SK7!Qqs zUS9>m@N`?VE#7b$^x{kTPaY*4lE)LNBxaW5_{M89z1`T*giEsLe5obBTo(7Zrhb6m zL>6gr2UY7QgAo7Z_i>EGg5dC#Hp8b*8aQ_;7AKr~l$+98rZ^d%Wgl6a)bCAV^>j&0 z*xn#vC74l6v5YP?P46G>;dKL0FcYY`pj>=EXSt~5?zhS?DRa7?bx+?O#EdCIjm)tB zV~MQv$73AuWqmI67ivNpm7By3=T6^zNRjW#BZ(2JdQng|iwO3ITwQAQ$?G@B6YVT1bR#7BoO62{X?;klF z32{8~-1l`~*LnU<;tiLbDg{s96Tc?obL+SZ)$pcg8`c^wszMRITDGB=vuDa>-FCD$ zwrVoOvG}lxPVcRCdm0&+ zR{>5jlxN6ASE8~xt3fKeeyEs%Gmi<&@Ch{bnr$EfuGz0P*5<&&8zc$UG zs%6fvWvPElB{$y~=j=*BMh^NQRkP_NzYG@a7Y*TsOuAVH#WSpG1d*<2yKl9)#txF2{L|X7dA_R3 z#H=0r8fR5!ziQ;i_#=~t=wGm^aDkL~dn|N5V#OvK?iVHR(DN7C{E6&G_u!TdZE|24 zB-`NFp(*3Um+4@OMofMq4$FfPWrx0KT9Qe2Z<9mc#Sk_RfS-OhdQLQ|eH68ip;mAgmo6e4+o zLk9y)t0w={;zP}6e=fB*{6~UMhuB1ghORcl8$kEhAon1Cv2+9>8u$z1FPJ6oa`7&Y z{Fs6%ZQ9cyeq7gi7*J(MVwm!;WQn68tS~Li{cP>&AUGyIs5zR*VqwEk4-V?RW^ZLN z|9Ct)^n(T2u5vqw4%_@={KLpPR9P?Kpg6d`KTik+mNl5IvD@xyUk!mvF+Am*{db1V zIp+eDOU%}YqZgB1Zg}texQupBjB=pKLK6B>1gOmGXK1_UC8SQF6$jDYZH}E%r z2r_V_k}L*DZc843K{2y)&5Bx1mHU_X16Uy`ky*BnU+a|oZVz($+^k}W6%is7$L`4O_O++_x5)P209@w)eW3C_pjGSs zvL5}B{l*XEHzE__9$K^qe(O)jZTvGSbMI=}A+C<*sl%xqLx263X}`6rbRgOenVTQ` z((LX7du#V&RhMe%!;vXV6J}Zs$2Y4GWrK;Z5P^`H zE^-xWNb|%XWmLmHGA3X*U1bs`IY_MqBNJt_^9rYh9*NRJFb`{sl2?+2$UP`1#l=3f@ z-&wxf=&@%M^Zwzsa@@sjQ`m*(8aZ!DtGoDiL%?) zq!rKIEBEKJCd+Z_8GmnQW-^KL>Po`wwG39v_n3@UDHoRQBV~Ws6`o%UNCoN{ZW*M1 zQs-K^PNK2>vSMdb^@M-1>a{gX0OerUzkQ80uYzBb)xtA6K5td0)6Yv0)&X<4jJ?%u zkUXnv&K(o*&2!LjT_d#_fC+yiA7?&}+#b{)pAYg6ZzpW8Sk z$SigAYLxboY0e)r1bxbzApGqMp0{Pntytb&Wu6gn=TZB=zOt~9j?ftpgoe1EZPg3XmN@wySrZcj%R}w)WIbSrQ}uY!TFKVAgGrnY zAPk#fTKE3tzH)nZVrkFD&Zs$QZ}nKa!JuGY=5EdD@ykRnxI*5x7|Ey?>%Ae_4=5Um zCA~M_-0~R;XV5b|s!GRJtNAPUb|q*veC7HFjbHn{(+NaZ-@_;mG#2gFtwP(r__5`@ z(yh!@c7Oz{Y8H{v8{)&PNkUvi{ZkO-r0e zG@`Vz_IukWmNPue8aO7Z&|#DAUkk<-=X}54&_AV$7MSyA zt$8niFZ8jw<;=l=)@PF#yhvzucT#lJ)fd(_A#T3U0n#h|08xF3TLS4f~D)4jEb zJ>@{mqiPJydAXa}vTBK`x?nHhc6@RARA7!%b8aliMg8;C>zpuU*GVNo^r%(uDjzU+ z7iC#SjB8>!s~)!FgR6E=IP9m+kLUjeKxRe!B`lt{TUhduw+`)oq=o`iDMY*;J`ATq z{Rk+9(|YH?Xg!amaf2L7Y)!mR1^*KFywt+2NALC-o?%I~DcUOk9TC{j%UzL~3Z*GX zMBsqmJ;VsGwcPi4P=reB2`IV7wnqP~=l3@4x7S`(5d%y2;{~l|7<31jw1 zN0K%%%__3E)iAW4#C)&qJ*;Y!sFIOq5g;jr#06HCms-JO zs7ix}e~wvVOlT6c;+nB*14PvptZLu#Z#JDSd<5DmpJ4(2?$O+7pt9|MB(LgfBb{5s z&4(EyOJ=)$?5le;X-GVmK6G+mk&zZ>!J1cnrkLNLz{VmI;Kw#HA?@tM=rUpgzy5T&zV5e@{`0D{9oQILtpdG!Xsdyd#_RTF6|&RMo_kD4+~_wNUK`>I$= zynjy}%WGb2;w~a?NRY)BmTHv|bg=b!o?c7UIBA%`>gq5X><&WlWkXwSf)yLpl+893 zFG-b}j%n~PSUTqN9Jv9G&uIJ7NtXk*k=1Muw(7mCNzGP`45BdXc5gV)7V3W8;`5n_ zX~8u-!`>DQ5M9DlU|GR9;LJHf^+`4fNmh~uR<<`+gQB&R-|H`#k<)SSFFGu zmMao5W2o;F%XTgAEiL}Zo=;ZNErwh+M;G|ie{y@bFml5&19J!~B>(Q1L|XsAI`93d{HX)cdDw_u3w%dj?i^Y_&GE++BGYHH?3n z=uxHqzIFW-B^Vu@6zrvg8w5V*5h_eG4ISz|(|aIhf-XAC;W$XNGC0j5^>0I3SC+@| zv&noB`jduK_B1%002GjEfjgZO4g9w6wI<|5(6qODmds*~YUkD7 zblm!oa%X;`>sFBHdZJpVYLM7;kj@73wzXT{&H5R(zEwG#bnbOjPRVsk%-@i~`_Qc3 z0RvQz^Wc|o)DoQJPxG7tJWNTlVn4g9-vp;$h^ZFEK)XGQ5FUDJLP|sKj*SvRzB01h zGwCijW;0|sTuD*+^r$x&4k(5*z8q21n|FT#=?;_=cY~f`kAL?&(M7v3+s~co>Qago zS?eg?xW5y{u@9`v{WLu2!QT8hTNNBA)@o3}X}jnRkn++=jnj&*I#6PS1w%-0IcM)N zeIDTwDnCx55Y$4u#G!OH266L=L< zMnBrt0j50L?YZ{e*yLVhJm9#fKa4I0;1Lg*py;EUe-xh15d6^`nny-a)K@uy^6Q_$ z9DQ1&Nk%{WN&LG2Ck-PaQwwmF@b{SlfX-svPR~rZ@V!3HhdLfYA_U;nquRhaHlTU0 zDc6Oux2M`;kxz{jb)r3q^w}2{0Y`(VgJ2c-dj_eFlli?05i1(O@Z0jJ6k9W9F&jOh zQPC_Or*x8As;o@Zo(; zQOBkI38#;*MPD6}2Z`We8=xql8&uUeDyxl~R>u^g1?>bxsh0LCSk3jMzqWKFu4{)` zh=8C{s0oVkUb<-2Tgg!b0~{Db*W1N}x3a>{A(s^@jK%G@N1A5+3((suAiqbtKi*@cUo?ukSxw+nO@@ zJTPf)16O*FI!erK@uIKrWvcH*I+^zJNjH;!04;~4Da<(?L%;H_Yr|E0w1gGP4E$w; z?O)6xo79c?Li{`?DjI#2PwLu9-8_$il_CbM>TytOs|C00yieIL#jMa z`6r+hDb~%V0Lnj+53m&LhpeYhfcgt$k)lxQ*@MPoj*)6F`-Na|6VMidnnREXq zUQoWqnlm})q5dEsrhzIWANZnt5$80aq=h-U8)QA{qbzDMeVVAI*H|!f$gDM8b8rxz zc$qLxK0PFmTfOOJ!<31MxKh|p4HCn*gQ5s#MPN@RWMCljSzGo#lW+O=C6w2TJdKil z4FSckZ*rhZ(0OSWl%rk2;6YLHG{x6~jD2 z3^q5tYe437>*B3mLqIi{fnm=grRiySuf zM9isZ1(I^G@P65@rOZ55d<170tavZtC5|}~?#aobC$_Q`fZ82&ASMxtM}>*RA-n< z$IJY&wtMw$WdHVnY)a?lu86gJaFl0(Im(WP;P2f`s;#*Xrm?#_>Ul5h=RFn2J8vb> zntDMREHq*Z>ZHY$zHgc%F5`$zL2Bqx>i#yHxmb*{$hg_GsJ%EC8b~^NFJeAi4sakz zsPKh$i=jYOdlySMs_@}lyI~<(nKld!Xg}hQYIbKwZgOSyKhDa6>3lEpaK3W^3 z8bhjWJn}3K*=F0DjKu#eji(W*QgDws zRRr)}$#!%vJOOhX6r#@*@KxxFGZ;&vj)Cz)3eB#b^$&6is!62pcmW4W`RgH#bi!CMa?A{nfw=zKn?rCgzDweb%fdgl^D?}eX#aTh ze4FjZS~Uy}r+OuXPT*f&VEI4H_ybzNvYPJ^N_9pfX*_{E@(vE@3Ffz+E)#QOH5pFN zTZxEtzcAelr<6nP?ru=1f0UKc*WPrI{=e4W889ELF}o+&KA8~CyEe|zbDmTg`nFj6 zU?r{Qf%kx9xLkFG-t^>N_;@Yha{1GVa5JF7b}4z8@bz%x4QO96gz?e}P_cH)3A=k} ztft_ojdbtBa0`0@u5FJg)pms90OVc_D`6(@*RC!1y!U+YhTd%1^vL@A0hX8kz^ns0 zQD!O)ADIB_4cqeaF3^vYaqc`o%DeQDv8WQ;09JZka70>?GW1ued%=zR)AMS5PmZ6@ z_b4mmRTEWtBa*z15@tM*jTBRUzPm=n9!82_uzubr5`UtxOR}fwX$#F}^t5u@tX;iS zxf;Owhw5eM$^^GZ7g9n9yV5=mz!+3=rBjk1G#$dcgm-)F({&I(YPoh`MjOA?>v6{w z{p{E)V?S?p{YS*a>~e?Z-dR|C-rirWK08QO+3}Bc@*z30r3$h<(iFUXUGJoK@pAf+ zeLvC_&ySt!#kj+E zwthy|x>6@P!hLn4l1)1qE)v?C7efBZ-&o6MJ~<4NvF8@kp)|>Zy}scE*E4dl7AW0P z5WZzczxg3hB!lq(fd7rk+KYdWNx>X$UeeS2pQc|<;;!nSJQ>uNj2muNHe<@Ix_Kj~ zRbJU^ROI{&h@sxP>dA%)TGM&pnH|=zx>&VYAhB--jJ*A@6=2Jm3+~N9TdnZ1q397t{W^L&@@OkHr1L zd1bIwrJ-^_|CMK8=nqontHFhheeE(R#lTyyh}G<0g`Zto4|F<$Lth*=x56K)V3RST zJ(_q8Mq;Vd96tFvOXc&8Y3e(tpj{5hI6TDBnPi9MU@qI5KD;k%f_?oJ2^raY!MI3S zeM1=F-^V_^MOjX{Z`0NL+f08-34)G4u%&BoJzx4oQ@*@;Lr5e1yZnPeq1;2qZxAZ}hI6w6=~tt(`~|{MsQAm5B>(Cy-lgxX^)KcPb);IHvwl@c zw!RyDRN$y_^MgSW;z1#YZ&K(B-!0|A4a>05-hh}XpTJ;^baQoq7Nei*5xaJ3gg5wk z2u`s#;88r&d#Toj_K3Ih5yq+bu>mfYM>4ONl@X`NEI&Z^V0y!PowH0j;k&mW<_Shn z@Yr@_Zf*1CjTi4rn(4dU9i)m1YI+R1Q&q_ZzvoSN8b@BCYWZM-fcHZ+7m!_aABz&u2g3Isk3Idt zxUoo?GI3fljNK^9x=6nG_K12CG5CPA*7yx|o7=q9ht$dBu+N;Y*g<1RsSl!$z2@PT zj*mC*(B5pCDg#+^GC`4L*ImgP#4hKR3ug-()mT6jW{{L?0s;beE%A zQ)2mfcjQM+Y1dzilbEH*y@a49DEK* z|D)hSU}!#meb zXh+wtIkpDoT+6^el0WggNW_z@JY@bUxaowl*Beb?YzTi_JE zAbM_qHJPzYj_$lc5RZ5jOFAfg7|m26@RmY-v?b!`%l!PC&+Or$3J|^|ogt1+NERpWoj86_eY}6g-s5or})t#oD1GYg9(DSG`Pwb9A&;YRPu!>c=4*_!rYa z0P-ADi;_Q+FV^9-rq=OYpMNwNt`ZV1;cTmrrX_gjry-M`@PHs*r1ie(Rnp2o|7&t< zy?gq}Y%tiMhi<4wHR&ELD>{^X{IvAn$E5n!OJPGjABU~rXptPpj)%=0EoSg-@|R7f zKf<=u=0Ui>4?;?l73lvX5q4C?va0dkd|L;?Gb#rXc{Wo5|C+`XxtjdkajOa){wAH? z`sM;Gx0$AIA^*d$m#q#g4O8l&APrkc(LZXn9X)gSS|4dvD*v~%sv4!v?tNC?EWa;C zIr)_I(|t<5#pDn+HP@;VR;HnR&2$`Ccv%zhRmycdHisBfly zS;uO*HB80KhtMi`CJDsTBVGu?gcS0^>%=}8nOS9(YKGr$NxsNru&(2)*!QCUB0?~H!pbJORkW^@t3~+j$k%7a7A@$=CYG#dE$R0vWJwH1eg7O z=y+t?_e_>W@4FFytQhNq3YFB$n=*2|=Q_kcRz?MCvLieFH#$hXmYRyLn|;%`#rq&E z4_}j1eh(E2VLTCyo%ijidbs0UaF;emlbHbBS0s-`fxkhP?9$(qA`-jm)!l9?>~=v~ znOP`_pVvd4bz0093S(^E_@-@J3;#HLt3hJen7mDs5Gro@J@G@cH7&#;F^XD*&OJ%b zg6pf{uQJ7Vl+`Xqg^L<{Dd$~(UEukgf843Kr1oP@7BX_)5=}0>$`|nSx;XOfg89!= z+tVR1DUEhH@N8*G-wwdT4! z>sWyY=FO;(|9NZ5WX9a)-8P$8x2JPAv8E^qT-R7cwyJVAy}M)_6k+~vniRj6E&BDrDas@i`#b?d}Y1N z#m1VBSF{)_lGwsB-nGAwbvM&0Gw(r?@qWvk2O-3l=(U2*4>YD1Xp?oDTPKYR>fSS< zOOJcR34!xo#co25G~7d;JYP8K#rhG=vBZajC)gCK4OK>q-HZ61Zg@G1t@>eO-_Vsw z(1S?~U*q))wudSf>)%gi2R&TL_GmQ0wXNCGBig!RMyahkX;zlfVTgG{kzZ^?^P`6$ zHi8?<>gV&E~Z`o?Omyi8)iXd+0N&w*M788A0z5?&qu@_1UrELw|I#M-hQl&!$yoT&Wp) zlj*_0)Q>WG-ULzwvlUwrTpEI`$8s>9t><{39`bar$|U($SD&VGSMJNg#~zeM%GsaX z$$zr^YokMM>A@rwJRw}}WSKDecRvCeL$vlmSkt51*88k&u0$q4ClPCBA)?PJYN+Vw zX=fZVWY;*O+DMB32#;2?5uf>_xnVfYOILPU;<7+j$;aw_>+9+z`mp$)2CATSypW>l zZ$V2##7O&O$OIo-Z`IRUj$i>J2%LQQ1#E-|;eq*Q_N2AB#-q8%r#aB8C<~9n z;$Og0pEjR7R_P|w@UZNS$t;w8p%o37*D-jh(o zrS%=2D8>`Mlz==1)=Iw7^Ay;*1q?Ow`gW6q5s#8-aMHlZR_yK3hkXf)J2R$~YJPh8 zSDJ@bfe=bz-=cZ}2d9CnfD?F$?- zOP^b=v9Uk)nmH>JY-b;L@!AZAg?U*22 zS?_9Dow!E(vHyWaT3+9%_3UXBal^1Z8(V$x;o;p+`Pvew#Kwaq>2*I)` zjt~03L_;W*u+g9r58IN`L|D_xgq&7M7=@2#Vo<; z+i(+5_{ZNt-WqwipY$_pr2uz$yxoDm(qka=s$4`_Wc2fyY;t+O>Yd0wVpi{L zn_kCJCLT!N3UX~aXDzKPaJ8IS@{JeCr_#=iu}u^J^T;UNg?^euRyTw)?5S|$_zwCT z*FJjp;V3^!T}$|dW^cP1V|jYMgDh94kSGI)e+ipI^Pt&unQci!-~)w=fR z1Bn%;B|mva<_KIr$0%{EQ?nU=&lN6#{_!~6Xif56PQRy5w6tdAc`Ncn zN^m4m)c{A?7jwq8Y)87Mz&99K<6~~|2sI6N-?`GO9?Df8erEqX_2I7pPB-{1Xs0CB zr=dx-twqknMg|k-Lpx8B2M&q!-R?iZyQZ!MDf!Y}K2`gLlaYFDBJFyyoAu?)T@W|dp*EdluS zdq0$9zqw{Q8@z4$J{0;X{c94-IhfX@nHJiCqXb}C4EV1w{bkHf&nTG=t~A#(6dl7~ zI}`NGC(xxOduLcO72psB9x@7(toq(DV=3I@_ zjmA3E%DN-p4b{p_P{_s-Y{PLrt!me|>W$_?aAd>f!&<|s>OtUM63n{1@$(5h>c z`4-Q2Zo2e4Ov`6zyH#;nH5T`$Ewe9_6VjF$-S8VUxC;*~u{GCyf_pj4JL{BhsI4uw ztl=r~?a0hS9;q?yqZ*Sv5Qzy?WkA?pS?4^R_3n$dm{sY=vK zgmr|z(J4b?(+u$u{_Epp5I;`-*2zZ3xiev*MFg;Czrv30#K1+QZ^~rnHhzwKW-?`N zd|mzH$L>>(&(lggr36p}I3Cm0r>x$8fMH8cSQ?B#aTRM7*sWRb-(Bk8QkVXv*WtYd z7w>zsfI*Es#g3&H7#=PppH)Ct=ybaNEhoYjyqEM(WRnP1%AY;nWYZvJz7L zJ-?>dreh9306O+SxWr91bg7elTIpe%Uwn{Bwe^o(XpL2WNw1R+BP!|O_E7oQUfolr z?`0IN!Q6Y)U=H04L2z6M7xw+M^oSEqG;$q#khoe{z0@rv3&ej9F^=d-J)$&s`l5Md zM*5z6QiTrz>b+Rynfi(kE^`A>5_#5=De;9a%x#@zm?y$TCwa4HS(|+HlGvgl6AXp&qxIQ-OEXdRs}~0O7W3;WLTJ36wQ~>>X zAI%2oU;}{zePRep5IwLm4I-_fDUdBuX$z${PM+vmw=~EI2%Ej=oRsFp%4DHc?;(PfL@u#+|IRk%=uSUWbd+WIZd3KA?j5uX zpI-^BcmurE1ANo!Z9vSv+XfC-k}lSAQjLMT*PJe>^j3C@W~`6g&3GdDX!~O&q2Lvz z7DhET?;duv7({U@=cCFJ#5UjX0jnL38QU?PS5hNiso<@BRL!o5K=MIjRsm=b5BaBa zq~e4Rjmvs^^8x>x5_QbT$W^XgZ|H3+WAzfJm z_38@%VjSWC%KF+J#Mq+JLn8OIlnuC7R^@Tx5lV5>b}`3vP6YPmqt#uYUy>Mrk^jDp2+ip+RcC1X4 z5~d0G2*JVluxf-LdMApYgQ0OjD<}35W$F&Ln2GkEH_lgR=YM| zXx*giu39C5ZW84H#G*9Kz==-~IhwU;1F|ZhZ0*x7nqKLd%MPw?;U#m_pH+D$C!Z}^ zJ<~d7TmA@)Y!cxO76hITvO=qJBI6s!>7a8dwr*x~bs7p_*Nkah3E6Z|W~{>NIn6X+ z{RdniGz7Z!uEaKqcn)OrU)X^(@;>3oOj+uGB>k7-iQChd*(wI@U->SGU(T4B>j{+i zH&)slT%c)Ae;2(H8*sIhKjh!9@zI4JRQvV$ak9=xv-#=z=KTEbNX`CskUh^<;p8cc z3VTjp06a#CYXeM=FU3&#*fFdi<^hx*E%G5^y|!uE>5URY`>zRJClM0*XOhS3Kq9?m z$Q3&JtU_~fhXyj&DNTE^Gp@?OzGFls`cVgf=eWpc zKzGal#JsyDrRn7Txg{MXzbwOrbe*kr>9v|~M*ahU_QOk0-UiccX#!2n%5jC8Uo$Bu zh{mrkLBsDE{y(7;=J8g2K@uMKxZq~a`<)5Xmn%EF`E!kBe}DkpUmqRmeoj#E?jhj% zG>$9J^|g;iy%|cWZaT_tLS+zjRrgPo>HeRhKB~hqG)C8KS-BM`x@9>|zw(aVD@nuj z7<^%O{8h22;Hxq6O|nNi{WE!^YZ{2Z?dU&a3I>HJP^1Tix@O;7c@Ft~9{0>e?{{?ori#s?w2E$v;F`# zg4i6D;vtVgo<6$YA{lKmd37;~B;1;y`~*w8+Bho^dcP@m4V@1~8v|lBwFiK%UyC3R z8~TR_wCzeZq#FEta7*uDUcLBbitPxf=M!jOnq285AJJ`{*2UDNCgk4J|j zwEPyTQrLJfY6*_E1tlN#z70GUqag{}Y62aFG{8Q1wR8SM7OSF3u|M|jL=eeeD3PJl zrl|CT+2jl8zL595j%Y98U*b_F%g56MOM-gWXdm6G^WDKmgNAE>Btp8%8`oJtw>Xe< z#)5Xd_P9_$hY!TNbC?azyaL!vLD^S~L5%2?JG+45BVCbr7fDO^FVc!=4D@F=`K*s? zfBOF|EqR_B(~m0l`v?7tAn+6nzR$M#J_!EE+SW#q&Lm#8BwA_@LO-=QSCKbABmw=I zIwc+`GxI5 z|EO+t&@8>vM&;eD12%8f$l$M1m0Sr{R-#w6bl9>)h1mdJ^{y4t^pEd`PF2KM^}jtG z%k;~?yntg%h(oige^>y|`uhVS<9YO={V9+eFI74vKKq8<<&f1WQ2ty+Ci&Ui+94#< zfw-7XOb-yfjmR1wDOsUEY(dt1kl9Zda#ws0oUK_+Wa7NeD_;i$p90^IEdp2UEjBc! zb}Z2|zn1{n=qB>;gBC7SKLgKRuIo`yh`?h0BMFhbhV+D{ zJ#^5?2bln`e2X=U9U440{*UBh3MeCjq1y|7olTT2C)~i3tT1H?+sj2Q*!bP?{ilH} z`TRh{MsWhrR~i|w6vaL&zV}s^o{PBuav|#EuvJu$F%AnJ{Fa5 z?GwTuItR(^8|$h}N!e!85~84LB?NQ-zklAHfgxw11D)xzm!_c`C&$@Jp$g>0%=`@O zPV*5UgJC6G`1P+3ac`hSv7r*yc`WkR@5qopEC~FOclx!_-XlP7s&J`ox3IB|ih#S1 zb9%0INH@~l5wSd85j)x$%nv!Gtj#*P#8dVmZdw#vzMwoSQMrNR+IL0$M>1_dls=@X zhP?mSmR>;CoD0HFYc`hM3#+gUT?1Cpf%oTz-T>yZa9Gs2w-QjiMwz7e?xRhfm1+0M9bSyfsAxb?fW+*PC+knjqfnX z7a9XO%syo|^2kXZ4?QH+l6K&qA$s>)2M1>RkcfaQ2zxf)0z(>U%nNRk(5B1ZP-N4Om1r2$f*`!nf)@=hLykxZr|SSyiOhQ#wOdio{ObM%vJ~m@em! z@^UOg($Yiy!(W4^B%YRhCS(3Zhn{;cez<7=a>Lu}h1DD7llgyUlKxB!rT$t!k0VX~ z+}Hr6dmAR`QU6reEK5Has#;!n`F({B#rpcE_=PLCL1+1Tqaawsq9^eeF4|Bb^s+Ly ztxnfo%0OJ}Ei$rA(4d?@R zup<74(eES;(Gt53NPM`gUxu_N6>gBJ1?X8)z6Vg zL>Z^!ORbmdAHAkY%qIM@9W#e3A2>NCI6e`0O9C2h4drm%vBGZEKXxJhoXXTqNJ&1U z+!~yFuj1DZ(DQO9(+j;TmE?tP=t=(KTx0yXG1*e;w2&BR|3c+ z#m&cjiDO<#YQ)Aw7gyQMv0>U#_Kaj4+!!x?Wls>t!_aWrg=K`_0P#U%mnO=~_wwyB zfgc$<*Y&kp9o*4A`FD#r^V}&m_IQT$EtMQ-s_S#|(yc_r^Zo18##>2u@<xz5ZDYOrXuB*G{5;cNE1vuTK#LU7oOXvQ3) z1Wm!ehvGMl*Mui6?pV<$ZIj<31H`Qd`RdQ0s&T6{9i5u~(p!<*CpSAeQ*Qhiyns#= z;>WSu{U4XC?Sc#5%j%W1Avs%Z!|P8gAKN$Gv#L&WiCVrTOsMRf=53Uz`r7lvMR07y zTk45o7@q6Ogz#+UC`1Ixnv|-ab9-cpD& z$q((;>|_Kq6bR5WTwaR9R_>FvD-%>l$F-+jyn+Fzp>~nK3478GX?vl6^CojxH0p}nK%im8}AE^l*GTFv4mOKq#lh;33&?(dmIJLk}!^8 z87<7ib;t_;3ShERC+K#Xd*&~Q_i*rNADDtx)Q;{fPb=+*B8h0WYg`<$D})MxB0%x{ z#lKhXw?tS?%!6m>KZ%*Tp4)^gtGj@R--!09<9hFS>n2drMFWF8zh1hb0?x;!uXq6a zB9L`@-Rg;Z|>Ik0+r8ie^<@0!t>dn(sxMU?ju=9P&g1riP z>5n4O=Jr<94ITbz*WB(Dlvx7C_8U-&opVr`4TqP0s%uuC?A_R}v^hb20v!6vC#K#9 zoPqo5?C~7!FRFQ%U!yA49k9rpE~mA47!HhPimr;UbZ)IpQkHohlQ>R)Cwa#z#my+|D-9=!hnN`Ha?_i7AnNkWiF{(L zo27L{vfuBO9?Vn7>eU@~PBE=Vty^DRq?%l|x(+O>{v&AyyvpI<^h2H39rxE z95`xvNF}~zk@@ZSx%s}2?HnI_>r!a^-$>H^;Tm^Z)>_E{Hd%1 zwnp?yf<|TBclN-7g=rN`WrKH zDj;4V=R1EdL<~xd781;+dL5#?F^#eZ$p1*t9FvWz_w61ah0b*4x*FYAXM{_?9Ji4e z%Kj@B@=WY_+?BNPD(O<#!60K^ueH@*GtD{netn_%=dCYi0w^a+Y06m6bLub`<^HJF zV*H!YjgsqlHwH~7r~bB|Ulfs8mlAuojAlOt#?_W{*2u))YcbhJ8ug9I2ZB;>m0-N? zIxAILtJbegz9efow10=GobQ{=!G(}je+hh>5Sfe&VO|-tZ4K4Vn2`@Bbg#%C0e<_r zPHqDyFOKnuL-*AytBJ6w-a7LH@-dnv3a+p4YsjR#DQo#hoZ;&}z{tab& zMQMW#xjeR`+r2akQ8{jt(g3rFsK4%T> z4rTt2#2vA>=yXps+8U9kJE-xd`}T?xLXL6g|D&^42thL(zSp~(rWqSEmx|Bx z3{ut)X+^%BMLk=iRpCXb4|IzA%{c&^0WR63Q<*eXY>MsodiSC04fwl&FUPLZ5imEi zS??}3AW@1QWx^kEmeWO#kMA{*Uac;7CGzL@yz3}$OLhG)X?+h~_r%^u-``nzuQ+p+ zE4ufRJTu-PhzpKUWp!)Y?h1zUl~$Kqx?V;Vg|e=w3t%Wes=V>IGN02=XKDq&(q?z@ zF0Z0rL|~YskZ0qJ3vNd|T2+>i(&L>gm3y4VO3eDlopb^{^@YUYHmpcS_DZZsVkyCT z79|RUD1X~i@QdQIark+6MX1l@3-)r}QMuE?%-VmL zI=L|ZP3!!s#eN2PbTfKHE(&5eW_v65S=@nl*KIJS18jqX_gym&Tx$HD%a>_|SGAAB z%Q_B94)ZxumlsDaB2NbJN#K@mR|x51r{D*iftYLm5Ej>^tuF=^5TYQE>5-w3A70GN zd~s16oHs0Q$@>WE-NHM_{`qOLa6rj?gpz9T#;93$h(H4nMXQBGjNLjQAYgB1ij%h2 zbYDMgpB9;U3Q%mex)p}FOLCd$s-lJ1T? zD0UPd+7OLIAAW~2}XVeh%$ZbrWvPH?X35H$qeD;+J&y14Cj0);yYK1Zdan3l;dhZ4~VALri8mJXV zmL*{5nP=gt3%0ulUblBVZ?M0EHcS%~Ey=}(*6nSs; zw_UE>(wddK>%sODcD|`Q_U5V2Fu6G6lmJ!|_v}s9fkL>$#!>8&5keu9e3Z6niM*z)Vr^~j z-Jp|lOB8j6n7^lfwOo2sPi0c0eJHJKwqG3aeh_Woh_X6bwNFu5&~}nwIiU{UkeUIE zF9)QTn3adm>V-GOh`V)>V)97&j!6_-p(}{K6t~t>Z9Cr=5FK5uinat$d^BTa@0z`q zi93cmFb`VB*P%i}pN|Q>5w=LQY9xpW=B-Iu_ z5xgmXy1eYI8con3I>53%^e+PI)*QCT?>V99}RgNo7K+>~& zSZh^02N#1%H6`+e>l_RvxoSIDC=}bV0g0%8%$h&qe`|w!tHEHHRaG)Jt-X9%I?nBjBnxh7c9qYR-r~bTMP=kAh zA~Ko+LSj<-ma{hew9L3n1-(H}7ud+XX}8UFMFeq<4Mz zb*-Fpi^MG&a~pD=kNiB&;SkUT*e#lP2h1%MetiD3iH2m-J+LPlN%4oZse-l{SO}X^ zk2PTM61c-=WJ8>^H&?2TA8R#W%Z`q%`X5JE9oE$M@P`Pflt|}LP?VICW++l3C7n}2 zY9P`h2O`}fpdj51GPzJ(~y>aIefh^|0Gu%wOwpat*<|V*5 z=dsVepLu_Jz9)tG>CUrd1JaSBuIC@T1_IYd*xUSs3((HAm}YzjQ1EcmpB4P&v*1zM|*fp>AVZB`JxXREHvn&>ecAAE0 z^2b92FxqB~LY3V_fH2IwGvd@ZQD#2%w^s+I=km(wq5c>i(QRxXNr-N(?Xe zV&-7A7H0px0p|JK`mv(w;Zw4c?Avuq^gZ6hC)4eZw>s{g=+O9UcBY?1OE4klR=8Trq?f} z>`Gw^)fWv|S9`tBynPA8yIC*i>I{B0eRXz|NZ0N_n(_i6%S}x`k~P+sIgH1q2z-sL zzosQPDPIDdN{qZ;Io@0gr$gXHY3KIuH3$6bPj%q1(lDWq#(_hnPpjH4Xr@lxLIsA$mYp8>!`EPcb3tQ`FBY!kM+`(p0mhb z!)$se9wN*lljOmQ!bO%6mXf)C18p`CT5Q0r|13zZovP55nQEiVf>PNAAnND@8c} z-FAZQ!d=?c8vq3Gcsl z?$01Mx|iD&;ofRuG37`_OSX-47LrP9@S(c+Wtuw-B2G>n2&QQef~+P6%BJ0P zR$f#2Y0P)n?~GpKwcaxO=yz66 zcpP?X^&&Y|B-$g{I&$JFYzdkNNWX4I&(KUt^-)`<=4I{qy@h1>GGzcqWASiCNL}DV z{16&hZtGr1;M_8eoo1!?6`~H)m8ElckHLemy%kDa8`BWfgK^GV*i>xep6dNRHnb4 z8W`dBSl0E*gzV)(vM+V&sROA(&|R` z{+tdLoNf|2A^wQV07l%1CNlXemzsvGJgn8#z^O3&3mj@Ba*I)5V3$8?u9E<4KAO64dKFOG zJn@_#xKn6Di8N8VZmbga8U&o$d=a78ReM+YLOmW6Fw?4JX7%Z& zUU|p~c||{tw1?i+rNB{~E2y_n<38l8@o9!LwjW)WecNT#g<7@j_d@Q%KDfZcXqgIY zbLXZaD|V5O1H2dQ$#asAtK%Bvj1+K;UpIlT^)8WzR)UozV4o2umKK)Qn7TivLV@gr zmrY?hr|t`Iaow-13bS9Nc@~XN2Y}e%T&MoRtx5N+B?ny9ky(A(vmfB4ut~&Xy$X0J zb>8tz`PUwTXBgbqkJ3kn_x#dX8viWGg*YOELT?i%%@VkvUE`6`J30Qe#rGlciO@Ne ziAkRDJ;jdhyS?`LOxZLf3dHAX|38j7cpw|^ex=RDygJ_-Hnz; zZR%IZh}_EbG5M*ug+HWOXJ(e&Rj$yvx0>%__;k)3l_qGSActv+Eylk{FW!J_MfO93 zv%X|Ll4ijWXZ{D;I~D5KYq)Y)()?G{nRTzHqubT9a=ZFB!1m9lTnk*5Qqx^1kwW$` z@ijex&VR=1A7AcU4bc9pC9(i2%Edr>v{QD?ns-!rFahCXc9vBgzTZ*;nu059PAjj5 zw%~s9fi1txpAZDsIM%cNy(wsQn6Udfd5UUF0FT6`66jOUrayIG$#ojNJ)vHsN+sk} zMAPCQdGBZOh>GFw^}F_M;%xr75JIAe-@EwNI7?q%byd7C1)3@$>2$z#*>+t!4q1Rw z1@U!6ZH^Noff@$p7>Diq=YzBbRe9u1t8lxxgicdpCloXfDFJ{%JYgbrQj*#d`=uX zIby=HJ$+hsr#EoBFF@ zKYqhhJCN{f`Cf|`*ysuhNk%AlX$R4t6n%V8`$-o2_;M7=4arOfrX%U^V2kQN@`bwo z1&|bqM(c~~%1YoyPHC5vy@zlBQx^C0%Ts<@3{aehPW%)K%A2r7-qZa=vI))ro0hFp ztkMJnA8UXUuO=>D=ka)tk6)*+x^UYq_*a-e>%hL$QgJExx^|Y-kv1EDDNnf?VWfVc zU{X)(GSuO>`Zk=k&le%v`YT9Pn^rf#{{N>%20;%T4f+TEy;9$4F?HpVXC_fxIa=8^ z{0B^z&5^f7?MlPZWXvFo?6>jJ@$NagUVW$kr#D}LHv44zcZq=i&h$78(MjE^dVAsO z)nMF0J6K6)^DK&jaCfDrY3(c}QKuO1N3KSEZG7^i?SG)wmGj9W0a0$I_X@X1|Nl!J z16L|m8AAW6#pb%?p$&13ARjyvNRH_+gS@Z$tJb|zv(lZR^BZLxB?)D7^qnj8w1isC z3SnwYIRpey4(HIz9%c}T%AC!DEaa8&-C%K%Fq@8SiOI^fI8B{X~o})UzHKk zZs4r(sE}cM0zQ7Ef=Od{>hnYPoj4)GJox%Ty^5>sGsU+<@VCC}zEh0myGK_fZA&d1 ztj0X^%Pk}yI9r-JUSF5?uv6zH7-V)N^PTyk7I@3zMO}TGbVd{V9*fuRxnX(3jiVg& zT~NZKVFgF~w<^vT7IqCKg~T3n&+Ib@2+mUrRrB!oK~51_2(#TfP*R5K&dr6h1`SZ( z9SN2#Slo;YG|Mwhf|uVSLhCq}kGqG9UQMWtPI1m;k%T zysm2Py{?43r&e-&&0ybq*Ml@Vn_^4g@)`E@Pb0Q3(aDDQJKb?+6X=uxTW^dFJg52} zs4@OyN`EOz!$m@m5E)Adl9sMGZ9{ryytZ}}84V8U=bdLR9CrR#kM-Q#;6XJ@A2?b2 z4Df5-&8I==47GYBr-T(Lzk7;=Hi&|RWKU)o@sQKh)yy4v)|5q3h1F22!h-sw) z6cLnR$3_oU^k-XDJPWr=Tbknq;<8SLD#IAx%cOZVBwqzzHLNKxYvVJp9X)}ZUnS;+ zP8DP|$}^1Nydmd-UtFQX@zFs24?DiY0;>}-d7>FBM%4TynJjDm&LlXVSclNc`ehgH z@4PA!%0)M!$iuE#bzYZH={xr#yr>LWBd8 z2M8?K|EdbbfvBN^b@Gj&-QK4=#tBcl2005i`H7|8ZnPAPyYB;%3X8}l+Y&g0j$pFJ zsfsPx@Klwh_}Y#L4}lDZr5HO8Rl_^GpJ{Y6Z&ksr(-nCZ36l6pbO)2U1&g!r$6V)} zGu0I-eu|DU#bDT}Iq?nz+c$z2SH*{9JD?$GaLiV7W#Yd~A&TMceQ3B86E&5uRY9)Y zqUlFkJGpzpLONC%u4a=tvVR^%#G4m(P+kOIzw`fucgQ1n&yi z)ExFe;?7Y6H8}FP`Fr-bdh#rmaCz=Acau!;b#34y^T0t_yPihEJ`6+C{8_!AQPH!a z{=9EBFS{yTksNCN-;$sKA9wDCoE~PxebefplOqkHm}i_Ij`$w_9;XlNW`hI~@59Fy zUgDmWV4rlPPuN82VpR0wJg38$;*E(c4U}~BviUvw_tfA=vw>`8VshEcgL-q zy}*a8u8`uFPw)#}#Ah?1@u37g_H=4Z(<{9THVjvA5RcobKD0eyc~ONtS>*4BNATGd zkKSq%(vWedIryNgkm`KfSO~Z3%?3&rPNdb#FZVxm`m=3IB=Wj-Zd4${-ctorEd388 zQzq8S(WAlpNtMTWYQI~QP&)f9p|fMi+>4$=t)4|OP%dpge%d8RU?ZcF+d?iuqy{<8YTP+hGWZyE3NmBoq>?~q^- z{2cLr8+u-P_Y+>9>;bwLXa<`uH6q`k;M3*){#>d6T}YmlIdsTPCua%j-97KYJD<7( zpEhci-Q5?~KngMIR?B+MX2pmY$_teKaV#!mE#>iu@9s_?u7=nID;MAy3<(qoC=&skZk4#(KS$*+NF)lwX~B)37u`95($_v!-jX;aA-1rtXznq-^l z!Qy4}uoku@OtV-%jiMeKf+IP5>|3u7470*skdh%e+?#7&pYM^|AjRhH^zd!`N6ODS z!U9IneRD*(nSp?}T@`y-h`S$GtgVpI%&%vHk8C$bc@AY1V4{+0)4VP7@@CCp>4lDG zXAU{=aJ3jKGt^)1KNx+mVEj^gqOr%qdNnR1E{mzQ=r3NaH$s9kI^)q&odCmE_~2*k zi^US?nu{68$%+=+5!EV1T@*ynkz6{DcX5`4GH<7iqL!_;1~<*}$qX-C9jgbMg8sWt ztkSdb@jBS>9uY1W7t`!}oYWUjFvYk_p~L0D_w!~*xV)N++xaK?2?*g-og-z-KgY_s zs9cu%ptj8Zoa^3EH^ z>Z8-6o#il0wN<9u?K0T!9_EMC!<-ePbwx=|*@0*~{wat@Q}&%^!?_BK2ovxS&nW|Z zMPng2zs`ns`c|CrSzTcg4DCIeA})w>Fa5EWCK-wTY7CMdC~IJ|i?|7QU#oU!K}PjC!%(8xIClayA#L*%%nUbw)AV1505z)f1G>h~ zr3eP0s6bZLEN-Lz#pXxMB|O!yXXX3qbL*{iT&>5hBykwu3G*w7l>`2@O+OTGqnOgm z&CGVaYyWOf35^asOkoH!{K_kKS0+A<+FD?1th=ikzr5Q6z57u*DNNH{{xX* zIyS%b)lL@bi!HQ}>}j|wC_239!%QD3pKNect?FvA5{|~2_2TCHtXOO3PCM>dwJMS% zbrK&?xa`^3Z@0{)3gY_p$I}!L?S+61WDDeH%hmDJ(fy2d4ZxUStJt9|md` zXC>ueA-u;XgO1!!dG`wbI{Qx!KqP(5@hfN)@WkYjs0Z?o8iG#z;Qo9?f3?cRC0Ahr znyi&twdzJt<^s-XD%FKtIokGdBLRcHz7 zTpap>sIvt5Xy>3SDAn=FdG=?Q0Lm974=KSPYt~_xQoEO!hNeuvZb0k1U5ZCK^OHUx z_51EoJrKNUTe&NaPwfK?c{;I3a72pHki2Cv-0j~<8IX3ilhhiG@L^uK|32|yb069; zZuOA0v$DTSR;Z(g4%?zpi=z@*Ym|Rd?ik2wH+jI_`0U)*s|aCT_;+meBDDlotoqU& zJxfd8dUFJGhy1OS`G%Bb@C;aIYA?U#SK6%)q8F~^!K*_D z4wOIBK)ty5P?tR-I{;@2A-wZ;d@I}5&Xc-6J3GM=wt23^rpAbZdHbQBrgb-7^V|yM z2j7Joo3!GS9P;t0J^MN4_KI}Y7;06NjAXik@S*yIhgV}mn6)B9{@1%hAwIWU(;9LB zzY8v`rMSBYuG}lmIN{JE>4Qe^U&Y zf}oENSX*Ju3cFl7Yj7yo_L_5VZ*j;Ou{FqKZy9!YVbbq04s&jQ@FHgv1YepDKmFmU zL+Q_fqaKUR!54Kgvu)ItZ7=g1&Yl3sZpmNNZM13s(D=RUA9;UTGL@68YBBK<=PUGq zqotj$Xc0zwBToRuN1YDHGtXJ(JGvMY-)3S4_j%D$<%QNpcxql8XwLsZG&t`f@%t-c8!=$l80 zbj~Y^AgBDz^MS511=~&SSuH}!M0e$AiQ}`H#qy`L&kSbGP&xt!Enu@9f;ezrTHR^D zYay`Xy;dA`Krbx2>94ky8QL>Q)Vn#A-Vt>huGh;p&vrTP(u#kvr8Ni-E0@>z#x+~= z{nn?YGr_kLk9*ieo7y~_d5oGmA@oDaTUS=k5iyD zL`JJ4CqEvtIqN(Rc+mS%2ZfQ>a8RWEt}}M)H{&?IegS=wg`8_zE5JeH`eJi;pUE2B zh5H_KJ*mu6LO#QFr;z*+CFi>x`)A$wxsSIe7Gueban5%ms8!?CqPUKg{FZn--3v36 zpE!x^f!7DVU4PdO8UDSlOF@Y>2SnP`o-T2E+h#A91!g4vKAe?TA&)GDot^tWOY{sp z_#M%eH~ukc@fT=>Rny2e$JrToV_eT95DYgwXjQ=6YGubzi&)hu`=PfBe4O_lnERNI zP!*Efy!RrkrJWygj4H-cbak-e&pXq!6LG2LY{@Alxeg6AorQ(*43jH@NoL9FqigCD zzk-xVe2u^RYvWE&m*QjmMRB#AX{lf2^{bXm;dweZ+gP-@rMUS#yIM=!rqky~M+a{y z@(s5#_{0wlX1pH$29psZd^ln zT{@@H;j3w)sC_dc4(Y7(rbA1_Y|7>BUzd`%RhNC%U>)C8q@1&eez-YtAhoZ#w?3;P zRzouKFgIn#;h=q%vFm_`zk{0_h|s$j58i_CKUJXkr>Wwz`J57nD=UI5OQ1l2hR|b1 zQihd9Vdvh{Pky>LMP>q?B#R3Nw#B|sm6jk;q{t?e(sxRqmh6!41R_Cwq&HXXI9+w$ za%F?N%B7S~iXY!-d(nLp7mTWOg6hoW@Dx7?0n*3B>PdD;2v6>m>|eO*e`8q-(W8r_ zCQD`&(;)wD5I5`o{xT3bl^Kqe;P^+bcAC-O7kKR^6{bAE_SLT@s z^sw=bAIr|I+062C8RqH*$mD&*+D!YqJ}KO3>5SgE;+|j&t>EIX+O7;bsv=&`XA_c0wG)68F{tT-cg};jDQ0fHR`5b zLaZE_c~urT{YdkswWd*9iuHH3`)OIO{rWM!I3-grK0z6oo7avHdT@kN#=!pLqNGlq z=?6i-_Do4#w4b;I=xiGJ_Y-k>BZ$NQwC{fZsnuJ)dqd(SUjj)=Y49XSkJ`)xlVvp5 zTizp8-_4i_1NyHJvk>kR?&%P^lap+lAx0f-+O}7WwAu)^AZf)FGdNHl1Zt@XfSCEN z(k1rm6ew}TyS|~ISlG1$ncOK#fS5fKDcaS$p{A@uy8~eZwMVt+a9%s=HGoL)vmQ_4 z2wo-1RUp#&f}5|TW|_jDpA>Q2bDgeJGRc&seU%pS-~&?Lcba4S9#z^KTK801qtA;qQ5Y5`y{iLNih5~X3ZlXqym!B=B21V zfT@`9Q^jm{xSG0NA1TOyW9@08^0AL^baC8&@8)Yz!$HSqaU50D8hK+4gni1t@kxmV zaHV9?p)Zjy5uGjYGs2LBjd52|D0V6B;)$__*YoLjA-8 z;1YJ$z9soV5nJl$MzQYb>4fzK92%f0tB`F?!>#NaKeONlGrBi-0nB$VU?;;Oz73>d zteF~B+-Mm;7m{+zdHa59x07sRzxVsKYR zCY!88*Y#AUzz{?uQ>1%i6+nx>ktTNTZtLqQF+I+W0>%2Qv2eP{&g4E2b5A-QmCh#p zM<}-Z%jtSJ6$Dy;>)I>d$7`|n({o4VHILP8j??WZRm&nC>BEo^B}NpFNJ^GR*zT@w z^Rq{9#B0Bbj4lq8?c}nnneQ&xwnC8}5_6!sOa_{QxH+S4oZY^=})H zRt3)VM$}3;iFXtqDzOe^!bl#y5>%PULi2in6AF&lhrTFkbi3Re>=#}eUS^g zRw`bP`K9sns&XjE_buRF4EAazwg0{N%f@4gD8UjFVdK*NrH|$4MNFc3g=41w&L<`V zeb)ZhG>-HX!)~JI>L?0|T_rBdwd*^Y9kg{r_eGqj7HUF*+ypiaV!!o`+!kzy*_G^% z1}p&@${cjY3n|@EUUG?n&BUp8kq)GvTy&%9E6LW4C1o1*@dEY(I~|Qbc<-}GQK@~6 zE4ux@*J|9Jr2EVk#wUPA+7(^F`RlKyeYBr{By>z_-=}Ct^GYYM`!eyp^^AzHlKvPd za~IJ5=Z;fB1!Xztr27VVK%_}sm9TYqJkbKNu#&Tnu1E092t_4pCVmo&O`?;wCi+x< zWxtle95YEVvywy(LW`@!ex>~$Xb>A4(7)M5Lk_EGXuf(*mP6@;H*~Uo(E5Gw)iYTg z;p=L_Jb=Tn%i?&D{r-}nV){DSWgB|KU-r5hnH2*51?XAO&hOsgUVaEPl=G#7mV29d z{Xpc67K~7jw*FXRSR0G^?EbkZ>SF%IbqvCmJ&R!&6QG6$x{y!3_(X(0Q$rx9`|*5` zP$RB}>W!&$fSI9~>8Lr3mp8=mtsaIE?AA1+>*pkQZ?>8oJfyz&qVx3!V~%^YX6GwR zyKBG(IjZjND^6z3#%81OH;Lk;m&R#-EK%DD<_?#RD%S5D*cKK#Z`{g@H6SxInr7*_WS87vo6REYPiq(ucp@N!s)&BOmC&v_tYDc>@DtnSsP*P zQwiMMu3x4x0hsde+!Fai6GQEQ#$J!h*Cl!CG|}%EUW%e{xvK#*0+l9l_D99RB{*2u zGbo^vfmw0Ryi-dzo&GnSHS)Y;BvO?9clzpD54+fk^=p{2mO3;a<7IfYS zdb$uXjs`qrDE*G##Q%ZtAcREbZQvJvA2@&6SMV+X11EC9)n3GD%}X7@QI`6;p<*ly z!9rb02{dd5>ohtpTY~;HQHQH8gePTfUVe{72#?d4a*E9rx073|3nn#ff(%wkcSn8O zGgthZIDXbEZp&}fh2$n|vRIMGTeoSM9pt{LE2lW_#vJ1LjQ8_$;EpcARx}n&{EQMS$tMD`(sBsbMmN;8&~A?W~Ms$p3f?yrjVY1jA@j zED6&P?e_>&B0L7ZJDi}_0Bpf^BB5-G5+?qtVA>64U-HmGyzQC_lAd~}>dDuC^B{mB z(1o475+LQux>Nh~X;3L8(@WBrJ3U5F$$X_;Pk2 z@I9-%J^jm0!C+|$0todSuGzi!$FboCJfGsvTyVS=ao=Yp-U2OpyQ>#(+h;vTVXxKS zaS25ITURrgq1G6_XTsH!c?~=9JNu4;IO&9`L|g=d;E~>3q8a*XYbTNyQB0P?2U^xw zhH=Q|-EHlvQUuj3`mV;h!w?}S zqTK|E4Y<9o>1Dgs{4Cxtw=%L|XWM6u6RhKNc;MfGeDTJZmb0$8W8_85LBEAjY;R%K z8k7c1rBnE4o5&r<`k}EtYGtqABy%QSGzZf4YH#4Icxi4;8%!_HL-xxAu01Pp4ORcD zLY!(c<)upj`CsLc#p#^Gie^vbERB_>L3gHi1 zBz28X31&?TtSN$-Wky?<|NXl?-_90B$;l)aT^KdAqaOC^g>i`N&-DgI&df+Z2j@~p z*@p!`chOm_d=Y|sr!u-ao*yeV7J8kLXl?(=ls?C{st5_K7ncY+eCe{3#@ifbmPK(+d;1cjw?t>0PM=dZraV$=Eeu3_ zr~5fU8Xn~##B>EDEg-Y{e_6njx|8hRY|-fyre6y`c7Y&;d0$Wt?J(MQ9gOivE;+~o z$mM+;Wf%CbuW^LGLy5V)8++N6maWz!FiU@F_ohN;^x*qReoOOk5Z3xpQ^ZLY-F7`w zAj8#rJQUi39bXVUVK-e}DK=X|4VTm{RsNB$6%!iyor5^FSMeaS<0v8mAHtK)5Ve-? zkGqy7CY14NmhB51D3!jOqdNH-u#odVVRSyf2AP8V|XtuyeNVp`Y8rmz? zt{{WWxM5P{ZOYg}cO;efy>ai&>LZl(gXXeVP2F>}-LD&ZV@3K=+VM2;SmG=}D|dOf zx!{{xH;U|fc#%`?`jJk`hUQBn?ib-?J7+=5ve=DC?4}mBx3EkkOp-RTIrR(i;mS@* zzs0owU(Y;iSE^r&Hy)Ve@#k>*I6SGw=XEcO1A4>wR+2TLH!k6qB46y9@WHFQI+SXh z1($z!erQzKOalots#4FfLtEkhd_hBX^9OZcG6yKdUKMi5)&L(~ZfdV6*f1yGas{L$ zPvOXFGdd)08MZb>42!T-rgWP;(z(-(re$<6VoS+DJ4=wxIt9qKEFbi{q2ay4P4+T`S>k<61NRtZc{>*$)-p z@&kTs_`LoB@ih2}X>K$A?S;ehtr8t+6a#e%^o?>n(V!=Et68ceyXW9iN zcdP$_1}m!d|(cJ6z;jQVKzGVFa9`q|I9 zY~P};CFWkP`&pLwQ0%78wCAXKmzif}2U;U`eo>WEThl~+XSwgFls|qk z6cl2a8th4_1qL>k_^O;`7#Hs}fe-DCWsX3ykBTB&s_2JH7YF8~dYvLebK>NDEN}h~ z)TRU)gMFU!44~Om!T!N5r(zW3EL^B8;YsMMkW_Qx=mc{3R{mE3SbF_;$&pMaqa*EV z+6>pPu1cI0{c%LmEvaUyu6=fu@b1h94JiTl6xh3$X{M38C8rwud95>cZOJ-`>-%YP z4NmBhzSeWhd@!V10!)KX*R97|C86zGG6R^vta}-JT9yVa}CqRF-3CKNS2vcnL9kIPdSTEhDt06io~DBkz`Yv zodTo^J>C&|2TswQ$<;jNv4q(7_O%N;N%x}+P*lEWR?&MhUj04a&S7~|`a`U-Ol46| zAQv7{zMJ{%3euBd{-OgnEEyk>H;E)E*!~+6A zL#)N6YKSwgp+~lBS4<<<@|TIdSIJGL`3Y8oG6~`0sNXToi{hSuU?*n{8jf1-!06nG z<)Wn`$l()?cIUZxv7;3uRzjI;&-EoU^Texf!1=zDed9YwbzLx7p_QjD#fQ9}KLz^o zxUu4Rck^EjSby0i0xB?VJ}ty&T98>ZBZ2u7>pjKW5J@}u&bZYKL1-01p@O6DzB}mR zN%6&lnoj6#)07eBs^A-2x!3Z$cih*glB15cw9^)yTaIb{VL=lxvUG zlfyjMe?!}(WFnODNeuh$XyJxDc&%wE1y+e@3v{fyEV4ImZq+pO=u?l>ID zETsL>q`m3rdlu|n3KQL4W=NaX#%8R1IXK~Kf!={Gn3W&3(hBU^e|%5rmL34F{H*Ch zY3cvGUQ5#i7awt;wV7J=mxa4oR^g;tK50RP)xWJ&9!CzuQaV_q1efC7yHSCO02O<8 zE6t_nYUM7xNXdI<14u}KP@8Szg3fRAD9+nQB`3{sJqFGE$FW6?uN5>zBDG*47d8Kdm4n1!KH54!rh$xgK;IG)t|+kU%~lo6hYRRS#8BVZ?LEH)+?t+; z^xG?_BjK!f4o42dpCB_sIB9OK9R9eHHChgW7EZgYXxFSg7NC>?_w&xBaH`}K=OgMD zof~(zQ=yJviO_cs&AnNEOZxQ$QsP`XE&0%u89BlknD{W?5$6XxIyZe!TiJT_MsLET zS)VWrs8fmlBvE1j2r{r>2a=`;6CkH2TlCqb)zZZo9U#Ay?#$ms>PW9Q0f1IfrmQ_R z;?_Jj8h0zCEV1%uKqnT>4~&pbr*B6VCYH@o`>qSxyRj+m@KswTN8-css&@J7tx?~@ z?kZY5MHi7AU$rU{>3dT)v#vs@Bfid0=$^~3an^?J{!e=C_DhTjpTm>m88iceD z;!Gg&5-x^bgv--FlEs3+)t6Dh3F}9)vqQnnSrs6qflof1{M6wyhJ9Os$z&ko z;-4IwH6=lO1^4@Ce7ynKX3pZ;k1e5OoFinQa012(RaJ7$Bv)vj($f?7B;5+w5~JY8 zEqY1}Jqg9S#$}$6P?g1Z&!uJDJ}=2}c7x=m_bB1qJ2ISFSHCLeY3B(a+e*+b8dNOL_)qR6T?5V;|Yk~tsv{wU#Z(=Or; zczk12onAgup(IL7ZLTQ$My1+v>7I+uTtzmI3@^0Gnt12Om#Mg?kj`=*KtB>a(A+o)ET38WqEj@_>9ULj~z4^1+uAH~v4T>$WuG z+b0TSd@0@^`{$Q~I3iTV2X@DO)9+A_QgjqZKY1(N-|k=})OyBuoK5cYQTw^{NlCKU zjm-Qr)&~Vfzk!+PN!jk%D!Nb7wCxTuLl*5ggq61U2!A{C|!sO{;s<9$|9b1~`^dYG*A9nF)J3fpygDiMx z2;bM5>WsAJ`MFk{J-RJ1iTAm31oGsvkj#5>erI9kKJv!JrVEui2VILppcA4jF~VQ+ zQ@F^EjZG9Cxy(~DRup^f`Wji=FGz=g@ZlUV@5uS zB>@l8Rw=Ku>Ark)WT(t#g_n_8%r=_>GW6SOredLL%qNSXJe;o6o)ud}`H&xytc zH&eCOnY6nn1$%^`Qy))YE%v>qy3bA9;jGpyyy=d*nDCUEzQxg!dArmNjZNOUSma#r z@Kfm>*U=|^8umdeT2`9UU*raP(KN0NbxzOAhMk?hO5`Xf++G@W_11Sd=Q6Qe4;iC< z^`~i?I9u5BVDZN4XBi&yntyX=q|-v451+NZriu~!w3yZ?dE07ba9H%CwEX;6lR;M) zuY+JLlH_L+(a%@~R@u|=;K4!=DPP0f&uz_W&XOlCPNSZb-&yXdzo%A1pRc&>lclr2 z@XcJDVVXbl&KH{f^Q>YFwOl_Vu_X7eA@!P(ct#GR(KvgnB?@u)_8ZS_N0D9j>|Qpq z@yZ}uiranQ(n#VQWmBv9uzWOyBeD1S2iKxoHdh9FLG7fX(iO=o%If2J&$tf6Z{)qw z8Sy$^h}w}TiqZp7A5(c(3C|psJO48b(^b;_?YYNapN^@E!@awQ)n;Jo)2UN=<>r74 z)q9lw`Xc-+c`DuDx~!EdkH7mY5O=4NR({8b6iBsUylC?Bfc+q_mTHtfh+cZLX)vcu z63VXuhJj-PlL#iWC$TPPo!Il_GIBQKy^GS?QukO?awH@p&|#|?dREtaP{Wm)zjLXW zjM1#%F`W9gnqYyV-Aua@W_=UKl?S^(==YQr41e8Ld@w0#F7P~{aAn(ftXlH>{_us% z$6THVgJM;jL98VbRd=nn*hYy}?$qsxTxBrMf5|hY+_APz-})tLWC=YW@zLk#r5A4+ z+_&dbo~87iVZvgoH0lAFR7Zl9zlXJkKlb=egtiuv@0y$_!+U zs~hcKjz_gb^kk{qD@rZxnZBC9$8}qqXYS1sJDtup0ulzA5b*(V59z^OU?WqjUA{V`h$vu3bg)MDlM z$f=&a`FICa7cm_kD#vOi;XSx`<|}q^9y(Lv>z=q^uLz{vbyPD_Z&0nuY{}Z z8a(SPUn(AbP+4t_q6eFq``A5&tM#nmEAwCN=ra=@-ITrl^`?)a z78E@%C*_5#J<;kX?wClAET)2#+BLbBZNXMczw*Hc`O!|Ls(+ZB+XvM7p6y!3pvGD- z#&`q{++Aaef3VP{dbV@4A%4?Z`Rm-A9Q${k;03b6XYKSiZhxnR$7b14c8J zwu?(Ka}I%5_dL9pMX6FK^v$c5H&tp|fa`;Wld&O>XRR)IYBZ7p$WV#e!(f+d3;Wl= zbS4Y_N_CSJ1f~8yMXpv5Z+$9I+oIw&GI{V-@L=Gy__RXvH&GZHAC+n}Ez}Ms=wszW zUg5avvbSK0p#fw&;aaZ*q)7Kt7uN3J9x3&~XnV|z!~I__-@;!MnW|3#q25e6=xb|q z&p9AGKFP7^f0K5!aUm)ggYKk|?q{6RM91I5Z*^ArznM9Kg7C23ZN<96UAEJvUzWCF z8=BI3)9lfzXd?&lfovM?H!=S;Df3?99w7Vtu~nT_@k z&E`ya;`f0^jYsmW7w_K-*!5n9CE`T7Q7ciBFn2U9hyTO2Nr`Mk;`^W|qa|4apZXOTJhrlS#RkD2YGzh<6Vj{Rl%99#5g(cgZrt=A1o zawAv1k)7FFoW=NERUk`J7@w7ohYaA(qx_$HV%IQ68I{XAW!r480=_P93t?=A%g?`v z9$(tbk%iXht;Led?aNLLt7A7qk=JtC*o{!0!L#Bj;?kp0>IRJ7`sZ^l?*a#Nsi+En z#?>tH@ejFhF+h3I8>^_Gx~5*6Hmrw3WPFP8US>Cm%+50PI8kM;8qCFajz4vAq8*TY2Nw;VlcklFA^NXn_ksA`9FbishJ}n};x0 z2)0tJZ6AnG&wi6~wQA20PPJoD&$4T%OU&Fp=ivXgnRe(2W$;%bc1{Gc?I_;wn6Sax zSa%v(J-}VZ6L=8VAEPcC=4M))!`;$wl#~sX^m}~;$N6AMKWa@P6L=4|w!|hv(r=fq zQ;L`BQ3M(U!0+4YY-TD?w!ge-mOsiSdpKtEqN$wykS@a*%>k(JAYq;eFubEHlQ-T3 zJ961qCTIC9)Y~`pk$wIzgj685exzbV*eK{h^%U`u3H}PB_GSP5RN%v9^958*+WhnjwMMUd|LVSW?S`+plzh);4Lk`>W zC~GtcZ8D+Pi(^co|4K2Mwl5(>ug-NFuYnx~g48Dn0&DE%>FMK4TMznFXV%S|!Ya@9 zpWI+-RL_OC{#cBIXVd6tOc31P6)O9b+xs5&xKO~Odne${D{pQMGiAB@;}*qtsLw@j^tv)G(K(cqqWq-)!5i( zWx<;-o^zH_bbHmOUNZNvABLh*$|@YrpDw|DH^$b1zsa3U^6JHgl;c6J>tp30CYfZ_ z$*D4Y{Qog^)?rQk|N9?}NJy82f`F9LA*pY=yFm$Iz(AxMM7mo*S{U8kozm&((IBuP zF<|ii9Y5dt{lTt_bFRfX+qJ#U{k-qT4aZHb_IlORh0zW%Fq*fWc9IYSfY6lw1=vUm zs%y_tmbJsLwO~R{VY~!uO*~q}!^%I-PXH67$MD1DD#zL-trpe17PLDbX7SwI z>wFA1___y3>Y->AM05|_-)G2ST=Mgup-dMlSX|-LB*6rn%+(|W?8nUb9%*o#9hQcC z_mTudC7K3h<_*p_JM3cZW)w!IhY6{Pa>?EoVciJVl8=ogtW?qZS<(I%r^ zlzzN(C$Ic8d|iOC>!43qV&e=XV$1AXi@v1npu03d$BPQo;`UJB6NzVV(Y-stiHZX$ zEacijQ@mPxhvtW<#Z61rIB%8WJ`OC4{&lP-1aV^Z=#~b9U0d_uMubPxgGlq7pOGab zXR*)M8`@fLWD=H0^{z8s2fvyZd7AFKY4ONUazTpbM`qD=e6DsAl5#TFp|RoSeH=~Z zuk8~I+ZRET|MayzRXFd8PTSp!s`!u76U2q~vm}?inBKKD z``0aH0uIT*=T%&!|5Z5hm)(q)@`+G47Ao0zUfAqNKQrcuYP|w2e0ze^QpV>#R}f>m zzX0VhkhvJUwNh>Z@WkvNND%W=a1wGuRajMq4RfT4)*R!a6G6g1k<2^fgCADREllj0 z2&I_3oZ;3^wg@Ry*`ogg?MV}u&=ia%wMsZ2XPhZS_Bp+`En_Vr(G8Xyc+_?=1-9o zY5ev+p}XG%hMxbF_9x&NIh6ys(Md;L+% z@pCnQIn$hfAUL|s?Ki{gZwg>*T*CY6_s@)xR3gtpz2Dvym$#IgjV>rLrhY!>Y1>?u zOs1K+KZ#sdv@Y3?^d-`s#FbGhe4y%q;}7o4YCTX%%VzXh^oWzLR@G*TrP>Ejq1xjf zzSBij=n!B{!-HP_AB)sL^#2Ew;;?B;4p$0S=sLFSxSdLJVAjXEF3;O0D3p|ATfe_9 z86!;+W2yuhs6!9+b|$?p;FUwr{LN&&9U3$dp3DdkIu$EBoA>8jwUUl3Vc>VkNg;9y z`UJY5#4&x8KUoXz(*qD@KLsw3Y7f7L&{>@B216@);w3Y)T zW@lugE@Jrcp_D8oKdM~ws^yf&a}>`Qw{UU05@Vdd+52C)Y>41@pSfmi%bQdSek4-k8_LJk5sYyaN722!#z|C^gN{2QL7 z0fdS?TxL-T#;#OmZS~g*t(4EPLIBs4#^1dl)u2t{O976Rp2M5j=Q%%ImvsjfpI)4q zf%Nspu}&t8Ws|35wKx-ov6$mHXI~zOUkZYDnHgo6@7$o@Mu*l{wQv5(!C(qCj=(uS zyv*C@dY$P6&A=|I;g zG5>OJr4I5QM_z}jX+qa2g+P*&&BP?TI73&Gx4?v7=~W5`1oT$4nFO z|8Dn)!%>X$B*pmrs;(c*dDQ{Dg!il5N|#Rqr0ht?x%QP>?5xl`eS1yDkPjE7c_`48GCTvwv|TD;)}w z)U`^SYAK~O__P_In{uI(060>EWe#526$FuERpI)(sK`-(tZ(n8y@$MqRj&Y3-OGyn zw#&<7^&*;)DfJ6bKkeu?{gQL{&EA*pW9eTQ0WIYi!L$+#%b4F3r8EIVL*SO|Bwy1u z4ZY2K?-N)!WD7Yyw83$CtMgg|N-*ehqDDVIbUeCj7ABCyfu&CB%$NlX8P2|^jczst z-VW7OHQZdr3ROmzeEa^SpE=4TdL_EEtoC=J*XAb|W2)Jn59iJN<{bMJM0TeE*nz!r z*S#eVBcJM-E&^kz6K^q^tTDTdBv`g9c{+&li8iU4np97v|NJx<1VEA-zYCE9+a9rq ztNpD)Ffar_1#Yk8Qk$EZuRi80?tK}V!nx0Dl%#GzGyE>|<}W5dx`{npl}@T0$UM0k z|9bv|tf~|$`#}`MVVyG7jtvU1rkU^-J>oAb*ak4#`NuOUy4sHS!3{{ES{p8R%>4w~ z(c!Jk-@iMwqd?SGQP8ueV~=hV9L_(k1}qWlt2l?gvI|cUF=v~bk1sV{k_EG$eE(TW z@>N3G-nFLX9s8k`?g>1tmeCCZ^}rx)fV$JIi^H&L+^#5?#WQAz`qoCVDDL z|H^5K!6lS-(70#bH_!FUQNRQV&EY`_Yp3QLTrbT4nZ+|ZqsP`_xY2k=wnoGCWXzv|+((-*fs|CV&8j_9b9H?{gi zc&#$Wl7wfxbVT`v`~*1de0K_X(Qc@b^D|3L?>@y==^&v(ym&#wYym%tw0-_6jbn>Q zuDdr6GtGRlifI4&T{TfZAp11S(umD;T^wkBb8HfOCyWM$W)dRzP~_QQ8q*5yuNQpF zM!gTQ?*D=qmn4`1Qo0JI`mYjB16Bk3mJq8T+^!I={*PO-j2U}X)xd}0aVkb5y$xfx zy@f?(01LRgZaBhtN;maE3ay!CGUt?Wy45=0fJz_b_Ee1GdDOT0lxh@PKMi^(mLWL7 z4IP|{H2CqS+;&h)UK*5GeW-Fo_WPBC%1z>(dcbQG-D}h1tCI0QRws`Wb(yXr5W4nO zjBG(Tq9C&%JR#Jb?H!w!j>gjFtRJMzPp!3~sq0)q)^44*v!*SMJu=ZcPH|ZvcrSg^ zwFYB63P6Ao79#pcKP^prHNh!ULpv|`qup`&*#h+5TeAnpb-K>Rm;BeERv$?>viFaZ z?QIWw*ioEYXzC3gn^tr;E%i=FG6Weil*iCcTWe zhu0A9dLi5G3{Yp%*h%2`5}2Q57j)hObsy!_x`3@L6^%VRO^sYn8d;w`M676+4M?;DHp4qaH05x8>A&1B*5r z6bUUCxaw(XkFZPUe#QlUg~pcYMnv~!mGtASIRRVTR`;om=>F^8kxQnQeMFT(e-0jk z@YCq#@rks`99k02BhMAlNb6|n-7v~*>&_;3H|F>A3E#DxivLzLY1LXU{EdTcx6y_| zWZIfX-KmW{76U$JTiH(SkAj`WE(?UZz1N^tmtJ!&8Y^X9db4!KT*1>7yy+b2x;$=K zS+oK3qSoOveN8{+#20L?0DNq57*M4Z4c9(+eeu!M$d0kaS=lYFlJzkefwWbH8=;Gi z0J7#r#L3r$V>;6|%YR_sVOEE8kvx2m7B)jSwgx}GEn4~keILEC{sO>CWxM!+{)6Hv zi;3folW}O8&hZUhht5OB&PF};;91-{8>)0WK8jHi@q3-BYYEMQ7bZwvm6`@${AHcA zwN^R*_C;+>y3TH778_}Uc3CT&v`Q2-Ea|Zk?L-V_W@;4AC^x* zG5SA5!FtLN`_6|Q~% zs3D4Lf1oUMraP3InyE8|^3`}Ms-Ke=kFvfAPSR+fl;_GjH~(EJHnXCw_OAc7Xfn6R zUOcrjbuF#a^(unrW7@|**-!juF}QxKxmAAHQmJO#KzR-vR~+6_re(8IrQO=Z9j~cV z1$P;0sCSFZwgQIXuiAr+@pxVZi?@q2XH|e1ips=z4YXw9eU|z>OG}fT7Ms)<#%(6Hm6t_-$WUhU7m1fe$HqWB`m5>tE669TzF3f07T-Xk2C;ZCsD zpzVES5&F%-1y#*V0JE3&m0MT)$G9n#HsZHx&bv;m*YLJAK0lpGKiRB-CYVijRlIke zsh7n7)356!uR!(4JhM5|$vfpHe>*I^{{3N}!0-zTBCogfJfEEzmX+XU4hr+EAzI-U zCV9ob%~!;5v9(@XGVfor&t_EhZ>i}Fa8(+v4i>JX1XSy5a)yBch66aySFAwz)=%mD z+m08lOjgVY*Q=g345Ub~;07s54=n)RmJZDkZJT#rBRD^GII$fRUh)*7g2U!C-%>*U zF(Cfb{b$5L33}8-r?Dd8UV!4=TaibF7UberxR?$z=5DPiD1Ua_3wr&tPw5$R+VLJ8 zXee2;bEb=79j%0TmFx{g|AXj2dZku84S9{Zj>U4ny#1;BR!aA6#-IxoU00SZqOhNl zq8_ObD+pi(iDV#+X2eKGAtvGt``aH&{3h$Ho1dIsc<8buWl3@%iJ*~w5L?84Prw_b zz(HnQIHFH(?gYaAf$d){(d(OayW;MJebZ`b_+|vig0f+F9uu z7wekNH_Vzkoq2QpF%oVk!{np#WlJKuw~( z6s=ulgNmBe5zG*>)8d8U`P`LUUT6Oq=PN=pqhm6Z!7#bQnLpfu3J}43~iJABw$C ziZ@_AJ<*|=qBaRNH*vUj;zWR^YP^D$K{5gADyc|J@$@Bdiq|pbI`rThVYkB(YRv%J zdxIEeBFoTO@fpsy*G}Gm-jJru*y3<^7TCrOMbc|8bZ^lhuYH&2P*dJQd*xM)u^Yh>|5(poN?P?>={Q_<)PYZso{R+V zSc54Zsk=U@a3*kAyvik&Fx%9iUpW?8CqP_({fJ6+E_UFLY?Q_yh0ueq7log-zW!2j z^x{S#g-dbl_VsJX<>O8bgGFvBK2(IsQ2-V~GOcmzB~RtYuc#2s+0@Xc?5pnqr*;Xp zCj^SwUIirdhW6rs8s6c$9ZRS7k%w(@TOnF?S~V?sUCqS-f-@7R0e`ac)*80zguUc~ zs2`yF*+qz)*sH$}-!_T14eu8QuKdmBUzT|Ve6WjHddy5~nC37L!t+pBYZ?#&K$oMs zFlU7VA33A}c+$@jB-;+<6YkGuCyVuWoz{w9$ipCZO;>EUj`+PzXhVTmp5 z<`ob3-Y-aCu~GH2q$k1gu4W(OZIRSN(uAi{&%BKLCZ(BBU;YJY&s;`Va(Y)>BB6&! zEN73V@{wO0@{WMBOy^zrmh)G4uali=sTW?xEAmLO*#~BG``RzP=GQcY5Djw02uUrB~RajwD=xZ*vs%xmWUl_~2v~e4KVeW!^1XC|S=; zdqrL4Yi%0b@k>1u%bxqO8GE?jJ4E4Nrk`gwg@gp;m7`!WVlkxH6lQ8q_jF*W*~8#A zMkOfbTvYl5XD^5r$z)R7STNFodyhT;1&vBjy-SSyjj&y zjy9Tc3}8h)R!r_+x|I)iDMpDZZCgA#tjBMBb7DN&(N5j;@y3XWn~%}Hx!;1(%)vvN zoP4m0bjHtO+cy}P%}tSf>)3B?O4VO9RF%LbO%;$It{tfs%UoYY<*F?TY2YgrFT)(J z0Bk}gZ{4$~U+LiHNI2dzDqYB!z+#Xjmh$}Ww8UBT`g6o@n0agdq5cELqQtAx*U^f| z9RW@S%B6I)jzW^y!-=N|)<4LTt5PIw0|4H&_?p&~8JAk*H~P#84lK%Ahvm|M~|wCfO6aT|6s1x-z9HC=1w2_W zAMbtO=|U7|xo)1(n>jSC6V)LJsfi?GPa69g$4cdI5-0a!=dpm1(v)hJ5~_S_gDMg? z7vVW1ZV|zK*-5o;8r%>owP(^Y(f`kM^KBpX>m5&_RA0D8L;&-&&bvBf>cm6qW-i${ z^%Y6DAs7}SyW>5h=J4`v+rt2BvC84rAPNof#?5-Mo&^_^VmxBeU2yNToN`XIoN?qE z(Ir|@Tz@nvV8(itL*X0^`~pY?|KK*pi$(LjVQq7takVLtb-n`cG-9RoFnW+wg1i^I zMWP*rIvs|61P)`jDt-H}s@)}ve-I7D23*OHqBq~1in1-=2l{bVyiI{&YXj7Z!5i$%4#{H>dSQTQlp;|q5Vzxz?~xB-HnKyq8Z zea?K&B3BoHNZz78Ni3SI8=}vI@TGp`kxV6pG&7AAvf$x08o~OTkG1M{T;>gO+$b|# zM~+v0=Jl*g8RYmRvC~E$@FRyHJ=;GdPc|Et%HQ3~TWHRU>P;<|r@GjHFuw?Z! z{@EZ%-)5Kv>hpmX+b2dZDl{E0E-Z*yc2w$1`G^22swp~-gjUF0ZVKx=9dU4COaNy7 zhcw2pih}KsA+@(MQ`1P9?KW0?;rJr`L;{i89l99;K(-9l+cg{U2h^uopkrvlCFD1_ zk?V^~uvUVC@hpE=%!qPm7)kAp?))Mx<93l9wxE{W-{2>X{CJ##`u6OPg4S`aSxUT; zQi7-7iQi~D0zRf7W|uFoU-M~IZO@Z9>UDm-#9~Cxp%ZXjP%#9c>RmGayia1+Ws~6& zB$f6cJj}4Kr0p@=Qu7$ejh!#QVl7tICFW}Uh2zF`-XCDTjsa~;XzK;xV@ah9sh*2U z9$<2E`T=cET7Lt}K$~DL)^vbwzN{!HKo_K??+3JG;oozdPhBe<%8)|eT|(z03h{!M zW`8_R?x97OVE$vik0@3C{#jH)J8#F=RXY(7VXJ~T%Mu2BUC#6qeTerf`7lN$Yk>?L z_Psg>=Df=negz?lBZK0AM!VOVt)~KmFJlzNZKH@?#YvN=P`8T-AVPvFOAh&&4Vshn zO1YNJob^sSj9!ue93vUN6{*x0VjoszLB#wV7`?i2K(X04xf9KfKc`$YLm-oJ&G#pK z7gu?Y7KLHrdSBl)e12J&cQU9B#AdPHzGmKW(fP`1%aUm$Ng{fg_ZXkw`+)NkJ_~bP zK3@5_eV+HIOwaVQ&lO|J@=}n7=_gKO z5T~3Dkba#^#8vkP{;R0 z>`bxHWhW;E)Q$qV4-1yv$M0)**x~XmE$dJTVY@7a%m%Tmhc5{VY;F?gH1ZF%;C1oA zz8$pooGb>>QIG^y0v18ZGD!ddJ)iiJkY6Il_1%rM82Z6y_36lrAM_hc>v2bu!emVBq8V6rA@}Ugy%e*G zMBNHjm|sGZ*d6jGX#BS%xY%6uUr?G8HA|Nr<_nxhy*KrvMKT34J0RC_PxOHYcD)<+ zbjhsn;3VAF<4lGqXPsT&;Emk&4RLD^*J`3Bcf3-JVNUUa(wHK@f=j`-33yrW17|B0OS9BnwvZ)<6~^*@_E8gm zz^m}uMXEH4*wL5Fu%|I0?cLi-gCee8x)4FdiL374X+d*wiJ;=)tCu7W`q;Wx4bJmwbA!ks{ zyONTGp6-hQKJGlXiT6$)k3}kdOFHkrTEa9ae!&hizgOY1wm0B76-!?(YGffRRvslR zJ2YvF*0v>)g01Z2$xK^KA_X2sZ;l*HL@()$DrSGDd|5X$`Z!64`*Ha|dhO}_Rf5Di z)50Z@@|^G|2hx@PN{ohHZg3f&6StTyD|A>2;=uRbi;<{_noUX-w%UzP>>j$^Ibpm zp_#E=`s<~?_~{!9^2$u3BWe{VH-F)eUqdL0&fiM2?}2uLGiwm7tF-#^cX(F;6}o3i ztkMJYfI<6Ai(#hySIQ+<^XaEhR(eEDPdvv8fV(L4^Q$C4hDVNKbxxsGaKlLo32O?Zq3V@ zRJ;qa{96)Cdp?Uv($6mnC;A40y{q1y6dh3|3-!#q9a`8l)$hf>u=&EYmF~$EZ+sG^ zuRxL2&XyqvuFjHAVlW@>$GpG1<1z`uv(3i9e|Gy+FP3gY4N1A4TxicPoKGd7mT(#<8t26x#if$7#F^giOF9g$I9h*3<+EPM5Z73`JlQrCk@eWw zZHD!rZ1jF^Cr|1(=Z+^ysh7r9SfL9X^L8>B{?aWhP9x1scy_noeD@!T-+kTcueqF6 zYoiASt}>z3_>jg^mbNahlebYoJQWs*j% zEbAGqi8jKmTgPiSf?y|iy%43&T$z^6Kwj7$KGkRA)qg?bED>G1t_EE0ctH@$FD9Z5 zX2$o>uDV1}$86QEUFx3o$xns7Gh>*at34wT;%BD+?$4YzGmRM+$M?_8A=Okw6IC&|ZpEg^c{C{OrGmZbLL-a?dQ6a4T+w66l1=unr3*H5CY zaWU2BHm5XieKJ!oDUHY978oZaP#^E^d@!l9!}>9O;v~hify(W>7H7LTN3jx3FFRM)nUE@KTY(g&<3$_mW0}U>VSmhK3pz0L;QBXj z%fHYyISS^I0EOlnBx?RrYKEz}e&1P=6l}8qt|#oSPI#-@ruxPY(duqj%tuuFmXSNeSY<+bfKQf<)ruT)9=1Cq zAd92XFj(G;^aO@U)V#cC$#SsIVtVDWS#xNinL5{K_HHcMyMYAmJjIqn^JwU*7r>jO zvltkyY;?%Q12clsd%DRs=iHoYy~gNI-m=Xn>nSqryjL{Bz+>Qw$~F7 z(}g9&r6ZbVyu%dczw#aad0RIq!TFil;G6u{Tm9y6wDwZ&&=<3YxEkyAN z#lHDDSJ2X6=r@>=Oa`h^e`cDKf>A^g-q0PI8UE$c@IuYO5WyB~>so>qN99ueaC+aC zWt8lmeR9$!UoO-^Hp`eSfl-xf#_7FZUU5 zvrx&M>P)#@qv0wiBd!?baogDd3F+}V-#nUWtE7XaQUP)HHV4+)9G$Sj^^N_ri8~{aSK`tQ)CkbI9hjh>eR(m;Z4+4r+=$uA7KdOx0*CzXS z+8Glc&2yfALGJu79WT3a`~q81(CuRry8x=A90n9vB-~H#gG&id`WJvo=gU9(h`fa` z>xa&Hl}DFSH5(GAs~vHyiO8w7BB~DW@C4;BC_h%}Zg{nwbc*WmIEL21tPHW79`#^R zeum(V4+n@fw;pV+p2KLXNCj6v(0jcPu5UQ!z?|wo?BMwT zpTe84_EC0n##>P^iIoM?Uxiz<|XbWDAsBsJccDq-nM<)|+dj?#=wYFL3IzQua-aSYc+Rm? zA}>NZi1u1D&)$lq9)g7x!l#~~-X5#Wp!v2$ZR@7v(X5#CqU2gTLzOw^dN20kyZB6b zGkCi_KfvQ-405ot25xPG&?+KdfAhThy*|6XIK;(}^<#>@a)pn3qtC0v$xlS8c`I9e zX-l~Dhbf9>U?~xm;YM2NpY$(Cb)l$sg{ORH|9vv22}*n#*859o?UjS6IJq&s3#Rd=kg7cVnWAp;Nm(I!CD@rS7jVy>@ptNamL zw$);cVl0?)PEq~PQtLBK?f$i8d-NHxS9uR3<18^NLcrS7UDPnrXC1 zqK`IGqMsGB0A|pVu3cn^v<#%lV3))Kd)7Myg{Iy4s{Eq#;i3mmnKxOM*SV)6c3Qoo z##IScD&qBw;IHnw#;@XyjYD~DR;V%IBqhOLP6@x{T!cl19~`J{o(A1i7f7f$Z@t1k z6uwFVcM%~iq9jBhHo#$0E+6_VEDS~a(|wE0zW>SW{K=Ezh15YcYX|U?0h}~tjd0jd zb{U$j?)4OWigbCvT(DjLV`q+{)UDL69H|@j#}c~@L?{eZKg38s3q^heT6p^U&icD( zI?{F&pf@qtHQoj^W06#}arCFDdBoiVRO_sD3jvIN&WPQd?EGIAU=MvCr|;AIYV*5I zp5b?b4S{@X4&%vaz46A}Aa{}{sNo@C`L!36!!Y|EiBpx~QW9u~3Rt|gVzv%v_c=*+ z0R0-W*C23UB13Z_CYcB~P@j+JB{hc0m%#x~yHfo&h*d3(cR~aJLY!hmnNe|OJ9y`9;A+C=mKzN-M}KK@nSjIh}V?_l5J`G9_BYYTsKxAF>Q)J56aW|KB+ z(oRbPvx>65tD5@~^@EYFqqVZ4(Sj5#J~ddbl0KuJd>@jpy7ZXi%kL2uT;}gITQ?ZP zr3F)RNb_z_XrOiAhgAzSe{**mFlcj7o`|-e(GY%qe(m=yvTv-nJrne+23fgY1n-Ur zBx_jX-%v-C8^esfvU;xCT64JO%KJWKRE47(xLzJl&;^E{Ui`9|4xksh$gGZ_S3*)H zet6>?t?~tCMf6jPZyWR7Se!%h!wM4TA-MwOEZ2FHi^Y}*oF?{OeP4u_7N{A&v!f1=06TMu3>Tf?=hPg!#b)(%yA7V zpl?7Ac;R1ds6o^12_y7aNqJ3UF)4^sTK2MJSnIMhVx;#>3nL74B?y}3>n-`E{#op* zT($M~O6U>I<}{8U#`6Dt@VO zp_gyPUD1ar_*F8JGSbFY%#yE34t4mq6X$MpfK)1_@ZiNgxFUOaSB6r#<|G#?2&+|; zk(2|;0`xG<_y65ru010|c>p+;I7Tml+iGAJ#$ULY&;Q9?#GeTOy+!+P;raI7)i zK|DkF=KeTbi7}pn(9rFg5`JO@s4;P{aP1VU-zww6^CbKuui?^i(&6)*)+y10mqo9C zU0fZ@kUejbg}EF@WjQcL4I@g)PowH^K}^|TAoA*(nrKL@8Km8A5=kLMD>tYcd;QmVU_na{Q89m^c^cwC8f>;5`3hqCnJ9kFV@>eh`H7L2A z)vngM%zO0rG&X#H!X>MSmzanyi?LU!#-sck#KVV;crBeRpX;Vmq9=Obk{ri@3B1i9 zTpZp%37k2OR7EIQoAjSuwq4Vh+q*;PvS~Q^&)D7Aa>O$X>yN zn1F+M`PZ_juIUMw>SU<@@)PAj2Ou=iC*rf6X$<;Hb*q(=O+E?~=LcYZGUPL}d4FTJ zv_J$m4?Du|?B=3uGokuOgOb}icHmE9%)D*s?X+vsXfCIO&;0wX`AeGpi&FY;^KM*P z7`N_uj{>G85XA`0L@m7;js%==T2n436@fMq7&-Jv z7AUo`GZd&8j5yFh*PvhW(kKb7{0PtkfLN=dG`W7d?SyM`I8qMFx0{K}Zr36^l(nHH!Q$0mqvm91|-I+q&kc!dIi&Vmqf07O^X6uZ-yT-5(EMc^NhlhP=C)Uuhu zSp2}PG&&GvpyLa%x?|FPgW1~9Mm5Z|9u6W`4;$8-?ylR3&5&-;p>v73u}NosqWD|! zslMBXbX~f*qGG(c$r8&2O!t(MUaY0+W1~B1e#zW#8^mh1R6rLg=J~_kOZPWiS~wk` zmX3}v9nn9-GH+j_aZINrl%R&FsXharpMjS3t)YHmaR0Znl2_FZ;`Bx;zFWc4%B}g} zHq|!y=B@FGw>BYWl%6TyQE)V|7ArW3Ak>MVZD;`oqO@x&@FK} z^rwg%{RF}2ljvE;m>vC(HeAc_8Ed3)(nmGz#jOqXrcOB=cY3e%>u251%%q^UuBEH6 zBXP!B!q-yq5dSjcE)10{JBfx+Neu=r#>rKU5^&~=&O$tu9nwegCR$c((|NglxrIfk z>qV7d@mZxG;}93I8AjnAlbw{ZVfH&|a}II5F}gXW8Gs>v{Bp@~uFA1%EEkD{juYle zI7+X)Rh*C~;{a5Mqa}^D&Y2ahC>Z23&cGu1NXW^Pz@EYpN@vx^nH+$30;lDvcm=uG z3WSueFicMg;wz8f-3!K7+8$ohO#swmt3vJtlKvH4RkV8<_%Ts&C2u}MQ~mont80Gt+cyK@`OijKU`5?+^V|AJ z#%NzRSbPW&tTnP~`o*(W14&Zj!noEf!Oj^9`Cjhq3omt36tZb(caRR}r>E$QlQDk9 z_tRRrFgr5MqOSq{%7!V@PvJw}ec7-alCXA=J-m_Y&Xux#wIS>s1rVwM-KhH?Ij9Nf zEx1dQdwKR{7IjXRR-yD7TQBBwZMr&W2a;sTatNb4nx7)|U(8qenZT#8j0Exe+g7jB z)*0iDj+W)D2%APIZhne8pZBcVVde*t9!Zh%O+oFSteQA*Im0U%SED2MbLOoTdtCeU zRNC*nc`lhK4mBI7UP9=xRb%yezH*O@FO$a+LBQ8Or}5j)B&ZJ43_)kA<6Ll>32n1N zNoSYp7sV;8pLmpDXZ3hr_%Y5jz2=;sjSKf51uN>@z`|aNFx!>G-a!y>nPRJhC|TsL zW^Y0Y=CG(K9v(l6JzG>nX9PIy@)L71xT-b8%c$IO9b9G=j29obL00?_vZQ@n3QL5; z7Zu>4FM@$28({IFatF~ki2CR&h{tfz=-!Q8QqCPp^s1`h+=0k*z??8w%U_B??!-i8 z=@KI7P3OP;?8Z73kCt}Q4vXF}ODC&$`WFe2{8G-7%(V-yao^sZRFg)i^3|nu%DSpdV=`|@EkOmcW z%Zy}DO002aAMo}`mKiB|+ZGcERlS&Fm9bL#=v0Jt3hBBm`~h3G$J)G(X<&L{r|Iy? zLTPKwq@Qly+`UjfD@P1iiHr+AYW2uH)Ba^@pPpG~&kj2(8{HNjo-W z$rMXcwgV;&E*nd;zyPcr2X87<$1?O^HqQ6lLL5YPy;ij@o8HwEDt>9jYC zR)Y9Dy`tK)jsBf$mnd_S_T;hCQ+@sBf`bQwIkfMl%CR?EEBc#+%VswzSfC=!fT}qy za-XGVco+1D7*Cl{E$f?~($=eRj|V*cx}}B<8i24z-+HF|?c(IE5}UvT_&H+Rn(q{^ z*uD*wY?#~&YYum8JYgA>;s&x^QI<$SO$)o&K-U5j^TFK$qp>v>9hy}VOlZxV+lZsY zYqohmqe?%C#Q>Uq_?=;ep1TtIP2g3Le4{JV)b49C%)&e&_RwUF#)az34G=2njbxy4 zlMPZhwW=opCj9*aZyKT<8QO2{jvK`1&Z9A4&ees|s|3?MnZ4*V8Hlcw-5M!8cWP8j zzvomLNp4OuO4TsSgI736BVy2U3+`7>jJ;e<5kEFyiKZLJYy(GhUTx<^Z9(73X1D}M z{1z%du4pwQuKVL7VAKO^R7*orPd!`Hg_-h z>A@Aq8x48;m?T5g_- z$@DV&Med>5rQg>CB9O56i|1T~j(cTBW?tgHB=}x|gPFXIn+{o$d>uTS@zh3q598me z&we|fWt~ORKTgBL%A9X$MT#N$?G*+xDVXT}1h#GjNIIw0V-uWX{WRa8IWrt6uet6m6Y0XRUNQX7(sW~X6G1Wt4 zUE-`#ln1q@G`W7FRkqBew-$i!Ajb|9aLKCIN1HhzQurGG^@%48vUXqxdyR)n>AE|X z+Z$)!6bg@qh`?=NJg1$uTW67rOX3F6FmG#tgQU)S4HtL25a!O516mr_+HxoWQxtkd z=r!J(X&cqZAg^+q#pBxVDIRq*^NUrJdWmlSdv1=9Nl-XybP#0awcl?X8`>O)CbG<7 zO;(+OMh^-{@`OxDm0}Gu9)9c^9y6L2kGDU%%ns}`fH{8!-qACX8)4Xv@KP7&qA|im zt&IM$wD{h>*Pek9&CqryZxIjyjne*^!?oxqE765F-S}8(;E&0$9qh6#w2mt2-J;F< zV^XvbZ+eB7bbn?XFejlvOHxd=HQu=Fq+aK~%|O)qtL z!o3@bC?6P1!MD|YCGI1FHx1<~mVZnXyqy*eJPc;sVbvK{QVT;F?j%@VSw;xCufqe3 z3=6!Kjo*x6SOhQTN0J1u@?5@k6d7S$RLexo(vy%MNBo#%R6W7Omr9K+I3!;`Vw4CZKdNc|dJ%nyHiOz5a|f9n zF8MBE@b-_yy;tnLtV-6cL0rc+#5x!u;=`*XB#U8(iKsxs#gAqQCI#hiwKe*Q&l(I9 zuEF|>5`0!n;nnUA2UW%MZU;i;7Wf6;F%>QnESZZvSw$tMkO(y&oBr1ttwLKv29Abkkst&tcu5tquM3h4xSCKvJzWK~8 z`|af9^P-*j!mX~Y(r1XN2nn^V`;U(yPE!L^P2vpEC=-h&Mo3X))Z0PpfST+MV7(C} zmZe4ymx`sxbV}#67Z+>}gai^vjtSU%)P2WIRDd!#5T6Y!iQBcQY3RlG8{9J7ft%VK z^?~Y(McK}-#%{I5*lbsf~O} z+UU}i8@f5`&1=T6e0O>c#`P48G+8{{r0@TNyyoo0@##weDWO^C@^6LsY%6nI-htwG6s&)Q!)-9eDiWrL25yO&`k_4zjzwQCp4W&eW-$xB}v-&!;shz;6;&7 z%`Q51CsM;j!okCC2F3jQiAy*0KU?;jk5%*Jd_KtdxS-2yX~Zsz0iEaN3jN&W59Yr# z_Ys!L7lzD?jpWas#wi@jP;wLjo0Vj6D70iA{a;Z7hz%%TD8;9dAkIlS`ir2)Q0hV! z&*cJ*9iYE$=YNH<|1KcK6Z@O0EFB}>>P43sb70DgX-!EUmi_p?9rt6q^3ipu@vq_T zL)mFHyfx{wz))O%!}tE2f;bBKllJGt58nwux{+PxqQfpaj#33hhjMsgRQ*RB%l>jI za(^`=Z0z^&Vjy#VNd7AfCVZ#kaWtjUNMW zEg9$lDiG^kK^0U75Rv%)BN0J|*E40gWsZ|&sQ&H+G@>$gor`iXU~f{)_0k)-D<}mX z!vzRL;{BD0eiWG(9?Ou=0sXF!zfblUd1(Q?DB}M7NnK!Ake%=)G)SWeWK8&(UtM5I z2)J7rO9DxyMLZ3y1duwsqn^7g1X?N@Oa@#l{K=Z+9^Uhngia6T*DH3m7GA5p4=A$FDb7)P}>jkf1x zwvgJ1>Pr#>#q#Q0L-g4y5^85{Ou?>ziH+mCUk z+he2b&4M?oiZ!jhe^OpmyQsIg=g@yE0KL}hy%sWlY@2L3qW+Ba4#5HP5?M8sqwPs1 zs^pL%61_*ui<%G}qo%R_*IpXAT z^kqthxdmjsr4C~__jk8(Gso$6vqwHm&aDSg*?OT{=F>9S$=>n)4wVY>IMk3~ZJlR% zj|FHeN^Q;wmrSv&a*#&)$2Uqz_$eJ}!wK6(@16;$UL(JAWJ4XadS5PU;>22_%?_LR zG#v9Q3f?L?eJaGdC{L>~9rbj*vUmZxl;mb9eqf>z9rh#5t+cAk*!gDmt0l@ofSL0X zHT&}dlW&%0LMOBC*70Km78vbTLep40mQnh?j|LaYU~8Pc+z#I&T0L_HK{USxodQkMP(`tK)?7tSIwztk0R>#B!L8M1aiO;*7jKYANzXSG0EK z%6?r#*TZxJnXvlQn|*$)``sIFD65OTh&a`E9;yZAwmU4-ZCscD`%jA{hYx{tNh=Bt z4ovhbN6opvV2io#yT1+(HrT2kW$itFINIu_BmN>y(Ls0FvCb->`0#ArnXoOz2mAjk>N=yE2-Ejb zSWwsPh^4-l9>B)v8;={K)&$q7Txvl91V_`y`mLbre_Bvz0l2?JF^-y!*uAl z%86=bjq|(LCAWAxy})dsk6Vx`5$9vga=s@`cyP;CycON#E+SL65`X!dott6dnoSnP5+h2&6nh?{QTavd&JhV#-g+J{5f3egtNYbF&%0${;!0f|Z;IL1*8IIG z-y54_;nUYL$Nx%`gK^fL@`8gK{_scUGTZGwjp06aXgq_MApZESniB&h;Wj=#JE+99 z3e0BD81o=)@|N8FM0%=DZrjI~OE4dT6BDxN8w843w`P=1N6OV)yDfbEd%;VDgY+_4 zx)cxZ)qXzPSA0%1JvP@YaNtDT3QJ4N2AH(O_}`u63~k~lV?%-_j&I;w)Niq~>@DRGO8AN-hQi&Nlt z%3H0uMzxaYcK3EL+Sif|E6EDok$yqPYGz}*;@Gm7enq)#<7x6OaCGj1_lB9f91mu5 zmpNd0%ujUGnb)d3Df4DDO~$|aj$Wm<6foUyW~d|8#xx5$&B5)~xzbg=aE11C zky08L-&S^qcxjk^Rm-|GGgeJyW$g_j%rhlKP1odNkX3pnY_8T^)2*`o?q9f@UZ+7D z4QPMa_zv3QAC6)ws*e%h4%v_i?Q>FN(oHgD6fx5*_0F`SnrM}Vfb@5?T`ykQWH>ff z5CMr9M7_ePC{Z4BKw2iwcx*)c-(oQ}0ZTAXmJP*m0_6yl1YBN+gSU!r77Uk{z z5omM)?8J&3Ynyy;bjS4V=%vfHG@Cd3uXHP8k_6mQ(SaUw{9nl|nV)UlbIt={Y2^c+ zM^5=L&N?@bG^>+qDwcv_*4%j;8Y)0x-A<^DmD=2qz&R3V=;KZV5Ij-FlM8>E`a`T{ zSQJ4QVuP$+RF)&bl$J&RIC-3UWR!aM9_}RCIkZryb*nq;?9jQ|{y=^N9`@*3plf z!yMhqr4_Qzj1K-utJzX{Fk7{GC(5fyq!5m*RG=~_RGdM++*{dhujN`Ms@5czYPZgI zLY63cT$=QxtVz+uY(5z7Dk z6XO~|C~A6qfZ0D;3 z?gp-8gQ^qw`)kug6Vmv)Lca+M(K?ie42{SG6epVx&Fkt&08AlXgD=M?dwa9#2RzR( z#SlX`hR-%LR|0ISd>q*;ssxGZN=sYX94s=BH#gx-PaARfF6pM z8diY;Qt(npLeXCPv%M^Zu9N#^0X)|wO>^GHT>goD+EzEHW7tqP(j-G>Z_}W`CAYGq zJ93e&V!YYy5P#-0JXg=g6I)et2}Q1^G22no=&tZZml2s@)+JGZnTC0amnVSubZP}#5ga9iTF)!_xAg3S3~oyOruPK;9ttnPw*$ZBa1c6m@f~1C6Rufl`o)fA2Yc)yApA~T&svk?pKTnt>rr5B{$JhRaXsR zACwM8^i*bg7F?ReX)EwYtc!>!vR=fZH+$m-W9G(gqt(lP^XjwW3ACltO zCIlgsn#+nEQ|qXbVdNxwo(d?6ZT%9$x>+2XHr8>%JBb1RSi~6(xXD*M@AP~C4R{nw z1Hd1|iDt!-Wr}6q8%YT6?vF9e=AdO(sq#b-!;vaKS^?(g4TZJg7!Q$p{E;8?ddr ze2WJpNZ~9LirUErK;7?qoU>Vzx7?RZCcPvHf6|o8-wS8h02qeP-v?oGJNWUend4V7?~?yI{d7Cbp3=WE_(}ElBopLitcD?-cA#Yf zMISA1Lf7&JuBPrwP^8m8XXI5R#7AKd zEwWMbj5N}9RnS5>FkxML&aIa0(CgwNomtW|(Jxgv$`L=O`)Z%`GH?@e!WkwF@j-k- z+T9+(PLS{$z6xE%rJdmdYc^VuW>Ax^Mmr%+8-yaa4`N~h@F{s={iWS&;_apF_gd8T zsRW>27CM6mBKM3;Tjms&vd_UQfT|i~o&Q!`^#XAC>aGynn%b2Zn1BZ9iXDDC*{9$~ z!>*dg>kAEiOg?r85-d&>AT7l7HRy-D3+@J>47hv9h;bfW%dCR7ww}*1u^C8!oCwC9 zf&e)MFUSvoApXG+9Lt;c@JTN|uYrJ`&ftI}|I1zZKjw=5EbC}mVuMg2$n2j<`zqkp z{-1XLg6>$J{%eB_Oei_AEU+Ek6*506(|eVN0C6ll$YMB~I0+rL5ZS6-G%+q-11z5G z{+;coa`}i^1sH{{P+(G)zn(AbSvz2=1cc{_^YF9eq%z+C20AlMfU0L|5HV4_cO zhl2wDA8xP);0WX)&?lBg-S9uDmbZ?_G`Sy~f-L5BV4f#cCuiLNQUtJb)G1YaI8V8h z$M`2??{HLXj^pcpw=@d>y18pf)WFh&$}AoMvZGQmigoGOy%Y40zEU~ToQt=-P0dHg z$L*ZthlxgQqjCdlvQg~E?w_DRN7V7U|6YNzEI;j`xoaN%KhyWD*dMgM562V){sTi4 zywgZo&{yFYUjy9QX?$!}&+Zb6b%xa43*rCBGa=n7->;@>kc$2R7oY}!nv;venHc(X z$^xVsDbRIrR))p@5p9To0n{C8Q7Z6@2ryXYT5weFrj=B*+(Hgb>BKDf&|(->?){IP zGbu;2rXImHN_((UI_u|MK{59{WUbhhrwJLdO~5Ip0tWh`AdaZ8&=hRkFu=_z>+{cF zrIZ?6j#x(I$XZ@I1=-|oqwan=1(B)T069nMA9z;i1@NvkFKz=veA$t;`cBp;KTH7k z)i`jJPDEMVO+1g0qwswg1DGWx#q><1$j3s-?)nppX>l4Y5oNH~M*PmilM7Q17D(usXKKvAO0^iS;hCIVT; zbMq*@0WEn~z+H~0p&aWiOS{n7la$MYQe6X`S+9DWQbMlZ2kYnY(_JyC+bQbZ|G5F< zKEwkMpy?BhUvooCre9qi^xwRfJbY1^Y%{TPD~ z+D45xiaJRc%P%+ghItbHwIhK+_!&^sz5q?zfXi+tBxNaT9@!U zvkP>To*x8_Qh8E0g`q75wi{M4mgzcD7gH4sdVVsFdvID8tNY?W?3V{+8) zlZ4Vh!%r~TfC7E+QZz?Y_(DRYUUdSo=t$YCtfF?{%PC>hz^-3~@tJD-8KHiYo zq3mL0l7r&<=BK*4H-og5ihrH`cjfz)5<0}%FHU!O_#x3-kp5)AugSyT%BWH@BfnCz z=$9P2FSiZ5Bdws$Nzb?k%T0NTYcxIgC`gQCxzgxceWY82#4roE_|)MlwHXGj%%4n$ zhD(Mq+ZksVh-Ag{&eV6YR+~11kP_Cdv>I2#vRIk~vD7fSn2%pTvZGmCw8?(~!DpF( zrDt&?J|d$B{z8JC%roGUw?1Esb_x)jgpUR5J(pl$QM%F7PJ8ojxV_}iDd>qv(8H%o zJ^)yNk(pGvYk8MRjG&GN}jMdW+| zQ>_@w2Nh!iq-?#N%TjDK@-9 z<_^bZHtLR6Q~Vg?;6r<07P*O9oqaN@bpuAoY(NHeKNd)7UqZ&}+LXlXbItn$lq#IU zrCq1UeXqBZW}>Z0zfu%BavRdOq2`nfP?`)2F~d9hc}o4H2(9@Cj7xeuQP|eO{!xfe z?hx924xpF&BKuIx?#|3IaMg$o_}X7V11{Nj>KkSY=kTHYo*5tqWmmfr!geaa64-Zd99nZb?ut>_hJ9GXjl`flFhw>9*Z&v2FRDY&C6t|F- z&rhUPxi{n-eBw7u=P>j(SiMX!yL{SizVoxIZie!k$BE?rOT)?G$(#0$Rb{&66bXa+ zQLk&G=IxGGsn>N4^PS^CNA$}QV-TnA*d2S|FUj^*d1<04$^>+zK=u)4gFMv)yYLUw zqme&5_YUXV%YIdk@fqaW<^Cq$?XSjKR3D`B{fuQgoKTPGjwl?1FfQTzVM>3nP())m z((Z%Qvl!uh<&ABNCfN6gyE#_+UV^%iC^ZwXzsAZJ4+db-38ug*X6>M#_T+NRs8~~a1fW03sQy%7P#+@g z0J~S^V8u5uDDfK-H+u_q-+vL9S{Gx-pZ|;rnx&DsGUjLd6YvyIThrt;Z_i_vxF-xk z)hsPD306zLjut&0(~l8BxwZ@tFE{U(IUzf4kKxmX*bxf;?nZTf1ulpZeHa zloW!|#~HA`c*|cB*vhqTK!HC&L|yG-|8=3xv_;&h@M*Z^ + + + 2.1 + +

### uVision Project, (C) Keil Software
+ + + + rt-thread + 0x4 + ARM-ADS + 5060528::V5.06 update 5 (build 528)::.\ARMCC + 0 + + + FT32F407VEA2 + FMD + FMD.FT32F4xx_DFP.1.0.0 + https://www.fremontmicro.com/upload/tools/pack/ + IRAM(0x20000000,0x00020000) IRAM2(0x10000000,0x00010000) IROM(0x08000000,0x00080000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0FT32F4xx_512 -FS08000000 -FL080000 -FP0($$Device:FT32F407VEA2$Flash\FT32F4xx_512.FLM)) + 0 + + + + + + + + + + + $$Device:FT32F407VEA2$SVD\FT32F407x.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\build\keil\Obj\ + rt-thread + 1 + 0 + 0 + 1 + 0 + .\build\keil\List\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 1 + 0 + fromelf --bin !L --output rtthread.bin + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -REMAP -MPU + DCM.DLL + -pCM4 + SARMCM3.DLL + -MPU + TCM.DLL + -pCM4 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M4" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 2 + 0 + 0 + 0 + 1 + 0 + 8 + 1 + 0 + 0 + 0 + 3 + 4 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x20000 + + + 1 + 0x8000000 + 0x80000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x8000000 + 0x80000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x20000 + + + 0 + 0x10000000 + 0x10000 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 0 + + + FT32F407xE, RT_USING_LIBC, __STDC_LIMIT_MACROS, __RTTHREAD__, __CLK_TCK=RT_TICK_PER_SECOND, RT_USING_ARMLIBC + + ..\..\..\components\libc\posix\ipc;..\..\..\components\libc\compilers\common\extension\fcntl\octal;..\..\..\libcpu\arm\cortex-m4;..\..\..\components\libc\posix\io\eventfd;..\..\..\components\drivers\include;..\..\..\components\finsh;..\..\..\components\libc\posix\io\poll;..\..\..\components\drivers\include;..\..\..\components\drivers\smp_call;board;..\libraries\Drivers;..\..\..\components\libc\compilers\common\include;..\..\..\components\drivers\phy;..\..\..\components\libc\compilers\common\extension;..\..\..\components\drivers\include;..\libraries\FT32F4xx\FT32F4xx_Driver\inc;..\..\..\components\drivers\include;applications;..\libraries\FT32F4xx\FT32F4xx_Driver\templates\inc;.;..\..\..\include;..\..\..\components\libc\posix\io\epoll;..\..\..\libcpu\arm\common;..\..\..\components\drivers\include;..\libraries\FT32F4xx\CMSIS\FT32F4xx\include + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 4 + + + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x08000000 + 0x20000000 + + .\board\linker_scripts\link.sct + + + + + + + + + + + Applications + + + main.c + 1 + .\applications\main.c + + + + + Compiler + + + syscall_mem.c + 1 + ..\..\..\components\libc\compilers\armlibc\syscall_mem.c + + + syscalls.c + 1 + ..\..\..\components\libc\compilers\armlibc\syscalls.c + + + cctype.c + 1 + ..\..\..\components\libc\compilers\common\cctype.c + + + cstdlib.c + 1 + ..\..\..\components\libc\compilers\common\cstdlib.c + + + cstring.c + 1 + ..\..\..\components\libc\compilers\common\cstring.c + + + ctime.c + 1 + ..\..\..\components\libc\compilers\common\ctime.c + + + cunistd.c + 1 + ..\..\..\components\libc\compilers\common\cunistd.c + + + cwchar.c + 1 + ..\..\..\components\libc\compilers\common\cwchar.c + + + + + DeviceDrivers + + + device.c + 1 + ..\..\..\components\drivers\core\device.c + + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + __RT_IPC_SOURCE__ + + + + + + + + + completion_comm.c + 1 + ..\..\..\components\drivers\ipc\completion_comm.c + + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + __RT_IPC_SOURCE__ + + + + + + + + + completion_up.c + 1 + ..\..\..\components\drivers\ipc\completion_up.c + + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + __RT_IPC_SOURCE__ + + + + + + + + + condvar.c + 1 + ..\..\..\components\drivers\ipc\condvar.c + + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + __RT_IPC_SOURCE__ + + + + + + + + + dataqueue.c + 1 + ..\..\..\components\drivers\ipc\dataqueue.c + + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + __RT_IPC_SOURCE__ + + + + + + + + + pipe.c + 1 + ..\..\..\components\drivers\ipc\pipe.c + + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + __RT_IPC_SOURCE__ + + + + + + + + + ringblk_buf.c + 1 + ..\..\..\components\drivers\ipc\ringblk_buf.c + + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + __RT_IPC_SOURCE__ + + + + + + + + + ringbuffer.c + 1 + ..\..\..\components\drivers\ipc\ringbuffer.c + + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + __RT_IPC_SOURCE__ + + + + + + + + + waitqueue.c + 1 + ..\..\..\components\drivers\ipc\waitqueue.c + + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + __RT_IPC_SOURCE__ + + + + + + + + + workqueue.c + 1 + ..\..\..\components\drivers\ipc\workqueue.c + + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + __RT_IPC_SOURCE__ + + + + + + + + + dev_pin.c + 1 + ..\..\..\components\drivers\pin\dev_pin.c + + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + __RT_IPC_SOURCE__ + + + + + + + + + dev_serial.c + 1 + ..\..\..\components\drivers\serial\dev_serial.c + + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + __RT_IPC_SOURCE__ + + + + + + + + + + + Drivers + + + board.c + 1 + .\board\board.c + + + startup_ft32f407xe.s + 2 + ..\libraries\FT32F4xx\CMSIS\FT32F4xx\source\arm\startup_ft32f407xe.s + + + drv_gpio.c + 1 + ..\libraries\Drivers\drv_gpio.c + + + drv_usart.c + 1 + ..\libraries\Drivers\drv_usart.c + + + + + Finsh + + + cmd.c + 1 + ..\..\..\components\finsh\cmd.c + + + msh_parse.c + 1 + ..\..\..\components\finsh\msh_parse.c + + + shell.c + 1 + ..\..\..\components\finsh\shell.c + + + msh.c + 1 + ..\..\..\components\finsh\msh.c + + + + + Kernel + + + clock.c + 1 + ..\..\..\src\clock.c + + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + __RT_KERNEL_SOURCE__ + + + + + + + + + components.c + 1 + ..\..\..\src\components.c + + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + __RT_KERNEL_SOURCE__ + + + + + + + + + cpu_up.c + 1 + ..\..\..\src\cpu_up.c + + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + __RT_KERNEL_SOURCE__ + + + + + + + + + defunct.c + 1 + ..\..\..\src\defunct.c + + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + __RT_KERNEL_SOURCE__ + + + + + + + + + idle.c + 1 + ..\..\..\src\idle.c + + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + __RT_KERNEL_SOURCE__ + + + + + + + + + ipc.c + 1 + ..\..\..\src\ipc.c + + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + __RT_KERNEL_SOURCE__ + + + + + + + + + irq.c + 1 + ..\..\..\src\irq.c + + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + __RT_KERNEL_SOURCE__ + + + + + + + + + kservice.c + 1 + ..\..\..\src\kservice.c + + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + __RT_KERNEL_SOURCE__ + + + + + + + + + mem.c + 1 + ..\..\..\src\mem.c + + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + __RT_KERNEL_SOURCE__ + + + + + + + + + mempool.c + 1 + ..\..\..\src\mempool.c + + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + __RT_KERNEL_SOURCE__ + + + + + + + + + object.c + 1 + ..\..\..\src\object.c + + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + __RT_KERNEL_SOURCE__ + + + + + + + + + scheduler_comm.c + 1 + ..\..\..\src\scheduler_comm.c + + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + __RT_KERNEL_SOURCE__ + + + + + + + + + scheduler_up.c + 1 + ..\..\..\src\scheduler_up.c + + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + __RT_KERNEL_SOURCE__ + + + + + + + + + thread.c + 1 + ..\..\..\src\thread.c + + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + __RT_KERNEL_SOURCE__ + + + + + + + + + timer.c + 1 + ..\..\..\src\timer.c + + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + __RT_KERNEL_SOURCE__ + + + + + + + + + + + klibc + + + kstring.c + 1 + ..\..\..\src\klibc\kstring.c + + + kerrno.c + 1 + ..\..\..\src\klibc\kerrno.c + + + rt_vsnprintf_tiny.c + 1 + ..\..\..\src\klibc\rt_vsnprintf_tiny.c + + + rt_vsscanf.c + 1 + ..\..\..\src\klibc\rt_vsscanf.c + + + kstdio.c + 1 + ..\..\..\src\klibc\kstdio.c + + + + + libcpu + + + div0.c + 1 + ..\..\..\libcpu\arm\common\div0.c + + + showmem.c + 1 + ..\..\..\libcpu\arm\common\showmem.c + + + context_rvds.S + 2 + ..\..\..\libcpu\arm\cortex-m4\context_rvds.S + + + cpuport.c + 1 + ..\..\..\libcpu\arm\cortex-m4\cpuport.c + + + + + Libraries + + + ft32f4xx_adc.c + 1 + ..\libraries\FT32F4xx\FT32F4xx_Driver\src\ft32f4xx_adc.c + + + ft32f4xx_comp.c + 1 + ..\libraries\FT32F4xx\FT32F4xx_Driver\src\ft32f4xx_comp.c + + + ft32f4xx_crc.c + 1 + ..\libraries\FT32F4xx\FT32F4xx_Driver\src\ft32f4xx_crc.c + + + ft32f4xx_crs.c + 1 + ..\libraries\FT32F4xx\FT32F4xx_Driver\src\ft32f4xx_crs.c + + + ft32f4xx_dac.c + 1 + ..\libraries\FT32F4xx\FT32F4xx_Driver\src\ft32f4xx_dac.c + + + ft32f4xx_debug.c + 1 + ..\libraries\FT32F4xx\FT32F4xx_Driver\src\ft32f4xx_debug.c + + + ft32f4xx_dma.c + 1 + ..\libraries\FT32F4xx\FT32F4xx_Driver\src\ft32f4xx_dma.c + + + ft32f4xx_ecap.c + 1 + ..\libraries\FT32F4xx\FT32F4xx_Driver\src\ft32f4xx_ecap.c + + + ft32f4xx_epwm.c + 1 + ..\libraries\FT32F4xx\FT32F4xx_Driver\src\ft32f4xx_epwm.c + + + ft32f4xx_eqep.c + 1 + ..\libraries\FT32F4xx\FT32F4xx_Driver\src\ft32f4xx_eqep.c + + + ft32f4xx_eth.c + 1 + ..\libraries\FT32F4xx\FT32F4xx_Driver\src\ft32f4xx_eth.c + + + ft32f4xx_exti.c + 1 + ..\libraries\FT32F4xx\FT32F4xx_Driver\src\ft32f4xx_exti.c + + + ft32f4xx_fdcan.c + 1 + ..\libraries\FT32F4xx\FT32F4xx_Driver\src\ft32f4xx_fdcan.c + + + ft32f4xx_flash.c + 1 + ..\libraries\FT32F4xx\FT32F4xx_Driver\src\ft32f4xx_flash.c + + + ft32f4xx_fmc.c + 1 + ..\libraries\FT32F4xx\FT32F4xx_Driver\src\ft32f4xx_fmc.c + + + ft32f4xx_gpio.c + 1 + ..\libraries\FT32F4xx\FT32F4xx_Driver\src\ft32f4xx_gpio.c + + + ft32f4xx_i2c.c + 1 + ..\libraries\FT32F4xx\FT32F4xx_Driver\src\ft32f4xx_i2c.c + + + ft32f4xx_i2s.c + 1 + ..\libraries\FT32F4xx\FT32F4xx_Driver\src\ft32f4xx_i2s.c + + + ft32f4xx_iwdg.c + 1 + ..\libraries\FT32F4xx\FT32F4xx_Driver\src\ft32f4xx_iwdg.c + + + ft32f4xx_lptim.c + 1 + ..\libraries\FT32F4xx\FT32F4xx_Driver\src\ft32f4xx_lptim.c + + + ft32f4xx_misc.c + 1 + ..\libraries\FT32F4xx\FT32F4xx_Driver\src\ft32f4xx_misc.c + + + ft32f4xx_opamp.c + 1 + ..\libraries\FT32F4xx\FT32F4xx_Driver\src\ft32f4xx_opamp.c + + + ft32f4xx_pwr.c + 1 + ..\libraries\FT32F4xx\FT32F4xx_Driver\src\ft32f4xx_pwr.c + + + ft32f4xx_qspi.c + 1 + ..\libraries\FT32F4xx\FT32F4xx_Driver\src\ft32f4xx_qspi.c + + + ft32f4xx_rcc.c + 1 + ..\libraries\FT32F4xx\FT32F4xx_Driver\src\ft32f4xx_rcc.c + + + ft32f4xx_rng.c + 1 + ..\libraries\FT32F4xx\FT32F4xx_Driver\src\ft32f4xx_rng.c + + + ft32f4xx_rtc.c + 1 + ..\libraries\FT32F4xx\FT32F4xx_Driver\src\ft32f4xx_rtc.c + + + ft32f4xx_sdio.c + 1 + ..\libraries\FT32F4xx\FT32F4xx_Driver\src\ft32f4xx_sdio.c + + + ft32f4xx_spdif.c + 1 + ..\libraries\FT32F4xx\FT32F4xx_Driver\src\ft32f4xx_spdif.c + + + ft32f4xx_spi.c + 1 + ..\libraries\FT32F4xx\FT32F4xx_Driver\src\ft32f4xx_spi.c + + + ft32f4xx_ssi.c + 1 + ..\libraries\FT32F4xx\FT32F4xx_Driver\src\ft32f4xx_ssi.c + + + ft32f4xx_syscfg.c + 1 + ..\libraries\FT32F4xx\FT32F4xx_Driver\src\ft32f4xx_syscfg.c + + + ft32f4xx_tim.c + 1 + ..\libraries\FT32F4xx\FT32F4xx_Driver\src\ft32f4xx_tim.c + + + ft32f4xx_uart.c + 1 + ..\libraries\FT32F4xx\FT32F4xx_Driver\src\ft32f4xx_uart.c + + + ft32f4xx_usart.c + 1 + ..\libraries\FT32F4xx\FT32F4xx_Driver\src\ft32f4xx_usart.c + + + ft32f4xx_wwdg.c + 1 + ..\libraries\FT32F4xx\FT32F4xx_Driver\src\ft32f4xx_wwdg.c + + + system_ft32f4xx.c + 1 + ..\libraries\FT32F4xx\CMSIS\FT32F4xx\source\system_ft32f4xx.c + + + + + + + + + + + + + + + + + project + 1 + + + + + diff --git a/bsp/ft32/ft32f407xe-starter/rtconfig.h b/bsp/ft32/ft32f407xe-starter/rtconfig.h new file mode 100644 index 00000000000..9980e867b26 --- /dev/null +++ b/bsp/ft32/ft32f407xe-starter/rtconfig.h @@ -0,0 +1,418 @@ +#ifndef RT_CONFIG_H__ +#define RT_CONFIG_H__ + +/* RT-Thread Kernel */ + +/* klibc options */ + +/* rt_vsnprintf options */ + +/* end of rt_vsnprintf options */ + +/* rt_vsscanf options */ + +/* end of rt_vsscanf options */ + +/* rt_memset options */ + +/* end of rt_memset options */ + +/* rt_memcpy options */ + +/* end of rt_memcpy options */ + +/* rt_memmove options */ + +/* end of rt_memmove options */ + +/* rt_memcmp options */ + +/* end of rt_memcmp options */ + +/* rt_strstr options */ + +/* end of rt_strstr options */ + +/* rt_strcasecmp options */ + +/* end of rt_strcasecmp options */ + +/* rt_strncpy options */ + +/* end of rt_strncpy options */ + +/* rt_strcpy options */ + +/* end of rt_strcpy options */ + +/* rt_strncmp options */ + +/* end of rt_strncmp options */ + +/* rt_strcmp options */ + +/* end of rt_strcmp options */ + +/* rt_strlen options */ + +/* end of rt_strlen options */ + +/* rt_strnlen options */ + +/* end of rt_strnlen options */ +/* end of klibc options */ +#define RT_NAME_MAX 12 +#define RT_CPUS_NR 1 +#define RT_ALIGN_SIZE 8 +#define RT_THREAD_PRIORITY_32 +#define RT_THREAD_PRIORITY_MAX 32 +#define RT_TICK_PER_SECOND 1000 +#define RT_USING_OVERFLOW_CHECK +#define RT_USING_HOOK +#define RT_HOOK_USING_FUNC_PTR +#define RT_USING_IDLE_HOOK +#define RT_IDLE_HOOK_LIST_SIZE 4 +#define IDLE_THREAD_STACK_SIZE 256 + +/* kservice options */ + +/* end of kservice options */ +#define RT_USING_DEBUG +#define RT_DEBUGING_ASSERT +#define RT_DEBUGING_COLOR +#define RT_DEBUGING_CONTEXT + +/* Inter-Thread communication */ + +#define RT_USING_SEMAPHORE +#define RT_USING_MUTEX +#define RT_USING_EVENT +#define RT_USING_MAILBOX +#define RT_USING_MESSAGEQUEUE +/* end of Inter-Thread communication */ + +/* Memory Management */ + +#define RT_USING_MEMPOOL +#define RT_USING_SMALL_MEM +#define RT_USING_SMALL_MEM_AS_HEAP +#define RT_USING_HEAP +/* end of Memory Management */ +#define RT_USING_DEVICE +#define RT_USING_CONSOLE +#define RT_CONSOLEBUF_SIZE 128 +#define RT_CONSOLE_DEVICE_NAME "uart2" +#define RT_VER_NUM 0x50201 +#define RT_BACKTRACE_LEVEL_MAX_NR 32 +/* end of RT-Thread Kernel */ +#define ARCH_ARM +#define ARCH_ARM_CORTEX_M +#define ARCH_ARM_CORTEX_M0 + +/* RT-Thread Components */ + +#define RT_USING_COMPONENTS_INIT +#define RT_USING_USER_MAIN +#define RT_MAIN_THREAD_STACK_SIZE 2048 +#define RT_MAIN_THREAD_PRIORITY 10 +#define RT_USING_MSH +#define RT_USING_FINSH +#define FINSH_USING_MSH +#define FINSH_THREAD_NAME "tshell" +#define FINSH_THREAD_PRIORITY 20 +#define FINSH_THREAD_STACK_SIZE 4096 +#define FINSH_USING_HISTORY +#define FINSH_HISTORY_LINES 5 +#define FINSH_USING_SYMTAB +#define FINSH_CMD_SIZE 80 +#define MSH_USING_BUILT_IN_COMMANDS +#define FINSH_USING_DESCRIPTION +#define FINSH_ARG_MAX 10 +#define FINSH_USING_OPTION_COMPLETION + +/* DFS: device virtual file system */ + +/* end of DFS: device virtual file system */ + +/* Device Drivers */ + +#define RT_USING_DEVICE_IPC +#define RT_UNAMED_PIPE_NUMBER 64 +#define RT_USING_SERIAL +#define RT_USING_SERIAL_V1 +#define RT_SERIAL_RB_BUFSZ 64 +#define RT_USING_PIN +/* end of Device Drivers */ + +/* C/C++ and POSIX layer */ + +/* ISO-ANSI C layer */ + +/* Timezone and Daylight Saving Time */ + +#define RT_LIBC_USING_LIGHT_TZ_DST +#define RT_LIBC_TZ_DEFAULT_HOUR 8 +#define RT_LIBC_TZ_DEFAULT_MIN 0 +#define RT_LIBC_TZ_DEFAULT_SEC 0 +/* end of Timezone and Daylight Saving Time */ +/* end of ISO-ANSI C layer */ + +/* POSIX (Portable Operating System Interface) layer */ + + +/* Interprocess Communication (IPC) */ + + +/* Socket is in the 'Network' category */ + +/* end of Interprocess Communication (IPC) */ +/* end of POSIX (Portable Operating System Interface) layer */ +/* end of C/C++ and POSIX layer */ + +/* Network */ + +/* end of Network */ + +/* Memory protection */ + +/* end of Memory protection */ + +/* Utilities */ + +/* end of Utilities */ + +/* Using USB legacy version */ + +/* end of Using USB legacy version */ +/* end of RT-Thread Components */ + +/* RT-Thread Utestcases */ + +/* end of RT-Thread Utestcases */ + +/* RT-Thread online packages */ + +/* IoT - internet of things */ + + +/* Wi-Fi */ + +/* Marvell WiFi */ + +/* end of Marvell WiFi */ + +/* Wiced WiFi */ + +/* end of Wiced WiFi */ + +/* CYW43012 WiFi */ + +/* end of CYW43012 WiFi */ + +/* BL808 WiFi */ + +/* end of BL808 WiFi */ + +/* CYW43439 WiFi */ + +/* end of CYW43439 WiFi */ +/* end of Wi-Fi */ + +/* IoT Cloud */ + +/* end of IoT Cloud */ +/* end of IoT - internet of things */ + +/* security packages */ + +/* end of security packages */ + +/* language packages */ + +/* JSON: JavaScript Object Notation, a lightweight data-interchange format */ + +/* end of JSON: JavaScript Object Notation, a lightweight data-interchange format */ + +/* XML: Extensible Markup Language */ + +/* end of XML: Extensible Markup Language */ +/* end of language packages */ + +/* multimedia packages */ + +/* LVGL: powerful and easy-to-use embedded GUI library */ + +/* end of LVGL: powerful and easy-to-use embedded GUI library */ + +/* u8g2: a monochrome graphic library */ + +/* end of u8g2: a monochrome graphic library */ +/* end of multimedia packages */ + +/* tools packages */ + +/* end of tools packages */ + +/* system packages */ + +/* enhanced kernel services */ + +/* end of enhanced kernel services */ + +/* acceleration: Assembly language or algorithmic acceleration packages */ + +/* end of acceleration: Assembly language or algorithmic acceleration packages */ + +/* CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */ + +#define PKG_USING_CMSIS_CORE +#define PKG_USING_CMSIS_CORE_LATEST_VERSION +/* end of CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */ + +/* Micrium: Micrium software products porting for RT-Thread */ + +/* end of Micrium: Micrium software products porting for RT-Thread */ +/* end of system packages */ + +/* peripheral libraries and drivers */ + +/* HAL & SDK Drivers */ + +/* STM32 HAL & SDK Drivers */ + +/* end of STM32 HAL & SDK Drivers */ + +/* Infineon HAL Packages */ + +/* end of Infineon HAL Packages */ + +/* Kendryte SDK */ + +/* end of Kendryte SDK */ + +/* WCH HAL & SDK Drivers */ + +/* end of WCH HAL & SDK Drivers */ + +/* AT32 HAL & SDK Drivers */ + +/* end of AT32 HAL & SDK Drivers */ + +/* HC32 DDL Drivers */ + +/* end of HC32 DDL Drivers */ + +/* NXP HAL & SDK Drivers */ + +/* end of NXP HAL & SDK Drivers */ + +/* NUVOTON Drivers */ + +/* end of NUVOTON Drivers */ + +/* GD32 Drivers */ + +/* end of GD32 Drivers */ +/* end of HAL & SDK Drivers */ + +/* sensors drivers */ + +/* end of sensors drivers */ + +/* touch drivers */ + +/* end of touch drivers */ +/* end of peripheral libraries and drivers */ + +/* AI packages */ + +/* end of AI packages */ + +/* Signal Processing and Control Algorithm Packages */ + +/* end of Signal Processing and Control Algorithm Packages */ + +/* miscellaneous packages */ + +/* project laboratory */ + +/* end of project laboratory */ + +/* samples: kernel and components samples */ + +/* end of samples: kernel and components samples */ + +/* entertainment: terminal games and other interesting software packages */ + +/* end of entertainment: terminal games and other interesting software packages */ +/* end of miscellaneous packages */ + +/* Arduino libraries */ + + +/* Projects and Demos */ + +/* end of Projects and Demos */ + +/* Sensors */ + +/* end of Sensors */ + +/* Display */ + +/* end of Display */ + +/* Timing */ + +/* end of Timing */ + +/* Data Processing */ + +/* end of Data Processing */ + +/* Data Storage */ + +/* Communication */ + +/* end of Communication */ + +/* Device Control */ + +/* end of Device Control */ + +/* Other */ +#define PKG_USING_FT32F4_STD_DRIVER +#define PKG_USING_FT32F4_STD_DRIVER_LATEST_VERSION +#define PKG_USING_FT32F4_CMSIS_DRIVER +#define PKG_USING_FT32F4_CMSIS_DRIVER_LATEST_VERSION +/* end of Other */ + +/* Signal IO */ + +/* end of Signal IO */ + +/* Uncategorized */ + +/* end of Arduino libraries */ +/* end of RT-Thread online packages */ +#define SOC_FAMILY_FT32 +#define SOC_SERIES_FT32F4 + +/* Hardware Drivers Config */ + +#define SOC_FT32F407VE + +/* Onboard Peripheral Drivers */ + +/* On-chip Peripheral Drivers */ + +#define BSP_USING_GPIO +#define BSP_USING_UART2 + +/* end of On-chip Peripheral Drivers */ + +/* Board extended module Drivers */ + +/* end of Hardware Drivers Config */ + +#endif diff --git a/bsp/ft32/ft32f407xe-starter/rtconfig.py b/bsp/ft32/ft32f407xe-starter/rtconfig.py new file mode 100644 index 00000000000..5ad587f65a2 --- /dev/null +++ b/bsp/ft32/ft32f407xe-starter/rtconfig.py @@ -0,0 +1,185 @@ +import os + +# toolchains options +ARCH='arm' +CPU='cortex-m4' +CROSS_TOOL='gcc' + +# bsp lib config +BSP_LIBRARY_TYPE = None + +if os.getenv('RTT_CC'): + CROSS_TOOL = os.getenv('RTT_CC') +if os.getenv('RTT_ROOT'): + RTT_ROOT = os.getenv('RTT_ROOT') + +# cross_tool provides the cross compiler +# EXEC_PATH is the compiler execute path, for example, CodeSourcery, Keil MDK, IAR +if CROSS_TOOL == 'gcc': + PLATFORM = 'gcc' + EXEC_PATH = r'C:\Users\XXYYZZ' +elif CROSS_TOOL == 'keil': + PLATFORM = 'armcc' + EXEC_PATH = r'C:/Keil_v5' +elif CROSS_TOOL == 'iar': + PLATFORM = 'iccarm' + EXEC_PATH = r'C:/Program Files (x86)/IAR Systems/Embedded Workbench 8.3' + +if os.getenv('RTT_EXEC_PATH'): + EXEC_PATH = os.getenv('RTT_EXEC_PATH') + +BUILD = 'debug' + +if PLATFORM == 'gcc': + # toolchains + PREFIX = 'arm-none-eabi-' + CC = PREFIX + 'gcc' + AS = PREFIX + 'gcc' + AR = PREFIX + 'ar' + CXX = PREFIX + 'g++' + LINK = PREFIX + 'gcc' + TARGET_EXT = 'elf' + SIZE = PREFIX + 'size' + OBJDUMP = PREFIX + 'objdump' + OBJCPY = PREFIX + 'objcopy' + + DEVICE = ' -mcpu=cortex-m4 -mthumb -ffunction-sections -fdata-sections' + CFLAGS = DEVICE + ' -Dgcc' + AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -Wa,-mimplicit-it=thumb ' + LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rt-thread.map,-cref,-u,Reset_Handler -T board/linker_scripts/link.lds' + + CPATH = '' + LPATH = '' + + if BUILD == 'debug': + CFLAGS += ' -O0 -gdwarf-2 -g' + AFLAGS += ' -gdwarf-2' + else: + CFLAGS += ' -O2' + + CXXFLAGS = CFLAGS + + POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n' + +elif PLATFORM == 'armcc': + # toolchains + CC = 'armcc' + CXX = 'armcc' + AS = 'armasm' + AR = 'armar' + LINK = 'armlink' + TARGET_EXT = 'axf' + + DEVICE = ' --cpu Cortex-M4 ' + CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99' + AFLAGS = DEVICE + ' --apcs=interwork ' + LFLAGS = DEVICE + ' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rt-thread.map --strict' + CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include' + LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib' + + CFLAGS += ' -D__MICROLIB ' + AFLAGS += ' --pd "__MICROLIB SETA 1" ' + LFLAGS += ' --library_type=microlib ' + EXEC_PATH += '/ARM/ARMCC/bin/' + + if BUILD == 'debug': + CFLAGS += ' -g -O0' + AFLAGS += ' -g' + else: + CFLAGS += ' -O2' + + CXXFLAGS = CFLAGS + CFLAGS += ' -std=c99' + + POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET' + +elif PLATFORM == 'armclang': + # toolchains + CC = 'armclang' + CXX = 'armclang' + AS = 'armasm' + AR = 'armar' + LINK = 'armlink' + TARGET_EXT = 'axf' + + DEVICE = ' --cpu Cortex-M4 ' + CFLAGS = ' --target=arm-arm-none-eabi -mcpu=cortex-m4 ' + CFLAGS += ' -mcpu=cortex-m4 ' + CFLAGS += ' -c -fno-rtti -funsigned-char -fshort-enums -fshort-wchar ' + CFLAGS += ' -gdwarf-3 -ffunction-sections ' + AFLAGS = DEVICE + ' --apcs=interwork ' + LFLAGS = DEVICE + ' --info sizes --info totals --info unused --info veneers ' + LFLAGS += ' --list rt-thread.map ' + LFLAGS += r' --strict --scatter "board\linker_scripts\link.sct" ' + CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCLANG/include' + LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCLANG/lib' + + EXEC_PATH += '/ARM/ARMCLANG/bin/' + + if BUILD == 'debug': + CFLAGS += ' -g -O1' # armclang recommend + AFLAGS += ' -g' + else: + CFLAGS += ' -O2' + + CXXFLAGS = CFLAGS + CFLAGS += ' -std=c99' + + POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET' + +elif PLATFORM == 'iccarm': + # toolchains + CC = 'iccarm' + CXX = 'iccarm' + AS = 'iasmarm' + AR = 'iarchive' + LINK = 'ilinkarm' + TARGET_EXT = 'out' + + DEVICE = '-Dewarm' + + CFLAGS = DEVICE + CFLAGS += ' --diag_suppress Pa050' + CFLAGS += ' --no_cse' + CFLAGS += ' --no_unroll' + CFLAGS += ' --no_inline' + CFLAGS += ' --no_code_motion' + CFLAGS += ' --no_tbaa' + CFLAGS += ' --no_clustering' + CFLAGS += ' --no_scheduling' + CFLAGS += ' --endian=little' + CFLAGS += ' --cpu=Cortex-M4' + CFLAGS += ' -e' + CFLAGS += ' --fpu=None' + CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"' + CFLAGS += ' --silent' + + AFLAGS = DEVICE + AFLAGS += ' -s+' + AFLAGS += ' -w+' + AFLAGS += ' -r' + AFLAGS += ' --cpu Cortex-M4' + AFLAGS += ' --fpu None' + AFLAGS += ' -S' + + if BUILD == 'debug': + CFLAGS += ' --debug' + CFLAGS += ' -On' + else: + CFLAGS += ' -Oh' + + LFLAGS = ' --config "board/linker_scripts/link.icf"' + LFLAGS += ' --entry __iar_program_start' + + CXXFLAGS = CFLAGS + + EXEC_PATH = EXEC_PATH + '/arm/bin/' + POST_ACTION = 'ielftool --bin $TARGET rtthread.bin' + +def dist_handle(BSP_ROOT, dist_dir): + import sys + cwd_path = os.getcwd() + sys.path.append(os.path.join(os.path.dirname(BSP_ROOT), 'tools')) + from sdk_dist import dist_do_building + dist_do_building(BSP_ROOT, dist_dir) + diff --git a/bsp/ft32/ft32f407xe-starter/template.uvprojx b/bsp/ft32/ft32f407xe-starter/template.uvprojx new file mode 100644 index 00000000000..695d59daa2b --- /dev/null +++ b/bsp/ft32/ft32f407xe-starter/template.uvprojx @@ -0,0 +1,397 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + rt-thread + 0x4 + ARM-ADS + 5060528::V5.06 update 5 (build 528)::.\ARMCC + 0 + + + FT32F407VEA2 + FMD + FMD.FT32F4xx_DFP.1.0.0 + https://www.fremontmicro.com/upload/tools/pack/ + IRAM(0x20000000,0x00020000) IRAM2(0x10000000,0x00010000) IROM(0x08000000,0x00080000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0FT32F4xx_512 -FS08000000 -FL080000 -FP0($$Device:FT32F407VEA2$Flash\FT32F4xx_512.FLM)) + 0 + + + + + + + + + + + $$Device:FT32F407VEA2$SVD\FT32F407x.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\build\keil\Obj\ + rt-thread + 1 + 0 + 0 + 1 + 0 + .\build\keil\List\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 1 + 0 + fromelf --bin !L --output rtthread.bin + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -REMAP -MPU + DCM.DLL + -pCM4 + SARMCM3.DLL + -MPU + TCM.DLL + -pCM4 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M4" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 2 + 0 + 0 + 0 + 1 + 0 + 8 + 0 + 0 + 0 + 0 + 3 + 4 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x20000 + + + 1 + 0x8000000 + 0x80000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x8000000 + 0x80000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x20000 + + + 0 + 0x10000000 + 0x10000 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 4 + + + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x08000000 + 0x20000000 + + .\board\linker_scripts\link.sct + + + + + + + + + + + Source Group 1 + + + + + + + + + + + + diff --git a/bsp/ft32/libraries/Drivers/drv_config.h b/bsp/ft32/libraries/Drivers/drv_config.h index 8b0c854f8ab..eca48e4f5c4 100644 --- a/bsp/ft32/libraries/Drivers/drv_config.h +++ b/bsp/ft32/libraries/Drivers/drv_config.h @@ -23,6 +23,11 @@ extern "C" { #include "uart_config.h" #endif +#if defined(SOC_SERIES_FT32F4) +#include "dma_config.h" +#include "uart_config.h" +#endif + #ifdef __cplusplus } #endif diff --git a/bsp/ft32/libraries/Drivers/drv_dma.h b/bsp/ft32/libraries/Drivers/drv_dma.h index fe455f958f7..cc1e39c6c91 100644 --- a/bsp/ft32/libraries/Drivers/drv_dma.h +++ b/bsp/ft32/libraries/Drivers/drv_dma.h @@ -22,6 +22,10 @@ extern "C" { #define DMA_INSTANCE_TYPE DMA_Channel_TypeDef #endif +#if defined(SOC_SERIES_FT32F4) +#define DMA_INSTANCE_TYPE DMA_Channel_TypeDef +#endif + struct dma_config { DMA_INSTANCE_TYPE *Instance; rt_uint32_t dma_rcc; diff --git a/bsp/ft32/libraries/Drivers/drv_gpio.c b/bsp/ft32/libraries/Drivers/drv_gpio.c index 479294a3d03..94b03b5c651 100644 --- a/bsp/ft32/libraries/Drivers/drv_gpio.c +++ b/bsp/ft32/libraries/Drivers/drv_gpio.c @@ -6,6 +6,7 @@ * Change Logs: * Date Author Notes * 2022-03-02 FMD-AE first version + * 2025-12-31 FMD-AE add ft32f4 support */ #include @@ -59,6 +60,24 @@ static const struct pin_irq_map pin_irq_map[] = {GPIO_Pin_14, EXTI4_15_IRQn}, {GPIO_Pin_15, EXTI4_15_IRQn}, #endif +#if defined(SOC_SERIES_FT32F4) + {GPIO_Pin_0, EXTI0_IRQn}, + {GPIO_Pin_1, EXTI1_IRQn}, + {GPIO_Pin_2, EXTI2_IRQn}, + {GPIO_Pin_3, EXTI3_IRQn}, + {GPIO_Pin_4, EXTI4_IRQn}, + {GPIO_Pin_5, EXTI9_5_IRQn}, + {GPIO_Pin_6, EXTI9_5_IRQn}, + {GPIO_Pin_7, EXTI9_5_IRQn}, + {GPIO_Pin_8, EXTI9_5_IRQn}, + {GPIO_Pin_9, EXTI9_5_IRQn}, + {GPIO_Pin_10, EXTI15_10_IRQn}, + {GPIO_Pin_11, EXTI15_10_IRQn}, + {GPIO_Pin_12, EXTI15_10_IRQn}, + {GPIO_Pin_13, EXTI15_10_IRQn}, + {GPIO_Pin_14, EXTI15_10_IRQn}, + {GPIO_Pin_15, EXTI15_10_IRQn}, +#endif }; static struct rt_pin_irq_hdr pin_irq_hdr_tab[] = @@ -339,12 +358,18 @@ static void rt_gpio_deinit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin) /* Deactivate the Pull-up and Pull-down resistor for the current IO */ GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPDR0 << (position * 2u)); +#if defined (SOC_SERIES_FT32F0) /* Configure the default value IO Output Type */ GPIOx->OTYPER &= ~(GPIO_OTYPER_OT_0 << position) ; - /* Configure the default value for IO Speed */ GPIOx->OSPEEDR &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2u)); - +#endif +#if defined (SOC_SERIES_FT32F4) + /* Configure the default value IO Output Type */ + GPIOx->OTYPER &= ~(GPIO_OTYPER_OT0 << position) ; + /* Configure the default value for IO Speed */ + GPIOx->OSPEEDR &= ~(GPIO_OSPEEDR_OSPEEDR0 << (position * 2u)); +#endif } position++; @@ -416,6 +441,7 @@ static rt_err_t ft32_pin_irq_enable(struct rt_device *device, rt_base_t pin, break; } GPIO_Init(PIN_FTPORT(pin), &GPIO_InitStruct); + EXTI_Init(&EXTI_InitStructure); NVIC_SetPriority(irqmap->irqno, 5); @@ -438,7 +464,6 @@ static rt_err_t ft32_pin_irq_enable(struct rt_device *device, rt_base_t pin, pin_irq_enable_mask &= ~irqmap->pinbit; - #if defined(SOC_SERIES_FT32F0) if ((irqmap->pinbit >= GPIO_Pin_0) && (irqmap->pinbit <= GPIO_Pin_1)) { @@ -467,6 +492,26 @@ static rt_err_t ft32_pin_irq_enable(struct rt_device *device, rt_base_t pin, NVIC_DisableIRQ(irqmap->irqno); } +#endif +#if defined(SOC_SERIES_FT32F4) + if ((irqmap->pinbit >= GPIO_Pin_5) && (irqmap->pinbit <= GPIO_Pin_9)) + { + if (!(pin_irq_enable_mask & (GPIO_Pin_5 | GPIO_Pin_6 | GPIO_Pin_7 | GPIO_Pin_8 | GPIO_Pin_9))) + { + NVIC_DisableIRQ(irqmap->irqno); + } + } + else if ((irqmap->pinbit >= GPIO_Pin_10) && (irqmap->pinbit <= GPIO_Pin_15)) + { + if (!(pin_irq_enable_mask & (GPIO_Pin_10 | GPIO_Pin_11 | GPIO_Pin_12 | GPIO_Pin_13 | GPIO_Pin_14 | GPIO_Pin_15))) + { + NVIC_DisableIRQ(irqmap->irqno); + } + } + else + { + NVIC_DisableIRQ(irqmap->irqno); + } #endif rt_hw_interrupt_enable(level); } @@ -546,15 +591,84 @@ void EXTI4_15_IRQHandler(void) rt_interrupt_leave(); } #endif +#if defined(SOC_SERIES_FT32F4) +void EXTI0_Handler(void) +{ + rt_interrupt_enter(); + GPIO_EXTI_IRQHandler(GPIO_Pin_0); + rt_interrupt_leave(); +} + +void EXTI1_Handler(void) +{ + rt_interrupt_enter(); + GPIO_EXTI_IRQHandler(GPIO_Pin_1); + rt_interrupt_leave(); +} + +void EXTI2_Handler(void) +{ + rt_interrupt_enter(); + GPIO_EXTI_IRQHandler(GPIO_Pin_2); + rt_interrupt_leave(); +} + +void EXTI3_Handler(void) +{ + rt_interrupt_enter(); + GPIO_EXTI_IRQHandler(GPIO_Pin_3); + rt_interrupt_leave(); +} + +void EXTI4_Handler(void) +{ + rt_interrupt_enter(); + GPIO_EXTI_IRQHandler(GPIO_Pin_4); + rt_interrupt_leave(); +} + +void EXTI5_9_Handler(void) +{ + rt_interrupt_enter(); + GPIO_EXTI_IRQHandler(GPIO_Pin_5); + GPIO_EXTI_IRQHandler(GPIO_Pin_6); + GPIO_EXTI_IRQHandler(GPIO_Pin_7); + GPIO_EXTI_IRQHandler(GPIO_Pin_8); + GPIO_EXTI_IRQHandler(GPIO_Pin_9); + rt_interrupt_leave(); +} + +void EXTI10_15_Handler(void) +{ + rt_interrupt_enter(); + GPIO_EXTI_IRQHandler(GPIO_Pin_10); + GPIO_EXTI_IRQHandler(GPIO_Pin_11); + GPIO_EXTI_IRQHandler(GPIO_Pin_12); + GPIO_EXTI_IRQHandler(GPIO_Pin_13); + GPIO_EXTI_IRQHandler(GPIO_Pin_14); + GPIO_EXTI_IRQHandler(GPIO_Pin_15); + rt_interrupt_leave(); +} +#endif int rt_hw_pin_init(void) { +#if defined(SOC_SERIES_FT32F0) RCC_AHBPeriphClockCmd(RCC_AHBPeriph_GPIOA, ENABLE); RCC_AHBPeriphClockCmd(RCC_AHBPeriph_GPIOB, ENABLE); RCC_AHBPeriphClockCmd(RCC_AHBPeriph_GPIOC, ENABLE); RCC_AHBPeriphClockCmd(RCC_AHBPeriph_GPIOD, ENABLE); RCC_AHBPeriphClockCmd(RCC_AHBPeriph_GPIOF, ENABLE); return rt_device_pin_register("pin", &_ft32_pin_ops, RT_NULL); +#endif +#if defined(SOC_SERIES_FT32F4) + RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOA, ENABLE); + RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOB, ENABLE); + RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOC, ENABLE); + RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOD, ENABLE); + RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOE, ENABLE); + return rt_device_pin_register("pin", &_ft32_pin_ops, RT_NULL); +#endif } #endif /* RT_USING_PIN */ diff --git a/bsp/ft32/libraries/Drivers/drv_gpio.h b/bsp/ft32/libraries/Drivers/drv_gpio.h index c571f35bea3..4e124e45f51 100644 --- a/bsp/ft32/libraries/Drivers/drv_gpio.h +++ b/bsp/ft32/libraries/Drivers/drv_gpio.h @@ -6,6 +6,7 @@ * Change Logs: * Date Author Notes * 2022-03-02 FMD-AE first version + * 2025-12-31 FMD-AE add ft32f4 support */ #ifndef __DRV_GPIO_H__ @@ -17,11 +18,21 @@ extern "C" { #endif +#if defined(SOC_SERIES_FT32F0) #define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0U :\ ((__GPIOx__) == (GPIOB))? 1U :\ ((__GPIOx__) == (GPIOC))? 2U :\ ((__GPIOx__) == (GPIOD))? 3U :\ ((__GPIOx__) == (GPIOF))? 5U : 4U) +#elif defined(SOC_SERIES_FT32F4) +#define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0U :\ + ((__GPIOx__) == (GPIOB))? 1U :\ + ((__GPIOx__) == (GPIOC))? 2U :\ + ((__GPIOx__) == (GPIOD))? 3U :\ + ((__GPIOx__) == (GPIOE))? 4U : 5U) +#else +#error "Unsupported SOC series" +#endif #define __GPIO_EXTI_GET_IT(__EXTI_LINE__) (EXTI->PR & (__EXTI_LINE__)) diff --git a/bsp/ft32/libraries/Drivers/drv_usart.c b/bsp/ft32/libraries/Drivers/drv_usart.c index 5cbd353ea02..a31d27fae78 100644 --- a/bsp/ft32/libraries/Drivers/drv_usart.c +++ b/bsp/ft32/libraries/Drivers/drv_usart.c @@ -23,10 +23,6 @@ /* this driver can be disabled at menuconfig -> RT-Thread Components -> Device Drivers */ #endif -#ifdef RT_SERIAL_USING_DMA - static void ft32_dma_config(struct rt_serial_device *serial, rt_ubase_t flag); -#endif - enum { #ifdef BSP_USING_UART1 @@ -54,7 +50,12 @@ void UART_MspInit(USART_TypeDef *USARTx) GPIO_InitTypeDef GPIO_InitStruct; if (USARTx == USART1) { +#if defined(SOC_SERIES_FT32F0) RCC_AHBPeriphClockCmd(RCC_AHBPeriph_GPIOA, ENABLE); +#endif +#if defined(SOC_SERIES_FT32F4) + RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOA, ENABLE); +#endif RCC_APB2PeriphClockCmd(RCC_APB2Periph_USART1, ENABLE); /*GPIO INIT*/ @@ -64,17 +65,28 @@ void UART_MspInit(USART_TypeDef *USARTx) GPIO_InitStruct.GPIO_OType = GPIO_OType_PP; GPIO_InitStruct.GPIO_PuPd = GPIO_PuPd_NOPULL; GPIO_Init(GPIOA, &GPIO_InitStruct); +#if defined(SOC_SERIES_FT32F0) GPIO_PinAFConfig(GPIOA, GPIO_PinSource9, GPIO_AF_1); GPIO_PinAFConfig(GPIOA, GPIO_PinSource10, GPIO_AF_1); - +#endif +#if defined(SOC_SERIES_FT32F4) + GPIO_PinAFConfig(GPIOA, GPIO_PinSource9, GPIO_AF_7); + GPIO_PinAFConfig(GPIOA, GPIO_PinSource10, GPIO_AF_7); +#endif /* USART1 interrupt Init */ NVIC_SetPriority(USART1_IRQn, 5); NVIC_EnableIRQ(USART1_IRQn); } else if (USARTx == USART2) { +#if defined(SOC_SERIES_FT32F0) RCC_AHBPeriphClockCmd(RCC_AHBPeriph_GPIOA, ENABLE); RCC_APB1PeriphClockCmd(RCC_APB1Periph_USART2, ENABLE); +#endif +#if defined(SOC_SERIES_FT32F4) + RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOA, ENABLE); + RCC_APB1PeriphClockCmd(RCC_APB1Periph_UART2, ENABLE); +#endif /*GPIO INIT*/ GPIO_InitStruct.GPIO_Pin = GPIO_Pin_2 | GPIO_Pin_3; @@ -83,8 +95,14 @@ void UART_MspInit(USART_TypeDef *USARTx) GPIO_InitStruct.GPIO_OType = GPIO_OType_PP; GPIO_InitStruct.GPIO_PuPd = GPIO_PuPd_NOPULL; GPIO_Init(GPIOA, &GPIO_InitStruct); +#if defined(SOC_SERIES_FT32F0) GPIO_PinAFConfig(GPIOA, GPIO_PinSource2, GPIO_AF_1); GPIO_PinAFConfig(GPIOA, GPIO_PinSource3, GPIO_AF_1); +#endif +#if defined(SOC_SERIES_FT32F4) + GPIO_PinAFConfig(GPIOA, GPIO_PinSource2, GPIO_AF_7); + GPIO_PinAFConfig(GPIOA, GPIO_PinSource3, GPIO_AF_7); +#endif /* USART2 interrupt Init */ NVIC_SetPriority(USART2_IRQn, 5); @@ -100,15 +118,24 @@ static rt_err_t ft32_configure(struct rt_serial_device *serial, struct serial_co uart = rt_container_of(serial, struct ft32_uart, serial); uart->Init.USART_BaudRate = cfg->baud_rate; +#if defined(SOC_SERIES_FT32F0) uart->Init.USART_Mode = USART_Mode_Tx | USART_Mode_Rx; - +#endif +#if defined(SOC_SERIES_FT32F4) + uart->Init.USART_Mode = USART_MODE_TX_RX; +#endif switch (cfg->flowcontrol) { case RT_SERIAL_FLOWCONTROL_NONE: uart->Init.USART_HardwareFlowControl = USART_HardwareFlowControl_None; break; case RT_SERIAL_FLOWCONTROL_CTSRTS: +#if defined(SOC_SERIES_FT32F0) uart->Init.USART_HardwareFlowControl = USART_HardwareFlowControl_RTS_CTS; +#endif +#if defined(SOC_SERIES_FT32F4) + uart->Init.USART_HardwareFlowControl = USART_HardwareFlowControl_RTS_DTR; +#endif break; default: uart->Init.USART_HardwareFlowControl = USART_HardwareFlowControl_None; @@ -117,6 +144,7 @@ static rt_err_t ft32_configure(struct rt_serial_device *serial, struct serial_co switch (cfg->data_bits) { +#if defined(SOC_SERIES_FT32F0) case DATA_BITS_8: if (cfg->parity == PARITY_ODD || cfg->parity == PARITY_EVEN) uart->Init.USART_WordLength = USART_WordLength_9b; @@ -129,10 +157,32 @@ static rt_err_t ft32_configure(struct rt_serial_device *serial, struct serial_co default: uart->Init.USART_WordLength = USART_WordLength_8b; break; +#endif +#if defined(SOC_SERIES_FT32F4) + case DATA_BITS_9: + uart->Init.USART_WordLength = USART_CHAR_LENGTH9_ENABLE; + break; + case DATA_BITS_8: + uart->Init.USART_WordLength = USART_CHAR_LENGTH_8BIT; + break; + case DATA_BITS_7: + uart->Init.USART_WordLength = USART_CHAR_LENGTH_7BIT; + break; + case DATA_BITS_6: + uart->Init.USART_WordLength = USART_CHAR_LENGTH_6BIT; + break; + case DATA_BITS_5: + uart->Init.USART_WordLength = USART_CHAR_LENGTH_5BIT; + break; + default: + uart->Init.USART_WordLength = USART_CHAR_LENGTH_8BIT; + break; +#endif } switch (cfg->stop_bits) { +#if defined(SOC_SERIES_FT32F0) case STOP_BITS_1: uart->Init.USART_StopBits = USART_StopBits_1; break; @@ -142,10 +192,23 @@ static rt_err_t ft32_configure(struct rt_serial_device *serial, struct serial_co default: uart->Init.USART_StopBits = USART_StopBits_1; break; +#endif +#if defined(SOC_SERIES_FT32F4) + case STOP_BITS_1: + uart->Init.USART_StopBits = USART_STOPBITS_1; + break; + case STOP_BITS_2: + uart->Init.USART_StopBits = USART_STOPBITS_2; + break; + default: + uart->Init.USART_StopBits = USART_STOPBITS_1; + break; +#endif } switch (cfg->parity) { +#if defined(SOC_SERIES_FT32F0) case PARITY_NONE: uart->Init.USART_Parity = USART_Parity_No; break; @@ -158,11 +221,23 @@ static rt_err_t ft32_configure(struct rt_serial_device *serial, struct serial_co default: uart->Init.USART_Parity = USART_Parity_No; break; +#endif +#if defined(SOC_SERIES_FT32F4) + case PARITY_NONE: + uart->Init.USART_Parity = USART_PARITY_NONE; + break; + case PARITY_ODD: + uart->Init.USART_Parity = USART_PARITY_ODD; + break; + case PARITY_EVEN: + uart->Init.USART_Parity = USART_PARITY_EVEN; + break; + default: + uart->Init.USART_Parity = USART_PARITY_NONE; + break; +#endif } -#ifdef RT_SERIAL_USING_DMA - uart->dma_rx.last_index = 0; -#endif UART_MspInit(uart->config->Instance); USART_Init(uart->config->Instance, &(uart->Init)); USART_Cmd(uart->config->Instance, ENABLE); @@ -172,9 +247,6 @@ static rt_err_t ft32_configure(struct rt_serial_device *serial, struct serial_co static rt_err_t ft32_control(struct rt_serial_device *serial, int cmd, void *arg) { struct ft32_uart *uart; -#ifdef RT_SERIAL_USING_DMA - rt_ubase_t ctrl_arg = (rt_ubase_t)arg; -#endif RT_ASSERT(serial != RT_NULL); uart = rt_container_of(serial, struct ft32_uart, serial); @@ -186,21 +258,17 @@ static rt_err_t ft32_control(struct rt_serial_device *serial, int cmd, void *arg /* disable rx irq */ NVIC_DisableIRQ(uart->config->irq_type); /* disable interrupt */ +#if defined(SOC_SERIES_FT32F0) + /* enable interrupt */ USART_ITConfig(uart->config->Instance, USART_IT_RXNE, DISABLE); - -#ifdef RT_SERIAL_USING_DMA - /* disable DMA */ - if (ctrl_arg == RT_DEVICE_FLAG_DMA_RX) - { - NVIC_DisableIRQ(uart->config->dma_rx->dma_irq); - DMA_DeInit(uart->dma_rx.Instance); - } - else if (ctrl_arg == RT_DEVICE_FLAG_DMA_TX) - { - NVIC_DisableIRQ(uart->config->dma_tx->dma_irq); - DMA_DeInit(uart->dma_rx.Instance); - } + break; +#endif +#if defined(SOC_SERIES_FT32F4) + /* enable interrupt */ + USART_ITConfig(uart->config->Instance, USART_IT_RXRDY, DISABLE); + break; #endif + break; /* enable interrupt */ @@ -208,15 +276,17 @@ static rt_err_t ft32_control(struct rt_serial_device *serial, int cmd, void *arg /* enable rx irq */ NVIC_SetPriority(uart->config->irq_type, 1); NVIC_EnableIRQ(uart->config->irq_type); +#if defined(SOC_SERIES_FT32F0) /* enable interrupt */ USART_ITConfig(uart->config->Instance, USART_IT_RXNE, ENABLE); break; - -#ifdef RT_SERIAL_USING_DMA - case RT_DEVICE_CTRL_CONFIG: - ft32_dma_config(serial, ctrl_arg); +#endif +#if defined(SOC_SERIES_FT32F4) + /* enable interrupt */ + USART_ITConfig(uart->config->Instance, USART_IT_RXRDY, ENABLE); break; #endif + break; case RT_DEVICE_CTRL_CLOSE: USART_DeInit(uart->config->Instance); @@ -226,6 +296,7 @@ static rt_err_t ft32_control(struct rt_serial_device *serial, int cmd, void *arg return RT_EOK; } +#if defined(SOC_SERIES_FT32F0) rt_uint32_t ft32_uart_get_mask(rt_uint32_t word_length, rt_uint32_t parity) { rt_uint32_t mask; @@ -269,6 +340,7 @@ rt_uint32_t ft32_uart_get_mask(rt_uint32_t word_length, rt_uint32_t parity) } return mask; } +#endif static int ft32_putc(struct rt_serial_device *serial, char c) { @@ -276,13 +348,20 @@ static int ft32_putc(struct rt_serial_device *serial, char c) RT_ASSERT(serial != RT_NULL); uart = rt_container_of(serial, struct ft32_uart, serial); - UART_INSTANCE_CLEAR_FUNCTION(uart->config->Instance, USART_FLAG_TC); #if defined(SOC_SERIES_FT32F0) + UART_INSTANCE_CLEAR_FUNCTION(uart->config->Instance, USART_FLAG_TC); uart->config->Instance->TDR = c; +#elif defined(SOC_SERIES_FT32F4) + USART_Transmit(uart->config->Instance, c); #else uart->config->Instance->DR = c; #endif +#if defined(SOC_SERIES_FT32F0) while (USART_GetFlagStatus(uart->config->Instance, USART_FLAG_TC) == RESET); +#endif +#if defined(SOC_SERIES_FT32F4) + while (USART_GetFlagStatus(uart->config->Instance, USART_FLAG_TXRDY) == RESET); +#endif return 1; } @@ -294,14 +373,21 @@ static int ft32_getc(struct rt_serial_device *serial) uart = rt_container_of(serial, struct ft32_uart, serial); ch = -1; +#if defined(SOC_SERIES_FT32F0) if (USART_GetFlagStatus(uart->config->Instance, USART_FLAG_RXNE) != RESET) - { +#endif +#if defined(SOC_SERIES_FT32F4) + if (USART_GetFlagStatus(uart->config->Instance, USART_FLAG_RXRDY) != RESET) +#endif + { #if defined(SOC_SERIES_FT32F0) - ch = uart->config->Instance->RDR & ft32_uart_get_mask(uart->Init.USART_WordLength, uart->Init.USART_Parity); + ch = uart->config->Instance->RDR & ft32_uart_get_mask(uart->Init.USART_WordLength, uart->Init.USART_Parity); +#elif defined(SOC_SERIES_FT32F4) + ch = USART_Receive(uart->config->Instance); #else - ch = uart->config->Instance->DR & ft32_uart_get_mask(uart->Init.USART_WordLength, uart->Init.USART_Parity); + ch = uart->config->Instance->DR & ft32_uart_get_mask(uart->Init.USART_WordLength, uart->Init.USART_Parity); #endif - } + } return ch; } @@ -329,43 +415,24 @@ static rt_ssize_t ft32_dma_transmit(struct rt_serial_device *serial, rt_uint8_t static void uart_isr(struct rt_serial_device *serial) { struct ft32_uart *uart; -#ifdef RT_SERIAL_USING_DMA - rt_size_t recv_total_index, recv_len; - rt_base_t level; -#endif RT_ASSERT(serial != RT_NULL); uart = rt_container_of(serial, struct ft32_uart, serial); - +#if defined(SOC_SERIES_FT32F0) /* UART in mode Receiver -------------------------------------------------*/ if (USART_GetFlagStatus(uart->config->Instance, USART_FLAG_RXNE) != RESET) { rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND); } -#ifdef RT_SERIAL_USING_DMA - else if ((uart->uart_dma_flag) && (USART_GetFlagStatus(uart->config->Instance, USART_FLAG_RXNE) != RESET)) - { - level = rt_hw_interrupt_disable(); - recv_total_index = serial->config.bufsz - DMA_GetCurrDataCounter(&(uart->dma_rx.Instance)); - recv_len = recv_total_index - uart->dma_rx.last_index; - uart->dma_rx.last_index = recv_total_index; - rt_hw_interrupt_enable(level); - - if (recv_len) - { - rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_DMADONE | (recv_len << 8)); - } - USART_ClearFlag(uart->config->Instance, USART_IT_IDLE); - } - else if (USART_GetFlagStatus(uart->config->Instance, USART_FLAG_TC) != RESET) +#endif +#if defined(SOC_SERIES_FT32F4) + /* UART in mode Receiver -------------------------------------------------*/ + if (USART_GetFlagStatus(uart->config->Instance, USART_FLAG_RXRDY) != RESET) { - if ((serial->parent.open_flag & RT_DEVICE_FLAG_DMA_TX) != 0) - { - - } - UART_INSTANCE_CLEAR_FUNCTION(uart->config->Instance, USART_FLAG_TC); + rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND); } #endif +#if defined (SOC_SERIES_FT32F0) else { if (USART_GetFlagStatus(uart->config->Instance, USART_FLAG_ORE) != RESET) @@ -384,12 +451,6 @@ static void uart_isr(struct rt_serial_device *serial) { USART_ClearFlag(uart->config->Instance, USART_FLAG_PE); } -#if !defined(SOC_SERIES_FT32F0) - if (USART_GetFlagStatus(uart->config->Instance, USART_FLAG_LBD) != RESET) - { - UART_INSTANCE_CLEAR_FUNCTION(uart->config->Instance, USART_FLAG_LBD); - } -#endif if (USART_GetFlagStatus(uart->config->Instance, USART_FLAG_CTS) != RESET) { UART_INSTANCE_CLEAR_FUNCTION(uart->config->Instance, USART_FLAG_CTS); @@ -407,42 +468,16 @@ static void uart_isr(struct rt_serial_device *serial) UART_INSTANCE_CLEAR_FUNCTION(uart->config->Instance, USART_FLAG_RXNE); } } -} - -#ifdef RT_SERIAL_USING_DMA -static void dma_isr(struct rt_serial_device *serial) -{ - struct ft32_uart *uart; - rt_size_t recv_total_index, recv_len; - rt_base_t level; - - RT_ASSERT(serial != RT_NULL); - uart = rt_container_of(serial, struct ft32_uart, serial); - - if ((DMA_GetITStatus(uart->dma_rx.Instance, DMA_IT_TC) != RESET) || - (DMA_GetITStatus(uart->dma_rx.Instance, DMA_IT_HT) != RESET)) +#endif +#if defined (SOC_SERIES_FT32F4) + else { - level = rt_hw_interrupt_disable(); - recv_total_index = serial->config.bufsz - DMA_GetCurrDataCounter(uart->dma_rx.Instance); - if (recv_total_index == 0) - { - recv_len = serial->config.bufsz - uart->dma_rx.last_index; - } - else - { - recv_len = recv_total_index - uart->dma_rx.last_index; - } - uart->dma_rx.last_index = recv_total_index; - rt_hw_interrupt_enable(level); - if (recv_len) - { - rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_DMADONE | (recv_len << 8)); - } } -} #endif +} +#if defined(SOC_SERIES_FT32F0) #if defined(BSP_USING_UART1) void USART1_IRQHandler(void) { @@ -454,30 +489,7 @@ void USART1_IRQHandler(void) /* leave interrupt */ rt_interrupt_leave(); } -#if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART1_RX_USING_DMA) -void UART1_DMA_RX_IRQHandler(void) -{ - /* enter interrupt */ - rt_interrupt_enter(); - - __DMA_IRQHandler(uart_obj[UART1_INDEX].dma_rx.Instance); - - /* leave interrupt */ - rt_interrupt_leave(); -} -#endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART1_RX_USING_DMA) */ -#if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART1_TX_USING_DMA) -void UART1_DMA_TX_IRQHandler(void) -{ - /* enter interrupt */ - rt_interrupt_enter(); - - __DMA_IRQHandler(uart_obj[UART1_INDEX].dma_tx.Instance); - /* leave interrupt */ - rt_interrupt_leave(); -} -#endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART1_TX_USING_DMA) */ #endif /* BSP_USING_UART1 */ #if defined(BSP_USING_UART2) @@ -491,170 +503,51 @@ void USART2_IRQHandler(void) /* leave interrupt */ rt_interrupt_leave(); } -#if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART2_RX_USING_DMA) -void UART2_DMA_RX_IRQHandler(void) + +#endif /* BSP_USING_UART2 */ +#endif + +#if defined(SOC_SERIES_FT32F4) +#if defined(BSP_USING_UART1) +void USART1_Handler(void) { /* enter interrupt */ rt_interrupt_enter(); - __DMA_IRQHandler(uart_obj[UART2_INDEX].dma_rx.Instance); + uart_isr(&(uart_obj[UART1_INDEX].serial)); /* leave interrupt */ rt_interrupt_leave(); } -#endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART2_RX_USING_DMA) */ -#if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART2_TX_USING_DMA) -void UART2_DMA_TX_IRQHandler(void) + +#endif /* BSP_USING_UART1 */ + +#if defined(BSP_USING_UART2) +void USART2_Handler(void) { /* enter interrupt */ rt_interrupt_enter(); - __DMA_IRQHandler(uart_obj[UART2_INDEX].dma_tx.Instance); + uart_isr(&(uart_obj[UART2_INDEX].serial)); /* leave interrupt */ rt_interrupt_leave(); } -#endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART2_TX_USING_DMA) */ -#endif /* BSP_USING_UART2 */ +#endif /* BSP_USING_UART2 */ +#endif static void ft32_uart_get_dma_config(void) { #ifdef BSP_USING_UART1 uart_obj[UART1_INDEX].uart_dma_flag = 0; -#ifdef BSP_UART1_RX_USING_DMA - uart_obj[UART1_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX; - static struct dma_config uart1_dma_rx = UART1_DMA_RX_CONFIG; - uart_config[UART1_INDEX].dma_rx = &uart1_dma_rx; -#endif -#ifdef BSP_UART1_TX_USING_DMA - uart_obj[UART1_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_TX; - static struct dma_config uart1_dma_tx = UART1_DMA_TX_CONFIG; - uart_config[UART1_INDEX].dma_tx = &uart1_dma_tx; -#endif #endif #ifdef BSP_USING_UART2 uart_obj[UART2_INDEX].uart_dma_flag = 0; -#ifdef BSP_UART2_RX_USING_DMA - uart_obj[UART2_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX; - static struct dma_config uart2_dma_rx = UART2_DMA_RX_CONFIG; - uart_config[UART2_INDEX].dma_rx = &uart2_dma_rx; -#endif -#ifdef BSP_UART2_TX_USING_DMA - uart_obj[UART2_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_TX; - static struct dma_config uart2_dma_tx = UART2_DMA_TX_CONFIG; - uart_config[UART2_INDEX].dma_tx = &uart2_dma_tx; #endif -#endif -} - -#ifdef RT_SERIAL_USING_DMA -static void ft32_dma_config(struct rt_serial_device *serial, rt_ubase_t flag) -{ - struct rt_serial_rx_fifo *rx_fifo; - - DMA_InitTypeDef Init; - struct dma_config *dma_config; - struct ft32_uart *uart; - - RT_ASSERT(serial != RT_NULL); - RT_ASSERT(flag == RT_DEVICE_FLAG_DMA_TX || flag == RT_DEVICE_FLAG_DMA_RX); - uart = rt_container_of(serial, struct ft32_uart, serial); - - if (RT_DEVICE_FLAG_DMA_RX == flag) - { - Init = &uart->dma_rx.Init; - dma_config = uart->config->dma_rx; - } - else /* RT_DEVICE_FLAG_DMA_TX == flag */ - { - Init = &uart->dma_tx.Init; - dma_config = uart->config->dma_tx; - } - LOG_D("%s dma config start", uart->config->name); - - { - rt_uint32_t tmpreg = 0x00U; -#if defined(SOC_SERIES_FT32F0) - /* enable DMA clock && Delay after an RCC peripheral clock enabling*/ - SET_BIT(RCC->AHBENR, dma_config->dma_rcc); - tmpreg = READ_BIT(RCC->AHBENR, dma_config->dma_rcc); -#endif - - (void)(tmpreg); /* To avoid compiler warnings */ - } - - if (RT_DEVICE_FLAG_DMA_RX == flag) - { - } - else if (RT_DEVICE_FLAG_DMA_TX == flag) - { - } - - Init.DMA_PeripheralInc = DMA_PeripheralInc_Disable; - Init.MemInc = DMA_MemoryInc_Enable; - Init.PeriphDataAlignment = DMA_PeripheralDataSize_Byte; - Init.MemDataAlignment = DMA_MemoryDataSize_Byte; - - if (RT_DEVICE_FLAG_DMA_RX == flag) - { - Init.Direction = DMA_DIR_PeripheralSRC; - Init.Mode = DMA_Mode_Circular; - } - else if (RT_DEVICE_FLAG_DMA_TX == flag) - { - Init.Direction = DMA_DIR_PeripheralDST; - Init.Mode = DMA_Mode_Normal; - } - - Init.Priority = DMA_Priority_Medium; - DMA_DeInit(dma_config->Instance); - DMA_Init(dma_config->Instance); - - /* enable interrupt */ - if (flag == RT_DEVICE_FLAG_DMA_RX) - { - rx_fifo = (struct rt_serial_rx_fifo *)serial->serial_rx; - /* Start DMA transfer */ - UART_Receive_DMA(uart->config->Instance, rx_fifo->buffer, serial->config.bufsz); - CLEAR_BIT(uart->handle.Instance->CR3, USART_CR3_EIE); - USART_ITConfig(uart->config->Instance, USART_IT_IDLE, ENABLE); - } - - /* DMA irq should set in DMA TX mode, or HAL_UART_TxCpltCallback function will not be called */ - NVIC_SetPriority(dma_config->dma_irq, 0, 0); - NVIC_EnableIRQ(dma_config->dma_irq); - - NVIC_SetPriority(uart->config->irq_type, 1, 0); - NVIC_EnableIRQ(uart->config->irq_type); - - LOG_D("%s dma %s instance: %x", uart->config->name, flag == RT_DEVICE_FLAG_DMA_RX ? "RX" : "TX", DMA_Handle->Instance); - LOG_D("%s dma config done", uart->config->name); } -static void _dma_tx_complete(struct rt_serial_device *serial) -{ - struct ft32_uart *uart; - rt_size_t trans_total_index; - rt_base_t level; - - RT_ASSERT(serial != RT_NULL); - uart = rt_container_of(serial, struct ft32_uart, serial); - - level = rt_hw_interrupt_disable(); - trans_total_index = DMA_GetCurrDataCounter(uart->dma_tx.Instance); - rt_hw_interrupt_enable(level); - - if (trans_total_index == 0) - { - rt_hw_serial_isr(serial, RT_SERIAL_EVENT_TX_DMADONE); - } -} - - -#endif /* RT_SERIAL_USING_DMA */ - static const struct rt_uart_ops ft32_uart_ops = { .configure = ft32_configure, diff --git a/bsp/ft32/libraries/Drivers/drv_usart.h b/bsp/ft32/libraries/Drivers/drv_usart.h index ae0462f407c..0530ddcfe0e 100644 --- a/bsp/ft32/libraries/Drivers/drv_usart.h +++ b/bsp/ft32/libraries/Drivers/drv_usart.h @@ -25,6 +25,9 @@ int rt_hw_usart_init(void); #if defined(SOC_SERIES_FT32F0) #define UART_INSTANCE_CLEAR_FUNCTION USART_ClearITPendingBit #endif +#if defined(SOC_SERIES_FT32F4) + #define UART_INSTANCE_CLEAR_FUNCTION USART_ClearFlag +#endif #define USART_TX_Pin GPIO_PIN_2 #define USART_TX_GPIO_Port GPIOA @@ -46,20 +49,6 @@ struct ft32_uart { USART_InitTypeDef Init; struct ft32_uart_config *config; - -#ifdef RT_SERIAL_USING_DMA - struct - { - DMA_InitTypeDef Init; - DMA_Channel_TypeDef *Instance; - rt_size_t last_index; - } dma_rx; - struct - { - DMA_InitTypeDef Init; - DMA_Channel_TypeDef *Instance; - } dma_tx; -#endif rt_uint16_t uart_dma_flag; struct rt_serial_device serial; }; diff --git a/bsp/ft32/libraries/Drivers/uart_config.h b/bsp/ft32/libraries/Drivers/uart_config.h index 19a9ab79739..febb31f71da 100644 --- a/bsp/ft32/libraries/Drivers/uart_config.h +++ b/bsp/ft32/libraries/Drivers/uart_config.h @@ -28,17 +28,6 @@ extern "C" { #endif /* UART1_CONFIG */ #endif /* BSP_USING_UART1 */ -#if defined(BSP_UART1_RX_USING_DMA) -#ifndef UART1_DMA_RX_CONFIG -#define UART1_DMA_RX_CONFIG \ - { \ - .Instance = UART1_RX_DMA_INSTANCE, \ - .dma_rcc = UART1_RX_DMA_RCC, \ - .dma_irq = UART1_RX_DMA_IRQ, \ - } -#endif /* UART1_DMA_RX_CONFIG */ -#endif /* BSP_UART1_RX_USING_DMA */ - #if defined(BSP_USING_UART2) #ifndef UART2_CONFIG #define UART2_CONFIG \ @@ -50,17 +39,6 @@ extern "C" { #endif /* UART2_CONFIG */ #endif /* BSP_USING_UART2 */ -#if defined(BSP_UART2_RX_USING_DMA) -#ifndef UART2_DMA_RX_CONFIG -#define UART2_DMA_RX_CONFIG \ - { \ - .Instance = UART2_RX_DMA_INSTANCE, \ - .dma_rcc = UART2_RX_DMA_RCC, \ - .dma_irq = UART2_RX_DMA_IRQ, \ - } -#endif /* UART2_DMA_RX_CONFIG */ -#endif /* BSP_UART2_RX_USING_DMA */ - #ifdef __cplusplus } #endif diff --git a/bsp/ft32/libraries/FT32F0xx/CMSIS/FT32F0xx/Include/core_cm0.h b/bsp/ft32/libraries/FT32F0xx/CMSIS/FT32F0xx/Include/core_cm0.h deleted file mode 100644 index 620987b3d2a..00000000000 --- a/bsp/ft32/libraries/FT32F0xx/CMSIS/FT32F0xx/Include/core_cm0.h +++ /dev/null @@ -1,702 +0,0 @@ -/**************************************************************************//** - * @file core_cm0.h - * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File - * @version V3.30 - * @date 17. February 2014 - * - * @note - * - ******************************************************************************/ -/* Copyright (c) 2009 - 2014 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#endif - -#ifdef __cplusplus - extern "C" { -#endif - -#ifndef __CORE_CM0_H_GENERIC -#define __CORE_CM0_H_GENERIC - -/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** \ingroup Cortex_M0 - @{ - */ - -/* CMSIS CM0 definitions */ -#define __CM0_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */ -#define __CM0_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */ -#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16) | \ - __CM0_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ - -#define __CORTEX_M (0x00) /*!< Cortex-M Core */ - - -#if defined ( __CC_ARM ) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - #define __STATIC_INLINE static __inline - -#elif defined ( __GNUC__ ) - #define __ASM __asm /*!< asm keyword for GNU Compiler */ - #define __INLINE inline /*!< inline keyword for GNU Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __ICCARM__ ) - #define __ASM __asm /*!< asm keyword for IAR Compiler */ - #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ - #define __STATIC_INLINE static inline - -#elif defined ( __TMS470__ ) - #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __TASKING__ ) - #define __ASM __asm /*!< asm keyword for TASKING Compiler */ - #define __INLINE inline /*!< inline keyword for TASKING Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __CSMC__ ) /* Cosmic */ - #define __packed - #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ - #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */ - #define __STATIC_INLINE static inline - -#endif - -/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all -*/ -#define __FPU_USED 0 - -#if defined ( __CC_ARM ) - #if defined __TARGET_FPU_VFP - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TMS470__ ) - #if defined __TI__VFP_SUPPORT____ - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TASKING__ ) - #if defined __FPU_VFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __CSMC__ ) /* Cosmic */ - #if ( __CSMC__ & 0x400) // FPU present for parser - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif -#endif - -#include /* standard types definitions */ -#include /* Core Instruction Access */ -#include /* Core Function Access */ - -#endif /* __CORE_CM0_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_CM0_H_DEPENDANT -#define __CORE_CM0_H_DEPENDANT - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __CM0_REV - #define __CM0_REV 0x0000 - #warning "__CM0_REV not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 2 - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0 - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ -#else - #define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/*@} end of group Cortex_M0 */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - ******************************************************************************/ -/** \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { -#if (__CORTEX_M != 0x04) - uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ -#else - uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ -#endif - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - - -/** \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - - -/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ -#if (__CORTEX_M != 0x04) - uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ -#else - uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ -#endif - uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - - -/** \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ - uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ - uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ - uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/*@} end of group CMSIS_CORE */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[31]; - __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[31]; - __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[31]; - __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[31]; - uint32_t RESERVED4[64]; - __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ -} NVIC_Type; - -/*@} end of group CMSIS_NVIC */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ - uint32_t RESERVED0; - __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - uint32_t RESERVED1; - __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ - __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ -#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ -#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) - are only accessible over DAP and not via processor. Therefore - they are not covered by the Cortex-M0 header file. - @{ - */ -/*@} end of group CMSIS_CoreDebug */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of Cortex-M0 Hardware */ -#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - -#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ - - -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Register Access Functions - ******************************************************************************/ -/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -/* Interrupt Priorities are WORD accessible only under ARMv6M */ -/* The following MACROS handle generation of the register offset and byte masks */ -#define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 ) -#define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) ) -#define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) ) - - -/** \brief Enable External Interrupt - - The function enables a device-specific interrupt in the NVIC interrupt controller. - - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) -{ - NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); -} - - -/** \brief Disable External Interrupt - - The function disables a device-specific interrupt in the NVIC interrupt controller. - - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) -{ - NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); -} - - -/** \brief Get Pending Interrupt - - The function reads the pending register in the NVIC and returns the pending bit - for the specified interrupt. - - \param [in] IRQn Interrupt number. - - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - */ -__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); -} - - -/** \brief Set Pending Interrupt - - The function sets the pending bit of an external interrupt. - - \param [in] IRQn Interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); -} - - -/** \brief Clear Pending Interrupt - - The function clears the pending bit of an external interrupt. - - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ -} - - -/** \brief Set Interrupt Priority - - The function sets the priority of an interrupt. - - \note The priority cannot be set for every core interrupt. - - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - */ -__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if(IRQn < 0) { - SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) | - (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); } - else { - NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) | - (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); } -} - - -/** \brief Get Interrupt Priority - - The function reads the priority of an interrupt. The interrupt - number can be positive to specify an external (device specific) - interrupt, or negative to specify an internal (core) interrupt. - - - \param [in] IRQn Interrupt number. - \return Interrupt Priority. Value is aligned automatically to the implemented - priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) -{ - - if(IRQn < 0) { - return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M0 system interrupts */ - else { - return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ -} - - -/** \brief System Reset - - The function initiates a system reset request to reset the MCU. - */ -__STATIC_INLINE void NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | - SCB_AIRCR_SYSRESETREQ_Msk); - __DSB(); /* Ensure completion of memory access */ - while(1); /* wait until reset */ -} - -/*@} end of CMSIS_Core_NVICFunctions */ - - - -/* ################################## SysTick function ############################################ */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if (__Vendor_SysTickConfig == 0) - -/** \brief System Tick Configuration - - The function initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - - \param [in] ticks Number of ticks between two interrupts. - - \return 0 Function succeeded. - \return 1 Function failed. - - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ - - SysTick->LOAD = ticks - 1; /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0); /* Function successful */ -} - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - - -#endif /* __CORE_CM0_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ - -#ifdef __cplusplus -} -#endif diff --git a/bsp/ft32/libraries/FT32F0xx/CMSIS/FT32F0xx/Include/core_cm0plus.h b/bsp/ft32/libraries/FT32F0xx/CMSIS/FT32F0xx/Include/core_cm0plus.h deleted file mode 100644 index e0bbfdcadae..00000000000 --- a/bsp/ft32/libraries/FT32F0xx/CMSIS/FT32F0xx/Include/core_cm0plus.h +++ /dev/null @@ -1,813 +0,0 @@ -/**************************************************************************//** - * @file core_cm0plus.h - * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File - * @version V3.30 - * @date 17. February 2014 - * - * @note - * - ******************************************************************************/ -/* Copyright (c) 2009 - 2014 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#endif - -#ifdef __cplusplus - extern "C" { -#endif - -#ifndef __CORE_CM0PLUS_H_GENERIC -#define __CORE_CM0PLUS_H_GENERIC - -/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** \ingroup Cortex-M0+ - @{ - */ - -/* CMSIS CM0P definitions */ -#define __CM0PLUS_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */ -#define __CM0PLUS_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */ -#define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16) | \ - __CM0PLUS_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */ - -#define __CORTEX_M (0x00) /*!< Cortex-M Core */ - - -#if defined ( __CC_ARM ) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - #define __STATIC_INLINE static __inline - -#elif defined ( __GNUC__ ) - #define __ASM __asm /*!< asm keyword for GNU Compiler */ - #define __INLINE inline /*!< inline keyword for GNU Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __ICCARM__ ) - #define __ASM __asm /*!< asm keyword for IAR Compiler */ - #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ - #define __STATIC_INLINE static inline - -#elif defined ( __TMS470__ ) - #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __TASKING__ ) - #define __ASM __asm /*!< asm keyword for TASKING Compiler */ - #define __INLINE inline /*!< inline keyword for TASKING Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __CSMC__ ) /* Cosmic */ - #define __packed - #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ - #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */ - #define __STATIC_INLINE static inline - -#endif - -/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all -*/ -#define __FPU_USED 0 - -#if defined ( __CC_ARM ) - #if defined __TARGET_FPU_VFP - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TMS470__ ) - #if defined __TI__VFP_SUPPORT____ - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TASKING__ ) - #if defined __FPU_VFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __CSMC__ ) /* Cosmic */ - #if ( __CSMC__ & 0x400) // FPU present for parser - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif -#endif - -#include /* standard types definitions */ -#include /* Core Instruction Access */ -#include /* Core Function Access */ - -#endif /* __CORE_CM0PLUS_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_CM0PLUS_H_DEPENDANT -#define __CORE_CM0PLUS_H_DEPENDANT - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __CM0PLUS_REV - #define __CM0PLUS_REV 0x0000 - #warning "__CM0PLUS_REV not defined in device header file; using default!" - #endif - - #ifndef __MPU_PRESENT - #define __MPU_PRESENT 0 - #warning "__MPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __VTOR_PRESENT - #define __VTOR_PRESENT 0 - #warning "__VTOR_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 2 - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0 - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ -#else - #define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/*@} end of group Cortex-M0+ */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - - Core MPU Register - ******************************************************************************/ -/** \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { -#if (__CORTEX_M != 0x04) - uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ -#else - uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ -#endif - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - - -/** \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - - -/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ -#if (__CORTEX_M != 0x04) - uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ -#else - uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ -#endif - uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - - -/** \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ - uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ - uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ - uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/*@} end of group CMSIS_CORE */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[31]; - __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[31]; - __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[31]; - __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[31]; - uint32_t RESERVED4[64]; - __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ -} NVIC_Type; - -/*@} end of group CMSIS_NVIC */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ -#if (__VTOR_PRESENT == 1) - __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ -#else - uint32_t RESERVED0; -#endif - __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - uint32_t RESERVED1; - __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ - __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ -#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ - -#if (__VTOR_PRESENT == 1) -/* SCB Interrupt Control State Register Definitions */ -#define SCB_VTOR_TBLOFF_Pos 8 /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ -#endif - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ -#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - -#if (__MPU_PRESENT == 1) -/** \ingroup CMSIS_core_register - \defgroup CMSIS_MPU Memory Protection Unit (MPU) - \brief Type definitions for the Memory Protection Unit (MPU) - @{ - */ - -/** \brief Structure type to access the Memory Protection Unit (MPU). - */ -typedef struct -{ - __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ - __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ - __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ - __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ - __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ -} MPU_Type; - -/* MPU Type Register */ -#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ - -#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ - -#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */ - -/* MPU Control Register */ -#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ - -#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ - -#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */ - -/* MPU Region Number Register */ -#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */ - -/* MPU Region Base Address Register */ -#define MPU_RBAR_ADDR_Pos 8 /*!< MPU RBAR: ADDR Position */ -#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ - -#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ -#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ - -#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ -#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */ - -/* MPU Region Attribute and Size Register */ -#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */ -#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ - -#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */ -#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ - -#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */ -#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ - -#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */ -#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ - -#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */ -#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ - -#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */ -#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ - -#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */ -#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ - -#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ -#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ - -#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ -#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ - -#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */ -#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */ - -/*@} end of group CMSIS_MPU */ -#endif - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) - are only accessible over DAP and not via processor. Therefore - they are not covered by the Cortex-M0 header file. - @{ - */ -/*@} end of group CMSIS_CoreDebug */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of Cortex-M0+ Hardware */ -#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - -#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ - -#if (__MPU_PRESENT == 1) - #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ - #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ -#endif - -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Register Access Functions - ******************************************************************************/ -/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -/* Interrupt Priorities are WORD accessible only under ARMv6M */ -/* The following MACROS handle generation of the register offset and byte masks */ -#define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 ) -#define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) ) -#define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) ) - - -/** \brief Enable External Interrupt - - The function enables a device-specific interrupt in the NVIC interrupt controller. - - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) -{ - NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); -} - - -/** \brief Disable External Interrupt - - The function disables a device-specific interrupt in the NVIC interrupt controller. - - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) -{ - NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); -} - - -/** \brief Get Pending Interrupt - - The function reads the pending register in the NVIC and returns the pending bit - for the specified interrupt. - - \param [in] IRQn Interrupt number. - - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - */ -__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); -} - - -/** \brief Set Pending Interrupt - - The function sets the pending bit of an external interrupt. - - \param [in] IRQn Interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); -} - - -/** \brief Clear Pending Interrupt - - The function clears the pending bit of an external interrupt. - - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ -} - - -/** \brief Set Interrupt Priority - - The function sets the priority of an interrupt. - - \note The priority cannot be set for every core interrupt. - - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - */ -__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if(IRQn < 0) { - SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) | - (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); } - else { - NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) | - (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); } -} - - -/** \brief Get Interrupt Priority - - The function reads the priority of an interrupt. The interrupt - number can be positive to specify an external (device specific) - interrupt, or negative to specify an internal (core) interrupt. - - - \param [in] IRQn Interrupt number. - \return Interrupt Priority. Value is aligned automatically to the implemented - priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) -{ - - if(IRQn < 0) { - return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M0 system interrupts */ - else { - return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ -} - - -/** \brief System Reset - - The function initiates a system reset request to reset the MCU. - */ -__STATIC_INLINE void NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | - SCB_AIRCR_SYSRESETREQ_Msk); - __DSB(); /* Ensure completion of memory access */ - while(1); /* wait until reset */ -} - -/*@} end of CMSIS_Core_NVICFunctions */ - - - -/* ################################## SysTick function ############################################ */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if (__Vendor_SysTickConfig == 0) - -/** \brief System Tick Configuration - - The function initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - - \param [in] ticks Number of ticks between two interrupts. - - \return 0 Function succeeded. - \return 1 Function failed. - - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ - - SysTick->LOAD = ticks - 1; /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0); /* Function successful */ -} - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - - -#endif /* __CORE_CM0PLUS_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ - -#ifdef __cplusplus -} -#endif diff --git a/bsp/ft32/libraries/FT32F0xx/CMSIS/FT32F0xx/Include/core_cmFunc.h b/bsp/ft32/libraries/FT32F0xx/CMSIS/FT32F0xx/Include/core_cmFunc.h deleted file mode 100644 index 2c2af69c180..00000000000 --- a/bsp/ft32/libraries/FT32F0xx/CMSIS/FT32F0xx/Include/core_cmFunc.h +++ /dev/null @@ -1,637 +0,0 @@ -/**************************************************************************//** - * @file core_cmFunc.h - * @brief CMSIS Cortex-M Core Function Access Header File - * @version V3.30 - * @date 17. February 2014 - * - * @note - * - ******************************************************************************/ -/* Copyright (c) 2009 - 2014 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - -#ifndef __CORE_CMFUNC_H -#define __CORE_CMFUNC_H - - -/* ########################### Core Function Access ########################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions - @{ - */ - -#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ -/* ARM armcc specific functions */ - -#if (__ARMCC_VERSION < 400677) - #error "Please use ARM Compiler Toolchain V4.0.677 or later!" -#endif - -/* intrinsic void __enable_irq(); */ -/* intrinsic void __disable_irq(); */ - -/** \brief Get Control Register - - This function returns the content of the Control Register. - - \return Control Register value - */ -__STATIC_INLINE uint32_t __get_CONTROL(void) -{ - register uint32_t __regControl __ASM("control"); - return(__regControl); -} - - -/** \brief Set Control Register - - This function writes the given value to the Control Register. - - \param [in] control Control Register value to set - */ -__STATIC_INLINE void __set_CONTROL(uint32_t control) -{ - register uint32_t __regControl __ASM("control"); - __regControl = control; -} - - -/** \brief Get IPSR Register - - This function returns the content of the IPSR Register. - - \return IPSR Register value - */ -__STATIC_INLINE uint32_t __get_IPSR(void) -{ - register uint32_t __regIPSR __ASM("ipsr"); - return(__regIPSR); -} - - -/** \brief Get APSR Register - - This function returns the content of the APSR Register. - - \return APSR Register value - */ -__STATIC_INLINE uint32_t __get_APSR(void) -{ - register uint32_t __regAPSR __ASM("apsr"); - return(__regAPSR); -} - - -/** \brief Get xPSR Register - - This function returns the content of the xPSR Register. - - \return xPSR Register value - */ -__STATIC_INLINE uint32_t __get_xPSR(void) -{ - register uint32_t __regXPSR __ASM("xpsr"); - return(__regXPSR); -} - - -/** \brief Get Process Stack Pointer - - This function returns the current value of the Process Stack Pointer (PSP). - - \return PSP Register value - */ -__STATIC_INLINE uint32_t __get_PSP(void) -{ - register uint32_t __regProcessStackPointer __ASM("psp"); - return(__regProcessStackPointer); -} - - -/** \brief Set Process Stack Pointer - - This function assigns the given value to the Process Stack Pointer (PSP). - - \param [in] topOfProcStack Process Stack Pointer value to set - */ -__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) -{ - register uint32_t __regProcessStackPointer __ASM("psp"); - __regProcessStackPointer = topOfProcStack; -} - - -/** \brief Get Main Stack Pointer - - This function returns the current value of the Main Stack Pointer (MSP). - - \return MSP Register value - */ -__STATIC_INLINE uint32_t __get_MSP(void) -{ - register uint32_t __regMainStackPointer __ASM("msp"); - return(__regMainStackPointer); -} - - -/** \brief Set Main Stack Pointer - - This function assigns the given value to the Main Stack Pointer (MSP). - - \param [in] topOfMainStack Main Stack Pointer value to set - */ -__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) -{ - register uint32_t __regMainStackPointer __ASM("msp"); - __regMainStackPointer = topOfMainStack; -} - - -/** \brief Get Priority Mask - - This function returns the current state of the priority mask bit from the Priority Mask Register. - - \return Priority Mask value - */ -__STATIC_INLINE uint32_t __get_PRIMASK(void) -{ - register uint32_t __regPriMask __ASM("primask"); - return(__regPriMask); -} - - -/** \brief Set Priority Mask - - This function assigns the given value to the Priority Mask Register. - - \param [in] priMask Priority Mask - */ -__STATIC_INLINE void __set_PRIMASK(uint32_t priMask) -{ - register uint32_t __regPriMask __ASM("primask"); - __regPriMask = (priMask); -} - - -#if (__CORTEX_M >= 0x03) - -/** \brief Enable FIQ - - This function enables FIQ interrupts by clearing the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -#define __enable_fault_irq __enable_fiq - - -/** \brief Disable FIQ - - This function disables FIQ interrupts by setting the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -#define __disable_fault_irq __disable_fiq - - -/** \brief Get Base Priority - - This function returns the current value of the Base Priority register. - - \return Base Priority register value - */ -__STATIC_INLINE uint32_t __get_BASEPRI(void) -{ - register uint32_t __regBasePri __ASM("basepri"); - return(__regBasePri); -} - - -/** \brief Set Base Priority - - This function assigns the given value to the Base Priority register. - - \param [in] basePri Base Priority value to set - */ -__STATIC_INLINE void __set_BASEPRI(uint32_t basePri) -{ - register uint32_t __regBasePri __ASM("basepri"); - __regBasePri = (basePri & 0xff); -} - - -/** \brief Get Fault Mask - - This function returns the current value of the Fault Mask register. - - \return Fault Mask register value - */ -__STATIC_INLINE uint32_t __get_FAULTMASK(void) -{ - register uint32_t __regFaultMask __ASM("faultmask"); - return(__regFaultMask); -} - - -/** \brief Set Fault Mask - - This function assigns the given value to the Fault Mask register. - - \param [in] faultMask Fault Mask value to set - */ -__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) -{ - register uint32_t __regFaultMask __ASM("faultmask"); - __regFaultMask = (faultMask & (uint32_t)1); -} - -#endif /* (__CORTEX_M >= 0x03) */ - - -#if (__CORTEX_M == 0x04) - -/** \brief Get FPSCR - - This function returns the current value of the Floating Point Status/Control register. - - \return Floating Point Status/Control register value - */ -__STATIC_INLINE uint32_t __get_FPSCR(void) -{ -#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) - register uint32_t __regfpscr __ASM("fpscr"); - return(__regfpscr); -#else - return(0); -#endif -} - - -/** \brief Set FPSCR - - This function assigns the given value to the Floating Point Status/Control register. - - \param [in] fpscr Floating Point Status/Control value to set - */ -__STATIC_INLINE void __set_FPSCR(uint32_t fpscr) -{ -#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) - register uint32_t __regfpscr __ASM("fpscr"); - __regfpscr = (fpscr); -#endif -} - -#endif /* (__CORTEX_M == 0x04) */ - - -#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/ -/* GNU gcc specific functions */ - -/** \brief Enable IRQ Interrupts - - This function enables IRQ interrupts by clearing the I-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void) -{ - __ASM volatile ("cpsie i" : : : "memory"); -} - - -/** \brief Disable IRQ Interrupts - - This function disables IRQ interrupts by setting the I-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void) -{ - __ASM volatile ("cpsid i" : : : "memory"); -} - - -/** \brief Get Control Register - - This function returns the content of the Control Register. - - \return Control Register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, control" : "=r" (result) ); - return(result); -} - - -/** \brief Set Control Register - - This function writes the given value to the Control Register. - - \param [in] control Control Register value to set - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control) -{ - __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); -} - - -/** \brief Get IPSR Register - - This function returns the content of the IPSR Register. - - \return IPSR Register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); - return(result); -} - - -/** \brief Get APSR Register - - This function returns the content of the APSR Register. - - \return APSR Register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, apsr" : "=r" (result) ); - return(result); -} - - -/** \brief Get xPSR Register - - This function returns the content of the xPSR Register. - - \return xPSR Register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); - return(result); -} - - -/** \brief Get Process Stack Pointer - - This function returns the current value of the Process Stack Pointer (PSP). - - \return PSP Register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, psp\n" : "=r" (result) ); - return(result); -} - - -/** \brief Set Process Stack Pointer - - This function assigns the given value to the Process Stack Pointer (PSP). - - \param [in] topOfProcStack Process Stack Pointer value to set - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) -{ - __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp"); -} - - -/** \brief Get Main Stack Pointer - - This function returns the current value of the Main Stack Pointer (MSP). - - \return MSP Register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, msp\n" : "=r" (result) ); - return(result); -} - - -/** \brief Set Main Stack Pointer - - This function assigns the given value to the Main Stack Pointer (MSP). - - \param [in] topOfMainStack Main Stack Pointer value to set - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) -{ - __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp"); -} - - -/** \brief Get Priority Mask - - This function returns the current state of the priority mask bit from the Priority Mask Register. - - \return Priority Mask value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, primask" : "=r" (result) ); - return(result); -} - - -/** \brief Set Priority Mask - - This function assigns the given value to the Priority Mask Register. - - \param [in] priMask Priority Mask - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask) -{ - __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); -} - - -#if (__CORTEX_M >= 0x03) - -/** \brief Enable FIQ - - This function enables FIQ interrupts by clearing the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void) -{ - __ASM volatile ("cpsie f" : : : "memory"); -} - - -/** \brief Disable FIQ - - This function disables FIQ interrupts by setting the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void) -{ - __ASM volatile ("cpsid f" : : : "memory"); -} - - -/** \brief Get Base Priority - - This function returns the current value of the Base Priority register. - - \return Base Priority register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, basepri_max" : "=r" (result) ); - return(result); -} - - -/** \brief Set Base Priority - - This function assigns the given value to the Base Priority register. - - \param [in] basePri Base Priority value to set - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value) -{ - __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory"); -} - - -/** \brief Get Fault Mask - - This function returns the current value of the Fault Mask register. - - \return Fault Mask register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); - return(result); -} - - -/** \brief Set Fault Mask - - This function assigns the given value to the Fault Mask register. - - \param [in] faultMask Fault Mask value to set - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) -{ - __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); -} - -#endif /* (__CORTEX_M >= 0x03) */ - - -#if (__CORTEX_M == 0x04) - -/** \brief Get FPSCR - - This function returns the current value of the Floating Point Status/Control register. - - \return Floating Point Status/Control register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void) -{ -#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) - uint32_t result; - - /* Empty asm statement works as a scheduling barrier */ - __ASM volatile (""); - __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); - __ASM volatile (""); - return(result); -#else - return(0); -#endif -} - - -/** \brief Set FPSCR - - This function assigns the given value to the Floating Point Status/Control register. - - \param [in] fpscr Floating Point Status/Control value to set - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr) -{ -#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) - /* Empty asm statement works as a scheduling barrier */ - __ASM volatile (""); - __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc"); - __ASM volatile (""); -#endif -} - -#endif /* (__CORTEX_M == 0x04) */ - - -#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ -/* IAR iccarm specific functions */ -#include - - -#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/ -/* TI CCS specific functions */ -#include - - -#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/ -/* TASKING carm specific functions */ -/* - * The CMSIS functions have been implemented as intrinsics in the compiler. - * Please use "carm -?i" to get an up to date list of all intrinsics, - * Including the CMSIS ones. - */ - - -#elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/ -/* Cosmic specific functions */ -#include - -#endif - -/*@} end of CMSIS_Core_RegAccFunctions */ - -#endif /* __CORE_CMFUNC_H */ diff --git a/bsp/ft32/libraries/FT32F0xx/CMSIS/FT32F0xx/Include/core_cmInstr.h b/bsp/ft32/libraries/FT32F0xx/CMSIS/FT32F0xx/Include/core_cmInstr.h deleted file mode 100644 index 49ded78b3db..00000000000 --- a/bsp/ft32/libraries/FT32F0xx/CMSIS/FT32F0xx/Include/core_cmInstr.h +++ /dev/null @@ -1,687 +0,0 @@ -/**************************************************************************//** - * @file core_cmInstr.h - * @brief CMSIS Cortex-M Core Instruction Access Header File - * @version V3.30 - * @date 17. February 2014 - * - * @note - * - ******************************************************************************/ -/* Copyright (c) 2009 - 2014 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - -#ifndef __CORE_CMINSTR_H -#define __CORE_CMINSTR_H - - -/* ########################## Core Instruction Access ######################### */ -/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface - Access to dedicated instructions - @{ -*/ - -#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ -/* ARM armcc specific functions */ - -#if (__ARMCC_VERSION < 400677) - #error "Please use ARM Compiler Toolchain V4.0.677 or later!" -#endif - - -/** \brief No Operation - - No Operation does nothing. This instruction can be used for code alignment purposes. - */ -#define __NOP __nop - - -/** \brief Wait For Interrupt - - Wait For Interrupt is a hint instruction that suspends execution - until one of a number of events occurs. - */ -#define __WFI __wfi - - -/** \brief Wait For Event - - Wait For Event is a hint instruction that permits the processor to enter - a low-power state until one of a number of events occurs. - */ -#define __WFE __wfe - - -/** \brief Send Event - - Send Event is a hint instruction. It causes an event to be signaled to the CPU. - */ -#define __SEV __sev - - -/** \brief Instruction Synchronization Barrier - - Instruction Synchronization Barrier flushes the pipeline in the processor, - so that all instructions following the ISB are fetched from cache or - memory, after the instruction has been completed. - */ -#define __ISB() __isb(0xF) - - -/** \brief Data Synchronization Barrier - - This function acts as a special kind of Data Memory Barrier. - It completes when all explicit memory accesses before this instruction complete. - */ -#define __DSB() __dsb(0xF) - - -/** \brief Data Memory Barrier - - This function ensures the apparent order of the explicit memory operations before - and after the instruction, without ensuring their completion. - */ -#define __DMB() __dmb(0xF) - - -/** \brief Reverse byte order (32 bit) - - This function reverses the byte order in integer value. - - \param [in] value Value to reverse - \return Reversed value - */ -#define __REV __rev - - -/** \brief Reverse byte order (16 bit) - - This function reverses the byte order in two unsigned short values. - - \param [in] value Value to reverse - \return Reversed value - */ -#ifndef __NO_EMBEDDED_ASM -__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value) -{ - rev16 r0, r0 - bx lr -} -#endif - -/** \brief Reverse byte order in signed short value - - This function reverses the byte order in a signed short value with sign extension to integer. - - \param [in] value Value to reverse - \return Reversed value - */ -#ifndef __NO_EMBEDDED_ASM -__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value) -{ - revsh r0, r0 - bx lr -} -#endif - - -/** \brief Rotate Right in unsigned value (32 bit) - - This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. - - \param [in] value Value to rotate - \param [in] value Number of Bits to rotate - \return Rotated value - */ -#define __ROR __ror - - -/** \brief Breakpoint - - This function causes the processor to enter Debug state. - Debug tools can use this to investigate system state when the instruction at a particular address is reached. - - \param [in] value is ignored by the processor. - If required, a debugger can use it to store additional information about the breakpoint. - */ -#define __BKPT(value) __breakpoint(value) - - -#if (__CORTEX_M >= 0x03) - -/** \brief Reverse bit order of value - - This function reverses the bit order of the given value. - - \param [in] value Value to reverse - \return Reversed value - */ -#define __RBIT __rbit - - -/** \brief LDR Exclusive (8 bit) - - This function performs a exclusive LDR command for 8 bit value. - - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) - - -/** \brief LDR Exclusive (16 bit) - - This function performs a exclusive LDR command for 16 bit values. - - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) - - -/** \brief LDR Exclusive (32 bit) - - This function performs a exclusive LDR command for 32 bit values. - - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) - - -/** \brief STR Exclusive (8 bit) - - This function performs a exclusive STR command for 8 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STREXB(value, ptr) __strex(value, ptr) - - -/** \brief STR Exclusive (16 bit) - - This function performs a exclusive STR command for 16 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STREXH(value, ptr) __strex(value, ptr) - - -/** \brief STR Exclusive (32 bit) - - This function performs a exclusive STR command for 32 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STREXW(value, ptr) __strex(value, ptr) - - -/** \brief Remove the exclusive lock - - This function removes the exclusive lock which is created by LDREX. - - */ -#define __CLREX __clrex - - -/** \brief Signed Saturate - - This function saturates a signed value. - - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (1..32) - \return Saturated value - */ -#define __SSAT __ssat - - -/** \brief Unsigned Saturate - - This function saturates an unsigned value. - - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (0..31) - \return Saturated value - */ -#define __USAT __usat - - -/** \brief Count leading zeros - - This function counts the number of leading zeros of a data value. - - \param [in] value Value to count the leading zeros - \return number of leading zeros in value - */ -#define __CLZ __clz - -#endif /* (__CORTEX_M >= 0x03) */ - - -#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/ -/* GNU gcc specific functions */ - -/* Define macros for porting to both thumb1 and thumb2. - * For thumb1, use low register (r0-r7), specified by constrant "l" - * Otherwise, use general registers, specified by constrant "r" */ -#if defined (__thumb__) && !defined (__thumb2__) -#define __CMSIS_GCC_OUT_REG(r) "=l" (r) -#define __CMSIS_GCC_USE_REG(r) "l" (r) -#else -#define __CMSIS_GCC_OUT_REG(r) "=r" (r) -#define __CMSIS_GCC_USE_REG(r) "r" (r) -#endif - -/** \brief No Operation - - No Operation does nothing. This instruction can be used for code alignment purposes. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __NOP(void) -{ - __ASM volatile ("nop"); -} - - -/** \brief Wait For Interrupt - - Wait For Interrupt is a hint instruction that suspends execution - until one of a number of events occurs. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFI(void) -{ - __ASM volatile ("wfi"); -} - - -/** \brief Wait For Event - - Wait For Event is a hint instruction that permits the processor to enter - a low-power state until one of a number of events occurs. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFE(void) -{ - __ASM volatile ("wfe"); -} - - -/** \brief Send Event - - Send Event is a hint instruction. It causes an event to be signaled to the CPU. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __SEV(void) -{ - __ASM volatile ("sev"); -} - - -/** \brief Instruction Synchronization Barrier - - Instruction Synchronization Barrier flushes the pipeline in the processor, - so that all instructions following the ISB are fetched from cache or - memory, after the instruction has been completed. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __ISB(void) -{ - __ASM volatile ("isb"); -} - - -/** \brief Data Synchronization Barrier - - This function acts as a special kind of Data Memory Barrier. - It completes when all explicit memory accesses before this instruction complete. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __DSB(void) -{ - __ASM volatile ("dsb"); -} - - -/** \brief Data Memory Barrier - - This function ensures the apparent order of the explicit memory operations before - and after the instruction, without ensuring their completion. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __DMB(void) -{ - __ASM volatile ("dmb"); -} - - -/** \brief Reverse byte order (32 bit) - - This function reverses the byte order in integer value. - - \param [in] value Value to reverse - \return Reversed value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV(uint32_t value) -{ -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) - return __builtin_bswap32(value); -#else - uint32_t result; - - __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return(result); -#endif -} - - -/** \brief Reverse byte order (16 bit) - - This function reverses the byte order in two unsigned short values. - - \param [in] value Value to reverse - \return Reversed value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV16(uint32_t value) -{ - uint32_t result; - - __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return(result); -} - - -/** \brief Reverse byte order in signed short value - - This function reverses the byte order in a signed short value with sign extension to integer. - - \param [in] value Value to reverse - \return Reversed value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __REVSH(int32_t value) -{ -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) - return (short)__builtin_bswap16(value); -#else - uint32_t result; - - __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return(result); -#endif -} - - -/** \brief Rotate Right in unsigned value (32 bit) - - This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. - - \param [in] value Value to rotate - \param [in] value Number of Bits to rotate - \return Rotated value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2) -{ - return (op1 >> op2) | (op1 << (32 - op2)); -} - - -/** \brief Breakpoint - - This function causes the processor to enter Debug state. - Debug tools can use this to investigate system state when the instruction at a particular address is reached. - - \param [in] value is ignored by the processor. - If required, a debugger can use it to store additional information about the breakpoint. - */ -#define __BKPT(value) __ASM volatile ("bkpt "#value) - - -#if (__CORTEX_M >= 0x03) - -/** \brief Reverse bit order of value - - This function reverses the bit order of the given value. - - \param [in] value Value to reverse - \return Reversed value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RBIT(uint32_t value) -{ - uint32_t result; - - __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); - return(result); -} - - -/** \brief LDR Exclusive (8 bit) - - This function performs a exclusive LDR command for 8 bit value. - - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr) -{ - uint32_t result; - -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) - __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) ); -#else - /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not - accepted by assembler. So has to use following less efficient pattern. - */ - __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); -#endif - return ((uint8_t) result); /* Add explicit type cast here */ -} - - -/** \brief LDR Exclusive (16 bit) - - This function performs a exclusive LDR command for 16 bit values. - - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr) -{ - uint32_t result; - -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) - __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) ); -#else - /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not - accepted by assembler. So has to use following less efficient pattern. - */ - __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); -#endif - return ((uint16_t) result); /* Add explicit type cast here */ -} - - -/** \brief LDR Exclusive (32 bit) - - This function performs a exclusive LDR command for 32 bit values. - - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr) -{ - uint32_t result; - - __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); - return(result); -} - - -/** \brief STR Exclusive (8 bit) - - This function performs a exclusive STR command for 8 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) -{ - uint32_t result; - - __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); - return(result); -} - - -/** \brief STR Exclusive (16 bit) - - This function performs a exclusive STR command for 16 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) -{ - uint32_t result; - - __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); - return(result); -} - - -/** \brief STR Exclusive (32 bit) - - This function performs a exclusive STR command for 32 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) -{ - uint32_t result; - - __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); - return(result); -} - - -/** \brief Remove the exclusive lock - - This function removes the exclusive lock which is created by LDREX. - - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __CLREX(void) -{ - __ASM volatile ("clrex" ::: "memory"); -} - - -/** \brief Signed Saturate - - This function saturates a signed value. - - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (1..32) - \return Saturated value - */ -#define __SSAT(ARG1,ARG2) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1); \ - __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - - -/** \brief Unsigned Saturate - - This function saturates an unsigned value. - - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (0..31) - \return Saturated value - */ -#define __USAT(ARG1,ARG2) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1); \ - __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - - -/** \brief Count leading zeros - - This function counts the number of leading zeros of a data value. - - \param [in] value Value to count the leading zeros - \return number of leading zeros in value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __CLZ(uint32_t value) -{ - uint32_t result; - - __ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) ); - return ((uint8_t) result); /* Add explicit type cast here */ -} - -#endif /* (__CORTEX_M >= 0x03) */ - - -#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ -/* IAR iccarm specific functions */ -#include - - -#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/ -/* TI CCS specific functions */ -#include - - -#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/ -/* TASKING carm specific functions */ -/* - * The CMSIS functions have been implemented as intrinsics in the compiler. - * Please use "carm -?i" to get an up to date list of all intrinsics, - * Including the CMSIS ones. - */ - - -#elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/ -/* Cosmic specific functions */ -#include - -#endif - -/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ - -#endif /* __CORE_CMINSTR_H */ diff --git a/bsp/ft32/libraries/FT32F0xx/CMSIS/FT32F0xx/Include/ft32f030x6.h b/bsp/ft32/libraries/FT32F0xx/CMSIS/FT32F0xx/Include/ft32f030x6.h deleted file mode 100644 index 04847c65eb0..00000000000 --- a/bsp/ft32/libraries/FT32F0xx/CMSIS/FT32F0xx/Include/ft32f030x6.h +++ /dev/null @@ -1,3888 +0,0 @@ -/** - ****************************************************************************** - * @file ft32f030x6.h - * @author FMD AE - * @brief CMSIS Cortex-M0 Device Peripheral Access Layer Header File. - * @details This file contains all the peripheral register's definitions, bits - * definitions and memory mapping for FT32F030X6 devices. - * @version V1.0.0 - * @date 2021-07-01 - ******************************************************************************* - */ - - -#ifndef __FT32F030X6_H -#define __FT32F030X6_H - -#ifdef __cplusplus - extern "C" { -#endif - - -#if !defined (FT32F030X6) - #define FT32F030X6 -#endif - - -#if !defined USE_STDPERIPH_DRIVER -/** - * @brief Comment the line below if you will not use the peripherals drivers. - In this case, these drivers will not be included and the application code will - be based on direct access to peripherals registers - */ - /*#define USE_STDPERIPH_DRIVER*/ -#endif /* USE_STDPERIPH_DRIVER */ - -/** - * @brief In the following line adjust the value of External High Speed oscillator (HSE) - used in your application - - Tip: To avoid modifying this file each time you need to use different HSE, you - can define the HSE value in your toolchain compiler preprocessor. - */ -#if !defined (HSE_VALUE) -#define HSE_VALUE ((uint32_t)8000000) /*!< Value of the External oscillator in Hz*/ -#endif /* HSE_VALUE */ - -/** - * @brief In the following line adjust the External High Speed oscillator (HSE) Startup - Timeout value - */ -#if !defined (HSE_STARTUP_TIMEOUT) -#define HSE_STARTUP_TIMEOUT ((uint16_t)0x5000) /*!< Time out for HSE start up */ -#endif /* HSE_STARTUP_TIMEOUT */ - -/** - * @brief In the following line adjust the Internal High Speed oscillator (HSI) Startup - Timeout value - */ -#if !defined (HSI_STARTUP_TIMEOUT) -#define HSI_STARTUP_TIMEOUT ((uint16_t)0x5000) /*!< Time out for HSI start up */ -#endif /* HSI_STARTUP_TIMEOUT */ - -#if !defined (HSI_VALUE) -#define HSI_VALUE ((uint32_t)8000000) /*!< Value of the Internal High Speed oscillator in Hz. - The real value may vary depending on the variations - in voltage and temperature. */ -#endif /* HSI_VALUE */ - -#if !defined (HSI14_VALUE) -#define HSI14_VALUE ((uint32_t)14000000) /*!< Value of the Internal High Speed oscillator for ADC in Hz. - The real value may vary depending on the variations - in voltage and temperature. */ -#endif /* HSI14_VALUE */ - -#if !defined (HSI48_VALUE) -#define HSI48_VALUE ((uint32_t)48000000) /*!< Value of the Internal High Speed oscillator for USB in Hz. - The real value may vary depending on the variations - in voltage and temperature. */ -#endif /* HSI48_VALUE */ - -#if !defined (LSI_VALUE) -#define LSI_VALUE ((uint32_t)40000) /*!< Value of the Internal Low Speed oscillator in Hz - The real value may vary depending on the variations - in voltage and temperature. */ -#endif /* LSI_VALUE */ - -#if !defined (LSE_VALUE) -#define LSE_VALUE ((uint32_t)32768) /*!< Value of the External Low Speed oscillator in Hz */ -#endif /* LSE_VALUE */ - -/** - * @brief FT32F0XX Standard Peripheral Library version number V1.0.0 - */ -#define __FT32F0XX_STDPERIPH_VERSION_MAIN (0x01) /*!< [31:24] main version */ -#define __FT32F0XX_STDPERIPH_VERSION_SUB1 (0x05) /*!< [23:16] sub1 version */ -#define __FT32F0XX_STDPERIPH_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */ -#define __FT32F0XX_STDPERIPH_VERSION_RC (0x00) /*!< [7:0] release candidate */ -#define __FT32F0XX_STDPERIPH_VERSION ((__FT32F0XX_STDPERIPH_VERSION_MAIN << 24)\ - |(__FT32F0XX_STDPERIPH_VERSION_SUB1 << 16)\ - |(__FT32F0XX_STDPERIPH_VERSION_SUB2 << 8)\ - |(__FT32F0XX_STDPERIPH_VERSION_RC)) - -/** - * @} - */ - -/** @addtogroup Configuration_section_for_CMSIS - * @{ - */ - -/** - * @brief FT32F030X6 Interrupt Number Definition, according to the selected device - * in @ref Library_configuration_section - */ -#define __CM0_REV 0 /*!< Core Revision r0p0 */ -#define __MPU_PRESENT 0 /*!< FT32F030X6 do not provide MPU */ -#define __NVIC_PRIO_BITS 2 /*!< FT32F030X6 uses 2 Bits for the Priority Levels */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ - -/*!< Interrupt Number Definition */ -typedef enum IRQn -{ -/****** Cortex-M0 Processor Exceptions Numbers ******************************************************/ - NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ - HardFault_IRQn = -13, /*!< 3 Cortex-M0 Hard Fault Interrupt */ - SVC_IRQn = -5, /*!< 11 Cortex-M0 SV Call Interrupt */ - PendSV_IRQn = -2, /*!< 14 Cortex-M0 Pend SV Interrupt */ - SysTick_IRQn = -1, /*!< 15 Cortex-M0 System Tick Interrupt */ - -/****** FT32F0 specific Interrupt Numbers ******************************************************************/ - WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ - PVD_VDDIO2_IRQn = 1, /*!< PVD and VDDIO2 supply comparator through EXTI Line detect Interrupt */ - RTC_IRQn = 2, /*!< RTC through EXTI Line Interrupt */ - FLASH_IRQn = 3, /*!< FLASH Interrupt */ - RCC_CRS_IRQn = 4, /*!< RCC and CRS Interrupts */ - EXTI0_1_IRQn = 5, /*!< EXTI Line 0 and 1 Interrupts */ - EXTI2_3_IRQn = 6, /*!< EXTI Line 2 and 3 Interrupts */ - EXTI4_15_IRQn = 7, /*!< EXTI Line 4 to 15 Interrupts */ - DMA1_Channel1_IRQn = 9, /*!< DMA1 Channel 1 Interrupt */ - DMA1_Channel2_3_IRQn = 10, /*!< DMA1 Channel 2 and Channel 3 Interrupts */ - DMA1_Channel4_5_IRQn = 11, /*!< DMA1 Channel 4, Channel 5, Channel 6 and Channel 7 Interrupts */ - ADC1_COMP_IRQn = 12, /*!< ADC1, COMP1 and COMP2 Interrupts */ - TIM1_BRK_UP_TRG_COM_IRQn = 13, /*!< TIM1 Break, Update, Trigger and Commutation Interrupts */ - TIM1_CC_IRQn = 14, /*!< TIM1 Capture Compare Interrupt */ - TIM3_IRQn = 16, /*!< TIM3 Interrupt */ - TIM6_DAC_IRQn = 17, /*!< TIM6 and DAC Interrupts */ - TIM14_IRQn = 19, /*!< TIM14 Interrupt */ - TIM15_IRQn = 20, /*!< TIM15 Interrupt */ - TIM16_IRQn = 21, /*!< TIM16 Interrupt */ - TIM17_IRQn = 22, /*!< TIM17 Interrupt */ - I2C1_IRQn = 23, /*!< I2C1 Interrupt */ - I2C2_IRQn = 24, /*!< I2C2 Interrupt */ - SPI1_IRQn = 25, /*!< SPI1 Interrupt */ - SPI2_IRQn = 26, /*!< SPI2 Interrupt */ - USART1_IRQn = 27, /*!< USART1 Interrupt */ - USART2_IRQn = 28, /*!< USART2 Interrupt */ - USB_IRQn = 31 /*!< USB Low Priority global Interrupt */ -}IRQn_Type; - -/** - * @} - */ - -#include "core_cm0.h" -#include "ft32f0xx.h" -#include "system_ft32f0xx.h" -#include - -/** @addtogroup Exported_types - * @{ - */ - -typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus; - -typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState; -#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE)) - -typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus; -/** - * @brief Analog to Digital Converter - */ - -typedef struct -{ - __IO uint32_t ISR; /*!< ADC Interrupt and Status register, Address offset:0x00 */ - __IO uint32_t IER; /*!< ADC Interrupt Enable register, Address offset:0x04 */ - __IO uint32_t CR; /*!< ADC Control register, Address offset:0x08 */ - __IO uint32_t CFGR1; /*!< ADC Configuration register 1, Address offset:0x0C */ - __IO uint32_t CFGR2; /*!< ADC Configuration register 2, Address offset:0x10 */ - __IO uint32_t SMPR; /*!< ADC Sampling time register, Address offset:0x14 */ - uint32_t RESERVED1; /*!< Reserved, 0x18 */ - uint32_t RESERVED2; /*!< Reserved, 0x1C */ - __IO uint32_t TR; /*!< ADC watchdog threshold register, Address offset:0x20 */ - uint32_t RESERVED3; /*!< Reserved, 0x24 */ - __IO uint32_t CHSELR; /*!< ADC channel selection register, Address offset:0x28 */ - uint32_t RESERVED4[5]; /*!< Reserved, 0x2C */ - __IO uint32_t DR; /*!< ADC data register, Address offset:0x40 */ -} ADC_TypeDef; - -typedef struct -{ - __IO uint32_t CCR; /*Address offset:0x308 */ - __IO uint32_t CR2; /*Address offset:0x30C */ -} ADC_Common_TypeDef; - -/** - * @brief Comparator - */ - -typedef struct -{ - __IO uint32_t RESERVED[7]; /*!< Reserved, Address offset: 0x18-0x00 */ - __IO uint32_t CSR; /*!< COMP comparator control and status register, Address offset: 0x1C */ -} COMP_TypeDef; - -/** - * @brief DAC Configuration - */ -typedef struct -{ - __IO uint32_t RESERVED[8]; /*!< Reserved, Address offset: 0x1C-0x00 */ - __IO uint32_t CTRL; /*!< DAC configuration register Address offset: 0x20 */ - __IO uint32_t DATA1; /*!< DAC1 Input data Address offset: 0x24 */ - __IO uint32_t DATA2; /*!< DAC2 Input data Address offset: 0x28 */ -}DAC_TypeDef; - -/** - * @brief CRC calculation unit - */ - -typedef struct -{ - __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ - __IO uint32_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ - __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ - uint32_t RESERVED2; /*!< Reserved, 0x0C */ - __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */ - __IO uint32_t RESERVED3; /*!< Reserved, 0x14 */ -} CRC_TypeDef; - -/** - * @brief Clock Recovery System - */ -typedef struct -{ -__IO uint32_t CR; /*!< CRS ccontrol register, Address offset: 0x00 */ -__IO uint32_t CFGR; /*!< CRS configuration register, Address offset: 0x04 */ -__IO uint32_t ISR; /*!< CRS interrupt and status register, Address offset: 0x08 */ -__IO uint32_t ICR; /*!< CRS interrupt flag clear register, Address offset: 0x0C */ -} CRS_TypeDef; - -/** - * @brief Debug MCU - */ - -typedef struct -{ - __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ - __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ - __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */ - __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */ -}DBGMCU_TypeDef; - -/** - * @brief DMA Controller - */ - -typedef struct -{ - __IO uint32_t CCR; /*!< DMA channel x configuration register */ - __IO uint32_t CNDTR; /*!< DMA channel x number of data register */ - __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */ - __IO uint32_t CMAR; /*!< DMA channel x memory address register */ -} DMA_Channel_TypeDef; - -typedef struct -{ - __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */ - __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */ -}DMA_TypeDef; - -/** - * @brief External Interrupt/Event Controller - */ - -typedef struct -{ - __IO uint32_t IMR; /*! exti[31] Interrupt */ -//#define SYSCFG_ITLINE1_SR_VDDIO2 ((uint32_t)0x00000002) /*!< VDDIO2 -> exti[16] Interrupt */ -//#define SYSCFG_ITLINE2_SR_RTC_WAKEUP ((uint32_t)0x00000001) /*!< RTC WAKEUP -> exti[20] Interrupt */ -//#define SYSCFG_ITLINE2_SR_RTC_TSTAMP ((uint32_t)0x00000002) /*!< RTC Time Stamp -> exti[19] interrupt */ -//#define SYSCFG_ITLINE2_SR_RTC_ALRA ((uint32_t)0x00000003) /*!< RTC Alarm -> exti[17] interrupt .... */ -//#define SYSCFG_ITLINE3_SR_FLASH_ITF ((uint32_t)0x00000001) /*!< Flash ITF Interrupt */ -//#define SYSCFG_ITLINE4_SR_CRS ((uint32_t)0x00000001) /*!< CRS interrupt */ -//#define SYSCFG_ITLINE4_SR_CLK_CTRL ((uint32_t)0x00000002) /*!< CLK CTRL interrupt */ -//#define SYSCFG_ITLINE5_SR_EXTI0 ((uint32_t)0x00000001) /*!< External Interrupt 0 */ -//#define SYSCFG_ITLINE5_SR_EXTI1 ((uint32_t)0x00000002) /*!< External Interrupt 1 */ -//#define SYSCFG_ITLINE6_SR_EXTI2 ((uint32_t)0x00000001) /*!< External Interrupt 2 */ -//#define SYSCFG_ITLINE6_SR_EXTI3 ((uint32_t)0x00000002) /*!< External Interrupt 3 */ -//#define SYSCFG_ITLINE7_SR_EXTI4 ((uint32_t)0x00000001) /*!< External Interrupt 15 to 4 */ -//#define SYSCFG_ITLINE7_SR_EXTI5 ((uint32_t)0x00000002) /*!< External Interrupt 15 to 4 */ -//#define SYSCFG_ITLINE7_SR_EXTI6 ((uint32_t)0x00000004) /*!< External Interrupt 15 to 4 */ -//#define SYSCFG_ITLINE7_SR_EXTI7 ((uint32_t)0x00000008) /*!< External Interrupt 15 to 4 */ -//#define SYSCFG_ITLINE7_SR_EXTI8 ((uint32_t)0x00000010) /*!< External Interrupt 15 to 4 */ -//#define SYSCFG_ITLINE7_SR_EXTI9 ((uint32_t)0x00000020) /*!< External Interrupt 15 to 4 */ -//#define SYSCFG_ITLINE7_SR_EXTI10 ((uint32_t)0x00000040) /*!< External Interrupt 15 to 4 */ -//#define SYSCFG_ITLINE7_SR_EXTI11 ((uint32_t)0x00000080) /*!< External Interrupt 15 to 4 */ -//#define SYSCFG_ITLINE7_SR_EXTI12 ((uint32_t)0x00000100) /*!< External Interrupt 15 to 4 */ -//#define SYSCFG_ITLINE7_SR_EXTI13 ((uint32_t)0x00000200) /*!< External Interrupt 15 to 4 */ -//#define SYSCFG_ITLINE7_SR_EXTI14 ((uint32_t)0x00000400) /*!< External Interrupt 15 to 4 */ -//#define SYSCFG_ITLINE7_SR_EXTI15 ((uint32_t)0x00000800) /*!< External Interrupt 15 to 4 */ -//#define SYSCFG_ITLINE8_SR_TSC_EOA ((uint32_t)0x00000001) /*!< Touch control EOA Interrupt */ -//#define SYSCFG_ITLINE8_SR_TSC_MCE ((uint32_t)0x00000002) /*!< Touch control MCE Interrupt */ -//#define SYSCFG_ITLINE9_SR_DMA1_CH1 ((uint32_t)0x00000001) /*!< DMA1 Channel 1 Interrupt */ -//#define SYSCFG_ITLINE10_SR_DMA1_CH2 ((uint32_t)0x00000001) /*!< DMA1 Channel 2 Interrupt */ -//#define SYSCFG_ITLINE10_SR_DMA1_CH3 ((uint32_t)0x00000002) /*!< DMA2 Channel 3 Interrupt */ -//#define SYSCFG_ITLINE10_SR_DMA2_CH1 ((uint32_t)0x00000004) /*!< DMA2 Channel 1 Interrupt */ -//#define SYSCFG_ITLINE10_SR_DMA2_CH2 ((uint32_t)0x00000008) /*!< DMA2 Channel 2 Interrupt */ -//#define SYSCFG_ITLINE11_SR_DMA1_CH4 ((uint32_t)0x00000001) /*!< DMA1 Channel 4 Interrupt */ -//#define SYSCFG_ITLINE11_SR_DMA1_CH5 ((uint32_t)0x00000002) /*!< DMA1 Channel 5 Interrupt */ -//#define SYSCFG_ITLINE11_SR_DMA1_CH6 ((uint32_t)0x00000004) /*!< DMA1 Channel 6 Interrupt */ -//#define SYSCFG_ITLINE11_SR_DMA1_CH7 ((uint32_t)0x00000008) /*!< DMA1 Channel 7 Interrupt */ -//#define SYSCFG_ITLINE11_SR_DMA2_CH3 ((uint32_t)0x00000010) /*!< DMA2 Channel 3 Interrupt */ -//#define SYSCFG_ITLINE11_SR_DMA2_CH4 ((uint32_t)0x00000020) /*!< DMA2 Channel 4 Interrupt */ -//#define SYSCFG_ITLINE11_SR_DMA2_CH5 ((uint32_t)0x00000040) /*!< DMA2 Channel 5 Interrupt */ -//#define SYSCFG_ITLINE12_SR_ADC ((uint32_t)0x00000001) /*!< ADC Interrupt */ -//#define SYSCFG_ITLINE12_SR_COMP1 ((uint32_t)0x00000002) /*!< COMP1 Interrupt -> exti[21] */ -//#define SYSCFG_ITLINE12_SR_COMP2 ((uint32_t)0x00000004) /*!< COMP2 Interrupt -> exti[22] */ -//#define SYSCFG_ITLINE13_SR_TIM1_BRK ((uint32_t)0x00000001) /*!< TIM1 BRK Interrupt */ -//#define SYSCFG_ITLINE13_SR_TIM1_UPD ((uint32_t)0x00000002) /*!< TIM1 UPD Interrupt */ -//#define SYSCFG_ITLINE13_SR_TIM1_TRG ((uint32_t)0x00000004) /*!< TIM1 TRG Interrupt */ -//#define SYSCFG_ITLINE13_SR_TIM1_CCU ((uint32_t)0x00000008) /*!< TIM1 CCU Interrupt */ -//#define SYSCFG_ITLINE14_SR_TIM1_CC ((uint32_t)0x00000001) /*!< TIM1 CC Interrupt */ -//#define SYSCFG_ITLINE15_SR_TIM2_GLB ((uint32_t)0x00000001) /*!< TIM2 GLB Interrupt */ -//#define SYSCFG_ITLINE16_SR_TIM3_GLB ((uint32_t)0x00000001) /*!< TIM3 GLB Interrupt */ -//#define SYSCFG_ITLINE17_SR_DAC ((uint32_t)0x00000001) /*!< DAC Interrupt */ -//#define SYSCFG_ITLINE17_SR_TIM6_GLB ((uint32_t)0x00000002) /*!< TIM6 GLB Interrupt */ -//#define SYSCFG_ITLINE18_SR_TIM7_GLB ((uint32_t)0x00000001) /*!< TIM7 GLB Interrupt */ -//#define SYSCFG_ITLINE19_SR_TIM14_GLB ((uint32_t)0x00000001) /*!< TIM14 GLB Interrupt */ -//#define SYSCFG_ITLINE20_SR_TIM15_GLB ((uint32_t)0x00000001) /*!< TIM15 GLB Interrupt */ -//#define SYSCFG_ITLINE21_SR_TIM16_GLB ((uint32_t)0x00000001) /*!< TIM16 GLB Interrupt */ -//#define SYSCFG_ITLINE22_SR_TIM17_GLB ((uint32_t)0x00000001) /*!< TIM17 GLB Interrupt */ -//#define SYSCFG_ITLINE23_SR_I2C1_GLB ((uint32_t)0x00000001) /*!< I2C1 GLB Interrupt -> exti[23] */ -//#define SYSCFG_ITLINE24_SR_I2C2_GLB ((uint32_t)0x00000001) /*!< I2C2 GLB Interrupt */ -//#define SYSCFG_ITLINE25_SR_SPI1 ((uint32_t)0x00000001) /*!< SPI1 Interrupt */ -//#define SYSCFG_ITLINE26_SR_SPI2 ((uint32_t)0x00000001) /*!< SPI2 Interrupt */ -//#define SYSCFG_ITLINE27_SR_USART1_GLB ((uint32_t)0x00000001) /*!< USART1 GLB Interrupt -> exti[25] */ -//#define SYSCFG_ITLINE28_SR_USART2_GLB ((uint32_t)0x00000001) /*!< USART2 GLB Interrupt -> exti[26] */ -//#define SYSCFG_ITLINE29_SR_USART3_GLB ((uint32_t)0x00000001) /*!< USART3 GLB Interrupt -> exti[28] */ -//#define SYSCFG_ITLINE29_SR_USART4_GLB ((uint32_t)0x00000002) /*!< USART4 GLB Interrupt */ -//#define SYSCFG_ITLINE29_SR_USART5_GLB ((uint32_t)0x00000004) /*!< USART5 GLB Interrupt */ -//#define SYSCFG_ITLINE29_SR_USART6_GLB ((uint32_t)0x00000008) /*!< USART6 GLB Interrupt */ -//#define SYSCFG_ITLINE29_SR_USART7_GLB ((uint32_t)0x00000010) /*!< USART7 GLB Interrupt */ -//#define SYSCFG_ITLINE29_SR_USART8_GLB ((uint32_t)0x00000020) /*!< USART8 GLB Interrupt */ -//#define SYSCFG_ITLINE30_SR_CAN ((uint32_t)0x00000001) /*!< CAN Interrupt */ -//#define SYSCFG_ITLINE30_SR_CEC ((uint32_t)0x00000002) /*!< CEC Interrupt */ - -/******************************************************************************/ -/* */ -/* Timers (TIM) */ -/* */ -/******************************************************************************/ -/******************* Bit definition for TIM_CR1 register ********************/ -#define TIM_CR1_CEN ((uint16_t)0x0001) /*! - -/** @addtogroup Exported_types - * @{ - */ - -typedef enum -{ - RESET = 0, - SET = !RESET -} FlagStatus, ITStatus; - -typedef enum -{ - DISABLE = 0, - ENABLE = !DISABLE -} FunctionalState; -#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE)) - -typedef enum -{ - ERROR = 0, - SUCCESS = !ERROR -} ErrorStatus; - -/** - * @brief Analog to Digital Converter - */ - -typedef struct -{ - __IO uint32_t ISR; /*!< ADC Interrupt and Status register, Address offset:0x00 */ - __IO uint32_t IER; /*!< ADC Interrupt Enable register, Address offset:0x04 */ - __IO uint32_t CR; /*!< ADC Control register, Address offset:0x08 */ - __IO uint32_t CFGR1; /*!< ADC Configuration register 1, Address offset:0x0C */ - __IO uint32_t CFGR2; /*!< ADC Configuration register 2, Address offset:0x10 */ - __IO uint32_t SMPR; /*!< ADC Sampling time register, Address offset:0x14 */ - uint32_t RESERVED1; /*!< Reserved, 0x18 */ - uint32_t RESERVED2; /*!< Reserved, 0x1C */ - __IO uint32_t TR; /*!< ADC watchdog threshold register, Address offset:0x20 */ - uint32_t RESERVED3; /*!< Reserved, 0x24 */ - __IO uint32_t CHSELR; /*!< ADC channel selection register, Address offset:0x28 */ - uint32_t RESERVED4[5]; /*!< Reserved, 0x2C */ - __IO uint32_t DR; /*!< ADC data register, Address offset:0x40 */ -} ADC_TypeDef; - -typedef struct -{ - __IO uint32_t CCR; /*Address offset:0x308 */ - __IO uint32_t CR2; /*Address offset:0x30C */ -} ADC_Common_TypeDef; - -/** - * @brief Comparator - */ - -typedef struct -{ - __IO uint32_t RESERVED[7]; /*!< Reserved, Address offset: 0x18-0x00 */ - __IO uint32_t CSR; /*!< COMP comparator control and status register, Address offset: 0x1C */ -} COMP_TypeDef; - -/** - * @brief DAC Configuration - */ -typedef struct -{ - __IO uint32_t RESERVED[8]; /*!< Reserved, Address offset: 0x1C-0x00 */ - __IO uint32_t CTRL; /*!< DAC configuration register Address offset: 0x20 */ - __IO uint32_t DATA1; /*!< DAC1 Input data Address offset: 0x24 */ - __IO uint32_t DATA2; /*!< DAC2 Input data Address offset: 0x28 */ -}DAC_TypeDef; - -/** - * @brief CRC calculation unit - */ - -typedef struct -{ - __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ - __IO uint32_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ - __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ - uint32_t RESERVED2; /*!< Reserved, 0x0C */ - __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */ - __IO uint32_t RESERVED3; /*!< Reserved, 0x14 */ -} CRC_TypeDef; - -/** - * @brief Clock Recovery System - */ -typedef struct -{ -__IO uint32_t CR; /*!< CRS ccontrol register, Address offset: 0x00 */ -__IO uint32_t CFGR; /*!< CRS configuration register, Address offset: 0x04 */ -__IO uint32_t ISR; /*!< CRS interrupt and status register, Address offset: 0x08 */ -__IO uint32_t ICR; /*!< CRS interrupt flag clear register, Address offset: 0x0C */ -} CRS_TypeDef; - -/** - * @brief Debug MCU - */ - -typedef struct -{ - __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ - __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ - __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */ - __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */ -}DBGMCU_TypeDef; - -/** - * @brief DMA Controller - */ - -typedef struct -{ - __IO uint32_t CCR; /*!< DMA channel x configuration register */ - __IO uint32_t CNDTR; /*!< DMA channel x number of data register */ - __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */ - __IO uint32_t CMAR; /*!< DMA channel x memory address register */ -} DMA_Channel_TypeDef; - -typedef struct -{ - __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */ - __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */ -}DMA_TypeDef; - -/** - * @brief External Interrupt/Event Controller - */ - -typedef struct -{ - __IO uint32_t IMR; /*! exti[31] Interrupt */ -//#define SYSCFG_ITLINE1_SR_VDDIO2 ((uint32_t)0x00000002) /*!< VDDIO2 -> exti[16] Interrupt */ -//#define SYSCFG_ITLINE2_SR_RTC_WAKEUP ((uint32_t)0x00000001) /*!< RTC WAKEUP -> exti[20] Interrupt */ -//#define SYSCFG_ITLINE2_SR_RTC_TSTAMP ((uint32_t)0x00000002) /*!< RTC Time Stamp -> exti[19] interrupt */ -//#define SYSCFG_ITLINE2_SR_RTC_ALRA ((uint32_t)0x00000003) /*!< RTC Alarm -> exti[17] interrupt .... */ -//#define SYSCFG_ITLINE3_SR_FLASH_ITF ((uint32_t)0x00000001) /*!< Flash ITF Interrupt */ -//#define SYSCFG_ITLINE4_SR_CRS ((uint32_t)0x00000001) /*!< CRS interrupt */ -//#define SYSCFG_ITLINE4_SR_CLK_CTRL ((uint32_t)0x00000002) /*!< CLK CTRL interrupt */ -//#define SYSCFG_ITLINE5_SR_EXTI0 ((uint32_t)0x00000001) /*!< External Interrupt 0 */ -//#define SYSCFG_ITLINE5_SR_EXTI1 ((uint32_t)0x00000002) /*!< External Interrupt 1 */ -//#define SYSCFG_ITLINE6_SR_EXTI2 ((uint32_t)0x00000001) /*!< External Interrupt 2 */ -//#define SYSCFG_ITLINE6_SR_EXTI3 ((uint32_t)0x00000002) /*!< External Interrupt 3 */ -//#define SYSCFG_ITLINE7_SR_EXTI4 ((uint32_t)0x00000001) /*!< External Interrupt 15 to 4 */ -//#define SYSCFG_ITLINE7_SR_EXTI5 ((uint32_t)0x00000002) /*!< External Interrupt 15 to 4 */ -//#define SYSCFG_ITLINE7_SR_EXTI6 ((uint32_t)0x00000004) /*!< External Interrupt 15 to 4 */ -//#define SYSCFG_ITLINE7_SR_EXTI7 ((uint32_t)0x00000008) /*!< External Interrupt 15 to 4 */ -//#define SYSCFG_ITLINE7_SR_EXTI8 ((uint32_t)0x00000010) /*!< External Interrupt 15 to 4 */ -//#define SYSCFG_ITLINE7_SR_EXTI9 ((uint32_t)0x00000020) /*!< External Interrupt 15 to 4 */ -//#define SYSCFG_ITLINE7_SR_EXTI10 ((uint32_t)0x00000040) /*!< External Interrupt 15 to 4 */ -//#define SYSCFG_ITLINE7_SR_EXTI11 ((uint32_t)0x00000080) /*!< External Interrupt 15 to 4 */ -//#define SYSCFG_ITLINE7_SR_EXTI12 ((uint32_t)0x00000100) /*!< External Interrupt 15 to 4 */ -//#define SYSCFG_ITLINE7_SR_EXTI13 ((uint32_t)0x00000200) /*!< External Interrupt 15 to 4 */ -//#define SYSCFG_ITLINE7_SR_EXTI14 ((uint32_t)0x00000400) /*!< External Interrupt 15 to 4 */ -//#define SYSCFG_ITLINE7_SR_EXTI15 ((uint32_t)0x00000800) /*!< External Interrupt 15 to 4 */ -//#define SYSCFG_ITLINE8_SR_TSC_EOA ((uint32_t)0x00000001) /*!< Touch control EOA Interrupt */ -//#define SYSCFG_ITLINE8_SR_TSC_MCE ((uint32_t)0x00000002) /*!< Touch control MCE Interrupt */ -//#define SYSCFG_ITLINE9_SR_DMA1_CH1 ((uint32_t)0x00000001) /*!< DMA1 Channel 1 Interrupt */ -//#define SYSCFG_ITLINE10_SR_DMA1_CH2 ((uint32_t)0x00000001) /*!< DMA1 Channel 2 Interrupt */ -//#define SYSCFG_ITLINE10_SR_DMA1_CH3 ((uint32_t)0x00000002) /*!< DMA2 Channel 3 Interrupt */ -//#define SYSCFG_ITLINE10_SR_DMA2_CH1 ((uint32_t)0x00000004) /*!< DMA2 Channel 1 Interrupt */ -//#define SYSCFG_ITLINE10_SR_DMA2_CH2 ((uint32_t)0x00000008) /*!< DMA2 Channel 2 Interrupt */ -//#define SYSCFG_ITLINE11_SR_DMA1_CH4 ((uint32_t)0x00000001) /*!< DMA1 Channel 4 Interrupt */ -//#define SYSCFG_ITLINE11_SR_DMA1_CH5 ((uint32_t)0x00000002) /*!< DMA1 Channel 5 Interrupt */ -//#define SYSCFG_ITLINE11_SR_DMA1_CH6 ((uint32_t)0x00000004) /*!< DMA1 Channel 6 Interrupt */ -//#define SYSCFG_ITLINE11_SR_DMA1_CH7 ((uint32_t)0x00000008) /*!< DMA1 Channel 7 Interrupt */ -//#define SYSCFG_ITLINE11_SR_DMA2_CH3 ((uint32_t)0x00000010) /*!< DMA2 Channel 3 Interrupt */ -//#define SYSCFG_ITLINE11_SR_DMA2_CH4 ((uint32_t)0x00000020) /*!< DMA2 Channel 4 Interrupt */ -//#define SYSCFG_ITLINE11_SR_DMA2_CH5 ((uint32_t)0x00000040) /*!< DMA2 Channel 5 Interrupt */ -//#define SYSCFG_ITLINE12_SR_ADC ((uint32_t)0x00000001) /*!< ADC Interrupt */ -//#define SYSCFG_ITLINE12_SR_COMP1 ((uint32_t)0x00000002) /*!< COMP1 Interrupt -> exti[21] */ -//#define SYSCFG_ITLINE12_SR_COMP2 ((uint32_t)0x00000004) /*!< COMP2 Interrupt -> exti[22] */ -//#define SYSCFG_ITLINE13_SR_TIM1_BRK ((uint32_t)0x00000001) /*!< TIM1 BRK Interrupt */ -//#define SYSCFG_ITLINE13_SR_TIM1_UPD ((uint32_t)0x00000002) /*!< TIM1 UPD Interrupt */ -//#define SYSCFG_ITLINE13_SR_TIM1_TRG ((uint32_t)0x00000004) /*!< TIM1 TRG Interrupt */ -//#define SYSCFG_ITLINE13_SR_TIM1_CCU ((uint32_t)0x00000008) /*!< TIM1 CCU Interrupt */ -//#define SYSCFG_ITLINE14_SR_TIM1_CC ((uint32_t)0x00000001) /*!< TIM1 CC Interrupt */ -//#define SYSCFG_ITLINE15_SR_TIM2_GLB ((uint32_t)0x00000001) /*!< TIM2 GLB Interrupt */ -//#define SYSCFG_ITLINE16_SR_TIM3_GLB ((uint32_t)0x00000001) /*!< TIM3 GLB Interrupt */ -//#define SYSCFG_ITLINE17_SR_DAC ((uint32_t)0x00000001) /*!< DAC Interrupt */ -//#define SYSCFG_ITLINE17_SR_TIM6_GLB ((uint32_t)0x00000002) /*!< TIM6 GLB Interrupt */ -//#define SYSCFG_ITLINE18_SR_TIM7_GLB ((uint32_t)0x00000001) /*!< TIM7 GLB Interrupt */ -//#define SYSCFG_ITLINE19_SR_TIM14_GLB ((uint32_t)0x00000001) /*!< TIM14 GLB Interrupt */ -//#define SYSCFG_ITLINE20_SR_TIM15_GLB ((uint32_t)0x00000001) /*!< TIM15 GLB Interrupt */ -//#define SYSCFG_ITLINE21_SR_TIM16_GLB ((uint32_t)0x00000001) /*!< TIM16 GLB Interrupt */ -//#define SYSCFG_ITLINE22_SR_TIM17_GLB ((uint32_t)0x00000001) /*!< TIM17 GLB Interrupt */ -//#define SYSCFG_ITLINE23_SR_I2C1_GLB ((uint32_t)0x00000001) /*!< I2C1 GLB Interrupt -> exti[23] */ -//#define SYSCFG_ITLINE24_SR_I2C2_GLB ((uint32_t)0x00000001) /*!< I2C2 GLB Interrupt */ -//#define SYSCFG_ITLINE25_SR_SPI1 ((uint32_t)0x00000001) /*!< SPI1 Interrupt */ -//#define SYSCFG_ITLINE26_SR_SPI2 ((uint32_t)0x00000001) /*!< SPI2 Interrupt */ -//#define SYSCFG_ITLINE27_SR_USART1_GLB ((uint32_t)0x00000001) /*!< USART1 GLB Interrupt -> exti[25] */ -//#define SYSCFG_ITLINE28_SR_USART2_GLB ((uint32_t)0x00000001) /*!< USART2 GLB Interrupt -> exti[26] */ -//#define SYSCFG_ITLINE29_SR_USART3_GLB ((uint32_t)0x00000001) /*!< USART3 GLB Interrupt -> exti[28] */ -//#define SYSCFG_ITLINE29_SR_USART4_GLB ((uint32_t)0x00000002) /*!< USART4 GLB Interrupt */ -//#define SYSCFG_ITLINE29_SR_USART5_GLB ((uint32_t)0x00000004) /*!< USART5 GLB Interrupt */ -//#define SYSCFG_ITLINE29_SR_USART6_GLB ((uint32_t)0x00000008) /*!< USART6 GLB Interrupt */ -//#define SYSCFG_ITLINE29_SR_USART7_GLB ((uint32_t)0x00000010) /*!< USART7 GLB Interrupt */ -//#define SYSCFG_ITLINE29_SR_USART8_GLB ((uint32_t)0x00000020) /*!< USART8 GLB Interrupt */ -//#define SYSCFG_ITLINE30_SR_CAN ((uint32_t)0x00000001) /*!< CAN Interrupt */ -//#define SYSCFG_ITLINE30_SR_CEC ((uint32_t)0x00000002) /*!< CEC Interrupt */ - -/******************************************************************************/ -/* */ -/* Timers (TIM) */ -/* */ -/******************************************************************************/ -/******************* Bit definition for TIM_CR1 register ********************/ -#define TIM_CR1_CEN ((uint16_t)0x0001) /*! - -/** @addtogroup Exported_types - * @{ - */ - -typedef enum -{ - RESET = 0, - SET = !RESET -} FlagStatus, ITStatus; - -typedef enum -{ - DISABLE = 0, - ENABLE = !DISABLE -} FunctionalState; -#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE)) - -typedef enum -{ - ERROR = 0, - SUCCESS = !ERROR -} ErrorStatus; - -/** - * @brief Analog to Digital Converter - */ - -typedef struct -{ - __IO uint32_t ISR; /*!< ADC Interrupt and Status register, Address offset:0x00 */ - __IO uint32_t IER; /*!< ADC Interrupt Enable register, Address offset:0x04 */ - __IO uint32_t CR; /*!< ADC Control register, Address offset:0x08 */ - __IO uint32_t CFGR1; /*!< ADC Configuration register 1, Address offset:0x0C */ - __IO uint32_t CFGR2; /*!< ADC Configuration register 2, Address offset:0x10 */ - __IO uint32_t SMPR; /*!< ADC Sampling time register, Address offset:0x14 */ - uint32_t RESERVED1; /*!< Reserved, 0x18 */ - uint32_t RESERVED2; /*!< Reserved, 0x1C */ - __IO uint32_t TR; /*!< ADC watchdog threshold register, Address offset:0x20 */ - uint32_t RESERVED3; /*!< Reserved, 0x24 */ - __IO uint32_t CHSELR; /*!< ADC channel selection register, Address offset:0x28 */ - uint32_t RESERVED4[5]; /*!< Reserved, 0x2C */ - __IO uint32_t DR; /*!< ADC data register, Address offset:0x40 */ -} ADC_TypeDef; - -typedef struct -{ - __IO uint32_t CCR; /*Address offset:0x308 */ - __IO uint32_t CR2; /*Address offset:0x30C */ -} ADC_Common_TypeDef; - -/** - * @brief Comparator - */ - -typedef struct -{ - __IO uint32_t RESERVED[7]; /*!< Reserved, Address offset: 0x18-0x00 */ - __IO uint32_t CSR; /*!< COMP comparator control and status register, Address offset: 0x1C */ -} COMP_TypeDef; - -/** - * @brief OPA - */ -typedef struct -{ - __IO uint32_t RESERVED[12]; /*!< Reserved, Address offset: 0x2C-0x00 */ - __IO uint32_t CR; /*!< COMP comparator control and status register, Address offset: 0x30 */ -} OPA_TypeDef; - -/** - * @brief DAC Configuration - */ -typedef struct -{ - __IO uint32_t RESERVED[8]; /*!< Reserved, Address offset: 0x1C-0x00 */ - __IO uint32_t CTRL; /*!< DAC configuration register Address offset: 0x20 */ - __IO uint32_t DATA1; /*!< DAC1 Input data Address offset: 0x24 */ - __IO uint32_t DATA2; /*!< DAC2 Input data Address offset: 0x28 */ -}DAC_TypeDef; - -/** - * @brief CRC calculation unit - */ - -typedef struct -{ - __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ - __IO uint32_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ - __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ - uint32_t RESERVED2; /*!< Reserved, 0x0C */ - __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */ - __IO uint32_t RESERVED3; /*!< Reserved, 0x14 */ -} CRC_TypeDef; - -/** - * @brief Clock Recovery System - */ -typedef struct -{ -__IO uint32_t CR; /*!< CRS ccontrol register, Address offset: 0x00 */ -__IO uint32_t CFGR; /*!< CRS configuration register, Address offset: 0x04 */ -__IO uint32_t ISR; /*!< CRS interrupt and status register, Address offset: 0x08 */ -__IO uint32_t ICR; /*!< CRS interrupt flag clear register, Address offset: 0x0C */ -} CRS_TypeDef; - -/** - * @brief Debug MCU - */ - -typedef struct -{ - __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ - __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ - __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */ - __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */ -}DBGMCU_TypeDef; - -/** - * @brief DMA Controller - */ - -typedef struct -{ - __IO uint32_t CCR; /*!< DMA channel x configuration register */ - __IO uint32_t CNDTR; /*!< DMA channel x number of data register */ - __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */ - __IO uint32_t CMAR; /*!< DMA channel x memory address register */ -} DMA_Channel_TypeDef; - -typedef struct -{ - __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */ - __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */ -}DMA_TypeDef; - -/** - * @brief External Interrupt/Event Controller - */ - -typedef struct -{ - __IO uint32_t IMR; /*! exti[31] Interrupt */ -//#define SYSCFG_ITLINE1_SR_VDDIO2 ((uint32_t)0x00000002) /*!< VDDIO2 -> exti[16] Interrupt */ -//#define SYSCFG_ITLINE2_SR_RTC_WAKEUP ((uint32_t)0x00000001) /*!< RTC WAKEUP -> exti[20] Interrupt */ -//#define SYSCFG_ITLINE2_SR_RTC_TSTAMP ((uint32_t)0x00000002) /*!< RTC Time Stamp -> exti[19] interrupt */ -//#define SYSCFG_ITLINE2_SR_RTC_ALRA ((uint32_t)0x00000003) /*!< RTC Alarm -> exti[17] interrupt .... */ -//#define SYSCFG_ITLINE3_SR_FLASH_ITF ((uint32_t)0x00000001) /*!< Flash ITF Interrupt */ -//#define SYSCFG_ITLINE4_SR_CRS ((uint32_t)0x00000001) /*!< CRS interrupt */ -//#define SYSCFG_ITLINE4_SR_CLK_CTRL ((uint32_t)0x00000002) /*!< CLK CTRL interrupt */ -//#define SYSCFG_ITLINE5_SR_EXTI0 ((uint32_t)0x00000001) /*!< External Interrupt 0 */ -//#define SYSCFG_ITLINE5_SR_EXTI1 ((uint32_t)0x00000002) /*!< External Interrupt 1 */ -//#define SYSCFG_ITLINE6_SR_EXTI2 ((uint32_t)0x00000001) /*!< External Interrupt 2 */ -//#define SYSCFG_ITLINE6_SR_EXTI3 ((uint32_t)0x00000002) /*!< External Interrupt 3 */ -//#define SYSCFG_ITLINE7_SR_EXTI4 ((uint32_t)0x00000001) /*!< External Interrupt 15 to 4 */ -//#define SYSCFG_ITLINE7_SR_EXTI5 ((uint32_t)0x00000002) /*!< External Interrupt 15 to 4 */ -//#define SYSCFG_ITLINE7_SR_EXTI6 ((uint32_t)0x00000004) /*!< External Interrupt 15 to 4 */ -//#define SYSCFG_ITLINE7_SR_EXTI7 ((uint32_t)0x00000008) /*!< External Interrupt 15 to 4 */ -//#define SYSCFG_ITLINE7_SR_EXTI8 ((uint32_t)0x00000010) /*!< External Interrupt 15 to 4 */ -//#define SYSCFG_ITLINE7_SR_EXTI9 ((uint32_t)0x00000020) /*!< External Interrupt 15 to 4 */ -//#define SYSCFG_ITLINE7_SR_EXTI10 ((uint32_t)0x00000040) /*!< External Interrupt 15 to 4 */ -//#define SYSCFG_ITLINE7_SR_EXTI11 ((uint32_t)0x00000080) /*!< External Interrupt 15 to 4 */ -//#define SYSCFG_ITLINE7_SR_EXTI12 ((uint32_t)0x00000100) /*!< External Interrupt 15 to 4 */ -//#define SYSCFG_ITLINE7_SR_EXTI13 ((uint32_t)0x00000200) /*!< External Interrupt 15 to 4 */ -//#define SYSCFG_ITLINE7_SR_EXTI14 ((uint32_t)0x00000400) /*!< External Interrupt 15 to 4 */ -//#define SYSCFG_ITLINE7_SR_EXTI15 ((uint32_t)0x00000800) /*!< External Interrupt 15 to 4 */ -//#define SYSCFG_ITLINE8_SR_TSC_EOA ((uint32_t)0x00000001) /*!< Touch control EOA Interrupt */ -//#define SYSCFG_ITLINE8_SR_TSC_MCE ((uint32_t)0x00000002) /*!< Touch control MCE Interrupt */ -//#define SYSCFG_ITLINE9_SR_DMA1_CH1 ((uint32_t)0x00000001) /*!< DMA1 Channel 1 Interrupt */ -//#define SYSCFG_ITLINE10_SR_DMA1_CH2 ((uint32_t)0x00000001) /*!< DMA1 Channel 2 Interrupt */ -//#define SYSCFG_ITLINE10_SR_DMA1_CH3 ((uint32_t)0x00000002) /*!< DMA2 Channel 3 Interrupt */ -//#define SYSCFG_ITLINE10_SR_DMA2_CH1 ((uint32_t)0x00000004) /*!< DMA2 Channel 1 Interrupt */ -//#define SYSCFG_ITLINE10_SR_DMA2_CH2 ((uint32_t)0x00000008) /*!< DMA2 Channel 2 Interrupt */ -//#define SYSCFG_ITLINE11_SR_DMA1_CH4 ((uint32_t)0x00000001) /*!< DMA1 Channel 4 Interrupt */ -//#define SYSCFG_ITLINE11_SR_DMA1_CH5 ((uint32_t)0x00000002) /*!< DMA1 Channel 5 Interrupt */ -//#define SYSCFG_ITLINE11_SR_DMA1_CH6 ((uint32_t)0x00000004) /*!< DMA1 Channel 6 Interrupt */ -//#define SYSCFG_ITLINE11_SR_DMA1_CH7 ((uint32_t)0x00000008) /*!< DMA1 Channel 7 Interrupt */ -//#define SYSCFG_ITLINE11_SR_DMA2_CH3 ((uint32_t)0x00000010) /*!< DMA2 Channel 3 Interrupt */ -//#define SYSCFG_ITLINE11_SR_DMA2_CH4 ((uint32_t)0x00000020) /*!< DMA2 Channel 4 Interrupt */ -//#define SYSCFG_ITLINE11_SR_DMA2_CH5 ((uint32_t)0x00000040) /*!< DMA2 Channel 5 Interrupt */ -//#define SYSCFG_ITLINE12_SR_ADC ((uint32_t)0x00000001) /*!< ADC Interrupt */ -//#define SYSCFG_ITLINE12_SR_COMP1 ((uint32_t)0x00000002) /*!< COMP1 Interrupt -> exti[21] */ -//#define SYSCFG_ITLINE12_SR_COMP2 ((uint32_t)0x00000004) /*!< COMP2 Interrupt -> exti[22] */ -//#define SYSCFG_ITLINE13_SR_TIM1_BRK ((uint32_t)0x00000001) /*!< TIM1 BRK Interrupt */ -//#define SYSCFG_ITLINE13_SR_TIM1_UPD ((uint32_t)0x00000002) /*!< TIM1 UPD Interrupt */ -//#define SYSCFG_ITLINE13_SR_TIM1_TRG ((uint32_t)0x00000004) /*!< TIM1 TRG Interrupt */ -//#define SYSCFG_ITLINE13_SR_TIM1_CCU ((uint32_t)0x00000008) /*!< TIM1 CCU Interrupt */ -//#define SYSCFG_ITLINE14_SR_TIM1_CC ((uint32_t)0x00000001) /*!< TIM1 CC Interrupt */ -//#define SYSCFG_ITLINE15_SR_TIM2_GLB ((uint32_t)0x00000001) /*!< TIM2 GLB Interrupt */ -//#define SYSCFG_ITLINE16_SR_TIM3_GLB ((uint32_t)0x00000001) /*!< TIM3 GLB Interrupt */ -//#define SYSCFG_ITLINE17_SR_DAC ((uint32_t)0x00000001) /*!< DAC Interrupt */ -//#define SYSCFG_ITLINE17_SR_TIM6_GLB ((uint32_t)0x00000002) /*!< TIM6 GLB Interrupt */ -//#define SYSCFG_ITLINE18_SR_TIM7_GLB ((uint32_t)0x00000001) /*!< TIM7 GLB Interrupt */ -//#define SYSCFG_ITLINE19_SR_TIM14_GLB ((uint32_t)0x00000001) /*!< TIM14 GLB Interrupt */ -//#define SYSCFG_ITLINE20_SR_TIM15_GLB ((uint32_t)0x00000001) /*!< TIM15 GLB Interrupt */ -//#define SYSCFG_ITLINE21_SR_TIM16_GLB ((uint32_t)0x00000001) /*!< TIM16 GLB Interrupt */ -//#define SYSCFG_ITLINE22_SR_TIM17_GLB ((uint32_t)0x00000001) /*!< TIM17 GLB Interrupt */ -//#define SYSCFG_ITLINE23_SR_I2C1_GLB ((uint32_t)0x00000001) /*!< I2C1 GLB Interrupt -> exti[23] */ -//#define SYSCFG_ITLINE24_SR_I2C2_GLB ((uint32_t)0x00000001) /*!< I2C2 GLB Interrupt */ -//#define SYSCFG_ITLINE25_SR_SPI1 ((uint32_t)0x00000001) /*!< SPI1 Interrupt */ -//#define SYSCFG_ITLINE26_SR_SPI2 ((uint32_t)0x00000001) /*!< SPI2 Interrupt */ -//#define SYSCFG_ITLINE27_SR_USART1_GLB ((uint32_t)0x00000001) /*!< USART1 GLB Interrupt -> exti[25] */ -//#define SYSCFG_ITLINE28_SR_USART2_GLB ((uint32_t)0x00000001) /*!< USART2 GLB Interrupt -> exti[26] */ -//#define SYSCFG_ITLINE29_SR_USART3_GLB ((uint32_t)0x00000001) /*!< USART3 GLB Interrupt -> exti[28] */ -//#define SYSCFG_ITLINE29_SR_USART4_GLB ((uint32_t)0x00000002) /*!< USART4 GLB Interrupt */ -//#define SYSCFG_ITLINE29_SR_USART5_GLB ((uint32_t)0x00000004) /*!< USART5 GLB Interrupt */ -//#define SYSCFG_ITLINE29_SR_USART6_GLB ((uint32_t)0x00000008) /*!< USART6 GLB Interrupt */ -//#define SYSCFG_ITLINE29_SR_USART7_GLB ((uint32_t)0x00000010) /*!< USART7 GLB Interrupt */ -//#define SYSCFG_ITLINE29_SR_USART8_GLB ((uint32_t)0x00000020) /*!< USART8 GLB Interrupt */ -//#define SYSCFG_ITLINE30_SR_CAN ((uint32_t)0x00000001) /*!< CAN Interrupt */ -//#define SYSCFG_ITLINE30_SR_CEC ((uint32_t)0x00000002) /*!< CEC Interrupt */ - -/******************************************************************************/ -/* */ -/* Timers (TIM) */ -/* */ -/******************************************************************************/ -/******************* Bit definition for TIM_CR1 register ********************/ -#define TIM_CR1_CEN ((uint16_t)0x0001) /*! - -/** @addtogroup Exported_types - * @{ - */ - -typedef enum -{ - RESET = 0, - SET = !RESET -} FlagStatus, ITStatus; - -typedef enum -{ - DISABLE = 0, - ENABLE = !DISABLE -} FunctionalState; -#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE)) - -typedef enum -{ - ERROR = 0, - SUCCESS = !ERROR -} ErrorStatus; - -/** - * @brief Analog to Digital Converter - */ - -typedef struct -{ - __IO uint32_t ISR; /*!< ADC Interrupt and Status register, Address offset:0x00 */ - __IO uint32_t IER; /*!< ADC Interrupt Enable register, Address offset:0x04 */ - __IO uint32_t CR; /*!< ADC Control register, Address offset:0x08 */ - __IO uint32_t CFGR1; /*!< ADC Configuration register 1, Address offset:0x0C */ - __IO uint32_t CFGR2; /*!< ADC Configuration register 2, Address offset:0x10 */ - __IO uint32_t SMPR; /*!< ADC Sampling time register, Address offset:0x14 */ - uint32_t RESERVED1; /*!< Reserved, 0x18 */ - uint32_t RESERVED2; /*!< Reserved, 0x1C */ - __IO uint32_t TR; /*!< ADC watchdog threshold register, Address offset:0x20 */ - uint32_t RESERVED3; /*!< Reserved, 0x24 */ - __IO uint32_t CHSELR; /*!< ADC channel selection register, Address offset:0x28 */ - uint32_t RESERVED4[5]; /*!< Reserved, 0x2C */ - __IO uint32_t DR; /*!< ADC data register, Address offset:0x40 */ -} ADC_TypeDef; - -typedef struct -{ - __IO uint32_t CCR; /*Address offset:0x308 */ - __IO uint32_t CR2; /*Address offset:0x30C */ -} ADC_Common_TypeDef; - -/** - * @brief Comparator - */ - -typedef struct -{ - __IO uint32_t RESERVED[7]; /*!< Reserved, Address offset: 0x18-0x00 */ - __IO uint32_t CSR; /*!< COMP comparator control and status register, Address offset: 0x1C */ -} COMP_TypeDef; - -/** - * @brief OPA - */ -typedef struct -{ - __IO uint32_t RESERVED[12]; /*!< Reserved, Address offset: 0x2C-0x00 */ - __IO uint32_t CR; /*!< COMP comparator control and status register, Address offset: 0x30 */ -} OPA_TypeDef; - -/** - * @brief DAC Configuration - */ -typedef struct -{ - __IO uint32_t RESERVED[8]; /*!< Reserved, Address offset: 0x1C-0x00 */ - __IO uint32_t CTRL; /*!< DAC configuration register Address offset: 0x20 */ - __IO uint32_t DATA1; /*!< DAC1 Input data Address offset: 0x24 */ - __IO uint32_t DATA2; /*!< DAC2 Input data Address offset: 0x28 */ -}DAC_TypeDef; - -/** - * @brief CRC calculation unit - */ - -typedef struct -{ - __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ - __IO uint32_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ - __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ - uint32_t RESERVED2; /*!< Reserved, 0x0C */ - __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */ - __IO uint32_t RESERVED3; /*!< Reserved, 0x14 */ -} CRC_TypeDef; - -/** - * @brief Clock Recovery System - */ -typedef struct -{ -__IO uint32_t CR; /*!< CRS ccontrol register, Address offset: 0x00 */ -__IO uint32_t CFGR; /*!< CRS configuration register, Address offset: 0x04 */ -__IO uint32_t ISR; /*!< CRS interrupt and status register, Address offset: 0x08 */ -__IO uint32_t ICR; /*!< CRS interrupt flag clear register, Address offset: 0x0C */ -} CRS_TypeDef; - -/** - * @brief Debug MCU - */ - -typedef struct -{ - __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ - __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ - __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */ - __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */ -}DBGMCU_TypeDef; - -/** - * @brief DMA Controller - */ - -typedef struct -{ - __IO uint32_t CCR; /*!< DMA channel x configuration register */ - __IO uint32_t CNDTR; /*!< DMA channel x number of data register */ - __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */ - __IO uint32_t CMAR; /*!< DMA channel x memory address register */ -} DMA_Channel_TypeDef; - -typedef struct -{ - __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */ - __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */ -}DMA_TypeDef; - -/** - * @brief External Interrupt/Event Controller - */ - -typedef struct -{ - __IO uint32_t IMR; /*! exti[31] Interrupt */ -//#define SYSCFG_ITLINE1_SR_VDDIO2 ((uint32_t)0x00000002) /*!< VDDIO2 -> exti[16] Interrupt */ -//#define SYSCFG_ITLINE2_SR_RTC_WAKEUP ((uint32_t)0x00000001) /*!< RTC WAKEUP -> exti[20] Interrupt */ -//#define SYSCFG_ITLINE2_SR_RTC_TSTAMP ((uint32_t)0x00000002) /*!< RTC Time Stamp -> exti[19] interrupt */ -//#define SYSCFG_ITLINE2_SR_RTC_ALRA ((uint32_t)0x00000003) /*!< RTC Alarm -> exti[17] interrupt .... */ -//#define SYSCFG_ITLINE3_SR_FLASH_ITF ((uint32_t)0x00000001) /*!< Flash ITF Interrupt */ -//#define SYSCFG_ITLINE4_SR_CRS ((uint32_t)0x00000001) /*!< CRS interrupt */ -//#define SYSCFG_ITLINE4_SR_CLK_CTRL ((uint32_t)0x00000002) /*!< CLK CTRL interrupt */ -//#define SYSCFG_ITLINE5_SR_EXTI0 ((uint32_t)0x00000001) /*!< External Interrupt 0 */ -//#define SYSCFG_ITLINE5_SR_EXTI1 ((uint32_t)0x00000002) /*!< External Interrupt 1 */ -//#define SYSCFG_ITLINE6_SR_EXTI2 ((uint32_t)0x00000001) /*!< External Interrupt 2 */ -//#define SYSCFG_ITLINE6_SR_EXTI3 ((uint32_t)0x00000002) /*!< External Interrupt 3 */ -//#define SYSCFG_ITLINE7_SR_EXTI4 ((uint32_t)0x00000001) /*!< External Interrupt 15 to 4 */ -//#define SYSCFG_ITLINE7_SR_EXTI5 ((uint32_t)0x00000002) /*!< External Interrupt 15 to 4 */ -//#define SYSCFG_ITLINE7_SR_EXTI6 ((uint32_t)0x00000004) /*!< External Interrupt 15 to 4 */ -//#define SYSCFG_ITLINE7_SR_EXTI7 ((uint32_t)0x00000008) /*!< External Interrupt 15 to 4 */ -//#define SYSCFG_ITLINE7_SR_EXTI8 ((uint32_t)0x00000010) /*!< External Interrupt 15 to 4 */ -//#define SYSCFG_ITLINE7_SR_EXTI9 ((uint32_t)0x00000020) /*!< External Interrupt 15 to 4 */ -//#define SYSCFG_ITLINE7_SR_EXTI10 ((uint32_t)0x00000040) /*!< External Interrupt 15 to 4 */ -//#define SYSCFG_ITLINE7_SR_EXTI11 ((uint32_t)0x00000080) /*!< External Interrupt 15 to 4 */ -//#define SYSCFG_ITLINE7_SR_EXTI12 ((uint32_t)0x00000100) /*!< External Interrupt 15 to 4 */ -//#define SYSCFG_ITLINE7_SR_EXTI13 ((uint32_t)0x00000200) /*!< External Interrupt 15 to 4 */ -//#define SYSCFG_ITLINE7_SR_EXTI14 ((uint32_t)0x00000400) /*!< External Interrupt 15 to 4 */ -//#define SYSCFG_ITLINE7_SR_EXTI15 ((uint32_t)0x00000800) /*!< External Interrupt 15 to 4 */ -//#define SYSCFG_ITLINE8_SR_TSC_EOA ((uint32_t)0x00000001) /*!< Touch control EOA Interrupt */ -//#define SYSCFG_ITLINE8_SR_TSC_MCE ((uint32_t)0x00000002) /*!< Touch control MCE Interrupt */ -//#define SYSCFG_ITLINE9_SR_DMA1_CH1 ((uint32_t)0x00000001) /*!< DMA1 Channel 1 Interrupt */ -//#define SYSCFG_ITLINE10_SR_DMA1_CH2 ((uint32_t)0x00000001) /*!< DMA1 Channel 2 Interrupt */ -//#define SYSCFG_ITLINE10_SR_DMA1_CH3 ((uint32_t)0x00000002) /*!< DMA2 Channel 3 Interrupt */ -//#define SYSCFG_ITLINE10_SR_DMA2_CH1 ((uint32_t)0x00000004) /*!< DMA2 Channel 1 Interrupt */ -//#define SYSCFG_ITLINE10_SR_DMA2_CH2 ((uint32_t)0x00000008) /*!< DMA2 Channel 2 Interrupt */ -//#define SYSCFG_ITLINE11_SR_DMA1_CH4 ((uint32_t)0x00000001) /*!< DMA1 Channel 4 Interrupt */ -//#define SYSCFG_ITLINE11_SR_DMA1_CH5 ((uint32_t)0x00000002) /*!< DMA1 Channel 5 Interrupt */ -//#define SYSCFG_ITLINE11_SR_DMA1_CH6 ((uint32_t)0x00000004) /*!< DMA1 Channel 6 Interrupt */ -//#define SYSCFG_ITLINE11_SR_DMA1_CH7 ((uint32_t)0x00000008) /*!< DMA1 Channel 7 Interrupt */ -//#define SYSCFG_ITLINE11_SR_DMA2_CH3 ((uint32_t)0x00000010) /*!< DMA2 Channel 3 Interrupt */ -//#define SYSCFG_ITLINE11_SR_DMA2_CH4 ((uint32_t)0x00000020) /*!< DMA2 Channel 4 Interrupt */ -//#define SYSCFG_ITLINE11_SR_DMA2_CH5 ((uint32_t)0x00000040) /*!< DMA2 Channel 5 Interrupt */ -//#define SYSCFG_ITLINE12_SR_ADC ((uint32_t)0x00000001) /*!< ADC Interrupt */ -//#define SYSCFG_ITLINE12_SR_COMP1 ((uint32_t)0x00000002) /*!< COMP1 Interrupt -> exti[21] */ -//#define SYSCFG_ITLINE12_SR_COMP2 ((uint32_t)0x00000004) /*!< COMP2 Interrupt -> exti[22] */ -//#define SYSCFG_ITLINE13_SR_TIM1_BRK ((uint32_t)0x00000001) /*!< TIM1 BRK Interrupt */ -//#define SYSCFG_ITLINE13_SR_TIM1_UPD ((uint32_t)0x00000002) /*!< TIM1 UPD Interrupt */ -//#define SYSCFG_ITLINE13_SR_TIM1_TRG ((uint32_t)0x00000004) /*!< TIM1 TRG Interrupt */ -//#define SYSCFG_ITLINE13_SR_TIM1_CCU ((uint32_t)0x00000008) /*!< TIM1 CCU Interrupt */ -//#define SYSCFG_ITLINE14_SR_TIM1_CC ((uint32_t)0x00000001) /*!< TIM1 CC Interrupt */ -//#define SYSCFG_ITLINE15_SR_TIM2_GLB ((uint32_t)0x00000001) /*!< TIM2 GLB Interrupt */ -//#define SYSCFG_ITLINE16_SR_TIM3_GLB ((uint32_t)0x00000001) /*!< TIM3 GLB Interrupt */ -//#define SYSCFG_ITLINE17_SR_DAC ((uint32_t)0x00000001) /*!< DAC Interrupt */ -//#define SYSCFG_ITLINE17_SR_TIM6_GLB ((uint32_t)0x00000002) /*!< TIM6 GLB Interrupt */ -//#define SYSCFG_ITLINE18_SR_TIM7_GLB ((uint32_t)0x00000001) /*!< TIM7 GLB Interrupt */ -//#define SYSCFG_ITLINE19_SR_TIM14_GLB ((uint32_t)0x00000001) /*!< TIM14 GLB Interrupt */ -//#define SYSCFG_ITLINE20_SR_TIM15_GLB ((uint32_t)0x00000001) /*!< TIM15 GLB Interrupt */ -//#define SYSCFG_ITLINE21_SR_TIM16_GLB ((uint32_t)0x00000001) /*!< TIM16 GLB Interrupt */ -//#define SYSCFG_ITLINE22_SR_TIM17_GLB ((uint32_t)0x00000001) /*!< TIM17 GLB Interrupt */ -//#define SYSCFG_ITLINE23_SR_I2C1_GLB ((uint32_t)0x00000001) /*!< I2C1 GLB Interrupt -> exti[23] */ -//#define SYSCFG_ITLINE24_SR_I2C2_GLB ((uint32_t)0x00000001) /*!< I2C2 GLB Interrupt */ -//#define SYSCFG_ITLINE25_SR_SPI1 ((uint32_t)0x00000001) /*!< SPI1 Interrupt */ -//#define SYSCFG_ITLINE26_SR_SPI2 ((uint32_t)0x00000001) /*!< SPI2 Interrupt */ -//#define SYSCFG_ITLINE27_SR_USART1_GLB ((uint32_t)0x00000001) /*!< USART1 GLB Interrupt -> exti[25] */ -//#define SYSCFG_ITLINE28_SR_USART2_GLB ((uint32_t)0x00000001) /*!< USART2 GLB Interrupt -> exti[26] */ -//#define SYSCFG_ITLINE29_SR_USART3_GLB ((uint32_t)0x00000001) /*!< USART3 GLB Interrupt -> exti[28] */ -//#define SYSCFG_ITLINE29_SR_USART4_GLB ((uint32_t)0x00000002) /*!< USART4 GLB Interrupt */ -//#define SYSCFG_ITLINE29_SR_USART5_GLB ((uint32_t)0x00000004) /*!< USART5 GLB Interrupt */ -//#define SYSCFG_ITLINE29_SR_USART6_GLB ((uint32_t)0x00000008) /*!< USART6 GLB Interrupt */ -//#define SYSCFG_ITLINE29_SR_USART7_GLB ((uint32_t)0x00000010) /*!< USART7 GLB Interrupt */ -//#define SYSCFG_ITLINE29_SR_USART8_GLB ((uint32_t)0x00000020) /*!< USART8 GLB Interrupt */ -//#define SYSCFG_ITLINE30_SR_CAN ((uint32_t)0x00000001) /*!< CAN Interrupt */ -//#define SYSCFG_ITLINE30_SR_CEC ((uint32_t)0x00000002) /*!< CEC Interrupt */ - -/******************************************************************************/ -/* */ -/* Timers (TIM) */ -/* */ -/******************************************************************************/ -/******************* Bit definition for TIM_CR1 register ********************/ -#define TIM_CR1_CEN ((uint16_t)0x0001) /*! - -/** @addtogroup Exported_types - * @{ - */ -/** @addtogroup Exported_types - * @{ - */ -typedef enum -{ - RESET = 0, - SET = !RESET -} FlagStatus, ITStatus; - -typedef enum -{ - DISABLE = 0, - ENABLE = !DISABLE -} FunctionalState; -#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE)) - -typedef enum -{ - ERROR = 0, - SUCCESS = !ERROR -} ErrorStatus; - - -/** @addtogroup Peripheral_registers_structures - * @{ - */ - -/** - * @brief Analog to Digital Converter - */ - -typedef struct -{ - __IO uint32_t ISR; /*!< ADC Interrupt and Status register, Address offset:0x00 */ - __IO uint32_t IER; /*!< ADC Interrupt Enable register, Address offset:0x04 */ - __IO uint32_t CR; /*!< ADC Control register, Address offset:0x08 */ - __IO uint32_t CFGR1; /*!< ADC Configuration register 1, Address offset:0x0C */ - __IO uint32_t CFGR2; /*!< ADC Configuration register 2, Address offset:0x10 */ - __IO uint32_t SMPR; /*!< ADC Sampling time register, Address offset:0x14 */ - uint32_t RESERVED1; /*!< Reserved, 0x18 */ - uint32_t RESERVED2; /*!< Reserved, 0x1C */ - __IO uint32_t TR; /*!< ADC watchdog threshold register, Address offset:0x20 */ - uint32_t RESERVED3; /*!< Reserved, 0x24 */ - __IO uint32_t CHSELR; /*!< ADC channel selection register, Address offset:0x28 */ - uint32_t RESERVED4[5]; /*!< Reserved, 0x2C */ - __IO uint32_t DR; /*!< ADC data register, Address offset:0x40 */ -} ADC_TypeDef; - -typedef struct -{ - __IO uint32_t CCR; /*Address offset:0x308 */ - __IO uint32_t CR2; /*Address offset:0x30C */ -} ADC_Common_TypeDef; - -/** - * @brief Comparator - */ - -typedef struct -{ - __IO uint32_t RESERVED[7]; /*!< Reserved, Address offset: 0x18-0x00 */ - __IO uint32_t CSR; /*!< COMP comparator control and status register, Address offset: 0x1C */ -} COMP_TypeDef; -/** - * @brief OPA - */ -typedef struct -{ - __IO uint32_t RESERVED[12]; /*!< Reserved, Address offset: 0x2C-0x00 */ - __IO uint32_t CR; /*!< COMP comparator control and status register, Address offset: 0x30 */ -} OPA_TypeDef; - -/** - * @brief DAC Configuration - */ -typedef struct -{ - __IO uint32_t RESERVED[8]; /*!< Reserved, Address offset: 0x1C-0x00 */ - __IO uint32_t CTRL; /*!< DAC configuration register Address offset: 0x20 */ - __IO uint32_t DATA1; /*!< DAC1 Input data Address offset: 0x24 */ - __IO uint32_t DATA2; /*!< DAC2 Input data Address offset: 0x28 */ -}DAC_TypeDef; - -/** - * @brief CRC calculation unit - */ - -typedef struct -{ - __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ - __IO uint32_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ - __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ - uint32_t RESERVED2; /*!< Reserved, 0x0C */ - __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */ - __IO uint32_t RESERVED3; /*!< Reserved, 0x14 */ -} CRC_TypeDef; - -/** - * @brief Clock Recovery System - */ -typedef struct -{ -__IO uint32_t CR; /*!< CRS ccontrol register, Address offset: 0x00 */ -__IO uint32_t CFGR; /*!< CRS configuration register, Address offset: 0x04 */ -__IO uint32_t ISR; /*!< CRS interrupt and status register, Address offset: 0x08 */ -__IO uint32_t ICR; /*!< CRS interrupt flag clear register, Address offset: 0x0C */ -} CRS_TypeDef; - -/** - * @brief Debug MCU - */ - -typedef struct -{ - __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ - __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ - __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */ - __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */ -}DBGMCU_TypeDef; - -/** - * @brief DMA Controller - */ - -typedef struct -{ - __IO uint32_t CCR; /*!< DMA channel x configuration register */ - __IO uint32_t CNDTR; /*!< DMA channel x number of data register */ - __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */ - __IO uint32_t CMAR; /*!< DMA channel x memory address register */ -} DMA_Channel_TypeDef; - -typedef struct -{ - __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */ - __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */ -}DMA_TypeDef; - -/** - * @brief External Interrupt/Event Controller - */ - -typedef struct -{ - __IO uint32_t IMR; /*! exti[31] Interrupt */ -//#define SYSCFG_ITLINE1_SR_VDDIO2 ((uint32_t)0x00000002) /*!< VDDIO2 -> exti[16] Interrupt */ -//#define SYSCFG_ITLINE2_SR_RTC_WAKEUP ((uint32_t)0x00000001) /*!< RTC WAKEUP -> exti[20] Interrupt */ -//#define SYSCFG_ITLINE2_SR_RTC_TSTAMP ((uint32_t)0x00000002) /*!< RTC Time Stamp -> exti[19] interrupt */ -//#define SYSCFG_ITLINE2_SR_RTC_ALRA ((uint32_t)0x00000003) /*!< RTC Alarm -> exti[17] interrupt .... */ -//#define SYSCFG_ITLINE3_SR_FLASH_ITF ((uint32_t)0x00000001) /*!< Flash ITF Interrupt */ -//#define SYSCFG_ITLINE4_SR_CRS ((uint32_t)0x00000001) /*!< CRS interrupt */ -//#define SYSCFG_ITLINE4_SR_CLK_CTRL ((uint32_t)0x00000002) /*!< CLK CTRL interrupt */ -//#define SYSCFG_ITLINE5_SR_EXTI0 ((uint32_t)0x00000001) /*!< External Interrupt 0 */ -//#define SYSCFG_ITLINE5_SR_EXTI1 ((uint32_t)0x00000002) /*!< External Interrupt 1 */ -//#define SYSCFG_ITLINE6_SR_EXTI2 ((uint32_t)0x00000001) /*!< External Interrupt 2 */ -//#define SYSCFG_ITLINE6_SR_EXTI3 ((uint32_t)0x00000002) /*!< External Interrupt 3 */ -//#define SYSCFG_ITLINE7_SR_EXTI4 ((uint32_t)0x00000001) /*!< External Interrupt 15 to 4 */ -//#define SYSCFG_ITLINE7_SR_EXTI5 ((uint32_t)0x00000002) /*!< External Interrupt 15 to 4 */ -//#define SYSCFG_ITLINE7_SR_EXTI6 ((uint32_t)0x00000004) /*!< External Interrupt 15 to 4 */ -//#define SYSCFG_ITLINE7_SR_EXTI7 ((uint32_t)0x00000008) /*!< External Interrupt 15 to 4 */ -//#define SYSCFG_ITLINE7_SR_EXTI8 ((uint32_t)0x00000010) /*!< External Interrupt 15 to 4 */ -//#define SYSCFG_ITLINE7_SR_EXTI9 ((uint32_t)0x00000020) /*!< External Interrupt 15 to 4 */ -//#define SYSCFG_ITLINE7_SR_EXTI10 ((uint32_t)0x00000040) /*!< External Interrupt 15 to 4 */ -//#define SYSCFG_ITLINE7_SR_EXTI11 ((uint32_t)0x00000080) /*!< External Interrupt 15 to 4 */ -//#define SYSCFG_ITLINE7_SR_EXTI12 ((uint32_t)0x00000100) /*!< External Interrupt 15 to 4 */ -//#define SYSCFG_ITLINE7_SR_EXTI13 ((uint32_t)0x00000200) /*!< External Interrupt 15 to 4 */ -//#define SYSCFG_ITLINE7_SR_EXTI14 ((uint32_t)0x00000400) /*!< External Interrupt 15 to 4 */ -//#define SYSCFG_ITLINE7_SR_EXTI15 ((uint32_t)0x00000800) /*!< External Interrupt 15 to 4 */ -//#define SYSCFG_ITLINE8_SR_TSC_EOA ((uint32_t)0x00000001) /*!< Touch control EOA Interrupt */ -//#define SYSCFG_ITLINE8_SR_TSC_MCE ((uint32_t)0x00000002) /*!< Touch control MCE Interrupt */ -//#define SYSCFG_ITLINE9_SR_DMA1_CH1 ((uint32_t)0x00000001) /*!< DMA1 Channel 1 Interrupt */ -//#define SYSCFG_ITLINE10_SR_DMA1_CH2 ((uint32_t)0x00000001) /*!< DMA1 Channel 2 Interrupt */ -//#define SYSCFG_ITLINE10_SR_DMA1_CH3 ((uint32_t)0x00000002) /*!< DMA2 Channel 3 Interrupt */ -//#define SYSCFG_ITLINE10_SR_DMA2_CH1 ((uint32_t)0x00000004) /*!< DMA2 Channel 1 Interrupt */ -//#define SYSCFG_ITLINE10_SR_DMA2_CH2 ((uint32_t)0x00000008) /*!< DMA2 Channel 2 Interrupt */ -//#define SYSCFG_ITLINE11_SR_DMA1_CH4 ((uint32_t)0x00000001) /*!< DMA1 Channel 4 Interrupt */ -//#define SYSCFG_ITLINE11_SR_DMA1_CH5 ((uint32_t)0x00000002) /*!< DMA1 Channel 5 Interrupt */ -//#define SYSCFG_ITLINE11_SR_DMA1_CH6 ((uint32_t)0x00000004) /*!< DMA1 Channel 6 Interrupt */ -//#define SYSCFG_ITLINE11_SR_DMA1_CH7 ((uint32_t)0x00000008) /*!< DMA1 Channel 7 Interrupt */ -//#define SYSCFG_ITLINE11_SR_DMA2_CH3 ((uint32_t)0x00000010) /*!< DMA2 Channel 3 Interrupt */ -//#define SYSCFG_ITLINE11_SR_DMA2_CH4 ((uint32_t)0x00000020) /*!< DMA2 Channel 4 Interrupt */ -//#define SYSCFG_ITLINE11_SR_DMA2_CH5 ((uint32_t)0x00000040) /*!< DMA2 Channel 5 Interrupt */ -//#define SYSCFG_ITLINE12_SR_ADC ((uint32_t)0x00000001) /*!< ADC Interrupt */ -//#define SYSCFG_ITLINE12_SR_COMP1 ((uint32_t)0x00000002) /*!< COMP1 Interrupt -> exti[21] */ -//#define SYSCFG_ITLINE12_SR_COMP2 ((uint32_t)0x00000004) /*!< COMP2 Interrupt -> exti[22] */ -//#define SYSCFG_ITLINE13_SR_TIM1_BRK ((uint32_t)0x00000001) /*!< TIM1 BRK Interrupt */ -//#define SYSCFG_ITLINE13_SR_TIM1_UPD ((uint32_t)0x00000002) /*!< TIM1 UPD Interrupt */ -//#define SYSCFG_ITLINE13_SR_TIM1_TRG ((uint32_t)0x00000004) /*!< TIM1 TRG Interrupt */ -//#define SYSCFG_ITLINE13_SR_TIM1_CCU ((uint32_t)0x00000008) /*!< TIM1 CCU Interrupt */ -//#define SYSCFG_ITLINE14_SR_TIM1_CC ((uint32_t)0x00000001) /*!< TIM1 CC Interrupt */ -//#define SYSCFG_ITLINE15_SR_TIM2_GLB ((uint32_t)0x00000001) /*!< TIM2 GLB Interrupt */ -//#define SYSCFG_ITLINE16_SR_TIM3_GLB ((uint32_t)0x00000001) /*!< TIM3 GLB Interrupt */ -//#define SYSCFG_ITLINE17_SR_DAC ((uint32_t)0x00000001) /*!< DAC Interrupt */ -//#define SYSCFG_ITLINE17_SR_TIM6_GLB ((uint32_t)0x00000002) /*!< TIM6 GLB Interrupt */ -//#define SYSCFG_ITLINE18_SR_TIM7_GLB ((uint32_t)0x00000001) /*!< TIM7 GLB Interrupt */ -//#define SYSCFG_ITLINE19_SR_TIM14_GLB ((uint32_t)0x00000001) /*!< TIM14 GLB Interrupt */ -//#define SYSCFG_ITLINE20_SR_TIM15_GLB ((uint32_t)0x00000001) /*!< TIM15 GLB Interrupt */ -//#define SYSCFG_ITLINE21_SR_TIM16_GLB ((uint32_t)0x00000001) /*!< TIM16 GLB Interrupt */ -//#define SYSCFG_ITLINE22_SR_TIM17_GLB ((uint32_t)0x00000001) /*!< TIM17 GLB Interrupt */ -//#define SYSCFG_ITLINE23_SR_I2C1_GLB ((uint32_t)0x00000001) /*!< I2C1 GLB Interrupt -> exti[23] */ -//#define SYSCFG_ITLINE24_SR_I2C2_GLB ((uint32_t)0x00000001) /*!< I2C2 GLB Interrupt */ -//#define SYSCFG_ITLINE25_SR_SPI1 ((uint32_t)0x00000001) /*!< SPI1 Interrupt */ -//#define SYSCFG_ITLINE26_SR_SPI2 ((uint32_t)0x00000001) /*!< SPI2 Interrupt */ -//#define SYSCFG_ITLINE27_SR_USART1_GLB ((uint32_t)0x00000001) /*!< USART1 GLB Interrupt -> exti[25] */ -//#define SYSCFG_ITLINE28_SR_USART2_GLB ((uint32_t)0x00000001) /*!< USART2 GLB Interrupt -> exti[26] */ -//#define SYSCFG_ITLINE29_SR_USART3_GLB ((uint32_t)0x00000001) /*!< USART3 GLB Interrupt -> exti[28] */ -//#define SYSCFG_ITLINE29_SR_USART4_GLB ((uint32_t)0x00000002) /*!< USART4 GLB Interrupt */ -//#define SYSCFG_ITLINE29_SR_USART5_GLB ((uint32_t)0x00000004) /*!< USART5 GLB Interrupt */ -//#define SYSCFG_ITLINE29_SR_USART6_GLB ((uint32_t)0x00000008) /*!< USART6 GLB Interrupt */ -//#define SYSCFG_ITLINE29_SR_USART7_GLB ((uint32_t)0x00000010) /*!< USART7 GLB Interrupt */ -//#define SYSCFG_ITLINE29_SR_USART8_GLB ((uint32_t)0x00000020) /*!< USART8 GLB Interrupt */ -//#define SYSCFG_ITLINE30_SR_CAN ((uint32_t)0x00000001) /*!< CAN Interrupt */ -//#define SYSCFG_ITLINE30_SR_CEC ((uint32_t)0x00000002) /*!< CEC Interrupt */ - -/******************************************************************************/ -/* */ -/* Timers (TIM) */ -/* */ -/******************************************************************************/ -/******************* Bit definition for TIM_CR1 register ********************/ -#define TIM_CR1_CEN ((uint16_t)0x0001) /*! - -/** @addtogroup Exported_types - * @{ - */ -/** @addtogroup Exported_types - * @{ - */ -typedef enum -{ - RESET = 0, - SET = !RESET -} FlagStatus, ITStatus; - -typedef enum -{ - DISABLE = 0, - ENABLE = !DISABLE -} FunctionalState; -#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE)) - -typedef enum -{ - ERROR = 0, - SUCCESS = !ERROR -} ErrorStatus; - - -/** @addtogroup Peripheral_registers_structures - * @{ - */ - -/** - * @brief Analog to Digital Converter - */ - -typedef struct -{ - __IO uint32_t ISR; /*!< ADC Interrupt and Status register, Address offset:0x00 */ - __IO uint32_t IER; /*!< ADC Interrupt Enable register, Address offset:0x04 */ - __IO uint32_t CR; /*!< ADC Control register, Address offset:0x08 */ - __IO uint32_t CFGR1; /*!< ADC Configuration register 1, Address offset:0x0C */ - __IO uint32_t CFGR2; /*!< ADC Configuration register 2, Address offset:0x10 */ - __IO uint32_t SMPR; /*!< ADC Sampling time register, Address offset:0x14 */ - uint32_t RESERVED1; /*!< Reserved, 0x18 */ - uint32_t RESERVED2; /*!< Reserved, 0x1C */ - __IO uint32_t TR; /*!< ADC watchdog threshold register, Address offset:0x20 */ - uint32_t RESERVED3; /*!< Reserved, 0x24 */ - __IO uint32_t CHSELR; /*!< ADC channel selection register, Address offset:0x28 */ - uint32_t RESERVED4; /*!< Reserved, 0x2C */ - __IO uint32_t ETCR; /*!< External trigger Control register, Address offset:0x30 */ - __IO uint32_t RTENR; /*!< ADC rising edge trigger enable register, Address offset:0x34 */ - __IO uint32_t FTENR; /*!< ADC falling edge trigger enable register, Address offset:0x38 */ - uint32_t RESERVED5 ; /*!< Reserved, 0x3C */ - __IO uint32_t DR; /*!< ADC data register, Address offset:0x40 */ -} ADC_TypeDef; - -typedef struct -{ - __IO uint32_t CCR; /*Address offset:0x308 */ - __IO uint32_t CR2; /*Address offset:0x30C */ - __IO uint32_t ADC_IOSH1DR; /*Address offset:0x310 */ - __IO uint32_t ADC_IOSH2DR; /*Address offset:0x314 */ -} ADC_Common_TypeDef; - -/** - * @brief Comparator - */ - -typedef struct -{ - __IO uint32_t RESERVED1[7]; /*!< Reserved, Address offset: 0x18-0x00 */ - __IO uint32_t CSR; /*!< COMP comparator control and status register, Address offset: 0x1C */ - __IO uint32_t RESERVED2[3]; /*!< Reserved, Address offset: 0x20-0x28 */ - __IO uint32_t CSR2; /*!< COMP comparator control and status register 2, Address offset: 0x2C */ -} COMP_TypeDef; -/** - * @brief OPA - */ -typedef struct -{ - __IO uint32_t RESERVED1[12]; /*!< Reserved, Address offset: 0x2C-0x00 */ - __IO uint32_t CR; /*!< COMP comparator control and status register, Address offset: 0x30 */ -} OPA_TypeDef; -/** - * @brief ONEW - */ -typedef struct -{ - __IO uint32_t RESERVED1[13]; /*!< Reserved, Address offset: 0x30-0x00 */ - __IO uint32_t CFG; /*!< COMP comparator control and status register, Address offset: 0x34 */ - __IO uint32_t BUF; /*!< COMP comparator control and status register, Address offset: 0x38 */ -} ONEW_TypeDef; -/** - * @brief DAC Configuration - */ -typedef struct -{ - __IO uint32_t RESERVED[8]; /*!< Reserved, Address offset: 0x1C-0x00 */ - __IO uint32_t CTRL; /*!< DAC configuration register Address offset: 0x20 */ - __IO uint32_t DATA1; /*!< DAC1 Input data Address offset: 0x24 */ - __IO uint32_t DATA2; /*!< DAC2 Input data Address offset: 0x28 */ -}DAC_TypeDef; -/** - * @brief DIV Configuration - */ -typedef struct -{ - __IO uint32_t RESERVED[32]; /*!< Reserved, Address offset: 0x7C-0x00 */ - __IO uint32_t DID; /*!< DID register Address offset: 0x80 */ - __IO uint32_t DIS; /*!< DIS register Address offset: 0x84 */ - __IO uint32_t QUO; /*!< QUO register Address offset: 0x88 */ - __IO uint32_t REM; /*!< REM register Address offset: 0x8C */ - __IO uint32_t SC; /*!< SC register Address offset: 0x90 */ -}DIV_TypeDef; -/** - * @brief LEB Configuration - */ -typedef struct -{ - __IO uint32_t LEBCR; /*!< LEBCR register Address offset: 0x80 */ - __IO uint32_t FLTCFG1; /*!< FLTCFG1 register Address offset: 0x84 */ - __IO uint32_t FLTCFG2; /*!< FLTCFG2 register Address offset: 0x88 */ - __IO uint32_t LEBCFG; /*!< LEBCFG register Address offset: 0x8C */ - __IO uint32_t LEB1CFG; /*!< LEB1CFG register Address offset: 0x90 */ - __IO uint32_t LEB2CFG; /*!< LEB2CFG register Address offset: 0x90 */ - __IO uint32_t LEB3CFG; /*!< LEB3CFG register Address offset: 0x90 */ - __IO uint32_t LEB1PR; /*!< LEB1PR register Address offset: 0x90 */ - __IO uint32_t LEB2PR; /*!< LEB2PR register Address offset: 0x90 */ - __IO uint32_t LEB3PR; /*!< LEB3PR register Address offset: 0x90 */ -}LEB_TypeDef; -/** - * @brief CRC calculation unit - */ - -typedef struct -{ - __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ - __IO uint32_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ - __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ - uint32_t RESERVED2; /*!< Reserved, 0x0C */ - __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */ - __IO uint32_t RESERVED3; /*!< Reserved, 0x14 */ -} CRC_TypeDef; - -/** - * @brief Clock Recovery System - */ -typedef struct -{ -__IO uint32_t CR; /*!< CRS ccontrol register, Address offset: 0x00 */ -__IO uint32_t CFGR; /*!< CRS configuration register, Address offset: 0x04 */ -__IO uint32_t ISR; /*!< CRS interrupt and status register, Address offset: 0x08 */ -__IO uint32_t ICR; /*!< CRS interrupt flag clear register, Address offset: 0x0C */ -} CRS_TypeDef; - -/** - * @brief Debug MCU - */ - -typedef struct -{ - __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ - __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ - __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */ - __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */ -}DBGMCU_TypeDef; - -/** - * @brief DMA Controller - */ - -typedef struct -{ - __IO uint32_t CCR; /*!< DMA channel x configuration register */ - __IO uint32_t CNDTR; /*!< DMA channel x number of data register */ - __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */ - __IO uint32_t CMAR; /*!< DMA channel x memory address register */ -} DMA_Channel_TypeDef; - -typedef struct -{ - __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */ - __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */ -}DMA_TypeDef; - -/** - * @brief External Interrupt/Event Controller - */ - -typedef struct -{ - __IO uint32_t IMR; /*! exti[31] Interrupt */ -//#define SYSCFG_ITLINE1_SR_VDDIO2 ((uint32_t)0x00000002) /*!< VDDIO2 -> exti[16] Interrupt */ -//#define SYSCFG_ITLINE2_SR_RTC_WAKEUP ((uint32_t)0x00000001) /*!< RTC WAKEUP -> exti[20] Interrupt */ -//#define SYSCFG_ITLINE2_SR_RTC_TSTAMP ((uint32_t)0x00000002) /*!< RTC Time Stamp -> exti[19] interrupt */ -//#define SYSCFG_ITLINE2_SR_RTC_ALRA ((uint32_t)0x00000003) /*!< RTC Alarm -> exti[17] interrupt .... */ -//#define SYSCFG_ITLINE3_SR_FLASH_ITF ((uint32_t)0x00000001) /*!< Flash ITF Interrupt */ -//#define SYSCFG_ITLINE4_SR_CRS ((uint32_t)0x00000001) /*!< CRS interrupt */ -//#define SYSCFG_ITLINE4_SR_CLK_CTRL ((uint32_t)0x00000002) /*!< CLK CTRL interrupt */ -//#define SYSCFG_ITLINE5_SR_EXTI0 ((uint32_t)0x00000001) /*!< External Interrupt 0 */ -//#define SYSCFG_ITLINE5_SR_EXTI1 ((uint32_t)0x00000002) /*!< External Interrupt 1 */ -//#define SYSCFG_ITLINE6_SR_EXTI2 ((uint32_t)0x00000001) /*!< External Interrupt 2 */ -//#define SYSCFG_ITLINE6_SR_EXTI3 ((uint32_t)0x00000002) /*!< External Interrupt 3 */ -//#define SYSCFG_ITLINE7_SR_EXTI4 ((uint32_t)0x00000001) /*!< External Interrupt 15 to 4 */ -//#define SYSCFG_ITLINE7_SR_EXTI5 ((uint32_t)0x00000002) /*!< External Interrupt 15 to 4 */ -//#define SYSCFG_ITLINE7_SR_EXTI6 ((uint32_t)0x00000004) /*!< External Interrupt 15 to 4 */ -//#define SYSCFG_ITLINE7_SR_EXTI7 ((uint32_t)0x00000008) /*!< External Interrupt 15 to 4 */ -//#define SYSCFG_ITLINE7_SR_EXTI8 ((uint32_t)0x00000010) /*!< External Interrupt 15 to 4 */ -//#define SYSCFG_ITLINE7_SR_EXTI9 ((uint32_t)0x00000020) /*!< External Interrupt 15 to 4 */ -//#define SYSCFG_ITLINE7_SR_EXTI10 ((uint32_t)0x00000040) /*!< External Interrupt 15 to 4 */ -//#define SYSCFG_ITLINE7_SR_EXTI11 ((uint32_t)0x00000080) /*!< External Interrupt 15 to 4 */ -//#define SYSCFG_ITLINE7_SR_EXTI12 ((uint32_t)0x00000100) /*!< External Interrupt 15 to 4 */ -//#define SYSCFG_ITLINE7_SR_EXTI13 ((uint32_t)0x00000200) /*!< External Interrupt 15 to 4 */ -//#define SYSCFG_ITLINE7_SR_EXTI14 ((uint32_t)0x00000400) /*!< External Interrupt 15 to 4 */ -//#define SYSCFG_ITLINE7_SR_EXTI15 ((uint32_t)0x00000800) /*!< External Interrupt 15 to 4 */ -//#define SYSCFG_ITLINE8_SR_TSC_EOA ((uint32_t)0x00000001) /*!< Touch control EOA Interrupt */ -//#define SYSCFG_ITLINE8_SR_TSC_MCE ((uint32_t)0x00000002) /*!< Touch control MCE Interrupt */ -//#define SYSCFG_ITLINE9_SR_DMA1_CH1 ((uint32_t)0x00000001) /*!< DMA1 Channel 1 Interrupt */ -//#define SYSCFG_ITLINE10_SR_DMA1_CH2 ((uint32_t)0x00000001) /*!< DMA1 Channel 2 Interrupt */ -//#define SYSCFG_ITLINE10_SR_DMA1_CH3 ((uint32_t)0x00000002) /*!< DMA2 Channel 3 Interrupt */ -//#define SYSCFG_ITLINE10_SR_DMA2_CH1 ((uint32_t)0x00000004) /*!< DMA2 Channel 1 Interrupt */ -//#define SYSCFG_ITLINE10_SR_DMA2_CH2 ((uint32_t)0x00000008) /*!< DMA2 Channel 2 Interrupt */ -//#define SYSCFG_ITLINE11_SR_DMA1_CH4 ((uint32_t)0x00000001) /*!< DMA1 Channel 4 Interrupt */ -//#define SYSCFG_ITLINE11_SR_DMA1_CH5 ((uint32_t)0x00000002) /*!< DMA1 Channel 5 Interrupt */ -//#define SYSCFG_ITLINE11_SR_DMA1_CH6 ((uint32_t)0x00000004) /*!< DMA1 Channel 6 Interrupt */ -//#define SYSCFG_ITLINE11_SR_DMA1_CH7 ((uint32_t)0x00000008) /*!< DMA1 Channel 7 Interrupt */ -//#define SYSCFG_ITLINE11_SR_DMA2_CH3 ((uint32_t)0x00000010) /*!< DMA2 Channel 3 Interrupt */ -//#define SYSCFG_ITLINE11_SR_DMA2_CH4 ((uint32_t)0x00000020) /*!< DMA2 Channel 4 Interrupt */ -//#define SYSCFG_ITLINE11_SR_DMA2_CH5 ((uint32_t)0x00000040) /*!< DMA2 Channel 5 Interrupt */ -//#define SYSCFG_ITLINE12_SR_ADC ((uint32_t)0x00000001) /*!< ADC Interrupt */ -//#define SYSCFG_ITLINE12_SR_COMP1 ((uint32_t)0x00000002) /*!< COMP1 Interrupt -> exti[21] */ -//#define SYSCFG_ITLINE12_SR_COMP2 ((uint32_t)0x00000004) /*!< COMP2 Interrupt -> exti[22] */ -//#define SYSCFG_ITLINE13_SR_TIM1_BRK ((uint32_t)0x00000001) /*!< TIM1 BRK Interrupt */ -//#define SYSCFG_ITLINE13_SR_TIM1_UPD ((uint32_t)0x00000002) /*!< TIM1 UPD Interrupt */ -//#define SYSCFG_ITLINE13_SR_TIM1_TRG ((uint32_t)0x00000004) /*!< TIM1 TRG Interrupt */ -//#define SYSCFG_ITLINE13_SR_TIM1_CCU ((uint32_t)0x00000008) /*!< TIM1 CCU Interrupt */ -//#define SYSCFG_ITLINE14_SR_TIM1_CC ((uint32_t)0x00000001) /*!< TIM1 CC Interrupt */ -//#define SYSCFG_ITLINE15_SR_TIM2_GLB ((uint32_t)0x00000001) /*!< TIM2 GLB Interrupt */ -//#define SYSCFG_ITLINE16_SR_TIM3_GLB ((uint32_t)0x00000001) /*!< TIM3 GLB Interrupt */ -//#define SYSCFG_ITLINE17_SR_DAC ((uint32_t)0x00000001) /*!< DAC Interrupt */ -//#define SYSCFG_ITLINE17_SR_TIM6_GLB ((uint32_t)0x00000002) /*!< TIM6 GLB Interrupt */ -//#define SYSCFG_ITLINE18_SR_TIM7_GLB ((uint32_t)0x00000001) /*!< TIM7 GLB Interrupt */ -//#define SYSCFG_ITLINE19_SR_TIM14_GLB ((uint32_t)0x00000001) /*!< TIM14 GLB Interrupt */ -//#define SYSCFG_ITLINE20_SR_TIM15_GLB ((uint32_t)0x00000001) /*!< TIM15 GLB Interrupt */ -//#define SYSCFG_ITLINE21_SR_TIM16_GLB ((uint32_t)0x00000001) /*!< TIM16 GLB Interrupt */ -//#define SYSCFG_ITLINE22_SR_TIM17_GLB ((uint32_t)0x00000001) /*!< TIM17 GLB Interrupt */ -//#define SYSCFG_ITLINE23_SR_I2C1_GLB ((uint32_t)0x00000001) /*!< I2C1 GLB Interrupt -> exti[23] */ -//#define SYSCFG_ITLINE24_SR_I2C2_GLB ((uint32_t)0x00000001) /*!< I2C2 GLB Interrupt */ -//#define SYSCFG_ITLINE25_SR_SPI1 ((uint32_t)0x00000001) /*!< SPI1 Interrupt */ -//#define SYSCFG_ITLINE26_SR_SPI2 ((uint32_t)0x00000001) /*!< SPI2 Interrupt */ -//#define SYSCFG_ITLINE27_SR_USART1_GLB ((uint32_t)0x00000001) /*!< USART1 GLB Interrupt -> exti[25] */ -//#define SYSCFG_ITLINE28_SR_USART2_GLB ((uint32_t)0x00000001) /*!< USART2 GLB Interrupt -> exti[26] */ -//#define SYSCFG_ITLINE29_SR_USART3_GLB ((uint32_t)0x00000001) /*!< USART3 GLB Interrupt -> exti[28] */ -//#define SYSCFG_ITLINE29_SR_USART4_GLB ((uint32_t)0x00000002) /*!< USART4 GLB Interrupt */ -//#define SYSCFG_ITLINE29_SR_USART5_GLB ((uint32_t)0x00000004) /*!< USART5 GLB Interrupt */ -//#define SYSCFG_ITLINE29_SR_USART6_GLB ((uint32_t)0x00000008) /*!< USART6 GLB Interrupt */ -//#define SYSCFG_ITLINE29_SR_USART7_GLB ((uint32_t)0x00000010) /*!< USART7 GLB Interrupt */ -//#define SYSCFG_ITLINE29_SR_USART8_GLB ((uint32_t)0x00000020) /*!< USART8 GLB Interrupt */ -//#define SYSCFG_ITLINE30_SR_CAN ((uint32_t)0x00000001) /*!< CAN Interrupt */ -//#define SYSCFG_ITLINE30_SR_CEC ((uint32_t)0x00000002) /*!< CEC Interrupt */ - -/******************************************************************************/ -/* */ -/* Timers (TIM) */ -/* */ -/******************************************************************************/ -/******************* Bit definition for TIM_CR1 register ********************/ -#define TIM_CR1_CEN ((uint16_t)0x0001) /*! Heap Configuration -; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - -Heap_Size EQU 0x00000200 - - AREA HEAP, NOINIT, READWRITE, ALIGN=3 -__heap_base -Heap_Mem SPACE Heap_Size -__heap_limit - - PRESERVE8 - THUMB - - -; Vector Table Mapped to Address 0 at Reset - AREA RESET, DATA, READONLY - EXPORT __Vectors - EXPORT __Vectors_End - EXPORT __Vectors_Size - -__Vectors DCD __initial_sp ; Top of Stack - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - - ; External Interrupts - DCD WWDG_IRQHandler ; Window Watchdog - DCD PVD_VDDIO_IRQHandler ; PVD_VDDIO - DCD RTC_IRQHandler ; RTC through EXTI Line - DCD FLASH_IRQHandler ; FLASH - DCD RCC_IRQHandler ; RCC - DCD EXTI0_1_IRQHandler ; EXTI Line 0 and 1 - DCD EXTI2_3_IRQHandler ; EXTI Line 2 and 3 - DCD EXTI4_15_IRQHandler ; EXTI Line 4 to 15 - DCD 0 ; Reserved - DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 - DCD DMA1_Channel2_3_IRQHandler ; DMA1 Channel 2 and Channel 3 - DCD DMA1_Channel4_5_IRQHandler ; DMA1 Channel 4 and Channel 5 - DCD ADC1_IRQHandler ; ADC1 - DCD TIM1_BRK_UP_TRG_COM_IRQHandler ; TIM1 Break, Update, Trigger and Commutation - DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare - DCD 0 ; Reserved - DCD TIM3_IRQHandler ; TIM3 - DCD TIM6_IRQHandler ; TIM6 - DCD 0 ; Reserved - DCD TIM14_IRQHandler ; TIM14 - DCD TIM15_IRQHandler ; TIM15 - DCD TIM16_IRQHandler ; TIM16 - DCD TIM17_IRQHandler ; TIM17 - DCD I2C1_IRQHandler ; I2C1 - DCD I2C2_IRQHandler ; I2C2 - DCD SPI1_IRQHandler ; SPI1 - DCD SPI2_IRQHandler ; SPI2 - DCD USART1_IRQHandler ; USART1 - DCD USART2_IRQHandler ; USART2 - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD USB_IRQHandler ; USB - -__Vectors_End - -__Vectors_Size EQU __Vectors_End - __Vectors - - AREA |.text|, CODE, READONLY - -; Reset handler routine -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT __main - IMPORT SystemInit - - - - LDR R0, =__initial_sp ; set stack pointer - MSR MSP, R0 - -;;Check if boot space corresponds to test memory - - LDR R0,=0x00000004 - LDR R1, [R0] - LSRS R1, R1, #24 - LDR R2,=0x1F - CMP R1, R2 - - BNE ApplicationStart - -;; SYSCFG clock enable - - LDR R0,=0x40021018 - LDR R1,=0x00000001 - STR R1, [R0] - -;; Set CFGR1 register with flash memory remap at address 0 - - LDR R0,=0x40010000 - LDR R1,=0x00000000 - STR R1, [R0] -ApplicationStart - LDR R0, =SystemInit - BLX R0 - LDR R0, =__main - BX R0 - ENDP - -; Dummy Exception Handlers (infinite loops which can be modified) - -NMI_Handler PROC - EXPORT NMI_Handler [WEAK] - B . - ENDP -HardFault_Handler\ - PROC - EXPORT HardFault_Handler [WEAK] - B . - ENDP -SVC_Handler PROC - EXPORT SVC_Handler [WEAK] - B . - ENDP -PendSV_Handler PROC - EXPORT PendSV_Handler [WEAK] - B . - ENDP -SysTick_Handler PROC - EXPORT SysTick_Handler [WEAK] - B . - ENDP - -Default_Handler PROC - - EXPORT WWDG_IRQHandler [WEAK] - EXPORT PVD_VDDIO_IRQHandler [WEAK] - EXPORT RTC_IRQHandler [WEAK] - EXPORT FLASH_IRQHandler [WEAK] - EXPORT RCC_IRQHandler [WEAK] - EXPORT EXTI0_1_IRQHandler [WEAK] - EXPORT EXTI2_3_IRQHandler [WEAK] - EXPORT EXTI4_15_IRQHandler [WEAK] - EXPORT DMA1_Channel1_IRQHandler [WEAK] - EXPORT DMA1_Channel2_3_IRQHandler [WEAK] - EXPORT DMA1_Channel4_5_IRQHandler [WEAK] - EXPORT ADC1_IRQHandler [WEAK] - EXPORT TIM1_BRK_UP_TRG_COM_IRQHandler [WEAK] - EXPORT TIM1_CC_IRQHandler [WEAK] - EXPORT TIM3_IRQHandler [WEAK] - EXPORT TIM6_IRQHandler [WEAK] - EXPORT TIM14_IRQHandler [WEAK] - EXPORT TIM15_IRQHandler [WEAK] - EXPORT TIM16_IRQHandler [WEAK] - EXPORT TIM17_IRQHandler [WEAK] - EXPORT I2C1_IRQHandler [WEAK] - EXPORT I2C2_IRQHandler [WEAK] - EXPORT SPI1_IRQHandler [WEAK] - EXPORT SPI2_IRQHandler [WEAK] - EXPORT USART1_IRQHandler [WEAK] - EXPORT USART2_IRQHandler [WEAK] - EXPORT USB_IRQHandler [WEAK] - - -WWDG_IRQHandler -PVD_VDDIO_IRQHandler -RTC_IRQHandler -FLASH_IRQHandler -RCC_IRQHandler -EXTI0_1_IRQHandler -EXTI2_3_IRQHandler -EXTI4_15_IRQHandler -DMA1_Channel1_IRQHandler -DMA1_Channel2_3_IRQHandler -DMA1_Channel4_5_IRQHandler -ADC1_IRQHandler -TIM1_BRK_UP_TRG_COM_IRQHandler -TIM1_CC_IRQHandler -TIM3_IRQHandler -TIM6_IRQHandler -TIM14_IRQHandler -TIM15_IRQHandler -TIM16_IRQHandler -TIM17_IRQHandler -I2C1_IRQHandler -I2C2_IRQHandler -SPI1_IRQHandler -SPI2_IRQHandler -USART1_IRQHandler -USART2_IRQHandler -USB_IRQHandler - - B . - - ENDP - - ALIGN - -;******************************************************************************* -; User Stack and Heap initialization -;******************************************************************************* - IF :DEF:__MICROLIB - - EXPORT __initial_sp - EXPORT __heap_base - EXPORT __heap_limit - - ELSE - - IMPORT __use_two_region_memory - EXPORT __user_initial_stackheap - -__user_initial_stackheap - - LDR R0, = Heap_Mem - LDR R1, =(Stack_Mem + Stack_Size) - LDR R2, = (Heap_Mem + Heap_Size) - LDR R3, = Stack_Mem - BX LR - - ALIGN - - ENDIF - - END - -;************************ (C) COPYRIGHT FMD *****END OF FILE***** diff --git a/bsp/ft32/libraries/FT32F0xx/CMSIS/FT32F0xx/source/arm/startup_ft32f030x8.s b/bsp/ft32/libraries/FT32F0xx/CMSIS/FT32F0xx/source/arm/startup_ft32f030x8.s deleted file mode 100644 index 83d871bc5b6..00000000000 --- a/bsp/ft32/libraries/FT32F0xx/CMSIS/FT32F0xx/source/arm/startup_ft32f030x8.s +++ /dev/null @@ -1,252 +0,0 @@ -;/** -; ****************************************************************************** -; * @file startup_ft32f030x8.s -; * @author FMD AE -; * @brief FT32F030X8 devices vector table for MDK-ARM toolchain. -; * @version V1.0.0 -; * @data 2021-07-01 -; ****************************************************************************** -; */ - -Stack_Size EQU 0x00000400 - - AREA STACK, NOINIT, READWRITE, ALIGN=3 -Stack_Mem SPACE Stack_Size -__initial_sp - - -; Heap Configuration -; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - -Heap_Size EQU 0x00000200 - - AREA HEAP, NOINIT, READWRITE, ALIGN=3 -__heap_base -Heap_Mem SPACE Heap_Size -__heap_limit - - PRESERVE8 - THUMB - - -; Vector Table Mapped to Address 0 at Reset - AREA RESET, DATA, READONLY - EXPORT __Vectors - EXPORT __Vectors_End - EXPORT __Vectors_Size - -__Vectors DCD __initial_sp ; Top of Stack - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - - ; External Interrupts - DCD WWDG_IRQHandler ; Window Watchdog - DCD PVD_VDDIO_IRQHandler ; PVD_VDDIO - DCD RTC_IRQHandler ; RTC through EXTI Line - DCD FLASH_IRQHandler ; FLASH - DCD RCC_IRQHandler ; RCC - DCD EXTI0_1_IRQHandler ; EXTI Line 0 and 1 - DCD EXTI2_3_IRQHandler ; EXTI Line 2 and 3 - DCD EXTI4_15_IRQHandler ; EXTI Line 4 to 15 - DCD 0 ; Reserved - DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 - DCD DMA1_Channel2_3_IRQHandler ; DMA1 Channel 2 and Channel 3 - DCD DMA1_Channel4_5_IRQHandler ; DMA1 Channel 4 and Channel 5 - DCD ADC1_IRQHandler ; ADC1 - DCD TIM1_BRK_UP_TRG_COM_IRQHandler ; TIM1 Break, Update, Trigger and Commutation - DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare - DCD 0 ; Reserved - DCD TIM3_IRQHandler ; TIM3 - DCD TIM6_IRQHandler ; TIM6 - DCD 0 ; Reserved - DCD TIM14_IRQHandler ; TIM14 - DCD TIM15_IRQHandler ; TIM15 - DCD TIM16_IRQHandler ; TIM16 - DCD TIM17_IRQHandler ; TIM17 - DCD I2C1_IRQHandler ; I2C1 - DCD I2C2_IRQHandler ; I2C2 - DCD SPI1_IRQHandler ; SPI1 - DCD SPI2_IRQHandler ; SPI2 - DCD USART1_IRQHandler ; USART1 - DCD USART2_IRQHandler ; USART2 - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD USB_IRQHandler ; USB - -__Vectors_End - -__Vectors_Size EQU __Vectors_End - __Vectors - - AREA |.text|, CODE, READONLY - -; Reset handler routine -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT __main - IMPORT SystemInit - - - - LDR R0, =__initial_sp ; set stack pointer - MSR MSP, R0 - -;;Check if boot space corresponds to test memory - - LDR R0,=0x00000004 - LDR R1, [R0] - LSRS R1, R1, #24 - LDR R2,=0x1F - CMP R1, R2 - - BNE ApplicationStart - -;; SYSCFG clock enable - - LDR R0,=0x40021018 - LDR R1,=0x00000001 - STR R1, [R0] - -;; Set CFGR1 register with flash memory remap at address 0 - - LDR R0,=0x40010000 - LDR R1,=0x00000000 - STR R1, [R0] -ApplicationStart - LDR R0, =SystemInit - BLX R0 - LDR R0, =__main - BX R0 - ENDP - -; Dummy Exception Handlers (infinite loops which can be modified) - -NMI_Handler PROC - EXPORT NMI_Handler [WEAK] - B . - ENDP -HardFault_Handler\ - PROC - EXPORT HardFault_Handler [WEAK] - B . - ENDP -SVC_Handler PROC - EXPORT SVC_Handler [WEAK] - B . - ENDP -PendSV_Handler PROC - EXPORT PendSV_Handler [WEAK] - B . - ENDP -SysTick_Handler PROC - EXPORT SysTick_Handler [WEAK] - B . - ENDP - -Default_Handler PROC - - EXPORT WWDG_IRQHandler [WEAK] - EXPORT PVD_VDDIO_IRQHandler [WEAK] - EXPORT RTC_IRQHandler [WEAK] - EXPORT FLASH_IRQHandler [WEAK] - EXPORT RCC_IRQHandler [WEAK] - EXPORT EXTI0_1_IRQHandler [WEAK] - EXPORT EXTI2_3_IRQHandler [WEAK] - EXPORT EXTI4_15_IRQHandler [WEAK] - EXPORT DMA1_Channel1_IRQHandler [WEAK] - EXPORT DMA1_Channel2_3_IRQHandler [WEAK] - EXPORT DMA1_Channel4_5_IRQHandler [WEAK] - EXPORT ADC1_IRQHandler [WEAK] - EXPORT TIM1_BRK_UP_TRG_COM_IRQHandler [WEAK] - EXPORT TIM1_CC_IRQHandler [WEAK] - EXPORT TIM3_IRQHandler [WEAK] - EXPORT TIM6_IRQHandler [WEAK] - EXPORT TIM14_IRQHandler [WEAK] - EXPORT TIM15_IRQHandler [WEAK] - EXPORT TIM16_IRQHandler [WEAK] - EXPORT TIM17_IRQHandler [WEAK] - EXPORT I2C1_IRQHandler [WEAK] - EXPORT I2C2_IRQHandler [WEAK] - EXPORT SPI1_IRQHandler [WEAK] - EXPORT SPI2_IRQHandler [WEAK] - EXPORT USART1_IRQHandler [WEAK] - EXPORT USART2_IRQHandler [WEAK] - EXPORT USB_IRQHandler [WEAK] - - -WWDG_IRQHandler -PVD_VDDIO_IRQHandler -RTC_IRQHandler -FLASH_IRQHandler -RCC_IRQHandler -EXTI0_1_IRQHandler -EXTI2_3_IRQHandler -EXTI4_15_IRQHandler -DMA1_Channel1_IRQHandler -DMA1_Channel2_3_IRQHandler -DMA1_Channel4_5_IRQHandler -ADC1_IRQHandler -TIM1_BRK_UP_TRG_COM_IRQHandler -TIM1_CC_IRQHandler -TIM3_IRQHandler -TIM6_IRQHandler -TIM14_IRQHandler -TIM15_IRQHandler -TIM16_IRQHandler -TIM17_IRQHandler -I2C1_IRQHandler -I2C2_IRQHandler -SPI1_IRQHandler -SPI2_IRQHandler -USART1_IRQHandler -USART2_IRQHandler -USB_IRQHandler - - B . - - ENDP - - ALIGN - -;******************************************************************************* -; User Stack and Heap initialization -;******************************************************************************* - IF :DEF:__MICROLIB - - EXPORT __initial_sp - EXPORT __heap_base - EXPORT __heap_limit - - ELSE - - IMPORT __use_two_region_memory - EXPORT __user_initial_stackheap - -__user_initial_stackheap - - LDR R0, = Heap_Mem - LDR R1, =(Stack_Mem + Stack_Size) - LDR R2, = (Heap_Mem + Heap_Size) - LDR R3, = Stack_Mem - BX LR - - ALIGN - - ENDIF - - END - -;************************ (C) COPYRIGHT FMD *****END OF FILE***** diff --git a/bsp/ft32/libraries/FT32F0xx/CMSIS/FT32F0xx/source/arm/startup_ft32f072xb.s b/bsp/ft32/libraries/FT32F0xx/CMSIS/FT32F0xx/source/arm/startup_ft32f072xb.s deleted file mode 100644 index 230b0ebf22b..00000000000 --- a/bsp/ft32/libraries/FT32F0xx/CMSIS/FT32F0xx/source/arm/startup_ft32f072xb.s +++ /dev/null @@ -1,254 +0,0 @@ -;/** -; ****************************************************************************** -; * @file startup_ft32f072x8.s -; * @author FMD AE -; * @brief FT32F072X8 devices vector table for MDK-ARM toolchain. -; * @version V1.0.0 -; * @data 2021-07-01 -; ****************************************************************************** -; */ - -Stack_Size EQU 0x00000400 - - AREA STACK, NOINIT, READWRITE, ALIGN=3 -Stack_Mem SPACE Stack_Size -__initial_sp - - -; Heap Configuration -; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - -Heap_Size EQU 0x00000200 - - AREA HEAP, NOINIT, READWRITE, ALIGN=3 -__heap_base -Heap_Mem SPACE Heap_Size -__heap_limit - - PRESERVE8 - THUMB - - -; Vector Table Mapped to Address 0 at Reset - AREA RESET, DATA, READONLY - EXPORT __Vectors - EXPORT __Vectors_End - EXPORT __Vectors_Size - -__Vectors DCD __initial_sp ; Top of Stack - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - - ; External Interrupts - DCD WWDG_IRQHandler ; Window Watchdog - DCD PVD_VDDIO_IRQHandler ; PVD_VDDIO - DCD RTC_IRQHandler ; RTC through EXTI Line - DCD FLASH_IRQHandler ; FLASH - DCD RCC_IRQHandler ; RCC - DCD EXTI0_1_IRQHandler ; EXTI Line 0 and 1 - DCD EXTI2_3_IRQHandler ; EXTI Line 2 and 3 - DCD EXTI4_15_IRQHandler ; EXTI Line 4 to 15 - DCD 0 ; Reserved - DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 - DCD DMA1_Channel2_3_IRQHandler ; DMA1 Channel 2 and Channel 3 - DCD DMA1_Channel4_5_IRQHandler ; DMA1 Channel 4 and Channel 5 - DCD ADC1_IRQHandler ; ADC1 - DCD TIM1_BRK_UP_TRG_COM_IRQHandler ; TIM1 Break, Update, Trigger and Commutation - DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare - DCD 0 ; Reserved - DCD TIM3_IRQHandler ; TIM3 - DCD TIM6_IRQHandler ; TIM6 - DCD 0 ; Reserved - DCD TIM14_IRQHandler ; TIM14 - DCD TIM15_IRQHandler ; TIM15 - DCD TIM16_IRQHandler ; TIM16 - DCD TIM17_IRQHandler ; TIM17 - DCD I2C1_IRQHandler ; I2C1 - DCD I2C2_IRQHandler ; I2C2 - DCD SPI1_IRQHandler ; SPI1 - DCD SPI2_IRQHandler ; SPI2 - DCD USART1_IRQHandler ; USART1 - DCD USART2_IRQHandler ; USART2 - DCD DIV_IRQHandler ; DIV - DCD 0 ; Reserved - DCD USB_IRQHandler ; USB - -__Vectors_End - -__Vectors_Size EQU __Vectors_End - __Vectors - - AREA |.text|, CODE, READONLY - -; Reset handler routine -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT __main - IMPORT SystemInit - - - - LDR R0, =__initial_sp ; set stack pointer - MSR MSP, R0 - -;;Check if boot space corresponds to test memory - - LDR R0,=0x00000004 - LDR R1, [R0] - LSRS R1, R1, #24 - LDR R2,=0x1F - CMP R1, R2 - - BNE ApplicationStart - -;; SYSCFG clock enable - - LDR R0,=0x40021018 - LDR R1,=0x00000001 - STR R1, [R0] - -;; Set CFGR1 register with flash memory remap at address 0 - - LDR R0,=0x40010000 - LDR R1,=0x00000000 - STR R1, [R0] -ApplicationStart - LDR R0, =SystemInit - BLX R0 - LDR R0, =__main - BX R0 - ENDP - -; Dummy Exception Handlers (infinite loops which can be modified) - -NMI_Handler PROC - EXPORT NMI_Handler [WEAK] - B . - ENDP -HardFault_Handler\ - PROC - EXPORT HardFault_Handler [WEAK] - B . - ENDP -SVC_Handler PROC - EXPORT SVC_Handler [WEAK] - B . - ENDP -PendSV_Handler PROC - EXPORT PendSV_Handler [WEAK] - B . - ENDP -SysTick_Handler PROC - EXPORT SysTick_Handler [WEAK] - B . - ENDP - -Default_Handler PROC - - EXPORT WWDG_IRQHandler [WEAK] - EXPORT PVD_VDDIO_IRQHandler [WEAK] - EXPORT RTC_IRQHandler [WEAK] - EXPORT FLASH_IRQHandler [WEAK] - EXPORT RCC_IRQHandler [WEAK] - EXPORT EXTI0_1_IRQHandler [WEAK] - EXPORT EXTI2_3_IRQHandler [WEAK] - EXPORT EXTI4_15_IRQHandler [WEAK] - EXPORT DMA1_Channel1_IRQHandler [WEAK] - EXPORT DMA1_Channel2_3_IRQHandler [WEAK] - EXPORT DMA1_Channel4_5_IRQHandler [WEAK] - EXPORT ADC1_IRQHandler [WEAK] - EXPORT TIM1_BRK_UP_TRG_COM_IRQHandler [WEAK] - EXPORT TIM1_CC_IRQHandler [WEAK] - EXPORT TIM3_IRQHandler [WEAK] - EXPORT TIM6_IRQHandler [WEAK] - EXPORT TIM14_IRQHandler [WEAK] - EXPORT TIM15_IRQHandler [WEAK] - EXPORT TIM16_IRQHandler [WEAK] - EXPORT TIM17_IRQHandler [WEAK] - EXPORT I2C1_IRQHandler [WEAK] - EXPORT I2C2_IRQHandler [WEAK] - EXPORT SPI1_IRQHandler [WEAK] - EXPORT SPI2_IRQHandler [WEAK] - EXPORT USART1_IRQHandler [WEAK] - EXPORT USART2_IRQHandler [WEAK] - EXPORT DIV_IRQHandler [WEAK] - EXPORT USB_IRQHandler [WEAK] - - -WWDG_IRQHandler -PVD_VDDIO_IRQHandler -RTC_IRQHandler -FLASH_IRQHandler -RCC_IRQHandler -EXTI0_1_IRQHandler -EXTI2_3_IRQHandler -EXTI4_15_IRQHandler -DMA1_Channel1_IRQHandler -DMA1_Channel2_3_IRQHandler -DMA1_Channel4_5_IRQHandler -ADC1_IRQHandler -TIM1_BRK_UP_TRG_COM_IRQHandler -TIM1_CC_IRQHandler -TIM3_IRQHandler -TIM6_IRQHandler -TIM14_IRQHandler -TIM15_IRQHandler -TIM16_IRQHandler -TIM17_IRQHandler -I2C1_IRQHandler -I2C2_IRQHandler -SPI1_IRQHandler -SPI2_IRQHandler -USART1_IRQHandler -USART2_IRQHandler -DIV_IRQHandler -USB_IRQHandler - - B . - - ENDP - - ALIGN - -;******************************************************************************* -; User Stack and Heap initialization -;******************************************************************************* - IF :DEF:__MICROLIB - - EXPORT __initial_sp - EXPORT __heap_base - EXPORT __heap_limit - - ELSE - - IMPORT __use_two_region_memory - EXPORT __user_initial_stackheap - -__user_initial_stackheap - - LDR R0, = Heap_Mem - LDR R1, =(Stack_Mem + Stack_Size) - LDR R2, = (Heap_Mem + Heap_Size) - LDR R3, = Stack_Mem - BX LR - - ALIGN - - ENDIF - - END - -;************************ (C) COPYRIGHT FMD *****END OF FILE***** diff --git a/bsp/ft32/libraries/FT32F0xx/CMSIS/FT32F0xx/source/gcc/startup_ft32f030x6.s b/bsp/ft32/libraries/FT32F0xx/CMSIS/FT32F0xx/source/gcc/startup_ft32f030x6.s deleted file mode 100644 index 2dd8a28b089..00000000000 --- a/bsp/ft32/libraries/FT32F0xx/CMSIS/FT32F0xx/source/gcc/startup_ft32f030x6.s +++ /dev/null @@ -1,258 +0,0 @@ -/** - ****************************************************************************** - * @file startup_stm32f030x6.s - * @author MCD Application Team - * @brief STM32F030x4/STM32F030x6 devices vector table for GCC toolchain. - * This module performs: - * - Set the initial SP - * - Set the initial PC == Reset_Handler, - * - Set the vector table entries with the exceptions ISR address - * - Branches to main in the C library (which eventually - * calls main()). - * After Reset the Cortex-M0 processor is in Thread mode, - * priority is Privileged, and the Stack is set to Main. - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** - */ - - .syntax unified - .cpu cortex-m0 - .fpu softvfp - .thumb - -.global g_pfnVectors -.global Default_Handler - -/* start address for the initialization values of the .data section. -defined in linker script */ -.word _sidata -/* start address for the .data section. defined in linker script */ -.word _sdata -/* end address for the .data section. defined in linker script */ -.word _edata -/* start address for the .bss section. defined in linker script */ -.word _sbss -/* end address for the .bss section. defined in linker script */ -.word _ebss - - .section .text.Reset_Handler - .weak Reset_Handler - .type Reset_Handler, %function -Reset_Handler: - ldr r0, =_estack - mov sp, r0 /* set stack pointer */ - -/* Copy the data segment initializers from flash to SRAM */ - ldr r0, =_sdata - ldr r1, =_edata - ldr r2, =_sidata - movs r3, #0 - b LoopCopyDataInit - -CopyDataInit: - ldr r4, [r2, r3] - str r4, [r0, r3] - adds r3, r3, #4 - -LoopCopyDataInit: - adds r4, r0, r3 - cmp r4, r1 - bcc CopyDataInit - -/* Zero fill the bss segment. */ - ldr r2, =_sbss - ldr r4, =_ebss - movs r3, #0 - b LoopFillZerobss - -FillZerobss: - str r3, [r2] - adds r2, r2, #4 - -LoopFillZerobss: - cmp r2, r4 - bcc FillZerobss - -/* Call the clock system intitialization function.*/ - bl SystemInit -/* Call static constructors */ - bl __libc_init_array -/* Call the application's entry point.*/ - bl entry - -LoopForever: - b LoopForever - - -.size Reset_Handler, .-Reset_Handler - -/** - * @brief This is the code that gets called when the processor receives an - * unexpected interrupt. This simply enters an infinite loop, preserving - * the system state for examination by a debugger. - * - * @param None - * @retval : None -*/ - .section .text.Default_Handler,"ax",%progbits -Default_Handler: -Infinite_Loop: - b Infinite_Loop - .size Default_Handler, .-Default_Handler -/****************************************************************************** -* -* The minimal vector table for a Cortex M0. Note that the proper constructs -* must be placed on this to ensure that it ends up at physical address -* 0x0000.0000. -* -******************************************************************************/ - .section .isr_vector,"a",%progbits - .type g_pfnVectors, %object - .size g_pfnVectors, .-g_pfnVectors - - -g_pfnVectors: - .word _estack - .word Reset_Handler - .word NMI_Handler - .word HardFault_Handler - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word SVC_Handler - .word 0 - .word 0 - .word PendSV_Handler - .word SysTick_Handler - .word WWDG_IRQHandler /* Window WatchDog */ - .word 0 /* Reserved */ - .word RTC_IRQHandler /* RTC through the EXTI line */ - .word FLASH_IRQHandler /* FLASH */ - .word RCC_IRQHandler /* RCC */ - .word EXTI0_1_IRQHandler /* EXTI Line 0 and 1 */ - .word EXTI2_3_IRQHandler /* EXTI Line 2 and 3 */ - .word EXTI4_15_IRQHandler /* EXTI Line 4 to 15 */ - .word 0 /* Reserved */ - .word DMA1_Channel1_IRQHandler /* DMA1 Channel 1 */ - .word DMA1_Channel2_3_IRQHandler /* DMA1 Channel 2 and Channel 3 */ - .word DMA1_Channel4_5_IRQHandler /* DMA1 Channel 4 and Channel 5 */ - .word ADC1_IRQHandler /* ADC1 */ - .word TIM1_BRK_UP_TRG_COM_IRQHandler /* TIM1 Break, Update, Trigger and Commutation */ - .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */ - .word 0 /* Reserved */ - .word TIM3_IRQHandler /* TIM3 */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word TIM14_IRQHandler /* TIM14 */ - .word 0 /* Reserved */ - .word TIM16_IRQHandler /* TIM16 */ - .word TIM17_IRQHandler /* TIM17 */ - .word I2C1_IRQHandler /* I2C1 */ - .word 0 /* Reserved */ - .word SPI1_IRQHandler /* SPI1 */ - .word 0 /* Reserved */ - .word USART1_IRQHandler /* USART1 */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - -/******************************************************************************* -* -* Provide weak aliases for each Exception handler to the Default_Handler. -* As they are weak aliases, any function with the same name will override -* this definition. -* -*******************************************************************************/ - - .weak NMI_Handler - .thumb_set NMI_Handler,Default_Handler - - .weak HardFault_Handler - .thumb_set HardFault_Handler,Default_Handler - - .weak SVC_Handler - .thumb_set SVC_Handler,Default_Handler - - .weak PendSV_Handler - .thumb_set PendSV_Handler,Default_Handler - - .weak SysTick_Handler - .thumb_set SysTick_Handler,Default_Handler - - .weak WWDG_IRQHandler - .thumb_set WWDG_IRQHandler,Default_Handler - - .weak RTC_IRQHandler - .thumb_set RTC_IRQHandler,Default_Handler - - .weak FLASH_IRQHandler - .thumb_set FLASH_IRQHandler,Default_Handler - - .weak RCC_IRQHandler - .thumb_set RCC_IRQHandler,Default_Handler - - .weak EXTI0_1_IRQHandler - .thumb_set EXTI0_1_IRQHandler,Default_Handler - - .weak EXTI2_3_IRQHandler - .thumb_set EXTI2_3_IRQHandler,Default_Handler - - .weak EXTI4_15_IRQHandler - .thumb_set EXTI4_15_IRQHandler,Default_Handler - - .weak DMA1_Channel1_IRQHandler - .thumb_set DMA1_Channel1_IRQHandler,Default_Handler - - .weak DMA1_Channel2_3_IRQHandler - .thumb_set DMA1_Channel2_3_IRQHandler,Default_Handler - - .weak DMA1_Channel4_5_IRQHandler - .thumb_set DMA1_Channel4_5_IRQHandler,Default_Handler - - .weak ADC1_IRQHandler - .thumb_set ADC1_IRQHandler,Default_Handler - - .weak TIM1_BRK_UP_TRG_COM_IRQHandler - .thumb_set TIM1_BRK_UP_TRG_COM_IRQHandler,Default_Handler - - .weak TIM1_CC_IRQHandler - .thumb_set TIM1_CC_IRQHandler,Default_Handler - - .weak TIM3_IRQHandler - .thumb_set TIM3_IRQHandler,Default_Handler - - .weak TIM14_IRQHandler - .thumb_set TIM14_IRQHandler,Default_Handler - - .weak TIM16_IRQHandler - .thumb_set TIM16_IRQHandler,Default_Handler - - .weak TIM17_IRQHandler - .thumb_set TIM17_IRQHandler,Default_Handler - - .weak I2C1_IRQHandler - .thumb_set I2C1_IRQHandler,Default_Handler - - .weak SPI1_IRQHandler - .thumb_set SPI1_IRQHandler,Default_Handler - - .weak USART1_IRQHandler - .thumb_set USART1_IRQHandler,Default_Handler - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ - diff --git a/bsp/ft32/libraries/FT32F0xx/CMSIS/FT32F0xx/source/gcc/startup_ft32f030x8.s b/bsp/ft32/libraries/FT32F0xx/CMSIS/FT32F0xx/source/gcc/startup_ft32f030x8.s deleted file mode 100644 index b65a82bb6ea..00000000000 --- a/bsp/ft32/libraries/FT32F0xx/CMSIS/FT32F0xx/source/gcc/startup_ft32f030x8.s +++ /dev/null @@ -1,273 +0,0 @@ -/** - ****************************************************************************** - * @file startup_stm32f030x8.s - * @author MCD Application Team - * @brief STM32F030x8 devices vector table for GCC toolchain. - * This module performs: - * - Set the initial SP - * - Set the initial PC == Reset_Handler, - * - Set the vector table entries with the exceptions ISR address - * - Branches to main in the C library (which eventually - * calls main()). - * After Reset the Cortex-M0 processor is in Thread mode, - * priority is Privileged, and the Stack is set to Main. - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** - */ - - .syntax unified - .cpu cortex-m0 - .fpu softvfp - .thumb - -.global g_pfnVectors -.global Default_Handler - -/* start address for the initialization values of the .data section. -defined in linker script */ -.word _sidata -/* start address for the .data section. defined in linker script */ -.word _sdata -/* end address for the .data section. defined in linker script */ -.word _edata -/* start address for the .bss section. defined in linker script */ -.word _sbss -/* end address for the .bss section. defined in linker script */ -.word _ebss - - .section .text.Reset_Handler - .weak Reset_Handler - .type Reset_Handler, %function -Reset_Handler: - ldr r0, =_estack - mov sp, r0 /* set stack pointer */ - -/* Copy the data segment initializers from flash to SRAM */ - ldr r0, =_sdata - ldr r1, =_edata - ldr r2, =_sidata - movs r3, #0 - b LoopCopyDataInit - -CopyDataInit: - ldr r4, [r2, r3] - str r4, [r0, r3] - adds r3, r3, #4 - -LoopCopyDataInit: - adds r4, r0, r3 - cmp r4, r1 - bcc CopyDataInit - -/* Zero fill the bss segment. */ - ldr r2, =_sbss - ldr r4, =_ebss - movs r3, #0 - b LoopFillZerobss - -FillZerobss: - str r3, [r2] - adds r2, r2, #4 - -LoopFillZerobss: - cmp r2, r4 - bcc FillZerobss - -/* Call the clock system intitialization function.*/ - bl SystemInit -/* Call static constructors */ - bl __libc_init_array -/* Call the application's entry point.*/ - bl entry - -LoopForever: - b LoopForever - - -.size Reset_Handler, .-Reset_Handler - -/** - * @brief This is the code that gets called when the processor receives an - * unexpected interrupt. This simply enters an infinite loop, preserving - * the system state for examination by a debugger. - * - * @param None - * @retval : None -*/ - .section .text.Default_Handler,"ax",%progbits -Default_Handler: -Infinite_Loop: - b Infinite_Loop - .size Default_Handler, .-Default_Handler -/****************************************************************************** -* -* The minimal vector table for a Cortex M0. Note that the proper constructs -* must be placed on this to ensure that it ends up at physical address -* 0x0000.0000. -* -******************************************************************************/ - .section .isr_vector,"a",%progbits - .type g_pfnVectors, %object - .size g_pfnVectors, .-g_pfnVectors - - -g_pfnVectors: - .word _estack - .word Reset_Handler - .word NMI_Handler - .word HardFault_Handler - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word SVC_Handler - .word 0 - .word 0 - .word PendSV_Handler - .word SysTick_Handler - .word WWDG_IRQHandler /* Window WatchDog */ - .word 0 /* Reserved */ - .word RTC_IRQHandler /* RTC through the EXTI line */ - .word FLASH_IRQHandler /* FLASH */ - .word RCC_IRQHandler /* RCC */ - .word EXTI0_1_IRQHandler /* EXTI Line 0 and 1 */ - .word EXTI2_3_IRQHandler /* EXTI Line 2 and 3 */ - .word EXTI4_15_IRQHandler /* EXTI Line 4 to 15 */ - .word 0 /* Reserved */ - .word DMA1_Channel1_IRQHandler /* DMA1 Channel 1 */ - .word DMA1_Channel2_3_IRQHandler /* DMA1 Channel 2 and Channel 3 */ - .word DMA1_Channel4_5_IRQHandler /* DMA1 Channel 4 and Channel 5 */ - .word ADC1_IRQHandler /* ADC1 */ - .word TIM1_BRK_UP_TRG_COM_IRQHandler /* TIM1 Break, Update, Trigger and Commutation */ - .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */ - .word 0 /* Reserved */ - .word TIM3_IRQHandler /* TIM3 */ - .word TIM6_IRQHandler /* TIM6 */ - .word 0 /* Reserved */ - .word TIM14_IRQHandler /* TIM14 */ - .word TIM15_IRQHandler /* TIM15 */ - .word TIM16_IRQHandler /* TIM16 */ - .word TIM17_IRQHandler /* TIM17 */ - .word I2C1_IRQHandler /* I2C1 */ - .word I2C2_IRQHandler /* I2C2 */ - .word SPI1_IRQHandler /* SPI1 */ - .word SPI2_IRQHandler /* SPI2 */ - .word USART1_IRQHandler /* USART1 */ - .word USART2_IRQHandler /* USART2 */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - -/******************************************************************************* -* -* Provide weak aliases for each Exception handler to the Default_Handler. -* As they are weak aliases, any function with the same name will override -* this definition. -* -*******************************************************************************/ - - .weak NMI_Handler - .thumb_set NMI_Handler,Default_Handler - - .weak HardFault_Handler - .thumb_set HardFault_Handler,Default_Handler - - .weak SVC_Handler - .thumb_set SVC_Handler,Default_Handler - - .weak PendSV_Handler - .thumb_set PendSV_Handler,Default_Handler - - .weak SysTick_Handler - .thumb_set SysTick_Handler,Default_Handler - - .weak WWDG_IRQHandler - .thumb_set WWDG_IRQHandler,Default_Handler - - .weak RTC_IRQHandler - .thumb_set RTC_IRQHandler,Default_Handler - - .weak FLASH_IRQHandler - .thumb_set FLASH_IRQHandler,Default_Handler - - .weak RCC_IRQHandler - .thumb_set RCC_IRQHandler,Default_Handler - - .weak EXTI0_1_IRQHandler - .thumb_set EXTI0_1_IRQHandler,Default_Handler - - .weak EXTI2_3_IRQHandler - .thumb_set EXTI2_3_IRQHandler,Default_Handler - - .weak EXTI4_15_IRQHandler - .thumb_set EXTI4_15_IRQHandler,Default_Handler - - .weak DMA1_Channel1_IRQHandler - .thumb_set DMA1_Channel1_IRQHandler,Default_Handler - - .weak DMA1_Channel2_3_IRQHandler - .thumb_set DMA1_Channel2_3_IRQHandler,Default_Handler - - .weak DMA1_Channel4_5_IRQHandler - .thumb_set DMA1_Channel4_5_IRQHandler,Default_Handler - - .weak ADC1_IRQHandler - .thumb_set ADC1_IRQHandler,Default_Handler - - .weak TIM1_BRK_UP_TRG_COM_IRQHandler - .thumb_set TIM1_BRK_UP_TRG_COM_IRQHandler,Default_Handler - - .weak TIM1_CC_IRQHandler - .thumb_set TIM1_CC_IRQHandler,Default_Handler - - .weak TIM3_IRQHandler - .thumb_set TIM3_IRQHandler,Default_Handler - - .weak TIM6_IRQHandler - .thumb_set TIM6_IRQHandler,Default_Handler - - .weak TIM14_IRQHandler - .thumb_set TIM14_IRQHandler,Default_Handler - - .weak TIM15_IRQHandler - .thumb_set TIM15_IRQHandler,Default_Handler - - .weak TIM16_IRQHandler - .thumb_set TIM16_IRQHandler,Default_Handler - - .weak TIM17_IRQHandler - .thumb_set TIM17_IRQHandler,Default_Handler - - .weak I2C1_IRQHandler - .thumb_set I2C1_IRQHandler,Default_Handler - - .weak I2C2_IRQHandler - .thumb_set I2C2_IRQHandler,Default_Handler - - .weak SPI1_IRQHandler - .thumb_set SPI1_IRQHandler,Default_Handler - - .weak SPI2_IRQHandler - .thumb_set SPI2_IRQHandler,Default_Handler - - .weak USART1_IRQHandler - .thumb_set USART1_IRQHandler,Default_Handler - - .weak USART2_IRQHandler - .thumb_set USART2_IRQHandler,Default_Handler - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ - diff --git a/bsp/ft32/libraries/FT32F0xx/CMSIS/FT32F0xx/source/gcc/startup_ft32f072xb.s b/bsp/ft32/libraries/FT32F0xx/CMSIS/FT32F0xx/source/gcc/startup_ft32f072xb.s deleted file mode 100644 index 1e110032855..00000000000 --- a/bsp/ft32/libraries/FT32F0xx/CMSIS/FT32F0xx/source/gcc/startup_ft32f072xb.s +++ /dev/null @@ -1,294 +0,0 @@ -/** - ****************************************************************************** - * @file startup_stm32f072xb.s - * @author MCD Application Team - * @brief STM32F072x8/STM32F072xB devices vector table for GCC toolchain. - * This module performs: - * - Set the initial SP - * - Set the initial PC == Reset_Handler, - * - Set the vector table entries with the exceptions ISR address - * - Branches to main in the C library (which eventually - * calls main()). - * After Reset the Cortex-M0 processor is in Thread mode, - * priority is Privileged, and the Stack is set to Main. - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** - */ - - .syntax unified - .cpu cortex-m0 - .fpu softvfp - .thumb - -.global g_pfnVectors -.global Default_Handler - -/* start address for the initialization values of the .data section. -defined in linker script */ -.word _sidata -/* start address for the .data section. defined in linker script */ -.word _sdata -/* end address for the .data section. defined in linker script */ -.word _edata -/* start address for the .bss section. defined in linker script */ -.word _sbss -/* end address for the .bss section. defined in linker script */ -.word _ebss - - .section .text.Reset_Handler - .weak Reset_Handler - .type Reset_Handler, %function -Reset_Handler: - ldr r0, =_estack - mov sp, r0 /* set stack pointer */ - -/* Copy the data segment initializers from flash to SRAM */ - ldr r0, =_sdata - ldr r1, =_edata - ldr r2, =_sidata - movs r3, #0 - b LoopCopyDataInit - -CopyDataInit: - ldr r4, [r2, r3] - str r4, [r0, r3] - adds r3, r3, #4 - -LoopCopyDataInit: - adds r4, r0, r3 - cmp r4, r1 - bcc CopyDataInit - -/* Zero fill the bss segment. */ - ldr r2, =_sbss - ldr r4, =_ebss - movs r3, #0 - b LoopFillZerobss - -FillZerobss: - str r3, [r2] - adds r2, r2, #4 - -LoopFillZerobss: - cmp r2, r4 - bcc FillZerobss - -/* Call the clock system intitialization function.*/ - bl SystemInit -/* Call static constructors */ - bl __libc_init_array -/* Call the application's entry point.*/ - bl entry - -LoopForever: - b LoopForever - - -.size Reset_Handler, .-Reset_Handler - -/** - * @brief This is the code that gets called when the processor receives an - * unexpected interrupt. This simply enters an infinite loop, preserving - * the system state for examination by a debugger. - * - * @param None - * @retval : None -*/ - .section .text.Default_Handler,"ax",%progbits -Default_Handler: -Infinite_Loop: - b Infinite_Loop - .size Default_Handler, .-Default_Handler -/****************************************************************************** -* -* The minimal vector table for a Cortex M0. Note that the proper constructs -* must be placed on this to ensure that it ends up at physical address -* 0x0000.0000. -* -******************************************************************************/ - .section .isr_vector,"a",%progbits - .type g_pfnVectors, %object - .size g_pfnVectors, .-g_pfnVectors - - -g_pfnVectors: - .word _estack - .word Reset_Handler - .word NMI_Handler - .word HardFault_Handler - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word SVC_Handler - .word 0 - .word 0 - .word PendSV_Handler - .word SysTick_Handler - .word WWDG_IRQHandler /* Window WatchDog */ - .word PVD_VDDIO2_IRQHandler /* PVD and VDDIO2 through EXTI Line detect */ - .word RTC_IRQHandler /* RTC through the EXTI line */ - .word FLASH_IRQHandler /* FLASH */ - .word RCC_CRS_IRQHandler /* RCC and CRS */ - .word EXTI0_1_IRQHandler /* EXTI Line 0 and 1 */ - .word EXTI2_3_IRQHandler /* EXTI Line 2 and 3 */ - .word EXTI4_15_IRQHandler /* EXTI Line 4 to 15 */ - .word TSC_IRQHandler /* TSC */ - .word DMA1_Channel1_IRQHandler /* DMA1 Channel 1 */ - .word DMA1_Channel2_3_IRQHandler /* DMA1 Channel 2 and Channel 3 */ - .word DMA1_Channel4_5_6_7_IRQHandler /* DMA1 Channel 4, Channel 5, Channel 6 and Channel 7*/ - .word ADC1_COMP_IRQHandler /* ADC1, COMP1 and COMP2 */ - .word TIM1_BRK_UP_TRG_COM_IRQHandler /* TIM1 Break, Update, Trigger and Commutation */ - .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */ - .word TIM2_IRQHandler /* TIM2 */ - .word TIM3_IRQHandler /* TIM3 */ - .word TIM6_DAC_IRQHandler /* TIM6 and DAC */ - .word TIM7_IRQHandler /* TIM7 */ - .word TIM14_IRQHandler /* TIM14 */ - .word TIM15_IRQHandler /* TIM15 */ - .word TIM16_IRQHandler /* TIM16 */ - .word TIM17_IRQHandler /* TIM17 */ - .word I2C1_IRQHandler /* I2C1 */ - .word I2C2_IRQHandler /* I2C2 */ - .word SPI1_IRQHandler /* SPI1 */ - .word SPI2_IRQHandler /* SPI2 */ - .word USART1_IRQHandler /* USART1 */ - .word USART2_IRQHandler /* USART2 */ - .word USART3_4_IRQHandler /* USART3 and USART4 */ - .word CEC_CAN_IRQHandler /* CEC and CAN */ - .word USB_IRQHandler /* USB */ - -/******************************************************************************* -* -* Provide weak aliases for each Exception handler to the Default_Handler. -* As they are weak aliases, any function with the same name will override -* this definition. -* -*******************************************************************************/ - - .weak NMI_Handler - .thumb_set NMI_Handler,Default_Handler - - .weak HardFault_Handler - .thumb_set HardFault_Handler,Default_Handler - - .weak SVC_Handler - .thumb_set SVC_Handler,Default_Handler - - .weak PendSV_Handler - .thumb_set PendSV_Handler,Default_Handler - - .weak SysTick_Handler - .thumb_set SysTick_Handler,Default_Handler - - .weak WWDG_IRQHandler - .thumb_set WWDG_IRQHandler,Default_Handler - - .weak PVD_VDDIO2_IRQHandler - .thumb_set PVD_VDDIO2_IRQHandler,Default_Handler - - .weak RTC_IRQHandler - .thumb_set RTC_IRQHandler,Default_Handler - - .weak FLASH_IRQHandler - .thumb_set FLASH_IRQHandler,Default_Handler - - .weak RCC_CRS_IRQHandler - .thumb_set RCC_CRS_IRQHandler,Default_Handler - - .weak EXTI0_1_IRQHandler - .thumb_set EXTI0_1_IRQHandler,Default_Handler - - .weak EXTI2_3_IRQHandler - .thumb_set EXTI2_3_IRQHandler,Default_Handler - - .weak EXTI4_15_IRQHandler - .thumb_set EXTI4_15_IRQHandler,Default_Handler - - .weak TSC_IRQHandler - .thumb_set TSC_IRQHandler,Default_Handler - - .weak DMA1_Channel1_IRQHandler - .thumb_set DMA1_Channel1_IRQHandler,Default_Handler - - .weak DMA1_Channel2_3_IRQHandler - .thumb_set DMA1_Channel2_3_IRQHandler,Default_Handler - - .weak DMA1_Channel4_5_6_7_IRQHandler - .thumb_set DMA1_Channel4_5_6_7_IRQHandler,Default_Handler - - .weak ADC1_COMP_IRQHandler - .thumb_set ADC1_COMP_IRQHandler,Default_Handler - - .weak TIM1_BRK_UP_TRG_COM_IRQHandler - .thumb_set TIM1_BRK_UP_TRG_COM_IRQHandler,Default_Handler - - .weak TIM1_CC_IRQHandler - .thumb_set TIM1_CC_IRQHandler,Default_Handler - - .weak TIM2_IRQHandler - .thumb_set TIM2_IRQHandler,Default_Handler - - .weak TIM3_IRQHandler - .thumb_set TIM3_IRQHandler,Default_Handler - - .weak TIM6_DAC_IRQHandler - .thumb_set TIM6_DAC_IRQHandler,Default_Handler - - .weak TIM7_IRQHandler - .thumb_set TIM7_IRQHandler,Default_Handler - - .weak TIM14_IRQHandler - .thumb_set TIM14_IRQHandler,Default_Handler - - .weak TIM15_IRQHandler - .thumb_set TIM15_IRQHandler,Default_Handler - - .weak TIM16_IRQHandler - .thumb_set TIM16_IRQHandler,Default_Handler - - .weak TIM17_IRQHandler - .thumb_set TIM17_IRQHandler,Default_Handler - - .weak I2C1_IRQHandler - .thumb_set I2C1_IRQHandler,Default_Handler - - .weak I2C2_IRQHandler - .thumb_set I2C2_IRQHandler,Default_Handler - - .weak SPI1_IRQHandler - .thumb_set SPI1_IRQHandler,Default_Handler - - .weak SPI2_IRQHandler - .thumb_set SPI2_IRQHandler,Default_Handler - - .weak USART1_IRQHandler - .thumb_set USART1_IRQHandler,Default_Handler - - .weak USART2_IRQHandler - .thumb_set USART2_IRQHandler,Default_Handler - - .weak USART3_4_IRQHandler - .thumb_set USART3_4_IRQHandler,Default_Handler - - .weak CEC_CAN_IRQHandler - .thumb_set CEC_CAN_IRQHandler,Default_Handler - - .weak USB_IRQHandler - .thumb_set USB_IRQHandler,Default_Handler - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ - diff --git a/bsp/ft32/libraries/FT32F0xx/CMSIS/FT32F0xx/source/iar/linker/stm32f030x6_flash.icf b/bsp/ft32/libraries/FT32F0xx/CMSIS/FT32F0xx/source/iar/linker/stm32f030x6_flash.icf deleted file mode 100644 index 0bb19fbf749..00000000000 --- a/bsp/ft32/libraries/FT32F0xx/CMSIS/FT32F0xx/source/iar/linker/stm32f030x6_flash.icf +++ /dev/null @@ -1,33 +0,0 @@ -/*###ICF### Section handled by ICF editor, don't touch! ****/ -/*-Editor annotation file-*/ -/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ -/*-Specials-*/ -define symbol __ICFEDIT_intvec_start__ = 0x08000000; -/*-Memory Regions-*/ -define symbol __ICFEDIT_region_ROM_start__ = 0x08000000; -define symbol __ICFEDIT_region_ROM_end__ = 0x08007FFF; -define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; -define symbol __ICFEDIT_region_RAM_end__ = 0x20000FFF; -/*-Sizes-*/ -define symbol __ICFEDIT_size_cstack__ = 0x400; -define symbol __ICFEDIT_size_heap__ = 0x000; -/**** End of ICF editor section. ###ICF###*/ - -define memory mem with size = 4G; -define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; -define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; - -define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; -define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; - -initialize by copy { readwrite }; -do not initialize { section .noinit }; - -place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; - -place in ROM_region { readonly }; -place in RAM_region { readwrite, - block CSTACK, block HEAP }; - -export symbol __ICFEDIT_region_RAM_start__; -export symbol __ICFEDIT_region_RAM_end__; diff --git a/bsp/ft32/libraries/FT32F0xx/CMSIS/FT32F0xx/source/iar/linker/stm32f030x8_flash.icf b/bsp/ft32/libraries/FT32F0xx/CMSIS/FT32F0xx/source/iar/linker/stm32f030x8_flash.icf deleted file mode 100644 index 397a960ef40..00000000000 --- a/bsp/ft32/libraries/FT32F0xx/CMSIS/FT32F0xx/source/iar/linker/stm32f030x8_flash.icf +++ /dev/null @@ -1,33 +0,0 @@ -/*###ICF### Section handled by ICF editor, don't touch! ****/ -/*-Editor annotation file-*/ -/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ -/*-Specials-*/ -define symbol __ICFEDIT_intvec_start__ = 0x08000000; -/*-Memory Regions-*/ -define symbol __ICFEDIT_region_ROM_start__ = 0x08000000; -define symbol __ICFEDIT_region_ROM_end__ = 0x0800FFFF; -define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; -define symbol __ICFEDIT_region_RAM_end__ = 0x20001FFF; -/*-Sizes-*/ -define symbol __ICFEDIT_size_cstack__ = 0x400; -define symbol __ICFEDIT_size_heap__ = 0x000; -/**** End of ICF editor section. ###ICF###*/ - -define memory mem with size = 4G; -define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; -define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; - -define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; -define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; - -initialize by copy { readwrite }; -do not initialize { section .noinit }; - -place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; - -place in ROM_region { readonly }; -place in RAM_region { readwrite, - block CSTACK, block HEAP }; - -export symbol __ICFEDIT_region_RAM_start__; -export symbol __ICFEDIT_region_RAM_end__; diff --git a/bsp/ft32/libraries/FT32F0xx/CMSIS/FT32F0xx/source/iar/linker/stm32f072xb_flash.icf b/bsp/ft32/libraries/FT32F0xx/CMSIS/FT32F0xx/source/iar/linker/stm32f072xb_flash.icf deleted file mode 100644 index cd275db870d..00000000000 --- a/bsp/ft32/libraries/FT32F0xx/CMSIS/FT32F0xx/source/iar/linker/stm32f072xb_flash.icf +++ /dev/null @@ -1,33 +0,0 @@ -/*###ICF### Section handled by ICF editor, don't touch! ****/ -/*-Editor annotation file-*/ -/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ -/*-Specials-*/ -define symbol __ICFEDIT_intvec_start__ = 0x08000000; -/*-Memory Regions-*/ -define symbol __ICFEDIT_region_ROM_start__ = 0x08000000; -define symbol __ICFEDIT_region_ROM_end__ = 0x0801FFFF; -define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; -define symbol __ICFEDIT_region_RAM_end__ = 0x20003FFF; -/*-Sizes-*/ -define symbol __ICFEDIT_size_cstack__ = 0x400; -define symbol __ICFEDIT_size_heap__ = 0x000; -/**** End of ICF editor section. ###ICF###*/ - -define memory mem with size = 4G; -define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; -define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; - -define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; -define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; - -initialize by copy { readwrite }; -do not initialize { section .noinit }; - -place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; - -place in ROM_region { readonly }; -place in RAM_region { readwrite, - block CSTACK, block HEAP }; - -export symbol __ICFEDIT_region_RAM_start__; -export symbol __ICFEDIT_region_RAM_end__; diff --git a/bsp/ft32/libraries/FT32F0xx/CMSIS/FT32F0xx/source/iar/startup_ft32f030x6.s b/bsp/ft32/libraries/FT32F0xx/CMSIS/FT32F0xx/source/iar/startup_ft32f030x6.s deleted file mode 100644 index a3575ee9a9f..00000000000 --- a/bsp/ft32/libraries/FT32F0xx/CMSIS/FT32F0xx/source/iar/startup_ft32f030x6.s +++ /dev/null @@ -1,245 +0,0 @@ -;******************************************************************************* -;* File Name : startup_stm32f030x6.s -;* Author : MCD Application Team -;* Description : STM32F030x4/STM32F030x6 devices vector table for EWARM toolchain. -;* This module performs: -;* - Set the initial SP -;* - Set the initial PC == __iar_program_start, -;* - Set the vector table entries with the exceptions ISR -;* address, -;* - Branches to main in the C library (which eventually -;* calls main()). -;* After Reset the Cortex-M0 processor is in Thread mode, -;* priority is Privileged, and the Stack is set to Main. -;******************************************************************************* -;* @attention -;* -;*

© Copyright (c) 2016 STMicroelectronics. -;* All rights reserved.

-;* -;* This software component is licensed by ST under BSD 3-Clause license, -;* the "License"; You may not use this file except in compliance with the -;* License. You may obtain a copy of the License at: -;* opensource.org/licenses/BSD-3-Clause -;* -;******************************************************************************* -; -; -; The modules in this file are included in the libraries, and may be replaced -; by any user-defined modules that define the PUBLIC symbol _program_start or -; a user defined start symbol. -; To override the cstartup defined in the library, simply add your modified -; version to the workbench project. -; -; The vector table is normally located at address 0. -; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. -; The name "__vector_table" has special meaning for C-SPY: -; it is where the SP start value is found, and the NVIC vector -; table register (VTOR) is initialized to this address if != 0. -; -; Cortex-M version -; - - MODULE ?cstartup - - ;; Forward declaration of sections. - SECTION CSTACK:DATA:NOROOT(3) - - SECTION .intvec:CODE:NOROOT(2) - - EXTERN __iar_program_start - EXTERN SystemInit - PUBLIC __vector_table - - DATA -__vector_table - DCD sfe(CSTACK) - DCD Reset_Handler ; Reset Handler - - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - - ; External Interrupts - DCD WWDG_IRQHandler ; Window Watchdog - DCD 0 ; Reserved - DCD RTC_IRQHandler ; RTC through EXTI Line - DCD FLASH_IRQHandler ; FLASH - DCD RCC_IRQHandler ; RCC - DCD EXTI0_1_IRQHandler ; EXTI Line 0 and 1 - DCD EXTI2_3_IRQHandler ; EXTI Line 2 and 3 - DCD EXTI4_15_IRQHandler ; EXTI Line 4 to 15 - DCD 0 ; Reserved - DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 - DCD DMA1_Channel2_3_IRQHandler ; DMA1 Channel 2 and Channel 3 - DCD DMA1_Channel4_5_IRQHandler ; DMA1 Channel 4 and Channel 5 - DCD ADC1_IRQHandler ; ADC1 - DCD TIM1_BRK_UP_TRG_COM_IRQHandler ; TIM1 Break, Update, Trigger and Commutation - DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare - DCD 0 ; Reserved - DCD TIM3_IRQHandler ; TIM3 - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD TIM14_IRQHandler ; TIM14 - DCD 0 ; Reserved - DCD TIM16_IRQHandler ; TIM16 - DCD TIM17_IRQHandler ; TIM17 - DCD I2C1_IRQHandler ; I2C1 - DCD 0 ; Reserved - DCD SPI1_IRQHandler ; SPI1 - DCD 0 ; Reserved - DCD USART1_IRQHandler ; USART1 - -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -;; -;; Default interrupt handlers. -;; - THUMB - - PUBWEAK Reset_Handler - SECTION .text:CODE:NOROOT:REORDER(2) -Reset_Handler - LDR R0, =SystemInit - BLX R0 - LDR R0, =__iar_program_start - BX R0 - - PUBWEAK NMI_Handler - SECTION .text:CODE:NOROOT:REORDER(1) -NMI_Handler - B NMI_Handler - - PUBWEAK HardFault_Handler - SECTION .text:CODE:NOROOT:REORDER(1) -HardFault_Handler - B HardFault_Handler - - PUBWEAK SVC_Handler - SECTION .text:CODE:NOROOT:REORDER(1) -SVC_Handler - B SVC_Handler - - PUBWEAK PendSV_Handler - SECTION .text:CODE:NOROOT:REORDER(1) -PendSV_Handler - B PendSV_Handler - - PUBWEAK SysTick_Handler - SECTION .text:CODE:NOROOT:REORDER(1) -SysTick_Handler - B SysTick_Handler - - PUBWEAK WWDG_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -WWDG_IRQHandler - B WWDG_IRQHandler - - PUBWEAK RTC_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -RTC_IRQHandler - B RTC_IRQHandler - - PUBWEAK FLASH_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -FLASH_IRQHandler - B FLASH_IRQHandler - - PUBWEAK RCC_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -RCC_IRQHandler - B RCC_IRQHandler - - PUBWEAK EXTI0_1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -EXTI0_1_IRQHandler - B EXTI0_1_IRQHandler - - PUBWEAK EXTI2_3_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -EXTI2_3_IRQHandler - B EXTI2_3_IRQHandler - - PUBWEAK EXTI4_15_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -EXTI4_15_IRQHandler - B EXTI4_15_IRQHandler - - PUBWEAK DMA1_Channel1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA1_Channel1_IRQHandler - B DMA1_Channel1_IRQHandler - - PUBWEAK DMA1_Channel2_3_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA1_Channel2_3_IRQHandler - B DMA1_Channel2_3_IRQHandler - - PUBWEAK DMA1_Channel4_5_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA1_Channel4_5_IRQHandler - B DMA1_Channel4_5_IRQHandler - - PUBWEAK ADC1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -ADC1_IRQHandler - B ADC1_IRQHandler - - PUBWEAK TIM1_BRK_UP_TRG_COM_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM1_BRK_UP_TRG_COM_IRQHandler - B TIM1_BRK_UP_TRG_COM_IRQHandler - - PUBWEAK TIM1_CC_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM1_CC_IRQHandler - B TIM1_CC_IRQHandler - - PUBWEAK TIM3_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM3_IRQHandler - B TIM3_IRQHandler - - PUBWEAK TIM14_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM14_IRQHandler - B TIM14_IRQHandler - - PUBWEAK TIM16_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM16_IRQHandler - B TIM16_IRQHandler - - PUBWEAK TIM17_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM17_IRQHandler - B TIM17_IRQHandler - - PUBWEAK I2C1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -I2C1_IRQHandler - B I2C1_IRQHandler - - PUBWEAK SPI1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -SPI1_IRQHandler - B SPI1_IRQHandler - - PUBWEAK USART1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -USART1_IRQHandler - B USART1_IRQHandler - - - END -;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE***** diff --git a/bsp/ft32/libraries/FT32F0xx/CMSIS/FT32F0xx/source/iar/startup_ft32f030x8.s b/bsp/ft32/libraries/FT32F0xx/CMSIS/FT32F0xx/source/iar/startup_ft32f030x8.s deleted file mode 100644 index ee339812016..00000000000 --- a/bsp/ft32/libraries/FT32F0xx/CMSIS/FT32F0xx/source/iar/startup_ft32f030x8.s +++ /dev/null @@ -1,274 +0,0 @@ -;******************************************************************************* -;* File Name : startup_stm32f030x8.s -;* Author : MCD Application Team -;* Description : STM32F030x8 devices vector table for EWARM toolchain. -;* This module performs: -;* - Set the initial SP -;* - Set the initial PC == __iar_program_start, -;* - Set the vector table entries with the exceptions ISR -;* address, -;* - Branches to main in the C library (which eventually -;* calls main()). -;* After Reset the Cortex-M0 processor is in Thread mode, -;* priority is Privileged, and the Stack is set to Main. -;******************************************************************************* -;* @attention -;* -;*

© Copyright (c) 2016 STMicroelectronics. -;* All rights reserved.

-;* -;* This software component is licensed by ST under BSD 3-Clause license, -;* the "License"; You may not use this file except in compliance with the -;* License. You may obtain a copy of the License at: -;* opensource.org/licenses/BSD-3-Clause -;* -;******************************************************************************* -; -; -; The modules in this file are included in the libraries, and may be replaced -; by any user-defined modules that define the PUBLIC symbol _program_start or -; a user defined start symbol. -; To override the cstartup defined in the library, simply add your modified -; version to the workbench project. -; -; The vector table is normally located at address 0. -; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. -; The name "__vector_table" has special meaning for C-SPY: -; it is where the SP start value is found, and the NVIC vector -; table register (VTOR) is initialized to this address if != 0. -; -; Cortex-M version -; - - MODULE ?cstartup - - ;; Forward declaration of sections. - SECTION CSTACK:DATA:NOROOT(3) - - SECTION .intvec:CODE:NOROOT(2) - - EXTERN __iar_program_start - EXTERN SystemInit - PUBLIC __vector_table - - DATA -__vector_table - DCD sfe(CSTACK) - DCD Reset_Handler ; Reset Handler - - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - - ; External Interrupts - DCD WWDG_IRQHandler ; Window Watchdog - DCD 0 ; Reserved - DCD RTC_IRQHandler ; RTC through EXTI Line - DCD FLASH_IRQHandler ; FLASH - DCD RCC_IRQHandler ; RCC - DCD EXTI0_1_IRQHandler ; EXTI Line 0 and 1 - DCD EXTI2_3_IRQHandler ; EXTI Line 2 and 3 - DCD EXTI4_15_IRQHandler ; EXTI Line 4 to 15 - DCD 0 ; Reserved - DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 - DCD DMA1_Channel2_3_IRQHandler ; DMA1 Channel 2 and Channel 3 - DCD DMA1_Channel4_5_IRQHandler ; DMA1 Channel 4 and Channel 5 - DCD ADC1_IRQHandler ; ADC1 - DCD TIM1_BRK_UP_TRG_COM_IRQHandler ; TIM1 Break, Update, Trigger and Commutation - DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare - DCD 0 ; Reserved - DCD TIM3_IRQHandler ; TIM3 - DCD TIM6_IRQHandler ; TIM6 - DCD 0 ; Reserved - DCD TIM14_IRQHandler ; TIM14 - DCD TIM15_IRQHandler ; TIM15 - DCD TIM16_IRQHandler ; TIM16 - DCD TIM17_IRQHandler ; TIM17 - DCD I2C1_IRQHandler ; I2C1 - DCD I2C2_IRQHandler ; I2C2 - DCD SPI1_IRQHandler ; SPI1 - DCD SPI2_IRQHandler ; SPI2 - DCD USART1_IRQHandler ; USART1 - DCD USART2_IRQHandler ; USART2 - - - -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -;; -;; Default interrupt handlers. -;; - THUMB - - PUBWEAK Reset_Handler - SECTION .text:CODE:NOROOT:REORDER(2) -Reset_Handler - LDR R0, =SystemInit - BLX R0 - LDR R0, =__iar_program_start - BX R0 - - PUBWEAK NMI_Handler - SECTION .text:CODE:NOROOT:REORDER(1) -NMI_Handler - B NMI_Handler - - PUBWEAK HardFault_Handler - SECTION .text:CODE:NOROOT:REORDER(1) -HardFault_Handler - B HardFault_Handler - - PUBWEAK SVC_Handler - SECTION .text:CODE:NOROOT:REORDER(1) -SVC_Handler - B SVC_Handler - - PUBWEAK PendSV_Handler - SECTION .text:CODE:NOROOT:REORDER(1) -PendSV_Handler - B PendSV_Handler - - PUBWEAK SysTick_Handler - SECTION .text:CODE:NOROOT:REORDER(1) -SysTick_Handler - B SysTick_Handler - - PUBWEAK WWDG_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -WWDG_IRQHandler - B WWDG_IRQHandler - - PUBWEAK RTC_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -RTC_IRQHandler - B RTC_IRQHandler - - PUBWEAK FLASH_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -FLASH_IRQHandler - B FLASH_IRQHandler - - PUBWEAK RCC_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -RCC_IRQHandler - B RCC_IRQHandler - - PUBWEAK EXTI0_1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -EXTI0_1_IRQHandler - B EXTI0_1_IRQHandler - - PUBWEAK EXTI2_3_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -EXTI2_3_IRQHandler - B EXTI2_3_IRQHandler - - PUBWEAK EXTI4_15_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -EXTI4_15_IRQHandler - B EXTI4_15_IRQHandler - - PUBWEAK DMA1_Channel1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA1_Channel1_IRQHandler - B DMA1_Channel1_IRQHandler - - PUBWEAK DMA1_Channel2_3_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA1_Channel2_3_IRQHandler - B DMA1_Channel2_3_IRQHandler - - PUBWEAK DMA1_Channel4_5_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA1_Channel4_5_IRQHandler - B DMA1_Channel4_5_IRQHandler - - PUBWEAK ADC1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -ADC1_IRQHandler - B ADC1_IRQHandler - - PUBWEAK TIM1_BRK_UP_TRG_COM_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM1_BRK_UP_TRG_COM_IRQHandler - B TIM1_BRK_UP_TRG_COM_IRQHandler - - PUBWEAK TIM1_CC_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM1_CC_IRQHandler - B TIM1_CC_IRQHandler - - PUBWEAK TIM3_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM3_IRQHandler - B TIM3_IRQHandler - - PUBWEAK TIM6_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM6_IRQHandler - B TIM6_IRQHandler - - PUBWEAK TIM14_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM14_IRQHandler - B TIM14_IRQHandler - - PUBWEAK TIM15_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM15_IRQHandler - B TIM15_IRQHandler - - PUBWEAK TIM16_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM16_IRQHandler - B TIM16_IRQHandler - - PUBWEAK TIM17_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM17_IRQHandler - B TIM17_IRQHandler - - PUBWEAK I2C1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -I2C1_IRQHandler - B I2C1_IRQHandler - - PUBWEAK I2C2_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -I2C2_IRQHandler - B I2C2_IRQHandler - - PUBWEAK SPI1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -SPI1_IRQHandler - B SPI1_IRQHandler - - PUBWEAK SPI2_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -SPI2_IRQHandler - B SPI2_IRQHandler - - PUBWEAK USART1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -USART1_IRQHandler - B USART1_IRQHandler - - PUBWEAK USART2_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -USART2_IRQHandler - B USART2_IRQHandler - - - - END -;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE***** diff --git a/bsp/ft32/libraries/FT32F0xx/CMSIS/FT32F0xx/source/iar/startup_ft32f072xb.s b/bsp/ft32/libraries/FT32F0xx/CMSIS/FT32F0xx/source/iar/startup_ft32f072xb.s deleted file mode 100644 index 9cfc37da7a9..00000000000 --- a/bsp/ft32/libraries/FT32F0xx/CMSIS/FT32F0xx/source/iar/startup_ft32f072xb.s +++ /dev/null @@ -1,308 +0,0 @@ -;******************************************************************************* -;* File Name : startup_stm32f072xb.s -;* Author : MCD Application Team -;* Description : STM32F072x8/STM32F072xB devices vector table for EWARM toolchain. -;* This module performs: -;* - Set the initial SP -;* - Set the initial PC == __iar_program_start, -;* - Set the vector table entries with the exceptions ISR -;* address, -;* - Branches to main in the C library (which eventually -;* calls main()). -;* After Reset the Cortex-M0 processor is in Thread mode, -;* priority is Privileged, and the Stack is set to Main. -;******************************************************************************* -;* @attention -;* -;*

© Copyright (c) 2016 STMicroelectronics. -;* All rights reserved.

-;* -;* This software component is licensed by ST under BSD 3-Clause license, -;* the "License"; You may not use this file except in compliance with the -;* License. You may obtain a copy of the License at: -;* opensource.org/licenses/BSD-3-Clause -;* -;******************************************************************************* -; -; -; The modules in this file are included in the libraries, and may be replaced -; by any user-defined modules that define the PUBLIC symbol _program_start or -; a user defined start symbol. -; To override the cstartup defined in the library, simply add your modified -; version to the workbench project. -; -; The vector table is normally located at address 0. -; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. -; The name "__vector_table" has special meaning for C-SPY: -; it is where the SP start value is found, and the NVIC vector -; table register (VTOR) is initialized to this address if != 0. -; -; Cortex-M version -; - - MODULE ?cstartup - - ;; Forward declaration of sections. - SECTION CSTACK:DATA:NOROOT(3) - - SECTION .intvec:CODE:NOROOT(2) - - EXTERN __iar_program_start - EXTERN SystemInit - PUBLIC __vector_table - - DATA -__vector_table - DCD sfe(CSTACK) - DCD Reset_Handler ; Reset Handler - - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - - ; External Interrupts - DCD WWDG_IRQHandler ; Window Watchdog - DCD PVD_VDDIO2_IRQHandler ; PVD and VDDIO2 through EXTI Line detect - DCD RTC_IRQHandler ; RTC through EXTI Line - DCD FLASH_IRQHandler ; FLASH - DCD RCC_CRS_IRQHandler ; RCC and CRS - DCD EXTI0_1_IRQHandler ; EXTI Line 0 and 1 - DCD EXTI2_3_IRQHandler ; EXTI Line 2 and 3 - DCD EXTI4_15_IRQHandler ; EXTI Line 4 to 15 - DCD TSC_IRQHandler ; TSC - DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 - DCD DMA1_Channel2_3_IRQHandler ; DMA1 Channel 2 and Channel 3 - DCD DMA1_Channel4_5_6_7_IRQHandler ; DMA1 Channel 4 to Channel 7 - DCD ADC1_COMP_IRQHandler ; ADC1, COMP1 and COMP2 - DCD TIM1_BRK_UP_TRG_COM_IRQHandler ; TIM1 Break, Update, Trigger and Commutation - DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare - DCD TIM2_IRQHandler ; TIM2 - DCD TIM3_IRQHandler ; TIM3 - DCD TIM6_DAC_IRQHandler ; TIM6 and DAC - DCD TIM7_IRQHandler ; TIM7 - DCD TIM14_IRQHandler ; TIM14 - DCD TIM15_IRQHandler ; TIM15 - DCD TIM16_IRQHandler ; TIM16 - DCD TIM17_IRQHandler ; TIM17 - DCD I2C1_IRQHandler ; I2C1 - DCD I2C2_IRQHandler ; I2C2 - DCD SPI1_IRQHandler ; SPI1 - DCD SPI2_IRQHandler ; SPI2 - DCD USART1_IRQHandler ; USART1 - DCD USART2_IRQHandler ; USART2 - DCD USART3_4_IRQHandler ; USART3 and USART4 - DCD CEC_CAN_IRQHandler ; CEC and CAN - DCD USB_IRQHandler ; USB - -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -;; -;; Default interrupt handlers. -;; - THUMB - - PUBWEAK Reset_Handler - SECTION .text:CODE:NOROOT:REORDER(2) -Reset_Handler - LDR R0, =SystemInit - BLX R0 - LDR R0, =__iar_program_start - BX R0 - - PUBWEAK NMI_Handler - SECTION .text:CODE:NOROOT:REORDER(1) -NMI_Handler - B NMI_Handler - - PUBWEAK HardFault_Handler - SECTION .text:CODE:NOROOT:REORDER(1) -HardFault_Handler - B HardFault_Handler - - PUBWEAK SVC_Handler - SECTION .text:CODE:NOROOT:REORDER(1) -SVC_Handler - B SVC_Handler - - PUBWEAK PendSV_Handler - SECTION .text:CODE:NOROOT:REORDER(1) -PendSV_Handler - B PendSV_Handler - - PUBWEAK SysTick_Handler - SECTION .text:CODE:NOROOT:REORDER(1) -SysTick_Handler - B SysTick_Handler - - PUBWEAK WWDG_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -WWDG_IRQHandler - B WWDG_IRQHandler - - PUBWEAK PVD_VDDIO2_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -PVD_VDDIO2_IRQHandler - B PVD_VDDIO2_IRQHandler - - PUBWEAK RTC_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -RTC_IRQHandler - B RTC_IRQHandler - - PUBWEAK FLASH_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -FLASH_IRQHandler - B FLASH_IRQHandler - - PUBWEAK RCC_CRS_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -RCC_CRS_IRQHandler - B RCC_CRS_IRQHandler - - PUBWEAK EXTI0_1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -EXTI0_1_IRQHandler - B EXTI0_1_IRQHandler - - PUBWEAK EXTI2_3_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -EXTI2_3_IRQHandler - B EXTI2_3_IRQHandler - - PUBWEAK EXTI4_15_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -EXTI4_15_IRQHandler - B EXTI4_15_IRQHandler - - PUBWEAK TSC_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TSC_IRQHandler - B TSC_IRQHandler - - PUBWEAK DMA1_Channel1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA1_Channel1_IRQHandler - B DMA1_Channel1_IRQHandler - - PUBWEAK DMA1_Channel2_3_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA1_Channel2_3_IRQHandler - B DMA1_Channel2_3_IRQHandler - - PUBWEAK DMA1_Channel4_5_6_7_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA1_Channel4_5_6_7_IRQHandler - B DMA1_Channel4_5_6_7_IRQHandler - - PUBWEAK ADC1_COMP_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -ADC1_COMP_IRQHandler - B ADC1_COMP_IRQHandler - - PUBWEAK TIM1_BRK_UP_TRG_COM_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM1_BRK_UP_TRG_COM_IRQHandler - B TIM1_BRK_UP_TRG_COM_IRQHandler - - PUBWEAK TIM1_CC_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM1_CC_IRQHandler - B TIM1_CC_IRQHandler - - PUBWEAK TIM2_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM2_IRQHandler - B TIM2_IRQHandler - - PUBWEAK TIM3_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM3_IRQHandler - B TIM3_IRQHandler - - PUBWEAK TIM6_DAC_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM6_DAC_IRQHandler - B TIM6_DAC_IRQHandler - - PUBWEAK TIM7_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM7_IRQHandler - B TIM7_IRQHandler - - PUBWEAK TIM14_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM14_IRQHandler - B TIM14_IRQHandler - - PUBWEAK TIM15_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM15_IRQHandler - B TIM15_IRQHandler - - PUBWEAK TIM16_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM16_IRQHandler - B TIM16_IRQHandler - - PUBWEAK TIM17_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM17_IRQHandler - B TIM17_IRQHandler - - PUBWEAK I2C1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -I2C1_IRQHandler - B I2C1_IRQHandler - - PUBWEAK I2C2_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -I2C2_IRQHandler - B I2C2_IRQHandler - - PUBWEAK SPI1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -SPI1_IRQHandler - B SPI1_IRQHandler - - PUBWEAK SPI2_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -SPI2_IRQHandler - B SPI2_IRQHandler - - PUBWEAK USART1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -USART1_IRQHandler - B USART1_IRQHandler - - PUBWEAK USART2_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -USART2_IRQHandler - B USART2_IRQHandler - - PUBWEAK USART3_4_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -USART3_4_IRQHandler - B USART3_4_IRQHandler - - PUBWEAK CEC_CAN_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -CEC_CAN_IRQHandler - B CEC_CAN_IRQHandler - - PUBWEAK USB_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -USB_IRQHandler - B USB_IRQHandler - - END -;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE***** diff --git a/bsp/ft32/libraries/FT32F0xx/CMSIS/FT32F0xx/source/system_ft32f0xx.c b/bsp/ft32/libraries/FT32F0xx/CMSIS/FT32F0xx/source/system_ft32f0xx.c deleted file mode 100644 index d4bf01a2958..00000000000 --- a/bsp/ft32/libraries/FT32F0xx/CMSIS/FT32F0xx/source/system_ft32f0xx.c +++ /dev/null @@ -1,755 +0,0 @@ -/** - ****************************************************************************** - * @file system_ft32f0xx.h - * @author FMD AE - * @brief CMSIS FT32F0xx Device Peripheral Access Layer Header File. - * @version V1.0.0 - * @data 2021-07-01 - ****************************************************************************** - */ - -/** @addtogroup CMSIS - * @{ - */ - -/** @addtogroup FT32f0xx_system - * @{ - */ - -/** @addtogroup FT32f0xx_System_Private_Includes - * @{ - */ - -#include "ft32f0xx.h" - -/** - * @} - */ - -/** @addtogroup FT32f0xx_System_Private_TypesDefinitions - * @{ - */ - -/** - * @} - */ - -/** @addtogroup FT32F0xx_System_Private_Defines - * @{ - */ - -// #define SYSCLK_FREQ_HSE HSE_VALUE -// #define SYSCLK_FREQ_24MHz 24000000 -// #define SYSCLK_FREQ_36MHz 36000000 -// #define SYSCLK_FREQ_48MHz 48000000 -// #define SYSCLK_FREQ_56MHz 56000000 - #define SYSCLK_FREQ_72MHz 72000000 -// #define SYSCLK_FREQ_96MHz 96000000 -/** - * @} - */ - -/** @addtogroup FT32f0xx_System_Private_Macros - * @{ - */ - -/** - * @} - */ - -/** @addtogroup FT32f0xx_System_Private_Variables - * @{ - */ -/******************************************************************************* -* Clock Definitions -*******************************************************************************/ -#ifdef SYSCLK_FREQ_HSE - uint32_t SystemCoreClock = SYSCLK_FREQ_HSE; /*!< System Clock Frequency (Core Clock) */ -#elif defined SYSCLK_FREQ_24MHz - uint32_t SystemCoreClock = SYSCLK_FREQ_24MHz; /*!< System Clock Frequency (Core Clock) */ -#elif defined SYSCLK_FREQ_36MHz - uint32_t SystemCoreClock = SYSCLK_FREQ_36MHz; /*!< System Clock Frequency (Core Clock) */ -#elif defined SYSCLK_FREQ_48MHz - uint32_t SystemCoreClock = SYSCLK_FREQ_48MHz; /*!< System Clock Frequency (Core Clock) */ -#elif defined SYSCLK_FREQ_56MHz - uint32_t SystemCoreClock = SYSCLK_FREQ_56MHz; /*!< System Clock Frequency (Core Clock) */ -#elif defined SYSCLK_FREQ_72MHz - uint32_t SystemCoreClock = SYSCLK_FREQ_72MHz; /*!< System Clock Frequency (Core Clock) */ -#elif defined SYSCLK_FREQ_96MHz -#ifdef FT32F072xB - uint32_t SystemCoreClock = SYSCLK_FREQ_96MHz; /*!< System Clock Frequency (Core Clock) */ -#endif -#else /*!< HSI Selected as System Clock source */ - uint32_t SystemCoreClock = HSI_VALUE; /*!< System Clock Frequency (Core Clock) */ -#endif -__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; - -/** - * @} - */ - -/** @addtogroup FT32f0xx_System_Private_FunctionPrototypes - * @{ - */ - -static void SetSysClock(void); - -#ifdef SYSCLK_FREQ_HSE - static void SetSysClockToHSE(void); -#elif defined SYSCLK_FREQ_24MHz - static void SetSysClockTo24(void); -#elif defined SYSCLK_FREQ_36MHz - static void SetSysClockTo36(void); -#elif defined SYSCLK_FREQ_48MHz - static void SetSysClockTo48(void); -#elif defined SYSCLK_FREQ_56MHz - static void SetSysClockTo56(void); -#elif defined SYSCLK_FREQ_72MHz - static void SetSysClockTo72(void); -#elif defined SYSCLK_FREQ_96MHz - static void SetSysClockTo96(void); -#endif -/** - * @} - */ - -/** @addtogroup FT32f0xx_System_Private_Functions - * @{ - */ - -/** - * @brief Setup the microcontroller system. - * Initialize the Embedded Flash Interface, the PLL and update the - * SystemCoreClock variable. - * @param None - * @retval None - */ -void SystemInit (void) -{ - /* Set HSION bit */ - RCC->CR |= (uint32_t)0x00000001; - - /* Reset SW[1:0], HPRE[3:0], PPRE[2:0], ADCPRE and MCOSEL[2:0] bits */ - RCC->CFGR &= (uint32_t)0xF8FFB80C; - - /* Reset HSEON, CSSON and PLLON bits */ - RCC->CR &= (uint32_t)0xFEF6FFFF; - - /* Reset HSEBYP bit */ - RCC->CR &= (uint32_t)0xFFFBFFFF; - - /* Reset PLLSRC, PLLXTPRE and PLLMUL[3:0] bits */ - RCC->CFGR &= (uint32_t)0xFFC0FFFF; - - /* Reset PREDIV1[3:0] bits */ - RCC->CFGR2 &= (uint32_t)0xFFFFFFF0; - - /* Reset USARTSW[1:0], I2CSW, CECSW and ADCSW bits */ - RCC->CFGR3 &= (uint32_t)0xFFFFFEAC; - - /* Reset HSI14 bit */ - RCC->CR2 &= (uint32_t)0xFFFFFFFE; - - /* Disable all interrupts */ - RCC->CIR = 0x00000000; - - /* Configure the System clock frequency, AHB/APBx prescalers and Flash settings */ - SetSysClock(); -} - -/** - * @brief Update SystemCoreClock according to Clock Register Values - * The SystemCoreClock variable contains the core clock (HCLK), it can - * be used by the user application to setup the SysTick timer or configure - * other parameters. - * - * @note Each time the core clock (HCLK) changes, this function must be called - * to update SystemCoreClock variable value. Otherwise, any configuration - * based on this variable will be incorrect. - * - * @note - The system frequency computed by this function is not the real - * frequency in the chip. It is calculated based on the predefined - * constant and the selected clock source: - * - * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) - * - * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) - * - * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) - * or HSI_VALUE(*) multiplied/divided by the PLL factors. - * - * (*) HSI_VALUE is a constant defined in FT32f0xx.h file (default value - * 8 MHz) but the real value may vary depending on the variations - * in voltage and temperature. - * - * (**) HSE_VALUE is a constant defined in FT32f0xx.h file (default value - * 8 MHz), user has to ensure that HSE_VALUE is same as the real - * frequency of the crystal used. Otherwise, this function may - * have wrong result. - * - * - The result of this function could be not correct when using fractional - * value for HSE crystal. - * @param None - * @retval None - */ -void SystemCoreClockUpdate (void) -{ - uint32_t tmp = 0, pllmull = 0, pllsource = 0, prediv1factor = 0; - - /* Get SYSCLK source -------------------------------------------------------*/ - tmp = RCC->CFGR & RCC_CFGR_SWS; - - switch (tmp) - { - case 0x00: /* HSI used as system clock */ - SystemCoreClock = HSI_VALUE; - break; - case 0x04: /* HSE used as system clock */ - SystemCoreClock = HSE_VALUE; - break; - case 0x08: /* PLL used as system clock */ - /* Get PLL clock source and multiplication factor ----------------------*/ - pllmull = RCC->CFGR & RCC_CFGR_PLLMULL; - pllsource = RCC->CFGR & RCC_CFGR_PLLSRC; - pllmull = ( pllmull >> 18) + 2; - - if (pllsource == 0x00) - { - /* HSI oscillator clock divided by 2 selected as PLL clock entry */ - SystemCoreClock = (HSI_VALUE >> 1) * pllmull; - } - else - { - prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1; - /* HSE oscillator clock selected as PREDIV1 clock entry */ - SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; - } - break; - default: /* HSI used as system clock */ - SystemCoreClock = HSI_VALUE; - break; - } - /* Compute HCLK clock frequency ----------------*/ - /* Get HCLK prescaler */ - tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; - /* HCLK clock frequency */ - SystemCoreClock >>= tmp; -} - - - -/** - * @brief Configures the System clock frequency, HCLK, PCLK prescalers. - * @param None - * @retval None - */ -static void SetSysClock(void) -{ -#ifdef SYSCLK_FREQ_HSE - SetSysClockToHSE(); -#elif defined SYSCLK_FREQ_24MHz - SetSysClockTo24(); -#elif defined SYSCLK_FREQ_36MHz - SetSysClockTo36(); -#elif defined SYSCLK_FREQ_48MHz - SetSysClockTo48(); -#elif defined SYSCLK_FREQ_56MHz - SetSysClockTo56(); -#elif defined SYSCLK_FREQ_72MHz - SetSysClockTo72(); -#elif defined SYSCLK_FREQ_96MHz -#ifdef FT32F072xB - SetSysClockTo96(); -#endif -#endif - - /* If none of the define above is enabled, the HSI is used as System clock - source (default after reset) */ -} - -#ifdef SYSCLK_FREQ_HSE -/** - * @brief Selects HSE as System clock source and configure HCLK, PCLK - * prescalers. - * @note This function should be used only after reset. - * @param None - * @retval None - */ -static void SetSysClockToHSE(void) -{ - __IO uint32_t StartUpCounter = 0, HSEStatus = 0; - - /* SYSCLK, HCLK, PCLK configuration ----------------------------------------*/ - /* Enable HSE */ - RCC->CR |= ((uint32_t)RCC_CR_HSEON); - - /* Wait till HSE is ready and if Time out is reached exit */ - do - { - HSEStatus = RCC->CR & RCC_CR_HSERDY; - StartUpCounter++; - } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); - - if ((RCC->CR & RCC_CR_HSERDY) != RESET) - { - HSEStatus = (uint32_t)0x01; - } - else - { - HSEStatus = (uint32_t)0x00; - } - - if (HSEStatus == (uint32_t)0x01) - { - /* Enable Prefetch Buffer and set Flash Latency */ - FLASH->ACR = FLASH_ACR_PRFTBE | ((uint32_t)0x00000000); - - /* HCLK = SYSCLK */ - RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; - - /* PCLK = HCLK */ - RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE_DIV1; - - /* Select PLL as system clock source */ - RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); - RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE; - - /* Wait till PLL is used as system clock source */ - while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)RCC_CFGR_SWS_HSE) - { - } - } - else - { /* If HSE fails to start-up, the application will have wrong clock - configuration. User can add here some code to deal with this error */ - } -} -#elif defined SYSCLK_FREQ_24MHz -/** - * @brief Sets System clock frequency to 24MHz and configure HCLK, PCLK - * prescalers. - * @note This function should be used only after reset. - * @param None - * @retval None - */ -static void SetSysClockTo24(void) -{ - __IO uint32_t StartUpCounter = 0, HSIStatus = 0; - - /* SYSCLK, HCLK, PCLK configuration ----------------------------------------*/ - /* Enable HSE */ - RCC->CR |= ((uint32_t)RCC_CR_HSION); - - /* Wait till HSE is ready and if Time out is reached exit */ - do - { - HSIStatus = RCC->CR & RCC_CR_HSIRDY; - StartUpCounter++; - } while((HSIStatus == 0) && (StartUpCounter != HSI_STARTUP_TIMEOUT)); - - if ((RCC->CR & RCC_CR_HSIRDY) != RESET) - { - HSIStatus = (uint32_t)0x01; - } - else - { - HSIStatus = (uint32_t)0x00; - } - - if (HSIStatus == (uint32_t)0x01) - { - /* Enable Prefetch Buffer and set Flash Latency */ - FLASH->ACR = FLASH_ACR_PRFTBE | ((uint32_t)0x00000000); - - /* HCLK = SYSCLK */ - RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; - - /* PCLK = HCLK */ - RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE_DIV1; - - /* PLL configuration */ - RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL)); - RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSI_PREDIV | RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLMULL3); - - /* Enable PLL */ - RCC->CR |= RCC_CR_PLLON; - - /* Wait till PLL is ready */ - while((RCC->CR & RCC_CR_PLLRDY) == 0) - { - } - - /* Select PLL as system clock source */ - RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); - RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; - - /* Wait till PLL is used as system clock source */ - while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)RCC_CFGR_SWS_PLL) - { - } - } - else - { /* If HSE fails to start-up, the application will have wrong clock - configuration. User can add here some code to deal with this error */ - } -} -#elif defined SYSCLK_FREQ_36MHz -/** - * @brief Sets System clock frequency to 36MHz and configure HCLK, PCLK - * prescalers. - * @note This function should be used only after reset. - * @param None - * @retval None - */ -static void SetSysClockTo36(void) -{ - __IO uint32_t StartUpCounter = 0, HSIStatus = 0; - - /* SYSCLK, HCLK, PCLK configuration ----------------------------------------*/ - /* Enable HSE */ - RCC->CR |= ((uint32_t)RCC_CR_HSION); - - /* Wait till HSE is ready and if Time out is reached exit */ - do - { - HSIStatus = RCC->CR & RCC_CR_HSIRDY; - StartUpCounter++; - } while((HSIStatus == 0) && (StartUpCounter != HSI_STARTUP_TIMEOUT)); - - if ((RCC->CR & RCC_CR_HSIRDY) != RESET) - { - HSIStatus = (uint32_t)0x01; - } - else - { - HSIStatus = (uint32_t)0x00; - } - - if (HSIStatus == (uint32_t)0x01) - { - /* Enable Prefetch Buffer and set Flash Latency */ - FLASH->ACR = FLASH_ACR_PRFTBE | ((uint32_t)0x00000001); - - /* HCLK = SYSCLK */ - RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; - - /* PCLK = HCLK */ - RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE_DIV1; - - /* PLL configuration */ - RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL)); - RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSI_PREDIV | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL9); - - /* Enable PLL */ - RCC->CR |= RCC_CR_PLLON; - - /* Wait till PLL is ready */ - while((RCC->CR & RCC_CR_PLLRDY) == 0) - { - } - - /* Select PLL as system clock source */ - RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); - RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; - - /* Wait till PLL is used as system clock source */ - while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)RCC_CFGR_SWS_PLL) - { - } - } - else - { /* If HSE fails to start-up, the application will have wrong clock - configuration. User can add here some code to deal with this error */ - } -} -#elif defined SYSCLK_FREQ_48MHz -/** - * @brief Sets System clock frequency to 48MHz and configure HCLK, PCLK - * prescalers. - * @note This function should be used only after reset. - * @param None - * @retval None - */ -static void SetSysClockTo48(void) -{ - __IO uint32_t StartUpCounter = 0, HSIStatus = 0; - - /* SYSCLK, HCLK, PCLK configuration ----------------------------------------*/ - /* Enable HSE */ - RCC->CR |= ((uint32_t)RCC_CR_HSION); - - /* Wait till HSE is ready and if Time out is reached exit */ - do - { - HSIStatus = RCC->CR & RCC_CR_HSIRDY; - StartUpCounter++; - } while((HSIStatus == 0) && (StartUpCounter != HSI_STARTUP_TIMEOUT)); - - if ((RCC->CR & RCC_CR_HSIRDY) != RESET) - { - HSIStatus = (uint32_t)0x01; - } - else - { - HSIStatus = (uint32_t)0x00; - } - - if (HSIStatus == (uint32_t)0x01) - { - /* Enable Prefetch Buffer and set Flash Latency */ - FLASH->ACR = FLASH_ACR_PRFTBE | ((uint32_t)0x00000001); - - /* HCLK = SYSCLK */ - RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; - - /* PCLK = HCLK */ - RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE_DIV1; - - /* PLL configuration */ - RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL)); - RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSI_PREDIV | RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLMULL6); - - /* Enable PLL */ - RCC->CR |= RCC_CR_PLLON; - - /* Wait till PLL is ready */ - while((RCC->CR & RCC_CR_PLLRDY) == 0) - { - } - - /* Select PLL as system clock source */ - RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); - RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; - - /* Wait till PLL is used as system clock source */ - while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)RCC_CFGR_SWS_PLL) - { - } - } - else - { /* If HSE fails to start-up, the application will have wrong clock - configuration. User can add here some code to deal with this error */ - } -} -#elif defined SYSCLK_FREQ_56MHz -/** - * @brief Sets System clock frequency to 56MHz and configure HCLK, PCLK - * prescalers. - * @note This function should be used only after reset. - * @param None - * @retval None - */ -static void SetSysClockTo56(void) -{ - __IO uint32_t StartUpCounter = 0, HSIStatus = 0; - - /* SYSCLK, HCLK, PCLK configuration ----------------------------------------*/ - /* Enable HSE */ - RCC->CR |= ((uint32_t)RCC_CR_HSION); - - /* Wait till HSE is ready and if Time out is reached exit */ - do - { - HSIStatus = RCC->CR & RCC_CR_HSIRDY; - StartUpCounter++; - } while((HSIStatus == 0) && (StartUpCounter != HSI_STARTUP_TIMEOUT)); - - if ((RCC->CR & RCC_CR_HSIRDY) != RESET) - { - HSIStatus = (uint32_t)0x01; - } - else - { - HSIStatus = (uint32_t)0x00; - } - - if (HSIStatus == (uint32_t)0x01) - { - /* Enable Prefetch Buffer and set Flash Latency */ - FLASH->ACR = FLASH_ACR_PRFTBE | ((uint32_t)0x00000002); - - /* HCLK = SYSCLK */ - RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; - - /* PCLK = HCLK */ - RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE_DIV1; - - /* PLL configuration */ - RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL)); - RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSI_PREDIV | RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLMULL7); - - /* Enable PLL */ - RCC->CR |= RCC_CR_PLLON; - - /* Wait till PLL is ready */ - while((RCC->CR & RCC_CR_PLLRDY) == 0) - { - } - - /* Select PLL as system clock source */ - RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); - RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; - - /* Wait till PLL is used as system clock source */ - while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)RCC_CFGR_SWS_PLL) - { - } - } - else - { /* If HSE fails to start-up, the application will have wrong clock - configuration. User can add here some code to deal with this error */ - } -} -#elif defined SYSCLK_FREQ_72MHz -/** - * @brief Sets System clock frequency to 72MHz and configure HCLK, PCLK - * prescalers. - * @note This function should be used only after reset. - * @param None - * @retval None - */ -static void SetSysClockTo72(void) -{ - __IO uint32_t StartUpCounter = 0, HSIStatus = 0; - - /* SYSCLK, HCLK, PCLK configuration ----------------------------------------*/ - /* Enable HSE */ - RCC->CR |= ((uint32_t)RCC_CR_HSION); - - /* Wait till HSE is ready and if Time out is reached exit */ - do - { - HSIStatus = RCC->CR & RCC_CR_HSIRDY; - StartUpCounter++; - } while((HSIStatus == 0) && (StartUpCounter != HSI_STARTUP_TIMEOUT)); - - if ((RCC->CR & RCC_CR_HSIRDY) != RESET) - { - HSIStatus = (uint32_t)0x01; - } - else - { - HSIStatus = (uint32_t)0x00; - } - - if (HSIStatus == (uint32_t)0x01) - { - /* Enable Prefetch Buffer and set Flash Latency */ - FLASH->ACR = FLASH_ACR_PRFTBE | ((uint32_t)0x00000002); - - /* HCLK = SYSCLK */ - RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; - - /* PCLK = HCLK */ - RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE_DIV1; - - /* PLL configuration */ - RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL)); - RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSI_PREDIV | RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLMULL9); - - /* Enable PLL */ - RCC->CR |= RCC_CR_PLLON; - - /* Wait till PLL is ready */ - while((RCC->CR & RCC_CR_PLLRDY) == 0) - { - } - - /* Select PLL as system clock source */ - RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); - RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; - - /* Wait till PLL is used as system clock source */ - while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)RCC_CFGR_SWS_PLL) - { - } - } - else - { /* If HSE fails to start-up, the application will have wrong clock - configuration. User can add here some code to deal with this error */ - } -} -#elif defined SYSCLK_FREQ_96MHz -/** - * @brief Sets System clock frequency to 96MHz and configure HCLK, PCLK - * prescalers. - * @note This function should be used only after reset. - * @param None - * @retval None - */ -static void SetSysClockTo96(void) -{ - __IO uint32_t StartUpCounter = 0, HSIStatus = 0; - - /* SYSCLK, HCLK, PCLK configuration ----------------------------------------*/ - /* Enable HSE */ - RCC->CR |= ((uint32_t)RCC_CR_HSION); - - /* Wait till HSE is ready and if Time out is reached exit */ - do - { - HSIStatus = RCC->CR & RCC_CR_HSIRDY; - StartUpCounter++; - } while((HSIStatus == 0) && (StartUpCounter != HSI_STARTUP_TIMEOUT)); - - if ((RCC->CR & RCC_CR_HSIRDY) != RESET) - { - HSIStatus = (uint32_t)0x01; - } - else - { - HSIStatus = (uint32_t)0x00; - } - - if (HSIStatus == (uint32_t)0x01) - { - /* Enable Prefetch Buffer and set Flash Latency */ - FLASH->ACR = FLASH_ACR_PRFTBE | ((uint32_t)0x00000002); - - /* HCLK = SYSCLK */ - RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; - - /* PCLK = HCLK */ - RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE_DIV1; - - /* PLL configuration */ - RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL)); - RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSI_PREDIV | RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLMULL12); - - /* Enable PLL */ - RCC->CR |= RCC_CR_PLLON; - - /* Wait till PLL is ready */ - while((RCC->CR & RCC_CR_PLLRDY) == 0) - { - } - - /* Select PLL as system clock source */ - RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); - RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; - - /* Wait till PLL is used as system clock source */ - while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)RCC_CFGR_SWS_PLL) - { - } - } - else - { /* If HSE fails to start-up, the application will have wrong clock - configuration. User can add here some code to deal with this error */ - } -} -#endif - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT FMD *****END OF FILE****/ diff --git a/bsp/ft32/libraries/FT32F0xx/FT32F0xx_Driver/Inc/ft32f0xx_adc.h b/bsp/ft32/libraries/FT32F0xx/FT32F0xx_Driver/Inc/ft32f0xx_adc.h deleted file mode 100644 index 536965ee98a..00000000000 --- a/bsp/ft32/libraries/FT32F0xx/FT32F0xx_Driver/Inc/ft32f0xx_adc.h +++ /dev/null @@ -1,592 +0,0 @@ -/** - ****************************************************************************** - * @file ft32f0xx_adc.h - * @author FMD AE - * @brief This file contains all the functions prototypes for the ADC firmware - * library - * @version V1.0.0 - * @data 2021-07-01 - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __FT32F0XX_ADC_H -#define __FT32F0XX_ADC_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "ft32f0xx.h" - -/** @addtogroup ADC - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ - -/** - * @brief ADC Init structure definition - */ - -typedef struct -{ - uint32_t ADC_Resolution; /*!< Selects the resolution of the conversion. - This parameter can be a value of @ref ADC_Resolution */ - - FunctionalState ADC_ContinuousConvMode; /*!< Specifies whether the conversion is performed in - Continuous or Single mode. - This parameter can be set to ENABLE or DISABLE. */ - - uint32_t ADC_ExternalTrigConvEdge; /*!< Selects the external trigger Edge and enables the - trigger of a regular group. This parameter can be a value - of @ref ADC_external_trigger_edge_conversion */ - - uint32_t ADC_ExternalTrigConv; /*!< Defines the external trigger used to start the analog - to digital conversion of regular channels. This parameter - can be a value of @ref ADC_external_trigger_sources_for_channels_conversion */ - - uint32_t ADC_DataAlign; /*!< Specifies whether the ADC data alignment is left or right. - This parameter can be a value of @ref ADC_data_align */ - - uint32_t ADC_ScanDirection; /*!< Specifies in which direction the channels will be scanned - in the sequence. - This parameter can be a value of @ref ADC_Scan_Direction */ -}ADC_InitTypeDef; - - -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup ADC_Exported_Constants - * @{ - */ -#define IS_ADC_ALL_PERIPH(PERIPH) ((PERIPH) == ADC1) - -/** @defgroup ADC_JitterOff - * @{ - */ -/* These defines are obsolete and maintained for legacy purpose only. They are replaced by the ADC_ClockMode */ -#define ADC_JitterOff_PCLKDiv2 ADC_CFGR2_JITOFFDIV2 -#define ADC_JitterOff_PCLKDiv4 ADC_CFGR2_JITOFFDIV4 - -#define IS_ADC_JITTEROFF(JITTEROFF) (((JITTEROFF) & 0x3FFFFFFF) == (uint32_t)RESET) - -/** - * @} - */ - -/** @defgroup ADC_ClockMode - * @{ - */ -#define ADC_ClockMode_AsynClk ((uint32_t)0x00000000) /*!< ADC Asynchronous clock mode */ -#define ADC_ClockMode_SynClkDiv2 ADC_CFGR2_CKMODE_0 /*!< Synchronous clock mode divided by 2 */ -#define ADC_ClockMode_SynClkDiv4 ADC_CFGR2_CKMODE_1 /*!< Synchronous clock mode divided by 4 */ -#define IS_ADC_CLOCKMODE(CLOCK) (((CLOCK) == ADC_ClockMode_AsynClk) ||\ - ((CLOCK) == ADC_ClockMode_SynClkDiv2) ||\ - ((CLOCK) == ADC_ClockMode_SynClkDiv4)) - -/** - * @} - */ - -/** @defgroup ADC_Resolution - * @{ - */ -#define ADC_Resolution_12b ((uint32_t)0x00000000) -#define ADC_Resolution_10b ADC_CFGR1_RES_0 -#define ADC_Resolution_8b ADC_CFGR1_RES_1 -#define ADC_Resolution_6b ADC_CFGR1_RES - -#define IS_ADC_RESOLUTION(RESOLUTION) (((RESOLUTION) == ADC_Resolution_12b) || \ - ((RESOLUTION) == ADC_Resolution_10b) || \ - ((RESOLUTION) == ADC_Resolution_8b) || \ - ((RESOLUTION) == ADC_Resolution_6b)) - -/** - * @} - */ - -/** @defgroup ADC_external_trigger_edge_conversion - * @{ - */ -#define ADC_ExternalTrigConvEdge_None ((uint32_t)0x00000000) -#define ADC_ExternalTrigConvEdge_Rising ADC_CFGR1_EXTEN_0 -#define ADC_ExternalTrigConvEdge_Falling ADC_CFGR1_EXTEN_1 -#define ADC_ExternalTrigConvEdge_RisingFalling ADC_CFGR1_EXTEN - -#define IS_ADC_EXT_TRIG_EDGE(EDGE) (((EDGE) == ADC_ExternalTrigConvEdge_None) || \ - ((EDGE) == ADC_ExternalTrigConvEdge_Rising) || \ - ((EDGE) == ADC_ExternalTrigConvEdge_Falling) || \ - ((EDGE) == ADC_ExternalTrigConvEdge_RisingFalling)) -/** - * @} - */ - -/** @defgroup ADC_external_trigger_sources_for_channels_conversion - * @{ - */ - -/* TIM1 */ -#define ADC_ExternalTrigConv_T1_TRGO ((uint32_t)0x00000000) -#define ADC_ExternalTrigConv_T1_CC4 ADC_CFGR1_EXTSEL_0 - -/* TIM2 */ -#define ADC_ExternalTrigConv_T2_TRGO ADC_CFGR1_EXTSEL_1 - -/* TIM3 */ -#define ADC_ExternalTrigConv_T3_TRGO ((uint32_t)(ADC_CFGR1_EXTSEL_0 | ADC_CFGR1_EXTSEL_1)) - -/* TIM15 */ -#define ADC_ExternalTrigConv_T15_TRGO ADC_CFGR1_EXTSEL_2 - -#define IS_ADC_EXTERNAL_TRIG_CONV(CONV) (((CONV) == ADC_ExternalTrigConv_T1_TRGO) || \ - ((CONV) == ADC_ExternalTrigConv_T1_CC4) || \ - ((CONV) == ADC_ExternalTrigConv_T2_TRGO) || \ - ((CONV) == ADC_ExternalTrigConv_T3_TRGO) || \ - ((CONV) == ADC_ExternalTrigConv_T15_TRGO)) -/** - * @} - */ - -/** @defgroup ADC_data_align - * @{ - */ - -#define ADC_DataAlign_Right ((uint32_t)0x00000000) -#define ADC_DataAlign_Left ADC_CFGR1_ALIGN - -#define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DataAlign_Right) || \ - ((ALIGN) == ADC_DataAlign_Left)) -/** - * @} - */ - -/** @defgroup ADC_Scan_Direction - * @{ - */ - -#define ADC_ScanDirection_Upward ((uint32_t)0x00000000) -#define ADC_ScanDirection_Backward ADC_CFGR1_SCANDIR - -#define IS_ADC_SCAN_DIRECTION(DIRECTION) (((DIRECTION) == ADC_ScanDirection_Upward) || \ - ((DIRECTION) == ADC_ScanDirection_Backward)) -/** - * @} - */ - -/** @defgroup ADC_DMA_Mode - * @{ - */ - -#define ADC_DMAMode_OneShot ((uint32_t)0x00000000) -#define ADC_DMAMode_Circular ADC_CFGR1_DMACFG - -#define IS_ADC_DMA_MODE(MODE) (((MODE) == ADC_DMAMode_OneShot) || \ - ((MODE) == ADC_DMAMode_Circular)) -/** - * @} - */ - -/** @defgroup ADC_analog_watchdog_selection - * @{ - */ - -#define ADC_AnalogWatchdog_Channel_0 ((uint32_t)0x00000000) -#define ADC_AnalogWatchdog_Channel_1 ((uint32_t)0x04000000) -#define ADC_AnalogWatchdog_Channel_2 ((uint32_t)0x08000000) -#define ADC_AnalogWatchdog_Channel_3 ((uint32_t)0x0C000000) -#define ADC_AnalogWatchdog_Channel_4 ((uint32_t)0x10000000) -#define ADC_AnalogWatchdog_Channel_5 ((uint32_t)0x14000000) -#define ADC_AnalogWatchdog_Channel_6 ((uint32_t)0x18000000) -#define ADC_AnalogWatchdog_Channel_7 ((uint32_t)0x1C000000) -#define ADC_AnalogWatchdog_Channel_8 ((uint32_t)0x20000000) -#define ADC_AnalogWatchdog_Channel_9 ((uint32_t)0x24000000) -#define ADC_AnalogWatchdog_Channel_10 ((uint32_t)0x28000000) -#define ADC_AnalogWatchdog_Channel_11 ((uint32_t)0x2C000000) -#define ADC_AnalogWatchdog_Channel_12 ((uint32_t)0x30000000) -#define ADC_AnalogWatchdog_Channel_13 ((uint32_t)0x34000000) -#define ADC_AnalogWatchdog_Channel_14 ((uint32_t)0x38000000) -#define ADC_AnalogWatchdog_Channel_15 ((uint32_t)0x3C000000) -#define ADC_AnalogWatchdog_Channel_16 ((uint32_t)0x40000000) -#define ADC_AnalogWatchdog_Channel_17 ((uint32_t)0x44000000) -#define ADC_AnalogWatchdog_Channel_18 ((uint32_t)0x48000000) - - -#define IS_ADC_ANALOG_WATCHDOG_CHANNEL(CHANNEL) (((CHANNEL) == ADC_AnalogWatchdog_Channel_0) || \ - ((CHANNEL) == ADC_AnalogWatchdog_Channel_1) || \ - ((CHANNEL) == ADC_AnalogWatchdog_Channel_2) || \ - ((CHANNEL) == ADC_AnalogWatchdog_Channel_3) || \ - ((CHANNEL) == ADC_AnalogWatchdog_Channel_4) || \ - ((CHANNEL) == ADC_AnalogWatchdog_Channel_5) || \ - ((CHANNEL) == ADC_AnalogWatchdog_Channel_6) || \ - ((CHANNEL) == ADC_AnalogWatchdog_Channel_7) || \ - ((CHANNEL) == ADC_AnalogWatchdog_Channel_8) || \ - ((CHANNEL) == ADC_AnalogWatchdog_Channel_9) || \ - ((CHANNEL) == ADC_AnalogWatchdog_Channel_10) || \ - ((CHANNEL) == ADC_AnalogWatchdog_Channel_11) || \ - ((CHANNEL) == ADC_AnalogWatchdog_Channel_12) || \ - ((CHANNEL) == ADC_AnalogWatchdog_Channel_13) || \ - ((CHANNEL) == ADC_AnalogWatchdog_Channel_14) || \ - ((CHANNEL) == ADC_AnalogWatchdog_Channel_15) || \ - ((CHANNEL) == ADC_AnalogWatchdog_Channel_16) || \ - ((CHANNEL) == ADC_AnalogWatchdog_Channel_17) || \ - ((CHANNEL) == ADC_AnalogWatchdog_Channel_18)) -/** - * @} - */ - -/** @defgroup ADC_sampling_times - * @{ - */ - -#define ADC_SampleTime_1_5Cycles ((uint32_t)0x00000000) -#define ADC_SampleTime_7_5Cycles ((uint32_t)0x00000001) -#define ADC_SampleTime_13_5Cycles ((uint32_t)0x00000002) -#define ADC_SampleTime_28_5Cycles ((uint32_t)0x00000003) -#define ADC_SampleTime_41_5Cycles ((uint32_t)0x00000004) -#define ADC_SampleTime_55_5Cycles ((uint32_t)0x00000005) -#define ADC_SampleTime_71_5Cycles ((uint32_t)0x00000006) -#define ADC_SampleTime_239_5Cycles ((uint32_t)0x00000007) - -#define IS_ADC_SAMPLE_TIME(TIME) (((TIME) == ADC_SampleTime_1_5Cycles) || \ - ((TIME) == ADC_SampleTime_7_5Cycles) || \ - ((TIME) == ADC_SampleTime_13_5Cycles) || \ - ((TIME) == ADC_SampleTime_28_5Cycles) || \ - ((TIME) == ADC_SampleTime_41_5Cycles) || \ - ((TIME) == ADC_SampleTime_55_5Cycles) || \ - ((TIME) == ADC_SampleTime_71_5Cycles) || \ - ((TIME) == ADC_SampleTime_239_5Cycles)) -/** - * @} - */ - -/** @defgroup ADC_thresholds - * @{ - */ - -#define IS_ADC_THRESHOLD(THRESHOLD) ((THRESHOLD) <= 0xFFF) - -/** - * @} - */ - -/** @defgroup ADC_channels - * @{ - */ - -#define ADC_Channel_0 ADC_CHSELR_CHSEL0 -#define ADC_Channel_1 ADC_CHSELR_CHSEL1 -#define ADC_Channel_2 ADC_CHSELR_CHSEL2 -#define ADC_Channel_3 ADC_CHSELR_CHSEL3 -#define ADC_Channel_4 ADC_CHSELR_CHSEL4 -#define ADC_Channel_5 ADC_CHSELR_CHSEL5 -#define ADC_Channel_6 ADC_CHSELR_CHSEL6 -#define ADC_Channel_7 ADC_CHSELR_CHSEL7 -#define ADC_Channel_8 ADC_CHSELR_CHSEL8 -#define ADC_Channel_9 ADC_CHSELR_CHSEL9 -#define ADC_Channel_10 ADC_CHSELR_CHSEL10 -#define ADC_Channel_11 ADC_CHSELR_CHSEL11 -#define ADC_Channel_12 ADC_CHSELR_CHSEL12 -#define ADC_Channel_13 ADC_CHSELR_CHSEL13 -#define ADC_Channel_14 ADC_CHSELR_CHSEL14 -#define ADC_Channel_15 ADC_CHSELR_CHSEL15 -#define ADC_Channel_16 ADC_CHSELR_CHSEL16 -#define ADC_Channel_17 ADC_CHSELR_CHSEL17 -#define ADC_Channel_18 ADC_CHSELR_CHSEL18 -#define ADC_Channel_19 ADC_CHSELR_CHSEL19 -#define ADC_Channel_20 ADC_CHSELR_CHSEL20 -#define ADC_Channel_21 ADC_CHSELR_CHSEL21 - -#define ADC_Channel_TempSensor ((uint32_t)ADC_Channel_16) -#define ADC_Channel_Vrefint ((uint32_t)ADC_Channel_17) -#if defined (FT32F072xB) - #define ADC_Channel_OP1 ((uint32_t)ADC_Channel_18) - #define ADC_Channel_OP2 ((uint32_t)ADC_Channel_19) - #define ADC_Channel_IOSH1 ((uint32_t)ADC_Channel_20) - #define ADC_Channel_IOSH2 ((uint32_t)ADC_Channel_21) - - #define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) != (uint32_t)RESET) && (((CHANNEL) & 0xFFC00000) == (uint32_t)RESET)) - -#else - #define ADC_Channel_IOSH ((uint32_t)ADC_Channel_18) - #define ADC_Channel_OP ((uint32_t)ADC_Channel_19) - - #define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) != (uint32_t)RESET) && (((CHANNEL) & 0xFFF00000) == (uint32_t)RESET)) - -#endif - - - -#if defined (FT32F072xB) - /** - * @}ADC_IOSH1_SMPSEL - */ - #define ADC_IOSH1_SMPSEL_PB1 ((uint32_t)0x00000000) - #define ADC_IOSH1_SMPSEL_OP1OUT ((uint32_t)0x00000400) - - #define ADC_IOSH2_SMPSEL_PB0 ((uint32_t)0x00000000) - #define ADC_IOSH2_SMPSEL_OP2OUT ((uint32_t)0x00004000) - - #define IS_ADC_SMPSEL(SEL) ( ((SEL) == ADC_IOSH2_SMPSEL_PB1) || \ - ((SEL) == ADC_IOSH2_SMPSEL_OP1OUT) || \ - ((SEL) == ADC_IOSH1_SMPSEL_OP2OUT) ) - /** - * @}IS_ADC_SMPEN - */ - #define ADC_IOSH1_SMPEN ((uint32_t)0x00000200) - #define ADC_IOSH2_SMPEN ((uint32_t)0x00002000) - - #define IS_ADC_SMPEN(SMPEN) ( ((SMPEN) == ADC_IOSH1_SMPEN) || \ - ((SMPEN) == ADC_IOSH2_SMPEN) ) - /** - * @}IS_ADC_SMPMOD - */ - #define IS_ADC_SMPMOD(SMPMOD) ( ((SMPMOD) == ADC_CR2_IOSH1_SMPMOD) || \ - ((SMPMOD) == ADC_CR2_IOSH2_SMPMOD) ) - - #define ADC_SMP_SOFTWARE_MODE ((uint32_t)0x00000000) - #define ADC_SMP_HARDWARE_MODE ((uint32_t)0x00000001) - - #define IS_ADC_MODE(MODE) ( ((MODE) == ADC_SMP_SOFTWARE_MODE) || \ - ((MODE) == ADC_SMP_HARDWARE_MODE) ) - - /** - * @}IS_ADC_AMPEN - */ - #define ADC_IOSH1_AMPEN ((uint32_t)0x00000100) - #define ADC_IOSH2_AMPEN ((uint32_t)0x00001000) - - #define IS_ADC_AMPEN(AMPEN) ( ((AMPEN) == ADC_IOSH1_AMPEN) || \ - ((AMPEN) == ADC_IOSH2_AMPEN) ) - /** - * @}IS_ADC_EXTDLY - */ - #define IS_ADC_EXTDLY(EXTDLY) ( ((EXTDLY) >=0 ) && ((EXTDLY) <= 0x000003FF)) - - /** - * @}IS_ADC_RTEN - */ - #define IS_ADC_RTEN(RTEN) ( ((RTEN) == ADC_RTENR_RTEN) || \ - ((RTEN) == ADC_RTENR_RTEN_0) || \ - ((RTEN) == ADC_RTENR_RTEN_1) || \ - ((RTEN) == ADC_RTENR_RTEN_2) || \ - ((RTEN) == ADC_RTENR_RTEN_3) || \ - ((RTEN) == ADC_RTENR_RTEN_4) || \ - ((RTEN) == ADC_RTENR_RTEN_5) || \ - ((RTEN) == ADC_RTENR_RTEN_6) || \ - ((RTEN) == ADC_RTENR_RTEN_7) || \ - ((RTEN) == ADC_RTENR_RTEN_8) || \ - ((RTEN) == ADC_RTENR_RTEN_9) || \ - ((RTEN) == ADC_RTENR_RTEN_10) || \ - ((RTEN) == ADC_RTENR_RTEN_11) || \ - ((RTEN) == ADC_RTENR_RTEN_12) || \ - ((RTEN) == ADC_RTENR_RTEN_13) || \ - ((RTEN) == ADC_RTENR_RTEN_14) || \ - ((RTEN) == ADC_RTENR_RTEN_15) || \ - ((RTEN) == ADC_RTENR_RTEN_16) || \ - ((RTEN) == ADC_RTENR_RTEN_17) || \ - ((RTEN) == ADC_RTENR_RTEN_18) ) - - /** - * @}IS_ADC_FTEN - */ - #define IS_ADC_FTEN(FTEN) ( ((FTEN) == ADC_FTENR_FTEN) || \ - ((FTEN) == ADC_FTENR_FTEN_0) || \ - ((FTEN) == ADC_FTENR_FTEN_1) || \ - ((FTEN) == ADC_FTENR_FTEN_2) || \ - ((FTEN) == ADC_FTENR_FTEN_3) || \ - ((FTEN) == ADC_FTENR_FTEN_4) || \ - ((FTEN) == ADC_FTENR_FTEN_5) || \ - ((FTEN) == ADC_FTENR_FTEN_6) || \ - ((FTEN) == ADC_FTENR_FTEN_7) || \ - ((FTEN) == ADC_FTENR_FTEN_8) || \ - ((FTEN) == ADC_FTENR_FTEN_9) || \ - ((FTEN) == ADC_FTENR_FTEN_10) || \ - ((FTEN) == ADC_FTENR_FTEN_11) || \ - ((FTEN) == ADC_FTENR_FTEN_12) || \ - ((FTEN) == ADC_FTENR_FTEN_13) || \ - ((FTEN) == ADC_FTENR_FTEN_14) || \ - ((FTEN) == ADC_FTENR_FTEN_15) || \ - ((FTEN) == ADC_FTENR_FTEN_16) || \ - ((FTEN) == ADC_FTENR_FTEN_17) || \ - ((FTEN) == ADC_FTENR_FTEN_18)) - -#else - /** - * @}IS_ADC_AMPEN - */ - #define ADC_IOSH1_AMPEN ((uint32_t)0x00000100) - #define ADC_IOSH_AMPEN ADC_IOSH1_AMPEN - - #define IS_ADC_AMPEN(AMPEN) ( ((AMPEN) == ADC_IOSH1_AMPEN)) - - /** - * @}IS_ADC_SMPEN - */ - #define ADC_IOSH1_SMPEN ((uint32_t)0x00000200) - #define ADC_IOSH_SMPEN ADC_IOSH1_SMPEN - - #define IS_ADC_SMPEN(SMPEN) ( ((SMPEN) == ADC_IOSH1_SMPEN) ) - -#endif - - -/** - * @} - */ - -/** @defgroup ADC_interrupts_definition - * @{ - */ - -#define ADC_IT_ADRDY ADC_IER_ADRDYIE -#define ADC_IT_EOSMP ADC_IER_EOSMPIE -#define ADC_IT_EOC ADC_IER_EOCIE -#define ADC_IT_EOSEQ ADC_IER_EOSEQIE -#define ADC_IT_OVR ADC_IER_OVRIE -#define ADC_IT_AWD ADC_IER_AWDIE - -#define IS_ADC_CONFIG_IT(IT) (((IT) != (uint32_t)RESET) && (((IT) & 0xFFFFFF60) == (uint32_t)RESET)) - -#define IS_ADC_GET_IT(IT) (((IT) == ADC_IT_ADRDY) || ((IT) == ADC_IT_EOSMP) || \ - ((IT) == ADC_IT_EOC) || ((IT) == ADC_IT_EOSEQ) || \ - ((IT) == ADC_IT_OVR) || ((IT) == ADC_IT_AWD)) - -#define IS_ADC_CLEAR_IT(IT) (((IT) != (uint32_t)RESET) && (((IT) & 0xFFFFFF60) == (uint32_t)RESET)) - -/** - * @} - */ - -/** @defgroup ADC_flags_definition - * @{ - */ - -#define ADC_FLAG_ADRDY ADC_ISR_ADRDY -#define ADC_FLAG_EOSMP ADC_ISR_EOSMP -#define ADC_FLAG_EOC ADC_ISR_EOC -#define ADC_FLAG_EOSEQ ADC_ISR_EOSEQ -#define ADC_FLAG_OVR ADC_ISR_OVR -#define ADC_FLAG_AWD ADC_ISR_AWD - -#define ADC_FLAG_ADEN ((uint32_t)0x01000001) -#define ADC_FLAG_ADDIS ((uint32_t)0x01000002) -#define ADC_FLAG_ADSTART ((uint32_t)0x01000004) -#define ADC_FLAG_ADSTP ((uint32_t)0x01000010) -#define ADC_FLAG_ADCAL ((uint32_t)0x81000000) - -#define IS_ADC_CLEAR_FLAG(FLAG) (((FLAG) != (uint32_t)RESET) && (((FLAG) & 0xFFFFFF60) == (uint32_t)RESET)) - -#define IS_ADC_GET_FLAG(FLAG) (((FLAG) == ADC_FLAG_ADRDY) || ((FLAG) == ADC_FLAG_EOSMP) || \ - ((FLAG) == ADC_FLAG_EOC) || ((FLAG) == ADC_FLAG_EOSEQ) || \ - ((FLAG) == ADC_FLAG_AWD) || ((FLAG) == ADC_FLAG_OVR) || \ - ((FLAG) == ADC_FLAG_ADEN) || ((FLAG) == ADC_FLAG_ADDIS) || \ - ((FLAG) == ADC_FLAG_ADSTART) || ((FLAG) == ADC_FLAG_ADSTP) || \ - ((FLAG) == ADC_FLAG_ADCAL)) - - - - - -#define ADC_Vrefsel_0_625V ((uint32_t)0x00000002) -#define ADC_Vrefsel_1_5V ((uint32_t)0x00000006) -#define ADC_Vrefsel_2_5V ((uint32_t)0x0000000A) -#define ADC_Vrefsel_VDDA ((uint32_t)(~(uint32_t)0x0000000E)) -#define IS_ADC_Vrefsel(Vref) ( ( (Vref) == ADC_Vrefsel_0_625V) || \ - ( (Vref) == ADC_Vrefsel_1_5V ) || \ - ( (Vref) == ADC_Vrefsel_2_5V ) || \ - ( (Vref) == ADC_Vrefsel_VDDA ) ) - -#define ADC_VrefEN ((uint32_t)0x00000002) - - -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions ------------------------------------------------------- */ - -/* Function used to set the ADC configuration to the default reset state *****/ -void ADC_DeInit(ADC_TypeDef* ADCx); - -/* Initialization and Configuration functions *********************************/ -void ADC_Init(ADC_TypeDef* ADCx, ADC_InitTypeDef* ADC_InitStruct); -void ADC_StructInit(ADC_InitTypeDef* ADC_InitStruct); -void ADC_ClockModeConfig(ADC_TypeDef* ADCx, uint32_t ADC_ClockMode); -void ADC_Cmd(ADC_TypeDef* ADCx, FunctionalState NewState); -/* This Function is obsolete and maintained for legacy purpose only. - ADC_ClockModeConfig() function should be used instead */ -void ADC_JitterCmd(ADC_TypeDef* ADCx, uint32_t ADC_JitterOff, FunctionalState NewState); - -/* Power saving functions *****************************************************/ -void ADC_AutoPowerOffCmd(ADC_TypeDef* ADCx, FunctionalState NewState); -void ADC_WaitModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState); - -/* Analog Watchdog configuration functions ************************************/ -void ADC_AnalogWatchdogCmd(ADC_TypeDef* ADCx, FunctionalState NewState); -void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef* ADCx, uint16_t HighThreshold,uint16_t LowThreshold); -void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef* ADCx, uint32_t ADC_AnalogWatchdog_Channel); -void ADC_AnalogWatchdogSingleChannelCmd(ADC_TypeDef* ADCx, FunctionalState NewState); - -/* Temperature Sensor , Vrefint and Vbat management function ... ******************/ -void ADC_TempSensorCmd(FunctionalState NewState); -void ADC_VrefintCmd(FunctionalState NewState); -void ADC_VbatCmd(FunctionalState NewState); -void ADC_VrefDecibCmd(FunctionalState NewState); -void ADC_IoshSmpCmd(uint32_t SmpEn, FunctionalState NewState); -void ADC_IoshAmpCmd(uint32_t AmpEn, FunctionalState NewState); - -/* Channels Configuration functions *******************************************/ -void ADC_ChannelConfig(ADC_TypeDef* ADCx, uint32_t ADC_Channel, uint32_t ADC_SampleTime); -void ADC_ContinuousModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState); -void ADC_DiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState); -void ADC_OverrunModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState); -uint32_t ADC_GetCalibrationFactor(ADC_TypeDef* ADCx); -void ADC_StopOfConversion(ADC_TypeDef* ADCx); -void ADC_StartOfConversion(ADC_TypeDef* ADCx); -uint16_t ADC_GetConversionValue(ADC_TypeDef* ADCx); - -#if defined (FT32F072xB) -void ADC_IoshSmpSel(uint32_t Ioshx, uint32_t SmpSel); -void ADC_IoshSmpMod(uint32_t SmpModBit, uint32_t Mode); -void ADC_ExtModeCmd(FunctionalState NewState); -void ADC_TrgdDisSmpCmd(FunctionalState NewState); -void ADC_ExtDlyConfig(uint32_t ExtDly); -void ADC_RtenCmd(uint32_t Rtenx, FunctionalState NewState); -void ADC_FtenCmd(uint32_t Ftenx, FunctionalState NewState); - -#endif - - -/* Regular Channels DMA Configuration functions *******************************/ -void ADC_DMACmd(ADC_TypeDef* ADCx, FunctionalState NewState); -void ADC_DMARequestModeConfig(ADC_TypeDef* ADCx, uint32_t ADC_DMARequestMode); - -/* Interrupts and flags management functions **********************************/ -void ADC_ITConfig(ADC_TypeDef* ADCx, uint32_t ADC_IT, FunctionalState NewState); -FlagStatus ADC_GetFlagStatus(ADC_TypeDef* ADCx, uint32_t ADC_FLAG); -void ADC_ClearFlag(ADC_TypeDef* ADCx, uint32_t ADC_FLAG); -ITStatus ADC_GetITStatus(ADC_TypeDef* ADCx, uint32_t ADC_IT); -void ADC_ClearITPendingBit(ADC_TypeDef* ADCx, uint32_t ADC_IT); -void ADC_VrefselConfig(uint32_t ADC_Vrefsel); -#ifdef __cplusplus -} -#endif - -#endif /*__ft32F0XX_ADC_H */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT FMD *****END OF FILE****/ diff --git a/bsp/ft32/libraries/FT32F0xx/FT32F0xx_Driver/Inc/ft32f0xx_comp.h b/bsp/ft32/libraries/FT32F0xx/FT32F0xx_Driver/Inc/ft32f0xx_comp.h deleted file mode 100644 index 8f4a5c4a383..00000000000 --- a/bsp/ft32/libraries/FT32F0xx/FT32F0xx_Driver/Inc/ft32f0xx_comp.h +++ /dev/null @@ -1,255 +0,0 @@ -/** - ****************************************************************************** - * @file ft32f0xx_comp.h - * @author FMD AE - * @brief This file contains all the functions prototypes for the COMP firmware - * library - * @version V1.0.0 - * @data 2021-07-01 - ****************************************************************************** - */ - - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __FT32F0XX_COMP_H -#define __FT32F0XX_COMP_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "ft32f0xx.h" - -/** @addtogroup COMP - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ - -/** - * @brief COMP Init structure definition - */ - -typedef struct -{ - - uint32_t COMP_VipSel; /*!< Select the positive input of the comparator. - This parameter can be a value of @ref COMP_VipSel */ - - uint32_t COMP_VinSel; /*!< Select the negative input of the comparator. - This parameter can be a value of @ref COMP_VinSel */ - - uint32_t COMP_OutputSel; /*!< Selects The output selection of the comparator. - This parameter can be a value of @ref COMP_OutputSel */ - - uint32_t COMP_Pol; /*!< Select the output polarity of the comparator. - This parameter can be a value of @ref COMP_Pol */ - -}COMP_InitTypeDef; - -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup COMP_Exported_Constants - * @{ - */ - -/** @defgroup COMP_Selection - * @{ - */ - -#define NCOMP_Selection_COMP ((uint32_t)0x00000000) /*!< NCOMP Selection */ -#define PCOMP_Selection_COMP ((uint32_t)0x00000010) /*!< PCOMP Selection */ -#define COMP_Selection_COMP3 ((uint32_t)0x00000001) /*!< PCOMP Selection */ - -#define IS_COMP_ALL_PERIPH(PERIPH) (((PERIPH) == NCOMP_Selection_COMP) || \ - ((PERIPH) == PCOMP_Selection_COMP)) - - -#define COMP_Selection_COMP1 NCOMP_Selection_COMP -#define COMP_Selection_COMP2 PCOMP_Selection_COMP -/** - * @} - */ - -/** @defgroup COMP_VipSel - * @{ - */ - -#define NCOMP_VIP_SEL_1WIRE ((uint32_t)0x00000000) -#define NCOMP_VIP_SEL_PAD_PA1 ((uint32_t)0x00000002) -#define NCOMP_VIP_SEL_PAD_PA4 ((uint32_t)0x00000004) -#define NCOMP_VIP_SEL_PAD_PA13 ((uint32_t)0x00000006) -#define NCOMP_VIP_SEL_PAD_PB12 ((uint32_t)0x00000008) - -#define PCOMP_VIP_SEL_PAD_PA3 ((uint32_t)0x00000000) -#define PCOMP_VIP_SEL_PAD_PA4 ((uint32_t)0x00020000) -#define PCOMP_VIP_SEL_PAD_PA13 ((uint32_t)0x00040000) -#define PCOMP_VIP_SEL_PAD_PB12 ((uint32_t)0x00060000) - -#define COMP3_VIP_SEL_PAD_PF5 ((uint32_t)0x00000000) -#define COMP3_VIP_SEL_PAD_PB12 ((uint32_t)0x00000002) -#define COMP3_VIP_SEL_PAD_PA13 ((uint32_t)0x00000004) -#define COMP3_VIP_SEL_PAD_PA4 ((uint32_t)0x00000006) - -#define IS_COMP_VIP_SEL(INPUT) (((INPUT) == NCOMP_VIP_SEL_1WIRE) || \ - ((INPUT) == NCOMP_VIP_SEL_PAD_PA1) || \ - ((INPUT) == NCOMP_VIP_SEL_PAD_PA4) || \ - ((INPUT) == NCOMP_VIP_SEL_PAD_PA13) || \ - ((INPUT) == NCOMP_VIP_SEL_PAD_PB12) || \ - ((INPUT) == PCOMP_VIP_SEL_PAD_PA3) || \ - ((INPUT) == PCOMP_VIP_SEL_PAD_PA4) || \ - ((INPUT) == PCOMP_VIP_SEL_PAD_PA13) || \ - ((INPUT) == PCOMP_VIP_SEL_PAD_PB12) ) -/** - * @} - */ - -/** @defgroup COMP_VinSel - * @{ - */ - -#define NCOMP_VIN_SEL_DAC1_OUT ((uint32_t)0x00000000) -#define NCOMP_VIN_SEL_PAD_PA0 ((uint32_t)0x00000010) -#define NCOMP_VIN_SEL_PAD_PA4 ((uint32_t)0x00000020) -#define NCOMP_VIN_SEL_PAD_PA5 ((uint32_t)0x00000030) - -#define PCOMP_VIN_SEL_DAC2_OUT ((uint32_t)0x00000000) -#define PCOMP_VIN_SEL_PAD_PA2 ((uint32_t)0x00080000) -#define PCOMP_VIN_SEL_PAD_PA4 ((uint32_t)0x00100000) -#define PCOMP_VIN_SEL_PAD_PA5 ((uint32_t)0x00180000) - -#define COMP3_VIN_SEL_PAD_PF4 ((uint32_t)0x00000000) -#define COMP3_VIN_SEL_DAC2_OUT ((uint32_t)0x00000010) -#define COMP3_VIN_SEL_PAD_PA4 ((uint32_t)0x00000020) -#define COMP3_VIN_SEL_PAD_PA5 ((uint32_t)0x00000030) - -#define IS_COMP_VINSEL(INPUT) (((INPUT) == NCOMP_VIN_SEL_DAC1_OUT) || \ - ((INPUT) == NCOMP_VIN_SEL_PAD_PA0) || \ - ((INPUT) == NCOMP_VIN_SEL_PAD_PA4) || \ - ((INPUT) == NCOMP_VIN_SEL_PAD_PA5) || \ - ((INPUT) == PCOMP_VIN_SEL_DAC2_OUT)|| \ - ((INPUT) == PCOMP_VIN_SEL_PAD_PA2) || \ - ((INPUT) == PCOMP_VIN_SEL_PAD_PA4) || \ - ((INPUT) == PCOMP_VIN_SEL_PAD_PA5) ) -/** - * @} - */ - -/** @defgroup COMP_OutputSel - * @{ - */ - -#define COMP_OUTPUT_NO_SELECTION ((uint32_t)0x00000000) -#define NCOMP_OUTPUT_SEL_TIM1_CAPTURE1 ((uint32_t)0x00000200) -#define NCOMP_OUTPUT_SEL_TIM1_OCREFCLEAR ((uint32_t)0x00000300) -#define NCOMP_OUTPUT_SEL_TIM3_CAPTURE1 ((uint32_t)0x00000600) -#define NCOMP_OUTPUT_SEL_TIM3_OCREFCLEAR ((uint32_t)0x00000700) - -#define PCOMP_OUTPUT_SEL_TIM1_BREAK ((uint32_t)0x01000000) -#define PCOMP_OUTPUT_SEL_TIM1_CAPTURE1 ((uint32_t)0x02000000) -#define PCOMP_OUTPUT_SEL_TIM1_OCREFCLEAR ((uint32_t)0x03000000) -#define PCOMP_OUTPUT_SEL_TIM3_CAPTURE1 ((uint32_t)0x06000000) -#define PCOMP_OUTPUT_SEL_TIM3_OCREFCLEAR ((uint32_t)0x07000000) - -#define COMP3_OUTPUT_SEL_TIM1_CAPTURE1 ((uint32_t)0x00000200) -#define COMP3_OUTPUT_SEL_TIM1_OCREFCLEAR ((uint32_t)0x00000300) -#define COMP3_OUTPUT_SEL_TIM3_CAPTURE1 ((uint32_t)0x00000600) -#define COMP3_OUTPUT_SEL_TIM3_OCREFCLEAR ((uint32_t)0x00000700) - -#define IS_COMP_OUTPUT_SEL(SEL) ( ((SEL) == NCOMP_OUTPUT_SEL_TIM1_CAPTURE1) || \ - ((SEL) == NCOMP_OUTPUT_SEL_TIM1_OCREFCLEAR) ||\ - ((SEL) == NCOMP_OUTPUT_SEL_TIM3_CAPTURE1) ||\ - ((SEL) == NCOMP_OUTPUT_SEL_TIM3_OCREFCLEAR) ||\ - ((SEL) == PCOMP_OUTPUT_SEL_TIM1_BREAK) ||\ - ((SEL) == PCOMP_OUTPUT_SEL_TIM1_CAPTURE1) ||\ - ((SEL) == PCOMP_OUTPUT_SEL_TIM1_OCREFCLEAR) ||\ - ((SEL) == PCOMP_OUTPUT_SEL_TIM3_CAPTURE1) ||\ - ((SEL) == PCOMP_OUTPUT_SEL_TIM3_OCREFCLEAR) ||\ - ((SEL) == COMP_OUTPUT_NO_SELECTION) ) - -/** - * @} - */ - -/** @defgroup COMP_Pol - * @{ - */ - -#define NCOMP_POL_NOT_INVERT ((uint32_t)0x00000000) -#define NCOMP_POL_INVERT ((uint32_t)0x00000800) - -#define PCOMP_POL_NOT_INVERT ((uint32_t)0x00000000) -#define PCOMP_POL_INVERT ((uint32_t)0x08000000) - -#define COMP3_POL_NOT_INVERT ((uint32_t)0x00000000) -#define COMP3_POL_INVERT ((uint32_t)0x00000800) - -#define IS_COMP_POL(POL) ( ((POL) == NCOMP_POL_NOT_INVERT) || \ - ((POL) == NCOMP_POL_INVERT) || \ - ((POL) == PCOMP_POL_NOT_INVERT) || \ - ((POL) == PCOMP_POL_INVERT) ) - - -/** - * @} - */ - -/** - * @} - */ - -/** @defgroup COMP_OutputLevel - * @{ - */ -/* When output polarity is not inverted, comparator output is high when - the non-inverting input is at a higher voltage than the inverting input */ -#define COMP_OutputLevel_High COMP_CSR_COMP1OUT -/* When output polarity is not inverted, comparator output is low when - the non-inverting input is at a lower voltage than the inverting input*/ -#define COMP_OutputLevel_Low ((uint32_t)0x00000000) - - -#define IS_COMP_OUTPUT_LEVEL(LEVEL) (((LEVEL) == COMP_CSR_COMP1OUT) || \ - ((LEVEL) == COMP_CSR_COMP2OUT)) -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions ------------------------------------------------------- */ - -/* Function used to set the COMP configuration to the default reset state ****/ -void COMP_DeInit(void); - -/* Initialization and Configuration functions *********************************/ -void COMP_Init(uint32_t COMP_Selection, COMP_InitTypeDef* COMP_InitStruct); -void COMP_StructInit(COMP_InitTypeDef* COMP_InitStruct); -void COMP_Cmd(uint32_t COMP_Selection, FunctionalState NewState); -uint32_t COMP_GetOutputLevel(uint32_t COMP_Selection); - -/* Window mode control function ***********************************************/ -void COMP_WindowCmd(FunctionalState NewState); - -/* COMP configuration locking function ****************************************/ -void COMP_LockConfig(uint32_t COMP_Selection); - -#ifdef __cplusplus -} -#endif - -#endif /*__FT32F0XX_COMP_H */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT FMD *****END OF FILE****/ diff --git a/bsp/ft32/libraries/FT32F0xx/FT32F0xx_Driver/Inc/ft32f0xx_crc.h b/bsp/ft32/libraries/FT32F0xx/FT32F0xx_Driver/Inc/ft32f0xx_crc.h deleted file mode 100644 index 267bdca81d7..00000000000 --- a/bsp/ft32/libraries/FT32F0xx/FT32F0xx_Driver/Inc/ft32f0xx_crc.h +++ /dev/null @@ -1,103 +0,0 @@ -/** - ****************************************************************************** - * @file ft32f0xx_crc.h - * @author FMD AE - * @brief This file contains all the functions prototypes for the CRC firmware - * library. - * @version V1.0.0 - * @data 2021-07-01 - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __FT32F0XX_CRC_H -#define __FT32F0XX_CRC_H - -#ifdef __cplusplus - extern "C" { -#endif - -/*!< Includes ----------------------------------------------------------------*/ -#include "ft32f0xx.h" - - -/** @addtogroup CRC - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup CRC_ReverseInputData - * @{ - */ -#define CRC_ReverseInputData_No ((uint32_t)0x00000000) /*!< No reverse operation of Input Data */ -#define CRC_ReverseInputData_8bits CRC_CR_REV_IN_0 /*!< Reverse operation of Input Data on 8 bits */ -#define CRC_ReverseInputData_16bits CRC_CR_REV_IN_1 /*!< Reverse operation of Input Data on 16 bits */ -#define CRC_ReverseInputData_32bits CRC_CR_REV_IN /*!< Reverse operation of Input Data on 32 bits */ - -#define IS_CRC_REVERSE_INPUT_DATA(DATA) (((DATA) == CRC_ReverseInputData_No) || \ - ((DATA) == CRC_ReverseInputData_8bits) || \ - ((DATA) == CRC_ReverseInputData_16bits) || \ - ((DATA) == CRC_ReverseInputData_32bits)) - -/** - * @} - */ - -/** @defgroup CRC_PolynomialSize - * @brief Only applicable for FT32F042 and FT32F072 devices - * @{ - */ -#define CRC_PolSize_7 CRC_CR_POLSIZE /*!< 7-bit polynomial for CRC calculation */ -#define CRC_PolSize_8 CRC_CR_POLSIZE_1 /*!< 8-bit polynomial for CRC calculation */ -#define CRC_PolSize_16 CRC_CR_POLSIZE_0 /*!< 16-bit polynomial for CRC calculation */ -#define CRC_PolSize_32 ((uint32_t)0x00000000)/*!< 32-bit polynomial for CRC calculation */ - -#define IS_CRC_POL_SIZE(SIZE) (((SIZE) == CRC_PolSize_7) || \ - ((SIZE) == CRC_PolSize_8) || \ - ((SIZE) == CRC_PolSize_16) || \ - ((SIZE) == CRC_PolSize_32)) - - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions ------------------------------------------------------- */ -/* Configuration of the CRC computation unit **********************************/ -void CRC_DeInit(void); -void CRC_ResetDR(void); -//void CRC_PolynomialSizeSelect(uint32_t CRC_PolSize); /*!< Only applicable for FT32F042 and FT32F072 devices */ -void CRC_ReverseInputDataSelect(uint32_t CRC_ReverseInputData); -void CRC_ReverseOutputDataCmd(FunctionalState NewState); -void CRC_SetInitRegister(uint32_t CRC_InitValue); -void CRC_SetPolynomial(uint32_t CRC_Pol); - -/* CRC computation ************************************************************/ -uint32_t CRC_CalcCRC(uint32_t CRC_Data); -uint32_t CRC_CalcCRC16bits(uint16_t CRC_Data); -uint32_t CRC_CalcCRC8bits(uint8_t CRC_Data); -uint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength); -uint32_t CRC_GetCRC(void); - -/* Independent register (IDR) access (write/read) *****************************/ -void CRC_SetIDRegister(uint8_t CRC_IDValue); -uint8_t CRC_GetIDRegister(void); - -#ifdef __cplusplus -} -#endif - -#endif /* __FT32F0XX_CRC_H */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT FMD *****END OF FILE****/ diff --git a/bsp/ft32/libraries/FT32F0xx/FT32F0xx_Driver/Inc/ft32f0xx_crs.h b/bsp/ft32/libraries/FT32F0xx/FT32F0xx_Driver/Inc/ft32f0xx_crs.h deleted file mode 100644 index 5105d6b5de8..00000000000 --- a/bsp/ft32/libraries/FT32F0xx/FT32F0xx_Driver/Inc/ft32f0xx_crs.h +++ /dev/null @@ -1,163 +0,0 @@ -/** - ****************************************************************************** - * @file ft32f0xx_crs.h - * @author FMD AE - * @brief This file contains all the functions prototypes for the CRS firmware - * library. - * @version V1.0.0 - * @data 2021-07-01 - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __FT32F0XX_CRS_H -#define __FT32F0XX_CRS_H - -#ifdef __cplusplus - extern "C" { -#endif - -/*!< Includes ----------------------------------------------------------------*/ -#include "ft32f0xx.h" - - -/** @addtogroup CRS - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup CRS_Interrupt_Sources - * @{ - */ -#define CRS_IT_SYNCOK CRS_ISR_SYNCOKF /*!< SYNC event OK */ -#define CRS_IT_SYNCWARN CRS_ISR_SYNCWARNF /*!< SYNC warning */ -#define CRS_IT_ERR CRS_ISR_ERRF /*!< error */ -#define CRS_IT_ESYNC CRS_ISR_ESYNCF /*!< Expected SYNC */ -#define CRS_IT_TRIMOVF CRS_ISR_TRIMOVF /*!< Trimming overflow or underflow */ -#define CRS_IT_SYNCERR CRS_ISR_SYNCERR /*!< SYNC error */ -#define CRS_IT_SYNCMISS CRS_ISR_SYNCMISS /*!< SYNC missed*/ - -#define IS_CRS_IT(IT) (((IT) == CRS_IT_SYNCOK) || ((IT) == CRS_IT_SYNCWARN) || \ - ((IT) == CRS_IT_ERR) || ((IT) == CRS_IT_ESYNC)) - -#define IS_CRS_GET_IT(IT) (((IT) == CRS_IT_SYNCOK) || ((IT) == CRS_IT_SYNCWARN) || \ - ((IT) == CRS_IT_ERR) || ((IT) == CRS_IT_ESYNC) || \ - ((IT) == CRS_IT_TRIMOVF) || ((IT) == CRS_IT_SYNCERR) || \ - ((IT) == CRS_IT_SYNCMISS)) - -#define IS_CRS_CLEAR_IT(IT) ((IT) != 0x00) - -/** - * @} - */ - -/** @defgroup CRS_Flags - * @{ - */ -#define CRS_FLAG_SYNCOK CRS_ISR_SYNCOKF /*!< SYNC event OK */ -#define CRS_FLAG_SYNCWARN CRS_ISR_SYNCWARNF /*!< SYNC warning */ -#define CRS_FLAG_ERR CRS_ISR_ERRF /*!< error */ -#define CRS_FLAG_ESYNC CRS_ISR_ESYNCF /*!< Expected SYNC */ -#define CRS_FLAG_TRIMOVF CRS_ISR_TRIMOVF /*!< Trimming overflow or underflow */ -#define CRS_FLAG_SYNCERR CRS_ISR_SYNCERR /*!< SYNC error */ -#define CRS_FLAG_SYNCMISS CRS_ISR_SYNCMISS /*!< SYNC missed*/ - -#define IS_CRS_FLAG(FLAG) (((FLAG) == CRS_FLAG_SYNCOK) || ((FLAG) == CRS_FLAG_SYNCWARN) || \ - ((FLAG) == CRS_FLAG_ERR) || ((FLAG) == CRS_FLAG_ESYNC) || \ - ((FLAG) == CRS_FLAG_TRIMOVF) || ((FLAG) == CRS_FLAG_SYNCERR) || \ - ((FLAG) == CRS_FLAG_SYNCMISS)) - -/** - * @} - */ - -/** @defgroup CRS_Synchro_Source - * @{ - */ -#define CRS_SYNCSource_GPIO ((uint32_t)0x00) /*!< Synchro Signal soucre GPIO */ -#define CRS_SYNCSource_LSE CRS_CFGR_SYNCSRC_0 /*!< Synchro Signal source LSE */ -#define CRS_SYNCSource_USB CRS_CFGR_SYNCSRC_1 /*!< Synchro Signal source USB SOF */ - -#define IS_CRS_SYNC_SOURCE(SOURCE) (((SOURCE) == CRS_SYNCSource_GPIO) || \ - ((SOURCE) == CRS_SYNCSource_LSE) ||\ - ((SOURCE) == CRS_SYNCSource_USB)) -/** - * @} - */ - -/** @defgroup CRS_SynchroDivider - * @{ - */ -#define CRS_SYNC_Div1 ((uint32_t)0x00) /*!< Synchro Signal not divided */ -#define CRS_SYNC_Div2 CRS_CFGR_SYNCDIV_0 /*!< Synchro Signal divided by 2 */ -#define CRS_SYNC_Div4 CRS_CFGR_SYNCDIV_1 /*!< Synchro Signal divided by 4 */ -#define CRS_SYNC_Div8 (CRS_CFGR_SYNCDIV_1 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 8 */ -#define CRS_SYNC_Div16 CRS_CFGR_SYNCDIV_2 /*!< Synchro Signal divided by 16 */ -#define CRS_SYNC_Div32 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 32 */ -#define CRS_SYNC_Div64 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_1) /*!< Synchro Signal divided by 64 */ -#define CRS_SYNC_Div128 CRS_CFGR_SYNCDIV /*!< Synchro Signal divided by 128 */ - -#define IS_CRS_SYNC_DIV(DIV) (((DIV) == CRS_SYNC_Div1) || ((DIV) == CRS_SYNC_Div2) ||\ - ((DIV) == CRS_SYNC_Div4) || ((DIV) == CRS_SYNC_Div8) || \ - ((DIV) == CRS_SYNC_Div16) || ((DIV) == CRS_SYNC_Div32) || \ - ((DIV) == CRS_SYNC_Div64) || ((DIV) == CRS_SYNC_Div128)) -/** - * @} - */ - -/** @defgroup CRS_SynchroPolarity - * @{ - */ -#define CRS_SYNCPolarity_Rising ((uint32_t)0x00) /*!< Synchro Active on rising edge */ -#define CRS_SYNCPolarity_Falling CRS_CFGR_SYNCPOL /*!< Synchro Active on falling edge */ - -#define IS_CRS_SYNC_POLARITY(POLARITY) (((POLARITY) == CRS_SYNCPolarity_Rising) || \ - ((POLARITY) == CRS_SYNCPolarity_Falling)) -/** - * @} - */ - - - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions ------------------------------------------------------- */ -/* Configuration of the CRS **********************************/ -void CRS_DeInit(void); -void CRS_AdjustHSI48CalibrationValue(uint8_t CRS_HSI48CalibrationValue); -void CRS_FrequencyErrorCounterCmd(FunctionalState NewState); -void CRS_AutomaticCalibrationCmd(FunctionalState NewState); -void CRS_SoftwareSynchronizationGenerate(void); -void CRS_FrequencyErrorCounterReload(uint32_t CRS_ReloadValue); -void CRS_FrequencyErrorLimitConfig(uint8_t CRS_ErrorLimitValue); -void CRS_SynchronizationPrescalerConfig(uint32_t CRS_Prescaler); -void CRS_SynchronizationSourceConfig(uint32_t CRS_Source); -void CRS_SynchronizationPolarityConfig(uint32_t CRS_Polarity); -uint32_t CRS_GetReloadValue(void); -uint32_t CRS_GetHSI48CalibrationValue(void); -uint32_t CRS_GetFrequencyErrorValue(void); -uint32_t CRS_GetFrequencyErrorDirection(void); - -/* Interrupts and flags management functions **********************************/ -void CRS_ITConfig(uint32_t CRS_IT, FunctionalState NewState); -FlagStatus CRS_GetFlagStatus(uint32_t CRS_FLAG); -void CRS_ClearFlag(uint32_t CRS_FLAG); -ITStatus CRS_GetITStatus(uint32_t CRS_IT); -void CRS_ClearITPendingBit(uint32_t CRS_IT); - -#ifdef __cplusplus -} -#endif - -#endif /* __FT32F0XX_CRS_H */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT FMD *****END OF FILE****/ diff --git a/bsp/ft32/libraries/FT32F0xx/FT32F0xx_Driver/Inc/ft32f0xx_dac.h b/bsp/ft32/libraries/FT32F0xx/FT32F0xx_Driver/Inc/ft32f0xx_dac.h deleted file mode 100644 index e7801b9c6a9..00000000000 --- a/bsp/ft32/libraries/FT32F0xx/FT32F0xx_Driver/Inc/ft32f0xx_dac.h +++ /dev/null @@ -1,43 +0,0 @@ -/** - ****************************************************************************** - * @file ft32f0xx_dac.h - * @author FMD AE - * @brief This file contains all the functions prototypes for the DAC firmware - * library. - * @version V1.0.0 - * @data 2021-07-01 - ****************************************************************************** - */ -#ifndef __FT32F0XX_DAC_H -#define __FT32F0XX_DAC_H - - -#include "ft32f0xx.h" - - - -/** - * @Parama DAC_CTRL - */ - -#define DAC_DATA_RESET ((uint32_t)(0x0000007f)) - -#define DAC_CTRL_READ (uint8_t)(0x20) -#define DAC_DATA1_READ (uint8_t)(0x24) -#define DAC_DATA2_READ (uint8_t)(0x28) - - -#define IS_DAC_DATA(DATA) ((DATA) <= 0x7F) - - -/** - * @Parama DAC1_DATA - */ -void DAC_Ref_Config(uint32_t DAC_RefSel); -void Bsp_DAC_Config(void); -uint8_t DAC_Read_Reg(uint8_t DAC_Register); -void DAC_Cmd(FunctionalState NewState); -void DAC_SetChannel1Data(uint32_t DAC_Align, uint8_t Data); -void DAC_SetChannel2Data(uint32_t DAC_Align, uint8_t Data); - -#endif diff --git a/bsp/ft32/libraries/FT32F0xx/FT32F0xx_Driver/Inc/ft32f0xx_debug.h b/bsp/ft32/libraries/FT32F0xx/FT32F0xx_Driver/Inc/ft32f0xx_debug.h deleted file mode 100644 index fb26b75f383..00000000000 --- a/bsp/ft32/libraries/FT32F0xx/FT32F0xx_Driver/Inc/ft32f0xx_debug.h +++ /dev/null @@ -1,87 +0,0 @@ -/** - ****************************************************************************** - * @file ft32f0xx_debug.h - * @author FMD AE - * @brief This file contains all the functions prototypes for the DBGMCU firmware - * library. - * @version V1.0.0 - * @data 2021-07-01 - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __FT32F0XX_DBGMCU_H -#define __FT32F0XX_DBGMCU_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "ft32f0xx.h" - - -/** @addtogroup DBGMCU - * @{ - */ -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ - - -/** @defgroup DBGMCU_Exported_Constants - * @{ - */ - -#define DBGMCU_STOP DBGMCU_CR_DBG_STOP -#define DBGMCU_STANDBY DBGMCU_CR_DBG_STANDBY -#define IS_DBGMCU_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFFF9) == 0x00) && ((PERIPH) != 0x00)) - -#define DBGMCU_TIM2_STOP DBGMCU_APB1_FZ_DBG_TIM2_STOP -#define DBGMCU_TIM3_STOP DBGMCU_APB1_FZ_DBG_TIM3_STOP -#define DBGMCU_TIM6_STOP DBGMCU_APB1_FZ_DBG_TIM6_STOP -#define DBGMCU_TIM7_STOP DBGMCU_APB1_FZ_DBG_TIM7_STOP -#define DBGMCU_TIM14_STOP DBGMCU_APB1_FZ_DBG_TIM14_STOP -#define DBGMCU_RTC_STOP DBGMCU_APB1_FZ_DBG_RTC_STOP -#define DBGMCU_WWDG_STOP DBGMCU_APB1_FZ_DBG_WWDG_STOP -#define DBGMCU_IWDG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP -#define DBGMCU_I2C1_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT -#define DBGMCU_CAN1_STOP DBGMCU_APB1_FZ_DBG_CAN1_STOP -#define IS_DBGMCU_APB1PERIPH(PERIPH) ((((PERIPH) & 0xFDDFE2CC) == 0x00) && ((PERIPH) != 0x00)) - -#define DBGMCU_TIM1_STOP DBGMCU_APB2_FZ_DBG_TIM1_STOP -#define DBGMCU_TIM15_STOP DBGMCU_APB2_FZ_DBG_TIM15_STOP -#define DBGMCU_TIM16_STOP DBGMCU_APB2_FZ_DBG_TIM16_STOP -#define DBGMCU_TIM17_STOP DBGMCU_APB2_FZ_DBG_TIM17_STOP -#define IS_DBGMCU_APB2PERIPH(PERIPH) ((((PERIPH) & 0xFFF8F7FF) == 0x00) && ((PERIPH) != 0x00)) - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions ------------------------------------------------------- */ - -/* Device and Revision ID management functions ********************************/ -uint32_t DBGMCU_GetREVID(void); -uint32_t DBGMCU_GetDEVID(void); - -/* Peripherals Configuration functions ****************************************/ -void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState); -void DBGMCU_APB1PeriphConfig(uint32_t DBGMCU_Periph, FunctionalState NewState); -void DBGMCU_APB2PeriphConfig(uint32_t DBGMCU_Periph, FunctionalState NewState); - -#ifdef __cplusplus -} -#endif - -#endif /* __FT32F0XX_DBGMCU_H */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT FMD *****END OF FILE****/ diff --git a/bsp/ft32/libraries/FT32F0xx/FT32F0xx_Driver/Inc/ft32f0xx_div.h b/bsp/ft32/libraries/FT32F0xx/FT32F0xx_Driver/Inc/ft32f0xx_div.h deleted file mode 100644 index e8d17728ec8..00000000000 --- a/bsp/ft32/libraries/FT32F0xx/FT32F0xx_Driver/Inc/ft32f0xx_div.h +++ /dev/null @@ -1,112 +0,0 @@ -/** - ****************************************************************************** - * @file FT32f0xx_div.h - * @author FMD AE - * @brief This file contains all the functions prototypes for the dividor firmware - * library. - * @version V1.0.0 - * @data 2021-12-01 - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __FT32F0XX_DIV_H -#define __FT32F0XX_DIV_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "ft32f0xx.h" -#include -/** @addtogroup DIV - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ - -/** - * @brief DIV Status - */ -typedef enum -{ - DIV_COMPLETE = 0, - DIV_ERROR_DIV0ERR, - DIV_ERROR_DIV0V, -}DIV_Status; - -/** - * @brief Dividor Data structure definition - */ -typedef struct -{ - uint32_t DIV_quotient; /*!< Selects The feedback resister of the OPA. */ - uint32_t DIV_remainder; /*!< Selects The compensate cap of the OPA.*/ -}DIV_ResultTypeDef; - -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup DIV_interrupts_definition - * @{ - */ - -#define DIV_IT_DIV0ERR DIV_SC_DIV0IE -#define DIV_IT_DIVOV DIV_SC_DIVOVIE -#define IS_DIV_CONFIG_IT(IT) (((IT) != (uint32_t)RESET) && (((IT) & 0xFFFFFFEB) == (uint32_t)RESET)) - -#define IS_DIV_GET_IT(IT) (((IT) == DIV_IT_DIV0ERR) || ((IT) == DIV_IT_DIVOV)) - -#define IS_DIV_CLEAR_IT(IT) (((IT) != (uint32_t)RESET) && (((IT) & 0xFFFFFFEB0) == (uint32_t)RESET)) - -/** - * @} - */ - -/** @defgroup DIV_flags_definition - * @{ - */ - -#define DIV_FLAG_BUSY DIV_SC_DIVBUSY -#define DIV_FLAG_DIV0ERR DIV_SC_DIV0ERR -#define DIV_FLAG_DIVOV DIV_SC_DIVOV - -#define IS_DIV_CLEAR_FLAG(FLAG) (((FLAG) != (uint32_t)RESET) && (((FLAG) & 0xFFFFFFFF5) == (uint32_t)RESET)) - -#define IS_DIV_GET_FLAG(FLAG) (((FLAG) == DIV_FLAG_BUSY) || ((FLAG) == DIV_FLAG_DIV0ERR) || ((FLAG) == DIV_FLAG_DIV0ERR)) - -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions ------------------------------------------------------- */ -/* DIV Calculating functions *****************************************/ -DIV_Status DivS32ByS16(DIV_ResultTypeDef* pResult,int32_t divedent,int16_t dividor); - -/* Interrupts and flags management functions **********************************/ -void DIV_ITConfig(uint32_t DIV_IT, FunctionalState NewState); -FlagStatus DIV_GetFlagStatus(uint32_t DIV_FLAG); -void DIV_ClearFlag(uint32_t DIV_FLAG); -ITStatus DIV_GetITStatus(uint32_t DIV_IT); -void DIV_ClearITPendingBit(uint32_t DIV_IT); - -#ifdef __cplusplus -} -#endif - -#endif /*__FT32F0XX_DIV_H */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT FMD *****END OF FILE****/ diff --git a/bsp/ft32/libraries/FT32F0xx/FT32F0xx_Driver/Inc/ft32f0xx_dma.h b/bsp/ft32/libraries/FT32F0xx/FT32F0xx_Driver/Inc/ft32f0xx_dma.h deleted file mode 100644 index 69ff8f6f164..00000000000 --- a/bsp/ft32/libraries/FT32F0xx/FT32F0xx_Driver/Inc/ft32f0xx_dma.h +++ /dev/null @@ -1,783 +0,0 @@ -/** - ****************************************************************************** - * @file ft32f0xx_dma.h - * @author FMD AE - * @brief This file contains all the functions prototypes for the DMA firmware - * library. - * @version V1.0.0 - * @data 2021-07-01 - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __FT32F0XX_DMA_H -#define __FT32F0XX_DMA_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "ft32f0xx.h" - - -/** @addtogroup DMA - * @{ - */ -/* Exported types ------------------------------------------------------------*/ - -/** - * @brief DMA Init structures definition - */ -typedef struct -{ - uint32_t DMA_PeripheralBaseAddr; /*!< Specifies the peripheral base address for DMAy Channelx. */ - - uint32_t DMA_MemoryBaseAddr; /*!< Specifies the memory base address for DMAy Channelx. */ - - uint32_t DMA_DIR; /*!< Specifies if the peripheral is the source or destination. - This parameter can be a value of @ref DMA_data_transfer_direction */ - - uint32_t DMA_BufferSize; /*!< Specifies the buffer size, in data unit, of the specified Channel. - The data unit is equal to the configuration set in DMA_PeripheralDataSize - or DMA_MemoryDataSize members depending in the transfer direction */ - - uint32_t DMA_PeripheralInc; /*!< Specifies whether the Peripheral address register is incremented or not. - This parameter can be a value of @ref DMA_peripheral_incremented_mode */ - - uint32_t DMA_MemoryInc; /*!< Specifies whether the memory address register is incremented or not. - This parameter can be a value of @ref DMA_memory_incremented_mode */ - - uint32_t DMA_PeripheralDataSize; /*!< Specifies the Peripheral data width. - This parameter can be a value of @ref DMA_peripheral_data_size */ - - uint32_t DMA_MemoryDataSize; /*!< Specifies the Memory data width. - This parameter can be a value of @ref DMA_memory_data_size */ - - uint32_t DMA_Mode; /*!< Specifies the operation mode of the DMAy Channelx. - This parameter can be a value of @ref DMA_circular_normal_mode - @note: The circular buffer mode cannot be used if the memory-to-memory - data transfer is configured on the selected Channel */ - - uint32_t DMA_Priority; /*!< Specifies the software priority for the DMAy Channelx. - This parameter can be a value of @ref DMA_priority_level */ - - uint32_t DMA_M2M; /*!< Specifies if the DMAy Channelx will be used in memory-to-memory transfer. - This parameter can be a value of @ref DMA_memory_to_memory */ -}DMA_InitTypeDef; - -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup DMA_Exported_Constants - * @{ - */ - -#define IS_DMA_ALL_PERIPH(PERIPH) (((PERIPH) == DMA1_Channel1) || \ - ((PERIPH) == DMA1_Channel2) || \ - ((PERIPH) == DMA1_Channel3) || \ - ((PERIPH) == DMA1_Channel4) || \ - ((PERIPH) == DMA1_Channel5) || \ - ((PERIPH) == DMA1_Channel6) || \ - ((PERIPH) == DMA1_Channel7) || \ - ((PERIPH) == DMA2_Channel1) || \ - ((PERIPH) == DMA2_Channel2) || \ - ((PERIPH) == DMA2_Channel3) || \ - ((PERIPH) == DMA2_Channel4) || \ - ((PERIPH) == DMA2_Channel5)) - -/** @defgroup DMA_data_transfer_direction - * @{ - */ - -#define DMA_DIR_PeripheralSRC ((uint32_t)0x00000000) -#define DMA_DIR_PeripheralDST DMA_CCR_DIR - -#define IS_DMA_DIR(DIR) (((DIR) == DMA_DIR_PeripheralSRC) || \ - ((DIR) == DMA_DIR_PeripheralDST)) -/** - * @} - */ - -/** @defgroup DMA_peripheral_incremented_mode - * @{ - */ - -#define DMA_PeripheralInc_Disable ((uint32_t)0x00000000) -#define DMA_PeripheralInc_Enable DMA_CCR_PINC - -#define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PeripheralInc_Disable) || \ - ((STATE) == DMA_PeripheralInc_Enable)) -/** - * @} - */ - -/** @defgroup DMA_memory_incremented_mode - * @{ - */ - -#define DMA_MemoryInc_Disable ((uint32_t)0x00000000) -#define DMA_MemoryInc_Enable DMA_CCR_MINC - -#define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MemoryInc_Disable) || \ - ((STATE) == DMA_MemoryInc_Enable)) -/** - * @} - */ - -/** @defgroup DMA_peripheral_data_size - * @{ - */ - -#define DMA_PeripheralDataSize_Byte ((uint32_t)0x00000000) -#define DMA_PeripheralDataSize_HalfWord DMA_CCR_PSIZE_0 -#define DMA_PeripheralDataSize_Word DMA_CCR_PSIZE_1 - -#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PeripheralDataSize_Byte) || \ - ((SIZE) == DMA_PeripheralDataSize_HalfWord) || \ - ((SIZE) == DMA_PeripheralDataSize_Word)) -/** - * @} - */ - -/** @defgroup DMA_memory_data_size - * @{ - */ - -#define DMA_MemoryDataSize_Byte ((uint32_t)0x00000000) -#define DMA_MemoryDataSize_HalfWord DMA_CCR_MSIZE_0 -#define DMA_MemoryDataSize_Word DMA_CCR_MSIZE_1 - -#define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MemoryDataSize_Byte) || \ - ((SIZE) == DMA_MemoryDataSize_HalfWord) || \ - ((SIZE) == DMA_MemoryDataSize_Word)) -/** - * @} - */ - -/** @defgroup DMA_circular_normal_mode - * @{ - */ - -#define DMA_Mode_Normal ((uint32_t)0x00000000) -#define DMA_Mode_Circular DMA_CCR_CIRC - -#define IS_DMA_MODE(MODE) (((MODE) == DMA_Mode_Normal) || ((MODE) == DMA_Mode_Circular)) -/** - * @} - */ - -/** @defgroup DMA_priority_level - * @{ - */ - -#define DMA_Priority_VeryHigh DMA_CCR_PL -#define DMA_Priority_High DMA_CCR_PL_1 -#define DMA_Priority_Medium DMA_CCR_PL_0 -#define DMA_Priority_Low ((uint32_t)0x00000000) - -#define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_Priority_VeryHigh) || \ - ((PRIORITY) == DMA_Priority_High) || \ - ((PRIORITY) == DMA_Priority_Medium) || \ - ((PRIORITY) == DMA_Priority_Low)) -/** - * @} - */ - -/** @defgroup DMA_memory_to_memory - * @{ - */ - -#define DMA_M2M_Disable ((uint32_t)0x00000000) -#define DMA_M2M_Enable DMA_CCR_MEM2MEM - -#define IS_DMA_M2M_STATE(STATE) (((STATE) == DMA_M2M_Disable) || ((STATE) == DMA_M2M_Enable)) - -/** - * @} - */ - -/** @defgroup DMA_Remap_Config - * @{ - */ -#define DMAx_CHANNEL1_RMP 0x00000000 -#define DMAx_CHANNEL2_RMP 0x10000000 -#define DMAx_CHANNEL3_RMP 0x20000000 -#define DMAx_CHANNEL4_RMP 0x30000000 -#define DMAx_CHANNEL5_RMP 0x40000000 -#define DMAx_CHANNEL6_RMP 0x50000000 -#define DMAx_CHANNEL7_RMP 0x60000000 - - -#define IS_DMA_ALL_LIST(LIST) (((LIST) == DMA1) || \ - ((LIST) == DMA2)) - -/****************** DMA1 remap bit field definition********************/ -/* DMA1 - Channel 1 */ -#define DMA1_CH1_DEFAULT (uint32_t) (DMAx_CHANNEL1_RMP | DMA_RMPCR1_DEFAULT) /*!< Default remap position for DMA1 */ -#define DMA1_CH1_ADC (uint32_t) (DMAx_CHANNEL1_RMP | DMA_RMPCR1_CH1_ADC) /*!< Remap ADC on DMA1 Channel 1*/ -#define DMA1_CH1_TIM17_CH1 (uint32_t) (DMAx_CHANNEL1_RMP | DMA_RMPCR1_CH1_TIM17_CH1) /*!< Remap TIM17 channel 1 on DMA1 channel 1 */ -#define DMA1_CH1_TIM17_UP (uint32_t) (DMAx_CHANNEL1_RMP | DMA_RMPCR1_CH1_TIM17_UP) /*!< Remap TIM17 up on DMA1 channel 1 */ -#define DMA1_CH1_USART1_RX (uint32_t) (DMAx_CHANNEL1_RMP | DMA_RMPCR1_CH1_USART1_RX) /*!< Remap USART1 Rx on DMA1 channel 1 */ -#define DMA1_CH1_USART2_RX (uint32_t) (DMAx_CHANNEL1_RMP | DMA_RMPCR1_CH1_USART2_RX) /*!< Remap USART2 Rx on DMA1 channel 1 */ -#define DMA1_CH1_USART3_RX (uint32_t) (DMAx_CHANNEL1_RMP | DMA_RMPCR1_CH1_USART3_RX) /*!< Remap USART3 Rx on DMA1 channel 1 */ -#define DMA1_CH1_USART4_RX (uint32_t) (DMAx_CHANNEL1_RMP | DMA_RMPCR1_CH1_USART4_RX) /*!< Remap USART4 Rx on DMA1 channel 1 */ -#define DMA1_CH1_USART5_RX (uint32_t) (DMAx_CHANNEL1_RMP | DMA_RMPCR1_CH1_USART5_RX) /*!< Remap USART5 Rx on DMA1 channel 1 */ -#define DMA1_CH1_USART6_RX (uint32_t) (DMAx_CHANNEL1_RMP | DMA_RMPCR1_CH1_USART6_RX) /*!< Remap USART6 Rx on DMA1 channel 1 */ -#define DMA1_CH1_USART7_RX (uint32_t) (DMAx_CHANNEL1_RMP | DMA_RMPCR1_CH1_USART7_RX) /*!< Remap USART7 Rx on DMA1 channel 1 */ -#define DMA1_CH1_USART8_RX (uint32_t) (DMAx_CHANNEL1_RMP | DMA_RMPCR1_CH1_USART8_RX) /*!< Remap USART8 Rx on DMA1 channel 1 */ -/* DMA1 - Channel 2 */ -#define DMA1_CH2_DEFAULT (uint32_t) (DMAx_CHANNEL2_RMP | DMA_RMPCR1_DEFAULT) /*!< Default remap position for DMA1 */ -#define DMA1_CH2_ADC (uint32_t) (DMAx_CHANNEL2_RMP | DMA_RMPCR1_CH2_ADC) /*!< Remap ADC on DMA1 channel 2 */ -#define DMA1_CH2_I2C1_TX (uint32_t) (DMAx_CHANNEL2_RMP | DMA_RMPCR1_CH2_I2C1_TX) /*!< Remap I2C1 Tx on DMA1 channel 2 */ -#define DMA1_CH2_SPI1_RX (uint32_t) (DMAx_CHANNEL2_RMP | DMA_RMPCR1_CH2_SPI_1RX) /*!< Remap SPI1 Rx on DMA1 channel 2 */ -#define DMA1_CH2_TIM1_CH1 (uint32_t) (DMAx_CHANNEL2_RMP | DMA_RMPCR1_CH2_TIM1_CH1) /*!< Remap TIM1 channel 1 on DMA1 channel 2 */ -#define DMA1_CH2_TIM17_CH1 (uint32_t) (DMAx_CHANNEL2_RMP | DMA_RMPCR1_CH2_TIM17_CH1) /*!< Remap TIM17 channel 1 on DMA1 channel 2 */ -#define DMA1_CH2_TIM17_UP (uint32_t) (DMAx_CHANNEL2_RMP | DMA_RMPCR1_CH2_TIM17_UP) /*!< Remap TIM17 up on DMA1 channel 2 */ -#define DMA1_CH2_USART1_TX (uint32_t) (DMAx_CHANNEL2_RMP | DMA_RMPCR1_CH2_USART1_TX) /*!< Remap USART1 Tx on DMA1 channel 2 */ -#define DMA1_CH2_USART2_TX (uint32_t) (DMAx_CHANNEL2_RMP | DMA_RMPCR1_CH2_USART2_TX) /*!< Remap USART2 Tx on DMA1 channel 2 */ -#define DMA1_CH2_USART3_TX (uint32_t) (DMAx_CHANNEL2_RMP | DMA_RMPCR1_CH2_USART3_TX) /*!< Remap USART3 Tx on DMA1 channel 2 */ -#define DMA1_CH2_USART4_TX (uint32_t) (DMAx_CHANNEL2_RMP | DMA_RMPCR1_CH2_USART4_TX) /*!< Remap USART4 Tx on DMA1 channel 2 */ -#define DMA1_CH2_USART5_TX (uint32_t) (DMAx_CHANNEL2_RMP | DMA_RMPCR1_CH2_USART5_TX) /*!< Remap USART5 Tx on DMA1 channel 2 */ -#define DMA1_CH2_USART6_TX (uint32_t) (DMAx_CHANNEL2_RMP | DMA_RMPCR1_CH2_USART6_TX) /*!< Remap USART6 Tx on DMA1 channel 2 */ -#define DMA1_CH2_USART7_TX (uint32_t) (DMAx_CHANNEL2_RMP | DMA_RMPCR1_CH2_USART7_TX) /*!< Remap USART7 Tx on DMA1 channel 2 */ -#define DMA1_CH2_USART8_TX (uint32_t) (DMAx_CHANNEL2_RMP | DMA_RMPCR1_CH2_USART8_TX) /*!< Remap USART8 Tx on DMA1 channel 2 */ -/* DMA1 - Channel 3 */ -#define DMA1_CH3_DEFAULT (uint32_t) (DMAx_CHANNEL3_RMP | DMA_RMPCR1_DEFAULT) /*!< Default remap position for DMAx */ -#define DMA1_CH3_TIM6_UP (uint32_t) (DMAx_CHANNEL3_RMP | DMA_RMPCR1_CH3_TIM6_UP) /*!< Remap TIM6 up on DMA1 channel 3 */ -#define DMA1_CH3_DAC_CH1 (uint32_t) (DMAx_CHANNEL3_RMP | DMA_RMPCR1_CH3_DAC_CH1) /*!< Remap DAC Channel 1on DMA1 channel 3 */ -#define DMA1_CH3_I2C1_RX (uint32_t) (DMAx_CHANNEL3_RMP | DMA_RMPCR1_CH3_I2C1_RX) /*!< Remap I2C1 Rx on DMA1 channel 3 */ -#define DMA1_CH3_SPI1_TX (uint32_t) (DMAx_CHANNEL3_RMP | DMA_RMPCR1_CH3_SPI1_TX) /*!< Remap SPI1 Tx on DMA1 channel 3 */ -#define DMA1_CH3_TIM1_CH2 (uint32_t) (DMAx_CHANNEL3_RMP | DMA_RMPCR1_CH3_TIM1_CH2) /*!< Remap TIM1 channel 2 on DMA1 channel 3 */ -#define DMA1_CH3_TIM2_CH2 (uint32_t) (DMAx_CHANNEL3_RMP | DMA_RMPCR1_CH3_TIM2_CH2) /*!< Remap TIM2 channel 2 on DMA1 channel 3 */ -#define DMA1_CH3_TIM16_CH1 (uint32_t) (DMAx_CHANNEL3_RMP | DMA_RMPCR1_CH3_TIM16_CH1) /*!< Remap TIM16 channel 1 on DMA1 channel 3 */ -#define DMA1_CH3_TIM16_UP (uint32_t) (DMAx_CHANNEL3_RMP | DMA_RMPCR1_CH3_TIM16_UP) /*!< Remap TIM16 up on DMA1 channel 3 */ -#define DMA1_CH3_USART1_RX (uint32_t) (DMAx_CHANNEL3_RMP | DMA_RMPCR1_CH3_USART1_RX) /*!< Remap USART1 Rx on DMA1 channel 3 */ -#define DMA1_CH3_USART2_RX (uint32_t) (DMAx_CHANNEL3_RMP | DMA_RMPCR1_CH3_USART2_RX) /*!< Remap USART2 Rx on DMA1 channel 3 */ -#define DMA1_CH3_USART3_RX (uint32_t) (DMAx_CHANNEL3_RMP | DMA_RMPCR1_CH3_USART3_RX) /*!< Remap USART3 Rx on DMA1 channel 3 */ -#define DMA1_CH3_USART4_RX (uint32_t) (DMAx_CHANNEL3_RMP | DMA_RMPCR1_CH3_USART4_RX) /*!< Remap USART4 Rx on DMA1 channel 3 */ -#define DMA1_CH3_USART5_RX (uint32_t) (DMAx_CHANNEL3_RMP | DMA_RMPCR1_CH3_USART5_RX) /*!< Remap USART5 Rx on DMA1 channel 3 */ -#define DMA1_CH3_USART6_RX (uint32_t) (DMAx_CHANNEL3_RMP | DMA_RMPCR1_CH3_USART6_RX) /*!< Remap USART6 Rx on DMA1 channel 3 */ -#define DMA1_CH3_USART7_RX (uint32_t) (DMAx_CHANNEL3_RMP | DMA_RMPCR1_CH3_USART7_RX) /*!< Remap USART7 Rx on DMA1 channel 3 */ -#define DMA1_CH3_USART8_RX (uint32_t) (DMAx_CHANNEL3_RMP | DMA_RMPCR1_CH3_USART8_RX) /*!< Remap USART8 Rx on DMA1 channel 3 */ -/* DMA1 - Channel 4 */ -#define DMA1_CH4_DEFAULT (uint32_t) (DMAx_CHANNEL4_RMP | DMA_RMPCR1_DEFAULT) /*!< Default remap position for DMA1 */ -#define DMA1_CH4_TIM7_UP (uint32_t) (DMAx_CHANNEL4_RMP | DMA_RMPCR1_CH4_TIM7_UP) /*!< Remap TIM7 up on DMA1 channel 4 */ -#define DMA1_CH4_DAC_CH2 (uint32_t) (DMAx_CHANNEL4_RMP | DMA_RMPCR1_CH4_DAC_CH2) /*!< Remap DAC Channel 2 on DMA1 channel 4 */ -#define DMA1_CH4_I2C2_TX (uint32_t) (DMAx_CHANNEL4_RMP | DMA_RMPCR1_CH4_I2C2_TX) /*!< Remap I2C2 Tx on DMA1 channel 4 */ -#define DMA1_CH4_SPI2_RX (uint32_t) (DMAx_CHANNEL4_RMP | DMA_RMPCR1_CH4_SPI2_RX) /*!< Remap SPI2 Rx on DMA1 channel 4 */ -#define DMA1_CH4_TIM2_CH4 (uint32_t) (DMAx_CHANNEL4_RMP | DMA_RMPCR1_CH4_TIM2_CH4) /*!< Remap TIM2 channel 4 on DMA1 channel 4 */ -#define DMA1_CH4_TIM3_CH1 (uint32_t) (DMAx_CHANNEL4_RMP | DMA_RMPCR1_CH4_TIM3_CH1) /*!< Remap TIM3 channel 1 on DMA1 channel 4 */ -#define DMA1_CH4_TIM3_TRIG (uint32_t) (DMAx_CHANNEL4_RMP | DMA_RMPCR1_CH4_TIM3_TRIG) /*!< Remap TIM3 Trig on DMA1 channel 4 */ -#define DMA1_CH4_TIM16_CH1 (uint32_t) (DMAx_CHANNEL4_RMP | DMA_RMPCR1_CH4_TIM16_CH1) /*!< Remap TIM16 channel 1 on DMA1 channel 4 */ -#define DMA1_CH4_TIM16_UP (uint32_t) (DMAx_CHANNEL4_RMP | DMA_RMPCR1_CH4_TIM16_UP) /*!< Remap TIM16 up on DMA1 channel 4 */ -#define DMA1_CH4_USART1_TX (uint32_t) (DMAx_CHANNEL4_RMP | DMA_RMPCR1_CH4_USART1_TX) /*!< Remap USART1 Tx on DMA1 channel 4 */ -#define DMA1_CH4_USART2_TX (uint32_t) (DMAx_CHANNEL4_RMP | DMA_RMPCR1_CH4_USART2_TX) /*!< Remap USART2 Tx on DMA1 channel 4 */ -#define DMA1_CH4_USART3_TX (uint32_t) (DMAx_CHANNEL4_RMP | DMA_RMPCR1_CH4_USART3_TX) /*!< Remap USART3 Tx on DMA1 channel 4 */ -#define DMA1_CH4_USART4_TX (uint32_t) (DMAx_CHANNEL4_RMP | DMA_RMPCR1_CH4_USART4_TX) /*!< Remap USART4 Tx on DMA1 channel 4 */ -#define DMA1_CH4_USART5_TX (uint32_t) (DMAx_CHANNEL4_RMP | DMA_RMPCR1_CH4_USART5_TX) /*!< Remap USART5 Tx on DMA1 channel 4 */ -#define DMA1_CH4_USART6_TX (uint32_t) (DMAx_CHANNEL4_RMP | DMA_RMPCR1_CH4_USART6_TX) /*!< Remap USART6 Tx on DMA1 channel 4 */ -#define DMA1_CH4_USART7_TX (uint32_t) (DMAx_CHANNEL4_RMP | DMA_RMPCR1_CH4_USART7_TX) /*!< Remap USART7 Tx on DMA1 channel 4 */ -#define DMA1_CH4_USART8_TX (uint32_t) (DMAx_CHANNEL4_RMP | DMA_RMPCR1_CH4_USART8_TX) /*!< Remap USART8 Tx on DMA1 channel 4 */ -/* DMA1 - Channel 5 */ -#define DMA1_CH5_DEFAULT (uint32_t) (DMAx_CHANNEL5_RMP | DMA_RMPCR1_DEFAULT) /*!< Default remap position for DMA1 */ -#define DMA1_CH5_I2C2_RX (uint32_t) (DMAx_CHANNEL5_RMP | DMA_RMPCR1_CH5_I2C2_RX) /*!< Remap I2C2 Rx on DMA1 channel 5 */ -#define DMA1_CH5_SPI2_TX (uint32_t) (DMAx_CHANNEL5_RMP | DMA_RMPCR1_CH5_SPI2_TX) /*!< Remap SPI1 Tx on DMA1 channel 5 */ -#define DMA1_CH5_TIM1_CH3 (uint32_t) (DMAx_CHANNEL5_RMP | DMA_RMPCR1_CH5_TIM1_CH3) /*!< Remap TIM1 channel 3 on DMA1 channel 5 */ -#define DMA1_CH5_USART1_RX (uint32_t) (DMAx_CHANNEL5_RMP | DMA_RMPCR1_CH5_USART1_RX) /*!< Remap USART1 Rx on DMA1 channel 5 */ -#define DMA1_CH5_USART2_RX (uint32_t) (DMAx_CHANNEL5_RMP | DMA_RMPCR1_CH5_USART2_RX) /*!< Remap USART2 Rx on DMA1 channel 5 */ -#define DMA1_CH5_USART3_RX (uint32_t) (DMAx_CHANNEL5_RMP | DMA_RMPCR1_CH5_USART3_RX) /*!< Remap USART3 Rx on DMA1 channel 5 */ -#define DMA1_CH5_USART4_RX (uint32_t) (DMAx_CHANNEL5_RMP | DMA_RMPCR1_CH5_USART4_RX) /*!< Remap USART4 Rx on DMA1 channel 5 */ -#define DMA1_CH5_USART5_RX (uint32_t) (DMAx_CHANNEL5_RMP | DMA_RMPCR1_CH5_USART5_RX) /*!< Remap USART5 Rx on DMA1 channel 5 */ -#define DMA1_CH5_USART6_RX (uint32_t) (DMAx_CHANNEL5_RMP | DMA_RMPCR1_CH5_USART6_RX) /*!< Remap USART6 Rx on DMA1 channel 5 */ -#define DMA1_CH5_USART7_RX (uint32_t) (DMAx_CHANNEL5_RMP | DMA_RMPCR1_CH5_USART7_RX) /*!< Remap USART7 Rx on DMA1 channel 5 */ -#define DMA1_CH5_USART8_RX (uint32_t) (DMAx_CHANNEL5_RMP | DMA_RMPCR1_CH5_USART8_RX) /*!< Remap USART8 Rx on DMA1 channel 5 */ -/* DMA1 - Channel 6 */ -#define DMA1_CH6_DEFAULT (uint32_t) (DMAx_CHANNEL6_RMP | DMA_RMPCR1_DEFAULT) /*!< Default remap position for DMA1 */ -#define DMA1_CH6_I2C1_TX (uint32_t) (DMAx_CHANNEL6_RMP | DMA_RMPCR1_CH6_I2C1_TX) /*!< Remap I2C1 Tx on DMA1 channel 6 */ -#define DMA1_CH6_SPI2_RX (uint32_t) (DMAx_CHANNEL6_RMP | DMA_RMPCR1_CH6_SPI2_RX) /*!< Remap SPI2 Rx on DMA1 channel 6 */ -#define DMA1_CH6_TIM1_CH1 (uint32_t) (DMAx_CHANNEL6_RMP | DMA_RMPCR1_CH6_TIM1_CH1) /*!< Remap TIM1 channel 1 on DMA1 channel 6 */ -#define DMA1_CH6_TIM1_CH2 (uint32_t) (DMAx_CHANNEL6_RMP | DMA_RMPCR1_CH6_TIM1_CH2) /*!< Remap TIM1 channel 2 on DMA1 channel 6 */ -#define DMA1_CH6_TIM1_CH3 (uint32_t) (DMAx_CHANNEL6_RMP | DMA_RMPCR1_CH6_TIM1_CH3) /*!< Remap TIM1 channel 3 on DMA1 channel 6 */ -#define DMA1_CH6_TIM3_CH1 (uint32_t) (DMAx_CHANNEL6_RMP | DMA_RMPCR1_CH6_TIM3_CH1) /*!< Remap TIM3 channel 1 on DMA1 channel 6 */ -#define DMA1_CH6_TIM3_TRIG (uint32_t) (DMAx_CHANNEL6_RMP | DMA_RMPCR1_CH6_TIM3_TRIG) /*!< Remap TIM3 Trig on DMA1 channel 6 */ -#define DMA1_CH6_TIM16_CH1 (uint32_t) (DMAx_CHANNEL6_RMP | DMA_RMPCR1_CH6_TIM16_CH1) /*!< Remap TIM16 channel 1 on DMA1 channel 6 */ -#define DMA1_CH6_TIM16_UP (uint32_t) (DMAx_CHANNEL6_RMP | DMA_RMPCR1_CH6_TIM16_UP) /*!< Remap TIM16 up on DMA1 channel 6 */ -#define DMA1_CH6_USART1_RX (uint32_t) (DMAx_CHANNEL6_RMP | DMA_RMPCR1_CH6_USART1_RX) /*!< Remap USART1 Rx on DMA1 channel 6 */ -#define DMA1_CH6_USART2_RX (uint32_t) (DMAx_CHANNEL6_RMP | DMA_RMPCR1_CH6_USART2_RX) /*!< Remap USART2 Rx on DMA1 channel 6 */ -#define DMA1_CH6_USART3_RX (uint32_t) (DMAx_CHANNEL6_RMP | DMA_RMPCR1_CH6_USART3_RX) /*!< Remap USART3 Rx on DMA1 channel 6 */ -#define DMA1_CH6_USART4_RX (uint32_t) (DMAx_CHANNEL6_RMP | DMA_RMPCR1_CH6_USART4_RX) /*!< Remap USART4 Rx on DMA1 channel 6 */ -#define DMA1_CH6_USART5_RX (uint32_t) (DMAx_CHANNEL6_RMP | DMA_RMPCR1_CH6_USART5_RX) /*!< Remap USART5 Rx on DMA1 channel 6 */ -#define DMA1_CH6_USART6_RX (uint32_t) (DMAx_CHANNEL6_RMP | DMA_RMPCR1_CH6_USART6_RX) /*!< Remap USART6 Rx on DMA1 channel 6 */ -#define DMA1_CH6_USART7_RX (uint32_t) (DMAx_CHANNEL6_RMP | DMA_RMPCR1_CH6_USART7_RX) /*!< Remap USART7 Rx on DMA1 channel 6 */ -#define DMA1_CH6_USART8_RX (uint32_t) (DMAx_CHANNEL6_RMP | DMA_RMPCR1_CH6_USART8_RX) /*!< Remap USART8 Rx on DMA1 channel 6 */ -/* DMA1 - Channel 7 */ -#define DMA1_CH7_DEFAULT (uint32_t) (DMAx_CHANNEL7_RMP | DMA_RMPCR1_DEFAULT) /*!< Default remap position for DMA1 */ -#define DMA1_CH7_I2C1_RX (uint32_t) (DMAx_CHANNEL7_RMP | DMA_RMPCR1_CH7_I2C1_RX) /*!< Remap I2C1 Rx on DMA1 channel 7 */ -#define DMA1_CH7_SPI2_TX (uint32_t) (DMAx_CHANNEL7_RMP | DMA_RMPCR1_CH7_SPI2_TX) /*!< Remap SPI2 Tx on DMA1 channel 7 */ -#define DMA1_CH7_TIM2_CH2 (uint32_t) (DMAx_CHANNEL7_RMP | DMA_RMPCR1_CH7_TIM2_CH2) /*!< Remap TIM2 channel 2 on DMA1 channel 7 */ -#define DMA1_CH7_TIM2_CH4 (uint32_t) (DMAx_CHANNEL7_RMP | DMA_RMPCR1_CH7_TIM2_CH4) /*!< Remap TIM2 channel 4 on DMA1 channel 7 */ -#define DMA1_CH7_TIM17_CH1 (uint32_t) (DMAx_CHANNEL7_RMP | DMA_RMPCR1_CH7_TIM17_CH1) /*!< Remap TIM17 channel 1 on DMA1 channel 7 */ -#define DMA1_CH7_TIM17_UP (uint32_t) (DMAx_CHANNEL7_RMP | DMA_RMPCR1_CH7_TIM17_UP) /*!< Remap TIM17 up on DMA1 channel 7 */ -#define DMA1_CH7_USART1_TX (uint32_t) (DMAx_CHANNEL7_RMP | DMA_RMPCR1_CH7_USART1_TX) /*!< Remap USART1 Tx on DMA1 channel 7 */ -#define DMA1_CH7_USART2_TX (uint32_t) (DMAx_CHANNEL7_RMP | DMA_RMPCR1_CH7_USART2_TX) /*!< Remap USART2 Tx on DMA1 channel 7 */ -#define DMA1_CH7_USART3_TX (uint32_t) (DMAx_CHANNEL7_RMP | DMA_RMPCR1_CH7_USART3_TX) /*!< Remap USART3 Tx on DMA1 channel 7 */ -#define DMA1_CH7_USART4_TX (uint32_t) (DMAx_CHANNEL7_RMP | DMA_RMPCR1_CH7_USART4_TX) /*!< Remap USART4 Tx on DMA1 channel 7 */ -#define DMA1_CH7_USART5_TX (uint32_t) (DMAx_CHANNEL7_RMP | DMA_RMPCR1_CH7_USART5_TX) /*!< Remap USART5 Tx on DMA1 channel 7 */ -#define DMA1_CH7_USART6_TX (uint32_t) (DMAx_CHANNEL7_RMP | DMA_RMPCR1_CH7_USART6_TX) /*!< Remap USART6 Tx on DMA1 channel 7 */ -#define DMA1_CH7_USART7_TX (uint32_t) (DMAx_CHANNEL7_RMP | DMA_RMPCR1_CH7_USART7_TX) /*!< Remap USART7 Tx on DMA1 channel 7 */ -#define DMA1_CH7_USART8_TX (uint32_t) (DMAx_CHANNEL7_RMP | DMA_RMPCR1_CH7_USART8_TX) /*!< Remap USART8 Tx on DMA1 channel 7 */ - -#define IS_DMA1_REMAP(REMAP) ((REMAP == DMA1_CH1_DEFAULT) ||\ - (REMAP == DMA1_CH1_ADC) ||\ - (REMAP == DMA1_CH1_TIM17_CH1) ||\ - (REMAP == DMA1_CH1_TIM17_UP) ||\ - (REMAP == DMA1_CH1_USART1_RX) ||\ - (REMAP == DMA1_CH1_USART2_RX) ||\ - (REMAP == DMA1_CH1_USART3_RX) ||\ - (REMAP == DMA1_CH1_USART4_RX) ||\ - (REMAP == DMA1_CH1_USART5_RX) ||\ - (REMAP == DMA1_CH1_USART6_RX) ||\ - (REMAP == DMA1_CH1_USART7_RX) ||\ - (REMAP == DMA1_CH1_USART8_RX) ||\ - (REMAP == DMA1_CH2_DEFAULT) ||\ - (REMAP == DMA1_CH2_ADC) ||\ - (REMAP == DMA1_CH2_I2C1_TX) ||\ - (REMAP == DMA1_CH2_SPI1_RX) ||\ - (REMAP == DMA1_CH2_TIM1_CH1) ||\ - (REMAP == DMA1_CH2_I2C1_TX) ||\ - (REMAP == DMA1_CH2_TIM17_CH1) ||\ - (REMAP == DMA1_CH2_TIM17_UP) ||\ - (REMAP == DMA1_CH2_USART1_TX) ||\ - (REMAP == DMA1_CH2_USART2_TX) ||\ - (REMAP == DMA1_CH2_USART3_TX) ||\ - (REMAP == DMA1_CH2_USART4_TX) ||\ - (REMAP == DMA1_CH2_USART5_TX) ||\ - (REMAP == DMA1_CH2_USART6_TX) ||\ - (REMAP == DMA1_CH2_USART7_TX) ||\ - (REMAP == DMA1_CH2_USART8_TX) ||\ - (REMAP == DMA1_CH3_DEFAULT) ||\ - (REMAP == DMA1_CH3_TIM6_UP) ||\ - (REMAP == DMA1_CH3_DAC_CH1) ||\ - (REMAP == DMA1_CH3_I2C1_RX) ||\ - (REMAP == DMA1_CH3_SPI1_TX) ||\ - (REMAP == DMA1_CH3_TIM1_CH2) ||\ - (REMAP == DMA1_CH3_TIM2_CH2) ||\ - (REMAP == DMA1_CH3_TIM16_CH1) ||\ - (REMAP == DMA1_CH3_TIM16_UP) ||\ - (REMAP == DMA1_CH3_USART1_RX) ||\ - (REMAP == DMA1_CH3_USART2_RX) ||\ - (REMAP == DMA1_CH3_USART3_RX) ||\ - (REMAP == DMA1_CH3_USART4_RX) ||\ - (REMAP == DMA1_CH3_USART5_RX) ||\ - (REMAP == DMA1_CH3_USART6_RX) ||\ - (REMAP == DMA1_CH3_USART7_RX) ||\ - (REMAP == DMA1_CH3_USART8_RX) ||\ - (REMAP == DMA1_CH4_DEFAULT) ||\ - (REMAP == DMA1_CH4_TIM7_UP) ||\ - (REMAP == DMA1_CH4_DAC_CH2) ||\ - (REMAP == DMA1_CH4_I2C2_TX) ||\ - (REMAP == DMA1_CH4_SPI2_RX) ||\ - (REMAP == DMA1_CH4_TIM2_CH4) ||\ - (REMAP == DMA1_CH4_TIM3_CH1) ||\ - (REMAP == DMA1_CH4_TIM3_TRIG) ||\ - (REMAP == DMA1_CH4_TIM16_CH1) ||\ - (REMAP == DMA1_CH4_TIM16_UP) ||\ - (REMAP == DMA1_CH4_USART1_TX) ||\ - (REMAP == DMA1_CH4_USART2_TX) ||\ - (REMAP == DMA1_CH4_USART3_TX) ||\ - (REMAP == DMA1_CH4_USART4_TX) ||\ - (REMAP == DMA1_CH4_USART5_TX) ||\ - (REMAP == DMA1_CH4_USART6_TX) ||\ - (REMAP == DMA1_CH4_USART7_TX) ||\ - (REMAP == DMA1_CH4_USART8_TX) ||\ - (REMAP == DMA1_CH5_DEFAULT) ||\ - (REMAP == DMA1_CH5_I2C2_RX) ||\ - (REMAP == DMA1_CH5_SPI2_TX) ||\ - (REMAP == DMA1_CH5_TIM1_CH3) ||\ - (REMAP == DMA1_CH5_USART1_RX) ||\ - (REMAP == DMA1_CH5_USART2_RX) ||\ - (REMAP == DMA1_CH5_USART3_RX) ||\ - (REMAP == DMA1_CH5_USART4_RX) ||\ - (REMAP == DMA1_CH5_USART5_RX) ||\ - (REMAP == DMA1_CH5_USART6_RX) ||\ - (REMAP == DMA1_CH5_USART7_RX) ||\ - (REMAP == DMA1_CH5_USART8_RX) ||\ - (REMAP == DMA1_CH6_DEFAULT) ||\ - (REMAP == DMA1_CH6_I2C1_TX) ||\ - (REMAP == DMA1_CH6_SPI2_RX) ||\ - (REMAP == DMA1_CH6_TIM1_CH1) ||\ - (REMAP == DMA1_CH6_TIM1_CH2) ||\ - (REMAP == DMA1_CH6_TIM1_CH3) ||\ - (REMAP == DMA1_CH6_TIM3_CH1) ||\ - (REMAP == DMA1_CH6_TIM3_TRIG) ||\ - (REMAP == DMA1_CH6_TIM16_CH1) ||\ - (REMAP == DMA1_CH6_TIM16_UP) ||\ - (REMAP == DMA1_CH6_USART1_RX) ||\ - (REMAP == DMA1_CH6_USART2_RX) ||\ - (REMAP == DMA1_CH6_USART3_RX) ||\ - (REMAP == DMA1_CH6_USART4_RX) ||\ - (REMAP == DMA1_CH6_USART5_RX) ||\ - (REMAP == DMA1_CH6_USART6_RX) ||\ - (REMAP == DMA1_CH6_USART7_RX) ||\ - (REMAP == DMA1_CH6_USART8_RX) ||\ - (REMAP == DMA1_CH7_DEFAULT) ||\ - (REMAP == DMA1_CH7_I2C1_RX) ||\ - (REMAP == DMA1_CH7_SPI2_TX) ||\ - (REMAP == DMA1_CH7_TIM2_CH2) ||\ - (REMAP == DMA1_CH7_TIM2_CH4) ||\ - (REMAP == DMA1_CH7_TIM17_CH1) ||\ - (REMAP == DMA1_CH7_TIM17_UP) ||\ - (REMAP == DMA1_CH7_USART1_TX) ||\ - (REMAP == DMA1_CH7_USART2_TX) ||\ - (REMAP == DMA1_CH7_USART3_TX) ||\ - (REMAP == DMA1_CH7_USART4_TX) ||\ - (REMAP == DMA1_CH7_USART5_TX) ||\ - (REMAP == DMA1_CH7_USART6_TX) ||\ - (REMAP == DMA1_CH7_USART7_TX) ||\ - (REMAP == DMA1_CH7_USART8_TX)) - -/****************** DMA2 remap bit field definition********************/ -/* DMA2 - Channel 1 */ -#define DMA2_CH1_DEFAULT (uint32_t) (DMAx_CHANNEL1_RMP | DMA_RMPCR2_DEFAULT) /*!< Default remap position for DMA2 */ -#define DMA2_CH1_I2C2_TX (uint32_t) (DMAx_CHANNEL1_RMP | DMA_RMPCR2_CH1_I2C2_TX) /*!< Remap I2C2 TX on DMA2 channel 1 */ -#define DMA2_CH1_USART1_TX (uint32_t) (DMAx_CHANNEL1_RMP | DMA_RMPCR2_CH1_USART1_TX) /*!< Remap USART1 Tx on DMA2 channel 1 */ -#define DMA2_CH1_USART2_TX (uint32_t) (DMAx_CHANNEL1_RMP | DMA_RMPCR2_CH1_USART2_TX) /*!< Remap USART2 Tx on DMA2 channel 1 */ -#define DMA2_CH1_USART3_TX (uint32_t) (DMAx_CHANNEL1_RMP | DMA_RMPCR2_CH1_USART3_TX) /*!< Remap USART3 Tx on DMA2 channel 1 */ -#define DMA2_CH1_USART4_TX (uint32_t) (DMAx_CHANNEL1_RMP | DMA_RMPCR2_CH1_USART4_TX) /*!< Remap USART4 Tx on DMA2 channel 1 */ -#define DMA2_CH1_USART5_TX (uint32_t) (DMAx_CHANNEL1_RMP | DMA_RMPCR2_CH1_USART5_TX) /*!< Remap USART5 Tx on DMA2 channel 1 */ -#define DMA2_CH1_USART6_TX (uint32_t) (DMAx_CHANNEL1_RMP | DMA_RMPCR2_CH1_USART6_TX) /*!< Remap USART6 Tx on DMA2 channel 1 */ -#define DMA2_CH1_USART7_TX (uint32_t) (DMAx_CHANNEL1_RMP | DMA_RMPCR2_CH1_USART7_TX) /*!< Remap USART7 Tx on DMA2 channel 1 */ -#define DMA2_CH1_USART8_TX (uint32_t) (DMAx_CHANNEL1_RMP | DMA_RMPCR2_CH1_USART8_TX) /*!< Remap USART8 Tx on DMA2 channel 1 */ -/* DMA2 - Channel 2 */ -#define DMA2_CH2_DEFAULT (uint32_t) (DMAx_CHANNEL2_RMP | DMA_RMPCR2_DEFAULT) /*!< Default remap position for DMA2 */ -#define DMA2_CH2_I2C2_RX (uint32_t) (DMAx_CHANNEL2_RMP | DMA_RMPCR2_CH2_I2C2_RX) /*!< Remap I2C2 Rx on DMA2 channel 2 */ -#define DMA2_CH2_USART1_RX (uint32_t) (DMAx_CHANNEL2_RMP | DMA_RMPCR2_CH2_USART1_RX) /*!< Remap USART1 Rx on DMA2 channel 2 */ -#define DMA2_CH2_USART2_RX (uint32_t) (DMAx_CHANNEL2_RMP | DMA_RMPCR2_CH2_USART2_RX) /*!< Remap USART2 Rx on DMA2 channel 2 */ -#define DMA2_CH2_USART3_RX (uint32_t) (DMAx_CHANNEL2_RMP | DMA_RMPCR2_CH2_USART3_RX) /*!< Remap USART3 Rx on DMA2 channel 2 */ -#define DMA2_CH2_USART4_RX (uint32_t) (DMAx_CHANNEL2_RMP | DMA_RMPCR2_CH2_USART4_RX) /*!< Remap USART4 Rx on DMA2 channel 2 */ -#define DMA2_CH2_USART5_RX (uint32_t) (DMAx_CHANNEL2_RMP | DMA_RMPCR2_CH2_USART5_RX) /*!< Remap USART5 Rx on DMA2 channel 2 */ -#define DMA2_CH2_USART6_RX (uint32_t) (DMAx_CHANNEL2_RMP | DMA_RMPCR2_CH2_USART6_RX) /*!< Remap USART6 Rx on DMA2 channel 2 */ -#define DMA2_CH2_USART7_RX (uint32_t) (DMAx_CHANNEL2_RMP | DMA_RMPCR2_CH2_USART7_RX) /*!< Remap USART7 Rx on DMA2 channel 2 */ -#define DMA2_CH2_USART8_RX (uint32_t) (DMAx_CHANNEL2_RMP | DMA_RMPCR2_CH2_USART8_RX) /*!< Remap USART8 Rx on DMA2 channel 2 */ -/* DMA2 - Channel 3 */ -#define DMA2_CH3_DEFAULT (uint32_t) (DMAx_CHANNEL3_RMP | DMA_RMPCR2_DEFAULT) /*!< Default remap position for DMA2 */ -#define DMA2_CH3_TIM6_UP (uint32_t) (DMAx_CHANNEL3_RMP | DMA_RMPCR2_CH3_TIM6_UP) /*!< Remap TIM6 up on DMA2 channel 3 */ -#define DMA2_CH3_DAC_CH1 (uint32_t) (DMAx_CHANNEL3_RMP | DMA_RMPCR2_CH3_DAC_CH1) /*!< Remap DAC channel 1 on DMA2 channel 3 */ -#define DMA2_CH3_SPI1_RX (uint32_t) (DMAx_CHANNEL3_RMP | DMA_RMPCR2_CH3_SPI1_RX) /*!< Remap SPI1 Rx on DMA2 channel 3 */ -#define DMA2_CH3_USART1_RX (uint32_t) (DMAx_CHANNEL3_RMP | DMA_RMPCR2_CH3_USART1_RX) /*!< Remap USART1 Rx on DMA2 channel 3 */ -#define DMA2_CH3_USART2_RX (uint32_t) (DMAx_CHANNEL3_RMP | DMA_RMPCR2_CH3_USART2_RX) /*!< Remap USART2 Rx on DMA2 channel 3 */ -#define DMA2_CH3_USART3_RX (uint32_t) (DMAx_CHANNEL3_RMP | DMA_RMPCR2_CH3_USART3_RX) /*!< Remap USART3 Rx on DMA2 channel 3 */ -#define DMA2_CH3_USART4_RX (uint32_t) (DMAx_CHANNEL3_RMP | DMA_RMPCR2_CH3_USART4_RX) /*!< Remap USART4 Rx on DMA2 channel 3 */ -#define DMA2_CH3_USART5_RX (uint32_t) (DMAx_CHANNEL3_RMP | DMA_RMPCR2_CH3_USART5_RX) /*!< Remap USART5 Rx on DMA2 channel 3 */ -#define DMA2_CH3_USART6_RX (uint32_t) (DMAx_CHANNEL3_RMP | DMA_RMPCR2_CH3_USART6_RX) /*!< Remap USART6 Rx on DMA2 channel 3 */ -#define DMA2_CH3_USART7_RX (uint32_t) (DMAx_CHANNEL3_RMP | DMA_RMPCR2_CH3_USART7_RX) /*!< Remap USART7 Rx on DMA2 channel 3 */ -#define DMA2_CH3_USART8_RX (uint32_t) (DMAx_CHANNEL3_RMP | DMA_RMPCR2_CH3_USART8_RX) /*!< Remap USART8 Rx on DMA2 channel 3 */ -/* DMA2 - Channel 4 */ -#define DMA2_CH4_DEFAULT (uint32_t) (DMAx_CHANNEL4_RMP | DMA_RMPCR2_DEFAULT) /*!< Default remap position for DMA2 */ -#define DMA2_CH4_TIM7_UP (uint32_t) (DMAx_CHANNEL4_RMP | DMA_RMPCR2_CH4_TIM7_UP) /*!< Remap TIM7 up on DMA2 channel 4 */ -#define DMA2_CH4_DAC_CH2 (uint32_t) (DMAx_CHANNEL4_RMP | DMA_RMPCR2_CH4_DAC_CH2) /*!< Remap DAC channel 2 on DMA2 channel 4 */ -#define DMA2_CH4_SPI1_TX (uint32_t) (DMAx_CHANNEL4_RMP | DMA_RMPCR2_CH4_SPI1_TX) /*!< Remap SPI1 Tx on DMA2 channel 4 */ -#define DMA2_CH4_USART1_TX (uint32_t) (DMAx_CHANNEL4_RMP | DMA_RMPCR2_CH4_USART1_TX) /*!< Remap USART1 Tx on DMA2 channel 4 */ -#define DMA2_CH4_USART2_TX (uint32_t) (DMAx_CHANNEL4_RMP | DMA_RMPCR2_CH4_USART2_TX) /*!< Remap USART2 Tx on DMA2 channel 4 */ -#define DMA2_CH4_USART3_TX (uint32_t) (DMAx_CHANNEL4_RMP | DMA_RMPCR2_CH4_USART3_TX) /*!< Remap USART3 Tx on DMA2 channel 4 */ -#define DMA2_CH4_USART4_TX (uint32_t) (DMAx_CHANNEL4_RMP | DMA_RMPCR2_CH4_USART4_TX) /*!< Remap USART4 Tx on DMA2 channel 4 */ -#define DMA2_CH4_USART5_TX (uint32_t) (DMAx_CHANNEL4_RMP | DMA_RMPCR2_CH4_USART5_TX) /*!< Remap USART5 Tx on DMA2 channel 4 */ -#define DMA2_CH4_USART6_TX (uint32_t) (DMAx_CHANNEL4_RMP | DMA_RMPCR2_CH4_USART6_TX) /*!< Remap USART6 Tx on DMA2 channel 4 */ -#define DMA2_CH4_USART7_TX (uint32_t) (DMAx_CHANNEL4_RMP | DMA_RMPCR2_CH4_USART7_TX) /*!< Remap USART7 Tx on DMA2 channel 4 */ -#define DMA2_CH4_USART8_TX (uint32_t) (DMAx_CHANNEL4_RMP | DMA_RMPCR2_CH4_USART8_TX) /*!< Remap USART8 Tx on DMA2 channel 4 */ -/* DMA2 - Channel 5 */ -#define DMA2_CH5_DEFAULT (uint32_t) (DMAx_CHANNEL5_RMP | DMA_RMPCR2_DEFAULT) /*!< Default remap position for DMA2 */ -#define DMA2_CH5_ADC (uint32_t) (DMAx_CHANNEL5_RMP | DMA_RMPCR2_CH5_ADC) /*!< Remap ADC on DMA2 channel 5 */ -#define DMA2_CH5_USART1_TX (uint32_t) (DMAx_CHANNEL5_RMP | DMA_RMPCR2_CH5_USART1_TX) /*!< Remap USART1 Tx on DMA2 channel 5 */ -#define DMA2_CH5_USART2_TX (uint32_t) (DMAx_CHANNEL5_RMP | DMA_RMPCR2_CH5_USART2_TX) /*!< Remap USART2 Tx on DMA2 channel 5 */ -#define DMA2_CH5_USART3_TX (uint32_t) (DMAx_CHANNEL5_RMP | DMA_RMPCR2_CH5_USART3_TX) /*!< Remap USART3 Tx on DMA2 channel 5 */ -#define DMA2_CH5_USART4_TX (uint32_t) (DMAx_CHANNEL5_RMP | DMA_RMPCR2_CH5_USART4_TX) /*!< Remap USART4 Tx on DMA2 channel 5 */ -#define DMA2_CH5_USART5_TX (uint32_t) (DMAx_CHANNEL5_RMP | DMA_RMPCR2_CH5_USART5_TX) /*!< Remap USART5 Tx on DMA2 channel 5 */ -#define DMA2_CH5_USART6_TX (uint32_t) (DMAx_CHANNEL5_RMP | DMA_RMPCR2_CH5_USART6_TX) /*!< Remap USART6 Tx on DMA2 channel 5 */ -#define DMA2_CH5_USART7_TX (uint32_t) (DMAx_CHANNEL5_RMP | DMA_RMPCR2_CH5_USART7_TX) /*!< Remap USART7 Tx on DMA2 channel 5 */ -#define DMA2_CH5_USART8_TX (uint32_t) (DMAx_CHANNEL5_RMP | DMA_RMPCR2_CH5_USART8_TX) /*!< Remap USART8 Tx on DMA2 channel 5 */ - -#define IS_DMA2_REMAP(REMAP) ((REMAP == DMA2_CH1_DEFAULT) ||\ - (REMAP == DMA2_CH1_I2C2_TX) ||\ - (REMAP == DMA2_CH1_USART1_TX) ||\ - (REMAP == DMA2_CH1_USART2_TX) ||\ - (REMAP == DMA2_CH1_USART3_TX) ||\ - (REMAP == DMA2_CH1_USART4_TX) ||\ - (REMAP == DMA2_CH1_USART5_TX) ||\ - (REMAP == DMA2_CH1_USART6_TX) ||\ - (REMAP == DMA2_CH1_USART7_TX) ||\ - (REMAP == DMA2_CH1_USART8_TX) ||\ - (REMAP == DMA2_CH2_DEFAULT) ||\ - (REMAP == DMA2_CH2_I2C2_RX) ||\ - (REMAP == DMA2_CH2_USART1_RX) ||\ - (REMAP == DMA2_CH2_USART2_RX) ||\ - (REMAP == DMA2_CH2_USART3_RX) ||\ - (REMAP == DMA2_CH2_USART4_RX) ||\ - (REMAP == DMA2_CH2_USART5_RX) ||\ - (REMAP == DMA2_CH2_USART6_RX) ||\ - (REMAP == DMA2_CH2_USART7_RX) ||\ - (REMAP == DMA2_CH2_USART8_RX) ||\ - (REMAP == DMA2_CH3_DEFAULT) ||\ - (REMAP == DMA2_CH3_TIM6_UP) ||\ - (REMAP == DMA2_CH3_DAC_CH1) ||\ - (REMAP == DMA2_CH3_SPI1_RX) ||\ - (REMAP == DMA2_CH3_USART1_RX) ||\ - (REMAP == DMA2_CH3_USART2_RX) ||\ - (REMAP == DMA2_CH3_USART3_RX) ||\ - (REMAP == DMA2_CH3_USART4_RX) ||\ - (REMAP == DMA2_CH3_USART5_RX) ||\ - (REMAP == DMA2_CH3_USART6_RX) ||\ - (REMAP == DMA2_CH3_USART7_RX) ||\ - (REMAP == DMA2_CH3_USART8_RX) ||\ - (REMAP == DMA2_CH4_DEFAULT) ||\ - (REMAP == DMA2_CH4_TIM7_UP) ||\ - (REMAP == DMA2_CH4_DAC_CH2) ||\ - (REMAP == DMA2_CH4_SPI1_TX) ||\ - (REMAP == DMA2_CH4_USART1_TX) ||\ - (REMAP == DMA2_CH4_USART2_TX) ||\ - (REMAP == DMA2_CH4_USART3_TX) ||\ - (REMAP == DMA2_CH4_USART4_TX) ||\ - (REMAP == DMA2_CH4_USART5_TX) ||\ - (REMAP == DMA2_CH4_USART6_TX) ||\ - (REMAP == DMA2_CH4_USART7_TX) ||\ - (REMAP == DMA2_CH4_USART8_TX) ||\ - (REMAP == DMA2_CH5_DEFAULT) ||\ - (REMAP == DMA2_CH5_ADC) ||\ - (REMAP == DMA2_CH5_USART1_TX) ||\ - (REMAP == DMA2_CH5_USART2_TX) ||\ - (REMAP == DMA2_CH5_USART3_TX) ||\ - (REMAP == DMA2_CH5_USART4_TX) ||\ - (REMAP == DMA2_CH5_USART5_TX) ||\ - (REMAP == DMA2_CH5_USART6_TX) ||\ - (REMAP == DMA2_CH5_USART7_TX) ||\ - (REMAP == DMA2_CH5_USART8_TX )) - -/** - * @} - */ - -/** @defgroup DMA_interrupts_definition - * @{ - */ - -#define DMA_IT_TC DMA_CCR_TCIE -#define DMA_IT_HT DMA_CCR_HTIE -#define DMA_IT_TE DMA_CCR_TEIE - -#define IS_DMA_CONFIG_IT(IT) ((((IT) & 0xFFFFFFF1) == 0x00) && ((IT) != 0x00)) - -#define DMA1_IT_GL1 DMA_ISR_GIF1 -#define DMA1_IT_TC1 DMA_ISR_TCIF1 -#define DMA1_IT_HT1 DMA_ISR_HTIF1 -#define DMA1_IT_TE1 DMA_ISR_TEIF1 -#define DMA1_IT_GL2 DMA_ISR_GIF2 -#define DMA1_IT_TC2 DMA_ISR_TCIF2 -#define DMA1_IT_HT2 DMA_ISR_HTIF2 -#define DMA1_IT_TE2 DMA_ISR_TEIF2 -#define DMA1_IT_GL3 DMA_ISR_GIF3 -#define DMA1_IT_TC3 DMA_ISR_TCIF3 -#define DMA1_IT_HT3 DMA_ISR_HTIF3 -#define DMA1_IT_TE3 DMA_ISR_TEIF3 -#define DMA1_IT_GL4 DMA_ISR_GIF4 -#define DMA1_IT_TC4 DMA_ISR_TCIF4 -#define DMA1_IT_HT4 DMA_ISR_HTIF4 -#define DMA1_IT_TE4 DMA_ISR_TEIF4 -#define DMA1_IT_GL5 DMA_ISR_GIF5 -#define DMA1_IT_TC5 DMA_ISR_TCIF5 -#define DMA1_IT_HT5 DMA_ISR_HTIF5 -#define DMA1_IT_TE5 DMA_ISR_TEIF5 -#define DMA1_IT_GL6 DMA_ISR_GIF6 -#define DMA1_IT_TC6 DMA_ISR_TCIF6 -#define DMA1_IT_HT6 DMA_ISR_HTIF6 -#define DMA1_IT_TE6 DMA_ISR_TEIF6 -#define DMA1_IT_GL7 DMA_ISR_GIF7 -#define DMA1_IT_TC7 DMA_ISR_TCIF7 -#define DMA1_IT_HT7 DMA_ISR_HTIF7 -#define DMA1_IT_TE7 DMA_ISR_TEIF7 - -#define DMA2_IT_GL1 ((uint32_t)0x10000001) -#define DMA2_IT_TC1 ((uint32_t)0x10000002) -#define DMA2_IT_HT1 ((uint32_t)0x10000004) -#define DMA2_IT_TE1 ((uint32_t)0x10000008) -#define DMA2_IT_GL2 ((uint32_t)0x10000010) -#define DMA2_IT_TC2 ((uint32_t)0x10000020) -#define DMA2_IT_HT2 ((uint32_t)0x10000040) -#define DMA2_IT_TE2 ((uint32_t)0x10000080) -#define DMA2_IT_GL3 ((uint32_t)0x10000100) -#define DMA2_IT_TC3 ((uint32_t)0x10000200) -#define DMA2_IT_HT3 ((uint32_t)0x10000400) -#define DMA2_IT_TE3 ((uint32_t)0x10000800) -#define DMA2_IT_GL4 ((uint32_t)0x10001000) -#define DMA2_IT_TC4 ((uint32_t)0x10002000) -#define DMA2_IT_HT4 ((uint32_t)0x10004000) -#define DMA2_IT_TE4 ((uint32_t)0x10008000) -#define DMA2_IT_GL5 ((uint32_t)0x10010000) -#define DMA2_IT_TC5 ((uint32_t)0x10020000) -#define DMA2_IT_HT5 ((uint32_t)0x10040000) -#define DMA2_IT_TE5 ((uint32_t)0x10080000) - -#define IS_DMA_CLEAR_IT(IT) (((((IT) & 0xF0000000) == 0x00) || (((IT) & 0xEFF00000) == 0x00)) && ((IT) != 0x00)) - -#define IS_DMA_GET_IT(IT) (((IT) == DMA1_IT_GL1) || ((IT) == DMA1_IT_TC1) || \ - ((IT) == DMA1_IT_HT1) || ((IT) == DMA1_IT_TE1) || \ - ((IT) == DMA1_IT_GL2) || ((IT) == DMA1_IT_TC2) || \ - ((IT) == DMA1_IT_HT2) || ((IT) == DMA1_IT_TE2) || \ - ((IT) == DMA1_IT_GL3) || ((IT) == DMA1_IT_TC3) || \ - ((IT) == DMA1_IT_HT3) || ((IT) == DMA1_IT_TE3) || \ - ((IT) == DMA1_IT_GL4) || ((IT) == DMA1_IT_TC4) || \ - ((IT) == DMA1_IT_HT4) || ((IT) == DMA1_IT_TE4) || \ - ((IT) == DMA1_IT_GL5) || ((IT) == DMA1_IT_TC5) || \ - ((IT) == DMA1_IT_HT5) || ((IT) == DMA1_IT_TE5) || \ - ((IT) == DMA1_IT_GL6) || ((IT) == DMA1_IT_TC6) || \ - ((IT) == DMA1_IT_HT6) || ((IT) == DMA1_IT_TE6) || \ - ((IT) == DMA1_IT_GL7) || ((IT) == DMA1_IT_TC7) || \ - ((IT) == DMA1_IT_HT7) || ((IT) == DMA1_IT_TE7) || \ - ((IT) == DMA2_IT_GL1) || ((IT) == DMA2_IT_TC1) || \ - ((IT) == DMA2_IT_HT1) || ((IT) == DMA2_IT_TE1) || \ - ((IT) == DMA2_IT_GL2) || ((IT) == DMA2_IT_TC2) || \ - ((IT) == DMA2_IT_HT2) || ((IT) == DMA2_IT_TE2) || \ - ((IT) == DMA2_IT_GL3) || ((IT) == DMA2_IT_TC3) || \ - ((IT) == DMA2_IT_HT3) || ((IT) == DMA2_IT_TE3) || \ - ((IT) == DMA2_IT_GL4) || ((IT) == DMA2_IT_TC4) || \ - ((IT) == DMA2_IT_HT4) || ((IT) == DMA2_IT_TE4) || \ - ((IT) == DMA2_IT_GL5) || ((IT) == DMA2_IT_TC5) || \ - ((IT) == DMA2_IT_HT5) || ((IT) == DMA2_IT_TE5)) - -/** - * @} - */ - -/** @defgroup DMA_flags_definition - * @{ - */ -#define DMA1_FLAG_GL1 DMA_ISR_GIF1 -#define DMA1_FLAG_TC1 DMA_ISR_TCIF1 -#define DMA1_FLAG_HT1 DMA_ISR_HTIF1 -#define DMA1_FLAG_TE1 DMA_ISR_TEIF1 -#define DMA1_FLAG_GL2 DMA_ISR_GIF2 -#define DMA1_FLAG_TC2 DMA_ISR_TCIF2 -#define DMA1_FLAG_HT2 DMA_ISR_HTIF2 -#define DMA1_FLAG_TE2 DMA_ISR_TEIF2 -#define DMA1_FLAG_GL3 DMA_ISR_GIF3 -#define DMA1_FLAG_TC3 DMA_ISR_TCIF3 -#define DMA1_FLAG_HT3 DMA_ISR_HTIF3 -#define DMA1_FLAG_TE3 DMA_ISR_TEIF3 -#define DMA1_FLAG_GL4 DMA_ISR_GIF4 -#define DMA1_FLAG_TC4 DMA_ISR_TCIF4 -#define DMA1_FLAG_HT4 DMA_ISR_HTIF4 -#define DMA1_FLAG_TE4 DMA_ISR_TEIF4 -#define DMA1_FLAG_GL5 DMA_ISR_GIF5 -#define DMA1_FLAG_TC5 DMA_ISR_TCIF5 -#define DMA1_FLAG_HT5 DMA_ISR_HTIF5 -#define DMA1_FLAG_TE5 DMA_ISR_TEIF5 -#define DMA1_FLAG_GL6 DMA_ISR_GIF6 -#define DMA1_FLAG_TC6 DMA_ISR_TCIF6 -#define DMA1_FLAG_HT6 DMA_ISR_HTIF6 -#define DMA1_FLAG_TE6 DMA_ISR_TEIF6 -#define DMA1_FLAG_GL7 DMA_ISR_GIF7 -#define DMA1_FLAG_TC7 DMA_ISR_TCIF7 -#define DMA1_FLAG_HT7 DMA_ISR_HTIF7 -#define DMA1_FLAG_TE7 DMA_ISR_TEIF7 - -#define DMA2_FLAG_GL1 ((uint32_t)0x10000001) -#define DMA2_FLAG_TC1 ((uint32_t)0x10000002) -#define DMA2_FLAG_HT1 ((uint32_t)0x10000004) -#define DMA2_FLAG_TE1 ((uint32_t)0x10000008) -#define DMA2_FLAG_GL2 ((uint32_t)0x10000010) -#define DMA2_FLAG_TC2 ((uint32_t)0x10000020) -#define DMA2_FLAG_HT2 ((uint32_t)0x10000040) -#define DMA2_FLAG_TE2 ((uint32_t)0x10000080) -#define DMA2_FLAG_GL3 ((uint32_t)0x10000100) -#define DMA2_FLAG_TC3 ((uint32_t)0x10000200) -#define DMA2_FLAG_HT3 ((uint32_t)0x10000400) -#define DMA2_FLAG_TE3 ((uint32_t)0x10000800) -#define DMA2_FLAG_GL4 ((uint32_t)0x10001000) -#define DMA2_FLAG_TC4 ((uint32_t)0x10002000) -#define DMA2_FLAG_HT4 ((uint32_t)0x10004000) -#define DMA2_FLAG_TE4 ((uint32_t)0x10008000) -#define DMA2_FLAG_GL5 ((uint32_t)0x10010000) -#define DMA2_FLAG_TC5 ((uint32_t)0x10020000) -#define DMA2_FLAG_HT5 ((uint32_t)0x10040000) -#define DMA2_FLAG_TE5 ((uint32_t)0x10080000) - -#define IS_DMA_CLEAR_FLAG(FLAG) (((((FLAG) & 0xF0000000) == 0x00) || (((FLAG) & 0xEFF00000) == 0x00)) && ((FLAG) != 0x00)) - -#define IS_DMA_GET_FLAG(FLAG) (((FLAG) == DMA1_FLAG_GL1) || ((FLAG) == DMA1_FLAG_TC1) || \ - ((FLAG) == DMA1_FLAG_HT1) || ((FLAG) == DMA1_FLAG_TE1) || \ - ((FLAG) == DMA1_FLAG_GL2) || ((FLAG) == DMA1_FLAG_TC2) || \ - ((FLAG) == DMA1_FLAG_HT2) || ((FLAG) == DMA1_FLAG_TE2) || \ - ((FLAG) == DMA1_FLAG_GL3) || ((FLAG) == DMA1_FLAG_TC3) || \ - ((FLAG) == DMA1_FLAG_HT3) || ((FLAG) == DMA1_FLAG_TE3) || \ - ((FLAG) == DMA1_FLAG_GL4) || ((FLAG) == DMA1_FLAG_TC4) || \ - ((FLAG) == DMA1_FLAG_HT4) || ((FLAG) == DMA1_FLAG_TE4) || \ - ((FLAG) == DMA1_FLAG_GL5) || ((FLAG) == DMA1_FLAG_TC5) || \ - ((FLAG) == DMA1_FLAG_HT5) || ((FLAG) == DMA1_FLAG_TE5) || \ - ((FLAG) == DMA1_FLAG_GL6) || ((FLAG) == DMA1_FLAG_TC6) || \ - ((FLAG) == DMA1_FLAG_HT6) || ((FLAG) == DMA1_FLAG_TE6) || \ - ((FLAG) == DMA1_FLAG_GL7) || ((FLAG) == DMA1_FLAG_TC7) || \ - ((FLAG) == DMA1_FLAG_HT7) || ((FLAG) == DMA1_FLAG_TE7) || \ - ((FLAG) == DMA2_FLAG_GL1) || ((FLAG) == DMA2_FLAG_TC1) || \ - ((FLAG) == DMA2_FLAG_HT1) || ((FLAG) == DMA2_FLAG_TE1) || \ - ((FLAG) == DMA2_FLAG_GL2) || ((FLAG) == DMA2_FLAG_TC2) || \ - ((FLAG) == DMA2_FLAG_HT2) || ((FLAG) == DMA2_FLAG_TE2) || \ - ((FLAG) == DMA2_FLAG_GL3) || ((FLAG) == DMA2_FLAG_TC3) || \ - ((FLAG) == DMA2_FLAG_HT3) || ((FLAG) == DMA2_FLAG_TE3) || \ - ((FLAG) == DMA2_FLAG_GL4) || ((FLAG) == DMA2_FLAG_TC4) || \ - ((FLAG) == DMA2_FLAG_HT4) || ((FLAG) == DMA2_FLAG_TE4) || \ - ((FLAG) == DMA2_FLAG_GL5) || ((FLAG) == DMA2_FLAG_TC5) || \ - ((FLAG) == DMA2_FLAG_HT5) || ((FLAG) == DMA2_FLAG_TE5)) -/** - * @} - */ - -/** @defgroup DMA_Buffer_Size - * @{ - */ - -#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1) && ((SIZE) < 0x10000)) - -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions ------------------------------------------------------- */ - -/* Function used to set the DMA configuration to the default reset state ******/ -void DMA_DeInit(DMA_Channel_TypeDef* DMAy_Channelx); - -/* Initialization and Configuration functions *********************************/ -void DMA_Init(DMA_Channel_TypeDef* DMAy_Channelx, DMA_InitTypeDef* DMA_InitStruct); -void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct); -void DMA_Cmd(DMA_Channel_TypeDef* DMAy_Channelx, FunctionalState NewState); - -/* Data Counter functions******************************************************/ -void DMA_SetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx, uint16_t DataNumber); -uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx); - -/* Interrupts and flags management functions **********************************/ -void DMA_ITConfig(DMA_Channel_TypeDef* DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState); -FlagStatus DMA_GetFlagStatus(uint32_t DMAy_FLAG); -void DMA_ClearFlag(uint32_t DMAy_FLAG); -ITStatus DMA_GetITStatus(uint32_t DMAy_IT); -void DMA_ClearITPendingBit(uint32_t DMAy_IT); - -#ifdef __cplusplus -} -#endif - -#endif /*__FT32F0XX_DMA_H */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT FMD *****END OF FILE****/ diff --git a/bsp/ft32/libraries/FT32F0xx/FT32F0xx_Driver/Inc/ft32f0xx_exti.h b/bsp/ft32/libraries/FT32F0xx/FT32F0xx_Driver/Inc/ft32f0xx_exti.h deleted file mode 100644 index a158cebcb9d..00000000000 --- a/bsp/ft32/libraries/FT32F0xx/FT32F0xx_Driver/Inc/ft32f0xx_exti.h +++ /dev/null @@ -1,186 +0,0 @@ -/** - ****************************************************************************** - * @file ft32f0xx_exti.h - * @author FMD AE - * @brief This file contains all the functions prototypes for the EXTI - * firmware library - * @version V1.0.0 - * @data 2021-07-01 - ****************************************************************************** - */ -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __FT32F0XX_EXTI_H -#define __FT32F0XX_EXTI_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "ft32f0xx.h" - - -/** @addtogroup EXTI - * @{ - */ -/* Exported types ------------------------------------------------------------*/ - -/** - * @brief EXTI mode enumeration - */ - -typedef enum -{ - EXTI_Mode_Interrupt = 0x00, - EXTI_Mode_Event = 0x04 -}EXTIMode_TypeDef; - -#define IS_EXTI_MODE(MODE) (((MODE) == EXTI_Mode_Interrupt) || ((MODE) == EXTI_Mode_Event)) - -/** - * @brief EXTI Trigger enumeration - */ - -typedef enum -{ - EXTI_Trigger_Rising = 0x08, - EXTI_Trigger_Falling = 0x0C, - EXTI_Trigger_Rising_Falling = 0x10 -}EXTITrigger_TypeDef; - -#define IS_EXTI_TRIGGER(TRIGGER) (((TRIGGER) == EXTI_Trigger_Rising) || \ - ((TRIGGER) == EXTI_Trigger_Falling) || \ - ((TRIGGER) == EXTI_Trigger_Rising_Falling)) -/** - * @brief EXTI Init Structure definition - */ - -typedef struct -{ - uint32_t EXTI_Line; /*!< Specifies the EXTI lines to be enabled or disabled. - This parameter can be any combination of @ref EXTI_Lines */ - - EXTIMode_TypeDef EXTI_Mode; /*!< Specifies the mode for the EXTI lines. - This parameter can be a value of @ref EXTIMode_TypeDef */ - - EXTITrigger_TypeDef EXTI_Trigger; /*!< Specifies the trigger signal active edge for the EXTI lines. - This parameter can be a value of @ref EXTIMode_TypeDef */ - - FunctionalState EXTI_LineCmd; /*!< Specifies the new state of the selected EXTI lines. - This parameter can be set either to ENABLE or DISABLE */ -}EXTI_InitTypeDef; - -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup EXTI_Exported_Constants - * @{ - */ -/** @defgroup EXTI_Lines - * @{ - */ - -#define EXTI_Line0 ((uint32_t)0x00000001) /*!< External interrupt line 0 */ -#define EXTI_Line1 ((uint32_t)0x00000002) /*!< External interrupt line 1 */ -#define EXTI_Line2 ((uint32_t)0x00000004) /*!< External interrupt line 2 */ -#define EXTI_Line3 ((uint32_t)0x00000008) /*!< External interrupt line 3 */ -#define EXTI_Line4 ((uint32_t)0x00000010) /*!< External interrupt line 4 */ -#define EXTI_Line5 ((uint32_t)0x00000020) /*!< External interrupt line 5 */ -#define EXTI_Line6 ((uint32_t)0x00000040) /*!< External interrupt line 6 */ -#define EXTI_Line7 ((uint32_t)0x00000080) /*!< External interrupt line 7 */ -#define EXTI_Line8 ((uint32_t)0x00000100) /*!< External interrupt line 8 */ -#define EXTI_Line9 ((uint32_t)0x00000200) /*!< External interrupt line 9 */ -#define EXTI_Line10 ((uint32_t)0x00000400) /*!< External interrupt line 10 */ -#define EXTI_Line11 ((uint32_t)0x00000800) /*!< External interrupt line 11 */ -#define EXTI_Line12 ((uint32_t)0x00001000) /*!< External interrupt line 12 */ -#define EXTI_Line13 ((uint32_t)0x00002000) /*!< External interrupt line 13 */ -#define EXTI_Line14 ((uint32_t)0x00004000) /*!< External interrupt line 14 */ -#define EXTI_Line15 ((uint32_t)0x00008000) /*!< External interrupt line 15 */ -#define EXTI_Line16 ((uint32_t)0x00010000) /*!< External interrupt line 16 */ -#define EXTI_Line17 ((uint32_t)0x00020000) /*!< Internal interrupt line 17 - Connected to the RTC Alarm - event */ -#define EXTI_Line18 ((uint32_t)0x00040000) /*!< Internal interrupt line 18 - Connected to the USB - event*/ -#define EXTI_Line19 ((uint32_t)0x00080000) /*!< Internal interrupt line 19 - Connected to the RTC Tamper - and Time Stamp events */ -#define EXTI_Line20 ((uint32_t)0x00100000) /*!< Internal interrupt line 20 - Connected to the RTC wakeup - event */ -#define EXTI_Line21 ((uint32_t)0x00200000) /*!< Internal interrupt line 21 - Connected to the Comparator 1 - event */ -#define EXTI_Line22 ((uint32_t)0x00400000) /*!< Internal interrupt line 22 - Connected to the Comparator 2 - event*/ -#define EXTI_Line23 ((uint32_t)0x00800000) /*!< Internal interrupt line 23 - Connected to the I2C1 wakeup - event*/ -#define EXTI_Line25 ((uint32_t)0x02000000) /*!< Internal interrupt line 25 - Connected to the USART1 wakeup - event */ -#define EXTI_Line26 ((uint32_t)0x04000000) /*!< Internal interrupt line 26 - Connected to the USART2 wakeup - event*/ -#define EXTI_Line27 ((uint32_t)0x08000000) /*!< Internal interrupt line 27 - Connected to the CEC wakeup - event */ -#define EXTI_Line31 ((uint32_t)0x80000000) /*!< Internal interrupt line 31 - Connected to the VDD USB monitor - event */ -#define IS_EXTI_LINE(LINE) ((((LINE) & (uint32_t)0x71000000) == 0x00) && ((LINE) != (uint16_t)0x00)) - -#define IS_GET_EXTI_LINE(LINE) (((LINE) == EXTI_Line0) || ((LINE) == EXTI_Line1) || \ - ((LINE) == EXTI_Line2) || ((LINE) == EXTI_Line3) || \ - ((LINE) == EXTI_Line4) || ((LINE) == EXTI_Line5) || \ - ((LINE) == EXTI_Line6) || ((LINE) == EXTI_Line7) || \ - ((LINE) == EXTI_Line8) || ((LINE) == EXTI_Line9) || \ - ((LINE) == EXTI_Line10) || ((LINE) == EXTI_Line11) || \ - ((LINE) == EXTI_Line12) || ((LINE) == EXTI_Line13) || \ - ((LINE) == EXTI_Line14) || ((LINE) == EXTI_Line15) || \ - ((LINE) == EXTI_Line16) || ((LINE) == EXTI_Line17) || \ - ((LINE) == EXTI_Line18) || ((LINE) == EXTI_Line19) || \ - ((LINE) == EXTI_Line20) || ((LINE) == EXTI_Line21) || \ - ((LINE) == EXTI_Line22) || ((LINE) == EXTI_Line23) || \ - ((LINE) == EXTI_Line25) || ((LINE) == EXTI_Line26) || \ - ((LINE) == EXTI_Line27) || ((LINE) == EXTI_Line31)) - -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions ------------------------------------------------------- */ -/* Function used to set the EXTI configuration to the default reset state *****/ -void EXTI_DeInit(void); - -/* Initialization and Configuration functions *********************************/ -void EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct); -void EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct); -void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line); - -/* Interrupts and flags management functions **********************************/ -FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line); -void EXTI_ClearFlag(uint32_t EXTI_Line); -ITStatus EXTI_GetITStatus(uint32_t EXTI_Line); -void EXTI_ClearITPendingBit(uint32_t EXTI_Line); - -#ifdef __cplusplus -} -#endif - -#endif /* __FT32F0XX_EXTI_H */ -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT FMD *****END OF FILE****/ diff --git a/bsp/ft32/libraries/FT32F0xx/FT32F0xx_Driver/Inc/ft32f0xx_flash.h b/bsp/ft32/libraries/FT32F0xx/FT32F0xx_Driver/Inc/ft32f0xx_flash.h deleted file mode 100644 index bc197529ad2..00000000000 --- a/bsp/ft32/libraries/FT32F0xx/FT32F0xx_Driver/Inc/ft32f0xx_flash.h +++ /dev/null @@ -1,389 +0,0 @@ -/** - ****************************************************************************** - * @file ft32f0xx_flash.h - * @author FMD AE - * @brief This file contains all the functions prototypes for the FLASH - * firmware library. - * @version V1.0.0 - * @data 2021-07-01 - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __FT32F0XX_FLASH_H -#define __FT32F0XX_FLASH_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "ft32f0xx.h" - - -/** @addtogroup FLASH - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ - -/** - * @brief FLASH Status - */ -typedef enum -{ - FLASH_BUSY = 1, - FLASH_ERROR_WRP, - FLASH_ERROR_PROGRAM, - FLASH_COMPLETE, - FLASH_TIMEOUT -}FLASH_Status; - -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup FLASH_Exported_Constants - * @{ - */ - -/** @defgroup FLASH_Latency - * @{ - */ -#define FLASH_Latency_0 ((uint32_t)0x00000000) /*!< FLASH Zero Latency cycle */ -#define FLASH_Latency_1 ((uint32_t)0x00000001) /*!< FLASH One Latency cycle */ -#define FLASH_Latency_2 ((uint32_t)0x00000002) -#define FLASH_Latency_3 ((uint32_t)0x00000003) -#define FLASH_Latency_4 ((uint32_t)0x00000004) -#define FLASH_Latency_5 ((uint32_t)0x00000005) -#define FLASH_Latency_6 ((uint32_t)0x00000006) -#define FLASH_Latency_7 ((uint32_t)0x00000007) -#define FLASH_Latency_8 ((uint32_t)0x00000008) -#define FLASH_Latency_9 ((uint32_t)0x00000009) -#define FLASH_Latency_10 ((uint32_t)0x0000000a) -#define FLASH_Latency_11 ((uint32_t)0x0000000b) -#define FLASH_Latency_12 ((uint32_t)0x0000000c) -#define FLASH_Latency_13 ((uint32_t)0x0000000d) -#define FLASH_Latency_14 ((uint32_t)0x0000000e) -#define FLASH_Latency_15 ((uint32_t)0x0000000f) - -#define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_Latency_0) || \ - ((LATENCY) == FLASH_Latency_1) || \ - ((LATENCY) == FLASH_Latency_2 ) || \ - ((LATENCY) == FLASH_Latency_3 ) || \ - ((LATENCY) == FLASH_Latency_4 ) || \ - ((LATENCY) == FLASH_Latency_5 ) || \ - ((LATENCY) == FLASH_Latency_6 ) || \ - ((LATENCY) == FLASH_Latency_7 ) || \ - ((LATENCY) == FLASH_Latency_8 ) || \ - ((LATENCY) == FLASH_Latency_9 ) || \ - ((LATENCY) == FLASH_Latency_10) || \ - ((LATENCY) == FLASH_Latency_11) || \ - ((LATENCY) == FLASH_Latency_12) || \ - ((LATENCY) == FLASH_Latency_13) || \ - ((LATENCY) == FLASH_Latency_14) || \ - ((LATENCY) == FLASH_Latency_15)) -/** - * @} - */ - -/** @defgroup FLASH_Interrupts - * @{ - */ - -#define FLASH_IT_EOP FLASH_CR_EOPIE /*!< End of programming interrupt source */ -#define FLASH_IT_ERR FLASH_CR_ERRIE /*!< Error interrupt source */ -#define IS_FLASH_IT(IT) ((((IT) & (uint32_t)0xFFFFEBFF) == 0x00000000) && (((IT) != 0x00000000))) -/** - * @} - */ - -/** @defgroup FLASH_Address - * @{ - */ - -#if defined(FT32F030X8) /*64K devices */ - #define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) >= 0x08000000) && ((ADDRESS) <= 0x0800FFFF)) -#elif defined (FT32F072xB) /*128K devices */ - #define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) >= 0x08000000) && ((ADDRESS) <= 0x0801FFFF)) -#endif - -/** - * @} - */ - -/** @defgroup FLASH_OB_DATA_ADDRESS - * @{ - */ -#define IS_OB_DATA_ADDRESS(ADDRESS) (((ADDRESS) == 0x1FFFF804)) - -/** - * @} - */ - -/** @defgroup FLASH_Option_Bytes_Write_Protection - * @{ - */ - -#define OB_WRP_Pages0to7 ((uint32_t)0x00000001) /* Write protection of page 0 to 7 */ -#define OB_WRP_Pages8to15 ((uint32_t)0x00000002) /* Write protection of page 8 to 15 */ -#define OB_WRP_Pages16to23 ((uint32_t)0x00000004) /* Write protection of page 16 to 23 */ -#define OB_WRP_Pages24to31 ((uint32_t)0x00000008) /* Write protection of page 24 to 31 */ -#define OB_WRP_Pages32to39 ((uint32_t)0x00000010) /* Write protection of page 32 to 39 */ -#define OB_WRP_Pages40to47 ((uint32_t)0x00000020) /* Write protection of page 40 to 47 */ -#define OB_WRP_Pages48to55 ((uint32_t)0x00000040) /* Write protection of page 48 to 55 */ -#define OB_WRP_Pages56to63 ((uint32_t)0x00000080) /* Write protection of page 56 to 63 */ -#define OB_WRP_Pages64to71 ((uint32_t)0x00000100) /* Write protection of page 64 to 71 */ -#define OB_WRP_Pages72to79 ((uint32_t)0x00000200) /* Write protection of page 72 to 79 */ -#define OB_WRP_Pages80to87 ((uint32_t)0x00000400) /* Write protection of page 80 to 87 */ -#define OB_WRP_Pages88to95 ((uint32_t)0x00000800) /* Write protection of page 88 to 95 */ -#define OB_WRP_Pages96to103 ((uint32_t)0x00001000) /* Write protection of page 96 to 103 */ -#define OB_WRP_Pages104to111 ((uint32_t)0x00002000) /* Write protection of page 104 to 111 */ -#define OB_WRP_Pages112to119 ((uint32_t)0x00004000) /* Write protection of page 112 to 119 */ -#define OB_WRP_Pages120to127 ((uint32_t)0x00008000) /* Write protection of page 120 to 127 */ - -#define OB_WRP_AllPages ((uint32_t)0x0000FFFF) /*!< Write protection of all Sectors */ - -#define IS_OB_WRP(PAGE) (((PAGE) != 0x0000000)) - -/** - * @} - */ - -/** @defgroup FLASH_Option_Bytes_Read_Protection - * @{ - */ - -/** - * @brief FLASH_Read Protection Level - */ -#define OB_RDP_Level_0 ((uint8_t)0xAA) -#define OB_RDP_Level_1 ((uint8_t)0xBB) -/*#define OB_RDP_Level_2 ((uint8_t)0xCC)*/ /* Warning: When enabling read protection level 2 - it's no more possible to go back to level 1 or 0 */ - -#define IS_OB_RDP(LEVEL) (((LEVEL) == OB_RDP_Level_0)||\ - ((LEVEL) == OB_RDP_Level_1))/*||\ - ((LEVEL) == OB_RDP_Level_2))*/ -/** - * @} - */ - -/** @defgroup FLASH_Option_Bytes_IWatchdog - * @{ - */ -#if defined (FT32F072xB) - #define OB_IWDG_SW ((uint8_t)0x01) /*!< Software IWDG selected */ - #define OB_IWDG_HW ((uint8_t)0x00) /*!< Hardware IWDG selected */ -#else - #define OB_IWDG_SW ((uint8_t)0x00) /*!< Software IWDG selected */ - #define OB_IWDG_HW ((uint8_t)0x01) /*!< Hardware IWDG selected */ -#endif -#define IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW)) - -/** - * @} - */ - -/** @defgroup FLASH_Option_Bytes_nRST_STOP - * @{ - */ - -#define OB_STOP_NoRST ((uint8_t)0x02) /*!< No reset generated when entering in STOP */ -#define OB_STOP_RST ((uint8_t)0x00) /*!< Reset generated when entering in STOP */ -#define IS_OB_STOP_SOURCE(SOURCE) (((SOURCE) == OB_STOP_NoRST) || ((SOURCE) == OB_STOP_RST)) - -/** - * @} - */ - -/** @defgroup FLASH_Option_Bytes_nRST_STDBY - * @{ - */ - -#define OB_STDBY_NoRST ((uint8_t)0x04) /*!< No reset generated when entering in STANDBY */ -#define OB_STDBY_RST ((uint8_t)0x00) /*!< Reset generated when entering in STANDBY */ -#define IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NoRST) || ((SOURCE) == OB_STDBY_RST)) - -/** - * @} - */ - -/** @defgroup FLASH_Option_Bytes_BOOT1 - * @{ - */ - -#define OB_BOOT1_RESET ((uint8_t)0x00) /*!< BOOT1 Reset */ -#define OB_BOOT1_SET ((uint8_t)0x10) /*!< BOOT1 Set */ -#define IS_OB_BOOT1(BOOT1) (((BOOT1) == OB_BOOT1_RESET) || ((BOOT1) == OB_BOOT1_SET)) - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** @defgroup FLASH_Option_Bytes_VDDA_Analog_Monitoring - * @{ - */ - -#define OB_VDDA_ANALOG_ON ((uint8_t)0x20) /*!< Analog monitoring on VDDA Power source ON */ -#define OB_VDDA_ANALOG_OFF ((uint8_t)0x00) /*!< Analog monitoring on VDDA Power source OFF */ - -#define IS_OB_VDDA_ANALOG(ANALOG) (((ANALOG) == OB_VDDA_ANALOG_ON) || ((ANALOG) == OB_VDDA_ANALOG_OFF)) - -/** - * @} - */ - -/** @defgroup FLASH_Option_Bytes_SRAM_Parity_Enable - * @{ - */ - -#define OB_SRAM_PARITY_SET ((uint8_t)0x00) /*!< SRAM parity enable Set */ -#define OB_SRAM_PARITY_RESET ((uint8_t)0x40) /*!< SRAM parity enable reset */ - -#define IS_OB_SRAM_PARITY(PARITY) (((PARITY) == OB_SRAM_PARITY_SET) || ((PARITY) == OB_SRAM_PARITY_RESET)) - -/** - * @} - */ - -/** @defgroup FLASH_Flags - * @{ - */ - -#define FLASH_FLAG_BSY FLASH_SR_BSY /*!< FLASH Busy flag */ -#define FLASH_FLAG_PGERR FLASH_SR_PGERR /*!< FLASH Programming error flag */ -#define FLASH_FLAG_WRPERR FLASH_SR_WRPERR /*!< FLASH Write protected error flag */ -#define FLASH_FLAG_EOP FLASH_SR_EOP /*!< FLASH End of Programming flag */ - -#define IS_FLASH_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFFCB) == 0x00000000) && ((FLAG) != 0x00000000)) - -#define IS_FLASH_GET_FLAG(FLAG) (((FLAG) == FLASH_FLAG_BSY) || ((FLAG) == FLASH_FLAG_PGERR) || \ - ((FLAG) == FLASH_FLAG_WRPERR) || ((FLAG) == FLASH_FLAG_EOP)) -/** - * @} - */ - -/** @defgroup FLASH_Timeout_definition - * @{ - */ -#define FLASH_ER_PRG_TIMEOUT ((uint32_t)0x000B0000) - -/** - * @} - */ - -/** @defgroup FLASH_Legacy - * @{ - */ -#define FLASH_WRProt_Pages0to7 OB_WRP_Pages0to7 -#define FLASH_WRProt_Pages8to15 OB_WRP_Pages8to15 -#define FLASH_WRProt_Pages16to23 OB_WRP_Pages16to23 -#define FLASH_WRProt_Pages24to31 OB_WRP_Pages24to31 -#define FLASH_WRProt_Pages32to39 OB_WRP_Pages32to39 -#define FLASH_WRProt_Pages40to47 OB_WRP_Pages40to47 -#define FLASH_WRProt_Pages48to55 OB_WRP_Pages48to55 -#define FLASH_WRProt_Pages56to63 OB_WRP_Pages56to63 -#define FLASH_WRProt_Pages64to71 OB_WRP_Pages64to71 -#define FLASH_WRProt_Pages72to79 OB_WRP_Pages72to79 -#define FLASH_WRProt_Pages80to87 OB_WRP_Pages80to87 -#define FLASH_WRProt_Pages88to95 OB_WRP_Pages88to95 -#define FLASH_WRProt_Pages96to103 OB_WRP_Pages96to103 -#define FLASH_WRProt_Pages104to111 OB_WRP_Pages104to111 -#define FLASH_WRProt_Pages112to119 OB_WRP_Pages112to119 -#define FLASH_WRProt_Pages120to127 OB_WRP_Pages120to127 - - -#define FLASH_WRProt_AllPages OB_WRP_AllPages -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions ------------------------------------------------------- */ - -/** - * @brief FLASH memory functions that can be executed from FLASH. - */ -/* FLASH Interface configuration functions ************************************/ -void FLASH_SetLatency(uint32_t FLASH_Latency); -void FLASH_PrefetchBufferCmd(FunctionalState NewState); -FlagStatus FLASH_GetPrefetchBufferStatus(void); - -/* FLASH Memory Programming functions *****************************************/ -void FLASH_Unlock(void); -void FLASH_Lock(void); -FLASH_Status FLASH_ErasePage(uint32_t Page_Address); -FLASH_Status FLASH_EraseAllPages(void); -FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data); -#if defined(FT32F072xB) -FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data); -#endif - -/* FLASH Option Bytes Programming functions *****************************************/ -void FLASH_OB_Unlock(void); -void FLASH_OB_Lock(void); -void FLASH_OB_Launch(void); -FLASH_Status FLASH_OB_Erase(void); -FLASH_Status FLASH_OB_EnableWRP(uint32_t OB_WRP); -FLASH_Status FLASH_OB_RDPConfig(uint8_t OB_RDP); -FLASH_Status FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY); -FLASH_Status FLASH_OB_BOOTConfig(uint8_t OB_BOOT1); -FLASH_Status FLASH_OB_VDDAConfig(uint8_t OB_VDDA_ANALOG); -FLASH_Status FLASH_OB_SRAMParityConfig(uint8_t OB_SRAM_Parity); -FLASH_Status FLASH_OB_WriteUser(uint8_t OB_USER); -#if defined(FT32F072xB) -FLASH_Status FLASH_OB_ProgramData(uint32_t Address, uint8_t Data); -#else -FLASH_Status FLASH_OB_ProgramData(uint32_t Address, uint32_t Data); -#endif -uint8_t FLASH_OB_GetUser(void); -uint32_t FLASH_OB_GetWRP(void); -FlagStatus FLASH_OB_GetRDP(void); - -/* FLASH Interrupts and flags management functions **********************************/ -void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState); -FlagStatus FLASH_GetFlagStatus(uint32_t FLASH_FLAG); -void FLASH_ClearFlag(uint32_t FLASH_FLAG); -FLASH_Status FLASH_GetStatus(void); -FLASH_Status FLASH_WaitForLastOperation(uint32_t Timeout); - -/** @defgroup FLASH_Legacy - * @{ - */ -#define FLASH_EraseOptionBytes FLASH_OB_Erase -#define FLASH_EnableWriteProtection FLASH_OB_EnableWRP -#define FLASH_UserOptionByteConfig FLASH_OB_UserConfig -#define FLASH_ProgramOption4ByteData FLASH_OB_ProgramData -#define FLASH_GetUserOptionByte FLASH_OB_GetUser -#define FLASH_GetWriteProtectionOptionByte FLASH_OB_GetWRP - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __FT32F0XX_FLASH_H */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT FMD *****END OF FILE****/ diff --git a/bsp/ft32/libraries/FT32F0xx/FT32F0xx_Driver/Inc/ft32f0xx_gpio.h b/bsp/ft32/libraries/FT32F0xx/FT32F0xx_Driver/Inc/ft32f0xx_gpio.h deleted file mode 100644 index 4d86816ced1..00000000000 --- a/bsp/ft32/libraries/FT32F0xx/FT32F0xx_Driver/Inc/ft32f0xx_gpio.h +++ /dev/null @@ -1,370 +0,0 @@ -/** - ****************************************************************************** - * @file ft32f0xx_gpio.h - * @author FMD AE - * @brief This file contains all the functions prototypes for the GPIO - * firmware library. - * @version V1.0.0 - * @data 2021-07-01 - ****************************************************************************** - */ - - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __FT32F030X8_GPIO_H -#define __FT32F030X8_GPIO_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "ft32f0xx.h" - - - -/** @addtogroup GPIO - * @{ - */ -/* Exported types ------------------------------------------------------------*/ - -#define IS_GPIO_ALL_PERIPH(PERIPH) (((PERIPH) == GPIOA) || \ - ((PERIPH) == GPIOB) || \ - ((PERIPH) == GPIOC) || \ - ((PERIPH) == GPIOD) || \ - ((PERIPH) == GPIOE) || \ - ((PERIPH) == GPIOF)) - -#define IS_GPIO_LIST_PERIPH(PERIPH) (((PERIPH) == GPIOA) || \ - ((PERIPH) == GPIOB)) - -/** @defgroup Configuration_Mode_enumeration - * @{ - */ -typedef enum -{ - GPIO_Mode_IN = 0x00, /*!< GPIO Input Mode */ - GPIO_Mode_OUT = 0x01, /*!< GPIO Output Mode */ - GPIO_Mode_AF = 0x02, /*!< GPIO Alternate function Mode */ - GPIO_Mode_AN = 0x03 /*!< GPIO Analog In/Out Mode */ -}GPIOMode_TypeDef; - -#define IS_GPIO_MODE(MODE) (((MODE) == GPIO_Mode_IN)|| ((MODE) == GPIO_Mode_OUT) || \ - ((MODE) == GPIO_Mode_AF)|| ((MODE) == GPIO_Mode_AN)) -/** - * @} - */ - -/** @defgroup Output_type_enumeration - * @{ - */ -typedef enum -{ - GPIO_OType_PP = 0x00, - GPIO_OType_OD = 0x01 -}GPIOOType_TypeDef; - -#define IS_GPIO_OTYPE(OTYPE) (((OTYPE) == GPIO_OType_PP) || ((OTYPE) == GPIO_OType_OD)) - -/** - * @} - */ - -/** @defgroup Output_Maximum_frequency_enumeration - * @{ - */ -typedef enum -{ - GPIO_Speed_Level_1 = 0x00, /*!< I/O output speed: Low 2 MHz */ - GPIO_Speed_Level_2 = 0x01, /*!< I/O output speed: Medium 10 MHz */ - GPIO_Speed_Level_3 = 0x03 /*!< I/O output speed: High 50 MHz */ -}GPIOSpeed_TypeDef; - -#define IS_GPIO_SPEED(SPEED) (((SPEED) == GPIO_Speed_Level_1) || ((SPEED) == GPIO_Speed_Level_2) || \ - ((SPEED) == GPIO_Speed_Level_3)) -/** - * @} - */ - -/** @defgroup Configuration_Pull-Up_Pull-Down_enumeration - * @{ - */ -typedef enum -{ - GPIO_PuPd_NOPULL = 0x00, - GPIO_PuPd_UP = 0x01, - GPIO_PuPd_DOWN = 0x02 -}GPIOPuPd_TypeDef; - -#define IS_GPIO_PUPD(PUPD) (((PUPD) == GPIO_PuPd_NOPULL) || ((PUPD) == GPIO_PuPd_UP) || \ - ((PUPD) == GPIO_PuPd_DOWN)) -/** - * @} - */ - -/** @defgroup Bit_SET_and_Bit_RESET_enumeration - * @{ - */ -typedef enum -{ - Bit_RESET = 0, - Bit_SET -}BitAction; - -#define IS_GPIO_BIT_ACTION(ACTION) (((ACTION) == Bit_RESET) || ((ACTION) == Bit_SET)) -/** - * @} - */ - -/** - * @brief GPIO Init structure definition - */ -typedef struct -{ - uint32_t GPIO_Pin; /*!< Specifies the GPIO pins to be configured. - This parameter can be any value of @ref GPIO_pins_define */ - - GPIOMode_TypeDef GPIO_Mode; /*!< Specifies the operating mode for the selected pins. - This parameter can be a value of @ref GPIOMode_TypeDef */ - - GPIOSpeed_TypeDef GPIO_Speed; /*!< Specifies the speed for the selected pins. - This parameter can be a value of @ref GPIOSpeed_TypeDef */ - - GPIOOType_TypeDef GPIO_OType; /*!< Specifies the operating output type for the selected pins. - This parameter can be a value of @ref GPIOOType_TypeDef */ - - GPIOPuPd_TypeDef GPIO_PuPd; /*!< Specifies the operating Pull-up/Pull down for the selected pins. - This parameter can be a value of @ref GPIOPuPd_TypeDef */ -}GPIO_InitTypeDef; - -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup GPIO_Exported_Constants - * @{ - */ - -/** @defgroup GPIO_pins_define - * @{ - */ -#define GPIO_Pin_0 ((uint16_t)0x0001) /*!< Pin 0 selected */ -#define GPIO_Pin_1 ((uint16_t)0x0002) /*!< Pin 1 selected */ -#define GPIO_Pin_2 ((uint16_t)0x0004) /*!< Pin 2 selected */ -#define GPIO_Pin_3 ((uint16_t)0x0008) /*!< Pin 3 selected */ -#define GPIO_Pin_4 ((uint16_t)0x0010) /*!< Pin 4 selected */ -#define GPIO_Pin_5 ((uint16_t)0x0020) /*!< Pin 5 selected */ -#define GPIO_Pin_6 ((uint16_t)0x0040) /*!< Pin 6 selected */ -#define GPIO_Pin_7 ((uint16_t)0x0080) /*!< Pin 7 selected */ -#define GPIO_Pin_8 ((uint16_t)0x0100) /*!< Pin 8 selected */ -#define GPIO_Pin_9 ((uint16_t)0x0200) /*!< Pin 9 selected */ -#define GPIO_Pin_10 ((uint16_t)0x0400) /*!< Pin 10 selected */ -#define GPIO_Pin_11 ((uint16_t)0x0800) /*!< Pin 11 selected */ -#define GPIO_Pin_12 ((uint16_t)0x1000) /*!< Pin 12 selected */ -#define GPIO_Pin_13 ((uint16_t)0x2000) /*!< Pin 13 selected */ -#define GPIO_Pin_14 ((uint16_t)0x4000) /*!< Pin 14 selected */ -#define GPIO_Pin_15 ((uint16_t)0x8000) /*!< Pin 15 selected */ -#define GPIO_Pin_All ((uint16_t)0xFFFF) /*!< All pins selected */ - -#define IS_GPIO_PIN(PIN) ((PIN) != (uint16_t)0x00) - -#define IS_GET_GPIO_PIN(PIN) (((PIN) == GPIO_Pin_0) || \ - ((PIN) == GPIO_Pin_1) || \ - ((PIN) == GPIO_Pin_2) || \ - ((PIN) == GPIO_Pin_3) || \ - ((PIN) == GPIO_Pin_4) || \ - ((PIN) == GPIO_Pin_5) || \ - ((PIN) == GPIO_Pin_6) || \ - ((PIN) == GPIO_Pin_7) || \ - ((PIN) == GPIO_Pin_8) || \ - ((PIN) == GPIO_Pin_9) || \ - ((PIN) == GPIO_Pin_10) || \ - ((PIN) == GPIO_Pin_11) || \ - ((PIN) == GPIO_Pin_12) || \ - ((PIN) == GPIO_Pin_13) || \ - ((PIN) == GPIO_Pin_14) || \ - ((PIN) == GPIO_Pin_15)) - -/** - * @} - */ - -/** @defgroup GPIO_Pin_sources - * @{ - */ -#define GPIO_PinSource0 ((uint8_t)0x00) -#define GPIO_PinSource1 ((uint8_t)0x01) -#define GPIO_PinSource2 ((uint8_t)0x02) -#define GPIO_PinSource3 ((uint8_t)0x03) -#define GPIO_PinSource4 ((uint8_t)0x04) -#define GPIO_PinSource5 ((uint8_t)0x05) -#define GPIO_PinSource6 ((uint8_t)0x06) -#define GPIO_PinSource7 ((uint8_t)0x07) -#define GPIO_PinSource8 ((uint8_t)0x08) -#define GPIO_PinSource9 ((uint8_t)0x09) -#define GPIO_PinSource10 ((uint8_t)0x0A) -#define GPIO_PinSource11 ((uint8_t)0x0B) -#define GPIO_PinSource12 ((uint8_t)0x0C) -#define GPIO_PinSource13 ((uint8_t)0x0D) -#define GPIO_PinSource14 ((uint8_t)0x0E) -#define GPIO_PinSource15 ((uint8_t)0x0F) - -#define IS_GPIO_PIN_SOURCE(PINSOURCE) (((PINSOURCE) == GPIO_PinSource0) || \ - ((PINSOURCE) == GPIO_PinSource1) || \ - ((PINSOURCE) == GPIO_PinSource2) || \ - ((PINSOURCE) == GPIO_PinSource3) || \ - ((PINSOURCE) == GPIO_PinSource4) || \ - ((PINSOURCE) == GPIO_PinSource5) || \ - ((PINSOURCE) == GPIO_PinSource6) || \ - ((PINSOURCE) == GPIO_PinSource7) || \ - ((PINSOURCE) == GPIO_PinSource8) || \ - ((PINSOURCE) == GPIO_PinSource9) || \ - ((PINSOURCE) == GPIO_PinSource10) || \ - ((PINSOURCE) == GPIO_PinSource11) || \ - ((PINSOURCE) == GPIO_PinSource12) || \ - ((PINSOURCE) == GPIO_PinSource13) || \ - ((PINSOURCE) == GPIO_PinSource14) || \ - ((PINSOURCE) == GPIO_PinSource15)) -/** - * @} - */ - -/** @defgroup GPIO_Alternate_function_selection_define - * @{ - */ - -/** - * @brief AF 0 selection - */ -#define GPIO_AF_0 ((uint8_t)0x00) /* WKUP, EVENTOUT, TIM15, SPI1, TIM17, - MCO, SWDAT, SWCLK, TIM14, BOOT, - USART1, CEC, IR_OUT, SPI2, TS, TIM3, - USART4, CAN, TIM3, USART2, USART3, - CRS, TIM16, TIM1 */ -/** - * @brief AF 1 selection - */ -#define GPIO_AF_1 ((uint8_t)0x01) /* USART2, CEC, TIM3, USART1, IR, - EVENTOUT, I2C1, I2C2, TIM15, SPI2, - USART3, TS, SPI1 */ -/** - * @brief AF 2 selection - */ -#define GPIO_AF_2 ((uint8_t)0x02) /* TIM2, TIM1, EVENTOUT, TIM16, TIM17, - USB */ -/** - * @brief AF 3 selection - */ -#define GPIO_AF_3 ((uint8_t)0x03) /* TS, I2C1, TIM15, EVENTOUT */ - -/** - * @brief AF 4 selection - */ -#define GPIO_AF_4 ((uint8_t)0x04) /* TIM14, USART4, USART3, CRS, CAN, - I2C1 */ - -/** - * @brief AF 5 selection - */ -#define GPIO_AF_5 ((uint8_t)0x05) /* TIM16, TIM17, TIM15, SPI2, I2C2, - MCO, I2C1, USB */ - -/** - * @brief AF 6 selection - */ -#define GPIO_AF_6 ((uint8_t)0x06) /* EVENTOUT */ -/** - * @brief AF 7 selection - */ -#define GPIO_AF_7 ((uint8_t)0x07) /* COMP1 OUT and COMP2 OUT */ - -#define IS_GPIO_AF(AF) (((AF) == GPIO_AF_0) || ((AF) == GPIO_AF_1) || \ - ((AF) == GPIO_AF_2) || ((AF) == GPIO_AF_3) || \ - ((AF) == GPIO_AF_4) || ((AF) == GPIO_AF_5) || \ - ((AF) == GPIO_AF_6) || ((AF) == GPIO_AF_7)) - -/** - * @} - */ - -/** @defgroup GPIO_Speed_Legacy - * @{ - */ - -#define GPIO_Speed_2MHz GPIO_Speed_Level_1 /*!< I/O output speed: Low 2 MHz */ -#define GPIO_Speed_10MHz GPIO_Speed_Level_2 /*!< I/O output speed: Medium 10 MHz */ -#define GPIO_Speed_50MHz GPIO_Speed_Level_3 /*!< I/O output speed: High 50 MHz */ - -/** @defgroup GPIO_LEDM Only Use in GPIOA and GPIOB - * @} - */ -#define GPIO_LEDM_0 ((uint32_t)(0x00000001)) -#define GPIO_LEDM_1 ((uint32_t)(0x00000002)) -#define GPIO_LEDM_3 ((uint32_t)(0x00000008)) -#define GPIO_LEDM_4 ((uint32_t)(0x00000010)) -#define GPIO_LEDM_5 ((uint32_t)(0x00000020)) -#define GPIO_LEDM_6 ((uint32_t)(0x00000040)) -#define GPIO_LEDM_7 ((uint32_t)(0x00000080)) - -#define GPIO_LEDM_8 ((uint32_t)(0x00000100)) -#define GPIO_LEDM_9 ((uint32_t)(0x00000200)) -#define GPIO_LEDM_10 ((uint32_t)(0x00000400)) -#define GPIO_LEDM_13 ((uint32_t)(0x00002000)) -#define GPIO_LEDM_14 ((uint32_t)(0x00004000)) -#define GPIO_LEDM_15 ((uint32_t)(0x00008000)) - - -#define IS_GPIO_LEDM(LEDM) (((LEDM) == GPIO_LEDM_0) ||\ - ((LEDM) == GPIO_LEDM_1) ||\ - ((LEDM) == GPIO_LEDM_3) ||\ - ((LEDM) == GPIO_LEDM_4) ||\ - ((LEDM) == GPIO_LEDM_5) ||\ - ((LEDM) == GPIO_LEDM_6) ||\ - ((LEDM) == GPIO_LEDM_7) ||\ - ((LEDM) == GPIO_LEDM_8) ||\ - ((LEDM) == GPIO_LEDM_9) ||\ - ((LEDM) == GPIO_LEDM_10) ||\ - ((LEDM) == GPIO_LEDM_13) ||\ - ((LEDM) == GPIO_LEDM_14) ||\ - ((LEDM) == GPIO_LEDM_15)) -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions ------------------------------------------------------- */ -/* Function used to set the GPIO configuration to the default reset state *****/ -void GPIO_DeInit(GPIO_TypeDef* GPIOx); - -/* Initialization and Configuration functions *********************************/ -void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct); -void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct); -void GPIO_PinLockConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); - -/* GPIO Read and Write functions **********************************************/ -uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); -uint16_t GPIO_ReadInputData(GPIO_TypeDef* GPIOx); -uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); -uint16_t GPIO_ReadOutputData(GPIO_TypeDef* GPIOx); -void GPIO_SetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); -void GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); -void GPIO_WriteBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, BitAction BitVal); -void GPIO_Write(GPIO_TypeDef* GPIOx, uint16_t PortVal); - -/* GPIO Alternate functions configuration functions ***************************/ -void GPIO_PinAFConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_PinSource, uint8_t GPIO_AF); -/*GPIO LED*/ -void GPIO_LedmConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_LEDMx); - -#ifdef __cplusplus -} -#endif - -#endif /* __FT32F0XX_GPIO_H */ -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT FMD *****END OF FILE****/ diff --git a/bsp/ft32/libraries/FT32F0xx/FT32F0xx_Driver/Inc/ft32f0xx_i2c.h b/bsp/ft32/libraries/FT32F0xx/FT32F0xx_Driver/Inc/ft32f0xx_i2c.h deleted file mode 100644 index 41cad1d0d8b..00000000000 --- a/bsp/ft32/libraries/FT32F0xx/FT32F0xx_Driver/Inc/ft32f0xx_i2c.h +++ /dev/null @@ -1,458 +0,0 @@ -/** - ****************************************************************************** - * @file ft32f0xx_i2c.h - * @author FMD AE - * @brief This file contains all the functions prototypes for the I2C firmware - * library - * @version V1.0.0 - * @data 2021-07-01 - ****************************************************************************** - */ - - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __FT32F0XX_I2C_H -#define __FT32F0XX_I2C_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "ft32f0xx.h" - - -/** @addtogroup I2C - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ - -/** - * @brief I2C Init structure definition - */ - -typedef struct -{ - uint32_t I2C_Timing; /*!< Specifies the I2C_TIMINGR_register value. - This parameter must be set by referring to I2C_Timing_Config_Tool*/ - - uint32_t I2C_AnalogFilter; /*!< Enables or disables analog noise filter. - This parameter can be a value of @ref I2C_Analog_Filter*/ - - uint32_t I2C_DigitalFilter; /*!< Configures the digital noise filter. - This parameter can be a number between 0x00 and 0x0F*/ - - uint32_t I2C_Mode; /*!< Specifies the I2C mode. - This parameter can be a value of @ref I2C_mode*/ - - uint32_t I2C_OwnAddress1; /*!< Specifies the device own address 1. - This parameter can be a 7-bit or 10-bit address*/ - - uint32_t I2C_Ack; /*!< Enables or disables the acknowledgement. - This parameter can be a value of @ref I2C_acknowledgement*/ - - uint32_t I2C_AcknowledgedAddress; /*!< Specifies if 7-bit or 10-bit address is acknowledged. - This parameter can be a value of @ref I2C_acknowledged_address*/ -}I2C_InitTypeDef; - -/* Exported constants --------------------------------------------------------*/ - - -/** @defgroup I2C_Exported_Constants - * @{ - */ - -#define IS_I2C_ALL_PERIPH(PERIPH) (((PERIPH) == I2C1) || \ - ((PERIPH) == I2C2)) - -#define IS_I2C_1_PERIPH(PERIPH) ((PERIPH) == I2C1) - -/** @defgroup I2C_Analog_Filter - * @{ - */ - -#define I2C_AnalogFilter_Enable ((uint32_t)0x00000000) -#define I2C_AnalogFilter_Disable I2C_CR1_ANFOFF - -#define IS_I2C_ANALOG_FILTER(FILTER) (((FILTER) == I2C_AnalogFilter_Enable) || \ - ((FILTER) == I2C_AnalogFilter_Disable)) -/** - * @} - */ - -/** @defgroup I2C_Digital_Filter - * @{ - */ - -#define IS_I2C_DIGITAL_FILTER(FILTER) ((FILTER) <= 0x0000000F) -/** - * @} - */ - -/** @defgroup I2C_mode - * @{ - */ - -#define I2C_Mode_I2C ((uint32_t)0x00000000) -#define I2C_Mode_SMBusDevice I2C_CR1_SMBDEN -#define I2C_Mode_SMBusHost I2C_CR1_SMBHEN - -#define IS_I2C_MODE(MODE) (((MODE) == I2C_Mode_I2C) || \ - ((MODE) == I2C_Mode_SMBusDevice) || \ - ((MODE) == I2C_Mode_SMBusHost)) -/** - * @} - */ - -/** @defgroup I2C_acknowledgement - * @{ - */ - -#define I2C_Ack_Enable ((uint32_t)0x00000000) -#define I2C_Ack_Disable I2C_CR2_NACK - -#define IS_I2C_ACK(ACK) (((ACK) == I2C_Ack_Enable) || \ - ((ACK) == I2C_Ack_Disable)) -/** - * @} - */ - -/** @defgroup I2C_acknowledged_address - * @{ - */ - -#define I2C_AcknowledgedAddress_7bit ((uint32_t)0x00000000) -#define I2C_AcknowledgedAddress_10bit I2C_OAR1_OA1MODE - -#define IS_I2C_ACKNOWLEDGE_ADDRESS(ADDRESS) (((ADDRESS) == I2C_AcknowledgedAddress_7bit) || \ - ((ADDRESS) == I2C_AcknowledgedAddress_10bit)) -/** - * @} - */ - -/** @defgroup I2C_own_address1 - * @{ - */ - -#define IS_I2C_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= (uint32_t)0x000003FF) -/** - * @} - */ - -/** @defgroup I2C_transfer_direction - * @{ - */ - -#define I2C_Direction_Transmitter ((uint16_t)0x0000) -#define I2C_Direction_Receiver ((uint16_t)0x0400) - -#define IS_I2C_DIRECTION(DIRECTION) (((DIRECTION) == I2C_Direction_Transmitter) || \ - ((DIRECTION) == I2C_Direction_Receiver)) -/** - * @} - */ - -/** @defgroup I2C_DMA_transfer_requests - * @{ - */ - -#define I2C_DMAReq_Tx I2C_CR1_TXDMAEN -#define I2C_DMAReq_Rx I2C_CR1_RXDMAEN - -#define IS_I2C_DMA_REQ(REQ) ((((REQ) & (uint32_t)0xFFFF3FFF) == 0x00) && ((REQ) != 0x00)) -/** - * @} - */ - -/** @defgroup I2C_slave_address - * @{ - */ - -#define IS_I2C_SLAVE_ADDRESS(ADDRESS) ((ADDRESS) <= (uint16_t)0x03FF) -/** - * @} - */ - - -/** @defgroup I2C_own_address2 - * @{ - */ - -#define IS_I2C_OWN_ADDRESS2(ADDRESS2) ((ADDRESS2) <= (uint16_t)0x00FF) - -/** - * @} - */ - -/** @defgroup I2C_own_address2_mask - * @{ - */ - -#define I2C_OA2_NoMask ((uint8_t)0x00) -#define I2C_OA2_Mask01 ((uint8_t)0x01) -#define I2C_OA2_Mask02 ((uint8_t)0x02) -#define I2C_OA2_Mask03 ((uint8_t)0x03) -#define I2C_OA2_Mask04 ((uint8_t)0x04) -#define I2C_OA2_Mask05 ((uint8_t)0x05) -#define I2C_OA2_Mask06 ((uint8_t)0x06) -#define I2C_OA2_Mask07 ((uint8_t)0x07) - -#define IS_I2C_OWN_ADDRESS2_MASK(MASK) (((MASK) == I2C_OA2_NoMask) || \ - ((MASK) == I2C_OA2_Mask01) || \ - ((MASK) == I2C_OA2_Mask02) || \ - ((MASK) == I2C_OA2_Mask03) || \ - ((MASK) == I2C_OA2_Mask04) || \ - ((MASK) == I2C_OA2_Mask05) || \ - ((MASK) == I2C_OA2_Mask06) || \ - ((MASK) == I2C_OA2_Mask07)) - -/** - * @} - */ - -/** @defgroup I2C_timeout - * @{ - */ - -#define IS_I2C_TIMEOUT(TIMEOUT) ((TIMEOUT) <= (uint16_t)0x0FFF) - -/** - * @} - */ - -/** @defgroup I2C_registers - * @{ - */ - -#define I2C_Register_CR1 ((uint8_t)0x00) -#define I2C_Register_CR2 ((uint8_t)0x04) -#define I2C_Register_OAR1 ((uint8_t)0x08) -#define I2C_Register_OAR2 ((uint8_t)0x0C) -#define I2C_Register_TIMINGR ((uint8_t)0x10) -#define I2C_Register_TIMEOUTR ((uint8_t)0x14) -#define I2C_Register_ISR ((uint8_t)0x18) -#define I2C_Register_ICR ((uint8_t)0x1C) -#define I2C_Register_PECR ((uint8_t)0x20) -#define I2C_Register_RXDR ((uint8_t)0x24) -#define I2C_Register_TXDR ((uint8_t)0x28) - -#define IS_I2C_REGISTER(REGISTER) (((REGISTER) == I2C_Register_CR1) || \ - ((REGISTER) == I2C_Register_CR2) || \ - ((REGISTER) == I2C_Register_OAR1) || \ - ((REGISTER) == I2C_Register_OAR2) || \ - ((REGISTER) == I2C_Register_TIMINGR) || \ - ((REGISTER) == I2C_Register_TIMEOUTR) || \ - ((REGISTER) == I2C_Register_ISR) || \ - ((REGISTER) == I2C_Register_ICR) || \ - ((REGISTER) == I2C_Register_PECR) || \ - ((REGISTER) == I2C_Register_RXDR) || \ - ((REGISTER) == I2C_Register_TXDR)) -/** - * @} - */ - -/** @defgroup I2C_interrupts_definition - * @{ - */ - -#define I2C_IT_ERRI I2C_CR1_ERRIE -#define I2C_IT_TCI I2C_CR1_TCIE -#define I2C_IT_STOPI I2C_CR1_STOPIE -#define I2C_IT_NACKI I2C_CR1_NACKIE -#define I2C_IT_ADDRI I2C_CR1_ADDRIE -#define I2C_IT_RXI I2C_CR1_RXIE -#define I2C_IT_TXI I2C_CR1_TXIE - -#define IS_I2C_CONFIG_IT(IT) ((((IT) & (uint32_t)0xFFFFFF01) == 0x00) && ((IT) != 0x00)) - -/** - * @} - */ - -/** @defgroup I2C_flags_definition - * @{ - */ - -#define I2C_FLAG_TXE I2C_ISR_TXE -#define I2C_FLAG_TXIS I2C_ISR_TXIS -#define I2C_FLAG_RXNE I2C_ISR_RXNE -#define I2C_FLAG_ADDR I2C_ISR_ADDR -#define I2C_FLAG_NACKF I2C_ISR_NACKF -#define I2C_FLAG_STOPF I2C_ISR_STOPF -#define I2C_FLAG_TC I2C_ISR_TC -#define I2C_FLAG_TCR I2C_ISR_TCR -#define I2C_FLAG_BERR I2C_ISR_BERR -#define I2C_FLAG_ARLO I2C_ISR_ARLO -#define I2C_FLAG_OVR I2C_ISR_OVR -#define I2C_FLAG_PECERR I2C_ISR_PECERR -#define I2C_FLAG_TIMEOUT I2C_ISR_TIMEOUT -#define I2C_FLAG_ALERT I2C_ISR_ALERT -#define I2C_FLAG_BUSY I2C_ISR_BUSY - -#define IS_I2C_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFF4000) == 0x00) && ((FLAG) != 0x00)) - -#define IS_I2C_GET_FLAG(FLAG) (((FLAG) == I2C_FLAG_TXE) || ((FLAG) == I2C_FLAG_TXIS) || \ - ((FLAG) == I2C_FLAG_RXNE) || ((FLAG) == I2C_FLAG_ADDR) || \ - ((FLAG) == I2C_FLAG_NACKF) || ((FLAG) == I2C_FLAG_STOPF) || \ - ((FLAG) == I2C_FLAG_TC) || ((FLAG) == I2C_FLAG_TCR) || \ - ((FLAG) == I2C_FLAG_BERR) || ((FLAG) == I2C_FLAG_ARLO) || \ - ((FLAG) == I2C_FLAG_OVR) || ((FLAG) == I2C_FLAG_PECERR) || \ - ((FLAG) == I2C_FLAG_TIMEOUT) || ((FLAG) == I2C_FLAG_ALERT) || \ - ((FLAG) == I2C_FLAG_BUSY)) - -/** - * @} - */ - - -/** @defgroup I2C_interrupts_definition - * @{ - */ - -#define I2C_IT_TXIS I2C_ISR_TXIS -#define I2C_IT_RXNE I2C_ISR_RXNE -#define I2C_IT_ADDR I2C_ISR_ADDR -#define I2C_IT_NACKF I2C_ISR_NACKF -#define I2C_IT_STOPF I2C_ISR_STOPF -#define I2C_IT_TC I2C_ISR_TC -#define I2C_IT_TCR I2C_ISR_TCR -#define I2C_IT_BERR I2C_ISR_BERR -#define I2C_IT_ARLO I2C_ISR_ARLO -#define I2C_IT_OVR I2C_ISR_OVR -#define I2C_IT_PECERR I2C_ISR_PECERR -#define I2C_IT_TIMEOUT I2C_ISR_TIMEOUT -#define I2C_IT_ALERT I2C_ISR_ALERT - -#define IS_I2C_CLEAR_IT(IT) ((((IT) & (uint32_t)0xFFFFC001) == 0x00) && ((IT) != 0x00)) - -#define IS_I2C_GET_IT(IT) (((IT) == I2C_IT_TXIS) || ((IT) == I2C_IT_RXNE) || \ - ((IT) == I2C_IT_ADDR) || ((IT) == I2C_IT_NACKF) || \ - ((IT) == I2C_IT_STOPF) || ((IT) == I2C_IT_TC) || \ - ((IT) == I2C_IT_TCR) || ((IT) == I2C_IT_BERR) || \ - ((IT) == I2C_IT_ARLO) || ((IT) == I2C_IT_OVR) || \ - ((IT) == I2C_IT_PECERR) || ((IT) == I2C_IT_TIMEOUT) || \ - ((IT) == I2C_IT_ALERT)) - - -/** - * @} - */ - -/** @defgroup I2C_ReloadEndMode_definition - * @{ - */ - -#define I2C_Reload_Mode I2C_CR2_RELOAD -#define I2C_AutoEnd_Mode I2C_CR2_AUTOEND -#define I2C_SoftEnd_Mode ((uint32_t)0x00000000) - - -#define IS_RELOAD_END_MODE(MODE) (((MODE) == I2C_Reload_Mode) || \ - ((MODE) == I2C_AutoEnd_Mode) || \ - ((MODE) == I2C_SoftEnd_Mode)) - - -/** - * @} - */ - -/** @defgroup I2C_StartStopMode_definition - * @{ - */ - -#define I2C_No_StartStop ((uint32_t)0x00000000) -#define I2C_Generate_Stop I2C_CR2_STOP -#define I2C_Generate_Start_Read (uint32_t)(I2C_CR2_START | I2C_CR2_RD_WRN) -#define I2C_Generate_Start_Write I2C_CR2_START - - -#define IS_START_STOP_MODE(MODE) (((MODE) == I2C_Generate_Stop) || \ - ((MODE) == I2C_Generate_Start_Read) || \ - ((MODE) == I2C_Generate_Start_Write) || \ - ((MODE) == I2C_No_StartStop)) - - -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions ------------------------------------------------------- */ - - -/* Initialization and Configuration functions *********************************/ -void I2C_DeInit(I2C_TypeDef* I2Cx); -void I2C_Init(I2C_TypeDef* I2Cx, I2C_InitTypeDef* I2C_InitStruct); -void I2C_StructInit(I2C_InitTypeDef* I2C_InitStruct); -void I2C_Cmd(I2C_TypeDef* I2Cx, FunctionalState NewState); -void I2C_SoftwareResetCmd(I2C_TypeDef* I2Cx); -void I2C_ITConfig(I2C_TypeDef* I2Cx, uint32_t I2C_IT, FunctionalState NewState); -void I2C_StretchClockCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); -void I2C_DualAddressCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); -void I2C_OwnAddress2Config(I2C_TypeDef* I2Cx, uint16_t Address, uint8_t Mask); -void I2C_GeneralCallCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); -void I2C_SlaveByteControlCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); -void I2C_SlaveAddressConfig(I2C_TypeDef* I2Cx, uint16_t Address); -void I2C_10BitAddressingModeCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); - -/* Communications handling functions ******************************************/ -void I2C_AutoEndCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); -void I2C_ReloadCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); -void I2C_NumberOfBytesConfig(I2C_TypeDef* I2Cx, uint8_t Number_Bytes); -void I2C_MasterRequestConfig(I2C_TypeDef* I2Cx, uint16_t I2C_Direction); -void I2C_GenerateSTART(I2C_TypeDef* I2Cx, FunctionalState NewState); -void I2C_GenerateSTOP(I2C_TypeDef* I2Cx, FunctionalState NewState); -void I2C_10BitAddressHeaderCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); -void I2C_AcknowledgeConfig(I2C_TypeDef* I2Cx, FunctionalState NewState); -uint8_t I2C_GetAddressMatched(I2C_TypeDef* I2Cx); -uint16_t I2C_GetTransferDirection(I2C_TypeDef* I2Cx); -void I2C_TransferHandling(I2C_TypeDef* I2Cx, uint16_t Address, uint8_t Number_Bytes, uint32_t ReloadEndMode, uint32_t StartStopMode); - -/* SMBUS management functions ************************************************/ -void I2C_SMBusAlertCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); -void I2C_ClockTimeoutCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); -void I2C_ExtendedClockTimeoutCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); -void I2C_IdleClockTimeoutCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); -void I2C_TimeoutAConfig(I2C_TypeDef* I2Cx, uint16_t Timeout); -void I2C_TimeoutBConfig(I2C_TypeDef* I2Cx, uint16_t Timeout); -void I2C_CalculatePEC(I2C_TypeDef* I2Cx, FunctionalState NewState); -void I2C_PECRequestCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); -uint8_t I2C_GetPEC(I2C_TypeDef* I2Cx); - -/* I2C registers management functions *****************************************/ -uint32_t I2C_ReadRegister(I2C_TypeDef* I2Cx, uint8_t I2C_Register); - -/* Data transfers management functions ****************************************/ -void I2C_SendData(I2C_TypeDef* I2Cx, uint8_t Data); -uint8_t I2C_ReceiveData(I2C_TypeDef* I2Cx); - -/* DMA transfers management functions *****************************************/ -void I2C_DMACmd(I2C_TypeDef* I2Cx, uint32_t I2C_DMAReq, FunctionalState NewState); - -/* Interrupts and flags management functions **********************************/ -FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG); -void I2C_ClearFlag(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG); -ITStatus I2C_GetITStatus(I2C_TypeDef* I2Cx, uint32_t I2C_IT); -void I2C_ClearITPendingBit(I2C_TypeDef* I2Cx, uint32_t I2C_IT); - - -#ifdef __cplusplus -} -#endif - -#endif /*__FT32F0XX_I2C_H */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT FMD *****END OF FILE****/ diff --git a/bsp/ft32/libraries/FT32F0xx/FT32F0xx_Driver/Inc/ft32f0xx_iwdg.h b/bsp/ft32/libraries/FT32F0xx/FT32F0xx_Driver/Inc/ft32f0xx_iwdg.h deleted file mode 100644 index b3be18a7a74..00000000000 --- a/bsp/ft32/libraries/FT32F0xx/FT32F0xx_Driver/Inc/ft32f0xx_iwdg.h +++ /dev/null @@ -1,121 +0,0 @@ -/** - ****************************************************************************** - * @file ft32f0xx_iwdg.h - * @author FMD AE - * @brief This file contains all the functions prototypes for the IWDG - * firmware library. - * @version V1.0.0 - * @data 2021-07-01 - ****************************************************************************** - */ - - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __FT32F030X8_IWDG_H -#define __FT32F030X8_IWDG_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "ft32f0xx.h" - - -/** @addtogroup IWDG - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup IWDG_Exported_Constants - * @{ - */ - -/** @defgroup IWDG_WriteAccess - * @{ - */ - -#define IWDG_WriteAccess_Enable ((uint16_t)0x5555) -#define IWDG_WriteAccess_Disable ((uint16_t)0x0000) -#define IS_IWDG_WRITE_ACCESS(ACCESS) (((ACCESS) == IWDG_WriteAccess_Enable) || \ - ((ACCESS) == IWDG_WriteAccess_Disable)) -/** - * @} - */ - -/** @defgroup IWDG_prescaler - * @{ - */ - -#define IWDG_Prescaler_4 ((uint8_t)0x00) -#define IWDG_Prescaler_8 ((uint8_t)0x01) -#define IWDG_Prescaler_16 ((uint8_t)0x02) -#define IWDG_Prescaler_32 ((uint8_t)0x03) -#define IWDG_Prescaler_64 ((uint8_t)0x04) -#define IWDG_Prescaler_128 ((uint8_t)0x05) -#define IWDG_Prescaler_256 ((uint8_t)0x06) -#define IS_IWDG_PRESCALER(PRESCALER) (((PRESCALER) == IWDG_Prescaler_4) || \ - ((PRESCALER) == IWDG_Prescaler_8) || \ - ((PRESCALER) == IWDG_Prescaler_16) || \ - ((PRESCALER) == IWDG_Prescaler_32) || \ - ((PRESCALER) == IWDG_Prescaler_64) || \ - ((PRESCALER) == IWDG_Prescaler_128)|| \ - ((PRESCALER) == IWDG_Prescaler_256)) -/** - * @} - */ - -/** @defgroup IWDG_Flag - * @{ - */ - -#define IWDG_FLAG_PVU IWDG_SR_PVU -#define IWDG_FLAG_RVU IWDG_SR_RVU -#define IWDG_FLAG_WVU IWDG_SR_WVU -#define IS_IWDG_FLAG(FLAG) (((FLAG) == IWDG_FLAG_PVU) || ((FLAG) == IWDG_FLAG_RVU) || \ - ((FLAG) == IWDG_FLAG_WVU)) - -#define IS_IWDG_RELOAD(RELOAD) ((RELOAD) <= 0xFFF) - -#define IS_IWDG_WINDOW_VALUE(VALUE) ((VALUE) <= 0xFFF) -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions ------------------------------------------------------- */ - -/* Prescaler and Counter configuration functions ******************************/ -void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess); -void IWDG_SetPrescaler(uint8_t IWDG_Prescaler); -void IWDG_SetReload(uint16_t Reload); -void IWDG_ReloadCounter(void); -void IWDG_SetWindowValue(uint16_t WindowValue); - -/* IWDG activation function ***************************************************/ -void IWDG_Enable(void); - -/* Flag management function ***************************************************/ -FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG); - -#ifdef __cplusplus -} -#endif - -#endif /* __FT32F0XX_IWDG_H */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT FMD *****END OF FILE****/ diff --git a/bsp/ft32/libraries/FT32F0xx/FT32F0xx_Driver/Inc/ft32f0xx_misc.h b/bsp/ft32/libraries/FT32F0xx/FT32F0xx_Driver/Inc/ft32f0xx_misc.h deleted file mode 100644 index 45e08bcb76b..00000000000 --- a/bsp/ft32/libraries/FT32F0xx/FT32F0xx_Driver/Inc/ft32f0xx_misc.h +++ /dev/null @@ -1,124 +0,0 @@ -/** - ****************************************************************************** - * @file ft32f0xx_misc.h - * @author FMD AE - * @brief This file contains all the functions prototypes for the miscellaneous - * firmware library functions (add-on to CMSIS functions). - * @version V1.0.0 - * @data 2021-07-01 - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __FT32F0XX_MISC_H -#define __FT32F0XX_MISC_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "ft32f0xx.h" - - - -/** @addtogroup MISC - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ - -/** - * @brief NVIC Init Structure definition - */ - -typedef struct -{ - uint8_t NVIC_IRQChannel; /*!< Specifies the IRQ channel to be enabled or disabled. - This parameter can be a value of @ref IRQn_Type - (For the complete FT32 Devices IRQ Channels list, - please refer to ft32f0xx.h file) */ - - uint8_t NVIC_IRQChannelPriority; /*!< Specifies the priority level for the IRQ channel specified - in NVIC_IRQChannel. This parameter can be a value - between 0 and 3. */ - - FunctionalState NVIC_IRQChannelCmd; /*!< Specifies whether the IRQ channel defined in NVIC_IRQChannel - will be enabled or disabled. - This parameter can be set either to ENABLE or DISABLE */ -} NVIC_InitTypeDef; - -/** - * -@verbatim - -@endverbatim -*/ - -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup MISC_Exported_Constants - * @{ - */ - -/** @defgroup MISC_System_Low_Power - * @{ - */ - -#define NVIC_LP_SEVONPEND ((uint8_t)0x10) -#define NVIC_LP_SLEEPDEEP ((uint8_t)0x04) -#define NVIC_LP_SLEEPONEXIT ((uint8_t)0x02) -#define IS_NVIC_LP(LP) (((LP) == NVIC_LP_SEVONPEND) || \ - ((LP) == NVIC_LP_SLEEPDEEP) || \ - ((LP) == NVIC_LP_SLEEPONEXIT)) -/** - * @} - */ - -/** @defgroup MISC_Preemption_Priority_Group - * @{ - */ -#define IS_NVIC_PRIORITY(PRIORITY) ((PRIORITY) < 0x04) - -/** - * @} - */ - -/** @defgroup MISC_SysTick_clock_source - * @{ - */ - -#define SysTick_CLKSource_HCLK_Div8 ((uint32_t)0xFFFFFFFB) -#define SysTick_CLKSource_HCLK ((uint32_t)0x00000004) -#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SysTick_CLKSource_HCLK) || \ - ((SOURCE) == SysTick_CLKSource_HCLK_Div8)) -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions ------------------------------------------------------- */ - -void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct); -void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState); -void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource); - -#ifdef __cplusplus -} -#endif - -#endif /* __FT32F0XX_MISC_H */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT FMD *****END OF FILE****/ diff --git a/bsp/ft32/libraries/FT32F0xx/FT32F0xx_Driver/Inc/ft32f0xx_opa.h b/bsp/ft32/libraries/FT32F0xx/FT32F0xx_Driver/Inc/ft32f0xx_opa.h deleted file mode 100644 index 680c402cf85..00000000000 --- a/bsp/ft32/libraries/FT32F0xx/FT32F0xx_Driver/Inc/ft32f0xx_opa.h +++ /dev/null @@ -1,232 +0,0 @@ -/** - ****************************************************************************** - * @file ft32f0xx_opa.h - * @author FMD AE - * @brief This file contains all the functions prototypes for the OPA firmware - * library. - * @version V1.0.0 - * @data 2021-07-01 - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __FT32F0XX_OPA_H -#define __FT32F0XX_OPA_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "ft32f0xx.h" - - - -/** @addtogroup OPA - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ - -/** - * @brief OPA Init structure definition - */ - -typedef struct -{ - - uint32_t OPA_OP0PSel; /*!< Select the positive input of the OPA. - This parameter can be a value of @ref OPA_OP0PSel */ - - uint32_t OPA_OP0NSel; /*!< Select the negative input of the OPA. - This parameter can be a value of @ref OPA_OP0NSel */ - - uint32_t OPA_OP0FR; /*!< Selects The feedback resister of the OPA. - This parameter can be a value of @ref OPA_OP0FR */ - - uint32_t OPA_OP0FCAPE; /*!< Selects The compensate cap of the OPA. - This parameter can be a value of @ref OPA_OP0FCAPE */ - - uint32_t OPA_OPTODIG; /*!< Selects The output to REG of the OPA. - This parameter can be a value of @ref OPA_OPTODIG */ - - uint32_t OPA_OPTOIO; /*!< Selects The output to PA0 of the OPA. - This parameter can be a value of @ref OPA_OPTOIO */ - -}OPA_InitTypeDef; - -/* Exported constants --------------------------------------------------------*/ -/** - * @} - */ -/** @defgroup OPA_Exported_Constants - * @{ - */ -#define IS_OPA_ALL_PERIPH(PERIPH) (((PERIPH) == OPA) || ((PERIPH) == OPA2)) - -/** @defgroup OPA_OP0PSel - * @{ - */ - -#define OPA_VIP_SEL_PA1 ((uint32_t)0x00000000) -#define OPA_VIP_SEL_GND ((uint32_t)0x00008000) - -#define OPA1_VIP_SEL_PA1 OPA_VIP_SEL_PA1 -#define OPA1_VIP_SEL_GND OPA_VIP_SEL_GND - -#define OPA2_VIP_SEL_PA3 ((uint32_t)0x00000000) -#define OPA2_VIP_SEL_PA4 ((uint32_t)0x00020000) -#define OPA2_VIP_SEL_GND ((uint32_t)0x00008000) - -#define IS_OPA_VIP_SEL(INPUT) ( ((INPUT) == OPA_VIP_SEL_PA1) || \ - ((INPUT) == OPA2_VIP_SEL_PA4) || \ - ((INPUT) == OPA_VIP_SEL_GND) ) - -/** - * @} - */ - -/** @defgroup OPA_OP0NSel - * @{ - */ -#define OPA_VIN_SEL_GND ((uint32_t)0x00000000) -#define OPA_VIN_SEL_PA2 ((uint32_t)0x00002000) -#define OPA_VIN_SEL_R4K_PA2 ((uint32_t)0x00004000) -#define OPA_VIN_SEL_R4K_GND ((uint32_t)0x00006000) - -#define OPA2_VIN_SEL_GND ((uint32_t)0x00000000) -#define OPA2_VIN_SEL_PF4 ((uint32_t)0x00002000) -#define OPA2_VIN_SEL_R4K_PF4 ((uint32_t)0x00004000) -#define OPA2_VIN_SEL_R4K_GND ((uint32_t)0x00006000) - -#define IS_OPA_VIN_SEL(INPUT) ( ((INPUT) == OPA_VIN_SEL_GND) || \ - ((INPUT) == OPA_VIN_SEL_PA2) || \ - ((INPUT) == OPA_VIN_SEL_R4K_PA2) || \ - ((INPUT) == OPA_VIN_SEL_R4K_GND) ) - -/** - * @} - */ - -/** @defgroup OPA_OP0FR - * @{ - */ - -#define OPA_FR_SEL_NORES ((uint32_t)0x00000000) -#define OPA_FR_SEL_40K ((uint32_t)0x00001000) -#define OPA_FR_SEL_80K ((uint32_t)0x00001400) -#define OPA_FR_SEL_160K ((uint32_t)0x00001800) -#define OPA_FR_SEL_320K ((uint32_t)0x00001C00) - -#define OPA2_FR_SEL_NORES ((uint32_t)0x00000000) -#define OPA2_FR_SEL_40K ((uint32_t)0x00001000) -#define OPA2_FR_SEL_80K ((uint32_t)0x00001400) -#define OPA2_FR_SEL_160K ((uint32_t)0x00001800) -#define OPA2_FR_SEL_320K ((uint32_t)0x00001C00) - -#define IS_OPA_FR_SEL(INPUT) ( ((INPUT) == OPA_FR_SEL_NORES) || \ - ((INPUT) == OPA_FR_SEL_40K) || \ - ((INPUT) == OPA_FR_SEL_80K) || \ - ((INPUT) == OPA_FR_SEL_160K) || \ - ((INPUT) == OPA_FR_SEL_320K) ) - -/** - * @} - */ - -/** @defgroup OPA_OP0FCAPE - * @{ - */ - -#define OPA_FCAP_SEL_EN ((uint32_t)0x00000000) -#define OPA_FCAP_SEL_DIS ((uint32_t)0x00000200) - -#define OPA2_FCAP_SEL_EN ((uint32_t)0x00000000) -#define OPA2_FCAP_SEL_DIS ((uint32_t)0x00000200) - -#define IS_OPA_FCAP_SEL(INPUT) (((INPUT) == OPA_FCAP_SEL_EN) || \ - ((INPUT) == OPA_FCAP_SEL_DIS)) - - -/** - * @} - */ - -/** @defgroup OPA_OPTODIG - * @{ - */ - -#define OPA_ODIG_SEL_DIS ((uint32_t)0x00000000) -#define OPA_ODIG_SEL_EN ((uint32_t)0x00000080) - -#define OPA2_ODIG_SEL_DIS ((uint32_t)0x00000000) -#define OPA2_ODIG_SEL_EN ((uint32_t)0x00000080) - -#define IS_OPA_ODIG_SEL(INPUT) (((INPUT) == OPA_ODIG_SEL_DIS) || \ - ((INPUT) == OPA_ODIG_SEL_EN)) - - -/** - * @} - */ - -/** @defgroup OPA_OPTOIO - * @{ - */ - -#define OPA_OIO_SEL_DIS ((uint32_t)0x00000000) -#define OPA_OIO_SEL_EN ((uint32_t)0x00000040) - -#define OPA2_OIO_SEL_DIS ((uint32_t)0x00000000) -#define OPA2_OIO_SEL_EN ((uint32_t)0x00000040) - -#define IS_OPA_OIO_SEL(INPUT) (((INPUT) == OPA_OIO_SEL_DIS) || \ - ((INPUT) == OPA_OIO_SEL_EN)) - - -#define OPA_OutputLevel_High ((uint32_t)0x00010000) -#define OPA_OutputLevel_Low ((uint32_t)0x00000000) - - -#define IS_OPA_OUTPUT_LEVEL(LEVEL) ( ((LEVEL) == OPA_OutputLevel_High) || \ - ((LEVEL) == OPA_OutputLevel_Low)) - - - - -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions ------------------------------------------------------- */ - -/* Function used to set the OPA configuration to the default reset state ****/ -void OPA_DeInit(OPA_TypeDef* OPAx); - -/* Initialization and Configuration functions *********************************/ -void OPA_Init(OPA_TypeDef* OPAx, OPA_InitTypeDef* OPA_InitStruct); -void OPA_StructInit(OPA_InitTypeDef* OPA_InitStruct); -void OPA_Cmd(OPA_TypeDef* OPAx, FunctionalState NewState); -uint32_t OPA_GetOutputLevel(OPA_TypeDef* OPAx, uint32_t OPA_OutLevel); -uint8_t OPA_Cali(OPA_TypeDef* OPAx); - -#ifdef __cplusplus -} -#endif - -#endif /*__FT32F0XX_OPA_H */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT FMD *****END OF FILE****/ diff --git a/bsp/ft32/libraries/FT32F0xx/FT32F0xx_Driver/Inc/ft32f0xx_pwr.h b/bsp/ft32/libraries/FT32F0xx/FT32F0xx_Driver/Inc/ft32f0xx_pwr.h deleted file mode 100644 index 95ceb16616c..00000000000 --- a/bsp/ft32/libraries/FT32F0xx/FT32F0xx_Driver/Inc/ft32f0xx_pwr.h +++ /dev/null @@ -1,190 +0,0 @@ -/** - ****************************************************************************** - * @file ft32f0xx_pwr.h - * @author FMD AE - * @brief This file contains all the functions prototypes for the PWR firmware - * library. - * @version V1.0.0 - * @data 2021-07-01 - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __FT32F0XX_PWR_H -#define __FT32F0XX_PWR_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "ft32f0xx.h" - - - -/** @addtogroup PWR - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ - -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup PWR_Exported_Constants - * @{ - */ - -/** @defgroup PWR_PVD_detection_level - * @brief - * @{ - */ - -#define PWR_PVDLevel_0 PWR_CR_PLS_LEV0 -#define PWR_PVDLevel_1 PWR_CR_PLS_LEV1 -#define PWR_PVDLevel_2 PWR_CR_PLS_LEV2 -#define PWR_PVDLevel_3 PWR_CR_PLS_LEV3 -#define PWR_PVDLevel_4 PWR_CR_PLS_LEV4 -#define PWR_PVDLevel_5 PWR_CR_PLS_LEV5 -#define PWR_PVDLevel_6 PWR_CR_PLS_LEV6 -#define PWR_PVDLevel_7 PWR_CR_PLS_LEV7 -#define PWR_PVDLevel_8 PWR_CR_PLS_LEV8 -#define PWR_PVDLevel_9 PWR_CR_PLS_LEV9 -#define PWR_PVDLevel_10 PWR_CR_PLS_LEV10 -#define PWR_PVDLevel_11 PWR_CR_PLS_LEV11 -#define PWR_PVDLevel_12 PWR_CR_PLS_LEV12 -#define PWR_PVDLevel_13 PWR_CR_PLS_LEV13 -#define PWR_PVDLevel_14 PWR_CR_PLS_LEV14 -#define PWR_PVDLevel_15 PWR_CR_PLS_LEV15 - -#define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLevel_0) || ((LEVEL) == PWR_PVDLevel_1)|| \ - ((LEVEL) == PWR_PVDLevel_2) || ((LEVEL) == PWR_PVDLevel_3)|| \ - ((LEVEL) == PWR_PVDLevel_4) || ((LEVEL) == PWR_PVDLevel_5)|| \ - ((LEVEL) == PWR_PVDLevel_6) || ((LEVEL) == PWR_PVDLevel_7)|| \ - ((LEVEL) == PWR_PVDLevel_8) || ((LEVEL) == PWR_PVDLevel_9)|| \ - ((LEVEL) == PWR_PVDLevel_10) || ((LEVEL) == PWR_PVDLevel_11)|| \ - ((LEVEL) == PWR_PVDLevel_12) || ((LEVEL) == PWR_PVDLevel_13)|| \ - ((LEVEL) == PWR_PVDLevel_14) || ((LEVEL) == PWR_PVDLevel_15)) -/** - * @} - */ - -/** @defgroup PWR_WakeUp_Pins - * @{ - */ - -#define PWR_WakeUpPin_1 PWR_CSR_EWUP1 -#define PWR_WakeUpPin_2 PWR_CSR_EWUP2 -#define PWR_WakeUpPin_3 PWR_CSR_EWUP3 -#define PWR_WakeUpPin_4 PWR_CSR_EWUP4 -#define PWR_WakeUpPin_5 PWR_CSR_EWUP5 -#define PWR_WakeUpPin_6 PWR_CSR_EWUP6 -#define PWR_WakeUpPin_7 PWR_CSR_EWUP7 -#define PWR_WakeUpPin_8 PWR_CSR_EWUP8 -#define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WakeUpPin_1) || ((PIN) == PWR_WakeUpPin_2) || \ - ((PIN) == PWR_WakeUpPin_3) || ((PIN) == PWR_WakeUpPin_4) || \ - ((PIN) == PWR_WakeUpPin_5) || ((PIN) == PWR_WakeUpPin_6) || \ - ((PIN) == PWR_WakeUpPin_7) || ((PIN) == PWR_WakeUpPin_8)) -/** - * @} - */ - - -/** @defgroup PWR_Regulator_state_is_Sleep_STOP_mode - * @{ - */ - -#define PWR_Regulator_ON ((uint32_t)0x00000000) -#define PWR_Regulator_LowPower PWR_CR_LPSDSR -#define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_Regulator_ON) || \ - ((REGULATOR) == PWR_Regulator_LowPower)) -/** - * @} - */ - -/** @defgroup PWR_SLEEP_mode_entry - * @{ - */ - -#define PWR_SLEEPEntry_WFI ((uint8_t)0x01) -#define PWR_SLEEPEntry_WFE ((uint8_t)0x02) -#define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPEntry_WFI) || ((ENTRY) == PWR_SLEEPEntry_WFE)) - -/** - * @} - */ - -/** @defgroup PWR_STOP_mode_entry - * @{ - */ - -#define PWR_STOPEntry_WFI ((uint8_t)0x01) -#define PWR_STOPEntry_WFE ((uint8_t)0x02) -#define PWR_STOPEntry_SLEEPONEXIT ((uint8_t)0x03) -#define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPEntry_WFI) || ((ENTRY) == PWR_STOPEntry_WFE) ||\ - ((ENTRY) == PWR_STOPEntry_SLEEPONEXIT)) - -/** - * @} - */ - -/** @defgroup PWR_Flag - * @{ - */ - -#define PWR_FLAG_WU PWR_CSR_WUF -#define PWR_FLAG_SB PWR_CSR_SBF -#define PWR_FLAG_PVDO PWR_CSR_PVDO -#define PWR_FLAG_VREFINTRDY PWR_CSR_VREFINTRDYF - -#define IS_PWR_GET_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB) || \ - ((FLAG) == PWR_FLAG_PVDO) || ((FLAG) == PWR_FLAG_VREFINTRDY)) - -#define IS_PWR_CLEAR_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB)) -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions ------------------------------------------------------- */ - -/* Function used to set the PWR configuration to the default reset state ******/ -void PWR_DeInit(void); - -/* Backup Domain Access function **********************************************/ -void PWR_BackupAccessCmd(FunctionalState NewState); - -/* PVD configuration functions ************************************************/ -void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel); -void PWR_PVDCmd(FunctionalState NewState); - -/* WakeUp pins configuration functions ****************************************/ -void PWR_WakeUpPinCmd(uint32_t PWR_WakeUpPin, FunctionalState NewState); - -/* Low Power modes configuration functions ************************************/ -void PWR_EnterSleepMode(uint8_t PWR_SLEEPEntry); -void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry); -void PWR_EnterSTANDBYMode(void); - -/* Flags management functions *************************************************/ -FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG); -void PWR_ClearFlag(uint32_t PWR_FLAG); - -#ifdef __cplusplus -} -#endif - -#endif /* __FT32F0XX_PWR_H */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT FMD *****END OF FILE****/ diff --git a/bsp/ft32/libraries/FT32F0xx/FT32F0xx_Driver/Inc/ft32f0xx_rcc.h b/bsp/ft32/libraries/FT32F0xx/FT32F0xx_Driver/Inc/ft32f0xx_rcc.h deleted file mode 100644 index ba1826cc375..00000000000 --- a/bsp/ft32/libraries/FT32F0xx/FT32F0xx_Driver/Inc/ft32f0xx_rcc.h +++ /dev/null @@ -1,597 +0,0 @@ -/** - ****************************************************************************** - * @file ft32f0xx_rcc.h - * @author FMD AE - * @brief This file contains all the functions prototypes for the RCC - * firmware library. - * @version V1.0.0 - * @data 2021-07-01 - ****************************************************************************** - */ - - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __FT32F0XX_RCC_H -#define __FT32F0XX_RCC_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "ft32f0xx.h" - - -/** @addtogroup RCC - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ - -typedef struct -{ - uint32_t SYSCLK_Frequency; - uint32_t HCLK_Frequency; - uint32_t PCLK_Frequency; - uint32_t ADCCLK_Frequency; - uint32_t CECCLK_Frequency; - uint32_t I2C1CLK_Frequency; - uint32_t USART1CLK_Frequency; - uint32_t USART2CLK_Frequency; - uint32_t USART3CLK_Frequency; - uint32_t USBCLK_Frequency; -}RCC_ClocksTypeDef; - -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup RCC_Exported_Constants - * @{ - */ - -/** @defgroup RCC_HSE_configuration - * @{ - */ - -#define RCC_HSE_OFF ((uint8_t)0x00) -#define RCC_HSE_ON ((uint8_t)0x01) -#define RCC_HSE_Bypass ((uint8_t)0x05) -#define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \ - ((HSE) == RCC_HSE_Bypass)) - -/** - * @} - */ - -/** @defgroup RCC_PLL_Clock_Source - * @{ - */ - -#define RCC_PLLSource_HSI_Div2 RCC_CFGR_PLLSRC_HSI_Div2 -#define RCC_PLLSource_PREDIV1 RCC_CFGR_PLLSRC_HSE_PREDIV /* Old HSEPREDIV1 bit definition, maintained for legacy purpose */ -#define RCC_PLLSource_HSE RCC_CFGR_PLLSRC_HSE_PREDIV -#define RCC_PLLSource_HSI48 RCC_CFGR_PLLSRC_HSI48_PREDIV -#define RCC_PLLSource_HSI RCC_CFGR_PLLSRC_HSI_PREDIV - -#define IS_RCC_PLL_SOURCE(SOURCE) (((SOURCE) == RCC_PLLSource_HSI_Div2) || \ - ((SOURCE) == RCC_PLLSource_HSI48) || \ - ((SOURCE) == RCC_PLLSource_HSI) || \ - ((SOURCE) == RCC_PLLSource_HSE) || \ - ((SOURCE) == RCC_PLLSource_PREDIV1)) -/** - * @} - */ - -/** @defgroup RCC_PLL_Multiplication_Factor - * @{ - */ - -#define RCC_PLLMul_2 RCC_CFGR_PLLMULL2 -#define RCC_PLLMul_3 RCC_CFGR_PLLMULL3 -#define RCC_PLLMul_4 RCC_CFGR_PLLMULL4 -#define RCC_PLLMul_5 RCC_CFGR_PLLMULL5 -#define RCC_PLLMul_6 RCC_CFGR_PLLMULL6 -#define RCC_PLLMul_7 RCC_CFGR_PLLMULL7 -#define RCC_PLLMul_8 RCC_CFGR_PLLMULL8 -#define RCC_PLLMul_9 RCC_CFGR_PLLMULL9 -#define RCC_PLLMul_10 RCC_CFGR_PLLMULL10 -#define RCC_PLLMul_11 RCC_CFGR_PLLMULL11 -#define RCC_PLLMul_12 RCC_CFGR_PLLMULL12 -#define RCC_PLLMul_13 RCC_CFGR_PLLMULL13 -#define RCC_PLLMul_14 RCC_CFGR_PLLMULL14 -#define RCC_PLLMul_15 RCC_CFGR_PLLMULL15 -#define RCC_PLLMul_16 RCC_CFGR_PLLMULL16 -#define IS_RCC_PLL_MUL(MUL) (((MUL) == RCC_PLLMul_2) || ((MUL) == RCC_PLLMul_3) || \ - ((MUL) == RCC_PLLMul_4) || ((MUL) == RCC_PLLMul_5) || \ - ((MUL) == RCC_PLLMul_6) || ((MUL) == RCC_PLLMul_7) || \ - ((MUL) == RCC_PLLMul_8) || ((MUL) == RCC_PLLMul_9) || \ - ((MUL) == RCC_PLLMul_10) || ((MUL) == RCC_PLLMul_11) || \ - ((MUL) == RCC_PLLMul_12) || ((MUL) == RCC_PLLMul_13) || \ - ((MUL) == RCC_PLLMul_14) || ((MUL) == RCC_PLLMul_15) || \ - ((MUL) == RCC_PLLMul_16)) -/** - * @} - */ - -/** @defgroup RCC_PREDIV1_division_factor - * @{ - */ -#define RCC_PREDIV1_Div1 RCC_CFGR2_PREDIV1_DIV1 -#define RCC_PREDIV1_Div2 RCC_CFGR2_PREDIV1_DIV2 -#define RCC_PREDIV1_Div3 RCC_CFGR2_PREDIV1_DIV3 -#define RCC_PREDIV1_Div4 RCC_CFGR2_PREDIV1_DIV4 -#define RCC_PREDIV1_Div5 RCC_CFGR2_PREDIV1_DIV5 -#define RCC_PREDIV1_Div6 RCC_CFGR2_PREDIV1_DIV6 -#define RCC_PREDIV1_Div7 RCC_CFGR2_PREDIV1_DIV7 -#define RCC_PREDIV1_Div8 RCC_CFGR2_PREDIV1_DIV8 -#define RCC_PREDIV1_Div9 RCC_CFGR2_PREDIV1_DIV9 -#define RCC_PREDIV1_Div10 RCC_CFGR2_PREDIV1_DIV10 -#define RCC_PREDIV1_Div11 RCC_CFGR2_PREDIV1_DIV11 -#define RCC_PREDIV1_Div12 RCC_CFGR2_PREDIV1_DIV12 -#define RCC_PREDIV1_Div13 RCC_CFGR2_PREDIV1_DIV13 -#define RCC_PREDIV1_Div14 RCC_CFGR2_PREDIV1_DIV14 -#define RCC_PREDIV1_Div15 RCC_CFGR2_PREDIV1_DIV15 -#define RCC_PREDIV1_Div16 RCC_CFGR2_PREDIV1_DIV16 - -#define IS_RCC_PREDIV1(PREDIV1) (((PREDIV1) == RCC_PREDIV1_Div1) || ((PREDIV1) == RCC_PREDIV1_Div2) || \ - ((PREDIV1) == RCC_PREDIV1_Div3) || ((PREDIV1) == RCC_PREDIV1_Div4) || \ - ((PREDIV1) == RCC_PREDIV1_Div5) || ((PREDIV1) == RCC_PREDIV1_Div6) || \ - ((PREDIV1) == RCC_PREDIV1_Div7) || ((PREDIV1) == RCC_PREDIV1_Div8) || \ - ((PREDIV1) == RCC_PREDIV1_Div9) || ((PREDIV1) == RCC_PREDIV1_Div10) || \ - ((PREDIV1) == RCC_PREDIV1_Div11) || ((PREDIV1) == RCC_PREDIV1_Div12) || \ - ((PREDIV1) == RCC_PREDIV1_Div13) || ((PREDIV1) == RCC_PREDIV1_Div14) || \ - ((PREDIV1) == RCC_PREDIV1_Div15) || ((PREDIV1) == RCC_PREDIV1_Div16)) -/** - * @} - */ - -/** @defgroup RCC_System_Clock_Source - * @{ - */ - -#define RCC_SYSCLKSource_HSI RCC_CFGR_SW_HSI -#define RCC_SYSCLKSource_HSE RCC_CFGR_SW_HSE -#define RCC_SYSCLKSource_PLLCLK RCC_CFGR_SW_PLL -#define RCC_SYSCLKSource_HSI48 RCC_CFGR_SW_HSI48 - -#define IS_RCC_SYSCLK_SOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSource_HSI) || \ - ((SOURCE) == RCC_SYSCLKSource_HSE) || \ - ((SOURCE) == RCC_SYSCLKSource_HSI48) || \ - ((SOURCE) == RCC_SYSCLKSource_PLLCLK)) -/** - * @} - */ - -/** @defgroup RCC_AHB_Clock_Source - * @{ - */ - -#define RCC_SYSCLK_Div1 RCC_CFGR_HPRE_DIV1 -#define RCC_SYSCLK_Div2 RCC_CFGR_HPRE_DIV2 -#define RCC_SYSCLK_Div4 RCC_CFGR_HPRE_DIV4 -#define RCC_SYSCLK_Div8 RCC_CFGR_HPRE_DIV8 -#define RCC_SYSCLK_Div16 RCC_CFGR_HPRE_DIV16 -#define RCC_SYSCLK_Div64 RCC_CFGR_HPRE_DIV64 -#define RCC_SYSCLK_Div128 RCC_CFGR_HPRE_DIV128 -#define RCC_SYSCLK_Div256 RCC_CFGR_HPRE_DIV256 -#define RCC_SYSCLK_Div512 RCC_CFGR_HPRE_DIV512 -#define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_Div1) || ((HCLK) == RCC_SYSCLK_Div2) || \ - ((HCLK) == RCC_SYSCLK_Div4) || ((HCLK) == RCC_SYSCLK_Div8) || \ - ((HCLK) == RCC_SYSCLK_Div16) || ((HCLK) == RCC_SYSCLK_Div64) || \ - ((HCLK) == RCC_SYSCLK_Div128) || ((HCLK) == RCC_SYSCLK_Div256) || \ - ((HCLK) == RCC_SYSCLK_Div512)) -/** - * @} - */ - -/** @defgroup RCC_APB_Clock_Source - * @{ - */ - -#define RCC_HCLK_Div1 RCC_CFGR_PPRE_DIV1 -#define RCC_HCLK_Div2 RCC_CFGR_PPRE_DIV2 -#define RCC_HCLK_Div4 RCC_CFGR_PPRE_DIV4 -#define RCC_HCLK_Div8 RCC_CFGR_PPRE_DIV8 -#define RCC_HCLK_Div16 RCC_CFGR_PPRE_DIV16 -#define IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_Div1) || ((PCLK) == RCC_HCLK_Div2) || \ - ((PCLK) == RCC_HCLK_Div4) || ((PCLK) == RCC_HCLK_Div8) || \ - ((PCLK) == RCC_HCLK_Div16)) -/** - * @} - */ - -/** @defgroup RCC_ADC_clock_source - * @{ - */ -/* These defines are obsolete and kept for legacy purpose only. -Proper ADC clock selection is done within ADC driver by mean of the ADC_ClockModeConfig() function */ -#define RCC_ADCCLK_HSI14 ((uint32_t)0x00000000) -#define RCC_ADCCLK_PCLK_Div2 ((uint32_t)0x01000000) -#define RCC_ADCCLK_PCLK_Div4 ((uint32_t)0x01004000) - -#define IS_RCC_ADCCLK(ADCCLK) (((ADCCLK) == RCC_ADCCLK_HSI14) || ((ADCCLK) == RCC_ADCCLK_PCLK_Div2) || \ - ((ADCCLK) == RCC_ADCCLK_PCLK_Div4)) - -/** - * @} - */ - - -/** - * @} - */ - -/** @defgroup RCC_I2C_clock_source - * @{ - */ - -#define RCC_I2C1CLK_HSI ((uint32_t)0x00000000) -#define RCC_I2C1CLK_SYSCLK RCC_CFGR3_I2C1SW - -#define IS_RCC_I2CCLK(I2CCLK) (((I2CCLK) == RCC_I2C1CLK_HSI) || ((I2CCLK) == RCC_I2C1CLK_SYSCLK)) - -/** - * @} - */ - -/** @defgroup RCC_USB_clock_source - * @brief - * @{ - */ - -#define RCC_USBCLK_HSI48 ((uint32_t)0x00000000) -#define RCC_USBCLK_PLLCLK RCC_CFGR3_USBSW - -#define IS_RCC_USBCLK(USBCLK) (((USBCLK) == RCC_USBCLK_HSI48) || ((USBCLK) == RCC_USBCLK_PLLCLK)) - -/** - * @} - */ - -/** @defgroup RCC_USART_clock_source - * @{ - */ - -#define RCC_USART1CLK_PCLK ((uint32_t)0x10000000) -#define RCC_USART1CLK_SYSCLK ((uint32_t)0x10000001) -#define RCC_USART1CLK_LSE ((uint32_t)0x10000002) -#define RCC_USART1CLK_HSI ((uint32_t)0x10000003) - -#define RCC_USART2CLK_PCLK ((uint32_t)0x20000000) -#define RCC_USART2CLK_SYSCLK ((uint32_t)0x20010000) -#define RCC_USART2CLK_LSE ((uint32_t)0x20020000) -#define RCC_USART2CLK_HSI ((uint32_t)0x20030000) - -#define RCC_USART3CLK_PCLK ((uint32_t)0x30000000) -#define RCC_USART3CLK_SYSCLK ((uint32_t)0x30040000) -#define RCC_USART3CLK_LSE ((uint32_t)0x30080000) -#define RCC_USART3CLK_HSI ((uint32_t)0x300C0000) - - -#define IS_RCC_USARTCLK(USARTCLK) (((USARTCLK) == RCC_USART1CLK_PCLK) || \ - ((USARTCLK) == RCC_USART1CLK_SYSCLK) || \ - ((USARTCLK) == RCC_USART1CLK_LSE) || \ - ((USARTCLK) == RCC_USART1CLK_HSI) || \ - ((USARTCLK) == RCC_USART2CLK_PCLK) || \ - ((USARTCLK) == RCC_USART2CLK_SYSCLK) || \ - ((USARTCLK) == RCC_USART2CLK_LSE) || \ - ((USARTCLK) == RCC_USART2CLK_HSI)|| \ - ((USARTCLK) == RCC_USART3CLK_PCLK) || \ - ((USARTCLK) == RCC_USART3CLK_SYSCLK) || \ - ((USARTCLK) == RCC_USART3CLK_LSE) || \ - ((USARTCLK) == RCC_USART3CLK_HSI)) - -/** - * @} - */ - -/** @defgroup RCC_Interrupt_Source - * @{ - */ - -#define RCC_IT_LSIRDY ((uint8_t)0x01) -#define RCC_IT_LSERDY ((uint8_t)0x02) -#define RCC_IT_HSIRDY ((uint8_t)0x04) -#define RCC_IT_HSERDY ((uint8_t)0x08) -#define RCC_IT_PLLRDY ((uint8_t)0x10) -#define RCC_IT_HSI14RDY ((uint8_t)0x20) -#define RCC_IT_HSI48RDY ((uint8_t)0x40) -#define RCC_IT_CSS ((uint8_t)0x80) - -#define IS_RCC_IT(IT) ((((IT) & (uint8_t)0x80) == 0x00) && ((IT) != 0x00)) - -#define IS_RCC_GET_IT(IT) (((IT) == RCC_IT_LSIRDY) || ((IT) == RCC_IT_LSERDY) || \ - ((IT) == RCC_IT_HSIRDY) || ((IT) == RCC_IT_HSERDY) || \ - ((IT) == RCC_IT_PLLRDY) || ((IT) == RCC_IT_HSI14RDY) || \ - ((IT) == RCC_IT_CSS) || ((IT) == RCC_IT_HSI48RDY)) - -#define IS_RCC_CLEAR_IT(IT) ((IT) != 0x00) - -/** - * @} - */ - -/** @defgroup RCC_LSE_Configuration - * @{ - */ - -#define RCC_LSE_OFF ((uint32_t)0x00000000) -#define RCC_LSE_ON RCC_BDCR_LSEON -#define RCC_LSE_Bypass ((uint32_t)(RCC_BDCR_LSEON | RCC_BDCR_LSEBYP)) -#define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \ - ((LSE) == RCC_LSE_Bypass)) -/** - * @} - */ - -/** @defgroup RCC_RTC_Clock_Source - * @{ - */ - -#define RCC_RTCCLKSource_LSE RCC_BDCR_RTCSEL_LSE -#define RCC_RTCCLKSource_LSI RCC_BDCR_RTCSEL_LSI -#define RCC_RTCCLKSource_HSE_Div32 RCC_BDCR_RTCSEL_HSE - -#define IS_RCC_RTCCLK_SOURCE(SOURCE) (((SOURCE) == RCC_RTCCLKSource_LSE) || \ - ((SOURCE) == RCC_RTCCLKSource_LSI) || \ - ((SOURCE) == RCC_RTCCLKSource_HSE_Div32)) -/** - * @} - */ - -/** @defgroup RCC_LSE_Drive_Configuration - * @{ - */ - -#define RCC_LSEDrive_Low ((uint32_t)0x00000000) -#define RCC_LSEDrive_MediumLow RCC_BDCR_LSEDRV_0 -#define RCC_LSEDrive_MediumHigh RCC_BDCR_LSEDRV_1 -#define RCC_LSEDrive_High RCC_BDCR_LSEDRV -#define IS_RCC_LSE_DRIVE(DRIVE) (((DRIVE) == RCC_LSEDrive_Low) || ((DRIVE) == RCC_LSEDrive_MediumLow) || \ - ((DRIVE) == RCC_LSEDrive_MediumHigh) || ((DRIVE) == RCC_LSEDrive_High)) -/** - * @} - */ - -/** @defgroup RCC_AHB_Peripherals - * @{ - */ - -#define RCC_AHBPeriph_GPIOA RCC_AHBENR_GPIOAEN -#define RCC_AHBPeriph_GPIOB RCC_AHBENR_GPIOBEN -#define RCC_AHBPeriph_GPIOC RCC_AHBENR_GPIOCEN -#define RCC_AHBPeriph_GPIOD RCC_AHBENR_GPIODEN -#define RCC_AHBPeriph_GPIOE RCC_AHBENR_GPIOEEN -#define RCC_AHBPeriph_GPIOF RCC_AHBENR_GPIOFEN -#define RCC_AHBPeriph_TS RCC_AHBENR_TSEN -#define RCC_AHBPeriph_CRC RCC_AHBENR_CRCEN -#define RCC_AHBPeriph_FLITF RCC_AHBENR_FLITFEN -#define RCC_AHBPeriph_SRAM RCC_AHBENR_SRAMEN -#define RCC_AHBPeriph_DMA1 RCC_AHBENR_DMA1EN -#define RCC_AHBPeriph_DMA2 RCC_AHBENR_DMA2EN - -#define IS_RCC_AHB_PERIPH(PERIPH) ((((PERIPH) & 0xFE81FFA8) == 0x00) && ((PERIPH) != 0x00)) -#define IS_RCC_AHB_RST_PERIPH(PERIPH) ((((PERIPH) & 0xFE81FFA8) == 0x00) && ((PERIPH) != 0x00)) - -/** - * @} - */ - -/** @defgroup RCC_APB2_Peripherals - * @{ - */ - -#define RCC_APB2Periph_SYSCFG RCC_APB2ENR_SYSCFGEN -#define RCC_APB2Periph_USART6 RCC_APB2ENR_USART6EN -#define RCC_APB2Periph_USART7 RCC_APB2ENR_USART7EN -#define RCC_APB2Periph_USART8 RCC_APB2ENR_USART8EN -#define RCC_APB2Periph_ADC1 RCC_APB2ENR_ADC1EN -#define RCC_APB2Periph_TIM1 RCC_APB2ENR_TIM1EN -#define RCC_APB2Periph_SPI1 RCC_APB2ENR_SPI1EN -#define RCC_APB2Periph_USART1 RCC_APB2ENR_USART1EN -#define RCC_APB2Periph_TIM15 RCC_APB2ENR_TIM15EN -#define RCC_APB2Periph_TIM16 RCC_APB2ENR_TIM16EN -#define RCC_APB2Periph_TIM17 RCC_APB2ENR_TIM17EN -#define RCC_APB2Periph_DBGMCU RCC_APB2ENR_DBGMCUEN - -#define IS_RCC_APB2_PERIPH(PERIPH) ((((PERIPH) & 0xFFB8A51E) == 0x00) && ((PERIPH) != 0x00)) - -/** - * @} - */ - -/** @defgroup RCC_APB1_Peripherals - * @{ - */ - -#define RCC_APB1Periph_TIM2 RCC_APB1ENR_TIM2EN -#define RCC_APB1Periph_TIM3 RCC_APB1ENR_TIM3EN -#define RCC_APB1Periph_TIM6 RCC_APB1ENR_TIM6EN -#define RCC_APB1Periph_TIM7 RCC_APB1ENR_TIM7EN -#define RCC_APB1Periph_TIM14 RCC_APB1ENR_TIM14EN -#define RCC_APB1Periph_WWDG RCC_APB1ENR_WWDGEN -#define RCC_APB1Periph_SPI2 RCC_APB1ENR_SPI2EN -#define RCC_APB1Periph_USART2 RCC_APB1ENR_USART2EN -#define RCC_APB1Periph_USART3 RCC_APB1ENR_USART3EN -#define RCC_APB1Periph_USART4 RCC_APB1ENR_USART4EN -#define RCC_APB1Periph_USART5 RCC_APB1ENR_USART5EN -#define RCC_APB1Periph_I2C1 RCC_APB1ENR_I2C1EN -#define RCC_APB1Periph_I2C2 RCC_APB1ENR_I2C2EN -#define RCC_APB1Periph_USB RCC_APB1ENR_USBEN -#define RCC_APB1Periph_CAN RCC_APB1ENR_CANEN -#define RCC_APB1Periph_CRS RCC_APB1ENR_CRSEN -#define RCC_APB1Periph_PWR RCC_APB1ENR_PWREN -#define RCC_APB1Periph_DAC RCC_APB1ENR_DACEN -#define RCC_APB1Periph_CEC RCC_APB1ENR_CECEN - -#define IS_RCC_APB1_PERIPH(PERIPH) ((((PERIPH) & 0x8581B6CC) == 0x00) && ((PERIPH) != 0x00)) -/** - * @} - */ - -/** @defgroup RCC_MCO_Clock_Source - * @{ - */ - -#define RCC_MCOSource_NoClock ((uint8_t)0x00) -#define RCC_MCOSource_HSI14 ((uint8_t)0x01) -#define RCC_MCOSource_LSI ((uint8_t)0x02) -#define RCC_MCOSource_LSE ((uint8_t)0x03) -#define RCC_MCOSource_SYSCLK ((uint8_t)0x04) -#define RCC_MCOSource_HSI ((uint8_t)0x05) -#define RCC_MCOSource_HSE ((uint8_t)0x06) -#define RCC_MCOSource_PLLCLK_Div2 ((uint8_t)0x07) -#define RCC_MCOSource_HSI48 ((uint8_t)0x08) -#define RCC_MCOSource_PLLCLK ((uint8_t)0x87) - -#define IS_RCC_MCO_SOURCE(SOURCE) (((SOURCE) == RCC_MCOSource_NoClock) || ((SOURCE) == RCC_MCOSource_HSI14) || \ - ((SOURCE) == RCC_MCOSource_SYSCLK) || ((SOURCE) == RCC_MCOSource_HSI) || \ - ((SOURCE) == RCC_MCOSource_HSE) || ((SOURCE) == RCC_MCOSource_PLLCLK_Div2)|| \ - ((SOURCE) == RCC_MCOSource_LSI) || ((SOURCE) == RCC_MCOSource_HSI48) || \ - ((SOURCE) == RCC_MCOSource_PLLCLK) || ((SOURCE) == RCC_MCOSource_LSE)) -/** - * @} - */ - -/** @defgroup RCC_MCOPrescaler - * @{ - */ -#if !defined (FT32F051) -#define RCC_MCOPrescaler_1 RCC_CFGR_MCO_PRE_1 -#define RCC_MCOPrescaler_2 RCC_CFGR_MCO_PRE_2 -#define RCC_MCOPrescaler_4 RCC_CFGR_MCO_PRE_4 -#define RCC_MCOPrescaler_8 RCC_CFGR_MCO_PRE_8 -#define RCC_MCOPrescaler_16 RCC_CFGR_MCO_PRE_16 -#define RCC_MCOPrescaler_32 RCC_CFGR_MCO_PRE_32 -#define RCC_MCOPrescaler_64 RCC_CFGR_MCO_PRE_64 -#define RCC_MCOPrescaler_128 RCC_CFGR_MCO_PRE_128 - -#define IS_RCC_MCO_PRESCALER(PRESCALER) (((PRESCALER) == RCC_MCOPrescaler_1) || \ - ((PRESCALER) == RCC_MCOPrescaler_2) || \ - ((PRESCALER) == RCC_MCOPrescaler_4) || \ - ((PRESCALER) == RCC_MCOPrescaler_8) || \ - ((PRESCALER) == RCC_MCOPrescaler_16) || \ - ((PRESCALER) == RCC_MCOPrescaler_32) || \ - ((PRESCALER) == RCC_MCOPrescaler_64) || \ - ((PRESCALER) == RCC_MCOPrescaler_128)) -#endif /* FT32F051 */ -/** - * @} - */ - -/** @defgroup RCC_Flag - * @{ - */ -#define RCC_FLAG_HSIRDY ((uint8_t)0x01) -#define RCC_FLAG_HSERDY ((uint8_t)0x11) -#define RCC_FLAG_PLLRDY ((uint8_t)0x19) -#define RCC_FLAG_LSERDY ((uint8_t)0x21) -#define RCC_FLAG_LSIRDY ((uint8_t)0x41) -#define RCC_FLAG_V18PWRRSTF ((uint8_t)0x57) -#define RCC_FLAG_OBLRST ((uint8_t)0x59) -#define RCC_FLAG_PINRST ((uint8_t)0x5A) -#define RCC_FLAG_PORRST ((uint8_t)0x5B) -#define RCC_FLAG_SFTRST ((uint8_t)0x5C) -#define RCC_FLAG_IWDGRST ((uint8_t)0x5D) -#define RCC_FLAG_WWDGRST ((uint8_t)0x5E) -#define RCC_FLAG_LPWRRST ((uint8_t)0x5F) -#define RCC_FLAG_HSI14RDY ((uint8_t)0x61) -#define RCC_FLAG_HSI48RDY ((uint8_t)0x71) - -#define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY) || ((FLAG) == RCC_FLAG_HSERDY) || \ - ((FLAG) == RCC_FLAG_PLLRDY) || ((FLAG) == RCC_FLAG_LSERDY) || \ - ((FLAG) == RCC_FLAG_LSIRDY) || ((FLAG) == RCC_FLAG_OBLRST) || \ - ((FLAG) == RCC_FLAG_PINRST) || ((FLAG) == RCC_FLAG_PORRST) || \ - ((FLAG) == RCC_FLAG_SFTRST) || ((FLAG) == RCC_FLAG_IWDGRST) || \ - ((FLAG) == RCC_FLAG_WWDGRST) || ((FLAG) == RCC_FLAG_LPWRRST) || \ - ((FLAG) == RCC_FLAG_HSI14RDY)|| ((FLAG) == RCC_FLAG_HSI48RDY)|| \ - ((FLAG) == RCC_FLAG_V18PWRRSTF)) - -#define IS_RCC_HSI_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F) -#define IS_RCC_HSI14_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F) - -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions ------------------------------------------------------- */ - -/* Function used to set the RCC clock configuration to the default reset state */ -void RCC_DeInit(void); - -/* Internal/external clocks, PLL, CSS and MCO configuration functions *********/ -void RCC_HSEConfig(uint8_t RCC_HSE); -ErrorStatus RCC_WaitForHSEStartUp(void); -void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue); -void RCC_HSICmd(FunctionalState NewState); -void RCC_AdjustHSI14CalibrationValue(uint8_t HSI14CalibrationValue); -void RCC_HSI14Cmd(FunctionalState NewState); -void RCC_HSI14ADCRequestCmd(FunctionalState NewState); -void RCC_LSEConfig(uint32_t RCC_LSE); -void RCC_LSEDriveConfig(uint32_t RCC_LSEDrive); -void RCC_LSICmd(FunctionalState NewState); -void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t RCC_PLLMul); -void RCC_PLLCmd(FunctionalState NewState); -void RCC_HSI48Cmd(FunctionalState NewState); -uint32_t RCC_GetHSI48CalibrationValue(void); -void RCC_PREDIV1Config(uint32_t RCC_PREDIV1_Div); -void RCC_ClockSecuritySystemCmd(FunctionalState NewState); -#ifdef FT32F051 -void RCC_MCOConfig(uint8_t RCC_MCOSource); -#else -void RCC_MCOConfig(uint8_t RCC_MCOSource,uint32_t RCC_MCOPrescaler); -#endif /* FT32F051 */ - -/* System, AHB and APB busses clocks configuration functions ******************/ -void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource); -uint8_t RCC_GetSYSCLKSource(void); -void RCC_HCLKConfig(uint32_t RCC_SYSCLK); -void RCC_PCLKConfig(uint32_t RCC_HCLK); -void RCC_ADCCLKConfig(uint32_t RCC_ADCCLK); /* This function is obsolete. - For proper ADC clock selection, refer to - ADC_ClockModeConfig() in the ADC driver */ -void RCC_CECCLKConfig(uint32_t RCC_CECCLK); -void RCC_I2CCLKConfig(uint32_t RCC_I2CCLK); -void RCC_USARTCLKConfig(uint32_t RCC_USARTCLK); -void RCC_USBCLKConfig(uint32_t RCC_USBCLK); -void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks); - -/* Peripheral clocks configuration functions **********************************/ -void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource); -void RCC_RTCCLKCmd(FunctionalState NewState); -void RCC_BackupResetCmd(FunctionalState NewState); - -void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState); -void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState); -void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState); - -void RCC_AHBPeriphResetCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState); -void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState); -void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState); - -/* Interrupts and flags management functions **********************************/ -void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState); -FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG); -void RCC_ClearFlag(void); -ITStatus RCC_GetITStatus(uint8_t RCC_IT); -void RCC_ClearITPendingBit(uint8_t RCC_IT); - -#ifdef __cplusplus -} -#endif - -#endif /* __FT32F0XX_RCC_H */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT FMD *****END OF FILE****/ diff --git a/bsp/ft32/libraries/FT32F0xx/FT32F0xx_Driver/Inc/ft32f0xx_rtc.h b/bsp/ft32/libraries/FT32F0xx/FT32F0xx_Driver/Inc/ft32f0xx_rtc.h deleted file mode 100644 index ff0aa82e29a..00000000000 --- a/bsp/ft32/libraries/FT32F0xx/FT32F0xx_Driver/Inc/ft32f0xx_rtc.h +++ /dev/null @@ -1,747 +0,0 @@ -/** - ****************************************************************************** - * @file ft32f0xx_rtc.h - * @author FMD AE - * @brief This file contains all the functions prototypes for the RTC firmware - * library. - * @version V1.0.0 - * @data 2021-07-01 - ****************************************************************************** - */ - - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __FT32F0XX_RTC_H -#define __FT32F0XX_RTC_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "ft32f0xx.h" - - - -/** @addtogroup RTC - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ - -/** - * @brief RTC Init structures definition - */ -typedef struct -{ - uint32_t RTC_HourFormat; /*!< Specifies the RTC Hour Format. - This parameter can be a value of @ref RTC_Hour_Formats */ - - uint32_t RTC_AsynchPrediv; /*!< Specifies the RTC Asynchronous Predivider value. - This parameter must be set to a value lower than 0x7F */ - - uint32_t RTC_SynchPrediv; /*!< Specifies the RTC Synchronous Predivider value. - This parameter must be set to a value lower than 0x1FFF */ -}RTC_InitTypeDef; - -/** - * @brief RTC Time structure definition - */ -typedef struct -{ - uint8_t RTC_Hours; /*!< Specifies the RTC Time Hour. - This parameter must be set to a value in the 0-12 range - if the RTC_HourFormat_12 is selected or 0-23 range if - the RTC_HourFormat_24 is selected. */ - - uint8_t RTC_Minutes; /*!< Specifies the RTC Time Minutes. - This parameter must be set to a value in the 0-59 range. */ - - uint8_t RTC_Seconds; /*!< Specifies the RTC Time Seconds. - This parameter must be set to a value in the 0-59 range. */ - - uint8_t RTC_H12; /*!< Specifies the RTC AM/PM Time. - This parameter can be a value of @ref RTC_AM_PM_Definitions */ -}RTC_TimeTypeDef; - -/** - * @brief RTC Date structure definition - */ -typedef struct -{ - uint8_t RTC_WeekDay; /*!< Specifies the RTC Date WeekDay. - This parameter can be a value of @ref RTC_WeekDay_Definitions */ - - uint8_t RTC_Month; /*!< Specifies the RTC Date Month. - This parameter can be a value of @ref RTC_Month_Date_Definitions */ - - uint8_t RTC_Date; /*!< Specifies the RTC Date. - This parameter must be set to a value in the 1-31 range. */ - - uint8_t RTC_Year; /*!< Specifies the RTC Date Year. - This parameter must be set to a value in the 0-99 range. */ -}RTC_DateTypeDef; - -/** - * @brief RTC Alarm structure definition - */ -typedef struct -{ - RTC_TimeTypeDef RTC_AlarmTime; /*!< Specifies the RTC Alarm Time members. */ - - uint32_t RTC_AlarmMask; /*!< Specifies the RTC Alarm Masks. - This parameter can be a value of @ref RTC_AlarmMask_Definitions */ - - uint32_t RTC_AlarmDateWeekDaySel; /*!< Specifies the RTC Alarm is on Date or WeekDay. - This parameter can be a value of @ref RTC_AlarmDateWeekDay_Definitions */ - - uint8_t RTC_AlarmDateWeekDay; /*!< Specifies the RTC Alarm Date/WeekDay. - This parameter must be set to a value in the 1-31 range - if the Alarm Date is selected. - This parameter can be a value of @ref RTC_WeekDay_Definitions - if the Alarm WeekDay is selected. */ -}RTC_AlarmTypeDef; - -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup RTC_Exported_Constants - * @{ - */ - - -/** @defgroup RTC_Hour_Formats - * @{ - */ -#define RTC_HourFormat_24 ((uint32_t)0x00000000) -#define RTC_HourFormat_12 ((uint32_t)0x00000040) -#define IS_RTC_HOUR_FORMAT(FORMAT) (((FORMAT) == RTC_HourFormat_12) || \ - ((FORMAT) == RTC_HourFormat_24)) -/** - * @} - */ - -/** @defgroup RTC_Asynchronous_Predivider - * @{ - */ -#define IS_RTC_ASYNCH_PREDIV(PREDIV) ((PREDIV) <= 0x7F) - -/** - * @} - */ - - -/** @defgroup RTC_Synchronous_Predivider - * @{ - */ -#define IS_RTC_SYNCH_PREDIV(PREDIV) ((PREDIV) <= 0x7FFF) - -/** - * @} - */ - -/** @defgroup RTC_Time_Definitions - * @{ - */ -#define IS_RTC_HOUR12(HOUR) (((HOUR) > 0) && ((HOUR) <= 12)) -#define IS_RTC_HOUR24(HOUR) ((HOUR) <= 23) -#define IS_RTC_MINUTES(MINUTES) ((MINUTES) <= 59) -#define IS_RTC_SECONDS(SECONDS) ((SECONDS) <= 59) - -/** - * @} - */ - -/** @defgroup RTC_AM_PM_Definitions - * @{ - */ -#define RTC_H12_AM ((uint8_t)0x00) -#define RTC_H12_PM ((uint8_t)0x40) -#define IS_RTC_H12(PM) (((PM) == RTC_H12_AM) || ((PM) == RTC_H12_PM)) - -/** - * @} - */ - -/** @defgroup RTC_Year_Date_Definitions - * @{ - */ -#define IS_RTC_YEAR(YEAR) ((YEAR) <= 99) - -/** - * @} - */ - -/** @defgroup RTC_Month_Date_Definitions - * @{ - */ -#define RTC_Month_January ((uint8_t)0x01) -#define RTC_Month_February ((uint8_t)0x02) -#define RTC_Month_March ((uint8_t)0x03) -#define RTC_Month_April ((uint8_t)0x04) -#define RTC_Month_May ((uint8_t)0x05) -#define RTC_Month_June ((uint8_t)0x06) -#define RTC_Month_July ((uint8_t)0x07) -#define RTC_Month_August ((uint8_t)0x08) -#define RTC_Month_September ((uint8_t)0x09) -#define RTC_Month_October ((uint8_t)0x10) -#define RTC_Month_November ((uint8_t)0x11) -#define RTC_Month_December ((uint8_t)0x12) -#define IS_RTC_MONTH(MONTH) (((MONTH) >= 1) && ((MONTH) <= 12)) -#define IS_RTC_DATE(DATE) (((DATE) >= 1) && ((DATE) <= 31)) - -/** - * @} - */ - -/** @defgroup RTC_WeekDay_Definitions - * @{ - */ - -#define RTC_Weekday_Monday ((uint8_t)0x01) -#define RTC_Weekday_Tuesday ((uint8_t)0x02) -#define RTC_Weekday_Wednesday ((uint8_t)0x03) -#define RTC_Weekday_Thursday ((uint8_t)0x04) -#define RTC_Weekday_Friday ((uint8_t)0x05) -#define RTC_Weekday_Saturday ((uint8_t)0x6) -#define RTC_Weekday_Sunday ((uint8_t)0x07) -#define IS_RTC_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_Weekday_Monday) || \ - ((WEEKDAY) == RTC_Weekday_Tuesday) || \ - ((WEEKDAY) == RTC_Weekday_Wednesday) || \ - ((WEEKDAY) == RTC_Weekday_Thursday) || \ - ((WEEKDAY) == RTC_Weekday_Friday) || \ - ((WEEKDAY) == RTC_Weekday_Saturday) || \ - ((WEEKDAY) == RTC_Weekday_Sunday)) -/** - * @} - */ - - -/** @defgroup RTC_Alarm_Definitions - * @{ - */ -#define IS_RTC_ALARM_DATE_WEEKDAY_DATE(DATE) (((DATE) > 0) && ((DATE) <= 31)) -#define IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_Weekday_Monday) || \ - ((WEEKDAY) == RTC_Weekday_Tuesday) || \ - ((WEEKDAY) == RTC_Weekday_Wednesday) || \ - ((WEEKDAY) == RTC_Weekday_Thursday) || \ - ((WEEKDAY) == RTC_Weekday_Friday) || \ - ((WEEKDAY) == RTC_Weekday_Saturday) || \ - ((WEEKDAY) == RTC_Weekday_Sunday)) - -/** - * @} - */ - - -/** @defgroup RTC_AlarmDateWeekDay_Definitions - * @{ - */ -#define RTC_AlarmDateWeekDaySel_Date ((uint32_t)0x00000000) -#define RTC_AlarmDateWeekDaySel_WeekDay ((uint32_t)0x40000000) - -#define IS_RTC_ALARM_DATE_WEEKDAY_SEL(SEL) (((SEL) == RTC_AlarmDateWeekDaySel_Date) || \ - ((SEL) == RTC_AlarmDateWeekDaySel_WeekDay)) - -/** - * @} - */ - - -/** @defgroup RTC_AlarmMask_Definitions - * @{ - */ -#define RTC_AlarmMask_None ((uint32_t)0x00000000) -#define RTC_AlarmMask_DateWeekDay ((uint32_t)0x80000000) -#define RTC_AlarmMask_Hours ((uint32_t)0x00800000) -#define RTC_AlarmMask_Minutes ((uint32_t)0x00008000) -#define RTC_AlarmMask_Seconds ((uint32_t)0x00000080) -#define RTC_AlarmMask_All ((uint32_t)0x80808080) -#define IS_RTC_ALARM_MASK(MASK) (((MASK) & 0x7F7F7F7F) == (uint32_t)RESET) - -/** - * @} - */ - -/** @defgroup RTC_Alarms_Definitions - * @{ - */ -#define RTC_Alarm_A ((uint32_t)0x00000100) -#define IS_RTC_ALARM(ALARM) ((ALARM) == RTC_Alarm_A) -#define IS_RTC_CMD_ALARM(ALARM) (((ALARM) & (RTC_Alarm_A)) != (uint32_t)RESET) - -/** - * @} - */ - -/** @defgroup RTC_Alarm_Sub_Seconds_Masks Definitions. - * @{ - */ -#define RTC_AlarmSubSecondMask_All ((uint8_t)0x00) /*!< All Alarm SS fields are masked. - There is no comparison on sub seconds - for Alarm */ -#define RTC_AlarmSubSecondMask_SS14_1 ((uint8_t)0x01) /*!< SS[14:1] are don't care in Alarm - comparison. Only SS[0] is compared. */ -#define RTC_AlarmSubSecondMask_SS14_2 ((uint8_t)0x02) /*!< SS[14:2] are don't care in Alarm - comparison. Only SS[1:0] are compared */ -#define RTC_AlarmSubSecondMask_SS14_3 ((uint8_t)0x03) /*!< SS[14:3] are don't care in Alarm - comparison. Only SS[2:0] are compared */ -#define RTC_AlarmSubSecondMask_SS14_4 ((uint8_t)0x04) /*!< SS[14:4] are don't care in Alarm - comparison. Only SS[3:0] are compared */ -#define RTC_AlarmSubSecondMask_SS14_5 ((uint8_t)0x05) /*!< SS[14:5] are don't care in Alarm - comparison. Only SS[4:0] are compared */ -#define RTC_AlarmSubSecondMask_SS14_6 ((uint8_t)0x06) /*!< SS[14:6] are don't care in Alarm - comparison. Only SS[5:0] are compared */ -#define RTC_AlarmSubSecondMask_SS14_7 ((uint8_t)0x07) /*!< SS[14:7] are don't care in Alarm - comparison. Only SS[6:0] are compared */ -#define RTC_AlarmSubSecondMask_SS14_8 ((uint8_t)0x08) /*!< SS[14:8] are don't care in Alarm - comparison. Only SS[7:0] are compared */ -#define RTC_AlarmSubSecondMask_SS14_9 ((uint8_t)0x09) /*!< SS[14:9] are don't care in Alarm - comparison. Only SS[8:0] are compared */ -#define RTC_AlarmSubSecondMask_SS14_10 ((uint8_t)0x0A) /*!< SS[14:10] are don't care in Alarm - comparison. Only SS[9:0] are compared */ -#define RTC_AlarmSubSecondMask_SS14_11 ((uint8_t)0x0B) /*!< SS[14:11] are don't care in Alarm - comparison. Only SS[10:0] are compared */ -#define RTC_AlarmSubSecondMask_SS14_12 ((uint8_t)0x0C) /*!< SS[14:12] are don't care in Alarm - comparison.Only SS[11:0] are compared */ -#define RTC_AlarmSubSecondMask_SS14_13 ((uint8_t)0x0D) /*!< SS[14:13] are don't care in Alarm - comparison. Only SS[12:0] are compared */ -#define RTC_AlarmSubSecondMask_SS14 ((uint8_t)0x0E) /*!< SS[14] is don't care in Alarm - comparison.Only SS[13:0] are compared */ -#define RTC_AlarmSubSecondMask_None ((uint8_t)0x0F) /*!< SS[14:0] are compared and must match - to activate alarm. */ -#define IS_RTC_ALARM_SUB_SECOND_MASK(MASK) (((MASK) == RTC_AlarmSubSecondMask_All) || \ - ((MASK) == RTC_AlarmSubSecondMask_SS14_1) || \ - ((MASK) == RTC_AlarmSubSecondMask_SS14_2) || \ - ((MASK) == RTC_AlarmSubSecondMask_SS14_3) || \ - ((MASK) == RTC_AlarmSubSecondMask_SS14_4) || \ - ((MASK) == RTC_AlarmSubSecondMask_SS14_5) || \ - ((MASK) == RTC_AlarmSubSecondMask_SS14_6) || \ - ((MASK) == RTC_AlarmSubSecondMask_SS14_7) || \ - ((MASK) == RTC_AlarmSubSecondMask_SS14_8) || \ - ((MASK) == RTC_AlarmSubSecondMask_SS14_9) || \ - ((MASK) == RTC_AlarmSubSecondMask_SS14_10) || \ - ((MASK) == RTC_AlarmSubSecondMask_SS14_11) || \ - ((MASK) == RTC_AlarmSubSecondMask_SS14_12) || \ - ((MASK) == RTC_AlarmSubSecondMask_SS14_13) || \ - ((MASK) == RTC_AlarmSubSecondMask_SS14) || \ - ((MASK) == RTC_AlarmSubSecondMask_None)) -/** - * @} - */ - -/** @defgroup RTC_Alarm_Sub_Seconds_Value - * @{ - */ - -#define IS_RTC_ALARM_SUB_SECOND_VALUE(VALUE) ((VALUE) <= 0x00007FFF) - -/** - * @} - */ - -/** - * @} - */ - -/** @defgroup RTC_Time_Stamp_Edges_definitions - * @{ - */ -#define RTC_TimeStampEdge_Rising ((uint32_t)0x00000000) -#define RTC_TimeStampEdge_Falling ((uint32_t)0x00000008) -#define IS_RTC_TIMESTAMP_EDGE(EDGE) (((EDGE) == RTC_TimeStampEdge_Rising) || \ - ((EDGE) == RTC_TimeStampEdge_Falling)) -/** - * @} - */ - -/** @defgroup RTC_Output_selection_Definitions - * @{ - */ -#define RTC_Output_Disable ((uint32_t)0x00000000) -#define RTC_Output_AlarmA ((uint32_t)0x00200000) -#define RTC_Output_WakeUp ((uint32_t)0x00600000) - -#define IS_RTC_OUTPUT(OUTPUT) (((OUTPUT) == RTC_Output_Disable) || \ - ((OUTPUT) == RTC_Output_AlarmA) || \ - ((OUTPUT) == RTC_Output_WakeUp)) - -/** - * @} - */ - -/** @defgroup RTC_Output_Polarity_Definitions - * @{ - */ -#define RTC_OutputPolarity_High ((uint32_t)0x00000000) -#define RTC_OutputPolarity_Low ((uint32_t)0x00100000) -#define IS_RTC_OUTPUT_POL(POL) (((POL) == RTC_OutputPolarity_High) || \ - ((POL) == RTC_OutputPolarity_Low)) -/** - * @} - */ - - -/** @defgroup RTC_Calib_Output_selection_Definitions - * @{ - */ -#define RTC_CalibOutput_512Hz ((uint32_t)0x00000000) -#define RTC_CalibOutput_1Hz ((uint32_t)0x00080000) -#define IS_RTC_CALIB_OUTPUT(OUTPUT) (((OUTPUT) == RTC_CalibOutput_512Hz) || \ - ((OUTPUT) == RTC_CalibOutput_1Hz)) -/** - * @} - */ - -/** @defgroup RTC_Smooth_calib_period_Definitions - * @{ - */ -#define RTC_SmoothCalibPeriod_32sec ((uint32_t)0x00000000) /*!< if RTCCLK = 32768 Hz, Smooth calibation - period is 32s, else 2exp20 RTCCLK seconds */ -#define RTC_SmoothCalibPeriod_16sec ((uint32_t)0x00002000) /*!< if RTCCLK = 32768 Hz, Smooth calibation - period is 16s, else 2exp19 RTCCLK seconds */ -#define RTC_SmoothCalibPeriod_8sec ((uint32_t)0x00004000) /*!< if RTCCLK = 32768 Hz, Smooth calibation - period is 8s, else 2exp18 RTCCLK seconds */ -#define IS_RTC_SMOOTH_CALIB_PERIOD(PERIOD) (((PERIOD) == RTC_SmoothCalibPeriod_32sec) || \ - ((PERIOD) == RTC_SmoothCalibPeriod_16sec) || \ - ((PERIOD) == RTC_SmoothCalibPeriod_8sec)) - -/** - * @} - */ - -/** @defgroup RTC_Smooth_calib_Plus_pulses_Definitions - * @{ - */ -#define RTC_SmoothCalibPlusPulses_Set ((uint32_t)0x00008000) /*!< The number of RTCCLK pulses added - during a X -second window = Y - CALM[8:0]. - with Y = 512, 256, 128 when X = 32, 16, 8 */ -#define RTC_SmoothCalibPlusPulses_Reset ((uint32_t)0x00000000) /*!< The number of RTCCLK pulses subbstited - during a 32-second window = CALM[8:0]. */ -#define IS_RTC_SMOOTH_CALIB_PLUS(PLUS) (((PLUS) == RTC_SmoothCalibPlusPulses_Set) || \ - ((PLUS) == RTC_SmoothCalibPlusPulses_Reset)) - -/** - * @} - */ - -/** @defgroup RTC_Smooth_calib_Minus_pulses_Definitions - * @{ - */ -#define IS_RTC_SMOOTH_CALIB_MINUS(VALUE) ((VALUE) <= 0x000001FF) - -/** - * @} - */ - -/** @defgroup RTC_DayLightSaving_Definitions - * @{ - */ -#define RTC_DayLightSaving_SUB1H ((uint32_t)0x00020000) -#define RTC_DayLightSaving_ADD1H ((uint32_t)0x00010000) -#define IS_RTC_DAYLIGHT_SAVING(SAVING) (((SAVING) == RTC_DayLightSaving_SUB1H) || \ - ((SAVING) == RTC_DayLightSaving_ADD1H)) - -#define RTC_StoreOperation_Reset ((uint32_t)0x00000000) -#define RTC_StoreOperation_Set ((uint32_t)0x00040000) -#define IS_RTC_STORE_OPERATION(OPERATION) (((OPERATION) == RTC_StoreOperation_Reset) || \ - ((OPERATION) == RTC_StoreOperation_Set)) -/** - * @} - */ - -/** @defgroup RTC_Tamper_Trigger_Definitions - * @{ - */ -#define RTC_TamperTrigger_RisingEdge ((uint32_t)0x00000000) -#define RTC_TamperTrigger_FallingEdge ((uint32_t)0x00000001) -#define RTC_TamperTrigger_LowLevel ((uint32_t)0x00000000) -#define RTC_TamperTrigger_HighLevel ((uint32_t)0x00000001) -#define IS_RTC_TAMPER_TRIGGER(TRIGGER) (((TRIGGER) == RTC_TamperTrigger_RisingEdge) || \ - ((TRIGGER) == RTC_TamperTrigger_FallingEdge) || \ - ((TRIGGER) == RTC_TamperTrigger_LowLevel) || \ - ((TRIGGER) == RTC_TamperTrigger_HighLevel)) - -/** - * @} - */ - -/** @defgroup RTC_Tamper_Filter_Definitions - * @{ - */ -#define RTC_TamperFilter_Disable ((uint32_t)0x00000000) /*!< Tamper filter is disabled */ - -#define RTC_TamperFilter_2Sample ((uint32_t)0x00000800) /*!< Tamper is activated after 2 - consecutive samples at the active level */ -#define RTC_TamperFilter_4Sample ((uint32_t)0x00001000) /*!< Tamper is activated after 4 - consecutive samples at the active level */ -#define RTC_TamperFilter_8Sample ((uint32_t)0x00001800) /*!< Tamper is activated after 8 - consecutive samples at the active leve. */ -#define IS_RTC_TAMPER_FILTER(FILTER) (((FILTER) == RTC_TamperFilter_Disable) || \ - ((FILTER) == RTC_TamperFilter_2Sample) || \ - ((FILTER) == RTC_TamperFilter_4Sample) || \ - ((FILTER) == RTC_TamperFilter_8Sample)) -/** - * @} - */ - -/** @defgroup RTC_Tamper_Sampling_Frequencies_Definitions - * @{ - */ -#define RTC_TamperSamplingFreq_RTCCLK_Div32768 ((uint32_t)0x00000000) /*!< Each of the tamper inputs are sampled - with a frequency = RTCCLK / 32768 */ -#define RTC_TamperSamplingFreq_RTCCLK_Div16384 ((uint32_t)0x00000100) /*!< Each of the tamper inputs are sampled - with a frequency = RTCCLK / 16384 */ -#define RTC_TamperSamplingFreq_RTCCLK_Div8192 ((uint32_t)0x00000200) /*!< Each of the tamper inputs are sampled - with a frequency = RTCCLK / 8192 */ -#define RTC_TamperSamplingFreq_RTCCLK_Div4096 ((uint32_t)0x00000300) /*!< Each of the tamper inputs are sampled - with a frequency = RTCCLK / 4096 */ -#define RTC_TamperSamplingFreq_RTCCLK_Div2048 ((uint32_t)0x00000400) /*!< Each of the tamper inputs are sampled - with a frequency = RTCCLK / 2048 */ -#define RTC_TamperSamplingFreq_RTCCLK_Div1024 ((uint32_t)0x00000500) /*!< Each of the tamper inputs are sampled - with a frequency = RTCCLK / 1024 */ -#define RTC_TamperSamplingFreq_RTCCLK_Div512 ((uint32_t)0x00000600) /*!< Each of the tamper inputs are sampled - with a frequency = RTCCLK / 512 */ -#define RTC_TamperSamplingFreq_RTCCLK_Div256 ((uint32_t)0x00000700) /*!< Each of the tamper inputs are sampled - with a frequency = RTCCLK / 256 */ -#define IS_RTC_TAMPER_SAMPLING_FREQ(FREQ) (((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div32768) || \ - ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div16384) || \ - ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div8192) || \ - ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div4096) || \ - ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div2048) || \ - ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div1024) || \ - ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div512) || \ - ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div256)) - -/** - * @} - */ - - /** @defgroup RTC_Tamper_Pin_Precharge_Duration_Definitions - * @{ - */ -#define RTC_TamperPrechargeDuration_1RTCCLK ((uint32_t)0x00000000) /*!< Tamper pins are pre-charged before - sampling during 1 RTCCLK cycle */ -#define RTC_TamperPrechargeDuration_2RTCCLK ((uint32_t)0x00002000) /*!< Tamper pins are pre-charged before - sampling during 2 RTCCLK cycles */ -#define RTC_TamperPrechargeDuration_4RTCCLK ((uint32_t)0x00004000) /*!< Tamper pins are pre-charged before - sampling during 4 RTCCLK cycles */ -#define RTC_TamperPrechargeDuration_8RTCCLK ((uint32_t)0x00006000) /*!< Tamper pins are pre-charged before - sampling during 8 RTCCLK cycles */ - -#define IS_RTC_TAMPER_PRECHARGE_DURATION(DURATION) (((DURATION) == RTC_TamperPrechargeDuration_1RTCCLK) || \ - ((DURATION) == RTC_TamperPrechargeDuration_2RTCCLK) || \ - ((DURATION) == RTC_TamperPrechargeDuration_4RTCCLK) || \ - ((DURATION) == RTC_TamperPrechargeDuration_8RTCCLK)) -/** - * @} - */ - -/** @defgroup RTC_Tamper_Pins_Definitions - * @{ - */ -#define RTC_Tamper_1 RTC_TAFCR_TAMP1E /*!< Tamper detection enable for - input tamper 1 */ -#define RTC_Tamper_2 RTC_TAFCR_TAMP2E /*!< Tamper detection enable for - input tamper 2 */ -#define RTC_Tamper_3 RTC_TAFCR_TAMP3E /*!< Tamper detection enable for - input tamper 3*/ -#define IS_RTC_TAMPER(TAMPER) ((((TAMPER) & (uint32_t)0xFFFFFFD6) == 0x00) && ((TAMPER) != (uint32_t)RESET)) - -/** - * @} - */ - -/** @defgroup RTC_Output_Type_ALARM_OUT - * @{ - */ -#define RTC_OutputType_OpenDrain ((uint32_t)0x00000000) -#define RTC_OutputType_PushPull ((uint32_t)0x00040000) -#define IS_RTC_OUTPUT_TYPE(TYPE) (((TYPE) == RTC_OutputType_OpenDrain) || \ - ((TYPE) == RTC_OutputType_PushPull)) - -/** - * @} - */ - -/** @defgroup RTC_Add_1_Second_Parameter_Definitions - * @{ - */ -#define RTC_ShiftAdd1S_Reset ((uint32_t)0x00000000) -#define RTC_ShiftAdd1S_Set ((uint32_t)0x80000000) -#define IS_RTC_SHIFT_ADD1S(SEL) (((SEL) == RTC_ShiftAdd1S_Reset) || \ - ((SEL) == RTC_ShiftAdd1S_Set)) -/** - * @} - */ - -/** @defgroup RTC_Substract_Fraction_Of_Second_Value - * @{ - */ -#define IS_RTC_SHIFT_SUBFS(FS) ((FS) <= 0x00007FFF) - -/** - * @} - */ - -/** - * @} - */ - -/** @defgroup RTC_Input_parameter_format_definitions - * @{ - */ -#define RTC_Format_BIN ((uint32_t)0x000000000) -#define RTC_Format_BCD ((uint32_t)0x000000001) -#define IS_RTC_FORMAT(FORMAT) (((FORMAT) == RTC_Format_BIN) || ((FORMAT) == RTC_Format_BCD)) - -/** - * @} - */ - -/** @defgroup RTC_Flags_Definitions - * @{ - */ -#define RTC_FLAG_RECALPF RTC_ISR_RECALPF -#define RTC_FLAG_TAMP3F RTC_ISR_TAMP3F -#define RTC_FLAG_TAMP2F RTC_ISR_TAMP2F -#define RTC_FLAG_TAMP1F RTC_ISR_TAMP1F -#define RTC_FLAG_TSOVF RTC_ISR_TSOVF -#define RTC_FLAG_TSF RTC_ISR_TSF -#define RTC_FLAG_WUTF RTC_ISR_WUTF -#define RTC_FLAG_ALRAF RTC_ISR_ALRAF -#define RTC_FLAG_INITF RTC_ISR_INITF -#define RTC_FLAG_RSF RTC_ISR_RSF -#define RTC_FLAG_INITS RTC_ISR_INITS -#define RTC_FLAG_SHPF RTC_ISR_SHPF -#define RTC_FLAG_WUTWF RTC_ISR_WUTWF -#define RTC_FLAG_ALRAWF RTC_ISR_ALRAWF - -#define IS_RTC_GET_FLAG(FLAG) (((FLAG) == RTC_FLAG_TSOVF) || ((FLAG) == RTC_FLAG_TSF) || \ - ((FLAG) == RTC_FLAG_WUTF) || ((FLAG) == RTC_FLAG_ALRAWF) || \ - ((FLAG) == RTC_FLAG_ALRAF) || ((FLAG) == RTC_FLAG_INITF) || \ - ((FLAG) == RTC_FLAG_RSF) || ((FLAG) == RTC_FLAG_WUTWF) || \ - ((FLAG) == RTC_FLAG_TAMP1F) || ((FLAG) == RTC_FLAG_TAMP2F) || \ - ((FLAG) == RTC_FLAG_TAMP3F) || ((FLAG) == RTC_FLAG_RECALPF) || \ - ((FLAG) == RTC_FLAG_SHPF)) -#define IS_RTC_CLEAR_FLAG(FLAG) (((FLAG) != (uint32_t)RESET) && (((FLAG) & 0xFFFF02DF) == (uint32_t)RESET)) - -/** - * @} - */ - -/** @defgroup RTC_Interrupts_Definitions - * @{ - */ -#define RTC_IT_TS ((uint32_t)0x00008000) -#define RTC_IT_WUT ((uint32_t)0x00004000) -#define RTC_IT_ALRA ((uint32_t)0x00001000) -#define RTC_IT_TAMP ((uint32_t)0x00000004) /* Used only to Enable the Tamper Interrupt */ -#define RTC_IT_TAMP1 ((uint32_t)0x00020000) -#define RTC_IT_TAMP2 ((uint32_t)0x00040000) -#define RTC_IT_TAMP3 ((uint32_t)0x00080000) - -#define IS_RTC_CONFIG_IT(IT) (((IT) != (uint32_t)RESET) && (((IT) & 0xFFFF2FFB) == (uint32_t)RESET)) -#define IS_RTC_GET_IT(IT) (((IT) == RTC_IT_TS) || ((IT) == RTC_IT_ALRA) || \ - ((IT) == RTC_IT_TAMP1) || ((IT) == RTC_IT_WUT) || \ - ((IT) == RTC_IT_TAMP2) || ((IT) == RTC_IT_TAMP3)) - -#define IS_RTC_CLEAR_IT(IT) (((IT) != (uint32_t)RESET) && (((IT) & 0xFFF12FFF) == (uint32_t)RESET)) - -/** - * @} - */ - -/** - * @} - */ - - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions ------------------------------------------------------- */ -/* Function used to set the RTC configuration to the default reset state *****/ -ErrorStatus RTC_DeInit(void); - - -/* Initialization and Configuration functions *********************************/ -ErrorStatus RTC_Init(RTC_InitTypeDef* RTC_InitStruct); -void RTC_StructInit(RTC_InitTypeDef* RTC_InitStruct); -void RTC_WriteProtectionCmd(FunctionalState NewState); -ErrorStatus RTC_EnterInitMode(void); -void RTC_ExitInitMode(void); -ErrorStatus RTC_WaitForSynchro(void); -ErrorStatus RTC_RefClockCmd(FunctionalState NewState); -void RTC_BypassShadowCmd(FunctionalState NewState); - -/* Time and Date configuration functions **************************************/ -ErrorStatus RTC_SetTime(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_TimeStruct); -void RTC_TimeStructInit(RTC_TimeTypeDef* RTC_TimeStruct); -void RTC_GetTime(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_TimeStruct); -uint32_t RTC_GetSubSecond(void); -ErrorStatus RTC_SetDate(uint32_t RTC_Format, RTC_DateTypeDef* RTC_DateStruct); -void RTC_DateStructInit(RTC_DateTypeDef* RTC_DateStruct); -void RTC_GetDate(uint32_t RTC_Format, RTC_DateTypeDef* RTC_DateStruct); - -/* Alarms (Alarm A) configuration functions **********************************/ -void RTC_SetAlarm(uint32_t RTC_Format, uint32_t RTC_Alarm, RTC_AlarmTypeDef* RTC_AlarmStruct); -void RTC_AlarmStructInit(RTC_AlarmTypeDef* RTC_AlarmStruct); -void RTC_GetAlarm(uint32_t RTC_Format, uint32_t RTC_Alarm, RTC_AlarmTypeDef* RTC_AlarmStruct); -ErrorStatus RTC_AlarmCmd(uint32_t RTC_Alarm, FunctionalState NewState); -void RTC_AlarmSubSecondConfig(uint32_t RTC_Alarm, uint32_t RTC_AlarmSubSecondValue, uint8_t RTC_AlarmSubSecondMask); -uint32_t RTC_GetAlarmSubSecond(uint32_t RTC_Alarm); - -/* Daylight Saving configuration functions ************************************/ -void RTC_DayLightSavingConfig(uint32_t RTC_DayLightSaving, uint32_t RTC_StoreOperation); -uint32_t RTC_GetStoreOperation(void); - -/* Output pin Configuration function ******************************************/ -void RTC_OutputConfig(uint32_t RTC_Output, uint32_t RTC_OutputPolarity); - -/* Digital Calibration configuration functions ********************************/ -void RTC_CalibOutputCmd(FunctionalState NewState); -void RTC_CalibOutputConfig(uint32_t RTC_CalibOutput); -ErrorStatus RTC_SmoothCalibConfig(uint32_t RTC_SmoothCalibPeriod, - uint32_t RTC_SmoothCalibPlusPulses, - uint32_t RTC_SmouthCalibMinusPulsesValue); - -/* TimeStamp configuration functions ******************************************/ -void RTC_TimeStampCmd(uint32_t RTC_TimeStampEdge, FunctionalState NewState); -void RTC_GetTimeStamp(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_StampTimeStruct, RTC_DateTypeDef* RTC_StampDateStruct); -uint32_t RTC_GetTimeStampSubSecond(void); - -/* Tampers configuration functions ********************************************/ -void RTC_TamperTriggerConfig(uint32_t RTC_Tamper, uint32_t RTC_TamperTrigger); -void RTC_TamperCmd(uint32_t RTC_Tamper, FunctionalState NewState); -void RTC_TamperFilterConfig(uint32_t RTC_TamperFilter); -void RTC_TamperSamplingFreqConfig(uint32_t RTC_TamperSamplingFreq); -void RTC_TamperPinsPrechargeDuration(uint32_t RTC_TamperPrechargeDuration); -void RTC_TimeStampOnTamperDetectionCmd(FunctionalState NewState); -void RTC_TamperPullUpCmd(FunctionalState NewState); - -/* Output Type Config configuration functions *********************************/ -void RTC_OutputTypeConfig(uint32_t RTC_OutputType); - -/* RTC_Shift_control_synchonisation_functions *********************************/ -ErrorStatus RTC_SynchroShiftConfig(uint32_t RTC_ShiftAdd1S, uint32_t RTC_ShiftSubFS); - -/* Interrupts and flags management functions **********************************/ -void RTC_ITConfig(uint32_t RTC_IT, FunctionalState NewState); -FlagStatus RTC_GetFlagStatus(uint32_t RTC_FLAG); -void RTC_ClearFlag(uint32_t RTC_FLAG); -ITStatus RTC_GetITStatus(uint32_t RTC_IT); -void RTC_ClearITPendingBit(uint32_t RTC_IT); - -#ifdef __cplusplus -} -#endif - -#endif /*__FT32F0XX_RTC_H */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT FMD *****END OF FILE****/ diff --git a/bsp/ft32/libraries/FT32F0xx/FT32F0xx_Driver/Inc/ft32f0xx_spi.h b/bsp/ft32/libraries/FT32F0xx/FT32F0xx_Driver/Inc/ft32f0xx_spi.h deleted file mode 100644 index 9ae04c86981..00000000000 --- a/bsp/ft32/libraries/FT32F0xx/FT32F0xx_Driver/Inc/ft32f0xx_spi.h +++ /dev/null @@ -1,540 +0,0 @@ -/** - ****************************************************************************** - * @file ft32f0xx_spi.h - * @author FMD AE - * @brief This file contains all the functions prototypes for the SPI - * firmware library. - * @version V1.0.0 - * @data 2021-07-01 - ****************************************************************************** - */ - - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __FT32F0XX_SPI_H -#define __FT32F0XX_SPI_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "ft32f0xx.h" - - -/** @addtogroup SPI - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ - -/** - * @brief SPI Init structure definition - */ - -typedef struct -{ - uint16_t SPI_Direction; /*!< Specifies the SPI unidirectional or bidirectional data mode. - This parameter can be a value of @ref SPI_data_direction */ - - uint16_t SPI_Mode; /*!< Specifies the SPI mode (Master/Slave). - This parameter can be a value of @ref SPI_mode */ - - uint16_t SPI_DataSize; /*!< Specifies the SPI data size. - This parameter can be a value of @ref SPI_data_size */ - - uint16_t SPI_CPOL; /*!< Specifies the serial clock steady state. - This parameter can be a value of @ref SPI_Clock_Polarity */ - - uint16_t SPI_CPHA; /*!< Specifies the clock active edge for the bit capture. - This parameter can be a value of @ref SPI_Clock_Phase */ - - uint16_t SPI_NSS; /*!< Specifies whether the NSS signal is managed by - hardware (NSS pin) or by software using the SSI bit. - This parameter can be a value of @ref SPI_Slave_Select_management */ - - uint16_t SPI_BaudRatePrescaler; /*!< Specifies the Baud Rate prescaler value which will be - used to configure the transmit and receive SCK clock. - This parameter can be a value of @ref SPI_BaudRate_Prescaler - @note The communication clock is derived from the master - clock. The slave clock does not need to be set. */ - - uint16_t SPI_FirstBit; /*!< Specifies whether data transfers start from MSB or LSB bit. - This parameter can be a value of @ref SPI_MSB_LSB_transmission */ - - uint16_t SPI_CRCPolynomial; /*!< Specifies the polynomial used for the CRC calculation. */ -}SPI_InitTypeDef; - - -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup SPI_Exported_Constants - * @{ - */ - -#define IS_SPI_ALL_PERIPH(PERIPH) (((PERIPH) == SPI1) || \ - ((PERIPH) == SPI2)) - -#define IS_SPI_1_PERIPH(PERIPH) (((PERIPH) == SPI1)) - -/** @defgroup SPI_data_direction - * @{ - */ - -#define SPI_Direction_2Lines_FullDuplex ((uint16_t)0x0000) -#define SPI_Direction_2Lines_RxOnly ((uint16_t)0x0400) -#define SPI_Direction_1Line_Rx ((uint16_t)0x8000) -#define SPI_Direction_1Line_Tx ((uint16_t)0xC000) -#define IS_SPI_DIRECTION_MODE(MODE) (((MODE) == SPI_Direction_2Lines_FullDuplex) || \ - ((MODE) == SPI_Direction_2Lines_RxOnly) || \ - ((MODE) == SPI_Direction_1Line_Rx) || \ - ((MODE) == SPI_Direction_1Line_Tx)) -/** - * @} - */ - -/** @defgroup SPI_mode - * @{ - */ - -#define SPI_Mode_Master ((uint16_t)0x0104) -#define SPI_Mode_Slave ((uint16_t)0x0000) -#define IS_SPI_MODE(MODE) (((MODE) == SPI_Mode_Master) || \ - ((MODE) == SPI_Mode_Slave)) -/** - * @} - */ - -/** @defgroup SPI_data_size - * @{ - */ - -#define SPI_DataSize_4b ((uint16_t)0x0300) -#define SPI_DataSize_5b ((uint16_t)0x0400) -#define SPI_DataSize_6b ((uint16_t)0x0500) -#define SPI_DataSize_7b ((uint16_t)0x0600) -#define SPI_DataSize_8b ((uint16_t)0x0700) -#define SPI_DataSize_9b ((uint16_t)0x0800) -#define SPI_DataSize_10b ((uint16_t)0x0900) -#define SPI_DataSize_11b ((uint16_t)0x0A00) -#define SPI_DataSize_12b ((uint16_t)0x0B00) -#define SPI_DataSize_13b ((uint16_t)0x0C00) -#define SPI_DataSize_14b ((uint16_t)0x0D00) -#define SPI_DataSize_15b ((uint16_t)0x0E00) -#define SPI_DataSize_16b ((uint16_t)0x0F00) -#define IS_SPI_DATA_SIZE(SIZE) (((SIZE) == SPI_DataSize_4b) || \ - ((SIZE) == SPI_DataSize_5b) || \ - ((SIZE) == SPI_DataSize_6b) || \ - ((SIZE) == SPI_DataSize_7b) || \ - ((SIZE) == SPI_DataSize_8b) || \ - ((SIZE) == SPI_DataSize_9b) || \ - ((SIZE) == SPI_DataSize_10b) || \ - ((SIZE) == SPI_DataSize_11b) || \ - ((SIZE) == SPI_DataSize_12b) || \ - ((SIZE) == SPI_DataSize_13b) || \ - ((SIZE) == SPI_DataSize_14b) || \ - ((SIZE) == SPI_DataSize_15b) || \ - ((SIZE) == SPI_DataSize_16b)) -/** - * @} - */ - -/** @defgroup SPI_CRC_length - * @{ - */ - -#define SPI_CRCLength_8b ((uint16_t)0x0000) -#define SPI_CRCLength_16b SPI_CR1_CRCL -#define IS_SPI_CRC_LENGTH(LENGTH) (((LENGTH) == SPI_CRCLength_8b) || \ - ((LENGTH) == SPI_CRCLength_16b)) -/** - * @} - */ - -/** @defgroup SPI_Clock_Polarity - * @{ - */ - -#define SPI_CPOL_Low ((uint16_t)0x0000) -#define SPI_CPOL_High SPI_CR1_CPOL -#define IS_SPI_CPOL(CPOL) (((CPOL) == SPI_CPOL_Low) || \ - ((CPOL) == SPI_CPOL_High)) -/** - * @} - */ - -/** @defgroup SPI_Clock_Phase - * @{ - */ - -#define SPI_CPHA_1Edge ((uint16_t)0x0000) -#define SPI_CPHA_2Edge SPI_CR1_CPHA -#define IS_SPI_CPHA(CPHA) (((CPHA) == SPI_CPHA_1Edge) || \ - ((CPHA) == SPI_CPHA_2Edge)) -/** - * @} - */ - -/** @defgroup SPI_Slave_Select_management - * @{ - */ - -#define SPI_NSS_Soft SPI_CR1_SSM -#define SPI_NSS_Hard ((uint16_t)0x0000) -#define IS_SPI_NSS(NSS) (((NSS) == SPI_NSS_Soft) || \ - ((NSS) == SPI_NSS_Hard)) -/** - * @} - */ - -/** @defgroup SPI_BaudRate_Prescaler - * @{ - */ - -#define SPI_BaudRatePrescaler_2 ((uint16_t)0x0000) -#define SPI_BaudRatePrescaler_4 ((uint16_t)0x0008) -#define SPI_BaudRatePrescaler_8 ((uint16_t)0x0010) -#define SPI_BaudRatePrescaler_16 ((uint16_t)0x0018) -#define SPI_BaudRatePrescaler_32 ((uint16_t)0x0020) -#define SPI_BaudRatePrescaler_64 ((uint16_t)0x0028) -#define SPI_BaudRatePrescaler_128 ((uint16_t)0x0030) -#define SPI_BaudRatePrescaler_256 ((uint16_t)0x0038) -#define IS_SPI_BAUDRATE_PRESCALER(PRESCALER) (((PRESCALER) == SPI_BaudRatePrescaler_2) || \ - ((PRESCALER) == SPI_BaudRatePrescaler_4) || \ - ((PRESCALER) == SPI_BaudRatePrescaler_8) || \ - ((PRESCALER) == SPI_BaudRatePrescaler_16) || \ - ((PRESCALER) == SPI_BaudRatePrescaler_32) || \ - ((PRESCALER) == SPI_BaudRatePrescaler_64) || \ - ((PRESCALER) == SPI_BaudRatePrescaler_128) || \ - ((PRESCALER) == SPI_BaudRatePrescaler_256)) -/** - * @} - */ - -/** @defgroup SPI_MSB_LSB_transmission - * @{ - */ - -#define SPI_FirstBit_MSB ((uint16_t)0x0000) -#define SPI_FirstBit_LSB SPI_CR1_LSBFIRST -#define IS_SPI_FIRST_BIT(BIT) (((BIT) == SPI_FirstBit_MSB) || \ - ((BIT) == SPI_FirstBit_LSB)) -/** - * @} - */ - -/** @defgroup SPI_I2S_Mode - * @{ - */ - -#define I2S_Mode_SlaveTx ((uint16_t)0x0000) -#define I2S_Mode_SlaveRx ((uint16_t)0x0100) -#define I2S_Mode_MasterTx ((uint16_t)0x0200) -#define I2S_Mode_MasterRx ((uint16_t)0x0300) -#define IS_I2S_MODE(MODE) (((MODE) == I2S_Mode_SlaveTx) || \ - ((MODE) == I2S_Mode_SlaveRx) || \ - ((MODE) == I2S_Mode_MasterTx)|| \ - ((MODE) == I2S_Mode_MasterRx)) -/** - * @} - */ - -/** @defgroup SPI_I2S_Standard - * @{ - */ - -#define I2S_Standard_Phillips ((uint16_t)0x0000) -#define I2S_Standard_MSB ((uint16_t)0x0010) -#define I2S_Standard_LSB ((uint16_t)0x0020) -#define I2S_Standard_PCMShort ((uint16_t)0x0030) -#define I2S_Standard_PCMLong ((uint16_t)0x00B0) -#define IS_I2S_STANDARD(STANDARD) (((STANDARD) == I2S_Standard_Phillips) || \ - ((STANDARD) == I2S_Standard_MSB) || \ - ((STANDARD) == I2S_Standard_LSB) || \ - ((STANDARD) == I2S_Standard_PCMShort) || \ - ((STANDARD) == I2S_Standard_PCMLong)) -/** - * @} - */ - -/** @defgroup SPI_I2S_Data_Format - * @{ - */ - -#define I2S_DataFormat_16b ((uint16_t)0x0000) -#define I2S_DataFormat_16bextended ((uint16_t)0x0001) -#define I2S_DataFormat_24b ((uint16_t)0x0003) -#define I2S_DataFormat_32b ((uint16_t)0x0005) -#define IS_I2S_DATA_FORMAT(FORMAT) (((FORMAT) == I2S_DataFormat_16b) || \ - ((FORMAT) == I2S_DataFormat_16bextended) || \ - ((FORMAT) == I2S_DataFormat_24b) || \ - ((FORMAT) == I2S_DataFormat_32b)) -/** - * @} - */ - -/** @defgroup SPI_I2S_MCLK_Output - * @{ - */ - -#define I2S_MCLKOutput_Enable SPI_I2SPR_MCKOE -#define I2S_MCLKOutput_Disable ((uint16_t)0x0000) -#define IS_I2S_MCLK_OUTPUT(OUTPUT) (((OUTPUT) == I2S_MCLKOutput_Enable) || \ - ((OUTPUT) == I2S_MCLKOutput_Disable)) -/** - * @} - */ - -/** @defgroup SPI_I2S_Audio_Frequency - * @{ - */ - -#define I2S_AudioFreq_192k ((uint32_t)192000) -#define I2S_AudioFreq_96k ((uint32_t)96000) -#define I2S_AudioFreq_48k ((uint32_t)48000) -#define I2S_AudioFreq_44k ((uint32_t)44100) -#define I2S_AudioFreq_32k ((uint32_t)32000) -#define I2S_AudioFreq_22k ((uint32_t)22050) -#define I2S_AudioFreq_16k ((uint32_t)16000) -#define I2S_AudioFreq_11k ((uint32_t)11025) -#define I2S_AudioFreq_8k ((uint32_t)8000) -#define I2S_AudioFreq_Default ((uint32_t)2) - -#define IS_I2S_AUDIO_FREQ(FREQ) ((((FREQ) >= I2S_AudioFreq_8k) && \ - ((FREQ) <= I2S_AudioFreq_192k)) || \ - ((FREQ) == I2S_AudioFreq_Default)) -/** - * @} - */ - -/** @defgroup SPI_I2S_Clock_Polarity - * @{ - */ - -#define I2S_CPOL_Low ((uint16_t)0x0000) -#define I2S_CPOL_High SPI_I2SCFGR_CKPOL -#define IS_I2S_CPOL(CPOL) (((CPOL) == I2S_CPOL_Low) || \ - ((CPOL) == I2S_CPOL_High)) -/** - * @} - */ - -/** @defgroup SPI_FIFO_reception_threshold - * @{ - */ - -#define SPI_RxFIFOThreshold_HF ((uint16_t)0x0000) -#define SPI_RxFIFOThreshold_QF SPI_CR2_FRXTH -#define IS_SPI_RX_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) == SPI_RxFIFOThreshold_HF) || \ - ((THRESHOLD) == SPI_RxFIFOThreshold_QF)) -/** - * @} - */ - -/** @defgroup SPI_I2S_DMA_transfer_requests - * @{ - */ - -#define SPI_I2S_DMAReq_Tx SPI_CR2_TXDMAEN -#define SPI_I2S_DMAReq_Rx SPI_CR2_RXDMAEN -#define IS_SPI_I2S_DMA_REQ(REQ) ((((REQ) & (uint16_t)0xFFFC) == 0x00) && ((REQ) != 0x00)) -/** - * @} - */ - -/** @defgroup SPI_last_DMA_transfers - * @{ - */ - -#define SPI_LastDMATransfer_TxEvenRxEven ((uint16_t)0x0000) -#define SPI_LastDMATransfer_TxOddRxEven ((uint16_t)0x4000) -#define SPI_LastDMATransfer_TxEvenRxOdd ((uint16_t)0x2000) -#define SPI_LastDMATransfer_TxOddRxOdd ((uint16_t)0x6000) -#define IS_SPI_LAST_DMA_TRANSFER(TRANSFER) (((TRANSFER) == SPI_LastDMATransfer_TxEvenRxEven) || \ - ((TRANSFER) == SPI_LastDMATransfer_TxOddRxEven) || \ - ((TRANSFER) == SPI_LastDMATransfer_TxEvenRxOdd) || \ - ((TRANSFER) == SPI_LastDMATransfer_TxOddRxOdd)) -/** - * @} - */ -/** @defgroup SPI_NSS_internal_software_management - * @{ - */ - -#define SPI_NSSInternalSoft_Set SPI_CR1_SSI -#define SPI_NSSInternalSoft_Reset ((uint16_t)0xFEFF) -#define IS_SPI_NSS_INTERNAL(INTERNAL) (((INTERNAL) == SPI_NSSInternalSoft_Set) || \ - ((INTERNAL) == SPI_NSSInternalSoft_Reset)) -/** - * @} - */ - -/** @defgroup SPI_CRC_Transmit_Receive - * @{ - */ - -#define SPI_CRC_Tx ((uint8_t)0x00) -#define SPI_CRC_Rx ((uint8_t)0x01) -#define IS_SPI_CRC(CRC) (((CRC) == SPI_CRC_Tx) || ((CRC) == SPI_CRC_Rx)) -/** - * @} - */ - -/** @defgroup SPI_direction_transmit_receive - * @{ - */ - -#define SPI_Direction_Rx ((uint16_t)0xBFFF) -#define SPI_Direction_Tx ((uint16_t)0x4000) -#define IS_SPI_DIRECTION(DIRECTION) (((DIRECTION) == SPI_Direction_Rx) || \ - ((DIRECTION) == SPI_Direction_Tx)) -/** - * @} - */ - -/** @defgroup SPI_I2S_interrupts_definition - * @{ - */ - -#define SPI_I2S_IT_TXE ((uint8_t)0x71) -#define SPI_I2S_IT_RXNE ((uint8_t)0x60) -#define SPI_I2S_IT_ERR ((uint8_t)0x50) - -#define IS_SPI_I2S_CONFIG_IT(IT) (((IT) == SPI_I2S_IT_TXE) || \ - ((IT) == SPI_I2S_IT_RXNE) || \ - ((IT) == SPI_I2S_IT_ERR)) - -#define I2S_IT_UDR ((uint8_t)0x53) -#define SPI_IT_MODF ((uint8_t)0x55) -#define SPI_I2S_IT_OVR ((uint8_t)0x56) -#define SPI_I2S_IT_FRE ((uint8_t)0x58) - -#define IS_SPI_I2S_GET_IT(IT) (((IT) == SPI_I2S_IT_RXNE) || ((IT) == SPI_I2S_IT_TXE) || \ - ((IT) == SPI_I2S_IT_OVR) || ((IT) == SPI_IT_MODF) || \ - ((IT) == SPI_I2S_IT_FRE)|| ((IT) == I2S_IT_UDR)) -/** - * @} - */ - - -/** @defgroup SPI_transmission_fifo_status_level - * @{ - */ - -#define SPI_TransmissionFIFOStatus_Empty ((uint16_t)0x0000) -#define SPI_TransmissionFIFOStatus_1QuarterFull ((uint16_t)0x0800) -#define SPI_TransmissionFIFOStatus_HalfFull ((uint16_t)0x1000) -#define SPI_TransmissionFIFOStatus_Full ((uint16_t)0x1800) - -/** - * @} - */ - -/** @defgroup SPI_reception_fifo_status_level - * @{ - */ -#define SPI_ReceptionFIFOStatus_Empty ((uint16_t)0x0000) -#define SPI_ReceptionFIFOStatus_1QuarterFull ((uint16_t)0x0200) -#define SPI_ReceptionFIFOStatus_HalfFull ((uint16_t)0x0400) -#define SPI_ReceptionFIFOStatus_Full ((uint16_t)0x0600) - -/** - * @} - */ - - -/** @defgroup SPI_I2S_flags_definition - * @{ - */ - -#define SPI_I2S_FLAG_RXNE SPI_SR_RXNE -#define SPI_I2S_FLAG_TXE SPI_SR_TXE -#define I2S_FLAG_CHSIDE SPI_SR_CHSIDE -#define I2S_FLAG_UDR SPI_SR_UDR -#define SPI_FLAG_CRCERR SPI_SR_CRCERR -#define SPI_FLAG_MODF SPI_SR_MODF -#define SPI_I2S_FLAG_OVR SPI_SR_OVR -#define SPI_I2S_FLAG_BSY SPI_SR_BSY -#define SPI_I2S_FLAG_FRE SPI_SR_FRE - - - -#define IS_SPI_CLEAR_FLAG(FLAG) (((FLAG) == SPI_FLAG_CRCERR)) -#define IS_SPI_I2S_GET_FLAG(FLAG) (((FLAG) == SPI_I2S_FLAG_BSY) || ((FLAG) == SPI_I2S_FLAG_OVR) || \ - ((FLAG) == SPI_FLAG_MODF) || ((FLAG) == SPI_FLAG_CRCERR) || \ - ((FLAG) == SPI_I2S_FLAG_TXE) || ((FLAG) == SPI_I2S_FLAG_RXNE)|| \ - ((FLAG) == SPI_I2S_FLAG_FRE)|| ((FLAG) == I2S_FLAG_CHSIDE)|| \ - ((FLAG) == I2S_FLAG_UDR)) -/** - * @} - */ - -/** @defgroup SPI_CRC_polynomial - * @{ - */ - -#define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) ((POLYNOMIAL) >= 0x1) -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions ------------------------------------------------------- */ - -/* Initialization and Configuration functions *********************************/ -void SPI_I2S_DeInit(SPI_TypeDef* SPIx); -void SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct); -void SPI_StructInit(SPI_InitTypeDef* SPI_InitStruct); -void SPI_TIModeCmd(SPI_TypeDef* SPIx, FunctionalState NewState); -void SPI_NSSPulseModeCmd(SPI_TypeDef* SPIx, FunctionalState NewState); -void SPI_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState); -void SPI_DataSizeConfig(SPI_TypeDef* SPIx, uint16_t SPI_DataSize); -void SPI_RxFIFOThresholdConfig(SPI_TypeDef* SPIx, uint16_t SPI_RxFIFOThreshold); -void SPI_BiDirectionalLineConfig(SPI_TypeDef* SPIx, uint16_t SPI_Direction); -void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* SPIx, uint16_t SPI_NSSInternalSoft); -void SPI_SSOutputCmd(SPI_TypeDef* SPIx, FunctionalState NewState); - -/* Data transfers functions ***************************************************/ -void SPI_SendData8(SPI_TypeDef* SPIx, uint8_t Data); -void SPI_I2S_SendData16(SPI_TypeDef* SPIx, uint16_t Data); -uint8_t SPI_ReceiveData8(SPI_TypeDef* SPIx); -uint16_t SPI_I2S_ReceiveData16(SPI_TypeDef* SPIx); - -/* Hardware CRC Calculation functions *****************************************/ -void SPI_CRCLengthConfig(SPI_TypeDef* SPIx, uint16_t SPI_CRCLength); -void SPI_CalculateCRC(SPI_TypeDef* SPIx, FunctionalState NewState); -void SPI_TransmitCRC(SPI_TypeDef* SPIx); -uint16_t SPI_GetCRC(SPI_TypeDef* SPIx, uint8_t SPI_CRC); -uint16_t SPI_GetCRCPolynomial(SPI_TypeDef* SPIx); - -/* DMA transfers management functions *****************************************/ -void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState); -void SPI_LastDMATransferCmd(SPI_TypeDef* SPIx, uint16_t SPI_LastDMATransfer); - -/* Interrupts and flags management functions **********************************/ -void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState); -uint16_t SPI_GetTransmissionFIFOStatus(SPI_TypeDef* SPIx); -uint16_t SPI_GetReceptionFIFOStatus(SPI_TypeDef* SPIx); -FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG); -void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG); -ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT); - -#ifdef __cplusplus -} -#endif - -#endif /*__FT32F0XX_SPI_H */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT FMD *****END OF FILE****/ diff --git a/bsp/ft32/libraries/FT32F0xx/FT32F0xx_Driver/Inc/ft32f0xx_syscfg.h b/bsp/ft32/libraries/FT32F0xx/FT32F0xx_Driver/Inc/ft32f0xx_syscfg.h deleted file mode 100644 index 2b025eacadb..00000000000 --- a/bsp/ft32/libraries/FT32F0xx/FT32F0xx_Driver/Inc/ft32f0xx_syscfg.h +++ /dev/null @@ -1,276 +0,0 @@ -/** - ****************************************************************************** - * @file ft32f0xx_syscfg.h - * @author FMD AE - * @brief This file contains all the functions prototypes for the SYSCFG firmware - * library. - * @version V1.0.0 - * @data 2021-07-01 - ****************************************************************************** - */ - - -/*!< Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __FT32F0XX_SYSCFG_H -#define __FT32F0XX_SYSCFG_H - -#ifdef __cplusplus - extern "C" { -#endif - -/*!< Includes ------------------------------------------------------------------*/ -#include "ft32f0xx.h" - - -/** @addtogroup SYSCFG - * @{ - */ -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup SYSCFG_Exported_Constants - * @{ - */ - -/** @defgroup SYSCFG_EXTI_Port_Sources - * @{ - */ -#define EXTI_PortSourceGPIOA ((uint8_t)0x00) -#define EXTI_PortSourceGPIOB ((uint8_t)0x01) -#define EXTI_PortSourceGPIOC ((uint8_t)0x02) -#define EXTI_PortSourceGPIOD ((uint8_t)0x03) -#define EXTI_PortSourceGPIOE ((uint8_t)0x04) -#define EXTI_PortSourceGPIOF ((uint8_t)0x05) - -#define IS_EXTI_PORT_SOURCE(PORTSOURCE) (((PORTSOURCE) == EXTI_PortSourceGPIOA) || \ - ((PORTSOURCE) == EXTI_PortSourceGPIOB) || \ - ((PORTSOURCE) == EXTI_PortSourceGPIOC) || \ - ((PORTSOURCE) == EXTI_PortSourceGPIOD) || \ - ((PORTSOURCE) == EXTI_PortSourceGPIOE) || \ - ((PORTSOURCE) == EXTI_PortSourceGPIOF)) -/** - * @} - */ - -/** @defgroup SYSCFG_EXTI_Pin_sources - * @{ - */ -#define EXTI_PinSource0 ((uint8_t)0x00) -#define EXTI_PinSource1 ((uint8_t)0x01) -#define EXTI_PinSource2 ((uint8_t)0x02) -#define EXTI_PinSource3 ((uint8_t)0x03) -#define EXTI_PinSource4 ((uint8_t)0x04) -#define EXTI_PinSource5 ((uint8_t)0x05) -#define EXTI_PinSource6 ((uint8_t)0x06) -#define EXTI_PinSource7 ((uint8_t)0x07) -#define EXTI_PinSource8 ((uint8_t)0x08) -#define EXTI_PinSource9 ((uint8_t)0x09) -#define EXTI_PinSource10 ((uint8_t)0x0A) -#define EXTI_PinSource11 ((uint8_t)0x0B) -#define EXTI_PinSource12 ((uint8_t)0x0C) -#define EXTI_PinSource13 ((uint8_t)0x0D) -#define EXTI_PinSource14 ((uint8_t)0x0E) -#define EXTI_PinSource15 ((uint8_t)0x0F) - -#define IS_EXTI_PIN_SOURCE(PINSOURCE) (((PINSOURCE) == EXTI_PinSource0) || \ - ((PINSOURCE) == EXTI_PinSource1) || \ - ((PINSOURCE) == EXTI_PinSource2) || \ - ((PINSOURCE) == EXTI_PinSource3) || \ - ((PINSOURCE) == EXTI_PinSource4) || \ - ((PINSOURCE) == EXTI_PinSource5) || \ - ((PINSOURCE) == EXTI_PinSource6) || \ - ((PINSOURCE) == EXTI_PinSource7) || \ - ((PINSOURCE) == EXTI_PinSource8) || \ - ((PINSOURCE) == EXTI_PinSource9) || \ - ((PINSOURCE) == EXTI_PinSource10) || \ - ((PINSOURCE) == EXTI_PinSource11) || \ - ((PINSOURCE) == EXTI_PinSource12) || \ - ((PINSOURCE) == EXTI_PinSource13) || \ - ((PINSOURCE) == EXTI_PinSource14) || \ - ((PINSOURCE) == EXTI_PinSource15)) -/** - * @} - */ - -/** @defgroup SYSCFG_Memory_Remap_Config - * @{ - */ -#define SYSCFG_MemoryRemap_Flash ((uint8_t)0x00) -#define SYSCFG_MemoryRemap_SystemMemory ((uint8_t)0x01) -#define SYSCFG_MemoryRemap_SRAM ((uint8_t)0x03) - - -#define IS_SYSCFG_MEMORY_REMAP(REMAP) (((REMAP) == SYSCFG_MemoryRemap_Flash) || \ - ((REMAP) == SYSCFG_MemoryRemap_SystemMemory) || \ - ((REMAP) == SYSCFG_MemoryRemap_SRAM)) - -/** - * @} - */ - -/** @defgroup SYSCFG_DMA_Remap_Config - * @{ - */ -#define SYSCFG_DMARemap_TIM3 SYSCFG_CFGR1_TIM3_DMA_RMP /* Remap TIM3 DMA requests from channel4 to channel6*/ -#define SYSCFG_DMARemap_TIM2 SYSCFG_CFGR1_TIM2_DMA_RMP /* Remap TIM2 DMA requests from channel3/4 to channel7*/ -#define SYSCFG_DMARemap_TIM1 SYSCFG_CFGR1_TIM1_DMA_RMP /* Remap TIM1 DMA requests from channel2/3/4 to channel6*/ -#define SYSCFG_DMARemap_I2C1 SYSCFG_CFGR1_I2C1_DMA_RMP /* Remap I2C1 DMA requests from channel3/2 to channel7/6*/ -#define SYSCFG_DMARemap_USART3 SYSCFG_CFGR1_USART3_DMA_RMP /* Remap USART3 DMA requests from channel6/7 to channel3/2*/ -#define SYSCFG_DMARemap_USART2 SYSCFG_CFGR1_USART2_DMA_RMP /* Remap USART2 DMA requests from channel4/5 to channel6/7*/ -#define SYSCFG_DMARemap_SPI2 SYSCFG_CFGR1_SPI2_DMA_RMP /* Remap SPI2 DMA requests from channel4/5 to channel6/7*/ -#define SYSCFG_DMARemap_TIM17_2 SYSCFG_CFGR1_TIM17_DMA_RMP2 /* Remap TIM17 DMA requests from channel1/2 to channel7*/ -#define SYSCFG_DMARemap_TIM16_2 SYSCFG_CFGR1_TIM16_DMA_RMP2 /* Remap TIM16 DMA requests from channel3/4 to channel6*/ -#define SYSCFG_DMARemap_TIM17 SYSCFG_CFGR1_TIM17_DMA_RMP /* Remap TIM17 DMA requests from channel1 to channel2*/ -#define SYSCFG_DMARemap_TIM16 SYSCFG_CFGR1_TIM16_DMA_RMP /* Remap TIM16 DMA requests from channel3 to channel4*/ -#define SYSCFG_DMARemap_USART1Rx SYSCFG_CFGR1_USART1RX_DMA_RMP /* Remap USART1 Rx DMA requests from channel3 to channel5*/ -#define SYSCFG_DMARemap_USART1Tx SYSCFG_CFGR1_USART1TX_DMA_RMP /* Remap USART1 Tx DMA requests from channel2 to channel4*/ -#define SYSCFG_DMARemap_ADC1 SYSCFG_CFGR1_ADC_DMA_RMP /* Remap ADC1 DMA requests from channel1 to channel2*/ - -#define IS_SYSCFG_DMA_REMAP(REMAP) (((REMAP) == SYSCFG_DMARemap_TIM17) || \ - ((REMAP) == SYSCFG_DMARemap_TIM16) || \ - ((REMAP) == SYSCFG_DMARemap_USART1Rx) || \ - ((REMAP) == SYSCFG_DMARemap_USART1Tx) || \ - ((REMAP) == SYSCFG_CFGR1_TIM3_DMA_RMP) || \ - ((REMAP) == SYSCFG_CFGR1_TIM2_DMA_RMP) || \ - ((REMAP) == SYSCFG_CFGR1_TIM1_DMA_RMP) || \ - ((REMAP) == SYSCFG_CFGR1_I2C1_DMA_RMP) || \ - ((REMAP) == SYSCFG_CFGR1_USART3_DMA_RMP) || \ - ((REMAP) == SYSCFG_CFGR1_USART2_DMA_RMP) || \ - ((REMAP) == SYSCFG_CFGR1_SPI2_DMA_RMP) || \ - ((REMAP) == SYSCFG_CFGR1_TIM17_DMA_RMP2) || \ - ((REMAP) == SYSCFG_CFGR1_TIM16_DMA_RMP2) || \ - ((REMAP) == SYSCFG_DMARemap_ADC1)) - -/** - * @} - */ - -/** @defgroup SYSCFG_I2C_FastModePlus_Config - * @{ - */ -#define SYSCFG_I2CFastModePlus_PB6 SYSCFG_CFGR1_I2C_FMP_PB6 /* Enable Fast Mode Plus on PB6 */ -#define SYSCFG_I2CFastModePlus_PB7 SYSCFG_CFGR1_I2C_FMP_PB7 /* Enable Fast Mode Plus on PB7 */ -#define SYSCFG_I2CFastModePlus_PB8 SYSCFG_CFGR1_I2C_FMP_PB8 /* Enable Fast Mode Plus on PB8 */ -#define SYSCFG_I2CFastModePlus_PB9 SYSCFG_CFGR1_I2C_FMP_PB9 /* Enable Fast Mode Plus on PB9 */ -#define SYSCFG_I2CFastModePlus_I2C1 SYSCFG_CFGR1_I2C_FMP_I2C1 /* Enable Fast Mode Plus on PB10, PB11, PF6 and PF7*/ -#define SYSCFG_I2CFastModePlus_I2C2 SYSCFG_CFGR1_I2C_FMP_I2C2 /* Enable Fast Mode Plus on I2C2 pins*/ -#define SYSCFG_I2CFastModePlus_PA9 SYSCFG_CFGR1_I2C_FMP_PA9 /* Enable Fast Mode Plus on PA9*/ -#define SYSCFG_I2CFastModePlus_PA10 SYSCFG_CFGR1_I2C_FMP_PA10/* Enable Fast Mode Plus on PA10*/ - -#define IS_SYSCFG_I2C_FMP(PIN) (((PIN) == SYSCFG_I2CFastModePlus_PB6) || \ - ((PIN) == SYSCFG_I2CFastModePlus_PB7) || \ - ((PIN) == SYSCFG_I2CFastModePlus_PB8) || \ - ((PIN) == SYSCFG_I2CFastModePlus_PB9) || \ - ((PIN) == SYSCFG_I2CFastModePlus_I2C1) || \ - ((PIN) == SYSCFG_I2CFastModePlus_I2C2) || \ - ((PIN) == SYSCFG_I2CFastModePlus_PA9) || \ - ((PIN) == SYSCFG_I2CFastModePlus_PA10)) - - -/** - * @} - */ - -/** @defgroup SYSCFG_Lock_Config - * @{ - */ -#define SYSCFG_Break_PVD SYSCFG_CFGR2_PVD_LOCK /*!< Connects the PVD event to the Break Input of TIM1 */ -#define SYSCFG_Break_Lockup SYSCFG_CFGR2_LOCKUP_LOCK /*!< Connects Lockup output of CortexM0 to the break input of TIM1 */ - -#define IS_SYSCFG_LOCK_CONFIG(CONFIG) (((CONFIG) == SYSCFG_Break_PVD) || \ - ((CONFIG) == SYSCFG_Break_Lockup)) - -/** - * @} - */ - -/** - * @} - */ - -/** @defgroup SYSCFG_ISR_WRAPPER - * @{ - */ -#define SYSCFG_ITLINE0 ((uint32_t) 0x00000000) -#define SYSCFG_ITLINE1 ((uint32_t) 0x00000001) -#define SYSCFG_ITLINE2 ((uint32_t) 0x00000002) -#define SYSCFG_ITLINE3 ((uint32_t) 0x00000003) -#define SYSCFG_ITLINE4 ((uint32_t) 0x00000004) -#define SYSCFG_ITLINE5 ((uint32_t) 0x00000005) -#define SYSCFG_ITLINE6 ((uint32_t) 0x00000006) -#define SYSCFG_ITLINE7 ((uint32_t) 0x00000007) -#define SYSCFG_ITLINE8 ((uint32_t) 0x00000008) -#define SYSCFG_ITLINE9 ((uint32_t) 0x00000009) -#define SYSCFG_ITLINE10 ((uint32_t) 0x0000000A) -#define SYSCFG_ITLINE11 ((uint32_t) 0x0000000B) -#define SYSCFG_ITLINE12 ((uint32_t) 0x0000000C) -#define SYSCFG_ITLINE13 ((uint32_t) 0x0000000D) -#define SYSCFG_ITLINE14 ((uint32_t) 0x0000000E) -#define SYSCFG_ITLINE15 ((uint32_t) 0x0000000F) -#define SYSCFG_ITLINE16 ((uint32_t) 0x00000010) -#define SYSCFG_ITLINE17 ((uint32_t) 0x00000011) -#define SYSCFG_ITLINE18 ((uint32_t) 0x00000012) -#define SYSCFG_ITLINE19 ((uint32_t) 0x00000013) -#define SYSCFG_ITLINE20 ((uint32_t) 0x00000014) -#define SYSCFG_ITLINE21 ((uint32_t) 0x00000015) -#define SYSCFG_ITLINE22 ((uint32_t) 0x00000016) -#define SYSCFG_ITLINE23 ((uint32_t) 0x00000017) -#define SYSCFG_ITLINE24 ((uint32_t) 0x00000018) -#define SYSCFG_ITLINE25 ((uint32_t) 0x00000019) -#define SYSCFG_ITLINE26 ((uint32_t) 0x0000001A) -#define SYSCFG_ITLINE27 ((uint32_t) 0x0000001B) -#define SYSCFG_ITLINE28 ((uint32_t) 0x0000001C) -#define SYSCFG_ITLINE29 ((uint32_t) 0x0000001D) -#define SYSCFG_ITLINE30 ((uint32_t) 0x0000001E) -#define SYSCFG_ITLINE31 ((uint32_t) 0x0000001F) - -/** - * @} - */ -/** @defgroup IRDA_ENV_SEL - * @{ - */ -#define SYSCFG_IRDA_ENV_SEL_TIM16 (SYSCFG_CFGR1_IRDA_ENV_SEL_0&SYSCFG_CFGR1_IRDA_ENV_SEL_1) /* Timer16 is selected as IRDA Modulation envelope source */ -#define SYSCFG_IRDA_ENV_SEL_USART1 (SYSCFG_CFGR1_IRDA_ENV_SEL_0) /* USART1 is selected as IRDA Modulation envelope source.*/ -#define SYSCFG_IRDA_ENV_SEL_USART2 (SYSCFG_CFGR1_IRDA_ENV_SEL_1) /* USART2 is selected as IRDA Modulation envelope source.*/ - -#define IS_SYSCFG_IRDA_ENV(ENV) (((ENV) == SYSCFG_IRDA_ENV_SEL_TIM16) || \ - ((ENV) == SYSCFG_IRDA_ENV_SEL_USART1) || \ - ((ENV) == SYSCFG_IRDA_ENV_SEL_USART2)) -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions ------------------------------------------------------- */ - -/* Function used to set the SYSCFG configuration to the default reset state **/ -void SYSCFG_DeInit(void); - -/* SYSCFG configuration functions *********************************************/ -void SYSCFG_MemoryRemapConfig(uint32_t SYSCFG_MemoryRemap); -void SYSCFG_DMAChannelRemapConfig(uint32_t SYSCFG_DMARemap, FunctionalState NewState); -void SYSCFG_I2CFastModePlusConfig(uint32_t SYSCFG_I2CFastModePlus, FunctionalState NewState); -void SYSCFG_IRDAEnvSelection(uint32_t SYSCFG_IRDAEnv); -void SYSCFG_EXTILineConfig(uint8_t EXTI_PortSourceGPIOx, uint8_t EXTI_PinSourcex); -void SYSCFG_BreakConfig(uint32_t SYSCFG_Break); - -#ifdef __cplusplus -} -#endif - -#endif /*__FT32F0XX_SYSCFG_H */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT FMD *****END OF FILE****/ diff --git a/bsp/ft32/libraries/FT32F0xx/FT32F0xx_Driver/Inc/ft32f0xx_tim.h b/bsp/ft32/libraries/FT32F0xx/FT32F0xx_Driver/Inc/ft32f0xx_tim.h deleted file mode 100644 index 002665cbbee..00000000000 --- a/bsp/ft32/libraries/FT32F0xx/FT32F0xx_Driver/Inc/ft32f0xx_tim.h +++ /dev/null @@ -1,1167 +0,0 @@ -/** - ****************************************************************************** - * @file ft32f0xx_tim.h - * @author FMD AE - * @brief This file contains all the functions prototypes for the TIM - * firmware library. - * @version V1.0.0 - * @data 2021-07-01 - ****************************************************************************** - */ - - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __FT32F0XX_TIM_H -#define __FT32F0XX_TIM_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "ft32f0xx.h" - - -/** @addtogroup TIM - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ - -/** - * @brief TIM Time Base Init structure definition - * @note This sturcture is used with all TIMx. - */ - -typedef struct -{ - uint16_t TIM_Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock. - This parameter can be a number between 0x0000 and 0xFFFF */ - - uint16_t TIM_CounterMode; /*!< Specifies the counter mode. - This parameter can be a value of @ref TIM_Counter_Mode */ - - uint32_t TIM_Period; /*!< Specifies the period value to be loaded into the active - Auto-Reload Register at the next update event. - This parameter must be a number between 0x0000 and 0xFFFF. */ - - uint16_t TIM_ClockDivision; /*!< Specifies the clock division. - This parameter can be a value of @ref TIM_Clock_Division_CKD */ - - uint8_t TIM_RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter - reaches zero, an update event is generated and counting restarts - from the RCR value (N). - This means in PWM mode that (N+1) corresponds to: - - the number of PWM periods in edge-aligned mode - - the number of half PWM period in center-aligned mode - This parameter must be a number between 0x00 and 0xFF. - @note This parameter is valid only for TIM1. */ -} TIM_TimeBaseInitTypeDef; - -/** - * @brief TIM Output Compare Init structure definition - */ - -typedef struct -{ - uint16_t TIM_OCMode; /*!< Specifies the TIM mode. - This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */ - - uint16_t TIM_OutputState; /*!< Specifies the TIM Output Compare state. - This parameter can be a value of @ref TIM_Output_Compare_state */ - - uint16_t TIM_OutputNState; /*!< Specifies the TIM complementary Output Compare state. - This parameter can be a value of @ref TIM_Output_Compare_N_state - @note This parameter is valid only for TIM1. */ - - uint32_t TIM_Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. - This parameter can be a number between 0x0000 and 0xFFFF ( or 0xFFFFFFFF - for TIM2) */ - - uint16_t TIM_OCPolarity; /*!< Specifies the output polarity. - This parameter can be a value of @ref TIM_Output_Compare_Polarity */ - - uint16_t TIM_OCNPolarity; /*!< Specifies the complementary output polarity. - This parameter can be a value of @ref TIM_Output_Compare_N_Polarity - @note This parameter is valid only for TIM1. */ - - uint16_t TIM_OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. - This parameter can be a value of @ref TIM_Output_Compare_Idle_State - @note This parameter is valid only for TIM1. */ - - uint16_t TIM_OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. - This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State - @note This parameter is valid only for TIM1. */ -} TIM_OCInitTypeDef; - -/** - * @brief TIM Input Capture Init structure definition - */ - -typedef struct -{ - - uint16_t TIM_Channel; /*!< Specifies the TIM channel. - This parameter can be a value of @ref TIM_Channel */ - - uint16_t TIM_ICPolarity; /*!< Specifies the active edge of the input signal. - This parameter can be a value of @ref TIM_Input_Capture_Polarity */ - - uint16_t TIM_ICSelection; /*!< Specifies the input. - This parameter can be a value of @ref TIM_Input_Capture_Selection */ - - uint16_t TIM_ICPrescaler; /*!< Specifies the Input Capture Prescaler. - This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ - - uint16_t TIM_ICFilter; /*!< Specifies the input capture filter. - This parameter can be a number between 0x0 and 0xF */ -} TIM_ICInitTypeDef; - -/** - * @brief TIM_BDTR structure definition - * @note This sturcture is used only with TIM1. - */ - -typedef struct -{ - - uint16_t TIM_OSSRState; /*!< Specifies the Off-State selection used in Run mode. - This parameter can be a value of @ref TIM_OSSR_Off_State_Selection_for_Run_mode_state */ - - uint16_t TIM_OSSIState; /*!< Specifies the Off-State used in Idle state. - This parameter can be a value of @ref TIM_OSSI_Off_State_Selection_for_Idle_mode_state */ - - uint16_t TIM_LOCKLevel; /*!< Specifies the LOCK level parameters. - This parameter can be a value of @ref TIM_Lock_level */ - - uint16_t TIM_DeadTime; /*!< Specifies the delay time between the switching-off and the - switching-on of the outputs. - This parameter can be a number between 0x00 and 0xFF */ - - uint16_t TIM_Break; /*!< Specifies whether the TIM Break input is enabled or not. - This parameter can be a value of @ref TIM_Break_Input_enable_disable */ - - uint16_t TIM_BreakPolarity; /*!< Specifies the TIM Break Input pin polarity. - This parameter can be a value of @ref TIM_Break_Polarity */ - - uint16_t TIM_AutomaticOutput; /*!< Specifies whether the TIM Automatic Output feature is enabled or not. - This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */ -} TIM_BDTRInitTypeDef; - -/** - * @brief TIM Input Capture Init structure definition - */ - -/* Exported constants --------------------------------------------------------*/ - - -/** @defgroup TIM_Exported_constants - * @{ - */ - -#define IS_TIM_ALL_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ - ((PERIPH) == TIM2) || \ - ((PERIPH) == TIM3) || \ - ((PERIPH) == TIM6) || \ - ((PERIPH) == TIM7) || \ - ((PERIPH) == TIM14)|| \ - ((PERIPH) == TIM15)|| \ - ((PERIPH) == TIM16)|| \ - ((PERIPH) == TIM17)) - -/* LIST1: TIM 1 */ -#define IS_TIM_LIST1_PERIPH(PERIPH) ((PERIPH) == TIM1) - -/* LIST2: TIM 1, 15, 16 and 17 */ -#define IS_TIM_LIST2_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ - ((PERIPH) == TIM15)|| \ - ((PERIPH) == TIM16)|| \ - ((PERIPH) == TIM17)) - -/* LIST3: TIM 1, 2 and 3 */ -#define IS_TIM_LIST3_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ - ((PERIPH) == TIM2) || \ - ((PERIPH) == TIM3)) - -/* LIST4: TIM 1, 2, 3, 14, 15, 16 and 17 */ -#define IS_TIM_LIST4_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ - ((PERIPH) == TIM2) || \ - ((PERIPH) == TIM3) || \ - ((PERIPH) == TIM14) || \ - ((PERIPH) == TIM15)|| \ - ((PERIPH) == TIM16)|| \ - ((PERIPH) == TIM17)) - -/* LIST5: TIM 1, 2, 3, 15, 16 and 17 */ -#define IS_TIM_LIST5_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ - ((PERIPH) == TIM2) || \ - ((PERIPH) == TIM3) || \ - ((PERIPH) == TIM15)|| \ - ((PERIPH) == TIM16)|| \ - ((PERIPH) == TIM17)) - -/* LIST6: TIM 1, 2, 3 and 15 */ -#define IS_TIM_LIST6_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ - ((PERIPH) == TIM2) || \ - ((PERIPH) == TIM3) || \ - ((PERIPH) == TIM15)) - -/* LIST7: TIM 1, 2, 3, 6, 7 and 14 */ -#define IS_TIM_LIST7_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ - ((PERIPH) == TIM2) || \ - ((PERIPH) == TIM3) || \ - ((PERIPH) == TIM6) || \ - ((PERIPH) == TIM7) || \ - ((PERIPH) == TIM14)) - -/* LIST8: TIM 1, 2, 3 and 14 */ -#define IS_TIM_LIST8_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ - ((PERIPH) == TIM2) || \ - ((PERIPH) == TIM3) || \ - ((PERIPH) == TIM14)) - -/* LIST9: TIM 1, 2, 3, 6, 7 and 15 */ -#define IS_TIM_LIST9_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ - ((PERIPH) == TIM2) || \ - ((PERIPH) == TIM3) || \ - ((PERIPH) == TIM6) || \ - ((PERIPH) == TIM7) || \ - ((PERIPH) == TIM15)) - -/* LIST10: TIM 1, 2, 3, 6, 7, 15, 16 and 17 */ -#define IS_TIM_LIST10_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ - ((PERIPH) == TIM2) || \ - ((PERIPH) == TIM3) || \ - ((PERIPH) == TIM6) || \ - ((PERIPH) == TIM7) || \ - ((PERIPH) == TIM15)|| \ - ((PERIPH) == TIM16)|| \ - ((PERIPH) == TIM17)) - -/* LIST1: TIM 11 */ -#define IS_TIM_LIST11_PERIPH(PERIPH) ((PERIPH) == TIM14) - - -/** - * @} - */ - -/** @defgroup TIM_Output_Compare_and_PWM_modes - * @{ - */ - -#define TIM_OCMode_Timing ((uint16_t)0x0000) -#define TIM_OCMode_Active ((uint16_t)0x0010) -#define TIM_OCMode_Inactive ((uint16_t)0x0020) -#define TIM_OCMode_Toggle ((uint16_t)0x0030) -#define TIM_OCMode_PWM1 ((uint16_t)0x0060) -#define TIM_OCMode_PWM2 ((uint16_t)0x0070) -#define IS_TIM_OC_MODE(MODE) (((MODE) == TIM_OCMode_Timing) || \ - ((MODE) == TIM_OCMode_Active) || \ - ((MODE) == TIM_OCMode_Inactive) || \ - ((MODE) == TIM_OCMode_Toggle)|| \ - ((MODE) == TIM_OCMode_PWM1) || \ - ((MODE) == TIM_OCMode_PWM2)) -#define IS_TIM_OCM(MODE) (((MODE) == TIM_OCMode_Timing) || \ - ((MODE) == TIM_OCMode_Active) || \ - ((MODE) == TIM_OCMode_Inactive) || \ - ((MODE) == TIM_OCMode_Toggle)|| \ - ((MODE) == TIM_OCMode_PWM1) || \ - ((MODE) == TIM_OCMode_PWM2) || \ - ((MODE) == TIM_ForcedAction_Active) || \ - ((MODE) == TIM_ForcedAction_InActive)) -/** - * @} - */ - -/** @defgroup TIM_One_Pulse_Mode - * @{ - */ - -#define TIM_OPMode_Single ((uint16_t)0x0008) -#define TIM_OPMode_Repetitive ((uint16_t)0x0000) -#define IS_TIM_OPM_MODE(MODE) (((MODE) == TIM_OPMode_Single) || \ - ((MODE) == TIM_OPMode_Repetitive)) -/** - * @} - */ - -/** @defgroup TIM_Channel - * @{ - */ - -#define TIM_Channel_1 ((uint16_t)0x0000) -#define TIM_Channel_2 ((uint16_t)0x0004) -#define TIM_Channel_3 ((uint16_t)0x0008) -#define TIM_Channel_4 ((uint16_t)0x000C) - -#define IS_TIM_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \ - ((CHANNEL) == TIM_Channel_2) || \ - ((CHANNEL) == TIM_Channel_3) || \ - ((CHANNEL) == TIM_Channel_4)) -#define IS_TIM_COMPLEMENTARY_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \ - ((CHANNEL) == TIM_Channel_2) || \ - ((CHANNEL) == TIM_Channel_3)) -#define IS_TIM_PWMI_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \ - ((CHANNEL) == TIM_Channel_2)) - -/** - * @} - */ - -/** @defgroup TIM_Clock_Division_CKD - * @{ - */ - -#define TIM_CKD_DIV1 ((uint16_t)0x0000) -#define TIM_CKD_DIV2 ((uint16_t)0x0100) -#define TIM_CKD_DIV4 ((uint16_t)0x0200) -#define IS_TIM_CKD_DIV(DIV) (((DIV) == TIM_CKD_DIV1) || \ - ((DIV) == TIM_CKD_DIV2) || \ - ((DIV) == TIM_CKD_DIV4)) -/** - * @} - */ - -/** @defgroup TIM_Counter_Mode - * @{ - */ - -#define TIM_CounterMode_Up ((uint16_t)0x0000) -#define TIM_CounterMode_Down ((uint16_t)0x0010) -#define TIM_CounterMode_CenterAligned1 ((uint16_t)0x0020) -#define TIM_CounterMode_CenterAligned2 ((uint16_t)0x0040) -#define TIM_CounterMode_CenterAligned3 ((uint16_t)0x0060) -#define IS_TIM_COUNTER_MODE(MODE) (((MODE) == TIM_CounterMode_Up) || \ - ((MODE) == TIM_CounterMode_Down) || \ - ((MODE) == TIM_CounterMode_CenterAligned1) || \ - ((MODE) == TIM_CounterMode_CenterAligned2) || \ - ((MODE) == TIM_CounterMode_CenterAligned3)) -/** - * @} - */ - -/** @defgroup TIM_Output_Compare_Polarity - * @{ - */ - -#define TIM_OCPolarity_High ((uint16_t)0x0000) -#define TIM_OCPolarity_Low ((uint16_t)0x0002) -#define IS_TIM_OC_POLARITY(POLARITY) (((POLARITY) == TIM_OCPolarity_High) || \ - ((POLARITY) == TIM_OCPolarity_Low)) -/** - * @} - */ - -/** @defgroup TIM_Output_Compare_N_Polarity - * @{ - */ - -#define TIM_OCNPolarity_High ((uint16_t)0x0000) -#define TIM_OCNPolarity_Low ((uint16_t)0x0008) -#define IS_TIM_OCN_POLARITY(POLARITY) (((POLARITY) == TIM_OCNPolarity_High) || \ - ((POLARITY) == TIM_OCNPolarity_Low)) -/** - * @} - */ - -/** @defgroup TIM_Output_Compare_state - * @{ - */ - -#define TIM_OutputState_Disable ((uint16_t)0x0000) -#define TIM_OutputState_Enable ((uint16_t)0x0001) -#define IS_TIM_OUTPUT_STATE(STATE) (((STATE) == TIM_OutputState_Disable) || \ - ((STATE) == TIM_OutputState_Enable)) -/** - * @} - */ - -/** @defgroup TIM_Output_Compare_N_state - * @{ - */ - -#define TIM_OutputNState_Disable ((uint16_t)0x0000) -#define TIM_OutputNState_Enable ((uint16_t)0x0004) -#define IS_TIM_OUTPUTN_STATE(STATE) (((STATE) == TIM_OutputNState_Disable) || \ - ((STATE) == TIM_OutputNState_Enable)) -/** - * @} - */ - -/** @defgroup TIM_Capture_Compare_state - * @{ - */ - -#define TIM_CCx_Enable ((uint16_t)0x0001) -#define TIM_CCx_Disable ((uint16_t)0x0000) -#define IS_TIM_CCX(CCX) (((CCX) == TIM_CCx_Enable) || \ - ((CCX) == TIM_CCx_Disable)) -/** - * @} - */ - -/** @defgroup TIM_Capture_Compare_N_state - * @{ - */ - -#define TIM_CCxN_Enable ((uint16_t)0x0004) -#define TIM_CCxN_Disable ((uint16_t)0x0000) -#define IS_TIM_CCXN(CCXN) (((CCXN) == TIM_CCxN_Enable) || \ - ((CCXN) == TIM_CCxN_Disable)) -/** - * @} - */ - -/** @defgroup TIM_Break_Input_enable_disable - * @{ - */ - -#define TIM_Break_Enable ((uint16_t)0x1000) -#define TIM_Break_Disable ((uint16_t)0x0000) -#define IS_TIM_BREAK_STATE(STATE) (((STATE) == TIM_Break_Enable) || \ - ((STATE) == TIM_Break_Disable)) -/** - * @} - */ - -/** @defgroup TIM_Break_Polarity - * @{ - */ - -#define TIM_BreakPolarity_Low ((uint16_t)0x0000) -#define TIM_BreakPolarity_High ((uint16_t)0x2000) -#define IS_TIM_BREAK_POLARITY(POLARITY) (((POLARITY) == TIM_BreakPolarity_Low) || \ - ((POLARITY) == TIM_BreakPolarity_High)) -/** - * @} - */ - -/** @defgroup TIM_AOE_Bit_Set_Reset - * @{ - */ - -#define TIM_AutomaticOutput_Enable ((uint16_t)0x4000) -#define TIM_AutomaticOutput_Disable ((uint16_t)0x0000) -#define IS_TIM_AUTOMATIC_OUTPUT_STATE(STATE) (((STATE) == TIM_AutomaticOutput_Enable) || \ - ((STATE) == TIM_AutomaticOutput_Disable)) -/** - * @} - */ - -/** @defgroup TIM_Lock_level - * @{ - */ - -#define TIM_LOCKLevel_OFF ((uint16_t)0x0000) -#define TIM_LOCKLevel_1 ((uint16_t)0x0100) -#define TIM_LOCKLevel_2 ((uint16_t)0x0200) -#define TIM_LOCKLevel_3 ((uint16_t)0x0300) -#define IS_TIM_LOCK_LEVEL(LEVEL) (((LEVEL) == TIM_LOCKLevel_OFF) || \ - ((LEVEL) == TIM_LOCKLevel_1) || \ - ((LEVEL) == TIM_LOCKLevel_2) || \ - ((LEVEL) == TIM_LOCKLevel_3)) -/** - * @} - */ - -/** @defgroup TIM_OSSI_Off_State_Selection_for_Idle_mode_state - * @{ - */ - -#define TIM_OSSIState_Enable ((uint16_t)0x0400) -#define TIM_OSSIState_Disable ((uint16_t)0x0000) -#define IS_TIM_OSSI_STATE(STATE) (((STATE) == TIM_OSSIState_Enable) || \ - ((STATE) == TIM_OSSIState_Disable)) -/** - * @} - */ - -/** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state - * @{ - */ - -#define TIM_OSSRState_Enable ((uint16_t)0x0800) -#define TIM_OSSRState_Disable ((uint16_t)0x0000) -#define IS_TIM_OSSR_STATE(STATE) (((STATE) == TIM_OSSRState_Enable) || \ - ((STATE) == TIM_OSSRState_Disable)) -/** - * @} - */ - -/** @defgroup TIM_Output_Compare_Idle_State - * @{ - */ - -#define TIM_OCIdleState_Set ((uint16_t)0x0100) -#define TIM_OCIdleState_Reset ((uint16_t)0x0000) -#define IS_TIM_OCIDLE_STATE(STATE) (((STATE) == TIM_OCIdleState_Set) || \ - ((STATE) == TIM_OCIdleState_Reset)) -/** - * @} - */ - -/** @defgroup TIM_Output_Compare_N_Idle_State - * @{ - */ - -#define TIM_OCNIdleState_Set ((uint16_t)0x0200) -#define TIM_OCNIdleState_Reset ((uint16_t)0x0000) -#define IS_TIM_OCNIDLE_STATE(STATE) (((STATE) == TIM_OCNIdleState_Set) || \ - ((STATE) == TIM_OCNIdleState_Reset)) -/** - * @} - */ - -/** @defgroup TIM_Input_Capture_Polarity - * @{ - */ - -#define TIM_ICPolarity_Rising ((uint16_t)0x0000) -#define TIM_ICPolarity_Falling ((uint16_t)0x0002) -#define TIM_ICPolarity_BothEdge ((uint16_t)0x000A) -#define IS_TIM_IC_POLARITY(POLARITY) (((POLARITY) == TIM_ICPolarity_Rising) || \ - ((POLARITY) == TIM_ICPolarity_Falling)|| \ - ((POLARITY) == TIM_ICPolarity_BothEdge)) -/** - * @} - */ - -/** @defgroup TIM_Input_Capture_Selection - * @{ - */ - -#define TIM_ICSelection_DirectTI ((uint16_t)0x0001) /*!< TIM Input 1, 2, 3 or 4 is selected to be - connected to IC1, IC2, IC3 or IC4, respectively */ -#define TIM_ICSelection_IndirectTI ((uint16_t)0x0002) /*!< TIM Input 1, 2, 3 or 4 is selected to be - connected to IC2, IC1, IC4 or IC3, respectively. */ -#define TIM_ICSelection_TRC ((uint16_t)0x0003) /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC. */ -#define IS_TIM_IC_SELECTION(SELECTION) (((SELECTION) == TIM_ICSelection_DirectTI) || \ - ((SELECTION) == TIM_ICSelection_IndirectTI) || \ - ((SELECTION) == TIM_ICSelection_TRC)) -/** - * @} - */ - -/** @defgroup TIM_Input_Capture_Prescaler - * @{ - */ - -#define TIM_ICPSC_DIV1 ((uint16_t)0x0000) /*!< Capture performed each time an edge is detected on the capture input. */ -#define TIM_ICPSC_DIV2 ((uint16_t)0x0004) /*!< Capture performed once every 2 events. */ -#define TIM_ICPSC_DIV4 ((uint16_t)0x0008) /*!< Capture performed once every 4 events. */ -#define TIM_ICPSC_DIV8 ((uint16_t)0x000C) /*!< Capture performed once every 8 events. */ -#define IS_TIM_IC_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ICPSC_DIV1) || \ - ((PRESCALER) == TIM_ICPSC_DIV2) || \ - ((PRESCALER) == TIM_ICPSC_DIV4) || \ - ((PRESCALER) == TIM_ICPSC_DIV8)) -/** - * @} - */ - -/** @defgroup TIM_interrupt_sources - * @{ - */ - -#define TIM_IT_Update ((uint16_t)0x0001) -#define TIM_IT_CC1 ((uint16_t)0x0002) -#define TIM_IT_CC2 ((uint16_t)0x0004) -#define TIM_IT_CC3 ((uint16_t)0x0008) -#define TIM_IT_CC4 ((uint16_t)0x0010) -#define TIM_IT_COM ((uint16_t)0x0020) -#define TIM_IT_Trigger ((uint16_t)0x0040) -#define TIM_IT_Break ((uint16_t)0x0080) -#define IS_TIM_IT(IT) ((((IT) & (uint16_t)0xFF00) == 0x0000) && ((IT) != 0x0000)) - -#define IS_TIM_GET_IT(IT) (((IT) == TIM_IT_Update) || \ - ((IT) == TIM_IT_CC1) || \ - ((IT) == TIM_IT_CC2) || \ - ((IT) == TIM_IT_CC3) || \ - ((IT) == TIM_IT_CC4) || \ - ((IT) == TIM_IT_COM) || \ - ((IT) == TIM_IT_Trigger) || \ - ((IT) == TIM_IT_Break)) -/** - * @} - */ - -/** @defgroup TIM_DMA_Base_address - * @{ - */ - -#define TIM_DMABase_CR1 ((uint16_t)0x0000) -#define TIM_DMABase_CR2 ((uint16_t)0x0001) -#define TIM_DMABase_SMCR ((uint16_t)0x0002) -#define TIM_DMABase_DIER ((uint16_t)0x0003) -#define TIM_DMABase_SR ((uint16_t)0x0004) -#define TIM_DMABase_EGR ((uint16_t)0x0005) -#define TIM_DMABase_CCMR1 ((uint16_t)0x0006) -#define TIM_DMABase_CCMR2 ((uint16_t)0x0007) -#define TIM_DMABase_CCER ((uint16_t)0x0008) -#define TIM_DMABase_CNT ((uint16_t)0x0009) -#define TIM_DMABase_PSC ((uint16_t)0x000A) -#define TIM_DMABase_ARR ((uint16_t)0x000B) -#define TIM_DMABase_RCR ((uint16_t)0x000C) -#define TIM_DMABase_CCR1 ((uint16_t)0x000D) -#define TIM_DMABase_CCR2 ((uint16_t)0x000E) -#define TIM_DMABase_CCR3 ((uint16_t)0x000F) -#define TIM_DMABase_CCR4 ((uint16_t)0x0010) -#define TIM_DMABase_BDTR ((uint16_t)0x0011) -#define TIM_DMABase_DCR ((uint16_t)0x0012) -#define TIM_DMABase_OR ((uint16_t)0x0013) -#define IS_TIM_DMA_BASE(BASE) (((BASE) == TIM_DMABase_CR1) || \ - ((BASE) == TIM_DMABase_CR2) || \ - ((BASE) == TIM_DMABase_SMCR) || \ - ((BASE) == TIM_DMABase_DIER) || \ - ((BASE) == TIM_DMABase_SR) || \ - ((BASE) == TIM_DMABase_EGR) || \ - ((BASE) == TIM_DMABase_CCMR1) || \ - ((BASE) == TIM_DMABase_CCMR2) || \ - ((BASE) == TIM_DMABase_CCER) || \ - ((BASE) == TIM_DMABase_CNT) || \ - ((BASE) == TIM_DMABase_PSC) || \ - ((BASE) == TIM_DMABase_ARR) || \ - ((BASE) == TIM_DMABase_RCR) || \ - ((BASE) == TIM_DMABase_CCR1) || \ - ((BASE) == TIM_DMABase_CCR2) || \ - ((BASE) == TIM_DMABase_CCR3) || \ - ((BASE) == TIM_DMABase_CCR4) || \ - ((BASE) == TIM_DMABase_BDTR) || \ - ((BASE) == TIM_DMABase_DCR) || \ - ((BASE) == TIM_DMABase_OR)) -/** - * @} - */ - - -/** @defgroup TIM_DMA_Burst_Length - * @{ - */ - -#define TIM_DMABurstLength_1Transfer ((uint16_t)0x0000) -#define TIM_DMABurstLength_2Transfers ((uint16_t)0x0100) -#define TIM_DMABurstLength_3Transfers ((uint16_t)0x0200) -#define TIM_DMABurstLength_4Transfers ((uint16_t)0x0300) -#define TIM_DMABurstLength_5Transfers ((uint16_t)0x0400) -#define TIM_DMABurstLength_6Transfers ((uint16_t)0x0500) -#define TIM_DMABurstLength_7Transfers ((uint16_t)0x0600) -#define TIM_DMABurstLength_8Transfers ((uint16_t)0x0700) -#define TIM_DMABurstLength_9Transfers ((uint16_t)0x0800) -#define TIM_DMABurstLength_10Transfers ((uint16_t)0x0900) -#define TIM_DMABurstLength_11Transfers ((uint16_t)0x0A00) -#define TIM_DMABurstLength_12Transfers ((uint16_t)0x0B00) -#define TIM_DMABurstLength_13Transfers ((uint16_t)0x0C00) -#define TIM_DMABurstLength_14Transfers ((uint16_t)0x0D00) -#define TIM_DMABurstLength_15Transfers ((uint16_t)0x0E00) -#define TIM_DMABurstLength_16Transfers ((uint16_t)0x0F00) -#define TIM_DMABurstLength_17Transfers ((uint16_t)0x1000) -#define TIM_DMABurstLength_18Transfers ((uint16_t)0x1100) -#define IS_TIM_DMA_LENGTH(LENGTH) (((LENGTH) == TIM_DMABurstLength_1Transfer) || \ - ((LENGTH) == TIM_DMABurstLength_2Transfers) || \ - ((LENGTH) == TIM_DMABurstLength_3Transfers) || \ - ((LENGTH) == TIM_DMABurstLength_4Transfers) || \ - ((LENGTH) == TIM_DMABurstLength_5Transfers) || \ - ((LENGTH) == TIM_DMABurstLength_6Transfers) || \ - ((LENGTH) == TIM_DMABurstLength_7Transfers) || \ - ((LENGTH) == TIM_DMABurstLength_8Transfers) || \ - ((LENGTH) == TIM_DMABurstLength_9Transfers) || \ - ((LENGTH) == TIM_DMABurstLength_10Transfers) || \ - ((LENGTH) == TIM_DMABurstLength_11Transfers) || \ - ((LENGTH) == TIM_DMABurstLength_12Transfers) || \ - ((LENGTH) == TIM_DMABurstLength_13Transfers) || \ - ((LENGTH) == TIM_DMABurstLength_14Transfers) || \ - ((LENGTH) == TIM_DMABurstLength_15Transfers) || \ - ((LENGTH) == TIM_DMABurstLength_16Transfers) || \ - ((LENGTH) == TIM_DMABurstLength_17Transfers) || \ - ((LENGTH) == TIM_DMABurstLength_18Transfers)) -/** - * @} - */ - -/** @defgroup TIM_DMA_sources - * @{ - */ - -#define TIM_DMA_Update ((uint16_t)0x0100) -#define TIM_DMA_CC1 ((uint16_t)0x0200) -#define TIM_DMA_CC2 ((uint16_t)0x0400) -#define TIM_DMA_CC3 ((uint16_t)0x0800) -#define TIM_DMA_CC4 ((uint16_t)0x1000) -#define TIM_DMA_COM ((uint16_t)0x2000) -#define TIM_DMA_Trigger ((uint16_t)0x4000) -#define IS_TIM_DMA_SOURCE(SOURCE) ((((SOURCE) & (uint16_t)0x80FF) == 0x0000) && ((SOURCE) != 0x0000)) - -/** - * @} - */ - -/** @defgroup TIM_External_Trigger_Prescaler - * @{ - */ - -#define TIM_ExtTRGPSC_OFF ((uint16_t)0x0000) -#define TIM_ExtTRGPSC_DIV2 ((uint16_t)0x1000) -#define TIM_ExtTRGPSC_DIV4 ((uint16_t)0x2000) -#define TIM_ExtTRGPSC_DIV8 ((uint16_t)0x3000) -#define IS_TIM_EXT_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ExtTRGPSC_OFF) || \ - ((PRESCALER) == TIM_ExtTRGPSC_DIV2) || \ - ((PRESCALER) == TIM_ExtTRGPSC_DIV4) || \ - ((PRESCALER) == TIM_ExtTRGPSC_DIV8)) -/** - * @} - */ - -/** @defgroup TIM_Internal_Trigger_Selection - * @{ - */ - -#define TIM_TS_ITR0 ((uint16_t)0x0000) -#define TIM_TS_ITR1 ((uint16_t)0x0010) -#define TIM_TS_ITR2 ((uint16_t)0x0020) -#define TIM_TS_ITR3 ((uint16_t)0x0030) -#define TIM_TS_TI1F_ED ((uint16_t)0x0040) -#define TIM_TS_TI1FP1 ((uint16_t)0x0050) -#define TIM_TS_TI2FP2 ((uint16_t)0x0060) -#define TIM_TS_ETRF ((uint16_t)0x0070) -#define IS_TIM_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \ - ((SELECTION) == TIM_TS_ITR1) || \ - ((SELECTION) == TIM_TS_ITR2) || \ - ((SELECTION) == TIM_TS_ITR3) || \ - ((SELECTION) == TIM_TS_TI1F_ED) || \ - ((SELECTION) == TIM_TS_TI1FP1) || \ - ((SELECTION) == TIM_TS_TI2FP2) || \ - ((SELECTION) == TIM_TS_ETRF)) -#define IS_TIM_INTERNAL_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \ - ((SELECTION) == TIM_TS_ITR1) || \ - ((SELECTION) == TIM_TS_ITR2) || \ - ((SELECTION) == TIM_TS_ITR3)) -/** - * @} - */ - -/** @defgroup TIM_TIx_External_Clock_Source - * @{ - */ - -#define TIM_TIxExternalCLK1Source_TI1 ((uint16_t)0x0050) -#define TIM_TIxExternalCLK1Source_TI2 ((uint16_t)0x0060) -#define TIM_TIxExternalCLK1Source_TI1ED ((uint16_t)0x0040) - -/** - * @} - */ - -/** @defgroup TIM_External_Trigger_Polarity - * @{ - */ -#define TIM_ExtTRGPolarity_Inverted ((uint16_t)0x8000) -#define TIM_ExtTRGPolarity_NonInverted ((uint16_t)0x0000) -#define IS_TIM_EXT_POLARITY(POLARITY) (((POLARITY) == TIM_ExtTRGPolarity_Inverted) || \ - ((POLARITY) == TIM_ExtTRGPolarity_NonInverted)) -/** - * @} - */ - -/** @defgroup TIM_Prescaler_Reload_Mode - * @{ - */ - -#define TIM_PSCReloadMode_Update ((uint16_t)0x0000) -#define TIM_PSCReloadMode_Immediate ((uint16_t)0x0001) -#define IS_TIM_PRESCALER_RELOAD(RELOAD) (((RELOAD) == TIM_PSCReloadMode_Update) || \ - ((RELOAD) == TIM_PSCReloadMode_Immediate)) -/** - * @} - */ - -/** @defgroup TIM_Forced_Action - * @{ - */ - -#define TIM_ForcedAction_Active ((uint16_t)0x0050) -#define TIM_ForcedAction_InActive ((uint16_t)0x0040) -#define IS_TIM_FORCED_ACTION(ACTION) (((ACTION) == TIM_ForcedAction_Active) || \ - ((ACTION) == TIM_ForcedAction_InActive)) -/** - * @} - */ - -/** @defgroup TIM_Encoder_Mode - * @{ - */ - -#define TIM_EncoderMode_TI1 ((uint16_t)0x0001) -#define TIM_EncoderMode_TI2 ((uint16_t)0x0002) -#define TIM_EncoderMode_TI12 ((uint16_t)0x0003) -#define IS_TIM_ENCODER_MODE(MODE) (((MODE) == TIM_EncoderMode_TI1) || \ - ((MODE) == TIM_EncoderMode_TI2) || \ - ((MODE) == TIM_EncoderMode_TI12)) -/** - * @} - */ - - -/** @defgroup TIM_Event_Source - * @{ - */ - -#define TIM_EventSource_Update ((uint16_t)0x0001) -#define TIM_EventSource_CC1 ((uint16_t)0x0002) -#define TIM_EventSource_CC2 ((uint16_t)0x0004) -#define TIM_EventSource_CC3 ((uint16_t)0x0008) -#define TIM_EventSource_CC4 ((uint16_t)0x0010) -#define TIM_EventSource_COM ((uint16_t)0x0020) -#define TIM_EventSource_Trigger ((uint16_t)0x0040) -#define TIM_EventSource_Break ((uint16_t)0x0080) -#define IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & (uint16_t)0xFF00) == 0x0000) && ((SOURCE) != 0x0000)) - -/** - * @} - */ - -/** @defgroup TIM_Update_Source - * @{ - */ - -#define TIM_UpdateSource_Global ((uint16_t)0x0000) /*!< Source of update is the counter overflow/underflow - or the setting of UG bit, or an update generation - through the slave mode controller. */ -#define TIM_UpdateSource_Regular ((uint16_t)0x0001) /*!< Source of update is counter overflow/underflow. */ -#define IS_TIM_UPDATE_SOURCE(SOURCE) (((SOURCE) == TIM_UpdateSource_Global) || \ - ((SOURCE) == TIM_UpdateSource_Regular)) -/** - * @} - */ - -/** @defgroup TIM_Output_Compare_Preload_State - * @{ - */ - -#define TIM_OCPreload_Enable ((uint16_t)0x0008) -#define TIM_OCPreload_Disable ((uint16_t)0x0000) -#define IS_TIM_OCPRELOAD_STATE(STATE) (((STATE) == TIM_OCPreload_Enable) || \ - ((STATE) == TIM_OCPreload_Disable)) -/** - * @} - */ - -/** @defgroup TIM_Output_Compare_Fast_State - * @{ - */ - -#define TIM_OCFast_Enable ((uint16_t)0x0004) -#define TIM_OCFast_Disable ((uint16_t)0x0000) -#define IS_TIM_OCFAST_STATE(STATE) (((STATE) == TIM_OCFast_Enable) || \ - ((STATE) == TIM_OCFast_Disable)) - -/** - * @} - */ - -/** @defgroup TIM_Output_Compare_Clear_State - * @{ - */ - -#define TIM_OCClear_Enable ((uint16_t)0x0080) -#define TIM_OCClear_Disable ((uint16_t)0x0000) -#define IS_TIM_OCCLEAR_STATE(STATE) (((STATE) == TIM_OCClear_Enable) || \ - ((STATE) == TIM_OCClear_Disable)) -/** - * @} - */ - -/** @defgroup TIM_Trigger_Output_Source - * @{ - */ - -#define TIM_TRGOSource_Reset ((uint16_t)0x0000) -#define TIM_TRGOSource_Enable ((uint16_t)0x0010) -#define TIM_TRGOSource_Update ((uint16_t)0x0020) -#define TIM_TRGOSource_OC1 ((uint16_t)0x0030) -#define TIM_TRGOSource_OC1Ref ((uint16_t)0x0040) -#define TIM_TRGOSource_OC2Ref ((uint16_t)0x0050) -#define TIM_TRGOSource_OC3Ref ((uint16_t)0x0060) -#define TIM_TRGOSource_OC4Ref ((uint16_t)0x0070) -#define IS_TIM_TRGO_SOURCE(SOURCE) (((SOURCE) == TIM_TRGOSource_Reset) || \ - ((SOURCE) == TIM_TRGOSource_Enable) || \ - ((SOURCE) == TIM_TRGOSource_Update) || \ - ((SOURCE) == TIM_TRGOSource_OC1) || \ - ((SOURCE) == TIM_TRGOSource_OC1Ref) || \ - ((SOURCE) == TIM_TRGOSource_OC2Ref) || \ - ((SOURCE) == TIM_TRGOSource_OC3Ref) || \ - ((SOURCE) == TIM_TRGOSource_OC4Ref)) -/** - * @} - */ - -/** @defgroup TIM_Slave_Mode - * @{ - */ - -#define TIM_SlaveMode_Reset ((uint16_t)0x0004) -#define TIM_SlaveMode_Gated ((uint16_t)0x0005) -#define TIM_SlaveMode_Trigger ((uint16_t)0x0006) -#define TIM_SlaveMode_External1 ((uint16_t)0x0007) -#define IS_TIM_SLAVE_MODE(MODE) (((MODE) == TIM_SlaveMode_Reset) || \ - ((MODE) == TIM_SlaveMode_Gated) || \ - ((MODE) == TIM_SlaveMode_Trigger) || \ - ((MODE) == TIM_SlaveMode_External1)) -/** - * @} - */ - -/** @defgroup TIM_Master_Slave_Mode - * @{ - */ - -#define TIM_MasterSlaveMode_Enable ((uint16_t)0x0080) -#define TIM_MasterSlaveMode_Disable ((uint16_t)0x0000) -#define IS_TIM_MSM_STATE(STATE) (((STATE) == TIM_MasterSlaveMode_Enable) || \ - ((STATE) == TIM_MasterSlaveMode_Disable)) -/** - * @} - */ - -/** @defgroup TIM_Flags - * @{ - */ - -#define TIM_FLAG_Update ((uint16_t)0x0001) -#define TIM_FLAG_CC1 ((uint16_t)0x0002) -#define TIM_FLAG_CC2 ((uint16_t)0x0004) -#define TIM_FLAG_CC3 ((uint16_t)0x0008) -#define TIM_FLAG_CC4 ((uint16_t)0x0010) -#define TIM_FLAG_COM ((uint16_t)0x0020) -#define TIM_FLAG_Trigger ((uint16_t)0x0040) -#define TIM_FLAG_Break ((uint16_t)0x0080) -#define TIM_FLAG_CC1OF ((uint16_t)0x0200) -#define TIM_FLAG_CC2OF ((uint16_t)0x0400) -#define TIM_FLAG_CC3OF ((uint16_t)0x0800) -#define TIM_FLAG_CC4OF ((uint16_t)0x1000) -#define IS_TIM_GET_FLAG(FLAG) (((FLAG) == TIM_FLAG_Update) || \ - ((FLAG) == TIM_FLAG_CC1) || \ - ((FLAG) == TIM_FLAG_CC2) || \ - ((FLAG) == TIM_FLAG_CC3) || \ - ((FLAG) == TIM_FLAG_CC4) || \ - ((FLAG) == TIM_FLAG_COM) || \ - ((FLAG) == TIM_FLAG_Trigger) || \ - ((FLAG) == TIM_FLAG_Break) || \ - ((FLAG) == TIM_FLAG_CC1OF) || \ - ((FLAG) == TIM_FLAG_CC2OF) || \ - ((FLAG) == TIM_FLAG_CC3OF) || \ - ((FLAG) == TIM_FLAG_CC4OF)) - - -#define IS_TIM_CLEAR_FLAG(TIM_FLAG) ((((TIM_FLAG) & (uint16_t)0xE100) == 0x0000) && ((TIM_FLAG) != 0x0000)) -/** - * @} - */ - - -/** @defgroup TIM_Input_Capture_Filer_Value - * @{ - */ - -#define IS_TIM_IC_FILTER(ICFILTER) ((ICFILTER) <= 0xF) -/** - * @} - */ - -/** @defgroup TIM_External_Trigger_Filter - * @{ - */ - -#define IS_TIM_EXT_FILTER(EXTFILTER) ((EXTFILTER) <= 0xF) -/** - * @} - */ - -/** @defgroup TIM_OCReferenceClear - * @{ - */ -#define TIM_OCReferenceClear_ETRF ((uint16_t)0x0008) -#define TIM_OCReferenceClear_OCREFCLR ((uint16_t)0x0000) -#define TIM_OCREFERENCECECLEAR_SOURCE(SOURCE) (((SOURCE) == TIM_OCReferenceClear_ETRF) || \ - ((SOURCE) == TIM_OCReferenceClear_OCREFCLR)) - -/** - * @} - */ -/** @defgroup TIM_Remap - * @{ - */ -#define TIM14_GPIO ((uint16_t)0x0000) -#define TIM14_RTC_CLK ((uint16_t)0x0001) -#define TIM14_HSEDiv32 ((uint16_t)0x0002) -#define TIM14_MCO ((uint16_t)0x0003) - -#define IS_TIM_REMAP(TIM_REMAP) (((TIM_REMAP) == TIM14_GPIO)|| \ - ((TIM_REMAP) == TIM14_RTC_CLK) || \ - ((TIM_REMAP) == TIM14_HSEDiv32) || \ - ((TIM_REMAP) == TIM14_MCO)) -/** - * @} - */ - -/** @defgroup TIM_Legacy - * @{ - */ - -#define TIM_DMABurstLength_1Byte TIM_DMABurstLength_1Transfer -#define TIM_DMABurstLength_2Bytes TIM_DMABurstLength_2Transfers -#define TIM_DMABurstLength_3Bytes TIM_DMABurstLength_3Transfers -#define TIM_DMABurstLength_4Bytes TIM_DMABurstLength_4Transfers -#define TIM_DMABurstLength_5Bytes TIM_DMABurstLength_5Transfers -#define TIM_DMABurstLength_6Bytes TIM_DMABurstLength_6Transfers -#define TIM_DMABurstLength_7Bytes TIM_DMABurstLength_7Transfers -#define TIM_DMABurstLength_8Bytes TIM_DMABurstLength_8Transfers -#define TIM_DMABurstLength_9Bytes TIM_DMABurstLength_9Transfers -#define TIM_DMABurstLength_10Bytes TIM_DMABurstLength_10Transfers -#define TIM_DMABurstLength_11Bytes TIM_DMABurstLength_11Transfers -#define TIM_DMABurstLength_12Bytes TIM_DMABurstLength_12Transfers -#define TIM_DMABurstLength_13Bytes TIM_DMABurstLength_13Transfers -#define TIM_DMABurstLength_14Bytes TIM_DMABurstLength_14Transfers -#define TIM_DMABurstLength_15Bytes TIM_DMABurstLength_15Transfers -#define TIM_DMABurstLength_16Bytes TIM_DMABurstLength_16Transfers -#define TIM_DMABurstLength_17Bytes TIM_DMABurstLength_17Transfers -#define TIM_DMABurstLength_18Bytes TIM_DMABurstLength_18Transfers -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions ------------------------------------------------------- */ - -/* TimeBase management ********************************************************/ -void TIM_DeInit(TIM_TypeDef* TIMx); -void TIM_TimeBaseInit(TIM_TypeDef* TIMx, TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct); -void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct); -void TIM_PrescalerConfig(TIM_TypeDef* TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode); -void TIM_CounterModeConfig(TIM_TypeDef* TIMx, uint16_t TIM_CounterMode); -void TIM_SetCounter(TIM_TypeDef* TIMx, uint32_t Counter); -void TIM_SetAutoreload(TIM_TypeDef* TIMx, uint32_t Autoreload); -uint32_t TIM_GetCounter(TIM_TypeDef* TIMx); -uint16_t TIM_GetPrescaler(TIM_TypeDef* TIMx); -void TIM_UpdateDisableConfig(TIM_TypeDef* TIMx, FunctionalState NewState); -void TIM_UpdateRequestConfig(TIM_TypeDef* TIMx, uint16_t TIM_UpdateSource); -void TIM_ARRPreloadConfig(TIM_TypeDef* TIMx, FunctionalState NewState); -void TIM_SelectOnePulseMode(TIM_TypeDef* TIMx, uint16_t TIM_OPMode); -void TIM_SetClockDivision(TIM_TypeDef* TIMx, uint16_t TIM_CKD); -void TIM_Cmd(TIM_TypeDef* TIMx, FunctionalState NewState); - -/* Advanced-control timers (TIM1) specific features*******************/ -void TIM_BDTRConfig(TIM_TypeDef* TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct); -void TIM_BDTRStructInit(TIM_BDTRInitTypeDef* TIM_BDTRInitStruct); -void TIM_CtrlPWMOutputs(TIM_TypeDef* TIMx, FunctionalState NewState); - -/* Output Compare management **************************************************/ -void TIM_OC1Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct); -void TIM_OC2Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct); -void TIM_OC3Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct); -void TIM_OC4Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct); -void TIM_OCStructInit(TIM_OCInitTypeDef* TIM_OCInitStruct); -void TIM_SelectOCxM(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode); -void TIM_SetCompare1(TIM_TypeDef* TIMx, uint32_t Compare1); -void TIM_SetCompare2(TIM_TypeDef* TIMx, uint32_t Compare2); -void TIM_SetCompare3(TIM_TypeDef* TIMx, uint32_t Compare3); -void TIM_SetCompare4(TIM_TypeDef* TIMx, uint32_t Compare4); -void TIM_ForcedOC1Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction); -void TIM_ForcedOC2Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction); -void TIM_ForcedOC3Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction); -void TIM_ForcedOC4Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction); -void TIM_CCPreloadControl(TIM_TypeDef* TIMx, FunctionalState NewState); -void TIM_OC1PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload); -void TIM_OC2PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload); -void TIM_OC3PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload); -void TIM_OC4PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload); -void TIM_OC1FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast); -void TIM_OC2FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast); -void TIM_OC3FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast); -void TIM_OC4FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast); -void TIM_ClearOC1Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear); -void TIM_ClearOC2Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear); -void TIM_ClearOC3Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear); -void TIM_ClearOC4Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear); -void TIM_OC1PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity); -void TIM_OC1NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity); -void TIM_OC2PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity); -void TIM_OC2NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity); -void TIM_OC3PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity); -void TIM_OC3NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity); -void TIM_OC4PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity); -void TIM_SelectOCREFClear(TIM_TypeDef* TIMx, uint16_t TIM_OCReferenceClear); -void TIM_CCxCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx); -void TIM_CCxNCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN); -void TIM_SelectCOM(TIM_TypeDef* TIMx, FunctionalState NewState); - -/* Input Capture management ***************************************************/ -void TIM_ICInit(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct); -void TIM_ICStructInit(TIM_ICInitTypeDef* TIM_ICInitStruct); -void TIM_PWMIConfig(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct); -uint32_t TIM_GetCapture1(TIM_TypeDef* TIMx); -uint32_t TIM_GetCapture2(TIM_TypeDef* TIMx); -uint32_t TIM_GetCapture3(TIM_TypeDef* TIMx); -uint32_t TIM_GetCapture4(TIM_TypeDef* TIMx); -void TIM_SetIC1Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC); -void TIM_SetIC2Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC); -void TIM_SetIC3Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC); -void TIM_SetIC4Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC); - -/* Interrupts, DMA and flags management ***************************************/ -void TIM_ITConfig(TIM_TypeDef* TIMx, uint16_t TIM_IT, FunctionalState NewState); -void TIM_GenerateEvent(TIM_TypeDef* TIMx, uint16_t TIM_EventSource); -FlagStatus TIM_GetFlagStatus(TIM_TypeDef* TIMx, uint16_t TIM_FLAG); -void TIM_ClearFlag(TIM_TypeDef* TIMx, uint16_t TIM_FLAG); -ITStatus TIM_GetITStatus(TIM_TypeDef* TIMx, uint16_t TIM_IT); -void TIM_ClearITPendingBit(TIM_TypeDef* TIMx, uint16_t TIM_IT); -void TIM_DMAConfig(TIM_TypeDef* TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength); -void TIM_DMACmd(TIM_TypeDef* TIMx, uint16_t TIM_DMASource, FunctionalState NewState); -void TIM_SelectCCDMA(TIM_TypeDef* TIMx, FunctionalState NewState); - -/* Clocks management **********************************************************/ -void TIM_InternalClockConfig(TIM_TypeDef* TIMx); -void TIM_ITRxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource); -void TIM_TIxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_TIxExternalCLKSource, - uint16_t TIM_ICPolarity, uint16_t ICFilter); -void TIM_ETRClockMode1Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, - uint16_t ExtTRGFilter); -void TIM_ETRClockMode2Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, - uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter); - - -/* Synchronization management *************************************************/ -void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource); -void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_TRGOSource); -void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode); -void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_MasterSlaveMode); -void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, - uint16_t ExtTRGFilter); - -/* Specific interface management **********************************************/ -void TIM_EncoderInterfaceConfig(TIM_TypeDef* TIMx, uint16_t TIM_EncoderMode, - uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity); -void TIM_SelectHallSensor(TIM_TypeDef* TIMx, FunctionalState NewState); - -/* Specific remapping management **********************************************/ -void TIM_RemapConfig(TIM_TypeDef* TIMx, uint16_t TIM_Remap); - - -#ifdef __cplusplus -} -#endif - -#endif /*__FT32F0XX_TIM_H */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT FMD *****END OF FILE****/ diff --git a/bsp/ft32/libraries/FT32F0xx/FT32F0xx_Driver/Inc/ft32f0xx_usart.h b/bsp/ft32/libraries/FT32F0xx/FT32F0xx_Driver/Inc/ft32f0xx_usart.h deleted file mode 100644 index 3cc5f4e9b7b..00000000000 --- a/bsp/ft32/libraries/FT32F0xx/FT32F0xx_Driver/Inc/ft32f0xx_usart.h +++ /dev/null @@ -1,539 +0,0 @@ -/** - ****************************************************************************** - * @file ft32f0xx_usart.h - * @author FMD AE - * @brief This file contains all the functions prototypes for the USART - * firmware library. - * @version V1.0.0 - * @data 2021-07-01 - ****************************************************************************** - */ - - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __FT32F0XX_USART_H -#define __FT32F0XX_USART_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "ft32f0xx.h" - - -/** @addtogroup USART - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ - - - -/** - * @brief USART Init Structure definition - */ - -typedef struct -{ - uint32_t USART_BaudRate; /*!< This member configures the USART communication baud rate. - The baud rate is computed using the following formula: - - IntegerDivider = ((PCLKx) / (16 * (USART_InitStruct->USART_BaudRate))) - - FractionalDivider = ((IntegerDivider - ((uint32_t) IntegerDivider)) * 16) + 0.5 */ - - uint32_t USART_WordLength; /*!< Specifies the number of data bits transmitted or received in a frame. - This parameter can be a value of @ref USART_Word_Length */ - - uint32_t USART_StopBits; /*!< Specifies the number of stop bits transmitted. - This parameter can be a value of @ref USART_Stop_Bits */ - - uint32_t USART_Parity; /*!< Specifies the parity mode. - This parameter can be a value of @ref USART_Parity - @note When parity is enabled, the computed parity is inserted - at the MSB position of the transmitted data (9th bit when - the word length is set to 9 data bits; 8th bit when the - word length is set to 8 data bits). */ - - uint32_t USART_Mode; /*!< Specifies wether the Receive or Transmit mode is enabled or disabled. - This parameter can be a value of @ref USART_Mode */ - - uint32_t USART_HardwareFlowControl; /*!< Specifies wether the hardware flow control mode is enabled - or disabled. - This parameter can be a value of @ref USART_Hardware_Flow_Control*/ -} USART_InitTypeDef; - -/** - * @brief USART Clock Init Structure definition - */ - -typedef struct -{ - uint32_t USART_Clock; /*!< Specifies whether the USART clock is enabled or disabled. - This parameter can be a value of @ref USART_Clock */ - - uint32_t USART_CPOL; /*!< Specifies the steady state of the serial clock. - This parameter can be a value of @ref USART_Clock_Polarity */ - - uint32_t USART_CPHA; /*!< Specifies the clock transition on which the bit capture is made. - This parameter can be a value of @ref USART_Clock_Phase */ - - uint32_t USART_LastBit; /*!< Specifies whether the clock pulse corresponding to the last transmitted - data bit (MSB) has to be output on the SCLK pin in synchronous mode. - This parameter can be a value of @ref USART_Last_Bit */ -} USART_ClockInitTypeDef; - -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup USART_Exported_Constants - * @{ - */ - -#define IS_USART_ALL_PERIPH(PERIPH) (((PERIPH) == USART1) || \ - ((PERIPH) == USART2)) - -#define IS_USART_123_PERIPH(PERIPH) (((PERIPH) == USART1) || \ - ((PERIPH) == USART2) || \ - ((PERIPH) == USART3)) - -/** @defgroup USART_Word_Length - * @{ - */ - -#define USART_WordLength_8b ((uint32_t)0x00000000) -#define USART_WordLength_9b USART_CR1_M /* should be ((uint32_t)0x00001000) */ -#define USART_WordLength_7b ((uint32_t)0x10001000) -#define IS_USART_WORD_LENGTH(LENGTH) (((LENGTH) == USART_WordLength_8b) || \ - ((LENGTH) == USART_WordLength_9b) || \ - ((LENGTH) == USART_WordLength_7b)) -/** - * @} - */ - -/** @defgroup USART_Stop_Bits - * @{ - */ - -#define USART_StopBits_1 ((uint32_t)0x00000000) -#define USART_StopBits_2 USART_CR2_STOP_1 -#define USART_StopBits_1_5 (USART_CR2_STOP_0 | USART_CR2_STOP_1) -#define IS_USART_STOPBITS(STOPBITS) (((STOPBITS) == USART_StopBits_1) || \ - ((STOPBITS) == USART_StopBits_2) || \ - ((STOPBITS) == USART_StopBits_1_5)) -/** - * @} - */ - -/** @defgroup USART_Parity - * @{ - */ - -#define USART_Parity_No ((uint32_t)0x00000000) -#define USART_Parity_Even USART_CR1_PCE -#define USART_Parity_Odd (USART_CR1_PCE | USART_CR1_PS) -#define IS_USART_PARITY(PARITY) (((PARITY) == USART_Parity_No) || \ - ((PARITY) == USART_Parity_Even) || \ - ((PARITY) == USART_Parity_Odd)) -/** - * @} - */ - -/** @defgroup USART_Mode - * @{ - */ - -#define USART_Mode_Rx USART_CR1_RE -#define USART_Mode_Tx USART_CR1_TE -#define IS_USART_MODE(MODE) ((((MODE) & (uint32_t)0xFFFFFFF3) == 0x00) && \ - ((MODE) != (uint32_t)0x00)) -/** - * @} - */ - -/** @defgroup USART_Hardware_Flow_Control - * @{ - */ - -#define USART_HardwareFlowControl_None ((uint32_t)0x00000000) -#define USART_HardwareFlowControl_RTS USART_CR3_RTSE -#define USART_HardwareFlowControl_CTS USART_CR3_CTSE -#define USART_HardwareFlowControl_RTS_CTS (USART_CR3_RTSE | USART_CR3_CTSE) -#define IS_USART_HARDWARE_FLOW_CONTROL(CONTROL)\ - (((CONTROL) == USART_HardwareFlowControl_None) || \ - ((CONTROL) == USART_HardwareFlowControl_RTS) || \ - ((CONTROL) == USART_HardwareFlowControl_CTS) || \ - ((CONTROL) == USART_HardwareFlowControl_RTS_CTS)) -/** - * @} - */ - -/** @defgroup USART_Clock - * @{ - */ - -#define USART_Clock_Disable ((uint32_t)0x00000000) -#define USART_Clock_Enable USART_CR2_CLKEN -#define IS_USART_CLOCK(CLOCK) (((CLOCK) == USART_Clock_Disable) || \ - ((CLOCK) == USART_Clock_Enable)) -/** - * @} - */ - -/** @defgroup USART_Clock_Polarity - * @{ - */ - -#define USART_CPOL_Low ((uint32_t)0x00000000) -#define USART_CPOL_High USART_CR2_CPOL -#define IS_USART_CPOL(CPOL) (((CPOL) == USART_CPOL_Low) || ((CPOL) == USART_CPOL_High)) - -/** - * @} - */ - -/** @defgroup USART_Clock_Phase - * @{ - */ - -#define USART_CPHA_1Edge ((uint32_t)0x00000000) -#define USART_CPHA_2Edge USART_CR2_CPHA -#define IS_USART_CPHA(CPHA) (((CPHA) == USART_CPHA_1Edge) || ((CPHA) == USART_CPHA_2Edge)) - -/** - * @} - */ - -/** @defgroup USART_Last_Bit - * @{ - */ - -#define USART_LastBit_Disable ((uint32_t)0x00000000) -#define USART_LastBit_Enable USART_CR2_LBCL -#define IS_USART_LASTBIT(LASTBIT) (((LASTBIT) == USART_LastBit_Disable) || \ - ((LASTBIT) == USART_LastBit_Enable)) -/** - * @} - */ - -/** @defgroup USART_DMA_Requests - * @{ - */ - -#define USART_DMAReq_Tx USART_CR3_DMAT -#define USART_DMAReq_Rx USART_CR3_DMAR -#define IS_USART_DMAREQ(DMAREQ) ((((DMAREQ) & (uint32_t)0xFFFFFF3F) == 0x00) && \ - ((DMAREQ) != (uint32_t)0x00)) - -/** - * @} - */ - -/** @defgroup USART_DMA_Recception_Error - * @{ - */ - -#define USART_DMAOnError_Enable ((uint32_t)0x00000000) -#define USART_DMAOnError_Disable USART_CR3_DDRE -#define IS_USART_DMAONERROR(DMAERROR) (((DMAERROR) == USART_DMAOnError_Disable)|| \ - ((DMAERROR) == USART_DMAOnError_Enable)) -/** - * @} - */ - -/** @defgroup USART_MuteMode_WakeUp_methods - * @{ - */ - -#define USART_WakeUp_IdleLine ((uint32_t)0x00000000) -#define USART_WakeUp_AddressMark USART_CR1_WAKE -#define IS_USART_MUTEMODE_WAKEUP(WAKEUP) (((WAKEUP) == USART_WakeUp_IdleLine) || \ - ((WAKEUP) == USART_WakeUp_AddressMark)) -/** - * @} - */ - -/** @defgroup USART_Address_Detection - * @{ - */ - -#define USART_AddressLength_4b ((uint32_t)0x00000000) -#define USART_AddressLength_7b USART_CR2_ADDM7 -#define IS_USART_ADDRESS_DETECTION(ADDRESS) (((ADDRESS) == USART_AddressLength_4b) || \ - ((ADDRESS) == USART_AddressLength_7b)) -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** @defgroup USART_IrDA_Low_Power - * @{ - */ - -#define USART_IrDAMode_LowPower USART_CR3_IRLP -#define USART_IrDAMode_Normal ((uint32_t)0x00000000) -#define IS_USART_IRDA_MODE(MODE) (((MODE) == USART_IrDAMode_LowPower) || \ - ((MODE) == USART_IrDAMode_Normal)) -/** - * @} - */ - -/** @defgroup USART_DE_Polarity - * @{ - */ - -#define USART_DEPolarity_High ((uint32_t)0x00000000) -#define USART_DEPolarity_Low USART_CR3_DEP -#define IS_USART_DE_POLARITY(POLARITY) (((POLARITY) == USART_DEPolarity_Low) || \ - ((POLARITY) == USART_DEPolarity_High)) -/** - * @} - */ - -/** @defgroup USART_Inversion_Pins - * @{ - */ - -#define USART_InvPin_Tx USART_CR2_TXINV -#define USART_InvPin_Rx USART_CR2_RXINV -#define IS_USART_INVERSTION_PIN(PIN) ((((PIN) & (uint32_t)0xFFFCFFFF) == 0x00) && \ - ((PIN) != (uint32_t)0x00)) - -/** - * @} - */ - -/** @defgroup USART_AutoBaudRate_Mode - * @{ - */ - -#define USART_AutoBaudRate_StartBit ((uint32_t)0x00000000) -#define USART_AutoBaudRate_FallingEdge USART_CR2_ABRMODE_0 -#define IS_USART_AUTOBAUDRATE_MODE(MODE) (((MODE) == USART_AutoBaudRate_StartBit) || \ - ((MODE) == USART_AutoBaudRate_FallingEdge)) -/** - * @} - */ - -/** @defgroup USART_OVR_DETECTION - * @{ - */ - -#define USART_OVRDetection_Enable ((uint32_t)0x00000000) -#define USART_OVRDetection_Disable USART_CR3_OVRDIS -#define IS_USART_OVRDETECTION(OVR) (((OVR) == USART_OVRDetection_Enable)|| \ - ((OVR) == USART_OVRDetection_Disable)) -/** - * @} - */ -/** @defgroup USART_Request - * @{ - */ - -#define USART_Request_ABRRQ USART_RQR_ABRRQ -#define USART_Request_SBKRQ USART_RQR_SBKRQ -#define USART_Request_MMRQ USART_RQR_MMRQ -#define USART_Request_RXFRQ USART_RQR_RXFRQ -#define USART_Request_TXFRQ USART_RQR_TXFRQ - -#define IS_USART_REQUEST(REQUEST) (((REQUEST) == USART_Request_TXFRQ) || \ - ((REQUEST) == USART_Request_RXFRQ) || \ - ((REQUEST) == USART_Request_MMRQ) || \ - ((REQUEST) == USART_Request_SBKRQ) || \ - ((REQUEST) == USART_Request_ABRRQ)) -/** - * @} - */ - -/** @defgroup USART_Flags - * @{ - */ -#define USART_FLAG_REACK USART_ISR_REACK -#define USART_FLAG_TEACK USART_ISR_TEACK -#define USART_FLAG_WU USART_ISR_WUF -#define USART_FLAG_RWU USART_ISR_RWU -#define USART_FLAG_SBK USART_ISR_SBKF -#define USART_FLAG_CM USART_ISR_CMF -#define USART_FLAG_BUSY USART_ISR_BUSY -#define USART_FLAG_ABRF USART_ISR_ABRF -#define USART_FLAG_ABRE USART_ISR_ABRE -#define USART_FLAG_EOB USART_ISR_EOBF -#define USART_FLAG_RTO USART_ISR_RTOF -#define USART_FLAG_nCTSS USART_ISR_CTS -#define USART_FLAG_CTS USART_ISR_CTSIF -#define USART_FLAG_LBD USART_ISR_LBD -#define USART_FLAG_TXE USART_ISR_TXE -#define USART_FLAG_TC USART_ISR_TC -#define USART_FLAG_RXNE USART_ISR_RXNE -#define USART_FLAG_IDLE USART_ISR_IDLE -#define USART_FLAG_ORE USART_ISR_ORE -#define USART_FLAG_NE USART_ISR_NE -#define USART_FLAG_FE USART_ISR_FE -#define USART_FLAG_PE USART_ISR_PE -#define IS_USART_FLAG(FLAG) (((FLAG) == USART_FLAG_PE) || ((FLAG) == USART_FLAG_TXE) || \ - ((FLAG) == USART_FLAG_TC) || ((FLAG) == USART_FLAG_RXNE) || \ - ((FLAG) == USART_FLAG_IDLE) || ((FLAG) == USART_FLAG_LBD) || \ - ((FLAG) == USART_FLAG_CTS) || ((FLAG) == USART_FLAG_ORE) || \ - ((FLAG) == USART_FLAG_NE) || ((FLAG) == USART_FLAG_FE) || \ - ((FLAG) == USART_FLAG_nCTSS) || ((FLAG) == USART_FLAG_RTO) || \ - ((FLAG) == USART_FLAG_EOB) || ((FLAG) == USART_FLAG_ABRE) || \ - ((FLAG) == USART_FLAG_ABRF) || ((FLAG) == USART_FLAG_BUSY) || \ - ((FLAG) == USART_FLAG_CM) || ((FLAG) == USART_FLAG_SBK) || \ - ((FLAG) == USART_FLAG_RWU) || ((FLAG) == USART_FLAG_WU) || \ - ((FLAG) == USART_FLAG_TEACK)|| ((FLAG) == USART_FLAG_REACK)) - -#define IS_USART_CLEAR_FLAG(FLAG) (((FLAG) == USART_FLAG_WU) || ((FLAG) == USART_FLAG_TC) || \ - ((FLAG) == USART_FLAG_IDLE) || ((FLAG) == USART_FLAG_ORE) || \ - ((FLAG) == USART_FLAG_NE) || ((FLAG) == USART_FLAG_FE) || \ - ((FLAG) == USART_FLAG_LBD) || ((FLAG) == USART_FLAG_CTS) || \ - ((FLAG) == USART_FLAG_RTO) || ((FLAG) == USART_FLAG_EOB) || \ - ((FLAG) == USART_FLAG_CM) || ((FLAG) == USART_FLAG_PE)) -/** - * @} - */ - -/** @defgroup USART_Interrupt_definition - * @brief USART Interrupt definition - * USART_IT possible values - * Elements values convention: 0xZZZZYYXX - * XX: Position of the corresponding Interrupt - * YY: Register index - * ZZZZ: Flag position - * @{ - */ - -#define USART_IT_WU ((uint32_t)0x00140316) -#define USART_IT_CM ((uint32_t)0x0011010E) -#define USART_IT_EOB ((uint32_t)0x000C011B) -#define USART_IT_RTO ((uint32_t)0x000B011A) -#define USART_IT_PE ((uint32_t)0x00000108) -#define USART_IT_TXE ((uint32_t)0x00070107) -#define USART_IT_TC ((uint32_t)0x00060106) -#define USART_IT_RXNE ((uint32_t)0x00050105) -#define USART_IT_IDLE ((uint32_t)0x00040104) -#define USART_IT_LBD ((uint32_t)0x00080206) -#define USART_IT_CTS ((uint32_t)0x0009030A) -#define USART_IT_ERR ((uint32_t)0x00000300) -#define USART_IT_ORE ((uint32_t)0x00030300) -#define USART_IT_NE ((uint32_t)0x00020300) -#define USART_IT_FE ((uint32_t)0x00010300) - -#define IS_USART_CONFIG_IT(IT) (((IT) == USART_IT_PE) || ((IT) == USART_IT_TXE) || \ - ((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \ - ((IT) == USART_IT_IDLE) || ((IT) == USART_IT_LBD) || \ - ((IT) == USART_IT_CTS) || ((IT) == USART_IT_ERR) || \ - ((IT) == USART_IT_RTO) || ((IT) == USART_IT_EOB) || \ - ((IT) == USART_IT_CM) || ((IT) == USART_IT_WU)) - -#define IS_USART_GET_IT(IT) (((IT) == USART_IT_PE) || ((IT) == USART_IT_TXE) || \ - ((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \ - ((IT) == USART_IT_IDLE) || ((IT) == USART_IT_LBD) || \ - ((IT) == USART_IT_CTS) || ((IT) == USART_IT_ORE) || \ - ((IT) == USART_IT_NE) || ((IT) == USART_IT_FE) || \ - ((IT) == USART_IT_RTO) || ((IT) == USART_IT_EOB) || \ - ((IT) == USART_IT_CM) || ((IT) == USART_IT_WU)) - -#define IS_USART_CLEAR_IT(IT) (((IT) == USART_IT_TC) || ((IT) == USART_IT_PE) || \ - ((IT) == USART_IT_FE) || ((IT) == USART_IT_NE) || \ - ((IT) == USART_IT_ORE) || ((IT) == USART_IT_IDLE) || \ - ((IT) == USART_IT_LBD) || ((IT) == USART_IT_CTS) || \ - ((IT) == USART_IT_RTO) || ((IT) == USART_IT_EOB) || \ - ((IT) == USART_IT_CM) || ((IT) == USART_IT_WU)) -/** - * @} - */ - -/** @defgroup USART_Global_definition - * @{ - */ - -#define IS_USART_BAUDRATE(BAUDRATE) (((BAUDRATE) > 0) && ((BAUDRATE) < 0x005B8D81)) -#define IS_USART_DE_ASSERTION_DEASSERTION_TIME(TIME) ((TIME) <= 0x1F) -#define IS_USART_AUTO_RETRY_COUNTER(COUNTER) ((COUNTER) <= 0x7) -#define IS_USART_TIMEOUT(TIMEOUT) ((TIMEOUT) <= 0x00FFFFFF) -#define IS_USART_DATA(DATA) ((DATA) <= 0x1FF) - -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions ------------------------------------------------------- */ - -/* Initialization and Configuration functions *********************************/ -void USART_DeInit(USART_TypeDef* USARTx); -void USART_Init(USART_TypeDef* USARTx, USART_InitTypeDef* USART_InitStruct); -void USART_StructInit(USART_InitTypeDef* USART_InitStruct); -void USART_ClockInit(USART_TypeDef* USARTx, USART_ClockInitTypeDef* USART_ClockInitStruct); -void USART_ClockStructInit(USART_ClockInitTypeDef* USART_ClockInitStruct); -void USART_Cmd(USART_TypeDef* USARTx, FunctionalState NewState); -void USART_DirectionModeCmd(USART_TypeDef* USARTx, uint32_t USART_DirectionMode, FunctionalState NewState); -void USART_OverSampling8Cmd(USART_TypeDef* USARTx, FunctionalState NewState); -void USART_OneBitMethodCmd(USART_TypeDef* USARTx, FunctionalState NewState); -void USART_MSBFirstCmd(USART_TypeDef* USARTx, FunctionalState NewState); -void USART_DataInvCmd(USART_TypeDef* USARTx, FunctionalState NewState); -void USART_InvPinCmd(USART_TypeDef* USARTx, uint32_t USART_InvPin, FunctionalState NewState); -void USART_SWAPPinCmd(USART_TypeDef* USARTx, FunctionalState NewState); -void USART_ReceiverTimeOutCmd(USART_TypeDef* USARTx, FunctionalState NewState); -void USART_SetReceiverTimeOut(USART_TypeDef* USARTx, uint32_t USART_ReceiverTimeOut); - -/* AutoBaudRate functions *****************************************************/ -void USART_AutoBaudRateCmd(USART_TypeDef* USARTx, FunctionalState NewState); -void USART_AutoBaudRateConfig(USART_TypeDef* USARTx, uint32_t USART_AutoBaudRate); - -/* Data transfers functions ***************************************************/ -void USART_SendData(USART_TypeDef* USARTx, uint16_t Data); -uint16_t USART_ReceiveData(USART_TypeDef* USARTx); - -/* Multi-Processor Communication functions ************************************/ -void USART_SetAddress(USART_TypeDef* USARTx, uint8_t USART_Address); -void USART_MuteModeWakeUpConfig(USART_TypeDef* USARTx, uint32_t USART_WakeUp); -void USART_MuteModeCmd(USART_TypeDef* USARTx, FunctionalState NewState); -void USART_AddressDetectionConfig(USART_TypeDef* USARTx, uint32_t USART_AddressLength); - -/* Half-duplex mode function **************************************************/ -void USART_HalfDuplexCmd(USART_TypeDef* USARTx, FunctionalState NewState); - -/* RS485 mode functions *******************************************************/ -void USART_DECmd(USART_TypeDef* USARTx, FunctionalState NewState); -void USART_DEPolarityConfig(USART_TypeDef* USARTx, uint32_t USART_DEPolarity); -void USART_SetDEAssertionTime(USART_TypeDef* USARTx, uint32_t USART_DEAssertionTime); -void USART_SetDEDeassertionTime(USART_TypeDef* USARTx, uint32_t USART_DEDeassertionTime); - -/* DMA transfers management functions *****************************************/ -void USART_DMACmd(USART_TypeDef* USARTx, uint32_t USART_DMAReq, FunctionalState NewState); -void USART_DMAReceptionErrorConfig(USART_TypeDef* USARTx, uint32_t USART_DMAOnError); - -/* Interrupts and flags management functions **********************************/ -void USART_ITConfig(USART_TypeDef* USARTx, uint32_t USART_IT, FunctionalState NewState); -void USART_RequestCmd(USART_TypeDef* USARTx, uint32_t USART_Request, FunctionalState NewState); -void USART_OverrunDetectionConfig(USART_TypeDef* USARTx, uint32_t USART_OVRDetection); -FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, uint32_t USART_FLAG); -void USART_ClearFlag(USART_TypeDef* USARTx, uint32_t USART_FLAG); -ITStatus USART_GetITStatus(USART_TypeDef* USARTx, uint32_t USART_IT); -void USART_ClearITPendingBit(USART_TypeDef* USARTx, uint32_t USART_IT); - -#ifdef __cplusplus -} -#endif - -#endif /* __FT32F0XX_USART_H */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT FMD *****END OF FILE****/ diff --git a/bsp/ft32/libraries/FT32F0xx/FT32F0xx_Driver/Inc/ft32f0xx_wwdg.h b/bsp/ft32/libraries/FT32F0xx/FT32F0xx_Driver/Inc/ft32f0xx_wwdg.h deleted file mode 100644 index 02e7c658b36..00000000000 --- a/bsp/ft32/libraries/FT32F0xx/FT32F0xx_Driver/Inc/ft32f0xx_wwdg.h +++ /dev/null @@ -1,91 +0,0 @@ -/** - ****************************************************************************** - * @file ft32f030x8_wwdg.h - * @author MCD Application Team - * @version V1.0.0 - * @date 2020-06-22 - * @brief This file contains all the functions prototypes for the WWDG - * firmware library. - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __FT32F030X8_WWDG_H -#define __FT32F030X8_WWDG_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "ft32f0xx.h" - -/** @addtogroup FT32F030X8_StdPeriph_Driver - * @{ - */ - -/** @addtogroup WWDG - * @{ - */ -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup WWDG_Exported_Constants - * @{ - */ - -/** @defgroup WWDG_Prescaler - * @{ - */ - -#define WWDG_Prescaler_1 ((uint32_t)0x00000000) -#define WWDG_Prescaler_2 ((uint32_t)0x00000080) -#define WWDG_Prescaler_4 ((uint32_t)0x00000100) -#define WWDG_Prescaler_8 ((uint32_t)0x00000180) -#define IS_WWDG_PRESCALER(PRESCALER) (((PRESCALER) == WWDG_Prescaler_1) || \ - ((PRESCALER) == WWDG_Prescaler_2) || \ - ((PRESCALER) == WWDG_Prescaler_4) || \ - ((PRESCALER) == WWDG_Prescaler_8)) -#define IS_WWDG_WINDOW_VALUE(VALUE) ((VALUE) <= 0x7F) -#define IS_WWDG_COUNTER(COUNTER) (((COUNTER) >= 0x40) && ((COUNTER) <= 0x7F)) - -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions ------------------------------------------------------- */ -/* Function used to set the WWDG configuration to the default reset state ****/ -void WWDG_DeInit(void); - -/* Prescaler, Refresh window and Counter configuration functions **************/ -void WWDG_SetPrescaler(uint32_t WWDG_Prescaler); -void WWDG_SetWindowValue(uint8_t WindowValue); -void WWDG_EnableIT(void); -void WWDG_SetCounter(uint8_t Counter); - -/* WWDG activation functions **************************************************/ -void WWDG_Enable(uint8_t Counter); - -/* Interrupts and flags management functions **********************************/ -FlagStatus WWDG_GetFlagStatus(void); -void WWDG_ClearFlag(void); - -#ifdef __cplusplus -} -#endif - -#endif /* __FT32F030X8_WWDG_H */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT FMD *****END OF FILE****/ diff --git a/bsp/ft32/libraries/FT32F0xx/FT32F0xx_Driver/Src/ft32f0xx_adc.c b/bsp/ft32/libraries/FT32F0xx/FT32F0xx_Driver/Src/ft32f0xx_adc.c deleted file mode 100644 index d909f9f3268..00000000000 --- a/bsp/ft32/libraries/FT32F0xx/FT32F0xx_Driver/Src/ft32f0xx_adc.c +++ /dev/null @@ -1,1265 +0,0 @@ -/** - ****************************************************************************** - * @file ft32f0xx_adc.c - * @author FMD AE - * @brief This file provides firmware functions to manage the following - * functionalities of the Analog to Digital Convertor (ADC) peripheral: - * + Initialization and Configuration - * + Power saving - * + Analog Watchdog configuration - * + Temperature Sensor, Vrefint (Internal Reference Voltage) and - * Vbat (Voltage battery) management - * + ADC Channels Configuration - * + ADC Channels DMA Configuration - * + Interrupts and flags management. - * @version V1.0.0 - * @data 2021-07-01 - ****************************************************************************** - */ - - -/* Includes ------------------------------------------------------------------*/ -#include "ft32f0xx_adc.h" -#include "ft32f0xx_rcc.h" - - - -/* ADC CFGR mask */ -#define CFGR1_CLEAR_MASK ((uint32_t)0xFFFFD203) - -/* Calibration time out */ -#define CALIBRATION_TIMEOUT ((uint32_t)0x0000F000) - -/** - * @brief Deinitializes ADC1 peripheral registers to their default reset values. - * @param ADCx: where x can be 1 to select the ADC peripheral. - * @retval None - */ -void ADC_DeInit(ADC_TypeDef* ADCx) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - - if(ADCx == ADC1) - { - /* Enable ADC1 reset state */ - RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC1, ENABLE); - - /* Release ADC1 from reset state */ - RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC1, DISABLE); - } -} - -/** - * @brief Initializes the ADCx peripheral according to the specified parameters - * in the ADC_InitStruct. - * @note This function is used to configure the global features of the ADC ( - * Resolution, Data Alignment, continuous mode activation, External - * trigger source and edge, Sequence Scan Direction). - * @param ADCx: where x can be 1 to select the ADC peripheral. - * @param ADC_InitStruct: pointer to an ADC_InitTypeDef structure that contains - * the configuration information for the specified ADC peripheral. - * @retval None - */ -void ADC_Init(ADC_TypeDef* ADCx, ADC_InitTypeDef* ADC_InitStruct) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_ADC_RESOLUTION(ADC_InitStruct->ADC_Resolution)); - assert_param(IS_FUNCTIONAL_STATE(ADC_InitStruct->ADC_ContinuousConvMode)); - assert_param(IS_ADC_EXT_TRIG_EDGE(ADC_InitStruct->ADC_ExternalTrigConvEdge)); - assert_param(IS_ADC_EXTERNAL_TRIG_CONV(ADC_InitStruct->ADC_ExternalTrigConv)); - assert_param(IS_ADC_DATA_ALIGN(ADC_InitStruct->ADC_DataAlign)); - assert_param(IS_ADC_SCAN_DIRECTION(ADC_InitStruct->ADC_ScanDirection)); - - /* Get the ADCx CFGR value */ - tmpreg = ADCx->CFGR1; - - /* Clear SCANDIR, RES[1:0], ALIGN, EXTSEL[2:0], EXTEN[1:0] and CONT bits */ - tmpreg &= CFGR1_CLEAR_MASK; - - /*---------------------------- ADCx CFGR Configuration ---------------------*/ - - /* Set RES[1:0] bits according to ADC_Resolution value */ - /* Set CONT bit according to ADC_ContinuousConvMode value */ - /* Set EXTEN[1:0] bits according to ADC_ExternalTrigConvEdge value */ - /* Set EXTSEL[2:0] bits according to ADC_ExternalTrigConv value */ - /* Set ALIGN bit according to ADC_DataAlign value */ - /* Set SCANDIR bit according to ADC_ScanDirection value */ - - tmpreg |= (uint32_t)(ADC_InitStruct->ADC_Resolution | ((uint32_t)(ADC_InitStruct->ADC_ContinuousConvMode) << 13) | - ADC_InitStruct->ADC_ExternalTrigConvEdge | ADC_InitStruct->ADC_ExternalTrigConv | - ADC_InitStruct->ADC_DataAlign | ADC_InitStruct->ADC_ScanDirection); - - /* Write to ADCx CFGR */ - ADCx->CFGR1 = tmpreg; -} - -/** - * @brief Fills each ADC_InitStruct member with its default value. - * @note This function is used to initialize the global features of the ADC ( - * Resolution, Data Alignment, continuous mode activation, External - * trigger source and edge, Sequence Scan Direction). - * @param ADC_InitStruct: pointer to an ADC_InitTypeDef structure which will - * be initialized. - * @retval None - */ -void ADC_StructInit(ADC_InitTypeDef* ADC_InitStruct) -{ - /* Reset ADC init structure parameters values */ - /* Initialize the ADC_Resolution member */ - ADC_InitStruct->ADC_Resolution = ADC_Resolution_12b; - - /* Initialize the ADC_ContinuousConvMode member */ - ADC_InitStruct->ADC_ContinuousConvMode = DISABLE; - - /* Initialize the ADC_ExternalTrigConvEdge member */ - ADC_InitStruct->ADC_ExternalTrigConvEdge = ADC_ExternalTrigConvEdge_None; - - /* Initialize the ADC_ExternalTrigConv member */ - ADC_InitStruct->ADC_ExternalTrigConv = ADC_ExternalTrigConv_T1_TRGO; - - /* Initialize the ADC_DataAlign member */ - ADC_InitStruct->ADC_DataAlign = ADC_DataAlign_Right; - - /* Initialize the ADC_ScanDirection member */ - ADC_InitStruct->ADC_ScanDirection = ADC_ScanDirection_Upward; -} - -/** - * @brief Enables or disables the specified ADC peripheral. - * @param ADCx: where x can be 1 to select the ADC1 peripheral. - * @param NewState: new state of the ADCx peripheral. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void ADC_Cmd(ADC_TypeDef* ADCx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Set the ADEN bit to Enable the ADC peripheral */ - ADCx->CR |= (uint32_t)ADC_CR_ADEN; - } - else - { - /* Set the ADDIS to Disable the ADC peripheral */ - ADCx->CR |= (uint32_t)ADC_CR_ADDIS; - } -} - -/** - * @brief Configure the ADC to either be clocked by the asynchronous clock(which is - * independent, the dedicated 14MHz clock) or the synchronous clock derived from - * the APB clock of the ADC bus interface divided by 2 or 4 - * @note This function can be called only when ADC is disabled. - * @param ADCx: where x can be 1 to select the ADC1 peripheral. - * @param ADC_ClockMode: This parameter can be : - * @arg ADC_ClockMode_AsynClk: ADC clocked by the dedicated 14MHz clock - * @arg ADC_ClockMode_SynClkDiv2: ADC clocked by PCLK/2 - * @arg ADC_ClockMode_SynClkDiv4: ADC clocked by PCLK/4 - * @retval None - */ -void ADC_ClockModeConfig(ADC_TypeDef* ADCx, uint32_t ADC_ClockMode) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_ADC_CLOCKMODE(ADC_ClockMode)); - - /* Configure the ADC Clock mode according to ADC_ClockMode */ - ADCx->CFGR2 = (uint32_t)ADC_ClockMode; - -} - -/** - * @brief Enables or disables the jitter when the ADC is clocked by PCLK div2 - * or div4 - * @note This function is obsolete and maintained for legacy purpose only. ADC_ClockModeConfig() - * function should be used instead. - * @param ADCx: where x can be 1 to select the ADC1 peripheral. - * @param ADC_JitterOff: This parameter can be : - * @arg ADC_JitterOff_PCLKDiv2: Remove jitter when ADC is clocked by PLCK divided by 2 - * @arg ADC_JitterOff_PCLKDiv4: Remove jitter when ADC is clocked by PLCK divided by 4 - * @param NewState: new state of the ADCx jitter. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void ADC_JitterCmd(ADC_TypeDef* ADCx, uint32_t ADC_JitterOff, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_ADC_JITTEROFF(ADC_JitterOff)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Disable Jitter */ - ADCx->CFGR2 |= (uint32_t)ADC_JitterOff; - } - else - { - /* Enable Jitter */ - ADCx->CFGR2 &= (uint32_t)(~ADC_JitterOff); - } -} - -/** - * @} - */ - -/** - * @brief Enables or disables the ADC Power Off. - * @note ADC power-on and power-off can be managed by hardware to cut the - * consumption when the ADC is not converting. - * @param ADCx: where x can be 1 to select the ADC1 peripheral. - * @note The ADC can be powered down: - * - During the Auto delay phase: The ADC is powered on again at the end - * of the delay (until the previous data is read from the ADC data register). - * - During the ADC is waiting for a trigger event: The ADC is powered up - * at the next trigger event (when the conversion is started). - * @param NewState: new state of the ADCx power Off. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void ADC_AutoPowerOffCmd(ADC_TypeDef* ADCx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the ADC Automatic Power-Off */ - ADCx->CFGR1 |= ADC_CFGR1_AUTOFF; - } - else - { - /* Disable the ADC Automatic Power-Off */ - ADCx->CFGR1 &= (uint32_t)~ADC_CFGR1_AUTOFF; - } -} - -/** - * @brief Enables or disables the Wait conversion mode. - * @note When the CPU clock is not fast enough to manage the data rate, a - * Hardware delay can be introduced between ADC conversions to reduce - * this data rate. - * @note The Hardware delay is inserted after each conversions and until the - * previous data is read from the ADC data register - * @note This is a way to automatically adapt the speed of the ADC to the speed - * of the system which will read the data. - * @note Any hardware triggers wich occur while a conversion is on going or - * while the automatic Delay is applied are ignored - * @param ADCx: where x can be 1 to select the ADC1 peripheral. - * @param NewState: new state of the ADCx Auto-Delay. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void ADC_WaitModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the ADC Automatic Delayed conversion */ - ADCx->CFGR1 |= ADC_CFGR1_WAIT; - } - else - { - /* Disable the ADC Automatic Delayed conversion */ - ADCx->CFGR1 &= (uint32_t)~ADC_CFGR1_WAIT; - } -} - -/** - * @} - */ -/** - * @brief Enables or disables the analog watchdog - * @param ADCx: where x can be 1 to select the ADC1 peripheral. - * @param NewState: new state of the ADCx Analog Watchdog. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void ADC_AnalogWatchdogCmd(ADC_TypeDef* ADCx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the ADC Analog Watchdog */ - ADCx->CFGR1 |= ADC_CFGR1_AWDEN; - } - else - { - /* Disable the ADC Analog Watchdog */ - ADCx->CFGR1 &= (uint32_t)~ADC_CFGR1_AWDEN; - } -} - -/** - * @brief Configures the high and low thresholds of the analog watchdog. - * @param ADCx: where x can be 1 to select the ADC1 peripheral. - * @param HighThreshold: the ADC analog watchdog High threshold value. - * This parameter must be a 12bit value. - * @param LowThreshold: the ADC analog watchdog Low threshold value. - * This parameter must be a 12bit value. - * @retval None - */ -void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef* ADCx, uint16_t HighThreshold, - uint16_t LowThreshold) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_ADC_THRESHOLD(HighThreshold)); - assert_param(IS_ADC_THRESHOLD(LowThreshold)); - - /* Set the ADCx high and low threshold */ - ADCx->TR = LowThreshold | ((uint32_t)HighThreshold << 16); - -} - -/** - * @brief Configures the analog watchdog guarded single channel - * @param ADCx: where x can be 1 to select the ADC1 peripheral. - * @param ADC_AnalogWatchdog_Channel: the ADC channel to configure for the analog watchdog. - * This parameter can be one of the following values: - * @arg ADC_AnalogWatchdog_Channel_0: ADC Channel0 selected - * @arg ADC_AnalogWatchdog_Channel_1: ADC Channel1 selected - * @arg ADC_AnalogWatchdog_Channel_2: ADC Channel2 selected - * @arg ADC_AnalogWatchdog_Channel_3: ADC Channel3 selected - * @arg ADC_AnalogWatchdog_Channel_4: ADC Channel4 selected - * @arg ADC_AnalogWatchdog_Channel_5: ADC Channel5 selected - * @arg ADC_AnalogWatchdog_Channel_6: ADC Channel6 selected - * @arg ADC_AnalogWatchdog_Channel_7: ADC Channel7 selected - * @arg ADC_AnalogWatchdog_Channel_8: ADC Channel8 selected - * @arg ADC_AnalogWatchdog_Channel_9: ADC Channel9 selected - * @arg ADC_AnalogWatchdog_Channel_10: ADC Channel10 selected - * @arg ADC_AnalogWatchdog_Channel_11: ADC Channel11 selected - * @arg ADC_AnalogWatchdog_Channel_12: ADC Channel12 selected - * @arg ADC_AnalogWatchdog_Channel_13: ADC Channel13 selected - * @arg ADC_AnalogWatchdog_Channel_14: ADC Channel14 selected - * @arg ADC_AnalogWatchdog_Channel_15: ADC Channel15 selected - * @arg ADC_AnalogWatchdog_Channel_16: ADC Channel16 selected - * @arg ADC_AnalogWatchdog_Channel_17: ADC Channel17 selected - * @arg ADC_AnalogWatchdog_Channel_18: ADC Channel18 selected - * @note The channel selected on the AWDCH must be also set into the CHSELR - * register - * @retval None - */ -void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef* ADCx, uint32_t ADC_AnalogWatchdog_Channel) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_ADC_ANALOG_WATCHDOG_CHANNEL(ADC_AnalogWatchdog_Channel)); - - /* Get the old register value */ - tmpreg = ADCx->CFGR1; - - /* Clear the Analog watchdog channel select bits */ - tmpreg &= ~ADC_CFGR1_AWDCH; - - /* Set the Analog watchdog channel */ - tmpreg |= ADC_AnalogWatchdog_Channel; - - /* Store the new register value */ - ADCx->CFGR1 = tmpreg; -} - -/** - * @brief Enables or disables the ADC Analog Watchdog Single Channel. - * @param ADCx: where x can be 1 to select the ADC1 peripheral. - * @param NewState: new state of the ADCx ADC Analog Watchdog Single Channel. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void ADC_AnalogWatchdogSingleChannelCmd(ADC_TypeDef* ADCx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the ADC Analog Watchdog Single Channel */ - ADCx->CFGR1 |= ADC_CFGR1_AWDSGL; - } - else - { - /* Disable the ADC Analog Watchdog Single Channel */ - ADCx->CFGR1 &= (uint32_t)~ADC_CFGR1_AWDSGL; - } -} - -/** - * @} - */ -/** - * @brief Enables or disables the temperature sensor channel. - * @param NewState: new state of the temperature sensor input channel. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void ADC_TempSensorCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the temperature sensor channel*/ - ADC->CCR |= (uint32_t)ADC_CCR_TSEN; - } - else - { - /* Disable the temperature sensor channel*/ - ADC->CCR &= (uint32_t)(~ADC_CCR_TSEN); - } -} - -/** - * @brief Enables or disables the Vrefint channel. - * @param NewState: new state of the Vref input channel. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void ADC_VrefintCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the Vrefint channel*/ - ADC->CCR |= (uint32_t)ADC_CCR_VREFEN; - } - else - { - /* Disable the Vrefint channel*/ - ADC->CCR &= (uint32_t)(~ADC_CCR_VREFEN); - } -} - -/** - * @brief Enables or disables the Vbat channel. - * @note This feature is not applicable for FT32F030 devices. - * @param NewState: new state of the Vbat input channel. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void ADC_VbatCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the Vbat channel*/ - ADC->CCR |= (uint32_t)ADC_CCR_VBATEN; - } - else - { - /* Disable the Vbat channel*/ - ADC->CCR &= (uint32_t)(~ADC_CCR_VBATEN); - } -} - -/** - * @} - */ -/** - * @brief Configures for the selected ADC and its sampling time. - * @param ADCx: where x can be 1 to select the ADC peripheral. - * @param ADC_Channel: the ADC channel to configure. - * This parameter can be any combination of the following values: - * @arg ADC_Channel_0: ADC Channel0 selected - * @arg ADC_Channel_1: ADC Channel1 selected - * @arg ADC_Channel_2: ADC Channel2 selected - * @arg ADC_Channel_3: ADC Channel3 selected - * @arg ADC_Channel_4: ADC Channel4 selected - * @arg ADC_Channel_5: ADC Channel5 selected - * @arg ADC_Channel_6: ADC Channel6 selected - * @arg ADC_Channel_7: ADC Channel7 selected - * @arg ADC_Channel_8: ADC Channel8 selected - * @arg ADC_Channel_9: ADC Channel9 selected - * @arg ADC_Channel_10: ADC Channel10 selected, - * @arg ADC_Channel_11: ADC Channel11 selected, - * @arg ADC_Channel_12: ADC Channel12 selected, - * @arg ADC_Channel_13: ADC Channel13 selected, - * @arg ADC_Channel_14: ADC Channel14 selected, - * @arg ADC_Channel_15: ADC Channel15 selected, - * @arg ADC_Channel_16: ADC Channel16 selected - * @arg ADC_Channel_17: ADC Channel17 selected - * @arg ADC_Channel_18: ADC Channel18 selected, - * @arg ADC_Channel_19: ADC Channel19 selected, - * @arg ADC_Channel_20: ADC Channel20 selected, - * @arg ADC_Channel_21: ADC Channel21 selected, - * @param ADC_SampleTime: The sample time value to be set for the selected channel. - * This parameter can be one of the following values: - * @arg ADC_SampleTime_1_5Cycles: Sample time equal to 1.5 cycles - * @arg ADC_SampleTime_7_5Cycles: Sample time equal to 7.5 cycles - * @arg ADC_SampleTime_13_5Cycles: Sample time equal to 13.5 cycles - * @arg ADC_SampleTime_28_5Cycles: Sample time equal to 28.5 cycles - * @arg ADC_SampleTime_41_5Cycles: Sample time equal to 41.5 cycles - * @arg ADC_SampleTime_55_5Cycles: Sample time equal to 55.5 cycles - * @arg ADC_SampleTime_71_5Cycles: Sample time equal to 71.5 cycles - * @arg ADC_SampleTime_239_5Cycles: Sample time equal to 239.5 cycles - * @retval None - */ -void ADC_ChannelConfig(ADC_TypeDef* ADCx, uint32_t ADC_Channel, uint32_t ADC_SampleTime) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_ADC_CHANNEL(ADC_Channel)); - assert_param(IS_ADC_SAMPLE_TIME(ADC_SampleTime)); - - /* Configure the ADC Channel */ - ADCx->CHSELR |= (uint32_t)ADC_Channel; - - /* Clear the Sampling time Selection bits */ - tmpreg &= ~ADC_SMPR1_SMPR; - - /* Set the ADC Sampling Time register */ - tmpreg |= (uint32_t)ADC_SampleTime; - - /* Configure the ADC Sample time register */ - ADCx->SMPR = tmpreg ; -} - -/** - * @brief Enable the Continuous mode for the selected ADCx channels. - * @param ADCx: where x can be 1 to select the ADC1 peripheral. - * @param NewState: new state of the Continuous mode. - * This parameter can be: ENABLE or DISABLE. - * @note It is not possible to have both discontinuous mode and continuous mode - * enabled. In this case (If DISCEN and CONT are Set), the ADC behaves - * as if continuous mode was disabled - * @retval None - */ -void ADC_ContinuousModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the Continuous mode*/ - ADCx->CFGR1 |= (uint32_t)ADC_CFGR1_CONT; - } - else - { - /* Disable the Continuous mode */ - ADCx->CFGR1 &= (uint32_t)(~ADC_CFGR1_CONT); - } -} - -/** - * @brief Enable the discontinuous mode for the selected ADC channels. - * @param ADCx: where x can be 1 to select the ADC1 peripheral. - * @param NewState: new state of the discontinuous mode. - * This parameter can be: ENABLE or DISABLE. - * @note It is not possible to have both discontinuous mode and continuous mode - * enabled. In this case (If DISCEN and CONT are Set), the ADC behaves - * as if continuous mode was disabled - * @retval None - */ -void ADC_DiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the Discontinuous mode */ - ADCx->CFGR1 |= (uint32_t)ADC_CFGR1_DISCEN; - } - else - { - /* Disable the Discontinuous mode */ - ADCx->CFGR1 &= (uint32_t)(~ADC_CFGR1_DISCEN); - } -} - -/** - * @brief Enable the Overrun mode for the selected ADC channels. - * @param ADCx: where x can be 1 to select the ADC1 peripheral. - * @param NewState: new state of the Overrun mode. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void ADC_OverrunModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the Overrun mode */ - ADCx->CFGR1 |= (uint32_t)ADC_CFGR1_OVRMOD; - } - else - { - /* Disable the Overrun mode */ - ADCx->CFGR1 &= (uint32_t)(~ADC_CFGR1_OVRMOD); - } -} - -/** - * @brief Active the Calibration operation for the selected ADC. - * @note The Calibration can be initiated only when ADC is still in the - * reset configuration (ADEN must be equal to 0). - * @param ADCx: where x can be 1 to select the ADC1 peripheral. - * @retval ADC Calibration factor - */ -uint32_t ADC_GetCalibrationFactor(ADC_TypeDef* ADCx) -{ - uint32_t tmpreg = 0, calibrationcounter = 0, calibrationstatus = 0; - - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - - /* Set the ADC calibartion */ - ADCx->CR |= (uint32_t)ADC_CR_ADCAL; - - /* Wait until no ADC calibration is completed */ - do - { - calibrationstatus = ADCx->CR & ADC_CR_ADCAL; - calibrationcounter++; - } while((calibrationcounter != CALIBRATION_TIMEOUT) && (calibrationstatus != 0x00)); - - if((uint32_t)(ADCx->CR & ADC_CR_ADCAL) == RESET) - { - /*Get the calibration factor from the ADC data register */ - tmpreg = ADCx->DR; - } - else - { - /* Error factor */ - tmpreg = 0x00000000; - } - return tmpreg; -} - -/** - * @brief Stop the on going conversions for the selected ADC. - * @note When ADSTP is set, any on going conversion is aborted, and the ADC - * data register is not updated with current conversion. - * @param ADCx: where x can be 1 to select the ADC1 peripheral. - * @retval None - */ -void ADC_StopOfConversion(ADC_TypeDef* ADCx) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - - ADCx->CR |= (uint32_t)ADC_CR_ADSTP; -} - -/** - * @brief Start Conversion for the selected ADC channels. - * @note In continuous mode, ADSTART is not cleared by hardware with the - * assertion of EOSEQ because the sequence is automatic relaunched - * @param ADCx: where x can be 1 to select the ADC1 peripheral. - * @retval None - */ -void ADC_StartOfConversion(ADC_TypeDef* ADCx) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - - ADCx->CR |= (uint32_t)ADC_CR_ADSTART; -} - -/** - * @brief Returns the last ADCx conversion result data for ADC channel. - * @param ADCx: where x can be 1 to select the ADC1 peripheral. - * @retval The Data conversion value. - */ -uint16_t ADC_GetConversionValue(ADC_TypeDef* ADCx) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - - /* Return the selected ADC conversion value */ - return (uint16_t) ADCx->DR; -} - -/** - * @} - */ -/** - * @brief Enables or disables the specified ADC DMA request. - * @param ADCx: where x can be 1 to select the ADC1 peripheral. - * @param NewState: new state of the selected ADC DMA transfer. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void ADC_DMACmd(ADC_TypeDef* ADCx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the selected ADC DMA request */ - ADCx->CFGR1 |= (uint32_t)ADC_CFGR1_DMAEN; - } - else - { - /* Disable the selected ADC DMA request */ - ADCx->CFGR1 &= (uint32_t)(~ADC_CFGR1_DMAEN); - } -} - -/** - * @brief Enables or disables the ADC DMA request after last transfer (Single-ADC mode) - * @param ADCx: where x can be 1 to select the ADC1 peripheral. - * @param ADC_DMARequestMode: the ADC channel to configure. - * This parameter can be one of the following values: - * @arg ADC_DMAMode_OneShot: DMA One Shot Mode - * @arg ADC_DMAMode_Circular: DMA Circular Mode - * @retval None - */ -void ADC_DMARequestModeConfig(ADC_TypeDef* ADCx, uint32_t ADC_DMARequestMode) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - - ADCx->CFGR1 &= (uint32_t)~ADC_CFGR1_DMACFG; - ADCx->CFGR1 |= (uint32_t)ADC_DMARequestMode; -} - -/** - * @} - */ -/** - * @brief Enables or disables the specified ADC interrupts. - * @param ADCx: where x can be 1 to select the ADC peripheral. - * @param ADC_IT: specifies the ADC interrupt sources to be enabled or disabled. - * This parameter can be one of the following values: - * @arg ADC_IT_ADRDY: ADC ready interrupt - * @arg ADC_IT_EOSMP: End of sampling interrupt - * @arg ADC_IT_EOC: End of conversion interrupt - * @arg ADC_IT_EOSEQ: End of sequence of conversion interrupt - * @arg ADC_IT_OVR: overrun interrupt - * @arg ADC_IT_AWD: Analog watchdog interrupt - * @param NewState: new state of the specified ADC interrupts. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void ADC_ITConfig(ADC_TypeDef* ADCx, uint32_t ADC_IT, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - assert_param(IS_ADC_CONFIG_IT(ADC_IT)); - - if (NewState != DISABLE) - { - /* Enable the selected ADC interrupts */ - ADCx->IER |= ADC_IT; - } - else - { - /* Disable the selected ADC interrupts */ - ADCx->IER &= (~(uint32_t)ADC_IT); - } -} - -/** - * @brief Checks whether the specified ADC flag is set or not. - * @param ADCx: where x can be 1 to select the ADC1 peripheral. - * @param ADC_FLAG: specifies the flag to check. - * This parameter can be one of the following values: - * @arg ADC_FLAG_AWD: Analog watchdog flag - * @arg ADC_FLAG_OVR: Overrun flag - * @arg ADC_FLAG_EOSEQ: End of Sequence flag - * @arg ADC_FLAG_EOC: End of conversion flag - * @arg ADC_FLAG_EOSMP: End of sampling flag - * @arg ADC_FLAG_ADRDY: ADC Ready flag - * @arg ADC_FLAG_ADEN: ADC enable flag - * @arg ADC_FLAG_ADDIS: ADC disable flag - * @arg ADC_FLAG_ADSTART: ADC start flag - * @arg ADC_FLAG_ADSTP: ADC stop flag - * @arg ADC_FLAG_ADCAL: ADC Calibration flag - * @retval The new state of ADC_FLAG (SET or RESET). - */ -FlagStatus ADC_GetFlagStatus(ADC_TypeDef* ADCx, uint32_t ADC_FLAG) -{ - FlagStatus bitstatus = RESET; - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_ADC_GET_FLAG(ADC_FLAG)); - - if((uint32_t)(ADC_FLAG & 0x01000000)) - { - tmpreg = ADCx->CR & 0xFEFFFFFF; - } - else - { - tmpreg = ADCx->ISR; - } - - /* Check the status of the specified ADC flag */ - if ((tmpreg & ADC_FLAG) != (uint32_t)RESET) - { - /* ADC_FLAG is set */ - bitstatus = SET; - } - else - { - /* ADC_FLAG is reset */ - bitstatus = RESET; - } - /* Return the ADC_FLAG status */ - return bitstatus; -} - -/** - * @brief Clears the ADCx's pending flags. - * @param ADCx: where x can be 1 to select the ADC1 peripheral. - * @param ADC_FLAG: specifies the flag to clear. - * This parameter can be any combination of the following values: - * @arg ADC_FLAG_AWD: Analog watchdog flag - * @arg ADC_FLAG_EOC: End of conversion flag - * @arg ADC_FLAG_ADRDY: ADC Ready flag - * @arg ADC_FLAG_EOSMP: End of sampling flag - * @arg ADC_FLAG_EOSEQ: End of Sequence flag - * @arg ADC_FLAG_OVR: Overrun flag - * @retval None - */ -void ADC_ClearFlag(ADC_TypeDef* ADCx, uint32_t ADC_FLAG) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_ADC_CLEAR_FLAG(ADC_FLAG)); - - /* Clear the selected ADC flags */ - ADCx->ISR = (uint32_t)ADC_FLAG; -} - -/** - * @brief Checks whether the specified ADC interrupt has occurred or not. - * @param ADCx: where x can be 1 to select the ADC1 peripheral - * @param ADC_IT: specifies the ADC interrupt source to check. - * This parameter can be one of the following values: - * @arg ADC_IT_ADRDY: ADC ready interrupt - * @arg ADC_IT_EOSMP: End of sampling interrupt - * @arg ADC_IT_EOC: End of conversion interrupt - * @arg ADC_IT_EOSEQ: End of sequence of conversion interrupt - * @arg ADC_IT_OVR: overrun interrupt - * @arg ADC_IT_AWD: Analog watchdog interrupt - * @retval The new state of ADC_IT (SET or RESET). - */ -ITStatus ADC_GetITStatus(ADC_TypeDef* ADCx, uint32_t ADC_IT) -{ - ITStatus bitstatus = RESET; - uint32_t enablestatus = 0; - - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_ADC_GET_IT(ADC_IT)); - - /* Get the ADC_IT enable bit status */ - enablestatus = (uint32_t)(ADCx->IER & ADC_IT); - - /* Check the status of the specified ADC interrupt */ - if (((uint32_t)(ADCx->ISR & ADC_IT) != (uint32_t)RESET) && (enablestatus != (uint32_t)RESET)) - { - /* ADC_IT is set */ - bitstatus = SET; - } - else - { - /* ADC_IT is reset */ - bitstatus = RESET; - } - /* Return the ADC_IT status */ - return bitstatus; -} - -/** - * @brief Clears the ADCx's interrupt pending bits. - * @param ADCx: where x can be 1 to select the ADC1 peripheral. - * @param ADC_IT: specifies the ADC interrupt pending bit to clear. - * This parameter can be one of the following values: - * @arg ADC_IT_ADRDY: ADC ready interrupt - * @arg ADC_IT_EOSMP: End of sampling interrupt - * @arg ADC_IT_EOC: End of conversion interrupt - * @arg ADC_IT_EOSEQ: End of sequence of conversion interrupt - * @arg ADC_IT_OVR: overrun interrupt - * @arg ADC_IT_AWD: Analog watchdog interrupt - * @retval None - */ -void ADC_ClearITPendingBit(ADC_TypeDef* ADCx, uint32_t ADC_IT) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_ADC_CLEAR_IT(ADC_IT)); - - /* Clear the selected ADC interrupt pending bits */ - ADCx->ISR = (uint32_t)ADC_IT; -} - - -/** - * @brief select the ADC VREF. - * @param ADC_Vrefsel: The sVREF value to be set for the ADC. - This parameter can be one of the following values: - * @arg ADC_Vrefsel_0_625V: VREF 0.625V selected - * @arg ADC_Vrefsel_1_5V: VREF 1.5V selected - * @arg ADC_Vrefsel_2_5V: VREF 2.5V selected - * @arg ADC_Vrefsel_VDDA: VREF VDDA selected - * @retval None - */ -void ADC_VrefselConfig(uint32_t ADC_Vrefsel) -{ - uint32_t tmpreg = 0; - /* Check the parameters */ - assert_param(IS_ADC_Vrefsel(ADC_Vrefsel)); - - /* Read CR2 register */ - tmpreg = ADC->CR2; - - /* Clear the Vref Selection bits */ - tmpreg &= ~((uint32_t)0x0000000E) ; - - /* Set the ADC Vref register */ - tmpreg |= (uint32_t)ADC_Vrefsel; - - /* Configure the ADC Vref register */ - ADC->CR2 = tmpreg; -} - -/** - * @brief Enable Reference voltage halved. - * @param NewState: new state of the reference voltage halved. - * This parameter can be: ENABLE or DISABLE. - * @note None - * @retval None - */ -void ADC_VrefDecibCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the Discontinuous mode */ - ADC->CR2 |= (uint32_t)ADC_CR2_VREF_DECIB; - } - else - { - /* Disable the Discontinuous mode */ - ADC->CR2 &= (uint32_t)(~ADC_CR2_VREF_DECIB); - } -} - -/** - * @brief Sampling hold circuit sampling enable or disable. - * @param SmpEn: - * @arg ADC_IOSH1_SMPEN - * @arg ADC_IOSH2_SMPEN - * @param NewState: new state of SMP. - * This parameter can be: ENABLE or DISABLE. - * @note None - * @retval None - */ -void ADC_IoshSmpCmd(uint32_t SmpEn, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_ADC_SMPEN(SmpEn)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - ADC->CR2 |= SmpEn; - } - else - { - ADC->CR2 &= ~SmpEn; - } -} - -/** - * @brief The hold enable bit of the sample-hold circuit. - * @param SmpEn: - * @arg ADC_IOSH1_AMPEN - * @arg ADC_IOSH2_AMPEN - * @param NewState: new state of AMP. - * This parameter can be: ENABLE or DISABLE. - * @note None - * @retval None - */ -void ADC_IoshAmpCmd(uint32_t AmpEn, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_ADC_AMPEN(AmpEn)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - ADC->CR2 |= AmpEn; - } - else - { - ADC->CR2 &= ~AmpEn; - } -} - -/** - * @brief Input source selection. - * @param Ioshx: - * @arg ADC_CR2_IOSH1_SEL - * @arg ADC_CR2_IOSH2_SEL - * @param SmpSel: - * if Ioshx is ADC_CR2_IOSH1_SEL,the SmpSel can be - * @arg ADC_IOSH1_SMPSEL_PB1 - * @arg ADC_IOSH1_SMPSEL_OP1OUT - * if Ioshx is ADC_CR2_IOSH2_SEL,the SmpSel can be - * @arg ADC_IOSH2_SMPSEL_PB0 - * @arg ADC_IOSH2_SMPSEL_OP2OUT - * @note None - * @retval None - */ -#if defined (FT32F072xB) -void ADC_IoshSmpSel(uint32_t Ioshx, uint32_t SmpSel) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_ADC_IOSH(Ioshx)); - assert_param(IS_ADC_SMPSEL(SmpSel)); - - /* Read CR2 register */ - tmpreg = ADC->CR2; - - if (Ioshx != ADC_CR2_IOSH1_SEL) - { - /* IOSH2 */ - tmpreg &= ~ADC_CR2_IOSH2_SEL; - } - else - { - /* IOSH1 */ - tmpreg &= ~ADC_CR2_IOSH1_SEL; - } - - tmpreg |= SmpSel; - - /* Config CR2 register */ - ADC->CR2 = tmpreg; -} -/** - * @brief The hold enable bit of the sample-hold circuit. - * @param SmpModBit: - * @arg ADC_CR2_IOSH1_SMPMOD - * @arg ADC_CR2_IOSH2_SMPMOD - * @param Mode: - * @arg ADC_SMP_SOFTWARE_MODE - * @arg ADC_SMP_HARDWARE_MODE - * @note None - * @retval None - */ -void ADC_IoshSmpMod(uint32_t SmpModBit, uint32_t Mode) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_ADC_SMPMOD(SmpModBit)); - assert_param(IS_ADC_MODE(Mode)); - - /* Read CR2 register */ - tmpreg = ADC->CR2; - - if (Mode != ADC_SMP_SOFTWARE_MODE) - { - /* Hardware mode */ - if (SmpModBit != ADC_CR2_IOSH1_SMPMOD) - { - /* IOSH2 */ - tmpreg |= ADC_CR2_IOSH2_SMPMOD | ADC_CR2_IOSH2_AMPEN; - } - else - { - /* IOSH1 */ - tmpreg |= ADC_CR2_IOSH1_SMPMOD | ADC_CR2_IOSH1_AMPEN; - } - } - else - { - /* Software mode */ - if (SmpModBit != ADC_CR2_IOSH1_SMPMOD) - { - /* IOSH2 */ - tmpreg &= ~ADC_CR2_IOSH2_AMPEN; - tmpreg |= ADC_CR2_IOSH2_SMPMOD | ADC_CR2_IOSH2_SMPEN; - } - else - { - /* IOSH1 */ - tmpreg &= ~ADC_CR2_IOSH1_AMPEN; - tmpreg |= ADC_CR2_IOSH1_SMPMOD | ADC_CR2_IOSH1_SMPEN; - } - } - - /* Config CR2 register */ - ADC->CR2 = tmpreg; -} -/** - * @brief External hardware trigger mode config. - * @param NewState: new state of . - * This parameter can be: ENABLE or DISABLE. - * @note None - * @retval None - */ -void ADC_ExtModeCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - ADC1->ETCR |= ADC_ETCR_EXTMOD; - } - else - { - ADC1->ETCR &= ~ADC_ETCR_EXTMOD; - } -} - -/** - * @brief Stop sampling configuration after triggering. - * @param NewState: new state of . - * This parameter can be: ENABLE or DISABLE. - * @note None - * @retval None - */ -void ADC_TrgdDisSmpCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - ADC1->ETCR |= ADC_ETCR_TRGDISSMP; - } - else - { - ADC1->ETCR &= ~ADC_ETCR_TRGDISSMP; - } -} -/** - * @brief The delay time of The external hardware triggers. - * @param ExtDly: 0~1023. - * @note None - * @retval None - */ -void ADC_ExtDlyConfig(uint32_t ExtDly) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_ADC_EXTDLY(ExtDly)); - - /* Read ETCR register */ - tmpreg = ADC1->ETCR; - - /* Clear EXTDLY */ - tmpreg &= ~ADC_ETCR_EXTDLY; - - /* Config EXTDLY */ - tmpreg |= ExtDly; - - /* Config ETCR */ - ADC1->ETCR = tmpreg; -} - -/** - * @brief Rising edge triggering config. - * @param Rtenx:This parameter can be : - * ADC_RTENR_RTEN or ADC_RTENR_RTEN_0 ~ ADC_RTENR_RTEN_18 - * @param NewState: new state of . - * This parameter can be: ENABLE or DISABLE. - * @note None - * @retval None - */ -void ADC_RtenCmd(uint32_t Rtenx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_ADC_RTEN(Rtenx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - ADC1->RTENR |= Rtenx; - } - else - { - ADC1->RTENR &= ~Rtenx; - } -} - -/** - * @brief Falling edge triggering config. - * @param Ftenx:This parameter can be : - * ADC_FTENR_RTEN or ADC_FTENR_RTEN_0 ~ ADC_FTENR_RTEN_18 - * @param NewState: new state of . - * This parameter can be: ENABLE or DISABLE. - * @note None - * @retval None - */ -void ADC_FtenCmd(uint32_t Ftenx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_ADC_FTEN(Ftenx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - ADC1->FTENR |= Ftenx; - } - else - { - ADC1->FTENR &= ~Ftenx; - } -} - -#endif -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT FMD *****END OF FILE****/ diff --git a/bsp/ft32/libraries/FT32F0xx/FT32F0xx_Driver/Src/ft32f0xx_comp.c b/bsp/ft32/libraries/FT32F0xx/FT32F0xx_Driver/Src/ft32f0xx_comp.c deleted file mode 100644 index c816032be10..00000000000 --- a/bsp/ft32/libraries/FT32F0xx/FT32F0xx_Driver/Src/ft32f0xx_comp.c +++ /dev/null @@ -1,309 +0,0 @@ -/** - ****************************************************************************** - * @file ft32f0xx_comp.c - * @author FMD AE - * @brief This file provides firmware functions to manage the following - * functionalities of the comparators (COMP1 and COMP2) peripheral: - * + Comparators configuration - * + Window mode control - * @version V1.0.0 - * @data 2021-07-01 - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "ft32f0xx_comp.h" - -#define COMP_CSR_CLEAR_MASK ((uint32_t)0x00003FFE) - -/** - * @brief Deinitializes COMP peripheral registers to their default reset values. - * @note Deinitialization can't be performed if the COMP configuration is locked. - * To unlock the configuration, perform a system reset. - * @param None - * @retval None - */ -void COMP_DeInit(void) -{ - COMP->CSR = ((uint32_t)0x00000000); /*!< Set COMP_CSR register to reset value */ - - #if defined(FT32F072xB) - COMP->CSR2 = ((uint32_t)0x00000000); - #endif -} - -/** - * @brief Initializes the COMP peripheral according to the specified parameters - * in COMP_InitStruct - * @note If the selected comparator is locked, initialization can't be performed. - * To unlock the configuration, perform a system reset. - * @note By default, PA1 is selected as COMP1 non inverting input. - * - * @param COMP_Selection: the selected comparator. - * This parameter can be one of the following values: - * @arg COMP_Selection_COMP1: COMP1 selected - * @arg COMP_Selection_COMP2: COMP2 selected - * @arg COMP_Selection_COMP3: COMP3 selected - * @param COMP_InitStruct: pointer to an COMP_InitTypeDef structure that contains - * the configuration information for the specified COMP peripheral. - * @retval None - */ -void COMP_Init(uint32_t COMP_Selection, COMP_InitTypeDef* COMP_InitStruct) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_COMP_ALL_PERIPH(COMP_Selection)); - assert_param(IS_COMP_VIP_SEL(COMP_InitStruct->COMP_VipSel)); - assert_param(IS_COMP_VINSEL(COMP_InitStruct->COMP_VinSel)); - assert_param(IS_COMP_OUTPUT_SEL(COMP_InitStruct->COMP_OutputSel)); - assert_param(IS_COMP_POL(COMP_InitStruct->COMP_Pol)); - - if (COMP_Selection != COMP_Selection_COMP3) - { - /*!< Get the COMP_CSR register value */ - tmpreg = COMP->CSR; - - /*!< Clear the bits */ - tmpreg &= (uint32_t) ~(COMP_CSR_CLEAR_MASK<COMP_VipSel | COMP_InitStruct->COMP_VinSel| - COMP_InitStruct->COMP_OutputSel | COMP_InitStruct->COMP_Pol)); - - /*!< Write to COMP_CSR register */ - COMP->CSR = tmpreg; - } - else - { - #if defined(FT32F072xB) - /*!< Get the COMP_CSR register value */ - tmpreg = COMP->CSR2; - - /*!< Clear the bits */ - tmpreg &= (uint32_t) ~(COMP_CSR_CLEAR_MASK); - - /*!< Configure COMP: COMP_VipSel, COMP_VinSel, COMP_OutputSel value and COMP_Pol */ - tmpreg |= (uint32_t)((COMP_InitStruct->COMP_VipSel | COMP_InitStruct->COMP_VinSel| - COMP_InitStruct->COMP_OutputSel | COMP_InitStruct->COMP_Pol)); - - /*!< Write to COMP_CSR2 register */ - COMP->CSR2 = tmpreg; - #endif - } -} - -/** - * @brief Fills each COMP_InitStruct member with its default value. - * @param COMP_InitStruct: pointer to an COMP_InitTypeDef structure which will - * be initialized. - * @retval None - */ -void COMP_StructInit(COMP_InitTypeDef* COMP_InitStruct) -{ - #if defined(FT32F072xB) - COMP_InitStruct->COMP_VipSel = 0; - COMP_InitStruct->COMP_VinSel = 0; - COMP_InitStruct->COMP_OutputSel = 0; - COMP_InitStruct->COMP_Pol = 0; - #else - COMP_InitStruct->COMP_VipSel = NCOMP_VIP_SEL_PAD_PA1; - COMP_InitStruct->COMP_VinSel = NCOMP_VIN_SEL_PAD_PA0 | PCOMP_VIN_SEL_PAD_PA2; - COMP_InitStruct->COMP_OutputSel = 0; - COMP_InitStruct->COMP_Pol = 0; - #endif -} - -/** - * @brief Enable or disable the COMP peripheral. - * @note If the selected comparator is locked, enable/disable can't be performed. - * To unlock the configuration, perform a system reset. - * @param COMP_Selection: the selected comparator. - * This parameter can be one of the following values: - * @arg COMP_Selection_COMP1: COMP1 selected - * @arg COMP_Selection_COMP2: COMP2 selected - * @arg COMP_Selection_COMP3: COMP3 selected - * @param NewState: new state of the COMP peripheral. - * This parameter can be: ENABLE or DISABLE. - * @note When enabled, the comparator compares the non inverting input with - * the inverting input and the comparison result is available on comparator output. - * @note When disabled, the comparator doesn't perform comparison and the - * output level is low. - * @retval None - */ -void COMP_Cmd(uint32_t COMP_Selection, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_COMP_ALL_PERIPH(COMP_Selection)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if(COMP_Selection != COMP_Selection_COMP3) - { - if (NewState != DISABLE) - { - /* Enable the selected COMP peripheral */ - COMP->CSR |= (uint32_t) (1<CSR &= (uint32_t)(~((uint32_t)1<CSR2 |= (uint32_t) (1); - } - else - { - /* Disable the selected COMP peripheral */ - COMP->CSR2 &= (uint32_t)(~((uint32_t)1)); - } - #endif - - } -} - -/** - * @brief Return the output level (high or low) of the selected comparator. - * @note The output level depends on the selected polarity. - * @note If the polarity is not inverted: - * - Comparator output is low when the non-inverting input is at a lower - * voltage than the inverting input - * - Comparator output is high when the non-inverting input is at a higher - * voltage than the inverting input - * @note If the polarity is inverted: - * - Comparator output is high when the non-inverting input is at a lower - * voltage than the inverting input - * - Comparator output is low when the non-inverting input is at a higher - * voltage than the inverting input - * @param COMP_Selection: the selected comparator. - * This parameter can be one of the following values: - * @arg COMP_Selection_COMP1: COMP1 selected - * @arg COMP_Selection_COMP2: COMP2 selected - * @arg COMP_Selection_COMP3: COMP3 selected - * @retval Returns the selected comparator output level: low or high. - * - */ -uint32_t COMP_GetOutputLevel(uint32_t COMP_Selection) -{ - uint32_t compout = 0x0; - - /* Check the parameters */ - assert_param(IS_COMP_ALL_PERIPH(COMP_Selection)); - - if(COMP_Selection != COMP_Selection_COMP3) - { - /* Check if selected comparator output is high */ - if ((COMP->CSR & (COMP_CSR_COMP1OUT<CSR2 & COMP_CSR_COMP3OUT) != 0) - { - compout = COMP_OutputLevel_High; - } - else - { - compout = COMP_OutputLevel_Low; - } - #endif - } - - /* Return the comparator output level */ - return (uint32_t)(compout); -} - -/** - * @} - */ -/** - * @brief Enables or disables the window mode. - * @note In window mode, COMP1 and COMP2 non inverting inputs are connected - * together and only COMP1 non inverting input (PA1) can be used. - * @param NewState: new state of the window mode. - * This parameter can be : - * @arg ENABLE: COMP1 and COMP2 non inverting inputs are connected together. - * @arg DISABLE: OMP1 and COMP2 non inverting inputs are disconnected. - * @retval None - */ -void COMP_WindowCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the window mode */ - COMP->CSR |= (uint32_t) COMP_CSR_WNDWEN; - } - else - { - /* Disable the window mode */ - COMP->CSR &= (uint32_t)(~COMP_CSR_WNDWEN); - } -} - -/** - * @} - */ -/** - * @brief Lock the selected comparator (COMP1/COMP2) configuration. - * @note Locking the configuration means that all control bits are read-only. - * To unlock the comparator configuration, perform a system reset. - * @param COMP_Selection: selects the comparator to be locked - * This parameter can be a value of the following values: - * @arg COMP_Selection_COMP1: COMP1 configuration is locked. - * @arg COMP_Selection_COMP2: COMP2 configuration is locked. - * @arg COMP_Selection_COMP3: COMP3 configuration is locked. - * @retval None - */ -void COMP_LockConfig(uint32_t COMP_Selection) -{ - /* Check the parameter */ - assert_param(IS_COMP_ALL_PERIPH(COMP_Selection)); - - if(COMP_Selection != COMP_Selection_COMP3) - { - /* Set the lock bit corresponding to selected comparator */ - COMP->CSR |= (uint32_t) (COMP_CSR_NCOMPLOCK<CSR2 |= (uint32_t) (COMP_CSR_COMP3LOCK); - #endif - } -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT FMD *****END OF FILE****/ diff --git a/bsp/ft32/libraries/FT32F0xx/FT32F0xx_Driver/Src/ft32f0xx_crc.c b/bsp/ft32/libraries/FT32F0xx/FT32F0xx_Driver/Src/ft32f0xx_crc.c deleted file mode 100644 index df21a888731..00000000000 --- a/bsp/ft32/libraries/FT32F0xx/FT32F0xx_Driver/Src/ft32f0xx_crc.c +++ /dev/null @@ -1,261 +0,0 @@ -/** - ****************************************************************************** - * @file ft32f0xx_crc.c - * @author FMD AE - * @brief This file provides firmware functions to manage the following - * functionalities of CRC computation unit peripheral: - * + Configuration of the CRC computation unit - * + CRC computation of one/many 32-bit data - * + CRC Independent register (IDR) access - * @version V1.0.0 - * @data 2021-07-01 - ****************************************************************************** - */ - - -/* Includes ------------------------------------------------------------------*/ -#include "ft32f0xx_crc.h" - -/** - * @brief Deinitializes CRC peripheral registers to their default reset values. - * @param None - * @retval None - */ -void CRC_DeInit(void) -{ - /* Set DR register to reset value */ - CRC->DR = 0xFFFFFFFF; - - /* Reset IDR register */ - CRC->IDR = 0x00; - - /* Set INIT register to reset value */ - CRC->INIT = 0xFFFFFFFF; - - /* Reset the CRC calculation unit */ - CRC->CR = CRC_CR_RESET; -} - -/** - * @brief Resets the CRC calculation unit and sets INIT register content in DR register. - * @param None - * @retval None - */ -void CRC_ResetDR(void) -{ - /* Reset CRC generator */ - CRC->CR |= CRC_CR_RESET; -} - -/** - * @brief Selects the polynomial size. This function is only applicable for - * FT32F072 devices. - * @param CRC_PolSize: Specifies the polynomial size. - * This parameter can be: - * @arg CRC_PolSize_7: 7-bit polynomial for CRC calculation - * @arg CRC_PolSize_8: 8-bit polynomial for CRC calculation - * @arg CRC_PolSize_16: 16-bit polynomial for CRC calculation - * @arg CRC_PolSize_32: 32-bit polynomial for CRC calculation - * @retval None - */ -//void CRC_PolynomialSizeSelect(uint32_t CRC_PolSize) -//{ -// uint32_t tmpcr = 0; - -// /* Check the parameter */ -// assert_param(IS_CRC_POL_SIZE(CRC_PolSize)); - -// /* Get CR register value */ -// tmpcr = CRC->CR; - -// /* Reset POL_SIZE bits */ -// tmpcr &= (uint32_t)~((uint32_t)CRC_CR_POLSIZE); -// /* Set the polynomial size */ -// tmpcr |= (uint32_t)CRC_PolSize; - -// /* Write to CR register */ -// CRC->CR = (uint32_t)tmpcr; -//} - -/** - * @brief Selects the reverse operation to be performed on input data. - * @param CRC_ReverseInputData: Specifies the reverse operation on input data. - * This parameter can be: - * @arg CRC_ReverseInputData_No: No reverse operation is performed - * @arg CRC_ReverseInputData_8bits: reverse operation performed on 8 bits - * @arg CRC_ReverseInputData_16bits: reverse operation performed on 16 bits - * @arg CRC_ReverseInputData_32bits: reverse operation performed on 32 bits - * @retval None - */ -void CRC_ReverseInputDataSelect(uint32_t CRC_ReverseInputData) -{ - uint32_t tmpcr = 0; - - /* Check the parameter */ - assert_param(IS_CRC_REVERSE_INPUT_DATA(CRC_ReverseInputData)); - - /* Get CR register value */ - tmpcr = CRC->CR; - - /* Reset REV_IN bits */ - tmpcr &= (uint32_t)~((uint32_t)CRC_CR_REV_IN); - /* Set the reverse operation */ - tmpcr |= (uint32_t)CRC_ReverseInputData; - - /* Write to CR register */ - CRC->CR = (uint32_t)tmpcr; -} - -/** - * @brief Enables or disable the reverse operation on output data. - * The reverse operation on output data is performed on 32-bit. - * @param NewState: new state of the reverse operation on output data. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void CRC_ReverseOutputDataCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable reverse operation on output data */ - CRC->CR |= CRC_CR_REV_OUT; - } - else - { - /* Disable reverse operation on output data */ - CRC->CR &= (uint32_t)~((uint32_t)CRC_CR_REV_OUT); - } -} - -/** - * @brief Initializes the INIT register. - * @note After resetting CRC calculation unit, CRC_InitValue is stored in DR register - * @param CRC_InitValue: Programmable initial CRC value - * @retval None - */ -void CRC_SetInitRegister(uint32_t CRC_InitValue) -{ - CRC->INIT = CRC_InitValue; -} - -/** - * @brief Initializes the polynomail coefficients. This function is only - * applicable for FT32F072 devices. - * @param CRC_Pol: Polynomial to be used for CRC calculation. - * @retval None - */ -void CRC_SetPolynomial(uint32_t CRC_Pol) -{ - // CRC->POL = CRC_Pol; -} - -/** - * @} - */ - -/** - * @brief Computes the 32-bit CRC of a given data word(32-bit). - * @param CRC_Data: data word(32-bit) to compute its CRC - * @retval 32-bit CRC - */ -uint32_t CRC_CalcCRC(uint32_t CRC_Data) -{ - CRC->DR = CRC_Data; - - return (CRC->DR); -} - -/** - * @brief Computes the 16-bit CRC of a given 16-bit data. - * @param CRC_Data: data half-word(16-bit) to compute its CRC - * @retval 16-bit CRC - */ -uint32_t CRC_CalcCRC16bits(uint16_t CRC_Data) -{ - *(uint16_t*)(CRC_BASE) = (uint16_t) CRC_Data; - - return (CRC->DR); -} - -/** - * @brief Computes the 8-bit CRC of a given 8-bit data. - * @param CRC_Data: 8-bit data to compute its CRC - * @retval 8-bit CRC - */ -uint32_t CRC_CalcCRC8bits(uint8_t CRC_Data) -{ - *(uint8_t*)(CRC_BASE) = (uint8_t) CRC_Data; - - return (CRC->DR); -} - -/** - * @brief Computes the 32-bit CRC of a given buffer of data word(32-bit). - * @param pBuffer: pointer to the buffer containing the data to be computed - * @param BufferLength: length of the buffer to be computed - * @retval 32-bit CRC - */ -uint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength) -{ - uint32_t index = 0; - - for(index = 0; index < BufferLength; index++) - { - CRC->DR = pBuffer[index]; - } - return (CRC->DR); -} - -/** - * @brief Returns the current CRC value. - * @param None - * @retval 32-bit CRC - */ -uint32_t CRC_GetCRC(void) -{ - return (CRC->DR); -} - -/** - * @} - */ -/** - * @brief Stores an 8-bit data in the Independent Data(ID) register. - * @param CRC_IDValue: 8-bit value to be stored in the ID register - * @retval None - */ -void CRC_SetIDRegister(uint8_t CRC_IDValue) -{ - CRC->IDR = CRC_IDValue; -} - -/** - * @brief Returns the 8-bit data stored in the Independent Data(ID) register - * @param None - * @retval 8-bit value of the ID register - */ -uint8_t CRC_GetIDRegister(void) -{ - return (uint8_t)(CRC->IDR); -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT FMD *****END OF FILE****/ diff --git a/bsp/ft32/libraries/FT32F0xx/FT32F0xx_Driver/Src/ft32f0xx_crs.c b/bsp/ft32/libraries/FT32F0xx/FT32F0xx_Driver/Src/ft32f0xx_crs.c deleted file mode 100644 index f0ed578869c..00000000000 --- a/bsp/ft32/libraries/FT32F0xx/FT32F0xx_Driver/Src/ft32f0xx_crs.c +++ /dev/null @@ -1,401 +0,0 @@ -/** - ****************************************************************************** - * @file ft32f0xx_crs.c - * @author FMD AE - * @brief This file provides firmware functions to manage the following - * functionalities of CRS peripheral : - * + Configuration of the CRS peripheral - * + Interrupts and flags management - * @version V1.0.0 - * @data 2021-07-01 - ****************************************************************************** - */ - - -/* Includes ------------------------------------------------------------------*/ -#include "ft32f0xx_crs.h" -#include "ft32f0xx_rcc.h" - - -/** @defgroup CRS - * @brief CRS driver modules - * @{ - */ - -/* CRS Flag Mask */ -#define FLAG_MASK ((uint32_t)0x700) - - -/** - * @brief Deinitializes CRS peripheral registers to their default reset values. - * @param None - * @retval None - */ -void CRS_DeInit(void) -{ - RCC_APB1PeriphResetCmd(RCC_APB1Periph_CRS, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_CRS, DISABLE); -} - -/** - * @brief Adjusts the Internal High Speed 48 oscillator (HSI 48) calibration value. - * @note The calibration is used to compensate for the variations in voltage - * and temperature that influence the frequency of the internal HSI48 RC. - * @note This function can be called only when the AUTOTRIMEN bit is reset. - * @param CRS_HSI48CalibrationValue: - * @retval None - */ -void CRS_AdjustHSI48CalibrationValue(uint8_t CRS_HSI48CalibrationValue) -{ - /* Clear TRIM[5:0] bits */ - CRS->CR &= ~CRS_CR_TRIM; - - /* Set the TRIM[5:0] bits according to CRS_HSI48CalibrationValue value */ - CRS->CR |= (uint32_t)((uint32_t)CRS_HSI48CalibrationValue << 8); - -} - -/** - * @brief Enables or disables the oscillator clock for frequency error counter. - * @note when the CEN bit is set the CRS_CFGR register becomes write-protected. - * @param NewState: new state of the frequency error counter. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void CRS_FrequencyErrorCounterCmd(FunctionalState NewState) -{ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - CRS->CR |= CRS_CR_CEN; - } - else - { - CRS->CR &= ~CRS_CR_CEN; - } -} - -/** - * @brief Enables or disables the automatic hardware adjustement of TRIM bits. - * @note When the AUTOTRIMEN bit is set the CRS_CFGR register becomes write-protected. - * @param NewState: new state of the automatic trimming. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void CRS_AutomaticCalibrationCmd(FunctionalState NewState) -{ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - CRS->CR |= CRS_CR_AUTOTRIMEN; - } -else - { - CRS->CR &= ~CRS_CR_AUTOTRIMEN; - } -} - -/** - * @brief Generate the software synchronization event - * @param None - * @retval None - */ -void CRS_SoftwareSynchronizationGenerate(void) -{ - CRS->CR |= CRS_CR_SWSYNC; -} - -/** - * @brief Adjusts the Internal High Speed 48 oscillator (HSI 48) calibration value. - * @note The calibration is used to compensate for the variations in voltage - * and temperature that influence the frequency of the internal HSI48 RC. - * @note This function can be called only when the CEN bit is reset. - * @param CRS_ReloadValue: specifies the HSI calibration trimming value. - * This parameter must be a number between 0 and . - * @retval None - */ -void CRS_FrequencyErrorCounterReload(uint32_t CRS_ReloadValue) -{ - - /* Clear RELOAD[15:0] bits */ - CRS->CFGR &= ~CRS_CFGR_RELOAD; - - /* Set the RELOAD[15:0] bits according to CRS_ReloadValue value */ - CRS->CFGR |= (uint32_t)CRS_ReloadValue; - -} - -/** - * @brief - * @note This function can be called only when the CEN bit is reset. - * @param CRS_ErrorLimitValue: specifies the HSI calibration trimming value. - * This parameter must be a number between 0 and . - * @retval None - */ -void CRS_FrequencyErrorLimitConfig(uint8_t CRS_ErrorLimitValue) -{ - /* Clear FELIM[7:0] bits */ - CRS->CFGR &= ~CRS_CFGR_FELIM; - - /* Set the FELIM[7:0] bits according to CRS_ErrorLimitValue value */ - CRS->CFGR |= (uint32_t)(CRS_ErrorLimitValue <<16); -} - -/** - * @brief - * @note This function can be called only when the CEN bit is reset. - * @param CRS_Prescaler: specifies the HSI calibration trimming value. - * This parameter can be one of the following values: - * @arg CRS_SYNC_Div1: - * @arg CRS_SYNC_Div2: - * @arg CRS_SYNC_Div4: - * @arg CRS_SYNC_Div8: - * @arg CRS_SYNC_Div16: - * @arg CRS_SYNC_Div32: - * @arg CRS_SYNC_Div64: - * @arg CRS_SYNC_Div128: - * @retval None - */ -void CRS_SynchronizationPrescalerConfig(uint32_t CRS_Prescaler) -{ - /* Check the parameters */ - assert_param(IS_CRS_SYNC_DIV(CRS_Prescaler)); - - /* Clear SYNCDIV[2:0] bits */ - CRS->CFGR &= ~CRS_CFGR_SYNCDIV; - - /* Set the CRS_CFGR_SYNCDIV[2:0] bits according to CRS_Prescaler value */ - CRS->CFGR |= CRS_Prescaler; -} - -/** - * @brief - * @note This function can be called only when the CEN bit is reset. - * @param CRS_Source: . - * This parameter can be one of the following values: - * @arg CRS_SYNCSource_GPIO: - * @arg CRS_SYNCSource_LSE: - * @arg CRS_SYNCSource_USB: - * @retval None - */ -void CRS_SynchronizationSourceConfig(uint32_t CRS_Source) -{ - /* Check the parameters */ - assert_param(IS_CRS_SYNC_SOURCE(CRS_Source)); - - /* Clear SYNCSRC[1:0] bits */ - CRS->CFGR &= ~CRS_CFGR_SYNCSRC; - - /* Set the SYNCSRC[1:0] bits according to CRS_Source value */ - CRS->CFGR |= CRS_Source; -} - -/** - * @brief - * @note This function can be called only when the CEN bit is reset. - * @param CRS_Polarity: . - * This parameter can be one of the following values: - * @arg CRS_SYNCPolarity_Rising: - * @arg CRS_SYNCPolarity_Falling: - * @retval None - */ -void CRS_SynchronizationPolarityConfig(uint32_t CRS_Polarity) -{ - /* Check the parameters */ - assert_param(IS_CRS_SYNC_POLARITY(CRS_Polarity)); - - /* Clear SYNCSPOL bit */ - CRS->CFGR &= ~CRS_CFGR_SYNCPOL; - - /* Set the SYNCSPOL bits according to CRS_Polarity value */ - CRS->CFGR |= CRS_Polarity; -} - -/** - * @brief Returns the Relaod value. - * @param None - * @retval The reload value - */ -uint32_t CRS_GetReloadValue(void) -{ - return ((uint32_t)(CRS->CFGR & CRS_CFGR_RELOAD)); -} - -/** - * @brief Returns the HSI48 Calibration value. - * @param None - * @retval The reload value - */ -uint32_t CRS_GetHSI48CalibrationValue(void) -{ - return (((uint32_t)(CRS->CR & CRS_CR_TRIM)) >> 8); -} - -/** - * @brief Returns the frequency error capture. - * @param None - * @retval The frequency error capture value - */ -uint32_t CRS_GetFrequencyErrorValue(void) -{ - return ((uint32_t)(CRS->ISR & CRS_ISR_FECAP)); -} - -/** - * @brief Returns the frequency error direction. - * @param None - * @retval The frequency error direction. The returned value can be one - * of the following values: - * - 0x00: Up counting - * - 0x8000: Down counting - */ -uint32_t CRS_GetFrequencyErrorDirection(void) -{ - return ((uint32_t)(CRS->ISR & CRS_ISR_FEDIR)); -} - - -/** - * @brief Enables or disables the specified CRS interrupts. - * @param CRS_IT: specifies the RCC interrupt sources to be enabled or disabled. - * This parameter can be any combination of the following values: - * @arg CRS_IT_SYNCOK: - * @arg CRS_IT_SYNCWARN: - * @arg CRS_IT_ERR: - * @arg CRS_IT_ESYNC: - * @param NewState: new state of the specified CRS interrupts. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void CRS_ITConfig(uint32_t CRS_IT, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_CRS_IT(CRS_IT)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - CRS->CR |= CRS_IT; - } - else - { - CRS->CR &= ~CRS_IT; - } -} - -/** - * @brief Checks whether the specified CRS flag is set or not. - * @param CRS_FLAG: specifies the flag to check. - * This parameter can be one of the following values: - * @arg CRS_FLAG_SYNCOK: - * @arg CRS_FLAG_SYNCWARN: - * @arg CRS_FLAG_ERR: - * @arg CRS_FLAG_ESYNC: - * @arg CRS_FLAG_TRIMOVF: - * @arg CRS_FLAG_SYNCERR: - * @arg CRS_FLAG_SYNCMISS: - * @retval The new state of CRS_FLAG (SET or RESET). - */ -FlagStatus CRS_GetFlagStatus(uint32_t CRS_FLAG) -{ - /* Check the parameters */ - assert_param(IS_CRS_FLAG(CRS_FLAG)); - - return ((FlagStatus)(CRS->ISR & CRS_FLAG)); -} - -/** - * @brief Clears the CRS specified FLAG. - * @param CRS_FLAG: specifies the flag to check. - * This parameter can be one of the following values: - * @arg CRS_FLAG_SYNCOK: - * @arg CRS_FLAG_SYNCWARN: - * @arg CRS_FLAG_ERR: - * @arg CRS_FLAG_ESYNC: - * @arg CRS_FLAG_TRIMOVF: - * @arg CRS_FLAG_SYNCERR: - * @arg CRS_FLAG_SYNCMISS: - * @retval None - */ -void CRS_ClearFlag(uint32_t CRS_FLAG) -{ - /* Check the parameters */ - assert_param(IS_CRS_FLAG(CRS_FLAG)); - - if ((CRS_FLAG & FLAG_MASK)!= 0) - { - CRS->ICR |= CRS_ICR_ERRC; - } - else - { - CRS->ICR |= CRS_FLAG; - } -} - -/** - * @brief Checks whether the specified CRS IT pending bit is set or not. - * @param CRS_IT: specifies the IT pending bit to check. - * This parameter can be one of the following values: - * @arg CRS_IT_SYNCOK: - * @arg CRS_IT_SYNCWARN: - * @arg CRS_IT_ERR: - * @arg CRS_IT_ESYNC: - * @arg CRS_IT_TRIMOVF: - * @arg CRS_IT_SYNCERR: - * @arg CRS_IT_SYNCMISS: - * @retval The new state of CRS_IT (SET or RESET). - */ -ITStatus CRS_GetITStatus(uint32_t CRS_IT) -{ - /* Check the parameters */ - assert_param(IS_CRS_GET_IT(CRS_IT)); - - return ((ITStatus)(CRS->ISR & CRS_IT)); -} - -/** - * @brief Clears the CRS specified IT pending bi. - * @param CRS_FLAG: specifies the IT pending bi to clear. - * This parameter can be one of the following values: - * @arg CRS_IT_SYNCOK: - * @arg CRS_IT_SYNCWARN: - * @arg CRS_IT_ERR: - * @arg CRS_IT_ESYNC: - * @arg CRS_IT_TRIMOVF: - * @arg CRS_IT_SYNCERR: - * @arg CRS_IT_SYNCMISS: - * @retval None - */ -void CRS_ClearITPendingBit(uint32_t CRS_IT) -{ - /* Check the parameters */ - assert_param(IS_CRS_CLEAR_IT(CRS_IT)); - - if ((CRS_IT & FLAG_MASK)!= 0) - { - CRS->ICR |= CRS_ICR_ERRC; - } - else - { - CRS->ICR |= CRS_IT; - } -} -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT FMD *****END OF FILE****/ diff --git a/bsp/ft32/libraries/FT32F0xx/FT32F0xx_Driver/Src/ft32f0xx_dac.c b/bsp/ft32/libraries/FT32F0xx/FT32F0xx_Driver/Src/ft32f0xx_dac.c deleted file mode 100644 index e91068f090f..00000000000 --- a/bsp/ft32/libraries/FT32F0xx/FT32F0xx_Driver/Src/ft32f0xx_dac.c +++ /dev/null @@ -1,82 +0,0 @@ -/** - ****************************************************************************** - * @file ft32f0xx_dac.c - * @author FMD AE - * @brief This file provides firmware functions to manage the following - * functionalities of DAC peripheral - * @version V1.0.0 - * @data 2021-07-01 - ****************************************************************************** - */ -/* Includes ------------------------------------------------------------------*/ -#include "ft32f0xx_dac.h" - -/** - * - */ -void DAC_Ref_Config(uint32_t DAC_RefSel) -{ - uint32_t tmpreg = 0; - - assert_param(IS_DAC_REF_SEL(DAC_RefSel)); - - tmpreg = DAC->CTRL; - tmpreg &= ~DAC_CTRL_REF_SEL; - tmpreg |= DAC_RefSel; - - DAC->CTRL |= tmpreg; -} -/** - * @Parame - */ -void DAC_Cmd(FunctionalState NewState) -{ - if(NewState != DISABLE) - { - DAC->CTRL |= DAC_CTRL_EN; - } - else - { - DAC->CTRL &= ~DAC_CTRL_EN; - } -} - - -/** - * @brief Set the specified data holding register value for DAC channel1. - * @param DAC_Align: no use. - * @param Data: Data to be loaded in the selected data DAC1DATA register. 7BIT - * @retval None - */ -void DAC_SetChannel1Data(uint32_t DAC_Align, uint8_t Data) -{ - /* Check the parameters */ - assert_param(IS_DAC_DATA(Data)); - - DAC->DATA1 = (uint32_t)Data; -} - -void DAC_SetChannel2Data(uint32_t DAC_Align, uint8_t Data) -{ - /* Check the parameters */ - assert_param(IS_DAC_DATA(Data)); - - DAC->DATA2 = (uint32_t)Data; -} - - - -/** - * @Parame - * - */ -uint8_t DAC_Read_Reg(uint8_t DAC_Register) -{ - __IO uint32_t tmp = 0; - - tmp = (uint32_t)DAC_BASE; - tmp += DAC_Register; - - /* Return the selected register value */ - return (uint8_t)(*(__IO uint32_t *) tmp); -} diff --git a/bsp/ft32/libraries/FT32F0xx/FT32F0xx_Driver/Src/ft32f0xx_debug.c b/bsp/ft32/libraries/FT32F0xx/FT32F0xx_Driver/Src/ft32f0xx_debug.c deleted file mode 100644 index 81a296d27d3..00000000000 --- a/bsp/ft32/libraries/FT32F0xx/FT32F0xx_Driver/Src/ft32f0xx_debug.c +++ /dev/null @@ -1,152 +0,0 @@ -/** - ****************************************************************************** - * @file ft32f0xx_debug.c - * @author FMD AE - * @brief This file provides firmware functions to manage the following - * functionalities of the Debug MCU (DBGMCU) peripheral: - * + Device and Revision ID management - * + Peripherals Configuration - * @version V1.0.0 - * @data 2021-07-01 - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "ft32f0xx_debug.h" - - -#define IDCODE_DEVID_MASK ((uint32_t)0x00000FFF) - - - -/** - * @brief Returns the device revision identifier. - * @param None - * @retval Device revision identifier - */ -uint32_t DBGMCU_GetREVID(void) -{ - return(DBGMCU->IDCODE >> 16); -} - -/** - * @brief Returns the device identifier. - * @param None - * @retval Device identifier - */ -uint32_t DBGMCU_GetDEVID(void) -{ - return(DBGMCU->IDCODE & IDCODE_DEVID_MASK); -} - -/** - * @} - */ -/** - * @brief Configures low power mode behavior when the MCU is in Debug mode. - * @param DBGMCU_Periph: specifies the low power mode. - * This parameter can be any combination of the following values: - * @arg DBGMCU_STOP: Keep debugger connection during STOP mode - * @arg DBGMCU_STANDBY: Keep debugger connection during STANDBY mode - * @param NewState: new state of the specified low power mode in Debug mode. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_DBGMCU_PERIPH(DBGMCU_Periph)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - DBGMCU->CR |= DBGMCU_Periph; - } - else - { - DBGMCU->CR &= ~DBGMCU_Periph; - } -} - - -/** - * @brief Configures APB1 peripheral behavior when the MCU is in Debug mode. - * @param DBGMCU_Periph: specifies the APB1 peripheral. - * This parameter can be any combination of the following values: - * @arg DBGMCU_TIM2_STOP: TIM2 counter stopped when Core is halted - * @arg DBGMCU_TIM3_STOP: TIM3 counter stopped when Core is halted - * @arg DBGMCU_TIM6_STOP: TIM6 counter stopped when Core is halted - * @arg DBGMCU_TIM7_STOP: TIM7 counter stopped when Core is halted - * @arg DBGMCU_TIM14_STOP: TIM14 counter stopped when Core is halted - * @arg DBGMCU_RTC_STOP: RTC Calendar and Wakeup counter stopped - * when Core is halted. - * @arg DBGMCU_WWDG_STOP: Debug WWDG stopped when Core is halted - * @arg DBGMCU_IWDG_STOP: Debug IWDG stopped when Core is halted - * @arg DBGMCU_I2C1_SMBUS_TIMEOUT: I2C1 SMBUS timeout mode stopped - * when Core is halted - * @arg DBGMCU_CAN1_STOP: Debug CAN1 stopped when Core is halted - * @param NewState: new state of the specified APB1 peripheral in Debug mode. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void DBGMCU_APB1PeriphConfig(uint32_t DBGMCU_Periph, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_DBGMCU_APB1PERIPH(DBGMCU_Periph)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - DBGMCU->APB1FZ |= DBGMCU_Periph; - } - else - { - DBGMCU->APB1FZ &= ~DBGMCU_Periph; - } -} - -/** - * @brief Configures APB2 peripheral behavior when the MCU is in Debug mode. - * @param DBGMCU_Periph: specifies the APB2 peripheral. - * This parameter can be any combination of the following values: - * @arg DBGMCU_TIM1_STOP: TIM1 counter stopped when Core is halted - * @arg DBGMCU_TIM15_STOP: TIM15 counter stopped when Core is halted - * @arg DBGMCU_TIM16_STOP: TIM16 counter stopped when Core is halted - * @arg DBGMCU_TIM17_STOP: TIM17 counter stopped when Core is halted - * @param NewState: new state of the specified APB2 peripheral in Debug mode. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void DBGMCU_APB2PeriphConfig(uint32_t DBGMCU_Periph, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_DBGMCU_APB2PERIPH(DBGMCU_Periph)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - DBGMCU->APB2FZ |= DBGMCU_Periph; - } - else - { - DBGMCU->APB2FZ &= ~DBGMCU_Periph; - } -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT FMD *****END OF FILE****/ diff --git a/bsp/ft32/libraries/FT32F0xx/FT32F0xx_Driver/Src/ft32f0xx_div.c b/bsp/ft32/libraries/FT32F0xx/FT32F0xx_Driver/Src/ft32f0xx_div.c deleted file mode 100644 index 92f4ab12890..00000000000 --- a/bsp/ft32/libraries/FT32F0xx/FT32F0xx_Driver/Src/ft32f0xx_div.c +++ /dev/null @@ -1,228 +0,0 @@ -/** - ****************************************************************************** - * @file FT32f0xx_div.c - * @author FMD AE - * @brief This file provides firmware functions to manage the following - * functionalities of the dividor peripheral - * applicable only on FT32F072xB devices: - * + Comparators configuration - * + Window mode control - * @version V1.0.0 - * @data 2021-12-01 - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "ft32f0xx_div.h" - -/** - * @brief Enable or disable the OPA peripheral. - * @note If the selected comparator is locked, enable/disable can't be performed. - * To unlock the configuration, perform a system reset. - * @param OPA_Selection: the selected comparator. - * This parameter can be one of the following values: - * @arg NOPA_Selection_OPA: OPA1 selected - * @arg POPA_Selection_OPA: OPA2 selected - * @param NewState: new state of the OPA peripheral. - * This parameter can be: ENABLE or DISABLE. - * @note When enabled, the comparator compares the non inverting input with - * the inverting input and the comparison result is available on comparator output. - * @note When disabled, the comparator doesn't perform comparison and the - * output level is low. - * @retval None - */ -DIV_Status DivS32ByS16(DIV_ResultTypeDef* pResult,int32_t divedent,int16_t dividor) -{ - DIV_Status status = DIV_COMPLETE; - DIV->DID = divedent; - DIV->DIS = dividor; - while(DIV_GetFlagStatus(DIV_FLAG_BUSY) == SET); - if(DIV_GetFlagStatus(DIV_FLAG_DIV0ERR) == SET) - { - status = DIV_ERROR_DIV0ERR; - } - else if(DIV_GetFlagStatus(DIV_FLAG_DIVOV) == SET) - { - status = DIV_ERROR_DIV0V; - } - else - { - pResult -> DIV_quotient = DIV-> QUO; - pResult -> DIV_remainder = DIV-> REM; - } - return status; -} - -/** @defgroup DIV Interrupts and flags management functions - * @brief Interrupts and flags management functions. - * -@verbatim - =============================================================================== - ##### Interrupts and flags management functions ##### - =============================================================================== - [..] This section provides functions allowing to configure the DIV Interrupts - and get the status and clear flags and Interrupts pending bits. - - *** Flags for DIV status *** - ====================================================== - [..] - (+)Flags : - (##) DIV_FLAG_DIV0ERR : This flag is set after the ADC has been enabled (bit ADEN=1) - and when the ADC reaches a state where it is ready to accept conversion requests - (##) DIV_FLAG_DIVOV : This flag is set by software to enable the ADC. - The DIV will be effectively ready to operate once the ADRDY flag has been set. - (##) DIV_FLAG_BUSY : This flag is cleared once the ADC is effectively - disabled. - (+)Interrupts - (##) DIV_IT_DIV0ERR : specifies the interrupt source for ADC ready event. - (##) DIV_IT_DIVOV : specifies the interrupt source for ADC ready event. - - [..] The user should identify which mode will be used in his application to - manage the ADC controller events: Polling mode or Interrupt mode. - - [..] In the Polling Mode it is advised to use the following functions: - (+) DIV_GetFlagStatus() : to check if flags events occur. - (+) DIV_ClearFlag() : to clear the flags events. - - [..] In the Interrupt Mode it is advised to use the following functions: - (+) DIV_ITConfig() : to enable or disable the interrupt source. - (+) DIV_GetITStatus() : to check if Interrupt occurs. - (+) DIV_ClearITPendingBit() : to clear the Interrupt pending Bit - (corresponding Flag). - -@endverbatim - * @{ - */ -/** - * @brief Enables or disables the specified DIV interrupts. - * @param DIV_IT: specifies the DIV interrupt sources to be enabled or disabled. - * This parameter can be one of the following values: - * @arg DIV_IT_DIV0ERR: Divide By Zero Exception - * @arg DIV_IT_DIVOV: Overflow interrupt - * @param NewState: new state of the specified DIV interrupts. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void DIV_ITConfig(uint32_t DIV_IT, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - assert_param(IS_DIV_CONFIG_IT(DIV_IT)); - - if (NewState != DISABLE) - { - /* Enable the selected DIV interrupts */ - DIV->SC |= DIV_IT; - } - else - { - /* Disable the selected DIV interrupts */ - DIV->SC &= (~(uint32_t)DIV_IT); - } -} - -/** - * @brief Checks whether the specified DIV flag is set or not. - * @param DIV_FLAG: specifies the flag to check. - * This parameter can be one of the following values: - * @arg DIV_FLAG_DIV0ERR: Divide By Zero Exception flag - * @arg DIV_FLAG_DIVOV: Overflow flag - * @arg DIV_FLAG_BUSY: Busy flag - * @retval The new state of DIV_FLAG (SET or RESET). - */ -FlagStatus DIV_GetFlagStatus(uint32_t DIV_FLAG) -{ - FlagStatus bitstatus = RESET; - - /* Check the parameters */ - assert_param(IS_DIV_GET_FLAG(DIV_FLAG)); - - /* Check the status of the specified DIV flag */ - if ((DIV->SC & DIV_FLAG) != (uint32_t)RESET) - { - /* DIV_FLAG is set */ - bitstatus = SET; - } - else - { - /* DIV_FLAG is reset */ - bitstatus = RESET; - } - /* Return the DIV_FLAG status */ - return bitstatus; -} - -/** - * @brief Clears the DIV's pending flags. - * @param DIV_FLAG: specifies the flag to clear. - * This parameter can be any combination of the following values: - * @arg DIV_FLAG_DIV0ERRC: Divide By Zero Exception flag - * @arg DIV_FLAG_DIVOVC: Overflow flag - * @retval None - */ -void DIV_ClearFlag(uint32_t DIV_FLAG) -{ - /* Check the parameters */ - assert_param(IS_DIV_CLEAR_FLAG(DIV_FLAG)); - /* Clear the selected DIV flags */ - DIV->SC |= (uint32_t)(DIV_FLAG<<8); -} - -/** - * @brief Checks whether the specified DIV interrupt has occurred or not. - * @param DIV_IT: specifies the DIV interrupt source to check. - * This parameter can be one of the following values: - * @arg DIV_IT_DIV0ERR: Divide By Zero Exception - * @arg DIV_IT_DIVOV: Overflow interrupt - * @retval The new state of DIV_IT (SET or RESET). - */ -ITStatus DIV_GetITStatus(uint32_t DIV_IT) -{ - ITStatus bitstatus = RESET; - uint32_t enablestatus = 0; - - /* Check the parameters */ - assert_param(IS_DIV_GET_IT(DIV_IT)); - - /* Get the DIV_IT enable bit status */ - enablestatus = (uint32_t)((DIV->SC>>1) & DIV_IT); - - /* Check the status of the specified DIV interrupt */ - if (((uint32_t)(DIV->SC & DIV_IT) != (uint32_t)RESET) && (enablestatus != (uint32_t)RESET)) - { - /* DIV_IT is set */ - bitstatus = SET; - } - else - { - /* DIV_IT is reset */ - bitstatus = RESET; - } - /* Return the DIV_IT status */ - return bitstatus; -} - -/** - * @brief Clears the DIV's interrupt pending bits. - * @param DIV: where x can be 1 to select the DIV1 peripheral. - * @param DIV_IT: specifies the DIV interrupt pending bit to clear. - * This parameter can be one of the following values: - * @arg DIV_IT_DIV0ERR: Divide By Zero Exception - * @arg DIV_IT_DIVOV: Overflow interrupt - * @retval None - */ -void DIV_ClearITPendingBit(uint32_t DIV_IT) -{ - /* Check the parameters */ - assert_param(IS_DIV_CLEAR_IT(DIV_IT)); - - /* Clear the selected DIV interrupt pending bits */ - DIV->SC |= (uint32_t)(DIV_IT<<8); -} - -/** - * @} - */ - -/************************ (C) COPYRIGHT FMD *****END OF FILE****/ - diff --git a/bsp/ft32/libraries/FT32F0xx/FT32F0xx_Driver/Src/ft32f0xx_dma.c b/bsp/ft32/libraries/FT32F0xx/FT32F0xx_Driver/Src/ft32f0xx_dma.c deleted file mode 100644 index 710938e0c7a..00000000000 --- a/bsp/ft32/libraries/FT32F0xx/FT32F0xx_Driver/Src/ft32f0xx_dma.c +++ /dev/null @@ -1,649 +0,0 @@ -/** - ****************************************************************************** - * @file ft32f0xx_dma.c - * @author FMD AE - * @brief This file provides firmware functions to manage the following - * functionalities of the Direct Memory Access controller (DMA): - * + Initialization and Configuration - * + Data Counter - * + Interrupts and flags management - * @version V1.0.0 - * @data 2021-07-01 - ****************************************************************************** - */ - - -/* Includes ------------------------------------------------------------------*/ -#include "ft32f0xx_dma.h" - - -/** @defgroup DMA - * @brief DMA driver modules - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -#define CCR_CLEAR_MASK ((uint32_t)0xFFFF800F) /* DMA Channel config registers Masks */ -#define FLAG_Mask ((uint32_t)0x10000000) /* DMA2 FLAG mask */ - -/* DMA1 Channelx interrupt pending bit masks */ -#define DMA1_CHANNEL1_IT_MASK ((uint32_t)(DMA_ISR_GIF1 | DMA_ISR_TCIF1 | DMA_ISR_HTIF1 | DMA_ISR_TEIF1)) -#define DMA1_CHANNEL2_IT_MASK ((uint32_t)(DMA_ISR_GIF2 | DMA_ISR_TCIF2 | DMA_ISR_HTIF2 | DMA_ISR_TEIF2)) -#define DMA1_CHANNEL3_IT_MASK ((uint32_t)(DMA_ISR_GIF3 | DMA_ISR_TCIF3 | DMA_ISR_HTIF3 | DMA_ISR_TEIF3)) -#define DMA1_CHANNEL4_IT_MASK ((uint32_t)(DMA_ISR_GIF4 | DMA_ISR_TCIF4 | DMA_ISR_HTIF4 | DMA_ISR_TEIF4)) -#define DMA1_CHANNEL5_IT_MASK ((uint32_t)(DMA_ISR_GIF5 | DMA_ISR_TCIF5 | DMA_ISR_HTIF5 | DMA_ISR_TEIF5)) -#define DMA1_CHANNEL6_IT_MASK ((uint32_t)(DMA_ISR_GIF6 | DMA_ISR_TCIF6 | DMA_ISR_HTIF6 | DMA_ISR_TEIF6)) -#define DMA1_CHANNEL7_IT_MASK ((uint32_t)(DMA_ISR_GIF7 | DMA_ISR_TCIF7 | DMA_ISR_HTIF7 | DMA_ISR_TEIF7)) - -/* DMA2 Channelx interrupt pending bit masks:*/ -#define DMA2_CHANNEL1_IT_MASK ((uint32_t)(DMA_ISR_GIF1 | DMA_ISR_TCIF1 | DMA_ISR_HTIF1 | DMA_ISR_TEIF1)) -#define DMA2_CHANNEL2_IT_MASK ((uint32_t)(DMA_ISR_GIF2 | DMA_ISR_TCIF2 | DMA_ISR_HTIF2 | DMA_ISR_TEIF2)) -#define DMA2_CHANNEL3_IT_MASK ((uint32_t)(DMA_ISR_GIF3 | DMA_ISR_TCIF3 | DMA_ISR_HTIF3 | DMA_ISR_TEIF3)) -#define DMA2_CHANNEL4_IT_MASK ((uint32_t)(DMA_ISR_GIF4 | DMA_ISR_TCIF4 | DMA_ISR_HTIF4 | DMA_ISR_TEIF4)) -#define DMA2_CHANNEL5_IT_MASK ((uint32_t)(DMA_ISR_GIF5 | DMA_ISR_TCIF5 | DMA_ISR_HTIF5 | DMA_ISR_TEIF5)) - - - -/** - * @brief Deinitializes the DMAy Channelx registers to their default reset - * values. - * @param DMAy_Channelx: where y can be 1 to select the DMA and - * x can be 1 to 7 for DMA1 to select the DMA Channel. - * @note - * @retval None - */ -void DMA_DeInit(DMA_Channel_TypeDef* DMAy_Channelx) -{ - /* Check the parameters */ - assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx)); - - /* Disable the selected DMAy Channelx */ - DMAy_Channelx->CCR &= (uint16_t)(~DMA_CCR_EN); - - /* Reset DMAy Channelx control register */ - DMAy_Channelx->CCR = 0; - - /* Reset DMAy Channelx remaining bytes register */ - DMAy_Channelx->CNDTR = 0; - - /* Reset DMAy Channelx peripheral address register */ - DMAy_Channelx->CPAR = 0; - - /* Reset DMAy Channelx memory address register */ - DMAy_Channelx->CMAR = 0; - - if (DMAy_Channelx == DMA1_Channel1) - { - /* Reset interrupt pending bits for DMA1 Channel1 */ - DMA1->IFCR |= DMA1_CHANNEL1_IT_MASK; - } - else if (DMAy_Channelx == DMA1_Channel2) - { - /* Reset interrupt pending bits for DMA1 Channel2 */ - DMA1->IFCR |= DMA1_CHANNEL2_IT_MASK; - } - else if (DMAy_Channelx == DMA1_Channel3) - { - /* Reset interrupt pending bits for DMA1 Channel3 */ - DMA1->IFCR |= DMA1_CHANNEL3_IT_MASK; - } - else if (DMAy_Channelx == DMA1_Channel4) - { - /* Reset interrupt pending bits for DMA1 Channel4 */ - DMA1->IFCR |= DMA1_CHANNEL4_IT_MASK; - } - else if (DMAy_Channelx == DMA1_Channel5) - { - /* Reset interrupt pending bits for DMA1 Channel5 */ - DMA1->IFCR |= DMA1_CHANNEL5_IT_MASK; - } -// else if (DMAy_Channelx == DMA1_Channel6) -// { -// /* Reset interrupt pending bits for DMA1 Channel6 */ -// DMA1->IFCR |= DMA1_CHANNEL6_IT_MASK; -// } -// else if (DMAy_Channelx == DMA1_Channel7) -// { -// /* Reset interrupt pending bits for DMA1 Channel7 */ -// DMA1->IFCR |= DMA1_CHANNEL7_IT_MASK; -// } -} - -/** - * @brief Initializes the DMAy Channelx according to the specified parameters - * in the DMA_InitStruct. - * @param DMAy_Channelx: where y can be 1 to select the DMA and x can be 1 to 7 - * for DMA1 to select the DMA Channel and 1 to 5 for DMA2 to select the DMA Channel. - * @note - * @param DMA_InitStruct: pointer to a DMA_InitTypeDef structure that contains - * the configuration information for the specified DMA Channel. - * @retval None - */ -void DMA_Init(DMA_Channel_TypeDef* DMAy_Channelx, DMA_InitTypeDef* DMA_InitStruct) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx)); - assert_param(IS_DMA_DIR(DMA_InitStruct->DMA_DIR)); - assert_param(IS_DMA_BUFFER_SIZE(DMA_InitStruct->DMA_BufferSize)); - assert_param(IS_DMA_PERIPHERAL_INC_STATE(DMA_InitStruct->DMA_PeripheralInc)); - assert_param(IS_DMA_MEMORY_INC_STATE(DMA_InitStruct->DMA_MemoryInc)); - assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(DMA_InitStruct->DMA_PeripheralDataSize)); - assert_param(IS_DMA_MEMORY_DATA_SIZE(DMA_InitStruct->DMA_MemoryDataSize)); - assert_param(IS_DMA_MODE(DMA_InitStruct->DMA_Mode)); - assert_param(IS_DMA_PRIORITY(DMA_InitStruct->DMA_Priority)); - assert_param(IS_DMA_M2M_STATE(DMA_InitStruct->DMA_M2M)); - -/*--------------------------- DMAy Channelx CCR Configuration ----------------*/ - /* Get the DMAy_Channelx CCR value */ - tmpreg = DMAy_Channelx->CCR; - - /* Clear MEM2MEM, PL, MSIZE, PSIZE, MINC, PINC, CIRC and DIR bits */ - tmpreg &= CCR_CLEAR_MASK; - - /* Configure DMAy Channelx: data transfer, data size, priority level and mode */ - /* Set DIR bit according to DMA_DIR value */ - /* Set CIRC bit according to DMA_Mode value */ - /* Set PINC bit according to DMA_PeripheralInc value */ - /* Set MINC bit according to DMA_MemoryInc value */ - /* Set PSIZE bits according to DMA_PeripheralDataSize value */ - /* Set MSIZE bits according to DMA_MemoryDataSize value */ - /* Set PL bits according to DMA_Priority value */ - /* Set the MEM2MEM bit according to DMA_M2M value */ - tmpreg |= DMA_InitStruct->DMA_DIR | DMA_InitStruct->DMA_Mode | - DMA_InitStruct->DMA_PeripheralInc | DMA_InitStruct->DMA_MemoryInc | - DMA_InitStruct->DMA_PeripheralDataSize | DMA_InitStruct->DMA_MemoryDataSize | - DMA_InitStruct->DMA_Priority | DMA_InitStruct->DMA_M2M; - - /* Write to DMAy Channelx CCR */ - DMAy_Channelx->CCR = tmpreg; - -/*--------------------------- DMAy Channelx CNDTR Configuration --------------*/ - /* Write to DMAy Channelx CNDTR */ - DMAy_Channelx->CNDTR = DMA_InitStruct->DMA_BufferSize; - -/*--------------------------- DMAy Channelx CPAR Configuration ---------------*/ - /* Write to DMAy Channelx CPAR */ - DMAy_Channelx->CPAR = DMA_InitStruct->DMA_PeripheralBaseAddr; - -/*--------------------------- DMAy Channelx CMAR Configuration ---------------*/ - /* Write to DMAy Channelx CMAR */ - DMAy_Channelx->CMAR = DMA_InitStruct->DMA_MemoryBaseAddr; -} - -/** - * @brief Fills each DMA_InitStruct member with its default value. - * @param DMA_InitStruct: pointer to a DMA_InitTypeDef structure which will - * be initialized. - * @retval None - */ -void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct) -{ -/*-------------- Reset DMA init structure parameters values ------------------*/ - /* Initialize the DMA_PeripheralBaseAddr member */ - DMA_InitStruct->DMA_PeripheralBaseAddr = 0; - /* Initialize the DMA_MemoryBaseAddr member */ - DMA_InitStruct->DMA_MemoryBaseAddr = 0; - /* Initialize the DMA_DIR member */ - DMA_InitStruct->DMA_DIR = DMA_DIR_PeripheralSRC; - /* Initialize the DMA_BufferSize member */ - DMA_InitStruct->DMA_BufferSize = 0; - /* Initialize the DMA_PeripheralInc member */ - DMA_InitStruct->DMA_PeripheralInc = DMA_PeripheralInc_Disable; - /* Initialize the DMA_MemoryInc member */ - DMA_InitStruct->DMA_MemoryInc = DMA_MemoryInc_Disable; - /* Initialize the DMA_PeripheralDataSize member */ - DMA_InitStruct->DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte; - /* Initialize the DMA_MemoryDataSize member */ - DMA_InitStruct->DMA_MemoryDataSize = DMA_MemoryDataSize_Byte; - /* Initialize the DMA_Mode member */ - DMA_InitStruct->DMA_Mode = DMA_Mode_Normal; - /* Initialize the DMA_Priority member */ - DMA_InitStruct->DMA_Priority = DMA_Priority_Low; - /* Initialize the DMA_M2M member */ - DMA_InitStruct->DMA_M2M = DMA_M2M_Disable; -} - -/** - * @brief Enables or disables the specified DMAy Channelx. - * @param DMAy_Channelx: where y can be 1 to select the DMA and x can be 1 to 7 - * for DMA1 to select the DMA Channel and 1 to 5 for DMA2 to select the DMA Channel. - * @param NewState: new state of the DMAy Channelx. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void DMA_Cmd(DMA_Channel_TypeDef* DMAy_Channelx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the selected DMAy Channelx */ - DMAy_Channelx->CCR |= DMA_CCR_EN; - } - else - { - /* Disable the selected DMAy Channelx */ - DMAy_Channelx->CCR &= (uint16_t)(~DMA_CCR_EN); - } -} -/** - * @} - */ - - - -/** - * @brief Sets the number of data units in the current DMAy Channelx transfer. - * @param DMAy_Channelx: where y can be 1 to select the DMA and x can be 1 to 7 - * for DMA1 to select the DMA Channel and 1 to 5 for DMA2 to select the DMA Channel. - - * @param DataNumber: The number of data units in the current DMAy Channelx - * transfer. - * @note This function can only be used when the DMAy_Channelx is disabled. - * @retval None. - */ -void DMA_SetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx, uint16_t DataNumber) -{ - /* Check the parameters */ - assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx)); - -/*--------------------------- DMAy Channelx CNDTR Configuration --------------*/ - /* Write to DMAy Channelx CNDTR */ - DMAy_Channelx->CNDTR = DataNumber; -} - -/** - * @brief Returns the number of remaining data units in the current - * DMAy Channelx transfer. - * @param DMAy_Channelx: where y can be 1 to select the DMA and x can be 1 to 7 - * for DMA1 to select the DMA Channel and 1 to 5 for DMA2 to select the DMA Channel. - * @retval The number of remaining data units in the current DMAy Channelx - * transfer. - */ -uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx) -{ - /* Check the parameters */ - assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx)); - /* Return the number of remaining data units for DMAy Channelx */ - return ((uint16_t)(DMAy_Channelx->CNDTR)); -} - -/** - * @} - */ - - -/** - * @brief Enables or disables the specified DMAy Channelx interrupts. - * @param DMAy_Channelx: where y can be 1 to select the DMA and x can be 1 to 7 - * for DMA1 to select the DMA Channel and 1 to 5 for DMA2 to select the DMA Channel. - * @param DMA_IT: specifies the DMA interrupts sources to be enabled - * or disabled. - * This parameter can be any combination of the following values: - * @arg DMA_IT_TC: Transfer complete interrupt mask - * @arg DMA_IT_HT: Half transfer interrupt mask - * @arg DMA_IT_TE: Transfer error interrupt mask - * @param NewState: new state of the specified DMA interrupts. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void DMA_ITConfig(DMA_Channel_TypeDef* DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx)); - assert_param(IS_DMA_CONFIG_IT(DMA_IT)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the selected DMA interrupts */ - DMAy_Channelx->CCR |= DMA_IT; - } - else - { - /* Disable the selected DMA interrupts */ - DMAy_Channelx->CCR &= ~DMA_IT; - } -} - -/** - * @brief Checks whether the specified DMAy Channelx flag is set or not. - * @param DMA_FLAG: specifies the flag to check. - * This parameter can be one of the following values: - * @arg DMA1_FLAG_GL1: DMA1 Channel1 global flag. - * @arg DMA1_FLAG_TC1: DMA1 Channel1 transfer complete flag. - * @arg DMA1_FLAG_HT1: DMA1 Channel1 half transfer flag. - * @arg DMA1_FLAG_TE1: DMA1 Channel1 transfer error flag. - * @arg DMA1_FLAG_GL2: DMA1 Channel2 global flag. - * @arg DMA1_FLAG_TC2: DMA1 Channel2 transfer complete flag. - * @arg DMA1_FLAG_HT2: DMA1 Channel2 half transfer flag. - * @arg DMA1_FLAG_TE2: DMA1 Channel2 transfer error flag. - * @arg DMA1_FLAG_GL3: DMA1 Channel3 global flag. - * @arg DMA1_FLAG_TC3: DMA1 Channel3 transfer complete flag. - * @arg DMA1_FLAG_HT3: DMA1 Channel3 half transfer flag. - * @arg DMA1_FLAG_TE3: DMA1 Channel3 transfer error flag. - * @arg DMA1_FLAG_GL4: DMA1 Channel4 global flag. - * @arg DMA1_FLAG_TC4: DMA1 Channel4 transfer complete flag. - * @arg DMA1_FLAG_HT4: DMA1 Channel4 half transfer flag. - * @arg DMA1_FLAG_TE4: DMA1 Channel4 transfer error flag. - * @arg DMA1_FLAG_GL5: DMA1 Channel5 global flag. - * @arg DMA1_FLAG_TC5: DMA1 Channel5 transfer complete flag. - * @arg DMA1_FLAG_HT5: DMA1 Channel5 half transfer flag. - * @arg DMA1_FLAG_TE5: DMA1 Channel5 transfer error flag. - * @arg DMA1_FLAG_GL6: DMA1 Channel6 global flag - * @arg DMA1_FLAG_TC6: DMA1 Channel6 transfer complete flag - * @arg DMA1_FLAG_HT6: DMA1 Channel6 half transfer flag - * @arg DMA1_FLAG_TE6: DMA1 Channel6 transfer error flag - * @arg DMA1_FLAG_GL7: DMA1 Channel7 global flag - * @arg DMA1_FLAG_TC7: DMA1 Channel7 transfer complete flag - * @arg DMA1_FLAG_HT7: DMA1 Channel7 half transfer flag - * @arg DMA1_FLAG_TE7: DMA1 Channel7 transfer error flag - * @arg DMA2_FLAG_GL1: DMA2 Channel1 global flag - * @arg DMA2_FLAG_TC1: DMA2 Channel1 transfer complete flag - * @arg DMA2_FLAG_HT1: DMA2 Channel1 half transfer flag - * @arg DMA2_FLAG_TE1: DMA2 Channel1 transfer error flag - * @arg DMA2_FLAG_GL2: DMA2 Channel2 global flag - * @arg DMA2_FLAG_TC2: DMA2 Channel2 transfer complete flag - * @arg DMA2_FLAG_HT2: DMA2 Channel2 half transfer flag - * @arg DMA2_FLAG_TE2: DMA2 Channel2 transfer error flag - * @arg DMA2_FLAG_GL3: DMA2 Channel3 global flag - * @arg DMA2_FLAG_TC3: DMA2 Channel3 transfer complete flag - * @arg DMA2_FLAG_HT3: DMA2 Channel3 half transfer flag - * @arg DMA2_FLAG_TE3: DMA2 Channel3 transfer error flag - * @arg DMA2_FLAG_GL4: DMA2 Channel4 global flag - * @arg DMA2_FLAG_TC4: DMA2 Channel4 transfer complete flag - * @arg DMA2_FLAG_HT4: DMA2 Channel4 half transfer flag - * @arg DMA2_FLAG_TE4: DMA2 Channel4 transfer error flag - * @arg DMA2_FLAG_GL5: DMA2 Channel5 global flag - * @arg DMA2_FLAG_TC5: DMA2 Channel5 transfer complete flag - * @arg DMA2_FLAG_HT5: DMA2 Channel5 half transfer flag - * @arg DMA2_FLAG_TE5: DMA2 Channel5 transfer error flag - * @note The Global flag (DMAy_FLAG_GLx) is set whenever any of the ot - * relative to the same channel is set (Transfer Complete, Half-transfer - * Complete or Transfer Error flags: DMAy_FLAG_TCx, DMAy_FLAG_HTx or - * DMAy_FLAG_TEx). - * - * @retval The new state of DMA_FLAG (SET or RESET). - */ -FlagStatus DMA_GetFlagStatus(uint32_t DMAy_FLAG) -{ - FlagStatus bitstatus = RESET; - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_DMA_GET_FLAG(DMAy_FLAG)); - - /* Calculate the used DMAy */ - if ((DMAy_FLAG & FLAG_Mask) != (uint32_t)RESET) - { - ; - } - else - { - /* Get DMA1 ISR register value */ - tmpreg = DMA1->ISR ; - } - - /* Check the status of the specified DMAy flag */ - if ((tmpreg & DMAy_FLAG) != (uint32_t)RESET) - { - /* DMAy_FLAG is set */ - bitstatus = SET; - } - else - { - /* DMAy_FLAG is reset */ - bitstatus = RESET; - } - - /* Return the DMAy_FLAG status */ - return bitstatus; -} - -/** - * @brief Clears the DMAy Channelx's pending flags. - * @param DMA_FLAG: specifies the flag to clear. - * This parameter can be any combination (for the same DMA) of the following values: - * @arg DMA1_FLAG_GL1: DMA1 Channel1 global flag. - * @arg DMA1_FLAG_TC1: DMA1 Channel1 transfer complete flag. - * @arg DMA1_FLAG_HT1: DMA1 Channel1 half transfer flag. - * @arg DMA1_FLAG_TE1: DMA1 Channel1 transfer error flag. - * @arg DMA1_FLAG_GL2: DMA1 Channel2 global flag. - * @arg DMA1_FLAG_TC2: DMA1 Channel2 transfer complete flag. - * @arg DMA1_FLAG_HT2: DMA1 Channel2 half transfer flag. - * @arg DMA1_FLAG_TE2: DMA1 Channel2 transfer error flag. - * @arg DMA1_FLAG_GL3: DMA1 Channel3 global flag. - * @arg DMA1_FLAG_TC3: DMA1 Channel3 transfer complete flag. - * @arg DMA1_FLAG_HT3: DMA1 Channel3 half transfer flag. - * @arg DMA1_FLAG_TE3: DMA1 Channel3 transfer error flag. - * @arg DMA1_FLAG_GL4: DMA1 Channel4 global flag. - * @arg DMA1_FLAG_TC4: DMA1 Channel4 transfer complete flag. - * @arg DMA1_FLAG_HT4: DMA1 Channel4 half transfer flag. - * @arg DMA1_FLAG_TE4: DMA1 Channel4 transfer error flag. - * @arg DMA1_FLAG_GL5: DMA1 Channel5 global flag. - * @arg DMA1_FLAG_TC5: DMA1 Channel5 transfer complete flag. - * @arg DMA1_FLAG_HT5: DMA1 Channel5 half transfer flag. - * @arg DMA1_FLAG_TE5: DMA1 Channel5 transfer error flag. - * @arg DMA1_FLAG_GL6: DMA1 Channel6 global flag - * @arg DMA1_FLAG_TC6: DMA1 Channel6 transfer complete flag - * @arg DMA1_FLAG_HT6: DMA1 Channel6 half transfer flag - * @arg DMA1_FLAG_TE6: DMA1 Channel6 transfer error flag - * @arg DMA1_FLAG_GL7: DMA1 Channel7 global flag - * @arg DMA1_FLAG_TC7: DMA1 Channel7 transfer complete flag - * @arg DMA1_FLAG_HT7: DMA1 Channel7 half transfer flag - * @arg DMA1_FLAG_TE7: DMA1 Channel7 transfer error flag - * @arg DMA2_FLAG_GL1: DMA2 Channel1 global flag - * @arg DMA2_FLAG_TC1: DMA2 Channel1 transfer complete flag - * @arg DMA2_FLAG_HT1: DMA2 Channel1 half transfer flag - * @arg DMA2_FLAG_TE1: DMA2 Channel1 transfer error flag - * @arg DMA2_FLAG_GL2: DMA2 Channel2 global flag - * @arg DMA2_FLAG_TC2: DMA2 Channel2 transfer complete flag - * @arg DMA2_FLAG_HT2: DMA2 Channel2 half transfer flag - * @arg DMA2_FLAG_TE2: DMA2 Channel2 transfer error flag - * @arg DMA2_FLAG_GL3: DMA2 Channel3 global flag - * @arg DMA2_FLAG_TC3: DMA2 Channel3 transfer complete flag - * @arg DMA2_FLAG_HT3: DMA2 Channel3 half transfer flag - * @arg DMA2_FLAG_TE3: DMA2 Channel3 transfer error flag - * @arg DMA2_FLAG_GL4: DMA2 Channel4 global flag - * @arg DMA2_FLAG_TC4: DMA2 Channel4 transfer complete flag - * @arg DMA2_FLAG_HT4: DMA2 Channel4 half transfer flag - * @arg DMA2_FLAG_TE4: DMA2 Channel4 transfer error flag - * @arg DMA2_FLAG_GL5: DMA2 Channel5 global flag - * @arg DMA2_FLAG_TC5: DMA2 Channel5 transfer complete flag - * @arg DMA2_FLAG_HT5: DMA2 Channel5 half transfer flag - * @arg DMA2_FLAG_TE5: DMA2 Channel5 transfer error flag - * - * @note Clearing the Global flag (DMAy_FLAG_GLx) results in clearing all other flags - * relative to the same channel (Transfer Complete, Half-transfer Complete and - * Transfer Error flags: DMAy_FLAG_TCx, DMAy_FLAG_HTx and DMAy_FLAG_TEx). - * - * @retval None - */ -void DMA_ClearFlag(uint32_t DMAy_FLAG) -{ - /* Check the parameters */ - assert_param(IS_DMA_CLEAR_FLAG(DMAy_FLAG)); - -/* Calculate the used DMAy */ - if ((DMAy_FLAG & FLAG_Mask) != (uint32_t)RESET) - { - ; - } - else - { - /* Clear the selected DMAy flags */ - DMA1->IFCR = DMAy_FLAG; - } -} - -/** - * @brief Checks whether the specified DMAy Channelx interrupt has occurred or not. - * @param DMA_IT: specifies the DMA interrupt source to check. - * This parameter can be one of the following values: - * @arg DMA1_IT_GL1: DMA1 Channel1 global interrupt. - * @arg DMA1_IT_TC1: DMA1 Channel1 transfer complete interrupt. - * @arg DMA1_IT_HT1: DMA1 Channel1 half transfer interrupt. - * @arg DMA1_IT_TE1: DMA1 Channel1 transfer error interrupt. - * @arg DMA1_IT_GL2: DMA1 Channel2 global interrupt. - * @arg DMA1_IT_TC2: DMA1 Channel2 transfer complete interrupt. - * @arg DMA1_IT_HT2: DMA1 Channel2 half transfer interrupt. - * @arg DMA1_IT_TE2: DMA1 Channel2 transfer error interrupt. - * @arg DMA1_IT_GL3: DMA1 Channel3 global interrupt. - * @arg DMA1_IT_TC3: DMA1 Channel3 transfer complete interrupt. - * @arg DMA1_IT_HT3: DMA1 Channel3 half transfer interrupt. - * @arg DMA1_IT_TE3: DMA1 Channel3 transfer error interrupt. - * @arg DMA1_IT_GL4: DMA1 Channel4 global interrupt. - * @arg DMA1_IT_TC4: DMA1 Channel4 transfer complete interrupt. - * @arg DMA1_IT_HT4: DMA1 Channel4 half transfer interrupt. - * @arg DMA1_IT_TE4: DMA1 Channel4 transfer error interrupt. - * @arg DMA1_IT_GL5: DMA1 Channel5 global interrupt. - * @arg DMA1_IT_TC5: DMA1 Channel5 transfer complete interrupt. - * @arg DMA1_IT_HT5: DMA1 Channel5 half transfer interrupt. - * @arg DMA1_IT_TE5: DMA1 Channel5 transfer error interrupt. - * @arg DMA1_IT_GL6: DMA1 Channel6 global interrupt - * @arg DMA1_IT_TC6: DMA1 Channel6 transfer complete interrupt - * @arg DMA1_IT_HT6: DMA1 Channel6 half transfer interrupt - * @arg DMA1_IT_TE6: DMA1 Channel6 transfer error interrupt - * @arg DMA1_IT_GL7: DMA1 Channel7 global interrupt - * @arg DMA1_IT_TC7: DMA1 Channel7 transfer complete interrupt - * @arg DMA1_IT_HT7: DMA1 Channel7 half transfer interrupt - * @arg DMA1_IT_TE7: DMA1 Channel7 transfer error interrupt - * @arg DMA2_IT_GL1: DMA2 Channel1 global interrupt - * @arg DMA2_IT_TC1: DMA2 Channel1 transfer complete interrupt - * @arg DMA2_IT_HT1: DMA2 Channel1 half transfer interrupt - * @arg DMA2_IT_TE1: DMA2 Channel1 transfer error interrupt - * @arg DMA2_IT_GL2: DMA2 Channel2 global interrupt - * @arg DMA2_IT_TC2: DMA2 Channel2 transfer complete interrupt - * @arg DMA2_IT_HT2: DMA2 Channel2 half transfer interrupt - * @arg DMA2_IT_TE2: DMA2 Channel2 transfer error interrupt - * @arg DMA2_IT_GL3: DMA2 Channel3 global interrupt - * @arg DMA2_IT_TC3: DMA2 Channel3 transfer complete interrupt - * @arg DMA2_IT_HT3: DMA2 Channel3 half transfer interrupt - * @arg DMA2_IT_TE3: DMA2 Channel3 transfer error interrupt - * @arg DMA2_IT_GL4: DMA2 Channel4 global interrupt - * @arg DMA2_IT_TC4: DMA2 Channel4 transfer complete interrupt - * @arg DMA2_IT_HT4: DMA2 Channel4 half transfer interrupt - * @arg DMA2_IT_TE4: DMA2 Channel4 transfer error interrupt - * @arg DMA2_IT_GL5: DMA2 Channel5 global interrupt - * @arg DMA2_IT_TC5: DMA2 Channel5 transfer complete interrupt - * @arg DMA2_IT_HT5: DMA2 Channel5 half transfer interrupt - * @arg DMA2_IT_TE5: DMA2 Channel5 transfer error interrupt - * @note The Global interrupt (DMAy_FLAG_GLx) is set whenever any of the other - * interrupts relative to the same channel is set (Transfer Complete, - * Half-transfer Complete or Transfer Error interrupts: DMAy_IT_TCx, - * DMAy_IT_HTx or DMAy_IT_TEx). - * - * @retval The new state of DMA_IT (SET or RESET). - */ -ITStatus DMA_GetITStatus(uint32_t DMAy_IT) -{ - ITStatus bitstatus = RESET; - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_DMA_GET_IT(DMAy_IT)); - - /* Calculate the used DMA */ - if ((DMAy_IT & FLAG_Mask) != (uint32_t)RESET) - { - ; - } - else - { - /* Get DMA1 ISR register value */ - tmpreg = DMA1->ISR; - } - - /* Check the status of the specified DMAy interrupt */ - if ((tmpreg & DMAy_IT) != (uint32_t)RESET) - { - /* DMAy_IT is set */ - bitstatus = SET; - } - else - { - /* DMAy_IT is reset */ - bitstatus = RESET; - } - /* Return the DMAy_IT status */ - return bitstatus; -} - -/** - * @brief Clears the DMAy Channelx's interrupt pending bits. - * @param DMA_IT: specifies the DMA interrupt pending bit to clear. - * This parameter can be any combination (for the same DMA) of the following values: - * @arg DMA1_IT_GL1: DMA1 Channel1 global interrupt. - * @arg DMA1_IT_TC1: DMA1 Channel1 transfer complete interrupt. - * @arg DMA1_IT_HT1: DMA1 Channel1 half transfer interrupt. - * @arg DMA1_IT_TE1: DMA1 Channel1 transfer error interrupt. - * @arg DMA1_IT_GL2: DMA1 Channel2 global interrupt. - * @arg DMA1_IT_TC2: DMA1 Channel2 transfer complete interrupt. - * @arg DMA1_IT_HT2: DMA1 Channel2 half transfer interrupt. - * @arg DMA1_IT_TE2: DMA1 Channel2 transfer error interrupt. - * @arg DMA1_IT_GL3: DMA1 Channel3 global interrupt. - * @arg DMA1_IT_TC3: DMA1 Channel3 transfer complete interrupt. - * @arg DMA1_IT_HT3: DMA1 Channel3 half transfer interrupt. - * @arg DMA1_IT_TE3: DMA1 Channel3 transfer error interrupt. - * @arg DMA1_IT_GL4: DMA1 Channel4 global interrupt. - * @arg DMA1_IT_TC4: DMA1 Channel4 transfer complete interrupt. - * @arg DMA1_IT_HT4: DMA1 Channel4 half transfer interrupt. - * @arg DMA1_IT_TE4: DMA1 Channel4 transfer error interrupt. - * @arg DMA1_IT_GL5: DMA1 Channel5 global interrupt. - * @arg DMA1_IT_TC5: DMA1 Channel5 transfer complete interrupt. - * @arg DMA1_IT_HT5: DMA1 Channel5 half transfer interrupt. - * @arg DMA1_IT_TE5: DMA1 Channel5 transfer error interrupt. - * @arg DMA1_IT_GL6: DMA1 Channel6 global interrupt - * @arg DMA1_IT_TC6: DMA1 Channel6 transfer complete interrupt - * @arg DMA1_IT_HT6: DMA1 Channel6 half transfer interrupt - * @arg DMA1_IT_TE6: DMA1 Channel6 transfer error interrupt - * @arg DMA1_IT_GL7: DMA1 Channel7 global interrupt - * @arg DMA1_IT_TC7: DMA1 Channel7 transfer complete interrupt - * @arg DMA1_IT_HT7: DMA1 Channel7 half transfer interrupt - * @arg DMA1_IT_TE7: DMA1 Channel7 transfer error interrupt - * @note Clearing the Global interrupt (DMAy_IT_GLx) results in clearing all other - * interrupts relative to the same channel (Transfer Complete, Half-transfer - * Complete and Transfer Error interrupts: DMAy_IT_TCx, DMAy_IT_HTx and - * DMAy_IT_TEx). - * - * @retval None - */ -void DMA_ClearITPendingBit(uint32_t DMAy_IT) -{ - /* Check the parameters */ - assert_param(IS_DMA_CLEAR_IT(DMAy_IT)); - - /* Calculate the used DMAy */ - if ((DMAy_IT & FLAG_Mask) != (uint32_t)RESET) - { - ; - } - else - { - /* Clear the selected DMAy interrupt pending bits */ - DMA1->IFCR = DMAy_IT; - } -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT FMD *****END OF FILE****/ diff --git a/bsp/ft32/libraries/FT32F0xx/FT32F0xx_Driver/Src/ft32f0xx_exti.c b/bsp/ft32/libraries/FT32F0xx/FT32F0xx_Driver/Src/ft32f0xx_exti.c deleted file mode 100644 index 334733204f2..00000000000 --- a/bsp/ft32/libraries/FT32F0xx/FT32F0xx_Driver/Src/ft32f0xx_exti.c +++ /dev/null @@ -1,223 +0,0 @@ -/** - ****************************************************************************** - * @file ft32f0xx_exti.c - * @author FMD AE - * @brief This file provides firmware functions to manage the following - * functionalities of the EXTI peripheral: - * + Initialization and Configuration - * + Interrupts and flags management - * @version V1.0.0 - * @data 2021-07-01 - ****************************************************************************** - */ - - -/* Includes ------------------------------------------------------------------*/ -#include "ft32f0xx_exti.h" - - - -/** @defgroup EXTI - * @brief EXTI driver modules - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -#define EXTI_LINENONE ((uint32_t)0x00000) /* No interrupt selected */ - - -/** - * @brief Deinitializes the EXTI peripheral registers to their default reset - * values. - * @param None - * @retval None - */ -void EXTI_DeInit(void) -{ - EXTI->IMR = 0x0F940000; - EXTI->EMR = 0x00000000; - EXTI->RTSR = 0x00000000; - EXTI->FTSR = 0x00000000; - EXTI->PR = 0x006BFFFF; -} - -/** - * @brief Initializes the EXTI peripheral according to the specified - * parameters in the EXTI_InitStruct. - * @param EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure that - * contains the configuration information for the EXTI peripheral. - * @retval None - */ -void EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct) -{ - uint32_t tmp = 0; - - /* Check the parameters */ - assert_param(IS_EXTI_MODE(EXTI_InitStruct->EXTI_Mode)); - assert_param(IS_EXTI_TRIGGER(EXTI_InitStruct->EXTI_Trigger)); - assert_param(IS_EXTI_LINE(EXTI_InitStruct->EXTI_Line)); - assert_param(IS_FUNCTIONAL_STATE(EXTI_InitStruct->EXTI_LineCmd)); - - tmp = (uint32_t)EXTI_BASE; - - if (EXTI_InitStruct->EXTI_LineCmd != DISABLE) - { - /* Clear EXTI line configuration */ - EXTI->IMR &= ~EXTI_InitStruct->EXTI_Line; - EXTI->EMR &= ~EXTI_InitStruct->EXTI_Line; - - tmp += EXTI_InitStruct->EXTI_Mode; - - *(__IO uint32_t *) tmp |= EXTI_InitStruct->EXTI_Line; - - /* Clear Rising Falling edge configuration */ - EXTI->RTSR &= ~EXTI_InitStruct->EXTI_Line; - EXTI->FTSR &= ~EXTI_InitStruct->EXTI_Line; - - /* Select the trigger for the selected interrupts */ - if (EXTI_InitStruct->EXTI_Trigger == EXTI_Trigger_Rising_Falling) - { - /* Rising Falling edge */ - EXTI->RTSR |= EXTI_InitStruct->EXTI_Line; - EXTI->FTSR |= EXTI_InitStruct->EXTI_Line; - } - else - { - tmp = (uint32_t)EXTI_BASE; - tmp += EXTI_InitStruct->EXTI_Trigger; - - *(__IO uint32_t *) tmp |= EXTI_InitStruct->EXTI_Line; - } - } - else - { - tmp += EXTI_InitStruct->EXTI_Mode; - - /* Disable the selected external lines */ - *(__IO uint32_t *) tmp &= ~EXTI_InitStruct->EXTI_Line; - } -} - -/** - * @brief Fills each EXTI_InitStruct member with its reset value. - * @param EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure which will - * be initialized. - * @retval None - */ -void EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct) -{ - EXTI_InitStruct->EXTI_Line = EXTI_LINENONE; - EXTI_InitStruct->EXTI_Mode = EXTI_Mode_Interrupt; - EXTI_InitStruct->EXTI_Trigger = EXTI_Trigger_Falling; - EXTI_InitStruct->EXTI_LineCmd = DISABLE; -} - -/** - * @brief Generates a Software interrupt on selected EXTI line. - * @param EXTI_Line: specifies the EXTI line on which the software interrupt - * will be generated. - * This parameter can be any combination of EXTI_Linex where x can be (0..27). - * @retval None - */ -void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line) -{ - /* Check the parameters */ - assert_param(IS_EXTI_LINE(EXTI_Line)); - - EXTI->SWIER |= EXTI_Line; -} - - -/** - * @brief Checks whether the specified EXTI line flag is set or not. - * @param EXTI_Line: specifies the EXTI line flag to check. - * This parameter can be EXTI_Linex where x can be (0..27). - * @retval The new state of EXTI_Line (SET or RESET). - */ -FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line) -{ - FlagStatus bitstatus = RESET; - /* Check the parameters */ - assert_param(IS_GET_EXTI_LINE(EXTI_Line)); - - if ((EXTI->PR & EXTI_Line) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - return bitstatus; -} - -/** - * @brief Clears the EXTI's line pending flags. - * @param EXTI_Line: specifies the EXTI lines flags to clear. - * This parameter can be any combination of EXTI_Linex where x can be (0..27). - * @retval None - */ -void EXTI_ClearFlag(uint32_t EXTI_Line) -{ - /* Check the parameters */ - assert_param(IS_EXTI_LINE(EXTI_Line)); - - EXTI->PR = EXTI_Line; -} - -/** - * @brief Checks whether the specified EXTI line is asserted or not. - * @param EXTI_Line: specifies the EXTI line to check. - * This parameter can be EXTI_Linex where x can be (0..27). - * @retval The new state of EXTI_Line (SET or RESET). - */ -ITStatus EXTI_GetITStatus(uint32_t EXTI_Line) -{ - ITStatus bitstatus = RESET; - - /* Check the parameters */ - assert_param(IS_GET_EXTI_LINE(EXTI_Line)); - - if ((EXTI->PR & EXTI_Line) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - return bitstatus; -} - -/** - * @brief Clears the EXTI's line pending bits. - * @param EXTI_Line: specifies the EXTI lines to clear. - * This parameter can be any combination of EXTI_Linex where x can be (0..27). - * @retval None - */ -void EXTI_ClearITPendingBit(uint32_t EXTI_Line) -{ - /* Check the parameters */ - assert_param(IS_EXTI_LINE(EXTI_Line)); - - EXTI->PR = EXTI_Line; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT FMD *****END OF FILE****/ diff --git a/bsp/ft32/libraries/FT32F0xx/FT32F0xx_Driver/Src/ft32f0xx_flash.c b/bsp/ft32/libraries/FT32F0xx/FT32F0xx_Driver/Src/ft32f0xx_flash.c deleted file mode 100644 index 006438111a0..00000000000 --- a/bsp/ft32/libraries/FT32F0xx/FT32F0xx_Driver/Src/ft32f0xx_flash.c +++ /dev/null @@ -1,1601 +0,0 @@ -/** - ****************************************************************************** - * @file ft32f0xx_flash.c - * @author FMD AE - * @brief This file provides firmware functions to manage the following - * functionalities of the FLASH peripheral: - * - FLASH Interface configuration - * - FLASH Memory Programming - * - Option Bytes Programming - * - Interrupts and flags management - * @version V1.0.0 - * @data 2021-07-01 - ****************************************************************************** - */ - - -/* Includes ------------------------------------------------------------------*/ -#include "ft32f0xx_flash.h" - -/** - * @brief Sets the code latency value. - * @param FLASH_Latency: specifies the FLASH Latency value. - * This parameter can be one of the following values: - * @arg FLASH_Latency_0: FLASH Zero Latency cycle - * @arg FLASH_Latency_1: FLASH One Latency cycle - * @retval None - */ -void FLASH_SetLatency(uint32_t FLASH_Latency) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_FLASH_LATENCY(FLASH_Latency)); - - /* Read the ACR register */ - tmpreg = FLASH->ACR; - - /* Sets the Latency value */ - tmpreg &= (uint32_t) (~((uint32_t)FLASH_ACR_LATENCY)); - tmpreg |= FLASH_Latency; - - /* Write the ACR register */ - FLASH->ACR = tmpreg; -} - -/** - * @brief Enables or disables the Prefetch Buffer. - * @param NewState: new state of the FLASH prefetch buffer. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void FLASH_PrefetchBufferCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if(NewState != DISABLE) - { - FLASH->ACR |= FLASH_ACR_PRFTBE; - } - else - { - FLASH->ACR &= (uint32_t)(~((uint32_t)FLASH_ACR_PRFTBE)); - } -} - -/** - * @brief Checks whether the FLASH Prefetch Buffer status is set or not. - * @param None - * @retval FLASH Prefetch Buffer Status (SET or RESET). - */ -FlagStatus FLASH_GetPrefetchBufferStatus(void) -{ - FlagStatus bitstatus = RESET; - - if ((FLASH->ACR & FLASH_ACR_PRFTBS) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - /* Return the new state of FLASH Prefetch Buffer Status (SET or RESET) */ - return bitstatus; -} - - -/** - * @brief Unlocks the FLASH control register and program memory access. - * @param None - * @retval None - */ -void FLASH_Unlock(void) -{ - if((FLASH->CR & FLASH_CR_LOCK) != RESET) - { - /* Unlocking the program memory access */ - FLASH->KEYR = FLASH_FKEY1; - FLASH->KEYR = FLASH_FKEY2; - } -} - -/** - * @brief Locks the Program memory access. - * @param None - * @retval None - */ -void FLASH_Lock(void) -{ - /* Set the LOCK Bit to lock the FLASH control register and program memory access */ - FLASH->CR |= FLASH_CR_LOCK; -} - -/** - * @brief Erases a specified page in program memory. - * @note To correctly run this function, the FLASH_Unlock() function must be called before. - * @note Call the FLASH_Lock() to disable the flash memory access (recommended - * to protect the FLASH memory against possible unwanted operation) - * @param Page_Address: The page address in program memory to be erased. - * @note A Page is erased in the Program memory only if the address to load - * is the start address of a page (multiple of 512 bytes,in FT32F072XB is 1024 bytes). - * @retval FLASH Status: The returned value can be: - * FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. - */ -FLASH_Status FLASH_ErasePage(uint32_t Page_Address) -{ - FLASH_Status status = FLASH_COMPLETE; - - /* Check the parameters */ - assert_param(IS_FLASH_PROGRAM_ADDRESS(Page_Address)); - - FLASH_PrefetchBufferCmd(DISABLE); - __ASM("ISB"); - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); - - if(status == FLASH_COMPLETE) - { - /* If the previous operation is completed, proceed to erase the page */ - FLASH->CR |= FLASH_CR_PER; - FLASH->AR = Page_Address; - FLASH->CR |= FLASH_CR_STRT; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); - - /* Disable the PER Bit */ - FLASH->CR &= ~FLASH_CR_PER; - } - - FLASH_PrefetchBufferCmd(ENABLE); - - /* Return the Erase Status */ - return status; -} - -/** - * @brief Erases all FLASH pages. - * @note To correctly run this function, the FLASH_Unlock() function must be called before. - * @note Call the FLASH_Lock() to disable the flash memory access (recommended - * to protect the FLASH memory against possible unwanted operation) - * @param None - * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG, - * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. - */ -FLASH_Status FLASH_EraseAllPages(void) -{ - FLASH_Status status = FLASH_COMPLETE; - - FLASH_PrefetchBufferCmd(DISABLE); - __ASM("ISB"); - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); - - if(status == FLASH_COMPLETE) - { - /* if the previous operation is completed, proceed to erase all pages */ - FLASH->CR |= FLASH_CR_MER; - FLASH->CR |= FLASH_CR_STRT; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); - - /* Disable the MER Bit */ - FLASH->CR &= ~FLASH_CR_MER; - } - - FLASH_PrefetchBufferCmd(ENABLE); - - /* Return the Erase Status */ - return status; -} - -#if defined(FT32F072xB) -/** - * @brief Programs a word at a specified address. - * @note To correctly run this function, the FLASH_Unlock() function must be called before. - * @note Call the FLASH_Lock() to disable the flash memory access (recommended - * to protect the FLASH memory against possible unwanted operation) - * @param Address: specifies the address to be programmed. - * @param Data: specifies the data to be programmed. - * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG, - * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. - */ -FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data) -{ - FLASH_Status status = FLASH_COMPLETE; - __IO uint32_t tmp = 0; - - /* Check the parameters */ - assert_param(IS_FLASH_PROGRAM_ADDRESS(Address)); - - FLASH_PrefetchBufferCmd(DISABLE); - __ASM("ISB"); - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); - - if(status == FLASH_COMPLETE) - { - /* If the previous operation is completed, proceed to program the new first - half word */ - FLASH->CR |= FLASH_CR_PG; - - *(__IO uint16_t*)Address = (uint16_t)Data; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); - - if(status == FLASH_COMPLETE) - { - /* If the previous operation is completed, proceed to program the new second - half word */ - tmp = Address + 2; - - *(__IO uint16_t*) tmp = Data >> 16; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); - - /* Disable the PG Bit */ - FLASH->CR &= ~FLASH_CR_PG; - } - else - { - /* Disable the PG Bit */ - FLASH->CR &= ~FLASH_CR_PG; - } - } - - FLASH_PrefetchBufferCmd(ENABLE); - /* Return the Program Status */ - return status; -} - -/** - * @brief Programs a half word at a specified address. - * @note To correctly run this function, the FLASH_Unlock() function must be called before. - * @note Call the FLASH_Lock() to disable the flash memory access (recommended - * to protect the FLASH memory against possible unwanted operation) - * @param Address: specifies the address to be programmed. - * @param Data: specifies the data to be programmed. - * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG, - * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. - */ -FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data) -{ - FLASH_Status status = FLASH_COMPLETE; - - /* Check the parameters */ - assert_param(IS_FLASH_PROGRAM_ADDRESS(Address)); - - FLASH_PrefetchBufferCmd(DISABLE); - __ASM("ISB"); - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); - - if(status == FLASH_COMPLETE) - { - /* If the previous operation is completed, proceed to program the new data */ - FLASH->CR |= FLASH_CR_PG; - - *(__IO uint16_t*)Address = Data; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); - - /* Disable the PG Bit */ - FLASH->CR &= ~FLASH_CR_PG; - } - - FLASH_PrefetchBufferCmd(ENABLE); - - /* Return the Program Status */ - return status; -} -#else -/** - * @brief Programs a word at a specified address. - * @note To correctly run this function, the FLASH_Unlock() function must be called before. - * @note Call the FLASH_Lock() to disable the flash memory access (recommended - * to protect the FLASH memory against possible unwanted operation) - * @param Address: specifies the address to be programmed. - * @param Data: specifies the data to be programmed. - * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG, - * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. - */ -FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data) -{ - FLASH_Status status = FLASH_COMPLETE; - __IO uint32_t tmp = 0; - - /* Check the parameters */ - assert_param(IS_FLASH_PROGRAM_ADDRESS(Address)); - - FLASH_PrefetchBufferCmd(DISABLE); - __ASM("ISB"); - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); - - if(status == FLASH_COMPLETE) - { - /* If the previous operation is completed, proceed to program the new first word */ - FLASH->CR |= FLASH_CR_PG; - - *(__IO uint32_t*)Address = Data; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); - - /* Disable the PG Bit */ - FLASH->CR &= ~FLASH_CR_PG; - } - - FLASH_PrefetchBufferCmd(ENABLE); - - /* Return the Program Status */ - return status; -} -#endif - -/** - * @} - */ - -/** - * @brief Unlocks the option bytes block access. - * @param None - * @retval None - */ -void FLASH_OB_Unlock(void) -{ - if((FLASH->CR & FLASH_CR_OPTWRE) == RESET) - { - /* Unlocking the option bytes block access */ - FLASH->OPTKEYR = FLASH_OPTKEY1; - FLASH->OPTKEYR = FLASH_OPTKEY2; - } -} - -/** - * @brief Locks the option bytes block access. - * @param None - * @retval None - */ -void FLASH_OB_Lock(void) -{ - /* Set the OPTWREN Bit to lock the option bytes block access */ - FLASH->CR &= ~FLASH_CR_OPTWRE; -} - -/** - * @brief Launch the option byte loading. - * @param None - * @retval None - */ -void FLASH_OB_Launch(void) -{ - /* Set the OBL_Launch bit to launch the option byte loading */ - FLASH->CR |= FLASH_CR_OBL_LAUNCH; -} - -#if defined(FT32F072xB) -/** - * @brief Erases the FLASH option bytes. - * @note To correctly run this function, the FLASH_OB_Unlock() function must be called before. - * @note Call the FLASH_OB_Lock() to disable the flash control register access and the option - * bytes (recommended to protect the FLASH memory against possible unwanted operation) - * @note This functions erases all option bytes except the Read protection (RDP). - * @param None - * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG, - * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. - */ -FLASH_Status FLASH_OB_Erase(void) -{ - uint16_t rdptmp = OB_RDP_Level_0; - - FLASH_Status status = FLASH_COMPLETE; - - /* Get the actual read protection Option Byte value */ - if(FLASH_OB_GetRDP() != RESET) - { - rdptmp = 0x0; - } - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); - - if(status == FLASH_COMPLETE) - { - /* If the previous operation is completed, proceed to erase the option bytes */ - FLASH->CR |= FLASH_CR_OPTER; - FLASH->CR |= FLASH_CR_STRT; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); - - if(status == FLASH_COMPLETE) - { - /* If the erase operation is completed, disable the OPTER Bit */ - FLASH->CR &= ~FLASH_CR_OPTER; - - /* Enable the Option Bytes Programming operation */ - FLASH->CR |= FLASH_CR_OPTPG; - - /* Restore the last read protection Option Byte value */ - OB->RDP = (uint16_t)rdptmp; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); - - if(status != FLASH_TIMEOUT) - { - /* if the program operation is completed, disable the OPTPG Bit */ - FLASH->CR &= ~FLASH_CR_OPTPG; - } - - } - else - { - if (status != FLASH_TIMEOUT) - { - FLASH->CR &= ~FLASH_CR_OPTER; - } - } - } - /* Return the erase status */ - return status; -} - -/** - * @brief Write protects the desired pages - * @note To correctly run this function, the FLASH_OB_Unlock() function must be called before. - * @note Call the FLASH_OB_Lock() to disable the flash control register access and the option - * bytes (recommended to protect the FLASH memory against possible unwanted operation) - * @param OB_WRP: specifies the address of the pages to be write protected. - * This parameter can be: - * @arg OB_WRP_Pages0to7..OB_WRP_Pages120to127 - * @arg OB_WRP_AllPages - * @retval FLASH Status: The returned value can be: - * FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. - */ -FLASH_Status FLASH_OB_EnableWRP(uint32_t OB_WRP) -{ - uint16_t WRP0_Data = 0xFFFF, WRP1_Data = 0xFFFF, WRP2_Data = 0xFFFF, WRP3_Data = 0xFFFF; - - FLASH_Status status = FLASH_COMPLETE; - - /* Check the parameters */ - assert_param(IS_OB_WRP(OB_WRP)); - - OB_WRP = (uint32_t)(~OB_WRP); - WRP0_Data = (uint16_t)(OB_WRP & OB_WRP0_WRP0); - WRP1_Data = (uint16_t)((OB_WRP >> 8) & OB_WRP0_WRP0); - WRP2_Data = (uint16_t)((OB_WRP >> 16) & OB_WRP0_WRP0) ; - WRP3_Data = (uint16_t)((OB_WRP >> 24) & OB_WRP0_WRP0) ; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); - - if(status == FLASH_COMPLETE) - { - FLASH->CR |= FLASH_CR_OPTPG; - - if(WRP0_Data != 0xFF) - { - OB->WRP0 = WRP0_Data; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); - } - if((status == FLASH_COMPLETE) && (WRP1_Data != 0xFF)) - { - OB->WRP1 = WRP1_Data; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); - } - if((status == FLASH_COMPLETE) && (WRP2_Data != 0xFF)) - { - OB->WRP2 = WRP2_Data; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); - } - if((status == FLASH_COMPLETE) && (WRP3_Data != 0xFF)) - { - OB->WRP3 = WRP3_Data; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); - } - if(status != FLASH_TIMEOUT) - { - /* if the program operation is completed, disable the OPTPG Bit */ - FLASH->CR &= ~FLASH_CR_OPTPG; - } - } - /* Return the write protection operation Status */ - return status; -} -/** - * @brief Enables or disables the read out protection. - * @note To correctly run this function, the FLASH_OB_Unlock() function must be called before. - * @note Call the FLASH_OB_Lock() to disable the flash control register access and the option - * bytes (recommended to protect the FLASH memory against possible unwanted operation) - * @param FLASH_ReadProtection_Level: specifies the read protection level. - * This parameter can be: - * @arg OB_RDP_Level_0: No protection - * @arg OB_RDP_Level_1: Read protection of the memory - * @arg - * @note When enabling OB_RDP level 2 it's no more possible to go back to level 1 or 0 - * @retval FLASH Status: The returned value can be: - * FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. - */ -FLASH_Status FLASH_OB_RDPConfig(uint8_t OB_RDP) -{ - FLASH_Status status = FLASH_COMPLETE; - - /* Check the parameters */ - assert_param(IS_OB_RDP(OB_RDP)); - status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); - - if(status == FLASH_COMPLETE) - { - FLASH->CR |= FLASH_CR_OPTER; - FLASH->CR |= FLASH_CR_STRT; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); - - if(status == FLASH_COMPLETE) - { - /* If the erase operation is completed, disable the OPTER Bit */ - FLASH->CR &= ~FLASH_CR_OPTER; - - /* Enable the Option Bytes Programming operation */ - FLASH->CR |= FLASH_CR_OPTPG; - - OB->RDP = OB_RDP; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); - - if(status != FLASH_TIMEOUT) - { - /* if the program operation is completed, disable the OPTPG Bit */ - FLASH->CR &= ~FLASH_CR_OPTPG; - } - } - else - { - if(status != FLASH_TIMEOUT) - { - /* Disable the OPTER Bit */ - FLASH->CR &= ~FLASH_CR_OPTER; - } - } - } - /* Return the protection operation Status */ - return status; -} - -/** - * @brief Programs the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY. - * @note To correctly run this function, the FLASH_OB_Unlock() function must be called before. - * @note Call the FLASH_OB_Lock() to disable the flash control register access and the option - * bytes (recommended to protect the FLASH memory against possible unwanted operation) - * @param OB_IWDG: Selects the WDG mode - * This parameter can be one of the following values: - * @arg OB_IWDG_SW: Software WDG selected - * @arg OB_IWDG_HW: Hardware WDG selected - * @param OB_STOP: Reset event when entering STOP mode. - * This parameter can be one of the following values: - * @arg OB_STOP_NoRST: No reset generated when entering in STOP - * @arg OB_STOP_RST: Reset generated when entering in STOP - * @param OB_STDBY: Reset event when entering Standby mode. - * This parameter can be one of the following values: - * @arg OB_STDBY_NoRST: No reset generated when entering in STANDBY - * @arg OB_STDBY_RST: Reset generated when entering in STANDBY - * @retval FLASH Status: The returned value can be: - * FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. - */ -FLASH_Status FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY) -{ - FLASH_Status status = FLASH_COMPLETE; - - /* Check the parameters */ - assert_param(IS_OB_IWDG_SOURCE(OB_IWDG)); - assert_param(IS_OB_STOP_SOURCE(OB_STOP)); - assert_param(IS_OB_STDBY_SOURCE(OB_STDBY)); - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); - - if(status == FLASH_COMPLETE) - { - /* Enable the Option Bytes Programming operation */ - FLASH->CR |= FLASH_CR_OPTPG; - - OB->USER = (uint16_t)((uint16_t)(OB_IWDG | OB_STOP) | (uint16_t)(OB_STDBY | 0xF8)); - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); - - if(status != FLASH_TIMEOUT) - { - /* If the program operation is completed, disable the OPTPG Bit */ - FLASH->CR &= ~FLASH_CR_OPTPG; - } - } - /* Return the Option Byte program Status */ - return status; -} - -/** - * @brief Sets or resets the BOOT1 option bit. - * @param OB_BOOT1: Set or Reset the BOOT1 option bit. - * This parameter can be one of the following values: - * @arg OB_BOOT1_RESET: BOOT1 option bit reset - * @arg OB_BOOT1_SET: BOOT1 option bit set - * @retval None - */ -FLASH_Status FLASH_OB_BOOTConfig(uint8_t OB_BOOT1) -{ - FLASH_Status status = FLASH_COMPLETE; - - /* Check the parameters */ - assert_param(IS_OB_BOOT1(OB_BOOT1)); - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); - - if(status == FLASH_COMPLETE) - { - /* Enable the Option Bytes Programming operation */ - FLASH->CR |= FLASH_CR_OPTPG; - - OB->USER = OB_BOOT1 | 0xEF; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); - - if(status != FLASH_TIMEOUT) - { - /* If the program operation is completed, disable the OPTPG Bit */ - FLASH->CR &= ~FLASH_CR_OPTPG; - } - } - /* Return the Option Byte program Status */ - return status; -} - -/** - * @brief Sets or resets the analogue monitoring on VDDA Power source. - * @param OB_VDDA_ANALOG: Selects the analog monitoring on VDDA Power source. - * This parameter can be one of the following values: - * @arg OB_VDDA_ANALOG_ON: Analog monitoring on VDDA Power source ON - * @arg OB_VDDA_ANALOG_OFF: Analog monitoring on VDDA Power source OFF - * @retval None - */ -FLASH_Status FLASH_OB_VDDAConfig(uint8_t OB_VDDA_ANALOG) -{ - FLASH_Status status = FLASH_COMPLETE; - - /* Check the parameters */ - assert_param(IS_OB_VDDA_ANALOG(OB_VDDA_ANALOG)); - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); - - if(status == FLASH_COMPLETE) - { - /* Enable the Option Bytes Programming operation */ - FLASH->CR |= FLASH_CR_OPTPG; - - OB->USER = OB_VDDA_ANALOG | 0xDF; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); - - if(status != FLASH_TIMEOUT) - { - /* if the program operation is completed, disable the OPTPG Bit */ - FLASH->CR &= ~FLASH_CR_OPTPG; - } - } - /* Return the Option Byte program Status */ - return status; -} - -/** - * @brief Sets or resets the SRAM parity. - * @param OB_SRAM_Parity: Set or Reset the SRAM parity enable bit. - * This parameter can be one of the following values: - * @arg OB_SRAM_PARITY_SET: Set SRAM parity. - * @arg OB_SRAM_PARITY_RESET: Reset SRAM parity. - * @retval None - */ -FLASH_Status FLASH_OB_SRAMParityConfig(uint8_t OB_SRAM_Parity) -{ - FLASH_Status status = FLASH_COMPLETE; - - /* Check the parameters */ - assert_param(IS_OB_SRAM_PARITY(OB_SRAM_Parity)); - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); - - if(status == FLASH_COMPLETE) - { - - /* Enable the Option Bytes Programming operation */ - FLASH->CR |= FLASH_CR_OPTPG; - - OB->USER = OB_SRAM_Parity | 0xBF; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); - - if(status != FLASH_TIMEOUT) - { - /* if the program operation is completed, disable the OPTPG Bit */ - FLASH->CR &= ~FLASH_CR_OPTPG; - } - } - /* Return the Option Byte program Status */ - return status; -} - -/** - * @brief Programs the FLASH User Option Byte: IWDG_SW, RST_STOP, RST_STDBY, - * BOOT1 and VDDA ANALOG monitoring. - * @note To correctly run this function, the FLASH_OB_Unlock() function must be called before. - * @note Call the FLASH_OB_Lock() to disable the flash control register access and the option - * bytes (recommended to protect the FLASH memory against possible unwanted operation) - * @param OB_USER: Selects all user option bytes - * This parameter is a combination of the following values: - * @arg OB_IWDG_SW / OB_IWDG_HW: Software / Hardware WDG selected - * @arg OB_STOP_NoRST / OB_STOP_RST: No reset / Reset generated when entering in STOP - * @arg OB_STDBY_NoRST / OB_STDBY_RST: No reset / Reset generated when entering in STANDBY - * @arg OB_BOOT1_RESET / OB_BOOT1_SET: BOOT1 Reset / Set - * @arg OB_VDDA_ANALOG_ON / OB_VDDA_ANALOG_OFF: Analog monitoring on VDDA Power source ON / OFF - * @arg OB_SRAM_PARITY_SET / OB_SRAM_PARITY_RESET: SRAM Parity SET / RESET - * @arg OB_BOOT0_RESET / OB_BOOT0_SET: BOOT0 Reset / Set - * @arg OB_BOOT0_SW / OB_BOOT0_SW: BOOT0 pin disabled / BOOT0 pin bonded with GPIO - * @retval FLASH Status: The returned value can be: - * FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. - */ -FLASH_Status FLASH_OB_WriteUser(uint8_t OB_USER) -{ - FLASH_Status status = FLASH_COMPLETE; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); - - if(status == FLASH_COMPLETE) - { - /* If the erase operation is completed, disable the OPTER Bit */ - FLASH->CR &= ~FLASH_CR_OPTER; - /* Enable the Option Bytes Programming operation */ - FLASH->CR |= FLASH_CR_OPTPG; - - OB->USER = OB_USER; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); - - if(status != FLASH_TIMEOUT) - { - /* If the program operation is completed, disable the OPTPG Bit */ - FLASH->CR &= ~FLASH_CR_OPTPG; - } - } - /* Return the Option Byte program Status */ - return status; - -} - -/** - * @brief Programs a half word at a specified Option Byte Data address. - * @note To correctly run this function, the FLASH_OB_Unlock() function must be called before. - * @note Call the FLASH_OB_Lock() to disable the flash control register access and the option - * bytes (recommended to protect the FLASH memory against possible unwanted operation) - * @param Address: specifies the address to be programmed. - * This parameter can be 0x1FFFF804. - * @param Data: specifies the data to be programmed. - * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG, - * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. - */ -FLASH_Status FLASH_OB_ProgramData(uint32_t Address, uint8_t Data) -{ - FLASH_Status status = FLASH_COMPLETE; - /* Check the parameters */ - assert_param(IS_OB_DATA_ADDRESS(Address)); - status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); - - if(status == FLASH_COMPLETE) - { - /* Enables the Option Bytes Programming operation */ - FLASH->CR |= FLASH_CR_OPTPG; - *(__IO uint16_t*)Address = Data; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); - - if(status != FLASH_TIMEOUT) - { - /* If the program operation is completed, disable the OPTPG Bit */ - FLASH->CR &= ~FLASH_CR_OPTPG; - } - } - /* Return the Option Byte Data Program Status */ - return status; -} -#else -/** - * @brief Erases the FLASH option bytes. - * @note To correctly run this function, the FLASH_OB_Unlock() function must be called before. - * @note Call the FLASH_OB_Lock() to disable the flash control register access and the option - * bytes (recommended to protect the FLASH memory against possible unwanted operation) - * @note This functions erases all option bytes except the Read protection (RDP). - * @param None - * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG, - * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. - */ -FLASH_Status FLASH_OB_Erase(void) -{ - uint32_t rdptmp = 0; - - FLASH_Status status = FLASH_COMPLETE; - - /* Get the actual read protection Option Byte value */ - if(FLASH_OB_GetRDP() != RESET) - { - rdptmp = 0x0000 | 0xff00; //读保护级别1 - } - else - { - rdptmp = OB_RDP_Level_0 | 0x5500; //读保护级别0 - } - - /*Get iwdg value */ -// if ((uint8_t)(FLASH->OBR & (FLASH_OBR_IWDG_SW)) != RESET) -// { -// rdptmp |= 0x0f0000 | 0xf0000000;//HW iwdg -// } -// else - { - rdptmp |= 0x0e0000 | 0xf1000000;//sw iwdg - } - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); - - if(status == FLASH_COMPLETE) - { - /* If the previous operation is completed, proceed to erase the option bytes */ - FLASH->CR |= FLASH_CR_OPTER; - FLASH->CR |= FLASH_CR_STRT; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); - - if(status == FLASH_COMPLETE) - { - /* If the erase operation is completed, disable the OPTER Bit */ - FLASH->CR &= ~FLASH_CR_OPTER; - - /* Enable the Option Bytes Programming operation */ - FLASH->CR |= FLASH_CR_OPTPG; - - /* Restore the last read protection Option Byte value */ - OB->USER_RDP = rdptmp; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); - - if(status != FLASH_TIMEOUT) - { - /* if the program operation is completed, disable the OPTPG Bit */ - FLASH->CR &= ~FLASH_CR_OPTPG; - } - } - else - { - if (status != FLASH_TIMEOUT) - { - /* Disable the OPTPG Bit */ - FLASH->CR &= ~FLASH_CR_OPTPG; - } - } - } - /* Return the erase status */ - return status; -} - -/** - * @brief Write protects the desired pages - * @note To correctly run this function, the FLASH_OB_Unlock() function must be called before. - * @note Call the FLASH_OB_Lock() to disable the flash control register access and the option - * bytes (recommended to protect the FLASH memory against possible unwanted operation) - * @param OB_WRP: specifies the address of the pages to be write protected. - * This parameter can be: - * @arg OB_WRP_Pages0to3..OB_WRP_Pages60to63 - * @arg OB_WRP_AllPages - * @retval FLASH Status: The returned value can be: - * FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. - */ -FLASH_Status FLASH_OB_EnableWRP(uint32_t OB_WRP) -{ - uint8_t WRP0_Data = 0xFF,WRP1_Data = 0xFF,WRP2_Data = 0xFF,WRP3_Data = 0xFF; - uint8_t nWRP0_Data = 0,nWRP1_Data = 0,nWRP2_Data = 0,nWRP3_Data = 0; - FLASH_Status status = FLASH_COMPLETE; - - /* Check the parameters */ - assert_param(IS_OB_WRP(OB_WRP)); - - OB_WRP = (uint32_t)(~OB_WRP); - WRP0_Data = (uint8_t)(OB_WRP & OB_WRP0_WRP0); - nWRP0_Data = ~WRP0_Data; - - WRP1_Data = (uint8_t)((OB_WRP >> 8) & OB_WRP0_WRP0); - nWRP1_Data = ~WRP1_Data; - - WRP2_Data = (uint8_t)((OB_WRP >> 16) & OB_WRP0_WRP0); - nWRP2_Data = ~WRP2_Data; - - WRP3_Data = (uint8_t)((OB_WRP >> 24) & OB_WRP0_WRP0); - nWRP3_Data = ~WRP3_Data; - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); - - if(status == FLASH_COMPLETE) - { - FLASH->CR |= FLASH_CR_OPTPG; - - if((WRP0_Data != 0xFF) ||(WRP1_Data != 0xFF)) - { - OB->WRP1_WRP0 = (WRP0_Data) | (nWRP0_Data<<8) | (WRP1_Data<<16) | (nWRP1_Data<<24); - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); - } - if((status == FLASH_COMPLETE) && (WRP2_Data != 0xFF)) - { - OB->WRP3_WRP2 = (WRP2_Data) | (nWRP2_Data<<8) | (WRP3_Data<<16) | (nWRP3_Data<<24); - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); - } - if(status != FLASH_TIMEOUT) - { - /* if the program operation is completed, disable the OPTPG Bit */ - FLASH->CR &= ~FLASH_CR_OPTPG; - } - } - /* Return the write protection operation Status */ - return status; -} - -/** - * @brief Enables or disables the read out protection. - * @note To correctly run this function, the FLASH_OB_Unlock() function must be called before. - * @note Call the FLASH_OB_Lock() to disable the flash control register access and the option - * bytes (recommended to protect the FLASH memory against possible unwanted operation) - * @param FLASH_ReadProtection_Level: specifies the read protection level. - * This parameter can be: - * @arg OB_RDP_Level_0: No protection - * @arg OB_RDP_Level_1: Read protection of the memory - * @arg - * @note When enabling OB_RDP level 2 it's no more possible to go back to level 1 or 0 - * @retval FLASH Status: The returned value can be: - * FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. - */ -FLASH_Status FLASH_OB_RDPConfig(uint8_t OB_RDP) -{ - FLASH_Status status = FLASH_COMPLETE; - uint32_t ob_user_rdp = 0; - uint16_t ob_rdp_nrdp = 0; - - /* Check the parameters */ - assert_param(IS_OB_RDP(OB_RDP)); - status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); - - ob_user_rdp = OB->USER_RDP & 0xffff0000; - ob_rdp_nrdp = OB_RDP; - OB_RDP = ~OB_RDP; - ob_rdp_nrdp |= OB_RDP<<8; - ob_user_rdp |= ob_rdp_nrdp; - - if(status == FLASH_COMPLETE) - { - FLASH->CR |= FLASH_CR_OPTER; - FLASH->CR |= FLASH_CR_STRT; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); - - if(status == FLASH_COMPLETE) - { - /* If the erase operation is completed, disable the OPTER Bit */ - FLASH->CR &= ~FLASH_CR_OPTER; - - /* Enable the Option Bytes Programming operation */ - FLASH->CR |= FLASH_CR_OPTPG; - - OB->USER_RDP = ob_user_rdp; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); - - if(status != FLASH_TIMEOUT) - { - /* if the program operation is completed, disable the OPTPG Bit */ - FLASH->CR &= ~FLASH_CR_OPTPG; - } - } - else - { - if(status != FLASH_TIMEOUT) - { - /* Disable the OPTER Bit */ - FLASH->CR &= ~FLASH_CR_OPTER; - } - } - } - /* Return the protection operation Status */ - return status; -} - -/** - * @brief Programs the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY. - * @note To correctly run this function, the FLASH_OB_Unlock() function must be called before. - * @note Call the FLASH_OB_Lock() to disable the flash control register access and the option - * bytes (recommended to protect the FLASH memory against possible unwanted operation) - * @param OB_IWDG: Selects the WDG mode - * This parameter can be one of the following values: - * @arg OB_IWDG_SW: Software WDG selected - * @arg OB_IWDG_HW: Hardware WDG selected - * @param OB_STOP: Reset event when entering STOP mode. - * This parameter can be one of the following values: - * @arg OB_STOP_NoRST: No reset generated when entering in STOP - * @arg OB_STOP_RST: Reset generated when entering in STOP - * @param OB_STDBY: Reset event when entering Standby mode. - * This parameter can be one of the following values: - * @arg OB_STDBY_NoRST: No reset generated when entering in STANDBY - * @arg OB_STDBY_RST: Reset generated when entering in STANDBY - * @retval FLASH Status: The returned value can be: - * FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. - */ -FLASH_Status FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY) -{ - FLASH_Status status = FLASH_COMPLETE; - uint32_t ob_user_rdp = 0; - uint8_t ob_user = 0,ob_nuser = 0; - - /* Check the parameters */ - assert_param(IS_OB_IWDG_SOURCE(OB_IWDG)); - assert_param(IS_OB_STOP_SOURCE(OB_STOP)); - assert_param(IS_OB_STDBY_SOURCE(OB_STDBY)); - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); - - ob_user = OB->USER_RDP >>16 & 0xF8;//Clear - ob_user |= OB_IWDG | OB_STOP | OB_STDBY; - ob_nuser = ~ob_user; - - ob_user_rdp = (OB->USER_RDP &0x0000ffff) | ob_user<<16 | ob_nuser<<24; - - if(status == FLASH_COMPLETE) - { - FLASH->CR |= FLASH_CR_OPTER; - FLASH->CR |= FLASH_CR_STRT; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); - - if(status == FLASH_COMPLETE) - { - /* If the erase operation is completed, disable the OPTER Bit */ - FLASH->CR &= ~FLASH_CR_OPTER; - /* Enable the Option Bytes Programming operation */ - FLASH->CR |= FLASH_CR_OPTPG; - - OB->USER_RDP = ob_user_rdp; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); - - if(status != FLASH_TIMEOUT) - { - /* If the program operation is completed, disable the OPTPG Bit */ - FLASH->CR &= ~FLASH_CR_OPTPG; - } - } - } - /* Return the Option Byte program Status */ - return status; -} - -/** - * @brief Sets or resets the BOOT1 option bit. - * @param OB_BOOT1: Set or Reset the BOOT1 option bit. - * This parameter can be one of the following values: - * @arg OB_BOOT1_RESET: BOOT1 option bit reset - * @arg OB_BOOT1_SET: BOOT1 option bit set - * @retval None - */ -FLASH_Status FLASH_OB_BOOTConfig(uint8_t OB_BOOT1) -{ - FLASH_Status status = FLASH_COMPLETE; - uint32_t ob_user_rdp = 0; - uint8_t ob_user =0,ob_nuser = 0; - - /* Check the parameters */ - assert_param(IS_OB_BOOT1(OB_BOOT1)); - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); - - ob_user = OB->USER_RDP >>16 & 0xef;//Clear - ob_user |= OB_BOOT1; - ob_nuser = ~ob_user; - ob_user_rdp = (OB->USER_RDP &0x0000ffff) | ob_user<<16 | ob_nuser<<24; - - if(status == FLASH_COMPLETE) - { - FLASH->CR |= FLASH_CR_OPTER; - FLASH->CR |= FLASH_CR_STRT; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); - - if(status == FLASH_COMPLETE) - { - /* If the erase operation is completed, disable the OPTER Bit */ - FLASH->CR &= ~FLASH_CR_OPTER; - /* Enable the Option Bytes Programming operation */ - FLASH->CR |= FLASH_CR_OPTPG; - - OB->USER_RDP = ob_user_rdp; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); - - if(status != FLASH_TIMEOUT) - { - /* If the program operation is completed, disable the OPTPG Bit */ - FLASH->CR &= ~FLASH_CR_OPTPG; - } - } - } - /* Return the Option Byte program Status */ - return status; -} - -/** - * @brief Sets or resets the analogue monitoring on VDDA Power source. - * @param OB_VDDA_ANALOG: Selects the analog monitoring on VDDA Power source. - * This parameter can be one of the following values: - * @arg OB_VDDA_ANALOG_ON: Analog monitoring on VDDA Power source ON - * @arg OB_VDDA_ANALOG_OFF: Analog monitoring on VDDA Power source OFF - * @retval None - */ -FLASH_Status FLASH_OB_VDDAConfig(uint8_t OB_VDDA_ANALOG) -{ - FLASH_Status status = FLASH_COMPLETE; - uint32_t ob_user_rdp = 0; - uint8_t ob_user = 0,ob_nuser = 0; - - /* Check the parameters */ - assert_param(IS_OB_VDDA_ANALOG(OB_VDDA_ANALOG)); - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); - - ob_user = OB->USER_RDP >>16 & 0xdf;//Clear - ob_user |= OB_VDDA_ANALOG; - ob_nuser = ~ob_user; - ob_user_rdp = (OB->USER_RDP &0x0000ffff) | ob_user<<16 | ob_nuser<<24; - - if(status == FLASH_COMPLETE) - { - FLASH->CR |= FLASH_CR_OPTER; - FLASH->CR |= FLASH_CR_STRT; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); - - if(status == FLASH_COMPLETE) - { - /* If the erase operation is completed, disable the OPTER Bit */ - FLASH->CR &= ~FLASH_CR_OPTER; - /* Enable the Option Bytes Programming operation */ - FLASH->CR |= FLASH_CR_OPTPG; - - OB->USER_RDP = ob_user_rdp; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); - - if(status != FLASH_TIMEOUT) - { - /* if the program operation is completed, disable the OPTPG Bit */ - FLASH->CR &= ~FLASH_CR_OPTPG; - } - } - } - /* Return the Option Byte program Status */ - return status; -} - -/** - * @brief Sets or resets the SRAM parity. - * @param OB_SRAM_Parity: Set or Reset the SRAM parity enable bit. - * This parameter can be one of the following values: - * @arg OB_SRAM_PARITY_SET: Set SRAM parity. - * @arg OB_SRAM_PARITY_RESET: Reset SRAM parity. - * @retval None - */ -FLASH_Status FLASH_OB_SRAMParityConfig(uint8_t OB_SRAM_Parity) -{ - FLASH_Status status = FLASH_COMPLETE; - uint32_t ob_user_rdp = 0; - uint8_t ob_user = 0,ob_nuser = 0; - - /* Check the parameters */ - assert_param(IS_OB_SRAM_PARITY(OB_SRAM_Parity)); - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); - - ob_user = OB->USER_RDP >>16 & 0xbf;//Clear - ob_user |= OB_SRAM_Parity; - ob_nuser = ~ob_user; - ob_user_rdp = (OB->USER_RDP &0x0000ffff) | ob_user<<16 | ob_nuser<<24; - - if(status == FLASH_COMPLETE) - { - FLASH->CR |= FLASH_CR_OPTER; - FLASH->CR |= FLASH_CR_STRT; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); - - if(status == FLASH_COMPLETE) - { - /* If the erase operation is completed, disable the OPTER Bit */ - FLASH->CR &= ~FLASH_CR_OPTER; - /* Enable the Option Bytes Programming operation */ - FLASH->CR |= FLASH_CR_OPTPG; - - OB->USER_RDP = ob_user_rdp; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); - - if(status != FLASH_TIMEOUT) - { - /* if the program operation is completed, disable the OPTPG Bit */ - FLASH->CR &= ~FLASH_CR_OPTPG; - } - } - } - /* Return the Option Byte program Status */ - return status; -} - -/** - * @brief Programs the FLASH User Option Byte: IWDG_SW, RST_STOP, RST_STDBY, - * BOOT1 and VDDA ANALOG monitoring. - * @note To correctly run this function, the FLASH_OB_Unlock() function must be called before. - * @note Call the FLASH_OB_Lock() to disable the flash control register access and the option - * bytes (recommended to protect the FLASH memory against possible unwanted operation) - * @param OB_USER: Selects all user option bytes - * This parameter is a combination of the following values: - * @arg OB_IWDG_SW / OB_IWDG_HW: Software / Hardware WDG selected - * @arg OB_STOP_NoRST / OB_STOP_RST: No reset / Reset generated when entering in STOP - * @arg OB_STDBY_NoRST / OB_STDBY_RST: No reset / Reset generated when entering in STANDBY - * @arg OB_BOOT1_RESET / OB_BOOT1_SET: BOOT1 Reset / Set - * @arg OB_VDDA_ANALOG_ON / OB_VDDA_ANALOG_OFF: Analog monitoring on VDDA Power source ON / OFF - * @arg OB_SRAM_PARITY_SET / OB_SRAM_PARITY_RESET: SRAM Parity SET / RESET - * @arg OB_BOOT0_RESET / OB_BOOT0_SET: BOOT0 Reset / Set - * @arg OB_BOOT0_SW / OB_BOOT0_SW: BOOT0 pin disabled / BOOT0 pin bonded with GPIO - * @retval FLASH Status: The returned value can be: - * FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. - */ -FLASH_Status FLASH_OB_WriteUser(uint8_t OB_USER) -{ - FLASH_Status status = FLASH_COMPLETE; - uint32_t ob_user_rdp = 0; - uint8_t ob_user = 0,ob_nuser = 0; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); - - ob_user = OB->USER_RDP >>16 & 0x00;//Clear - ob_user |= OB_USER; - ob_nuser = ~ob_user; - ob_user_rdp = (OB->USER_RDP &0x0000ffff) | ob_user<<16 | ob_nuser<<24; - - if(status == FLASH_COMPLETE) - { - FLASH->CR |= FLASH_CR_OPTER; - FLASH->CR |= FLASH_CR_STRT; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); - - if(status == FLASH_COMPLETE) - { - /* If the erase operation is completed, disable the OPTER Bit */ - FLASH->CR &= ~FLASH_CR_OPTER; - /* Enable the Option Bytes Programming operation */ - FLASH->CR |= FLASH_CR_OPTPG; - - OB->USER_RDP = ob_user_rdp; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); - - if(status != FLASH_TIMEOUT) - { - /* If the program operation is completed, disable the OPTPG Bit */ - FLASH->CR &= ~FLASH_CR_OPTPG; - } - } - } - /* Return the Option Byte program Status */ - return status; - -} - -/** - * @brief Programs a half word at a specified Option Byte Data address. - * @note To correctly run this function, the FLASH_OB_Unlock() function must be called before. - * @note Call the FLASH_OB_Lock() to disable the flash control register access and the option - * bytes (recommended to protect the FLASH memory against possible unwanted operation) - * @param Address: specifies the address to be programmed. - * This parameter can be 0x1FFFF804. - * @param Data: specifies the data to be programmed. - * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG, - * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. - */ -FLASH_Status FLASH_OB_ProgramData(uint32_t Address, uint32_t Data) -{ - FLASH_Status status = FLASH_COMPLETE; - - /* Check the parameters */ - assert_param(IS_OB_DATA_ADDRESS(Address)); - status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); - - if(status == FLASH_COMPLETE) - { - /* Enables the Option Bytes Programming operation */ - FLASH->CR |= FLASH_CR_OPTPG; - *(__IO uint32_t*)Address = Data; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); - - if(status != FLASH_TIMEOUT) - { - /* If the program operation is completed, disable the OPTPG Bit */ - FLASH->CR &= ~FLASH_CR_OPTPG; - } - } - /* Return the Option Byte Data Program Status */ - return status; -} -#endif - -/** - * @brief Returns the FLASH User Option Bytes values. - * @param None - * @retval The FLASH User Option Bytes . - */ -uint8_t FLASH_OB_GetUser(void) -{ - /* Return the User Option Byte */ - return (uint8_t)(FLASH->OBR >> 8); -} - -/** - * @brief Returns the FLASH Write Protection Option Bytes value. - * @param None - * @retval The FLASH Write Protection Option Bytes value - */ -uint32_t FLASH_OB_GetWRP(void) -{ - /* Return the FLASH write protection Register value */ - return (uint32_t)(FLASH->WRPR); -} - -/** - * @brief Checks whether the FLASH Read out Protection Status is set or not. - * @param None - * @retval FLASH ReadOut Protection Status(SET or RESET) - */ -FlagStatus FLASH_OB_GetRDP(void) -{ - FlagStatus readstatus = RESET; - - if ((uint8_t)(FLASH->OBR & (FLASH_OBR_RDPRT1 | FLASH_OBR_RDPRT2)) != RESET) - { - readstatus = SET; - } - else - { - readstatus = RESET; - } - return readstatus; -} - -/** - * @} - */ - -/** - * @brief Enables or disables the specified FLASH interrupts. - * @param FLASH_IT: specifies the FLASH interrupt sources to be enabled or - * disabled. - * This parameter can be any combination of the following values: - * @arg FLASH_IT_EOP: FLASH end of programming Interrupt - * @arg FLASH_IT_ERR: FLASH Error Interrupt - * @retval None - */ -void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FLASH_IT(FLASH_IT)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if(NewState != DISABLE) - { - /* Enable the interrupt sources */ - FLASH->CR |= FLASH_IT; - } - else - { - /* Disable the interrupt sources */ - FLASH->CR &= ~(uint32_t)FLASH_IT; - } -} - -/** - * @brief Checks whether the specified FLASH flag is set or not. - * @param FLASH_FLAG: specifies the FLASH flag to check. - * This parameter can be one of the following values: - * @arg FLASH_FLAG_BSY: FLASH write/erase operations in progress flag - * @arg FLASH_FLAG_PGERR: FLASH Programming error flag flag - * @arg FLASH_FLAG_WRPERR: FLASH Write protected error flag - * @arg FLASH_FLAG_EOP: FLASH End of Programming flag - * @retval The new state of FLASH_FLAG (SET or RESET). - */ -FlagStatus FLASH_GetFlagStatus(uint32_t FLASH_FLAG) -{ - FlagStatus bitstatus = RESET; - - /* Check the parameters */ - assert_param(IS_FLASH_GET_FLAG(FLASH_FLAG)); - - if((FLASH->SR & FLASH_FLAG) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - /* Return the new state of FLASH_FLAG (SET or RESET) */ - return bitstatus; -} - -/** - * @brief Clears the FLASH's pending flags. - * @param FLASH_FLAG: specifies the FLASH flags to clear. - * This parameter can be any combination of the following values: - * @arg FLASH_FLAG_PGERR: FLASH Programming error flag flag - * @arg FLASH_FLAG_WRPERR: FLASH Write protected error flag - * @arg FLASH_FLAG_EOP: FLASH End of Programming flag - * @retval None - */ -void FLASH_ClearFlag(uint32_t FLASH_FLAG) -{ - /* Check the parameters */ - assert_param(IS_FLASH_CLEAR_FLAG(FLASH_FLAG)); - - /* Clear the flags */ - FLASH->SR = FLASH_FLAG; -} - -/** - * @brief Returns the FLASH Status. - * @param None - * @retval FLASH Status: The returned value can be: - * FLASH_BUSY, FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP or FLASH_COMPLETE. - */ -FLASH_Status FLASH_GetStatus(void) -{ - FLASH_Status FLASHstatus = FLASH_COMPLETE; - - if((FLASH->SR & FLASH_FLAG_BSY) == FLASH_FLAG_BSY) - { - FLASHstatus = FLASH_BUSY; - } - else - { - if((FLASH->SR & (uint32_t)FLASH_FLAG_WRPERR)!= (uint32_t)0x00) - { - FLASHstatus = FLASH_ERROR_WRP; - } - else - { - if((FLASH->SR & (uint32_t)(FLASH_SR_PGERR)) != (uint32_t)0x00) - { - FLASHstatus = FLASH_ERROR_PROGRAM; - } - else - { - FLASHstatus = FLASH_COMPLETE; - } - } - } - /* Return the FLASH Status */ - return FLASHstatus; -} - - -/** - * @brief Waits for a FLASH operation to complete or a TIMEOUT to occur. - * @param Timeout: FLASH programming Timeout - * @retval FLASH Status: The returned value can be: FLASH_BUSY, - * FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. - */ -FLASH_Status FLASH_WaitForLastOperation(uint32_t Timeout) -{ - FLASH_Status status = FLASH_COMPLETE; - - /* Check for the FLASH Status */ - status = FLASH_GetStatus(); - - /* Wait for a FLASH operation to complete or a TIMEOUT to occur */ - while((status == FLASH_BUSY) && (Timeout != 0x00)) - { - status = FLASH_GetStatus(); - Timeout--; - } - - if(Timeout == 0x00 ) - { - status = FLASH_TIMEOUT; - } - /* Return the operation status */ - return status; -} - -/** - * @} - */ - -/** - * @} - */ - - /** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT FMD *****END OF FILE****/ diff --git a/bsp/ft32/libraries/FT32F0xx/FT32F0xx_Driver/Src/ft32f0xx_gpio.c b/bsp/ft32/libraries/FT32F0xx/FT32F0xx_Driver/Src/ft32f0xx_gpio.c deleted file mode 100644 index ef5172e4a77..00000000000 --- a/bsp/ft32/libraries/FT32F0xx/FT32F0xx_Driver/Src/ft32f0xx_gpio.c +++ /dev/null @@ -1,423 +0,0 @@ -/** - ****************************************************************************** - * @file ft32f0xx_gpio.c - * @author FMD AE - * @brief This file provides firmware functions to manage the following - * functionalities of the GPIO peripheral: - * + Initialization and Configuration functions - * + GPIO Read and Write functions - * + GPIO Alternate functions configuration functions - * @version V1.0.0 - * @data 2021-07-01 - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "ft32f0xx_gpio.h" -#include "ft32f0xx_rcc.h" - - -/** - * @brief Deinitializes the GPIOx peripheral registers to their default reset - * values. - * @param GPIOx: where x can be (A, B, C, D, E or F) to select the GPIO peripheral. - * @retval None - */ -void GPIO_DeInit(GPIO_TypeDef* GPIOx) -{ - /* Check the parameters */ - assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); - - if(GPIOx == GPIOA) - { - RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOA, ENABLE); - RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOA, DISABLE); - } - else if(GPIOx == GPIOB) - { - RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOB, ENABLE); - RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOB, DISABLE); - } - else if(GPIOx == GPIOC) - { - RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOC, ENABLE); - RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOC, DISABLE); - } - else if(GPIOx == GPIOD) - { - RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOD, ENABLE); - RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOD, DISABLE); - } -// else if(GPIOx == GPIOE) -// { -// RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOE, ENABLE); -// RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOE, DISABLE); -// } - else - { - if(GPIOx == GPIOF) - { - RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOF, ENABLE); - RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOF, DISABLE); - } - } -} - -/** - * @brief Initializes the GPIOx peripheral according to the specified - * parameters in the GPIO_InitStruct. - * @param GPIOx: where x can be (A, B, C, D, E or F) to select the GPIO peripheral. - * @param GPIO_InitStruct: pointer to a GPIO_InitTypeDef structure that contains - * the configuration information for the specified GPIO peripheral. - * @retval None - */ -void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct) -{ - uint32_t pinpos = 0x00, pos = 0x00 , currentpin = 0x00; - - /* Check the parameters */ - assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); - assert_param(IS_GPIO_PIN(GPIO_InitStruct->GPIO_Pin)); - assert_param(IS_GPIO_MODE(GPIO_InitStruct->GPIO_Mode)); - assert_param(IS_GPIO_PUPD(GPIO_InitStruct->GPIO_PuPd)); - - /*-------------------------- Configure the port pins -----------------------*/ - /*-- GPIO Mode Configuration --*/ - for (pinpos = 0x00; pinpos < 0x10; pinpos++) - { - pos = ((uint32_t)0x01) << pinpos; - - /* Get the port pins position */ - currentpin = (GPIO_InitStruct->GPIO_Pin) & pos; - - if (currentpin == pos) - { - if ((GPIO_InitStruct->GPIO_Mode == GPIO_Mode_OUT) || (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_AF)) - { - /* Check Speed mode parameters */ - assert_param(IS_GPIO_SPEED(GPIO_InitStruct->GPIO_Speed)); - - /* Speed mode configuration */ - GPIOx->OSPEEDR &= ~(GPIO_OSPEEDER_OSPEEDR0 << (pinpos * 2)); - GPIOx->OSPEEDR |= ((uint32_t)(GPIO_InitStruct->GPIO_Speed) << (pinpos * 2)); - - /* Check Output mode parameters */ - assert_param(IS_GPIO_OTYPE(GPIO_InitStruct->GPIO_OType)); - - /* Output mode configuration */ - GPIOx->OTYPER &= ~((GPIO_OTYPER_OT_0) << ((uint16_t)pinpos)); - GPIOx->OTYPER |= (uint16_t)(((uint16_t)GPIO_InitStruct->GPIO_OType) << ((uint16_t)pinpos)); - } - - GPIOx->MODER &= ~(GPIO_MODER_MODER0 << (pinpos * 2)); - - GPIOx->MODER |= (((uint32_t)GPIO_InitStruct->GPIO_Mode) << (pinpos * 2)); - - /* Pull-up Pull down resistor configuration */ - GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPDR0 << ((uint16_t)pinpos * 2)); - GPIOx->PUPDR |= (((uint32_t)GPIO_InitStruct->GPIO_PuPd) << (pinpos * 2)); - } - } -} - -/** - * @brief Fills each GPIO_InitStruct member with its default value. - * @param GPIO_InitStruct: pointer to a GPIO_InitTypeDef structure which will - * be initialized. - * @retval None - */ -void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct) -{ - /* Reset GPIO init structure parameters values */ - GPIO_InitStruct->GPIO_Pin = GPIO_Pin_All; - GPIO_InitStruct->GPIO_Mode = GPIO_Mode_IN; - GPIO_InitStruct->GPIO_Speed = GPIO_Speed_Level_2; - GPIO_InitStruct->GPIO_OType = GPIO_OType_PP; - GPIO_InitStruct->GPIO_PuPd = GPIO_PuPd_NOPULL; -} - -/** - * @brief Locks GPIO Pins configuration registers. - * @note The locked registers are GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR, - * GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH. - * @note The configuration of the locked GPIO pins can no longer be modified - * until the next device reset. - * @param GPIOx: where x can be (A or B) to select the GPIO peripheral. - * @param GPIO_Pin: specifies the port bit to be written. - * This parameter can be any combination of GPIO_Pin_x where x can be (0..15). - * @retval None - */ -void GPIO_PinLockConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) -{ - __IO uint32_t tmp = 0x00010000; - - /* Check the parameters */ - assert_param(IS_GPIO_LIST_PERIPH(GPIOx)); - assert_param(IS_GPIO_PIN(GPIO_Pin)); - - tmp |= GPIO_Pin; - /* Set LCKK bit */ - GPIOx->LCKR = tmp; - /* Reset LCKK bit */ - GPIOx->LCKR = GPIO_Pin; - /* Set LCKK bit */ - GPIOx->LCKR = tmp; - /* Read LCKK bit */ - tmp = GPIOx->LCKR; - /* Read LCKK bit */ - tmp = GPIOx->LCKR; -} - -/** - * @} - */ - -/** - * @brief Reads the specified input port pin. - * @param GPIOx: where x can be (A, B, C, D, E or F) to select the GPIO peripheral. - - * @param GPIO_Pin: specifies the port bit to read. - * @note This parameter can be GPIO_Pin_x where x can be: - * (0..15) for GPIOA, GPIOB, GPIOC, GPIOD, GPIOE, (0..10) for GPIOF. - * @retval The input port pin value. - */ -uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) -{ - uint8_t bitstatus = 0x00; - - /* Check the parameters */ - assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); - assert_param(IS_GET_GPIO_PIN(GPIO_Pin)); - - if ((GPIOx->IDR & GPIO_Pin) != (uint32_t)Bit_RESET) - { - bitstatus = (uint8_t)Bit_SET; - } - else - { - bitstatus = (uint8_t)Bit_RESET; - } - return bitstatus; -} - -/** - * @brief Reads the specified input port pin. - * @param GPIOx: where x can be (A, B, C, D, E or F) to select the GPIO peripheral. - * @retval The input port pin value. - */ -uint16_t GPIO_ReadInputData(GPIO_TypeDef* GPIOx) -{ - /* Check the parameters */ - assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); - - return ((uint16_t)GPIOx->IDR); -} - -/** - * @brief Reads the specified output data port bit. - * @param GPIOx: where x can be (A, B, C, D, E or F) to select the GPIO peripheral. - * @param GPIO_Pin: Specifies the port bit to read. - * @note This parameter can be GPIO_Pin_x where x can be: - * (0..15) for GPIOA, GPIOB, GPIOC, GPIOD, GPIOE, (0..10) for GPIOF. - * @retval The output port pin value. - */ -uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) -{ - uint8_t bitstatus = 0x00; - - /* Check the parameters */ - assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); - assert_param(IS_GET_GPIO_PIN(GPIO_Pin)); - - if ((GPIOx->ODR & GPIO_Pin) != (uint32_t)Bit_RESET) - { - bitstatus = (uint8_t)Bit_SET; - } - else - { - bitstatus = (uint8_t)Bit_RESET; - } - return bitstatus; -} - -/** - * @brief Reads the specified GPIO output data port. - * @param GPIOx: where x can be (A, B, C, D, E or F) to select the GPIO peripheral. - * @retval GPIO output data port value. - */ -uint16_t GPIO_ReadOutputData(GPIO_TypeDef* GPIOx) -{ - /* Check the parameters */ - assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); - - return ((uint16_t)GPIOx->ODR); -} - -/** - * @brief Sets the selected data port bits. - * @param GPIOx: where x can be (A, B, C, D, E or F) to select the GPIO peripheral. - * @param GPIO_Pin: specifies the port bits to be written. - * @note This parameter can be GPIO_Pin_x where x can be: - * (0..15) for GPIOA, GPIOB, GPIOC, GPIOD, GPIOE, (0..10) for GPIOF. - * @retval None - */ -void GPIO_SetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) -{ - /* Check the parameters */ - assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); - assert_param(IS_GPIO_PIN(GPIO_Pin)); - - GPIOx->BSRR = GPIO_Pin; -} - -/** - * @brief Clears the selected data port bits. - * @param GPIOx: where x can be (A, B, C, D, E or F) to select the GPIO peripheral. - * @param GPIO_Pin: specifies the port bits to be written. - * @note This parameter can be GPIO_Pin_x where x can be: - * (0..15) for GPIOA, GPIOB, GPIOC, GPIOD, GPIOE, (0..10) for GPIOF. - * @retval None - */ -void GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) -{ - /* Check the parameters */ - assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); - assert_param(IS_GPIO_PIN(GPIO_Pin)); - - GPIOx->BRR = GPIO_Pin; -} - -/** - * @brief Sets or clears the selected data port bit. - * @param GPIOx: where x can be (A, B, C, D, E or F) to select the GPIO peripheral. - * @param GPIO_Pin: specifies the port bit to be written. - * @param BitVal: specifies the value to be written to the selected bit. - * This parameter can be one of the BitAction enumeration values: - * @arg Bit_RESET: to clear the port pin - * @arg Bit_SET: to set the port pin - * @note This parameter can be GPIO_Pin_x where x can be: - * (0..15) for GPIOA, GPIOB, GPIOC, GPIOD, GPIOE, (0..10) for GPIOF. - * @retval None - */ -void GPIO_WriteBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, BitAction BitVal) -{ - /* Check the parameters */ - assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); - assert_param(IS_GET_GPIO_PIN(GPIO_Pin)); - assert_param(IS_GPIO_BIT_ACTION(BitVal)); - - if (BitVal != Bit_RESET) - { - GPIOx->BSRR = GPIO_Pin; - } - else - { - GPIOx->BRR = GPIO_Pin ; - } -} - -/** - * @brief Writes data to the specified GPIO data port. - * @param GPIOx: where x can be (A, B, C, D, E or F) to select the GPIO peripheral. - * @param PortVal: specifies the value to be written to the port output data register. - * @retval None - */ -void GPIO_Write(GPIO_TypeDef* GPIOx, uint16_t PortVal) -{ - /* Check the parameters */ - assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); - - GPIOx->ODR = PortVal; -} - -/** - * @} - */ - - -/** - * @brief Writes data to the specified GPIO data port. - * @param GPIOx: where x can be (A, B, C, D, E or F) to select the GPIO peripheral. - * @param GPIO_PinSource: specifies the pin for the Alternate function. - * This parameter can be GPIO_PinSourcex where x can be (0..15) for GPIOA, GPIOB, GPIOD, GPIOE - * and (0..12) for GPIOC and (0, 2..5, 9..10) for GPIOF. - * @param GPIO_AF: selects the pin to used as Alternate function. - * This parameter can be one of the following value: - * @arg GPIO_AF_0: WKUP, EVENTOUT, TIM15, SPI1, TIM17, MCO, SWDAT, SWCLK, - * TIM14, BOOT, USART1, CEC, IR_OUT, SPI2, TIM3, USART4, - * CAN, USART2, CRS, TIM16, TIM1, TS, USART8 - * @arg GPIO_AF_1: USART2, CEC, TIM3, USART1, USART2, EVENTOUT, I2C1, - * I2C2, TIM15, SPI2, USART3, TS, SPI1, USART7, USART8 - * USART5, USART4, USART6, I2C1 - * @arg GPIO_AF_2: TIM2, TIM1, EVENTOUT, TIM16, TIM17, USB, USART6, USART5, - * USART8, USART7, USART6 - * @arg GPIO_AF_3: TS, I2C1, TIM15, EVENTOUT - * @arg GPIO_AF_4: TIM14, USART4, USART3, CRS, CAN, I2C1, USART5 - * @arg GPIO_AF_5: TIM16, TIM17, TIM15, SPI2, I2C2, USART6, MCO - * @arg GPIO_AF_6: EVENTOUT - * @arg GPIO_AF_7: COMP1 OUT, COMP2 OUT - * @note The pin should already been configured in Alternate Function mode(AF) - * using GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF - * @note Refer to the Alternate function mapping table in the device datasheet - * for the detailed mapping of the system and peripherals'alternate - * function I/O pins. - * @retval None - */ -void GPIO_PinAFConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_PinSource, uint8_t GPIO_AF) -{ - uint32_t temp = 0x00; - uint32_t temp_2 = 0x00; - - /* Check the parameters */ - assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); - assert_param(IS_GPIO_PIN_SOURCE(GPIO_PinSource)); - assert_param(IS_GPIO_AF(GPIO_AF)); - - temp = ((uint32_t)(GPIO_AF) << ((uint32_t)((uint32_t)GPIO_PinSource & (uint32_t)0x07) * 4)); - GPIOx->AFR[GPIO_PinSource >> 0x03] &= ~((uint32_t)0xF << ((uint32_t)((uint32_t)GPIO_PinSource & (uint32_t)0x07) * 4)); - temp_2 = GPIOx->AFR[GPIO_PinSource >> 0x03] | temp; - GPIOx->AFR[GPIO_PinSource >> 0x03] = temp_2; -} - -/** - * @param GPIOx:GPIOA,GPIOB - * GPIO_LEDMx: - * GPIO_LEDM_0 - * GPIO_LEDM_1 - * GPIO_LEDM_3 - * GPIO_LEDM_4 - * GPIO_LEDM_5 - * GPIO_LEDM_6 - * GPIO_LEDM_7 - * GPIO_LEDM_8 - * GPIO_LEDM_9 - * GPIO_LEDM_10 - * GPIO_LEDM_13 - * GPIO_LEDM_14 - * GPIO_LEDM_15 - */ -void GPIO_LedmConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_LEDMx) -{ - /* Check the parameters */ - assert_param(IS_GPIO_LIST_PERIPH(GPIOx)); - assert_param(IS_GPIO_LEDM(GPIO_LEDMx)); - - GPIOx->LEDM |= (uint16_t)GPIO_LEDMx; -} -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT FMD *****END OF FILE****/ diff --git a/bsp/ft32/libraries/FT32F0xx/FT32F0xx_Driver/Src/ft32f0xx_i2c.c b/bsp/ft32/libraries/FT32F0xx/FT32F0xx_Driver/Src/ft32f0xx_i2c.c deleted file mode 100644 index 88281401889..00000000000 --- a/bsp/ft32/libraries/FT32F0xx/FT32F0xx_Driver/Src/ft32f0xx_i2c.c +++ /dev/null @@ -1,1256 +0,0 @@ -/** - ****************************************************************************** - * @file ft32f0xx_i2c.c - * @author FMD AE - * @brief This file provides firmware functions to manage the following - * functionalities of the Inter-Integrated circuit (I2C): - * + Initialization and Configuration - * + Communications handling - * + SMBUS management - * + I2C registers management - * + Data transfers management - * + DMA transfers management - * + Interrupts and flags management - * @version V1.0.0 - * @data 2021-07-01 - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "ft32f0xx_i2c.h" -#include "ft32f0xx_rcc.h" - - - -#define CR1_CLEAR_MASK ((uint32_t)0x00CFE0FF) /*I2C_AnalogFilter)); - assert_param(IS_I2C_DIGITAL_FILTER(I2C_InitStruct->I2C_DigitalFilter)); - assert_param(IS_I2C_MODE(I2C_InitStruct->I2C_Mode)); - assert_param(IS_I2C_OWN_ADDRESS1(I2C_InitStruct->I2C_OwnAddress1)); - assert_param(IS_I2C_ACK(I2C_InitStruct->I2C_Ack)); - assert_param(IS_I2C_ACKNOWLEDGE_ADDRESS(I2C_InitStruct->I2C_AcknowledgedAddress)); - - /* Disable I2Cx Peripheral */ - I2Cx->CR1 &= (uint32_t)~((uint32_t)I2C_CR1_PE); - - /*---------------------------- I2Cx FILTERS Configuration ------------------*/ - /* Get the I2Cx CR1 value */ - tmpreg = I2Cx->CR1; - /* Clear I2Cx CR1 register */ - tmpreg &= CR1_CLEAR_MASK; - /* Configure I2Cx: analog and digital filter */ - /* Set ANFOFF bit according to I2C_AnalogFilter value */ - /* Set DFN bits according to I2C_DigitalFilter value */ - tmpreg |= (uint32_t)I2C_InitStruct->I2C_AnalogFilter |(I2C_InitStruct->I2C_DigitalFilter << 8); - - /* Write to I2Cx CR1 */ - I2Cx->CR1 = tmpreg; - - /*---------------------------- I2Cx TIMING Configuration -------------------*/ - /* Configure I2Cx: Timing */ - /* Set TIMINGR bits according to I2C_Timing */ - /* Write to I2Cx TIMING */ - I2Cx->TIMINGR = I2C_InitStruct->I2C_Timing & TIMING_CLEAR_MASK; - - /* Enable I2Cx Peripheral */ - I2Cx->CR1 |= I2C_CR1_PE; - - /*---------------------------- I2Cx OAR1 Configuration ---------------------*/ - /* Clear tmpreg local variable */ - tmpreg = 0; - /* Clear OAR1 register */ - I2Cx->OAR1 = (uint32_t)tmpreg; - /* Clear OAR2 register */ - I2Cx->OAR2 = (uint32_t)tmpreg; - /* Configure I2Cx: Own Address1 and acknowledged address */ - /* Set OA1MODE bit according to I2C_AcknowledgedAddress value */ - /* Set OA1 bits according to I2C_OwnAddress1 value */ - tmpreg = (uint32_t)((uint32_t)I2C_InitStruct->I2C_AcknowledgedAddress | \ - (uint32_t)I2C_InitStruct->I2C_OwnAddress1); - /* Write to I2Cx OAR1 */ - I2Cx->OAR1 = tmpreg; - /* Enable Own Address1 acknowledgement */ - I2Cx->OAR1 |= I2C_OAR1_OA1EN; - - /*---------------------------- I2Cx MODE Configuration ---------------------*/ - /* Configure I2Cx: mode */ - /* Set SMBDEN and SMBHEN bits according to I2C_Mode value */ - tmpreg = I2C_InitStruct->I2C_Mode; - /* Write to I2Cx CR1 */ - I2Cx->CR1 |= tmpreg; - - /*---------------------------- I2Cx ACK Configuration ----------------------*/ - /* Get the I2Cx CR2 value */ - tmpreg = I2Cx->CR2; - /* Clear I2Cx CR2 register */ - tmpreg &= CR2_CLEAR_MASK; - /* Configure I2Cx: acknowledgement */ - /* Set NACK bit according to I2C_Ack value */ - tmpreg |= I2C_InitStruct->I2C_Ack; - /* Write to I2Cx CR2 */ - I2Cx->CR2 = tmpreg; -} - -/** - * @brief Fills each I2C_InitStruct member with its default value. - * @param I2C_InitStruct: pointer to an I2C_InitTypeDef structure which will be initialized. - * @retval None - */ -void I2C_StructInit(I2C_InitTypeDef* I2C_InitStruct) -{ - /*---------------- Reset I2C init structure parameters values --------------*/ - /* Initialize the I2C_Timing member */ - I2C_InitStruct->I2C_Timing = 0; - /* Initialize the I2C_AnalogFilter member */ - I2C_InitStruct->I2C_AnalogFilter = I2C_AnalogFilter_Enable; - /* Initialize the I2C_DigitalFilter member */ - I2C_InitStruct->I2C_DigitalFilter = 0; - /* Initialize the I2C_Mode member */ - I2C_InitStruct->I2C_Mode = I2C_Mode_I2C; - /* Initialize the I2C_OwnAddress1 member */ - I2C_InitStruct->I2C_OwnAddress1 = 0; - /* Initialize the I2C_Ack member */ - I2C_InitStruct->I2C_Ack = I2C_Ack_Disable; - /* Initialize the I2C_AcknowledgedAddress member */ - I2C_InitStruct->I2C_AcknowledgedAddress = I2C_AcknowledgedAddress_7bit; -} - -/** - * @brief Enables or disables the specified I2C peripheral. - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @param NewState: new state of the I2Cx peripheral. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void I2C_Cmd(I2C_TypeDef* I2Cx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the selected I2C peripheral */ - I2Cx->CR1 |= I2C_CR1_PE; - } - else - { - /* Disable the selected I2C peripheral */ - I2Cx->CR1 &= (uint32_t)~((uint32_t)I2C_CR1_PE); - } -} - -/** - * @brief Enables or disables the specified I2C software reset. - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @retval None - */ -void I2C_SoftwareResetCmd(I2C_TypeDef* I2Cx) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - - /* Disable peripheral */ - I2Cx->CR1 &= (uint32_t)~((uint32_t)I2C_CR1_PE); - - /* Perform a dummy read to delay the disable of peripheral for minimum - 3 APB clock cycles to perform the software reset functionality */ - *(__IO uint32_t *)(uint32_t)I2Cx; - - /* Enable peripheral */ - I2Cx->CR1 |= I2C_CR1_PE; -} - -/** - * @brief Enables or disables the specified I2C interrupts. - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @param I2C_IT: specifies the I2C interrupts sources to be enabled or disabled. - * This parameter can be any combination of the following values: - * @arg I2C_IT_ERRI: Error interrupt mask - * @arg I2C_IT_TCI: Transfer Complete interrupt mask - * @arg I2C_IT_STOPI: Stop Detection interrupt mask - * @arg I2C_IT_NACKI: Not Acknowledge received interrupt mask - * @arg I2C_IT_ADDRI: Address Match interrupt mask - * @arg I2C_IT_RXI: RX interrupt mask - * @arg I2C_IT_TXI: TX interrupt mask - * @param NewState: new state of the specified I2C interrupts. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void I2C_ITConfig(I2C_TypeDef* I2Cx, uint32_t I2C_IT, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - assert_param(IS_I2C_CONFIG_IT(I2C_IT)); - - if (NewState != DISABLE) - { - /* Enable the selected I2C interrupts */ - I2Cx->CR1 |= I2C_IT; - } - else - { - /* Disable the selected I2C interrupts */ - I2Cx->CR1 &= (uint32_t)~((uint32_t)I2C_IT); - } -} - -/** - * @brief Enables or disables the I2C Clock stretching. - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @param NewState: new state of the I2Cx Clock stretching. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void I2C_StretchClockCmd(I2C_TypeDef* I2Cx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable clock stretching */ - I2Cx->CR1 &= (uint32_t)~((uint32_t)I2C_CR1_NOSTRETCH); - } - else - { - /* Disable clock stretching */ - I2Cx->CR1 |= I2C_CR1_NOSTRETCH; - } -} - -/** - * @brief Enables or disables the I2C own address 2. - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @param NewState: new state of the I2C own address 2. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void I2C_DualAddressCmd(I2C_TypeDef* I2Cx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable own address 2 */ - I2Cx->OAR2 |= I2C_OAR2_OA2EN; - } - else - { - /* Disable own address 2 */ - I2Cx->OAR2 &= (uint32_t)~((uint32_t)I2C_OAR2_OA2EN); - } -} - -/** - * @brief Configures the I2C slave own address 2 and mask. - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @param Address: specifies the slave address to be programmed. - * @param Mask: specifies own address 2 mask to be programmed. - * This parameter can be one of the following values: - * @arg I2C_OA2_NoMask: no mask. - * @arg I2C_OA2_Mask01: OA2[1] is masked and don't care. - * @arg I2C_OA2_Mask02: OA2[2:1] are masked and don't care. - * @arg I2C_OA2_Mask03: OA2[3:1] are masked and don't care. - * @arg I2C_OA2_Mask04: OA2[4:1] are masked and don't care. - * @arg I2C_OA2_Mask05: OA2[5:1] are masked and don't care. - * @arg I2C_OA2_Mask06: OA2[6:1] are masked and don't care. - * @arg I2C_OA2_Mask07: OA2[7:1] are masked and don't care. - * @retval None - */ -void I2C_OwnAddress2Config(I2C_TypeDef* I2Cx, uint16_t Address, uint8_t Mask) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_I2C_OWN_ADDRESS2(Address)); - assert_param(IS_I2C_OWN_ADDRESS2_MASK(Mask)); - - /* Get the old register value */ - tmpreg = I2Cx->OAR2; - - /* Reset I2Cx OA2 bit [7:1] and OA2MSK bit [1:0] */ - tmpreg &= (uint32_t)~((uint32_t)(I2C_OAR2_OA2 | I2C_OAR2_OA2MSK)); - - /* Set I2Cx SADD */ - tmpreg |= (uint32_t)(((uint32_t)Address & I2C_OAR2_OA2) | \ - (((uint32_t)Mask << 8) & I2C_OAR2_OA2MSK)) ; - - /* Store the new register value */ - I2Cx->OAR2 = tmpreg; -} - -/** - * @brief Enables or disables the I2C general call mode. - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @param NewState: new state of the I2C general call mode. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void I2C_GeneralCallCmd(I2C_TypeDef* I2Cx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable general call mode */ - I2Cx->CR1 |= I2C_CR1_GCEN; - } - else - { - /* Disable general call mode */ - I2Cx->CR1 &= (uint32_t)~((uint32_t)I2C_CR1_GCEN); - } -} - -/** - * @brief Enables or disables the I2C slave byte control. - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @param NewState: new state of the I2C slave byte control. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void I2C_SlaveByteControlCmd(I2C_TypeDef* I2Cx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable slave byte control */ - I2Cx->CR1 |= I2C_CR1_SBC; - } - else - { - /* Disable slave byte control */ - I2Cx->CR1 &= (uint32_t)~((uint32_t)I2C_CR1_SBC); - } -} - -/** - * @brief Configures the slave address to be transmitted after start generation. - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @param Address: specifies the slave address to be programmed. - * @note This function should be called before generating start condition. - * @retval None - */ -void I2C_SlaveAddressConfig(I2C_TypeDef* I2Cx, uint16_t Address) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_I2C_SLAVE_ADDRESS(Address)); - - /* Get the old register value */ - tmpreg = I2Cx->CR2; - - /* Reset I2Cx SADD bit [9:0] */ - tmpreg &= (uint32_t)~((uint32_t)I2C_CR2_SADD); - - /* Set I2Cx SADD */ - tmpreg |= (uint32_t)((uint32_t)Address & I2C_CR2_SADD); - - /* Store the new register value */ - I2Cx->CR2 = tmpreg; -} - -/** - * @brief Enables or disables the I2C 10-bit addressing mode for the master. - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @param NewState: new state of the I2C 10-bit addressing mode. - * This parameter can be: ENABLE or DISABLE. - * @note This function should be called before generating start condition. - * @retval None - */ -void I2C_10BitAddressingModeCmd(I2C_TypeDef* I2Cx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable 10-bit addressing mode */ - I2Cx->CR2 |= I2C_CR2_ADD10; - } - else - { - /* Disable 10-bit addressing mode */ - I2Cx->CR2 &= (uint32_t)~((uint32_t)I2C_CR2_ADD10); - } -} - -/** - * @} - */ - - -/** - * @brief Enables or disables the I2C automatic end mode (stop condition is - * automatically sent when nbytes data are transferred). - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @param NewState: new state of the I2C automatic end mode. - * This parameter can be: ENABLE or DISABLE. - * @note This function has effect if Reload mode is disabled. - * @retval None - */ -void I2C_AutoEndCmd(I2C_TypeDef* I2Cx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable Auto end mode */ - I2Cx->CR2 |= I2C_CR2_AUTOEND; - } - else - { - /* Disable Auto end mode */ - I2Cx->CR2 &= (uint32_t)~((uint32_t)I2C_CR2_AUTOEND); - } -} - -/** - * @brief Enables or disables the I2C nbytes reload mode. - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @param NewState: new state of the nbytes reload mode. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void I2C_ReloadCmd(I2C_TypeDef* I2Cx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable Auto Reload mode */ - I2Cx->CR2 |= I2C_CR2_RELOAD; - } - else - { - /* Disable Auto Reload mode */ - I2Cx->CR2 &= (uint32_t)~((uint32_t)I2C_CR2_RELOAD); - } -} - -/** - * @brief Configures the number of bytes to be transmitted/received. - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @param Number_Bytes: specifies the number of bytes to be programmed. - * @retval None - */ -void I2C_NumberOfBytesConfig(I2C_TypeDef* I2Cx, uint8_t Number_Bytes) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - - /* Get the old register value */ - tmpreg = I2Cx->CR2; - - /* Reset I2Cx Nbytes bit [7:0] */ - tmpreg &= (uint32_t)~((uint32_t)I2C_CR2_NBYTES); - - /* Set I2Cx Nbytes */ - tmpreg |= (uint32_t)(((uint32_t)Number_Bytes << 16 ) & I2C_CR2_NBYTES); - - /* Store the new register value */ - I2Cx->CR2 = tmpreg; -} - -/** - * @brief Configures the type of transfer request for the master. - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @param I2C_Direction: specifies the transfer request direction to be programmed. - * This parameter can be one of the following values: - * @arg I2C_Direction_Transmitter: Master request a write transfer - * @arg I2C_Direction_Receiver: Master request a read transfer - * @retval None - */ -void I2C_MasterRequestConfig(I2C_TypeDef* I2Cx, uint16_t I2C_Direction) -{ -/* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_I2C_DIRECTION(I2C_Direction)); - - /* Test on the direction to set/reset the read/write bit */ - if (I2C_Direction == I2C_Direction_Transmitter) - { - /* Request a write Transfer */ - I2Cx->CR2 &= (uint32_t)~((uint32_t)I2C_CR2_RD_WRN); - } - else - { - /* Request a read Transfer */ - I2Cx->CR2 |= I2C_CR2_RD_WRN; - } -} - -/** - * @brief Generates I2Cx communication START condition. - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @param NewState: new state of the I2C START condition generation. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void I2C_GenerateSTART(I2C_TypeDef* I2Cx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Generate a START condition */ - I2Cx->CR2 |= I2C_CR2_START; - } - else - { - /* Disable the START condition generation */ - I2Cx->CR2 &= (uint32_t)~((uint32_t)I2C_CR2_START); - } -} - -/** - * @brief Generates I2Cx communication STOP condition. - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @param NewState: new state of the I2C STOP condition generation. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void I2C_GenerateSTOP(I2C_TypeDef* I2Cx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Generate a STOP condition */ - I2Cx->CR2 |= I2C_CR2_STOP; - } - else - { - /* Disable the STOP condition generation */ - I2Cx->CR2 &= (uint32_t)~((uint32_t)I2C_CR2_STOP); - } -} - -/** - * @brief Enables or disables the I2C 10-bit header only mode with read direction. - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @param NewState: new state of the I2C 10-bit header only mode. - * This parameter can be: ENABLE or DISABLE. - * @note This mode can be used only when switching from master transmitter mode - * to master receiver mode. - * @retval None - */ -void I2C_10BitAddressHeaderCmd(I2C_TypeDef* I2Cx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable 10-bit header only mode */ - I2Cx->CR2 |= I2C_CR2_HEAD10R; - } - else - { - /* Disable 10-bit header only mode */ - I2Cx->CR2 &= (uint32_t)~((uint32_t)I2C_CR2_HEAD10R); - } -} - -/** - * @brief Generates I2C communication Acknowledge. - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @param NewState: new state of the Acknowledge. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void I2C_AcknowledgeConfig(I2C_TypeDef* I2Cx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable ACK generation */ - I2Cx->CR2 &= (uint32_t)~((uint32_t)I2C_CR2_NACK); - } - else - { - /* Enable NACK generation */ - I2Cx->CR2 |= I2C_CR2_NACK; - } -} - -/** - * @brief Returns the I2C slave matched address . - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @retval The value of the slave matched address . - */ -uint8_t I2C_GetAddressMatched(I2C_TypeDef* I2Cx) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - - /* Return the slave matched address in the SR1 register */ - return (uint8_t)(((uint32_t)I2Cx->ISR & I2C_ISR_ADDCODE) >> 16) ; -} - -/** - * @brief Returns the I2C slave received request. - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @retval The value of the received request. - */ -uint16_t I2C_GetTransferDirection(I2C_TypeDef* I2Cx) -{ - uint32_t tmpreg = 0; - uint16_t direction = 0; - - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - - /* Return the slave matched address in the SR1 register */ - tmpreg = (uint32_t)(I2Cx->ISR & I2C_ISR_DIR); - - /* If write transfer is requested */ - if (tmpreg == 0) - { - /* write transfer is requested */ - direction = I2C_Direction_Transmitter; - } - else - { - /* Read transfer is requested */ - direction = I2C_Direction_Receiver; - } - return direction; -} - -/** - * @brief Handles I2Cx communication when starting transfer or during transfer (TC or TCR flag are set). - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @param Address: specifies the slave address to be programmed. - * @param Number_Bytes: specifies the number of bytes to be programmed. - * This parameter must be a value between 0 and 255. - * @param ReloadEndMode: new state of the I2C START condition generation. - * This parameter can be one of the following values: - * @arg I2C_Reload_Mode: Enable Reload mode . - * @arg I2C_AutoEnd_Mode: Enable Automatic end mode. - * @arg I2C_SoftEnd_Mode: Enable Software end mode. - * @param StartStopMode: new state of the I2C START condition generation. - * This parameter can be one of the following values: - * @arg I2C_No_StartStop: Don't Generate stop and start condition. - * @arg I2C_Generate_Stop: Generate stop condition (Number_Bytes should be set to 0). - * @arg I2C_Generate_Start_Read: Generate Restart for read request. - * @arg I2C_Generate_Start_Write: Generate Restart for write request. - * @retval None - */ -void I2C_TransferHandling(I2C_TypeDef* I2Cx, uint16_t Address, uint8_t Number_Bytes, uint32_t ReloadEndMode, uint32_t StartStopMode) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_I2C_SLAVE_ADDRESS(Address)); - assert_param(IS_RELOAD_END_MODE(ReloadEndMode)); - assert_param(IS_START_STOP_MODE(StartStopMode)); - - /* Get the CR2 register value */ - tmpreg = I2Cx->CR2; - - /* clear tmpreg specific bits */ - tmpreg &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | I2C_CR2_RD_WRN | I2C_CR2_START | I2C_CR2_STOP)); - - /* update tmpreg */ - tmpreg |= (uint32_t)(((uint32_t)Address & I2C_CR2_SADD) | (((uint32_t)Number_Bytes << 16 ) & I2C_CR2_NBYTES) | \ - (uint32_t)ReloadEndMode | (uint32_t)StartStopMode); - - /* update CR2 register */ - I2Cx->CR2 = tmpreg; -} - -/** - * @} - */ - -/** - * @brief Enables or disables I2C SMBus alert. - * @param I2Cx: where x can be 1 to select the I2C peripheral. - * @param NewState: new state of the I2Cx SMBus alert. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void I2C_SMBusAlertCmd(I2C_TypeDef* I2Cx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_I2C_1_PERIPH(I2Cx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable SMBus alert */ - I2Cx->CR1 |= I2C_CR1_ALERTEN; - } - else - { - /* Disable SMBus alert */ - I2Cx->CR1 &= (uint32_t)~((uint32_t)I2C_CR1_ALERTEN); - } -} - -/** - * @brief Enables or disables I2C Clock Timeout (SCL Timeout detection). - * @param I2Cx: where x can be 1 to select the I2C peripheral. - * @param NewState: new state of the I2Cx clock Timeout. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void I2C_ClockTimeoutCmd(I2C_TypeDef* I2Cx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_I2C_1_PERIPH(I2Cx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable Clock Timeout */ - I2Cx->TIMEOUTR |= I2C_TIMEOUTR_TIMOUTEN; - } - else - { - /* Disable Clock Timeout */ - I2Cx->TIMEOUTR &= (uint32_t)~((uint32_t)I2C_TIMEOUTR_TIMOUTEN); - } -} - -/** - * @brief Enables or disables I2C Extended Clock Timeout (SCL cumulative Timeout detection). - * @param I2Cx: where x can be 1 to select the I2C peripheral. - * @param NewState: new state of the I2Cx Extended clock Timeout. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void I2C_ExtendedClockTimeoutCmd(I2C_TypeDef* I2Cx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_I2C_1_PERIPH(I2Cx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable Clock Timeout */ - I2Cx->TIMEOUTR |= I2C_TIMEOUTR_TEXTEN; - } - else - { - /* Disable Clock Timeout */ - I2Cx->TIMEOUTR &= (uint32_t)~((uint32_t)I2C_TIMEOUTR_TEXTEN); - } -} - -/** - * @brief Enables or disables I2C Idle Clock Timeout (Bus idle SCL and SDA - * high detection). - * @param I2Cx: where x can be 1 to select the I2C peripheral. - * @param NewState: new state of the I2Cx Idle clock Timeout. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void I2C_IdleClockTimeoutCmd(I2C_TypeDef* I2Cx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_I2C_1_PERIPH(I2Cx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable Clock Timeout */ - I2Cx->TIMEOUTR |= I2C_TIMEOUTR_TIDLE; - } - else - { - /* Disable Clock Timeout */ - I2Cx->TIMEOUTR &= (uint32_t)~((uint32_t)I2C_TIMEOUTR_TIDLE); - } -} - -/** - * @brief Configures the I2C Bus Timeout A (SCL Timeout when TIDLE = 0 or Bus - * idle SCL and SDA high when TIDLE = 1). - * @param I2Cx: where x can be 1 to select the I2C peripheral. - * @param Timeout: specifies the TimeoutA to be programmed. - * @retval None - */ -void I2C_TimeoutAConfig(I2C_TypeDef* I2Cx, uint16_t Timeout) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_I2C_1_PERIPH(I2Cx)); - assert_param(IS_I2C_TIMEOUT(Timeout)); - - /* Get the old register value */ - tmpreg = I2Cx->TIMEOUTR; - - /* Reset I2Cx TIMEOUTA bit [11:0] */ - tmpreg &= (uint32_t)~((uint32_t)I2C_TIMEOUTR_TIMEOUTA); - - /* Set I2Cx TIMEOUTA */ - tmpreg |= (uint32_t)((uint32_t)Timeout & I2C_TIMEOUTR_TIMEOUTA) ; - - /* Store the new register value */ - I2Cx->TIMEOUTR = tmpreg; -} - -/** - * @brief Configures the I2C Bus Timeout B (SCL cumulative Timeout). - * @param I2Cx: where x can be 1 to select the I2C peripheral. - * @param Timeout: specifies the TimeoutB to be programmed. - * @retval None - */ -void I2C_TimeoutBConfig(I2C_TypeDef* I2Cx, uint16_t Timeout) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_I2C_1_PERIPH(I2Cx)); - assert_param(IS_I2C_TIMEOUT(Timeout)); - - /* Get the old register value */ - tmpreg = I2Cx->TIMEOUTR; - - /* Reset I2Cx TIMEOUTB bit [11:0] */ - tmpreg &= (uint32_t)~((uint32_t)I2C_TIMEOUTR_TIMEOUTB); - - /* Set I2Cx TIMEOUTB */ - tmpreg |= (uint32_t)(((uint32_t)Timeout << 16) & I2C_TIMEOUTR_TIMEOUTB) ; - - /* Store the new register value */ - I2Cx->TIMEOUTR = tmpreg; -} - -/** - * @brief Enables or disables I2C PEC calculation. - * @param I2Cx: where x can be 1 to select the I2C peripheral. - * @param NewState: new state of the I2Cx PEC calculation. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void I2C_CalculatePEC(I2C_TypeDef* I2Cx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_I2C_1_PERIPH(I2Cx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable PEC calculation */ - I2Cx->CR1 |= I2C_CR1_PECEN; - } - else - { - /* Disable PEC calculation */ - I2Cx->CR1 &= (uint32_t)~((uint32_t)I2C_CR1_PECEN); - } -} - -/** - * @brief Enables or disables I2C PEC transmission/reception request. - * @param I2Cx: where x can be 1 to select the I2C peripheral. - * @param NewState: new state of the I2Cx PEC request. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void I2C_PECRequestCmd(I2C_TypeDef* I2Cx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_I2C_1_PERIPH(I2Cx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable PEC transmission/reception request */ - I2Cx->CR2 |= I2C_CR2_PECBYTE; - } - else - { - /* Disable PEC transmission/reception request */ - I2Cx->CR2 &= (uint32_t)~((uint32_t)I2C_CR2_PECBYTE); - } -} - -/** - * @brief Returns the I2C PEC. - * @param I2Cx: where x can be 1 to select the I2C peripheral. - * @retval The value of the PEC . - */ -uint8_t I2C_GetPEC(I2C_TypeDef* I2Cx) -{ - /* Check the parameters */ - assert_param(IS_I2C_1_PERIPH(I2Cx)); - - /* Return the slave matched address in the SR1 register */ - return (uint8_t)((uint32_t)I2Cx->PECR & I2C_PECR_PEC); -} - -/** - * @} - */ - - - - /** - * @brief Reads the specified I2C register and returns its value. - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @param I2C_Register: specifies the register to read. - * This parameter can be one of the following values: - * @arg I2C_Register_CR1: CR1 register. - * @arg I2C_Register_CR2: CR2 register. - * @arg I2C_Register_OAR1: OAR1 register. - * @arg I2C_Register_OAR2: OAR2 register. - * @arg I2C_Register_TIMINGR: TIMING register. - * @arg I2C_Register_TIMEOUTR: TIMEOUTR register. - * @arg I2C_Register_ISR: ISR register. - * @arg I2C_Register_ICR: ICR register. - * @arg I2C_Register_PECR: PECR register. - * @arg I2C_Register_RXDR: RXDR register. - * @arg I2C_Register_TXDR: TXDR register. - * @retval The value of the read register. - */ -uint32_t I2C_ReadRegister(I2C_TypeDef* I2Cx, uint8_t I2C_Register) -{ - __IO uint32_t tmp = 0; - - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_I2C_REGISTER(I2C_Register)); - - tmp = (uint32_t)I2Cx; - tmp += I2C_Register; - - /* Return the selected register value */ - return (*(__IO uint32_t *) tmp); -} - -/** - * @} - */ - -/** - * @brief Sends a data byte through the I2Cx peripheral. - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @param Data: Byte to be transmitted.. - * @retval None - */ -void I2C_SendData(I2C_TypeDef* I2Cx, uint8_t Data) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - - /* Write in the DR register the data to be sent */ - I2Cx->TXDR = (uint8_t)Data; -} - -/** - * @brief Returns the most recent received data by the I2Cx peripheral. - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @retval The value of the received data. - */ -uint8_t I2C_ReceiveData(I2C_TypeDef* I2Cx) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - - /* Return the data in the DR register */ - return (uint8_t)I2Cx->RXDR; -} - -/** - * @} - */ - -/** - * @brief Enables or disables the I2C DMA interface. - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @param I2C_DMAReq: specifies the I2C DMA transfer request to be enabled or disabled. - * This parameter can be any combination of the following values: - * @arg I2C_DMAReq_Tx: Tx DMA transfer request - * @arg I2C_DMAReq_Rx: Rx DMA transfer request - * @param NewState: new state of the selected I2C DMA transfer request. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void I2C_DMACmd(I2C_TypeDef* I2Cx, uint32_t I2C_DMAReq, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - assert_param(IS_I2C_DMA_REQ(I2C_DMAReq)); - - if (NewState != DISABLE) - { - /* Enable the selected I2C DMA requests */ - I2Cx->CR1 |= I2C_DMAReq; - } - else - { - /* Disable the selected I2C DMA requests */ - I2Cx->CR1 &= (uint32_t)~I2C_DMAReq; - } -} -/** - * @} - */ -/** - * @brief Checks whether the specified I2C flag is set or not. - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @param I2C_FLAG: specifies the flag to check. - * This parameter can be one of the following values: - * @arg I2C_FLAG_TXE: Transmit data register empty - * @arg I2C_FLAG_TXIS: Transmit interrupt status - * @arg I2C_FLAG_RXNE: Receive data register not empty - * @arg I2C_FLAG_ADDR: Address matched (slave mode) - * @arg I2C_FLAG_NACKF: NACK received flag - * @arg I2C_FLAG_STOPF: STOP detection flag - * @arg I2C_FLAG_TC: Transfer complete (master mode) - * @arg I2C_FLAG_TCR: Transfer complete reload - * @arg I2C_FLAG_BERR: Bus error - * @arg I2C_FLAG_ARLO: Arbitration lost - * @arg I2C_FLAG_OVR: Overrun/Underrun - * @arg I2C_FLAG_PECERR: PEC error in reception - * @arg I2C_FLAG_TIMEOUT: Timeout or Tlow detection flag - * @arg I2C_FLAG_ALERT: SMBus Alert - * @arg I2C_FLAG_BUSY: Bus busy - * @retval The new state of I2C_FLAG (SET or RESET). - */ -FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG) -{ - uint32_t tmpreg = 0; - FlagStatus bitstatus = RESET; - - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_I2C_GET_FLAG(I2C_FLAG)); - - /* Get the ISR register value */ - tmpreg = I2Cx->ISR; - - /* Get flag status */ - tmpreg &= I2C_FLAG; - - if(tmpreg != 0) - { - /* I2C_FLAG is set */ - bitstatus = SET; - } - else - { - /* I2C_FLAG is reset */ - bitstatus = RESET; - } - return bitstatus; -} - -/** - * @brief Clears the I2Cx's pending flags. - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @param I2C_FLAG: specifies the flag to clear. - * This parameter can be any combination of the following values: - * @arg I2C_FLAG_ADDR: Address matched (slave mode) - * @arg I2C_FLAG_NACKF: NACK received flag - * @arg I2C_FLAG_STOPF: STOP detection flag - * @arg I2C_FLAG_BERR: Bus error - * @arg I2C_FLAG_ARLO: Arbitration lost - * @arg I2C_FLAG_OVR: Overrun/Underrun - * @arg I2C_FLAG_PECERR: PEC error in reception - * @arg I2C_FLAG_TIMEOUT: Timeout or Tlow detection flag - * @arg I2C_FLAG_ALERT: SMBus Alert - * @retval The new state of I2C_FLAG (SET or RESET). - */ -void I2C_ClearFlag(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_I2C_CLEAR_FLAG(I2C_FLAG)); - - /* Clear the selected flag */ - I2Cx->ICR = I2C_FLAG; -} - -/** - * @brief Checks whether the specified I2C interrupt has occurred or not. - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @param I2C_IT: specifies the interrupt source to check. - * This parameter can be one of the following values: - * @arg I2C_IT_TXIS: Transmit interrupt status - * @arg I2C_IT_RXNE: Receive data register not empty - * @arg I2C_IT_ADDR: Address matched (slave mode) - * @arg I2C_IT_NACKF: NACK received flag - * @arg I2C_IT_STOPF: STOP detection flag - * @arg I2C_IT_TC: Transfer complete (master mode) - * @arg I2C_IT_TCR: Transfer complete reload - * @arg I2C_IT_BERR: Bus error - * @arg I2C_IT_ARLO: Arbitration lost - * @arg I2C_IT_OVR: Overrun/Underrun - * @arg I2C_IT_PECERR: PEC error in reception - * @arg I2C_IT_TIMEOUT: Timeout or Tlow detection flag - * @arg I2C_IT_ALERT: SMBus Alert - * @retval The new state of I2C_IT (SET or RESET). - */ -ITStatus I2C_GetITStatus(I2C_TypeDef* I2Cx, uint32_t I2C_IT) -{ - uint32_t tmpreg = 0; - ITStatus bitstatus = RESET; - uint32_t enablestatus = 0; - - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_I2C_GET_IT(I2C_IT)); - - /* Check if the interrupt source is enabled or not */ - /* If Error interrupt */ - if ((uint32_t)(I2C_IT & ERROR_IT_MASK)) - { - enablestatus = (uint32_t)((I2C_CR1_ERRIE) & (I2Cx->CR1)); - } - /* If TC interrupt */ - else if ((uint32_t)(I2C_IT & TC_IT_MASK)) - { - enablestatus = (uint32_t)((I2C_CR1_TCIE) & (I2Cx->CR1)); - } - else - { - enablestatus = (uint32_t)((I2C_IT) & (I2Cx->CR1)); - } - - /* Get the ISR register value */ - tmpreg = I2Cx->ISR; - - /* Get flag status */ - tmpreg &= I2C_IT; - - /* Check the status of the specified I2C flag */ - if((tmpreg != RESET) && enablestatus) - { - /* I2C_IT is set */ - bitstatus = SET; - } - else - { - /* I2C_IT is reset */ - bitstatus = RESET; - } - - /* Return the I2C_IT status */ - return bitstatus; -} - -/** - * @brief Clears the I2Cx's interrupt pending bits. - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @param I2C_IT: specifies the interrupt pending bit to clear. - * This parameter can be any combination of the following values: - * @arg I2C_IT_ADDR: Address matched (slave mode) - * @arg I2C_IT_NACKF: NACK received flag - * @arg I2C_IT_STOPF: STOP detection flag - * @arg I2C_IT_BERR: Bus error - * @arg I2C_IT_ARLO: Arbitration lost - * @arg I2C_IT_OVR: Overrun/Underrun - * @arg I2C_IT_PECERR: PEC error in reception - * @arg I2C_IT_TIMEOUT: Timeout or Tlow detection flag - * @arg I2C_IT_ALERT: SMBus Alert - * @retval The new state of I2C_IT (SET or RESET). - */ -void I2C_ClearITPendingBit(I2C_TypeDef* I2Cx, uint32_t I2C_IT) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_I2C_CLEAR_IT(I2C_IT)); - - /* Clear the selected flag */ - I2Cx->ICR = I2C_IT; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT FMD *****END OF FILE****/ diff --git a/bsp/ft32/libraries/FT32F0xx/FT32F0xx_Driver/Src/ft32f0xx_iwdg.c b/bsp/ft32/libraries/FT32F0xx/FT32F0xx_Driver/Src/ft32f0xx_iwdg.c deleted file mode 100644 index 5b2a49f617c..00000000000 --- a/bsp/ft32/libraries/FT32F0xx/FT32F0xx_Driver/Src/ft32f0xx_iwdg.c +++ /dev/null @@ -1,167 +0,0 @@ -/** - ****************************************************************************** - * @file ft32f0xx_iwdg.c - * @author FMD AE - * @brief This file provides firmware functions to manage the following - * functionalities of the Independent watchdog (IWDG) peripheral: - * + Prescaler and Counter configuration - * + IWDG activation - * + Flag management - * @version V1.0.0 - * @data 2021-07-01 - ****************************************************************************** - */ -/* Includes ------------------------------------------------------------------*/ -#include "ft32f0xx_iwdg.h" - -/* ---------------------- IWDG registers bit mask ----------------------------*/ -/* KR register bit mask */ -#define KR_KEY_RELOAD ((uint16_t)0xAAAA) -#define KR_KEY_ENABLE ((uint16_t)0xCCCC) - - -/** - * @brief Enables or disables write access to IWDG_PR and IWDG_RLR registers. - * @param IWDG_WriteAccess: new state of write access to IWDG_PR and IWDG_RLR registers. - * This parameter can be one of the following values: - * @arg IWDG_WriteAccess_Enable: Enable write access to IWDG_PR and IWDG_RLR registers - * @arg IWDG_WriteAccess_Disable: Disable write access to IWDG_PR and IWDG_RLR registers - * @retval None - */ -void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess) -{ - /* Check the parameters */ - assert_param(IS_IWDG_WRITE_ACCESS(IWDG_WriteAccess)); - IWDG->KR = IWDG_WriteAccess; -} - -/** - * @brief Sets IWDG Prescaler value. - * @param IWDG_Prescaler: specifies the IWDG Prescaler value. - * This parameter can be one of the following values: - * @arg IWDG_Prescaler_4: IWDG prescaler set to 4 - * @arg IWDG_Prescaler_8: IWDG prescaler set to 8 - * @arg IWDG_Prescaler_16: IWDG prescaler set to 16 - * @arg IWDG_Prescaler_32: IWDG prescaler set to 32 - * @arg IWDG_Prescaler_64: IWDG prescaler set to 64 - * @arg IWDG_Prescaler_128: IWDG prescaler set to 128 - * @arg IWDG_Prescaler_256: IWDG prescaler set to 256 - * @retval None - */ -void IWDG_SetPrescaler(uint8_t IWDG_Prescaler) -{ - /* Check the parameters */ - assert_param(IS_IWDG_PRESCALER(IWDG_Prescaler)); - IWDG->PR = IWDG_Prescaler; -} - -/** - * @brief Sets IWDG Reload value. - * @param Reload: specifies the IWDG Reload value. - * This parameter must be a number between 0 and 0x0FFF. - * @retval None - */ -void IWDG_SetReload(uint16_t Reload) -{ - /* Check the parameters */ - assert_param(IS_IWDG_RELOAD(Reload)); - IWDG->RLR = Reload; -} - -/** - * @brief Reloads IWDG counter with value defined in the reload register - * (write access to IWDG_PR and IWDG_RLR registers disabled). - * @param None - * @retval None - */ -void IWDG_ReloadCounter(void) -{ - IWDG->KR = KR_KEY_RELOAD; -} - - -/** - * @brief Sets the IWDG window value. - * @param WindowValue: specifies the window value to be compared to the downcounter. - * @retval None - */ -void IWDG_SetWindowValue(uint16_t WindowValue) -{ - /* Check the parameters */ - assert_param(IS_IWDG_WINDOW_VALUE(WindowValue)); - IWDG->WINR = WindowValue; -} - -/** - * @} - */ - -/** @defgroup IWDG_Group2 IWDG activation function - * @brief IWDG activation function - * -@verbatim - ============================================================================== - ##### IWDG activation function ##### - ============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Enables IWDG (write access to IWDG_PR and IWDG_RLR registers disabled). - * @param None - * @retval None - */ -void IWDG_Enable(void) -{ - IWDG->KR = KR_KEY_ENABLE; -} - -/** - * @} - */ - -/** - * @brief Checks whether the specified IWDG flag is set or not. - * @param IWDG_FLAG: specifies the flag to check. - * This parameter can be one of the following values: - * @arg IWDG_FLAG_PVU: Prescaler Value Update on going - * @arg IWDG_FLAG_RVU: Reload Value Update on going - * @arg IWDG_FLAG_WVU: Counter Window Value Update on going - * @retval The new state of IWDG_FLAG (SET or RESET). - */ -FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG) -{ - FlagStatus bitstatus = RESET; - /* Check the parameters */ - assert_param(IS_IWDG_FLAG(IWDG_FLAG)); - if ((IWDG->SR & IWDG_FLAG) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - /* Return the flag status */ - return bitstatus; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT FMD *****END OF FILE****/ diff --git a/bsp/ft32/libraries/FT32F0xx/FT32F0xx_Driver/Src/ft32f0xx_misc.c b/bsp/ft32/libraries/FT32F0xx/FT32F0xx_Driver/Src/ft32f0xx_misc.c deleted file mode 100644 index cc50bec2628..00000000000 --- a/bsp/ft32/libraries/FT32F0xx/FT32F0xx_Driver/Src/ft32f0xx_misc.c +++ /dev/null @@ -1,112 +0,0 @@ -/** - ****************************************************************************** - * @file ft32f0xx_misc.c - * @author FMD AE - * @brief This file provides all the miscellaneous firmware functions (add-on - * to CMSIS functions). - * @version V1.0.0 - * @data 2021-07-01 - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "ft32f0xx_misc.h" - -/** - * @brief Initializes the NVIC peripheral according to the specified - * parameters in the NVIC_InitStruct. - * @param NVIC_InitStruct: pointer to a NVIC_InitTypeDef structure that contains - * the configuration information for the specified NVIC peripheral. - * @retval None - */ -void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct) -{ - uint32_t tmppriority = 0x00; - - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NVIC_InitStruct->NVIC_IRQChannelCmd)); - assert_param(IS_NVIC_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelPriority)); - - if (NVIC_InitStruct->NVIC_IRQChannelCmd != DISABLE) - { - /* Compute the Corresponding IRQ Priority --------------------------------*/ - tmppriority = NVIC->IP[NVIC_InitStruct->NVIC_IRQChannel >> 0x02]; - tmppriority &= (uint32_t)(~(((uint32_t)0xFF) << ((NVIC_InitStruct->NVIC_IRQChannel & 0x03) * 8))); - tmppriority |= (uint32_t)((((uint32_t)NVIC_InitStruct->NVIC_IRQChannelPriority << 6) & 0xFF) << ((NVIC_InitStruct->NVIC_IRQChannel & 0x03) * 8)); - - NVIC->IP[NVIC_InitStruct->NVIC_IRQChannel >> 0x02] = tmppriority; - - /* Enable the Selected IRQ Channels --------------------------------------*/ - NVIC->ISER[0] = (uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F); - } - else - { - /* Disable the Selected IRQ Channels -------------------------------------*/ - NVIC->ICER[0] = (uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F); - } -} - -/** - * @brief Selects the condition for the system to enter low power mode. - * @param LowPowerMode: Specifies the new mode for the system to enter low power mode. - * This parameter can be one of the following values: - * @arg NVIC_LP_SEVONPEND: Low Power SEV on Pend. - * @arg NVIC_LP_SLEEPDEEP: Low Power DEEPSLEEP request. - * @arg NVIC_LP_SLEEPONEXIT: Low Power Sleep on Exit. - * @param NewState: new state of LP condition. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_NVIC_LP(LowPowerMode)); - - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - SCB->SCR |= LowPowerMode; - } - else - { - SCB->SCR &= (uint32_t)(~(uint32_t)LowPowerMode); - } -} - -/** - * @brief Configures the SysTick clock source. - * @param SysTick_CLKSource: specifies the SysTick clock source. - * This parameter can be one of the following values: - * @arg SysTick_CLKSource_HCLK_Div8: AHB clock divided by 8 selected as SysTick clock source. - * @arg SysTick_CLKSource_HCLK: AHB clock selected as SysTick clock source. - * @retval None - */ -void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource) -{ - /* Check the parameters */ - assert_param(IS_SYSTICK_CLK_SOURCE(SysTick_CLKSource)); - - if (SysTick_CLKSource == SysTick_CLKSource_HCLK) - { - SysTick->CTRL |= SysTick_CLKSource_HCLK; - } - else - { - SysTick->CTRL &= SysTick_CLKSource_HCLK_Div8; - } -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT FMD *****END OF FILE****/ diff --git a/bsp/ft32/libraries/FT32F0xx/FT32F0xx_Driver/Src/ft32f0xx_opa.c b/bsp/ft32/libraries/FT32F0xx/FT32F0xx_Driver/Src/ft32f0xx_opa.c deleted file mode 100644 index 0c18e15e058..00000000000 --- a/bsp/ft32/libraries/FT32F0xx/FT32F0xx_Driver/Src/ft32f0xx_opa.c +++ /dev/null @@ -1,360 +0,0 @@ -/** - ****************************************************************************** - * @file ft32f0xx_opa.c - * @author FMD AE - * @brief This file provides firmware functions to manage the following - * functionalities of the comparators (OPA1 and OPA2) peripheral - * applicable only on FT32F030 devices: - * + Comparators configuration - * + Window mode control - * @version V1.0.0 - * @data 2021-07-01 - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "ft32f0xx_comp.h" -#include "ft32f0xx_opa.h" - -/* CSR register Mask */ -#define OPA_CR_CLEAR_MASK ((uint32_t)0x0003FFC1) - -/* Clear PRMAP BIT*/ -#define OPA_OP2_CLEAR_PRMAP ((uint32_t)0x00020000) - -/** - * @brief Deinitializes OPA peripheral registers to their default reset values. - * @note Deinitialization can't be performed if the OPA configuration is locked. - * To unlock the configuration, perform a system reset. - * @param OPAx: the selected comparator. - * This parameter can be one of the following values: - * @arg OPA: OPA1 selected - * @arg OPA2: OPA2 selected - * @retval None - */ -void OPA_DeInit(OPA_TypeDef* OPAx) -{ - /* Check the parameters */ - assert_param(IS_OPA_ALL_PERIPH(OPAx)); - - OPAx->CR = ((uint32_t)0x00000000); /*!< Set OPA_CSR register to reset value */ -} - -/** - * @brief Initializes the OPA peripheral according to the specified parameters - * in OPA_InitStruct - * @note If the selected comparator is locked, initialization can't be performed. - * To unlock the configuration, perform a system reset. - * @note To correctly run this function, the OPA_Cali() function must be called before. - * @param OPAx: the selected comparator. - * This parameter can be one of the following values: - * @arg OPA: OPA1 selected - * @arg OPA2: OPA2 selected - * @param OPA_InitStruct: pointer to an OPA_InitTypeDef structure that contains - * the configuration information for the specified OPA peripheral. - * @retval None - */ -void OPA_Init(OPA_TypeDef* OPAx, OPA_InitTypeDef* OPA_InitStruct) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_OPA_VIP_SEL(OPA_InitStruct->OPA_OP0PSel)); - assert_param(IS_OPA_VIN_SEL(OPA_InitStruct->OPA_OP0NSel)); - assert_param(IS_OPA_FR_SEL(OPA_InitStruct->OPA_OP0FR)); - assert_param(IS_OPA_FCAP_SEL(OPA_InitStruct->OPA_OP0FCAPE)); - assert_param(IS_OPA_ODIG_SEL(OPA_InitStruct->OPA_OPTODIG)); - assert_param(IS_OPA_OIO_SEL(OPA_InitStruct->OPA_OPTOIO)); - - /*!< Get the OPA_CR register value */ - tmpreg = OPAx->CR; - - /*!< Clear the bits */ - tmpreg &= (uint32_t) ~(OPA_CR_CLEAR_MASK); - - /*!< Configure OPA: OPA_VipSel, OPA_VinSel, OPA_OutputSel value and OPA_Pol */ - tmpreg |= (uint32_t)((OPA_InitStruct->OPA_OP0PSel | OPA_InitStruct->OPA_OP0NSel| - OPA_InitStruct->OPA_OP0FR | OPA_InitStruct->OPA_OP0FCAPE | OPA_InitStruct->OPA_OPTODIG |OPA_InitStruct->OPA_OPTOIO)); - - /*!< Write to OPA_CR register */ - OPAx->CR = tmpreg; -} - -/** - * @brief Fills each OPA_InitStruct member with its default value. - * @param OPA_InitStruct: pointer to an OPA_InitTypeDef structure which will - * be initialized. - * @retval None - */ -void OPA_StructInit(OPA_InitTypeDef* OPA_InitStruct) -{ - OPA_InitStruct->OPA_OP0PSel = 0x00000000; - OPA_InitStruct->OPA_OP0NSel = 0x00002000; - OPA_InitStruct->OPA_OP0FR = 0x00000000; - OPA_InitStruct->OPA_OP0FCAPE = 0x00000000; - OPA_InitStruct->OPA_OPTODIG = 0x00000080; - OPA_InitStruct->OPA_OPTOIO = 0x00000040; -} - -/** - * @brief Enable or disable the OPA peripheral. - * @note If the selected comparator is locked, enable/disable can't be performed. - * To unlock the configuration, perform a system reset. - * @param OPAx: the selected comparator. - * This parameter can be one of the following values: - * @arg OPA: OPA1 selected - * @arg OPA2: OPA2 selected - * @param NewState: new state of the OPA peripheral. - * This parameter can be: ENABLE or DISABLE. - * @note When enabled, the comparator compares the non inverting input with - * the inverting input and the comparison result is available on comparator output. - * @note When disabled, the comparator doesn't perform comparison and the - * output level is low. - * @retval None - */ -void OPA_Cmd(OPA_TypeDef* OPAx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_OPA_ALL_PERIPH(OPAx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the selected OPA peripheral */ - OPAx->CR |= OPA_OP1_ON; - } - else - { - /* Disable the selected OPA peripheral */ - OPAx->CR &= ~OPA_OP1_ON; - } -} - -/** - * @brief Return the output level (high or low) of the selected comparator. - * @note The output level depends on the selected polarity. - * @note If the polarity is not inverted: - * - Comparator output is low when the non-inverting input is at a lower - * voltage than the inverting input - * - Comparator output is high when the non-inverting input is at a higher - * voltage than the inverting input - * @note If the polarity is inverted: - * - Comparator output is high when the non-inverting input is at a lower - * voltage than the inverting input - * - Comparator output is low when the non-inverting input is at a higher - * voltage than the inverting input - * @param OPAx: the selected comparator. - * This parameter can be one of the following values: - * @arg OPA: OPA1 selected - * @arg OPA2: OPA2 selected - * @param OPA_OutLevel: - * This parameter can be one of the following values: - * @arg OPA_OutputLevel_High - * @arg OPA_OutputLevel_Low - * @retval Returns the selected comparator output level: low or high. - * - */ -uint32_t OPA_GetOutputLevel(OPA_TypeDef* OPAx, uint32_t OPA_OutLevel) -{ - uint32_t compout = 0x0; - - /* Check the parameters */ - assert_param(IS_OPA_ALL_PERIPH(OPAx)); - assert_param(IS_OPA_OUTPUT_LEVEL(OPA_OutLevel)); - - /* Check if selected comparator output is high */ - if ((OPAx->CR & OPA_OutLevel) != 0) - { - compout = OPA_OutLevel; - } - else - { - compout = OPA_OutputLevel_Low; - } - - /* Return the comparator output level */ - return (uint32_t)(compout); -} - -/** - * @brief Return the output level (high or low) of the selected comparator. - * @note The output level depends on the selected polarity. - * @param OPAx: the selected comparator. - * This parameter can be one of the following values: - * @arg OPA: OPA1 selected - * @arg OPA2: OPA2 selected - * @retval Returns: 0：fail others：The calibration value - * - */ -uint8_t OPA_Cali(OPA_TypeDef* OPAx) -{ - uint32_t opadelay; - uint32_t outstate; - uint8_t CalDA, CalDB; - uint32_t opatmp32; - uint32_t delay_time = 0x1fff; - - /* Check the parameters */ - assert_param(IS_OPA_ALL_PERIPH(OPAx)); - - /* Enable the selected OPA peripheral */ - OPAx->CR |= OPA_OP1_ON; - - /* Enable OP0TM */ - OPAx->CR |= OPA_OP1_TM; - - /* OP0NSEL = 00 , SET TO GND */ - OPAx->CR &= ~OPA_OP1_NSEL; - - /* OP0PSEL = 1 , SET TO GND */ - OPAx->CR |= OPA_OP1_PSEL; - - /* OP0FCAPE = 0 */ - OPAx->CR &= ~OPA_OP1_FCAPE; - - /* OPTODIG = 1 */ - OPAx->CR |= OPA_OP1_TODIG; - - /* OP0FR = 000 */ - OPAx->CR &= ~OPA_OP1_FR; - - if (OPAx == OPA) - { - /* PA2 TO FLOAT */ - GPIOA ->PUPDR &= ~(GPIO_PUPDR_PUPDR0 << ((uint32_t)2 * 2)); - } - else - { - /* Clear PRMAP */ - OPAx->CR &= (~OPA_OP2_CLEAR_PRMAP); - - /* PF4 TO FLOAT */ - GPIOF ->PUPDR &= ~(GPIO_PUPDR_PUPDR0 << ((uint32_t)4 * 2)); - } - - #if defined (FT32F072xB) - /* OP0COF = 00000 */ - OPAx->CR &= ~OPA_OP1_COF; - CalDA = 0; - opadelay = delay_time; - while(opadelay--); - outstate = OPAx->CR; // save - - for(;;) - { - CalDA++; - if(CalDA >= 0x1F) - return 0; //fail - - opatmp32 = OPAx->CR & (~OPA_OP1_COF); - OPAx->CR = opatmp32 | (CalDA << 1); - opadelay = delay_time; - while(opadelay--); - - if( (outstate ^ OPAx->CR) & OPA_OP1_OUT) - break; - } - - OPAx->CR |= OPA_OP1_COF; //0x1F - CalDB = 0x1F; - opadelay = delay_time; - while(opadelay--); - outstate = OPAx->CR; // save - - for(;;) - { - if(0 == CalDB) - return 0; - - CalDB--; - opatmp32 = OPAx->CR & (~OPA_OP1_COF); - OPAx->CR = opatmp32 | (CalDB << 1); - opadelay = delay_time; - while(opadelay--); - - if( (outstate ^ OPAx->CR) & OPA_OP1_OUT ) - break; - } - - CalDA+= CalDB; - CalDA/= 2; - opatmp32 = OPAx->CR & (~OPA_OP1_COF); - OPAx->CR = opatmp32 | (CalDA << 1); - #else - /* OP0COF = 10000 */ - OPAx->CR &= ~OPA_OP1_COF; - OPAx->CR |= OPA_OP1_COF_4; - CalDA = 0; - opadelay = delay_time; - while(opadelay--); - outstate = OPAx->CR; // save - - for(;;) - { - CalDA++; - if(CalDA >= 0x0F) - return 0; - - opatmp32 = OPAx->CR & (~OPA_OP1_COF); - OPAx->CR = opatmp32 | (CalDA << 1); - opadelay = delay_time; - while(opadelay--); - - if((outstate^OPAx->CR) & OPA_OP1_OUT) - break; - } - - OPAx->CR &= ~OPA_OP1_COF; - OPAx->CR |= OPA_OP1_COF_0 | OPA_OP1_COF_1 | OPA_OP1_COF_2 | OPA_OP1_COF_3; //0x0F - CalDB = 0x0F; - opadelay = delay_time; - while(opadelay--); - outstate = OPAx->CR; // save - - for(;;) - { - if(0 == CalDB) - return 0; - - CalDB--; - opatmp32 = OPAx->CR & (~OPA_OP1_COF); - OPAx->CR = opatmp32 | (CalDB << 1); - opadelay = delay_time; - while(opadelay--); - - if( (outstate^OPAx->CR) & OPA_OP1_OUT ) - break; - } - - CalDA+= CalDB; - CalDA/= 2; - opatmp32 = OPAx->CR & (~OPA_OP1_COF); - OPAx->CR = opatmp32 | (CalDA << 1); - #endif - - return CalDA; -} - - - - - - - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT FMD *****END OF FILE****/ diff --git a/bsp/ft32/libraries/FT32F0xx/FT32F0xx_Driver/Src/ft32f0xx_pwr.c b/bsp/ft32/libraries/FT32F0xx/FT32F0xx_Driver/Src/ft32f0xx_pwr.c deleted file mode 100644 index 4ef218c9bc0..00000000000 --- a/bsp/ft32/libraries/FT32F0xx/FT32F0xx_Driver/Src/ft32f0xx_pwr.c +++ /dev/null @@ -1,366 +0,0 @@ -/** - ****************************************************************************** - * @file ft32f0xx_pwr.c - * @author FMD AE - * @brief This file provides firmware functions to manage the following - * functionalities of the Power Controller (PWR) peripheral: - * + Backup Domain Access - * + PVD configuration - * + WakeUp pins configuration - * + Low Power modes configuration - * + Flags management - * @version V1.0.0 - * @data 2021-07-01 - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "ft32f0xx_pwr.h" -#include "ft32f0xx_rcc.h" - - -/* ------------------ PWR registers bit mask ------------------------ */ - -/* CR register bit mask */ -#define CR_DS_MASK ((uint32_t)0xFFFFFFFC) -#define CR_PLS_MASK ((uint32_t)0xFFFFFD1F) - - -/** - * @brief Deinitializes the PWR peripheral registers to their default reset values. - * @param None - * @retval None - */ -void PWR_DeInit(void) -{ - RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, DISABLE); -} - -/** - * @brief Enables or disables access to the Backup domain registers. - * @note If the HSE divided by 32 is used as the RTC clock, the - * Backup Domain Access should be kept enabled. - * @param NewState: new state of the access to the Backup domain registers. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void PWR_BackupAccessCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the Backup Domain Access */ - PWR->CR |= PWR_CR_DBP; - } - else - { - /* Disable the Backup Domain Access */ - PWR->CR &= (uint32_t)~((uint32_t)PWR_CR_DBP); - } -} - -/** - * @} - */ - -/** - * @brief Configures the voltage threshold detected by the Power Voltage Detector(PVD). - * @param PWR_PVDLevel: specifies the PVD detection level - * This parameter can be one of the following values: - * @arg PWR_PVDLevel_0 - * @arg PWR_PVDLevel_1 - * @arg PWR_PVDLevel_2 - * @arg PWR_PVDLevel_3 - * @arg PWR_PVDLevel_4 - * @arg PWR_PVDLevel_5 - * @arg PWR_PVDLevel_6 - * @arg PWR_PVDLevel_7 - * @arg PWR_PVDLevel_8 - * @arg PWR_PVDLevel_9 - * @arg PWR_PVDLevel_10 - * @arg PWR_PVDLevel_11 - * @arg PWR_PVDLevel_12 - * @arg PWR_PVDLevel_13 - * @arg PWR_PVDLevel_14 - * @arg PWR_PVDLevel_15 - * @note Refer to the electrical characteristics of your device datasheet for - * more details about the voltage threshold corresponding to each - * detection level. - * @retval None - */ -void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_PWR_PVD_LEVEL(PWR_PVDLevel)); - - tmpreg = PWR->CR; - - /* Clear PLS[7:5] bits PLS3*/ - tmpreg &= CR_PLS_MASK; - - /* Set PLS[7:5] and PLS3 bits according to PWR_PVDLevel value */ - tmpreg |= PWR_PVDLevel; - - /* Store the new value */ - PWR->CR = tmpreg; -} - -/** - * @brief Enables or disables the Power Voltage Detector(PVD). - * @param NewState: new state of the PVD. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void PWR_PVDCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the PVD */ - PWR->CR |= PWR_CR_PVDE; - } - else - { - /* Disable the PVD */ - PWR->CR &= (uint32_t)~((uint32_t)PWR_CR_PVDE); - } -} - -/** - * @} - */ -/** - * @brief Enables or disables the WakeUp Pin functionality. - * @param PWR_WakeUpPin: specifies the WakeUpPin. - * This parameter can be one of the following values - * @arg PWR_WakeUpPin_1 - * @arg PWR_WakeUpPin_2 - * @arg PWR_WakeUpPin_3 - * @arg PWR_WakeUpPin_4 - * @arg PWR_WakeUpPin_5 - * @arg PWR_WakeUpPin_6 - * @arg PWR_WakeUpPin_7 - * @arg PWR_WakeUpPin_8 - * @param NewState: new state of the WakeUp Pin functionality. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void PWR_WakeUpPinCmd(uint32_t PWR_WakeUpPin, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_PWR_WAKEUP_PIN(PWR_WakeUpPin)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the EWUPx pin */ - PWR->CSR |= PWR_WakeUpPin; - } - else - { - /* Disable the EWUPx pin */ - PWR->CSR &= ~PWR_WakeUpPin; - } -} - -/** - * @} - */ - -/** - * @brief Enters Sleep mode. - * @note In Sleep mode, all I/O pins keep the same state as in Run mode. - * @param PWR_SLEEPEntry: specifies if SLEEP mode in entered with WFI or WFE instruction. - * This parameter can be one of the following values: - * @arg PWR_SLEEPEntry_WFI: enter SLEEP mode with WFI instruction - * @arg PWR_SLEEPEntry_WFE: enter SLEEP mode with WFE instruction - * @retval None - */ -void PWR_EnterSleepMode(uint8_t PWR_SLEEPEntry) -{ - /* Check the parameters */ - assert_param(IS_PWR_SLEEP_ENTRY(PWR_SLEEPEntry)); - - /* Clear SLEEPDEEP bit of Cortex-M0 System Control Register */ - SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk); - - /* Select SLEEP mode entry -------------------------------------------------*/ - if(PWR_SLEEPEntry == PWR_SLEEPEntry_WFI) - { - /* Request Wait For Interrupt */ - __WFI(); - } - else - { - /* Request Wait For Event */ - __SEV(); - __WFE(); - __WFE(); - } -} - -/** - * @brief Enters STOP mode. - * @note In Stop mode, all I/O pins keep the same state as in Run mode. - * @note When exiting Stop mode by issuing an interrupt or a wakeup event, - * the HSI RC oscillator is selected as system clock. - * @note When the voltage regulator operates in low power mode, an additional - * startup delay is incurred when waking up from Stop mode. - * By keeping the internal regulator ON during Stop mode, the consumption - * is higher although the startup time is reduced. - * @param PWR_Regulator: specifies the regulator state in STOP mode. - * This parameter can be one of the following values: - * @arg PWR_Regulator_ON: STOP mode with regulator ON - * @arg PWR_Regulator_LowPower: STOP mode with regulator in low power mode - * @param PWR_STOPEntry: specifies if STOP mode in entered with WFI or WFE instruction. - * This parameter can be one of the following values: - * @arg PWR_STOPEntry_WFI: enter STOP mode with WFI instruction - * @arg PWR_STOPEntry_WFE: enter STOP mode with WFE instruction - @arg PWR_STOPEntry_SLEEPONEXIT: enter STOP mode with SLEEPONEXIT instruction - * @retval None - */ -void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_PWR_REGULATOR(PWR_Regulator)); - assert_param(IS_PWR_STOP_ENTRY(PWR_STOPEntry)); - - /* Select the regulator state in STOP mode ---------------------------------*/ - tmpreg = PWR->CR; - /* Clear PDDS and LPDSR bits */ - tmpreg &= CR_DS_MASK; - - /* Set LPDSR bit according to PWR_Regulator value */ - tmpreg |= PWR_Regulator; - - /* Store the new value */ - PWR->CR = tmpreg; - - /* Set SLEEPDEEP bit of Cortex-M0 System Control Register */ - SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; - - /* Select STOP mode entry --------------------------------------------------*/ - if(PWR_STOPEntry == PWR_STOPEntry_WFI) - { - /* Request Wait For Interrupt */ - __WFI(); - /* Reset SLEEPDEEP bit of Cortex System Control Register */ - SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk); - } - else if (PWR_STOPEntry == PWR_STOPEntry_WFE) - { - /* Request Wait For Event */ - __WFE(); - /* Reset SLEEPDEEP bit of Cortex System Control Register */ - SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk); - } - else - { - /* Set SLEEP on exit bit of Cortex-M0 System Control Register */ - SCB->SCR |= SCB_SCR_SLEEPONEXIT_Msk; - } -} - -/** - * @brief Enters STANDBY mode. - * @note In Standby mode, all I/O pins are high impedance except for: - * - Reset pad (still available) - * - RTC_AF1 pin (PC13) if configured for Wakeup pin 2 (WKUP2), tamper, - * time-stamp, RTC Alarm out, or RTC clock calibration out. - * - WKUP pin 1 (PA0) if enabled. - * @note The Wakeup flag (WUF) need to be cleared at application level before to call this function - * @param None - * @retval None - */ -void PWR_EnterSTANDBYMode(void) -{ - /* Select STANDBY mode */ - PWR->CR |= PWR_CR_PDDS; - - /* Set SLEEPDEEP bit of Cortex-M0 System Control Register */ - SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; - - /* Request Wait For Interrupt */ - __WFI(); -} - -/** - * @} - */ - -/** - * @brief Checks whether the specified PWR flag is set or not. - * @param PWR_FLAG: specifies the flag to check. - * This parameter can be one of the following values: - * @arg PWR_FLAG_WU: Wake Up flag. This flag indicates that a wakeup - * event was received from the WKUP pin or from the RTC alarm - * (Alarm A or Alarm B), RTC Tamper event or RTC TimeStamp event. - * @arg PWR_FLAG_SB: StandBy flag. This flag indicates that the - * system was resumed from StandBy mode. - * @arg PWR_FLAG_PVDO: PVD Output. This flag is valid only if PVD - * is enabled by the PWR_PVDCmd() function. - * @arg PWR_FLAG_VREFINTRDY: Internal Voltage Reference Ready flag. - * This flag indicates the state of the internal voltage - * reference, VREFINT. - * @retval The new state of PWR_FLAG (SET or RESET). - */ -FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG) -{ - FlagStatus bitstatus = RESET; - /* Check the parameters */ - assert_param(IS_PWR_GET_FLAG(PWR_FLAG)); - - if ((PWR->CSR & PWR_FLAG) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - /* Return the flag status */ - return bitstatus; -} - -/** - * @brief Clears the PWR's pending flags. - * @param PWR_FLAG: specifies the flag to clear. - * This parameter can be one of the following values: - * @arg PWR_FLAG_WU: Wake Up flag - * @arg PWR_FLAG_SB: StandBy flag - * @retval None - */ -void PWR_ClearFlag(uint32_t PWR_FLAG) -{ - /* Check the parameters */ - assert_param(IS_PWR_CLEAR_FLAG(PWR_FLAG)); - - PWR->CR |= PWR_FLAG << 2; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT FMD *****END OF FILE****/ diff --git a/bsp/ft32/libraries/FT32F0xx/FT32F0xx_Driver/Src/ft32f0xx_rcc.c b/bsp/ft32/libraries/FT32F0xx/FT32F0xx_Driver/Src/ft32f0xx_rcc.c deleted file mode 100644 index 5a9332cb3e5..00000000000 --- a/bsp/ft32/libraries/FT32F0xx/FT32F0xx_Driver/Src/ft32f0xx_rcc.c +++ /dev/null @@ -1,1509 +0,0 @@ -/** - ****************************************************************************** - * @file ft32f0xx_rcc.c - * @author FMD AE - * @brief This file provides firmware functions to manage the following - * functionalities of the Reset and clock control (RCC) peripheral: - * + Internal/external clocks, PLL, CSS and MCO configuration - * + System, AHB and APB busses clocks configuration - * + Peripheral clocks configuration - * + Interrupts and flags management - * @version V1.0.0 - * @data 2021-07-01 - ****************************************************************************** - */ - - -/* Includes ------------------------------------------------------------------*/ -#include "ft32f0xx_rcc.h" - - -/* ---------------------- RCC registers mask -------------------------------- */ -/* RCC Flag Mask */ -#define FLAG_MASK ((uint8_t)0x1F) - -/* CR register byte 2 (Bits[23:16]) base address */ -#define CR_BYTE2_ADDRESS ((uint32_t)0x40021002) - -/* CFGR register byte 3 (Bits[31:23]) base address */ -#define CFGR_BYTE3_ADDRESS ((uint32_t)0x40021007) - -/* CIR register byte 1 (Bits[15:8]) base address */ -#define CIR_BYTE1_ADDRESS ((uint32_t)0x40021009) - -/* CIR register byte 2 (Bits[23:16]) base address */ -#define CIR_BYTE2_ADDRESS ((uint32_t)0x4002100A) - -static __I uint8_t APBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9}; - -/** - * @brief Resets the RCC clock configuration to the default reset state. - * @note The default reset state of the clock configuration is given below: - * @note HSI ON and used as system clock source - * @note HSI14, HSE and PLL OFF - * @note AHB, APB prescaler set to 1. - * @note CSS and MCO OFF - * @note All interrupts disabled - * @note However, this function doesn't modify the configuration of the - * @note Peripheral clocks - * @note LSI, LSE and RTC clocks - * @param None - * @retval None - */ -void RCC_DeInit(void) -{ - /* Set HSION bit */ - RCC->CR |= (uint32_t)0x00000001; - - /* Reset SW[1:0], HPRE[3:0], PPRE[2:0], ADCPRE, MCOSEL[2:0], MCOPRE[2:0] and PLLNODIV bits */ - RCC->CFGR &= (uint32_t)0x08FFB80C; - - /* Reset HSEON, CSSON and PLLON bits */ - RCC->CR &= (uint32_t)0xFEF6FFFF; - - /* Reset HSEBYP bit */ - RCC->CR &= (uint32_t)0xFFFBFFFF; - - /* Reset PLLSRC, PLLXTPRE and PLLMUL[3:0] bits */ - RCC->CFGR &= (uint32_t)0xFFC0FFFF; - - /* Reset PREDIV1[3:0] bits */ - RCC->CFGR2 &= (uint32_t)0xFFFFFFF0; - - /* Reset USARTSW[1:0], I2CSW, CECSW and ADCSW bits */ - RCC->CFGR3 &= (uint32_t)0xFFF0FEAC; - - /* Reset HSI14 bit */ - RCC->CR2 &= (uint32_t)0xFFFFFFFE; - - /* Disable all interrupts */ - RCC->CIR = 0x00000000; -} - -/** - * @brief Configures the External High Speed oscillator (HSE). - * @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application - * software should wait on HSERDY flag to be set indicating that HSE clock - * is stable and can be used to clock the PLL and/or system clock. - * @note HSE state can not be changed if it is used directly or through the - * PLL as system clock. In this case, you have to select another source - * of the system clock then change the HSE state (ex. disable it). - * @note The HSE is stopped by hardware when entering STOP and STANDBY modes. - * @note This function resets the CSSON bit, so if the Clock security system(CSS) - * was previously enabled you have to enable it again after calling this - * function. - * @param RCC_HSE: specifies the new state of the HSE. - * This parameter can be one of the following values: - * @arg RCC_HSE_OFF: turn OFF the HSE oscillator, HSERDY flag goes low after - * 6 HSE oscillator clock cycles. - * @arg RCC_HSE_ON: turn ON the HSE oscillator - * @arg RCC_HSE_Bypass: HSE oscillator bypassed with external clock - * @retval None - */ -void RCC_HSEConfig(uint8_t RCC_HSE) -{ - /* Check the parameters */ - assert_param(IS_RCC_HSE(RCC_HSE)); - - /* Reset HSEON and HSEBYP bits before configuring the HSE ------------------*/ - *(__IO uint8_t *) CR_BYTE2_ADDRESS = RCC_HSE_OFF; - - /* Set the new HSE configuration -------------------------------------------*/ - *(__IO uint8_t *) CR_BYTE2_ADDRESS = RCC_HSE; - -} - -/** - * @brief Waits for HSE start-up. - * @note This function waits on HSERDY flag to be set and return SUCCESS if - * this flag is set, otherwise returns ERROR if the timeout is reached - * and this flag is not set. The timeout value is defined by the constant - * HSE_STARTUP_TIMEOUT in ft32f0xx.h file. You can tailor it depending - * on the HSE crystal used in your application. - * @note The HSE is stopped by hardware when entering STOP and STANDBY modes. - * @param None - * @retval An ErrorStatus enumeration value: - * - SUCCESS: HSE oscillator is stable and ready to use - * - ERROR: HSE oscillator not yet ready - */ -ErrorStatus RCC_WaitForHSEStartUp(void) -{ - __IO uint32_t StartUpCounter = 0; - ErrorStatus status = ERROR; - FlagStatus HSEStatus = RESET; - - /* Wait till HSE is ready and if timeout is reached exit */ - do - { - HSEStatus = RCC_GetFlagStatus(RCC_FLAG_HSERDY); - StartUpCounter++; - } while((StartUpCounter != HSE_STARTUP_TIMEOUT) && (HSEStatus == RESET)); - - if (RCC_GetFlagStatus(RCC_FLAG_HSERDY) != RESET) - { - status = SUCCESS; - } - else - { - status = ERROR; - } - return (status); -} - -/** - * @brief Adjusts the Internal High Speed oscillator (HSI) calibration value. - * @note The calibration is used to compensate for the variations in voltage - * and temperature that influence the frequency of the internal HSI RC. - * Refer to the Application Note AN4067 for more details on how to - * calibrate the HSI. - * @param HSICalibrationValue: specifies the HSI calibration trimming value. - * This parameter must be a number between 0 and 0x1F. - * @retval None - */ -void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_RCC_HSI_CALIBRATION_VALUE(HSICalibrationValue)); - - tmpreg = RCC->CR; - - /* Clear HSITRIM[4:0] bits */ - tmpreg &= ~RCC_CR_HSITRIM; - - /* Set the HSITRIM[4:0] bits according to HSICalibrationValue value */ - tmpreg |= (uint32_t)HSICalibrationValue << 3; - - /* Store the new value */ - RCC->CR = tmpreg; -} - -/** - * @brief Enables or disables the Internal High Speed oscillator (HSI). - * @note After enabling the HSI, the application software should wait on - * HSIRDY flag to be set indicating that HSI clock is stable and can - * be used to clock the PLL and/or system clock. - * @note HSI can not be stopped if it is used directly or through the PLL - * as system clock. In this case, you have to select another source - * of the system clock then stop the HSI. - * @note The HSI is stopped by hardware when entering STOP and STANDBY modes. - * @param NewState: new state of the HSI. - * This parameter can be: ENABLE or DISABLE. - * @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator - * clock cycles. - * @retval None - */ -void RCC_HSICmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - RCC->CR |= RCC_CR_HSION; - } - else - { - RCC->CR &= ~RCC_CR_HSION; - } -} - -/** - * @brief Adjusts the Internal High Speed oscillator for ADC (HSI14) - * calibration value. - * @note The calibration is used to compensate for the variations in voltage - * and temperature that influence the frequency of the internal HSI RC. - * Refer to the Application Note AN4067 for more details on how to - * calibrate the HSI14. - * @param HSI14CalibrationValue: specifies the HSI14 calibration trimming value. - * This parameter must be a number between 0 and 0x1F. - * @retval None - */ -void RCC_AdjustHSI14CalibrationValue(uint8_t HSI14CalibrationValue) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_RCC_HSI14_CALIBRATION_VALUE(HSI14CalibrationValue)); - - tmpreg = RCC->CR2; - - /* Clear HSI14TRIM[4:0] bits */ - tmpreg &= ~RCC_CR2_HSI14TRIM; - - /* Set the HSITRIM14[4:0] bits according to HSI14CalibrationValue value */ - tmpreg |= (uint32_t)HSI14CalibrationValue << 3; - - /* Store the new value */ - RCC->CR2 = tmpreg; -} - -/** - * @brief Enables or disables the Internal High Speed oscillator for ADC (HSI14). - * @note After enabling the HSI14, the application software should wait on - * HSIRDY flag to be set indicating that HSI clock is stable and can - * be used to clock the ADC. - * @note The HSI14 is stopped by hardware when entering STOP and STANDBY modes. - * @param NewState: new state of the HSI14. - * This parameter can be: ENABLE or DISABLE. - * @note When the HSI14 is stopped, HSI14RDY flag goes low after 6 HSI14 oscillator - * clock cycles. - * @retval None - */ -void RCC_HSI14Cmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - RCC->CR2 |= RCC_CR2_HSI14ON; - } - else - { - RCC->CR2 &= ~RCC_CR2_HSI14ON; - } -} - -/** - * @brief Enables or disables the Internal High Speed oscillator request from ADC. - * @param NewState: new state of the HSI14 ADC request. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_HSI14ADCRequestCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - RCC->CR2 &= ~RCC_CR2_HSI14DIS; - } - else - { - RCC->CR2 |= RCC_CR2_HSI14DIS; - } -} - -/** - * @brief Configures the External Low Speed oscillator (LSE). - * @note As the LSE is in the Backup domain and write access is denied to this - * domain after reset, you have to enable write access using - * PWR_BackupAccessCmd(ENABLE) function before to configure the LSE - * (to be done once after reset). - * @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_Bypass), the application - * software should wait on LSERDY flag to be set indicating that LSE clock - * is stable and can be used to clock the RTC. - * @param RCC_LSE: specifies the new state of the LSE. - * This parameter can be one of the following values: - * @arg RCC_LSE_OFF: turn OFF the LSE oscillator, LSERDY flag goes low after - * 6 LSE oscillator clock cycles. - * @arg RCC_LSE_ON: turn ON the LSE oscillator - * @arg RCC_LSE_Bypass: LSE oscillator bypassed with external clock - * @retval None - */ -void RCC_LSEConfig(uint32_t RCC_LSE) -{ - /* Check the parameters */ - assert_param(IS_RCC_LSE(RCC_LSE)); - - /* Reset LSEON and LSEBYP bits before configuring the LSE ------------------*/ - /* Reset LSEON bit */ - RCC->BDCR &= ~(RCC_BDCR_LSEON); - - /* Reset LSEBYP bit */ - RCC->BDCR &= ~(RCC_BDCR_LSEBYP); - - /* Configure LSE */ - RCC->BDCR |= RCC_LSE; -} - -/** - * @brief Configures the External Low Speed oscillator (LSE) drive capability. - * @param RCC_LSEDrive: specifies the new state of the LSE drive capability. - * This parameter can be one of the following values: - * @arg RCC_LSEDrive_Low: LSE oscillator low drive capability. - * @arg RCC_LSEDrive_MediumLow: LSE oscillator medium low drive capability. - * @arg RCC_LSEDrive_MediumHigh: LSE oscillator medium high drive capability. - * @arg RCC_LSEDrive_High: LSE oscillator high drive capability. - * @retval None - */ -void RCC_LSEDriveConfig(uint32_t RCC_LSEDrive) -{ - /* Check the parameters */ - assert_param(IS_RCC_LSE_DRIVE(RCC_LSEDrive)); - - /* Clear LSEDRV[1:0] bits */ - RCC->BDCR &= ~(RCC_BDCR_LSEDRV); - - /* Set the LSE Drive */ - RCC->BDCR |= RCC_LSEDrive; -} - -/** - * @brief Enables or disables the Internal Low Speed oscillator (LSI). - * @note After enabling the LSI, the application software should wait on - * LSIRDY flag to be set indicating that LSI clock is stable and can - * be used to clock the IWDG and/or the RTC. - * @note LSI can not be disabled if the IWDG is running. - * @param NewState: new state of the LSI. - * This parameter can be: ENABLE or DISABLE. - * @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator - * clock cycles. - * @retval None - */ -void RCC_LSICmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - RCC->CSR |= RCC_CSR_LSION; - } - else - { - RCC->CSR &= ~RCC_CSR_LSION; - } -} - -/** - * @brief Configures the PLL clock source and multiplication factor. - * @note This function must be used only when the PLL is disabled. - * - * @param RCC_PLLSource: specifies the PLL entry clock source. - * This parameter can be one of the following values: - * @arg RCC_PLLSource_HSI_Div2: HSI oscillator clock selected as PLL clock source - * @arg RCC_PLLSource_PREDIV1: PREDIV1 clock selected as PLL clock entry - * @arg RCC_PLLSource_HSI48 HSI48 oscillator clock selected as PLL clock source, - * @arg RCC_PLLSource_HSI: HSI clock selected as PLL clock entry - * @note The minimum input clock frequency for PLL is 2 MHz (when using HSE as - * PLL source). - * - * @param RCC_PLLMul: specifies the PLL multiplication factor, which drive the PLLVCO clock - * This parameter can be RCC_PLLMul_x where x:[2,16] - * - * @retval None - */ -void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t RCC_PLLMul) -{ - /* Check the parameters */ - assert_param(IS_RCC_PLL_SOURCE(RCC_PLLSource)); - assert_param(IS_RCC_PLL_MUL(RCC_PLLMul)); - - /* Clear PLL Source [16] and Multiplier [21:18] bits */ - RCC->CFGR &= ~(RCC_CFGR_PLLMULL | RCC_CFGR_PLLSRC); - - /* Set the PLL Source and Multiplier */ - RCC->CFGR |= (uint32_t)(RCC_PLLSource | RCC_PLLMul); -} - -/** - * @brief Enables or disables the PLL. - * @note After enabling the PLL, the application software should wait on - * PLLRDY flag to be set indicating that PLL clock is stable and can - * be used as system clock source. - * @note The PLL can not be disabled if it is used as system clock source - * @note The PLL is disabled by hardware when entering STOP and STANDBY modes. - * @param NewState: new state of the PLL. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_PLLCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - RCC->CR |= RCC_CR_PLLON; - } - else - { - RCC->CR &= ~RCC_CR_PLLON; - } -} - -/** - * @brief Enables or disables the Internal High Speed oscillator for USB (HSI48). - * @note After enabling the HSI48, the application software should wait on - * HSI48RDY flag to be set indicating that HSI48 clock is stable and can - * be used to clock the USB. - * @note The HSI48 is stopped by hardware when entering STOP and STANDBY modes. - * @param NewState: new state of the HSI48. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_HSI48Cmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - RCC->CR2 |= RCC_CR2_HSI48ON; - } - else - { - RCC->CR2 &= ~RCC_CR2_HSI48ON; - } -} - -/** - * @brief Configures the PREDIV1 division factor. - * @note This function must be used only when the PLL is disabled. - * @param RCC_PREDIV1_Div: specifies the PREDIV1 clock division factor. - * This parameter can be RCC_PREDIV1_Divx where x:[1,16] - * @retval None - */ -void RCC_PREDIV1Config(uint32_t RCC_PREDIV1_Div) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_RCC_PREDIV1(RCC_PREDIV1_Div)); - - tmpreg = RCC->CFGR2; - /* Clear PREDIV1[3:0] bits */ - tmpreg &= ~(RCC_CFGR2_PREDIV1); - /* Set the PREDIV1 division factor */ - tmpreg |= RCC_PREDIV1_Div; - /* Store the new value */ - RCC->CFGR2 = tmpreg; -} - -/** - * @brief Enables or disables the Clock Security System. - * @note If a failure is detected on the HSE oscillator clock, this oscillator - * is automatically disabled and an interrupt is generated to inform the - * software about the failure (Clock Security System Interrupt, CSSI), - * allowing the MCU to perform rescue operations. The CSSI is linked to - * the Cortex-M0 NMI (Non-Maskable Interrupt) exception vector. - * @param NewState: new state of the Clock Security System. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_ClockSecuritySystemCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - RCC->CR |= RCC_CR_CSSON; - } - else - { - RCC->CR &= ~RCC_CR_CSSON; - } -} -/** - * @brief Selects the clock source to output on MCO pin (PA8) and the corresponding - * prescsaler. - * @note PA8 should be configured in alternate function mode. - * @param RCC_MCOSource: specifies the clock source to output. - * This parameter can be one of the following values: - * @arg RCC_MCOSource_NoClock: No clock selected. - * @arg RCC_MCOSource_HSI14: HSI14 oscillator clock selected. - * @arg RCC_MCOSource_LSI: LSI oscillator clock selected. - * @arg RCC_MCOSource_LSE: LSE oscillator clock selected. - * @arg RCC_MCOSource_SYSCLK: System clock selected. - * @arg RCC_MCOSource_HSI: HSI oscillator clock selected. - * @arg RCC_MCOSource_HSE: HSE oscillator clock selected. - * @arg RCC_MCOSource_PLLCLK_Div2: PLL clock divided by 2 selected. - * @arg RCC_MCOSource_PLLCLK: PLL clock selected. - * @arg RCC_MCOSource_HSI48: HSI48 clock selected. - * @param RCC_MCOPrescaler: specifies the prescaler on MCO pin. - * This parameter can be one of the following values: - * @arg RCC_MCOPrescaler_1: MCO clock is divided by 1. - * @arg RCC_MCOPrescaler_2: MCO clock is divided by 2. - * @arg RCC_MCOPrescaler_4: MCO clock is divided by 4. - * @arg RCC_MCOPrescaler_8: MCO clock is divided by 8. - * @arg RCC_MCOPrescaler_16: MCO clock is divided by 16. - * @arg RCC_MCOPrescaler_32: MCO clock is divided by 32. - * @arg RCC_MCOPrescaler_64: MCO clock is divided by 64. - * @arg RCC_MCOPrescaler_128: MCO clock is divided by 128. - * @retval None - */ -void RCC_MCOConfig(uint8_t RCC_MCOSource, uint32_t RCC_MCOPrescaler) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_RCC_MCO_SOURCE(RCC_MCOSource)); - assert_param(IS_RCC_MCO_PRESCALER(RCC_MCOPrescaler)); - - /* Get CFGR value */ - tmpreg = RCC->CFGR; - /* Clear MCOPRE[2:0] bits */ - tmpreg &= ~(RCC_CFGR_MCO_PRE | RCC_CFGR_MCO | RCC_CFGR_PLLNODIV); - /* Set the RCC_MCOSource and RCC_MCOPrescaler */ - tmpreg |= (RCC_MCOPrescaler | ((uint32_t)RCC_MCOSource<<24)); - /* Store the new value */ - RCC->CFGR = tmpreg; -} - -/** - * @} - */ -/** - * @brief Configures the system clock (SYSCLK). - * @note The HSI is used (enabled by hardware) as system clock source after - * startup from Reset, wake-up from STOP and STANDBY mode, or in case - * of failure of the HSE used directly or indirectly as system clock - * (if the Clock Security System CSS is enabled). - * @note A switch from one clock source to another occurs only if the target - * clock source is ready (clock stable after startup delay or PLL locked). - * If a clock source which is not yet ready is selected, the switch will - * occur when the clock source will be ready. - * You can use RCC_GetSYSCLKSource() function to know which clock is - * currently used as system clock source. - * @param RCC_SYSCLKSource: specifies the clock source used as system clock source - * This parameter can be one of the following values: - * @arg RCC_SYSCLKSource_HSI: HSI selected as system clock source - * @arg RCC_SYSCLKSource_HSE: HSE selected as system clock source - * @arg RCC_SYSCLKSource_PLLCLK: PLL selected as system clock source - * @arg RCC_SYSCLKSource_HSI48: HSI48 selected as system clock source - * @retval None - */ -void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_RCC_SYSCLK_SOURCE(RCC_SYSCLKSource)); - - tmpreg = RCC->CFGR; - - /* Clear SW[1:0] bits */ - tmpreg &= ~RCC_CFGR_SW; - - /* Set SW[1:0] bits according to RCC_SYSCLKSource value */ - tmpreg |= RCC_SYSCLKSource; - - /* Store the new value */ - RCC->CFGR = tmpreg; -} - -/** - * @brief Returns the clock source used as system clock. - * @param None - * @retval The clock source used as system clock. The returned value can be one - * of the following values: - * - 0x00: HSI used as system clock - * - 0x04: HSE used as system clock - * - 0x08: PLL used as system clock - * - 0x0C: HSI48 used as system clock - */ -uint8_t RCC_GetSYSCLKSource(void) -{ - return ((uint8_t)(RCC->CFGR & RCC_CFGR_SWS)); -} - -/** - * @brief Configures the AHB clock (HCLK). - * @param RCC_SYSCLK: defines the AHB clock divider. This clock is derived from - * the system clock (SYSCLK). - * This parameter can be one of the following values: - * @arg RCC_SYSCLK_Div1: AHB clock = SYSCLK - * @arg RCC_SYSCLK_Div2: AHB clock = SYSCLK/2 - * @arg RCC_SYSCLK_Div4: AHB clock = SYSCLK/4 - * @arg RCC_SYSCLK_Div8: AHB clock = SYSCLK/8 - * @arg RCC_SYSCLK_Div16: AHB clock = SYSCLK/16 - * @arg RCC_SYSCLK_Div64: AHB clock = SYSCLK/64 - * @arg RCC_SYSCLK_Div128: AHB clock = SYSCLK/128 - * @arg RCC_SYSCLK_Div256: AHB clock = SYSCLK/256 - * @arg RCC_SYSCLK_Div512: AHB clock = SYSCLK/512 - * @retval None - */ -void RCC_HCLKConfig(uint32_t RCC_SYSCLK) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_RCC_HCLK(RCC_SYSCLK)); - - tmpreg = RCC->CFGR; - - /* Clear HPRE[3:0] bits */ - tmpreg &= ~RCC_CFGR_HPRE; - - /* Set HPRE[3:0] bits according to RCC_SYSCLK value */ - tmpreg |= RCC_SYSCLK; - - /* Store the new value */ - RCC->CFGR = tmpreg; -} - -/** - * @brief Configures the APB clock (PCLK). - * @param RCC_HCLK: defines the APB clock divider. This clock is derived from - * the AHB clock (HCLK). - * This parameter can be one of the following values: - * @arg RCC_HCLK_Div1: APB clock = HCLK - * @arg RCC_HCLK_Div2: APB clock = HCLK/2 - * @arg RCC_HCLK_Div4: APB clock = HCLK/4 - * @arg RCC_HCLK_Div8: APB clock = HCLK/8 - * @arg RCC_HCLK_Div16: APB clock = HCLK/16 - * @retval None - */ -void RCC_PCLKConfig(uint32_t RCC_HCLK) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_RCC_PCLK(RCC_HCLK)); - - tmpreg = RCC->CFGR; - - /* Clear PPRE[2:0] bits */ - tmpreg &= ~RCC_CFGR_PPRE; - - /* Set PPRE[2:0] bits according to RCC_HCLK value */ - tmpreg |= RCC_HCLK; - - /* Store the new value */ - RCC->CFGR = tmpreg; -} - -/** - * @brief Configures the ADC clock (ADCCLK). - * @note This function is obsolete. - * For proper ADC clock selection, refer to ADC_ClockModeConfig() in the ADC driver - * @param RCC_ADCCLK: defines the ADC clock source. This clock is derived - * from the HSI14 or APB clock (PCLK). - * This parameter can be one of the following values: - * @arg RCC_ADCCLK_HSI14: ADC clock = HSI14 (14MHz) - * @arg RCC_ADCCLK_PCLK_Div2: ADC clock = PCLK/2 - * @arg RCC_ADCCLK_PCLK_Div4: ADC clock = PCLK/4 - * @retval None - */ -void RCC_ADCCLKConfig(uint32_t RCC_ADCCLK) -{ - /* Check the parameters */ - assert_param(IS_RCC_ADCCLK(RCC_ADCCLK)); - - /* Clear ADCPRE bit */ - RCC->CFGR &= ~RCC_CFGR_ADCPRE; - /* Set ADCPRE bits according to RCC_PCLK value */ - RCC->CFGR |= RCC_ADCCLK & 0xFFFF; - - /* Clear ADCSW bit */ - RCC->CFGR3 &= ~RCC_CFGR3_ADCSW; - /* Set ADCSW bits according to RCC_ADCCLK value */ - RCC->CFGR3 |= RCC_ADCCLK >> 16; -} - -/** - * @brief Configures the CEC clock (CECCLK). - * @param RCC_CECCLK: defines the CEC clock source. This clock is derived - * from the HSI or LSE clock. - * This parameter can be one of the following values: - * @arg RCC_CECCLK_HSI_Div244: CEC clock = HSI/244 (32768Hz) - * @arg RCC_CECCLK_LSE: CEC clock = LSE - * @retval None - */ - - -/** - * @brief Configures the I2C1 clock (I2C1CLK). - * @param RCC_I2CCLK: defines the I2C1 clock source. This clock is derived - * from the HSI or System clock. - * This parameter can be one of the following values: - * @arg RCC_I2C1CLK_HSI: I2C1 clock = HSI - * @arg RCC_I2C1CLK_SYSCLK: I2C1 clock = System Clock - * @retval None - */ -void RCC_I2CCLKConfig(uint32_t RCC_I2CCLK) -{ - /* Check the parameters */ - assert_param(IS_RCC_I2CCLK(RCC_I2CCLK)); - - /* Clear I2CSW bit */ - RCC->CFGR3 &= ~RCC_CFGR3_I2C1SW; - /* Set I2CSW bits according to RCC_I2CCLK value */ - RCC->CFGR3 |= RCC_I2CCLK; -} - -/** - * @brief Configures the USART1 clock (USART1CLK). - * @param RCC_USARTCLK: defines the USART clock source. This clock is derived - * from the HSI or System clock. - * This parameter can be one of the following values: - * @arg RCC_USART1CLK_PCLK: USART1 clock = APB Clock (PCLK) - * @arg RCC_USART1CLK_SYSCLK: USART1 clock = System Clock - * @arg RCC_USART1CLK_LSE: USART1 clock = LSE Clock - * @arg RCC_USART1CLK_HSI: USART1 clock = HSI Clock - * @arg RCC_USART2CLK_PCLK: USART2 clock = APB Clock (PCLK) - * @arg RCC_USART2CLK_SYSCLK: USART2 clock = System Clock - * @arg RCC_USART2CLK_LSE: USART2 clock = LSE Clock - * @arg RCC_USART2CLK_HSI: USART2 clock = HSI Clock - * @arg RCC_USART3CLK_PCLK: USART3 clock = APB Clock (PCLK) - * @arg RCC_USART3CLK_SYSCLK: USART3 clock = System Clock - * @arg RCC_USART3CLK_LSE: USART3 clock = LSE Clock - * @arg RCC_USART3CLK_HSI: USART3 clock = HSI Clock - * @retval None - */ -void RCC_USARTCLKConfig(uint32_t RCC_USARTCLK) -{ - uint32_t tmp = 0; - - /* Check the parameters */ - assert_param(IS_RCC_USARTCLK(RCC_USARTCLK)); - - /* Get USART index */ - tmp = (RCC_USARTCLK >> 28); - - /* Clear USARTSW[1:0] bit */ - if (tmp == (uint32_t)0x00000001) - { - /* Clear USART1SW[1:0] bit */ - RCC->CFGR3 &= ~RCC_CFGR3_USART1SW; - } -// else if (tmp == (uint32_t)0x00000002) -// { -// /* Clear USART2SW[1:0] bit */ -// RCC->CFGR3 &= ~RCC_CFGR3_USART2SW; -// } -// else -// { -// /* Clear USART3SW[1:0] bit */ -// RCC->CFGR3 &= ~RCC_CFGR3_USART3SW; -// } - - /* Set USARTxSW bits according to RCC_USARTCLK value */ - RCC->CFGR3 |= RCC_USARTCLK; -} - -/** - * @brief Configures the USB clock (USBCLK). - * @param RCC_USBCLK: defines the USB clock source. This clock is derived - * from the HSI48 or system clock. - * This parameter can be one of the following values: - * @arg RCC_USBCLK_HSI48: USB clock = HSI48 - * @arg RCC_USBCLK_PLLCLK: USB clock = PLL clock - * @retval None - */ -void RCC_USBCLKConfig(uint32_t RCC_USBCLK) -{ - /* Check the parameters */ - assert_param(IS_RCC_USBCLK(RCC_USBCLK)); - - /* Clear USBSW bit */ - RCC->CFGR3 &= ~RCC_CFGR3_USBSW; - /* Set USBSW bits according to RCC_USBCLK value */ - RCC->CFGR3 |= RCC_USBCLK; -} - -/** - * @brief Returns the frequencies of the System, AHB and APB busses clocks. - * @note The frequency returned by this function is not the real frequency - * in the chip. It is calculated based on the predefined constant and - * the source selected by RCC_SYSCLKConfig(): - * - * @note If SYSCLK source is HSI, function returns constant HSI_VALUE(*) - * - * @note If SYSCLK source is HSE, function returns constant HSE_VALUE(**) - * - * @note If SYSCLK source is PLL, function returns constant HSE_VALUE(**) - * or HSI_VALUE(*) multiplied by the PLL factors. - * - * @note If SYSCLK source is HSI48, function returns constant HSI48_VALUE(***) - * - * @note (*) HSI_VALUE is a constant defined in ft32f0xx.h file (default value - * 8 MHz) but the real value may vary depending on the variations - * in voltage and temperature, refer to RCC_AdjustHSICalibrationValue(). - * - * @note (**) HSE_VALUE is a constant defined in ft32f0xx.h file (default value - * 8 MHz), user has to ensure that HSE_VALUE is same as the real - * frequency of the crystal used. Otherwise, this function may - * return wrong result. - * - * @note (***) HSI48_VALUE is a constant defined in ft32f0xx.h file (default value - * 48 MHz) but the real value may vary depending on the variations - * in voltage and temperature. - * - * @note The result of this function could be not correct when using fractional - * value for HSE crystal. - * - * @param RCC_Clocks: pointer to a RCC_ClocksTypeDef structure which will hold - * the clocks frequencies. - * - * @note This function can be used by the user application to compute the - * baudrate for the communication peripherals or configure other parameters. - * @note Each time SYSCLK, HCLK and/or PCLK clock changes, this function - * must be called to update the structure's field. Otherwise, any - * configuration based on this function will be incorrect. - * - * @retval None - */ -void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks) -{ - uint32_t tmp = 0, pllmull = 0, pllsource = 0, prediv1factor = 0, presc = 0, pllclk = 0; - - /* Get SYSCLK source -------------------------------------------------------*/ - tmp = RCC->CFGR & RCC_CFGR_SWS; - - switch (tmp) - { - case 0x00: /* HSI used as system clock */ - RCC_Clocks->SYSCLK_Frequency = HSI_VALUE; - break; - case 0x04: /* HSE used as system clock */ - RCC_Clocks->SYSCLK_Frequency = HSE_VALUE; - break; - case 0x08: /* PLL used as system clock */ - /* Get PLL clock source and multiplication factor ----------------------*/ - pllmull = RCC->CFGR & RCC_CFGR_PLLMULL; - pllsource = RCC->CFGR & RCC_CFGR_PLLSRC; - pllmull = ( pllmull >> 18) + 2; - - if (pllsource == 0x00) - { - /* HSI oscillator clock divided by 2 selected as PLL clock entry */ - pllclk = (HSI_VALUE >> 1) * pllmull; - } - else - { - prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1; - /* HSE oscillator clock selected as PREDIV1 clock entry */ - pllclk = (HSE_VALUE / prediv1factor) * pllmull; - } - RCC_Clocks->SYSCLK_Frequency = pllclk; - break; - case 0x0C: /* HSI48 used as system clock */ - RCC_Clocks->SYSCLK_Frequency = HSI48_VALUE; - break; - default: /* HSI used as system clock */ - RCC_Clocks->SYSCLK_Frequency = HSI_VALUE; - break; - } - /* Compute HCLK, PCLK clocks frequencies -----------------------------------*/ - /* Get HCLK prescaler */ - tmp = RCC->CFGR & RCC_CFGR_HPRE; - tmp = tmp >> 4; - presc = APBAHBPrescTable[tmp]; - /* HCLK clock frequency */ - RCC_Clocks->HCLK_Frequency = RCC_Clocks->SYSCLK_Frequency >> presc; - - /* Get PCLK prescaler */ - tmp = RCC->CFGR & RCC_CFGR_PPRE; - tmp = tmp >> 8; - presc = APBAHBPrescTable[tmp]; - /* PCLK clock frequency */ - RCC_Clocks->PCLK_Frequency = RCC_Clocks->HCLK_Frequency >> presc; - - /* ADCCLK clock frequency */ - if((RCC->CFGR3 & RCC_CFGR3_ADCSW) != RCC_CFGR3_ADCSW) - { - /* ADC Clock is HSI14 Osc. */ - RCC_Clocks->ADCCLK_Frequency = HSI14_VALUE; - } - else - { - if((RCC->CFGR & RCC_CFGR_ADCPRE) != RCC_CFGR_ADCPRE) - { - /* ADC Clock is derived from PCLK/2 */ - RCC_Clocks->ADCCLK_Frequency = RCC_Clocks->PCLK_Frequency >> 1; - } - else - { - /* ADC Clock is derived from PCLK/4 */ - RCC_Clocks->ADCCLK_Frequency = RCC_Clocks->PCLK_Frequency >> 2; - } - - } - - /* CECCLK clock frequency */ - - - /* I2C1CLK clock frequency */ - if((RCC->CFGR3 & RCC_CFGR3_I2C1SW) != RCC_CFGR3_I2C1SW) - { - /* I2C1 Clock is HSI Osc. */ - RCC_Clocks->I2C1CLK_Frequency = HSI_VALUE; - } - else - { - /* I2C1 Clock is System Clock */ - RCC_Clocks->I2C1CLK_Frequency = RCC_Clocks->SYSCLK_Frequency; - } - - /* USART1CLK clock frequency */ - if((RCC->CFGR3 & RCC_CFGR3_USART1SW) == 0x0) - { - /* USART1 Clock is PCLK */ - RCC_Clocks->USART1CLK_Frequency = RCC_Clocks->PCLK_Frequency; - } - else if((RCC->CFGR3 & RCC_CFGR3_USART1SW) == RCC_CFGR3_USART1SW_0) - { - /* USART1 Clock is System Clock */ - RCC_Clocks->USART1CLK_Frequency = RCC_Clocks->SYSCLK_Frequency; - } - else if((RCC->CFGR3 & RCC_CFGR3_USART1SW) == RCC_CFGR3_USART1SW_1) - { - /* USART1 Clock is LSE Osc. */ - RCC_Clocks->USART1CLK_Frequency = LSE_VALUE; - } - else if((RCC->CFGR3 & RCC_CFGR3_USART1SW) == RCC_CFGR3_USART1SW) - { - /* USART1 Clock is HSI Osc. */ - RCC_Clocks->USART1CLK_Frequency = HSI_VALUE; - } - - /* USART2CLK clock frequency */ - RCC_Clocks->USART2CLK_Frequency=RCC_Clocks->PCLK_Frequency; - /* USART2CLK clock frequency */ -// if((RCC->CFGR3 & RCC_CFGR3_USART2SW) == 0x0) -// { -// /* USART Clock is PCLK */ -// RCC_Clocks->USART2CLK_Frequency = RCC_Clocks->PCLK_Frequency; -// } -// else if((RCC->CFGR3 & RCC_CFGR3_USART2SW) == RCC_CFGR3_USART2SW_0) -// { -// /* USART Clock is System Clock */ -// RCC_Clocks->USART2CLK_Frequency = RCC_Clocks->SYSCLK_Frequency; -// } -// else if((RCC->CFGR3 & RCC_CFGR3_USART2SW) == RCC_CFGR3_USART2SW_1) -// { -// /* USART Clock is LSE Osc. */ -// RCC_Clocks->USART2CLK_Frequency = LSE_VALUE; -// } -// else if((RCC->CFGR3 & RCC_CFGR3_USART2SW) == RCC_CFGR3_USART2SW) -// { -// /* USART Clock is HSI Osc. */ -// RCC_Clocks->USART2CLK_Frequency = HSI_VALUE; -// } - - - /* USART3CLK clock frequency */ - - /* USBCLK clock frequency */ - if((RCC->CFGR3 & RCC_CFGR3_USBSW) != RCC_CFGR3_USBSW) - { - /* USB Clock is HSI48 */ - RCC_Clocks->USBCLK_Frequency = HSI48_VALUE; - } - else - { - /* USB Clock is PLL clock */ - RCC_Clocks->USBCLK_Frequency = pllclk; - } -} - -/** - * @} - */ - -/** - * @brief Configures the RTC clock (RTCCLK). - * @note As the RTC clock configuration bits are in the Backup domain and write - * access is denied to this domain after reset, you have to enable write - * access using PWR_BackupAccessCmd(ENABLE) function before to configure - * the RTC clock source (to be done once after reset). - * @note Once the RTC clock is configured it can't be changed unless the RTC - * is reset using RCC_BackupResetCmd function, or by a Power On Reset (POR) - * - * @param RCC_RTCCLKSource: specifies the RTC clock source. - * This parameter can be one of the following values: - * @arg RCC_RTCCLKSource_LSE: LSE selected as RTC clock - * @arg RCC_RTCCLKSource_LSI: LSI selected as RTC clock - * @arg RCC_RTCCLKSource_HSE_Div32: HSE divided by 32 selected as RTC clock - * - * @note If the LSE or LSI is used as RTC clock source, the RTC continues to - * work in STOP and STANDBY modes, and can be used as wakeup source. - * However, when the HSE clock is used as RTC clock source, the RTC - * cannot be used in STOP and STANDBY modes. - * - * @note The maximum input clock frequency for RTC is 2MHz (when using HSE as - * RTC clock source). - * - * @retval None - */ -void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource) -{ - /* Check the parameters */ - assert_param(IS_RCC_RTCCLK_SOURCE(RCC_RTCCLKSource)); - - /* Select the RTC clock source */ - RCC->BDCR |= RCC_RTCCLKSource; -} - -/** - * @brief Enables or disables the RTC clock. - * @note This function must be used only after the RTC clock source was selected - * using the RCC_RTCCLKConfig function. - * @param NewState: new state of the RTC clock. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_RTCCLKCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - RCC->BDCR |= RCC_BDCR_RTCEN; - } - else - { - RCC->BDCR &= ~RCC_BDCR_RTCEN; - } -} - -/** - * @brief Forces or releases the Backup domain reset. - * @note This function resets the RTC peripheral (including the backup registers) - * and the RTC clock source selection in RCC_BDCR register. - * @param NewState: new state of the Backup domain reset. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_BackupResetCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - RCC->BDCR |= RCC_BDCR_BDRST; - } - else - { - RCC->BDCR &= ~RCC_BDCR_BDRST; - } -} - -/** - * @brief Enables or disables the AHB peripheral clock. - * @note After reset, the peripheral clock (used for registers read/write access) - * is disabled and the application software has to enable this clock before - * using it. - * @param RCC_AHBPeriph: specifies the AHB peripheral to gates its clock. - * This parameter can be any combination of the following values: - * @arg RCC_AHBPeriph_GPIOA: GPIOA clock - * @arg RCC_AHBPeriph_GPIOB: GPIOB clock - * @arg RCC_AHBPeriph_GPIOC: GPIOC clock - * @arg RCC_AHBPeriph_GPIOD: GPIOD clock - * @arg RCC_AHBPeriph_GPIOE: GPIOE clock - * @arg RCC_AHBPeriph_GPIOF: GPIOF clock - * @arg RCC_AHBPeriph_TS: TS clock - * @arg RCC_AHBPeriph_CRC: CRC clock - * @arg RCC_AHBPeriph_FLITF: (has effect only when the Flash memory is in power down mode) - * @arg RCC_AHBPeriph_SRAM: SRAM clock - * @arg RCC_AHBPeriph_DMA1: DMA1 clock - * @arg RCC_AHBPeriph_DMA2: DMA2 clock - * @param NewState: new state of the specified peripheral clock. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_RCC_AHB_PERIPH(RCC_AHBPeriph)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - RCC->AHBENR |= RCC_AHBPeriph; - } - else - { - RCC->AHBENR &= ~RCC_AHBPeriph; - } -} - -/** - * @brief Enables or disables the High Speed APB (APB2) peripheral clock. - * @note After reset, the peripheral clock (used for registers read/write access) - * is disabled and the application software has to enable this clock before - * using it. - * @param RCC_APB2Periph: specifies the APB2 peripheral to gates its clock. - * This parameter can be any combination of the following values: - * @arg RCC_APB2Periph_SYSCFG: SYSCFG clock - * @arg RCC_APB2Periph_USART6: USART6 clock - * @arg RCC_APB2Periph_USART7: USART7 clock - * @arg RCC_APB2Periph_USART8: USART8 clock - * @arg RCC_APB2Periph_ADC1: ADC1 clock - * @arg RCC_APB2Periph_TIM1: TIM1 clock - * @arg RCC_APB2Periph_SPI1: SPI1 clock - * @arg RCC_APB2Periph_USART1: USART1 clock - * @arg RCC_APB2Periph_TIM15: TIM15 clock - * @arg RCC_APB2Periph_TIM16: TIM16 clock - * @arg RCC_APB2Periph_TIM17: TIM17 clock - * @arg RCC_APB2Periph_DBGMCU: DBGMCU clock - * @param NewState: new state of the specified peripheral clock. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - RCC->APB2ENR |= RCC_APB2Periph; - } - else - { - RCC->APB2ENR &= ~RCC_APB2Periph; - } -} - -/** - * @brief Enables or disables the Low Speed APB (APB1) peripheral clock. - * @note After reset, the peripheral clock (used for registers read/write access) - * is disabled and the application software has to enable this clock before - * using it. - * @param RCC_APB1Periph: specifies the APB1 peripheral to gates its clock. - * This parameter can be any combination of the following values: - * @arg RCC_APB1Periph_TIM2: TIM2 clock - * @arg RCC_APB1Periph_TIM3: TIM3 clock - * @arg RCC_APB1Periph_TIM6: TIM6 clock - * @arg RCC_APB1Periph_TIM7: TIM7 clock - * @arg RCC_APB1Periph_TIM14: TIM14 clock - * @arg RCC_APB1Periph_WWDG: WWDG clock - * @arg RCC_APB1Periph_SPI2: SPI2 clock - * @arg RCC_APB1Periph_USART2: USART2 clock - * @arg RCC_APB1Periph_USART3: USART3 clock - * @arg RCC_APB1Periph_USART4: USART4 clock - * @arg RCC_APB1Periph_USART5: USART5 clock - * @arg RCC_APB1Periph_I2C1: I2C1 clock - * @arg RCC_APB1Periph_I2C2: I2C2 clock - * @arg RCC_APB1Periph_USB: USB clock - * @arg RCC_APB1Periph_CAN: CAN clock - * @arg RCC_APB1Periph_CRS: CRS clock - * @arg RCC_APB1Periph_PWR: PWR clock - * @arg RCC_APB1Periph_DAC: DAC clock - * @arg RCC_APB1Periph_CEC: CEC clock - * @param NewState: new state of the specified peripheral clock. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - RCC->APB1ENR |= RCC_APB1Periph; - } - else - { - RCC->APB1ENR &= ~RCC_APB1Periph; - } -} - -/** - * @brief Forces or releases AHB peripheral reset. - * @param RCC_AHBPeriph: specifies the AHB peripheral to reset. - * This parameter can be any combination of the following values: - * @arg RCC_AHBPeriph_GPIOA: GPIOA clock - * @arg RCC_AHBPeriph_GPIOB: GPIOB clock - * @arg RCC_AHBPeriph_GPIOC: GPIOC clock - * @arg RCC_AHBPeriph_GPIOD: GPIOD clock - * @arg RCC_AHBPeriph_GPIOE: GPIOE clock - * @arg RCC_AHBPeriph_GPIOF: GPIOF clock - * @arg RCC_AHBPeriph_TS: TS clock - * @param NewState: new state of the specified peripheral reset. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_AHBPeriphResetCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_RCC_AHB_RST_PERIPH(RCC_AHBPeriph)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - RCC->AHBRSTR |= RCC_AHBPeriph; - } - else - { - RCC->AHBRSTR &= ~RCC_AHBPeriph; - } -} - -/** - * @brief Forces or releases High Speed APB (APB2) peripheral reset. - * @param RCC_APB2Periph: specifies the APB2 peripheral to reset. - * This parameter can be any combination of the following values: - * @arg RCC_APB2Periph_SYSCFG: SYSCFG clock - * @arg RCC_APB2Periph_USART6: USART6 clock - * @arg RCC_APB2Periph_USART7: USART7 clock - * @arg RCC_APB2Periph_USART8: USART8 clock - * @arg RCC_APB2Periph_ADC1: ADC1 clock - * @arg RCC_APB2Periph_TIM1: TIM1 clock - * @arg RCC_APB2Periph_SPI1: SPI1 clock - * @arg RCC_APB2Periph_USART1: USART1 clock - * @arg RCC_APB2Periph_TIM15: TIM15 clock - * @arg RCC_APB2Periph_TIM16: TIM16 clock - * @arg RCC_APB2Periph_TIM17: TIM17 clock - * @arg RCC_APB2Periph_DBGMCU: DBGMCU clock - * @param NewState: new state of the specified peripheral reset. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - RCC->APB2RSTR |= RCC_APB2Periph; - } - else - { - RCC->APB2RSTR &= ~RCC_APB2Periph; - } -} - -/** - * @brief Forces or releases Low Speed APB (APB1) peripheral reset. - * @param RCC_APB1Periph: specifies the APB1 peripheral to reset. - * This parameter can be any combination of the following values: - * @arg RCC_APB1Periph_TIM2: TIM2 clock - * @arg RCC_APB1Periph_TIM3: TIM3 clock - * @arg RCC_APB1Periph_TIM6: TIM6 clock - * @arg RCC_APB1Periph_TIM7: TIM7 clock - * @arg RCC_APB1Periph_TIM14: TIM14 clock - * @arg RCC_APB1Periph_WWDG: WWDG clock - * @arg RCC_APB1Periph_SPI2: SPI2 clock - * @arg RCC_APB1Periph_USART2: USART2 clock - * @arg RCC_APB1Periph_USART3: USART3 clock - * @arg RCC_APB1Periph_USART4: USART4 clock - * @arg RCC_APB1Periph_USART5: USART5 clock - * @arg RCC_APB1Periph_I2C1: I2C1 clock - * @arg RCC_APB1Periph_I2C2: I2C2 clock - * @arg RCC_APB1Periph_USB: USB clock - * @arg RCC_APB1Periph_CAN: CAN clock - * @arg RCC_APB1Periph_CRS: CRS clock - * @arg RCC_APB1Periph_PWR: PWR clock - * @arg RCC_APB1Periph_DAC: DAC clock - * @arg RCC_APB1Periph_CEC: CEC clock - * @param NewState: new state of the specified peripheral clock. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - RCC->APB1RSTR |= RCC_APB1Periph; - } - else - { - RCC->APB1RSTR &= ~RCC_APB1Periph; - } -} - -/** - * @} - */ -/** - * @brief Enables or disables the specified RCC interrupts. - * @note The CSS interrupt doesn't have an enable bit; once the CSS is enabled - * and if the HSE clock fails, the CSS interrupt occurs and an NMI is - * automatically generated. The NMI will be executed indefinitely, and - * since NMI has higher priority than any other IRQ (and main program) - * the application will be stacked in the NMI ISR unless the CSS interrupt - * pending bit is cleared. - * @param RCC_IT: specifies the RCC interrupt sources to be enabled or disabled. - * This parameter can be any combination of the following values: - * @arg RCC_IT_LSIRDY: LSI ready interrupt - * @arg RCC_IT_LSERDY: LSE ready interrupt - * @arg RCC_IT_HSIRDY: HSI ready interrupt - * @arg RCC_IT_HSERDY: HSE ready interrupt - * @arg RCC_IT_PLLRDY: PLL ready interrupt - * @arg RCC_IT_HSI14RDY: HSI14 ready interrupt - * @arg RCC_IT_HSI48RDY: HSI48 ready interrupt - * @param NewState: new state of the specified RCC interrupts. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_RCC_IT(RCC_IT)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Perform Byte access to RCC_CIR[13:8] bits to enable the selected interrupts */ - *(__IO uint8_t *) CIR_BYTE1_ADDRESS |= RCC_IT; - } - else - { - /* Perform Byte access to RCC_CIR[13:8] bits to disable the selected interrupts */ - *(__IO uint8_t *) CIR_BYTE1_ADDRESS &= (uint8_t)~RCC_IT; - } -} - -/** - * @brief Checks whether the specified RCC flag is set or not. - * @param RCC_FLAG: specifies the flag to check. - * This parameter can be one of the following values: - * @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready - * @arg RCC_FLAG_HSERDY: HSE oscillator clock ready - * @arg RCC_FLAG_PLLRDY: PLL clock ready - * @arg RCC_FLAG_LSERDY: LSE oscillator clock ready - * @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready - * @arg RCC_FLAG_OBLRST: Option Byte Loader (OBL) reset - * @arg RCC_FLAG_PINRST: Pin reset - * @arg RCC_FLAG_V18PWRRSTF: V1.8 power domain reset - * @arg RCC_FLAG_PORRST: POR/PDR reset - * @arg RCC_FLAG_SFTRST: Software reset - * @arg RCC_FLAG_IWDGRST: Independent Watchdog reset - * @arg RCC_FLAG_WWDGRST: Window Watchdog reset - * @arg RCC_FLAG_LPWRRST: Low Power reset - * @arg RCC_FLAG_HSI14RDY: HSI14 oscillator clock ready - * @arg RCC_FLAG_HSI48RDY: HSI48 oscillator clock ready - * @retval The new state of RCC_FLAG (SET or RESET). - */ -FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG) -{ - uint32_t tmp = 0; - uint32_t statusreg = 0; - FlagStatus bitstatus = RESET; - - /* Check the parameters */ - assert_param(IS_RCC_FLAG(RCC_FLAG)); - - /* Get the RCC register index */ - tmp = RCC_FLAG >> 5; - - if (tmp == 0) /* The flag to check is in CR register */ - { - statusreg = RCC->CR; - } - else if (tmp == 1) /* The flag to check is in BDCR register */ - { - statusreg = RCC->BDCR; - } - else if (tmp == 2) /* The flag to check is in CSR register */ - { - statusreg = RCC->CSR; - } - else /* The flag to check is in CR2 register */ - { - statusreg = RCC->CR2; - } - - /* Get the flag position */ - tmp = RCC_FLAG & FLAG_MASK; - - if ((statusreg & ((uint32_t)1 << tmp)) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - /* Return the flag status */ - return bitstatus; -} - -/** - * @brief Clears the RCC reset flags. - * The reset flags are: RCC_FLAG_OBLRST, RCC_FLAG_PINRST, RCC_FLAG_V18PWRRSTF, - * RCC_FLAG_PORRST, RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, - * RCC_FLAG_LPWRRST. - * @param None - * @retval None - */ -void RCC_ClearFlag(void) -{ - /* Set RMVF bit to clear the reset flags */ - RCC->CSR |= RCC_CSR_RMVF; -} - -/** - * @brief Checks whether the specified RCC interrupt has occurred or not. - * @param RCC_IT: specifies the RCC interrupt source to check. - * This parameter can be one of the following values: - * @arg RCC_IT_LSIRDY: LSI ready interrupt - * @arg RCC_IT_LSERDY: LSE ready interrupt - * @arg RCC_IT_HSIRDY: HSI ready interrupt - * @arg RCC_IT_HSERDY: HSE ready interrupt - * @arg RCC_IT_PLLRDY: PLL ready interrupt - * @arg RCC_IT_HSI14RDY: HSI14 ready interrupt - * @arg RCC_IT_HSI48RDY: HSI48 ready interrupt - * @arg RCC_IT_CSS: Clock Security System interrupt - * @retval The new state of RCC_IT (SET or RESET). - */ -ITStatus RCC_GetITStatus(uint8_t RCC_IT) -{ - ITStatus bitstatus = RESET; - - /* Check the parameters */ - assert_param(IS_RCC_GET_IT(RCC_IT)); - - /* Check the status of the specified RCC interrupt */ - if ((RCC->CIR & RCC_IT) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - /* Return the RCC_IT status */ - return bitstatus; -} - -/** - * @brief Clears the RCC's interrupt pending bits. - * @param RCC_IT: specifies the interrupt pending bit to clear. - * This parameter can be any combination of the following values: - * @arg RCC_IT_LSIRDY: LSI ready interrupt - * @arg RCC_IT_LSERDY: LSE ready interrupt - * @arg RCC_IT_HSIRDY: HSI ready interrupt - * @arg RCC_IT_HSERDY: HSE ready interrupt - * @arg RCC_IT_PLLRDY: PLL ready interrupt - * @arg RCC_IT_HSI48RDY: HSI48 ready interrupt - * @arg RCC_IT_HSI14RDY: HSI14 ready interrupt - * @arg RCC_IT_CSS: Clock Security System interrupt - * @retval None - */ -void RCC_ClearITPendingBit(uint8_t RCC_IT) -{ - /* Check the parameters */ - assert_param(IS_RCC_CLEAR_IT(RCC_IT)); - - /* Perform Byte access to RCC_CIR[23:16] bits to clear the selected interrupt - pending bits */ - *(__IO uint8_t *) CIR_BYTE2_ADDRESS = RCC_IT; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT FMD *****END OF FILE****/ diff --git a/bsp/ft32/libraries/FT32F0xx/FT32F0xx_Driver/Src/ft32f0xx_rtc.c b/bsp/ft32/libraries/FT32F0xx/FT32F0xx_Driver/Src/ft32f0xx_rtc.c deleted file mode 100644 index 1708575e6cd..00000000000 --- a/bsp/ft32/libraries/FT32F0xx/FT32F0xx_Driver/Src/ft32f0xx_rtc.c +++ /dev/null @@ -1,1902 +0,0 @@ -/** - ****************************************************************************** - * @file ft32f0xx_rtc.c - * @author FMD AE - * @brief This file provides firmware functions to manage the following - * functionalities of the Real-Time Clock (RTC) peripheral: - * + Initialization - * + Calendar (Time and Date) configuration - * + Alarms (Alarm A) configuration - * + Daylight Saving configuration - * + Output pin Configuration - * + Digital Calibration configuration - * + TimeStamp configuration - * + Tampers configuration - * + Backup Data Registers configuration - * + Output Type Config configuration - * + Shift control synchronisation - * + Interrupts and flags management - * @version V1.0.0 - * @data 2021-07-01 - ****************************************************************************** - */ - - -/* Includes ------------------------------------------------------------------*/ -#include "ft32f0xx_rtc.h" - - -/* Masks Definition */ -#define RTC_TR_RESERVED_MASK ((uint32_t)0x007F7F7F) -#define RTC_DR_RESERVED_MASK ((uint32_t)0x00FFFF3F) -#define RTC_INIT_MASK ((uint32_t)0xFFFFFFFF) -#define RTC_RSF_MASK ((uint32_t)0xFFFFFF5F) -#define RTC_FLAGS_MASK ((uint32_t)(RTC_FLAG_TSOVF | RTC_FLAG_TSF | RTC_FLAG_ALRAF | \ - RTC_FLAG_RSF | RTC_FLAG_INITS |RTC_FLAG_INITF | \ - RTC_FLAG_TAMP1F | RTC_FLAG_TAMP2F | RTC_FLAG_RECALPF | \ - RTC_FLAG_SHPF)) - -#define INITMODE_TIMEOUT ((uint32_t) 0x00004000) -#define SYNCHRO_TIMEOUT ((uint32_t) 0x00008000) -#define RECALPF_TIMEOUT ((uint32_t) 0x00001000) -#define SHPF_TIMEOUT ((uint32_t) 0x00001000) - - -static uint8_t RTC_ByteToBcd2(uint8_t Value); -static uint8_t RTC_Bcd2ToByte(uint8_t Value); - -/** - * @brief Deinitializes the RTC registers to their default reset values. - * @note This function doesn't reset the RTC Clock source and RTC Backup Data - * registers. - * @param None - * @retval An ErrorStatus enumeration value: - * - SUCCESS: RTC registers are deinitialized - * - ERROR: RTC registers are not deinitialized - */ -ErrorStatus RTC_DeInit(void) -{ - ErrorStatus status = ERROR; - - /* Disable the write protection for RTC registers */ - RTC->WPR = 0xCA; - RTC->WPR = 0x53; - - /* Set Initialization mode */ - if (RTC_EnterInitMode() == ERROR) - { - status = ERROR; - } - else - { - /* Reset TR, DR and CR registers */ - RTC->TR = (uint32_t)0x00000000; - RTC->DR = (uint32_t)0x00002101; - RTC->CR &= (uint32_t)0x00000000; - RTC->PRER = (uint32_t)0x007F00FF; - RTC->ALRMAR = (uint32_t)0x00000000; - RTC->SHIFTR = (uint32_t)0x00000000; - RTC->CALR = (uint32_t)0x00000000; - RTC->ALRMASSR = (uint32_t)0x00000000; - - /* Reset ISR register and exit initialization mode */ - RTC->ISR = (uint32_t)0x00000000; - - /* Reset Tamper and alternate functions configuration register */ - RTC->TAFCR = 0x00000000; - - /* Wait till the RTC RSF flag is set */ - if (RTC_WaitForSynchro() == ERROR) - { - status = ERROR; - } - else - { - status = SUCCESS; - } - - } - - /* Enable the write protection for RTC registers */ - RTC->WPR = 0xFF; - - return status; -} - -/** - * @brief Initializes the RTC registers according to the specified parameters - * in RTC_InitStruct. - * @param RTC_InitStruct: pointer to a RTC_InitTypeDef structure that contains - * the configuration information for the RTC peripheral. - * @note The RTC Prescaler register is write protected and can be written in - * initialization mode only. - * @retval An ErrorStatus enumeration value: - * - SUCCESS: RTC registers are initialized - * - ERROR: RTC registers are not initialized - */ -ErrorStatus RTC_Init(RTC_InitTypeDef* RTC_InitStruct) -{ - ErrorStatus status = ERROR; - - /* Check the parameters */ - assert_param(IS_RTC_HOUR_FORMAT(RTC_InitStruct->RTC_HourFormat)); - assert_param(IS_RTC_ASYNCH_PREDIV(RTC_InitStruct->RTC_AsynchPrediv)); - assert_param(IS_RTC_SYNCH_PREDIV(RTC_InitStruct->RTC_SynchPrediv)); - - /* Disable the write protection for RTC registers */ - RTC->WPR = 0xCA; - RTC->WPR = 0x53; - - /* Set Initialization mode */ - if (RTC_EnterInitMode() == ERROR) - { - status = ERROR; - } - else - { - /* Clear RTC CR FMT Bit */ - RTC->CR &= ((uint32_t)~(RTC_CR_FMT)); - /* Set RTC_CR register */ - RTC->CR |= ((uint32_t)(RTC_InitStruct->RTC_HourFormat)); - - /* Configure the RTC PRER */ - RTC->PRER = (uint32_t)(RTC_InitStruct->RTC_SynchPrediv); - RTC->PRER |= (uint32_t)(RTC_InitStruct->RTC_AsynchPrediv << 16); - - /* Exit Initialization mode */ - RTC_ExitInitMode(); - - status = SUCCESS; - } - /* Enable the write protection for RTC registers */ - RTC->WPR = 0xFF; - - return status; -} - -/** - * @brief Fills each RTC_InitStruct member with its default value. - * @param RTC_InitStruct: pointer to a RTC_InitTypeDef structure which will be - * initialized. - * @retval None - */ -void RTC_StructInit(RTC_InitTypeDef* RTC_InitStruct) -{ - /* Initialize the RTC_HourFormat member */ - RTC_InitStruct->RTC_HourFormat = RTC_HourFormat_24; - - /* Initialize the RTC_AsynchPrediv member */ - RTC_InitStruct->RTC_AsynchPrediv = (uint32_t)0x7F; - - /* Initialize the RTC_SynchPrediv member */ - RTC_InitStruct->RTC_SynchPrediv = (uint32_t)0xFF; -} - -/** - * @brief Enables or disables the RTC registers write protection. - * @note All the RTC registers are write protected except for RTC_ISR[13:8], - * RTC_TAFCR and RTC_BKPxR. - * @note Writing a wrong key reactivates the write protection. - * @note The protection mechanism is not affected by system reset. - * @param NewState: new state of the write protection. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RTC_WriteProtectionCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the write protection for RTC registers */ - RTC->WPR = 0xFF; - } - else - { - /* Disable the write protection for RTC registers */ - RTC->WPR = 0xCA; - RTC->WPR = 0x53; - } -} - -/** - * @brief Enters the RTC Initialization mode. - * @note The RTC Initialization mode is write protected, use the - * RTC_WriteProtectionCmd(DISABLE) before calling this function. - * @param None - * @retval An ErrorStatus enumeration value: - * - SUCCESS: RTC is in Init mode - * - ERROR: RTC is not in Init mode - */ -ErrorStatus RTC_EnterInitMode(void) -{ - __IO uint32_t initcounter = 0x00; - ErrorStatus status = ERROR; - uint32_t initstatus = 0x00; - - /* Check if the Initialization mode is set */ - if ((RTC->ISR & RTC_ISR_INITF) == (uint32_t)RESET) - { - /* Set the Initialization mode */ - RTC->ISR = (uint32_t)RTC_INIT_MASK; - - /* Wait till RTC is in INIT state and if Time out is reached exit */ - do - { - initstatus = RTC->ISR & RTC_ISR_INITF; - initcounter++; - } while((initcounter != INITMODE_TIMEOUT) && (initstatus == 0x00)); - - if ((RTC->ISR & RTC_ISR_INITF) != RESET) - { - status = SUCCESS; - } - else - { - status = ERROR; - } - } - else - { - status = SUCCESS; - } - - return (status); -} - -/** - * @brief Exits the RTC Initialization mode. - * @note When the initialization sequence is complete, the calendar restarts - * counting after 4 RTCCLK cycles. - * @note The RTC Initialization mode is write protected, use the - * RTC_WriteProtectionCmd(DISABLE) before calling this function. - * @param None - * @retval None - */ -void RTC_ExitInitMode(void) -{ - /* Exit Initialization mode */ - RTC->ISR &= (uint32_t)~RTC_ISR_INIT; - - /*when BypassShadow is enable,this bit should wait to clear zero.edit:2020.5.23*/ - while((RTC->ISR & RTC_ISR_INITF) != RESET) - { - ; - } -} - -/** - * @brief Waits until the RTC Time and Date registers (RTC_TR and RTC_DR) are - * synchronized with RTC APB clock. - * @note The RTC Resynchronization mode is write protected, use the - * RTC_WriteProtectionCmd(DISABLE) before calling this function. - * @note To read the calendar through the shadow registers after Calendar - * initialization, calendar update or after wakeup from low power modes - * the software must first clear the RSF flag. - * The software must then wait until it is set again before reading - * the calendar, which means that the calendar registers have been - * correctly copied into the RTC_TR and RTC_DR shadow registers. - * @param None - * @retval An ErrorStatus enumeration value: - * - SUCCESS: RTC registers are synchronised - * - ERROR: RTC registers are not synchronised - */ -ErrorStatus RTC_WaitForSynchro(void) -{ - __IO uint32_t synchrocounter = 0; - ErrorStatus status = ERROR; - uint32_t synchrostatus = 0x00; - - if ((RTC->CR & RTC_CR_BYPSHAD) != RESET) - { - /* Bypass shadow mode */ - status = SUCCESS; - } - else - { - /* Disable the write protection for RTC registers */ - RTC->WPR = 0xCA; - RTC->WPR = 0x53; - - /* Clear RSF flag */ - RTC->ISR &= (uint32_t)RTC_RSF_MASK; - - /* Wait the registers to be synchronised */ - do - { - synchrostatus = RTC->ISR & RTC_ISR_RSF; - synchrocounter++; - } while((synchrocounter != SYNCHRO_TIMEOUT) && (synchrostatus == 0x00)); - - if ((RTC->ISR & RTC_ISR_RSF) != RESET) - { - status = SUCCESS; - } - else - { - status = ERROR; - } - - /* Disable the write protection for RTC registers */ - RTC->WPR = 0xFF; - } - - return (status); -} - -/** - * @brief Enables or disables the RTC reference clock detection. - * @param NewState: new state of the RTC reference clock. - * This parameter can be: ENABLE or DISABLE. - * @retval An ErrorStatus enumeration value: - * - SUCCESS: RTC reference clock detection is enabled - * - ERROR: RTC reference clock detection is disabled - */ -ErrorStatus RTC_RefClockCmd(FunctionalState NewState) -{ - ErrorStatus status = ERROR; - - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - /* Disable the write protection for RTC registers */ - RTC->WPR = 0xCA; - RTC->WPR = 0x53; - - /* Set Initialization mode */ - if (RTC_EnterInitMode() == ERROR) - { - status = ERROR; - } - else - { - if (NewState != DISABLE) - { - /* Enable the RTC reference clock detection */ - RTC->CR |= RTC_CR_REFCKON; - } - else - { - /* Disable the RTC reference clock detection */ - RTC->CR &= ~RTC_CR_REFCKON; - } - /* Exit Initialization mode */ - RTC_ExitInitMode(); - - status = SUCCESS; - } - - /* Enable the write protection for RTC registers */ - RTC->WPR = 0xFF; - - return status; -} - -/** - * @brief Enables or Disables the Bypass Shadow feature. - * @note When the Bypass Shadow is enabled the calendar value are taken - * directly from the Calendar counter. - * @param NewState: new state of the Bypass Shadow feature. - * This parameter can be: ENABLE or DISABLE. - * @retval None -*/ -void RTC_BypassShadowCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - /* Disable the write protection for RTC registers */ - RTC->WPR = 0xCA; - RTC->WPR = 0x53; - - if (NewState != DISABLE) - { - /* Set the BYPSHAD bit */ - RTC->CR |= (uint8_t)RTC_CR_BYPSHAD; - } - else - { - /* Reset the BYPSHAD bit */ - RTC->CR &= (uint8_t)~RTC_CR_BYPSHAD; - } - - /* Enable the write protection for RTC registers */ - RTC->WPR = 0xFF; -} - -/** - * @} - */ - -/** - * @brief Set the RTC current time. - * @param RTC_Format: specifies the format of the entered parameters. - * This parameter can be one of the following values: - * @arg RTC_Format_BIN: Binary data format - * @arg RTC_Format_BCD: BCD data format - * @param RTC_TimeStruct: pointer to a RTC_TimeTypeDef structure that contains - * the time configuration information for the RTC. - * @retval An ErrorStatus enumeration value: - * - SUCCESS: RTC Time register is configured - * - ERROR: RTC Time register is not configured - */ -ErrorStatus RTC_SetTime(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_TimeStruct) -{ - uint32_t tmpreg = 0; - ErrorStatus status = ERROR; - - /* Check the parameters */ - assert_param(IS_RTC_FORMAT(RTC_Format)); - - if (RTC_Format == RTC_Format_BIN) - { - if ((RTC->CR & RTC_CR_FMT) != (uint32_t)RESET) - { - assert_param(IS_RTC_HOUR12(RTC_TimeStruct->RTC_Hours)); - assert_param(IS_RTC_H12(RTC_TimeStruct->RTC_H12)); - } - else - { - RTC_TimeStruct->RTC_H12 = 0x00; - assert_param(IS_RTC_HOUR24(RTC_TimeStruct->RTC_Hours)); - } - assert_param(IS_RTC_MINUTES(RTC_TimeStruct->RTC_Minutes)); - assert_param(IS_RTC_SECONDS(RTC_TimeStruct->RTC_Seconds)); - } - else - { - if ((RTC->CR & RTC_CR_FMT) != (uint32_t)RESET) - { - tmpreg = RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Hours); - assert_param(IS_RTC_HOUR12(tmpreg)); - assert_param(IS_RTC_H12(RTC_TimeStruct->RTC_H12)); - } - else - { - RTC_TimeStruct->RTC_H12 = 0x00; - assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Hours))); - } - assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Minutes))); - assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Seconds))); - } - - /* Check the input parameters format */ - if (RTC_Format != RTC_Format_BIN) - { - tmpreg = (((uint32_t)(RTC_TimeStruct->RTC_Hours) << 16) | \ - ((uint32_t)(RTC_TimeStruct->RTC_Minutes) << 8) | \ - ((uint32_t)RTC_TimeStruct->RTC_Seconds) | \ - ((uint32_t)(RTC_TimeStruct->RTC_H12) << 16)); - } - else - { - tmpreg = (uint32_t)(((uint32_t)RTC_ByteToBcd2(RTC_TimeStruct->RTC_Hours) << 16) | \ - ((uint32_t)RTC_ByteToBcd2(RTC_TimeStruct->RTC_Minutes) << 8) | \ - ((uint32_t)RTC_ByteToBcd2(RTC_TimeStruct->RTC_Seconds)) | \ - (((uint32_t)RTC_TimeStruct->RTC_H12) << 16)); - } - - /* Disable the write protection for RTC registers */ - RTC->WPR = 0xCA; - RTC->WPR = 0x53; - - /* Set Initialization mode */ - if (RTC_EnterInitMode() == ERROR) - { - status = ERROR; - } - else - { - /* Set the RTC_TR register */ - RTC->TR = (uint32_t)(tmpreg & RTC_TR_RESERVED_MASK); - - /* Exit Initialization mode */ - RTC_ExitInitMode(); - - /* If RTC_CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */ - if ((RTC->CR & RTC_CR_BYPSHAD) == RESET) - { - if (RTC_WaitForSynchro() == ERROR) - { - status = ERROR; - } - else - { - status = SUCCESS; - } - } - else - { - status = SUCCESS; - } - - } - /* Enable the write protection for RTC registers */ - RTC->WPR = 0xFF; - - return status; -} - -/** - * @brief Fills each RTC_TimeStruct member with its default value - * (Time = 00h:00min:00sec). - * @param RTC_TimeStruct: pointer to a RTC_TimeTypeDef structure which will be - * initialized. - * @retval None - */ -void RTC_TimeStructInit(RTC_TimeTypeDef* RTC_TimeStruct) -{ - /* Time = 00h:00min:00sec */ - RTC_TimeStruct->RTC_H12 = RTC_H12_AM; - RTC_TimeStruct->RTC_Hours = 0; - RTC_TimeStruct->RTC_Minutes = 0; - RTC_TimeStruct->RTC_Seconds = 0; -} - -/** - * @brief Get the RTC current Time. - * @param RTC_Format: specifies the format of the returned parameters. - * This parameter can be one of the following values: - * @arg RTC_Format_BIN: Binary data format - * @arg RTC_Format_BCD: BCD data format - * @param RTC_TimeStruct: pointer to a RTC_TimeTypeDef structure that will - * contain the returned current time configuration. - * @retval None - */ -void RTC_GetTime(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_TimeStruct) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_RTC_FORMAT(RTC_Format)); - - /* Get the RTC_TR register */ - tmpreg = (uint32_t)(RTC->TR & RTC_TR_RESERVED_MASK); - - /* Fill the structure fields with the read parameters */ - RTC_TimeStruct->RTC_Hours = (uint8_t)((tmpreg & (RTC_TR_HT | RTC_TR_HU)) >> 16); - RTC_TimeStruct->RTC_Minutes = (uint8_t)((tmpreg & (RTC_TR_MNT | RTC_TR_MNU)) >>8); - RTC_TimeStruct->RTC_Seconds = (uint8_t)(tmpreg & (RTC_TR_ST | RTC_TR_SU)); - RTC_TimeStruct->RTC_H12 = (uint8_t)((tmpreg & (RTC_TR_PM)) >> 16); - - /* Check the input parameters format */ - if (RTC_Format == RTC_Format_BIN) - { - /* Convert the structure parameters to Binary format */ - RTC_TimeStruct->RTC_Hours = (uint8_t)RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Hours); - RTC_TimeStruct->RTC_Minutes = (uint8_t)RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Minutes); - RTC_TimeStruct->RTC_Seconds = (uint8_t)RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Seconds); - } -} - -/** - * @brief Gets the RTC current Calendar Subseconds value. - * @note This function freeze the Time and Date registers after reading the - * SSR register. - * @param None - * @retval RTC current Calendar Subseconds value. - */ -uint32_t RTC_GetSubSecond(void) -{ - uint32_t tmpreg = 0; - - /* Get subseconds values from the correspondent registers*/ - tmpreg = (uint32_t)(RTC->SSR); - - /* Read DR register to unfroze calendar registers */ - (void) (RTC->DR); - - return (tmpreg); -} - -/** - * @brief Set the RTC current date. - * @param RTC_Format: specifies the format of the entered parameters. - * This parameter can be one of the following values: - * @arg RTC_Format_BIN: Binary data format - * @arg RTC_Format_BCD: BCD data format - * @param RTC_DateStruct: pointer to a RTC_DateTypeDef structure that contains - * the date configuration information for the RTC. - * @retval An ErrorStatus enumeration value: - * - SUCCESS: RTC Date register is configured - * - ERROR: RTC Date register is not configured - */ -ErrorStatus RTC_SetDate(uint32_t RTC_Format, RTC_DateTypeDef* RTC_DateStruct) -{ - uint32_t tmpreg = 0; - ErrorStatus status = ERROR; - - /* Check the parameters */ - assert_param(IS_RTC_FORMAT(RTC_Format)); - - if ((RTC_Format == RTC_Format_BIN) && ((RTC_DateStruct->RTC_Month & 0x10) == 0x10)) - { - RTC_DateStruct->RTC_Month = (RTC_DateStruct->RTC_Month & (uint32_t)~(0x10)) + 0x0A; - } - if (RTC_Format == RTC_Format_BIN) - { - assert_param(IS_RTC_YEAR(RTC_DateStruct->RTC_Year)); - assert_param(IS_RTC_MONTH(RTC_DateStruct->RTC_Month)); - assert_param(IS_RTC_DATE(RTC_DateStruct->RTC_Date)); - } - else - { - assert_param(IS_RTC_YEAR(RTC_Bcd2ToByte(RTC_DateStruct->RTC_Year))); - tmpreg = RTC_Bcd2ToByte(RTC_DateStruct->RTC_Month); - assert_param(IS_RTC_MONTH(tmpreg)); - tmpreg = RTC_Bcd2ToByte(RTC_DateStruct->RTC_Date); - assert_param(IS_RTC_DATE(tmpreg)); - } - assert_param(IS_RTC_WEEKDAY(RTC_DateStruct->RTC_WeekDay)); - - /* Check the input parameters format */ - if (RTC_Format != RTC_Format_BIN) - { - tmpreg = ((((uint32_t)RTC_DateStruct->RTC_Year) << 16) | \ - (((uint32_t)RTC_DateStruct->RTC_Month) << 8) | \ - ((uint32_t)RTC_DateStruct->RTC_Date) | \ - (((uint32_t)RTC_DateStruct->RTC_WeekDay) << 13)); - } - else - { - tmpreg = (((uint32_t)RTC_ByteToBcd2(RTC_DateStruct->RTC_Year) << 16) | \ - ((uint32_t)RTC_ByteToBcd2(RTC_DateStruct->RTC_Month) << 8) | \ - ((uint32_t)RTC_ByteToBcd2(RTC_DateStruct->RTC_Date)) | \ - ((uint32_t)RTC_DateStruct->RTC_WeekDay << 13)); - } - - /* Disable the write protection for RTC registers */ - RTC->WPR = 0xCA; - RTC->WPR = 0x53; - - /* Set Initialization mode */ - if (RTC_EnterInitMode() == ERROR) - { - status = ERROR; - } - else - { - /* Set the RTC_DR register */ - RTC->DR = (uint32_t)(tmpreg & RTC_DR_RESERVED_MASK); - - /* Exit Initialization mode */ - RTC_ExitInitMode(); - - /* If RTC_CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */ - if ((RTC->CR & RTC_CR_BYPSHAD) == RESET) - { - if (RTC_WaitForSynchro() == ERROR) - { - status = ERROR; - } - else - { - status = SUCCESS; - } - } - else - { - status = SUCCESS; - } - } - /* Enable the write protection for RTC registers */ - RTC->WPR = 0xFF; - - return status; -} - -/** - * @brief Fills each RTC_DateStruct member with its default value - * (Monday, January 01 xx00). - * @param RTC_DateStruct: pointer to a RTC_DateTypeDef structure which will be - * initialized. - * @retval None - */ -void RTC_DateStructInit(RTC_DateTypeDef* RTC_DateStruct) -{ - /* Monday, January 01 xx00 */ - RTC_DateStruct->RTC_WeekDay = RTC_Weekday_Monday; - RTC_DateStruct->RTC_Date = 1; - RTC_DateStruct->RTC_Month = RTC_Month_January; - RTC_DateStruct->RTC_Year = 0; -} - -/** - * @brief Get the RTC current date. - * @param RTC_Format: specifies the format of the returned parameters. - * This parameter can be one of the following values: - * @arg RTC_Format_BIN: Binary data format - * @arg RTC_Format_BCD: BCD data format - * @param RTC_DateStruct: pointer to a RTC_DateTypeDef structure that will - * contain the returned current date configuration. - * @retval None - */ -void RTC_GetDate(uint32_t RTC_Format, RTC_DateTypeDef* RTC_DateStruct) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_RTC_FORMAT(RTC_Format)); - - /* Get the RTC_TR register */ - tmpreg = (uint32_t)(RTC->DR & RTC_DR_RESERVED_MASK); - - /* Fill the structure fields with the read parameters */ - RTC_DateStruct->RTC_Year = (uint8_t)((tmpreg & (RTC_DR_YT | RTC_DR_YU)) >> 16); - RTC_DateStruct->RTC_Month = (uint8_t)((tmpreg & (RTC_DR_MT | RTC_DR_MU)) >> 8); - RTC_DateStruct->RTC_Date = (uint8_t)(tmpreg & (RTC_DR_DT | RTC_DR_DU)); - RTC_DateStruct->RTC_WeekDay = (uint8_t)((tmpreg & (RTC_DR_WDU)) >> 13); - - /* Check the input parameters format */ - if (RTC_Format == RTC_Format_BIN) - { - /* Convert the structure parameters to Binary format */ - RTC_DateStruct->RTC_Year = (uint8_t)RTC_Bcd2ToByte(RTC_DateStruct->RTC_Year); - RTC_DateStruct->RTC_Month = (uint8_t)RTC_Bcd2ToByte(RTC_DateStruct->RTC_Month); - RTC_DateStruct->RTC_Date = (uint8_t)RTC_Bcd2ToByte(RTC_DateStruct->RTC_Date); - RTC_DateStruct->RTC_WeekDay = (uint8_t)(RTC_DateStruct->RTC_WeekDay); - } -} - -/** - * @} - */ -/** - * @brief Set the specified RTC Alarm. - * @note The Alarm register can only be written when the corresponding Alarm - * is disabled (Use the RTC_AlarmCmd(DISABLE)). - * @param RTC_Format: specifies the format of the returned parameters. - * This parameter can be one of the following values: - * @arg RTC_Format_BIN: Binary data format - * @arg RTC_Format_BCD: BCD data format - * @param RTC_Alarm: specifies the alarm to be configured. - * This parameter can be one of the following values: - * @arg RTC_Alarm_A: to select Alarm A - * @param RTC_AlarmStruct: pointer to a RTC_AlarmTypeDef structure that - * contains the alarm configuration parameters. - * @retval None - */ -void RTC_SetAlarm(uint32_t RTC_Format, uint32_t RTC_Alarm, RTC_AlarmTypeDef* RTC_AlarmStruct) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_RTC_FORMAT(RTC_Format)); - assert_param(IS_RTC_ALARM(RTC_Alarm)); - assert_param(IS_RTC_ALARM_MASK(RTC_AlarmStruct->RTC_AlarmMask)); - assert_param(IS_RTC_ALARM_DATE_WEEKDAY_SEL(RTC_AlarmStruct->RTC_AlarmDateWeekDaySel)); - - if (RTC_Format == RTC_Format_BIN) - { - if ((RTC->CR & RTC_CR_FMT) != (uint32_t)RESET) - { - assert_param(IS_RTC_HOUR12(RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours)); - assert_param(IS_RTC_H12(RTC_AlarmStruct->RTC_AlarmTime.RTC_H12)); - } - else - { - RTC_AlarmStruct->RTC_AlarmTime.RTC_H12 = 0x00; - assert_param(IS_RTC_HOUR24(RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours)); - } - assert_param(IS_RTC_MINUTES(RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes)); - assert_param(IS_RTC_SECONDS(RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds)); - - if(RTC_AlarmStruct->RTC_AlarmDateWeekDaySel == RTC_AlarmDateWeekDaySel_Date) - { - assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(RTC_AlarmStruct->RTC_AlarmDateWeekDay)); - } - else - { - assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(RTC_AlarmStruct->RTC_AlarmDateWeekDay)); - } - } - else - { - if ((RTC->CR & RTC_CR_FMT) != (uint32_t)RESET) - { - tmpreg = RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours); - assert_param(IS_RTC_HOUR12(tmpreg)); - assert_param(IS_RTC_H12(RTC_AlarmStruct->RTC_AlarmTime.RTC_H12)); - } - else - { - RTC_AlarmStruct->RTC_AlarmTime.RTC_H12 = 0x00; - assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours))); - } - - assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes))); - assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds))); - - if(RTC_AlarmStruct->RTC_AlarmDateWeekDaySel == RTC_AlarmDateWeekDaySel_Date) - { - tmpreg = RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmDateWeekDay); - assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(tmpreg)); - } - else - { - tmpreg = RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmDateWeekDay); - assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(tmpreg)); - } - } - - /* Check the input parameters format */ - if (RTC_Format != RTC_Format_BIN) - { - tmpreg = (((uint32_t)(RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours) << 16) | \ - ((uint32_t)(RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes) << 8) | \ - ((uint32_t)RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds) | \ - ((uint32_t)(RTC_AlarmStruct->RTC_AlarmTime.RTC_H12) << 16) | \ - ((uint32_t)(RTC_AlarmStruct->RTC_AlarmDateWeekDay) << 24) | \ - ((uint32_t)RTC_AlarmStruct->RTC_AlarmDateWeekDaySel) | \ - ((uint32_t)RTC_AlarmStruct->RTC_AlarmMask)); - } - else - { - tmpreg = (((uint32_t)RTC_ByteToBcd2(RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours) << 16) | \ - ((uint32_t)RTC_ByteToBcd2(RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes) << 8) | \ - ((uint32_t)RTC_ByteToBcd2(RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds)) | \ - ((uint32_t)(RTC_AlarmStruct->RTC_AlarmTime.RTC_H12) << 16) | \ - ((uint32_t)RTC_ByteToBcd2(RTC_AlarmStruct->RTC_AlarmDateWeekDay) << 24) | \ - ((uint32_t)RTC_AlarmStruct->RTC_AlarmDateWeekDaySel) | \ - ((uint32_t)RTC_AlarmStruct->RTC_AlarmMask)); - } - - /* Disable the write protection for RTC registers */ - RTC->WPR = 0xCA; - RTC->WPR = 0x53; - - /* Configure the Alarm register */ - RTC->ALRMAR = (uint32_t)tmpreg; - - /* Enable the write protection for RTC registers */ - RTC->WPR = 0xFF; -} - -/** - * @brief Fills each RTC_AlarmStruct member with its default value - * (Time = 00h:00mn:00sec / Date = 1st day of the month/Mask = - * all fields are masked). - * @param RTC_AlarmStruct: pointer to a @ref RTC_AlarmTypeDef structure which - * will be initialized. - * @retval None - */ -void RTC_AlarmStructInit(RTC_AlarmTypeDef* RTC_AlarmStruct) -{ - /* Alarm Time Settings : Time = 00h:00mn:00sec */ - RTC_AlarmStruct->RTC_AlarmTime.RTC_H12 = RTC_H12_AM; - RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours = 0; - RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes = 0; - RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds = 0; - - /* Alarm Date Settings : Date = 1st day of the month */ - RTC_AlarmStruct->RTC_AlarmDateWeekDaySel = RTC_AlarmDateWeekDaySel_Date; - RTC_AlarmStruct->RTC_AlarmDateWeekDay = 1; - - /* Alarm Masks Settings : Mask = all fields are not masked */ - RTC_AlarmStruct->RTC_AlarmMask = RTC_AlarmMask_None; -} - -/** - * @brief Get the RTC Alarm value and masks. - * @param RTC_Format: specifies the format of the output parameters. - * This parameter can be one of the following values: - * @arg RTC_Format_BIN: Binary data format - * @arg RTC_Format_BCD: BCD data format - * @param RTC_Alarm: specifies the alarm to be read. - * This parameter can be one of the following values: - * @arg RTC_Alarm_A: to select Alarm A - * @param RTC_AlarmStruct: pointer to a RTC_AlarmTypeDef structure that will - * contains the output alarm configuration values. - * @retval None - */ -void RTC_GetAlarm(uint32_t RTC_Format, uint32_t RTC_Alarm, RTC_AlarmTypeDef* RTC_AlarmStruct) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_RTC_FORMAT(RTC_Format)); - assert_param(IS_RTC_ALARM(RTC_Alarm)); - - /* Get the RTC_ALRMAR register */ - tmpreg = (uint32_t)(RTC->ALRMAR); - - /* Fill the structure with the read parameters */ - RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours = (uint32_t)((tmpreg & (RTC_ALRMAR_HT | \ - RTC_ALRMAR_HU)) >> 16); - RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes = (uint32_t)((tmpreg & (RTC_ALRMAR_MNT | \ - RTC_ALRMAR_MNU)) >> 8); - RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds = (uint32_t)(tmpreg & (RTC_ALRMAR_ST | \ - RTC_ALRMAR_SU)); - RTC_AlarmStruct->RTC_AlarmTime.RTC_H12 = (uint32_t)((tmpreg & RTC_ALRMAR_PM) >> 16); - RTC_AlarmStruct->RTC_AlarmDateWeekDay = (uint32_t)((tmpreg & (RTC_ALRMAR_DT | RTC_ALRMAR_DU)) >> 24); - RTC_AlarmStruct->RTC_AlarmDateWeekDaySel = (uint32_t)(tmpreg & RTC_ALRMAR_WDSEL); - RTC_AlarmStruct->RTC_AlarmMask = (uint32_t)(tmpreg & RTC_AlarmMask_All); - - if (RTC_Format == RTC_Format_BIN) - { - RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours = RTC_Bcd2ToByte(RTC_AlarmStruct-> \ - RTC_AlarmTime.RTC_Hours); - RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes = RTC_Bcd2ToByte(RTC_AlarmStruct-> \ - RTC_AlarmTime.RTC_Minutes); - RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds = RTC_Bcd2ToByte(RTC_AlarmStruct-> \ - RTC_AlarmTime.RTC_Seconds); - RTC_AlarmStruct->RTC_AlarmDateWeekDay = RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmDateWeekDay); - } -} - -/** - * @brief Enables or disables the specified RTC Alarm. - * @param RTC_Alarm: specifies the alarm to be configured. - * This parameter can be any combination of the following values: - * @arg RTC_Alarm_A: to select Alarm A - * @param NewState: new state of the specified alarm. - * This parameter can be: ENABLE or DISABLE. - * @retval An ErrorStatus enumeration value: - * - SUCCESS: RTC Alarm is enabled/disabled - * - ERROR: RTC Alarm is not enabled/disabled - */ -ErrorStatus RTC_AlarmCmd(uint32_t RTC_Alarm, FunctionalState NewState) -{ - __IO uint32_t alarmcounter = 0x00; - uint32_t alarmstatus = 0x00; - ErrorStatus status = ERROR; - - /* Check the parameters */ - assert_param(IS_RTC_CMD_ALARM(RTC_Alarm)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - /* Disable the write protection for RTC registers */ - RTC->WPR = 0xCA; - RTC->WPR = 0x53; - - /* Configure the Alarm state */ - if (NewState != DISABLE) - { - RTC->CR |= (uint32_t)RTC_Alarm; - - status = SUCCESS; - } - else - { - /* Disable the Alarm in RTC_CR register */ - RTC->CR &= (uint32_t)~RTC_Alarm; - - /* Wait till RTC ALRxWF flag is set and if Time out is reached exit */ - do - { - alarmstatus = RTC->ISR & (RTC_Alarm >> 8); - alarmcounter++; - } while((alarmcounter != INITMODE_TIMEOUT) && (alarmstatus == 0x00)); - - if ((RTC->ISR & (RTC_Alarm >> 8)) == RESET) - { - status = ERROR; - } - else - { - status = SUCCESS; - } - } - - /* Enable the write protection for RTC registers */ - RTC->WPR = 0xFF; - - return status; -} - -/** - * @brief Configure the RTC AlarmA/B Subseconds value and mask. - * @note This function is performed only when the Alarm is disabled. - * @param RTC_Alarm: specifies the alarm to be configured. - * This parameter can be one of the following values: - * @arg RTC_Alarm_A: to select Alarm A - * @param RTC_AlarmSubSecondValue: specifies the Subseconds value. - * This parameter can be a value from 0 to 0x00007FFF. - * @param RTC_AlarmSubSecondMask: specifies the Subseconds Mask. - * This parameter can be any combination of the following values: - * @arg RTC_AlarmSubSecondMask_All: All Alarm SS fields are masked. - * There is no comparison on sub seconds for Alarm. - * @arg RTC_AlarmSubSecondMask_SS14_1: SS[14:1] are don't care in Alarm comparison. - * Only SS[0] is compared - * @arg RTC_AlarmSubSecondMask_SS14_2: SS[14:2] are don't care in Alarm comparison. - * Only SS[1:0] are compared - * @arg RTC_AlarmSubSecondMask_SS14_3: SS[14:3] are don't care in Alarm comparison. - * Only SS[2:0] are compared - * @arg RTC_AlarmSubSecondMask_SS14_4: SS[14:4] are don't care in Alarm comparison. - * Only SS[3:0] are compared - * @arg RTC_AlarmSubSecondMask_SS14_5: SS[14:5] are don't care in Alarm comparison. - * Only SS[4:0] are compared - * @arg RTC_AlarmSubSecondMask_SS14_6: SS[14:6] are don't care in Alarm comparison. - * Only SS[5:0] are compared - * @arg RTC_AlarmSubSecondMask_SS14_7: SS[14:7] are don't care in Alarm comparison. - * Only SS[6:0] are compared - * @arg RTC_AlarmSubSecondMask_SS14_8: SS[14:8] are don't care in Alarm comparison. - * Only SS[7:0] are compared - * @arg RTC_AlarmSubSecondMask_SS14_9: SS[14:9] are don't care in Alarm comparison. - * Only SS[8:0] are compared - * @arg RTC_AlarmSubSecondMask_SS14_10: SS[14:10] are don't care in Alarm comparison. - * Only SS[9:0] are compared - * @arg RTC_AlarmSubSecondMask_SS14_11: SS[14:11] are don't care in Alarm comparison. - * Only SS[10:0] are compared - * @arg RTC_AlarmSubSecondMask_SS14_12: SS[14:12] are don't care in Alarm comparison. - * Only SS[11:0] are compared - * @arg RTC_AlarmSubSecondMask_SS14_13: SS[14:13] are don't care in Alarm comparison. - * Only SS[12:0] are compared - * @arg RTC_AlarmSubSecondMask_SS14: SS[14] is don't care in Alarm comparison. - * Only SS[13:0] are compared - * @arg RTC_AlarmSubSecondMask_None: SS[14:0] are compared and must match to activate alarm - * @retval None - */ -void RTC_AlarmSubSecondConfig(uint32_t RTC_Alarm, uint32_t RTC_AlarmSubSecondValue, uint8_t RTC_AlarmSubSecondMask) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_RTC_ALARM(RTC_Alarm)); - assert_param(IS_RTC_ALARM_SUB_SECOND_VALUE(RTC_AlarmSubSecondValue)); - assert_param(IS_RTC_ALARM_SUB_SECOND_MASK(RTC_AlarmSubSecondMask)); - - /* Disable the write protection for RTC registers */ - RTC->WPR = 0xCA; - RTC->WPR = 0x53; - - /* Configure the Alarm A or Alarm B SubSecond registers */ - tmpreg = (uint32_t) (((uint32_t)(RTC_AlarmSubSecondValue)) | ((uint32_t)(RTC_AlarmSubSecondMask) << 24)); - - /* Configure the AlarmA SubSecond register */ - RTC->ALRMASSR = tmpreg; - - /* Enable the write protection for RTC registers */ - RTC->WPR = 0xFF; - -} - -/** - * @brief Gets the RTC Alarm Subseconds value. - * @param RTC_Alarm: specifies the alarm to be read. - * This parameter can be one of the following values: - * @arg RTC_Alarm_A: to select Alarm A - * @param None - * @retval RTC Alarm Subseconds value. - */ -uint32_t RTC_GetAlarmSubSecond(uint32_t RTC_Alarm) -{ - uint32_t tmpreg = 0; - - /* Get the RTC_ALRMAR register */ - tmpreg = (uint32_t)((RTC->ALRMASSR) & RTC_ALRMASSR_SS); - - return (tmpreg); -} - -/** - * @} - */ - -/** - * @brief Adds or substract one hour from the current time. - * @param RTC_DayLightSaveOperation: the value of hour adjustment. - * This parameter can be one of the following values: - * @arg RTC_DayLightSaving_SUB1H: Substract one hour (winter time) - * @arg RTC_DayLightSaving_ADD1H: Add one hour (summer time) - * @param RTC_StoreOperation: Specifies the value to be written in the BCK bit - * in CR register to store the operation. - * This parameter can be one of the following values: - * @arg RTC_StoreOperation_Reset: BCK Bit Reset - * @arg RTC_StoreOperation_Set: BCK Bit Set - * @retval None - */ -void RTC_DayLightSavingConfig(uint32_t RTC_DayLightSaving, uint32_t RTC_StoreOperation) -{ - /* Check the parameters */ - assert_param(IS_RTC_DAYLIGHT_SAVING(RTC_DayLightSaving)); - assert_param(IS_RTC_STORE_OPERATION(RTC_StoreOperation)); - - /* Disable the write protection for RTC registers */ - RTC->WPR = 0xCA; - RTC->WPR = 0x53; - - /* Clear the bits to be configured */ - RTC->CR &= (uint32_t)~(RTC_CR_BCK); - - /* Configure the RTC_CR register */ - RTC->CR |= (uint32_t)(RTC_DayLightSaving | RTC_StoreOperation); - - /* Enable the write protection for RTC registers */ - RTC->WPR = 0xFF; -} - -/** - * @brief Returns the RTC Day Light Saving stored operation. - * @param None - * @retval RTC Day Light Saving stored operation. - * - RTC_StoreOperation_Reset - * - RTC_StoreOperation_Set - */ -uint32_t RTC_GetStoreOperation(void) -{ - return (RTC->CR & RTC_CR_BCK); -} - -/** - * @} - */ - -/** - * @brief Configures the RTC output source (AFO_ALARM). - * @param RTC_Output: Specifies which signal will be routed to the RTC output. - * This parameter can be one of the following values: - * @arg RTC_Output_Disable: No output selected - * @arg RTC_Output_AlarmA: signal of AlarmA mapped to output - * @arg RTC_Output_WakeUp: signal of WakeUp mapped to output - * @param RTC_OutputPolarity: Specifies the polarity of the output signal. - * This parameter can be one of the following: - * @arg RTC_OutputPolarity_High: The output pin is high when the - * ALRAF is high (depending on OSEL) - * @arg RTC_OutputPolarity_Low: The output pin is low when the - * ALRAF is high (depending on OSEL) - * @retval None - */ -void RTC_OutputConfig(uint32_t RTC_Output, uint32_t RTC_OutputPolarity) -{ - /* Check the parameters */ - assert_param(IS_RTC_OUTPUT(RTC_Output)); - assert_param(IS_RTC_OUTPUT_POL(RTC_OutputPolarity)); - - /* Disable the write protection for RTC registers */ - RTC->WPR = 0xCA; - RTC->WPR = 0x53; - - /* Clear the bits to be configured */ - RTC->CR &= (uint32_t)~(RTC_CR_OSEL | RTC_CR_POL); - - /* Configure the output selection and polarity */ - RTC->CR |= (uint32_t)(RTC_Output | RTC_OutputPolarity); - - /* Enable the write protection for RTC registers */ - RTC->WPR = 0xFF; -} - -/** - * @} - */ - -/** - * @brief Enables or disables the RTC clock to be output through the relative pin. - * @param NewState: new state of the digital calibration Output. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RTC_CalibOutputCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - /* Disable the write protection for RTC registers */ - RTC->WPR = 0xCA; - RTC->WPR = 0x53; - - if (NewState != DISABLE) - { - /* Enable the RTC clock output */ - RTC->CR |= (uint32_t)RTC_CR_COE; - } - else - { - /* Disable the RTC clock output */ - RTC->CR &= (uint32_t)~RTC_CR_COE; - } - - /* Enable the write protection for RTC registers */ - RTC->WPR = 0xFF; -} - -/** - * @brief Configure the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz). - * @param RTC_CalibOutput: Select the Calibration output Selection . - * This parameter can be one of the following values: - * @arg RTC_CalibOutput_512Hz: A signal has a regular waveform at 512Hz. - * @arg RTC_CalibOutput_1Hz: A signal has a regular waveform at 1Hz. - * @retval None -*/ -void RTC_CalibOutputConfig(uint32_t RTC_CalibOutput) -{ - /* Check the parameters */ - assert_param(IS_RTC_CALIB_OUTPUT(RTC_CalibOutput)); - - /* Disable the write protection for RTC registers */ - RTC->WPR = 0xCA; - RTC->WPR = 0x53; - - /*clear flags before config*/ - RTC->CR &= (uint32_t)~(RTC_CR_CALSEL); - - /* Configure the RTC_CR register */ - RTC->CR |= (uint32_t)RTC_CalibOutput; - - /* Enable the write protection for RTC registers */ - RTC->WPR = 0xFF; -} - -/** - * @brief Configures the Smooth Calibration Settings. - * @param RTC_SmoothCalibPeriod: Select the Smooth Calibration Period. - * This parameter can be can be one of the following values: - * @arg RTC_SmoothCalibPeriod_32sec: The smooth calibration periode is 32s. - * @arg RTC_SmoothCalibPeriod_16sec: The smooth calibration periode is 16s. - * @arg RTC_SmoothCalibPeriod_8sec: The smooth calibartion periode is 8s. - * @param RTC_SmoothCalibPlusPulses: Select to Set or reset the CALP bit. - * This parameter can be one of the following values: - * @arg RTC_SmoothCalibPlusPulses_Set: Add one RTCCLK puls every 2**11 pulses. - * @arg RTC_SmoothCalibPlusPulses_Reset: No RTCCLK pulses are added. - * @param RTC_SmouthCalibMinusPulsesValue: Select the value of CALM[8:0] bits. - * This parameter can be one any value from 0 to 0x000001FF. - * @retval An ErrorStatus enumeration value: - * - SUCCESS: RTC Calib registers are configured - * - ERROR: RTC Calib registers are not configured -*/ -ErrorStatus RTC_SmoothCalibConfig(uint32_t RTC_SmoothCalibPeriod, - uint32_t RTC_SmoothCalibPlusPulses, - uint32_t RTC_SmouthCalibMinusPulsesValue) -{ - ErrorStatus status = ERROR; - uint32_t recalpfcount = 0; - - /* Check the parameters */ - assert_param(IS_RTC_SMOOTH_CALIB_PERIOD(RTC_SmoothCalibPeriod)); - assert_param(IS_RTC_SMOOTH_CALIB_PLUS(RTC_SmoothCalibPlusPulses)); - assert_param(IS_RTC_SMOOTH_CALIB_MINUS(RTC_SmouthCalibMinusPulsesValue)); - - /* Disable the write protection for RTC registers */ - RTC->WPR = 0xCA; - RTC->WPR = 0x53; - - /* check if a calibration is pending*/ - if ((RTC->ISR & RTC_ISR_RECALPF) != RESET) - { - /* wait until the Calibration is completed*/ - while (((RTC->ISR & RTC_ISR_RECALPF) != RESET) && (recalpfcount != RECALPF_TIMEOUT)) - { - recalpfcount++; - } - } - - /* check if the calibration pending is completed or if there is no calibration operation at all*/ - if ((RTC->ISR & RTC_ISR_RECALPF) == RESET) - { - /* Configure the Smooth calibration settings */ - RTC->CALR = (uint32_t)((uint32_t)RTC_SmoothCalibPeriod | (uint32_t)RTC_SmoothCalibPlusPulses | (uint32_t)RTC_SmouthCalibMinusPulsesValue); - - status = SUCCESS; - } - else - { - status = ERROR; - } - - /* Enable the write protection for RTC registers */ - RTC->WPR = 0xFF; - - return (ErrorStatus)(status); -} - -/** - * @} - */ - -/** - * @brief Enables or Disables the RTC TimeStamp functionality with the - * specified time stamp pin stimulating edge. - * @param RTC_TimeStampEdge: Specifies the pin edge on which the TimeStamp is - * activated. - * This parameter can be one of the following: - * @arg RTC_TimeStampEdge_Rising: the Time stamp event occurs on the rising - * edge of the related pin. - * @arg RTC_TimeStampEdge_Falling: the Time stamp event occurs on the - * falling edge of the related pin. - * @param NewState: new state of the TimeStamp. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RTC_TimeStampCmd(uint32_t RTC_TimeStampEdge, FunctionalState NewState) -{ - uint32_t tmpreg = 0; - - /* 设置Edge的边缘触发，没有特定位的情况 */ - /* Check the parameters */ - assert_param(IS_RTC_TIMESTAMP_EDGE(RTC_TimeStampEdge)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - /* Get the RTC_CR register and clear the bits to be configured */ - tmpreg = (uint32_t)(RTC->CR & (uint32_t)~(RTC_CR_TSEDGE | RTC_CR_TSE)); - - /* Get the new configuration */ - if (NewState != DISABLE) - { - tmpreg |= (uint32_t)(RTC_TimeStampEdge | RTC_CR_TSE); - } - else - { - tmpreg |= (uint32_t)(RTC_TimeStampEdge); - } - - /* Disable the write protection for RTC registers */ - RTC->WPR = 0xCA; - RTC->WPR = 0x53; - - /* Configure the Time Stamp TSEDGE and Enable bits */ - RTC->CR = (uint32_t)tmpreg; - - /* Enable the write protection for RTC registers */ - RTC->WPR = 0xFF; -} - -/** - * @brief Get the RTC TimeStamp value and masks. - * @param RTC_Format: specifies the format of the output parameters. - * This parameter can be one of the following values: - * @arg RTC_Format_BIN: Binary data format - * @arg RTC_Format_BCD: BCD data format - * @param RTC_StampTimeStruct: pointer to a RTC_TimeTypeDef structure that will - * contains the TimeStamp time values. - * @param RTC_StampDateStruct: pointer to a RTC_DateTypeDef structure that will - * contains the TimeStamp date values. - * @retval None - */ -void RTC_GetTimeStamp(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_StampTimeStruct, - RTC_DateTypeDef* RTC_StampDateStruct) -{ - uint32_t tmptime = 0, tmpdate = 0; - - /* Check the parameters */ - assert_param(IS_RTC_FORMAT(RTC_Format)); - - /* Get the TimeStamp time and date registers values */ - tmptime = (uint32_t)(RTC->TSTR & RTC_TR_RESERVED_MASK); - tmpdate = (uint32_t)(RTC->TSDR & RTC_DR_RESERVED_MASK); - - /* Fill the Time structure fields with the read parameters */ - RTC_StampTimeStruct->RTC_Hours = (uint8_t)((tmptime & (RTC_TR_HT | RTC_TR_HU)) >> 16); - RTC_StampTimeStruct->RTC_Minutes = (uint8_t)((tmptime & (RTC_TR_MNT | RTC_TR_MNU)) >> 8); - RTC_StampTimeStruct->RTC_Seconds = (uint8_t)(tmptime & (RTC_TR_ST | RTC_TR_SU)); - RTC_StampTimeStruct->RTC_H12 = (uint8_t)((tmptime & (RTC_TR_PM)) >> 16); - - /* Fill the Date structure fields with the read parameters */ - RTC_StampDateStruct->RTC_Year = 0; - RTC_StampDateStruct->RTC_Month = (uint8_t)((tmpdate & (RTC_DR_MT | RTC_DR_MU)) >> 8); - RTC_StampDateStruct->RTC_Date = (uint8_t)(tmpdate & (RTC_DR_DT | RTC_DR_DU)); - RTC_StampDateStruct->RTC_WeekDay = (uint8_t)((tmpdate & (RTC_DR_WDU)) >> 13); - - /* Check the input parameters format */ - if (RTC_Format == RTC_Format_BIN) - { - /* Convert the Time structure parameters to Binary format */ - RTC_StampTimeStruct->RTC_Hours = (uint8_t)RTC_Bcd2ToByte(RTC_StampTimeStruct->RTC_Hours); - RTC_StampTimeStruct->RTC_Minutes = (uint8_t)RTC_Bcd2ToByte(RTC_StampTimeStruct->RTC_Minutes); - RTC_StampTimeStruct->RTC_Seconds = (uint8_t)RTC_Bcd2ToByte(RTC_StampTimeStruct->RTC_Seconds); - - /* Convert the Date structure parameters to Binary format */ - RTC_StampDateStruct->RTC_Month = (uint8_t)RTC_Bcd2ToByte(RTC_StampDateStruct->RTC_Month); - RTC_StampDateStruct->RTC_Date = (uint8_t)RTC_Bcd2ToByte(RTC_StampDateStruct->RTC_Date); - RTC_StampDateStruct->RTC_WeekDay = (uint8_t)RTC_Bcd2ToByte(RTC_StampDateStruct->RTC_WeekDay); - } -} - -/** - * @brief Get the RTC timestamp Subseconds value. - * @param None - * @retval RTC current timestamp Subseconds value. - */ -uint32_t RTC_GetTimeStampSubSecond(void) -{ - /* Get timestamp subseconds values from the correspondent registers */ - return (uint32_t)(RTC->TSSSR); -} - -/** - * @} - */ -/** - * @brief Configures the select Tamper pin edge. - * @param RTC_Tamper: Selected tamper pin. - * This parameter can be any combination of the following values: - * @arg RTC_Tamper_1: Select Tamper 1. - * @arg RTC_Tamper_2: Select Tamper 2. - * @param RTC_TamperTrigger: Specifies the trigger on the tamper pin that - * stimulates tamper event. - * This parameter can be one of the following values: - * @arg RTC_TamperTrigger_RisingEdge: Rising Edge of the tamper pin causes tamper event. - * @arg RTC_TamperTrigger_FallingEdge: Falling Edge of the tamper pin causes tamper event. - * @arg RTC_TamperTrigger_LowLevel: Low Level of the tamper pin causes tamper event. - * @arg RTC_TamperTrigger_HighLevel: High Level of the tamper pin causes tamper event. - * @retval None - */ -void RTC_TamperTriggerConfig(uint32_t RTC_Tamper, uint32_t RTC_TamperTrigger) -{ - /* Check the parameters */ - assert_param(IS_RTC_TAMPER(RTC_Tamper)); - assert_param(IS_RTC_TAMPER_TRIGGER(RTC_TamperTrigger)); - - if (RTC_TamperTrigger == RTC_TamperTrigger_RisingEdge) - { - /* Configure the RTC_TAFCR register */ - RTC->TAFCR &= (uint32_t)((uint32_t)~(RTC_Tamper << 1)); - } - else - { - /* Configure the RTC_TAFCR register */ - RTC->TAFCR |= (uint32_t)(RTC_Tamper << 1); - } -} - -/** - * @brief Enables or Disables the Tamper detection. - * @param RTC_Tamper: Selected tamper pin. - * This parameter can be any combination of the following values: - * @arg RTC_Tamper_1: Select Tamper 1. - * @arg RTC_Tamper_2: Select Tamper 2. - * @param NewState: new state of the tamper pin. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RTC_TamperCmd(uint32_t RTC_Tamper, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_RTC_TAMPER(RTC_Tamper)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the selected Tamper pin */ - RTC->TAFCR |= (uint32_t)RTC_Tamper; - } - else - { - /* Disable the selected Tamper pin */ - RTC->TAFCR &= (uint32_t)~RTC_Tamper; - } -} - -/** - * @brief Configures the Tampers Filter. - * @param RTC_TamperFilter: Specifies the tampers filter. - * This parameter can be one of the following values: - * @arg RTC_TamperFilter_Disable: Tamper filter is disabled. - * @arg RTC_TamperFilter_2Sample: Tamper is activated after 2 consecutive - * samples at the active level - * @arg RTC_TamperFilter_4Sample: Tamper is activated after 4 consecutive - * samples at the active level - * @arg RTC_TamperFilter_8Sample: Tamper is activated after 8 consecutive - * samples at the active level - * @retval None - */ -void RTC_TamperFilterConfig(uint32_t RTC_TamperFilter) -{ - /* Check the parameters */ - assert_param(IS_RTC_TAMPER_FILTER(RTC_TamperFilter)); - - /* Clear TAMPFLT[1:0] bits in the RTC_TAFCR register */ - RTC->TAFCR &= (uint32_t)~(RTC_TAFCR_TAMPFLT); - - /* Configure the RTC_TAFCR register */ - RTC->TAFCR |= (uint32_t)RTC_TamperFilter; -} - -/** - * @brief Configures the Tampers Sampling Frequency. - * @param RTC_TamperSamplingFreq: Specifies the tampers Sampling Frequency. - * This parameter can be one of the following values: - * @arg RTC_TamperSamplingFreq_RTCCLK_Div32768: Each of the tamper inputs are sampled - * with a frequency = RTCCLK / 32768 - * @arg RTC_TamperSamplingFreq_RTCCLK_Div16384: Each of the tamper inputs are sampled - * with a frequency = RTCCLK / 16384 - * @arg RTC_TamperSamplingFreq_RTCCLK_Div8192: Each of the tamper inputs are sampled - * with a frequency = RTCCLK / 8192 - * @arg RTC_TamperSamplingFreq_RTCCLK_Div4096: Each of the tamper inputs are sampled - * with a frequency = RTCCLK / 4096 - * @arg RTC_TamperSamplingFreq_RTCCLK_Div2048: Each of the tamper inputs are sampled - * with a frequency = RTCCLK / 2048 - * @arg RTC_TamperSamplingFreq_RTCCLK_Div1024: Each of the tamper inputs are sampled - * with a frequency = RTCCLK / 1024 - * @arg RTC_TamperSamplingFreq_RTCCLK_Div512: Each of the tamper inputs are sampled - * with a frequency = RTCCLK / 512 - * @arg RTC_TamperSamplingFreq_RTCCLK_Div256: Each of the tamper inputs are sampled - * with a frequency = RTCCLK / 256 - * @retval None - */ -void RTC_TamperSamplingFreqConfig(uint32_t RTC_TamperSamplingFreq) -{ - /* Check the parameters */ - assert_param(IS_RTC_TAMPER_SAMPLING_FREQ(RTC_TamperSamplingFreq)); - - /* Clear TAMPFREQ[2:0] bits in the RTC_TAFCR register */ - RTC->TAFCR &= (uint32_t)~(RTC_TAFCR_TAMPFREQ); - - /* Configure the RTC_TAFCR register */ - RTC->TAFCR |= (uint32_t)RTC_TamperSamplingFreq; -} - -/** - * @brief Configures the Tampers Pins input Precharge Duration. - * @param RTC_TamperPrechargeDuration: Specifies the Tampers Pins input - * Precharge Duration. - * This parameter can be one of the following values: - * @arg RTC_TamperPrechargeDuration_1RTCCLK: Tamper pins are pre-charged before sampling during 1 RTCCLK cycle - * @arg RTC_TamperPrechargeDuration_2RTCCLK: Tamper pins are pre-charged before sampling during 2 RTCCLK cycle - * @arg RTC_TamperPrechargeDuration_4RTCCLK: Tamper pins are pre-charged before sampling during 4 RTCCLK cycle - * @arg RTC_TamperPrechargeDuration_8RTCCLK: Tamper pins are pre-charged before sampling during 8 RTCCLK cycle - * @retval None - */ -void RTC_TamperPinsPrechargeDuration(uint32_t RTC_TamperPrechargeDuration) -{ - /* Check the parameters */ - assert_param(IS_RTC_TAMPER_PRECHARGE_DURATION(RTC_TamperPrechargeDuration)); - - /* Clear TAMPPRCH[1:0] bits in the RTC_TAFCR register */ - RTC->TAFCR &= (uint32_t)~(RTC_TAFCR_TAMPPRCH); - - /* Configure the RTC_TAFCR register */ - RTC->TAFCR |= (uint32_t)RTC_TamperPrechargeDuration; -} - -/** - * @brief Enables or Disables the TimeStamp on Tamper Detection Event. - * @note The timestamp is valid even the TSE bit in tamper control register - * is reset. - * @param NewState: new state of the timestamp on tamper event. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RTC_TimeStampOnTamperDetectionCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Save timestamp on tamper detection event */ - RTC->TAFCR |= (uint32_t)RTC_TAFCR_TAMPTS; - } - else - { - /* Tamper detection does not cause a timestamp to be saved */ - RTC->TAFCR &= (uint32_t)~RTC_TAFCR_TAMPTS; - } -} - -/** - * @brief Enables or Disables the Precharge of Tamper pin. - * @param NewState: new state of tamper pull up. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RTC_TamperPullUpCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable precharge of the selected Tamper pin */ - RTC->TAFCR &= (uint32_t)~RTC_TAFCR_TAMPPUDIS; - } - else - { - /* Disable precharge of the selected Tamper pin */ - RTC->TAFCR |= (uint32_t)RTC_TAFCR_TAMPPUDIS; - } -} - -/** - * @} - */ -/** - * @brief Configures the RTC Output Pin mode. - * @param RTC_OutputType: specifies the RTC Output (PC13) pin mode. - * This parameter can be one of the following values: - * @arg RTC_OutputType_OpenDrain: RTC Output (PC13) is configured in - * Open Drain mode. - * @arg RTC_OutputType_PushPull: RTC Output (PC13) is configured in - * Push Pull mode. - * @retval None - */ -void RTC_OutputTypeConfig(uint32_t RTC_OutputType) -{ - /* Check the parameters */ - assert_param(IS_RTC_OUTPUT_TYPE(RTC_OutputType)); - - RTC->TAFCR &= (uint32_t)~(RTC_TAFCR_ALARMOUTTYPE); - RTC->TAFCR |= (uint32_t)(RTC_OutputType); -} - -/** - * @} - */ -/** - * @brief Configures the Synchronization Shift Control Settings. - * @note When REFCKON is set, firmware must not write to Shift control register - * @param RTC_ShiftAdd1S: Select to add or not 1 second to the time Calendar. - * This parameter can be one of the following values : - * @arg RTC_ShiftAdd1S_Set: Add one second to the clock calendar. - * @arg RTC_ShiftAdd1S_Reset: No effect. - * @param RTC_ShiftSubFS: Select the number of Second Fractions to Substitute. - * This parameter can be one any value from 0 to 0x7FFF. - * @retval An ErrorStatus enumeration value: - * - SUCCESS: RTC Shift registers are configured - * - ERROR: RTC Shift registers are not configured -*/ -ErrorStatus RTC_SynchroShiftConfig(uint32_t RTC_ShiftAdd1S, uint32_t RTC_ShiftSubFS) -{ - ErrorStatus status = ERROR; - uint32_t shpfcount = 0; - - /* Check the parameters */ - assert_param(IS_RTC_SHIFT_ADD1S(RTC_ShiftAdd1S)); - assert_param(IS_RTC_SHIFT_SUBFS(RTC_ShiftSubFS)); - - /* Disable the write protection for RTC registers */ - RTC->WPR = 0xCA; - RTC->WPR = 0x53; - - /* Check if a Shift is pending*/ - if ((RTC->ISR & RTC_ISR_SHPF) != RESET) - { - /* Wait until the shift is completed*/ - while (((RTC->ISR & RTC_ISR_SHPF) != RESET) && (shpfcount != SHPF_TIMEOUT)) - { - shpfcount++; - } - } - - /* Check if the Shift pending is completed or if there is no Shift operation at all*/ - if ((RTC->ISR & RTC_ISR_SHPF) == RESET) - { - /* check if the reference clock detection is disabled */ - if((RTC->CR & RTC_CR_REFCKON) == RESET) - { - /* Configure the Shift settings */ - RTC->SHIFTR = (uint32_t)(uint32_t)(RTC_ShiftSubFS) | (uint32_t)(RTC_ShiftAdd1S); - - if(RTC_WaitForSynchro() == ERROR) - { - status = ERROR; - } - else - { - status = SUCCESS; - } - } - else - { - status = ERROR; - } - } - else - { - status = ERROR; - } - - /* Enable the write protection for RTC registers */ - RTC->WPR = 0xFF; - - return (ErrorStatus)(status); -} - -/** - * @} - */ - -/** - * @brief Enables or disables the specified RTC interrupts. - * @param RTC_IT: specifies the RTC interrupt sources to be enabled or disabled. - * This parameter can be any combination of the following values: - * @arg RTC_IT_TS: Time Stamp interrupt mask - * @arg RTC_IT_WUT: WakeUp Timer interrupt mask - * @arg RTC_IT_ALRA: Alarm A interrupt mask - * @arg RTC_IT_TAMP: Tamper event interrupt mask - * @param NewState: new state of the specified RTC interrupts. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RTC_ITConfig(uint32_t RTC_IT, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_RTC_CONFIG_IT(RTC_IT)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - /* Disable the write protection for RTC registers */ - RTC->WPR = 0xCA; - RTC->WPR = 0x53; - - if (NewState != DISABLE) - { - /* Configure the Interrupts in the RTC_CR register */ - RTC->CR |= (uint32_t)(RTC_IT & ~RTC_TAFCR_TAMPIE); - /* Configure the Tamper Interrupt in the RTC_TAFCR */ - RTC->TAFCR |= (uint32_t)(RTC_IT & RTC_TAFCR_TAMPIE); - } - else - { - /* Configure the Interrupts in the RTC_CR register */ - RTC->CR &= (uint32_t)~(RTC_IT & (uint32_t)~RTC_TAFCR_TAMPIE); - /* Configure the Tamper Interrupt in the RTC_TAFCR */ - RTC->TAFCR &= (uint32_t)~(RTC_IT & RTC_TAFCR_TAMPIE); - } - /* Enable the write protection for RTC registers */ - RTC->WPR = 0xFF; -} - -/** - * @brief Checks whether the specified RTC flag is set or not. - * @param RTC_FLAG: specifies the flag to check. - * This parameter can be one of the following values: - * @arg RTC_FLAG_RECALPF: RECALPF event flag - * @arg RTC_FLAG_TAMP2F: Tamper 2 event flag - * @arg RTC_FLAG_TAMP1F: Tamper 1 event flag - * @arg RTC_FLAG_TSOVF: Time Stamp OverFlow flag - * @arg RTC_FLAG_TSF: Time Stamp event flag - * @arg RTC_FLAG_WUTF: WakeUp Timer flag - * @arg RTC_FLAG_ALRAF: Alarm A flag - * @arg RTC_FLAG_INITF: Initialization mode flag - * @arg RTC_FLAG_RSF: Registers Synchronized flag - * @arg RTC_FLAG_INITS: Registers Configured flag - * @retval The new state of RTC_FLAG (SET or RESET). - */ -FlagStatus RTC_GetFlagStatus(uint32_t RTC_FLAG) -{ - FlagStatus bitstatus = RESET; - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_RTC_GET_FLAG(RTC_FLAG)); - - /* Get all the flags */ - tmpreg = (uint32_t)(RTC->ISR & RTC_FLAGS_MASK); - - /* Return the status of the flag */ - if ((tmpreg & RTC_FLAG) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - return bitstatus; -} - -/** - * @brief Clears the RTC's pending flags. - * @param RTC_FLAG: specifies the RTC flag to clear. - * This parameter can be any combination of the following values: - * @arg RTC_FLAG_TAMP2F: Tamper 2 event flag - * @arg RTC_FLAG_TAMP1F: Tamper 1 event flag - * @arg RTC_FLAG_TSOVF: Time Stamp Overflow flag - * @arg RTC_FLAG_TSF: Time Stamp event flag - * @arg RTC_FLAG_WUTF: WakeUp Timer flag - * @arg RTC_FLAG_ALRAF: Alarm A flag - * @arg RTC_FLAG_RSF: Registers Synchronized flag - * @retval None - */ -void RTC_ClearFlag(uint32_t RTC_FLAG) -{ - /* Check the parameters */ - assert_param(IS_RTC_CLEAR_FLAG(RTC_FLAG)); - - /* Clear the Flags in the RTC_ISR register */ - RTC->ISR = (uint32_t)((uint32_t)(~((RTC_FLAG | RTC_ISR_INIT)& 0x0001FFFF) | (uint32_t)(RTC->ISR & RTC_ISR_INIT))); -} - -/** - * @brief Checks whether the specified RTC interrupt has occurred or not. - * @param RTC_IT: specifies the RTC interrupt source to check. - * This parameter can be one of the following values: - * @arg RTC_IT_TS: Time Stamp interrupt - * @arg RTC_IT_WUT: WakeUp Timer interrupt - * @arg RTC_IT_ALRA: Alarm A interrupt - * @arg RTC_IT_TAMP1: Tamper1 event interrupt - * @arg RTC_IT_TAMP2: Tamper2 event interrupt - * @retval The new state of RTC_IT (SET or RESET). - */ -ITStatus RTC_GetITStatus(uint32_t RTC_IT) -{ - ITStatus bitstatus = RESET; - uint32_t tmpreg = 0, enablestatus = 0; - - /* Check the parameters */ - assert_param(IS_RTC_GET_IT(RTC_IT)); - - /* Get the TAMPER Interrupt enable bit and pending bit */ - tmpreg = (uint32_t)(RTC->TAFCR & (RTC_TAFCR_TAMPIE)); - - /* Get the Interrupt enable Status */ - enablestatus = (uint32_t)((RTC->CR & RTC_IT) | (tmpreg & ((RTC_IT >> (RTC_IT >> 18)) >> 15))); - - /* Get the Interrupt pending bit */ - tmpreg = (uint32_t)((RTC->ISR & (uint32_t)(RTC_IT >> 4))); - - /* Get the status of the Interrupt */ - if ((enablestatus != (uint32_t)RESET) && ((tmpreg & 0x0000FFFF) != (uint32_t)RESET)) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - return bitstatus; -} - -/** - * @brief Clears the RTC's interrupt pending bits. - * @param RTC_IT: specifies the RTC interrupt pending bit to clear. - * This parameter can be any combination of the following values: - * @arg RTC_IT_TS: Time Stamp interrupt - * @arg RTC_IT_WUT: WakeUp Timer interrupt - * @arg RTC_IT_ALRA: Alarm A interrupt - * @arg RTC_IT_TAMP1: Tamper1 event interrupt - * @arg RTC_IT_TAMP2: Tamper2 event interrupt - * @retval None - */ -void RTC_ClearITPendingBit(uint32_t RTC_IT) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_RTC_CLEAR_IT(RTC_IT)); - - /* Get the RTC_ISR Interrupt pending bits mask */ - tmpreg = (uint32_t)(RTC_IT >> 4); - - /* Clear the interrupt pending bits in the RTC_ISR register */ - RTC->ISR = (uint32_t)((uint32_t)(~((tmpreg | RTC_ISR_INIT)& 0x0000FFFF) | (uint32_t)(RTC->ISR & RTC_ISR_INIT))); -} - -/** - * @} - */ - -/** - * @brief Converts a 2 digit decimal to BCD format. - * @param Value: Byte to be converted. - * @retval Converted byte - */ -static uint8_t RTC_ByteToBcd2(uint8_t Value) -{ - uint8_t bcdhigh = 0; - - while (Value >= 10) - { - bcdhigh++; - Value -= 10; - } - - return ((uint8_t)(bcdhigh << 4) | Value); -} - -/** - * @brief Convert from 2 digit BCD to Binary. - * @param Value: BCD value to be converted. - * @retval Converted word - */ -static uint8_t RTC_Bcd2ToByte(uint8_t Value) -{ - uint8_t tmp = 0; - tmp = ((uint8_t)(Value & (uint8_t)0xF0) >> (uint8_t)0x4) * 10; - return (tmp + (Value & (uint8_t)0x0F)); -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT FMD *****END OF FILE****/ diff --git a/bsp/ft32/libraries/FT32F0xx/FT32F0xx_Driver/Src/ft32f0xx_spi.c b/bsp/ft32/libraries/FT32F0xx/FT32F0xx_Driver/Src/ft32f0xx_spi.c deleted file mode 100644 index adf1ddbfc90..00000000000 --- a/bsp/ft32/libraries/FT32F0xx/FT32F0xx_Driver/Src/ft32f0xx_spi.c +++ /dev/null @@ -1,825 +0,0 @@ -/** - ****************************************************************************** - * @file ft32f0xx_spi.c - * @author FMD AE - * @brief This file provides firmware functions to manage the following - * functionalities of the Serial peripheral interface (SPI): - * + Initialization and Configuration - * + Data transfers functions - * + Hardware CRC Calculation - * + DMA transfers management - * + Interrupts and flags management - * @version V1.0.0 - * @data 2021-07-01 - ****************************************************************************** - */ -/* Includes ------------------------------------------------------------------*/ -#include "ft32f0xx_spi.h" -#include "ft32f0xx_rcc.h" - -/* SPI registers Masks */ -#define CR1_CLEAR_MASK ((uint16_t)0x3040) -#define CR1_CLEAR_MASK2 ((uint16_t)0xFFFB) -#define CR2_LDMA_MASK ((uint16_t)0x9FFF) - -#define I2SCFGR_CLEAR_Mask ((uint16_t)0xF040) - - -/** - * @brief Deinitializes the SPIx peripheral registers to their default - * reset values. - * @param SPIx: where x can be 1 or 2 to select the SPI peripheral. - * @retval None - */ -void SPI_I2S_DeInit(SPI_TypeDef* SPIx) -{ - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - - if (SPIx == SPI1) - { - /* Enable SPI1 reset state */ - RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, ENABLE); - /* Release SPI1 from reset state */ - RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, DISABLE); - } - else - { - if (SPIx == SPI2) - { - /* Enable SPI2 reset state */ - RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI2, ENABLE); - /* Release SPI2 from reset state */ - RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI2, DISABLE); - } - } -} - -/** - * @brief Fills each SPI_InitStruct member with its default value. - * @param SPI_InitStruct: pointer to a SPI_InitTypeDef structure which will be initialized. - * @retval None - */ -void SPI_StructInit(SPI_InitTypeDef* SPI_InitStruct) -{ -/*--------------- Reset SPI init structure parameters values -----------------*/ - /* Initialize the SPI_Direction member */ - SPI_InitStruct->SPI_Direction = SPI_Direction_2Lines_FullDuplex; - /* Initialize the SPI_Mode member */ - SPI_InitStruct->SPI_Mode = SPI_Mode_Slave; - /* Initialize the SPI_DataSize member */ - SPI_InitStruct->SPI_DataSize = SPI_DataSize_8b; - /* Initialize the SPI_CPOL member */ - SPI_InitStruct->SPI_CPOL = SPI_CPOL_Low; - /* Initialize the SPI_CPHA member */ - SPI_InitStruct->SPI_CPHA = SPI_CPHA_1Edge; - /* Initialize the SPI_NSS member */ - SPI_InitStruct->SPI_NSS = SPI_NSS_Hard; - /* Initialize the SPI_BaudRatePrescaler member */ - SPI_InitStruct->SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_2; - /* Initialize the SPI_FirstBit member */ - SPI_InitStruct->SPI_FirstBit = SPI_FirstBit_MSB; - /* Initialize the SPI_CRCPolynomial member */ - SPI_InitStruct->SPI_CRCPolynomial = 7; -} - -/** - * @brief Initializes the SPIx peripheral according to the specified - * parameters in the SPI_InitStruct. - * @param SPIx: where x can be 1 or 2 to select the SPI peripheral. - * @param SPI_InitStruct: pointer to a SPI_InitTypeDef structure that - * contains the configuration information for the specified SPI peripheral. - * @retval None - */ -void SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct) -{ - uint16_t tmpreg = 0; - - /* check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - - /* Check the SPI parameters */ - assert_param(IS_SPI_DIRECTION_MODE(SPI_InitStruct->SPI_Direction)); - assert_param(IS_SPI_MODE(SPI_InitStruct->SPI_Mode)); - assert_param(IS_SPI_DATA_SIZE(SPI_InitStruct->SPI_DataSize)); - assert_param(IS_SPI_CPOL(SPI_InitStruct->SPI_CPOL)); - assert_param(IS_SPI_CPHA(SPI_InitStruct->SPI_CPHA)); - assert_param(IS_SPI_NSS(SPI_InitStruct->SPI_NSS)); - assert_param(IS_SPI_BAUDRATE_PRESCALER(SPI_InitStruct->SPI_BaudRatePrescaler)); - assert_param(IS_SPI_FIRST_BIT(SPI_InitStruct->SPI_FirstBit)); - assert_param(IS_SPI_CRC_POLYNOMIAL(SPI_InitStruct->SPI_CRCPolynomial)); - - /*---------------------------- SPIx CR1 Configuration ------------------------*/ - /* Get the SPIx CR1 value */ - tmpreg = SPIx->CR1; - /* Clear BIDIMode, BIDIOE, RxONLY, SSM, SSI, LSBFirst, BR, CPOL and CPHA bits */ - tmpreg &= CR1_CLEAR_MASK; - /* Configure SPIx: direction, NSS management, first transmitted bit, BaudRate prescaler - master/slave mode, CPOL and CPHA */ - /* Set BIDImode, BIDIOE and RxONLY bits according to SPI_Direction value */ - /* Set SSM, SSI bit according to SPI_NSS values */ - /* Set LSBFirst bit according to SPI_FirstBit value */ - /* Set BR bits according to SPI_BaudRatePrescaler value */ - /* Set CPOL bit according to SPI_CPOL value */ - /* Set CPHA bit according to SPI_CPHA value */ - tmpreg |= (uint16_t)((uint32_t)SPI_InitStruct->SPI_Direction | SPI_InitStruct->SPI_FirstBit | - SPI_InitStruct->SPI_CPOL | SPI_InitStruct->SPI_CPHA | - SPI_InitStruct->SPI_NSS | SPI_InitStruct->SPI_BaudRatePrescaler); - /* Write to SPIx CR1 */ - SPIx->CR1 = tmpreg; - /*-------------------------Data Size Configuration -----------------------*/ - /* Get the SPIx CR2 value */ - tmpreg = SPIx->CR2; - /* Clear DS[3:0] bits */ - tmpreg &=(uint16_t)~SPI_CR2_DS; - /* Configure SPIx: Data Size */ - tmpreg |= (uint16_t)(SPI_InitStruct->SPI_DataSize); - /* Write to SPIx CR2 */ - SPIx->CR2 = tmpreg; - - /*---------------------------- SPIx CRCPOLY Configuration --------------------*/ - /* Write to SPIx CRCPOLY */ - SPIx->CRCPR = SPI_InitStruct->SPI_CRCPolynomial; - - /*---------------------------- SPIx CR1 Configuration ------------------------*/ - /* Get the SPIx CR1 value */ - tmpreg = SPIx->CR1; - /* Clear MSTR bit */ - tmpreg &= CR1_CLEAR_MASK2; - /* Configure SPIx: master/slave mode */ - /* Set MSTR bit according to SPI_Mode */ - tmpreg |= (uint16_t)((uint32_t)SPI_InitStruct->SPI_Mode); - /* Write to SPIx CR1 */ - SPIx->CR1 = tmpreg; - -// /* Activate the SPI mode (Reset I2SMOD bit in I2SCFGR register) */ -// SPIx->I2SCFGR &= (uint16_t)~((uint16_t)SPI_I2SCFGR_I2SMOD); -} -/** - * @brief Enables or disables the specified SPI peripheral. - * @param SPIx: where x can be 1 or 2 to select the SPI peripheral. - * @param NewState: new state of the SPIx peripheral. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void SPI_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the selected SPI peripheral */ - SPIx->CR1 |= SPI_CR1_SPE; - } - else - { - /* Disable the selected SPI peripheral */ - SPIx->CR1 &= (uint16_t)~((uint16_t)SPI_CR1_SPE); - } -} - -/** - * @brief Enables or disables the TI Mode. - * - * @note This function can be called only after the SPI_Init() function has - * been called. - * @note When TI mode is selected, the control bits SSM, SSI, CPOL and CPHA - * are not taken into consideration and are configured by hardware - * respectively to the TI mode requirements. - * - * @param SPIx: where x can be 1 or 2 to select the SPI peripheral. - * @param NewState: new state of the selected SPI TI communication mode. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void SPI_TIModeCmd(SPI_TypeDef* SPIx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the TI mode for the selected SPI peripheral */ - SPIx->CR2 |= SPI_CR2_FRF; - } - else - { - /* Disable the TI mode for the selected SPI peripheral */ - SPIx->CR2 &= (uint16_t)~((uint16_t)SPI_CR2_FRF); - } -} -/** - * @brief Configures the data size for the selected SPI. - * @param SPIx: where x can be 1 or 2 to select the SPI peripheral. - * @param SPI_DataSize: specifies the SPI data size. - * For the SPIx peripheral this parameter can be one of the following values: - * @arg SPI_DataSize_4b: Set data size to 4 bits - * @arg SPI_DataSize_5b: Set data size to 5 bits - * @arg SPI_DataSize_6b: Set data size to 6 bits - * @arg SPI_DataSize_7b: Set data size to 7 bits - * @arg SPI_DataSize_8b: Set data size to 8 bits - * @arg SPI_DataSize_9b: Set data size to 9 bits - * @arg SPI_DataSize_10b: Set data size to 10 bits - * @arg SPI_DataSize_11b: Set data size to 11 bits - * @arg SPI_DataSize_12b: Set data size to 12 bits - * @arg SPI_DataSize_13b: Set data size to 13 bits - * @arg SPI_DataSize_14b: Set data size to 14 bits - * @arg SPI_DataSize_15b: Set data size to 15 bits - * @arg SPI_DataSize_16b: Set data size to 16 bits - * @retval None - */ -void SPI_DataSizeConfig(SPI_TypeDef* SPIx, uint16_t SPI_DataSize) -{ - uint16_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - assert_param(IS_SPI_DATA_SIZE(SPI_DataSize)); - /* Read the CR2 register */ - tmpreg = SPIx->CR2; - /* Clear DS[3:0] bits */ - tmpreg &= (uint16_t)~SPI_CR2_DS; - /* Set new DS[3:0] bits value */ - tmpreg |= SPI_DataSize; - SPIx->CR2 = tmpreg; -} - -/** - * @brief Configures the FIFO reception threshold for the selected SPI. - * @param SPIx: where x can be 1 or 2 to select the SPI peripheral. - * @param SPI_RxFIFOThreshold: specifies the FIFO reception threshold. - * This parameter can be one of the following values: - * @arg SPI_RxFIFOThreshold_HF: RXNE event is generated if the FIFO - * level is greater or equal to 1/2. - * @arg SPI_RxFIFOThreshold_QF: RXNE event is generated if the FIFO - * level is greater or equal to 1/4. - * @retval None - */ -void SPI_RxFIFOThresholdConfig(SPI_TypeDef* SPIx, uint16_t SPI_RxFIFOThreshold) -{ - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - assert_param(IS_SPI_RX_FIFO_THRESHOLD(SPI_RxFIFOThreshold)); - - /* Clear FRXTH bit */ - SPIx->CR2 &= (uint16_t)~((uint16_t)SPI_CR2_FRXTH); - - /* Set new FRXTH bit value */ - SPIx->CR2 |= SPI_RxFIFOThreshold; -} - -/** - * @brief Selects the data transfer direction in bidirectional mode for the specified SPI. - * @param SPIx: where x can be 1 or 2 to select the SPI peripheral. - * @param SPI_Direction: specifies the data transfer direction in bidirectional mode. - * This parameter can be one of the following values: - * @arg SPI_Direction_Tx: Selects Tx transmission direction - * @arg SPI_Direction_Rx: Selects Rx receive direction - * @retval None - */ -void SPI_BiDirectionalLineConfig(SPI_TypeDef* SPIx, uint16_t SPI_Direction) -{ - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - assert_param(IS_SPI_DIRECTION(SPI_Direction)); - if (SPI_Direction == SPI_Direction_Tx) - { - /* Set the Tx only mode */ - SPIx->CR1 |= SPI_Direction_Tx; - } - else - { - /* Set the Rx only mode */ - SPIx->CR1 &= SPI_Direction_Rx; - } -} - -/** - * @brief Configures internally by software the NSS pin for the selected SPI. - * @note This function can be called only after the SPI_Init() function has - * been called. - * @param SPIx: where x can be 1 or 2 to select the SPI peripheral. - * @param SPI_NSSInternalSoft: specifies the SPI NSS internal state. - * This parameter can be one of the following values: - * @arg SPI_NSSInternalSoft_Set: Set NSS pin internally - * @arg SPI_NSSInternalSoft_Reset: Reset NSS pin internally - * @retval None - */ -void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* SPIx, uint16_t SPI_NSSInternalSoft) -{ - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - assert_param(IS_SPI_NSS_INTERNAL(SPI_NSSInternalSoft)); - - if (SPI_NSSInternalSoft != SPI_NSSInternalSoft_Reset) - { - /* Set NSS pin internally by software */ - SPIx->CR1 |= SPI_NSSInternalSoft_Set; - } - else - { - /* Reset NSS pin internally by software */ - SPIx->CR1 &= SPI_NSSInternalSoft_Reset; - } -} - -/** - * @brief Enables or disables the SS output for the selected SPI. - * @note This function can be called only after the SPI_Init() function has - * been called and the NSS hardware management mode is selected. - * @param SPIx: where x can be 1 or 2 to select the SPI peripheral. - * @param NewState: new state of the SPIx SS output. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void SPI_SSOutputCmd(SPI_TypeDef* SPIx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the selected SPI SS output */ - SPIx->CR2 |= SPI_CR2_SSOE; - } - else - { - /* Disable the selected SPI SS output */ - SPIx->CR2 &= (uint16_t)~((uint16_t)SPI_CR2_SSOE); - } -} - -/** - * @brief Enables or disables the NSS pulse management mode. - * @note This function can be called only after the SPI_Init() function has - * been called. - * @note When TI mode is selected, the control bits NSSP is not taken into - * consideration and are configured by hardware respectively to the - * TI mode requirements. - * @param SPIx: where x can be 1 or 2 to select the SPI peripheral. - * @param NewState: new state of the NSS pulse management mode. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void SPI_NSSPulseModeCmd(SPI_TypeDef* SPIx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the NSS pulse management mode */ - SPIx->CR2 |= SPI_CR2_NSSP; - } - else - { - /* Disable the NSS pulse management mode */ - SPIx->CR2 &= (uint16_t)~((uint16_t)SPI_CR2_NSSP); - } -} - -/** - * @} - */ -/** - * @brief Transmits a Data through the SPIx/I2Sx peripheral. - * @param SPIx: where x can be 1 or 2 in SPI mode to select the SPI peripheral. - * @param Data: Data to be transmitted. - * @retval None - */ -void SPI_SendData8(SPI_TypeDef* SPIx, uint8_t Data) -{ - uint32_t spixbase = 0x00; - - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - - spixbase = (uint32_t)SPIx; - spixbase += 0x0C; - - *(__IO uint8_t *) spixbase = Data; -} - -/** - * @brief Transmits a Data through the SPIx/I2Sx peripheral. - * @param SPIx: where x can be 1 or 2 in SPI mode or 1 in I2S mode to select - * the SPI peripheral. - * @param Data: Data to be transmitted. - * @retval None - */ -void SPI_I2S_SendData16(SPI_TypeDef* SPIx, uint16_t Data) -{ - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - - SPIx->DR = (uint16_t)Data; -} - -/** - * @brief Returns the most recent received data by the SPIx/I2Sx peripheral. - * @param SPIx: where x can be 1 or 2 in SPI mode to select the SPI peripheral. - * @retval The value of the received data. - */ -uint8_t SPI_ReceiveData8(SPI_TypeDef* SPIx) -{ - uint32_t spixbase = 0x00; - - spixbase = (uint32_t)SPIx; - spixbase += 0x0C; - - return *(__IO uint8_t *) spixbase; -} - -/** - * @brief Returns the most recent received data by the SPIx peripheral. - * @param SPIx: where x can be 1 or 2 in SPI mode or 1 in I2S mode to select - * the SPI peripheral. - * @retval The value of the received data. - */ -uint16_t SPI_I2S_ReceiveData16(SPI_TypeDef* SPIx) -{ - return SPIx->DR; -} -/** - * @} - */ -/** - * @brief Configures the CRC calculation length for the selected SPI. - * @note This function can be called only after the SPI_Init() function has - * been called. - * @param SPIx: where x can be 1 or 2 to select the SPI peripheral. - * @param SPI_CRCLength: specifies the SPI CRC calculation length. - * This parameter can be one of the following values: - * @arg SPI_CRCLength_8b: Set CRC Calculation to 8 bits - * @arg SPI_CRCLength_16b: Set CRC Calculation to 16 bits - * @retval None - */ -void SPI_CRCLengthConfig(SPI_TypeDef* SPIx, uint16_t SPI_CRCLength) -{ - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - assert_param(IS_SPI_CRC_LENGTH(SPI_CRCLength)); - - /* Clear CRCL bit */ - SPIx->CR1 &= (uint16_t)~((uint16_t)SPI_CR1_CRCL); - - /* Set new CRCL bit value */ - SPIx->CR1 |= SPI_CRCLength; -} - -/** - * @brief Enables or disables the CRC value calculation of the transferred bytes. - * @note This function can be called only after the SPI_Init() function has - * been called. - * @param SPIx: where x can be 1 or 2 to select the SPI peripheral. - * @param NewState: new state of the SPIx CRC value calculation. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void SPI_CalculateCRC(SPI_TypeDef* SPIx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the selected SPI CRC calculation */ - SPIx->CR1 |= SPI_CR1_CRCEN; - } - else - { - /* Disable the selected SPI CRC calculation */ - SPIx->CR1 &= (uint16_t)~((uint16_t)SPI_CR1_CRCEN); - } -} - -/** - * @brief Transmit the SPIx CRC value. - * @param SPIx: where x can be 1 or 2 to select the SPI peripheral. - * @retval None - */ -void SPI_TransmitCRC(SPI_TypeDef* SPIx) -{ - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - - /* Enable the selected SPI CRC transmission */ - SPIx->CR1 |= SPI_CR1_CRCNEXT; -} - -/** - * @brief Returns the transmit or the receive CRC register value for the specified SPI. - * @param SPIx: where x can be 1 or 2 to select the SPI peripheral. - * @param SPI_CRC: specifies the CRC register to be read. - * This parameter can be one of the following values: - * @arg SPI_CRC_Tx: Selects Tx CRC register - * @arg SPI_CRC_Rx: Selects Rx CRC register - * @retval The selected CRC register value.. - */ -uint16_t SPI_GetCRC(SPI_TypeDef* SPIx, uint8_t SPI_CRC) -{ - uint16_t crcreg = 0; - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - assert_param(IS_SPI_CRC(SPI_CRC)); - - if (SPI_CRC != SPI_CRC_Rx) - { - /* Get the Tx CRC register */ - crcreg = SPIx->TXCRCR; - } - else - { - /* Get the Rx CRC register */ - crcreg = SPIx->RXCRCR; - } - /* Return the selected CRC register */ - return crcreg; -} - -/** - * @brief Returns the CRC Polynomial register value for the specified SPI. - * @param SPIx: where x can be 1 or 2 to select the SPI peripheral. - * @retval The CRC Polynomial register value. - */ -uint16_t SPI_GetCRCPolynomial(SPI_TypeDef* SPIx) -{ - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - - /* Return the CRC polynomial register */ - return SPIx->CRCPR; -} - -/** - * @} - */ -/** - * @brief Enables or disables the SPIx/I2Sx DMA interface. - * @param SPIx: where x can be 1 or 2 in SPI mode or 1 in I2S mode to select - * the SPI peripheral. - * @param SPI_I2S_DMAReq: specifies the SPI DMA transfer request to be enabled or disabled. - * This parameter can be any combination of the following values: - * @arg SPI_I2S_DMAReq_Tx: Tx buffer DMA transfer request - * @arg SPI_I2S_DMAReq_Rx: Rx buffer DMA transfer request - * @param NewState: new state of the selected SPI DMA transfer request. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - assert_param(IS_SPI_I2S_DMA_REQ(SPI_I2S_DMAReq)); - - if (NewState != DISABLE) - { - /* Enable the selected SPI DMA requests */ - SPIx->CR2 |= SPI_I2S_DMAReq; - } - else - { - /* Disable the selected SPI DMA requests */ - SPIx->CR2 &= (uint16_t)~SPI_I2S_DMAReq; - } -} - -/** - * @brief Configures the number of data to transfer type(Even/Odd) for the DMA - * last transfers and for the selected SPI. - * @note This function have a meaning only if DMA mode is selected and if - * the packing mode is used (data length <= 8 and DMA transfer size halfword) - * @param SPIx: where x can be 1 or 2 to select the SPI peripheral. - * @param SPI_LastDMATransfer: specifies the SPI last DMA transfers state. - * This parameter can be one of the following values: - * @arg SPI_LastDMATransfer_TxEvenRxEven: Number of data for transmission Even - * and number of data for reception Even. - * @arg SPI_LastDMATransfer_TxOddRxEven: Number of data for transmission Odd - * and number of data for reception Even. - * @arg SPI_LastDMATransfer_TxEvenRxOdd: Number of data for transmission Even - * and number of data for reception Odd. - * @arg SPI_LastDMATransfer_TxOddRxOdd: Number of data for transmission Odd - * and number of data for reception Odd. - * @retval None - */ -void SPI_LastDMATransferCmd(SPI_TypeDef* SPIx, uint16_t SPI_LastDMATransfer) -{ - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - assert_param(IS_SPI_LAST_DMA_TRANSFER(SPI_LastDMATransfer)); - - /* Clear LDMA_TX and LDMA_RX bits */ - SPIx->CR2 &= CR2_LDMA_MASK; - - /* Set new LDMA_TX and LDMA_RX bits value */ - SPIx->CR2 |= SPI_LastDMATransfer; -} - -/** - * @} - */ -/** - * @brief Enables or disables the specified SPI/I2S interrupts. - * @param SPIx: where x can be 1 or 2 in SPI mode or 1 in I2S mode to select - * the SPI peripheral. - * @param SPI_I2S_IT: specifies the SPI interrupt source to be enabled or disabled. - * This parameter can be one of the following values: - * @arg SPI_I2S_IT_TXE: Tx buffer empty interrupt mask - * @arg SPI_I2S_IT_RXNE: Rx buffer not empty interrupt mask - * @arg SPI_I2S_IT_ERR: Error interrupt mask - * @param NewState: new state of the specified SPI interrupt. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState) -{ - uint16_t itpos = 0, itmask = 0 ; - - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - assert_param(IS_SPI_I2S_CONFIG_IT(SPI_I2S_IT)); - - /* Get the SPI IT index */ - itpos = SPI_I2S_IT >> 4; - - /* Set the IT mask */ - itmask = (uint16_t)1 << (uint16_t)itpos; - - if (NewState != DISABLE) - { - /* Enable the selected SPI interrupt */ - SPIx->CR2 |= itmask; - } - else - { - /* Disable the selected SPI interrupt */ - SPIx->CR2 &= (uint16_t)~itmask; - } -} - -/** - * @brief Returns the current SPIx Transmission FIFO filled level. - * @param SPIx: where x can be 1 or 2 to select the SPI peripheral. - * @retval The Transmission FIFO filling state. - * - SPI_TransmissionFIFOStatus_Empty: when FIFO is empty - * - SPI_TransmissionFIFOStatus_1QuarterFull: if more than 1 quarter-full. - * - SPI_TransmissionFIFOStatus_HalfFull: if more than 1 half-full. - * - SPI_TransmissionFIFOStatus_Full: when FIFO is full. - */ -uint16_t SPI_GetTransmissionFIFOStatus(SPI_TypeDef* SPIx) -{ - /* Get the SPIx Transmission FIFO level bits */ - return (uint16_t)((SPIx->SR & SPI_SR_FTLVL)); -} - -/** - * @brief Returns the current SPIx Reception FIFO filled level. - * @param SPIx: where x can be 1 or 2 to select the SPI peripheral. - * @retval The Reception FIFO filling state. - * - SPI_ReceptionFIFOStatus_Empty: when FIFO is empty - * - SPI_ReceptionFIFOStatus_1QuarterFull: if more than 1 quarter-full. - * - SPI_ReceptionFIFOStatus_HalfFull: if more than 1 half-full. - * - SPI_ReceptionFIFOStatus_Full: when FIFO is full. - */ -uint16_t SPI_GetReceptionFIFOStatus(SPI_TypeDef* SPIx) -{ - /* Get the SPIx Reception FIFO level bits */ - return (uint16_t)((SPIx->SR & SPI_SR_FRLVL)); -} - -/** - * @brief Checks whether the specified SPI flag is set or not. - * @param SPIx: where x can be 1 or 2 in SPI mode or 1 in I2S mode to select - * the SPI peripheral. - * @param SPI_I2S_FLAG: specifies the SPI flag to check. - * This parameter can be one of the following values: - * @arg SPI_I2S_FLAG_TXE: Transmit buffer empty flag. - * @arg SPI_I2S_FLAG_RXNE: Receive buffer not empty flag. - * @arg SPI_I2S_FLAG_BSY: Busy flag. - * @arg SPI_I2S_FLAG_OVR: Overrun flag. - * @arg SPI_FLAG_MODF: Mode Fault flag. - * @arg SPI_FLAG_CRCERR: CRC Error flag. - * @arg SPI_I2S_FLAG_FRE: TI frame format error flag. - * @arg I2S_FLAG_UDR: Underrun Error flag. - * @arg I2S_FLAG_CHSIDE: Channel Side flag. - * @retval The new state of SPI_I2S_FLAG (SET or RESET). - */ -FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG) -{ - FlagStatus bitstatus = RESET; - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - assert_param(IS_SPI_I2S_GET_FLAG(SPI_I2S_FLAG)); - - /* Check the status of the specified SPI flag */ - if ((SPIx->SR & SPI_I2S_FLAG) != (uint16_t)RESET) - { - /* SPI_I2S_FLAG is set */ - bitstatus = SET; - } - else - { - /* SPI_I2S_FLAG is reset */ - bitstatus = RESET; - } - /* Return the SPI_I2S_FLAG status */ - return bitstatus; -} - -/** - * @brief Clears the SPIx CRC Error (CRCERR) flag. - * @param SPIx: where x can be 1 or 2 to select the SPI peripheral. - * @param SPI_I2S_FLAG: specifies the SPI flag to clear. - * This function clears only CRCERR flag. - * @note OVR (OverRun error) flag is cleared by software sequence: a read - * operation to SPI_DR register (SPI_I2S_ReceiveData()) followed by - * a read operation to SPI_SR register (SPI_I2S_GetFlagStatus()). - * @note MODF (Mode Fault) flag is cleared by software sequence: a read/write - * operation to SPI_SR register (SPI_I2S_GetFlagStatus()) followed by - * a write operation to SPI_CR1 register (SPI_Cmd() to enable the SPI). - * @retval None - */ -void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG) -{ - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - assert_param(IS_SPI_CLEAR_FLAG(SPI_I2S_FLAG)); - - /* Clear the selected SPI CRC Error (CRCERR) flag */ - SPIx->SR = (uint16_t)~SPI_I2S_FLAG; -} - -/** - * @brief Checks whether the specified SPI/I2S interrupt has occurred or not. - * @param SPIx: where x can be 1 or 2 in SPI mode or 1 in I2S mode to select - * the SPI peripheral. - * @param SPI_I2S_IT: specifies the SPI interrupt source to check. - * This parameter can be one of the following values: - * @arg SPI_I2S_IT_TXE: Transmit buffer empty interrupt. - * @arg SPI_I2S_IT_RXNE: Receive buffer not empty interrupt. - * @arg SPI_IT_MODF: Mode Fault interrupt. - * @arg SPI_I2S_IT_OVR: Overrun interrupt. - * @arg I2S_IT_UDR: Underrun interrupt. - * @arg SPI_I2S_IT_FRE: Format Error interrupt. - * @retval The new state of SPI_I2S_IT (SET or RESET). - */ -ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT) -{ - ITStatus bitstatus = RESET; - uint16_t itpos = 0, itmask = 0, enablestatus = 0; - - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - assert_param(IS_SPI_I2S_GET_IT(SPI_I2S_IT)); - - /* Get the SPI_I2S_IT index */ - itpos = 0x01 << (SPI_I2S_IT & 0x0F); - - /* Get the SPI_I2S_IT IT mask */ - itmask = SPI_I2S_IT >> 4; - - /* Set the IT mask */ - itmask = 0x01 << itmask; - - /* Get the SPI_I2S_IT enable bit status */ - enablestatus = (SPIx->CR2 & itmask) ; - - /* Check the status of the specified SPI interrupt */ - if (((SPIx->SR & itpos) != (uint16_t)RESET) && enablestatus) - { - /* SPI_I2S_IT is set */ - bitstatus = SET; - } - else - { - /* SPI_I2S_IT is reset */ - bitstatus = RESET; - } - /* Return the SPI_I2S_IT status */ - return bitstatus; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT FMD *****END OF FILE****/ diff --git a/bsp/ft32/libraries/FT32F0xx/FT32F0xx_Driver/Src/ft32f0xx_syscfg.c b/bsp/ft32/libraries/FT32F0xx/FT32F0xx_Driver/Src/ft32f0xx_syscfg.c deleted file mode 100644 index eefae7f62ce..00000000000 --- a/bsp/ft32/libraries/FT32F0xx/FT32F0xx_Driver/Src/ft32f0xx_syscfg.c +++ /dev/null @@ -1,227 +0,0 @@ -/** - ****************************************************************************** - * @file ft32f0xx_syscfg.c - * @author FMD AE - * @brief This file provides firmware functions to manage the following - * functionalities of the SYSCFG peripheral: - * + Remapping the memory mapped at 0x00000000 - * + Remapping the DMA channels - * + Enabling I2C fast mode plus driving capability for I2C pins - * + Configuring the EXTI lines connection to the GPIO port - * + Configuring the CFGR2 features (Connecting some internal signal - * to the break input of TIM1) - * @version V1.0.0 - * @data 2021-07-01 - ****************************************************************************** - */ -/* Includes ------------------------------------------------------------------*/ -#include "ft32f0xx_syscfg.h" - -/** - * @brief Deinitializes the SYSCFG registers to their default reset values. - * @param None - * @retval None - * @note MEM_MODE bits are not affected by APB reset. - * @note MEM_MODE bits took the value from the user option bytes. - * @note CFGR2 register is not affected by APB reset. - * @note CLABBB configuration bits are locked when set. - * @note To unlock the configuration, perform a system reset. - */ -void SYSCFG_DeInit(void) -{ - /* Set SYSCFG_CFGR1 register to reset value without affecting MEM_MODE bits */ - SYSCFG->CFGR1 &= SYSCFG_CFGR1_MEM_MODE; - /* Set EXTICRx registers to reset value */ - SYSCFG->EXTICR[0] = 0; - SYSCFG->EXTICR[1] = 0; - SYSCFG->EXTICR[2] = 0; - SYSCFG->EXTICR[3] = 0; - /* Set CFGR2 register to reset value: clear SRAM parity error flag */ - SYSCFG->CFGR2 |= 0; -} - -/** - * @brief Configures the memory mapping at address 0x00000000. - * @param SYSCFG_MemoryRemap: selects the memory remapping. - * This parameter can be one of the following values: - * @arg SYSCFG_MemoryRemap_Flash: Main Flash memory mapped at 0x00000000 - * @arg SYSCFG_MemoryRemap_SystemMemory: System Flash memory mapped at 0x00000000 - * @arg SYSCFG_MemoryRemap_SRAM: Embedded SRAM mapped at 0x00000000 - * @retval None - */ -void SYSCFG_MemoryRemapConfig(uint32_t SYSCFG_MemoryRemap) -{ - uint32_t tmpctrl = 0; - - /* Check the parameter */ - assert_param(IS_SYSCFG_MEMORY_REMAP(SYSCFG_MemoryRemap)); - - /* Get CFGR1 register value */ - tmpctrl = SYSCFG->CFGR1; - - /* Clear MEM_MODE bits */ - tmpctrl &= (uint32_t) (~SYSCFG_CFGR1_MEM_MODE); - - /* Set the new MEM_MODE bits value */ - tmpctrl |= (uint32_t) SYSCFG_MemoryRemap; - - /* Set CFGR1 register with the new memory remap configuration */ - SYSCFG->CFGR1 = tmpctrl; -} - -/** - * @brief Configure the DMA channels remapping. - * @param SYSCFG_DMARemap: selects the DMA channels remap. - * This parameter can be one of the following values: - * @arg SYSCFG_DMARemap_TIM17: Remap TIM17 DMA requests from channel1 to channel2 - * @arg SYSCFG_DMARemap_TIM16: Remap TIM16 DMA requests from channel3 to channel4 - * @arg SYSCFG_DMARemap_USART1Rx: Remap USART1 Rx DMA requests from channel3 to channel5 - * @arg SYSCFG_DMARemap_USART1Tx: Remap USART1 Tx DMA requests from channel2 to channel4 - * @arg SYSCFG_DMARemap_ADC1: Remap ADC1 DMA requests from channel1 to channel2 - * @param NewState: new state of the DMA channel remapping. - * This parameter can be: ENABLE or DISABLE. - * @note When enabled, DMA channel of the selected peripheral is remapped - * @note When disabled, Default DMA channel is mapped to the selected peripheral - * @note By default TIM17 DMA requests is mapped to channel 1, - * use SYSCFG_DMAChannelRemapConfig(SYSCFG_DMARemap_TIM17, Enable) to remap - * TIM17 DMA requests to channel 2 and use - * SYSCFG_DMAChannelRemapConfig(SYSCFG_DMARemap_TIM17, Disable) to map - * TIM17 DMA requests to channel 1 (default mapping) - * @retval None - */ -void SYSCFG_DMAChannelRemapConfig(uint32_t SYSCFG_DMARemap, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_SYSCFG_DMA_REMAP(SYSCFG_DMARemap)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Remap the DMA channel */ - SYSCFG->CFGR1 |= (uint32_t)SYSCFG_DMARemap; - } - else - { - /* use the default DMA channel mapping */ - SYSCFG->CFGR1 &= (uint32_t)(~SYSCFG_DMARemap); - } -} - -/** - * @brief Configure the I2C fast mode plus driving capability. - * @param SYSCFG_I2CFastModePlus: selects the pin. - * This parameter can be one of the following values: - * @arg SYSCFG_I2CFastModePlus_PB6: Configure fast mode plus driving capability for PB6 - * @arg SYSCFG_I2CFastModePlus_PB7: Configure fast mode plus driving capability for PB7 - * @arg SYSCFG_I2CFastModePlus_PB8: Configure fast mode plus driving capability for PB8 - * @arg SYSCFG_I2CFastModePlus_PB9: Configure fast mode plus driving capability for PB9 - * @arg SYSCFG_I2CFastModePlus_PA9: Configure fast mode plus driving capability for PA9 - * @arg SYSCFG_I2CFastModePlus_PA10: Configure fast mode plus driving capability for PA10 - * @arg SYSCFG_I2CFastModePlus_I2C1: Configure fast mode plus driving capability for PB10, PB11, PF6 and PF7 - * @arg SYSCFG_I2CFastModePlus_I2C2: Configure fast mode plus driving capability for I2C2 pins - * - * @param NewState: new state of the DMA channel remapping. - * This parameter can be: ENABLE or DISABLE. - * @note ENABLE: Enable fast mode plus driving capability for selected I2C pin - * @note DISABLE: Disable fast mode plus driving capability for selected I2C pin - * @note For I2C1, fast mode plus driving capability can be enabled on all selected - * I2C1 pins using SYSCFG_I2CFastModePlus_I2C1 parameter or independently - * on each one of the following pins PB6, PB7, PB8 and PB9. - * @note For remaining I2C1 pins (PA14, PA15...) fast mode plus driving capability - * can be enabled only by using SYSCFG_I2CFastModePlus_I2C1 parameter. - * @note For all I2C2 pins fast mode plus driving capability can be enabled - * only by using SYSCFG_I2CFastModePlus_I2C2 parameter. - * @retval None - */ -void SYSCFG_I2CFastModePlusConfig(uint32_t SYSCFG_I2CFastModePlus, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_SYSCFG_I2C_FMP(SYSCFG_I2CFastModePlus)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable fast mode plus driving capability for selected pin */ - SYSCFG->CFGR1 |= (uint32_t)SYSCFG_I2CFastModePlus; - } - else - { - /* Disable fast mode plus driving capability for selected pin */ - SYSCFG->CFGR1 &= (uint32_t)(~SYSCFG_I2CFastModePlus); - } -} - -/** @brief select the modulation envelope source - * @param SYSCFG_IRDAEnv: select the envelope source. - * This parameter can be a value - * @arg SYSCFG_IRDA_ENV_SEL_TIM16 - * @arg SYSCFG_IRDA_ENV_SEL_USART1 - * @arg SYSCFG_IRDA_ENV_SEL_USART2 - * @retval None - */ -void SYSCFG_IRDAEnvSelection(uint32_t SYSCFG_IRDAEnv) -{ - /* Check the parameters */ - assert_param(IS_SYSCFG_IRDA_ENV(SYSCFG_IRDAEnv)); - - SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_IRDA_ENV_SEL); - SYSCFG->CFGR1 |= (SYSCFG_IRDAEnv); -} - -/** - * @brief Selects the GPIO pin used as EXTI Line. - * @param EXTI_PortSourceGPIOx: selects the GPIO port to be used as source - * for EXTI lines where x can be (A, B, C, D, E or F). - * @param EXTI_PinSourcex: specifies the EXTI line to be configured. - * @note This parameter can be EXTI_PinSourcex where x can be: - * (0..15) for GPIOA, GPIOB, GPIOC, GPIOD, GPIOE, (0..10) for GPIOF. - * @retval None - */ -void SYSCFG_EXTILineConfig(uint8_t EXTI_PortSourceGPIOx, uint8_t EXTI_PinSourcex) -{ - uint32_t tmp = 0x00; - - /* Check the parameters */ - assert_param(IS_EXTI_PORT_SOURCE(EXTI_PortSourceGPIOx)); - assert_param(IS_EXTI_PIN_SOURCE(EXTI_PinSourcex)); - - tmp = ((uint32_t)0x0F) << (0x04 * (EXTI_PinSourcex & (uint8_t)0x03)); - SYSCFG->EXTICR[EXTI_PinSourcex >> 0x02] &= ~tmp; - SYSCFG->EXTICR[EXTI_PinSourcex >> 0x02] |= (((uint32_t)EXTI_PortSourceGPIOx) << (0x04 * (EXTI_PinSourcex & (uint8_t)0x03))); -} - -/** - * @brief Connect the selected parameter to the break input of TIM1. - * @note The selected configuration is locked and can be unlocked by system reset - * @param SYSCFG_Break: selects the configuration to be connected to break - * input of TIM1 - * This parameter can be any combination of the following values: - * @arg SYSCFG_Break_PVD: Connects the PVD event to the Break Input of TIM1 - * @arg SYSCFG_Break_SRAMParity: Connects the SRAM_PARITY error signal to the Break Input of TIM1 . - * @arg SYSCFG_Break_Lockup: Connects Lockup output of CortexM0 to the break input of TIM1. - * @retval None - */ -void SYSCFG_BreakConfig(uint32_t SYSCFG_Break) -{ - /* Check the parameter */ - assert_param(IS_SYSCFG_LOCK_CONFIG(SYSCFG_Break)); - - SYSCFG->CFGR2 |= (uint32_t) SYSCFG_Break; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ -/************************ (C) COPYRIGHT FMD *****END OF FILE****/ diff --git a/bsp/ft32/libraries/FT32F0xx/FT32F0xx_Driver/Src/ft32f0xx_tim.c b/bsp/ft32/libraries/FT32F0xx/FT32F0xx_Driver/Src/ft32f0xx_tim.c deleted file mode 100644 index ee417188df8..00000000000 --- a/bsp/ft32/libraries/FT32F0xx/FT32F0xx_Driver/Src/ft32f0xx_tim.c +++ /dev/null @@ -1,2885 +0,0 @@ -/** - ****************************************************************************** - * @file ft32f0xx_tim.c - * @author FMD AE - * @brief This file provides firmware functions to manage the following - * functionalities of the TIM peripheral: - * + TimeBase management - * + Output Compare management - * + Input Capture management - * + Interrupts, DMA and flags management - * + Clocks management - * + Synchronization management - * + Specific interface management - * + Specific remapping management - * @version V1.0.0 - * @data 2021-07-01 - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "ft32f0xx_tim.h" -#include "ft32f0xx_rcc.h" - - -/* ---------------------- TIM registers bit mask ------------------------ */ -#define SMCR_ETR_MASK ((uint16_t)0x00FF) -#define CCMR_OFFSET ((uint16_t)0x0018) -#define CCER_CCE_SET ((uint16_t)0x0001) -#define CCER_CCNE_SET ((uint16_t)0x0004) - - -static void TI1_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, - uint16_t TIM_ICFilter); -static void TI2_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, - uint16_t TIM_ICFilter); -static void TI3_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, - uint16_t TIM_ICFilter); -static void TI4_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, - uint16_t TIM_ICFilter); - -/** - * @brief Deinitializes the TIMx peripheral registers to their default reset values. - * @param TIMx: where x can be 1, 2, 3, 6, 7, 14, 15, 16 and 17 to select the TIM peripheral. - * @retval None - * - */ -void TIM_DeInit(TIM_TypeDef* TIMx) -{ - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - - if (TIMx == TIM1) - { - RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM1, ENABLE); - RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM1, DISABLE); - } -// else if (TIMx == TIM2) -// { -// RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, ENABLE); -// RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, DISABLE); -// } - else if (TIMx == TIM3) - { - RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, DISABLE); - } - else if (TIMx == TIM6) - { - RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM6, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM6, DISABLE); - } -// else if (TIMx == TIM7) -// { -// RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM7, ENABLE); -// RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM7, DISABLE); -// } - else if (TIMx == TIM14) - { - RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM14, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM14, DISABLE); - } - else if (TIMx == TIM15) - { - RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM15, ENABLE); - RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM15, DISABLE); - } - else if (TIMx == TIM16) - { - RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM16, ENABLE); - RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM16, DISABLE); - } - else - { - if (TIMx == TIM17) - { - RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM17, ENABLE); - RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM17, DISABLE); - } - } - -} - -/** - * @brief Initializes the TIMx Time Base Unit peripheral according to - * the specified parameters in the TIM_TimeBaseInitStruct. - * @param TIMx: where x can be 1, 2, 3, 6, 7, 14, 15, 16 and 17 to select the TIM - * peripheral. - * @param TIM_TimeBaseInitStruct: pointer to a TIM_TimeBaseInitTypeDef - * structure that contains the configuration information for - * the specified TIM peripheral. - * @retval None - */ -void TIM_TimeBaseInit(TIM_TypeDef* TIMx, TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct) -{ - uint16_t tmpcr1 = 0; - - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - assert_param(IS_TIM_COUNTER_MODE(TIM_TimeBaseInitStruct->TIM_CounterMode)); - assert_param(IS_TIM_CKD_DIV(TIM_TimeBaseInitStruct->TIM_ClockDivision)); - - tmpcr1 = TIMx->CR1; - - if((TIMx == TIM1) || (TIMx == TIM2) || (TIMx == TIM3)) - { - /* Select the Counter Mode */ - tmpcr1 &= (uint16_t)(~((uint16_t)(TIM_CR1_DIR | TIM_CR1_CMS))); - tmpcr1 |= (uint32_t)TIM_TimeBaseInitStruct->TIM_CounterMode; - } - - if(TIMx != TIM6) - { - /* Set the clock division */ - tmpcr1 &= (uint16_t)(~((uint16_t)TIM_CR1_CKD)); - tmpcr1 |= (uint32_t)TIM_TimeBaseInitStruct->TIM_ClockDivision; - } - - TIMx->CR1 = tmpcr1; - - /* Set the Autoreload value */ - TIMx->ARR = TIM_TimeBaseInitStruct->TIM_Period ; - - /* Set the Prescaler value */ - TIMx->PSC = TIM_TimeBaseInitStruct->TIM_Prescaler; - - if ((TIMx == TIM1) || (TIMx == TIM15)|| (TIMx == TIM16) || (TIMx == TIM17)) - { - /* Set the Repetition Counter value */ - TIMx->RCR = TIM_TimeBaseInitStruct->TIM_RepetitionCounter; - } - - /* Generate an update event to reload the Prescaler and the Repetition counter - values immediately */ - TIMx->EGR = TIM_PSCReloadMode_Immediate; -} - -/** - * @brief Fills each TIM_TimeBaseInitStruct member with its default value. - * @param TIM_TimeBaseInitStruct: pointer to a TIM_TimeBaseInitTypeDef structure - * which will be initialized. - * @retval None - */ -void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct) -{ - /* Set the default configuration */ - TIM_TimeBaseInitStruct->TIM_Period = 0xFFFFFFFF; - TIM_TimeBaseInitStruct->TIM_Prescaler = 0x0000; - TIM_TimeBaseInitStruct->TIM_ClockDivision = TIM_CKD_DIV1; - TIM_TimeBaseInitStruct->TIM_CounterMode = TIM_CounterMode_Up; - TIM_TimeBaseInitStruct->TIM_RepetitionCounter = 0x0000; -} - -/** - * @brief Configures the TIMx Prescaler. - * @param TIMx: where x can be 1, 2, 3, 6, 7, 14, 15, 16 and 17 to select the TIM peripheral. - * @param Prescaler: specifies the Prescaler Register value - * @param TIM_PSCReloadMode: specifies the TIM Prescaler Reload mode - * This parameter can be one of the following values: - * @arg TIM_PSCReloadMode_Update: The Prescaler is loaded at the update event. - * @arg TIM_PSCReloadMode_Immediate: The Prescaler is loaded immediatly. - * @retval None - */ -void TIM_PrescalerConfig(TIM_TypeDef* TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode) -{ - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - assert_param(IS_TIM_PRESCALER_RELOAD(TIM_PSCReloadMode)); - - /* Set the Prescaler value */ - TIMx->PSC = Prescaler; - /* Set or reset the UG Bit */ - TIMx->EGR = TIM_PSCReloadMode; -} - -/** - * @brief Specifies the TIMx Counter Mode to be used. - * @param TIMx: where x can be 1, 2, or 3 to select the TIM peripheral. - * @param TIM_CounterMode: specifies the Counter Mode to be used - * This parameter can be one of the following values: - * @arg TIM_CounterMode_Up: TIM Up Counting Mode - * @arg TIM_CounterMode_Down: TIM Down Counting Mode - * @arg TIM_CounterMode_CenterAligned1: TIM Center Aligned Mode1 - * @arg TIM_CounterMode_CenterAligned2: TIM Center Aligned Mode2 - * @arg TIM_CounterMode_CenterAligned3: TIM Center Aligned Mode3 - * @retval None - */ -void TIM_CounterModeConfig(TIM_TypeDef* TIMx, uint16_t TIM_CounterMode) -{ - uint16_t tmpcr1 = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_TIM_COUNTER_MODE(TIM_CounterMode)); - - tmpcr1 = TIMx->CR1; - /* Reset the CMS and DIR Bits */ - tmpcr1 &= (uint16_t)(~((uint16_t)(TIM_CR1_DIR | TIM_CR1_CMS))); - /* Set the Counter Mode */ - tmpcr1 |= TIM_CounterMode; - /* Write to TIMx CR1 register */ - TIMx->CR1 = tmpcr1; -} - -/** - * @brief Sets the TIMx Counter Register value - * @param TIMx: where x can be 1, 2, 3, 6, 7, 14, 15, 16 and 17 to select the TIM - * peripheral. - * @param Counter: specifies the Counter register new value. - * @retval None - */ -void TIM_SetCounter(TIM_TypeDef* TIMx, uint32_t Counter) -{ - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - - /* Set the Counter Register value */ - TIMx->CNT = Counter; -} - -/** - * @brief Sets the TIMx Autoreload Register value - * @param TIMx: where x can be 1, 2, 3, 6, 7, 14, 15, 16 and 17 to select the TIM peripheral. - * @param Autoreload: specifies the Autoreload register new value. - * @retval None - */ -void TIM_SetAutoreload(TIM_TypeDef* TIMx, uint32_t Autoreload) -{ - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - - /* Set the Autoreload Register value */ - TIMx->ARR = Autoreload; -} - -/** - * @brief Gets the TIMx Counter value. - * @param TIMx: where x can be 1, 2, 3, 6, 7, 14, 15, 16 and 17 to select the TIM - * peripheral. - * @retval Counter Register value. - */ -uint32_t TIM_GetCounter(TIM_TypeDef* TIMx) -{ - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - - /* Get the Counter Register value */ - return TIMx->CNT; -} - -/** - * @brief Gets the TIMx Prescaler value. - * @param TIMx: where x can be 1, 2, 3, 6, 7, 14, 15, 16 and 17 to select the TIM - * peripheral. - * @retval Prescaler Register value. - */ -uint16_t TIM_GetPrescaler(TIM_TypeDef* TIMx) -{ - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - - /* Get the Prescaler Register value */ - return TIMx->PSC; -} - -/** - * @brief Enables or Disables the TIMx Update event. - * @param TIMx: where x can be 1, 2, 3, 6, 7, 14, 15, 16 and 17 to select the TIM - * peripheral. - * @param NewState: new state of the TIMx UDIS bit - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void TIM_UpdateDisableConfig(TIM_TypeDef* TIMx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Set the Update Disable Bit */ - TIMx->CR1 |= TIM_CR1_UDIS; - } - else - { - /* Reset the Update Disable Bit */ - TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_UDIS); - } -} - -/** - * @brief Configures the TIMx Update Request Interrupt source. - * @param TIMx: where x can be 1, 2, 3, 6, 7, 14, 15, 16 and 17 to select the TIM - * peripheral. - * @param TIM_UpdateSource: specifies the Update source. - * This parameter can be one of the following values: - * @arg TIM_UpdateSource_Regular: Source of update is the counter - * overflow/underflow or the setting of UG bit, or an update - * generation through the slave mode controller. - * @arg TIM_UpdateSource_Global: Source of update is counter overflow/underflow. - * @retval None - */ -void TIM_UpdateRequestConfig(TIM_TypeDef* TIMx, uint16_t TIM_UpdateSource) -{ - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - assert_param(IS_TIM_UPDATE_SOURCE(TIM_UpdateSource)); - - if (TIM_UpdateSource != TIM_UpdateSource_Global) - { - /* Set the URS Bit */ - TIMx->CR1 |= TIM_CR1_URS; - } - else - { - /* Reset the URS Bit */ - TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_URS); - } -} - -/** - * @brief Enables or disables TIMx peripheral Preload register on ARR. - * @param TIMx: where x can be 1, 2, 3, 6, 7, 14, 15, 16 and 17 to select the TIM - * peripheral. - * @param NewState: new state of the TIMx peripheral Preload register - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void TIM_ARRPreloadConfig(TIM_TypeDef* TIMx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Set the ARR Preload Bit */ - TIMx->CR1 |= TIM_CR1_ARPE; - } - else - { - /* Reset the ARR Preload Bit */ - TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_ARPE); - } -} - -/** - * @brief Selects the TIMx's One Pulse Mode. - * @param TIMx: where x can be 1, 2, 3, 6, 7, 14, 15, 16 and 17 to select the TIM - * peripheral. - * @param TIM_OPMode: specifies the OPM Mode to be used. - * This parameter can be one of the following values: - * @arg TIM_OPMode_Single - * @arg TIM_OPMode_Repetitive - * @retval None - */ -void TIM_SelectOnePulseMode(TIM_TypeDef* TIMx, uint16_t TIM_OPMode) -{ - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - assert_param(IS_TIM_OPM_MODE(TIM_OPMode)); - - /* Reset the OPM Bit */ - TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_OPM); - /* Configure the OPM Mode */ - TIMx->CR1 |= TIM_OPMode; -} - -/** - * @brief Sets the TIMx Clock Division value. - * @param TIMx: where x can be 1, 2, 3, 14, 15, 16 and 17 to select the TIM peripheral. - * @param TIM_CKD: specifies the clock division value. - * This parameter can be one of the following value: - * @arg TIM_CKD_DIV1: TDTS = Tck_tim - * @arg TIM_CKD_DIV2: TDTS = 2*Tck_tim - * @arg TIM_CKD_DIV4: TDTS = 4*Tck_tim - * @retval None - */ -void TIM_SetClockDivision(TIM_TypeDef* TIMx, uint16_t TIM_CKD) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST4_PERIPH(TIMx)); - assert_param(IS_TIM_CKD_DIV(TIM_CKD)); - - /* Reset the CKD Bits */ - TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_CKD); - /* Set the CKD value */ - TIMx->CR1 |= TIM_CKD; -} - -/** - * @brief Enables or disables the specified TIM peripheral. - * @param TIMx: where x can be 1, 2, 3, 6, 7, 14, 15, 16 and 17to select the TIMx - * peripheral. - * @param NewState: new state of the TIMx peripheral. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void TIM_Cmd(TIM_TypeDef* TIMx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the TIM Counter */ - TIMx->CR1 |= TIM_CR1_CEN; - } - else - { - /* Disable the TIM Counter */ - TIMx->CR1 &= (uint16_t)(~((uint16_t)TIM_CR1_CEN)); - } -} - -/** - * @} - */ -/** - * @brief Configures the: Break feature, dead time, Lock level, OSSI/OSSR State - * and the AOE(automatic output enable). - * @param TIMx: where x can be 1, 15, 16 or 17 to select the TIM - * @param TIM_BDTRInitStruct: pointer to a TIM_BDTRInitTypeDef structure that - * contains the BDTR Register configuration information for the TIM peripheral. - * @retval None - */ -void TIM_BDTRConfig(TIM_TypeDef* TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST2_PERIPH(TIMx)); - assert_param(IS_TIM_OSSR_STATE(TIM_BDTRInitStruct->TIM_OSSRState)); - assert_param(IS_TIM_OSSI_STATE(TIM_BDTRInitStruct->TIM_OSSIState)); - assert_param(IS_TIM_LOCK_LEVEL(TIM_BDTRInitStruct->TIM_LOCKLevel)); - assert_param(IS_TIM_BREAK_STATE(TIM_BDTRInitStruct->TIM_Break)); - assert_param(IS_TIM_BREAK_POLARITY(TIM_BDTRInitStruct->TIM_BreakPolarity)); - assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(TIM_BDTRInitStruct->TIM_AutomaticOutput)); - /* Set the Lock level, the Break enable Bit and the Ploarity, the OSSR State, - the OSSI State, the dead time value and the Automatic Output Enable Bit */ - TIMx->BDTR = (uint32_t)TIM_BDTRInitStruct->TIM_OSSRState | TIM_BDTRInitStruct->TIM_OSSIState | - TIM_BDTRInitStruct->TIM_LOCKLevel | TIM_BDTRInitStruct->TIM_DeadTime | - TIM_BDTRInitStruct->TIM_Break | TIM_BDTRInitStruct->TIM_BreakPolarity | - TIM_BDTRInitStruct->TIM_AutomaticOutput; -} - -/** - * @brief Fills each TIM_BDTRInitStruct member with its default value. - * @param TIM_BDTRInitStruct: pointer to a TIM_BDTRInitTypeDef structure which - * will be initialized. - * @retval None - */ -void TIM_BDTRStructInit(TIM_BDTRInitTypeDef* TIM_BDTRInitStruct) -{ - /* Set the default configuration */ - TIM_BDTRInitStruct->TIM_OSSRState = TIM_OSSRState_Disable; - TIM_BDTRInitStruct->TIM_OSSIState = TIM_OSSIState_Disable; - TIM_BDTRInitStruct->TIM_LOCKLevel = TIM_LOCKLevel_OFF; - TIM_BDTRInitStruct->TIM_DeadTime = 0x00; - TIM_BDTRInitStruct->TIM_Break = TIM_Break_Disable; - TIM_BDTRInitStruct->TIM_BreakPolarity = TIM_BreakPolarity_Low; - TIM_BDTRInitStruct->TIM_AutomaticOutput = TIM_AutomaticOutput_Disable; -} - -/** - * @brief Enables or disables the TIM peripheral Main Outputs. - * @param TIMx: where x can be 1, 15, 16 or 17 to select the TIMx peripheral. - * @param NewState: new state of the TIM peripheral Main Outputs. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void TIM_CtrlPWMOutputs(TIM_TypeDef* TIMx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST2_PERIPH(TIMx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the TIM Main Output */ - TIMx->BDTR |= TIM_BDTR_MOE; - } - else - { - /* Disable the TIM Main Output */ - TIMx->BDTR &= (uint16_t)(~((uint16_t)TIM_BDTR_MOE)); - } -} - -/** - * @} - */ - -/** - * @brief Initializes the TIMx Channel1 according to the specified - * parameters in the TIM_OCInitStruct. - * @param TIMx: where x can be 1, 2, 3, 14, 15, 16 and 17 to select the TIM peripheral. - * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure - * that contains the configuration information for the specified TIM - * peripheral. - * @retval None - */ -void TIM_OC1Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct) -{ - uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST4_PERIPH(TIMx)); - assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode)); - assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState)); - assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity)); - /* Disable the Channel 1: Reset the CC1E Bit */ - TIMx->CCER &= (uint16_t)(~(uint16_t)TIM_CCER_CC1E); - /* Get the TIMx CCER register value */ - tmpccer = TIMx->CCER; - /* Get the TIMx CR2 register value */ - tmpcr2 = TIMx->CR2; - - /* Get the TIMx CCMR1 register value */ - tmpccmrx = TIMx->CCMR1; - - /* Reset the Output Compare Mode Bits */ - tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR1_OC1M)); - tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR1_CC1S)); - - /* Select the Output Compare Mode */ - tmpccmrx |= TIM_OCInitStruct->TIM_OCMode; - - /* Reset the Output Polarity level */ - tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC1P)); - /* Set the Output Compare Polarity */ - tmpccer |= TIM_OCInitStruct->TIM_OCPolarity; - - /* Set the Output State */ - tmpccer |= TIM_OCInitStruct->TIM_OutputState; - - if((TIMx == TIM1) || (TIMx == TIM15) || (TIMx == TIM16) || (TIMx == TIM17)) - { - assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState)); - assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity)); - assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState)); - assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState)); - - /* Reset the Output N Polarity level */ - tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC1NP)); - /* Set the Output N Polarity */ - tmpccer |= TIM_OCInitStruct->TIM_OCNPolarity; - - /* Reset the Output N State */ - tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC1NE)); - /* Set the Output N State */ - tmpccer |= TIM_OCInitStruct->TIM_OutputNState; - - /* Reset the Ouput Compare and Output Compare N IDLE State */ - tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS1)); - tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS1N)); - - /* Set the Output Idle state */ - tmpcr2 |= TIM_OCInitStruct->TIM_OCIdleState; - /* Set the Output N Idle state */ - tmpcr2 |= TIM_OCInitStruct->TIM_OCNIdleState; - } - /* Write to TIMx CR2 */ - TIMx->CR2 = tmpcr2; - - /* Write to TIMx CCMR1 */ - TIMx->CCMR1 = tmpccmrx; - - /* Set the Capture Compare Register value */ - TIMx->CCR1 = TIM_OCInitStruct->TIM_Pulse; - - /* Write to TIMx CCER */ - TIMx->CCER = tmpccer; -} - -/** - * @brief Initializes the TIMx Channel2 according to the specified - * parameters in the TIM_OCInitStruct. - * @param TIMx: where x can be 1, 2, 3 or 15 to select the TIM peripheral. - * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure - * that contains the configuration information for the specified TIM - * peripheral. - * @retval None - */ -void TIM_OC2Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct) -{ - uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST6_PERIPH(TIMx)); - assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode)); - assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState)); - assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity)); - /* Disable the Channel 2: Reset the CC2E Bit */ - TIMx->CCER &= (uint16_t)(~((uint16_t)TIM_CCER_CC2E)); - - /* Get the TIMx CCER register value */ - tmpccer = TIMx->CCER; - /* Get the TIMx CR2 register value */ - tmpcr2 = TIMx->CR2; - - /* Get the TIMx CCMR1 register value */ - tmpccmrx = TIMx->CCMR1; - - /* Reset the Output Compare mode and Capture/Compare selection Bits */ - tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR1_OC2M)); - tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR1_CC2S)); - - /* Select the Output Compare Mode */ - tmpccmrx |= (uint16_t)(TIM_OCInitStruct->TIM_OCMode << 8); - - /* Reset the Output Polarity level */ - tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC2P)); - /* Set the Output Compare Polarity */ - tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 4); - - /* Set the Output State */ - tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 4); - - if((TIMx == TIM1) || (TIMx == TIM15)) - { - /* Check the parameters */ - assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState)); - - /* Reset the Ouput Compare State */ - tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS2)); - - /* Set the Output Idle state */ - tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 2); - - if (TIMx == TIM1) - { - /* Check the parameters */ - assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState)); - assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity)); - assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState)); - - /* Reset the Output N Polarity level */ - tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC2NP)); - /* Set the Output N Polarity */ - tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCNPolarity << 4); - - /* Reset the Output N State */ - tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC2NE)); - /* Set the Output N State */ - tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputNState << 4); - - /* Reset the Output Compare N IDLE State */ - tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS2N)); - - /* Set the Output N Idle state */ - tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCNIdleState << 2); - } - } - /* Write to TIMx CR2 */ - TIMx->CR2 = tmpcr2; - - /* Write to TIMx CCMR1 */ - TIMx->CCMR1 = tmpccmrx; - - /* Set the Capture Compare Register value */ - TIMx->CCR2 = TIM_OCInitStruct->TIM_Pulse; - - /* Write to TIMx CCER */ - TIMx->CCER = tmpccer; -} - -/** - * @brief Initializes the TIMx Channel3 according to the specified - * parameters in the TIM_OCInitStruct. - * @param TIMx: where x can be 1, 2 or 3 to select the TIM peripheral. - * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure - * that contains the configuration information for the specified TIM - * peripheral. - * @retval None - */ -void TIM_OC3Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct) -{ - uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode)); - assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState)); - assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity)); - /* Disable the Channel 2: Reset the CC2E Bit */ - TIMx->CCER &= (uint16_t)(~((uint16_t)TIM_CCER_CC3E)); - - /* Get the TIMx CCER register value */ - tmpccer = TIMx->CCER; - /* Get the TIMx CR2 register value */ - tmpcr2 = TIMx->CR2; - - /* Get the TIMx CCMR2 register value */ - tmpccmrx = TIMx->CCMR2; - - /* Reset the Output Compare mode and Capture/Compare selection Bits */ - tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR2_OC3M)); - tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR2_CC3S)); - /* Select the Output Compare Mode */ - tmpccmrx |= TIM_OCInitStruct->TIM_OCMode; - - /* Reset the Output Polarity level */ - tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC3P)); - /* Set the Output Compare Polarity */ - tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 8); - - /* Set the Output State */ - tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 8); - - if(TIMx == TIM1) - { - assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState)); - assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity)); - assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState)); - assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState)); - - /* Reset the Output N Polarity level */ - tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC3NP)); - /* Set the Output N Polarity */ - tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCNPolarity << 8); - /* Reset the Output N State */ - tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC3NE)); - - /* Set the Output N State */ - tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputNState << 8); - /* Reset the Ouput Compare and Output Compare N IDLE State */ - tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS3)); - tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS3N)); - /* Set the Output Idle state */ - tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 4); - /* Set the Output N Idle state */ - tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCNIdleState << 4); - } - /* Write to TIMx CR2 */ - TIMx->CR2 = tmpcr2; - - /* Write to TIMx CCMR2 */ - TIMx->CCMR2 = tmpccmrx; - - /* Set the Capture Compare Register value */ - TIMx->CCR3 = TIM_OCInitStruct->TIM_Pulse; - - /* Write to TIMx CCER */ - TIMx->CCER = tmpccer; -} - -/** - * @brief Initializes the TIMx Channel4 according to the specified - * parameters in the TIM_OCInitStruct. - * @param TIMx: where x can be 1, 2 or 3 to select the TIM peripheral. - * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure - * that contains the configuration information for the specified TIM - * peripheral. - * @retval None - */ -void TIM_OC4Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct) -{ - uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode)); - assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState)); - assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity)); - /* Disable the Channel 2: Reset the CC4E Bit */ - TIMx->CCER &= (uint16_t)(~((uint16_t)TIM_CCER_CC4E)); - - /* Get the TIMx CCER register value */ - tmpccer = TIMx->CCER; - /* Get the TIMx CR2 register value */ - tmpcr2 = TIMx->CR2; - - /* Get the TIMx CCMR2 register value */ - tmpccmrx = TIMx->CCMR2; - - /* Reset the Output Compare mode and Capture/Compare selection Bits */ - tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR2_OC4M)); - tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR2_CC4S)); - - /* Select the Output Compare Mode */ - tmpccmrx |= (uint16_t)(TIM_OCInitStruct->TIM_OCMode << 8); - - /* Reset the Output Polarity level */ - tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC4P)); - /* Set the Output Compare Polarity */ - tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 12); - - /* Set the Output State */ - tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 12); - - if(TIMx == TIM1) - { - assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState)); - /* Reset the Ouput Compare IDLE State */ - tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS4)); - /* Set the Output Idle state */ - tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 6); - } - /* Write to TIMx CR2 */ - TIMx->CR2 = tmpcr2; - - /* Write to TIMx CCMR2 */ - TIMx->CCMR2 = tmpccmrx; - - /* Set the Capture Compare Register value */ - TIMx->CCR4 = TIM_OCInitStruct->TIM_Pulse; - - /* Write to TIMx CCER */ - TIMx->CCER = tmpccer; -} - -/** - * @brief Fills each TIM_OCInitStruct member with its default value. - * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure which will - * be initialized. - * @retval None - */ -void TIM_OCStructInit(TIM_OCInitTypeDef* TIM_OCInitStruct) -{ - /* Set the default configuration */ - TIM_OCInitStruct->TIM_OCMode = TIM_OCMode_Timing; - TIM_OCInitStruct->TIM_OutputState = TIM_OutputState_Disable; - TIM_OCInitStruct->TIM_OutputNState = TIM_OutputNState_Disable; - TIM_OCInitStruct->TIM_Pulse = 0x0000000; - TIM_OCInitStruct->TIM_OCPolarity = TIM_OCPolarity_High; - TIM_OCInitStruct->TIM_OCNPolarity = TIM_OCPolarity_High; - TIM_OCInitStruct->TIM_OCIdleState = TIM_OCIdleState_Reset; - TIM_OCInitStruct->TIM_OCNIdleState = TIM_OCNIdleState_Reset; -} - -/** - * @brief Selects the TIM Output Compare Mode. - * @note This function disables the selected channel before changing the Output - * Compare Mode. - * User has to enable this channel using TIM_CCxCmd and TIM_CCxNCmd functions. - * @param TIMx: where x can be 1, 2, 3, 14, 15, 16 or 17 to select the TIM peripheral. - * @param TIM_Channel: specifies the TIM Channel - * This parameter can be one of the following values: - * @arg TIM_Channel_1: TIM Channel 1 - * @arg TIM_Channel_2: TIM Channel 2 - * @arg TIM_Channel_3: TIM Channel 3 - * @arg TIM_Channel_4: TIM Channel 4 - * @param TIM_OCMode: specifies the TIM Output Compare Mode. - * This parameter can be one of the following values: - * @arg TIM_OCMode_Timing - * @arg TIM_OCMode_Active - * @arg TIM_OCMode_Toggle - * @arg TIM_OCMode_PWM1 - * @arg TIM_OCMode_PWM2 - * @arg TIM_ForcedAction_Active - * @arg TIM_ForcedAction_InActive - * @retval None - */ -void TIM_SelectOCxM(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode) -{ - uint32_t tmp = 0; - uint16_t tmp1 = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST4_PERIPH(TIMx)); - assert_param(IS_TIM_OCM(TIM_OCMode)); - - tmp = (uint32_t) TIMx; - tmp += CCMR_OFFSET; - - tmp1 = CCER_CCE_SET << (uint16_t)TIM_Channel; - - /* Disable the Channel: Reset the CCxE Bit */ - TIMx->CCER &= (uint16_t) ~tmp1; - - if((TIM_Channel == TIM_Channel_1) ||(TIM_Channel == TIM_Channel_3)) - { - tmp += (TIM_Channel>>1); - - /* Reset the OCxM bits in the CCMRx register */ - *(__IO uint32_t *) tmp &= (uint32_t)~((uint32_t)TIM_CCMR1_OC1M); - - /* Configure the OCxM bits in the CCMRx register */ - *(__IO uint32_t *) tmp |= TIM_OCMode; - } - else - { - tmp += (uint16_t)(TIM_Channel - (uint16_t)4)>> (uint16_t)1; - - /* Reset the OCxM bits in the CCMRx register */ - *(__IO uint32_t *) tmp &= (uint32_t)~((uint32_t)TIM_CCMR1_OC2M); - - /* Configure the OCxM bits in the CCMRx register */ - *(__IO uint32_t *) tmp |= (uint16_t)(TIM_OCMode << 8); - } -} - -/** - * @brief Sets the TIMx Capture Compare1 Register value - * @param TIMx: where x can be 1, 2, 3, 14, 15, 16 or 17 to select the TIM peripheral. - * @param Compare1: specifies the Capture Compare1 register new value. - * @retval None - */ -void TIM_SetCompare1(TIM_TypeDef* TIMx, uint32_t Compare1) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST4_PERIPH(TIMx)); - - /* Set the Capture Compare1 Register value */ - TIMx->CCR1 = Compare1; -} - -/** - * @brief Sets the TIMx Capture Compare2 Register value - * @param TIMx: where x can be 1, 2, 3 or 15 to select the TIM peripheral. - * @param Compare2: specifies the Capture Compare2 register new value. - * @retval None - */ -void TIM_SetCompare2(TIM_TypeDef* TIMx, uint32_t Compare2) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST6_PERIPH(TIMx)); - - /* Set the Capture Compare2 Register value */ - TIMx->CCR2 = Compare2; -} - -/** - * @brief Sets the TIMx Capture Compare3 Register value - * @param TIMx: where x can be 1, 2 or 3 to select the TIM peripheral. - * @param Compare3: specifies the Capture Compare3 register new value. - * @retval None - */ -void TIM_SetCompare3(TIM_TypeDef* TIMx, uint32_t Compare3) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - - /* Set the Capture Compare3 Register value */ - TIMx->CCR3 = Compare3; -} - -/** - * @brief Sets the TIMx Capture Compare4 Register value - * @param TIMx: where x can be 1, 2 or 3 to select the TIM peripheral. - * @param Compare4: specifies the Capture Compare4 register new value. - * @retval None - */ -void TIM_SetCompare4(TIM_TypeDef* TIMx, uint32_t Compare4) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - - /* Set the Capture Compare4 Register value */ - TIMx->CCR4 = Compare4; -} - -/** - * @brief Forces the TIMx output 1 waveform to active or inactive level. - * @param TIMx: where x can be 1, 2, 3, 14, 15, 16 or 17 to select the TIM peripheral. - * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform. - * This parameter can be one of the following values: - * @arg TIM_ForcedAction_Active: Force active level on OC1REF - * @arg TIM_ForcedAction_InActive: Force inactive level on OC1REF. - * @retval None - */ -void TIM_ForcedOC1Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction) -{ - uint16_t tmpccmr1 = 0; - /* Check the parameters */ - assert_param(IS_TIM_LIST4_PERIPH(TIMx)); - assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction)); - tmpccmr1 = TIMx->CCMR1; - /* Reset the OC1M Bits */ - tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC1M); - /* Configure The Forced output Mode */ - tmpccmr1 |= TIM_ForcedAction; - /* Write to TIMx CCMR1 register */ - TIMx->CCMR1 = tmpccmr1; -} - -/** - * @brief Forces the TIMx output 2 waveform to active or inactive level. - * @param TIMx: where x can be 1, 2, 3, or 15 to select the TIM peripheral. - * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform. - * This parameter can be one of the following values: - * @arg TIM_ForcedAction_Active: Force active level on OC2REF - * @arg TIM_ForcedAction_InActive: Force inactive level on OC2REF. - * @retval None - */ -void TIM_ForcedOC2Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction) -{ - uint16_t tmpccmr1 = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST6_PERIPH(TIMx)); - assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction)); - - tmpccmr1 = TIMx->CCMR1; - /* Reset the OC2M Bits */ - tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC2M); - /* Configure The Forced output Mode */ - tmpccmr1 |= (uint16_t)(TIM_ForcedAction << 8); - /* Write to TIMx CCMR1 register */ - TIMx->CCMR1 = tmpccmr1; -} - -/** - * @brief Forces the TIMx output 3 waveform to active or inactive level. - * @param TIMx: where x can be 1, 2 or 3 to select the TIM peripheral. - * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform. - * This parameter can be one of the following values: - * @arg TIM_ForcedAction_Active: Force active level on OC3REF - * @arg TIM_ForcedAction_InActive: Force inactive level on OC3REF. - * @retval None - */ -void TIM_ForcedOC3Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction) -{ - uint16_t tmpccmr2 = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction)); - - tmpccmr2 = TIMx->CCMR2; - /* Reset the OC1M Bits */ - tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC3M); - /* Configure The Forced output Mode */ - tmpccmr2 |= TIM_ForcedAction; - /* Write to TIMx CCMR2 register */ - TIMx->CCMR2 = tmpccmr2; -} - -/** - * @brief Forces the TIMx output 4 waveform to active or inactive level. - * @param TIMx: where x can be 1, 2 or 3 to select the TIM peripheral. - * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform. - * This parameter can be one of the following values: - * @arg TIM_ForcedAction_Active: Force active level on OC4REF - * @arg TIM_ForcedAction_InActive: Force inactive level on OC4REF. - * @retval None - */ -void TIM_ForcedOC4Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction) -{ - uint16_t tmpccmr2 = 0; - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction)); - - tmpccmr2 = TIMx->CCMR2; - /* Reset the OC2M Bits */ - tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC4M); - /* Configure The Forced output Mode */ - tmpccmr2 |= (uint16_t)(TIM_ForcedAction << 8); - /* Write to TIMx CCMR2 register */ - TIMx->CCMR2 = tmpccmr2; -} - -/** - * @brief Sets or Resets the TIM peripheral Capture Compare Preload Control bit. - * @param TIMx: where x can be 1, 2, 3 or 15 to select the TIMx peripheral - * @param NewState: new state of the Capture Compare Preload Control bit - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void TIM_CCPreloadControl(TIM_TypeDef* TIMx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST6_PERIPH(TIMx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Set the CCPC Bit */ - TIMx->CR2 |= TIM_CR2_CCPC; - } - else - { - /* Reset the CCPC Bit */ - TIMx->CR2 &= (uint16_t)~((uint16_t)TIM_CR2_CCPC); - } -} - - -/** - * @brief Enables or disables the TIMx peripheral Preload register on CCR1. - * @param TIMx: where x can be 1, 2, 3, 14, 15, 16 and 17 to select the TIM peripheral. - * @param TIM_OCPreload: new state of the TIMx peripheral Preload register - * This parameter can be one of the following values: - * @arg TIM_OCPreload_Enable - * @arg TIM_OCPreload_Disable - * @retval None - */ -void TIM_OC1PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload) -{ - uint16_t tmpccmr1 = 0; - /* Check the parameters */ - assert_param(IS_TIM_LIST4_PERIPH(TIMx)); - assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload)); - - tmpccmr1 = TIMx->CCMR1; - /* Reset the OC1PE Bit */ - tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC1PE); - /* Enable or Disable the Output Compare Preload feature */ - tmpccmr1 |= TIM_OCPreload; - /* Write to TIMx CCMR1 register */ - TIMx->CCMR1 = tmpccmr1; -} - -/** - * @brief Enables or disables the TIMx peripheral Preload register on CCR2. - * @param TIMx: where x can be 1, 2, 3 and 15 to select the TIM peripheral. - * @param TIM_OCPreload: new state of the TIMx peripheral Preload register - * This parameter can be one of the following values: - * @arg TIM_OCPreload_Enable - * @arg TIM_OCPreload_Disable - * @retval None - */ -void TIM_OC2PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload) -{ - uint16_t tmpccmr1 = 0; - /* Check the parameters */ - assert_param(IS_TIM_LIST6_PERIPH(TIMx)); - assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload)); - - tmpccmr1 = TIMx->CCMR1; - /* Reset the OC2PE Bit */ - tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC2PE); - /* Enable or Disable the Output Compare Preload feature */ - tmpccmr1 |= (uint16_t)(TIM_OCPreload << 8); - /* Write to TIMx CCMR1 register */ - TIMx->CCMR1 = tmpccmr1; -} - -/** - * @brief Enables or disables the TIMx peripheral Preload register on CCR3. - * @param TIMx: where x can be 1, 2 or 3 to select the TIM peripheral. - * @param TIM_OCPreload: new state of the TIMx peripheral Preload register - * This parameter can be one of the following values: - * @arg TIM_OCPreload_Enable - * @arg TIM_OCPreload_Disable - * @retval None - */ -void TIM_OC3PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload) -{ - uint16_t tmpccmr2 = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload)); - - tmpccmr2 = TIMx->CCMR2; - /* Reset the OC3PE Bit */ - tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC3PE); - /* Enable or Disable the Output Compare Preload feature */ - tmpccmr2 |= TIM_OCPreload; - /* Write to TIMx CCMR2 register */ - TIMx->CCMR2 = tmpccmr2; -} - -/** - * @brief Enables or disables the TIMx peripheral Preload register on CCR4. - * @param TIMx: where x can be 1, 2 or 3 to select the TIM peripheral. - * @param TIM_OCPreload: new state of the TIMx peripheral Preload register - * This parameter can be one of the following values: - * @arg TIM_OCPreload_Enable - * @arg TIM_OCPreload_Disable - * @retval None - */ -void TIM_OC4PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload) -{ - uint16_t tmpccmr2 = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload)); - - tmpccmr2 = TIMx->CCMR2; - /* Reset the OC4PE Bit */ - tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC4PE); - /* Enable or Disable the Output Compare Preload feature */ - tmpccmr2 |= (uint16_t)(TIM_OCPreload << 8); - /* Write to TIMx CCMR2 register */ - TIMx->CCMR2 = tmpccmr2; -} - -/** - * @brief Configures the TIMx Output Compare 1 Fast feature. - * @param TIMx: where x can be 1, 2, 3, 14, 15, 16 or 17 to select the TIM peripheral. - * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit. - * This parameter can be one of the following values: - * @arg TIM_OCFast_Enable: TIM output compare fast enable - * @arg TIM_OCFast_Disable: TIM output compare fast disable - * @retval None - */ -void TIM_OC1FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast) -{ - uint16_t tmpccmr1 = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST4_PERIPH(TIMx)); - assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast)); - - /* Get the TIMx CCMR1 register value */ - tmpccmr1 = TIMx->CCMR1; - /* Reset the OC1FE Bit */ - tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC1FE); - /* Enable or Disable the Output Compare Fast Bit */ - tmpccmr1 |= TIM_OCFast; - /* Write to TIMx CCMR1 */ - TIMx->CCMR1 = tmpccmr1; -} - -/** - * @brief Configures the TIMx Output Compare 2 Fast feature. - * @param TIMx: where x can be 1, 2, 3 or 15 to select the TIM peripheral. - * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit. - * This parameter can be one of the following values: - * @arg TIM_OCFast_Enable: TIM output compare fast enable - * @arg TIM_OCFast_Disable: TIM output compare fast disable - * @retval None - */ -void TIM_OC2FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast) -{ - uint16_t tmpccmr1 = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST6_PERIPH(TIMx)); - assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast)); - - /* Get the TIMx CCMR1 register value */ - tmpccmr1 = TIMx->CCMR1; - /* Reset the OC2FE Bit */ - tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC2FE); - /* Enable or Disable the Output Compare Fast Bit */ - tmpccmr1 |= (uint16_t)(TIM_OCFast << 8); - /* Write to TIMx CCMR1 */ - TIMx->CCMR1 = tmpccmr1; -} - -/** - * @brief Configures the TIMx Output Compare 3 Fast feature. - * @param TIMx: where x can be 1, 2 or 3 to select the TIM peripheral. - * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit. - * This parameter can be one of the following values: - * @arg TIM_OCFast_Enable: TIM output compare fast enable - * @arg TIM_OCFast_Disable: TIM output compare fast disable - * @retval None - */ -void TIM_OC3FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast) -{ - uint16_t tmpccmr2 = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast)); - - /* Get the TIMx CCMR2 register value */ - tmpccmr2 = TIMx->CCMR2; - /* Reset the OC3FE Bit */ - tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC3FE); - /* Enable or Disable the Output Compare Fast Bit */ - tmpccmr2 |= TIM_OCFast; - /* Write to TIMx CCMR2 */ - TIMx->CCMR2 = tmpccmr2; -} - -/** - * @brief Configures the TIMx Output Compare 4 Fast feature. - * @param TIMx: where x can be 1, 2 or 3 to select the TIM peripheral. - * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit. - * This parameter can be one of the following values: - * @arg TIM_OCFast_Enable: TIM output compare fast enable - * @arg TIM_OCFast_Disable: TIM output compare fast disable - * @retval None - */ -void TIM_OC4FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast) -{ - uint16_t tmpccmr2 = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast)); - - /* Get the TIMx CCMR2 register value */ - tmpccmr2 = TIMx->CCMR2; - /* Reset the OC4FE Bit */ - tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC4FE); - /* Enable or Disable the Output Compare Fast Bit */ - tmpccmr2 |= (uint16_t)(TIM_OCFast << 8); - /* Write to TIMx CCMR2 */ - TIMx->CCMR2 = tmpccmr2; -} - -/** - * @brief Clears or safeguards the OCREF1 signal on an external event - * @param TIMx: where x can be 1, 2, 3, 14, 15, 16 or 17 to select the TIM peripheral. - * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit. - * This parameter can be one of the following values: - * @arg TIM_OCClear_Enable: TIM Output clear enable - * @arg TIM_OCClear_Disable: TIM Output clear disable - * @retval None - */ -void TIM_ClearOC1Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear) -{ - uint16_t tmpccmr1 = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST4_PERIPH(TIMx)); - assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear)); - - tmpccmr1 = TIMx->CCMR1; - /* Reset the OC1CE Bit */ - tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC1CE); - /* Enable or Disable the Output Compare Clear Bit */ - tmpccmr1 |= TIM_OCClear; - /* Write to TIMx CCMR1 register */ - TIMx->CCMR1 = tmpccmr1; -} - -/** - * @brief Clears or safeguards the OCREF2 signal on an external event - * @param TIMx: where x can be 1, 2, 3 or 15 to select the TIM peripheral. - * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit. - * This parameter can be one of the following values: - * @arg TIM_OCClear_Enable: TIM Output clear enable - * @arg TIM_OCClear_Disable: TIM Output clear disable - * @retval None - */ -void TIM_ClearOC2Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear) -{ - uint16_t tmpccmr1 = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST6_PERIPH(TIMx)); - assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear)); - - tmpccmr1 = TIMx->CCMR1; - /* Reset the OC2CE Bit */ - tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC2CE); - /* Enable or Disable the Output Compare Clear Bit */ - tmpccmr1 |= (uint16_t)(TIM_OCClear << 8); - /* Write to TIMx CCMR1 register */ - TIMx->CCMR1 = tmpccmr1; -} - -/** - * @brief Clears or safeguards the OCREF3 signal on an external event - * @param TIMx: where x can be 1, 2 or 3 to select the TIM peripheral. - * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit. - * This parameter can be one of the following values: - * @arg TIM_OCClear_Enable: TIM Output clear enable - * @arg TIM_OCClear_Disable: TIM Output clear disable - * @retval None - */ -void TIM_ClearOC3Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear) -{ - uint16_t tmpccmr2 = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear)); - - tmpccmr2 = TIMx->CCMR2; - /* Reset the OC3CE Bit */ - tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC3CE); - /* Enable or Disable the Output Compare Clear Bit */ - tmpccmr2 |= TIM_OCClear; - /* Write to TIMx CCMR2 register */ - TIMx->CCMR2 = tmpccmr2; -} - -/** - * @brief Clears or safeguards the OCREF4 signal on an external event - * @param TIMx: where x can be 1, 2 or 3 to select the TIM peripheral. - * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit. - * This parameter can be one of the following values: - * @arg TIM_OCClear_Enable: TIM Output clear enable - * @arg TIM_OCClear_Disable: TIM Output clear disable - * @retval None - */ -void TIM_ClearOC4Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear) -{ - uint16_t tmpccmr2 = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear)); - - tmpccmr2 = TIMx->CCMR2; - /* Reset the OC4CE Bit */ - tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC4CE); - /* Enable or Disable the Output Compare Clear Bit */ - tmpccmr2 |= (uint16_t)(TIM_OCClear << 8); - /* Write to TIMx CCMR2 register */ - TIMx->CCMR2 = tmpccmr2; -} - -/** - * @brief Configures the TIMx channel 1 polarity. - * @param TIMx: where x can be 1, 2, 3, 14, 15, 16 or 17 to select the TIM peripheral. - * @param TIM_OCPolarity: specifies the OC1 Polarity - * This parmeter can be one of the following values: - * @arg TIM_OCPolarity_High: Output Compare active high - * @arg TIM_OCPolarity_Low: Output Compare active low - * @retval None - */ -void TIM_OC1PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity) -{ - uint16_t tmpccer = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST4_PERIPH(TIMx)); - assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity)); - - tmpccer = TIMx->CCER; - /* Set or Reset the CC1P Bit */ - tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC1P); - tmpccer |= TIM_OCPolarity; - /* Write to TIMx CCER register */ - TIMx->CCER = tmpccer; -} - -/** - * @brief Configures the TIMx Channel 1N polarity. - * @param TIMx: where x can be 1, 15, 16 or 17 to select the TIM peripheral. - * @param TIM_OCNPolarity: specifies the OC1N Polarity - * This parmeter can be one of the following values: - * @arg TIM_OCNPolarity_High: Output Compare active high - * @arg TIM_OCNPolarity_Low: Output Compare active low - * @retval None - */ -void TIM_OC1NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity) -{ - uint16_t tmpccer = 0; - /* Check the parameters */ - assert_param(IS_TIM_LIST2_PERIPH(TIMx)); - assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity)); - - tmpccer = TIMx->CCER; - /* Set or Reset the CC1NP Bit */ - tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC1NP); - tmpccer |= TIM_OCNPolarity; - /* Write to TIMx CCER register */ - TIMx->CCER = tmpccer; -} - -/** - * @brief Configures the TIMx channel 2 polarity. - * @param TIMx: where x can be 1, 2, 3, or 15 to select the TIM peripheral. - * @param TIM_OCPolarity: specifies the OC2 Polarity - * This parmeter can be one of the following values: - * @arg TIM_OCPolarity_High: Output Compare active high - * @arg TIM_OCPolarity_Low: Output Compare active low - * @retval None - */ -void TIM_OC2PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity) -{ - uint16_t tmpccer = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST6_PERIPH(TIMx)); - assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity)); - - tmpccer = TIMx->CCER; - /* Set or Reset the CC2P Bit */ - tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC2P); - tmpccer |= (uint16_t)(TIM_OCPolarity << 4); - /* Write to TIMx CCER register */ - TIMx->CCER = tmpccer; -} - -/** - * @brief Configures the TIMx Channel 2N polarity. - * @param TIMx: where x can be 1 to select the TIM peripheral. - * @param TIM_OCNPolarity: specifies the OC2N Polarity - * This parmeter can be one of the following values: - * @arg TIM_OCNPolarity_High: Output Compare active high - * @arg TIM_OCNPolarity_Low: Output Compare active low - * @retval None - */ -void TIM_OC2NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity) -{ - uint16_t tmpccer = 0; - /* Check the parameters */ - assert_param(IS_TIM_LIST1_PERIPH(TIMx)); - assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity)); - - tmpccer = TIMx->CCER; - /* Set or Reset the CC2NP Bit */ - tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC2NP); - tmpccer |= (uint16_t)(TIM_OCNPolarity << 4); - /* Write to TIMx CCER register */ - TIMx->CCER = tmpccer; -} - -/** - * @brief Configures the TIMx channel 3 polarity. - * @param TIMx: where x can be 1, 2 or 3 to select the TIM peripheral. - * @param TIM_OCPolarity: specifies the OC3 Polarity - * This parmeter can be one of the following values: - * @arg TIM_OCPolarity_High: Output Compare active high - * @arg TIM_OCPolarity_Low: Output Compare active low - * @retval None - */ -void TIM_OC3PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity) -{ - uint16_t tmpccer = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity)); - - tmpccer = TIMx->CCER; - /* Set or Reset the CC3P Bit */ - tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC3P); - tmpccer |= (uint16_t)(TIM_OCPolarity << 8); - /* Write to TIMx CCER register */ - TIMx->CCER = tmpccer; -} - -/** - * @brief Configures the TIMx Channel 3N polarity. - * @param TIMx: where x can be 1 to select the TIM peripheral. - * @param TIM_OCNPolarity: specifies the OC3N Polarity - * This parmeter can be one of the following values: - * @arg TIM_OCNPolarity_High: Output Compare active high - * @arg TIM_OCNPolarity_Low: Output Compare active low - * @retval None - */ -void TIM_OC3NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity) -{ - uint16_t tmpccer = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST1_PERIPH(TIMx)); - assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity)); - - tmpccer = TIMx->CCER; - /* Set or Reset the CC3NP Bit */ - tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC3NP); - tmpccer |= (uint16_t)(TIM_OCNPolarity << 8); - /* Write to TIMx CCER register */ - TIMx->CCER = tmpccer; -} - -/** - * @brief Configures the TIMx channel 4 polarity. - * @param TIMx: where x can be 1, 2 or 3 to select the TIM peripheral. - * @param TIM_OCPolarity: specifies the OC4 Polarity - * This parmeter can be one of the following values: - * @arg TIM_OCPolarity_High: Output Compare active high - * @arg TIM_OCPolarity_Low: Output Compare active low - * @retval None - */ -void TIM_OC4PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity) -{ - uint16_t tmpccer = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity)); - - tmpccer = TIMx->CCER; - /* Set or Reset the CC4P Bit */ - tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC4P); - tmpccer |= (uint16_t)(TIM_OCPolarity << 12); - /* Write to TIMx CCER register */ - TIMx->CCER = tmpccer; -} - -/** - * @brief Selects the OCReference Clear source. - * @param TIMx: where x can be 1, 2 or 3 to select the TIM peripheral. - * @param TIM_OCReferenceClear: specifies the OCReference Clear source. - * This parameter can be one of the following values: - * @arg TIM_OCReferenceClear_ETRF: The internal OCreference clear input is connected to ETRF. - * @arg TIM_OCReferenceClear_OCREFCLR: The internal OCreference clear input is connected to OCREF_CLR input. - * @retval None - */ -void TIM_SelectOCREFClear(TIM_TypeDef* TIMx, uint16_t TIM_OCReferenceClear) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(TIM_OCREFERENCECECLEAR_SOURCE(TIM_OCReferenceClear)); - - /* Set the TIM_OCReferenceClear source */ - TIMx->SMCR &= (uint16_t)~((uint16_t)TIM_SMCR_OCCS); - TIMx->SMCR |= TIM_OCReferenceClear; -} - -/** - * @brief Enables or disables the TIM Capture Compare Channel x. - * @param TIMx: where x can be 1, 2, 3, 14, 15, 16 or 17 to select the TIM peripheral. - * @param TIM_Channel: specifies the TIM Channel - * This parameter can be one of the following values: - * @arg TIM_Channel_1: TIM Channel 1 - * @arg TIM_Channel_2: TIM Channel 2 - * @arg TIM_Channel_3: TIM Channel 3 - * @arg TIM_Channel_4: TIM Channel 4 - * @param TIM_CCx: specifies the TIM Channel CCxE bit new state. - * This parameter can be: TIM_CCx_Enable or TIM_CCx_Disable. - * @retval None - */ -void TIM_CCxCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx) -{ - uint16_t tmp = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST4_PERIPH(TIMx)); - assert_param(IS_TIM_CCX(TIM_CCx)); - - tmp = CCER_CCE_SET << TIM_Channel; - - /* Reset the CCxE Bit */ - TIMx->CCER &= (uint16_t)~ tmp; - - /* Set or reset the CCxE Bit */ - TIMx->CCER |= (uint16_t)(TIM_CCx << TIM_Channel); -} - -/** - * @brief Enables or disables the TIM Capture Compare Channel xN. - * @param TIMx: where x can be 1, 15, 16 or 17 to select the TIM peripheral. - * @param TIM_Channel: specifies the TIM Channel - * This parmeter can be one of the following values: - * @arg TIM_Channel_1: TIM Channel 1 - * @arg TIM_Channel_2: TIM Channel 2 - * @arg TIM_Channel_3: TIM Channel 3 - * @param TIM_CCxN: specifies the TIM Channel CCxNE bit new state. - * This parameter can be: TIM_CCxN_Enable or TIM_CCxN_Disable. - * @retval None - */ -void TIM_CCxNCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN) -{ - uint16_t tmp = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST2_PERIPH(TIMx)); - assert_param(IS_TIM_COMPLEMENTARY_CHANNEL(TIM_Channel)); - assert_param(IS_TIM_CCXN(TIM_CCxN)); - - tmp = CCER_CCNE_SET << TIM_Channel; - - /* Reset the CCxNE Bit */ - TIMx->CCER &= (uint16_t) ~tmp; - - /* Set or reset the CCxNE Bit */ - TIMx->CCER |= (uint16_t)(TIM_CCxN << TIM_Channel); -} - -/** - * @brief Selects the TIM peripheral Commutation event. - * @param TIMx: where x can be 1, 15, 16 or 17 to select the TIMx peripheral - * @param NewState: new state of the Commutation event. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void TIM_SelectCOM(TIM_TypeDef* TIMx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST2_PERIPH(TIMx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Set the COM Bit */ - TIMx->CR2 |= TIM_CR2_CCUS; - } - else - { - /* Reset the COM Bit */ - TIMx->CR2 &= (uint16_t)~((uint16_t)TIM_CR2_CCUS); - } -} - -/** - * @} - */ -/** - * @brief Initializes the TIM peripheral according to the specified - * parameters in the TIM_ICInitStruct. - * @param TIMx: where x can be 1, 2, 3, 14, 15, 16 or 17 to select the TIM peripheral. - * @param TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure - * that contains the configuration information for the specified TIM - * peripheral. - * @retval None - */ -void TIM_ICInit(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST4_PERIPH(TIMx)); - assert_param(IS_TIM_CHANNEL(TIM_ICInitStruct->TIM_Channel)); - assert_param(IS_TIM_IC_SELECTION(TIM_ICInitStruct->TIM_ICSelection)); - assert_param(IS_TIM_IC_PRESCALER(TIM_ICInitStruct->TIM_ICPrescaler)); - assert_param(IS_TIM_IC_FILTER(TIM_ICInitStruct->TIM_ICFilter)); - assert_param(IS_TIM_IC_POLARITY(TIM_ICInitStruct->TIM_ICPolarity)); - - if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_1) - { - assert_param(IS_TIM_LIST4_PERIPH(TIMx)); - /* TI1 Configuration */ - TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, - TIM_ICInitStruct->TIM_ICSelection, - TIM_ICInitStruct->TIM_ICFilter); - /* Set the Input Capture Prescaler value */ - TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); - } - else if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_2) - { - assert_param(IS_TIM_LIST6_PERIPH(TIMx)); - /* TI2 Configuration */ - TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, - TIM_ICInitStruct->TIM_ICSelection, - TIM_ICInitStruct->TIM_ICFilter); - /* Set the Input Capture Prescaler value */ - TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); - } - else if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_3) - { - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - /* TI3 Configuration */ - TI3_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, - TIM_ICInitStruct->TIM_ICSelection, - TIM_ICInitStruct->TIM_ICFilter); - /* Set the Input Capture Prescaler value */ - TIM_SetIC3Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); - } - else - { - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - /* TI4 Configuration */ - TI4_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, - TIM_ICInitStruct->TIM_ICSelection, - TIM_ICInitStruct->TIM_ICFilter); - /* Set the Input Capture Prescaler value */ - TIM_SetIC4Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); - } -} - -/** - * @brief Fills each TIM_ICInitStruct member with its default value. - * @param TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure which will - * be initialized. - * @retval None - */ -void TIM_ICStructInit(TIM_ICInitTypeDef* TIM_ICInitStruct) -{ - /* Set the default configuration */ - TIM_ICInitStruct->TIM_Channel = TIM_Channel_1; - TIM_ICInitStruct->TIM_ICPolarity = TIM_ICPolarity_Rising; - TIM_ICInitStruct->TIM_ICSelection = TIM_ICSelection_DirectTI; - TIM_ICInitStruct->TIM_ICPrescaler = TIM_ICPSC_DIV1; - TIM_ICInitStruct->TIM_ICFilter = 0x00; -} - -/** - * @brief Configures the TIM peripheral according to the specified - * parameters in the TIM_ICInitStruct to measure an external PWM signal. - * @param TIMx: where x can be 1, 2, 3 or 15 to select the TIM peripheral. - * @param TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure - * that contains the configuration information for the specified TIM - * peripheral. - * @retval None - */ -void TIM_PWMIConfig(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct) -{ - uint16_t icoppositepolarity = TIM_ICPolarity_Rising; - uint16_t icoppositeselection = TIM_ICSelection_DirectTI; - /* Check the parameters */ - assert_param(IS_TIM_LIST6_PERIPH(TIMx)); - /* Select the Opposite Input Polarity */ - if (TIM_ICInitStruct->TIM_ICPolarity == TIM_ICPolarity_Rising) - { - icoppositepolarity = TIM_ICPolarity_Falling; - } - else - { - icoppositepolarity = TIM_ICPolarity_Rising; - } - /* Select the Opposite Input */ - if (TIM_ICInitStruct->TIM_ICSelection == TIM_ICSelection_DirectTI) - { - icoppositeselection = TIM_ICSelection_IndirectTI; - } - else - { - icoppositeselection = TIM_ICSelection_DirectTI; - } - if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_1) - { - /* TI1 Configuration */ - TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection, - TIM_ICInitStruct->TIM_ICFilter); - /* Set the Input Capture Prescaler value */ - TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); - /* TI2 Configuration */ - TI2_Config(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->TIM_ICFilter); - /* Set the Input Capture Prescaler value */ - TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); - } - else - { - /* TI2 Configuration */ - TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection, - TIM_ICInitStruct->TIM_ICFilter); - /* Set the Input Capture Prescaler value */ - TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); - /* TI1 Configuration */ - TI1_Config(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->TIM_ICFilter); - /* Set the Input Capture Prescaler value */ - TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); - } -} - -/** - * @brief Gets the TIMx Input Capture 1 value. - * @param TIMx: where x can be 1, 2, 3, 14, 15, 16 or 17 to select the TIM peripheral. - * @retval Capture Compare 1 Register value. - */ -uint32_t TIM_GetCapture1(TIM_TypeDef* TIMx) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST4_PERIPH(TIMx)); - - /* Get the Capture 1 Register value */ - return TIMx->CCR1; -} - -/** - * @brief Gets the TIMx Input Capture 2 value. - * @param TIMx: where x can be 1, 2, 3 or 15 to select the TIM peripheral. - * @retval Capture Compare 2 Register value. - */ -uint32_t TIM_GetCapture2(TIM_TypeDef* TIMx) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST6_PERIPH(TIMx)); - - /* Get the Capture 2 Register value */ - return TIMx->CCR2; -} - -/** - * @brief Gets the TIMx Input Capture 3 value. - * @param TIMx: where x can be 1, 2 or 3 to select the TIM peripheral. - * @retval Capture Compare 3 Register value. - */ -uint32_t TIM_GetCapture3(TIM_TypeDef* TIMx) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - - /* Get the Capture 3 Register value */ - return TIMx->CCR3; -} - -/** - * @brief Gets the TIMx Input Capture 4 value. - * @param TIMx: where x can be 1, 2 or 3 to select the TIM peripheral. - * @retval Capture Compare 4 Register value. - */ -uint32_t TIM_GetCapture4(TIM_TypeDef* TIMx) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - - /* Get the Capture 4 Register value */ - return TIMx->CCR4; -} - -/** - * @brief Sets the TIMx Input Capture 1 prescaler. - * @param TIMx: where x can be 1, 2, 3, 14, 15, 16 or 17 to select the TIM peripheral. - * @param TIM_ICPSC: specifies the Input Capture1 prescaler new value. - * This parameter can be one of the following values: - * @arg TIM_ICPSC_DIV1: no prescaler - * @arg TIM_ICPSC_DIV2: capture is done once every 2 events - * @arg TIM_ICPSC_DIV4: capture is done once every 4 events - * @arg TIM_ICPSC_DIV8: capture is done once every 8 events - * @retval None - */ -void TIM_SetIC1Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST4_PERIPH(TIMx)); - assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC)); - - /* Reset the IC1PSC Bits */ - TIMx->CCMR1 &= (uint16_t)~((uint16_t)TIM_CCMR1_IC1PSC); - /* Set the IC1PSC value */ - TIMx->CCMR1 |= TIM_ICPSC; -} - -/** - * @brief Sets the TIMx Input Capture 2 prescaler. - * @param TIMx: where x can be 1, 2, 3 or 15 to select the TIM peripheral. - * @param TIM_ICPSC: specifies the Input Capture2 prescaler new value. - * This parameter can be one of the following values: - * @arg TIM_ICPSC_DIV1: no prescaler - * @arg TIM_ICPSC_DIV2: capture is done once every 2 events - * @arg TIM_ICPSC_DIV4: capture is done once every 4 events - * @arg TIM_ICPSC_DIV8: capture is done once every 8 events - * @retval None - */ -void TIM_SetIC2Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST6_PERIPH(TIMx)); - assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC)); - - /* Reset the IC2PSC Bits */ - TIMx->CCMR1 &= (uint16_t)~((uint16_t)TIM_CCMR1_IC2PSC); - /* Set the IC2PSC value */ - TIMx->CCMR1 |= (uint16_t)(TIM_ICPSC << 8); -} - -/** - * @brief Sets the TIMx Input Capture 3 prescaler. - * @param TIMx: where x can be 1, 2 or 3 to select the TIM peripheral. - * @param TIM_ICPSC: specifies the Input Capture3 prescaler new value. - * This parameter can be one of the following values: - * @arg TIM_ICPSC_DIV1: no prescaler - * @arg TIM_ICPSC_DIV2: capture is done once every 2 events - * @arg TIM_ICPSC_DIV4: capture is done once every 4 events - * @arg TIM_ICPSC_DIV8: capture is done once every 8 events - * @retval None - */ -void TIM_SetIC3Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC)); - - /* Reset the IC3PSC Bits */ - TIMx->CCMR2 &= (uint16_t)~((uint16_t)TIM_CCMR2_IC3PSC); - /* Set the IC3PSC value */ - TIMx->CCMR2 |= TIM_ICPSC; -} - -/** - * @brief Sets the TIMx Input Capture 4 prescaler. - * @param TIMx: where x can be 1, 2 or 3 to select the TIM peripheral. - * @param TIM_ICPSC: specifies the Input Capture4 prescaler new value. - * This parameter can be one of the following values: - * @arg TIM_ICPSC_DIV1: no prescaler - * @arg TIM_ICPSC_DIV2: capture is done once every 2 events - * @arg TIM_ICPSC_DIV4: capture is done once every 4 events - * @arg TIM_ICPSC_DIV8: capture is done once every 8 events - * @retval None - */ -void TIM_SetIC4Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC)); - - /* Reset the IC4PSC Bits */ - TIMx->CCMR2 &= (uint16_t)~((uint16_t)TIM_CCMR2_IC4PSC); - /* Set the IC4PSC value */ - TIMx->CCMR2 |= (uint16_t)(TIM_ICPSC << 8); -} - -/** - * @} - */ -/** - * @brief Enables or disables the specified TIM interrupts. - * @param TIMx: where x can be 1, 2, 3, 6, 7, 14, 15, 16 or 17 to select the TIMx peripheral. - * @param TIM_IT: specifies the TIM interrupts sources to be enabled or disabled. - * This parameter can be any combination of the following values: - * @arg TIM_IT_Update: TIM update Interrupt source - * @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source - * @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source - * @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source - * @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source - * @arg TIM_IT_COM: TIM Commutation Interrupt source - * @arg TIM_IT_Trigger: TIM Trigger Interrupt source - * @arg TIM_IT_Break: TIM Break Interrupt source - * - * @note TIM6 and TIM7 can only generate an update interrupt. - * @note TIM15 can have only TIM_IT_Update, TIM_IT_CC1,TIM_IT_CC2 or TIM_IT_Trigger. - * @note TIM14, TIM16 and TIM17 can have TIM_IT_Update or TIM_IT_CC1. - * @note TIM_IT_Break is used only with TIM1 and TIM15. - * @note TIM_IT_COM is used only with TIM1, TIM15, TIM16 and TIM17. - * - * @param NewState: new state of the TIM interrupts. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void TIM_ITConfig(TIM_TypeDef* TIMx, uint16_t TIM_IT, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - assert_param(IS_TIM_IT(TIM_IT)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the Interrupt sources */ - TIMx->DIER |= TIM_IT; - } - else - { - /* Disable the Interrupt sources */ - TIMx->DIER &= (uint16_t)~TIM_IT; - } -} - -/** - * @brief Configures the TIMx event to be generate by software. - * @param TIMx: where x can be 1, 2, 3, 6, 7, 14, 15, 16 or 17 to select the - * TIM peripheral. - * @param TIM_EventSource: specifies the event source. - * This parameter can be one or more of the following values: - * @arg TIM_EventSource_Update: Timer update Event source - * @arg TIM_EventSource_CC1: Timer Capture Compare 1 Event source - * @arg TIM_EventSource_CC2: Timer Capture Compare 2 Event source - * @arg TIM_EventSource_CC3: Timer Capture Compare 3 Event source - * @arg TIM_EventSource_CC4: Timer Capture Compare 4 Event source - * @arg TIM_EventSource_COM: Timer COM event source - * @arg TIM_EventSource_Trigger: Timer Trigger Event source - * @arg TIM_EventSource_Break: Timer Break event source - * - * @note TIM6 and TIM7 can only generate an update event. - * @note TIM_EventSource_COM and TIM_EventSource_Break are used only with TIM1. - * - * @retval None - */ -void TIM_GenerateEvent(TIM_TypeDef* TIMx, uint16_t TIM_EventSource) -{ - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - assert_param(IS_TIM_EVENT_SOURCE(TIM_EventSource)); - /* Set the event sources */ - TIMx->EGR = TIM_EventSource; -} - -/** - * @brief Checks whether the specified TIM flag is set or not. - * @param TIMx: where x can be 1, 2, 3, 6, 7, 14, 15, 16 or 17 to select the TIM peripheral. - * @param TIM_FLAG: specifies the flag to check. - * This parameter can be one of the following values: - * @arg TIM_FLAG_Update: TIM update Flag - * @arg TIM_FLAG_CC1: TIM Capture Compare 1 Flag - * @arg TIM_FLAG_CC2: TIM Capture Compare 2 Flag - * @arg TIM_FLAG_CC3: TIM Capture Compare 3 Flag - * @arg TIM_FLAG_CC4: TIM Capture Compare 4 Flag - * @arg TIM_FLAG_COM: TIM Commutation Flag - * @arg TIM_FLAG_Trigger: TIM Trigger Flag - * @arg TIM_FLAG_Break: TIM Break Flag - * @arg TIM_FLAG_CC1OF: TIM Capture Compare 1 overcapture Flag - * @arg TIM_FLAG_CC2OF: TIM Capture Compare 2 overcapture Flag - * @arg TIM_FLAG_CC3OF: TIM Capture Compare 3 overcapture Flag - * @arg TIM_FLAG_CC4OF: TIM Capture Compare 4 overcapture Flag - * - * @note TIM6 and TIM7 can have only one update flag. - * @note TIM15 can have only TIM_FLAG_Update, TIM_FLAG_CC1, TIM_FLAG_CC2 or TIM_FLAG_Trigger. - * @note TIM14, TIM16 and TIM17 can have TIM_FLAG_Update or TIM_FLAG_CC1. - * @note TIM_FLAG_Break is used only with TIM1 and TIM15. - * @note TIM_FLAG_COM is used only with TIM1 TIM15, TIM16 and TIM17. - * - * @retval The new state of TIM_FLAG (SET or RESET). - */ -FlagStatus TIM_GetFlagStatus(TIM_TypeDef* TIMx, uint16_t TIM_FLAG) -{ - ITStatus bitstatus = RESET; - - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - assert_param(IS_TIM_GET_FLAG(TIM_FLAG)); - - if ((TIMx->SR & TIM_FLAG) != (uint16_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - return bitstatus; -} - -/** - * @brief Clears the TIMx's pending flags. - * @param TIMx: where x can be 1, 2, 3, 6, 7, 14, 15, 16 or 17 to select the TIM peripheral. - * @param TIM_FLAG: specifies the flag bit to clear. - * This parameter can be any combination of the following values: - * @arg TIM_FLAG_Update: TIM update Flag - * @arg TIM_FLAG_CC1: TIM Capture Compare 1 Flag - * @arg TIM_FLAG_CC2: TIM Capture Compare 2 Flag - * @arg TIM_FLAG_CC3: TIM Capture Compare 3 Flag - * @arg TIM_FLAG_CC4: TIM Capture Compare 4 Flag - * @arg TIM_FLAG_COM: TIM Commutation Flag - * @arg TIM_FLAG_Trigger: TIM Trigger Flag - * @arg TIM_FLAG_Break: TIM Break Flag - * @arg TIM_FLAG_CC1OF: TIM Capture Compare 1 overcapture Flag - * @arg TIM_FLAG_CC2OF: TIM Capture Compare 2 overcapture Flag - * @arg TIM_FLAG_CC3OF: TIM Capture Compare 3 overcapture Flag - * @arg TIM_FLAG_CC4OF: TIM Capture Compare 4 overcapture Flag - * - * @note TIM6 and TIM7 can have only one update flag. - * @note TIM15 can have only TIM_FLAG_Update, TIM_FLAG_CC1,TIM_FLAG_CC2 or - * TIM_FLAG_Trigger. - * @note TIM14, TIM16 and TIM17 can have TIM_FLAG_Update or TIM_FLAG_CC1. - * @note TIM_FLAG_Break is used only with TIM1 and TIM15. - * @note TIM_FLAG_COM is used only with TIM1, TIM15, TIM16 and TIM17. - * - * @retval None - */ -void TIM_ClearFlag(TIM_TypeDef* TIMx, uint16_t TIM_FLAG) -{ - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - assert_param(IS_TIM_CLEAR_FLAG(TIM_FLAG)); - - /* Clear the flags */ - TIMx->SR = (uint16_t)~TIM_FLAG; -} - -/** - * @brief Checks whether the TIM interrupt has occurred or not. - * @param TIMx: where x can be 1, 2, 3, 6, 7, 14, 15, 16 or 17 to select the TIM peripheral. - * @param TIM_IT: specifies the TIM interrupt source to check. - * This parameter can be one of the following values: - * @arg TIM_IT_Update: TIM update Interrupt source - * @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source - * @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source - * @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source - * @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source - * @arg TIM_IT_COM: TIM Commutation Interrupt source - * @arg TIM_IT_Trigger: TIM Trigger Interrupt source - * @arg TIM_IT_Break: TIM Break Interrupt source - * - * @note TIM6 and TIM7 can generate only an update interrupt. - * @note TIM15 can have only TIM_IT_Update, TIM_IT_CC1, TIM_IT_CC2 or TIM_IT_Trigger. - * @note TIM14, TIM16 and TIM17 can have TIM_IT_Update or TIM_IT_CC1. - * @note TIM_IT_Break is used only with TIM1 and TIM15. - * @note TIM_IT_COM is used only with TIM1, TIM15, TIM16 and TIM17. - * - * @retval The new state of the TIM_IT(SET or RESET). - */ -ITStatus TIM_GetITStatus(TIM_TypeDef* TIMx, uint16_t TIM_IT) -{ - ITStatus bitstatus = RESET; - uint16_t itstatus = 0x0, itenable = 0x0; - - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - assert_param(IS_TIM_GET_IT(TIM_IT)); - - itstatus = TIMx->SR & TIM_IT; - - itenable = TIMx->DIER & TIM_IT; - if ((itstatus != (uint16_t)RESET) && (itenable != (uint16_t)RESET)) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - return bitstatus; -} - -/** - * @brief Clears the TIMx's interrupt pending bits. - * @param TIMx: where x can be 1, 2, 3, 6, 7, 14, 15, 16 or 17 to select the TIM peripheral. - * @param TIM_IT: specifies the pending bit to clear. - * This parameter can be any combination of the following values: - * @arg TIM_IT_Update: TIM1 update Interrupt source - * @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source - * @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source - * @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source - * @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source - * @arg TIM_IT_COM: TIM Commutation Interrupt source - * @arg TIM_IT_Trigger: TIM Trigger Interrupt source - * @arg TIM_IT_Break: TIM Break Interrupt source - * - * @note TIM6 and TIM7 can generate only an update interrupt. - * @note TIM15 can have only TIM_IT_Update, TIM_IT_CC1, TIM_IT_CC2 or TIM_IT_Trigger. - * @note TIM14, TIM16 and TIM17 can have TIM_IT_Update or TIM_IT_CC1. - * @note TIM_IT_Break is used only with TIM1 and TIM15. - * @note TIM_IT_COM is used only with TIM1, TIM15, TIM16 and TIM17. - * - * @retval None - */ -void TIM_ClearITPendingBit(TIM_TypeDef* TIMx, uint16_t TIM_IT) -{ - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - assert_param(IS_TIM_IT(TIM_IT)); - - /* Clear the IT pending Bit */ - TIMx->SR = (uint16_t)~TIM_IT; -} - -/** - * @brief Configures the TIMx's DMA interface. - * @param TIMx: where x can be 1, 2, 3, 15, 16 or 17 to select the TIM peripheral. - * @param TIM_DMABase: DMA Base address. - * This parameter can be one of the following values: - * @arg TIM_DMABase_CR1 - * @arg TIM_DMABase_CR2 - * @arg TIM_DMABase_SMCR - * @arg TIM_DMABase_DIER - * @arg TIM_DMABase_SR - * @arg TIM_DMABase_EGR - * @arg TIM_DMABase_CCMR1 - * @arg TIM_DMABase_CCMR2 - * @arg TIM_DMABase_CCER - * @arg TIM_DMABase_CNT - * @arg TIM_DMABase_PSC - * @arg TIM_DMABase_ARR - * @arg TIM_DMABase_CCR1 - * @arg TIM_DMABase_CCR2 - * @arg TIM_DMABase_CCR3 - * @arg TIM_DMABase_CCR4 - * @arg TIM_DMABase_DCR - * @arg TIM_DMABase_OR - * @param TIM_DMABurstLength: DMA Burst length. This parameter can be one value - * between: TIM_DMABurstLength_1Transfer and TIM_DMABurstLength_18Transfers. - * @retval None - */ -void TIM_DMAConfig(TIM_TypeDef* TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST4_PERIPH(TIMx)); - assert_param(IS_TIM_DMA_BASE(TIM_DMABase)); - assert_param(IS_TIM_DMA_LENGTH(TIM_DMABurstLength)); - /* Set the DMA Base and the DMA Burst Length */ - TIMx->DCR = TIM_DMABase | TIM_DMABurstLength; -} - -/** - * @brief Enables or disables the TIMx's DMA Requests. - * @param TIMx: where x can be 1, 2, 3, 6, 7, 15, 16 or 17 to select the TIM peripheral. - * @param TIM_DMASource: specifies the DMA Request sources. - * This parameter can be any combination of the following values: - * @arg TIM_DMA_Update: TIM update Interrupt source - * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source - * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source - * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source - * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source - * @arg TIM_DMA_COM: TIM Commutation DMA source - * @arg TIM_DMA_Trigger: TIM Trigger DMA source - * @param NewState: new state of the DMA Request sources. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void TIM_DMACmd(TIM_TypeDef* TIMx, uint16_t TIM_DMASource, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST10_PERIPH(TIMx)); - assert_param(IS_TIM_DMA_SOURCE(TIM_DMASource)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the DMA sources */ - TIMx->DIER |= TIM_DMASource; - } - else - { - /* Disable the DMA sources */ - TIMx->DIER &= (uint16_t)~TIM_DMASource; - } -} - -/** - * @brief Selects the TIMx peripheral Capture Compare DMA source. - * @param TIMx: where x can be 1, 2, 3, 15, 16 or 17 to select the TIM peripheral. - * @param NewState: new state of the Capture Compare DMA source - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void TIM_SelectCCDMA(TIM_TypeDef* TIMx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST5_PERIPH(TIMx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Set the CCDS Bit */ - TIMx->CR2 |= TIM_CR2_CCDS; - } - else - { - /* Reset the CCDS Bit */ - TIMx->CR2 &= (uint16_t)~((uint16_t)TIM_CR2_CCDS); - } -} - -/** - * @} - */ -/** - * @brief Configures the TIMx internal Clock - * @param TIMx: where x can be 1, 2, 3, or 15 to select the TIM peripheral. - * @retval None - */ -void TIM_InternalClockConfig(TIM_TypeDef* TIMx) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST6_PERIPH(TIMx)); - /* Disable slave mode to clock the prescaler directly with the internal clock */ - TIMx->SMCR &= (uint16_t)(~((uint16_t)TIM_SMCR_SMS)); -} - -/** - * @brief Configures the TIMx Internal Trigger as External Clock - * @param TIMx: where x can be 1, 2, 3, or 15 to select the TIM peripheral. - * @param TIM_ITRSource: Trigger source. - * This parameter can be one of the following values: - * @arg TIM_TS_ITR0: Internal Trigger 0 - * @arg TIM_TS_ITR1: Internal Trigger 1 - * @arg TIM_TS_ITR2: Internal Trigger 2 - * @arg TIM_TS_ITR3: Internal Trigger 3 - * @retval None - */ -void TIM_ITRxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST6_PERIPH(TIMx)); - assert_param(IS_TIM_INTERNAL_TRIGGER_SELECTION(TIM_InputTriggerSource)); - /* Select the Internal Trigger */ - TIM_SelectInputTrigger(TIMx, TIM_InputTriggerSource); - /* Select the External clock mode1 */ - TIMx->SMCR |= TIM_SlaveMode_External1; -} - -/** - * @brief Configures the TIMx Trigger as External Clock - * @param TIMx: where x can be 1, 2, 3, or 15 to select the TIM peripheral. - * @param TIM_TIxExternalCLKSource: Trigger source. - * This parameter can be one of the following values: - * @arg TIM_TIxExternalCLK1Source_TI1ED: TI1 Edge Detector - * @arg TIM_TIxExternalCLK1Source_TI1: Filtered Timer Input 1 - * @arg TIM_TIxExternalCLK1Source_TI2: Filtered Timer Input 2 - * @param TIM_ICPolarity: specifies the TIx Polarity. - * This parameter can be one of the following values: - * @arg TIM_ICPolarity_Rising - * @arg TIM_ICPolarity_Falling - * @param ICFilter: specifies the filter value. - * This parameter must be a value between 0x0 and 0xF. - * @retval None - */ -void TIM_TIxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_TIxExternalCLKSource, - uint16_t TIM_ICPolarity, uint16_t ICFilter) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST6_PERIPH(TIMx)); - assert_param(IS_TIM_IC_POLARITY(TIM_ICPolarity)); - assert_param(IS_TIM_IC_FILTER(ICFilter)); - - /* Configure the Timer Input Clock Source */ - if (TIM_TIxExternalCLKSource == TIM_TIxExternalCLK1Source_TI2) - { - TI2_Config(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter); - } - else - { - TI1_Config(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter); - } - /* Select the Trigger source */ - TIM_SelectInputTrigger(TIMx, TIM_TIxExternalCLKSource); - /* Select the External clock mode1 */ - TIMx->SMCR |= TIM_SlaveMode_External1; -} - -/** - * @brief Configures the External clock Mode1 - * @param TIMx: where x can be 1, 2 or 3 to select the TIM peripheral. - * @param TIM_ExtTRGPrescaler: The external Trigger Prescaler. - * This parameter can be one of the following values: - * @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF. - * @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2. - * @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4. - * @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8. - * @param TIM_ExtTRGPolarity: The external Trigger Polarity. - * This parameter can be one of the following values: - * @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active. - * @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active. - * @param ExtTRGFilter: External Trigger Filter. - * This parameter must be a value between 0x00 and 0x0F - * @retval None - */ -void TIM_ETRClockMode1Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, - uint16_t ExtTRGFilter) -{ - uint16_t tmpsmcr = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler)); - assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity)); - assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter)); - - /* Configure the ETR Clock source */ - TIM_ETRConfig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter); - - /* Get the TIMx SMCR register value */ - tmpsmcr = TIMx->SMCR; - /* Reset the SMS Bits */ - tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMCR_SMS)); - /* Select the External clock mode1 */ - tmpsmcr |= TIM_SlaveMode_External1; - /* Select the Trigger selection : ETRF */ - tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMCR_TS)); - tmpsmcr |= TIM_TS_ETRF; - /* Write to TIMx SMCR */ - TIMx->SMCR = tmpsmcr; -} - -/** - * @brief Configures the External clock Mode2 - * @param TIMx: where x can be 1, 2 or 3 to select the TIM peripheral. - * @param TIM_ExtTRGPrescaler: The external Trigger Prescaler. - * This parameter can be one of the following values: - * @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF. - * @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2. - * @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4. - * @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8. - * @param TIM_ExtTRGPolarity: The external Trigger Polarity. - * This parameter can be one of the following values: - * @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active. - * @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active. - * @param ExtTRGFilter: External Trigger Filter. - * This parameter must be a value between 0x00 and 0x0F - * @retval None - */ -void TIM_ETRClockMode2Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, - uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler)); - assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity)); - assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter)); - - /* Configure the ETR Clock source */ - TIM_ETRConfig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter); - /* Enable the External clock mode2 */ - TIMx->SMCR |= TIM_SMCR_ECE; -} - -/** - * @} - */ -/** - * @brief Selects the Input Trigger source - * @param TIMx: where x can be 1, 2, 3 or 15 to select the TIM peripheral. - * @param TIM_InputTriggerSource: The Input Trigger source. - * This parameter can be one of the following values: - * @arg TIM_TS_ITR0: Internal Trigger 0 - * @arg TIM_TS_ITR1: Internal Trigger 1 - * @arg TIM_TS_ITR2: Internal Trigger 2 - * @arg TIM_TS_ITR3: Internal Trigger 3 - * @arg TIM_TS_TI1F_ED: TI1 Edge Detector - * @arg TIM_TS_TI1FP1: Filtered Timer Input 1 - * @arg TIM_TS_TI2FP2: Filtered Timer Input 2 - * @arg TIM_TS_ETRF: External Trigger input - * @retval None - */ -void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource) -{ - uint16_t tmpsmcr = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST6_PERIPH(TIMx)); - assert_param(IS_TIM_TRIGGER_SELECTION(TIM_InputTriggerSource)); - - /* Get the TIMx SMCR register value */ - tmpsmcr = TIMx->SMCR; - /* Reset the TS Bits */ - tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMCR_TS)); - /* Set the Input Trigger source */ - tmpsmcr |= TIM_InputTriggerSource; - /* Write to TIMx SMCR */ - TIMx->SMCR = tmpsmcr; -} - -/** - * @brief Selects the TIMx Trigger Output Mode. - * @param TIMx: where x can be 1, 2, 3, 6, 7, or 15 to select the TIM peripheral. - * @param TIM_TRGOSource: specifies the Trigger Output source. - * This parameter can be one of the following values: - * - * - For all TIMx - * @arg TIM_TRGOSource_Reset: The UG bit in the TIM_EGR register is used as the trigger output (TRGO). - * @arg TIM_TRGOSource_Enable: The Counter Enable CEN is used as the trigger output (TRGO). - * @arg TIM_TRGOSource_Update: The update event is selected as the trigger output (TRGO). - * - * - For all TIMx except TIM6 and TIM7 - * @arg TIM_TRGOSource_OC1: The trigger output sends a positive pulse when the CC1IF flag - * is to be set, as soon as a capture or compare match occurs (TRGO). - * @arg TIM_TRGOSource_OC1Ref: OC1REF signal is used as the trigger output (TRGO). - * @arg TIM_TRGOSource_OC2Ref: OC2REF signal is used as the trigger output (TRGO). - * @arg TIM_TRGOSource_OC3Ref: OC3REF signal is used as the trigger output (TRGO). - * @arg TIM_TRGOSource_OC4Ref: OC4REF signal is used as the trigger output (TRGO). - * - * @retval None - */ -void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_TRGOSource) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST9_PERIPH(TIMx)); - assert_param(IS_TIM_TRGO_SOURCE(TIM_TRGOSource)); - - /* Reset the MMS Bits */ - TIMx->CR2 &= (uint16_t)~((uint16_t)TIM_CR2_MMS); - /* Select the TRGO source */ - TIMx->CR2 |= TIM_TRGOSource; -} - -/** - * @brief Selects the TIMx Slave Mode. - * @param TIMx: where x can be 1, 2, 3 or 15 to select the TIM peripheral. - * @param TIM_SlaveMode: specifies the Timer Slave Mode. - * This parameter can be one of the following values: - * @arg TIM_SlaveMode_Reset: Rising edge of the selected trigger signal (TRGI) re-initializes - * the counter and triggers an update of the registers. - * @arg TIM_SlaveMode_Gated: The counter clock is enabled when the trigger signal (TRGI) is high. - * @arg TIM_SlaveMode_Trigger: The counter starts at a rising edge of the trigger TRGI. - * @arg TIM_SlaveMode_External1: Rising edges of the selected trigger (TRGI) clock the counter. - * @retval None - */ -void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST6_PERIPH(TIMx)); - assert_param(IS_TIM_SLAVE_MODE(TIM_SlaveMode)); - - /* Reset the SMS Bits */ - TIMx->SMCR &= (uint16_t)~((uint16_t)TIM_SMCR_SMS); - /* Select the Slave Mode */ - TIMx->SMCR |= TIM_SlaveMode; -} - -/** - * @brief Sets or Resets the TIMx Master/Slave Mode. - * @param TIMx: where x can be 1, 2, 3, or 15 to select the TIM peripheral. - * @param TIM_MasterSlaveMode: specifies the Timer Master Slave Mode. - * This parameter can be one of the following values: - * @arg TIM_MasterSlaveMode_Enable: synchronization between the current timer - * and its slaves (through TRGO). - * @arg TIM_MasterSlaveMode_Disable: No action - * @retval None - */ -void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_MasterSlaveMode) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST6_PERIPH(TIMx)); - assert_param(IS_TIM_MSM_STATE(TIM_MasterSlaveMode)); - - /* Reset the MSM Bit */ - TIMx->SMCR &= (uint16_t)~((uint16_t)TIM_SMCR_MSM); - - /* Set or Reset the MSM Bit */ - TIMx->SMCR |= TIM_MasterSlaveMode; -} - -/** - * @brief Configures the TIMx External Trigger (ETR). - * @param TIMx: where x can be 1, 2 or 3 to select the TIM peripheral. - * @param TIM_ExtTRGPrescaler: The external Trigger Prescaler. - * This parameter can be one of the following values: - * @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF. - * @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2. - * @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4. - * @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8. - * @param TIM_ExtTRGPolarity: The external Trigger Polarity. - * This parameter can be one of the following values: - * @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active. - * @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active. - * @param ExtTRGFilter: External Trigger Filter. - * This parameter must be a value between 0x00 and 0x0F - * @retval None - */ -void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, - uint16_t ExtTRGFilter) -{ - uint16_t tmpsmcr = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler)); - assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity)); - assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter)); - - tmpsmcr = TIMx->SMCR; - /* Reset the ETR Bits */ - tmpsmcr &= SMCR_ETR_MASK; - /* Set the Prescaler, the Filter value and the Polarity */ - tmpsmcr |= (uint16_t)(TIM_ExtTRGPrescaler | (uint16_t)(TIM_ExtTRGPolarity | (uint16_t)(ExtTRGFilter << (uint16_t)8))); - /* Write to TIMx SMCR */ - TIMx->SMCR = tmpsmcr; -} - -/** - * @} - */ -/** - * @brief Configures the TIMx Encoder Interface. - * @param TIMx: where x can be 1, 2 or 3 to select the TIM peripheral. - * @param TIM_EncoderMode: specifies the TIMx Encoder Mode. - * This parameter can be one of the following values: - * @arg TIM_EncoderMode_TI1: Counter counts on TI1FP1 edge depending on TI2FP2 level. - * @arg TIM_EncoderMode_TI2: Counter counts on TI2FP2 edge depending on TI1FP1 level. - * @arg TIM_EncoderMode_TI12: Counter counts on both TI1FP1 and TI2FP2 edges depending - * on the level of the other input. - * @param TIM_IC1Polarity: specifies the IC1 Polarity - * This parmeter can be one of the following values: - * @arg TIM_ICPolarity_Falling: IC Falling edge. - * @arg TIM_ICPolarity_Rising: IC Rising edge. - * @param TIM_IC2Polarity: specifies the IC2 Polarity - * This parmeter can be one of the following values: - * @arg TIM_ICPolarity_Falling: IC Falling edge. - * @arg TIM_ICPolarity_Rising: IC Rising edge. - * @retval None - */ -void TIM_EncoderInterfaceConfig(TIM_TypeDef* TIMx, uint16_t TIM_EncoderMode, - uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity) -{ - uint16_t tmpsmcr = 0; - uint16_t tmpccmr1 = 0; - uint16_t tmpccer = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_TIM_ENCODER_MODE(TIM_EncoderMode)); - assert_param(IS_TIM_IC_POLARITY(TIM_IC1Polarity)); - assert_param(IS_TIM_IC_POLARITY(TIM_IC2Polarity)); - - /* Get the TIMx SMCR register value */ - tmpsmcr = TIMx->SMCR; - /* Get the TIMx CCMR1 register value */ - tmpccmr1 = TIMx->CCMR1; - /* Get the TIMx CCER register value */ - tmpccer = TIMx->CCER; - /* Set the encoder Mode */ - tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMCR_SMS)); - tmpsmcr |= TIM_EncoderMode; - /* Select the Capture Compare 1 and the Capture Compare 2 as input */ - tmpccmr1 &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCMR1_CC1S)) & (uint16_t)(~((uint16_t)TIM_CCMR1_CC2S))); - tmpccmr1 |= TIM_CCMR1_CC1S_0 | TIM_CCMR1_CC2S_0; - /* Set the TI1 and the TI2 Polarities */ - tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC1P | TIM_CCER_CC1NP)) & (uint16_t)~((uint16_t)(TIM_CCER_CC2P | TIM_CCER_CC2NP)); - tmpccer |= (uint16_t)(TIM_IC1Polarity | (uint16_t)(TIM_IC2Polarity << (uint16_t)4)); - /* Write to TIMx SMCR */ - TIMx->SMCR = tmpsmcr; - /* Write to TIMx CCMR1 */ - TIMx->CCMR1 = tmpccmr1; - /* Write to TIMx CCER */ - TIMx->CCER = tmpccer; -} - -/** - * @brief Enables or disables the TIMx's Hall sensor interface. - * @param TIMx: where x can be 1, 2 or 3 to select the TIM peripheral. - * @param NewState: new state of the TIMx Hall sensor interface. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void TIM_SelectHallSensor(TIM_TypeDef* TIMx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Set the TI1S Bit */ - TIMx->CR2 |= TIM_CR2_TI1S; - } - else - { - /* Reset the TI1S Bit */ - TIMx->CR2 &= (uint16_t)~((uint16_t)TIM_CR2_TI1S); - } -} - -/** - * @} - */ -/** - * @brief Configures the TIM14 Remapping input Capabilities. - * @param TIMx: where x can be 14 to select the TIM peripheral. - * @param TIM_Remap: specifies the TIM input reampping source. - * This parameter can be one of the following values: - * @arg TIM14_GPIO: TIM14 Channel 1 is connected to GPIO. - * @arg TIM14_RTC_CLK: TIM14 Channel 1 is connected to RTC input clock. - * RTC input clock can be LSE, LSI or HSE/div128. - * @arg TIM14_HSE_DIV32: TIM14 Channel 1 is connected to HSE/32 clock. - * @arg TIM14_MCO: TIM14 Channel 1 is connected to MCO clock. - * MCO clock can be HSI14, SYSCLK, HSI, HSE or PLL/2. - * @retval None - */ -void TIM_RemapConfig(TIM_TypeDef* TIMx, uint16_t TIM_Remap) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST11_PERIPH(TIMx)); - assert_param(IS_TIM_REMAP(TIM_Remap)); - - /* Set the Timer remapping configuration */ - TIMx->OR = TIM_Remap; -} - -/** - * @} - */ - -/** - * @brief Configure the TI1 as Input. - * @param TIMx: where x can be 1, 2, 3, 14, 15, 16 or 17 to select the TIM peripheral. - * @param TIM_ICPolarity: The Input Polarity. - * This parameter can be one of the following values: - * @arg TIM_ICPolarity_Rising - * @arg TIM_ICPolarity_Falling - * @param TIM_ICSelection: specifies the input to be used. - * This parameter can be one of the following values: - * @arg TIM_ICSelection_DirectTI: TIM Input 1 is selected to be connected to IC1. - * @arg TIM_ICSelection_IndirectTI: TIM Input 1 is selected to be connected to IC2. - * @arg TIM_ICSelection_TRC: TIM Input 1 is selected to be connected to TRC. - * @param TIM_ICFilter: Specifies the Input Capture Filter. - * This parameter must be a value between 0x00 and 0x0F. - * @retval None - */ -static void TI1_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, - uint16_t TIM_ICFilter) -{ - uint16_t tmpccmr1 = 0, tmpccer = 0; - /* Disable the Channel 1: Reset the CC1E Bit */ - TIMx->CCER &= (uint16_t)~((uint16_t)TIM_CCER_CC1E); - tmpccmr1 = TIMx->CCMR1; - tmpccer = TIMx->CCER; - /* Select the Input and set the filter */ - tmpccmr1 &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCMR1_CC1S)) & ((uint16_t)~((uint16_t)TIM_CCMR1_IC1F))); - tmpccmr1 |= (uint16_t)(TIM_ICSelection | (uint16_t)(TIM_ICFilter << (uint16_t)4)); - - /* Select the Polarity and set the CC1E Bit */ - tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC1P | TIM_CCER_CC1NP)); - tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CCER_CC1E); - /* Write to TIMx CCMR1 and CCER registers */ - TIMx->CCMR1 = tmpccmr1; - TIMx->CCER = tmpccer; -} - -/** - * @brief Configure the TI2 as Input. - * @param TIMx: where x can be 1, 2, 3, or 15 to select the TIM peripheral. - * @param TIM_ICPolarity: The Input Polarity. - * This parameter can be one of the following values: - * @arg TIM_ICPolarity_Rising - * @arg TIM_ICPolarity_Falling - * @param TIM_ICSelection: specifies the input to be used. - * This parameter can be one of the following values: - * @arg TIM_ICSelection_DirectTI: TIM Input 2 is selected to be connected to IC2. - * @arg TIM_ICSelection_IndirectTI: TIM Input 2 is selected to be connected to IC1. - * @arg TIM_ICSelection_TRC: TIM Input 2 is selected to be connected to TRC. - * @param TIM_ICFilter: Specifies the Input Capture Filter. - * This parameter must be a value between 0x00 and 0x0F. - * @retval None - */ -static void TI2_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, - uint16_t TIM_ICFilter) -{ - uint16_t tmpccmr1 = 0, tmpccer = 0, tmp = 0; - /* Disable the Channel 2: Reset the CC2E Bit */ - TIMx->CCER &= (uint16_t)~((uint16_t)TIM_CCER_CC2E); - tmpccmr1 = TIMx->CCMR1; - tmpccer = TIMx->CCER; - tmp = (uint16_t)(TIM_ICPolarity << 4); - /* Select the Input and set the filter */ - tmpccmr1 &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCMR1_CC2S)) & ((uint16_t)~((uint16_t)TIM_CCMR1_IC2F))); - tmpccmr1 |= (uint16_t)(TIM_ICFilter << 12); - tmpccmr1 |= (uint16_t)(TIM_ICSelection << 8); - /* Select the Polarity and set the CC2E Bit */ - tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC2P | TIM_CCER_CC2NP)); - tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CCER_CC2E); - /* Write to TIMx CCMR1 and CCER registers */ - TIMx->CCMR1 = tmpccmr1 ; - TIMx->CCER = tmpccer; -} - -/** - * @brief Configure the TI3 as Input. - * @param TIMx: where x can be 1, 2 or 3 to select the TIM peripheral. - * @param TIM_ICPolarity: The Input Polarity. - * This parameter can be one of the following values: - * @arg TIM_ICPolarity_Rising - * @arg TIM_ICPolarity_Falling - * @param TIM_ICSelection: specifies the input to be used. - * This parameter can be one of the following values: - * @arg TIM_ICSelection_DirectTI: TIM Input 3 is selected to be connected to IC3. - * @arg TIM_ICSelection_IndirectTI: TIM Input 3 is selected to be connected to IC4. - * @arg TIM_ICSelection_TRC: TIM Input 3 is selected to be connected to TRC. - * @param TIM_ICFilter: Specifies the Input Capture Filter. - * This parameter must be a value between 0x00 and 0x0F. - * @retval None - */ -static void TI3_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, - uint16_t TIM_ICFilter) -{ - uint16_t tmpccmr2 = 0, tmpccer = 0, tmp = 0; - /* Disable the Channel 3: Reset the CC3E Bit */ - TIMx->CCER &= (uint16_t)~((uint16_t)TIM_CCER_CC3E); - tmpccmr2 = TIMx->CCMR2; - tmpccer = TIMx->CCER; - tmp = (uint16_t)(TIM_ICPolarity << 8); - /* Select the Input and set the filter */ - tmpccmr2 &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCMR2_CC3S)) & ((uint16_t)~((uint16_t)TIM_CCMR2_IC3F))); - tmpccmr2 |= (uint16_t)(TIM_ICSelection | (uint16_t)(TIM_ICFilter << (uint16_t)4)); - /* Select the Polarity and set the CC3E Bit */ - tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC3P | TIM_CCER_CC3NP)); - tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CCER_CC3E); - /* Write to TIMx CCMR2 and CCER registers */ - TIMx->CCMR2 = tmpccmr2; - TIMx->CCER = tmpccer; -} - -/** - * @brief Configure the TI4 as Input. - * @param TIMx: where x can be 1, 2 or 3 to select the TIM peripheral. - * @param TIM_ICPolarity: The Input Polarity. - * This parameter can be one of the following values: - * @arg TIM_ICPolarity_Rising - * @arg TIM_ICPolarity_Falling - * @param TIM_ICSelection: specifies the input to be used. - * This parameter can be one of the following values: - * @arg TIM_ICSelection_DirectTI: TIM Input 4 is selected to be connected to IC4. - * @arg TIM_ICSelection_IndirectTI: TIM Input 4 is selected to be connected to IC3. - * @arg TIM_ICSelection_TRC: TIM Input 4 is selected to be connected to TRC. - * @param TIM_ICFilter: Specifies the Input Capture Filter. - * This parameter must be a value between 0x00 and 0x0F. - * @retval None - */ -static void TI4_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, - uint16_t TIM_ICFilter) -{ - uint16_t tmpccmr2 = 0, tmpccer = 0, tmp = 0; - - /* Disable the Channel 4: Reset the CC4E Bit */ - TIMx->CCER &= (uint16_t)~((uint16_t)TIM_CCER_CC4E); - tmpccmr2 = TIMx->CCMR2; - tmpccer = TIMx->CCER; - tmp = (uint16_t)(TIM_ICPolarity << 12); - /* Select the Input and set the filter */ - tmpccmr2 &= (uint16_t)((uint16_t)(~(uint16_t)TIM_CCMR2_CC4S) & ((uint16_t)~((uint16_t)TIM_CCMR2_IC4F))); - tmpccmr2 |= (uint16_t)(TIM_ICSelection << 8); - tmpccmr2 |= (uint16_t)(TIM_ICFilter << 12); - /* Select the Polarity and set the CC4E Bit */ - tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC4P)); - tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CCER_CC4E); - /* Write to TIMx CCMR2 and CCER registers */ - TIMx->CCMR2 = tmpccmr2; - TIMx->CCER = tmpccer; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT FMD *****END OF FILE****/ diff --git a/bsp/ft32/libraries/FT32F0xx/FT32F0xx_Driver/Src/ft32f0xx_usart.c b/bsp/ft32/libraries/FT32F0xx/FT32F0xx_Driver/Src/ft32f0xx_usart.c deleted file mode 100644 index efd5e0c1738..00000000000 --- a/bsp/ft32/libraries/FT32F0xx/FT32F0xx_Driver/Src/ft32f0xx_usart.c +++ /dev/null @@ -1,1188 +0,0 @@ -/** - ****************************************************************************** - * @file ft32f0xx_usart.c - * @author FMD AE - * @brief This file provides firmware functions to manage the following - * functionalities of the Universal synchronous asynchronous receiver - * transmitter (USART): - * + Initialization and Configuration - * + STOP Mode - * + AutoBaudRate - * + Data transfers - * + Multi-Processor Communication - * + LIN mode - * + Half-duplex mode - * + Smartcard mode - * + IrDA mode - * + RS485 mode - * + DMA transfers management - * + Interrupts and flags management - * @version V1.0.0 - * @data 2021-07-01 - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "ft32f0xx_usart.h" -#include "ft32f0xx_rcc.h" - -/*!< USART CR1 register clear Mask ((~(uint32_t)0xFFFFE6F3)) */ -#define CR1_CLEAR_MASK ((uint32_t)(USART_CR1_M | USART_CR1_PCE | \ - USART_CR1_PS | USART_CR1_TE | \ - USART_CR1_RE)) - -/*!< USART CR2 register clock bits clear Mask ((~(uint32_t)0xFFFFF0FF)) */ -#define CR2_CLOCK_CLEAR_MASK ((uint32_t)(USART_CR2_CLKEN | USART_CR2_CPOL | \ - USART_CR2_CPHA | USART_CR2_LBCL)) - -/*!< USART CR3 register clear Mask ((~(uint32_t)0xFFFFFCFF)) */ -#define CR3_CLEAR_MASK ((uint32_t)(USART_CR3_RTSE | USART_CR3_CTSE)) - -/*!< USART Interrupts mask */ -#define IT_MASK ((uint32_t)0x000000FF) - - -/** - * @brief Deinitializes the USARTx peripheral registers to their default reset values. - * @param USARTx: where x can be from 1 to 2 to select the USART peripheral. - * @retval None - */ -void USART_DeInit(USART_TypeDef* USARTx) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - - if (USARTx == USART1) - { - RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART1, ENABLE); - RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART1, DISABLE); - } - else if (USARTx == USART2) - { - RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART2, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART2, DISABLE); - } -} - -/** - * @brief Initializes the USARTx peripheral according to the specified - * parameters in the USART_InitStruct . - * @param USARTx: where x can be from 1 to 2 to select the USART peripheral. - * @param USART_InitStruct: pointer to a USART_InitTypeDef structure that contains - * the configuration information for the specified USART peripheral. - * @retval None - */ -void USART_Init(USART_TypeDef* USARTx, USART_InitTypeDef* USART_InitStruct) -{ - uint32_t divider = 0, apbclock = 0, tmpreg = 0; - RCC_ClocksTypeDef RCC_ClocksStatus; - - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_USART_BAUDRATE(USART_InitStruct->USART_BaudRate)); - assert_param(IS_USART_WORD_LENGTH(USART_InitStruct->USART_WordLength)); - assert_param(IS_USART_STOPBITS(USART_InitStruct->USART_StopBits)); - assert_param(IS_USART_PARITY(USART_InitStruct->USART_Parity)); - assert_param(IS_USART_MODE(USART_InitStruct->USART_Mode)); - assert_param(IS_USART_HARDWARE_FLOW_CONTROL(USART_InitStruct->USART_HardwareFlowControl)); - - /* Disable USART */ - USARTx->CR1 &= (uint32_t)~((uint32_t)USART_CR1_UE); - - /*---------------------------- USART CR2 Configuration -----------------------*/ - tmpreg = USARTx->CR2; - /* Clear STOP[13:12] bits */ - tmpreg &= (uint32_t)~((uint32_t)USART_CR2_STOP); - - /* Configure the USART Stop Bits, Clock, CPOL, CPHA and LastBit ------------*/ - /* Set STOP[13:12] bits according to USART_StopBits value */ - tmpreg |= (uint32_t)USART_InitStruct->USART_StopBits; - - /* Write to USART CR2 */ - USARTx->CR2 = tmpreg; - - /*---------------------------- USART CR1 Configuration -----------------------*/ - tmpreg = USARTx->CR1; - /* Clear M, PCE, PS, TE and RE bits */ - tmpreg &= (uint32_t)~((uint32_t)CR1_CLEAR_MASK); - - /* Configure the USART Word Length, Parity and mode ----------------------- */ - /* Set the M bits according to USART_WordLength value */ - /* Set PCE and PS bits according to USART_Parity value */ - /* Set TE and RE bits according to USART_Mode value */ - tmpreg |= (uint32_t)USART_InitStruct->USART_WordLength | USART_InitStruct->USART_Parity | - USART_InitStruct->USART_Mode; - - /* Write to USART CR1 */ - USARTx->CR1 = tmpreg; - - /*---------------------------- USART CR3 Configuration -----------------------*/ - tmpreg = USARTx->CR3; - /* Clear CTSE and RTSE bits */ - tmpreg &= (uint32_t)~((uint32_t)CR3_CLEAR_MASK); - - /* Configure the USART HFC -------------------------------------------------*/ - /* Set CTSE and RTSE bits according to USART_HardwareFlowControl value */ - tmpreg |= USART_InitStruct->USART_HardwareFlowControl; - - /* Write to USART CR3 */ - USARTx->CR3 = tmpreg; - - /*---------------------------- USART BRR Configuration -----------------------*/ - /* Configure the USART Baud Rate -------------------------------------------*/ - RCC_GetClocksFreq(&RCC_ClocksStatus); - - if (USARTx == USART1) - { - apbclock = RCC_ClocksStatus.USART1CLK_Frequency; - } - else if (USARTx == USART2) - { - apbclock = RCC_ClocksStatus.USART2CLK_Frequency; - } - - /* Determine the integer part */ - if ((USARTx->CR1 & USART_CR1_OVER8) != 0) - { - /* (divider * 10) computing in case Oversampling mode is 8 Samples */ - divider = (uint32_t)((2 * apbclock) / (USART_InitStruct->USART_BaudRate)); - tmpreg = (uint32_t)((2 * apbclock) % (USART_InitStruct->USART_BaudRate)); - } - else /* if ((USARTx->CR1 & CR1_OVER8_Set) == 0) */ - { - /* (divider * 10) computing in case Oversampling mode is 16 Samples */ - divider = (uint32_t)((apbclock) / (USART_InitStruct->USART_BaudRate)); - tmpreg = (uint32_t)((apbclock) % (USART_InitStruct->USART_BaudRate)); - } - - /* round the divider : if fractional part i greater than 0.5 increment divider */ - if (tmpreg >= (USART_InitStruct->USART_BaudRate) / 2) - { - divider++; - } - - /* Implement the divider in case Oversampling mode is 8 Samples */ - if ((USARTx->CR1 & USART_CR1_OVER8) != 0) - { - /* get the LSB of divider and shift it to the right by 1 bit */ - tmpreg = (divider & (uint16_t)0x000F) >> 1; - - /* update the divider value */ - divider = (divider & (uint16_t)0xFFF0) | tmpreg; - } - - /* Write to USART BRR */ - USARTx->BRR = (uint16_t)divider; -} - -/** - * @brief Fills each USART_InitStruct member with its default value. - * @param USART_InitStruct: pointer to a USART_InitTypeDef structure - * which will be initialized. - * @retval None - */ -void USART_StructInit(USART_InitTypeDef* USART_InitStruct) -{ - /* USART_InitStruct members default value */ - USART_InitStruct->USART_BaudRate = 9600; - USART_InitStruct->USART_WordLength = USART_WordLength_8b; - USART_InitStruct->USART_StopBits = USART_StopBits_1; - USART_InitStruct->USART_Parity = USART_Parity_No ; - USART_InitStruct->USART_Mode = USART_Mode_Rx | USART_Mode_Tx; - USART_InitStruct->USART_HardwareFlowControl = USART_HardwareFlowControl_None; -} - -/** - * @brief Initializes the USARTx peripheral Clock according to the - * specified parameters in the USART_ClockInitStruct. - * @param USARTx: where x can be from 1 to 2 to select the USART peripheral. - * @param USART_ClockInitStruct: pointer to a USART_ClockInitTypeDef - * structure that contains the configuration information for the specified - * USART peripheral. - * @retval None - */ -void USART_ClockInit(USART_TypeDef* USARTx, USART_ClockInitTypeDef* USART_ClockInitStruct) -{ - uint32_t tmpreg = 0; - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_USART_CLOCK(USART_ClockInitStruct->USART_Clock)); - assert_param(IS_USART_CPOL(USART_ClockInitStruct->USART_CPOL)); - assert_param(IS_USART_CPHA(USART_ClockInitStruct->USART_CPHA)); - assert_param(IS_USART_LASTBIT(USART_ClockInitStruct->USART_LastBit)); -/*---------------------------- USART CR2 Configuration -----------------------*/ - tmpreg = USARTx->CR2; - /* Clear CLKEN, CPOL, CPHA, LBCL and SSM bits */ - tmpreg &= (uint32_t)~((uint32_t)CR2_CLOCK_CLEAR_MASK); - /* Configure the USART Clock, CPOL, CPHA, LastBit and SSM ------------*/ - /* Set CLKEN bit according to USART_Clock value */ - /* Set CPOL bit according to USART_CPOL value */ - /* Set CPHA bit according to USART_CPHA value */ - /* Set LBCL bit according to USART_LastBit value */ - tmpreg |= (uint32_t)(USART_ClockInitStruct->USART_Clock | USART_ClockInitStruct->USART_CPOL | - USART_ClockInitStruct->USART_CPHA | USART_ClockInitStruct->USART_LastBit); - /* Write to USART CR2 */ - USARTx->CR2 = tmpreg; -} - -/** - * @brief Fills each USART_ClockInitStruct member with its default value. - * @param USART_ClockInitStruct: pointer to a USART_ClockInitTypeDef - * structure which will be initialized. - * @retval None - */ -void USART_ClockStructInit(USART_ClockInitTypeDef* USART_ClockInitStruct) -{ - /* USART_ClockInitStruct members default value */ - USART_ClockInitStruct->USART_Clock = USART_Clock_Disable; - USART_ClockInitStruct->USART_CPOL = USART_CPOL_Low; - USART_ClockInitStruct->USART_CPHA = USART_CPHA_1Edge; - USART_ClockInitStruct->USART_LastBit = USART_LastBit_Disable; -} - -/** - * @brief Enables or disables the specified USART peripheral. - * @param USARTx: where x can be from 1 to 2 to select the USART peripheral. - * @param NewState: new state of the USARTx peripheral. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void USART_Cmd(USART_TypeDef* USARTx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the selected USART by setting the UE bit in the CR1 register */ - USARTx->CR1 |= USART_CR1_UE; - } - else - { - /* Disable the selected USART by clearing the UE bit in the CR1 register */ - USARTx->CR1 &= (uint32_t)~((uint32_t)USART_CR1_UE); - } -} - -/** - * @brief Enables or disables the USART's transmitter or receiver. - * @param USARTx: where x can be from 1 to 2 to select the USART peripheral. - * @param USART_Direction: specifies the USART direction. - * This parameter can be any combination of the following values: - * @arg USART_Mode_Tx: USART Transmitter - * @arg USART_Mode_Rx: USART Receiver - * @param NewState: new state of the USART transfer direction. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void USART_DirectionModeCmd(USART_TypeDef* USARTx, uint32_t USART_DirectionMode, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_USART_MODE(USART_DirectionMode)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the USART's transfer interface by setting the TE and/or RE bits - in the USART CR1 register */ - USARTx->CR1 |= USART_DirectionMode; - } - else - { - /* Disable the USART's transfer interface by clearing the TE and/or RE bits - in the USART CR3 register */ - USARTx->CR1 &= (uint32_t)~USART_DirectionMode; - } -} - -/** - * @brief Enables or disables the USART's 8x oversampling mode. - * @param USARTx: where x can be from 1 to 2 to select the USART peripheral. - * @param NewState: new state of the USART 8x oversampling mode. - * This parameter can be: ENABLE or DISABLE. - * @note This function has to be called before calling USART_Init() function - * in order to have correct baudrate Divider value. - * @retval None - */ -void USART_OverSampling8Cmd(USART_TypeDef* USARTx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the 8x Oversampling mode by setting the OVER8 bit in the CR1 register */ - USARTx->CR1 |= USART_CR1_OVER8; - } - else - { - /* Disable the 8x Oversampling mode by clearing the OVER8 bit in the CR1 register */ - USARTx->CR1 &= (uint32_t)~((uint32_t)USART_CR1_OVER8); - } -} - -/** - * @brief Enables or disables the USART's one bit sampling method. - * @param USARTx: where x can be from 1 to 2 to select the USART peripheral. - * @param NewState: new state of the USART one bit sampling method. - * This parameter can be: ENABLE or DISABLE. - * @note This function has to be called before calling USART_Cmd() function. - * @retval None - */ -void USART_OneBitMethodCmd(USART_TypeDef* USARTx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the one bit method by setting the ONEBITE bit in the CR3 register */ - USARTx->CR3 |= USART_CR3_ONEBIT; - } - else - { - /* Disable the one bit method by clearing the ONEBITE bit in the CR3 register */ - USARTx->CR3 &= (uint32_t)~((uint32_t)USART_CR3_ONEBIT); - } -} - -/** - * @brief Enables or disables the USART's most significant bit first - * transmitted/received following the start bit. - * @param USARTx: where x can be from 1 to 2 to select the USART peripheral. - * @param NewState: new state of the USART most significant bit first - * transmitted/received following the start bit. - * This parameter can be: ENABLE or DISABLE. - * @note This function has to be called before calling USART_Cmd() function. - * @retval None - */ -void USART_MSBFirstCmd(USART_TypeDef* USARTx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the most significant bit first transmitted/received following the - start bit by setting the MSBFIRST bit in the CR2 register */ - USARTx->CR2 |= USART_CR2_MSBFIRST; - } - else - { - /* Disable the most significant bit first transmitted/received following the - start bit by clearing the MSBFIRST bit in the CR2 register */ - USARTx->CR2 &= (uint32_t)~((uint32_t)USART_CR2_MSBFIRST); - } -} - -/** - * @brief Enables or disables the binary data inversion. - * @param USARTx: where x can be from 1 to 2 to select the USART peripheral. - * @param NewState: new defined levels for the USART data. - * This parameter can be: - * @arg ENABLE: Logical data from the data register are send/received in negative - * logic (1=L, 0=H). The parity bit is also inverted. - * @arg DISABLE: Logical data from the data register are send/received in positive - * logic (1=H, 0=L) - * @note This function has to be called before calling USART_Cmd() function. - * @retval None - */ -void USART_DataInvCmd(USART_TypeDef* USARTx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the binary data inversion feature by setting the DATAINV bit in - the CR2 register */ - USARTx->CR2 |= USART_CR2_DATAINV; - } - else - { - /* Disable the binary data inversion feature by clearing the DATAINV bit in - the CR2 register */ - USARTx->CR2 &= (uint32_t)~((uint32_t)USART_CR2_DATAINV); - } -} - -/** - * @brief Enables or disables the Pin(s) active level inversion. - * @param USARTx: where x can be from 1 to 2 to select the USART peripheral. - * @param USART_InvPin: specifies the USART pin(s) to invert. - * This parameter can be any combination of the following values: - * @arg USART_InvPin_Tx: USART Tx pin active level inversion. - * @arg USART_InvPin_Rx: USART Rx pin active level inversion. - * @param NewState: new active level status for the USART pin(s). - * This parameter can be: - * @arg ENABLE: pin(s) signal values are inverted (Vdd =0, Gnd =1). - * @arg DISABLE: pin(s) signal works using the standard logic levels (Vdd =1, Gnd =0). - * @note This function has to be called before calling USART_Cmd() function. - * @retval None - */ -void USART_InvPinCmd(USART_TypeDef* USARTx, uint32_t USART_InvPin, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_USART_INVERSTION_PIN(USART_InvPin)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the active level inversion for selected pins by setting the TXINV - and/or RXINV bits in the USART CR2 register */ - USARTx->CR2 |= USART_InvPin; - } - else - { - /* Disable the active level inversion for selected requests by clearing the - TXINV and/or RXINV bits in the USART CR2 register */ - USARTx->CR2 &= (uint32_t)~USART_InvPin; - } -} - -/** - * @brief Enables or disables the swap Tx/Rx pins. - * @param USARTx: where x can be from 1 to 2 to select the USART peripheral. - * @param NewState: new state of the USARTx TX/RX pins pinout. - * This parameter can be: - * @arg ENABLE: The TX and RX pins functions are swapped. - * @arg DISABLE: TX/RX pins are used as defined in standard pinout - * @note This function has to be called before calling USART_Cmd() function. - * @retval None - */ -void USART_SWAPPinCmd(USART_TypeDef* USARTx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the SWAP feature by setting the SWAP bit in the CR2 register */ - USARTx->CR2 |= USART_CR2_SWAP; - } - else - { - /* Disable the SWAP feature by clearing the SWAP bit in the CR2 register */ - USARTx->CR2 &= (uint32_t)~((uint32_t)USART_CR2_SWAP); - } -} - -/** - * @brief Enables or disables the receiver Time Out feature. - * @param USARTx: where x can be 1, 2 to select the USART peripheral. - * @param NewState: new state of the USARTx receiver Time Out. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void USART_ReceiverTimeOutCmd(USART_TypeDef* USARTx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_USART_123_PERIPH(USARTx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the receiver time out feature by setting the RTOEN bit in the CR2 - register */ - USARTx->CR2 |= USART_CR2_RTOEN; - } - else - { - /* Disable the receiver time out feature by clearing the RTOEN bit in the CR2 - register */ - USARTx->CR2 &= (uint32_t)~((uint32_t)USART_CR2_RTOEN); - } -} - -/** - * @brief Sets the receiver Time Out value. - * @param USARTx: where x can be 1, 2 to select the USART peripheral. - * @param USART_ReceiverTimeOut: specifies the Receiver Time Out value. - * @retval None - */ -void USART_SetReceiverTimeOut(USART_TypeDef* USARTx, uint32_t USART_ReceiverTimeOut) -{ - /* Check the parameters */ - assert_param(IS_USART_123_PERIPH(USARTx)); - assert_param(IS_USART_TIMEOUT(USART_ReceiverTimeOut)); - - /* Clear the receiver Time Out value by clearing the RTO[23:0] bits in the RTOR - register */ - USARTx->RTOR &= (uint32_t)~((uint32_t)USART_RTOR_RTO); - /* Set the receiver Time Out value by setting the RTO[23:0] bits in the RTOR - register */ - USARTx->RTOR |= USART_ReceiverTimeOut; -} -/** - * @} - */ -/** - * @brief Enables or disables the Auto Baud Rate. - * @param USARTx: where x can be 1or 2 to select the USART peripheral. - * @param NewState: new state of the USARTx auto baud rate. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void USART_AutoBaudRateCmd(USART_TypeDef* USARTx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_USART_123_PERIPH(USARTx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the auto baud rate feature by setting the ABREN bit in the CR2 - register */ - USARTx->CR2 |= USART_CR2_ABREN; - } - else - { - /* Disable the auto baud rate feature by clearing the ABREN bit in the CR2 - register */ - USARTx->CR2 &= (uint32_t)~((uint32_t)USART_CR2_ABREN); - } -} - -/** - * @brief Selects the USART auto baud rate method. - * @param USARTx: where x can be 1or 2 to select the USART peripheral. - * @param USART_AutoBaudRate: specifies the selected USART auto baud rate method. - * This parameter can be one of the following values: - * @arg USART_AutoBaudRate_StartBit: Start Bit duration measurement. - * @arg USART_AutoBaudRate_FallingEdge: Falling edge to falling edge measurement. - * @note This function has to be called before calling USART_Cmd() function. - * @retval None - */ -void USART_AutoBaudRateConfig(USART_TypeDef* USARTx, uint32_t USART_AutoBaudRate) -{ - /* Check the parameters */ - assert_param(IS_USART_123_PERIPH(USARTx)); - assert_param(IS_USART_AUTOBAUDRATE_MODE(USART_AutoBaudRate)); - - USARTx->CR2 &= (uint32_t)~((uint32_t)USART_CR2_ABRMODE); - USARTx->CR2 |= USART_AutoBaudRate; -} - -/** - * @} - */ -/** - * @brief Transmits single data through the USARTx peripheral. - * @param USARTx: where x can be from 1 to 2 to select the USART peripheral. - * @param Data: the data to transmit. - * @retval None - */ -void USART_SendData(USART_TypeDef* USARTx, uint16_t Data) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_USART_DATA(Data)); - - /* Transmit Data */ - USARTx->TDR = (Data & (uint16_t)0x01FF); -} - -/** - * @brief Returns the most recent received data by the USARTx peripheral. - * @param USARTx: where x can be from 1 to 2 to select the USART peripheral. - * @retval The received data. - */ -uint16_t USART_ReceiveData(USART_TypeDef* USARTx) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - - /* Receive Data */ - return (uint16_t)(USARTx->RDR & (uint16_t)0x01FF); -} - -/** - * @} - */ -/** - * @brief Sets the address of the USART node. - * @param USARTx: where x can be from 1 to 2 to select the USART peripheral. - * @param USART_Address: Indicates the address of the USART node. - * @retval None - */ -void USART_SetAddress(USART_TypeDef* USARTx, uint8_t USART_Address) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - - /* Clear the USART address */ - USARTx->CR2 &= (uint32_t)~((uint32_t)USART_CR2_ADD); - /* Set the USART address node */ - USARTx->CR2 |=((uint32_t)USART_Address << (uint32_t)0x18); -} - -/** - * @brief Enables or disables the USART's mute mode. - * @param USARTx: where x can be from 1 to 2 to select the USART peripheral. - * @param NewState: new state of the USART mute mode. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void USART_MuteModeCmd(USART_TypeDef* USARTx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the USART mute mode by setting the MME bit in the CR1 register */ - USARTx->CR1 |= USART_CR1_MME; - } - else - { - /* Disable the USART mute mode by clearing the MME bit in the CR1 register */ - USARTx->CR1 &= (uint32_t)~((uint32_t)USART_CR1_MME); - } -} - -/** - * @brief Selects the USART WakeUp method from mute mode. - * @param USARTx: where x can be from 1 to 2 to select the USART peripheral. - * @param USART_WakeUp: specifies the USART wakeup method. - * This parameter can be one of the following values: - * @arg USART_WakeUp_IdleLine: WakeUp by an idle line detection - * @arg USART_WakeUp_AddressMark: WakeUp by an address mark - * @retval None - */ -void USART_MuteModeWakeUpConfig(USART_TypeDef* USARTx, uint32_t USART_WakeUp) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_USART_MUTEMODE_WAKEUP(USART_WakeUp)); - - USARTx->CR1 &= (uint32_t)~((uint32_t)USART_CR1_WAKE); - USARTx->CR1 |= USART_WakeUp; -} - -/** - * @brief Configure the the USART Address detection length. - * @param USARTx: where x can be from 1 to 2 to select the USART peripheral. - * @param USART_AddressLength: specifies the USART address length detection. - * This parameter can be one of the following values: - * @arg USART_AddressLength_4b: 4-bit address length detection - * @arg USART_AddressLength_7b: 7-bit address length detection - * @retval None - */ -void USART_AddressDetectionConfig(USART_TypeDef* USARTx, uint32_t USART_AddressLength) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_USART_ADDRESS_DETECTION(USART_AddressLength)); - - USARTx->CR2 &= (uint32_t)~((uint32_t)USART_CR2_ADDM7); - USARTx->CR2 |= USART_AddressLength; -} - -/** - * @} - */ -/** - * @brief Enables or disables the USART's Half Duplex communication. - * @param USARTx: where x can be from 1 to 2 to select the USART peripheral. - * @param NewState: new state of the USART Communication. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void USART_HalfDuplexCmd(USART_TypeDef* USARTx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the Half-Duplex mode by setting the HDSEL bit in the CR3 register */ - USARTx->CR3 |= USART_CR3_HDSEL; - } - else - { - /* Disable the Half-Duplex mode by clearing the HDSEL bit in the CR3 register */ - USARTx->CR3 &= (uint32_t)~((uint32_t)USART_CR3_HDSEL); - } -} - -/** - * @} - */ -/** - * @brief Enables or disables the USART's DE functionality. - * @param USARTx: where x can be from 1 to 8 to select the USART peripheral. - * @param NewState: new state of the driver enable mode. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void USART_DECmd(USART_TypeDef* USARTx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the DE functionality by setting the DEM bit in the CR3 register */ - USARTx->CR3 |= USART_CR3_DEM; - } - else - { - /* Disable the DE functionality by clearing the DEM bit in the CR3 register */ - USARTx->CR3 &= (uint32_t)~((uint32_t)USART_CR3_DEM); - } -} - -/** - * @brief Configures the USART's DE polarity - * @param USARTx: where x can be from 1 to 8 to select the USART peripheral. - * @param USART_DEPolarity: specifies the DE polarity. - * This parameter can be one of the following values: - * @arg USART_DEPolarity_Low - * @arg USART_DEPolarity_High - * @retval None - */ -void USART_DEPolarityConfig(USART_TypeDef* USARTx, uint32_t USART_DEPolarity) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_USART_DE_POLARITY(USART_DEPolarity)); - - USARTx->CR3 &= (uint32_t)~((uint32_t)USART_CR3_DEP); - USARTx->CR3 |= USART_DEPolarity; -} - -/** - * @brief Sets the specified RS485 DE assertion time - * @param USARTx: where x can be from 1 to 8 to select the USART peripheral. - * @param USART_DEAssertionTime: specifies the time between the activation of - * the DE signal and the beginning of the start bit - * @retval None - */ -void USART_SetDEAssertionTime(USART_TypeDef* USARTx, uint32_t USART_DEAssertionTime) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_USART_DE_ASSERTION_DEASSERTION_TIME(USART_DEAssertionTime)); - - /* Clear the DE assertion time */ - USARTx->CR1 &= (uint32_t)~((uint32_t)USART_CR1_DEAT); - /* Set the new value for the DE assertion time */ - USARTx->CR1 |=((uint32_t)USART_DEAssertionTime << (uint32_t)0x15); -} - -/** - * @brief Sets the specified RS485 DE deassertion time - * @param USARTx: where x can be from 1 to 8 to select the USART peripheral. - * @param USART_DeassertionTime: specifies the time between the middle of the last - * stop bit in a transmitted message and the de-activation of the DE signal - * @retval None - */ -void USART_SetDEDeassertionTime(USART_TypeDef* USARTx, uint32_t USART_DEDeassertionTime) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_USART_DE_ASSERTION_DEASSERTION_TIME(USART_DEDeassertionTime)); - - /* Clear the DE deassertion time */ - USARTx->CR1 &= (uint32_t)~((uint32_t)USART_CR1_DEDT); - /* Set the new value for the DE deassertion time */ - USARTx->CR1 |=((uint32_t)USART_DEDeassertionTime << (uint32_t)0x10); -} - -/** - * @} - */ - -/** - * @brief Enables or disables the USART's DMA interface. - * @param USARTx: where x can be from 1 to 8 to select the USART peripheral. - * @param USART_DMAReq: specifies the DMA request. - * This parameter can be any combination of the following values: - * @arg USART_DMAReq_Tx: USART DMA transmit request - * @arg USART_DMAReq_Rx: USART DMA receive request - * @param NewState: new state of the DMA Request sources. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void USART_DMACmd(USART_TypeDef* USARTx, uint32_t USART_DMAReq, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_USART_DMAREQ(USART_DMAReq)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the DMA transfer for selected requests by setting the DMAT and/or - DMAR bits in the USART CR3 register */ - USARTx->CR3 |= USART_DMAReq; - } - else - { - /* Disable the DMA transfer for selected requests by clearing the DMAT and/or - DMAR bits in the USART CR3 register */ - USARTx->CR3 &= (uint32_t)~USART_DMAReq; - } -} - -/** - * @brief Enables or disables the USART's DMA interface when reception error occurs. - * @param USARTx: where x can be from 1 to 8 to select the USART peripheral. - * @param USART_DMAOnError: specifies the DMA status in case of reception error. - * This parameter can be any combination of the following values: - * @arg USART_DMAOnError_Enable: DMA receive request enabled when the USART DMA - * reception error is asserted. - * @arg USART_DMAOnError_Disable: DMA receive request disabled when the USART DMA - * reception error is asserted. - * @retval None - */ -void USART_DMAReceptionErrorConfig(USART_TypeDef* USARTx, uint32_t USART_DMAOnError) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_USART_DMAONERROR(USART_DMAOnError)); - - /* Clear the DMA Reception error detection bit */ - USARTx->CR3 &= (uint32_t)~((uint32_t)USART_CR3_DDRE); - /* Set the new value for the DMA Reception error detection bit */ - USARTx->CR3 |= USART_DMAOnError; -} - -/** - * @} - */ -/** - * @brief Enables or disables the specified USART interrupts. - * @param USARTx: where x can be from 1 to 2 to select the USART peripheral. - * @param USART_IT: specifies the USART interrupt sources to be enabled or disabled. - * This parameter can be one of the following values: - * @arg USART_IT_WU: Wake up interrupt - * @arg USART_IT_CM: Character match interrupt. - * @arg USART_IT_EOB: End of block interrupt - * @arg USART_IT_RTO: Receive time out interrupt. - * @arg USART_IT_CTS: CTS change interrupt. - * @arg USART_IT_LBD: LIN Break detection interrupt - * @arg USART_IT_TXE: Tansmit Data Register empty interrupt. - * @arg USART_IT_TC: Transmission complete interrupt. - * @arg USART_IT_RXNE: Receive Data register not empty interrupt. - * @arg USART_IT_IDLE: Idle line detection interrupt. - * @arg USART_IT_PE: Parity Error interrupt. - * @arg USART_IT_ERR: Error interrupt(Frame error, noise error, overrun error) - * @param NewState: new state of the specified USARTx interrupts. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void USART_ITConfig(USART_TypeDef* USARTx, uint32_t USART_IT, FunctionalState NewState) -{ - uint32_t usartreg = 0, itpos = 0, itmask = 0; - uint32_t usartxbase = 0; - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_USART_CONFIG_IT(USART_IT)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - usartxbase = (uint32_t)USARTx; - - /* Get the USART register index */ - usartreg = (((uint16_t)USART_IT) >> 0x08); - - /* Get the interrupt position */ - itpos = USART_IT & IT_MASK; - itmask = (((uint32_t)0x01) << itpos); - - if (usartreg == 0x02) /* The IT is in CR2 register */ - { - usartxbase += 0x04; - } - else if (usartreg == 0x03) /* The IT is in CR3 register */ - { - usartxbase += 0x08; - } - else /* The IT is in CR1 register */ - { - } - if (NewState != DISABLE) - { - *(__IO uint32_t*)usartxbase |= itmask; - } - else - { - *(__IO uint32_t*)usartxbase &= ~itmask; - } -} - -/** - * @brief Enables the specified USART's Request. - * @param USARTx: where x can be from 1 to 2 to select the USART peripheral. - * @param USART_Request: specifies the USART request. - * This parameter can be any combination of the following values: - * @arg USART_Request_TXFRQ: Transmit data flush ReQuest - * @arg USART_Request_RXFRQ: Receive data flush ReQuest - * @arg USART_Request_MMRQ: Mute Mode ReQuest - * @arg USART_Request_SBKRQ: Send Break ReQuest - * @arg USART_Request_ABRRQ: Auto Baud Rate ReQuest - * @param NewState: new state of the DMA interface when reception error occurs. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void USART_RequestCmd(USART_TypeDef* USARTx, uint32_t USART_Request, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_USART_REQUEST(USART_Request)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the USART ReQuest by setting the dedicated request bit in the RQR - register.*/ - USARTx->RQR |= USART_Request; - } - else - { - /* Disable the USART ReQuest by clearing the dedicated request bit in the RQR - register.*/ - USARTx->RQR &= (uint32_t)~USART_Request; - } -} - -/** - * @brief Enables or disables the USART's Overrun detection. - * @param USARTx: where x can be from 1 to 2 to select the USART peripheral. - * @param USART_OVRDetection: specifies the OVR detection status in case of OVR error. - * This parameter can be any combination of the following values: - * @arg USART_OVRDetection_Enable: OVR error detection enabled when - * the USART OVR error is asserted. - * @arg USART_OVRDetection_Disable: OVR error detection disabled when - * the USART OVR error is asserted. - * @retval None - */ -void USART_OverrunDetectionConfig(USART_TypeDef* USARTx, uint32_t USART_OVRDetection) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_USART_OVRDETECTION(USART_OVRDetection)); - - /* Clear the OVR detection bit */ - USARTx->CR3 &= (uint32_t)~((uint32_t)USART_CR3_OVRDIS); - /* Set the new value for the OVR detection bit */ - USARTx->CR3 |= USART_OVRDetection; -} - -/** - * @brief Checks whether the specified USART flag is set or not. - * @param USARTx: where x can be from 1 to 2 to select the USART peripheral.. - * @param USART_FLAG: specifies the flag to check. - * This parameter can be one of the following values: - * @arg USART_FLAG_REACK: Receive Enable acknowledge flag. - * @arg USART_FLAG_TEACK: Transmit Enable acknowledge flag. - * @arg USART_FLAG_WU: Wake up flag - * @arg USART_FLAG_RWU: Receive Wake up flag - * @arg USART_FLAG_SBK: Send Break flag. - * @arg USART_FLAG_CM: Character match flag. - * @arg USART_FLAG_BUSY: Busy flag. - * @arg USART_FLAG_ABRF: Auto baud rate flag. - * @arg USART_FLAG_ABRE: Auto baud rate error flag. - * @arg USART_FLAG_EOB: End of block flag - * @arg USART_FLAG_RTO: Receive time out flag. - * @arg USART_FLAG_nCTSS: Inverted nCTS input bit status. - * @arg USART_FLAG_CTS: CTS Change flag. - * @arg USART_FLAG_LBD: LIN Break detection flag - * @arg USART_FLAG_TXE: Transmit data register empty flag. - * @arg USART_FLAG_TC: Transmission Complete flag. - * @arg USART_FLAG_RXNE: Receive data register not empty flag. - * @arg USART_FLAG_IDLE: Idle Line detection flag. - * @arg USART_FLAG_ORE: OverRun Error flag. - * @arg USART_FLAG_NE: Noise Error flag. - * @arg USART_FLAG_FE: Framing Error flag. - * @arg USART_FLAG_PE: Parity Error flag. - * @retval The new state of USART_FLAG (SET or RESET). - */ -FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, uint32_t USART_FLAG) -{ - FlagStatus bitstatus = RESET; - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_USART_FLAG(USART_FLAG)); - - if ((USARTx->ISR & USART_FLAG) != (uint16_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - return bitstatus; -} - -/** - * @brief Clears the USARTx's pending flags. - * @param USARTx: where x can be from 1 to 2 to select the USART peripheral. - * @param USART_FLAG: specifies the flag to clear. - * This parameter can be any combination of the following values: - * @arg USART_FLAG_WU: Wake up flag - * @arg USART_FLAG_CM: Character match flag. - * @arg USART_FLAG_EOB: End of block flag - * @arg USART_FLAG_RTO: Receive time out flag. - * @arg USART_FLAG_CTS: CTS Change flag. - * @arg USART_FLAG_LBD: LIN Break detection flag - * @arg USART_FLAG_TC: Transmission Complete flag. - * @arg USART_FLAG_IDLE: IDLE line detected flag. - * @arg USART_FLAG_ORE: OverRun Error flag. - * @arg USART_FLAG_NE: Noise Error flag. - * @arg USART_FLAG_FE: Framing Error flag. - * @arg USART_FLAG_PE: Parity Errorflag. - * - * @note RXNE pending bit is cleared by a read to the USART_RDR register - * (USART_ReceiveData()) or by writing 1 to the RXFRQ in the register - * USART_RQR (USART_RequestCmd()). - * @note TC flag can be also cleared by software sequence: a read operation - * to USART_SR register (USART_GetFlagStatus()) followed by a write - * operation to USART_TDR register (USART_SendData()). - * @note TXE flag is cleared by a write to the USART_TDR register (USART_SendData()) - * or by writing 1 to the TXFRQ in the register USART_RQR (USART_RequestCmd()). - * @note SBKF flag is cleared by 1 to the SBKRQ in the register USART_RQR - * (USART_RequestCmd()). - * @retval None - */ -void USART_ClearFlag(USART_TypeDef* USARTx, uint32_t USART_FLAG) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_USART_CLEAR_FLAG(USART_FLAG)); - - USARTx->ICR = USART_FLAG; -} - -/** - * @brief Checks whether the specified USART interrupt has occurred or not. - * @param USARTx: where x can be from 1 to 2 to select the USART peripheral. - * @param USART_IT: specifies the USART interrupt source to check. - * This parameter can be one of the following values: - * @arg USART_IT_WU: Wake up interrupt - * @arg USART_IT_CM: Character match interrupt. - * @arg USART_IT_EOB: End of block interrupt - * @arg USART_IT_RTO: Receive time out interrupt. - * @arg USART_IT_CTS: CTS change interrupt. - * @arg USART_IT_LBD: LIN Break detection interrupt - * @arg USART_IT_TXE: Tansmit Data Register empty interrupt. - * @arg USART_IT_TC: Transmission complete interrupt. - * @arg USART_IT_RXNE: Receive Data register not empty interrupt. - * @arg USART_IT_IDLE: Idle line detection interrupt. - * @arg USART_IT_ORE: OverRun Error interrupt. - * @arg USART_IT_NE: Noise Error interrupt. - * @arg USART_IT_FE: Framing Error interrupt. - * @arg USART_IT_PE: Parity Error interrupt. - * @retval The new state of USART_IT (SET or RESET). - */ -ITStatus USART_GetITStatus(USART_TypeDef* USARTx, uint32_t USART_IT) -{ - uint32_t bitpos = 0, itmask = 0, usartreg = 0; - ITStatus bitstatus = RESET; - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_USART_GET_IT(USART_IT)); - - /* Get the USART register index */ - usartreg = (((uint16_t)USART_IT) >> 0x08); - /* Get the interrupt position */ - itmask = USART_IT & IT_MASK; - itmask = (uint32_t)0x01 << itmask; - - if (usartreg == 0x01) /* The IT is in CR1 register */ - { - itmask &= USARTx->CR1; - } - else if (usartreg == 0x02) /* The IT is in CR2 register */ - { - itmask &= USARTx->CR2; - } - else /* The IT is in CR3 register */ - { - itmask &= USARTx->CR3; - } - - bitpos = USART_IT >> 0x10; - bitpos = (uint32_t)0x01 << bitpos; - bitpos &= USARTx->ISR; - if ((itmask != (uint16_t)RESET)&&(bitpos != (uint16_t)RESET)) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - - return bitstatus; -} - -/** - * @brief Clears the USARTx's interrupt pending bits. - * @param USARTx: where x can be from 1 to 2 to select the USART peripheral. - * @param USART_IT: specifies the interrupt pending bit to clear. - * This parameter can be one of the following values: - * @arg USART_IT_WU: Wake up interrupt - * @arg USART_IT_CM: Character match interrupt. - * @arg USART_IT_EOB: End of block interrupt - * @arg USART_IT_RTO: Receive time out interrupt. - * @arg USART_IT_CTS: CTS change interrupt. - * @arg USART_IT_LBD: LIN Break detection interrupt - * @arg USART_IT_TC: Transmission complete interrupt. - * @arg USART_IT_IDLE: IDLE line detected interrupt. - * @arg USART_IT_ORE: OverRun Error interrupt. - * @arg USART_IT_NE: Noise Error interrupt. - * @arg USART_IT_FE: Framing Error interrupt. - * @arg USART_IT_PE: Parity Error interrupt. - * - * @note RXNE pending bit is cleared by a read to the USART_RDR register - * (USART_ReceiveData()) or by writing 1 to the RXFRQ in the register - * USART_RQR (USART_RequestCmd()). - * @note TC pending bit can be also cleared by software sequence: a read - * operation to USART_SR register (USART_GetITStatus()) followed by - * a write operation to USART_TDR register (USART_SendData()). - * @note TXE pending bit is cleared by a write to the USART_TDR register - * (USART_SendData()) or by writing 1 to the TXFRQ in the register - * USART_RQR (USART_RequestCmd()). - * @retval None - */ -void USART_ClearITPendingBit(USART_TypeDef* USARTx, uint32_t USART_IT) -{ - uint32_t bitpos = 0, itmask = 0; - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_USART_CLEAR_IT(USART_IT)); - - bitpos = USART_IT >> 0x10; - itmask = ((uint32_t)0x01 << (uint32_t)bitpos); - USARTx->ICR = (uint32_t)itmask; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT FMD *****END OF FILE****/ diff --git a/bsp/ft32/libraries/FT32F0xx/FT32F0xx_Driver/Src/ft32f0xx_wwdg.c b/bsp/ft32/libraries/FT32F0xx/FT32F0xx_Driver/Src/ft32f0xx_wwdg.c deleted file mode 100644 index cbef31c8ee5..00000000000 --- a/bsp/ft32/libraries/FT32F0xx/FT32F0xx_Driver/Src/ft32f0xx_wwdg.c +++ /dev/null @@ -1,177 +0,0 @@ -/** - ****************************************************************************** - * @file ft32f0xx_wwdg.c - * @author FMD AE - * @brief This file provides firmware functions to manage the following - * functionalities of the Window watchdog (WWDG) peripheral: - * + Prescaler, Refresh window and Counter configuration - * + WWDG activation - * + Interrupts and flags management - * @version V1.0.0 - * @data 2021-07-01 - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "ft32f0xx_wwdg.h" -#include "ft32f0xx_rcc.h" -/* --------------------- WWDG registers bit mask ---------------------------- */ -/* CFR register bit mask */ -#define CFR_WDGTB_MASK ((uint32_t)0xFFFFFE7F) -#define CFR_W_MASK ((uint32_t)0xFFFFFF80) -#define BIT_MASK ((uint8_t)0x7F) - - -/** - * @brief Deinitializes the WWDG peripheral registers to their default reset values. - * @param None - * @retval None - */ -void WWDG_DeInit(void) -{ - RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, DISABLE); -} - -/** - * @brief Sets the WWDG Prescaler. - * @param WWDG_Prescaler: specifies the WWDG Prescaler. - * This parameter can be one of the following values: - * @arg WWDG_Prescaler_1: WWDG counter clock = (PCLK1/4096)/1 - * @arg WWDG_Prescaler_2: WWDG counter clock = (PCLK1/4096)/2 - * @arg WWDG_Prescaler_4: WWDG counter clock = (PCLK1/4096)/4 - * @arg WWDG_Prescaler_8: WWDG counter clock = (PCLK1/4096)/8 - * @retval None - */ -void WWDG_SetPrescaler(uint32_t WWDG_Prescaler) -{ - uint32_t tmpreg = 0; - /* Check the parameters */ - assert_param(IS_WWDG_PRESCALER(WWDG_Prescaler)); - /* Clear WDGTB[1:0] bits */ - tmpreg = WWDG->CFR & CFR_WDGTB_MASK; - /* Set WDGTB[1:0] bits according to WWDG_Prescaler value */ - tmpreg |= WWDG_Prescaler; - /* Store the new value */ - WWDG->CFR = tmpreg; -} - -/** - * @brief Sets the WWDG window value. - * @param WindowValue: specifies the window value to be compared to the downcounter. - * This parameter value must be lower than 0x80. - * @retval None - */ -void WWDG_SetWindowValue(uint8_t WindowValue) -{ - __IO uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_WWDG_WINDOW_VALUE(WindowValue)); - /* Clear W[6:0] bits */ - - tmpreg = WWDG->CFR & CFR_W_MASK; - - /* Set W[6:0] bits according to WindowValue value */ - tmpreg |= WindowValue & (uint32_t) BIT_MASK; - - /* Store the new value */ - WWDG->CFR = tmpreg; -} - -/** - * @brief Enables the WWDG Early Wakeup interrupt(EWI). - * @note Once enabled this interrupt cannot be disabled except by a system reset. - * @param None - * @retval None - */ -void WWDG_EnableIT(void) -{ - WWDG->CFR |= WWDG_CFR_EWI; -} - -/** - * @brief Sets the WWDG counter value. - * @param Counter: specifies the watchdog counter value. - * This parameter must be a number between 0x40 and 0x7F (to prevent - * generating an immediate reset). - * @retval None - */ -void WWDG_SetCounter(uint8_t Counter) -{ - /* Check the parameters */ - assert_param(IS_WWDG_COUNTER(Counter)); - /* Write to T[6:0] bits to configure the counter value, no need to do - a read-modify-write; writing a 0 to WDGA bit does nothing */ - WWDG->CR = Counter & BIT_MASK; -} - -/** - * @} - */ - -/** - * @brief Enables WWDG and load the counter value. - * @param Counter: specifies the watchdog counter value. - * This parameter must be a number between 0x40 and 0x7F (to prevent - * generating an immediate reset). - * @retval None - */ -void WWDG_Enable(uint8_t Counter) -{ - /* Check the parameters */ - assert_param(IS_WWDG_COUNTER(Counter)); - WWDG->CR = WWDG_CR_WDGA | Counter; -} - -/** - * @} - */ - -/** - * @brief Checks whether the Early Wakeup interrupt flag is set or not. - * @param None - * @retval The new state of the Early Wakeup interrupt flag (SET or RESET). - */ -FlagStatus WWDG_GetFlagStatus(void) -{ - FlagStatus bitstatus = RESET; - - if ((WWDG->SR) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - return bitstatus; -} - -/** - * @brief Clears Early Wakeup interrupt flag. - * @param None - * @retval None - */ -void WWDG_ClearFlag(void) -{ - WWDG->SR = (uint32_t)RESET; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT FMD *****END OF FILE****/ diff --git a/bsp/ft32/libraries/FT32F0xx/FT32F0xx_Driver/templates/Inc/ft32f0xx_conf.h b/bsp/ft32/libraries/FT32F0xx/FT32F0xx_Driver/templates/Inc/ft32f0xx_conf.h deleted file mode 100644 index b1f0947868a..00000000000 --- a/bsp/ft32/libraries/FT32F0xx/FT32F0xx_Driver/templates/Inc/ft32f0xx_conf.h +++ /dev/null @@ -1,132 +0,0 @@ -/** - ****************************************************************************** - * @file ft32f0xx_conf.h - * @author FMD-AE - * @version V1.0.0 - * @date 2021-8-2 - * @brief Library configuration file. - ****************************************************************************** -*/ - -#ifndef __FT32F030XX_CONF_H -#define __FT32F030XX_CONF_H - -#ifdef _RTE_ -#include "RTE_Components.h" /* Component selection */ -#endif - -#ifdef __cplusplus - extern "C" { -#endif - -#ifdef RTE_DEVICE_ADC -#include "ft32f0xx_adc.h" -#endif /*RTE_DEVICE_ADC*/ - -#ifdef RTE_DEVICE_COMP -#include "ft32f0xx_comp.h" -#endif /*RTE_DEVICE_COMP*/ - -#ifdef RTE_DEVICE_CRC -#include "ft32f0xx_crc.h" -#endif /*RTE_DEVICE_CRC*/ - -#ifdef RTE_DEVICE_CRS -#include "ft32f0xx_crs.h" -#endif /*RTE_DEVICE_CRS*/ - -#ifdef RTE_DEVICE_DAC -#include "ft32f0xx_dac.h" -#endif /*RTE_DEVICE_DAC*/ - -#ifdef RTE_DEVICE_DMA -#include "ft32f0xx_dma.h" -#endif /*RTE_DEVICE_DMA*/ - -#ifdef RTE_DEVICE_DBGMCU -#include "ft32f0xx_debug.h" -#endif /*RTE_DEVICE_DBGMCU*/ - -#ifdef RTE_DEVICE_EXTI -#include "ft32f0xx_exti.h" -#endif /*RTE_DEVICE_EXTI*/ - -#ifdef RTE_DEVICE_FLASH -#include "ft32f0xx_flash.h" -#endif /*RTE_DEVICE_FLASH*/ - -#ifdef RTE_DEVICE_GPIO -#include "ft32f0xx_gpio.h" -#endif /*RTE_DEVICE_GPIO*/ - -#ifdef RTE_DEVICE_I2C -#include "ft32f0xx_i2c.h" -#endif /*RTE_DEVICE_I2C*/ - -#ifdef RTE_DEVICE_IWDG -#include "ft32f0xx_iwdg.h" -#endif /*RTE_DEVICE_IWDG*/ - -#ifdef RTE_DEVICE_MISC -#include "ft32f0xx_misc.h" -#endif /*RTE_DEVICE_MISC*/ - -#ifdef RTE_DEVICE_OPA -#include "ft32f0xx_opa.h" -#endif /*RTE_DEVICE_OPA*/ - -#ifdef RTE_DEVICE_PWR -#include "ft32f0xx_pwr.h" -#endif /*RTE_DEVICE_PWR*/ - -#ifdef RTE_DEVICE_RCC -#include "ft32f0xx_rcc.h" -#endif /*RTE_DEVICE_RCC*/ - -#ifdef RTE_DEVICE_RTC -#include "ft32f0xx_rtc.h" -#endif /*RTE_DEVICE_RTC*/ - -#ifdef RTE_DEVICE_SPI -#include "ft32f0xx_spi.h" -#endif /*RTE_DEVICE_SPI*/ - -#ifdef RTE_DEVICE_SYSCFG -#include "ft32f0xx_syscfg.h" -#endif /*RTE_DEVICE_SYSCFG*/ - -#ifdef RTE_DEVICE_TIM -#include "ft32f0xx_tim.h" -#endif /*RTE_DEVICE_TIM*/ - -#ifdef RTE_DEVICE_USART -#include "ft32f0xx_usart.h" -#endif /*RTE_DEVICE_USART*/ - -#ifdef RTE_DEVICE_WWDG -#include "ft32f0xx_wwdg.h" -#endif /*RTE_DEVICE_WWDG*/ - - - -#include "stdio.h" - -#ifdef USE_FULL_ASSERT - -/** - * @brief The assert_param macro is used for function's parameters check. - * @param expr: If expr is false, it calls assert_failed function which reports - * the name of the source file and the source line number of the call - * that failed. If expr is true, it returns no value. - * @retval None - */ - #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__)) -/* Exported functions ------------------------------------------------------- */ - void assert_failed(uint8_t* file, uint32_t line); -#else - #define assert_param(expr) ((void)0) -#endif /* USE_FULL_ASSERT */ - -#endif /* __FT32F030X8_CONF_H */ - -/************************ (C) COPYRIGHT FMD *****END OF FILE****/ diff --git a/bsp/ft32/libraries/FT32F0xx/FT32F0xx_Driver/templates/Inc/ft32f0xx_it.h b/bsp/ft32/libraries/FT32F0xx/FT32F0xx_Driver/templates/Inc/ft32f0xx_it.h deleted file mode 100644 index e01fc70fb7b..00000000000 --- a/bsp/ft32/libraries/FT32F0xx/FT32F0xx_Driver/templates/Inc/ft32f0xx_it.h +++ /dev/null @@ -1,41 +0,0 @@ -/** - ****************************************************************************** - * @file ft32f0xx_it.h - * @author FMD AE - * @brief CMSIS Cortex-M0 Device Peripheral Access Layer System Header File. - * @details - * @version V1.0.0 - * @date 2021-07-01 - ******************************************************************************* - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __FT32F030X8_it_H -#define __FT32F030X8_it_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "main.h" - -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions ------------------------------------------------------- */ - -void NMI_Handler(void); -void HardFault_Handler(void); -void SVC_Handler(void); -void PendSV_Handler(void); -void SysTick_Handler(void); -void PPP_Handler(void); - -#ifdef __cplusplus -} -#endif - -#endif /* __FT32F030X8_it_H */ - -/************************ (C) COPYRIGHT FMD *****END OF FILE****/ diff --git a/bsp/ft32/libraries/FT32F0xx/FT32F0xx_Driver/templates/Inc/main.h b/bsp/ft32/libraries/FT32F0xx/FT32F0xx_Driver/templates/Inc/main.h deleted file mode 100644 index f04eb665bb0..00000000000 --- a/bsp/ft32/libraries/FT32F0xx/FT32F0xx_Driver/templates/Inc/main.h +++ /dev/null @@ -1,25 +0,0 @@ -/** - ****************************************************************************** - * @file main.h - * @author FMD AE - * @brief - * @version V1.0.0 - * @data 2021-07-01 - ****************************************************************************** - */ - - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __MAIN_H -#define __MAIN_H - -/* Includes ------------------------------------------------------------------*/ -#include "ft32f0xx.h" -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions ------------------------------------------------------- */ - -#endif /* __MAIN_H */ - -/************************ (C) COPYRIGHT FMD *****END OF FILE****/ diff --git a/bsp/ft32/libraries/FT32F0xx/FT32F0xx_Driver/templates/Src/ft32f0xx_it.c b/bsp/ft32/libraries/FT32F0xx/FT32F0xx_Driver/templates/Src/ft32f0xx_it.c deleted file mode 100644 index f9f816e0e63..00000000000 --- a/bsp/ft32/libraries/FT32F0xx/FT32F0xx_Driver/templates/Src/ft32f0xx_it.c +++ /dev/null @@ -1,80 +0,0 @@ -/** - ****************************************************************************** - * @file ft32F0xx_it.c - * @author FMD AE - * @brief - * @version V1.0.0 - * @data 2021-07-01 - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "ft32f0xx_it.h" - -/** - * @brief This function handles NMI exception. - * @param None - * @retval None - */ -void NMI_Handler(void) -{ -} - -/** - * @brief This function handles Hard Fault exception. - * @param None - * @retval None - */ -void HardFault_Handler(void) -{ - /* Go to infinite loop when Hard Fault exception occurs */ - while (1) - { - } -} - -/** - * @brief This function handles SVCall exception. - * @param None - * @retval None - */ -void SVC_Handler(void) -{ -} - -/** - * @brief This function handles PendSVC exception. - * @param None - * @retval None - */ -void PendSV_Handler(void) -{ -} - -/** - * @brief This function handles SysTick Handler. - * @param None - * @retval None - */ -void SysTick_Handler(void) -{ -} - -/** - * @brief This function handles PPP interrupt request. - * @param None - * @retval None - */ -/*void PPP_IRQHandler(void) -{ -}*/ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT FMD *****END OF FILE****/ diff --git a/bsp/ft32/libraries/FT32F0xx/FT32F0xx_Driver/templates/Src/main.c b/bsp/ft32/libraries/FT32F0xx/FT32F0xx_Driver/templates/Src/main.c deleted file mode 100644 index b5777be1190..00000000000 --- a/bsp/ft32/libraries/FT32F0xx/FT32F0xx_Driver/templates/Src/main.c +++ /dev/null @@ -1,59 +0,0 @@ -/** - ****************************************************************************** - * @file main.c - * @author FMD AE - * @brief - * @version V1.0.0 - * @data 2021-07-01 - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "main.h" - -/* Private functions ---------------------------------------------------------*/ - -/** - * @brief Main program. - * @param None - * @retval None - */ -int main(void) -{ - /* Infinite loop */ - while (1) - { - } -} - - -#ifdef USE_FULL_ASSERT - -/** - * @brief Reports the name of the source file and the source line number - * where the assert_param error has occurred. - * @param file: pointer to the source file name - * @param line: assert_param error line source number - * @retval None - */ -void assert_failed(uint8_t* file, uint32_t line) -{ - /* User can add his own implementation to report the file name and line number, - ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ - - /* Infinite loop */ - while (1) - { - } -} -#endif - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT FMD *****END OF FILE****/ diff --git a/bsp/ft32/libraries/FT32F0xx/SConscript b/bsp/ft32/libraries/FT32F0xx/SConscript deleted file mode 100644 index 04932ffe391..00000000000 --- a/bsp/ft32/libraries/FT32F0xx/SConscript +++ /dev/null @@ -1,55 +0,0 @@ -import rtconfig -Import('RTT_ROOT') -from building import * - -# get current directory -cwd = GetCurrentDir() - -# The set of source files associated with this SConscript file. -src = Split(""" -CMSIS/FT32F0xx/source/system_ft32f0xx.c -FT32F0xx_Driver/Src/ft32f0xx_comp.c -FT32F0xx_Driver/Src/ft32f0xx_crc.c -FT32F0xx_Driver/Src/ft32f0xx_crs.c -FT32F0xx_Driver/Src/ft32f0xx_debug.c -FT32F0xx_Driver/Src/ft32f0xx_div.c -FT32F0xx_Driver/Src/ft32f0xx_dma.c -FT32F0xx_Driver/Src/ft32f0xx_exti.c -FT32F0xx_Driver/Src/ft32f0xx_gpio.c -FT32F0xx_Driver/Src/ft32f0xx_iwdg.c -FT32F0xx_Driver/Src/ft32f0xx_misc.c -FT32F0xx_Driver/Src/ft32f0xx_opa.c -FT32F0xx_Driver/Src/ft32f0xx_pwr.c -FT32F0xx_Driver/Src/ft32f0xx_rcc.c -FT32F0xx_Driver/Src/ft32f0xx_syscfg.c -FT32F0xx_Driver/Src/ft32f0xx_tim.c -""") - -if GetDepend(['RT_USING_SERIAL']): - src += ['FT32F0xx_Driver/Src/ft32f0xx_usart.c'] - -if GetDepend(['RT_USING_I2C']): - src += ['FT32F0xx_Driver/Src/ft32f0xx_i2c.c'] - -if GetDepend(['RT_USING_SPI']): - src += ['FT32F0xx_Driver/Src/ft32f0xx_spi.c'] - -if GetDepend(['RT_USING_ADC']): - src += ['FT32F0xx_Driver/Src/ft32f0xx_adc.c'] - -if GetDepend(['RT_USING_RTC']): - src += ['FT32F0xx_Driver/Src/ft32f0xx_rtc.c'] - -if GetDepend(['RT_USING_WDT']): - src += ['FT32F0xx_Driver/Src/ft32f0xx_wwdg.c'] - -if GetDepend(['BSP_USING_ON_CHIP_FLASH']): - src += ['FT32F0xx_Driver/Src/ft32f0xx_flash.c'] - -path = [cwd + '/CMSIS/FT32F0xx/Include', - cwd + '/FT32F0xx_Driver/Inc', - cwd + '/FT32F0xx_Driver/templates/Inc'] - -group = DefineGroup('Libraries', src, depend = [''], CPPPATH = path) - -Return('group') diff --git a/bsp/ft32/libraries/Kconfig b/bsp/ft32/libraries/Kconfig index afdd0fb83f0..c30621242a4 100644 --- a/bsp/ft32/libraries/Kconfig +++ b/bsp/ft32/libraries/Kconfig @@ -5,6 +5,11 @@ config SOC_SERIES_FT32F0 bool select ARCH_ARM_CORTEX_M0 select SOC_FAMILY_FT32 + select PKG_USING_FT32F0_STD_DRIVER - +config SOC_SERIES_FT32F4 + bool + select ARCH_ARM_CORTEX_M4 + select SOC_FAMILY_FT32 + select PKG_USING_FT32F4_STD_DRIVER diff --git a/bsp/gd32/arm/gd32103c-eval/.config b/bsp/gd32/arm/gd32103c-eval/.config index 5c11ef98df8..683660ae4ab 100644 --- a/bsp/gd32/arm/gd32103c-eval/.config +++ b/bsp/gd32/arm/gd32103c-eval/.config @@ -347,8 +347,6 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_RT_USING_RT_LINK is not set # end of Utilities -# CONFIG_RT_USING_VBUS is not set - # # Using USB legacy version # @@ -631,6 +629,9 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_RVBACKTRACE is not set # CONFIG_PKG_USING_HPATCHLITE is not set # CONFIG_PKG_USING_THREAD_METRIC is not set +# CONFIG_PKG_USING_UORB is not set +# CONFIG_PKG_USING_RT_TUNNEL is not set +# CONFIG_PKG_USING_VIRTUAL_TERMINAL is not set # end of tools packages # @@ -725,6 +726,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_R_RHEALSTONE is not set # CONFIG_PKG_USING_HEARTBEAT is not set # CONFIG_PKG_USING_MICRO_ROS_RTTHREAD_PACKAGE is not set +# CONFIG_PKG_USING_CHERRYECAT is not set # end of system packages # @@ -887,6 +889,12 @@ CONFIG_PKG_GD32_ARM_SERIES_DRIVER_PATH="/packages/peripherals/hal-sdk/gd32/gd32- CONFIG_PKG_USING_GD32_ARM_SERIES_DRIVER_LATEST_VERSION=y CONFIG_PKG_GD32_ARM_SERIES_DRIVER_VER="latest" # end of GD32 Drivers + +# +# HPMicro SDK +# +# CONFIG_PKG_USING_HPM_SDK is not set +# end of HPMicro SDK # end of HAL & SDK Drivers # @@ -935,6 +943,7 @@ CONFIG_PKG_GD32_ARM_SERIES_DRIVER_VER="latest" # CONFIG_PKG_USING_MLX90393 is not set # CONFIG_PKG_USING_MLX90392 is not set # CONFIG_PKG_USING_MLX90394 is not set +# CONFIG_PKG_USING_MLX90396 is not set # CONFIG_PKG_USING_MLX90397 is not set # CONFIG_PKG_USING_MS5611 is not set # CONFIG_PKG_USING_MAX31865 is not set @@ -1406,7 +1415,7 @@ CONFIG_SOC_SERIES_GD32F10x=y # # Hardware Drivers Config # -CONFIG_SOC_GD32103V=y +CONFIG_SOC_GD32F103VC=y # # Onboard Peripheral Drivers @@ -1417,12 +1426,15 @@ CONFIG_SOC_GD32103V=y # CONFIG_BSP_USING_GPIO=y CONFIG_BSP_USING_UART=y +CONFIG_BSP_USING_SERIAL_V1=y +# CONFIG_BSP_USING_SERIAL_V2 is not set # CONFIG_BSP_USING_UART0 is not set CONFIG_BSP_USING_UART1=y -# CONFIG_BSP_UART1_RX_USING_DMA is not set +CONFIG_BSP_UART1_TX_PIN="PA2" +CONFIG_BSP_UART1_RX_PIN="PA3" +CONFIG_BSP_UART1_AFIO="AF7" # CONFIG_BSP_USING_UART2 is not set # CONFIG_BSP_USING_UART3 is not set -# CONFIG_BSP_USING_UART4 is not set # CONFIG_BSP_USING_SPI is not set # CONFIG_BSP_USING_ADC is not set # CONFIG_BSP_USING_TIM is not set diff --git a/bsp/gd32/arm/gd32103c-eval/board/Kconfig b/bsp/gd32/arm/gd32103c-eval/board/Kconfig index 2e98cae740f..46de28e3606 100644 --- a/bsp/gd32/arm/gd32103c-eval/board/Kconfig +++ b/bsp/gd32/arm/gd32103c-eval/board/Kconfig @@ -4,7 +4,7 @@ config SOC_SERIES_GD32F10x bool default y -config SOC_GD32103V +config SOC_GD32F103VC bool select SOC_SERIES_GD32F10x select RT_USING_COMPONENTS_INIT @@ -25,57 +25,199 @@ menu "On-chip Peripheral Drivers" menuconfig BSP_USING_UART bool "Enable UART" default y - select RT_USING_SERIAL if BSP_USING_UART - config BSP_USING_UART0 + choice + prompt "Select UART framework version" + default BSP_USING_SERIAL_V1 + + config BSP_USING_SERIAL_V1 + bool "Use Serial V1 framework" + select RT_USING_SERIAL + + config BSP_USING_SERIAL_V2 + bool "Use Serial V2 framework" + select RT_USING_SERIAL_V2 + endchoice + + menuconfig BSP_USING_UART0 bool "Enable UART0" default n + if BSP_USING_UART0 + config BSP_UART0_TX_PIN + string "UART0 TX name, such as PA8" + default "PA9" + + config BSP_UART0_RX_PIN + string "UART0 RX name, such as PA9" + default "PA10" + + config BSP_UART0_AFIO + string "UART0 alternate function, such as AF7" + default "AF1" + + if BSP_USING_SERIAL_V2 + config BSP_UART0_RX_USING_DMA + bool "Enable UART0 RX DMA" + depends on RT_SERIAL_USING_DMA + default n + + config BSP_UART0_TX_USING_DMA + bool "Enable UART0 TX DMA" + depends on RT_SERIAL_USING_DMA + default n + + config BSP_UART0_DMA_PING_BUFSIZE + int "Set UART0 RX DMA ping-pong buffer size" + range 16 65535 + depends on BSP_UART0_RX_USING_DMA + default 64 + + config BSP_UART0_RX_BUFSIZE + int "Set UART0 RX buffer size" + range 64 65535 + default 128 + + config BSP_UART0_TX_BUFSIZE + int "Set UART0 TX buffer size" + range 0 65535 + default 128 + endif + endif - config BSP_UART0_RX_USING_DMA - bool "Enable UART0 RX DMA" - depends on BSP_USING_UART0 - select RT_SERIAL_USING_DMA - default n - - config BSP_USING_UART1 + menuconfig BSP_USING_UART1 bool "Enable UART1" default y + if BSP_USING_UART1 + config BSP_UART1_TX_PIN + string "UART1 TX name, such as PA8" + default "PA2" + + config BSP_UART1_RX_PIN + string "UART1 RX name, such as PA9" + default "PA3" + + config BSP_UART1_AFIO + string "UART1 alternate function, such as AF7" + default "AF7" + + if BSP_USING_SERIAL_V2 + config BSP_UART1_RX_USING_DMA + bool "Enable UART1 RX DMA" + depends on RT_SERIAL_USING_DMA + default n + + config BSP_UART1_TX_USING_DMA + bool "Enable UART1 TX DMA" + depends on RT_SERIAL_USING_DMA + default n + + config BSP_UART1_DMA_PING_BUFSIZE + int "Set UART1 RX DMA ping-pong buffer size" + range 16 65535 + depends on BSP_UART1_RX_USING_DMA + default 64 + + config BSP_UART1_RX_BUFSIZE + int "Set UART1 RX buffer size" + range 64 65535 + default 128 + + config BSP_UART1_TX_BUFSIZE + int "Set UART1 TX buffer size" + range 0 65535 + default 128 + endif + endif - config BSP_UART1_RX_USING_DMA - bool "Enable UART1 RX DMA" - depends on BSP_USING_UART1 - select RT_SERIAL_USING_DMA - default n - - config BSP_USING_UART2 + menuconfig BSP_USING_UART2 bool "Enable UART2" default n + if BSP_USING_UART2 + config BSP_UART2_TX_PIN + string "UART2 TX name, such as PA8" + default "PA8" + + config BSP_UART2_RX_PIN + string "UART2 RX name, such as PA9" + default "PA9" + + config BSP_UART2_AFIO + string "UART2 alternate function, such as AF7" + default "AF7" + + if BSP_USING_SERIAL_V2 + config BSP_UART2_RX_USING_DMA + bool "Enable UART2 RX DMA" + depends on RT_SERIAL_USING_DMA + default n + + config BSP_UART2_TX_USING_DMA + bool "Enable UART2 TX DMA" + depends on RT_SERIAL_USING_DMA + default n + + config BSP_UART2_DMA_PING_BUFSIZE + int "Set UART2 RX DMA ping-pong buffer size" + range 16 65535 + depends on BSP_UART2_RX_USING_DMA + default 64 + + config BSP_UART2_RX_BUFSIZE + int "Set UART2 RX buffer size" + range 64 65535 + default 128 + + config BSP_UART2_TX_BUFSIZE + int "Set UART2 TX buffer size" + range 0 65535 + default 128 + endif + endif - config BSP_UART2_RX_USING_DMA - bool "Enable UART2 RX DMA" - depends on BSP_USING_UART2 - select RT_SERIAL_USING_DMA - default n - - config BSP_USING_UART3 + menuconfig BSP_USING_UART3 bool "Enable UART3" default n - - config BSP_UART3_RX_USING_DMA - bool "Enable UART3 RX DMA" - depends on BSP_USING_UART3 - select RT_SERIAL_USING_DMA - default n - - config BSP_USING_UART4 - bool "Enable UART4" - default n - - config BSP_UART4_RX_USING_DMA - bool "Enable UART4 RX DMA" - depends on BSP_USING_UART4 - select RT_SERIAL_USING_DMA - default n + if BSP_USING_UART3 + config BSP_UART3_TX_PIN + string "UART3 TX name, such as PA8" + default "PA8" + + config BSP_UART3_RX_PIN + string "UART3 RX name, such as PA9" + default "PA9" + + config BSP_UART3_AFIO + string "UART3 alternate function, such as AF7" + default "AF7" + + if BSP_USING_SERIAL_V2 + config BSP_UART3_RX_USING_DMA + bool "Enable UART3 RX DMA" + depends on RT_SERIAL_USING_DMA + default n + + config BSP_UART3_TX_USING_DMA + bool "Enable UART3 TX DMA" + depends on RT_SERIAL_USING_DMA + default n + + config BSP_UART3_DMA_PING_BUFSIZE + int "Set UART3 RX DMA ping-pong buffer size" + range 16 65535 + depends on BSP_UART3_RX_USING_DMA + default 64 + + config BSP_UART3_RX_BUFSIZE + int "Set UART3 RX buffer size" + range 64 65535 + default 128 + + config BSP_UART3_TX_BUFSIZE + int "Set UART3 TX buffer size" + range 0 65535 + default 128 + endif + endif endif menuconfig BSP_USING_SPI diff --git a/bsp/gd32/arm/gd32103c-eval/project.ewp b/bsp/gd32/arm/gd32103c-eval/project.ewp index 2218268e137..1167c385eb3 100644 --- a/bsp/gd32/arm/gd32103c-eval/project.ewp +++ b/bsp/gd32/arm/gd32103c-eval/project.ewp @@ -166,13 +166,13 @@ 1 @@ -303,27 +303,29 @@ @@ -1275,27 +1277,29 @@ @@ -303,26 +303,28 @@ @@ -1275,26 +1277,28 @@ @@ -1275,27 +1277,29 @@ @@ -1276,28 +1278,30 @@ @@ -1275,27 +1277,29 @@ @@ -1275,27 +1277,29 @@ @@ -303,27 +303,29 @@ @@ -1275,27 +1277,29 @@ @@ -303,26 +303,28 @@ @@ -1275,26 +1277,28 @@ @@ -303,27 +303,29 @@ @@ -1275,27 +1277,29 @@ @@ -303,27 +303,29 @@ @@ -1275,27 +1277,29 @@ @@ -1277,27 +1279,29 @@ @@ -303,27 +303,29 @@ @@ -1275,27 +1277,29 @@ @@ -306,28 +306,30 @@ @@ -1280,28 +1282,30 @@ @@ -306,29 +305,30 @@ @@ -1281,29 +1280,30 @@ @@ -306,28 +306,30 @@ @@ -1281,28 +1283,30 @@ R#fXZY>z+vuYVQG&s&Uz;h4Dif~C+Pj)T5qSmC3^(;)uf4vLxorGZEZCuJY`#IQ?vX z1tzl~LFR7+Q&e6m=`)0&%ppgzAzT>^GeS%(N22A?L%55g3snyiY9lzI=j5RY7z;_Z zPc}*wmdxq&AIeO41q8y*%ZW=El{EL)dfbWy+cw0_#{@3pzN0@R%(O;MfJ#+dnDX5` zdGzuzJA{V}uEei?_iH8UKwg!Yej2z+ovN=T*V8Ena;Qdl%e%ciAekH-BaM+L-T(tFkEyz-bC-hYTP_q*<%h<>Y9C2QdPU6+DmVh*Fc!? zBAKp(NE46U&pv12WX^FNk7ngaJoU;O@!f}CilKeOViL^2oaqzMPPIfU`;^rjjpm4! z*3P5xt?yvE`+=)t)-=vjWgjGT9Gc5bEHwSGc-eeRCh;`S!g0e{^WuqB&j5Q{Oq!sB zx>+z9$05LaV)73W>X`SgE?k1QQEEmv3(d=bzV)3r=GyyJ_Q_6=(qimi4NK^5qICcnT zToo*ghI1LMoAB8$XP`;uV^03BUXEeMheWw`()3d2N;;%U0U>ka;P{y?O$N=xUzrc} z`hN`O_1C`q>6pp+<8>!mF_G?xwj=v#cN`!>aQ4uyFTAuN4jej|`(v$(xSRMZQG-UP zrFm#vxMX>J;F>Eq(oe<^4KGCVb=STRQ`HtuJBWA=ujofPCTI+%^cY+u4E}wa3iH88 zm_^gyHN%>ty{{|&!`JSLjqERPQF;SWI})aED%Jq^t^GbkFIz0eG{t@x-gfBV4siEu z&X0Ev_`#}gfQx9*IHqnGmJ&_$!_>+1VhnBa)jL+kJx{z8<60n!F{_nnU;oCISOs(Z zE6mYW=DPR4KbcmEa*z13kJN<8wC~)tCtiHF{H#*TwY7^YOsEA7RF+IM}`~#!qcj zM1{6~5kiSQX_c{P;aTL3--e4WX8q`eK|+g2-8v!O6<8cUQ5)l%CMNOOho-cV{h=O9 zICt*sm@;LOXqEjCr-|m*TLB2sWYR7w0GbAU_8kdk{RPCV^-dQ zndpMp)7lw#Jn)lP_wp;T0YSrqt6pU5%R-K;+Y&3+y%AS%G++bf$~~-MMaYjS{>V`= zVhSe~#Ar?ez;)s1aq%0!@$1oq)rdILg@9w1`$~1F$GbS5!Xp3{{!{dqBSfOxGwP3W z3Wko@6mZ$v#!n`}=Zd00!3X?Yj*A={q-7Q%pf{QNzxkU#j89`_;t2`a*^Gd3VX?p}@pz2=&$aEQj7*xQ+K z%UtLqp;iLkHXxM@fbEh0xT|E5l~eFxQGPRGm1e5Eo^HPa4p9`0I*%c=OeqZ?xSUg^ zUqCYAAW+35JcTe!guSd4GNYC)BR(8$etmtJtF&Yo%AOh>l?rz&)==rh4&cmA-zmaW z;0Jfm_77+Nx6QMEc^X!6lvfYVpJ2|Dp=xGpinyQ`eVP2`Q!UK#Mce3h6#Kpo23)6` z9bK(43Fnvp;@7{7?~}#ZUifHbeJL1VJ7K7Uv;amOv;KPMDST?i!K3XQk9sj%iAKhz zEt{Du+G$s;D42&7P#ob*bC24)?2?O97}&aJ1F)D8`GTXuX6I5C`KR&_-)q8_>uD+C>GcAq!~JjcOB9It^VC%O=( zur;7Ag-+l_=3ejww8-~rS>jHm@GRdsqB^GBR+e}JaG3{4lQpWqJCM|OtLP<8XC{@` zN?5*`cjcYhC9Rfln19l|nL9DeBU23gNjUsc8Y;u9a3*ww+txC($#hqw$>QT!gp3Lj z-Dab}z8hZ)V!60y{1aUWNl0DimOB`G$G(u%fa{*D(aLrj{aZ{L+Y}9~=e_ia6)vnk zk3KV2^t&S1+0t1j8{6>?Y=i4Vo>oJMz2pH#pn*Tmn()Ve_09O_pZOqj{dt9cVcwGY zzwhCPuqv7gA2b>Z8padj#5QyMyN#;a7G=E_`f}NBSr+$fpM;Jl-YwsB`Qxp`ERa=_ z=dGI8;IPxrKl|(Hc>n)?dQUL+B0_bbd6&^300c$KnhT<%yb`D2&rkPi!M047`DJ{g z6~ro1QF38&1a+b7KtO)|IZz4;n$F3yf}>f61IS+n`j8(Jg?R+I33Kr>hx})lPo|@2 zz~?H1F(<3c&kVgPW%)>4(|9js7*IY`ie$v1Q^J8t57K1M%v3`%6qB}e0E4tuiJ{U# zCC9lhDuD-<%$U;1Ul=X7T95Kxit@WpO74`n=~M<;u7Q~F{X{`++B-&A$Q- z;92u#p+y`Y*IqG#J(3+9U9}}1;HbFv4i>LEoYz1QrM3bh(@zPsaY}MAfz-emP2xBD?agy>=s?Oq#{wE%PYE9hp=<_js>H@|oX(8&) zVo&_Sv*yY}rbC%Lk2wcnPmFCY+D&)AN%+FzS~|~4^m(GmWiHgR^r|Tmx}i-Fm7ej8 zRRIp*PU9O-neWfQx--zxG3J<(Y0|7(4X!hp^Wy*-5AMuLAmm2EDe+McF}N8`VrTo| zm_1_xZU`sfN=m|F3WOtsB6-6j!HX*dp}I^w>^o|&qIr`TZXSg;iuq1QZ=)b~)SOFX4FN`K6Qf`>Qo{gYs`ln2 zLZuD_7DFNSCQYcvR|4k-Kld`$35_v+^5mE?lVhpyE3gfX@Z!bOAkrtHDMz?NZeHS9 z6=LsCz3@u>-+%a@67Lk&=#&kecg$oD{XhBTFXA|EAy@)2&dKgwKZSFzA&q@F^uxg%2`09Tk57H*Q=}Dptz97+#UfdUZsL$l96Zt!Ppx_( z9)05Jv@)28C;i0;1;_7=`IH?p3ETP*0o~cZpUdv5VYn+wBG;bU&NpN`R~UB z1X`NLpX`JAW2_Fr@udzp7oW2bQ~H-V-chr0G6E2?%`sQ{-gkv|;wtzCs45$hkwu6z zY4Qw?U&D%nnsuWgu4|yj0By^LeH@K8A@g+nNGeHR6gs4mKLrhpZ|deaSAbVNt9|R% zEpg=)m!)Gi^%^qkCuq~0s}Xv^l9*{;!d4i`GPejbLHzhrxf^DAwX~hIkZtZfdWx+M z_Ok&ww}2y#BX}dmBWnZ9tWNPXO_wXzGDQCb`esmJVS{POMA&C?2i z+;{HWRg@6GVB6a52^{b!h;3xdx_7?4{dl&4u#SR}SIeJ*Ef^rzKb@axy`-bap&Tta zqEUfB4Ghxp+?TxXKx@*YGX6`JE{R2FofUfyvK8Z{mvc)?I^NR)fkr*fsV|$h@55t1 z^AG3DQ_HxPJ@w7aW7v|mIoDQ4qT9+&!Pp(;h`STC$E8>gH8AI`LDN6Hrk!=BV2jOd zdx+C%ZOWJ{N7W%_qU{uJxOOUV&bYvxbO2Hv!|ex!mu{ajN9k(!&wJkbPz2g1acH}7 z=hi%Vql*(bv_w1E(?)spA%0WpSdR_Mt##rY<3fRvWt4S(9SPDG!3vFW* z$C_8-tZ{tKS*eUUt6Z!?{35ia4C~K_vNmRD`DzXX=jQ^0`B8u3XBj1fN(#SmRe{P- zLb9k*R*7g%1#iupMxb0Z?vC*q919-FEmV8=?qLgu77l*X@nmnF7%~!NMIUnl&5a)! z99@#G7w3iI*JnO@U0PbLedTq|h~JyAr>&m#%d*5_1)4%4PVGpXDaJR;qGUWC&SaW^NJI zv+~`EBcC%{hmH9er~1IWCcFg7#GhcH(qwliQf`_1Jo*H)&QrZC7A!t4046R_3Qy&k zfGX^#v$muxJ@fZZIvP41oFJQ-^_TIe#`mdul^n`jmPSCe-%7^SnA|NqZvzkIokhnw zdf6h`w&k_**RaZC0pv6&!dA_AAk9GJYNCNJ|4SaMGyf6}t5z-kO@$fb9bT2@8HkmK9aY?uu#xnVNZ81J*W(-~H4d-WN}C7TxSHf05@4yaZ*EiA8tjX-P{60fLZjg5wsTj9yROi!UK6fn$5X$XK}{;;+TZ> zb_ZTvfA9DHC>g;kF258DgBp&Udp6IoZ(`vD`{Uws&yPjZn=mT_3K;j6$s=RNgryMk z{qgO4)}SFh!NQ6bP~wP%dh9rf^0xTOt>20-fBKU#Z~Az~m-7zHj-A8&K(j!c1t!~g zOkcG!E=N_$f2S(@Pao zJQCE(_^A0Hw3d0ON_gaX;)(Z#NU^CMyL}L+D(2k*ylvOf*mD$V{BRju`x(G(~U zJ$YQrpEVoP#KUn&XNd}n#x^H$z7^ti7?umpQEdyLBM}~G@Rq&dl1-gFfBx{{R`wNl;hgDEtmC}q z*I?><*~5A0;4v&&CL$nM0sO<*GVmN*B5(#aatv6^AVW}~h|D$eSceP*qAUc1eWaDi z^0bIf7>*W>0INqxaQp3dAV~N~EL|{({qX^j`dIuBA>FbW^Wqdz3VYJ}X>sGauZ53( zD%1+M;!C3K_%YfNh6e;vdu*G^;EI#tl=$i1ZZ-a$9c@X>4~MCL0aN(D{LB9kpZzRb z0S+IGd+xo9zI%?x z{*SMue}xM#ybz|NnfC6%GI4*@?^^8Xa6CNFB*{Kj>Y+H?DZ3Uk4K5A4;wu9c~j~+cr-2Rw|WtfgF-Ba(` z6HT`v)+6j2#yIs%Z@06Ys$sokJ6A80^1-7WvHJO!;zxHq1denP588`< zY(sM0gK7IXj$*B0Za9dU_C+f$%hM#bY}v-PnZw{&5v}#p;K#5!aNfP-5>6<|wiFX9uSWW(?2B7({TgdRbA0Nv zU&N8{oM<~SB>wK3w=$2*WEUS-jgEBwj7PuFRQlRa37nOkwMooWWzhJ2)^4vni>1t@K`o?cdQ;L13JXS*_BC3qkrHBD37;U4>h)1=wRCdik8 zEUFJB_v%~qZhMsaQTY-`#A=_~^5$Dj>z+O($^+WNOjG?zy3C@IPc=UQ^pbcgPreL1 z6?g}~5Bl^o9_>m~oi6=nL>~Mpiz+Eio3Dev^ZZtMo*6IG4h|fsZ^`Vf^2i1noaT&j ztFPj^nhGam&4Q0`*7llPACKWz&yUNNpI-=KX7wDKm2%BiEc$tu(G%ZbVmX)yhPH(= zdgCj9_5Bz-W>{?5x)m*Z3*LZtv#_uyn7!shIdV(P((7~$nuH1Cn(-JDHc>c95I9Hn!BXIQ9il(*)LSQ0H?vllGVOqg!G!^}r z=<8q)@gn_B=9t&!Q9+bZ3jIjfb%ac!+)K!-tKE;rJ_% zs4tjqU)b1AX11R1Z-1S}=gK&tqh!hw01JM*3jqD603iwWoD$49;WT6Mz0Ee-yvRk!zzSo3G~d@4s4*2DO&S^GTrTo+3hEvAf~*bPA^qwctLZdQn+;HaN9s1HVdCHtv| zH6c_QLL14*GLJXZVRglkMeUeu9>P;~FXq1|(fGK(w-=LhS)&@-qQ9mA{|4LHg2K2N z34_YK-;ZNAWEg3}twXR~d-lhHH{OU5bbdVo0tMR=`!X)6VN#_}pR}_N@|l-6#6isD zr%sucejHAqIn|r}AAIjev3>8ZSTb)$^q**tF0`Co%oz;~7PW;#5GZRxu7G(sd&@VW ziF%E_#We^}`pAFM*r{>T2XBE{IS~&&`dIFtZ)_e5(|}Vi2;g3X(asbyMrxIkAw%s` z2VT2PW&_@vKX(0c7?TsRhGY9=a=&}q_hRk5c?h`MT92rf0W4!j#tMMWHG%P!BQLKCQ zMUE7_H(q;f9sUV+##L8e6ARhmaFAon{_M~GG7cU($yNjyQKXD&z@=xLZ_PW2_Q4oS z0Wx|yKJc?z)HLxyE9NR1@nr??-q;rr@W7&zy8C z@H%GEyJDLvD$|*=EX^n0I8}by6oS zqb67(Oh3!4?Xru%$YwWZn*Y(gx6#8{COSa*&fb0jR+JvC_|0? zj5)Kiy|#ka$I!Mq=X6lFviIMpw3QR&I;YD#N|t-Ao8YN#=Lwxtcge zok}jEe!=nQ6+L6(U&~?YA4VdIp7Jb-%3LgV#^v80v>M4$OJL$!2O zM|_rYGpGC}UgldRe-l-6FrnIwW-No;YzrOvD+hT`{r& zN`O9d+exv0VBVp^_G@a*tvqvL@(h%ka4F?CxcY8;`XS$~gTgGg-83SI?uys9cE|Ru z+c+ucUQWXRKR54#hWc8(|AQZiBW*bD1-2gI>(DZN0Wj{If33G|qcw;HTSN+ygsIXg zYV8v$zmwi|-|?T0CZ!Lkls+^Hjl!o`e!mBHem@h7Mf(hM^4&o~0ZRh^Xbl^`Wb$q9G-vH^OX7!~AQ#)Etk(6iqWv zj~z-u3-DPt>*-Zm#0OJV%Jsv*RRy9zHW2JX_0yXI-} z2cR*Sz-stgmtH~#;taH3C6~%=Ab4;l`E4NO;4g1_Hd-!hWFi4P8pid;-}!jVTXYsC zT8GkOw2r5&SM|#0O4-%0x4XNjJ023(F{|x|z(3N7m+;*O^N6>JjE!}cxFhOnRy=40u+IWS-_Vngvy z4g=uUgYK?2w5({NfKvh^hYZc=Jm(Anmr6Ygfd^TFFoH1));J>=*JE)`F-PrfI~Cvf z{_XMikFATva~3iNJdfD@eCEj*w{McDE@M5l59aUXr*g~JN>GML9wide)=5MVn&>J* z{Z#+*O`vkIE*~Y*OxJS)Vg%;xS}Yl^z5HDEeRJdw1vNvYUw6$1QoAh?V;{;`yLT|1 z7*f7?(TM5zYnulV`yc?Txu}=HXXiay*4KL<1hi@fn>2I60(M2UAi3 zA7Bf93ilw`eT1Rub&qx(+a_q^VSw&7i(cmc;Sl=Un&dZO zVR8&&ei&PvYEVtrps90vMGtM?fPg`#Nm^c5@zkB!g?7NAW{chuwfNQV3 zEG|EHZsMxDtrZ721KYr2wBiYxFXk_~ApZMbe}l8$kKrH@W*1o2fsePm?~?fF$8SLE z?`hfK5j8!<77(>H%*v^Cli@jk#j*ICuYW&w9mdp{(<59LhC-Ze+`cJ3_rWXUbD#cj zj8KvQL*%hl5?ta>df_KnXM%dnc1y{kv)0Dn-ugqVXMh$WlFwW<@%hUyk6-=r7o(Xi zAhi(r{R$YEpJlpa-ke9Yh#1cic&%tX+wZtLUckATYf*E{M9l9mg!$-;SDs%(Je(?F zWp)h0(xdDem}6@2fuQw3FO0$|w6E^Rr6RO-E&JvV#V>vM^7zE3K8jYgF8=gC(@t<8 z|LoU(EqXeRBLL}+>#w>be)5w?;@h`jJ%V6OxNRG~jgKA2X$b7s?`B)VjvYH;zV`#~ zN&0Yj)OT`f1?{54D?3j#7cXU$x-kVnPLbnz{j2NanrknMn{U1WQ|;ZD-)g3fFM@H? zW8uZSbFY4`jIUCS7E>$TDDWdmdz^e+Pchn)K@e7q)!ms zw6u)Q_3*pj`9VDL@MD;p?~I3j@&HW1jI5KI4E9(fZ?3Pyl>w&s~+=G}r%g)s>I6k7D)lSRuy$HYnJ7~J+_f*E+_g0Cp<<;+tD( zJfds_J}tCV>c*O9Pb)2>6Ab8MrydMUtH(p!6C3bPdm~@TX19U=p_ySUX%~CcoQc6bhfJMN|rX z#0QwoVVL}nU|YwQZQJ5J{MPM-MY0f^(VmPu`vexprUcto%re)JvrxWX^I+fiGf79 zj5*4(4-{nhQsyW44z>!Ft(lGyz{=JZu(GaM2m4#Wb%t3Fo?IU?$SSZ7J4PLkC9KT3 z1iYuNcO7GImy4&OMS0*wga9GEe@q0W1_qxI z$7B`rM}e*k1B4BH5I~do;H&u&CkKt+EYI(mXBotr6_$j2bLI6SsLo0FO;>p@*$8K) zURf@or6S~S>B4OOY*)af%rjSo!z&@K#^rmNSjx8o-RVMYyECCEbs&BvKbiH+m%ER) zoes(L@VsEr0z3>)$vu#-u6rfJov3ReR8s%8A0LAF;l_k=6|kUs0ny_yw~GKl=&`BhC^N%6CiCjP!f1hcSg{#6%;62KzH zz_XpzwzZ@QNf^h4Apg8~( zz44KouE1nb5BBZxgWDgB7hm0n6S6Vr_=m;Qk3SVxU9<#7Ye-C(fH||-Sp^85ZpOe# z+E*EuUe&i8J{k`^`bbQl@$smIU^{rEEvC+xgOf=JchcB*IPFdhKoSrNrV(J0IxK58QX*AAo9p8xmCxpLDjH) z&OgFIoczZ_rGLvDou4Xy_~17_IF}|NLceyx?0)pdt7G|6j)R-2nYYnS#dMhR#v5d9`)s3*P-n9?qlml$MK`! z|K2#!0fWJ|6!&s_B-h%tYh%miD`VcwaWEyv(57LMPCB;<)WaC(2@4SW(>daC@|4Ed zfeCL-Kl?ptml}yQi00-7JZ3Yl9VfM<*Y|;@_-?@&0W6vTJI1wck;puBcnYw0#^~V_ zbDMzL(f#`m#i_<&F}AS@CxMv4)9kWJn)7NJTn`K~Q##+|fn)c^v4!Tm_{KNC$#$B# z@%|ewiK8%WKfd>SX=O7XCwp!c@R-0pG}Fgvn;saGX3YDWzz^hq(T-3>M`pvYFxaqt zZ=AJYO3a*E7rS;JWl!)a%$0XBXSK(4PRtMsB%qs{KZt4cvsqVOlPTB=BjX-v*BBXg z3Ga5yi<@ZYY15|XJa_~RsrXoj1%&fpGLVih>Zen)eYZp9W|iY7CybkgFyc52oP@EhBE3)B@-U!@17lNh;b7sCnAS=| zLca+Ip*kXT-BD}2Z{GphABT=OIGm2dMzwK;@l=CKPqSv1_1pOX5G;sa3g@LsESoqw zIBcT-oY#-G9Y#pmBoy(X4}K^<`^8_4`yO~A?tOG+3M{%QBdtMz9v%vzC0^*22U(f4 z_E1EnkhIjxwl&0grkozYctGZv*IjW5_;5qKx^_)G{=}o;1LK9Q zF2}+BS{z*t!D3<95X{}FdtvPR!O5dGQ;r>-9?IaUWw*U#*0ntGcvAaU0f3Bt86R4H zAY_F}-+$mBcLjNsbq?i$Cj2^%)GU8A)?;IEB$oay5U46l7(JRZ!P`3-n}@%6EK^(s!+*u@xwk)sXGU-wQNz5p>^D9akm#d z9f2d(vE$j+!+>{OSGUypykO$!__MEmgZArS-}M4cgHb?U3-i}W+nh+PbRBa7QE5~A z6TukeyVXNMVB(tevg-|fUKBCnL8-7LqWH$=3f`4Fe-k%Ov1ZFSi|gXbkV=18KQM_j zj1}NcCfqrTxK$?IvXap>F8G`bIeFNh3Ni{E3|y3*T4Tc1Hk*gzurR>|(AwHjSqH}t zpIB>!OW+fb>=)yg6BcMW1ROTX`&1WxmN@K z?b~jHpxN`it zW>ErlWOUFc$>(G~=KS8f-gS)qTXms`Dl#}hBojx+m&H&7F5gPJ@?IrWt6!>j>=%*Tnq^2?DSAe@70P%f3MD#%^p8)jZ9G0zAhy%V9oQby)V zq|@(~>p*lMQv$@5=5t0Ua8&LNtekB4lXWizR3CG}CXcKq6R+jEKs&?uZ2s9krads)2BoYCiuG#x5sXrig^UpUHAV46G=4@t`kGOQ5CECixahnE z?28>6Kfdpwcyav>m^E+`kN57ehtkB0I)wY!(KsgqU)kqA1+CG7IdfvpymffQe-ep4 z+F!JfCrN-qVN8A@Nc%a5TSmCFV9p0NWD50U`?8_HVSB9w`|#hSTYMH zx}!f{c;(MoUHwi{F5eK8tMTOJ2Q1=TQ_S1ru%Cq8^tOvOo?J{J1e zn>w_AMQXu@5oN)YrugKCZ;99c(^n{$@BLNnOlhy2LalDLqYtMqEsfwDW7fox@&3yf zfG-PTA`H##_pXF_7y@(M5!YONZY*CsC7l?s)jpm6*pfG1dv3hMu|Tu19B68$PoV(y z#O=DY@pU}6KfQ`A1kc9JH(nd(op&yT-b^e)YH$>{3$w?&W5Xu2{gh#g-F^4H@hC#4 zSrCJbXnObV-3uY#$)5E|Sef+2y^lSEFl!v`HUk(tAq=}Y9ilzPVZfAZsk1<# z9*#hJk-fkY;XM$IucYwgH-784V(4%@dUv*x7T*pC&D5f+X&cF!&;!FT94nHwIOD2= zNY`WYS~NI^I4Vx_WUuis0%tE>!nTqv@jA!TU9y~`ks4ZJ_S}UC;9Bw4&3HoF_uX%O zJ?6}s%6{lt&f4CS%$v;oGz76t&5iN=>ecb#4}Un$J?EVCp8qSK|5Ti}{35oFj7q{+ zZP#J;w?E6iyQcCn@8O0<|wXv**U@eg9pt{vGvZUb}nvrY;sWzKCQg&o4L_VWZj z8+3e^8bjJji-X-Tu~o)01<;hI;9p@tJ?6!F`IZqZ=fdNymCO2A2kX|^J|w+{t5DDq z$G*`oNCynE`5Jc{LLu*62oD+&1UYAEdE_>Zre>V2fe*wjg`-<-Y)3uc zALA_g)h}#d8-;=iwZjOl=-(4){AFyGpMN3FB*)P&dvXha45k7J8PZyb8r!g)&Sp_jN;niM2{ivU~K0!?1gtqgy+)NN`IL%>!5s2*5_fAN|F*qiG1* zdW5L2Kqx!t35T15VO}yh3 zI=~+#Qg#8r=S&RGP?+`tDVc&_j4=gj%#)P@GT+o`BX3ENC-Vwo5A=4Wa~KaCtt01~F6VKvmrB^{9vmPjNL^P^y9uS&5N zmf^hn%r7S%@~Xn6cg##j&Q2&UY8jXJ(^pC7JFyc4O*>0nxI385+q69QnLilsfXRWI z35C+KGC6;ENO=61kEPr)DhV-ug;4R4s|u&D<(YD<2zmKrnvBZq;G~iRmbSA=jN^AN zVRZs>LC*9UI`~hC0ER$$zc)DKt)4S^rFw^~$O-m5Sq zIKB&fquwIbD-VDYi3{yo+C2z`)=?_uMmaA&bhQ$q*Wx zwLN-VCCUhBv03zQXWP*{{hlE)K%P9)rkrJREB~&c5~o2q$K9 z%w0q)T98gm$4BE$`_iRzVm?k0+gta>va{#LiY2qqMkcDqW#>)9n&YB)`q{_vui*B9 z{#gIo>+y@9`yv|Rsqw;^7udHtCK*Q0$7Z#Q&wuDf+M%7}9@*vr1EFB|n)7DCjLwe> zFIa+Ry#@{T(Rc~!eCyUNaoOcp=FxJ0{kMM|UpU$tGe%LTV~4;+wASMqV$04wF_vSL zIxvMFEn~<&@9kT+#*Noq3&W3TJVLUUaRTRD?pfRm7R<+?<-|NnaqG6Nv1P{=x*1b> ztP&1zl%#t#Nyd5HFUNoW{ojve=PZjSaVGh~>K9TQe(lxQ=05P}F|*&XXIC=zBiR!0 zsZV??HB=~687sN8qTPzPY{jy;^_zbm&%W?#{L5edINNEi1_y?seGNR$zZ8G{)xSrO z+rc=3P-k47!s0S`-oK(N*DG#n-GJx)x z9*2Nf5BU4`?n|w$M+Umzyp29qUxK8S-8g6)uGxoeKxPdvawN|+s7enxmNl{NppO)c&Y3fd z`LX2J(x5ZW=Jc7=hSNJ?wmsZV<`H_XWioV@I|`=CHW-11eyG9&p4HrUVTsZK!VLk2 z2G*jy0Akdrrp!ks+hgvu;1IsFP?9;MZqGdZR7{^aJAVHUzCc+u=@ow!V__}h{L0H# zuw~>^Fnh;h=bo3a4rxbl#QFha-$lQkWbW%?jkxHd*3!3ygiB;e zM%udAmM*7Wwv+UdLhV8uL61>qkE_*DXdYV&%-t|k3L%oI=iN^0MGOm(lIGD5mvm1jxZ(C3w`&Y(#o;D%|Mnetz(;6O zQ}+}CL{3^EU$y#cs(+R?~1l2P&WGb_Q3 z12F%rH|=fE2~rexk#+XTKE`Urw&tI8cRuhGuR<*3NTXcFP*rf~oCPjA$7G!m+zjKl zZ{J>ogH5q`;cSLcf9&74E4FXj92X;G^AwW_C~&rKZzXR93FL2I+3t2H{Xl`#hZjC6 z5K|BY77%7%@Y!}XT1Iik@Oud-MW*ShXzYz&YE;TGT4vz`m$>iyd*OQ5G4^lnxbh|< zh}2?)3^Gq3i;D$8AXOq(rMCw^pGE+4FrN7(T5+$G1U9)~ri4+XBtIvI60I7SS23Aj zzm;4n>3tIhz!AR(E~7ITGA{z1a2Z!zl}JA4BY#NzrnHqjEig+na|Z;2Iu{W07RG8` z#%D6hx|>n;lW=7jM9o&KyjR0%KcnVlm=FHR@A*&(@B^0oP! zg%0HIm!E%ClNocM4y^CAqku_>O`Sd+iQ>7bH8_ao!egmUrCAu$7!zDcR@$vvdZlIq zSq`f8AeaUhJ}CJA^T#UG7CiX*9~Y2nn+(piV76UY83W*$&nYx9jDMyR_aw?>yiT{; z+ryf1#EZmPN~|O*<-odw-z_cUW7D=n@r|#4mpy)SWB%+ZF#~VmV{o3@NM+7N_ zUO0D3z$4`4Ud}~x(UP)Q?>(>v;wed(#5c|B)aW|Fy5H8lytzM)d1o%(*ss0(qBz)w zsTv0oODtHYUL4?cv++^$MTr23o*o<~5Vt=706+jqL_t)VdCu~6S6s;1?Z@MZ)vsbg ze+uvL6EPD;6U+kW`PnuP3SArDKg<=3uY|HRn}kQdL<$7X0elVIeeXljiih*jqw%ti ziFZ9`F?VBDnnN;M%gpSbl1mEO4EkSmIUkfc#<2<S+a6!Le^s2%DFid; z&tb3k(fGqZ`8Lc~V{AWg0)l32)Hk-IaH6grh`|%jIqzeCZasw6_kM79Y<^=QJ`+ab z0FicpDD{Y-E{;Mwgdc-lSY>R4sA@!Of?qVs7H7FL=}LRp0;TE|3@5-R@lL`|XICRJ zNyHB$&mK+2I+K(OM3WOYmrUGq&#sEcRy~)*{=-i`9-sZ>Cvd!Yc{axz{>a`VlJ2W86{bpT$^EY|b9MCMT11lccbgLaN)@8!6uabrfuXFmPu7*ri_m-eEfZR zNI@qK^hS*s7S~_143qj%vGUn9Xlc7?x6YW2DfFIwM`Gnu&&I`^y|Fq3FG$FSW?kMc6%3IUz#%ABXR z)C~q@4R)?^%*|ggH$8;Ae_w|1*s5Ox3 z1;YwXTAswQ47zve9tn3Ik{~bG%t+kmC%V_D%JQ+B~g~I>BJXu7Uw=Kl+pfyd> zGK>%Na2ymSMk}L{v18Zv`0QuC6uSMV^CQfAx^{M%$T$yV%#qIRB0+Y)xyOg$S!inV0)Vxm^?;iW!cnKki zrxVz&;?GC~Smemqq^wHYxEH+<-y1p|Q(&NZzjQ()47-e57u%n-G8m1f+J0?E5MX_U zSLVJEYYgvR`Y&hz2ZUcH?~vZ;m%)X>?bP}kLTgFy8$951etcUPcmW=_}-Se+7TpUu6?7ODa9vPT*XU9!`HwQ|vl$*a&a;Hwp;Y{!>A5v;SIX%-I(BMd-T!>~KWB;u9>*Ikb?bqvX9 z5635mw6I%JaO#pu1pRIt>o}Tl>}Ed7{pgMqGS+cu1HO0MZ{I;5%$YSK{>cr$1Z^@N zq3Rnr8pTN>eX(-Y>UhQsVpxmsSe^VcqTfqzQm|D3+3K$9r({c}HA(&Gq}=+oGVhdnICmu8(w08!HzLQhJz^)wr{%po zlGvJX5&j;z-gS)qoBGZEWRzvMf}nPKK_&?{wYYq%^mQUcMi(Kgh+uA+NxAV{{gR>L zk3>0$Q-?HD32e%H$T=8tAqGLSywe}k(F53SoN9baO@hEQg`3aJGN~Dt2cwne zlIa<6^G!G^FjS-FGEI6XH$Nt*BEJ85IbC-nnTjjRD=#S^$#*9u!^+QmXbk?7hd=%$ zSQ*z$d@p(UX0jv@$lOJ6AQ}%Pny_TdH~q0)-hBCP+)}3b3b4@(bE3{KJa?f*(R_8( zsAeSD2h$|683|`PN6A=~wBC4k67o7-GAy+!9B+Ae?|FM;eLzFj%o1kA)K9{Z8kH3os{erPdymjwGO`diERQ{` zyzZ&Y@y`JCpY3iwnbW{n&usru|Cluj2QJGJR@+O$3C0;}pn2rzIDguZxN^lp7^#IE znb;op-}5w1)H-AFys7vrXh2h|SuLiBX?jQ-Q?DUth3j#~wqqA(zHfVp`s4MwlfC53 z)u-s-I?NvXYK8@V6=M?Kn@3cLmVVmZZARIow5Rh_RzDH(bk)p?p)j zs>3hx?ZNS(cx2W3A?D6sae2&LygW6zW5!K`FoI}>km`i^+p^;bX7ly2Zo?iNj&;R| zN%b)X#&_)x?v2~;d^G;)mwz#tW%JUUwWYBECyOu=5QCSlSP>gGZh){_6jxt)Rce;H zUOYHf)qmk5Hw83ZESNk2jm)?d4qSNt1%-gaaz@RdM{~KALaaOm;jVDC3+>`0 zoIs62%cKY8jc>dfAN$CMVL%R{d1~h9CXT;@5%b!|c7kW0eJ*Crni(@@O^1oFojPM2 zr%ZSqhp9WnR+^d9XW-l5K-_cpU3qT(jknw!7c5>Jv)MA!Li@-{A33})O`6+a?weXB za;)P)EVm9JFhH9~zv*{i2!0y=>z{rjF2hH{qJ{JGc(R>4cgL2kJJI$HjX(ZR{~bqQ zXhrcxc(fJ22NOnN-aj@z_32N=l~-QQdU7aMu3X7}=jT~B`f@M3Of!v~%xf?0+yFf8 zYu9&xOyr6c=OdibA3{$aRrc(2&&H-r+bTT-L&caheka;FnG5&E%b+L-lp&PiR3n|8 z>>%aQ_Y_cjXO7LE%(J~txz5AxqnFV-junUSxphDb104-I9}i)oDCW$JM-x=9%420l zNXF27y>uXV1m|BfW-pAZufH)~cwsHV!$+|YX~8;ZYdrkKD&}DDQK1ral5Ajg?$5Qm zQjRdDMMDy1&IJWutJRdr=s_^27kQcJiMriYyQ!V z+p0T9w4oL40H0+H$B&tcj6MD;7<>9I5)SK_ z@r8+Jg%Pzw8WF?=!m_2%D|;}%{&D=>-+eWH{WsVmLm9^rbe%fsR)V9958^QnTiDKZ z_{gC=8nOeS87-QOrdD5NQjUKU+vuwB4@hllziw_aECMx-@zj14WozXvA{z zfyW7YQia?V_eGF7 zH?1K?GC$0pw+O4Y2biZ$A+W}e2!2)+tSU$;C!TbIS6JzAZ0KH2S+Fvb5F$@OnA(E> zBTtm+$MGRzNI)i?(usuM`9tLx>jm&0INTZQ-)LnXKE>K~EFSy4KaXGil`Q7nHGcM8eDH_85$z z5U2ZCKpR-RlIbIYbu;VCGw(iEuSy;B)xIj_m--Qyg=f(P1UtryXim^B`kK}~z4F;) z@HHW_h?HR3AwK8dpZCX>sg(bwsP8QGo09wkU$Sj!sAP&tbH7DSe0Ya7dW*#WFM|pu zRl4YOpOUMvC;A8-O;&|coT{Yysj>&RY)K=YIBtl_7?VNjhX`qzFgeE7PC#nh6^9@k z9$LFI?pU)8)MlXs|Lx{+Fg%S&z&CB#8DIVCt?>$;#h0JA7%l&7G?^|q61Ole^Jl~f zaPy%jpG!hA(VF7illjzRPsUk`aKLu{`8fR=9_OFCIKKbb?Q!-fj#x^@UXwr;EB@)= z#p7}WRcUw!3z3@4kAL{ahC|2+74Klttb>3!)YcIP zIa;X>6Hy5`K4vEkD64V5?FV1am_(%j3r5Z9aeGp}8QO2N6 zqe2kn%{WKIWD%-q|Nfm2TX?1Zf5>|e=)A7$K=%+tBS3;6!QOinN%dk?OO|E1CAMRG z9FLvqB%ZvNmGv^olr=M%Sy@@mWHMfPndHTZGj=Q~w&S8=*_PF8iBzX3_D-;OkN`mf zL?!UPZ=ZWXh@xV>_cEC^d>8ot|K4*?-DjVD_TFcoeY#kMLYQ+eV}mPckP4akdR9cG zg_;U$D%l+?HMEj^L%@$YAVWZWRZ#XX@Q}9J6SiX{tC2EO1295@MPX|q))Av&=I7(- zxV3dD0?(GPvhef)SY!kO&a~zjyMEH!l`@1n8gu`kOijZW%t7hP@tDCkurJg7=jJ_o z_N;W{%{Q>W7|+`kI1dExrE{8uD{PpP{tHx^RNL2Fp>(59of9;@bsz5j1Bb}-LYh8h zO4__(12D(4_cd3?ky-9*pEGY>YG=L}kLAOs{@KS_b!?)2I@?0ofEnzl@nZnDOd2az zv{%{`V;aQtBpT1+b^y+&zWWdEXT|+2mJ~Y>hS#Q>Z@z_LoKFV8h6P;aI50deA8$F1 zg}@Ke2S5D5G+|N`Ou8E>7=xG_J7vwc!|7muE$EE9-Bv2=!^~z`junTnl)R}L*IQdO~5h77+|co z?-3({Mkjd2w$=5U@BN^PSn zfjZXHDW^(8l}rk8XYp^KwTI5hdU5)Aj(y)cZgV9!4?w{qDq?EuL=vqw6g*_69qXocB~9xW(;LrKYjMIYivi;(z=+Zq94{i^xC(6@922p! z&FX&@D~e4MrliO5Tk`m~UVwm3PED*#PG+7Rj{=k>L_P|D{D>TkbA^!;n2Pr)baJUw z&_P~eY&w?Yk)%cPRxSYOG|yFIpRc}p6(mBalA?*aG-Xn^Ba+TjX(I2WWYeJBqEv#@eSH=Hdpo`Tn7JdUd1m{rmk z-dQ+kydcfzl|CSZy4o_p_MkNfBt+xEQ*pJQzQIKb9}=F{Ej{hZ)3ZPs+g^6~h@$xO^+ zt{#_sXh0R3=n=X`~F_pdvri}#K_E9AZPGG7&2(n)boOG2M*r^+;i z?KoLOWe&o-mpEy-?H{eh2ix@IEmZ(I4)^TkgaZ8Tcp5_RynI{th z5sEIiNKiju9WZpDQLjGw*Lgz|bzxv|Pxm=s)6K%dAuRY>(kUE~di-G(cv#I?SiEo% z^m%RC(|QcwKJ*P1fObV6zGXVvPp8**?o0Qu9r51xznfDmu=t}KY0tq!N7Absb|R19 zdy4i{a1E?Vc9&r(b#~-SF}Vk6}@r1S79$4+&J z1(54-Xc-%t`#=Cq8~V1i>ZbkB+oHlmm)PoiX8kxl~Q zBq&1X!7D+7=rNd`9AX7CS0K`gpeh4mKbeWSq7CsIk3|_yuC_@8H-lW$93z@D6jr9U zJT-=v*~28+!9Gd}h?jLLszKeo=c#~2q#w%OLE^he7GJ_SuTtjv`m!w3Hmg7gZ?yc% zF!Y4i&aw~kU^Hb6!7_`B+2^8)xfg6`TXj1=*YhG3#`7)n>Hy8BD`#60^D}^R625^9pM}*U~8ynB?y=}YT!?X z!0V(J%r`>4?}dwLJ$|Z|mG8rCUFmDz_)a?0#Zhnwh+PQK*3cDd*bRQkEBeh`GhH!v z`v^dD_vXt~L)Wld!yI>)y@)qFY92Y#L4^q?X&8B6>^|9}Cyu0F{`7lsLI)E}qF|87 z^ro8^vU>aL=|6qpOE?qM@l`#rr$1a_V@2qb@4J)z?h{~cq_;9ow1GZ9+deI5HY^qK zs2`_u$Xwalox69YAFtJ`{RGnJ;7q4Htdt_0R0gf|$TXBmLS1@6D_q^zd=@ar%9_3r zM&e|y^IQw7FJ0_|M}bM+?d&;ye)Ws24B`PBTI=fUyKcQP`lymT>#&J$IdO*71zz&5EU|hoc!EeDDGG&a>)&-HJ4M(&TjYs#Wxp{gcxA4I9&qwbyg(TLY=MXqII} zpTlt4Z$jKH9@aV{P=CF&$7%_+*uASc@N?n91z{Fn2NV0pfA9zCCRP9^;DqlD9P2ew zZUu~=-P(?~_QxN8B7OFgACDYYKew8rxvpZxQV;w15um(mlHS45kJIyNC`|1SfA9qR z*$>msx>#-3T-ZIpGZA!0V=<$-s+il0aA~!x7*DUf_Hr7}YU^vj>|-DM6!o_Sc?C>C zO~$uzJdCFtCfEMM`_t3U{5XB`=ROfDjt34N1omsvz4w1G-Er6L=^%a?{^G0ON#nsW zk6OFn{tK8_ePXx@x`=b59joF*Ppqf`H{Q9by&DhmbsU8k!Y8%Zw0%n)_w>S=HL1C| zInI@i{m0DROw3|Pj42f}gD7P*#h%FVcvCR54uv|cwar_$Y{i10GpvSU+%O({SlR7S zK%{*NBw5Lyd(eKDricR+5%?YBHhLrDC&65Kp0h39E3jx*tZ?F-?4D%#0qg1h=J+#j z-pQ{FP!G#DTiHx5YV{f~c%>scGC^=+MHD4V)8wf@)^X5>V(Xc74N8ogaXR_F``;I`hy??L-;Iaf|$g-xB7am?K31i8~k7js6uygCCCP@+j^2=(>9`zohdT$fg?SO)#$ zC|mkniw-TwY-E-ihtgG? z{P5eq{JBup)iEwzJUMvqaN4wSOZxloKSv#_)7&|8unuEu65~!~qFwB9r?D6Sol^FS z1yrCVeIh7mjQA)#?RRlVrQqB0CIS8b^}ntt!Cqz}U-bCUl?h1s7#eg2k;o|lQEM$# z$m1#BJFJFZ<`Bdx0>zdhhKNN%i9t5ShiHW%t;Qp~bLR3xd7*Vf!!Kb_(AP7p$SHw| z^2sBR&5D?(Rf+cGXP=5n<~)5zyv*EP{LRrKaS>kv!6#QEvdOg<`71D$8;xTmH0BWS zYP6eW+pJ3n<(5&VQizH+7XfecV_8NFLT(x^c?0WfxUg`tZg0i2GZViWSSlIsj8h~Z zDwh|8MX0x2-sgPtcLcueR~g6lWM(8!I%R?~w_Lk2wEQJ>c+m!1-?v=3-bL--^7bDk zV0f|K4|@&}S_olfdrNr#qm(^7ld}Co1r2|B$-RAE*3-I~W_TTW6vIT5{EnAp{7bUB z^icuX{>&PDep!_ahC;zwDCpka@~m&%gL_cCLG~0^GP`{A!}q3n(_z*sI+;jdvKldU zC3-)DZ_|dY=?}m5WSZX8lqO7>mX4!Me)h-Dr+KqKj)uNI&0oAQOysQV8TRQu`;#B1 z32e0PWR*=Xz!f9MP!}75GK)H@01R3K-BEijv#SnZ>4I75x~t};)vxb}Npt4(>8#+j zr~mxbhtraU)6>nISFOg~a;g}|rmaQbRahiPzB9ANO)$SQWQhJQ57KPQrNNB1UYMpm z`;Mk>J^oDEga`SC#;KUF0USAJt65Bb0kC-XPMGG7$w3if^t^g}w3=G0>Gx3kA>A>Ur_t=_nbDGSG@G{`8Qsmf)vk0SmSkY(CDkg^& z9AQ=43q8eBqp6`Hz3(nO$&UlZMY)2|&p?`ukzuqlAm;?A5bYko>v2-o&C2cfvGAD8 zUTLALKwxZz1}|5xLg7lEvSk-#1A8#(Z<}vEOBT&ezxCMCQWDXV2yISiPJ#7f<99uZ=mVRA8!1g$<&v z)|QLqm`F4?Oe$E7PagZ#+3Hxtb>OD^m|s^*DR#PvYS3SJ?l*Y1h&8U%&Wg z>EW+@JN@S8ewh_Z;DiF>i~sdcVsHEuwh*}Ld+HR9@xa5+e&!d_ocW7F&}nIDO;0}g zRGKzpY6w$pD3wRT?EV0OUjgdiA(*^nt8j|f1Pl;BVTkqgy&kXoyLasZC!9!fy}M!7 z9ol-4{`PmiovvE3BHfCRQ(ZSU?K^m!eWvTvhwr;L{bcn^=~qAVi|N1o<(Jdve&biu z47L=s(+{KATRX_At0u3mYTD0^DOZ4;vwfC9bZWYQ1xF=xr4dH8iZN&{PH`&5-~avJ z!+;)$O7V?2*+Xe z%&Miw0BQy^Tb$PcKwd!L*^3|Nd(#;bf&%nR9FR{@QPqn8BmX1+ zVI1Rnm5L&P8uNdI<@eDh%2Y8ve6{`zN|~t$0q$|{W1sE_;HB4e{3(K;?pF>&vyKZ5c>6gK+EQDLuTje?Cw z4<3cDxZ&EX+1@ZAaOlQc-jzPz-j-f?{<%=Ls$9|HLfllCcOUxLM$P2eE+Wi{kuIdXDg@oLu+&&$ejX(jc0AsyFfCO7=YO%Va?GzWvrcv~@ zejob!p#?5*K&L~Q$SUT{ISbO_r7P3=joT5RaUj|>4YTLNsT*G?GiFYUJkQ`8q=%zP z=Pg>6CQoCl3VhUtEo<==aUv8KBPd^iQ2|<<66zT#>~Z@yR;^=ERd|FG9USvvrR)Qc3G6?ba*3N$fj$U{~g? zXb6j}P&-y^qwj==3wDkf6}{qX@cSqO+c@!J`t&Jm!FeTZ-n2QbeeE^O*~f77Aztk% zOKSlPnNS4KF7i>4=D6__)3|zPNtGk#7++@?Qz{KuIH4W^OK?nukH@ptvGvW9Bf5H!DZ*(n z3Tw8`8Q*rrLa1~ISbBQHY!tSC`fqnXxF{!ihNVyZc?~ zJCFPzy@W+UKmFRzd;!AaKzJ1K`%^W_^gekm(rM+=!=j45DBLn2Y^5#s=RhBHIbfRs z9W;)2flGlzM7~0<++$ZrW8TsXdzH(f9c@ID7H=bMj#zy2 zJ~V6)D~W(6MWaA6otpGkXjTRhlyDWuQib!bn0(dVF;RrMkCQcZkWp0FkE@7(v0M;b z#+v}cBq(tM@rb7WpslvX_Jr3<^MZg%u#D8eInd}e)8Xdb35kKh zp{5k#l?xy}>G%?U#*g9xt~pnqxUmNQ+{_5Rvzj|LAYsvH@xHvGG#<y+pUshntm%XG zOhlXy4+E#Oy+un_r4QZNmG&M!$#|$pv!_kryyYJDjBQ2Wo*gShP8K~(GOJ&BK5b>i zbHdaWEavNhnK3P6z}R-usEU=r?3|~cvDXWIaN_l>^KlI|I7C~S)}opAcr6Uq5cmhu z(izhbUQdUxSnZ5OliX+K*{{{?f#Z(6Gn3>?N2p^}22Nq93bR+ud8=!y64r3(l})?T zUw{4KwD0)2GIXkTI+bNlan?|Z3%eXjT1bsJ8~>JScJ06ynoo;WsbdLv9Odk@)nJsL)4 z)JT}S9-I%QhIFpG6;sv2m_2h61C|%(5U3Sz1*y!8+L?M*LNcbN}HugqYVi??@l`z3yv4v2ElC_ zKVf3}2o@o>vl{co!3P12pGdU#^@ftSwuyD!s9BTY6vH1w7N^ zpXBtpblb=7$NUb2b_R9rq?@nZD%F&Y?QV7h38NXjAW($Xf_2$S+Jiz z(bQJU4C|(FYkz$AyWeGHbR6E5Po|H2@WZT_o}iw+9GBIR&f`_yqwu_B+`5@RRJR;O zIq-!qKbTf5oS*(^>Ws8<@tkzWo$pOQLV0UrCOrYC>&BZNJz z8S>n(QeVL!R^_1s`cv?@FwdD*uy?yj7v`~>w`{;Gz5Y5Tz?)dA^E|8Sp-9TYEwg6` zMKKT4Z*f^K|EQa*R$ji(e|9hRG;W}(t67?p!`#9{D6BgF2QEi;#-&{EhvjcyDoBKt z3T2FhW+`kd0P0Nb^r_RFCb0~@2Pc2L9|V?>hjfbes-%n4fr`44odx8&(dX9BzCTM_ zU2w5@g=+;VJ&LpDrkW*`OzoJ(k7WzhQjQg@L`c}TZ+|GT6voU$dfUP3-wBjqzw*z2 zp15Pv!|X@jx@Akc|Ni@Mn0s~Fux?#C2^=g}CBP|6nd_jBeF{X3M_1^xQe=?4am)xj zwP;cK)rO+(1oYS@xCgtc8Y>~{N~D0LdCJ%I_qV4Lz4=Ug1v|%_ZB{5g%D6E<;~IVr z{|#C@C}6q*ss)k9owb}gliFT=BR%@WivXl1&BVIH(=Q%-Vl@I3=}1!z3>q0{3Wr^< zZ%U`np$I~WGDhnn-f2>waRZ#Sp3ph#D%N;8WB4fCy#Qgf*SfeBz%i|0tRg2At;Ew@ z-7Nz;)3dK!%%U;H#|$E?TnsU6XP)%)i?9k4K`a<}L?QgdI1^6dg#4->(q@4y!)rM1 zhj2(yk-yoIm+w_}YMo_PDu%H5j=4~!f?n~(U5gE8ceKHIQhcj{;O0I-@j~09KGfg$ zDzU_|{tM@cVe4T#C_G>*ECmx#^s5AI^ppLubI0!Vzyp7WVjH#{x+DcSkD_?%w!Lgmqkh$# zenK73W6gH5qc#227ymHbboBzPX>`yCU15y63cmsR(~Y2h_0`wdDjdw#q7=Uox;8I8 zhB9~CuDvKU`qK^;1+3n!@G73-;F#+v;G-}tifLjmJ6|_yCUA1m6ac8u0H<7YvEOWn z3L!0*dzrUp&zg~Lzi9=^ZG47cg)o9SVT95>{UBHQI0Hy9-VitwGc3yy4asRY$$Jq*vLt&uxlW_I!3{7v`f%d*N)e}@vhIodzP zQ^2*X%cTWcueW=5Y24w@muU|{LrpHCM$W+R(&if;Ihe*ic}o@E5>VuLnR16$%Y4g> zqlBLxe<*p;|3lB*3{}0Tu+R3kD`RH=j&f(V$kQMx13->z@SjhaL$o%Sbu49I;74lD zO<@!38`Fbd`*s@hOCRH``)c-MVop{&HnA-Y#)g&Ghn>v@-ym51S?Ugt1_&q)KqBv+r_&ARjqtX+2t_fyrFcz(Ct(di) zOLJ$;VcudavwyyteZI42O-VOhw-hIR`{H;v$8r}FUnM5Gny@mwCo8u*WW=L5UHr9~#o z6*?KGPyWn(&{CWtp`36}yp#Nf4cjom{s~MSf=e~$Mt8NxIqQ9x=5N@zj@1nMj8(-! zVDI_Ub)zZ~PEK(4`MLBjfA3$VM$E|d&7fnq-qE8_dcX)`sz0u2GV(dcjbYgoj6QT+ z!N@b7(@4(jKG~JN{>anm4$iEf+=NLo{Q-Fm)5nb)Iny08T7|kw_RqTlhrvj?P~DUc z9`8)gJhvX91AhrxVZasjQ~uglUQZ9>djX5_^rgT3R_gtQPloeG%X;CB=Jd$J52vSJ z-IzZAYv4b1Im61ajB69hiF%YCdZw2FKhIgiA%JXBN_&2`!Q2N$)zrzuK=R?8L2Lq^r&DBIVJd4K)#hT~0oNP(IM_;Jq zx&M9d=fs2Yair3yYJ_HRx=u$4TzZ&4hR}ZoX0``m;b-oDF9PP+^sPr8Ph)@ebK$7) zk?%i~Hg4IKZn^D-boC9KWzX2&ezY?^{OIFp#YFelGg`pu3K+>a#UOwq@)lSQolrn> zEDbQuM$)OBn7F#9*cdYTGWL0U9Yc}$F*nmJgg4H^BdyL#B!zlu%Se<|B&9k~GznysO3B<>j*1ccH^!!~vnP7!PdGxIGmmxoV_(;0@-FKxqbLQaiZ%=GVx}cJV z`nU~g034AHM}AQ^>JxN|hbTDn7@GRa$LmngOTMI&{54b7LQ0n`2a z_r)mz;p7bgK$_6S9``d?eB6PriLv7*q#fHh3Jz2EuYC2v^x#7eB~AxTohYqFQa7dp z3PLcWewtq^xR1ffU(^tQD*$Q*pn}0m|0pUBDxvRsGXlG#WHv$kXV073VYIw zYU1i)T#wz-jJ*2q>aRkpu*}D==}^&bmHx?#_2bXs9NS#l*0^t?85D=nF9=R`SlraJvg)EzFXj@lfI_=G=FY_-Fo2fW5&0t}w;tBb zOH^P(t2a6T;vaI31R8%}O*!(oFmoM*U?hsa* z)yE1p)>sh-pgC?zYh49Tm0tPeiOw`-^29=kVZYf=9+lZ0{a%5982wKBrI*{cZA(9o z!qy`_4`D&#DGOR^)Yee{ZXI6MGB@cf1wj~m&PU?`cksq`m$HZzi$%ETh-e&N!Zb#A zZZ6;YBdEsP{p86raPoN-${iH_SmU`RpabPj7x;1TSUZal1GES0m6J!(FMaBx#GQx0 zj}ux3F&7)e1AIjrN2%;Uj177 z#Ls>RC!u$wB}PH@iH^Cz5#C7;JW(d~ zGw)-$R3(82Pu#An%oIEnTQvHCV|{g9`oO)nr1$f2u6I|Dzr85Doa@G+7^u($l04}# zi)Im(yubmsUuwA+Jff4${|~MVfh)D4^q~Wp{*N08nOZUjvX_KB22>0n;_=RpY2v*& zV4}E;ZG0XagmJ?y?{zxm*~v1C7hobqV~K$ie-ID`v4|>BtY*-=-|7UKJ@;`1fzyEx z@3U4Nf7yiCo`EtC;tJ$t%FJi8R}e4Zm}%BmxR86h&0p?3y(Gi$RJ3<(l&Dg!C-*H1jYH@ z92wNF07qWIe3-n*H*TZ#mXqtA!-jtk5BEOT$ru;!cqm@IDa=S*m*#M3SVStnhDR>L zhJMTPohpZ4mn(Jn`?tF%p8((`?~7uDx%iMD`L>hG_=XqvfvdzSUtN;hTOQ5x?XGAS z8Rfi;7a?yK{Y~M<&Usr`|8x47h>MuRi_WG}Z_45ycwn4h3LR4mlcf8l#lu`r>nLLK ziRuE1h+axC76qzCR%nDI6?Vunpt6Pre)>o^npktcq@ zS@xUp8h$I<`MF|x2;4m|P~&cCB;K_2IFsM5L!7!$HI8uvBY>H&D^{A{#fU|aIeO%1 zdTH$&=@TEFfP)(x*P-B&d2C|e+=uRc4+?|T>E+ipgb8{h?)Me+9NVUM+{Fq8jN1i1 zw#<5n34Y>_b`HvL0SD%>)QV95w_krOefja#tWGW>KZR9N0V`Keh9if)a_Kch@hlVUmX|2KkV&%(bzH^V(|B ztvm|{*n>1@=B?@Ip>6E3-iMGlI)ru^)0>vujKf468Xb5Np%-UIFnVY38a-*!xb)$l zxj+5xzxrL6o^}l85oBQyT(Na;tR97XA-sB+7ca}PmFX}{2<@w^YXsi)>ATOaOMizK z@I{mBQU0(8{cK0VF*ki&k^cIz=hMRJlUbGJm^AuEe+>F-Xg`ZUvgTkK`Ss`0gt4sX z;yCCS`|LM0x1~ihr=)Q(m`6}1{N^A0dHR{#ucO|h*^9j!hS3$nMpk2b!%5wZH{O_D zec{D8m%M()47_2triUJQfH(>Z_3ZoR_N zXJntnbo`oC*QU{UOzr_kw`{}7-G&{QL6Q$!2Qx>n z?@#~FKSx3E-ZX_(byp%^du=V-UN)yy3+9Kgruk~Qhdky|`gDX`qrc4L)d<+mo%&KR zZaw=}-D~RjlaJ73+hg1`MK9BftIqqCfhgdqE4d*I4ic{p$BAtS#s}GUa1bG4MhFZF zA%pM^DiXqy#1YLHg(C?>FGhHb8;6b*A?l?t6eECW47%W79NPTFeKF9&!qAw^+g{>w zjM?F1)U1M5MwG}yVb7K1Smozl0Z3DHkC>Z3e*twz(LvjEZY3|I0>X0XUFyhKiu}nm z;91U3IUW^=f@X6NM|C;CbBNVQ8pI3d5}bdGJ)HjAs$*ufOIR zED#&h3u|5s*p6nex?6KVFnnvACBWsuUQBl}1$J+~5Ozh?rYmeI=!y>tti1>w zDnV?c_-34r!Onn@ZFJAP58e-lr#zDaoPxd9ISfP6qeLR#3WOqQi4HD(u7W3WJ|d6+ zXh4_0Iw7E873S)^0^9|NcqIz023C5*KLPP;nG>QS@J}PFfpgGI>Pi*^DjLDr3aqt4 z!AqD{2m@HWz$NDXgfA0&=&YD~>TFg~=PVSw76L0vkP8JumIz|pcHt>V~Q6LsJ?UYG4{bM?na`u}i3%Ir7`fIPDty*VbZjM5x zhHVHckDNpF!C>X1AL&a4^7EXApa3iW?cckPalxq_Smdw+AKW>E#ge`l=u5UqX#JqI zp6#;i*y2Myg_qU^hUF#}_qHiF*#!CCbXe=1Ki>|YG8%`ex1{-#^Y%fbE9f3Rb~=6K zfp4b6%p)E<*TnX~xtk^A4+SEahxhm0|(#_ z4jnm?o_*@sbf9@>`cMDnx6?g$-@`G#s;rr7k#lzL+=*|DGocKzov}~|!gzAX!i5WP zSlSdgGNu8?*wBm%)J1<0;Hbbq+Fr@|KKv~HzzSfrc=UJ2=-`QvnClb0+MMi7Q(bt2hB$J5IO*vZ4@RtJF%m*YX0)S~o{3;b3R_?AgJL%h01LW>QCEk0!Q< z5jdUwiLeUKptPb=!c9Zx;jd0(JHn4C$pSk;2GH3B@T^1v>6wusbuwCDGv~ zU_-4-f(s17yDab^C@z^uKQVwDm{8o%9z)El31|9Z!ea&BeR-@x$~*|@aP&ewomC=) zJ~0o=3`+#d2!^RBC~7Q}E|wh?pdyj3jAo$O7%#|EevY_)8PA#QEfi$6Rr7OEFr8xY*79; zdQJ>kjnyCEn_)pP=}a2REBnJVkr#bZ0)>7l&>?bq>lcZb$jd&=?@2>&QFzXYe8nd{ z-RBCtIj1Q0%|Y?RDCF1LSkbI3%1^nzIY}-o@AG3^fR7^?k5i^#s*U;k^qF(g^2O6p z%ynTNy`I(G-K^eDPotZr;F-0RdR4<5G^H>9%~#X$`|b<|vIgOB3<7xr0#p6Cm1!&H zv@dR6mu92s?sOGB+F{)&FD7)3#2GVzBk@k871th5x2#$~zA#N_5L|;?G+|7-@7*`D zkMn5ifbpNp5nuCWP0p)XW(NxBNN513Gowe1<2S>UR+3t#vtX7H4&XD>IT)P3d-TWY zZ=Twe7A;tT7M&G};Ni>+SUcH8C*&M5ob1cY#0k%g8~IIqNBm*W#ckk3fi^>L3%nS5 z9=gf+Vs~Xc=7n8Hddri^9|Z&JBo7rzdw1?hufMjANt{&>RzEyu3Elvj$39-@z&QlF zhB0H)vgOP1I6syZiQZJ%-(%J$N7CQ37zgqg#l|mdJHqe`NXY_72o}bj-C!-7+&dz^MRiX`ASUqC(}Vq?A`87r&(#Lt!qjR z<1xi0eK)H;N6+=7gLuN0nYXPfZALY4=J{xt7dq@LwEg5!jyGiM!BtmHj8*b(ltB$+ zXQgEg)6xsC?14c#j|cWCtp2KiLNLd?M9T1i4}Jv4bvK2#VpoLQunakJ_-HVwGGGsW z{kv(;i54tU>cS^M4_=jzo!FNWjue0C*MB*^3kFfAcQ@RAOTe(M9W>NuU-bTDB-at8}hmPfF7S z;LLRas}slNi!X0ZQ>V`iMcdKi95*>?Y}&H>X!^t z;@2%+$SN$E#M}ZF+KRCZm~Id7t8z)xS{3#R%YNegZdOTk z;u!ND?N)iAfS@_3Co%N)w4r!8jf29IY^z~~mzCP=4c%cNE~rqygr*8mktTiuy3Cs> z<-yMot_bqA^>kco+Ay?QAE}^1(mdW-FVmElV>kXt?7Sll&KEGjy2*TPqvOtf#tPE& z=FH(UHyp=N7<6!K96ec!aHL7TeddV}d8L^8(4YBeF<~sm=K7eq%B32{mQ1^s(AIjS zoA8mYz)^4Ha)gO~Jiwm}ysSZ>cFcHuZ95LZbZmL`Rm-t585aUpJ6j}bIq}0IumGtvcwlSrC&bANC{d21%sSn65>luz$Ob6Jy@F&YD&&=@n-0(v3bf`BW|iPMv7??U zd9vk$Ff~Xa1b9&wao3jE?x0)Xi2|ILruStZM4kn`Az=vetq5478pbhKK;(eQ2YppjH%$vi$aIBr`-?y0q#TajY^Y=YY2xU|Tg*EA zA}G_SxN<9nCsLH#5X@fQL51znmXqlW{z0TSk3RMog8o@fSecV{?b?N<%ipH2f9-*E z>s@!Hf5mZP$9N!$By(v7CY9jUq}5jPARwaa13h?O0!@4wa=%!?|FA9PUP>c z6qFq0+G+SGd>YlDzy)vHy09oX-art z!XjS*_4470_`NvN|0$dEKM0O_c)YbC5+%nDw2u!2&k2lQ_nhZvu7Yq8Q%b5hAo9z^H`>pOO`<7IPwQA;Dvgbb2P)e z(-}whyv(XOLWPq{=zyuHla>e{1DmpBAl2k+?&XmlP71Y501EUHtP8FzP%VjVc>bn5 zR|6{<9JQLOYNClbV3^zUPK{#&b@RENdtAX}YD)dp+&ZW%Lk(9A6P%h%Cw9YxpWzZw z?*&_Ep&6VKOye3RO;T|Z0;A@R)DWH$A}Ldbrd%c+q5eX5LC8p?5ahrclz}FLSUs_B z_LnoS*ToKqK8p#>un4zYaxiM~Y?8R*nS6M#Zoa=5#Ron`5jlZD;y`9Pa^y=Qm=}L# zJ{RxG9R7jd$ST*zT*^Fh#jFbv_;HFB_hKc{I&uvWd?N&$B5J@W%-s|$ojr_8oSe!B z%gfJEVw7P#nHT!Bgs}(yXS%6~bp}Zk8(BfiMB0QHMD-u=Yv8->5d4ipwK|*jCbL`5@ptu5A$7kvCmFXMb zdODqaZEw23`SShLsS?LCw_d*_-F(gBG-^aQj=VO&^wqIyb#v+k&SBCH-a0m9I29&j zm|8~T75xhq;Q18wKJ(<9%1I!)#b@Tn6T0<#9NU9-OPW=%{V|Hysm!0x?i!Tfn? z0fJ7zFPf4a1D$7b?e9Y%L_kCYh{hYoR@y~QY##l$4wLOKe*ODt*@7hqsB%%nqK@`N z?tQ+^S8zoJITv#>#^w4l=V1b)6uis44y-Uj`H)q6#O*Inm;!bL^0Cl&cmBMC{Ddv+49sh zZB}|*9|i2m%>u@Vv5isddyl8lcs?HF zxFJm)J<@UM?0HzS9K_@wkKrg+R=`+lVR5<3e68DZOyR%&==V}L3J2C=a7NdNQf*;+ z?>)Drg&gH*dRf6}2fx-y2$#>C-jwtRzK?AcUA@&|i825T_cZUvnN@Z+H=$`N$Ae9Q zvBiWLCUU{d(FidEX%={8Ztl&GIfAE>-1)|tJ(Shax0Gt72YZ4c^t=rfA}84wuiuKO zQ{+egFvp2BhQ+EUV^h3}d6YhtX>~RD_=yv2D`5Kqe1JkB!;#DR7U7I}T-=j4=vJXl zo_#VTqEXhTyka~X;3r4)Ci*>|McHV#ndB?#2ajZQ zS1sKeTgM9Kl*ybNf>7wm1;TYM0!|x8Xf_`_fkKNt-o)>-o+K2`S=mj&)GO*i_CwX+ zUV3a?@lMMU67USaM46Utjij-ofLZ1@a=lfUng7yd9I-XF5g!f*5mZ_HK$y|_q?Qx< zE07zQ~E%jpi2x6i;WL(*V;k&nj{3}c#?BOhk%lnP09v$0GRra{3G>F+akfC_$4*mc%?lWFwM{-yx z*i>u8YOVJk5$WQSb#z79RebqeV>w=9-VIn2LOrcn@Ids5eeFQjJYIABI&9J1{veFy zeH~+CP-NN{j?osj*tK%T`?&Ezdlu*`4`;8Rl}nlD@H6|IRo zaa~2BC-3MJWc!Y7>C}mO_SCx0J)tA7&obHJqA(b>NW{A! za>jvJxc@JRy7Yrf-MwfayA@@SsjG|C2&_70m_2P`TE1{Df;gY<4E9yFV(1b)MG-`>}{JZjU9uq%_jdgb5hvpo_bS_uO&I4T!kmkt* z#;=o!&*i=_onwXBBNId=`vWU5<8>9v{i>S%oj;3%F5=fnL8((P1^j9@H6XKL{a9&m zK)O%NORc4owN5vf1x&_3!oxl*FT%*Ot#j0ecImxY`ZbbCvkxJDu)mge>rEQxSP*-9 zB;YGa&H^kMI&l#y42%Ex%@1XdQk+rwSZ-X!y@WIRb6C{!eI}|odd{G@mm!MuJeTQI zFz^x9IcVqwafjW<+dQ?EIsdfZXj_p*Il)?iEJ)-R!Zs=ubyK}lmQj{%RWIHfJK7FR z%f?tv86$WD^2}8)LIq%G!-tYY`?HY4yNE^};$Scn!q$R#A+B)i<@-x7Lo##3%~0G( zoZ}OgljXFzEpN@|(tP8YXpYLV{Gm96n?vNqjj;7Oj@S{e!9B%d&0@#0xBkHXed($t zGt;CxCVwWD(FlmBlyTC6$t^3A8k6jWY5mm4Kb)3KV-=XyM~_u=Z>XSi5>mP57!>a- z5#sf<%|n1yM_G#yZ#!Rw-NlQFA1!M^G} zdv+uIu;-CDvu4alZ7^c4=xUUxdEOYEN`e1+X0O9!&y^+-K%qbrLC?Fk5p9^~%A}k? zNl;6A%T(bib2v1%fd$F9Xc2vqF{y04SS7qnY5t4_B4^<%j|*3u#s4rV1(7l{ooQqA zUrt)U-1K~40L{~Vx|-K2Xf#cnl4j1Dmgdf1nhxwc5)RvbuzDQ=?g4y6U|oU(zA9+2 zf{9%s!>Zups?FBsqp7Q+0le44wM^+~@D~990rIPV_rvt`8dtq%#HwtVk%J(Bk^RK5 z;NbMS^_bve{h&AT9++(bHOL$=8q2XAI}WEW|MkP{f1b^FLWx1&X>lgLI&Ok&@uey1 zu@k3QvEP<9?>!K!-YPcQyU(Vbn0y{QemLEI=dCcH4VZ=ETtFC*P6(4FxZyd}ocGR= zUV5G0vV9L8!I!g#A8UwX$6)YI#~fuHPoM5cbLPxo1+Ec=xhp;@=M<#bkE!D($0ecV z9Od|uVb;{x@{Gs-(4|u-Pu%cWsL5mK6KII>H0jlsj%TsE+NZgHjpc5t~khJ#x3ez)XjGpLK!QKKYYv?Etl?_ zeC4!;ife{tWkvvm=i*I7mf6-4PvOQz3CGA%R_`WHnixEcCfW)*vw`)h3DeTpt$Wjf z14q-jQ*H1nu9AD?7kEa#Q54^fAQ}~)Jnp@xxM+*Nwn2-QO7NFed!Fql`4z{PDSmUj%vRw_8@M zqy7y{A8oTd?&TN5+JSh&#D3MGs^LDz{6hWZr!-{`+8-@7M_?G?z{)oAF@6Yp;DFX0 z(sRHJy*r=ku{zMntJ@G%1Xp0uQ4s>UW#_h2I`yJ%%0A}Dy}nj5$E3h)9r;iz% z9nMZ0IL45%twKk5NcZ^WLtW@&1w2om(Cohkg`9$+CsLfpQnmf$nV3f${|bZlo9)wC zr-}jVs@eG&EUg^Z6_~*bH1SYHf%ADQ3ZV{8OL*|Xuci0gcOQzbif}r54o9xy@+jsX zX-if(h%Zzv>c-2Mhz$@ga&SEP!2i%#CQ-~WgqdGE3hxzHEl8jLjbFq!KHq6B*f#if@7!@(3p ziQiah278<=;1xg`k;#;PL@U4fD+soUB{s2tmoOO&2@}+lh`nhP=D6cw)~{YPC#{$@ zfw-EGn#WjUMULPSBhuqh$c8}qMlZ=vksC}ZlNEmsW~1voNcO|9FnNkl!a-`&NCJ&1 z(NM^j(e*j6*!!z+k1#=jz5J>`$P=C#GfaRXfbI?QY+e}&HPl@w93<;9hYIEH9khn7 zD0zfeM`uT9!E^%RB&sG;fklR-kK=j<`L$frXjxDR;W|&fI#FQAlqm32Rie?y>B%Y^xMuIDv0}k=(?DPDSXP;MM6K673J!9Yj`~4M@dD( zGQCxdiNIgtWN!McOxo`I-R3^n+0i!{;EJHf3VE?Z%a9N+VV) zoHu?LleF_q6VgWZ5qDwkrt_eF7$(hRD`6^|4<1WTJpD|n{lHym8Yb3FtgfIV3+Bl! zD~=TfA;+UtQZpQ$VKGNkP*oAe9Ek~YKU)B%r|&-VD#F?%Jb&MTU@y+Vc+hdZ1D#C5 zGIWq;ahuCAY12-!zib?4b*?-|zX-?Toxk?q1ps)2?E{a$_y&{y0;WV5OWtLyG#6uf z*((>HBIuobkvvMJ9LqD0%XS*^f)UR#-kftJ%0YoMkq>!MNns^zvgw{0pwp}itdzRq zGaALA&WZHmE;HW&O*(e?aC-HnS2+_Mb8ONaK6D7@Q)kl$@4r8tICdlp9v{QfRpi2m<_A6_w-r7p-dDx8i&03SJ5NARk$X* zU<7sUBLk!YC}1WG)D@43Y46F7w07r4 zl%;vRszlK2*%}LfSKr2?z?w4mx|lo6Tft;BIOf#?ecrtZZ}l7S&<%Y0SaBJRm*^hM zO)FTfo-v^j)6WS`JgK#_EpYxkirz{Dn|dr1Y7snMcws$?q}Ng(mINKHt_6I6h5yvS z?P@y4VoKpiq#7*88t4~~(qd(0fK{_G4QbuB7S2Had%QJk(Z-xdWEI3hG%Va;wm}58 zyc|vM=P0uq*m`i_z#;rroM0a7hOxsR0&r3Yzv+fmY4+T?Y3u~H1^{beE}luxWX9bm zE+3$R-8A-xjC)qhF@`8xpU!{2M5om%9ayZAfjIOp7onFX;L_qYB_N- z_MV#F)yZ;2+4;5uM}`V9D*5dL_n4Neg!Z|DtNky|8{ZCe)il~~J%S!9c;zys$H9w` z#+nSj#HmPmDcVLP-*S;p{w-5lpyB=mX7j)=@yh++bLY%~ZcYJ5Z3lFbdg_Z|>((u) zzOjWPLA&tlp@0nyr0&(4k%NDk%9Qmacj|1l%P|)9Ai$xdrGxRq(gkyO1&wlSh}+R8 z!lU3jg!MW266-4MHDgQCf)K8UoN|9^mE)0EngU-ynbg*HI-NPmxHm2W+jLGnaX+>E zlga_px!2fy#S{0wpXY4tNfXD1X}4oY9}Xc%QWyKjdb)_xjVE#*BQO0%2q%wJ6YmsM zOk;n01fnM3z8}GSW3TB9)VV|0C>*z+JHu)(a|Z$X`-mx-c}XX;DwK^|$-GlpWqnCB zP{no|ES7-1X3Ul0loNr5yrfHjjxT2faGc-FTarv@#k1km#0J=WFLA>DihCfFZv+j2 ze)-|zh4@m<7LH8^Po}hPXG-&%QfkBwm3hytKaqHBWtumsG3c@8_wuqT5W~~_2KK71S#r9}7Pg_waRrq(GxVRVF zN`YsOmIT0{17-SS>|38be@O_KaTF>2?Vfm|2kZk}z$!4*$&Neg>9-0ZVVtl0?7i?D z3Ns$CympJh!2``{{kk{Or1#vJns@CA zA0sDQPJ{DR2>z$R%M&O@Pe4l#QxO%g9NCMdiltVAn@uPz^*L}9hpO8V@Yk(dTfl>} z<{4AcGZ!}fl_t1l#_@6-W$O{@un_I+igfS|Sf2=_eKtN702%rKi9ALcXR5&k>C z^YJL;RWf)IhsXIHWzLqq8fn$l*95&)h|fMxaIi~BDs?S)6Ansmyy*tufsY%;PzH1f z*9_e&?VB0o%DM8uxmX$T1QJVEq(j`C_$r#5 z{47N#RkKSNDxTe=WnMiDNb4elVO=fR!J;Xlmqf1z2B{MTfdcuNc8*6PBV$VVJY(53 zG9YTG&AER-2Yu|JIRz7btRp56l^Dc|JcP9qvJ7Fso;T(p{HJ5AoWCK~#h#-g($G&NGn*VShx=Sy zB@^ePI1+HT$T9+Vn(^iULd6&V%KW^E2Lnhi2T<0#%!6dXXBE%JjCfXxiC>szCMq*S zp=B;$6>){PA2kPF#ZP|l@sfb@g$QAl`7-}}sVKDU3hr*Tc#}7bde)CN`y?!=c*gj-Ir3+aAtx zZNoIUF0EX)Fzr5gC_VAykJ4<;Tb+x^_u|Ei5#T&yxj&rEG_ilT5!Oyi@3d%l{fq|o6dp`ZKew7PGp+8x z2a4z4W|}|+Y>0IUswV#OP~d-njDX?oam+*%e(jf_nv9_^*_AHwFJnJ64v3TYv>I0S z3OSQdhNnVh5f)v&C^uSJ8A>DD5kSWB62?k=0gtERWG}q_1_Ugfm@T1wZ z<+6CkeV(JL>c^!Ccm%gzRGFr64Ra%_&AutUX)on z`>MjZ*M@D|(YZJ~Vkg-btNopc}MV6jiWlKIP{44EAmPeRO9 zSL#XsItQzK)WaPHi>D9-_}V!-i1vr$5IhQO*2XMgCN%ygmP0r293G(v$v#khDNK6{zo9#uh8 z3bsB+9gF-U5@DCShU2D%SWaZ2v`CmTc{0%}VC>Hz0C0>Z zEAtAQ<0sZ}%+~I-6Q2tco4`fj*bkf?i{)5}?94RE;wLIH^f>fFhmWC9wy&s+yhaGm zq_t1N=^8LJ8+nqjzTw__1E9!PdQ7e91N&AuBWw`n_9>m`b)a~-?>+b8SZgZr*(8IK zaQluOI2Ah_LYY7cA(>pXte6h{n9PxL4Je=#(06R#mAaWn07bOXwphL^h6;fCK(epx zXV1OYIi9CL7|E4hY1r|Tr?IlBLw21O+k(0fl6ryJNYeLXK90T&df%FsE?k&q&6>sB znl{72k~MkIeh>abwlgrNO}-~JTNHvHFdbkEZmz z4&NO64jf?%&mJ6sZb!Jr?+7Q&xF5d;ONu>gt7@njO#kkWekZ;6z3*W>&jU_4unT&l zfM|Qz)`IYQmhq;w)f;cTk$(8p(|IpEbVUV^3t(E!2=_hBdw>f^a$*TI0|k!$M5M=) zusl)OqA9+3C*GXJ$AOM-Pn~LsG3$}B`diUjR;=^SxyA7)T|pB`or=??=ob|N=7B~F z7;AkaZE*n%_=qsVif`Y0tRFW%aS3CQn2$dZUd%V~1Wf^eZY|K$ehZdszyBwHk~;C{ zb#}|v^yy#zZ2F@w{Bg|p4Or?8a01DQ5o6dQH6}gs$YUsKJ8&3#0+@BB6)Uf!?7>iq ztX;RBeqp;V3l*W{VN8|$vr16ujDq=2R_b4R=_PpmbHQ7<%I@hgDm!9(S=1N$*m*W+ zU+Y<{c7TzVbej2#A1du!rPom*Lp8>^^icXD6r^wdIsRii2=J+@#xW{mLi&6h#p!d; zJs&IgDpSqW)%p_%`uYrOq0h$PZ_NIcK262bzvJ>GN{|jLdL~bvMxC5ryaaNFeSkZ{ zuAHySb6)?8wyzu_Z&!UMQU!aFDtg?Aai4!fkg>Bfl_Jo==47iwm&863G`l$O8N&b` zV8UT&6QeKHBH)jLtHiet*~w7FO_bpTUNQ=0{W1Y{;*wpoJcxr8A+Bk&IlRe1a$X0k zNE}x#thd^584gXCEKi3!G4WGl%aHh(uS}Jvd-;xp@t+kM5)8;XlUx=;WTSDqL4FSI z+yAtz+=$aN=?1dg&idPVrTiV-jb62dHZ4{5k@l8F^IO+>luLt(^! z)GGq{l7N`d_Bt_`ua|8I2n*K;$!Wbef0=WrB_9bZKO&FeanEy+%4eCs{2LkNFTFjwSP(65c!c#u&f3)F#-0E9%O%Z6P~!4gow9d)$+9F zfn6V zK^#R666XGC&lj&8$zEk9%s>3%U#5TeJHNqMtuwKvRERe}SuV$V*(f#Q6)<=+(+rNr z>eE~@;F@7F6pi+=)iv$p40I>zk*qv)BZ!Q^8I75VPlC<(Ly$ATtIVYQ9RhcG!;9iJ zCn+PAzd4)yZA8K^dF7-1e@SqWFEt{W&UifPONyjPYV*E*=?p6-lO{|FGg)bk6My44 z936qTx88OentLaIOzufDZ_$!ClB$mOZ-U{GA(%UV0mA2|5DEr>c|WvUCZh$*h8?^2 zz%ZNwPB4U&UqwIlcvIFg@Q!DL0_OaB%U_IxVhl%M*<^mDfnGtwQ0hnz!}%2T*L+zr zl}jOVG3FxsKv^>aSAB(|SW72qb;Fn@ETQUPs1P)vNh4t5`=DhZ#9%(+ICcIA!H7_b zq7~9r-&tR$dqS);Oti4<&5;PFKHzgblh_`%HhlgUKbCI4WqGPZD5|9h%{jH|Rp4;( zjqKQ31*6XW{AIJ#mmd5k=8sr-f!6~lZ-br)J3bXe4ra}^^QTwrP!z!JDr@uy{ZSc^ zXH+UeZDgELB%>(k>QsoTPB&cpt~6)fywu!$IPKfdnc$Fog?VA)%KWU^nBPyBl=dGy zj92u-FtMz(Az-=XO(9P+P*?Sw55+@;x0r8%e=$7_(Z3LetUL8{f2Uge+8P{EfjeP^ zAiPLqUaeSB?B2CIo@H94FSgfJ`%~=Mm1Zi?$$tb*r9Ye#Wj=+Ib#VT)PMYdFx0^;7 zJKvaJ)VU~A{vj@Y%XusZl;6Imv%HF^aa-P(zXV3C7|>!#bXSqaJ`+bqqzN#}<8ee~ zS$-PEjH4Yo=V}KYeH@E8GMMI5o}W$qwQj5e*J55)!9iP#+E|U@Rm#t{gTeuIn58=$ z!g|7$YH-ClJ>#{wZXL5SM!1--ypH{99QhY{7FRW6<=sXRUdP`3dW5&0bL|N9({Z4= z5O3j2Luk|V+S5x8961U=s4JN|_UvD&)m1B3r1#u&5A=67!su2OFgn;0bs+jCD-pmG z;?J1LncTPCo@UORg=N)v_8M>EXvN0@f6PaPl5||Fo1Z~>ylmNW;5H?2VKe!@{>H|j zLACgLIf!ZWb*rvQzx#W?jYG-tq;=k+DU`#1T!p%c_GhaubXzROByj&MLf9tu9>0Q> zLAGX~GieYo0#5X73MPFbXu@z zUYfgLD!ek*N`z@2q~cXBt@DG2;vA3}Fm_olGQ7!8rxxNBef?9bkvKKHp_Ojoa5 zmfSdW9Kr3y7uI6_y(i4b#Ywj=%)$!G<1HI;@OkH*w};|o&+dKrmf1jluE;}+sFZzq zjMd}JBTJ9-Ho30uleD)o^3rnk0z#^ng1&Qu3LKAHv)$)V%vGbb4ClP$XB{;E4?KbX z=JARgP&*psUOT6Y>_}&2AfQ3El#;g;1<}_yxjtx=bxGnDlzD-Q0@<`t_#*gt}iQERb zbMaTq_x}{Z{&EE39|NK>KpYJqQ2dyw9S7Dhwqii4;k5H(qLBIWKd_33G8iV0ZxKBs z+!!W>d9!QN^;b_%3unzsW1(Iuet3;}Iwo2mGt)?F!EDOocw)ie7)jzX%+&}HF!py5&uZ%M&!NC<853u2X-*q87iozo`Bq3X zpU8_`{S_b*mRM1+oxsX^7-o5{4$4fFTM?{+aIK`xuCx$~eDma)nQ+=^jS<3yoik7r zD6$K(+}Q%x(p!M8H39217e1Pk&Ab1&;GPMI!W z;w5Q;mkemMTacJ%z=e0T*M1XQYz-m&EHj$-%Qson-R@HzNc;E9c++ec_c@cHKcJ&(tVU0xC32~ zah6dNAHAeEod`h(@CQ(Z)D`<*Lti+u zyWnp3?%$VgzWEN0k{Ziu{KJ?JPv_{KCotPTlz#q`pGb31knDn~*}*DZHC~T9Fy-EN z@OT=Jlb!S3o;>1s&b4=Z2?LpY;hr(ZagaZkwlJRK%SJi3d z9BmO-*axbUTytAq5e9vt?_6>B3}R`&FI+|Afx7Xlpe|hoKOCM>XEWm8IB{k?Wyd2m zaE0Hhg#`}3yb9R%!_am@Hz%_{ofG(=1+09LU&$z#MjqEo!NPaTSlyq_UddD24q_!C z;fIaS%_2tbrvL5n<`7mPQNnk#($a~x>Z+wn z(#+|z5bF2y;bG~Kz){H6EOcX@=M{QygcYT~+`6auDmj`NK5EawYADPgLAI z^Cheum!ex9k<{;7>l|4@VmrcGbMs!zmXC)Scl0H3?IVgqiPVXJ!#U}U)6*z(+OXpAI78=B zx0Kj-zEc1>!Cv7RGp8e%A}9gt4pviJ*y7Q}uZj_mqSQiVDkntDKp11UCuYrupi^gw z&lVyqBfH_5`WZ}Gp=g2W2?Arlxp|9LvI32tCRWH@xei#0_tJ=x*3&-cjFBi{G=jEEwYD|)jTLpb!R6Lv4md)$anl)>(&`v)dJahz$lw-&T9CgQ>qa~5` z)vC)&i-vZN@zaW9(&35WQ%9$IT6Y-U*vK(_%r#a-S`${Vk@Cv=D(CAfqE!xt0{`FK z9>;|*ic3V0AUl!E(S+azG8v`(mLU<@#?$$F&Czfclvf%uD84la^l6xR1RKQ z?7z%IN%$3nP3s`j9Mr7JH1W%$0zqiscxheCL^x)~DCg&(HEER3O|@y@`FhbJd%khq z7>@0$hLMf}s1NU5-3h(|p*B|WgAf7@;&@U(Zc`?bLqZJ#n#4;%F4w_^ql|FHKiZz# zk_WQFfm+tAnY3}P>e)B_oSiJAU>=z{ARAWl?5F5U-~y`?3J3R~1%ZZ02=gG^#LFwr zLPMB15ek3qgs)c#YkpzXqFsS=wB5G(6OqgTe6Y?E=+Le+DMpz_B)`C6CTGjaI1J8N zjAh!!c*u1yPbU`tE|y``C@}Ieoq6SnoOdt;!SE6m?}!@ZD|x=-%eY1S=oY_nP+4}g zzlbxuZbK1`Ueq&(b_bfkU_>Ir=q0^2rGTPqtiFO`K@$t->P)yt=Hnwp79$KQ3d<&Pp3`Wcc&(p z-%2Jgh44*yrG4p@H_|<~Tu&IL^k;g~`mMWyL9Rx*rz4vlh(!a60QY46*?<2=y65_< z)78rt;t_uuE0H=MVw^_{Y=;b77A_4cnejXc7f_*{$K5Y?=tLR|jd3+r=T(``Wguku zmQW<4z>)H~fD=E)4xsrHcu_nF(EPHvDPU~8|Cg89Db$UmFWOlhY2I@n&6~Cy1;ug3 zKn)f?p83vxRJK6a_AsetoJw{~+la^C-TMy3HiW~+PNi>r?`bsjo^gFPooek!kA3e4 z(CxmoXwhPve=SK(C{%Q0=4l_A-jBtr@i)KySlY=d@P@6;X);FvNdlz-!GKYy4lUy^ z2(CaVKSiUdh#}==zr@%lz$Ec(ZG~mvrty98=5+CFv>0>DAH^7shDJE~#*Dy&R|xlU z69tLeUh!Q-fmlRXSyt35Dx2wc&|BiFKz1ugJ*g`IKv;W0XSx|D=U`Y9EAiQU9`j~A zEDy4mwGyFkGmh+zo@nI+0?u&mB@6{aWN$n9SVi&9{nl1VUn$aR8AXptVqh{C$&|t5 z6Bf=6F`?~cj_AS*{o+M)(ww=o(vEGI-y`7YD?_@ZpBMALYT4pcgBQx<2acrEXIj!Z zj!`-b&fIpxtuX#K62)_;?MoSS6d=}%3R)L$d_E7}9VTy0d&7K|{&rPb=UJ}8p;m!W ztxOZA&%kQJRW5be9uHO-Cfc)R&II4g<8Y*xA(r0UbmNWqeK;D*2Fjtmp?DxJMN@bptjI4aH}u6D!;QyH2p0Jvq6>q_ zi5v5a|DvCCI_Bz}b#M>z1q7fT#*6+!JYU^o+Y9u8mhcuT&9b(JV$#SPZ3^ZVR*E_K=6n7q4eO<=E@ty_7~>CMuZ{# zF`TNw4vPNQe0K~cmYP`~JARTQw-6RMo=iCDa83)&*kjJKwA?zL#w^|igci(x_p)+G z?f9cy@Wd@%3Q77Ea&^#rv><8TzZX6SMK1JSFXqC&n?9X0b8_0g^&<&&)dE!BDaZGHc|{O;7&jKg z_;n7+aqS2ARg`K|IkD+`Us=rwQRC9P@4Pb|J#;KR^5|2M_oqKQ1z4i+hMTHl5Bl+w z$J0I6EKmRO_kTalMyPK=Ab;tl7t>#T>2K1jYq#Pf1gDKFZvx-wGvMiV2Zg>9$6C{0 z{K?QRrrpsuTO{BmpyOp=~OpkTC75wkHW5w zs$FnXS>wKO{cVKR2RLNA90QI&>6Lw5jiL~2Bg{SNE`{lX>OB2}b2zp}nQu4S?J76{ zK;^q}RTg5h7dTVG)nOc`Kn2bVYp(b)e#YkAJ z@^a2Pa&L>V6bk2IqUrX3sFmwD#pH5;fuVu>}cib7rPo82=d_Br@edW|}LV^u+E6@J@ z`@?MBEiNJVFt)5umThnX$as7Fdyiw8wVz}BZc4AOdmRgyjnKvhR`JKuPaM6861Wmv zaqMY{VPB|F)hVFLoaW};Y^k8XQ7Y_5A-r_)Qt(?Pjt(*d=+x)Rysjw0zU(3q^Br{? zi0Wi7VmqMn4}*flplSTpAT)Xg<}^&JMuEf?cpTMR@d$+aIDV`s=xkR~uQYgK1CX1NlNgP)Jv(Kgpojf9`ae*fBnJLZmet8ifYD2F6wbQjeLDdw%NBka0(h~&~9HF!!E&&H2b($Us=D_DXktjIF$^%rk7R@H(9Mf7n zhlb4p3_@^!CNvGq4!`c-*L*FU$w0NLT{V&5S-1`I;+b>F_>nMVSnvaE)Cfw_vq_}C zgP65S3}n`1)O9#AB*;S;@`}EWQ9N#lyfh1@@u+vm2RNV&4rK;U5+H?X?g-DnmM=pw zbWsmsIK-szA`|r@hOm|zTVdl-C;#+05T;wgj(0kql3B8@DnH^9PVo_k`B0bma4*cQ zQx*AzV-oU+IFw~k*4BE*jrkK+sbYjbupmC%62m?(nDls;6FX*N+!*PnT~QciMO+@r zB-Xh|8$mt<9N#8G5%-eIBsq^Fry_6L6L08>h$Bo06LXwI#Fw+I)@Xjoaj0yg8NpsP z_R`h4DoQ-!R3O!G3yyYzN0^(zP*gGQ9{9me(ht|X#6EkJ027*6S*u7}cOOcf^yQdw zQxPcpu*ez5M3&McKX^X9{>u88h)!~b_wg2-yRfpQbDpde!xS1Et;G{^Hx9bK`S`PV zX@7(9(U;!$o}1I%cX2j38QF$tQnVpI*i&Mr>O-$!erfn#7)C8%CcyZh5T{?+b1qXs z?0f}8Op!mr<}z0>%H^wJI1o_@AA&If`Tnh$yiL|`iD+3~)ioR^1Oxo+voEmK;e2}O zxhFX@cN4H2#p=X0;3AQV@l{UDVuj~~Z``;g9X;Ef_Tn*q!OVGS?Z%zKw9T5@1Yp7I%srSpsuA!naEMauH>pU_rznSB6Q0m7 z%L-<_(*5UbQ-LOTcd~DkGmjzRY5B6b_z;-FF-^OfFWb{ZykK{BI7sdHsx)`r-0-Ea zYx@S6!MqAMmesR)n4^wH5Z|?ZW8gu+fij&>vLG4FFTaA8J6|}WJhrKeEdW`-XC;)C z)&9ONo_oSMoMyUSWETu%S662`)p81R*g1h?J9q620pB^OX?zo=*)vc~osIcO!7@B- z12~N?Pln90pnN~X++>g^jD4-{aC;@dJr7QxMD{3D3#*hE8qLziyWALiU>w3 z#$Kl91`ySGh1A^;N8zP6>SG8+qYzl~{3hkW0uMSmcH*>DhajqxPL+t^iQVMIRg@l2 zVq5+*_k3j~Y<@ObR@O7_q`~050;a-+?G{d1(M)QdRcyz62%h9=vB;Hl3iZ-@_o1uQ zIdK|~>bm`yxuBM6IM2Q=2VI@@~hP%w%jO zmg6O!lQ}+vn z5#xH4Nf*qe0rJ`DclM!#f$vUVbnFt%wrpajj`5+56z=r&50>lSd>sP6(+D2Wq(V(| zgmHWQbvw(IS8YeA0k1s$Nch^rlp&Aab@sN8ekqvbb#{ezqzzn*JoUsLY9^G;&UV)X4mHq9ou zO@nTM#>D{)v9W`UK+-X$I{)zSGWrOHAmPW4AmCAuW_VMqT2?;vQgcYYU3@I{wjk?_AIem*DVAM$YU!1pr%s>1i0IDp@|WLK zmUE=h@~mIK2_XWTY2^3Z-reOf^yIC*27otWJHmWhZ3yeB*5ujo(ejrc{TP}WpD4ff zYyU&e@;`*uqz#xp$J3*C($_J@jy%0MpE`rU7s1QM_1=hrk;{eGM=S5CC!a1)JpKf` z`sd2)UjKT=&yMtE>5F-a^VGko`Agx!uz%?|JB+Rlk@}u*d+4Q}O*|Vkl3u817$ycE zW1$Wv5^1fbsNiO zj00%}c?JfW0A7(3O2$B7?ey?5A1(n0X!N* zTtkEul5gSaWMO=pWx$w*{go!9!}3bH;*x?N@nL$G!>Z=VAUX(VAe5#$&q8S-yOCO7 z?qiav(*$s7i`UgiYgF-mTv6?;U%cH^^|=O@X<4#gXY{FcvPq&v2Zu=9C_qC9K;loPCMEr2pE7R zjwLQK8)72yAYf6+m+-X6NGKJz??FAngqYGgHaJpv0LTy-ahATwi}#eOE)?k{u*HE! zvSbb_b_0_4x+q9d__75hRJ!ca6403_oK)zKbwO0iVEJ`zzLm(CINm&9N+@jnGf{Pd zh%ndwHTL)Tr9s1#3AARHh?Xmif_?;9JYUGIdiXidwe_0k6?l%_jx(u)M0kNyfmf&o zDy&lo#AL^g-lG^ndc$jWmT`8^AAIb|a?|yLSaDUY67@CO#U0(;7(wRt zw8v!Gk6QgRs86cq+dr_fEQM%HGl-PmPmms|0g~dCWj~C~xkG2k*YUXw27rY&i&lD6 z&MUJ@ib1jk^s9~R`l+onLjt8BQ+& zx9r3?5fW5GSr~91^R9i|?W{n#8#>FRki{{_Nz7##J0e|-gDHe#8uoI*AGqepo9z~j zBHr|=i^v)x9FIOs(_fdsxKDC!``eE_Q8p~;DOc@SU)HS|DtmYD;ymax+<8x1GIm|~ z_Cq7rarV1lZT=~=EJhKS%jCIJw-FWQ#msBFcRf(fXwa3cWJaZZ?t-VyDk2D@-p%-M zoo%UHRLVs5K=@r0x&Sx7Zg$`fW580wxtd`xt-F0svJi2%-go<#=j`pvGU8wQ@|QEO zsE+DYeCD+Rfnb|fi`&*GxF%2IDD0Q+#J?%0_-y-{UTwLP&_d61ZIapp45)2iTf^T# z;J1xQ6v}1U@{gy^#fkzB8Gm=|&ayxlXTjPJAK^}4FXwevva7Fw(5WeK;$%ir=X&9Z zcVX)0iim#`W*tn>F5HdRs;q1K#LWg5G|uKiN!e&a>05+Ej3JMxWT%wTtBK!bz+-2OdvUcri(w}942TTM#3ON)KtL>0wHRW205X5VZowMyDr%?}f z_fZS`E7q+kJFdEp>yqn^)wNTg=G(#Rco>BPNk1%ha5s4{PM@zFkk1M|VA0Zn%DD`SpMC z>j=6qdP>^!bRhZC-Dp_-%v)YlF5kXAIC;7_q6n^iUmAws6MS5I!wqHa ziXpD&tz5co=NQpFivVsKO~8A;b1yt=PYhaXfRZN7T0|@J5g5{EsY1rJHdnk&MA~m= z=GRgQuLcxfjxlXWsLH>KW3*>Zd-DTh9(dwG!*uU?_j@=NfkEP}o8e(rBS1k&4sWgo zq=J^uf8p=3Rq@tnQMoRuGz@%Ddh>Kqukh6K^ndave^`F+_x^}Bm@0qv=l_YDRE9Dh zH8MHPpX(Ua=;ht*b5+xV_GIm|d-rbEM2pL7U-KH&^;ZE|ZQqIV(T{$#JoWU`(x@cn&YCLi^ZYCfnNQ`Mso{>0dEfNApIi%bUPSxNwz@_1!3q3Fnbac-cR^q^- z;PBqE7pui2%;Mg&K{*@GB;#&}Dp+Tb9J(u@kr9nZsbZ-*N*^6~7zw44cdr*&r1Tm> z;~=gg4V!Z6r!3g32$kGV@pQ)n{)oP* z+7f~Y>Nrh0H8rN0B&OL77SA$T3KZN`vme`^)j;rF^f?a1n|Y=TO`5u>H@w2&E#Vmz zNZGBA>23FfrR0HF^8miHK@BI$59Fw~<46Z6abWr4+L!nnZh)nEA*X*6v3Yg!X=4W@ z>8+b}j(^~_z)g-nxb9j4g3NF7N<@G7(xblRX?(|=IIaMF zBtgPEKj7Ye`T`-HDDz*WLmq9oz|N?GmksMTlq9x&@=Nh>`vM4!HL|Y zIgz!-%;t7;r3nT>zq{(o*dowm0%un^vFMQz(nOEd1D&xN)^N7RKxl7#Z z9G@C?QuyvX)SeL~vy{zPme;w?%>mzK$lW1!AuNv7ii=AXOjmI&WtbPhYlWs?Xm`^- zmPI)EN0jsn%3b>haWP*eUbR!>0`@W%FDq9-A33%(!ZvI-^Qa5W8E6{aLh=J1%+CC3 zp8nQvUvN!+^`qk7D%%ciD$A1(BBl2l0oRsK+Y^-r8G#s9oqrj#;6$2fcZi@~K7lLL z((Xib*R`L%__FIfn>@|Jhd#&R&vH+&$W}XWaES{@@W4E*TKuN<>oQK=U>ITtKNi|i z<2R1HQa?g>d75?5EDBtnd+s?F-G_n2S$Fy^trcEOUPHRSW$X6XS?Xo;W-+_^M-c*y z!#f>6eYSksm8pa1;dArO1E9OmlGH*yAlIb&)Z+cci3e(KpLIU7Bc1+Z70 zO6o>NCSt5n?JWDEZ96nH$QXjZJO$B0n0Uw6z7wNu?|JWg%NFik-?i&;j=n7+ydS|| z7rXa+%eKomhxSi^r?cZD^oKJDc-U!&w;MxfrB;QDetE9C7)OvqKe?Kn=%L}2(cFs> zJvz()XU&bLAgR6fS$i*Q5zL<&*$0mdrKbHCcq|v%RTuNp)lgNDmibx%Q5v8@ptuj| z1exMf=QvzUeqZ>~m&-T4`StSh>#i#Ay8W#&oOk%}e(t3|US9Ls*Rcqn;--P4IXW_k z3cS3p3w!NksG+EUa}vJ7X-nYZmX4e`Z`QL{_+_0!;cR1tTM8}DqG2MP8(O-!tmJsb z!2|oj7aE9cQm*F=`?c3zSJq;Meg)bPYQwC6PPnLdUGX;k- zsuDjkb~5vaJh%1%?!Nn;@~40LVT?=u1aa4uPa>@Gs>8ae=jJBDPuDNtQyx8nKxm2^ znXXHQ7>6sk8t=@Rk@A(Ve64KXj!h)!v<7xJZrmI?d(S<0mkk@%Q)lU_4%!ohStP&?oCWL%_tVKNYov2d#0(n8P#6u;OtA3HZZDkFIE&$2?L)YesN7ZV zHKpU`ygLKLGkHpsN0BlvWXIiWSR#Y~mdw1Wg2$1ji76S1zJ;6(VXLIsz?OM(!Jc}`NI=+RjAbeg9X^yrzrAZmX4{~nmlbMyme~V=LsXX zfQ6O*ZM;sL8m03q$krLxZ`(&FGp(}=ZCkZ9{%xE#opAj#Zu$iQR398v343;)_-MPK z?IWWV0SHvGwlaz5x%6if=yKws0(L7sb!w5vu!#_n5uGK zWfXkP6{CT9$wSyMQO%s6KtRQrhj+aub9`#~d^QVE(>8H^L~XUHN6Yxhq*%>LB?2V4 zwclp!rzMkJ=S@bo3&0%7<-G2h^6&r8KQ5bA50}-PNq>g3lOO%~UqJ&V%k`tzGHy6O z|MYIu22XMQ-O;jWISXxeEzbqNTCdkO1Gr%9tMXp^2K`N%!lFgPgwnKG7px)-d{+Z! zERHNZM@y!;E4+*Q_IhDV`WQPmp?bJuJ$EY8X=kXMckhzWnm6^V?Vk3xo-LlpN4bku zX&*hpwJ$Jn94LXA=q;x)bmcO!YBx0LEf)}zD1)v+cF^d%@#g&apq`w!V=NA8Cdr)}&xzq1&}dS>_2sETtg6$bbMM`jctj*p#2TW6-M9o&qTPItNO)>|pj zG>iF>(mSvu_xQR?GhMj%wuhq@sFU|B90WFMz^X6-KjjBkGVyju>3PP6i+x$Fodi2Sa7p~-`6ZG(2) zB=;0ri1h_9opxRKF5b4tT(2$I0PeZo0ZIwb`NHYr^ zpP_AZ!pIT8ppl=Z-$_5yh7D%gei=X87i6i%F8vFf=IML-cJ<9~`=gLd<~Ldx)Y*I9 z6-cbYXw~?{fwE^0YR=r$uxR-zXdDC;Ov!uI)&W1sil=?7&CfZ9_gef~<}r6h?dwg( z&Wk3No;nolGfBbIzV3t~P8UQo#6-?xM5H~;UH+{bp^tZnGtDr+Vu+DN+yw+ZD`EQo zoA>_|ai$Sa?B?&;asZ?A|$g)5Mxx6*RzwkJal6bM=pm@vF~H^ zs#L{_uqRbZEzXq|Cb;DUC-Qu zK#Te271!L5Huk8aH-Fsz<~NnM{qQ>xkZ~0;wC6C^>ZReHL%#V{SCzBaqgV`oVE=Zh z1)|_d!KK`fOj%kf1rOfsdw#V}oZCiHf7{MB?4y5w_t0qhoqzEQWgFx6_>t$z9bf%? z`PcvEe=0jRY%HgbkCkT*oQ6MzrzXCJ0k?14jKGy^?ng#3jCKSKDtE=*^x>EfHU~Tk za)d>n_o=%XCoek8d_4^AhFN6x!mBRhINOacySjY(GhZmTyyms#8m#KS>eMUBUF;OU z<+k^;I2{A_!E)Vo*F~#hHP_n8&pPhps})SRd8MX+>f#D3#g%RB;?yhDd_R2}1BcA( z8sqClpf!oL_va2CkC1K*zvbNCGQ>i(x9b1`CGbT@iB)|1KsElzb`JT1E&2qQ1J7bF z|C%w9vA~$IO!lccq|I4TUPc2Cn<-zv<7?&2=&AB!?|UCw4VRHd!EYDBhq{RW z+Sl(u;Euu56DL^wyMZZ=N6Xgjmy`C}<%?hX8X75Akgh}v#tknw6{i`?;zvP`T3PPi z=ZfHlW@xNWy6O!FU0rBJK?7X}NwfFu+ee#@mSKbsZcYlkK|Qs8X}D(T^x{;eb{zAn z3x~=ON-VGj+jJ0nafiW4vFtc)`RHzWm+0u4&QAl^DDF7~y!? z)tkyD2Ior7?X6g~iUwDW14%p*SSnKcHs^Y&R}2%8Xy)AHLCh_lI=puH`Sxm&~x9Eg*cOR z%69S|p;IOvVId5_w6iB4z>p<7!N9aU5D3+&&yJ0x?0u*aO_G1l;6f%0RNLKQrruFs zV?ncO+Xj84m~lI0i3#>nFX8o)h^j62#NIUtj7~`9Lh9tzeEx$TDFZ3mVwqUKl*JER zTRsVGv-F97`(yWUVVQs8si~BcMupr!H;jMw8>7s3rtwIF0TC=1!T+{B@7YlV8NNG_ zPuZscki5iG^WL_}MX&`#gie+fbeLF$A@K)pU=i^=XTzH8YZ;n^6s5+=Hvomnc*<3Y z4TF*0EGA=x7YeE3%uj$gab=r2hDn;gg{YDaac-^;53O1Lwp$7ko3 zO=ZJMCQ!n=;C952>iy4mwgjle_ezs(PBEa42_^Oa}VA zde!-^ZD84*1hd$i=WksUCTi$OgEZ2*EMkq{wqqc*KO&-if1zi^k^Rwr6ZR5Vv*2N- z3%U!pI?HZNH~1MqK&aqXn-MbC3SY(j1s3=AP3zFlZq~KiFJtim{W3ekN4TCx?Uz*? zzgfT{OB^j*I)pK_5v(4c3iG~g<7H^fbaNN?dfKIrTML+*V8G}1<(57LH`LYoPODKR zo|q%zsIHDG*frDk@yL4(>_Xrx{`-1KLs|O!p}U;#icpU}T-&8Znz*RrPecm0_Tvf* zpBB71gnsMMmb-oGSJTxnvZYVRu#$J`NnKf-D1SqDi>Vo$uhAyKQR)flgMfDTOqZ8m zrsB1TX3e)hjqr!eoul-s<+J?;DF??R*opkmKYw3& z%Nt(iz`)O>l#?`&H$YT+Z28-9?DKgp`CaO3#C9Bt%bHLh%ciTpypX;L&bypNZ5dn!PaEg!rDkk|!)R>)dTuP+=ZD?5?A>gOJHWaTXpvPIcZPv?}ay3KEwsTfv!e&drm* z=j3}()At;+npxYnT~5E41wZ?_KYIge%Uifc^Gx!bW=!>*k~E*AB(WqYm^oEMB@u#<0M*0?|%C`QD=S?$CQ@F@T+{3i~C9X z&MZfnybaS^FLrQ_dEt@;<=!WcutWa$<=(sRWiGi;)^K&}FaOeii!cJ=HMG#a;Bm|@ zXk-t<66Z$ehEBKOJ7Wfq^yAE4^_j-h(NeoMV;l(V3J)XTU^54tU%-~tIJ~q1 zvy})$TwF_+!m~rGa9$K0|3k}?V z_+-YjwnAR<3baz$RGVaz>jWAgBM6KX>^o95Mk#~p8o+vpOON}64%-Xqcc8k1YsXU> z2Vd!+gmDr(1s>JZkhIr%Zr!@E{K^ME811F4Teq?3=W0*-w+roa;LOcK;pVJ7E$T*( z%MW>_j5QmZ|5>Eh*UYW<2?L}7y>u>lBn3&@6FGx0+~Y)A%U6@u-EraBrfcCnRv>gb zi%|W}@7#&tWvJZ#wqJ+<@ZoeA7)gm0NFnQ{Y87CCPjVIcKOB*U@7ZKnVI+w2gA#;d#~8CCVV)oiw|zi#jJ$ znu7OAV8UEw(vXqJl+UD4Razyqro6yJ;7lQHF)FkYUx+f&?sRY#FYkQ)4KP;hHaM{O z3sI6o;D5InQ-&}(>|A?=NRQGk;UOuKxYYq>_aR5}ouWf4k<%zi7g8!Gm@t08%48Ig zF^mrbC|8J4PbaesSUVeVW+7hHXdUGh0XPSslcYK6G9alVX$6~Y%sULgvUV}=f| z1k&)-jR>lt8-5;Du!F}Anu*}a+VGD5yof1>0lfHLzdOF2B+q;KK2a`(L6tj@n+yWZ zN#4?lleUa5WLkDIW#`BADYCOVG26HTsiVi~XZtQ(+abI@@AKjK?q6Gm_T6%eKcD{T9~?1m`xx6YM^i8k zlB0|v!UM#Jjmvlua05K!h=SaB<>qo7e=fQsoFWR%lOtvE458}O%Td?!_|TRu z+sZrM@gvZ1cHJVdRCr0M}ST9B%N@5CXVb3_}TmrlLyGgH(r zOcizZXp>`IZJ0V<#b5nr<9iiVb>b`4%CojTbi46$9{N=0j$n(bWrwh);|n~wz@ zrjogiNy&w07mEYg&^{I-y>Q!{GB0nt_0{E#uX#lnDBHLS!_^Ez*lfw|sAOolQYhe? zbH#yg;GTByJ7sRdrEY3hWEY8i*C^1UUG0C8H2X!ImEpf>0Tq|``g-wi6Ru}_j3H3k z1i+e`!ws32pn+s|t@Abg(|ATrn4`A3RNWXRB7DR8P37l)_WkAefA9C0FIlM5pFGYH zAt2%Q8Ryj2)p?%wW8QRepEN8$$5F+0Az}PU=45xx)shh3Ii4efL*_Y}rf^$G5RNHn*OHz;T$zFK;E!U~R1i2%&=h>&QbLNBSWcvT~!+(n4WVEbZx5`qo_(q_Wg{in; z_m;Y^=gj&OyPhcb-Sr*l3^tF@z^LR=29si z``d4p+uwS7`LTDR>OZm&Bq@ACTL5HsLDTJr?luSEJglECZRXRq0=enCjaRZRe}lc)Bcrofltoz-Z9x>M~u zc?@Cg@am-qP^vLP&vCnGbPPFX96ofY+ylQV&+2Uf3pr}%JhpYqmIwjvy8AAKF^9>; zd4f7qVR_!g2#60KKE{I8U12ucsN+(OYdA;S@4Dz83OmnXlu-@fLA3f5-ds*w*+Vq~ zt#DGUB#E27-f`uzRj+YYa8t*NSQfu5UYYDvA5XugD7Jx3GR6j-!tULa)5Y;HT5Q|N zO9P+c>)B_YWoP>s{qGF(GuhFo(fkr_pf^u}>65YKoA3JZ7jJQZCL!~vyWVH99kGH% zy0pvd^t6=U+w0x*^g`n7+_{r`<1dTW!xYDrG*YVo^!n>>0EU}`p`u`G+46Yk<`+r)7z zJsjX$+8J8PT(0(oIJV06S%oxT{Nk4o!n`8=!!i0&b1(YBUKGl7&0wkXk#BypjBq|= zIaWOpg>hcQ9U56&8qtV!y6gn-%vp5?^fUvF%L*{^)>{UUruAdUqz|II2+8WAfn^Yf zYF&4lL8d{w8U8$Xq!3}60Y8O=b;8{@;CSjzQ)rps=+x#cv2a(Si%B3vl7;6CN#J;5VJhu@y$xxJJXn ze|E=Z<*1ypA})B8(j53@tu z^Qe!RKKVdQoqUXCnVfu>{}^oUkZDAzoI8LulFqM70>2jn(MdS(<$J-drKk}v0^j-Qyv&1k$?Nxt zQiJA2Fhg-L&ub2v2xtSEk`XsrB0O6c!ry+(d%7c+vtXAX=F<4)kYc2@>Q|u8%cGN9 zQyxbO-6?&d!XusWQ{4PCC4r$Qf7cw}%hf(Y8ep4J?VVbpHpP5+jbBrz+HdLzNjbkiWMRNacACb z9=vwo_^xZ=)~~tW`TnNYJ^$JI)Np^(ukx&ZmLswFiBUofHdeK0N~YEt^XEeP(IR%R zENwKb=mSH{b)La)1rimSv^zbre$M-yUtYcIx4J6gLN(CFj~B;)g{qGl(=s;RCjSAP zDXMGJ&S9tx`To!OWlk@n6V>*#a6oG!R3R2)nfa|3t)92N!Ie<~etdimCbb zz`F>;1%?c>E^R@j?5nM#>t;h?5S}Q^C}GaU!gl<+(2$|^Zrh-bJO z1KvMf?F+C2k7aV5#`)BAQB7FmaXJ_K9xd`1Kx=&0jT0H}v2n%{`HZmR_Cs%fNBQ~p zzrWn{s#oUv&hykqO`cvDgIVHN1W}*RM=BHKJG1NPA9>LqTxL+>P2JjF<5S+D#gVB} zHxOgm;Edn;R>O>A=Mc0ZK;VZz`Yjkw`g&B3T|5>5rI%}m7qU5lnz0%{1^Xxc9Mu^| zOG`Ys$Xq;#{R0+7r&+`(AoTdAaI?XoAOOhKj?uyxPCJibWWU`>RoEDVWGPJL<9gU# zyy}W8BLF^(;a&xcE|^pYR=9Hd^>fNYC^bsed^3Omfyd_^>$CQ zczd9nJa!-|^^+W9Q5a`d+HWe`>X=a8TdY9rauv;P}U8zTW-0!eD06_ zq`dK#n+q0d%d!1jH@0nSdG)JqC_AxBu>x!U(+EiVz=Kn+Lm*elv2gY}wF&GVEXMHb zwk=x_P7H8f{uISfD-_<7o$m?yrN;Tzatubb?;+I1V*`QvX;s;Gr`b8(4L6NiE@t=E zGuSzL#kjEFYxBUPqW1SEpL{YZ+Fm#4xbweOs%r?3jlTs(>^`^V|7 zGYAwoT1A6tAaTd`9XVpLNP!pl>V}VYF=|hbprPTvoo^dVXM6{_jt%~dCr_`CrWGVR z8G6J=BX$#9ll#cSk8pJ0q4+(%>q&%02m+Dym{#@l(1|o;r908ab0ATUN;BHr<73O_ zKf%UePGmOZ&jq!(Q|PvC!}|1J`@05zhgl!lpS6B(V~%pmgl%y1&94OKiy7W(oOH)- z&P^|SIl`|+tUN^!6PEV4Jy)&&9oQ2N~xcHBS5>|E2L0zURfS3Y`{- zTn}m;8yK84JsqA!tYS%8BTOz&7X_+hT!83I(ix$)e{(cpdDz3a1wPQyk8 z1B^WBP~%Q~ zmcmKCrlIGDAgXRubzm$2C4!)62tL^;$qsLYQ<}&6$0%pW5e>Xc08k07;15J{5lz=BmrYzXme}h zrJoo#Ss6+j5-WM*XL$PcT*?mQBr{2}b?mfY>~GE3nHRgpnCHFk@OmCnSuAyAm#LRAp{gn?kGO=!HqC z?Qu~_C`ilC8X}DY0Pu{-*rO2DsF~bOEqxa3ZAIoi+q~O)=INNiCWm>n4wNvlS$1n@ zss_t4-|0VknXe&r=cSWp$|kTX_`JZ*g!PS*NRrhsUIW>uZmwnL6{H3=@oG7YX%RX0L-9&VVPy9XAgo83^m$1;T3$myU@>2)sr_R1-{2FFn@lKu1+a%IMGD<#{Hz{iJ zM6PLVFZ*66_gZfN)Npg|fai^hq|U+*n3^)l{b^(SR8ZwS;<6{?y}nz%{HrjiZt&iP zCR{tFY#fiNi8r&$TxCxBCr3P`_dqmM7|BuG`O&z!Iv_j-n0Qr?6@TLSO!UANg3yFD z2P2+8@X!2o!khp7d>}Q)OZ~-8t!1ry#aC*JN9H+_EJAR7`@7y=zWeCIWf|wTXV{gU zRp^e(u?y-dE@U`U4vG?iB!1D%g7>fw%6Q7a`tHt@c2v|rv8|oIqlSurUB+9?WY-ql z`^-X?d=$3Jj4$CB;!=1Mg#}*w=psZ*(Q7#`uhxi*I$_IebfY%m-RoY>xpmu)@-Ql~ z4?p}^dEbx!RQccsf2nNQzO9@E&cWlyF-nF}H*THCdEvA)MG?3Dr|p`r4&Fdg$1g9< zSM6Wcq6#I{ykR|%^4J%|ZJn7&?|;Xeu$sQ&t2h*YW^2oI`WxRy4~`9|o}OdRE+1u| zLVbChn@qHeq>8tFdjLLjh8q_^M(*2oN7kb!eWdSYVInK0otR;^!22}j1%EgNf8*l9 zy=3mb00z-@IF5AG-$0Z0%Xa~Y?f7iP>O0*n4@_c#2 z+a|#?=cSoePJ-i4ee&bwzkK{7W$mhE7;^0{+c&O_<$I4jYPsBYJA3L})TC#7SF)>m zimMsN%hqeRm)mc@1;OW%a_2Y3Fzk1#{Ng|PX;k^IrS0J9*yvgZOk2v`-QFum)E zr!i)Dh_QtLoC+&^@LIw;{wwWw;q7&Cj&WV3eSpvW6fb=<{@XdpMXTeJ>d~iGVzllW zcAYU&hjF@LjQc(K;G@)SG{zaV2cRZK#sO_<}G zVb5Sci}}N4FSvJcZ&?NqjGn;Wgu+P6E?k9+bunL6?kCW;aM7)n7yE^{wf`KUou!`?xZ=H5{3Y}I!rbWpN7b{t%+Q&bJ|Nmic_9J| zB?Rtr(*efe;^^{rW$1~M6$ThMD|CS~+x@7140Fb2kaO|Dbpzr3aX#@b|yO=>eya{O`DlNwk?k>lk+f&Al94!l3X)b2)xyY2mm*Mux zmBoFiS1B-X2Od}#I|n+QnTavy^C9d@dY5Dp?jemMCbW@6N-^~aV+feaVDch9AY@KD z_3Ataf)kXHn4W;0&ZqE#{4)$QI4zG+WD=;l1c!8)1QiyLUnJjz5z8Nb>pvL*ab#Ki zn-T9!T#gXaIS^7?%Op(xxoFqGpXZ+NEt68!1=+!#(a-9;S2al+I~grilZ?K1 zYMbpJ;$#rxlFm9+kBhx)8#G-acuBZ8ZsLQri?W?Xy?DOMq=84CMxBS;7M5O3F*6n|m`U4s$^W7vbP{Q8J1uKL<{>j>Y#O0$d8M^RG0eW+ z)-f^-A=*b$&}7~Tx2I*i8O7B0X&$M6@&#tPF3dBYG8(F*TEnWkYNn1m7f2?MjCxcD zAo$9m-Zpk)YJIQpXF$B_LVH^m!nra zSpw;BCU^6$v69{v>tyRo>Szq=-yHi$PJ~q^uoIiet+N2;{JmV8raoOfb}~)%Nozlo zK=2A>2T%i#@~{jE{zXu5M_6!Rn~*Me5qZ2=4C$Ef=_BIVFld)~if&uOzF@lfI8Xm* zJ?Io|+a#h@BYhstGkNHp@20$d^Upq-g@5vJ5!IB3`qY@V4*yJRf99!An^y!DshIF< zdzvuwr8KmGViMh4?)AIlNqC#ysJ@FA@#eSi^2;32PBjF@IY&81MDSZ9TjCTkFcYuM znJ53PPZ(1mByOPBICW9X3eE+q5z_!h05`^uUyC0+{sFG$U;+!OYYKePcN;brd+x2K zy6CsXe+L@r?O;Cqp&Dr5q8_{y#(RkQklm+epDoiY4#a`5+cWdsG_Z`e27PB>mYqwb zFS9VjE{g_WL?@231I*5%i^s*PmoiRj8U*aDe5cqPA!P@SN9DBSFMYF3UEs*b)-$~@ z-3z(dg9XTCTu;@tV6Z&()GpNX*_nqK)*zPoFJHm6Yuk2|t?SlCEqcw$)u>A!L*4f3 zvU~4=vIhfa`&qnv>+btAk9WhLb;E0AH`fZ627k}baLYpvqoqwJW?)Lh` zW?>(p9`$fRE~?wUDhP*lb@W}{{gl>Sa2H!7f*Z$;JJRMg$*%SkM~O}yJ;E9KfwFYf zy6~455aM>xaNb(tafL3<+>ddeHhX+!nuWO~3vUX)c@pDZGwiAlaaVUYyST?sa+coP zAmEXrEd=i=e>J6`j5hLin=uwg=h*Byi@LE_^Y&xBQ{#GP&z(U4FjiJvhLJuOhbOsG zkR4a+`p{#?IlsN9-1VJ1$_4ts&9A?;oZx#cHZZnwrPvw_5EpDQQNk=3Coc?^2OhYu zJiP1g%dTgRmc56Lp>;Y@-tnFvE=!kl9AoM}@h*oO z!i>RaQ>x}38W4n5x@i4vTIszs!63`1MyDPvef5?oHE)lxkpEvl{E70aTV7q(tzJ~N zu6;9QEaibm_Lnc;aaZ~FeGg*r^x3ix&E0?cvp-(8tk_EVz%y+$I*Q@cQxoOxyY526 zb7jtwA4H8l$5m*@bM)0^%eXd>U3C|k@}=6FP<>y4)lvj&9+_})Xg$1*4VUg?Xa<7!E5Fwv%^&l6Y`>i zr%&_axL0eS9zi=-e(q=9iz@pDvc4g#NN330U5}BBa0EqRl*aEyMylb$#n^XPx32EoyV<96U11KrtW|8sDy+4R zwS8ju2Z7<u0)`Jy&AnWWZ#|KNEIgEp?Vjqi4}ltc4Dj1WSh-HT_b_^C4)H4v9GZ2g^q)11AHO1M_9y+C++g+d#LEp1DZ_mM_rI5j8 z$7eVgiE`T!C7v=_;q0iUgT=wq1)h}HX*@?sWu$M`4P16%LA$EM)1(pu;?1~#fH97R zSn!tY#0SJjwO6`YDXtOVc|6c(d`8Xy<9Cd4P!tifzyjbtPdl4 zIoB^N+m(SL5!QOI@75sK0s?0m0;|OJ{Fx!PoNQhevi%Nmp@Nvq?B%$&07y^{b3@Q*OS^yY?vy#vgUE+Q!!zUd!MM z9(?3Gp?=T3Bt`Sx<|`y|9RO=Ul)uMAc$On@@XW9@&@dkU#jiWp}k~@!~PVm`$?8Xn%l7MYW{w*s=!%l9ea#Ha>y48m3=x#81L`il>?t zeIRiyh2e=EAN!JEQ@(bmH{bd+E&$t)`V5Q~$$B-B)6PxQxp&Lbv{M__Nz%zBFj5{% z+vdqL*@Qq=&pIM_C#kiMZyHTM;k9*dVb{17sC20Mn=Tk4jpvBlIygT#TU5hnO@W(- z!j~$LO|CV+Aij-oas1F6D}`%I;~P{6hTn2of+mE%ltq~E^s+7qA_o2BBG>q*9r9j7 zlT&^!#`i^O+YjOyRk3Qtn`1REVIxn)R!53gZysv4>{{GjECpKw(-c0PCB9rrA~uyHO}ynowpF`yN3 z=LQ!p9?^3*&bhdrGexZ!byZc=zy6JHmH+$C{;aIqd^tQ>-J$;UXTDfwKlc?ZtaAmS z8#C}{OBOFj*@gvix&oP+Nt1bAEkx?4e_kuC)sG0_VUnn#!|2XaYV7ysu ztw)Oi9%uplr`q{@4{_F-^Xp5NugX=Lp8tK~$)|Gs=PkG27T)y!`yb4L&xNJ8g?PqZ z{GMdD{Mp^lv6vpFG_=#n3mA$!Qnn)ih+4hZ7b6UDNj||j>K-%zMp?{%;>-7xv)sh8 z)SEf15B5Ngjh-xB=SIp;zvY&)ar5RF9PaOjwr7m6uu1ZQI@m_?kcKaWAAI;5d&-AD@-Nx7y^7mexP=LGOi%54 zq&&i6{_~%|r+nr9LuK3Mq1Y*yeD+Y;!@};B*K9?w;O5;*7VRs`l~-O}KJ>ePfZ=8A z0>EF6vamKEuN>BJ>(y6Z$6e{GB3P0KS5@5e_}*Y6&#FN+)$BD+H-aGMEP^#vyj5#= zw^U-Ybn+=W~I~w)$ z^DN}oP?mFSc6sB;hK=jXo_+hvQdHD6>Sul$(_X|lRNKjM?E1o8=sNaQF=ye=SRJQ7 zj4~!qBTRDhOP(*wQ4nu?ET>M3IEt`-{VM8wA&caG3_WT{&YJ-=8n|J@dKSm07~|fw zAO1b3R#v>KhLz=uhrJISGcL?lLW!Noy0cD zW+pJB5yaX@&F5W@JzhThxzCm77VefwPK=iSIQeGc4{sH@5%@ zU?ptkrQ-=~RcTHkH6P>3h1XwqV;R5#GhM5UDM^O_DM56Yc;?BSL9aZTfqCcHXU?>F zbxQ6cw|>Mt%cMHWwG?9zY>jg)Nd3I8(mHA#Tte6GPKI~`dlGdQ ziBTmM5F=v)-ZsqO0N)BA#E`;=Nbqa}dKHYwS5{sIC1$Q ziRmtO4t^&PcQ(z>d@92(hWW$8_Dz=gF}<;X1-$eFpGIu_tDo_V_53{J4=lkc1dtRu zaU}M<=)x50oSXZy+#y^kK~0q6S&l?&;_|Roh8auW3YWJg%6tlKyp9yMf^ERb)QDH` z8^Wj&A}0tJFVsNzmZ_<)NyS@gU{(_RHb29N&?ze40nnt)r)lC_A=zKro#4c!EXFWT zUFyWEEh3msTHe#Db}HjFdDQ&p%1c#hIOTL_L>CxsLE~dS^`&_6ZW;CBSzTS2xAoDlEo+dK?;5kl0kfuW;M#|D^K%wknVtXuKmbWZK~$+}vYi1m&pTl+@RO!%%5VI+x|>HWn_$`~ zF9g&w38(FMW+Q`M({(VYx0Q>3`;r`_2}UN+F4Fm|5b&?qGDdZ6xtjhLjG6WlY!a=G z>^9xS&zkoo<(rp-Wf323Jj>Cx@f;)yZoGKZ-@M}2wpANiBY~x+u5&PqQR!RqY66U= zVZcuMlmuS`YN47iKg2%T0)*9equhAcHkrep?b150ZtNhtMh^ZnRuielHMLlpOW8u0 zdnU}E249_Q(k9Qx+8ov|rXjWe)e1@jD|5#D!~EoYBtz$O&b6hozV*G9wxUQ}w=vQ? z^1%=PBdksuOG8BRkOxsP)T*1OK5Dd);nZ1d`s{nITsVHX^l)|KLez-mTeO%XZ1a~M zTV~aSWx(4%>*c10WuG0dt&%K5$CYYu3^z(>fj!5E0;s_!{ZxS@rAn=Rb_A3n8|NcJb<;IY+_;!J502xg zm+{(puE8LF;$|+L@0qvEGT!=7N9TKRy^KZH4DE0LBWN2rm%U}%6}gsd&kf@GQKiJHFemzP{|Z{PGyRd*a!B@O#vk-TXyMhV$n&d8mX|-jvO#h4{~& z#$q|U@wdM5=CX42+H&B){_@}h_m{)RPqO%5LO<~AGlk^u%vtps3wy1QuUNUf96zPH z1D5fZt!I~2K9r*d-R$flta#-$*TC;#NDy9gDT{ymEPGMduPS9IwgptH7XNrs%!+05 z6Segte)YY!LWD4cowr;&R$zhu{;~iba|-_Vj&FRu{PkD9UB(ZMan62YdG$4$%9$({ zv5voHMfvonKT~eH@w&3YACS4 z_pWv|d~=l^SM8l3%=6+35w6&IWx4)_mzB@{?cX9i!62*a1ID7lGFAFd5qImh?YTSM z#p1?Io6756|N63S)0SvrEW%R%S#Y4Xs_OXmch^3SRoNo>X?b{E`m{(5jw_vre?sYI zw6Ow;XP$nFD_f5<#u0doVU>R59J}eOGUn~G^5@n?Vb2W5ALN-GKh@cay5_t6wdli{^5A2>l4WdCP>hxF*>I)ZT#$_QxK3EY~$Y z@W2DyuyG`3-rbc?(STo%J(8aG^hkp^_9%dY1?htA{=7fS0 z=|Oh-DOZFj){*)uba2PMYEh^7!M(6wD(*#I*wbG?9_UWvxl23+@p2uZ{@Mg$%ZX_w z7YreJl}8^}%&EG+fB|7ovnwiDR#tAKsTNbuh|YCdJ6$5`<;Y3Hx1G2)EKN%Z3`g=b zi9`!Evi{|3_*=oCMG7PUI`Mg>e5g{W7%{KmQ)v`9(9Uy z{Hw6W=^gJUF(M%sq`?TKgF}Pdm8>QJ^>ERD7U^7!e;^4{%_I{ygGa%`5i|&%-Loff zR&W;R5SB2tKtF^eSVEeKn}MNmlnf?1wb$hA-n~16aF9vlJk}^rb5-40m<GO;O$LxSax|%?-@`;U!24qlK2Vn5@Ny*67+-RS(sr^S{{J> zu9Bio6SdJ=5bby8*#0v z!9$yenMU26;7)D?3ac$h;_7Ey>gu0)ck&lB@hMu(m%L5Wmcihtbv5`jFsY3vZgr_r zeu9BuA!TU7^YEwkg(gArY2WL!DOJ)|c=N-hj&-V?pKtRnv^Gie(&9R0Y=4^iwV(A# zLh2Vh_{61u1$2eq=2GMPb+J!PQ$wHkE1mBYu1(iGJ7sRZ^RTbYhtiZSUTp#+)Ogl& zE_%%=>D#FDLA}uX3*uxhV%rzy@|X*2-|Tap@D#UZ-n1yu2)(F0eq7{HL3Mz%kWE?t zwLVP~#rNVw)}2w<_DcdQHpnN52<>Fqz7Qj?md_XR;?aht-1zDAyQoji!`sEho{L{g zU(?RTX`xq$0nU%%(izK9W6=6utue(G+!8ePuQS_Jpb@{=q+R9$tq zFuVF`d(~s>?xpZZM1I!5O$ZDVv*GdMZ+rt+T&*a-`Jq24>#x0*4G}gtT*QJmcN5vC zXzEf&m*{M&7SvX{-{RE3+Ge%(sag%pTr>Bru;T(oz(`Qr5x{==XM0#ioo!{FKCQoW zTb#Dqfd)wXD{Y z^M^5x*qdGbSmS3b^|9F7kN+&VxCY^XeDL}Wn}H{3&~YDH7hFrT z-O)zi#OCMh$rI(7XLiGPtb^wsN%Ls5asR%<<-q;}MI(S7YcwEQfRuL*R?~(T4MhEH zZ#*eu>wI;ck&QxN+25)rS*5qqG}F0ua51eRZ5RF8$dIl)w|5_g51+v3<9_UPJRBP1 zx+j`(Y&zO=YVWCYjCFLKAr7>GA$%9?s^r_JrE&IgOX$X_e+-kr6^_D(0oE|$(X

l`gc{&-QCd@S7&_!`KM49S-UAXWhMPl z>bMk(l0i8&wyq}5Q}J2L{?vHehVl&4p}7P{vV^eum8eFhIYi|>2H@pxS=u>|eiN0Y z^N=`ziTFh}Q-dwnnVvj|JTWE}+ctiZ4UPw1Uws42aE5tN+{B=f)z|l4+1)b?o0IzR z1Kyhhf_RCKkA8;hl2q|?2tQs{Ahv^%T8WzROHp16qc<-;O^F&X1Z`cTrG0;Pl;L&i z+xwKv7EVp$?tful$RBxf=U=q!_8^ zM^*SRqKKu$`y#jW4BhT&4vLi#@~%V7d)U`tnzX`FIW-h9V-l)+@9L=A;V!Bak^q1i zi75iBXBEex=FDG;;ISzVQy8n<q8rqZW-koY%@kaXNgTus6MGMuI zJK*{EFTYyjb$cIS^PcQ?l@KHK@>r_Uv3k=nqStgOR&z!Tdu_pFr z0*FL#FI6CQv$Z;_`+Pn&0c<{a8$ZJ|m1Bp}~S%1e7HhpPb(!x_2cvAoOyn(p>7 zB{BS$gq-Z*Hw*LNwFVsg(7{6^nnoY-T3y!xTX}A{=+yBxaq8lrRtZh z!^`u;!W6g|?Bk6Jlz%z!fsjWASBvpc?Xi)q0A7q$IK|rY&bCw->xtiV;Ije#jm!+Z zanx|yepQ-O7H*QEpni$C|2N&>k3A{v5f#wG#@}>ZW!r~9VNvt5vH>sf2&y6o-8DV3 zCvenWb}b8(!b3}oVzkTQ;BA<8BYek|hUJ(R^W|hmp0sXcLa%5-1Z_czFl=7{WsP)4 z*cI|zVF9ChGj(NQTWHZee1}NGDb`%3NZlTyUF>^A9tWa8^*>2gOp~O$Qq$hKDe!@m zB`Hko8OU-PMX7|It&#Mh00be&^^^3_^tA>gvA7EZD8C3WGGTAzXw zpy>WFd9Jsxf$;1e+KY$Z3E?(~RRQ2GY{6$)JCg2hj)@^RKmDd_PDKP`j?UaT4`eb| zJX8@*`O6SpU;kk;5k-Ct1tX6ob;VAHDwy_Snb)Q22%cEa%K#_&in(ulsY7h<m5pPAj7;zGrL1p_*Y4?lpxiuGOREjvt;)@(%nh=j<7-r!xO{$MDI5h>FT5sF$bs39lQLL#JF&pQ=a)jpl$bsic zv-sD~Zz+lPp?I9GqFX>q{1xjIy(dF6G!lS;g>R&&?8#jYJ!>Ih@nIK4Cxi-Wmja#d z0Wp^FFHC7d$E7R>uqtA?4 ziIw3LTa|#X#5i%o=XK z`L;Ns$+k z=(zdm@TP0F-lEfc!QD1eIGzGRf%U3@>1FC3P+@RK#7;zHI{^WfxvB0nqG2w)6R4$8 zMU8%Cz{3E1=k@I*H?U*t5ox%=l?aINi26+lyLIeg-!Qx)40f`H_sUp}K;IqU#)CP5 zr-P(;{HpW>O`z}QE;SdZJya=rOeq=cIF#e+c}F18qZLQc37|s9kQ8m;K|CsiorDpz z7OL0bedmFci{9VhbIP=?CJ1N_33rgU$@F}`5?>z*K3)|7>P7r~M(V0Rx?M5~4h~0g zpgWC6P|uBzo-9kF&FLyB;jdBGPAuSP6JPdve8g~^Ugt9 zK%FT~jCnlM z0q|ok0f?$?2nI|j0UX0ER0UOVG(7}ei_U)>QzE-9F~fVlTlBijNJ4SNLaCV?)y8!| zDq=e?38u$Ev8hNNYr-xGS~6}kooSBrFun<`fKd%SHz4(1!ZC?q@CT9rj`Wr-4@@g< zT59lxn$ldd!=xJ6pdC3@trFY#i(3+Tq@E5Y>|b8NzA^4@{k|wOw6zgMvA$jLC8FGh zea2%agC_Out7p`f&15SLyOgyc!L90f6lQ%2oD&c+?K6|oAQQB-*RYb68}n1$9po5; zb|15Pc{sHgNl03Zvto4V=i_k(izgHyxOwaI)-mNaOJ~%5+dLT<#_nKncXm79``b=l zM|ZbkaH>-Bp-;0ElW5b71eiZa;L?7JpPhHDsQWrW7h0{cxusXYP z?PES4Egn=^B}S}1diKeGZ?q++kxag7KSi#?HizM05{2;v3)%Y6BneDu4A>}`jA>|o zlpM>QD31Sd$5_LrP1_^Ni4)eD3~`f0rFFeso0LOdJDARIrHpE=TIF-1O9Z#Ydq|UY zg}Cp7c3g_$&K#fs{XGRE?Ct%zMHbhW0&!p)q=N~M#6SKBG|A*xUG-C}^nrN&LOM6{ zEeNOG66VD|G@3WWz1h@n2*MuyAk02PRR`B0ufOH_!{DC2@dw3vV`qd z)4%ETrg;>7%JxhbrGdD`pvT9wz*+W*fI}T%W2&US(&`4bK8)fKFBY!Avj6pIuN&yE zArfr4U-s{{;A!LCu*jLWvq_ti^Kzalb3S8BJci4!42JKr0TJG!8(^Cp#X#{PVZb=i zUb(c*oMD0iy8cri5a(6-61)4>p6m$3DR&#hmPbhnvu!{ZtpgZ@&vwHEY2NUP2&f*3 zz3xOUGXG8Y3T)U=af&(i6nXdO``s~MKYc3!N{kyp*@c`>xwq8cmlZ8BQ%wik-bMxN zR)f_g8B5wIuwbdF;5}j8z4tC4Pm)~fE@kTH^F{$9T4Je^@3q#0vM1N39|8NagK18T zSgxYcl=hZ%efX<4lt)hL$#}6V_sThPuof-D#~$r zW%Wy>XK=e>dhY31ug+&eOOyLU++}aTHnAY?@FlwXyN1G}m0=%ruZaovqvk`My<~=T z5Qmuk=W*cv|L|q~*9wVtwmmTNrL(Hhp-_zfY5xrGe z5!84Z-zU0?L3`|Q?Y%0WFEvi)B|1Tt3zJLtnY4M-dZbLL@f449rr=-@7H?HrOpjt* zw3YJdgji=d?Og|8Iyb|2C@bAHo-pgh3`nS-A$TQ0(#Zds$;qgT9Ref$P6LNlhx z$~AqB!IGZE!8(QCgI6MG!9 zkJ%>PEdCty7-JsJc5_F=m9JAx05PjmxEs8}Dk@&L*+9G54mwnG`-0bvBVn~WeraXY zPYUM8ZZHR&v*+Q7pH0Jxgr<0$b7p#X|$e0H8J{9%n`?#OayazTmzIIVj_^1ht;{UQla)f%60 zWmXMiw#Fi=QWjwHbaDD#H)Jk$ve+g(w|k2reVS|Fdj)gBybbQF5|pdXHJCO$9s!#(D`{_8tR5jLD?!5qwS*QANevEcNE z)poUKKBTE@1KmdERbik<+djE1e+@XkaK)G+j_0OLr5?Q(z%EezR6d@on(uMzxiyY> zM?OfV_={5GZD+mg+)2BY@Y8+B^%-mG`-k`V0}!iI&?9)E8kBjRmk}r?0m$GUc7)b#F~~`ud29ed^4TM&>stLWlN@SDhHGc&bwj zWmgzAM80vA(JJP8cR7n@^rhXWwT96uNU@=aclLlP$8zA*P#49!FkB_%5rCCE zT)ogN-G@25MU9}Gh0hZF%da1Q98OfnKM&1=B$+k7M7Axs$$B{kmVA`D1{;>GyE7cQ zsLJEl^8ji%=YG%xgc~b9y>=hk7l9xP1a^|zIkFxoa}X6t&cFrwWqiE;H{Has!xZcD z)CjLL%)9qfoUU;1d&HnhlxE45Y8rif9u!ZJ^_^-}Z}&x~k5u=giTChVLcVegiq8*g z*c8THeAoP`k+xqOUI3`n%aD^shOHA{1>hg`N~!Oa*hhQ`fj?3zgu>fTL1sOyIAKtO z&)KKVht2|C^Iph>UN_E~8mR>PY%y)Zf&N~-*WsRX1V0h#TUpv^R_q{UD}M4-hY?~J zjx9e@xD%PaT(Blwt$xm8{Kd6m--s{SkMs2i;;A+T4fWCQyPs(i!dvUt8Aq;-E z$NZ{GcL%{$vFg`dOrdVW{-^nd2Y7B{yB2id*bgKTsP%M+}M zLa5=O{Z1t#t&*80@ZRS;imB@);>E%*04<0i>Tr)cl|HFF3omr5?^fq`&h?<+D3=h+ z$@m7Y6txJdGBZAfEW~6fD)qyd$OkKQY+w&JYnOzr?E`m-%Ua|MUV?SV^G_6&kI~#y zsUMXKx|GCzaE&tu6E#SBTn=UxP*ylT3yJ>@*crG*SHkxJ0F zxLmjy>P>t|C|X{PI_E|EXe->1`-)fi2Z!b)z72KAfY%|Re7of|I(%4cs&yfiWz!}# z8asFs#XiTJu1Xf9oPR6PV0wO^v+r*@s*M*^h-o;KpS3?;)h^5iD!M{_TV8g>Am4Eq zft9B&={b!#PW8cvcSt-E_VG6-pl@?mq#$!_6^p3w57dZ|Aebc`>5Fj&zV~kGPuRw;+6G&`;5qfgBpFsHTerm@%t2on+7FpM5OJ!p*juO^56uF7g!M|p96QGqa^@36E>Zx1w&CCnxuw`d_1oy0{9y5N8lLnT3Vg3y0iocm6 z+!XaDD4Tc0ZF~_I-kSss^S$XTRX= z`FTDD30655^LPS`aKf2+XZvI?U_L$i>cVW5-EX?mlwIvs$V|+SeW_5UqNR!%pH}E~ zZS@Ihn|FMN#TYTnh#eMeE3dfjY3@YH6aaL!bPEN!xpW|;X+`@0nQ5-Ns5Tz6(eJyh z?$d}m&L#J)dY+mJ7RF;xXGF~JkTTb3Z$t7J3ad&~;a%=DghHV81!l*gD6Cz)zU_+2 zklV)fE^H7)5m#;4Z}fg*vbpBfUJXt-0`-sAEU^iX2rc#4dtK=qm zr{ggNuPk6gRkZ^PGc7qbBD~K2E`l3PcP0zMU%9>u*6V)|u8PEGV+t-o@-hG}_y(Lb zN$wGtWmD`v)tG4>HAZs%CsYCS_RcUophOU9N!MMdkL>(0+frhT(G930pK`w-ISXg4*?CxBC!Nxx|t5DMSp}Tp@`p6%Rd{^aaPb zqb-~m?rN$8Z^G=j&_xk1lPuZ-N<LtJ60j6Zo6AelR=Z z-*m!5w2x8%ZCd}hj%m=LCeZ@^5jI4EBrlR)eOg*oUOiV%4X8Oj7Fy_CF6hFFhwcW# zpCWyG-kTIv=`iwBQ!BuBk&Q*|f&`C=1?5#?sDagsXa7fz@@6{8sIr9zg3EBc*=^HU zhuQt>`o<-}ZCAP~`m0rb^xLBp%5xJ7aKN*&>Nx=%3YnuX7z7DPX1Sh{y-d3eS*e%QFE%Iv zqW(wazv-m?h|u|JWPxnm?1wf!WGgd1{xu!-vMV*XhDF%es0!KC#c#-p>Mf!*H@r;9 zYBcPTUsqkdtV(94oPIFcK`wHWg;8yKN~obUHvLO?Lfd%CuJUW?iJo@jpxnCG@$D(B zJP!_(PVN(AN0lB_&EvFV5=G-|#|GcdxX?6leI_ftYe9<|s$2!5+)}6?crk5J1}bAD z%v#qBXB_0CJB(+<2Ia{vOX8dAi_es19EDi)UL7ZyWSDJ6cYMYyO^8=jI-T7s`}HVu z!Xh;zmW$L23GbPpDMW6(g6*sUDPAw^ApF|S&X`iMx?rkfXgJlgabi7%U8{!ry5}mdD|J&D*u3v+&a*|?v{LK# zl_xP`juI;XnDin*wD4y~MjX}EiS zpBm*IJ?pw;^BFW?=LeBF`@Leeil`g-R%N2f?PEpirxi9A;>d8KItf$^Y)U-y(@TUf ziZFn4xH~`sY9^dvi|pjcaM#QNyWQ2G$p6|H$p5im%m2*{F-JpI%mA}c%+X-5qF8f+ z!si&M@6vd05W$3I`_O#{?aLQo;Lg`u5k3qfrVwB&g7(wDsx|SnwOak~H+hlua}#s8 zu5tN&KT^b-YjYX#xCl_2)uQJ=q|w6u7Gjxqkcu|{38F=oT>-jhcs4!km-R((7aCK9 zI3LG5!Tqcbp@K2_+qKY$EhsTjXPrYj+Cm_yBgppiM630(dlQE5kYd!yE7IN(66nb}Bor$tJxeh?aO;IelTkPmsIPrr*+vG^xL8UOF!f&TCN3r1!F ztZ5*T0Wa_kceH+=wT$z9#_fbh%bKeluSkPkm;$IFIGllUp7-2Mmn)p6)ty>@3f}1p z=d3y4g(QuWk66iKiozSa=)1D4&s^yEF(OlB!|$G(vwA@SqH}nTXsBd= zh=CeW(jf6ODfG*4x+i+1G@0;wr7`E9M_v&*cYDY8iTuyAaJ`Eee@d#o{}y}mpXQ?s z^&ml(s|kLB!ex&|9hEwlT2p45rqrw2yZEGUsKkK~y+q>~+Ja^!KkjMIG?B^fpsz3AZ b;D75b`1h3lNz^j@Z|~p#p4UIkybk|Al$WIo literal 0 HcmV?d00001 diff --git a/bsp/nxp/mcx/mcxa/frdm-mcxa346/applications/arduino_pinout/pins_arduino.c b/bsp/nxp/mcx/mcxa/frdm-mcxa346/applications/arduino_pinout/pins_arduino.c new file mode 100644 index 00000000000..b040b77cdbc --- /dev/null +++ b/bsp/nxp/mcx/mcxa/frdm-mcxa346/applications/arduino_pinout/pins_arduino.c @@ -0,0 +1,49 @@ +/* + * Copyright (c) 2006-2023, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2025-12-08 westcity-yolo first version + * + */ + +#include +#include +#include +#include "pins_arduino.h" + +/* + * {Arduino Pin, RT-Thread Pin [, Device Name, Channel]} + * [] means optional + * Digital pins must NOT give the device name and channel. + * Analog pins MUST give the device name and channel(ADC, PWM or DAC). + * Arduino Pin must keep in sequence. + */ +const pin_map_t pin_map_table[]= +{ + {D0, GET_PINS(2,3), "uart2"}, /* Serial2-RX */ + {D1, GET_PINS(2,2), "uart2"}, /* Serial2-TX */ + {D2, GET_PINS(3,31)}, + {D3, GET_PINS(3,14), "pwm1", 1}, /* PWM */ + {D4, GET_PINS(4,7)}, + {D5, GET_PINS(3,1), "pwm0", 0}, /* PWM */ + {D6, GET_PINS(3,17), "pwm1", 0}, /* PWM */ + {D7, GET_PINS(3,22)}, + {D8, GET_PINS(4,3)}, + {D9, GET_PINS(3,13), "pwm1", 2}, /* PWM */ + {D10, GET_PINS(3,11),"spi1"}, /* SPI-SS */ + {D11, GET_PINS(3,8), "spi1"}, /* SPI-SDO */ + {D12, GET_PINS(3,9), "spi1"}, /* SPI-SDI */ + {D13, GET_PINS(3,10),"spi1"}, /* SPI-SCK */ + {D18, GET_PINS(1,8),"i2c2"}, /* I2C-SDA (Wire) */ + {D19, GET_PINS(1,9),"i2c2"}, /* I2C-SCL (Wire) */ + {A0, GET_PINS(1,14),"adc1", 12}, /* ADC */ + {A1, GET_PINS(2,5), "adc1", 1}, /* ADC */ + {A2, GET_PINS(2,7),"adc0", 7}, /* ADC */ + {A3, GET_PINS(3,30),"adc1", 21}, + {A4, GET_PINS(1,0),"i2c1"}, /* I2C-SDA (Wire) */ + {A5, GET_PINS(1,1),"i2c1"}, /* I2C-SCL (Wire) */ + +}; \ No newline at end of file diff --git a/bsp/nxp/mcx/mcxa/frdm-mcxa346/applications/arduino_pinout/pins_arduino.h b/bsp/nxp/mcx/mcxa/frdm-mcxa346/applications/arduino_pinout/pins_arduino.h new file mode 100644 index 00000000000..afb824ddf97 --- /dev/null +++ b/bsp/nxp/mcx/mcxa/frdm-mcxa346/applications/arduino_pinout/pins_arduino.h @@ -0,0 +1,58 @@ +/* + * Copyright (c) 2006-2023, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2025-12-08 westcity-yolo first version + * + */ + +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + + + +/* pins alias. Must keep in sequence */ +#define D0 (0) +#define D1 (1) +#define D2 (2) +#define D3 (3) +#define D4 (4) +#define D5 (5) +#define D6 (6) +#define D7 (7) +#define D8 (8) +#define D9 (9) +#define D10 (10) +#define D11 (11) +#define D12 (12) +#define D13 (13) +#define D18 (14) +#define D19 (15) + +#define A0 (16) +#define A1 (17) +#define A2 (18) +#define A3 (19) +#define A4 (20) +#define A5 (21) +#define A6 (22) +#define A7 (23) + +#define RTDUINO_PIN_MAX_LIMIT A7 /* pin number max limit check */ + +#define F_CPU 180000000L /* CPU:180MHz */ + +/* i2c2 : P(,1_8-SDA P(,1_9-SCL */ +#define RTDUINO_DEFAULT_IIC_BUS_NAME "i2c2" + +/* Serial2 : P(,2_2-TX P(,2_3-RX */ +#define RTDUINO_SERIAL2_DEVICE_NAME "uart2" + +/* spi1 : P(,3_8-SDO P(,3_9-SDI P(,3_10-SCK P(,3_11-SS */ + +#define RTDUINO_DEFAULT_SPI_BUS_NAME "spi1" + +#endif /* Pins_Arduino_h */ \ No newline at end of file diff --git a/bsp/nxp/mcx/mcxa/frdm-mcxa346/board/Kconfig b/bsp/nxp/mcx/mcxa/frdm-mcxa346/board/Kconfig index b4fbf9377c0..5e2569c132a 100644 --- a/bsp/nxp/mcx/mcxa/frdm-mcxa346/board/Kconfig +++ b/bsp/nxp/mcx/mcxa/frdm-mcxa346/board/Kconfig @@ -104,25 +104,55 @@ menu "On-chip Peripheral Drivers" default n endif - menuconfig BSP_USING_PWM - config BSP_USING_PWM - bool "Enable PWM" - select RT_USING_PWM - default n - - if BSP_USING_PWM - config BSP_USING_PWM0 - bool "Enable eFlex PWM0" - default n - config BSP_USING_PWM1 - bool "Enable eFlex PWM1" - default n - config BSP_USING_PWM2 - bool "Enable eFlex PWM2" - default n - endif + menuconfig BSP_USING_PWM + config BSP_USING_PWM + bool "Enable PWM" + select RT_USING_PWM + default n + + if BSP_USING_PWM + config BSP_USING_PWM0 + bool "Enable eFlex PWM0" + default n + config BSP_USING_PWM1 + bool "Enable eFlex PWM1" + default n + config BSP_USING_PWM2 + bool "Enable eFlex PWM2" + default n + endif + + menuconfig BSP_USING_CAN + config BSP_USING_CAN + bool "Enable CAN" + select RT_USING_CAN + default n + if BSP_USING_CAN + config BSP_USING_CAN0 + bool "Enable CAN0" + default n + + config BSP_USING_CAN1 + bool "Enable CAN1" + default n + endif + endmenu +menu "Onboard Peripheral Drivers" + config BSP_USING_ARDUINO + bool "Compatible with Arduino Ecosystem (RTduino)" + select PKG_USING_RTDUINO + select BSP_USING_UART2 + select BSP_USING_GPIO + select BSP_USING_ADC0 + select BSP_USING_PWM0 + select BSP_USING_PWM1 + select BSP_USING_I2C1 + select BSP_USING_I2C2 + select BSP_USING_SPI1 + endmenu + menu "Board extended module Drivers" menuconfig BSP_USING_RW007 diff --git a/bsp/nxp/mcx/mcxa/frdm-mcxa346/board/MCUX_Config/board/pin_mux.c b/bsp/nxp/mcx/mcxa/frdm-mcxa346/board/MCUX_Config/board/pin_mux.c index 03b612b08b6..57004a9c156 100644 --- a/bsp/nxp/mcx/mcxa/frdm-mcxa346/board/MCUX_Config/board/pin_mux.c +++ b/bsp/nxp/mcx/mcxa/frdm-mcxa346/board/MCUX_Config/board/pin_mux.c @@ -48,6 +48,7 @@ void BOARD_InitPins(void) static const reset_ip_name_t i2c_resets[] = LPI2C_RSTS; static const reset_ip_name_t spi_resets[] = LPSPI_RSTS; static const reset_ip_name_t dma_resets[] = DMA_RSTS_N; + static const reset_ip_name_t can_resets[] = FLEXCAN_RSTS_N; // Release resets release_reset_array(port_resets, ARRAY_SIZE(port_resets)); @@ -56,7 +57,7 @@ void BOARD_InitPins(void) release_reset_array(i2c_resets, ARRAY_SIZE(i2c_resets)); release_reset_array(spi_resets, ARRAY_SIZE(spi_resets)); release_reset_array(dma_resets, ARRAY_SIZE(dma_resets)); - + release_reset_array(can_resets, ARRAY_SIZE(can_resets)); const port_pin_config_t port2_2_pin35_config = {/* Internal pull-up resistor is enabled */ .pullSelect = kPORT_PullUp, @@ -285,107 +286,6 @@ void BOARD_InitPins(void) /* PORT3_28 (pin 73) is configured as LPI2C3_SDA */ PORT_SetPinConfig(PORT3, 28U, &port3_28_pin73_config); - - const port_pin_config_t port1_0_pin135_config = {/* Internal pull-up/down resistor is disabled */ - .pullSelect = kPORT_PullDisable, - /* Low internal pull resistor value is selected. */ - .pullValueSelect = kPORT_LowPullResistor, - /* Fast slew rate is configured */ - .slewRate = kPORT_FastSlewRate, - /* Passive input filter is disabled */ - .passiveFilterEnable = kPORT_PassiveFilterDisable, - /* Open drain output is disabled */ - .openDrainEnable = kPORT_OpenDrainDisable, - /* Low drive strength is configured */ - .driveStrength = kPORT_LowDriveStrength, - /* Normal drive strength is configured */ - .driveStrength1 = kPORT_NormalDriveStrength, - /* Pin is configured as LPSPI0_SDO */ - .mux = kPORT_MuxAlt2, - /* Digital input enabled */ - .inputBuffer = kPORT_InputBufferEnable, - /* Digital input is not inverted */ - .invertInput = kPORT_InputNormal, - /* Pin Control Register fields [15:0] are not locked */ - .lockRegister = kPORT_UnlockRegister}; - /* PORT1_0 (pin 135) is configured as LPSPI0_SDO */ - PORT_SetPinConfig(PORT1, 0U, &port1_0_pin135_config); - - const port_pin_config_t port1_1_pin136_config = {/* Internal pull-up/down resistor is disabled */ - .pullSelect = kPORT_PullDisable, - /* Low internal pull resistor value is selected. */ - .pullValueSelect = kPORT_LowPullResistor, - /* Fast slew rate is configured */ - .slewRate = kPORT_FastSlewRate, - /* Passive input filter is disabled */ - .passiveFilterEnable = kPORT_PassiveFilterDisable, - /* Open drain output is disabled */ - .openDrainEnable = kPORT_OpenDrainDisable, - /* Low drive strength is configured */ - .driveStrength = kPORT_LowDriveStrength, - /* Normal drive strength is configured */ - .driveStrength1 = kPORT_NormalDriveStrength, - /* Pin is configured as LPSPI0_SCK */ - .mux = kPORT_MuxAlt2, - /* Digital input enabled */ - .inputBuffer = kPORT_InputBufferEnable, - /* Digital input is not inverted */ - .invertInput = kPORT_InputNormal, - /* Pin Control Register fields [15:0] are not locked */ - .lockRegister = kPORT_UnlockRegister}; - /* PORT1_1 (pin 136) is configured as LPSPI0_SCK */ - PORT_SetPinConfig(PORT1, 1U, &port1_1_pin136_config); - - const port_pin_config_t port1_2_pin137_config = {/* Internal pull-up/down resistor is disabled */ - .pullSelect = kPORT_PullDisable, - /* Low internal pull resistor value is selected. */ - .pullValueSelect = kPORT_LowPullResistor, - /* Fast slew rate is configured */ - .slewRate = kPORT_FastSlewRate, - /* Passive input filter is disabled */ - .passiveFilterEnable = kPORT_PassiveFilterDisable, - /* Open drain output is disabled */ - .openDrainEnable = kPORT_OpenDrainDisable, - /* Low drive strength is configured */ - .driveStrength = kPORT_LowDriveStrength, - /* Normal drive strength is configured */ - .driveStrength1 = kPORT_NormalDriveStrength, - /* Pin is configured as LPSPI0_SDI */ - .mux = kPORT_MuxAlt2, - /* Digital input enabled */ - .inputBuffer = kPORT_InputBufferEnable, - /* Digital input is not inverted */ - .invertInput = kPORT_InputNormal, - /* Pin Control Register fields [15:0] are not locked */ - .lockRegister = kPORT_UnlockRegister}; - /* PORT1_2 (pin 137) is configured as LPSPI0_SDI */ - PORT_SetPinConfig(PORT1, 2U, &port1_2_pin137_config); - - const port_pin_config_t port1_3_pin138_config = {/* Internal pull-up/down resistor is disabled */ - .pullSelect = kPORT_PullDisable, - /* Low internal pull resistor value is selected. */ - .pullValueSelect = kPORT_LowPullResistor, - /* Fast slew rate is configured */ - .slewRate = kPORT_FastSlewRate, - /* Passive input filter is disabled */ - .passiveFilterEnable = kPORT_PassiveFilterDisable, - /* Open drain output is disabled */ - .openDrainEnable = kPORT_OpenDrainDisable, - /* Low drive strength is configured */ - .driveStrength = kPORT_LowDriveStrength, - /* Normal drive strength is configured */ - .driveStrength1 = kPORT_NormalDriveStrength, - /* Pin is configured as LPSPI0_PCS0 */ - .mux = kPORT_MuxAlt2, - /* Digital input enabled */ - .inputBuffer = kPORT_InputBufferEnable, - /* Digital input is not inverted */ - .invertInput = kPORT_InputNormal, - /* Pin Control Register fields [15:0] are not locked */ - .lockRegister = kPORT_UnlockRegister}; - /* PORT1_3 (pin 138) is configured as LPSPI0_PCS0 */ - PORT_SetPinConfig(PORT1, 3U, &port1_3_pin138_config); - const port_pin_config_t port3_10_pin96_config = {/* Internal pull-up/down resistor is disabled */ .pullSelect = kPORT_PullDisable, /* Low internal pull resistor value is selected. */ @@ -485,4 +385,54 @@ void BOARD_InitPins(void) .lockRegister = kPORT_UnlockRegister}; /* PORT3_9 (pin 97) is configured as LPSPI1_SDI */ PORT_SetPinConfig(PORT3, 9U, &port3_9_pin97_config); + + const port_pin_config_t port1_11_pin4_config = {/* Internal pull-up/down resistor is disabled */ + .pullSelect = kPORT_PullDisable, + /* Low internal pull resistor value is selected. */ + .pullValueSelect = kPORT_LowPullResistor, + /* Fast slew rate is configured */ + .slewRate = kPORT_FastSlewRate, + /* Passive input filter is disabled */ + .passiveFilterEnable = kPORT_PassiveFilterDisable, + /* Open drain output is disabled */ + .openDrainEnable = kPORT_OpenDrainDisable, + /* Low drive strength is configured */ + .driveStrength = kPORT_LowDriveStrength, + /* Normal drive strength is configured */ + .driveStrength1 = kPORT_NormalDriveStrength, + /* Pin is configured as CAN0_RXD */ + .mux = kPORT_MuxAlt11, + /* Digital input enabled */ + .inputBuffer = kPORT_InputBufferEnable, + /* Digital input is not inverted */ + .invertInput = kPORT_InputNormal, + /* Pin Control Register fields [15:0] are not locked */ + .lockRegister = kPORT_UnlockRegister}; + /* PORT1_11 (pin 4) is configured as CAN0_RXD */ + PORT_SetPinConfig(PORT1, 11U, &port1_11_pin4_config); + + const port_pin_config_t port1_2_pin137_config = {/* Internal pull-up/down resistor is disabled */ + .pullSelect = kPORT_PullDisable, + /* Low internal pull resistor value is selected. */ + .pullValueSelect = kPORT_LowPullResistor, + /* Fast slew rate is configured */ + .slewRate = kPORT_FastSlewRate, + /* Passive input filter is disabled */ + .passiveFilterEnable = kPORT_PassiveFilterDisable, + /* Open drain output is disabled */ + .openDrainEnable = kPORT_OpenDrainDisable, + /* Low drive strength is configured */ + .driveStrength = kPORT_LowDriveStrength, + /* Normal drive strength is configured */ + .driveStrength1 = kPORT_NormalDriveStrength, + /* Pin is configured as CAN0_TXD */ + .mux = kPORT_MuxAlt11, + /* Digital input enabled */ + .inputBuffer = kPORT_InputBufferEnable, + /* Digital input is not inverted */ + .invertInput = kPORT_InputNormal, + /* Pin Control Register fields [15:0] are not locked */ + .lockRegister = kPORT_UnlockRegister}; + /* PORT1_2 (pin 137) is configured as CAN0_TXD */ + PORT_SetPinConfig(PORT1, 2U, &port1_2_pin137_config); } diff --git a/bsp/qemu-virt64-aarch64/applications/console.c b/bsp/qemu-virt64-aarch64/applications/console.c index b69b9b3b978..3f8be481891 100644 --- a/bsp/qemu-virt64-aarch64/applications/console.c +++ b/bsp/qemu-virt64-aarch64/applications/console.c @@ -31,30 +31,3 @@ static int console_init() return status; } INIT_ENV_EXPORT(console_init); - -static int console(int argc, char **argv) -{ - rt_err_t result = RT_EOK; - - if (argc > 1) - { - if (!rt_strcmp(argv[1], "set")) - { - rt_kprintf("console change to %s\n", argv[2]); - rt_console_set_device(argv[2]); - } - else - { - rt_kprintf("Unknown command. Please enter 'console' for help\n"); - result = -RT_ERROR; - } - } - else - { - rt_kprintf("Usage: \n"); - rt_kprintf("console set - change console by name\n"); - result = -RT_ERROR; - } - return result; -} -MSH_CMD_EXPORT(console, set console name); diff --git a/bsp/qemu-virt64-riscv/SConstruct b/bsp/qemu-virt64-riscv/SConstruct index 3387d0e1490..ae0e3375e11 100644 --- a/bsp/qemu-virt64-riscv/SConstruct +++ b/bsp/qemu-virt64-riscv/SConstruct @@ -38,5 +38,25 @@ if GetDepend('__STACKSIZE__'): stack_size = GetDepend('__STACKSIZE__') stack_lds.write('__STACKSIZE__ = %d;\n' % stack_size) stack_lds.close() +# Obtain the number of harts from rtconfig.h and write +# it into link_cpus.lds for the linker script +try: + with open('rtconfig.h', 'r') as f: + rtconfig_content = f.readlines() +except FileNotFoundError: + cpus_nr = 1 +else: + cpus_nr = 1 # default value + for line in rtconfig_content: + line = line.strip() + if line.startswith('#define') and 'RT_CPUS_NR' in line: + parts = line.split() + if len(parts) >= 3 and parts[2].isdigit(): + cpus_nr = int(parts[2]) + break + +with open('link_cpus.lds', 'w') as cpus_lds: + cpus_lds.write(f'RT_CPUS_NR = {cpus_nr};\n') + # make a building DoBuilding(TARGET, objs) diff --git a/bsp/qemu-virt64-riscv/driver/board.c b/bsp/qemu-virt64-riscv/driver/board.c index c5116aad0c5..092244278ed 100644 --- a/bsp/qemu-virt64-riscv/driver/board.c +++ b/bsp/qemu-virt64-riscv/driver/board.c @@ -24,6 +24,10 @@ #include "plic.h" #include "stack.h" +#ifdef RT_USING_SMP +#include "interrupt.h" +#endif /* RT_USING_SMP */ + #ifdef RT_USING_SMART #include "riscv_mmu.h" #include "mmu.h" @@ -89,6 +93,11 @@ void rt_hw_board_init(void) rt_hw_tick_init(); +#ifdef RT_USING_SMP + /* ipi init */ + rt_hw_ipi_init(); +#endif /* RT_USING_SMP */ + #ifdef RT_USING_COMPONENTS_INIT rt_components_board_init(); #endif diff --git a/bsp/qemu-virt64-riscv/driver/board.h b/bsp/qemu-virt64-riscv/driver/board.h index 433b1d8f53b..9c74ae6b267 100644 --- a/bsp/qemu-virt64-riscv/driver/board.h +++ b/bsp/qemu-virt64-riscv/driver/board.h @@ -25,7 +25,7 @@ extern unsigned int __bss_end; #define RT_HW_HEAP_BEGIN ((void *)&__bss_end) #define RT_HW_HEAP_END ((void *)(RT_HW_HEAP_BEGIN + 64 * 1024 * 1024)) #define RT_HW_PAGE_START RT_HW_HEAP_END -#define RT_HW_PAGE_END ((void *)(KERNEL_VADDR_START + (256 * 1024 * 1024 - VIRT64_SBI_MEMSZ))) +#define RT_HW_PAGE_END ((void *)(KERNEL_VADDR_START + (128 * 1024 * 1024 - VIRT64_SBI_MEMSZ))) void rt_hw_board_init(void); void rt_init_user_mem(struct rt_thread *thread, const char *name, diff --git a/bsp/qemu-virt64-riscv/link.lds b/bsp/qemu-virt64-riscv/link.lds index a76fed4fa30..da750aca9bb 100644 --- a/bsp/qemu-virt64-riscv/link.lds +++ b/bsp/qemu-virt64-riscv/link.lds @@ -9,6 +9,7 @@ */ INCLUDE "link_stacksize.lds" +INCLUDE "link_cpus.lds" OUTPUT_ARCH( "riscv" ) @@ -121,12 +122,9 @@ SECTIONS { . = ALIGN(64); __stack_start__ = .; - - . += __STACKSIZE__; - __stack_cpu0 = .; - - . += __STACKSIZE__; - __stack_cpu1 = .; + /* Dynamically allocate stack areas according to RT_CPUS_NR */ + . += (__STACKSIZE__ * RT_CPUS_NR); + __stack_end__ = .; } > SRAM .sbss : @@ -138,6 +136,24 @@ SECTIONS *(.scommon) } > SRAM + .percpu (NOLOAD) : + { + /* 2MB Align for MMU early map */ + . = ALIGN(0x200000); + PROVIDE(__percpu_start = .); + + *(.percpu) + + /* 2MB Align for MMU early map */ + . = ALIGN(0x200000); + + PROVIDE(__percpu_end = .); + + /* Clone the area */ + . = __percpu_end + (__percpu_end - __percpu_start) * (RT_CPUS_NR - 1); + PROVIDE(__percpu_real_end = .); + } > SRAM + .bss : { *(.bss) diff --git a/bsp/qemu-virt64-riscv/link_cpus.lds b/bsp/qemu-virt64-riscv/link_cpus.lds new file mode 100644 index 00000000000..2659b2befb4 --- /dev/null +++ b/bsp/qemu-virt64-riscv/link_cpus.lds @@ -0,0 +1 @@ +RT_CPUS_NR = 8; diff --git a/bsp/qemu-virt64-riscv/link_smart.lds b/bsp/qemu-virt64-riscv/link_smart.lds index ddf596630ed..29d33fdbb1c 100644 --- a/bsp/qemu-virt64-riscv/link_smart.lds +++ b/bsp/qemu-virt64-riscv/link_smart.lds @@ -9,6 +9,7 @@ */ INCLUDE "link_stacksize.lds" +INCLUDE "link_cpus.lds" OUTPUT_ARCH( "riscv" ) @@ -122,12 +123,9 @@ SECTIONS { . = ALIGN(64); __stack_start__ = .; - - . += __STACKSIZE__; - __stack_cpu0 = .; - - . += __STACKSIZE__; - __stack_cpu1 = .; + /* Dynamically allocate stack areas according to RT_CPUS_NR */ + . += (__STACKSIZE__ * RT_CPUS_NR); + __stack_end__ = .; } > SRAM .sbss : @@ -139,6 +137,24 @@ SECTIONS *(.scommon) } > SRAM + .percpu (NOLOAD) : + { + /* 2MB Align for MMU early map */ + . = ALIGN(0x200000); + PROVIDE(__percpu_start = .); + + *(.percpu) + + /* 2MB Align for MMU early map */ + . = ALIGN(0x200000); + + PROVIDE(__percpu_end = .); + + /* Clone the area */ + . = __percpu_end + (__percpu_end - __percpu_start) * (RT_CPUS_NR - 1); + PROVIDE(__percpu_real_end = .); + } > SRAM + .bss : { *(.bss) diff --git a/bsp/qemu-virt64-riscv/qemu-dbg.sh b/bsp/qemu-virt64-riscv/qemu-dbg.sh index a7958ef8e88..69f62e7f6fb 100755 --- a/bsp/qemu-virt64-riscv/qemu-dbg.sh +++ b/bsp/qemu-virt64-riscv/qemu-dbg.sh @@ -1,4 +1,16 @@ -qemu-system-riscv64 -nographic -machine virt -m 256M -kernel rtthread.bin -s -S \ +QEMU_CMD="qemu-system-riscv64 -nographic -machine virt -m 256M -kernel rtthread.bin -s -S" + +if grep -q "#define RT_USING_SMP" ./rtconfig.h 2>/dev/null; then + hart_num=$(grep "RT_CPUS_NR = [0-9]*;" ./link_cpus.lds | awk -F'[=;]' '{gsub(/ /, "", $2); print $2}') + if [ -z "$hart_num" ]; then + hart_num=1 + fi + QEMU_CMD="$QEMU_CMD -smp $hart_num" +fi + +QEMU_CMD="$QEMU_CMD \ -drive if=none,file=sd.bin,format=raw,id=blk0 -device virtio-blk-device,drive=blk0,bus=virtio-mmio-bus.0 \ -netdev user,id=tap0 -device virtio-net-device,netdev=tap0,bus=virtio-mmio-bus.1 \ --device virtio-serial-device -chardev socket,host=127.0.0.1,port=4321,server=on,wait=off,telnet=on,id=console0 -device virtserialport,chardev=console0 +-device virtio-serial-device -chardev socket,host=127.0.0.1,port=4321,server=on,wait=off,telnet=on,id=console0 -device virtserialport,chardev=console0" + +eval $QEMU_CMD \ No newline at end of file diff --git a/bsp/qemu-virt64-riscv/run.sh b/bsp/qemu-virt64-riscv/run.sh index dd53c95f612..c332915098c 100755 --- a/bsp/qemu-virt64-riscv/run.sh +++ b/bsp/qemu-virt64-riscv/run.sh @@ -24,7 +24,20 @@ if [ ! -f $path_image ]; then exit fi -qemu-system-riscv64 -nographic -machine virt -m 256M -kernel rtthread.bin \ +QEMU_CMD="qemu-system-riscv64 -nographic -machine virt -m 256M -kernel rtthread.bin" + +if grep -q "#define RT_USING_SMP" ./rtconfig.h 2>/dev/null; then + hart_num=$(grep "RT_CPUS_NR = [0-9]*;" ./link_cpus.lds 2>/dev/null | awk -F'[=;]' '{gsub(/ /, "", $2); print $2}') + if [ -z "$hart_num" ] || [ "$hart_num" -lt 1 ]; then + echo "Warning: Invalid or missing RT_CPUS_NR, defaulting to 1" + hart_num=1 + fi + QEMU_CMD="$QEMU_CMD -smp $hart_num" +fi + +QEMU_CMD="$QEMU_CMD \ -drive if=none,file=$path_image,format=raw,id=blk0 -device virtio-blk-device,drive=blk0,bus=virtio-mmio-bus.0 \ -netdev user,id=tap0 -device virtio-net-device,netdev=tap0,bus=virtio-mmio-bus.1 \ --device virtio-serial-device -chardev socket,host=127.0.0.1,port=4321,server=on,wait=off,telnet=on,id=console0 -device virtserialport,chardev=console0 +-device virtio-serial-device -chardev socket,host=127.0.0.1,port=4321,server=on,wait=off,telnet=on,id=console0 -device virtserialport,chardev=console0" + +eval $QEMU_CMD \ No newline at end of file diff --git a/bsp/renesas/README.md b/bsp/renesas/README.md index ef89868352f..c843959cacb 100644 --- a/bsp/renesas/README.md +++ b/bsp/renesas/README.md @@ -19,7 +19,8 @@ RA 系列 BSP 目前支持情况如下表所示： | [ra8m1-ek](ra8m1-ek) | Renesas 官方 EK-RA8M1 开发板 | | [ra8d1-ek](ra8d1-ek) | Renesas 官方 EK-RA8D1 开发板 | | [ra8d1-vision-board](ra8d1-vision-board) | Renesas 联合 RT-Thread RA8D1-Vision-Board 开发板 | -| **RZ 系列** | | +| [ra8p1-titan-board](ra8p1-titan-board) | Renesas 联合 RT-Thread RA8P1-Titan-Board 开发板 | +| **RZ 系列** | | | [rzt2m_rsk](rzt2m_rsk) | Renesas 官方 RSK-RZT2M 开发板 | | [rzn2l_rsk](rzn2l_rsk) | Renesas 官方 RSK-RZN2L 开发板 | diff --git a/bsp/renesas/libraries/HAL_Drivers/drivers/SConscript b/bsp/renesas/libraries/HAL_Drivers/drivers/SConscript index 767f470faca..75e41c133a4 100644 --- a/bsp/renesas/libraries/HAL_Drivers/drivers/SConscript +++ b/bsp/renesas/libraries/HAL_Drivers/drivers/SConscript @@ -62,6 +62,9 @@ if GetDepend(['BSP_USING_SDHI']): if GetDepend(['BSP_USING_LCD']): src += ['drv_lcd.c'] +if GetDepend(['BSP_USING_RS485']): + src += ['drv_rs485.c'] + path = [cwd] path += [cwd + '/config'] diff --git a/bsp/renesas/libraries/HAL_Drivers/drivers/config/drv_config.h b/bsp/renesas/libraries/HAL_Drivers/drivers/config/drv_config.h index 598837f30b1..9d758f371eb 100644 --- a/bsp/renesas/libraries/HAL_Drivers/drivers/config/drv_config.h +++ b/bsp/renesas/libraries/HAL_Drivers/drivers/config/drv_config.h @@ -195,6 +195,32 @@ extern "C" #endif /* SOC_SERIES_R7FA8M85 */ +#ifdef SOC_SERIES_R7KA8P1 + +#include "ra8/uart_config.h" + +#ifdef BSP_USING_PWM +#include "ra8/pwm_config.h" +#endif + +#ifdef BSP_USING_ADC +#include "ra8/adc_config.h" +#endif + +#ifdef BSP_USING_DAC +#include "ra8/dac_config.h" +#endif + +#ifdef BSP_USING_TIM +#include "ra8/timer_config.h" +#endif + +#ifdef BSP_USING_CANFD +#include "ra8/canfd_config.h" +#endif + +#endif /* SOC_SERIES_R7KA8P1 */ + #ifdef SOC_SERIES_R9A07G0 #include "rzt/uart_config.h" #include "rzt/timer_config.h" diff --git a/bsp/renesas/libraries/HAL_Drivers/drivers/config/ra8/adc_config.h b/bsp/renesas/libraries/HAL_Drivers/drivers/config/ra8/adc_config.h index 9d36a369c21..238f5fc8f83 100644 --- a/bsp/renesas/libraries/HAL_Drivers/drivers/config/ra8/adc_config.h +++ b/bsp/renesas/libraries/HAL_Drivers/drivers/config/ra8/adc_config.h @@ -31,7 +31,11 @@ struct ra_adc_map const char *device_name; const adc_cfg_t *g_cfg; const adc_ctrl_t *g_ctrl; - const adc_channel_cfg_t *g_channel_cfg; +#ifdef SOC_SERIES_R7KA8P1 + const adc_b_scan_cfg_t *g_channel_cfg; +#else + const adc_channel_cfg_t *g_channel_cfg; +#endif }; #endif #endif diff --git a/bsp/renesas/libraries/HAL_Drivers/drivers/config/ra8/canfd_config.h b/bsp/renesas/libraries/HAL_Drivers/drivers/config/ra8/canfd_config.h new file mode 100644 index 00000000000..207a43097cc --- /dev/null +++ b/bsp/renesas/libraries/HAL_Drivers/drivers/config/ra8/canfd_config.h @@ -0,0 +1,54 @@ +/* + * Copyright (c) 2006-2025, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2025-02-11 kurisaW first version + */ + +#ifndef __CAN_CONFIG_H__ +#define __CAN_CONFIG_H__ + +#include +#include "hal_data.h" + +#if defined(BSP_USING_CANFD) + +#ifdef __cplusplus +extern "C" +{ +#endif + +#if defined(BSP_USING_CAN0) +#ifndef CAN0_CONFIG +#define CAN0_CONFIG \ + { \ + .name = "canfd0", \ + .num_of_mailboxs = 48, \ + .p_api_ctrl = &g_canfd0_ctrl, \ + .p_cfg = &g_canfd0_cfg, \ + } +#endif /* CAN0_CONFIG */ +#endif /* BSP_USING_CAN0 */ + +#if defined(BSP_USING_CAN1) +#ifndef CAN1_CONFIG +#define CAN1_CONFIG \ + { \ + .name = "canfd1", \ + .num_of_mailboxs = 48, \ + .p_api_ctrl = &g_canfd1_ctrl, \ + .p_cfg = &g_canfd1_cfg, \ + } +#endif /* CAN1_CONFIG */ +#endif /* BSP_USING_CAN1 */ + +#ifdef __cplusplus +} +#endif + +#endif /* BSP_USING_CANFD */ + +#endif /* __CAN_CONFIG_H__ */ diff --git a/bsp/renesas/libraries/HAL_Drivers/drivers/config/ra8/pwm_config.h b/bsp/renesas/libraries/HAL_Drivers/drivers/config/ra8/pwm_config.h index d6a0e86ab96..8772d509141 100644 --- a/bsp/renesas/libraries/HAL_Drivers/drivers/config/ra8/pwm_config.h +++ b/bsp/renesas/libraries/HAL_Drivers/drivers/config/ra8/pwm_config.h @@ -58,6 +58,9 @@ enum #endif #ifdef BSP_USING_PWM12 BSP_PWM12_INDEX, +#endif +#ifdef BSP_USING_PWM13 + BSP_PWM13_INDEX, #endif BSP_PWMS_NUM }; diff --git a/bsp/renesas/libraries/HAL_Drivers/drivers/config/ra8/timer_config.h b/bsp/renesas/libraries/HAL_Drivers/drivers/config/ra8/timer_config.h new file mode 100644 index 00000000000..9e2d62b51f3 --- /dev/null +++ b/bsp/renesas/libraries/HAL_Drivers/drivers/config/ra8/timer_config.h @@ -0,0 +1,70 @@ +/* + * Copyright (c) 2006-2023, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2023-09-04 Rbb666 first version + */ + +#ifndef __TIMER_CONFIG_H__ +#define __TIMER_CONFIG_H__ + +#include +#include "hal_data.h" + +#ifdef SOC_SERIES_R7KA8P1 + +#ifdef __cplusplus +extern "C" +{ +#endif + +#define PLCKD_PRESCALER_MAX_SELECT 9 +#define PLCKD_PRESCALER_250M (250000000U) +#define PLCKD_PRESCALER_200M (200000000U) +#define PLCKD_PRESCALER_100M (100000000U) +#define PLCKD_PRESCALER_50M (50000000U) +#define PLCKD_PRESCALER_25M (25000000U) +#define PLCKD_PRESCALER_12_5M (12500000U) +#define PLCKD_PRESCALER_6_25M (6250000U) +#define PLCKD_PRESCALER_3_125M (3125000U) +#define PLCKD_PRESCALER_1_5625M (1562500U) + +#ifndef TMR_DEV_INFO_CONFIG +#define TMR_DEV_INFO_CONFIG \ + { \ + .maxfreq = 250000000, \ + .minfreq = 1562500, \ + .maxcnt = 0XFFFFFFFF, \ + .cntmode = HWTIMER_CNTMODE_UP, \ + } +#endif /* TIM_DEV_INFO_CONFIG */ + +enum +{ +#ifdef BSP_USING_TIM0 + BSP_TIMER0_INDEX, +#endif +#ifdef BSP_USING_TIM1 + BSP_TIMER1_INDEX, +#endif + BSP_TIMERS_NUM +}; + +#define TIMER_DRV_INITIALIZER(num) \ + { \ + .name = "timer" #num, \ + .g_cfg = &g_timer##num##_cfg, \ + .g_ctrl = &g_timer##num##_ctrl, \ + .g_timer = &g_timer##num, \ + } + +#ifdef __cplusplus +} +#endif + +#endif /* SOC_SERIES_R7KA8P1 */ + +#endif /* __TIMER_CONFIG_H__ */ diff --git a/bsp/renesas/libraries/HAL_Drivers/drivers/drv_adc.c b/bsp/renesas/libraries/HAL_Drivers/drivers/drv_adc.c index 37f87a70d8c..09feabeb7a5 100644 --- a/bsp/renesas/libraries/HAL_Drivers/drivers/drv_adc.c +++ b/bsp/renesas/libraries/HAL_Drivers/drivers/drv_adc.c @@ -20,6 +20,17 @@ #endif /* DRV_DEBUG */ #include +#if defined(SOC_SERIES_R7KA8P1) + +#define R_ADC_Open R_ADC_B_Open +#define R_ADC_ScanCfg R_ADC_B_ScanCfg +#define R_ADC_ScanStart R_ADC_B_ScanStart +#define R_ADC_Read32 R_ADC_B_Read32 +#define R_ADC_Read R_ADC_B_Read +#define R_ADC_ScanStop R_ADC_B_ScanStop + +#endif + struct ra_adc_map ra_adc[] = { #ifdef BSP_USING_ADC0 @@ -27,7 +38,11 @@ struct ra_adc_map ra_adc[] = .device_name = "adc0", .g_cfg = &g_adc0_cfg, .g_ctrl = &g_adc0_ctrl, +#ifdef SOC_SERIES_R7KA8P1 + .g_channel_cfg = &g_adc0_scan_cfg, +#else .g_channel_cfg = &g_adc0_channel_cfg, +#endif }, #endif #ifdef BSP_USING_ADC1 diff --git a/bsp/renesas/libraries/HAL_Drivers/drivers/drv_can.c b/bsp/renesas/libraries/HAL_Drivers/drivers/drv_can.c index 80c33813ca0..fdf0ae24240 100644 --- a/bsp/renesas/libraries/HAL_Drivers/drivers/drv_can.c +++ b/bsp/renesas/libraries/HAL_Drivers/drivers/drv_can.c @@ -58,6 +58,45 @@ static const struct ra_baud_rate_tab can_baud_rate_tab[] = #define R_CAN_InfoGet R_CANFD_InfoGet #define R_CAN_Write R_CANFD_Write +#define can0_callback canfd0_callback +#define can1_callback canfd1_callback + +const canfd_afl_entry_t p_canfd0_afl[CANFD_CFG_AFL_CH0_RULE_NUM] = +{ + { + .id = + { + .id = 0x00, + .frame_type = CAN_FRAME_TYPE_DATA, + .id_mode = CAN_ID_MODE_STANDARD + }, + .destination = + { + .minimum_dlc = CANFD_MINIMUM_DLC_0, + .rx_buffer = CANFD_RX_MB_NONE, + .fifo_select_flags = CANFD_RX_FIFO_0 + } + }, +}; + +const canfd_afl_entry_t p_canfd1_afl[CANFD_CFG_AFL_CH1_RULE_NUM] = +{ + { + .id = + { + .id = 0x01, + .frame_type = CAN_FRAME_TYPE_DATA, + .id_mode = CAN_ID_MODE_STANDARD + }, + .destination = + { + .minimum_dlc = CANFD_MINIMUM_DLC_1, + .rx_buffer = CANFD_RX_MB_NONE, + .fifo_select_flags = CANFD_RX_FIFO_1 + } + }, +}; + #endif static rt_uint32_t get_can_baud_index(rt_uint32_t baud) @@ -193,7 +232,7 @@ rt_ssize_t ra_can_sendmsg(struct rt_can_device *can_dev, const void *buf, rt_uin g_can_tx_frame.id_mode = msg_rt->ide; g_can_tx_frame.type = msg_rt->rtr; g_can_tx_frame.data_length_code = msg_rt->len; -#if defined(BSP_USING_CANFD) && defined(BSP_USING_CAN_RZ) +#if defined(BSP_USING_CANFD) && (defined(BSP_USING_CAN_RZ) || defined(BSP_USING_CAN_RA)) g_can_tx_frame.options = 0; #elif defined(BSP_USING_CANFD) g_can_tx_frame.options = CANFD_FRAME_OPTION_FD | CANFD_FRAME_OPTION_BRS; diff --git a/bsp/renesas/libraries/HAL_Drivers/drivers/drv_dac.c b/bsp/renesas/libraries/HAL_Drivers/drivers/drv_dac.c index b971643a80b..6281c103ef5 100644 --- a/bsp/renesas/libraries/HAL_Drivers/drivers/drv_dac.c +++ b/bsp/renesas/libraries/HAL_Drivers/drivers/drv_dac.c @@ -21,6 +21,15 @@ #endif /* DRV_DEBUG */ #include +#if defined(SOC_SERIES_R7KA8P1) + +#define R_DAC_Open R_DAC_B_Open +#define R_DAC_Write R_DAC_B_Write +#define R_DAC_Start R_DAC_B_Start +#define R_DAC_Stop R_DAC_B_Stop + +#endif + struct ra_dac_map ra_dac[] = { #ifdef BSP_USING_DAC0 diff --git a/bsp/renesas/libraries/HAL_Drivers/drivers/drv_eth.c b/bsp/renesas/libraries/HAL_Drivers/drivers/drv_eth.c index 8fe6bcfead5..2f1d1932a1e 100644 --- a/bsp/renesas/libraries/HAL_Drivers/drivers/drv_eth.c +++ b/bsp/renesas/libraries/HAL_Drivers/drivers/drv_eth.c @@ -10,6 +10,7 @@ * 2019-06-10 SummerGift optimize PHY state detection process * 2019-09-03 xiaofan optimize link change detection process * 2025-02-11 kurisaW adaptation for RZ Ethernet driver +* 2025-12-01 yans adaptation for RA8P1 Ethernet driver */ #include "drv_config.h" @@ -22,7 +23,11 @@ // #define ETH_RX_DUMP // #define ETH_TX_DUMP #define MINIMUM_ETHERNET_FRAME_SIZE (60U) +#ifdef SOC_SERIES_R7KA8P1 +#define ETH_MAX_PACKET_SIZE (1514U) +#else #define ETH_MAX_PACKET_SIZE (2048U) +#endif #define ETHER_GMAC_INTERRUPT_FACTOR_RECEPTION (0x000000C0) #define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE #define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE @@ -52,6 +57,34 @@ static uint8_t g_link_change = 0; ///< Link change (bit0:port0, bit1:port1, bit2 static uint8_t g_link_status = 0; ///< Link status (bit0:port0, bit1:port1, bit2:port2) static uint8_t previous_link_status = 0; +/* Multi-PHY support structures */ +typedef struct +{ +#if defined(SOC_SERIES_R7KA8P1) + rmac_phy_instance_ctrl_t *p_ctrl; +#else + ether_phy_instance_ctrl_t *p_ctrl; +#endif + uint8_t port_bit; + const char *name; +} phy_port_info_t; + +static const phy_port_info_t phy_ports[] = +{ +#if defined(SOC_SERIES_R7KA8P1) + { &g_rmac_phy0_ctrl, 0x01, "PHY0" }, + { &g_rmac_phy1_ctrl, 0x02, "PHY1" }, +#elif defined(SOC_SERIES_R9A07G0) + { &g_ether_phy0_ctrl, 0x01, "PHY0" }, + { &g_ether_phy1_ctrl, 0x02, "PHY1" }, + { &g_ether_phy2_ctrl, 0x04, "PHY2" }, +#else + { &g_ether_phy0_ctrl, 0x01, "PHY" }, +#endif +}; + +#define PHY_PORTS_COUNT (sizeof(phy_ports) / sizeof(phy_ports[0])) + #if defined(SOC_SERIES_R9A07G0) #define status_ecsr status_link @@ -62,6 +95,14 @@ static uint8_t previous_link_status = 0; #define R_ETHER_Read R_GMAC_Read #define R_ETHER_LinkProcess R_GMAC_LinkProcess +#elif defined(SOC_SERIES_R7KA8P1) + +#define R_ETHER_Open R_RMAC_Open +#define R_ETHER_Write R_RMAC_Write +#define R_ETHER_Read R_RMAC_Read +#define R_ETHER_LinkProcess R_RMAC_LinkProcess +#define R_ETHER_PHY_LinkStatusGet R_RMAC_PHY_LinkStatusGet + #endif #if defined(ETH_RX_DUMP) || defined(ETH_TX_DUMP) @@ -90,7 +131,6 @@ static void dump_hex(const rt_uint8_t *ptr, rt_size_t buflen) } #endif -extern void phy_reset(void); /* EMAC initialization function */ static rt_err_t rt_ra_eth_init(void) { @@ -139,6 +179,8 @@ static rt_err_t rt_ra_eth_control(rt_device_t dev, int cmd, void *args) { #if defined(SOC_SERIES_R9A07G0) SMEMCPY(args, g_ether0_ctrl.p_gmac_cfg->p_mac_address, 6); +#elif defined(SOC_SERIES_R7KA8P1) + SMEMCPY(args, g_ether0_ctrl.p_cfg->p_mac_address, 6); #else SMEMCPY(args, g_ether0_ctrl.p_ether_cfg->p_mac_address, 6); #endif @@ -209,9 +251,15 @@ rt_err_t rt_ra_eth_tx(rt_device_t dev, struct pbuf *p) } } #endif - res = R_ETHER_Write(&g_ether0_ctrl, buffer, p->tot_len);//>MINIMUM_ETHERNET_FRAME_SIZE?p->tot_len:MINIMUM_ETHERNET_FRAME_SIZE); +#if defined(__DCACHE_PRESENT) + SCB_CleanInvalidateDCache(); +#endif + res = R_ETHER_Write(&g_ether0_ctrl, buffer, p->tot_len < MINIMUM_ETHERNET_FRAME_SIZE ? MINIMUM_ETHERNET_FRAME_SIZE : p->tot_len); if (res != FSP_SUCCESS) + { LOG_W("R_ETHER_Write failed!, res = %d", res); + return (err_t)ERR_USE; + } return RT_EOK; } @@ -234,10 +282,19 @@ struct pbuf *rt_ra_eth_rx(rt_device_t dev) LOG_D("receive frame len : %d", len); +#if defined(__DCACHE_PRESENT) + SCB_CleanInvalidateDCache(); +#endif + if (len > 0) { /* We allocate a pbuf chain of pbufs from the Lwip buffer pool */ p = pbuf_alloc(PBUF_RAW, len, PBUF_POOL); + if (p == NULL) + { + LOG_E("Failed to allocate pbuf for %d bytes", len); + return NULL; + } } #ifdef ETH_RX_DUMP @@ -290,61 +347,77 @@ static void phy_linkchange() fsp_err_t res; uint8_t port = 0; uint8_t port_bit = 0; - -#if defined(SOC_SERIES_R9A07G0) - gmac_link_status_t port_status; -#endif + uint8_t status_change; + uint8_t current_link_status = 0; + uint8_t i; res = R_ETHER_LinkProcess(&g_ether0_ctrl); if (res != FSP_SUCCESS) LOG_D("R_ETHER_LinkProcess failed!, res = %d", res); +#if !defined(SOC_SERIES_R7KA8P1) && !defined(SOC_SERIES_R7FA6M3) if (0 == g_ether0.p_cfg->p_callback) +#endif { - for (port = 0; port < PING_PORT_COUNT; port++) + /* Check link status for all PHY ports */ + for (i = 0; i < PHY_PORTS_COUNT; i++) { -#if defined(SOC_SERIES_R9A07G0) - res = R_GMAC_GetLinkStatus(&g_ether0_ctrl, port, &port_status); -#else - res = R_ETHER_PHY_LinkStatusGet(&g_ether_phy0_ctrl); -#endif - if (FSP_SUCCESS != res) + res = R_ETHER_PHY_LinkStatusGet(phy_ports[i].p_ctrl); + + // ETHER_PHY successfully get link partner ability. + if (res == FSP_SUCCESS) { - /* An error has occurred */ - LOG_E("PHY_LinkStatus get failed!, res = %d", res); - break; + current_link_status |= phy_ports[i].port_bit; /* Port link up */ + + status_change = previous_link_status ^ current_link_status; + if (status_change & phy_ports[i].port_bit) + { + g_link_change |= phy_ports[i].port_bit; + LOG_I("%s Manual Link status changed: UP", phy_ports[i].name); + } } - - /* Set link up */ - g_link_status |= (uint8_t)(1U << port); - } - if (FSP_SUCCESS == res) - { - /* Set changed link status */ - g_link_change = previous_link_status ^ g_link_status; + // PHY-LSI is not link up. + else if (res == FSP_ERR_ETHER_PHY_ERROR_LINK) + { + current_link_status &= ~(phy_ports[i].port_bit); /* Port link down */ + + status_change = previous_link_status ^ current_link_status; + if (status_change & phy_ports[i].port_bit) + { + g_link_change |= phy_ports[i].port_bit; + LOG_I("%s Manual Link status changed: DOWN", phy_ports[i].name); + } + } + else + { + LOG_E("%s PHY_Read failed!, res = %d", phy_ports[i].name, res); + } + /* Update global link status */ + g_link_status = current_link_status; } } - for (port = 0; port < PING_PORT_COUNT; port++) + /* Process link changes for all ports */ + for (port = 0; port < PHY_PORTS_COUNT; port++) { - port_bit = (uint8_t)(1U << port); + port_bit = phy_ports[port].port_bit; if (g_link_change & port_bit) { /* Link status changed */ - g_link_change &= (uint8_t)(~port_bit); // change bit clear + g_link_change &= (uint8_t)(~port_bit); /* change bit clear */ if (g_link_status & port_bit) { /* Changed to Link-up */ eth_device_linkchange(&ra_eth_device.parent, RT_TRUE); - LOG_I("link up"); + LOG_I("%s link up", phy_ports[port].name); } else { /* Changed to Link-down */ eth_device_linkchange(&ra_eth_device.parent, RT_FALSE); - LOG_I("link down"); + LOG_I("%s link down", phy_ports[port].name); } } } @@ -371,7 +444,11 @@ void user_ether0_callback(ether_callback_args_t *p_args) case ETHER_EVENT_WAKEON_LAN: ///< Magic packet detection event /* If EDMAC FR (Frame Receive Event) or FDE (Receive Descriptor Empty Event) * interrupt occurs, send rx mailbox. */ +#if defined(SOC_SERIES_R7KA8P1) + case ETHER_EVENT_RX_COMPLETE: ///< BSD Interrupt event +#else case ETHER_EVENT_INTERRUPT: ///< BSD Interrupt event +#endif { rt_err_t result; result = eth_device_ready(&(ra_eth_device.parent)); diff --git a/bsp/renesas/libraries/HAL_Drivers/drivers/drv_eth.h b/bsp/renesas/libraries/HAL_Drivers/drivers/drv_eth.h index e72d29e3cfa..d2edc6fd2a1 100644 --- a/bsp/renesas/libraries/HAL_Drivers/drivers/drv_eth.h +++ b/bsp/renesas/libraries/HAL_Drivers/drivers/drv_eth.h @@ -105,6 +105,5 @@ #define PHY_LINK (1 << 0) #define PHY_100M (1 << 1) -#define PING_PORT_COUNT (3) ///< Count of port #endif /* __DRV_ETH_H__ */ diff --git a/bsp/renesas/libraries/HAL_Drivers/drivers/drv_gpio.c b/bsp/renesas/libraries/HAL_Drivers/drivers/drv_gpio.c index d92fe298ea2..2ecd823235a 100644 --- a/bsp/renesas/libraries/HAL_Drivers/drivers/drv_gpio.c +++ b/bsp/renesas/libraries/HAL_Drivers/drivers/drv_gpio.c @@ -109,6 +109,58 @@ static void ra_pin_map_init(void) pin_irq_map[15].irq_ctrl = &g_external_irq15_ctrl; pin_irq_map[15].irq_cfg = &g_external_irq15_cfg; #endif +#if defined(VECTOR_NUMBER_ICU_IRQ16) || (VECTOR_NUMBER_IRQ016) + pin_irq_map[16].irq_ctrl = &g_external_irq16_ctrl; + pin_irq_map[16].irq_cfg = &g_external_irq16_cfg; +#endif +#if defined(VECTOR_NUMBER_ICU_IRQ17) || (VECTOR_NUMBER_IRQ017) + pin_irq_map[17].irq_ctrl = &g_external_irq17_ctrl; + pin_irq_map[17].irq_cfg = &g_external_irq17_cfg; +#endif +#if defined(VECTOR_NUMBER_ICU_IRQ18) || (VECTOR_NUMBER_IRQ018) + pin_irq_map[18].irq_ctrl = &g_external_irq18_ctrl; + pin_irq_map[18].irq_cfg = &g_external_irq18_cfg; +#endif +#if defined(VECTOR_NUMBER_ICU_IRQ19) || (VECTOR_NUMBER_IRQ019) + pin_irq_map[19].irq_ctrl = &g_external_irq19_ctrl; + pin_irq_map[19].irq_cfg = &g_external_irq19_cfg; +#endif +#if defined(VECTOR_NUMBER_ICU_IRQ20) || (VECTOR_NUMBER_IRQ020) + pin_irq_map[20].irq_ctrl = &g_external_irq20_ctrl; + pin_irq_map[20].irq_cfg = &g_external_irq20_cfg; +#endif +#if defined(VECTOR_NUMBER_ICU_IRQ21) || (VECTOR_NUMBER_IRQ021) + pin_irq_map[21].irq_ctrl = &g_external_irq21_ctrl; + pin_irq_map[21].irq_cfg = &g_external_irq21_cfg; +#endif +#if defined(VECTOR_NUMBER_ICU_IRQ22) || (VECTOR_NUMBER_IRQ022) + pin_irq_map[22].irq_ctrl = &g_external_irq22_ctrl; + pin_irq_map[22].irq_cfg = &g_external_irq22_cfg; +#endif +#if defined(VECTOR_NUMBER_ICU_IRQ23) || (VECTOR_NUMBER_IRQ023) + pin_irq_map[23].irq_ctrl = &g_external_irq23_ctrl; + pin_irq_map[23].irq_cfg = &g_external_irq23_cfg; +#endif +#if defined(VECTOR_NUMBER_ICU_IRQ24) || (VECTOR_NUMBER_IRQ024) + pin_irq_map[24].irq_ctrl = &g_external_irq24_ctrl; + pin_irq_map[24].irq_cfg = &g_external_irq24_cfg; +#endif +#if defined(VECTOR_NUMBER_ICU_IRQ25) || (VECTOR_NUMBER_IRQ025) + pin_irq_map[25].irq_ctrl = &g_external_irq25_ctrl; + pin_irq_map[25].irq_cfg = &g_external_irq25_cfg; +#endif +#if defined(VECTOR_NUMBER_ICU_IRQ26) || (VECTOR_NUMBER_IRQ026) + pin_irq_map[26].irq_ctrl = &g_external_irq26_ctrl; + pin_irq_map[26].irq_cfg = &g_external_irq26_cfg; +#endif +#if defined(VECTOR_NUMBER_ICU_IRQ27) || (VECTOR_NUMBER_IRQ027) + pin_irq_map[27].irq_ctrl = &g_external_irq27_ctrl; + pin_irq_map[27].irq_cfg = &g_external_irq27_cfg; +#endif +#if defined(VECTOR_NUMBER_ICU_IRQ28) || (VECTOR_NUMBER_IRQ028) + pin_irq_map[28].irq_ctrl = &g_external_irq28_ctrl; + pin_irq_map[28].irq_cfg = &g_external_irq28_cfg; +#endif } #endif /* R_ICU_H */ diff --git a/bsp/renesas/libraries/HAL_Drivers/drivers/drv_hwtimer.c b/bsp/renesas/libraries/HAL_Drivers/drivers/drv_hwtimer.c index 49f5565579a..bf7f2c79a29 100644 --- a/bsp/renesas/libraries/HAL_Drivers/drivers/drv_hwtimer.c +++ b/bsp/renesas/libraries/HAL_Drivers/drivers/drv_hwtimer.c @@ -47,6 +47,16 @@ const rt_uint32_t PLCKD_FREQ_PRESCALER[PLCKD_PRESCALER_MAX_SELECT] = PLCKD_PRESCALER_6_25M, PLCKD_PRESCALER_3_125M, PLCKD_PRESCALER_1_5625M +#elif defined(SOC_SERIES_R7KA8P1) + PLCKD_PRESCALER_250M, + PLCKD_PRESCALER_200M, + PLCKD_PRESCALER_100M, + PLCKD_PRESCALER_50M, + PLCKD_PRESCALER_25M, + PLCKD_PRESCALER_12_5M, + PLCKD_PRESCALER_6_25M, + PLCKD_PRESCALER_3_125M, + PLCKD_PRESCALER_1_5625M #endif }; @@ -117,11 +127,19 @@ static rt_uint32_t timer_counter_get(rt_hwtimer_t *timer) tim = (struct ra_hwtimer *)timer->parent.user_data; +#if defined(SOC_SERIES_R7KA8P1) + timer_info_t info; + if (R_GPT_InfoGet(tim->g_ctrl, &info) != FSP_SUCCESS) + return -RT_ERROR; + + return info.period_counts; +#else timer_status_t status; if (R_GPT_StatusGet(tim->g_ctrl, &status) != FSP_SUCCESS) return -RT_ERROR; return status.counter; +#endif } static rt_err_t timer_ctrl(rt_hwtimer_t *timer, rt_uint32_t cmd, void *arg) diff --git a/bsp/renesas/libraries/HAL_Drivers/drivers/drv_lcd.c b/bsp/renesas/libraries/HAL_Drivers/drivers/drv_lcd.c index f236060fe87..883b43d2bf7 100644 --- a/bsp/renesas/libraries/HAL_Drivers/drivers/drv_lcd.c +++ b/bsp/renesas/libraries/HAL_Drivers/drivers/drv_lcd.c @@ -14,6 +14,8 @@ #ifdef BSP_USING_LCD #ifdef SOC_SERIES_R7FA8M85 #include +#elif defined(SOC_SERIES_R7KA8P1) +#include #else #include #endif @@ -24,6 +26,7 @@ #define DRV_DEBUG #define LOG_TAG "drv_lcd" #include + struct drv_lcd_device { struct rt_device parent; @@ -39,7 +42,7 @@ static uint16_t *gp_double_buffer = NULL; static uint16_t *lcd_current_working_buffer = (uint16_t *) &fb_background[0]; #ifdef SOC_SERIES_R7FA8M85 -static uint8_t lcd_framebuffer[LCD_BUF_SIZE] BSP_ALIGN_VARIABLE(64) BSP_PLACE_IN_SECTION(".sdram"); +static uint8_t lcd_framebuffer[LCD_BUF_SIZE] rt_align(64) rt_section(".sdram") rt_used; #endif // G2D @@ -47,7 +50,7 @@ extern d2_device *d2_handle0; static d2_device **_d2_handle_user = &d2_handle0; static d2_renderbuffer *renderbuffer; -#ifdef SOC_SERIES_R7FA8M85 +#if defined(SOC_SERIES_R7FA8M85) || defined(SOC_SERIES_R7KA8P1) extern void ra8_mipi_lcd_init(void); #endif @@ -85,7 +88,7 @@ static void turn_on_lcd_backlight(void) static void ra_bsp_lcd_clear(uint16_t color) { - for (uint32_t i = 0; i < LCD_BUF_SIZE; i++) + for (uint32_t i = 0; i <= LCD_BUF_SIZE / sizeof(uint16_t); i++) { lcd_current_working_buffer[i] = color; } @@ -262,7 +265,7 @@ static rt_err_t ra_lcd_control(rt_device_t device, int cmd, void *args) { case RTGRAPHIC_CTRL_RECT_UPDATE: { -#ifdef SOC_SERIES_R7FA8M85 +#if defined(SOC_SERIES_R7FA8M85) || defined(SOC_SERIES_R7KA8P1) struct rt_device_rect_info *info = (struct rt_device_rect_info *)args; #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) SCB_CleanInvalidateDCache_by_Addr((uint32_t *)lcd->lcd_info.framebuffer, sizeof(fb_background[0])); @@ -279,7 +282,7 @@ static rt_err_t ra_lcd_control(rt_device_t device, int cmd, void *args) fsp_err_t err = R_GLCDC_BufferChange(&g_display0_ctrl, (uint8_t *) lcd_current_working_buffer, DISPLAY_FRAME_LAYER_1); RT_ASSERT(err == 0); #endif -#endif /* SOC_SERIES_R7FA8M85 */ +#endif /* SOC_SERIES_R7FA8M85 | SOC_SERIES_R7KA8P1 */ /* wait for vsync interrupt */ vsync_wait(); } @@ -340,7 +343,7 @@ static rt_err_t ra_bsp_lcd_init(void) error = R_GLCDC_Open(&g_display0_ctrl, &g_display0_cfg); if (FSP_SUCCESS == error) { -#ifdef SOC_SERIES_R7FA8M85 +#if (defined(SOC_SERIES_R7FA8M85) || defined(SOC_SERIES_R7KA8P1)) && defined(BSP_USING_MIPI_LCD) /* config mipi */ ra8_mipi_lcd_init(); #endif @@ -408,7 +411,7 @@ int rt_hw_lcd_init(void) } INIT_DEVICE_EXPORT(rt_hw_lcd_init); -#ifdef SOC_SERIES_R7FA8M85 +#if defined(SOC_SERIES_R7FA8M85) || defined(SOC_SERIES_R7KA8P1) rt_weak void ra8_mipi_lcd_init(void) { LOG_E("please Implementation function %s", __func__); diff --git a/bsp/renesas/libraries/HAL_Drivers/drivers/drv_pwm.c b/bsp/renesas/libraries/HAL_Drivers/drivers/drv_pwm.c index 4e23a0df1af..6564bff2f7d 100644 --- a/bsp/renesas/libraries/HAL_Drivers/drivers/drv_pwm.c +++ b/bsp/renesas/libraries/HAL_Drivers/drivers/drv_pwm.c @@ -51,6 +51,18 @@ static struct ra_pwm ra6m4_pwm_obj[BSP_PWMS_NUM] = #ifdef BSP_USING_PWM9 [BSP_PWM9_INDEX] = PWM_DRV_INITIALIZER(9), #endif +#ifdef BSP_USING_PWM10 + [BSP_PWM10_INDEX] = PWM_DRV_INITIALIZER(10), +#endif +#ifdef BSP_USING_PWM11 + [BSP_PWM11_INDEX] = PWM_DRV_INITIALIZER(11), +#endif +#ifdef BSP_USING_PWM12 + [BSP_PWM12_INDEX] = PWM_DRV_INITIALIZER(12), +#endif +#ifdef BSP_USING_PWM13 + [BSP_PWM13_INDEX] = PWM_DRV_INITIALIZER(13), +#endif }; #ifdef SOC_SERIES_R9A07G0 diff --git a/bsp/renesas/libraries/HAL_Drivers/drivers/drv_rs485.c b/bsp/renesas/libraries/HAL_Drivers/drivers/drv_rs485.c new file mode 100644 index 00000000000..f4371d22375 --- /dev/null +++ b/bsp/renesas/libraries/HAL_Drivers/drivers/drv_rs485.c @@ -0,0 +1,158 @@ +/* + * Copyright (c) 2006-2025, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2025-07-22 kurisaw first version + */ + +#include +#include +#include "drv_rs485.h" + +#define DBG_TAG "drv.rs485" +#define DBG_LVL DBG_LOG +#include + +#ifdef BSP_USING_RS485 + +#define RS485_OUT rt_pin_write((rt_base_t)RS485_DE_PIN, PIN_HIGH) +#define RS485_IN rt_pin_write((rt_base_t)RS485_DE_PIN, PIN_LOW) + +static rt_device_t rs485_serial = RT_NULL; +static struct rt_semaphore rs485_rx_sem; +static struct rt_ringbuffer rs485_rx_rb; +static rt_uint8_t rs485_rx_buffer[RS485_RX_BUFFER_SIZE]; + +/* uart receive data callback function */ +static rt_err_t rs485_input(rt_device_t dev, rt_size_t size) +{ + if (size > 0) + { + rt_uint8_t ch; + while (rt_device_read(dev, 0, &ch, 1) == 1) + { + rt_ringbuffer_put_force(&rs485_rx_rb, &ch, 1); + } + rt_sem_release(&rs485_rx_sem); + } + return RT_EOK; +} + +/* send data */ +int rs485_send_data(const void *tbuf, rt_uint16_t t_len) +{ + RT_ASSERT(tbuf != RT_NULL); + + /* change rs485 mode to transmit */ + RS485_OUT; + + /* send data */ + rt_size_t sent = rt_device_write(rs485_serial, 0, tbuf, t_len); + + if (sent != t_len) + { + /* Transmission failed, switch back to receive mode */ + RS485_IN; + return -RT_ERROR; + } + + /* Note: We don't switch back to receive mode here - + that will be done in the tx_complete callback (rs485_output) */ + + LOG_I("send==>>"); + for (int i = 0; i < t_len; i++) + { + LOG_I(" %d: %c ", i, ((rt_uint8_t *)tbuf)[i]); + } + RS485_IN; + + return RT_EOK; +} + +#ifndef BSP_USING_LED_MATRIX_RS485_DEMO +static void rs485_thread_entry(void *parameter) +{ + rt_uint8_t ch; + rt_size_t length; + + while (1) + { + /* Wait for data */ + rt_sem_take(&rs485_rx_sem, RT_WAITING_FOREVER); + + /* Process all available data in the ring buffer */ + while (length = rt_ringbuffer_get(&rs485_rx_rb, &ch, 1)) + { + if (length == 1) + { + LOG_I("recv data:%c", ch); + } + } + } +} +#endif + +/* rs485 rts pin init */ +int rs485_init(void) +{ + /* Initialize ring buffer */ + rt_ringbuffer_init(&rs485_rx_rb, rs485_rx_buffer, RS485_RX_BUFFER_SIZE); + + /* find uart device */ + rs485_serial = rt_device_find(RS485_UART_DEVICE_NAME); + if (!rs485_serial) + { + LOG_E("find %s failed!", RS485_UART_DEVICE_NAME); + return -RT_ERROR; + } + + /* Open device in interrupt mode with DMA support if available */ + rt_device_open(rs485_serial, RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_DMA_RX); + + /* set receive data callback function */ + rt_device_set_rx_indicate(rs485_serial, rs485_input); + + /* Initialize RTS pin */ + rt_pin_mode((rt_base_t)RS485_DE_PIN, PIN_MODE_OUTPUT); + RS485_IN; + + /* Initialize semaphore */ + rt_sem_init(&rs485_rx_sem, "rs485_rx_sem", 0, RT_IPC_FLAG_FIFO); + + rt_thread_t thread = rt_thread_create("rs485", rs485_thread_entry, RT_NULL, + 1024, 25, 10); + + if (thread != RT_NULL) + { + rt_thread_startup(thread); + } + else + { + return -RT_ERROR; + } + + return RT_EOK; +} +INIT_DEVICE_EXPORT(rs485_init); + +void rs485_cmd(int argc, char **argv) +{ + if (argc == 1) + { + LOG_I("Usage:"); + LOG_I("rs485_cmd -t -- send message via RS485"); + } + else if (argc == 3 && rt_strcmp(argv[1], "-t") == 0) + { + char *str = argv[2]; + rs485_send_data(str, rt_strnlen(str, 32)); + } + + return; +} +MSH_CMD_EXPORT(rs485_cmd, rs485 transmission cmd); + +#endif /* BSP_USING_RS485 */ diff --git a/bsp/renesas/libraries/HAL_Drivers/drivers/drv_rs485.h b/bsp/renesas/libraries/HAL_Drivers/drivers/drv_rs485.h new file mode 100644 index 00000000000..a0d6dfe72fb --- /dev/null +++ b/bsp/renesas/libraries/HAL_Drivers/drivers/drv_rs485.h @@ -0,0 +1,30 @@ +/* + * Copyright (c) 2006-2025, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2025-07-22 kurisaw first version + */ + +#ifndef __DRV_RS485_H__ +#define __DRV_RS485_H__ + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#define RS485_SEND_MODE 0 +#define RS485_RECV_MODE 1 + +extern int rs485_send_data(const void *tbuf, rt_uint16_t t_len); +extern int rs485_init(void); +#ifdef __cplusplus +} +#endif + +#endif /* drv_rs485.h */ diff --git a/bsp/renesas/libraries/HAL_Drivers/drivers/drv_sci.c b/bsp/renesas/libraries/HAL_Drivers/drivers/drv_sci.c index 4cd7ef70565..7570f83f36e 100644 --- a/bsp/renesas/libraries/HAL_Drivers/drivers/drv_sci.c +++ b/bsp/renesas/libraries/HAL_Drivers/drivers/drv_sci.c @@ -461,7 +461,7 @@ static rt_ssize_t ra_i2c_mst_xfer(struct rt_i2c_bus_device *bus, { //LOG_E("10Bit not support"); //break; -#ifdef SOC_SERIES_R7FA8M85 +#if defined(SOC_SERIES_R7FA8M85) || defined(SOC_SERIES_R7KA8P1) R_SCI_B_I2C_SlaveAddressSet(master_ctrl, msg->addr, I2C_MASTER_ADDR_MODE_10BIT); #else R_SCI_I2C_SlaveAddressSet(master_ctrl, msg->addr, I2C_MASTER_ADDR_MODE_10BIT); @@ -470,7 +470,7 @@ static rt_ssize_t ra_i2c_mst_xfer(struct rt_i2c_bus_device *bus, else { //master_ctrl->slave = msg->addr; -#ifdef SOC_SERIES_R7FA8M85 +#if defined(SOC_SERIES_R7FA8M85) || defined(SOC_SERIES_R7KA8P1) R_SCI_B_I2C_SlaveAddressSet(master_ctrl, msg->addr, I2C_MASTER_ADDR_MODE_7BIT); #else R_SCI_I2C_SlaveAddressSet(master_ctrl, msg->addr, I2C_MASTER_ADDR_MODE_7BIT); @@ -479,7 +479,7 @@ static rt_ssize_t ra_i2c_mst_xfer(struct rt_i2c_bus_device *bus, if (msg->flags & RT_I2C_RD) { -#ifdef SOC_SERIES_R7FA8M85 +#if defined(SOC_SERIES_R7FA8M85) || defined(SOC_SERIES_R7KA8P1) err = R_SCI_B_I2C_Read(master_ctrl, msg->buf, msg->len, restart); #else err = R_SCI_I2C_Read(master_ctrl, msg->buf, msg->len, restart); @@ -487,7 +487,7 @@ static rt_ssize_t ra_i2c_mst_xfer(struct rt_i2c_bus_device *bus, } else { -#ifdef SOC_SERIES_R7FA8M85 +#if defined(SOC_SERIES_R7FA8M85) || defined(SOC_SERIES_R7KA8P1) err = R_SCI_B_I2C_Write(master_ctrl, msg->buf, msg->len, restart); #else err = R_SCI_I2C_Write(master_ctrl, msg->buf, msg->len, restart); @@ -783,7 +783,7 @@ static int ra_hw_sci_init(void) obj->ibus.ops = param->ops; obj->ibus.priv = 0; /* opening IIC master module */ -#ifdef SOC_SERIES_R7FA8M85 +#if defined(SOC_SERIES_R7FA8M85) || defined(SOC_SERIES_R7KA8P1) err = R_SCI_B_I2C_Open((i2c_master_ctrl_t *)param->sci_ctrl, param->sci_cfg); #else err = R_SCI_I2C_Open((i2c_master_ctrl_t *)param->sci_ctrl, param->sci_cfg); @@ -793,7 +793,7 @@ static int ra_hw_sci_init(void) LOG_E("R_IIC_MASTER_Open API failed,%d", err); continue; } -#ifdef SOC_SERIES_R7FA8M85 +#if defined(SOC_SERIES_R7FA8M85) || defined(SOC_SERIES_R7KA8P1) err = R_SCI_B_I2C_CallbackSet((i2c_master_ctrl_t *)param->sci_ctrl, sci_i2c_irq_callback, obj, NULL); #else err = R_SCI_I2C_CallbackSet((i2c_master_ctrl_t *)param->sci_ctrl, sci_i2c_irq_callback, obj, NULL); diff --git a/bsp/renesas/libraries/HAL_Drivers/drivers/drv_sdhi.c b/bsp/renesas/libraries/HAL_Drivers/drivers/drv_sdhi.c index 22863db77aa..a4b2228a578 100644 --- a/bsp/renesas/libraries/HAL_Drivers/drivers/drv_sdhi.c +++ b/bsp/renesas/libraries/HAL_Drivers/drivers/drv_sdhi.c @@ -9,7 +9,6 @@ */ #include -struct ra_sdhi sdhi; #define RTHW_SDIO_LOCK(_sdio) rt_mutex_take(&_sdio->mutex, RT_WAITING_FOREVER) #define RTHW_SDIO_UNLOCK(_sdio) rt_mutex_release(&_sdio->mutex); @@ -20,12 +19,18 @@ struct rthw_sdio struct ra_sdhi sdhi_des; struct rt_event event; struct rt_mutex mutex; + rt_uint8_t *cache_buf; }; -static struct rt_mmcsd_host *host; +#ifdef BSP_USING_SDHI0 + static struct rt_mmcsd_host *host0; +#endif +#ifdef BSP_USING_SDHI1 + static struct rt_mmcsd_host *host1; +#endif rt_align(SDIO_ALIGN_LEN) -static rt_uint8_t cache_buf[SDIO_BUFF_SIZE]; +static rt_uint8_t cache_buf1[SDIO_BUFF_SIZE], cache_buf2[SDIO_BUFF_SIZE]; rt_err_t command_send(sdhi_instance_ctrl_t *p_ctrl, struct rt_mmcsd_cmd *cmd) { @@ -302,14 +307,20 @@ void ra_sdhi_request(struct rt_mmcsd_host *host, struct rt_mmcsd_req *req) rt_uint32_t size = data->blks * data->blksize; RT_ASSERT(size <= SDIO_BUFF_SIZE); - + /* 使用 SDIO WiFi(cyw43438) 时不使用数据流模式 */ +#if defined(SOC_SERIES_R7KA8P1) + if (data->flags & DATA_STREAM) + { + data->flags &= ~DATA_STREAM; + } +#endif buffer = (rt_uint8_t *)data->buf; if ((rt_uint32_t)data->buf & (SDIO_ALIGN_LEN - 1)) { - buffer = cache_buf; + buffer = sdio->cache_buf; if (data->flags & DATA_DIR_WRITE) { - rt_memcpy(cache_buf, data->buf, size); + rt_memcpy(sdio->cache_buf, data->buf, size); } } if (data->flags & DATA_DIR_WRITE) @@ -319,6 +330,9 @@ void ra_sdhi_request(struct rt_mmcsd_host *host, struct rt_mmcsd_req *req) else if (data->flags & DATA_DIR_READ) { transfer_read(sdio->sdhi_des.instance->p_ctrl, data->blks, data->blksize, buffer); +#if defined(__DCACHE_PRESENT) + SCB_CleanInvalidateDCache(); +#endif } /* Set the sector count. */ if (data->blks > 1U) @@ -337,7 +351,10 @@ void ra_sdhi_request(struct rt_mmcsd_host *host, struct rt_mmcsd_req *req) rt_exit_critical(); if ((data != RT_NULL) && (data->flags & DATA_DIR_READ) && ((rt_uint32_t)data->buf & (SDIO_ALIGN_LEN - 1))) { - rt_memcpy(data->buf, cache_buf, data->blksize * data->blks); +#if defined(__DCACHE_PRESENT) + SCB_CleanInvalidateDCache_by_Addr((uint32_t*)((uint32_t)sdio->cache_buf & ~(32U - 1U)), data->blks * data->blksize + 32U); +#endif + rt_memcpy(data->buf, sdio->cache_buf, data->blksize * data->blks); } } @@ -384,7 +401,11 @@ static rt_err_t clock_rate_set(sdhi_instance_ctrl_t *p_ctrl, uint32_t max_rate) /* Set the calculated divider and enable clock output to start the 74 clocks required before * initialization. Do not change the automatic clock control setting. */ uint32_t clkctrlen = p_ctrl->p_reg->SD_CLK_CTRL & (1U << 9); - p_ctrl->p_reg->SD_CLK_CTRL = setting | clkctrlen | (1U << 8); +#if defined(SOC_SERIES_R7KA8P1) + p_ctrl->p_reg->SD_CLK_CTRL = 0x0100 | 0x00FF; +#else + p_ctrl->p_reg->SD_CLK_CTRL = setting | clkctrlen | (1U << 8); +#endif p_ctrl->device.clock_rate = frequency >> divisor_shift; return RT_EOK; @@ -445,11 +466,52 @@ struct rt_mmcsd_host_ops ra_sdhi_ops = .enable_sdio_irq = ra_sdhi_enable_sdio_irq }; -void sdhi_callback(sdmmc_callback_args_t *p_args) +/** + * @brief This function interrupt process function. + * @param host rt_mmcsd_host + * @retval None + */ +void rthw_sdio_irq_process(struct rt_mmcsd_host *host) +{ + struct rthw_sdio *sdio = host->private_data; + rt_event_send(&sdio->event, 0xffffffff); +} + +#ifdef BSP_USING_SDHI0 +void sdhi0_callback(sdmmc_callback_args_t *p_args) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + if ((SDMMC_EVENT_ERASE_COMPLETE | SDMMC_EVENT_TRANSFER_COMPLETE) & p_args->event) + { + /* Process All SDIO Interrupt Sources */ + rthw_sdio_irq_process(host0); + } + + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif + +#ifdef BSP_USING_SDHI1 +void sdhi1_callback(sdmmc_callback_args_t *p_args) { + /* enter interrupt */ + rt_interrupt_enter(); + + if ((SDMMC_EVENT_ERASE_COMPLETE | SDMMC_EVENT_TRANSFER_COMPLETE) & p_args->event) + { + /* Process All SDIO Interrupt Sources */ + rthw_sdio_irq_process(host1); + } + + /* leave interrupt */ + rt_interrupt_leave(); } +#endif -struct rt_mmcsd_host *sdio_host_create(struct ra_sdhi *sdhi_des) +struct rt_mmcsd_host *sdio_host_create(struct ra_sdhi *sdhi_des, rt_uint8_t cache_buf[SDIO_BUFF_SIZE]) { struct rt_mmcsd_host *host; struct rthw_sdio *sdio = RT_NULL; @@ -461,6 +523,7 @@ struct rt_mmcsd_host *sdio_host_create(struct ra_sdhi *sdhi_des) if (sdio == RT_NULL) return RT_NULL; rt_memset(sdio, 0, sizeof(struct rthw_sdio)); + sdio->cache_buf = cache_buf; host = mmcsd_alloc_host(); if (host == RT_NULL) @@ -472,17 +535,17 @@ struct rt_mmcsd_host *sdio_host_create(struct ra_sdhi *sdhi_des) rt_memcpy(&sdio->sdhi_des, sdhi_des, sizeof(struct ra_sdhi)); rt_event_init(&sdio->event, "sdio", RT_IPC_FLAG_FIFO); - rt_mutex_init(&sdio->mutex, "sdio", RT_IPC_FLAG_FIFO); + rt_mutex_init(&sdio->mutex, "sdio", RT_IPC_FLAG_PRIO); - /* set host defautl attributes */ + /* set host default attributes */ host->ops = &ra_sdhi_ops; host->freq_min = 400 * 1000; host->freq_max = SDIO_MAX_FREQ; host->valid_ocr = 0X00FFFF80; /* The voltage range supported is 1.65v-3.6v */ #ifndef SDHI_USING_1_BIT - host->flags = MMCSD_BUSWIDTH_4 | MMCSD_MUTBLKWRITE | MMCSD_SUP_SDIO_IRQ; + host->flags = MMCSD_BUSWIDTH_4 | MMCSD_MUTBLKWRITE | MMCSD_SUP_SDIO_IRQ | MMCSD_SUP_HIGHSPEED; #else - host->flags = MMCSD_MUTBLKWRITE | MMCSD_SUP_SDIO_IRQ; + host->flags = MMCSD_MUTBLKWRITE | MMCSD_SUP_SDIO_IRQ | MMCSD_SUP_HIGHSPEED; #endif host->max_seg_size = SDIO_BUFF_SIZE; host->max_dma_segs = 1; @@ -496,7 +559,9 @@ struct rt_mmcsd_host *sdio_host_create(struct ra_sdhi *sdhi_des) ra_sdhi_enable_sdio_irq(host, 1); /* ready to change */ -// mmcsd_change(host); +#if defined (SOC_SERIES_R7KA8P1) + mmcsd_change(host); +#endif return host; } @@ -504,24 +569,44 @@ struct rt_mmcsd_host *sdio_host_create(struct ra_sdhi *sdhi_des) int rt_hw_sdhi_init(void) { #if defined(BSP_USING_SDHI0) - sdhi.instance = &g_sdmmc0; -#elif defined(BSP_USING_SDHI1) - sdhi.instance = &g_sdmmc1; + struct ra_sdhi sdhi0; + sdhi0.instance = &g_sdmmc0; +#ifndef SDHI_USING_1_BIT + sdhi0.bus_width = MMCSD_BUS_WIDTH_4; #else -#error "please defined the g_sdmmc handle" + sdhi0.bus_width = MMCSD_BUS_WIDTH_1; #endif - - sdhi.instance->p_api->open(sdhi.instance->p_ctrl, sdhi.instance->p_cfg); - host = sdio_host_create(&sdhi); - if (host == RT_NULL) + sdhi0.instance->p_api->open(sdhi0.instance->p_ctrl, sdhi0.instance->p_cfg); + host0 = sdio_host_create(&sdhi0, cache_buf1); + if (host0 == RT_NULL) { return -1; } +#endif +#if defined(BSP_USING_SDHI1) + struct ra_sdhi sdhi1; + sdhi1.instance = &g_sdmmc1; +#ifndef SDHI_USING_1_BIT + sdhi1.bus_width = MMCSD_BUS_WIDTH_4; +#else + sdhi1.bus_width = MMCSD_BUS_WIDTH_1; +#endif + sdhi1.instance->p_api->open(sdhi1.instance->p_ctrl, sdhi1.instance->p_cfg); + host1 = sdio_host_create(&sdhi1, cache_buf2); + if (host1 == RT_NULL) + { + return -1; + } +#endif return 0; } INIT_DEVICE_EXPORT(rt_hw_sdhi_init); void sdcard_change(void) { - mmcsd_change(host); +#if (defined(SOC_SERIES_R7KA8P1) || defined(SOC_SERIES_R7FA6M4)) && defined(BSP_USING_SDHI0) + mmcsd_change(host0); +#elif (defined(SOC_SERIES_R7FA6M3) || defined(SOC_SERIES_R7FA8M85)) && defined(BSP_USING_SDHI1) + mmcsd_change(host1); +#endif } diff --git a/bsp/renesas/libraries/HAL_Drivers/drivers/drv_sdhi.h b/bsp/renesas/libraries/HAL_Drivers/drivers/drv_sdhi.h index a9e5f3165a2..8ce151c807a 100644 --- a/bsp/renesas/libraries/HAL_Drivers/drivers/drv_sdhi.h +++ b/bsp/renesas/libraries/HAL_Drivers/drivers/drv_sdhi.h @@ -46,7 +46,11 @@ #define SDHI_BLK_TRANSFER (1 << 13) #define SDHI_BLK_NOT_AUTO_STOP (1 << 14) -#define SDIO_MAX_FREQ 25000000 +#if defined(SOC_SERIES_R7KA8P1) +#define SDIO_MAX_FREQ (50 * 1000 * 1000) +#else +#define SDIO_MAX_FREQ (25 * 1000 * 1000) +#endif #define HW_SDHI_ERR_CRCE (0x01U << 17) #define HW_SDHI_ERR_RTIMEOUT (0x01U << 22) @@ -61,6 +65,7 @@ struct ra_sdhi { const sdmmc_instance_t *instance; sdmmc_device_t *media_device; + rt_uint8_t bus_width; /* Store bus width (1 or 4) for each SDHI instance */ }; extern void sdcard_change(void); diff --git a/bsp/renesas/libraries/HAL_Drivers/drivers/drv_spi.c b/bsp/renesas/libraries/HAL_Drivers/drivers/drv_spi.c index 20ecdfe4809..50509744068 100644 --- a/bsp/renesas/libraries/HAL_Drivers/drivers/drv_spi.c +++ b/bsp/renesas/libraries/HAL_Drivers/drivers/drv_spi.c @@ -30,7 +30,7 @@ #define RA_SPI2_EVENT 0x03 static struct rt_event complete_event = {0}; -#ifdef SOC_SERIES_R7FA8M85 +#if defined(SOC_SERIES_R7FA8M85) || defined(SOC_SERIES_R7KA8P1) #define R_SPI_Write R_SPI_B_Write #define R_SPI_Read R_SPI_B_Read #define R_SPI_WriteRead R_SPI_B_WriteRead @@ -218,7 +218,7 @@ static rt_err_t ra_hw_spi_configure(struct rt_spi_device *device, rt_pin_write(device->cs_pin, PIN_HIGH); /**< config bitrate */ -#ifdef SOC_SERIES_R7FA8M85 +#if defined(SOC_SERIES_R7FA8M85) || defined(SOC_SERIES_R7KA8P1) R_SPI_B_CalculateBitrate(spi_dev->rt_spi_cfg_t->max_hz, SPI_B_CLOCK_SOURCE_PCLK, &spi_cfg.spck_div); #elif defined(SOC_SERIES_R9A07G0) R_SPI_CalculateBitrate(spi_dev->rt_spi_cfg_t->max_hz, SPI_CLOCK_SOURCE_PCLKM, &spi_cfg.spck_div); diff --git a/bsp/renesas/libraries/HAL_Drivers/drivers/drv_usart_v2.c b/bsp/renesas/libraries/HAL_Drivers/drivers/drv_usart_v2.c index 8abbd917f84..7509f3f3b11 100644 --- a/bsp/renesas/libraries/HAL_Drivers/drivers/drv_usart_v2.c +++ b/bsp/renesas/libraries/HAL_Drivers/drivers/drv_usart_v2.c @@ -211,7 +211,7 @@ static rt_err_t ra_uart_configure(struct rt_serial_device *serial, struct serial uart = rt_container_of(serial, struct ra_uart, serial); RT_ASSERT(uart != RT_NULL); -#ifdef SOC_SERIES_R7FA8M85 +#if defined(SOC_SERIES_R7FA8M85) || defined(SOC_SERIES_R7KA8P1) err = R_SCI_B_UART_Open(uart->config->p_api_ctrl, uart->config->p_cfg); #else err = R_SCI_UART_Open(uart->config->p_api_ctrl, uart->config->p_cfg); @@ -237,7 +237,7 @@ static int ra_uart_putc(struct rt_serial_device *serial, char c) uart = rt_container_of(serial, struct ra_uart, serial); RT_ASSERT(uart != RT_NULL); -#ifdef SOC_SERIES_R7FA8M85 +#if defined(SOC_SERIES_R7FA8M85) || defined(SOC_SERIES_R7KA8P1) sci_b_uart_instance_ctrl_t *p_ctrl = (sci_b_uart_instance_ctrl_t *)uart->config->p_api_ctrl; #else sci_uart_instance_ctrl_t *p_ctrl = (sci_uart_instance_ctrl_t *)uart->config->p_api_ctrl; @@ -245,7 +245,7 @@ static int ra_uart_putc(struct rt_serial_device *serial, char c) p_ctrl->p_reg->TDR = c; -#if defined(SOC_SERIES_R7FA8M85) || defined(SOC_SERIES_R9A07G0) +#if defined(SOC_SERIES_R7FA8M85) || defined(SOC_SERIES_R9A07G0) || defined(SOC_SERIES_R7KA8P1) while ((p_ctrl->p_reg->CSR_b.TEND) == 0); #else while ((p_ctrl->p_reg->SSR_b.TEND) == 0); diff --git a/bsp/renesas/libraries/HAL_Drivers/drv_common.c b/bsp/renesas/libraries/HAL_Drivers/drv_common.c index f2d4b4f3723..b85e180cbae 100644 --- a/bsp/renesas/libraries/HAL_Drivers/drv_common.c +++ b/bsp/renesas/libraries/HAL_Drivers/drv_common.c @@ -170,6 +170,12 @@ rt_weak void rt_hw_board_init() rt_hw_interrupt_init(); #endif +#if defined(BSP_CFG_CPU_CORE) && (BSP_CFG_CPU_CORE == CPU0) && defined(SOC_SERIES_R7KA8P1) && defined(BSP_START_SECONDARY_CORE) + #if !defined(BSP_USING_RPMSG_LITE_MCMGR) + R_BSP_SecondaryCoreStart(); + #endif +#endif + rt_hw_systick_init(); /* Heap initialization */ diff --git a/bsp/renesas/libraries/Kconfig b/bsp/renesas/libraries/Kconfig index 239dbd62349..40b97913f0e 100644 --- a/bsp/renesas/libraries/Kconfig +++ b/bsp/renesas/libraries/Kconfig @@ -61,6 +61,12 @@ config SOC_SERIES_R7FA8M85 select SOC_FAMILY_RENESAS_RA default n +config SOC_SERIES_R7KA8P1 + bool + select ARCH_ARM_CORTEX_M85 + select SOC_FAMILY_RENESAS_RA + default n + config SOC_SERIES_R9A07G0 bool select ARCH_ARM_CORTEX_R52 diff --git a/bsp/renesas/ra8p1-titan-board/.ci/attachconfig/attachconfig.yml b/bsp/renesas/ra8p1-titan-board/.ci/attachconfig/attachconfig.yml new file mode 100644 index 00000000000..3e6cf30168e --- /dev/null +++ b/bsp/renesas/ra8p1-titan-board/.ci/attachconfig/attachconfig.yml @@ -0,0 +1,40 @@ +# ------ devices CI ------ +devices.adc: + kconfig: + - CONFIG_RT_USING_ADC=y + - CONFIG_BSP_USING_ADC0=y +devices.spi: + kconfig: + - CONFIG_BSP_USING_SPI=y + - CONFIG_BSP_USING_SPI0=y +devices.i2c: + kconfig: + - CONFIG_BSP_USING_HW_I2C=y + - CONFIG_BSP_USING_HW_I2C2=y +devices.sdhi: + kconfig: + - CONFIG_BSP_USING_SDHI=y + - CONFIG_BSP_USING_SDHI0=y + - CONFIG_SDHI_USING_1_BIT=y +devices.timer: + kconfig: + - CONFIG_BSP_USING_TIM=y + - CONFIG_BSP_USING_TIM0=y +devices.pwm: + kconfig: + - CONFIG_BSP_USING_PWM=y + - CONFIG_BSP_USING_PWM12=y +devices.can: + kconfig: + - CONFIG_BSP_USING_CANFD=y + - CONFIG_BSP_USING_CAN_RA=y + - CONFIG_BSP_USING_CAN0=y +devices.hyperram: + kconfig: + - CONFIG_BSP_USING_OSPI_RAM=y +devices.ethernet: + kconfig: + - CONFIG_BSP_USING_ETH=y +devices.rtc: + kconfig: + - CONFIG_BSP_USING_ONCHIP_RTC=y diff --git a/bsp/renesas/ra8p1-titan-board/.config b/bsp/renesas/ra8p1-titan-board/.config new file mode 100644 index 00000000000..8e695e5f0fa --- /dev/null +++ b/bsp/renesas/ra8p1-titan-board/.config @@ -0,0 +1,1466 @@ +CONFIG_SOC_R7KA8P1KF=y + +# +# RT-Thread Kernel +# + +# +# klibc options +# + +# +# rt_vsnprintf options +# +# CONFIG_RT_KLIBC_USING_LIBC_VSNPRINTF is not set +# CONFIG_RT_KLIBC_USING_VSNPRINTF_LONGLONG is not set +# CONFIG_RT_KLIBC_USING_VSNPRINTF_STANDARD is not set +# end of rt_vsnprintf options + +# +# rt_vsscanf options +# +# CONFIG_RT_KLIBC_USING_LIBC_VSSCANF is not set +# end of rt_vsscanf options + +# +# rt_memset options +# +# CONFIG_RT_KLIBC_USING_USER_MEMSET is not set +# CONFIG_RT_KLIBC_USING_LIBC_MEMSET is not set +# CONFIG_RT_KLIBC_USING_TINY_MEMSET is not set +# end of rt_memset options + +# +# rt_memcpy options +# +# CONFIG_RT_KLIBC_USING_USER_MEMCPY is not set +# CONFIG_RT_KLIBC_USING_LIBC_MEMCPY is not set +# CONFIG_RT_KLIBC_USING_TINY_MEMCPY is not set +# end of rt_memcpy options + +# +# rt_memmove options +# +# CONFIG_RT_KLIBC_USING_USER_MEMMOVE is not set +# CONFIG_RT_KLIBC_USING_LIBC_MEMMOVE is not set +# end of rt_memmove options + +# +# rt_memcmp options +# +# CONFIG_RT_KLIBC_USING_USER_MEMCMP is not set +# CONFIG_RT_KLIBC_USING_LIBC_MEMCMP is not set +# end of rt_memcmp options + +# +# rt_strstr options +# +# CONFIG_RT_KLIBC_USING_USER_STRSTR is not set +# CONFIG_RT_KLIBC_USING_LIBC_STRSTR is not set +# end of rt_strstr options + +# +# rt_strcasecmp options +# +# CONFIG_RT_KLIBC_USING_USER_STRCASECMP is not set +# end of rt_strcasecmp options + +# +# rt_strncpy options +# +# CONFIG_RT_KLIBC_USING_USER_STRNCPY is not set +# CONFIG_RT_KLIBC_USING_LIBC_STRNCPY is not set +# end of rt_strncpy options + +# +# rt_strcpy options +# +# CONFIG_RT_KLIBC_USING_USER_STRCPY is not set +# CONFIG_RT_KLIBC_USING_LIBC_STRCPY is not set +# end of rt_strcpy options + +# +# rt_strncmp options +# +# CONFIG_RT_KLIBC_USING_USER_STRNCMP is not set +# CONFIG_RT_KLIBC_USING_LIBC_STRNCMP is not set +# end of rt_strncmp options + +# +# rt_strcmp options +# +# CONFIG_RT_KLIBC_USING_USER_STRCMP is not set +# CONFIG_RT_KLIBC_USING_LIBC_STRCMP is not set +# end of rt_strcmp options + +# +# rt_strlen options +# +# CONFIG_RT_KLIBC_USING_USER_STRLEN is not set +# CONFIG_RT_KLIBC_USING_LIBC_STRLEN is not set +# end of rt_strlen options + +# +# rt_strnlen options +# +# CONFIG_RT_KLIBC_USING_USER_STRNLEN is not set +# end of rt_strnlen options +# end of klibc options + +CONFIG_RT_NAME_MAX=20 +# CONFIG_RT_USING_ARCH_DATA_TYPE is not set +# CONFIG_RT_USING_NANO is not set +# CONFIG_RT_USING_SMART is not set +# CONFIG_RT_USING_AMP is not set +# CONFIG_RT_USING_SMP is not set +CONFIG_RT_CPUS_NR=1 +CONFIG_RT_ALIGN_SIZE=8 +# CONFIG_RT_THREAD_PRIORITY_8 is not set +CONFIG_RT_THREAD_PRIORITY_32=y +# CONFIG_RT_THREAD_PRIORITY_256 is not set +CONFIG_RT_THREAD_PRIORITY_MAX=32 +CONFIG_RT_TICK_PER_SECOND=1000 +CONFIG_RT_USING_OVERFLOW_CHECK=y +CONFIG_RT_USING_HOOK=y +CONFIG_RT_HOOK_USING_FUNC_PTR=y +# CONFIG_RT_USING_HOOKLIST is not set +CONFIG_RT_USING_IDLE_HOOK=y +CONFIG_RT_IDLE_HOOK_LIST_SIZE=4 +CONFIG_IDLE_THREAD_STACK_SIZE=256 +CONFIG_RT_USING_TIMER_SOFT=y +CONFIG_RT_TIMER_THREAD_PRIO=4 +CONFIG_RT_TIMER_THREAD_STACK_SIZE=512 +# CONFIG_RT_USING_TIMER_ALL_SOFT is not set +# CONFIG_RT_USING_CPU_USAGE_TRACER is not set + +# +# kservice options +# +# CONFIG_RT_USING_TINY_FFS is not set +# end of kservice options + +CONFIG_RT_USING_DEBUG=y +CONFIG_RT_DEBUGING_ASSERT=y +CONFIG_RT_DEBUGING_COLOR=y +CONFIG_RT_DEBUGING_CONTEXT=y +# CONFIG_RT_DEBUGING_AUTO_INIT is not set +# CONFIG_RT_USING_CI_ACTION is not set + +# +# Inter-Thread communication +# +CONFIG_RT_USING_SEMAPHORE=y +CONFIG_RT_USING_MUTEX=y +CONFIG_RT_USING_EVENT=y +CONFIG_RT_USING_MAILBOX=y +CONFIG_RT_USING_MESSAGEQUEUE=y +# CONFIG_RT_USING_MESSAGEQUEUE_PRIORITY is not set +# CONFIG_RT_USING_SIGNALS is not set +# end of Inter-Thread communication + +# +# Memory Management +# +CONFIG_RT_USING_MEMPOOL=y +# CONFIG_RT_USING_SMALL_MEM is not set +# CONFIG_RT_USING_SLAB is not set +CONFIG_RT_USING_MEMHEAP=y +CONFIG_RT_MEMHEAP_FAST_MODE=y +# CONFIG_RT_MEMHEAP_BEST_MODE is not set +# CONFIG_RT_USING_SMALL_MEM_AS_HEAP is not set +CONFIG_RT_USING_MEMHEAP_AS_HEAP=y +CONFIG_RT_USING_MEMHEAP_AUTO_BINDING=y +# CONFIG_RT_USING_SLAB_AS_HEAP is not set +# CONFIG_RT_USING_USERHEAP is not set +# CONFIG_RT_USING_NOHEAP is not set +# CONFIG_RT_USING_MEMTRACE is not set +# CONFIG_RT_USING_HEAP_ISR is not set +CONFIG_RT_USING_HEAP=y +# end of Memory Management + +CONFIG_RT_USING_DEVICE=y +# CONFIG_RT_USING_DEVICE_OPS is not set +# CONFIG_RT_USING_INTERRUPT_INFO is not set +# CONFIG_RT_USING_THREADSAFE_PRINTF is not set +CONFIG_RT_USING_CONSOLE=y +CONFIG_RT_CONSOLEBUF_SIZE=128 +CONFIG_RT_CONSOLE_DEVICE_NAME="uart8" +CONFIG_RT_VER_NUM=0x50201 +# CONFIG_RT_USING_STDC_ATOMIC is not set +CONFIG_RT_BACKTRACE_LEVEL_MAX_NR=32 +# end of RT-Thread Kernel + +CONFIG_RT_USING_HW_ATOMIC=y +CONFIG_RT_USING_CPU_FFS=y +CONFIG_ARCH_ARM=y +CONFIG_ARCH_ARM_CORTEX_M=y +CONFIG_ARCH_ARM_CORTEX_M85=y + +# +# RT-Thread Components +# +CONFIG_RT_USING_COMPONENTS_INIT=y +CONFIG_RT_USING_USER_MAIN=y +CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048 +CONFIG_RT_MAIN_THREAD_PRIORITY=10 +# CONFIG_RT_USING_LEGACY is not set +CONFIG_RT_USING_MSH=y +CONFIG_RT_USING_FINSH=y +CONFIG_FINSH_USING_MSH=y +CONFIG_FINSH_THREAD_NAME="tshell" +CONFIG_FINSH_THREAD_PRIORITY=20 +CONFIG_FINSH_THREAD_STACK_SIZE=4096 +CONFIG_FINSH_USING_HISTORY=y +CONFIG_FINSH_HISTORY_LINES=5 +# CONFIG_FINSH_USING_WORD_OPERATION is not set +# CONFIG_FINSH_USING_FUNC_EXT is not set +CONFIG_FINSH_USING_SYMTAB=y +CONFIG_FINSH_CMD_SIZE=80 +CONFIG_MSH_USING_BUILT_IN_COMMANDS=y +CONFIG_FINSH_USING_DESCRIPTION=y +# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set +# CONFIG_FINSH_USING_AUTH is not set +CONFIG_FINSH_ARG_MAX=10 +CONFIG_FINSH_USING_OPTION_COMPLETION=y + +# +# DFS: device virtual file system +# +# CONFIG_RT_USING_DFS is not set +# end of DFS: device virtual file system + +# CONFIG_RT_USING_FAL is not set + +# +# Device Drivers +# +# CONFIG_RT_USING_DM is not set +# CONFIG_RT_USING_DEV_BUS is not set +CONFIG_RT_USING_DEVICE_IPC=y +CONFIG_RT_UNAMED_PIPE_NUMBER=64 +CONFIG_RT_USING_SYSTEM_WORKQUEUE=y +CONFIG_RT_SYSTEM_WORKQUEUE_STACKSIZE=2048 +CONFIG_RT_SYSTEM_WORKQUEUE_PRIORITY=23 +CONFIG_RT_USING_SERIAL=y +# CONFIG_RT_USING_SERIAL_V1 is not set +CONFIG_RT_USING_SERIAL_V2=y +# CONFIG_RT_SERIAL_BUF_STRATEGY_DROP is not set +CONFIG_RT_SERIAL_BUF_STRATEGY_OVERWRITE=y +CONFIG_RT_SERIAL_USING_DMA=y +# CONFIG_RT_USING_SERIAL_BYPASS is not set +# CONFIG_RT_USING_CAN is not set +# CONFIG_RT_USING_CPUTIME is not set +# CONFIG_RT_USING_I2C is not set +# CONFIG_RT_USING_PHY is not set +# CONFIG_RT_USING_PHY_V2 is not set +# CONFIG_RT_USING_ADC is not set +# CONFIG_RT_USING_DAC is not set +# CONFIG_RT_USING_NULL is not set +# CONFIG_RT_USING_ZERO is not set +# CONFIG_RT_USING_RANDOM is not set +# CONFIG_RT_USING_PWM is not set +# CONFIG_RT_USING_PULSE_ENCODER is not set +# CONFIG_RT_USING_INPUT_CAPTURE is not set +CONFIG_RT_USING_MTD_NOR=y +# CONFIG_RT_USING_MTD_NAND is not set +# CONFIG_RT_USING_PM is not set +# CONFIG_RT_USING_RTC is not set +# CONFIG_RT_USING_SDIO is not set +# CONFIG_RT_USING_SPI is not set +# CONFIG_RT_USING_WDT is not set +# CONFIG_RT_USING_AUDIO is not set +# CONFIG_RT_USING_SENSOR is not set +# CONFIG_RT_USING_TOUCH is not set +# CONFIG_RT_USING_LCD is not set +# CONFIG_RT_USING_HWCRYPTO is not set +# CONFIG_RT_USING_WIFI is not set +# CONFIG_RT_USING_BLK is not set +# CONFIG_RT_USING_VIRTIO is not set +CONFIG_RT_USING_PIN=y +# CONFIG_RT_USING_KTIME is not set +# CONFIG_RT_USING_HWTIMER is not set +# CONFIG_RT_USING_CHERRYUSB is not set +# end of Device Drivers + +# +# C/C++ and POSIX layer +# + +# +# ISO-ANSI C layer +# + +# +# Timezone and Daylight Saving Time +# +# CONFIG_RT_LIBC_USING_FULL_TZ_DST is not set +CONFIG_RT_LIBC_USING_LIGHT_TZ_DST=y +CONFIG_RT_LIBC_TZ_DEFAULT_HOUR=8 +CONFIG_RT_LIBC_TZ_DEFAULT_MIN=0 +CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 +# end of Timezone and Daylight Saving Time +# end of ISO-ANSI C layer + +# +# POSIX (Portable Operating System Interface) layer +# +# CONFIG_RT_USING_POSIX_FS is not set +# CONFIG_RT_USING_POSIX_DELAY is not set +# CONFIG_RT_USING_POSIX_CLOCK is not set +# CONFIG_RT_USING_POSIX_TIMER is not set +# CONFIG_RT_USING_PTHREADS is not set +# CONFIG_RT_USING_MODULE is not set + +# +# Interprocess Communication (IPC) +# +# CONFIG_RT_USING_POSIX_PIPE is not set +# CONFIG_RT_USING_POSIX_MESSAGE_QUEUE is not set +# CONFIG_RT_USING_POSIX_MESSAGE_SEMAPHORE is not set + +# +# Socket is in the 'Network' category +# +# end of Interprocess Communication (IPC) +# end of POSIX (Portable Operating System Interface) layer + +# CONFIG_RT_USING_CPLUSPLUS is not set +# end of C/C++ and POSIX layer + +# +# Network +# +# CONFIG_RT_USING_SAL is not set +# CONFIG_RT_USING_NETDEV is not set +# CONFIG_RT_USING_LWIP is not set +# CONFIG_RT_USING_AT is not set +# end of Network + +# +# Memory protection +# +# CONFIG_RT_USING_MEM_PROTECTION is not set +# CONFIG_RT_USING_HW_STACK_GUARD is not set +# end of Memory protection + +# +# Utilities +# +# CONFIG_RT_USING_RYM is not set +# CONFIG_RT_USING_ULOG is not set +# CONFIG_RT_USING_UTEST is not set +# CONFIG_RT_USING_VAR_EXPORT is not set +# CONFIG_RT_USING_RESOURCE_ID is not set +# CONFIG_RT_USING_ADT is not set +# CONFIG_RT_USING_RT_LINK is not set +# end of Utilities + +# +# Using USB legacy version +# +# CONFIG_RT_USING_USB_HOST is not set +# CONFIG_RT_USING_USB_DEVICE is not set +# end of Using USB legacy version + +# CONFIG_RT_USING_FDT is not set +# end of RT-Thread Components + +# +# RT-Thread Utestcases +# +# CONFIG_RT_USING_UTESTCASES is not set +# end of RT-Thread Utestcases + +# +# RT-Thread online packages +# + +# +# IoT - internet of things +# +# CONFIG_PKG_USING_LORAWAN_DRIVER is not set +# CONFIG_PKG_USING_PAHOMQTT is not set +# CONFIG_PKG_USING_UMQTT is not set +# CONFIG_PKG_USING_WEBCLIENT is not set +# CONFIG_PKG_USING_WEBNET is not set +# CONFIG_PKG_USING_MONGOOSE is not set +# CONFIG_PKG_USING_MYMQTT is not set +# CONFIG_PKG_USING_KAWAII_MQTT is not set +# CONFIG_PKG_USING_BC28_MQTT is not set +# CONFIG_PKG_USING_WEBTERMINAL is not set +# CONFIG_PKG_USING_FREEMODBUS is not set +# CONFIG_PKG_USING_NANOPB is not set +# CONFIG_PKG_USING_WIFI_HOST_DRIVER is not set +# CONFIG_PKG_USING_ESP_HOSTED is not set + +# +# Wi-Fi +# + +# +# Marvell WiFi +# +# CONFIG_PKG_USING_WLANMARVELL is not set +# end of Marvell WiFi + +# +# Wiced WiFi +# +# CONFIG_PKG_USING_WLAN_WICED is not set +# end of Wiced WiFi + +# CONFIG_PKG_USING_RW007 is not set + +# +# CYW43012 WiFi +# +# CONFIG_PKG_USING_WLAN_CYW43012 is not set +# end of CYW43012 WiFi + +# +# BL808 WiFi +# +# CONFIG_PKG_USING_WLAN_BL808 is not set +# end of BL808 WiFi + +# +# CYW43439 WiFi +# +# CONFIG_PKG_USING_WLAN_CYW43439 is not set +# end of CYW43439 WiFi +# end of Wi-Fi + +# CONFIG_PKG_USING_COAP is not set +# CONFIG_PKG_USING_NOPOLL is not set +# CONFIG_PKG_USING_NETUTILS is not set +# CONFIG_PKG_USING_CMUX is not set +# CONFIG_PKG_USING_PPP_DEVICE is not set +# CONFIG_PKG_USING_AT_DEVICE is not set +# CONFIG_PKG_USING_ATSRV_SOCKET is not set +# CONFIG_PKG_USING_WIZNET is not set +# CONFIG_PKG_USING_ZB_COORDINATOR is not set + +# +# IoT Cloud +# +# CONFIG_PKG_USING_ONENET is not set +# CONFIG_PKG_USING_GAGENT_CLOUD is not set +# CONFIG_PKG_USING_ALI_IOTKIT is not set +# CONFIG_PKG_USING_AZURE is not set +# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set +# CONFIG_PKG_USING_JIOT-C-SDK is not set +# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set +# CONFIG_PKG_USING_JOYLINK is not set +# CONFIG_PKG_USING_IOTSHARP_SDK is not set +# end of IoT Cloud + +# CONFIG_PKG_USING_NIMBLE is not set +# CONFIG_PKG_USING_LLSYNC_SDK_ADAPTER is not set +# CONFIG_PKG_USING_OTA_DOWNLOADER is not set +# CONFIG_PKG_USING_IPMSG is not set +# CONFIG_PKG_USING_LSSDP is not set +# CONFIG_PKG_USING_AIRKISS_OPEN is not set +# CONFIG_PKG_USING_LIBRWS is not set +# CONFIG_PKG_USING_TCPSERVER is not set +# CONFIG_PKG_USING_PROTOBUF_C is not set +# CONFIG_PKG_USING_DLT645 is not set +# CONFIG_PKG_USING_QXWZ is not set +# CONFIG_PKG_USING_SMTP_CLIENT is not set +# CONFIG_PKG_USING_ABUP_FOTA is not set +# CONFIG_PKG_USING_LIBCURL2RTT is not set +# CONFIG_PKG_USING_CAPNP is not set +# CONFIG_PKG_USING_AGILE_TELNET is not set +# CONFIG_PKG_USING_NMEALIB is not set +# CONFIG_PKG_USING_PDULIB is not set +# CONFIG_PKG_USING_BTSTACK is not set +# CONFIG_PKG_USING_BT_CYW43012 is not set +# CONFIG_PKG_USING_CYW43XX is not set +# CONFIG_PKG_USING_LORAWAN_ED_STACK is not set +# CONFIG_PKG_USING_WAYZ_IOTKIT is not set +# CONFIG_PKG_USING_MAVLINK is not set +# CONFIG_PKG_USING_BSAL is not set +# CONFIG_PKG_USING_AGILE_MODBUS is not set +# CONFIG_PKG_USING_AGILE_FTP is not set +# CONFIG_PKG_USING_EMBEDDEDPROTO is not set +# CONFIG_PKG_USING_RT_LINK_HW is not set +# CONFIG_PKG_USING_RYANMQTT is not set +# CONFIG_PKG_USING_RYANW5500 is not set +# CONFIG_PKG_USING_LORA_PKT_FWD is not set +# CONFIG_PKG_USING_LORA_GW_DRIVER_LIB is not set +# CONFIG_PKG_USING_LORA_PKT_SNIFFER is not set +# CONFIG_PKG_USING_HM is not set +# CONFIG_PKG_USING_SMALL_MODBUS is not set +# CONFIG_PKG_USING_NET_SERVER is not set +# CONFIG_PKG_USING_ZFTP is not set +# CONFIG_PKG_USING_WOL is not set +# CONFIG_PKG_USING_ZEPHYR_POLLING is not set +# CONFIG_PKG_USING_MATTER_ADAPTATION_LAYER is not set +# CONFIG_PKG_USING_LHC_MODBUS is not set +# CONFIG_PKG_USING_QMODBUS is not set +# CONFIG_PKG_USING_PNET is not set +# CONFIG_PKG_USING_OPENER is not set +# CONFIG_PKG_USING_FREEMQTT is not set +# end of IoT - internet of things + +# +# security packages +# +# CONFIG_PKG_USING_MBEDTLS is not set +# CONFIG_PKG_USING_LIBSODIUM is not set +# CONFIG_PKG_USING_LIBHYDROGEN is not set +# CONFIG_PKG_USING_TINYCRYPT is not set +# CONFIG_PKG_USING_TFM is not set +# CONFIG_PKG_USING_YD_CRYPTO is not set +# end of security packages + +# +# language packages +# + +# +# JSON: JavaScript Object Notation, a lightweight data-interchange format +# +# CONFIG_PKG_USING_CJSON is not set +# CONFIG_PKG_USING_LJSON is not set +# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set +# CONFIG_PKG_USING_RAPIDJSON is not set +# CONFIG_PKG_USING_JSMN is not set +# CONFIG_PKG_USING_AGILE_JSMN is not set +# CONFIG_PKG_USING_PARSON is not set +# CONFIG_PKG_USING_RYAN_JSON is not set +# end of JSON: JavaScript Object Notation, a lightweight data-interchange format + +# +# XML: Extensible Markup Language +# +# CONFIG_PKG_USING_SIMPLE_XML is not set +# CONFIG_PKG_USING_EZXML is not set +# end of XML: Extensible Markup Language + +# CONFIG_PKG_USING_LUATOS_SOC is not set +# CONFIG_PKG_USING_LUA is not set +# CONFIG_PKG_USING_JERRYSCRIPT is not set +# CONFIG_PKG_USING_MICROPYTHON is not set +# CONFIG_PKG_USING_PIKASCRIPT is not set +# CONFIG_PKG_USING_RTT_RUST is not set +# end of language packages + +# +# multimedia packages +# + +# +# LVGL: powerful and easy-to-use embedded GUI library +# +# CONFIG_PKG_USING_LVGL is not set +# CONFIG_PKG_USING_LV_MUSIC_DEMO is not set +# CONFIG_PKG_USING_GUI_GUIDER_DEMO is not set +# end of LVGL: powerful and easy-to-use embedded GUI library + +# +# u8g2: a monochrome graphic library +# +# CONFIG_PKG_USING_U8G2_OFFICIAL is not set +# CONFIG_PKG_USING_U8G2 is not set +# end of u8g2: a monochrome graphic library + +# CONFIG_PKG_USING_OPENMV is not set +# CONFIG_PKG_USING_MUPDF is not set +# CONFIG_PKG_USING_STEMWIN is not set +# CONFIG_PKG_USING_WAVPLAYER is not set +# CONFIG_PKG_USING_TJPGD is not set +# CONFIG_PKG_USING_PDFGEN is not set +# CONFIG_PKG_USING_HELIX is not set +# CONFIG_PKG_USING_AZUREGUIX is not set +# CONFIG_PKG_USING_TOUCHGFX2RTT is not set +# CONFIG_PKG_USING_NUEMWIN is not set +# CONFIG_PKG_USING_MP3PLAYER is not set +# CONFIG_PKG_USING_TINYJPEG is not set +# CONFIG_PKG_USING_UGUI is not set +# CONFIG_PKG_USING_MCURSES is not set +# CONFIG_PKG_USING_TERMBOX is not set +# CONFIG_PKG_USING_VT100 is not set +# CONFIG_PKG_USING_QRCODE is not set +# CONFIG_PKG_USING_GUIENGINE is not set +# CONFIG_PKG_USING_3GPP_AMRNB is not set +# end of multimedia packages + +# +# tools packages +# +# CONFIG_PKG_USING_CMBACKTRACE is not set +# CONFIG_PKG_USING_MCOREDUMP is not set +# CONFIG_PKG_USING_EASYFLASH is not set +# CONFIG_PKG_USING_EASYLOGGER is not set +# CONFIG_PKG_USING_SYSTEMVIEW is not set +# CONFIG_PKG_USING_SEGGER_RTT is not set +# CONFIG_PKG_USING_RTT_AUTO_EXE_CMD is not set +# CONFIG_PKG_USING_RDB is not set +# CONFIG_PKG_USING_ULOG_EASYFLASH is not set +# CONFIG_PKG_USING_LOGMGR is not set +# CONFIG_PKG_USING_ADBD is not set +# CONFIG_PKG_USING_COREMARK is not set +# CONFIG_PKG_USING_DHRYSTONE is not set +# CONFIG_PKG_USING_MEMORYPERF is not set +# CONFIG_PKG_USING_NR_MICRO_SHELL is not set +# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set +# CONFIG_PKG_USING_LUNAR_CALENDAR is not set +# CONFIG_PKG_USING_BS8116A is not set +# CONFIG_PKG_USING_GPS_RMC is not set +# CONFIG_PKG_USING_URLENCODE is not set +# CONFIG_PKG_USING_UMCN is not set +# CONFIG_PKG_USING_LWRB2RTT is not set +# CONFIG_PKG_USING_CPU_USAGE is not set +# CONFIG_PKG_USING_GBK2UTF8 is not set +# CONFIG_PKG_USING_VCONSOLE is not set +# CONFIG_PKG_USING_KDB is not set +# CONFIG_PKG_USING_WAMR is not set +# CONFIG_PKG_USING_MICRO_XRCE_DDS_CLIENT is not set +# CONFIG_PKG_USING_LWLOG is not set +# CONFIG_PKG_USING_ANV_TRACE is not set +# CONFIG_PKG_USING_ANV_MEMLEAK is not set +# CONFIG_PKG_USING_ANV_TESTSUIT is not set +# CONFIG_PKG_USING_ANV_BENCH is not set +# CONFIG_PKG_USING_DEVMEM is not set +# CONFIG_PKG_USING_REGEX is not set +# CONFIG_PKG_USING_MEM_SANDBOX is not set +# CONFIG_PKG_USING_SOLAR_TERMS is not set +# CONFIG_PKG_USING_GAN_ZHI is not set +# CONFIG_PKG_USING_FDT is not set +# CONFIG_PKG_USING_CBOX is not set +# CONFIG_PKG_USING_SNOWFLAKE is not set +# CONFIG_PKG_USING_HASH_MATCH is not set +# CONFIG_PKG_USING_ARMV7M_DWT_TOOL is not set +# CONFIG_PKG_USING_VOFA_PLUS is not set +# CONFIG_PKG_USING_ZDEBUG is not set +# CONFIG_PKG_USING_RVBACKTRACE is not set +# CONFIG_PKG_USING_HPATCHLITE is not set +# CONFIG_PKG_USING_THREAD_METRIC is not set +# CONFIG_PKG_USING_UORB is not set +# end of tools packages + +# +# system packages +# + +# +# enhanced kernel services +# +# CONFIG_PKG_USING_RT_MEMCPY_CM is not set +# CONFIG_PKG_USING_RT_KPRINTF_THREADSAFE is not set +# end of enhanced kernel services + +# CONFIG_PKG_USING_AUNITY is not set + +# +# acceleration: Assembly language or algorithmic acceleration packages +# +# CONFIG_PKG_USING_QFPLIB_M0_FULL is not set +# CONFIG_PKG_USING_QFPLIB_M0_TINY is not set +# CONFIG_PKG_USING_QFPLIB_M3 is not set +# end of acceleration: Assembly language or algorithmic acceleration packages + +# +# CMSIS: ARM Cortex-M Microcontroller Software Interface Standard +# +# CONFIG_PKG_USING_CMSIS_5 is not set +# CONFIG_PKG_USING_CMSIS_CORE is not set +# CONFIG_PKG_USING_CMSIS_NN is not set +# CONFIG_PKG_USING_CMSIS_RTOS1 is not set +# CONFIG_PKG_USING_CMSIS_RTOS2 is not set +# end of CMSIS: ARM Cortex-M Microcontroller Software Interface Standard + +# +# Micrium: Micrium software products porting for RT-Thread +# +# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set +# CONFIG_PKG_USING_UCOSII_WRAPPER is not set +# CONFIG_PKG_USING_UC_CRC is not set +# CONFIG_PKG_USING_UC_CLK is not set +# CONFIG_PKG_USING_UC_COMMON is not set +# CONFIG_PKG_USING_UC_MODBUS is not set +# end of Micrium: Micrium software products porting for RT-Thread + +# CONFIG_PKG_USING_FREERTOS_WRAPPER is not set +# CONFIG_PKG_USING_LITEOS_SDK is not set +# CONFIG_PKG_USING_TZ_DATABASE is not set +# CONFIG_PKG_USING_CAIRO is not set +# CONFIG_PKG_USING_PIXMAN is not set +# CONFIG_PKG_USING_PARTITION is not set +# CONFIG_PKG_USING_PERF_COUNTER is not set +# CONFIG_PKG_USING_FILEX is not set +# CONFIG_PKG_USING_LEVELX is not set +# CONFIG_PKG_USING_FLASHDB is not set +# CONFIG_PKG_USING_SQLITE is not set +# CONFIG_PKG_USING_RTI is not set +# CONFIG_PKG_USING_DFS_YAFFS is not set +# CONFIG_PKG_USING_LITTLEFS is not set +# CONFIG_PKG_USING_DFS_JFFS2 is not set +# CONFIG_PKG_USING_DFS_UFFS is not set +# CONFIG_PKG_USING_LWEXT4 is not set +# CONFIG_PKG_USING_THREAD_POOL is not set +# CONFIG_PKG_USING_ROBOTS is not set +# CONFIG_PKG_USING_EV is not set +# CONFIG_PKG_USING_SYSWATCH is not set +# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set +# CONFIG_PKG_USING_PLCCORE is not set +# CONFIG_PKG_USING_RAMDISK is not set +# CONFIG_PKG_USING_MININI is not set +# CONFIG_PKG_USING_QBOOT is not set +# CONFIG_PKG_USING_PPOOL is not set +# CONFIG_PKG_USING_OPENAMP is not set +# CONFIG_PKG_USING_RPMSG_LITE is not set +# CONFIG_PKG_USING_LPM is not set +# CONFIG_PKG_USING_TLSF is not set +# CONFIG_PKG_USING_EVENT_RECORDER is not set +# CONFIG_PKG_USING_ARM_2D is not set +# CONFIG_PKG_USING_MCUBOOT is not set +# CONFIG_PKG_USING_TINYUSB is not set +# CONFIG_PKG_USING_KMULTI_RTIMER is not set +# CONFIG_PKG_USING_TFDB is not set +# CONFIG_PKG_USING_QPC is not set +# CONFIG_PKG_USING_AGILE_UPGRADE is not set +# CONFIG_PKG_USING_FLASH_BLOB is not set +# CONFIG_PKG_USING_MLIBC is not set +# CONFIG_PKG_USING_TASK_MSG_BUS is not set +# CONFIG_PKG_USING_UART_FRAMEWORK is not set +# CONFIG_PKG_USING_SFDB is not set +# CONFIG_PKG_USING_RTP is not set +# CONFIG_PKG_USING_REB is not set +# CONFIG_PKG_USING_RMP is not set +# CONFIG_PKG_USING_R_RHEALSTONE is not set +# CONFIG_PKG_USING_HEARTBEAT is not set +# CONFIG_PKG_USING_MICRO_ROS_RTTHREAD_PACKAGE is not set +# CONFIG_PKG_USING_CHERRYECAT is not set +# end of system packages + +# +# peripheral libraries and drivers +# + +# +# HAL & SDK Drivers +# + +# +# STM32 HAL & SDK Drivers +# +# CONFIG_PKG_USING_STM32F0_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32F0_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32F1_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32F1_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32F2_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32F2_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32F3_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32F3_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32F4_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32F4_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32F7_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32F7_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32G0_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32G0_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32G4_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32G4_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32H5_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32H5_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32H7_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32H7_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32H7RS_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32H7RS_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32L0_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32L0_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32L4_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32L4_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32L5_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32L5_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32U5_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32U5_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32WB55_SDK is not set +# CONFIG_PKG_USING_STM32_SDIO is not set +# CONFIG_PKG_USING_STM32WL_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32WL_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32WB_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32WB_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32MP1_M4_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32MP1_M4_CMSIS_DRIVER is not set +# end of STM32 HAL & SDK Drivers + +# +# Infineon HAL Packages +# +# CONFIG_PKG_USING_INFINEON_CAT1CM0P is not set +# CONFIG_PKG_USING_INFINEON_CMSIS is not set +# CONFIG_PKG_USING_INFINEON_CORE_LIB is not set +# CONFIG_PKG_USING_INFINEON_MTB_HAL_CAT1 is not set +# CONFIG_PKG_USING_INFINEON_MTB_PDL_CAT1 is not set +# CONFIG_PKG_USING_INFINEON_RETARGET_IO is not set +# CONFIG_PKG_USING_INFINEON_CAPSENSE is not set +# CONFIG_PKG_USING_INFINEON_CSDIDAC is not set +# CONFIG_PKG_USING_INFINEON_SERIAL_FLASH is not set +# CONFIG_PKG_USING_INFINEON_USBDEV is not set +# end of Infineon HAL Packages + +# CONFIG_PKG_USING_BLUETRUM_SDK is not set +# CONFIG_PKG_USING_EMBARC_BSP is not set +# CONFIG_PKG_USING_ESP_IDF is not set + +# +# Kendryte SDK +# +# CONFIG_PKG_USING_K210_SDK is not set +# CONFIG_PKG_USING_KENDRYTE_SDK is not set +# end of Kendryte SDK + +# CONFIG_PKG_USING_NRF5X_SDK is not set +# CONFIG_PKG_USING_NRFX is not set +# CONFIG_PKG_USING_RASPBERRYPI_PICO_RP2350_SDK is not set +# CONFIG_PKG_USING_RASPBERRYPI_PICO_SDK is not set +# CONFIG_PKG_USING_MM32 is not set + +# +# WCH HAL & SDK Drivers +# +# CONFIG_PKG_USING_CH32V20x_SDK is not set +# CONFIG_PKG_USING_CH32V307_SDK is not set +# end of WCH HAL & SDK Drivers + +# +# AT32 HAL & SDK Drivers +# +# CONFIG_PKG_USING_AT32A403A_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32A403A_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32A423_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32A423_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F45x_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F45x_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F402_405_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F402_405_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F403A_407_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F403A_407_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F413_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F413_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F415_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F415_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F421_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F421_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F423_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F423_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F425_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F425_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F435_437_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F435_437_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32M412_416_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32M412_416_CMSIS_DRIVER is not set +# end of AT32 HAL & SDK Drivers + +# +# HC32 DDL Drivers +# +# CONFIG_PKG_USING_HC32F3_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_HC32F3_SERIES_DRIVER is not set +# CONFIG_PKG_USING_HC32F4_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_HC32F4_SERIES_DRIVER is not set +# end of HC32 DDL Drivers + +# +# NXP HAL & SDK Drivers +# +# CONFIG_PKG_USING_NXP_MCX_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_NXP_MCX_SERIES_DRIVER is not set +# CONFIG_PKG_USING_NXP_LPC_DRIVER is not set +# CONFIG_PKG_USING_NXP_LPC55S_DRIVER is not set +# CONFIG_PKG_USING_NXP_IMX6SX_DRIVER is not set +# CONFIG_PKG_USING_NXP_IMX6UL_DRIVER is not set +# CONFIG_PKG_USING_NXP_IMXRT_DRIVER is not set +# end of NXP HAL & SDK Drivers + +# +# NUVOTON Drivers +# +# CONFIG_PKG_USING_NUVOTON_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_NUVOTON_SERIES_DRIVER is not set +# CONFIG_PKG_USING_NUVOTON_ARM926_LIB is not set +# end of NUVOTON Drivers + +# +# GD32 Drivers +# +# CONFIG_PKG_USING_GD32_ARM_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_GD32_ARM_SERIES_DRIVER is not set +# end of GD32 Drivers + +# +# HPMicro SDK +# +# CONFIG_PKG_USING_HPM_SDK is not set +# end of HPMicro SDK +# end of HAL & SDK Drivers + +# +# sensors drivers +# +# CONFIG_PKG_USING_LSM6DSM is not set +# CONFIG_PKG_USING_LSM6DSL is not set +# CONFIG_PKG_USING_LPS22HB is not set +# CONFIG_PKG_USING_HTS221 is not set +# CONFIG_PKG_USING_LSM303AGR is not set +# CONFIG_PKG_USING_BME280 is not set +# CONFIG_PKG_USING_BME680 is not set +# CONFIG_PKG_USING_BMA400 is not set +# CONFIG_PKG_USING_BMI160_BMX160 is not set +# CONFIG_PKG_USING_SPL0601 is not set +# CONFIG_PKG_USING_MS5805 is not set +# CONFIG_PKG_USING_DA270 is not set +# CONFIG_PKG_USING_DF220 is not set +# CONFIG_PKG_USING_HSHCAL001 is not set +# CONFIG_PKG_USING_BH1750 is not set +# CONFIG_PKG_USING_MPU6XXX is not set +# CONFIG_PKG_USING_AHT10 is not set +# CONFIG_PKG_USING_AP3216C is not set +# CONFIG_PKG_USING_TSL4531 is not set +# CONFIG_PKG_USING_DS18B20 is not set +# CONFIG_PKG_USING_DHT11 is not set +# CONFIG_PKG_USING_DHTXX is not set +# CONFIG_PKG_USING_GY271 is not set +# CONFIG_PKG_USING_GP2Y10 is not set +# CONFIG_PKG_USING_SGP30 is not set +# CONFIG_PKG_USING_HDC1000 is not set +# CONFIG_PKG_USING_BMP180 is not set +# CONFIG_PKG_USING_BMP280 is not set +# CONFIG_PKG_USING_SHTC1 is not set +# CONFIG_PKG_USING_BMI088 is not set +# CONFIG_PKG_USING_HMC5883 is not set +# CONFIG_PKG_USING_MAX6675 is not set +# CONFIG_PKG_USING_MAX31855 is not set +# CONFIG_PKG_USING_TMP1075 is not set +# CONFIG_PKG_USING_SR04 is not set +# CONFIG_PKG_USING_CCS811 is not set +# CONFIG_PKG_USING_PMSXX is not set +# CONFIG_PKG_USING_RT3020 is not set +# CONFIG_PKG_USING_MLX90632 is not set +# CONFIG_PKG_USING_MLX90382 is not set +# CONFIG_PKG_USING_MLX90393 is not set +# CONFIG_PKG_USING_MLX90392 is not set +# CONFIG_PKG_USING_MLX90394 is not set +# CONFIG_PKG_USING_MLX90397 is not set +# CONFIG_PKG_USING_MS5611 is not set +# CONFIG_PKG_USING_MAX31865 is not set +# CONFIG_PKG_USING_VL53L0X is not set +# CONFIG_PKG_USING_INA260 is not set +# CONFIG_PKG_USING_MAX30102 is not set +# CONFIG_PKG_USING_INA226 is not set +# CONFIG_PKG_USING_LIS2DH12 is not set +# CONFIG_PKG_USING_HS300X is not set +# CONFIG_PKG_USING_ZMOD4410 is not set +# CONFIG_PKG_USING_ISL29035 is not set +# CONFIG_PKG_USING_MMC3680KJ is not set +# CONFIG_PKG_USING_QMP6989 is not set +# CONFIG_PKG_USING_BALANCE is not set +# CONFIG_PKG_USING_SHT2X is not set +# CONFIG_PKG_USING_SHT3X is not set +# CONFIG_PKG_USING_SHT4X is not set +# CONFIG_PKG_USING_AD7746 is not set +# CONFIG_PKG_USING_ADT74XX is not set +# CONFIG_PKG_USING_MAX17048 is not set +# CONFIG_PKG_USING_AS7341 is not set +# CONFIG_PKG_USING_CW2015 is not set +# CONFIG_PKG_USING_ICM20608 is not set +# CONFIG_PKG_USING_PAJ7620 is not set +# CONFIG_PKG_USING_STHS34PF80 is not set +# CONFIG_PKG_USING_P3T1755 is not set +# CONFIG_PKG_USING_QMI8658 is not set +# CONFIG_PKG_USING_ICM20948 is not set +# end of sensors drivers + +# +# touch drivers +# +# CONFIG_PKG_USING_GT9147 is not set +# CONFIG_PKG_USING_GT1151 is not set +# CONFIG_PKG_USING_GT917S is not set +# CONFIG_PKG_USING_GT911 is not set +# CONFIG_PKG_USING_FT6206 is not set +# CONFIG_PKG_USING_FT5426 is not set +# CONFIG_PKG_USING_FT6236 is not set +# CONFIG_PKG_USING_XPT2046_TOUCH is not set +# CONFIG_PKG_USING_CST816X is not set +# CONFIG_PKG_USING_CST812T is not set +# end of touch drivers + +# CONFIG_PKG_USING_REALTEK_AMEBA is not set +# CONFIG_PKG_USING_BUTTON is not set +# CONFIG_PKG_USING_PCF8574 is not set +# CONFIG_PKG_USING_SX12XX is not set +# CONFIG_PKG_USING_SIGNAL_LED is not set +# CONFIG_PKG_USING_LEDBLINK is not set +# CONFIG_PKG_USING_LITTLED is not set +# CONFIG_PKG_USING_LKDGUI is not set +# CONFIG_PKG_USING_INFRARED is not set +# CONFIG_PKG_USING_MULTI_INFRARED is not set +# CONFIG_PKG_USING_AGILE_BUTTON is not set +# CONFIG_PKG_USING_AGILE_LED is not set +# CONFIG_PKG_USING_AT24CXX is not set +# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set +# CONFIG_PKG_USING_PCA9685 is not set +# CONFIG_PKG_USING_ILI9341 is not set +# CONFIG_PKG_USING_I2C_TOOLS is not set +# CONFIG_PKG_USING_NRF24L01 is not set +# CONFIG_PKG_USING_RPLIDAR is not set +# CONFIG_PKG_USING_AS608 is not set +# CONFIG_PKG_USING_RC522 is not set +# CONFIG_PKG_USING_WS2812B is not set +# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set +# CONFIG_PKG_USING_MULTI_RTIMER is not set +# CONFIG_PKG_USING_MAX7219 is not set +# CONFIG_PKG_USING_BEEP is not set +# CONFIG_PKG_USING_EASYBLINK is not set +# CONFIG_PKG_USING_PMS_SERIES is not set +# CONFIG_PKG_USING_CAN_YMODEM is not set +# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set +# CONFIG_PKG_USING_QLED is not set +# CONFIG_PKG_USING_AGILE_CONSOLE is not set +# CONFIG_PKG_USING_LD3320 is not set +# CONFIG_PKG_USING_WK2124 is not set +# CONFIG_PKG_USING_LY68L6400 is not set +# CONFIG_PKG_USING_DM9051 is not set +# CONFIG_PKG_USING_SSD1306 is not set +# CONFIG_PKG_USING_QKEY is not set +# CONFIG_PKG_USING_RS485 is not set +# CONFIG_PKG_USING_RS232 is not set +# CONFIG_PKG_USING_NES is not set +# CONFIG_PKG_USING_VIRTUAL_SENSOR is not set +# CONFIG_PKG_USING_VDEVICE is not set +# CONFIG_PKG_USING_SGM706 is not set +# CONFIG_PKG_USING_RDA58XX is not set +# CONFIG_PKG_USING_LIBNFC is not set +# CONFIG_PKG_USING_MFOC is not set +# CONFIG_PKG_USING_TMC51XX is not set +# CONFIG_PKG_USING_TCA9534 is not set +# CONFIG_PKG_USING_KOBUKI is not set +# CONFIG_PKG_USING_ROSSERIAL is not set +# CONFIG_PKG_USING_MICRO_ROS is not set +# CONFIG_PKG_USING_MCP23008 is not set +# CONFIG_PKG_USING_MISAKA_AT24CXX is not set +# CONFIG_PKG_USING_MISAKA_RGB_BLING is not set +# CONFIG_PKG_USING_LORA_MODEM_DRIVER is not set +# CONFIG_PKG_USING_SOFT_SERIAL is not set +# CONFIG_PKG_USING_MB85RS16 is not set +# CONFIG_PKG_USING_RFM300 is not set +# CONFIG_PKG_USING_IO_INPUT_FILTER is not set +# CONFIG_PKG_USING_LRF_NV7LIDAR is not set +# CONFIG_PKG_USING_AIP650 is not set +# CONFIG_PKG_USING_FINGERPRINT is not set +# CONFIG_PKG_USING_BT_ECB02C is not set +# CONFIG_PKG_USING_UAT is not set +# CONFIG_PKG_USING_ST7789 is not set +# CONFIG_PKG_USING_VS1003 is not set +# CONFIG_PKG_USING_X9555 is not set +# CONFIG_PKG_USING_SYSTEM_RUN_LED is not set +# CONFIG_PKG_USING_BT_MX01 is not set +# CONFIG_PKG_USING_RGPOWER is not set +# CONFIG_PKG_USING_BT_MX02 is not set +# CONFIG_PKG_USING_GC9A01 is not set +# CONFIG_PKG_USING_IK485 is not set +# CONFIG_PKG_USING_SERVO is not set +# CONFIG_PKG_USING_SEAN_WS2812B is not set +# CONFIG_PKG_USING_IC74HC165 is not set +# CONFIG_PKG_USING_IST8310 is not set +# CONFIG_PKG_USING_ST7789_SPI is not set +# CONFIG_PKG_USING_SPI_TOOLS is not set +# end of peripheral libraries and drivers + +# +# AI packages +# +# CONFIG_PKG_USING_LIBANN is not set +# CONFIG_PKG_USING_NNOM is not set +# CONFIG_PKG_USING_ONNX_BACKEND is not set +# CONFIG_PKG_USING_ONNX_PARSER is not set +# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set +# CONFIG_PKG_USING_ELAPACK is not set +# CONFIG_PKG_USING_ULAPACK is not set +# CONFIG_PKG_USING_QUEST is not set +# CONFIG_PKG_USING_NAXOS is not set +# CONFIG_PKG_USING_R_TINYMAIX is not set +# CONFIG_PKG_USING_LLMCHAT is not set +# end of AI packages + +# +# Signal Processing and Control Algorithm Packages +# +# CONFIG_PKG_USING_APID is not set +# CONFIG_PKG_USING_FIRE_PID_CURVE is not set +# CONFIG_PKG_USING_QPID is not set +# CONFIG_PKG_USING_UKAL is not set +# CONFIG_PKG_USING_DIGITALCTRL is not set +# CONFIG_PKG_USING_KISSFFT is not set +# CONFIG_PKG_USING_CMSIS_DSP is not set +# end of Signal Processing and Control Algorithm Packages + +# +# miscellaneous packages +# + +# +# project laboratory +# +# end of project laboratory + +# +# samples: kernel and components samples +# +# CONFIG_PKG_USING_KERNEL_SAMPLES is not set +# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set +# CONFIG_PKG_USING_NETWORK_SAMPLES is not set +# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set +# end of samples: kernel and components samples + +# +# entertainment: terminal games and other interesting software packages +# +# CONFIG_PKG_USING_CMATRIX is not set +# CONFIG_PKG_USING_SL is not set +# CONFIG_PKG_USING_CAL is not set +# CONFIG_PKG_USING_ACLOCK is not set +# CONFIG_PKG_USING_THREES is not set +# CONFIG_PKG_USING_2048 is not set +# CONFIG_PKG_USING_SNAKE is not set +# CONFIG_PKG_USING_TETRIS is not set +# CONFIG_PKG_USING_DONUT is not set +# CONFIG_PKG_USING_COWSAY is not set +# CONFIG_PKG_USING_MORSE is not set +# CONFIG_PKG_USING_TINYSQUARE is not set +# end of entertainment: terminal games and other interesting software packages + +# CONFIG_PKG_USING_LIBCSV is not set +# CONFIG_PKG_USING_OPTPARSE is not set +# CONFIG_PKG_USING_FASTLZ is not set +# CONFIG_PKG_USING_MINILZO is not set +# CONFIG_PKG_USING_QUICKLZ is not set +# CONFIG_PKG_USING_LZMA is not set +# CONFIG_PKG_USING_RALARAM is not set +# CONFIG_PKG_USING_MULTIBUTTON is not set +# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set +# CONFIG_PKG_USING_CANFESTIVAL is not set +# CONFIG_PKG_USING_ZLIB is not set +# CONFIG_PKG_USING_MINIZIP is not set +# CONFIG_PKG_USING_HEATSHRINK is not set +# CONFIG_PKG_USING_DSTR is not set +# CONFIG_PKG_USING_TINYFRAME is not set +# CONFIG_PKG_USING_KENDRYTE_DEMO is not set +# CONFIG_PKG_USING_UPACKER is not set +# CONFIG_PKG_USING_UPARAM is not set +# CONFIG_PKG_USING_HELLO is not set +# CONFIG_PKG_USING_VI is not set +# CONFIG_PKG_USING_KI is not set +# CONFIG_PKG_USING_ARMv7M_DWT is not set +# CONFIG_PKG_USING_CRCLIB is not set +# CONFIG_PKG_USING_LIBCRC is not set +# CONFIG_PKG_USING_LWGPS is not set +# CONFIG_PKG_USING_STATE_MACHINE is not set +# CONFIG_PKG_USING_DESIGN_PATTERN is not set +# CONFIG_PKG_USING_CONTROLLER is not set +# CONFIG_PKG_USING_PHASE_LOCKED_LOOP is not set +# CONFIG_PKG_USING_MFBD is not set +# CONFIG_PKG_USING_SLCAN2RTT is not set +# CONFIG_PKG_USING_SOEM is not set +# CONFIG_PKG_USING_QPARAM is not set +# CONFIG_PKG_USING_CorevMCU_CLI is not set +# CONFIG_PKG_USING_DRMP is not set +# end of miscellaneous packages + +# +# Arduino libraries +# +# CONFIG_PKG_USING_RTDUINO is not set + +# +# Projects and Demos +# +# CONFIG_PKG_USING_ARDUINO_MSGQ_C_CPP_DEMO is not set +# CONFIG_PKG_USING_ARDUINO_SKETCH_LOADER_DEMO is not set +# CONFIG_PKG_USING_ARDUINO_ULTRASOUND_RADAR is not set +# CONFIG_PKG_USING_ARDUINO_RTDUINO_SENSORFUSION_SHIELD is not set +# CONFIG_PKG_USING_ARDUINO_NINEINONE_SENSOR_SHIELD is not set +# CONFIG_PKG_USING_ARDUINO_SENSOR_KIT is not set +# CONFIG_PKG_USING_ARDUINO_MATLAB_SUPPORT is not set +# end of Projects and Demos + +# +# Sensors +# +# CONFIG_PKG_USING_ARDUINO_SENSOR_DEVICE_DRIVERS is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSOR is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSORLAB is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL375 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L0X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L1X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL6180X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31855 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31865 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31856 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX6675 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90614 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM9DS1 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AHTX0 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM9DS0 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP280 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADT7410 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP085 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BME680 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP9808 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4728 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA219 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LTR390 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL345 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DHT is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP9600 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM6DS is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO055 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX1704X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMC56X3 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90393 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90395 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ICM20X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DPS310 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTS221 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHT4X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHT31 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL343 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BME280 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS726X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AMG88XX is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AM2320 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AM2315 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LTR329_LTR303 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP085_UNIFIED is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP183 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP183_UNIFIED is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP3XX is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MS8607 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3MDL is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90640 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMA8451 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MSA301 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL115A2 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X_RVC is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS2MDL is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM303DLH_MAG is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LC709203F is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_CAP1188 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_CCS811 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_NAU7802 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS331 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LPS2X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LPS35HW is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM303_ACCEL is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3DH is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8591 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL3115A2 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPR121 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPRLS is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPU6050 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCT2075 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PM25AQI is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_EMC2101 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_FXAS21002C is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SCD30 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_FXOS8700 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HMC5883_UNIFIED is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SGP30 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP006 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TLA202X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TCS34725 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI7021 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI1145 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SGP40 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHTC3 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HDC1000 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU21DF is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS7341 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU31D is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA260 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP007_LIBRARY is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_L3GD20 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP117 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSC2007 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSL2561 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSL2591_LIBRARY is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VCNL4040 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML6070 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML6075 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML7700 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LIS3DHTR is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_DHT is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_ADXL335 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_ADXL345 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BME280 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BMP280 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_H3LIS331DL is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_MMA7660 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_TSL2561 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_PAJ7620 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_VL53L0X is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_ITG3200 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_SHT31 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HP20X is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_DRV2605L is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BBM150 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HMC5883L is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LSM303DLH is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_TCS3414CS is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_MP503 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BMP085 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HIGHTEMP is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_VEML6070 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_SI1145 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_SHT35 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_AT42QT1070 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LSM6DS3 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HDC1000 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HM3301 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_MCP9600 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LTC2941 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LDC1612 is not set +# CONFIG_PKG_USING_ARDUINO_CAPACITIVESENSOR is not set +# CONFIG_PKG_USING_ARDUINO_JARZEBSKI_MPU6050 is not set +# end of Sensors + +# +# Display +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_GFX_LIBRARY is not set +# CONFIG_PKG_USING_ARDUINO_U8G2 is not set +# CONFIG_PKG_USING_ARDUINO_TFT_ESPI is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ST7735 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SSD1306 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ILI9341 is not set +# CONFIG_PKG_USING_SEEED_TM1637 is not set +# end of Display + +# +# Timing +# +# CONFIG_PKG_USING_ARDUINO_RTCLIB is not set +# CONFIG_PKG_USING_ARDUINO_MSTIMER2 is not set +# CONFIG_PKG_USING_ARDUINO_TICKER is not set +# CONFIG_PKG_USING_ARDUINO_TASKSCHEDULER is not set +# end of Timing + +# +# Data Processing +# +# CONFIG_PKG_USING_ARDUINO_KALMANFILTER is not set +# CONFIG_PKG_USING_ARDUINO_ARDUINOJSON is not set +# CONFIG_PKG_USING_ARDUINO_TENSORFLOW_LITE_MICRO is not set +# CONFIG_PKG_USING_ARDUINO_RUNNINGMEDIAN is not set +# end of Data Processing + +# +# Data Storage +# + +# +# Communication +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PN532 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI4713 is not set +# end of Communication + +# +# Device Control +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8574 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCA9685 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TPA2016 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DRV2605 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS1841 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS3502 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_PCF85063TP is not set +# end of Device Control + +# +# Other +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MFRC630 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI5351 is not set +# end of Other + +# +# Signal IO +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BUSIO is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TCA8418 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP23017 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADS1X15 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AW9523 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP3008 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4725 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BD3491FS is not set +# end of Signal IO + +# +# Uncategorized +# +# end of Arduino libraries +# end of RT-Thread online packages + +CONFIG_SOC_FAMILY_RENESAS_RA=y +CONFIG_SOC_SERIES_R7KA8P1=y + +# +# Hardware Drivers Config +# + +# +# Onboard Peripheral Drivers +# +# CONFIG_BSP_START_SECONDARY_CORE is not set +# CONFIG_BSP_USING_RPMSG is not set +# CONFIG_BSP_USING_FILESYSTEM is not set +# CONFIG_BSP_USING_IST8310 is not set +# CONFIG_BSP_USING_BMI088 is not set +# CONFIG_BSP_USING_LVGL is not set +# end of Onboard Peripheral Drivers + +# +# On-chip Peripheral Drivers +# +CONFIG_BSP_USING_GPIO=y +# CONFIG_BSP_USING_ONCHIP_FLASH is not set +# CONFIG_BSP_USING_WDT is not set +# CONFIG_BSP_USING_ONCHIP_RTC is not set +CONFIG_BSP_USING_UART=y +# CONFIG_BSP_USING_UART0 is not set +# CONFIG_BSP_USING_UART5 is not set +# CONFIG_BSP_USING_UART6 is not set +CONFIG_BSP_USING_UART8=y +CONFIG_BSP_UART8_RX_BUFSIZE=256 +CONFIG_BSP_UART8_TX_BUFSIZE=0 +# CONFIG_BSP_USING_UART9 is not set +# CONFIG_BSP_USING_ADC is not set +# CONFIG_BSP_USING_DAC is not set +# CONFIG_BSP_USING_SCI is not set +# CONFIG_BSP_USING_SPI is not set +# CONFIG_BSP_USING_HW_I2C is not set +# CONFIG_BSP_USING_SOFT_I2C is not set +# CONFIG_BSP_USING_SDHI is not set +# CONFIG_BSP_USING_TIM is not set +# CONFIG_BSP_USING_PWM is not set +# CONFIG_BSP_USING_CANFD is not set +# CONFIG_BSP_USING_RS485 is not set +# CONFIG_BSP_USING_OSPI_FLASH is not set +# CONFIG_BSP_USING_OSPI_RAM is not set +# CONFIG_BSP_USING_RA8P1_USB is not set +# CONFIG_BSP_USING_ETH is not set +# end of On-chip Peripheral Drivers + +# +# Board extended module Drivers +# +# CONFIG_BSP_USING_MIPI_CSI_CAMERA is not set +# CONFIG_BSP_USING_CEU_CAMERA is not set +# CONFIG_BSP_USING_LCD is not set +# end of Board extended module Drivers +# end of Hardware Drivers Config diff --git a/bsp/renesas/ra8p1-titan-board/.cproject b/bsp/renesas/ra8p1-titan-board/.cproject new file mode 100644 index 00000000000..eb0118980be --- /dev/null +++ b/bsp/renesas/ra8p1-titan-board/.cproject @@ -0,0 +1,266 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/bsp/renesas/ra8p1-titan-board/.gitignore b/bsp/renesas/ra8p1-titan-board/.gitignore new file mode 100644 index 00000000000..38515c8a9c8 --- /dev/null +++ b/bsp/renesas/ra8p1-titan-board/.gitignore @@ -0,0 +1,26 @@ +/RTE +/Listings +/Objects +/Debug +/build +/makefile.targets +/rtconfig.pyc +/libraries +/rt-thread +/project.custom_argvars +/.vscode +/__pycache +/settings +/rtconfig_preinc.h +/bsp_linker_info.h +/fsp_gen.ld +/memory_regions.ld +/cmake +/.api_xml +/.clangd +/.secure_azone +/.secure_rzone +/.secure_xml +/ra_cfg.txt +/packages/pkgs.json +/packages/pkgs_error.json \ No newline at end of file diff --git a/bsp/renesas/ra8p1-titan-board/.project b/bsp/renesas/ra8p1-titan-board/.project new file mode 100644 index 00000000000..ce8f8e12f7c --- /dev/null +++ b/bsp/renesas/ra8p1-titan-board/.project @@ -0,0 +1,25 @@ + + + project + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + org.eclipse.cdt.core.cnature + org.rt-thread.studio.rttnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + diff --git a/bsp/renesas/ra8p1-titan-board/.settings/.rtmenus b/bsp/renesas/ra8p1-titan-board/.settings/.rtmenus new file mode 100644 index 0000000000000000000000000000000000000000..dc35e17f38c814809d61173a3578663ba2dfff15 GIT binary patch literal 1951024 zcmV(hK={9+?^jxgT`+Y&hC1!9D#_W0%u81GUn%5}@Qz{LOI;IyA8%h(8w+_SHBPd@ zDq$xj6ua8CCyf-%&v}W}2#Yx)3Nw>FqJnkm)AA5Dp8hC54|A|1!#!`tzmJxP;j7U_87+IEc(&4M1zERq611G6+coEa2mPZVTa=xI?n6RXMDONOO9vO;Yj; zWL>8W0a$lnp;uzfjE%3#Wp%OblB?^Vj+l;UeGgRQxK;IC)LI-)%)+uC9lg2s)dO;CdUCc-d7bD`UsPquUxrPst)!SP3 zwIlmJT&OkX6WM15<>o{G3*o7Fn(+8?BTtI=FzkUffdHZMCC@7$at$i(=H_;W`5z?M zEG`-6U(jT4yQz^ehR1kwx#cjp&p8=}$P|h^L~#|)AWBt!abc@Zax=7u2=Xw;h{bnk zA|Amj0Ktm@!TLFd-M#ZOzv0nyl+O$3avpgwDeHEO1LhpDHqs_80~;F@1-gUDr|2Wk zukB_*CuASHpk%F*AUI{}%4z?`!y{dtjG zP1HBZumIZ*eRycmZ^m_C@by)rk^X=kqkBJbHn=`HTw2{UKOf(J|A=*#f4pb+990=Y#U`e@R$S`-2+ zsngtM3qf+U&S=5|bdz9im1U7q1F827eC z!?DV*(Tv{<@2^l=@}^>Wz%H{K+?>~GF#30{xtw?zx<$aYTtb~Me5E#EN8>elNfBTg z=gjRuZEdF=mQUV}rYh@e0nSV1Qv7wTxOPzp%om7@Um>uA9x^DN(ipw;vzwfw(&=L9 zD(x+T-R+tx%w_p$o^93NI!d%BgDSIQwwtLm2(Ukvx{Oit?5Y!}OblNQR@%|3sT(W{ zU|w2paa~2)r~>^Mfq7R`cR;9aK!Dnm4k|EE8~Rs&Tu4)()UVqc(PVzK1~V#aSIUk7 z^=zFvu_Lm7;d!*;sZCo-YFHR>9m1@T{KB1Lm5PW2*45tgL6lH>vB7j!}g*7z}xJdn9SM$uGT=l z??3KvPXa2};>JZ~b$AS)t6&mvafi9elwF7)6dEU}c$KZ$%%pFl9X% zR10l?#bICCLEKcmK2-MY8tF=e^^sx7%tk^5m?!z|ehO@_1HHp(FV|T9 zWs{MhI#7bu>AiD%^a;S>gY#z{7WzF2i4lEo4pL0E)`h$ksqPJh(E2=M?Pi8bNJ=bF z`mMnq=9#=spE|@c+7vZD{;YT{Oxl{3Bt%H{pTr=L(@@Md%2(vVPsy!!cDh9!O;U3U z;D&V}%`A^_GP#O$>sd-IVr=`!n`&Zi|9r}Jve+t(oRNr`{x8f~Y?k4GR$}{MewZK> zCK1iq9VpYC)|LK1;HBuKI5nX9jlT!_<++5FTdu0`5#OL(J8OwAGUILe|1}ePQ!EF= z_dY$i7DuHBObgJzIRjw)Cm@Sur(u1`M2!|9|NU9&PWY<+808P*LHB}LdPz{XJhp8_ z;?&GDbr7>-OWC^W!Z05a5aollvn?~BoKGN0{rYOherYChbk+uoK&L2^V(E-mUwED7 z1Vc(8hwpHAaC++@wUiTuMzy!Z@puq`PvtBCUSf3r21C4cBE&nE11p(=0wOx=&+U|$ z0(ShBi@Bi-=vWpjBKYel9X74;eusaB7A-sUGbdA%7hF1xAN|Q*bF1-e<6xMvFjDq4q30I$0sT_ zs5Ixm{I(ClP#mKiHDv)wmKiWDA$0Nzz4e=(wU@KC z?v%Lzc`YyjM1Va=0Is5y;W}00;pH5tCp|b5Ff?9PL#G*tvocZF7tGtx3hQp)v{hmw znqUyS?mC~&lY$E-Keu$i+BoVZN&rG^fUAEa|CfMB8ntWrWIcFuwHEl!Kc1nKyf~V= z@HKX$e^(9=x}KdCdQL{vLk@t}?a02AWw%cAx9jc@3(+z{H{&b?C}- z{hqBo7sUhxS8T6V0K@)dwll;Mvh^)sTwD7RI96({%N_3k^+A@Ls1QSif7Zu=Wj(h{zL>F&02t5ATNIzFCu%CU4T4uPzuZ_ zYlriPK+X*J)TkKL?-0K-<@l&j&g^*CKiT=RgfM-scvfI^&TDL(ctmDErn>h?(`Mk} zW!`#Y=fCU5u7znnvZcT``pIc+wyxl~*DlTKlA33ua%hZo)F6X@I4rxt5F=~YG~f2; z6Lae2HV#0`;m((`qHvca_ps0S$`JO`?z_qZNFnG-9p3()YCrS*8(TDym`<0}5ZDW8 z1VlZYug7-QH4^DW!7k+Fq2f4~mXcRu$nRRU-;bE56P}J;;81PXj{c!F_yoOnzG2k< z6JZ7U9D-%RyrgFIGczfCA3w>#Yjz2Q?PGgYAb>)&xE)|PC0lne>AT$R%!i#MP50Wk6u+Ikq_6qsCKgjX%sG)AvEMG z#4C=8KE$Ju<7YLk3Ymu?CAf#BWLP;X(K*5CW|bsr00*Ypb{MJeV=cATcZZxzYnONN z&fJjcSgdd$8M8EmK(62r_-Cg>WS!ppUdlVJjl3k-g5v_NN@5ym;~{=MXi%FS^F-bC z7<=RcHfwhpLv|xw`**MESz#b1Dq|iCjq%dDWf~$&A+{y$PQi%mm131?i|>U8{ZMyI z?OWEmltf*aSVU{qnrNsX&!kHi$&m}N%`+{!Uk^(L$ut_kno?j_RjZMT?X*8dF;O&4 zwxrB=Z?|-f% z`P=7tR3Z_Jik%vl7<^LCK1bHc`cqOg66tj}&z@d|)*`i&bEHdXx~m-Ai=huVAODlV zv8HxVM;IM%sa#nH@8&{H!?*sSV5ECaSsZ8V`mweCZS zu>K!_KPuPwEe(c~RV||c@U?g>?bw}VOtVo(UA)#78))ddf(gw5U)72cdg=3ILEyeB zBNPzF!mr7La?3zX4*Ze?5&yGA|L*i3Id+a=k#Exz7t5TF{VXZ3Q}d=5Q{h(=Ss$+& zUq?MSR$-DzXIgCL(x|yjwR*P~;{k{X73w{hSI$gybf^mV#>~83EbZV_ien=Y@$gNU z&&Is{X3ES!6HOZPk2Kt3+-$mLSnkX3!CIiVuI!Yxt^jJ~=~_(EmtJb=1tuto;>zUn z<8J$l!80>FZX!*9pw%uh$!`WypwgJ&eH^9`uF4)STi|&j8aiLoAobjU_h4RX3GCH=FpH&}pFXZ3lT$W{Yq^{hG4{ z_KI@;#d<4j3=kxVfFb~7nYYVNin6xtd?vQeG_0i$(3P_FdE1o1;?2TT#%C&s%zT$a z3c!mMy9biQC$Rw_TGH;I-xBI{9x-p4OYQQ>84ewqc&7}OvNXUbO&dvxL@~=%ZibAu zQ?R@e^Zs{J^ZUo|RaCzQu)&pP^KHWTtf_1Rvn7vBkh1fu1UMX zy28e>);xaTAYIsjEXXb<|@lTD7leoL8AlPldt0X8kC057m_J5_qLWZ zGYPLWnTr=0o~C8Z&u@~Hfvdrs_SaCJf_?ZN-%f%o2oPYd!J8bp=p3fOqt^xwb5zwV zd%l!x3{R25n4*DWS5+eerK3WW7xKWZ8D&|ZBPDY~!_6?QtfT;u*Mapjw>=Wv!n7Vn zf;YAwbqdJO<6v*h;}_QO$E{48`cD0Vc^V20Y1LT9rbT%d!2K6&SHxsPqk}un;DpRT zBX}Fu$FK{s_uB?1!bk&$(WJaxyHmc7hjd|5RR~#}es-)K)zVGQO?y9lnLdh*(O03l zNl*FG;;&N2tLNC55q_BGi!b_aLDK=Xy`@bjdwYNe_#JO}jL>BgfSXN&!x$UPSCeoF zfF`|oF2Q2JEXu-35KeY%Mu4h)=h`SGdXMc^yvV^Nl-TZK7vb4|%XfcEU`YKrBtduF zz`^Ifb9dZdNyc06`1)L}OAFN*tN2s`GHZ|gf4Uu`I!eL3@}`e)@O?)Li~*Mm32vIi zB@{U5ZVV*uWR|@fQiZnhoUvC}i|&nDJl?n~MYK9b2|VlbFfPi-+~tXPtdB^cM=%Yz z335b-rTftKGc&&JDx_HLCZ#NJ>E)(_psN&&iNrFh+?LDM3}xWKo&?iA}aEX z#vSWpfe=KZ7AFjvvYG6m-Bdgp1(8zo!FPzV$g?E z(`fTS9|A6a`(vG-ZMosGb@4cgpg%W1UdQ`0j~IswcFaQ`JuF7v8m`>E31b_y(-O@2 zw7*_OTHLkLIF?HPZA9+tMuwu&xO!YAPkZfxIl)ojuw!GzWhSOo#Oq=tnal)>b4V7I zU_k(=uy<*Z(3t%p>cE_FM&5iQzxvS_>9}hC5->sOauFd@>-CrjnzS?S$m4bx-GQ?u7v1j4 z%lFv^q;MosD>@U`+UQ&u1t9U=RtP2C#ed`~;#fpx-u<&#jh`<-8c50;^jK|l%6w*u z5P&AHh;e`$IpdxBJPFOkakc6uYWxgiRA!EVeA=i!_*jL1$-ce4pRyGFxD|j5sb)N$ z{77mWiD6OcxRw7Ya%KM6soJRK6st#OIV?+WzHCO;=BS9E_c#&0RTNyt^o}S=n98#b z=%%GBwt3+6mX^o7Vq@H$xVaZJZQJt$e7o9L!u~@HPxi&5L%7 z4rS@zbLrj3r0~K_l)drNjq3eU?*@OUP4krB0%44 zGVr@-#d-G{x8OFyZpFeO0zPJ&NPoUypkGBQ-Yq}DFs#8ThG8@Tp=NfBKU2q@(JteG z@}@_~HGN__8+Ryu9D@V&xWeX;&kA4H_noDPy@qgpxf=|8FLzfPYQQoa$_O?hpRUe( znUyE?{iiJYu6jVTpC=Y>ji=6m3pXpOr(PJvv8e7rON!PD>@xLixx7`!xkej9r5ZFV zCW`3|86Mv^apc^oP)mtPRA(!)9Fe&{W0n?g%8aW|YrxoA#+I!5on`NA&CnSy9l$$1 zK?}0-7S5oJG!n;zcZ1MEC=9hbli`jR5=lW7O|eI99ar%?lv0vn?us&TnjqJ>Jc1Jo z5F!sGBr=cZ#;n+9v!B#S?9iN|`lS5A#hHk-3|?wQAPZQh_NFFwL)5wadUI%*zW9kM|Oqg9tVqFq?D~T$W$386jx{;_a zC?y;Em%N&Zpz+P;uXBj;!yD&>MC>z>MHx9agV z7L`w{x7)l)0qL!RjW=JvZxF`Y&}EXya~9nuY;LPtMURkzIsj5uZs_6I6T8r|OYpDQS6oO1O_E z(RI433MD}X4s=OYq4tG_7!ZL>3~0NPiAdY)N2*gWWx7;<)x34X2Q|+i`a+ly~AOE7$b1D0Tt2XsmSVy12c@bcB zem2VY*Ouh{T)1HV$ZkFiV@!OY!q}*O-g2bdA4|u&p;{-5(a+ktKb_57Qjza~Ip5?DZVhk=rv2UUSdR@T8+2`#2QTt$FgeZT@ zw);H=4*%gnnw~?1LZP#v3)eU;fh4LIDosIzRGDt~EV0rTc2@{{r?ng-N2HiDWr2Lp zsE`%#o?H=9h^Yok2zUUiQ7b1JTx%cCl(^SP%&X)WX*88dHIfcN5c)o9HicHWb%a6W z?3vQX4QH>kCrPFdqNjEoA}JLp^?h^svHBNwf#cV;kRWa5AL!Gps5tq#moih4>q@@Q!Lvhqfx94#JV^UWeV^E)9hQ_lP@H81H`)e zo>4K3vTKk%TUFF+GE2g3uTj>d>pJ@}&u9h~dcPk`WT;x$L@ABhOp7k62T}&sgUx6) zu`};WJ|R>=a40ms2`q2{(fR_TcNs0QU~b%t@N!2T*8KVMYMKSPyA~Q`SZj(mG6I;M zZ%r??31tMQWKMq?ntU_~^XL0|QvG8|%y+MU7QmzE4inY@A4mr>d^p@8TRhZ&XM8aL z|7Axmm}S?)Ik`%N0Tr}$U{XE%r7peQ-oLh-z6OAAw0k`1T`}F=zMtOB30>{`ee?o% z1pw>!8oVkln{1D%#2j`RX3j{%DS~tK2nj5~;f3MTu+0z&rSenHAA(Ni202Gg0E zZWaj_Z1b^Z-x|OFk1}F=xGY)A&EAfne!gz)?4iGjg^cU2Uk@);<`E+CLh7<;wDk-m&PYy<6W z?C5@b?%GoC=c(aJi8o3+3QFb4oblC8O)Ag2^&A{1_XM4E>FG!WuHu%;EO?q!r`#sf zIGGWxuR`eZa}RpM+q4Mc@2$1}1|uX0-0}OPyTBI&#G_Z1o4A_0U-X1lT0j{LIq*K7 z#-#q%ms_YvejBVJzyt(6;$A{g?I0rD+UW~EP%kBH>B#ZlQdAX-K)kv@gD_BsBvkv% z27Qq!b2OQV>zgRt;yGRJvN&w4e1IVeC;(vtL3>DTp{t5%t7_e!QUN&B@?gV-+%>ow z9Z9QKCQ+Ys2uFNVDtt8^=$2zv!yF3tuyMtmS!D&l5FYmiY#7_gXhr& zFQ4L9F<(p4N-FLcIM38TeYBLT}Jx_O zX)!jVw{iQpgTfiz{!rmfk1PTJonufb(nYCu%xf+>55YH~UP2uTcHu#=6larFLxlX( zD(AMO`?3ll&^Pfhyf4^@T@?$u*45My&ugSVXc;Db|84*7LXFYYDyD!js``{xptb20 zYl$YNkHgTDLH>6>VBr%HXvp|HSUE$ZJ&h;_;K50>r&_Bl&{QT=9A(^Q&m-|9-nj+L z^mh$;H_>{ZIosi~52~>VsFvuZ#Ol@09A)nG;P-IV$c1N#0>ahk)-Cr@xnNdmNUMUa z0xw$E&)z{g>?evS&Td)Hb-A3sNPv-P-RR)}%LG1MseU6wkA z!V!z*$DS#(LHE6oEUb)ow@MTcS1mD$GEr;Fv6Y_Y@*+E!q4oc0yUG|bB+Q03xp{Iu z6kR(+=a$Lx;yQ=lOrof(oh!Tpg}ie)@2O~bRUEc?fuaS~JPb6Mf&S?0Ns#ECS9@j&6VYuXVUil`RPmbZt7;l0iFK+^p?Vw zrZ@eSd`ax{BRxL1Ys&&;#)5f{^_4H#xE8exP$XjNmI!~Ia(c$v_!iH`*8 z^JkcwR6_X}Y7f>q#PLPH?mD(>!CN4v1DZQIPt|BMCJW38SfgoKv8n9rYm?v*tUS&= zP`3Lei^-u0HKvFLjc5iPOa(}Gh#av0@@O~3S<7B5R4L)<=9D4_K4uDFCF7`Jvqy#X zVl^!7htnzDeJ(BJ4$<(Ea}Qq>;HpN?_oB|*Dz_rJcp!tp=46z7@wBMg_enaoMoM4@ znWlwwS8jfAe37oPvT&Q;wZ{_929JLZ_c$59RZ+WsXI^>x>BJc+A}SfONpBJb-O2W) zZm1KSqe?P0P*+qJi+huwwYU&GRCf(gQRJCzzT}HJiXVscBhTI zAzyzpfC$DhTEdTPAX12NfyvzjQe?T-T8{F(`ygCx)#>L+*nW3sHHu;WIpZ1&^F-0) z@?CccRG>jP;s+`g27`>rxZfO(a&0d_M}ycfE*CBp{(?{;6S8zK%$!((qOv6vm?N4T zrSP5qFh*^P0&*II|g(7IGPFiRP=j_i= zD$SVv-~z$e(9cqYU8SJ`$lYm9XV+Dl^*qoA!M@>I+&zHCslTSCw)iu&3sxBdF)+e6BE{&5m4>E}xz=bQiV43GjlSlQdJ6<(rhX+95L8 zs#%6_;$dA6S0MNArqP^}Otl)<@jx+KGXdla2SI$oQ&ktFh!aJFV_!}8Vm24HE&io| zLAf)6Y$oe)8d zvzr;e-T0^?VMn*xFq}2TmJm=H}ALOR&aIa*oppCTqrrp80%g zK=-mN8-}&|MB|K%?0GmVm9qnOOu|T2P4|WQZWMd17F)LWD?dU zJ7{UOQNL3vMI{P4muG7?id~MhKfZ4(>gorUAA^}Pzt2RKU684-IRbY!#;(dEmOSN8 z5ycC&O?n22Sr6f`oCi@?_pnu!5@in_!dWsdh1|8Ov@Y_ zMwB6R;mN`P4CG#MX&W*S)JpqnuSGMiCMb0~*@2JFLzD@&5Lpf)$PtKt6I7HB)39B2 z$j0OoL2@&R>UIZj;kvGVnW2}F8gz5zsBp=~{+$Cf>LnUT#F-59*RXFQ=Np_%Fg1YF zen$0=j$d3NNtEM6g1|!0s52lF3S1qCN@h-B`tM1^XIqI6-Urd76w*lk#+j@v)&bYz zt{cLMx(KgS?{}v#B>EZ&2g2aTv0YKw&Q{s(*+jUUfi16!%lzds^}zP1N(W8vD9Rqo zL#g!OwJ~;XreCVHVs_9SQG(PXYh(B^a<5eFtKdgfsp^)R)waa73T^%3b2b*YPxQ8c zsX{K#P#b|b!-zVqUqAnK{oGRuu{&JpaVAJkr;Sg_jyneF@D?B}AtBQJ<@hKGs?Wv> zCWJpc<9n#5uv2pkc}JJPdw1GzukRFlFHfH!avwXNHuUj|NN1WSg#S+_GY=O9QfMYW zPKmei`;Q3RB;Y=#NBsc6qjSSS`E)DJM7W(=U?=KL2r;JGjJGCLNtxtzmEZ&xve zi{Dt8jmG%kvXfXajd>rSJP{zbtSRBAC`}6=tjaxn)G%QRxdfTvDjyPDQddp|+iXc$FKQ=tDr+feT~Z6Lpaw;YYrIXg@_Uc&1D zc`+3XvN7h^!3HJkfE+>GpAk<`pdIPj<++$bIT(DBW8x-ZR*`ONjzQiduH!9Sm34@{u&KmC8J?~osv;7YH zggFvLhS+KHU3rSEINtOt66^E+I%fNV$){tE?!7V(yW z_>}hjZJA8)0N&aYz-x^I4cwrQXzhRIiKFL3Yrv{yJO7Rh!RWxTBlzR5`4A+@J9rz> z$T?1>84M>4Ibm0xL<#eu>D+K-S*hPCfs|bU8VxB#ZavpA*H)jHrr?Q0`g_!Q$i@p^ z7ZaE!2i*RLmDT$Q+S7z;+=PwwrYfY*lBQIAe5t>rC^Ob?%!sa>E>S<(K0^oGA!<$w zQJ%uJ{aJbhpv}l=Ns`6E4oj-`SAGb?=ti!`G9BXYKDRcrBJj&xkGy<&)DkUAAVQq2 z4s+AubCRsw$gtNhO2=DidHd!iQ$t_mPL93TNCE`)%}`{itT6Rq~%brI^ig5dBZqO ze~7tg77|7x5-Zt$$KFC8=|w-$Jo(^Eh6kgE*~qoO2oZcW)bd+j?pl`gd15aZ8r33< zQV(T47|b(v7K>MuPBRj+*2>a8V?|l?*}B3g$gFbu@6_7^c&M$TW_B!lRwn)Y5Wtz` zGs1hTn!yD;FTLW<2&V)co4&CbG)u+@a{hkw*2Tx0E}iHuaPSBtALRmnc}+SR>02ev zCE>F&biNW9DF287ER^%*62UmAh0%YF@R9EM;IB@JVvGaW=UaRA=9+=rUd7^zi75mkq`yL)JN+ zMCb97G0|{*s9gLTmY=U1f+{n)LV@1@MwzT!VvJvZQ%5pzb6839_t#b=RWHM_d#a5n zVfI!5#qf+5De;aLa>4}%u?m|bVO8xJ(YE}$-eJa%P*y-WcwV28?qf0JE=#mRq9=}9 z66D!RDQ`KC<}OVbl0z_Kh}3iy+&_PSi-l-KOl>3C<8}cSDxlV@t5qR^%_y03S*1{+ z`jZBw2-8yGFY)97!3s=2<8-1p7O@d#j&Wm^Az42GSW4R60a6!+C3*+QV$PIIzqoZW-5d2(!A{Ge}ZMJmoKGY4|+mYsmW%Mh9NY;Ut z0Vg(oh*kD;@^@vO2Z`>m(C5f0AGbpwfjGU33U<;_;Mvtc^>yK-YCz!;6PxFUx!(Mm zTm1!*d_$xI2p7U7$kwx1vPtso{SMvVBXDJcqEr)kX|%T_z83*Kmqk#;varK8N_CEk zBF&d?@WqNxQD)uaMdO_Wb{eu|_S@#rt>+0rDhppU-fK`UR@2Zm%KirF4MY64cZMZPy@R{uu^wlXOpH4FvdNoUQvw8TMGBTkObvb zq}~`iTB!sz_Q)U;`eOImBWFRkyDV+iwzY0h!j&JJ*xt#v>#N>nS@li+gOAC4EF&E{Y75LvA3{RKYH>eu8TmX&Xx~-rM ze2~E9hqdH?E55^*+q9)h561b%2m1}#T$K<0+6wp~g%s0cx;qz>LasdvYHA_?nl`Tw z&DX0QklFY`bpopCo(HK#q|m*`oGW`K#rcPI`cAi7f(_`r9d`p{i$sT5B zi?`^OJY6IeDikUup^vW?NLH@2IN@VH!uB&4yPegHvyRmnqNp21j9z+qu{|H3epXqk z^yCvN!1E|9fu-uk{>i9L!G_0?^Y*lehR0;{@CFzA&OiguHpl(9Ke+{+eT!I)d@Q`h ztdu`NVS20{QTS{9zw^hIOJY>??rF*o_Vurh%*2|LwZY7RxXxw(^hEEvD=WgcjO*Y1 zDF%LyQmo_AyD`qj?xq6-0FRMt^aF7x{&`kC#JH(t!2h_r%eCiKN?s&`w6fg%jss&zGfp7-+@cjw zkU*VP(n4B^t@Ras>!5%iBZ60ogFB`|ItkSu8mejR2;0Oz4n%Xs7t7vznsvPmgzd%k;fn|YHG-0nI4(FjbLN`@VTn_=&EjCWJg8*Qk z-~TfIlVH#9W0s7haEN|m1o{CyiVD1X6s$tg>~|&+tcfdzRpRj?chMqw{GdAZy@YGT z-3O;VLPsKb13&*;BwB;<1%5os81pRDb@DH{xLy4Tu%-jP!>U8Bz z3)=DUC5w7yIR>Pswk8y%J)yl+5~>q58pFb!KHhl4NA-4)tcCx3wF8e!;(%J@SRH?C z#L|fg+0~43LsKSl7T3k@;Gzb1+3(s3YL*lR;pf#|i6-Vzi!1rZ;ZopFyv|Ny zp@K`1Xj20a_wShlO|C9oeJv<=EcCKCAq(r@=Jt@|pqIPmC1=b%V6#f|;QocbV~zj@jx~tW$sx#g{D~ojROOa^3)XEwAaej~}_VPzv(# zMlJO$+^BnjHoZ~y-`h;q?M)CJ+z*qP9UlRI!I%^n=|25G_ip=_(I)Vp(cVTaF5fug zr3?!orXD%TvE{PrAduF2ZIQig^HKC2p&hn;0mWMpJTO7)thDedqM$f7eNYMq?LKfV z=`*knCSgxmgrG@JtxqvT;W?WqyX>(vH)>CI#zbuRXqaNztf6?Rgtgou9iqJXH*0E| z_xof061<^KI@a2Wp5}XM6rkw`Ko%zX0iLi;D;})9%?~Y2s<GnK2BUKWFs-Az{K65ATW?oH_Qce*yead=?etaL-4u<|@8W1zU17?#A+chG6VH+1`dK`{A#2Z> zKb01v1YvPlUk~59%d?!XqrLHd7z5_uIgn>_^-OX@U6(*1oM8QE--+Y3|c@ zc^Eg(4j2s&G~)iAi2jy~)bwe5%DV?J`=a2D=%_c^xwk;_l8SfsCfpcI~dIjcN${!?WZwD)6{%9HZmdHEt ze3SeR(Lq-vc}33ac6SPstBc>uTD3EPRRy=Bymy(bn~7Fnp0BDuo#Nl0JqkM@jEJ$AZk)XbiY~2je{0c*O8UbF5VjbRS;)>e77tWJX2+5?EH z8R;N}Tf`DQkK1jIR~|5MIG=%vOVT_&%~=g3Z82^GSgh>|0P>KVQ%9s$laV$(JjShCJ{j#QqvfD*r{KjkyYRL=gb^IHyqFZ5YD-`K1+x>p<5p)U)58Ns}EN6QtEn9kWb?*b`q+l!3hrLa?Xw-Rv*q-b2n|sN33kLbe zC7$ayA&Xif{4}QALj;_JJI3exoo5BjPJ^ z^k2!6Y8uq>jzSfn#j?FaYkjFkYO^l4@3ap*Feh~fZ^Sf8AL$iUlM;a{!*5A*i}VE5 zR1HudI?zp&z#+2IVo-;)`79HPH|QqIJN}EH@MrLc(ZhWoU3^hWZe;*0ebON@mh%WP z;5Cpg5(DDv$$|J36L54V@>Fv4ktF9*W;yRuCB1_roo2ASr@ggG{H|Yjfrv9JP+%Al z(0p*fasDPce$XZzX{YWZz!F;GG%Wv!(NhHs~!g9Z*MK=%U zqL-$DAKV%TgPw}4K?`cHz|kvdL?V{e$fU)PXMW&$fuHH(nt3nl0=`-c?sD?XCLS8H za(&j#rV`wK<zSSd}8tv)Vh#irQLW%v#m0Jo)+D1 z@!I!wG~JK071kVkzD3l$`a7yw!=h}8M39A>ZD{(FRSv9$dLU66V;J5th*xm8Rpo9W zdtt9D57pM?p&)LtBT}c)j1>XeocRP3!6PaPX0ZyyARxU?3GsC0}cfF^{wkxEGJ*iS<$746yFU8@L zwh8lSpk0Jb`n2;oenD76z(=?RK_(}t25ZeVu}pkC0mz6(wWW=%p(_NRR&AwB0r)r6 zLr3C1PnrlNiHx~?=%rF}?zAlMVL9QKTLSWN^EVG_!B z$^&~6fIe!VL_2;ksVKqVwV-l-jeUUv2{?kVI0;{44f8Jw8!&s5wzfOocx$uOa0w)q z2nQHrNot@)dx2Vm4lP`p@-+jb&YUwyI!k!im8~sxy)P@vo9hFW_m|+zzf9PbEg|_7 zh~D!a9ZkPKktcT}Wm*z73Gqc&;#R1jFnri@Kq)uSWQg^?u}~Etm9YGsM9IWcu*PvP z&b-BJ0!m8Q`--jY>s&h-6w;R~7uFj8#s+gc6}8OJJ*s2G%PqmU8;Y0PwK|v;$17gU zVP0_>@v7{s`m>Osi`A$Pt^B&ktXUW~Z0;mR%QFoFnV= z_At}Zc@w!hU7I(AUud`Zz9i)INyM_BF^$$ik6Ibgy?Ky%A!{l99jJJ*0j~*4HHZpZ z-0*qe!7E;gIspx|o+Tv>O!=GgZ`U!b&9M(!ItQ_Gk7cFZ-nS-#VRL5NpraI4<1-M7 zs0j~9fT&rTVXO46?KW#6ON=S02|FjfaiK@3qu8)aC|{1EXd^s9K@F#Evizjz$Bf^4 z5T3~*_KTa`dmwyN-H-xj`zDA8rZtq0zDu$-Ib-fbsDah|R}PsxfRqDaCkuWKU}{ZCM~ON&U*`9l(}X3dI<5;LY&~?Xge@A z_}XGrRqCCH?T&QOEs=#8E8%(;_MaG@@&Cfv!cvy=91>J0oJ4!wENn)L+8e5kn z@yGZ@qKDyv&?skDF$#Q&EG9?L>AkA^`}(bsRKXTGYK#BkY-)Oo?_a_)ms_(&#I@@A zr)Z1H6NE8mWh(jLSiBuHzupX;Hqfkd#fsu3%o?_|OriPip-(3in&f$ZFOU~A^R3sL z`^Ksebu&i!t@*XmKDJ6a0!pq6PHTVAOTn)d1i`nAvL!DeAApQkM~kA_xjuB@BQ#n+ za0ll`DrH0j0P1L8ibg9DX3eU8j+1OVB>z7+rfkdUOl~MP2#H|JVRvWaXt&uFM#|wL zlzPewH}sHJ#*TcF#Mn{xnA2KU_Urp%k*crag*;iU)Krfc(%d(Jc}7LJPk}joX;Tw8y4$cx>rrddGOgY%X27}J0CQ5%DVV1Z(&_aD-iJVf?H0R3X+nHk2>1E7GB*%jh*OvbEcn06(eB&Z0%V~A9-Q>#Cv1>)hGwl4wd zKH7+lq3cm$Xgb$ei`DiL1&-&i-UW~IE=2ND83`~3gc8Oq61;}t>wuP;7{~=tekY9Y zvH3v)_-_aub%Xy)+(=Sf39mYZs(zHi$k^2_1phZ%5d|bi%*8c$b&+-bQiR(94L~qt z;#Q!45{AsYa&7hs!$}Lk#h#xvw(Eu{1~f5^`(hF-T?{S~o31<gI+rxf3RosV0?3rgQ!mL4}9HhpA^h7}JW z6z#mdID&=NAmeDHTn{S*^M#?(Y})d|%tnpRVY?{Pry3e>NF}c$NEtb5NgrZ>TuAfP zE?AWkTsWRoLCqL#N;JUdg`7vfrUJ`Go(>pKwT8q zmwy=Q#)6x=P~$(GZU#2ca~SK9+s`W7%7?)c)3X;VNYI4Q!hswKZSx^=bf43LKd-cY;v>)?`Ndz7e zawv9Q7n(ue0nNrbsEU5em3z>&AT&K2%j{#IrH7NwwUZ24>gPi=_k;el!3vKz&qf`p z0Z)vAsh=3WIY#1GXZRmWJJvxK0A;nc&+x+P%w81+VBvdt z0v$a*ISh;5(>8aEtgEiXnQwSK^FKbREcO#h{Lcp@rRdVj#30bBSf3#ns<%p}-Q&OX z5I0~GtbO_|@Xg{6p>;);^GBp(LGl&uJK%Unk=M{MW9Nm>1{u+_mb9GAyFqa`+{{6D zXxQCM_3FQ(?5=r$%Gzc9^c>W>vuEa5A}Mlsr=jDaHmH}lps%{id%dra?~{)aiblCj zOX`dtOT%eXTu_ZpxaC*li@$~2dwT5}DmXWh3zZL`l1D>6sLGmXi(Q ztBEs3G?mz@k`^PQF{_@r0+$nomNAXM)e(}+0Cxq?(FD>zzb2JF%ry;nx;rzw(OaDR zOc~X~aC*}K6vnhj4ezuNc2^Yf6DZ7Xs8Z>Jn6EhfoWXLQxbDjcJK4~PLLwcix6oYk zr7mSTyGn7l3|IY_l;G=lBcj)?a<)G4mk2-Zyi;7+Q}qq6dwV^8Kj5v&E_=2e2y}%c z#Jc=P`TeJ(=0F{GLW1!5Tx?5-D+2iP!#jUi3MDi>=578eN^L?IIyqm@uayOu{D#VX zOipOLQtq%p$jQgE*%j-&9zlkZqbdB>#N_*V+kor5X`x4qYZu-4vad(=Q=QAiM4(Fn z<(@gG5&eIo1hQfmdED}mlvn`dW!@eRhg(s1brQc~=U)*=^-Z|LijZH_rLO~qe1Tf=8qgKsbEYUT*|2uMZG+QS z7*kIT#)O57+IE5~IHV#_`aze&#B49cFIs{BA6rXbP#f-6$rM>8DfFlkVU)aoheu}W z+QbNpkU?BOHbSr4W+%(TeQo?48h~*tx8*5sxWbfVMw3vX%|?7j2P!ZNEa3T&E7pdu z6?60WCv@qy+5F{?JN(=J3kngHIlG+B6~{+-C9m2}>O18oP%&}S1Kkcmw9;f8E6R=1 z`DdN%W4|Q-re$c(;gbw1%M_=7IVv%XW3Q;-Fq{Sg;O8e%OYr}RVFYryxxbGl`1il{YBO zX0cRT!VgS*i(L9Zm)^2YScX%~$m(lfDA+ zR3^Da$OnSp$fO2Vhykb67;Bmmwmtw~p?a$}hA3fnVQkCj;#+38Ir#_(-khJxV*#Y= zS@fZpeKYiRWgUDuX29Ag`RS9}ywQUD8RhO~-rLhdB4vLrbhtVj2Loz#IYHD~xcO|= z;+T^%t%dOGtpRdm)wd@Iy3~#nYeseS7InhV7&kJqo}F3oE^ymHEc@KU)o@+asDkD! zq0DlrPjuFiqQ4DUJ(WI?EAr6RUULJM?(Yn?PIoXEL za~cfHC9D|K59BhSQuoH9WGuRcV|mxHryIeNN{*JO8n{Byl4Z0aNJ5UI6lSpN=+0Y` zR66!KjTiwaPrxgEG4;0ib5@<^F0N5)fCh`R5w;!}fM>LM4&FK7 zpXh8b+qdz(Tzl#Fn{UR=<#5uX2{yKNp6pVT(4A z{s1z=zk@g$*zF*u!km?u$dA!_%DPBFWS~yzt2$?NRcx3kr(fm*qjum~x5Qteq26P0_IH7O)-Wxd;HQWKHP(I0=r@>`5#FZ-+ZU4R6efK@_2sBhst? zgkV4bb(5YbzhuN*S46Nkn+`4X+ICUKx>+^G=IYqFI#Q7>Kh7maZbq}C=0g`?Fsxzz zXK$_J!pVAg4`f&Z{H3pgTLN7qUi8nqxsCwEfI-r5y~7xroNsRN*rmd`EvG=wpZ(o; zh7R#RWlsdqoK`#K-DpR{$70+&RJtRO$Z{&+Qq;p6+YVrav?b=g=$ZKOXww>V-EJ}A zznWurAH&7FP<@)QAavO9wX;7cqz_d{c=ky!pry^ElJ%}7?8=Y&a~aV3tI!G9KZYhP&;^=x>|&lOAg?(t0sU$~+F~p~?zo z)4YD)8S_c@#UE5;IYgrjRDm@66ck*~%DbR>zR-kDW}4rhli<1k`J;P9O8Wq~wKy{F zeAD))e)IBk{mX#4!;hV7qt7HCW8Z2~N`IFLQMQpzL-#oln~nOr6=|C<{qC#Odc9|$ zVok1FTyuAhzL#StucnuST(PFlGj84{fqc1$cNif)`&_xUaY&s)bnq~D-iLiEBBpdW zN_IAHj(hxA+3at7`$ZX0Tw=ZWj*mIdx~_2L+Reolb32R z*LE^&G=W*q8DGI~xOpHbToR-DWaDRYaAgsEkU(H?uW?=EGEh~En~FnD!`E1_yj`B7El+og;ofJmhmHP&xA5JaFT^_^C0+Ac-G#nS`SCt{Pc`!hE#D@$4A-OiI5L7tUZh(GZE^sO_Z~D3d&1pldtMHN$GR z%~encnn@_=DvUf3D2j)>CG0O3z`LyXAdMpa&|Yop3j_x@nx{6!)DWkkP|iyg5evF@ zQXX{+cole*REXbFfk3s=;*>BISB&;EU{2Vc;y_}H-vDgXWWp@j)Hxe%{COM=oM_NK zSptC$#gbq-CpwCrA=v+Ge4@cOamemUFV(AQU@*m9o-P zz!zBLDxw9QD%0-a$65ocVDKFpS`~kf&98&1d(Qf*3TJQ_cEJULEd*wHuH~$DWN(JH z`tpa)6}r94?hTqfyveyWSb3-?sWm4&Fv66oJZfU&YA(RBFMVwDn`?y>8zdmcYn^h8 z%8P2{=*eJ}f3!4%1N&&l;byex%4^I4@aMn0cFMpM2n`Aj=vj*z8W@wb8~vMN7Ub3D z4|@jL>ixtiRnB+J=82&FZtY?CAopxC-*H{$ku82*cgcPcAZ;=QH;<&dR@vjEkn(a` z?bG&sZKQ;(dG`;;_|ntT_i-7U3U`tfsQwsJpYG!E27>v%8moL30y2{Ufez+-$o##U zqpmLPJ_fACLZ|20%C+fKr++3#nup3VwxlC-VyV4fS~%Yhzfnqt1p+p!1dAr!Io2SQ z$QI5=Tt#Z#h}BxoAubMKTv@0vj3LG$Y}gI+JPL_CwCwtm(Per3t>$rg07)cPvym{) ze?E0$>2~vv5BzQWsCY5FGKS22$!mY;os@F_=_Bw7U7ecOkFV#0W6+b^jtUt!^*x(Eo*H1Xk6PUB=4t%W zXxFckDQo!s?_iqH(TEgS$Mum{glG@B5Je`h;pJWbhkZF zUppIua|6{-;2Hy&zmqXHA#hpS94&jJ8$Xwv=eAt(ut4$n`rVd`=DTv(y@D&?=Dzog z!&BL(bec(J*brZ>j$b=kT7O{5h>48-4B+|T>d?7~Xyq5v!o1ld;uAk{G2vQiy)j+d zV!%v(GYJHDJF2i`F1uMfb%dlL_eA=srmm^b6M~0y@GbToTo)SEwXW`Pky6&hE7+_B zeV4%u=Kkz>8{lc_VZx2H79saZiaSUI_IH0zoY6}R+y^M>0MXH^!Vc>3pHQ8xHncXR z%-Vd$k1oIa%#vk+m&eQFSqeRr!4^j*{MqtL4@XS-V2j$0Z%*jA5Kp^C`1s|kjOB17 zK|>a=qL*qdZNIOzlr;BGNs-4Wg_Mlp?zfb^?ZO^@*quT79ihar^3Ea9)<8~O5I0LJ z`)7&dB(!0p5HHz2qwd*vBpI0%_D!l~;>TXwoQR(0bZ@Vj0OQPG1ahu17)}IN_NE~` z*&uKJyQseEppwD{hX`U@oKoJ!oDB`s z{Fm2a;)V1+z~V%KN3%E>d33Pw%@i+ByaN(4Nm9StDxMt;4%mELkCm&$-U}|N{4#8~ zABjx~oLT}tP&txqSE`}c!|xx4yb?{b9@Rcd{4`;yc^PYdlGz8>u9v8x8wpOYT>WG@ zKK^2cn*CI7xb`B*Snin?89VR);zYuy1xtWG2KKw4rOf-Z?g?^7oK(BVuXGJqyKjNF zP$aBdvVO}iumOT4dvAe67G`3VgJv2#Q6r%T{kUk*EG@wM1Z%5Ql*?T0kZx}J*ucO( zsrRnVfIXC)s7O{MAF`fs6xu_>1kY^IfbzU*r7AigBZ$)|u}j@}!B(fV8@_sjTPq9Y z#w%HQ4Drg+^GADBc=}b3*>NVsr7G8y^Zpt4&{I^jb`$KpJAhWy5ScOY_FAfp8jE)rt6UFiW%ggXEoEXUR zAJhepDg^^;H8G^wMVSs&%5}e3i4YQj(bbtf`QCcyzC9aQ+e1t`tM$xNf1ev6N9;kJ zk=xBYXvzhg!iA<_@?!GD@AoZ#P{hb#Mo`JOEOUn7jN1(p`7d}mcrC~$&i$~vAOvk# zNE5+ijW?I}2n|srv+(JzR^VdWTDzqH6OO$F`GRDJDUd-xo9Ts?dB0$k3|*@J=+{)! z=u^Ow1dKA}VPxEF$J=v7Y_Xi*MQ8Yp%%uXIe!_#3lf!bbX5fDH=b&tBub*$vTxIWu zK4ft=B`YfCEOT9fDNdQro-v~HXkqJ2_}cX(;9o8X0{`)>Vg7kLb!wTUGWKzSTxh;mvtD~R!E5|V(e zg#!NxBzCUt*_(zTW{f>1a2=ihOyMj67ECTPW-MtD;5d2kSaZfpO~viNUg+sA)WFMbU?bO3FWoWh9S{IH4wD5 zX{0xwb?K6?+QK0Lz8~#yh%OqmSu^TD8Ypwm$N6Gst_!zA+TRnL5perFPOMltX=YNS zM;k*^>l<*1^VQ$asbjRIr=)-Cr_9xwR-CR))IP*8{qwy%K5c6r8i8O2$_ouJ->PlN z&UqsHQxbAtN8Yi5qLEyhN6UnX08*4qSXXgHN{c&_70z=AaG1j+xDN-u*w2p~0PQR3 z9MTFMmYYMIC6C1jJ!~6sW^$puSgA-|Q}g;U(ye~R`*uocQC7I@iW*g8(Lh==aKy;YB>vp?LwKT3tpj( zXYu6l$q%sg?72J?I0|pg(d{T!!a)sg2(^#mS@TNa`HbWLZ!VldJEXh!VKO$e7WY5x zA}4vAj^g8KgM0jYeq~a`O9g9rH?To1ygKFZZj;TFWKic1${=D zLpT;3S_$Tny&A>CqF~2Pmv?L7*6BZbB%E;|2E{Qf6o5ex8yb_UdH^9Hc}Nyxe2fi; z+5tJ)Mk8)N`lFaB(DX%iPOwHt(@Htik{qxM(RF_^`VVY?#wO48G(a?tkkexP-O`Fi z)qHDE51a@Olu%lCaYOSZu8kUoGLkyU*I3Ijej;~!oOmsLL)FxAcVcKXAdyaI)I0+ zHNbl7QimvppV84FCL)i>rlJ)^jQabr*si+|OACf&7*(CehcY!gU+i8(7yJE`*9zKZ zzU3Dble>ctUIk)loq@bV=*O4GravHXBP62CMBOh=@3uNc*MP;s(Z}4yV*BxjlId0E z>vPfPcnfg~xj2A6uzOv3Z7j>O(h1dMR79Moxh?RB>W20clQ{tuXeuG4UEhBD; zv#`|Tq~2fD89l(R$IGQ)&Jfh}AbE@D6gyCWCixdX2!T*GR$Pb7AW_@Likmb~YnRpH z;kH_={t}H~8k{rFH&?|rO^J${>)^Ue2A(+nK95nlv6O=Z+AA!-sd@odV;#UZQsL)ZK8e^Qvf%p%JRZ{jkKphbl?tB2mT^$}+U+$yM{-3KGYuF~!J(=i0+*;vbaPv$1vC93!GWQ4Dn=>Q@SXJw&H z&DP7SFM<1B+IdvbUc0{9lY+Q^VV0h#FW{L~y|zK-M7C zge@y&%2bbt|0P5@)3{(j2!hL6I~)v6#T;fvK_4k-W+ePOrF3{v&Q=s#;_#ruPeeM-^Ad+9BLTE>tp zyD(wqBED{++p>-l6DgU0wOUyDS*O=BjKd7vN6z^ zd4q6#azMOgQOT31qDwC#EBm-We}&$1_u`yrO%*r2hMq7vJjj3h0<8nq=eIrn-`6o$ zq0-#U%-H`z7Nmz*G55!cGn|IE359kY>7!WkSqwo=L2Dh5$Y;fYRmUMr`0;SIV12UP&=mlbLU!@4gsh z_;T9{{<)?_b>itypdBcI^>~M~M9Afi_AY3yU1l7s8!M3-vGcTleX3a-I))W?$o6k& zPG6YiB7QfzLZWSfS6gCMHUkZ7h2EM`zHQ3+uIFuz)Kp{+6Vp9UyF#$!$*>*R?cKwP z+0K*8ejd}+g^cc==`3r(`T#iRI7{X>??&xF+SmiEXJ)yt(wyyn@P~nV;#pa| zP8o3As5D?FX&&=vn#bd7R=SwL`p1c#7l^0vdWb68RVR+3NDjxE#Adex=*fPqEjS)4 zyzH*i(b>d)ZnD^s1{UobJZPAivI=4_KV-C~tAG@RK*)!E)ERT^$S*!|XMIcWye_#Z z*=nv982A=Ru6#UF=HsX8@#kDiM-IkbfnI#PkU(0R`3@r_vW~1!!jipQ!e-oA9;`ln zfD06#`+R{YI%}wk0a*d4F~nj>CgsJvn!R1g)k`DQX2R*`i&)fLVhHu8 z*ouAQ3iRI5r`D^0q~Mt7i=(a{c!OuAS)M%U1Z|zqimZ2&hOwbU2- z`XZSd^f@1)ol@_Ar@ryiX`v4K-dp#_PNanP=zK$ZYc?;Y5CW;xH;$MkaX_^0apD~m_R5>wxdxNZ6&VONUIKu@ z`5nIHhSW~_FT0WQa{9e^RUo?oXAs_?YvzoM>axi;Mf-D*QKKKd$2Km-ex=rngW}z% zMIZE_!Dv2|` zk$D9#*8;|1#Xckjzb5_fvKX786(1b;0VL<47*rx1Xw#_bm3Q^jd=~1qUTR#nv0Fz3 zl4yKoiJrT*JW3fUxa*n_mD_KoT3cDy+=eN7^gjpa@hBo)iFBK?{ z@He3GP}qWrQ^U6FAWX#C$Oc@bnhN=2QfMkf7UNBiwRv6jy#ayF$C0Do2fK-7yzEMB zwQ2$v!{xe9iMWT`W*am`p!;dQjRY+tp@<&P;>YB)`nPO42B(P`HHc2V>_fAxXJ*W5YANLyGt)%Tc`@ zPPFl56&p#_E!1}jjB2R}ypFq{)oeyHsNgHRKmD3B-V12vG}8yzK$UWNWYzE#JF`Sr zEEAI)KdvDYGsgnW2FG%PY+bBSC-JJZ;76$fNm$c9W81sbF1Nt{TvuIvGV{gHDz?S z=%RKzqNYc?2SYK!50*d#v*ZxubMKIN0nmFX2UC__fMQ4%{kD$W^Yom>>%V8y3^TgN z?i+N=fxJzYiAeNKxq##VNJMQjWRHs@*8)CqMkg>-Nv7+W1L_?Zm$%UDe@XI}4{hFn zc@$D@aF9jm-oiiDXH#$u0frFlv$lYAc1ZX?@s-RCWu5CddN^0dTiDp{-Mj(Rwvl8= z7>ktgj~Mzkjrm~?TzLaVtAe8Q!G}Uz?QU%^yw(kRa1yunxNoSwoOo{|0@9H_<2|5_ zL)5P~zsWjqH;t>zzvJq@ouPKr_;IGVPd%?NUCCVN#Z_80eSHh11fR>dnELrga*a}v z(Ti-sMH4yICP9O354u>NbC-%a;8;sBUtrD+$WP-d)JVf=aM(ALGXWSI*t>Ct6{I^K zaBxx`@{oEQYW=aK<1cI@_;X@i~Mj(S^f~!Wfo(*aTCd!u50C7 z97xOtnVuf69>?GD&(K}>ACqGD`D*3B1d1VYFYG2yduwF{pTRKR+(yT$7 z0NDsz|0&I?f<{?YRnySTz|p@Ruw)`n)vi&exF8FNN4JZHol~aw9{Ak^sn%;_BY=|hI?TW$FkH7XqSf$k({eJS%H>rR z*H=-_<;D&uSEpv%?Ayl8bV4rzit-~9ZZ4Jig{Ct>Ot?tY3scXr;F3V8`x8x|Gzxxy z$N7{`q_pBf+1}Aj6+>oJOu!#4Cb?MHLb`F*L4{T4HXPBbZ5vLw$bN+IRlX3*Ujk5I zx|vi$10iIGUvXCtqR=@$F`B1~(vBjIzI-4i@FmQkzCs^HgdpJbkCi3tv`J{H3FpOu z5buPqKQ4MHqH$)Zv|UFST}wB~IAL@YCS98dM`YkND`oKC2AB6^4lDHpupFelkysxK zQaj-JNRkB*ZQJJ?(d0_snw9*I6r86UiY{#AYnX+t&v*w}1lK?VR`l_oi_Nn%Qc{R8tV0MDEAohFNoD4m}jp#+3#p*`F*6w`1?|`Qw4M<#%ggAnAZSQ(roI z=m$=95=RF{+*&LOU-j#Vuc0O^$;$nX-&K7##+_H#34xM<5w?h;TkIX6R>8n;wHy0+ z?y2Gv@UY-BYMpoY0)^bB4`=k+U^P$z7G^|qV;0b=|NbYj!+M%tOfw-=uM!n*7Rf2O z&QM|-@S9_$SEdh0T37`ZPCW0*3;)i}YG8b%V#^0wJp>yHKS zx+13EShXnCsL?U*(Ba~6O`LGa&OC%1GHt)Kx0^OeHEOcD=|*`Cp5u02x#CnHma|$s z*Jc|i^|&6GS4cnfO#pCpnVed8i{hh4?;sb}xi5RvI5*6dUrVJLVKeqJzkw<({^|_- zW-f&t0zRx4P?<&;Zv+9bg8QHo)CZ9T6P=vdS5n4OiofDA-)3;xF)a{dvA^6UW_<~G z`*_bll7HQzS1I4^xB0*N(YsT7vJiexVc3dBgZDArY9l^qnkk7$x`fEqa^ku+%3-IoEpUKt^y+;+(b*mtjxCEhhPO>ree>K6gNVbt>Qn*g8-n=>IT2#OvKJA4wH&+5 z8L0ui!vWBqdhi7JyF6F_|C;2^PNC`V^u2a9_%RyjsLDg`4eTKrsS9{PRA82DyLoK7f z5a# z365Muj~S`VAL&$lcN@{J!i-6{M)VnA`q;$@gon*u~!aOp%wt<+y zYz0`VHwyP@y(Z4-=XlO)dKiq@ZlsbfW)N{EVCGV^j(Sps6Zz^59R60 zjz!+@4p%hjM)SWoI6Ws<^x;xeIn9cQ?OYO>hN>S

pj+>L?LAR0Qw3w}$mC|0+~$NC0lfeDzCM20rvr9NxM68-+Z3!041 zFNIJ65f~4_3#$ailRp_f5t3t)1tJcq1 z@`s8kP~g1_=i4p7HwO<%WT^uRatdOMn}nJva!jucyOTI^zC4M`5J8npNh4dMs0k9V zx3%HaU8w{iKK-J}@*CQdt9pl1YrbE@m*swMoC@{Mv)WPl7s22DcqzRsTcafT(%lj; z9}g^icyF!;MKn0Ki|VJeU=K<^>NgiN+!sIH)jsh*Nm-ITxs3ecQ!4420B9wYmI>wx zt4;S?R;!vSUnwvciPxosd_e+5E4cQ|DT;2!3$iz(l z#;Y9xN0P!ci#d6f(T4EFkNrkC3r8Ofl^K{-!Zac>>ajRVn~fl!|85m~!y-G|=+qnp zQb&boH{}#9%I=8ImyNu@X#go2o?xYn_+{>+JRXD@34&gaFxI^sEK=nK_@PW*G2Pll zvvRcYMZ=c~vl18hafJ*00giX?F`G{Vr`_zay4g^&2sIp-G!Xc-f*_6D2mD=7)G*|` zrkd_WnY{jGQ6vuI*|@37z)G4P+ziE<)%l#ixbdb6NRwp&lZ02KVTD7|0RY;``UEsR z{JEVql*+&t;nL7gnlEDpm8(8_ANc%@B>thNpZ~VmSxYu;%PpLS_cE#~Uws*&FTGYHp~1LY(eUEzB- zasC5i2Q9R~jlRGYhfbcJ5dv0*{YIf6|Az>{f2UutqJeI+J!z_@BvzI4=BtB)7M-sA z8^^#pf)wmqMvWHxoZ692*%%k0Ay@K;KJA}PraDsBMZq%NfX6D;zpcMQd4FQFQN0vICzM>+ zhkNQ;BvC-P&wqqd%Ke1w58ovK*8&bT4Y5~};@}dW%@yMsgmZ(lKe!0w}OnUy^@K@cV@hT36tXX4sb z_#|rQ$b4mMNke8{d1!}#57wcCYxg$OL(|p{CNDmjwx2t?(;#oE<$UwP7e$|k(qi=KCVE$3FVxNN z+Jm@(R`wZ~YT^9$2Ca9VO}gL8N|UXIKrn%Q=?!J%5ZVPgb#}8DrdOlHh-feJFGoN} zyg2eW#W3MAaZ9TG9eD|A$^ZCLB`@zj{I-)nHDVeX2PNux9KH=fBJqlNR9UFGqv>^) zU$uK%HaQ^QeaBdqe40N$a-L!{%s6+beh7AQo=1&Ku8+H4E)082^S1TSO z!6gAX`=C!&>uU7c^J=c}>7J#FkdH^7-HJuNj2TpVU>crQf}b3sKR@1u`wMuPTzht8 z4xAFIXB~Jau)(4PC+{b$!6%`h=`Y90Ty@BIUXn(N7%XvGC;aQ=Rs9Kl(q@uib_huY zDmCQ;)5TNbxnMfQH4;%3znR~WS5o46cshpanvrFymyf*Z|9MbQ>>!hL|YuB|V ze5WzHbrhT{+FogGQtjqDs%Vb%K9vUA5&q!Xgj^QFO&}Am$3zjn0_xj8B*;4J{k?Nn zclBDEQmmN(LcWn9Rx-f`9`IFo@Vi>>- zX3{fze1g-k>pYl$VTC&{WGFCkWhyP`RTh>i{=_0_6Ebs?4*w!M5SK2NYrGztTpP>Izlm+hbwC!k(S}1&^s{}jAySs{1#k}+2TW0 zzM-qsa|wNu$U<8V{sb(7>U+#PDk^P{S55NME~_93{LU{Nh3+_aBD4sGH56)7jqZd; z7SvrrNX26dY^0LLiI(A&Verg(r0yFRoa|@CGR96tuhIq-fyKnGagz6JFs8$1a0om* z24M?!COiL)0fgr*YKTnKC1=$&VWq?+kBIP;H zRg8CvXS^u-`>67@qrF8d_w9N=jC13tyRWZKT0H`}R1c5R`DW_U%iND{htBu*P4>!4 zKo@AL!R?9&^*jOKZ%noT1z4UpWmLR|Ch=~D?9K>MH4PjPqhxJ{pM;b3NJ6u$jCRQ0 zD{rCBr>I(PW%&C_4;4~Y`IQ>4_`@9{8N{kCx7(++0g;L|;k zzyYRnOn)b(ja->o{@4vwMaq+)2Cd%3tT1>Hs1BDeSI2mZVMjd$0Fd680MHnk1h(kR zIdT22HrVJcDW3rIR)EOCGn0MH~UE< zWkjQn6Xq7@yqxO<${Ob>P!*rBDn}Q$C>Dd}L0>vE_AVok{`%^a`{A>>cwbyV8&UF9VLCtX%xDYy=ke(;*V93*=r=9!rFq!|?s7JBDO>pVCmuz;)R+>pfpPyu{cct+@1 z`29&h=N_cU3GnrB8jw{RYSJA&J9*#*Wzo@r_)S0%^v;vaw2nF?s`o=1JtQmUWrwgH`= z7{0^9szY^uq@J2_eDto)eOHo$5)Ls9*$RN!G9y83pc{g=(J%~uw&AjTEHEM2;M^b#-R zyBdU50N|f6j-FIM{Qur4H()7G2RRCe zaWGG5dbVo}Vr~WK+V4~WL@7wtV{J)Xya?tLP*!DmTH#F*(IGwQx?u1% z2N6ry1EI8HDpW{5HbUsXnifcAfT+fcA821mX9afyGdpcFnz$ou+^vv;~diggq)TMTX`EL9H-8| z();@+@(r9Css}S0ugvPj6P5)n{ZbxHrg)&H4ACN^4q`Rh3%nwU!4LWk;~Q^pW~B8z z`o#~;>hz2vlweX{xS?zX>FnF`Re@~P9Q>d2ao~QbZL!G58koo>4@d?6L?YV;Ga+gG zq?b)yJ*zcRK-Tv()pV^61lK2aS$-3ohyiWwqoMV8}! zLw3Gjf|1Y$Icg_`z*8@mr2+|$M$=+zN_%C%c-hOhAgb=M=Q<1Z0_#AeF3o*H0lP|? z<1`!8m{!HN@DJIIL^siOcyWqK-MZVv2RTtk68IA#FmmX01a2#)RzKqJkpz$6Mx&C^ zLqsT4f29E0HM6>6Z!+A@C{zs>VcKj+#K>(J2A>mLa-^!WUE7Lg9`k)-g4|t3gdcOl zbxz~G%5~OT@dmMDNI&=UUu73?bMrv4m@DD*?6@!(GTo!#+-4H% zhgHez{nV3h>HH!wmLpUaW8Fv_<}Epf|MIeLsg+j=_mu^iAyf)R2FbbA5p@I$xFv~u z#WwPX4Crh)dp7v17;k~Q=>j9-(%jO3&Kp};u3{}jx!IK6q?n|lU@ zA&SW|2sCPg5DZcaWC#!%6^RCl8UPFjFIC0h`Bio0=If|ZqEG}fhMZ0NejA;^s7iM>V!Z69re@%!ssM;HB6VGTBQK7gr1_W! zq8oGCg5#?XD*o)FhiYxHdJo1;ng25uKqSw4!_sRm@-1W^_Z60Ss&d=2yjaL1;iFa> z2$c~ZI#5lh~aHKB8szm*kVA!kAb0ag5vh&&_bJ|71CI?nV4DWjCF4& z7331~eviavR!+InEV8hr>bADtEt}u+glJTt>0L<6$4Xuv5J;uU1W${aSlg!)jz8%3 zMBW=H)-{QO=m(4!oIp8^zk_GXp^m(?-FN#f_}#2Ad|k5s8Qg?cR6GNdh}qJAF+u*6 zUECPh)ub>HB~3c>?~q0dv{)wIq#2MML>Ut)pH%I{5kl69crEzkkw%Wwe(MjaD6eS_ z*)m=Ck3g_q$Bddb;H+oFj2_9B{KE%foPd|JgT;Gy|PyI#f9h3)tWn zlZ&?e$1B1Ql(9bvP91>vmjt{+4&PkZ1S#`j4fQp~aT%C<3#RkD6PEMNqU6mL7v}#N zQ{raaszTzlT4%$xl7c4y@=S;18m3pPx8;yFJHuV#Ic$L-&(pEk?&ytRb8R>HoL07W z1bY3m{ynM}OgI%_{LLm7uK)W=&K8s;q&dbF>sMjfcLzchJAPdlBb@gB4^qDfeJ6t6 zAtpEy2rGe)-3>-i^!HehEPhsA)`=%;t$cjhkXB@m1_qFsm2m#7*;0F_3KrnWW!O5# zqINY0&Pb1<&yk#c6|uJWfaAJgF?U?mWK~rU=NGJs&>4{HGqruGyqyE{q|}WDS6lu$DeWx+bVR*GiH41b{2%cXF1DP)3Sn>QhJGAeLY5~tt6N_bs*LpioABW^BUHR(2laW z+$XocyG6I(mT>l`9L@9wL)+@W9%T5ahnur%8%2^ zyWSvf!66r|0l&bo0qMbVSH^t}QsnBTGiPIrG$t}>?*8@=Pyqa64QG2eM7N6E(g?kc zEU+1g>q|z@c^G0l?>nHcN4{8c=7Klod;B5BmqYjl+Cf?HWJtCis8(RWnn&^yp<>F9 z_tCXKP8O&;Tk=bk;2Q}8uaJ5popFl*2@Z**mXvLZp+sD#_Y3;a?1eL94SIDAjj8iJ z&U0|lDqqd;c92yg2YC_JsNQy|YqeM1iudb;r%- zR+<}!329|$8c>C$YgcL-K?@~+W%TCk(pVB`G~b|y)Bkm-pVaxHRI&9>X2|G(2V2E$OIQuGOr~2xceDV$b;gM95TuiWA35C%d-!*$!hPp%>FQbXWUMV$ zXU#F(R3LX>YY?e7zNPlNze3cPKxd3;3i6Xcqh|vnzDL?5nvuOLwOiPIjszM17Z}K?qkude#NNC;=BI2It%^Z z@*Gq3%#gF-*7i{dovdJ{i7rxvf*1(}!DL8qDCGrdVa~FKn=wzs&>&ZBKTW)Z?#J>9 z@~hwkEYVgW0O=ayPMBgpd*sodLPX@$FpcB@zOcqLqptc9=138TSaZv(_Q$}IRhl8b z$F-sdVi7ty$q27+F2`cf4#Oy9WAY743!p0?uk`yyAD<4toiy(=b7>or=7T3^hD8f- zYnemNcpes6h9!r=l%N+-Fj;Ot!vF1AlGwHLj~A#uq}nC-QTGL88Ep%fu$0XK0mlC7 z%_mX8pD|}qcAw|V=9{X+-NVW8kxl4Ney8&A$Za*#V;5uYp>AO_KD%;&6F}FE;q&`u z-)#KAZ#!E`R;aabMtc40-al&ZjEy5NVR_LXtrF;2ZWC(iVEYO9s%WDg1tI}qVO5yJ zJI&7gcjdJo_U_NL$ze_9g}=9RYh}%CVh9{uk)y&!I$Au-g9F_XVx})Znw)7o3phO0jOc)2S{QXary2+U#M1z;Dpo-9QiEV%lGu9D9?(#r+4dZ+)5@x)( z96ZG6&~h(}Qz?NBe|>gOy#<^#JO3+Fla*}M>)-R8bTkiq6{xCg1%ObNVQcn{&0h<> zYD-;b-ecen+6j0G-NMK}Y_fo+1eA?Vr-6648qE>%h11Q(3a<+(pth6_0TG)6Cd}W0 zQ8C6(L;HuA%+aS-SVGP34zRUUetqaYh>4!{vfZEGv{=p8S)3!uHZ7~w^r)RFhm>{^ zz)qy!-R-_p&a(4{A_Y2FU6V_y)csCZh~d4@_z%NyLf0L|>H5&K1_ws|4#ef3G+wtn zK-r~HJ_ld30cPD7e_=r$%wa1A@!9sg0qtRowL!JXz?;qGAlcX}zTmtL6y)3BG(qEf z({e-53w)GE@19q?jLgjC9uM~qflHo18>XZx<82Zc-TLtp&191kE=T5?joZwS+`o^X~Cn}uQWhM?4^+sy&f$I_L!a1jHEv!_e z2S1leYAN(>ZRUxOJkNpSzl}} zwi9EsmCt+2%G5E3!*4-e@URja@{oy0RZ%h@SHhnb(Vs_7!Zz6QyXJ)(Ij#89Hx?O8IZ{e;A#P=i z*ex?PUp>WVjWZOm<$&rz#Q2s)Q!=gEUlm7=u2eJ*WM-O`t_440(lt6zlbwCilICXG z_EUTumP+Q3sr)NBub$6&87lnGtJAN!-NtpRK*7lCLr^sw(NjF|*|9ShKxUko!r&@p z{Bi%=L~h-i2XSV%Y8u&3Yoz78RfCJAyG}|`EzeuV%KbksN~_!Dv%?q@%^^JpiQ>|A z2P(QwrG7j2D_H~cKcwfPh=1IDkTM@@s~j+f?R6fVOU4Rud_7Gd~V+asHgfk z>V^{`J&{Y4I6VM;{7NF|4JadXc)dWCb0&4Hvx=xIS?L67k56TLbe~0n-Id#HJ_`v; zOKP-qU8I+EG&g}&kFk7as>~z)&>x+y>}zvDVPlrJM{yV7c*^=lE1_8AcMK(0*5iphhih7+}g#g99cLGEsPo(+dripqJbL%j(Pw zvAZ6j%>)m`OO$A}gK{^$Den3GfD50Ia4z{zMQjbGp$8k_$>dIiG(OHDhW@8_~nD^_^Q_PPOMuF-Fk% zuujm9#Nc0}p+ECr*>E8?_Gbh%y8R+vO|0zH*cx;09|*A|7BjQ|%$8&9l3ehVO>5!j zba3Dl&7`$_a|j4P-TJ!6)|VAh^hU+7D}!Bv(&dC&+R*cOW+;XUF3v{&9|5eI{2B_u z#}{4WEAF4B0XpBdR-^AsYcl`S2gM_(P4{tcpi%uOv8ZX6igt0>PfOwkY{ZuaC@Yw1 zwr81JDOyEEl4F+}(U3S32f|13~qo?pl=Iggz%1dX^|qf&Xzz~N`nhvy98qI zx5Sw$t1ti|WTZBdll@-%7V^$d?GI5ZGJIyyfJflMSXx0|z@66k&}pr3tK8=-u`B@M zRqLo3EYq(oA&VTZIDd8rw58j>*^%~ z=-6E7A)?4~)h*Y3JN5}031P2~~K7O;WI+B9Z%T?L*a`}+tuFbRj(=fn4!XOVBZK9JRSLxmvw`Ka8ynDv9sSGTsbU! zRXZ$BRhJ$U8Xbtz!kmgv&yO`enTI-dji=`|$byw>u?cs??a2~S*lqxIr14TeGldOtXG6}D~5}H=N!@1d< zQ;k7kQBOe8Is2x+1yQIWVN~EjP4mtuB*?EPG-8FzL z+rUA-SISD7%o2me@|s%t*;VXpgcZx-y^((aKoDFyP2O^6KdR z3J7%8LTIsS>U1(i8H@r%Bs|fe4vogkAixQoeH;7-zL`k#5+Qu40&QcP^{BwN=xB>o zSFkhuC6DbqiJAg`tgM{$!V}oCm~j_zY*X5SZaJVd@ndI5QI|h_kT+^bR3he(8rAxM zy@mHKmPCBi*2}yPU&iJV#NZp@S{

yWjdsx26}a4RYPgVldxQ2#uvTpAK<>V|yu4 zZ`{@eNHoKTAsZf8Z$)nxT(w%*cIu!8j|L4;>w!-IR>NOkPmcPqKILmHR|mJ}!X@)} zW`A4#X^uhu;a0;^Zq$WMRa8#2m_lnTmvm5P17cAzEUn zBv92lfrJ51mwkvpir=?5Kkge*im7MT1C*+F6^Pi*Or?aMAMpe6hY)liWE^Rk%2dk( zS;(girWErcFaCXF3E`O6$ZBHM)Fl8l6}{1*FDRU=x|rdyyAe~mCq=1|q3If-fHM(O ze>XtL;6N1;6~1OsbP!g?EU$;kn~zaOTlfdou$8sFum`a$K=!g=Ykkquc;Dni80ifGTkXh^)o2cI&?Tn0;JeiN_#I4 zxBOD4OBS9=^oO_{L!ntGUAZlaw=Khr3N`M3{vEPW5`MITNdH!c{|>${ab2y6IVj(Pz3 z(EI#HvM>&*9Ndh)AYg!7I=hGPR-vA`FJD6ZTiXmZu%d!B- z*Q}S~EbnDIUqL(4pbbW!y7&>X`mz74NF;qYc&m3ccIZ<43uMg!BmX9@Yp0hpJVN@v zvKt&aAZ#5VGe@G5kMXc3Npf~`XUk=%DbS~l>Tq|KwuWM1Su~hTE6M*{4_5UNHX7~_ zGvv8)m~GD7b$s3ux2=ON2}+Oy%o?bqU)Q=C6W2Q2n^OoH2kq8z*`$ zXJgvTNVUG)wkTj}UPy23n6$^3#dbSlXPLGw+BgR^%>uGbhOv)1aQ<1gC9|HjHrpfJ z+GH_5@ArD1|J~aOmk3PG;(mA47D%+&2&YsaXF~~Ccu>i9!Vf1~W^VlZP=f%o7N2?&6chZXS~2^h%!|oeIA9?Ivy+tfVo|f}L$784 zs4a0)s=4c#ysriefU(d_xRVI-aff=dA7{U2b+CMbm1&Z~V`^y5{q6kZQT`LxltFX? zLNNosqNsmhrmEgh?2UvFp`;ZEjHrBk-f;RhbSa^&v5^r{uKvY9pjy;8xw85U+cnyM z`OAwE4>mq_r!v0EQMOewXo#!JE`6KkEunnAw%A1*r(ceid+rJ=b2GZL^ckkJ)>KKT zpdbkvql=6Rnm6;-g=<4rYa}opO*|?%!|;iGUx08-pe2$Zu9nBb}EqH0v?2(5{!DtyPpx>*``#V^?8J zm*+7n)PH3uyvrquvthg~40V$0ve_!OF-bWr3>)hZpA{5_J@hNkuGhl=Fk%? z4Dk-fBXRn@E=**L!i1Yg+J;CHH)WjuLncA<9Q zy7s%8sUMlRtHwXEY2_269gX@Jnq=GmmCW(mIe~ z{f##lyVHrJKD&t1`$poCZ2bazTfpwCFQ&XFDVPQPj>}|Cjm4B;oPB-t=Yz#1h&+wD z%(dW1x49q9h6t9iIls1MY^llWUWZ=UlTk&ZX{XRDitTphro(I^^nU1_DML3+V#H5)etpUg68=vgj$65Iu(hLh{K#%3g*pw7 zEO2ajZGKm?Aavc-H*du!aTKVCe#RV-?6TEtA!@;y_>{-*Ag8A-#AKgtoP=uj0^>2! zw2TD_n>hxc1a6Ob#0ixfuO|^o-;4^(1W64~=;;Lv5RMoudMaqSJZohDTsKBuAsx0C zi$eKlyjRo?(->4I1(K^OLcwYbG5&jbj?`hVa_R%~13NU=>y86cKNDade>?_t_!W2`2qvuAn3zt)iGN#oig6&`a|Kx@hq-1q>-Ab zW$$$zL>+V3-Cp}95AhY+8>k-<#IR>4YH@bn6sYPGJ#>PcT95mol8$b zTc|nS1!t3|%5Fn~6;7VJu-O@gQ~{cD&`a6$>L@{20={*Q>oS|Lj_<}a@`tt31*Nw~UJUxyQ4SSQ_WNCi)*GIsg z%6LI+%s180YP7z*pFvx^#E6b90aX0j%qVc>255hP*R5? zHyCY40N{r1CAp zrr3<@duQFTegt=J4g6{a!4cgUti~Yrl!^EyxL+2;JLJFjnsSVd&r3L$nOob;{A5gAs**}h5~IKA38y+W3x(Kibhl5~v83C<3t+7w z&@0XD=Hq3qKy##QI%;+vuTn8z)00TvBi<&h5OQVu5-)jJ@4-Z+d0sr2S^}oQsop+NtdMS8jiGC?=$~ zKXQd`^&RpPt-B}rP`EMCw1#?6G3XL(@hX@a?K$6`Q)$x$tU`%r^0EjrF``<8M)Br& zfc7YhlAH$JUoIEkL+Fi!Dre6;nV5CpcO>g_9|4&9L96Nqp+ol_k&!sN0Z}}nOF53; zUucXH41pC_DGxS_p5md}_D7NX(94!C>Y}XaNQ?4%jYvSInP2tuIfEq?J-j1330?No zqUZo@sOr=*Q&#_Vf==l1-`YF&$q#z+g0&s1y#2X6LEL=Zj0iTNmLy=Ez=sH{h!L2* zCJ*7k)oBXTO@!`!vFmiQ(IbKY;M>tn#=F-G^Z=%c!{;NG&+UuMet6Z3r$jf08 zSmfDR&?khS3lr#HhB_YUQ_!wT@{a{H8B1Aze;!uTInU7Px+Y%Ry?9K_89!eKoeO(J zSyn2RnTI1LGly6Cx-Vm8#qQ<<>H;qTTwn>x4v^Ewohhq*le~AmGmMplaFFvmm3))G z2ZkR-rBO6qyFiMaGy&xT!c6&WS8eNUR^PyJTo}A=S_M#kJF004DpTu|DZBkIkgl@* zKoUZtxPS!0{P(O*O7Tf(wD;UZVpOKy2l+EU1=w87>*c8oOcyJL5`k6&UUY1vd z7ah7M!5i86*Bg(4i2e?Ro%PB;Rs1|_JlWy-68_JuSyR((ne!X2bGJFiuRY<4K zVCwJeD){fGp{WJglon!-BS}sW6xCMC0boU25_?&D^K8^WVPMZwXv)ZpZeWdX#Y>ZR zPUWl$&H7x1BNh>(j(LfI0_Oven`#4A!w<986H@u1g}4;?e7 zmiM+j8MV%5E9*M%>_KE9GSmhY#IX zc~W4_UD)g&9Mxn~ThQHHlxfnzlH)@OA75*l}_GGW!*v3_pya=Ts4miDH=Wf-+Y zn5gND(n3A@7m6en|9P8Y@DO9R&7X{iFPvAUvND!7ET7n|1@TlM-0s?gdA`xW4cI4% z+*QJ#vtUfmH=$rswHD53(vdY#WUd*P-IViFl%{$1b4ZLtzD8*FmQAlAELjsjlf ztyhwy3jG*K0o@O`oHA@%^Ze9YoUfS|%V`0wg$ALt6*}@!#;P9NxzVV*#v^nG- zuWUC06yZ;pn`cn3PeLJw)K{%@hJJ(~fXOv}yD#mWj<1y|(utq+%=`NF z+*?L*9AkhMMVaK$@`vcw{S|6WbKaNK;1GCCGAs(nie|qF@tlf}ACU3TTu?tQXMpvO zAi#N}PT+)^O;WOd#9-RxA9x>v046ViiWSn)K92~*0xzZ81=K>-h=+O;%jgst|HUON zebg-P^wjtis})&{c_f(okEf?s#wc2*Gv0<5;$${=K`n{_LhDvM>ryQUJM=H&neHxl z{(3^w6!9pTddvSgILm!*!3i!>qu?m^76Jb|fhekRxa}@F$N?uG&Q}PXH!1nrm(U|) zUIXO%!y0okC~0xddSp%0?p?ljjLIF|zHa8gQ_u0i7OK?MBD^=WV*0BMG+sKYJee3Z z0rRCRwWR4v?A0S`hYo^^VzX@#WVFEDh|wI7FMSRu?`ct)Ewk(J_n|!N4IncTTm?VS z?xq`S0Ml$!wT#2;TN``7QZw?wnFuw$*m?MSV6@)qWljDz0;))Cx95inXrcH9*8#Rk zxYI%=Um7#zsn}_;9o`HV;P(r-h0=A&59i&FS(*3YCg(glQ-1J|GfWu%uhu{C6bU&p zSwZwYdIuTizQSqKQT6j4G+Sq7)x{SlGM$&k75O2XS4|Kr=}P%jbvIH*^#Ey`-eHJLq3&c!IBwEFktKL?ni;l=(9yn1PQeqIby4i; zTfvG_3&uQ~wc)*y`gJY>hHl1 zTE?>oVU++g*ZN(F0<}N#z9Hfj$mv-0q<7wWS*GSjAmGJrmt9O^nPX z?GhiRI@6}8LjqkJXWC55>3sX$p|x55ja#E*+XU*<2--JwU5kPuoxw`XXH(%geZRKS4&_`(5&CeC&e0Si^&BIq3D6~_ijgOqQkvr0 zbpAEwx5lkHLY3ecgQRR7l`U(tgBum_%Sqw~lJl;dK}$Ran+!dBGm zrnI(i)8>KWG~dNO-BXBO>w!&jneCaYHt9|t04W<2JJHts*99oiFmy>Or>mA|fNxGx zLqLB~o7UFq1uj$-zQem@J(C5(mEJPF!-^^20vAt~l~p-ZV2f;P@4Jq;kD%72QFuW8 z3k9ir?L*#>9F+LN#<*m-zbO%GbT$=h@g4jhCLG zd~3Q@sejwg9Q%W^cJA*Jl9odWLqL(+=iy!lCtiVx$LoYnDEoa*#T4{6W48i02h1eBG5<5wVPTR1P2AN^FRX?gbYa`Wh(e`jm~R)5)0xyS}8)Ne>q_ab27ecm1$OLX2AUd zTvirOfZ^t!!XSudeT-NWH%J}h=s&+iP1rGWAlYU3_WaGrvb5&phYCEI6ExvuugEZd zV`BCo03&7%mYCXT{o?XroAIf;S&Nj;6;EP*fP79&L8hp1HWD!4DuRk#O&kb4f@fbL~~|l(6HR&o&A!|DD06o;BVL{M7NPP zQ$4Ws=+IyKY|U1?6?{aOa;-<*P&7O>^GUB{es~EJ<|HjCCM8}u;Es7E<*XWz*7Ip! z!xLV~LS&)wtGN$)WDwEN+F@cIBb-M=1%7f;jVG78lN`%k>M1OFCz8L}Vh_38X|4FO zgWnGWThynoN!%zf&`}-?+Y3-IkNwA)g!B;`UhFT(KD4Q){=QC}1WsFD(v-kFLEV}DrD{38XK`;yF`FZG zsa~#k6^c613EPH!{1Ex6b2qprKo6ayW4a#KlkUDtMY)v*lmK)FRuG1~8OVym-QkJ{ zO`WZ99T@|un0})=lfjCDo9wG3BujFje^)Od-4ADlfbM$P(UzxT=3!Pbu0)FYdnHJ7 zg5ME?J1s`;U$HZ08uaK#eg$(}gm)E)M~QeJYXCU*Po5OWDgOjix#a}Gl1Le1iSXGd zR;T36^5rYP@k~_25Hv17%uPc_IYsSKULN_%xI=pSGvd^I+qKZVX-5rHL7fQT4fl9y zc^=O0X1IY6IxofqAup2yRf?3U9vu$8DlsV~;ur_Skk1=AUd5pPQB>`LY!6q#ym+^p zgau^&nHobUz^~-Q>WNHs1pI)_y%SJ9=bwFmez$3@W4Az}eB8NRj-hFOIksSUzy5Dz zhoSAFUqCJdUYJjr76+@(zveuOpkni0<2;x+cPklbCTVd=CZP4)T`>)O*!rdLe2 zBFRFKD}?n4NE{*FS9ffw|D4PA4=5F>$kVW_Euh&|mW>ZrVv?jC*J$8t+D}Tvk}HS zUUD%?vb`I-aUtfFoI%n4!IcDKy}#2&JcD<6p->YF?FfB<-6dW4W00f9o1k+);cZfS zfsU^>ados;ctCXJZ(=5=GsHZHK|m^Zoz*+iD2e;aV4x`1qi!j8Z%ShMdyoS}p|wEJ zMF-OS;p#QJEd2&4kD7VgfqbJ|Mcv}CbhbFs)UCg6tf9PzU1^JZ3uRDY8eS3LZ<_!f z(4IxChs8fobpVYi4m1OwHWyUL3e6q=G{OA*S24glAQxtgEiw(qBR)(hf`` zUQvB{qHqFxkC;L#Nx_0t~;{Q}4C?QGEF7T;Bt4}PFjEB@7AU4#u=5;u!@ z{^z&o$^i*1aF;s7lrgZ%SvWj42Wo)g?I_vK^3jXmK73FGILZGaLc>oKsGq_Sk*{2| z^B(=Q6F;bXskro0*!~s*qk?{_m{&E|L|Ll%iiME`+kMso)FY9)e`OaA%ivX51i4$@ zNbuxi4UaM9{yi@LHlxxL*6AuV|BJKgmQr>Qei`LhgF^^|p|2%h@bg?B|f z;l&3FieG=@Z?+scxh$EqaDe{=Q?8gnDGJ@^r~WlLh|0zg54U_qn{0p5y4JXPLnY`) zbx=o^{-|e>R82|(RQc-uXK-0d%*M0*JrY^CnDFz12&W`s)O^g#aQw+_dKCGrTh$8j z%QiW%wdghcp`418@87fuG^GM!NQy(rU}51o{_AE;c_njUL~$w6U6K)vYAL7`-iuDE zA;Hvxek-^_Fla#1_!y%hT`t<72*Q;`3yButm_1~Gk|*B=?pLfMp8H`>suXNT1h8LH za}7Tr&y_51483JFt(+e-&nqjY$==6Gaj_(WgDelt8i$FQx>x9mgBBXeaI-OrTD67s z0rmcek|g#5ih6#^5yg(Zu?Bp`g6qa2#UfPAtlo)_TPSf)gZB~6Gw=pIYZT4ER{R6z zeyvB#0=ezTf|o*1sQ2LGrNbC$?O@pO5>l!mUQpjYeC{&+hQmx-&;X5N@upORCBzo6 z)QbHQ_xj9nTo6t59u6312?r|NL(;T*IS}r;rzOLw} z&K**SIh^_=*fvsQqS7kZ&hb5}zsj&sW{sj`2$y9!+Nuqm>H z@wpPCg@1%q)hU~jh(P5kuU@Q^`Y8GamM-?|Pb!3`m zl$yPY$`|~$qhgJ82tAyPIqp14PE6of+>(l5fLeJ8;ZK0iHVY{5I&+?MG`XqnN5@;g z*ar=-)DoEU9|abTcacTUT!C!ak1q3|-apVb+TG8R4s^6$T#ARh7>|wzR_1fk0J#Ad zdPw{FaJuZUaD^;>NlGB@7u>YPYm!Zh6epaPNm%Hp9#N^R>}}+k#+?1P8+_q^ZcE7= zo5e)i{AMs0=JJb65gKT1G(r~>O%h?T2?!_FMio)U;E?HH+2N}Ur81?*oWYt^Y-jKj7&0M#N19-1OLgp=A zY)SMcx4sw#-C>X)VaSSB!R+P&F~N{JmCEqa-D>4MIu+bwTG?Y=fDqOYzoHal2_?op zj}G4sKuB5BHJV+aJc?A`25}vK>KsXZ4`F=%6z*dBdOfwv-<)Z2@H^(0z@=HX&RpR8 za)^lWJ&A^QeJWknvcS@@I(6}9VhfE(W*<>waFRkk(jo%2Q?1Ov#m)}HNW!|~dp&$v zFH+U85|1&-j5u!Nb%BMDe4O8|pYyxw4{pK<1%F^#u_EHEa67cNDf zK@m4*3XrhYCSeu|qD#?+fMrErR$vN{NWbHDRfS66jJhutAs0x#Vox#6Jc=8#UKoei zO85!_E2z+7*cz9~Ekvx)%~ZWTU-SZ5);^BbV95l9@CZ*Awp-2#@EH5}(e(|dheouA z%~Kyp8jo|=n^#_E3^;xuL2r@C4`AAIV85sP6W5Ppa}y=L=flFE=95-8$ly{?9L{{p zu(EUb@(~~`w-ZSH+!?0T>pTEitoB|M4u?UFmEW1BfmCBnbFhIGoCWhJ8^=m)ipXv< zN&U|o1`@-g@C`$s=8ti_&JA2YE-I`z<*SRbTuzb^b$pp}B#iCxQCD*drBTkhe4ic8 zoHcIF1mJ`@p5tAm6A>O_H!~JgFEE{c+$CxUlhx4}s9{b9dD{5)Hw^6G4@);7A9x7a zSU4-){TIVddLapkvjiLNMHM0*9#(ZtJ^?3QdMoxd6qi5M`j&#@WQ7z%CF#tDh2Vkr z@-cuT&>m%nhr;21We#O^S%*Wn*%}N~55k4x6%mM8#g3_2A^dwK%nraD=~TU#9wS^t zWpTwYu>7_B@%M_o|K*CKavcZoh8D#`cEa^$5(uus)%4W}?% zHAla)NCsFl*$vE3B#1PvU*TPlL-I6+5Ro?p?59g6fmNvkRTS?;l8PmkrxCb+C*z9iSJ6ch_nu;L@w z$6ndmh7%a-&nTe=0FFaupdB zW$B^z$qsLU2|n`KEV)kh6O=T8FBI9i^-q?R=I)SCD{Mddt8qAZYf(&TnPn-Zs zeYq7cpE!;yt44!taJr!2=1mU!Z_DsBG#TMU$88@ajBpv66`h4Id0I7nY=Ln$4R5&U zx zht`~ik*xVj4fc8u?w^}H>R zjOC`15)-K3kyHL*P3ru@ceKe(XPDD(o0nV^l3=z6gJ0CUfC7V%(J$yszh#OZkvP(7 zZt`gBa=Ie%KhIoydEuNu=ytxr_2*YdqkoM6aF7sLn#chUApg7}O=VBsZ}JnMflu$| zNWADm2&zQ$)MS_$?R#enNBnH4V6K`a!-{Ns^F0RXV%vC5+r-a~VyCXFvLZ;xCC+D^ zTd66j@|;C4_p7Evl1wJG3<%UO`f<_J2Ea#AgL5n#*%Ijbef0{KpQ?-L;i%b6l*u`p zBfD78JG#xq%41IjDjm?wt)y)fW#HU!hNbw_7 z$L+r}@`{Js7W#Iy=B{|F2q2@0x^|$+6hspMu1=|!oE_(`@YWsesH;Z17Ha?{+V!bC z7s5Bp4ca$AAMVEv2%djme)XARlh6|=Nd{8P9Hpu>9Z|9CJ%{@4>{7XOJz-yck%e?@ zNrC^j`vMN-+V_5QC7-G;1zDrq5&2|m%J{J4zB3Y^1s*A=JW}NyRvR(P)>T_*c?D1DMPAYIZW=%VsE z3rF#E-7U_W!t2^MgrJ{_#Ts&(QML5PPke1uYI_KjIAnaE5dBcl`ai1cs)Q0vbqJR# zgUt$NI7UQ?w&(t?Qp?%#G}q#1f_PJt_Xa~TBbC7KXdBVILNs-b+Z%sLX_g5FQ@$C( z|H*5}mF~Bd62nVX*=>fF$x(3=p;S3^Q!$7I`$pyfmAAHu2d`6nrWXlk>D|AMe;a3A zR$^F(?Y(i}k?%-!_$ZK(VBwzsqEfK66r)TF7gcvIfc>=o76@HbF)`ab^UorldO6kJ z8-$*Qz#N6!6KP+EaF^@Nn$ZcQ-W@cdJXuwS8wT&S5p@D5e%x-0^~pdY`8<7%M$cnG6c;sBn;!M*O`x^ZsPnO-G`o&&xOl(2jO4bntv*EN4Uu#WuGBt(L~mRZ^fvO zOuj>4>!(lsfFe*q`AqqkvXJSWzh_Rtk$K7zsC8>Y?EXkUVej+5=_|UySlG#T&lfpn zgl%QayWsn9SPxA-N!?JL+d>IF?iZ&qwNElIi2S0p-O5XkMf4``bj-D?aWSqe=}e~s zha3h!dt)M}!{|4iMbFDa=-Fa9F2T%#FF0<~DzX!1jA{`OVRj zj;(@~SP6fDNKw%`JhhgbHflw7JLC*KU21=jwOo;n5(2Zb&oCwcfevI`j%zz*06c8x z$+?8+;Zr@7}?I6u9Go^Z?;gr{2xIjn)32>e5Ix_AQ0npl(w@}S z`tT@bJ(PNg7vl5PYa$x86^qJ(APe>fmZ#z^-1WDU4NZQ5zkcQ zCu(|~yjSbh#NP_&s7}f_^aL<`Sx$5{mnkX!IDrzK=3*ykEZ03Kiwu&imeWb1u-0JL zp%l0J8Uqj@6cHHt=SMZ@&6uoH6Z7*6KCagKx=3>?{pHCoC)_Qr zt~=_YYj!&ejlCYxo-HINznKUahi-i80C^#dPRp5yt}2g)(_JN+Cr)BGj<5xF>sVjU zRE=NCJo4}uL3|=m6WeGL#~V(WgVixFoyU=1ioDyZw+`Z^*r*h<(tC>wiK8&W*i}SdIzc7z*r=CPcW^gZY zC6vp7l3U@e2DjfP+f^%31Ch>4*EU!X38k*%&vg>Tth^Vq_$fWF=aS8k=TvZf#vjPt zq&`*jGpWWMS!_227^)K5!llN)SeizEvz@K1CiH#7_8=9uDzAmR?-|wDvEL%DeREcA zKOAnPQ$&C?v1CWdc87)2NJOcU=D+W9tAsH|I5U)wu`#2P18G~&xdqW=(ufJ|Ouqz% z5#^z%AIa%brSA$2XkUA1{7VEdq4t5bOP;Ti_Bnflrb7qg9abE{oVZVtytQ{?z;=62 z^Ne8oA2wdG;R-GUpT^4MisNeRnlB*p4+9vYP^||RRRel2Aw|0Bwln!iKY%;K1GVqT zm3oZXKMtYs-j1s4N-{(Bz6I`>s=i{io_ckl&h@wm|<^vMpV=Emao?>kiX9vl*VKc*$u8LU-gTlLc7q!BI>%DxQ7vdcvO z1>B}kkdZHNhHT$`uy1>(YGb~68u)4Xul|RYYG0Y8rXhc(m&2&yHgKAHKP$0O<4&D= z`AQ|nYdFOLCRbv_+v5SDKRsevE}@2TXnE=6O>sEpqQ1Qb3UOxQ0u%XD_0DsRf}*M&y}D=g zGzvgg#As=`CSlJ!QMz(T?6AyPDU7stT)>%E-P*2~eLa@=Syp3l=*6asq8BiG(HSW) z06>DzS99k1P<;o{&9Ll;sW5{b_g+77?05Bm`^FEuPFvu}@{lnk_s5<$j4R@-P1?tK zdszt1QU7p9v>)8tM1~dJdMG_IV-kV!RP=4f-E~iHEM-_WdFy@W<+PfYq2Zk9hZrRU z$5`q1D+TNBJAu;0%RRjYHc;UEiXquNFisd+#Hs~$uQy=(ofxJ<#!NXDY`Tw)(nfTK zz0)P6IyL>7V(gf|>0Bc8PoPPlm)+?kFKG+b(=~ zVOAGIy$o_O=Ud%shRDG@RH;zPsXyHi&>7XyZEZhH4p*3V!4;A?6tS+g8W4}gJAJGN zM1iLC5-w&GohWQF?-JBHaPS(STcRK2MO{8gD2@AX7%VhI_Vpjb5Z^^~Q2S{Rx-z6(^V~jI9-W&qVYv{lB zo~gI5a4iz)$@zuDm2P)>LEhF-WzkSLyb%i3%CVk5e7Q4Z@R*!$Lm1*@eoz&4dTxV! zmLU}%DBs1L)anC8;M(?dze#Z*TZf849AZ_D6&{HeQf#dyqeY=WpCyc$Q5Evb3VXU{ zn;E8gR2rkG`;e7ze_TE7{;yLtZiq1o2SjGg@T>X{wf1>m7fcMc%uCAiHCh*~#aQGG zsR*w2nQJJ3(P4ahQQ!wsj=fGYs)P|S((!mp|LfG%z~p^ANRq$qc-9GORlpsR|G&42iP8`JwvfqN z8&6SERBJ3)jgrm0(iM`|Gz`;#`isibm7YOkth3fU4FI|0((mCg3g>-)87t0g{R*^x zwuVuK?F_9_MTU~Z?|%dS4_8Z3Y46h0w3W(%&O74v? zqTvalxI;usCM!`ZeVws&05!gj0(=9VvS=~PbuL=Qg*Y=*iYr50*Cvkez}Y8*6Nu9_ zGsP+SF0mDpG9Zd%6l7CyF}3%Il+`@Bt%mxkK{biA<%4X$OW- z`WGKPr4?bdvXcHl{uA+Nz5U)iH&e5)2X^8}6=B0c{uWNPa}T|yIZ{-%mG(?3eR`U% zr^7daaghNhqgZr<97k5a$ctDp5U}I=;Y9WBCjb?Bp>MaWT_^gZ7J{@a@6PVP7Poqm z^czur9hKi)n6Xh}v_LTxSnHFU4PwgF(u#^t?8lovb*R3z$oht9@6=Q1|Ajw?V2kyV zgvzt7@=B=e9(vW0&x}~Vi^PIA5U64AGZ$i$t68fIle>8xos`inHmE~}sz_k6$F20D zYTh4q<7Y_a8+4B^^tVe41jd&F0=DXU3C>rwW@;X7Xn(fR>>v0?$Ym*1C$nG~nnUOG z1H}wsj`|ybYqqZBpRG!a_30!09#$CU;-NTZVP82@L2d;sKaFSx2;dh;@N&WPOhP~whR$@_a|fL+RXQ%g>F$i z=AJlsOC!X{_Qd>x>gX5Ivx!FU=1ThWTPOMGaVS1>bl*PNHPIm;kQiN(5K$sa#z(hf z0kF=Z3Lw^f>bb+D@OtKA&=%A$io@Khl~~kp=BOO4J6 z>#c7!^@Z|<39cc%Nl#dK2d4U-8EzYKdu&WK04mtCcgQQq(c_40xMMQ`{w~R=6tUXQ zRh-=V9F8gbXAs>*l@D7d2s!Y8KI5ubn+9@Q$oM;+jd`rJL&76tIWh;TyIk&LMtWv% zDNER1JyUYIrwwMJx80gX2s}8Oopw8Yd}qM z%?N+~veh^HU}%CMR_Ewq1WQza0Z_oGN=BXp-)aluHdfP-Nr3Z5tHGbo7j^`dY8c~O z+HiU`5Q4L{H;_B;GG2^7*4f58^fpFF2xAnjt75Ta=Y!D~G!qgr( zr|LzLrNBQR1GR>&{)49B&_a7@w(NYcFx&q55eMedJ2pvh)*NrPMX|kY@tsSQK4~qCJELAId0%T8Uindp_NKASFQfZs8TF>dI=jZLvSw3y$76$XrdR zneBxtdO(9vm92+(Ep7%Zc_0_t9ljJXntk4WLdSJ_!e~GuAF-XggtecpW?fjE7Kv?5 z*D3O$$-oqPl>HGd5?eg`zRm}xJMsJJ&r+1gYTW?CvxVNg!BF^ob|umIUtTW{Q&8~k zQ_Audj+AkT@b)!Vde$7z7)Zj{WxsG`7xL0ca`Et0tNx|04IQ@K zBx?7<|K$Gk%j%e0ED=9IupMv;m(B|=m6u;59g+-qVZ>PJmm>0zCshQrhuxbKA6XYG zb{{metUQ@6v2tLvHC}YSyl>3`HvB#ar9ml_bCx zZ;B9iDvc?gmT5umtGO6bQq-99`eP>1-*%4bPicE0SddH|XG!}7d)01W%M~8hscOiU ziU!W}OCFGLs#o0WS)zzQ6Mtwu9M$?_+URgQY9Mwy$@d}v6`kxHtpXcgV;0LYKgn7# zxRq6Euo9O+gysfh8EA_YVdEQM^ z!*1NV`t_a}AOCVYXg#Zw$od|%&oKx)AJn!FXPwz6DOjqS$cvd&c7YKff5yT2<%h6OdoN^@22$d5KC0;>Z6E&9F~O%GI&zk6TLFbT+!pc;ZyH zPc{)TiCDCLOCbFMYOLH}upxrt2MV=Sts@1>6he}ztkW>>()j98zlU67W_S3^*?&8h z(ED+jO~V8_4<_uYQvp62UObhw@fry8{IvVr4IWi86m+|*hY2~YE|0>7f?fz{e9^dtZJ`o^%*|rpnT1J!&7%&#W-kv$err zwjWHpirt&%rcIu&ai0ge;eYY}B((9(I*8H2c?~7vu(YXU)8M3CRc@fBEam==%9`MM zJ~VNW4`3(;Mx$XCg@9#y3%?|aexPJ&*faEtQCD%I&I*)aRgp8`-@LmW#y(T*Ug?1f zUBe|C3ta14NhEY$odF4|t$rhC@Inn>E7%I~TRmlN`kovT}~o{5C7c}GYR#f0T?Ktf+Y2--n{qSW)4 z%j%7$5j=TLD}F*V-1DTQPj5`(w=^Xs$dz!yG9vj1e%cH}ioTy7+ly^DaE|cZg9gHQ zoMGs3>8Ki~TT*&dqu5^B(u|B94|7fJ#5cHIKrm3cEWk83NA?JzZYb8922pU5mkCfr zs!H*LsN&OPDCIiAiY@)G+g|=k@J({eV3GGV{FuYboX6+|TNUo*eZ&^o zY%R5MnX~lkxpbnLA1NxiGR6lDO}(Prp{>yT%=>so@Fv*^_3hfj69eK}LvC3%r(bc@ zzYvI7i^w5HskxY-^i0I&lZu#>OKxKe*;p31{3RJ19^oqRWKvXf1}7et*O-jr7P}|U zV=cG80$`*92%DF`r5+JFbreTHiPp;uZhB3*eYWD~+r6#TQ7>CfIAyJyN>OB?)I<3D?4R}YdN%Yqn;ULT;nWL{R1YqaROuuIvry~1op>&hTkEJ zHenyXN6yavg7dV^fOU@_%!{8OkN2D85-|sTe}qhHptD?-XEg;@2*83I9C!I9vdVDR zp&#RT^cRBGG{P4@i5#Av|hOo~f8-1J)=lb#J1LP<(J$$668E+LDJAf<9 z^K4q0{lO;z!o3tB=p9Gxc~r6#aL-MF!+UbyX%#hLCaEQrb6YlVU^Tq~ft+|C%^3$_ zi_AB1VQ;_;5$Buy0mSZfNW>8;!g}IV-JFBJ#Ov^>A!&_MCI9X;Bj6Dja?TOdpLMhv z(~~{~a#)YxTDuogpfVc3uzv`>e5Uc1KI!zA5>kmu;oGX&HdWh-g za0-j5ei%B>EEw=L9=;7rV2x+kBy3%Ls18lBdPJ&}|MZ>)xtk zVSUpnA4q;02<%Qkzlv^f+L#kLnKoFYXh3c*e`gcjX+nhKlgI!)K*GPfZMBnGsi_gm z-C85c$7l=X#L+8AU6bpqk8*abDbU!vU#C^JpHz0t<=q;XtuHh&KDUXd*pc6ul5tTdjq?3PDTv=wS*);I0T0`l z!ei_m3Wer7Ss|B=r5-9+hU)v9@m(R*S@sk;HNNh}N*PF_)d^NdFaohfP}Ks3##znJYqQa(%}Dio&a^6 zESP%`Fr`Whm#K79(V3EAljwt8AH<4!m+@zZoAXfnVp`WM%%@!p!}(%blo5QlWe)1PQGM;gI#GR+@bsuu!C7)%hiG z>kD8y8>v}x9>;09`FUz-Q;0Ozm%*5c;#NZjHfrCmI?+>@bSnk(EXLdL-muA zBB}N1L6v=KtC#Phm3I^5m??XP)S$=4Y@7*Mq;et&I5;RX8u?#hW|byfV_HU#n>PeJ znJoQN5Z@5=THg^5>Hj$6{_F8n|0z1iT_@kpqYzBPU>czhZt!S`IMezz`%qi2-2;rb z#iW$8ED7M2RtTi~=x6@%g2W(Al2CU9X0f7BAj#V+BwFjd?+~7J#v7*~1;5|a@u#@z zc!PrbMjI&gPLgR2k<~-c5jQk5n1{!(f`wEshdP&2c1}E<91<7;+Y3!uMr=b8?)KNy z_xu}N!0AMv5|K?7fM)C}Y_v|L14Fos0n^C#jaDtMO2GH3K%rq!$-oo|zrUA(gR)oZ z#pUE;_CLiV@luw5o~A@7idt)RzgMtl3E6Np>2CC=vdFf4j}JNfU%uYk_N-pf|AZ;3B-Cn`yjOUbm&v3s8H4`3+A3L zc%zVO>`cgdtJ~78%8Or93YPci7(gkBDB>UeVU=i!cuJ%n8Y2Ov*(y~NjGe)J0Yb@5 zo~DcNWgwb3oTM_mX(FT!4spZldh@(j_EznzpPgxbF~y9FM8DP;RH<*FW8?(&d+FBP zq#%oLbi?`+l?KR!25>%)=3+j|A7eEp4O9wj?Q3%jtpVW&&AfVIkd z+nz4(?`Wkn`}rW{6EsOovFUI~mQdDeMQoI3yp3A;s9WyDDsEYkPZt*ILXlWG^2YlR z-CxG@B>MHOB>lmC`M+z#`5TU0gCc(+?8RA$tlK~GLivu*o~y25U*DT_m&^<>o%lk- zI-#4p+4{~oY;rP`8R53IWWDWF%F(53c zujYR_OwyvS1pOu^sJ>h6X}Aq`I|B*(^k5%L+>6v9YFr};VOZ)f51G{`1wa)`t71D59x7c}L{M}-S$dA{{k$Z4^kjI<6{;IIli)N|1 zAFHRZ>ErS!v{AEXE88k_8kfq6pmVS7<3A>4Jtc1n#djYH-HYwk#YeFAUJC(7at@f= zzIj#AaQ?0(4TQdXlA5Kdtq_JBtouh%<^J{y?R3*wX`OpZE2*rkAK4$})zoS}#4xy@nKuBX>E6mOfmoS>eSIF@fuoWL;U2S=dBV5D19heFCM$0?}CFQ4dpXo@U zhY|`;0F9la2IeI$IDzm)ciZ@&)>2;?ysB!pT3Q>6K%soB^9oA)NIC+Hyh(%nz*qb7!5xnfmAX|3PTHH`!z}16^A>H&*4X!= zt@q&Mr!K7~uU;+l0fcolx8o~BFZhLqyNR`_G4S$5DF@_N-Gv;7s?kB5FF#O%Nn|t$ z@21LeVJ_|PzTw^kqDk-;oHdDX=~kY%`UjDlMh^60O*1sFG~*78Hi>y8ShU{(Qi^=2 zP>;EwmDdUXVB>^a+0c@fby{~z{T)vrP4+hEw$~CJnq^k*MFT1m`a?g=P|gl4`QWM*HsgQ_&jrpza?$Gr1ae2bpw^2z+#~jOf+2#P}?h#O=B=X)?fH zarB*!)?)k3L)Bj>(0zus`zkbXk8fOvzr;2?ko}5C!jR?Cv0b`e_liIH-M)w-%W|1T z1=~kQgmR=3%nHyKvrajpKo|^JoyBZzwqns^#ii~F(2BPgQ8Q3jCt&yNM-_WC@J$s% zKUbiZO&~OgjWwg^#w`ZvS1)L%`@o_D2>w0>JLF=O41S*i@)FtoE)a_Fy}Jjo*6Lld zA-f|*8wD?fcA%ZqAM_jmaM6Q1vXr6`3k(i4C+6;#B>F?rsu-H8omHd94*eW_XL=z9 z?kS>nlN4uUlz}a+X0I|-lO1a%+@cuSQHzZlRq@e@UwA0R8rzDyaGbF6D-z7@$8a*t z=UlvJzk@dilJ2Gph`exyvTNInj4g?MMHY8ew|-G1tI>^l8;&@lA8gT0b-@MU;q zNX9Z*1L|fXRD84qzYBMe3`5S)yZx-3g2q5bDh+FHV_|OzQ>m&-9R1AjE)3WthrJ&V z?b6`SdIQ0E8FKnZI=z(mEG+9wh2I;%n3=y_O5e;vcY+`!ss%;W%74v^NvzkxDwWzt zJd7ziCn#cvt=^_ib7xD4iJWnsAKQd2efqy4uf%$r2e8NMtx%`1_22I1z7aU1-wf8s za^31a+`P^D=#$^m;#0K(*Qmd?7qDDk%QKs)@Wtv%K|T)qW6Q&ZO~fGMhz0Gi3aZqQ zXNh?S%UWzw4G3Ss>92RZES-bdJP^$mlEWNjng$|*q36ro_gh15ltg(s)AsS0%KU(>9YI=RqZPGvY5 zcS>>FHp-j@qF?ZC7h@{qvnCYea>yh{6 zabMKJU?s~zh2;K%+`SgZ&Op$&tlOLNP-cK9azfdzS~0QK9*Vo=(J}eVgME0tu8qU% zSaELV=g8jKN$a8?GGg@plV{A%bK^*%(rN|4Foh>cWg;|lqLBgEd=@1qkDNh&bsYZ( z@xD#C+pYJ!y4k(o5JtrV`QE-f}i7~5LEiMe#i@&0dUEDcBFFzmhOmm+KuX!Su6X+0pD}cKx=AQ}n3MtNkMBKu?)U=Q`NH7iuRo z53>uj(A?`u>oyFzc}D6$xg^QGY#&k_K1hID^oIwj^~2RzvD=Mh+ig#nj3Ci)c=RC! z<+@0QL6-L~^G4dN#kav(9hbq!|4}h?On!8V5-2drNeUo0-t?sYql?&j!P3K!G4v{h z^_&k2VRuIZW6=m1_r+8N1aV^9F zs()A@YrgDQ&$$M%$i}H7{)du+G3WXWNzKn08bG*bLDkC`b!@Qfk4CkCbBh$YXUfR-O;g&-EY6hTD&rE0%P zrdA{Z*8El7=FB^+>VGhaj31nd{%05L`Akg(#fj2gkV`W|?4q5aAh>M4CX+a9Lgw}) z(rA%v&6QvXdPY%4cV_f9iF^d)_kE9X=^IyzO_8UxJTo5~$T?GT z){ckWk=J?J=k_{r5A8aYorJ5-s<@cdQ8~)|HaH%Pa#dFqKKsh7x0^cC#H<%Snfo#~^F#APY!3%phG_TZH_w4dzffoG9np zBMk?E+K<2l13Iv5QN_;uhcWuo7>56 zy25LIVnkM5Wc({SroI%(7BwxSs8B*J^fuyu5IwY@5EKwp-*xg-M|6&L0JO5VaVnm< z8@<|Y0khT2?Sv)Vq8Zg1WID1r>bv)+-PodLjMj{w&pw~2{rU)X@ev)oPz)A?ba+Fj||WcH53k%v#_ z#Fy5FW<7oP?0URbn`=((As4R=FybZgdTLo@ISLjDXFrS%Dm$r8ag_|ga8;&3(}1eg z41kGx>KSabk;ZOc>H@ows}0p*&dNB~C>4ftrA5I{w;OjThoIvKZ6tV|hm$MRtwp@* zQOj);l2JducLBydPS>%wLn&@(4R)a0Q<~x;-D9C+OXq8-CbGRAp1+C~UYyX`zlm2c znLL8D&sp0R9bIGF9F}AHiZOF;-3wv>6M8!Hhe~O|&@^)?Efs~3@L-_%=e#*c&OOz% zoYHC0a+4BFpr-d$5zaZ7u+*j+H*%ub3Ht7v9RU30F{q6dFxi!$abkunTvB?<{uTPa zl7pQP<`EGo@pkpsp&GK(Kg{Fj)z`_cG;`;7{OQ7k{j)~B%hqP5mT>6Hu!Awwg0gvr z&E0XCZ(PBH2~JhrP+#pA0p!DD*ajZk?0&rcKC~EnbhPg4M$H3R_rxu=P;|0yYg{N6 z|M51L*!zeZhz1E&_piXd>u5bYC+%V`R6zT}s>_VYUlEFFU3#6beRa6j{*1`RSyVG3 z4HjWYuuIw0;SPCVgav3#lu2s-SY?t*cR*i7iR#jUN)XjNf(cIJIKn3FuR=R8#s=se zq$qAlD{_&}fME#O8bh!l>upD>gda44SF?P{vKi}?YliZY7k*{6#mZ0oNTLRcyg2~D zGtIiMwphZ%$7*GHwrCiB;7t02c=d$EwXhXPcp`%>NArkMhYyR7JB-s|dL`oTI5$cO zG^t$$NC;Dr)A$1{o~0zB1tR=yT{>a~eJ$3mNt$uigP<)?&q2Kc)M85X*+vCpKbw4C z^{3-U8}D6%DUl3>H@SXUZEeBYlg=Sb5G0WE@X!Y}77%)qogFe!DI$eE#G_ga=0H03 z z^9>E5@M&d=_2D>Y8Y6ETHFd|n28ffXLl$Ss?$fxYB&G0B7pR$i+ww49+BQNV6el)e z;WwuT#z)y{DyZDTFzVC2;q~eR4R#>^TU^1}@T1z4Uc%ZQol^J@mIGEMojPE#6|~cZ zE5=)ft9vG4>~Zb+11EY+jx65YNLm5Mdr~xKUTJG|q=wUOZ@TX0gvZ<(rRnp^uD&(a zf7F#uq8Om5p5u_kBjuF6RWRs6hhqEq;RgMp+y+?ZYj;(W1`Cw%{+r8R-bYodEtax@6zFiI+?nLf_JYU)oPj zFgqMdU^@uU?CyCUl=nTA+U2U!!mdD^)f!9!77U$Osp>j z@qn5P$wHNZIU5_2OHI8&FbPtB#61mX$mD)OWXaA2W^C(P($(Jm15!kCf81k0?;6Da zE?I=8C?WGLwlEw@Nt_c^C7TX+um8BD03?S`uOE?a}eK~GP2 z$d5Hw+yzR6vjL07WP^)Iv() z#E!igL#PwL7Uac+Z~O;5#vw;d#ol(@qb%SUWOU}F*_dQIj?u|6Ypk-teeK8$zCLLiWu)9V)8Y>322NF^6Jjn*s^e4785z!{{aqy^?x z;Qjgl+l|%6Ecm;vhI__P_-4sAh@=>?86dv|tqr3^-bo3N%VtpSfWqsd;M1wd{*V7LR-l7E&(u6=L{WBx{ZzKlrn^sQ6au`x3Z!M< zJ~+UqGGU#(pfrrqSG3k8Vf;ypnr2?rcrH}``VPgb9!^y#W!5%A8!Ptr8#|jjuJd5MK zdZyWMFq$t&y5tvUI^h{%&ZXs;xmmpv_v`esWLhSoxwX zmnT`f3~Ue~I|Yn@$L5rdO>keL(W&=a72KH_lcOY6-PBVWU$;kvcZ3S&@K>W#irxa_<%2OXm5 zeQS34C@D?xm`L&rf|a@^I$|roqFS zx)a=o0jHuUyC+t|4}pB@>A$n0jJWiz6-M*o0iM#_O3B)Z#tT;R)B)dj_~SqgyCBZ>CX511TFd>12g zb4F#bix=o-Ym<>F&r0ZaT!A$Cw=c}i>AhEqLy|>_^m|UMI(0TiaDiS| zrIhhguqKGw9Z1>VHO+J-ngFQStjDJ|=+oWN9X3(k1ZIryA5Sw@FwzEcqLMX%0|vE6JTtzNIVbqgCjybT~KQy~{n8_f=ly{rW$e7p#Cq z572WJPQzzYwRl4{arm%0SJIsC7F(Vo4HB1VUrz=5r`^U|CsLus`X|}!`?9!#F;gMV zA)Z;Jrqr3Wl3S8qAv^1;Ydt#W1baw%TJ-}t^{o4USXy!6UaKGh)ZObQf{T2(1k@O* z^Ef1OJ?ZRr;Tdq@-rI1%q1vgLV8I;218pQ6ywrJuj0UQpus+OBzS*xy_lcv=Vow7) zIJMIm<{2=J{1tf-)oe;!|3NCw4ht;lwEQSse7>mXUOw{KREw)v31=tBs{?PullUS> z=5E66u7vXT*Ro_kauyK#$PaPCGRy-@8r;atP@h;JvXLa9fWWMmDn%hF=n*cTTV)t+ zRkkVK+ZU2Ect)?IZQcldd39pGsb)W#6g+?CNuH<)xyXo`Mf#gAeS*Uhp_3?DThG$8 zw5d)#xC+0D_H%|)by=)HNbiYNU*QjR)ZHxbWTlwLrdHctu?0UGEBqm-4xG@*DQIY@ zgT2mO2BK1Ux2(9fFQRRa;qeX*m8>nR#m)Shq1N;yP3jqLdaWk#Dj@P163UZ% z&lWDl!}{=tJgqAji#+n-^!27FlA1+#sX2`;?*zhXqrx(&F&ai2RKQsw5*TQmvi)R#gOXkN~{ z4Hz=f=)}lSy{>KYj5nsrk@%^Wb%hyFE~3wWf1TSQ3Q|LhbW2AZp+~BgK_@-$kM3F3 z_pZ6`Y6iR|EB|OgWTCT%ZUzvWm$~>pOsx@f#xV54$4;Hhiz$;4hg{isM>pIVEczFJ zzXvDP_$v64TfP|NAdQ{RIULZsd(ja(9L3?Y5fQn(MfO zm}PVXjvT`B;I%miTa)e?Ms4O~g!KK9Fm*&v>z+W6ujPj8&gc{Ow*A!0u9{+%aeJEv z=DMjY)W}2r8BWtCiQ^Eyqj?t?{7#cZdnY_%KE$ee7fuDO2^eh6fc2X#FPh%#U>%=5 zF>P!fh&4_qPdiL(=LXXy5H_mBYyeOM_d%K0x;h#2j+9qha=HQrsN}0;4QB75AZ? z4%kl4xh(1z$QzNKkT04>2f8*m*~xpBD}+$XNU0*4hfn|(JaamQ*s*AIB?12j2I|wf z%p4WeqXyV~Gs*84GF<>s-h6q%e=aqGcU1)LV4ql%rI2eYqgm&Q;A>3>6KT(4cYSiP(Wb25BI2=eWlAFoxtB=~b2+|vk}DjLr#I_38M;!$>T(i49!(>1J9 z{`48+BG5@1@MfRM3A==l2_I&xXVC+ z-!$#-26NZCihn&1(rP&V>ta#Gf+XD>-NDAHnm|1qRO5YbD*3Gr<)@4SsPc7E>Q(Vab3Zv8`Ei#ZWKu<$h)Qj z)F@ZO;@AVRa7dQ(SxS+NrjqS0599LzwYZkrzOT*@j^w0SWK}2l*VC<8u>*+4nACh9 zNGFEn%)lPB%IMc@f+QvRG#Vm?X~4TfeJ?=;+!5wxx=#d8t#v5Eohg<3<%I6sPtjjy z58nU6lJU)8evfcA4$<|@x#7c2->(m#Zb&DDd-qIVw&&sS+2W za^$a5=?Q~~5x-djb*WbMuEb}}#;^vf(bbqWyIODM$@DUp;**yEh9{IHH=+5G8oVMa zTu@KG?q3Q5>A`Znv41NFq=Pd|1jlL=Mif6<8;Dsd8~)Q73Ua(&7F5WDoiCBMt?SVm zku2m1>cG<|uD9HI2xxEgdndwS-n!Kf)UQsBh`kfc0h#jmkm#aCo~;*OvxiYAN?&(Z zjaoK2HL<2Zld70YIl)JFZ^VLI)DCX&zo;irYNc<#W>`NooNvc>GIL~EzQbPJ7xT?& zim=i1ay&IK&G)yvta#qpfz?0mHm`6TnvABv_*y8I_a&CSfkI`n9%Zen^I5%Dh=>&yf_+vS6PsyIQTCVL?gF46)OvKTGd~F zfplRFx24Q+eezEhu0IdT(wvRL>(~gi^s)I0Nyh#cb{lT1bUmz4UQ`27bj4ts13_!s zGNLJS&?Ki1^7U4OIvMT>^5tiQwGb??YWi6Ev+>wY(KMd%x!Fq5qM=a1bvT$H!Lt=&&}74x3s z;Hm6wPO11>NhLXS>pH3yZ@zKJBr?vGVh($~53bg-`9qFm`jTGOCx>?pK%?vj1(k83 z%9rTDE{`UUvDN))ng^L2Gj#PCj$DLFG?#aq0(LjqvIs*bnUb!GvYG%+kvD8%Qxrbw z(v~>8XNQrGTM}8DoX36Wp}oPk1y}}KPJ>XdD7S5y{Sf>>r?y zP*|8{zngHfXpIq0{pSqb_7I4&*W(a1?F2)>h@fN!)bmG7q!d;JL;_1 z;(-ip6ecA8x>HVJpFk{Nx~KXv=E1w`Upb2`)maTM__YN>?zR>jwN~^W8l+XyNE{cm zuherevWG^X{jNZ@M^&yK=DATu1uo2V``Z%VC6p+cb&${`YT2T*Br%z+MUDr*j!Zb2Ax) zRZ0|BQQm^ec?nRKBJ=WWI|^X3;uQC~*I<}rKZGpF^|^dl+6CBp$rq_7_tbhXEX0RHyXkqqB_&uR+z#nte?9a4?^`!$@7)j!i~yeK^l>0|UvtF-AUlI|H4xtI93-c9!@8CY=Wo5AES zuGG_Q6-r;YIT&^AeXtwb`MY#&T&s8xw~fmkhqWR}e)(A7elLW`v!HW*;3#b)nDae; z^0Vgnyeb3H%%v7>{xfcN!|(~DZ*!{{o5OPKwoHcbu&I;3tT}sV*-{r(*{+gHShi!Q z@#I@zUXoaDC+rVpio|+E2s;zWOq1 zZasI0dK=H>Nt2tNip&jlO$@Cm+Xye}4=TU=@ou(1y8U7zT015%0#ObVwr;R;yF}3z z0K)T^x-l@xv4Vt1Tt{y$hofDFQf+w?s-`|&NqZ-fW54XwiW)*-wS zex~g0L5_jIb5p7&a?M(8=`JgMy^>^J)I%9$=e(-tfK-s78L%lD5R@4hGATxpdfWa> z?2DlFDdWVLaRFObqzX-tz&k)_RparQ^=9bW(v&S*cn6LTEX0#HYUz+L!13I#qEg`8 z;!{FXE7|zeuvGv=vf}&w$vBK^Ob-h^^dY&olzu^DvOTh!J@2dQT8#XdetQ4WO5_`S z83P9)P;%ZQ1n3S+d4rXDq$E*J0cN#9g1aQLF@96tPlRHj3w@`a<|uRV>ZGABKf8ni zqcL1%y;U)&od|;Q(5&Tn<#P@(ITGfeGnho_X-5tqq9YfW3hp&Dlxl$Kx_aX$U)Kwjq+tkYU_XpQ{q0)& zIMh-VLSQs|qiv}M*&EWLdQFv~;C=M{Xo5+?a~ykZ)H$B{^4=L8`|8}l3d^7B4|uHk zV}vWRBs0M_up2IK!b@2FKS4-KNYwiXs|(0X~-7IW_icZkTA_DRfgSi6Tx;raWSGI+kShs}rYe(jLLZmy74AL_NZX~<; z@lyr-?Z*Ef|K|I()r4j&F(aLbdT6BeSoi4Exsqu{%HgLl%M+veMkMkfM-!x|W)K1p zCA4UdNQU1D`_s;c;8z4dA996-h2le=QmVS68sjVK+397=WV!X1x$PCj!tZzDb=98P z9X_oB2Yt73@{U{P-^^Ksp;BP*$~qe)_Zz{9|vmTMQzGQC#mJe*4Mpv(`zB=G0w30QBDd>^-(`W zrQ~l^z)tAV?lAe1UFVXyQ%rH^-Pzfxp0i5WxDFliO+tm)oXFDCRn>LE)63L1*hxXO z22F+|PUsuibvQ!c_&6oFKbOb4t0Eackb|@#)k?j%Sph(+=>0x2V)$xX0zy8UD2y+t@|X|3{Et*-n^TbNCi0aJW2-7OKGd<>+!Aqy31sIuz-(lPu)Bu9~pXovrND3 z(3$qdTA!c)9oR?EhS0?&2$Q9TAJQHZrX_kXRuNn*2fqv?-VHv$@V+<7Kh#~`II$#W zL(Z4+ag`$E?7}GpKZuxkf-)p=+YmL2g@pVgxF(k8l4Ia z^YV9sLZ-*9Is5Nt%`Qi!6IluQiABz8>?8|!%)bHmi&>=!!2QI_TJ~=V$sA;0x?cn1 zqAUqv7e6yxeo3)>i}*+4waUT_kG4lMj2+d!v+`p2+D1i#O@u(XRMe{)v@tH)f>@L+ z&M0Ac&Q&(~?7YhxD|y9W_z)8Q)e9JndyE$ZyWnn~pF4K4AsBNmEB3DzGb4kUm{AA> zTvxb3vxJRH_S8VkH)*dRISan`+_A~KVK7kT4^^~1RR3~Z+nLNJzw4&`pNua7c4r97 z{hk=4WOS_HaQOV+x>Y^6E1;k;fOn}hTBUx(d^KXUvp6=|{PU{eW7t*(D5~4F++a9M zAo*ebFJ&GA($)i@pNy?g?SSOx4i52DS8i(4;QF*I>ZdM+9 zdBQ7yziVPkx$rWQ7~a0b=i{`4g&nvIVP_7i7u}F~-N2@!U*E!OV2>b)J5|aUAO=ic z?#K<&uH?{fL1GD=o8jiz<_rVAD)CztPqVF>((ZT52<6S8YYxwaEH|WWsi*?_z6122 z1}%aTL$L7ToaNT!>|a*T0_w_aus-6gATBm?$eIQ+j#N@U;3<7137#W_SC+hbYrwaB zl!3ePGI@Gwy|`gUCefMf|K9Z+a3EtkC(A9ikjr)etkD3ROU@;b#ESsQPC{`%E zo)51k%>M#OA_6RZ1?Kutc9ycdMAu?t{kXu`X2|)iqF-U+7YLMigvEV9z$<72s>F@7 z;xe{`61*P*M7(Kw2|Eir=s~CttuY3iM6$&EHoaL%h^*Qg^z(Z2DR~HC)Fjq_=_aUo zq`BAa;Vbs8_%<_l<997ZJL^bA_)RQDwUCb}>>zAx_8C6juI97h#!qoT%WS!1qkDO? z2El~+kyB?B6l&??@+nMc_p+HT#kyR^Bip#4f9m?iguZF5s|w1{DS%Q1z>jih;#5!J zdNqc=y`;9=RGt>c!wE*HsHy8_n8)rHg)o6`Mb^U?9K-H&#G<5BO(ws4>=7+5J%ZIf z!zpuG_I-GkFrY8l)kZAq=e#TvAXUSgZ|Ec7 zpwxzYL0;!`DtijwSL;#dszszP-K0m>q0W*K42g1%!Tf}ps}DVIUd@@XA_?yCPF)>p z5q*jwyDZys4aqC)pwvzGSeB4ZvM3$;M!h7_gDwIb8DLylY9%|~8+YQ`P4vk2vh(3| zd_jZ4orI*E=tlca1_#@}p)nw>;Fg%0Z#0So(qWk0xZL2g#a#jd2@3GPT6kOL4>POW zl;NYX`!g#9HsE!A1jFgM!m~StItudy&RnKx-~j(?VC&WFhPqdI+^iJPWfG+WicXZ( zen1VND6o2EY77M1^n<0KYh53OlRTo|(MicLJqNvON2TE!ItGSicO2dTxnudi_V>DG z7J#9O!@`G-6>F9gcT-u-cdrwqWloxDMgK^gAtAO_PxRz(gzw#pX63{08DTky>8(N? z0G@~i6Mt=C{x|qo z!y4e9L9tM&`t~H)r$)nbyVVD%o!K*AuUVj68b@r|Bv^+YehSL)k9W%LbHVaqE~@c% zW?_aJ{5NfVKfnYtpxVY-FF^zB&1%My2ZyM#s=9JKLyBh*5TxCnYF}}CS*(tUQ!;i5 z;!@hV1xGbZ`u*)dlAA0;uk5#Qge}@2l)4`*{v6x+HlXI{$huOi%BS@rm;>7f$jU8F z+d^(CljbcG7O_f3|4=>>cgGnoz*hg?PQwQYnS#XSUGp{OI!Q7-g5&AJ!V2>@Ni_3X zwYxzCPkLFquyL=~*Un1s$_~xOLvXP{zwK&v8hYvoa{*Q@LO*~iB=fv$H&H|Q?q9_A zkeRmAW?lhZEiVIdGEwD8aiU(hQ09nxFD_nrwLjZMMfokOw2F^wkM_x2)ZbZ9({Jxn z0m6ecqdqe~F2LB!2U6~!SD#?&Q&Qw zk9K}0CkG{fq4vzVObR7?6s(jEFIg0d4TP^PYf4BnDO!0Zgiqi0I2?F7Pp-Hme;`;nrK=a z7N;NU$@kQ3qcd036TTeTh+so^EWDxV0hC=;VtQUmEo%f7ND7@@i3V8_%Wk=J1s;L= zVQV|$ntjO+NXb3t#q?N9NlBK<1jUxL+-<^D4cNH0}*t!-W(+`;m8xkn7uo{bAD zpFl%H%}z3+4b{Dw`@ym>DsoL(%`_BilzbupgpqtKJo%0{G~r;p(5WwH;qu5>tvmms z#n@1!EA7$M`%@%$3>lmAd3Uh&Do$2R(cWaOH54s(_<2$k8`1uJ5p~O$`R+}bkG;+T z7tDaeZfJ!kU=P`?VjfXJ>uuSJ;r`EP^Q2qF_!Z|zXT~T+;pypMl9!pc2g%weBdLrw zg~k!YYzF^IgC5$Z!N*-qu}zs{(!&$oY4=adnAk1; zH4Jn=9CW}5PtnGw{qZBp5d1?XQxAZS@Z(qCzI6%&R znL|WAdAvvN>-rlFJti$8P3%lE9ZV?w^1qF0LsQ=**(D6DbH3fgW~D6;VZRf$5mDE{ z*Qu!%6>a0+Ynstr#FgvZt(xeXN;{#T%$4sg>Z(Su5Q6Mx*7x?V2X_}y4N-(L4gYX+ zAH|i_)n({r8AGpTrB|;U2=S0{`?S43;nea1qTQ6a+Bapnj02p-o}%;vI4_|YF4slcBQh=! z%mhB%ihoFDdKtG};XPylK|6#kc*OVmQ4g7$8Ql=9Sh5xS4?<{kC0@cXd zo{01I`B0R{=C-|Y>#&8PMqh=eQv#ci_Zuaa%A%T)S6wFtc~yOH%QDO^^`jiy*xIEOEasov5=hI#q^oAH~xXoRcVin}eJiF<3}c6{gbq@NatB*loc z<{sx(gI#l*>^V1Mt$b^r~)0VKLl5?@P|jSe%)kZ>yVvY`GcMnkj}=3fb~^gB{k%$ z!|}(B9MXXL=6^Z_3;xmCpJgI$P=F{c(ZyMAftBSPOKo1FxAT|)RW*^bfT@fJTEd40ZZ%;Vb|IS&G&tQSOo6JQA?IA{5X#FF4 zW7Nsy)vC*_lt7^d3K-){fzsc#nxVN^zBRN}E{~LYD_{49$Tl;@)s;6JS7Q z3kV!z*e%#e-Il~t3GYC3vcxg|5{K38u1}>1>TBk_Ut8yDnS*jQ=IzXGUz?` zJ37~TUF23A6>vJQ<&#Ypfv_Zu>xZ}vce0e%d$@Ik@tBcEBFftGaL|DK{&p-{SveKa z*YoQV7zDFD?g84h!TJ$vZtxpe#XRJ(idL{DO2?v!ll$%n87Bql5y2^u?i0caS=?vU zM)W%_G{->=U#gPW{($Y!b;?hq8H%R-6*k99VQZ@docOFt`3Cr4VFGQiN?LT9g-{BY zH|o?nP^vo`J?tGB6rk?6MC?`Hejv!so@t^%i$z0Yt=~hdS!L$EUjyAUTqma>Hs6eg zp8RzV)+R0_>ar94i#>SeL>{tQS?V}Z+2*$yWa@b(825HZ)=GTMhuV8~YLx%IIYULM zLv@7!NTNm>8scsUpX*(zCkRWm9APj$wkL8B(xAM#G}}*mu~Oj$xg8)B*2?5+xYbqi zj_bom=Chd1vUPZ9c3VX2Nm+{gpP*?z*w@RchC&EjM7-OmzVP#5xG1bvAzj{sqMs10 zZB^(|(zt$(+z1%~!bV#vuiMVP2OgP)C?|{gr*}?Fenl@B_S6-vD&W6qvWq4Wpy|9& zGR>G7Zhb*1o~YNyTQ1v`Nbvldgs~V?FPF=SP8jjnA2an%JZ+~8FGZW@MR^XQIfIY? zSU8RDYDVYqCPctbpwrXekC5TBBScMx&IwS{lGz6($47Q@JG5Igc~mLkT3}A zfGIAudqJjWAxHB+)GM;_7)_1>zwgw4;oJzU4fS`2B%v=--0nfq%x7Y}rJF0@E`zl= zqVfb=r|0g|r32S_)81bt#%U^m2{}35OLCknY}C=#11vIUO14^&yBXPd+ zX_5#`En;98hY0g&M_qI3B=J%=`rH>qCakA^05R?I%GI)f4vl*u6sUf>x;6d{xo+&GM-1fBQNeF>r@cHDX^iaf##(kF3 zPeaNIx9jX-i5`U(E`&W8K`b$YsH3%xh@Zw*xMVJo9_jSBz5+Tr;NQHIVST)i5@JEY z$g|Q305w3$zlaeu=;dzo#MOsN&P@I=_>%LC0*|Y%ZXn2)_@cZO|Dr(4qPid=TkkpWPow* zmGF$#Ap6dgc}M2>+lk~}SOvrW?sdjliJYIzCk*k~4%mV9o5ZfKl6ZRq90VzP~z9lUKL16iRB;)aN819kWEzQJ6M# z$p0d?`nrIHc7=7eaIA*t>(VC_21U$pD;IddsfmYi`7RdHqkB@Pk#n7+VPGdU)^D#S&OC9cWA_*dlKvX};5t z+x=efPvDk^6}6S)ZzN9I68tEtd`mXQvW-CEa)^?|qOm4kfy~l5cD5@w0cyJypXU^f8ge$d zb|qig6BUCUnYQFPDu>j7w{=R%mkkQhsGh-gx^L)pZdSy{Io4PSI&XD zk(T>f->J&vzlG-R`69wZIzfs>Z3pl~Yc+wRdvFQXdEd1QS6pS@AvTqK-URaKCC#N_zWOh+Dj$W%)Va{O<``%c3 z;M!Y<-j~{4b6Y6uRkGpsS%t5|1HU$snwC&ub}5J_DW-<{%$)W*UMp*&_@N*QYc!X$ zIknE{g@~-f(m&!MDJ*}|FdwWg@=?7G)_{_S>og*EIgmd&@iQ~D5!BsyZcB)qH)Wgo zdPMS7eo>~5Fx!5LwHSkdqlxN*7*E?XmZwNxETjEUE+2gmw8dE(?m z@XY!jEk@u(96*4H+8(gDsZO6|D1$PD4kYqI#cjP7*dJdUBEcQS#x-=~_IlS+H4Gr# zvz=&l5H_hcOt(hWmIYG7?gO6^enT5kYy~XOaidkEkOLZWBX~;158=|af}K;8GLFFx zI-=kX=L6qO$(0yHBTND-K^0`IxBgCz!$majLHxu>@*lt=4{;vwEV0T3 zd|1G?`ll-%4CN-2U2QrK;#D8@>OmGf+SX+9sA0)&nx;>yMDm99{1PxyiY`ARbOer^ zT=aO+yv%v=ZzL1~uPETd?(0Ir<>CTaTR8utEG9pCZU2!cYD#^}u+$Yqjf{n=N(-=x z>%ut=J*)V=KxGkDdFP+CQD(-~Hgwqx68tFSq~1-baTnuLYuZFghsC-Gr&Fp;>+q4p zMpIKLDJs-vix{o^pFI;8gE-k;Z;7#>(1hF~_4%i9KWHbze*?e7tA?GQ3C(2v2(6vo z7$#X_?{*?WeFO+=If$0bpkBJ_v|=HoA4Hp9Wtn|%n)0(_4U*%-WSHJh~fc>j*HUs>U0fJjv3 z`p(feS2?4X;OVQA%0cF7V-KjDY`+wvg%K$=dcV{q_owudSM%u~w^c-->d&IGjGPnt zti&0^p8Kd`pC&H9&|>VchJ|vho;9a&AiwYTI^lhnbV+5}R&_11M0Vrd&z2KaWWTs5 z$&4U1x;Jgy!gq6-V?(qSyo*{)7<-^6e-oS#EH@gJo7PWdYUW?&_~YrUwlo~ZZvCKa zSMc7Ct(;-ThuglvxTpw=cfRbi*e1wK*9cgk(qd!~$hY&k{jJv%{#?-qJqz!dg{&on zucVW26GdDE6|&EytI@Q-Uj&)BV4dq>Cln-JC_Er;Y@&4WlN_6ovG-qJr;T(50XU<;V#yZPrhYm8TJ1M0`5R#?Z6WK{v<^#vq&XGp33G*79|Pu)ty3h zpZ?-;Y%KR+=LwADFLc{|Q1|#YG2x;nh7)X*@2+L+33C;Ae70S$Qi3IyKAt)rTyxsHviUNPG zAWq+{zpG2j60T6LL(s?zsAfzY#n$@I#Z)~iGd|sS%4bAkaRcj4_eD(V+G9*&RK^ZKC4DNVrHW8?C+OA;bKFptQl zs1E09b$d}wHexnG=vxOGt2s}K;yPD4{eD~?E_)c+{!P1aH;RB^6LB`ug@i<>kLUJt z6DyM7&(+&l5Nj8`7|JqZ8=F}06y7ui@?9P@Tvhby2tJ*!+wg_re50J(Mk&B>{yw*F zr1$HS`djPh=p#@VA&!xPTH~~?Z z2@_d~zcJOTPv1k^oiP@@_;I*P_zJm)5Zj27qi-iSHTU+`l=1 z9JAt@t7H&3xP6 zy4np(U0bWBJhfvKi^N@Iy1-5F*4H=7}3LV<)(?%xhcwgW;>N z{q-9)sE?wcE-ItYMW}yG>C*hmsq!*D;!C8wGdOem=udj%nNSKzDf>;KssJb)Z8xvO zyOoU#2GrmYHcX>6ah%!ob4>F`2yo}^k64R29T2VX&s(l)EPX-5@kbS><||URMTVDc?cJ7 z*S;B11xr(VA}-eDAoOsyTs1>8QdU=zw^w&g!|KfTV$9Zw zUjwZ!@^U>re%!IO6V6g3ejHNw1RUp91P4|K0-IALM7`HAEb%Cg;<`BZ=R);fyN4o2 z84SqV*sm|+hzY@vn1FmAm-P4KaQlIv4#mSvJ9II%Xv z5cIq>qH1=pX{yGBF&c%W=kn75cAzaX?7*iB{6({8P-K=O@+8l}GOnMi^MB9r-6^g0 zeAYGt%p8@upLhszh<1kdb6f^S?wFIVPtkO}(|hDw-^btUUP;AoW6n{@|2gbwpVpOl z%KQ4yGTwK#132h;Ma4a4z{6rt5{BP5P;LQl>Qynq>QlHR9bjG;%8tIP4iQPy5wc2( zT$nvUmSv^O#*$y^e(0|8jiv34f=@OC7z~np=OImE7%davWBH6= zQ(52r>mU2FSCM4eV98rt*Rb?H37D&?im2MR&*Qmc)6MBu+Sl>n(9Q4_I5vwnQ5IJj zaV^I0v6P<#+DENN5#;4R-6oY?J~TasYp#KiKeM+=R~t<~%RI=LieE;_0zZpJTD^eB zRsV0Dg>$s&tf6x~>%Na(^80&RLexWs?FJ~9(Lrf^VJzD~@z^1qpk+JVWx|QyAyR^4 zE>tQ2L0^T$8QFO1k=z*p&LW}J$8{i<6U3Whuz^H1CULo!mARCDWvbRyL4j>eFvD#G9fI;VYeX0}l%0Dqz9YC?xq(bMwt@j41Jm)d~!qOzp(Jzeg zm2+|fTPbc~@0$rJ8>#I2BkYs+1vU`JD{u);Jtbdl$W3X*w&-D}X)6i{n_yCa`Lq5( z2s+jSf-Ak-1owyGEhT?z<^0G6UqZYdm;%58c$U;fB?WT^C2ZFj;h5(>H3pl4qaAV5 zrJgh-lK1s`655meaKM`Uy>^6zaK=)5Xap7$ih+<+@1>ilwp*f_Cm71PjtUWW0%;DG z|5VC7z!-&fb}Em_8Jqv%pk;S6@>lXiHlP3kmf9o)22jaUpgCJiOnG6a`kHG-VIKqq zpW|0}&`aVH??V_?)=_GY3Cs#)9#z#B4nKBduy$53XUOw9FW1_U_#HSXeX{%^DA8}V z?ba4CxmjU##3H^<5O{z@V1MWrvdxh_-=%E#fnC^{LvZqN*qiX})<4nyUa z(2VGeK#$1^r%?J^BFt&rXs)$b7}^h(Z`^?|nH+Ngy2S3vZ=F+b;6yU?YU$C2|C7Hv+MQN#UT_#!f>SH=Sv)dSzP0&Hnx&COZfzYBNWbB93;ztMd%BO(u z=DU^}FH8@sLFWmPeJ9>K=hy}e054lP(VmZ&*)qPi?=LtuL`F^7Vzd$b7*!n1@p`(h zLwpT6H(%i6+6f2?_c{06f|>iIRLd418(k0NZMEc}KfXRk&i4>4{GAMV=o$u3VRskKLwscp!D^6^;+kr}{H*#+z@dH0 zCRhB76+ZUfxPHb+k1VuF0@yHR39gQD=d^qum!RfjB9n*4x0A$4as1utQ|2K!HAJ zPGn1nGcVR!8))?BBoHz(fiO!gQkiO)IwCCSz(F}ZaPO2O?!s#v2SxVt0JSf9|IU2< ziAJjtV!JZbzigmy;Vy@d)%+A1j|~v3P|S8F&7sn}T?>8MiS%u%RGWQZ_}gtG!1F7l zMwC(~buLbtTMbfQOhYFBr>LjbdiWSN_=9TJFp-&73jnoHQbQ^C8;A5orG{R)gmjJ1 z|5!T_sw<)E@7TdYK~ByBP(KCtc`B8eP27~yo&3ENKaTsY#}t={7c#^|%_p`0Vl7k` z@`A0Q%Js3b*fP@F z@dgO3?Kt)k>dRZPGpd#lniDZVo;3l2&IF=ZDhL;pX_8dHVllEfORf!4Gf3D$Tjni= zfjmN4Y~ok$jFPi>puNo~6y>k*ZwE3xCiKW$Y&C2W`d{?egT>B)c8c)99YEBDpuN)U zD{RU+up7#|a-PeFyunh5HGq}RCI3DR_Lx_Bb{ztx(zNQUFqT3O!+@MBCFJ~Aa!=F* z8`z$90@(U5G`7tlDr)`;2mdR?1bh?iLzBy3VH5U?uHONie53U~Gx)Gs;7e#WNank+ zMp?g|(*J?z!6>_02HaMlzHetC&uENn0NQxSMq4ag)Z=c-Bh)Yqc(u7w2boXIwjH)17PT*C_zRuOc><8C|{2!OaAT+qS!tC6NWCEE6 z7lUqpjh-x00q`=T!MNM71+dsklxj?0Q-pT=*}_ct1eFi2aH_N0ZF(}-VOr;Yr!o&X zjdr;nM}Oc4>~B6Xd6rtq9ki1qthpBjSAGW-V^%=|ck#W=6B9Us?Cfipw1q)FFXRzI z`m&XC&N=^aEVX+g0r){SPR>{_3PM-~gx*gP@2oLevGq)g>sy$aMlqoDA`4!LqfFMG zFchf=5IvaTu#K^?T2qT{jAIL5q*|Bv*jG=xHfssAK=0N5g0_1O{tMT@X0fwEfK_%C z$q!1~Fp_h5;+8W(V4gDudXqi%rD_WEj*o~S+sYo;KYvY%0 zTAZgTbd3iNs{U0jE+t=$;H_ksAIG0^&^BWZMTti>5^*E1#4RAdu+Gya{bntzKNCWC zP+o*)&FcIEKj}HapCMGQ2AEjL74EyemfX;2^vO&#vVO=b%LofjPU>w~^?Sf{K{vpt zC=M7%DpMI7#i>!INs<>@jzSf?V{Z`KLm);p3_tk^ZT6S-`pTT1Ws{mqSHcc*DICBd z-%uU8T@<;#hUfZf*c9<#5f4_qyAF8;0*!cd#`(zo{J@@?vd_*B8ezuZ*zhM7lWDI$ zBPDwHNozC5J;#8e;r5240@s%5PZwG@Oj*#`Evq_WuQcd$Iit0X!yG|}0`niA@_9!s zWolrTYn}A~68hl1ps7D!>7}#B!7}ztHm6uu1XAASLG~ zX$zK3R-;N7e~U=?!d2rDc>peu-+HH-?4p)2N|gy481+wMK|yzRjr2?H!)Oh1juIlJ zl67%OCGIP_cPdzvQ)uUkh;S-)rt8*vM5}RHe^*yWev zN?VdOH6p`wMcGrnUOE~&!ov^%#e)cAd2x?2QKdeNwr(v$r3?@8HUTCSaSBn;T`2w5 zs>O!Hp9f%B&HKkk-7DE#G&a(q!fOFd)^nn~S$`!27;U`6xn<-kWGxdv))3L>6xr_lm z6D&$*G8QM*f9A2$VAU#cwC;gEW-(Y#!;k~Cc_b6syodn~vU_@7=)Bg;>g@W#k+o%a zPW})SRgb;e9OpDd?>jAhgo}*F(0;I0$vCEyNg^QD93KuYdwiiglHBrt7 z7DMP0*rx=ohh%{t`zlen$ealJ5F`HsD*#>xf0jbUsef8Kt(UfG-4!;6^_Y^F7ncj2 zAV-q8KXefnzZo|Tb=G70qtjzL{+DGyz}c^a*kcQJ-{pAf&L!V|h)s$~3FdYB*5BLr zH_*}hZvFcfYY4P_xhOL#?;xiT1d2AVZmp4Wx)q2HsTP7)_*k}Y(tbJ94Ng$mp8RV1 z<$?=lsE4@}nr(Cac{dMg08VI28l?1nlY_0f)CDj{9sEH8${Rqmk^=~+KoGp%^sG7X zFIw>NsIcysO_2_(GxkVOvpwC;62HC9crRugF5Uom-wqd)8TdMxjPu)bp$8DXr064N zO=Z5ZIAHSA)xKZOF#3?`GvLx8rIs1ylX5cSK9BN;>Sc=wpTQ!<&$aku;UDeDDxGm2 zY|e5n_In5io)3hZe=RE&bghoByQ_llInyzRn3f$nCfY+2PZT^`6hA7;pq29rR6Lgh z4c@i7J#}bSs1hwE@*;b6GcL1#Kk`|(dqS*3W+6&=Vm$D=e5r5IC7g&h(vSTtkJFXw zYPRqZ+<2X{kPQk(p;u}+S#IsR(kP!dtt8L6lcDr@HvYD*VyeCQY~dX1s8Wm~n5Wr@ z+vDHN9nABx2WknBDi2)hTVgBbs4hzmqpv=^TnvY|KlH_{7TuQBk2koD&bE=X_Q`llOypG14LuD~qfhugl%XCk_(Qvg&IXBs2 zRvv!h;tH$@w` zj;(1D0TDD~G`eu0`UluMXiE-KLOaQdp<3!Mg?7XqUmi)t{pmuPr;W&@E(@0i0izY< zf0}A@Ytq~=P&dyGBf+ff*5zf2mpo8#R9;*D41+a~1lrvwF&dh4IBZSnb1pTRJ6{4c zZI`SqAc;t#u!VPfKicNIM%{PK0zqAmwC9Z5Iqdd6Ru@>Mv_BP9va+Ypd)$oA^Vx9& zlwdYY+!Al|aRf%y!#v*HgZ5u0lX_^C=AAxcmv~&sr12{Ee~J2)3LTtZihG`?R$eJ& z^p7?>Yr*bSH%WdmQvhIqy2ff;B8&G^Xz3DzqV`$c+a1C=y9**;(Y=*y@kWK#AL*gT z#&Uc?qY$VO{(Uo#a|dW)zFON(e@I)o44jW5B!PzE%!54*;`+RA_H)PFc_GpoD?bsC z8q}rkVU9(zpzMCBxBnm_a|Fuxe~w-;;XJ(;Y4=u`A)3;Jr$YGJb@;F$*f%r9%uZZT z{Zdl<2JRw1Dt=a;w}wYEY9=essZzMgHh}yT$L8^$4;6=h&vFM0Ea;?h9NE0fhvl9|q&E$B2uw89C9c#+($mbm^w;(}D z>BkgRhKRlZ?fH=u%YdQci?mvq$uJ^=0u)9hJXPAf%KwKr!I1C-HXyR}37Pq%z71sc z|7zJ-`OEWDr89Uy(su?qG>F(6p|Li`*Y?QQ*G-~5b@XS}O-8^R6y?O-;ktlPJu7zV zx!?nO_%)dOqHbN+OpT(V;ve<)zWmq20XJAlWR)y+SiLULPZjSvQUmU4pw;p=fPp_V zVdKH*BAx6i3pG;Hx&W3y_)&;$H&4bbMg2^7_dlt2UtC=yT)Bsi4u z`CbvxTKbRG0G3dqJVqLQu0R*jYfnuCS^s?>0t{^{5e;_x3V-VI}9d zul+yu0hp40S~1_X9EGAQP1{F1nq4}D~D~8%3o?`wmicVll_{Mv0}O7Q&nI^91rjpP46W& zeE%BEN$@+_NE|VpH39e|Y{#b=q({H>`E^YAiNZ}2eo`)NM4bZ=}Z)Gv9;D(Vc$THZ=UKkbe5RD?uYL^iFpH?r^Z2p*n;E6`yYOYdwT_b0}NpKX`h*|D7G94*7(% z>8K0wTSv@h>yzV~Ymf3GW^I|XH`$ZZ&T`t})iueE`j=2kV6Y51QN1>L*oMz*&}G(U zH3zp9ord?#Dg3Ao02#ufL*guMX~@t13xDQlpxXbP+rL{W;~t*BOAf~wdyy+oR5cYI z=%`((h??aAHhrZF{Xb%o+%`{O7LSzD=*O$6m>9h)xR#}KX{K*{1Rq2`W^Wg>q+hF}5wLN|a(WH9fyc3bWO?B66b2+%?2XK}~G71Q! z8FMw~j@aZUl!OSc-dl>az^b*l~s&5 zex&eLfJhJ1)(1#ui7r?uItE6qH1lKgll=beb;xq-x(aOtC1y}7MR?@V>|mn(%(T{u zui6?zjFojUFEQ;9^?1c8+%KjpB<^^bLm`H-8Fh)^v&Q|wc_YXV{keGi^bzo3yg z3It&3>1Vp8&plr8W76;T$mxCPEe0*+&jK(vS5eM8&dB_4lvZg{EyPPb9_~3{S!tw! z>nZ$gGtoA=Y9X>r%7Tw}H2-8q!XkGBBK^|q=Xi1OuW|V9)4R)Xnr~m^Q(p&LRGjUa z|0d8$$PvkmU?6{cmO5iB6e}$)CdUa?;icPNK@!}q`?-fR5h0f9G!?B=P!M)Rq+~2% zeUa0N!(asM8e_v*`=yYrDQXI0i~uRm^Hkqq8F5SZstz>%@xp^>~8I0*nSo;;IzZz zrYYUD*9?Iu+Cg`O@jQ#l8Hma%%NqCuFR`D!rHs;%jLBShPB7#8M)k2L=(c<{&1F zAE@d@a*Xc>#WDWx{u3yv11t^&P`6!v%gjuzyQ5S-1#VR)b`WQCb_0Obn2p>o`*d8m ztk3W<(4P+>KzMv#phKiZcl5x+~o)hFcb1CQM^Sr5$~{Oe!{7uyy!KAC-|N) zSXlK$AKzYwjp~?|9$}=uGjyLAhGnT(7hz0c;rqCfx1!xuRXQ49C07k)&JVD;;q08M zf2N3ITj@&&D(bWTJ<+akjT^cMsbb?GKJ2q{d?}gjBGR=CJ<^Ub$+r-p$RGhl0}54? zj1o~=EaunavRpxCeo6W@M@f74hZ(;jbQk0FF+Pt0Y5~1o2hh{a|i7!A#LG=a;_&UowdhS;Zp2et|uI3b^Qfc*_u&%g?w`Bj`3B6B| zW9_b2EMwVM%zMKcgD>U)QH#^l1heE-VbN!l&uUN1@G0@Gge&XPcQEgnen^+;LeGh8cDq^DQ=y{phANWYhvsshra z18)b9F6yJ3Gis$5mYz zGxchu3MclV$sJ>_p)<>iTz@55^0^EqkL~YcArE}S8vmT2#`C{AlYHY2sr5T9ub&w; zuNIH{?I?L>R;j7RwkDQ7iNQ+oz<2BScwL$C7X**M??;lBGe#Upvru)+5#R6xpY_yduA}@^Ifl&$~=A#4|u+uWr z8rfBXBjaX@vD-(vo@3Nruk1J>ss7oNo@5!8V@-kH#uca-6YOP=K!nUx)0lUtv0YZ) zL&PM;s79)$u(F^>u39r!bpeekLPlY8cIaxZLmDgMrTv+6dVFtI9fOBk0^u~^&sUCQ zBO~jXwP3A^f>hVhffm%Y@kFAZn9Lekl|D0_Z|%&l;9t&BMEpYqDEuf_ zJ|IKs+e}dSQe|*f3NZj}a*O1*PAHZc$wkXqy*{6veN3w|B8<5ev~T`z)=%EX7Xs)L)-27w;4%x=nPAO1rJ(%I%%0Ml(;Mh2LRLny&lYfwZ=tG^?68n;v7C zK^Rc@Lum@bEkc`fNmYk){lO)+12x2%v2Q~J1WrkwOTC-KcF2^8ouoB?P3ewnzPyM^3)vZ%I zmci;i>)koiKJ_nyA#d{55FOLu5P3a?A&ky6r5!`-~ZtBl%((C4J%c)Jbgv>Z2 z2a5F_b+N&a>WP>j)LU_8)y$;aNk<+5+u5o3`Zo&J{JZ!*Vm-l40JmOl`+yrdB{R-2 z($nHdWFt9sug+8e)x(YMkp}nSc}=WoWO$OB^>$Cki3nvyY`xWH`e2=}MumyI`a>^t z&I7Re}; ze@@cPUeK?d@t7W^*oG6If_>(I3i`9)$&mrbNdnXucQ=5L00&ub_nMwp&Nuzvwe8N+ z&i8#rGo8ND#}$~;=G8`9t*Txw%lo{=mA1mi$VXUeDAB&h^Lr^Or4aC`JjejIvnayx zbr>ggXps>p6a2+E?OHBwW(RKKJr0UWeu)n~SSOES4^X|w`U=~b%yerf|BDcP zZ`S@NPcI*|5$y>G^{OOrwcIc#UIcex0r#B`^>87T1-zqh;@0kfaIWH+5{}XFFb9;J zYGKfFnx3#uE;bkEU^$poI$Y#`Q@{soS;B5k6zVsYZ6+RDJF4$CDcRJI+*x8JuFEwMZIo23XU0J+iJ(aCr^_y9q+Ix!X+o4fWXw$4g+$cg@G zo6~OxtpznKb0tgvuO%!!UUI0OoWs|ed*oW&j(fUvV%;SL(X13xo4wVuJZBxXXpxua z;35&MN?oobuyh?O?41rg-R~9xU+mo6O=HEcPpT=v#^B8*3yNd87U3ZUKYy7d9yGnfDzh zSx|FpS#YMP7LP%dRJluzvf>hckg|$BXL4G?ptsSjVsSW^rDbINN(RtZpTifX78iE9 zVjlGbAvr`x!3~BsWs4H{RS{6RSS{PV`@)r*%2`yeO&q?k*Hc17pFko>HQ6wcA?e zpbomE0-*O36B)~V4Av$zZJQsLj0H5oqcAN9j~uCD-&mAu64spBz%sofjn0G}@Fhe= z)^<7wgYqW(vW*P5hep#56fuYTFE7#avq+kbkdbZl56M$(Wh`FRN7gSyJEPvKd4O$S zfis;TqQTsOqw5(cvPLXu1rKAyI|hhurq-X$+>~zOq_teq@p}XS2;&*!$o|TX_|Z>_ zTcgrSHy|q14;~_L@|wU1vD3zcYS=hv=On`DDF%$1d7eDiEUk)Dl?p4hD0MmGs@fAA zXPSR3EOA0#}HZJB7=0u92$#1+($OM-QB)rV- zCjXkfVV6(JMVq<71HDpaZ@8RB5VWyh8^)rkOt|JFgk^)bQL77Nf%0{By=A7RPxoIAbUh-Y+je*eHRM zwSyb7yUam|3Bu;uOhv_)!2Jy#^k8ECyZ(hi$d~BL$sMunisvpc5M6+f*zkvh%pgD* zNQ5KaPrUR7Bf$DnG=NnV52aV!w(H`e!X{~LJO=6+xc3_(8D%>eG!xm>eHCm%>uF|3 zpuW5kwAUPRrT(Cn8W-L&GhwTubrLOlo1H<KYZlf(t;nO`gRg$^QGx%{)xGadL)C`mhx;s(p)B?-Os*_(&EZ(-j zCrJ!wb2pI**p6P>Hrgm(xDOrcQ*I{Na#3!}#Fc|i_WoiL@hTjpz<^I)?>O5bf;-%9 z0Fr0HL=DJR&O@eh*E9PXYz2=bt`NOOyeFRc(&cUY_*k>=?8A?M{ee?L>$G*3LFpYt zM-LF)0a?t-UvS{9u-gc+9&2D)cc4dZsoq@ZP^HezP^%U^$R04{dkf{>AUgUsq|Cv?wwpp8#wP+{ zbE8w=JV)Pm(@NdHO^}nZ6e0s@07#;TH%8o@P<+7+CnB~4Guo_Zmjy5cz>?$C86WhJ z9ZC^*nvkZwD9q{N$$FVYa`zWYO<2s7Uj3NY%iuwKzD&ajuD$d3D?rPQZ0LiUu->=|9KP&q&UAz= zr_KYSyewTyOgT^y{-7aTxtt-)=dgP#0b-t>y?Q|2PquOVB0|fgX4Ak^+QxGrH^~6+ ziO{Z;A#h#%FpWl`#@j+GjAcJmlZwoX8MAr$_Hv#P_O2c&-Y&CU1xaOS?V>(A9 zuw7y{(JhDJI!NK_1vO%UG!kVAu7Spsf1QQ<@MACRM3vM&Z--x{y?@}7)F8;>k@5}g zxRRjI`=oUmtx*v`)m_zbppM*pBcoBz zHW4D}gvOL@wGR4*qpC6!QUC;@GF$lk;CR+mM3Feu!*OZ4-H~}#BUnvQr_C$3)%?Au zG@J`9=+n^=X&h+oXYj^@)K^Zy?0)T}1k4q2Vl%A=FF-7rvYH)xGS*7lw_+$y>`)~_lsQ6~55@rm=X__GquX~VEJx2~xA8HWp2gO5 zK}bm)bx!*AapIrDaES?k@Z_OG6ShEP&Ewx!dk7~wISzuAL$X_=<2}J0Rs(!rw0K%H z=(s}AB3lv$?qt?UTboI}AT8OB`=0KG`t7%~4o!Z&um>+|QGOu3s+v#@$2N3*`oyMT z#s4}+N(_d$HiG&^=qJN*Lq`mc(-i_{`c2u%iLzcLC-z_$_!S@}^vEKxA?b3*orl>6 z1dN@X-CPBKwQ8)>IY8~fIyb)#k5c|%WB>~5t@e7)eF57VFwdjJ^lCwdoZ+H&2_8+} zJ6k1Qw>;K)Svb{7&n@(3q^v1}y;HKYj-5U}p)`9?{$0lZvI zj4q5^WUea|A3*e98ruo|Iv-rCL?evlnl^;UmX$@`YoKhKuB6IgIi2SBY(%7IHJfnB z^*E;(^Tea>^*R*;>5K2Iz^RseQ}{<6q6%mxl^P=~y~^Q$g9E*DE5?-w2H-57b|6;q zjUIdM2--rga6>t!J&2$r6V%Uc zo{~KT=~z9wSiRC4l|>*68rVslu4zvKo8w%NY4b>hAf*l=eK1KyI?x_RL8~|D*+6I5;G5siH+>U_9(?x3tYtDRA;N+MzT-g{Oj}I;7 zDNU{wv$Cv?4Afj)l<+8gDpxM@Wr@(HO2cu&m22m-{5e*zefFbnc~h3(EazGx4kO>b zmI-;M4~m;$pPr9L22$Z_0x!mC~Bg%;&jt`I7K(-M&3|A~)?1b&IYL zR6m;l+<~C>IvafuapP7Vt3HL66TXJ9_lWM*g8?*Kj)vTSftcltM;z%vJ@?4MA5HnYz+V~Y7a?D|f~T)?X-*IXJlyykII8cRps~J|Hkwf+ zmA&iSk>1M!j3caYa1swPnuNNqVR9+ELP6dNJ8+upaoP8O|5WNnxmK93GlaGW>T{&$ zz~wy~Ri8LZ)itw&0Miy~|5QY~WSJB&%D&wH(B>8ejsZ(K_(JFf{b-CbIno~TWh+`u zPxyw4{PnM??222UDN)ZElNmil-EM3>atMsTnJ5}TFbDyLi=fe?+Xw45ll{1F=7NC# z^tOETR?W%Y9UiY5CcYg*hJCsXX%vQ7H*P)b7fD|yMz{sJ6jZnHjjg>vX=`}R@R>>p zhwYi@C&o^FEfJ<^(mLfb-<8(Y?T4>0Hg+c+2j4{QX^1R+f56&0pAtQSm<FavOF=ltH2`z04vDe#c^QtoJSG zNP|%HF@tREsSI`9T3YsIF3WYVImyN9_`+b~NeiEhe9lQM4ka}#E4E*80nx<4$I&Ux z`qflmNl=nA$(E(_oi7iiLrP@kC*@JV;B;4{=+TPCwZ~irka0WSI&|p~ndCX4XvB|` zlNLB@wwvzF_!s2OHdF}y+3(|sHd-9Ct%}|nV#kx-AO=jjyj-GX zrp>XRv(!vZ20VPT8hskn8tCHQ){S+eItF2OF&+aM#JHszM+I#+bS_3bh6g@=9;+6O zuGCIusv$K|<{y!ZQ+&8{R+kVq55^&1gXFU_&``HLuRKfjj#;p$!sQJXRJ`e@@f6e- z0^2PBn3J6A6t-Q}d-0tFU@6+3we82$x1V$BF$QtN`TJGlR@8f<_2Z~aD~Vg2_zpCGh+eh(w_kfuu^SIaeZF)OzAGlgb2 zX?l1PpO^+|+LZ&NU&XPn@=W}{n?5?B_`<4NDh?wjqF(zao~Gj%HA4r%j&8do!NYAR zTs^gsuqrC7`{bF8H7B7rP{xHOy6@zaQ(5x^Gt`jeDbn(S6lIxwyw@~?Rm-#J*RC9f z6yJn}o&}<#jQAKoyr)%#$CG-a`SUs-2{La&6|Ns8+;t07gw)XLTnozy6sAa#t{_DS zHtwvTq>4p>BU6Jut*G%<2(I{dozEy+?HoO5e_#=r;LIvV+tg7zYYBQ_8B;UJHTpdX z?rnHc+C|7?yxUO(<6ZzJ3^VOBBp{tKD%tgX)O~Fc={!a`G|1R-e$atZ0-txgbDfs(PQQ-!stY~e;^sVTQ6Vf`@KS7X zz|ulfQD_;sG9$0w|AR0Mfd%KiDYb~UZ~Fbsajt)#%!wjHgpj}KNr4_*T`8qLqZvZO z>2Q^^=X)*=CG&0D2cHz;CAz=YGY(MOnRS z_s_W)xgO0oD;-ODCcKN>kkvE_E^lFv5=hqR>cne4E;llcdp zNLQQVqp=PyemDck<4*Aob1fRZ>Fad&4L&&R+T@u4aA5WWNO&bK@TfP*(Y@j1Mp`8L zFIktuagryq@CyVBm_WYre1c{0z=e(`87u~+j92Nr$!N#|auVm=jk?hof9!ZZ>H0`O zJ78Nwi(}FAWhe(w1A-r?dZAL!`k`aOU_EMBuD`a)g z(#=1X`n ziQ^q}Ai*Q;*E83211Q-FU}W zV2?Q!3!>3M#;&)}T7fMN=MdZShyO!SBa21G#?Qe~@)6$fd=MXP= z3?kz@5Qi^<#4rnyx;VZkEX63(fvY+U|9P&F^Ooyw!1cJW{ABYX*f4KbvRFM|UzAO? zfq=^x5#b?5c?mrT9Cjq$5vmERVzfIp4%Yv`DxWQR<~q$r4CsZ#&qG(JXg*We@l`l{ zz7NTNL<5Z-T4Q${1(+c2PM^qP3<0_+o;K!PwccAo0^1|MN?+8fO1Yp^l%Kb|0AK={ znI*1D9XydIV%%4w(w&RQpCTT&2LD|QR#S(^A@v@Oc;ACKhy2X8br`Y^F~&P|j7GX9 zU#Ls1q^9FO6DhR`ar#KdX~?C{-fK`Sd#=-OoM@~zr&LY}-ly2*&ap7=5W1s;kxRV1 zboT&3aUEbr@1)-fASldGt!Cx#bQ{=i zX-RQYktfcHu-c~&49B=FS*YA8SkPlO@@Wl=nE`w3_{uW}7>9 zgK(6wjR-I%-x> z-zNN)ZivP7gU-T;A^Y%oeCL>AOCK8UIgrdI(@9d5RuWKr*s|ufu z!3WTaih#fsJW%?XNv8yxkRP8FbdjRGBwTN&>23}?!1MVHuw$R>Pkb!ZSBr#!QS^n^ zit!RIRDjm85F{(T4dyu=MHHT|>uhPfnkF{OOQ|3UI05bF5+WEz()c$>pfzt~ z$ZvLJ%Tw_MxnRIS3qU^tWMT1pQFNCvK!NSQSe4xcR+>$!lZ~8FuKo*+I(4L2H_l~` z<^FiRCJBJ@)GrjLvp)C1Hh5j+-`&R~MS(K;C7bqp6EKQ#ilF1?9a9jIWQ@ei^+4Fi z`Eqp_hxHwusgi5FxF8MFGuXs^1_TEGxqQy}DwPW#BVbxKS+bjTax;58Qd=F%2`4}F zFKBiOt0WI~cobZN=KaEG6>W9%v1Gj_RxsJW7O%smr2&h{4_MZJOJY{^!iULA|qSe^)Db)je(w39Lr+f?>U~ZEr`FrME zBx3?3TjxU@`VYPliH*@rG3WTF(E#H^4;~hc^ZAcg&-Dn=AO9VK2>j-h$?u&>=A!NW z)%Dp{BZU>fR@CSVGdaTuu(qI%!5?D-GyT+dA~?8Iqk9Yh4du`eTScI$}XjZFhHP5We~TZ)q~kXU1- zel(0^_k&geQ5~t%8veICSv2L65S|eNmSp%%oDsq(C)z50$$@cD$u+{kE;*Cti&Wiu zv=y;GdIVE|VJnj715lkCclppO4xc2Wj<+O3(A%tAdg7Mr2QAhdJCh&N&5{-$k`WfD z( z{6cJ1j2<{q$Bdk85%Mj0{xeoZbE{O}W{r+YnhdZTk^u z=r9QHF^`)E_S-zoaW2wvS+fIY?Vx7wvK#D}CT%Trb4_X-!+uQP%?F<O3yf}VRE}e(0rPudkYZ$Xz2usl#Y-^e7)Xad>NUjAd9@JzQH`|74?b%lg|qUw z^%NF6iySOe_0;{SdAgo z&{kU{Qd%{pTi?7o7{ZEpcO0t25?Mb==U%n;5!AtqG$@~vQ*H38a^K6lz}>yNhAbs+ zM)-tu{pm{xi6vq?EsV?^Jxhx`6yE2T@V4rSIeMI9cPcmTQ#>r~xBEph(JQq6j><{< zj4fho)90`Tow(OmI_zbyzw_Npw0okZliazTI{gq9ZaX-j`w=1Go`xI~y4E3hZ1?^O z`LtK*qCarbtO;Gp8#mt2+qy@6EZ_KghB`_Pepe_znqjliWHrmG8TZ7(byeEZvp@>9 zpag7~t@FsP;>EtJ{P@nm>LE~Zw+e$T-pADCH^|kR8G)nRotryGB7RUXt%$u1Yi_&& zbGWSSRzqBv+@rGkMs<4eYEyObU z7LPehBUf2F&_+r08_8`E!hfScPMC1~Dm4~sOHJIrNAk(#B6i(Um zO70pt?|}!~)Fq!!ny{}OB3+a1oE1)spEQc^7s-_^se9RP~fsaISMkp zXB5ua<%=x#P4HU#ZUQXzl*h(7a##&(d|+>S6UWO*A<_g+09~CKGaB=eu*k znUSLR><#N>KOszrP{wciDWBr4jmc74(e(OLUBftd(c+wPpMm!KCB60d)HA-=Kyqwv z+iq?RFW&4gN^3IQ8XMD9z@$095*MHAp~zCE$mE9x?imvSqZ_Ee6se(-;e$2Yvd5wk z312sV8Y2Dq=rKufxtca<$A4i4Tq?)7k6~YQG@O~X$vv}rh@35A;OmTtX|y|v9A?Fv zZCsXyhtYZ(O|%c#vwpa$e;{#2cECNl{U-b5@47WU*ezlCt1nXb`V4Gnnw5u$l2f93 zVXRBU$tNZz~@Of7jUZ5AE{F(rg)Hg)zyRh61{2evbem%2mtWOUS_b7bdM@O!a8 zWEh<@Wo9OY3vEs(slOYT|LVo0+@XIJeD^eMQ(on4d`P!Sw>FW1mouZ?X}-8lLV&n@ zzXB9{4Za%9&Gf5Yy2zPDN22>dRn$}HPKKUc6^x_kbevbdg8K6VEDnX`*^18XV}d(~5-fL96$@7kq?#d*z7qBhChX_lIQaQVDn6bL%qnt=TIS!X!uy z-qBg9I@#!EqE`%U*F_2A5y0XE0v_h9-2EWNibgW*_>i5}#!C0tfKY%O1BhZMIJmA* z_4#dqkZR))ZaAkwao2LvND22|bq#)p9ZLlBZ`@{OWSo5TCRLul53{X|`o3`SxaL^= zuF+A(5cz-I;LCo$m*k&|!Q}VK93-)0T`#%j+__VKkY^T~u>H2v%}@k>$*riz^=)z`qDy2=^GH=ptz$5J zy;E`c4rr-9bbP|K)~2JppApg!6pGggvSekd$&nl-mGaw*swlxP2pxqwKXW z^$MW`IReiz9R#tYXVRqy?ZRxpxwAiBj(zU{)ZU0z)aLP|3>(aurvmi_y1XK}Pr_|H zNLe4%3>^DjF#-Qm{c{o3+a7SrC~2g3iSV^}#h4J=@NTVR_cQkzyU=40ar#)3_g54# zah8bTib)gS0(0^6 zMdxr`yrgPR2iB_id^}I*8Mcwz+;F`FY9kNR$`jK?tgGq?&UGlsZGe68{1IGX0;Jk; zJKq?84-~M@BEL>$OY(89Mr|x7D0{?UY|%TQ9o!|K2$q%PL6NPt<1J*N+X~?MHy)JRJva&|GXYdd z`IXv?DgUt97fw0Zrb^F-jq<;H_F6YJR*$EJAm-d0-}0laAGaIbc5iyUQR)niSyf9c z+wH^y+cCNC{B|V=vHjq8ge5+7S`!BH1x&uDsB0rn*sib)A_FkC&GZSuJe#=+>LdNw zADrc?ppB$mI5_)nb3MG4!TGs(6oO@onE)Dp{$+0Eibajxlpy0~>2xR9?eY_^9pVk@432gF@e zB~iR^a@ubQ(AavKPLUzCG6qhah>@b|M*QXJq53F}#^=7uWK>Cm?AV#!)MH{gudUdd z=vC$~acXL~eSr90x3<-R*pK~?AWTn3Fyg>3ua)|EVON(ZIl^6NnN{5`N_kHv3_$PT zu8xB}Vki4=)VjHc*#w#K-Ejoh7|$1b1yLlnSlYs=u%%|MVOrHQ_-&3N9vs9^GAWnn zNkNjm9UMNTKUYkcoiyVw6*XaW6nrJ_=Kw%;)}gS3JlMx~PZ?D?YC9WOhvrk5d{jn- z{-cuhl(jo?`vK&M?1=y^1ldly%e+xv*uiR{xjv6>!|jnZIrCpHK@Rt`XB<|fN?-0? zKW2$eM>vbmHXpE`-~|Z#{1{8&oTgW~Z;cQBv)#3mPEqoZxUF&tf2yd3FC5$l)-gi#4EI2?v z{zZ}UskD{t5Lkh4E#X1yL?9<03JmR-8;pivw@DoapI6IUC{8F2bd90(P&E7tSgiDg zhtmV@asPbJlCLIXqgPBRTW+u~XQe@~3J|Mxo*?uBz6HkEw2+8DH5DIpx@t-uw4QMpfJhJ%lsCO z3z_~Yt=WM~Yf1QWpqZA-SZZ+Vwoacbq>9j@|gQo-#({Wv1+!a zO<*LW!oq}kSwdhRvUF_Vk18DVH?y~86N z2Ao&K(u{(ul+I98~U%cWr?>*aPZPoZHfhAfxexEpNQ7&tkgxacJ8Q zn&(&*hEn$-d*)3l+G~A zG0!4akd}rS-Fl`vy}16haNuh-B%)LhbUSv0*r_L5gVvj(F4$&KG$*$Bm>B@{%pavB z=(EXD5KX*0fwNQ+XwiRMd;S{QO$P;4PY>huiU!8VGk;p#!)RCc8zPGc^HH8E=F2ye zOs&6xh9M39&|9G!JjpDP&3eB@S^un_yUOFFgOBfAM=|MeJ<0G~ycOwgOyWLgL(218 zXH3$XmF^HnRvip-99wxauhv7gKc=*T=q-GS2O_1oU}4-RI?C( zwiGZh)+UtGVdO$)((^lgTLox`j7Mo8Zy5gdw|}o{Ac2~P(X!`tO+@PB>+ka$k#Y(j z4>~VdBM>`?5O5IQ6-$rjJEd>$S#>DI2wEe<8oXd$9uyl zbR6hHUFSAHA{x-o*q6x}Z)l&?O=*QTtx0X>vYc%;sY=tmh z9VvqPYo9Y2$|(IqYRs_Mnqc%Ma2~`14VF!cy~58D@ba8#_$g%0LJs~Aq6vy584#JB zS`Ip(ZLOr0p!Yy(Xd}B4cQQIcBa&|9d(v}8a zc_`LIS5uUl-Kg(`7i1F@P=%?Ki#Lpz(Z~yRjytg)RG8kJqUUzFSGW!V#?yrf(~2iQ z_S*q1gV2mgmSK<6UJR{84(eD4tt2Cac}FahhwP`vU58d@_NDjElmzSX#gn!60{OfE zV~oXm$JV1sNE4ViF;1yPn2w&syxVAPoD~yHj*UGG0$o=$_D>m5Vk4WqCfqd?)dD-7)01bL$o8rd_gp6lW`w799 zCGRxQRC%PtqBVz+<#fKA-Y#K}n@{EQB5AK>m({%`?t&n@gXC2lC7heT(er%*D$rAI zXo)wpkq+~{sn;U*0on4*^TKevQk|W%KP(&cPK|7a?KnZjkyf|}nBmf=6JC`vO$(P? z$!uvKAsY*`pNXFY8Qb`?cgQyuHlj=a?alCw7Ub!@@YC5XuL~MPY-2XZ1N}JlJ!>rj z%Jd1zbipxR2rM{h-5wA8BqfN0WT|j{@G7b+w(X!?We!ZNXd}TPNnI8|h3Gd{f^$$R z2m>|2V2c|G6tWSb_j4G|7yo#qbvNjD2t_4$9V6z|X%2p!PDd+7U2Z4}e6m(gc&~^| zUN0?Y_yIXP|9qKOK7t_KTyn|e5-AI$hPxHI{89#>&!EPO@fuSA-9r2z2kl-*;6wvr zn>bi^dsHvC(qPam0VCX+*Fbm3D6Haf69-lWSa-ro?>&;%K(A9933v+=)Q4m+JK;rd zbfB><`t(w+mklkk_e}Y;13}QP1Y)C>f5DNbv#+!FHKG_>G(pQs!)U_KT5ZCT)m1LRL^dY!W0;b~4mddtn9sTp%)pCFG0?ME3r6g;rj-{v>QZ|CdXA$Of zcMb@D*OYd@A1ES!zC3wU!MJVwJR@1(NpyIEevQ>lo%b!A+96wwz8n6^&B3{9%f7hyXBzpI>v|j?eLuI= zmSKl+<_f?4NF7>dd^+nq^*H}iROntCX9HzYue_Yq+g+RkV1O4Hf9xDaYJIh`;dsH> z`?@q?07&}7HwPD1X-A?jm(A>wll(b5=}{7b3AbV$3H}&!`FKw{HtB!7EawknRC4c7 z6!BY@{G1Qh_003EU?zH{GXK%>z}MhgCDm#I`1jY6m(50HQeQE?&Tn}i>UE+jn!`s^ zV>!Wr+k;9gv|f!Y5z4?-WBW9OtA%499t0=$EdO=f3f5vP=hdCh6U6$u+D)X$@>icM zm4N!(D?hxZ{LS7*#q4VSOGgI2(Plt|^&C^GJVA_=MD^Zd%Cu?FnW}H&H_2oMfjZaY^*;f{ zo(qW77B>c=cBoS!EUY3*A?epZMeG1S9Y;sgJvwn$dK(?cH?mu^NxAj#JD3^|SyX`O z2_qr!g*0_T=AA-_WpU8k+LIXGM?6MvZ(kAW^# zR1~}H7-AwM0A8_$VhrB_-P|_p++E6_Pwvrl+?4+3<2d+sI=`dm1ftbqK-2s45`vfn zgW3x%x8L7mGq-H1M9!w`clP@eUI*#%MfVZPSpx@(ppd4B*jZ$ zgf2-E)y6;=A({Q{mmBB5Ev_YNKN-B`DuvcKb@xzw?Z_Xoww!Ffen=ubk(MR5#NmZR zU{1QK2EMI2^#Ii(7AqS_8cElp(Ew6HZ8>VZ<(3qJR{EA)PGqQennn1rbPr1+=HlgI zWhT7$a*HY+XBg!)E{|xi5jR1Md>g1>qV)-NT02IIqZk?2yaMjq=iOOBc)hV9Kc9A~ zUTl|4#aGJW%5U_n6*%V;(vmQB^{O7=AJ7#Jkr$I|W_L&<#;&S3AT#;Sx2uZ8+ep$z zp|Vurx1YHZ4qe%p5{LjT^=}g(Hjglrou&_&Rjw4YURBP$)WQavId+oi@gUrGvv2=* zK~Y6>pf-Qc?W#Mp7E4>8olj*EljxjRYJoj`;q617IOxtTT}0OA*Q@iNMzK#?c_UUp z=xrn%ZAH$vyIBW$@9|gKt1S&v;9)_hKTf1NntLuEG0@+!+H_@*qIQyWA*AUa6DYgU z7lG>waq=EKf{#XiRJwohAZfZmWS*cST`u0=MpA`s8@tG#}~)KpCJGq zp9_FPL$(@9zAH3CazE6}wL_TE=GvkYi3rR$iEI6if9QpF|D=GzJ)zMwThL#4$?0!j z;odOipAYI#oBW&BXqncvWn8qJzhmF8ATkiGW3)AwSrg-$W9#=qdqT6T!K=@&!2~ZX z!oZ_>yQoAclYWPCy_;O3p=6#~RP@yiq*(s3_4wqs{m)k{{m~b0IT%j0ot&4ngEdne7lx9W_s@n^jw{GFVq zptlJFnmCJ@G|daNAPL>1`XXTF;l4ny87l$78?}%4(=y3m`-2SH!oK#vaN7j)n;u~2Jrd;HBl9g2vy}Uw9Fig%?7nY}8Aksp%YEx0y+6-w5N-dAX) z9e-P#u^AxMzni_yuci%ATAa6s8lU~G(lQDv zr_?E=L5H;*ZI=2AuGD=s;Fsp;1Y(BxfAN0P!9el)Fu<@TT?-$&9NjtscCaEK`c0fa z>#fBoKwYJ=!~WPOm({um>CYAQ>FPtP2?r|+dvqcvgZ$j|uboJsVBMzT6mT-us`0c} ztU_aAS>0B>dm z(Wg5uX4@(IfxU_{kq!*-k*~P`%a@6paWj~vMF8+#C3X_MLVQcAzd<#4Q-eC)L;u-o zP4;I?=z>Hi1umkv+vF#7vJ@S%;)Bx1ty<6{Y1-b@Sz(5ese| z={`(ovQAI*{--;qPiseFo=jJlZ^{W+#32aYlNueT;3QvHNm|qSdbUpVhbvQH1qrSk z#0v_ph$O2GqE4Fzzz%GMhpjMQTgT#K2?9y z4+BG;oj2QN0nA>IJ0?3yESgi{lht-w))>`Odd1vx)p2$gmVwYWNZ4)QB%D1mg-Lg( zXHEsLP1%M87qMtd8LCKnA7kXM`Z|j~HAx9e+o-RHIIR_e3 z?DFUPbMWn1T9f2NQZDdPnjhM)G$5C2J>Q{w)u!^Vh&~n~zV(b|#5oTlU>T`dPiiw; zc8hc!^~O_{Zce5LbMd^M$n;v)zh31^*yqz(4K%F|HP7Sp9LTcq56N9+#sE;Vw`mUp6K41deY=?!MgC7D_Nu_CW8$Z z$N&JL*zAM_6yr7i=3;$=u06>M+)gq^aNzuEXH=5qOJb3IwLAz_~y-|sr5$1)t z3Fz8|jLy{RD@#P)T;U%5NqUJYtbCJu;s`?FVMHq%I6PPq`sRCY#XI!;yOriG{p)|U zC#8*@$53h}C?xen$CY0hHQRa|qfw<@u>7=RKWRlWq4)62-6zSz zwq|1Yj7klg>jRXZ4ej-dX}ym}FTQBlH%Da@U4P8V{uRCnMk|E!&_rC&!X`P*EEq{h z*0LltEOD*f09?hVb>R>;026#(CFhiy%A(h(ss+nB@%HWj96HXS8Qz9I1Pwtt)5s@+wu>leDArz7yLh#ZJnvmQ>}Mde$->kI>tmwFpj z2F^7|LF*`GP(WtoQIENAM2_35#QF+b6%OZT*owvpoKGcgom=7aXE43WOdg$C6=Vfb z0oG|kh92YJ;R{PbAD65z`636%NVQfjUqRP#Lj!Mh{`SkqSB?zJQ3mmOm2Zec>Facz z@B}2Vo$rDR{^yw%yMhTh%+D~vO9mGEb`lvEU27nClj!)FesHg)*Pe9VY z*ASHZX^xnNT*J_JB!9ealSANcMZPCq%Xfy0a2lMNlQty?0CcIPeqIq+yg~`_B-)^L!BK;=yR(?Jp`?EY_%%C8bdAS)Ivq@Yz*RYBs!NkScU2NgdAm|@BeV?& zGw--)b~!Bgv?Do3Bo3amG`>kYcY7f=^Cl5KTGl>LpFyE@?L;aDt?ZKHUFuW;C^E zyFC~xJb3z96s@^u!c@{S-KXMCdlFBgDg+kw#{zU3y@kng8SqpCMO@D2 z3`%a^Y)9c&jvcof4Of1nyG`A}Q(4&{WSCu*k2raz?Zg7`>mwFGj96R@2Vk;$E-elM zX$cNG$FeIJ=y>-Q3S5-w?6=28C*rih^;+DZ;LrHg630d0Pg_%HvlH=(d+2K1ajHe_ zpl|Qe;fW;Hh=3FQMm5&d4MoF9C<0}Fux<_xrf+~h+R6%R!$jBp=W^^#s#~A5-3&;U3DFhD zt{lQ_2-hSNVGxj)?W^e2{eG@w)uMr?2pb|&g9`lGqV?#Mu|%uHg<*S4&s4LBRIJRu zkyG#KplYXb$DEP7IpB4k%k>IT6J>|xRXIya>EU(Th(TFpsd}%yQ5<&G2RyiKXOR~3 z(zV>o07>yT4-%_!TTF#k)3OdYA64Tzv>>*Nd~}V)x>9I}2@t#oH83h<-^QXe;VzQ9 z?s5H>?Ta;!i>AZwr`nQXNKx_rOY0i^um&@(CX|4GK=`c}`y79on7b$YulPp~$a|5`1L zju(5baOaF|o(XcHFP~8_US`i?9y8|STI#1=bEsuc)LkWTmKbEv?*$eofc|#V@&%2g zg_?m3s`TPwTXj_@3Tw3)b#(-SfCeie23!AfX*@x~zu?~SLx7F7d3Lw9wwfg3mNJpP z3t9FHvY7-XPjf&2xZ74Q;2H>K806@%6Ss}&zx2Zyq+B5pYTDfkzz@O4kIfrSAcc)+ zO@U5{Zm(RTIym&Ko;|1=J><&|*dx{us;-y-xi-W->?YUKHwH?`o&)eEp%i36#!P($ zQAWE$Q%R&LDEUkuW_JJYl8jcl`mESZLu^p`5)Aw~0~{(V63~a`No>w|T)?pxYd%-! zUo*xZ4MOn;_|sB2F~m~xC{rqEKhC4+DQHm);LG#jG$NQSOcpZ}up9e-UT!q~E1XNP zr?~+3BWWi;&IHz~z(Jv{M^`_;<26H|0Q_x$s$_lV07~1(K^|*J=GMF>D?;Y`8d zizMv(#n<)*q$6vEgKTI>HRvQJZ0?B-e`Nm6Xz88OR4vN$wX>eRV&_V39}ruJ+ERxs#j;@2Q!J6$uAncN2PkwD|1h6FejQ zL+ZnaBjjRK8cEC$#lDmO2i6{jKD7Ue>07n`YDiP_Q$&f~&>0Apxt04i>VSJxfaUO2WjMJ9Q`rbH(m47r3EH

9n(H6d~t0s*27ct}fDSPT}we3Qw zY1lh%b<}+D1%IbF{+<1=ccVKAnXY7Nv7j$cm_#c* zOUFPL`mghOKlA04%mor)@VYhP6o^ETi$ixdjbWuwsy09f{n>S92WTilbTnuxr~bm^ zQNwBB-+vYZRi!hSPO9jj_@^n#EEhz8aBL;FiEJP{=f_=_zuZ1t<0UJ#^5`BKq26`X zIxf`F?3m^r7)gCj)8-$aUuhGg2X$JpUM9XC1;a`{B_{U8(o|r#9H_lKDuMUAt5-{V zCnAk#3aY`KYTBP6B3o8nL;!#m28xvfx@kkU|5%g)v0&3aj#@2IhfzYk zX8&fcUD){zGH7&zTC3I1UFfL~SA$ztrEwHDxEmFD$$<^=FqZShqkw&=ONy>xNYA2H zb(&#OxX&73IT8WcgmVKW!GHUe^N6^`>CoV_)9OD<1M%o;OcW84SWy$jc!(@vt6D8k zerE}MLWJ`}eRRI-WogQWEICLa;=v+KhV68Z9>9L=uZi#TON;Rn$9ehkZm`ygS8}s< z#m4X@$c{jsz=h@o1jre*{=9EbDvo#m>s}WX`ok<`=;_j19oGpc7oK;X&TP zSZaxpr9=R$MC^I2 ze8M#TCEOjz%bcAso4rV*IfW1IpbE?Wp<PL1+C9_dN!I7rZyH*6y!6`V{LD>}7*k z3AqbOO-{0+1AW{}C#&~iWHHaQt^FS;S;KwYkGO&Hrn{p6pcJis*yT43>gF<=sX$I2 z9Ak9l*YUI6o&q5iP98Le$J7ZEc}`#CtY56mKf(4?p@VoEe>Ij6zkQzuSaUU5jz>6s zhoT4SLfFaxi!Y=4*GEG!`7lGK8RTN(lkUUc+c}xg5wIkvj6iRB z3*4u~5qc(A(V=dONMPyFBQfRI%gBrfI-#f*26(OzR0(12qs_~{^=FXi6q73&xhp52 zHCn&gNYJJ9jk)Xq{Ftv6U2FqfpetPgU3HRB@;N{XXP^OoRwK(WV)M{UMG=wiNeZKe z{&h0xKL0{_z_87)JaAZq020>wH>SKY$70=YJ7Dm!@#pkLhU2ZTQLU7@2cMezk29;B z1+s;mEMsk+p`q8VWi>26^{ILrAm-g40K`3l!loR+%|B3Q)6Dp;yE3Ba={H@zkU=}lZIyVBU&F5H|R=x&G} zdu<*KxC4ZH*OwKNo&0}`w^BwJe!8}Q(S*s5od85TXJ@lQg`}A*{Fj(_wc=JHXASq9 z*o4MxQ>%Lq7UPIVTpix}$8GoepJGWJeJtbwZU1SVXud<9^Kx@D{JBh1))AI2%mFCd z0rAf=72lb6O0GbotAiA1*TQ zO2uvD-jhL(;vV!}%1e{vl+TQtU_l|$m4of2erbn6S20pyjs(p%=q6-G4Q>8657uR| z?tM13u%v~E_jOd`wVt`j^Mh05%2MqpT#4Ix;=d0BU3fP5>Qo;jfv3&2u4m)z?Db~I zE+R8S&-Ws2P~X=d7es`}ul4_kt`6^e>)cA20L)DoU5_ zXyov{YGr#(8emq4AZCA!n2?;!7((A%WZ4Zi-iUCEcVB~#rzoa<$EI}{jb(Wco$={9 zo8jg#iOA8p#l<}%uA2AcnVPqe_j-4SrZRV)1qeaXYdmcW1=RF>%3BEB`kJF>BL4)w z_|M3z*mKcoDS-!VZagv7vEPA)+s8W?e@I&mrGJzTf0KQRG%|niaGxM(V%0Zi~aY)(fo7++8+xqxQXq9 z#$Gsh>${n#jCW&*_`x9mbm~QfXS)Er1P#FQy`!Kjd5X7(YQ+)y&2B;e*N%>5>`Z#5 zjLykQ74eLKBW*Z|{QMG&!+-Q1CL_h148fz;E>t`>^Ji+l2CG=D=KLlD8OMgi-DyAl z;V=}qw*A#NDm>}OkX0{D?IF{i5Yl-~N}wZMO(o~>A~ifsoj+o>rlP)F>S26~xvvB8 zs&B!E^4Okza0Ti&&)Z^~fslr(ewcPIrj;}aC>?EYAg8xSDjBcFy#fe2*tSRwGCct% zyz-R8Fz0o=bj#W|1}3h`xrYion&(V^8>!cUHiNru;CfIXJ`;)?|K)U{k))i3xD z(+(32Lc`7QJCqNenM~fJ@dfWU`%5aIq>f^mhZmX_V^L6`n7nw5iFIl#(1?mMYw~*X ziUrwqHm-vb>QjtSrPLj44}r#*XUPHi%{#w9hQtM~8-CbZW1<2oXfi!Wam~D0?69&G zdX2#%)17S%6MMW#33CxU1A_$F1hy-%0DtJ2fM5EI@O;u_;}wQ4@YPuiQcPgygh{mh zuaY2>;{_kUJtrRtQ3X9FYiwmmt^`S`uFY~QbJ4$Vi059a&;c(9Al9zx<<{E?1>SdR zDWI~?ln4=^e-v*tK&LM8AeF0|)}o38xTkZ$Cyo zMDEN816Y=vdS$}VF<{ zcIb!TQy?4+M_si6&hHnB^vB9jd720STG?#_IwQNiFr{lLsWCsN(`LhS$~k?O}a!mVr>mwPEZf@VAl;f>_LjZ9#wAgdJA%m5UBHZEU#r$7Cd8*HrQ z2f_=Qt^M~D$b{X*-dOfoSKSUXWG3QknJ}|BT0QE((97#=2Q7P}8_Y{b+}((Tg|UNz zmii>tXLqcf8PA5~P47rxUJ!)2sq2g^U(tv{ey?GOWLX3`u);k-W87+nrksw2Z&g6t zFeO7(-@MoQ-_Plm4Cdy6@+O}oJjn6*P^w2NA)PHbWhFW_1Y$(k(+b3u4wvj2Y|;Qj zJ7M`-yHR)&NM14D%XaR;^hCa~XbI`J6BxLY8U_RVJT7-NlV!@+Edc9^vE-orv@?cQ z_zkilB?P_y820S6sVM1dB~ORn{|B5I5eL)RczER1A$if92H&+hDK{-=j1v*!8UufU zuK%sOk5KAm1Z_ekhFKNmOE_YQd7lMfR&q>~>T-3_ok()aVP>ZuT4^w4bgvhN5xmJk zr%2M1u~ONz*3Xx;*QezyA(HNrZoTw@k%O9SLf4oqF&gjMB>OT?!53`1OK-DXUKlyC zW*kgFtX1v7ueT3HgTtYR#AVGho^-tb$eL+V#Xch|~ejjO&OY&v8_J5j#MzVbDJ? zCv;iQrXLo5R-|i|lkGZyj?`8S;j`(-l_94KuUG}>i=-vuaQNC3{jcppR%npjRkMww z7+2}*BY>4ggNUYto(UnCB#RoW<*02O?vObi_p5o{@ybmA6ig4HFN|G1uI2TO1ruH| zw;zaMqEdT)!|pk~rc6++N-s3C+{7f(o`L9m>^zOO0*h0LrE`s%&`i7hM7Yk@hJ#2E zzRuA_WK5xs5Q|QPIh?p`76ae+TCZ`Z`gR9U@})gZJg>``D5de;OTz{|NE&;rO@ove zjU0_#gcYhUn=Y!*zLt~Yfy=q%p3RA|R$dn*t&;AMBUDix1shU{K80?kIbp^tb z2?{W#AqATUCqUAXMyu^SxxZXx5gk)=vvj+IkV&u|l{^J#qQJqm3~F5q)w5qLOxKVq zM(|$waO%ZtL2#M!tj1zv7h?g&<(Mhhk78O)%CF;xZHiI#Wvc)+K+3-WeO$peXG%ng@0$cI2K|{(-L2(QQU`Ok)0~A(NGh#ZY=X4lMvs() zn$gNNRl{A`*yEVIw3p6Z2%3+V6Fzw1vo?+P_1X5}U?lV~&&&#&@6bB8=5cDWy+{fI z0(U5M*BoI5W484m01^DQ7GclOi?wSu`!aw7#`l+#$0Ee8kZFyB=kDBR9^!d`Bsuos z<~4Ffa3HF*btL~QmG%3RkIpD0pDtraDZoQ5p2qmQX&$aVsn%FX1o*NQ7*Vsr3kF9; z7g2`fZVm_ua?kWwM88XG*bE(M?XcK)2UKG1gHK6Aik-#WzDPaC; zUxV@&1zLAXI!*UUfyNC^{!H4V3{#$UIxfR|$V67}C?wfmn`@Q^aRaBrUALpBM%#z>KY}Qh!>sNyegDo7zZBISze2b!MbwF;uhL5UuG3p%&2sg@A zL*qRlj}P^~R}3Wu==Rtc=!$0Xy4jV5bO4&p`^?%sI-z|k6BSstB_WI^UE$-ymEk+h zJ5SS&qsR5^!Z*#@r8GB7?!fuqp&@rX5|%)HZP<#C@>5Q5hRK1tKW?GlCGjX$EP)Jw znQ=+yLc2Mo1bOgi4iC#3Lx+$s(R<4Cm>FhJyCl0Rj^9UGiK#^UWjV{04%{JtP2HLZ zEFbw@Ce}Za=8D;A_2Qz%J9dSaocHg_6r-FW1J-v~vZE_PGb39reCeqfg73;2`%=k1 zA)FwurAj09o!c4!ZC3{Iw$%gu$fIV=+3%t)RtsZK4`%kg-J^5BM7U4T&mE_j(c)?z z`{0G`Vs3#pOMKhf(6a|(`JnFEp;$6x=IBSO1L?M|nDL-y5yn905y;H+&N5Q_Ln}^G zT0V7?b?Io{G(>ie?GaELd%0DY5{xUcQzBh;K`TaRYZl}ICCe8TFlj!L4X5>0-@$6@ z|9}*OEp2%Oixk@1wF?+V1%iSKa6AFw(QA-EpL+E#1wZ&C5-Xe;E|dWe-+Y+|vlEW# zD7|DeMu!x={Ux8B_KxU2raOMgxkmr=VTsgHs=f=(FqSUekhe%EQX+M zhdDPLwt9=ZO+LoN*xCYOJvEh_#oqt9m*!S%(AQYt)_6;*qtDAjCo+5)&~)MYWX;6{ z2T`0$kz2)cDHxC{SiW~j+u|56`lNZcda(mff#9MmOTTDAUyl_Y3kz?6{Y{p3_M!=U zcX5Hzk^{foB9T>+47c*?ueY!!hkWuO=|NhF|Ee zgo4?*2C=T6=(h*ro;!HY|b?3!wx{KvlaX?ch zA8U?uyeb2wBK4OL`n-LHaQ`}{a%y<;(9Z&K>CIyLSS6q)f%D>y3%EayDc@cPb2?VD zH>#b?-OFdF9BmLI#M{rZ%yOnT16mTQtdEyc+KCBm;B*@hUBZ3BVN3uFW!t#j3LBS( zH}&?Yg{u7ag;G_^Sb3Bg;=VV6gb5~LqEQHTZ!H?Tdb3eKOMjPhY-36NQy32Y^=G>Y zYs*6IlIlotvhPH@;l0zhP0vr_Ph*rupfMC^OoH4gSI+5D=S=>P(NCl(cV%JBpB!ge zbh`0Mxc3V2-Ax^jlPr>cjB{Zs7l6e3?sO&BStboNW`3tRBcfyoKJ|J&m?H4YMAf-d zS0!hnT+O60F{6mf%+z7}%WM=DE|WXT2I(P0eOC{*ePr16x@SitOmsb*nT=7dBY4J+ zLn$w~Cblp}r`R~YCqXw`oax7kEB5Ps+_~LexfEez4-nPKdGLhODEcr{+?f-((8{za zZX(J{X4M73fI?8QvZVb6te#V#1hH&KKiM=PS^h61+dy#Fl{wKE$5aLQrVI4e@s`mF zKtuIN_8x|x?lmbhuOy*tpiSo2?JqOxmXCdm7zt?LJ18*;l_G%wDIawzR(@+rc0!V~ z|HwYPUdq4`L)p4t;lcBJ7m+Q90+i%peAgwe*(#$x(5KB7`)IkdYv@E`8%$bP&@DK` z4|bkoL51UoTGt)EG&YQ2jjYe4XpP!U4k&{{ho!Uc>r*-08o5oEytu{j(X&oF2OJ%L zJhKg!8gC>xuxC3Dw(L&WxaxU1eR7V;K-K}Ml|IqwnLeY4ht<={RQi9?zbVF+<3p@w zdE{E!go(~4!Ha+!uoyLr^X^ch6V0Z>m6?Jcw-v(j(DVrUA8N;}e>XGZq-W=;v6+8tjs_k#!h6Hvg4(z>r zm39LeM=t|a1AjdUdf|vNuI?J)0zCF5|>*}EK^p_Q$wJHj)?m0u-xfwgP zxgkzzHHO_NAHMor4IhU8J&91gl|?$oKXFLmlit}zz)zvTa8}H)&^PiZ2&q%*`1!d+ zn_W=RCCwX$T61VTvn5{ulx_$6jOPYxeL05}2Zl<0V2*Tt``QKqS%`FJ5ANL25wftg zC$JU7c3LYBY}&!yB>AY-axSp2iS~l%Zrt6vY%@l!kI8lA085PiFGL)_^KRSIU+1&7 zjqeIEM0zCSy{U9~#(816U(D$kU8f_>`Zrdo>c!HTN~rpvS#mw0(y&k60`Lr4@DNW1 zERYSTCro2$ZuPQToiBH8x?pRVELcRQlJpVrRBqTUvJwAF(Fq1>`R)9B6;&d%#gso* zQ1JD|R2aX3rkWe8KivobV->Ilk_@m5$;<_klR#M9S`68&A<4!#Yq&!KWn`i5+PHO= zpn8Y_&YlomraHEt^-!301*Koj#+8F=i!rr_G7jW37!A^hT8MkyZ|Ck^x1eNz!Q$V~ z&z|sEuMH?crVF49m;}+OnZb>0vX{1=Dd;AR3{#!z@+F;N0+d-=em z0U@loD44c6Qukfy-ZMMQuxW{GQ8lQJH@D3*cO13@%6l=0N)YaS^0D_guB%OadmnuZnApDhF2*A}2cIn~6X*v*;ok&kC z@ZyV|k)+8G@=d()5{|iQ8?={-eE;{~kRv&TzE#59gBP>JUeEsjr=z=r7(Vz)VNeOo z>I6AS{XROIty-<~kk@PIjZ~~p#J7)vcQGcNW}e~{p!^EDwP1Ea<*pG=6#?Y|)923B zhN(N=^Q)5yDs!siuN~~%zC5_;q9)u*%=xrI*lKy{I8t=3RxzTMfSH7nlvC9c)2o~> z|GIf0pKv6p@_pJeLshFmSth6BFR9qnbgy{6L!RYecQZ+SDu+11=<5iG9Q`_QBiG@C zf5L-wkNu=*5ZY`9D`#OSpA1SZoZp|~_y$5UbCuGO#T))xZ9Lu{mb%3x#4g^SA584? zAyF7|beoo}8LJ99f-NyZo0>D8V`3WHW%D|aQx?;t_U_w4b1u}F>HKu>j)6uQeLZD; zgL5Zh_3Bfe41=(WLlGO4Kl|fTv95x-X)$?H} zZ#LoEjkc%bHoLZ5C^`1SksGVYn!)7hHYtS@xD2P06$~BNQ-el$&S2~xt?UhCJbD;q zzB;YArN#K1gO`2!-nEqu2nBFt$)qbhp`$Jt>jwYrnxtxPR%(=`?&m@Fo4vy7B3NBY zI+UH&AL~g*ypin2UsPW1`uy=DtdZjwfDdb2@SePGJ^Q-t?D2klk9_`ja37oH8vDky zXg|LU%q~^_?Qu|=UA zR0%A)Y>0jQJMGG*?`9mKOK$NvzUXv#3&rHb5$61HdjvIZV}ro)$hM%&m(t7cAsULf zNClf+c^?SU{u~OT$Ab%15SPYU#J(2Yh-rn{F1(dnf5vDIo2-9jpa>*Ek#Tw^+%NwS zp!0*bMcMqQUL0(OmTh@5?;m7Edzbat=YP`{-+bqc#V z{sQcxJaN~5mi3;V4ba7aD21r~AV+_=(vMeg+LOd5IsWnBC&xY3WD{x^zr}*ivmd~p z+VRaNkUKUYUQrB+Tkm*=Dx&_*R)5)TO21IwSA+IK+4Iq^V#K=G4Nh2Bcbm!X_`b0< zac<|Ts3X=u8iSyh$y)cKlm|imv7s*E^gsiYULn431>ES?H3al?4-Ww z?P{l-P(GX%9Kgrtux2$Dj4Y3EH1_y8uT`8DeF?O|fD&IvU{R0m2HqmM1~qWe1glmSp#S5VzS2Pm?mrwn z3}Y4l7D)+=_-_l2)uYc$-aT(Zjx_>VunS$Rx}%{jP3loZLuaLe-DozUQot)_10qdU zEvUgFfX`cYgqGxtS3$5FhE2&x=gPq7x8hGnF&rbTWLg2(r`4%4-uOP8`gH*Ugt?yZ3V zZ65|67P7&iqt!<;iW7?McPT#Y-h|V@@;f%NrJhk^VFDZ^s{{K_A3I*_7p|?4!QS6a z`Ms$?idigs0&?V-6dlsQzk-At1;UHf3o>-;)GY{LtxXP)-x`QN3m~GoO+vt!_JWM4>`R?N!4UkmA;+eX`;AbU$m)Ub*9$&n|YdRhK}HT5(`{>rI1Jo z*gJP!ryK=*(&gSQyC zY0u%itiCH)hGs;XyIfSbmJL8%x|9NFe39|*I{3y7d9L!TA&b0G@#4_!rS;GFY_o{VEjJ7#^(O&j5elUD6dAfV| z%S5-Jz3g(zN z$3W)XsywcSvG2N@6-x2GeC#cvy2WhKmvY@Yv6gQczC8Jqi4nA`JVCI++)@~ftS$h) zymZz7zRub&oEEICIblU*^B;fjIDz0jt^sa|ag2gXU1`-@M#OA%HGg&<8R4^r`ln-eL1Y+FB1+&w%G?$1 z?fT?5jmif0X_lfVGqitEdW!M0>zhsfQ`&Dv-?^Dqqwfv^w!($c4go!ILdD1ce-!R5 z$Enwi=XrGipSI{|Jk^#=k8RkBamqVvr0X+e*GEi zwGd(?P~IGInk{jRnMv7|msz4DhFhcZ+v)6CS$-RGg)|k-fe;K^>Ph;=51t91M;}wT zu_3}n*!8cllk>k5V_F6S9wa_@*du|?_2dq^nAaSZr4>KK-d5#D&7q`8klKo zJ7oLQpPva){w@Ja^NsQ(j$jpGl(|6&K|7rJ1fdc355J)vMf{QmsdJ!*Yfu_TIHu#{ zWwxr5^5NAdNPB=U+HQmz7pw*2LYzy`29zzoL#fMh6L=u1(uJ-fjeDgr+z{nIk}i{8 zo+_t6Xk59ORj#|dP+Pn97E;Wr?2RJjMD9KzhEwE~%?1P!I$rLFb@R{k!EaLE6~YLN zzJ9o=$<)GRn^l=84iA@AI2^;`k2A%*Sj&UfYehj@WPaZU%?j=A( zt(-=n%y!bLHP1w6Vu!V=e4&@+Ne*MhYirlrL^T8J9)*6$GO7tPhuJ6bC9;hRgW~G> zO_|`Ykzf8qC}D6L!yV#+Efw@5iSVVtJip)g zJw3Vje79DxV2EeJ;!=jI=I~Y-&D4P{=<-61u_J~v^>;f5EmRv%Zdqtf{;f?mLnEr! zq5-GFsVfU}fNlt);l35eoPssLvQ_G-hVgQc+NbL19S)nZ73-R+V)J;0l`g8GlUnw2 z@O?4_T4at?KpJ4ZeZ_J*@Jm(N(gB81fSlPLE5n=y80NCTrLs!*AA+#cp~d@vt9Dc@ zMLScD;|pS4AyIt@sUX8qm6bKe1=|shI;a$)9)oLsmZQ!%d&6~$dOz+f+H$FQ(icvk zTr9_tyf(m&DhSgn(bt!<5T^iz$0o+~zi&HUvj}gRSDf_vRcEz-;FL__C}W3j#<-_^ zbQl+~_Zi~FocldS)I<{ZE`p*8agHU7IEYW)k@dwXf?}#v9=F|QE=YNJLpNu}2KY*U9(i2@ENq|EU@xid0`7n1-=_ME^m zU6vdvDBEKBp1+weo2#BzQaGk z25SN0O`3XL>b)d}y8YyMWgaBgvdmlf7D=>_B00Y+H0NvF^~MJVq}riLHeUXD5a zW3v+}6N^iJV4W$lAuPca-ds9FD~hKF38?>4i_V88I0vc}Vqi8jrEmO|pK9p4OLETj zhavF%)MWYg$-cBf`2Dfd#6|G_H)9IBudtu zp&J2dw{g1I8bkL5MU50!W`8ysx^$|dz^tc=@t#U=>@Ghepvi14$&>mr3(y+oqFllZ z>Sf@oXOR3p;9C4ZP*^wPRta>h{2#z6p49_DR6Y+>P%U^LEcwM(F$mnm)r2W5cd6?3 z@?of#k1PefaKY*ODqxbj>HoR61v{cC?Jj_^?+w*W>0&v49h07+Iv^(o2LpyB$Ws!m zQnF2@Tfzv``9%7S&>(AK8^|-Ntp81_)#b0{{CPYWjKtvgH(uAhjmR z_Z^GrE0PASZRms-4^Gqr_{I_fGaV$t>J=MuCXpFm&z{)6ox;QzZd-R`cFGFV@}8e|S~Jh9)+??z`Hhoo0#_ zh^p}pa{BRu4%Loxj+2zYPdc6Y!KF)6+IuA@A$1{5MFPSl&uNXd;EsGUd!`qr~z_saYf2`4~>0 z#JKXk+q+%h$ZIPo+T*#|m7MeTs7<)BN3+HMsG{nc>J>WMXgP6~K5NRtRA&$CZ34C}YDsdv!3tufJh)bGf zP^sV-zes_naY1=#!efy(vAgK1 z7CqaO8iPVTo6Lzc3qWT}Obua>tUj7FMj;~DgJI&mbY%C3*ndJtU6_d6S>bN*7j;P8 zKj;*jh|b00b%|?f^rpqFt2=Tgrq-NZ!;QsT90tbS@q(kT_M zd@y?a@Eh4MSvfFqEWkz?sa`|1(&edR=#o;aw5un#{i}Meh3RO2n~mcW(6w4TTN;cJ zij+(uGjUgwCx=qqCn0E4QxRUj_~!uAXP?R-al92&tRCA9?q6u%-5vEx%i+`X7yzSO z2vDL~F*5%!Y&q!;`#ZtQ|m_>0tLI26P3lCQo#DCaY7Oc4eHymsy zG4n|ipQYxlhx8IV;F$~rYvb*>Y39Gd(S#sxOGH~8wUg=&UN{HIJ$tkbVCgNAS31cj3&8=8Sm246N>yX@ zXHohK&Gsr)`a_Qnj$I-1dKzz*-Q}o+f=Aa&se;T))DG|sAd6py7cPZ5tz-Xxsvh^b zO8tWUg_$hoxlV=YQDTXU4~lbW4k@QVcxDlBDl6w}qYnC4)ucRXM{DI_-Wn6z`Yg;D zdx4(8T1qD+($U8+VCtXhX*NOFTtbdhJHr`W)A{o4Md`Fn`2+9FXC7i>JX&FgK zVuEvzZk*zBX(Udq`0wNE)sC+*lo{`PSZdOZK2<&nWH0CR4R`Op^_BY@0&MUV64VaI z-%8wmY%wK&`9#l4Y78r2dH2)XNUZ6nQ}ogTFqNf?RBU}m?q#T~rotIJJ|FcBmeC8i zRRq-fx>;a&mdn1`$X5+eWx+3EAd{g*M)puES&#WhEl&`UG&fh7%1x2Fn@;O~++`O_S^KGk8&5+rAqQ`)^+5^Np!y4xd zN$FBbO6s4>L0TqjWZ3QgDh7kQnku}BoJa%dIa)GwSauNIwWnoAsdZ7Ce|q3ku}M%= zMFcZx@rSbEbzQ)Fcvi^V#i1vRcGl$ls2o`?PmNvWjDZ>jp^|2B+|9zK2(hxD?)No? z{b-n+2;<75J{telAmnpm>))vp*UC45zX;x>>0Xy=a$0L^L$pq!RjPim@b4@Jdo?5% zX*c90^j~`6Mp-`nLN{(n0Sh*0%^{UYp%5(W*h86en`YH+ddMr|z0& zUs#+oC#)@!$7#LUrChTtx8LYb`(i!E`>>*In){Qg9fJlDc z@*9y#H8*^RhD`as!z0#frOsnoZGXR5Ds^}7rAPS7KF!?ba9)4g>RnaTI7ez@XK5b7HK z(Jg^5iuv-j*Y=X#Iq8qC&8p4A@u)F+cO#So_@&&W{V8W1SA`5LzfTm!ato=gVVzMh z$Qde1{x5+Vm?2KiddbTj7zx{zv*E)5+CDRx5Mje1zU#VY0R@qFfPtOMs*5U_Gt$Ux zv~gVtJ`N1eJIa8)(&~bIDs4lW{0YwuvB6hpo=dP43WcUMLM_%Ha#=|V% z^iLUI;Du01s|W=aaGdYgy+P`=ILD9Cq*-y9l>v*s=SE?xgOAFnA4hr`%ge0CIAXl` zt;vDB2^DqP!ZAg!!h=q>&A1Lbe*5&Nzuxoy)0BN(9RSu<+(pJ+q!MhKXtE-&5HXDv zjkZ=_OH)_U=)^z(v6o5|6!?~BLWK1s;cvD8tkyS^1oPK;`!4ukkz-3?) zx|)?@&g#UAcu_7gY>@BzIA?T=p_Tl%NS;<8CJDU40hu}-U9ENuRB9Gr>&P_%leZUm z`d#ElV_69VuNTU|W+&znu6!6Pvwun&1~F;Z+kO>%F;}Q&u<=WPH~SBUOpN}a5A)s& zLE=r6i;q;Wv-?2C)g)hLm)`LRCz+G;;u=n9vZ{orsM3kh6jd?z6Ht@-XN4{w7Ryu^ zfuao)o_b%mwio682m;Aac|ZIbM4$n6I+lr335%gADMk`jg2sJLJ_%4PM^U$wCkJO< zjtl@+{TRC9b{j(7rO<3l8PF%H|C(J2-_AJz4{!?H5;#QbzL~8ArvsG6SHSWCB{sEY zBc&6CF7NV#K215&3h9Kx@=ZudPhkt1cI`TKrDvH{5bPYyZG^$PU1;*0;AJjDbR&Jk ziv2TCcUee=@RIyJ-G@DT4A_GMY{3%%wZi04LYW@@)l5z9g|Nfzg6&;}MOYWmlu}i4 zI@po4I_guQ=p}E+l3jOsHA55koQ+mGxh)1h1y0to&a|_VBg%fzMFZZSk_nNHC=QD` zugt2xgZT}1n+PpavXAzOAJd#%`pGA>@n+e_wre^BH}PGH@%Tn}TrNOaC3=0IB?+N` zVQ+D1_C=v!9g-Uk`WW@c#>K73%!2r&sS~vn5q#1bHlIWgk}HlOrft?0BPnkhS2*p* z_r>**1yBq`Q`WS$9|&&hG#Eu^T`yv}_nDEY4nf%PI?_+Aor)?AxD~Jhy)JT^MUgF6Q1HJw6scRJ8#bw45n|QgA1CP&(4JZTJbX z1ygb>Cq8lX$dEQBqkU5T64wa665KB= zLro;r=@4i&`DOxVH$PAHn26kb%eFiEqMy9RNJMV?DbU#}xevhIG^-PW_EtOi2OhmgX9^}dV@h^=06_zX&rN@4`)Ga~ z6X_~obQEFmnRJBpD))JMuN&w(m6|u=TAFv;&!Wr$JN`P8ZRG%i)o`=oIt{EQjXzg8 zcL#*T_G)Vsq4PV&x>=P_^KyzDV7$K{>^P{ph3rqQed^6A5|&56o{;pOapiQqYtPY` zC(m#Npl#*+hI z?yT}%uCC8GgRi4r613x49`cslCO*lk@<{C~WI#n6eJAV@yJZqj4{9d@eD*N$fn5u- z4d48_M2P+A=wFeQjQ0c!L&d&9z1D$gsA=zOd3nRRlp#G3amv>#c2{o9DGR>{Oq{EU znI488t|NP+a_&BM(^)uEDoL4&qe+eidVEuR8kc*jAMp1)NB%n9K2a@qg-2ZuU^mKx zIHml*{c)ke($FSzWSiC$jNz-v>tl1K6SAASD_@C0jK;{?h5dtj(0*3Om+y;-)DJsV z0vqvGwWhQjeJoMpT9I6wG{9xR$pWgvhDvLtq8(bjQEZe&92tYG2K+Ws{cRFQ73t@6 zcr&TZMJ#35Y_P4&=vN>4>Npkd`GU~rnP@8Uh=+$bP-QlI*vCkuZwt^!K|_7ykV=b& zotnndlyV;cp!S8%uG^}U9cS49h&TMW#LJY?4(YwGrQ5_$8g_umH2*OCu4a0D zjpGa;r4plwHgnMB3OE_?^V4^4B#9zi0?U>Y>1F@x{IfkVK6<*%MCVNX_-IP=YqE^i z2om#Ku8$pu8*bI^m8Mx0@JW#(oLU3b&dRxhN|Pcwp(#-I3FJj$o2x1{sf{f~?;eHC zBzRR1|N0jAsmt{FAL6^mFR1JSN_<25^pYrs_MPsOjAXwTLjQj|qds;_RHc%ad6IAp zHoMV6cdBk|BZ8pxhcYvERn{9UnNE^gE2$pA}*h!t-}vG?l-C8so#f~=d3WNUJR;Q2fQ zuXjc56ac#iBF)}<_la9<{_Kl~aJW{83V4R>^QhS(KcjjlsVP#HxjY${8LLO1Arq4! z@}Y*3SQ&KBk3 zESb<2{o->#$~E2bb!pHUElr+-T@`CtU=03xf`S0P?Gzx^pq09SoS`<^mUX*~$}DlF zAatQS3-)5{U)VE=n(SaSSV`46dBmnGl4o;TVB@|NldqK@%uhl@wIzxYcWK9l zRBV$4@7)gCV9&mm_@ic3Jg#+S0c|jMsv+Lg0%jdl!(2ig9U@r!KMw2{Ivrz($11}H z*BKI2@2l^c0yXGCx$0n|`3L+}B4XMQFOD3uREwn@Kwxp8+tJm^eA!x?4@N9CNK%LL z>x)bqXS()_Bhd-i$RJp^Pxhjn1&MEX(=jsVh|OVj09xZ{lDpmGY`uYO#f<`7q!GyV zoA=zy)RvM+7=hc0m)=X?quad$R=XOumtSeTTF&K1=FXPTpR8&$vf=yQRr>MIT5AK-yrUjjGK|1G zc3|adAU&FzPM_1#IdpCp{m6yGWp_g@equ zeklg?EEw#S06ikm=zR7^EZaTg{f@*Hoe%O;TvwY8abjNA{wlZNLmwxMb}V4jY(+aV zc;==EFiKzB2}q(!QXfqYl@sz)R_CaSPZy5#f+&K{vpv$i4OQ6#w8b7k1!dRA&Qqbn zgOkElOfS!0Zbiz-?hhEWUgzzS;qw#cHKKR&iZVm3h4|-Mvl`Dm&0OzG zEy5)!rC5EsIzAkQ8*GOd=OK_(Dw2Qxp-qEnaZ+>aVU#{8g4&J1+H3vR^KCWL_Qm&2 zdwowm)5j>ld_Nw0`Y3=~8-=NRM#fO!9iX-ox|6i_7^GKBSM@r;sa)aZ30Zvo7jry; zU-0L4wYo9?HY*l)ogzQ(ifrxwD^6ImZvW*9y;fG8H>ebUJK2^U1l_Vr4n2wbwcxcB zbQ%UFt)yQVP}ZshghE3JU-h|QVPxH(&Offp`t2R3QOpA~axym$w|IEdU(M+6st1EI4 z9!QL+@2`PGhZp0i*S5krT1*DNzcM>iv@8uq7|A}_9=pup?#A^&c}sDeQMl$OVnYbC zCX$%^bc3Kt&{G>GL?>Lt@@JcGP$ zRS+Jhj(0j(<&v47P>FWhb0Lc?@~_(?#6KwBxm6B0ZaBZyJip67-2pGZ*NzPTv<&=G zNH$URxlc$CPDY>Ya0#bI8@an5kn7qGuc)I*n`p$Gzrjx->}JhBQK%c6O^OE7lx4F+?V%7dS2-#- z>#*)IP2$_B_m3eeuPHWChL^=zk?ClM7Z4I?5m3*w-Vb@w60(EP4hbK7^X3~8tJIz? zySRwv_5)#*dyNjlb|e3^!}e$Mow)Mx>rD9?qi{Z-m}94K$g8ZJX~Agv6J}j|HqD*y z^w*jD$6;HV=&zbE@L&f)0cryY`k&btZ&Ao4C+A=XYMx*<6pn{o4nK*Bwv|{n_uu4W zJyHYhq}&}kYLmfQ+v#IO5o=*HYLWJA<<@%S;&?)l9$evFR6daO=}3D9#;~l&kMZ$= z@>G+xI`Dg_i=Sk63E=HuCQvl53o>%9sG&+8C_CZhb|E8_ zB|FYf61y++&Uc0@7j*y?uCpjL&*=jJEikL96KVslW(SALGWNq+DV8!ZB=KTCoA*Os zB+(2yH)PyEin9CHCEwO#>ixqF$fdCJFugGbJz&JJnqIXIRrmaXGnq6+wSr^4DPFTx zG#~D^c-;~g{*0!*3!JB4fFO9?GSzXlDtJ1v+iR4h`*{<-lKe+d^qPMf{EUiP==?20 zGmUQT_!p=%Vr||)UMY(4J(@gz8+z*xgI7{fDMzA*2^vQa4N1bgnEn9AhToEAIX=gA z+5d@Hns=;PVT2=?dA4u)$*)H6#VW`JcJj99oauT>a3?);-6E4$hcvUUQj^6Jj+>8c zM>BA`?iR{hE(I07iAwVEXXKR&w;n)fW(Vn&?t{~~hUmug1m{IfP27rpIzU*oV_M!Z zKF{6Zy1>W1D{kpw$S#7%DpY9TIi2@}#$y>$!gdIDI zi1eAVjWjY1wHjK&Y}jQzRshxcq#GG??h}o_hWE{hV<8(fHhBlKtM0v}BzHl)Kbb(O zn=VhSsHpB?rqTCB3HBa-w)G4UKMjIrp*fY)=Xc}3f=Q1D`|9QMDvLCu*a#Dq2@Q;; zb^~5SF*R@U`tFc#ONS>=nuKY>E8fXmoXFcrhEonifH_<;R#su&>VX1bic-x1{N1Qk zR>nMA@_v)dyq!^DDbQP+4#pNs2B=Y=&}-m>Zo*uum5yu6u&05#APCGtw0mZbDPBee z)qw$shFP|eUC&|J%xr5OZ?v8#TklW#n*9_^x`EJ47C#grkeEPek5WzooFc_?Ki!}b zU+J~fWC$UT^7ZXLj7vS1<$;W)zOVjQF?i**#AeDdjIW2%>Mz*L9gy6$)y0R&&!F9Y z8gR(K$z&4K!b264xbyC$&2e&IIR{Qmingi9=s;QK5Zrd=dR^2hQAzpiuDdPH>WX;O zIX>xdaw<_g*qv7u+;pwq8ptoR$0!3Q#rS|z4CJM5j@FL-MssND?O9Ruh1%vx2NG81 z0yH9_2uV$tj*+Vsh5)X>sHb}N!tVMuQ%F-;*OZrRB7f91{!cJJt>f5%gC_=vj`rh| zg;t$g9e?5E%)>}NA8HBEr!=gGmOeO{-Lq;&Eb0c=Cn6QQ3)T-JbT@Y((qJ())56W$|#7JJFmJl)XAMPrPrq6lTcwSDG5U`A%cfvwWjbK3+( zPhyf6byJi5*FGjEw&bz#v~VkyZCJY$@n&9umK0PomHS66W7oY}ywtqDcmxF7USH1^ zJQe$@SLQ?<`Z0hvf1zUwI6hFo$0$iFf0KhM7HgAYgPzD+eaGNwuIDP4q!cqP31B?s zLoIuJw0=LLZ10g7*tFul9cXsKGx0c5!4n}2eerEAmfiuNS#CdWc}qMYnbyE$*|;pT zU`qK|Rpb$oHQ214mGP1&6`Xq0J!F%)($^@8-D&i7c$*@AtJ~`nma-MZp28GMz~)MY z*Ai@G9Acu<-x+Iwa*N0yhL%Q8Dtf{c7)^YYacvqKExpCZwL9>cXS$EQ0Gh)3GXQ!p z6#BpuX>@~)EZXJ{Hj8>Vulb63&qzi7rG3-Pp1q0wdOH(5$YJj^IwDPv_Xf!3Y&qc} z84URfyJUz0Hie@KejaOg2=1&TzIXw0E5TEl?4kuya$F6E6Lf~u8wlQixsq>!9wX|D zk&MmR5la!$l^P%+Wh@xk7H67{ye~u?(&eYy7}OlQ(z&19%a!8_p_?04nCHx|yON7X zZ;$d!1#PlA9G(5OhR>KleKCIV&c*~`|GZ0Ox+zJ}j1FW`h@wLfB=q9i0<=c`D#^Lq z*jnLm(9Sr;@YxZy(4&Wxu*ffF{*966HpGDwRL`~uEId%^0ZsHZQWc33F}&ZZ5`!7n z)>F=A+fN9HSAK_TRg3(gg3T=Sh%WP6yDH80@&!hqbx6@HddBAgMlPXC+|(S$7cKz+ z5Fphk{wQ)8V(Pb4`MudzPQcNw?yPB;u)Bo_NWQ%<^RGO&d!nSo`o8DZro>p`zm+gT z(BnH%AZ5nR@;$A3V6CY5CQoO2s8f!gos9*KE}(7j8D{OS84@wqG)M zCmi7{=ZEWt&OQ$g_eOP|YF?04S?@8Cv87&HBs&PjX2Wh4IgF3V{=n-Pk;JoqpovSB zjaCHmenz@H-ve9sKbb^HoB25aNk>98FhZ$wX9ju!(P7!eQ~-SWu`3_5u*`*d=$+Vd zaWzWg(Q&88i#SM`OfW}h6cWcam(&x6GG&UA8n+IeuC9JJ@hFEL3Ro%eJ|BlmnAyOj zz`5DpTQ=X%bLSOdra9xVIIjE{o}$O#Md?k!%qm@M?IU*$A|RLlq0S7ykVFV^WXkwV zgedYKKE2+tsFgH9J%1mhmxLhsUq)}$tBHQx4=5m$Pp!3^&zHN8wwatKbCy(Zy~TbZ zUM#7dG2qg)J*9RY%}c zH5VUXlVygzYuZ|;-NMEj!)CD^YQvTV2Sd*qeKt}QE(Q%fx%uv_$CR8!$;yZ@@9j)9 z>w|nn(Rmula4nkn0JdEy8(Ll9RbWuAq7B}v_Be>UR>Pwydn67}Ia2(cwQ)*>eU?P0+`<8KCsN}LlFz6qd2|;8 zSa*rN_TkMi#KAHZqOa7|iNW5u69tH?YoY2ZalnZU{p%TCB4u_-Nl9TT$l0Bq30(b& zrDfQvn8?MS51&CmD6tW z2%3dZi1`sD);(=_$-;6gMDcM<6tZ;4)PLvAaCNQKI1IeTm7CNKSs>JOiA}z_TN}eq zISEdvwFX%aS(k6mWz4)byQ zLbhcV{TtIG@P2(??K0$wio6j^2ECJOpN-FK4VTywvVr|~r9Bm_c(t_P1$-?x7R_$g z8G_-slJ=5WjxEvu13#j^ePjg-Wr^MXgnn3-eE@3@WT3A1LBq6xAMk6?$u+(9nya7w zXVjbJ0T|_Ul?liGAs0?!wB`mJ)lgo9tL~{#T3czWY#&}H-4&G&=S54GEUUh6+o*U5 zQ)WncuirVrM)iiH(t(6uVz1+$S!!TsdeKC-=GbetT6ccRiO=ujBzv%cgy#3X!U&)` zf)+qD(C9|ZjKT`>KbGRtPuVMl3c4bU-Qz)qS|stTro%C?m>iv5?nkf690`B206Rd$ zzjrROOXx^UEVZrW_*enB^ zC>V-82hz+Dj9GF&{$rrj_+wWFXGdoC0_m@^#<}fb9rF|%&SA#(3_chWgm9LJmo!Nn zm;$uYG$lm~2Lyw?&x9(&Uwv@aj(ey>`w&-ybkukQLBOpFh4i>#m?@2@fs79@33a^4 zdaise$O)zj)pE*K*QcM%#*OPQJKIX!*ScYfi@2q|6n&;4G(f>-aM3+h2{Ws zt&=&&pNc>rNX*xFjX#k5L+1F(3Cr)*POid3PEO4$v z{I&Gq5bnUWDw+QF34tS~aLJVSP`4XJ*(G3dXhoPX<;7`S8@tjk86bNZ@XQoM_lK|r z3~>`UQPrTcBc*Q>4-!yA^@ph<7$o5LWw0yd4`1j1c<@5zb#elj#DaJn{*{=gyFuYx zXAb8FEfo6o^q^ZmYwB3T;Q`J_GjD-|;TxW8^`NPK6#E2ivEbv;ay1S0epH%+#^$Mn48Bo9>Q9>D6Z5tq~V-Ic)f-l8)TL>2t zqw(W0YA=s897*>T+$u)QDcJKYIexYlsIfO(el{#Ua|KnQPux$xN<)TCmpu9ng5m^- zVcv6nJtWG-n^zJ)QD!PFSTf_Ag6WzLf!Mi=F&4%@zI89D_TL)d0aNjl?uM0Npr=i( zZ5->X)w*!U`2R6}27gx@y~}}C60hmUG<{N~Nc+u1Z47g&f~@90i&RI)B-e=}j!18n ztGqsupn!ez-z&#@)-{OQK?MUl8scII`=I{AyItNL*>}eTTW`B9W8<|npoxH&( zG!`mNSIwT@D?zg6ZOq8tNBflLj}LD3rchKsO7F z>jZ{cdb>n=FGs-fW+?+ybyK7j!j|ofNmlZ-;Yf)iU7olwI36GF?uj=5-|C&s`GNoU zD)ra+w1E~F&m4xHeiP;WlM8mFB8RT-_yTWP1`saS6DL6Y)sc}JpjPtndN-`{0$mb} z;8;S0wJtB>>(JnGiv(dkazy>+Vn$o>L6Cnwho7an80{tX`gef?D{>MHe~Q@;`DYyW z++#bBK^t@yyMNS>gxJ<s(uHeBNakKgh;@P9E64Eq$m;im+8-`w)}wmCuArfE%D8L5UIbiK3PYy-NV;wOFT!eio| z5+~m79g`d*)F=Ht2cK)RiZNiNv(V#|688RrbhIoP>02T6P=0pX+T)yqKFM=eU#3t$4Ao(4y!L|qk%+nyAqY_OEOXuQ4hTGz>C zH)mf}Twl+p#g*C~okoSK|NA9o!4U@9v1=Dv?B;OPU6u$G${zmQp7t|Za{8iaO85iI zwzFF>KQOS?FX6orAHt)Q;^WYa#$G%i@k^VMqiAQ@|JvTNg|tcIm64#(S)3PMHy6Cq z3ZJ7zqQ_6^c&)Z!(z(v@5G=z*OX!_wJq%ms)1bMRHS|cQ8ZTg~3Lp4hReeIt&2u{B z%xOS})(Fcqdt8;y56C!ft|SmdHJzRoMqDt+Q1I;ar^nj;`v`B)~zvWwAlNdERwl7CLSsxi|H4~2-5OFGy5VsZB}5^D}KaY#>A+~ z3Li9ge>hUTflh9lb_5i*uV69irU!a;JTTvmR8eJFYTbBg zAWb3mRi9N%yVZ37thUr(q%64OKQfo8cwtYOc{J&~yU^vhR4N}ee;D~gDc?WH_F;0w z4~auTXAlnN=$2cU6*WJvYh>FIVVQ4^xRg|iA}&i#r>$8Hh~egKMZ1R6vBHS0E^B#z zixcNIRU9xlU`Ty^`{q)b#T8&6@B`YXuAe9Ff`pVK;Cwm}GNhL}I(sMRVd@h3FhE5p zRVU~Myj;Vnvf0(M-G2WnG&pmtB!rO9No>c)@^i)dpBf%uSyUnHpqCS@@jw@q5~N8dRo(h&7;}*XQJ_eJ=?F zV#v1}NQF$=^h{h~-^8i*e2x6eGDBkIk83lT-7Rd-E#X|na*i-h^O zN{;1Sc#r@*$B3EB-LfZz9ay*#z2e)SYg7oSdSHn2`Ld{}(ga4H zK`5{3_2V{n-5F$lfd6^~nhPaF^DUKIn>-7%5j=D7hDrqDgrco^vh+Y0xKYEx>0%(8 zMF-JnPaL^>0q$9N92H^(X#<~{31{)5eVt4H!I z)+4PiSdG@Pe_@vHj0G)33h>fhQf2iHmR%8*&=J8P4|MUVLw=O#36t2wI%0y&V^GJw zQVuS}nf|?mx~(*N07c*L=b(#*qeoi@BWBr$Nl-bx9T|d13NjMqegxXM{i}l&(zg(U z_H8i{w$wB1*UQ-Er7pKY{@z}X%lJ;fYmRHzu;8?>*9KVy zI8F5Q!Bf_wV#|Ted>!Ubs>ikSO`@9KWp&dpv=VoE8`D^7+7PG(FN%s{UjdHWpW6rDep~Zl~O~<;2YPPvB z1#M2o5bf!6|IW9sWR_JdRdQX;F_`XY3lO`=CF1->pY8TofNIZs8h72odbDeL?OmVIL_(mpFK`Af zG2}b;LteF)N+u=y(=!n-aOr3Xq!)|5LdLa~i|yfkT?~te$JWF@rFMD_6PjiUpr~ok z7ILCtaL=j8A5QVGZ|IC~8)cpdt!Vjf2=V!?0*5Z_OZLHSeSqT<^f!~P5uq*OjR{gy z;5A#GNj`palNZK#E9sBPG26$6e%-4r|4LzntcYrophvgqJw$1>`$P7xU942s1sB>LQtkv%rVPbsr8`NbuPm5yYU(UYQ~C z9ko*@B{}NYs2%;Sb+GYzhFPg;ab%Y@+dD&LlN_06g7NTHS8(Ztx~hWI9n9)JIGN&L zh4kRxM=aZU5NH)?KRnsR4N*AzkRxy6_x|cHY3y}E@7UZ?gTJGYpCj1fF7k}aOZ=Oq zf;HVL5*LbOxDYVONm+pJn`UX)bW7Jh#}8Q{*r(W*qZpw(c%sH&6JIPf)j(RGqaPCOXf>A`~leA^S~-8EuXdVj`G#{g%jX2 z$reo#$u8et#f_6ppCySz~2Z3#ZHvW+3yYX}S*T z6oZ=Yu`O;lzN!Kg^+C7LIMCN-g?(kbf~Ky7ZpN5wt-Jcb!{o@1DIT#g0D`z$790+g zaB}0MmG>X;#W~X&zM?Iv)?*i%m_OhOE>0b;&ZLtOBxSg|{rH}V*0E+hIkrwtru zVy(F_mP|N@u)&>si(VnUMNkfp`Rf-+Wo;!O^OqZCs3CeYWB6~UpyYA{XYi|GKnL$^Pn_i3b&=Qa? zP%YD@Q;vGpoN!ATdnlTWO(P#g<8qAA4|t|FLBe;`sJJv!YK0`*i8;+Tk|wSYjqOH1 z;RY8LB(5j2Dt>g)d~rO|vNygh%2!lQMq`Vrbrt=v^IiHq2a`x*pHkK-6sk2J;&{M$ zW`vUngteIoS^rm$Y1yxIQ8ab{e(_4Wvw_(HB#NiLpiy zE43QEQU5~Ev+gq{yJ5Bsynem5W*x?%qs;iYcB(|Y#+jh+V%W83ADrhy04M(upk+7C zS7Pn?3Mm0pzKYj-$Sz&W2V$CNO+XxrS4nuleWN%_}r>6RPF6%S#7o=`{V7Z(jqn5oe*DoU_l@@ng*n`=U zWLp&nIz7O(5oMPRAlZCx5uP6r3!BBnOGZ*1%n1)y=p?Ux0Oa%H>+9cDl3hZAT61x; z0V>6y7D~o75DPufPVyM9o~5s4)g6RBV}otdum3}w^Ppx~v5N#hWiDkhV0OySy23TQ z-E1@jwLz}zeUF<4;yB3v@2B!t!o3bxB;&1?pn8iPK4Vhs0ib5L?Mbr$)=^9oos3rPBj^%yt@D2roud^b+OjKV(vj}UI9V1&XlM=J+j7ks<+7*hNJi-vZTooqF+cY4 z4eP2f-W^q7uZA6Xm#?DoT|7_pywq)-uy@%1!^_2H(|xKOAcP-jKLS$>fSjI`Eqf9K z^m48WV0T>Iv<*qjkf3}X?g9@ucTdjfN}(8;0fzEaS~%k4YhOlA-p-odZ9hcM1 zGYjSXBor-=_c{ow&;exB4r0Xw2CIrC*1UaP$75vH4D~J5mAofLyV(?$eBbb{)nO(p zBJt>BkVTIAK_8*(TuNZ1ls{*6SwrxM$I}UA$c8jt#{>n*v;=zJ>V;}iQi9mo@jxl6 z$D_*iyJVe#gSKeJE-k;XXeL1%iA3ccTP>35AUXj*!fU2iXLAQGu=5?mtC0?9iKjU` zDOelDr2u8G3xi}EKvFqsufLw3it_%e0O{z6ZIgt~IAhQ>3UTV*!p)i5Jw1wiEg-XW zR@M~skw|>hoSkJ#X<55?e!6&u`QMWGTi%dH{D5xSz`YZ9l@h-PCkd=PtDf{^f{DZP z`d$oy+y1mW1f~CK9A0{xo%gT77=L8MReR)NU3Rm@-iPNU(c!x448#Y z$t$Aq(s!9RIO%UV?-6Gv;@6LLtEL`)A1Xs_6VGeu!IP+P<545uF+u1MiS&^ezs)X; zX<(i75`jt&7c`jYpc!FiC+HBp5(J$Wbiy62badJWrDXGEO;Z0@W(7I{99EKrLbE7G z0Dn4Aa27nRw4IgYJ?^!X%E-2q@iwVS=daBSM57gKMnsvKpeybCt&dBi<9BlsViTVS zcV;PzPi2?(wu9z|`>@U`L7>0CYG5mdvL!T4`h5U1I0nM}AS-2KTS-LC{DFu2l>s4T z)~=Yz4GeaCgCsU+B2EnlA^XU%en$Ym)iEBs>5_r%sHR8FqN5Td{PIHdPK|m3Y!;f8h zz!Zn-jrhV`N^34k$$u80eubE!l2#yPkDF3*3=DF}bb141eyy`mNp1E?DfT=)7Q z4&N(`6}7v(GEm*^SXbOPO$a(QxZXUq{vtCDq`GB#Wn_CjanEDPA@31?Ku6A;bjNQ> z-tU@SY|F@5Ro%-k1vq^vHQV-u@d>*qa9wPQ%HN=)pn>?=SqUW7ado2BAVQ@YNjkvd z_pO%gmv->-+Flo$StV+0`DljSemXzSUy;SuRs1WOBJ~(ntKN8E61>4-9`kwA{K}Cp z?`F#k*_$jzAa1iDRnfQlTN7rDI^7nvFdrZj)tHP| zyS-FfK7!U9kLtXgnqwtsISOvE#4Wzj2~AFlwvGwXl#?-HmPxs1$4kD4+f&3p>$J2b z-deVgr1^?PkLYKAlo6-?@OQ&7Iec=BLzm#eUs>49D6_v0+vs`)#n2@8B^s*6$8+HU zXO22(1=Q^gSCH8>#PP+6oV*}qEsOJyJ6^4lx(0s5asn{Czvv+6aRWuC1dcgUPj0Lt z#^>`O4*KYM6=Nx$?fBmw0xBb&Q! z_dA~H;(s95qsx(qWOHJ6^wmaB7B8wngQ@K8j}34GXT>L58ToR`R2;b=x&1Pod5mYX zmYe0G=_Z($|A!n&uK#nd;B)<$NK%me5lGZ?ZVzuF(;{d`;X8@nR4()8ZIuE0EB`M= z32{fUU28J^6T!Bl>P-!CWV4VixI{d0>ES%1yK*FqM^kIJ-KLe$Vbta!Q`D`$p8+&3 z+3&aJC)EqX^H=|`ma99+Y55U3GabO(*(9|7g>Y#)&nTZRvhUC;xmB4s_Ww~U;TyI8 z^37H-8D^(a9&M9!)?AVBETk`J!Y@|lBzU6a*wl5U6bLSx^VX_#$4JP5+R?vfUwjjdMpEGtBIAj?n5S@3#McF@H zYFXy0L20S~6+;5_x{oSlAaw*0o)0yptbVzjOJwsfUAtC$rAtnMAyMYir8QH+=oy#d zV$xMh3v>sdMj+^#nlnU%aqlwG^glzD1+*Z|KGaH`hf8$GL5-OqukngFjsLJMp3n z@EzdN_@hJ>ZdQLW;D%tsi?eP4K`uPJkX%>9vzd>!eOgGJqpQ3_L`tuR%XCA;5DN@k z?IMFA!03L$=Pc@lbkM3}qs$#uQwWobj2&NE-`~qZj64X>hZxvdzHqH0`; z?-S(=qguYgDz%k3Kq)13ElZxVotg|PRuItYdHU9PH+iGvkbKOOOz>;X3XDSM89|EP zdv7(s+bmjZ%N_ggh7^U)t-5~ki)Vu6`^b*F1W$~@*u~L`t*RgYZjt7kuuT`b2B2os z_YM{3C)-sxwhf1$4@z`vG__hB&=QyC#r`KFef~!dQ+LkygSHA`zx|H=^J5QILk(~5 zH0a%Mf-y+;T8J7kZ7|RyDGV6N8LoZBV5UC*i7+*@;nJN*rIRU_* zhv)}qbF$99d=S^_xjZY^nuv7pTWC@BFS6SECAOwLqM{)e+pCp5sYo4Nb6yusW~@$q zN>+vFPIrlg=6)22z(<#K$}$0NoGcB?1D!1UyG7rg11+Sit{48O?vyaFuo@CN3w+vM zv#%5Aa+xx$+LvX6Sv&B^z^omyM&33iXN{2ANBbqJ=bzwy_hw6CTUAi{`qSUBINTd= zvWZ}rUjt!vO$VsI^OS>;1#t4pGZYu5_mT_<)xyncrJ`WvBo%Z2znC3;FPFh51xq}P zFgvw|>Qx5?Sn27@tRhq))py_^>(Bxz(51VSE%{-zJKhR!hFm%>NvtGf$xT!E3Pp8P z@7~C&?PrzESA?z}JhJG|yUpO$I}de4BOvJwdz}4i@_m^&`#JeSI1YeLnJiL{U&+ZS zkg=>DjqnWO@H%Zo?(?B2CM$0xDL*5v=M^>IZVCfe#QCdq>7BQ~WlypvwRh3|0LGiN z_HYw``)UX+z~(>Z==oZ~F-6f!G4bn%DulKbc&FH%OK~*9wO)?cYY!6>z)KWTu zH<(*fhnPnDsBA5G?#vd2a7!WildV3!vOJJ)Di40DW(CNGxJ;zf zfEH*G$L+v}r_G_H0}yxIZ*+0o_v!;>KU~F$_btf8hF6zQHe#&d_uEG~o7X%&Evz!X zm6W<#4D$LBWlpjg$85P2cDf>`{sB%XgfgD$6%YkwV77na{V|<{iWY!zsHoNkS+et% zvv?f>3S_%~>$)~JcS8=A|NryRh08p1Z8YuCaOfF2V-*$IIb1B84)9yxnfV#d$q5iD zAE%dTEnW%t%0AOwP#<#_wPy6&4^-=JiLx4j_TCIx4;rPH-lWGCp&;l#(5w0WRx=@> z1sLDp2OFL6H2{qa0>9rwAvBNnF{bZM z4NV|vi)M0?!A&%iSdMvF@a>h--AbNS>gO}wYs=UDar38FI&Nb>Z`_lJKg*D>6|g-X0FydO+=w`^UTp#d>)F)7jhsHV zP_7~wOkQ4IN?0a6q@MQ;##yfP;{#9FGuN@r1o2+w_@OU-VYsh zT=&29%dgm;nU#O>DOZvmTd+`iaP{Qi>2khGlhfly{6D#q%gESftH-kVB7JmNf)0)S zHQO!7DAVW$zGD@|FX@?a8{<2dl*t2{GU}s=p>dou8a{;ql1YXu7LuD8%P$FtmF_u~ zueM7YFHmWeF?COYNG%LUFOEYT{Bj!PjM8CxBEvKONFVx1C%30%J{|T-?7c0_`QME2 zHU9;DyKz^1*5X{;VNOzszhS=ye8fDunusenHM>DOm#0K zeQo&@Q>2+!xPEZo&koQNp?_yU!aP^)k%Idstl^z_mP%hNB8}eZACjzyNG=7?wk<1& z>f@I)z#&l}q!8iUrQkM!yO-w*wgzH~8v=|eQ-Wu)!PPxNTy$46tTvIE5pR#gi#QQO zEz9JhJEl9e9tL+&5u<_Rrn8|gi>r{cTT65|Bi^gbGrtVd877=#GTc2BNXnE;mbtI@ zKFV;U?9`5C8%LUD{YiEqeoHkr^+KX=;>75U&}`#Jr;A@==iFDPO@i=1k7LwjDr|pL zv&~`!mw2u_j(F`e;&iA#|i)>ON z_Y|PHvl^BS!A;pJy%xEuti%`MG5we22H+hS^4@&SabDi^t;FX8QxuT>i@K;wh!0+b zQqpE{5(1{*%`=?Tv2B|8Gy~a9clZuJ34eH>>CF5hu7#oRy|~IqBCD0{6p+>X0rm?e zrIZIeS|n_wmrnd@blx_Q<1YC}^{q2aSZxxlK5U!;YlPH-eA-@EyoWiC-XYZT##sr~ z`uE>RR8PG2)-w^%0Z}P<->*5~Ao@(^8{J-S9CEtDL@dfzRc1OYZIRsuzn>Ck+e2pZ zxgd!HO0w$E15REFdC{$Nr`zzVXBXQDD~EXAR3RsUlUO)@Pby01je5<#ouvBHb zl_f!V!fB8*$EtFz7#GMM(qWqHJ{c^k!hz4rwWE96n8X!d>@F#B`gCvp-I#3_bA3HS zpvLmqFLhZp%U>Detc=35qNwu!e_1VShH4w8<{ zs4+_jWU1hoDO?`e<1mBsUDFyA=;$}xas&~$DGZL`XN0Zj?%L$)b^j*sk7J{g5`)b* zFQ^`&c=^9yTd+Z3OV9UazhS&qMxREM!qC)(Pm;VdHx!FhD8Qy*a?ZMPZe zBzv*UV~J4lXaBob(rZoINJ1DE?Yox>UM_p1Bhvy}tUXvlQq(t>{+IMYKPd#<)~ zZ5JWEtYn7S-z=W$cynmIY~zvp0{&2d7{`Lt6BCDU{DqJqDlXOHbLeJ7)Y-ihnb0tU z5|(7^PUn+v^4Q<$fkp||C_1#>VW5D>lu>fVmddmp!BgP_;$$|NgUAa0VptTQ0H4G8 z>K*T%Au%f?PhrW9%;O*Q&8;|tW9O~8Y}UNwixE2N2W(7MP{~|xqtmE$IdwCrcHRSQ z5$hFu^bDI=7Vi2;!WPZGdeGq-<1pqb5HZ4H9Lx}|`M;LV{D<4tHc@hT`Or*_|%L`Ke!GvGeu1JNH8uDTSa3QdO3@=hqQ zKxs*t>2mkylkk8UEMsXpx8Jd?s>Z(sJd1l$KYp0o`sM~8*CI77xIn@7Y=hSgM8;B1 zNIHP2#gYU}ez;?z(9l&cpc7m92KiA#aVY*D)*6W)c0rG}PyYzB2tmw}{py9QP1@Ly z_2z{}*|QS`$#Z(reVQLstJz*^L0uK)n!V|D!(kjdhBSqk3S{EwnHuy8h_(t@HvD9{ zvr6vK+xgPJ9*$ecF;B7=(n4tC_Pw`QEdHyi{x^soKu7(sB#=`nU0m{kZh#IQAkoF` z9_$MAa?RTIK)FSo*fBO2x7=hmwEUsKHaED}H1Wx$Um=*f>$qs?o@I^n4~^2;qdhCx zOqpJ%TwX0~rG4VUFGa>YjMAaV@qraB+&0r8%n&D&J>wG;2(ms2UH=&jZ4A~ zv|QnvQzfu7jwAWVmJcw#m)}8=Y`v@N-e$~H>yFXruT7i#M$0uBWbaiSv<2{$ETFU2 zS-!|6!k>D1FtkG}8%3tty^g7S4-Llh2Rp9bP(u?mDVW8R8;*>T7{)7h3FQ)C3-zJC za|CVxA5{W(;}V9UDlc<4$J-JCe{PgHKOQ?f+}v5?y==B&#f0r#<`MPx&!jY=%-`Pz zM{J2f@O!LnV{o>Jds8u|GG7N5EUq=oF}>E+;RRm3k`e6IV!a+%ZbTQv!$_-*?R)M$ z>jxv$1aYgRaYK-C4S7`hq2prPkVZiC5iXBWQP6v+^nkEZb$S}>)nn>3kCAzsQ_W4l zd->bz9d3qc6nbXsLkI(Kp)v?&K~4R6hh~x&wXCbIgZTlW+M{8HUu(j3tSTx>oSMfI zccxp+EX{Jixl>AlszJ5(A?cIW?qCws48R3d?8{Cx**Rtqr%_;TpHKU~G`DxlP&&g| zstf3?5$sBZkIcM*Gq${tL}hr`$Ti7DTMiNuGNZ~k-o8Twc6XkbQ?Qk5j{zQG%Pz27%>en@I!fD_r~-9PoW^qWzE zRY`vin01>jJJqn#Oby)lph(E;o>>c`^dsFR-$h#?+fqpdD0;QHAd2lX^@-kO5At2r zdn1gYn`SBEvl6JUeCFWQU96tZ*RAYX;EP{(lbUj$ja`MDWiKz{ACVeN7>;u0i%}R< ztuI>zz?*1ZO?BDmzucz;Oqt4gnb7`y4r2jC!<53yag~+QDc1Oe=R^Gg2ye2ZK}>_+ z!GI1Yb!;CSE8OBJloqom+~z7}KO-I3yqEu#8N`ByCNiMJ{T3bhFIye4R z#GlwVU@n!*=5Dgv%Tha}JOwwv``E$u58;KE!?^4(#c2OfY`74GnN>7ejqC*%=3mV_ z+c13M-3C}d-M3a^epkLixmerz2kEjQ8s$0QZG^IHW!B69OkHBjB;8XkPOkJ-r+3Wy zNeP8$4SYf)h<>aNk@f_>0<7`(8n0pvmhr9R>w&e5fm)BV6L&!05IjRWuG z@R)t6P$AXyWI;E+VubJ3!YKBL)BC=eBPESTZ0QHEHvRot?0~s*lh$5wZl7&cXcGR) zP+TpSu2UE5W8>Ts>k^eXcJGpxB>~~G_6@*e91ee9yM%pr>mWu; zsZXMpTXdj$zjG}e6F3S<&>>%m2-_vx&xSd?k<=J_rmIe|%W5;N0)R+U1XrJQvxKx_0FSAGw{m{0W7J;lYB0lnc$EuA#kU6uK*%{;Q3rkWf6pP!vtw8;ug7)hwW8uFfzxk7BDPDJjt0@XjAN~~R0I493>OE;EuvUd`ZHc==68>{JP7&5g zJi;Zi1zjNN)*2YisAqsddksYO;=)!?R6kDy%a98!r4VQPpf5@hsjShLI$0@hnS!de z6_`26^V)Y%JKpL?pQ&JZ`~Po1sVo-#w=P_I2JdbFsubp98Gkl*^? z|J{x_m>OA1m;$A;1B+ZHC4!ivi{-I#%9@POA%P4vpAMUmM4arfc)L$TP1rUP94?HZesx5wH&{MN+ zpkxmxL*|Xag7&^rC3|iFn*kYZH;vXXl9QD_Cc?%INv$4Mm7z;L**MZw5bi#Lxpenv zqynZKWNXc-!65xtn2|b|;5X$4TN>(7i?rLk?+rhyIIjnqIYA5+Ko0{$jRS7YoWPR* zL=D~DGbrp!2!CUgkgS{0DwPW^4Sb7>&2NEjZP@z(8`Dj1?FFWd5YZXElvN^U!L9Sz;1(dHW~}$5Y@LnTcc5Xk$xq&85qz~9hjlna_Taw4DR(RLT`B7iubFmiGPQN6 zatPAI>P$M>z&{rNip3DY5KJcwxFH>YVCpZH6rEbrE{DPKVglUGwNQ$Nd&J0y@a6O`l36e0+!t~bsWv1aQ|3e;RL#m!!&>QLv_x3;c5zuaLPgw zfC4U0Q#_Y&$QvD<0(94BAOwI5_8UQaX2-hyd+>6+A?JHa2?Xw_dN_LL1Ap{M8rsXh z0kn0M#K}Ooi2Or(Ae@mK3%Pm{TsejcMbnLj&ISj4HCGv=68`qDi%DUH<}Q1Bo9@)y zJq);}!zp=g7ufxOc)q?+aOk>|2uhbMe&9nr3TShML1mXS=vz8 zEjCf>A#P{V>y4E^KjNKVT!EHM0bR59rvgUqHH*mZEJ(q==8p$eqGPRgTK17Z^>!2cHc5Iz6wGW(}J;jo$5#+pPCTtCw@D zza^$3rIq&7(};8+p%kAUil#oL$RLaFdnz<6Jq+KK0#ekmfbNVKk6`HjUzI$Z_pSA@ylZXMok&`@#HS$5$;bTDVtVaUAHD# z*q9|_-nZmdStSle^hn!j#$*heLBVV76tV=k_K)pM6HK`_efk_BiueNbSxhfkv2q=a zZH6G3(h11BiYP!b)t9O+7{aQxnTl`!&;|YU^(HL`lOE?pii4d_LEmRolHR$RbtR7y zq)B#?$g;rqzIA*Bea{$(BfNrX!){xO0u-08`7*3Yn$iC-hQ0KV(7;nzY+8jMBP zyU2NCkIA>}ag;KqNHqJk3LBl?8H;fgJ;}&B{ICG;G8;wWMGuO7?=+xS8HSRF&0T(F zj~Z;d#MCCX5FtP<-b>N3LUPvKEfpYFaFTcaO!XK+{w>M)NwckcHK7IPbVi2#8UM#j z+C+_iOoW%gNi*obXu|-cn2y~DTvMZ_LTUK$_wNdUHpcP8EpcyYv+qIQ6^dSHgzAMT zi7`N*n8yp64n?7m)@{gY!n1>GBkEt?2(&Q7i!mIQ@`Z9O3cN7oO$_Yyw>w{VC7=-aQ=&1v0M-H;)}_Es zW`o+#8MfcoEel^_S<@ARA1FxrMTa2&04S6Op66UX$R-uJZq36Y9O|R53I1(Qa}Ve( z-x-cl(47(jHSwgY6Y1jhd7M_v{iwzMs9|FwuihxG$bFHIx9-~Cb_P}Ej#VNF*Nn7@ z7flcDu4(;>%bmyVmCFy=Iu%^yoJC+X9dK(U1k|!@Fru*&Z+DE?37 zYin^zH?e3@yO%+`;6^&cxWX^zAK$&U_oVb~GT=iC4?nJVA1BKWeJmGiC-v90?!zvm z&};#`hbav+<*`k=t&xw8+D(2_9Xkj33j{ zV7uu?TP_hJ*pQ|>3vs8R)ibiow$Z3Ew-E93*cs9IaE))RPfAWhKc~(nBv>XLQPzYR z$G*{4J;)j)A~SLnfH`JV&e;^<^~xfitH^kBLdHVlOsr)3i>|Me&yy@+%T;3zCk6$c z><^5Omun}#yY50;LYr}Ne)-hNytetM%N{YoY^`RrlkF5d9X7lAg?nGz&cy6UULsBzCM)MWjxE z8CT+<(L9zA+Uktu=cv@==x)z)if130Rk&_yuZ}gvxdre$$;!x-4E> z;GPROymT}?k$&xw{qtQ$f{3O+m*maC3S0s~;ZQV`H;JP^aws~Esf!IK@El$qQm{CO{* z3)f5Lf31$Msb5Lcd@gr~jgBK;nqo9+kL(3hFe2!et!s&w*s1|>Y1DE#GiB=o~LWQrb9w9D}c|WOa7LQIO4US|9Gbzi4<{g zPq^7Q0lDb4BskjL08T)$zv|h)z_6o;DxSu?OK-EK*DW4Kh5C+S9wpr%{?V?iDW_OD zy%ET#__8KKodU$RsKNR~sCz%R)YK|y>rT?0s#zA3ZqLMhZaNPlH@0K}iwFBbihqOu zC>XW0;S7-uSzQPMJ_4Mmoeby6%2DxA9^=tF;%wFdGJXwY0vltCSfBoyx`4rgOd6z#tn~@~sIYN|eMZhx9A%gwPoSDA15>0aJxn zHK=ay_DC~hHqZFCTCY4RhG2QwGjaV0?X~3)Pec3SoQ-|k7Z)lgc?#j3xwM^ssyboTaqOd@{BX@ zC~3P@Y% z6HxJUG0#~vt5cNGJQ#r(r7oJyhL(abKToniR=;!rY`kd{a#_pOOZndndCU6#s{Mv( zo$S_dN_9)7O08bkf7ih=kv-+xx{{|J|&9EKz;*R)) zP>XJxjumo>G-=6my25BgL?r(sD_`B*n5+b@|M130kkacKtk}`Q3gF23t0#?sOi$qu zRdSkCt%A!@p@=PMnGAU?&T^pv4R2;EU&b>)A>iQkBMg`PA1}$JIctEzf#bka_*y7I z_#l(yRj2LON-WZ7Sqo8h1hQ%^=CUVx#4%N{92^7FOY?!jp@5i7?0bJi7%oXyOFQN7 zrWQy4&9WtgQRYU3f+Zk{PcZ8WIsoP0@zi1yESoS%1Bu3=B7oLuVcwQCS0srVx|Fs& zatwn@%4553p@QZiH>Q241(2J9 zC^jv5tkTt|WcP*9f#n(Mp+N#q0?F;BU%jn-7QZDJuI0CEL<6P#^Bkhw62OAG^g?z5 zVWTsbiHo|vUbM0!i8M(iV2e|*0x|Nt|N6OJZ3hWFkgc+o56F*Sx%0>JMRrNYaGOAd5g<8GR8Z`24#F3I9MLyer9$bb<6(Be?& z+q@&X{OQ5#5}^&P0hc-ABnB)x@6*lxfyNam^r9!8p_#c2Z6#7Vj(o9GnGJ!o`;A_e zF{r2|`jaS<6?zdPC^e9Mu}v&!){1UJk}SVP)99UdEeS4#U!6q zcGf0v2pFc^#Dxae`y``l3#qKd2FL7c9MW~OvO#jXKEaJkBC>OG-(f?Kn}yM=Q3VdQ zOr;($qVn-UdV|QC=M+wr@rr&lyyt$@jSK?k>kYN{#8vBqiIPVUNex^dB~v;MkWW`f2;j=H?5A+ZGEWZQ#y=Vuk@7=9Gxrw=idMpl)sF{V zKxOI!y)@399v)^{`BYjQlbC?m7o(Z;`huC1VyL9QYI8IAvPV~MgA?4^HDS$lO)-TxNQ6x?|& zYDsN&YgVE*gy$$@iI_T7ru~jpKz(@8;%O@gh#qLSas&`6tSQDKBC>6V2pN)csl>L_ zsH7gPB9R}>RETQd*SI$YQy!z}D&u#LS)RB>{_^@@D0{d7*-B9+lq|~f(&HTnKk27} zT4VOQT_+7xy(Lu^H8P5a4Bsbq4=X?fs?4?>|;OFfa?fp ziaP6c1)SF!06;+FdwS{=VfcE^n(L=vLV|*#1kG$P5;vqv)TaEOI{3<#%p)xsV`b_1 z^zy)FlAFiRE7%(#fAHhDn`nGz3}(YX$5`$34xCq{{!>Vuj-4A9EoLVTFggY28}P6< zd2zYHkzhsSd7;+1Zx$g*pv5N|>I zJA^fcyp`@_)6lHLD}prQ&ZEd^jBg6X5j}*DJI#v- z?atmY+`HG5=;CX#vzpmt=EkCcE z0$Xq@n9TRUj*1{}(mfpxlTeL6U7idcdzpg1l&~`WMu+;<<$=KJ&cX{@Nh1gm`ghQf zOnio35DlZkzRCwa>?8#O!_-=&*$s=hz_FM{0vLHz#$g2Snx6i!p|f$IuhjwZH&2U} z1Ek#SYPd&W8>PZRXtlDq$Hlq|MV+os!zQL*f1o{hF^Ei@$<(77EOM*xlCNw+qW`d0 zjd%Ds^zDJt-r>*<1sr|*S&YzbkOj-$_Sc~-bz^K&f7vKPTqPL;8B~nN+h@P*2g<)o z;&&9EFmhH!QniZ^Pg8lfv+COy(~C$m@pPloDqR=D>FttVHlfpJHwKki-jJTUd-Tw* z#3|WC0=tC`L`s|YfD$pHcx#(dTM9*Ie4$xAfQ-vb@`{Wqk-;OrM-_L?=|0iJLm@yp z`-qh(%=ryz*q@AoLT9-g#tzT?<1(?vIM;i`@J844(24G2ij!QE9n^;Mh zUDiUhsm{YxYieZ zzmTj>2nvD+#})io38sZAYi-vq)3d2zp!OJ8GSZ5ej7Dl5U2v6?y_No}Md)iA*8Z#_g&B zDKTNsz$`6BKI~A~6Qg!R8QM=!$jyqDxiu2@?4@!C=7^q$5LcL085P|G z&&f=d(`5NbwHekf`c8I+0F}STc?I0|#E-@by~S+1NmWtELco8k3%Yw0UTEDoUui!g zJHlSvNJ>2O9f5mrv!U$18d7L+X3{812q^|zS1Fm(qA<&#WNCibJNBIPr!*1(1}g?7 zfJ__qg{vi!o#uv~CP|o=cNpC2g2d=_b>!3^&QolveQQ1v`b;ib|0I#$%jk$9J6vcW z1S0*ih|NG9OtC3(1Y>-`s)S2d*50_O26@ZNGfZqlIHDYTxZ*y2KZLjpSC^s*JZyqF zZ6zMhOuaI3W=eVxvZ|J0;;7Ovf&b4FnZ)g_&LyV@53eI)fjmhkeBdslTaR*n+~u*Y zP!TD-f&WPulJ-zDM{q3rCSA%(ABh_@*4q(pB~jILifd&7LNb>(`s-1^s0Z|5ebGsm{TL~<8EFQB7o4Eeg zb1jT28jY)%v_3hc%Gxi41FRn2pb3L+Sh|hPmixI5sPx_V&b3haaw{LMObxdKmGL!4 zajjHS*9CA_+c=pSoYqqaZgdbfDonbFRj1ipvN+$Q4hn#;X@f`r(0u_Zm?a)LG_5-Iil#rBqYj3 z95J`z8#`u!p?d}$bLHBI58vy?-47&tbA}t2@@tQ95#n0{-uY)?tBrxyVlR&I$j7Z>hvr=MC(J`b=Z5d4zWhmy}<&Oakj!~c`v~6;DEkKSy zsbp=ZhC%G?>(N%%c$J<4fL3t7L1a)2@418Gl_FxHfcIw{H;_puq@nnYYO2w9Mo(K) zY_#H)6G%UBI`3?8UNmSX=%{gT@DD@GB6~oec6}mfmkXQL}m>i9r7)29rv^Nxq`+*hC zCNx@cBU7|rnm_u_`6^%BV<#1M2;#Kpuk2>GcJft(He(Dw6*|&D5<vPR>^@{hzL6g@QD^(}yi<2d(GMNj;cgeX-mE20<2-T(j zM$6z4!w@KVepB;2*XFJy%ogS&7ij9E0fyqwO?a({xytKsRAqJV%}FP@WtSH%n_P@G z@LC*%r-iXBu=H)pNd3w`O7uqM?l3ZI8!|;3j-3%vxo!0%(UjsR>(4M|Py=K*_Ck_# z|It2SQxno16tSY`EqG)k0b~sh~|KZ7TA$ zg$o=~5$O8~a=CDnKT`$&Xa*D03XWG$SG8^JOeT$tS0E7T*KtU@7JLxrewQWpfbjt* z?|S2b=R<-+>HlT4ueB0CWIx(5wd4)TjDUS}W*o#f{W0tSo74h0VF;Bur)?nEFcn4V z-zpdJ@ z>hqqkoR5Zpm}c$7ySXm`i1)GVWP7qxLnK8g9(76B z?@R*AER}h;8^Op(o&IG7g_{XUZN*G+i^8SjQr+vKmD=W#+eOYNS#4B{S=4NlDB*OS z)XflNGjpLlb2*o}7zzA!hV0ltX#7YwF8l@p^9!#yhNV#Q0T!ua>2(#@p$Lg7K`k0S zeK+pH>Ij#m7$671v<)O4=`;d2oxvMd4!xcDqW3a|bpZw^3ITD2>hi55Asf#0KtPR)mM1m{?rh` zc$qx@^R!3@7YSHY3G=5zf8Phb^E;nSSGL3o5jyr2@bn{^RU}WCL113Kdu1Pl{e%M} zT9H?U&7DI%fV3LJTkBwhLtvZOm#4os$A@}+QaTXt{5^@MEerF4r44o8_}dB0USjkV zULzUi(K1vNWelu;@0xyuWVqerC&+3wQl0?;fP(6IV=MJ3P7WRvjQL46ZO7xiA>Bs;? zXn3i_AvsCg&ylHQw-A{2sA^X*3FlcfL@u#Hx#jLravpXhjKJlL$~Y%l0$}LP$4K$X z_PYTkE0rcU`MOk)a=2Z^W=#hLQ7genQ{kJCG-M307qzo2{Yjh0p;;TIcjKY%mv^RD z0w(5$>}US+qjL(-Y)Q|(3&gyf2reC+DTF#jXx_*(06%Oqsjykywf+JwIjz2uO)}{$ zi41b^Z+JgS9k2I57XXpI)->dMLw^%E)6zytA~q-QLqEY+6gTOj^FlG-)U1<7@jx`V ztu@Ygf&3jY_rLLnGCVNfX+0nH+%08LZcnV-bx0+RJTXfeeP-+DD4Rqik7*3`ai4&{ zJ-}}NG!Bf`aglmINLWwzdeoc>^#8)}=#%lohujf*AiuSnuSO0!sfFIA*&CZpDCY@N z*s-SD^%k+3Zy=d#W1~Z+K+3Bc}l)qC!;JzmdyjN%?XWl-DM+aztlrxdkL zN^~phh=J=*2VEqpbaeKG5h;c!vPF*s9AlAD5PutlE=s8tU8Cd4QP$rE+VLdByd=sF zsX*9(ms+dtgFVqU=R|7wbnB9ZNttYC5PfZNc1rcmoAJ?(YHiG)of%vE&|O4KVh9wy;qh(9!K*-3@WhU$;&c$*9b_TwGr@w%n3S@2*4^|m#`j%%{O0Zx}J6k9)MSBnv= zu|k7WJ5k2MC1O$Lr!fC#E*1@5z`2k0-<2F@c+qEvE5-7N_1+kL%!i&K3d5%&@IUx* zho#VD%)kshTvLBLxt975C#L_D!}dSc3~&I;txPVq)r#1xKfdfe!78=TSzH#f4tMo_3>Vl(awinw;Qeie3- zoHxVL{_Ca+IO#m+sK7<`1sSWsH~-l7n#@E~f9zC==8;T?kYUAJH>7b#ox|)|jA5pp zDI(geW#=1V$Nk-dvX_jc>83~}v#?D)RZ(VF(FRp>@Qq9<^QpA#jC5Uj9C$Frvf{|0 zEMW?`1Oy(Rxblyfw@}5AJLalh!zoi&N?50TUsCzQ2w42-Owt2;#1uF;UJa&MyV=r1 zN#>E6cvE1wW$rHoDqes%_s-DI!Nq9Y@{yENWF7iR0>?;U8$>)RovztI^I>-WXfS&` z)pFri3H>q;axTI{jNeyVze_)(^Uk>*e@CWCSs9uoiSjzb9$wp}R&eOKzP&&%T^ZsY zyEZeXH_4yE64{$DMPwN`G{DTJSaWU6An?lca*C23OJIT4BdmA5uy{ei%ozMIcgM}f z9a&n7fssPc3y0~jlZ#nnt?ljP8B`yTaU*2r7 z?D^_M3+?YC5BrzT_YXug_lRG%*avHaip3#JT1onGC3ERw&8%Yj=98AuuAL*LjZ2y1MFZiBP=2 zanv*z7#-tX>(<#hE*K19D4X(apU~AyhlaQa4QVI&x6C;uR%-$-7hh0#QkA49LW(jQ+qbfHjxRv=u-%Mea0~&_dXow8NY$q2=nXUh#W2GF+0W;xW)dHPXxT> zC#XvuY%G^P<4D#6(fr9)9I9Ritv82=n=QGW5}+{_r`^`Gw*Ai6XPEsW`lC1~Q80Bq zJlaLVe#O(4WWYnK()JqRh|uSwtQQ|?9iet108%gy39o&hv$m2-$tj!ez|}c^NjYyy z(Dkp1n@nT{YlNBJxgNJHO-ITt!qvG%mFK zm<0bXioR#5dHios{Jlc!H+KZOFc-Z^TeK#FY;PSa?xp)*z8+xrtGBkuW3BJ@BMEQhv8dOr${~PX_UqjN ze7>|cGeq8tD(Y`eW?pP2QGx)BDj{Bvj1iqNa_(Pt@xb@45<%ngKCK7YH51;4L{Fjk zD^QP#GAx#WX2yy>~E?kTA zrv%W<$@j$7iaJH@y9m0Q`pU}_y1@Q8R-Z4Q< zgK~8Cl1E*V9z?P(&N49&a9R6j`lgqBm5a8$C-lTi2t%S(Vi5R^ke9-BEXuDcAdfKJ zCR1KKdfd4FNoxebgYWyQl;;f6CNfbQ+rd+9ECKpkzd5Z>mipU_h^4go7o`e1gLX+w z;s^Z@o>Z%l=GslmQ0)ehVPllpd|)Bj2IydWJ)^a$ixtjSi!WC?R-Q#!5(jpQna*hA z^!yYw;&f_%(?eRv&F~7LT8}=~C8m$9$Sz4A5p!Eq)lnmQ^nu7S;Wn)K!cslptxc}& zg_`pEHL`1Urv9^D3yswGp-4E@lE4j%b|`OFBlPL zETAlsnpSBb0Y>m1y7BSpe3`F%9|AL=`K7>Xf`~^CsG)=IrBGIGT$H$p>y626^EMT# z+*Rq3L9@{vSB9Ls$=q%*-n@t(xlUjQ$@|l(6t@S{aCUKO&(jj&05Meam5!qgV|0Zs z0VF9+KR#rDf%`~U;?I24zj69&n)f3XQF6kit_Yc(Eaux!y@3qeTvHS)SfnOXlO9LL z29rf~x}DPm*JM!|CL^6P#yKn>498XkPRFeAXO(Ap&}x{7=UL7{_d#Gn4ckxVgqopT zLt0w6b8-^{BqwKXceO&}nq1Y{+n|PZnC3hRojK0g&LrbGpx=3LN4LB4 zeAOc5_Tl7`0~Pes`Y4bp;CB)%tQKp)aS-FT1! z%(X`AUvxYkW_<}W7o=wkJ0Y>&0dtC8j>4@w8e`T|^4b80sO4u}=rcn*_@BZJd+lfh zf;|WHtB@tsz?N*>cM}2=o0z3WN>YvG;@cxP-9PR$-ue$^X&N<%bEUzGVYCde;+u#2 z!({8wa;(R`n|XYghAhNxa7a>XYII4w?yf~S`K~)9-PDrNiM^h>qu?gj_1(N`p|fNO zdHwOk!Rvs5lvHg#r!HqQx-UBI)^zC)>K|2MPQ_q&T*&{u#!O>@)k}Ou{gX3g zKUJDDE7KbL$s7qFTHA`&@g!}F%tM{G{!|&@oZA)Zv4;6AzTW!dH|zNYQ|4&vGuv|8 zH*=u%?JRlv&p?Gg&k=w8vb?iJs$ww8$u*7xbS36eEWo#b!G5%fUd-EJfu$E#+)RHT zNb#R27H>q5o`q}d1XO(T{fS3VebhA|@pU3HMZPV8gh@)@+M<_*PcjCU(-;SZGv^IQ z*;J*>!+7aD1ZVA@2zL3N+m(1QAbc@R>xL&2lOUh24kkrv7cBrq92 ziaU?v;rWI37A685bC<|nEFn6=p{!N2n+3Dv*y%`ulF61QEl@g=y91Oi^x>l;Fy=DU zGmuuE`b4TC;of8dtne`uVw;6O3Co#tQNowzKCR`YNeV4w!RWs|RqFWnQ3#=G9cf#m zjefhnE9p6*xIJn0rq|XmlSa$Ot{i8IVhWi0#@7kB}P#Ys3 zy_=7!^~v6r7Gu{YH(ro=Tv#E_q;`Kbj?z>@j+Fx#sMMOHiI zQdkO);VLHSM>Si#L3upr8|hGN`)axrV3*e|^XpkV8ZQ1Qlmb1B@IlYF{H(Ur*YH$$ z`4W6;$pcHMZEYqFyy0wYV#c7RNMi>^g|+hGQ;mLM2mm=`7h}#vLlziRX?LS8|9Xd0 z>)_n(&jb}>ap(remjy}*t5aAfh9e}cN{o*-_vHkP~3 zTh4mHOXXOr5saoGZ9p1wY$||cvv{N5bKtxI=gjvquz%m^V0PWXt7$)R&FuO0!@2Xc zdLs>%^=kl|8C#r-rjDSt(4z(~wSPELPx+{Cj|dUbDWjY8sA0{NA)FPQ~SAbDQc5Ui$>9sRDThzD&f7S=fvz?ljbcPM=o zMfRL)mrPcP_c=53zSMY&C4;{Ax@?uryXkMgqrbOL) zE9IYtx0J0L?)~2<0B^LhL75MYv}tzmnUB0#R<{L+I&aE589=voM6$qJos$XfpN;UEc`5(+c$Rb;EwKnq9J(hHu`e>EFKFKtva zX5p}CGFaLfp|lIYKGj(a!m*mcG2n3M)`=WIhrea0kyk!v65de;U?){K1Cqj+2HE%SX) zLP-sVAh_7`Xnf3d(o4T)-Ul8EZ%+pa)Qs_JpN|;uZWqpBsC6;Q+X^ea{8nz>e!|Wl z^rHX^ms+=@s!Y0t1h@1rhOhl~LafN{6fPpd$Uec#9=7;kWYc@r= z2ELtH;R*gaF6An5MVnl{uoLKDgxzMct|xvS_`RP(zw-bmyuFXT=kK#dZSM-af2e`n z6aiEReBjR(D&sR?Vc)WX!0Dz^)qQCD@ssfp;m~Kz*7At+IlOWcaQfFgD)e+)wu&XIBkeL0^UzYV&clA z;I!2AzhVWbD4l4VbA^Atc)%>@AdZl7^fuY#n%CSbiUQN^|8%R2!=lln0+X5Ua|W#S zl0cNnw4z6ZLii|Eexp#>xA4fYJk(dlre+%^|BzGSU9@iv&h`c^w`gGv#IyEhf^Jl8 zUYnVs8dVhAnQRJy0Y=YXflmdHOW~~b1hNPWJ=A(45y*sxHEO{NVR~Q_Vs7xEg9Y%(Yl#`?m z@EpOWL#jt**@lY`@zyuLVd4tqt*V!Y{6lDb1#*Bi$|dFd2By`4+v5ASLfMSMbDq!b z0S}U>cF{<&2<{fi%xa;C@&}^Po@gmWr%rY!@yjy`t~D9(Bo(WM!7Hi1>VFP4CgVtj zHN{7bbaDJ#-tTo85#$dk_jl{?eZTf&?pMUBoT^nklE~(ApO7*r{BJ4SQK>$=*zJij zZbq^qDx!R*`$0RZ(xv71oC5*LMdsfM8WQ-PsosVfbmalp%1bx3ZbsfJSGCX3Q{Rlg zy4wk%pUt3jsc2@V1{$$1CVv~Pro>QASoLY4`xZQEX$ocZm)N5pZY(dGpdI=S+vdeb zQ(s0dR**N*$I4jc*+N{(eX(%NSSlV5(B0g62p$INU(}8yZA_7cH#D{h)??r+tIv7+ zxBaBl)yq-_1U3#Mp6^V4O2$<_2@KVX?RI#)&!pY^*eu`g-YhtoORVs&Pxr0ehPd9u zaD`Xa*3mKgc$2+a;?W^9XQYgWQp;)*(92y@O`9x|{y3NQRJY#3Vb~K3d_)>&S2u-qxA{_aO#Mzvm0iyZS@3JU-v_kYTP50WcFM*|b4;C8kFocgkI`y4+or zgwh8ry?MA=QcAZuFYr!WF=gA>aj|lxO=)=cpOVJ7MFUv$;0I zzB2~r@Iy7tzwA?>#6xLZSW}J9O0Tn>sl%1+00k8ba|L9tDF|nQ+$-Q}TTPW%9}=eD`*?-l5TZH_5exE`hsFI330EUbmzOsPyD9f&giDwPV%`SC$8Ck0ke* z(j86>0*`;^G7wli%3QA#lIy*eBwWB2!j|+QdBrm4ua5ag>I%nlDyD}GF?RFAcIsmE zOc`Ymi$2S?wZ_LJ>jVQLlp$sq)r(>BR;iFSz_l!X$@a47AI#86D;>7DpIE~6&t(8V<4a-yisAYu>!38-ivkVI}?o)$d3sjx4e3o{^P0C=V zNn8kM=YchISEkNe4_Am<-q=}{UosqyKS!ZBeEiQV0>vdp9dgB?dY=c|&fD>!w?wTr0aZ@@sm0Zo9dnP8+VSABA z8F0pxN4f`>$VSA!GLHwDQT@eGq#PB4a=g16QT<$mpL#h9{!=2Bh@x#WD#iX(vYIj)TP>bEQL1LZ*pspze{UC?uvRMY z;|6Hug{8|_T_jBvyFOP#gtH2MGniVml_ZV(_1=*e15NM^WKqN<8eX3HrjieuqxP%# zRx~_SS)_?!9)*PbR^@$UsF{YwS7L}uJjiJq{Bu|Z98VP4vx8wGgU`tWi$~JIoNKG` z@7AwT8ZO#z85x6TPh3T|Kmdk6s&m!B;Gep^4t{PON{*HRPQ>~fci1URV|{4MQ2S0( zz1@o7E}IT(GTGc<<`?cR6V;^RHcYGY$ax4O9B2KrX-L^1I)~GTPLV86#2uV0HavtO z-!pIAO2#Qdn5x5|mC`Dl&4qazy?jl`<3v)wXJ}7EoXhF-UxvIbqbP?g=NA7eKILjn zb?4i3rsOiO-sTY8>m_B?kxcq%EaO2#QgJ1V836e*x{pk9j9hw4fz6LNCwRE8M?t+E z-ieL0q#?Q10Ucglc0a7lh%lwblJK*Zxov8E*x9o77;54E>P0UFH$~_Oq6N6F@hpd> z;q*0mf-F+9Fm@(Rr z9*L7vv`jY@;AOr3_l4oZZeH>qlVN&mDVcv>_fX;z<4=CsZ-BWtRpQ>v4|ZuA z^f}v9uoB=YLU_*W?(fwk;XLz-P{{Q_QE&4SR-hvo%~_kunbW$pXcgMLlo{J^!{rVf z1Gx#ks%}3hk9N`c}MpI7nD#b=h z#fvI+KzYEgPb5AhbStow&QG2IP3wm?;WD3ig9t}$Zg;u{z(vfrm=-B^R3yCl`E|L; zH(Ol2b5yOfU=Ypxtu!}VE1+R%suoc^?_ zGF@NGia@tUU#_P($+9tvghDr%yR6lUL-^fpk z-R6Eq#;CzUDVVj4Her^7`(KK17}WP@_7@R|w2m>M=}?~ItXGMtjld&HlH5oVty8mu zXrCG+E7k^%z6=-RB%Op`NU;bHLIRiPly)B{QTs3M%X>s?Q35r0LKnc{+xYmrT(*W8 zG6K0bNGz17^ig?XKl}tXA+n>EOrwrZ&XU(0Ex=4xrzD>iV#scXJV(%%i=Hh!!C%?8Udsb2&e-{K1cSU$! zxwNPYwvYAuejtI=Q9#inHf;V&94iL&A%dkzHS^*nrJJ^=P6%IISwlD*VP;euGE;s- zRyKSt;0+B1#0SU-@}wZS&^mwSIpMPyI$g7!21lda!tz=FkOD;Vo>z`%X=x` zsx9r>4U1x27E%EY>a2wC%Xchwd6p8@Uld=$xW2n>x}pRax>-*}p1YYOwEggtIf^_4QIJJVI2(~wWf@K<%Dcz3RITFy#sm9!>AOQ;w? zDQrE8!@9SH0nNiU&8C`8==1RoZcayw`E-;Rco035e{0 zmIDO5_0l+5(M4o%9^(Jpc-~b#i*f_ze-?fRw1&K`za+Lr^6*$*BI7px!C`7?Yj4YC zl=i{7FZeR~_9w5QCuRu0u!0AyEm;h~uY6vXfPqL5roKro2|!_@)wtTc{tqzEC-o+e z#T-s`BjjN6AZcw`nV!<7(49py5}C=MVoIP9U&WM|M1r*C3i|cwJDNkwR&jk?gw;fZ zge3`CU~Vz;Xti~uv<%0rRQrST1+Xc`)?7lFaGd|gaJo>Dw5-@oUm6DK+EWlfiosgn zqb$8SkxljQ?&B3pCic4WkfEj~n0J?Ij2O2)kxPPh6m18dP|s;xiqU!Nh%CYe@4%e~ zKJaG#!lu)~h*&>h2ZWO8jmOe&GJeRm(Hzm(@^=PI1bJ-@hwNWfoFVmNbMWy`{;BxR z@e{am11&wk*=%si;j-~Qu7cRR_)&j5@d&W7ro$>97 z^WJ&hIIF~Y5fohstA}Iom-H0F6_%bUN=fPwjGWM z)Rde&?{|Z|6*9--&L2q(hgVg9X`a6-eS)z7u;;;z?x(cwy!J9W@=^XHvqvn5QOr&> z7|wyQdBxWc?6tIds|)hZ8g{<7!D8 zSVr0r^^X)Mp(&NnS*I3_Q*1%FEMWq7VjY4+yX^mTWx*e zgyWW@FOgao#gR4oUxd+#ge>uytFVgFpRz^axQCv7t&RsRk$JWhfF?y@D5l`B*y81y znp<7KaMSB1G0nP&Vmyd3yQ+qFWlQTgmX`J``@((W9Nzf68httdTGuKo^U1`XLBvL`F1ea0O!3whS^6_(qrlT#}-T;!%Y=hj`5$BBBj;P z)btL;cDx)ZAr4%ttx6J9qB&&)ou1fbh#L)_h`D^ATEP6!@!M|g?Cpov-FGyFhwck7 z6CQuisDPhj4a|6~hH+n?zrXC`!nS8cTvz;HKg-BV2m?s8Hfy_7>Z3NVea*DE9I3QS zqcKnro&~PZb@h9Uegl5DC>@It$sGUWeKWElbo$gY>`|;jDdEe!-o_}_A5Bm6P6g4a zhk}C5>q&Pxc|uYi1Q>i?YgcD8+WYi|lLMTeCQr^vft?q~?;Y7lHJdubnOj{Vgcs5K z4_|Z)H-nz;7(D$W63d1C*~BGF3CWLY@z$) z#2~_?9^_t&ar#S1QywTu9sQ+6+ZkOGcxR_kPmL+nIr%+I*|M)p(usee49w7&+yt9_ zYSwoawGX`l1tF36P}L7U9CQLt&;`Ly;vyf$hPHg_1)c|E-pfsSP_yk^VoJ^Dv{`73 zOV5dmIlc@*lNZSyFiBVCD>SZap-9dZ<@!)6aa;&5n~gy&_62{~V0>wdQ_&*;GeFG0 zvpk-}KHo)tP+Kth$>!!j)+6S8D2Lx&85LW0rYg#;4A!)`Hp03Fnv;&h4opKgWcn8x zO02XS)=}*znFwk!af!@$fO5us^TQ@30s7{$CB?&p1SfN_eO@LRSd)Ll`n~9@;@wKp z;ew3J_6_Xvuk~ouDoof;A}a%Ny7|~8g&@QyTxmN0lxBCHY*WH*Yqzjak$=NVkSih3 z1}9$cO@0jQ6A4iLoeDOQZ5rnTMRhV9@_-0Djz{km8F^w(X)?uWXDFC>!=H-5Oa(op@}g>TXNYXXp>-R0=~X-l zQqbEe1dw^L+rnxUf=eUHJAA_OS`oo8739KL_)#kTP1tXQy8O>V6(kxb<_Nwi-kTHO zZ4`|11^Zw;5Etql>K4Ye7|uGlgIgTsn;KWM?r?iK)BC~n`W9J~RxUPaJ;UuPTkFDL z`svEhkiWaeaq?E2H&XhfUmd5I1)#swmqUn*9*w5h1S?pSEha7jO|mo#v`3EMQAzOr zqi_f_U>9q10F-@@MkrD#7m?*M9dm5E(xYSyfCjVn5o-?2Vcf>_bgy^tXI~a3c=A0D zNj8*;K~PRvxO&e3vWBu#-*6Dh%FK~5L-mDdG-7g}c^v z_p9igl0M@pF<%e_kn;`Fp>S07H(7nv!+OQscKZ1my3m{H!j2)+g_cl+oZ|r0M?>3;M*oX$Ly;bV0k~a0vJbJh(HPqSv6f{=7#9S$KrA#q5 zxDHCZ5+N(?hk6xR`L)#s{n)4lJF?zAqN`+KarA=2GmC#(Gaonl(Za4(Q0~Djb4Km84 z!OBWnf~sOTq^vHYWBSVxY2Vn^tvB32wVMxXkQn61G}*-~t;!c^ic^q|VY3Io%zLJG zIJAh2GgfVnfddnN=<6TuH1h*P;sZU#q=_A!v9K$5DvWjTnOlGb=dFar(lbedCwBA~ zsAWNdfe)cBr!{v(bvSrc4KE)5aGx&q&w*gR`r+YkA5T-rJerbkYQFK^ih5^zl4_RH zI@kU#G($nhyr(L!|e!LhP=*Gb5^qa%mW zA&|E4aicHFI~Yog=m)-7R`I=w*zZr);j@~ruaVi`5N<(@AZK;t#a7#T`RogZXYhxu zfM^qtg-5C}`w7}m<$by=?I*1{ieAT!yzWBLDPK{Xzp0mKjA()g|7%2A&DW=&dhtve z%Kkr@I-ocSMFN@9uw4gf<@u#G0l6_L1=EYZV9;d6%TWSeiG{f#Z+hiCuP;Q5aNvhb9`GiZ8 z;JYj0u0(op*^cn+^%WBR_fEfHywJ^52sg5RyW#X)V)@)?}t#b0p zW?7C;{l*)BNLkqMLj8Rwlp&%u5L+Iq*w{XQ4~wwVVm&5Mt~-JwAxt4?$p9$X3{dQl z_x74$7QI;#NImqy?Zf-{c>UTl3OI?y_atx_mmIlRx`a8N2Na#TwY5B)rO;dD13j$; zLuKCrsNNq=u`pI|$mJ&;Lj?z-ZTayw=~KZO_XyHsA;tp- zd8@pzw!Rb0OlJQFCMN|@UuEy!4Zh27p73mXw}a~x8^y45$hYI|IV|Jh^dbP#MmGPf zrVk=vxjbe4{sy+Q0!k^^7Jbd9pby;-l)tbf)p8|RQ)=EEMCmFAFk}b_p3nPEM`XpKC;_T=>+n!7 zQ|H!xraE_It7HyiO2xX!_S6|d&)MhtId?=DBN0mTXbh%K5AqYM4ru`xQCvLo?)V5W z(U6Dx+-M%VBO{HNSyB(~Ac`gycn&FB#cS;uEne%oO8{o-=azQGez5q*5fERVJu006 zQ6yhlG2{R0=*gS`s!*r*Z#Pnsupvtt4Jl|S1r>7R6EJGLr|T73`0{Djwd(A9nEKqD zrXDjC*4ACg`4Y^0OMZ$;Y5QhnapZs<82xBPhB$x`68B<|F!7sANc`O|ZS>VK8>I!= z0_#aN9yfV7ddTk9xPBM}jb6)f=54yuBurY_fbmY;o6*T;Ytpf-18@IkD?p|m6R!SP z{8(^0Pf?|vJ&&I8ufaV=-V3th&v-w7lRHVboTnuZqi?@TEE|_cyv~U@aPn}2Fw77dyI=Vmb+c+CNXzk-{>jVl|xWopSflmf2Xd{Tzz;eK2 z%eD;AzudDa#p$h9iD%ge*BmN!0r`x0{@GiEErs{H#0P_PbY;F$*rB$)3d8`4M?II5iFVHGr)>u1q>vNgW^*Gik2PTh1I>jN{Io}uxq(Q7(YuEaSa*x z`IFBiPV5gLRv*^2xSdV|Dzfthi0=A9PQG`BQn*i>SML1>Td+7UNWP^cXF;JmKnfqt zDV^N7-dcj@ie^E=d$si8#Q>idg;!>o$Wyo6In^x9QGPv#B=GDau zKIBz7fRm_V)y8g~oY0CTXi=)}Md?>_62l2>jx(Bwh+&nK%DU-70w$d+JVCN7d-?QG z$>BMf`%=0EV@?Cg*5d$GO}E~Nb`9-KD2{YY&rx9@nI==fOs2ZAFvj7#ZNP0&!YqBb z1@sZ9K3yKbHhdr43tH=Z(IN#h{Yl?Xhnk-;f7Nl6F=EeP<}LxbYW+9R48QEw!lmbs z@T}Q0ZjKTk)0!M?@ZYoNn}T8r*FSPur5OiA&XWl`oc2A}HI?mcIxhwfRe~9+2=JL^ zTbQ46MpR}MYW<_;Eb)89xjCzVOA_3r3yaZ&@b`=a#D)X8%4=BeNs`Qs%MTq04;niWPQ&@0IbIrRP$_p*ANq3&bIU!;@O!MSy9 ziYk2@yV7H=uW*rkozlr2bnD%Sa&0a;sTvmHq{sPx6<-7CR=OG%4LUvBP@kRE7yozt z%t~w+V&48t!ycg%6mG(^2bqR|rE0~$lpI#Dz1t`->wa4`V$sh;)7?%v*ltlf>A)(h z&NZK=W{ib3<8`V4YvuZ|u1$fMy)X+P#2d>2!dry)m`^8S1qkBCVZnLK*9f8eubKU1 z#uk?mfd9LB;6jGMYSGk{F@5vqoBjalZ8rLQwFg?_&NGAX&EjrOkWP65W<6 zuEJDvF`YFN4gl$*6;@AGb(xsk^V|*K6e-#1Q)uM{b?%lbLmw4`yVX77P=^+rpZ8>) zEJ^dE;zG1h(9|K1`)SU)4Oy#IiS<5dOE5I!?a4*`&As?(uqpr@(Qsga=_|zTWkXEB#ht04Z9##ndU!%WR3Mq0Q6Aj_6VJ;qv5gUT}cuR@KtCA7`X8m3_2qb9dYx>@Z z=O?it>Nz%ZBw%@XfjKgt>E9s+MQ3w5^WGGo-9);n$Fe&yqE#wed5>fFDlRjlLW&ci z@o3;j$(z|(pSSDHK#W$U)L46mChkj!-M&gm$>^tv;1*BDd_A^)Uwirj8xqN+R>R?A*CR=%jE+}YFq?nH7 z5vOkYS`d6p1L4-rIJuL;fhp#MFz}c5(;Taz34($Lj@KTkH_ePG+<2}SrlCUuTHYS3 zEqpgsK8C2&lmeNC|n# zya)brS<2*`r!vx-nTdrxkLwN6#!#C%AZl)0Iyp3u*Ttz%Kjstd;%O>qM;j9j5uW<( zC#MYy?|3|7OGtYb2QGCt$`cC3V0uLLVF7511YKq#`16)d7yWK;7B#0q5?aYV&YcsV z`o=%mFYo>C(?#n-d}Ba-ta&R9Ev)`Mo+&rGx1uP|hJeLrLA11}g_MH#g#w!e_}Xcot)tAY@C zK?ti+;Pl|;tcKBso?pp)bM%mRwXgR*FYd6DuBOsnQ6=odn7B~S4HqYO)y5?aTp}ZG zc^X{{g|f7-bagDtP*~qwr>PV*JWEI9Zpm)sq~yIvLt)I%e1c_mHPLbF9zVZWd9vke z3V-O_QEp!2XMvcP#yvuo_{wfP6^ap)TW;11m|YCT12hrnd4*l6VOp$0_|xjO=JMFV z&>GH1K6M6JHs;e4fRY$S0x1zEv ziRp}j2JAEX2tV@+*iY;@v<7(+{5@6lwkEycI7`*?TcFc4`$yQ?tdgPW%I}v`4t^nG zI&BP~0rdjOcUaNsur+cLWPdd5yum@HOpzp?%dMfeu*EtB82~iC1$m{QE}$)b=3GZU z$41#Yudh##v4omB#iQsZ7TUw;*)hygjzk=t3)KY^0Bpcfw#me^pL&y}&jbl6tiHqF21_4*t4{l2t; z?|G4A>K{ftQSgP~T+&lC0la+Vg))Ni&S$?z=LQa7O~i8jDFy8XSReTiKhcFUz;)d^ zIq17rcYdd}peQieCF{x`#=0Gmdp4eNdAwzX#0KARa3`;uvkHpH+;-*TX+S$#i&$z3 zm$%BKl{nNjy#P*`1XLvVkW4+f!S5+wj(4$2O)_%P;00$Qj)YP$Jdv8I@v=_^ZStKH zCxx~1cCPt+T$@s+=sk~@@U$Ir$fqZ${C$pD1--}TL|XFg3+s+slP1=9r8k#+we4;f z8A+s)ggd4ZiYW|~Yp<O(K3& zoh|P^d^K)yggMvVZWUfe&HWB%?`%DsG+TZPgWYjCD+elJ7OP#ULe@Ljg5@ zRLzR306PO}&7h+$8L&fND*SIvt(M^#K39z@(|-EDb86HElGWo1ZGdwvmEpNn%gcyB zG!IN2e2#cGp)JqRNx3rJpJ)>oN2c#Vd^jvB7$IZv&CO-l zNpyj44O>`^rBw@-!$O(@>+4SjuPW8`$S8KIOAqv{oDr(Tc%3Jk3D8DB$u;G)Wa9U^ zu1tvw`h&*W56Os&uIazddGh~j{Hq@Czvzd;rP3=>X6LGHx7-2)Aq7RHE`;}+adQbqyA56Y+G&k)TeVNdXMYGE zzF$STq8gKYn@&D1?^WC0JwidqtDn<(MnhB&@$!vJKOO5UK8B(*k)~j$iVjNUqccG? z{D_s|Q`rdUF}jOlBa_RzmA3jppj=^;01eN-;eQgJs%;SIGS&3KE&Vl=wtmOXW^YdJ zYpVKJM;rlE_)+h%W;Gq`u*EIjcOPiIV`mq+a&D{X%+GGqiK4fS#ns`v^Cw%LtkZt? zg*en3@Etlo37pH1e_@lT)gX$8tnpF@iF=e&0cwR)0*aLH3a4@-Jr@~<(HQ|U*AR4j zH;u}i3_@Kg$1%OuYMTi9gi9T8#U@d6c5sZ=#9j`+$L)OM$PPL3#Lr%g}}8Ph-wcrlbLos=AN} zOU-P6AgaUNFwb#2{Fc2zpcGXmUYr}7yb)&bM(?Lf`uVO(!g7&1yS%C8uL5g1G4>0` zuKv8ZXnTBz{}{6hb>~J%ej@xN-8sv|o>N4#m>rBMsb z%5|?J!Z)mAix*|2%ORtBlFe3-0VX@xO3)0r2Oc5t0sNmdTeu0R*_ z%Ih>17qMqYdg2#130*cmB-KZ?naVLhZH_KKQkj96XEE;7$08;iDwJY7ttTd2!4~vl zYEN*qo&Owma30!w_P!8RM_9E4ifC@V&PIEqZD*z4Ir~`6dj*uHg5P`-?mbv_3x}#5ma}s*YAt}f_$OfmlMf?7C+$5}VvAiVv&^2s z<2U2dSlt2Jn_YtX?WBDBYQt+ETl#ndjlIc;A|IRBizPb!KgV0W=!#j2&E+NZ_5bC<$crC27&I&A4!t=0OM-6`0@LNd4+xd$_vSVEY z=#Fi}&K(3Sy&mVm_xx2&*MaT>*O{FdyB)f@Ug0d*)tzk(;Hdmt;^**axI5m9^LDv^ zJ`{|x^eyn6?ON(}QuiwN*e7gum#t-Q31*pR!i&l5mNm3L)|-v_EYny^gPfFk2J`S; z{gx6e^P1CC#Lf|i6;-Y-sxv_;-M()62}D!)dtK&b$i|Lgsp6Ox*nLgZous1Ie*n0F zie+{8YWX}6fR;X7&64p#7#7*KscX@kd@V721D4e0-lc-yXd7kE*dS?PxN%rS0xEQ^ z?Jn;Fx_aOl2@XM{MO<`qTu(VwH9tYI5@?d?yjc(TdR+rW2h4^4{JIN&Me)bL>Nn?@rt6IzWizLO@gn?71E z|4dDPEGHSAEFMy^I1P^bmsm0)V-I0!d;$N@I)bJcj#8x{-N!V};pKHw@T*pB1P&PC z@NiebTx4aw_{;Eoboq3Iw9OdIIS1O*6rE;k7H+h{2LDDOVJ#ddq4ard>1_8Z-gpB~ zp4G;flFAK2F>f6@X4mot0Jq7Xut@Kb_+re)yWRB4Glzexiu20Rz1Q~Ss%Z)y)`lQ_ zj&NAKTzOGObQg;m z%#Iwszko$6D1>+d&!zvu;=$Y1!SKPNnnv1^`}`u+Fm1v#P=UW5hr@UcO#$wjlo?f5 z3HIQ@;1X_kbmcaHjvl~EX$JsbgOsjop|lWS#)C}ep+>1u2h*qcYEr}_Aq@JY|F2~u{-0cK#V$_IC%EE1(*jZqZH;3Hw5%0liOebaZ zt#=hf4JF1ZAsj4s*sdAqIFjMc!;8MD7n|N_Vx`KC2eM%D`tDi?x6g(cChJt&l5q-H zB^!190Ub?t0-{OE|7X*YnhQQAjy;A4`$!#WlrESuyZ}L>>=b$R(VL@uZ#qeChKs;H zlT?$uOiR`u-5)>7D%r%iX7hE|qSu;W;uGKFIq`>MtK`iZB-N3w^`{LL^$Xi|hT!Dl z?3aG43nhjfK!SUW`BDo8kDgUxkolrCurinD8?T+(`CEqNaboxM-{>+iX02gcP-PH2 zf%7qp#&oP0nb^WzFdg$aHY^kWXj;mM$KMAnJCB@X6~4td%naxLj{dP9Ke#l8#6T@Q z3HvSn&f!9d?g;7RFTy**COX#A7t5FL)#UM}T@xp)oCQdSp_3vTf#P;NW76DMkma_Vt-A{ek%k(2xOi0553b~M#;fW`(Vi=; z*;SM?`wnOB>$zF{ans?&dZ+abO(0KJ91g_%Op-_Sr$5)xu_8AOqzcC58bvq8w8D>< zWTnlY^$`76k9$LOmhj1Z3p-+nx_+r-KHxqXx#-rIRERqk!o(YFWuYK4g9?Upydk2D zz4B9l6&N3q;^rvGv&eo{XRBofi03N4Ao0lyJbF@LrAUC~xEcbq_%0+sdw8xErza0x z^W~Pe8Cp_FaLlZ~J4u7=qziY=O6u8-4VB%%Ag^!N_(V#b)ky1iiYU8%94tH)&wC(8;FYx>ka9R_nHi`ydrSfX^YSY!F4i}q!t*ru?rvi$kpa9SOOOkvEiS* zvcu+(&TH8kZ;7Dz#)&3?lt5t-eK&92lpr}!#i*e&c*D;VcK3#FvQ%KP)_i)lg|uqw zRT<&2;_5K953|dE+2yB=f-pdVkeC> z?$K}?vL0!i*x&i>&|ax@mT~0tNXwdfWiDZls(EajVAowl-iRKc^ZNx^=Hl8e=e}9A z%}ZX^w(Y6EGSHJrpD6_O51}=Y66;+~6 zhIfJ*Bm-Y6>O>E?g~Iw%>n$OW!tjoKVnXo~E}}i7)pQIQLRAXXW$4r7Txpm!L%)2c z+;n%)LJdl*3Jx*D&e))Hv7o!RawG?(7+RqG!Q{v9nq1KK=jxQ-qYiFXA8;it715HtR;>y@3`2TWe2lz=nuPtwy1qI(l8iwM~m?jMI+9&U>04lMNxZ z{D#q=>PI1iQO>M)np$5jij$}0 z?zbfZBpyvlT*j2z7`dYOfU<>cScmmVxcZ||Koz6BZ=ZqZ{=ZE%KrP5A~c1NZkMypvG33@!!Sb**O3;)H0OSMioz66cZyW{jklssbI zfev=vr$$TACrBY@d9ze+hEke5(oh%s(vozPqL5)G$mMkfIjj(Ir;P901!!2^es=Wx zXLetC*Jj_FfQW%#Dwk^UcE2J?6LTXN6V!g))@}(-j7NrGB@Dl-puZ)peR*mLSS1F3g!im5dZd_q?#?;> zGQTXp+>)LPgAJQp6idu?W``h(!&w^#-v_O^RH@*PYS#=Le!K)VHGo&TUGCdfhrS+H z7jm2n*4XWT_NXOVS6h)I42vZa$In&C-QP3uI3$dxST)^k_erKYtZh6DD^ zULdAnq{Y08`Fx!-ti}g?#><5CSV-}7s3{mb0shXpsVDdLlqG@U8#f>td( zrQ{R;OXs6eP?#&S6&@qcNol89l(ND@8@>$73y69FTI4s9RE(M(D_!)K`B$M0r9q~T zSNJFLH~9TVSG>x5g%M>BBb<_de@A%Q7V!;O15jQhy$Q2xF@sA38SzEBU=w}{;EgJz zxL;;q5c)|?@g{7DvwYWX{;KtBp<0+-@lG!l7a26}rkW^;`h6`V??&q?CtWbgd;OG5lJad#1tLnE~vc*72zQQ@K_ zl<$|N#qzuAh`E8biTU9Hp7$9~4TD;UraQM7`J6HFH!5ocO1?z%!_;glTnTiP1j}~R z46FG$4g4JArdfjSLtHT_t(mg<_R~N=l0Bo`J19lsfY9DMeZk7jQt$79u~_w_vqb8R zbapc@S@EmB!9cx9s1~omVb`nNLF~>iK|d z_K(3UN^M4;U);ibDKuU@eGOB;gjx}lLJXtRScs%y??RE)9IlPr&}{M52B^@0cE!)Q zX&hZ1fp&+6*qX>YniPyOZ;V1qsRRpy_e$w2&u<&Hn%ovLJphsyQ?Su#@#y{KjV{f3 zlz<@7HAR`;x&udyIPn{zmH~w&NCxWaJQf)*`Pq!W4us?PJ={jIw^^Ks7CcSk7e&5q z{YFP&_nCvMbHIyXZfy(}w}0&%cYSBO+w@443^d!E`Eby{X=t%mUa}*fTxo}=<}s

NTH{%0X*1Q_mrI$ zs|?-r>70NU%p9mE>3FZLsV%Hl`=2Nr>3dzh@f@uCbo-7=CY!wfEbMMg00z5uundGH z<}foLt%xQ=kq*nd#|K*=+=(rjQHHSN#1;N|66cn9E0=ua|Dz3HMO)cY*Cl>jpUfyh zpKB55hdk_OU0T}W2c?kD5ZQpD4g!$rUs#92ADVa?O6z;=&Q-|t(dA}>(bcnxpM`!H zlwcpcL+@k#r%ET9$h*WV zB|{G#ds6S<`aKFE>ma0Q*5u*{i1Mx|>ax3;7Pe;{bw%2wP`3m`gKwDZb3&2u82cFk z$IBe6)eO@nA6aCd!UAp&F%uU2u57yO|E%){wnE+EgI5c>bw1YLO0kvFdy`%dvz#^d zln&qE-<@xtYo)#Js!wA$4TAp+E~qFFxZp^3s)rX=cJ!(eK@>@8zF;}OF{tNd{#$@NfsAcmWz8viY!Q z2LgXCvTTR@0gNm=Nr=gnr<&k-)3M z;j<60_oL#p*r z4@xKoca+M+S}L|NlJ?+-h96epnSb_srKlcHgk$Y@KBQ-|W615?@HgDtGcSz8az_Bf zp_bI}hgI*iDtGE?*W--tg~X?gny<>))dM5@rAu5|WJpXXRtV@EJL2vN0Es+6*e7@L zq5Kd_Mr@AawEpzm^jkaZwdSANjU6_cx?yG*&MM=GNU z!zE_PlFu0mOT@qu0!j%mG2ERw}XtPo6!1h5$1ALdhqUfjeYBKwqesEx> zxFM@(1Y^&LSVYv~+a2H3@ROv78OcME?(p#X*lhrl?#AIXy#d2c!n0r$&391oqB-XeLclyKX z^=;adBR&AWksIdU6p|4Oixt*N-fyrAPREqGr#}bzz1S;CXWMW%pNwB}NtwUaWBIL9 zz#TohRiAQPya~}H%L&@sB*S)B2&)- zZX31u?(1+p$kN@pAgzPWNJ$W+)3lRpp*tTlMuDAU=o6V|F6v<%UU)gI@pI}qD zeAZ+$-i76pLVHs+73s(?UJoNBK7!%)hI;zI?XVix1~H7nB6z@dEi#WIKe<=3?+wbc znQ3Om@-7Stu*Mi=TZdHJjTjl^TsS6}qX9{{`e41}bHnuSa>APq4?+T4kg3ZTC_=H6 z$j;HmrDh!|S)v4at?Q#SDw}s>KC}kt_g2t$XW7U1;=+_xHIC@EMV=V7MYS30H#~Gv zMjjm2#Qzi){S?(3eZ=>W%OWZ#hh7@1xePu}nUr3m6}wqqLP!zwTA%xq_5OnD_1 z;iJy=u9@>n|7!_Dn;*B&P3_t*FfK9j*@v_cwl)(`GRc{$S&?cVX^i(am4Uz%q8tIS z2FCDX99jvM7;o7{v8rlN^<622L;?~&JVuX|%fd8>ojqdcK?Mb1e1<#b0yQ#=h#wbe zf#kJGd#VO#h;D{MeoglACw)f@nr$|<>hKd{xaBG5naaQ!LQ8Y?vt<~oqmA#SWx=Rp z#6!r8i≫FcN8_%@WpkGD4$;emwTT1Gkud0izA?qS~IK5mF!s?x54#ij%W7kqay> zVAQ~*F{G5S-|l_OZ_8F~X5U-p=xglY2fP)x0`rey?yF2N*tcw^Vo{PcxyF@WRablh zDSHtkpK1cywP@4a-*y~+qEe?Z9iX3C?}mM%XF`?ht1Zv~r{La)B>Jl*kQ98IRUU1P znhD9atNcsnJhE)TRH(uu#7o2ii>h1A%GV-!aFDrh!>h1FcD-_UNXBE|4=!P7rAxPA z_9kVpp-_fm-Yr_S6N_UxSBC-)Km=+hZ0rE4=ThRQ*j*o}pk+N=R5%0ECL~q5OGg z20<$?EHAq8z*$8`qPjJh#A;6$!>Xk+~WYzr0ZaY9xzfounAIeQ)# zefQJ%bbIu|#tQ zD1X*xWqP1}@^TO$A?=pzY|EfuEH!lOTJ(4|x1SH_Y*;q(`t7kI$|}6`CYvWH$W~dT z8YmHGpCcEZ-!SYXv6YGL^s+dGf4t>b-cr?4Ek49NszH_?QG`3-+tVE@Y#S^rm|%;7 zV6g6YQ!titrr>tZJVV>Mu{-C3VFq?QLHLR_sjb!%#K_F!CXuoxybqFg7Gr$yTLnX) zPNB3QQk2sB8M2+6#OA)r5=|*7ZCT9WS2(wFZG?6QYBlf@)Qod{+#v0Hv!?nv?$R#B zDz`E7*rAta)#VQs4^G-EPX#$|oOqZ{R^!Dn62GD56EFphX50eSheHOZbWqdN6Z4PvI> zm`ST{_Tr9_oQb%#T)hZGYCpCJwad@0=d8aXhcoBI)Zou{ws%0Q9h)}{92 z$oVeat72i7ov7XHfQnf2wJmYk2QwaYjZBh}S&M4}<%g9VJ@^a_-WBgK)Dp^d%2LWu zHSUy#&vKt`)D*Tj#~WxTYcg-}3G#9mvv!RX!TKLB0XJ{xei35BT0)gu_21U zMjX{9{F~#jTF>4RN>pQ_%<)M~JQuz3yc9fI+g~8Z(&m%=cWm;UXh$T@TTt4yhHi?l9dgF`6IQCGoD zX8|5_LXRw=%<%@)mJg(o?>IDbd$gMrMY_Yy%yDtR)in4~R}n`%l7Z>+y8 zYMDXP-y=G>doBtJ zx)j&gmQ}`$EQ!&c|3Nnx6sQoLXAo1TNzB>Tl_tMf#pNu}O%h|7)QW>GNZGRQog%z1 z$fujxB*jDQzw61Ob+JY~eHsO7;(f&w>*a{rh{)tp7qt-w`3M8E{oWAJxZoHIV$0_^ zN;af8Y35d%ps+er>|vN{uKZt+HL_Swx+dj#o;|EZ0=t1A5278RN2oMh-hNE4jgH6ib7#C+3+%Qrl4fqjTa#-MG}hc-xJ+0?!({vzKIABS!j7Uh4_-4%x;UYn#l| zIt3voGtyocu4s}s0dWyx4u?=RH6gPbkigSk33U2_mxA04Z2t6`Mr4Ft`{vLahXj&N zEx_Y$q<2ciD}H+p{9Ci1djH^XEvUs&R*ZK?XUmjpim0IK{6i-rZi3&bRD`fcrK`{7 zJtJNY;V?YqncTMN@mRyyw`c${Nm!JW#+n_cCJ*AbuK;Wv(?ZGAn;h+y;(n!IMQUR2 z+qgs`qoA*-UFoDHhbklMM^>kh+Ay*Gc{8P?HtB(gdjW3j^zO=6(N zzhxzzMfd=-QPjawI?x3j5}Gl%i-VI;*f!xh#E8*KSPiAKC>TLswj}BsUq>Ou%2HL`Av-Q_ z;ze#_zFVNL`y5FaMDkRnsoa?|j~5Ac|AaIzLR%Yw zK^%LAu*KN#bgXGmjjKZMoX+CIVAX6@mR;4orYPIq(}BJ(KHL8T=%*ec)vFa!;mQ7H zch*aPM#H&;#&XKM_|{I$|s3K_h?F4Ww|B$#Mg`rZ_)R4emxlX@%gCAr#N+m9!cr&XIDd}C zN%F!SxFZ9oJAdY5ENUY$NBR`1{@3o#<}TvEc0PxbwS(nz`XYHOY5fg z4K4`Ae16VbPM4Ei;xJohGYR^ShAPVehOmXWVqAvf1&_(O?@B&jrUEZ%#k;P=gQC?q z4L#VFz*A9ZpY}>|)H;!=9f)_?csm_sRtDHCtNo<_Z?~FKDc{Z_kh?pxEF+K^PqH8FnSD<$OArodU6~DEfaujqA%ZJdhW;T zFLS~{fUUI)EqVg1>Yug+hy8Md%mt`*dFk2Tgbd<8(dDblBQ*Dd@P=A{Gc=U?Hkr>C zyHF|qfx-J^KlP6uAe$G&2cndm{2)v1ydCG^hB>$Fu&0AF>sN6K_-{r4}xQKxC?#!Ze4Fl0M9Ui2k72j1b+biHuL5wQ*rkuh_mZ$1(>r9%=P6QCxb{@c@q zt%R<`Au?Upq-OqFuv;60w&Hh7St|JEm(XyjI1q@Ifd739qlxdb@}oRpoG>hBY)tRj z`p{7%&mKkEuADUtu4})VrBo8vjT7UiMTtzrtRsVIq6Sc4ZH$2{>1f@rwS=iL%_zGFWV zqm-zv1#vv%Pv55jMVwJYh)T`!oZVMn01h|JdmLGJgv4Ta zaFZSjQDW&%9=<`2^ujB%E;B2!80jcf#8nItVSu501yi0wsVygQyL}3GMeN4x2bnCd zugkO5k~i350txjvd%V;yY;9{-eEW$j_*osjp7}E2HE_PGVYXxL$w6tSq>(fBT(IQu zTLjuql+siv^9}3u6~cNT^8mjBw#lLmNO4J>PsqFdxm#1B%V;qbdi{m!13U85;o{#aD~8XJf`Be%-VU7Pc|<0qe#3HHUovW@O=&$M z6JUuigj-_BakWL^v|vS(e;ryBj|hhVX;vrICgSs3tV1eZqixl^=4IR5J^){7 z^*J<>+BresC2%{JL794IWHRkvtM2C_h1=Q2EsTHkhNn^+`8*w6L$vXTKXUav6}e zI9Md^_k*Hwhf|fU57DDDdsP+}Z3ZEef^=)vwE6}<;JqEkrl5+bxsU)8)x}uPdbNKoFxou$Jxsby(K<021l?r z1nSIh%@6dHCf9XrO*oML){7eCQBqcbhNby*C#r3__Y^y#f&7RXJ!XQ`7p+I??ksql zb#z;u?j;0US7O`qo_Go^-Kfu2dd?H6c%6+D>s2)3lrgxL97%EDy!o?0U3_9b zcZqjCx>uVBy0~Oqdfp18hM8o9-XUSf%tB6RWI1Co7G8xDI(LKDp1EEQeBGOn6N0@u5*m#zUD&HiBx*jCD5(Wva|EW;I z1flE1t$C|TD7lPBA+V=O5Cd(!pPp>{g5HT2c%{LbW9)MBZakc_y+&WKifTh zsu#>d8VWzFCjEqX{~i_oMB?wFUy}`RBH(=Bsd3xm%~y{ln^?>!Q;g{{sPttNrhu+~=k?wXad4_VAmn~fJ;rhy88Qe(#?d-sK*CCq>T?{RBg6+WWh=Ylq>2Z^gZ6wJ1DLRv;9tv z^Z7-kIR6{9jumM?yyz?~n{Sp0x5+^?5h>V}#Q9P>baQ(^F<1B$RmP57QS7u;tt}G0T z`UTRaG^MO19t%Xm#Zui!j$d=daZ#IgnF5kyg*JNpim>TR$1LGnk0gaaq(jh~z zW9@3VRS~9W{op2tq^vZ^l5}5XH4yF01Q1-OQ)`@j?9!;te6Z|!1)KR&{3LKf*VYm@ z4mrw)Mv1EfzaDT~w@_#OKNT>pUl%tu$;D?)%yyJ}kvUhRQpKyuuD6}jkL>#ke1^%< zb$)S9RvLVAPFQgJ&aYW8(zfg2p%r4NEh4J!Yz=_m`6NGl>(fPyGyHpjyI}|^bd1n4 ztt*#E%m}@D2D8;{lMneoND&7fNcOt;4H^Ror4DqEa+v$Hj?MX1!9dwVuKm>H4h!?Y z3FdJ_uuF_YNB$f;Y3Ex8RgKp3Y_JE;$+p6DG}12d$G@K0S?=C1J|2zCGt)`oTqsBvPXPKm@gF$MxkV>E@Aux94dXxGEgTcrmEj) z$5qzPXr304FmWhuH}A~%CAG9r?Y8AYaunI*X|CZ1h%c3_>ZZe3#&lV0+?CZQHZ!Bk zJiY}G)({u#2{w(w>X#VYbG4jOI1`KY|NLvnl<`YDVq*|~ZEq}|SB-N$U-6>=FAjpP zx4>#mbBFryACtwR>L6b)Q@DwD58#AqNiI0-Krg2#(@(^dz!F;56qUH+q zqItNCU#%~N%4a!_6lnk??q8G4Z@PHeJCXD5LLXM++oWL~W51dYg@?8#seeHjpq_gX z^&?Z4mi@5Syy=B;{Q205Bhurv+){!>g0u?hpR@9#a$$ruw;+zhaqs}hTiz z04|?~D1QVfdTEWWgeAoUkBF-Ki9Y8TdIq9wiy0zCd^&lTnKpAYQOCU9M^T==)zbi^ zlb$YmWBHaoGnV($G3sl_Z6@&(a1a<0S(PWx%j11DrHspDO_<+kL5;-G0`5sIT!FM1 zieH@FHh3A+DyQDI?y%XycXR9cNtJx8@5cfzpT~u{%4Vv^&HoxIfjTEjSX3DZ1h1n) z9A5kML@Jar;+V|EWsh!QcZM(fS%D4`Uo;jPt68wVhas_snVnzQzhS7o%yNkJFd?p$ zP<$S{{2Y;?5#wv<4D8C}(%CmDbfFh_3rmD!IlxnzNTeuh;m>m2QWDnX-UJWKRU}dGL2E2;cSjuXE0Az=iO>e zPWC;wv_hkB6BYUrx}p-jj=pU*6rd1s6wBz!qC5XL2py{&POJ6<5|tXXaI-(X#zPC_ ztblyEQe;*;8jcj+!?$@XdQ>=`$?o|Uj2y;INz6d(V5~%WFuH3?%cn^9>zIW6c-p|2 zeK6S!?wmPgAGOsHurQCNO0A9lpxEr#&>}oe@yTTz8&<)RvjLD75J*GB$NI008i3@O z7XoInyfgKVUd(AjG=K+A!gdWD;`q9~4aUVs?E>InsO6V%auG@S{p=!UUSX+NkM)RQ zL4SnXrNvJiix>9tnxF8jE|TU8t{8eAl&}4ElKsudSwe|#oKMQXj}p{i4;@jIJgyV+ zD;HyJ*lc9x{@(@Xyyjc2DNJ0dRig+DIGq8za3*i+V;vj4$Udbuu~}kA?QjtTmQI7J zD8sVhM!8U73Q;lo&FAE5J4dBBs(Dix7c*fC!AuqsRi-4A=}Qlwob1|y$pD4&6~m$c zqdS6xIY;?oywV+TDGz~4AS=N!I|Grv2A8zkY@huk5GMsAi-QkIOu%o4jixJFJ@Q@O5p}Jf;Y;@{{H6cjX2UM3; z@0599K(=XrqYJ-FcFkp8d<{dtb}1;s;4_EIkx|G1@?X`*eh*?*sDtCJwn6wH@gao>tcHD8<}X|cd#OT=~G zjX*+}^OStPxSVVx{}NB8`m?Xs_iE28=4YqLB44J4oh-(DxlTNK#!GA4BTR7B3pA!_yI-|mmi_pavwD>XD{KS`? znT@{E(r{1NIf7(UrTK)jW$dIF82AS2_+$3U7P?o8F~XApv43N~=g*5Ec&85%WZ)1a zH!|{oA;cqBp8=MfF>4%d-|NOuyk zvx#e{&+fiVgazc2?9qoDrqVb2PnOv`fmNw1qua+tHQzA^XQd zCf?Bn9&{nYR9m6HA?(`$!{u`7Rr)e3@C!&u-IhkSlerJ=659!J0!-EuMIz`6s~;tKY9>NA0C)#?d646isB58@Z!u90NCMsD+# z=ZIj5JY;NM)@v{5=%MouiBDi_f>;zKvdDVmT8IAXq5h5qOSTj7$d90banT610h>UM zR~7)3`9LPuS2L$^?pEQ-r{;u@+6ucepybd~93D?b41BH=*61wUX{NkzN(jyP8#c0GE-tK z=1ImT+A>l!n}br*cdcoi(!OV`+LlEv4bU{dC5oLvl$jJEH-$qa-@j|vu=N^_jAA#R zs7H$>4CG_bx+3|Qo}G%RZX2&_k6C)f7P&0G2Nt-O!^tD+S=Yq)n^Q6!t`KS(V+k*B z8U`O)23qi$D!|<8YQ9g;)-OldwoDV}W0)zxkprBXSQhsc?>_B~?++faD&*D%nfqdL zG(JYbRk8DcT*ecw z)p|6F^aln^uMC4jtTH@1uxL7eYrB-dqC3MHY}n~a3`;wc5D(%G4JGH-W8>jL_v27& z)ZThr^ojahgFBzrhNf(l2V3P~E)O1?W1nUoD+86v2OJe!ke!Fodti<#nkop%lobV^ z?~%3B_r33`N0^CG;N`vsKoXx))!`6pZQtPzp*#G@tbn7YH((anQKG1oP`wHeF`PTbQE z`MiWmZcQuFY>_0UjI<&PiE3Xd#{1u5(g~PpIq`IIMbN{)NqlLUIM71G+5%m(R zMFny*K^T(^e4Bpl8Qh!Klo5sHiKxx;t$vU5H%o3Ua^FA(k4eAd-H2WcGmW#>4)_3K zP^uT7_jc169X30brh+6*Cz-G&H(d`=sFY`q98l+Q7O|$^uZgw#hPuO1mhAVGTY^{p zK{oXQf&XGGjFEyc!<@vwlSOx>y?ixV0fr3VHc?uBThVC8+jZWJDYn1B#t>^bX@IUn zXMskKI3uQ6ZyENc)U?(lvMo#AR%gkumg4-=^M5*zQ=pyR-%7_b;u{YKGC z%F8_3?c;h+Y`PxSd1<%z1jYHI4iNc-iTyYz)#3-wCZQcdm5|OR+m^jsjW*F zm&}~xr{)ynm7y}g->@)XD}!%)=#MNbYy%7vSzZ#{lj>nUP`XFN@L;hY+efTcqKEsi zQPqFk2P|GOd%t7v-Aq{2@0DoVWrC~D0o2);F23=76|{trzzw%XOoKH=-Vb4j9E)@; zln=BP*SmI**67PVI~k73DU`+n`Z%A6U+=^7C&(M!BPX#^m)Fye5~I`$NFdKvx2#5B zAU}Xal*J<`_olFOYOT+ED<1@sVzcqTWL7}{tz$m7)8vX3G7GI2oCRQPHquGI!eXL= z5j=p?eM|RLbW}+g@mqC!1$d07sYD%?n7XVu`NQZcdnj=MuDS=(pEmi6&1PVoMThBI z2ECBX)D7{V_OwsxNthqC1%$MTm1eSyTG+dOk1<1Xy++Ta-D*ohp1VLz;x&J2n$UkuU{8J0C-;9ldrxF{%f8EiIo}H~oWct$rf5Bj)sB2RWgDfN;FRyqB-8rH2F{3EhOKkz0F53Pd))Ou7TK%w_%^arNXh zUPj0$!yYqEnwi(@UD%@)ktEjWI9#{aID#O!?E}uD2xo1H@+w%g=;2d1AG_UgLV|vQ zLMa0gH`8ClZqam5Uio`$15Zvn%co4BLq{mJ<==qFXq&%jTEqhNs3;6z&5Y|=aM~%s zhzADQyUx9q+8GEPs!Z7&;gDI3~ZFv~>7 z;{N&Npc@eDQqla2xQ{_jak4|{;))yy@IC9pWet!U%CLX+_wOgvS5OAVS2wL18F0RF zM%nhZf(P+gLMj8gbe2@pZt*Oz9NuW1;4@D~Y!{oYbajCSHCEsGFQdutKytK$egVt> zT}8i@ulBr6Y`(0|z8X^|!?k)XRJCGmmCG`J;jwEM2N9fP+evSc43SWz$^*7p`VC2GAzHF%_ozKilT&Db%d$e}@Y^B;wLf%f z{^BC3vqTznz-jC&(JmH*0UTKzCxTXvIOp@pbH)}#U?^&z*c~Mv^st(FlAP_sqAY3( z3#3@dU&gQ=-{6;5{Y**@kXZC3P~U5kClEe6StO=B@lQ8PLD&~)Gx$if>BKExF+gHs zaVBW5rF4##;tk>x_P1-9-Zq)NpW+owslb;+3?cyDe@<_ZP+8tG0ZCl$+TntKHRUpY zkQ_Aaqu^OiLrE{{nDoogPnvZuNAtWz@}a^lAY<;A&S`u^?X$qLJZ!VXpM#a8B{Y# z&4~yAjfmBeXq%)w4=(0d(P4GqyGyj@bSxQcApNt-M6_3}tL4K4%skdk?lSERZHXd` zmV_MCqt!|jWZU3OT~@%esv7QWO~{R!cDx$~LbE)6cdHi53(LL>k zn3SEf;>>EqJvm~FprrJzK>qvYXSBdeV-bgk+o>z8f!m|jGsI7Qfvn?@6Eif4l5y=G zvsyhliUs3(EE&ZoL-JCcGQZ|8tR)jiA0#2PHqP zpqGQZ+X6`o*2lQd-CMa^DxeDkiPp%`j#NN1OA3|DI)2)V-sRA3&B3-t+pXhMLG>F^ z4ur}2KD!W_m4y!%)Ew{=7s-H`?sRa0RJTy5_37lC(ZBXYS|8LgA|Be#>?N`slaSH! z{03_lm>iT|@Z%SCDwEL9sNl5l@?#}ukL-Fx)&@4;lDYBmoYMKwdC%zI-qGE~Fh^<0 zW;ylnSs}V6$fQtM+}KYX#Gd*w-s*mE1VH4ZYLeJa9th(CQM zAfpX{IJ+{2({8cB_=$O>nA3G?*7e1+jel8YaX;9%icE}o#^3C<*bES``La@|a(n(} zTGSnOzDLG06-TaSK{yp~1&I+{yv*4IOAUliU?F@6Yz1}pZ4@pRRgO>Z< zuVZK77T+0MyV3ln4$UBiAO;mqaP&Z#8!MG*G4Z9}K#g}w7>z_w|7S=S5;J?rv^1|| zj0Qw4<+jvKbSh&(2d6(msu}GO=mDKIt^aJcN)jo%;d4>WUfj}AKS^C^;gk*nqgwb4 zGD*uZ^FtG4f-xK$B}pa8#g~2Co;>Cx3Ll)L@1pvv-vz@kw7z}-SS}@vLdfFYpolTx zVh!UimkoI&92~WwCO~LEj~*I)ugBMeyw!P|Y>r>z_$4O`bc@4C&Rcz;{=a;&)!?o7 zz~SX4$v8-V%(PcMM;5*Cyu;Ztjq6*6U}Eo)j(#t1FwTc!FS{;gCRyPtNzjSh6Wjcy zmljF--`9@DeUgGKHC0`}cI^5p|1PMk38-~5mA(myH{#*Zac5MnBHYP%%ONhd7=(Eb2* zu!BC}z%%du$lIy%cgd0u>~Xmc zY~+uDMR$OI|02)OZ1P>Rlpmn1RHMdAc^Rw9>P5ZR;6Ew;?I|RJMZV^hdOho=Qdqt} zz~|>3YSU|zLqMRqJ2Ts!K1YM`OZ&nmYQT-Ws!3_RsA9g2Siz>X@6iX;2nVpoYqon4p? zXZ+I_NU3{X?32zGh|`*=0dOx3g3yMd7;fAYmnPN_3QVSf%(tLq^c%XF%K#XjaK-$< zGi#aZRR;i!Hn-5g1_NQc3Jutc9)J>0q-C)%r=d;@>A#s%mB2c?ERRZDFhAP) zjLYf{^dhxgrFFPSt6TR1;t4imrj@qG0g+RFzDzYjckGVO$w8-4U?zoG8F7G=T4w-Z zsfrC>P5afGooP(I9Ss^(xhSd?y$S|6sOfj6<;Wmu%cZ6sKkmGBlE+vos+nZUPcnkd z=Za?4*jp<$Xuwr7wrC5hrYl?IJ?AIw)+$!*s3~5rK_`B`0AJjjLTTj(IC70|v4**R zPiBR>z5&cF;&8uHx{^;{O8>yx+ z)qkWBAi_Fuvm1M;OQdp;PFq+MjnEb%AG#uX3nJHvtyjdd69}B1lZxuxs>kxA3)c_c zs>ci?F1+s+7$O~(4Uw;Ex+Jho4)Q$@*7=%za7Yb-uk z4BplHP^(#v8D5U|11;NLqk(iOTE}{17Jh=N!%3dLq8N*=Qa1~(lLBCx%q=^Q%V;ED zOWM3UT|JzFdm|;*5%q}xbHHZweht*wv?MRR6_l}O0EMSN^LT2c3@hBvHi{6i;y8#q zYoY|YefaQ89iP6C3fvUCW%gqei2TX0weAJlE=s2?nQ0 zvd-$|$IJ-DlufrhcM3gpVlPQ9{d9d#cOB1g(5$`i&C4{rkaPe4iM(r(UWP$(?UD|v z&EJKrzY{UryD7AKThYz-1D^Y%;7t_v;_37+=G8V(UwtSV$SrGPd@t>*jn1*m&6~~? z*Q8GPYq;}mLjnBC)h+9gF;su*ku5)VlZW*yE&GvOH`EP9sAipdOMLZTEWT(on*qoO zIo#hWd7|Ns7dvV88RpyKjKMMAJ@1|9yf1&*?mj2{9(8I*60<*WlRfBx4?xem|xQ`Z;&26(WO25eJUAXsW3dE zP)+j5D_5xJ!gl>517!3D_7fK$Hh3PEjD0vUZH97~wYv!W%iHUaZBPY6c1puZ3&O~M z(3X@#jju{K{+Pz3cj2%-@#)>CD{?#3>HOJMF_`IkH{ zoT4yC&ntn01!Tz}rg7cEm**DjqNwlU9S=}q>zf;PFk|Qt9k}Kv2$k-?8c6m2B`2Rc+q%fon{UHxNQ@FHzpVr z&s-qk&!<;Ca9q)ZeuXO!-AO1K3{tF?r@_d~(*ru6fuUg@rsQPaOjfT+EnbRt44o6& zN?d1iEsp^sZezM7eKR)bO_t=QGof2kp zJf*0^DE>S)K44r&Z3={h7I-pr9$xKwZ*w=&xG^ra@bIaPr6(v^lyMy#Wge9jK*{+= zIWCseY!%q>`v+q@4Z4xwtsY;xue6uT5`LfbNJr2N;Q<%H3M#_L8Q#BO6B0@jwTgEsC4fs*Y%R{l^*4UcUe63= zE6%?mNZ=r9`PsjW%F$%@k$X6T*b8u-p~k6rG15xjP@wW#gX~B4XE5!teB@||J9-%d}N5qAS$U6k2oI_HiSAa8<6t{5Fg6GVK}=b-Ny!0p27e>>dh zN%nLf_7GpBztc@VEg?$xjiXQpimVGLTKmuTY%@q`2lbj#`uKQdZFPhCH_!7y(Ft$b z;J>0B7s|q7S4P<-@hRMcrqAFp&`4L%rfm#`^?p>+jDPa z@5V9aKOa%Rhbqbi=YC=4R;C*>N>Sq>k5IwW{MshB<2S=*)LyL1fJ%)U4vW&K z2y&#Ru5KrcDs;E1c{YitoQ0H8+=mtlUKJH_!zI|?`qcI+&e9_VRiI4jUUl(Gu*UpW zVSbgd8vS-)u|pHDsU{pA7xAc-haR!dyePP!^ujnnMic$)J=e2rN}a-VxUMcacMSuR zJ(*(ULKChKT{x+I`n%hyrXpv#6`o=rvJca1Y67x>pp_549Y-Ye01Q_Pa`7|6sgxw5 zL(5yp+4-4{AZo3|Ib()OpYAQllN&4bn-Mr6!<+H6lM~`UWRbzbm!53?lu_G29 zwg~mN%>etGmPpsU4s6UG9QG|~pm5_^BA^w(Jvhp{7=Lhj#Fc|(x?C9Z_^sji?}6*1 zNx|fau*K~Sw&SFu$rG}RxaD`_nCr?Gtqnytp;wwAtp@ z0Nj&>DT&F;%EI6`5smJ9CL7gKclV}(<%bm~D_+(=*Wt2sP+wI~Xf2YiNR3T80zn4V z8>GRZr6R7-Nc`+8_dC)W9|V}O@fi1*?f-c_st{Q%!xKa(<|nd@Kj1&?&K4|=N3Z@O zo*#umDFl?>U_IB~O6W3CVSBW~C%-1?h#)v9TL8C4?SeDi9&9xttw~I096?fJQwl$Cc zqECHgi@+O{_d)8T`FvK=Cn4rf@)5Y1VJc9~gCsK%;H>TDn5H!aa;i|USwKXI;*V@M zMbK0jLF2Fkhfu#Fk`GgYdPE~k*Drh6(QMAVACgWh_>g{(sxm;?#}m~~2pzQ&1=s(* zz0t>q5`0DzKiPRVKYI>pBe1||h`xJ424EYb0?#Z9Xn{{^yQFg0U5sLyVm{rM&b27a zn8iS)#?dQ!4AjnpN3lji{Vnq9LISkx!2o%yDLQ&q?s7ydC)Rc+?R^cxJUB!owKhEk zZ3v{orJ40!%SN~CrWO9ZOy7|2>>ZLS|PrGK@wiYdgE34z}kSkO1Qq2yPbfYAG;K>D4lYQI8SR<;Q-)90yGv zi52$}9_k4-!A0-mfJ4};{{KBSOja|kuaovz9gVgl+N{m{XX**QAWST^ z+PuYc0Y3#)LOFD;d?^zuU`rhX>C+!^5}P^V9#@F5e2l+yU<KxeHcsE542hq zSC6g({qaWe+l6gANa-Sz)r}?e&UFx?tfopDhb486x2)r&eCfz}qk;utgOd4Tot4!c z@TV+Ioo+S02gd(?7}oBwn?N|nMvXL!$Ek7iGL=nEzv{Q?GtvR~{t zlJT9v^!kEooNXXJ3v_dmT8u&t0q%oLT`27A=4xhczPd7(%N+1VnZhWoa`g;Dc9^ON zVa;ad%ew19fOIG9>QoBx1X9xzXWyTon`+d^hZ++d&5cvqE)_ANEg=Qb-}if=92MY7 z`OWVQ`Ezm?a>6WC^)jvxzBE3yjBhU7V6J@yCgQHG4K!=S%b!73Ti8{$aT*O7 z9fLPJ`mHo{`$mHaD*Lv~&;?0p&}JfHUIlF6sHX;29(_l4jTpCRf|4{y`-&^ddoTuF zX@|?!7sv&rSz!Gda%qb1z|?r%I+K7twd60cV9j?PAXL*pRUUcXv!XIoV{kAh9g{8^ zUG2PHIu2UF({MTGL1>&Vt4$$=@17C-TO*9&2^564Fb3;Q-DR(mV~<(z%|oYYV5ZQO zd-|Xh2NKuWBq!(Ywp>Tc90k(xbmjRn5w51Q9ML7(MBRnPwBPk}1e4nzn9w2W#$R?- z_cMLPtXG7U@^2A(ugcHvmAt>Xh0r_QK^G4lO$V>!q*NtDYVt^AwC>YWIb}%Hpo@h1 z*zeSxzx#p-+Q?JJ2_+eScSksWU0I@z6&lJzl%bC%S3&@eP82fzHy2(k1--AB0a)eJ zInss4*|sz6lrL)@(c>x!+%5Jy=#m7LxyOTOy0=;1t?Qwd`1`3EeAJS(yltT-X!6m6 z1{0>eb>(Y@(VOaeJ$)S5*m4T9`$*rn=tqI44E9|l`?FkTnWvZ5;zq(10mGPkBj4F@ z1RmCnLWOdKKS2x+5d_MW+HLHK#Vp;#+V*Lv&(yR7j#Iu87ROsHSV)w>f%OO;56wUO6=PXuVcg>r}NU4 zZt|m^E|F_#j!ZV6Oy?<>85E`0*jcMYb)%SP7|LO+RbWV0Tk0@@%&qK#h6rZJ5kf)S zk`BXACs$x-8C*-<+d-@^t&^B91v}O*My&6VwUKbjFfW6Q_u@_F@-_WZ3xthRJ&E-0Z;+ z#Fvxru&e&; zpK67rfpAvHYq!#_s&K>_zI{TnfTdZPk@b%Kce;%u<0eko^T>rw60)BR$CfWVvg=wb zB@1~S6`O_a8)d0SDo?qOCosZE|K#Binu!;VVO{Zsz80xWQomny>K~BROUyL1KK>txO$JK`Q*FT6iFSr< zi-c4r9AvLA?wcH_e|?(MK;VwjidMKlG?tggloF#g6Ttw)VJ&$JZ2WqmmjlT~Qq7Rv z-;}K{;atU1mo>#dSEa-~*=*(K!Ny=w@1ttqU*VwJEfTN^T5iYo)4_b>%b4+#3Y3mz4wmCnbYMedg?I`xUjNxyFt!#>_ zV1UCj0y3vv_KM8YXs(3t-!g_*jr_Wy{mQe2!>3p8(QT9UikV~I%o}#XbD?|vqLNw8 z@ybNpIRjkwr9Ayx4UM5|Q0^)_lRc-+{m@Q52+sUGF0v!}D-FI?H{gOhoxHau>p;(i zU|HlQro6q9A^Md%-u|V<6cyGOHu)$^D=Ht;G6fvnU$hl6T$~_eR+S##>V3k9tZ0Py zrd|eX-nc$z;eR*{sk6%&whJ-P^xsLKDJNw+0i0tP7c50&#yX-#-KR>W;UYmMiL&14 ze|Sd^_^CZc016q~0}m+kz@%;*VVRRNoh|byeYo?I(aaZ%R+=Z_`@Mg8)_~H=mXhRO z)>@{htYxH@DX%LYFXKAk>!kS&NO2IHuLJnRUkfKG5 z**8>95jK?D{Lm-~QTtNitk#dk0$q8MNn$_jp&H*4Sht($dP*v_hrsrp)kUJp>V-*JJQR6b$nw=gkWHe0(`X&=#{24m>YYp zX=$g0)z~4)6T)~Ed8{-Plo^Xvm>SK=Zf_&be1MIuNWGTO<7eR-2|NVa%qB&F%e^bxy zqiGbFxMCAuYLt}5eu9?qB=CfD0vzJ=twLUc7#h^8xNT$+rR@gh!;CdhIz72p+T-*yTV~cLf zlB7+HG1>0LPZWi^+F|m>aAW7;+j_OmJx6Rh;G9Ap2Nk8B?y|(Y;bWw2xpM*1^;e)) zNO!mecO_bE5Z0}4x!pLIZe2t#sBc506z|v}`5>>-O=o9Ey_QMu9pE)kY@7RRnQ zcxBc;6q&s%_mxIBX=upew2HGY>54S~3>}<>&ZY_puHXp9jFL zGP;tlopA66RW99l5pT&Qv1YMB#`Y>Zz_iA?qdle01Q?z;)bVsz3k}+w&xd_{LlRuj ztVNNGeRJwYm(he_{Z^fjagjizsZMuK$T( mNnQ^P;-o32a!Q{ibIw>gFohjfiAWUm)7_sffM8$g(tm!~SukT4d^ zOF2me9GWj95%2!7IK&mDL|T%wchk#gNQ7-MB5|gFPE0+>a?LJ+H`+6%#ogw}&QrRl2U!simw%HD`-^V@f{Q_mxJ>Mv1xDQ*fs(9y z&==j*!=xCu@sEmAY)dkFss+7SK|>?`B!;={(ZFa2pY%kC!5>G zhUv_zD>4}|8P=8?Koo&g;j%ldXwaGzJ&NI&gNtdHw9RA#3&t2b0@R@uQl(Aw5kUWq zst~>0BCImjh&J&;VL|V#8!+-v%3kT7a@(a5YTzs!;PUpj>s)gF5l?op_h)@sFlH*M zjBZn>i&19O(|TKKx1Ta-RG68G+FbTnQB`Cia9Yxi>QoicO!v7yt~s)8bCsb1t>N~2Bx-5KUNe7urk;=jDMO>eB_oFK!x_bI005 zAt!8(MCL9U=H%zZz&nH3d|yMB;<349`^3U+(9d{Q@HJ$d`%LX|7i(#p{5w!;ZBIApXYJdR-WHIC`i! z;?2&XyY6FJBG-cRcY(??`(wj`sVd>`yY70xnrHkBmnL`25Uc)iLqn=887=Zze^&lf zD7JpcHcz8c@pkk79qF3nGx8I&+EeMV06s}%j}$IlzRns_Zk*&fq?FZyJnx0&L9tkf zG(D(hnx^l9N{`@YjgCmdW98WFcN2J$`NW`+vBCz=?4eZ3X(4l|2_(Vd=>!m4I#i&` z+cKTTyQ!m&&NS%^+TYu^k44@ud?Hmz19&Tz>ik?$tjq;{JT=_lDhf(b6!$J8*4{=a zK;9O>_2Ovz5%0up!CB6}$ihcwF2mJpT~wF1a0+~)?QULIFirrz2POKD0y}6nv_!T= zhH)j3~W{v0L``IVqY)Is}NGJHE0JXb?8ART@!G&}Ok8 zNGhpSYJ8_PTUlHp9!S3m5l`tIRC1LeUpG`)6LanteVpNOkB)M8XN-bzJ|Hv-(Y;J< zpL>FE$!0|0)Bh$q<3C(WUB)k2-p&O|9@mZ|sY@96`L5jHN_oC?fal3(%h_gN5TI(vUlT^?egO0p(mRdyq6sk_fp%X%a}7P8KUa$a`1ub)Cb3b z;+vFlSw*TS>*FG;PQSn;DSNBRgr9L59?Hfrp8&t_O60cj9hdsu7|Lv$I9HJVB^7%D zfw1dxRxyWyuELq_lkhBwLY}9B=lKorltYdl5P);SSBm?Tw6RPO+DO-uvJrOML~~ci z&XsF6;oTA~og`rt-6RL;j4NaKP9VTVfMebk(X}*z4877}y|4Ov1QLbUvBwe(FrRF( z77~!>!IsTr2a3C<=&bjk>5oEpRrT06&ZeDd*cdsEU{@RGLijdcPk!$;O`6fU5#JfG z{fW)8bX$EKVsXiK-eddLTeMcI#%%i`3M9(EYmQ$2%7MqE7d+?(9~QQDeiNcvvxu49 zYR02-nZzhD$+jQJr;7TTwHOA56dRfD)s5<#ivX9=NW_NsOy*YturMI2?d~o@vUtrn_Y6AbFdd zS%1?Z$IJ(rD~2|kU+6byX8g)bq@EWYus>RIdG9JO>HlfC!(0x;%!rO3%KudYHhT}?sp)YWGV{B*w+1$GeR--N2j{nyB zxk%u_fn;1PPf^6(+y@}>KOY-Wz-Pg3M_&7wa$QvG^6?om{tUT;ssKGe!oQk1kO2km z&jj}?U>ed;AC2)&M^vJCwsYuenPv>_6Jk%?qMt)6N;6T`^$%sKK!;DH z;07%8bLGmfrA0$)H>`yjtQ|gFdTyvK2mOP${G(je_+DeDD*TV!OT}=FjQ@bU%-)@6 z6y#&&$#-2y#dx5(qc1qfn|2L+WV=*jf9~!s+Vz}xhVPPJ1yy4A;BOFJ7c!hU;_yLb zG4R+f-*%4m^0mi3e|62#T{pMY5k10ByYInLTi-<|nw|8&=C&V^1+0~S3KSh1_feNkeYcs>|Q5#7bTmvaBp z$)FOZp|1@Y+qmlLoR?dOrL@K_haa?86i|TC57gl%k)Y&A*16-21B%VrHNV3{s<$Zi z;)R^&pO3e}qnO#AskE9zXoI&qnENODeV`-Kbq`!6m4)|d^!V`HVPfIcC7BJN5N3wTFZum$si7e-km4oIcv z!rQOrG28KH0s|&8F{pkDUcVTNP7dYF_+nKay9_2JopBM{U{#HE$_Vj>l&6cAuz%Xp zdqn;xN1ESbV%ejt)B~@q-&8&7D*L)K_B7DFzI0|+@6>v8JGWTsO&~ZImd(@mD^62~ z!Xn$I3P}N-G0dR{q|Wk~LN+@>_@O9R`bul1b=;{dEExB+&x>cJGtBFoB-E*7_5b*| zAP&i8o@$s6-24eROfcb6-OyseG4d7nd>0QouJteJ$t07@_NBuNsNV@(hWyB?f!vP! zq$FQmSt>@qwog>sW=QvuR{H+w;O)&Gq1OzS@O_b!t`BZ${`ig)f)&-++sUUHA%qPF8Aga z`NC2k6Oc9oZApWNy%4Y0w?qNsg=Qxs3z~!@$t2HA6VpR(vkCQ5PbT`cvdL;%J|9u2Ad%%x9rg zS_%z$=Fnf}W!UbOYu4pDl?$tLuF|?c)0zzTymZQz6pZ|DWeSW}-*Elo%R(VPYMWAo z>}u?f!`yH4FpM5?4RFRMjQJ!-rvF-2pInoAe!XkM5sQUD<)w~=H}*ETuSILSCn==G zuHrdh4Mgup8v-&SYSQl3o~cvagE){rA1|2zMm{@4Dk*Kn5c&zxkhNWeqmA0{t9&|!)!%j0_sXvekW!C&;?Sx&_vhx z+3U-TQ|4+sf6|@D!Qmc_ebHFRk9%he-kMo?n1?c;2e~&sgR6hepg8^}eW#@ZXP3t? zBplX(2EiaRJ#-%D$c6R_x|SSMXsr0oC_`=zHTqG>eXn4R_e@je#_^{C`1t6oZ4yjK zA1>doiRDyJ#sZe%-dtE~+<+K3lp<5I2AzPlbpJKbSQ~RY+co>?V^CvX|HhZKT&q7B zX~3~?g;Eqa)=_YKxKyQlD^!@F8U`q_xyAHdB`P_N_ucK%D2D`>eNj2bY9RKyG$2U* z(J<+rC+K7}Z5(P;-TD?Akm6ytQhto7qD_ZUtmk=#DmoKg zi2LNT;UM>B962CV9_o11F@-}IMJl4D)ZVh_Ht=Bt%sCh|d4Xyv)l{tC@$3CITdhyL zI)p6`nv-GYTv%tuPjunC--a%yPmKnve#Z;hyQe#~QFkAjeYMA{B6Stjns_ecKG^+h zkR52WjSI>!0-ubep8T8+2jO}7B{gEGK*LDHm7})lfJK>yk~2l)N2`w!YZpdAveYo$ zt1NrS5HuG9D=XiX0-VRd3aSo>AOn-w@_{^^AQ> zitt*!HtIMX9mT$nv?a$4u`OZxOOU2b+fBrIXQ?OUD)e?JQT>Q~HMcgdgS1fmMe99Z62y@m5}f1eOACV6Cz#_D84I>W-QFH8gAmT;qO|)9T#zZ^a`u{Sz1w zC7v#WW+fxIMU~HDx3#P^{Se*;CXSjWf}p~gEwKo{9Ht)WCZE}Y<%-TI%62?w)Jw3O z&d*T{o36#}{&_m7!_0*dG|X#GDUd`6Xz4sI^q`A0z}r^tna_A&2xiF-Y=gLupX;XM ziO0hG8J2|Le&~LC@ZO~TAtl&4m+Gi ztyMDQO6Nq*4ZXWat@u?z&2Li~T57T0gT>K4F*VE5q_IP)Rfj`N!2ttW(T@n? zqAxh@pI(rcbq)|vyf$ZNa}0gwz#|S{M6Pv`iV0K6)o;Cj_+g*CEiOuo zaFl<5P?^ArkfJ*`5Jq0Y_X{0VnH6}5O*a%*4@Fy_p|(427|xt&o2ggZyOEx>9Uhav zWpVSZyJ_`pG-6E(j-us|VUn-gips8+Va7TRV}YhAFX?;Y{R zJY~`xjKj7im~~jb$D`4zw5=EgyfG#MR7P0U6MD2QEilXj$IgMk!2DZYf5Vh z;H4>+By!*C9yb?e(v*>Jc_pN77BVCh2!OBZYO)2`8eNMgdIZj*){E#I<}@!!y1yT*=>b`)J^_h- zV97~@Tw41ciJuK=S~1{4cD-Dm{cH#_OInEblL78V{q%{&UHCm%+rsVRAosG9@v81Z zS=L}P6&w|nJf5{<@Q9O?7sXPW%;ajTpj6QmlH=F2bT3f>DWbpHETPh*a11t8@9fXZ z#WV5t6Mu7$j7@WE&6RjP+B2L;!@Hu@{lQ1M*lUhbteg&?ct@*pn@H*Gk|4+=pV+47 zZ2aH>L)eIW>_WPHaV2ik8{-6I1Y_go`9q6s?i_4H-tWw`os)T@4F>T-`fJKs@f{+|EInrh(noPg!qRxTNc$5!*GLP=xc)jnh4i8^ zr>^vDpXrW-`}3&P(Cq)?N$e}*b$-&~W(jsp#Ox(OR-Fj_D;^zg_OJ>)?cQ5;1K%XC zkWW^r^ctTnTU14=uXm#0g-Voj>ecz(lC7eSK)*))&N6d}Q#4)!^Wi(Vh^AM|V8llTlRRx76Ka&?H@G0?y6xgpcp|WE^XNmdR%=!Fe-3Dj0Ya@kmy6=&2(+bM zGhQOe3l|YEHpGQ4;((D?2&EkmO*v9Oj5US9qeM4GH3ElWHcj9*94TK6Vj@i zqFlIHr>d%ivLZ3QulyupDwG+|r;!zYzyXMLe)PLPRhe>KT1X*I6nR%(ps#n*JYC#c zl^Wimjit7D)ktq2?ItvuoR>0ZvR)|lK7HmCBAGBPvdb1XyD&Rx(fkSiN3aPyst&(8H`v1=~2- z<3Yn57q?&B;X9}Dru=lzfLhckTQ&+CG-?~STFSsgZ)G_kul7uk-_FaowFl1Ume9;+ zPW|+HjIKdP-ab~B1vN*A)^L5WN}InfNt|F)bnB#fwNR@qMNPj(GlkFZ7OW;&FzM(l$!n3s1qxW#;7fx~NiBvd9UK>33PgL*ez7t6ZBE{B$M(Ml6kiXkGtlSK;HecFTo&=Nu=LbSCJduyL3z@v7y(C~B@WGtYS`iV z#0pODMBKHE7|nk!Ok;sh{nau4$y5u|38d`S@9z&IEjhboiDdrvVf|v+i@bLkjys}K zI?pr%Z62n6EBF^#CRaWR))0eF$xFCM*2vBV*nHgfeP9BkFFyiLCrN{QO7k=blBm3e z-}G^+_A$EJ`wOzixxc4+(3Q?m1)k${tI53TT3W2ZFwLNbIo0xy{)YMEzJ_mXCI0ItgZPNrj!Yg+uof@J#WyiBjsEXhZZiD6f ziH1G>-$kot`98mmI8}IXN3JH)usk;)BCB9df?j)kOca#&qbA7hUx`XBUnS%oDmso zWADf(w96Equ-!Tt+k6Ru>Z#<|&HJSiB}sh=43R3DS94>hh)YY&k97-NV)0Lx*%MSX z6+ul-E}zB5I`nR{MhI;lGL^!#Zh-B1#cjzyb|sMD7$dZ;c*SlA?J{WrD+TwAC&2x+ zjVld^Y4#viGG4r0iz33X8EFDFQFRa1c=0Y*89W2_ZTYhw1~39SG?asHy8sQoi08C@ zLtOVy_aO_SmtyiojQ6Yz|F?0H9pHtkayG7Dod0h*gdJb!QEJK2wW4uheE4jj!PW@O zKV_H>iW*zIM69P5S5XCCM+E*2VvyMfP6&B8*bV#zL_ha&Aqi4XM0w^9+_#-pqX!ks zn$*x2-Y_fqu*ez{C*=Ua7Ho`8|2MP&m0YJu^<22VF;2hEZs&v*lBl%CCOnl z)J^&CWCORUxo8QbNhr(IN5P+r$r%Hk+UN-9 z9)!SDWWI%3mhvj?L!(iHH%A{f5UTqm-eP@*Ybbw5x&oS_mH@{VY)H*x?uFB_7@g^$~^pY=K$-_`HbN;ZxZp32bGh>N(2qT_6P;)dH< z6|l=L8U~rBrYN%_@07P;Z+Ux-*haowmiCo$IOrpszgbB)yWs>1)Nlt=t4)kNb=Yytq02#ePailfos)Frk1 zC0zsSe#uwu=mD#508ik_+xMSm`#*!c-JZM1YpKV^Nxs%6+*19UES;-eOaOjy+cOKExe?W~ygeE)H&&hb9##3XtcRe>@m#0diWb z*E`mKNQixU5Nt*(CBZWjNK=DL|3PeLR!23@Dp=vh1SZ04pvlSd^0-!(C1c^nr@i~&4HY075MtwCyG-}u?p($@As>@H@ z0)~qw`&}1Uw9%3W9X&S*o0UW;nou_r%=#OvM3!g#eO*j!iyFJjX4HMx>gGBMBQ#6R zw=WAs@E;VQR2n=V@M&LaQRsvKM{lcPV&Ax1+bo$=oSA{Yt_`Z^V0Jp0ke5zgw`ejP z7fhnSX71kWhMIt;mvM90rPjRO!Y=~OOeieIX7G?zik)8*NFHg=Ww&N}M+8HofurvK zbfwQ@1w4G6mr9X_nr~z?A5F}->_MC`%5PAP&m1j8pvxypMRXKE(^j7BE4fCObji|( zcnbLLFdJMJ>^Rstfm7?1YLxF3$cQHk!c5xQ%3+Qm>scVP7iknBw}k_rA7*rnj0#)R zV5GLb-li7o)XbKlV6cqFIY{}_=9eySY7w>gZ{f+3Lt$CmWP_iJzc22G} zLI!{4N4ttpn@{d`vv-J z_4=;3tT!ysajQb9zX3Q9F8i&mc?3#08NvgefLhvS4SValAGZtMd%t7nKN8Vs!?aYx zBG=kp`34j#6sqqA8{)6A=lJ7vqc5C11+YD6XSeW`lW8aJ4g%B=W??K7lO6D|H(uVI zhLKM&rrXTf;T>T=1V&L2ac_IKZcr!<5U2dR#0&O}FTh5+-fUzHWwTxR(0{YlUG3aS z!6fiIN?SmSUoA}G#~RIR6->LWun<{$VBxQKOgnB{o8#j8>+j$mO`BL#4OLH(SMVbjccww#VJgmVg8LgY`hHdP%IK`xX9 zmPgMK&Kp3kIl%w9fo_${Nqh#_Q?ZvfM9kp>KAJ({b+w#SuYJU5FAL+SyZTqVfM#2K znZ~QNAA?z4i>|`o5LG%@rvBq$;&}OBuDaq3$ z*cLPd)Q6D22i^RtTA$M1JYpYui0arSDQjmtUHes7byO%iHf~ph8_@8VW`oT*D-ji% z7Rqxt^b(o0Zk0ay+)^eX9QgEVK}KThfFl)2Sw#MZ24XKZ;Xxqw;LWM!QtP$ee)wyu z2CW)GmF#-9=;He#u}9B@?;2m{M74ebB$26HpIu+FqZ&1p_(HCov^IyYdu_w&hh4au z&YOC$A-mi86`xoIln4;p;W)ib{5=}kS@BTu)WrX!SO(D!OA3JUsfx-nDjZKcRD)i8 z#wd{Poa-BA?-(?hqhFI?(ntCv^RcjhhJ>skFA=UTxC~DV(!kyuMuvE>7uMeg`)k8f zAZ!2(d`PzH_Y0|S`{zOe2x1x)89-n1ZRnx);_lvwA<}Ysx3{JBhUcs6g5rWDAi~(2 z>8Yx|>E}~_1}eA5qj#3Vp#yHFx$EsCEwW-bgQG9Ey`2D%GH>5C#B6p`qqpNxujHPK zSK#VqtNvUc;?soPlu1N`t}KJ%pNpr!;RSZ9g4zz5{}vqbS>du8N#(}T|*Y$*ksjLh}d3GhV*T<{2$gmf0yscd{SinC?bKeYYHcUNh?`g z-Q!|v_}g{&3AMjYa-G}&22YK^wRzeja3R%DSK>~qB+=T+Bfq47(s^yk(LaR)g@+Y zMzRlALa+3d%A-;-an$+kpd(}vXkro&!l^}bp0O1D7TD&YZ^m8QKu^rL9nzi3sD65y z8)4!Z4!*_};Kx6fl@Sd|>|1GH~N4e)}%Z895QuFBFq_zZ^~$}Vu^1YD{&19YQ{x}`cVkG?3J5DU3h ze++Yv#crbO;-E}}N#bWW>}oN^A_o;Y&+AeeJM2G~O6rM|4zP73HWw~R#z+8l(G<|r zC)O`u{;+oZhD`Qc&E?9G9pfd8$K?ZHOT5yGQRV>2NUf$|aY27s%*fxA1}M2Y6VRj? zsCnK<%&9a_A^zYsg&|4IA0|n7@h8*2S0L+`zwSjg@yl$q^=iM}$*%=i;xTImn|#i5 zbD;^|<6;m1HYXQr!PM$eW48ow= zw6!A?9bj8_%S6M8R;+*TZ+O(2H}%f=ok@pXcuS~yIWM4bFA`Ii^a2#anPpFH9I}NUnz`=K#M}4$g*a6R z%ah@UN9eM#*mi9tjeJ#QPAd~T&b{JxwjcB0KN3lJo=#vf66s&%vA|<~^k#C1^dB{J z=()q-!BHUd1hTP|5ujhS()mIe4@q-eL3M{izm!}MAWbI7-Y-B47<*W|0R2V)NXb2&`KS)-b2 z6oTCXs<-R822g_kh=Bd^!-aC(=xh@GN=1O%SR_e{l2;cRzuA;bzdh|RJclk=epa)+ z^5gnrY9A!l!ZJ&qlmD@lIRc!9Y`>@)3xUh6e(3;CUBR)abU=n07N^twzJiR8A~-FH zGE|s5_rIwPuBGPJ#_)l1obV?lWxhRMo?29LXKX4!zJp-nIUf_de3$VnF@0yBvLkni z-{r^jj_E;3d}sC(^+vU;gJyB+s~eW*drecFed%i{S_KWalZmdK6&-)sO@VyFyyJ>w z<``$pG((uF5&4@Nm28pgQORrnL(5RT*K^fPz)7n3vx_Yoh`ayMkj#?(3|0FqR1Y!R zKr>Sj#>)p)R4^kS{#|q~wrVC)N?0Q9?piE(Qqm(W?wM!RJrpwF(C5z_)zwC80g(}Mi()(ldf*Lvz zWIBS*_Pb#0+*eYBC#h~w5LW4)WH}GOxrhOWD-=a<3-H2qPd;yIX=xfu>Axf6-s>%s zm^-CN%InJkMx;pKD;AfIEbty!0F6Yml*Q%b-Ksh|IaftF23dh}`y=-P2-1VXsc}oy3Y|DL_jAG*7 z$aogxm@{LJRZ`xqAA6mi$F}facOtPPE=*hvi_g8BRN^@1@jDJWB`S57V(g{WslGFe zt1iurvWl4A(?mA&lmL|&ckyTJ3QPE`@tRQ6x(MG>S6f2W&da``J7rwm9{UHk*6k9o ziU1zF(>I9qpaKfJ?6jI=<^(f}_XK`ATKh+meg*2`{_Bj@Ap(0J(+SDC9O=yORIUrK zl;g#=@`ugKswtUNfqx;!Xyvr{-u8pbtZjr0v7bj^G9y+cry1S})~$hq-}B zP9E8Oe17M(2Vt{I>-QA{=YIpC$+QA^jd_gu^9+oXirZOfd9KGt||Jc_g=vtNOS1d+8L@gm(eJ1CwPZu)5C>A@x0ClGE zNabceb8V`V{ypuwjVLEkF8xj`rg^|>bSbULD@pL;kRYfDt^-njVWTp)8Yk=> zus>)~Nv@@0iPsbn)ac2uy)XMAm*F3?D6-v0}TnH^X z=|5w>*Zt=Sy?rXMvI>Bnn2#PKfQs|`ts(VVTAsXYW^e&ynFE*ryL(Vm?SX?JsWCL|Gr_MSHX%U788_kbBh=j_0Yx-IX$sT-H`;-;w_I{QEpTVwJ1MY@gkg0&9O}t@CoGCYLxte$wmVANB4>uc(t7Tbel3u9wSQulm2zVOLvjvCXZM-9W~RIjqFoTT zI}Z!_S5xkPu=`8N0~L4~0GkOB#JG~{plWLPsxG#Ol()~q;8~jxHF^yk-=`y?!(AGO zfKJ_R>uyYUJRbBT?zF0sN}~88>NCdH^&5ICL1gn3;1Ln~_xF<1>Svb>8;w^C?!nwq zH_WKnedP=jaTRb+BQiEe7Mf>0oK+6msg9{ar@n0}3Asnk@+s3WC{>~Jt^^Kl%8Q5R zXRoI%V8eVCcREgM38!xn6XJX*<5dVf#_I^uX*jF8bd!~2atKYu-kO%5(ieSrg_&dq zz~mV`>I5Vj1GbM!s1+!HesI;+kySwy1GAieD)UV97WrPMg zHS7;`0*oE&p5ru_IAk#|vvxymlKSO<*_r6UDQq>vvgi+@#9HSgF&n@1abG+@~Q5t{|i^|VgL-fZL2&aud&yV{tQyO!OTDgPzHvE#% z+A+e5u>+`?|M$#u33f~yR^^}#_bE5FuItfu8<Hyul@O`3}yI-fB75)tLOk+Kd$d>0IVq9mS3v0gxU@7T#6`C)_HM1=b7X zd*nIMX4$6(uy+kdW6n7c*_!Gr30M8LL$>$@ z_!06TsF4o=()s~fGj}N1g^*>nJ^DfAd-&V-5)H00P_r|4{U6joK}|AmB)}WK7T9`w z-m40V{BGAwVeV5gRAY^W#1$iHpgDP7l#VC)A7%JTK8)g$QAXon419r00862zZ=5kn zWHx&3GPHCLeL!vE6yTR*?*Amr*O`o}0&cvA_NGN>UDQ!jGvzj&Ax=o6x97?sxpdK+#?-W+=L%_CFY?|1X^R^~w_kH-5asn( zGX}U(Gm}D4B@?)&5H%M%qj74f*z76~u<08{k24cNfkm_65Ee*|1|KfWmu*>aMtu+t zHU5+_u6)!=1Fm;;}~`kUgTq5`E5EkIeyK% zOIGlY`$Vv}v9n&bNyPH=$TR^Y%QCIg&)me+J&-DMI?(cgaB$A{6)s2g0yRCw58gO^FX?sq-L#WN@qbvmI6T5lkEdH?^7FD`pG!jGy_MC$9*+dZ(CXM z=2YTI!mQlGN1yAs5@Q|3=-R4CNUk%BUU}xp_w(^1v9}Ou2zq)XRIX+f(WG`Qo|n+< z{maw;=999JkFIVk6gR%@+~VKeWR#oPH&7#saE8+Vf8c)TGk3QxtHZ1V5x&gKuxR2= zx?rg;90}cHpUW{EhX}$_0}50&cl#_EX}X+TayUM^*i~QZ1oXa%gB<7i(6~4ahUVzt zx4PfhaqP@UZZ0miEOtUi6HZ%0h3Zd@@)Xl4t_kxHt+AWf)FQPU4P@d!ixY{UpeWcjQ!+zTzqq=851&)l^(L;eUwhd=pcFas-{yrI~O??&^>onk4?sDH=VKI z1X&=}VD69L5gLPzde~uy5IUZ$%)HVgIeR03PrJ8~T}g;{Q~5E{GVtKDN_3#TOtkCb z;MS&J`8E&EOCXIh0Lt=AM}NW)E+#uxd481=67>Ve!uPMEAu09T5b3i`7A#*I{J)X+E zgU=hF4zo|W6Uxu~DMi2Q1NN1$aM1Bl4sB=7y}G0lX$RAJ1mHFEzz0w{FSt^R!_&|5 zNBwN7W6OKr(zW|)!r{y~cP}G{j4*MpP_5z{{!_&yVsluAk1B8Z>$L2qm+|#y83lz@ z=rGY-tI%zQpgfi9FW+*^rpJi9eyB#N`9H%8=^(Edqdy!uAkHz-^kYzi-pYW(pXtzt zUwjYV9`EtFuJ&861FOt={}rOQo`JhKu`WI*PS7ih5Tfswt#51c{cFj64By!;<5$)@ zPpF3BR(Y!IBiC*$4LjI(aWb-&iXJgTx|;;|ar?Hq?GyX=nHfjM4#m;!6A!k@wJQso z1Zz9ls6&eTg_##rL^OnOG-4M*FW#(%t1{cM&H>g2;;6)*C1cAysil)ng*LmFxrx45v3ahZcRYI zY~bB{Q3^oCe4!`$XDCREF2szFM^rHl<8Gs(h2q-RsmEcOlw%zh&;Yc)^FGM1fkQme zvS(eJP)iJcCPU}FYqs=pF&EwCTPRY4a?fpL#bXJ$S$-hS$0 zSj3}REik{X$|Ga9qZMZy?oW7qDy*37itH`9#Jke};9Q8!LHe1$dUBsHP@?sd?8 zQLXC`Gs}qXkAbU5Ysts|8I(|1yNjV*id9NJrqM7Z9{&+m5yXa4fJ>#-ZQaiR&g}8? z4#@IKN7EwMT7yoO%X&oiXd^yHLpfh)+GvUJI|86#;{g&e<0EQAGHDj*%z9&=m`WSG zDw_Y07Y*%4F8tz(4N{1;2+&1q9QpP65TnFulih2wF3o!QU_h5!#KdRtm3k)J_1Q2I zH5y{`mW7+}XPr0}3S~E(_VV&=92#L4+b`yqqdbYq=RfK0lkM>*2d)~N09p0dE=X<9 zFe8ClQr>6U>V~FN@q~^|!U;gh>EZme7Qlnolh%B z%3w__UtqV`KWm|BFjc4ItxQtnyLNIzF|3xCw&N;XhomCssy9g+!mbMI)x)3-59~us ze#(Cf(x)w`(guHU9WM2LI^Eda@1^!|VI`TwShu=T$)44qNyuw_ER5*yUlObZZzCd2 znG1v0{3;-$^gR;;J{KIvjLo^dx+{3lXWn>Th*6ZAMAp8){oA21qF{YIIItLEj|sF`Gq>Jayiw(pQIq7crVu z7p|G?*@TzX=F^?YH+nYG!aKG_%4c5;9v#+l5JcQED}p5pFGK4{gQpZe8J#NXF~DoC zhd7LNq<8GR|C6>8ZaBZu5g6VFaz-XuJ(I^p8@!jj$OSb%Q=2UY?q)b0Ju!(yAK%Y& zAZWX}$irf-;8NeFPYRj?Q(^5vA+Ia(-y@WY={4dO-W}uLTq-<9BdjIqHSswiRTwNH zm|BE3y`kkVN}+ZSG;7!C?4P!DVlM0gY3!WEVV_NGX{IDzKt!}-p>(=A^OCOQe5xDz~s7M{luVjJj zZ`^N8xlUh}!&YiNe_4wR9FmfP2?AD3q)zS|%R4 zZvgUXVMgS8^%k-{oWi53o>(k*K@pC{*FN|N%IcVJxN_=W52NkGB%*yCZ}{(l}Wh%R_b-G zx2Byln@_FM51*>J0&z29u)+hjZVG3O zcW^+^A$Mow3Ire5RdZ!)_mNmZjc&I#Aw!hpi*YKWoW+CdU+DsM@MVjvj@h!`l&N9j zc>@;v6>qDe=YO0`6HG7rb;rkx#ahx4Gfk9y{TH zG+XAAx$+`~ycp>@nChr7X<#9Uj#_2VosUc;& zCBgQ%@O^UH6YN;+>k*H2gSj53m1@i(;xXNv?(wte?MnCM8Ot&R$ zcV?#cHNs_vwio3OXS5)08*lUHuJn9uV!zYp`1ioT$fXcu_M^JI&=t1+r0v8MV<0R^ z8D44T1L8n`!S&fh&-=UDyzCIeyT4OP3ISDcU(_T;YB{nx(jhMj!4x%IjyT?!WcxJIQSCT4AUTYz>b8m#AXNmBT; zuq=g}mqq|NV-K%fp8^nQ-9Er}^iPhop+Eu?V|dRBZ414z8K{Tp6pSoLNcDpsVGj05 zu8}r?Kf9w1IzU$-nl~}p734N!kbOBZm&J8pfp~7HWFSSS$iL6yP|rDTzjvdD6hRz>a;HAqz9gt>uAj=@ zm<2?s8h#K{OD-i-Ed|5c&|P#v~{&xn!^i#`YCDZ`3e_-VA-8Y+PIFnHbc zNqWg=o33jS{X1iNRq~f^1nB=x@mb#iaxcezLg|*PuTxHadlq&x5+H zu>nS5ZU5_#5)@ikL&BJAb3l4*jqfbWTE%^V@^jnyvj~e%Cp?jG(U1@p9f=e^z?|Jd z>sTszf#8uB%*bKY1+UAm&`Qg){L zuQEuCw;#N0E@VNuy@K2$VF=%m@)Z_|wb*j6LORHRhIgzumvn_F}e%e$UtWP1Ex% z(-6NRDbnhq%GnZy#b(~ZB&6Lug;MZ46R9t$5?f!uF(#BJ#NAoVQMQR+5#5RZpj?qe zQt*}T^tOkpCow_Zs^NtC+U=Ik_W#nFeGQC88nDT4xQEWUFj%|US}5>U^e*$Yt`GyI zAB2s~+7{?ZT*TuDadIx}VvD5*K5olo6aUWd1*lcv0fE<~Cwv0y^(F)Q1gg0}Pj_js zs#>w`f4(X2<0m-BLGsP@ zl^1$hgn@`rc!~}x#s|sG7_n2@y)%;jl0x2Twb_dBO2@?^hDK6~N$72JIPR}`mODS* z)`}GuvqEg`cUW4$$p?TeQOI3GgVB)h#~6+bD;{${G&N}?NR$5q3Wm4kkPihcLl4R?*& z-nf{!yih<^-%cHgL_1(wx=T8Z7IS3QuN_`{dI#aoFU+zKM2A`(n=#5-E*fPe=5!*w z$H%OJpI{2Po71|kku-XMaVIYgQyJuO4B|Hin5dtfKNi3U{4lwE0V9mvY=VT^Sx~l}A4z_s@a_4M_+AJ4v6Qi|Por3b^+>xLRX)h% z5?~^U*`4od(ejrYL7tEVmW-zurPQ~LC7k8C$yY|F^)`Wseysn%%1F1zI^ za`Pr|U8vECXuA#-xM7N-XPqJW>nPa+w9jv&@h#VK7e~LZ!w;smaGNKbrlLAlv|u7J zb-)U0&E;Luj(N_y1GiMO*PaU8mTEfXK4C0CPMMv>2K(S;8_N+ILiLV0w9#Ce1CVqJ_Uy0I8PZhhZ_> z-IPj4`7p^c5tXyu=IyjoPvgWkV@G+fgB^7UmYEc|?}sDTG@0;r8ST&|a)~txl&*=1 zsQskg^7NVPSoH)apU$h78v6!n2OkANp(7Yw`GrUhdjx*h@yPkZaspw6OBt@TmF5A4 zWlJ7%SB&n2nB`3sNhkFi*fnq#^16%_4dvj&yJ)=Po((CgooF~74~AsTfU1FPut*$(yr6kJR}^) zz0wB<9=5}n#_c@{$6O-ipz$AL#Z~qd7BeCcfui^L3eZgCt4cblkbQJnR)N&*7_1EK zCd8fAk6o(}W}(QpSp?V@hH4&U)1z0wK0ZQxrPj-ZB^)U^Cia97o6Dm_!}FPX-44TC zMp`=~#NA}>&E3JERv%bil=-i50=G>;FdX@RUg2*2*-cm_gzO+9%plMoZ5?PoHm`L1 zGEaOI3ZO(wT@9n_nJ$0_3n_PD&vj?QZuX%~reh2L6$|#wZXRboG5eM`_a}0)hKvel0ZrpyfVb+b2F)ZGPTFyu{d-r}q(Q(2P(=G=}*5K-1;R zUu1CgDwkSaKnm^1=CUIg1dYoybyGhBIgG`VT@TAg)Lmp)#fX#tcn_|f*J`@WEtX`z zlaa>x1}x|aE@`7BA|J6kn1-W&Vf3<=UQq(xff8>>@XpdD zzP4g>O-AEKnO6k5Z~obaC#jFfFGO};J>COpT-kCrsr&-LY!(OS+ZyQL6+;3(Y(~sG zM(@h)IkW)0Dvk0c1#?>c?(?x#V>S zOPeXPygS3x#OxX}PP7#1R~WekfD1nP3l)~dRo!h*F(Kb2^q+r#h4Y6{x*nLKt~uy^ z)i*3(DWYl;AV2+S`S}s!pxI9uui?)v$L;v)RB+5Rg^va@a+aR3*uIZ6pD>a6c-Ek5 zkxpo~7UTu_zv&nZPgFwXZbZGHoFV!7{W(r@Ic}zUaHTWE7F(Wx zFg2B(vFO(Z4z)kZyaF;;cqw(Y6Tgse3G+mS*gT>cOG8w3qk`afZ3`j>Zpps-O z`sBr3UF3i*fbwadhIv-nUiv=I3dG~rg1o$jW4#CwO)=K+0ezHG>TG>A6GUN-{$xy& zx)U2`VEZ{WZ6S2HgE)d3r2ilD;u@X3(9v89OpJ5|q5qDpTB;a8%hlY=jXv_e_7%&G zU56Vk1XH4()$&hXaOv9-|G;tB8rTecIqTh?*IqwI zFkKC=C%$of-4R0f$jHBV1UaK*3mO-$lW`nv2#<=&Q@_OU?;6!ETv@L!_Mh#i8pBg* z;T2<<+tT^uH*B%`kt&N9l{7roHU%j-klkOC#g(4H4~jw&=fbPG5M$3xr3V7K{W_Pj zzP7I$kLS{LVHDMoDTlaoWL^^p$d|}XlU`$@IFoZWPc^cKznAr9K&QeiwsZNcQtS^~riUD2ZUjOh8Ul4)1V ze^MH$B`+Ws$I(w$T;Gfbsn>*2Q(yrtkhHO!@)S62e%cs5vFDy=HSg*R=nyc!|G*7G z0L4?(?aLk;HGM8O7a<$uMFN!bDVzon1jH;B zhS4Gtl-UyCxE_gcIX}*sY&`XdH~HeI%)UerOCYP0HM3C1*Cp=~~4I(Dg~K3nO12JN)>m9`LQXXs$U(&|hr4u$HZ6~iP#k2lVQP!Yj| z(nMuEKylrNM83clj)v}06&xe6WHds~yxT#(YoxM>MG;LQ+kUrulp2KIYbk)&upFiF zc~d&BxbU0Y)MuB&0JJBvO}_`M27GSayts%5RKs{3POOcELcV!_WZaSvrcL($)y@r=kD*&7ufKQzzP7KvrC~Wb>jWz2a#2X*+^#t$Eu}bklP6<{sC!ZXb4E zOlKl>mv@T>3Ot2+8#&2@X%lE>wVGw1*MGk}mcxYKD3$s4f0(R4tFOH!bUG3r29N}u zU~4xRm<}9d2M5NwqEki?f0Tvf7m0Oh4Oe*jY>VeqD@r8pRuocgJmhZ(w~;I~h!xzu zOHEmJUZ0{@`x2KM>^Vh9NVvE;hQUgr#2D)Gfi%b^A*+ur5XXf7SBUq%%B)O&B-BEc zw(83!48TR@axByZQ$zgxE%@|;0DLY+Wk}nr$Wm-l>TEmlV%JwzHv52 zl-9t=j1?H4O}PeBi_#+rdpZ}H1bL4_2y~=_^upVfpAR(mKQ9zGYoKahkVW0t^-au< z?Ag8Nrk9vz)$+qTJmJPL_lMHAY1P3X+vxI_@o(P7g18C6?G-=i6P+`Yuy?tn$eAYQD#a?vyjsQ~@ zPzbcLgC|LDZK6cvHshpc`|<6_yuDhp65NjJwHUSX_Z>yH$2bz?^$w~_Gjj`MNu>vv zWXaiVm*jNKc`!qxKw~A!a^2a1Dhgdy-MW&74P2Da6u1c7ruW{rWhVlkTJJ4y z#oAENyxMsM?UP9QUorf7%;`J(9;Fipi;y!i8o&RVV3U$l-VrN#0V(?A%6wax@;_oB z3W3HJ+`RzWueB96mF99-p17(-p>GXl=2Cg~t4t zN|+wJwo?(k@;U#xY($iQ=MdD!w-q}NOA2O^^cDUT68cUVmneyD!`-hrpuPFw$*oSz zJZB6VVa7M=bMi3;rVSkkwYj=;olc0w84j`Am8(jRk67G?QG=tcw)i7>V`4mxb(Bc@ z)M7hsaMc#|C?}}pclda=?*-!J$2{>Tx$$piXEx+?K3kZJlm_UlS2dcN2`PI`MS*%7 z@vyV|r}1}G7wKXExKY<3#)|g%)NbH{j+aw!o!I_YkAfG{kBmR|aL+KQlcG%Obrxn2WZ9HF1jOKG z;h+T9fe{RIHQMfdJ`_;hE5IzP>w5|iPK}kx-GAg%f#S4?=Kk-jpjnYS)jDL$$Scmx zmKgI28&w_(y<8nhRTq@0)gS9QB?M1((+yMXVPr!@D`FX7u=Woo`Jnye7+^n(Xe=lnloaDrbNdon?!c&SerB^Xt*l%^bn>9au+2A zSS9_ilO52Fdk*d%TUnXod0GrRe23b%AP!Z9HsMdcBfK&0IM0>Li$7^Lg*L zwa?K--cekrTuvGZWQHr`ByO ztJ|}7M%Y}_dgLpj9c8|A&2%w7-%GMnlVPz10pgq;x15(1WB9o7$*t0BA>6BIe$hOS zG^_lBD=&NJfEGIziP5frC^teIF#I z!qxF%9YXFL!1P-Z#_l96qQOPyU=3L>Kp17kog>)V)i?%a)Duy6(_QbF=^a zb8AaCkUl_H$R9K zp&{f98q|;=F87oAL6_8~M7sBaNDsZ*j3)|5m4fz@LI)-@M=K6>>P&ytz-@wVeW^0i zo|PM43K-qdkj!CIj}0B;s#Wt|kukY<6cV@eSeh(22#XvGQD0u6XXDE5ud55Pr!01i zBvg}?tz{5r@A%8}oW`P{J=Ye&FWF}lA~l@=ocycste<30u8w=7S`zgLGKoI4%i{^f zLe@-?<3zWFRX_^dvfg)zoFR*XSQs+jV`O!TGbo7%yPBXC^&GkmOn5kY*(Q~1d{^c8 z*jzU{zDx>^Gf2trijWqQDY$01gc7k0Yg8FomO{=dcGaRpX2Z$~9 zV=ENaH(DB1hrOBFJnCwK@sh!&n3W(%uz4xfvYW;$B0waX6YUC5O&0s{d)ll?FUMAz zkEPQFw`$wSh$Q*n_;I_5iTs5qGD<KjLq*#>(qrF1ue1skgkrX1&IX#i149~k}F zSrWqHn8n^9bjBYT0dMum{s|=)Az)DWOx<%Waa!QGN=|1@_|y$f6fYTb&n-jjQ(o_P zgu+VNBbs6)?^hV|*xQ#@2Xo&SS_^sk5J?V3*f3%sFa`WMYKW!te)>T%Zqxdq^4( zR!Jw>SZ!h1+Qk33<2#EjVOB{5f~>>Tlnnd>Gr!o}lXgRCly`lp!!llx1Vlhwx{;S! zf#TDe^)gRI>Xr{$5qH$jg^loG%%`7v_<94(`Qk-^mkSTD5}nF9WJ zG(MxP*c!Q~^)39mpJ+OCriU+j+1tQUcOguQ1pMQHN8_$#OdW@yftbE9;L`CyyV4z) za!Z2EB+vIdF!gYeEZqYE*-x9d;V{AAju8sOay%rVpmWl`60bsYbPS*aMZTbbG5~iB z|DE+8SY5E&Mo-wfun?WjL<@>fM6_83a{AOC*GLYY`Zr?0Ypl=S^+}1#$k`O707=a^ zl+E5?T$`JS)(hLn&RA2v$LZJd;r+rKf{u%-Q0OX{6FLNY0_$&zK%tcIev3esh>XZR zvjh$$yN9FD})(hMZmR+2lT*W10;lD~_H?g6oLS@0F zraKYQG2~t=zC)ej!43tB@#uS1v6-1!qP{;>&@5B)-<&N~moB|{kUyfruJAK&d62=2dGWDCaE z?3rSO*R)5iw8BbsN4rX+7q;By_#ZPyUQji@Q?cOeqx;NyUbml2U0HTl0WaRMz9vMh zrjhl=G$97;%qriJkEQpNcd3^ge2T1`;tzZJ;s-^Lqfc*G zNvZ&HWWJx$i}<$;zdpKQg$mVnrI^GS|Kk#=j5)eu1=#$sMf+`s+88-z29&WE1XJ39lYez;OZ@O6oVVegHfDYwTl4yqH)b!&uGL zsZq40z><*eqT4P(Xn_U&1W!MiwR&?otCH;^E4#|Z&Y%IZ1$4vl3W1c8m_MMZm12jq zKm;LoH+iuzUjGm(uUwNQsfQ`7%5Q8l^MPWsTr3LM026}0=WSg%ZbX4JB|hP0pSjWb z{blt|{zWSB*^Hlx>ls4>rLs!RjEx7@e&W1-X0M-vEm&wZQd$S=*Qv)FgwrBM>r&pY5#z58%Y;V_CV|%4r`PC z?Fwn9(~*I<9rQfyfvRYQy^S$N0`i>H=A(k+@nGQ4N}QmAz_(r0PbB33&W->DiG=0s zUy-okcM$_~caA~Ty452;3^GD*juN<0bHxADENW_=LveVkaomc|z}yrfAw)^Vx6ciM zXVBuCNvU$V_9bksMv8#NNiT>-`}x(QF%^yAiAYsFfuv>J#+Q#9F=!HxiCPz_^C?)C_1MSN&BCO}7RQv$iOB;e|EHs1OWj?G>xI9eX{xB<<=9oK9%d zQf=NS$VL?I!)zlP$H;48e%#`reUTf)py=!AK+RmvI3!MSLYx#S0V{cK9?;@dn0=C3 zauyG)+>lk2_PlAY^|KX^4YIOvO1jB0>U~g=U^eC|bekB@$l6uBY&h%(`)w>@%6JCk z@|A9}t<#VZlBabwQ@ceM38~OY-|xtBkb*Fr+>mPpUNe^vM>;uMZz!_D+-1~&(E_1D z7oS)ZAWcs2>7DuaoD($U>&Fp4KOMN1NkGT>Fcs;s;P!4G ztURot%0VG^WrI(yGytjvFoHWWywlG^MQqq>K7;TQ0J2hvg&g z|4AcWq0!jFm>dn$guwnOLHkJa`G)-pN;XoiZLWGiKlS}@*-m{GU1Jw5_3G})y;d3~ zk80Fmyy_U_Y5OxikFYlokmw4!ys~mQebI{ei`N_aS1SZpiUI^Ti8r7EWU+9{pnx%U z5Z=M_0(QQ(qz*-~% zg%(;r-J$}sLhVgESFve_=2H09m5YjZ_T!R7#Io+AXIIXx2nLq6#catY-^duGfWuo3 z0Su|@#YN4P3iw$yAdGp$;Ub-4L*7xT!U&n0t-SIOQ}Colg zvU_LIh?PTTp*76Smysq^JEGs-#&$UAaxW>b-}ViC3#Kt-z}Ydg&|#BpjehJf@c$0u zkHl zU6%msnz4!q6?MB%;=mtT`l?>Qt=QJ9F@jC;mG5~T-S{t*Q8^w@ePLDHtM=_%vF{E} znenwWTk%g`nx=_@2WEkl$o1AMU_935WY(VZQLbub$eNDNr!~m%cTgrP4Nw>fH35(y^h}0NrMPNx^4~*$xkCvs9z!f#VlegCJi7{N!dlJ^nif+uA7T&uU|E8Zd*ISN zJ(k*Y%dh23H;3~L@tm~OxVx+AWY9f-KH@y3PCo*e)C4)j^!2iC6E(P6oaIbah$2~Y zWREO?-=+nqk9A#h^1Kyi8|kPqNadD6rWbVpa;W8OTq~l<91jhlGV;xf-Upkd zK&I=m!39)tHc$@G4bsspiHuU}BvUjQn4u(n!WYYrz$2WD5)XJcuLr5WkvXg(xr<{m z6Fu!blYb2bIv>;>tcw$RI`jqddM;BnVo6eQs3rS+BEFd)Raca=yZtRoY|6ZD%)Pg$ z_bTH5L_@vJkwZM+*FyvOBiRpUi}OK(ktC6bL?;bS>vYkLLr|5Ip#nP~;^V91P1AsV zEIyq6G>9BrE47I1{){hgxX!4Jg1Lo&=aV=v4$LIw1=s(RpgOGZz;(hQA0w_Ppf?@I ztWy`3Ie7)t7ieEPHt(Rzx45$jZ>WD`WapB}rc$(Hrd)mcb>E5S1`^Pq+g#~gHv>?F zh=TE>{m(sM?ufrJ{F}hKVNJe0Nx)f1BBu4k^zJe-!68>2&X@)6ET02$w|mR6w&{NZ z2G;$bi_sg@@A#|TBrJ89-%!Mj8Sc1^`pQoBVwv>hbcSDZPs$@J{=~HF8uud79Lan- z^=EYi2~JMS_gywA5Jtp2L};HQiILR6k*h51KwpCkho)DZH@9|bHBS>|V>3CltV0qiM4FZ^E zk?pRjatw{3%mp+*fwF2LMk|~}W1vj5BDt9BQFV~ABYm(Ay*$m;?~cl1t&9l7oMU$) z*)N484{`VoMlu=wRg=x|&mwCcF zdF&0+#(IodWwzeG^F?c3Z5@_)EL=B776eF22;hp_e(+Z$x%h(P<4jX7pLGWJPS_ui zxsq3=H%Ly0Scf<}&_G-ml{o}Tf5@PcdC8Ksv@cJ-@5B{RnjvYX1$QTmNvyoHG7*L5ey0MMgXh&k0o-#Ig0doA*MjXNg_sur+rOIEz8I;6KeOk zL(B{#d0z1Bf`?D`PIIUs0Q^DZ(NOYJglhNjYAvq-RtH5I%IVtu=>0OVVuB~-=f z0l|tdP67~^r~BGB6%RTJlh8wyX3yCe&>~XR>)lS?9nPJk5}STvPW1eBZLeaL#yi@N z(dX67s5}QbCOA@tYO=_JVuOVEvybRXiKW3QW8S5w$5DizhOOf0N0^jA8j$|Ol+yA< zosLTRk-?u^a-m9xX>jAKpUkD&e_w1 zd>IYr7znhDmkW`mDmm>D3kfNbW;gI7y#giJ4Lfkw@7rFp_3!V^$4k(%9q#a2jyHny zL5Pevkytdx#2*0Pi~=c`@&Y@kF0QZQEb5v~|Bft4H?Pra0zNgCD^5q(+L?G^4t8tr z)yanHx7HNXe&L{y=`0Zctx0&S2!~&)SGJJWWzW!iqL1alFL#q+b`R;c90rPz#+!sk z)lhXt<#JD0LR>1U0I#{`9f8j&+eBvK2)O8Sa}v36A{3HnMnIuV+y63%4+O4cvb{n} z-W65Kwl2$f%iEOrwR{cjX{tInCGgAgFb-F5u*oU#9pdK!W~{*dn*AM;~fGknNZLP5Y6_WKMt%g}Mmt>-&O@;xCPXTIwB_(a{b7Y=H_@Ah48>4ZD+JMAPCtU!p{LGUu*0^t#YQ8b`pPLv z{2^X+qPhCdchgvUZ!$X==)lzC&_4x?3kdeaC!eN^r8G7|(O^dNLNP9Qh?`Ib%YU zaaiLm3sVG*H`Ce?h}Xph`y@*WkD{Jz-C}P{!*Kx;1t)F&8KB)H2`jnFFOC@MK?G$< zIjFeWVPF`#P~@Pa?hwZ0hfk~}816wWN|e<`=i#1Gbpf7A&hln3#iZm}p+_EtsNq^Y zxZv?twx98}9Rm)IF6$dVXomV;2R@|2w)Ht@3O7Gr$?#Ii&3^kkJxJ8Ew(f%#!Go0( z(j-Ticp+L8PzKgM2W4~ys@y{8J*(LOU2v5+;nC6-i4$DeV{%Qad2#Gs2tWvaR%RJA z-c*v+ND?-iIwbt)BJ1J@*)&DVj9tDf_m2Z2Br;`{hU-WVbU9V$yL_D=Men1$z@x2H zS{&RXrI=&*M?SA+0d$it0o{Jb&ok(1BEu#I4@NG^Vedp7NlMQj7L3r&ZYS;DI8E4H z6YJt_wv5x42b}B|4*Tx)3}rPURkL2qY%g5s)138(Hi<<&dLh88!W??WZ7dYa76gOx z(T#6Kb(?KGe}oU%jrG}*qKNX?m^J~R)e#IafwYp*WYhf|3NrG)F=lHU^E`gS8@|U) zu$hM_m8LQ+q&pXOeKV`(sUB#w}{weDqN~6LoCO;M6B7sZG3o zy0ppmsOAc8$>>T0K?!DV64SnR?IS%1yBjC8xs6u>3@e~JzKJ9M-4r_S&ffcL+w!6* zF309a&8=Ni-3VI8g{m@91|Nyd_Q6h@lSV?-AwUQsuja&WGPuh+z6lPkYd;0?uXPdADtShkI2hhaL9o{Tq^f-NoUZ+W$O(ULd&dhdw?Eh75!Qfq9Z z+RwFGauvI(01+P?*HHIg#k%$J?PR6ReBLcz@*!FWJmQ!kh)Uo@`@($7jSVnmWT0f7&E;2It|iei&bo0P+)9p^0Zp(@kp;enT_i zF&4`~`?x~_zMOQ3ktXNX%$Y5dh{sx|E7-xHd|I$D2Rc3?n-aJR9XG^;d)RK|SKqU2 zq~h>DU=oi<)*?)?WVqfEZbogVuEsYc;{{zDT9rYWVE5bY_aX*AT`v~LN|L4O-Ws2>=i{~5Q#G(D{Y0{=ELAj(Vqp-8~jeA%y?^L z+l?Sh>^|0~#_<&g^i--DR-GB#&Q^bmZWDzo{PLOfmXwPmxLK+f^Y`znINJG=<8f>8 z@$0FcuO`!pD9iAZOJuE-SGYNVYZ0m9zO@o?AI=4q5ehQ}cj3CFZgF(hpnQxJfo&Dp zDspG~%-M<~cmNkGZ%iLov+q)FpSLVNZXl$Tn;uIlCaE=BUKiYoJRhOXg8slcR~bew zP;k(_Q=D7{?aN&4fCjCUD;bc9WS72E=U;|Z!EU+;{~P#ymsD{R=Thsk#4e7WSh~Jf zy9{Tfo>f*G+YHNNlz7IB7+r{Gq03CJp|vzRw!eZ6huIql4T0^{ChDe~W!y-!6C#v=C0}pQ0}{TU|OReM)F1QID{*qI9UL4b}54R zWnY939BF6(7_zsV<%bFjrR3}M5n_{gRY3}l)R$W?lUPdLg4!E;YoJscFqCXX7)gfA zu!RCyK=P7QDhI4sTEZd4%aiJr5xWCXhG+EopNv@;nci%Xu-^+5kO2FQmu(l(*iDjB zGFI(CY?EY1%2b7^XppDB_p^-G1dKaxMb4wr^h4?DfwiXYaBVu^HqW4KN+q`j-`YoC zSbKiCcNd7fK~Yo-hJJ2?vJ3qKn+FZezWJ-4nHTC8TxVO%?EtUEQMOg1qYaVH7G0Q!lUh~L~0wt=i?2^i#39@G&rS*kV0 z3FZd>CnZ0vn9cNIQ4TZZD4>SW74~z?Fp&uycDoMNMVd`^h6l2+SaLEp=Z#q7=rL(& zYw`0U)+1tmHeY@^d-}6(_ROb7MsiZdc`ti|86xxd&Bo0I5^Z(kEeoTrm|+*aHo6#1 z1)DGx2_pG<9G6x>vq$i@0?B=;OQigX)9tTCCqGl>-R8vp`#N!_MwQ5A`aNx4bRaNy z=gZDDS3ZyMC?x^_*DB}b%0AB|e7hsrfCM&t24~OwWI&?#pl#T-?zBIVHs|fJE!dOist4XWBSP*tdm#WmwwV!x6E`d2BlPhU@8Ji{>PYF zCX_#A<8#$0Oj1cvoXT7{=Gjj5`90SkX&HZA5!9%T_;_}+QogGU5t9&y4-%UNcf;kB~P z<2LY~;yqwbr_E>KsQ0mJq@_!hK!7f#=)Q&WO|Ov2ap`2}&4??2pcZAuJE&GRQM65D z6YQ0o;HfC^mh^Vx2@bAETO_^7nNX}hwYEL~3o`OxAZ0!=bTD@uoktSopRarxd#^tA65!X4;NxnT{y{&p zD_ruC8;zom1l|&u((7szPo`*J?grD9b+MXEfFp7@->2JlJJR+bnngMkaB00ztv_Oy zO^VpBA?cED!v&QjCv@l!8^|tL`TucYy2J}rw~(SAwYnb7{IRUxhAQs9mKC_JpVsO` z?&nLSbpKWReI%5Npz?so*QJ5FjDgNZ>I>~=ENJ1ibz(m93X8EX6;NC_i ze=;G=hEkSuh7>WhAZa(2RiT$=OBs@Iqc`*)vrojsvJ7zoZp7f}9+O2t`Z+is<$s4% z-p?>UIrgI7D*yi-QVR_nDyfdQ)-`A{ME63JpK2vT2sxyUThLvCM0hr;`dHgX;0#>= zeTF)yi+wS2l*5am8Ssbchslc?SlpJ@LuSB{LpBkJHbiLjz+bG9SY&=5q|kjwB_mu8 zGIp=`(oc|{6(G-k#bu(kBM=R~P1#6)UNNjNWl}+jVXTV^S04dp&gZ?GUggif9dT2& z-?3>)58QW{N12$MS)LiTB9TPnXgaEWHILvRygw64+?!ww>KeAx8QG7}=uP{$n_c{M zVK?x3RODHg80Cw^VT zP7khT5n=ZyyDMVnbq`9S78|CA+(7UkuOFQue!14>qq)m z)EO%u1%d0aF-Oa=;;0EjnRhB;uH)#^QurNUj9n9huz`z55dg&-0u91B4cIQSV0V|UtocOs_KNIkFplOr zlKG!59lic9?sSNW_A|8#W2^hB^K`lvCGYx){4FPeAt&4Y_mO;d9}_#*7-0Xj)pykC zO5lYJX%f<|q}!xJwj(tdxWr+IGI6e_x3tAE-Sdp7)@^8dKPN;GholvTCm{ccEn7)e z`>Gw}kc_mqUy}!Wynx)|ELqg9d-S*Mn|y8$J0a1^qM5XtA_lF&F8l&cr~=j@S?1u! z%Nwifdo$UB8I3t?cxclQ>F6coOQZ z{k`8Pz`vp^I})gRE32~+=vUPn?FQu3UGISTUV^r@c>_9udy<#yTuy!;_hgsyERYHk ziAJB2|N6H8#yTK-YuAg_u5JD)kl+>1!}k^6c{?@y(C@{hj9w;ZM626Yv=pc~dx>=w z0%EijV-IgS-1~Nmvvf+r8|3`b1=6o$>Fs_2T!}=8m5~D%LAe zPcGufj5*n`&a}sEl3Yg}T+lZ20|Ypb)AQyZ9TGz)*#H)o4J+5#(bS9z8%QJYfv4|F z(gWq1T9Izh&&1*b(4}_%VH5>xz7`kwAMV1w* z<1oR&F+kMCT)p|R^P}N-C8u8JPBG=roe)gcCd26V!mxsJg?MM@bBX9pdf{USvwhL^Z`NZ(@ zgq@}nRBNsGX{pp&jP-7DwnexeTF{XY=l_Ya1LF6cl!s4nEy%p`cFrPM`79=z8nF+= z44s>&2Xl{Iszi5)9Ma$3$U13FUPQBU1snq$_DRaHOv#R1N~gF0o~*Bwf`h~YvAs7} za8;<%i%LW)I3nZ>Q7s(hq;?2@rud7nRy~h`lguICJo`iIO?p&-d*zzeowZQt856?4 zCA);>kXI8=D{R{02s_67rxLS%IQRJ1)8{Dss%cO;_RFh~+UU_5-=wnOHke?^reC8E zFR+QZR_>+>;~75E@heX!`)-ybzV@m#)|TIQB&Bmz=4-0k3>8%X$k?QGkjae*b^KmE z(0zk$2a!=m`GkldU!0#dVGb%xi@Y)01w~+fD2TrIY%a=B8LFM%$zri0Nv@qeVKfJ{9A*zrU@{1~!a_A&sm13it`B8anurHk<)o+$|3`o2PNE6#7Nd0Cd@n{dtZN@L z$lMQ(rI(M>yHO!;kLe6Za)*fSej)Zy79i+prE2-RhM%Z^@!sZ-nodQ9)B>t@wV!v@ zd#tKuyR|x78d#B9-lMC?SuK01O7b)JrWeE~l_b%u)DW`Ej-E{kWFp;rn+$7R@RJYf zy8Q^JWX-?}rQGv+xeC?6Y;TeaaGEEz42{8mfxrKf@}sL7co)E90wg%#}58bHw;NK+YgO+338`$!^%k3_GbyJkG-$H$Yfv56VOb zegjMyA!z6Y%cq<+mXJUEKnIzB;1pV7NBsbE#gz4cu! zQNhLcl18nCa^znj!4I*}SIYKw0la_;RE!=Ug176ies+%1`d%qdT_rf*l;WOjqpMQ- z{wjDWhkP6p49QJzY>>-7GgX=MM*u58)V~0U>wW{=UZqcLM6q}?8kS!I`RqoYHrF*P zm+6pD<1)8$-Q$1w#ZMp-k5`)5_XBf{qMy2(NUuv#x0T~}wV`g30p243dA`|{kIvK{ z3URZdv8gp1iubd<1w0TxB6G7j;EEN!hb;d5vHCE~=mMA*2AZzPsN}7@Wo+ibr|8xD zcKz;7^!T~H!m4Yi+tV5XpCmLaQS=a^G?oN(yH33!%|Fq*Fq4>?%;rniRNQwoMYmWS z|5V6x-Xnzn3-Tree_H4IAOUcxB-fL&vFAQDIsQhG0oPe$hN{;Go_2L6DHZkiVOy)@ z`~Db_H~9IBO=CzjbgzYH#}`JDNnPN|bgqzOn2C%ZU?P2BL~PW!eQcXQKOTh!&m@sS z7RH$$AqURZxKK{~yVEE;tWw1_NW>5%#1AkWe9%6PQ{~!LmON*L_8OIPGTx6)>K6n) z&ho7MD*@96cO$Nh({0?ac%IOwcR)=Xr0XEP-1AxuCY-2;eW?6N-y#^aJd2bj9muDc zaU_jnpvK}!fvXav^77eE-CJQ+aEcukt|Rw*4Il(qdF8Mg2#CRJY(9aW>oq#4@UlsX zO7DIWLR1SlbxLq`$i>JN>Xf>rBu_B=z(Xu9xSK9`P_-z@^seL|;yh}E7vrb2J7Dr! ztwAFXcEAX`urq#zsGh3g`0gd0NCV_1FTlS2w zypr5E2Wv_|RA^H5W506#lzv&qzM>AcG7Nj59I1!PXXLT&YEIVcTOp&(i68i@9bxLK zmRytm#br>-aRciiC{aQ~x@gCHx{B3`)>;G?xlU@SUMqs-xExrwxS&~b4$v*6>($J2 zy($~8fb!M9#3H;ADUZD6g`;eHka2gFqGlB08orB0uf1S(YEmFQgKc%9jp3j~jA0GXx@M6kCDO zri+xI*_HUeNN!l;rX+^w7-~A@5ec4dgeoc9VUCyH_Je6(;r$)e&k_!5k7c?`Mwg=F zTVLPJp)uhUi#^cH#PuA6rZr=t-Sr;I*_5x}YZ)B3uG5bp?Z&5O;pM+_5gsNSNK-$9 zoYhCT0eR%H9@RAd+kVEj`})#a=Sm)@r)8C(+~tk{ev7i3I@P{ z`}BTxKkr|>oo8gXRjSS$T!Lo0^u|4o+mscFc*hUmlzhZ;ptG{dy0 zX;#k5NQdIw=m&i46@`Yb7ld$dJl)qRgL?p>PROHa#c*pt?D5U@-Y=g_VQ=@v>i=e4t@KFwCjj@VfmUP)hWN*0PaS_tnRqo zuIj-~-vOE69_CL-v+3QpmdHiJZmXn1PuizB)%4qJ5TOKMdLN|o3xEP?dsoGTky|i* z|Lheb?pKb|U=J@QHpj`=Q?0H|Dt#l{$x0u$IkDP8+{@mdtMAZB@&|{`MbS08zWL<> zwG^1O4T!kBBgFOFOGVersr!oy-TdlY(SHhV~0 zR$u!K_Z=#A9lSlcCtrzHpVb$CebcU>PzT)yMWhIR6VR~#3C^x-uYH3(VXqEwpP=6i z>$vn)&&{IeyGFNzFy?{@FUh6?=zd~Qupzv^V7GUsj@ep@#$)}VXFzmDezZ z3xg-AV4S@595ts;mSk>xV{w4K!aSc((JK2qx$swus$Tutruk}l@qI`7w?H{x@Tz$n z7C&GfF6$U4_0GXp+nE=qt(WJ1XxM@s4!nlNvJWRY8v&z7&9;1sq{h7@P|dh2P4Q)X z2MywdcJ<*y$qYnjv@=kdHbaOtgH>&4oj7l?(E!N}kN%cJ@qrFYj$lhJ)m@rxY`9Np z#!8AxEm)|HRw4X;_#n#Y9=_77LO(pWAatlJvpr^j^FNTMRm@{x_g&V3;~5ky)?cNz z_|qt`xHQB5n!#th|yY93VelRyR3FQidrH`YeMuzR?M%%-Jrb)-e3stu+U ztWR3(-8Cqy`-n*(v6GED+d-&pR@1Ey*6N*tr}#MQoAo1PhCN+K)Vk~4LGny^s0o&9 zQ)4um>ULw5U<0MBH&}HTvws@x0)na9hXO>vK(3Qa+tRiApnroQUKr&IHE!nc)&U$^ z!n$QXvLzOWar_Zef11_)i40ZlAPL-mZ$M3&hHA*0n?`IgEd!qrZ@Kc>g%wXNwVCAW z!~-0y*mR}I1CFbB5GteXjct*XoDejkW#X5!iZGp4HU1hK?(^wQUgJ%7SJ*79m!FwMvYUu z>gw=^daROjn;>bS}e@n3IZbiTMtLMWHt&6n60ndC!P` z%~Y5=Y$TY3h)pqv`tOJu50|g3%Bwth(b=ga59SjxL}epscIp)9i9P!#Lb_!?3wNHV}okkcJ!)2m_ zQZP1CVIc;lkQvy{D&;FA-$)5DPlup|$8cVTFs+mnosxJin^m_cG=690=*Bd;sS~R* zZ1LpcFICyW1>5q*Viq{bjZ-dtuMiuB}?S_ z)F(TaJs@qnm4XL;wmJVqo*rMCfQdAHg#6rA;2jBJ{o({)gV@a7oun>zT1Dp}`fNGqiRTePZXOf-pmosIo{h4nLWMGqC5O z-XyOizh3B!VoZjulvDc&!7CxG=X!)gvX8)*fxl5qb;EXg##X00)@_>3Fem9SkJ(_4 zZSI&cFUHo|!-t?^%vmE~vbMt)(E+(}knej$Q%&i`a-K8;(y^#nk$HYjQ;er zkto~_CxP0j8QPl~-cp8$X$;445qukYVfT_(USZcZU9TbLdI(!!OzJw6tvEj=*T5x9 z+IL%6+9cB3EiO!&MlMzAHXM@qjy#u1Bx7i&=!-^ z6qEkSFHNMHLjt*Izo5jDCIG2{#%=5R8_OX@)`itlDm}E^e4Y*NU$=(n(6_oL@ACO~ zL0Pu2+@9m06!R+xokmx*OB4y>A-sqs7Gt*5y7U3X{`$pSvx}Ga3Q7qInL|0mETbU~ z;X`io3BJ4`kT#4(y^KfJ8fa*gfkZ+2oo~U=%W*&=a>@dG3u$*!UH0bypT$|74`5id zkvCo4Yb%FGX((u@_xwRMhF&Zso4N%0>H+Wg0qP3Bqdj=LI6wjXFsl&`;#V?#gAzM^ zOwIjfZ~{dnR5d?XmcMxbo%{0kK-WoyBq?q9%k{0t8)^Q&&Rlp}DGPu;&KQudR}Z=Z zpxikJt{EB&4Kk)k1mA2%;pd&AxiH05%c!5YV+_wi9r=I1RO!h6ehcJ4EEFW=x?K-M zHOz|Wa!?aBuNsYITdcVAZ$OG$!{u3KLP>4TR0qfDT$#|rEVgT+o9m1Wis*i= zh_=)R?rMPc-<>Vy|0#2d%2%S4mTnK?2JNjR8#V}G(QeXH9?~Rgrlr7#8t(E|nKq6n zDKF2nP9i&_KvJ1XDo1ZuwAN2316ESx8R#-(Kv%bdyW~HEc8!k$JyTRh8UOJ{4ZRCY zDqKUtpy87rX>`TurreF1?gI~{;dZK2sY;XZU1-CxWELGou0m4x$B2w#L0)xxi;+vC z>waj^{dN&^{^`W2bn|;=Rnq4lsiS5r%Ev8tciLCh;lEpWqGY@X*C34`r`$z6B8M~G zi*RTTP*P5nMJQob_{Z!-aRk4(s+bA4@!5K9NX&(+D64tZOaoB?XSM$aexdfK9|qxo+iu1o*JpVV1j)GL$ub#t!rC)88l8=tIf zlr;lkxwgTLrhoW7R>Vqu7U(ZjU4wKA`9!tN`}Q8yVolDABo%m-@B8p@!rpYU;C=3J zWkkY4e;>9K@Og2W%&4;fMu+kR@%Lpwi}gao>^EtnB7h6H7HNw+>zUYPzSommJT=?# z7P@}q20dRr84Q}US#u-Vm$tW&%V1^QJzW1qR~($!@onqR@c0h&_Fx zklB;I0=sJE#V;GdALUQApKwbe6)(}K7IpTQ&sfiLnR1vEJ47x37^3yN*_FYT)k=%5 zb?~mCePaULES-R6ZjY^d`IvLuisXU&ZhZ8DvAHp}6|k?a`;I$#zptf?wJMQ5)*(%u zWU@JT+>pA8{qKsq-{%zW00E#^tZio}+30^sq z|6Hrq_KZ4tNWPv5xL!PdLI!^EE%l&i`8N(3SbGndoVq44ew@BcpAb^7X8kzxOqFwH z&<1fjw~M^<>VNq$Z~kk9?%x-AEl!(~VN}-LlUdu<>(1LdcX@inmsS5Dys8*WqK#Xa zLzwEOHRm3;pBwCux`+be-p)pk%75V=Ew8eDlkbu205v6@#SJ1D$T>mTyQG#-Na?S; zzS1_xiai`_JC-j+d4$ftQGxn&$img^Xt25Jd}VEc3ohV4^6oV-fid;zdw9e@tZA;9r^^+E?B|aH^ocxo=RrOaSQc=(0G_+>m~QR_PZZ?1 zVT|$~l#M_nlX|$mlgL^_gdSO3U|7Z!c_ns$bXQ7-%~=ZVT}vtORn5 zrJhQl-w9>|qtLAT91u>CRUAW+T<%)_m|zrSTxWiXHNSZR|#iSk})WLI5L9_r1`UAA5N zykF1ho0O3Wze{eB91pCCI#I4X6o912fre}A4v5?GJ;4jK^l#-STZu4HKuoPgyrc&n z?s?mazBVF3L`ZKI;*O46(U8J8pCnMRk|9aXRi*p0MX42brSTjmX+GU3E{_B;#I5!0 zG(+&+ur^V}_~y5cbVfgdU|gkj+|mbHZ)GeYfR6)LK0T(#U8V{Qndd`)xMBC)-0wm5AIQkdrrVA%4j#V??vBY+Wl{H+2QGM%qlBB6xO)1a zGPH^N8h&tCDw-ThBn3(5(cLKU8eMDf${c6)3?H2gV2JIF%B*@3Idxi=+pNPj8)?zM zyims$0}whLO0CFU?xD`ZQxyqX>@2LP1=YAUdVZvZLGO+G%V0>XOu{Vr;7(sOzlpEe z)%oNBU(2UK;)i#aAWf`@ii`I*CGe{-s#1WNS$om0689IRV9s0N@UoxSR^iaBtAbNV zSCt|K9 zm?WHz$;CqQkq1UWxFNV&@z^OV3wZWZ+F15y>uU(e-HQWAuxirJgvZg66cEF%uLtH( zuD_h&?=Gjb0Im~^lm3GZ$`H-&SZU>ej{)ZX(0HKz_1CQ3x>h{N&1Dxp1r_@`T(t`&)^14~i&`WOHC5;ud;=3O!~EyD+o2ts)( zijb68kg+BobE6_SWeEB9&>Wlano>Jqrg+D!NhoTt%@4sM;_jIbKGR6z*s@PC2oFW8 z0OGYY!-!${xMA(Lk?&qI*|$={hnV5tu2ms3LX@e6_oOzNVuJ9mD>;uMR@<*(J- z$2${YrEEgMw(XoVac;%d6q!D_8Pm@Q%3XeV0|;_weOiFtAvRt|&<5-WcITH;US`Q0 z^bG;xgp%i)p^GQ<4{DK$GC7}&>7b;aKC525d4EfCyaLH^(G237gsS3KAWC|7vDa-7BJcIXSpW~Bj%Z$h#^snjc4J_OM4>~5>$k~iI< zj-DSZDlFh@BP@a>m{sa$u2J2mQ>qsz{jSWCU>g%G5~7C%a!{!M_@T>st&m*S)A%^) zShM8gbuHVnsFXq-ZZmyT+Z4fQWj7wZY-u5^BCS3UYLg=Jce+t{ch$HFgV3RiDo4fP znxmuxP*Pq!$VJA=82ZM6kbVpR>rc=X1>f$tFY2XWP)|K z_DWO2_kEm1{V&+%kRJ`X9`G1s3eRnCThCu2(~_Gf1kQ>js@v5f#ZE)IVDGEcH9YzZU=G7`i z3}2^CUs5S(W#B#SR)AYZ$ehf{K+zDH1 zUy(0}qzMKZ_bz|bufcvhE1EJwXL3^lF7JCrDeChJGMVc1315{qF6h8rLcLgAF~DjD zWL=71AIOTEBaHPYq&QOUX;5x>*Tl7gPFC(K4EcXW(~PdjUZBtv>8TQjdYWGybHN?@ z;KzUO)E=xs8CqR|q%taSYiH8y?z;lFPvTIyMl>E>46TOO%H`&8y(W-3V|B>_%_aXC zzyjAotMgb# zuX*;njCr{$dc(YgxgW#)_X3EMju)Ft6Xy}qzelhuL0jk8P)BrlFDk3?yx~BKK7e*Q zCu&lqmF-8bN0lHN`cT!Q@2*6CuA>#WB*L=0(GBlvuVV@{B<34gM7T2j3g6&?>*FkqJP#%2=jL?l%U~I=LsG*umrh6fVn!E`qC4Q%tMVn zmY99PY!WV%TU7V$tO@}qT7Xq* ze1b`d*?hzH##5Y_p09Kc#BcJTweIj?2fTQ)c!P)LEN#Nyd2?kh79%ra%q4s)Iz#}T zXk;krx|Vyq!)8oDZ+-=~a#VI!c6!3vppQ$ECFw5w&6_%@siPsP-yIcbChQ8RaE%e6 zJV0^Bm_dyN5*Gi>Q4b@Kg3I}=Gh}K%p&!4J25PH5`69yIo@R+;ja?vm%iN06LZE-3 zGtxwJ2xG#)XBtUi9GZT_2yE>k2LH!bAP$@Jj4@fJ47MshlkM+1T9}W{gLq{9JL!Qf zBW|EV)Pf!?7WMgWuc>o-CW~*jZuE<2>%QEc0r$Jt*=w~8#n>3mmhO!V@b`{xfITmV zDOO#%RFW(dsmkJp96bFs9D~(pUe<(i4QlOIVkhvli>_$N!Nw})S(5j9GKcQb4m=>v zJ!OoKRMjc)(KrO2c`_(9pr|_DhlDHuKrO8hGJm(`zunH=`J2CcdQ5YZdVO(j8W*K< zp|7C6G$KVCBlEU9g8IEBAef_8kuwfQHrVN~m|Ea`RwkW6+q)ddG>(G2)T4hvcX>8gi1%o%= zLr!J~<z3kguU$WJdu4#Q z4lf7v7bQSO?90C-&4VCsbQz7CN9iyQf~3-+4m$yj*t3<|aAECKb0wD9B#aF|j5o+6 znzkoxNZiDcMFeL{Ny9E#3AKggvd&x%gf7Pt&vmc?RUZ zY7I`&W*U~4giGX-{L)&Mvpp{>rEYei_-`tg2*IiZa;U?aFB1xn=^x3k}bfZdAO{Pnipo*no96YmDvBli)0u_ zZ$wZ*t(PeEje2A?9R=w1o!mRF1SNyCoiHV9w|r4fg)FJGOA#{xl?fsGe)y>^J7OA zoUx!KZB-+**K4)cgVh2dvD+SYMRg=pP==@PVnV4qI*vhwSP zkC+NbW(>zz;j2nm2^1}z-Z#x?xkWd-k)Cde!-(vlr1K0JrsSno!8iAHr#V$`kD)dwjzteRr7o86_S4+09MB8l>xAAhk39{C zmm12HMAP{zQz|^H(~9N{fouzL;~X*=L)=%(32H0YZaKvd`YYrCP}UyPO~M!jnJSEB zJa6($TK44>C$*lS~_E5UOy_DIcD9nE+UV{@MHtOBrC z!j0zfKVzH~&33(&srkN24 zd(>Yiol%u4t63e8{$y8Zo*qwuc%R9@ptqxw|Yl6-QU$#gwx(T3F^;}rK{Kr;|BQA z1dus9%G0I&hI{4D&OyN!PIWQ+viJ&I`d*QM>CItfCk_&ZQ_s$Xoc@Ve+INjaFXI?t zykHs6#`;E<{U1JLMjj*pI%q3tfQx4*Gr)4U)vLVaRtU%6fzyJU$`3MQL%)RR@GhdG zvIo5=*+z264w#a97EGs&Kxkd`(5qhO{969_w`jc$rP&8?xj>P5-5a3SXOGM)Ev%Xu z;NU_zHQ1`;dn)V?&ITp#dlDx-QxpVn;!F6EuC zYcGr}H{fA^?%#3VArr8c3p|u>7&Ix=Cu%Vve21H2sq~Y(KaMU*RgNrsEKG`h8FYi< zYCY(`o$)u>FcvrgNEQQm@%YL<#OCth!9rx)kkbW)GT)`z!4J+4cFi9Y)4>t_Z#Hl= z#qzY7AEp)KD%Bab2={0YEm#+jV{c%m%<#ITD8F4yjZSWUlZHV|HX?H8Y6ZTQ%49t7 z*z7*`KnOEOz9$r}O9-vZ5Gt;i`Y2gB5i{m(%W;3U_sIQqej%xsy@U38*hbof%fsm7 zX@m30?oYEXC$nV`15dIdeD`rb_Wo~vcO#EUpBs)hJC2uJK-AI6yy~307nlO@w!G+E0iKKH`|rpxBa|j^O_F*nmC$7m$HzIDk^f(- z$*RrmS_iJkEW_o?kzjM2r8x-8XHSqNze5|u>6;*?F6`6%&5hpMPTUySVf?4(aZ(P7 z>ufB}Ff;0Lkps`6-*D<5bHow+*p1m>*_Cs;cf`r_)*HzTlEamj;G>k!GdK+CYA(;wlY9Fmd%*0>2C6YdDhl||c*d<-UP zd9Dhit2z{@Qnef?4#LkH|J)Bh_i66sg;$%1sr{&p_*8tutZgKBrEeX@#XJVji(yO7 z@J}~8nBS_Lno4&+${wmyYrJ#OPpMbH3wEZe@h_{V0{UFl%x)DgACv>;w|_yd?>jEk zem45f%j>}TCoY1?_k{vQbrW7nfMp?*Dyq)~{#%xP*qV6|){HYlXjWqufRiV%Q{YB| z2!2Zj@F#spQ@3kxPFN>bX|qxMDZF*OI*BHY>Yi{(U1S?Y8RXD-feWV?bK&4PqX@0z z65#dlT5`rTNu(H{uI(83GHmh3fS!STQiC?8vLLJKxe?FT*JYA}kYGSrU^FK0pJvgL z7)(6Pu+O3*Ym6;RFYFZLIRe% zj<6EJ7o?w8=;a_}fWQvSEk1w;recX0?jja0*3$>ugXQ37wK`VU#H|SRAcBs2*cmMk zaWsM1w^b;-Yu3wf2GHfzT)LhsB6CBPhh_HVYM~vfE-`#Y+Nv>@)f?h#o#O_?fd=hy zsJUiRVA2z1kGZh^^uW^_gvQ5sD*fIq}Mg4Fo^Z|5+vE6MSs0wXBfWH<6Ff# zSby4$Sj-M;Sz0|Bl1Dz{j+K|P<5a3?Ke(}2VBWpo(`7G)aUKF_F$_zpjKA-Rpy+OO zJ_%lndMAUH>rDaDqq6}0UsM`_R8uV5ovY$EZo^>K=V3sVtgKGwJ4=20nw>LL)7?|@ zvr6=NmUy4;_ltwztVmAjo#R6VF=EfE%$mqx0A-m(UeAU$?ksfvirxXkL$j%MGbAC( zb^ueTKR`#rFeS|#UD+vlSbm1V;vZC^UqqV^8 z`yaMe7YX1gb6i4Iw)B_{UNm=QRD(4I(rrF01}u+aO(WQM!v+y+yje%gi^wc9n2L@I za2DM6zFM8a+P)-fMRjpGj`8AeD|x?J0lSI@*a7)rz$o4J#WxD$WRVN@+?)26t3WWGDDDbk6((nraa!UGD9 zlq_&})I8gz&2)nsrnKkhx8)x<&f8t}}{m-nPtijqGke-1!% z-P-Dr^CDs|q$bU1w@T6V+>rz-1Kh;k24URJET6P8cwh}|h?CL*5E#fGNL}T_I(o&drKy2-C+gW2uC*W z3n3R(4rnvgeC#m>SxQ0v<-0Js6MO2v`|KKl6E-gxGB=_Pis*D0ySfpM8G-M9E2U2t z*HGzw2R@U*-Ap(A0lMdV;%*+Mj~pu9h59MSPJ74M!B`iHu42zcUm$cjae=YaOZfJR zGBOT%Ek|;bNEh7MMOUYtaNEE2Rdy0O zY{^)w2|`NfKa=*LSwwgW8G{~*EK?wTtk9X1y|>VvBH(gU;VrfL|CuW;n%b(^2Q1XW zo$>A@@)$hQC1ZdAFVCFs_i@js10jc!k(v}q!j1J1OZe`~31r5OcvA7eh8f$g`mSwS z1axv> zAw4lpHAaZFCubg=Wd7U>ET1ky%SXFj#|1b@`nj0Do%2AVxviFTa!6c@dC5z=-z00;=hx^<6yQ)f>(?YLS^;1%yA9MXA@C${~9uG51g=w<>3oP^2Sx=E9F*8l44 zRF~-0Gy=h>8iHt_+qB^)j4&&{<=gacHXU0w%ME+APS=qb({_m@@G9O=i98mSk$}ZLaoKLowi=KpZEg0qvq`o+H)V@!{WNo3*SAdyW$L|X4$zG;JsvCMl=Bs$SEF>D9Lkd|4%Rf;*a6E$_f+lQRYR?1P76D8D{L=%#Q! zffzDxrrU3+BWoTi4_66w{^UuSOipGa=zC&Mfvi4Wb39tmj&K+)gTyu$ZgmI5CFEw0 ziQz@Ek-5QT6dJmLWzz1S!arcV26^1^ZU>9pR>yVD93u}u1$a&-c`WPSTo=-C(NGcs zRBrqiDbqQ#H(N$0e{3bvW5}YBM*RPBT}->UOrkYD*6DH(@U_}@1QZF9mY*nURNY!7 zREzEXkb4Pn0^Oh-9)HN#)~NH%CSNR)^E7SyV9DP5JEdcIL7)qLEnW#2U5_9bhptO^ zV*o;k_R|_$7kJ!OU+pVg+6T%RDJ6OD0rlaGda=DFAs$;ri3R6Zfy<5J?jdD0&5)EF zuDA@$8~J^9c~)q48=|)t9Ckv7lZ$(l-~I2>kw2+2%zi-8CNe&!M2EC6LU5nU{9rn& zRCqUlaIO2AfGIVIfT{Er3wzf={#mfX$Xh}H8F=t;S3eGUcm}1WZKT}mX?YiES3^ii zK@qO}lZc`rteL-AeNvoGx<;o{q(+!uS5 z3#c4vnM*2c&(C%!8AQRT^4@x$bcJ7#jMTw+Ww8 zsJkpEiZi#j%e9VM>$YwhN@TwCpuC5z0*Wl~!{0FT0@TBsSf+X zdf=qwh!CQ8FX7;t_<;FGdNGG_2P~`Bt_nL8XY*f6p|SnjL4gaOk9d^v`2J#HFVcaS zdqQsrKtriouwbBKU3dV6nX{+TQN=)z3RWXybXu{l_|=D1u8VFiyCy$la0BPEY>2yp z`diLnR=C1>L%jpS9P?9gg9AE`KD_fH_aBkvbTx*13bgN@-u(SHCIR0cbm0dIZ@0fLEf|SL2l!L1O`g} z++!ARyBe8egtyqKslA9FPiADv;7?`j_b#VIZ6a{7B*H#_`~*aiD2@0atB^#JQ1iok7xn+`df)&m%eEAaJv| z63b<{${*Y1Yj?wDnO_T&4;P2aA)qQsKD?7uI5Ppdr_Ykqi{u;zk{E50HE?ThAf^QL z>#9db23=|vUWTQS{^cA+O__4Pl}2fEMM30k>Cr{&oBJ+*Kt}wg+{3Te1m*rECTx^H z9ACmTcnHUAR)*3@kf#T}VU&*qhNAK3Rc2*{VN;|?>PXU4i!=!^pTT3Aei<{80jq32 zZ9;D-0iQF1-1Y$(z+zm=<+0WqD62a~Eq1JS_zG?aJTYccjyZ;8Y_Z{7&5o)BD?}CD z7ruD$;3cWc0+|GHD1}IOR<*Z<(7p-}gVKkL0M5kID6;zOQgbco)ZP8 zL`vDg|B5g8oQ3alkDtWSGK!Q-9E%2S0$T4Pw9qjME>-H3{=*#Hu+>AM;3S***la+f zW}5rfEUw($ag+5Jb$ z5$h6dyAfvM8XL)dHI2uJTbt8yz(rObEV->?(X3VnJ_x>c`Pbg=xL%E0C%LS|sO*n) z-gz`ZrxanNf+TM$qUB}3^nn(7uQEioz?PX#_eXt^$~{c)J2(q1Bu?iyd2l*nj>n1_ zpBe9-7)4#HxaHq0@{3Gq0oRa)NB5Ny-z+2TKItml%6=?Cm$5A zFhTXIo?$M+@g1I@1%t720SmAoenjFeH!G1g*HJM@+m5m0D`zLwpo0K0quLpOKOC4U}6DrKR??tR%nXi?(e z;-;~bVrM}NmN^a+s_#{)kQE7=L!VrvkhMMXx=T$Zb~67(c$m`Su#PaR%+Y?iDFNjA zI|b*gD;TS(P21tmp5~tmXm(4vp1;&THWY1vFBDpnIpPJ&Z7`LWC@ol0VfR41im*+9liByL>TgNX`c)ycKo`_52M<8=iP-IPsV=cn^c41W$4V0`s zUS%xn16;C-yB=Tu_^lqRXTRtRXepsX6?SWwvdbXH@mo4xyrB|YD$Q#KlzB+emOM8a zswye^Q7Q1?usi2&^kXzjOr1n@GFD&x4nL|7(}{}sxKBD4VSPnUB4`~|-PJXNa*cBg z43&CVGGE)eJRpQzBG?ybLel{spW{J)uAnlouuH2bV}8sHG2@&iQ-nchrFxGuBPVn|i5-W36L8_hEGP>KgSmK`T%>I{))X&PGRB3`^4@3#D-kqs1YR|z4^MQOd{`!}#$Jv`WIrzTx5;ZpDc71zII7R2UGl@P z8mr%&H`DbzVMvQ?vi*gdnIXAUF8lw67QWJa1je5M{1QcenBoV4V~x-K(U~pUn&-jo zW+l{BSMUUei&f{!LuJ_UuZ)0u(hNPjb)c^Ye`F9pR0hv!L`mRRVNF)gZ|Cx)Nz$N# zm*{^-lFN;7LCpF*9eWld7SNg!0HP38;XpXF6em$Kty-t+s#w=n{}*8AJMN&h?MZx) zjl2G&2w&BI91m5W5u{NyBF$BZq1~$ytd~Yd? z-0`NnETT0eMOx{$O}((GN;;7xO8W7SX|cC(6u^{TVAHhXodNs&gH3fgKsy=41f76N za3OG;rBa%mf$a?!V?eEgC--y}Dbp_r17A?9SUeSFUAN>Ql^0cyb6dmCDnw2`pJVLm zE@sPtru-|}u-Kh0NFn`4*+SA@NSR$xl;m9-hh78E)~!-Lnt%P`4oM;nR^m#B7&Gvv zyABO^92Uo5G?Y*oU-{2V$>yj19_A9=)DFa>M-*b>+d0*^RW?`1%i*dHJO3gS*FLG9 zeP7!KlDmP6mAAgE)Z1Q7lc*oq-$5wpy2wN0^4Nl7Zw=u(F`*C|Q=c9Cj;1GMg#Yfk ze+OHIi6x^JAAUf%sQL5zRTQUpoMN+U{@I()(+?;K8BU?E0d{2X#mq{*bY)%5PbN=5 znM7h|#GDAJq4E5Fw!Jm8NN4Yh26>XUn;Q!Ju$z%U2-J*=JTEuBDFUxUOZa3+JorQs z5U4RvDXhRQGJr%=qx^IgR@hNP_Vj;H;rXWz5nZ87$ac_4dw-(A3!3if2A)^LIeDy& zoan;?1svG6gP--y&1Jl0mD6RwSP!Ltt3jIVOBflSbt;t68c6lGfLtx^8t27c`$hdU zLD?5QSxk zN0nUzsy2Yt7n8d)ETf~UpdL$%erQ6v`0{Zzf}j) z%tWLYWFA&Ay>4c9Kb2INCHP)LclX3qq55JTyRA99m%!&VT=wh{mt9y~5;eJ&uz>p; zVQ#{-7?a=g_6L~rwRXJ3Z%TTV^51Q<_gto~Wt6Fc>U9Ao%Yi_VvGPr9lF)8X=r6m@ z$!ozF-))XgunJ`LXaDjMO&enE>(wMfXsqIY|2Pyc0)l?`6*qEt@oqFGGCYX)noAj8 z;eYZPh#eYyVIb9hA+>%pVJP z1SXhLSIj7bcIUzY@WFoXey}0sjQ}@5$iIT7+E+`%^c$1X)}Y*aDopAsjSbyrWK8#8 zej)MXWymrhSux8!m=0`Qv$p^sYxoE455Bb+H{9vlN$cl8kJBhe(ctPPeDIv;A!dZr z63Y(fvaR`n!12@z&ob3AP&3e3F$V0we&w%p+Oim<42`CJJvMjCAk|v22a#L?D9!^( zt)uR*0Q098I`zwB!&WXJvuH7SJrfE-KCSL=6N1db1|kh&W|-=8F-prhnzKAS<;Q4P zdi%(;TL<(ft({=Bv{|Bv8Updy%0il{{mg3=zH{2yT=(Mdx}Lkgm%)Q35qZ2CaU7WY ze(@A>!7`F(!M@2CY>#?Twck1mC^IMT%8y(JSK4_5hi--0OG5Twm>IlhtLABz?Akc@ zoaUpsD!U1BU*Sgf2q?!?EA)hA z!Z1KuL_kg2iV(>GbL6%nfKQSG(;9aqds54syBn=4-YK5zb=`RsPG@<+qbw1&psL2okPy55>re+|KlR*3}xWz^mL(e&- zMZEQx?pDX#b2vdOT;Q)H*o^egl~!_!&>`hUR%&pH(b4$Sr+Ow9PnmgzuJJMYFSXR2 zGtiqS5$!-!pMPW`Xax_o&f&I{Y!}Bzysr(o0%h_qkHjC&wv;@P0TN#e?6}>Ipd%q& zm|enbkNI3lLF-oGQ>wnqRw#2A_=cRqNabP%i?xFQpMnWy&7!yct|(5tS4I4k!V>@7 z@|qv!vo&w$hQpaX!IDb9%c6dv%q1@*ajohYaUbl>YTwV6xuYTvwBg?HUPP8K(ue?4 zh#L-J99)POaL^=iYT5u-6L=Xx@N6k~AIF)p^BWzjn%1s$R&in!(dV@1?1hqd#-^@D zltJ41cbREmJW?!8V1Jb`a*oSiHJcZkB^kzkg(|Qm%zJ52RyFi?*Uh=wK21F{qlUx9 zT5Jx#E23bhP}6Rv0@-@U^|!Qo4_SX~(BZ2T^bRKFal@jJc8;2wDlKTC_?;U4E0=t?s^>Jbebfi4~$Wm1MLUz=p=Gf3Q$x?{BYZnFYZ9T}M!`pvswIFnm`!FCdXP@oCh z^hg317vB=~mp!P_=oUGP2BNuduym`E-D?;dnJaD6lIbNj$l%~^TFRY@`G*_Wz;L7b zqpZ%8nx@dCNXuy)=4RbedE&K~%hDpoL{3^xzs%U_S)v;Y+8mECshAH@U>>b>i@{Sw zepNFa8i+jMNxv`~gHBd6*5@I|)x{FN^!``L^MZMTS#$z$gq zYBO4nWe$PeXFs)ksM{&WZTl^b#`jgJVOu1Ci&J@Uv(RIUW8<& z;}2b!JX|sQUD7bDt+RysH_ztor zm<8$Pf^Di;=FTsUk=xE`yKmX}D41Nl`y&Uau>|a2+XkQDee!TgSM|D0u8JsoYYl%O zKvKXd*bItBYxEw->#CTzWoHzO9_VuZ8VK25bE%+xGKY;)e)}$k2iFHScD|XI zYCof~Y;t4rhWkkDU1P=^*W86lbq1K&mla(NoZ1^2pp~N(E}z>)^)jhwln!86`pS9+ zU!=%NhZh3D83eR2X-p%vF9bu9@S@l1(sQ1wC(<_Da^&r1VKq;R|v z)7q!#y#VwF{gnABI%d1Q-Dhrmo5Wh?RRx7S!8>4^xrFcuqbswQce+=|Q7$`{Y63q2 zW0x)epKy8WkDhH0$xWo^qs?*wr{Lekav}1kh{tsgKbcDD2|tarNM}%N4o0veG&d$I zo{cZlmT;C5vea(3RbISD%*a-CO;gVvjD8eBo4-hkH0hE`So9N|>SMwVL3BFhIEdq^ zDsaBKoPaT9L3YJyOSCjHd7}+%BsE;Wz0nwMpd(U28Xr}}Vr(U&f*=Bv;j-ige%^-* zn6ChHZf0rWsamZwpfa&*X-dej#v@U|`_`}8Q9su+cRZro8gB73f*!K~t+`9F8iIx| zLf56(BgcAuCqi`YD&hwii%eITx%6oL24Kmt{{bqV#`7Bdm5_}_C-`vhS;tX|Sq|pSxNU`FtJmXr z@3tUJ6<2|)xoH4P7+?>2^8l+r;7+{I!m!T$_kYA+lLJI}p^5-Xggya9#RZsii;>yr z=Cz!|M*HwK)H_1n{F23GJQ{I>Ls^&Ojcc6Tx) z?m`nS+M3p?)?~0C`@p5HGplJq^bw?i8orj;ZP@i_#SGp*CEzDcgAd5@-I17%0xbtU zRf$0XvyqHL_VV&*30%xW0>a@o97dD|)GAIc{&pbP;F|@dXHwhFa4Ofoyn3vZ{;y~J z4O*vUr4>5TO_{p!4nd^I$O{8lTC`p8XSTg@83-Q1&>?77>PIo6e=Srcb8WTpwMSV< zPyg+qElfQ+$yALMz=YLg+HW-5Si-@0sDRJ9wohZW?C3AT=S+~0rKi3BhlDRD*1sl+ z=QO}%1+_T1UTz(0A+}?BgHE0lmmfiexl#*-sJ2YV)tgWcp-ygb&Xqw>Oq@Q>{+OYa z$8tl$=vlVjlc9vXVe40@$eV=;b zG32pQs)*TezAgHdRvm82Gx!uCnO9ZYA zy*2d;nBB}6RU>XUSdI@a!xyc^B*qlNcPm(88k8Pf+itv6dRRHYjv@BdIP%aorJtZl z%KWkOETyp_W=s>tDpSm)*c*TP`rrR#Z%NYd(>WX~_|Qq&CY)vr%TS>uy(a-3lXUtOC1IsVu`nq!jBL zP%@iy*kFuU$qE!wY2Dx-1=MxKU?e>P?pJ@#ggo_#g4uP8=nF&w^3#1$A|jkD^nsyF z$bB4wV9u#TG(rxMyNZ`k3ZXtD-&~*nTvvT*M~>w^=3rDuN9`poG?~(d01pBCi+Y5P zdV70$P0y%c?*TO>@dbax+yZUur)lEe=c)dDiXKMM^64muP*KIoyuTXLG5M3pCV0D^ zG5UYCY!+{fx`7}v#d=7`I-YAwO)M^>AiSbZ~@HGNwQtlgc8m^;5?N| z>UOMD3HrlG47k&wGdrf;gZcQ_iA4X!b2Bvli#4iIKyXVrkPHS042*}-?hB#*)sr%L zc{ln*G{gR!G%J?V9ZdgSP*8P0x(W564FYaWo!MD>UWFba^wyy85A<&%=A@rZsXI-u~$&)K)5mgxzfbd)XQXtGN-Ls!v<~`6AAMcV&{y zOwK6u*N^$fAc(5PEtvE%zSF)RH?3s!*vSnr5f%p?3^Hn4)(&(DrOWWWd~j%gv1wTg zfR8H%X-)9pseO`dCNn!?_3D7WcrF3U&QX5irjhe)yi%`Me*e2El<`@e2FCDTkH)TA-pL zS}!Z&PX1Nzz~}rn3`-+c&Dc|>uYf#RPLYEdlbq|$4d6sb;TIlfDMWfM)JdKu?z|{D zgS!L0Gw#=Ohsu~9!f02 zrp;%=3#^fWCL&_0Zzt#61jGlNOx&67Eu%cXT>3Lg7b>${fUM!dKZ16Cwi;C?FFVT; zovBd1X-c-dI_6a4T8h*9;&;m2juHpX5ampw^4^TU#PP_g1OIF#1p+$WGL6aA>KE)m zS!r>9x*!+Kl3`1go!&HxRPKV(V`%J?tBU8{;ELF_@8oSj4|g);%6U-^xfq$BQ%i1V zg0|fNZQ!g=dv0%|SSy(3PrI`K0lwsg+6sz56FF`a&{}t8>-3IG29!OgBMZskX z?1UtzG_F!eai($jy04aM3T|s&0E#C+bJdKXP{wuEhn#R?9iBlla<3!!gdCEJv@M6I z0?Qk?!H{BV&0U{P+wJdgxZ<@4R9q65(+6pN~(* zv)R769b=En0D3T_(`PTYQFL)MILcP{VT+0)Q8l*ks+7Tx(xfC7ZhLJABH@Kfrbz^o8!((21q!uy9V z=w1H(IU}`d9OSH?u*84V;&Gzi^CziHV3zUI%)vb`nQNzlNCivJ@X*I6IS?o%FGEoH zeaB26eB-N@bq0_lF=;D+p#QsTbbCrgH1h0l3qavSF)wxp{ekvmatRf%-jkjpNLK5` z)A%#S@yx?-Sq-X$1i@!X<(pWU(wEzcKgJA{qh9&tQVXY#*&Kv-2E0NPg`@WH*&YEB zOg+>0({*cMvk9c&)nwc5OzgQ@D;zf~&&rXUkJTClFbj;Jga>A6$4xCWQCBZ0oABriz0>|G zp7&&(v7s87c>9D3*JHO$opY1{2}2}|jXuQu9uE_GVGC*rC=VP0JO-%t5dtypU3o_O zvsZDc%|(Gj^6GcI>!5nbf8q*fM(aYE_W=--j`?b*7F+&V1H7*jD7-qL<{7$*P&89q z2uqt-8KGH-o7DfRsCsdzJma@Rg!HAX#xos@&Wn$A%r0NypYTPclqJDx+Ik>*s5`-7 zjl%gGQz0+0#yWe5n0j=_cPSKB0zSEW1G|^aghPebM_3czY9(;=CYW(3W{e9C13Wdc zZ{C1BOhuE!w16(7uy#hMJFmmys?`PvMS`>eDfEn5b3CD8X1s?D_gDQGjbVuH7|m)4 z7k2$f7}%gw=_{@wV?)2WIsaPw_KisPt6Dq~a}z3cZ-ExmX-e1eZ!l0IZO z1D^j>2WqhUQye&V5mxxGGDAm|Z-NAtHR1*Z3K~XK?38|4@d#!FH4TE#6`%oiTzjFH zGxvTsTxYv~un0l!nxY6(of{EQJV?B=Z02ci1#N9DF^tPqN*Efs5RX|IS;+t>+^QQO zA=i|CM-x%jrCZ_m*`JPT7ya9sLfBi}4k2(NA=x+ge)WLh-=i-i^OE)@&D@dY@hj%s$l^{5PF&nnQZNl-bq!+9|mcESSa{L?|N?m%H?D7XpGa)ilEMWX<7cYfp(h2H{Pu zF9gi|6$|qMj2cbSatu(aT=@c3R}I#`#jiQ6=9~b;-Gm)5@E=3z_j>)amF0zs)7Ps! z(HE#xoVfp_e0Zk?!Nz?mfnv>=D*s()JZqPb?emWRyHrIgaXa@e_&e;d11WfF zl#jX|NtzINqKz^mwPVArXKYIg!J=(AJsBQix&7LD3KM}W@n3wyw9*HrR2;R6+s|s% zBLqCr=tTS0m9^q^R^62+uNed^Vt_|D<6|jgM?1gU8-vIU0`yh3mQyr+?BWLSonLOO zuy7foS%`D8C+1TYjInTw3CbNwZRHr=n~f^Nqh9;Ic8b15mf!bEj7=^6w^U24dBTg? z4@`krcN~Lr2lAjYuHI&BQgPq~Vm)E?|IlGf4?js(yCb5xF2ia^*C$(SWllm#w;xNEB#e*u~ z>!qm{<>?_krI6LK{cikL^fMwYW0rV2dfhDv?JZQtuw#a0tguBdMhIt~c#hRs)Z;D6 z6eW{y8;dzde>ro7HQ5*hy$8+Omv@rfnAYT$UnqFp9;O0#WN56!b#)JF(smW!SqINi=4EIjT+DS#n~ad z_+_`ihAy$aV{_G?8^q4CN-{N$k`_ROGJeQVaBz4NpJsM>VWfN1daLSYe4A|G5O!SW z7U?0B1G~3t$yxiaxcH|b+VlA|h0gj!)Iq+7Mha6 zGT#VN%P@(e6(`5l$F% z9nnPByH9${vqCtRaYu~U+0uy1Yq!ak%W*_@I@YjG1O+o2QrAJtOoS5fSb0|qW3wW7b+P62hDnQe z|Pb`p*D9^uSUpW2M#@=h7x)JVp7w9OsiCVeKNow@MsgoR3g z1E0;f(P_{cq!NbFIcuTg`ZDoUWJCe$3a$9_o%+jebg%_7IC@p zu=4F~O?a1ra>#dK0oM|thx&dM$kI3g?ccXRIwpU(@L&2wIS`hK3pmQ#A^$~!g&Gh9olR6= zQnk^pJEB1?T3Dpd$>kCs|8Oa5>@ZZ2qbmu}`6e3^I|}0-gTf&JEqV#%I3?Q-QInUH>jjEPO#LyrJR>mO)@Q_GZdQKig`$FC>2so) z1lBBr0A5*5n?d9CTr3)~f;Td}4&i6L=T5W)R7T~~BBej$vR-@7sdGr5E zu2;ZxE~m;mDQpMT`%j_tuP_=L z#Zyua&P6>H+}AMO{WSg(?$wwc$cy*MiWR`s)fOqk?VMyTfiT_S<7IURw>_WmKqxF$ z+NfS1nz{hOpqf?P2?<28V)+hoI&)mC8GP$rty!;bO9EWd?UB=uNw~|>EjYK*?i|>? zL>w2^gu&jCQ*86YItzkjVF;x~Y@^GV=S(`%8#A+eu?F30Fm3>#QvC;LKQwy@Q}bdp zNCRJrD84dy(Fm${pTlRT6XC#1qk>Z3T@q%+VsF43^G+ud)8&I95ztv(-dEgUVK8){ zGWwVd?{{56DI>)*w8m^ryAGE8)yKJmZDbAsZrQp5pf&>lB@OX`uOzZtqz4i*B)e@; z7V9Pvl4%Oej4zWDkoo!^h@5+CfGy<&XMEh77`_5gIcPm@WLUeu2j!k#I!KJ;DgQ0*DT@=8e**kwGIAABxbjDd|2>h zB~}V|lFn4upA}vUGK_S4myE%KM_Rfg>505pVG$C{f?xSbp9W!&+sGhc-TVmJ^7Kug zC8J;gB+lE#FP+(zPNlSRf*G_0G9%Cp)Q(LDXW9q7&#GpAq#xvxkoVh);UN+`OurxC zF5`-ZSg9k_8VH6)F%@PmhL3$=|YG z!PH+c`;ZLYcIlxSGb&NIYY`&0B)fz=V}=YR-_y8#MyK`8gOg(yc;n{rP(pDcdi(l^ z>eJ>-@*C3pHh4nKO9g1La!YtyJ!g5@>zf;N8;*WgQ8Z%UNqDi~$hN-H99sdN=XW#&SM zb)N(%TxV-LHw*+srhF>9=UQlg!*jI`jyybYh^RL$IYPfb&D*^3Qw&UYrre!AW8=-c z4#;Gh4|BIV@k^=iY%C2}*;27d)nTXd-(QfIi?OF+xtQs--lsVjB9Qu{r*2nVDql*Typv7i zH1(%PM+taQ4|&{Zb(c4%)=&7M2ogGvlUvmqu!1H? z2J^reZ9GB}u5bPQ6KF0hty5dC1c^m+At~(Oq6Ym=O3{M+r-as6EbY#=v-i+{Eiq>% zAAl{LT7SG$i=5t?9M!Y59HRKH=|fLff%w(m@_Ot~v)}w)6?EIn>)>RW<)^3}(?9-c zUk)IzuQ!X;88V06EM_8Q zgsx#n6Nhho(V!;&UWC-8>rXpiKjFH!3etiJhrAcSSzMO^KWtL7niO+=5^J_VR}$Z2 zG~cJ5dA!+|P2CopYHot`RBbKFZwa(j`M^gV7jXRM0o+&GhcsFBCP!1%^i5fVypgTY zI+67#pNV`urr}5+BmcMY7))PNI}9U~X1bL1rG>it#ssYA;Np zQve4*A)pq}Wz%55qPsG~Pu@b%mz~4$YDCtQ}PBKJ4#apDCUX3@o7f zI=)hrIyU<0vPqDZcRlWae z26UA`hw4_Wf!zBuTo}0c0VO7WNlb=4ns6qKS25EMVA6;4n+5v@_<9~cJM#u6Nd4o1 z1CIEx4TPYfUTHx+iLLAQj}$~1;Ml77W(7{Zmm-Y;R9=gub05D&lR>c)1{RCK5Y4KYW zB@DwWS4Cb9L`QjU_z=ZGtq=?xL!HZ*=kzf9=u1}%%ru~xZ&?{!n2$wM_|sy6gA-Lc zVr_*zPR}!KaumsgWIz_+(U@mLC*`<;t2G{6v%`4lKr`y#V|8Bx9oW->6TROMZ z52@=%tTH&CV)-BWJ>O}OkqORv`8mGJKd=Y@B6lS$&EcmZ;uaUj)d17iIKb1`au^e| zK|*J)E2t!7e+Ugp==(dOlNS(sjg9memOoi*_1)!KoA!faY@NzTXQ$u3ZZ9e4q~;g^ z2kuM@fRgnPqEuPcXYyzLGDTD1?_#H%TbPuB@&avXDsh%eq+J(_v45*g-IU&^- zWdu$_d&C72aR*I;#%Uv&^AV@fpvAsre)$8_vGrD}N7o$oL*Ei{a-PsQ5ohvJ*}UM- zOsJI&`l*0-m{%|KuuuE48q-x9Z?yGd%*Zy@nflAF zLr|(SI;F%)trW@X>*~2iU`Ni*nYdjKTU>+W?l3F|!MqW5B=%B}&+AF`gTI=2tm|Ccaaq zW+XwPR2^QJR;99(!H7@#ZABqx`YX|uqiYw!qbac2;cPPT!CQ;Wr5&88&}jXva}$Fhkt~AzV!r*WIzhrk^WkwY>f1BRzjGTPxqi{# zE0VL82eY>bcdS3I>QSJDeqDoGG%~^r&!=0C{!CU-bkWvBMHbA-(RCkq{eNR1A>J8Q zcL|Etm*=9@hf9twN%?fHUlD#mCA5*r8?Kn^A1!z?#!n|iN2z_+zV&(O)r8z0D%3oQ z1qK3l2xO^;F>Lp43dNe1YL;Hb7Hk1aE{&jls=yI}mF3hdVz`rRB!~TT;dWLRn;c=0 z90KZQ=!RfK^5R~OF5dE%+K4u2o{E$i6^sM`x14~?pPEN_ym2IoINgU6ArxD8p8eBm z?VsFez92y#mVdH+^^~^hi(iR@<3{Jd`CLxbt2fOqf^IlDyy}^ z08>Dn30yM&MVqF1<>H!3)Q<`g4qM|?4S2Vlbf*;r{sy?5}BjnRe*Hkdx;W;k3Wz}G12FJnYTXR};nni!i zO!5>6XA5xS%OOMi4mK1BF{RFYqRu$8iWYGU!0hCh0uf~Lj)EN+64snTZ=03VEbC>% zCMeEZ#sTCf<=R7Je;Yq>0Ko8$C$1&IK1g{dq!AvS*7TEID4H5frd?-1sh0Ce5bDI4 z-H)%p{d%wv)wd%Mu-p?x;Qdgefu?ZD2>9SZ&q!Gr|8g~vBUEag51h~P0b{q(Q_n~n z(6eub6)4kH>b%l&Exzs63F$U5#Ki##N<)AV?ug;ZGZ4r0m8}+yfk)B)>LHkE_6WlA z+^AbY2bZ1!%}UxySq?-&guDr>RujQLj6GgEuP+p(;)~uh7)F2mLa}|C)2%*=;DZw%d$q=an9s>bxj^v})@~BLZYvva*6Zaj)r&oHkH*c+6bGE^m&^S!7V%JBD=c}ji zU+GvTq#Hc;riCkit>kw8n@eJ)=Qy_^nXa-a@$rLgdg+7{+n;2`7t_|kaBvv3y^sxj zzzv`|F3J=7MG=ftVj4@;t*&Ox0+{- zzQaFHlZqK!z<=iGwM@*!jynGGns_F>(a(^9@>U`{ z>>WN_=>b)u!2A%WIN?B3l6S`aft}g594dG%#TE06R@Ojw03xMpT92kPP-#MI?ObU6 z7=(k9X}k0x2@IOEmJVlvVG#FynMaICB=&xf4)XJZ-2nCy#ou_NT>KNs6USKhl*i$X zp3B89m^8b^!G4mTR+xkUCF+P;H&FX{?Z|!+Q9Px9G_4~m-NOS71XV3^Kx_hL<1#v6 z(Fc4B^4iK6O(~2;9^?%abo0Pe(RBm}#WwB~gZQ*R3XxS)x#z5{7&=?!u??MMWKJF{ zX4v~?XX2wWs}LRGQCsTm8j*tezhO}>C+$@O&5NHs*d{qBsO{!6UknIVAMJR7I&Ly= zWct04Ht!Aw)+p`BgR8OE=+Q^RoFsK{9w&o*Jbo;92tGx+r_!+j>!sU#Dl>DfVXN@h z+Q26C%LykR%bK-I)1JM((`3C=}Mc6vK{$g4eI^W*zn|eE-Xqv|hOw zHOWRZ&KUeK^4_KjB3d77ADXzAkxq8Su4`$AzIQTTLF>}iK1A-?GAogL5$dR==kyY6 z%PXqe@LApGtq`(Uux^D8;7DDX1kWu`nwZXdxcC0vGp>j>%ZzLG5FuS6R5f2=Wav^| zwF6d4{5ODmXz4;?GWr$B05sO;{|^_vv%G6gqGuL40rp!M9+T1`!Kj|ZERtAlmt3!m zkOJMxrt-GMCq6pIt=bU^k?!9?2?_T>Q8<{C3hhI}G)(4_DlB%=z>FN@+!7s}-bsVDAai{nFWI6*a;1DvQh&A8oPI*?n#l7Eu01s88>6T0 z=aRyB{G}M_!flPaN3A*~u5$Jjfx#oXn9mRP{$dIdk-SU(@^m8(SA%=^blV?Ci!sc1 zdG+AkHDZ6HY0;RvS>mEgt6$_U0p5OMiEUIq7UHs;mc;pl_vcSu)Gi4u*~FbU$GY|> zW7jr{QN^}HbLqZX>u2l(a#1k9_P`Tj%~Jo9K)P0wh|0k=Mu_JYpdVCIrhR8r|MG$O z*-H?LdztNA13}>UxF<2d&9&c)-9aBS^9&8Lz0;7G7+$blQJdP13y#`R-*^Mc$tk4U zFIEqxnk3k?aF*Q>v}E!LsPSrsjT~c00Hf$`r5OrMWn$fgUWvKU+VJlVouA02WW2HZ zOp*zfgr5~1S*2vUhLF7A2lEkfP^B9SIN-ga_HAs}o}(jav4sWbCc?iqqxT7@Lg9d@ z894Kbs~+GbI*C)=ZpR`zb4}UCy3o3F;kT+?yYZPa$j6m*x?zUi*htcFJcx%)A2Vy; zgs(0^l{n!fmroKpiZUqADi?g0KYP1G((9X?TD}GjAtLt62F@95nWD`k+0SdN>TAIp^9@S1{ooHH9~gPuwiYv)b1|u3uA6K_VZ`v zwHV}&3Z2_ChwyhmbJek`4w#fg4f_T2T`~6{M}-7m1dhk#wJdD2 zPNjTTtllC^FY+vcpd+y(;_7Q^Ab`9wopPFGbr zwqnycV++07<*e?RTb*62SD5uD?V$Z){q7^PS2KaX-Y}^dC_CaR(}V0gbxtqeg+id3 z(cURqc(zmocspcH%jU3=Wx8=JyIstc+G*)%k~{G7bRjx&l7xb^v;)}Jz+a? zMCj14jRCfiY~f<&MKeIT21V>dZM`Ji2O%PpS;?V*YMFH?4GEhX#=%uf*I3lTh|_D~ zxGaRh<8=X+d{yEko*yZDX}zSqrwB$-&#-fY3j}uJYF##-58;$ACnk>fCd0Ni3LrPZDL{Vfr)!h6(dSrYEH^S4rQJQ|F{YvVxz6s_R(r9#dON zxp$_QO)`?S$wY^+6Nnnmb&Ae}rZg-J*B`;*E>KEAhSX@JlQBUQ| zr?&s01cck}_1YE5plCK|lFr-X%AlF%EBZ*s#G&BJhqadeAZHO1I}3=4VR?YesTdCh z*R&{ROFP98IaR8>bEj3IxAIwB5a(06%a+W%x zXa9e44{aA=nuLeINU+%B6DNr49kLjy4YuLf?_5!ZNfJZax@@!ft{~^^k^=kSikNh{ zF<7NXAe6y~S2yfAsJ4s)?*|Y{RcIYQ(2sbkuuekb7Jl54C0SE>PtCHm@vrNpisvuk z;;f&TwH?bJ#J;Pue!vI0N?6j%-FpP7Z!?~gtRgO3b@C5M(uEWyb4${*j;Y*DV|6DJ z)=&_&sD!)Ce0Vi?EPHI<9~!5lv!r=Tns2z;@wRJKwE<}`a0{R5pb9tt(uAC(h?q*1 zZ}mZVY3I-)&b>r6I7-5x4qYXWjlL09g4H@%XBaF-P&pcMX@Pg$i%lmfQS9PLpAlYl zkXugVeUw8;RyvEyL_R_~HnO6pU%bz3Q>WEO(8PLagwRR!k0D^VNt7+CIkaOtosnX4 zPo*cg?hB9mW1Hcw7Ye&?McCI>Z#w>yz$CiIrM1!<>qC%!rKH8WODa{p-_kg7Wjkd@ zoM-Ah;?g+iVJMo%S?(&9a0V>!MyeGItW`3i`?uvUaU#WeNTTuvn$`Qk7sITU#>f;L zf&9~!~CtvjzV+f_K*!h_>03z$RGDC>$qq6r_ zMs?B*ArJz)j3Dbo$Wu6A|3pvsOu0M@WX3`BM8*${>=9fXgOlhr6H z`vuDh>*h__*M!qrYt=E=L!jqw2CY)QfskFfbC1OP%(g=12dkjuNC{uz=3KI#R()>M z&dqkPU0hR>?@&Uidd!A?0C;{hEAIZ-Hv(MTt_S4=!z~n%nJB?v~1u!vP z=>~87#4JAorsdPS7$|9eOwe)JLy}i%ism#lw9rnacp-(_Q7cbf3fO*n6;Q%rhPf$u ziB+4ip6j=YFIWb;V$&Lt-V2{(&o)L+-tW^W2z*b&PpHY39LoAk-I#!|?dSES;RIT+ zRLF9{!amCScTWdYd`mxLKmFfh={cKT5)ccCE|{nr0b<0x0UwK(P8zezKHQebwW`|E z%|_{d#yV&=L@+ilRoy)tjbLT42;HE|`QO7W6MCLalq?d0Yh@h1z(?jzdbyrV!K-xL z2v-!}vbY-~jB^-(y$WynBm!GHsGgt6Toa#pvG4?)^v*AG9*Y&d%PCYrG*P06sjCuv zR(cu4<~V7puu+AU(jG<_OC zdPOErDg76iMl?V%5G9mdHgbXXM)re2g^%Hn!e?8425@b zv7D7g+Kgk60A)m`Wl-u7JBqS>)G5otx#7~1Q%w-6+eqpLB+!6GMs)t#!x}1H^#&=r zIxG;AXOQjqp$<^#--8L3Ro^FS?wS!b(LP%_H+`Nx^Llc*69|2@hZ@ge8SKGMhau7i zOFq?BB<6waU&x3rYUq5+c4jl7>kR)dpG#i7{aWa(ye8U}c@u3$Mn3R(bI-^4>5eY? zBU9P3mmOuWcTd28@Nf$;=jH0b@pTu}(}Dg8w#--BjTzdfv&2Bi#7)#+G_I}Rgol@^ zkhw{RcW*qMP%@Vn}OY-dL}EQ@yDvV}9XiH40t^ zGU3bPNMFq=dSp(kkh~fU;>2KUhy&Io{$-Zf7#Up%EwL54&)5bKx~RF;)Y{FpW0M(H2>l&fxXvuYGk@=v?^C<6*oN2#gaDt=>O~;%8_GdFs$H1+YfLze=LLLD~c#P=ndfvif*P~_=ScjUQ}zZf{5 zQ`WiFga^$PfLRqfyCOX)AZmVR>XcB6jeCMFzZJbp0S5ifl!QT$3Cn$mWIg9f4c3H7Pk_IKY-XTG70 zj~~&ou(Mnx@M!HDs%%F2fvsr}CiN#~bT*Hpd#>>PW`_{j>~XoWN83`xShS>>HnhUC{?7=EkVN6%$XF8qVC480p!HQRd(w(E;S#y=jLEaZ8t0?G-p_4wF$l zH~&f?c;Vb3@un&gney2F$eo{Y zTx!15ZLqOfr*0s`$@0C?OJo!qBj7=S4)^!hZj|RmGg%`;M7{FsOnNvbERc5-QhK5n z&h}@_z4tAlwG%7&6aGI;kxBKRo{VLr9atI-yx@*n0lt=b6#Le6`EuRNUK7NT6Em9r zI^b|NC;{XlOT;y^RjqL&-@)N&u*R!>H_*OT_!>}}6XHf`LX&_eGA(si}gMsHp>e=?|jlnhGkU+@s z1(k)u8V=^}`-799XH5qdf8`KLK=)wjT0n{TgAae(H22+arWlA@xW=S&ggt973Zf#f zd^Mw6a*#ckH$*G$FpZ<4;{<$wFzcg4!xR0$uF-GLDT-qtmxQj&pI9-eoJH5(poC6G z&w=Eaq4YoU-c*PYyYP3L3-Ghn5wF~bGu0a8{W-C|$T+wlM=cKjZ@MM?TTuO!xuDQG z_bPYtLo&HmFfAz8oR?-q7z&Aw(iLSzK6k^&XQ#v4hyX1>(!YL6DHDpRkOo<97bc-6 zhdGW4@-<@Q%^IFwELB|Dd@%%e6*|nifVJdWis+y`#E}Oh?6PdXx)i<%sTEejM%8(? zWR8$EU$HQW{gS=Wu(n5p0v1T^sn|!lgf%aAuYgLUjASH%nfDWug-NP=E1_)UaFe$1 z3p3)fua>*l++q%g@Rrex9?1~1Ngl4BUDNiv6y7Ze<%K-g*5IpL`Q1pMf#d>S61}1; zmx8vYUccGeL%&hes%d`ajNKly*jv!w<}92m{9TdyQy0PU11h)UwsnyKqF~(uKs~qVm(7l})yFg~W+*zn z@A}e2fdTjgf6)ziPYBZw4@FGAaBlyB4RXzE5s@hdZLdiq*uV^hYh+5%!#L0a*>6FX zv)dEFq6P^_!WPjYvDSz}`8w&&pOS#aM1rxAPUm=TZ%BB)=(Fs=zUfvIIXGl}vH=3ftK=_a%m)T+n%6 zP$0mMv&RxT`g(Ksuw}jN`d0=4E8&3Pd(2&8q~LPuOwL|r&>}oakQ0#qyt{pWzQO{9 z?ln+2`ED|s{2f28#=lXRf+g2lZiRLJcZ?0CP!Vb?VI`F*g0&j(dz$qh%2*W%1o?fm zQZ9Cjp1kSG=9D!vGvE-(09uE5UM@UU6c?Vl7wI?1&l_Va$#6-GGoF?e&TXUHj7CyH z#Rt#e)nMCASZ4N7!%6i#L5}M6(gj7&6|reMl6@+oFoB$$8P$vuyuuG|LYb*9L?ql^ zvDkA3k&qJzY`JX*7!*pj2@-c*_L4SYAiEr;b%y%1W?@u$n0p$`Oul$W){qtuK6LCq zPHs%yj(#qbU@PqIM+JkV9s*cX|Fqi%HBZ2^Zaw=DzE||3$b@Q*Q+*zrj}zT9FF~$l zidqZ}ZssL@u{Z=%a%t%S3NnIN$J@I=X$*1~d#p_&;W?rBVO^a%gPJ6IcRV&@Z0%4R z_~zPVn>q&I(Ay`HyLKH&nb0c$*TyZ7bjB?^4=H8?Z$e$^4)>YM-blJ9kf}tuoJYmy z4`EMcUnZ2<+H2B{n>w4-Vxh`4^?TR2N4vuIjeQb`LZu5NjZ!3!Y7oncd4ADn`!R0L z?SzoXdKrl~7}jc7AqTnQ2#z)BRf%gm@?n%`@RslsS4?MeKRmP^YW~V&@4(@_@wIHL zZh0xTBaXid`Vv8vA~RfIk(1%YErSd(&s_QuqBxqqOZ)h-h*|P3{k%mdXt~O64jn< zr6KK>9_SK5A82MbJcMuAOaj&X)4ob3Vcj`+G!R;|Q0=Zvd{4pieWvDONK@Mg4%xD) zd|Kjj{6IpC`#qxp4NW`HX5hJo^-etnP#Tj3KciXHe2P6~z3wU<8I4UyUYKH@T*6*B z#1CiDW@2U05`kv%1I3G@0EM84bndXP*mEJ$BNH?HI!FVa5LkdTP!BQx(IeQ8kpvi| z0+fQKU1B4U|JxG?tT1)9594HqQYAZ#mSYzxJTe~YPtje_6=!= zBvS}7C^zU?rz*0gzE1NYv$5J=lJ5FTWlsyuVDemwaA3htU?hsGNf$zK?T~p^*Ar2Y ztP&1?J~hBBl)BkICj;8OE(M+F+K{0096)1-&3GChhnsD+<@DH25D|iQ+zIal&0b*pOP`?bt2cArLVXv~DYEIO z?!|3k#kB+<aCqzT{Q{-sfM8wiUVTLOz2Q<{LU z?|b|IovdzFQC89>eD@~}=~Vd*5oIXeddRQ7C0Kk0hZaYP)Wo)93zK(i1K?bZ>@{4I zhX*AZ=&(|cJCN1hHZp!_(~=0ze;W?gR~~ER^csyDc%3zQoJ_iQO}7pMfG<#{SLH5{ zYp;ccpJzg8aKQQzo#??;Ft{PosRNPoXvn-AyUTmSt(rhJ#+6$|@>K0%$gZ1RhOVB$ zrI27ZI7#m{P`eSNQY2SS3zNwS|j47U~`U<6zrt*1VJXw2dz zn7Zbs)CE?W&Ra*1AWBpJB!3p{b&sbab;eD>+431uJmP&bA2MR&yUb&`7LHo<3u&#| zi(KJSXCtwH3=wGS6EY2_(`>r zw6StYhxhJFE*DTmrg2OYNel5zPn6W^j9e$-Y&ZcY(!8!tLQ97vwJW(=$~5sVKb&qr zyd+K026LxddHQF^5Ao=f+cQM?>g(BAWIrh~xk@#njm}Fl&P@zm9;VB@6*sMUVrZJZ z3JK7iz)&o{GW~YYv**`$eP+YiL{=hHZdr){C>cDcm?Zz;di?qps@$3CR;`c=I+ctM zB;s|Fi#OmZmwH^IfL!m;;%N8l5`7_R9~nIz!%2dXi~UWFcRX+vBXnG)=y31tZ8)-g z#rc9+K(7+x3V|n8$-s0q?@4;bpMSnk!pgK;6eT-UT#c^*U(IKvN6m=STFgo$s*|Q4 zGG`rV>ApA%e|&`ExscRYaQseC#A>7+xF;jpf9>#ugL6H?nyHazKxG?#!z{;f$R$1< zm1OnQ2G#zf$VjJkcbSFhu~K;_R#TdyLsrX1AophPvx=-eLnw>9Zw$j++Cn(jJMjfhi8cgn}D7DD(cmsWgcGkLcW{0Ivs%)!|=$a?( zcyF;jchk43TRe7Mk#F`bZLksD*hfpmQabV{|= zPssjI=l6$0US+9QDUavQH=NG6#;Ut>Xb_+?bW&&ZjY{~+!s4+zQPC3P(m?FU-?O95 z15x+e-q3`S+etf;r>3ONHSCuLVa3QsP=w14cgx=w?$)#a^)N$cxN;&S4C3N^*FJ}P zfoZRGPbU>`cReTJ**g1566i#I+qeRe^Ay&R|lP@MZ zaNYZcwHA^M=x$lHutHz70p(+Ax;2v-E&X|$j5Y<<0uua5r&1tP+hvC+Hb^azpsq+$ zD6ZHe;8QJR8{l>O4XD<{*TM8F34e|nAIVzFr4zHZiui4WR;H~S=wBs%r(W{DXA2d~ zrw1^DgKICn`*I@mQ}FwOk=uv-1?+GyL)EULaSL)SiMrMKP@`?&d}vxq{4J^aei)6i z=l6>OC7Y!60YgB&RkW5ac7zkRMF|8AlDfz#qX3P}3_!uz(kpVVe>h%?Xq0I|1d#wA zzUcBg23UJWvQ+T=(=);CO7RcG9)Oq1YcZ~5yw)yYEV3>*Xa(XDt1ed7%7hRl4^ZeAcFcQ{{S zAx4rZTXR&HoKyvdd)rn@LxR&8TrBbE5%bM$`x4$eWU53&U+Ba!Oj;&UOHBp(Hsjnw z8DwVhW2=Gf22;cp!?V0$*ht1?k}&nU)pO_y(E|XeevAB&m=!fBCUML^87|5Wc8e!4 z;Ka1Kd^CLTp&jRAoNQP;UF?>o?~dh>>aVgy{Aqr)2Fk}r!5$5W=@qV4ZwJ004J*(* zb$ukX+Y&X@Gf$ICpNYxjvb)NxF{B}S23^okL3BUHVNyJ|s@X?(@QTPZ{g_|G{$%fE zi>0kGWDbgy$qY26)bzRJs5kyBDpb0N6rXG$_6Nr&LbBRgrMoK=X}8;W8}QZ$EQS=b z(CKKUMOykNdd@hVGku}H)8EQ65<(gu+S7nlbJI!alTYuMq%r``bfdbxYE*NN5)PwO z32#XvN`ng%no8q8HQkJl_Lr$Sn?iIR)8e$?Wd?Zr|4F@#`qf(;zOD_WOIq+Oc)TP_ zWtJ2E+Qw~NGV|_+q9ntjU^&tq{t&?u%SD=3%*(F`1gGc>+kGj@nw$MlaMrq; ze!C7di8a4kD?Dlt5`DyJwR0p>u;Q5|kDc__3M9eO$BKCLDy+ zuK2ObxHU?722x?nS|GoC5E)Lmy*g4G`Jik_!lDW*@Se~1I~#a)XF8rYg|EoWj}ZPI z28rX?@^=KajdivNx=CcE);DT9c-2YPF|ojLzUygD;=JHx9Hot|_~utHVA2`$a62Y_ zUYy%T`Y_w|$AC2UVfYA<`?ejS3AU8~1B+(L4&v$q6$hIBHJ#6f`7$cSx~#X z@mP&cm22=Z*C4VmfEU+InV;uhaenebO4hcISh`%v^Y!w54+8&{?|u0Bw^sBB>-mmi zjBgDcISE9(D=q@m_^PofO|YpE4I_42pzon;R6w#r+U{u8Pb$#I2Bd^Tr&+EQGt%^g>&VB9v!kdU4cmBgYrFl z=D|%kM+snrdJ>Ujv;2Q(-!zj1?27dJ4l7Rp1Z_)%KiR`n|CHj|p$v(k;fa%Y_4@2W zzM}lw`K%(GbIvFDIWPMD`gEmm5qHmgZxuPP{M4V(na4Q|p-&{vu_SHVX+Rg2kAOxy z!un@TOv1UoEGHn})D=EP>g2V{Y&*)X?F^e6%kCoso@BRXu@3e=3qApwOD^&n*VQc1 zx+mEkf}*xLgy)QA?(bAv#IFN}%tDRm`va6;2*BhYHi=ODe!f) zI1%q!CZcVMUJMBOh2u(C-|7gs&nkr^eG_$__)u0sl3iuYxg8S`#I!D$L3Zfzl*6oi zX9l-iux&x#9m!7c%fuxpm3~`5+P))QX!v9Z{GNA8pAak)_{b=TulcOfsaqILiEOR` zjxi-FnYr>;$iKArF!=tGD~bW&TU=1fIvmF=kKuQZmZ29+NXMZx-0J%?;SdYM0p^{}?yIW-~b~O>lm2~+6cXDKd z_K?j`^Cxkk9Vf`i+r%Tf_>6Q;R}$xR_GqE&|H$q<{{ z4i|P0wly^JtZdI|pUmIxI)qZk&2B;^ylPGLMe2C$y)OK=xw>JvaeBT^g6pVRk8fWt zMZmrCNXAy^J9?l2QI^Zle+9E$6xaK<_u32DbMnENlJDCt1S1{ z#VJc)BJ2U(RaaE83APxh?v+aZ<9bwlr#I>#I0MU9U`N=P<(=*8T$(xs$WZlZt_PPfI zBs~}AU29A|Zhx#eRw*_Xn7fv$Sa1$5e-o0wmSCEbCltf?T%Er|y_v0vbm@=PGO*lf zbYvIRLF5={11U)&dT+p8rxdU=#VW?tq4KQNYwTY<6PNKS&8n2^53A)whZP}(TFokM z;Uvk%b{1*_K4yJRx0IbrtUef{F(Y3~@(5MvDrhWgdNq^zuBF=zH;WicMU}0m zfZV~B%y+=T<$U>DC{z}oayA_Jb+iSHYiYu5<{4Yc{Or502rZ|Bv`gjoQ&?ITS45<$ ze{fO_6fc6VQ%Y@{ojuKs1i3|zq+lJXr>hdNHemd(3!oREHrn4Y}Ta_ zHLkc=WC;}8_37x9a7|PDGU-ao`V&u*-!^>ABTKup*Ag?SL+Tpd_wo&2ictSz#b-r> z(h0zj%>nl=l1C+SpyVAxV7vMy@^>v6oKZ~?SA3s4zL!SoWKt(^m_R>0&Z%eMG_pgX zQc|FLFP}7(X3~%mf?}~!tj5**Dufo34c=P5WKs|28*9;rq07*6DvcBDu(e732YP%V zjXC8k_oJPCM`}1t?WZUYqhzgdW$u(egr+=gowVVjX8@SMS-~$av(y?hGN*HiR?>_ zFm~*RF;Qo))76Qvg^+QCSIN2;VF%mjQI~K0CAI^kXn^<(TH&+n2s26l=h1=}xDqZ> zhqGvKucSnFVrGQ>=CI0Gz|Gl^-S}7m5pU!)Z4nllx9@bCAyzCQB?#*ww_lWJ*`E-= ziC;N(rlFT!WQ%lRvId%oY$^Q*Uco6vj-nI(G6#E1m8J5s z(%5H-i?z)(D@x6;OrL6_g?($zXZZqoG_MUkP(>I{Yw`KfW`!t?jF4%ju1`wv>#rfM z5P0B1y$>nsHWz0@kHczfuy&R-ZRVuC6ESX8!b@{Cw!FRn_A|npcKI7?om%Hs7};Wv<+wyHr04aGb#ZKxURdu-q{s5TlrHxjNP^@X z<9$?|Jwu(Xbrk<+%)DWp*=6K=db5ziKB@}#{{oS5lc0$*!dfz=%5efnWA4zUca4!2h&3vj?k+*r-<=??mkwsMK2 zYW&zDr%ZWq(qca?<%K>>|09{Rv0s9P49UP>#@}^nxVT$E<>dnmtB(ZNPq0AxRfYmH z;#-hs5B>>y=dS@(P6@Vg7!fF;CZi3$S=yu&9rMeHCH(KBrQ5cz7i`^0oy7J8^mH@V z7YN$9L5z=l3ls<*Tm16i=kM|@lUlX4O}cyAJ4@4iDSG3YiK_qW+16W_*W4q?YM_`% z9_&i+qxRMqHMqrZ`y7pZr26KRTPdB|SJwGU8K;nr(NJG%iq zKXUhJ6F&tk@ihLDA2;UH$tJ(p?#WC{P78<2xq#pRnOmFq4p}aH=RwN0v@TMtLb&VY z8Iy62MjyUEgw5idFfWgj{lRPWkH>|~#V~;WcF;w}zOr5%)qdGij#6Q5r$o9`U%RbZ z{d3^3`_g%*Jm9%VtjTJb+MJeRBL%JBrt#y`$%f2~`Q#663obE`f4A>3hw#S34?~pj z%GaaF9C@EU&~sS8F+!pJJv9I|{-$AwYXDM)ag3-zEhB@r-jU5lgU#>qronRxDkk^C z!(`{(Ya_LMV!0uuk_(Mi@SxVg;ZUl3R9Qry=Aboi)WcQ!WdKi55IDDw!UalyG*aRa z!M}AzFN#=6C50YNAGm=&IeH0Xu>tHDq#=B0vZ=NR8T+CJDF9UWord(s6k=*4&~4C- zN)0n^BCxb!K}>C`FcLuS0_piB(Igt?H%}gpLpGG*}Z8@9)h*Lh*Fn6@;1f2Ph+d z1Y7Om$l)o|S5v_6jop#Ms@VPjovzC`?sTM68O7QrGz}X(@aT+iWV^ ziEJzE^36)U=n98cG|QGMbU8peV>XV8=_G%iJBmQGP@}yUSflrj+pAB%ey>-SR@E)| zm>^Vc68djyFo6~kk4Z-vCWW-W#GK^$G$T3qdXYwTlX%h4%>);$@xKBd7a+m$lLToI z=(&8D>A>E=qnj4&A?wmXAwJRn8)vn-X!sc6YfM2p|8lX&<_u-&`t7l96ROL*IZV_IPggP?|5-eI!Y3FS((D`gV|rP z%K#LeWdxw}&_Ga5X9_#BqgyeRf~?*ZGW>GJ3;zAVd6eOuvS7RTh`3(FA`(V?@qiGO zMDv(VW#k>pP8A0vfs8bTu{AjLT`>OkL*_2+mu1+~rZnCykN2}@jc-4ORUel#?!>`L z`I*^j&-Igfg#y>PVCeQRYg_2B?4JJi{hB8ZWCzcRE4oORjxH}kA3?A} zQh^}Pt~n#~Z!P!*JW`hpsV^Cnp+yYm2ys=w$uBEBKVsa#b*kxrX_c63dsn1A6mubh zgdm+>myRZfOoHlS)3ZXmVj$cJz#>|jLRZ10ZypQCb!k$5rrxJc|HMSK;suy~s7ixb zHtI`S4O&D3Yi);57(OhzYfI{~Vdc%5)Za6>z?EC`|HMy1+f9^v@u+Rx#?{*mb0HkA z3+`lk4UyEMc}wnBWgOVj@}G1#+n66HP%YvV`x*wg9_rC9+CDUc$I}WVk_;h(K`h+q z5N|@^HcCel3sP^L!5^e$?%MOH6-xO6PDhY+u|51Hi6@fkUSsif0Z`+( z13R`ZU+w#HK4t2)fZD9_eA{(jA;I2i<|Hki;)RXQk}!vvDl$aUV{v%@8i3fepFqK- z=XY$_T}sSnff)Mt_KRH(3`|x@C3%}NQXdN(d~JDyLM`#d_1ZjJzOZ%Wal0>^ zFy3HtC^fc9vuKh){Tbp{OX{MOu(f&!(Vl0Y{~N<-(`MD3AMi_6n2K9c*x^op)hJbm+1 z34M1%%4b>&$$qD~Z|1fY)@PH1c)OZJtS|zXILOnkBt@>uX$m$EXpp*>t2cY$78b;r5AZwPfY%Nfaog+3=pK z2QU6R@Q5QF_hVS=Umcvi`9~pDm9jKY(=GVRPU?k)anetCq3k-A7RpuJpi(_D-EX(2 zDW827T4ceCYU@O=8C#SC4}tcnEh8sblhKJ5qn6>lrtrv~Hw&?-V2a6REuiz0z273K z9stUBw^}Khertw}w&bfp)zpWyzr#KEXQEUQihI_xW?!y3@hd@lxHMH2@HF>Xu^iIXvWvCqf2}KU*IVvfcC(?-VvR13B zDj2UP_Ns?s2gGfR8WkyG3>d9Fc*^6AJ&8*y>s7M_Rje#xfzB(SGyJ}K$zyAE5kayG zyp3Ej;!Co2I`mgH>x3_~`4?-iOOY3ktkw65pUC%A{Nvb2LbwX&eL(Jm|w{ zQES=Z{7V=HC#7NFA{>!D6g6$jdwl_&r8hC@;m|3Qy2P0KzS(tpvO@Fz!rI1a_2mZr zQAJ9q>H8IIyW`c5%H<{$RtzTUF~fPl(aejOGZ%t-A_ocaXt!TS)oD03j(9S{l#tZeLCxI_o@-pwSzK;aI-2MQx_(1BrH6~F5Zioktbv)zpM zxS0^=BoD9KaJs%a>U`J80;R>_w4x`prNFj0I+=@4|t ztPc@`j8E8wsuE-$e!g80z-JZBJrPVukljNH!v2v&WuaFl?KE3rvy#7mtJf5Fa+FNQ zg?a*JubbuIh8RNq-{ZtUkII^beXwkB<1WZ{!RZp-XUPrEO3rV%{wbyml_E3v{?1R` zpQw$60}vA(Hq;R*Y?Kpw9$YiO;%*dhqx8pO3=_ESN(6HV@vr9Bx;CiLYYQ_M#a@7t zay=9H_e1?NBunGY<2%%>?feUF`N$E0Voh_<+<3QTtbWK_oLtmas=%U<^oGgR*}7xeQrF`-a~aQhTSKhu=;mV6Vg1048H zo{fPC{^LSPQw+Np8lxN~LhXYJ>S1N%cB`Kq@85jiQa*W0uoNvaGyenL#^*6nc9a{s z?uBCLZyu$5>YH^Llhx~UryRHUYpr{b@!1)|#a2Z1b#PK!SIGNBW($D4iT>5kw`1=O zII-!+mGEP^mKB_1O+iFMG5<$gv@XQW0zkv}4CgXrqZSLb=!erA$qo9!SXNz0;zVmt ziQ*XdpJFqly#`y@c+fe5V1dd}m0FO0OW%H_y-(hSW-7&XBEskTWnkeajGLMuHQMd5 zs%i;3aq*)L`1g&{Lv|P26o%P3rc2Ym2}@co&%@9!OV(==9Nr>tul^jiwxN|%D@HGZ z0R9)LQ%+dWOaW3@4=xCZsK>jhq7YE6RSH_LGeKHR1>&Mqnba{5B-}R;UC8SSYR9FE zA8^j-I+Y=iB*P^9%`JMrB`A#zith9$!cb3O!~C7D3+1UM#%$jwetY-P|+~ z%x{6tf-tMwHd+&PVoXr*+M-c00w-eJp9da%cmb^0$T-x~3#oDsTO}5?YZ59Dd@%$t zAPK4ah)UijeQ(77A=%CImJj_4ecj23&t{Ak=mh<4kovpW_=zCYrF0X?+-7U?}lhL8Fv&-Hadqa+NSH4G%fE;h%?eMR?$Rvmg#FWm0d|< zv4m6ka$Uk~KmxCIYjKc{5&i*7#_$5Tqr5vmeT=@rnJ@~(^v)9TMal=(2u5GwXVWuf zt9{0@`C6v!18sA(&=)%j3&XsoL%M!+_F+pK^`o`UC}s_iZlo^Y!+fnSbp1^UyFAb}(uc$$dr4goOds+U_GgdzMl$!!r?2U7XqDHC3%T3#yvx(_=b{a&{{-B5^62Dz+lFWp|# zE_AYpgnUH=>V3|gj9i|dpUUY{x_j4zmZFi3**;d0Zm6$4fAG&p4}v>ob>sVPfMy2O z*83NNTL@9#XT_d(HD*T6N9<+-BeM~7ORpT2P;{HDhc;2UADNsR*7pXK(OctF>&bmy zm@y#yV1rkel?z6`+fYkHAodeD{liD9o8Yc=In?sdU4Kc(m*Z2`9kKjaF4-Cs$+VL~ zuLRL-WUCg5Ht~aUn5M5X5C7HBBjx`Xk+!|wE&$(uc&eZR_483ULRh?WLS|S>NG^5M zDQcfsb?$52GRmiD>|1PRZEuMX(Ra&=QHYiiVK%;tV^T>vwE`kpZ3Tg@d=eh8B}5XU zfuG;jD~>9FQ4xG-~bzl zGVFu0eKJ_+NJuP(_j9UpNYl0#RqA2p?Z9u+)CMw|hEZTR;BXt}KKTy&{WaCsmraqw zbY=KA#x;{?zPVC?S{iQW9%hwNb%FrK1iblC_wv z5Var_ff9$#oUWyaQM(6Ds4v(0ty2l;>F75ESo>c@BjHXxPk+8oJK`*qY3+Uv5r~y7 zyz=1F-vSw|3jonvQGlLx-Klzw6aV+u;5Q+D3o@UY1$l7C_Pd>(ik&m&l0#w)RytI! zU@1c4Gf;|6P+Bq&Tt_wsU>44?>gUtW$po6rC4uG%1#|U{Fi@j(Tz!^m_sWL8_2pitFzm#Kjkb7GPc z;3l!@l3A7v*#0C&;;Ha`SLrMQmn9>@`n#c)#1rdh)^gYN)>HE|0IP#y(ieBQoMWTi|o zpRh4tO#6CgfTP~)Vq1mGX3fi;Tc(kP{%}uqhQ7&$Z?}qI42BIKRwyda6l+@>-me!E zwcW|Q+V-q7l5^mVOUvXl!8%=F0uGeTSS%=pdTw9lB|!cAaQDex9 z3)Z`w5FcrzA!bwl1KK2N$siT3548KTDg!#v{16VbJrs4^o;39B3DHnz(Kn;RcQ?&y zlbM6X^}GUb{JYn4;C+p<=1i%5pXU zHi@Jqz=-xNZP4la_BxyXeQuMN{Wor?5=zEbRb&Uzf>Y#+EJUU0{3m@kufn2tS??22 z5UNrJ$W_E*CEg>s8O_w;!Y;r?vjzFdzRwh9#JCcf*egJ7EC6FM^xQuQsLMC{2bc0# z&?0+#(zD?%=2P3$*9)s$Tqdt$cLIOcuLYLJOOD4Vw|(n;&Gbe|d3`UYYS9oHB4lzA#`>v`Xkh*8;>;bSt|%QypDZy))feK#Pl zYse{(+rVVJOHxgbG8P0}*oWA3Wd<-k1`0UF-UQQYqI6hGTeG=BKC*Y;;>YyLf7Jr% zEUbF%lJ`V$APX+Qlm|dlwPe_~2Ox&%WAKqNo!KLsE3Yu1?OsP6qZUs|&#Pa-WKyQy z+5f6=N?7peM1HNjG-Lp`q(>TLMnC@^0lPr=*=W=8VCZZ*bQ-#faj`zVZxF7+AM=WB z+O|nw38!wvK3`PV6dk?zCkI9HlTlQwqC;a~!fD>?SW-_l`nJiOQCFL8L*Y3Je&H4juCnNBTfj3>K>J_5FPDl zbap(P#?;{CJekYH!Fn6m{b^`G69k8)!X4tYQJu#qK!??>E>9Rpvi_F)sW8+g1HPd( z!FxXCW3#srVm=JC%8+01XmyjoT5TcjB7dXYA4SyYyd^ zSvFm$kRZh+g@vQ-|K|7K-=s3!9nqns;`s85|9;u$nR$88;r{NM@aHQDz@485yl^K9 zcOPN2KKQ2{Rd@gl1p_r8{qOIqwXXce{a!HO6skhIN8AR5@v(zP9Qgesb*U`0v_vmh zxN*)Fs)0>m1&=D;W+?KxOjax+KIYjLO@UO+Eui<&P>)+^yslaI1SI>h$_6t*%h`E6 zW~t*EE_Fc~nHI8~{U&x?QPiK@alT-MlX|fG^R1(c#_A>^f>y4bBwJ2@#BZl^@7$>V zf?C4CpWqS^YmkG_YAE%-&?*z%!G7UjH~^GyPi~!n+N?8WI!(xr@U+E-@%xxi!3dOS z25q%zt2b5C%8zYKFnG8RoXH8)r;D!nCL>;?dQ9jFe!A!7(7I_R1K(lq1VJ23-~h-2 z(jR5_m;$MZP*Wuk7uBu?MLFE!-?LV!9w#^%8ImT9m#BsL0BhY%v8$>d6dL1{s5yk@Srgnj8ku<3$AH`z#6$tfr( zmxT&`HRu-?fEWMI7LaU)>h|!H2Zyv4? z1Q^6;MxQYvFtZh(M9GI>>x*&9klI`BrLQx8yi#Iyqc`JB8>T z1f%93s)US%2zvk+bj>8~z!+Tq`8!yXt;ino094nKXD4N@C8BPDrH$-%*>i1$F1%(LTC~XPUBCvB?ag7uF>SEWz1N= zi84iB2ff`aIm-|ZG8U#V&9YM2wjGex=yIT!c(cVitP{uERCGm@eiM3UvO7;Q+C!F@ zQ4NAsy?uPLd0EBGTlJuYj`v+67$1BK?ZC=f zf+2cXR`bji7YM=P%8p);{GXWPjH1iUHWEepDw>Wm<#aM>T75gNnzfM`@tOTfS;iZACHwt3v9bIB9mKUn-HBcmo@i6|Y+A|Q#J55pV~QG!mE>*CuF^5D*-c#JeWBs;cw&yVRExQ#6E|$sms|20{Em#VO*^=RcbE4oNw(u2;e*91@>S2IXHE z_>TAK>g5^Ayj1%Mdq1~kRwJYbypb9@>zpGLAVy(f6BLxY{`c}5i(CCYYC1>U6W!!; zqZEjP^jd2`a?S#b+W?OlA0CU46WBsIEO0);pmeQFl06Id4dXdOC{{TSePd>WjaFKn zOd-)u(1s|>WdME)qsP3KoVyj*&NtaeGKT>wDQ)v;vTAKK{p1Yv!xKsw&bU#>B(v=M z*d(HS^e&Fn13^g!>;27N$#&P!+u&jSo|jp zPaWl~Xtug4?rlkwQFeeY%{?C=R+Mrqo61~gM4@j`dn5|8gm-Z$%>esrcD&YM(tGAZ zEx~02L}UkX@*yt~t`uj&eV2I@MZR2{gz4Xp!$R~Gdlga?Ke+-g7^)G8#e8jQbjhJS zkC*<^mB1=(AwmTYXaMBtbWc^BT|m$mxzwVjoVfJxJt`s+ zzLO&A-;<{G#KleHi1R7KQtw72NW=oE%xFf+q^)B{!T z^xS4X<&D0_iprxExxr#LV$G_z+0Qi zDv5X?dCjIz{9Qy`R(wu)G8rzKOz7wMq7*xeO{Tp|XJI){e%a$+9{YC4hsN7&S2|Fr zUjp4OG9YdmxKyl^w+C(MYVp4|F$e!l}{IB``bmh7T?`f!WUc+i% zx=uG)aL!AQI+U!g@bWeO5~U**SK2PfcP69nPq98=#ZR;hh#0`x0s`qW&So$1LlKBq z`vf3MlcUgdf{XTcMEp}di@Y7?1XV~3Lu|u4s6ftD#K&j}`t?{J~C2M zpee8Bd2tPeTcc^4#jfzqHja+KfofY5iRb+2QL8-9vY)ViegVA~b-eyWkSf3)Mtm4x z*eEGbrkOA)=U&;zWfM}=nOWE9qy z(%zI1(lSUL-b;>w%koN5PwL=ULk89UA5C;oIfb;U9$dW1lU^TLB#id}FNOAoZHGW!RbJ`VflC#c!NDE(g9GEh4px zg9J5(rB*6UcZ6_ujwb)W-q*Kjd#&;3dn+oIlGRZ{O~tT>dmLn%$oCbchgjK<3x4Fd z6Mso0a^W2>v1(s0BES;XUCGy;(SH)ZvQKj-a^}%8lxYc%y`F#Y`$TN)BX4Tbs}!{x z*a?1))!YP3jiOPmCN=4>hBZ-*GtOa?wS@7kT;$A060K0Cy0+c{S<+I7#qifmhwJpl zVNgx0WW8)yAE5B*+C=p^n(uZ(_FI*pJ7PuEAUANtfxsU>d+N znd`vj`4wqY`}Ztb-%E3B56TUq%T|9+Bdxygph*#`*0&CJg;!XK2Zd5I%|&Ieq2bt5+k#d*dqjCu;3%wBcLq*9U-8S z_*f*}-qxAeBd&E(K*Gd5vc{uQU>t&B(!ePI5#m4Bhll!Wjbfr)q>o$wmC5sW%1im@ zkhJd}%%jC9aDlWWIMwsAay=R8n&4QARU*&bS6l+Ixe~LKh##I2%XcI@(?K83oY(6_ zw7C#FJnsf~=~EKq0^Imoh*@jWr@r)!PGFSN!qA!4Y~8iF?C#DBoW8`$tL3GJcsQzR zVcRkmwqlx6%Imo3C%N=U9Ip2v>--QSc^5W8>25>Wmwm$)oXcxgq$y4PW!1XWI&dPQ zN*sM5#$_MR)8+;>o(tDemz?tX(3W6g|=OT0T zrCn&YR9`eycQ|e=M-;!(&Kwf@1YVme1v2c&si?O`9Ih4za-V}`o+84lN-9mtkSNc( zuRb{7Jb;5@)XFf%xkOrIm@UMX+crMaIFqzMA&3B>lf3yB&nX2-WB>Zm2tk$bD8o4a zZ^}55Zi7#A7RT;=`Lle}>Y6M|NiyLl)gPxE+6jCLM}~L+EkM%0{B?c-@QeJJaK1h8 z0^-=5sGV#$K~P1)kSJy6Nr`|@-@duk3HcnHckwnCMq?|Jpfn~2yvKVybG1D(gJA#d zT0z$it2phydlxkv9Vew@$zHZWbQ}zL;1?ekHr+u67Db_b4e#zbb|7KfMbB2<+w+yq zh=py0e>mfu$D*ggPtL^!;(`7bX?!AW+U>0|eu{)VQk0a4JZ8Tcd-PE>3pEbcLJ}^igKfNlw+Z8qnt4ZCbZhA3zCI)f1@wVn1D4!HND^u3z5h3x`Td2jn z@wSpVu@S4i^~lORXYhwkD<5egde@oQ38uGL;{>Mv-@U!yj!M)K`e){NnlN-nb0;Nn z@h&wf9GIK(eqgw-G(l&EMdBqVZBh`1cm33<;Ta{iH5-qYvE*sOhZu@V86XIA^!$NQ zAOOtQzd+;9SAKwJq8SAS#_rBS!_2`WqWS-M`i?DOkcT&-eE^Y0MmLI?@$Fwt@I_xG zJn)KeN;zJdju&D#^;D8oWJy%kwYKOL@}~2_R@G&MkLq-qHusd`#F3)7R30I_2-HZ6 zATy6YbOnD6{&8ASbe9Yv;9>s_rSS}H(%kDsDCCWWm}4{EL2;dwLW{;=ENiely3<0> zrp$rGS6tRT2ga|4xru*(3L1%3^hiAGWvRA&dK@kmr97U|aE_L1&Q+hLWi9s)LZrph z3*!8zQJ)WN7u%9jPgM-`LfdN!SqB~14I zwb@5NL9PGlZE$v^-AC4`bAOn^5!+ko`aikRCp9X)lg{==#7=kGz@6uoVq|8N=KlW5 zi7?cKQ!l<_Jk<Vky=ZFr*7?IK?KNK52Fs#hXwS|-sY5IV z5;AOQQ1FIQ0b3zX4*VgD%z!|4Ih-74it&+I)i4Wimk3hJ2vtHt)V>ID!%~ZN3_te@ zJHTeEW7)J$kpgH3$~i4BPA(8SR$a4DT#o@F?POABarHU>GOyr;ahvNko^4OK)?2EO zyKG9E{!#ZG%eXWTlqJ8xW|EZ0oDouJ(W00}n%?6)KEQMtuCA_ZBxF?q7;gVp*2td?mTjDmRKN5iQ>v<*==UlByu+nqJ@n;}-&(FyUe3>&ZxuaBrD%A}UcbYsM4u%bTjJ!xl zuguuEq~i}B@vzI}6lN}Jc)(@GJx4yY(46VGmkg$R*iE;YIEWOAzZPJ_*2MV^5z@F} z?3o!Kndz8bd9fh%i|3@XjF-Up_#kCR!w^WaH$Mw`CbhcUEQEY(f$e=vjQ(|OQUn(n z=s$ng z?A{&tUnDC$`V%@mdAlKWe%&$!FSm4YtA#U!&-hMh7sbe0IWo*_Nj7K+e>ZF&&is;0 z*Luw2PCtB?`VxQo`HQ9yQJmNFq}EoeIqFf|f0I5WTrJFllrz??P=>P_)IYhge<`@X8_mIZ8Tf+!U4wgs8Z23DxB_kqLC0I(hYOG1V7n5V0gGZ95{87 zWX)a#j>9C>Nkc!B&5Ua_p4k{&uilXKm1nXtHksn9IhmQi(ux~uofu@E!Rr~oiGD1ocM=_snFGL7p zfakVoLdwcSjcw#()HjDb1)82I@N^yoFVz7X)X@%%Pj-?4*T~E%%HP7g^#JBcMGPHq zB6XShW=F`NexBFR`1Z%gNs7K5L(X5P4#Aa8OJSMKX2&4}$yBpGwwV3{5pQ zKG7BgOqILSnGKW@+=PXBQJfwDMU*Ye3iiAZcc3eLn&gklUkKPchGs963JS!1b&~Yk z1|OwE{Do%D;|j^EOVot}Q`3RqUKnKIjj|6~zV7jkPhIFRJ5y*I&4r4-iZWHNjj*Tj9F?V?7%I^PYAqUnk;XbKR<-S{0__-r&wDzFve2W>XZQsic&J}JEVrWV%z%K(jnlB zXw@(^o598}tWw-)wAskWgu8kZ(2SkpD|^8bbKtz7bZK{PAQ(+d-p?3YM)saDxs@+sZ|0y7RTFk$e9GbF&b&t?*FmbEYt09CEZBdYBE}K z6@rOpU$*3PW9->iTI|2xW>{br_r*|Ml#(2QP^qg3ZVma4*SB&St*;oeBVmPR;Qq^S zPJr!*@05LPC+X?5Ww%CFUFw-sdY)5Kq57kTnb}(E9O#4xYn}v@1GMmb-#t!0fV-LY zABF;6mnl9m()j*9b0_0CD-j|=Do0N#Jy&)nbd*!kLxfBuwThDsye-^%S@X%z9hp|h z*4!XM>5QF=cgz)70Otom&U2s`D!E|#X&x+`4vk1m&@K~69;mQwn4K#;)lEbd6(y?1uwdQ&n1ODqZdDc57VTGy5fqr7^qxX4 zNV0kCK>=P(`)40pssvju$$5M95^;xS=<1J8=fWSu1*(t!^iqQ_n6)P^;m&3$o?B!0 z9st1ta18K$TK_J`Ng%XCK*1&K#6_P`Y&S(CuJ6J!C1sVRnT2ADoR@i9SH{ucHa3!X z)s-glIM=%ooZmV{P4mL%4`2|i@Sg;sOWfA5b{Tw6Lc{d^VoQUKx7+X4ZV`tJB^_-c z27WQgmXtCSI?1j*J!if+51t~ZvLI-yYJ6&&3$0WPpd*n;Bsf~7=LsJEhA*x&UETEj z!OjnNr*io(4WXr&IwvZcqLb{^a8qXMOCNH4tHi39gkJU4GB6%kBEd#$yAP!_(pxUSPhrLHo(>-^CY-HB!!P8^($KE_yQDHNVSZt8V#TGRI{B> zb6{KWhuPM8j6sp_a(+G}rgdxI&THN)$^)2Mq;&k&&-s$MObHAR_ty+Rs-Dt+D(g8~ zQ-f*?YoYm#EB2I~J))2GFNscRSz)hr$%AC1U>O1lXsDw$;z%Q9+oM%Yy09Hy$q9F^ zcqmc`-Bw8=F?Mfk`e0*qs+U?n%g&DjtiQTwfDiNcQ3dD@|zul@E^j_Lb(mEzbvzA+Gq0!}OLc|@flcYL5V^XV3i^Ckg{dhLEyqOg14 zb(ZSs{RaiT?+nKL7#-RiX!62j5DOy}<2$d4cnOGPL2Ee2#oaH$DPjW3CT)Kj@kYQU zFNa`-i$M$fX@?&}PZzD%rEvfvvIF#v1vz-8bT;(X@zin>Z|KBhPCsik<=s_@gIk?Dv&R4oz-%?;*fTICy1mE0F#KqM=S#02Tz=zr+BXz)q zL0l^xCKW&}rv`0~!(xRDD;&%ppF|MW%7odiwcDR(VJ_%o@l&#nv7RHl!{=hN4C4UG z&c*(Opi60w6)LxKuP@~1GWU%$N=WA;!e;C=(hSSGAr;=;-dZbO!_)|B4ZM47&p$9K z)tweBR>kILlOzORn>J8sUKk*xOCp!s3duv81cBH;vS5?+h7V*>ECQS2HD;!`yb$$d zyi5TfCLeN5p7oXLJLS%*K%PK1W;Ql>i!(!BtEi3MVILwUMK$ozK_Z{Q*-hc6RSy$1 zdAD{2T^tg{3ug7nv(0ZAbYAN~PIgA!tg44*$JNxLF_^FVzENoRc~xYLc-^NKg?f~q zX*=C`esw9RlC48(8wsK%sU=RRsokxO%faz^{c|xh>4W(0AF;3@3LBopYyu;cPV@S5 z5+W|6_0rL#i9(RJcD;<0zhoi-YK=oX(0qcUa6d;MGm~(4x2J(WPgF7smVmG~%$8VY zg&+Wc%ZFomWpQz{;G41hjVT9XH$&lp^v*5|OT<}hx!rHhh`~KV(fAOGSXq4TkW_H* zqJ7ZzMMn^Vxy0sxhtDgWkw#Ct1?dN>ik^{4Ls-5t-hEQiWEc&^(={})v($7FrBrF! zSo!Vkrt=SQ0T?$;s};P>@TF5XJFVdu+TEZ^U7m+hv`dZgE5YUqKI~QO8C&Y2)D*EQyAGncZe^$a?^8O=avE5% zpzSr*%Q@zNP%Nwyh>D2kfj1nvUIgFX2Pv|RBO>+5h)Ha^Vn z^agkG3{HOH_hZ}Q)$_AwApfN2fUFm}>dKSvEp;RoRi8Aj?Ki&vfe~2Ybd40mJv`2B zUV4BrmZth45VwhSQ~$+Qq#lGh=$ejV7_CK9f$P;hAF^=O8NyhBwRF zf*|EJ^$<)Db&w9VosPC%pJUPGVh;&l%8v4@!MSZv14Yd+p7wMkbTE6OBLM7Fk7EUp zoqC2<>os%3%ZS2`O?HD5$zD&LDbwazpmQp#qO&R*t0?cYTmGTf=i1_2YexL= zB=l!4eW@JfQjx}JGH(%dk5pqqjWR^Hgz*z!XoaFMYx)n<@e?tLsy1{%1yPj*aw60B z0hfMpCKtyr=q-%FbrRm0A%E1AVeMZTe7(WxIViDt3ZV65$l7MavOZ>g%P~n}_5hL* zx-;^A_K^zWkEiOSde9N>9PzS3@(t7s`Y?qkof;jho~7l%frPo7} zYSXx$*g>h8}@+rPH9%N*Rd}D1#sd!{5M<^SE!n3*&7=CkV_z8 z$ApCBs54%_s45{s+?kfM>aS5CmIz`Qd@5d=5;1#>x*FD_20RCCcm+OKH2nOAqH&;X zkmvNrma=$+wYoi88J4`;s-{&STp;1 z`yXnG8##^Z)WT%Pkb^lPha-JN>mRDR6af?YzC8#(U~>#lD7EFO!6WTv zEVL*HQ|&R0Dq`bsA^*kcr4`xW^@)+f_q^~95s^j@azq=)mkY! z=g7tG0@t{Q;y5FA@A>IIR*mR?Pbc-#kN#Ii#FfN88fPK7*{$41VR-2e<|^3tFiHJo zBtXhQh_HkCI|nDi6a0mz&r=({QNjS`BCb~1p^tgcV58&RSzpd zf9S_@VK9UyV+yYlp)-B!GV74XhBrXqWj$<}>;*3M718e5+$=9P7Tn&y)YQ>tN)@ZM zEPz3QcGfIDavCPs8I~+CJU-^&%kIZ&&sXP@Mm7cm+50D?fI|0Sk?~>voLESn#~ZB$ z{0BgM?yDl2mvLf3?7?+ozfqV;A8AG&B9~r#`(CiFcMl@DtGlLhC_)Fg!sT&4#q>1m za-_VdCbg=_q+_FR*!gxXvA>iF}UEVV$-hoe(?I~7GL zm?sD*D=Vj+_^Iz^?@=e$GVR*U+bDWfs|~uTm8FVk=@r@Ej)uStCs>7~`GegHp(VeJ zIc;VOwQ-l4n>UbxqdL&>_E1CA`JnzBC1fb!>HbOZsr5*MsTG=gbnnKjdS-cGt7YJY zYR+rFK~V{)l&vFoVco3{_W50+Xi~i{FO5j)cg!#(EC?DFpC}};L*U~V zW1l!@L|CAc>XdG3pDL==h*@4@GEvOuf@dx9^vXUxZ(#W@u>EbVcgsjlI$vy4Hx zV-ZCa>)3$7jnsa7d)e7Cqj)_We4J`(p{A!wQ~)Ir?#A!;4AzUq-RsN9OfM^|0DF7# zJ;#_HbgQbHyaf_g^km(mIaR+8iA! zd8m0kGj6Mn14EG;Zy^oTWlztFRKQKK`~ZOE5F;v4k+7B}%ydBWBaww1F6z}%#(zvg z%hE|RMhSLz;HXLcP8^Rq@?!mWZ5by0cAT@~ zU@}J60Hm1Pb&%qo<$o`<*vGdLXVE3b=4DLgqsX0T&)jjD)UYD_|LK#)Tdsr>bisHQ z+a1e*_yUsm%Ou2&HsFr%7l5(@HOJvw>R|%AmbGWkaD|8QkYKR(!)0CE&MIQQ#+z?> zGqA;fJY7>KeIHop1(NNz@f!&J-WI6}KkK_o;0M@LHphcml$v9nq4!tWXEFeEue`7} zKR$m6An!tt9Z{OiA3ZR&h6Jb>Tj*V*)D&6W4Fk?wG|^Bw_);whG(g#&=AMrptFXO+7u3 z03&w1DyzC*CqUaaIm+2<{jM>6hWrcYM|Zi-hmNOk9gW66o3+ z&-=EYyNRC;XHdyfj$WAV27GLjREXbH#T$7yKn3HIM@G25DbD=;6+^UWe7`7p5b(Ew z$AiY)V%3_RAJ9Img{KQ%GM3MTjkHzNw%Ly@2Uj9W=Hc_RTn+R(^RZJUY`EfGWPFNws9p0M`h9XD-Yr;D!BS?>CS@Tc$vJ3d9WUA z((L^1Pp0<X$#l>p!4j$%(}=f;C@vK@fLH%zd2f`Oe9r)4;3}U*;^0V(JQD_{d&=b$30d9?n|i~Ds=NAwLt479mAI`dND33 zYA&{BJ=wEf27&0F+SVV^A8HAJW5HSK_cZ1PzA&OZgfsFXI|H0MC=GUMEcK*U$j@ys-{$cd5egJ$1iu@-NTOP3rG*&qWm=0VnI4G1A#~X~$qMh`%0< zX<^xowWQxl6HX^0;?@_HWKQ}ro;2Va2a7+9Ke*l zL-vRq74O0k+FeT@VOEQVBlN2BEQ0F#*G;{Ryz`&=b?PeI#&+YUx8X(J8cmY$e;(gI zEZ;~s#$M%uuNYZp=}BBc1*jv9%OQb!QD8pQ#u&;PvKJ^EtJ+gLV2bn%Q5G#y?a zxoIf*6{o305&yKoN2Z>=IVU>r9r<&MkUJFO13kVC31lH z6;0){3YRsjw)1*EDT{0?^FFZp7%gvM^l>f3D1F%JJ9YiFcewVg7l7f=OSwSTles14NgujG` zfD@?Lc)x9=+g5#%uX~35&0u9E9vw?NUovw`yT>YwK4|_t8+wOyGIWCvAG`kCw0|8} zdj127jxQI+l1-_X)WYvKWzEJu)r$IYyZnP=Msj8@(5OKa#!<#{tt~5%P~_uh<66uf zy1Yw=hfqXj?8Hh)Mz^7T7{=sVE&apa(Vwc4S1}XCXjqRuMHO705^}-&(73I73CNmd1Zhe1Yur^PCz+(LmPyNlx?E(VGc62S4x=+ z`GS$&$s_VVybPur&e5~XacHj%EiK1*hXg;t{o32R+(+L~B}6y`GDz}(fn0{;u8X$5 zmO6A3YfA~#;G(J}K3ITrML-GfNFvwGtVX)s(?K&w{THvnr(Njvfk>Eb{^eyK9~He5?%m5F{d=Md-Deif(JW027D9Md<l+}O?BB(JMQ_(8cLku9dZNX2!+ud!+T{bhedo5DBup zK;REgr#2R=&+h;HkM*ouw_(UQ3^?}^vM%ljTXpG1>erM-=?7sHKwSR+l9w;LZ2Cab zrSy^%l{p-#WiU+#>!2r=L|jcb%1L%S9fr3d`%8gYQN*t)5zaL``~3zAbatJFezLf- z4Xf9>z#zpG<5b~wCND6>@ZxU?vpFJAo&Q_Vf`JgEhu-tw=5}rlU|YZm`JZU;kr7C5 zLV*4`UB^a8>1ejPfwXz}W!?&|jRAHF09wJi*sbggRtEpyIP(o=4hEPM_Ulg$!g*aY znIRu|rT%Z2q^PsdQMP?$7&^?<9i@1((5K^OZjeR>hFbPWJRiWw?^ zGa#bcij08VFIZt;QA_+_(FjXe*Q8z_N4LHPuUilKgc$NqD?R^ZVs+vD8jN(^N^w?t zng_E~&aVMep0NiLMvapq^77#ROg;tuf2_twliCbOobrnQB9mALFY{|$bQkr^|BQB8 zIJESix?OXciQZI1{0S3?E64Yy+4(9W|F)fN+D4iBZrBzAQXlPlg58oenJWJHzW~_v zH0n&2H{R(}gy)976A<;d9kp%`6Bg>l?jUWmIEbqlHoAIAwPVNC*TGwP?}D;yisL~^ z^HZWC%L`ba2M@h25q=ZEiW@b_r%o&Lb|va*goAFzbf28$mRy?e!`Zw{^}$@{Zx;&JSP0{J|S20*l5>YLkJGw(GQ72 z4axZ1P6@JkI`XL80Ao`{vjbQ)ROj<~IKJ6rf%zb44@RP&V%fJJ@nh7NJQCXl5#Mh? z;l!q$_$y)x!EqSpnwe1lNvbzqr|Mc4n7a{;ww4+oQGdkl`!}g^k_Q))D!f%5h$3&S zh5MFb4AQ=K3zBm8`SFKDE;kuN@YOO7Ub+zG`$#nPLLazNEflic;@vCPXuT6hyZe@w zwb3{{zmQel@!yM*D);Hc-0FyY3x`d!3Ib&mL(||I3|(n(K-s2sENh4bEp)B>J0!#H zS1pFLu9#K1E(s5_8RY=~bXZc&l7Fzs0EzfT*PnF(nT#r30{hZNl)Gi)1-+pVEevzN zeezui3r|AGy-B5Yt?`{*(Da$~d`t?x%+m5ogjtZ(+l`M$>gD`j!V4FkOJV-9@ta>n z$yl~kJ=b@J^?k@O2D5oJz@d;)Z;njHVAv4;hTz~1@Hn-Hn1Uy4(njvye zNP6-bTnpw)J77%F8NO827)A{$`?9V1Gck+_u%NdiSV`|12_bEh{Ir#gDG!uS9d+FN zZFhcJ*pkuLq7bmFeD#n|d~c$f%t^;Yp18@2#<+s$Q=LtL(yYXMCjkp+eBGdn%MtE) zG$~d+MWb1;uK6OJ$9t%y!DFAcqI(RiRv2P-n4PZK{>H8y8V?G;pe-~AfHmPm5tnRb zFlCoDta*9EauS z8?sHPk+M)$UkYGKKpJ6kvq^1Cehw=W&yxKBLkhxe9##M_;=^dOcC4s&j^04J&f;HM zLuSk5q(Nnx&03#Axf-b)gCbEJ`L7(-j+54gTi;8I8UtB*!lr{#2$ouLj57T%?&=Hb z{`o3xA}I1RHM*1Lm&EP5jJkZe%`n#)&vE&0!yQ!D!&w2J&jVRXBt`+DDY4!^XNimg zF^y>p{r)xx(Oa3JH5HhPP`Ul*D9nmS*4KJcWH$W z@Mks!w+^GqsoH%Nev5wpQ3iN`l@hK`roSb=>x|bp0i`K8uOEJ$Ois7nkn)zs!_<^I z8q;azu)*boPX!Kn*ao8lB0UI)<2wtw)~QzF4k9XcIWRC!6l>Q3@tgDvEv{ykHrIpV z`r8Wm+DW<93*9BJwD#6Fj)n_Rn#gul+|p=1vrwwLx>c7fHjCsB)Xlg@Kmcamil2vP zA}H*!Kg@hepp$9tWoz+s0J-+q7}7e_8pz=@V$xMoDfW*@%ZVKq1!2JyzO45Vk7*h& ztskRB0CEJ@!xG7Pfw#@h{X_T!@3t)?OeA`a-v0e8B0Z*!#^6)CUH{Yp#h3~^$Anbw zE`~P-V1)eXp99&SG8Fv3)VcQ2<&uo781F_)DxeB}drSrxI=^M>A zK#g3=|1jCma$YZsJ{@~Gts;Qr3Xe?7pcX$`9~WCeEBCZrXQ5LTN< z^cr{%(N7UE^9UnwbBFI)W;Zo|$NJdNnO%!=*U`PdgZ~e!T`5*(OUzllor;p#yV6n|-kqH#+;)uvmD2(vMA_D9w)pVOX z7xTk8bZlbDu>x)c?teIKrG|PUy_qJJuO}@j_X2_{9PNP{BJ00oGTcgI;+x`D)}%u~ zYCzrM^cy?)d1Z9P!fmhB&yX)@>!MWhpl6L&OEiQ{FIhm%-H~!&p}S8dtNltnjzr*Q zuufh2+rGxgBE zYkE2lx<8qJ&AS83D{ZqZe4YM)RA3#ZropTS(b%DZ4|W{LrX#hXAP$*zal<7B&|DE4 zXu@CqEB|*WJGtmzB-(A8q zFMdP}SuZ*J4YqiSR5~%z7~4BDBACGWT=wE$DgpjNdwo)N-N*Xn;wY%v_2*Z4*=$3oey}eV93$EQ@I31rkH!ct~;C|!NWaGaNj|9jG^f9zi z9=s-_n_GEq{tg9#=kiWDjxW=LNnFe*wx9+TN-_7G;OPncKD*7SyHt4_$YZv4^GMrC zlh~um6?2t-S+jp;Z{uWVHBvSr7jSuOoQIOp6;$&^ff!3|F0e#89mgKGt*a;clIX}U zA~gg2q?n{xrLY&cv-rJH!JnjKBu4SE)XWDwnh_)GfG_7E(=@09(tSLK`UlddbyLlm z(L7vfMDMsr6jI~YV{PP$|xPtC>4h_WxPbN_prrDoJtl;TIwT8DpXFm7uqrJ$IHOF;}dHa)S(fmv^=we3%@ z(o;4h+sBm7OKo@2 z@Vm0U3g@`q-bBq#^$&19f{tYj}9upOV{w|TlxTWGhHztVH zRq*WE0%*1g+6}8$@n)#YzTQ+ajI86i^;Tw0jC z36oRD35*W};=@j*5Os)jZx}R3>iD!nNQEo~w4NW7jEo8BaEp_}47pdi#q|NTft*u%yX}L%#37+NgmsI4lhLn`x{0g{TZqNPnHS+cg zpd(s^j<_QS@4yiUrVL0aVzpbkRJ$5Xw*8Q21Ljk&`$*-2msgM`R5TpO004d1{7p`+ z278O`+|PU_@{eoEUA$+)t(~I_^Xdq|i^Byf<)W?2nafgIN~8DkLUcfL?zJ;87+ju- z2ypmPSXLFfjR)qe`~J0a&VL^O8{W?#gavHh)t(Tw)C=o5w6^1%)ZEJWd-zI3ebBTY z3>9Rc0v~Gca8y<&^{IKN4`ePV*gc~7yxP6zYKfmjxhi<0fuUTnDvnS=>qKDyxMs}3 zNcLId=!$~MlBpFa>m%m&1m@$bWIs09?)7C9mH!W4$UCqWNO<>0$Y0&qSpvGA5h3wj zKnBb6E^AMp1SDvcZXu4C)0s8=6y+w#!L6gK2|mCU^k1}O{=n@$ZhMY`2?2GvoWB@U z0j42wiN__s67~C&oLiq*H(v*<>XR5*!SNYjOZr-<|179vRJ3X#tc6~vih9?%gArET z8uA*h10JM|?zu=JvR|r9bfJxE&{p&dD`uBU&bR?T&@LyAht^%*YRsh^cqLV-hB*o| zlyD(WCrK{VC)Y_#y_5B=#k&{tt#?SASh+z(MMTqr?N-!w)zWKS151@{Gvi&qB47&q zAOez4$yLYAq)+KCOMY2nNA27!3{UB%GxUYuBs5vb-ka;^@?YGl3zh!y_6bQ6_@w7Q zFf7qp1#rlM(DQ!aqEQu`e_I~`>LS;c5*k#{xSHggsQz#2$Z}gdGqKnDkrC@KxCle&I~r}4 z{!a;@m&?>C#bciq+83#xu=RTR-8{K*F-cp2bCv1Iz!+WyGF^(PJ|DxA;%h) zx3&JBIEg#o9ccl{rjAC|Mn>c&)M{NMoyOl0gvpD|$5UPJLJJ9hwjN2$bjDlyGEhjF z`3p2u`7v=OYrgif6LP&uVg>vTPR{wXebi{ zJW;Qz-MQ2KpwNzStkHejk`%e>FQk0iw4Y}mh~e7LZn}Op!ykU_yZLw8DY@ebFky&~mXoX1RGP9x*C0y;8Fumms7*3(u z&<_s_=vz0(rxk!Uv%)Xd&*GY9lmmqBda#tdDk*JTMyjf|A&(55@T{Co1sdi@E z4wmQs1jm!etat>igJU<3qHkr2LLP(>&?L=(n4sTUhrM8+sAwXK`8#$A1~QKB#>Qgw z$#;O6gUHHi9_`|d^pv~_woC`0k=Bxwox>Ud~hT z9>xL@2FGMk9eb-nb@Fn1+VlS`Tafl`1VxsNkAbxFcmbq_SBM)w>Q+J#sya-EmA#eB z)xlBJJzA^i%@C-=>V!G_wC(+pG!WkB=+ZJx{3#-gGKY>4`bXS!4vY= z&#)pjLIJn9=zhhS>qQ7b9bLv<7SudM%zOddw&?WFW>0rSMCP)rwRU#Xq8;80TK}zi z1DQN$9E&EP$r2L5f4Ze7Wuu>yEJ`$Ag#giSVML`0l{wH_Qq&ICir` zq6gGp$zotUwvCy8FN3&oEHic2mO-CZJVr{1JaMi5AlXRQLW}w{Xv*#ZQa#{(XAK+z z&+|?4h{?!B^4Y_23d$oVY^RNYsgValPBihFoM>a%al(#~JY_H?0mf(}!O_gg5HjY# zB9R!9VQ5y!W=$~fDodIg+{ar7v2z+424q@NeBqM%6Y8xkh|>)taE5xJE~S-iF<73; z8CTZ0je4nw-tZt{e{Czrdd}zd^$fIP%SFBJ+(8Q=lBiL`YsaXm@dGQ1nryElr#m0Iw{}spA z{dNB_SpKBh!BybGuz$dnLzkFyM4r#oKHQ3-+t_X zsSvJ-XX&M+pVU?xoc6z-@dnkepn2P!$=oSyB7wNpE-8lFQxc z#i=6mPd{FJI^1GL;G(!0nu?qmAEFDjxmgZLaR{@zb{FHKqLzD3;)GH!m^{m)9^yMm z1O|sNE?&0JF!7C=MsDoyZHL0%rtAht4yYD*!Dsbz_a^&;U0yO7*ym>9lN>oxT__wo zW4I{t^t|=eByKI9=hv|=Z464g0;N)juExMD88&P96X&U(Ev2OL542$*y9-qdp&&Th zejzkuk#W#JN5#g+D=IX8um};e|2oObr`~~~ze~3TuZv1PdLj>8Xr=_|sLzRYu`2k> za63>H;d}@59^l{@(}He@GM(EUtU__lEgc75Shw^dVrA3x&b4M`MpF1-Hm?IGzuiNL zPlPlHg9n+e(JV^jQlF|Qu>eSvbR~=XtbvFD>rbF}<<`$8kv=^YfXH%=3&0~zF7(@o zW9NzYHa3y(^Hx^cT1fLg8H?}V&^e&=h%@NQV`9W1 z(sP&R-qKTgIu0}-iGcErxkFZVc!knZFjE^mH(TBjh^Kn>ceY)*#khqO6KLCdTE2kuYe6t0 zvWgug4`wWtkloW!>#nN=Lli`>`^{B5BZvkw1GD79w85fryzW0w*6(9X0Fhf=40&^z zsYcWJh*3h$FQ=SqU>GC9U0(>9%yu40D3_5F6$^6Q@a72f#8Hs&a%pB$cF}M|A~fbV zLv>_2(PAQFmw11iEq>uS2^D$zD@?(>xWwk2qi-^n0%GthI_JXahCmH9>=vB>9hO?N zOmr6Wp<7$it^)aMGti9!r~p1Qf$t(fV)x6S!dQ17nG~)(CXWCphqnT3eFoflq^;Sb zj3~+oO((mZ6gv~I6R{Fy@+`tvTK)nzEg|Gh#93a@RGE@H4d3GKr?H~c6lyLF-(zb7 zf~*KA@qK_(!+`@7YOhdO>tv|AoX)v6eX3?VFQ=3qK#a==**w=&{YPW}>J&ItavU>t zSgVUG%3lG4T4GUld>%v*P2Q$G;DY81B92!f@Wq`!A-bjGx{^ho2wDaGV)2dmqUGmR ztk>VCoiEF4DBB&OcO-bwWK@7Kh)_%>3o3x0#757pVHicX&K)7n5I_)N7i141JHFGlrHq@ zpvomP6*f7SZ>o}4L9{tU+(Z@eMal;Z(@GzLnIo;66#+cpfj zwwdZ`{#6G98+noE$P_m%#odvwm{E++GduWzygem_=rS4txy!)K{0qzQI-MbZen;M< zf<1af6*}6UO%}9~+s_Voo~0iMsG68&En)GFU@)cC$3oWf+Y0}3XW#&%$1<7&Y1+lV z>2S955#}Nf-(KW1DhUz7hxp@6@x-P}A```vI?Uy{>L?@m@j|x6`|E1L+i=Pq3J*b( zKMVnuHxQ-jAq5*&-Q-#Y=Nx7e{iZK-)6oFHtG?PLiUND$QFHTI30s8l{8$xRjDuHE zQ@^jw1wqpW$Iqb@0F`XTSlhDWE&OifZ6bdw{rSI$_{h$l6&Vwh?_=LC-qULO+mdCh z4_#70-$!x8AH}g|StdT_+?r41uwbj&*E0=FlQdVJC*1t;CQo3p*QR(~T5X1+h83q5 zBW>+UB!8J!_igr%mIqTb0M%Ua3vDN+0kClu&ru7x=*XXbc_^}K^CBD`z@y_0btTV+ z!8kzLY1}#3lB6<_7|oy`W)isXbf1NLW@eZXYmMC&vi0Vi`BPOxp!eX5krVWQ{Au zkB3q5?2-_vm6gyVi}e?$;M<7wa>@Gg&>Hk+c(Bg`D8wq7sl2X6nd>Pd(P)2F&l2&g zP9Xi=CJ@8{PfP0+g0OR{(g!xU*a&oF;Ps24lHMEE8l&X(s2~f?4wLeeF#^_X{%PIU z(Zj-f;Ac_5fCpsfXh`h0u3FMnvdz4=G%hJv6b)uVozvJJw{3CS6X{B(#|cRIQhTaD zI^uc|-IskgJxjc9_Gt}!;TOB{h{OHcsZU}}g~215#y+Ttpk^$G_v!;KXvr2tFj)na zPF#>hZ62dmb(v(R2tcoazTqpFEq1S!UnCtKe}%mUt|sw&D!UCp-bGd84r2`9AJ2b6q#x^h62ynH_?j;=9ZQ{db zF)@b;{TcK7d*F91QlzJP$&CB>$t~DayO9ty1x**WCrG9TzuKG5JIwKgd_a;O)s>VV zA#^JAPh^lGf^TtLTJ7wVZbqN2cs4gLx)L5L%9|#w=~h^SE|Sm%P{RHtAe6ueA2q?i z*|)dY-XsL?Du})7cLr>I{V%Q{(1;CKusc176JfN&>_mh=8FZs8bEP%F<~8PbkhxCW zIgqV2)kHgP$ut5~AZ$OjFV*Ir%NN!6?n$9aAY5FDvur=9B0FaI*~MKUy}6F*Z2i#i zYd!S8RkH3>r#35T69&ljbuyOF|I873M8xCd+1H>_Ezjn@_lk5`k?=THucL;LLFPK``dQUxgp74X*~jPaA=h%s z3u2PGf341a`3SGEiIv)D7}8rDV7OxuM{-Hkic^`74&cek*Z?g+(!Yiym)SG^mRL_m zP3L--lxg(c;3XFmkoTj?c?`AA^cNXg&JZ=Wb$x5*8h&?c8azQ>v{4>`n=YgOy$rM< z6cs~;PjQCg0a!1sTOpIu($inSw!L|Wy=wP_ULBl?nneWp6TA`t)mG=5t+tnLi){fO z7pg61^!~*S;w1bTDkS9X##wqwGWJX1PVt}iQUu4_u>DWY#W!&JwnaXfSR)%pi{53W zJW@BL`yDq504m!BMwW>V)cM3b1}ECKv&$lHfAQ~=i%MOf>8-(n+e%#6Q^`0#6*L6^lI%TbcWV+Eats*9Z&9H5K(6&H028!t;E0q+Z5mCyCx(Vwo zV}nnEZFEfE=K>zmOD-E(7)&rHc7=7)?Cp|>gRm2Wq1NxHDzDFq1{ul3Hs1lCQfKZo zo!q~IA=~4ECJBFB(A8r&hcnPRZiGpw>lKh}_m1r(1Y(>ivh zHO6Hi#oJYfpP*Foo2yQ+p5;3^pj&|Yue03#n+hZffazan5b0-_=bN~nQ$mbh zl1YXqC0M$Xz#9zt56Jw)Z$q^OP2Ilh>UN$Uf4g>ezuKXSBtv(cU^f9zgKd6$-1mD$ zMP)}fDqMJ8^ZUdJ5emNSSWN!zA>TKbI!hHo=PJtEWb=pSW$f0*mNwe+{+IQf!< z^<6${UfT+p+JCQrhthIf$;royVkZ-GcRUfYqlFFoNWD2Lkbi19SrD5LS5WGs)- zZz0$Y1pEnK@|(Mft9vCg&#?nO#v+<$Ayb17OLn%l|)%A zf!)de)Q;dxfXlfhpX9J9dH_W@f50`U+*)O2IForr$Jn=mG-0YbQ1Su;T_>Si4|Wob zNbGXiL~oqxNNNogDVT|6XM#2vSYJeQ{gm%&tN>AGDi63f@g}Bvn>{Ks7OPzedu0z^ zB*3JMY4OmRv8Xl&cFK!Rshz0?)y6RqgcYbK5sYhWeoes0s3yn&QWS0Fng)K#TOxH0 zVRhVXk;dTUCQs?5Xt=*F;1T}=!lqj6SCUa8DzS1>9U^}F??#Kw;_+|maX**doOl)l ztv%C&lGha}16oI?Y8Tm2C>E8rHWJ_Rz~_3${TB}Yz2D;Fc|*y5d`L1OY=k%|Ifmy! z1{i(3S8cfj`q!4>gyDC| zS32|yrl*u_x~BZuilr&gv$L3y_?>D#P<@`fmK}8(@29==iDjsTMsYIxpxwsCz4!()T1_N2kxvfluw9>(`~@ zYirfXk06Jl=30AAeUT9G`F+#;zNoq#$z3vCUBZE<*D0Ao?A5Yac%g+QQEjN+(WH0T zo%djj_%_%9nwQe8t=R7i=bYthkV5d+(%Pgxq;e$1*&Zbk3F5y&M)E*&M1I?rr&xa za;6d7jUfAY=;|>PSaow)wZkTQKvQ>&;A_#a z-%K}nz8aPhI={SwHa;ISpdq`%P`buK*1m28_aIpa5^<=$ z0`WswBL>9D1b#9(4wK`PhtYbp=yqz<%l-gm(9v$vwKqy3RU@ZINgdqY)IzsZk=C~| z>NhSGB$(oB>shM!f0&4kL`@-Y{bANQIrx2rh=Hl82F*)&Se!}Ktv3DI1emo0JEX#C za^}Ye2mJD)cz51sT<|BCZWc#DNGrO2D)2EMI0vLWSeXzQt95}V}0I58Nv*7w4I z!i&!OfM;oLM#WWV;326e^Vx*-r=cmaee!j#(X$e8;-){L-vvV93d8)C5$CXOmp}3H z2n?5LmNy{CJy2U7!2a2_XCa-Gy`Ymjyc`e<1#kR|GyujH_ka*%Ab?Y+n+hdceB4h> z7ca0t#snuR51iKFm^rI5E9ws_?yg;<(%S+LK+Zg7>F$!7YeKyF2GoIMfsA)$A6ZV! zcohOIkC0aHZjV~~9sedlHk906Ik-xZK4coj^gao4FKSi{w_vO()+#ON+g6;ADmEF4g+_YhY2LYe8yj(ReMKp6o_4Ot+UY zstDp~++-l4l3qmTV*nr)^|#7_B%C&lpkW_s^siDUl7MbU?G%oA&v%+?5yr~>s*P(1 z6NzC~$Prrmo-~leS$)E+P$hqTe20Y%%z}uaa);mHf(W4-*}o?3dz?Z#Jd^QX^(MZ0 z|Cc_p>x~}29IF4?l;baEwH;AF+4HvRHLG<25wdMbw=;47t41Fz%_8Fa zp_Y6(NJ^N>-SCR+1!*k?LX${InN*dsvyD@N^ljJXx{0U8pJ6<|2jUi&u4Kf*MGt7JFQ+EOP7k6aO{DJo z$kwo)66YwKF7HZ8LZbqZSZ$vN zR1#-l@+bHENvXS^8!~d->?p9Tj~zGPL^Tt15N$D^{k27={5etJK7s4>)l@w=$U4~~Ph^e!zD9oL?yo(hP=l9^ z+k%IPL>+YxpQC}~a=*X1x%5`#vPpzR{KtC-$FJn9f5BCa$Wg#UygQxg)TI?Bn4DbL zEW1)H20gf6PeKqIqomQSVPv?OIqES~$HKkK#WBVw%J#S=p<@L6q4>7)m|MQAr#@6) zeRiKRuiuP|0;)Q<(uP1-gQ;j)x$io(wc2p0_0AXOYXnfj#|gb|2bOip_PtA9X~~hM zW43lxvpQNc`_kbsp{iuSJ_Ah}!ueWyiV%pM0M8F9S>;tVD-S{jVB-+dOj4mUI$Nu= z?37IHj3rW&DTqsW3;NnY$IKN?|5$>g-BL}-UplSI&d>w#7#@4pu|sQ`d@@T_6C({I zcr1ih{F#kxKABv~gYTazEkZ{#NSGkBkpm&vG;U}?U&&F2f|5oJW6&`Az+Zm11K!L4 z7kR=^1v3)rS^#} z%lIT3XfjZZZmB;9lY@@2Cz#%HZj;<7fw_Nxulp7=ar009;2I$n>i&!2_fk>uchi+a z;C>#2sj?=Vt_HgF({?qiCkFUF?WO!!MifZ6aBf@Bg}z3vu7UH^#a2 z%TGDegVK`>0w1#V4CUw>ez;j8I1MGH+q1k{F3b@QPxX_gM%47qzI|KfzC(`mc+>lg zDS9PBINnh=F00J^kQ(RV%FACg4BC&$wpwa4wy94fz&D>mggE%lrz1%u!#Z2t3vZ2Y z*LD5FeREH6&T8sJr-3jm&)zVsqV&s@kD(1#350?rnND|(ZYN1gJ=}V8bhgd)Wqg;x zLfAS@XK~BbdJeWwW~$B?Schk;W)!x!2OC}U5tr@v5S|4DfKjLcL0)$-H74ReVR zd%g(;POPSiHSqatad8%XVvFL?utbYWId?QogYhyfENR(Aq6vvS2AnXFB3UeF9 z*PJk9#S_@4M3qjmL;}rDd%DxMV)}`+xmE-ED<14!&!;=aNr{RG)Y!S3>(%_2a~@4m zbz<3k=v~S;+j*YU1iHjFFZ=^oO-jQ_um5CxhtVzW&{{H0bukr{D+&e%OOB47-m0e` z!G^8=u6gx@M{xV{iQhKaAi}NHWjg>1O)X>GygT#S*0lhN6jw*Y2&F=mqJA_iD|GQM zMW$1B>fWbH85dJ`5nLxAKxuJCYEbVAkY76uR(Od(*OUugxDGuSo#$^&hJXoCuw8){eK`tcpj(_V^rks zm3kS-I!esF!BX{EdAwe6lzL7J*2^+JHWhh%Dl@r-Q1}mumFV*jWY6xWoh;X4F;16$ zQh-B%M|0ImVm=WyTE>FqrKvxRu!lr(D(YxNWTH7zLJpBDGu%si@KiCwwQPUHjEf9n zF!hZPto5Iy=vIoz;R$x~?Nn|nqHIH+z+f>tXNbb+7D#k}Pkgk8i)QRA+L42C%S6a@ zPXDslF1NP7ZXeHhVTbr|$-~fAzIy~p0Ib>hJ$`jP7}dWv5^=->ydvs?`N1fYV)D6! zWRmlmn`zluh`k?EfD?^4XGXIPti`YEa)j#&TanabOb9uaOT$m9tK(G~mdMA`2PXUy zAfv5;?>O_!&Dj<%|46(SF&N5Y|KE5Z_0SCr5_z@TOE_Wick8kTw9>#@o1&%eD{Tt9 zk9Ox+yvXgQrnA$m%nQ**lJvC! zZW-_l^WqG?{GK(1ma}8xRrd z))s&Qp&scQK-EbH7NL{PGFuXzr@c{(pn!Y?<#3mSf_4tv!x%vBF2b6fWvuZstDrWO zbg%}X_zHmY91!Ug2kjK9$+x#KG+{6g;cOI32y{3G{?NWrke;Ix3b~3-U}ZT9Y2FtR z0(m8#NpK9=y{(koO(mzUaOmBtR%NBgUT0Z`#IL9Yg7_z<0kzS&W@JIzYX^Q*qn6Vh zAz>hDJFpK|!cUAESEb|p0!nU>Nk%CM#Gsuc&S)vayi3VFIbCMUx2>*2!3kqY zP=qrJEDtD&w#1eSi>c4NR=!Un+PY@l%q<TR0JN~Kws7xpiU*xc*NMx zzzt^?{<(&psuFaS!#ndQ=FvjUa(2if9}uhqb)XvN@19~<;f>86=>^De6q8JF%YM1j z_{J$@StG4LZz3-?L(a!2}yH8N@K$8vDTjbwhCjwq5@LJ*AYTW29~9aJ#9$dqK`Rk1R!S-Z3Yor#N*<-zg?46J#>uKt-L zX`MDvpQ8lEW`icPO8vXr2~Qx5g%PQ!u92KJ8BD?suJO+it;i$3Zer~66W!?)sVkkK7V@S>xV>>D7`NdLyxsgz1)fQ#4z z<;&V7z6tgIgYK2rsdoVM4mP@Z>XJ{#Nx@`WTyyBrrEu25F0Zz-rUb4jJoC6#4 z*j4PuTvlV)w(N0JnE#0DWD@#yECej5*^3s+ge*gg3q&gfqIVOQkN9oEtg)2CH3ut5 z`R0`U0Mmsqsb1n2j{pB?zgG-{+Y{1&^AQ{Q+r8_iV&75oOy z%8}Qyz7p1JR1eDG7t06Bx{qu;xhf1zYK*pPt;foIpm;~_DD&M}wz_`67W~#mC@36_ zvF}kqOh4^uO|@D^5((#>d%p_Q>C4Ifo6z-k#dEFbiOAVkJax@xzd+MOmrMUSFS`n` zOSDFo%s0qat!1{w*E^}=Wy@H@ier(7K_E;Gdh^@e0;uii>XQnP0CGWNoKXyDnk$CM z)m0WQ^~ISp+r~93?%mk@kQJ1<$$yu%ob6$CD>-2kr`6YVnNmID!X?r9`}P^Dcjf&9 zV$jd6cvEF25J*Fel;xF!h2+Ra7zbINV?F8p+p!Lia05vlYder!qexS=S9t(E^T%0^8O4_QSoS4LdDk_gD1L?j6ipM zF*(~#)1mx2WNDFC_MYO`8Kee<`8vj1MB!lcp>hgP*&^hpAc+5A9M-;b#k>ezQAmtf z-0&Dy!QdHlE8ZiRtdA~-NgV<0*EH%YX+Nf zVt`$442TU!3hTZVG8(O*njj51>5hhxDsH%|CJ;=WJZ~d6DOTF@_KcW! z;9qj-@UqI&OuLoUF%z4e{nyh8zQ3^XtF8QaYH0u4io9?28ZADnTYx@ zjblTkgI;BKhee_ZD)z3S+)KqmjhkUk+z`+}?^C}f8j&hF=2lWrVZ?*$9njW>3tCc8 zjwT;PmT4_x&^D}4xU=+`z00881vyya#I8mtavR7{ZUc#|D&k%bhhy$#V)uH{353G+ zk>o5LQ5W`#d{FAuS+}CCPxc}7e^i8aCB7r28mWLq3cUfDW0a-qUc{|Gctbi&tB`=Y zowU`i#;Wk;Sxd?@oFaV4l`63Nx*_*k^`WBYc+X+|G;m4|2P48gmuW34eY8Fw+bHZT z?`e?yF2$ghJUgce2CfSl&bgetXlBgMNA{SKiSi7^3=-}>F`XmY2jD-|nv@oqEV?N$ zq)fz^?pify!Ic14Z}CeE7p#FQf_!aKxPXyhONFEaBQ(l!o2ZxigAy&?xEZdx6xPf( zaC{S61Ya!k8ET(7a3F=6ILvCNL|H`*TQXpyalx9Hfq!`>o7@1+N3~rdKm3mCO@U-K4(wy+~tp zxsWO152R9*$h#mH)(l3P%^g&9&e)D&H^dEE5jei_g`wC3xz1rqJ^&D;P5tD9i3s;Z zvy@vo4}_W(5Bsr=EdJd5(p3#S100EAEEMxCzp>mk4sf&*T_2~?Rz_yGq@fWPOS3x^ zJH!DrN#(~H#rRhxRC-#P)HriP{l&Yk1gRjHdI0(J+f4dO4@_mS1cOs@&K{r*MVmYK4-B0L=z|rk&WqxIGibyU5x_ zOn0(Qna?PrU_>3=Ike2B8_>-IEGbEd`o|jOX%j*F@Kyhth?OKR75Ob$WTk|5qNJW3wy^;M^~6`bZ!> zp5P?78k_E$u`Z-?yw-;K?@n}}VZr0xdOM;iu=vaAWFcO?#bilVCs$&b3D4#)tzc6W z)*+M@7L^t@!%LjtJO#N)6B&ak5%!5-0859{9U!ZkRCfCd@iti=dDUqtfZ^&*f_@$t{FUOmsE-KwRucGt}lZu7#&PLslCM&s(4iN9v)5G1y4b_1-R(~VTg zLZZd2qaWQgH0;ctxNXNjMm^RJ9@lpbSWsUQRAoun?ySpP#5HA%;=HCpRixGT7%mkh z&V0Ewozs+>7NVTVRHsI^)zRnRS+A&9>1PM>{!$gHcJIuGaBN@q*+!VZ;EJp^skZp& zL}0x77DU9()4a~0Gnbw2uDKsc2t^h~{Q~rUbk%ViJ**P_G<-#@d2_($%OOYa^nXs5 z@lwmYF=!Pn%4I)i6BcTkfCyNAKEq9Cl%g|_Q7fqI0nl9$sV>dJqsN7OHGUhk4UUi# z2_l7H*Zf+C!SW)nkJ`gIPt;Rsms)RDQHX`k3i}m^#z}s|nny5O3K&%1IZQ9GV(vE9 z><4==`jwXiM*O$%l@*}nv2$-FpW7h4p9Je>p`GF_D5mOHH4rilfbGy*Z=*Vxw<$sA zdZbbB;*yc?{DbvmCBVQ&aP3YTy=Azfa^)vuokg!>dI9|Rvf4HDqzoTG7vK9WT1zh< zwfM5>b4yQJiauU*iH?57gEQ~d@QJ6_;@Kok3FubVqu5F<0A}CXiFL1qiO}{ft1M@B zXQ3p(o}S!f3^``XcRr{Jr6llvXTByRwUpBT<~WtejHj{8h4XSTQ)F%h&V+^`b=Wvw)+f-CB7marJ#l&pBdN{ZhiPPWlCh{mIW;C#XOI#~rt9%dB315=s48Ep_zHO(Y=E3N{Jw)}e(Ah>CGztM79O4n+14m>DYE>FznW)Alvo-wtZ+4E7jYM=mBOLMdcYOy zv8yXZ2N~1*XGN;ip$Z}~8_agOP}rtSZZ-Tv-cV1x6GPI`*Hpu__uW=BHyu80lRlL! zymo-*6Je0m4bAB(c{;a>K!gPe&kZPL;*i#VIL2S_2L*+XTM`TfdH>~LH^C!e0|r&& z>%e6kGyRa4LZVxZ$hs@`a+9C;> zqG}!K;AP^mZR`NCdBi$5G&-I#5fDhjkfTbS55_bcBMxk3!960Lz9DV)_!tmkdL+>> zs)c1oI%NYG%ok7I-QE>(`-TDwNAqRd8df0+@o>cm>6Rk`g)X(PDuYrY0j1~q8QjD# zW;&qEOAa0yCtZ)m8z!jWY!J&Uhu$F^)54-#IQmPd+BAhq30^!6&i-WWqyB9@z@a=f?eYEn5S=k*yq~mPY0lJ$|i9y zZKgpVD9sL~apFWDT1K68s(TsrUc3?b;K3vjJ}|traHiUw!^WcGw_r!aL@>4@s`T61 zvGePCgG8Yq&|WWme-HBt9TNb>##Hx zP6E=q1c0-b+I5Vc>w|ZpFx2VuX|$am5)t<}keuY;JI^=k3I1iaosRz3)_vY!(F!ff zkw&QP8QLDbk%Fx(jC55Y79WS-h9I(3){c>D5a$Wd<$Z+oCo-Nv59BS#`LQvm6NX@W zh@1NKnoM)0^Rofp{L9kzCfMCB3ScCfpmS-FOmr7PQgOWBLj{Nja5=9mei&O^|ZKVi8H(hL8Tc zq9beMq90$Dc2|yDh5U)wWoqYB<7R0CyswT5lL-I-A?3uRV|g0_JZ)*8A_PsJLifH2 zl8!TKY$TP2EkeH ziHk(CXOaqF!zz075-_*dW3$SN@WkY`7`!gWqsBI{SJjj+%ZpjQRD6TvCZIfc>9}aa0NPkn$1C!^3p2?I!7Eh8iZG1I` z(QO{?6pomL`-({r)`r%_tiDou1bMtNhhPPUSs(viZVpo*#38!P>4UTs*gSiT)Nff=si|#kacge+VzRzP zhaC;o&ngUf4TrH*ENJy9CYGbl!@T^}-1G{sBnUa|NdZsN*O>x7MDB)eqh?~7e-Y=B z3J&XRS*A6jLfraI38-tE6Jp;E`7`6nfLT?Xk23!b;HFP7;YcPZ+4 zu3l@P?8i%6=-TI*?}IeaqS5Fn#J1CK^Bz$6`w_K;acQsG??gmjHGuLw(EiTqQt)i( z1IJu){%mh&c%|La)Ksu-&{bj7yq)zBJ_lstIo=i zGKNi210#LQ5JsbC zDVrHzry35C zoz}%fM1c3^FOF1lI+~38nwXFMnVcq<`N^z?O2oVUvpxg~N=ppv8F%hl5j!Wsb33gw z@qi0AWE1acka^B49Z#T%>nj;>^9GT~+_ZAw5f?w&B-2*U_%Dxu#6XtFig)?bI9Cl` z?UO8zbxogP?!o7pAKcjU+7$vx968Z z>Cq_Hn!y0}Hz#CKY4gP?7HzA_L2~2t3N|%W!6ju6mOGDI>v@FXlf%E#kqC$3tNr=sV~8MAZBAkblxR-M3rQ&}{j~ zfub`c` zJ-YN~*`p-HX!cDO5*cGF#FA4rf2vVJa!Mf@l`|pu&YIBece!{|(_W}Xd>-j=qWBNu zQW~DN`K`I$zx8$|VYhYwZK0@yYW~JIN?x@n-t=5D@K@tKpjP^*R72 zX_Gy;3|b4TQf)y89}*+JG0x#i488=*y;peOb^_Bp4UjtDknq^MEFD&qSm=dhf|AlL zzz~5iung@~G42_queJ;0^1XoVg*3B9v(dE{I>Y+F!{O0vW|chMtx3`Yz7+x)D*QhU zz!?b`Uwt5|MWJGei!L$JlWmV&awKdEn9J8B2R1}Lbizt5WTg3PypDBVP4aVZb!4<(L-7$!e?E5U{5Mxw z^Ls-4+=j}o(qi@4wh+s+6G)$swZr&WN!kx2?#z~)6r~GYFDI>ceUh}c*2B5~F~!K* z2*McDq%=IJhCXvso{VxiVy`{pM$5;0FFRo|1O*{?BTxTq>cz%hmMV`NoR!Ec@}Ry( zRQ6hUQj(iLxsWfc?3a=zGeU3te@D}<4O=Qr+)`DfznM)=RWg73Le9LHqyd{JzbiZ_ zjP>lH-9VJJPowZMEFA`8f3t`w{D{IP zD2Wv)r&jg~Q-&|7KHlar((xM85++RtVbKWP>9qiZ+z6?@-05we0bbRf7lS4DH&~mt6nrQ%w zs+ImosFL^o+=9C4oRQH(4F({l1=%1Gy{z=_y+nh<+AC@FP%IVgaw8HUEF*V!4o$GL z(2ONoAeU*zbdf+7La4P6LV?tHS3q7feK2y4m6{y4myD~MVZ}dI7qEvA<{8g4lfyg5 zL(U*X9Vz_FsbCl1NWVbofx0u5oE*9{-kk;_S^-pbmVU;)4dq>O1YEUudOd)k0&y;nR`smfF5o zSk=sACHTqM&_=1DoEWw1rr9dv8or~wkH_Agp*4$`7Swyo51p)i{shtP9j70D@j8iT z8j0xf3E+Glr}CgJ#d*cItZmYBco>OGmj3;n$+Qnjiu5fz(n*0{YdsTS`A?e z-Lo9Htg;EvfPd;4ccUidR%&r;03HueYz*r-*31!uIAt7#S_C^z7|?t4o}%&HG&js* zE(#S>BZ>9@+uwR*m|BZnkxyU027(*HlRA2i)+Pd5gBd9f2OsE31=kp^H$CITN!OIo z$srOBH*5oT$g8c!S45|srLl=q{+$+KPTuOqHt{9n{C#ZOe(V`Qw|{K)`9Jm9-)yZj z@cVW+PQc&hp{#d(WlUKJ(hIaH{Ca%`cpJYppb`1%Md2o3iMGVv|9=UvyV=rJKtP$J zrG>EwX~}WxD`%bQ{OYzkN)6Dag)W=^`+;ij;dD61yo)w}gl~_LF}^`FvWZ|6j&^QG z?sD6Gw@{`Nx1VxbEv%#&>z%PHjXE3BYN6@>H8>IW1Lp{8T|3Z@K$pVc%XiOo1{$-*HC@g~PCKB-{?4h#6zV9#z?=ZF z#2+9}Brbhg1E!O{d6v*~h3faG(^C{gaOz&=4fR(FsHA_2`X0LI+0<3u*R1E-PZuS& znUtsPpNQ$G$P*`FJ>=2}3kgMw)|YyboOm##%|)}j#zBtDnZ+KZF}{hNz0?NMck?pr zS6Kb5!4J%5K3yymdu1N*x-Xm_yA&$E1DT8$IQ2cHMKrgtM~(Ipd9}x-b;a;VVsFOd zi2Ed&(Xl<%>(ge%!6EJ+r}I+N!|D=#Uf}m5=pV1hEOlko6uED0U~rXiFeZ%NVJm%^ z(a_{;!i0af7&XnaxA>1ITHc>x29iK3_#cFhMcS$zh}Nr4lfSZD5DF4JV$Shw-<5mz@ThuPwA^YdGK3JtZTO<1f&g8UJ+q&NrL!i-f+4102od zlM=)!l)V0f5Xb{tib>2IeK2jrl zuy4j`gx?M2)zD&3%&1XIEy76Rprw)s@{R4^!0bex(Tt5LtW%%c^+hF>NC6G9Ma=WF zpO7@b`T2nv?d>1f{L*INo(F4mH#wy! z&y=V-NGq##VDiXKjB1rZ3>SyY!EJk)fjhU(GP-$1HV(Gyd1 zlm(r4qluk7@`mqW9(|~{vM_$^XzehJx~8RWZ`CPS?%81}EUFT7$Q}MqzSYprR7wOf``m;qGJcIlEk@mB?eQ|Pis`Q2M{Q*t>-FSmoCpQc4#~mfH!v5?+ zFUh=1O2bii$+HOVu`N=Q0J8AVZP`UD;FQ=q)bvOTMK?Wmk<+1o)UZ*F$M`RF<8!`j zUE@q`%6p(m&4B`@R$#;F?+bR*h2{$+E<_3&fNAx>Toc(}%tRAE+*=}CU*^N$gCe=6 zmlXeKyf-mn(bk3tGK*Fa4r0oWhe1W5F@z=Rn3eI``QP#TtOx(hGpc zogSu1mv~HEXN53@VG?{M7JXE54@hf`#5?z&T69v1lGBvidTz;qzem6En=BlCuKwP0 zBo&~s`9;-8$OAb{zXtD+{b;A1p}-_*vgK(;hnz73;KPD91g``8czj3Y9rkf3BulO= zbt^eUmJWDKuKLT6j+PNo0c3Fj-`pP_=&yEyh@!(eD%e2FV{r*kb!-Z8rm*y|GG#V zGh+xhlDUCCP5i(oZ2sG;%Lze|--_HGrdaz+5vrsI$DLP%$gB@5{HakaCD6%nIYtUE zYmZu7!=eQ8JIi_4{V-kGl+^RFC&;tCU8rYouqU?itwOkU~$WT3BADfp8y2$}cumPz*$L zl5N!#sisV;h<=S{4i1!Lyxs~B5CE?Tw|{O@X`hyQyI`0mSUPuFFvOInY3buhl|FF)bwDm>7i5%oS{xaLRP z$8$te|Hsnpz7U+8lU@dj)nt(dp)+$yUpNAG1$?gmp!m#j8O4IEE9A5Aw1&#PQuDGcID2w{%e1r{){z_?tMbqKgcygXLwV6i z#w#KA$k>EbY}nC(Y|Y!i->QX6Rt5+f0Xbprk}HAWLL&?F-{)jVE#QwKlGiZN_D7yu zb&)k>J|nNJTpo!w8f}XYP(Ff{?lRAvx5IQLDSkRjzwu+95k5h)Iv6!i0$vn=0SCntevgT#=!Zqx3Tccc% zIlfq~or_D7XUzzh;CNLgItG; zgn5`)$~U%aUuhgj`CFvKPJI>O)X;COFFQ0{7n4I;@+dudiu%Gz*wBE{r2QVaWx($q zP(MsfIA1Kg#j=I#T0`>A*1Z_Zw@lJ`a#qG1GSV2&;O}vZp;$mNy7?J3Zpq?7Cg;_3 zHZpeN%=$A*np7bb*&SIFP%m3=R$=4;6j=H2KTaOKza0_=P(4GHe>C&dn6x*Lj{0R; z@YK(CP>D&_VgP%~jP1NO)(-(&f@VHysJt8LI?Q!rrty%VKNWebb&jF1e+_(L3KVuo zJy`aDf5)5|6DWi>8)Iw^H<_P?5nBh;g+(B`d;`E0jM_&`nQnF;70;wfu6EOl%ir8^ zps>SxeD43m?DmC#;F5{DXVibmqd3h#;^9e%BD5Z79%P!;{M`kP&h+A+TJ*aqjGfa$ zwTp;9iXXler_l74y@nW19syS0lH1gmE~#o6tFxUa2I{e7R})UwGYWsG>jYVJH#sGkN^GXXDf zCb(+qDKXOT<;|3I;o#?58m*=U>4z+hMTSH@1d8VYk+&c(EiDOE!6Rc`o;^q~?f0d9 z1Oy+CHi9Z>?#FR*^4y3^x!)gRFcQ$wOtjszc=?7%+Gqym1bQNj@3NVDq^Wlq*kr!gm9Uu&$dddFmeOzp|`sGa+I9t z3Uv>Dt!QM(6mA7i8)(A+#k0R0y4SxAeblhf@j@u=A(pKO?$`cX%Z#2;zWI&!W%3U? zkpB|KNiTw3q&Xxw^+FEN2g|PpAQ6~>7LSK{o=QzKlr-OTV4g~cmt7>LiqD``tk`N0 z#M-B0-)CP>5YTd8k2>_kpB^#*txbizR+(BEbMj%&UzP@cuh82P!UT-$D*ENlE^8re zb+L3XQ<=BwiK?-2(uBMBinE*0VkapA=rofwp3N?vPPu{(;*9jhvao*j?PBSs;9V5E z3nyIkU+iD9RIvufy-Ad17s2tNickY-G|&=ChSi-yOy-iOiUgvpXl==2Q0*tndAkSYwxI@-D8kb6QqGFmK>VAXxxx|LL})j%@4{P8uq_oUTq9 zXtb)qpjyLWhn0j)))O=Q&_J-Y`Wxi+Qhoa}_bGt{{I~0`t@Uf#4&CT9^Rjl90DN&t zp6?651_#rw4L+-IY7q0n8E?#ceBX#TB<@B9COcS2Cx@)iNPKdRHW6rdy^glCC73SXFX27bJ zm!D;y0Q=lNmD11}4qeV6nW&{5SsS_C5u-y%hi^Lv^TDd1Pq*MxTZ*mDvx8SU5mR1I z zn4;xku_sL0Hu}OJE+p#-CbQ%Eou=@%4RPdQg+t|2-PPaA(gRfDNxVmi>_r zovtr0Caztx;V?&g9{roUHiAH3Mse7qM*`t4PPvvYqaLhjuf0z8Y=u}vdt(Wh-gJ)h zBjPb!I3y!qb|e-C#)P8^+{ym2->a4b)nvz4ES886-A|pxZI3CccSyn!z%@LFhtn0V zN%uMqW6+YO@IwU12u8f+Z|+pf3a_2=kWJ06d`7@=a3 zgqf&GJav9_7}Fa>hBDq7V0BsDGk#)R)skU-_YTCB7r3@zs!HOtxDM?9RdN;xDb3Le zE~DbAiUT7<)k#&BFt^668=)<;pNz=j&h=6upL#bdR9%>wnXgXp`8&98a$8Xnajz%sS_UA%B|x8o?4Z zJTLiPl)sn!Oq*-U1I^C?9Mrep4&8|s#n}^Iu`5JnXO=ctK}CDK4KWyb+0kR5g4cO; z=&B)pDLpF_9NO9layEV*0wa2UY2p*Y7+BYR*|5s2=&c{n6HtE{Xvo-ZABF4ZF+qzvA2jF=n{PgjQaydDaa$CF? zljt2yZs2mcpnBEZm&8Z{5`BBFPi4HQY9Yl=uO94lzQHx~W%(yFXhy^wlxQ-Ll!|{v z1iDwFH>ygbBdwDQ8OTu8S^SVe%$(;Dn1 z4m>BUvyNStW=S0DCwg@}n&OIwcvf2LwUrB@yl!%*W=rC=YL3f*Z$_m+Q$N4A65)=SQtelO1}$V-8IlP?E5!-e6V zd>z>INsn;)s;iPV7yv(ah=o&-WZ=auq`vt7hC4Hq9SXrES`^|YFVB~MT{YA6!2mW- z7&{~_2qDf!!sfscyb5iU4p}Ye_uWJ>q6=EmJW zBi0$uCFb}Sw8r04Mn5J@Xs?;@89@@g5LNU7%rWhtZpYm#`TAL>0yw_1X3#;bxbe#1%((+bt8Y=Z`zOh_ zuue7};*Oc3udl99whOFLh@9bOkS?qXiisTv#=hpgo-lB60WdZ0l>^ztWy~tVVIRaK z=|R6boYnwkv61gwH%U_X#n&n&40Ay0_vrBbU>w{#M~>~Tp#M0R%Dd(g&|lr1cSP+@$6P!8kK}9Xfwq4hPl*lm=uXex-8%oAHLxwbu_%UBKa&QdRAvIf=? zeNg2eCovsg{XO{)3mkwiu_lxxgJ*JVzddMa-f7$gFJO#5E0c%)Q72s6E%8SjfHbgs zeg8gADa5qgmOEi=oj=xlyz=x_(cZjd#TJa!DHH)wOobXP+W#ap4$`^tZ8 zpN2{vD;^z`FsDtkR44R>+EndYs1^Z;{>+HMn7CeoAeDNUqjKi{ zpI}KNjPrRx!q*qI2a$eax)6b+Ll3fUeme3rX!H^_N5fEnzIN0|8nw zX--z|cvSm(xA2H7ug=YAC?3QQc>vTvFKQj5TUrBsDVVKN$E_nS_ zs4~HHLDMe4kB(&bVj=D;ddQJqj zv&uOenK{`5F0HW^7?&tcQxn~!>0#pu^rSx|WyE!-hMlsA>8g$ZQRO4B?wr2{J%7 zecSqF_T8O3^lnD1`GAA=pddh)k^3}>Td6QJxNcm-g+l;b-0uLkZ-8sdGa+`~F@`#5 z?Y^*Zth7DFGokRMEPVCbNht@^yEu8ABkz@iYDD0RtryQow9NXz4 z#7b(t5*HJL?3s0~5t0dWGL~YOrx`v1N zwZwb4tYQR(!PE-0eDm0zgZKk;&3o{K2mzVW2sfB}KCc3Nqr}M#J)|3R#MN8fk-FRC zf1BcXD_0lf%fWTK&L|7zHjh)jW41ox)VJu3D55Dp)h!^k0Ra8ua7RmWgjD8>uWKSB z9Z86fgg)7fhJ#f5VPNZYw1-MG3OB{}c0m>FQ>9hQ>5QkVR94z86Hdt~Cd`w0yVbbt zl;Bj8GVFQ^D{75il+@U*o{7yvNShLAwR1!xb}{u`VtTJF?n36WOUin6vL3+2=B>D^ zn)mfKb7%?u_JBE3J55CLVtI%%;UfNiJh)@s>Z;j@+26s|oFR~h`CEtLdZRS_RLqC@ zyH19wVE3yj@!Te18}K&Gb?e<CQGdCr-{`WLg|BLQb4 zPoxnw5BNt{2Ie1Z`>Z4I(~lYTF&)$_%Q~B}r}(2MC~UCb{?sd_@7~+j>Yh{p_<%A* z&z#z7YTkOH;xWp3Hj~7QUnW?or$>G{4|;I-`|Gz2_jn$JRQc!DCR#FI=JhK=ac@y^ z*{LX}WIUkElTu!6d-U#2nSk5G9i)9sU!s=<@&@gGUbL-0_e`ku=bnr1V~!@`ixX7h zzzAtj$j5|;Xh0|j71*oZsmn%A_3-5G-!Yvei5*3<29)#Y-s;;h0X<=@Yuoj!kVm!@ zQJX3@;PKjKIBEwT)2(b6Rt1aY;xgm*8UBAvqzU!=w;)OSh3dcDj?EV^!P)QEZw%W*&4`k^E4 z)%MV0N_G1^AC98vIuGtNZ?Oh*6&# zO2UrW^@dTX{q%&zY;cnQvj?BYOERZSaa3@Gna2wN$&|GyyA@Yie#@nzmU7H{1yCNI zh{3~^RJbfQ)tvxFXRzSv`G*jV&xfZzoc9FY{YO9nUZ|AT(g$8c1QUwx-K2|gnSE=8 z9AYKmlxqmDmQec?Ls4zRnU*n`iJlv}f`{Bl?DQ zujBj+!l|LvQHSEn;{746X=r5zPpD+39`=_eD^N%)KquLZS!Al;C}I1UI^pOc#hY|# zl0|W!p~4U0bTLuWD|yNK7`Xk3eZfi}UaQAZy!8i6S=*FuDJF#NkO(HvyZ->942{=P zDD{)>@x;D>2@uxgu#gnLt^i~cYaK29iXBUCvK@Y9^h6GQO5ijsRzJaU*(l3dR*D0X@rAzlLf_49aK&Us>UpNl-zqk2w8*GG2ctEiiUW#8r4Gg&EB zHGgU@1b*Hx!f#fm#*nP*6ZXBj!(qGho74(^_*VlC^aOZU{|KTy z@f#%}VCEmUuBp_p8qPj=krYHxZWg!)tUnkGzUQ4Lt0rAK!0!tozHO>iSBl` zZ*Q2LV2kZ1#A5~B?fE&ej zb#jEjYiHmDqj|bT-BG+F`{L90v$L7V3RnBMCl~KMWg6I%hFPjSzLtic;e*99@zXzY zX0x;3l1AlG@{un(=i=wSCu!x|TiuK7S}o51_~0<&zfH6sTvm~!oNvJegc~oH@)S)g z2mRLa+Vk>Ie`goAN;9^p{&N2~G)%?)aqfJhupDaupO)fF`Jrv;MID2OBAl}9&Y_>#l_69?o zo9k_+E{hFiId*S)ug&kngAPEOHMA*7J>f?!oI6za3WtXoHsBnC<`uk<*CY3xutp`w zK%9UOv@j0N1}HcsK1a;GT3zZkvSQxp)nvfgU!Hg=HIycZb3^wtSdT-4@q*Evw!~e{0nXO+*^0Bz=7xP)vKZ>!dt0J-WIFt z-FG8mMn`jhIIr`kdh=5fh$m49+-x#ry|>WMrJ*IplL{J~-<#g1jMoeYGM;B4Uz6%o z`Q(YBFn%fLePYak#Hf(#TTeZoqZ%19>0!W3aME1OSa6FmebyF@94gFZ#UJe2&! zaEBK*ooM+auQYrt(vmDPd^J3FMPM5z4VHeKA6F>@$wTwb$MiYRvbVd}oY9PH>b*0c zRvZ@GQs)C$#&CC`r^}S6=1xOhA+Xotl{7-2d#}kay^8xM_E(1 zQ39L9v!wTJ(!QT{vOf1(5=&SR__(QKswdf@l+Wib-pP7apg2C{;`YUpZT!U`X9`$z zb(D${BD|MxFl+0FKs|L5X^OF-8r)V%WaqrxahLSa=T-t_V|o(0wyGp8bruB$O$gF9 z`*IX~8)Q5zDThw18f{B8;%|EN4slS9n08r8ZJp0HxH|3L=s#VE`CU*OX#E!yZlYG- zx~(2wZJ@g$@GxWE*1_B&@=xU;-z&n1ucPYtlw1yx?0jdLxg-Ne%$XC`c@yb)+K)A; z5BxfsMNG>l*c%KfX5{5J&Bu9DnV3kOlqv9ck>7n z{uBrz`li882@0;>h%OMgg48&dE1OUR#6ibeABL{QQBdQ0l2Fv5(`3l}IoMlurwSby znl7JwhZCt5Y2S&b=fN*ZHm-?J!lD;A1;@)6Fhv9WEm97vHbPI{Dsq_e2Fb8Y#L>}k zhRHmhr)cVlOgP^&kf{jgs-6+!>Y}0=Zh`Lng<>XcNki7f1T+CV&ta>nkJqut(1;kM zF1YA$d&3g48{Sc=fdw?YyMb`*B6S?DNo&>zZcUUMRj4)He?Z+Pv0`T-luApffQVdW z(w@B@!QXZ9}ixioWwGQ@PeRCgyvs+S(lUH_S$zctW#>jmwHhLnRuna$S zJ&)Qgb}*rjiOYN0mf%C-xSf&hSOXK{^4iU*&KTr@;c`shdbFB-y<@(EB7?-afIp+o^tqgNN*?70jGHr&(IeU-FM6SHr$B zbEV-;`u-OjRje>HWb@R_@HpmR>JB!YJ}TTwkw;mxRoMT)On+1ccv zk6_&sta)F*kni(T=&Bd2hj$ZNI7yPEvM3Q=8|mE?RI*(fNo3&U8u7U4Y7ZC_ZR?gcM<$pHOv0J02tIX770sD23hPN5a(C9&FeL3Y zZh?;5P^719+BZ}T2hdZWb2x*!m=ifG&-5^5|BxBV!>C#o!t%2x zT#OF&)u-Dr>}m1p?H@tSDOX@|&YcVqLS|sMBk#h;e(Qm0VhdYQhMRphR1jgSmO)Z_5=;60=b?oA{N=iM|9=GV#VMc&Q_L7F)ybrU z90axy`8;1MlN@_phm}L z7k~WMliG&}T`3J|v!stF9W7Rx;KZc9qB$e6Fx(<%#gf(+(Vz}$al3ZP&uKeJ8-;ej z_DZGCU-D{u!tx6`6nfHbj%_I4bbotEB~i2&QnW+sX8S4I_q1k%*#46*^+sUfz(aJ- znXvr8iDOn^#PpY~*DlgIIrgv<(Re+W)e$tO@#*Cx@Y9gRtE@a}^jMLp(}uk>mZEvQ z@OIG!3RGR#p^wGv{T^)&x^U2o^}9HN6+UE-;yB@}&js?l-Q2apa?NSE=1FwsFh8>(KCH`q%}gVM%_lhnq**V@VKSLrl@ zIUtJ)x{EMFz|^5#{%_p^ABnql*XoFa$`>FVRw@+I0@|B*scKKzlU6%Yj~^1a%r(4A z`Q9o4Z9484QREvUZs5L;jiIVc9Od|PBZ0=WgLtEdmvzOBXqc?=MdpB%6+Qfona3{q z`RV&Gl(|##(h97Rr^#plP2_D>Qm_}(g-|(6w)$CnwtmJgN0^Lej$ww{4shHLhlc$1 z05G{d@~Pde2`4M(<-O<`A=-q+z`n?$&GW;B&0h%#bb3-n|C(Vkycn(T5FG3+T^=?| z;)UM5HDhn-cAxz#2V=rSuM5#MT--NWGeI}&oiil|TnrL^0XZ2U$5_s)$)X%NC04)H zE*zXqJUPYq2;%@?telynB~3jgHO~V~m%>2++t5`N{4Weg`J=l@Xi<-qK(FZqqr@lt zg+#;m(${5AVGT76K$~KX330;S0)c?Aq1#;AB2}q?O63;s*t!nep{#xF1IOFb4S~d0 zRowm`70BaMJ?Hs`+;iG=swGqWZ%~51q)mcPSJqt3-Xd3&*m8)7T@jv4bIRWC1xA_R z!)%WoSw)>1cw97&^hsJLA9A;Z&ARaUN}!p?F6-2oZQg2awO=ktanAOxzc^YxV%~hDkn>x(GN`CBA5sKir|^#14O|1iffEAcbF}Q^rY>GIX&P3 z!wqu#_KUlRd21ywY2NE4Ft6XYNqZ;tT!(=s_FFkKL;gkxv!H&EzEwPYqcz>_{FsZ@ zh;5KCj==qATytg$+++_H0HM-re`@kqm@cw{=ETJ@r^opRwSl6&a2nUeE_Q}cUMSf= zMy1VGszpS=60cog4p{B;+mFLTa(_DgVvUartwcbqfd*&bM+5ez5-12;`kcw)U}+HY?{@DBNdq zcoq0Vm;HML(DQ97tXGn||F_beup!vPQXSN=a3GhQC;Rj=OxEaU1wNs!W^=0^y$ zZ&zXzZ8Pndm~~OKZ%B95T4T5IBfgmKKWMe?buz#2EYN1|25O#a^m46rbi>5{E@+ug zI(K|uLU(m)h(N%1bvK!FcR+*)w}}RIxN;V@L*OMeH*qhhM#`m&8%9f-4*mr_T|m zuLx>h8lB6)`uzl0J`qWKIX}#!ygfF?g`#3U2(uOoC3Q_Z)6h1&iG=sab}06fPs0G? z)RxX@L_fJ>D6nqnb4-H>E@B`iL4>VwkjDAaKx>3D*cfTP=u}an{v^rkTFl{P*|#hD zhG=C{kUEDmm%6@t2`p-6Wj)^`^9ol|;jRa6nAmuUTGKd?qscn*1(68d3h8Rr}LZKd;EGvOQs&b%uG@+RF;A5O&$-_MBPkyW4f5y#f<$js+GmyN z#F}g5C~CMAr+*T1jGrQ>xTfJ7MO20q{;w^wBd*7SG$D12=x~ED3@tFGI3g~r!;MR^ zZ|fs`Fqwdtr{%d}oai=qMp{wGG5sSLvEBB8b`i&U5|Wzf5RsLN+DyZ9*UZr%o_f$5 z@Z40HzD}|L>gGdlRCuX zJWBc?S-GPrN{{j7SxKJbIE!K%-ZX6+Ix+Xn#c4JP(f_x0vQQ^0 z`gN3fVy&JPHpKpDzV@v`cJV?x00HxVf6WKBAv5e96mi{)D)=lmWktzMA(Zwex6>~N zI0SoD15y#WcgecqVr)Ayn?q&Iv4gF^gBS*96EeBL@d!B=tYh-YDtf$s%*;Ad47^*q z#`&U^Z}m={7nb<3g0>p&Vr;R4Y2?iVSv@2|pf*b}572`ox9D#5i#xy6LF;0dEwT8P zc*pJk$9eag`KSb}lx^;@7kojL>Pqu6awQ{i6aI5r)Nlk#5I66;8-Pikv}+nNxKNDD zqHxim4;q|wB$gX;@NdR4TO7lyY(DO=9`pZ7zu{0m!A$^h@3bT-<)4Bb3gG0${`>w% z?wMUTmBSDC6OT?e>KKFnkJ2UAq%Sb_+V!d$IPo#ad7U=_1YQ$d|G$)toYr3mw4tRo zf1#B#-C9-_8}Daox96hUxA6ABm;CO7GYUHn+9U{j_k z-ly|l$btV-`?xOOgjM9;)y4l#P8YK=sX@`StpE~o)KmS$F%55eDjzb?q~k6$7AIYr6u)ZzNJLA zxVtH8MNUsIHgU^AHTWWXpVI@@b%>gKMQaAq6z_kF@!UoxqIq z>F5T+9~49IG%WzV5L`WpAvC=81CJid-0tOR0HvCYLMB7w=Hhb7?u%uCU9WBBPVIWSi4Gpi zx&2DnmPHgT1dj`>2=Q!sDM8b3FM^dvg;HTd2``P{1Oju&Nr)X8XWUf{MN6qCx4P9Z z`9|8oK}74I3MD?H+4YTfs5ZC*08&n^{=7zb@--<&}Pr^EIn9vU6?tyG$ZZno#RjT7}xr{o+^ zBn2$r@Xd?*6?2D06HeIhlk+qYWM~6&l-=-n3PV6RUt}74vB)|ajQMKH5bs{bA!K3O z5YUIg&M5olgA0Pc0&WP{ikX^Wq~7=@1#m?e{K=~1ylu(MRXH%4?817j|ta*Kbf07%f zWv^ZK4eZg&;`M^W0;WIH19CIgUM0>Z)N1|FcDblOdRP3Uq^IS`xyB~ROcR@PXh8FI zfY|(153`k5gxA|j?ubv$?aWB1P9E&$c!klAdxwS7ed?ka$ZAYG(SkFGjY&+uMrXkx(vt=~xBzJRC^uG5g|;qfywbj_t%=Af|Kaj_&u zEIQ-dmmj6k^;LvVjn(RnWO;`BzTm+n$Z0>6k=^N;*`!TheT~&RVaYS z%|}1Wv_P)umFlohzR%PjR4}z2yV)?I;>bL1?zWwjUNCV+cp%CA!)Y(R&sOO$jF03Pj_^QPTY>!}09N5)+24|_iS(_mW z(yijfb44`rd%~47;9+5xLnKJ@k1C$``YO8?IcF>7j8hA(28Z538HQQRA#$627ai-;LNjy3Rw%w_je1bBYTF z)}=79I=9c#01nmE7`G>xC4_Cr&LDmiA-cm)2m@A>m@Ri%!#gj5zI+wZT+!n6XpJ3YF70+=ux!hs&VBL;sC zX%o+XH_X3E?6Y0W0F#Y&Sm@lozR}eb#WeF6Lx|ilP49QfN#5K^+AjUy95~^osw=(p z4t~RlC&EeTyn&=efVGdK;rf`D|q z+`9IO38kU10SB`)P|H{@V~{~4O%l#!{gp-F)4vKuPwoD~2uJdq$9E|pbN4a@;zHV= z`OE7R^{x{+wQLqnT*Wy3i6y;j_Gz7p4^mLp2RsJ8C9;Aq8=WTz@CrFUQ1fc}?l$)b zM3qCU)*!yaM>W;fw3Vi*FL|#Jpi`<35Xt9EX%g`FK-jqdo9qwroaA>#6-WqLwNLH- zyKDX22%lY`0%c&^v-jU<%jtq=f+PR3M%&>PE(vv-Bs6J`^wLd+`(9b*P(>>s3g-;R zx#&+5XtqWr3)BEQQ7SEOCSLp!vdi_!2Q-fN2gyz5$ZQcZA`8Zq)>sK|lC9vm*(tyd zQ!@GUZ1bBTM7F=F&VL8A0N2yvDF-21!%yBp_tUR{uC&V`G{zT`X5+}XpNA^XkoEnK35@5EJHl#{Lyn0{U z<|h|ocx<)??Y?y;I1uD5sOE=nA8D@|?~nRs&Gm+0Whm&+r6Dh(mK6zIZ=Bn!sX{ug zmEeqn?U+VPT9X{S{suU->cY@ZuV%fR(9`Pos4UP`R^w2Oc*yI1EyCC$7#hJb%W1HG@aCcbSArTaM;H-%-EPeZ2F;)?t z)N_VmIRRgaXV#+dltvWeD>waT63S^3lzcAxq zT{DhY>b>Pv1ST<{lN>WAaOe5Rzhp=)v0Ds6#@{s)=dl3g>yHBXTSP`M5YhN1$D8RbR7L7_!W1q*@IZEc557X0WS15l#fZ@mT+|(RZInz zl)aVh){A4i!V|~zPqt%R5|+~84uP3ej8d5CWJJS{$%xX`alB&V&84_ID`* zs;5@6S2w5jrycVInRc6Yu1iUdIyCRf&gZ2)p;J+Ri-Y%VJ;1Ti(VF_Hk~(QHFiq8OgfZoDFyTIT0px-TohQYh@uJA?{=cp&@FMA6Avv_;2a#&+tHs15?`9Q;KqSQdy zSryDO-x+ud>nkZTx9=>E(#GLozsh&}K$TxB0wa}K;O~?u9red2pi!tn89T}&9Lo#= zcqek(PH_BH5&woaSjLuF5aigmW8lk%4|Xr~(9CjglCI@lvK~h~Ub;*HSGdU7lnx47 ztnkR6k7Jr;xekI$rVRBJBhj>O`<=(NQfNR5BziG@B5cde{Gvl3*oGRmgS{gVhQewn z;j+`FWx66H0SNY;;KvNx=lBUDQlhO5;>2Z@o?2(75|nz)DQL@zr$B%O4r~1n>fdWH z1K>^hIz$%iy!^eE`Yq**8#sp!S2O&TCC!a`3NSy*{3j}WmRzX>j-vwHpbd@pR=23x zdl-Wp8c-=cfdGvz~DnJ%8D@8>$1e?3i3fv@>!(yw10DB|(|vSH4CC z)ncO$xAaNA<{BeIP~Eq#8E6&cB^#36Xq92ol8ad7zD>2_d(e?-Ob%J41E!UD#dY$k zQ)kN#K1U@$Cu+voe-ic+sWn^PwnESv56`{` zsi84Pz0S@HwJq+$sjt~?jpzq>^U^~8HscEZ_F+|Kv2h-0-rXtp7EBxrAW zGoryldLnV~y4}2u01EBYqFs+%AY=fLS*X4rE*F)Y9YP_w7$bvUMDLW=vvD`$WtVHA zsf}sOW4=RNe$US&?3ac153N675fpkFSZHIq7@e)J6ciFRD!BAG&- z+fft7)}4y6ew+a39WFgJn+E7{ll2Ci;%@a_SNUB?Y;3h-53bs5szU4D@+xI~j!l|) zFdnKgWwCDt6R-KN{J#abOl+Min3xAO5FQWj1s=bucOMU1j+K^r^+Ei#WoBYc`y+E` z_$PkSuWOy!0QEOD>x=n`=ZO*PV4dWLQ&c$k(OUNlrm4V}o%o zCvVJF0hr*o#4flnh>n{PhK#R>uCT&uqQoNhV971=W(DwIQ(@==jZXZU<4o9VO5Kqm z%i#c7;Z5|$^|l1c|C41?ZoV$({SEfUD)1(qFyo|1u+|2Cqk}92|gK=^A?THvZN@ot4B{l@b1PkV0_%d)P&hsT=DR{~ro@swEqFJxX{XxCx z+Ghy$OLzj)=`w949dvShyaw!(+ZWf-;9<6q`;Ik7h%`~xK*gC{;)l$E-zf9j z(ce7`bqS5FE-LDrm)Kjf$gWrvX=6K=)K)gLAZaJiEqmR5aM^g+*Wy6gsK=n#EWU^n z7WxLaFcBuqk>!ra2}?8e?b|welh1Q_1=&Vm%(P&zYU^x^4 zyS?v(!ezB~qaByrkOh#9wDYLi2(V4axV43i@|l>`RT@zHRY!W4evH}E`#rkeF>JP& zm;*XPkotG_NsPvrjnk1nW->JjU+%u~+%1#q@4+G+n+9&>_16+8pAuj8K?kxxBG4w2 zsSzS@O(tdhmNJy~;+hsDnO13`{L{&of@iohyiSvvRkbB`)@Y7LqXf9~Z!Dje*Nx|D z1SF>UW?M>Z+@EoE+}AG2_Wnh`U;wQW^?!p-L<_5?Sy<^`@zX%5(r1egFbCBOmp-9556J#peREFGleK0%Xd6ItanS9A&EQ7m^B=3r z4cp^WLuS~U%L+MypG~ zBCqE`oxQ*W&@BePOP(-zUs)+JrlV%ahHJgG6{PQJRuBt!IP9jjc)s+X-HD z?#Ne@{?DWv)~hg!5FHzy7+PJ^5IiHMLoS73^T|*$TBoiMLawq70Do3zo%)dH6GGGF zXhxK53HVLlHT^clRMef2(FiEjwYklw-WE-n-`GFi=@B;L@>Iq8lkM;YkmMpy zniZYM{!5)en&|6Y`BJtmvXl-7anZnaKeUG;PPbm~Z8rQ!i)zyGfffe|M1cYuNMrU} z7Xw5MzCnO`Juc@=Cbx8WIJi#0H`6}dW#tSF85CAmiiBER^puS&W9@Bt0&7ICE3@U{)3@LMiN@Q%?nGT$B9) zJk?Cw+p8JqnYGUB+bURz5_BxNN~{fmn)^>+L4huj`3%o72J5~~wa;i=OWB_=cD7lA z>vw>kV0z-?OrcC1m>ETfy;m1q+P8JG=C0U1oavYVqn@e>ox72?1YnlcNdI&KVUfj) zb^?i=bMil;kDH9VULD=@I-Mwekn@a)knbd|p~VdKM#P0Q4j(5OeZ#`9)BICFQDpZ+ zUM51bwpb771YbKg3&!+FRVz10BmTj%tOa^&P;Zq0=T0eALki;Bt9%R>J5NKDb31L9 zl6-)N@57`%_2xL=f7unbGb|TE?Omh`z`pmeLK3?)K;S$oEIBTr)}4e>0aYjd}7>5CX%*8KC$1{TvgOc^y=(#r{*vhYuH_HX?2;Rn zQljqn)vgHwlOUKEb%9@WCw0mNzAR5nv;X{bXz9+!;}IGvT!MTV zcN&QLHw<@*azJp}gW$8Y!)Ep2aLkI=q=ShE$w&FY16PGF&2H1QRQ^S3=^C4BapDZ^ zEd!8JhWwkTI*IPP2Mz2xC;ST#10~SBf4y?=$-m?}NAo5gY^mYoxqG7C%=@k;EYm66 zO^k}IGGJj4wA_fZf9cG{&AiEqx?0*SVYUd@8mF6J;IZ8$$FN66EO4~$jd>Z}*|`_Z z78r70wu5t{rT+gsPjE{5<_lVEy1U%`K@Tq2>E7yGz>$;UFkdo&KGVpMq=Y0sMN6P1 zP|+V9*>JrSO;N`@(MfyYEVuRbg#n?PFY6XQsqmeneVDSH@^zEaSL z$Lz|mxFg^0qj(X^uOj$p`NJ@Kx$OyMjb`2(I^6JH+N@kc9AI$3!<-z?>b_)@FhJTT zi{-XCed016d$U^rX^7|rhSf_MRsYj`d8npbG$AV%V0>0Eq+Vtua+nrp1JemBn;1%A zI|G3)AIeX8hmzjrGh^kqrSV^u5f(@?Z@R3Mbk1p2amhMmd`_bC-4I5ze%R}EqSEiQ zN+0^oi@7}8ttIUT5k$d3mHj!V0|+n?r2+7hxJ@;{0mp|T@Nf%~JWTo-r#FxEMe6nF zS^XnIZ@*-T1tX)LihlFEX7;*1zxzzRU)R2?9jAa(|54Zk{;$syKwMt&!Agw1=yLFE z_^!WhUEKO^BK;8r;sd%3qZ~SXZgC#( zxBxRi%)f1EX{A%_-q;mh+M9%?&erl=9LE7kH_Bf?ksPB4_@atCWk=ix?W%H8 zt#svJN*~)dNq4E)ZLh|M{6_&izyO6{rh9|_sTOm~J4u>CnC{=Z==cq3v{n-wFr@Tn zn1IDzokSjLiYDxCGvROvB4FzNp3)t<(TD!ht!sT?hdWT3E7wbQ0ie6?1Z^GV5oefJ zV6$p&x-9v?AM5CBVoPNb*k3r~)!xT%3MrI_2nP4`eeX?AONp-z9&yGtg&CE9?v@Ak zcA}-*f`<=@#@bp4(?A4Qzd)VPhV;5Wy%NB_VLO=x^+gwGh^J3*V7Xxm)4gcm^qEMK z9YoyA>ZMQ`b4$Dz>7ljmHT!>5}fjzkq zHT$XCL`I=4_ zwdjn)t&UWt1@V~XT$!^Pzlslx+KD19$CS-EtkTRhhREK)WsL|GXZ zp%Q?Asc`Z~yqC40Frz>XUSnI-?h^CO0uTv6T8ixG{jv}EZ0LoDFd6I2Z(W#x*4+t! zpbkluRo0`9C(Ku?(!;v@JH>us_^RPM$Jo$C&wErvH(s`>t*)3|E*_yTe<4*L#mnj> zNJrd`^7Dn2tElc1J&0+V)V1Om^=NxpI;K>>X+P5(t&h(N?~x*TCCc?q6#W)*-h-@U|y#!?I{=&i4T_*)6pL86S8#r9#|CJ2^Mq!bOAPY5GLsW2<{H z{kk>+-W`8p+qV@Uxt23z2E?>eD{V^_E}Y@P z0uUIqxa&!M0&}~OwdIcbqjMbF(SZJ`A{|oBkRfJNquCg}@CK3?pRDq_V?Q&5F z#BK!3ivDkZZf0Zl)JmXwlvhjg`46I+zN^OQ;oUQQPWwlTZ;lT{OmQJca*f0?kzMk> z^K;_P84m7;uP z7vnk&hZYOoU~7xVWH_X1A~RXq_f(p{OQb5{bwF^!IZ1}#NrYr6SE>Vqm5~oAtVDAozWi421lBq3rW0mad*l2_4oqKd{)el=uvifXLa1{I)6bf`p*NJ`)Ca3uqXv`N8=;JQwP#@A(7bCx&i|%TFK3h^EMcsESA{=F;ND{xbL_&n>~-KR_MJ;L1y#l zDvnR01ImKRMw~B2BNjgo73~qpWP?Z9MfDw!;tph-oEukEeC?ZrO81c zS=LtQE*u9VUu2oKXel+%g2$zmF-5l_ig8E!FEpsG7oOk;0=6=A-0X`wvwb>!Ar zH-~;=i=G4V+0vLBT^m9m0CE@I^+`QLH=~v^BURcC+BO z03BzUg#t(ShBOF`s1T!pu*RX$4pI0!Dj?z8b3)XXx4`OBUygVdNK`f?7{eHl$s18N zoO1a4nt-pUCDh>un!*L07m9fSV?fMz*6cuf^cGD$QWc5nb4TV<(@X69w?6h;ldSIH zAbzJ;88YIPjZQ`-dyuxI_g%=r+o>2np!)n%`}1wO&7XYuUo$+Ly`xx}<>B71Kz2xc zoDCHQx;c;9jM$60@J4-rGw)o54Hx4bM#fo9s_f*mx@S1O6Fj}HtDc1N1nuR|rl=wS z-#Y=Ra#=fxk+?LD43AQ-u$JmzmDGuxSyADeddWjWNWo!U!e8;0%X^H4HTa}AN=^eR zWNysG;yo($ru?o93S^wJF{OAeXgEzk*4r;`|)WQn%7RZUg*9s=-@CQZhP*_2d?CwtPz z!6tYYf?OwJ_1=6tH~GbYP8!f@T6clS^S=0dgi;T0gM zo#@3ypJOOvhc-u@K8s9R{I>398x9dNSPi$F8s_Gy&VT$;{a|ZxuQ9wPPDx7*;IU(m zJY*8{{w$L&QdJ3h$_s>MgS&yypCyBW0V*wj*f1*sm(nl7C7s5-d$rV=YP(922jp_X zb2bC4=#QiFo7%sPVNn=U=-vV}3yWapoAa1SUIKiN{*kl8?iOMp)D{+r5BD~3>?!iU zq9;#PWUGp7KD&7&eusXdG3LMLZT!7$!YUUO6K3V{QVYFOBq%0NJ^YwFP?x9>^{#R# zT#t}a!ss%r8~wjzK<RO972-uFWEzrviDS6y?o4!0FLM@2)_yIy#ryX&L12p z_|t_dbEPD8y&=!??Bq4C53Kcpa(!_F_Yl?VVC!WR;sL8nE!3M$-_V8b*MnnNPYje@ zE4ue{M4977ow7PXI=cd)8&-ttVtwP_=-OdQ5|2l4 zt={Vh@Z;XhUM>ZDLWv+(Y;~h{;R_J|^D_SipxIogS`g~SfQTn*7< znwd2G1(P6$1F9sB;(ix~q*7=B#;n#SM`YVv4*SRFbOu5-ktG^J!2uMTTtfgi>5-Sd zsO9~nP{ysaJn0VD@#WtQGdX(MxBm0msL}_x5;ynMfmJOHGmoy4>@o_G`bH!022*&O z>;O7!YHTP=2^te$FeDpnQKTTO)R&ny{RvQ1$JqbFgbyugrx!=$tI^{2tm=f#95$J; zvP#i^Y_z)zlO<^jC|=X>!ih!Toq@(~b#$Q?H$%D~>r(_OheA++M;j>+trkLj zg}tX*Fcg}1?R*uHoO_*b?6^MRaJe9;;2J#D<$;t_&(C%%#*lNkg1$7f9W+zpK-cYU zt7P|VVrn+USFPRwIXNtBMM|3>_b2Y8G!xty&7JFDv92^v76u=Pu!owdnYKgW{@U1P zp`z&+hp#T$bDDjX;q*k|sG8wt)V)W&j~0-DmG$35OCbXv)ZtD0y!kk3H!Ful+%YiU z`_(d3Ml)V)`;d^y^%koWg?0e@&8soE;|_%l1>QH}(~wUsu^qMHiJBGXUTRrB9N)q5Sgl5u=%)>Q1Kuvi+2RF)8O`sD``gnYz7fB)$ZhDgTq%RPgsG zDhghWkepqVHB32GA`pj?gsX}CI=eOv> zOABpou5m?`_4gX4mX`Cd@X-%a&wUtzF&BiO+hhBA>D5pREzK~=gQ&XV6`>U(Q(P#o zr-z0>a#F$ij3vn>GNu1;p0UP+o)VdNXOPaYKCpS+sAC8XLMvkOQ&3zTDryx zD(1&AN;kT-7clc1`^TO|Kvv4+4~VTG8ngN0_0XK5hdgdtO%fGBfH=h?=DDcsqAxtc zL$>@fuW5KQ=Ut<{8ZXoP^s?{K3h^2PRQttK@RLjCjLwEijKmiy3S?U`2?w0K^%u+YB{*VjX4}Q$Vv+&mc;?vH@2wa1kK2ESbO|>c4uP0r+rX z(a>Gg=S{86Z!c!h3#aA*HqzbvV5xIr-`5+)Xg0Z2*8 zMS--woAL9D+YRZEWeY&;@T1T6DlmPxcTj%|2w3y`NI@O{O<{k70_LJ4|U+N=`F;qV!TE<)_9!ogm!^Ny(%iiDu`=M zR-|a*_%K}E)1gn3+I!RH}?CNHXh#MS~%G{xE8UQ`3PUdm{>l_T^oKjsGYVu>IqAvS;u zBrwKfywM6MmFeruAqN^JFCp)+E^Y3v<`U^$4hTQK0LqGx*RJ(Gb@K;CV59llb*#G+ zR;X7uO9aYJ*dkY+>V;mg6T9%fG{GQABnOhjDo2#u;TT|dVt9o};Lr4Hl- zf3c^oRlTfnsY|W);|`>6eBv5)v7+m5Ve--Yy^}~*n}~~#offXiZO|NP@m9x1ObDLO z@dYMxoQ~^isT8m~?;!+Q2FFw&NO*7T-U~!Td*Gy?)9is1iM)7uh6GIC^ir>f#xn~r zSWH7NGGrQ{+*=P6A@7#Wc80SjV)7YyX?!cvCWM65evixHh%V~Z&4O~ zLb6}?A87+Du&hiLKJO|}8}Ug~J27sTMGdT5-wg|o(ctUSwy^iV*VXCkX~gQr9EBG- z)aq`9`6`Vj=syxIDoPgF_o)>G@rMWW#ecC~gmN%jT6D98dS9{ zcf|Cq_Rral8?-0A)HVRc`ouvkhdTt>Ju#k|0p3x;I)o-t1Vn zD98JT7!-JzY^lPyV4I(q^r}7HTJd)nAscH{Lt@RJ{M@Wd zniUXh`9q;1#XK6~amHmav6`(z6Z@JzYao8n`ZF$hBww|;`l6+;;69Pd(Rrz-T`IOk?a?xWrKR-+G&)~YcE`pQ-57p0wM)^K3aO|8`S)h+o8_x7l`e#Ddk z+{-E*TgiQZ9n1u`<(hNnnULB@vxG=>1l^N95U#|0OuvKX)K|sHA~y}hcNfrUaIFMr z`TTM8|3rWc4QU}RHK4BwHPx@Ys@(nxW1L^J9;AcTvrYP7M+w-YK&TfSJJhJO~5>_pa4Jxamlj3k6b0G*E7GqjpH z<-2ASZ>>;(9W}t&@~h&v?L{Ze)4+(b%1DAWrdogGY>e>3X@LI7^-l_;XPPLsRQ6Vu z2q4gr&>ygFeds~EQ(GBJM+*VXdHJ|n2xUefAx*Pl(nQrp!6imCF*0lVpH)zee`QT} zjs>@^wuh{_x?~^XKOJaMP{5J>7qZi>NfcN)tF8lKpptSFQ^f{?FILb@gHF_bcNlGao6dOe9LwSdDrpUSdJ;sph}V+atPg0VS&zr^00nM zA&x~ zl?biAp3ThT*lp4jYkwo<>KiK>wvQO zSnL1qSio2{wmG{}B%Vf@&M+Tog^8u9E z#j=gNwD?_|0`Q8O8i6Y87wWA7(_1$PwS%-nivxou(P}_$pmwwDol(tWK8OB$cV~fY zmN1iBF5xK+B5d)(!o8ZzGfIq3resMzItbSx+7$EJr|$oQf(BR0K0cnJXS4x!cXeY@ zDc|#zbqC-poQA327m4&?wT!dA?<`joM(m%(UVh8$R{*A4l9?n~jEFTSFAf$-Z@T(o z8P>x+m(IdxZdOyjH`5?7Jdp@rbO}?B>ER)u1c&fZ!hngdg#Y3R%%6|ZM z`1~N_76}X?A9ydt8$JpZ#n2D1z*k4iJQ*|`k?YNOqljlHGM|T`4dV^`3#o54C@0p! z?>jkz{Sq@iyWuuJ0^CO1Wqc|2{1vgyhfq|VAARCc zJJ9UK&}6@m3hxUcyucWv;u2k9aY=%FuAVi+{~6AWR}|kY|Bqfu93tB0s;<$~Q6iyu zf?)7NExl-r$({;oZDMKJ?!lGh{!`j{ML}!~+8&e^_m`P7znp}T6FEYhY{Pm@cD-Q8 zI}~~w-*IeJkGnrOv30R4*`U41;-}EA4y^CY;x~Vimr$3%_#_!prPc|IysG(j%a;~S zNuF!Yv2~Tv-~sf%*9X)Gl77H4M`W9d+Zc__{Qa1a%bJ9D=$DNZ0617KrFl++L)?)e zwU^65f~(d0m^e;UTwgoKF3(ITSs+UziZ>Pys{t8pEA-u#dxKhRT#n~2ib``1-M9o{ z92L&f4v;uwp93tz$xgT_+7_M_u>&}-pcDz|^VZiixgzqwf-62~fp?4%(GNm>nz61l znlbn?c}fv~ufQ*Fs;Djmd6gGPS5U_Y;SV?oFKNDh1N;dW=j>-$N|0DCw%_^)gmnM3+7lsFk1HX7d>pGFO!?T*r2>9GLe)gv>wR$6@3)|_RuusKVx(MQLsLn04)=AuqR`rU_F`57cHP^pl2x;l;kThOMdr!OsEevoS_(n>iuLqR_B za8O70`$YJbSI$&@{b9Iviaf7hy3iTJ`%YD0Gex5N70N(NQVJ;5VmS0r>pC`wU;rjj zajt-VN~_IwNkE;DCBih^6X%i0ndSrC+Kuc8*o+j|UPW{qS`3D%J|29~C6ShEQ@t?O zn;Ih7}9LZ$;#acRrR4B;N!4f(d;IEQ$Z=TwKzztIE!|v~E`Q z{9p;AD!gpN6-cYfz;!k;m?t?11Ho9PW1}twcCAM|d9i3sVM?LOmNw2<4d3U*gO_S4 zEw52HyefsWaNAaTpSuo#YpZhF!pBFP6IoXfLfuTpdQS@Vy6F__4V6yb@j^Ezwxha&u@7Nq%0Yw9lct>%U z!L7xkWYBxuUt#_Hm?eBvfOQ}=zZ!!B(l&lf62C)#k=i;SL2~)wQYl9B0N}IGCR6E= zeuir2`CU#631f{tYkbAkwN{0i-;R7XKdDe+xc7||td`CJlfoE5i&jM;)IFYPGY!C+ zlk7ZH&TfZT*Fd0&vv1zO2Nn2)vog)6(-!_baI`Gu^&|+&kj4ABH)q~#G_~!w^}CvnvBkL z{J+PzvnRVe!WXcm*hfl>Wsxtxggq?Kd(||B|KPfl;e$$jk{d>VM?KA=`wN0}lX4R@ z(ZjLn%meRo6cjh^g%e{=OSkK&Hg9*um6^aK(oB+wgzx~i%>IsF%Hwe(_@Ma0(o|N{ zG!JVOo(W37v0P1Yg0Om1e1;}e5{f|j&$&YfaD@_atfiers zCA}rss?=+0jz^v!q z8Gh*UpoRLL?zj4Y({P=o;-(?&u;~~iw12U8jgX)TZ5E7~pRmIy6ok!W(faAh>d(MB z*rR=egBwh;*0#Y?Mt6S}RFJnD8 z(z(i$1)U+#nnik&BD!wNcmQNj>5cTiT&T7SxRReN-dP-feBuFBR-HkOIa?B?Tc+NU zV12P%-ovm87Ko_EP;F-kfhtHK;%6_4+#H1mSlP?_MB~`E&PC6FR4a3lyOGAEB!><=>Wqk}JJVCn*brq1apV(J&QesUv5S z&4$^lx|MXWWw@5lU-!7z?a^t4{0o!29B5LKz07fx%&QUs+wUyEcvQS-j zVtiFD)7k+>3!x05(VggmXfPBS-9;BP>e_svH4V(Swj{yH&*owJQY0X7##H6TP-)ht z4fihwn;|lIf$!+h4+Zi9OYWa<29OkL+qA79T8#I$D3>Fp$FizD-7aL_E31t8(=%Fb zqxeCDi-lEu_7C=x3?f+4(L{tb1c4~q5pSv%#>)rEu}LU!HA zDG`~`WHY-%8T=b~&f3L{NX|NX*WXXSr(lg%j8Zl-PaN@=lolUw-_ zyO2j)aI;5vrE5>~rH~W`nY3RT{T5R{q7?)Mz%7EE6f4n1W?yMC%C0w^#&eUm!bK*b zNQDBml13~BHx=R#@fkU@+k&OWt3e5zP;ae6t&}vgnQk1?Z7jb7WOwiw>+DiIUN~Kv zg6I1b;&lx34c2JJ|VC}Tu4BE2Vxlt@|o@ZP}MA&VC zia3c!G#Pq0CExf_0VWyxjNvO#8mo0Ff;7+TP8PNA!m(?4%WMYf$JAg9TpA=er0S;D*poSU8SO{n<-&=uC;(4F#W=|3ev;BQH zX7~uPE?lcsp28nkt|?!;)fd`WvA~LNm$B^+l{midTTQP6(1P-#?_DJ7Y`NLv4dE8( zg9650|8c4NcnurQ$h^K?4!-z|ur3R}*_M)3i2SFRile;o@fEvr)|u4rr_;}`bad{& zTZYEoc~l3$PnI;XN`0xS@hi{0!z}@OlLEt2Cro^%#1ciWAN0NYlO59qZNI4LM-|j6 z>`7*w3?(N`Es6(a>6H~KvxC~|H|sNPDpTuszvt|4c)ZsY{*#+LhBooVHw;C$o5-1j zx)ne%kdk2RE=>8k z3+YZ32)REQae^37$Zw~cwee-pDfth~fZZd*A=x29kPgKhuLoT9QvL4$uVD`au@uBh z+(ba8*kye)ScdF_R8K3MMw1{_j|}#V5qEsOE4RwpqNwG4$1qclP86MNX-| z-zeBu@$?6||8yo8ZUJZVh%Om2)usXb!wE6rXYq8zChvb7M4diu!R=t4Ol;r~T?cB>_o{_MTP6|r(h zdt)Aw()~(^MEEA=fkOlu=ei~VOiA~{DZfS&oKTosymjw2piehz8H$N~Wu+kvxGL54 z{{r%8CDh1CW<2lPJ|#@`0WVI6XeZ*YH%=jY9euM@#s}@4&fW0afMPrFqUd7W&&8@$OyWug#;M`wsSe2SfBpP(6TB-YL82&ESYo8rgypqS9#375WD- z%h~Q+4s48Aj|v;v<=uYY-(o+4iQ)*q7In@yBb>zbwx~#A(x)c~k!C4+4qZsp;{~xf z#Gi-6-#3Z$*SVwi@~4e# za`b13J0&Rv348j^8$MJ{e2U3B$owkzFrck&MU7$B0t!q)%7qGpZ?L*(z+#<^M(oeP z)xJFl`+eP=v2sIFK#n*8KhA;VwD=rxD<9#?EIWCmd>DKh))PRugBBgF6685K(rxF` z<%LE--oH@*=o}rV=a-_3&SAz__!JK1KM7I3NFV!+rN{14Mtjarjn3q{8MSR#Op!(JvUQTZd^6Vp{7!|lalsFd`n$oHpk(sBZBnny|}H_^<#XJZRI(Js6< z2ZrvoP!5G;UJu&cufN;UvdmoZOyzi2;T4S72l!zB_g%UDi zs`9*#>`R83HM$<8tz{wph`vJ7({ zn#7AaZR^lB0qURKPI6b0gAPi24)=t3$cI(F!XVBFJHp#$JN(;On&-I`+Zc&1kF{Hc z_4((@;OA5DQ8o>u!{<%WA&dhFz_gB^cf2C4S@#Gah0_^-hrk!B4)H!2HqF`^hQ1ec zX{yOgJ0fKL^PBO;pb>{*u$14uz8FZ3uYD27TFNR0U8+i2s@p_8FM(wX`aI$+P&gnjzl^EYavU%UP8|cc=IPO+NFyEQVz7DA zt900Cfi-^&i7kti{U9Xee*>C#7;kI+Uo~32BDZ9@5~KeXW?EG54;!9neIk(5(_Iuv z>esC$i{F?EI5!WPPEGMK!q^#-3fsQw=Ty3aN*oY_(|b33a*u zHUr>OysVj%eOVsSWnw~BuMz$3?0F=(wnZ7ncndJ&eVuxrKRs1Ctx4YA!Kjm1sRhJW zw<$gw1RQ~sh|94h^Psd4BkQ;A5odNHVo4zA=PUf5~yctBmT8S!#^hhs@J)(kqPp9&C+pcBM6>pa$ zmHM9NU5&~3aOifrE{5dBT8zhzF#LQtE?53wL*qQri z@m>uQX!upm&l+fqx=0JEOV}$l5Kkw^0}{ z)-_&|!^ftix`_TcPa4)nn$wsa8lgjxf-p>!eAscLd@=do0lQwZS-M(*e^LR29>&FD zU%l92?b)eLmEZCm78Mwz6Fxn!<<;z3^}<^G205xmA53?fA6YOM>bl>4!ZqIeP6y`p9P$eCAx2VlO)CZ^*&S-~qx3_GBO@1SG17J>noWo>e zDW~zugXUIMId?XKU3) z--45i?7n@JtS{2RM>;c21dH9 ziM6nkLWsNBBbqVtfWd89&hka93l~N%{TuLuNFe-XxXfzfJt_pX0|Xe zt$OjCG-6a_#KWf27!+Wo1e6T8zJRy2&aj;~O&K*c8&eT%Zub7ODE6ZJO0=As{zY{5>hf@`N6cg7GuRJ}zfMlSE_ry#!NvP%u#cJ}WieD8 zm5nMjj$Ozn67C~PSZvRvvvpW)O7h$~nX-jA&;2ZP(pUc3prI9&UN}qiG>@Pyz69QF zp5!yhZdRDqllc%Sa9UjWNz^}N$UCvk4&|nQX=B!QJb z9bZ~SrbI7EGyOsN`~jTHFW=`}A5Y?I1T+~eKvwFS+%`X@`;dNx{~9M&=2%Is)_%AhKJxWvBihoq==?*b((M>|46E=W zqBSD9-3MGMA>Ayfaxt8tSde1|)Q%azlbI z)q))6buy7+|9rU%WLS$E*ZsN$_!Cm z?pcUn-k$)DyDSZ=Ms{su;A0^gv2kGFmf=OA7t<-vfRP(*io4>Y7YHfBDR`YDNOzVE zqk3ne!PrjKt6>J8q>Zl|{%ip4a%(0Vj!0d14}eF{A;pKk7GJU*=^nWkO)n6sLnkHL^>X6EW-Z-2*eG~D+OL12b2i%NqP z^g|g#i!=1X2Fc`0wHqggnB%AtmbR|BB-TF|td8emKA)iU2voVci&6Ugg)fuNX(F1_ zq!%ukx20~i5GdY~TtTr&{gaSz7l?vyW6j10az zEdve;sc1sj|3qR>=41_7H9`Mf+K?~WGAhe{JFW^sbWL6)kaH6BU&*a8z4&gYA4)tR zKJ=Dx!%UZ^9v#(bKm-ERyESHPI5EbMtRzmq&Dtllbb2GZ`s#flYg4N>pprZodeP-?fH;HV}xjR2wJeC(Z0 zAe7$YYuetN!#1m?0=KCrs0b(EXnUl82;9D^JvAtDCMLe(BwPEUd81AkM^^MIB9R_j z{H6d`(*~7ep#S46AOwGpHaRFfn98(m!9l~_ICGE?wzQ$LCPh{qp z-kmyhE#B@Vj2Uw*;wAYGl@RbjED)>|Nx|?mCVXesa+2{V#}f#~K=_)hewLgfAvZw= zAtz9S5H#RXu7cz~lkvy*WaZ$yO%LRRkyGO$Ki#Az(%MT{jOs}6UuH_)ns#_SZNE;@ z>6<*n(Zhe#1tLayZ|^pT2d*LSgc95w+dgc6J!}~HtPB|9*_m3kqgwy9eU}^QRPB?a zgVqtw5kRD>0wK2J(zuMn!TzWXDyU)+FGvzs+C#@E7Oq$|*I&J%^YSIhA|>DxJLkmOOv--XGgcrBw9MRPSPw4`-jDDMAikPS`MJY)Yv>1*SqjkifM>k zCQ)jQ0>}zmkSFTitykc6MmP0f_3Ra~QsH@et=x#vw$rPoD+?Q3I{X_>`IuMBI|~iq+2Uxy>bsONbde{r$MGe26D@T0l1b7^(M1d$0Hr7h z2u)FN(bZ-8aOKGVW0-ic1(8qZ2XYLwTZxVew!^4O{dKzZV5?NvBVhr^)ms~q6UHdh z-)~GsXm0VEq-ZnBENR4tncmMs#_~Eo-L!(8fD*zF&}iYxr;T4r(kc2e^9HQJs#R-- zz5$S8xOp|6NNva%maVkT(=YvKr}xh;6ncnoFrY+Bs6!6Ns!}Gs zW_SkXy>+yEroE?=l83txZUBRuS`t`MIJ|OqVims!T;pWH`6F+lWI`*&P#UB>dh?G3RYjP z$NnW3%7d>Vuj&uK&SzCDnjc3<{dwncw>*^jio>YnYK7d=~=GSzm;CS zB#lfZYtAYl#eo!sg(=OMOfhsH&4w_FIOdNMgYplFu|@Osj!N2Ol9uJ5UOJ#sRW##k z)_bLaskMbdTh*Wa1jaNMX2g0H=Cr3zsjf}Ax1hMUGOqm;){ zeN6boaRA*$vASP$A`L`*)z)ePYZ;>uySy9Ds^m#g$;cmF)WyKHvkjJggB-E7QnmNcypwUT4^ z?rwh|P&=Bq)(;xK7YyfuGe36!cmF+_TXdN@biuHK@tuEkwjB_LpNld1+}>hO!#+ewh-EQM@M+N9$OH{I}ESZgu`h@2n z4ibuCP!Y3qb%4;)p5Ka)ryio@jSF)=!2z+G4*{>bz0oE{fhdg;lesFe&D~xG^wl=Z z;`t7ac4(+_Vsvgj_j)ors8J}Y~C4>3hqH)f!rnuPm?zgD7 zM$33QUma{na+m1!$qa>~dlPsETTw8d(ABy`IF{zLkS)TU>M( z1PhRpD@GTt=nBbJySe0VX_xm=aT+#x9_kl$GNir?HFO02Wpe{B^e1BrwK=!_+>wJfya399RdX58BmX!NoK=la1&vf0KoikL7#NjwgW z+&a*M1bp=DC>0v*K^2mkB;cPxg)h`f?$`X9PST zPP`;n>LS!^zmHcoxk0 z_rFt_%=p?4OxXkBG*^b@b0dL=^tH9X}@Ud-mFLHY&KO z@+6>QYv%YOy>mW;r-##(2@C1wIb0GBEf-{2=>3ByZ0f=O;4Kkqm{N^m&nVmVxzVcx zRT=2ZQtvaD`9CPffKQ*F@Y34N)Le{|!bZ`z;p{Nyy3}9w9WK6Ql%!B6TUrh4K}dw9YH9Af^(#qRccQD-MZT6gV0dUWQw@K~q#h|3T5hB(s57hdatI6sdd zeZVjS%5AkdY@!AbiLTo6Lx~a6PN?U!1igWWNRRRSq&3W>baH8-H7X`i+i9#5_I}Pi zess-_FZqkJi%^(oqP9P?j2pow84kt3i_RbNqJ|VhOMdSU;s;!W)R*D-r(Sg;`|S$Xc%4mvFX@`p;W`(b z)bygH=2X8uZt?pH@c(5OUN+mo1P87Pu3cTol^u~{D=pmkeaq-&b_0&Aem|Yph#uyp zk1NK$cNN9CNB}!P#J{!7!G`!(5nvi{vuFdgXAnQ(KO_G=K_aa@Jz)P*l9I<59r=8} z9r!$BmLM_+fi|+xcVZ3mx#*o07pDhtjwY?3@YqSt3OtW*35S9}OBBc)`EA~6kBZB7 z7OK!k;;jT(EnaBdP!1{8&R-FK`Ej&ac2mC3h!U}0Q3322?iPfs4d8@`wxW;M*$5Xs zR7%@ZFPVrBTAYZ8j#dt&XHOcoq@a@bC-j_I?qXM6~4!@sh zWRD-t`c3s`FrnducP@HcH#U{-mZe9bIvQ6Wxz*`iE{uTomb^@@12M0o$aW`HS*$%2 zS}}-(P!2XI%l+(7Q$1FpqhWghF5rq+a}8ir)|mh5XS$=43oORH-AL6{;MG+;&)%9` zAD{u3!!`YROYnm&YecsoW~63th83V*_QuHMXKM&#mU`zDqFC5AnpArfV)w4WE90FQ zv$5p1ZVS2N`p$(aK55E5iAaALtZLoIc5nM6ea(B2-Ph93yzDHUaPt)PbisX2RW)4? zM7IISveyo^i7vD1)q!Ytk1nwN5VznA1>%${dViF`=#d;O200~B1t?)T3x(>oEt?;< zh-sU9jY$$4K6$N2#0q-A6Hu^i#81a^cqws*U2J(3j1=||wdPC{KRl*B?vahiIoOmnYn2cBIJQW$EROmdD+#7Q+Wd>aZ=grk1viy z)TbH_%w3V5nio56*WzpFXfT>E@0b$OVYry`WdhiXx7=+e?WJb2!pO7a#kCrU%QXUc z+iJCVfMCj$Zm6L9G2MSeMtAczyWrzPfohlA+M)my<8N+Nj;m&6HF#l&yLw{~a$h$P zD8{AxJoGjGbC_|Jj_?McBfl%3@Xwc?U}a?wyqnWPfK(ch4Be5|hjqLbABh5RDF(og z=;UH6j_zJcn|z^4=pho%U5n@C}K0h6wFYqG}M!(g~p6qnwrL#bID7vt5`3 zDSaQ!L7p>eJRDg&X}_I+oH^kWWGAj_WLXF?1ZXJIk3bV`YiBfT_HxBGOZ&_SCM;q_ z>_VokJ!pqcfN_04Ilx!tYQXfEQQ;X|mBq_#t81&_Uu{(H$;BK8Ocnk*yc+QAD)C|_ z+C*uaX9}9-kx&w$$xV?jg_jisWNibpw&H~9v1#%I+(Y@>ONpaemrNIpy}5{~)p;6a z0IVXCLkce;X*qiZ#WtOWV#I2O9+b6|k~_b}kAD~nl+6lN>1&O>M8!M37o~U2sAz}B z=(1G?y&eEbIkxAMF11esmITOJDf_NZJ5HSYpAPXR3<6F*===R9d|e+6wRs*g_Nb!Q{O}PXl_jwU7~Q!EA!TBzGP>{G8GAz)QOQYqo;e% z{hl8TYXDXU$)C%f*)WnB+xR~HIWqRPN6%)PmtSBhS{YrgL8_SZVgQ}=f04QmVX;el z{{HK~RnnpK%uuqxyoZJ+C{(|@@F|cciwE}Y#mEElQeUG8zokl=6bziQeHx*v-^+eW z+o!M-*pbcDxoG*hczt7ve$|kjziSnUTK-cZfLKNxT-9RZ$ zsSvroSiElg4^oN2jxcD_JtqFq*pn0+8O{Zrt{83Z0Vg6+O2tRofk<}0jXvmPL5^qJdO3B+CFIVFtC54G(sODf&c#Z3 zzFG9l;Mn3|mZT#2U(DTa;O7UP2(^y#Q@%(c!mu>6X-WbSAC|J|j;xerq?ngQu_n`q z^^Oj1fDK7KeEV`iUz|Qvgj9_*uUpdCu}!JHqnOvSxvF9Q=B-H82xpc1RP+$pE?e|m?Rvp<>Z+~YlD!S`E%KOw~N1-g*;X&s2h;Wwnmbx zO>+Jv+lmc~(I!(mQJh65jkj8=z0dWVIwVE-uRQm4-3)f&m>NP*q`dXK_6*>0Ij7MVvA272Rx+hpUpwQ#=Yv>msR8j)I2~p#smjcpX!EN?j zM{lH(rmv$=%gtf|8C5Y`M~c?cyU zI*u;LW&N+n8Wq)0l`3P9x!ViVIP)lSQO=fKo+@oac%V8PVw)NL?sPwq0{K7OO9KS# z7~{&}s%W&kWHn5yCEG!puJ0O5!to7+NW_ZrWT_tD;kDSbE#;$wGJ3|V3 zeJ0Vf65Oa?b9pER-gRG9vXHQXlvzKqki94efqK$f3f=n5fW!=F?xFNvY>PFvo+=uE z_;P*hZ9UI>A&sl#JDp3*&n2kW324DPAyK+|p@?PXU!mypMdskRJsndqqZ6=jQ0vM> zz@BoOo|f$kWXh5qfsLP_*pB|v)1(KX)ZBg~U6Bj8aQqf!0UIU!(>`N)&Gx%}CxKDU ziu|Qgtf!2khQ#|CROj+;4wbCR=();TyZF7Dej)bn*BLx5n;#jMP0+vQ$aV@sPwYTN zX5hc3hnjQ;(3OJNT+$(L zRk~`aou;Oq{tj((&-XZ2Myf8L0Y^oL{?D$ztQhKl69g6k;2Cdh`OS!# zCqsQa4hL?(RSTkGwR;T^36gAUbF|^C&bH$=={mN@idB1|_*+1yVmW;*hGzmSzdQ4P z%ni;$?A&_Ua(;f8P$D4BsAWgyW`bP!)Oz0u34SbYHg%GMo@VaI*-~o0gRh}^5dBA- zk-$7^p;^l2a~b50Dl@S6QD=!OMu09zu1qpppJ*f;ZeSlHZ&<@JTCil;XDma%;@xbk z?sH3wapK`i$%bEGO@9qH`kjtNO98Rq5*WraOX`d9fIdbEBH)aEC5y(mcHW#(%@-Vq z51g?qylLWhhUzP->Ok+MOXlvHG7C2volJ}zt!W_HL zN|32D+7*!Bc%wtzv2r<)>E+1%$)7&=%1%*GwHZzEa691r&F+o@`*+xyxU6R%BgR=t z$iTP8D0d116!Fj|v?dw`f<#eB5V-RiHT%PA5!|2QT2q6zYTSoXI16(QfvlVRY--oL=Dlmx#F9h%5BY5POiL=@O*{kURuc)DLxmD^L}2i15&93 zU@VY7^Q>lpAEcY3xpks~RpZnUdMt&jP4q1UfWijEdSKQ1Xsz{O2lttB&a5)jlvSnD0;jZ~{nAu*6qbgU%S?JUaBEMZ#w=b`VP(LwTsUYf zTAaHgPe=D?DvIGRYXTbMM+jbI%gUOEG6igW##f4=E*T=Ck?@p3Km$R2LdlK=G;gR; zdT2*TxbSaX#r~mNa)xpx(c|5wS?umkQY5Eyav@f5rpcrEd$p3d-iP}p@lKq=_8lAGq(5N27T8-?O8I3z5r3wnB8 zPdK?_do%E{4LF5TnSNxSNAR}UeW!x1sSfKoKGvgU;AH*zvFVY={hn4agkj?Uz#_cN z$-FA?P1Sa#m^#ELgWX1mT6+V&Hwf+{f5IZ3qAwl@lw?(>@RJSaLsVn5NgZmUoXLJ6 zoXo4W8&TRX+NSM1O4(^Sx?=9NnEE)77E{TzT?2zGHM#TJVAg`h}K+tBs#^xB8Qe6O-VkMZxal23d_Xa_1 ztBfFp8DtiE%ILcy)KUX$#L5>PSz&xJKUus-=M3n?tO2xcfG+D;+y*hMn!xP62kFJ| z^FwZVHBp~=7#|ATcjRe&`hSw5%MPWd;(88eRIQV)^&1&dTp4;mg z6I-qM?Ery(&KA{B!^98TrK00@jm1!!_Z@WPy?Q8dtBZNXkpEr+1(9W7y)pX!AZJMd z?}Mtx6d{Np?b}I0?%Yi|X{rfucD-N2tLIS(zMgaa9E3#%rE7v_ zc4{`wsWXBFto69qJnPmMyxo0c%GVPqJ{J1~t6C+%(c?634|LsqMBTvFs|T9f#qZ#mIC&NRb)QF=_sfzC=Y|GieX2lq{5D-s%pss@u~WVWc= z0Wo<_H4i>e-Hsv?icl2su};MFuOqcU>0s8SS8R@28b@h7q`vZSGxfClyrr}G{qK1t zs5nYyd2tR9FM=5&+e*u4ddH>fZwRBva4>{#n?|Vvr113kV6E)7VMd`ufnr~%3az)k zJauy-Lc#S166}_Q*J5P~re6$ZZ;m_97=wq3FGHup)=^8k3eTCLZ)_>7IM`k+p8WWW zPj6CB<8awHPNB%ARiLu2fy9gn(1tTleCK?pj6nq=XwWB`W3G93CKJ5bhQ;-ad8G`i6<}=2nc27fa>*cn z>`m;4P?7!I>h!$PVfQDL998NC1oZqkOLW;w;KtA0;>*&q4Na7eblZAO6XX@gGN`7O zQMysd6jmZYZ`wtPy{HgpEUl}a*6aUJ$Qk=ZL}b9sYfTm-x1VP9bcJs``Q&ofq}fFR z{RmGPAtpWu8+x^ps?i0QK`@3d{KLz=vq-c+HIj>18CLg?T7gGA_m(hGHbw$nOmt8=s(w<&Mb|Gz#QKVs@m0{r|AHH)_>bojw>fPN}fCn}|^= zog%+DTQayP8}+qXIYiU^k06u(OieT_^gNCwdYXm0lhR1x`jw&*QQBXW_?0-eef0X{ z;Oekr!*MTpQk|wv?_XW;&v;UjcW*Jjgz_=fD+<10qEFE8zxWFO4h}1$8*L%JwJa`}V=U$q zwt^+XeTA+$5nchV6@thy)yYDB6cx|+EuW|aI0`_64x*a|*ca~u&Mh5T1*NwaB2Vtz z3`?^u#IjyxLiBq<9DFfmFn(9(Aq< zlNLXcCeS~vNHy32%1gbP>rSJI{$xv4Au%F*Ld#yOMthaP7eE6PVcinT4bP^ivmRd$ z*6Zxo>;GX?1z^_d|AzY}^l#^v(lzk5-~41a^*~td%9`g&Zl^r!m85jk$Hwi|zL2*x z2-c($0G1!Y@Y@V2oXzr1@mqgo?eZjjL(jq18feGhK>Vt??403VFgMN^N2<{4LxPqv zz^06BJ&C{B6L;QjLO`ssMGKXSXJm3TWtpJ?#Dn-PPwQNjoY%40UG~{ixxViPIB<2p z0GTS3Ohecr^rwAlo>eR7jn; zxb@nb!G)LSdpT4SKZmTz406N3LF)$k>k1Hc6E{4NYY!es_EVpRm7LNAsjq%UNZ*+I zh)0rR+xWNS$^9)0pr@NPYW7#vG*tL~bClJ&4GH7Kp_rGOg{dP0Qe;(WWjl=^zc}Rx z0Y){Nano@VcGpx!_Wj~WBvN%vpLFqkD4le2go-B!dOy{-sK6FkUb7T&Q>?XfQPq9YBW)J8Kfm)(yEBTHC7^#p@FLaeNE+{ zK@6BHnudE89m^Eao6Hg4W!f6~ozK^|>R2jZ^OFFv$k&Td=&5G^9N}Af<8=6Ylcov* zSXBoJ1Nm_~lf%l9bbbTGW2b+U@~pmNp>=jxNs6W!8 zu`g`}nlO3McCuun%jOhv5_y;^DZcS@LCX~yR3Kn8$(~|C+OiHzlV^#_Wms|U@Y%WG z;WgAQdm_F&UmDo&kWaSZr@Miy?^|jlM1D2x9vIBI?b7k<=Y=BLyc$VlhZ&{hF?xh+E8ggiF=-K+rEApe0a(%mrcH z2mEWF%pqYmiZJu?5r`E?kxuLw?mxNeF37D_M0z(!lQa!ZM|D|&6j$S%dRN~la0zEgKS_;|BRz)D^{R}>|6 zF=}l?j-_^V=5}TaKwC?^2|}kt58Tpx-{IxpKz0tzNnX$2!P$F!cth#8jL?)6ICoh( z_)Cubm1zN0xvTM8WMGWY5ru2OMI* zv3i~T%jv!u9(}%$N_e-5KQ^~FTl|>9C!&qy>a;#oe1x!zO+vbnJB3yH1M zS(JBBMhEezE*qe**hco+D~b#y_j3K%P#}J;K>J$=b34f6fQ1O&c-$Atu?h5XrC~R+ zupW#tXe21!daR1CxRQ58pLwFGC`^8lJHV4g5u{8GpQ7HYBBtJUiCWU1-`SG-NT^%0 zmZrKS83#IXOU(Y$Ngqm(VqfG*6E9(l&~d#D0Qu>)z-3-BFdzHd8p3?jkua1K#=p zFD8`?IwXW93~v;7SWn1EwyCz@k`0<8W)ZGQNOctKsI7vOyBdq7&gOL1-Io@xEn~^-hi^l;q|*uF*+^V*u|vRmP0XV2c@YrZ;+Q}3I1@9| zUmNPLB$I9`CjSBf(#$D)$83v^#O{$DCz@bH;u4Z3uenjJ@>^fRNj_&pKbHZFQ+`;R zJ~`54J17!vnQv4vt{s>kglk*VPB0q}AlpVnsw~7L)q>6zY#l&1H?-O`;hUG&NyrZu zfaV`}Z?)wbfk3z}uL|F=u6<|VOEd?xI9JIQ$p(BARNisbH0&^A# z8~5I8i~*d;FeXqqu;p8?&- zyp2Q91%Hr0$lp=h9iXMlYUAeIzY;cHdXts-**&C^G7_Z8)Itugw!%;&oycs(CO&_V>m}R~Wz0ZO%bUQ%7;tO`jQ@WZ0rE z)!KL2l4W@1&H070=Beom2S*~3xSIof1q?Ve)t>DBq4WSi*|yyl8#7t;*%Yr(E;AaL z9T4+VnP(O}7ZjFQmtXDiv7P3J8Z|hQt~7>($Rq!O;{O6EAq8WvQpQ$6Pm07~l@un4 zwH*pm3S0xh6e(0jtj03n zMewOuFq+mxKvMI)06R1sIsYK?X%uJs8 z->EZRa+~@HUHhm_lT8>?XXC;+WI`My7SsNsc<or8hVCyxCMhF1S*JkS;exeB3=~4QE8v`PNemb`gmdb6^IT(kC!q11tw3vt1%0; z#iQ?n9W}ydTNmwk^Bad;t&o)Ix-u2S*M2wfM9NWoB?TXg93?T`eo=L(@{8d8$;>E0{fIE?f;S#NZ^D3%@A;L1 zyPUAl4K4J#K_T8VA>JsbD5XRF2S>ZulnRDduytQ>>*nyT<)ngaM|_molwVMP_QuuC zYd+H}Jcop7XGI#!kwRa%lNcj}38$w7+~Hri*n^OSgoNJt?Z>~ilMl}9+KSH|DZ$~4 zS?R3Mc{?rlHDsRK%qG}eOcgkvr-=@U*O1VMeQE<17m?L<_XtRMOCv>|QDd(aU$kFC z9hhtLn5H!3uLd3jpn1wmwsJ3kavII@9l-wHwG=J*38fo97Qjxkt&$#3h~_mjYm(sD z(aQS21G8zZkrPaz2(p}ttIL~_WotgvF=0^H(Z>1&Es$Quw@+t>0ix87XcAqxdHl_S z8C#(oLWZGwd^#5~!7OI2z`JNy2&-jLHRQEu=c~s7-4k zS%KvI<;_=@lmG_-02dCZz;2UNG5;^X4;t47GKXWwR(`lfl{A;!I10E(hzj9iq!L40 zod~og%EBUfvi~(HF>q#%jq$#l=3pu z#(ChI0%;;9)PMqh3$$>iM%7^8%|BtK5^$q7=immR0iF=uVzj*Y^Iqz1Joo|QU908# z`Dh3M?DKk?NYU#^=Yq$Qz=s|xuc_JL`e2M=sA$5 zFS4NLBAKZ7fE({X*To?uwc*0Q%#Dlq_uIvx@9l~-nxbv)r_YNSLqwz@G;1&9-#Tjv zwyF~6$ScG4cXifgAyL~zN|}9JS$xI=!Zejw|9D#pKMOU5C8%OyM$s8M1W1?bX5jk3 zqa9}y?qRJ`17~CRP4HRd;G93_d~sK89xILr$?%{xUd@0eZj3dUPFkyXC|VI$kIqQK znE_fSJ?^VSqLcBAADD;AxXuLCP;>=Sdx+fT*~nl0lEvNRHUZO?bF?{sSj^57_oicF z)a`t-rdlZZuo6^zUlU`08UtbWcb^XMmgUick2l;EBA|JYzCy=>+g|`>N+Nu-Z=;x| zHpe&Wx1x>hb@um4?f5!%X#>W&0l=<6{b2DD9gcLKx-IJwuzQ=IkV$?LF6`fu zw1L}@eI|;2M{6o!A}|e>2Flleq$ko?i6W$biVCBt=Sx@J7wuG&elL|(%!<(+_*r;H zB%+Bpt#>d1c*-|!f&CrSgN=OvOs(>W_wp5Xo<%Wt7Y&A0h9(TU+H3G&OtAWBO>*;mk#q zE?);LglEZGY!5a2fDB)oSNIJ-z$|}h058GkRuns^+m<%d_?o`c9Ed<{_xhfi^u(=- zltOAXeF0k3%jUevoxBD*m+3;pRE>zC>^tPFV+?tvO6j4~UalGc!RWxxcf&d~NN@L- z>9MlM_{VFoHzv$@-V4b77-q57LL0or-^?l$o|O6q4Wn3K@G%1>tbuuZTzh%K=vi=b z!pFW!b?N0sk2Q_Yus`k?L6VJP2P5uETf2R#Lg82b=>|&i`?Sl~CL*MApCWmW%)P_G z-9R;pKv7q^k%`hp%Kn}6V<(*=3b|{j!7gqzngZmf25sYHLS@rR4aDENYb1t9ecw~q zw2;%(yg+%LR|gO*o!x3}M%9BiT_@NmWh9FgKE+>{D_{uFE>{E-gz+i)(>Z@89t~lM z%NB7Q z%>cwc&p??T=4ZFx;ms)0_}CldqE?<$s&Qjm@>Eww9nH=iU$BMs%19$_CZ5pLYQiIq zgl?43c_kBa4OL;k1VtafdYpa4e@4!OqVVwme;+|jw^(^zVuW-(=GYZv&ctb5&aaRo z>WkiYkoGb##-Wp|GS>uMUeQjFzU)qjdJ|eqw}CF}b;zgRDMA+z$|Ir`gRuBqF9#@F zfFN4@i3f&Y=K@A^RhPx?u9>jSrcK+53y?h7^f{8MJSYF;1Vy>^P z7cL)Awa?#vs)BZShLz911?K2QZQp;F&{oVrj}x|#dSkr3cn**hU63^MURrqMyG8cy zpk8oWI*3+QHA_O28K^#Ui#$`>na6sLQ)P4twG0L!V3ktq$F(aU4Ulwd)|p2*&M8T> z9*`srQirH}sENJM>t3tQY1Cy4D&-SL4XPGgTAc}GO%J>O$3a6mnz&@Cg zDd%$T;;X=!S)OQ$Xs@(s@BHGwg+QV0Fb!3+o-#s_Fg6$~OXs%o1(`@kIvtJ(&UzDD zO_lR_SVcZi_I@!mbyJ9rJWn~cu36X!Qc-^v0=We={Yo39Q*=5<$^)MwXP=IXZJ#GMMvyH=@0qaafB;p6b0yalz&wYdb~I7vPrqH2j&)Q?OrXsr0D_FSM&vo0VY{ZFMiu( zno27Rf8RP1iO&VP&PIq0JuB#fqE#b4^y0!5Zy_D9l@ech*Y{Ch(zqx+Q5L~uWKl$?DH3Y^X&biz zgMD!4R*p8Az}m)?T|?Z%AM)jQqSE4Y*$qu=ve^5cQv8Mi8k6LY?0zSKz$L3vXEGUT zN^J)`+F!bVWNE&;g2jEx4ITX4MN=U|m;!USq?}0|T?Mz*1d3V(U}B@@1n8Frc#sKCNfH2IPy z0q9{RbD!AQt|czIh8nyNg|b-ZN_gP0<*hw*1S)&-8e>U#XEn{hFUY*cAjf|o#28Mx zouWfKs9@afCsp^CdX^S-Xao!qk*FAU>!k*-*Atg9?BTN@OCchG7CvvL%>~VO_u{yj`x(~4mL5W*BBuX1-z{o)b*(@v zV~JS*JEB90A^cfefav1)-)c?HTm^^*5@CK8`s(EU)8i$_B$(L2vfy&tn4=W3vBI{@ zTvD%KH^ecuNsHp&(%RQvddj6(>}PkB3Pje1Jb7+WL=1IHT%ocs(v$BZqULSj$ z3*?_c^GCtCNv55LI_iShKZq>Gdj;&r zcxA0Aq{}Yu#4&a?8O5}jp;3YWsYYI1ECbOKMP-{qzy&&Xo6yBT#{V3u%Oo^h`<-@K z^vTx4c)r2b%C&KXxmkB4%xrglgn=^ z4*RtT6cra!csR(iu?@}jqw&{o>q^?YGp1rDYLWFLO@uWFgVg&#+s{$*R= znT}Gj!O@;>Zdi9f3lYxx$a=~f^aNl5AX+tw00`~o`yNAR;?z_}AT{Oa+A)jf@z0pWK~VPK8^Pi3 zVGOHgEvMAo-Y5;$O<>lUyG-cykYPxdo3l;>jYuI85Y1r_~an1+7zW-T+KYdBe~(W);Owu`13 zPPCKu*o?oH7q=yH|F&J%`FRLqe1tmWSQIRaUcHk1GLzP0$%Kug6Ygv_EO5L+*i%ef zjpBQ*%)Zqfu!ZOCF@|c+%@D9MHvyYWU&STJ2Qzoq$poL@9(^#gPUP6wCj*H*&$A4v z49${kJqk4(dYaA(nH>>s=ew>tzHUe0Sqd9=-9C;9r9*b&8*n%cBjleO+S%+h`R=Q3 z2RtJbZr_cVNuVEK-J}SS&Z1c$p0b0B8xWF;*=0CpjV#KMA*6?i^*JZd?(Y)o4>5(7 zjAT<6XrvKjbTEkrOoTS!)^H2#JjDUmA}H+2Uu_oCX?oUymlj3}>;GSQlA@dU3Ma6< znvdvZus(H|2vq)(mB|#w?I+JuJ3oYX-qnD!mV|pIp<1najSR4pUst z{h1{8Zy~`=Frw?@D(dSDFXAUZ>!p!ree%PF$}rA;={a>s20bBu=v1-qD{kVyc4~;U zhM4AMSjq4eVM0l9A55$-SybwUBhYAO`lnOvjycCZvdJvu3e$C@5ry~PhT%;vc1sB! zoEFRr=*}8W6sGHC&5D>sp48keh^)!1BJ@z=4^g<7A+&iz1{MUW5$Bogo0OCNg5ei%)RlT_xn))}=anjD`diQ2!r)^>%+>?06=amd{z{r6&F{xCUS)im_5<%oJIcAq5B2LSv|9Z(CuLLjUE;ddq*&BIy z$S7#OXb*(M;k~#;*xBINqYhyHxyR*JORLKUe6y?e#+y6w6;eu(bBveiF!%TukkE(2 ze|*O$S;#bS+BJhoY)pbgRc7nz8}n2b_KQd$dnswk^|5!ys?NtFmhsS8v#5>Dp-w*D)(v_z_ zQ%{CT-g0=J2=uBZQw;#bt<=Yp&(Io(qn*9opmb!TtF<}Y!VzA0WHA-{m}Z|8_}Gk- z35@0vxd|8?_I)$nr<8HI08+s->KNF!YNaVu?YjcO$ zqH@Jl#~sS z-U7@FPp=0*QP?*`#17bKCbA3KpdJj*0iR0&C=^dPDEY+6If}&p<0w%Z3JL!PJ%9Xw zTZPHp&u{Srcy@vTQEv%&NDtVJoQn=&ZDD!>vfYx#lX&5E?vk~u4YqJel@NVg?ofSc{l{w8$*XwvOST<|SDe==QOJYJ`@a3h zK_>7BQVoAI-qw?IU0O8|cBV^70lqQ8Ns2r0llTrs|7Hg5rG>k0kvjF_3z=X*LH@@L z$3B<+>YjgZ7l9>A+qI-7XFV=fmT5#_r0N@a!Suo0Ofk#_cVC#m`>x3|aS`Nj;;^Ln& z`VF;Hbb6O?LsPnpMJTC^toA0abm%}+f;Owfgo_rAVv|k#(aD5xE=so)q3(Wm2;?J9 z=df?ZDgSl54d6YB{T@g?uT3zXX_P<7NBe5*Ttt?G893I0jno~`gYKoGJ$>$aJ?0X7 zVVD|JE3Vpf@cKzOssXiY2WRY zk4XpIB^8an3U=_=FFQ=6SD0Tj4Yg)&VM%`L3ZcO3ycRQ`F#pDG&)-XE#=aqQ2vT)^ zu9vLtR1`{ndty{Lf_ScwKX#48fG0ZiIW~@Ir{w1uOo=koacaEnARzioD~MG&FmpEY z*{~%Pvr`)Bd;X=jAL$oVXxQME07G*Ae-}mg{YM?c#tJ?VlQpxeX?iSg!^O~t3a0{Y zcYRb(L#?OCz1$mGPJVl0Uaz#9%v+85QdV5JCaz9LS-+-m+2!{)4#dLGm-k(|>6^fW z`{;w2XScBw@N3jglRSk(8kd5zdx3f1V}f_((&WcR8iJ60Ej)l60dU3uy7FenejvD8 zNaKG3T@~&%tpz~9P@EeoTyEb*b+Gs+v`P@WQ?|}1b?K=l2BNCXz2ox4gP2Lk$Xn8P z2Nzb3UQn|)C`arVDGEJb^?rYnRUQIRy=`aD;cbhu2QXaY+M%yU7C(^{RyCP zeMGq&8b{AafE$|@()b^tQ-}9ITTb=DZW=$*55U4Ii!sd+G3 zQY>ygJMq;$L*kJw3wX^>^tmKyeSVn?qUuFI!?hTTH(mc4?E zo+HEM=v~Ndkax@%?=@$#A%zc*(FuM~ZgLR{skS$}hZE=ZT0^df`D>p_GjN~G4cEFy zALcQ+Cn?rcL#geG4|GbNWVKaXm6l(udk#rV7PR}<2G(t)a$HnuF8?`+eSq0aG~HLJ zZE_zb3>s3ic#SL|&^h8~?M*rtr{-=(@R`qg> z12fg0lHThAX5#CtB!nzi2yc7v-z;s5!i+W`4rM`AMocJ+CGCgfig0fCF#pabv@PAn zuW2X}hvL*vKrJ;UX9=WX5a7BZ1#Iollqy#@jEq(Ggg?sFYE?Hl-i?S%bJ&4|`Ezoa z&7<>(u8@kB7?8&p!fku0j{|-pY1K^9;(Rw=@{b_-QADtd!3_(mAfSvg@YleNHm#r0 z4XWSs_&_{fyk!7YE~Sm_QMPFpOm zh{YU}P8dUmcT&bO+*}u0hMy^q~S>vdxZZ z=x^?UWfgwq@HJd0r%w9~mk6b0-g?y~*rb5$>o6_wX}nQA~^D?039h_8f!I zNquc;O(waNmr;>?YKst`hCG~tcq5*_=v8I*_i<8A0ctS&VMLjFYRvBU7!ay)?mXcN92?|4vvD)1Y-te{iYQZJxyT@N_oA+QFEr` z-1A+IEP2WJ(PFLCrQx0+#z3RIf=jx8nf*Cfr4E`&6lJq`mM0TgS_Yuf4@UStPtExb zHC;4lrG6e{h~4^5u&xzuA&^`y1Gw04c=Otu*bwD>?IaDbWu0$;;>h#)d;z&55-ZcQ zHeaz`$cnoRs`Nr#Lk#K)DEbOYGJ@bBo6hr$THa>Eqcz|q1#axh*8f|AN$t~m2h_B6 z$mR>Uqrh~0c`yp$7rQ5C#yNb}L|wkmZ)JXs!xG7Pq{KGDXhnoJ9?Rk?tjsnw&X|1w zqB#fg_A5^nKO8VmcoFqzH*{&R zii%ntpz(wzZ#=N*`T0DkzDYdyoEl`TWWrkHa5+nEK%a?W`5?7QkfPm~%t-=+Zac`u zt(D7eJ1U3gCvsSU5H%`HaWq_E_2Msm|+gY){(lBw+6 zCk392DjaSyMiGAMsN91j)`4HSNqaW<`mw_DP>Iv_1U>NPA!4(oCun zitWu&z4CBTwQ1o9-@SW9t7R61X&BwnrQ$p{e6Kiys_6(U6sTl#NWkSvPy2PXdED3F z%kFMu+{PzB$YFjOg!Qe1J95z+?>Ox$n3Q8cVB@E@8aBcd(l^{eCYbv|zEru~0H-D1 zT*&zweO!#(BCh})XGq1S(y_}2Kv4tQo?C|pX?DpXDL@)6I?5LHY1jc4Xms9&*~zx5PM27FR!*zfN1p!JKy=lV!u{ zgBDA4ss4lQfaA-gsBc%E9M3@Rr@ewJ(+-AD&OaeHcCB1)%Jau6lq^_*=rl4z3{d^I9^e`r1u>- zCCA*VAl{O~Rp#_U*nWX84G08HjB}=0yf!Wm(ap3J_LT7mTk1KzsUbwB=}E4{9Oe#R z^K>bNrI#kuHW6D-zQd~wY%#9fs|EYjhUd7mzP|cU;uMrmM$3-geYv;b|E&j=s3K^G zXB-6`4rTNow_|N*03xXx1h42$7mQ@Pa-t}+jPjw|GcH8LGqM1JMpWJBP*}WVn$BZTBciJnl^7UKB9K6}z9VwK6!`kBnvz zA`WvDX&m94+4~U(@d{rdVqghD=si}7FaSY7zQ6fSQ{^QcN?yPeuqdCqbFtZXx43!J z(XJ9kGQYAVx)Q~|=O1+zbc>_?ZqETr1+20rZ%{ggPb0Nk-x8wisX#_i*<}cF(bZDb zLUj})OpwH7fJj>TRVkcUD(4s@<*G4r-<%7_)j%ErTzs!)G6^=1qEJWK^eX8VS4Y&4 z0wmWb2|EP^5%8F;=E8$*j6cTgHl;~ch~IF!;Y!5muiwLxRTUj?!#z^sEYLpq0a(ta zp}hGBm(W9^S5%;>Qgb;iPNpdk1Kf)eow;lhnOQYvSJ&X3 z5OGq!cnX~2F&F0`v+uL=jxqxddDJukKMR&k1)h*w<$~B(m{%nIMBOGe!9^o`7W$7+ z!LWW(G5Jz|$ssuVjHXVCr}s~vGacdbu0zf`V!=B*A(Tx%9_JoV^bGKUS#R!z_s?g5 zpcDrbrV-t{Ie0<4)ZfUe`bLfg{5F(jdI0)(A>N}~M-_1QRnEgcq zR~n3Eg4!wb*QP0;!u-Ef{{MVn)qocV$O;Xv8P69P>g(LcUUprYQs(e8tvrjb>6$NI zn6a21hi1s1IR`_zf2U08$mimUXhJD1)Ja>qhNvYM;JZk&Wl0&}hsZhfcFY5nly9A^@_)2A;9`(8VK z2BLPcd@KnHhub*FsytZpujJ6RT3eUA{_R-+_JAi<#yrpe_^uti75|Xzf6>m# zTsaMLF4;r*MmdhCJvdBHB=nT`CP0Mz(Vsr8TJ8GLVN2_sTE=9SsA=KP`D_UJ3i}$g z*XV`26g&1_AHSoX!V;pII$crlM_$27hM=a74VHn+?%k%}jiE3}zbv$c8y2qXo6cSD z0YkMiMNvc|>I)h_c0pbxudno{V!Qvd7DIEL@>Q+7X{7b!nohdahws;WRzotcWa6hT z74Et*e@i7g$XfiLqHrAJCp9CmB%iY?^itxrx*QY@W$!L+^g5K=i=}@$0WU<$MDZYq z0b@?56CVwYfWq4|2{c5Gcpilop4NyjLkyyQP@+nA8lU30p&^kF6$Zd1nhzquy{yrn zn?0AFltn^DEk0ZdICEHXg4(en%ny!E1z5z!M zeb~pEm*(-0`2oFuzXXO#hwVJQGO^Fjjvex=$@y?3aVWeLYhUnJdt?~AK_iO0GPl?% z!fju|D{uT>ZUjR(0QIuj?E#u=cVZP-8;{z34LSqG6$mSk=0X?*tfr1`j)Cp{-5|k4 z$Dz#q$Lmn9qCcPb-7#K8&jjOW8WV-Wx@uUFK$T0ILoOHkDt~v^)n|OX^Q@|sO

_6Ft<#`lrau=n z0Gt{O!Sj@0a`#ivh3J~4Y`X@ay7B=T_*X)v=Y)&;;<08KpnsS397(8uWUbt1sS^{C z)OlI&NwyGX5GQ~Dwad(7xA%5M7#5PpGjx9pZkQ%ANmDUHg@COClIYOJ`L4nK^a)&d z*tnyGVku}sR&2@#pz`!+8PFOQ&CAJKJMBHL2P+-3^|lrk|GwQ<@-v`mXF8pbFDp{hdJIb;Lt`!$OU`@vK zPVfAnnfX}>OxM`$^rJ>|;micYEMDh}X+~RMi#tm;DGpfp;<){Uor-*sB_eIaaHNg^ z`=MagPjD$tZN-qDL%W&wlXD`p%jvWSE5;34Lqt;`F})%tW3jg^9)TWkf}_8{Ybf6v zz3v2;e6WcF`AVpC(~n(Y-hxrHB1-8m4>>Sl4D_s$;Ozn=y3L zhu5uT?@E$NyTcDA^Hz9V>&cTMzvIVf-gLrWV3>UfY+9l*Va47b;-Q7eiC?^hoNXCI zMMMfAF*b2iq;P8>|3NRzsALIE#oq6TO6KcK;;C+}WBnU<4`NOneSo;mDyRb);%Q!# z?<*>0<2+o3P42DnKO#eWS4DwTf#ozrb7CJGuNS{avKsW@U>iD^?7mmxa7(971mMWi zUT*p*Ncvt1#Tq3)-}W?};9Gcpt{Vh7a;D^qbF}>H*}&cctlFY;xypmpw*{OYn9xDq zPZ9}7kg+N*(eb-~f32&XI1tZdvHx8${`e0p*G-Wdpg<%_kmECLL(C76B62L3H?(8! zHT|P$8vEze{9t@N?&ksU#pfAML>8u42~N)^o5g?9_}qnX>l&wqk(=ztx{mA>y;)&^ z_g83(h(CK>x>p#AYc8ofgh33g=%z-|<6wZgwY725ik+R3~PIugH*W> zyG5uu5vg9>H~a9)T?YgUpvJ9(G#nGw1ry1@zOCCdyF>zuO#q|zA}SM2C6nXV5%I_p z9w4MM37pn2R!bPyKZ*ub?VU7rLe$lsR0%~^^GT$b0n7DgTfYLxP=~9Zh&ekEcR!?P ztZ*|pAFUD9DulQ=?9Z0g#TgV_Geo)?&BnRjQM96hbiEfL=h!oVcI^n`moev;i22v& z<*iEpQU_>!q!N8m!Ofc6mMRo{y+GoH2gjqksN~^i0z%XdURmBLK_fVSWB9Zxe z6Cdd`7hvo&Ju9I7gonKvBmZU{Cl1}9ceHJ8L_nqsx=0o(-F`h44Um&P5!1Z3FdaJM zhfOF8{(P{sBN`;8`L#g%pdd}>-v0u1sf;r;0Mrp~o(!iYt?{h8A45!x;O6jyST zD@CA;#E0Hd%-a1{M}$juy{wrJU6`6FdgiF~7Nj^((}FnKwis)p9ps2BU(8p7^@hQO z!#!y?tc##)rj1a_H`n^(Db!&`I%Tms3)b&1Bw%v}w?oKY&(ryiJD||oxISRo-U?_* zpG4*@rjiDqBgouJRgAlEFp@>YJSPaxWZya&SN9*2;)1T79IdNJe~tom_bJwU^r}~_ z5e|asSar8CSc5Rt>u2Wl-z!kVTSm|gR7ES>`k8ovx!0(A0}w6m%J+RXiaeF`zq~MO zNbX{gW}I&N)3nZxp|O8S-F`dN@<<@A*KqAsrWq2#;a0DB-Gg;g0BEgk-r1F0d1 z?UeFB8mATJHI?ULh8U^LNGgKN3}44&*zX_=VH(tJpUfP)nj-^dcw>oN-0k>w3J60m z-!(~p4aTGt$S)Fo@Tf~hw4h}-kmf&)sC~{)CiG8-pF7**;C??9c;iznW!U^mI(7#? z6dx1#ruJeDU+9pJ+R26Gf0P@3^Yf!YD9PDiB-Huiss)UjrJ%9HPPQIXyb?C$cO-Tq zxpkmRVm2h(J%UxislS#3-G&Q-6hF~ZwVOvFHoFT@6h(3%o_$*Xo4JHEIuQ3HldYD@ z&H)9eVyj=nTvYYeNAYbc16AuW6DkT0seDNE4NB=C^JC_V(_`U!5czvT}A z`$@J^w*=NFU8;!|L}yK2Q&xt9ZKWwtCN`d~RUX|iXbkV{bw3$*h2R%jy4&`)t}sdj zK)ST>B>gXZi>4!D5}o>~FAY;d%Wm42!7rd-_m>|=;4;wUYrhCctwZ=NIB5-r#YF6e z+1n?i>xMO~Sxy#8PWVWlFinh~!lbOY9Vz8i3jA&|>T$We{n1xJ!lh#u|5w*>Pi|2d z`J>y^@3o(8dFWNZD*nU7R@q$2$ZFgBfPh^cRC6+UKaB;tdb12VI$`Q4lcn`=H263Y zhVyTbWf2R9pKxk8D@|9qfrM4F8x1jwbyD-YFU#6k(Dl5eLl@k<>%53KBu3A!&+`19?Y9rS3G+tCA@LWPvFf#XalP|Bm|e=^7g_-`99Dt zt>COLm5iEGAp1a+U*>A+=TK21RU)ev6P!`|&>E7fFGIfIz>&55Q2j`DajZO~HU);X z1D&NOpF$LK=N{#tL7JhBguCs{tAD`~nkH$VB6#@j5DC>F#z1jq1wb20b8Z$UX5PhK z8mCcjVQ}q|h4-fs3hM{JHD-c{soC(SX5-wPcCWf`f#O3!^mqGcZ@|-xMiNztoedG0 zK-7bO0cJVeR;w< z{H>G1o`d*N$!Ep!P4qWjmg9a)>4$vUX7YvecV5!KW<7?vAzp4)ofWuoE}>thtLtaU zx?H|=`zP_Z`$P$6nr2rZM}t)%n4xyh>R2NU2k79yU|nu{sT}%@#O{gTL4Va z2UjST1z8T5Zc4sR!uxuSgKHbBEyllj9oc~S((Jy3M z@GgC=+#@tU_d#UZh@_$eW1f4@&i@ih<0}gMJCYy!AlM>iaV)jYi)I6|Z?x@PJ0*Iq32*3F8683FnuYFg^%4lsfhl zWh2A5bl54@^XX0Rki8MOJD%?-BVcGWq+B>^Nbl1G4D%%45{MG*Fkr7OsP*W;; zOMpvjNlGdDtmVXto!QBga==neiXY+xRhUkB70V(jZ5`(&Bg@*j*6vyNFCmHME$!9q zdZ)E2Y#q6pWflVYm37k!=C~~+QMEs#HYY0uZ}eUNQNSO`Du_8Ui09N~fZpNu?Y zCkoxRd19XcY83X-SpmfmU z&jM|vPuFDme~*WXnCUeb+#MR1I)Vp$zGdreXQx^aYZ+w~wfO1ftLJ&3!$o%bnZ0{I ziyfz0_~~jIf|DBsClwGkwWr;)&iVEsFME9;m88O_?J?i4#UcEh@ChVX=wEVF3QLnQ ztIOdq{(SY-b*A(EB>SKWyn>j4*s|g@@5it&N#KD&J>nm0;RE-R#x4v{_jorI+_5P4 z?BY3+!@B@(+n3ZQ|FQ__{A?g?X;TBQ0H!ik{Y2L!Usp7bW>arSuKJm+G|?=!>-mIF z`CCKiRdB;m*?Jf~aOEg#sQQBh#FYz2H&+GQB!%FLRb|Z)LK$y9UqUjvc|zyqy;PRxIQHKVnt&2X=mAzZkbOi}b-m1{m_*F7#n{hs>q(dLuJPypD@V${ z6lYchyb{4pwwCX-Pd8fAp$`Psa~hlbaF|q%GEMW1DN-g z|IHaz@Ed7oy5Y0Jj}yNsm?>>SS0zO8$#E7&o=8ku=8z$^o-w#^smYCJ&08I6G-j3< zsnz0l&$YF_TUL%JSjDV(==%8|iHcks&4oQ@X5n+r8b0MW#3A2cdu$YQ@D7KKlGJz3 zAEnO>FL~BQou+KdBV0?tQAQ+&$TUP5eic3K_w`}vYG^W|zUax&QR_B!D@AteOGCZN zV$#)jN6=PbRBzAwtlL561oic|mK|uUW2iBS$JPG%K_yX}gD5m9jJ{3Nh?tJhHrCpd z{9<&2m_o#GpjM2H+=aPIf#Hpbf_p25<8Z%H;;y-K_2e304$V)Q^&fPL8zgmhrS5WK zfki#-^8D9Zf^dmcLe*Y_Xf?00S%o#jc6>1}v}|_>ic{ycc_~QkFd6j1F{)TYiro%d z$aNRh%zWL=@;9+aj!0aAeLXdI8I!ahr?@J*D0K~}eLCr5F5-FE3*LBWlpo0Cb@m9H z>LbOWDQ53kg`Ry7yhJKo|lj=b|U+ytif04 zu_dY8BvUiE^6zKlAV}gESlxAICru#@moOSu;Y712&oWy5W7D!erD_Stb9G55Ws3)N z$(AmJ^vrmj%9oDlDnV9b1mJGVaB|5wmlpAsPibssUa~PBq!C|re_nt08+Z`^?;R$t zEdxdJqjfr`LCL1nLT?`+OSXnjqCdR~2_~Kffb2cy5s;Y?Z|vYL$%=k-OF#oi1hSh! zq6~v3YU%$rW@hU;#!zZAeBU;*aDTwmF$KLHP**-NXEjmm6K9pzUfhw)v0e)fW~PGm zv8*2L%Suobianh} zVTHD*j(>Pa4Kq6iD5zuBB?An{K72_*j9tpUGZEZZurYAd>yv{*d${?tG$#GBX?&^|rIblRrbcS4t_lM{}`M3V}MLM0CHDpwa$C~QWhi>9vZwB^# z@&ALW@rUEh5S3-jNK_)4d5GSxbG0(i*t?|pBttZp>||TBa4usK7pp3R&vd&|y43lL zY)$(t&oeJF>wDp-yZk#&RQ@Uz@|=``Krn43{YBlW4Dr;3N~nuaQZ!LJgxN7I@`0op zq0>FRPH&B6f6xgXCk!{a5D}7nfMzBstrxK9?l4?oh_BGAU`nPWJCH*jy0PkOC%1|N zWk)tfafI98Dzf;RQu~tOc5C$ARB()-DTw}4iH_qagJ3Uqy*z; zUI`MA(jru%*2kY-H^WZ&HqOrF7&1@p#+}ng5j*(0$a{y*+(;ltTVcS#E?91lQW*|u zacGvO-^%7es5RSJqAYV^hzsld;Fk|pC9{Y}jH^Sl$Sl!%a%P$iWXyS1X32d`@wV(|hx%xL$XtLX@4CQ?y?|+N&W={nB9cpYJDDecYSwNs{u@8_iJumkL zhTAM?B}U}pURAWqK^CCK2>S(TSPJ=5ZN!!H<=X-beYTSHKG8j z|35erc6~=@D9%z8y0dPaSN6&9tG5L#wD4JbeHfs~?JyE8aTH55qqdNB0$dul9y|8d zDJdJ;Svdi;jH;Wu3h+?=$DKnWt$5p20$AA^qpsLa(PVbJX zFN1UHPZ2gl9zPugaR-2`)-b;Wb~qQd@txt}7!aM}h)349Dyl6Nb;JEK*`sNaad z(^KN1Kr_-+CtzX6aph)cRbzSvT9+AAB%ZH}K zDI@w|1$l6K^mHcIE3n6~Nc)&K=Y=nvv%v|J zkx%gG%GO?kgg)-(D}@hu(W!Ii6T>x9stX|l>O!cxQy!?}deEbXAgs+z9YuDv`hMI z!zQx_B>#kO04Y%%ETuI*5w0v{yTZ(mrM_jw+J{aZ|LtnCtZE&fFbk1z1k-{OHitrx zN`?ghc-C-)=fEf43#aEJh_bmB@Bv_b-m4T-_*V80ytqIVM5Yvv`^_1Ln;btE2T(L~ zrj`?>skQ@CJ!)#0>+v$89x5?>R4 zEQM&$3?J|s`%$Lx`hLLnjxAt?T*G7DcJAmb>I=ngh`FBg0W#VeXd?*_(z&Gl(8h~( z`a*nK3jEy$LO)kVzU$V%ojZu+`6^__42d!>u`8Yy9EH)Ah264h@$3tRokI1>loYyHXTY$mjtA#ww`+& zHE?noFKv)1MskkE>Oj!3uFBldB!qyvoIqj`QQK*bq!Oo3<9psN(O(*+Pm3u&T7oWW~TS}@sPol=g@PM_?X$ay^K(t*u~lRe45d*Dnx z3Q`ac#4jbhB*|v9cz?Zc93FrJYyYKJ6D3AP;#nD8s8%bxxDxM42tKW@4*;LrxKi`Jb~VkQau9}PLL;G7gCu6b zZWiQjhC7?jHzb%9djI7x>Ylg}2{&3(q9BN>5txlawv6Jo0Q9aBafB5@q7k?P%ryp~ z;>-b^{(h|fN{J86 zYv`-pt|O2Z_2Xt=&j`50>OBlxq=u|0+T1MDNd2m8Ysgn;yeo27Dhn< zG?f*-Kc_;op78|)AfXCWbnY=?^8fS<`lnxBEX!ESdYw!<< zrtklOaN{-PkRIJ?es~XqcHl}EnVf_!8_BtGux4y*{gPXOM#r$M#*q^t2~cno(5wg+ z4wF4j&u46u;IkMvS#vjvJObXIu2x{9k5{~2TZn0^md*k6g*q@Oi1%_{_fctY$0;mJ ze^<2(zhi!s$y3}2HVio};l3PaK;i0ZM-NKY!{7<+5}$aM`x}>5hd|)@I`9Y%0lNm? zs>_dfi|E-gba!1E3wbW|jM%P5`*4SN`$_|iPA4JklFe`;kZD7oF)pTx1#0Wbv0lD{ z=wE|(z#;p^Cnr6R(s;XMP%vP9<5%V!*nt}s)lG<8sg4*!sv>*@F`t<^O<(6hPrYAx zW>(83@n)(|5NJy&fh#aQurJHO0gHLmq%dRfR_Bh|IdmOMNFy`|duNEyV>-|bt$I0B z4GO*+8uC;fFY)d0Jzo=KW(fzfxJnl`Y3+08zpkbw{Y|K)E}IeZIOcGq%E91ZtVi$$ zmG#9ct>0rfZOlikl0O~LUe{tsuH!1*CIZVIAxoVEjC>m$F0}s) zZfhC(K)>EA*m9G-O|`nt(9F08&{34VGcg})FCDeR%k>Bj`)$q94`K{Txn}9fy2s0A z)p1iRgB%@Fwsypp*bt{_6lAm*SM5&9UD;57~uJH1DI`+gzqO#I~unwafN5 zofxcLWIwB@w*;VIK|ILBU1EQ#XA+%ThqE_`7B_>`V}_V|o&LSJAlzvg-gI7+=~pK; zwqBPSyVf2>GziE8t*w}?T5j0q8`b@vszDsk!3uXPvrbqYF)V0PmOIVXu%{9M!`>SA z2)wKqcTnvSrM+EngW{f?^#N@_N`=z4x^O|#ifo1HwhbK#%Xbk6vKl1ULi6#kSj-p7 zOFRxRysbbWztHMdOTN(wy(q=r!q&o;Fs;ct(#T#FGmXJrfYqwB4!!6UUZgw4`}@7V z)wZBs8xbC7(k) zp&8<|e1bR?w)=^i@V4@9#v^%@#=sv=&GQ3@o(xOmwfmlk^VPdXz~I95%iD-8Rxr^ z#!6Y6#yy%Wbwfp=3)5P83=K=@X1?!AeaBFnn1^X0wiB zn&tSnKNEg4wZovN{Kz7S1ZEl;{P(6NqhqJoU^EK%omos!@HUCxpR|l)^Q0gSUc{wc zQHYr-rMHIVGphRHsi@`8*!I(6w6xz;1yhp2p=Zafw3ktb&}NmI##2 z7I8>aBh+d6vaSVU-hqOJ?Tlf;8X z-HllW&R&!V`rLXHJu`Sy^1xq^$pThp5_{)YR)ub{+|eI`;>Q<)3-xAST&OSd`hYzU z0hKquSP7pcM<8N7e$|u{SwT;*2Oo~5ixO6pJK)HEEen@>Ne@|xg7woN4>;yb@IE7V zD(bC34hT|bj5=B(C`PFx_C>5Lys}d47VToHL(HSQRnZ?%i{{GBZyiq2r~Uf;X*MQb z_6MFP6W9FgLw5Uzq{rO1?s{+lA!(}qyRrvZ0}l54y@6?*__6pah570Rkag-F3>yWk zEN)Q-Ch*MKK{hy0sF|bAa%Mts-U{xGn|0EwM8|K9_HCk8qfXi~E^ zQ;)*1MXJ$85-;YNp46jgcvqCksMw`sy6NWg{)wVOf@j%Q$u~Ji6YyMdv@=Is7auqF z^3ReDj$ZN~SdUuPwSC^aO0^PBqyjVQ(-odWAI}!ML?Xz4oU%UVp7jLAY*x9Aps;wh z!GxRkBaB6{vahcChtWT4Qp(~lPIx0vBr*UV4oj@aZD?hNLfrSYtiPpQ{KCm5vy2)q zK1eS?rB9<~+tl$n#-(2my%cGlC6f2fdaecg@$bi(vN``ZC$`l#*dM+d%bN}2vy%+mseIRB@vOOMgGq1`GcClMar_Zm?AlT;HomdY-X;}ou5Yk zO;I&C0<8*PUem*6I1{jdpr+xH8FlyFJ>xNX0JN%-RcrAO_@#^9~N% z^+9uJlK~8Ah#mN0R2wclRzq*Ua6o`3a@T#l>lY`aNE?&hi3;bo0B)L)yS2z&d{C8dHhKWm!HwJ=U1*Y+9B4a zq?cDMNYQMPBG!K1L^1R@v1eK)<;0~G-(9o~HS2(6ZHt1Pg)WtpVme+Tif3!_w(TNm z({2_a_tJR4GcVo=a}3}-7)uzXk5HdjOmT=8 z^(NfCy_+Fcvf@y~*K9MFH!}oKi-CLKCgWOJj71g$v9yo2LUY%-g^8xldNE>4%G`$@ z!#Q4u;G`N-?qCDGsf`$T&UQHGDu;B$0N6mAO z+$im4r=Q;dB0qe+Lqerb5^(s-FN*N?>dku$#TL(Y0#3YHBXnBAmUzMt-EO&{b&EW; z@c^i0zyMndXf1EAZQQ}#+aS>HyXo<4JLfieyo!{#uVe4BUzrV__vM{%ETdmI4-=68 zmPEE*M@qkU6zT?N+M5{UO4u=H$aA9;sPUY(cknI<1>Z71m1b4U-x{)AuNy zB%ZZ=CC9}`ku?#Yn-_~WJy+mDR(Y$uURg7E$Z5<89r>;oIO392GMSTnaWbU0MBQ41 zX|*wMb_-qy4-wbd=kdb$8x2`X!=EH%MeYS4j67DD@RkZNjhZdLq3}85CHJ1Fv2U{F zvtg*y%h-A?CQ*{^xED}U@S1Zx5{sgoT&Ew99c8%}XIr{(SvgY2mGqNaDST{&CpKcZ z+*~CBCA%ln27&mM#cOxvjCew$K3(Ft60%m}HMR&QB09(c9~xH)CoT8vW@E~);l#DQ zC+E1SmH=4?I_3{?Pf7=D#Lg;#T>a<6bfE)moCs~;C&36!UDIS$phwU_66^$|3WQBj z+&t$}F(Jj@9s=DAw+1GL3ZcrkBT#Db5;~^<6w1(EI`VVCw$J$UPyoF{h)JuE<#ZC9 zF(rz~zlOI@PYUS-rfUA|O(b|W@23O~lcmv#E^TeAH)VcEoY2;4Vp&kAktF&mKOB3p z&15jc@34=jiCvy&xVt*WK~{maM13|%uGRxf23t5aOgSV|G4aA?mL^-DWlOQjkdje(1jv$e#2<(cj|@a0;{qMUqt|Ly1A zk~~`~#Z68@!i@|ij}};$en8nvc$#HUrtVW(WcMgRGUOePGztu(#Z1U2BR0U7PY7T* zUBnwS{hezSU9$_{d%teOu*Od*Q3RzRb=mggz4fBPIo9p6JRw%#zpV7d>z^dsJqjo5 z1ZX2m^e-k0*q1R+l?GOEW_oMVpB!H7yk}~>&=~U{RrZojowonO(&0jb)J;< zN@eWpe}!6w3v7E727_ffb$_!=hWCeLor1eWC$i_RMFwJ1s_Gyek8i9T5O_(oa(w6@ z{M1jT@_VL6B?VZbtmTFuWIKAJ@H zHQyktV-^kA#Y^F zW#1T)SbaK=_ph24!FBgJVmO@N?NkRlYbwKlfs2W2j@f>B8PsV!V^^xvuV6IUoJZ~{ zb;habv;Aq}*C65e>%xpfa3?D4Dpiw0Aa2jktdzbs|Nl5yz1A$8fX5vRhTsrAgSy3} zDV35387zv~lAazr)SSnFmS;^8z!B+O!i$&dC?IjvF?8R@I?&=+nlaI8h>WaJG|S|* zvX7kOsp1YCXX(ulAmBg#KmIjOzElj)596XGDcxra6Y^FKGfi#Y>KC{CAH=LNn>q1J z;`6F6YQ~3rJO8xwi2Tx#T^v^QcnRs)U1(RDp0qHPYfh{#WO?K!bU=)5x7s;DC}P+{IpC zHbV>r**q!%aQd2pYvCp0xe#QwLQ_c6)9Lz&rV+?PyxUPgELlxS!qX_capnJ`F4(aZ zoA|YC@G3J7x#)g_wZOTUM6IChlWS)raYsG7ib$bI)d^dglLeL0zjnlR`zO09d#u~u_{5D0=ad@o`HzN1d+x7g6GTV%sf zG!CKY^>Wp()2<2-?IwvA@|J)UqEOZ>L?$*w!F#l~RXI3GS;YBm`mC(u-C0d`ROK&q zl=3(_mqhC1n^MU_L*T*>}jQKw$&4cKr&YFZMIpaYJiHQ6PEL zHjS{1QB~B`aAuG6@a1b2s>%xs*AA5-=V=4(lue(~=YXQ&k!@A&dY*Zb3U;mRKG%r) znWU_OT=o|QER=Z6!|KV)kzI?*_5T3hkBXyA(ZBAL?RliUS+2VOYTsup?z}Av)a-EYpMv1`lDOfb08EaqVfy@$bo+exx);Tx@J=;D0j)q)$ zX69ZI!EC#TUFEYLkTVs9A_{<#5(u_S-jQsn-U3BwsOz4}%OVM4Kqy9_T!oQE#1>&r z4#&p)S7a3sIs+|=7Th!dAX(tZ*hUODv7OwFeV5#4+Lt>d$DCXR_iY#Ww4#)PlTQ4Q zj8(CiAsoG|e{ECggyNGP{82_AQ4FrL)C$2PHB*e@;ibxw^lK8I6Ss!bk)35&m+rQ6 zh>re{kRh8kDkJ$@&!OA;u0QbKG za3Nwn#nTnq^F~*H+t_vTmB6AdcDRN_g&UEQcy72Av>C(_8!s#(Byo>GXv(WI5v{ML z4C>l>T!#hjy^7uT1^&cLO8RGqdFO$|XFdh|E1(9uGhyR^qXKjZt2 z{>@Z#TUZMZJmCL!?4jEpET02UhT+tgUcrMKolu`KKD;vhL8O!(syf%vfJ=voC)J@* z>}PhGX0$cvVPla|*p;2uYi*l+i(O#R;J$GxAs^$GTZkzGZcP`O(CBK_17%axe~X^> zAje0*4(rs@3k9Rp1{mG*%om(Cu!B^KQIyLdcsfs02s>HEr_Fo9QDDT(^fQe+h9%r$ zR)o~QtamR=c-Mw((zi9}!0kRq??wxOm97wS1~n_lakZcqe1=WW{5 z;f4$+-_bhN7n4JWT1RF53*L3>Jps)o*HH37O_mPRj3EyJ?^fk#p=+w5* zD?TDxjI{n9LvE^otcw+zEgapQ31D%SGY4)FmI$8}RD@g>MuXUc&v}}{gFR0#rK`2p zNO}e0>jt3rQ$)SDF)Qe-b@(hJV4LQ=wg zyzY$_x-LzH=HTxduU_lHfA~~vsC06w-g-CQqneq#5d+Z$^MqWZoRpqmW~cA8F&;I~ zfn0!(bE3s^Z6fI*SjWkVI0-y=i~4lI00dTJv2O=_mMBk^JrRe%8fk9fY`L_JQ=a9% zwtdifL6}qT1J3DKl7fV(cfrWL*&#(2x^hT!8je{Pl{k;#-5)$gn0!)80|7IHW+OiZ zgJ__C#ZCm8;J~yCX5*fuiswI6HKe*n0x=ItwiiXpVRlI}3GW=*tO^4eS!*EMFTMU# zP4PA(E)o{j$*#j@9Z*P;h@##OSKdbaSV`nKdaSB-4DPdLLXw%Mnqj46IDZ`A3oU3M zc?`};1C#gv&sfZaU-lFae*cSQL;M~ZXKI%h#3#&DBITuyRd^5Jufjveo+fD>{~iGw zuLzb-uK@rgWbO@AXnvc1 z!%sr;#6E249;z&%W(AD9cra@5GD>{wDiHM8X|FXM^^^Z0bI-tt-X255*dzLGDsvDR zaNQcL>a(9Kd19j>C*e+HGH!`-r3BK{jdJQm4Q0yhNfPYpC5AFi<#r4j*M8JvIwAkd zVCBc+DL~2Jb&mz;0k#K4Ank~8d{7P5z3Vu@N8l#j{Q=5WCh~aVWedAA>YMo2_g?%_REPN)YnbIbgfmclfc# zPG!LbGtrDPNXAr8ALfQawdfvmdndS^0x#6^)X1)Ejm_pAV8EEQlHNIZj#s~Uq^(qA zP%VCIE>cswTet0R9FvBn!a)xxR zOyI>op%F06$t6)v$mq#1GeF)gocYxv#3BA)%;L4ajH!xSht&*;XF9wl9Ps2s6}%+A zJYAK;Pj`Kq2Ygj_GFRjaR@#fPCIi>eEyz#xArSr4NKJ_ZxcsezUCEg<4ZM(EF;M~u zh)km-*&R+lPv2e??^2jBn9L#pg~ijnroG4s=#%9|!G;ewk|1}h%B13ztlZTx1dp|~ zsD=0yku`!B9P`zqMZjoj$7RM=v=%>=49HUGWga`IFG{jt+RRTRrWRaMV3I9}kGeeI z@9rGY2xsH+lBW9jd3F$d^#dO^#3`1!Zk+HgxM0DeXEbg8K!Ah!Eyu7@qWqz%m=_=Q z(db8U7U61qGMkjQmK_pK4EXq@6bV8e--eIuc?ePR585LV2qhw2^A8uN*8LvX)Uc-W z*sy%RF5qc!D62nu!Byz~9n@viIsc;E`@YMP^!Xxwjy`Eg!K<98A1HqorXjdnB;+D? z9=9}ik@OXcuwscvUKgtu6!y52{0HALkm?a`6i~mgZ+SJt3PV)d?<`}g3-DS($3tIG zc~eY0K~rbp!}QYq!wWxD(ZIlpotQ_R=q<6j$5NmpU&WX8Geex1b}eh)XGl8!)r&w8 z$iIxtks;#QpsdG-X|K_49P%l}pA6~F*1!sBaKtgC=2uXv4MMa@`N;VSJ`Vwy-*ts= zepnIRa>HSRO5!ShVLS<~n;pV>h!go1@D{1c4QUmQ<#N~1c0X{W83E4J_j#ppC@=1w zZ>+LwWzpOY(`}#m-9>)sY1R>qR_iKt6bcHFjaqp@4DuTTwu{1og(4sw-r4f!;s`6r zm8Quccn;JuxWuX20#bY?KeY|W0&;GRyMs05G_ zT~3LVaZ7)i%qy;eBSh*^_Y|gmWE0riR>+v>4Y1SW3<;SF6`FUvJW*zryU6nxlpE7r z)E%!u1;(JMWY~bG8uqMhfK#_r?2p6oDvhI;z64R=@MRKM$D){Lz5LGWOJhcR`aRp^a!mPMo!b&UKv%05}6#@J?Tl42JdW!O!4X#aAa;G1&8oH$V zhm0`hwymB}OUN{lEapRsiCxXg&vR%PAznMf&{C^zZ9FeCM?1yOxCNedAg|dx`Nh(Q ztBvc#1bs7enk`T6IjLA5NELJRW&AP8U23MV<|>koW@kB0x_YP`?6YN>4nN|aC$P(A zcccLq65DO|m2B>P^U}w2LkK`O$qD~@x3PwxA_Z?dO^7my;cKv!PVkr$A%(GV=&7pc zO7L7Nd4cFb>P2)d%Vm$${X@}!8@*oCQSMFxsbVJ?mH5tS0soXQnf5e`6 zo>I483TVL%a)ulq)?YGwJ-S%pOT?5eUvhdpbF4qp6jf;kSO3)j|Ju|!^VBc)^ ziMH!I^@6UkO^Yx2+xqb=pch(wD=obK=}9DO_0gA6yD2VRagkGY-Rqkg*27(b3_}I7 zw{XZKA^D+NMb>8?edbP8!PKS*rYgyZt%r!8Xy?pSSfcOro-_|$z)0ZTFq1iC3hQ*choUy- zH5J#~g{aU6&}w2=(4QHkw<`>cu!Mf&`}cu1VPx6#Si;Wjb?oDlc$A^)Ij8omPI>`oE)Qi+qJOe9`-S+rwu@u?X=CjR>wE72}!j-4ISr;KDOF z^B5dNBME)>(f#K6dITOZO2Z@*SXa|~JTRnP0Edy%8??rBN~Kp5%{V$rBGKBEkJU#c zw(CWWZgQHpdm0&xt2w%6(o}gp+`V3kfHnYqwEzcI{s@w zR8sFEQ#oq>OZiVBeb;HDrP0hh>#a_MCE9jdB5O4+QC)6xu+|$oH}mv)uSC-TFF?@0 z2PB`jd^plun?D9YIFP5iXzI%Z^)>@X1P#oG6;9G-vpGbQ1N7-FcR}`EXuhlxYBaz|Ejh^EAr>nm{`X# z=9z{@j{}u-0aZbS;yTtmCay>&aAM%$yt7TXas}PmvLwd<6#nb}^QxjZr6$2VoF>t4 zpMErGK=1X3uq|6^=CWPF5SQtFEL3{$XzowKk?Fz=m-(Vn%KiH`qmLH76`-xi$iu&; zyK=}eE%&kNoB1>NaEdB_2!oD66<8{j!lo>gG#9)2%HV&2a~I-Cbr&uuW^e{Ai>bZ^ z+m;0T>xW4hsd1U$iQNFFp7$=^@^W{*;;)4*P=wm9yenuz$x6-PoqT^XMo9$iFig|S z*HjvTr^SRJ`xCqArxytG6=06W{U5k&Q-D~Bn24{dpYQz+T{xzHjr)xWaJ7lcH^v+S zax-!yEE3x3W@#VY-wm(Brq{TlT~A|yTa|3tb?#m~%iG&`JFAXc%G2f?bWpRd2YMzs znHL-M^rlxmfWOcL1oScv-C?x+?0Z$Ux2|YEk3?rLiGwbo)Coy+O=^=*Gm}ji`L{XA zlhfJ?vMo_HxioZU&-1?VE#Af^jUN5e+gPN>T{hX_1?cIgM}6sF=Ql?wspgO6f*fIgxV8q2nO+jPJx!X(K?ts_ z&W{9v>LQSE2+wHgRfzPS%Y6;8=B3f<M z+XKCL`xAwstv3^Xx%THla{u7{_@x<;82uTm4y65kz#q&r2^@7K*d!D~JG;#85!yp# zZ1=Q_(-jnvuP8bmqr*T7-Y-|BVNn$|5h%}(Hr$LF)Q7#dmV;w^DmUy!^cN&d`Mtmh zCwTNYU0(Ib!u9`Ds@#BStPxmim?NluhFS8brqECipQW`0449V$j+e(nm87B{#CW%y z(JeltzO1PmzeYRk`5(#hmhzA&sLAz?clvsJu3)P^i*=ML0yNVqLBlfffx}+7u61c_ zGtm=LV2u%hx`kRv`=dUu^_P9;nwhB`yoV5VrxIb+EzUuke|{ns36Mt-$7g6}rxVtS zqVsBiEd3DzmH6G8a5kp=-=?I8i%+LsyiQV-*Pw|}6<+!m?}QTvWc|CssODFJ(Hzd7 zGM4-r>d&zAqBG6Fn67=)JS?jJ*1Qf&H|Rxw`Ns)}7&Bl)Xt)C`VL3{B&rK6&NO*A0 zssEbq804OA)}hvEWG}(oh(C4tT~cGypF0--`Wp21I@=bCC7Q&&{-S~`zc|JHuc*t? zy;{yS`er7~uFA+EIYxg|N0>es8`&!WeYs=x@5L>2~f8m5iQ(W zR2dmg=p|=T?xi#M65>t(GY=9duA}gFGKeJW|#4|nk4=l#qbATh0waXVp?GD{{bRe6Y>??RugG1*WX{wt_T$3kcsFAWt3k;V}Kfje$Ji5yk=xGFkRw2s;T00gmky|=HtwBZ*G5rV{>mlN^G z?{_J2oaHzxgGcL+Q#5~pNXv6BoJrwVb`kzyLraF7iq9J-ua+0oBN9X~4db2-ON2>l zAchY=7A%^g-|RTkKUjx^YUXONHJFBhOvf*3Pawc%{ZnAuF2MjWW2)gP%_Qdn2iH}u~ za{1+OVvoL~W2Mi6+5=30e?7A6Ou3Mgy9Q1IhQ;Wna{CwiN%U^M4$;GVs_;$LtN)%0 zWo$`{FI^Hx z-OqAu^X2y?0$&t!Ua0}}F*wS~mFH&jEay|BnkR+A|2-PuFoxWGd$Qt|O1;rO^8So9 zuW@PQfO8dg(V;0RBm8sMQAGXVmg>&O9l_kkAGpuK z|KCuU_^TnBk8`Sk!exl=L%L|N#tc}?&S|uTI&89RNaH^aiYJgth*AW3w|e&1i=pq+ z1VFa#iUwdODzcRMk%;NL`Slni6ijwm!#_Y8%B&W^|f70jM&D+Zt^I zoCr8_U(Nesf@1jA_=A5zqhV8;GulC*lkm^gKc5=T?QUWMNRczUZ7v9N{4J^P@ z@_NTi;C=`gn^FuAIJ%GCI(kz+AW{V;Cbco}du7-ZOZ%kXHV9cj*Yb9s9^?A>L&w?Q zLZW2E@yxe;V`Q5Dj`Ot*4I!TSv|UUKHN>}V_hxne;}3YN_Rt`H`;E(5>;Guq8fT%TKWFFba%gbY6H}3hqNqQJIW;!Z~~T!t3ka? z3n|c32sOAuE6k0;u@-Km`)n5!Q6?*RGbRdof}&R$XTR@p^^YhaE$r@B9RI$&zgzjw zk^LOc%wvq9;ljzLR+J&LWA3HpaUhLQ+IYwo_$ni(>JhyDNb-P~A;?oKo~sc(f1XKq zx=byzYi()fG-YY_NIuk(Ux(!(86l)t3a3S_g=cY|ccO}4T;a$;yqvuwAWDE&K*R&mW>2X5${ zJldUp0_~x%LBK8YaZhNAZ^pb~VRGR5g=+fSj#kA{s>18V+#tz2D7{Gg zv=KiIkC8sVd4_&In2}9O!Q{JBoO<6>A>nBg%!r}CJg2&*dd|p*PR<)Ju0&k~o~(=tn8yMn zI#Pg|F@vF&9s)%Xn=uDkGnr9&mkc#;oW|8qV_W)oJ-&RFWEhY97{**D(y8mV+te~0d?scL^c7H|}*lvveS zm^m*)$EW&3?~>6l?6ko#4y6CtS-(@H5i6;wMBjDi4gRV7Q=R|EW zru`Lu^c{77lBhf30Jrw=-TY@5C^aQ0XKH_T{q@2HEzS zy{Uj(*I~h>`KVB?+SGgp^BD-rhttABQnjS>zraHG)JJR~P44E%3Yb9SL@}-NS8(D< z9>rgbMmxK~RApxnfnsbO>4!SjYf#kuI0N4EGIy&`bc$&RtLgtr`zmiab)U!Nh;sY3 zd3YB#FgXl%1UXd^Fmxaoh=*n|8%@>rU>#hYQsp+wH;3MSMm$m_+)3ez+2Z^4#Cj4| zxuSUhmGs@W>jop$a$N?Y5#}(NclB>MECD!JGr+0Ep!(!54Up~wCOApwf1SYmg%;V_$o6w)?Rd_+MIYWf7IT*IXy(^mQig$9ZD{wxEv~dgvSHey1Z`{5Yb8c6EPW!3)v)0!ZZ;QSV#Vkh5%oss*BC z@@e0ycQC7X44378*KWjMBaUV}U1dQIi&r%8*>y;b<{If)2loht=NPilyeS!jq2`%#J+A zVY$4UDdcP%YNB)wv4x~LZ0|>ezo*%!-sR14?`!Qano}3mq@28B70|6c+hkg?Xw7mB z?)(4jT_V5QPP5f+G92c%w9}zU^sb3}6LLphdVE7Xv3Z)0ayh^=tS6CmY0C)1#i1hG zWyaV1Es-!7S>rCu3q@i1m}SmknS}{o3PWfE494W4R3W=0_3Yd`t?s{QAC{(iSg=D8 zQ9j$zmt!1RXBPwF0h4b5gyLtjhMvutoj}c@-l#-UEsi4)_$L(I`|SqGc*p88`M!Vs zo+5kQsD=n;&RTrBF6+cFiVe_?%4C8-}n4BTz^^#x>&wqW#FrMiw zbn8-JV8mLqR2YiQW~W2cBe>xWt9To$pPxib5Mu+zTW?AYLir#0q=aN%fBRA0f;jW2 z)tnpmoD-MJ3ri(;IMu<~G6a0AgB1ihVK>|lP?1_d2qM1+0YxQEdqO>pnctL4Z2sK$ ztTtbeB4}E``xl9P575A15M0K;K83LSgxCp5U-2>eBA_`6D1|>4P~K9G z%hD^1p5X*Gkwy46vF;43jV0Y=UQ_23B~=Rl>}tFY*ZCrmk{YDFOKMVFrm)M}sSXD4 z_%(`~v*yulM)~_QLYbxFxw+e_pX5xme_K>3UV*swh~kWG85G`-^3S}}Yq&_PfhvYO zT3VUod(^X5(kCC`XpcI);tPLY^Mkmo5xxlm;_J0OH8oTEx7cC~GYrW`taJ|P(A;vt z>fjd>F$Am}$ybQGK?$~4Il`)bLcpcUwSOfeK<&6M?_)X0j+XaLpqn=IvSA)*r$h_P zv73?N`-K(%wHkbe{p*yH&3S}0e1D1s(;|O`t`;$@-od$67ge<4EzqaUuorh;~s<>VHYp% zg|&fKatN#UHBr)WO=jcLl;D6z5pXr9*42hzrOO9)zn2R;xd*w-#9avo&|Hv^6*#79 zkWj8*xaB%z*eCy{QnW{r1HoYtC2<<>u);TZ*U97d@Mfh{Z3{y88u+d|nFdANbaNp! z7s}0s%LEU7wW-)P)@=}LegZ@otO?3gT^7cK66Mv%@nGig;fH1JZ5IhU+>L{z3NO0z zz583kmq61$t;z7y>~`+h;UmMuW991UBuP$%XInHa3rC)v1&Hn0J;OZ`pVO0fsH1G) zGa0-p>Ur_;fsjB+;2aQuMSPt2`LaVu(;%^yo8{`6ShqjZC^#H_906XVEA|>&qRPPf zhC}+Ja526z0u+4;H+_gS$F*U=+md9|W~f`|Bmxu_h)WEu6M2+9@-l*3sm$(lUIC8T z0n8ytc|KwX-n|CV+DvYJWDp8vOx$JKX8!lrr*)fs<;&NAcW-;-S|aG>v+9 zRh1=d0aB>iD7G^(0?Nf*1&?<5R<~t`7@O-bg)|99l{W%AR_4+74P=5f^kZMW=X3sG z&&bn8{&pHh!Pxc*$fcGdoi>3UnV+C-VAf@ilP*0#t%||37vnpIAw;hd>>8{viIz{N z9q2+?ns7sEl~L8*BVf6YCArdxwezbTHMs8p6(Ld$MNYJ*~_`rz%UY~^V|^V z>UYa@>-T3y>9+=-gilvddS+eWfmd`3_d~@El(e}F^os>Y#SwU2MmgbrB_sQ72u*EM z8Qj@a37xWNV!m_pj7a^6!FIjYlja;SO?+k`l&7R6exOVB-06;^ZZ{Yq&R=s5vi#|r z>mmbOyVKxt*w!Uey|I5C6WcX-LL>flTS`UJ`MU+GJ?bae@?IgMVb+!&m@%8(xso{Z zUCxgn1anUI_frX~TIOpgEf8*PykqX16sfgUuUd%-+OpICaM}fbh+95(zsZinrZ%Z%d5^oz4HUulM{P}_=>gxm{?ONUR=PZLMggzQVEzx z<>~!w8U=@uO77b$Q-+kp1Ei8Tz_!3r7|H9mmN5vRS}RUQUCC2^>ii zq$WC1-EOt2hrzFQ*5Ha$)>N>y%(0a>pl$Jmc}{p^o>wkxn&$NF z&&&x32w~n|egKWJQscW+EWcp|*=RsDFqNL3pD=wg!GQ}Zf02F-Lb)tciCQPu2Y_X~ zaiE3d)Gvg@uk#A)UnQ$7t8>o*Jy7pzMEITkdR!G3M-E<_js~ZXEM8SgOeZRMSo5uV zneqLPv0Hw%=k{+ANH!I6PaqC>Pw?>O*EPNmRmp~jaWs}hYJCb{+d#MUb(QwGAC+kc zqOps7r0p>bK(ABOz#xx%6wJe^QC^|?X1~1d@SfTe51&N9BH07iaD2b#arS~nYuD5f zO_ry*oE{%Y+4hM zQLjtNo->MI&}%DisggKwX^d_6fz#-M>6&5hUgfLWv}I*7Kumt!jd6^mf<@f9g1W*k z5&zOsZE<0K&vBS0Z*z>h{cea9FWqvI<0Eh{mGmN-W}^7rfaBoNluD*cYD{9U;V~eI z`$gk}E1KEMNETfMHntnZMxK8@00{t&!LmxIgvCxTnprY8cw;41Ja!4@d5qKUun6x1 z1uu|HF=Dha6{nT3J7VF>)AJg|R2aM?%ShdJl>l^aN5hmIN~khpg=V7Bv>7?u(E+|i z;;KIhs;Urxc0ijWKsWd-9ZuaVh;Dkcni4Rq(^6>V#^!)AKLi@}Sj`>pup!=A7J@nb z<^rs`>)Hpv-sU8DFGejEp-*Q~b%Q!e%x2Uzd}590Hu=MTgWiN@`@YpNdHAot&R^m5 zy9E{pUqr&(@&kLZ1x!)u+pe$^eZ0%Z0D`i@Lz^#XatcX4hYJbRIA-cibcRfk?ZR*F zSZNxR1s2L&hN^T&{ocNk;?eODedo$LB^>rQa}yjdE?47|?N{Wna{;|@WI6e#BW;-W zCd(r{IQq|i>7P@W8JVF>#dr`ti&O`;$p^^=j&|j++ z`A$_=Y59S6ujXye!1@-XOJ;fp%WHs6C>Ti)YrNkBf@%lUQ5%!x2~`C6NKar4c@BL~ zmZmE{bCciD4>l8TM`=Ot#7E4VEcfp_l>q8{j65fRe1I*Hcbb$utqhFXqY#U)xAPc_yG7h%*U|VKNzcr@GcH{X&M>$4s=vK{bbC)a=W z!lrP;NPQj=DKoldeeJ2Mbq8VL__>_B_L6k^-GSWh3-*R1x|a#4JLs_WltpA!q?0)U za5L@>>cV3Q2<_fRg-z6mZPH5r2=@I^N;x$fyrj|?K2UAmkD>*vYv#F#?1C9HdEfd; z!hK=p>z8++Zh$!l?(_>BiW3`XJZ<|(`%WjZoQ=w-0p|}m{e_uU&VGZQ${?zlpk*F* z$Nt1d9~`@TH-_5uXwiB8o?)q{`(<|v@}n0}3zU>(9#JykX?vF_s1*C#>WkaR>TC!2 z|08>Nfc)dtKcaQ*YkQpx1L9KL8cCi>wH)itDJ}v?gRHSV%eM9y@C9fLqcR>JEj!G9 zkFb6>>?8y!Em6602$X~cd>F5tfSJz~J$}QIkNqi9-CXT1iu%n(yVdwvECLGnSQe(= zl8PnCsWKV1WqB4k899B}jRt}t5ohkqznlO-~|yG=mk4ShfCv3K=Pzi_!b>|&>IDg$ zyMNK4BAT5o{o+-SE9Axci+bY+)tZBSyCykj-oE&%_6k%G&1~@RiNWIR49q=~6{q#6 z0|ncw8Wf{~R`{)SQSmH!vUo&GGEL~5c$c$vZ!l5O;nh_K@e}tvRto7}KR!qHWxIfH zJ4R-m=Su96Hy$UR*$!}TYp(9e-i)m@S>eL1-$as~5Vyf2WiYgsT%iu9u~nW&vU!n2 zkuQ+GHgPeCzFAYaRqenQN=z*{M|t0=e1|a_scw|LTrk(}rp1Q?_zz5@0|uJSh9EcK z#S^&JL06BIwePwiXhs6mDWOn=n;Lb9W2C==sV^jnbYtV6VMM^$o*Lk_*-K_s5)}w$_omqqZHCsHj35Z^r z$k)(Y_6=m%fn6Yf5%VZsYoFdmruC)xJX_1TNe{5nVv(FhFw&Tc%Vui!VemV7-yFB` zFQ%$iUfd2l3k_jvc7^FeEJO;mI9EJ9D(3VLs5$_OJ7!KjLN3W39C_6w%BNVX_m-++ z+d(?}G@p^}q=;mA84BygdMlzAT+Ik!3Rk+s}Q#Wq+cx6OwA-zR*w{`Bm3u66M%8lSjsG8-TC&Z@OoDsf%8>PBBqm-?#}kU_U%bapi*4x zOK18^G2ix5CKKYi!8PJky-B)IjCEc7HOwud%jyfWrq2|;JhAeMcvjWrVU|~uZLfWn z>W{!kZVs-!vim)~fx;a`4AsPdxZsYQIVXx!|MoOI*@LvQbF%5eh8jUA@bv`7Mb`J_ z;=N?&<5xD+(u%jC)Gg%Zl$g8IsI&uDjad$+pQGMoXv}=Y9jQ!-+S@`_fHpEL1}3B~ zmv|14y@*R=?k+K?6-7{s`>PF*)xw`J-tRbsMO3AkDYhbe}x@%GIvKO`3 zT(r$P zd?Zb^D{TgD??Yd85Trp%zdQ$i2zvyD*R>kt$>^A2RGJ9&8(;wZG(0TK_ApfV2oxY= z&ZCh}m2NSiI8paCzmqp%!c+4nM3lSKg!KxlOqe!uQCgkWFl zkJDc@5Y1<2;kMi37V& zD?_f{QUr))EdO`Ja+ftfyxGkEFvUudC(z*TTDz2?MegRQV(#ag7Ja`#&?i1zanuMT zyL3(QnD#DqfbkcqO0{%q=uAB`+YQ!@T>v=$`Y&tn#BqI$Jx+6Jkk2iLQz3Tcp)B6z z98Y`dVkgAX^B_Jz1xY>M35nkWgl%^-r5j3Hk{LlWV_MCZpgF7S@!U*Smw(3+=lnFO ztE;+O>MP;C#uQWNYv$4bAmm(^Z+5PeLq~=A50(im^Xmpl6B&@maarT*V#OTyzfN(r zWhOCOeB6Ip&78`V(cWG7^e57hWY!q7!{Pkj)vl!-#u)va0$>fb*6c9|zdM1p`Si~r z*(>XY3Q53TbE(!NSP$ya#U*Adxf;gW@dPH2dm37P;7}P$XO=yHbG#q*+#r9^5 z8S5UqDv|r*)f zP>Cwr-Jy|%7G;UXguK(N1^6@Y`%E*x9`k9AL;Q-SnlT`rim>{c1u{u4+`S)(>WIIN zYN^@B6y@C^t(~(GtF^1XK#`Mv5ca_PdfQ40n2^Yb-yH?h3Hac)UvF~SHsn~R!8aHj~iR_7K=w>|7&3j);Z#)HCXIuGssbBm2YU=;0nvb`*d^RN&c;VQM>y0_%m$IJrSzM=jVKx!erZhpx7m}&p>dHYfKFnyFL84t7v7Ijy8`r#GV}F3;2EV>XBfOl}uQD4FO8gZ2AraLEDZ30*-Ww zp#fg0WZpXU$C=A7@s^p?CAs{QBSkI%UP7${i`U?Z-K8GCwH-NCxx@QFAd%i7Sg(x4 z#Ntn^*`26UuUjA%G?>hQ?B$T^z)w7dAUJj(n4r#ls-G>&f693lS5v2m++tXa0rAFt z0~d_V#-RJ4Bauan`t&D@mi4<~?jez$ zZbeOZZM!_tmLN>_zQFDln`_L7>gc9-Af>TU2zAXWVT` zOK0FbDD~5y+Qzhsp^0pyk^fgM%!G)h0O2rwiA+j*AKQ$OX4w|ypnMBT-ZU8S0%k|d zh&(rlyD<};dH1z3&=Z|wxob)p`A0xsTt~pOmfke1%DM`bPUREfy{XkUKCe-3VuIm8 zrxfqJuQ{R?Arp@*qmT|a7Eg=3t{gJqP|hvsxAazOLLAz`U-}e?7W}7=1?3mV>4qSH zUpX;>EC=*?1t}a9Z;jzQYE(U@_L5TNB$L9B4sknBNrNl*3`)k+sjqILX^(+6?Nshu zUSZJI7WV>>d8s$fy0;+-sXO+~8|SiIj3^=1aMhVEC3|h`1+Mh**%lJiWClN0AlgjI z@a2NZE8M;%6BLwx-h9lzi*;MYIbB@Ik0iE$Tttv0(0}lHHOm9DkT}}#1s=l7#8|>Q zAnKi2x0wXT075Cma-a87<0f86pzpP3GlADcZBFa9y?X|%?)s3UQi75` zOQjAW2%bvHmurzU1|6q;2LS?y6dWDqH9ey^!|k$CHZZhJt^4Dn`Lc9NooMvp*NN$c z_K!wIj56_6OfcE6_7m>Kg0+~WYFp!0q+X|`%T_|b%@wbox6=7FzBDcYK`3Xq@ma+F zi^EYM>H((00$Qn4lGT2hFb#+Tb}NB7SMftd50s23(lkz6%rC>hnrbkMq_f6p#@bhe z7Gcd*MANB*)0)A^U4=9VidgvcQ8grIA;CFi6YH)PZiDME={{-KAC)-O7u?VTf^~yd!rc2a+q7Pt3Coug2DNno5RmF zk=82)$N6{?nEG#q0A5@IU;focc%??}j`jHHZvqx1a8Fq)J{hekms#pVjzLtyQ>$k2 zS(vq?B+@W=*>$?*h&N{1jZsV|Ijc-vOn z9qZ9mJ54JqT29eoKz80)IdY`n%=yy@_RgK={Fsqe%g4I!#xy*05NXL<5!n9*cphS> zi+Kb|6tGC$zMQzjJ+b&=MDO!v?<6}H^mX?7Ogs)lKq_EMK-~E@xr@Opj0q-VsSaKJ zKpT;s&4e+O|3`stkHB8a6P)N%_ft#5YN8C;X$?(>=ICT^rlNf_Odno@)0jMABCMh| z)dWovNLPo^g}XRDvluL}n+zM@OP-v5e!{mTn|31=dn~k}+GyltcCmC5evtKy#P|Un zHj)3qQ2~;q-Wc*ftfB~F5_{Hh>GBbRJ?!qtU4RH{A)}&xVGqKJh6?{$>n)zEmCnvU zoN7>Np%+_)-74Pz4XlssIs07WS?Pm9BlZ({cpOR@t^Oxd z|HY-KD>bekVX0+k!fHF$qF0hmz~ZaYTtSq(Y4a+UACF!~IRb9I;z@jQ($|vxYDoU2 zyA@i5ri~#e@gclnlTki3J`jWJNeJTt|CyfmYUdQ7@FhW zXRZTtvxyfWC1!|=6pXh0sdhEgvv-oDiAk0f09mv!!C}Eb_)Y?E3pYj7eJwLITcRj@ zKVr3tC%@>D*OD2kC3)2!zKI?Tv{>l-DZ?B)FKclXK%J#WSJ*IHP3ih#28I~Bujtf|XjQ{3>fRHiExD85`(bAKq zmpMnGxfBK5H}^ab1uQC9{_G_b%w6_F?(On#OkY{W=)tXw`?Nz-(X$sg!LH`rSeSZ= zO-VW<%s-BOZ8*6BznZWju;|gsn!7Df&B9AWwr4Qf?c85q+^=Iz>n?R`0O|M8mjCv} zwgvs3O>DTlv1IEpf;%0lo^$C9{B4VbTxsyUMd9+fACYw#Y-Z_Cpq;6dPg%@QJ8w~F zp>C%-M}g?2Y(6&nso+j$Uo)my2+FIlMLKO@v?PYYJW4K0Subw(DWWocSg-MKj|N8Y zPELrajad!}m5ro1dzn@A*5dxBvj69Jq=Y>(CrRBE1Mz}rE?t?;3iFAq-~SX!Fggeg z1r{ErXK-W6&y|`gshgm0TZQ&_-e-FUnEod{-<|?{ z^Y7#NhhZc5S7-!~ITK{w03*RF#Mf!Qry*Gw1$j_R&<-{KWH@hTIv6|~c6x3GBrx4n zoUB+|?RNJ<)+ZwMNsIGz32DSwdbl4ddlJ0h?HGb(pV2ZVo`&Rt9jnL76whrk+=Gh( zpUqS&+WfY*P{e+vKr|_Ed+c0eYg0H!-U2GCrx@b;R@L^F=qnhi-7mwUm-Mk>NvZQ7 zSEGfv7!j)?k?v#f_=8!+UjS*|I^FiwM0O1T`_niD_%|?9(Y%PC2hwG$scUD0e*(;D z3?(SCSAg+rCLGt~c-?fK%_O|j3Yn(_)RWgvz^@_!`_MjZGZcZ-`#LXa=;I&$&m z#fsFOc5~o^U46BAf{BjN__hX9yWxg%m5n`}TJOzM$hc@zLn0yWUs(nvKL*Jy`{>%qL)FP=c&d~=9o!-x_JVr-3e3lb*0))hC`MtUKt(6Yzg=g`BebE6-DpOwE*yK#zmF-+SHZ)18YFI5Q4Y4ZHEy=CF_TY&YoK&w_YErKD|- z63A*O#6QohvG>hZBoGDeB3~gCn=~n?#T`*Hig24a?5e?O00RjM0G%X*kI62>%4^d9 zG{6s%CxMTTvxX0;E)qOYtsivyqWQD3hn|J}d0x@c+8z#%7&IVY{Hwx|rXhodZoCjz zNRO64Y{~Kues;e_)a2U3o2ksiFj*qQW@U<`{wKbJtU->UTOvH4E3nf78m{=JmA;Y zynGnj86F|jU49jVhvhG2-mIb!* z#qe$%ZLcrq=X(y1tT7%TBWb^F^|cxNSEYH4K!G&+y4Y}iHxQXQI9b|JU}*E3=#xz6(Tao z5{H8@I5iFcf~+cf+#~a(JBAP$ouEn7rxFEY)^`UaALV(K!F^mOQ|2xKh7b{b}Jzsvhgu~R9k3oO>-jmzR^ucn?!g}7k78D^sd z0u$expx~Ix6JnoNl@?KXmaWs`-gxM<(@nEtlNXU3Y&>|CdxE)vjPH|epW5Rw^ zO81gqC1C#`N1ZWa$RNi7z6Z6#&YXz#b_XAgTl$05;F>*~7BTAT?Sf+JJji~qq+D|d zpyZm1m(iWI8k7!g zW`N}U*88jrZv5 z9lD}Ox<$-@@j9aNo`$AU{He2-F%MHg=O@j37wzIKm3gc*rL?_75JjJA}GS_jLJk~Ap{wZ&P_O!i0t7zlClFKhz~c9 zC9V{bH6-hCM7)p~Iq+geb0~j@7y%GLBBo7N{nbk2WOCjAZ(b>?OlmOrE9fMYOTtP5 zu}?CbHZ;~(w*UvZQ_)ntE!B3BoJ@nIuX2L?X`$qIeuNw7QCr+syvyLC)T%mD-RSWh zhIR3*1OyGCC-WEU)&0A=qZaf`k35!8R3p`vJyBscQ0UQRUbPYXhUz5Tu0(e9z_`Df zuB%%K@nN51zY2gEbn)ZLv`^)zn9dG7qQ+v<3E`o;S&4v6#ft?mt4;7%%=qElU zN(`R1H*VLD)4HR_Y{o7W84C7UeSh*f1fOR3Y7oEpo>kIB3YQ-^GBaiYBXw2#V{+C% zP)49FS0s16CG=0^3>wlad>Arjz7P8vh5-6aaD5SA1H8TfE$D0#k1436C}T?^s(eN3 zIF>oyeW)5;;((RwZB1}?mXF2&s)G^b7Ua2-m%O(i4&b#&`l?!W&Yx*s1jAQrguo6d zjdaAX3(pfqRb*$WYL;J?gzu#Td5LIMC5Y@C9JY=nz9hQ@@gZAnA*v1G-6R!bM!yGu zU3@yP570gJW#KCyCnrcp)xld%uKmnj(-GI$k3l2*ABk#_!EzN#?Q%@MzbYufweo-T*ieZ@q z2{>BlD|84u%*#Uh`aY>RJ;dCwUs`>dj@WEeeTK%-Y?S1tORArm(XPNW=NbeKOYiHT ztDk&@V>W+{@Y5IEjaYe`HPiu*YT1OlLIE;Vtt}a zX0$t~9831hjT%h=>HzMlvkyOGg1%ch7{G%RwlaRr;Q#&C7m(^Vvo`OxQOrJ-$5LUv zK@{TONAJ|!gK^r7e5gDopw5`gHPSuv>uBCHGKtUxNOG=8VC`qh5Pit}_g{mOS z1xFL6WkwK0P%VOA$&Osx93dh3lM!YkOZ$eTnjkJVD7h`C*A0<^-? z!CMO(xDW4Z-gT$svEUNab7{J2Vx{;|=_r#2Y8Zw;TU97#vr?WhT9rcf$rCkw;vjWc zwm(GjU|=U8nSZW%E{7K_YYGNw7QP(@MIZ6`h)T=sv8p*Z3#5>l{lnGLLZc+H0}xGG zIfr>0z!S=rjXHu9+`v$@gIp3Lllo98c z@79z-MWKO}s+h8)Ka^-BMM$0M8Z^hQx4bSKas?#}Z~BW@Dgx?4`e;m&=L>PR$!>;B zU1|H>faY*&tdQ8Cs_LT|pd$Gar}6Xjgu zbSXs@)*Qarc7VuIAKQbPNm=3MOt$?9)m4zXduh>VK-s ziUfHJyYh6-OyEWNSDV9c5x3ttjRw4KV64qBk^gsx2;uS`4;K$JKQ&rl61W&3on z`XXHuXXRBb{<3nP38mx_C(78uqu9&EC!nO7KW{&aI5_|8$d_9C*z>_RoY;Krub>#` zBkq_8@k*%s9nozKjW{6&C#-+8V_glG?bsokQb~)HTbpjV9BosMw)brmE+>fb@RVX} zohLPZSuRmFY3ZWl)s7=p%Mdop$O+R<{F*UD*&w^3aE3qNo)9*jmloz~v~LAl>Ygt$ zmSj=+IUV`AS=GKD3M|q&*t*TN@cT&z&sEm=Stpn>Y*ZRpx^2DhCXh1EEg@lB7vBkc z%u#|f5tdy|UTx{4jXc>rNV=djFId+;wZiCzue`ZW-Cyi;1(g8YDw`?%1}hZtjCuti z|J!6=FB>`K^afo68Fp|l+i+YJ2ZLYJB3U{!nn?ded4{0|D^3cr$3+Gn?8$O&-pH;a zV5FW?a8hSF~+wn;N6_3QTcsmxO#f^w?6(%;p;WilwKJ=NR* zJ3z$0l+E~t9OG_KCO~8&6*k91L*;rWb!297IIwJYJWGZ7-3u{f%r{c!n}WfRNP^8N`POA)Vjb8&%+b_>|66Gi{jGaHs36bL?G(P6Jksu z?9a7pSYs&$A{S_8vb92^Pj+CFJAxCiA!2AJNwRI=_JuU%3(cdXBI3>q!F$6)h~t0u zs(yt9CF-2bR^n*#f=}OsCz_0xb84;rb&4eA6|=7&ZHDQn+sp$&AW-t{9|l{(Z#JoY zx3G%r#th^N97EkU#a^hqs5m5e&he4o7^2~|UNt-NZvnXep3FIrM`2wJFRrv>LufG^ z1mS$T?8b%52}U{BO{(?eofeXm$Qb#v254kHf+0$`Y})YwEPi)nq5`pDDL)+|_<|vx z+}`%KK#LS?4!0J@vQmPe#IJT3%_i({K3+35Wuo+u?j0W04_Olgs zmdWsJelm$-2uzd=4-oOKZ}SUD_vL3j>{EVI=o*8Tj#=SXiFd#lSKJ^Z<^jX+FO<3K z4nrTkCW|A3Zh3tmz?=@1-Mf3z2Ip?k;9wrHn=JW%WjgCx0zzGJm z1{)0aCYNSLd*_BJQu@^3TLvK`bF2$I7bJ`OO$uqG=yW#9$hWr0LObsp&9=n_#s3pL z1&eDKXwSK9z_hKuF157*swy(qTIMSlc9_GHmA<4xRPfiJV}=MuVXX%sgDL|ur54!h zP<@jj`bIA4ZlH%z5rzhdd9Q!q)RiAXv1ZMf9k4a|`Q1%YTHkqN!hARDLCVKU`ms?D zPm+tiI#~u?C#^r$;E3iiYW9}u054x1#H8Q+aJYZ4Yq}`JIhlB?Ijn2KoTH8JZieuCkVWVo+$&#?hBmelc#5V+E`w2Ec*r@ud?M5fC0wo zIS^wWEx0Q<9@a!>(e8pD>)Kq=`~mRl-x?0;G&-Z;HwKn^X&4 znhJN?yc(C{a@)8lB&quB@tj82_$3m<&lY7DJ;Db`$n^!hjdhY$WTQ~sf-W?6h?O&% zfq~_OS{4n|u@nQBqx!UQ~Ry z8A_eWe0VuGyuN+R>>YsAGY)XiVK`!mMP|BMVd|lM$jXzu^|XH-C#A?CntE78ETUu; zH*In=?;&Di+#fPf)$l2O^$43gL3_noePkWV3nk$3Tog>eU}N7Ti|Hr>d5*6EgcZ1I z&0to{1iR4?5UFVi;kGu|x_?br;4WkpWP%GuXt|ySJvjrjheDsJN9ikjS$x40`{Wzi7$^()3*p_Oqxq zpYlSM0KNohP)b#}H*@+81|vK0zrK5sw7l z5_f)#fjICgnh8O9=@VYwq97ms5N+i}8w4#KVSbXkOjX0SFEQ=2w0vvhUt?#IYX$Id zT#>t1RZ*Q$dKRq@NnERmXj6vl2s~y<@bNNvF@TnOiIUp8@@zNY+HWCmOTy-rB5lff z+=tOYF4a5dQjR%|RWNJE;6iry3!UY%FYbZwX)LqU^6fxY?sCW_{YdcGtur&nvH^1N zBrdng8X$%Q1M^LZ5MSQ{%Iq5kuj=u0TvA-W1a=Riaqgu-!<)>HDw=YXMj>7DhEn`$PWr!&BMj<*kiT#pY?;=DHWD zMg*Ny%cc0G?gM&X0XN*JpazByk+OQ`I3g4rJ37oF$uGm+EzfX(#N*;r=>Rb{d*s;+ zjMO#~CLuwW*i+Bk>1AaAu-m)|cB&D)WLC1XCrKz-62PJ7X^!m+QgDU-Bf8*lChY|) zuop8^Fqi2B$m;g6llH_x>bwx%Fp(ZX>b|+WMK~X2phM-ylyJ0uZ}6X8SB@f|5zNl! z9hN4haOC%S!a7=wCF5EkuUTUbjO8JEKA!sqSGr40zT=ao@A2@;144frz+*-C!BIVw_`8xo@c0@1x7w4D{fU&n zb7!}jmr^DTHalp@yP82fxO3D zx30TMz5a~M!=3go10)TiWSM&f4cdrpqqr@Q!l*m;=V0`@$Vu4QC5|HP`n6Kpb~6qj z1-#{!#}_zSha@cC-x^eTO2e@j$#_kq)Vt1I#jBWc<=bJaIhj~awA#+WR)C&XxEyh@ zI2%khQ(;ye99JP%+#*1tO;#rI=#K4Ky1)>gnBtS)zBdX!Zmn6Ii+=Z(A`{EA2-mHv zb1F0LR;vzuJ!eO`=q+R=T&r@A2MZrH<{7t!FpR3vMF!cbinfNT(0Gfn+QJ77EuJYu zTB8?-?K%Nm*&QTxKP}{eJO<#cV8P*pL8GDizuKz2vTsX$3tE&sDue`(=f?e9_|D>wRMX*C(z% z?@;|d-?U;CK}B!O-mxlQooF;9RvDu0oLX}BVAl%e&rO#|nYZ7_h7M#iLvdv z&VLQ-hO`_dG!HQe65s1Q{GbN2;iFX-#`@}nO&^$m&Txa@ohDnXU`WvWJ7{GJ49k|K zOzsWZg<$oN)YLpy@jeYz`#(+_;WG}Y=9f#~Df}qX+3#IlAt@3BMNWU0w`G1J^+wXk zGRJ_-1LTEfE$`LlcNH>iRO>jFz0`RYoJ(-^N5(>RWyq=Rvro2{tM=l)U~Is3EhDh~kkpuE*$Mfj|4b{#J{DsZB1jY#sF{JSH=B z(b+Z@%CC@h^UP#9V(|gkKrQu)ArI?~vn`wFigAUlLENQvHWXEKdsi8J3utpEg()qL zG9<0rdn(UYyLxACaSOm^ULbnv(|R%--B->X0wHg{KNZu;8kkz)R96Dju^Yipag1kW zoJT*+I>_q$ue6q$waHpd@uOT+`8QtddxtdR9LLexsUT171Ev*x?sLgCF_Z3u`Znt~ zNC4w#-9UWS>4DB8zS#X}O7#@XETs_DuW?Nw%o zS@U@&+IlR&sEUPxZ^Z`J+cWr&af^d|7xkwy)Ua(h)8ly3qe${4Beq0+H20iM!0ToB zS?|`UAoN^<8n!!QuCi5KeSBVsg@wB7U=d~V;Q4Ipt7PC3X}1Y?Lo4xhP;U*^BJ5`I zkDmm2Zv_YvolbE}Ln<+|u7s5L{BuG%a-&E}thq0zp}c8w)?djlbkprW%3=0v7Op6~ z?}r81?k~ywRq+P7Ng-S4WsGWxYZ3;}r*TzA1O!!{HQi1gi$;r50k*B;4W9OwUq}HD zdkzgacbU}tJInjz(@9FesMV~OwXb~Q&SMQZoMOk(Dj-kkZOv&t4`m8Ap4MB?VTu&+ z(v3P0<=LLeX~TzVWVl;OCL0$&w!NW2Nq%&GK$q41x9!r!4Uuk9o`Z7w*gcFeMDs0n z!s_2i9$DiZS0RmZe8Lz>OUV^5SVLBZEL^nRA( zL(sGD!eZwtA;nxU$*r1Bp^Up+{gwk;-uob9{2lGXLXMHg{HM}u8q1R6LYI^KhLQ)F zCZ>l;R{p-vpLfPH|4;LnT$V#CHc_qK0=2LCP*lH|Hcl>DL<&+~Ide9g>!KVQDLj(C zHPI0t&|r({oQ<(E%F&I9Z`ts;YeOm3o%U@r(8qzO!mC)jl;e~p%@t3H3Gfzh0C>O4 z)Sw_FN7~aS(n_UGXTu=}=NJtKZadiaTB#yBc8?)iGUjuiG-Mz_0vyQw#pAm`B3VC7 z5Rd#Hn6Yp>LRQ3I{fr` zW)>xf`JJG-f_njaa*(dAcH7WTCthLHxWAUWb1m) z)FnX0)UHeAXw&WLmdDZ+(~t@deUAF;zn!4ws7aA8^7NjSVh+8*=%HTFrCLzr(nm8( zRay&csX$1T$J(HaSbi7CUgbP>@l=~J4o_YN`iS!4NvnKJ(v$F7|F8=O$OS%yDiRt| z!x)s=hFrxBHP7Qy8IF~tPc5UMLF4NN{j9R}3~DCbij>bhz09R}dk_q59Dw}MWqgGsc%7cb%7va_)SQ8@VUaDyU|5$zJyrV!_QQ{p z$u0izoan~TDDq&3YUBlZE6Sm$v7bV6aI*8)05g@kx~V~ux8jBq5L(nY8eq5~raeY6 z)Z8KXj89jg#S<>KAer_u)oWK1xKH6*+S+jF!u#_~7_8{{_Hg$CTFtD2zFDDln!xNwvhDnchJ64pzl_a+w01W3=5!$bq-HUVGyP4J zhOUQ0oLJ^KTIkced7A`@a=`5hJPNl7Q|B)qti3RIX9uR<78+$_Bt^K9P;~45KklC_ z+nW3^6tu=(D<>6#uEKpRBpb)SN&;eGUw9Q}@(2nk&Eb2o@0$IlW~xx|^0j%G4GM(Q zOt7o>o~4Q7Z8-t9>eGPvi?Vd%S+3v6vhaA{=-7;hguO~{!OC4|-@f6=xUMxJ?B^~q z53$LE9;i0zwgAUD9f-ME3k>RWtk{jwTCc7T94FkaxIej4W?|>cFP{uo zF0_?t0TXK=+Tr4@WYYzH3imB<;*nLqEwEFf9P< zPdutl;nZc0Y>00BmXmpm#gCBLhk6)tlN!Q4M_4`{z-g?zE0JHH4pGcV~IieB5x99au*f&_V)XyLN1vp6!O`xcJ$Tq+LaK_|O2VE=-blgOog? z{9SWNIZ!pesKJI_+jPj>a^O<_b-6m`evrJ-U3kS?NMkKwW!|y*CBLy1->*zq4V7T% zLN9|1!Z(_H*z1t_te9JAB1(bTl~zBX8%ug#d-5ge1> z;ed598K`Hyk$cH?;yNs;em@E_!Aob;1WVAI(_Ep*+6ktasSiO#8lnjPY$))r@FH6~ zOLKgW@$1j%*}%(1&&|-Zjm0|<-7c&rW@9daY9J7C>n(pQ7zG7V5-ix~0t}Qr{mUa9^am8JanBAt~-PEBeB0$rvdhLvK*LWmpax$P~Ql8jUz_fc`^+8ORL?w z+>-`Xold7hqNZ3QpFJko5BLT+5D~JFHL3xbCfkF=(zxU3s|U381&U5^i!In@2c;k| zBZggg37~1TPwg*#FDGPf1Vnakq?&JyXRj2&+FkW>2qjlrym|L>H#&yYj210y^`5Yo za`?p2flJgj7hGQdBXp1MN;gkcnv5bh7t^ZNe!OXTCm(>Y{L*Nzd|!GWS*!lgs|~c@ zkZ0*hJt5JFB+CtK_?VnBeli#qJVCpmuy;hXy03SzRoy*5MO>3)ZVu0Ffp_=_U8t-+ zxmdR(JizN^1&Z{xLGYThvRenGM%TvwhRdk53THy-gz&6EywAp79@|TC{NqIM;J7%l zSQy;8mX6#1L28RKxz%$9RpbHH*1H7YD>$&Rh*m=34d&Q7$PT`hvbe3FO)g3tze(5o zxEF?OWHlf!mrt%(^~ro?*ETT6zxx7c+?DYuKlL@_3zL*>^$~FVt&mdCzXH|c0;6b6 z)dsVHI=w7NY)R`04K{aa4Z5ybJ8X#u>g^S6g%tl6mh2g5oSeUoO-3T=G9O*qGeb6vIWc z%l(}n-&F(L?QCPxi63|-lYMycCb1r)<1}5C+B*;VE#*URWs9~okRMN=bb3_D1sTSU zJsb4Bxir@|Lpg2@G4ZRFOwga3csO+25%-hs(Lrq+v~duoYRtEi%L}# z(Zzwc?nd1GQ$$jJQ7Tf+)e}-a(KsMTyTEziBAD@5`QgMD+VR9+$3XkjwCYx)ekFpY z@gxAV!WA_KHNi8&=%5sZPLCkDz_@QVSuT9!B`kIhfY?jC7>x}I_)rF>Q56^sU*|PL zK+rclS9;iOk&R9h^Ajyg>i>Nm!Y*767k_*MKSgbTZ4?bWOlU+IAqF8ek-bIERf zFiFaWl-;C)lZy{dPuT!)AA~NIf3-Y=n7{)}Y+wfklvLSaSJ0p4xX7VpM+3^YWjlX? zh&IWWHI%qdqbfF=HWx5Wt*i!L(q9I&}1s~UE5l1S0t)~A# zyzjVz=~UN;()5O=Lvxwi8bcv8$cMVsYDg)A&uulHAGNvQ7{7(%UIo_iw^kHVX9}|n->lhw zOU;0zjx+ivo^n#Mf>3os|I_RhyP1F)7cdg;A0vo;Ev4xyKGy6W6k`ClZEk9UeqU11eu5Pavt(?0e@3e_BFMc;9d*1_b4Q`ghj zv_jzRB{H$pTqwK}8UGYm5M9VyfET%NSOib)^N&woD??BtSXnj3NpkDtPo;0JCL!g2 zO?kX#Q~>2`GKcki1V=o*nKtP8gU|Z#BVAs|k`;-nR8c~BhUM)^n$@_;_iq|#4zn>I z2)hm1lH#9tTvlC0=vQxwMII~IYg*_K*|qS#PYhg%W=)2|I)^@$XF=&IV^X%uD&WkZ zYB3M2dT3{{GCCJ;__x?doKlV`-a;`s9UCot&MMmi^j#td7sK&mE|ZcIk>2WH1`rLx zoJI1GM-NQ;x9HoXKCZic?B>J^&+RZ4AGhIFa5qB|C-aqvYNr6}98NzgNq)$}X94%w zZUjZeaSDm4z``sT_t%)aV&?1$Yz|cjR4gAxcSA&-cu_A!Ujxicq_f&fo$B4o-qBN}jjFb@&`JRTBq2~*0tQeU zaLW77yte0dDO^8g_O5B0qfrae1EiTO*0Uh2wNxCZVe|6cgBeE4G3{q-j2QI@UYoxJ zwLC7E%~>Vx;pR+?7=H&~D${syT$p*lME?c2oGVJ0y^^bWphzPcfW@h5TLOfuTjo+c zNpyTY=M~+rhNvpS`LtELQNn%T)BPIu2cd>T>V*~Iu_wJ zGCqo6LZ*qV23E^V9k&LEi)gNzwMB@7ZfrIyUIy2wkwlTJ#C{7%yJ)c}SW z)xP*NN1#Q3%hZxAeugUXuiU4y$Vn$IXIZi?$i`AxYJ3*#FH5Z}n9118j@EK; zk3j`t(HHPtEjt_6s-MF9E4}~OI`pxBJ&_^B&A;aJeXH2!SM3bOUXm(zS)6j7j*0}% zAHbn^W5%c#-Krn7Xgy>Y6FFi(mWEtYe@Or>6XJ(5H7jcglQozOFs%nA13SxDo9d;3Y>negj$73}e0 z6Y=V8A5~!FMv7y#)A}RvILli8H*GemEZhjlu!7hBSiEqDf%;9$=b@aWO!Wt;&(Ch~ z-mN}KKcub$6Zn$(#z@}W2DdFDuAKKv9B`H^5k$yX765tw=ndP!pT1?X@9ZuYBb$oa#2+E3E$@M)#Fnt`}^X3_szRhWGP~g}A?Ry8dv`VaJ73 z{P&FHsm+~+3}Z6L=Sd8K6QV5VABqsir{a8rh6ePa|3G|aWs{4?_JZ#RC#v-$-LW9D zTt`GAUqg73Nz_l5!h5@(fKR6JDN?;2ZT5gka&IKoXUXMXfh$T(oy>9uyZX|;5)M?g zpcz3u#hoqwz&1VOZyY7R9qzO1oSkAEAPVU5*MU_$m<+R2p=gScqIr&2aGjCip^k>6 zdYxt5iaMcANCHwR-y#r+V&E)7J(pzz2;<3V8dAf* zgm`eXe)3bbMqiz~lCeiz9Q}UTW=!A{of#VVR6~kFr2z1 zH3@@m)VcsJ4Cms~@g%@jwcDycTeGm3QEXs`|_w&yT$0`?4ZCr&Mzh^6s zS|1algdMr~au`sR?dVZmi`>A*x=5ETqSGIk`2%<{6F#S`HC(N8>Bz%UQE};De%Ak+ ztO|6Ywr`fzh_3uSBzxH5V~{u?H?6GGs;oJkv@LBnwADV}SvoHJ>wT=_FAk5sq1Wx- z7A|MZ#t&{YksQ3*eMV3(ZuHsZa=r`$WO9<)6i|H{OPjfoJkJdZgQm^oZ;R&*Lx<%g zOqQc-6HJ}WQ%5z#@RW@r{qG}deqi(5R#h|2S8FY)WSBCoAzQ=Zli4MNraI!=m^gO7 zvG1zg#u&N|SY8^E!sohk8R|owbw;(q!o;CZ3ww^=xSez_PUW1m!}?!I6|KGf_P5B} z5x-dkn{nhbU`CBEL!^;9{yNu6qD%S5LvzBhYf)0u&CU~d4N4tk?lCDjN6zvP6DuUr zb3?H%EwvP(Wm?~!_cjiI!{qnG(EerviYXad=T*;Jg=&cbv-DHCwG2ZhLfrIUWb z8Bcnhm+JxtwcEr=JI%1{R-CYW7pS^@UACkUiI6ef{wjGc-rB{!oNVwL!HIvSx&AAYRl=sc2(q*G;+`cgn_lA4gs0CJ>T|uKw&v^1{Fj0% zF>{S+*QQzPR&e5+jEQ)0-WCb4&Kr+;=j8E*)kFQA!T{A8{M=YtZ{65m5WWEOy~&4; zPbrNcL_?i7cSw^!@~9avh6b2?ZnrnRVMYWBgJV%ER4Qgn{&NFEgkt{c^G#V90|;xX z3@Z9;O32UL6R;X*FOOP6sHKoeqVF*>R$2adqbqtIhEw@Je%<4XeRJG$nYx7V(GJWQ zZ=DfpI>~9o43+$^+QbRf#c?Qn8T-QKCb2h}#M1ljqQKB4=hMu+knOy|{a!&#h%dqI z%5To$&I++{tS-h`6IFM9fh3{QYVamSPr$T_`>{VL^?RC)35(#IQ47_>)%Em-2;?P! zmX}bO{(IhXM^Su%c$wkxIVzF~>gsBS39;t=%$ZrO&_O>p<*@iftNJGsvo;Kx3arI{ zuiN|Dswi*uKlN%5=|D?`#~l}+{EIq!InXh4rqk))E&k{40ocrmMvU-#8fQ{Kerhwk z7MtlSI0=O@m#U5a+qfYKjyUlrGvnox#%QC!5bFn)d_i`i8CXvE))gOvMkbaJtJ%GZ zIM}1krVep7*E@}1Wkbeb>A@T;IUlVNcJ^U+sHjxMGiIY&EbTf>{I~2rv!D_`zyMps z8_t`hmVheGe-6T-LI>6XEbQOaL> zveXF@s13>dF>h%2hYq+U+}r1-_bstTN8&eZEfOau6xsS#=tm&P%SLp9Fxh;HR0oY9 zo7;}ywz9>)ML>SJTS4aV=Z`bICvW>!Hy-Y(-B_uUYU|#f2GlRIPxQYYm{it?58(Z9 zwx5ezwUD_*>D@8eR*m+ig&)--Gk1;Esw1d`-k*D7@W8AES;r6>`>TVJEW{M4qe)tZ zg+C2#r}(<8R>ZJEfML$V5U|)aY5$aeTJ5(iKZE5%B!ajf1|#rX4aXdDlKeu{$p8Q= z`?e04VsB#q|Zg|Z@rwuStUs>}Q%D=WtysNb}4ATxPal-Ke}6wvK~%N5(xF%%;a zbkiN*_C^wv)=AAVaMSEB=UlW^`RAh{FdBeh2+-eQrfu{5mol+$N7~Kqd^itsUYs14 zfX{e&#VmIcywlN9!gfxTlg&@YQKoiriwXbV{I8PQl4mYsO(jCvSTMT#5YdE8D?&|| zNa(iIgvL}^FLrG)W^*Gc1><9Ay)DB^v?y)kDOl=moh)sIfLYz}^^hG3u$Cr$cZ=Bu|kPbDap#6-2dp0(ZU=9l*#CigmVS*Og}w0_$el9rtstGSO31^AcN z{YNq{iBN%Q8&)==?RWsfW!K1efNT%8F_Kl4px!D6#YtJV%>s{kLcS0XZSldh^z+_)Z|onS{o?$CKUPxU5c9A>I~sqrU=n&X zI$HD=h_M%I_kZ{df_pG>>{=GP(wa;*Pr^j+vHOZbF4JRe8Md$y)t`vB_R6=}v1S16 zV~HR!eLtR}8le*8C9wL{8kBYR8LL~gy=U9J4kQA*&LE^{NO3O{fUn12aOI&b$6MRB zv;2gR5~98=WASflqNCPbCy$sHu@}_%+95`Zfp+||V!Aj=UEY{PMwk~gtt4_tb9a6; z@~Gl!_0Pjqvd?4Q;sE=ef%9G9GQ>Dnb%QICC&(XX;|Ac7xC;V>EHe#=#^Oz;zxPs! zbx`fd=^^a0!bPU?wc7vZZqgm4>>_=b-(4@RwXmY;Qp#b>$Nun=`T#NkQpyjODw4ou zUdgIIEz)aIw!{X-p|qgyakjoo3L-t=wg-$TXLuF(lwP|=Ar?!<@TBUsp-h5?Xd?tZ zh_qyBQ(+`k5SV>R+Y}ll6%ADAT6Av;S-`AkYLmH}Fcr#YOO}UGGLIVBbfE|3*<1KJ zPOf=hI3k1F;8m?Rp?U6r z9T>i{%V-notXmEACUsr@2x8Y@MAkbajD8rqkoIO@n}qpZ@|5OH;faHJ&!B#%&efagW{}XF=~aX~%C<m@5yxJLI3d3ib0{U;U# zInh71ksxso`YjZzG&Cf-T5oahaymxLN-J#cAk_$60w_t+e_EHBUQ-<7XN<(KcbyWg zsZGhzU7-74sICY^wZ(^Eyf(k()N&?M%fy&XGj*4AGkVc7Z3UiP>kZlXR%S`3UjKt| zTgwkJECx3?T3k=!D+Yr`sJ9~zA^#E%1eK38h(|~9&Ao?e=UqIvKtWIbd=h+^R;zgGsK!2U zLR~F|y6!}ekv#EPJNaRJ*r z?Ihv(X6gLQ&4t@z`Id@^5zo5I)kYX*o70@radbli%%B|4 z+xwphH33Q;MKkVoASl?%W%sHCpUvn38MB|8z*?-AFI%Kbq_x*X;ekh6#V*78JKwf` z=6l|6UTOw1>V=Fk=BDr6AmvYe9~AJE*QL7VQlT2b-_l$r5#~>(ZCYf5fu#!mLWcPA%XIxhb3mx9H8KQQ(8s2lvda2(o^)# zOEn@q06QHuIyB#Ilrf%i)VS)il*-^@{U68*^ubhtx&XnCxTQxum?rT^9DlxyIr9G* zDY)Zn3Fr9kG-MZZ+(ktm(RacH3c*-I(ob>8U;gQ0g!kxd|QN#vEjmte)2 z4y}+@Pt!Thcc7=V7nD(Qw0LxmW6(qTRE@OSOIzS1?t%hG7V=l*iz-Ar5%C~)V*K(e zZd)O}0CImlxe);bf&+ny6|?q;g~i~_2+xdR6#C;6D)d=_8=5E*c-(3I8VSHO%!VOP zQrhi3RFfvo+8;!h#jc7q1hBIDEj^~a{ON@xA*OI7vtCkN=4krGOe7s@gt(JAG2hHR zQ`GH->5%C^a`nkZJP@q)?}-xNV*H+|&8b)Hlcrkuagb15%SxJ3&;$w}dS+ecmv#vIqkV zL6t6%H@{SZl@NgTWK*!>V})_|gWrsKN&v@3aL35!>y@iNoa9$E(m6!Ln*I){K4Sln zWV#Ytalo0HVeG{BX}(wSvf0gOisD=mME{AcDu9uOFH*}R6v7>&;ye4k~xv#iL zcU$TxS;O}6e^aUmXgd(kZ6^5T;r_@QyXLlnUe*udKYpg`epitUxo`6wMI@cJ3ywcn zF&AWdw8K8rJtc<&WnC4jY`ouv#kR~1%cw^nN19x$7m+Is6NnjB@T7_tI8JDTKcMXO z!FY?iA|g_GJDb^glA#h?;PF>3_^m3iIifE?{en$Woa_vXpu{u1WpY!G7FksKN-gE$ z4(y>7IJHM~W)pB1apiYLdO%8j?_SX=<|E)uiI`1;AHq)7Acrc4BVgPsfk|1*iiAn& z6LX>Q{dwKKVd)#PtbCc;qwt>6RLx3>ZVD@b@Druf#`SiXq?-KBs&O*z6z)m;#u&&= zWU5gxblcvx(N_GD4B?yvl&(|E;ZqEUX@k;Xspjj5H2yWX1VJwAP$EDUfPSmxueDl< zEi>y2*eqZI!un8Gc85zAAr`CqHCG3R!6u*wdMn9_buLF~&rx5+WNv^Qt0k(joPwW_ zdNL^;x3wp6?-m<(u*X>qvig22kp8Ev@Ovo3Ab;W}UaiNDvYQvEhB{?A-8%}x@%;SX zxLM%{9h`#52a|+Xg_&@HvSqIxpwQzxxMIaMl6~utUk75j)U-h9qmR>_q8Sx#`O^Fok7_|L{jz>3pCC6try2>kd0Cy^CMwEzFj&p) zT`x~Vd!MaLXJ114e}13ju_Z4|n0IFF9pl;#RNncMn)x{}fm<9v zWc!v>e}TcftCj*7@5gUau|dPN*@S%C4k`B>_fCpZTvW!4Q%(v)889$uRvR|q<|(PU zyx0m6zZf%zCwGmL;pgFIkOd)O4MymfzG=^Qo@0#%$B^@{?!6Q!C~y-J2*0c(Q_9b$ zVwe~XD)ZNHnqczlbVK8kDUE#P!yOw~$zA|`lfD6k9-}$%v4dg)%Zc5JFc!3t+^T#N z^dG>w<;v+qwWU%DjbP@GjP48!7dz-<7)Bc1=H9b~G&Lmiyn>JOhA&mwTnRy+LJStu zm|<-t&HS>+HQGevzMY5jT<4ck8{441^f@zq+NdqS=W$04`oiI{ZB1}}cLC`723YO5 zv~75_c49vB!dAvASq9~Ujmw^a9nKr%Ki0yT2R22U-?%6WNq<=(iFv*rnd{PG{8?Wv z@eEQjvVQiVuYnA`A7Ha|d?WPN5$tUXYOh6R$CiO!^(93=)b}C`G?V$} z{5j5d*Vj<)no-~a@DTN`2Is9x24JZ8-cEIegKr9)oj+zvPZ#Z?MHU@B_YXzT_B3(P zZCt0^TzarrIG}m6W;-t(djPZ;t34^ljVyRGG6}XcM$8ZQ_S^FWcW1MpLx=qK@xFj4kM_RYRqo%QM9;41U$| zEnyDHZHMHDSQV2i)}$7i5fo^MsF9K5fM^gTS5`5;q@#2!=c*4-SeVmO zr0i=d!h{ghd|@>ajXV4m)kFAO(&aBVB(s-vfhmmI2piqb5thN5n94M zh59utKLdGK>v8@YUE!f>Xmi2-5>u6v1H*ECx3!CC$A3KH26xOXN~%NItCabNt@GfZ+p`x_`mSDCu`QSm7@WT+ zb<+C^tQ^J#DpnY(E0u$y##)ckx#S!B)ug#Sw138 zgp}&*7oD3`7J-mp`ss~DQm9m66G)M6Bd(u?SAtX^sC3Fdb^}2=IPGXz<|EU?=5Pd; zca&X$xY89^n;9(;k55BvdW1`gkn{uZmg!$xdO2wn8 z%Jr%zxo7Z+kCv&lgT9%Qg#y8y!d|=hLl3N+R_fbOV3G-M!&|zYd%H9E^wpGI2)*S} zQv8Lx{!=s9k0zW(=*wqkG7~lH9~K0|7`;EDY-|Pc0oubsNZ?K1H+;x->hJokHLUoX zP3@NIgdrIfoR?F)CMRx=ik4=`=9SqXYdS(3`hR{=qBTioIY1FmMkO;IcyCn!uAz`$ zkm0}L!EcvvZcvXtC?hg0b?-e|@j!D95X+o17op}Zde@mPP{Q^^IT*dM!1MDQ4lKby zSPbTB48swawOD~ij{ixL|33|In1b9$tV5)tm2>qan;Pv!LN`lfvoOg0WQoZqCH4$a zJ}W;&Yek1*|9U4Vt-69N?q4Ini z{OJcD$ek&}+}9eoP!kW_j9JZg=kA77pN)OTSo{owH0OFBYX<4_UYkx}jj086o7#PE zr{P=2b%H58@!GrQV(LCaVt~FE^eilOqEek1F>-Y8+N4lZ^Yte)+tRPIz<4jK*L`Iy zgp1h=wD$A(9+hpu3|OE)MJB?<_9q${?=9o2c(KFs2rWFo`!(+3 zCtxRkj-a8P+U8o!F?4GE56QoA+`2-319S((2CmPHM}1X5f{(t=`Yh56=4Tt+MZ7}n z7WuG>u=WZI4u4EqQjqk-aQtGF#-63Z%RB|S~%Jh|-sbCq0hxC)dZ@zon{^t8 zzJ5bSwzJMmn-=>R=ahW!F&J@-(ER!sK%s--a2}xsrXS&zKw+O`*Pz|2Eo%1Trfu1>xsj&t zNe)O32ECN)xAafs=9#l*Vgbiw8!#q><}HDEZU0_$@aFC-TydeVG#A`vx!O+2h`*!m z@p)Ncf<&i9V;!qgMnYFA8X5++DGx%=9m^-*{JRJXE!uP=O>cgQ+5+5q^H+j3b$0fa z)T0#iLZT#-fs!%ehu}thLgvjq!A~$JVM)P6oo2|wCK|}*n{*$oCj@>QFMcrA;XkI! zd^q=&Ugu=iTWJ36SCSrKv5?I@*Bl!*ci!enAdm(iEyqw>fVHx`)Qw}l}mQn#7YgmePaO6Z+LC+2_IUMV<_lA3k2bPTq znp==Z<<(tJ*)l!61rY&k55b;pzs^nfSPC{B^?}o(bbTZV;HYxmLUUd6^#7V;#>)a1 z<>!h!gTh}@DS@-lo{p{rHDdLq>4Z|q3sdO#>J0)0f)-Fkr>tJMA}^(GW`Jn{4$M=j ze%+!TqZoN(2bNh~VCgoK><3wzw)5dLOhp4exU+G`=$-I-kbwJ5vNvzRH6LEKE@(C% zFy!Pe0qy(UU-g#CUu7MNPKI5xQT`mry^`ggYQJp|)H*)^f&ZiA@_1#jUoh*%O%Kbm zmK#EDC3#0PrauNK#H4XBwEv`5^VS0ftj@@)%6)!)*juMos)d3lC((xND^tC6rK2#X zfXX9ApsKVlLNG!zJqUFGH9*S0d+WTR!6iViJ)7S7bDux{zkf@rbSW1S6zCQRQ9aPh@or!OFm*Ea3>Ju2Ns!Ov?&*8u-Bc=yF*jyxmAP zQ}TV5oi+}lL%SYycJSI5YYrnB=xATtE;;26O`I{MHruRpEPz!tP@kv`+|*&<+}O=0 zr7pENe~5L8w>l%Xa1KKZL`3rGNhsdVTSC!TCt}gzx?g(6)kKzxbO|AoSzD*`4CeeP z;=x=wAbXOc&wwkPE1|meqNnl_!xhD<_MpnJz~xf!HO)M7ieO<7hm%Cu3?#fX#H3&K z*I_T5Q`R-8vRUS{-#+hMW@J^{A0Fy&@rw9$4@OZrjNUgTmm#TMiS2B+;5t34(k?kB zE*rsLj8Z?g6UuQOFz>uoVrkJ;R05KL3xlwhQNKXgLOj($$rdnd=*}ikVtGziZKpl3 zztSjuinT!7azZ-P8;4rmNDZ$o9+FJl1Q8h(Fbl}tkQ9Ft?&STdJZ_Puqm^hTg%I`? zB<3~ALc8^8Ch5|AI?J&|j!&&|8)e%E82%twv|H(ur#JKj`40N23NYooU%r zqc3PcviV`h#L{4s)E$ca(V;|rg}(|*Kg|jqL6^*a!MLL^bd!hs(7LW4%A%|4P-!;@ zs9#SkZVRIax9e79ifzSfL5zxX-J7-`3uzC<`KNrSX+yW1Ks0$@^Lbx*wvbugEY17R zEapF?a@`CaEI;b4 zeU#jHcU2L03jeU>IbZRJNbirymWE?lmmtWs>2b_5 zSU%Mk;k%+WNGWrcPO`CFP}La`|BI?9+Ni*=1#33Xeb$41Ngs?j_wB#nz6tJZWh_#0 z{5}-qr3L0?RK?iU8oGT-p_PYBdaDJmO$;8nNT6%}sT*=h4^UXoV*yes8Ni@TQmM{i zanfOt#}LEw%Zp{YMCjkKddp|Gx^lOwGIh&;^JJ4C7XdwiuYeM*-q9e8CTx&SF8^J$ zX$3S|L##>q95fp8*-%uO4{5ZNAy?yM&znhq#SEDXvYg=+@IunDE3gXfdgV4{NZ5NK z%Fxok=&J8J+q-Y4e6pY1g5EXP3P3`pDfPMe2ARZmhUUh2KH-DeDBvR)XFh(@OZ!|5 z37pp{LwsDE{U{AsB9?_}y#z#psi6)&5o7F_710EyM2*4*B?_WR#XZxpmi;RIo!i{Q z*UA_^xlBy4Wsyi+E(OIbzZ@#G7~lUGH2bi=D#4iD+E9H@P?(bcWtxtVO!7{jP#TZ| zG6oUZnKCSL!%q`;OXg^ly#win+##KoX->;FT+$}S`1bJ1a+#ZvvQFlgim^#~nAd}x z?IeVJWVx(8$F5TCMwaum?jryuavXNOxX|u z!`OGZK#;3fcBT@3pErmtF{wE{w20X9Hfx~|bN36pGKgVsQ;ytUBJnn?1zqX8szWuq z*!?xDKk~A_3ZZ0+xS5$AJMMR+Z_8@%|CE;*!F7p)hiiBsEV?*1x#7<_FL0^2a?~qA zXaF(@h2$GSwYf!`2LNuSHZws~_f7)FjTi3cMdGv*vOKuEK5$gLrbC9(ptuOZq>^xo zoveHdw`*$7-&3qD^oRDIkGsOD3>YBqx4ubXPeG26q=e%a4;^&X%6y+w;+@^~&DSFV za_dikvOYy9wP_%|-A0{9q0baime06^Q34`+`JmJqWrVpRdoh)$FQ}1QllO2ZRNJNl zaZAgt54*`8HtyPXZ7-33a}j|L>^0^^As!6$2SA)!^fM(e;Da{-`#l5OA{kMx+R~-v z{EA*^bRczKnT0G_PI~wO#Vy z-{`ZcyMM$WTlRqQn8`OKBrn;BT0(J@mONNXv!4;d5G>ml$&1BP8s96|cM95+0T#no z+0gz-gMp78<{5smbL+Q5vTY6Pj? z$k~Y>ascQLk6iJR>;z|z+`F%l$%f==@e3a94lt#vyy)$=}dwe$&#rT}+z znJU@TfK1^Xq9~;lqPPbFxM6%%WL^SY1}R3nu9|v}<;F`^HsHy0I7(hN$Q&XKrp$4F zD_nr0!LdhnH{AQ#0!%k#+9c)2#a&QGggd9Yu+6*%lF)@(51

!sbI3UGdR-o7_+D{Oe{)T$miY(qMz7vyXy;195Ud@rRME| z+%1&LZlY6MGsMH(g*nIBb(ZmdCSfWKI!^?|EB%X!Qw~1e(vYdt%MCL~na7tbBG(-JJA}5oc@m=6yMi$_fh7Xp5(7iB6ha6kSY- zznPXF>V3TocAluwWCs|l;h}$7t{6L2GwZK9LdT=WEJ%FqoRl*PXyfP|2+n1@B3{B- zx+>UZ+%*1@bI##xl~<%gpj*IWHm6lOyS9l~mMk<@(DnHkGF~SgY4uMoV`PKN5t;WY ze!F+kA7tT!R;&v)tn}V2Q0rg8ZUAyQABkUKW~~wKtu&9j;$?);YQnKOkNOHnkO$G= zST2hd#d<6M-@j5)z2bDzWz$B<$t2SEwgm)7+w5dDCjPTAP=17`mv!;R?%V_=2-g3% zcB8%XgENE7^8Jxz0||sC!Vx2bh(Fci#WF0%xfREO_`phY&39jJ- zAp}4kgcNjUa;tSncFvy|l}(DXvfY;bNB&69lZ1?)QLwl#=|3uWX`2J!*y%IsFYry| zi>lAJwR~P;-OP|1t_d@lL3Dw**Q3Uaj*_F^`6K(wav_rdyrwHtII05d%PX4rQQ_dvvQhTAWa$z_u-&lFX z@{VtZH8n~YAJ#Oxv7cvI`K?MJI>$W9Q#4Sm4zEU*EIpAUC$>&Bm{Ms*NFqJuvK6Y| zD^rVi%x4DNSDSP^2{B=?A`3g+{-2tbH6ZMOk|`zjSuwGp1;*)@`g-WEs7N9^7z*_| zAM|AD#kHO%O9Kkgu=>Wc=Qu?J0}*^jVOb0X#DdF+m`5=)t*A;{2>XF-c`Yc27=ArX zVx%_c(M@Rt$91?~!Lw#5@m+glhvPM2K3I$bpZe^)2Mh}ot;jde?(nPpgdKp(2f)X_ zOrX~+X|PcBP{sz$!Zh=@{$W|xcDnhh5U2LJf;PL<4ae9kE0B<2gC%wouht24sEHGM z-H&!>k-$e_awV~Ny#h{Topu_y}D9_~l zSDb;J=SXge>ZnU~;{5hlU9>Bo5ipz7eFchWoUix#b+d~Ht?-B>_&%?`HyleBgTvCh z^6oP2-vue-d$8E_%t`gw5z#Ab(Sex-q!LP_AuPb=C|fu5?6l7B_BsQf;PTtx=Z?tP zvu%Q@ixeld2Ir;wm#|Xr`#mj6~uBNwc z-TvM@G_w=+y*K4k`@4tSl^Uo2Wf6&~cIjR~%Gf0_J3jKcO9?u(rl|6A*;(&#=uJMI z$^wo5KpG@MTl^`9TrDqjyb+VS&;aGeJ;m87?UrMj_8v zY`4prptHB-o*Zolzf$Q?kUpmtJG!ve;r0u-LTf@0=2L8bvXG$;3GBNZdvRQaGssU=IY=kx0JdSaoXpYG; z-5|u6>1PSJ6D<=cN|JGRWZ1BxGNs+7B#3;oZB$*tEC#>KY<+SoOrtrpqx2OQ0tte1 z*AlHnp7zE9888>UVZ3NsBF9Vy`kRMS04zkA$z_;Uu4`R8!0oPoO^VzbaYy?*7SGw% zy4=hlL6t8F6w_}oc4k|LjzIaIEz0xwClp(lni_@-bw55|(nh6I?Xsi4{w3HSE}HvG zU1E?vK8zjgi^O{!Kuyy7%p>;1IbNxeNzb=YJOET8`Mb9eKMfAI!ed-U_l1d2B${!U z`JGRRSe&}`ZF?j*iI}3;9w|A>1l$PF{Do-EDaV+Bu~brs3DGuSfhOe3@b?qW{VQWeOT!H8gA^Wl zA*?oMPE$u_c@e;DI`GzmK~eO{9xRRuwCTC_#u33HAc8AsYsHNJhNNI2ogLM&={f1y zjnA|8Dm>5(0>zOoOwH4^!w)2b+Y*86WqqH^I6zPn%f}-bbZ@d!gmeDBQ>aD0NH} zA#u1T-93dEABF_9M?CoFS|KGRr7IU1gX&Mf)1WQM@hDu4h*3~yn}zxoiU_<2B*rNJ~wAjG|DS@;6Gwc#B!yp%qW`cog7bvf*YCUDP0A z;t4M5?iq!@vHKrDwn>WLvTPTQMCSBd!XFoiA)AV#N2hCHScu{1Q)3^lY5@TrOH{GyThv zQ?$y1RiW=LHcXzhS0Ky_tqf9!6<*usS=PYrU`q%9@CI47Uj2(@(xmtIjE%ONm+OF< z`T|wqayz?k(jhq2HZq5QfSZE?)vvaNC-z`cm3 zGE3;aF|7Ljve-!%im$K}r30+wUq1W5#{*K|BbQtqrG)Dqmg1dE9QTT*p;B!K}Cl0Ic~uhxw* zg6!Mn`K4@biIT309qlM6VY9v8%yBC4S$ASu87A|SQ=Ow=BURCLhWb(fKYCRJ`X!F1 zBvC&nU8ry69~CaZ>0lt$Tcj`3ngYNIt1AR_ISpwBLz$x&P60?BRoi0^f`_fD6WX-b z5=jzDli&R4t`TB%gn!Cb6cJH>33OjJN@M{_v*ik!$V;84=#23zSfoESI!7+{v-G!)dYC zigi(x>#e#iD6V>F5sUizm^#Q)+w>V7&Vfap=;i@YM?cBQo1s7K`e>*eB??y|RiP;< zip=t7(n$s_Jd>D!#+Nt=q2?jbhBlsL98II?eKcl8&TMZ*-e>&Br`nehk~;dChBMVh z#IY!gFMhK4$bS?$pGclQp!OkAE>$1z@uIcW*3HLLRDo}E8nfdXD@&y;gd6lm`n{~% zO-d%XvtTP109)x=T$GGnm0)K;NiK%{iHS3Xl~w#eRICoxXm+F!!>vjBcW7A;?SWgo z7d26qbB>WwsgR%p&payt`k_`r$mrIRSq7XTK|X}eG0A#m36~-z@UjyPjXl=gACp_! zc;oRO=4`k(*oiaPUM1x-+L>YMjX#IGiptCNCd(eIs2dt&teSRZW4lkr?u7nAx`vm& zABbH0(8!d)3!eWt`KKU=y2>sj15(su{EzqHt9X-Y6K#jy${~2HZE=(ql;?)`&y>MF zcBv21pw+da3)Bjyg=%X}mX z(Q0Z1cSsaRIX~z~=!Cu>!dB0!mv|@RY&9@=v(jUtf&|RCW}A2BGv*N@_R; z|C%fA==Uv(S|zP7`oW1pY)+k{mz{5q%6!>9v2lqq4;rd_BmY6)D2~XC&>JkM2H>99 zQd~3@+iI?xHby_*i@4~DuN8*OZayW}#EPnBVx6|xy_P?bE+|P%{;y;Qd~iR2D3HPr zM6j`ZtnFkG5#xtOMitsElC%u>Ge8t6UY6*Rh1Fz+}TFYdf7thg#N*&)0r8NT}?EB!PNJz6BD1Qdo-_u zc_vkrv)v18ck)*I$O}YA0TT{&n6=m1dX`|!!xFlCv)^P*5e%nvW{HfC3&yPRGA%1g zswsi*)NFM7Y!y`LN?>ke)iQv95W2$M>&7@ZGkDIlC&Bi#q z(Y%Ai_q8D_+5!I76w(OMhtEIW6b$W-5~kU+Nf-VtvD97{fDaoBqPAhb&-i$(xR2Je_V!tYXbMh4^*%OA4Ol|S4~jiILP%s4Jnyif;wwapX@Lv* zA9UB9V5UU>V)T235inZq?cc9_G zMPfEpZzou9svuVi%!y(x_|*5uma_b0S5QydHm!wLhB)OxFrn>*#9PJjk+61yCjy{-4qJ67$43Uy zaBP&B#OdC!6B%0C0V={6FBY~Poai35d=PJddpPer8#-{j%f-=1B16~5Nc!V_j}M%* z!9l*uH&&#Ps|ryH3*Kws)zpdkoL-fEwR0Xx4%Vb%OA7R=dfj%F8r9Yg;|<)aiyP#G zVPvHV8;28GI@}|MiPOk)P{&G%rk}UaXAQ(7jwijSfyr;)U;b3WwZu1h8bYU_i6A#1cf;8MMG!|?>;cOD1LU;_cmj84Cz0o zyo?QTMfk9YD0aaBQ9SxyeOX|MCh^3pj_3wWq9CvTQCM0oWqS`*EzR`HLE->%)Mi5_ zy0;N#{nnTL6m*G6BWR3bob&Wf`MXtTiFPXo9<^Xc(kHfaCzO#vHlME6R<{+krzjWJ zE$X+b&x-Pz!E7`3AuAV#wH5)!0OU#f>F^!7RKDfF_}cY{!*bFaQOb7qbZTO0PnmBY zT|bA6Wnp?}H4~p3P&5s*XsKMNm&aPO4!ot)I}AL{KSf0A>(un+XL%&n`Pq|$pJ#fE z07*4$FKNy2==OqJ!n4>Cs+n(;X!h>rcMjv*{5Mu8mKRDg6BYgLmer(I-AFDqD-G=I zhPrD&f>)a?q$!%%?ex#kUMb-942svsSpS+S&Bh>l)NjCabMd9^-IGsRy!s+_zpfjp z{f8v<>1N%?Cp!?%bPx1vmSt~=f&(3>V0B`!Cf{p;^Q1FB;>#!OJKMV-6M{bn-asRv z7OXf$809aVR@F8OH5}akT%Wd2;5cyIgU!<(D_}G6`OZ$U(N42~*P?n6RbG2+zO}4( z0d`;CSDkApUhzCYc+Ez_W~*;=5UEPhl+Zu$uDnFSssh?U%$7!VE^Ht5|D~Ft;y#57 zE9O6#M+`DsUwn3pY^azhXRFF`OT>r8B}F?g#(g;bwvd2m=n4dmC~?W3PW_tn(N*<6 zX{E~%Vn3YYex)e4_9N@TOLj6~AputTe%$_YISA5tqCql3X9tNDbwLl-`M*cZ`I@T_ z)-?<5H#e>L#adrpnX>+08biUOa3R?VuIiW=NcUNR!?coZPt8jbitpyy*HWtltCiEcC5o)n&g4D5@_PnEzU%cYj|Y4;d$EF3gVnso#P+a*<|{a5mc$Pie4_ zld?*?Q?BFpUD9)hHUqn_1t?QR0|3K(2{RJJsqm1BOKG(($D#(Mg&`_!F#w5JAs9*m z0S?^o#$MF;;M>TAl|_3m0VAf#DF&C=ngP%K)UQ;9xkuz|kCu>C1DgB=*SV@jpC)|0 zBLC-QSWSD}=my-Moo?~k&TzC<=~(0(cu`?9|GRcb;q%JLpmmHEhLwDDWWf9BGC%y= z^Zy!t*pHZ&H_yR346`eq5tD&drw`McCcUztAoe`BSu1F;rwy4|R}tn*S{UB87^ ztNxa&XZRS4^-}S78koqTRUv(th1Fa-W}rhO#p0YKM^=Cc>+BfN!#Imzk!wj_ zssH74Q?Zfi*NkEmP*Y)18M>n_h*=E2xjKjo;Mseo+-rMAvri&%qz_=lc)Tc%Ff~W# z9uycqMQ!qXV}pB}TJJ*7Z+f)y5H30B(SBYH5MD&W^rN90`8~6aLj(ATpobd=98|gq zPQd%HJrI1HQ?z8j9h?cRl5U!l(=e>j+wAue!(i}lZSRV(ZaZk%$YEKFc>rho!JQER zzt2at01I{4#J}#QW`@Im5IyEX%HJyw*L^zfn_t0voRRwMAg6Q`8T7I*26=L&F1q6~SgE4-F)(QjEqll#g5}I`he@+-aBC zf-Q_AN>=9LcM%zTeq-J(l;GXMsw|>*N^k}~^(GeJ2>@)Vv@-^5W~U4I`$1edr6*Q)@}u|g{jIU_vZ3G-qbxq%+$cAz z<4)W;tIonc&&wn_gS^CZ;tp<*JO3Ci8kS)kG@p z{1i(8{QoUw*fxoX#gIUtB&jcPu5d_i3z@e<#7F6To~g_3A}C^KhDFsk7SpB}j zKbHtCNc9VM7LNATTn#1Wxj-tbPlj@plA+p;!Fsq)-)>N-b+*T;1+r5q2D0GjH=sUt zlNvr_1xb;!?<#xpbv6l2 zO*{$s9?sHYYtg;v#S&TOygTfPj;GVBm&s1b$JG-Y7=no-c5ebUE*qlIq-KS$!=e6@ zWG)5Aa@f>k*!A?n5x6xi1~=5|qDj9<*R0eH)FcD_Roq7 zD$z8{6|8|YJeEt^Eszd91NFONo0%ff!N)qY1v*VEG|5JcVm@um-^Al=yiLk#Dk@rL zvck&OA5R?h6T&Mg$GdJ%_>nXPx&s*>wE=ADNBRM|1ZqpiZzlnDEpU!w=tS-Ae}OHJ zbs@&Jh;uc@tKNi&lEzrD;AEw6 z^804lK;gUwBzSKPJ^9_dKI?15st%Jlx)sz>X!1!f`LL>?iHHw_;(k0ivY^91fvmw1 z{&`YuKYN+*Ag%i)rec+-gp}CO!|L|@%i2oA-yzU)@?d9gJ7Wd!*-S>gIa^6X3=rBr zjotTxv|c609@IxVWL~0~9{78OYCz>VVa{wkOm`#MxMM-Vc~#7nFGdyY!iYY95x)d@ zXv}(wh~leekyJb2?P<)f2AU#}{v*M;?b;7h&6b~ZMUkOh?a7lQ5LOIwK)8*W=|MS+U# z2aZ9(j2e*V*G}SEfS+5!7?B*|2v&L>9!@5qx!@-Ui(LCL?~H@!YuWMt7Z}9G?^)H0 zy2%pgyFrSdr#jKv_}>&&A)gl&{N%lMY8op=i64vQ_-#X~^93BRdQ0h{<0@GO!k>P& zGxEr5NP+1V3iApY_c%q#Q+5af0u`67gDi!0DDWl__TjK(k09FWJn(T-;5!HrM45WL z=@CP)V&%05j!q?8Z^e(aeRUq}WmAWt^Dje$#$I^p9Yx+0J-KD38cZ}U{4P7(e1?@K z7G223*F>5+iCk&FTV}&kw??U)e6)~*Z$g6UO3wU@3F8a$KJn zLm;Shlt7EC{vV`|-eV_(+keS!<^P1NLimDNJ|_7@X%|ibcnw~*0kf`2Up&rJBpQi; zGit_clpe2Od_B_rGn&)7K@T{b9JR$K(Cq2Bj7SH4`6aWb55#WYg1-8U%nKGLi{ZT% z8%*GeAvNWehr0^XrcG!M?=#LO0)gA1ZzKD^QhjI|2^W*H0Xk{5V;$@^Z7drHi+u}h zL1q+CziV8LMwB&Ktx;SeT3B2l;%|KmsC}^1CY1cRp2JWvFNda#?tB!#2vi4F{g}jd zc*GQeAN*o|>5!6at?f2Nek$W1v9Vv=8^`H=)-UG_VYyP#h+>}p{(yAQyg&J8ggA># zZd27cnP|&BAq&Q~dBa(qyroSH;xBloTmJveu0EYQN8`)7gsb6&F@2O;HFqP+w(a>L zY%CcVr~(M0xW4P=FSavfv# zpL>0pPb5urejymn9>^5B3Vn^HCro|0mB8rm9FDtcH2RpSat-d|xNvibEfb&e{d7)? z#fe5H%BDIUAzGpt1Y~<(kfq6^%Y5DzY>V2J9EB9So|8FQ&#hfzV5x8k~ix&+! zv7V6ds%Ar^;z$@Bj{1x5e3Nm#5ADB5G-z+*{NMGVpe%7JMt6U7^nP4n6bt2SwlLr# z&hfhxkS`qoSL+*9gkc@lhJ5Rmv7BlUZ|g{)SS;Fj?|ep?|1?*&h^mZ~hcB;G>@qVD z@`vAM7?Nd&tGbQTJ|vwabG~}N!AinoC$G0_9sw`P6+=zd#2K^mE?cHrg)><4KQUocd)?N z3k&npF;!B{o=Jz2Puwjl*&-5w8ExG-ASIH{WHI%LTLV|hvfpEbyc`hU#&(P?g5Sv( zfjG;mQxxsPOx>ZpOh@x|%t!)SZk_$%B0{$;t{+Q#(N@&c#3|YnpUd&ItUQRZqH7eZU>|TNLZOoL;U57~-68-w_oOnuiu0!LY>WUEz_f=7N8HySBMMZubI-(`S9YKCLj*4Z;rMRh+9Da+OP6 zj$!Z{pEzcjOpx;q`51%g8Ij~fW1Fxs*%yR!YK?T&_uf<`_~%rs17W)a0Z9aEfjGI3 zNlIcy3PFwHq^MJKNOg}ExY$KB&N4D{Q3}-EGomBgjIoVfe3{s}HHKrzA}#>?(zTc} za=Ih};&w6%g$`>6EtnFAtlt;)i``gOi>LY3^pX^I$dVucGnwZu>N$gGH?F64JIwX^ ziV%OWVQ+LJ@5Lf)xXBi9KPd;szGP{us8@=F!TZp zR-t_a9H{rA#hB7tSh;d1BU(qt_)&CA*NF+)ZSh3$NCJ)>tevN*Kj3>GoogS|C!qC! zizf4Ax`r7*IY7t=p8zV9v_()cbP^$Nlb;BEqth%32=*DYO=mc>JXJ5NEBkhSl=1 zKJ8k;zsYY`Ka3z6btg{TO~BkJA0=B+5Lk{eYq#diGIFBC$27 zMtq3ba_>L_rB$h#s=fL$#*^aUxckHiN0N$BD+ zq(#&-0%mev*D9>9ED`16S8`%9z4c2fgH4`*OghDhDZ$Z7TS$aCF&O@6JJC^pY84OT zK9wLX-zQKG1X*=i#xRG=%3Dj6fK_SA$$g*_*-LdAi=2_Cs*tUaE2nlAMOPfq)z<&> zxVOunc`V}X_;D~oVACX8heTuSZOO@8!TvNm|9Gk+8h*u(D>(h`z5wY|63ySShV({{ zVJt-qAq;i+fkdNaV8*)tIkT-FpFh8e4d5!J-H+{FxYQ>hJ%C%mXAa;Cdq=UP@hK04 zY+%>KOb;Mv1I6u3KB4xrQ_uJSx7?2&pycrf!=^LYO8Ii{5s6_n)pv1m6^W*uTT| z3T*tyEV@Ry)&tB*Nazr0F#^8b3n4w~i)@@k8X>tUj-h^c>QX%))R9}!efYIIzDcwU zru|!VHm=M*_6XXJDOMP@Se5kM>G3kT5rmRXY&`#7WyG~9mUsfiGX-%|M9fN)MTaZO zN>NP;dsz){=M)v7Kn1lZlwfszxlO}?4unPmP43H9j-;jivx5hjfZH_GSC}EuwMS-Q8z&b8vrs9YCEU5mOxO4 z6fNsY8sC=E1QU#CY%1mdo`LvPUx@9PwPTg+d9D#maq2#Et|qo3{S!Myc)33(>J$47 z*+kpO=I5W6{6=!-rE-|U=s^UDLbDtG)}6R)&80Srss!nP(EJVAeOOD$SQI=MxHA^9 z3AF~QVb#h@p-F*hSZ0#?Tjd+^su#$k)XWQMz2c*ZAew8OQXK{@*uuJ606p)Op52um z5-*qXvKmNArfqQfw(T+M*Kxu;bupTW3x6~uKVuvwpjsG`RPvIm@5e_}mr#S5Q_W3e z0h4u;{SNgIcFinOe|%R`SwDf4!6~$y33o?8o*7}w@f6Z}I3QU511WKw? zS%la%_eH07Yhr<@H*W)VLP^Xps})b~OlA&>DMXlX?zb0>`SlP$(1Dh)c0V5IC0;(=sTST_$O*fij0Hule4XZtn`8Nw8j3N zP{ov!ZbXj!&y;kN=G-iYkEH)_m9>x;MD3^>H8pJ6=s4PXi1s%^wrr~Woq}xuYA~{s zmd9>2i35&s0o)JsXrlq$wsG3CTn{`D#XOIJ#ap_U?Bxqz!v8Nb#o!Bi-JcaX6gW>^ z);(R8}Df&^In6y&UT}(4}zDR``RTGVMQg zt>FV=6+_Y-a!<4+&W2)!5{V**2>ow1km1Tfe20B0`^Wi%l_p;5lw&&=!UW?Q-`o??}hS+WE zC4pl3=%wuW?NA`PZ{W)mm8PXnNI|J~qPqf8A0Rv@jfmMFOyw0FJ#Ffh`!E8E$%c_O z{0px3N=(Owu8Q|~^69b+jwIgkqUlTsFM5=oCszt)cN&W~( z?ju~tv%^T61=I_Et?r;0&zev6vIMSa-v|YRb@$AH*)N0~FZYTs4;}sbr|;@C9Uh_! z;&j|*S9Hg{+95tM{!fJu4>M(d6*N&QPlGJP@BHCQxLZ5()sK5Z#qc`%(O|H9b+Z%R zJa4l{*?cZk(BNv5j#a3g?Nf zG`A@vbJ39ZPyHWXW{-oru_fd`-$m*u_<|Vk1`4rvqEnA@J57kEkK+lm%uo(vCutZm zULUWvvn_@`}n-2HLr8`q|Es|BY6e2prV6b=hC=WY|uS&#B3;FneaIP+R=3OB|J z$-9XZS_g6)=IHv5ek0B58Xv3r9bw@Dz?af_F<^}A zSPj3wQHM-bj6lWm$P5mLN^D8BqCSiqreKL0moxkFn9-*v*E((M9xCG<`Hnwq397@>1lI+ezK`9wy-q@ zcMU^ZSyj~MGwvV{U{beutIRy;@0eXF^x2c-AT^I6NVLK6fEAOE=KbiD<7A?Jz*8z3 zGHCK{lrDM)$Vfw`{mcpQ6h>>XqUO0j)npyy-SxBBAv7qjwe2|&KHYvr@CbDw!C=j~ z_k_2UEnRE|kE?$n%{It}Zx;#gEE}QU;$hLP&l#dqH%0W7RuHO+h(X*L4%lbdOVLYK z^tJ|Oi3NMJ-?N%;7NXg>CxKthcVnrP2dAlY!!=Rpk_)+dbBYYrYwjiILzfNxz#-;H zaQnaasGNTAfNFpsO7=w?lxbS(wlV)O@J(daiD~-KrVbtihTiVh;=%7{%zSnPple&a zBssbsldL}7W>1|w?5(XJ^KxAU92vTk;qDaop7wb#-AJQa2V+}LH)ENm)1wY3I=gS} ziu(68vw;|CdH<{@R_NyJYRw7)KdfPThcy>`IRwgOlR@Lg@VB-$_5?rSCB@gg@GF0C zGk)+$+*V2$)3oI8Ra881#L1&h7OT;G^_y9*UUUreHC~WjmMGM98kawD5xwgML(w40 z9N}eeZnApUcCoo<1KdehT1LX+sqVgMX|q@vAB?**RhS z026czQIT*>?Z-$%{N`9lXfasWK7q~Ryon+J;eQtw+JSzTGmY^iTgPkRqVh(kuXzw4 z{|Rs_07C9r!UN{hJWDEV??3G1C+GEln9AV8Gu-vqSg{;28W`Otz_tpYJ7F#OZ%?CM zg~t^*f_$}7cMXXtPpRjES;eb-wm<`z*Y@WRbz3FX)Iz9hu`B(zJLMjYP$uQsl6t+z z4c@NCZcVOIG60^ksQWeN9d7YE8PjW24s4sRv&YhGWEABN*6OcFU)mBBG@gWfRs_e= z$>IRee4A$gESLR?%)FbRqz&-Lrz(FK;7mzux;8KJ^JBO@b{rZU0Ste&E@v0WL@~cx z@RgI&hd4-KREm@XW-A$1>_o~gzmdHe`h>J~Q)ZnGma8?~$3@Z~T0iwPw_l?h0R+5F z!YrKParelAEB~d;4=oIykEIYn6Dp4nmlyV0d^SRpyXq-fL{#}|yhE~FY;LOG>YJiU zP88aS<8P2~xRAs`UGTGLSyvw}5NO~CJD6`Ce>Gjo%f|xEg5xsUF?+ykH2VR2b97YY z2BmAO0X3J4oj63(&z}z?a8dxdCAUw(4MINmPW>Vf-pPIBIcG=PuU4u-L*y2wtO`Xr zTz#8~-zq3)a=ya0L;IT|0XO)k?B_`oktH7HUG=3qX{zsdgi64h%P1Zf2FNPZ6`%Qf zk8LI&>*%@izYr?5?3u`k&yQVcdc6G=)XPgL4<4q76-I3;bnRkB1Ub5J3qzq~TYnN7 z+`_L)&N>#bwonp~Y>Q;_{Gs9}i{)U6bkkB1cXkPMOXXZN}P%gAiN znTk{V5oMN##ZI)+KvVS5o{~~aCbwV3H4zEn0j-6|ct-o!ycP-W+}a44vT=jdcAM9F9&b)Rm#-&!|2DuZrHH6?H(c}nbz>TnB?~sPP z18rX02gzDV=gz^cf1~e2ocy--1_z@h;X8Mbpl6-1NP$SXsT>{?xFwWn7uSX;(UwOf zfupD@;-}zLZW1e}a!s;M{}C`2ZG7jgURWLNP2~C&Sik4o2Y)*4gqD=h<00$l+v;HY z=K9K}%klO(_Xm4!G#MC&k#P06!5B%p@RmxXS5;=AfpIFi4lG0-{3fX_#T#=9NdGLB z1vJzwR$qT^ex^p>{D)%glkQxNm0W=$6Jt0 zDYq%rUyK!|);VYlU#`ZTO2TZMq(eGF0Q~JhtSh1=^sJS148fjd>nSONJhu!43~8Mz zZ%u|iS;#(E<4?N#gL6(oY8dJ6#^#GJ^khMussDC~i%1W+^A5uFAv<``eO~3@$9~bf zB6B)K-@CfGve$AMLv&8L{%Yft;@T_VWlq0#Ks-`L=hQhX<9W{8t9jI^o8|0XSaXp z;BrPM(o5YFZk*mf4~-%i0?B zQ>Gzo%`%>o+mVb~)^ber`~$##%r>?f^`TxjSp)jkYUQiYWp{xdK8=(&*u@geo&0qP zHm|>zY;SGplkvr2ne;yt0rJ_hJW^j#f4%LI#^)6ePhp|PnDO>GkY%?Z1%(xerTomf zaobDWU1Jk!6_C;k%()=b+XV}y1{r4{MHlsc+T1pX{nPXUq{tX3JbAF|Qz&qdxLeVM z5)0xc9#Q#Q@c>GP=J8zcK^G^K@|s-2KwTk(Vq4p031`zxQ_NjkNbG0F^?kBip6k!J ze&7A7fvBM#>&pYXJ2g8e%^`@k^n=TEXpYIWi2zt+DN*3A0I|R>dhdA2*#{@YEP z_A^0ny{gyJy3t~q}-utX)}7bsN<_R>zIj8BUB^Wo-_|MKCM>lmYLu<;dU8sXL0 z4-AY~#5pG{*u<~Jvg~YV#^c>tNAe8UZpP0H5DiJabu>faDgn42KA77ttQVRB z^BPnOpc>+$@n&w+G?15GEomsggUynXwUBiLKS8V$ROaZTrDC!a^l}aiam_#AXC{T? zmNoVgisx{ane!3eT*~AgK|&liJh5_@)k|cMP4xA1kMucEGD7!&Dvcqtq#63(`;^kY zR&(R>34CKfp~OW9pKKoPT#VW;fR(l~VI}|%R{j_4=4FpURLSQHhaD5U4seksz=0hV zhIU8>1M5d+>kgj#7OgRo1V?$sbNVSA!^x~!JEh~nsqIRV z&C1Ep^DJ$yr*?%ac36cNgYaz!QOa_%3UY`c)I2k7ksVY1bK1Xy%b1y;=Sg<>4?jpj zNXG!kDF)WGqQ)=*xW=c-DgHzC7^Kw`+A=nIfm4F2>2yOXy_&msQ%pqYr7cb zx>T+E<#(%uU+n=z1P=zPvgJxaBuagd9^&G(3O*R4HKBTw6<%*H0{O@(B@w=OGV{R< zfK%;I&zBFFNetIcXht>6Nr2K%EewH=>!i7qPs%q3R zMbqJ!-s)uiGU6hK01A0Bl4Qz%sLW|Q_PC1vFOB19REW&tZq7K)4A4;Ay`eDpWz*6t z{h)ubDLW&m@x@9S2eqCL#F9Ygxw|6Mxwjl%Oji$)%|2yt+IG~`U45@#!-+V!p9bMdwhvs2vS=j}^See#WwpywJT|0>=n3OG8=BgcN9BFZ4LP#gVmgo08` z@@dJ8Gw%JPinO4`PwW6L*3+y#T+#Z3@o6;hmfjTSuv=D+?TTVr!Tqg52ZWs_LctxsTzB4v^` z^ZAT0^+KR`jHe0PAu0pdL?YB=gjAWrL+vR#irGKJyj$w=>h=lS4BQ6gOId#$y!nXa z3q;QmQ}MedfH7S@Em$wawjEzbxOHC3hGmXuUX5-$@{(uk`wI5z8P6kxnEF?KMCPkq z9S#kQs~2+y3k6S8jJ17Sfjl8hbVKC1G`@=H&FvIwu+8~c0U1gnN+{mfo#R@f)PqLV z0^1@m=cQ%Oiwqkh(~Cz*ty7vR{1*qaHpmfH%f`{72Uw}u?ubS2Q-kj}U=#!&WW$m_ zORYwugMUWqO5d-OxaLH{HI z?_`C_l8M&nDp-?|QPB}rq(^OM~k1)adn`Ja_4 z%l_}Bf_FN7QXR;xZd!?gftB5fsJpcURM4UY1!K2XlQA#vYAD%CU{AU*|ANLhbmO=5 zmKA_kWuL=)NOP6E(hp2DxC@5x1!ELrlF1cC796t}cy#Wgtp|()rg;3_P!$cJ~I-NlfiVsG&=m)wRUzI5DMCBp)#<#)$<@# zI`m&QZMFHNDUIe4;*Rn6fY~>DnLyMYuG4Y+^)vELayh68ZvW9QCFQ}`ili~8LmgAH|YPDSB$ zDfjn#GyS%oc0Phg*o_1}ls)v@vtSn}TQT!#i@tp355R)9@Qjk<33voK4Oz4*Wmh!e z%qWuOkCz03GtF7bM~iC3xR>yo%te$!1xFa3yt$GVBXgHism_J6xebUiHSTdwxe)YE zt!Syox*e9U!Jpeq|5v7@%%QrHA0xDf(P7#1aS3QMU#85uAqfooi9ErVUFnVmr|t zB8yiL1>a)`V^<9uep1S1;!n320!Mw|<1`S1W@RvhPh)<;&tjOr=>MT0_>z6AjQ=Ib zjd8nFlxZ&eh^Ld+SZqWSX`go_q@-|&=x}lGc>kKBdNUEvXfO?C;-`)049^>z3NJkDN0&R!U zlE^(+wn1`V$(kS)6X)ix!3WB@=oTM%UU~z9SEej{90%OyW9i8JuDN}Le>a$@ODgns z*3{9=(M1`UeN{Ti^WoVv^uXlfU#`UQPwX6dROO90Lnyo90J9VZsN~Fn_nQEEzHLp= z!lnHv{v7opcrgU-;z#o!@QeDyDyT0%7of#cdDV0!QDzdcWu zk)z&puk``JnZ7=cGApuIuL#Q(WpwHSdx=q{IP@+>7w?v)xfQCwCLXEQ<%!S)@=n zE20T~My~PQ@-ibR?g)#T_W=mGw!T{GIE~twa2t|3o}}y#@ml35;zD4*lXVlC%M?m9 zFRzLDZsjnMbr0uNFvko-bS|o#@>?jGCve|4L>r#QX}%nCk(Y0DNF=zK2edE@DJ;id zHYq!0TRgYBa~HmK5UGkjl7@nIhAy#YgfG~L6Am*A{qt!E~hNW#P@5j=) z#RIuHo=B1Z1|XQ0P8+6m*{qn11{9Vv!d!yIU7hm|oQMOv_==W8@PAUTr=zwVcBpR5 z*+;$0)1cyXiWI5ME0@Ipys1`+-(KyQQEGSvmP*49x$P==wc>gVTtBxb*mZYh_coz7 zVhgR8ad`~M5fFHxM?_0$r<0J6!Kr>Q(ym~FmU)&m?_oW$^%ymwd$#S#d|7JWZ7tj- zNJ!Y$HlZadwdB7uK1@@MQMlT}C;!J^%Q5jCIKPVIoyYiU4 zaJ>k!B~UG3AYR)FdYOG~zqOa%d^T#8ckO)gsy%EDIy)GvMsL1a0Ag7WRuzt*X6#@3 zvnjT5Yn@}02)-xSVvs3<7sF>*Dn3m}G7sOrvct9hxO+cUNs!frz`=^h&_Bs{geycv z6$UZX-tM{0WCR&(d7|@vMk;bF1zj+ZN6g{l+Z$#W zYK17kp~J_|U8nV@N%r#QL7r$nU=m_Mhu7t3rc7A3q8Zk1=5y5FQJ7D}8+-{_;B#$i zx~L5kqiqBby!&6de^AK1U6kWnEi6zwm zT&KyNgppxXiE8K8s=D-=lkNHvW>sH%zt0dyYwbWq8#_8Vi!>(+`8Sp;D3?q1vYB?j zh{;+kTBXPjaga+Nw3G4yUv#&|M|S_Q@u0C5pQ7XQM=$$o#(|6>1nut0;$%xyuoZvU z#JQwmGS#ec%USQw7gj?!efy*1_t3S8NCUtCqaP`6106WhbOsxZc6yT;6+(xMMef+b9Si!g2w zN}q>w+2C~FxEHI=v_VKw&D-`}L`Edz>0$mz%-qG7m4q(ZIvpkbf^@f>Y{vjU@mokK zq(`Awd}4#O@f!8u&gx>VZZE3j^D?L*2XSMV-T|HmK0XVpLns!imQ_2r*-h$=_dW@& zl?W)hhgZyHlgqyHTX_5z%Zy5fX)4qmlvHWNxSV)#06w!39u+o8PEGcQFjH+~hVkv! zBeCqqxiF9YtPx)%Di5a7`|rKfMya(>{pAP42l{iMwt$Z#9dtUO)Oxcm<7`{Zw*t^> z5e1_1)gHan6-f|g^S+#WiP`)0RjuOBHS|>dtsB@A#1hZ-E(Uu^!c&RNaZ6L)JRXyu zyZFeto_K`LNv)|eWAHEb$|7Yefx`>sD|VKko2I=ZHKvKZ!^4=3BDtgs9>rb3D{zda~bhH(^u~QZ1^QH%-rI z29$B$?mj-^xwQjjudB0P`|4~*tm;$hEc{eVQoC*?tiuC@el_9@pUqX`?Q@Wt6ik!N z7j1vCF#)J*Z^$!ml4oFvpAKBt=lYBT^mG&tzde}WJA5W8Hx?4^(zHsNzndyr!zlcrY&6BW(1{XC zU={3JXX1|_0e(9SJZ5j+Z>!PFZTxBH^3tD_I11y{PWnXl#V|zOg$xbvey7UFQV(Px zT!@`c=JOO?QX)6y9z~=lHIH{9XOhUr*?EeN;vMYnX;%Ncc!JHK?aOTbQUFhn{ZEz^ zXbK~Iwh8A|{^=!zB0})d+M|A904*EoYtm3!9}0_se`Zax7mtiWmF`dLHpeJWtHnBx za_db$1d>~JBqG+M%Cde08%HAP>J2d=2NcE2!vV-+Y|+8ATRnacI&hr^wDj6Jpr zGE{HnmbDFXBP*Hr2n9qmbuS(TnozCf;21xX;XO{paM?ZLg8sefW|fqN+}_W&Cx`bu zPtL@6;#E9iMewpi(a^eEj?YGf+__=xxX9}TPRxP} zJE}lCBYuSG-U7^ax3K&DH>%VoW8_0*-~xnT8rDUm^%l*NP3o2V#*qr5)icDE zo*4~y#m%qB8Yevsa875GqtdIynmp9iF!|kZRz%S#mvFZWYRJ#_StLbhXY=c6jk) zKSO`^lWsKQ%%il0oQ0j9Tfpl<`%D!xj3aRDk1^9)98Df8`P58cxWacXavd&_g|k%> zimfwww9PI}5RJ6}zaRwqfrNw9&C*d)&oQe^_*%hNs=QOoCRzUC?fTZz0S=c+tYU$-d$7K|c2J-giRqEgIx!$veH5y}*;#_as`(6sJ@G5G9> zL9661-^C(-F@08?93w`FYGg3Mk7A#>Ia4&F2>}i1ONoYmxoC``dGZz$&FA`I>~r@~_Ghj@9({C#n0tafK?m8XL_fi`sv|J%LG*X2 z(FNK`T%gdcg+7-Q;B6X7GI|7L7@Ycn%jm={9XI7#W45F@8r!f4-(Fz-a@E|oV_wA8 zVvE=sByW`x-kqAXdWzQOwPL*CuK1ye3io2eUmY(V`M4+{9^u2cg{z=6IT_F9$%)tP z$}Rkn9?AcxvWt~R*2o{Eqg#x*7*{bBX_cYVuP4oBQn~#i{N9+LtZ<)FB|6 zGExp0a7RH_A z<$`vd6cy+*&}f2FZ}fI}jL=BQAmf|~ylyDXjxIQjVxLMU5>2N+b5gPxUo=_c&WTF6 z>UmtijksUUCliE)MJCuMG8<>ijg+7LF=iF37}B3C5KjO_I;g&skH(`b7DVM+FchZ} z-!I$FwG&K>7Rq8L5f{Z%g#Cw8>opF~fD!fj8{%c25j6R6+{#)uhf`+ocDi!q2%Y;) z#r*voBjWnmp?rbLT3bx z=JIo}yHM0Kyn;XeUVIE(SA(D%fc-D?O^A{^UvYnxx5g*BEx&uDvP^o_T&%=2Y+g49 z`kNPs|9QIbZ(lm{U9mSq8;g2z?dPo5CaCz#IgrK#8{1meL}FQJ%SC+-3w|Bvke{i^ zQ7J@n&cmo`4}KaFsd{evVd?7`p;~Q+HLs1~dE1Og@bnNQg;Dq(4lq|;+OdmknfW== zPs+Gky>*J`UpY6N-7giu?*YK zGPcdKdq3k9?HrZph3d=}krEL_$S@T{>~$Q_e`cJPT5JRZOmb{w7ERV707&Mu6CvfyR_NDdaqzyA#}IBYso?KvqWt*5z4U}MpHgVT z!~1cO!NEOw8jxapw76;HR8-0U%6o0UgezOIe8n_?cE z(q?WP3MJ92$eN4w=e166!Ir%@Ib+h15FZliOGHb1wl2ryV<9f|2J_%I4z9tUijC|a94U;3MfA${)T#sT4!cCJl18ZhXL3TjezU(i}nLs zxC+M(c1(2+q@9#RrVhFQ1BPSRP6_&)$>u1P;niPDcfbHk^2$d*w=9zW2u3;efRvJL?r?s2F_`OUklqnN5#2gq{(S`H9i`T6WIdLCkbdXPsP_2htW*_~~>d-g#WHcWYGYDC@CIN`#3(A<#AuwxE?-Ti z6Xw8OTAWV_%Tb{684XwjZ77ew_5c>mjSVrDkV3^{}S4Tw;z3e;;9l?tIIA%%#{ z%{VU^Cd{2$Hf;lc1AEnYF_ItUnRC?*U3A`u)saj-yo!SjVJr|VHZ@+p@dSa{#5m;S z%r6vkjNfwGDf{BD>NUGdR-WT+Ab44qceAb&$SrZTD#$-3=UMk6*}KU|gRv#Vp7&B3 z7nSl~e&X=m3=em0ESZdHkp$&8V*i&0ss{`+TfkiF214y~eF?135rw}BHL!*Zg62|K zcit&E2T8LLM47$51Q}1)^zcvcX6|}nF4R>Sw5NoY6=Sq|71~Sr4G;JoQ;aM8FN{Wq z%Y1^Kisgdf%QYRjTgH-X&T$0nz2$yj1q?1w@K1YKAdss~iC}Mg1l3%Sh)jA+YO*Yy zjnsIR1=~X4T1cXG26LJV%x9fu$$e}dkV$WsV?f9Oi@oaGCqORo^x)=bcv?`AJQv9~ zls9N7kN*j!#1d@ZvJaeqcnkH|MTW5$DYF(Zn7uJQe0sp?CEok~oIh_KK|VyB zdG5PA5RLBFdyzhQNMhm`>x~7AoWJEOGJA+GfG5sGdGcO8=-(Lf>sFdD)JE$KJ9nJN zg5XZ4m0o2!AZ&euQdnyZVnxthpJ-xHYHY^j#<`1a&@iqS;qti-P@d>T@ROsDaq|{H znFK`Z%_a_bnnwzVderf2mli@PV+u)`_5=3H?d?H!F{^PA_e#s%?Ykl^!NAnEtK&kN z&BU%IRnj(`X@(g~~%gVX&Q{(S#QaQy4Lvugu$!s z3e9xns7HY??LfrD5@@G28oZvO7ky#MM~fDH{GV*D>E+$s_P;hUT!T#BgwZ2Qa`9yD zX%yid?RW``^5$IBqNLyb_nEy&hd0LZqDGU`hVo7~Uw7v#>Dh8f9)QfzBoY1T3p99n zBZKPyhvi`b5HMoK!9Oq+XhbnWE?|(R1pPf(mDZY1T4yzLhkqQ#spC~yeY=%1(ou6S zcq6l0+Ib={XQWg~UhR{V+X;I39QsJ4y*UJ7C$!)TYvf3UfFO!C8o06Rd$zy4OB<63!+yFo$= z2{o~xhgq_`($Q;kkcIfnMi$j@q;Ry^%r65@%6l=2qo{RgHOs7X;z4QBPBjqJ)I_8# zZ`m+j2t_36jDK!5GMMY$&mvz^Hd71g9-TO|E`9fc50Z$@@d->4BRYXiX^Tv~`(Y(J zwm2cwe$qNQW^fYf&3=^9{t-qd)fr@YE(|&(>-5*lH_FnAa0TFikabwv?riuVbd5dq zVsGN-Bg5e+RH!bVCDJXs(1NVvA)Yqp zhgHU^;Dr-GtvTT4mw&e}mCtcU)`NewQDCw0{|QpDQV~E-6KS~R5siyHI9^`cwo#XW z(#jY-34rg1T$3dKs=~+mRRt=ddh?mEm`9_9-gel5dKTkYA2U;A?11h*T=;h;3JoZO zYT7Ab=gwZij!95m9k0~v^x$Vr2kXaL^Yfe4c+`6a5J9} zH_LWjDjQfn`qL~~(slS%)TG5?qVBW+lsDiKtT|rb?7_uOB*(e7japPi1BdNsFoK&$hExyN6z}C8KV-*Rr|t7DT0MXXR0@?aPo740YcVRxvwnu}cPzqnX z8YCpN18?^W*1@)b{$2D-xG}nj8bE_j(~OoF?M*`;8yy$kJ#1z*-+%KJNdJ+hZ@?5d zx5inI1&c7o>`jCK!Z0e;43w3o3RqrfsbNR9>GySQt5nPA^ujnaPIos(iA)C(wvdQy zUW`e&^#%8^T9(`JJqqN~z!A!cbO5)^U{ETV%J{H?JI#OFx%e!B`m9i|2C7~YF@=ew znO|E+Nc3#_l+tw4ck-b@!l_8ivX0paWZ}{_9BcyiPHLD(4ZCRKAF4;S?yR?s$2dqY z<-C(?us<6pd*xDC`1^h{`+b*EPyFBrv)%(N5#A&Y5!7Fs zX~`fgxpGL_-{>XlRtq;JG-25)Z9n0FA`r|xH8+ttxN^HH9z;PoC0Tj9Wu>X*5fWt84N}_TbVH0OhmfE>8A;sFq~V1=9}JqaUq5j? zgo{=Uc@{=9KgmK2Jvla{e@yR+y1?`z`XBrV1H?`ch=lIM87SKD?ge_ub!FXFOr|KW zCj!7uAEZZ{*`0oJ@CBpG6v~Xh&_GI`PKhh@zC!bwxJ4(l_JE37!yEPYpbEV#}^Q!*JT!nmAax&V>K1re8TEM0qSYvTs?Jh#b0p zF{8RuQEBZ|S4eBunOvPp=*ldQlok1S{v`&E(;_G*^8$%|JW!;j{)WpETV_ZbH>9KHYOzg7f;ZgV6XNCTB3CIeE<64;wHtB-H+#2Li zY|Fl&2deZ`*$fHdem2?%iUNrJt2FhjZX${2>0Cr+yR`-(5Zs#wO2P!?RtqVcEdNa{ zX4d$PPgXkR+51G=aPVX7t1ruXw#BXi36ogvZA@T7UJ$GxTOA#S-21D^$-AePW=3%A zF!B3IUXdZ&FLI`@a=MJYP#?svj*6qnd83p5bTY?OP=HG0om#UxFCQ|!n+ zRG8#l2Y%Ub1KY#s?^`40w`TJ-*+oiFsHo(8HLurcRU&~`pGVU}+qkaL+qpBh@&N~> zqJOr2z^#v$2I&V=&B5Do&=HHQRR7lH9@hZURBz#-a!e+kqTcyq=h3^IgNr)$Jrfd> z!b(c|t+;eui#C1sL{5=j&#v@klPk-@raQO7J<(c~U#;OKN3`}EClcM!{K(cTH?W4C z3W-4Sd5U=wfu;;_d@N~<@XLbBsx4Aq5rNdd@r_x^nt3glzMNBaX5Lnim5T;cgtZR$e4i{owfOD5Scb1?hRH#RpBC*Ogm&(UzSN7-WMsjR zi`B}=q0qWB@yR{!X01lXOw8W@-zJang_oowWXfAIuwo;Dp?GUe>ED#Ni0;MF#SFu8P|svD3a@u?L7=u9>aU+oh05-H#Gkiw)r8$;e(Nc?Dd`y_dRyRSH!yma zy%}ihz#|g8t(IcGB_%7oRld4Rcwf!kq*a*js8XQY_Sv#w9Wx`Y31g9-=xO}eM z`9!7=oTQ)DhIm(jurRc#Ty*9}!YVGQMk`OYsYRlwh2 zSrhE~6RO~R$*!uug%4QTd|fsX)6He`a3+^~Z`K2KD|Aw~wxJh6DSbb7`QL0K5N-9h zHL;^8^xEu~Jmc4^u}u=2LWR^-5!|!-)O@^u;k?MAtxtYv((eP+Wciy zB->_S=5&DDQx%StoBgQX^A3sN)`CC9VACaqa=EVxZ(X@!fi8d13jTDVOwtfsi^KU&#RBLJ-thDn91!63&6ac9VI=92aQkvT-kkL(0E zbL3dWq}e}(X8H)6XiH?Uc`kWbiz(x*hx!7PU>^`P(FoahDrmb31f4JW$*k} z4@1LKiZxf0>+scd^SMO3Aj;@TQN#Z$t(u6RbsdTux&tp-m<)>xtTQ7KP~|h|yh{Au z`43h80aEpl(Y=;JeyMm@!#h$FS-MP(vRc z6rfAS^`firz>nMH_@T{3jP|LNh*N=rOw8&i_WT4-^!#x`H}A;PmNLw9ZiKL{an&M} z5!DXFdbtmW$nX}8eevqO(X<5`-0DV9Q^kehP~n)L26zMJurLK4xA7>_V;TCV*i*U! z-vUw*(z-xLWWrjo#!{}YC7LdNh|*QJ*cw8$Gkj<^Fh0BS9N-N;545u~un(4G1&eK$ zVh~g?#_=y1&n$23CU}WEx9xMIp0R`|+l-;vpfG>UDAM9tX^b7Mr3Hemyh3MGKuD~~ zZ{^D*t%!riwH2PkT$KMr^vZx2NS41k#PQsFn;0#oihB)d~P(5i2+1D%#M#C>2 zIwQ*Fwa-LP6y@o)x8_`K%S2o;1OWB^*i~M9wty}AJxtE6w4p6M=1T)bzf?ndzCBxf zARCGNPy-An)BLin!u&QMSSZmKlFBTY?PqP6+v0SiZ0#8+IK`Eg!6nw_i(V?&P(9Vk z1hdqYSfm;vj#&m?o` zT(BCea+oGO2|Y9bdj>Xh>F!r8&RcPJ*(|*b6*p&rbcMaVl$TCX@`fNzUI)@x6PHoE z6uc}2M3Krb83Ed>Z6p&{wgtAqaBnb+H?$D`4QUS~OPh=yd&8IBQT#mB%%~ ze7RGy35B&Fv#DR!F!bpw8?_WJSLiQ8H;4@k-lwBq0WO+ z{j;@;-$Gc=UH>W1M?`#ap>gN;Z_#*!fanIq2$lEF0*9YpV|!fgzi$Q^Aj5HAAS7s{ znJG|YM^)Z+uQP(WaQagv7v0BnbAkSVwA7FE^u)Gy{V6qrIU-C=5yTMKy5oz=sV!K2 zDOKUOCsB#&i7L16?Vx13IzuWTqZ+jO`Z>Gw4aF3B*7;NH{loSDf zu+jHWkIrOv@+bZ_;C8JX-+_ArWq#&=!xU-oIfP5i&bkEevdo0noP2 z9HX4-0s{!LtK?|>>y(bAz6qc)7Hf?Rv|$T`HsB5Qytu?$1X(<}9Is8uCZ&tJKU7LF z781m&u(*R1rh>q8d&V<78o^a&cg+J&B6GCd_u#rX7Ai7nr%La=>!P}cqovv|2P-W5 z1`*PIE5rF{@oN$M-^?8N;LFJvt5RDH%JS9qIFlh{wwc#ecU|$wAu1h}>U|siwYcrG z0-GmYR(E+QfpS#IdAR@oy3v8{D+EpaE(O8G#J8wUsg?J>EB5vVADT^ZT=S(-xY~vx z=}3lbRWfF`hy_2RLp=FREb3Rwbe)=YFrh7G)B-7HViD+59m62hjM-mwZ0{g0>ymQ7 zXVCLMY+rsAQQ%RScK-@S)o9eG&ql+ENf$u_qQ`m|Ljqm$bcGC43c0!9fJE<)CSS?V zbGwlob}9k?umN1{ou)dYOtL+%fJ$YTeh>fQr&2pK8NwcJLROW1Y!bDq{KOO}qM)J5 z^ie2qlFGA-e)bNET{M=aERCKUzg@MxxX`|{#7pkrrF#U+g_vaU^c<@mAJ|j9!cQ>7 zqeW`)xaq)i{BMKBWPk$^ytLCUhiEO!nf(}wDA=FdI$=f%-4)-#4=B`s4J8+b&0Uj< zoj2N3!6p=9J=V`$$A9j?(#C?K#a4aOg;wQ)kcHrD-!sPZT{e65*`!R;BGC}z*sCMr zK*!HEeIUsFw8sI-1h;a>#{DASFpoNby&2Ev+Fo2B`g#{pxqku6keGs*D@NXY;==0w zV0`&xi%trRj^rAY*q4yl66n?Mo!!wk(A#;c-;FE>@?*TPwOO1pAFoO0(!Fmb862Rz@g); z7-i%y16i{6GrL~a;i@NM6pIZEp@H9I1DE~f(bv_xgORoVLEp$p#dU3>fs?RQOf{+L z>b|3T*8Af+kku>Ji|fuxuGpA^AL=zWI2c1VV(g=6&JJ}(SAr$MH))+3iiJXkOzCun zgr4>>R@k_w{AOqI*{u_Y*S_KZhU_D~9@uF?MV}@d+%VtI9TgCU8@3dvLl{*}@sgug z0`?(jL#@p6rXReVWhpHkG-DDvKUl8?IRaEP7lpAAU)VJNS5~;JJKB8XuEZL@;4^Fw zpG`|xGf|qKXaJNpE(*&3t*l&V}bT+TY{8D9z42lL5X3 zh&q8sCU7&~4vqk=DSx2*_JxD=EZ`;K1*B1td6njzUx zOmS<;Ac_dANo7{Se1*WcNUWr;240B!zM3cRXw%l~=z~l`JJYxK#uO6FG}=~7kd>W3 zZM4R-{7QxNJezDn3ihT>q3f?GfW+u|m$URs6_51h3(=jpNVT=UDFbOT z7knsLpWhCEj(q6!kOE|C0`1ZPDd>nOPagU9SX!fr0wyx2PlkXR#jQB0rPhg%n5J0Q zog!@EVPQG(hKRuC7M|N>jV?H~^(K7bvu~PJzPL65Rk|PGgj-3P3-}m ziKcg_!o#J~Ei&Dx2fDaQ>!b+KCY4I~+&^UpiMGLq9c4kCC+n;eY18M+inK?PS*@CHvo^hIw-H9K0z^u*hpnM z^`Cb72OFjcLkT~=^2BPPvh~59&lYUxYMxZ!6kv;NPp4L^F~(R*q{{b2@4$M@;D=Yk zb@JG=%2B$e2xh(@k_dto#}@|HO`(E`7SW;)-1@N2=M z)PS4tIzS)IdOdNlr{zMf1Vg7r<$*8?z0-fu6{2jDev=??y? zZe(%b2o=kx8P@2ZeAdC8Mn{@K8NfPKs2eh!&|w}Y9h09jBxFe+Z)7b3VW3bCf6|vJ z7@;zZv~$)Mp;F|^8b8bJ?XR{%Cd6#bWLZ@;$%#s@@5^aX5@X%04AX(ud1L-M4J2(s zvI>wr2St$VAd_y%#k~Ea*mo*Fo^mv?&f1PF4Pb4}&m4ol2C7r1C_M0^qQqr0gt77` z^>CJ(phHJ(ah+Le%eHajaViVL`gt;DFEv|J@s62LI_o>##XEV49(px>-BG2QOoGTm zc$qrvdzIzSXv%We0SDhQ0bzltXbM^Dq0**lIibw@tQ>#xGeak|hi}hs^K$ z@rbdHKsOxhLovQYeBI3i>5VPSQA<;l<&`y}WRyMfb+WsQ`$b_hv}r>J4uSNX<|>Eh z_2`kT=c=$d-Xi*k&t+a&)*x;onYMhcIt544dIO|rXF*t1qNtZJh*XD3wdS9^uS3y= zit3J5TT?tXO*&EMVm_Fb%}TuNral4?N%}dDg{#JjBDuNZ@V~+m8x%Pc)iw(%(K_H( zK29V_@}?>*MAA@*_oXzRGEp;@KfHBP>1dyyc)!x2G|EPcP?~)hmFx=E zF$@KJTHXXaxvN*;f~C>RlVaW>xagEy)A<-_;HNZa1I6$6eeTtUB}akY2yQ6_y*6<2 zHSYUFtL~mS*f-FR@{%wwi33J16PRuaB=w2m@p;)DYPsXAucS;5o8)D>!cEz2+UQBYPytmD}P?PwZk7*e{*4^KoN1X~z4338X|Y8F(ezTGMc z76iQTYAB{`6qG;Giac32G&Fu0hTC2fT51UL?$i$+N$GCWxj0h9A{FAx(Rof*5y9M5 zNjev;Zc9a}QLsVHgoz#%3;>?q*`%M&i*UC6iloOBSi_0|92DhJV-wK}*aSJ`T7EuR zLZ2zHD@Z65!;WafNy-N#Q;f>EG3paZHows`>N6XE27JrF8C365MeYy0^%YJUOaFDT z8OPyd)!Ut^*LlA#f3UmHi0%;9+uS5;RQ+;gNNe`5NEDoOQD)eOAsrBo-B&q#Yta5( z%u?nNpe&TUw6U;B-mmma0PF}NI;KC&UIlH(%r7wR;p*4ui+CAYoaJ#?UPf4P(ZgrD zh{b*g4G4HpF(UY9Ig5iwf{sYuc(_b0Y@icvUU>qrBO_vlA0+~=5!|IXqT(zu2H4sP zHkLrhM|8}SY|4^_xYsWCGo6Hr(60if4I(k0i$vYQU6lLw8+NYi?_Z`uYjVCWnY>> zrW+BNT^)Y#O#^L;RfMQ8GJHc;5sQliG8YyX%PBg4cwF&j%LY!Ni*me3IHwklN-00i zSA*Vx=J4AJJZrvX;TC&3U49*60#Sm&_d>!(x%`rxiaf_rZm(~Te|;Zz=2?o5B`%f` z?qmWxE(^NWA&RvpUWVjrN8{#v{m+2~q!j%<<5w7qyrSV;Y>!)Lbj<>zroZX|7K1{+ zN|Pv0)t|bHV8B@K6{X7kv9HE$;iaLA%ucP{;So?hb46F|ACw|R8ccPO*-;3+edIVZ zxEO8|ol^XVm|e`^qM?U(^*zX#1pQIcx66Zboh2Yt4>Eq1@0PFS_hNk?3eDjep4#d| zoZA2V57ahy(jTW4M0<=prd6A8+b{qZ;s%=d{qh?P4aP(BdHP2GKkf0VK(7hOZjSiA)8hvM>k_h7nKKQHsEc@$XO1u{ zE|VYM4vnz+1qO7-a^BQ8aWxpzYC&+M@Jy@_HI_0)4zdioOa|bRj{ceCkHvcbw7O5< z8s3eBVcy?>{R-e2Z3r|Jjw}bXM*{iIo9Yo2erqBL`$_c)hX+$ri zs@sOZ%~?dB+0~d1Mv63`)CqfI?hpS;*ZF@0B@ArE zmYQ^>{64rK#w%8B4tDK+eT$~p=CS_Ddd4$WJg=usW8aEHrF~n&4e{cqaFm0d>n$}U zJ-!>H4~_Kts*|5oFhvcm}^ zYxNu}Lc#s#Q)6IzhSini3^i*=wp1-@OTE$N$^X0#@k0*Q|M zbQ2XBDBG)b@tu$3oramE!zl}|E%ip{Z40ioA;^q*r1HzX@nzf{Oq`1hWBG$(9;$J03 zx#+KDpnte3|rs{Z?Ef{44~K338@3} zfRIKuaGH&`E0v2U52AGY?Exdm}!2+Wt+_0=H)izXS8g5+7NFRCJ!fn_79UW2J z6>Pn=RqWY_#5IV^&R(rRZwD1}uCIrqa=C+n|FG6~n8Mgk%0UCrJ4-Cb_wiguqzxZ# zx~8@Auzz975r*EDk%^u6u(yuh&~Ts7Md-~;Slz8KGMEGPIQpuy9t?+xGEm*^J!1$U zbR)E4CGUlEo$|)!d!BMI)H)vDXDm%MgtIk377Pw)0&bzC{vj48spDA&!GRY5!EE-j zZEeBec~Dq$AMkZBJ2_5(g!`toxmtXib&u7z8I9^QO*l|{#jpGlV0QkCA!%R8cIJf) zDtz=AV@ssIX8K&gVRBhTL}8VY@fYxXfFx@?gdxS9bYY$;pUq3v?e->|hcR*OysHcOhMcU8xa-cL{xa-&B#l$o*qN=k% zu+q^hJ|X=jE}u;Da{#mT^_{HdiaPpFU+o(XJ|9jW&t$*9IA_1M5RX zMr`T!aQBpZj?SwNd|#>twuXVayT-303J(dMB%;4=oDlN7e2;I33j;)XvFc#~xND2S zR>d$nkiq@$9vJs3L8O-edU&U9l^={8p*!sHoE-<|btTO1M(7PK@8(s_w%Vp%cr}Uj zSk;`WhtOn>Pct+)#M2q=#s=z}UZWaBVKvd!4CN33+||NL?} z*#+&wLsc#8B!jotM!$Fhs){OOVMo}qv>=V1OHhpNkcN9`rpY?{MG+&!AEca}KV@$S zHM#t7$t|X4aLQSV>^)C8byfg(0(g1LqwAkG%RnQ04Zo(L=XLlU43y6s1?z8awsr1m zD&4Xnb-9vVkk2Q<-P!~@4LfsNw!H*C_JyvvKAo5wr`LU`CN_T9#&@R5)tDhmY^JZ0DGbEGyo6|d9mDp;PT4b zi;!c-k)!a{gdFZbhM{5f0vD(`&F!WdMAEkFn}QUVhQJOYsB%;oVFmi`8?Uy8^W{-& zG*>4VsNnGjSS3Wym8Fv&Qw}enDg-k=fbsu)4Fp;A2x$t*G~Y#|qHBjZh1hLi>jsgl ztS=Jxu{rvuX2xYk!o>@39Iz z>KXl3jF0L{RWzxqujjZO_ss#oO@7J#?T_&7woDiIxg)hW;|5eAQwumt!&h^-GmdS) z{Uh?Gj}|Hn38TjZHFpO^StE{21E~0m0YgQIkPG4&2v=#yt8~ucLZ4Q+6_^;En}LsE zTIl8*$cE75w^n|D03_m>E~C*IANy}$jHR0sw5KH3xAe1Farz{8@BLn20v0n}C4D@! zZ_C8hSMtu14;a0iACx2+l!TyGxb^yC-K#t6>qQoT(r}W5F13!*%LpFT;CaIwk>w*H zs8_}Q9lH*ju4b(ZNv52VK=ur4*CZ&qKsK`Z`3)az|AyLZ3hcAhDAp| zURt-~k}?cS$OfGw%+wg;dEFq$rk|kpTbx`9O*As)9%jG@ncpHOOqP;Bz zwWgx^x=eSgl2o}=)4j){QpTJJ$jo)OYRetyv1PY-{_SCgT0?95&@WYkbgu9rZ@B+v zS5o>V4|5_eoMBFK)$uE>&pqbi;qoR`47O^cIjj(S2`H07F~h+t>6A67eI2Nd2ba1! zyQOUx%`a~@yk0+|AoepBg|rIG4bXpx@YxR;$N(aVx}j^j!181z8+jqMd>2Z{nEY*W zrks=388t@sd?R{aap1t^atHHFZN z={pMCbqK@A=SURL|P(y^{>8Egkvj`sPf^|b8oDER9EAn z&!7p{s5O?|1Ac~s>&{*9)JBo<&Ys=TlzXWrYK1XTO&v5VYFlsnB$xOvFbhF2jb^{t zuET#I4iKlQdY3zQ|2B9(NJp$AKeE9J# zhI)W}QUdGr7U*9>SIctQq&L1m2aQl?ZzC0TH3>B(Aj~nn5}%>lf}lQK`dO~t2rObF zLg&Vht75%+gobImNoAx*w6OUJ>cZ{;Dde~%ae-@cwaM2i*iSJY00&1Zqo*qTXKb8hZs=Y7Q6 zDcoM}4C_rAk=%W=VckUfn#b+fN2N@@|NjSF=x>dkk}x|`ci3pHrQ8kDPeLYkz$<4wi>~-$T1J! zxE-wKbm$N-^{LUU{@E2~K%edA-tai(K|Fl{!wYn3h9^@AKa!*-5=r|lyQY!=MSyqc{#AaxRwL6STrmhQj^AVF;+`ahPE0{~ISu7xxu_$F#<7DFmE^AWuOL3tj!TDZokiplBqIxLh} zVI#W@dszAoP;$yUlhn9mR`-j@CKN=Nj;BF^AID6O(n49b_3O-UjA~9cDGvLJVm^lC z5RjnhfTD1ug+Ca!eeJ%zu$E5A>aRZYt~1cXn&7UA>rDbZcCoV&HQK*Mep*p zkd)7u??U#o70IYZC?Sz61@7DP&>^{)DhoZZKq3du6hQpnR1=~#MS{;5V#rBMGc1gs z=V8i^ZhqOl@?0d(R*V2Nt8NWLD!V}`QiK0v7h%|<%mS&yw1|AaG96!Dj}`^yjVMl_ zN7EL)iqK2zwccbXT%!vDD8uWTIke&`7g_Qwd!eJU-`%=p9Jqui4{;6DWbJz#ON$@( zM)JbuE|~tJ`~f^N;~$Rj?g8MeTU-gKL_8jVSx_2CeNV3*qopmdC67f){D*UlbmJr& z-&DB-Oxqc4uH^NrQ$5^nm>V=rXYuQ5cH~inVIeRW0`XuH#{vDgBtdg{i-I#TdF;Ip z>m_#!tuj7!2V~0BI0sQMq0W;uO)q*bgD%*+{7OcaS}^D)?8bBax5?9b;`dt2ysS*C zlauU^2dri}BgeLc*BzTy_wH^iPc44V!#5jgJtqF~RwGj>&D#-9n|5jK3f3HARDS?7 zDY}uECkaeK?=&6{Zds1<13B{Td^~doZAgH=zU1};753I+Kd(g_MBWM}^f#<|IolCC zhw^T#_7vCz|L2z*|D(K5H$YS^dEtPBYn-z4OUS}|o>B1UOk3Gr;v`aWpUlnDZ)?W6 z7qB64Qj!%Log& z%HJ^ykOL5n9DwiGY8Z#HyfF&jN>c)^Y(At<(TI8 zYr0XwCkFT#ZAJssMP^^AK-3bV>uOwSZPV;wx3?=$7rdwMvEY1C0uu_hG!6-=aZlp? zB?GSZpu5M}f!zZ989};E8?FyEEdo35t^DC@_n&ugM{k+wP;r=Fz~>mlDl_QTX9mxg zVj@-`-FWJ^He}4M8*f;O|1g{tnJ(IIGb?wC(^)H_6R$g|i>Wq#1hY#>p@-plQM7r$ z)v^>nrxU}PI{yB3ulIe{Sm|%b_f8pdQ8ec2&fmGn7ME2#}p+-toTl{i1a^npeD`^TnAL@;`(gm`mF< z-_BrU89!Pp%gLe|)p8OcpC@l8=r5x{){qdi)p?O5RoGg){V7r6^C zl#YD~(gNFSUb3R!0xX=00%cBDI)Qj2)L076t@1@=K99`PUTx(dbl=v zui86YYjmOm3@&JcK&2?_)FpwGJn20S)%bfR3QIkiqII7bh^31C5ZnbiGY8s?{~J40 z(aPK)%jDMm3C)7c{*=Sbkr~re=Cw_!tJYUZNym*qEAptRurMn}U1sQjzW78q8drw- z%i>x+#>}$ibhq2?)IzJj%DT-V2!5kZIfGOld>9&0cS2Rg%n1?xYEEC`SokGYA+IQw zCaF=9HRw0d&3sdN?`>z zQ;|R(j*Q@e)qC6&Rl>LVz(P`^`$KUd5bDt!(}cnqWkuo~qfZ~uW?Vs+j3*%Ggre69 z%S8~%K5b3PzmqaE)g@%ndqXFsDtMo<1eK*jsi-`8xyzpZq!0B6tq)1oTcZFhi+FI0 zH^cBc;c%9gC7`;%+9g znRK@iej@XF-Sd1Q)UgYTm_3b_h3$ipJlsyw*Bh!Z+XKdwRc{>`0bc}C*=k7YH(eN$ zR)J{ml&`tQ#I)2!W;35aukD^FBm0CJ3X7!(l=KRJDQY>QKYd~Lv@7S-Kw;VutyO<$ zcW~2;2(D6Hdbc!cEk_a-*?+|(W$u)xS!ehdq#)%JAtPY^a0k5Ru)EtsOk3yyztcTpB3A;tm=ILd#RVoh-o!AQ0{o*$&J zoRrYWa13YP_x1rJZWSPgZup1k&(cPIm-ncY&E-WLYKfXE=uTc@gxBR5uaN0~?hDa) zozV@MW81>$@bcS=+qzZ}F9o|R)<=dihfUXL0=X{yre2gWxbYLBvKgi4|3z7maACn~ zN2G6sUm$7aX80HxVg@%qlVxRR(iH_$=2(OM6$j-|-Qc{>fcTJK%RncF7rP?uR2a@7 zsUB0gsn69#&Hsm;zE$ZHx<%Qq8WPER4$rfjvog2siYSUKI$kaOekd zp8c5p3x!3t1Pcg4)(WGjY+EcHIcCR&f3bZyY*SYnwEj3GLX~V48$q~&emAdyTp$~L z$|#>mNmG*tyd z5iy*$?V~Jik4; zl_oH?gB^$nAR5DHa{9PLP6ww@YY546H_tmcVY0RQqI{z;(s*uadPzRI&4+WS+*7^x z=VI@W5Hq2eU#WPFV+3&j$1b$4Ui{|AMnSziev}VNIU64BQa$JA@jlRv&yaXdk05w_ zOWnQx7>^(}!%>dT<+(c|CXf2YFZ#wTACDY+=Aa4l_p9>ZdVXl>nAzs7I{n5|PNEQ9 zF<=x=10F~hOKUjpfL+W%Q@@ot*0E49^ni7Vr8xA7HQ8aNMu+h{2N4>N0DxpOgT_*h zeiE--A;gwneMA8&SF7DQGhA(1BcmzpL{7p$ADA{m^}{e!vG>eK3C)(0# z30gr!h|KSZ39N#wwn@T3|Dz3{jH-q_gHW33ds-@>Aih0gOuP>R!vNVjZs6~T1*#34 zW8tAW`AkM5<`}=>o68{`hx8Csitl%#w9Je=>YiCAng$wh^dk-&-7S&kL$+{w+y1H zbJ!X0PES|#Hvc9jM-$|WcQPk2Y5nD6I`ua+>NZ z%-XF`sY*jin&em){m6sGHSq2(#no;l4>F+cmfPL<@L3h(hMO>z*Im;X5UfGVm)|$e9V2% z+pGVNA|nmb|ykUMGZ=GjYK`#Sf%XMN>Z&LXQ??c5mo$XC9Yol zG{}F_k|?NVJ5dU84G$P(0VOsINF1>U6}En&QJvn6d!AueIqso=<8A-d(0xB{VIav3 z{=B4XS?Ph%dqY{h{ZNXlaAvVKJy~*~W)*Cw^0>i0Q;{6 z*CtpF(Sq7v)D@LO#Fg#|kj8MN_F&_d6)N?kUdZZXNBV9J3fsqH=IJgI?Rl}qhC;(1 z*~>Q>w$jyc>}i(>cydGL-0il&jE7NpULTK1ju|{#*71_xw)Jg4WUI-sOoM~?NO6iG z2N%&yJn>NfRTN+@hR!m=tK;z|AocdgX$0xS`-YCP7CVNMYXU0g@|$jsO%*HoTUq^) zsZ)?+-Q{Y4R@X6`aOhNZVoF%o37{FO{H8;Bd|GO6^K5tqjh{bIj-?ffSzJa?odu z28ni-pTNWH<1=ezvwL&f_ynm}vpN=Pwrpg!0|l&^75N9T+@6#Dy}y2-QZLNr?c`@;&+0FS}(-xS3;?0B-j`EO}C;`-quRg!hP z{{cmj*p=uuTr%f|%*%RD4>jImt!$_2rw}~;91#TIEvD)<6MMH1^x=T!6E>LB^!=k^ z6>Ihrq=%31D~FW3_oR-H86aKLJ4Qy{lDS0h*Mg$P$poe)qygA3dsnDh7XbhzQw1}@ z>s!GF^LC?;+z3PgRX1{zU>8WD$DY)L-E(wso$SkaNL3CW+JM zqwiJ4ECDZHFX-1Zb$q;UXGl12aY)ZQhv47;mmkgB>5am~318}x={CN+2^NfVkRddV zU@KY74YskfB0^khhRFP|R6Q^Y-cAI$gI2bR)D3s@EXYJ8Yt~UECf9;U>C0q=C$}Tn z{r}CQCXD)r6X5X&;I}DZI3aD&j$?4zdnk^FNFSE^Cs=N4=TWx3OYy&9IXQQ;+=6jH zWTmkxu)G?gdm)IqmWrZ`pi0Srmn4`S$Il_tRqMv4s=B@fk`w}oR(n&sobL$9Q94Yb z(1zlGHc8IbwCjj-I6zxh0lOq>V#fFLAA5AijB|XztC;-H9D<>}e}QcXALZqgg;kzg z$-Vl=kGM^6E|hlLMGI6C03^`4{)ptuyRjbq!uf53xpTgPjjWv-ep3R5I9rF?Pt@ix zTxLdmXrKq_dT^(0Q1w@;qB&wX>6fV1DM_06k%p;Ay<6>HjBknXsMkGL{WWaVUs$aY zmE7lXNEAOEUljwLzKfjBajEhVLeBD#J`}kv5Xm)dT+Hv2eA6Gmgs(X8WzEpqsC}fY z>m4(<-^*YpItp89Ae-;Yg(Y*X0R%rzyd|=Nl|jk>y+=WPzv6;`1SmOD;}g}ijm63H zAq}>JgPdH#bQLm8>z@oCx!`L_t5~vpq*FLg{aWH#n1!L49bw|O!ZDB1N7}PZUVO- zs5*qe1kTj|S!y!z+6DoXrsG2M7RX}uLtBp*NOZF~!dZT~tq&I^lh#t1f2w@`r>;x) zqc4bSr|v{CD^_fb2atOHa+vw6b)bqdEE2Nb^ zhi+Kn2=y}r0tjE0@$6s8LQ{kX97eL_?VWh;a8qoPH{mnS5fGwRun2o~iO!i- zW5+IOM;uyio`u{bta}y;f>n|Y9zwfe`y@9$0%9MYi zgs6PFq4+6zG;v3@E7;g-&On8aMpwWgu+);9_?R{r%>0iAZ2%m6GH@K7?$sW$#+8GB zja0}~=BJcwzfaQSA<$?LYn8I{Nml};QGpPHigx36pjfPOgk;WnWO~N*$Ow(D()KRb zL~^$m|LEX- zCQF!;7OImA-rD9hPJv$(vr{KXPUi^Ru6rea&?kg*1{pdnE5m*cs3MW^)dOV|ed-Kc z=es73=>SSXMrNov3||aytb^I4y(hUrIa<#HmCh|wTo0OreO4p;6WpHY(PlgwXv?M& zW5B{Fpj>#Iqs=%%uu%qZiS7WXQh&p5unec9(+HXOAtG+Cw~WfmYSH9}qx&fw-D?$h^Q=Hyt8uH5Y!CKYtYvAROde#Zn ze#3bcZ_xWQOpw&2xpCA}aI8k^fN%oxrvdltg*9Wyve|u#gm&So$rToa@ir690sNh| zFA{H57+s-nog+=8XkXNRaPXZ5RZE?-?T>m@{EDuH)0YB@|40ViR-e?6W5LW0_+R8s zKGqL;ttqm*Gv#`=QEkLA{*9^|aUrYo+|4eE?|(IZ^nxu$X_b8%;ks80pvbT?e-#@X z05?F$znyv=`pm#1$`fFDWuv5rT9|9M<(dq&Gh@FHX_}CHf>SW>aaUbji0-I|2j5hQ zXJ-gz)|2U_*CUa2ORg8WH+Z=MCnRmli?sFnMpKsQUi6Iz* ztB!t*YsC3?rDGeE1@qUVYk-bl2GLUitfqK)NR#@co-b*rfL7W(T8*m@Pi;f z$mjB^S~C9+istN)--{=Cer0Fww31J$xGx6++kb@vN=^?Ss~K#AKV7w`4h(q-j|qUA z3){5ViF|70_I=8ayeXEn4=->7=d@m+^G5Q2Sj`W5EL)Ou)h=F^>Qu!q@%3;2)9r8A$=g}_Ewz%{;AK9iFOfufDP*nJst&J; z<|JWraGcsog3S-H`#@?5QICwO1z0D*CN(BD;$Y8SOJ-fVgpH{Bi87nZhs1wazmhV$ zcCIB+w{rWq@M1$u+*7#ITGjpHjfByK|9DB8lMtU+0^h(E7WjrxkjsXn(cVONWJu|9 z?6}MOrYh@I25LGdc!TMG)zPv9a_$1V&s_Qt`JtQeEg!Uk`WfR32qq5~KWt=Qq;H;6 zGWQhnM$3I5f~8ennmsgXEfHtS?E=5Dtf)u=RV5dvv2 zHsK1B2K5GTKJ8ll6f&H4bEUZVRAX-ZDI=izf*L^Jyhv?79_f&|u%TG{#Efn_1DW)Y z0FnwV%kptW%D)YKeGVt@CLw65=}~Aw73fsjW}_l0Fqs|RW%57rEiZOcHTdIk9Z6@~ z$_FGEF+{lV>TOt-jRiMdu5|}BA(%O)!ah=|P4`yygf&2k5K2O9+TxU8NHQG42k;YO zgTzk;kk;$JFpX<(l#NATU)J&$MDW5(9`wjHoJAG1?q_Jix5S~o&$2Ba#P)SXIILXUqXGJRRBXH zNgQu9@1rwlsr3b;o}%mma9tZ>5W9S;rrOUqm!;0`FJbiZ)>Wj2U`%J4GItNgplc|b z9b5zWf^bib69tl0eaF^DVZUvQ_kyL$7NFB{noq$;M5^^o!O{Xz=`G|{;vyJ9TBuHS zV>kV!1f@b^+=oWO*D7-{>k_l)-j^7kRGM`G*i+o^e`bDigF5C(%UgTGq;)W1;*@4$O!t2bO&{O)~oqc&5#xU4G6(V?wJylMg${1>Y ze+_XKlDYFR+w&VPaI?MfWK8eqP9m(<^d+QUT^ie>6Z! zPIaJq)YolZ=5(QcO=)&+qR5sldB(eErS4s9Bs&i4mjB@f9$1PR#?N*oQ7Bcjw4Y@> zt#Kkf?2i#rx_T*qSkUYDV{}JtIV$Qpih;Z)I%iE-s0ee+Od+yEu{}^TA&!!)nX4k2 ze#+cv?6Le&uQ9oKJWw&PQ_EjXRz5!%uV*bsk^bEqJ8n|I2V%Ybkmv)FYtj8|f}EYK zA}hl8S$Pqb*T#ISVXu4R&U0t}E5y-2=WLKzENqY0=-O^gJmy#0HMoTNVmeP&vXo$S zFVdB@NxVNjvw~1xt#up+pvYIv;@Fz#V(=a7Bxu-7nYzU6(DE{U;Oc1>v6m^~3)B5L zGs%cg(Z#+Z>saP9$nGkRRI9-m3vu1z4Wn1LG z2`zS08`rIYF~4x89R*~u@qNyju!a4%ObJHo{f-vi+!XMPuHT2Sp<#lK+5E#QYbX2Q zou?YU^;rHS-^87^q~hLb$e(g$BOGloY-}k@-%2oVW*8m$N6c8yL%v4`4x9Ozfy^hZ z8sJ+vTB#5*U|D8W{gB~6!TtFf+OkzsvgmgNFS<+Q+@{w;YlOjw z$r0g5QPv>U?Z@Mihj904Hb0i`-VmP$BvutCC2M2Jxc#TJjj7l-{hrNA2`K|UKn(cp zN+v400V+B|-UBr=_mPN>C|%`W+XLP+>Q-{N-T7mAn{#Z!B5>?Yh;NdM<2+QDfr)yq zo#49>-IivUXaGi`^mpF^VaqiO0J&dyrlTQ`fQ+?KJR->qqU58W9vZKk%vCdDzu_UX zD&CR*)+3=w*v7uD{P%&xrAZ06er^2Kc$v-*Xa1m6Y&>1vEsIHAl!Cevf%9lC;4E&Y z$GF$F*OY0yKo|s``ZHfh`M;d&wD8|G`eJc-FYCRY3t(?GfN(8XEw;L&7@6aTE;&x0 zS4v8sPIJGndLp`4amxlYl;Ri)Gx37N=Sy~Wdh;SaemOU!{3fFX{p1XD9|D}}oQ5o6 ztL$|$+R-mtPgVzN{+|m5Hwji^;~6p^C%IMbRN8(EnK`?|WGQUD(LvXL{|H-@QUFf6 z2B?s4j?zxg^v?~xxf~$NPYhl+I^xgXLX;&>mUf(TeryAX>4Cxy9_>>-f}i9a1~n@j z*;W(YS>;6CrP9%47cMR$`^E?tFrGHjm?_VgDrI-`guAuEsm&>4rqG=VeV&p$U z!JgB*7Zy_PKFW~82OB+76wM`Qtx*uhfj4K0G;eD@n>qJdnvfJBni|u#(t1}A;O50c z47ueHR5N0b6hsuh5IYGixdMV1rYZaa$12EupyMMqRqM6pMAJin0EvzK)GOb}AwWZS z*7m0LuZdym`fvX{?oBPMTybKf&Hat~W7(nPycDXnr}s>IVK}8w$$tZR;G{O8Pl$B} z-sL~kXX{eMJxj7w;B&fBKW5y@jArbtoz?Uc&~4(0u`r%xnCO2Do%U`M|M{Sqz-ewj z6b{i+Y#Q9!ycxw|G3W-sTV?lXM=|AxF&0=yGB|;bh85t8J$RChAed$hlpuKOWce*_ ze}!*2WL?iX6H@l47KjATDv%T$=;1*Rz)vk%i0TH;Wu~FZdg5s34p<8TtMQKJbW^Z# zr{e^qjqkv1`3Iu+XdZNDjhHBXDp>ym0$9E1z zbVsDeyS#h%b&*)#4}7$Nz$-c18u2hyxDkZ9{heBD&fOH!H|O~_KU_?;ucG8jvM?Go zi;49JkTH$xZNs z_swHVa|FENaY#dY;Qvxu_}k0woVsxPZ^C9bj%voJ9SP~Jh=}AoH1H@fT}+h|b4#8s z*0#`c%evE@I;F89NvPL??yo_&LCQ(pjj|=~wwy|e4X&0Fvy%AaB&W%#nNTjh12F>Jcn)neUVkY{5I`xps zYTiql2cQaqhp&WC76OhPe{?_Ra0J)J~w3bFRy2qFW-mt#kr02TemvF@*=Ma9SI=ea8Qs)Wq$$RjFyN@PmJFQ?SNc zVVbEhK$bVOG?SFjhb|4-`1aW%tpZW@>FjuRpq-f|mbqcY%Tk}+PyEcX8Z;b59w_qw z>iu7*MM47K+WXgYdwU$uck6==ZeMM{_-?$dFauHi(sH~WkjR9lEyo+Ag&bT8u^hBG z`}x@+mn{ysx_eu%TGDZ1X=6&dDk-KMlPd>-We($%;p{bQ#ipYdSJ_+rSD_Q6+&->4 zM*94(bSi@6STC@cm;1Y#tw9}pl z{D@nGpv1K3!c@y?ULB;y=1vQ$C30{eQH+~rOKAEK+M1f`tUxjcZEgohtA}5x^6$2 z{UjZ9z@HP071k09&zi+d=^bSuT@7I=g@833}#s!s+dB$f51gf}Ts=i;M zIFS;l>qAE1-z7g^}W%4E$I;NDB5+0!ibEPOx4+WTb^JD(bh6(|1pDERAG6^Ow#NPyL zp-Mr&*wUtF3^}Mt`40GVeM?5{r&Voy5^kHpY9rJI4AE;I%{Gv4!(Ri^VH|-c3G777 zd|9bCwI*OmtOP`qgJl1SZSmfxXuM#q>BQYe{2z8KTCxK4?czfMIDBWbeFb5YwN^=cdb}X zhrx(a-ORR2R(_gNu2AV!`G`}fN77-NNaH1pnX#*PRWVbqJg!sEU`yZDHsze``T5vt zycnwqCy~jfq$;9%Q;X~O=7fE2Uld$0F@iDn#S)-_={WL}YWEhHcQkjJH93vx!tg%w zVL*{9qtJ0@JQgmB`|C*{$YpKNNBRFtFelkJTRvBe>m6_Lhw!ivJq*fch7rE=BLdX} zenZ0KmDD{XY0SQl$R<;}^J?c(v}D2Zyr1;3st1flUzt#fG!G-D;AK%ys)#0^|NZ$R zmur`^=7U`6dx=gV@_0Y`gB^PSCb0j3u0(S%?7iN$1ODmYYo5ytwTJ@32p=s|KzEg0 z#<2JTpb28MLIi#pmyVhzA@o+RmvYzr`@edU5^8=dNvXvsS3Ktcs_$7;T7_+MF^XTof)sXQR91=wb2pI!`D{>0fd{Xp0+Bx^JaO4lq#G+!Ip18*#ZHD6WMY= zG88qs=M?mh4;i7?;YNo5FNy()uZ{kdocLI|A-!<)7qjWPU`3kJT&l&XOA~ zJo^&_$sb07mfQWTm6tA|3oLrdwrCnbt9~Y8-o)t(x8H8H(93hils%+9S3`#;=NXuT z(`p~QdHkgwoqFpM$#iLtgoh1#GPgEc0qJAaS?4Z?RAVSKzK2MBIpel{wLit8&3m0n zt!IY3n0k~pxG$~T3)6mz(wQ2;waO;(Y(l8Z+KV(_5)QnG_-pO3ls$VDrWz(uzZ5yD z`L)TTPZ3a~gPCAjp~G@W46PX#uC2(&;BP`XhK|JR{7HdP?GjSQC9)XE6??d6NB?k% z(H@A$ZCcq>JfY-<$Vm(C&hFWxM%hYPVQ(0A+f-ZmMyvGbSIkvM@p)EZQCt_v1n$IP ziseVOv35FV|Fu06k2S0BoI+iYAD1My3cQT9YUZ(O+n8!1FxDN7%PfVA2Zyc*5DAxs z=u+<;1o5Ido`e7l;e;@1v7k@8TVZxd!yk=1#XAG|xE6_dlg15D7}YuIth+5sXk@rk z%7&FmOc>iqy1Tng!jA=)U{7iV!l3zJ9_+Nmsl2awCjr;g}ohuneao_n4w8az06UJ;Mcm;K5%bxX!1_O)yYQI z$JCv#J4VP(X9Rry)%8pRBD}`psb{exjvco`1|PNVUS(7Lp^|6`C=OfA87v<6!eZU5 zv;=)&nN-4(44$mnIG0?M1iLld=nn_Uhk+mfX=aSh+=TeF--yHLmZVa(02xBKwm^9i z=z5~Js$|$6C9(cZv~oEect|xbgo^XQ^yoH$PcrHedRmd1SHSo@@w)b+fhIC2nC7kC zR|`^gV|Gp?0H1DNs|Jd3Q%f#kM7Hvn)BmYncOWPl#=$#~HdCMqTC*55_Mn9dPTn8| zgD;iN?}Gw{br~3Q5HpF^-P|ju{VUIX)PcBbsvw-eK-*9$P*t6THXkgo>gkEdkg?@u zXn$3;5aV#N@2Hz?pVhn5B$=d0JEh0rgsA{z+I?Fqlg7yBzffjS;--FOouv`UtSH$- zbm>Z~|{-TB-q|n5dDClHHtB%d+be>4bn7s$N>R_RK^3&1TgGQoPax3HNKvXb!U@ zOYk8r&0i4vz5USHxk&-mX78%x7Y`3Qys#d_H?%XARil3lwtA z?gV{_Y=Mf`egL?$&9jOyTR8nW8RJqiFv{sowY|1vD@$Cr1x7I>+k^T!9DNm4`Ciw7 zjL_w$q-xQnDV&_wLn$t+zD}`!d(q*2#LOT3;W*9lQe{?PHAz<}D@H3i9q%#K*>!|^ z{>ogQaBuD7O@d24J^9tu&oAt&+Aos1fbT%V(^X)mBI$WYMI{cEb?z<1!5bmQ4d;PX zl@5V|1@zL<+3evK$uM>HWU(?_mKm}1ADkCcyv~OsyNh*X zHOLIRKzd8bu3j=nN#BrBvDGrhKYH}AQs)#cyr^GqWp!lO!uS$q_x~JTtiGL*r^VE4 zYK{BO7^a41{(7*3ot#2xji+dobin80O8mQk>0q1w3hopl3Ko6;376xTF;qTp_Lf$F$!Dnbg09tOr=dzXSi-Cg+D$x2%fcII==8{nj?bqNw>2BN z6-|}?!TKa{ze|U%h5eZ^DS-Pt$OVNbC%m4pL1bgx9^3caQf> zUIq{yAr`JhyWgqjt6WzJU#{0#&2Imaq|5iBx88A|IZ>9|-2sOfsIgeoqJuX=awmbl zLvWWtA9kIJ0{`E&u1J7Ux(*U$+)ypwQ+(j(+wPA}Toi7D+UNbK78C3jtZ>ot*z&X} zx^L%QTs9rDgO7vLFaS?%tZ>f*#$gbcz#LY0QOrm&`s~UHLlyTCJ@GSNny?l1Py8b3 z032Fx72@nGWv+JJusnEZxmE)SBcKcLn~}D306QFa0*3wu&qPb=)oF;k@PH-@jV1kR zmwP!SGF_WQSQHl0OzoQ7gO|nn);2)!as0h|p6iqcEl^DFyVRx8*msGb3hBI&4@Y-d zI>m=pir8y%{EN+Twhc-HNw8}4-DZEW#r+wMKj903HVB%K_AE?r|IqP%_ zY9rQdNMffvwN1I;USGl;hb4l1*oR+Z|3W{?bZx@+uYA8rm)U0dFkO)n%d$7-B8>DGQB+qhdytBKCvW|?^g%6BZ}WUWT{ zNo+zS%T)dpsp{(oaK8hM3&2l1^V^bq=r3X~Tj*ThHR2}yrtkHyWK*N?x;ml~rReQR z(vb{m?a?~n4K&tJK8wb8@1r0_U4fAG$>mT;8gx{9*aQnCLu z!^wQB-DYjS)l*~>s#fNV2hVQc5MsxEtDiLvp__6~PSFz%7c!}dFT3x8Z1)>1LcGcw zGH)z?xO-*7(GoQc9>@q3WmGsIWSFDB4TgqB2+wRyD8v=2vi#2$I(2s$w(ROGLl`O& zpxcDuU)AC`vJvoMHPSBznUea{1IR$Xv5a4ngEYsTpu3=rp-{%F2N?sVyH!0eh`cwc z+XbUIk{hv}ZfG$pLp4$IbjacX#kSCxj7Atz@oFiYNUWK6yoe~xJKL7p@Q`d)5e2Wm zt{?#e+UZiMVQGIYy~kPM7FOc`uu>FU@TY(+qA{)%kG;eAcN<|5x-LiCaJ{UGwk%M0 zG8NG?(5!zl$#Nx~F1j5Q<>_!i6Y-w>CpxUR6K$(IVeHtPGSHJq6(9gMABo z(SW@85WJRBU;vZ=G9zjd1w9~v3)t=1NAN%RX_7BY=o{e$v?dkT9$E4{tj3q^sK$B*O`^H<|>h>X-FrsEdvvW=(wfgSiAPMCl$G@sjDR^j-4H z!q-lhBW_G|K{N+DV0qR^S#xp<8O>qcY1%G~8F*!6wBsCYKisdk($<)NM*v z)eR+Run1TaDk*JkSs(E%F*mR-@`R`^`7I3c9u2cci+-~<%&Cn&0=1}1hf`Nj`ZRQ! z7NYI}OaK|L#Omyi-wPItLOTxcykcfo$~qtH?Jx5>b+eJaBz?T#CtI2&0ldMvlz49} z&-}8BRzbArwaut)I6l1)3hX_I$7W?$r+&=G9_iu}9nqT9CzB9Z4lybkrm3`AUtdEY zYlz(lsbU~;bnI>>IrfSIR@sF~Y|@6Tz0Oog8Blbb=pF%dNJBd$J{!Oa12i%p`%8}$ zlMAsL@i$qRVVGgbwy9V)cUr0ad+H?X6b`f*@_U=_NpX@JMr}w-Qdl)#b2<)srpkz8 z{Ac3RQqil`i9*wt`(V$`yuHy)InlO>Id>uY0opZfbo2Xoe(0V>#zE}c7;zg?{!%S7 z>#`ds5SAl(gB>qIH_pFzb40-gcs)z1frjI<@&g;lY!k)>+$To1P~nB5Ic%DpvA1 z+Fj#@a7-e{fi#CP-hi2*})OmR^PE*uu<6 zp?n-7CT#VR$X(EYeK|i!6*edFU4Z<_xrxqqu_J52y#iBwuIjuPX4Z_(x5gP>T9!!9 z?TEU@{bvTY?}Hd7Q12+jkRP)Zb#}yV*|-`9a^0R5dSlJuwT2L%2X3ai^i|F3hQvi7*Dc7MJ9981HHPvpoJ!&p4ot z^ZvlPI_2rTC{N~OMCDmJO5%g3Y68GlE-dKf-Mkys)q|LyHlYjqHy=~Y5L&PbiPS5y zMyz$#AU}09m)>C6g5IjFWoBu84TytzeZsJaG--|op;Blawzdg2TLaFp7s0$49wJa~ z2CZceCf6>2-##nFO~Ep=L6QMjDG6pP#dW>L#d_T3K{8XCjT4LO7g zX$Io>?|Fn(!pBW6>L=H3!*IV|HuKl6CIJ6^hF+rA*CYU|sVNO(fGD3veDY=(ii5A4 zh&XUa)m8zVc4}6aX%rVqoxus)k!6b1U&}1=f_t(a7M~O$;!7K zXK$$06!dmqniNar9zz!|#%1Z&6CII?xq2ld&EV1keJd4kOmA9kUO3!r5UKIto+r3A z=v6xVmny~hQFA_f?Vxgziw0$4tfkL&qGXw|<1zXbYqATsp1Zik&YYqPU@c~+kO=XK z0)3j41Gf&`D>`+&AFsTKBUO_9UDDorKO#X)>1TY|1yF_1;0tq5QzHrRcqeH4duv~i zPut|LDkauygqUv)sK_5bUw+p;T!Dh)2dhTTqs3W?c|b%`^BsrxgPAE4C6ufI+m}tC zgrH>IOXQNXW4_|NaL2o1TfXi5+YUGfCK z*ct+MtWkAR0V!Qd+4nN(dU(*e$!Nlh{#s;Pf+H4dXS+Zf?$cWdi{OVR{EYd$JPePP zBjzOAg((bfJnaP_V#1V$PDUDTi6(?%KMjYYT#(OOEh+=FY;Y%x6#vg|f&D0@0QizHe<(oe+iPaff9z6QK{^1D2YK${v$95B17D>s2=vNDmE9jGv*|7IZe za$(gtdU3LlWgT^Mj%AGW1I$KqNAOu=Vd1pjl`6#W$}wuP0>3KoF!Na4V7CC?LP$lZJjb`W6Jk`743+GB3k*}-Kbw_{EL&+A->V5`$+jNF|%%r{`Nc{4_?XNi!Oh_Lm>&kKYB~ZiIdufEHjJ)@snzslN&&_4@4a6OwEYS z-#OfEabA29zn{g>?K2PZ}LH&LHQGjZEy~_Mv7b*;%A*L&L`mMPt6eufc8Gy zurS4fOOD5`*D$w$*rh#zpOGxF6@4(SOf1RA3kF|fsjd5{r+u!FJSDNzjzY+;H-T=w zXXwVsTkVPbT`wiwILOMf-ZU2W`>=D`>pGKKkXFXtyFUTB0d7YOW5Yv<+*?z!LAI<1TqTnXI$WbRewPUP>@mN^D=01ob(`Eq!JjX8x*R|7f- zs~L9L;(v}u#0oTU2;zn5NBKd1Xhip+$QH;KR{W2g3;Bx8RTDBohYyK$Z=z*i8WD&D z5A?VOL-1?6@b#D+>!o=q!5E+dVa?v3sWj=Fr$Uf?v?ok4dXqmKy}ZblvZJ=~isRHv zL(QibT9c+K0dQ<6a=?M2qo>LWQ#VHQXs0P=6FaOG2*a{)en+l@EwhYCN$evw9LyH% zPzA5<@kit`TR>Cupg;a+miVy9-v+HlOgDzWF5_h|-TvR z#CwT#0PZWw)(2SDU`OT70u?Sm@%nd%jS;!Az^gg_Lo{nF$2-y#5g{d=PqpJ)sDG7b z1zeWH>F!EB;Eaocqew-+21^T2(5Ih9o&M1Xh|To&eA-z@q*0Hpqd<2bc-i#+TLJ-k z6-sSDk+2h&AQanWkgU)*&!sJ0ru{#D2ZrEcny=0s(hiv))lCjE(kU_yO8*ePwNiq8 za@=0sqki#ihoBVD;5Q&uYww$|+L1~kg-zET`#{`POH zy9&u))Gwb7vJTa)F?JRGvINQdFQPX2O>?-RvB?Y0Py7O~jT+?SrHFa7L6qovE(eCa zPa>qvxTboR8oC8d-q<=N5PEoW!c!@r#U2h^ zN5>z|Tx6x6E%J)x5|=*e6(?mEFx(w6>lw${YE6wkcq95H;@{8%;U{8t$yI(zj>EqI zIM&uaO>~GDT7b#)AY0dEd+2W<89J3?1m)-rcIO8rO(cPL2Rpe6o%A`7&_(^s)@I*^ z2w**WUM*4QNxDhAVWOymtyhup%NXW8Q5glo$L~i3ikYr=c3g&MnJM_9uy!YHM*dSe zMoq2QoCcmy!kGE1r4_HN7!Ae zu9~*2>;%JdnN9)bMk&^lZqqbwN29wT(s+)UC%Ntmsv{5wCbq}(AAlUg!xLn1-R^&g z=tmPPT**;A`EoZ%Z~uoc!sPOxUH3>|UbQSa)8@LQOlDlieAul+GareB2;=Cp#h za@3h6b+Oq)=0pHA;`iE8(!qS#B_dzX4k`IGrNm2wIy&t>T~P>aIPWbb7Z|ar*FMos z^_VLCu)E^Wt_u#Fi_L9+(x$&-ANn?xdbah&enpgxzrZbSvF>rN+nia|scg?Xwomtb zxj%5X7VgZ>{nn_%H3m%MgNA?nF?7>7W}JvwG-l80V$onny^2$)cnAIx)b^S$k6DeR z-+R*61co?`YTD2pY55u_$Or_w{r23v+Ti{};N7xx>Tr7)L>Ujtykqf*#F!o#{bj)He~lo` zC=9lJ-_e5mM6!wJcw}X!8>%!%rB{W&x&N5Z^v*Rh7O|WPF!zZEd5D*Cb+=~TXzOsC z{78=Zi|!U(R-gQ10*j#k>#Nuf>-89=c!RUSd=9CWM!Ct8;{8^!V7|y)P397tBjYua z@>cQv#Cdv z{ckxn+hdsmF=@uzBkZN=?oIR1gJT~5UX4%IYp^H&Uij zGm$^vinWXIAZ315Y_z+AKrUFd?uu+hdj{K&IeNo&<9)gA`4&-~>s42R0fN zzMKpn12X4fJt2`C*|x?X%o}AH;?o%D`KX4okKBzHsK}I&*O%L@O*T>Vn~m>W&m?9d zT<=5>-5AL5K>N2A-ZbJfA6rg7Q7_j25AwWjo8J$wW6*@LQwB|a z7m7Q94H3WR+O9#NU6{b5z&s=(5(yk(8fAM;yk~ zbOG?I02vq0f*UYm1c|r2zJ=2*X!sqcT4no#Dz*CG)J&Fm3j@v1F-tt(sxcr&GVmLg zK*)Sua$a~_ZW`bjXkwrX3#TpnNz8b%e(N@LVGIhA-3toYxkmNl>77C0m_5ozfHW?edlJk*mXpT+!Ut_7)ySL4Zk-P?nlZd0fN6yH9 zqBfD|o^4>APLQCdA`kVRR-w3yWs*W4?RjuMV=19OVVaid(DK%C z`P0V*_*;T>U*zX(9H;RG22C&0@+ZM$zg8SMYyEgOAp7S~dOxV&oGi{C067DEvZpWb zg(9Pa1q6gytdV#e{J(@l2wf>Q8IvEs?;K~uErwLbFp!e%-x3&&&9M9@!l$nT9a!wD z!NyAdC-$628rNNZ79d&bKQ`0BCzSZ_8^G%#U!3=SWWg#6SXx;!Inv9IqFUT|1+CgG zwFIDXwIJ>BmPXg*A}`?}M#-jb(4)bCwbSPH_(z38pgR&4%+s^zDgRKAj;@nDtfgqq z9BBLnJPNe+#F+jes-B)WnV9AbA9Au(b6s2?2}89@lG?eVrYIxue^vmM!u%6H*!SdIhAun?Q}KEUnMWlcm>NRp<&z$42Ka%0cSILx{$#vIF7Sg8fmlkcFje@ts0W^ zW?Lyjj0Lraco+1NB|36zK3YKQfQ#4_p2ZtZ>&{u@`RI)VF@8b{qDieX7>hMOLM&ZN zu5&JQC`AIa!4$@xp;84LwsT4oQT2k(rpn2r%T%+(!GSr(x~ho^tu8qBM*#CCdzE{m zaebmtN1Yn3cMA>#TC_|!U4pIJPQo|S_l@Hd8NVtoJ}W&B*6?KgPc|9iiW&`zU=O*i zxml}`n8;TsiF;{Tk0MR7xkRg=EM9iHu3@E_BC?{d677KYc@^yll&-bt@yoe6o6os1 zA3!iQHCX2mA@6NzcTV>*U+td&hkWT@?$_+sQdFnX2J<1zkzZuuB5HDFNf&7DT2}kQ z=@eUcfq!lL!8@?Z2#8Hgshx{DMB;C>FarQ%gSLxv{l&_hB}xN#PBOCYH2B-o%Sb;u zOH3}TUTNpe2HDjk4|AEhIigdCf%S%2%H=v<-|^VbTdKy0fn0o{*t)tz+dUH8D9smh z_5qo(o&RVy`=+M*rq-IdxFMxvw<^EapK=sDo@E+Gaf&xeSwYW1v%# zsIVex`b#DpYDThwxDU8|+_ySxE)_kD6fh-CRjyPMyQ55$Yl8PW9i}5YaZC@`t?8%y z5LGBg)`P{Es2-S_RgP&UEFi!vGgOB@4+l1N&f)KWi9wzCW_p7R!tgLjaDKh*Hbrx8 ztBf>Mm^}p7%OLgo?h3F4%L_Pdt86hK0^r5xMCY($#129exdA19&}^5P zItdB7<4H7QBgzs{aJb~KhJnO@5mG3ssbCH4II;K7J5$gAu*f31YTK?|CacE{d_o(& z5JCF!w#%DkY1eK)s${#|Ie#1Xzg!z;`v$q(4rL}U`U~>?uNb9|nJvw%Pa|=vI_+P4 zL>1X^N0zm$s4z7w_AA*oECDhT&R6PF!35j*3zUJCzsZ}hqR*tv0SBc(em<~TUx7D; zTcrnk&CGnv=!Bon0-p6wRa<)kBmmzwABY7lhw_G=C;GmJ=z#Oxgm1Z6#MFuoh_~P|C$D&9%hpn zygdNg1}4dd-H);^9zHw$?(f2k!h=x}e{w=$z{>cz^s(~Z=DaF*lET4M!v#uiGJ=`} zqG*0*f%l6KVcc%lYrzm_HX#+Y|BYKbdcLaGwb(j-mz0D6a_{f}Nfc$Kj@5)nUC2m^ zAH;w@NlD~*vEW-YW^%?xagD>9b7Oqec3{q1UAz77N}4bm%?(WCP@D)4EP8^_m1wc) zoo;ade=1Mt2OMkx$q4?cX_PKqsyk*MZX`p^lAj8#r@)U)^g~@#|M;+bO&PLTCN8Dx zX@C$zm}U{O8Pqi+E*?>a_@NWh1j;Ui*zRf>(&?`79euQ8JE;q>Ce;uyr|gyv_J*>l z0wpf^+6vmil{VN%G6~;*aoW2S^Gb8QY*uumbj{}9B=4@TdsZm){Yn{^NDOG*GwBC; znfYtK3)UuJ-gR0;_0GrdtTGk}68QG`lx=#ETjO-A(@NPMP#eMY2;`4?+)~nBs!YMD z(gwJ?x1dM%DoJ>56=E*Gkp!%ByFo6LMPc<3Ts;3gSbG?MHxzmq3>=gHH> z^{v`fmH#LoFILn+pOm~W)j#5UH2^Nkq2&AIS|^T`l!}H`nqZ193@9woK`giiGU1H1 zhOa{E1Q2fxYsYLX9$7N*+0BEnoBHvS;T$&ypBfnvQ=X-4eY9V}9{eO21wB>RMJpG* z0QPLhqYEd)P;)C)QgNJNMH{{Cm5QrQ7;WfW za!+@$(}Ul|sK8XG06{>$zt$ac3Uw+0#iRcm%u77>1YuvhLw5?z-kifp!cV?;#JWZ{ zV)#CVE3fzDHc}zcvzKbYkVLNrD)E!?I{k%2u+yATYeWm9cGeJ{*zjzc`CbohQ zJv1c~ONE0428qeFzb4Wpl>kn2`2L1YK;g)C!%t1Mo7h-jmZy|GEc4V8lo~dnt#j2? z%~INcjZ_8=K2IMZ{lGE3I|`oBbI8RE)>=Sz{>oRrqpM z0~b3tJ1R$MOvM1x1q|OM@MR=N?l+l8s%&92w|o&ySTM8Y3Luzz$ysWHEk2E4y{T>1 zX0(@S)Ag}-CjofsIfWg9O!{5YmGmQKg{&&X4Chqi`#8Yu&MN)q#(6$0pNS93(8uA- z07ZN7M$ab-I4=8xmRX<{n0sD2_ccl1R(wwzu=WB#^u@B-#KVf zE=)L^iFPFpQnyYk=6o0!`E<7Z;=E#yzJ_fX7 z9Ax+s2XMTgpLH+DXLKe`S~$0OzDosLhO>gg&?~*)A|sT5yFn;A`Ww6kc-p*gdl6hJ zla&88JBAQ+N4y&JKh!9Z#L|7C(|;XUO3Qb7YO1_Z!bdrHD#dyY1D+<1m8w}|tb0{L zc9Bn)))v^v@{VS zRRN)K94X!(BBs7%Z4RyY9N#}Zv=a5?{lzyT(*^<>XL8D7+Mm0>pqd0EH~+@~7l-{K z1T37ncK+DWo&~r~PnV_suz+)T^fY-)XT+PEx%_9)Pw-NiqYOL3SKTI3?2C(+U)n@> zmEIR%{s({_TfO5TWAF$%KZsIZ6#Rr4a|b&U9}Rg@gcf!LQ(Gz(u(9!u?X`O=S)D)@ zv`PEK+0RPoIS~x3=KZ+RfWm4Hfricvq4Z;@wL5%7AydKG6o?eoZYCumPFK0MUVMiT z4mA9kFEn>Kpog9>Hf?7BVepYpwB51kLuUdNy*NSx4d_@#t&v4KV}>sHw90SoDZ_8i z)-B-V(ZVK|V5-lWaYjLVakc&H(WcY&a)nr2W@~q#ZQ+id+5Ng=G&Mv@!gM3XFAEi# zC}2(R9^E_)W?>@UKq*$rS=isL27F-5d?NKsA0nopABzLrb(>2~ zCd@{kJb%nAA8Rim| z^}rORZrA>^Xg4BQ_ib_?^Iy4j_7`3E9fx#6$7aSN0 zkxE?}c{vGChP~b^o#eELXb$a9;%;KO(9lGunqEvVwrTIcbewt~VnW4WIh)MnDxia+*l0X*JSPJ4bL(?HXx6XR*%!Ws1$umq zk3EfP!z8mKB<@bQn?M6wmUA|DcW^6G>a{BfvgOY6C+E`vDNRG30Ln>v*6B^YgJ~ej zc&MzqH6nq|dP|13LJC0KcDq5sv4N-1t0ec2>O#-U8GVyed#|BN2tBC^hPtu+SViICc^}a9E zn7w4Kojm+idH+Lx31==?0eqL zGnx6ha1cths|bB<9oUwpF~!aBr9x-;+oZsMEUKWZZlU3_i$*Q%n7B# z=Frwjz(c}gJuX|O6uj`vLH$9avmm2&7lkt72CMdG&Q^Sp|0Iz?QA8o^OvJg4-7tgD z&A{?QT*e~uoeuV7B8T{@1>MCf<~NV8<1=^+6V>@gXThz`=kjcRo%h0`0ODR)ogqAU z5AYh5(c$Bn#=+lVqY^wE3?TO}mqY-AuEsKrVY-SzKKsuOw$?x11jb5MULrKk@jb56U1D7cN^O__5l z@U=q6;-+ObabI&j0XuW<(9GkpUF8NtYCNV(z(#<^+lO}&Md7L}&lpKV52tr#0>pF) z)N-(~vwyFqCsa}9fjiRm5GWiDBHj>RtLl4jpj!*$xr7^4s9B+y0Vy>hv?ZJPQUES{ zhO8NM$1`XvD6K*aHO+(b<_kW@99SuOSv?}jb5}5}#z(_E`BZwUyzmdV`>n2o=-ZW? zdo;cF=wD0vb1@fb5B=ghR?5pw&mJlhDnnAlX9Dhw7;NeFSto4*`}LeLQv^U!>36U> zFpi@O_&>pe*5XHoo40vH< zu4PIoA$KXqIO4hTnx)1^i*JdYE;I!6&#KZDMc~@?ls|gHWePk4Q)2mTkCbx_8EDxf zTJ!fzJHpX=Miw;^^vU6eR+~JbhNG#lI?MSZt}L$A_aow_(8^zo0g^+KbC)wUliWn1 zQ%+x1LC9B!F84q)<$yF7xl*CsVVw zj2gXj9bCA6ele#OpP`Vo2@^BsY&=GT(Ao1k&q0r}39Z`N4fA!q@Zc0xy=^;`np}s# z;X(AJ8R`9|cO$@eLR4Ddg6kSHaW=5iVF`65htH)-vo0+FWb)+{!4q6;&>;t+{=VC& zot~!ucWO{An7%3H8i6M{$(=Ljn2t6uVRF#%TiSMMGfZ)dQ;SU|KdVm`=m(KC)Af*l zK^20T<5S!tDAO?69{)YNIC1p**~(q)dha3~kEZKFf))wp`M~eLQ`zPJ39( z1_)VUMqB3#W#F8h9~&pB+!TePzU^=}9SRQ2u`LB}b!ct9bD!ShmVZ|M zoDIp!fwD8?WNJJ!&W44tqXR02;&~;F+F|IEG@+GBa1_)^yV_VaT>%rcX)*-9YoF3* zhH977&TrqWDN?{G3>prsi4dvcJb}E2ZB{DM)WqB8g|P^VX$H6b2U$!Pm3;?5>>T9a zJ#W&n3gZ!b`Njy*`^O3i_jn=R`9SVlXqKtph+hPU|3d-%=dYHy98H&mRDf|`SRwcD zUCl%?^fQ?V8br=mQdML1b`t(&WR4D?;|uZrRSYOy+1MA&HJ3wStD?JFLa~xV){8a0 zIN=@)P#)(8&f58J>s;a2g~@&an~_2*Eh@5Y4!%mIJPhTBx8M(!TntL)Po0(o5Lv4z z17R3->OH7uL(p*`)oUy=#N&EQel?1@png|!ysbN*){HI&6ZzLt+p!49WW{xoC|E48 zMqR9E{pD|j4led!)Fz~PX41Yj4dr~sN#NNUOe=@cl)(4$IgxzU4Ej1@6z@jmxZno2 z8XuslP|RZ4Sy1ZaDQlbqP?9cgd?wwrCW1)9d{{yOrPvAcm^51itvj->M~YpCVfAm+ zrct`#&2Qr;hv!PwNpa%!OJOP~aECSF3#mM!A;wI~IO;8=T)7vV;UtuKQe!EbwlBJH zw5GRw^R;5S4tI+iK@nxk?c~A)myrqKWbHhjb2hKVpIR15U&ko+SEL)2QG(KfHx-XZ zYEr^Bz~9IvlaHIHbP2Dr4(06ewvKFb&%<(|S!f7*{)X2T0P?clu?DWL4ggU2ZL>IW zspRv2u~I-9ZnwAi0Ftrb0Xe1jG>pd8ceA83&fnYEHeQIe92Jg;loBlpF(8X&`8YIp z0A8Fc`!6|Fk2WkXkWW%Y#E|)uN)d04$ckjlep2@v>dQAIsyS}e!)cIx;9=T!v8Z8I zqKpIxW3=tI0=YfSUicxA9&TL(G^5ExKe}(3oE@$4*+$F&5Q4tSgPcO2jh_>g|BoX-fLZL()uZ&ZvkLE-dO)y@L_;>ay;|6{b z+WYgK(%=s?i22%Nkl(*Ky`&?m&?W52&8g~t^uBsPZGEgh(WVZ2Z|-6nkDid&rugK5 zt-q7@^6NJTE8^*yG2@AzMlW!mSNPFs-XRVo@W`D=?=kOE4lYEB4Y{2ke22~)p@#Gu zrO2u?Ee4GL6Hidknj}m7?sRW2w&6y%Lwgizy2+?w`rdwhp}9R%OT@TLv)z;Zao2U0vrkf9%@q^4j(o`D5}Y-;u~<7*<}> z{9OJ~OrHuMwz>}Ju2o@0fqpNOFK{w>;T0)1+{w^0Y(nOQo~2+7*a)BkAD9FYT#+Ab zQ;`y9v;_CAhP;@8DKt>ycQy8134~8!&CHJo^QC{e3edy))SGatu&D0*Z+)FWHw|$~MwWruA+D zwH>=!$PaolRg1^!y;H=zE1Z^S-cASOz-m)k*x#10vn$IqlzBM_de}%)JCWxUl3|3* z>$VK-4$TVg{vkG1l*2~z%Z&|PrUv=oQShhvaBC$k0&gXmm8=;_F~;?x7!;2DAQo{w z7`k??kQzH{D_WF2HbM0Mc-DJNEeJqrj9h+3XYjC~s&K1Y-BjJxg#ODXYvW7t zeFh|d6Ro$#;|6+@SX~0Oe71gC5hWj9L3X9eqahWrsEDKz9-EOQYz?M>r(ATI=Yaq$ zlM7JczgE3LXQYy|@h^jZ%Wu%=+l8QjujWRaSXGqu&p$=^^C@ABvsTbtCDZb&L6@HZ12^ zt_lY#gXBHAIX&>LLv;b*YYERJElwKSW#oPbT?b$RXb@K;>EEn_5Dr6|w!p}Nv)RFs z@MZ7xU_jhW(E#1R(4NcP-T)o$3{S+hsFRPwl(Q!wC-1dmO*9 zAR8H;H*AtTSg>`69U`ECBqUZ`ej2O?$khdStyecG(-JhZy!PVp3URol(r z^)kYHSsBjRz?#gbqe=YkYM-=AWTqhZkGAoW)BIY1U}`cZ??W_GysR5HWMd7eJZw`| z??z)p{M@P3uOqjBA32ZPM{-h*h`5j!{bPmKTVhcy~Ki0yN_>d+LdL+5|}OMPGObpnY=qbe2Y%({47U(=4<@8|ug5=f{tD z>>E;Z^W_x*gb=C_>Z`OOcR3jc5Ot96Jdl4v(v6@0IXbaRTf*#*pgjUp zQgt}M)V?qkT>*?!f2ib7^#L9Xg?m6gSrg+%l@|L zzT-eHqJmZyNfWqE%9o)#={?<)>k_~evhB^Hrf5pvEBiZ`O3691@5oZQH6uJ!h@+(&J&~r zSz+2B9p#+)9+$bvV|$z}k(5GAz>l~I*Yg~R;syGk73~Snslx=&8Iy67oiX&rcx2qI zA4Y+OssciNHK==SVX|q0+9TUf<7HoJ!*#OOokJ(wO_AsLBCxJ*^yUb1yz(O1- zFQPBR^30$=_&(qaPwWlMlLK^|o+e?Ei|)flHU*F;mDM z=D6c)xl0k7e zw|*EX6AU`^v!aYSg~7G7tL=$le1P&cpiDBq<$@N&Q$92?TQ3v60Tsv?Kkmp7QPq-G z98O6b!QiMTPDG9k5vOvyfqtRV?F>O~qln(wDq4}J^j{}L?-;&~P1)Vi&liTotmY=L zjJ~a*uRS4rNy}g@Cqc()5Xsfxl-)22I!h3y35-`GE1(}76Je9Cc6QZAA@|Q^`WXi3 zuvvW@?X843C}AI8#lKby@S_F=y(d^GnW;-8`m2HBm2Fa7jr|IYb&O~m0EV8`9&ZN% zmXhMJfX?{a7kAz0!ie-lb!m~qSB)<>)2qZ^J*ekC;5Wh;lM;@CX^(>i2eh3U;gx)i zof1{%hKIq)G+>ye0VC!{nUIYqQp+q+t&WBQ%N*1MyuuTug9I$(WXK;x$tP#18XuQ{ zIjX~|sJ|yYUHIi6J+Q2zb+*J-pl&J1V=$!I5f{~^lv2DA7)lg7X}@OgP{XR3S`pT4 zB{C8CWCVPgxq;sjW3Y9*jNh>?x$t9AJE4_vRHaw0La%hYt}wV(O(L~9xIfd}S>XGt zdaQwY?TC{OzhiEp&1kQT#EYiLH?+;~vYa5H(vQNg%yAqMG{kjdp%tn;0vp`Tia>$~zTOBY6ns=Q%Co2!c>_ja5|RNV1*`c+O|R+TVnEwmOzkcAUowyX`Ml`tzRl{A?s-O zOW95bAzm7CL+I~j{snGPWpXET&`o`0x<#@4y|seOO@&})_m&952f@m zbL5M8R2TYbX``$Htjstkq)1iR&x?4Wt6B?$&!@0uS38O5P*@Z@0unB~_Sm!N3{665 zveVXQ83(6TKEQ38?+C`U(8Xn5dQlh+tKB zlFjm$${8Z;P+3UI9(~VMEOJu<2A#8G77&q~_Yy9bvA!v#TX!crr94?m$Ff9s>;gHjXAqD zK@unW%mxmeqaALWKa+ZjkAlAk_w=Ht&BhS%w92M|f!~svPHGPympAVQzDdxZ_E)tn zMC9R}O=0x{?^`RR0Lc&hyDMX{-r{9$W0Nems>3%$8fV^g-f$S;Mp-mKJ%D}%Xww+E z62AbMAiTz_?y0B@1-R6c<3SH2D|G-35#_((enUP@U@Cjk&Y&(;0F0|%}##~P%ci$u|%elYwZcfkHvhc zhTSPLASh_%2;mR%LaOPvcvutID%%mh#qG~%%`G@<=TV0-S6?9u#9eMnH;SNuQ!YG_ zJ;Sxf_pL^b*MPYOF+$W(=|Yb z8AY4(4u7D$HrA1q098xQ3eQgXnC|$XgOys%TmLGYcZwB%jX?hZlAQA(kq?p)H;As% zK-*=0psLGHvgDI@BN>rX-8k0!scE1)MnE0NsX4-Y7QabE}p3tFQ9X&JPbXsZ(M9n0$`$ zQf~Y-T0shVGJ2w&DN2-O%k@g*;=j#RCUp|QlSLeR4D{6PPI~N8cX1VvAAYP8&gzjS z%(ujTlX2?ZX>r5#cpgwxoq6Ju8#R7hj<{ZLDMs>Dn8u_KV|DRN9G_v`B95mvL%04TVxiSD49Hi z1HX@j9Kw>mhf0kEZdc2mirmJZrB^7;GD_mihb^>2psU;5a&dz0Jq6oU}WD|#^S~W*_!EMbm@S?!9(%~C@h9!Y<9n@t}`Q}Vp~W) z1{Z8#Zs;2>ytxJ<41i_9`PlFC2<3wJxoA`mlz8b4s<$sosaL-Ku>@7JdQ)yZX{Em; z-OoSWpE{;EWXY3TSaplRjx3~cW<9?jwDr{*_AuU5x=uF7oMsctN^`1bbs-aM;teia zLl~VisUzmY6YQ=$?+wrUrgKXV%=pLqg9o(6gIjh-uc%O0Neds^VyiD<@F&uqLsg zZvc)uGHm95Lo{%I_o$-Da_VV}0P>uWfXNUJh8`^B-wu_2aB`TQMy?-)y~34N#t7lC zr1039c_SPGw6)MbaBt-Wel%6?PD5E%uPN+$Q)8!FPQjchN!xIl=hdkK{4uQJMIfRp z1PV^iNP4Ln!@t&^EJ%-rc^U<%N(q)YPihk(b`;6CVCv#?j6M-X?#im{tGS^0ZZQG+ z<9<3pKXs}Z(C}H9I3Gs7YofbS?wKoq1oo#lEljbj>u+{4$H8oje(U(UgzFJz27R}wyq9+Z%R??$Qy_*>OQdmZY(EweIv!WhG?xb?zxQ5-)_Ezz0S zu~OhzY;ihn?T4I=7Jf66b#{}-l(N`0HI3O4>}H3+O0~#4GG;8v*IYm_LW?@C^N-Up z(GK|ov+>sWqbIpEB3y2HTbnZ5jbaJxiq)lqua)}SF(HD1$$|HT3r zF&K{mlL_J0UR3n)Wc>}I_VXcHs zl#6>a&O#n_g0Ot^BiB^{{RZ#yhzCBk#Mx|p6`*dg+k}|yAwF^^fn9T5eeZBFIXP11 zvFzKV@^=YWZrKu9W}g?Bcv?iz{Mq_;9cm(vSd`?qU{5<lwkf|I{bhaT&o6hqFR81KI)b^UHP?4I&g}#gK7r+cIY3tZrOSPi(iQ!9 zx7YR-tb4!fSaO`Xb4aF8RfEYoqG-R$6#|*Dq>gKYA25hbcJYJCfFprta3;jtWt(|T z(Cc**8sfi3<6-~qbU*3BD4xE&W&Rd&x2aaA)@bu~^1$#u0Bn%8)<^X2hWYRBv3r4i$b`z4*?ZtW^$Ehm!-M7XvD z!yOt>M#qSw%k z7xQMdO6@w`*PNP=0y-u*9T5hDJtIphK_x+FZEmR+K94QRj2Hi-r69df0QodXq3Lzp zwH3OUB&^9;aa#5C4Y75}sb&|^LKMdZoWKZx>&%_RD;CA+d}vZEwodlMV`p1Kn7{Ci zf;_&k8Y-AD5So0;oCJsAQs4-(P9V#v%c$Dv`YggVlJAe9guZQzvetVcLYr~@S%LK_ zt_8T2-%Llq`wc8D*I=G&LvYtn_C!0SocmWS@ZV~hysHlv4d7_aA$>@-bJi3AYg5YTXP8i**4YR@!YzcKb|S?Y6MA2W6lz~b8HH{vuC@nG+b(BJOrm%@Z9DtkG4_JFV+g%2HKg zqrsdReA3!wakv)QCrG~M@{Se^4elIEL6rt%(Vtf2lcEG^WC+tQAKDeW5P3OMOe41X zBD^G-2~J%IY?47Qz~N}7lc}QoPWr06rp{ml?>Jvl&}ZZ5?^X){ox#c(*L}j+VgzQ7VRg| zg%#iuBjcRf`edJSF;6Wux_@68TcX3o0_+ zF8E=PU?-3$gHz7IWtp`0M2GhBKIz-C2{@TX?gD0t;VU}aY8)btVs^UF7Z5ET$840# zs@;y_`*qBpAw_iBwC~Tp$EcOwsPIWxetm-=>Bug(N+wE^{`1RB71LD!_p%@D1qHt0 zy*fG!ii}fa(@bm24&93}a8nbiE2{`7YXr|`da1cmhJ(kK0un{zias&+0N%36D&*c9 zKn_5M5wBaegzZX25_szT6fI{+LU4+d`jf9-rWSO#Cg-R8 zzx+Wqtdpqw2H!MPHo4SONZ-MIs=IoVn9=3yP;+VZK|(*tI6tl^<$L z6?I+32LH*2CuPYoz^y3;c?+T8nGvBh+e?MoPRfJ2e`McApqgIvRy|XkBteWb3j5!k zj!gGLz1+r12Iq=wckvKHH?6Vy86QSV;gf8CQ22XLJx;}DfNi#XBQs_B0B(U*#wW9t z$xv{QHq*tqR6$H*c3b;Kg0WV;af*Bj!cOa72=1_K;SCGa>_&#bZ~z%kD){V*x~GpV zfovHGDTN{qi=u;Ai{CK+qAk)rft!C)5beEnRYs#`OzcAvti$_z*DzdhIv546?nw==ruixx+h=Qi zN!Pu-KhL3)3paCE$h0BNBiBQ!>&7=b@W^Fj?7nxHA>$%t-l(ne?C^}DOb6_)0kQy~ zXI-EI^aLA({Q0jd12O-4D?2pRkayK>y7y~Nc~Jk5GBYJ(c$1DX&Q4bsB@ouMRZRsS zQf;kkIr2)^PasP;OSa|Ng-KD*N}yw##L9HA@oo$BBqT#(qoj9e8Igu6_f$ImH!#Gs z`K>tbrU%)agRyA|DEoFJ?+sB?8;Qy)_vjdCkAq(dv+fXQIygUlkD?)!f61YhM5O!3 ze158ods6PH0ehYc0tL*q`j-@eNUdz!FG{w;@v(s9C!vnDx%A456Qr07 z>;k+y;d(R?p;--(TM&vF{|Uqw+FNb&8}4h@`MF|o!N2fxnPu01o$Pp^*9QXoyjtc( zO0qA@`;*xm`mM)fNLJi*c)%!SGe^}57g34Fw6=fQKq7kAE=UDwY=+;%I7||@=uwls zn1mZBbYt1=j&NLIK77L5Ny2t~mc_O9MrZ*0#EdQT)%OL-ZRp<<9E}P|s8J}GjVCEJ z-~=8>;6285A3bU8aPnc-Z)K0-bfx$50U{Cz9fToCo=N3o?Ff&e$LfRMTnsM91x;8I zK*h_sW7p?AFH1rYW>lNpPzZE?MY1Y6{`n<&%S3s9e&f z?yX|5nNdpfS!kcm6v^5MJD?hpaQxLgQ>F|+0+tVkb2Z=ZF9m*VV5&@Ew^+wvLL50w z&^^lQt{NAvbAVaC$8ob1%kbrV(eO-8#6(&-8H@e~slDk*<8Es#`H|)Hh$I}n)wwAX zS2q_xHSTqUjqX_P?|Z9C@!euiz2F#ttySWknxW8X1}CMlzTq9Ix$8Mui>wD3htp(* z!Jatq;apAqS=y;jY=2N_XaM{{mi=9MrvJcgPZh#AkHdS-7IaE&BI>fY#ep82MN#So z12+NJEGl_XiqJ509~LOT|DP}~h^^5@n_(+}5qo9o=x3M4IRNA#hQ7izrXWCqOQoqG zRMID)x4vU)Mz0q4D9Db4g{HvHiwwsCoAmpu6F9(U4TjhyVw^(*i?wU`CpEG!^-wx#wG~i!bjw$P)K-s8^2$%gJz> z7wc=V(V+Gm=p6z>j=@Ia*Q{`m9~C6S3<}cMeULf*bAA$;N8ZKz6f3c8I{_w(t>(iA zCqy~qo3*T!pV)OyJTV7s1uojQ_Y7-0WX{C1o-v#Mq=L*AktA6PjWL>6L{QS?17}9$ zb8$%>;+3cQay96GGK}IJh1;sWI%6BQJjGq=hOm8H$|yF40Z_7YPxf6W@EUR6v@xZp z2!2*cbRF5sn2by_#3Z#dqV(o!PD-z?FeI~!ewf*nn$b1}nI<0E zAjAT`rx=>*AyN^t1)P}|AfL|A64pfjw-VjOb?jEMXz=Wcy_m5F!I)tybIX-qopvw8 zarw|(L$xW*9R&o7x6gNz1g0zdnAhuCXixgZ49S4`{mS}B$1ZBfzBUY*&e+%!2hL0y z*UM`>+6-qQWUKc-;VU%NQ*pcVe^jo~@;wDC2X}2pQs&_P!RpY8Bug@}5$fU&W~5cLt+0*fWuu5c5A7!8l=6_? zYkZ3@xLxp<#hgaUy7R>fZTOYtqDw^eRCFVA&;z&H&Mg#6gfSj8$UcNArTOZ#lL((D zuk!EU59j7{q`1t_@PaNJ=Bjm+;9Y{ce`X+Xd`k4JUP&R)62GjxLbt zCA7t`9m+Me4$Eh!BfX)mvh?D0B9@w-M&w1E3?Ipa=VQLS|4=6069qMdZGDG}rId(_ z9Ci~&glF}WYm{j%KpAniuTC5D9fb9OAD2QM{Ok%sNGH%ub2C=z@v`oIR^RjAiv#9v zR;gS8L!1m)#KhuWMG(Z2VF7R97t>D<6bc#68sZYoyIP(8LpmIf+@2Ni@nqs$D_lJ{ zH&LQjLx`zjtgwlYDd+lP|Gr3~b!D27A>c$$89??*5)P9;`2+$`+_M%o$<|(GZOM|k z!qnP+_6HlZSBA?-FZ-i{DFYSvXKI6DIHI|sbV@gN3ke_&tBVDUKHQQB;>SU9cuhN z{dx@zY1I#5?ixoxAFvTKg7X|1OpL-uZ(Ps~H*i(Gv{4N7DNR?m8ra zlfbNL)u)g0n3Z%veEv*j2#|~b>T?s85lO)VP(%B=VVtQWvr^NGiJxt;#!2V zq9Ag^E^s5pD{@a3JePd+XKHxu?=7-~^$L|CCd#kC*(#45Y*;A!D?SV0L8GiLbRQ^> ztXzJl7v-y*j>`+mRt775G)hRhq?oWoR6uwGJWa4L7 zzSM#BMAB?+Lm*O0k94PZec8yxyI&~{IJrh-&X7@L+=LY$w5$d?#xVk$7O$o~Ju-j1 zXG!M=J-}I8H7XyLF}g)V)?(S{V1Gc3ssbN~?qN(-!POibreWSs_3c#kmXU{tp&gpK zs~77}<_Y!ocFtCd>s1mqh^5+$0BXEx5HUWa6>e~&oko^sJ~0lyWEUPXCKrKSJ-Mr8#hj0^#mxSmrGQBoA zQ3&O1Z+wS~{p_~_^$et5iXqrgf-N`jLw!zNj66o@JRVnD#8Xvr!l{_H^ZPa1sq^qbfYI7_(!Ki}(6e|tqA*eg6A8mLQpwm!g%2_dKMtx0DY?Q! zW)>FIg0vK~Qb=mB{H!wJufP%RL ztfAh<6wE6a1&kc8jv~jO#Bjtrer~Etp@I?f&#~)NR37;4Y}{ta(MN|ilr9URIZMy7 z8v1ftH=JiJ0hw;yK)-B~z)*WPDgD*pWj*l6%Ic*sri3@w>EWy3TY%c^!*z8Sm@|5r z7E^{ZutA?nt*8e}B;0_H*K!3S{*7y-?RJ%6SSYxD!cb*5)fA_8kPoHt`n^kN1#E1i zq0lQDy1kLtmiTc~+abrbV1pL#@Po!MyPaZ8vrI@T$bMF%@9)%ZeRLjIp_0&ZA&4&e zTq|0pxOeeTWFN1H8a|`Oh2#i902w~4zDgc!^sJrato_6QJQ$)l9-tdMG7-7G+hkai z0#P(HU@Ts`U(Qs+2qrRk`S5I*6h=a4xsGYztg0=u9Sk!IYlwJz z96-F79i-#L&uGx@PsMa0lRmU=A~hZkDI1`$;JneY(HH2675FiMB8}tMou35t#f;At zGFPS-F@XcQQDDV%jygV;@UuTTt5$--h9A=+bt*bXAW#__Fq}D4lLA~0b1OV)gu{HU zaqH+OaI>vXgG2+m^+P627cD@B;L9eKzQjl<&G%UE?$P-Y5uD+gm!W5$SdIKU-zWYK zOGaw;DRgcEC0jw{OKx}~er$ZXr;>;-yH1d$EspWMg8k{>D3h!{d(0oVp@b6vl(X6~ zF?<1Yy;{Jh-E-&qmg$Yd;w5X)2;xoSG3GsZ=#)Q_>w4L?5Dah88rME}))D~)3jAYa2FzAO>9xN+I}t7?!;k4`53#YCXK9__&fj$`5`nkZ-XF)&)@ zCwj{Z9?NJMJJuSOi8-%1$Jg-{1(cdBIA&W=^4DZWtN=U}>*kr_=qk+foOn)9EY6iY zK+W7ZUpcqXrpUy9Wjaa${>kz3FP9dO9pc(cVI!ttr97jhN}W;A1y7v|yn{VBr0D;M zn2H-^amS!_gwtdHJQKCF*4U!E+AKRVkZiJS%IYj#q^gbkb<~Kd*Mj)@e^fd5)OJb& zYC8(+7@R}S%(KGPs0MXiMq_xsv5jEG-D+cg@G?{=D5=BgQ65|or%q#aX4o>FrgTv% zt37dzh>^^;22_jV&srA@Q{`6KTQFA7)C&@BdR`KuC;GZh>RP31;RElS=nCez-t}E5 z4jAfTg8Cb(`}hX62KMPvUbzH+|C)rn?GwT#RxO=^F$^Pm5z=Dfdi6^6TpJ>VX{^kb z&f!Kk)p6pQdoXXDi=uU~c&g>F)eOZ+3{uHM#_&Cn&JV>!hJG&qWd$W>4{@4FXG-n4^gQ3F&Ox6lqVOpdxF1R8BVBo}X2bOP!4>Xo)-$ z$-6Vs-^*Kw(=#VT)un7c8k8}5duh6!N7WZY>m(VH!3QP!pNNA|;06M@%Tj$8tNIvJ zn({uyhX8XKbtWI2JdWH!L@q8v`3uw*%Lx^b!v${;-Gwj|g>usAJ>%p|o3I?|hPlTc z6cLEol<@DhWYWoU3m5^}8+N!3mOaB3x!Gkavc0%-aF&sXqWl-xlqSDB!}tspVe|nc zVd)Gk%Ss2a+__!p{--FLEmL>F0N>gd`_J&dQ_)l_t3T45>B$e8KE1v8 zP4|){vLpmp^d%ud(qAX$cl>KR7wNE~T#bc1N9FfQVX$6)3C!y68P62JH*St-yxfEq z@y$_)3qJ!DZsGyaIB6gm#(YUVoC8fW*>Er{RqhoT5oDO#HL3#OtOFjBa5Pa9vFn4g{C2VKi@W)rvBGBpp4IhJ@d zhNkBh3BM?mzqM~wLQy&)EC~N3`niWFAwvd%tCztZg}dciCh4lO|NrYjDK$4t>ya?9 zC|812`U4_Kk2rbXjwqSQ8+MQb#f+W*yS&j;<@FEs;x_v|L=vsr{~bgQr%oSZ9~vEm`TTSB%#Q3){K-fQU5 z1!Ej49Av@ZoN-PJEKn#R<+I9*dh#;`S(aLxos)7LM(K306R9imn>Yr3^$MJY!YkEo zP=)pBM*l(f>4peh8g&z;!mVf(2o+v$BHn+`Mgv)x*ZjqI_En=ngYx{WXC>cva>gRl zP?juT6e z(YJkVO-$-biF%~Vf-qiqb`lgvH2vkzrqibtl_^}qj;8=aK)k=B&4j~#Djq~$rP>A< z!`JKy{eLw#sgZd6*3V&+IA4K*x(0FQ+q16a4qCqi?3kcEELWn-tJA;C96ZupbH!+j zImFZ>Fw2wR6-X(cY-|td@B%`fkfw=6vS|P5I>f~pOhpdhwKZGjp=tRwn8S3V=8_ z12u3dU(V(EKZzV8`417{e?16}ZrlCk=FSnp2`S+T`wjh}c-jDhg|c&J6F;@S1}ZcJ zj>4hjdd13U4Fj{Lta3lJr>dxfx^op|zFWb9OySyhJNMC7Tg%wOZ1}`96=PmM16tkG zNx#cl8&qCVaL+!gFXBL1i1Eymfb|c{NA@X~5%{E}i+p(2qBfRmChHtR2?$*}f$u2S zVO$yuMzMcIO-;^J)yBw`19{W!;KA(M5%{~p_c;X};_9)){TbuMP>PWp4Jf!>FF~*) zVm^?_O++@o$Ee*dN=h<-p;eJAA{r&}O)WlTl2hfyXs} z107SZvc@i0jV(jQj}#IShiS6wyDqP@72{rtPiZRDbK*@uhG-K-a_$}Dy7Jlxj@jK$ zk=rI?K*UBQbHSac0JHuqbB*frWhHuVe4MpfK}^Fr_ijg;wpxt?uB<29VeUe5_Dm+L9xJ+hMXG))=10O7d^&PaxiqHrO3m2!2t5UAcz5$e;^LHEmxGpk8k`~ zHrfKmzJY^sni1)vH^}pB`F*X?q)Cp$xJeieo!u*6F@5=Oup0l7q1mch4+GT5D?q>e zd#N%`(*?x^R9@lsGWDpDQr1RdRu@RU%njh}f8z(}=*A-2yDa7CuU#)uLB%*1#Cd0G z8q5Ezw(S^rDiNfc_$R&j{NP{rl3R{Cl0zE_E+Ut0Fkz1 z8HI-Wki638xPBuROj^LT6)NALf;6|OxpA|V6nl5}vI=M@fLAPDO5aiE>nEqtzq{TV2ZplU6_CjC- zUGj}y#Y8x4?G%hC$~6~&=VI4q(?+)>UK@-gilnNOm%cVW%Lj{w`7JlF2Y zJ~HtyCb8@8gyZ5rqirCZ3Lak@voHNnD)6mGA#5I4{6^}~06c$1`V29Nu!tsxeN8j* zdQh7BqFzp_bv4xDsOybYY&-L9N>Z4wN!m?lQ!53;ZLli)uqB%32JAwqpU~JA9ri;5 zvZe1txc(h>WjR>?Jim&@Cmn1Y5*Nzq9Wfg@*`Qlbb1p&{&=b~3EO3@xVH-%9%{XVr zO!#z8y=L*@0;efXKHqHm@lI10t1{Y{TzbOx-C$6x4V+1MdW$)w#Fk|L57a%AL@{gP_x{cT{nGsqAJtBukJ_T zd4s>zYTxH5gu3d@uDkJ!hdduWUw^9|B72Xs&GU~|x;cXi`_vl>p$IG$agwvh-QtrH z4eUw$imsT2kxpVIcjM}jh*Bd8sYZ=tsxYr* z#;nz0bdt9&VOm;>dB^TH5ZV4@va5Zc9UW*^ugQ-0CxD^$BZ0;8T{9ReWZ1p6Q1&4= z9cXN-Oy$z{>Gdor`EZWb3zr_$CD#-)!=ni%hN8HMR_h&DZFW^dRo3WCjh`9aqIIX^ zs`0&^30?Ij*()+$3CDvJ+|zoaY{2Cpg}g;)KZ)EUD;7hW?RwtFXJSBM48Hx#hDd0u z4)Mp%i4v?OODl;D0O5+E;ostCyKBZenIZ|H5O!2X{hn3Ry>ekHHSC5c_Rb#euP)<~ ze(o#Se6$AnC{wRwAXraXU-&WAzTO)-tr`^K=4kgg0wdoTA5!Xh9lbl@z$h&UPD`qZ zBASi+3LWt{^5ax4EcCN@O*vs6krH_ClR6yk;lsKQ9ckg#>MIh&$v5o;%OyL+5`0}sd4S;G zQy?P_X)1JL-pH-epw$4*r(N~_?js6ra@0IwwqP95a|)#b;LdntzfL!JWszy|h67T} z{p$ZTlsodqEfvcDX&$vJ{*s$uXx`*mhqI(M+01Zo0jT~{4odQfA#UGcqOcC6mrZ3O zsJRdkG1I9}S;u%awhWM0jTG{n!hcdl7_6rhytK@q^Nh64{&LlRql|!fRf3$zHk+I> z!x5cjcKCA3eTe%-ujk^`v64%d0ivh$%;mY2<-?N+J|zfTVFqDpmA7sjWEDaW2!Mij z6TRxBI+#k_x3(!kG%m|tIVcVE&|dDh6OHL4^dOw$~*x=$xO{DjyO>c;KSQ7;U$ zBu*7=V|vACF`-Oq*>e3fpg)RnmGA&Xd^;oOS94qQ) z7!1fvt+-CwpUDB9-m%$Y9TfmOJufJbV(MJKQ%7}=b=K7j)y~YkuJLY#%I#sM0uxc> z{g%aK397JKm*w^mf5~3Q6Y?^g#tq_cJ`eKRa+Z*=Z#n2%MOM3|IsD}MQ}nRTJy)7XaLU@PlGEEx%>1!Y9;A2Yjgj%^ zu%gHIAsp*uhyXZ-b*JI@J3c1`7K4_WTim}ZD`OAkxRIf$A7*sO#QKiri#Y0pF%tLT z3~B(>!wy{5)754+_|>>RsY;}!z={N7?yLlh_WqOC4vZ-UCaR9&06|x{(lu@37iRK3 z=M&wU>IjvM?;~UB3?-iiQvWK;<1I=mT!sX|WBKd+hr}KL$QZ z?qEL{S6CSJyx6Fj`-(n6tD?wuS_N%gOEiecJi^)Sb+&scaKv5jzg)6hb!=aW(F|SP z*}mfLG6p<|vWI*Aa6XhF(zp|UofUfl$tfB$S)RC9uG?$=6bM{)#WB05e zPSn_{&QSoIY$>)}gOc3ve_~UI1K51MiL~dW?3mq^Yr3JT^@PY_miUfMP@iPv{W6>J zp$e8)@Ry%6y?{@npRF_r42e9ie4{(kL-f@_)#OUVqcf%>9VwI`}^4yRJMp63 z2aWhLbmuQ5yH&2t&PHRy7OQdrJGyw`FC$o}tugRb(zXH7*Yl>LKB zzE_lvyWA|7Ui$j1fMeu%3rrK#?I9*E>H6<(#tG82W5{kK$i#a2C1j=Rq$-u&8RX4(EwH0DWZq?$N7+-m0K(%OrwNxs!J6SIx z;$WZGF@s&q712B=r{Izd+PW^oz?rWfXf=6IV7|IYZ~!JO>-+s;>v$7P&Fd zVu3E)_C8C@A+_&Vn&8OZ3|=dh{TTKIXUXWD-P8e<2`7%Cl-U3tG?_`Tc#e5N74biW}{Q?&8M z>%fX1aDM%XFh_RLD}5Iz(^C?ZA^kA_LkNr|;zHwH;@I?)EI~h*dpNBXC=vG$0dn-h z>Z8pt8v7$+!GO4G1@M^>~`+b?4rfmGrm)8xx$gEJkXiC!rHjxaCsFb?1@4BO0(30c_~q zn8#a9>mgbe*GG5 zzRRq>O=npPVO9(PPXBQING+boihts;#^D7ziab#5lWmbrs^Xwz)yzTTlC78%5B)@C zS2 zu4*}u^cXX8;HKhy@AqD;@D~qwexM#IJ=ka|*IZZa>CgJf%>uA+uv~1Nt<~&teAg4L zV@rb3MZ5=i070IqcJuW6n?cKXn_@$}|=VFyJ=#TQbmDEnUTu9UN0t!1te6|Jc3hEQ%|DTShpB$^lGkESZ$_&T`6Z#{C zGg_ez0raEiacMz#=Fhb1ccY==Sk2$gjfg$g{dXvm`cS9hWA>lNU((AT$1Xze4D*hT zCuYS@1bBnnq8sKA&p^a0TZ(;qMxT=lvVd7%(-N*2p<322PrBoA8=uMue7G{RN;%m0 z79dEwbbM!}a+0{xS?WM$lZ1T6bD{_xWh}uUbDy3PQ?I0<;paMbFITX`pL0y`hl*78 z&Z|vx1l9Uo0YZAG{G1w;YwdFGh(hYthd^U|_3!UJrRgaLQE7DTBUY8b;%Gcu(FnJZ zzI4)y5&ILbabgL3uH71S;u?;QbWbc&@PyG0*ZfXt`+BHJ-TOkcJ^teMwYFRgMnlDY2XhT))Hn(+!Y{EKSmKcP= zu6I+XscaM`;71wY36%9`8myh&CJS#Znzv;dk$=Ww+>`clx{tv@eqr}-NZcuK&xmKE z$njBu0TzTdXLwJH(flG5sPf!V2pzWVlkyRnYa<-k=bW>_qOm+K*uew`;je5BK9!uo zC}nmvbl8&RuJ=K;-R34No~*3OB6M}O5zH{S1Medx{8Pi!G?m46qKsC1UiLuXj$AK)5`X z5V|E8bRl=XAt}Y*6se~k)a|(4=A3e~(6>08-{3m*PM7i#00>c~Uh86k zx!g%PUQ;ZdObq+3g|IyvDi|D@W)9G7W@uyYMy3L}1U?PoLyM~jk7~$auqa}Wmz&F~ z%HnUuTB1}&1_nXn4I}yVW`o9h)uR9Mw{Btfol>F*Eyb{0KHz`!zQjFg8!&vxe-9cc zlE4=@L`~Qw52gnN^4k0Ri+)E7Xy0|a2AI++O=K>bJ?Qx`&8lnnocBj{- zGng*2W#MEcaBxkn0zS$QX2XrmEbpWmyVNg+jgzWj=b@YvdSO5)+{%$CZGhTE04Sd` z2aO+O+51x&=7h#gvkQrFUztGOzy*b;*^wY9AFC56#rNWsYavlvsO@&2;&Z%!`tpa~ zw=o{o-sce01PcvG<;0_IDY1v7hF7cuhJ!i-&EwYpCzBI-f-|wm=T&lu zrlc8xuJ^s@)Bi{ZitI7iwOTn?FWf~)+P94ZK_}m;oyi|Yp&~&oT_N&T+i^fJm*-d8 zQ&uUDdM3Fn5JYK}h(>L@S91@UyWVzsh6P0!Jtjss>Jxb-I;UD6dR)>bpw|WHwDqC_ zulC}$!M_rxCv3RCm}}7Tn%%2Cz;#_!^Wq`h8-aFz=8ATEXaRX3Roh|AlgyZF+0}{l z7ct>yAN?EVnrACA$0}p~HtW_LYnBFfIcEk)!HtJeO|*FV`y;{YViQanvSR>W+qHUN zE@Y+*ICZ)*l3V4r_x1q3#fD1U%#=}JX}Y2^ZYk#?p}Pe-Qz zGkdd-{Ope8{Aqrp*nUcuuivpLYWmu)0)tC3($ayA=QeJAlBKQG`||coS#ORZfsWnBj_(dJVR?f+@(y z*=j$}q|9MsKZIdRXT;^~UGN%op$du0unA&1V_-D#4qlc6`Jle%WRx`V>V1gTzE@%^ zulj2l1r1InCP>4M6w##PwExEi zZH4l(6wC=~vUIlBbq!h4jHru?M%n=x1S(i{AAh%Y*4qncC^|AJ$NffuDOtZ2*Z$B2 z`5cmqW!@%scHsm6!X7{9a#`xhl_>Caf&rAv{0i(q;~3dQVOazF1H2x7(!Mc2e{XYp z4g7e(Qgr#`bPK8xtRDF&i?L1#RRHTx@B{MoCzy#+so&XLGLYcY*m68Ktbcwr7X?Tu zn)_o!_3k1Xq1iK8-9>4$(k^R_Dhkw^+v&i@$1>d_Y$ArLh*}oy4zHNx3N=3q;_I$u zW|4%(w((egp`y`S2Iurtq&Z1LY^wAQ(6`o6&nb7p6A%3Bxt zWCUOsErqBG9F-Q%F9MgAfnI@Rz0Ar6Ph~u6ubg2XMwjs43Ae>hSUA5LTkT5*7iu7y zd!1Sl1fVVnPQ?5Ib~RYv+u5|JG-obbAjfpLUI9c51Nf}&-Gl~h7OAWG=e z4QiCLJuLvz{sX~_qqIaw*Pwx+kN_yzau;H8zupIMI;j<|k~I?ZiMT(0I*FXUdiZx} zeKj6mfGbzCT(qWnBsV0kMu8ax2|1!Hd8Uk(?-AbNVauehzx*`wVW11?%6QE8Vm9E- zHXPk-9rQnpJ_LJ*^fwMm+M~90oZ) z`u{C1Z)aA4kK#)QMYn74WPe=bO=_!@1DGqzF>b!!1Vx~_@K*w|T0N#}FfqOnVjqd& z=MNUSW92~v0=+~pkE59}&x*qOG%y-dS zQWtEHrbZfNX@L1OxJy<}kYgFdg#rEdZ9#<3cn$&I@TVO2E?xIVU?uUw%TvDPHnO}j z1);noxl_mh&e3820VH#O=1645Q+P_Jp4O4h$^$b^Xb9jGdExm(--VZVK0!M7b%7jb&L4l$`ZgUnD#5d@Ak1x~@D}WfH=?rDK^n8MbS^wki&q4NVBg357Aq z?5e&$QB>!_(xL2*Ke#0pRsJno;tjz)?k6#i3f}yR2VFc3?if}4T6IUDf~LhUIN>x7 znWga5p1cI%hD!CXM-Ns;=wT*^bNbxm;o1JceE19l;yDA| z&0zta=6yFdIPP+#*wL4lBHFu>C?ZzI*?uxV|HV5w z*VJOx#1W)aj{Ql1%#~8lgOR~7b1sdLO86QX9jBovcIF!^5oK}#e{O_G0ff_Tk+Op1 zZ_WM!Jaja&0_S*5$50%xluDza1L3jUfF?4eK`uk^IJy!MDdwH~5VOc(eFoo!*wklE zAa=8bxSg4lvs=?bTGB)WBd;(jET45TlHhd_u>J6D@C;MIEhYf3AA@GySiefRVD%4zZ=b{}G6lAk@ z0Z|dP9-%kaAALi(+gD^|Tnhs?myYgBS|o%cBiKPU)|+3(-M+@O z@6s6`AX&)Rc{CY-KWr71a`(NvgrSDKY&&e4c@X=ub*s*w$?BHEC&f=|BbKD&Ux88tp~JCs_cEhz4bY!0p+bc;02i25Y(P3dJ-0?p zcz;l}#~6eiVHv;E?L8FOf4b(4$iQOp3)rXVm3MJxsqfmBcQDey!sK2Cmdk30)ZRtI zf#NpMzwCz2oF?DgKNEu(qwn*qt?HCQ4zUn1skKI3Zx+-%!)W4IQr&>S;$7fil!iAZ z;$W$j5sNj)n|;9JoiJ$-C1cBzus%O5BH21AI^p@-$n5g{_DJe0ClkHo0?Vd3ySXXN zyK|1Y5mJ@w?J-{P45`L9E9Yaq%n`zq-~yMvymIe;gz?y;RohmRcq3lYP!&jj^Tr#= zd^Fs>4d28DMdaXgz3st_eekQlnYNoYNVTS<&CO}Bc-0~DK{X^dw;^ie79l$k^Oe~b zTjS6Gl9f%BW_c30UC}AD?^@v5KNL$)pJVXwwgmps%yOmk9*T;XYS|XWLQ9|O*a1Zc z4Ez~0FJcb;Wx}lSYG0^F?uYI+A#C`Cat#ZX$2q4ekp6iV} z*JI_=399Zm&-$A*KdwEbr}-0dZSx?(A{^0BgURCLUM*XUjwb7Z@MrM!S|rju^9O?z z$%N8zi#vSx)zgq)aNl+62rv`7apfHKO&g?fH#5)=85D_Gv2%X_PK>@#hOYI)GXbUG zFU^0W#KddKRyX~sHR!0|;Vl9Ig{7t$LiVb^1OU@U~&Y`Dj9xQgZA;%p|two^^adfXm6Tp7!p)EOSRi_?hpd!{#%TU z`2CrCRp9ZmbUAuc1(TY#`_5dtGTz)NMzNR7-vH4rq6*|+1Eo+?zm6E; zpl7#}bG0j3;KXsn;&dEZX=j0VNX?RngW~S@25s`giw!3iIK@0xKGbWo;}#)J0FwL! z*x|r2tNYvUH|CohGFc`}-EDjvODLy~)7Wi4kpS7Vm-?RnBlmx625+n}NSYq?qTo$P5|+o_ zArv-vfjZlq_s_;EnUr9b%c$kBlQrQHka~nr0WKYKi=4KI$XkPCZCk3xLvB7qm7)O% zXqwH(2IP&*+}fNV>-=+9!K^#i(pEA9m13UDDh_u;Bf7}-A;bLlUA(}XB?x}=zA17} zC_VO|HsX1|oFj=N453%UX2c`s3>3z=MA?e>s?3Jyrc3qGpOJ;^T${i#)j#V&QlX$f zn;K*7gC)${a41G`XY6h|L(97CpOX;LtF33Eh1eV^D*UAPnvUDvNe%b2E(Nj_Vy~+G z#}AMueN*i|9Wxh>ToF8EUn1g+N(uIG@=wQnR^dZUL{YT;@^k=wYqLQ46fCSsR;9dq zSa%JlJ5?0U7<@yUN$nJI5B$97q;C=oAgQ(pT2REwmh@_HwP4gy=#Ed+bC4CJf9(DQ zo0>bmr#uvS^%7>C)*(N57Z4?K^XipBJ?^lhtg*6?)3p#y-IwPZ{w!@BP#O!al>AY_ zhRE}%M0eY17N^Q}NiUR27(RLz3^;qw6S`xZ?^nxmBT6$Ge&YAY-HL|dJNyE;wS*r1 zppND@Ghg7pso(6}v#bM@4;UY`xJzsV)MEs1<+CX40eu0+znEaN+H3$>tP!vC;u~jF zk3UdNDq)?YiLgTP4Ijz0tx^#Jl#;)hkbaBhGA0$07)XoHk5bU+vQ{Fu`kt8BDVee) zN=Kv?qbZUxqoC7%>%xG5A|oZAg?x>w?-%kdO7Y>iPw4}1@E><0s6ZSb^(@2L?saPORD$SP2*8>st?VB=*S4e+9XbEQGgq=0 z9z@8`N)#QxPc7E=T!34IPi@n_e42TfqIDwu_?AhSa5s6VIT-I&u@IIO@omOyA~oA? zWU!T{_vjN+8v3PJ<&D+3qCn*xGdFoOa? zZ#BdShf`|B@LI4Ww;rJ3~67NPXhqD@Ilz3hsEK! zA8TIXf3h0*3IG67okqKdwI&#}WK;Oi9@P4@^hExsnr^6Uw#fevvE(gfBrL2(&xEUC zEx%)#zbZva>EfM(9~@Qx_Ep`^t#i=i^AiqZbN0HI_8wRh@)Jduy_Ww}bmif8?|1Ah zkwB>l_<0t233SBrS^>pcu=dK+gp5KFx?dmCbG2nI%`Ig$O_Nfp0PrZnIbq6T-*6`` z1C!H^DLm4)-pp94FClj`GsgfM zj?~DqH=_C~?c&PH*tHYulU-W^;C9yPGA=&Nv^2hD&$MjhUA>v_TQjCsV?2cmbs5|+ z_^Jj%N!O3Docmr?i?YF^^R1|Qj6?pJ$)iDNF7-JnuaUG=_LkzpnZ-U!y~|LUSBU|H z{5&OapK3+~aQ3hpU*}V*#?SHm0k0;^YT}6u^~I|t=7cd(mn_Q*z5~`WY^dz+6(PxE zd~B1Ln>6%Xm?Oa$gh=l0YoP0dq$ac z&0qS#+k~yY1xXqA8ZLPPFC{^%8E;)!a)^ryjksHO#AB30*42QbGBvC_ZaR?)RZ?@8 zlq~oIY}F}@reAH1xW=*N?_!VzN|coqa~~&1brT`v%?@B>lry)di)4HsbK<f3_7Lt0tILRqlbsC&?g%<`4P305H>w#9FUve)e;9v+R>s?~ zaoUv!iZj^nP#$zInglT4k?;mw2|~Eco*A#SGkNkvw!$S<>?1n+9c*V)GMW68y1XP% z|N4kqM6|EkSS)&QPVbXjIh%kmih_r2%ov3e|0bCkZx+Umq#$diw;u^c zsY01eEj-38j3I&8@iCIEPK?B!Do|AI$Id_WLOmrGyv_Kxj^rB_ZPHxM1lbXg_jZ)t zNfk>c&(A^6%_kND?fB5u& z7|&qu{L<2EmDo;Yum-F&EBdANe)jkkUWNhA`Wtt({(pL8f>!^#V0DGzGRyVWE+td2 z?aGA;2f-}&dc{3$jru|Q(e7@eT!IHNhnPl=-jbm;uW^rD_Wou=m%_GzbnSS-SrYCu zb_Ztj0z;0`#{3SpR#93uhkkf0IhUK%mo@eDKwI1bVseKOvKlHsY!pkiuJoR$?ScTR z@kVaB1O$`LllOz>jQx-bh1yrgz(?faj1)6#qP`P7{yA!V5IxNVTe3j28^iKm zPN>v>H1&LQnqBAibAT18uNn=7&%y@ZyXh*vBFjOl^x}g@dPa}uB&Qgasnw*_n3>IX zit@2VeM$LeaZpAxIVUmV59t2M;LZApJ(kUCFGt#NAjgEyx$m-|yTTucp)bwRvm7j_(n zfs(Lmd8k`NrNrxJf-d6S)RIM52M1l!)|KWWL)yT=_vjRTEp?wmNec*eNwauA z(74Ok=lG0!BXMxee=A?FB)s}6WsH46`BneN4;t^rL}n$FC=0#^$Af9ghH5fBNWdbj zIHdAznef)=Oft$N3Op>`v)==Zh9f+*`Nk0imBu*cjvrEj!+(>Foe{UrKyE63`q`1c z??+52pf}())RG2bn+v63084qrzBTV=^}*Jd2a(UGYX8xD>7)A4->hZLZi?`$Qn10U z{QE1(235Xv=M`lW21GSuO3>M#1|PlND8>tB6AwZ>laVDZrcbV)!t~pV%i#1OQC^yE?FjW)% zxM1@YDCm!hyNwslhtyJjb+^8;oMmf^3ues6$>4?sdGlM}-rB9cF8ig#YWDNMUH?#6 z;*gs2-VhTLk`tT(FRE+y;z*`=9mcqoRyeR->0kPz|+;z^%(q%LuON3ofs$4`|(On z_~)Jan?_1i*w)iYu@W25AX@_k?RkDJm=K5BzJnh|6@_{!Ge~N0f>hK&kCFy^Wr2LB zy`U=1yqPP3AVog*_lN;c4(HxjHaOFW{0i+6H9{)yCw8_LDFDh;JGVua`h+hwgarQ4 zeszR$-Q_RXEy?A$jCz?mb>|v_k|(vopS|jg+NCwjyk~yz@G^9A(?BDKvP;)M2}bPI zx3By=l8TmBrn>j=M3(*8L67B(b3i<^UYK{DY1cG8>GKy1{^k@0yvpbJRp&joIF za*-(d-Jo2!nie*}tPWe{6ZdcLO&-$S`_+c<$!W7n(n0bI`iw{h3s+5p=loLpuAxiC zx09;Q+MER&9xJ|PVONKQy_XpG(`MPQq*T>s9Kc6P&3Pfn-Z|4_pTez?2O(0R)F9+w zlf%SqHs?WMWfEE58{n06hebp)g=3;thtQJA zVnIj1?(Fw`heo8zy3h**BA3+acXe%zb#S=WaVbW+jk`Uw+(j7-Xly8;%RW2vn|ruz zL}^25NM6e|UFHV-;}E8dwd77re1^I-hEwcqsyei1LP~{Ht)4FF;9eV}Sd}}f)&mHD zuxEb+9AQKwY&Z6~B(&CG9-i|X(5O$e;(wSiIT_r|sv3KAMvNL-H1{>!PK$I$+-`z} ziZ>LK3rwy`CxT?>ls7z2>as1S=gO`C(=E>#yB3^o#x!hi5BX&)ik8p0o|ZBoiSi>3 zix#Mk8-vMk=>mqg#i;!$rdPTyM-ohb^zI)8Fq9pekZ}=S&nK<}6TX*f>V07f^K2TLNm91I>j$J-MX-z_srznP^}rq;eoo8e@ig?-^WCe+dyvM8rJv3v8ng&_ zRkhrex17fx>Hy-oa*}e3tZJ%=2H?VjnV&Fb6SLEad2;q*cKXJ# zLN!;$oPXi#=)!E)9N6bPW+g@C7xvDoXOW&Dmrd#DgZX^tQj4ygH1ldqS<&}Ej*W_Z znifgb-^W^U>P&oGe_+|XdE*x2}kH2ajt8%H_IYE^>OwP@(M2)C;xn`$q0fzVEv`74!hpkka{waU zVv;7IFU*6O|EAfE5l8AaoSlm%;+e<25=1K^Yo<;~|7G&!XlWO=SK{oDdcIdE*qLI- zJCnjcSCl6maZy08Rb`K$o2_C5a|&SFHQz-)IuA3#%#xfYgc1G6btW_=tewu1=)Pi*~827k{KgMV;c-UJ_yHBX+AdSH~+5 zPV$8^EKHr?fmU58vB+Wz9;9^e~G_`l+Tf1 z7d-696)8n4qTt;2h@VcFLk3Vu11|60C)a4#s!m1n^!8?hS{R}gj=|v_Kw+KmY*2Dc zVI)xK%U2ZhNoo7JcSM&=tLEepfeLP=>GjIZ$s9qyl~FitJxH~i(b_qTRy6l>ZJ;&o zr6mAX>Fh<8N=ZRtrI8&e&kV?z!bk;xx+ZSXUDQh+Ayq(&6an%F@b&ZnMG$GrN%H+Fl8V8ILo51Ou zwesVIqD@pO?XrkY4AG~;wZ_t)FABKVJSSaC(!-kw-dJ@4w^UTDo!v5y$wO5@;(|Wo zD*YEK1AxWV=)(P}ObXr~xaY&ySA{p2enev7fDm2DpdZI!<$ z!o;*(mE)neL}{Z`3ySL8ImP{;wr&ZQH9jrwJJYcH2mo145NkqH%t^EWi?PBl4i)iZ znC>e>M1yC-qvztubQO9zhX}u`W&VWgHEg{+05*{emH$bI=}kFEOEL@D2?d|Gk^b|4g7n>55nyW=bi2~j*yOrh0$}fff07HJ zeOP5YiZuFb>n6%D3}e3+(nE(&H%MLq4g(}LYlTro%dz*;C9w?|?=J@dVT3S}140kw z0RI`Cbl^Re2Y&-e=A7mVi2tNBD3I}lQv{FH3Z2zU62YS&Mrpqo%1oQzS`GiKV3`Z2 zktt|@t4F%0@EyBEpY)%kKtbK3Q9@cy@j5Z2e~bOC*lF5OD2&^0S7@7_)rIk{3qdY8 zyUTnxTav3n;V|P*lI5qahQ)B1cGr|Lt-U06Uz2sIqLP4pGV!FEb*;Y zf;6_!m$TDA+T7_^f{IFcBdO9dQlFZP0q<33z6O1;_v4^lx}Xv7))F1SY;I>Vb?r?r zXUg$}R60CYn+voB4$#$b!nGW$fhaCC#nAx{30iy4)e?>4bGaAK#!W2#ox^sJ%+j2` z_=`eb#|QL%ebj_BlzyJ`i}>Z{dKmx(W_^ z^x<9c1dQYK+TW^tC}iD6^X&`Syf@r4>41C86irzV)W4;Acsu=oW8T^&?Wmq+2;r;|8gNM-25|AVp5cQKS{*0Bo^xCn; zgBz3RBRz;Rpo-hw`GT8?K7|FoGmSh+0u|v?J+iIVOpAaxM)s+Y^))`zcp!EU2ThC)K`?*4^HJ=Gjoq9M{N?s=x3ms zsJe3+?8U-8?0Hqy%1XjdsDBDyY(JUsGKV&51%E&+AG+BHcYhTxt5@-Ld*5uwJtTTA ze^6bAQ!=(|`pfOs%vLLi z@>458i;|T$R>Irfv|g}V&JK^LXiw=&keG;mykEJ^*KbzXvgl0U?wVa0m%xD%3K}(> zDw%VKA$FCT)jz9creaP#KI0H8gTM{`w4Jp)ZrzMJW^=eG1yAU)wBJ944(iw)8T5MF^R-gY&V8*Q61$GBqT3V3F4`?)j5YU{4>%VeT+M5%n171kZdEKW1;6z!;rj z0by$|_l^T*aK30h&a+2_~F# z$5SpN-%2U(0vG@5!kND*>tRlzc7`6oKT9Ha)M6}WETl_{WL7;tS01SKkdB2u#x4zv z%@$!@2|`cJ1Z6^8mNgV?b94*<=~=d~kT5=Y=c~jd$qUEr`~O)3eehAD16^s53pff% zBfvLeX<#ELjJ@7`EikpFRirtJ?a}<6qn|}ZUQ{kRhX7`Q)w;&)r^-*o~2F+eVh z^oDzA=&a@=Tt5ZK6=+CuWXTVm`V{dAcdDAZdH5z}EE>C+g(I7I-zl~Ct;oYJV!$A5 z;n4!NB49RoGDr?zFU;?LHe5j7-_fE2Vc*~V7UxdX3E&T?3(WhNXueaVjL587R0rkn z_?2W|R(_7ts*~EMSrd}wICc4o>}H5FKjn26%bCeK11j&K=&{lAM%PV;pW z*vkCY9(f$yXbnTfre_U>hCY$%woy$A>|oirYrt<)*p%C5}Tbn zxr9lN@T9lYtF~?Z%%uIgBb!7AoI)QQaoxMD8tmCWglCiXNkSIP+-0!sXiR%T_!9T+5`;iF zbS=nS{dS~lO4%!5775@1RdE(8vM6bDg+R zLp%KxNpeW4+Of(Zgn>dHLCWq-tbu`}Xav1e{DGltZWb&AL2t89YYWdut8|WRgFO|1 zkd20!`Z00$f+s*Tu5$Tc{mf6=WTnO+w$*xcJVaWe}$c%uARG!B%XF)U3K* z3x71D5U39S;`5KQV`rXfb?*!R=HJHvMG+P7jm*YO$E%i4A~!*e)`@n}^8chz!@z4g zQAEOC+8y)WBMkb?`TRn@(DChAWYOq}OGnnSIC@w;0vGT}n0n85_zc2Yk4i^Oq3_6= zWq<~_5GnYl00vJYFNcMur3^woOoo&hbp91|K48x`uXBo#+t0O82b9gYm3hngN@qkH1AsjN9Psz?HIgqB}m%rg% zy8idRx1;uIlBeKBm>LpjH3Mm#+WStHQiA&ngWu%Imo2`6O+l)t-WB1{r^q@i+d z5y6%_B3sy6g07A02_{QaV_`|r8qHp^XhMt0eJ*B1^Xx>PzISweZ(hc}V2HJeP64i#UkHpAS>G6LX_)Jq)w zV!*ApW|dPW*W>@b%toF>Rs03u87uJAv(K~qluGNuR+#J@je{x`-A?e)78jl`%xg&W zI=mgAmh!^)1jjdI>LBmU7l&g({reVOZO#kBhF0ai8!5SQd6pe_>Fs}^Yap2#NZl|> zFx*2wRF27Dq06*iQ}^~F$*2N7syG8DI+A#yrk$eQE7ptu<|H^m_#14&6y~JtlA918 z&nd$EfurzDlL!Dg)+sb-G0dGjf@SNV+={? z0Kcp-2qw=iVp5z2pC!YU_hgJwx}2WqI+v?rt8ByeP+8k@Nd$VP{<)R^mDWKmr*Pwn zh{sX_^gT)GC3?=E5h0>vZwdT*%f!evQ%@ruJiiGwG)(bpXT_qBY2*j>4FFY_CV4~4 z_ak|pd#*Q-G3PHPGHBEw-&L!OBq4{jpf`ht%z~$d{0gA7;3#Qom}!81?gg|xw3%=t z;GW$qp^SK9(#c9d+S1$(7_aDYQBH7Aou@ZpdJU|G#{U6&>Gkp$+ zis0fu%6MS9IUR#gT6w*-|351}WsnSs-;n>WNCG6#`bK8dS#pJ5Ev- zf;i!01`_&Xkw_(LgTdfaM1FbEC5h7gz6^N)QV`v5aJd@YrN7nsKSP`s&&l8XBiBp? zpThkG{CYueoT0g|YIDTF?1+ME`9@tv#z2sSas}OJ7@ngu_tuRo%$Bk6oxF!mu8;7N z$SvVF5loKyRV+Xyc!h1dEei84el5D+H9|J;Y=SDSJy{G3a5!UV$d9`>;qgV8)8J6l zDW{~lfl1z>`>2Rsp)}^6VZpFAvO^S`B~g%0Qk@DtY_mwDM1fXh@rGmN-CfPnI*wrs zs5l|IrMz=o9D^bIPzbJM;^4S3=Qzy+pjhfH*m*ehcgzMGwF03fn4I*dN8_H_Q-OrU zHs}A^WVg?mMK06`OoHK0eC}hC^|&U9D#d((x<)}6Lif8Rl2vf{L*N?3ZTRzJ3$EJT zuTQLs`=PKa<9Ct5#MgYk5EU#TrseIVYiP4?bn5xp)Nq#ko}`X*Qg}KV$r77;h}!5S zv`AgwlRoyBt|#+84e>YI5p9B9UhDvyt?y--%vTCHxh2Gnp}S+Xwp>c)twSur2s_?% zsUOQF8;Y=AIWCuQNKUQL^@>nYXC4c(`!RBP1Wkqiw?!uV6mrHxP{?8jm9)Y6V^lz; z&!q^N^}s2bqL5}?%fxTnZ65?wYlaEBbo1Mtn})I@R}j};zhV}rBkj8t8%BTAt!LkT zEKIkg8;CP)zTPRiUoBSVELi6A_!*ACQ^0xej=xMW2A2t*SRr+Wy-&6EaTXgyd}MP= zcEd)gcMSzIVRf7z)t*M~uQq#z#8c~T`VJS&i3A3kVM0qf0w{8~VHx?8`vs0_p_tb7XT#2-_tl-Fr>cwK zBiaEh#z(X4-y}(Uy!nF9L#aD4n3(pCzutMWq`a&Ha~%6qtNKeJA}dpsT$c8~iGGHB zCr`29s6~ka>|W&%(@{^pNM{L-=!8}2xU!4Om7YO&2QjaO&4T zdM3!QnVZ#|7Z%a@XWzOiHII#lBLVu!0g>12Wqmz1C5cYgabZB?`KT+J3?#YT5;DC= zA>ZwW^GiFLhTuz_o=TN?RT@9I2p;Kc+z^&F_DH1$u4$1l5s(X(;Pp3cVIg$-uvv=# zLwKM=#`mO{s{69m(WpQ}tSaR|^x&X1Y@+Le+8#9*0TGwLDuY4Z1USTeeu7RmQN`kl z#Vrh@CAkK4u7x|&XG8TRgQ;u%fzCKj#1;e^Wvq!ySWlq_+6Ta%_IJ~FNvx+=t>icy z%$W2j;3E{W%?|PP?m5SSV7=vssS8&X+Fl>dgiO7`olvMLPGdMMDU4`Oe~>oU-Cd!w zx#n5ly|1N=n?U=FRB(%27>3=#CW3DmgUs-eP5Uj08-ACGcsis>O_^|{{1*As9!=Jz zt->&zwX5P~_8Ogk#xGhfjKTY`zJ`(TiG&m$3h7zJ^666_+W1t}i%B9q8a0+-6o>{2 zXRO62G=+x8R;*zL@5XzL+AC!QE1&5t(FMD!=rLNIe6)20LCs)aJb1F4rW&a~Qc?!( zl|k!-+^PGyJY*6@Q*9YGa-Cot`Ka*b9E^`m<7P7?Q0_ZFk`qnJ4;-O~ijl2Rgkw^9 z32gIm5ymz0dEuOb6;2?d_`L1C>~bOWU@P0<-2wmGj>5lesp*1bv&z(N;PBw-g?Fjm zpD7;$?Mc_HuqX|E5`i(jQZz8qD&FVa9Z)ylpb!0Wpt*nkH7kyh6NJI=x=lDN{%A%} zmA#bjANn-x6-HteQN(|1D`fn54P#q+@fmesS`5?k`g1|Q(+)5_mhm2XF5;|Eiu+%w z_91YFvK+C)4ufzN>jL9$N$_VY9-Ph6b`*T4;7`1BNA8ENXRyjU*b}0C0^`0$Jm6!y zdT(7;i(OGcje}KO8=k`eN`N7lhq6MMd|K5yhG=IVIUd~TMhE)TmX`HL;`btI#;e** zr8@G+Byfm+*`avy)_=_prbJp1z_mVg%(JA5FkhA~O2W}W-PbBXs&m9! z5@I^TDF$f!KUrEF+9DoJ&{}=$lBCHW%cOxl48NJZBY#l>p|}|pnbTsJ8V;=t{|Kq2 zJX}}rS$XkqO2a&qPncbB|AyRMtjVryM?hCsX!cj&HZ4^8neeJWs+pSs6uq9Me~zZ& z4}CU|iIu7~aFOqjxtDGGfqjt7zM_Mn7h$;n7LG!h!GM(qu*fhozdMKXo%L+-vTJlwvQ*0H1NChnBKEqLGPFLbtF)(+2W`n5gzaAegGH^#a@55!S&eCsE#6FCm*3 zoVZ8G2T%Bery@x|`s__(fRyx8zST z^Nn+k`KzX?lOTzF^ug*b*ss%>ar5wc%L-DD2t4*0ZqiK_qxfD9BHZ99G`AYJL%4`QMySg{$gqHZl|h0fIf?8 z&w7YvcfjeigA|+WX}};}3!TKV?LaJeNstd;3xJ~VLD_7j{PzBhwlwAcAZh+JcQ!wH zaYHv&w>tU-0lhiRH8Bt1+>-=f=S5Fh+xFasv#vfW&G;eIrL3opn#w(E@Wq(|Qa4@F zr?Gtxu*MOZSE_&?gHAyCM5Y@@mpVTgZ(gK`lhpZ%>#i)DxZ#2>%0~tZAG@|estZY7 z!5{(zOVk?x{E}8nVZ28s7x3h*54t}(>bXLiwwLs$<-pGokza{_(Ix+NhZ&hh*-W@P z_ySWK{9u^b2%=zgv!+au#=Y)i(WsWi zMxB_TgF&~hDqB)3(m%0f!`+H+DM!XIN!QC1G2cqldeL@hD%C3?Sn|1i9bn#~r>+Sa zSIe0%Q5WfHwnwb#7io4AA1~B!a11Cf9*>L^-&e--vN~Zj#o7*v6lAoZT|u*(aIWdqc(4RvJSTm&T8B1 z9(+E;@O;0$bzks;Exm?uD@M(N+Wxl8-1%bC#HFZ(7#a-M1uiEO>3>Hid_%R}z#C0l zLxLbp((SwUX5fS$Xeo^tw%1}wNB6hDG&UK8OA$6Zq8RFYSskpH2ZG=hu@Gs?a#RghUK98nV zGaS_&lbO>~$k#j2t!Sh2``pQ24sh5A4jDC?k_Ema@OGSSvoh_eAvIs=j0_s}{ z_oZ%TGF^dk5&N&N3+UVl&RtBr!j>2AM4reBZ{PbK8l~$_+jK3fol0Yh7JONUvYFM` z2ZfxXWS50JlAgcw71;PtNSwN*?=<~N;=iGW`V*evSOPwY7`M{tXu*y62CTpbt4@w$ zl$!=3!He_5It@K{zV`9cP9KIGocK-mtrfKR0anADQG4-LaFTPy^z!TWKr37mkEOMb zAor~*zuKG6$#Rg#k>=WV9nHQVH4?U{<(8RpgdQu?VBCCqXKIhXrc^3a(E+wL|6AcE zcst?G>Hzr46c`XVS91tQ*Z@|nUm0{8(Ow8$&l1RuiMgb)x<^#aDWFkcx}{rtjFBeq z0BFqyY2l@ehcJddl0jJNbO&tG8BPM@pJryyG{)6zgva+2Di7M5Rc&%)OcjN%d}%R_ z^GosgyJhy^4;~#kQT(Dnd5dntOP0?H*HJsOkzJ%>DcBhQ&+L zWhQBNjx%XYtz4wr8;O0tGKskQ&<%p)8cinR?b>`4vxEV#(2$zKz*5_uD$>%hk?`X!#dkNTh5buz0^1eTSEsS!mhUf%7u+j2At~?8=R4Q z_cW~Tt@JSz`KS{}$dWJ%%~wWuj3?af_`n?8-%2(wvnO60Ise)fO2D)~O+cu8Em3s^ zFUcsmw=Md7GS44%fCsWV58sWTEn*11%xKaq`8WO&K;2(u+o^!Mt)82vj=k~NMXBvj zAUF7UL4V_Y0n(18>co@;17)fcv}YJzf1)(JHZ(7vC1O`K30z0A``Iuk=z zgus*_=lC`lL0x$>x0w>JLHFZAmQZp)eN7Py!u92Nm8Suoc82mvlb=?rfe!c~ZvU0n zhZ;r2O;9hJtI`V``bBXZA(2)}4VCYB)|lIHd>+6#U-(Q{@7sW6XA|#d&k`$aJDKp0 z^XiHwYJP%7xR;hdG)=cubW@}lyQl=3ekXTlZ<7if`cPbqsRUW{pS^K=uqBk(4VpgP zANO3!yov|SSU&C}M`H1iBS?NU*HLCZ85cC5HP{$)WjLc+^(y9L1o3nz(fWK?|JJyz zg!W9{D4Ts<*3``O^otvC4(`)*p=`VW-w{RsjlF-m{(lpR+7yUH&U>7(QXd6P zY)?@Ykv`5#!>-+n#Czb=Y@in}&w)zDYjo#CJgXwEURuKALUZsjv6d<9S|$)s1LoLD z&(Aw>5i$SwaP0q@Kcf>3%{o>_J%?(wJ7hhTE2c0$psJpbR#bU5rOK$dgFlB*BI0`M z!OVRSWq`^5>~55`nXA&CT*zP|qM>5eabliy$;d4=6-jNUN+^upd{rN;5oCA9t+>k{ z$SG*KdJ^9yw(9{pnwa)aW6p>J0(T1s!a!e1FR1Ra1qqOr{-l3^DwCHQ!e(?3zB~St ziFkIXY1;aw8#9nck+xcUNu9WpFY8y$XM5jgEL#}AENL5zn&CMENtJ+#Iw|M5dIAe| z>xNC|$5k=^%M%vhx(tG+qsi}~rQmlzX8kpNS`cd<3%opHYlOOH-3BXe zirz3~JYoni1RioVP{6Y}9YZt|x@*8O_+4quLBOQ`e@&VBEcp+UqtZz>Q%*SLoM8u8 zBHaVlTA4n5yD>BF#re-xz*KyT_d0)g8%tsn)9XLFXK$#E{|E{9*$&1VT#jV`Ds8dC zGjV@g1Etw;ysl~;vx2b{RHGB7N?jq&Ee*7+tq8C;<9J=l!_!IEAMS;4p$tbVapfd! ze9z-A^sYm!hKrUQ95L-b1N;8UCzMWwasR>gn$;yUL?y1#XIZ~pwG3^xeU4?ZC` z^RL+H!RPoGiR0D>V5X`J`ALW+;LM(n{9M=+$H9xKBtyaf#E-Yan&@WZlr!8)eLh|hXackTfoUkbLdzFeP}TKe3>#C6xz*+~1?Dxs)}xMc z;XZkpNi+yVySl+kk=+`Ev!{hN4AoI!lJQ981S^lGx}0$>1%VHi!H;xb4&=%hlmC@N#=)*^m^ z-A{(Ygl|@8BfLi`PPL@{;2j=aU%lti#jT4FOM(h-HZqGGT_#n32FM>|sNL#IBj0J51{^%pkcTOk){mp0G?LYk%OMb;L$!P~-0pN^U!?^#TgqCbk%+ zn;sbhtMgTabgv?{2H<&i7b-F4ztT7mva9Scv6+kDjuMN1?_jnEKP$oWY{wAzHH-6{ zALDC4alU8c>5$kUJ;e%J-I0wy(Wv^$8fwb4%i^XQ;)axxa`}ZYm^4o2g$$I>Ln${v z7M~z|?o+tcsw-1{W~!-+p&hes@uGm z(<~iy?~aUv<)5WPKRZ|9uDje%>Jj}~0ug_!dM0QY)FEh}XIPD4&E8D=Mqq=Od92H) z2$7e`le7)JaQUCP#Ow^--3j_b0nJI>a88Y(H`D|{6YNa!xeF4p+CqDx+7hZ^&;)k1 zFE;j!zcTwprxR5t%pX_WJ@EF2mh!Y-zy{(ttDqyd&Bm$gw7q=5-!R4WfWU40ezw&5 z*j!;)C)Gcv?V=2j25qPGjCRCnF>ba%Lc`7yRUO;iK$15XA2iLRQCT3DbC_9jnqbNW zuw_jJ+R(=6&K>6{b#bf49IFrStic4OJ)1Xr&`r=KL)9;Qe#6&V~3UYOsZ*qK1N9nYqr}N<}MG$$f`xy zaMD~KV{CnOm8rAG%~U0;F5g#+{lx!LSVSo@^*rydQEyS6gn!A#6tOMK{S8y-U%-01)3{p|DnW8p$yGT{2WoDARx^YVul?C*K z4MWsz*>l$_?=uy1y`fgw!;%e(O0gQy@aR&;6U!%xq7PVvuE@MI2>6n6ia4F@pSRaK zzO_x#DlxNvqdxdfG92$`ww{w%HOU$@BAj!07p0$>VZ+cr*2O-dKjMW4ZHev+Tgw{# zh{SrIi<>MD4E5wV-|vU>R%yuRJtRE<#TtsMWG(omv+E%eFfU}J>a!)E4Po`$1%~x7 zEC61C_WKRAEmrtFmxdVEx-=IJuoXlDx!xFwlPcrN8H;xkBRcZtWP)HMK5Vz!3Z*g> z-173(Jp~|w0!k4_gkcz+7Mm!Z;VAGDB`z5{v{hi*U zT=)9?1guc47n3Wc95(k!v@TP4aAb$n?3Z_@;eT;d@sEC|nyDN=brWnkVX#fZvS#_=xRjXN&lq0?Zs{ z1y0Hvy~8uOUPNaKmzsVXz+bc;-zR1ShoZK6ii}C6dv-iR@y0=Szz&*MjOFyX79bRK z`=^=Sg!DI2M$V<%SK~C(D!;z@B-`oorS*}*e-@L<>Mr<0Je6<=lZ8NL2DePX(RLWA zeY0&s{{X;h{sSu!xWI6Dnvo39aAoG3g^DZ>^4gE2fh&iA2I1ShoI^pt?-7Q{Lk4)= zc<+Kc`0@bR1#;Qo&7vFtZC)LV6?cBEg-L`ZXOG5or?LIyoqTdhKKw*L5l z)DJeQ;fsgSTD>D(azak8FKwoCbfy67y13M z=eucZ$y;s;2UDOg0iVc1q_s&R=$uiDO~aD(+(=-}0h~goNIO>fD!z*CmPI%i=~}O( zgFXdP-K3QHXeUJugUDHX4oVHv_CTOj@_&7M;G6!DIt-5tNR#AIgs%WS?R=CbGjiVuKuat-G z+j0-=->-9*upiV$Vrryq4zhkH&|VyL@!gZHk%+Wvs zs{4h)eL%pm3+X|lUvMES$-;${1by>mxT0th>gw`Ev{uY}Ae@8XE`!h1sz&VPk#%+b zxWKtPSnMeQ?>Xc#bz?HM4tDdPCT$RiH$btc)~6zvf5ik;2JobTMkwSZj?Cm^mIrGv zX-(7x9@D{GMijX4!dZ9cCj)2iYHI#J17HA6F&Q@+luyiUi4)r!PWO^gMB~D8QDg z%xelpLH5(}5)FL2v?XyWO2_!flEu06A=0`Xk(Aed1-ovO996^mtv4VQ)CIq*b3Ec6 z;g(0Q>QNj~T#xUp9l!*gt1;iSe}zyv0QFsG8`c3faY$|Ui!gZ^jxNuqbqkGEGG5V;@%Lw1Y^GAyA0WC*GJYqxrX zYvTpx!{A^WYLiBhs7Y+#(>I8ma-`nV`1!9p9pVrHqQ~H6L8EZ~3;xuc0T1ykM9&3@A(uQS@=aUKowhzU_-e3env$ED#cBx%B5nJDK>t`OjG<64xJtdbB0G@I-I^*xhq~<4-lIsqB-L7-_fBB!D8`y(Ky7V?CrXH`Naqsrtcw5y)BPqK`%*LLI`Wf0lnk?v~_VnEgN@xPo{Si&K$y!qO~{*vv4GS z(GiJZObct!^X}@zQs|zb`(R!wJ{S?f~;6+4b$d1(LoM zz=K<7wdVyLW&UjTykm7YnXaQXn{T!or{{wje-44}^=c$nYPhn*OP>wkzEx?$RsH_m z-rNV1AJF4c(1IgR!(|3tmBB6b7Dt7njX_FZMv;H(%JY(iZfeHsUhfnw&F@u*1k>*T zVrr#gyUhKwP-^{H+e{TNotaAOrmO-YUVAfyFsDkt=5VshS6mKPa7ykLumqO3$+@cC zGM|K93q}ZBX_z`u3gn&T6U42#8Pa-%hE!pJ16GFp?l(fF()9B4WuljbBR&K>OD{So z8CiCvNDk_JZ9k0Q6`+7(@skTH-6KSqEGd~SjR_o=*kfac#3iGPXc-@$Mxv^Q+~f=G z6tI~V!Xd1wI_fz`af?IQ2W4^-0U?#Hgs5&9_5&ru2C{{sl4_wR%gO58EvzIX{9Hoe zclm(Gkldf%@~avzX)~V5j7QZYSAY}R?;IP6?K?An!}=^H>#A9OuaHnl)bNcY-%fY4 zY9#|lp!bRE7%>3|!Ym_&;v#t}wr6(c$2X226AoJ4UCAiEDX2N5W^g~RxDz7rk2l!}Z z&c8uTNierL74<;NZ=l@@z<)8){F^o<^@Xb9EA3`!`x73IzTvWQIu+^Sh#{M~C$S** z=sP`s()6MgIOHdwGL?wfuv?&VJz}s1o^XF%e9kF&KZod-q3N&|qc5w%6voimPQDjq z^nP6l?Rc`ifjHpw^O69P+fc@RlIP-xR&U3P{$Q!OSozslT% z(3+Binx#103n2t*Ff>}7*qPXm2fs;QZi}k#5ENt~JN?c<#b@b_`p%v1tl$L0+q2O6 z!63MnV`x9Px+Yx|FZcw7=2GyBl5D)?)Z7;DS=-+~BZoLa8)a!aPrx)VZ9=_?r90tTcYETPZg} z#(FYA;~pe$vaLQ)eW$ZWB>|rw+aYEEe})@2Zk0S8qiC(BV~qX8;p3-zkyl3)t0SkK zptp+Nq&&59X?H%x6sV$rG`VgyDM>5|APovO@xW+|=~cn3v{vQ}?XN>we_;e?qfw30 zv{Y+NqLD|9Ll9`_(XE4#z1OfJG*NeQjI=hlkE@z0hs#B7WU8c`jpo1&Pyd9oUF?Vw zTd#vigFsi1+Y_4?r8+}3p5EUWWuySi&_~n&sOC+6AOIkyu#xhLVJoxLbRf*p;gN^Q zzQ@RIyBaW-%gDR~Qqlx9RPA>#H>wmRxVaSy`3ix0VzG`)z4nG@ z^&-(^s-{LKs~_)p;Ss6XQOKyKN(d`I&xV?|ZaxSHHYg<{PWVL;IkLwL-3J1DaCEm0_*p*h5=p;8A$_~rgUn_K z?;<*fuIplrGzWS4u=m`-f?<_AIK*E_KrTGF=TG`Ob2?dwlHm@=WS(aZuG(Yv7Ohs) zW3u19WNIMf+2c1fg*v@IHe?e#Nz86tYva;hJ>rn2UaQdGHEwwbD$t~NU*6DY&su49 z6F2$X*LtErZ^889 z_1}{b9o=at2jjWyDpuVuE4oH+8a>ND9fuR_jxpieN`xmqs(Mv&K48R48RoDC4!Evi z>073(`YU!U9>tKHFL3dD3?TC2i}&`ZNNW=-UO-TUy@-pWmEHOZAQXY4Q1@ero$Hce z4oI8ih;1NKCp;2^t`uS{z(f8Q2TOH9UupU(hh!*)aL!jf)RIL_(aG6Ge_4gKQtA4C zJS3EW@9Ao9)Y|9@2W5zOJaTksgI_q}3umZ}-<_MTl?XNRLNlG3Wedu0ji6pe>-jsp z{=oS|_X9tPoqLPmm}y^cV+p4ESPXTmq#ApohF)Q6*qVp$p}+!gv<`Y)%!N*aKC(Mb zPrCh21aiU1WHf{fyKDSeffa={-TWOR{hXw%=&QNQrGc^L_P_GPAynak3ST8aFrYsi zN*PcGR<<`UOK7#{`veLie^xLi^BK&)g-;{DnZkRbXFKAxKQq<1`HtL!uzV58^HdPv zH?<)Ri|>vhZ9Coe_nT&enGW%^`q`Zpf$M?oSqRtICuO^iT{M!m9)(}Wi(^wc5e%UC zfz87LWQdD1m+=K=y`pW(ZfA+`+a)zEG-aI1vgmX^yia{jr}LL6J!BOnT%7PE)I^r* zxx$Os+T4g?#j`UO*50YMo;C+kjpJ8}tzt+gD2F8$q{E)c#jJ8}=4r7l zgGV_q(*G8CRkRTfvrk*0jDP111*wix!Lcw4hvn)D}S2=8?1b)lI>bSND18cWRXd3jjzVVKMSG^p?4?(j$XUis{ z3vrK)8li1ez}pzM=1U=C)%{}mBq&A;NyBfYBGATt?8q6T!{`Os!XN;Ok0b7D@fnxL zJ{xxahkJ4Q-jS7v4o%6s+;pbtP9wIb3SzXwmDMmZSD&rAK%)Es2!$|}9#XbNey6=f zFXO6HvmK-6=|^gh?OJ>;vnpp43k)^_%H%?bt??cF`$InN4L#)s2RA!sH0rnC*3C`c z;>CZXz4?Zrl+#xQYr;SOlm+U^W`f~kLx+lc>BAgml+A$cOz#M(`T65{d^DN33Zh7D z8fkYDPlFK^?>J9^_btQG^9RR*j<&#X$LGF!6{r%G+YZ-T4t+TYemX zqF|L}`1EzpP8cO zE-P;->6ogE2PPgfnD9bSMzwz{mNxtl=y^41738r=BoXa;mDLr@lpi##(#iwjR?rpL z%F!?nkuP_6=N&lA&VB#R{JINxng3*(4b`B67+6Qke^ZW>T3JQ$f34Qrz7OztQBzg3 zT6o}(;<(6#0Ok#Y!h4fD(*>N?e!Ckp`lmZwkk>K(T>!CGH0qJvAt6_??ABr4$A?T7 ztUwQlh3004J!6^+e5tjoFiHeFFVqdY?TGum+jOVn z+(#U3%<{W&Hr~sshE7tG!LC?qf%w)af=XN==KL+1)taxz@Igf0@~)8vdMs_ zzc)f4#BG{yn?ZE86BUhRQoy$EV+bq8N_GhDyR)JMpIy-R^`KS>w9bDN{15B*HZ2WStU8VZv)=f*n`AWYT zd49+`%kY1*-erI=gea9Z9EuDJdQ@VIKHnshmYr3tBws;eDfCH|%gn-;o<0mQrqTE9 zOvLStId1To!4ltxD-zXGj^lz}u0FvjHd=z0`Xf45*;GU$Nsbpb)t)Cy=hQGs?C|6; zqLA^*LKn5k=3>jfk0T~qVDw}by1jB^&OuI+h*|ES6ccLplg2mh^j*%5kbe3vmli}_ z&{u4J{dGn+rqJY0YM|3Z!L+~qN6FTKfw-qY$4!;AF_kgE5EmCsqGo3<3$}@p32(uf z81iVG94B54CRX%c_}Z^3N7Dm(B(VQixDDR5h$!i?_cp74piQVn1E_kYo3 zgxy5PbzphrLE>Xl&!y=S1e{r4G&h}DiBTaO+!#bX;sx|GJk}*e(5~u^H&6JmH_MT! zE3xT#)flaQxW8Hq#?!npGGDZGy&C}%oT4h?Fhb}he9;NU~mm_-UmFJ!J7l#HbvNe%famDBG(hkZ;{46me z!fi|`yo;QDw;$UWgKnfdRkf)@AqZlhz|Tne808XQM~0B)G&3KVnx>wRw5j7}y+ik4 z)*>z#4z<`00M_hyXC%cz;G!x`RHG>oNE1ioko$A=9ljLm$5ZFYuw6@H z@MmgC?D|Ab;dtOMJ>tDDH>$?|p-^Qu0*u_Pi2sPX_C2WFA=GpM*1T!c7Xnyk9 zb-(^51#*wYEY&hB`9lGwIj#syCLeCi0oVSV!Sg9#z&nnfFX01a#Q_dJ9O)y}nl?Wj zp4|Zd-MXFeFagWPlQtgP*g)vmx#)IDAV}R?eg6U4GOUbE= z@fRd;e#@WTWvsJr`JQ_~k|$ zj{bjLUsLM@tpICqDJvs7S+)|HhEk+nJ0tNmXxIAD42sg8>r5cKu_I^1FL5-bt4t1V z5|Y1iW`ggDSoOaoX%FjDy_i^8F$_w>JFlB=Q81ESCllI7fpk8!-!|!`r?t~Ni)zY& zuQv#f>1&AzLX4n_9+t?ILjaYa;J{@4PY{&iZ5md17hFRyFJ!yVCOts%)F3F|wAuMns z{8-O6b_BsY+^OLTNBf5=ywB~x@fD?)q_+*q#W7vmFYEygIz(|6;@0&sOCA>XxkLV) zVO$BX3XQ@&$-**6Cv zDg1tYn#FiBu!<@2kPdTN#G&t+H2HKVYsAaIae@>|(|0nnI`4qp5&84`>Orcl$UtTn z{)r$)M?lOm7l~QvGEkVO^EEmvky?tQ&>3Bh#?miAcPJ#$BY>`^3S*K&#oPN|=%*r0 z^5U8``3XBoS!yg!;82^*M;Ib5;Rff9a5m=uaQ#JMY)NG~n!>5yF8L?Py_T?RsAkdP z%_s_V)W-RB2}Ss_58x37|MESX0$#=uGsAH?p)K{_HYFY2j6Qf+Ln72nf~5RF#lc(C zt8)I*fl{;|zy>RGz=<-zQ5(!P>sC9A(@wT&GzzV|{}6m0DDdh>#z*>6fWQp$5z#&| zm2{q}K{#B>gZMv3-(N@IFo}0gyYl7N+%RD>@(yYx>L>Uqc>>>twRh}#=|KLMt#2;V zq32GYrc9qt6xEtun}=yxFHj+H`*r-FGl`lUqtJ{VB^?s>gh6Ba%`>Xa%P=`Fkjf1E z{W~^2Lm(9_`-0Zj?ovbjDKYSqu_6Z72M`&hr;((=#K!udO6n299K6Wz;6`DZE9xw( zfXE%FQ6zQca?Y&MK=gY_%^6ADtfZVx{>C+cr|2gURKX0zXI0n>;MN5T_8b%?EU3AA z2SslNgGrH#aJ6Yb*v4mcZ3A_*IHlCfy|ZXV43OAq&Q1qfXm(*j9P}m)bX(7!B@kRj z6m8##DE(QpF$A@e6Dq$2w>Ny~*FrK8i75xaLs+}-^Xa#cOshZuI5{YXois(LZ!fW}Xt)*+m?i1wPmc;#n2 zXB2@;&=^AL!QU&tE8kjwEra4sxv%)kR35I@5~>QxpT zX9|<%`UpX}McnB>qd|E(Wr1{NI5YwvyN}gYvP8dcKLLFM+qAE5tJcI8e*4e;XzdR4 z@M4je6CLUP{EaT9oniP&M~__~f^(NASUIB{SNBRuzK}<85bOnHdB3@+Xd{DGCe5Ec z$gO)dCF|Tp&r=O2d+kN7p@8+ZWJ*S}o-&5kKS908l`)l89@T6*Tne4VLq9WT&wZHN z-DbikhQne*J#9L~MX?gN+ZCAo4n?i)EVNEc-t`Q0U#c20Y*aD7ay>4!634lD~&V%}X6XnT)8-@Fh+K;k9n#VT=~eE%4@AR>eYukhTje~Z4JQFS6Ku{O0mbC^nkLT{KU-pU=hX4=xY^S`6MOD`FosVmKZ?fhi=Fv*5?0wL!+r+zv zF7XMD&)cZd;ZMz>Al`Go4`HXSLFvo5Z{(t5MT&`XsRU-AR=iTEw(F! ztQhBa`NL}=G}HurId9hV*U}!8y;9anl6I>Oe*gIx!d1%K)r6!@?7M2=jSqQqZiM|i z*Dm`($m=?|ENRt7eA2(6O?B21T_<;xj%g1i@GIos?#Q59T(OJsySL)abLIW)+SL;w z0Aw*58!m9Y4I2jwNqTKaIWQN9YLWhs{(Rngk(sW}hF{FbQy+H*ro3q?0JROu*8PR= zXBfaK`${6NsNXMpU)Z&prCLzE@y?b^GW<9oBgO;uWH+tB*b1 zSo&iJK9;f5{63hraxhLosc}Y#EOWPAp@%$`d0mNwK=GRwf;!;Ga~kqpSCkTpMB-Xf zQ>DrID7Mw>g7Tm>dYN;;fW}v3B?vrz(@&{94v6cKgCNQ+)VzeeaIam>y5fw+L4ss!f7$}H6I%W1CXY&a%?rU!=V{|CpN_D)5Ro=&BfFS`P_)Uh*H#?$tO(bbrr|;~RFi%3xmATh>?v0i z=6Es;p2EdF>5*m9M>1FrCirC~f0l6r(Mcr590)dO07&wx+pYNs8>KDU;hFvcL?M#` zIXkrB*3HtVlk261jx{xw-1?DsX>Bn5wDRTwchAv+e+`x@X`RIbGS`J%oGuuik8K)p z7p2A@j^phdaWwX6%sB3CaUs|)jF3qDZREP6Mq>%|JXIyRJiIb!hNF-V2H)%qQA^b3X#_CvozD`a1dnBwVAQZc9H5Z5zP z+~jCdSkZ4!CqP%pXC$>qMuTyTot;{+@KW)=02{tnvdOHe;0r?(YL0dlR{*i|da}ya z6-{KqQwL4j)`Np80F_NySec+Ja;7Wg(7Mc)_CPw9G!S`kWOsZL!2<+H-C3XpP&b{X z;Zv7=v-BeA%62h*Y)ii!6QRt^ixG$%-4|z|;O{K|Ai&V|eUsD*kpS+tB~H+EPYF0} z5DWn#HlA5g17VyRdj*ngYc#hlUWQt}bs zbUe_Vw&~Xf=iV#0s5K#X;C;CA2kL-$(Gf?dYug!$tspHF6M6IY9NC~WC@G)tIq@D$ zU1DGm__U#?i0lPN<~d#1Xkrblk*GGI*R=EJ0)2B1ZGd4$q8a6zB^JLt`*sW1S!i zs$pXn2-hX}M)0aT1($J*w13}ZUwEvSfz6ipwy!F$%EBL9TCk7K(G%37NTel*NJNzr97OO_ZB;pYSXeprosdL%|h3YqWG7E-m_<$h;W#TT%vG zO$OFKEZiCc8#SB0m{mQMOf(Phy{=bAx{gsTD;J zxG2YOzOesu8G|SYwqWA14cVvJPkw-?l z8%;UnV$)pWItjHH20H4RsO|R5D~FHX(nF8bis_a+KA)6{QG^CPPcJqP;Omz>$|j?; zDZ7jKOixmp=bJWjF3B4#r$nT}O<5Y@G)?Sq9EBQ~WlI8Pg+J+YyO@86ORUS7<&L5G zl)rqxS0x(ug)X#d#|TPuD<)R#f;PP6IH6eZ+K{VzB)Ly)=@M$3+-T=nv zz$!Ey+}ae21^}ut@%yCq_shfd6U4peABrL7WZXfD8EW_s8IL4wiWH>VGMW0EK_F67 zhOp7CyNmUtzFh>lD63oWwlyiCCKokfM4YGL*6g|t@2N$8Gzs7bAQdb|^y~=%>en|2 zs_(Pfq|dK?qR{Kz1xYlR`WqP?Mm`5o^AmTl$}5W&$rftD*U(%Zi5$Qpfk681d27r( zs1B9);PYVzqN$<6tY_-YmSC1)uIiJWOZCTp>7YATfrv=lN zj629cKoA6n(7#%i-L4eruj7P#zy zu8`m>Hj@(AicIy7bhb}1R}y`>@$V=YC@nBm7&DMujfs#>3BkAeZbM|QS!f>I2OeH~ zP0$DxHZmgObJ%D)Q8Px`fU&(28LxM+BDb&LVYxp8`h<&~VTBl*REOM^7|2N_@&Uhy z?L^PE3g^YDeYO``MF+*Q>DW<)%w1FA><1}0POL>A0i)p$6HaKp1GVm7l@C7+Lfgn5 z1h*Jz8ZRBf`uu{DKi_Tg>80wy`fCWspl=7D=uL(Vd>idc{z!R%g17Ku%n+-|2!8$! zNKxD^M=%K(4*ji^7Np3+Ob{7jD-!@tUdXtbpGEI?!?}XWka;XwFjqrUOG`tmC1K#i zJo@EyJoUWDYJ>u|waU4KL*B(Y+pMLgeTy3BHo}F-#EgnE3#ET=kdck9MaNVnL1VZV zemWIxcrN3JnVvH`#i0bIKdhQ@Ahjl;UP@!5Rv%ZVv}^)wT~1INt^)X8Ayy1~Kjfjf zCx~B0>hT2fH#(s&QTis{fW^#^ZQOuOf{UY(SzmfKeKSw_cw6eNl?U;Hn=@I8g{VR0 z4J+ktK;-MqCqXfy?q!N-0ABgBFS1KyP(auPuOQ69O^E|`A?1goaMCJhaj$#6kY>{J znAE-V+x(1hhD33x|D=0EQQqmtB@sgk=a1HhH?z*vGST5d$+jhCD|_Vxq#~LEr&Fw> zJ>IladPfl`V2-=`z>H8k(-@8`$nhuAQlM~|0L9c2=g2!mI?5W+7NFPc;RsnG-SdbV61JKVQs&gPk8 zt8>@KZP>}Qp!kJEWT2`SI?oiuyj;MTwX}EQdMrnY5Rdo{g$L4C{npm!PD6AHWm%50BR#L+$SAI6KdXzuUzKaV3;#pl}u#elRvjfg#K-3rWBZkMZIU7+LSN z>V7=lyy~O799L@SFrVL{E6+7!h8BzgVr4)caH!?AErlM_gCqgu4i{VJ~u{ZWjexW!pWus@abX2rH#L_@bgVISXpA zVzvg-iTR9SAOQD@Pmde^N1OF#M7;`Bc8smiF5)1u1ST$-fp-{AFI5&<>(yYalq2p= zKLI{Rts*k>1u#GuW3>(_`JI~3^Yny9jISQP!{jxm!zhZ*gW|m#g=deXOgoNYH^G#a z4s0*Naj@XjJ@}a50)d+sj_<~x9&?Gr^))6FPJ5E6kTe^a9Ch}~+6b}oVR?t5Jwndo zn~!OI$~wVC+)Nn%fk7ZyFKi?|g`I6W^MYz{_yGJ&X`N_++K-Dn;{w??M7fh}%Scg%=Ur2|g`ODO+8Ja!(^9pF9kWc69d>`FTv_~MCE_l%w>>181ms^AYy#~tDzqmh#389!2 z^np#tYU#Ph#VArg6F#o&!b$+B{B792H>G&t^Cf$u9V2Lj#@j(TWzUVn87eN4b_#2v z#65R+#)YoUdJ(}oNE(QT7EdY_LR(&059FM@4!j9Is<(*nSO4pAo$$RPp;|_=LViI= zVO)%9jM*rc|0~7U2RDdClh;vwSr6bYa`fwxkA94N`Tcs>nbyld?_rvW!9&z^_ERie z7|v?&2B&4MCavg8NC4SFF~@hn&ayn9`({J7Xie8E*`l?M^wV`wSNe7^{J5!rCLFiy z9LuQXl>%9|VAo)h-X9$M^Hy6Zwh+%GkluCo|NQNPTvGWy{P_s`*6lwAVdN~CgoZtd zTlF?932P>EQ@KDo&x|^H36Xu^dIi5yy$lz5Ft0{jFi{X=l50!4rj)o^!y6=Gqt0&2 zT+Db;(+Op;2dUnINFgMk5n^OrC>nO zu=(EEP*%1ztF(AH;W@I-@E3A8O`TfcEnOY=4;^Eu+4NKV7l1p7YO}LfGe-FF;C$T# z7KP|Sk$J`}Z|;bmSu#DGs4A>KJPM`)yA;p!i-5du3Uw(}I=dU~;0vS5cNBOX(GRHe#M$>Z z(A^J@2yGOX?G@kFMLJ|4smF3~XITO$ulR4(2V_!M2_J8=_R1}R)1#VMbwb`3^7@J9 z5$~VfkR!2~_){#UH5hIYgIhD7SM1zr^BVrU+RKR`>@*lQD6{K+S2jB4*Xyyp@K{cW ze1OP<8^m;e;gH|-3{YiaurPt0dTMs7GA<+1(qTB6`wM{-Vpaoz7`)rF|3^7)c@y3k z_^X7(8Bd@j@Y|&~f90v1DBY?NFu(;C1(&$GUx8#~6~|~ynb3!*>O1fjUN>1kMNjmi zC44WtLr;Mf<^bu--kN$>00Pp2HFT9z%7AVM9Z$u9R7c5MgLSlJT^$q6QEVa2rxhD| z5WSnoX7zjusjm>rP$X?NswJSwY}qRZDTKK-quC{S!_PT;$J!+$plXaO2J)U7B*M|;AAxs1a>)WudT|yhHp?*#Qdw!0Pb#5^ zuB>>kyIcoXS+-cpK;ibryvp!j=cy|f?a%|m(qEM3E7+W~c8#?Zg^iI*nDxukE>xoI z%U6q*1wt$vY0~|f4Qy$EyA1E278zW9cz+MtiTQ={x`B`M<|`Gv`fvvIaWr;@%6sU> zsmmFV$sRc3ru53mH$&8?U@6m_zPl@dQn=peCdksM?QWD{{4 z07An5(CS>OxHP*U+iEu!LUD@um~Rt7>Mq<#Lj9mLGAJ=hx5NFxB~#s_5PDjS%@b2* zDuk_*TYtK%!uh4g_TrG90zm$ZB%G~1s&R4P2(?8_zF&r<$|mClOwC|*V!*U)pH zcvtEBXqMcx>5MjnuDW#I0b>3vZCn0=KYr;bnyK9AkOdm0Ve43!HEky~mHw<1GK74>Hun($ffD}dOp_K|Cbavi7XJ!bxOXH@k^ zy_>@F-bw!{6Fsi6`BjJu)R_3Ppkd`1Qo_ttptf2$OVSxf1_u__PrEL7Z(eVZMoz;u zFkc_Y;3(agg-H}ejmKidJhpr0DTCqW{P^PEoiVAE1=#ckeI^)n?kD=>=C8VZfNMVn zlpKo-nPyCbfb3L1YJJl0~r+f&GC>PT;DB zV3TM-OIlqAnHadp^3GMY%d``bxCJUp+SejIIRfn}tbidoJuF;>LK#rE)8HMgj~L6u zWmah$I^3eIN=d(m##LcDY=?$WE<(c-E_S*SAyJfZIiY{lV)PNz` zOQV?&f?#L!?P!x-7``}E7`tA8DvC=>VHQ;$%POLG!9&a~J_Gq$00&iO0_P2210g@P zQuQneYC=XeGkrWgCBvV4cDcqh`U>(pQrE-YbWx@Qf0)2okhlGJ7faEMzjFR>biY72 zv=L%TsCZ-@Nhwob;&##WOMMj*ylmU;y68aY^xfO<|Ey=3xle&$-+VaUf}mMsT!9X` ze)qfY?LQdvvCrKEqY1Nc2Z_G;uRz213`^PAfBVZ5I$V@gKxmXdI5S>{**qgqa17r( zx0vI~S3X)Fn6LdlsM^f$L}Gvg5vnv{vu}VIx$n-kLhoxk53a|R21x~BcAnvs${9L$ zUqX;dOY3hq<>UPE^NT;fky`LcjirzH?x73DY05<jv^_ONou@b*iOsR z(66h-YP`DkKED|mE_ow1yUSy1yB-Yf1-&4<%51eD!fjItrR?kky0=1F$QV)PhOf5O z(kv{sSK4MbEY1}{#>BBXe4JcS%l^sg@;$eYq%tzUx zXDm0Nh#HJysrz{v^LFJ>Ou_{8X{uuZzNFk&*5ib?DTQ2D*+*5rAsvrZ+)-pKe6Cu@ zJdqK6Rv8h77dHI!#C)wb%)QTTv(PdXE~P`t-HhZGUqK|#v)tUG^KzupBkLoOQIPBr z@Fo}XgnnYB96Q@ltogdNpkybh%rTvo&;XQp>F7!LA#bpN%ry|aZWcB*O6XW+ow0m9 z5IN^n`UNG@ny0}Nu}a?YLP0{5HVz*%iP6sH^eNv6?7Axo=nv@Hk!!bUCW?LC1jkEs z{z~T+q7|U|t>#(1FD8D{IYx=BoZ>9TmJ0+UDjY)>2BxJy{LEUK3Iq4K^UJpP`NgoQoV2SaU>w29nsoL-`xp9owmQlf&mOA?TZT|{?GlcBR$(q@N(3>r4Ez+*!Zhj z^I+YU8$Dg>;@`__O+*Buc_Aq=O1V0WRiqY>Z^uMv{|y=mp{x3LLd}Wj43vg5oDmVE z3OE+%$GJS1aPmsgi<}_GZXzKE`xWhWY8Fo1Z%(`!Lu-?@CH88)66w>lz$|CA};b=%(WaWFhccfhUZ_QxsC#Cp1rAFb@n!s~QaksBMAba9`b@^=N$Cw1=q$or;} zy&|il=@rQMKI-pO40(J%iCA!UYGwu z`g#Z^Gv4L$_G4w{$N|*m$HK7F4(m}RcK-#LjM7GC+3|}3=NI3)u-wGF6m4rZDMwqa z`p(@8zJK;cERIQAa8(v=+T}?${q*z-(PrELafu(OdVk1@J{7Ob4ip@Op=@udq@#Nm zSB!P8$sH>q$;Sv~(Xr#(b`Mg*eJ^?+=I2Gprj<4jX$%b+0hfB;7r`@r7;uvU)TTK~ zh%v>kz%Jb_2uAv#@6L8ta5Z|@BOGnSy>kdlY2OQW#)x{iid~5LMfe_Q0VGc_<*gCH z-rmJ{CAnqs4saBC0u7^mHbNON36ixp$P}g9=RlsG8D>g3jqA~AzQ|#nJxetxm?>nh zW8u$cIUV0VH}n>n9O#KQv*AWn=_zQcZy%7I;zK*yuGc>x%fe%4yFiy^>Zd6auci-` z#+S-~yS6T0S+ca333#P7(OR|1GP_qEzyG+2rU{nDZ9okFoOXe6h+P`>NGl9PL1y-# zgES$L5&G`-<}9A@7~4y8)3V!?>!4e`T}>3&m~X_)AF|JpQK|5Ix;0DTOu!tj_MF24 z&IHNm(i-OthABzFN5go%5TkmvAu;yXzS1(_s6j`jd^orbaMVyR*~TCaKl*B{zzrFp zcmVwi%nI20qInEEN$da!ZNxZ*ETR|Vs0QkwO*V@cvBfT~X6&j6YYQ(N#pD4MDH7KU z12=l*PCOiqGe>wVZUwhsQXxQnSoMT&c`qJJ1m)R(=|rUu=Z#)SB9X|Wx|}Ct^DvAR zL&B!IT6g>wqc~5!P95rGSnmlGw#-?@dz5u@ezQnk@qpX5ZLYpHv4NUI7@$Bqi7>l( zHq-$FsrQ3YOCL%eU;6Cf-V)qvJ$y?UKwDvLn~&FL6RN2gs%nZ;$wsOc#}HUZcQ zz&98Gci~XyfB9tki%ewnJ059johTh()-H9*Pj`piU^>}qW<@h1OJ$L=Q^_pZz+@o! zIs~F$XAp*P4qxf|iD-p33O_1CE8x*1QjdwG zlBCz#)R0wo)DGVWBRs}~3OlDFf}N|h_VJaYihva-HI6{g7E;JREqn^*Evy7X@R?@3RC#Vy^WS3T{wzqf7HZ01 zIEEm7o>ifMBb;);!WJ(k+EDt=d_|4QlGzm@ z7aXX%o)PIw6~bqIJ?oRvD&A*`-mteD%*%z6{8}9Lp@s3jGTAjN4EPsmX2B^t1QBJ& zhHDOKhPlR1vO)M#r}(Z=q#$OstCGcj^g(LC3lhi+Id%z(Crh^kfmMPRY&InvQn&i3BWGktMf)n$gGL2b)i z!=NHJF3U(=T*J?9@w$?g){QW%AiwQp#i--W_$f^SrXzt+pRT@zmZH6$Cof|?tnt+tQ2yr9T6v6>@v z?3=jTlJNr)>dEygGmeP$9;YP-!prmtGoa}2R@wB)+2+{Wq zHW0HYs+R(w5ii?4A6u~(E+y>+Z_QbuiDsz|GK&+6#lBTIl@GmriQ0r&hbIgAgK`)p z_HGTFhdv}~wbnY!2u)b3$orcd_A2Y*^eP~EBW?97eJAGEZR$A}e&@7!w4VvCozf7M zIp(b{_0D zr9g_+ky8P`&umqO+*qeRKOs`$Bk`KMnUJ8l3i*&uUrjK01GAvOh^>FblK<*k)0|87 zVB|&$1U^b9!+mu?VaJljvhxkJi>TK|jBbi1j!_d!*IXMIKQd9yK}n4#M&c?OeVYg+ zXDTIt{Wwp9>$jE7V1t8$K0<0$lEcSWC5Y#*H+!J|q~;)DsBS?Een|1GkVC&cP@`B; zY`Dc4yW`r)pKMCnHemy^A_q7DD5QQ)uErt32PdxH4A`BZ_^3N@3ps`rAakc8=f7&$ z8_#pAs?S&Z7&f|e3Odt#9Y=AQ?i~Nxud<=}0srtk|kn4$#ECBtEUdbZk z*a17mi3^Wj8qrhv@ zFK#i?+`?Gnq<71M^TJN$w??PQAGiB$@(vp33s6cStHmv`4$H!@8bMImdspqua@yc0 z(@#bwpsV1zjYKL~IJNy1gWojBfVE6$+e&|B#Fz4_d||-Oa#7)s%#XL@_OquP$mdn& zAg9(Tke_Fu48c$94ti!p(+Zj@^dr%;Rwu|`NW!R1S5b!FsJ@y4GmC;ij!??_%l?el zJEuGof_i`37w6Y?-(;F7!mL1BgC7K-VUpEB~FiR;;K0Gbr$4 z#!9*`z38#M-OK5xHJVpAu_jY~VyL-Ex$RD3B0EOhbC&W)Z!6wUy7GQt&%F3ytI6RS zEy^f~z%3-LsCt(f>jH64zzP&?yVK)+b)lZcE-Iu^yej|lNA9xdPYMuxwWF0#aQ<02 z6)RJV5e@H8=T94@!~Azvq1pmn*+#Lhs;O!?la-fB_awIa?Vx)U<>Nz*_T1e zl+lBqqP($l=0tk8w7#>6a2o|mP8j^yn*Gx2{*YwHfcGI36+b zf?5!AQw4DSz)>7}ua)0`BM=!DOrWXwh!7}{&xIw7eLgAFhv9yzoXe@9Sq(}V^rBF; zcO0n+p7V!pgy)m7W>*=|uR=kq#Xf^(%|D2vZKGMj3sS_yKKq-03=^UH`NcGVXvQb? z7Xf}QAa!-$2M~fUE18r32*1WFHDcQs1+YODF(a3^s4P!~Jah9c99h zT2oX#8lwV9Jp5M;Nx~p0)(j=m&Wj<|3Qw~Hmq6gevhP@DFP!saq4ZVKE|ykHxLOHKP1TN~5*reO0k0mGw#i z6d#p{Zs0J%I!#m+?mulXw%=R?-bnD~3l_J(>{KMKEHRUCbAZyG!&?P!0H9C`^)Tz{ zTpQ%EpJ3zkrSC~@g}~c1RW_XRgs(m`=fnmgn*eI3VNn2fHb(G3*xXJf9&?`PE}Gj8 z)y#E4J(P6liuh5KR+8b)y4*J11jdtfdx~u53r*#Nao(%usUA&%EB*5-%x~JM`h^T# zKYz{(b#(Y_P@AEq{2y3-4EmH4eixOE-Zwq?N%o&wMkNNTXh7ool^$NMT}(mejt%71 z9|SRJl_Qn-JJ|;mxu7^h-;+^RM5r^;BnMzrO%OF%PoQ;qnQQGM_Hdv>lJKGCR2}BE z*G&V+l>NO*3u=<=Kfb6h>IP@fWxi1LhW^6=`(oi7SnQVzC^<8=*2#KJnxJ|>l-P8R zd8ihPdSBM0ERyLx8(C%;;TImfSLuOy5Ac5u8nuZE0(I?Ya|g(}K@xT>>?zl75k!qSHb$KvI90uvn+24Da5dqZ)I zP=*tSqwh2ub^8UtoloY{pYZ|qXnF>XD6VL)fnb6H(Q7fd{W{$N)cP= zr3*XBU55bVxNWB6ts9=sI0KxW|EnYPkqe5nj(Y9RjVzlfQsE(NwHkkbE)Be#6=b!T zpC>jk#WI+j#yeFK+5Ent-$N9`Jh6@JYYvlzM!Gcd1NBS3OPL3eq%Hw zKZCUll--2g@3=vSxZixeVN3p~7!i6v#Kv2wdI#n19cdX`-Ba>a9z7?5^?JEc@w| z$wY57r!-5~?YI_rA=@gQ0tb@83)+SN7I9O_ggtwut>WHThkqJ<&8md(A_4WSYAeh9 z!R)W$$VwZ@5whqlBdewJ9tV{{??5XSP2M={e&6BLZTpsyc*%h+ue%<|+bb3oL~MKXy%n)cr0&O*vLHuB#}A2QVm zI^z*_hH&!_frKE0a9lu^>~BgzYuuO%UQJp>q=}7Sg527_(9!Y)deLi}^7J8PES^u; zkqhH%Mo&XO=NcL!Hd8yRx-H&j#vw5JeI@ zT96pwnp?&|W66LMiljf6dbaljJY7PSD}gTmBGAg@urkLj@B3nGksbKUJ3kIYCvIXU zjId&KP1QkpYK#yx(&yCR9z-Q{gdb+u`+G{FIW6@T{q47Ue^=b|Ol%tBcL=bKB z#)|I9lL~3f{qIiK=j#hu+s=2e6~@HyX-eSgW1)D^%Fcq&?QDnc+5eS@n0%&c_H-CJ zR&>wvju)%ii^udEV!3b7ji&x6rg}pY(>#D)A+!>~l1?6PEYNuVpr5k4Z(`k$Cb&WfrX(_L1AkQ_EMhIJu)q=|3kEh zQ}n8U;Fe0cst{FV(3`fnhZ7Q56i*E>oXmw1+Ly6QMwJ8mHLn|OkHBFP zY)N(Tuwn(6LtjvXC4o`YtqXxcmAEC?Ox9KQ7d-+SoFb!@xzLuzFR>H~)Ec|c{t!3! zKiD_3gv8MAEWJwIbL#r*>`1ZDItjsojI3qS15pce&N+dzip+YjGLZIz$?B!7z;8g5 zpOp0UD9;q#1Q)26-r9`&b=g=lUQh*{Afm4li}Ub4Fwl%z!EHEGyy`^#_#uy_d*?18 zODxm0chI$i<_3}3>Vg+5n|~vKnsnI=!o>r?Z#wEWe5zwf3vLfxaE+ z^xZ!=$2cvHxjqR*CuZ`akHoWjRy2NL_*dzNsCX|r(gs|AiJG&`lZQ_`dy)1pku9)Z zk-zMB@=$|8@I`T=_`YF#7pa@8N)I~1@f-7Np98Je1I;Xh)$`V))lt9>4CmYje_8A4 zLCB@03{VEzpdX}W0IF};38QWTqFB>L5$h8=pr9PaMu(XfQDE@qMdJ*OOXy%@gg8fT=vm`Ko(mD$tWWZYf^%Umi9To?;lV^cDxDPqI02 z0{Aj7p2~pjY3%gZ=g8O0EW=J$v)j#U;I_^UHChlSKDJ!WCE~k2+0R@( z6OH0_B)B5+lo6~X0O8F$e}>n;ywQWDp9v$`%^IQNT`^~{;ePpbXZIb3$Zr$8rx0y$i7x!7(X`x-DR8O8W;p12m3x`+^ZYP^T;uD zeXOiO-_vn8PDwjyrD%F-`V(V5} zqRq!ID~mbNwl4;^9F>8R#mjjT_xRHdX;TENyPaq8(;JF#;jxN?L+AKZOcokE8fFtC zOH%V9csDn{)W76bkblyqT4Ig6s4LJ#hxwR5Ro~ov1U*1@qa$qMenW zKLiV|-Y);ri{X3CJdr3OD+CG-BDXa}aAix_p$6S>p10lDWsw z#Yxm%DG>LOIf}SdWUWn&5LZ1z zra5o!5euj0H$&y@-`{#_!-Um0wb#%HdNcV26|K=ac<;1X9`Y4*enr~{BDbC<0JmSD ztbWEO!8QIF7MDx&k*qb8_fxN(CO0j&AL8dT7QI6{sJiH!t>ZEYkz!f%wYKXfs2HPC zVq3cxkVTiOY&QkZ|N04{t}mow!&23?%51oM8^thJo2>?(s@pShaCp5Q=XP9r!*yD3 zIaCSlKg{r>nPrDtc`$C@f2F`KH*AqI6Muu$QF#iwt^Sz>KVmQ8{h6o*K5Oc)srho0LnukK9G#z8?Y=nl1E}z93|9UV*67 zAPSsw7hhAtxp??)_dZz*`-9U%oajKg0~GCP){+g6CPnk+b2HqU=8v!B#Q%yu^x=%7HEHjM)_0sV9r94U|7vQ)|(tK$-z~DBu76Q+@BTY3VIX6|d#?Jr6_BQbznxq`**z-UFGJ*cbm|C{#uIOUE}HzOk>Y zY_=*)=)^UuV5~aw!r^5sR>N`r-^=}Vs@FDM3mxq~1LscL_nXv(WsVdZvIv{%t^{%F zrn`YhGc~Q|3%2t_(%FWJ;79pPosdN@{1_t)BbAMr7ns)`7ORr%Pf~l2k5fO+%=oxc z&Bs!s&26q91nCMxl8EIJkJm!?(}K;2K2Fc17yAFlL&*euqfHA;jqf_#-k853|mI{QQ)C{!G7S~;W{hd6TR74+_&dC63 zQHDA`(IG&(IwnoK&hRUtk=J5Zk^gfm(^CP{J2DpyHq+dgPAnNhAJA$B@M%oLgbs+S zbIj8=AL^Y#ld`G(5Z7!kK*{`Ga+Cs)Jnx*@u2ryNoG?Xg%$M6mo+@0{#7N$S3>I>K zCOc3Vk*yBa0k!rV0*7G<_EPFWGJX(5YOOrZE3#ElThMUAICBp6NseBkTE8Q0c1!s~ z(H_ajUp72N;%k=ilTyvd+Fmt_RaGw(9%3di_01@pPU4bA?%V#uw2s?J#YK8Uizt28nxz?kLN2?SgPSHFMJK}_eOjc-m14Y7j~3THnGJ<> zB3-yaw{hwzDj2(`)$_b6MxolgK)zZThfEXq`6(tzUE}i)vYluZ`c^q(VH*Co78GA= zp`&%m|6zssKBZi+t|kqQ_~^{H1>ocR^FS9?K%x_1tIuHS7>g0)B2T#=7yq~{{940~ z0D!nN9tPAF|Gsgmo&OF!J`|M>!rh2k*TmwZJm+p^r|BQEco5MYU$iKg$c>2$#y}>1 zP~|L77vy#f4=Q8+|0ConbF>tT<^iQPt}2BeW-Ivmej7S}vb0C&Vrj29Z)M(`yMk~p z$Vbeci{%gJBE(8Tx!>>cvXwvOMsGHU)v&2w&4qKxH`thVpHuE-yjn<&OL5VSR- zX_|U5jt9v?CCGwFNi@40)PCscCUxwbX;BWNp@lfQ!@LtJwtnw_4e4U5c>RP)hPg5I zU}T<$>FYVM%V~SUK{!8{suDRC_zN!o=j)>IENqViKCUi&?sB$6!#KuZM&B7yt-^jo zx_)%9u(q4*>-2vwt18fLA&)v3gmYv(YArbc`yp?I;jVvUORSfBz(zX2lG5j_ut(kL zo`h|%cPM@?$R^Dn*ie+evLY^!xieTuv7O7N$pn=G=378)0o$o&yj+AwvNKhISc|Gp z?Y$(Ten~i&Z&rus@*+bD>qIqB)wCNagb(;*Uj8C9oW8^#;Z}J#3P8N>|BHUd6$mqx zKK}(p7c$4~Z@KA;PoXaM_Lkws*)VGz9`}4DD}+bBAuj3J%C$aCr&SNcoQW_LGYT9I zW5KcfWfVbx^UBE)l1Xmezav~S8}(#cbn|-PQYr)Ii_nFA2+v)<)xY&-3e_bc#sA-B zs@3tp2C|RP&S#6=&oyw|M$hSMI2ICPpu!LDXOS2GY9EB5KNq$^s{z0NpvpeQlFyfo zCo3nT8kdVo4&H8tDwLG*;)CE`B9QMRtlKX+VI2gFeVD7Ex6=ojySD&tZa68P2cuWNF0o(6a>z=lP7>_gi z;0TBmbs*9(r}Lc$!|8ti2e!TU^&VDtYkPD2jsz$FeXF;VmK=|h>8{xUCpQa&xi@&c z5kJzjz~s>KBS!EGcs{!z#;#u3pYqM%t$O|pz_THVYb|Kz$V{$0FLh1B#^AjY1luF$Z=2pd_fk#`1zM<{-JD zt%45yM0Rq)>#Xoy3atDVLEIKk(01J#Q2+=wV89dCSrFku*VFS;RR$X%U_@Koxc!>* z--D~+8Xv9+wlL!ZJ@I&}XP`gTnUdOZ0nwHuq!s0nuZ^o6J0l$T0M?Hmg6(pgR6mV{ z!%V7PU1Hft7>Y{*#}OT6uhid@H;O$!`mXtTNq`&UNkkz`jfuMaqu=p3_$FEcRSn47 zD7oKXVet9Afk>akx5Q5Whcjqt4rEPz0zUpEn{QlB=$r`>VCwYnkj}rF*(&>jyG}LC zB5i?)Tha*)zU{_cZD0V=CG^(`*^`s1#h0f-nEDL20fn-~6CH_2-_vQj1ORCf9JHi; z(IEqxQU1Zvk8cfFPPZl}7xlfSsYpug7h_a!Ye5YL>{RoD3f+Qf_#-WC3e&tz7zdy8gU(=qF^l8xykQ7 z`_y!!dMKK|a%Jr!RCmImcC-#9(L?^iN@_zx|Loma^ojgmir|_p;o?Mg1AALI+nTXZ zqW#u5Qr=iBBjbN7_=y{d#YVgx26_r|@$ctQE)Vp2!e$x!vFOZ(vk1_~uGt5xbyX*vKrdHIbLj)5g zV`xVmtm5lho({ZH9pRo9K3sma4yX#-;-z2;CFzcArEGd|W>Z1)!p-P{(lB zw6Tt1COm$iV%!}9BZ{)Y%-&IY`NUV%5j9!;^g}UGpdf^0TKZay&PnwftAK}9lp=T| zgXayE*f3*b;xV;*E~mtK92tnRByR10hV0Y-$wHwoqjeo}8Mh7=|Dmw>bZpgrq<2NCM+nf_X3XVWJG=+i3{ z1oQ9)a7)78;x1nTT~L#wTSd5Md;>3Y%KHEzP0u%7&Jik?(02mT*wd9xk}O8U4TL$u z1@9iG1NtYT=JPK|=wJr4>;@xV+@>wGrr70oFv-tOaz@$#du75n#Q1&Y_;TzLvo6NF z4@D42$LZfB*b)phEjbkCIbQ*ujA(NJ&e8yZ;f<0;_awGJ1M@Z6-dUmqO&d<1D%FYeFO4jg{qx|ql+qC0C@tt{?%=CyDo$>v<+=Ue+$+xI(ULO9b*(Bc==r05$J4|H(vU_NDa4S(%`prqf9 zXKR{c*4SufI^4`JRjwBekOE*=C396}AYrIR68Bd7yjEs2PU@FOUmB z6hxih(Oi>O=h>IJohCKqt7wsB=#90Kt4*W#@oyY!FoBxT^BVvHPPXP)_NptGt6Z#j zD~JdzTtE(7jv&h2qVN6@?Cm?27oXuw(z4*xOFoq%{mfwf6v{(o6e>LFzF62yVgR0U zQjce4O}XEm0B$w@o#Q);L>AP_=e%h&Cg#r+cBT4aI%(#dJJ`3qYN36eLi=@3FI>uB zpMH&V0m#ob?T(0Nb7gIbGVY6eiMVh6^08u)9?5XE-L}1MF&I{+iD%LDxzdGcMSDL6 zP(GS^tAY?9cGQk9?;R5$FFbPg)Wavh%wjn#>D7lkNfRY$jxLdNF1gii4qgk#$ny<- z0JN}1#5^NuE_M??| z^tVfqng~E`2GW_-aC&~2US7%=bGiLrRh8*s(&Zta7e;*`1U!(uyK+x*x!SVIZd(W` zBWH`u+$k09*D(|QX)@EW9r+G2%scLj2f5Mef9EYeY~Bq zd9H0Aj0hr`dIG=2-xN1PYJF6|#B+A98B8pEm&}E107pQ$zr}ik(i;j7E79lF2`bB{ zeOe++63KDgrsIetBUE@c8}IK#vT170d3jD$=@DjaH;oNP{p!lvGNA2D4yqxIqY6`TGM5z0<<7jH_3Ez0#1sO^vs&|5n)N zN&Czdgo7(UlYP2y+5D51MnOXcA`cAqKzcslN#sLOf0N?Rh}v_!GwnR9u2JPc|2zW^ zup(8o5WF}Z3e|UcCDz-0--!FrEhk5j@2MkfN4S;#P{$Ke{FZ*hMU52 zdAglP&vBrhoMvKbi?``>KmHDb7r{=F+{e zrYdUYEbVOS%yzvJVewSeo!PMVkat+i+K;-aghp)Ao})Od^wJMoRttF7Z@d~K6L`o> zSX?2y{4_sGQ8f-B>T;8xp$1>>p-iFIbVV2#=PQM3icR#^PjL+HDC1j!K5L~5Nxx}3 z^b>MprE?7&wuLdZ*<>@;pt)6_UA*zuwPUS_+%zAx&FfEvHA+W8NKx|{ie zEh2H0Gdlj^>XGXmktcE=v|n}XZZKis3yNESFpp8Vts4ZIXAurf)~m$H`i06DHl``L zAArO{ts3&%D+&%U41tKUW4S*Mi>##T;`N3VkRZEYY^>gJLWDscjL1K(UE@tzQOe!6 zi`A(9dR*HtbuGZpH`f*&DU;2)G&Zr03m1E2W;;C4FF5hn+P$=4STUQt`SH^uhB)x%~^6^(V7ee>0(ZR}3fYja1}**aPi)qvHbY*9mr`U{;pdX# zD&7;p767cW&@j6sSC)Pd{Ts5+dZ4-My)`Sv4#egYuqRSX{~Tgdnt$-Xt^5d>@-O-U zXgfxPo%qvCa9-I_-atUggt~t?W1xd})lV5qDK@XB6B$KQ?{k9N8m9hE@I9+!t9P*g zYfa*`#ZASVC`z#gn@X^3)rqU)B8cp3|vh;Zyf)YC> zYQAxg?BB2S8>#JY&X|$335xh8j#7ush*TUi!yn2c0euJIW60oUYZQ^$h_-@Li&84u~uA1=TX$!x*z`E7xm`0)5QyMVIy8EL9j3Af%c z60E|m;PtYus{r)kTlmb+FHua}lRZzzKL9S@Q9~dNRF7?*-Hc|ou4?>&@i7j;q_A0Z zW5u74p}}A|&^xPoLpksi2Paqn@4ofE}H-pKI0yYzubo<8>o(k320#|B^m0Mr_fTA+nppci^j)zLr zkSryw&Eosc7ZWbU+$qV&Tzc_uR7;5B*UE4L$jv!Qk1Et>jvvHFi^{&DN_VY6L3+bA zOiAE#O@SY_%1zDAf=Pldb!4anzr375o95sr#4MV3XA!*%cf=}ql6@Gt+%QJ?XF)Cq zXR4@?Swjn?q}k$NKQ{1&^@l%Q6`AmnQ-49T>$anYhW|X!Yt|=+Q2k`uFH5IZ z<19)G7H1(BRW8-QFa^U*#TB@=_$_$*!h%ER#^r;y{PZV|xS^fEQfGe!vJ_l)08r;J zOM#uup4CSEhXZsM$aGkpSeB&OePCInj)_XlS0y#DXM_|aJ8`KVabv|AW`XZ;VKB~3 zmZoIK3ABa7-D2N0%edc5J82oUIl1%x7)R$4t4OW8##~uk)~ZcuMAjFq;(V4O@!qoLk=-0%)Piv1*Be+nI`^}#j9?kf)IE)a?cJkAWk;xPLH zC=%PX85cK9Y*5DSsJ_^z>CTrJQqgHeAKih*n@9@J$V4PqxGK_WY4 zaj+;r@Y}Qq_4u3ZPc6m&Sdv89<^&)wIURKn6%{(;Y@ENK75X+-1?vy)E#H0#0S|C` zDY&>%*TyyR;VVH3iS*9G{(=RU1~v^V3=BMOOkg1#!#kRZ&6DqW;2*o&M*po8u5iNuNi#~!gj0RWA7YV_!PZ{%~zzpnQg<{X!A z1X)o0`8s&(2PQnusRk-oh}ia~{TC!fT?_n~F}AhSdeNmc9uVBI&?UdwO`w0&vD+z3$V|fqkqY3{T9FIaJPIAO7X!p+5I20{dB)~ z?*!OrT)&Ho^pca1W?YtZ0U0zd49@RX-?g7CDBTDr6zg*e<||KXO{ZpQQr|5g!TIMC zebNMUok+2(c93iyN&+BgiCRHA$FdwOvzINu#joH+M+T2(taVpl;Q7iL&ifE0wMVWN zSH|X~gs?|a2`v_43)tXV?ORr=hnhv|-3sMxM*9(^13wC(O=*CMv8`bur( z?L>*ap&|idLD}~`V9f*mv=yo+vqxduUH`HnjCi}!y*?t<@U<_nk)cv-DlYDMXkDWRfmZ=JMTNbESL{q zXm{oiH2+)k-LQzgusYQmjg^cfwYVicVYnkf}P1V|DB7Liv4eWoTzMZt+dqK zau|OLE3@T{l$6vGLiM*n%+`S4<2hQq9dD-5*Z1(4>BnVikS^s-c+tHt{3lixXg0Yx zg=6pj6o9ly^n9q^M09z=pwqq&m00qbBt51c>Mz?TdmCbW%`7S!`AGvXmI_e5K=g3aa<4-=PDyNmPh z8YxqglS>+aE@I(n5T?M}L~LNP>hr$ae}*qQzRukBRy;O6QLDwK@31Z&I^O&fc(p7g zswMqYNS@KMRGuyru#9Z}L|OykNw%(sUUAcT^NZQ6vNEnVktYcGiCztvV^3^X-yJ8d zr1d81UfMKS)PP7`6}X%3{Fn-EzDFNswlUs6lzS>zLIRHIeWX5J+)E5QmVW??zm;!h z-g9dDuiAZ^j-(H7)okA@i~3b8D5L^ubc=9@J#hJ8J4vbVVPo1c@a}a!fVFus@Nhvl zv75ZofQzZUicG&OS_X1dU}X=wl`#u0@%oz7OUe^c;DK3>Uplczu@K4_N*>yGqfb)3 z2qwdV-Vy=x??=@pWiT>1ht9oD5Nr%jKVzy%v|+FcbkX482h+|oNt9HmVry%fxQ5#! zZ8BQybE8Ozuk)XuGdpeGWRLHRENV7Ux;R3+RRKP5A&WSdYhU5(q(hDYAe1OC6YGh4 zpLY|;oDE@oT>W;_zcCD#ftrUl>krf%%dOM=MdZswLw(4cgj>9vtFuJCNv1+3Vj7DL z;knt@+0Lm&7Sy)83W?i8PlNgni=KHS{0$1vj!u&AxM0avfU+6h5tI;RtFZT~EG0(0 zdFUQ5h0jJ`{Le3U=*}CejhE0E+-IB@SPq1X?VbSt%@u!PsZg*N(WSUi^YrYT zp0-0IYrof;E%M<@6amF}nvUEl%)H^3=sP{DF=N;-)U*!nn$EkLCbX--!nmz*m$f#~KXMp``#i(hM(`;3{7FRM>+khDY}@_b=^T9s2-z zfY~+|kZ47PvCF}ZD0xSHIW?-Wp#F%*J#@HQ5V02u#sPZN6IBP)dEr8%98<7lskaGX z>F4>4<5_aY(vrCZO$ptX)5LVD$T)Mz2SR(&DY!EA z{&g+YQj1>y*B-Eukz)qoc4Z#k=*G2c&)^<9c-966P$#10E-CFMlsvt;LtdHKbLa^- zRH%aD5%2dl8@m7;lH?H3^PQoRT_y@VVXRJ_@!(~-+$sW(v<1&{7^qB4pr84j-_%dW zI!mi&wki}uc5@?_^1R|!dwaIUsk^u7@o#uK8yPOK@I6(m+m=}994)buo|6h<_vqz9Y?-I0O$g{Z$r zNOqTFMrsEztPVQMtymNOjm1dClh3fbT3rH>WqQ+R5u~(8MO!iZ>LF z70^s(n2tuLr*&t_O`e7c)*i>+pwfR8`s7gBa9#BWI^3U*hU$Q+A2{kuN|kVV9)I1J zL{gblz}%8rq+Ib)PFtsCU}45o{L7DJBn3~HE#|i}%W>QJyxr6f+oSGkMYG(SG0lab6dr90J@nQWc`!&Zo+%9xrexbjAcz;>P`sRX!2BZR%V^;al9-%c2dh{S(53)wvXuV3uKw-PcA6zw0pA5b5Pb)}dh`Gdw}t}v4T#g*(*nkS z7aKt25fBnkPIC%= zU@kjvD$S3knB-hn4!~bkbwZW&D?zugJSeSAd>UPSMe{uiE#Vw3p^{p5NI}vv=Yoi7$y>6I$aM-|#C?jP;ME%oaxsu}y+@X1gB2 zZKa?9Dkvuo7BFc)5DeMvIJuG2z%B^!BE8d zkR7-A1(3|D1C3(G2?mC-Y$v#%QmMRvk<9{UJqkfndj<|~hhPeRl)cKr*qrNKh6PtPHLG0S#hHIz}T)y5XI z2drNbOC}e95;mFTT#bO}tXAVov zkF3?opUI9ev}%8+ZKvm}oZ)1{zVz;|^-0brRTtsN_18_)QacuzPr>b<*Q{ptn&1%r z#l|EMD;2m#HbrF0$g+2(T#h)$K6VEWlSkNgbQh4Q!=7A%EDo(SuPFuTflyGB5)Gldkm3BE_yP zGSL9Uoy_5jdFy?BHojEosY0K>J3KA2od4Hs)h1X@Kt1vAZ3ix|KZ1pu`JO}MCL1P@ zxlVT159_rCpxhyfLh^hQKgGMKDR|-=r%?!kq}CW74B`ba|1h@}q>cp)T7n<6XQFbJe1G~o z;+i2wz&1O)3^WRpqj0fxA2RA-TCf%Y78==@>I>aE(((6`W>*@S{Uqcuu!Ox|MG+3eL zWNV8CmBc?>^%$gy@~$aAd)1!5b$8~0w^p-W26y`>ag>iJOv6AI`k z(M&7M3^X2UM5e7YYtugWrZbxY_FXvmb@Whiw-Wo&pS&DEwHI(hK2}aR;N;x*2&1#B z3&!q=KQ4joe=d!A$?5)*@TxMwPr-2Xcu%GX0?UPkUv*sQ$ zZ2akbpT5A8(R==wKTz@8TmwrhSQC_6BtW+k5lXyv***566FUyRAdsj)RzX}aB>V#b zKO=NlA4xQptxlP&4342$T|)Lk_b%~m3Mijy!$dvblr?|Fv1$uI~fn z1A=z`(YTdC49qo{48eMQcPNMK+K9MHdGP!JS_K+(W{nz;)d=9C^uj|#WcqfOX<^iy z$mLwA`*&!NtoYxmODL+~zl%vF_?vTGOv6~3fw)DLplt^AhMP{!OT1JBCiJdOL*gwAF z4kxTAAiJiAtgCw;k9TXhP6*>m^1@wMPr@idmGY_tG1JL_;6{?IV!=mbE~efC5=y2m zCCAy)#J-xABmSq?|I`+LHgLg~6l#nJU{0JE6&ZhvgEi&!PynZaf+Y$o4G^D(5XjKO zZ)erFc*FR{+NNre0ns|&bThMdil!aG@i<8xDRZ=407R6HY-oF6Y2J{*rLWjy#~)SY@hmdP zro5b{PRnCwK(`6CIA?g`;-k5+nD%D)oNPmh7Zf>wH?A9fT-Ci32^FDGs;V_8@RIPp zgugYjjIUmWG271oMvE7&{h(Epr)dZSuE7jm{*FO$sz z%PLq(eHvFN*Dxgm(3v;iT|7wb9*lSBv60I?UGi#KL6?UV$>uHw}u+u`y>8JtJ=n55r@V& z4Yu)K&RHn~!-4ILeIn~!FCw0d)7ynQy-V$d6+qW3g4Lit1x@Qgg52lZ1_~o6Uj*TC znPr4cK^;IPQ8Tj2hX@qb@Nx?87O>h4%(#q>aHfOYtk?q$!Zhpc>X1_QFJL0_7y#nt z$0;N2LTiZXDO5BV4wJ{zUXqbUK}2b(;c9P7?ijI4RNaL1$qfgZHsFj8_EBX6TK}F0 zjoec;=Iy&_iqb3{4vFIJORCfN0wz{C@n9SjT`lOALlGYhAU8OXZY>S@HX#sjP8NgS znLcRLd;)~+JrKj8dl9F^ICW@W7Sw7x-=opai>=Bp|QRwX90ls~jFn_%W| z2*Jyo{%sf;1BBK#zw-4`pAN+hV-v*I>C@n$9%O?a1isLKSS9j%QZz*~v@{0(Y)(ER z*AZ?K50d?hLU?u+K*sM1C^*mxJXms1=gWZHc8tKk?FBvZjK4%VLX-Xa<|w z=?PzJ^nv9LA*Y`BfN{OaMV)RT@ZmLC-R^)9HBvTY$R4Q4!%xuCJ8i1CWp-9KKe zjTxm%Z1nmt`^v1h8vduVj9vA%1Uk~y-%Ycpn5~OWjvHY3rM_^mbJkv2cjKP-;qMHT ziV+;YSQ}s;KFAB0OSNmTO+u6@2d8VFx zcl5;UxeS6ANb(t`TFPYu-9ob0OHinH;B9nUWMg_+dmp$@{NT}9j_(P|=C<;2{8&CZ zSu9o}C@V_;mpjlmLQ*hg2}LXoS;oO6h&u(iYCmZ|Ypf%vA&S*78Kqy1|D^rGP z;5ZQVrhzr2;qy=Drc80j7&n zMnIHzmxT-vy7mwB+-7z+M+-|CAi_P3y83v@GjL{MNc%uiz_%=3CRl{B${$;XgG@cb zQ`&;uZstWskc{RRzG+8y1{)Gq)ioZcaDn3YJYpf?Gc(`;{aHx7RiSr0U2HMsApbn` zk(>GZlM!}xb!Oc)a4vK~?UDg#Oix$v1IWF|z!{mt()6=sHpp63813{@0R`Vo!!Hoz z^v&zFN@kPL4Y?m7_R{#C30jNW-G`^U_nR!ypqLfh)_VXX-~@`2dCHr1fBXZyOwx>Q zw^`XvJyF0)VsV_0+s2e`kOon-xX&S6K|P~k-BPJ1L59$HuJ&1zpU4Ofc25Ad>*%3y zCJ9$~j&#vcXOYZi2*b3@Tj2L#u-87&LQ2Fkt_5hj|KB0XauCzRPL60($t?zSM~pyE zlf;NuCa&x#mgygu+NYP%UqU82;u>zDZ{tv**5zTA7a1(F9a{6Hzta4VLqAV22HVlc z)~>_t67)7T|5y-K6_J|*iR!J`mjuNxc+I~J(G+lSan+^;nlqKm>($*OFl?1M%VF)6 zMBG6QtMe|xlq;AqDN|2r=t<`N4PlnGtlDBP-1+N(a6`%1=W+I1FKTA%+*Gg;%^YBS zPRTg~*6+SR!WJJP7f1chwf@`OkXC(Eiiw4SFidbP?Va<&X$8wvk0UvQ*x6(I-~!GB zorq$gkh;^$iU8L2Ov)8I8f2e3#zumEjrK8Hcug5-Q;zq-q$&DM#&poGez5CGL{rV9hL&JByqz&5L&#FoxKO-x#W$sx)M#ZmQA;G-PvZ}uY#n6st6b^2UfM9Wjsz`0%LyR} zepLzg^K>!#6FtW?lgQJli0}uG&d^s>Ot9Z6`-kM%^UySet8%yyEg5ihn>~4W)F(D| zxC^j6fC=2W)fJlwY>O24twe^{#pvk^D_|C^`9}!`M%4_r>@>v})BO|fEi;f1?`cV9 z1)f3RoEIsbROy32PYjI&V(hmaw1X6C+5qWU(ba?*mVK9IUDKl2$%Zu4smI}#^!+#S z{=cQ3JpRUb(eERIg+aCJuspc`j0z-b>ph>@oetxn1h1bXIfQ(&?MUdBNDKmow(_{N zhf|%s6CmvOj{+i?f;|khO}1zLRukTB6WdG%-o;px@-kYeuGaQ@Vcf{crxC#(A=exL z%LmMbIkxYNa4i_|DWvnn(yf7>QF*O2B2thAi7Il#5hje5olBqkr)_%1*V^%AS*|`W zlBFhtGex`Hg9r7jyI{v2(ziLuqGgej9l&PNK;L-v_xeQ;AL^=3^jM$g=>|z#e7bX| zax!l806~~X?4xMo<&k#zn;Hr2>N+gn$26xtyNbi##*Bq%PU)MBvLV>07PQ=tRB-cKfE#!o zV9h9{&;p~6lXgg`t-{_2%|wjQ%$p;1#YSlUX1nm1q=F3V^3I1{88MpPJ=icq~g4*jX#X69y>(YQ&l;eErY@;vT~t zthJ5C%7wjtX{avZu4CizA{h4ph<0^P8pv1q?DycJeD0Go)eYWPVx_?4h`@$LKE|7- z%m;wgnIFn0T%8^qMBlWU{3==?v|)|<+J(16QEHo{q*-M<6!p_nJWT>fjNz3w+n=vY z@dv)5bx68%Nh6@IH|v^}acLU2o3Dg|^5S2IvgjhEGF2(NC7TmkNBH#$15yu(%aW$+ z{mS|U)7WNBH;eI7fnEBmVVp0@^*0C;mU!imnIL>T>UoY3NIeHDB?^v_*uACFvxEl{ z``!3v)CX5%mC5o=qtR&Z&d&H^ahW-@<+f#zl>i*%x);a*3_m@k!I{eA$Y$!!F==$c z^dPAcqLndk93GA`%@7FSAqniPqy-gbI`H_Z0;$&Uu~}sZN2u`KX_MDMHqj4`C-1^w z8R@1~9&JEW4i2}DnY$^gjgpa+K&#jbGSl(znztRwfWrI$QNmW*q;a77r70tEXQ|7= zX5k~lk)JSaOGn;XdUr@^Qe{OcE{DQFTWS=VS0i%T2W}wR6E1>_s_GWl$RCVo$dE zN$>1IUa*QLW8drEN0k;5BZ!A7oRNa@w>>m2>2$LaXJyZ#O{IcVAYB%@9Hn{`<}Qhp zn)G#WPM!s$6x??{Iy*2qUWrzD*!B4Wb==2vkwQZOu2rTH_$RF-HbT(N|6QJkseL@^ z#&vZ>2RAwc@9-W!m^I{~`tblkkqTOr#U^d=qoc(rYw}HtWv*lm^LR71IfYT-faXm} zJhP$$U3T;df5;bQlHG|O-@ZL?NUicoU!`0aCi~{!fiV;!A>g^6n!H43-=?(Vq0J## z8o2Uu=y{JFVh|A_Q_zq>ZPhE9)TGgJPs=XQ7l;%kN0-7lAqmR`56hE7MSWdE`Tkvi z2QQnzV1EN^CH_90U98u&ckmF{GI=kIyRX8@1#~?iRy- zg@QotS9(zDE01cHa>Az4NEX9dlM{?5pH)o;y3GDFFJ7jqC-MT6h6}Q|_8Cu`Wg3A$MzCy-NYiBF-c}>HwIc=}MF=g7098*b} z6x*@C#`3gGjzMRk6vPlV(lm(i&buo@g-^W`KvN!psv6fEDWuhU4Z!{jeq(vP^2LRN zXmsGAnPCz+{l{-%R-5CC{T6p(%1$=NB4@NNy>FNFnkL*eMS?@37J>8O<12p zZF*GkI9Fb}8}WHY4e)&H9sj}L`W~dEHf4>ub=H@E@otlL)09kiV8My41kl3m8iPaC zQjQ}Tk0+>%sM60eZqkGh}TKZcwxQowPNJ`(XL+Z@+~^T*!DFKZUttGmMTT8>1cyQ+|(v!vv}W%Uwwj6s_C||BXu*ealaC@qfH91 zqETHbnm0(7iHokr0jr@CvdNNo{XkJE9IVHEB6oD;q7F>BtdE5<=D~QRJT&6FxyX$2 z@NrjtUGYasOEVbE^;ZBHol;9`oTK=m<(A1h>(@F#{alCW9Ocuowr&jCay)% z!=TvQNEw)bDp7AVr_|>Gpk_@*(uP6VvtvjMVS`R6rEyntg54H+P6u`RMgVG13_kt= z;1Mw2lZ?g4i?it!$yGjKc5RL8GaTjZebNPs5H)UXX9;ZlqRLwr#j zX+P}j2F8&`sT7HgKyQ?@$*EkCPVRbpmz{0Sdr%&@=0R{zQ z`&6{#^Zlrhv6VtQ;UR#IQ!yh>R!cPn$2wBnHEKkI&l%>oF)+y5dnS`3jUxL ziauAC<@(Mc1Cowwl_GDbJk?E8@4=yH`p(daCSgu@7zrERJb`@nA?rbWh>-;r$-zr7 z(rhXDaWq4?QrKL&mxOm%E@r;X(d{2I^Q)uVFI}!o+KEmM?h0j#gweYVsST2i5=EebKscx*Lx-ZU>!$7kp<$ zB0RQ;g`D1?Xs4nMTS*ux@8-S6mxjAZE(M-qRfo{;Q*@N%01e6S!}WST57OAV7IgI( zqs@^;s9E4ka~C@*E{x@G%U>HaWEurH)ezU&t`&A#pUa#lUf4xke^+E3rOw0A-8i4y zJRgSMZZ&o3E~4Jvf05y<-t-CCQt(GF`#7S^WVNL9D#~?PTwvd$^SI(S8liNA3b++o z&drdPKi-G^$4|uGPohD9m&pguL5f@@uxeswdwMbX51?Zd5DM3N|kfgeq4e|kF#jP;JVRNtgRJ#LsM~JzWSHy{SD+qz?uMagV zCoveHt9mi1B*b@YQ6-o~a*j32SG;J>m80JF##U{CzCN-QEBmU+rj_Jaxf_%>VJ_8x zFUJg6`3|;kWrx3pz|3pirAt*G5;3>`@QfkTik?c8H;Mf;(pz9l zkg_QKmRnLU(8NQHztg%lm(=2sx@So8$=2k^xEX7U5Hq*YI>g4on*3jabGu+?)WvMY zr4=FdvlmWw*P65YZu;IG&<@twMWpw<%uWhQR;MDrbq$MZD$&k^h z7u`f`F(#rd}1m5=kfZiV0#QkY_WiZ zt6SrP%g&ulPPO;_juU^Sndr7eEzi!rQb%R-82@mJi~>Y51+bx{-9f&Y6t2wMmrtTu z+%LbL0%2VgExm*+D4|6=T{7POmjGTa$?fs$fci8c|8PRK{Y;?p?$?9&AfWW{e{-M1 zwU?GMr8q=Y=B+4afe3Dm699Cha-7W*Q640+j<8tG2fJHEAnzv%!S+GDC)?yo=YS8YJ zZ~kjUwD&D@F0nT$%W7~dY`EG$QjJ&rkMX4etIr+l%oM%^(bE+u0yhkG5Hx0fTiB6@`qTzkIu~No+El=dtx5Mdd z*@NohHoR> zhfZT2Y-|*uv<3kxF`lAAYc1l|s-j!7uq+RNdmXCWBeHCF7U1{vCer6H!)>K!QQo^e zg61XV0EI6fO5s%m?Eu|NWtdFC^CbY&IrYrsjLZRcp#iHC15a-)Cv$95q1O8M1{N)R zNBJsS{h2q=rUChB65ZkWZ>kR{l-EaGAmajC@3ni3-T)u^B-xWl&j(k zW_cvv$FpSG#kNQ9@Fwa?E3HSJ1cT(RC#X~`|1n84-TU_Nv?xgxlQ4XZKj2WmBep|9 zaJ_G9evQP=Uu31<;Do?tbT+^_*^mM5f?ZU?45^yx`(VCJ!_Bkj+o8fm~de-C2|UP;t3Byn8D%I?b4&{5%afG#zBNp{k~siK*FM8 zULc(Dz46dsK+-LwoF@5Ts>D;}!28guLn*Dq?;GUyNK{^S!Qg}W2;Dex5H11}SJTV8 zBNX+$i$tN%$hdg6nYGzjY^lJYvHZ;`JNeYIesM<4t{_-5Qg*#kDDB!$((aRbxOy)- zg=9ZGHPZ;5Bpr}!PgeF64`h=h*5%jr_Ar=F5E3(X)AJIo?N+36$qf&5F$cD%r*B7s zrZUfu>)(7^pWna|q!}Z$W|Wjr6+tw)pp%SR3ScTLwsTQe$Op*N8)&==$_hUvhjKTO zRZBu}T+jk*N*|Cn-w$svZr~rJ`XF^m)mx{-?#1TBJJ_#e(D39lh&?V4wOWs;)K;e* zOS8#5)+hQtXPtu#GKwF!b8P*&)o+cKKkFN(&?BUjX?y6=(zGWrfKN1ib`Diyhh9w? zAxuWhR{HRku}{jtN1=WhL;`Ru1+aLmK6xth@=G0@@lB=88N}~CPa3+FGH|g1Vax~x z&&-V)Cl+Y~!tIY_%9Mg9fYo)1sxXIYnIU*YPgHi$nV!323vCsmrQK}WCIe-90#&jc zF2N`3|7I?uz4ELaDMNE65nZ5U)S8T<*Td29s{*p&h9MLaXej_0GJplDiKGG}tq+Krv- zvwG&HhH)Tb0A#_z&alSAC?AKiNB!=td&|Q)_ZzGNP(VwB%bdtPQH^mL7+(=PlE1-o zsRu56X@9Og<`{MbGe>%geF-i>fF;ZeF>-EB=NfnX3s{v}!1~ypzInp3AU5@@lK*$! zxHy9&k2JH}i+E9fi$8ed=GlDts~+9PRCfatrhk_RYSuO;IeE>Ket8J&;^AE6TEH{7 zYwYTMH4G7PJ~Jlc0K0?lT~r(3UdgS1<5ajqE_Z~rq_KM|m=}x-4AudMa$(y_@p^0F zSn7n%9>F!jF)|gb=Ks@)bye(5pYDrQDCG;nWSJNvc<;1WGw$pCqQWZ=e9pQ$` zS$_WXk=4vcF^okBY_2n*<4%n!32?pda!o zbh6A|nBHa=w9JR=RJ*$OjG>M;RBa4TLmt$v!7L)IWjJ3IC=Axr2xY-jRB3Dh3ZP5v zE>shTNm0XQ1~Ofg0b@{Q(l3i}-p`q14OAQm)3E8?_f1FDukN6dEVf2pG+pi)aX+)d z`{6Yh!D#sJ(wX4t+pVa?yl^`V;hH{u+(RW{25OgW_{uS8S;Jl|CT_K=M9J8^L@trWiKZt-Maq}rOabr`96pJJ z)dsERqW{^(u9SnyZu^*cizMpFD1L31aaF`Fwu0`bC1zIu7rN>0H8 z?%5#=9D)T-9&y|lss)4&^NN4~p#d_{djU)$czas%3RN2jzluXG1z+|wHn{hdtdeIo z4txjka;@I~7TKd(>|lNKV#Jf7gU?(@Z|bEDnhXJlh&Mx4G8lK9jG_ec+hGZVPx|73 zbtw#;92xd`^)qA22Z*;V`@)NV0(JmE&{kakTzt%MEF;8A#M-_<-SM$${gfz2f2TVB zv_hW<5br_yD_AN8(cVd~p~vJwV{>jp=0H5;RL= zA`!l39XB)g&XhXRHZXRV!{&msYujct7vh623T3e*rdg zXvBq|5OATg_}O~N?w0SpB7cv-sHOU~x*}0i_%3qZ_*4+TW`zqy5{CZsdca7WIzu`4 z@%wc5jrV&(XRq9~8t=X~z{#2n5p`NF}3 z@L;ppC6$_>Uo5oz@AAc03~Pm21m9mj*e);9&`dOBO5(eR%eFPSpn&yF4}m~FgWig6 zm0}#;CNB~|L*%1rz33Pg;*VJU?JNjg_`&j;3uH^-Dpa;XGtHZR=@OaAyQ9P+%f@U# z$Bn>fU!*d5m(bafTy+{Bgb6}Gz@8(mxaHBOVSXz+6#H`EjUIb}PF-IchZ4^7&clVOrE+FFsxlAU!Hpb%hK8#x_eCJtIw^v@-Np#@F6+d~QgBd` z?i_WU96Lwb67z-fr&fFjV@>e4a$~5poXH8sArmcHMB%}8j2`0o!W%*8N>TbwINwK7 z0W&IAArHC$EpgZ>HH`vxbC^Vhgb)xrdJ7BFw68^SQlG}Dpf3v zI5&Sz%H6N_z8o0^{EiB!SBExwUvuu9>6?Mz4AJ1$RBfiqVkjL9HvYPY6~R!2h0k0U z?746bCNOvqUNO*JcH8M<(UvbR23PhXazD6z`gsV{?u>~1&LxY z$O}gwK*aP39VE-Qt&wd>zZREq_3N?5|mp{zX>qRk*8OWqAoJ}ex5c4Jh2Gs zZJ;%ok>3^8KQ=~HhMdQ$_?*sl%1h{KVY>vL*fwX69fpc@hrVA2WjMIVzPmjlE0j>> zyer`XOAJ~li{79)WoR8?n1Oc`BYF*M%w(SrbQoR@@I;S*bG5SF0tS`p>`iC5Np(v| zv4$*lXPo#4s4%TDA#@meEMq1?Yn42s{1!KZqF1cKv2U}>o~#x9e1L^UhyEu{WPq)f zXqRvOl;1Yp069R$ze~1Sy3{cO{Vv^|Hv}xaU%VZ#^Lc{fNE!-+^x-?oT=5nbA%J7j zPIh6K{HKVm#N&kyUr^>7%kwB-cfl$4W+gL1$!U%4Y?=~xP8*?79nc3zTKiWpEhrx1 z4zP()Hg;0juvapTvaX5$;uoDtPoyemX(a1)lUcwXg3hDd*`p%3Q^t7UM)806A+k^q+Q&K~cMNOo z!*pgsZPl`QNA#;n-F{3<6tyH@Kl;?kJ(+aVx`kaY5+sk2HI;nt0kuo^5pE4SbvV7+ z5W1F!q}E_5NF|}EDnJF$liA;y1uTXIxt8heDycLOs?&f#e@e31Z$+(h*Q5iChR_lX}uU`q=PWAHbDe^=pwpD)jPDV>!R!sBPU+-81 zb^bqhC&z8nNBMjCsyMEDK@=^nEpoW~EWyu20uN>c@(TL9^52y@n(H z(ZAcx`m%SGYuldOqXg-{p{a<9Pd)XgMilpRVY2^9a=OC7Un06PFMQ6?LU3-m8l#~1 zJw792mWm*z=T0XNh)(=)QkWNyAVVor^c7uUd8k zK2jXt7L*@UCX(-23js{0?^=>Lp5}bn9ghH0kBa5UA-(BJMl6=?nm}I*v^%ofaYHudXbp_TYszdJPV;r>+jFGW<<$#4Wi*0J ze@!ez(X+-8hujr=Wg6vG72z+)NvC!#;WS7Nw*rXUGL9xFYF~?Y4vDjxcb517Tr^Gd z05E6!x1_s*be^jk&fTh{Ru|8$xP33pVfbk`$ak0>BXsqIw{ zn^2Y6xqQ&{=unCTZjyAzW^@irq&;3S-VQ+YkoYY2!o(kU6lIsw<<3! zv#=QsiQA^E-@t|bR`v-1%zJ{Farh98$Y~fyxZcR!{TjSi8?LCSuwCsBHDK!f4<=Fd zOKpu?gh4$I*462;+O%koO7?Ekh2dwBv>WQTFVs~YO0W8!I61+J5#KBnuPF8@P$N*V zK0EJ3PXC|PE&v0KGkr(^;w9{D-zT~bbyl1MGn=4iKEFYVHnCfb=oS>Ib%MZ)&5OO$ zXuRcVPo!~63?P*mch7gEej>hg*eLkNH=~?P)T=RyS4B=|lte|5{_{}G{t$K|le)If zF#Bv)6wy*Dw2Z$-cq3(QSFT3J-0@@4;wq8e61I1xQwSLc%x%G{7|%#)fHDB3o`52o z3LZDbMfB<#3s^!`u0rfgPyc3id9o$$_q-&1E>j0abLi*Ty4=t&JMLMv7sK{ zs)d}0b_}@>O~%zHnD4CY$=$^63>ziQqK{&qa{rZaC8L6-3=`bhtvml8T?VXjKn82` zU`!a103SU?G3BfjCHozm1b|vtt8rAmR2iqLS*`okP1dPi6|zN?*gLJBC~~9g9ztj4 z6mz74dr$3?BCK(0bMMv6R9-rgGsS)|>_Z)H&+P*dw_m7dbX~V+FdptN^m94?(zqIQ zbPa6_qT7k#Yi{$avqfSNsuT84(rO2R<6A9{j2LN|;utJ!IY&wojpu7nf{p>WTIMfk zQFZvqzw+Ez3V2er@+*-I-i6Bt_ErCl%n7MnCR(*dG~+1&#FMdsfx|8BnCLcgJV;9@ z$nZtok2m!Vno@_flw&xfjND5i$=q;&D`0I;)~IYq6YG7gkU-F`X~@bLJWj_eHab^u zr4;B80vhe-)d+Lm*5MPRy^qBx*PObR@ybka(1qqo-se4^LTK1cW<*Q0{;K~6Lm_RT z;Ejd<>kJu6g>dZU@?~}|dk3pNPdSlaVs4(I6<2qLIn!3(GvZK;=Nhb!$lQi*oSdgE)KdK8}`+M7@Z2))dH2dPL}yC zCOirP*NH2Mq$-tpTN~gpxVDI1LtzK4|L>9SCm zAq2x#L(Om>7V67}tfhe1b^&Z`t?Y#+FSO)~V+mOqL(f`oONLQ6q*y*MQ1ODlR~3lm3Mmv~`fV3GUDSGG>E-4@P&zG=@k0TxDlY4vb_I80VEd8%M zHBG_4d5iAoPYiri8eq<3#%mN{^AiRJ78^ zJ?{MKhREnz%+tCNdQgn=@uii0B4;TPYnV@~Pb;fj-domx^JQN7bE`~thH^B2 zH*(wfBTrb9AjO@TplS;J<(Lahy(3&Sxq?Nw8^hqr096Z{A%7nmO`}E_2U0p9I&_aScDPGD&k7}* ze=uM0M>P^Xl;I#{o4&Nh_k;YE@bb4tcA#Rbs$oUI`|D5!DvX@$zd%n&5vthkpc_d{ ztD7|aDXVCY!gO5dG^S@=vvvI%B6aj1Uje}x^s_NcI57AQ_7&**?Z84_cT)nH`WPTB zk&@MggCsfE?RGtU$6w(jWu+T65hddh4-x9>FPvZ;j4Y?t1YPzQKg*gm$5tCis1HNU z@s7~z+%L}^irfs``A}$ZSCH`lNOx(8U-$MxqT+F|8-Hb-9h?FLj)ju&di_9QjZ!~h zJye){xq`k3I*Vm|=-MC70VO=>HRaX#rC#*PLO{Sht#>&CXuud$!w9pPF1}Fbv0{nh zMCmZm0-A}~;BP2i8;aNG{~xsG*qF?;c*@bc&QsHnV`l>=uIJkg4^1LX?&r`t(J&*a!pmb;(+)#I2p$Jd%`JCLn%epw5N(#|ij0)H~;& zBR6eXA^QtFp3Ponswgfz)7i;0^q$y~l|94?F=6kHM8KC#@E9es+Y3l;|K+Bn*C*~Q zmmsR#JLl2n<0ulIv^Q*9*tY0rB@%Nti02&tquXv&Zr`oRzAnEQ+5++#Ja(!_bkiQD zInKt5eVo4(a5ZbV@%{vEtfv(Y7Q$oWMA8669WpapM7e)tGO*IlEG`or0mp}X7haTE zC*?A1#Ac_Kj`krY*y?txkDY}r3G3OnEv&wn&3R0jS{R00@U8c|!>J6gcft2O_@bxQ zQ^Va&wE9nkV;>PGcHNQP;Fk7r5~bbp!0#8PZemhZmJzpdDxsL3MUogHi_Rd4_tIMw zHAg_{BZ>@05K`022d%w9l2Fd_G#wp_Mj@AjU9}@I9F|*Jx0AdlR9fkC+3D4X8 zNh3>fnx`aXronvF4Nw9)HDmI>Nx2xPP<809T%M~st82@^X!m$t-!hZif&tCh9X`_N z^;Ju+;<2ejsj~OQNH6Z_dHJ4r_1)9E@Vz7GFquB2VCJ6Gf2GEu0~=NiF{CRO;^m|> zX_a0jPWMw8SfZlaM=-tGp*t{lY_1q$*bvHfR)J|CjfFnsZv|U`Qrk`k`q&M;PqpTb z;y9MoC+#mdr2*524l`((ev}f;(fil=z>XLO)$mm3sDZ6CCyVJe^#rtZGp_j07w(Uf zNAem4Lw0bWjq^rc%%Rr9c#36Ued0kimaK03Y_ql%0pF3J3?dvA^(;&2(RN1A%E9+v zJ7f)~@?+O~?UkNj$}wy(i`E^nI$|5jAK}5xiIC6$X51gX6VuS~CnvoaYHM9<|HoH& z>={e;fhu*2$rm~8nU}LaXX}G^`1{+~CCe&jgU!RhaH7`Hq~%lm8S-JI)ABP|P#h6y z+=wWU!n-)~kT*aU%{1t(Y7^tKhf56R?4}hi@=o}0DJywMt?mzNb_Z!Ei(X zk*k=VrVJM=d#NCH*~tA3{}C6Yra_)*=?WO?&!lrqsX@O19qo7kcqPbMSg4W+8aIw7 zO}6e}YLWi72{l~+O?Y_G(UD}4g@O4%6p?Y3q~xAxm%6a$3Z+=+mnzC7CojO;lcB*L ziYfhFAPZc(u4eLX*T=BSaUo*_s8~=_^ z!wEs@QqZrEWdvk@5fi8@zTwCVUbzUZ;3YhXZO}0PHGlRJL+$~}ed8R6%V_$pAN?l| zTU4}sT?rUvBfHQLnxhMAx1;RUXHPP_-hzPWoNw)BDJF(e_DUho#QVw|Q+GIXcsUOX zVdG>d`~*@s7m5i7bKuFk`{)fDMymk`OYjW-zKEH$%70w1(>iev643b3r4M?`FVI~m zrWl8Ed%L&dA$rN?P?Q)i#T9WFs>|z20B5UsFnrmzC_E3`ga;<@7*Ae38hr91 zS{rSd%vwmmSw`;7V}(ab$K|fwla;g4VK`!y{grG(gqDs;Gat$i)a4Yk$UA(qO%9#aJP(zDdcNl9O?wxsW{I=B_HRXK$qt`j2)aO;kdy zq(Z?(d1ii?Xq^Bn76uUBl5RZWh&Zf{86Ly!b8I%YKr%-J!lLjA>fWv`eO8!mJk8@~aM_^2?ahs_A;T*qedmfAk5; ze!u5ua8X^Onv-SzTz&Wb@?Xk&^8%Sa%Q!St#P+@mgzHmBcS=T&^=>%!j*eAt(=C}C zQq?fX-xjvyF)>o^mE`U@7f7JLJ=Lj;13;mO*=X_yU{B;e+xL~97V&AyPc>> z+X{+we5YjG@iFD2}=B1}@n#4{+3w6qsJBI`g_Q6FJsyZgZ# zc;A;$a~Jf7RJM(dUa+SRTZr6+#)5d|eGMFf8YOukT+3s+q_7c6tDxlTbXa83rLY^= zgVn;YhhJuf)u+a6MGl+?ZraG26o&{bUWT1390Sd#4nQ&Yx+FlsAZLvl68BR;-rrhL zoC&QCu*78M_n`Ww&}0_QHN6#ztZP&r))};@j86L{gWhkfetmpnMFMr_bpM6v(uENA z6}}PV&X56aS|UsuG!#q zZl_vvlbu^c(1)<1hMjo2xMh;*!a^!Ys@7r@Ota2k<=*JpbyP41M-pPPwG_(b`_%7O zyhF%ANrtw9Cc*EqLa4-?|DzCPo6dhS{ zj(-BIQW;lmuEACwZJ(5HKljZm6{kRJHm9^c8bjr=qeT772fC;2KI%A^F&kY|Ov|ki z)97Q1-j~3=nOuoy8Z<&$$oQ1lT3hIHx~()IFEz8uZ%OW z>3V=4t)BmUfrdtcmciX29BPdK$P!)8u0stvZD1|@)Jl_)D}NFS4PdpUeAWfswBnN{K>>Bt2{iTL7bzOIgc^{4T>|+g z49rPFrq+EY2R~qhbS{Hd<8Yb&3T=zW8WWPEUq3r#AR||>w1UbAYCB7DR%TM+ZR<%@J8=7V&{$gOMGi2zHcP%X$pO0DUmFb%EBwqbg22h^ z4BMOK*rZfp0i8bHKlS0+wTH~3!!rTmMxXAPtT3vf_1$xm6Vy)L0&o+j8wJW=EH%rY z)ZKTN5SHpMn&ekxe&>GUiOaEX{ola#R$Hlg9Wu)OU5&4k8wL(mR`ip1f{auOx3p%s zx8{h4wTvaHD{L?1C*S;RMeB~iz%|A{)^MJHJkX$wcC`6lr(a&US=?s|&dQm?# z&X*W3Ht_IJ>J*326x|O9hSL)P2EQKsEuNJZ1wt@aK6O$ah#Qiql@MqPc)L!)p~};0CAJ%iKpgjBQ*x3&Bl# zp8WsYHTvSvv+GaZi%Oz0@dcR07_L;A;CLF6W@D%ZTnGUIHqt%B2Y1!yM`CYC4QqZa zvM=w~0Vh5H{bZWC+KU&1BQ7pdV1Gjj7|1@#1y;`Rswr`}`e}niq18o*5KaK=Nf{U^ zkFV7^7@`v40MNggyy4|FRZRuJlQ0f(ZrZgxnX?A)syVSEuFo1m`)~;J_2R&_iM!y{ z3DT(K3X2WNJXO<^{m7q}y1;t43 zmI4imx#r>qiz5$dH>FiX;04k}4~`(=@C?d`zs)cgo-^hZwEa2v5pUV}2gsbV@1uZc zNJ*{ZzPBU->qJ8%vK>^x1erStem5`$*GCD>rr4zC4FU$yEtU5-NGMc_+AUA&y0R|& z5*38&;j=p?(EK_#T=IL=`v(0}O`b44Eoan(n2Uenxx9nL27AE}?ap%I+z)^S8xyBY z6mZ~(Ky1^VP0|)CX$j~X)U0rC417aV-7xM@Bc(lSJS~goGQ7 z@#+bj(ZOFXQ9v3-S9&(L(xeOQA*QXZ7<6OcekqB z9=InB6MQI(cT+JsgTg2okcB+<7i3;E-=*7>77NnqNM`Px;)pt!_`rvKbGX#;9(0Z7QFJv^2M7dqR>KX{Wk%Z*103R6+wfl-k7>S`IC?y`x!JMXECPUIo+v_77i z*~?tLg6HUbtA4it1AtDsBvvHbfh1IRT|Oz95)Xywfb5U9yN=k z>=0DWqZc={L-#F=HjHev1b(}z?^@KGPy2JtBTfq;cM;jMPHpn_fS;P}(RbfA#xA@; zRB@rV^~KSevKV3~%>q6J!y0b`pg|gw62R?8d*V^ND#FI2Q1wcpqXAkcdGder{0NfkPnmyxpu#8* zj53S70hoAr(_>e~UW9&Q(nNFh7{U^~wV=&GbtIeURcF|tXEBOIzj;I$qX17@qC9J? zlG_Tm=+c9LW&WP4S~H4%A)l@^6|PYHE4$?y-V)_`2=HTyOkiNL>l%#&WBK&))TLuc zS}5f*+y&1pu@33?il4$s_t3PjwVNh78(nK;{Y5yaM(H4rkuMhpb zjP4e<=k;cq{2_8bf&>zdB`EG+p|hP*EYrZ9BSx6Q&iT7A`_}XsF6f-y*Z)+LSOi)- zfA>jStE>(Sed0f^f|~NM%MItkX%!(2giyWf-9hIw&$~szl4!BoF*F}c{o1gt$sV`f z=moCk`bJ6_nH(?#C542S;>B&2oUDK4Y)hCUl`Tns z_v?Um;v$bK&#Tcgc`uo?njCO#M;?hVel@*~@;?n#z&z?|NTVd$1t0qXI+RuX_U76B zWS@p0Qtv}RA~U*US*Qw8Ua!H03L1?c1GrGs==46%aD0ROt(`EgY~4hVr7{p6Xy1yo zN%)4N*d-s)A{dco6Ls4iMs~2IQ_jA<3(hm|po)m7$@Oml`Vw*+Kpn5@SUq-<)?)AA ziqeu7d=zOj`4NeWL_s(;i4N+fB@=iUpRHpo9o={r<5w5sDMKH^4xTGTc!OBJoR?sWm(6&j#)yk3{vDpYuJ!H+cd$nP3Z~XV#VeZp z^22=&gUdOLeoy<(%_U{M>cnbC) zW!FVBStvQYH!gJV<^!za@`nQb#;Fj4D^R4-5{qXtIQg)gT(WjsdusN2Y|O+;Wvz`U z*yrE@1A!Hgnvw3|6k6ZdES$0cyk(&A&|`E|8>z@u0v8!)q`!Ciq_I36AR)3a3w@ZB zEX9Mf$y_;ejK_)6^dFLBCS*5?XS0f~m3JE79z%%t_eAZ~2I7Q2wLc8_cyv;kIW3g+ z_&-4K>ku?&@1D?2qU-J2Kdz2S2t{6I)At$bi-4AEyZ{)D4$XJtb}J$qUwe1+={0P> z2eDIAk{GQ^=K;KQ{amdZ1O!(w_#J2#pWTPF;~P#=|oSCu!9Q==$_<#3O8+WO)CQOrv-)llLmHJ0Wy%{XyU|D9c=(; zNN$SWSGZ^2hI{(^>4_$WOWq+KA2|7V>*+M}1w<9S_#oi-4^i*T4-Wn8+Vx0NVbxVk zIZ0AU&$GbcNl~Mjivw*C+jzR@Zr^uUpBwcGSFW047>hHvD1-+~^XiLEdGi?gL0A6g z$4i8hecm9q6mPmo;+bRI=3&JL6oC@hs!UH} zc*t|PFo3AgY2%8_U`2r}7 z1rPe+swdp&4()B8d)3G=NsHwAJ z{s5O|O~Oy1ISPmd^Bekk-{#U2Dg&BZZK zV1x%7&MmzKRQH*U|NM>su(=vk1?2#a>JK;Vuh_x|a96g?`uLogP2V1h*s-ysni{qD z4i|V@^jP^+ZEynS4WG)9uJ*%#aERTA!*v`L-1|c|_vUOgTT2r+;#J=d;^b=P%0czD z2?ADw?4?`X@Ta%zhjU8@|yA3X?X=;{etGMeWH zI|$u7=<(~*fGR7bdU3H=sjN(9x%rxP*HLHf5kkNM8ERJeG!!a$#l=d5KzOZ*_F@BNirk`~ncM3-L<}H<6HdXlT7#Ix%cwW?B#g#A|;M zsW2zWgs`%_Lfs56h{}X#q6*6ZJw!dldbIai6FX}h-PI*JFj5_Kl zszYC+n_-T|dpum%a4GYdeJH^cdiQAiv4wi36f1$4igVM=_v}*Wu(P&)m1Q%*rI82r z0a=Q0Obb4Q6TsLc&V(AG8jS*c9v1?zOVZ>|{+GM{koH2a zl15(Jj>TrZbjy%KVj(JDDwwou>tkdTUE~l>yK%5Y^5>F7 z_%~034tva!!964R)Ktu;wQEO3VsHwVLt&Qwd;cQ!!?hkmTR(P+-nHbd-@8=blheTI zJb)~rq%Dw(@g*45V|2O+*s!1@NKu9D+U7p-(`Wn3emMZJ^iU9-sRIKiN)@BpOnm!$ zs9&|wW^h4S{9BCC&5vHFWuf}EF9$R=fx1Wv%-r4)kP|=ca%G_FQG}%L7TkbzNU+FNROaWS_3afdgmxlAu*q!$qz7S*AjwR0t4&F zt6C^#04Q$1%v)dFe-oKY=ULZHaO+>U!6%%wgTaZylY8fvj5~b7oDNgHRY&?6HmOfQ z6gI8a&>U|$$PE;vChg?o$lITqi{ca_6S?TI2Gp{R4WZm8;g~cpEt}dsX5b}darVwv zNSJ?D-#03hhRe^)QwKFtSI)`u(O05CWc9w^f@Fy}Ez!ut8&3e1pn=kqdS#nb_!ETN z9yt|L5FN&Us;(t*S8bHK0xIWsk4G;@-u<$F82+T>RhEvN?)fl`2_}{1T^?f{{#mc8 zk@y3OSHG-rxRc6rW%sQ^a#)D}9`{;37hq{{?6RJOt7XCl#_Q{ca$eLNIpG-F9Fsg*{<%n5XZ5Q~4 zLuY=rqV*PsZqX)|$`5Z|a_`hV>MA8-LD#X8$NtPy3s;)63Rb%WIl98dS$Q2xuVh~J zQgak*CUY5_qDsMGg{*|YG3b1o=qEHWCSh47IDf=t?gFlcI%x0wA{ChmY#~fC4m#>Y zxK-Z9BN)QbCK+dbi_82)0IKNybhD8l&SDJB9i~`D3$>$)w>Kpssgj%Edk`c2-?(m< z0AUr*CEo6Cw<7ZwLEZD3A~kyjpJT|l%#f{I5W3txNqYjrbeTB!5-K8Ly$_L;&QWR# z&^LXH()0pkQAHm^1eIGp@4D77%gt*%8jPdM2FB?Y396|E{uJu~pIp#tQ{8YEl-}u>M znTyg5A;mY#>c>j7T?Qi)?Za0qi2XQ>4@O9yLG1_aX!!OL0~$j`(Rcp$>Rq zI|2walZDeB9Dfv1GWb|*&lCfRwdXp5Rm)a`09K{+)BISq<8h+iI}Rthu=X(WibRGyaMDh;BQljypAFRH=GYgt*k$IlM)^u`>2dL%7tm{{Sv z5ZHpSGM2FRzVJ$!n;5zWZ9N2>!vtdH|BQAwR zFPJ|~x(bF_9=D~1f!tz~LA=@hVw(&M#wP!jY~~WG!#Id_?H8jAd*h<<)p-A~6l@F7 z)wOoLNe%{Sm>_5|7WI>c1}2K(t2mtDx3QoN>$UvLurho>(oqA~>n?1k3UAcidUD*A zt^LL(2wFuQ>T9TFX;sA!!x->P8B+p8h)wyP^uJMUGR-zt-l9p)WWzuGSdqNdR_>hc z9wzBET?ULS*xxW@Kq`sWNQb|7f6bg^U5VC?m{(Rht`NpvhA**_&f80~`%lBESIWA| zOHQP+0?9vwWTqOxW@`_;2TsNa>-H}Kc7OIt@DcTp^Xx=8pZpA( z9A=YC;N{bP*jC-jE4_aY4rx}F)djY9(KXRgcJhSq1LW~2=#eR@g>arv)fK}N0VX-C z`czJ%E5TriTX;T>@_(|U+)QfAMSS^IbYAWqOEb=kW5iRTwJ=rLzWuO#E`a#4?P#EX z4Er=RMnpWj!jeOCO5KiDwab%Hbp3{^_E1%9q?%PQxny`0<f*+pJu1`%KB%^hzRYOo1f)eN2m6!o0RUebuHo+0AjX`S2#Lx3Uas-U z8K{5tUO!My8P&L)eMny2;EOeiU~^m~&wC8$Lz-1gf|>Wu zB8+SXF|dCAK2nk0eGmC<^J zEbO_9kdtBYe+vLp{THtuN~@ecc+272t7(>9x{tUzbK|ziTo{$nebH4&0Ie3Z9IOCuyga#1uoakfCe2MJ?=}3}`Kq7D!YkB}p zDzbA3q5b0DIT|oW`rl2=A^Y!(;7bk)Ph3#G{id|=j%h+&PcBNG8YwfyLa|LVJQ)B0 z7;X53j5leZ$$Y2y!d_!}+`#lOh=4LBUR#^-lu}0-5om<&%TK_XKW-P2p>g8~2 z#pmk(B0YMfzk4gu$%*YQz!L$S(;=r(Jd}l#(8V)edZngUR%MgFL`vzWFw#d;R-ZuBmnV`$69LRdK zTX%Z-Y*x?uoeP-*7an1`Kux4yAasuYo`U}Eh4*S?vY!S~WH|J=z-8SRbdX0kC z<7ebQ#xa&^!DG^(Au-RGl)%_NprU-^_xO$AYfxyx?M^$V8R>`8WtB!xtScCD_L8x9OGVU4Fc?tnI%xSNMN0N0J*DtOT*HyhT4s?f{#yumV{ zyI1cpZsrVYs3jo1i^70-S(@!rUarmT@Fv>NR-85F%nWkU{IKON@1?<+J+P~(JaGJW zzz|J-QWEG!IX{oaA1#AaIIoZi`*aHncVdI-DlGMNFaZ0@8AfuYTgTJ4*cwqn)z~@BNwGnN4)={_*`ztLZl&PE*IMriA#L~e6sK6N)g%0UL*Ao? z+|rs1B8NiAOU0xathU-NQ>o2D!IV_Np%} zuehW;us9BvjJ2j5Dp4QoPGw^piv9)(xy^tFGJ*mjpF&e!Q?NzVl^VtXH6I`OK#{tB z>Cl2r*N-O12xDbvOYf{u{}3S07f%!euQ1HdCpNusSY>R{Q%f2R13k!0H^3j*+g*1V zSK||W&>S=2qoht)=odeVsz(5A;k759DYHsw^ygK_&Bji=+MpD0bb#!^t_><`L(r1C zgd7z|hL{z;;KrzziTRTk5Qj+eD?_!&oAXlydyo>7%=N|Yxzy!J$+SA%wNDd(3&diy z(VmBjisp;9n(g*~ZZ35ECs;C@%A@3~L+N=|t$(ECS)LX!>}A!%AA8gZKucKATQMu=uU z6>IiKslfMIL*LZ~(K%s3X+k90*am>YiL-VQFQjf~BWoUKMs*W3H#i^jJtsIl*hYcJ z9ggeZu~`%{>^mE#GaRfK8?tXrF2duT*bY=x{QMw(BU-qb0N|_42O2rMP*L%`j%q-= zFh=8;ts=EA>L_H6&c38-IC;Ip|9&f3;^hQ>%`Fae7v#n;=2~YfFU>nfFIQ!W7;^DO z8OIIUZ&64NGVV4ke6j~il-C5al?*XG&~b)O7qHs808WI4axx(FAifC!v5HkK_u3g} znra-pMNOPZwHkJ7yLssfZ&fj~F!p!AEgx$S+DZ{4?auGN^s0t@2zmm! zQxj|S?{`HJCgN)A{6{gV4(^5Xw__-2yw-O{qhV~~z*B!=aQ|{aO4ljxh7W)38Pn_= zY5Z61Pl2HO9#H~KlPkaeHYE?7=w1x;z8OqEUrm&%!#hdwX~$cI2d2#E)BT3MC3(b_ zX*)PY!#2}VY`2Xh5qH}Pe;=mkcsnbAo(DdbQw1jq(1KAy{x7|1PqQx;Ltoy1q>L?v zG7bD=H|dQ{jsvE|zN5r_3!((9ZW^zLaw27j3XzOTI^A#-K0ZJ|5jg<Jx6gz6*`yg8q20|iqYw6_J*fewiC?}YX9Jvr`cs=9Id1fT4 z**tf$(bp&SxUI_}J}sPkVELT)8jNs}MV^ulJAS-JG#hXK^;2oTHmke~BZnZ0x*yq) zKE8KA?60(I(uFAZKQ3}wbeZ9fr;2Voeam}Ha^}OXEz>X_y$6&^b!ZU0+CP)q#kO2r z_?WA8b3oDSav*lxTZ4w5anXQu#Iy;Bs_j5wIQr|8#oP`#TM;6Ml5ijlK> zdeio|et&StDX5zb&GYf}zE0!#dZ%$X26f~PfzA~3Wh9Sy+18GwHR>fesU7m}!5 z+xPL2-)=p_&xalkJ!V~S-l-qUo(svxwVW{@1 z{?3c2S|$gRl#_yQwB@8|>ThOg^~X4#El=s&jYiqBdJ#qtMa>tofe~_eN0<4CTS2bu z5OLt;n*TJ=xhXVjWj%4~5;UGPo*&AAgJJ zZdph3$pzzUW;ZP-(z@pjWm`)D{{E5K&?g}-MsZRBY2EaL2Y~T{=U`~1G8gP&|55R?1@5njN{`?iM}V;lpw5WS<$o< zFq1cE-YcDwMel(AO8_^{Rkfnbh-tdhY4BhC(#v~YI)$?eq10!@vnn9kYIennUZ44D z!l#u8fi$FLlp-6wVgKyD^&(cM9$DfioaX6Q$+U>c0k|JVE=c`SZss8r|63vhn(~|t zkvep+_S5A#_-Q@?8KM3GQ297$t?fr=*});kMD&>=$auJ_k@#rHq}1%Y6yyNbHg{8E zZ-$d-+RwPb1GZ?%rB~A7hrK^DZlNB)*0^Tdsl=R!aYFrM;mLXuc@)O}qJ9v3IVea+ zV(~=yR9^+f5ACl-^=5cR1YIL-+wFST7Le8bVO6vl6e~Kc7Bl36#);E6&6qu%B7<50 zCP3y)VWZGi6I|Tl1U}n82wE>o?l?>&AyXo7P{KaQ1b2AEgMY!0Jb#kC5uvuiok$=HLC?rXXlWB96E9O zUF*26$^+G)UOWkDk-{>%p@!Jyh|2&wK*YZlW&#gkprh=1(KeVxm^IML5`S=YVL2Tp z{KrIDS&@g$RobxtTm69MvGb)_iBSQ0Cw9kQ4hnkZjU{Pi>DQ5}w-g`0zpATVAyx!2Cse{pHXiI?k!H3LYXe0qE8%-nN)N7?J`Drqd`+s!R^rPZ7v5A zK3^x}>@T~FbTsXav^?HBSPs@OMD)Z7`}YLD7YVArb#VUB?K|sr33R#^=;rB~HnQMO zW9vBUJrLW34WhP)Gxa7PYs{zXI8%Z`uoWwop0X|D|#5j<$c#Pk}Q>h(xo-?iEOZB(Pa9~2~YMqgwc6BKhQ$XZw1xq?0)hX?qS`}1fWhZjaI}mf@FUo>!A`IsJUsPsUp*iE%*Hu zTQDkHg4vwLukyw<=+PyU?wq70Qt~!o{^q8WFx`RRP)jE zFQ`4+VXn)JBe?`Ms#)!FWab*ryp|;RO+0($k!Ace;-&aSI}m01YxnIC&L~r{lC3Mx z8cSH&<6J$Z{l)rX5&+b#iWmY7vj2SD<3nwvdWa6GwL{1y24On>6{u_D-W)c`IN)HL zKzKKUSJTsIc`c^)n39rICuPRkBlnMFFl|61Jp5gezRDzEa-_g6+w=Me zft^g`B@@1~)vVpm<)*sW-e5s~?9KqfEfg&%4vu78DClnZXejtpEDD@@~j$pH| z3Ne!h85hdnBYVV}EWg;Nh>J`~rEhTJSM5`tlWxE`J8eDa8k7`|YhTK01J`}I~h zSO+Z({RV{o2a4;yC2JR35H9T{s>C^jlgIV8pq?%(5I47QTY?LPbe2h>& z!XQoWr%2Gmjw-B&cIFj@1KPN#MVOkAr;)9AvbUdHBU@vP{RVVlTBMF|pM-!X`fn^} z0@tb~K#xh`o5!^Pv=@y$RIApSYc!%r-Zqck>tQ{-P$DJ95ypP=*5aTquTgg@Y$SZj zjroyk(gGCzL@5YU+8SY-U#ipEz4Z1DqR+&{!5*qyeqj+8R?5)N4*TVDOnQsatqy)Y zlcCF|R|z_nP&qi8jLhO(p1*M#C#CgaAHHD9C&H#1Nbcn1abW z%D?D1vreVRPRV^i&m)p(Y7U?4CodV}^#J-7#foD)>FZ=kyc>~%5_XVDE;WWU9S8`Q z4Z;~UdvuKW>h2KZjdb!DMv)?StFs5qmcZWdIYI_W>sqvFd}jRizmH(-tmdJ`?I~tk zkcBMND$={oX}OfV$7Il^LFfC`6DIpKwDyyDfl#l2zOLU*X%F!CZD?Wll`f96=C`E&#o_QbXFHC{ZEp#N2ykcE2 zSo19tD|yzB2r^iZ&N3rY7KlNPWi$d+H?>79$Fn2xWv3#FQ*yZU027zm$ znU8gZ6aO65*aIHWP4+f(Mv`N=L)C z$#8Vewv=>#Q!8n`JrY!&($}LDSx$(?Z&o|pc!i!H2n~fJ`+cIV-Lh+oollvJ9pie63)@dyopX^XS-S%;2ISLOu^&)F<=xii*`qgj^Dx7O^$$ zh&=7uKBZJyjY%m=*Ue=>5aF_#OYLqiuM7IyFt?CjmTllc{B2kqYs|nk!N;w`gC4QR z;5+6YY=@gQLr~)apt8qyUa(*3a!`KNWdh&vK$4fT=y6AW83lRiaC5a=(a&JoAa75@ zIRX0jxgqh!xEF4Kj?j4l*PNur1OTnjq6A{M&+^t)jHcKu^>*V3jx%bz(q{$}4tjgs zNmp5>lXS8}C9MCVCo?^^slhE$*bH2~H`r_~O8@@zYCW3==!5Iws{VI}6!fSLtt zJ_4T6@XCW<*Ob?3^sKZ1)0Q|$Sf8;Ch&c^#sqt29DlU?6yp zLk-F7Mc5V2I$PSgUo3f_Z!Jd}J%cPJ%bPX}mlgvAl*+y z2t)Dt?FQP~JY8?|a;1eLxzc=t_&<@o`VC}B{i^~k==u?1wY=0~f)nGqC?^&luEfUy zja2XjM?ewCI^aetI{{|~ z*ypS}@l~Z{VzKWh_hrVpDTcFJc4{29V9Ba09R7l$Ot$rcmPUd-MzB?ZG*V`Wg8G(0 zqjrWt*LBHNchU`uuDc6tet!`WzZvC2gZ6&e7t8&ahV1^7K8r!XZPzz>i0TNM|up^B>>P`+zj#HO_vM$aJB={bIB;4=( zn|S+xdX;Vf*#8g4t)aY7U>rd+)jHlkD4#Er!X~h*)Eu*eF$7Tb` zrC3`dJs-aMsRQCC(29#eQ{*r?#n zL}MMSA!^V~g#TMWGF%foJ>!}_AtwUs;~T7C4*+l+zPh?e;EnuNIO3 zV-lo8_U{b9&??bO{P9ltLnlNXT7slDf4~{M&ILvh?-t!rUJ*l3Zz{JS6Ta(O3@SnM zC|E>Q{v58Vi>ne!QF9e4``(wMK227ubopZs z7}8#5jtF?^gnqZj6p6QOq5hAfvMcWzLxaW!jusQWi1PadoYW_d%^wkF{RUj%CWS0g zxeYIUFPZNhpYjaaa+Up5xiBy(luZ0|{o2k0S*O_~bq8o;AEnGHXzz_z)=zS9++5|; z?A{8Y_E6NAR`*GYypTsrqzW>ug28w*P?qdT%01C7DIAgfZYXd-?EfyHHBEG6ghCk~ z0xoTXC@#f3#5GeX%kr?H9vfAp!HFuSE>5>LSS?Cfbgp_?$rnbh%CT&e+vvv|H>LqZ zXcWHAZ1u$|;LMTXmR6dc?u#NWtqECpMMkTr!HL!zO(P4$#Q0h$@7bHuSKb;Lh+LOp zT!=6O{Ay%?LF6;wLu#Y66HTUiU$-*UYn8;;pAg~{%sbQwj+o6uVb}z1H)|X>Q3+_; zU>AO<-0X65JUi?x^>K!T2c2gaRiG{Kr+LDb7|v(^7gCr0SXZ_fun1HUm6r&|2KB>} zSP)}Wj;l%{)qXJ%S$zb7=3@HewbWmfEJmNYLq#=rHr_xLpzEf0^L9V@p`eIjM<8?~ zw0V5?r)Q;(@^Lg8gE@p}ranPo`v%70b9IW zK4uDIV3M$`xG2KFd`W#+DY@NUva@|wZ*jW~weHdBC?wJ7$x?3X?Tw88Ga|yNoXj7I zaPTY_a^XvI=}mRfO#x!-q-nu%eWYT3WUQ(AvK$^m_G9ZUMjtRHDKm>Hb~jq?T2Z1D zerl+ihBAsU+pEjmuzu*EJ6+6T1YYCHer?Ht^h=A$@ zmjleayPj^$tiA2@c+<+7$t@C@zrww8(UVZRvA1VirO_t22tpoIA+iV`W5c_-ao>|m zZT-SuUc-o-Sb52xQJjbX>AjBiGx#GU+kg=&GOh&C_5yXT$fN-bSKtO8CRw%wpIc8( zbNS@7==So#qeXZCMh52yP$Wd%;H6-*ZIn1?$_%OdS@BGixyLg|t>lNOYJ74Wyy;Wb zE}$3=E^scq7wUeQ}Xvo&)%% zOuKurDfipVe_U)dbkDK9bznRziWP;#=e!JJWq#8O!ZdXB`5e5@sgcV&T)qL#2LZi% ziH>b^jy?*ZBFOGaPCIBcP8{x*@pwt2A1_NkQGgpgf3WS_4W?1+nR;D^CZNDJRo;tB zdWK6gd+duLs{~w+3H0h=D>L^;->!shf+rL5oo^%$iK!2~W;`T?o!MStTHlvt#AAKW z&I9V1vQ3k!PBcv^Qc-o`LpeY3nE3FshP~!YYKbEO=BcNcFaoDS+eKpXCCfwsL=+l> z3^MDf%^sn2AL4B2vxjUMa{4Hx@b_}MfnOUhDQbmyKsWVsc%ii`Hj_OBEn+@m=Z<}f zdfVPczMQJzgYBy=2$o0r{E`tenu7;P=0lc+)h(Ch-oT@Yr#!3+hJJ9fT zK-bBPZhn+MLu(RlPx0fn00R+ncwc5=#(u-X!c@{UFf2Kh9Rs}d(IbB;GCjp)pBB5? z{M`x6@G~bKe z7rRWPd9e|<27AO>8VDU))TSLqIzL;8Vg_x|HoQt??DsIFqxi4V#7uf{cdZ#cmdUaah+*fR~TDQDg3RA97HV?(# z@)GHKfzofUoeX24JtK_u#y?5mYGYJvk$M@NdC5*p!1~MaT+HM`2HH4m9jS|As^OFB zfLN4V>bK5A_|O`!%Aq)o14Yr$xu|-A=wkQJ_o8NH4Nbn#xj8%D_Ny$;rdjJe4--?)t zNJO}h^8}d9UxgpKf=xp7o_T|K@1k;`&Ya{Khv%$!+8SdzS`}dqF3N8L5a<9d&da#$ zw1=2`Ai!9#uH{yDnJYyTUROEmu2diPU3o}F7JCsy?KzkfxQj3zSwVeodZ(TM#4tsE zon!{NC!z6rI3f{Z-?uGKgY3Q4*1uq4H)=qPRI_$)z?usG7sy#VUF-F*T-qpBcDm!G z0^%v;qPQX#GG9GP{Lq^>f7GE0hezBsDcDB%H*AG~lJm;?!41>6X-L|ObGEV2i9#i` z4f76y+p)%v_RoBoV&USd=VHST953X=Stio5va+$l|GLdtZn{I0na98DLSIrbV&;O$ znq?{TgaS3Q^=OJ8PR+tpf1at??UR}U-KDzTAPuGJEvHmh?j!BvDDe`eZLvUR0lf}8 zUMs661{qviUZ+vuO(_nWb3lC&o>A~%Y|~3Kl@Bbw`ZF>RfX6t;o%Cislt&4E5SrVr>}Q2!31qwpS36@&W({IF`v9-*rd z)RYE@o4ryWA~hvxK*!g0{Q1zywwppAm3zO;L2|&!w4Js9pf|6F!KlMn>2vJ2M_@77 z(_oBEl2fyG1_+c<`|ZjqC@htDQeI;}XsomhNd3=K^B4{F2*7fQzXtPjI|4rZL2D|F z#;fN>P!O0Tth$roQmM;TDzVS@$vm+wl|AMRl#kFSJ0? z!=mk4sdf@AV(o7aP^F?vs}aZ0T>2))1*NP}wZO)Soap+cKQE*|&DCT7bDc<97jqmw z(W_fMjoaX$1~)m9%Nx%@4Ge0!4+lRRO(B=}14yAfol5efLJbLI!h^kw&Oep4$ZADT z!~(#WL5*CB7XslsJWEa&3(~4~j&C^nV2uHQvlKQeJdCEe!3x3W3CD4Y)nrr#Ym}=>u>_E9v67FVpaTVH7;HdvxVRd0HfTP!37SP)x#5*dNE#T z6)jPmwPQ)b50|!t*mY`-p9lkk6=GH$cYI5^L{Ephjc@ztPTc;yu2L;wgRaRX4Zw_C zN$>0wXhm|K)3)(Lb4(`^ZwrL;z@{a zQvjVu1w|oT!p_g9VOX7Q$kh6f>GoGS45BRBnb!>)gHxy8;$5H5{s>RCWgnls?feR# zEYOyeCJ7aGOd0D8!@j-M$)qfE&MPdRB8bg!B$hr^;+>H2)N)+c;%{b$4kzIf{A0fgjNQS}QiF z_%tirmwv>9e!J z-2&8vlp^l8@9m>*wvRPocABug^!w1w%JL|FSthpx?NFQ?WKqKlaG7lkwKA<0UJd+k zbKceY(T@=5APQn7zw--5rrNaoZlSWb)>L@E+yGkBDa|?M`v)Zd$>a|l8%Cug_yG|R z>XAi;m3Y(PC(|b0>f+zYm-_(5te2VsjhWR<77KF&QU7y_nwVonGls9nKU!3l)n({M zoiC>iiD$!u)NMJ-EG}@<7Gj814t6A{za54?q?jD6u95ZXQm*E5xl1Sco2H%0!ht*L zL$|Yc-J`ByJQXnZoITgSM>P^A2>-Xt}w;e@37G@QH@ zuqXTvxv{TY!n#Bc@qQe9vOP^@QgS6C2^9Tu(Q;x+4W6H={2?zcaCiXR*H`Q$av3;@HmS?|M$xavw)N{3f2J8CnGaZK!t4BhwzNstK5is zwk}_DRRCTi&@#ut8XB5dp11LGfa`<*tMI~kkQcHs+;HNYf;Qlk37FL7SRvT^7RFvC1ODh* zgRTXW3UaV$N}`uv-h~XgY4%}}d(tR7A#Duo(QvGRf|o@7q^>pGMK-GHO8aBFYFomE zZ}z3`N3R(u^#Q564=cDot+#1_1v8VVCo$yFzd?d9)M^=3s9u~qshRS`T{#-bwP7mB z!sW$g z!(I+$w~IXtg+ttfj%M7Oq(Xbaendmj+!JYTR8f)i|9SW!r=jR;;11@u?tpMwhG{Un z(YRVZx{u6c^A6hlJ~NbvZ9D2L(Z&0sFwaieOrPWTMbfc-%WF%r4MawteNij$@o>B* z`)=GupLAQsnVY#;LJ2XOVC6~zHt6zzsx28kn?t$0qEfDk_VZ3Laeq#_g~EK}f`%7dbW~Z%ON!_Wu77Qg!+xp@G!K_v zs<(jogd#+F?gqj_dgQjy%!+c!lqtQrx`hn9QO#-yhR~J;5$X zxb^lY<FR6O#o-*428y#~q@qK$$5|cq4Ta0PJ zBx3L~=Jwn?7nX4aQ8SeF@}-mBqrkUg3kTxBb)>0?(Vl-uX73vg6U|E9nDnO85A9*$ zA}N6LES)G963FS)a-@HIPTgG;CWps(zwV`%;PqTx|GM0~Q8g*wjvq75e_|^=yh)N< zw;_dWbmjK}^7crZ-wxj##ndD%b$vsA18Qs^1&{SVN(Gb*_QvL}YB~J#(gso<944ik zBJ|}p!Vf>Z&>x~@-OevafdsTA<2+G1*j4?Akg-&cy21t{w9#RH>CU;$ zB5}@bcsG%IpCR&!jrC75F%we(^06^$@HI)?LctMnijv++k3HKSN96Gork-z)Ax`ziW(=U_-rDYaqH+gQ8 z$DhrMA(vm%S*Kq}!ZBhv4{oJ`jtrJk%#>t%lZ_v^^-_gX87FAbi`3&NBxy&qui~5= zw`o)w0(!4yx1rs}PghS9)WXQqhLta<=E)e7)lLF*%$kD+~ z^;+GU3Uzy-T#r1pc?c0h0nB4bkfOzGena#Z(_)gE7!Eb{#$o3b!(zhG9(6tX_bV71 zyQ?Iwmx|?ye6r+&4kXL?Sx^yk9GnCHTk>{Bkt;C;*BC^y-5Sz&|92gm_b!8w4N{16 z2?G>P?heT2t}<+V^hW!YVs;$j52oOkHOJ;V@hA_Ztgwi9v_*GX2Ns2hECna_^*Y6M zw@NViMeyA!|C;uN1#9o_c|500WkoLsyKer_t_A?5+OEASBV$pB9R?%JSLpHvf!li# z(t+5;1Y7|AwU#jm^NC0mjHKPCO!+=T3A&n@x4M+BPo8TekhXMZB{rGdtZimg9qnP( zC8^wY6z$^QUiG}+mB()UV0$2dZ&Trp;z(Zd4W1P>0yOP9bgieK-4V%$;SJVog@#ZZ}=tfBU zS{lX0W4caP>RQOTg*ThHr{2@{XO!y)fk26XwB&2b*hfi(#~pZagL~LSL|EFmOH14z zPm;esO!qXUA2MGH`!N^0+{4DEx-yL)G?}}iOc$E_$FFP*_Ag7;Go&!r>BBMZ?yG9} zAQsy|r0EkxEx}F@p^f$(Kr3lDm_Yr}+ogD4a=uG81^NzWtTRnR!4y~CF+3(67s_6b zGpA2HyDC}GYcb5JQ`9i2qv-^1&BqlWNvBoIUYc^a4LQ$}fuh$5iZ9In!5YYu^3RWWjbv4i?fk-@aGZzp`4)?z;`E zIh0arTNHL7j$G2AK)pFW%R5yI42ipkh0N+3U-7R~tgY<;hKMBQh>{@uC#L9h&Xr#l zNzwM;fSEgzOoe(j=}W4*1W}Uc!bPBVfe)QT4?y0PMKV?N4Oa%&jt=abP4+Kv6nl^4 z>v>=s&p_iX!?D)~F6OHFCQpIgFojjGIxvX3MB(0>wo;?$B}F86th-t#vymj|ar7(? zjX0O|f>ICPI}AE3M)-C;G;=PrV%uV|wz8v&O{h^U2yuC!gr&x6RK|u1pNhT;e1fen3`{H;}Am z`j_3F^|I;HsQU5mA9-Ga7Fz&$`8AA@E9xC_f;x>}ZN=uaG#B@anU++g_Fo}Tuf5Cu zIokNoCl~H-&MQXIC{>L)+BsnCvAIdS9;1xIEXF@Bd6YPLYWfwApfK3O!_peR-lhLN ze+<=i;b9icINWjfwit@@-I5;kzzj*VLT3iWR0l@!%*BK_=pPD-=|FPwbe*iBAoZNsVwXz-x+Q_5h^-;{|Hh9(iEPRmdpZY}XtIUE z(N(CQ*xFMUIv%7TsZ02VSJDXH6gu(R&A<72Ll&_9^i(ZaeaWA_dO+w=JM7b*4-A!O z>EQabHDp#}53T#iYKo!UWeP?q*(!)HVTU@YL3!Xn^`>wHRxzw$*mlSGHp zcbdAl={3+b6s(GR7-EW8>3|f?OXsZGRz~iDpC&-OLCyp4w@DQop00eROQ%XD9TH0V z^`ePjwf<}c(3B)54mgsZN28HfJcE3f9_$4&N z^cM1w0n+9=FTQt6lNs4&(|wFAMuUXqPuQiF6j3~*!2mARr7QAjd6g=%ft%4-tv_Do z0%1xZ0+Ks&l_Wip=~(l0k@81ic$Ye+8i%4=AC25x*f__xC@Cv++Pzh?+EVT*OM>!~ znRpY?{rO|)snrYRL2VKKVRq2>?Cq>Cf0&f?zJ_YYrp*Gq(Obu->Xh`?sL|;vm@iZp ztu)$5wbYv*c|ZKJ>0&&qSXd6(@*ZFn`|!FhaT2UluI%~2bBN0^BY}*4fyEYNQ)ZOt z|G{7*nmpWI;i;=u(v0+QZt`?}{zxW(xc;hkyQZKSoR_`1dexgN9Xfk*3)LWOsy9}B zRH_wd+4kc0Noj$mHpsrK7pdJOsqJ8Y?$IxeK++?{W{hCGyh&Kcn=;^{ep{9T!N6nM zK*lokOQfp5M47;e-sjM@9M7*`KTAf}<#Hel^c^B*Z#fj*>*Jb!rG7?7`=kVjd&DSW zm0Hw+LRwriOE=JbFPo$(wCE)0zTRuey+m_f(l10LJPraVU$I*{vL?z0_zk%=^IBp; z_g=554f4pdMm6&8xT^%S)@WsDN~>NeWEkmQj62|_{iwLK0YO>G1nJ+IKDcPNsoGrM z&6_=1elp6t)Mdp@S#o4;;KByHXxcyZ*uv@O@v6mlvl`Q@nD`21C;uwy(KOqZqSV{G z6f)VlwNQT~rm+@wS<4v@I4ghQMwBBrCKB@W)!p@5dlNM^+a{LU>bJHcS$I8H7x8*8 zKc^UxIO@TR3Oex3Ej~qefuv(r+NIw08fL~z<_L5A`E%;lsYerAe8?8Uf4KxN_Ww~mZ5lmSCB|O|$ zek|aJeCM#9EH6Z$G~#A}p|FwvZ)6mOzlA7N;5B5}Xo_w<6kf2|+s#WQ-cupE)1ia7 z3%P3(`xgkKW(RKgV--s3Dd|v9jRU~rZO|IHinW^k!c>2Y!4xjv3T6778>i*GGq|BD zs_)rBHnr}FkM{x6W}FJuWJ8-(4qUPEh2rVZ3*)PLmiA57k}o0R?-gh``X)HO#Uosy zhRXtqERj~l)*HR!LM@Q74|rHn8O=fgD#F6sq#qwz|K*gJrbuEM*h8k^2Fw6LX&SU4 zvNMA$x#*LvU-*m&E+Pt%Uw1t|rOuxMwDL!^vvbg;pVwPn@^mJvTjDuU#RjqBu$YR$ z8`I)HDj9Jf*@DCBT^wp{cxIk^q-u=U%t9q-kk^|KsoVA6(!ur^~u)S}L8hPPM1@?3H!__}_9xfao}u9O;^esrtn%6P9QsOGc>7i}$g zl>V7?dPs~=Q~dUPYrZ4i1q7K%|aux4%&GCd5^o_HsFw*-#P0ap!R%7iPL zzNw_`gwyUAyC=>cK%OVkFYX)OyNP-!e7*+c=<46M1(7qBdo^kjN|5oDAgNe?3jBvv zve9(GJBs53n^%%@`*G_TIxIhjyC4vld**JHQMy8$kWIBMo>!$jE9MC2ZYm=fA0E;R zn*#syA*&cmvuH;1?LGZey(Y5^2hqE!MPV(%YQ(*s-r6=!s-TsKCd)TY0$926EsEUY zu2a^$T9PBc+t20_FIkl2i*fb(Q}%=)jT*72vp=rZ1-5J$(5pDIGCJ@3w3mJSz|qFC z$a#a@;RBvHfUA`>A>Gn+2Jr_5I=Th-1q!K0RF*Lc1!R2j#TQ|ii8sJbrwu?~46G%g zU960wTvK2Ha^{9N7ZJ_wul+g-} zU#P~Qn0ZCB1U-1EN>sqaGvl+zT0i=1K0l6rK{XjGDN^QIDai^n;UB!678^)~e}e^E zj;(kLqdcUvA2px|Xi7|O1+IJv#sz(RoL!OyvEPAWjodpSpUbRTq@&W88ckLy^lEhc zrudplZouG|re@Q!1`@-iy%CJxQkrOHl8wIUciCbu$2kZ^%*wTI87Ob=02fh$0sDJG9y8NdFT-ry zrczMqyYxM-f>y&jiSdVY)m)8Xe#ffPDdXjLvu@Ov#g3Mw%9jJ#Rlcn2)6U#I)e_{cr61<{jQtTeF)F;E%ql*QR?|nQJ7lR7#Uq0;5 zGf=Bz5p&uAyESG-Msb{1H70H%BeM`Ui&=qLLq_ckZVjH9x8drp+HS0!M%S)scQU7D zXpidY#BP7!L*9t9vGUM2o$U}h0X0@|BTx34Ck1^1mQRi`W_Z`L13q8)a5Cw`Ji-SG z=$Tfqy&1CnFHPs>v!6Jc5MZ$zKG0SUR4!*3KSsq_df(KXyD<*6B;!@{`syks9bb0K z5qgGgyUfD_McU!e;Z^MO8m6A1Fl#gIpe*wsz+5E_t58$CUuO@f&SwmEg%{V;zXKVq zKc@*%!}PEYZ+cI&#jj43X4cd02+%<;<&dv@ROYG4_%7c^Afb9LoZ3IJJqX{_t1o%M zm{V|0Q_ATJ`19mp`z?I%deIQztFVT*AxBcAeyq7*^&jN1VT9qC@(Lu$z8Nob(jv`H zimEH_NFn7?KDjma)qdD9=uk0IT_-Wq5joDNIVS(fEo12uacl1ROM)5hO?ubq!DOC# zDJq2rprIk3xO%&F@{B8i+~u`-)(-tCD%grt6`%uh3sAMM$+=|iTo-JJXj>-urJiUJ z`dA%jAX%4Ilt|rLQM1#3Rm(ZsU2~$>v^G^j@{J zC}J(kdezuna7~r9&YPykZ4u!)r(91wO2K^eE3#x;r(L%<_CY2nTB)@?bs|N~chM*V zQLA|73(G)IInQClcV(}?l1g^Pz&0);h8v&s;c=K0FYfm-%a-+@512bO;DhVW8Yt}v zwaL9H&C?ywHyrcJr9yXf3H(%_a)Kl>;VO%v>Em4!&Qq&+vb>L68gOu0X(1=KK5xX9 zEqx?g5}eEo`}DO%+H)Yw8$|*7c9#2jl3_f9P3>(FP{NzF!?~UHqFz8HtE}V#R(JCX z=B{m!)~|kQA~%M2RC*wgEm^uV^BAVp-gXS}7)#ljo2-apH@@T#wM|rM_6Z*DSYdde z;Kk(5Jy=+xrp1Kr*>HN*iL}mpAv|s0?a1CQ?FB(SBBR|z)pveichh*l+-hS?f3EWE zVQ59b{1V=0H-pvAPh#jWlk_YTQ8ri3O&$oNn&=4u)RSwTOQx3v!;Wi3*eurClP+k} z3#j^+Fv{&0@~u5$)Y#$t0eE&MU&b!A3A1T@yffj?O%M2_weKhxEca1k_#mdmox=t2 zg{?Qn#^H$Paoly{PnX&Mj7^?oY&-uw%;`4;e2}iR>Vr>0=^Ju&`nx#wVHzNS;VvT{ z6Wnh-YV3KI^ewH}?elPFo~k%b+538s|2C;DJ-40w?&z@L#VoDSXseizVs_KiU=2p_ zqWuZ}#>tb9$kME5E-3D9+^#ivZP}83inj+;_wYW2g|+Yz@WX&{YY3_r}eK*=8`$$z0?g~h4S!7WfHfJI)n zgPuPAO4I4lCaZ99m;?DJy4N8Ra2YdWNI_XuivjXf$=U|R%Fh@KUNJEd7cpBo0o4=s zi?LI&{fg7}ey{#A&I^w0pTXaz057NhMZO7I&lvumGTzhV712)xNWCC;()J1E)&)2t znH`<4U^F3sSHcTteeQ3fY}GZIjOdTH8bc9$zY4rVhGuqhXBz3mtpWV`A5~=LtIbPG z?#rsa7}p$~7&zi(M`Ax(rz+`0(<&txZY?y9u8Kg4el>+Hczcn;@q8*iv1pn^j4Pja zRnF6PDf13)7uKzqZ7U(RQ=n?U8vy-XYX>(~ENbWbM4Q0j7~NupkVl#q8R>=k;c=em zT&v=2M{b5%(B3UVKo0`c;>~dbK1GkioIfy;P`Ch_=;o0rp!-TepQT|$jA`KtCxzHV zmAS7co&hmj#>|I7nQ2O*AhVI$W?Zq1Mc-1?0jvPIH&MF$f>myY`Ms$vKZ|2E=pFFb zc@`N)qtP}SuD>yPf^NLBSDyfd#;~vPKW2!JV!;KG?yNiA4}h_!JRCkAV0NZUR=IP_ zn}Kh1w9|~q!)z7GY!kJjMef1RW~5`K%|kI7!4`#uN)RON)}5bq2PW)-&!tH{M%qc0 za@^pVW_B*9N;~LqkZ&rx)WJ2z)^iYVmG-dLwx53S2JgEhD+yT`y9_JSFh|9K_0`y@ zQyIDi{cduG;gL>h2%;Ai^|>8N9G|)n6ebSd)Ppay@k*MrJ-8}3=owMO?ftzFs-f*5 z$)s1;KoL!?BUynZ9w;L?k?Lt<7_}w}N#OabEoqZ1iZ2|QRc+&PI(2nL#=VB4q2Rzj z95L5k!vjnud$FgFeCX&+=g4dr7ZOxih8WlOGjjc>(dG|IyDTrQi`}P5cfz}1_Ja3T z1FGf7OB#rX%^6pimdVGRKzeVqYHM-}HASw^Hc{v@Gm00}ayoETKQO{*MH;zlL-Uj$?Kdt<@k=ZKLS&D7vj|7Gc%cciR=g!>3yxqQ1pu1tw(6Y&A=^d`LjiH82^5@ zgwSJ!qvmxQz$P!&m%Jwfo+z;iyNlH67;eS~z*x4vhF3tcqNK0LyG4gpEDV2%wa2&V zapZ7^_0;Px#7I~pb+j_{=6{*pr78p-uj0oCZVOL)~U)0f8me2l4b-upc&6tkMQ-|HTaGPtXqs^0iHtpS0d+_=733HRb(L_<8crShx_4DR?Cy7H| ziGMRu`>|hIq>1k(jp7FL=-B_J9f02OoK!xoq2Gg;aiNO7vX)@ktzgknRGB~L&QQ>> z3at*|t1nJ$Eti&=*}EnU5n5MPb)7^$+z8SHM%la+(@9SU__gpu8g@x%Ju=4{fVQah zr~Zrot>Ao5x~Z4>x50pQ1&+r}c!gR^zCJ1h8hCHhL~^!k6#SPy_sM_FmloP zigOrE#39ag#-+bKoSg9ZhNd@bdfJ7EqMiwVO`M1sJ3oyxzS)y+Lb_bMCFj}pVi_CW zAPunR{r!S)A1*LB z1PRM@N>}6?YN9)r`BzF_|Nq_?NH4=`f{N_Y1bMdKTNhr}h#_`88w;tJ$FG&N-<}`S z3uyQ^R5)6FzUm5|)5D@$P?ln-@~>z&+;_b?v-RK7eA@8DD0gBsf-G&E1{jHO{vb`y zJkd2!>kru}=C&)8^7U7pn3!8a&^MPTu89|vGt!zoFM@PKal_b1ZbqTzuR}MDvVTf} z5~Bg?|=z?8%t@v1|liYhS10w(v47SW-GM7i9b0prFwtqhvMN5EcZwug@s6z zdfOS?aiyB~p80JNfkENdx1Sa0hot=1&>FuiVjjAgi23HXySTU@B|PEWmV@1eY|w+? zAZ3h`eo!F&r{1Hg&q@I|yH?W_;#paf5yXw%3d%hzNO*I6EVaF!tDKCs>*xLv1BTBK z*+5niDO0YZ*Uw_)3Rv8go`sMXA)O&f)9kn1<-NnkiXJFK*Pq^qZb&|@p)+QOOv5; z@8)tj!PbKz>+*O8{?(ajdkC5^?@T}PgH>3|FSF4r*^_o}W{vSTDGnNWkmg@&$8zZH z#%idx=&~bhpt_%&Njch_f`o`K;KIq_U1fn0$uYw{>X~8AM!D;ljy6cumw@9xfiU`< z)f0TCh?nEL`6ko;(GmZ4Z@dlVVsR?NEN7zeAQrV){1mg)o}D!h*J={%!6zL)Y&lpi z3*SW)cv>UltxD`I`YmVwd4Unm2#&pe@3%Y*+(1huhCAqnsC|#&c>aZ;r+L57GEk zyA~Sk6RAwuy_;)9lL3=Cbj_X@r37U|>(@=Y&+g{9ByFXRh5d#~Vfr;O#OkBJs_{b|bW1o8jv<$`L-zU8rks1}V;X-BpRAGE*V{t9lP=oQ+vmi3 z459AEW{$*G!OLT}9>T^}1alqH!)ZvHutav$`z@$Z-XEKRLY#>+Z~kML7Hkc}+ND=#{kENTEjK)%1-!4nY&kr|HD zCpN*cew-|oim*?bVxztT@U8%Vy@1+v{$ewcf1iYC9mzzwd$>-bB=_Vn$Km2==mdB8 zGQXrmjSZ?FjV@gqt&KAbZoWi zwP}dulkk^lUznmINN5mX%KUin`DCynIiNq>@1#VYZS=7<*Yohb8K{KS{x-2Y(_PLv%!j06M|wdlcLB3aX*m_wLT?n}^X z(*dctL2m@yr#D53TC1i_oD}C*vD*t5eh8UGnYvmT?+IBnwK#_pdS?FaaNiG+2?rl} z&P*em_#?%^)d8*eQo5q#(#$0XG96Hs#xrw+fcgdGvO;EtE}vWZut?zUP^~D^?@Rt@ zr*XPAhc@UCUb4Kik->v+{snzE@M`2MSfjI&?0Oxq886i!ZFI(KkSwHPW`6Kf z?xSV)OSK11tz!mB1q=x*Tb{_{2_vK9JP_9&mdcRaWW9mBi9*;mNVL9cTG9pSjwd2vI%fDDT6DC+3V%rbZesX712a_YmB z;ZPtQcXfZ(Q!Gg#ZE8bM{;Y^UF((-uXqPVDZp}{@F*?(y!~drvQW)iGi?gg}4LiD07(#gwrD-ISG&R&KY!#H{)ko2@J`cNtp%j zqHD2^pmkRC&X~mdA=urO~0(TIj!_n7>MXOWt4(O8)TE z=Cv`Hv?aIlxvQG{Kc2X&j)r8w=+&?4dTr!W)0FbF?$DrUI@^wOV2%o5DNJU^qTjCz z?vd4sYxvi6illnnXHs*%rHe>0*~9RC*`Uh$#~~cVEuOSODPoq-vJ9VSLL8K8X5)-V zQeP@$Y;Qi6xS%uy6-Ba{dNBXRh@FU}r;BebvpG)*XA1sAmPZ(D%2=HL#atny&pb!+ zWw7$gdCCmI^08Cw@7->QET>e3lIV(a(ncK|Ap`cVZo2A= zR9EJQBtBfj++8WH6x1h|4%L)y>p-YRzZ{4bY}%Bv*uzRXX{cZQo5U%X(Wf zZAId3e|#1ldU&L@0%fUv>wh;_=(K(Nj|asjvOxQVY!&s*otkcGjDAcA`UCSG-e=>< z%LbwLdasR#KC|t`JVNvb=cm6vf-!8mdGJ z8!001!)T1&_+(qaV*JXoj!`v>KnQS-(va_OX@F&6J+Np!r5Nlt0y~=6n%!f3^TMyP zrSXeLoBQ@!ISH5QU)p!mK$~i;hJ;-LRNR{lR;=zQ7oD3a)AduBNY)2l9uIH>+ne(2 za4S^cn^Y;yB}3(kxb#eP-#O1PjuOAORMrcT`{s9Iu=KWaP-I5~cyLobG!-=VHwRuu zeB1ykIA0U0IUZ9}=SkC-8>f*o?V=aXSSL_JxV%8}obL&=-j3j6U*Tx%^Fhm2{0)Lo zXwt-QiHpKL77}TA64LR~td29AW%!|fm*3?hMXpJy^A*2JW}<$8?Ddy0skI$GJBFR7 z!Q=qLL))g)GF<6$T}XYe)sRBD1h4gw$QVYn*l&0!3;iEt4m9L}V<9*UwFI_mCkAp& zD1G1y?MuWu52#YBs23b zqkQ>2Yy}!RXh~3;T7&azsZ=d{#=!3Z(I8%Nqu$k4I6pQo2ILs0T5VPdnrY9$E#cBA zSwP@Tt2U`gDD^i6dP*Ao=7|x+!c`r-RZT4#v_T4%lUm(`yQImCy4+rl^BAg5=w@UB zY|f-WOfJUL%H=#5sxo&x8*Q!egBLNx(t*$duR)(Y^Eh(CJ0=4Ox-aGfc3l2;@FSWjzv$yZ$D2AG5BSr^74ZjnS62+H1G z=NQ<%DP?1^>5Q`M?ul0bBum*BhN&pE_s(R}_`BI37R;)e!beug#x`T)HwNC_HEp0B zN|SrohAsILT?JP(4D;FGp-P${FDT6a4ZAR|()WX$==&7_7M;5|Jfw@h8@jRfHJ|s_ ziHT0s@(^RicN$FnzUZdF!Cu0*D3FD`2TVn>+?llL%E^-8aS6UPZg!Zk!>R@)kwzNR zr$7GX{Cz4CwN^gY$dxMNtJ0S6Q*a?_Wl(TAh{fP#0{P%qGy zKd{p`w^wwZIu|D`VLNJRr8=c{C78PBBSOLZZ`+x5$stJEjI`PXl<_sLD-+uqO%nEI z#iF&aLttfehOo}sUt4bc4MExBpKxfvgXH^W0teu@mqeJ+|A4Y)N4n6S1(#|EQ`F{XYoPQP?ctX zA2*hAE2Tm)3tXU^Tz0&~m>#IcKr?Bmg{z97-?{Sr*{ajRjZ=SfN6FB4H8Jcmz@PKi zvG7(b${MEjorB~R49W4=8;YGh27cFHcJk`h-8&U0q_Xz^`O!52PLE`GME63;l9cS^ zktr;-6XSSxVYuiB?H0b#ZY-Pe59;Ac#QWTv3x>#jJd~wxyio^KZH>-%z+OM^V-ut< z+aN_6FB0AM*=Nx|LGY2z?E^?3Z>pVwUw^yJr0**KzA(juG4f|x@kBnIHZd&t_qCd%HfBqpbqW2=eLT7MdaR0tB94vEr$lRL#o7D0Q7-VgeMAxq zhAj^Gd}E|@+x$w_Xfxb66bLRikw$cI*B)ZuUe*iD>_DLREepM%1wsr~uT+x-^KkNN z2~QVPsgP?p!{1PT`2kpk4+#hW5e^|`gYnmax@+22j~=1$aIxQV0&lZtW8|=^P+QN* zJ$6RT>w>22*WJ5R7i3sbO>GnEo-r7zU*q0=`s2av|6m#FA8gncZnMR#B>dSWd zJ4s9#FT{V0G|RE3LF26`xj5ugMdJsm4W zV{C1OwX=P*?{mmjygq)%grLv5nsx+?FiB3Kk1+SBYQu#78suIvx9i^C9eAiyYUs!HCGqg_rCdZ#qb zK;;C#YI%VZN2_e-Kx9q7M!1<)rl$(|VTWL(kN#q}|EeSGToJgR!b#hk;Q>jl_=CA^ z$Y+oRQ+kYn7(SEh0nz8I;zVN2p6QS(g!Y#eLTwIb-Z9`TiQ1-EUdYc_JXgejiU>Hz zmhf#bPeB*q3Y&orie~O|PJVJkcDdeoG#NCyFA;~nwHWb}xTW$v+Z~Zl0P8lq^ zXNin^ZVB#h*&4V=Rm<8jQvGdgB1!D^I?4TzO=za)aZ4c?NYPImCj8K|s zk|2IPmzVkTSEb$9RCh#s1Nll`GvPVY@V&?sx_Lgh$feL<6};EWI*@Sk zy{@zWZ~!(mCt=5|PSEyR@le4iDt{ybvYJjXSqUxd%kzqMj4&afe;i$HHeW4N^-HMM zC8gct!}ePHaTi_jd&xADJQO#N%QJyVH8RYPF0*Y1P0~MUbKwMXbw+gUst6TPW>LLW?G_s(Wr@f}tyM27tE=rhW|Bb--Goe!MFNVvlhRh;LRYvZg z$@Meb-I_iWY9A>kwJQD33|8k*LMw)~Hb%2D`aB4LU8pm!i?q`g)myn54l5(JbOPS9 zuwlG)pg5IWN^0N4iZ(B60}SzZ2nVxwSBj(lrYjP^1--0;vlh{Qt(`W7p6`pR7om7(vdf)dDE2veZa?Uq^~$G(floR_cvDw! zgIMWb3=4_pfpZ25h!^$tQlf|s=)78X7I!h!B(5EzHa(3?195_$UJl!>6-i{P@)Hv^^}i2f$^PmLpj?X1L8?W@xnh>!smMq30_@ zK_>_I9h+rWf5pgUL`%*?VC&r_=CWhvh@|xz?+hg#7 zp{%Fv0rkj=9=!Z((P;~7SynQen`YB=bn*O}x}3Gb{%nLm+l*qSv|nZ|+TZWp$H`kt z7x@W-5OX8fE`27rDH}>!ZAWB?cn0p9nBh?nPo6Dr?~Sm}Qgui#UsA*Gt%{Pu5r1EV z)?L+bX}mPHCt*8tmJs(Nf8K#H;oHsH>fVM;Fm(1wb~u_u1R7GiUf)9dsf0=W-uvIo zI1=u7F%8&J*tJqw#@$y*u5O36ybrnVgw(T&wKp z%C&(nN#K1g9!)rCR)>e=s}r`@*M$j|QxGs+dIL@RvxWkoCe==J_<@*(%u=)jPrz9N zO0uyKBBO0_$P+G6596hA`=Ks2)ta%{rH3sWRihw8cgYStt-@M|@&!r-(hwZF&x{Ib zZBR($`=*xv>|zML$-wVmh%PtLO3NQWFF5C52t}ok|6l_&l%l?NeR}HS$PBR4W#GP< z1HYQ-;7ukFN3J`FJyf);Io43{dScfX#8!yb<$zdA<^{zZ{?R3wG@u`6{y6K+p#Qx@ zxu$5{%$6VK*ed@W!Ea1(NqV|l9Z+Vq+pM>~)i?U6^ajT-tDte()8=rtL?`4eZJHjW zSmF|)e&ijwJqbIY2Tnh!3Z71g7#;xUZj4)rRbNZ!L=Qt>71Q3PpiL}*C+v^npoCSc-QeUgfX zjQr>Bx#59ZO|r{9dvW3smx;)K>Xb&Zq>QoI72rox&-7aE5w+ zoU>w6uK*U<2z?oPm>EbN>v#CjAp9fwnLXU*G9j)^z`OgXiqWCoNa*a9>zh-kDgxD$ zg`+*E74K!)=f0Et&W#aJn&M{c52Q|9yF*VhB)QLz>JZSE9drz{v4$s%;78|iopzT) zq@P@dY%<%4t7)!%Zo2*wiS@uQ7x?ESXgVr4 zwP-PPYSb(|Z3m2;x9W%K@0liRIIWFuH-Q%8h_AO!1jU#_(Y=t|C^!>s4}%zOZ&%2- zIf(sTY}4x;%zEMM)q)RZXCPX@rCI(Alb1LgKGsbEWXo7pMoL^u!n0&ZzL#I`bx2We z`Qcn+${!mJu6BiT$=q`cIx^hJ=%E4+2c>2FGSSEx2YHvu&&t#Qs;dh)+tB!=8u8T6 zE3Js7)r=4ylU3CK{dsdQKn^C&Ya*8lNh+zATC6z(@o4&e-mH|J--t=z#vG^Ux88LC zL(6#@^#i)s*Oz1(V<}94=o!hz1+OG}-qUerfRCF5va|wY3V}tELaRTAs51jFgn`^_ z%pVAy(#MB&&!@0(O|0Wgl_#F7<}W?{)G?)!9sVf4M}5IxVft^RiK|iDU_IPul9bjQ z%yWTgSqCSYY6QQ9zZhl}FGm(N;c}{fu~Eu}I?Dos9i%dUGnjea^`G$0{Zt7#sMbU- zHwWxa-di;{nw<5*JMk&}Sqlu4K6#VIjHkp=6cr88psr=tB-#vivDhZ%^DlKnULG6B zTMjzQdr?p*OiQ-3tcnIibK$)1ig6FxG=F>60+y(LWAt^%Zd?PIPQrC z|GT2rPQiH?HKVxfh~WC)xHNhDV1N3!$p7@|0@pA#x?+X z5@imam0lzPc-xGRc{Zqo9K+)--(T6Ri@BXw4{V0+Ru0xh_7c?PTnfSTHByOwP=t*% zgC-G-IS9c9EW}~cTMOCZ345`xW%Eo4F-n>%i6X^=ycMchdIW0|d*zZ`)1bZtZpnK8 zyN|4xRWlZ#hJUJ+Md$)sM* zRMO_J$Acv3H&(O>SNjk1Q|M1dIk=pE`S(ZK9Tx>zL=?>Rcn zlK&J~6*)%1V=yYm^togE7p=u!;D6Zks?QZ;LB5Z#7f2AjaA>oTs8{EZd-g z=NJnh);+A$plDs5sV9?($7U9>@7wx?$@6Q&&eiUbzX;|xn~sT}z)T0DcKHx?_Dog$(vd<4Zpwwo^ zl9PX!Ts(}iDsmM-0D&&1d9U2W@ikDfPf@3g>|W~i$6<31hpC|jHisLpth8V}tMhVz zANcO57foN}LO6Qw&f$N_>l*0|xct$5h3pH|H(nTodjWhon6R-$dtPkBDQ5%4G&0m{ z{N*F9N2-%|iy0#GoaO4GkTKB9`()&5!yM%9rDFgyGlZ)t09NDB-ND;|i%GJdwyu?q zO7OjawWn_pm`{E%GMRn)eiaw@RFa9CTiiXw+l$W)%aG+UdD1{lD%em8kF@7)OdaqA zLk8@8mO4DGGYHc9Ga;O%=8+^Q(6x}lKkP9)XyhQ9NMt{KjuJ{v;r-i+RB9j}ozJ1R zf^ib0*3(Qfc7Ot5Ez?cjPJs>yJ;SrB6SCORX+2J_&fTB=i3UP7i#48DdC~zGqkz)V zP-A!2@6zbiz6{7{f%w0cF4IQy0P%0)uOl~_ge>_^pfmvjS9nE{mzj^QX)R|($C!Qm zmn7>S8P{h$0QorxKN`ylnMG00X>){Q?NrA6`?w!uzgSJD;TarQ5_twu3)pi88qI7C zNi9;7=Tl+bXP=#}c+2%(s`rQ|E#Rsv(uG7Me8qmU8*TBZA45WLxli+xHaD;$w=$xI z#-%xzX9!}UAsy>Ig1mG#(WTAmcWF2P>`OkZdS*R$w%(pYv;0@xGv~+i){7NisAOEX z@f+-}u(U$YR$z3*FysV&V$;wCHm+cusK%uagoBRzjY2BOg&J=DQm0`{xB>Ux;6x{4b;PiPjjf{ClnwP>(l# zkoUpr(~Ex13=#55LyMny);@rf=;fyd1EVP}th{D8_Ouj%NC~_dl0@ZW!JzIiQ$d`F ziUQJ2#$WpQH<3N<#tAZAZhuyrY=_&!pg$ss3laB%luOb&ir{er|5+rD>LVsG4gV72 z{uAiWCrJ{-3JnT(y$t0WZGzqrMI8GY*-|WQEaBM^=UNK^-)KN!TD%lm^x|0Go|fUW2okgR<#(!HA{seEf(zAXadto;mB; zxRX7!2p!Eq_N~!&vx|OUknE=@yu8$t1N-VIy?m-3dczglb&}iu(-9JhJtT8qNdUzn z9))A$aq$^eV6hrx^l@aA#Jd^EBvVe~Z_kdr zY7iYDJHpxX?xfPmuK@1XLdK*od4vX+w8nOlrGpDwW-{J)`&)AmSNCr@UYl6AL+ef_ zZ^hG==fqIP=owCrR_}uBg$A6M3!&Mf(KdxpKA>HWSSr*=!jT<`X@v0)Mk%SlFX)>p z728Z-ERTzj7yF=f1tKcb>U5kn{uQ=yKg@3)x*f_$7Vrc$9vCfKosg{{8S&QyS);pX3>-7j8HL8iz55Y5Wy-lhVKvtaQf49SoPAQZ0zXgX|OfuHgXpugCL7r zV;Pi6OxKw2-Hw1An9xnGhjRAT+|Y|?D_CeM&TMY%F{{X8#t@*D+Ajzs;+DF;6hYP- z+(lc2wJb)l<^iiz9O7d`07alNY}|V1`;p0q{v)tig|)q@Un^^PNx3YcYPG-a{Al{_ z+R`^y83S(^rn(-pc^_%3;McKOpP`wDmo_jUsSAaqC?invrHh4#r8oWssR^D5t-SFK zcgibL@_2wZBzC;mLD&BC-~Eh3kH_ z=W#21B4`&}wPJ3Fq%6svkFBbc!?Y#z7)Im*^i_4F8uQ$k;3h!)WQu2~e_FXsSK z4iAuIIGHWktD`MYrd8bkri3^2D(Lavg-J4m-$A)mi}V_XqVs{{AF_^eW>^T{e^E0XIl=NEqmDSmHuAFm zy_fRiA(-!uuot1Hsyx0);|(S5cA~}{)@ch11+K)f_x4?A$uy()(r}_qu3^nubt|5U z<63y8PH}IqS+A6@zzJ5x%iZ5%r5b?K;Y1UrG;W^!^MM4*t8SlQ+I7FmxeNh#TxeX| zTI5GFSZIYDx_8Vn6?XFwXLD#$JKJ?5gy7|C2B*yfSoo$2JD#G+DhVkDw|ZFQNE++I zh%bCvqeyF0Ai2gMjGD)mm-g8Z9f$9`jsJ9{LA;xC#>dQYmrK38*7T-CFvhvf83YIH zivU=8xvnZx1Z8Ot3D8r{l@;X>&%V^sZYh6uz@8HX6CC4P@o2I}? ziSS#1_D7FmABOuqWOIA*&*BQvUk11`X}(BswN1=FkRwQ0sQ1Iu!hbMHA0oqsmo6l3 zG7%}aT_yU}gdEVS-y^TT?VLIt!pR4pvCb%!4e03=YY)1=$l-e;&LJq-Wz=Tz#K_Jz zwSAiPO#ML2;w^>RcJk<>s)ws9xi@VjVu1=`_Bc4waoy#d7ZF=tnVh3i1qxCh7wR(@rYbTN zFICitPVu%$r`OV6-sQFST)4e@L}Z#4AupAx@7pB@VCpx)4q8^7RsiK7K}^s0ShHvm z_`pAjd(htw!!6~Lt{6Kg3+t7|Le5R~&VTLZz7Tp# zT^gN{!C?NhoUeg?S?J^NvIy9YMw=1Sg--w<6M?b(&hhxHZu5 zgG0@3cjua<2tM#S#r>zYuZX_(Ji2&$oF=2eSAs`%Z?z)vsR8h{l$$qBmw-#v=z#cF zA;0lKlVA>|kZBZp`Zc%_R-1I($wup!cqY?g*y|LVtb-JdXN`o@R%(l_U{`r*?%TkX zuya9b)_0U87@UD9aL8a}$jiz9iY|}OB_Ssl<2n1SE9A*44e>v=5owWU@f1aiklZVv z&Xb;ijp;2;w3AR;8m(+QyReu*u<%1O)iuq29xY4?`s)Q-%{*mPS-45!4-w&wKi& zDoh2R{u2w6UPim)LY{6IJ`I|f5U&ig_kNfWPhod-_5quh!Dc^+UUG8vIGT{gwJM>yMtEp8(d?i#mcNh! z{t!Z=I4<|!WvAY5j2Ww%(0HL;>j~?8WzWVrW^9DGe#MS%p#NVQ=Drw?^+;W9=za7}3Xhtw~c1^7+GSKx-GX}j-v@(yN( z85mT#$>1T|ihk903E--e`ns+XDC4{rtn>V5@pDFt@A&%rNzMFp{ z>C>(ZN!w;e7HYg35DQN9lx25}Sbduk0#ma0n?(O6;|AMXAQ(t=dnJ;GACY)HCWj6w z(PUL1*^05frP$4(d{|9Ix7}SRD10EYND{2r)%K~7`wbh!LjOrnUgMK=JU+Afx{v+o zmg?bsHkcKo@-IpPgKp1ZkD$r=$wsBZs^Zq2&B9qe=T|#z3^_%KusabU3i1H>x2?*h*_G9nR z*??WQ7dKO)4NmLPQ!I)LCK6(nK11aR(SQAQExn;Nf1*Gy0!~9=glpeNf{v1tc0%9@2!^zy_=imQLpO4@|tbV`qV{ID^_ z#wAU2Oc9q`w)|Ni`sl>zBbp2DHX?4p5VA`h`RZ4%b<-3W$@?VPyJ@9-{lMlkNDHgM z%Ke^${Hf~#sK7_AB4sJx%fTM4IKlbeDtNYZBg{oB+V|~W~D1Y(BSf(^d0qy6zxR!1GV`oee&}g)zzBwI_8}lrS`pdZw59|@5 zjFD8$4|bodr0o1v`37YLGkRwAGH1s1Z_pe)mnUeF$9HPZIf~Y z9uAl^dJ-3dP)>@bHbYmCIj>Q`Ym7bqxK67j5Su6Q{&aRC(euo~C#qdtoHWah!r?E3 zm|_mKaGoy8^F;SArYGR?b3D~)1^4bdj>kSl6nY_HTS>qC9$vpFW)~g=I&<`^`ahgg z4*Xb`fU{wT^0=E8jK$OeeLvXPaEAe)Xf5=_BUHF)58LA{t>_ad>1@gJke15*$fC=a z)QKYw83}6GFTqNrP;6#fN#ZXVU5S??ZnM&8(lDMJ_8%1zkcWtJ{qj@}901IN;loh{ z_IkxFozzB(g}-1KL(NQJ`>EE;lP5;k7=Y!JL^N1GPvCK=)>1x#PUv@GOj2+sh~7{e zs+GFGs+q&4c-dm#tJ&&3S>={^s6S8G0i(pUv{_4ZJdiG*jVT)0DFDG*tJK89Y6ia+0hXI-eHB(BnUr-BX1fB~inJo}v|utgtl)d(ewMlHw}?7#^Gop!#bV!T@RWPK z$37}mVxo99MWI9;O;}u~>lfTFo47wBl*56x)+f1Wad+#J$I5;ZV-jkaDQ7R1bZ$`R zxCi02zWR=g`w!g^*--9#(o3&qqP#eu)IBnE(y8lC*X zxrm^~j{X`-QhRJ8abY)<%hk@nspvn}aeRAiJYGNs;v4^iTlwqpXKl3-MX;J2f7|?R z*_Eo)>r;6Du)j~I#qZaZ!l9mQeZ2j8kvcRkt<~ z^R9T4*H16H@$oPN?0xF6MzM7h_ae31kIW+2j({8SUep{6Zfu;Z;tv>rZce0~Ul?0S zk#*9J;n4m-_+um>rhs9s@|I?)QB6d4-^tH5j$rpXlAD1V$-`gf1_d=r!XL;$>CGJv z1FC8QOfhLRqxMfZyZ-gFOMxOj(aUASO8^CFuo%CJD^`^l&=#%&%FFW7+VGth`{f`8t=xMYROa>YO90l#gIVd+yD)Rr=z+xQGIN&RsqwHBDsQ*eUP$SnyvF#!su;VVev28Q2cg zYx1kFR^NOn2s-R9n79niu3Z6)L#2~3pPzrggV5gGb+UpC^E#Baq79>m&B?(S3HW)G z(W+t6x@vIpK_TAqpfY2#dv)3|$63}#6JU@~$8c``xogH=a}#O~pRl#fGz!{3+p6kY z?UZNkKnLEEqxzML9`6?GY()asWZhlEtBK)tzOi$HYuBKxeSbhceq4>l-gYJhgR0-u z9_-)YM&?B};%s`51@85_0q?!A- zZjCxX`jTG)Kt`{U$zJ|3S!*%Xj92gfyZG=2eIX~;kjfF(*qRJHEwd2zA;YYPQMhht zz)7(USl)gsX($c|LLab4nXSS9ey!M`cgac!9|Nxsz^Y>{;hueF2U6KZcx6)%uA(mS zz62>WK-)?tmU%1bfv%j2KTyi?y;ZjG9?GJrpXPt@59E7<(WmLrSnHKpd=#$o>ll!_ zKPn%g8{LvaEiENPGW00Vi&Rk|uj{oyXHZ+Z_03}cza_6#t?$NqmR1IX%@nj&4e^g* zT1fWQI}mux(U?@8DJry!48WED9dSYL7azLL{ z`nx@&s8=}0T#g$~a(Ctc_=JAYePz5+w2V7@fPcPF`4kxYY5FqMM5YlK{m>vyYfo9p zvbKKLdeonX16~^lI?yES0}VC5Jo&MrQGUU629G@f7>t6X6X8V<`8xb4pp*Pm;kP3) z4IXr9IyL)11#gNTK8{NK_GUC!vn}!_nFI)PJ!oKLLYb~-I1a~K7)wGkhrmP=*#|zV zEr;?lFGpdG_wux|i0B4@sv(x}rxBc^hh|tASZ$i`x1h!j+Vs}R(Onds(XDU;160r% z(a&uUc+A1@lC)DZq04?5vD@|#phPavifE1dO*G}F!AolNZjEB>;SUtt>dDh}DDB1N zil&Fb20+G!G@p|aNr8n3HIwq`Lon8=*5LlvdxI1p?O(`i#`RgF42BF5JO-_!bRZr04=AQn6Slp$YIR!pzs06F!owQ6 zg|$i#WIp4D9~Ndx!X-1k7%I8Fif zOu{G?^>-qR5O+&`jwKOGHVrvH7W^Lj3Pz!Eqfbbx&DD6h#Gl9vCRkl79Sv+I=znRr zej!(dDI8=4tbGRYRd7TTF6;4s^2_!|NwHnXX}3UjbSgPMy-MAC10bS+!ty}-M8BfV z-p!C0pv4YFF z<%qq_H~R5X{#tn#QmKVNI~cgS2I3TRFgJIm()M(m8ukOR#Iw|=(dfUQu(sh zg!}y8SM0`!dC1f^rU8bXw2b=r02WDWMLPeyd~|@}XI^|b=4s+w26WA`Rwi!jA^Qvj zJ%Rn<4A(OA-z;rpb)l{%_{x|05Z4Pwp3aGaVy4}5QPbh`zLV;`V=uMF<7#q*|OBU5H=6U?41518BR@M zl#@{>+)=L^WgQ;~-J7cKx6B3|Af=~p_28lLbLUkmq5{;k>_gY+(-8tajY6s3{i%m9?*IZNWk# zZxhDpjNeeSbMy*_#8A>3ogSCLp%M1-iCz?<1yJVoTC)Cj@M-Bglo6<83+hw_^%4N2ng!mpwD;EHSnEWhQ zrd{lN>m$LW7vk0JfE>o}DZc! zP*p1L_0Cah6>gn-9_GkWBS)sbPQh3|BJSk)I7zTx(W00iU5_ttoi?We2&K$u2fA<_ z>)w20QKUMJy2=KbL_Xa#3qr?`ur%xdG03~wmb1u?5`&(dxms+ij|Kh_o99c~<%`>R zAUTIeyF6-7s}B8k6?IB+l!J}mL2F#x!nVI$U=Z1gtPTC*cj@Y5$ev`uz)|R>T}m-R z3?Z;z-ZN_NzD4h_Y7+7A?FDo0eZ(25+&z#=G@O~6T!Cr>4R42>s?|@jB3ub!*YV4y zSPZwU4}7V@yS{`iZ%DI<5C!|HAL`$_d6VPkU}flk8f!6%SMS4bYXsRXtfBMRz$g6(pOz|2V+z;ry$_Owkt;?0Ld;nuwXvq2)E!Mn6Fxi>p5 z`53t&WS<9H681rVwuv%IN#!HUd!GC4A)rb5ChKOhQFD+U`)9<3&Rh%hB!E&_*DYh->K57+DF+^QDL&D27C<5nB(ty2l#d znQ#In{qcs0HM!;82QZY|ZNj4UV7lZW`W4m^9dPIRQ++S#p$tKNLHoUMCPt*7`1)>a zs;L}WzSEplUM#Dg9z23o(_T1$UpcTYO`3;7JgKrq0#~Gxzwh~@%V~G&b-^2EslT6P z&`^6za#1ZIriWJQSTl?Z*f_g1Wo#b$;ZR}cHlNuKJJxYqi-6Tfch2{?Ljtv<<+^CrFXKeMvpxfCe`+wN0-nC84jK1 z9VXG=@*`Tbd#cPD?e&CUm;8|9;>t6YayKp@juWJ0%^1FS9VvnP@5SFTuq|cqvu?q7oAQ5>?>ZlKPH(K-nxQbl^R-HR$vFot$Vk%T*wE z6fMM`!p9OV8+;tw5uy_a#e%lTFQzxkcgBX>RP>o!&IdGVsSM`OF-W*!FXlfEdaS!j z;ou4w5C0E-HAr<|Jp(h&%B|Wbd*BFGH+uSPNi`m^c_BG!(E==L&Io!pOo;_V8kEBs zwL%mdEV)IjU=b;+ILfi8@lS`{LNR%mKZ36SuxZM=>E7MnJg~^n;i)IIXA%~QY$+-%tWN`~kGr*N*;RnB$Vwg~y z+@)1_*Jy68(;_u(>^pv6Ws}9R0l2Vo&ycKKU%u4PkAL}VRKx)`g~X0##0@PNU>?ti zO_Rd}8TaGCu^?B~P%YeNj(8MudcmeH6>oU=3o}M?wI(9p6gQa(>*RsIARkP+yGTFBO26D)mSK1PSl^TK{ov27e91rmt zqG@%u7y8Byx)jhc^C5UwHjPRssG6^;87z|Kx41CuQZ6+vcVLc|4vhn(D;{3?c%;C` zA(^*-(13ubrCv{RpK&nC%7CQ(YHCE~v!SgU6P+J=3IO zZV>P7Fla&yn&X>;pln3=;bV&;T$0trm`*|;C#+6nQ8PfMXQ(P{tu-SX?_bNJcA{BL zNK6vWRxv-P>5jwTMw1_!v_1qMIEl&^*F?>RQ?zFuEdS}zM8!^N!_jZi8~s2FlU%)~ z>ACEt^w(~^X(~e|mjy_4r)~}n%emwqXx%Q8oasrgwmU*#d?_Z<-;H!^)zvG?j9`YZ z7~^z}YKg320{<|i#ht_f)MP<`+119I8<dXgcsRpS>m?-(u75 z{JV1ip91iU9>sC}4#{Vg|DTh|Q7y}OG|8plqG85$e%Jy>uDBK=@GK_tm(6i0&Mxg@ zpRs^eGlXXG_QH7WTW_t3cZHj>vc==jJknv`e@}G%G%+&`M;#U#M$9-T`20Isk%v0# z4+NcePeDUWyz78n2ZENfds{`wChXew4To?YNH_DYZIEdKh(Le9y*?(!Rux+$-gRvA zD*|zohWgs;_RW&C>G#e>gICzZpaO#((JMr$asQI?=9v(vdbTToI%zt5*}bQ;1x$`f zoVXb;{yf$j@%<3jF*>QyUoojBamvzn)V}gQJS4T@QUfo?-+4CzsGgta#u$Sc7l|H1 zn@t98KTP_VJ`E9Biuk1rn=qfmo8sQfs|eqL3}&NN&QUAY;7siMeEkIFCmF|O9zlY) zw?mABuMgUg={|AM{1Am*LY#MfVHDeD89&t&MvJ8(I^CmS(TBgR?xIjy*<2i}U#-)F z00S)vdTq0!`Mhu87BGWOHs%jkidAB|W)AQ9KYfW&=0fk~AHzcFkTmJd%g5L=j)Bxq zsdp61d{K#s?p|mn=)ccOW5%V%(*}ZPONDBVkZbgt2#aMl^=nh+Ew^8ZrE6jlsukL- zqPOtTJM@*&W$}D~3%9bIhla-k8bI=NjlBHyeLTeV7D zK^CVET8PU-TGHQCSveu+?Oc9<2T1a4bK^r5^Enju5y9yrWwUR%TtUD4Ur;C~cQ!H^ zRw~N?B(JrOtx>flIwjlT{>4M3jLN;rvK>*(aH-L#6C7Agd+|ph0Oe6#s~x17yUJ2Z zcDgNKU~z1pD!2$gZ@5P_k9O@`%z!8oO9-DM2WC!5jObB@`@6eFhXV(juYXWDqK#Lv zf<9M*9vUk^(TcW@*vfv}f;W7@g4DT9@3i`{XsxvfMnm3VOG{Q;DdkY6 zd+5 zz=KWAM7W|KHXUzQmnrWwn?17T<>UEAo#G8e4i+#5Ok79-OoA1u=vK0pi9&A%5#VO3qJ7ZP&Mx6iI$hQ`LlDm638jSFiN_ z=NE4{C*D~zyW*0ZRmf-cwD)Ay1SWF_5r9al`3P>xkMrtiy&*|5d$!aPg;@%YmPrn? z@DX+8%eb%K%vs5c1d%!Fn^#E8xy~_IO#Hzj6WRn__i|8C-I_gZ=C{I$zur=U*z^%4 zaVbvmS0xENCaTZKS^uk z7jiB5^UrREDUkci$R-|e1S!g_S|RQ!m6ovjEOPWz3$q6JuuU_+g|SjBCSUJOj$zI% zaQ(A1m{%x6L`eJC=oa~qzA7VN2U6zdedsvl2Kav0CyUYt zH<@@tFo5WEC@6#iYieZeD{WpM)nx3}lw_8FGMIJ3!AEZ^MS&#d6J&Nj!ooeXh1Z2GHl5);-~W9*=gY2Ajlm0t{^eBN6}N~THN813 zP(@np;YUNUJakc6l14%NT1HWUc6mIr`(J;=PJFDeykHdMYEuk1%CnGbWF}(igxx~Y zGEy~+b7rhc+n65HmO2bA{<&`9Wza}-+Aapd-Es&q!@l;|Tc*+tVvY-EwTn~^ zXDJgO$Ep|L;B=?g+_2VwFg7B4ybo8jgy%j&Zh()wu`&iM0gj%#=4B!(gLqk0c&F84 z$&O&=^dqx#6Q~x{A_`&GEZD@{#SAJ1@@aMC%k9(p=EGgDmXjOz&~d^Ai;ApI(i%1573>w9n`9ks4VD>t!C^EOA7 zzyy9r*yN|@z5Pyafi({6+|B%v!@}_Q=8V_AWi00KgNZD-Zaf|Kde=-8Wqgy0{e#9M zH;VN7w1!ba;(r!>)o&Vbp(g;_(p@%oh*ZsNZwR|%yp)znWid21_9d$KkWj$rReX?_&IlXQS{s)WK3eB=EBWC1NgC2-??${6)Q z7ETU<8~*~MN~ja!=_LqY_u=EpX#;1W;G%K6sb8JX=3EoT-O@qlL9me_{GBY}|7+pq zI}~A49W+5S4qeBAXPZYWkkOYWpi0*UQzzu_zbGyHgl|&lb`2#*gO7L6veKERtdioG z7B$XT5^k`)A8pOVoh|~6swtUSD7>=?MZ|Og5`w6}Pdv38 z!v4L432z{1O<&7G%47IPtA<^>>OMZyuMduXmb3eHXbX2lg5i6)Ztb57HAFp9^P>-S zSP)u-Ej^^8ES5p3T z+av50B4A&{5h0*NAJ;hW0Vy`1^iMlzsx`>qP**d-u9eS%xOi2JdBwpo?+hI(Ba#Rz zZ>y!OyGJg{-jJVm)TMRp*IU2y-4NN{xPng^qI;)zU{E}HANjmtc^Scqx@$bFi(J)m z!X&ZHjnJ5y{)GAa2(mErek=2nTPZ)Bt0{LMx!nH&UfHVEZ~wK28ka|filTI~af6cB z&+SzCAS|wN-A>9FgLBaK96eqW`rMxfCNq}uSH+=4&G?KD%j3)u^2xaA_7kMG(LD|D~*QRKm$PlF|^Sk-$TuZSwUq%w-PP*SG)? zEUSDG-rru&5S@ExC(^eCZFXTNDK^)R8F}9TjUuuBkqgizCt|XiiBa<`WxSS;khgR8 zsN&rS$5!=Wnn7i7X9Fw$gtX-fS50*v%&lcauwB<0(&FMZIO+1k*&m36DqL-mEo}0% zKl}5GThPBjaUyVTuFe|1%pblF%MEbNmgyvTF)#K1e428Ou{nfX>RN^R#wtwZ3>+xxWW^l$r+clmg334Tnm6)k}Uzxs%JA0{4)%FYZ`i*`C(f!w;e#BV!HKO#|Q$a0-HIt+FE}htl zXTK@>Ehw#tP?o(I;GYizA{Z3Hwzylk7bjlGS=i(vvS9GYpM8aMOF@0X6@srgysD7^ zgjlLH5;KJlMV+i<&Iq7O#mce5o0di_)R$kml#tpShN#JB4Mb*3Tf+*42}hip*C;Kq zd3Z{eadM@-+jw;e22^thW=^R|g*rJ)`Nv@W#G#6|f4d!9XD})yHH}R`5h^bN?w53y z4(xss!I)6T6>8hd3N(&|r_Vko!u!)zc$lm~Z2kriOKMNkw9wCti(!J<5qycfG4PN$ zTmxkTK$@DvRl8$dPdS-*52 z46lDY0D2Pro891$;9vURLO1TmhEH;%RQ#M&ZGQW4Pfw-CsJ z#|lstw6PmtayZP+=s0;#FS=+3R18}JcN;|j6CL~Vto_(G=S*s?tDeI!MDEKp8f07L zWp#0TUjmni4w5oT{SZ`TDN1Oz3uqAmBBbBppY-U=B|?UR^sZ;17VN*a~nOT%I zn;pTI`j$wuf)+9_nqb^$$LR%9Qu+*;e@px4O=v6nD*%Y&5n_*{Qr^~8%%@h5+QbRn zE-VP2f>c*^KcAhYA)yxc@wwhhO9Lfj5Q6voxlX--)irD#22{Sf1C z2#$iN&=-i&VePVkQ3mZawa^kd+JD_g2&F5zYV0w2dk@#8E-T`Z!-FaOWyOd=QHakq z;6IK}%X`_uc?bA8EB;m6&(Qju1tS=3wc0uEInQa+KW6iKv2&j26d~d$&7hK~znWL4 zVz@%KDbDyUf$T<{z>~a#rY=kXqe_nDx>{P%6kzyhRxfSiH`8Z>`By2Ty`VDfh5~gi zA?t(sbL_914^P8%Blw=Nk^E5Fe%0y6Uz3mxY&v8xc8;BbsJ0QVLh;Mp@^+CZbntYV&`}`w6{3n;TF+1#%C`zZJ-kz zKfXB>cx3!Da)V8*p+<=Fy>$Z@W2k^oc-QI$<$Bi-jvWv#_#odScd}9O!S|Jfl)l)D z+EXZN8gB;goFLtg^`Pa9irFwFoWydsXn=jgPqQzZd6@^5|Az+Thrqc*6iBUSMw_{& z#06bhsVae-Aky{U#8z%amj#?c?lK*z{qgC6GH|SsWNIB+fGbud6uxWdj%q_hRo{aX zd0v3SB#$MbLG9i*Ra2SQvd7W@U9602n26ZTS5pARfZp(Y^LWS|3gCdHtXK<+vFOLO zcWKDd!<5ivq#BT4+}ap0RivM|0he*tnu&VW(5HB@%##V_XEkO&=8w8hHLdG&JF)8c z!EfvqlWAqva+Hdjab7VNV^HJF7gItGsG)P*o|Mt=2DUMo9ciX@Ad&gEcCVsp_Ac8I zKTwb4>ChCjAtt1|Rn%r10Amp!qxHsv^z{lPCtIeb@+=zJqN>1-9u4QaY^^bEFq&5> zzndz1c)3Yq@y5_0JhY|{d{E+4-R;3gJpYxQNSG(-z<^yIZ&Wjnk{a%sQX5}v;!5~jEBmYDcjsPr z>pvY#gmS{S5y!(Z1n&W)8^hqRe~B4su$4~mg-}_f7UrW^%;i*UoV+fNYIOZM?f(so zqHNay{GpV7!~4o4RsIn-;d>C?dpG4$>%r}ov-}8|H7n26gLaA5Y{18bqcKEBPR|-V zicKQFlA~jm$kP=(O!!g_K?^zi=pa40i$#Z7e-kg7?}`H?Xg+>2ZMe7EQ=-8_LfZf- zvx9zUsf7C;lvz4<81aTJONE?Yoxs0pWtJ`Ip0qwC`0R`#7DC4+$R0BG^E#ZB+%-TE+o*yoT69m0;qgeF}N+l7^{=fQ3x0R#kOGiF@7H%8?9 zHO@DxnO9F|q}L0Xhe#Ak$}XeJ;OVl@I}O-1`;Q$T3APDmTMR;{*p^5S(b%3|Wlxel z-%G|2x#W?Fff*Gzt$DYO>71(Tb|wxe%5=SNDW{dv z(N?n@gl6lOvFpX3*p~QmIT0YP5=hd#_5nd1`+V>o3p@JQwq_3!=sVdOV+;KL{EWOi zU$wjp@NHT&n(EHwzwXQMa)Eu{&3w0$HqhliP2mDWjZdsd?@R`-$t43TPs3EDQM|}W zk4M%2&k*>-9JZqiEleH|@)o_&c0CE=G-$k3neYh8fT)6I{Osxt2&E0httemj2V0Gl zNFu>Za6lq?+^>f{;7T0`!kcy&N1+%%k)Xi>v{fUOa?gDshBZMMpn)|qjXv3YhZy`s zvM7Af4k^}}`r*wr2aC6XSYM8{Imo1wbm-xbx`t@~pNf0^U4n`M75k#NC7{4hKb2 zWPERfUEiSCBDu<{Ec(frYDKn5f<13P);e5h-B9jsRn+pLPkd}ma{A(zRCyJLL9XCd zBWg+dFuH!!EDJH`Dva(j#+q0jOm=V3oeby#Wh!Qvd_Fn>-}!qn>yWY1p1RsO~|@7dzYPj(d^;-uKWVPatvG8Y%-B=$0JgSc&KJA@j6Z^Y||rbU?WF=L<9z> zDXRS?AT}Q|x+p^Eta1cskYAlMt(?|67tK?NH3bl38&&&F3N9J(-LaZ6(Pr&3v&%7uSjn8<+gAW8pGKWYKM2SZt4#f^IdUb0#dC zVep>f=78QgWYw-VH+b8cz7@#W_{LSVF>{DM3hG|6igrr(>Tz!uPgnJp?ne{dD@w{; zTLakP-exK7H^>1WGR9M7_bM2n$+HJ$@2o~`+#a%M#*a!^cr%~YANXG!bJoc} zk`f4|=u@-2_%Yp1P*m8dIU3pfdr}Q8YZp++Q43MYWzngP$`L=DmqWBaA$za&@kgEH zIJ})faQsJms#%q)55>!CNC~D0%R2gN4ZqkKrj4;t-{-G1j682lqQ;|1OoWAxsLXuwtnC;} zlYJ*uT-e+yhI>fEi$@;XJpndiuQkt~ko0<$bO!Hutx@WkSB=#S8IxNJ_{b7onCg*S zwdLjGWi7LPVrB-3ctCQh`q8?+53{njRy}2Ey=L%Uy*Lt(y(>XBcncV8EG=`H+P3au zne;eFNz)V%lfqw?*^j`YLrQ6L`_#Z*4J7rXG~Sd*1r%`}by0pcsy1Nyl=!^VFkqBu zN_E1rVhD%(#}BH{KW}ecJ*C{+pzNRp=OmXrD<4tt6kSWk2%8$k!h^DcYNFvYAmu}Hh_II?cZGD?3gee>v>YK<&|AS-@Orbu)pP9lw@Z&Q?iT`>A+59< zngrt;3$I1mGZ)`PuMJ1f0+bMWapD{TCLo8EPz%eYnsw72&Qp;|}$ ze;D{3kDH6+n*XAKW%aQ|NP>1?W)3=_p8{aa9gM8mC?U>?{)`cifK%y4iPMhsF)>Ha zn*p4S@6B$!V6^0XO;-Jsdl|g2?jksMPxdBkYdexB;7lZ&}ts`?!^T zR-e`X0fI_V*v=?Wn(Ec7aoT^IGShw*B5d_eqGjwI0k|Zx&SELfSldK`EI8l}2R}F@e1`uZ>t#jOHn};2`&Vl#4(Go(>W#d zAy@U4ah~Ab`^m-S1%6W)?f{`t+RdgVXym#5_D$Z$yhd*k$G%F8bCOQBWf@3!u@GL8ru=u9EX0|w)7qDtjNXt%V31x=ScTw%Qf63A1ViZ|V9|y!NyS;sq{TkZ+df zyF<=aW`zi@m}I8MhKMX)7Xz^jAAIHs zdA6E8+Pgi7{kp>GfdB7JLwW)dh0F4~joTBJ?wUFL+C|qZ;!z6i8&cn5Y-=au0BYc{ z2}fgmGDe0*n|bh51=?_Sd_4Rw93c!|7`gb{G^sisb6bbTj-ioYabPWGd`8A+&Y#>u z!`&h-Vg|6E2`n1i;-raGVBUc4>(yaw_4uTEzz`m_>+J!$b%Uf zg|S>wmMw@B`KCc!&MgLantdD!ED7aq-+)-aNC!R>lcnu2Sgb-W^p#dsTRJ*^&MYpw zsS0pFSDL76{$W0Lsb|;ZM92WRN|j9fzL*F;LH$>+MgQ-w1+EN;_#9p0J`+b7%H@N~a;--N}y8v`k2DGY4rv;VYdG_`q9m$H2p7!?fU3sLmQncjUP+p2a|ANJF-&la2+Dx z`9OmLP5!i>pCafhhRP-sn~+QN#w^N~w{>I!%0fy31b&3=1dabZb042}t?yE!y#87j zMDn}9|Hv}oMB-1+)pa7#-W#K$gSQ#6gTsV35AXeq!mR=pW`6>0acs$eRTRUPxlVP* zTAUdr?(f)MzNVa?EiIT60|vl8O48_HzB5m|a&P`5lKPW%WY#9)7rURRF7U|u82_dT zS!);yIBJ7dI3&_ArmIx`W!3;Za7wxYBwue(>*u`>>ybRWTlK-FF@`%lwRG`>PU*_Y z+&6%-xY(u)pgtN;x3V~Zfay1`sZu4;IFr+l$Y9i&_QG-PhI!nun;f$dUll{6nw zyftkHU8mF7rMFM z4q1Im3GQr3Qg?uHQCOj&R@6As(DI@1PXb`5hRwa^isY^N*nnRzZB3#8A>LTlo4JNf zTb?<-hgd!sSF{LpJ5GVqet5&n06&zoxJ~b(Ob8+ps`Hv5Xf2F;O}`py-6UWFuO2Y} zpX&}Ut_^_duv&a`x93I+mMB!Pn0{gc0N-TT>e)hM{g+>P0%^vB`La!?ny3+ZSaE(| zAFp^J&SHSzLCL$j1RJflhiHU(rnBoL& zeW8j)YB8rJ7w^!h9(+9JVOQoF6bG8e)g$^AQnUU>LqhF}xrI$y7gWJe}1%6C-0qQ<_LiP*P2s1d++D zkgjeM4l9VZBM8#`;v#Dnt2`L`IDM|5txXknf%^-_?fhN|@8G`Qh=Rd?pq=u~;~B&G z+wltzrafN)fd(!BmLpcw)sILo4pzvMq=qs1tx~7+o+NpjBWcWeQQxFj?UH#{_=(<= z1>}#F8XYJe!GgCO8O(I%qv#`>mSv=* z=Ng;{FpL`Klmh}{S@9&l7||rLfcVv*u;FL-VHZE&=9=n9#04`=05(&0N;deF^3lc zm_wwZ3%rBX?_sye)19M9>Vfu%8{0<{&kfWNR~+e;A-qq*lI(FQZ@Nw*C0oWV;Dw+{ zRxh6<+K~6RB2nAJTiOb}Rec*g4n&Sk6>z{e)0n?3mUeG9p}l?qk!Dh@#w? zTNG@$2KQKtW5&j_oXz)E(o>>J|p@`kVZ@*%R(;`516B?#l_SLJ{Z*Y&J{;4Rv3KkiY~eyfCw*B-N}SYiXA_pt)~ zZ%UqBP#KmvL9@6jc*Eo}~Re5l%_4{3jBUoPpY(UMZyOX=x<3!byul zO0T%j!vTX;N0DJdL>7{U|2wk*-v-{^q0lF-ZJz8-{pH*viE*TeG&MfX|Nmw$6vNG) z!a4lxSpW37cLgS^B+LIFKj6oPM~O4S4Sb^U`*5o%mNIJjnWNk!7Iamo_(uP71pwdt z-97#IJf2~6Rv$(88t)#ci|J#@`YwHF_VX12QMrpb_@S&xH82)O*E1Pd4}yfZ`5o=2 zQVWaAw%&chtfysM=!vZ3&x5!K+Cqf|LBag)^E8Nfpdmg3UTAy<2tS38r1UF2DhAP~ z;^$gsQ*Ukmje_FS7h?saryErh40YOtf2UwGF{{9V@_gyo{Saus2di8ER@!?-s524e z<+jL&zz)_xoS4b(a@|3B)xfYW_Hg&zvb0lSOEf09F~|gfSwR%vBO; zyatPXj}W=z{aOH_{K}FTp{0Gr;t;j}i3>4MT$v6WF;((atV=~D3@vyr?`6LtCPHK- zJ%i5_S1S^2sGw-x3E_|2mD6g>z{iaHC^3I+aYskGHKwE>XmNP4-?+}N9?xlCP&Gd?iQZYr?w9P0Mt1xSKU4*77iYm!KtrG73!)x3 zt@Pbh7&jZJTe^XryN{&U1zqK(v9-?5 zWQn}`6BH6=~_74q$tn-hyB`Q>RpM$MZR)?WDl4QaRy*OS;0Ud?{8 z{lj~{*B=&gDWQ+L|LS<}Q5zcvkmdA$93b#WY*>;`CME1GZe>7A#(8ge>0Vw`&+Mxr}Xq)ZI)f7k)v>MGI?4PQxXLAGhG=b zT|A4@++Y)9*_8lk=u9-HrysTJp|#;1Q1_$cTMsAXA6oGB*)uS7#`@Jk>p{ zK-YONJpE3Gbt}Xc9~x3=lIZzenFPFKPx%zq70XZuTI~tw8g-}{(Td7DTi*-u!QtK{ z=MbO#cjK!Jl`lV0LadBh_>LHJ$M5Vc<}^Q3#(@F76dpP|+_x^@%=RAmg41HR);k%;yDEtAzExgNL_=>G$>X)?@&pPXXRMUkf#X>$v`8H+*^$$2^+to*Eo5b-4c0KeCxWF82;3rLcg zPc?G2u;_2D6ggW)O|UywwMvdWZ&l{U`H{e~OM7jB{vYPkF2g4MsT2L9an{!Md>P5| zmm&$H$t-DICPxvBTHrFnomv(Oq>1T$9`IPe%mxR6!sV3QlgEGo0m#WZNjAZpH=s)V zM}^`g8{VKF^FY4kI5sGE1ZegytuRypEn<}D&ep|M)$}u!u#;6=q=%8lmL-V>Qyx+H zbsL?nb1aORuP$64$>ZRuZuk2^B?K7q{AV78gex_UbF2?PigOTpVmOMr^S-OR_fE)I zNVHa{8c=0mxE0IxyxK!(>2t>;eYbM6K9z@;dDqZ{+8$^auhcBd9A@4waw(4 z21(#*r*^3GH|IpA7%5kIT*S27C7$bfm-2Ji%^IIeJiR%&Pa`_!S~L)Hjgt~|=~h@l z0V{kGED6A!*jmnNRfUUIvX~;Tp^#YtBIiPzcR%g%mVYpB5gzaee~{v4%j?m4-a=x8 zNP0N$4p5EIqPDb*UJB0k8;n7|o7Z)^#B4PqLHcS5cNI$PtAqVC~NOpFCU5c9=_ zScXN$2SgSzrY!5VVQa;J-U+dK%1QeSgU8_w^y8H2sqN1<5Aur!i`}X>IhceTQR6nA z>V6({W`9P1oH!9$!{6sQ3Y@kJ>WsMr#yVMpI|i04kR{u_hr#$PO~ zgMOzvko0S1{DRz=iV{ge;LS?IpOa%eg(15UBj`U+~Ou{hRmfv)0ToYIG|*|feuTXfp3FSiVPhVF7NT!BJDJ(`JVpQ1xcH0-15Z~!2f|uvi(H%L6xahebx`%eqWw73=Kz<{KW<0kTQc0R5t5_>%1Ym! zJlnXt-N^J?cbZmMIvT;HJ|@;JDG354&AiT`f$jk*Ej|wzGBu8MY($)hC2uw4CR-q> zv?7@bP%4r9m612pWmCEhP)NrrmOvx`}UZY`f>Ys_t}Favlfk(SAYobN<(WfL`Lc6#=raX z(!q(2k9C%J+z)^XmGF;4VFb1RVlE`%A)ZedOcQ~V<=OaTM1{r@co4zD%$AiI3n4B9i1W*T2OquZaqZ4D|oHaEuK%14hD{&k|ELf(+7WT)DF z!|aB}dPS2YipfOEei|X?1hcT$M%ESq`JiqK2V9nUV5$cZCacXeCGSs>?Y{ONVEO~f zMAB+vjGvvj!@A{8i3sc~J8+gk3}YF@lGsq>-rr)@QtBXZ4PxUhL!5y(LM!@)SlCM6 z7yVsP3Vyy9T|^q-URrYs_w4MS{18$&rYr=jtTbVq{mvVFL3t+)okiC{R1V$(ggq5z z`ojrbV#dKH`>2^vmh6}KF=;kig85#GxvndT29kC!QGeZ9$)$4uBo?*F!(BnrFibKF zBP&TNMilP#w*+Y!4xJ5N4llm2;3}eDW&F=*6XG^5e&5P0B;oH1R6b70`1!?nVg*Mv zSVNnIcOwli>K@s*aUehiBm!B_ob-w@Llpirm0v{UzVhM~U@G$xLjF^I(TX!D%h*va zX5ji+GO0U5y?hY?86ruqwlHaI^%zyJB)0tOWvg3rrf=6`NFpdwf)t)K#%a4$wkpmS zb-apSGUz3D_I}28%H{Q9TzzgXUy1^z87I2MwJR%BxjlAZJjjsPD0@kt9a)CIV%%3t zDut+6flE?7BC}A17Q4fS&CxQ22yH8W7(=4A2lbao)!;%~Mau@mxE0^+uJ>%6D0#@S zImo9J_~_pqy*_6(?3r|W=r&-ccoB~$Jcu%@=@yJ9Fu&F8^3NeCqsR7DkC{(_++cC7 zI08gy6U}09qROJa*-@qN4bGCb5nKC4DA{|fTe1V78T`5QNp!a-HE;D##XRmCw~z-H zO*|6pWZ(-+M5fyDtJ#g&4V6#PpH@9&47N9?QBD4NfVH?{wdmrhQ>yo^(t5G0O0Qu1 zJem_Bh#kspMh<6|qz z4t<4rRafkHD9<)6(hx)Ae`+HOF_`A939T2ia<|^@pIzm{c|{>vY0SZEjXeb%v;*D} zx8j$3>#C_hV4BfiMS1bBJu&gkN44=JMy8|FMb^omH=ATY!J*;Vox{S7O&vXhL1*~9 z(AX@;It2Bi!`+-z6P?bmh}35d*v`D=zfZraqLDFc3|8mdGf086b(UukiU3>q2vCaz zj3bJVrT6UF{uA)db?`o9sGZ^uz^owtK|={MJ#7wOiVjGL@a%$iA#*SY6m;#9;SpQK zPw7xEdha?;fIEJk!1MlOWhZ}m|5x-DDkZ5UyonzkFHecre<@V^vw=m+As=FGbbpkk z;vzWr$5b@Obx^jFFg2)xwTZLnQ?Vp5h_2>mLywH_lTW@``35;6T-Yiyp6P`5EZ{%6 z!tWX{_)hvjye9F@3V?t1U7wek(Vu&fdhG8_A#6No!v)7~W-kv&cU^-!TUvejPw!u4_hUC5StgiPVlv)43%P zX|d3VvEAb5+sjjgX6A*meNBz);yb0-)^GFfXle+CF`(gSBAf}Ya#wIc5Tjg|Kt*I3 z<}_e(cum)fEzRG%E!@4nNzMThyxC?By9z=u;ICgyx?_~`91(W{>UuaI({(>dKXv-h z`ZNh<_oSL<37Nbz06zR48g}W@{FB}>|5~@Fc5lc%pyW`Fx37vm7kusz<1%lyM~lST zxjg~&qSQEWR{B=k?4;g^xNsPZBu>Q(PLM!BTP!6XBmx*G%f#V)X0lfU9F5ic7n!Pa z>9VIlKKC5QdC&K3WsP4!t7-OTMOEHmr@ncZG(cJ{c8RNxA@#91h^c&0??KyQgff%n`ZwsiIk!=r0v-ZS<{McOgO4(5 zTi@FVwWBtZ3xnfN!|v(W4#gdxJQHhrqD-ri)!rMomL6U&yYIP+((a(|YVY%Nvgs z?px@#q2MbL#5oCFCs#V{W5Hc*L+8tas6>tCps}v=LKH-yK4FCcJQo)FES|i`o#fBH zmbHg=^b&l%7@1W9wn&YLC(uF;)juF&^irbQTu9rw41?7bORc2g>n$dPMI{&V?6VGh zv~$Cej&5YD0ii)8x*5hd2TF15dzzwQyNyh_<*Ux43T-xc;B@6*Sa~%L*jDLR9H;0! zoS|qnH&(A^l-@C!VahXF8!X*nj>2WclwR!C`lorkBU|B9P3H4!Bx&N7(G56C(sEM$ zyCt>yf46)?KfPDcVL8%?@SNnNZ*V7j8q6z!gGB=85YgBi0O z%#K59S}53hGAL|o@bQSMK23s5&h^vH!p+n%>GyCu;{JOK+Tovv zvX?=!Xp4X2ylVJ&J4FQgmw>c_2mS9QbCrjC4OOi8xkdhzxVf=A)L)Vp&$cI8;ewU& z0R1Vbn~3tD#wUR9o!ip3cgI7<~n$k%i)IhM$@GFe}_dUeH49U;-V$KL|X}9?7DYL zY?3c!*>hSbZ@>3w30>;&QxwG=lf0muQ#@Z&T)rb|zvGRH6r*#kc~fENWb;fB-!&HQ z=_NdARtT%g_j)YnSc!V02o~6>82j_PzTK0bh|*_8D!63s|GyDEBp|d6%t3OCF?qGJ zILa{`l?^CZ_FNMC-uoVW7VX*S(`7``B4BG!I($AMT+D*U zfHzQkrYV|c!v2L=AUxz`&ut~eA`Xc2@bfRKnq6fP1~mDZ<{YaT0WvHrXvqmX&BA+J zAye3jtK{My5+Oc6Feoi#I%f;Z1xk%_;?&RS$iXF3fP--{8FsSRE$nM59ABOAGF%<6 zljengPe8DfRQ3e-Y>fn&8U3XdOarpP9L>7CVtS8w&r1DKfOaG6%7Z;d?1#z3L!I<# z%#GFqZpQi2&U;X3mDrsJh{d3=DhaVVhxTmT$Wo+b=I)um9u}L9Cu`tIY>P)glFR#` zr`E{e_J;!l$PJN7&f)^y{JYd4#k5tM^9No&O*VDbO&MYqB!_G-m zcrVBM_gb{zMu?ZvDAcaQBT+ciB&vRa1^4Mm+(B4YWDG_yQbp(<}f}OQLar zjxABlb+ib}tV!~Di;Gk^+7ye=?8@N^Xp6QkBaOmU3`=bAM!4>rc5&^uFU~S-p8M=J z2J;Rr-I1dD5Vkawea}e7n!fWk!BUcuWYjUEsb^$0os>*Fpogj&V#~wVm;&8`bRp@X zPO5l&5D8P|wb>i@K=w8=|VMVaU7UBhvLYXTsOVxwZ zC|&crCm8#{!YSZ;B_oynb|6!ZI1Qq#2{bfTpc?)i#!bP@wm6>-Zk-vu&}?#2s-C~3 zGx5Ie$CmIrO8~JS`tIlq!?wfjan*!q zy#8J@25(l|ochwJht3Z~$6aXe_-F^N-&6vv8gQ$Jb6ygSBoU8Q2zg(MM0#}Fxn8%T zpUfClXo6(&`b^s$nyr#e31-(dXHV1rHk%MIkXgc=uUI?&SeM94R|vLJ`~UcIp{Y;U z%?udTlX>FWmA?g49=3@G^{tPR>?oyRscZ&PnxNbJugoj8K~rN~LZ(VmPtv%Cq&&oa zds87Cdc7b1%rL=XWA~wjd*43;l%e4>en)kEY!Va7l6oEp#k$zApO)lrmEuqSs?`G7 z1_gi{zJNzgy zyj|8=BaS+5x*h7? z2RVm>kpGndv~z5#s}7~4Wew< zf3MXpiOR#BAXI;v5zS0u`f=I@W#<%#{0VansV#)G*l|%6P*652NzM8kH%}c79i>{X zbCeP@S@Wgn2LkL@>5-N2;6{a*%=r!b`pfKI$M$2B5JmVOHoQd2&0N`z zwsC~itr>!w6Z0m17A*o2C}ho!>$Rs@xSUH&Iv?jE$<==I5v}XrV8CQFNu0CRYbcgh zEwPa^Wia^C0~o4KWp<)P5&e)0TV;nWuk;+A4>E%71W2ND**Un^9lqzWEBcYwIz;4_ zKU?q#o$P<0HR=Qe1y$^%gj!R3^no9YX zyaoGWXMCLFAcK6D?UikBf%2QI7h7;|N-xSsu+0Hah6+akZTP60TWG(Yv(}z&&(WCe zSVk_0i!mQ)7(l>ru6d#$lb$G(y6uP6WQp4nwAWGL`LpTZQ6*S;ytx;>^@RGGZf)Z0 z%Bk%DA0$c50>j@eadv%bRkH}~tZe{OK&-!-FTF8Ov}#g2rnk++O<5ZagZz#ngY0gn z6?magL=y@X1CGpxf<9IQLsXYC&<@d~NTwo&2zVL>X1R{-k^@sT#_A+gkb#`C3|D!1N9WlU~7%|Uc9a`8`xvOixnIMi+!^!+h9IQ z)5*4?z1mV4vh^`ry1Oc`C8dwp=Jo=F%kR&L-)jFA7~F9atN;!h!~2P?^Kkq7*}DJ> zf(XJdm|x_JSW;d_!4cY4&A8pfWB|+!xqIwRn7=|<=46Jg3R~CS^I7-EO22>?ccViSpTalJ@5dn1PI?mJGjbb-&_ z+rnk)W$9unuZVhYzK1T;OIB$S&hK0igkYf_y|B(cLdzr~Z1xPj)&V2A(f+MC#-pc^ zECdrag+jHHivW^-esN$Cea#>MWIFK;kg|+@@#m40?FPa^bw!Ae&+E!!Mg60fi`yz< zxP-Y^bZg=naB?4;C_zX2BaDN55l7!YCLaTS5ZP6lA_2Wz#7{{){2Z4kN$qUdlzLPJ zyV{a4g2y}!WW>Hkq@_Cj8-@urFuGw(eyo0!*BIG(UNVtOOfYU&MoZ9bhgCC@x`!g$ zouQx#WCP`rr&oOEIh}xXOvN=@p%;7Ut2}+?m|~|zsZw;E z3R<&YgblSRml#H}qp~@gE;Gc2VQP61n+jm=*lS()0^nDOo-~>fOiw9YuyhqfhwD1?)HM~$N6dv!;rws=9g z9Qvdqte|kGN2K!|24fyTp1DwEw~eb{gXjcG1DfL$g;0%dS2>P8g|^nrZ*A0c z)bWi+TohC?gtJVAf0m3KQL<~##ee=7w|=RQa8^XfU=~9HcpBz8f=N!cJ!Gw?876}= zz_?QSffmZw2!TPHvZ@r5zgclRouIf(uyU~6xlV${d{F}*zJh<^e(@=`a6&yig0C}= zKw%#}ve%f}+IwmD)cqv{{r8ZCVuZ+88uNTP#sY zxV4gzck~_)d0|(Rg%0iKf9;djU(ZC0x<2MV5V$cd=X(|mzk$8gcQW^`ao`p?uh4A? z$ZEIY4i;20WJ>MY(sM!z8dJ$MA+VRH7IC%P*dhy%t$8ZJ?WNQNjf+uc0XJ#_LlV0O4diKfb6z*p0_W<46AN_3?xqre|m;~jv~cdyD)1L3iT{=)$({?EW+9xGk{`K3a3HM z>cVg1Jj-;IBeBm4F;YOWv67)%O<^5BFKgkx)%}nQniK5X;j+`V7R9vMUc>4^CPTAb38RhQr{t*DVCmj-7HTqVR)N=sI}pv_o1t zzz@Kqj*yA`U+*yu)@x~WMRl>OuX{*F;Bjz0VO9s8GqH>&e$e$jhJ=FpfpYgi))br( zBJPMEc)bem5cuW)`=V|>rYHO3PzMzqg%d8<2fjiix_`^-@`cTgy(a0;fOW^1vtA!4w$Wi`?AZJ6dEj=8pF~1>*V^E31z<*x}q{hsO z`NM23Vn2e!F!ho)z)!St8#Z8rE>(@J{`A->5=E)KWzkLqBt-)b8^as#M!ucfwmZ(M z6l!4n2UHBQT_rf=;vDo}ZB*xoOfLG@3&8z9c+xX%SZA90IeO$p$SmZ0Zh^3(w|dg~ z)5v=-lFHvmt%iPG5B-s%(}=2(WLj^DAD44^(v}MV3`>hS+2QqvueyC2bv~nuZ&=db z#OXvLU?zgcPz_!BrVJ9!_T`99h}O-93S9&v!{3{`3tcxOi`H}R5Ow<#9x;@Q(6Yz7)oMjKDG-I5B9$?<9s zia4SqwfUwAVrRYK^sF$S-N$e*%{HD!BVojbCT$Zy>a#H{P*8X2`7*`noUGO6S}eAB zzG-ZNeRAI8Hexc+3pv>Wd=j7KR_P#<1DeL-c)%e2Es=dFlnEob zDb);g*s+cbkc%s;n%J#~(6A7n1Fn5=vxF?eug7RYuVD<#P3a{5vG`ibnnUTi;23VB z`vu3!_$I?jrk2;)sXgq=Zxttex1VrBm4=dleRhnga>UFFks3y;exn|l($*%9lIPRU z0TKOIA&_}fwz+zAeRm z>EaSoA=RqGN~17My#(S-7zdC8)z{1HrIKT}a$qrz3N4?;YCV?%P%)(}Ncc)%p zulwn52r$C&%}pK#bEt8--N|1vUtb0WeA#bbhv;Z=9d4gVhIFq6?;aZ<7vBi z`;an3(hU3|Li)uvCgSH?MrDb=YfUy;WDMaS13LGKvb{DMpLX!Aas=2;HJi&)6VcOu z8W)LM?7$b^VOXu5dhkS>03IhMkyD|^KlTQPRz}tN$lCgd>bLZOB_lX9LXuEe*I0Dj^zEu};knOu zGw^@3{RN6T(fz}g8@Q?{zqj|5y4?rdrKLH$nTn;7gxLn>8SRHJ>(&MCStw)^FxADy zpq))?*Fx6Ttv6${u9&btL8ba6Qm`Y`rH=QAr(PBh;U0K%DT5S)r|8H$5V`xeg_bl* zzFRgBD#YW!bxdx}X;%#`(>4nf3)|U}4mMMaEZ-WN<4r`d%eTQZ6K6mc-WRo>Y*SI& z$rT3b9*;r@m&8j&4!8-6R#!5%D$7Na9?lTkhu1Y|u_ifw-j9dXYwhb){I9b1?PuC9 zas*01UT(Uzh8s$%dit%B``G9t9@bIdY*AiE4uh^_)H=AQyP_?ml0|Bpq>K`^F;*W} z)c5N#Gm7i#@4ls*aZU9+K;Rt=tAq3tqtIEXg1{qC^d*H@Ca2#L^h^uFVrqKQ+XnP3 zkB`p$cpQsNQL@_C*b&pMIDf(|0q}@xxMCQgJv_u0e0KDT zE9>ys0f~=_Ru!~wlCb3VkQ%^^+?{OPB<_PP{QxStp>CGt0;sljeSQ$r7s(Ex!u%|( zF25rGo!s1Eah7ga|i=Ants+9yrYe8X2olE~Bb(@@U1ivNAK zRq+Q)yD^Sp)UhE!5J4S_10ab;T3pL6D2=>NDou-in)FWqw5uh*750D4sH=ep7E08d zCH!Wp&cS5{$AK^}%Mzl$U{%_p1(<7Jo>f(vW2Cml6~N;8N?jaVH>^!iC^WX$x&hSrYsjF_|Ce(CoC~0La1RT z@oprUeP=-XR_zD`={C{Y0EorVAs_vZLNQmk4OnrCX-I5t|8rR_xUmA6K0P60t83ns zCAl|4+D0mc)v=bp9BPCcU6cP8YgjF9;gB)E<%am^pK-Y=!w%;y&@KtstY$fdcV>Ja zp>yiwdlT%ah~|x{cGsEpE#Pzh#L<+6mIR26l!ajNL-q z_N#kNZmM)3!Lmm-FEuv&=?j&sGM5qJ!Rx3WfLE$-j^gJg-IBAa^Bk)yL@i-Co=|$) za6`1Jywjy=dJzplT@vu;1}zM;$#|6{jlAL=i;AM&M*BnLYbmPz!>Z%vBfVdds#6<+ zj7Tr$F^C9!nM>iK@3NZ5G7fm-n_kNxrO&jvZroJF_)ks{8)r^Ik)=?Lwx>b%=}voL z(7vtjEfN?|jY_J^k-jt?ZkOQANug)-6~8@5=XsrpHluV!eVPEU6RV4Y=c%ftO+VKX5fXZ>An!`4(}dd+|Ku zs@XAN_+x61Gi?rkOyX)DmK?S7P8|(p==x@sQhcweV-@jzFO%_qp8NGDTK;+Y5Ptgw zyXpuSr&h}$DOw^w2C`v4gJJ2r8r+aS`oU%w1QqEQYCySBK~= zv#0|6Yy1-}J#iWw4k-P~+mFoSGd$i;`i#{9*H%#Pn>KXEXtJi_x3MQ3(pH3}uX@8a zMCo3j0ieU$o4!0xe+%N19W(AE7-vzZ*=TqWD?a@o*KlVjRZwCWV5`dn=G=629M~^P zG!Z`IrJ!XNK~c<2xF#vg|Lnu04zL4TVAfN8NiD&;n2}&Gf4K`Sz{wUE;OTX|MU`!X z55jwheHW}=+B-32fH`8|ygnH}b*h5Qs=^^;$VFuWMhc=A^8r8+YTdBcW1qi^1w`c) zYpMQ(Zc>^GynpXzd5lqIcD~p;ybN4=l!zuT>BpNn@5 zAxTV5GInhmHHCj%nMrnKX@dV~EU%6>J*Eo$t2fvH=De9xmbm=c=GNCzag!c;T?QpR01_w<5+xckMw2|wdKoH0FaWE zdtw$b&yMIGCS6;_5WVQ5Fk%nn9)?HoxR1o_DEN_{$g3ZRXfHep-fb2jf~iRCsRRg` zG=sV6FjuU}JO&o$oTq|*p!%$Zc=;yC>Zg<;001b#mSo?1`RQ&J!&%D|9{Q$b^D4Z; zJc{V9K(ECHhu%Z**M5{orP^cxrUIo^5{)}w*#B62Tq|Bq(-jn!ok)q?w>ZIeH$B-`~gyV2)!<{$*9n7P+2cX14?xX)iJux|J$jLP-}_@ z4_RAz;IyZ#-zaVnW6z6LI$COqin&S{`Pv&fn}pTDk1=5(C~{xV4HVLNfcKrUrpHY^ zQu0v?-{;16-z;dvHLfp%K4n8ky1Abl7apa@>7o)VI}m^(p=ZgEu8r0+2{1<&@i?&P z?xspBzURoI;gAA!PN(#U$ZWK?m=<+;SlBLT`}VPQad>GT+OLr66#;|((oaJL>uDK! zJ_y>-a4MkyJM;EstPZ%30)u^W_EI(*2*`wxWtNgwVd5j9&Ij(EFKx!+u97HP-Hmr@ z`coZ4@(3#lCgG{*1L=stX;V1^_y%D%&yLW7p zC>F0cTu9%!KGCp4<31f(K*dpUqU?coJR=zUo@QnG*YQzynl}0smbR*}D5wsz0_(YGF=@zRYD|JWN7h z{ovM>f{I(tE@}BIGCQ5G^@6nj?`#=KPT4Z=K@HdA>P{uT6mjRnKyY#WfW(I`)mzO}aEs^J=Hw~no_yhxg4rts0_D8ufdJUK-yNlx$H6xR zoib*d<*eKWaq5Aqo-G~j9Nt#h!37VoMLh$%fxnItO}}rEHgoNFUU|`Ha8#*7olBl# z+OeuW*PoGHh3oAr1V8>ZQ192RV!_uq8``&&VOf9`{xZh&1DB_0${j02--ut{x`yWG zDX+CdYrBr`6T=fiSavbbfO68=Wp&Z?bBt>JUE#d^%47+K0AYBr7Hw5n&LpmeG8MYS ze)QQ`@-c7O+*B!CB{{Rzm~nd4+t5cuJrk>3P=>Gs&mNO2`o0qs$k{aT{XtQ_q)84> z+n9n2E1@TszKcX=yM&Io8TP zv&YkhF10guEQx-%I8=gz8M8o;gEfAXUxDtbDc z^Tp!K?Xf)w)S~o6frbVtYhIJdH4+|8dERLA9ow2)$M}0k&Vf`8n$zm>RqcrWR;Kf+ zg|&!Uk)e7dqiFyDX=uq!maoz8p+5ZyqDjOSU`?uY5C`5fY2nuwP?uU;EuXof?#Ics zt;L7xY;SZ3Zk&QuSqIetBd`)7l2M#uL|%?RxEHxEAq?}XZnl*$HwQTfJ+EoK9vE5p zci>ZTg+f*kabdUVw&VjCcovO+MaRR?jwFp>Ftez(-Y0cFy8YFxUj;=G64yr4OkouL z;dtfjdgHU7`|}%m*ZMlMef+LFDBG*?no5TXKueZdKaKAx9WD5XLNa?i*+{{fVagv` zB4d?PDzE)PkGrnO6RV#YUKp}Av&1=)iG~&kpT)^ANhiW7(7F-`8$>$*Wq$Nhw1}eL zoH69l*^4d-c}5<>;#0x+8Dlj4?~wWBbPYBTqaVd~N>UnK3)6elC~#k78Gu+W4aBul zs7~6ER%9^ao-~_FM-1jW+j9)T=)oN#cI=nB!-)=Rv#tnRKKW(P?9LB#>m#vUc#yGI zGM^;NkW&wd8XVR$W)|=}EJriIVqkWl3W~g8rBC}o%N4L|ORZi5RdS72Ry7ZYnWayd zax$n-COU)g2_^zhS^{C3vYQ!H2i-T*O1_hhX4zoAu?8 z(T%5;*=kc@%Mxd*xk=vHWeAga3%&rjj7+vw?Ld1)$@Dec-;bBwaiSTlXbFu`=+kN5 z?wIVV#X7VE$);)U+0MT_=VVfQ(as4R!su)c)qcXH_nts~D0$T3T_lSzqUy>p!bt zh?z~5*5gbugjNYd2}62*Dr_C#C7_XP!U*& zZ$|8J>ZHLoWZXqu)RY!X;StF+3_<|DX*;Rq&MAR{r zd6$B^VbvaWN2&W~VX`o=%yG5F*C>G0EHgLS7OWiYOP*^c%C1}ly~xuAEE{?C$4cJL zsz@2K*z9%)Ci-36i&=7t#TrkywS~0 zmRQN&CTHp)sC~2>eilObG{{cRxY=p;5l`D)2roH^L8-s{4u!BNW7BB-nyK9J$!r|1 zRHtjF8n&5FoUqX;lSxbn`&5QPFOj-rKW@?W{L$=)UQ;X0!|kZ4_XyHV@X*#n#C&bA zJbw!`jLn;F=vezos-7=M4J1Upr8dQhsMksv!0{DNk)M6yK^~`940P&^PDZzNYdUgT4Yo6GbL_z!@hSShKPprO7)a>HE%w4*wjv`E z57Qd(4S_+GGnhJk#W&1VoYv`PT7Z+Y&kk~k=RwjK=%J}G6Eg~`7?UPUu0yKp$n`~TXqXU#isLPgRqvW$5mfXoRRsGh@hn-G)93&B{)C<<%X7JUz-=y&$#P5jfg zf?_4W4+M_O?V<3<=4wvZt$aXE@E+WeN@EnIjOSh~jTjS<#`%dN2UzOTJH4 z!C945MBNp1650$t+LF}11V|hay>gRin*cf2095`f%WLYy#+#OC!yd9{f`>PFj{!4J0=0M!&4W5yX?c6C-(74!R0L`h=|$g*+q z;n!0{jFG9*$j1L|5QxW9q{QDeo^=5;s$2wD5tb-G5)cGpkTurWsQ&gh-c$q7XishovfkGBj9BK~L4SUG23x@=8rGw7+3MmeT}4ye6w-SN zTGCszXMUQ=_!gzdK3|ASvgc1ol7YhnAmNmr#5Dc%306uZa}9sd7c0GAeDf$$~QCaw;C!4ZZlz@Qx=}-SZ^%*7IBu&eayYPNGECLou z-I%!Nc=6Szi(rN8c?673zt>-yVrhzV`c9!k|{&g<6J>Lb-aa85+Co9dm|zXNIO*I z;|YwlX5p+A(TRf}vp?izaapp@nb*?{gyZEiCIt2i4Du zY|yfXjk~l<8MK(2&ryt!M}&vY_N4`x_;az|ma_^u!cVf|Ltd3|* z0D6V&#czf7X^k#}!bsN@AW4szr=OlN*N=id>Rc+ zUSI@t8+2!;Hez|XW+7Ql+%<~Lpz73@6h!d2q?V8OJi3RXYHX+NOvN%>CQcMyl@LDT z!#T^#xAUW}nprft9eWCxJ@DrXNMZ+iq-asKNCz%5p^)q=+n1-^#ulad4<0>_;@hPT z`mk$^6iDrzBHdktAc1l|;q1$ti~*mS)J|9Oq7Llc4+V(OxU2K!wTM>!t=z0RvXa1% z3|+HV$F`2cBg|zWsG{1cV@#;SJuOaZ*g8wCwd)253KWI?ck-b0a%6PE3^zXyfM&f6 zglinP3!q1jFtx7EQ&=er(!sipOHLkWt9mk=J67#!ykfl@W?8j}2+)IMd{)EUZ;TtI z|AuvASz&^$bi%*qsw51>Fa& zp;Ru<<`Dk)9aAL`KoDI>i?I8tYeYq0BY_i(#cI=iyxLL=wOf=Mw|3oxV70qUOCawj zeX#DA-UB^Ir{>ZqiQ&Hh-0Lb;6u1l^X8rg7dLSQ{V>{V?kW{NmA5VyzSHX&!X||9i zr}_N2dSe6{*ri6n+=u^zGF8@o3k}glcXYSnyFySWcGC~+K8H(9qnLhW*19+RPBH7@ zSlD7TM9;WE3I7;(y%!=gkA!jh za6_HlAa1I=mzi!$)sx^d=;d<#jOsSz;tPyn;fgB$aOxd^Fv7nx+|HM2v8jfH$dltm zR9F{#5!RU?ILv0o(2l)kT6QBSQbD?7&#W^MC#@QnODWZtGe$f3G z_j(hdjAQKIN`(}GXYdNRBW<%UYFIiB5@+_ZTn18!IdJgzL7b&Vl*fWH`U24ST{f{4 zhB8~7zTs9l%2-CE9Rpv(9b< zfGPHz%?V<nY}2vpvr|BvS8gx8hlgu?;7uN09Hc zZUXZ%CHNnNP5e(B<*e~&+`EZ~F0Dx=`%Sg z0#SWUnZ+Rd9rRs9pE;iRmTeTx_%T0M`mjrzdfU@%#6FBH21?DVu)eY^Fr+?gk+jsQAe{=+vC-=iCInoz0SrquCS^)rsb|pEH(vc z9MhX|OM~Gh0~ELsv`cr-nsbCep*F~pzp4V#(~e#eFmHIFEc|{Yq3K zAp+PK78Pg+G{_C>W;=ma{{mo*H|ODDY9Mx_dj2A;u~8fyh|PC-zr|vPM>652QVWdD zO_cSDZ}|pjFmJA+FS>c&mw#ZO6;V?O+z&5tV+2xhrY zxude}g`(|n^e32ptHJn5`BW^{iE@~_i}&U!-rnHl&IATIhg=A=Cft$C*SsxfACYRqCdv;%-4&}5kUE7V!doT|&q&!vCx0vK z3iX!`PFFIH_Nq%yO!))X%nL7$2U5^JRt#pms`9#K@nrHSsl;Ji?xRp^p1tS?#(%>9 zFwAQ_`DZcRA%C_mduavj!H&JSiV0y4wuh=(cpjId?!O?kQQoH-^STDg#fFi;Yy;jMfS()ZCZhp%9O92}kX3>L zQgG|^8K~6p^VsVK#MdMJ<&I{|h13M=#Z4eXwnyU)h&@nQyw zAqaxb(E6ObS=qG(xvvfl0&~>m1>kz)5~G~>Q&$@p3f{j$Srswc)OMPi&+cYJmS{l- zzY8b`dhB~%F^4PH+L{KrRliiW|ARNKSpn;TH~{w=^}bgV&hQs;e@`bd&tK;ThMX_m z4#QU(tgHHFqRaI6vjxv#$a`XO zPr;wyONJ))GIYz9VQh1K-#*P=Qnu-sBS_j-5u`YzFqJQQxCULRx0bxC9x8H*U?hxQJ7DAJWOJu`S%>mV@6 z_#;C3#2QoUtiP9*EqnCOjAq)l+t5HFr|5YtJILjds=p$m>Yyiu+;hOOTu2>PQFnu5 zBI?YX8Zw%A>e6eZRi!}k@{tP0`Fg>ft);W}MCHJB*zi-=3c4+vfgn&yjg2c+jl4nf z7u>tP1Odk&IrBgqVbt0MB^kRw(ge7kgnm|Jr`n(&nUfri&lXNLM0mDksI>75l6$f(Mxy4{(b-xf-Tk;?n?N@88aZ>cBqCK< z%Z0Pwm8+8jG*m`X>B!p)IL)#7)H=Uf0(-Z3S!%fRzfx!NmyX0Zkk*U8rI-%h55@42 zJkU)i4_~5w!`Kp+N@wUabqUEg_skap{g476(i&a7w!(&oqhP$ zVYx(E~ieT5APRS}=h>?`;&f?ye@u zP%sg28u9U_md3`L>k6oQT0v;SBxos*(f+NqXG{q=?t$@PIE8g^sG0`sbBu0@SxF%P zpj~JDcog76EFQv-MWswf(gy7GxbT@!we=x(4-@!LiPV1J5 zd0W4lyN&Dv>k%-;s}Qu=+>6KGGK6kK+h~sxPyoI z$E-^e`@cdBgh&_Y6ptDnH4*v`eY|j)Pxw&IU-WdhE-2e!XJ1?Ft`?TP=$t@DhB9o} zB}zxZu2hzR=ofh}1!2;wKJx{BWWncB)G|h>edP@_Wj$j0g^*V?8O4jl3X(3f1(BYL z=uDB3eOuKg4|=`iL!vVS_Npgq%6zuwU0+At;YBAVMq*P+!94eHJH%UD(UOds0C+vz2Ed#5y|F(rwpqM>}5zZbZr40~uBt_T;oE%5weL ziujzB#nP)*TGCQmbR12s^VrF3|MhvkydY$<>&u5%b;f8Ii7^z}gG6*F2hOVUBfDt} zXhgDg&k(RYm*(rHWROUTlZEu<(vC(7;mH?CNqT0C}RZy6yGxNuE8}djD`Ri z#Q-EkhGwVR?zd%ISl8|2)m*f~MM08dAT2E;qgw30^fV9_&&=PQ4(3fV|6(aceHp7z}>-rFJD0EG?;UrO)=uzucJ$XtA7xC@ns?ktVz< z|B_vg1C2C>ni&`~&^B?a%10}N5autLr1HE|XHHd%%w7R(@U{-qsolRz$qO;wgW;T< z0$`?a2KE2VgnT_?B+3fD6Fvg${MGPFap11zH}Z_YnPfZRD&qQN3jad?KYr_m(^-Z6 zHcW7N*IizzEuubt+?akX9fcXOLOsr&3U7|gYS8Oxa}+oW@b>(y%xC?R58 zo-`8I|4#s-?sK^xwM>vl@ZX&zzaQxFSb$|WU>*6w|4-%1oT(*j8#9U%svQ??De@!0 zdwF6~UT$rEAZ}1UTZ*x!6pod;p)U2a47+E#<%$99+(J`A15HUQh<4JB>2oFNMMMU) zG>X4J`rfhRax!)i!yP*(n2EY3iVQ&(q*JYNPCmtEk;qMVKC02w_DT=3v0(uPDR1t) zXrXJgULmj9{Th)eir@zO`v;Xaomql&R5@((XYO|LzrrjLmI6>gM53LRdSpEU^A)A% zabH2!;_yB;)o}0Kyu{xfVOHL(0xe|TzB62!LY6zsI5EX}(Oz7rdrSm!2F`r2(D>i% ze5v1f-5cg^82?zO{3Qzf7V9pQVKGQTWhVyHmRkdvX)()Rzgn~cin9-MIkF5%aL$@) z8i}QtiQLnlF008h95;^g+bBQNy{ybGcoGQWdC)liHK7SW4awP$`oR(#wqhkXsBoF3 zsLrziytgoOdht7pKE$v&f*xVVB#qH4Zk$Ns`Y!S-Im^f$)z`j`buaBpjTb6iyJN zNd4y5SO4y9Zq*CUc7cNt@L`!DeSm58TSeCDf7eRVaP54uL~q3Fw5z`?Ce}|{TSi_4 zZSs)v=9{Ii>acIK@e!bZ4QpR-7@$XW?tlU{dp{{KJHGVsw{XlP38!)?u=dVMoqQ z<}Gh6rDJX~HE88`Sq||-$%+JcOX=rRHBFJKf9yMjbwKs`6%lt{1p{RNwnML29B zG>sNxir|Gio@KBmCt%0M?Ht6>(bFZf?{TxoI1MRQ)}wvq)Yn_rLm1CWef}I;tR{pN zTElPfg8;hOjdK4mClOHzM}rFR4R4!x)gq5Y7z-{nr&N}+)>%}yWLJpvaMJo)jzuK4 z`pl#aK6xjB2iCkrX8w6evca&9e#78|y~&n@=UC3o(q(6@1!6c8RMK}Y>(Mfs!PlGd zh}SAB(q;my%Uz_01Zu`zzkF6AIPRb~<#x-e7J$$sp4zL_1m>b}8N@GN#v}u4pEi9-(}`>IL?xtVHNe zTQ|!<{+%I2AD7NYz)RE*>`ah~8E(b-t$Dp!Dt=R%A(nRy)Mq5?X77_QV#tyOGRzw? zjKpKCK$SDp-;0GG4nl&orj@s4ib#^;iXFFrvsdC?7@nnG0fjcllN_HTrzs~;@YUV3 zE~iVSnaRnUAt)A>;`jWcm%Ev5<_GCccUf&!mdBEv=AS0(Qi#ee0v#T?woB*-iC~+k zbDfE9nDLexlwMe09O!-kFc#r@~z$V%5tPXrH} z5%$ui;Q4k+Z^KK1{xr&)vA@UiX-oZn27b%7WOqo@;tWPb-_Ls%iOR5Cm>=w z89ke+?^S-yN~hzR+}i}MRIVaA;LMz$5|W{_oF3B{34kJ|t7dK(9R-nsdnOP#T4vNb2fEw!42m?JJWvpaq9)FGk1UxMjWhzu?@G>z~rTkbTRALAT)oqS^sUbx#cB?7>?V)V_{ z9JE4Qh?go54CqDP+in)`aI7IkqO+^pRKwm0gWxxccM(+ZVu8#-Q`^lKG3at2t%aat zA6S1f+<5&)%n(Sz9JE8 zf{<6u*C0@|lLoZ$DVrcJp<8Jmy1?|v7kbZ9n@fDdzryPnR08M8t*sh&sZOZLf$u(s zv>L3@{Njk(&FcxeO^(%1;!e@5(6<)aJ7WL+mmS~Ay~>PUWm++?w;CL(9mh`OZAi;0$`kgx|Td z(?cAk!0A$0@jOn^we}BBjqfcY|970mo%qsOHrtF9TzW8&q79U$BB)pJ<@ zM=_8;t;p>N3pWuvc0A8Coi>96;l-*|2`~o%OtrEbinU0@pV77!kvZ9tM!LzvldpeI z;I+$HUyu?ITXj1ip}cJkpy7kkvrI*IKMp53?SCCGwDzdZ{MAw<16pj&(HGuxRK3GQ$5mg1NwM!)!tg3w-c_f0 zO+T=h%E+ntW1qWw{3fng(#l_dwD#*^>1D|X<0?bbGCjCiStJhBoH$cw;Um5{rzzF? zR$SO0SK0r#FdEi-iZ3E`S-_#Nfm@VXLSih}p6=s1aH?Ez&|U%MODx~sL8ux+u*Y5AmK6^H9 z(3hS3)XB~zVG1fspL#VM=oHnn^ibqSS6{) zly7%iO37F13#b1qCInt7URau^$XsD?#1!F(*P%F$(tpJmH#=D<^!+eJcKo9b7=G(s z9jhHi>W^Lp-hA4)9QlbSyh_$ZEg`|BImLOGMv#gJYTVp7q-An-tH>wNk0hI|ug4p5 zdaxGL?1x4HHjKUjH?Z9~n-2j0S23WAC)cuSTe62OFa;nB83A|S#X`cQC1dj5Ey(-G z0wVBTY|2$jcmkWoN3*f!$WJo_^83gVNV!@PDCsEKTx;7kh@m}Z#SdM(+d94pK_q0r z1C3;KM}?{BOiMN2Oy0-LDK~c;jZPn*71giIh$OF?DH!6|sD9gXuG_B1l>S8+l`09K z_pk#MPVW=t-hQIF`)Xg%KKI&n_l&zXWEAx7H4p&~a{@@XjjEYKO^e#+Rd17_K7ACnmA<@T zee_&IegHE-70K^~Rx?sB=zzS{)N(|ruHuzLx&kEL!;vNJ3jw2B-b*I}b^z<<4FN}A zsm0$x^R9bzoV(bc7sRisR8$h<%+Y1;?Ldhpp@la!!F)|_|F^XL){Dy@gGUumCc~n4 zy1X`4F_UX84`!D;)olF(^PwcfR&gx;d07JIjyZg#+^DBMa*{AtWBq&DYt6kJa%zWd?+= zdjnKeG@tBt_dQIp2;{FgNu%~(2X(O2NR$o=$}5l1|exEWrdG`*f9l&olQ@DY2=qUpwn5m1w+8iFy( zTGO}GHy0Bc%-ifX$go%X!lxb zK=fHym<7YLV37bnK)}CFoch_tbR~Pw{>Tpdq?i14fTS}<2J+gcU7EW+@ntVc%GiS1 z?nBtef~}rE@kF$PFjN0TF+;5jd;ZW2CpFC=nd!@vwhO9PERMmTn4G6Wy*wdQUX z9iX6&)vW$8;irkds|Wk`tF0@^YzA3?+$k>5-DDhNeW0BmI;g-CDLOf@Jd^x7Y^Cou ziU7r*%0S_G&p>5EGmqL(%f%+M0D)4fsI^e!g*@b ztwTChA0FC*DBFndhR^C{R=&MvqWV{BcE@Oj_(c|JkyE;RhFno!5Exal^^kf@XY^}2HiF0`2C z<8LmB1R(C(Kj0>>i0vK;>H+WLpdlfLR%Ve@RbzuwM=)TA40h!4cwi$z=DMWYgNr~q zU>4_7y^4?-6xK>kDZh^r+8Xi{Fxt3MGV%JnDvYLlZK?T zgqKI!zNO-KH37)lF=MnWuhdWdP9qu0(Wji!_(095zZmz(b?t|QV zNq4;Ood45ZB3^eTaj<*}L_^rbfA8iz-lCW7)~I_pHJER4mZU>eKtxM{y0>7hrP6)^ z{45)AD@lLZUVt}6^R7hGL;rQgKH+<~o9V*JV~_nVVZtC#JXOtnfYg(g zk#DGU`5}#x_oJ>ATFNR7nE^FtCy>3Kp$>-PWaa1uFH+8%w{U*oH<=ZmZb*x7&|s3s zEjOmAzyQBnE@o`$$_8_h;->0lmmJ2%0#1H?Xs~q;{U7?oLQbkLr43n5n+hN(f9o69BgICI%!CaspE}u?a z6eLa^;E6uM^;YwVT!ZFc0@$5{_1MxkfDIIer|Ti2M8rZOyblkK12kA0;18Hv>QOLe z)oD_nyO8)>uBbY)iY~1aT7>P6Baa!&A0akB3jIOn#u8ZIyQ(;OuR=pRmD|e@7t!Z> zKR8wjyF@T+hrZ7^L;04!u6Yx~wuZF(W)5wKbg^X;aq-`VMkBlT15H33$&k39@S;AO z{@FlWm@+&iLBWvhmo+XBPcHfWV^QBAy&3Me_#71jnW3O_72i+G$_7D?!MKIfT}0y^ z+b3xn?el}VR=d;4+Fg_@<1Vu!?J)o(xsD4?`n%Lgh^OqX|7mKyYIwwD-tKq-hEfDT z&yDQ<|8xCjkpKZBV)i+)GM|IvmQDegiGJMzBdRLfCI=`|Z{(>A$6_B+H!t{iw3RM$ z3Pq(y^H>@UU_**BSAUx_v&kxq#ZA*fw9ggviM9Tua>6pGmH3Vvefm*lZjZEEHS{2PuV{XS+86Rey4(6GK+^ zxyZR!)N1U~GR1R)+^HR;T%ts%OSsDtx>@jT%2?;}m?O%rG2|_BIE+9X6-hAJzY)Mh zj~nOR0hB*k*Y^abOs;@wH2B{kPyT|omn0`m<7t?NZdl|JE>LV>eir_et`auFlFu(NAWztywn1WbX5zYx?8?1hc)6yYEkY|G+~Q}o0c z;%0aayrTqbB$-R7g_;CI+rX*ufQF8=l(q)NLlL59PV#JQ5tI``D636kqtirrSsWw2 zo!rTZ$U1{wt}cKerM@7&V{qTOD$h%MA*4p|u(Km2C&M9z*{^j^@o?6ffzKkIVs+r+ zii#%vn~6#7OcMs;?sBNH^68t5i*~5)SWqrh6E91CPcHI`t9YvR!yEy`M0f7e0PSbT*C3Tb4*f)9$H0Oa_byL899YJ-Ez2NnA5+UpXpPF}^&3@tWj?Li z#W_Ot_(m1Z$Z2 z#@co7OCYYSd4nJK$D)e|C#yy&ETPsBt=`R-vI_+rVE{mlUi~g)(m6=|N)RykZcpiK z(?(9q$)s+KIkP5raWNiNeErajTQz7adO{S)yLD{(`L!n5rA|Rn9(gd@d1Ae-g-QiK z8jJqE6Ds@jAf~qsTcoH~z%o=<9y|&l9~xF5I*>z*5JG+|6)X*#|9pmNe-Q5stC8hQ zr}5c%O{T7-B;d*lCi=0CT;VZs9Y+RID2`q6g;X6$=Jv1?YWO9kRR>x!|4#}q0w&@^ z^ja#z+{e!|zz((IOeA0rIha{w&-#AA#&t3$xq2_7=vg#2K-y+mDo zKH8SEGx;?I3Rld{pVEVg)`sDulzFGjWc+$}z02Af=MEkmBo$q` zH%HJ1mU_?Kj&Mi>5`%4PK8m@+!FP2F#jSQ@cdJn8m1*-Oyzx)Vg4s{be0> zLa`~fu7-*qPjDS0PSxTY4T_5T!Ur-f=Kw3U^~L}NwRsktqEx*79bx2H7BXL5(%`*F zMq+aZ>&4Abe*OEUm1tc{rmJ z>TMCNrcTq3$Jpp)T@to>i6$^?-66|a!-!JOZKktU!@rBL+^K3ySJn#`_;P^Rpm>P! z8}#7cC3Pco+AXiyl7(vQwC-24+YIKa99572*T{#~APg$0)tv12V>+s)kx2vM4Mnk@ zF&=V+Z{~0P(M@p1O9zBGe0=X=+fOj?{t*7$pCmK@qJ`r4?pAvcOdi<&N(_5u$X~@y zML}%y6#?g~3Em$Ta{4x6>obI_i-jjW6|_V`O^;?D5y%sT*nZ@-2|sO@Z<}w};_q*L zTAer-PX~5@_2Y`bWbLgsi&k~g+kX5q2tiyRzDQKeVYkEUiH(ZA=-m1*EHv)SrtVgV z_(dq4*9Wn7U4~(KJe3S<(IpP&dU5A2lAm)f9QL1ep@}E;X4~EYa=?4W;4VgBkeW|vK$G6QIVGXc6$6vI%pv7$*8#t zzeT=wHX6QFcE8%shZUn#_A&C1fkUg`U@l?`u$YMaHrZGEt4=`}+N$b1RG{n`_3x1j z5cB5M$)Ke`gMS_Ls4nDL;?52Lkut-7mzPt6Ly>80#4Cv?elM9hTNG~`sZgZ8$0!Jr zNDT@{)XPBpU}S%-RW_;>BGinR$|Mi%w+#Hh&Gaw+?XsidTC@i6j1b)^?_sMTb^B}m zbgz;@n+5NJl9@4SkSldCUBA@?*(qMtd+zQ+9M8P58yLl^+#s5fj2RjMQQ=WiDAydO zY!K24(;1lhJ~j`Rdkfq{nR{^vBs%aANQnO8Lp|%W+kjpYMTx8dzlUPQ#|I<9XtxS8 z=|43jJajjW&uk=H%ous3Z|cD8TMauPUf_xN#Nb-G&h4o^xEe>8;dE!eNRtP$tHXGR zPD?;T=3%=Cv*^IY)}9Ce@{6)LvA!!a0YRetS`)c5fxPkQH$`u(NC!qd=%w3A8Kma( z){X#kpaPbT3Crv;!mJ7EcB8)pTIV#z_1E;P;hiLl9g)$!SS+A?P>(xh@Js@+_{P|7_2XXf(0*s=U?Jb*)OsMfzUJDin$>RNflS9ii0M!-MpB+@1tR@V`vsHg zno;}4Tn_yTd$vd4Ha-2z6=)!5t!9`OUo2TGcLP4f+F(k*nF^M+C_S|T4)XD2)nB?L zNB*9dvRsL!JGR+G#&G7kmO{~s``s4{d;S`g9tM+*n4gnF&bfmek5&nRP9B&~7p;m3 zi@R?&UADasrC~t;3?ISFx2f4Iq<_jdy>Gsufwm4*_2^P**Tj@Skckn)6*}gpqmyki zkAwlNs$8g#zIM2Lz;L2ua#&;7uHAH63;Ywrn&sHF%6<80T>iIx@>{ZSSWn(dM@5z- z;i@Bs4h9P~to?IInZwZwfFg2fTJkCK1v1-}Q_#`jg49)TUbD(FDY~wAWZAdKGyhj=Vn49U)CdG1dl^e~fV6wi6JQ=)W^Y zfQ{oknk1#3l7blSC_D|Y@uO*-OzRDfdnxqE;Aaf9jiv z_+02sN&mLxwalB8S;o7(}#IQQ7k5^TOSpFZacjC>QEc(*K)q*Qcs1<-JdsVr(izdHr!WWZVU{0^Sqm3$sI}?mj2@ zznPmixmzqch+vyD4}H#c23C*k+DlnIuGWSe-32~n0c?NaI9|uhacL)BhYGOfwxzxP zsmC+s9Dqg4SpXUY!*Ssp8Zg!mb00Yxt?VlxtjCs;<0#+9rHnl4(3EG@vKe)N5mx+) zwCbhBV2unQ7u$2zo+rnE%huMGK%VawNXxQhBW)dZ6f$EoE@841M0F?6ZxaK{@C~BD znRvn()Xc5{WI@X)WiBJ_tlP;9?h_;F?zaWe=9c7&6_@H@h?#)`tUhR@0|pkTu0oZgxND(ir)o z(4bNFq^U<>iTLvob}!7-O91&Xb@@Uwv=cuWcxtFHs7Hx6Cn~^7gfRyfAJ8LmblJ|s zHu*tQf7$>qo^T;Ws-c7q4H4@%IZEyR$IqdL3+NbCyN+oJNZrGA;b+IXDMAh= zsXd=b{!p>;Cm4APg8l6eQvjhkXp|^|;Ka3vkLXVYQ@u{Fi?{O*K3Stj{Nc0uH9*)5 z(_#J7GnLWkdFo%Dd3%V@&Fx-JJyk3nmutIurupkk)T!>8yF^{qqal~NU~a_7iB`Bv zf(-RLqW8lK)3KOGd?E6X_ig#F$FF&3Qv5}mQaS-o8^?{`eKu>QfHSH9Zkm-(TtQmN zaPQq5p3Z#_MJo?bKu&_uCM9lcNu=VNnesGX;4C__d2EF)SqAktLUZlgOlp&)*s$QB zc1yy`jE0#MGk20%=eL;B{QJ=Ok4(>r4Gmz@@$(j<`NC7Zk4xx`(EcExHHR+=Gt}r0cXZS~1HI+>oI@BS>*HQAnNqU3CpADD zQ2;&&ZREw3>8xL9IbHtV76<+Y-5qUmNLWo(xH27)yl(1^hX!N-)&g_}b;Dck15{%e^^KWwwXbkV<<4fB9-x@FIB<&K z7vL6ONItZe8$i-al2C&QsJ)%al-g~ZkCk%lfNIZi*U5X@6FS8~zjlDuZ9fjRo{vLg zDlrU2Uz5;4Z)>5qjPG*x0)0hR>L#f--v44}9Js0y2j6;D9};-8?X8q*t)a0Ev%V4w zM<5e0JB-#^PVwa1NGcbrqEvM>#|q@^>GZ3ctdb`fjD}~R+ObutArDtUNvaL0pv5SQ*>Z$L;1C{qoTG#GDXN@%Dt_-C z|C5|gB*wq-c-SbXfZC{`pk)4JRq3c5bh3$xHe55&+u5l`GYeJI1-gVTI3&gmVI1Mf zs#v|;bz$l~g%efi3IMEn5Kv3*T6Yxjz4rbI`f%^I?APDPa)P zg$U9hcC7q@W;sQX9HVC00+w?&(~{AS-UHrnTQ)sdC++nqmtVU%v;*#_P@x%CP!nS# zM9gLVGkboBuAGj~ml&4qRq_e?bg#eW7;3D~U!{e+-wLI9jb=2kNPzA^vA89~NO?FxRz(wod*mDb;|j zwG!Dv%3+Z&9!>i4>RDpu&elU>V~Ej?OB)a{F=^^J0cdHJOUcUNFO8y~0>q{)EwH}m z(d*>IrU}(|^5=on-Hp1$<OESdkf6cJV zsz8nkN(E`WF)frlAdyhNAGhKab@Btt`o)jzHs9lk>Z;OMV zSsbHN_Cyi8y>?E-h;A_CAR$7zTchrl@O;l1$1}i%Xy^0}B++mwDG8z_mf!oHU95`p z#RB@I1zOJRprb1)DG!oT%b0GaiDc1AR6CW$V!EUMq`V;{T_2orwWH^f+rL=mF>5?l z#iuT#LGCc+=cJuuAnDL8&uZZscb7hvH^t^TP_XJNi3eDBwq#V|w+=44tCvJl)+6IC zvFTbv&E&PGkXDdUHKHPFtr`*lwjrT7#TNByn&Q@C5VGPh$R_LJ(2mKdaWwpjmOQ6y z@3WvwXP~oN(5%#UV!AD9;rCVsLgi>z&P51nd1nn=M&&E_4+4~M=PU3YNZkv7O7a?+ z#`$Ca&$Uk5+-Vdz`S11v;&Mpii5a6`#aiT3c>NQ+t#_yQz&US{GB}E7qdtExbH}^X z9smmb2usE-j`$(^T8s^3|7g>-sm|{zV-=ui@Fa0R2oHeyp9Cs$SQRYkr6D|?7*z^H z5xF8t7|NZlUM$ihm(sflvv;tA`;l~uuG-4;-xuu1+@r-Fp!V}PkkkL|i zpuiXD4mDw(yYA`Gh7aMTBmAryjR^^Vz(?UP2ucCUrqkYmHFGiVv(!Ef{g4+GpI673 z<@*LLaF$ISYR5Y<9sZ#5G#kcDXrpFRJb)H9pxlYU?BW^|OtFc>4EsJ;s3{AY_DA=2 z1NXJyf&UoEqeS_+cae9Z5$Q_(b6Ki643=&MjO;uvmXGq-<5EPDPWEJcX%w}<9n8c( zj+lr37PBp+QJN_zrKOK48>X@A0ufKzddN$iZ~(59MqCGZVOKG&vs=gy^e0CAjB-vf z7K;k0iHZ^y?o`H7LwmM4VrZWK!ocN2OgQ-{+AvAIMD>}Uxp)<8)b3)A=-oXZjj?)+AK5YDsv1Awtm<73}Y_Npym(;o~PK_wK@;G%xa; z?mh*xrQ~syT`F0G95+v^x1X(W)pU8HoUJWAfFZ3if0-{GePeA}b)x}ilXLOuF`n>6 z5Ge$KU%@SmO&w&oPRTo@42QYO0l+wiW+>y(a)RWgygOyWY1a@=QIVExB1nQceiL4K zzR1LmD&EPv>yHB@hV&MB%CEpBA;^@}F5@sp*(&=dG=8-t;5iuBnhpzI&UW+#P9^zY zViHLOJSM20?&d|aTy9^+h%&WJbwIoR(OmUFYtPiy!rTurEFeFSrMI0)dG#zOOLI{WC_1CF;s2zRRpAL?mrlkRY*2?ZWa zam-&&mriHRtt<$C!A}v>m^'B2=~wK5NSVod}y+l_%vh%>qRpcpJ%NO_3!DgrNm zD@Sz;5F}T{Q|%&;ML^-SS;O@^S6IB@_>BZ;nMjrWjiseV|6Xy~;FJDl!&0_jN5&EO z4TscMxxJGmT2Sh}gdlIt$;RD5-(Y>oHCZ(LFVO4>khOX*kdxAv=zc(Jb!DVY0s*5rG( zj60IQ&+m+*5Z5^k96iz-QEk|^KcTDF)PGK85Azh2YB?Pxt!A0+qqO=841=NFc64Oq zQu{H6kww3EP~5|d?X9kR4ug=(lt)9_e3_ijdAgLy!G2lothV)hQnK5`VkD=fr0O#= z{wS#}#RzxTUws_Aj*s&Fy;G;wbuRqE|8mU_MNjPuO9krNFBykP)G9u)4v;?6x>Y?M{p_wq z-SeBk{)VbH=z>0mN*R3thwYLQvq}Y#FB7#*EEne9h37h{tFjel_jVTMMBcA3IxP!I zvsu?3z(vvV9*g{?SL%)WN8$}mx_4Tn5G;az<|k|7a5cshaoZ2E0BJt0Y;uE(QkQQD zRpa_+@WwWpqhXJ}8yfCfa^ABkaq(>!I@EJ~Wgel`HOBr?l>AHK!37fd02L4ZqaaG< za2H&q2%|0m@i{ry?z3hxdcCoyspcBlnM9|^t^fz{S|D#Hx+Gr|^p|?I$;Ee?SBwA| zE>T1D|GYy`%O{!~JA+DT^-piXCbx2>^>_g!p=l|;)$uCyfYu*9sHpo-E&-2tX=LOF zx3;%~YSz7*5u7{j>q~s7-$Q04T9Dh~Tl^SjPo1M{WgTn&KdOD6#v5qxlo1_#U|Sb@ z{lL9l)bkfUDMCJMi;U=N6D0PQg-)GOuXL%>v=;48lc;yJ%3|V__gW2DgQq1imdF$V-OQ@4SmYzpephZ2KnRoXaM$ z$c$ohsDm#l8^uxf+~0~;+i}L#p&g}&$|SMOI!XZhk`FYl84)x5_u8i zZKbBu!NMM+dEWfxZ`E=cp=-~$qkT>f$00W3)2N$W0z>UjYOT83`B^`Jg-qaE-sXJybvQIfRZo*SIi%W)g&-d5i3_L> z?Oh)tdb^+p4JX{a&p!&x`wx=S@dajyf*S0Xk}Q{R0LH0_Nq3v{?m2muMi1VBRu|UL zbmwbbwjS@XCWOqC;aSij#l}W7jI&}lv}3C0$YkYga|lOk7~C1QlO{W`CFOi2vCdW8 zXv8{GBw#<$8-36xQy!`j7p+qB69TCL?FNM<81844((q-cRK*)a!`pjLOe;jpmMIzc zW0WmM@gNqDNM=Cxe@tswM;Z#fcMt{ExOM#HOMiT+A~F({-eR7&Yy{!CbjUyJ`^=bY zzp(N`a4?FIX!XhttYEyH+u#jUo)K~=(B$Egs{!w;@~VwSA_vP9v6*Bl?hII+Q-q%X zn;U!?Vymnup)MfMkoDl3GkwxRuLI?l0VE~bFlHA=>EzB#D?)FdSHL>rJ($zyySOqV z_l5*V|BY7)?d=5_#!3m)8EN8b^#%u!tEEE}uD*t%lIa@kB{m-1;JvxP@B!}sjn|nT zP@@`p(D-s(dN6@$=|CMfek?;9bj_Xeet7~n?B;(7YsIzJ;zUmyyNkFZuZfRYeRuj~ z+XuhE`P-~!P3q0?3_%uW5es*fLtpYWD>2JP(d1SB?ng8aE{fdE)up_4`hV%|_kIbM zBMDSh*-KKPw)#c&R(we~N z*~=~b$ZFg1=+*j%f=VR$N&rI>_~NJhhk1wh!{@!E)dGA1i&D~Sp zNdU2wac8E~OIDIM5xT33a+9taS>`CJSk>>i45w2IMt07PG~)aT?2c@RX4P0$f`UvZ zKJckMGLQ(G1)oWToLSHet zoY26Z+O6Bf(%5$3aou6s71izlPzwM5M$l&)U7|VA@BZ@-42LMON)sS{Yp>f-eCosz z_LpW!jv{z-8Z2A~5|=_PXt#Y0%3o;BXkX zgxipbLQSz=v-@_E_e7i4gDP#|P&#F&{}1Nmdb{w!GCkmsS7{@dE}D7G=N1RdW$>>T zHW!*@=)JLiCZen{^Js#L18DYlz8%IvS<2U!tSq{mzSoNwhuT)wwyYg0_e6}pY3%CzM)gB@=*@)xj(R5DXWufk)1UWk&xTH3peJi&Y{>? z7}bYQ7}gPWw2P#%M}DVKC=|%pIH0|4)dGRzKKr|&JdikVtY;!BXrRf~nEI``zSfI|{^+$%+ZgV-@m-+}yKcSGAgMkb)_q_hkp`IBsn8+c1WFf(Qp2b-S+M45@ z+Xcm&6PN_{nbYuv`Hl4rT)pmTeO(iU{V2uBk}vw>yM;y7kKqm>c4t z*eBX#92tSe$VgOW!zvQaR~neb1x^HcE|h}WCob9+>5xKOD#ZZ#3WsI`PvOP##Z0iB z_hq=K693FTfW}ViG=@<%tA8O<+BD6{@-Wq`WtMVu#CA1D%X-PIZc<5P@K#geVXx z=eTKUB+eUfU3o!&uKQd$O}!Qp4#)A>u;xYXO5)c;@=l2lSfSC%#2eHJVaz8P z6sX#jQyiLI>KKpTovk&$GfJIWnHr|cY1j^8<~b!wT#&Ko=vQebgeT(jb-vg&;@ls` z@*;5-pv^e^1~#vr=Qe%9jA6VW1|vl}M=%;9EF2pJm1AfmksaPmxiWdcnVG_fE%Z9w z$*-$8^fNF0Wh`-$S&tp!43=KOA`{wOh&hu@Shy$T^qlzw7-uomTG!N!kcAZ9d2|AT zptLnSXt=rxnmITol3mlWg1IeMa^WW0f|;az}BW z%-Piep?x!`BxX2GSvk`$JIbvW@Sfmcfc6*wQT@sP02YxDJ`1fkQZydBpV))0E=)CouZ zb+|31c1xV zBB--UZ<844P|i_WKW^B4O+A%fU~{(KZo#D~IK}P8>nFC41kSv7YvO$8^cn-DZ}i&Z zeuN5s3JI($4kp)qgdP5ht`Y4|8A~(AX)F)NcM?)W^9nOMFdLPM?7Y^+ifT|OSXn@! z#<+cghsxgo;~fg`Kw;Rmk8{H2v3fFj$C*hxrjj^H=Q)uy?t}adD%43ald+2K{C7=A z!av=y^{{%v6b@%c{WX$%p1jL@ontiGn=)`0<#b3nu~vHprMAQJFy0No_nV1y(Xz60 z+U1xgQmA^s&pF2As=XD#QJ+J(7P*l$anaNdWFm^nrPS$}u%3RhCK*&V6=ZDyRC8`q zXhz&j*jnh9Sf6Cj=YP@Sw1=J_NkE?lXn?UW^>uuQw#+&_<-47Gk*W(fs zO%SXAqjCjD$93kYV1k+qD)}ThJbSbxX{x*tZD?%%33UAnsX$6hvY-!rU==Ct3AK?` z!n_|2K^D3K`vb=yuBFpTu3?*EkV#)+el%LBhGBB6tc)s*0ma-OSG2z_^^K8cCaud$ zr_D8to|Dl7(!GTz))ProGz@#Lu$TCW>`iHu`+R%D9W~w#DclL`iu`7+$b})8oDbQ4 z3VD@qp%!d!vQ}JMiC;ujld$+afIidicRvR#VqCyb%bJOaL5Rn7q%SyW5(v)Rp+1|t zRFO_Vo=mk-`xKnNb$BuK@4H)UjX%MjL#z~v9wXlQ?**{65xD9%)b;GmBZsawRxh9x zLD!(rLOtop!dcV*`1p(Qj7-Z|t7Rloh3aXcQ_D;MQO zN5#(x)bEHf6c8aj6Q)uR!P8)*XU@&8&7`V~kN#Q!vcrqu|60-|6d&qZ$kALH+?7}& z-mZ3>Y#>!@y-tXH>xQA11iCJZF9YoBxD{ZH>pcc)QE=q3E1GOqg7_)b{+{SQYHPT& zOv6pi9583IHEwy?eLx2qhVOJttCI{9rR+MGdKQ!aw#zalO!^^~v;eHL!V(Ipy-dEW ziy3FBIBqTJ;lqhNj_=5q*rJ|+RidfEpdI#-Z?ZU-QF{BJUFX)HH37jiu=OX1VoFTxhO(8Q{t#IhIj$!~lI#PrVb}F{DihKw=ZM z$o4O533{cJL3k)1(CvPe4Ba97TKtkMvK5fBmS{tqvyT(_L?rzxUzweUSRZi*M3yGZ zt1I4&uoFkex!36@sEZYtAsJf};a0ETRQoOdgrz4$x-icZTp>~a4U^^GX)LVk&$BwX z5EK}b0>lG$+0vZIoV%bkR3koSIF(*>dVT=gUx7SyYfyDg|nxsRxjx* z)n*oQ#M5Pct$avAMzUix`n#e@!u98*0N0l*4x!hMVPA4&kg!U~=xv~0S4(Zxz}W(U z43lZ(eayt6EB{A8fvZQ$DwqXVoXCiSgbX1n5uHd7;{=^}7}RLKXEGx=0GaL}PVby7 z_{+KkIV1?evBkGF?@_eDkLLuSSeHpJNXL3n6Xe}% z;$7<`1L@2Ekg5&Kwv6R2+~wD^t70G1%*BxV>TrihQnL{NjsO{$_)J!{SiJpPrSg^C zx?{Fzyq!K`<87lL-o?jBDql^6)`tX(ToL6#B>p_vHV8o>`pTIMnj z;GH6Llf!jAT92Jb&)T2{SMs$4{hOkHapP$3=_E9>1@@tjZ0;=5A*9YUCHak=)dGyt zj|Th=6Jbf>h=Ut*<-r!d;?Ijb*ZR?y*BAv|$$d2r@+!`WRyzo;yvw$s2jF;E^VB+f z`PW8ajm!;2hJ5HYaB~uL@7|bx4$pX9U<((iH#i!X1?dNa5hxAYMpR}dBk%9_U#|it ztcC*hkbFD)p2q2vgftrq9`E$uEcp(_t*v1V672wyn)fbcE5lv&EsB8J{tPbev-q`C zOWDt1jF{x2rP|Q-ZyT#{P%L{jE~UE@%wuBzbxjRurbQJ_aeWj+&g>k8FJC9qK~ z=u?at`M~iZpL`oR++QcP;GJAE_X(~pc!gHE8H z6ezyeAf@u3J+C5OgGw}>5%^KA2MH^H_gopfaVxuh^T-(#GmseYdMg&~j?MOk!{q7o z0^e2;xbH*$z7UGrN|ayjcKfT^-jF$Lg%N?pfl6_Kk?liA11AgSC?-|dSjUifDN6FS zce_U4Xn4=qL-KL|9Nu_Av&wwXY0A;n&xpGxun z-jTSl7YCUsPhiSq+20QW(D#6Q`6KJ+c)9-ndD2t`wlk+ryx+e-C~?{5d^DC33c1xp z`c=swI|+Sv0nfQMbB$D9?jI!y%E}!5U38v>b6qFk`ZlX(TP@aodOja5sTpH3gwJSN@B!zpcV#ASUDgpiy_+-OwP!g`k z7xeIuqp*L*LQU?(lQMYmqDvm;YvifW8kfd8>Wm%OQDK(;ZH%mL%fnw#uK`jX)!CE| z9 oQMe8nT2E9x*c!TMZRgYIJnbo7QgGRg#KzNHfDt5#aMfMX12p{pj~aMvi=CMo z13(89-nq|d+X&K{?Jn<*;+M(duR#Jnh!x!daYOaUk^!bMI2sR19r5rClZ1hEabt73 z5~<2w<~AfyA->z62!%CE>XJhD7N|bo;)2)yPRhG&!27idYF$P&IQ93Fg>#=t6EZZ? zMz-kEP*R;H?HWb(gV7X?lVUrnE=;D6EUf;xB%2ngRPMY~s<9-dT5qpoo&mEX?ev2h zB!yG8agwa(m(LxZ?;^s3C1w=Ez8e2WF>H6tBH%@^dc`|a=n?SXB7l($QJO{9f}*9l z{X95{gl^3DgD~15(p9<0fRleYsa;&i46AeY8n?I3^|z(UE2uQ$q8akP5#wA$>uL&(O-cail zZosm7vNRcq3h|S>0J|5#g&MjQD=&ME1ICcdI-Ttd%MyLcOy%A5XlQpEf%wH0NwV7d zWU7R|*6l!x^eH~e9Mxb&IcRr)ij=jl-_WIM7oC4bjHU7Vc@&5;#0+_%E=$Tyex&Q> z(E^&g4)I>6p9Oaa=PWr?nDM~YpuEqSwFrY0x4aAfY?)lgiHUsiUz!G3F}bAZw=>=iXbxtyF7HPD zBBvw0ckZYAVSxYFdmSQmXJUhDGf*oY)7j58oBf|@dcqnc8EQ$5G-RV)@PG!Rwh74R zlCtfF=Eq(dv}c$N%_|jQ<4GGoyn)a9v>YX&(imZ1NWs=7kH}d{x3X>b=r)w17Gih6 zpcCA*6&>JtaZZ;p$K@adlNwf{*l5~k(GU*#5lz+OsM14~Mdo zMBoe+*45Na8s+SBwkH0LRy9egIng9mIMK&83)u%;xL({Gd^i5WGB`-h2Yh6?X~+Y1 zTc`d|n%mpy#Jd81!$zt+Jc4R4CQrPgj8&?zIc1CsPKCSDk6k5=8o^mhJe*2hY3rtg zPrgv{m48gj@LrVa=B{W6?qZ-w5yL}H<8pYCyLt~x{sQM*K|=y!xkBoeA7$+ihjX)9 zTfz@w6;W^^EQe89SfXZSn$;`E194EcxA&A%nw?@@SxnoAJE;L2zv!DNE)%iknV@7c zL-TJlLM8NXd43(vEAJG+&)O`-;V*`3l(Sb)x;XZz*?e|4mWIrQt~1A*VS{;3V+ddS z8jUa?iE$p7xi-4B3Q4vTndfj7Zr_bw)*e&9oK9IkKirC=^l***9$rEZMD<< z{HX9|11?VAF1e~qAw9OPy-u!;a}a*xnj`&cu<`@BlB+s8^BD#?)zftT($vwHlAQLD zcjZUB>T0E2r~0)Q-ZuIOIQl~tU*BfTs_l|;vYv=T$>VZNcFC+FfY-UK2Y&4R9M3(L{ zm1aprG7E| z$CFyJ(4|$hxQ*F|3c5Axu&QoV*VK3oorgzBZuz3V4`1W&m>W^{%cB2fFCf71-9*S> zn8fh7>$L8GK5-uyKgA5E$%&TH)kR0+7NGrRVG!b!`*MvMaO^gC|D{F-ukA)dpY}r4 zJU&GHPy!pLP{@)p3h%Y%%ppTq3T(>8G?hVj!Wsy>_3y(r$`<^)12h$n7V@cGjH@Q| zR|tQIwa*s^czHH98bVsuew>!q+~>q z1t-QIuL{iy5UPAFC5HxnT}dYxlB&mJ7N1ywl#x4A_H~q>3hcrdI4slvng5@8uSUJM zPUfc0m~5p)e|@I)=?6BD?27yu(SO1aiaBBxaGs=8Jgk9z!vw$IV-T7uv3VMGSnbvF zrIM1H%d}quAg+h%AIkSpPt(Au50VAm3T@)503h6tqSC|%Gq=Em%|)XFEL~GI)A zGvAn24&y2rkl-&lVq6Vs7SPpuJi0BCFra6R1+@N#H67^n$@`H9$Q7^UHs*xJ9p^#u zJ;^Ex#iiE>P(4*!%_VmHu|>N0X+6wCmUD*0?nlO$r_AKm%rwSN@nHIo)|)jS6UO}+ zv?*=J6c>hiqSsZO$ugfTddSIP9(y%9ALVW-WqHwFJ z$+PQPWao&H07plwshAdk?=T+m=Y$^}t<WsC z{-ep#UcT6puGxJoGP)hyDy9#;nHVrE#r6M*sRkLs9ny@olQaI*j$GgJwf(n~pcAVq z?xB?%7g21|ik@n%QT;sm@^9#N(Rxgttw0y{boiW#Nlgjwa``u;kPf_a0BE-<5XWa=I}^YpnO`f6@`- zYX0-s4QlB4Dn1({!Awjze;%}Gf=b2_B)?B8i?Ti}}^SSp8gjP9QA^0&b zS{6#CQ(&pI{V}f>2Md<{5HP&koTg(nQ7OCc+>G-~LL=A6TaDzgH3fh|or-LcCIy7o zJ{U|qUzjmr_i#xb`7rkZKOPvlt?Yx3xy9-RLIm+D&NLK(W6Wu(k-C`&}vh)*8Ph1DCA` zkNHp_rS_#bQUvZ5UD`|f`XoHkVht`DlRjX7y^TR@-p?LkNmH~x85xqRei{!p_;F;j zUu9X0X90>6Dvw3BXMysCQUC9o` zV^cA3qsI2mMi2Ts(m6Jmz81xgqk!_S&%IXY52cDePOdl8*b_2(v;v3AwF>v-dT^3#geT z&7D+xZ|og_(Cat{zAFP=Oa|D*GYmp&p0oX|S~E1B<_D6l6)KSdTSeI!DW| zxRr$s#EM8E=uvf_e5E1oWqbp17lmKf_fG=KmR^-(ZJG;0wh~9eDXAU5CqpR|)D<;+ z=qOJ|PXP5K7+i?eUT0BlMs=!%L6wAFC6KeF_P7Z@eB=R67_9X0)qr^%mB=><%~jmH z)caIbfz^crj8hpDGX(#4ds|{d)o;eo#uv*#TRKSiSPqD9 zpghE~)cE!Xei%xd8z6V}YO4_IDp@rV{sC*rW-o<(MjMN>&BFkXb28#cEU_N4f*TP# z*UkSb!DhyyWx_E%QeudZ&zQGYD>|5Ra^%I-(_G=DIAWIuqvq|PZ(H4LQBeTU^3(ni zZXjj(dD2Go)-e<`0bq<9Tj+G2gxc~d3|l*z)cyUvfaj5sGJ|9wbvyVfWIuTBEh36X+sfg{;UPp~T4;QwJ(r+abZam{@n14wI>`4|_Q7c5Nu#`EJmA zcu;E4qtOmGPo%jx<>f)`T-=&AWePR)lyhV&1TrgX7;%lKiz7#VkKbc_s*gqr%tla9 zX~Z7uZYq+!Vh*MT)`MTX`lbq{*7d_ieTYsX*zngqcI9C3?X z6b+c{8AiT35Ip95Jfot$Ds*A816xK^yV!UcUF+<=_v3W455i-%F5#ayvwwX_bQzM3 zC7;vFB)g-fE5TM{r!3Ib3isDw>7hFRkB6NYFx59L#VrB^+S0Xu2KG1necXKoR2T%yCN^|fEkXlrNQiHk~M z(Oqisq&mthm0HVn^Uzzf7|kV?RmObk;z}=puNt94eYjk$HvdfN9pf=_5zw9JRr$u( zv_-c)Z}}(DGicRrwlkXWd128xR=f(0mXh8D2T&x&Y?00NniLAnkD{Xjt#arqb3Qun zx8D+FN!CLR0Cc^-r=gKPJ%4a-19WmxJ14y8o zaeQ64I3=dogGnU~w7HTB((bDI#Lzd;Q{4HPY~M|Hj$?S-+q{|L_HWt)9HQ;6tG z3e{srGPpEnX+2bW4bKbkHZjQ+F0#IAxk<19lkE=<0su>N*>1S&RL?i13(1OSn6g?2 zeMLNPP=DMvP@QkS>9RHTIw3Rq$~+@0ku{39wB%{L0oX?525D1690WkJ49zf}g3C>U zp2D*y z9mx!KaWRPFXN+sUn`;%x8p=saGjmbQK)+xqDH1~UuJ7(Zs49die=ZUn1?eGHA0U!9 zj}ltVU(b)|DFKoz-L+&S?v*Gdp$?71H@9PRK(xc7D`6;8%0}?0=%GPw=bC1$1LaxO zB^?S2X((#;fX&Rc@{(oKh|n>_H{WwFkXNS0WT-K+c>6JWw{%^C!Mw*LeteW=jQ>Tz zpgrzQ9`-y+(YRsxFTeDYy%-^hD_#paaIbL6q6|-;*=}Z{@mZ%zYX*vvCy4`tI02y^ zkKu2+v-sJUQ#62JI2Cz+RU%TB38nYp_s?Pw*m3VJ$hnPjx88xTjj-J z>Ffzo`@RtfR@7=Ig5Ut{s2nPg+3L%~bIiH?9mT99q`9nY!qk36);6dJZ6n}|@GfXU zEITj+r^tq0Z~o2UsvaR5Jjhz!Fm|d_<6^?6Z@~HO2iG2VDVT-Cr*vkrl%8n> zpO{YkD+i$_%Sgp=Z_UC`WCtri=4~odgGCDPiznDp8(FlYmgP^Xa=uD#OAcUX_G+08GwQ%2(kFME3zEfI z2!{4_4ZX8~4u7p9g^nwffE(aDbMZ^g02Z8LvzW(1H{__bPqf*`2ofhDy?UFTX?+A) zoGnVqi#Ys@>w;_Y_AbuQPtDvAp!!Ij3urBlg&qhWu)GmY4M|3+i=h8k3C zk zj&Ww8%3;f3MJ0c_(U|<1a1geK(b6&81qZSP!-EO_q;tubdJXPR^vO}9^m5k|X@K5j zPX_lsFA}X`;b$rkod|Axxkq?znKckqD;JBoXv11n9~7In`C9^L+sEr zmX%v8;1NE2iOfv0_Q(9S&mzK99MrLfgMA%pM;K9G7Etwn1`2No*vp>lXs{h7&3^ya z1jMV2K&OsryMq?cV(|Szsh}h-_Y(P#oSlU~{?+EFmbmj~h3->eiHt!2Ku ztGwnIpStBs=uMRb@B+xuDHPm95yi)zM7t>qW(yo8w;{^tOMGPuu20GZU~AGa$1yBF zh18vxoPl8IVH?NElNt?n%Gxn!l;ErDA`!oNcnDU^^W;WgtShp}^H!C<$pPRA9m_2jWS7CV~B2S)%1O%X-L- z6H-*{2n7ILS<)%j1Y>`Xjwr{cPKjJ{Bn@U}_CTM48AYoiD5uVtxEZEtg+X)NKNg%~ zkVV^VKH9(%7wp$_E&3}91fzIUOjEQA)UuZ&gScG3y%F~ri6P3x=3FDL+a78A9N8Bj($o_@|7mF^J>g86~_>oJ35+ zL-7?wX#u1yvT;9mjjn=z-Ow8XRb&knfY9EI?v*69UcBlBOyu(bIOBggZ+3*Iv+-LN zU^+hr_vAm;sjtWhC3BaOkrmcVD8Q!Jl4Mn@Gy8diNK{gBxr*EqSOM2i9toVNIpuA< zn9maJ<#m+=S@U#<(!|=xw~T3s`op(*y__BG8whNeaZLVsYiaYh!mL}UGukBffR<{A zgFg;(N#xTdu#h^bh+TZXbO(>ik;q2%rc!#L);qOp{fun`qfNCs5T0+OfJy{b!_@C+tyn{T`96mwEsw zqXPJgU9&JFBiQA{=S!CrI=v? zfHu_Hccms24FO`$8b&)rKYdTw!CnSRT1Nd*(C7O$`t(VL7)}(HxgcfY^-mEVs1(ba zdD#n(^%H5kjv1s-=;+<99EyKsYn`{wE|*7rQtpR%+5z=_(yXSe=%SV?5Zet20xz2f z%9jI8@_9w-U7ZiyIc6Ov#@7Op0(67bFQWi+psbT z@$>sXM7L8Vg4CB=bot>ofl$-tasl~*nS$FLaB96CfLE@wrVY!R)=o0LUi;h-AW*%U z$O6-P$7)p=@^kF1rsqnqiB40s&J}8T~42+KQHn?mlR$C6p<)8SqWS-AIE<`m& zZ#>M!A?Xp~_f6b5F8^HD%5f^-1&M=aBgP%vDURStpMG_C0(4}IYlOUFzt&whK6_$v zcYpis5~K6gmeM@lkh!EsA1w5H8!>Lsb}#7UYUiB0;1QT`ywA@2cD7z0QLws;`$7+*L)5N!Vi|8B#HU~l-qEDl8 zfg=OI{%L#Khz&c!p?av0z!RFA!TP?({9T;orBx~+VvZ@94``Tn4nzmBFh^Twbx1XT zp68>=OHZQVRZtX8JP4hX{7tH6MLJzZfl^@DAIZnr#(wT@w$ z%BkG$!=%MfkSa&u&)3}N|8xscf{N3vdG57rqJjVKl;sDu!Co@>f9-*2B>R&1B-YEG zUO@WmX|)Bu!Xr7e0A>qx)Oiq%xquVd&7q!Hu7{;*w?x5E0>&fe3W% zA-15h9qJqqQ$Z?zNNq21jE5NsT6ZmHcMetdi0kta>(TwiX|*vdD;Td(TqFyEH48as zpG=h@fa{fw?bxEU=ELKD<-JRg*A$?g!H(WTx-H2x{>pN)y)@-M&dGCZ9Zme!om?{s z-hyYLKi-GkK@$Jt(*wD37fvDZv-Lb>cU0{-NIGhEY6V9%WK8l(esPsUxoee@rjg7E zp37~kEywj|zXfP`pn?FY^33YfU3uZuu|@7Cd8i=QPnd=X^=g3`2)5mKJV=uRQ~^wb@m||j@dCbp^-kgib<>_<%^v{D)L{m9Ulpgo<$rhN2z5l z-WD-pAK5$HrC@wK6rF}Xkt=FETCay9#ezC5cnfD zwz$z>C+>Yf(>%MzMcUG7a`dcRS~8vZ=2rZR>+mDg-2a}AW1z&Z5dfbWe{@3Ks&vBC z-e69F^M4wFiM5}P7qgD&Nb9cJ5dSDLxBIk%FOC^1@}$Ejm;m_V`J<+T9zP`g1G30`=cTaX{L zGvHNLvGW5mVsS!kuCaj<dom_O8F zKpbjmuLIvpyd)+6Y|Jw$Q1Rq!;2X(fY$6b=87QmEon}_-Oe7;jC0aAWXxle;Ch5co zDLkw)4j?m##+Udt*ep9KDcC@)#y9td1cN5Lp;p2DbM-^Dz#4{&I2a2$hnA3je^|6X zu52wp2R?3T6C`VT#U?r-7#)xo#-m^X713bCm}A+RyF_;FsP?vGdS+bZvhXhRqO!8- zG+vBgYnF1JyI(I|!OhYO)SpNJops;)zXMy}p^vU^598*!-81Ae`>tlMKqaKEBaPi( z5Y1429j6lN!cu>n5D`0iq-K4JI`J+1)q~|l5^o6w$}?5>pZ=ajl)o;$#e1#T`7m2o zgP*TpE>8ISqzxrP?A)o6`dW+s1of)NbvP)32<)x1X{1M4^07GhDL72y0K8Hm?+2Uu zvcuhxNzXt{pR-8s^HB>LaDc{&(U;lOe5po1;aI)XB?Qp@Q!8a91icJmWp^#p^u4{) zqapm%{MwH9$A%!Ft_ea=NxUHd@t_2IH@gcXvT7S(Vx5zOB&B6LbG~Z-Y}RhVywc%Y zBn5=OH1i1U&>a(UEvY$)QyS-=p01FjgMm1_x_pbmDqqmALeS61)P&T<8|6vMu8D_TZ&8Y7!AQi z>G?CM3$9y4M*J27gRakZR;}$(l(BH&a*7(;O#Aq|ah{!Eaf2{P0v;BOp3(?q++$PN z&^vBw_`Z`MDp2tE=6Xm}OD0w7N00dsgJR6AY3Ug{JUQUNKVsC(nKhk?YEC#~-#llZ z#ke?xl<&r>x-5%>=nuXpE_NqOcTy&Giew(;r^?p`ckcD&9ec*V!em#rjjR=Y)3;Y* z_s({GcOvgrRw_pXJX6kh1&yLmBpU}^=Ct>w>n9OCqt|)& z$f*?E4M4xEgo=toHrjB*2^V6 z$K};X`9fHS$}Ik9nU;~?QMq@}u20%WBF%xg&y~E%P&vJT?9$+W20Q#TPt2*4)ha<-)VG-=WRe9(OFX^D^B^+-U;!X}zF zvh~4Y?55Nv-xX<~V~oHusGkJcn|MO!T{{fvp#3OLWK%&r)1PYj}jYqt}u!Lomf zzF!cbD|&-@wN;}-*-FgbtGb9U(UKm0A)|rYrIdZ`p~^f#c5Fipy>|i}RFQc^~-+k&hCCWs88vuajTt#JGKdiy|P|4h(x>@%TvjhQtHn%oH}q8&wBfo| z6aQ9{xLm(QaN(1%9ZLFd8g$8N;tztRfkMh^QCj3!tbo=cjGD%~<6*OETE3hEF4)Wj z^m}&eZTdx7RBqqwN7ap^hxvpXrY!VIJEn|{qPjS!;IyV-kAd~6)sZC*=;?Y5t!IYb z%O-#Nzs`YjPuZ!N|S~8`r_RO@WJ#V| z)#=svel;jWh4GW3m(EykshbY3NbD;vA;7qtlj+fhwus2-AkBV)A}OHLrcU|5tUsK4 zl$m=yZB+J2Q1g=v`&;gg*8mN>AY5V=Un)M< zMKHFnz?T~RX1R1TwbSGlqAoV>IT{>`J$-xb`=*0J&4~&CSIrMscNby?RuM&5d1#|# zYst_GrY&sp2Flde+@loQ%W|WeJDM z8U`M1QUz)q@=K@wiY`BOF$GQs3F8loBrMv^3=!qRFSlweyGESl8n+lDZGQ;my)TPH zw58Clh~Hd|3}W*LzJ7%0yC-ISg4idCda}wH;C?N;0VV##95E1{wE$V|M%K#Q5|$Z?N?k#G)ZvbD#3c#T^7$p8skH;^NILRVMP#Ya zywFE5dMGZ%B=2=B^bD0j0)E`4L-d`fGYW&n9IEcBmh8F~N*oT&sJSdn9;UC&8H%gI zQePc^jNwkEW%acT*SEJW?jGx}+n+k}B+Yi_^Dz!nO^XUq@z9JQq2%qJ4BrWMrQExF z6rG~?#zEPfv2mbpGWHuC52&@x9`YKd+$z>zxh3ecqtp%rNnb~z*JrTiDGvRCpGfoE zw)cHsq*y&8uYo^f!$=#l?eX16I>`w}g0>>y=H%4Y7w(=X*Z?VbYb_gxs~AP!LYq4@CJnowx@yf*{?V`cPr>_+hivO$#a0y%U8O9$Pl6BwICOb^q^LR z3o+0OT&dj6VLRUQt9ox3dZnadQzz|ad)A`9IM}0FKm`qpUn-AENEyihV;)Sf>sWn0 zzc_;x=;1_6kW+2uAyURBmLn6&2rXzyo_9@zkW=j^k_`a!ByW#Ak-;_jPd`7)*?PXj zl0{fjSZs6I>rUbq0kELg^}qTfuV$L=+3}otKMnsGn==5^tSElTIbIt8jq?TvM?a*) zqgZ{A-i2HpSHGdNRy(zwVUOo$4<}~($z%4r{3DZ()Cz8D$gk~SmrIXgNu5^ht^JzA z9Gv^%Rit&qY?55$yHwX z!u-sNrMWAY#|dewM9MYnQZ8P!&iJ>vWt@2$MZ)?t_Kr2uKKJC_qcd4uX0$dmIWo`&5=lReK^M_j60ZDsRKalhGk~z5Nvm-5 zPyNL`pwbK1`1By|tlY8*-!&+bT+1V*SuDnzdD(6KDd>DZ>%&r@HikiVCr z*D4rJK!B_*b9#s##1LM6Ae^qd=I1OW*&`9A1W0qKd(;Tj+c;f6NgBL+#1=DZ^rr?z zx+eYLLSEe_XxqVTETG5FoPhBxS8kb zE@FFUSJoF7jh!3QZ3T}Q?(KQ3`*n7b;MOeHPJsvPcr8hc*&!qzb?6m_I;t8p4EYAr zpmaiyn(Lln4qkOhOja}w&t1TeJOC3fy8;n34O`QYaN58%+gimi34)DRK2(vg+5I=g#w6PRd1spfw@tO z?VACzLKu;57%`}%M&$$U;B$I)VhwFW;d?aLgyo1v`XMC&V2Q-+dhQ}b3AsN`6fULc zZt4u5w8B;ZkDH6@e(vo(IuFX88?!|YiNHpcnc@sf0-gHR70OSwR?&1pfl|U;z^Xp( zE7^dL%=VpN%a8T_veNgcZAXW8eAxry|310>$JR0=(p$rc9Gv(3D2CX8L^Jz!on37* za$7MbP!W>P|4ukFk;{$C3{Nd}00D*F4I&uS9k1$RS(KmBk2>wQD5==WwG_-o&FMD2 zLo$|(G!ZXIJ8yNmU}gt*x?<=s`!{IUqOLVasE|Z@J(sEqUNm1t;ZDBq1Es&l6XYtf zJVBY{mVKoF70(qyn#kp{n+X|Tzz9LQ;r0D7zt{vN8N?{m+6KZV_@ zq)w*aZVpufN%;m(tKawY-^Y?9VY8*$bh-h1TS}n#Ak)%^ERr*Cc-*vZxcKYb1H&ub zHx@i=W{E=e;tnl`)GT>-Gws>U%?3Zw#U8r~Po6hjvfT7tT3RJC%Qz zR{*4FHz-niwZw$Nt^N~pLX3q-S*{t5hj54@78OJm&46fZW`Hk&FzhY#g;binE}<0w-f1Z*IFU;+PPvLAbPi~l`tnGDEg`go=8L|Qa}}C0dK%%i|NyIVLQGUh+%f z{^}0P17v;fWQ|gyDlF4d0vA=v36xN^T#gr7SC}u#in}_%Jo;3{xV3Y_GQjaN0)r*F zH4Zmd!pPdLrJaCD=PXaXY8GA(&CygezIwT})vB#(h!ziaRDsV6zR{cmm`EtCF22YX z*)eLW^4w>18<*7%bO+g>*pd%JblD(Kip(b&W9QR^O=U~xM}~T`otk;n6Y7grTCk=O z6cC<({*}v!p_K>+CH04q+A_41Bh%lxxYoSuMJ0`E}C=2fi|H=TX6fbxF$Y&UtQ5_4{eo1)SH^|9K1#!F66u*7 zgG#)hiWLPRQ)0ebY=q@R*3R$5pUA4oaQBCB2|Ih^EG4y6AW@^T#4}vlCw}m?hd|o#PNJS_FO`}U zPf1zw2%4gaW{m?jT)37U)U+W@QUbw=0 zW>6vfV)kIckF5&rKmP>c5h3~&PihjefFVK6DZMBPo$jS!`&CKdFRYC3CE0%b8Cs^; zYQYvci{%3#=%Cn|B4&y)Y2|d0UbbEYL*Y}6XK|GqUs4TnX3UsexjlH)0kOYt)B&S| zt*jdX0*^5kYsJZEF|vcxl<5eGqyPdlvZU_o0EKiu0jkA1K|L9vuA9vC_ZNG?HeP-& zQA-5DY_Q_Bu*ReIF8%5icZqQ0Z40K6%v|qnpgZd1Y7=>ak?CpH%KCFz>kMH`tyf|H z6%S9IDhw@y{Qxz%a+{?VhPGE?LRi=ayk z1Gb;D?aY!dcgg(@_-*bbgPy#~kN&LGfeNWX_8)rI(G2*(@MaXYotcz`{CI`s(rdW? zXIBbi!JV8(nHbN@@GAkOHgk#`AQkwDjz*5@^PXQ}_B~H!gy79?$g#pBa4GoKTGi`i zL?CmjcKizl_?+&P6iTieWQu4<3g*H{pY3HadtYyZI5U37U=6r&=-G#@WXvo+)Xw-i zD>4devv`#$_(@p=3%GGaquRcP50)MG)2VTbUWRv6Dn3q>rB?CWBM5_bHa@=|5^QJj z&tb4oqbAP1RxajpM9O_zb$)J)Pb&_Nhw%VEu*;RghdyI!y9q3UU|Yi&X3w`|I63Z> zi!sQiT0(NLhbRTei90;J)SuLodsme+8o`+Z%T2LZqgyMB4=~S5XgQ^mQ{4)_pVA+V z`r1&{eOb}mvA(70$Vw$Bpmg~-69!9QA9unbMeqW}k*qa)u;b~dah8!i=i9@U_3b!& zHuyzFMxeaF&9${Sg2`gAY|}EgiuSq)PT5DC5&4$dJd_>@Jn)8v+6j(T#qW)Oq>4dl zaiZ$unI|-EuQhW@=W7Vvnx%H*Mke<5p3z!M4)}0E0dMEZRBLoyCF+6WYau$L@ia`W z**rTpnz{$T4rg8mQot6-)jsMKRoV8xXvhXzcRb*FIQwEP`m41p8BkTs=bgpGljp#7 z{=rP1iUi$lwsZX-YJAo!M7fS>ksF4Z8{ua5Z$g9}Xb*pFU`{q#Exw=FEvSH;6lQKT zJdb|9N!xlZJ7$$-!xYGjGlRK$mVe}P|LSF-S{#WM`lyAn%|};1H_a{ZYNb3(Qfu4G z@{0WUMMd|SRBAm1kg5yF+}K!}Z$8%%RvQOBo!hvsig#&w<~nPLS`f&%qnH?UW{$Ep zp0&XIry5XajRo4$!oB3&z+6RAza0rM;B!dlv0VA6WvzJGK``IVY1hHOox`jH5814= zK6Y%@;Kt8Lg&g>UpeRT9M&lHRE0efqSeK~vj8-;GuzoyYJ?isgwm1)-=Ltg9R|&2ry2O>0yEZ}QV91EKjVmlSVIOd zXxFQhz>GphMX~B;dqR8jIeJQLa5Zu1i?yzP@%_fuA=YRL=hN`Ye+};cX$N$6nZIpI z=HNW^#1bdRWVG_&^!gv-nd77O$Dcv4SWEJk-)h|7ubOYV8@CV33&Fw9m*{{8qQ>#= zGLv8O85q@sonei;6R|yEReGqfEp12p-?E#GzwZ7FBRX$&{5y`7*vuwCxXS2o2(Q+FF^x-+|rS51m4k0 zb$`!NTxeV*T2NcteW^!_gmAu~xbPH;?RgUW3eX;`%rk)3rZfkeY|yfTSb}NgQ4EPC z$sXfNkV4kHYSuvu5%b2{#6ux(a5YC-!4?0qoUYRs*p}^gCdb6|>1t&)Y{8#fDEPYF zSH2Dm=D88g{$%1MYo^psz5C7k0}t~4&85%wBo2SFnp3uKCNFRi-;b)7Y~_vPM~qXX z2PVOYe(b9tcCI+Xv&fVaKU~r1?+sf1B%(oaYwfyQ-)7bfWBxCo3DRVRsI26VV&()t zz_&0jsRe0k73J3y_jFo(svQ~50AIeawq*2fMd){xpYukb7S}k80sf9Bo~s%%4KHi0 zc$)&DQ}Sym!NrPT@x!&l>(vprhCuxVDJMLMmdMAcbLanKP0bW48wmAI`j8&DqlTlX zJ@7lS(WF;8!6lBMxc6S-2TR-o^DahRjJ3B?fO8{l_br;NL;WmhD1CG2A@tjm6x%ws z(d@ve{xwhBa!=Ik9d{v*XJF?4o#j%?i77vmYqEWchr^V z6C-e&L37xpzNrEtN|AB^s0hn7Gj-~PZpbt8&~3+snYw54OIdd#Hh9A2G}J`hg}OK5 z{3ch^jRqIK53L_6>0skhniV|NU1gq6_VO=vxjuHVcAPxo04yGv!hsgAqP58^oUS>h zWZax>yiXsi@KNgcwvmO?+R@RpiQURwt>gcRAFyt|6`U0PT%`YdafR& zJG5=N*|zE!tnEP_n-6+byG#Cm8^edND_MAz-ky|?vZd;}%xps^eEeiuC|QIedyCSL z`O_ZZX|%rH)3;-9r<4>X+#&Bb#>CtK?V@jr?hmYn<)B0v0XX*#Um-Icu+{D_FUU)g zLe?fWZl=|i1w)a=PemJ{5W7dY)Ddd1gedT7P`#SD4YH1s;pJD5Ldf-=P(Z(Ri3LAQ z6yP3jyUEh5L9cB2I{Fxe!gRf#Srd`Jo~#yJpla6`*r- z^(Fk3Tl!Xb?ap4wBqP&zy7WWHEEq(-CRR4SYf7@MqRfu-h>%lVYD?9?zhpE6Cg1zy zESaysJm@9)2(%DW^Ee8f%HJEc(VO0Ps?w(**s}-G{{d1cV9tqz@^i;B!MHuK7H)p?dp8Sey)I%AanonO zX{}B$4$2q#M&fnh$NsJI^W0OM-qDm-kJbQJs5IelE{xaUF zs)OU34zyaUj;_4`yKZmVJSE6Los}jL*B>y)*fY_V(@W6o1?t0R-;;DZ?o`eym)2%h zllB6^?mY%MN;#z~(`W3b%4w`ye(BOCPl@l4k95VEVh}Ci%EI2$V2NNxTo!^7qBhio&%P8+6Am+%3 z{t6y@DDe8%UQNMcO_4|}mo?r2Gu-nh<~nf=G=dZ3oLuq+)=w^005C9zbd98;c8Jkv zV{xSYn0T@xkC2n1D^8o~D$b73iEJV0rY_|6-9)6-GiW1!b`32{)wo+oljq3zo0jWd zC@@ejS8OW0!XKZfWYio>goCmYN+(}ZUxkpFOp46%lbWnEAF{UrdRdE868)m)DKIZ3 zvc2}R*lnoZu9y;_Qtv){hHa$WnAu?SRLW#U-$8wy$Pg%4yX%ooq;(o` za!wtL$*t3a%nzC1GsBm(cVZx4={#$x-Y^f){ZIq*ps14z@$ z6prwpk-NmrykWqB?aCd@COO30vkXVc!n`78m4gp{9+x$Pfi;<1H|Ilxo+p5;Y<6YC;6!44Sg@#aA{GTO%Ul$3 zM#I@RgyKVkD+MN~6Z=Obu5|7zIxNh$jzU-Hs7O29*7FJ9#!U{bFdvO)Lx3*e3v;C` zwM#%Fe5aHf0cE9MmPswrv$03-=GJ`)D!Iu_kF)NKIC`L}sG%`z!_b1%Gh@YzB1wie z<3lx5Sg9AT*aU!CIaKfw+~}o-=w#LZ?roY@>gV=JE6Db3u6$Vns9(ue?C_~do7!?t z(;D!zGw{^1m_=hcMh|fuG`6jPF*-IcQSHrBC}2J7ZlARxSV}MYX3RL3XpF`PAsmQW zgsCLWaIPB>m*V9GxIbdSiEINtNnJ6$R=78))pd7)k>_*Bkh%fOUE$J0`7CfupE4kO zS@f_g*6Bc0QAnjB2M3zyc(lNRT@VO-fH2Uf1rkuTvPC)+kJWj>Q~!pO3Dy0Ee1LU#S4 zCiRyzF*OTB{n>Mld9mh5RBWcD{hbG0Q4rvT_qQ96Bpm!7zgbOz)Xg} z0TMAsWN8W`fuMpMN)WOzDv(o1z&bbD7!CQwjR?Z)p0NLNromQc*CT35&b_FcSebKOm~S8V*wT4c<8#?o+bjRpEdpr;O1E-TP;=^Fb4ap|Rjux2dUH;9S-3tlJO zt>lZ2)57>gRcj2j#cihqfJEp$7+}9NUi19wSZWuE(mVYEq+mkIqL5uaCjfSFLy{9X zLTY}{EMQ`A+B=iQGy-sc=F-_{$^aAsPzi5IB-r1K$XYcEonq=;q`%S@7 zJ+XisfC>YkDZ0g9oj|aldl=!Nzjir7bXP zB$b~@efe`c)N3=6dTc^G3KqeM3xrj)QoA1Q(y+$VoNqUCy?C`2(cV*vg&H(x{b>Q5w5;vrm-kCV^saLsase%`ZyCA0L8XBcb5uqUx5CB1t+9(e<4tsG8S)Y|pg3)uw9@l7r&An34$S5W|iGrdFP^1)LWDSvSAI9@XdL+;dXJyE4 zRfzLPtjlARMWa%t9X5d+nG~c#s~ZwG`VEp^ysv#aU&WCz5y+;BiQv}$?sVjV*-z?i zzHb1An;60bk>rNA%?CxoMB*rW{p^TSqEgzJ&oHro#b-FkTs;|(+ST{CAgf4j%5>wu@=XjNdmgpIMUo*!DCT;o_WRAca<{^b2vTXAko_fPuB`Ry4_Hy3r8J-53VKA^n@N_(W*&mcZCPWf^s{rHz9P7Q_D%x|ug zi(@Y%=DxEXSF-c!0Ty=T3{ zH{BzV|1<7JY>*|pyERtY@`D92Yvd9<^1tnl63UYmCm z4sdLarP*7e!Fdz(coD;6B+|NDjh;>DjY7^=Eya`l9+XnP-jw(*ddYC)TQULj>N}TI z3OMP@f_JE2Gh&;4X8LmV92}+Ro$YC35Dz~Mj0wTilS#YICb0YR zfz%mOajOMDT6UAbJ+(_!<6>Ts70G#ea=C$w#`E{Zkzm@)CYuovsv>|zC|sN&CNU70 zd9)7!O0kaJ?DAQbIQ_8PA*uQna`dOSXqU8a^K7Cq^6G>;>A4FY?wM zV7!mZTB~PO1D3k_L8k&NO96qinD&HJ#l&nFF-l#=zL7nBT&%kUE^WdF3y2 zuI6HYX;Dasm`W*%`F-q(O{~4@EhLdULEbgxYX7WP5})4Fo(TwfGlN8C3#1UcB3^|Q z)YHT%Aj@iIR&~}oe=4t<+|^(f=JEb_-mr;~z%3X{cC9Ukmt|>0jr?HB8%#IoW;S?J zfAqBuISvv!d*kvH@gKK7_8LGT5E|r}sW}~%zT&%=R_#mUS(UlyCNRKAx9tQ>?aGQK zxjh??`1ok`R%t#1bsW?ToG|OPuvjXm+^l9t8_o2?CzY5g5GWS|v`aEoMu_6QK;IX3 zkX2}V0ruDhdM_e*F6U3HS6f9Est?~GcNAN$;7{-@4CEH{4+S>@@KsekSIlU(a+K|5 zk=@qfTDjs9*EN;mH!Cp!K_mUi(~3u}4M}c9Dr;#(w&@Oel}%0YcLQ$y#~WUN-0NOg zvUc{5nZ+4#pm!6(ox5A9Yao`KCU6Pj9*^bpXYCd4AfF~InQZX=B>(?2c;sTm>zaXm zL5Vz9!Ht|Ulpe@YmZ|Y#Jwm!_8bC00Fbb@McCa{*w^m1!fmO5|5x^EL0mdiO2c0VP zdvPiox67t=#ejw);j0CB!6^)$CJn0OuL<+hnuy%(H6Wl$zf>ux733-Rv^hX`S}&tP zTHso8)MY;ko_r-w$rytN{58a1;F{DuiERSx$9~&xl6g%B*PMt^N0L}-1dr;(7TQHQXi+8qd)2zCIUcRes|^$Yp=$WTp&=@&46odbZ~Ibk8rrQkXW z$;Tl4Gxkj$Fy_ zt5}c-fibDI{LslhnX?-k>jAGa(Lr6rCASp&(s|MPK}XWDhITYBaSjV#k}EdBP6TZ@ zH*+XE>(yqm?BnroRDxjmEZ^NXrLGEan&gubt+HR9DV5lyeMN~~fwZaeskMr5gTQ8w z^1+a;^2BE0lnutiH0x#(DmjD1;or(NwF<&MO{MdMb77y~km|*4xz}2p`@j$NCsz)O zxi6i6cKs08V>j@hEsAkA_b}1~O)+^n7;j3Hp}a9ki}CT6w>t7a!gf*8z>)0;bz2|b zcWe>4=4M;gBbR6JuEji{)gC9sIJUK;CXPGB%L9EmjSm5%XxC(O%)GT`wlF?u3?dIw zii(w<=xXH*67Z-L4|+&N_se^84m*gACqv5ZG+&r9UE2tfhyqxce~ReO<(8P6@~YY) zx5B{+W93#E%!T`*pgH*$`1Y!4rsmRs4^B!w%BhtB!X<=TUX4k24tc@J)PqyQhUGKbcoUHlB7mUZX8!4gW`G z$D-z4p$9jWyv_}BM)2l8kfX>-eISUfeV^1}v0&`AusAW7Lm$IBul4IODV_PUnZeJDZ($YJO(52jHSZrL%|Cy=B2ffVefs`%)e;u$U zZ`K+_^bO3Hp;IZd$3ujD!~Yw6oNkF%2dSq8u(q9^0V$OS21Vl3gI4r3w3$^^O4WMo z=PKbzK!DK^4uv!LCK3k{sKwh&?l7Youof@20i|x?8bntY_AM!GftR8y{LcUI&d3uMrw z@FNV(4<;KW)n}~BOgyvB+WX?x`IBhW_-LW)Amm9)_Th@r8CBK0LvO1xk`=UMd%}I> zC-$2PmyEWg`u<#(JbT%1?3`LpDw|#Et^Fq#T_|p37!nk(iNq%KUoGnwqCYANQhO3v z^_W4_9h$|}>*3kG)PE2=T@W;f@iq%)S!mzd#;l&;$g(LH-^^U^Xi#BY7OwplX!j~| z`Q({rL$evP{3Q{{oB6dd2wRb^1aghS21oJfTDJF&pmF#V*)Y+jPbfE*a1cZsho0KY_E5L5qW9QcZaRt{W-Y^BY(tWCUueukx%ZQuQ6=QLa z0>LTj`){xLinE%Z=(iUaBfO>7gV}D7V~+WaJyC!i0S2~#qhpOQvr-%p$;nj{tyY8i zi_BV8vj}zyr2XDHbg0<;U`wxS0*8ZAJP#7M5;1`0ZKZH`95*dQc;H-)GfB<^+A#<$ zr!~|u-%A^$=)+`tCM{@l!wspWs-k&=-Ap!zb$X$eA^!JWJvZZJ zFSsalaA2>?FSGoQ6>mEqyz|p89&-Z##fA&7-&G+G4fhGSqI$VXBzw*9ksQxSCRI<5 z-5I%OXjd0T)en_BL1z>mgATJQBfgXf(sRwZXCA%3 z{}{W>z6^nYFLo)Zvpq>rn=_bC2{5Id12 z;ypf{vsUTFTqHk~uH<3<-g=XPllB?n%PgVTF2ky|lX*V#V*gM48;lI-_h&@YP#?*L zqraeL`j>kbl^W6UH;khFSDOBx@YkD#njk@upd2h0LsV>&Veo+r|0oFq&^+H`oT;jw zg&kYTK;k@>wm5$zo#j&^={pDdu@>nNmOXZ@6zaq1T;C`n;n&cWVfb<58Dd+lIY%kz)xQtbB;hX>vBGW^1jbj!QRztCbEbIh4;9Izc zH|XaIZQQy%T>F;H>r#jDx}%`LEh05F+3J794d(sOB&Z-bGQU}&pTcsxkHVU>Um8O{ zZbqTBXyU^7Axz^=S_rOOkfx_ro=}9yo6AE{@mh>}GSk#}qTGmPiansD`ffM(f*+)+ zysQfB5a|RtH+@jOk0JQE#cA;TavYk!ZI5`)UK$yT)U=laUl3>&efM$l&t84`RJSx4 z3Y}S<`I@q*cpW_F-J-U)Wn;@FkiVH|vRAwG8z7#6-RcPY`2GDFI}&jM#LQMlXkJMj z2&zhw_Vi79Hl$^W(9?+zM|qMU-ZQQDXf`8|KFwp53_gms4r5Z_^RpY2jB(+&4PSxY zExQdRE!4ymd6lM)VA(5bV%@(nVE@;^2mz4u zUSx36QG1hR&Zy4Zw%8|i4bD@~t_05m^5X;HZRuAPe+ib}-bdm-f?xdD-(%SzjM^0? zO@i{O|Ju)U&PHkki8qNZCY$53W4DYoQ1VShy;Tl@w5`$YJe?+knK#tvV>;LrwuXcR zzs4YJ)`SL;(15e%UZ@UB?1?n~EjssQY42HQ^v-L+I|zmKh?B;g%W;=+0u&h#ZIX&Z zU5FUqFJ{HgVdtT}V9#4dH|HzucpCS^;gIWj^Bskd)f`jsD#i|(D!gxF`q?<@QjrQW zra5CSv@ilivg*F#+y0_f*C}^SLk>4;Nw1)=J(?m_`oeEK@i|8dbj6tG;!f|B;00m< zQf-T(Q3q87i*yMUy;kOj9!zUugpr0dW%{bs0!yGm08o=w;;YP-uih9nP{2P`wQ7#N zP=0*$pGZY^ga7878Bx$RL35?v>tm=pJMsFq#`BZi*G88yRew|WPrt8Y5k0j@vu@4&umDJ zs!t7x4K1C@T&#Nj(ACR$Pd!zpOzP(LC)ihAGF-D7bXWEHrCcJHVZ6s7U(HK-_4I)U z6(@ih(aJ5HIc?Zx7|3o=vx<;e-YJ;fn<>_xiQs?}Pw!asmaRy-#{_jT67X^>?_Fn# zMqT=nHltV#!pRt zcjRJnnpK9l=h1u&6^p4boO^>8)2BlIS;pD1w4p+mllCH#KVYB5A-V!Bp|to~ALNiQ zrf8WdCZrInbQUe5->-ZI*2ZBz&o@~>euH4Ao0F1y#sU^_7B;!V$O_SbqUnuO-c1!F z{5QClYmmr*G9l)lI}!8TR1i=z-#M<@%*7q4LyOa9QIH=!Jd>)02N85j8rX4Ob zQtx=n;Tx*E14hRPpSOQ2jlsBfY!kxlVxuni78GTy?M51qwn7RTSULQgh7ZFcC2+@&@=E^=Ag23nZeW^mUCO5_lQvcPG(Zn; zDNf87X=!<}f{;A|>f2qs;{eJt8>3-#&cH{_$3$+Gu-(4Ctrt!C{m=+_-rTMW;J8EFXl_kbRU~S{ImgP-WGYHkTXL97L+hWlR#q~hQ>&miLJuR){cft%iV_E zR;!@8(wEj;!Xa=K&`{n}^-5e3%5A}QMtQUf7?9|-E4lk<_HCZmRC3PW)26qIzDPcZ zdxESieGH?AeUY2N5GVTO5>Gtr3}aF%*+9{IJX?wIkC&40 zKBYSXkAy_1E$_rn=yGS0f`oC9I5p**7)x2|b_xKfRm0zqLZI?US=wM{dzs1f?k#BB4+jIV2G67K{}-GcH~MzL zILP~yt3Fjw1rMiuDUB_j&n?FI`dYggHGBb&c2;(24yUi@ro7mT=o+?h_ep z$Bjnr0)UcZQhu!@(!YSfouZH9zyd?@jcc}KhD2g%@Xn499}2592-@vc7=zPYgsIfKNC=E#tD+H@w^XDqeq|M z^#_4fS)c^A8b7-AM;VDY9Dp*E{C{LxaCY=G5@f-& zfQ2&@P=f8alk)uFBx#YHDAg-VY zGTffs;8k0C@_0RKK4V0um<(`|*Jur@|m)LgIG?!m72OA8?|*xAX8@A{xun@DZuzqCv!;RfDQ&%DRNo09_; znsHY9A|f&>czdB^rmWuLoL0#$FcK=D3Z(ja;NucYcSl2Zq5PQ13nk67*DRxaC4>3%Bmq22;VP&zsa)`m!yd0$97jE;rT-epqGdMztsGS$~&Hk(^wogd_pVVy~zh`0rzjJITvA zylL$)8fftO3blNAkZZaW?#5>I5{|Ap6s^r9aW#1j8xnj@-R#24$`@?}__KFQ6

_ zK~ZvXlCx2HI9L1BO8yK4?)Whb?V)-z%-NhRJFf_FNmk8|r4z1(L&mwY@}URsSJ9xH zX7}E^MeShI4q6w;5@62T3__R&*rm_6YDEkh&ns$>PW5`vEVl8Kt z_U|t@zv||4?gV*#_mQZiShwR49VdB>>xic+tpaoXOgO+Ba6;z})X^~nDQE*A=P$!c zhRXUy%UIxZe`(?C7d<1GK};%U`I%WcL=e; zO*t#c(}O(XSIe)@^IRuQ8`8vmo_`zu|MG-TcU+`kov+Tz^GfqP5289gf1onV;Sv5I zu1!`|;>Ch2oq@F-YI`?6v`vmE*kHK4=gsaVV?yClK3O2s5TB^VR=YvkQuFg^c%874 zrh*JKnK4}}ENDLF@@w;N3NM{%UK7>4qi)>9O99NJ!JTlE13yhpq;tZx3N@1cz6xv3 zRh)z-HvaJuj%Bc)C1C@#KFDKUJGa16$0h=PzR5H@8qKk4Tk+DA)pFI6%qvean}b2@ z>JnvMypDex*D&8}8~IvykLS`DGN{+O}jQ3HzhDaZTI%-oD&Ct{@f|-NX$s=lz_=PK zsVN9BthoN<<6J32zJT3W)p(_$mEM}xe1wd-OoCB!s_b);) z!oqr*Ixfa&*({orlPtVfty)=jUU^ls=saA`o*ao`uO6=X9UkE7HTu&z7ASqRnfIkH zVB^Tmm~*sKKYW^eYgdf3(*LO4%=roI0l=G0qZJBIx?$A@7CGa&1#0oK;UR&aFnw=tBrfosTmNUI&FK6b#@bFJjsHN)lhH@&eO-?tAWX(!3N zxi(BqN{?u=W3PZA&1Ew-Ek;WO|Fx~eytEi(*}k?DT(o#U4ewe`?MDS*d)ajY<8w>8 z%fI@uA1xbEA;0gTN6WV#*i|0jjP)2Q=hwXTW#unF@#%6M7SpfXx~jbC_BW#@Kf+G- zMA^M(H@G~@rWZTpXdS4jV%q0%GoH;FX)BZGA>{h5DJtg%Af5x=hC`1YU0!vuIY0# zPXPgc8tw~R-lawI#`QSw0`MYkI1YhOW&|OZ1_pheJb9|@*|RstPFxG*+&t;!x$Wg` z9cwxKW^vDY${l)dC$JpSU)MDXJo|Z%RswXw4NtF?bb+s(5Njpm9C}rcLP;O3 zn}+qg>P}1k3|#UP8!s*QqAu)39rPzXs*6rbZ%(IHCCRfeQ1Y^M>yEN){e~>IYsW!C zWEv=p|B{$zy~4?MA`ow%U36ZW)yRz>uR19W4!T1)?__O*I^{WW&=cyU3NMPPjwfRdmnnF+`+k}33lr(fD$+JQljeh z5lR@nw^oakXV|@u6j6Z#W%0^9C)UM%i^~$ut0};UnhpeH0K%iR>@-rh0e0jy{wLha zkaiD3d`6BOFK3P(E=La>K(k;MM;6cwaG}lMN;64xsDGwrXB80@42f*ND-&f~N?4=8 zVH!G#OhJublSG0~JGTQp;RLC!Q(@IfNq@^AL*^h)HfD>zIB>zQlu!a`T~x_Z$$ zc}fT+j<%1?gXI#>f!V${&n_k#ahLp^;BfZe2uA!cT^>AXs7l;P(lBKDS&r=Zhgdoe ztJBC#ySNs0@`9q+NbeXhxbyv(@V_0Z`?+skfpFPhd ztmez8e}3=__|-`BVfikM3g>x1zNd%jDvsN#)Uw(?=K4rYZrR%MwfW31!<=9H)@GX) z(=!AV7>Q8RwkU7oUi3`hC3&<(pnQ(aILDjL_-*tis0MtGU)rjIFmjuq&A@MgHFyyA z3oLMJoVmDja9Vin(-2{|1?06(0QgkD+OzeqZZ4&1Z4pz~-!@MBtZ6N4jdyXm+E_k` zA>a@>;tP)NnwP(|EUgb7^nZUZcGc?z0&L#ks>W~2H3xSNj=9x*d6C8jKRo9=6M3%A zjO$Kd8_6=Xi18FAOG}Jb8w@%Koz|juyr5Z0OiI^<;>h}j zm4rTXV{+8v&%&g;IGtu;HjY5OPdw*;Q(iKYhT3MKo6^oY0p?o&=l&dcaE_E2u63jU@D-lH*B%e+3Fa|25=i6S*kU*v zBKS|RyEW_4M6P+;wsSMb0sG4cd`wq2MxnaLj=lY<$+xX%cGC&EgLs% zD6f6(>kG%fb2+Iag4nXRp@3VqZY-CvIRnC}Gx-wWtR!DDPFuGw_*Ym$VvE*sA^_)n zo^k`DAK}om92NbgpS-o)^1uCZG*sOiAG)4ft=NTUUViGyr^@WY z-tv{lpDcg>`7f5s{_CINZ2CZX*Sp`wdH*HlYhUgzk39NNIk4|wjN-``A9(H{{On?K zhPR^ZPwmjxuk>duXJod!nQp z(DqdqW5a$Bn!tFQcIy{-@_ZV3K908SQHxc%kKZhi1St zxiO~(&B;@v?9wy-S&yh;x)Qqq@>il*=L_&aX*1k&S%QAXcV{!XQU$-D3>m| z0JloQ*N%j=Z_eRMn8$d9m`r=NPFeBc8gV11+@gmIa2%$4G$@Fvz@TxY97KGeYOhd{cE>wsX{QI>PX z#4-lK1qKJbh(ShYBEFp+Cl6Mb8(E?ei4z^SgYnm+EqPF&mVaR(%6|4 z+-|pgO?n62vQ=wX7*CyY8Kj{sgUT!fU)84NNK+TGuwF;q%ql8! zyjX9o+&V$Kym#TO#Bgw6DOoSg)f!IbO5Y@6=g%>*Bf+0#K+MpAALhJ}cQ#&tXm954 z`khyn2OoNs)^Ed_>q@YQAcTS0$DPJ zs1bJ^ob%zgYCe{wst37HWXB)eDAhBDJM|JI8K6w2E}SWg1VVrROlz3&g(c&ozs)PL zme5J`Wnes4HGwqV_^KDRyDO&ayc0LOvp@t;;+ntCa!FXc16QJD8nr8?X)o;=$k4TA z^T>ii63dcFhxF!ay(x0WO3IOQN0yr*OqnH+`gzRZiQ*@*7X*a{#Hn%%bmg_qO6x94ZWuq0N~! z>g8^$7HaM9#;@%FqX8~#v+T0qU+WBf24ZDGYrXA5!j##oZO600mt|Do)H33JTOOI) znr3c^Vbdzv71wEJktQR`Q(=u-A2Q137b~?q`Dkbc<+256H*saT{dNjzofD|#PCJ>I zj(S-Z{cZP@NdXE(z&>w3ODTw71tk^7CatC8mqvHTi3l}*>P}j|g;#M>^Ao=rN91Y$ z7D(zEur-dbgtkb+BTp0Nk|PQe9nLVTg72hCIaS{ zJ%qRxtVtp;&jvP}WC*m0D6^QSezujk6*ErY{v$%*3Iue-Pn>j|aGE+-U-RM5$hZo_ z7eiaW`7Ld%)){X3Dx?;k2UH8SF2tSh{^oD~rotnR^IN4Gj)x{L zfMgEEW82o1j-c6wV7DIzRer?rs$hB)b=>Vcc9eI%>zx_<(ih{`nIpxmIATF4wee{3 zBypI~%d$=D%7Qfu%M5d_s|~9n4$Rl$xae-jtK)nM9H?%Zehr<_xSeY03tiz--l(`r zi%sVkhh|L!D0~8SlD1|(U{`FA^wM$LuA9ZXJ89DF3;fLt01p_Bt@9QH#@ri#^n+06 zPj%#Rc0q?!dp12hjyudAjkF%tK^(>*c$1!mCj*|oiNjA~=+}7UVfq?ShgnjqEGx-{ z-t(uB#<69c`Oh2kkU*G^?cL5X;=#V2`6Bc{!0rONa3_&;mO4rb)sS3B+mf)HXXjLv zW?9G{`+HNqfCuNZZaRfV&t}I_{?QvO#>Y7eExOp9?}m5P5uN_xqQicSfi;dwy0bh+ z8@Sk4HJu)lwsf)PrhxoO>I1H)sE618y7;G*!IwOTHVmFVa;*I7PyI;w;dk7IfxpA$ z{=4od#}4j6*szSYz%ij} zeVRoQ1$N=;?Fb8~=PEQNf8_Qzavh$>L#YpA&=#bcI4TEH(p34XxC#=$iLt~>XoM-i zqvP#7!mO2R*OXh{_{ze57D5$pM6kFT0|!GZ2Fi^$T~VIhdxQnwv2yg#Xt{aort(|A z^9StE4wj$%i60@(aCy@Yy%o*S4dwFtx5q}o9bf-ed2aV3DH+DNcn*{|yzZ9r-XDE? zdC&XaTW-1eM)>r?PW$fib>cqo(07T0_V2P4<^TAjKPz{9`%ccHqjfsQu0{ClBJnQ$daA!H*-@ zc;vgg;H3}J*0hllH0mucAWaq__HSY2A2iS|r-l$H%$lGs?CGN-P2B35hOp0$(Z@Dy z*jV0j`w!8F>C@nR3AO_c9ynUQ_=T^QM;>{cyX3j+9^qhGkhG4U%(=j8Kmilj&0hpg z39I1|@=?xcb2J4oz2%X1O_Jvb$Bs23xMAal+(rL64C4(Ad1WKl{;@DWb@DXvxCU@c zBahH4a4WB8{^11!*Pja4hevu{#Cv?`0JjaSL*vBti?~&o5E$U{JjX9ivJNq&^e|cv z&}+X3*m!g73ria*_DkFA6q*`WUvo{l?mCVZ;j;Fi4ITScuo~}w^gmGe7tc8vR6{&= z77Q#vn7UE#;yTGPxPEgP-mtb^n;fU7_`0n)}8@6qMcyiw+ z!Vl4Co*DyG#Yt&-7EeL5q4b;PUFo611BDR2yU=#fpF;>?zQS-J>Y~T`TBj_4fTE!j z8KuQoot4Psnjy+>yh#4YSG-7o&DA3bUYm0cV@28~SiXE^Ie2IvyYEPyIf5_^Yz+>& zAhdV`T&w7@4TTfdTY*oy8|8Ax-hSYMRy=i4c389EewO?sOzxia0o!&}DA2+b)`B)-_|#~{f(az&0F7md-%v1}6~HS|{7c zwz7X&cFQw?biKt>%h=a6B%*n=ELtK4ozX|?m7oRPjQ&+~A zw~^#bAL&{KTxQg3b5tYrnxrbZS8!A9pDbiiXP>eju>wqfwX9T%%E$znCU;lU*IENV zwy*usaUL23&J`Sm_L7%vY5Bx=Y?JV`U1dZ(7o9pbif5xJH%RJ~5 zsY5FSv9Ez_`q@O%k|8xu(*pEIcvV8^Q&rF@Y{JF2@zREs&IbUoZ8zzFbRu|Y zU|W_7qmE0ys9&Y6-q4~Ns0^v`EQy+B?g|fcmRtN@z-qb1mIP{>D-cXsD4YFc0w!;q zxgmmI7CgRjtfvd=<-x?Erm7&&&L970`o8jJ0VnOoHcKL*I zyV%w^G5QK=XEpyWGz%O8vq>YWXSvltzRWRORjv`>I$kJ^JB9W~7v>60v|}_gqk&=b zVeSM@i*FZpuHJgIU`~45phM4rl?4m&XS-P73!gLl`{7rv*uJ{_Kis_sm}W_JrWxrf z%e%~SndMDaS66#WW7K#j5QvdM$RLNbnn7lz*^w9tt+b<=k(k-tSy?nlXao{M2oORb zV4!IP-LyAFyQ=Q;zA7`TD$7@9nR(wY?#;?(#4OM5GYD}r|Np-?ZkQ7%PMkRB#EFQN zY_7lKv|)H_&`XtU(_Z4v z{%k!nCh$ZhQ@7fn!e%?W+xz*laiFjK@drOy?tSo)vU2GHmY%ZXJO%{E<4)+vwf{$t zonr0vHsmRnd~y^rZFAEN8_UoChuE`EOU#?|iy+a3HS>Ez}+sbhi zGnepMu1j36Sbr6Y+EwHo+gW++;b+SGKlst|&|^;^rxZ3##FZO*8dx}+V*n48zkA?m z+Tlbg?0>*a83O_z{;f|rypx-`W#$ztGJY;#a!bCvb>~od{}e3V_T|6gf_#!p-r^Jq&cdrR zcAAc|EL$T>!i3jPlqG|UpjC7>VaPjUPrh2L ze|7leIN!YYA+2vDc;JxB=G1kJBMkWTvWw^9E7md~%Al)oW+N&5idK_+UFbE^M8t_3 z0w-OQg9FQ?0BaJ08pSjhO3urKI}Z7`|O=`1~zJdsi-_F5Xrpl zY)6g^(}^xcFm+Z`C0+qphVN!{^aN&dRT3DOn*l4BW`Zw0P)W>+GQ+dJQ2n2a9 z?or&96q5RBOZ#Vz>Y)A3atc76VG!=f>b-8^w(U5-Dzg`X-_C01v)!}aUS`{1-(Ts4 z*Qp;>%x}U8l+m>cl12)dg6*MOkV2?#lqzu=JrwQ~s-4ZyTOvmR!5lPPsPNj!H5jN| ziW`?uoMFA8inVFPjWY`SSW001jqjxbZCMJO?v`p?-+6SA`L-K^NDI0cwF*cN0-tRq za}?L&SHZw`On%UUN~#vnxgPh(W&SE2(%C5cIS7Jh|H|OJR4AX_x-}jeixv))H@x8u zxaK`ozI^Y!W!1`62P^s5bppP?;kFuu9_H}pCKGq*j1%8zvjT^c(9w%>UOC{$7MjCf4_P9uA zBIYfa&yh7lF#yQ4#bH&*p=*Q&&xCbt)VA%5dhlAEvK@sDdnAd6uqtRZx*O?JMRLi#;)HLpRZq2JG7k zlICw*1wjS9tUXgeqD<+@<8q8^|Fr+vH%u?SYd^97R%Oy~`?d6P0^wCt$av zPn8q%w|)X_xo+s=)h;=4K$CB%(1cov=U-rlX2pdAGF`Lj^A%U(r8O9M?|WggJj++{ zmA0j2^YSvDZR=&ZF#?j1A`@4-HLmL>ptk?mbf)?P1?`46Pc7R5B5IF4}41TTloA~Mx|%^IpM-=S;?P#t)n=PF$yDFXv+ME zQ-#YUqa4%uqcG(fM-&f>C#_{$H{mu+dUu@4Gx$(ZGC%9%(M94~n$!zSMXHBBb#OoD zJ)AlK@+zT zz(th1s*gi|hneXcJ9!js1H~SZT08=-Es^*@k#SG@k&YC)RRjUG8ubC(Wo&6*6Ixf` z7B9h#%|peevJsg4&E3c^0kyuy<)<#<_EM)Y4A5O}E|=M3MOwl@rnsgF zv!4ADbY(Mi;-+s};TCTeY+nRHl?Os(_8+(Ba-uZ`((n#4qK8?}Kpna!LoOA*J-hdo zr?>6IwY`sH^gL1z4@O|H-*iIzJ){Gzw4vhz^qclkh12*9|8}am$G!~hQ=UdKv~hCB zn8Ej#@A*=B_|Zpj_wOl(_8chBZrM`a_x{81uoEopJcR-^wcP*3hs(SE;QuZ!edX&? zKNYE^OQ31^Rvim)v1h}%uC)v4i(Tc=y2Z$=xQPQ#OdWvevbhLK6BH#s2c@7r&(3uzo`s=$lgJuUk>B;zMMPOs={? zyC(!qSPl-IEssC_bou@FypR2%Mrmq}AY>nf(`+c0*>vLcA*T#3p39nh6hFquDU63M zJCJYr+}m>|cE7gTO~!kFwN-V++%F$wHc*f07x+ zc|kp6=Z@`V<*HT4!{0%g+OD^~gy*k7FAxzdIorCN4AjtQxSyj4m-M$EI zNC;Y#++ZpUmxlbGb=kO+uRMKK*yQ(L>)wv3LL}jR0qSDuJqsNgEibuywl z`#X%{GK>;^2xVsI+3lr^jp$~8i|H_6FjMyJIsgu)pjggk_I`|AL_L-c3*-Or(ltqe z-X?V@_zY52$xr2E@yDEUbm+?pw=I_!4H+NBZ7AD;y zWpa9KxEw(otCWx8)p3wrUOitoN)6>d{`iySTGq`~w@^GBaJM>vMb!MQv-oo6@tJ3y z&9mVuomXwxKsx{nTvTQEU;K-=mw)xIeksDail@w07=+&e!16Tgcn+^ejokC)d&*5W z-IR9LD6x0%UWA+}W&M@w<9gM{J`Tq)=E!gd1_oof&FndOnZL9AT2yC1`(vILOI_Oc zwvmPqnY3b(bfRTEGmH#?!shJUY!rQI#aWS7sS;P#?+4!c!)a?b1Tv58`V8XJ{?t0k z8SN~cs(g4IK-hNUmRGKLP1@No)7ehK=0KoR>PF^WLpjm zZ9_2Yrr)pu5<-V~JA3vR;X|Qkl|2oGb7v#4(BAhy_)uAiTjS{H5ooJFu;`*^IXkxR zDvOsapuOCHNki5-)|+h?{G8}9Z(d)@oy#n0@BrW0y=yNU&D@w7(KFOz7PDhkbPlwu zTibE!EghabF$%8cl|97&THI$D!jO0wJ%TdFcF;3ekGXQ~dJI7$9B+id2soB3>JMEU z9rie!%E`XgxI2ptgs!>a7HIEidFp9rYwNXSA-gAIuo-33FV|uo$0c#*>{*;B!UjY1 zm0py9%CmKs#UOj^0J!WUE?zhnh9k5{NB#Yaa1}k2zA@Poni=Zmp3R9>X z7>h>X@dM#k@+1vSrj>>~f>pjCt!3sDh3OOuf&I}Lzn1s=tK#dWLT;KUDZr{yZy(Bs z{u4K7#z}>&8O;2u)Su&gX?df{wO0pAVwYXGsotlO*9zLNaZ}ZI=1&iF0ReQMMcIK!fdd#0B^j={y=sABI&q#WL?5j@F;7Zd#T@a;#5OByLUrJ zW3*K_Go3TX*h5ES2!E)T$V12;xZ59P%J($m+4Pjn3@CjAwIfwDW?G-RI4iki(Sq!O zvMzlGj<8DM&RUC z|H36@<;qp;O|%Ea6h(J&Us6 zc?Jk<>zNk{YG4ddD7XUdcC z*T4PLr_19zc7X@>cA7ei;(_Aw(ARzYYpBalvDel?_9|eXtb++1`$+7fLnsO=Q);_D}og z8>-k#%rZ|~mLaN~Wk8#?d|8>bY_Q;I1Y?2GK?GVl>n`cWmKr7~;hPKF4QLAETB=mk z{8i|m$ISg+j=Y(NP$tbDW*tgZ6uS|q7G+oYjl8&c>+Kn&WrPYd3N_^gB(S&f-XgS$ zs%Y9t(%HaA2)W?~tumv+;k_Nhgfdy(=m8b}Rz@U;B_obvcO`WO|tbs8>QvRC!b1tsUV6!-S!pO z9ax5kQTzz^lmeM?3@G4P8WR4%1HRlhL8bZ#LWqo1fl~!gCTY7)Wk+3)Pg2QI(NtiZ zf#ISLLyxe^bTtn6t1zr$&=38%iIY89VMAQ&Ibl2vEit5!x9z57c0N}8gA5|Jg%@@g@dzE_W%FFWIVOC>=I3(-P(FJCK#p^xye7U^iSAMmuTX#j`ORM5VFA3X3 zx-`xH{VKAv!l&e2=I>fUg)HgGx(Ji)r`L*W=rruy{`?mNHyWVapiJ7eokyS>6+`PS z4zf-edQef6U&W%25PN`f%~Q`4<7z-s=~R$ZsPgjYB0IbFHcw$Tu5g+*v#30)oJrq1 zcI=4P&59K(V<2+I+&o$wIRoXao47E(h8=OGF;JSbz8a1c#O*V}q=%1q8Xg`Ao~?rl ztMsd)zi83Iz@%}b&h*#5B#nC6=F*~lZ_nO6xN2(e zbuovQStuq`SjRqXHcMvMgv)(!I-!}$tMKxXr{khL0H4wTso_nx)qVuf#f;A{d(~^o zTYu<>%F0!%$`Eb(z=IFs8vLP*xf)}oS^0tEQmfc2z4#9?`2XKszVd{eZkpx-yRdUe zIWz;lIMzvg)TMvUbfVyp!8l5hd{OmD#lyTWB7BasRLAjcjQ*oyANs>+py9v?4`m}G z2LzOY1FWZ&-rT&+&D6T$!GMv4wus?F34?eQc)wNd6>1d@h{vy95o7SNv*WZs{XyoA z7?#=F9yGpZx7}A}_F>S6ciFy|t8c#TC0=+F_z24@u||Fh+6nU451I2OI92oIlRTm8 z4%%|XvPCGfivUAq4!%O3@|M(x=qeFo^rub?@7s2<7J3N7D!5mHS6iOKjP%i?8208& zD_0CGLbGD|2#VZvXk-R6ej1v3!BZCsrbpKurLA_b6yYLt)7w3hN#*f!>vgM`c)-OT z<<0)*4e-Q@7an>EnN2kx=h^|w|$`>~8EvwlCZsBa)(5dg@ zg?J5uZ;f;=DI-_vi`;@S;Uco{(NmPqQj!Z7pdSeT9L5T=4jpRrA^|+PuN=cT8pHW? z^2R$2R*6l3BbC_|{Sr$JrqlPAQt#WJ_q?(JW4ucnbX`|wTd`sxOJE9y`|Hb*L;E8G zh@AS$uwl4_|P|_WrBn3WkNi8X7&rAeKd2W9k~-g+Y$5-31ymg9Rt6K z>pVJ2c~=+93Uz~rCOdnO9mz|6?6HF#c-fq10_ck6v&xl&%ge*thst|@@wdut1M|ua z8`hM;C5teMuqidX=s3Lk2@KPBKDDD<&*piv>9_p@@MMgq8nVVwfaRr1ob_1)68eJp)~ zd+~Hy%weM8G)sy-y&wh!OQ{7V@5^8E zj1*SiTTROFQZ}3d4;KbyZfV!N)MFgC9bYua*biH}w7yOvnukVd?~fw?Y~S%r`OV*a zSGo0;=h2^#tKi3!5E(-r-=II`ek*+0E5GpV@YuCw0unM&jw1bU8m661eJS1z-#32D%upQ4YHA=5Dgmw;spnnDw;+VJPS&Ekm zTqp0kVJ-@$!lRJ5gbgf=Z`p%O2P34}$t+*NTw&6Bo45DonI!?-Yhlw(d(87zd3JsJ z?bqKD1BYjmD(HIrhnMf|&>93RTd4fDe%90a`|O}&d3I`r$-E_wcobg494y**zBg~{ ztx&3BEu+)LS*1bu9^1*m(gA!HmUY{YDH6h%+2fr`g@zH8PSe)Gz6#M1K7h#qTLom> zjvY|~9%W6I%Ch?c=*ww)JGbvBE7z>Ty=_nGx{O)A~v_wl~;VZanVkc=U2b_ zRp4eXv;nOS4${7LfcG5Ll`B`4haY(??LUPXoF|@qBAZbPn|(w2IErCIVP2!0N}e=v z8X8bBdJqM`O>0!J>so3QVH5`y9`n$ErtxDKWq$FJ#Ths>>Y1lY6#7}J5Z6chJw&ZS zy%=v8m*kwFZq`Hkn}_o2`ZX1B=~-n|9;0DHnqLI()Tp6RO{;eL9DK-qJ#;4yZDSnU zzI|uv(%E^ExC)G%urV}3`)X*>NTBl34NjT4q3>ucvprPgw2BLh0+e0`=U6)6MmV}# zc2S12qzZh-osNL1mw^JMMv>e@fA)nw=*jlq&n!qU@8>YHAAX6zJa4`*oyQQ0ODH($ zBroHNfBSfLvL%iA>Gj|Yw}M1fiuLx;Tc?|Kme+)mZL1y>92Lm9D6jUt`B}np2?2$6 z#CWEmM*4OpSYg>ZADMfE`eK};?t_C%~w_62!CAMW8xP%brmomW#rHMMQzvj7pA(-X$MQmnT|B?Tw>T^DtTHxI{HSs!W3 zxEko>nbLR03CdZv)TJk^@rKvR0~B%ute(%{?Q@h_urxdi9}dG+Bvw2Z!{VN?U#Y>sGk(=TVx zT&fU(4yhe1@QvXFLH-==AYJ-S#a?5=CT8O8ySD9y4I3O#Q10o6(A&rU=Hum;@MJo? z|1dj^uMVzSiy82` z2_XV%6kEqMawPsGV0P)+1^TN;(s|4mk+@KTxIs-xxh~U-62v4R&fRmzwdjS-Z{1i=Vcq`R!*Y)9PWv4*`?UE5 z_`ytQaWVb(nyX$CW7cW-K~7Ks3Df`>{dkETE*`~C9`ed~?d418hflk^b^vx4djMCG zsmA@Y<-6bX-Q~qEe=$lbSReyOcxkMw!0ibshBps zyKLJ#RKDj`FDh^Q$sa?uP(4MlrQ9Aq$}ECGHS-JlqlkUs3x8ie_VG`abEl4!fA@d< zO1$!v)#9#9rKBHc^y|2<{AM1#9IbYu{NW$HpPkrufLCWJkzass>B6q^#rOZ4vXFkI zS594W37;TO4aj0_3T>g0!d^k05}qvGb2zy8Qa z;PH41JpV=TPnS|EGtid6qtT2}23cSMd1{#42k)Od&R3?&$tYa z?RpZrWRDi==@LnKXWLiAk?kN{Dx>aG0RaT31cG?*CleK+#F0lBoG&c^@O+mTDGS~C z#klQqsjYw|K%bst9ie)xnq+P!N(_*1EOlW-~S zGR>qaJX<}lS_BW=c%R8U@D}*^a$N9*z_g-Ge3^&8C-M5( zvu96asCT~eSIcd;-NLxw(qLewNO^fT?%~pBXxdCBuF3Zkf&XM~z}h$N5_zrV%CjMt ztzB1UARvv?2vgWJ1$u*t)2K9-m`~>?jp@EAFW_~pl!Jdi!j|Wxs?>PdnH91|aW~Xj zuZ2ino!JbSoprj<4KuZq!F$}{)xplcT-Lw67YF9a7wjsbpowR~WsdwQ zR8tsqT&E}DM!A8xDg1faNyh2y5k|->9n>6wb# z6sB{o1q{jx(kfcUC3)7Ut0diW^DUgwx-so|H42PvXPa)g@+#V@9)l$4ZGX9efvze7 zb**GQ-?NnKI=qhEm%D^Iw88cZ8Yj*(iD{EPwb% z?<*q*_mBr`_ZF?pAU=AG-GCR&D#QDR6JCjh85k6lfqu`GE#-qB{X{vudt2!rTt__4 zhc0|(4RSUu%UEWLuR80wZ#Ur=d=Je5XFe#`@~4U40QNjLVt{{Fsl z{{s(aCf5FHzuditB^1fi0o1|M zcK73~`G-F8H|gVgyolSs{p6>zY{9;kHOtUTb=|JU0P%kO1T(M*9k!3lHl~u!zGk2F zcQ$P;p3TGkF4BXbL(4QzFYi^7HI7RA(vrWr)f>lr{>z{KS#U?>lqAu7VqZnlh^g0yA91lV_+%yN`&56yXpbD!TSV6@2SZ%dl_OeN{9h z2xF9U`aqOX`l*H(={W{Sc%3slb1~w{^A6#yq7teni1e&cMSRQOEhB~=>Z0&zx+MW^z1~V+~vLiW?b;C8+apv^Wj1Q|; ztu1eS{Ts@f)vFN>ox{F-v4olWvdrP6!X)i*@)$zfsVrU6-S`xHpd7+z>CBXE<@)5> zzGHZa?2Bj0#*J4a6Q3`4p}aYxdi}N6mCt?dbLE$R<(E+QuPGaEybj@?n&3)uV4U5Fn&5!-=pP<)6KHpqIrMoX1gC z&M2f&N9zz}MM7)tbuAVzZFqX3@7oXWYFw&pHhCsYuC#0 z@OZgX@OGDdDT~<$rRggN@mjh0#`5q355O~bmvzkOx}*CEmh;Ggb+2#7$H+R2Cv|xM z#=F_wWy3m7BHFQqeuhz!@!zxNmk%&AKAZiCW;6cGWt^sh-ON^_>rpOsC0`{JFb>3c zxy^V5uK!(lGj0Jk-YQ2?j(C}kr-W|uj+J}xc<~sug^Xt|v$8LqV42rm;GQ#kCW>m^ zkXYmLNB`<0WyAU_nT3b{k#-8k`(C^!r6tL17JO;_ivH5=3_1X6bhahrm3|=Zsi&#+F2pW3_)wn>xQN!b@ZH z=)v+muY6f}llulJ2P)GlgK8+T&zv}+rzw38dUulK*zr>s>z9-}?s!@G!soxpxI_8p zE|f1myrulek3Ns_V+Qg*UQHhx*zgXV*oo|Y4weE`b@J5XGj9tAL zMdK-ia_<#gKs?#TDclC;vR!RXZf!%@34Ki?vc~bV;k)WB>IRMr)1c9?Eb2UG_PpTF zc5$4HOb^^``i4>z34?57xhYWQo(*4y~}D+o`%dy%R=(4aaGOd8(9~LhR;+Q zWa?B*iCEQK1!H?^nGUnBT%Q1+B(HDIO9GW3Tz~5fqzZ`&TOYe)Dp-#(!=-Y>o+uFn zE3?DmMyHgbGV4s|wO_dw$QiR7r6H4QYc9UL`1P*3oKz*O?HCfhaQH0a(1qH(wb0wZ z;**cr z5RNrC*m0d*urryjX|&Grkj}2#oJ$1innSC{;2roH)@_fQxGH?I1c9$_{PwXBRF~2pWb9gD{Q5Ku@tQQ^DR1)l`lhgx!qG z_U!7?;@IK?%X=)swXF(G2BeVKmT87S(179m?$gg;9scz=O`&K6PWR?!cn$p|3|M(m{vv$%HILamD_YW^ze z&K^25*Mst}hsf$xs}rw%r;yvndT{Akfk)c%Xi1GX-e0wTeZ>_6;Hp)tQbz@HjY=9_ zmSB8vz_Bj2;nKmul%Gm+Ck{FnYt_Bnj@}zjp+gioz;|p|A0*j6v_7Av53XkxMBGQv zF_`zH7a8frz$d-o&R`Jul6LJQm3ED_mUZ$;$Gd85se_|Jr8Ba+vn$}vpRb~BpRe?2 z-=B-SwQX#e>kN0{V!C|!K7a!{6t?s%&ZN0)P{*#h(opTYydZzmUOHXj^POH(;y1LGzG)6Mk2CCH()NAxjIfhB z*r(uCq&J<0KyyBOj)n7FBS(%WT!XCwpm1Ke$S-y9{^G@xp|KOp#F@wF@w%BNi9(M; zkh+=~0Pn}};*H9}C~J$YgFR8fe&mvF#ubi3D8<&*wlLoaSj2WVQ91~ptyxBaPo2q3 zn4Ubl6+AmLMgVDhFf4A}xi7S87(prj%;9=Yusm=C!?fYjgvq3p;7LAklJ){@jcL+{ z?WOW)Kh%IJ-__tCPCa5(rToyyaM{Z~BKGasxc<-OT&Ygex*FTUdi zF~)fGr^>p#(qoUF!R_{MKlK<)kI(<`Vnc(1GVYAsg#+cP>uxT0fBB(u&qGg?J8rw4 zvADOq`;Y!C%V2K1{SM%(hLYNkF!TVw>!wwF^)|CFrGJ2Dd4o8o`W26XLwpiI8_7rY zSO7EJA`$b;TkdIh#y^@acyvPG!Z{4mB#Wm3yuOF`=fD{oLS!RR_iXWG5*7Pt@XAh% zr}lYzdbto!8;sZ}kh}NqMaICOOq^b37^eV+Gt?KrpN3e+`b#J)PC7U~P=U}XH>Hy? zz;&p$bqC{5Cv>FQp$kpJNfsv@+z;o_(9tp%Ln2f{=@cMQ@R3HjOa1Hk?vw8*hmY|? zgZVYA^2o|^RFe1Y-kbe8j-fPku{>cK zNBj;hU0Rl}SXr*SVzA7a{%vI+hPgu{EW5nOekh{{%5VL~uaz6GzaAHImac(gHE}Rog6Pgz>T%xA%izI9PuAS6^3t z^_PAa*~MMdZ3@O+WD>_m+tC!ZOXUx?U4nf@nE>j$=9}JOM4q4v>S`RgREF|hG==uy`|P%2z28up5!~2bpwYlGn>v$M+be}XYkb7;SvIJk){NNl$}f% zN`Fy~>03vc6xeZeU-{*qd|P?To4=LzjQ24d)J~&2 zuI}!*v8f=1)Z-`eb?(gM$Q?;@3OVs3(_$F)K`fELjUBhZ=HGf`N1(>Qowo7m#U=9@d zwN!dDI!EU?}+!+=4*f&hA}?XX1rX=pVvUmq=9ib`2g; zXitqGlo5teL8F=O%_^?qSX!$`7Rg_{hq9=qVa|To-WnPdjDkztGp(0!h!fG#pd^?g zhx8xQ)%Vb?c_;vj4CN9pal!>5ex>nYc2J866l6PCQXe{=!uIsD_7H zwzIP>j9S6P$KJjB*kj-X?#lBSOx@heey#g63NHg#j-lcA05h~MQHUX75)jrkbqQSg zs&G&TjZvW^%J`!-}6_; z3-U=Jgp=M2a!c4m{Vju6b-bzkY%Z?s0w>S){A}T$$vSn*H(!-=`;K`yQ`3c~ib}0C zWx^Cm4TLEQuD`rd0ajS_*YZ3oO#`p-ok7tP%_T@DP92XjqyfAOCDjciM~|FDi8_mr zys6y#_q)oMzqqfw@4fFL<>ZUa1DVk*)915!=K|X4b!n&Cf51OXtF|k!!we?y$mV%t zV=L13Pi@{-RxD--2;=fHJgKhQcwLUi+w_&k<89|mriKJzcE(@t5yw5!z|-C#YURbX@Wis60=A{f#oE| zlv$h$j+jN;=!OrT=+An)$Zszqu=}c85c%k?9(rqdrF}n0AY4Oy_6nG&9|^6ybiv2* zk;wV02y?u&ulqhx{Z9UET;ofBrj%AR@|mNsz4(qh%GFnHEH8cOE6bPf{u1=@CFmBf zF+8Y#?8ko`CA6n}_Rc%YU7!C#8Q#CM?B9D3!v+%(ta0yU-TEjSi`{tjhVosU3^R0S zq8;t;3ll&S>iUEwfuUR%$n8%>`So^?J294u7v-y=_L~eZh+UpxYxzUB>?*u z;UzE|PdgfhQ}crV9;`wxow46n7-)0aBrOU&dVsb(-2Pyj!YyjsraKUbG8=hD2Gm~O z^C|>ZWAji`Ptb<139BCy`rd)oFs~**;UJ)r>=WhjuRLAuyZ8QbfOG8SZ_e~PyWWn2(sU*i9OvkR={0yt z$V+Qq3A7bv$6nxX$EehuI$vVPK>O4F;UndLdE1YbSHI%L7@jzyj|P-YpTn?lf=wTH z?AXVW!-wKkb_QKQuVIhm*4xKPDL|`Ay9Wu=I2YMS5urac9o%ME2qY1mD;WP1DsMYu;Y8%)~>zX?eKtSeEjjm$Ihi zRL|h*<)ilywqbUVf{_RqiodIbJw`&-XSPv3C0*Mh&H*FQoH zr6L6-+#DSVCmNM{JF4W97N9X~#&7=1Sr!FCnXhXBJvwc8cqr>+6%th9?6}U5Myx_; zs&%`}gcJ^80|*t>66N46a?-J7WRuWPQPv>NA3iGYG6)rR1vQ1V%ofvYoDuL@7=+cC zQ=hA_Z?K(<&PE|Q&zE;vlU+M+!MdpWD@+c+cIqg1a1v)!w3xMdoMzX5XGL8btGi@% z@l+tTgKF3aPh;S4@CNjT;is!lR5C1YQjMEi6HLT0%!kQ=Uv+PVe4jK84x4*ZKPNNm zpAh3!Mx?Nw=tlLveJ~=IkGXB04U3DL?^3oQ+>=n;jgyCXXg33!hJvr+83hYmN<$8s zW~$q?&!We+s>+cCHKjIX3S&aUo$EjlnxXtCT)eF78HJ?QL4_r`_|Eh^C_qdI#EHo} z-q*ZL>%BYZpJg4|^W&EM@WT(G80h8+-NNJ(mwfVTeEx(k@Fj=(MUlDu$t_=r#cza2 z!lj!TxTZV9=q~j*b|sB@YRstcCw0xFxvluIF2bL$s-Tm)?%Pn)i%%6eKW)3VX@o^K zB)tlUgNyB_;UcqcL^N*dmqdbKe-$de`4OkqURWDo^Ug1gU#(&!jJ13RECyV2QaQpa zqGo4i(oLleX+;{*OXkQp8;haj+XnVg;S?sGopO=hH5>{CIEwB5jJ9`@bvh~(a6L^5P`qVhKxFNE2@ zy#hNt#jMPG93{dx8o)9xC97a1agA3E!Y)%15yrMHYCUaV!?L7_C1s8!@n#{+*(Q~3 z`-{S_v#=^@&aOEAWQL!9<@hi%%xMwF*mHp0&sVNvNeZsSU7f4Q8=i-t7KI(f_&nOj zn434@7=30;?;FNaKpW7srieKcq|dpZZtl`iVAkXc>FGOt>96%7ii=FlD$v%Z`s09o5FIQ>=aIW zTtK0BDUNR4DhpPywyOP_N4}IH^nT0HU*Hwci6aEW=a-m9=&J(sgA>RZ4% z`BSXho?os$eMK2qHjthD_wU|WZoJ{D(g!`w=QD#D`T6X~uBYAWUiZ54D4VgKJb64G zPWG8*7cFHI+T^6S zpQW(^jS$(Ae)A{c5GSufBfRjf(fne4_;atz=`V+yhfnmi0AbF}MOK!TZ~}ARyvMM_xFMaV#)5&*V$@z@XzMjO>B3Y+;#;QKrq| zzWeSifBNTt5ku2Sj1IlP-b0`7Krwe;6!V!vU+SU!ZZZPA^jb@8;i;`@J6F8v@-DsV zfuvV49fbZJM^MPuk0yky0H zWH{uy)!x%K}KLJ!%V$l6QGl_t%RdvP6m7HmR zEH0-GSPB#&LWPlZ!A8)fL&rMBz<7p@n^YpsaV$>Tp%m~l3)XhP)N(Klp?zD|iW~1DD7(wF6lMXYSh$q~bm{#sC294y<|zq$m;yqv`C(3PXNm zJ6TUd`)RP5$dfXTvtCXMo9I3v^K>@VQSphE$*j`g0P_R&bW znu_FwX(nGr_C3E%c9RwE$uYgZoVv2M3{b$9@oXZpwe`Ju*N@NjvaGfsLws)D@uT~t z_?&^2-2q!`r?afKl^>Nxvx?#ee$D9uLcfAXs*sWOa+XF2gR~^x)po4EmYu%VmQS1r z`Lt1lCED2Wr1hL|HrDdUBxU7E@N1CYgcC|RnKg!{wF3LzkAsy;LImrYlSu+oGBi$e z8K)W@E|-~^$iT+TA%lhrv3*9NTsqWaL}gs`IzY98pj;y53%v9cfw2~p0SA}_#Mgez z!@OIizT%blskikbPJ`zdToRXl$_qDhRv~i-_>(M$u|Ks6sAb#d9J0OavlX5^2GZOS zuVSU4UQZ@KgAIsNXaZ5{ChYmIP^2n+aV1WEy(dg2<3(ND`q+PcZV-`QX|G1(w~1&J zVFOxdpu(O=#Lb_1!h6E^g^P^c5nWuQZVLCroa`}C#|{-z#tO?JZd-N>m#+4%Jr2Dx z8)ihvGQYZSD~R7J~cYNb!%YuZg5!e8CpI&CV%@(h9jm9z+XtS{cYWjjjTOy^WNjbcuA znC_j9`!z;OmHWO0{TRmfmmm86@5MEDO~y2GNcqAOBTQ`uA1S4NQVa)jAxX2qvc*IRG7p)8y?t9;z9NY;H-C*r1k*&uJp0DMR&RTE{;;=RD`qVIE{w3?q#j}_19mU zlOaC-@xLiwy8BDz=idIa!HMv>M^aQi@U?R8Og83Yvoef0tJf@Mv&qGbKX-_(G?MtT z@7Ztdry6POf3BeJ;>fp?Oh2E+xYY}OTwX$J((WkxHaL0WmO$6Boop$20pZNHw=<-9 zK`O~3m-O5;tMno7$lCh$wPg_5cCD#QNrL7Fp)Su-OfA)CK1~#}so|4vq{!ND{59`3 zR=p)Xg{HiWUp0qXl(a3(U<&%3i{a)2AN*+9{>;Pd>BYvf+nz0R-M4@&_UzfmxH`2w z_QV!8FXXflHkQ1^ehA48+O}PsXwf@vfM;FOJ)&?9ZS+&G`9V(Cc^pqUw!h^Uw%o|j?pJx|bB2oe1Ghd)+M9vd#V z-+E(NwS0h$P6x{Ex8GJ)u3A|Ruw(tb_dQtdf9Naa2nND&(z&0Ey2=Gy`P=r9&Rw5= zxg2qALGV;QJ)U|1f^?~O3~>|R$fvZm_)yM}Zo04*xkS*-lQm*GDdw3vZ8D8Rq~Z#%&8*N-}au{Z=tJ7lHbq@+1Y3;8b+ zGH?hCAK|e)X(6+k2IgvhDXXE7CfIOsHu;+T?0uVuaoTrHI`T_U8{B3yDO>C3fWR0K zqp!FR^9fg}xUBeY@-k1#G|QSzh1h5B%+D+NGPvkMt}^eji0(Y^pgj}!Sd~o`#wfQ< z8kHgqEEzm&F2PqF*a)DI2)g7e?yG_kXe%&*z&M22=Hx4lSV090m2<=z?^9ns$R_fcd zbwyn0L0FtciMN8ny2`xn%S?ss=|f9XSxPZv-jCQ|0@j5tH2 zqCUI`)<|1vo%A(}q%kk~O$Ca~xHm7qB)`0C;5OJ7{^f-cgWFnLqbI@p%dVCay3?ktzHg62Wu25kFRZ7=a5jVZH2H8|N{b@#1` zBiJII3W$bh4R_P%-=sn~<{mfFDJb01xMM}7U-Kigz>AWHLR#1)OSkd-0fhX({**TH zJy(Z2(s5rw_Ln?>U3lUN0}e*n1na?v9%UBP<#L|>01WgSjnwiqPi{~ldhttMQdY0V zNY8PO85_w*gIgW1QXF}w)Q10XZ*ly{k6JZX1yu^M8OLy&cHbQZUdL3AI2*L@PAoVauLIJ4lh z*au)AJLGRFw{V2;jy>DUf`R^W^%Yl>1|0GyjV|O^$mhM_*0OZ}0JHCIXuF`S7#u9K zh%*HI9&hK4-{b6mVEZkiP4uh?FXVXy#l<}oJf8FKoCz~RIDakJlD9((ivUMH*B zLt)ItUQV;2;4u4nJhk~*HhVpueHprF>#Q%P z{0=vCqu**nwkeeZUTCq)oGtr=6os zuiLnx{P>T2Z<#l13L7QfS8l%frm|+$D&$lQBG_s+KeM}hks15PpMI93>`u`pDC8-R zlT(hd-kw?Rg^LHNl6$Lg;tMAZedj-WQ~B=hHfMGX9uLj4@4fA$FTyo>=q!Vr?D4zr`-}1$zxDr=t{GkB9dG-= z^3VVIPq8P_(tNJD_IhCbbos(P_W}DT{o@FEfE8s;X8tu+*#}h(QVd^#A??F^<1zrL zs8{~yhOBk}7stvm_^%tNW*;$SN)RZ|a8lC^SeGqZmgOgPuN?BGA>^HzIH7*6>}Km# z-N3#NOj;I!$?=6(kQreZqV0pu&_DAGdrNRi!oUC3cb1pHqo*-eZQHh$@q?uX@K)=j z0omo8PI6kiu^Ddo>e7I^1i0ltZF^0M&<1_Y zU&-?8iGMlwubI`?@uFpBp8Gi;Wo;@#!ZfVD?kMX~b0_HBW9%TDnMR1(fkFXCW+Sr~ z+KX6x6(l8Y1#{iKth~yS>EudLsATwr*}>X1^Od<)K9aJ z7VZ^_Os^GAn7k5~U&GDM0Zql+W2Pd=l3v)gT$_&qQI1ZcOv^J*kA_llwA0$DbmLKY zbQflq060i!;BdF-+PM^gYO6)CAYFS+uHR&eXy0G{rFJH^J_)Sf$%*{@O~}OiN_qg` zf0L%(HxHMy=B}a#7-4b~`2=@HtMH}_!h&~$o3ad#1(N|mrgk32qw&Kt&i8P{lJB&T zE5K_BHND0Z@f^X=LA7RQ1Db8(7*Ez4MrnMX`AoiSqu`KW`<$>V++@bf0-;FHymeqn z+EmUO)qGld5Du{I$uf>)0ma+&i|CA{%`13m#Kf>;#@AEEgX3jOtaA&g8ip(5% zNq4P6mYAe(`%`AMNmJd_6?U9a#@Y^!bsMuh>(*ZO4c`Yo0$XF1g9<3*vR~SUyrWLm z#hDQE6&D#0jmY~boaAqQril>Dz3o=7T1THP&%d@F!Ygd1$vYoNYx~>w*3W#?w#4n_ zS;54sQ@%lb2QMP<>%a@Yq3>xR#KW4)b|6oF%||R&u*7=3Oebu@p18bdapO75=5PIt z=Y8UlpD?FSlYjLD(49~C>IQS-&AM26t%E!c*hpu6BHZMyZ~%h znB?oPe>HVO|H(wUs5Db6*|u|S&%h#Fq_6GJv`g@59l<%D?@?Y9^o5zOoh87FBYHz>{6 zD9iy*`qkj)X){*PK2gI2u`2!6!L~xc?qoR`d1s9{Wt}+gW~Q8k(d$Ng9zW=Yurt|s zvJV&B(K3iqI0a>YDuT4@mYtCfPHlAZ3k-~}!fkV=9TO;@43aYbc3|9aPZL4x1!t~z zJ&yadXM>*`yTl0r!)4Aj&tuK>tn#tD9x0ng!5c>^&h1|xym>5eX7@lQXDk3G#*+D~ zdB-M>%t#$My1R6pIa<1zLF{2I^^#k!DO-*lEI;?oUn}qUg}0a6a2MbEz{9KoK3V26 z%O@)z$6dW^4t2mq*YT%|PiKDV@4)HCc}N-X68n2vyL6)XUc_bpB7H+#Sk?3?$szRx z5u|Ca+Se=YB?S9{SgCXg1?q}SCa&LR`ZVjmO{?)+LEV1hn%QMbmzKS|_OX%PV^sGN zyO|G{XSZ%HFL~*!STZpKMfOzL{KS)-Q9oX;zU>;8E1c$BcU0sAPr5~8&$Ba_Y`LM-3LJf%JFj@<=?#fLuJ8imZhPLb>q!2gHszI zpY#=@x%OEF{WOY|n~R-9xp%hSqeq>EcBxMf-X64a@GoETI5-u%bF4wWfIN4JBLeNO zy7cSSVq0Y_f)?COU*%TbXuI1#Y0)&hW2#D?mov6?{POr_H}55oua@6g0NHT?^u(2b ziKi4yhqC<2+*%q+NaES&%%g!Ka2rx{0v45V-gk6plmw|vrc5Dh=h1WJZQuVIPQh5s zO!v|9s@J@x0Bt~$zbu}^@xLrp&^6!XIvdt=O2~OmS}AM@x_MjKd+11+$?*sW4je8o zeBQO?2Y%?yxZp#wl+cZl&gC$(Ft|Xn;M0A3icY5m~=g^NCeai?-NxuJ$uPz(bt|$YG`pdet zYvUy>dc?3}aa`fKckiYiH{JwLPsZqA2@1nJG~gI2-pRM8U;El}(~URAsPO0`592A#X-e<|WfJw35so$N z@0$-#uST;YM~>zA={0NIe456ZxGL35JbsJZ{G%xLG~;FTebsFkM*DW+-Q`Z*zWRrM zjn~GVNc;~+{r?qO%Mextk5dxT&@i2Yj=%sp6~#6kh0Z*U&U74C7@3>`Wtb5?wF-Rz zVYq(~uMnqmJIF%#2Baik_@SfN8QgKS3gmTg`AdzMM!$d|*p_E8o;P?~P4RqF*k8 z=O%Dc7^q0Rd`~1Gz2!7-+USOo%x!PZQEX^2~Enxg*}lHt+_YEgj^|)AMjwz;46ZJ2BXHv)kbS! z15YyJ&2fJTS4Mqvv!V{s1XX|NI1fkAa5*UCR zkR|fu=Ckx790YMq`~tVUq7LxHM&OG;<=|@l1DW-x^=)xteyxGUd*KwnQIPqyAJjr9 z(85x-<=Y?3%b*I3_u`_`$V3&0z>9o|>3V0&HB}^j8>PW3FTz(z79JXg9f zzxD#E)R9cNtEC!0d@7FYMp`1F-XXT1V+WEs<>9@Qf-aAZa*EJfP#_%AR>eoa;>+bTwOow^RSA)Xb6z$| zPmFdL5fLHrI74A_>>hLP7+h8ryt(An)>iDvpDxpCFq4L8F=KqO1Hys}8H4*F*u3(LS?W4yzSz`C_Xc=W)z6OLj7@a&RfrZ`B1m}EX zKhs-t-c-^iS9vjVNyZWtNlFse@Boi-t&=)XEWx2+6i#vPQ&mKr(RJ2Zpwl#?F=3V#| z_aPm_sE6fSugcw;sMg60ydX}`v9G&{A~zUU0~K;kFYV#rx(o_#v!*w2`{vfOj` z-Q`0c{BU{gYhG7g`yH>xZ~{+4VfABKa^z`j#Ax4hB2Kw&CdQYU@(OTp9>sTf6!{kK zk?Cwknx(hUn&V4$?uf$JoGct)D!l%E4(GV%SC*yPAGq`AN;ozNkz6e!K^M z;irDGyy7Ld00X>>B_7jB%3%&=FQ+*?`^?tz^p{4zO`sfl0XL!!%XkyWEAsR7n@%DIH7; z8|%zu_&hr!=HPAzs!AhufavW2_2MogB^_fTq{+|cHd<~hSEfxTmco7Az7N6680mZn zbt>E*DW!66htmyTOI%&!Oy@SO`7me*qcB@n2Py|jU4{+Ul52U+>X>gBBW`uZts8nw zu8WY}c1y2^tbU6=fcpdn(}7rm0UplB`mgc}>)X+bC@Gzb^z~a5JS|v3w5E%HAkN1%#Dttt!Etn#p$>e4+Tq%Ly$zkNJHJ`r;cz{zgkk84R z=&mbO*puH$OD$e?IkXH1b^E(CYyOe)%oTrejj5KIN^ zy3S^2jFZPuO3!x8C~G!cTRzV0-T}N8=Joe+hCO{senDDcwVcZPJ%gKbo7ucgVcR;L z#qi!eWi|>rv%zDy$R6uPs2$=cyt8E?Yw^dIo-XhGz{kqZ{NS6*T!h<`2*6o0PxhyA zBcDS3yV!wVyvdtv0eQPhq(E18fuN38L;wOOdR6!?xF$mV16THUahX4(6Hi>*CRT?3 z1P~_|zqQQ_7N0eW{6mi+@nxQKIU>_p_+ieizJOt-2P4M1!8PTHr?-@M|KXpM8?U>T zjl%XavpQ5BVAHUZEDxN;aa@_DWron}?>_Z+>{$Ld>(tk#oDJ*Om91O1;RZj2qfZx? zp~FX^Ez8Gahj#WjTh~wvm*;ZN##k`K5sfNE9*?OQ zG~YR9`p>YbUNb7szGL(8r*kM>%+Yzh4GflQFNq1p7QvpHsv*>Yyp>(OD<7dX37 z>UFnQ{%ON>xEH|;Ht*9DQX0)JKMc$%AKsS zuQ=f(o#$g4k++_Ex!Q0NG$90gC+&e3FW0L^bY}J>F40GZ4smQHCs)v3%6*Ot zwqxx}HN`|yvJkGzSCi*NVDs#cG~|cUYuO2$1c%ht=Eq&)nzNyP_~yrBl{Ky|oHx5X z@X+Js1>bf}x#6ap%Gim6D2?Og3XUp#``bM(ZZ-0HVJGz?@cA?JzeD^CN_yL@E)-Wa&`w<@vaPhdL?S>BzN3xiW+kkOY)$K_mLqlcLV~?_& zU~3sVitNoE8|JT9(&aWJvR6e@y|)aX`Sr>z@MMjA3m-7e;$#sw$8!U{OFi&pVWK{s z;IVJtUJMCGlGY7=rAyN*^J^$k7f^?ge_4z?0Bd8z--wgalDG8{u@FxDvYYzAd*%wQA8wTcQLDty5LU%qP}?40JaRng(LrV8X;+41Z})) zE*Vmk88hJWJFdJuSEl3Ix=J20o9T2;j{$KVqJsMw+?VWvc2ME)*cZ=dAHnTRrB-1~ zxZO4O{CU=;1(eF%qS)g$<5fF2F99I%62=o(Wqhe)!fI$k@9<#E>(nQ*@>I{4*YT-U2IZ{KN6oWl;#qo)oc z$N-0m2l28o2@Kd>fz9*Gnd1RW?}tk$QGskS+)d7xOE5aIj7S|+977X|^t6>qN^si# z8jJjl9_xJu7E%y50QfHXCBr5y_ZC=#YX01(B;r~>-{mzzqFAnYB0N`q(SUd{VF8qpj3p8SO0wv3udXs9Y1)}f}Q zMonG~+_iG#RP(FFwdFN&lA_YIZ=?sytq4$=Y2hT8`_zZ}n`2uy({w2GFenGk1~2jn zd4qMx4*xuRx!l8i1D^R?H-7UjUwOlwVZve!n|xcNMV=ysXSGFt}zyc2gNh=Liv~bP{pH#w74-Y5t1h1lv{-*Bh@+^ z{@m-o4{y-(+-RxsbAu-1lPqvrMd9SCcx_%z1XNrlKVgP1`8RRdhCZ8* zw7}nUs#dd3z1wu@J53gW0T+DNnU67!T)_2JI1E?#jPVyExZX-G=Q6v@tT%1rb8yP9 z_nGD8*DJ6zbu)d&$`CP3`93oz~9OTe;dEmS%D* zQYoydQi8wwD=?Bo&l^nI%%-smJ~F_V>vNfnU2@a&%EP$&esbq2H!FPsI&i4}zW^m3eT&SZyy)J6b97jEq2-v$3_F_9E_r zOYhYB#LZ+ZTz-!6g{+L(#&L!|G)uUYWBbV2#ipD{`A7v;KH^T?t5&aOqr9W#6QBGf z=ftBBqcrc@c7T<#z2y_1_*{AKpM0n+o;w{6K_(F{G9yd=z3eA|YMimu8UGc_SCCeu|0mMkg@=F*AWE#Yf_@z1MW=nM?Pt=1@x@4tF|=*!M@0XEE8?7?Z!cgC`(J+KX;~cLp2Zm0SkAC9La^J&`l_9)KH1dcK`eVaCPrU87%Bx=W^0H)L5RZ`K zIc{Y`8kiVYz;V1;C};b&UFF(qFxU{@?NSD4y3$U- z_?G+nM^WrW>eqYO0luj(;8S5g$FBBvgb2!X7S}K;(CbPl5o?9^SK+}LMaYOyUGJSS zuoJ1As7N^bt;@5DUb-8DkjDnu5fm~_9|4)Xnl4Jdc2}O{7%9aL%RL2V)`L*rwFDj9 zYB4jIj||4OTIMZd63!|7>e^z*b{4sV4(RO4p~HtVBVY5vRSCi9(7}VT#+kmItv`v| zeqEDWg?%?Ha-%O{)uW-#Gzp@RTcVKE@AfGnwHnRaM5$jjdg|ET%HG9I@L(ofme<@w zc**-3QsXr*Ypj}6n_n{Ly>&I)z-)ePmXqi?sBc~*p7;hIEzSGh_O&g=#if1wQtzw@ z=cP2Dg*;i1e;8|v6W;|6znYH`xeqAKmvybTmlebe&JHpP;>OPaQrkSKNg&?3sEct! z$0>q3H-k-Px5zoPlmdvrmC`1jy>Z}Z0{Ch1kRZyoo%7Z@G|^I@npv$|(#d@5;3iCx zs?QbwMl-XDTa8gb2CNNy;);*iJD8bHxT9d0l75>uF@o`$dIyB2>^7{Xu^u(O`SRbS zF?mgITEqFSdFT0Z-fcR6jWfCOH4lRt-0<7RAcq>ifzd%fun`^{@YcMNzai$&$Mp5L z!u#LIdlM+Xv#Y-Il}b`cD(!0Rt!}C1Ufp&tcH5Y?4K`kYF*rF%CIgwnmI)Bz02y+C zlN@GFW|+*9$s7(DX3h*GlOb>>1P2>1xVz0pi8<$zo=<2i}FI3d^bnVw)~extP0fO4$s+ zdQaToqrCe7j|7;S+X$D~2X8o#4qpaysGBYqw8L`+BTc<5E?wujvKDy@;sg<9-5O-7 zq9-6_GT_%_3mpTzO8M2Vrs!@F*z&@o`*l*hkNkpMn*oW%?w6jVpnQ^*&nNPHGMvkB5OF5fQ z()$y5@S1;LgM7dN?8R;f3VpWWt{6E@Cvl99<2eQnmT$kMoo1Q!`yP9wZQ|tnvt!Kq zVQ|jE4?FRtpJbbPbk>{`o|(Zqc;FxhxSeS?@4YF@OqbF@cS-;G8O{j6wwPG6g>T!h zXs0oZ51%^McD(Xc?UTR%@pkWP?`f~PX?L4?gp~puBDIf8+NFSCzJ`*-81vm=I* z(^^4Bxxh2eMo_Q&%x&O_e)7imMY)$|>wf_YuPYRo_*+l1>MIN+Ax6JFCqcN^-7<95 zlD*U4rbF+(T-F29p?^LD7-w99&%WoWDdIAlIz7e8#(B0j(78P~bGhxCVPNCXqe1!E zLfp3RzJb+oQ|-O)c~9E|@0?gU%D2Eh_}A}}ui?|Gr_cBmmL+t8PK4K!oa#MGr~WxU zakgg7BzxsgwnrZMa(m|4{VeTf_2T*Ywss?*uDf!ANtwphfaBzgnM)4DTd{min`I#7 zxsN^u1v72?p4+hJ#@n;cA8LDd?`hk%(*Yri=cdlEwW3a6_uPtQZg;T0(HV4ayQ1TP zbFQ>dXDi2coTtyTv4Ss0I6$T66*`{|dMK1*=&jT}ld7;8FtEPzQ1w7Y6Hh%~PQ5)m zdgG6g;p@e&E_Ar1>z7sjnZTn*1K*Bwv;R>B#(YaVq{dwpZQvS_YeTGQO~(ZQHS< zE%~EIDF;{7a)=`3;$a=$l=1rY8?)ub!z#~kn4h2j zJiPG4|yFHkFENDp`~U&pn4x7E~VLCyo`%XKNpk zVsxk04$5#yYh$ZhH5@jP&I9kMkSG;b6|7{|*jW}2F>=sBxQ@g*>iF!l&rs>k#Mlsy zhMJ?|Sy}@=N9k5Eb0B?IKvw{W(awD>bA*qCb=6!Mh3=j);x2j=#Z|7tDo@&?^56et z)tEeMs2R_!#%?I@f{UlTG{FcD5A}@yf-lcHLn!Bzq2c9H9=zJA@L6c)Spq6<<}$eyvqaMy_-hh{6{wAjre<9sWMzQ%Kqq~{1YTW#jSWsm(c=R8ZF~% zc+R_xnDL+_>8nw5)SFjmNctDxFSu8bHPcC-apghMfjiISQOxyUxQ*WjJCZI$hT`z1 zcXrFitN8$iPvWt#0@Cu1cfu4TR%)ct*{8mnYtd zRi24b_>>uqQJ33hdjSc@$7@wW@u`dxX97B}gp;z62I1xc=&$3Uc4oU zi*<5jAQI5?Z9Ni>@#Xt#cC>TKkO$5=sN^zZ>z<$Ma<8R^ z+l#r7DMlX#SANw_IvXZ^>RRJiZszGSM=;yYTCUDOp66TF4#s;Ddtx>bUzor9nognU%eOA$o;n)OG?UH*RU4-gl@?F(Wv}0eoES zEJ1zu`##j}{V#v4O=9rRJo;#xqz$kWafN(OtY-2dvxq&f;HK_b|J9$Cv2DJy!Q*s3 zt(VePa=G}q(=72}a|S80f{%QemkcO!cg&3w1cS$py?G=F<)Y#39_K53Hu&cDUElqE zHP{2fad=>bcZS+S31>OH%K`c?fAP!h-M{`@taeySr-cKYqE$y%W^}j(U`V5`= zqnWM0JXZ(B`kibT0XfUs6Hh(e9{BJBtflvGvt@iv@mWyN$>vbNpZRA$%k1f0DOV-v z0v!zx2i(9GgVS_UHghWf_MKbdh_km0%q-_S=yZylu~(C2OMqeW2-&xt(NitBbP^Y3v>%3Rkepohd*5ERx&XF(m#*! ztQ7dE2D7CHp3O4ovFrNXv8(@^U;0Qp^$V1nyrS$jQ(oKIBfp+A1C*h8$~Iq{A?%q$ zkG1dm_BXfxs#9g9(=TY@(-V6Ld=5+ zp#|AqV1xAv9fY2fSliGG9I!3V^v??2G8RZf4*Rb%CaBcKS$ORxxnKXtFSl3Rx~Dz! z_?I}#;VBOOywLuq|K;Zi8Rv74H@5vp&bG5`|G3QPy;~9-(8`Jq>hTq5kP59Ow(G9j(2lXq<8cN*pLl}LQ=-G& zn&THKRx{{!h;u^rJ-3g6BtEgtz{L^<#SR=e99`+xA1<*qLRq=U>ag={kvMUj?L5Hv z%i#V@JNDgxSj@;#qi%)k(!MytHP1%L%yPu+n!vvRuPPUnZBG3~K~&SI5y-(n7$=?p zzl`NNOE}$BfsQ(&a^zq)c%W0^skk+W07eJCjF;N8N+*oUlhLsuTwygHtQk3noJHS#8C(ZcdGpI8Bw84!mquUF+-U-_DB zkjAnwO;QycwfZ90!;N8(p(DQmQE|5D$ul6s+X40>a4&caHskS=cN&es!h7MeV~-ID zAN&cz|0u*NDCq#x8^QK(d zC|A7jV+bpMVDxmMZQza1FK~o`s>3jA(y9wzg(Gi=pEQLq9~L6!*}TO|gJhIu0k(+v zA0^XBH@-AySuOXDr>|VGGiw?RczNF&z~ocQDiGv@d@@|iTwngeBRj%lY%!@VBsqA< zWaLY@Wj+k@((5Vy#XsTdgk4Yl>U)(_;i?G48{!H&pF$G}ag(q3L0^FBS#`+pkqcZP zlUH30OgK1U=iW|0!ONh5;m~a7&$_FVFX1ZDMtXgbt`U_Wit{{xT*IyC9`ZZTP;rEM zwKFf*(%cy&-_#G09h32%?B>~I1O~15MR0gcl*Aui@aTD|K&}fx1o~2WFrMIa;z(yb zVId*>*H2z)fF%~VY|HFQq z%!D-W#9PR2@-ErYuyiO~{cvXLL_RmQjZU`3dHISf8coXpH+F;*B05)2tYts*p~EMb zEgx&U_wJ?xZ~a7M=qroXXYtiy-qx;v*)8N}ZTqd?`WOS{Y@y)0?Q1t)*IvVC@$S9* z_O{N|^S~B^5+SL8%-vx~YvXyU^#n`(-~5*EU>WvtKBxB;Iv88BcYOQSjqTQ(_Q0ER z96E1bdG!8@d+uo)iSzN#e4LK@ws!MvujCZ}C)!5#VSn!r{GE3F#?^3j0e6R^Ch^&P z_&d$i@3GSt=!g-*o^4g^5|#oeZ&}_>TV_sjh_0C-@fA8=cJQ1P^*sZ#WKezX!MJk_ zhLrtWI>$C9B}kcBu1Fkhq(cJbY#+4GJb7JRD9p5<$er~ib(8w3ymk51&egwkBG7rZ zQ&;sw&JRu*zON6=JRy|=mNKR{ZyX`f(t5*Z~LcQ#&yCC8$DYSMPU6Y zMA>dage43nU7%jC;0%O&*n;7<2eoo|6rQjR#P&^|@ILMya^~chk1+s79YAc`;UnkT zM?d)S_Ta}JWCg~)HVvI`fBUzzzxVfkgh8Q|H5l3LK427`5GT*1iAT#x`%wDim-!3- zj5GX3`~!sfQLl3HCCmTE+mi=QxBu#0-{0Q)=GR8HcJURD*T4S$baM9{IK~qE544BB z^aLGp2LPzs(ZAs3ZY6S{BkYns@JW;S%yVqAJS#`Fy43dE12@0&m9J!lkgFRU47Xnp zKvYU6AXl%c6}=e{9ONbWqXMWqmA%-%*b17vD>xs(PWZ-6Yue83JK)6}`|6Lj&z?F; zCw@aFOA!Vp1y?0qw`DvZWs2=A=}#~SOQs@o=g(hYRnuW~4WHsh-zqEpWPB$jd;495 z^7VUFJ^Z=2Ug5qP@~X_K*Cm8sE%J+oMRZ>@Ox~0qk1Kg4=P5gHHza}nM!a{ z5iPDK^o8gCDh+uRFV96rg5^zr4~Wsl0DdFp@ix%yU1jFopR}P$3kOO{g*ZnG;lPL^ zkFzMmNwzXr_TeLOs`ELZ4h@!70Kqd9H8l4!twv1zMT74?n>sX5roEFIdI^y}3Cc{s zkpIr_q#Us!fWiwK-?)AkLXZlnTv(TIpYZMFJESpQr<;dlFn9-ikvSRwgKS{O9BEEN zUN|y%BV_qVSjUf7V0lT09=UWBSmVZRBI1>PI~<7$U3CV+Kw}XWz9xe2xRTH6C`eN^ z!U-A0HBPd}C7pAFab32r;Z6l|4ecY&8Q&lfi(6RyrJO@s5mcNhe+>ciJFpmj3~4HP z!IH1E+NqP_Ye5i|Kik@T&PYCEY*=Tl?`{bat{7s-`)qpcDKl$0_>~{a#}13Ls~!re zo^rKP9~>YuiOgTosu6LmlXCxym%t{1XezA_mB=cf71DWUoGOzcoOs4IyyDa|UU4J8 z;k|e#JPZ!>=8LQNPDB#-ffYZGRHR^0y<(Pf40SCjM5MRE*8to9%^JM|Q&wljC@wR{eNd^EIK(WJz0sq8To^1dAfd|_6{?)g) z8?WEhHggiahmoE{jNeeC!19rfdUR%_?>Jsik(3!SU? zw+DXvfp*V5_mXeyI5g=cmiGJEyzD)OkC)J)OPCRL5aZ(yKHPrm!=FG-oD;?$d6&n^ zsbADFeaU)t%I#%(V4me<4Nxyxcf6~Ys5VKnP&O6{H5egVO1XM4pY?0-O>wEq`(e;j z&FoY5D@;m8ts;;P9Jkm5c{NNMLzz(!gE;l4E<+L#p&P2>IEV`QQVz$UV-6lovMO{M zc{$D(1GaBo$Eq1@NW$GVBR+A&L)i)Cb=5DnY@wXmJB?J~|6c!uo=E8FYtzn{+M5(co? zj^MI>Y&v;sSbyyFc=0E!4K@DrF8gt){|JfCyg}`+roTKL+Nt!KG*v zyeLzI#)i*PPe&9ZY&2X7bl+o=Z!%gn<;9S7jYd2WLWRF7oQ>@~6-uXpWE?A)%E!hi z5&r~Pv=Zww(nVSuflFv~E4g7K9vjE<3Vf6rcSr9G_q5^5UfiG}X*cy*IY4+1F zH|^fj4zX`iW$FGeJN-7UBiD&m>6&@}`6c7ty92EJD_+LPg$+95Q&HnIQWt>+Ps@KeWhS4j)L&!OKNGNXB7Sw=qr zC@_SX=+qnd>9cfNr&nlX@?NVP&_&2f-~-M^(F1Ap5RPH`m7&HU5k{pjYBr2Wmc7(? z$&+O%uEl5NomopeOvZAdExE#!G^WMXZ*;5q$5HRu^fF@F>%|RXw0`nyt zVcHSNUuH zS28 z&M;oo72z6XHo?qb${77?C*Ol&qlY`(QDPtTT!j0ou!WZ-<<(Bz1f98AI$`c{U3=Yi zZP}&`ZT!&5HUX`Cr7R9IGMIU3-cDeoKd9uFawtanl@TSsCgUFS6)b0U_AQ_4!!B^& z{BoAE&s}6MJ$ac=hk{R2-Etir(1Y#LJuh!7*0OB>#6jvh-&Lnwo@Efuj)MFzETS!2 zLB7dD2SO|dt#6yBfrCXi>140@C2Cyc0spKJVzzTLvvHH0E{{3Hw#0M9(`Z+B(7EPM z-E05E8R{kDezI72dnhIZ-?9&fL65A~iq+D9JzO#8L>e~jh6&$o8) zZ2M1t@J;PqKlJ@=@19+B>ZjXhANp+j=$)h4`-0)Ax`T5;?rMgPamUmbZJT3 z%-;NMtTdRt?BRjhRP@^9i*ic6ad^lQlF5knNdKyFa*hLO9K4ukmcDGQ(#a|#>$_#* zos>5Efz>;c7MfzHF1Iu0A!+W#zD$}+Jc!SI{wd&UFnA_`KjP?m+4l#1As;+A;)vgN zxpWu_2O7-Va@r2h*VwjeNBg#K`&Qmr{k48gJ97L)d+4FhwdYuJJ;k7yazkq-eM`G>E31B3=^(AHbeLlx z&ut}sLe$JC3uAP8b10>sA;Die%WTWZk|}LKpNnVQ;&1&Gw|Q_C$OQ%@-BxTqCh6QS zM{i1(Kl?bdS7x&`Up6}_sZP~)>jQ+^`^(6iOYt2Xo8lAMByAfvt|tY%SHR=f!yM2t zjcu^`aiYMy^uC7u2L~IR96QH(2I{ETtfa|m*TnVEKJribc%GHGtyg~;+@ER3{;M(2 zg0KSVdgI%TgZ^$<#WCU#S6{L)kXp$cp|>KWL#0%^lu9L%J!A+dFqV>WJKs8m`0_BD6yc4pd>bCZ8ZL`@Is`#t zoV=Bn!kl+zApYbaX{5mlh+-oj8t5wcEF2}=%CrBu=dx$WJ@_ueQ4M-xv6V&G*%J;F zXI?b!1s|hW1p-`WTXK3Pym3ZHeo2t|Nj`n;`H^D67UWd3}C~ zLA61*t|yEcdsjBN zN%T1PY>E&x;~W~=;I|><3deOXeE=6J?@a?n%BYCEWN<>w9=>>;eQbr z2^-b70Tl7{@6i|T{fT%1{UXT42kquVUIoZC(K-+1SvO#dW++Bj!cSmm)Geped2#MM zh8JI3Vdh+_JddXIlsbiX+f@97*H=u4!@=$3gZxQw@wP~k@!~-wnVBs4PR$A74p3Em zW#7SRJGA0*l}Ze1AolvEY~zhb&uH<rk1Q^_K@ZEh~X0K13MEVOhMdvUV6wC4cW#f77)t^v|?r;Jw5)>N1tpD zfAI-AP_^=51vbdVGaPigVWJ&5c8FPS4hm$6>-4dGwBdYp0G!Loi1Kcy2J$kf>Q;IQ zS)e6BmBm31)w1pok`5eC;e~b2pU$xW59C$Nq|?HHgm+i-q*{X0gYser7@vL6<4c_V zTh(@K-PtCYf!n%quI*yK`<-{ZqFu+wx@RuTwP(J8_S6%v z~{}Wk}b2qc+6MUz9-+@znfBq01pvm^P zzWYY@OdnzJ_cAAbZ){IJcd*@l+s*AY-|!85;_TtJ>$;Wg{=a`u`{BR)gY7y77A~-7 zd4lr%EAMrc8p|2XSwdY^98))qloGa_ee9`yx!PH`%0V}gt$RtMr?i?!c;OQ4HLI4lFFp2n zyXB^x?VH|wKW8TJP4?$!IN#uSRy9IY@*^PiLH<%-gvd`^LB~b7gAiA{Qv4|aB~0cK zztbYDIA|&$^2xd=E}q$&&+u0J#b14(ef-m(Y4_iEdwa#p_p-u(LoHdkap=$yR(u?2 z`wt#%PwqdH$+K#2%igo|PA-81ucVnwyZXo#OX+NqC)--vYIRQ>Y3TMBk0`S$TL#Y2 z0n3)MG@bPHI@$`ef_=S`x&jpXAB`2ZYXJdH;Sx)op^lUPfi5qp_v9?$HBe;ErPCPj z2v$g=aJ2PZjkkfxr$Yx0ah}#`3oUlN{?cw6@12ymX@%2^|8_}bRgBnKL{qv#Sk|L{@Wtxk9H z)ByswDY`+D29tqcTAjNp*)>)QRfbnGpp6jUl+6_|~be%|A_)zk3)r&+$f+{e7*957G=Cob>dRd{KrJT=~+6!givjV821Hc``{s+>(5o>SSieXR6a%5K%l z=c9PgIMQjXdx)Q4JXnUa^FdA(R57TG_;o|bLp97>mh;j$sHo(eG}y=lFO^l}-^Sg% z6fa7p6qoB70P?D+Ni zWc>`mMwJIc{gAMFuiS{e-is$atltU5xU!xt&PgX^xC2C*O=G-r;uNMB5+QLi$Q4+{ zqd*;!8C6s^j0;8*5Y0=6TR?-N;#Zwaog;CtGx9Akf?r)b$Ra7_nVtHzG=es~&N6mb zjww1r=z&cRwm3-VoMIoC60xu}IBdkjCvuh!J+xJsl)iJ8#Jq5OfhJ)MOv+>N zDvt*AheYWwmHmaV?jMlynRF?O9&pv&a8VBRG<@bAeONS_w~8a(`S0)Cdx$Ws+u~A{ zDqDsr+a?-G3t^))FC^K>BUjQjdaVax%ZCm`7(83wU)&XxPN{E&wgVVamFJ6tcoAQD zqdZ;f(m{kT4)przulhO)a%WFsKq&>b7Y+cs&;H^Z@<5xU(dpKis@G6Vd^_{%D0Pkc zN4yK=v4A~g)yso8zW2DcHB14gopsfl+=_uqe4?eSg=sx>JH>PRkF@Xl8*ht2sNp@q z43e(!$|!%=@XrW3;SGNk1-Qt?1@d_TVYtK$`<0aw?Z%sSwHtTrrK8U(1(L~0H>r`+ zMJ+flgL5Fw5;okQ6zG@sn#4X|WH9da_ubY0{d+#xKK#iq@I80FHGT3}JA32+r^wU! zXG!^GXh~D=3>@u!J`qaU2wVSNPf|Ay+@%!N97FyK@L>cM}`U#l+>0E}pl>Oy1EKR?_sq+rZT&7bs!x=@M{y(#d?TKu1 zzsR!t=^64f&k|vD)wwW-tygHK8+LAJzxM8T^O?K#?TxQ~Wqa*w?`xm_#AnlqGLuth zJ^x63o7x?By`uf*`+vKwTFWW|a8I%S z{oTLzYwg^blYEBjhw>fy8*aD(o}e?$0Ccz|VmV7I{^y_jxi&HR6YVvxxvg#AwY9C@ zu&Qmkj+545ntWS<9zF8>;dY$!1g6ej9^=1Z6CwAco#v#}$f8_pM()GhLv z7*w6`lSj%4TMK*3dTHFqKjo$la`pgmK#sp%hXq0iKZNKa`>*+iVA9)^raDuu<s>mGwlTR4y4U;f*7x2GTH zYY|(wx2M@2af+qheg@JGq@TmgYCO}5VuVk76}xu$O9n@{$($9X5^#q^5H;;D_kd6 zZ$RhOwgWqz!ci|o4_br4)hAkPQ*~+MErj5<9kC1t8(BMu!J2vDu;SKp=l3y~@Sz7j z&}Qztv#lKCEU%^12MYV?{YTsHeB@*8@n?=ue>}g0!BNYN&NN8#%W8z=*>We3gsY;Z z(XuJ&Dj9O{b3gUrh8sK_aBXJFJ&)uJd)(FGI_tEv_iiJeIyc2+;A&)jQ#$Y33(D{Y zPVHZb?jsjqnd5N0&FzL=H^AT88s)^Fo%^%{#E?G@b}3_SOUa}uwB$<=)CWIDx*B@c zub-n|bsD|k!Kd=v<^4XZuP$>C-}S5r*uZn0BNT$a&M$v19eYPu+-ITS+fYP#scdLy zQdh%tYnyMSRQ|)t!L)x8C;a~y*WpJaM3`Noq5#H-r83&Fbs3_2vixr1G^d7|=cGW$ z?a-+=H9F*gqjn0m97qSsn8`ksK;;FQs_PumhrdFu0?6nd@1|FQS7&7*Po_&QeV{VL z*hWdE!%g~hHi_T}t%i;CJ4Q!P3@qvFGo>nk`FRiHKtUyfom0w@{J8Wo;g0m;)Y~F< z#!mWGIKG>czWhrarr{vpipV78SuPX~6>K^v86YV7&5DpZuWj^VP~x}Pr7^)Hv;=|S z6(^07c@UGd#z|m>=c<1cKU9}@#qwoHGHW)fBb9vA^=??m6{O;Vj zqdoJ?v*g2()S&|=HsHzw3GgpoxfM;-_ylpnBsqk54UPJgujP}2!DxI`wu3j}^0<_9 zwPw7KHZn@6vKCMfuPjK84S}*F12~u5@7Z%xPL2M|XFk);ou7`fx1+CN7+9i&UP(4D zp~sBicpb52fllL)*CCzpdU~H1yMie&Aqn3*MKwO>lCEhw7lXUuDBI;G%J)NFGHzam2IPc~$ zfdyHkDzXbR`e%sTKN~$wnhdm&LcMR?EA&pBsduTUCu@gaDkPlej$~27X@J(Of6mvcs zCC3CgVBoo9gBJXkkXOUqs^U{V4<}B_ei;VuVLr7qi+@eLf}cH1pCwU2)8DfXLVtaDJ` zQf9aOV$G}XzN2m0v8_G#)FWBVCC^>*979>W;tS5oi@GAVh`NIS2kplg+*2bj3=onK z4w#O@fy~m=`pPle{^jhy)p*y(Rb-iwW<`NI%?=gTpdp0AKYE~cgglwtnR(_rvlm*% z2+IzQ9pG3^EPtNi)c=_oRvm!$3QO0=mQucxEQ>xg)jsl}_qW%v7kcmRZS6M#cWigx70dFVy&k$*b_M^7B3!?LbzyM8+-d!GQ#d^^oP>4(4gh4u}vxwHM1Z+}}m z!6c2RY(MwZ)9k(fR2Fbdu^MydHag<)=ZafMpq6uh(dzT<_|Ze~^>X|9|1DWY^#A}s z07*naRO4T?|Ne%bZ8z=O)PCr1e_uL)OUXAI8YnNm4bBYcGtVC8d*tUhFKa+E)2IndNN)SJ53^C)^>!anMv@OR*o}}%ucX{j1E$zY2e4eb*8T1PetR$Ov zatvEw4jyD%9kMCz8pz<8m+CZE9<*a3Q<6%~#wb(uP5zWSSI3g!Ok!DP@=<`WEx>G> z(`XO?tZ~v)lL@2D*e(z2 z-6&XT@|*+houXTN7T>h_+62zr14>DeE*wjD_vD*)Ys@RIhjvj5N zsi&)18L$bQetBZ=-aT37uT0;1>n-3~9bPJ{@OYjI!h<`?AarHj)BU-2-uQ& z*4!YgD*bt9jS)`ko~wz{fP_TFT4#~hU%f9}hibdv@sdx%0#~ZaOGdgTpyOZUEzML8 zh0_xnckI}icZDx?Ps0ZVT6^sgMv}U}Tu6RKA~V()!!8kCiQ=4KsmOWuU0dNaG-f=U z1sEo@BPCB9!FC_)1cH8sS#&F&o&Ad_zRdhf9_eG;!0RXq6`1~l;@9K3?AwZM2Tr34 z6;q9@?+SkXqhP=dOe?w-tHva~JNht#W0lB>=~=9kHVAz@p>0*$|3M56KL-F7qonIrqty_)(y*E zqs!688pSoC@Fd1xIU7ZB*hrK@mNtJydyNRom!jXB;g*$x;ClvEj1Lt5;z^u-NR_Zu zz^>GAB-Ool8owIbiO*GquDnN9B~2Rq;~v)^L|Yz(XGj}*@mDsT>D$46%rl(8dUoz? zaKxB59f^|%4NYF>88}mZ)0s6K8tgQ<7tlI&mOXis3=&AoG#&gg>YhO4ha@ROffp?L z;ps2o6|ZAQe5B`~Th@aqlKA=WixSXcVez#TZeV*fhCr0D~%lhjn;_BgL z@XrA>J0<2pV@$c07dEtx-urGN?-I{C?9rHo!+Y^wKO8V4i}hkAAVc>@`gC(sRo@ZZSj}V;$Nz&?s+d7W($Nxrl03?%d1v`=(+fTz8&cFiW1#-D2+e&9px>3KQ>%U04hV&Gp|iEO#;fI)J8 z#ephQ+hW`M31+(%iotx)E>5sAaQbw+_uiMY^m|V_0~2)cW-;O~vsZuZ3gWQ8^!!mL z4=}9RR&#kJgwq3+S4-#^LnJhEK}gl(WD3~Y9Hg->(rKB1Ha5_~Ps-6wp}mfw?F+w? zqRdHYv>YwXWz0U8rB!;bm(LQ*T_Wq?7%K~CZs3I+^BsM%q*f5= zvzi%EzZ<`lKI}4Wm`hk8AoZK}OF6LMz>%lhEic>7r}F+*;}hh`)7`i4Y?t{-8_fgh znXzX-@VFf^+L8HlXEPJIcEeh>PM%|VH60*k^}oorhHYEcwb$JHDmw2BI?yR{vSI_X zk!kmUw|O&X7BFDs+@*somuBgtFL6Kk#r8wr_jlSxY#y@IUjDM(@S+YA9Ha9huD87H zt?lMJUd?JfzbG=9{1b)DlpJd>s?*gs@}}gyR=fy{BH|)%)i;z4ahyO>Z&!TYsdqGs zfK(=Yw|tkjv!{-<8?I-o!**sfwfvaIUpvX5);E4*J9h!TYj0qmUuMt$41)_7smJO} ztU%y+P_+1{8Sq28tWVm)>OJ>iJ899|CHZc>apg*nV{>L(;R=aq1|m+JI!nh`SdK%i z;In{idthMW_}P=~B)0I}G)pYZh%0EQhuTCi2T>$9+_emKeS4hn<;ya{loR79s~L14 z(DOXRr&E7h$LraeB|q^I1|8AyaVN0YLWGUx=L#LbP#0J>a@PE7$8|e-07V$`nKsz? z@~&vI+@xipJk^K3Q#RB!m+B`b@$C4!%2PYY$-*(W1t2e1SgrDdKlpds-8b{OOxmmE zgjlJrpseKL#$40bopxwU|JHT0f?N~eH>MrkY zx6-C@1=QNL94JnwUz*&;cY%q|)2wEmV3yquzWo{xzq1VGk#H|V^E`F@66XYXz~cn< zWgU8a2-g_uXgD78lCgGWmLTU-OQ=%#_*3 zpFhwxuj8{Xt5Ap5qQNQncGMKQt6AS8^?OgTa5wFr-2I2e{%UZopen20DbI3s{Lfyf^cpN$pW>0uK{EvwX+pD!3^Omd(Sd7v2UEee(g<5u z%8yW5SicY;-QqXg{Mm3_>$<_MzYSV{4^0x1f0b!9C?Pd8!J*J@N@+BX&wmmpf6b?v zt$bXSsf^#X_3GI-nMN^4j5O2*{_d%tdIUWaH-cjXQ3?y*>T((@{v3Z=a%PPT}-i zmv*Myg(NN20Jt37QR1yzw`TUiM#hou@MxgR_)?SfBN)PwHA7r8(&LXRK*dQw!YWE1 z>=I`3A2_@%%CPiV{u3Bx3Z9pS zu_&JO6LEnIC9mikc`iH*s7yh+5Kr7V0VQSLy03TTvUHkdQlCLxx6aR*u{V?%ag8rK z1AR4+OjV}F;k_tq$DA3qp2JiicKWJ}#F46)OVD3^8KQU37~UZldcm8SAL7`)Zr`>& z_w%$%TQ+aT$ee5Er;gD{8*lIbo!@P*y628|%ii5pmP6r*Usoo&Zw`nT(wO4VJO^#( z=NO=+fAe(v1i_8U(eYUkH(Vt{(0O`oFbcuYBIFM7b$AV2a@ z-k(6no@Y=SMpc+ZP!DgMm}}2{>CyJT{oGHsTXyf2u+(MSa}C~$m-x*xcy~p^ zm=4NCW}E>SeQT$s*9Wue&k|OrsHcJs@|B+G86)`2-Fl;8!L{7z!PhP)h8G-t=gIRp z=L>k=&st_=c}SmaoB@UjJ~1}K0L#*4q~$#}3)SDcCH~uQzoWh3bu;Y)zxNqd99U=N zS8Lz&P4~AwH{agg_dD-Lca62{cV16N@=AOD*=O7H&pk`6ywtwwTi!wuV1v+U55JMO zOSETpGV+Nm%5QRVO+EwY*#I-F0{Gm+&x7w(ZN;i3ZP)G_+6_0|*q(mo8HCl&WNT;6 zouSOI-+0!Xx$EA$+h;%jS?Idl-tdjDW8$K5hR#J+3>;#hV@cbwYp2?b<-@1i=RW^X zJAQ(#0eq^^&Wdc+CaSi#R(r%YLw0*xZpX!eC*xEx$Q2UuQXN!)>qB1bAUepcen+w* z%VP}Y__dieeC}=4YF0qdXhTq~Z*T`@ z&bc7Hu!9#myj$NgSw|wvsPa=VEIZQ;xeeN$j|&W%%pikv=m!UePH+GwU2g`{po!lG z1_?KDkf0r8KGmN3Xq{X(HrIab|M}In`G@~z+sfzSX0YR2vM!bj=#q<<7?5*926;a> zb(lfRS$?d>LobcHv;-;4%3THyvR!6as_wyd(GLt(X=CZ~xotRe;`lMX4sfzvxNaI- zkp3Hb-TsaT*(n;mTr3M$U0&wA2?ukO#o{@ge+Dk6?F%q)^T?M@0`o`)gB{p%(BM1+ zYo=etDog8r>`UHl7o1!$?|lWLtBvfeyE59Z@^}cUU*7QN!F)3eBClkb{=R+BF__@F z13Jt4>)XAsSM_I|UkYf66@pRgxs&Xj;nN;28C#0Px}5E5mRqazS@6{-b#0N~h-6^* z(2?I)dsqPb)ndJLSkjjQb972N?cn>9yitdAP<8@Rd4_cIsx7E;w(*Y=LOEz4s&HK5 zu2OR}iD1@(OQUS`BG^{+TkW?5dWfhX6fn{8I zmv(7O22!!SNVcvT@(N2{1pOi|Vfb6oFH1MdLmE_komb{v7iCZn1N?Z8E>fQ0(Z&1? z1QBFtr>lIus!;20GE^zFMl+h66jc9nMYyw#rJ?T}^^aO{&09gceQ7mB@BD@;0 zO@CC$Gh67GOb~vH&YK*)sq_cssECnS_<7+%GhMgIB8(!p4 za=YB-8>OVU_14=mvU(DQKE|O&(x(gw#|F@|0m{fgc7Y>~o(EoD;0)6lH-ktpF@^{J zE8V9>!|dlty76yx@nukmyScETsq`g7dMYO>{G-Q?wfi{u=;m8)ZomD$-)%STzR^r& zKw?yvh^s3WR~?Q={KbG9ZbGh?x)<+EGt^5%#ZPekEZ^aoyRPTC-s)Hw2 zXQD(HB@r(sS&)qkC__8)Uh#d0X5p3LQO1<%6GT`&J1EFZ6ZPMNY}7-3>(vI>yxF)a zGnVZVjZK~}Gkej?zw^O^n(`F`@QGO+5+hF9x=R2r-iMBWG?p9g`Y&?fN8;emOL)lR zJatL+ROwAqc_k!t8?We)?R>2CotLJU zEUQ53T`@bb77WD>qhmDzzvO3;-{7%8`=YSLag~t~U5nzp#N*DyYjcxa;tJnM-(gZ!5bsQL{fv!9XPXpVwZUwW@7x{FXFihu9*&e|Z zwm%)n!jBM%_u$`ow79H$KJ-gc%GF0@{0d8|&+ruz2mBn2KXv+KyJz`bu)%M>uV@GN zKaY*VsuY&4Q;=DPUPKfu>t}Q+uX$d?Flr4m+AO1{o9AGKONf_XFl(eQ#V%l8i!_{K zzj{;KwR5r^TRO?i@C38g_4&Uni)L2cGY2~DXl9{C9Tew_@6x*hOxLmW+=bwZg5iEz z%O$@{S)OkbyOQP1C-}CzE45e98C!v2zhuz86W9&o7{$foF4w?UADMTU=1Q%?5A+mG z@j<@kDMWeU$Nxg;D25Ls=URjMl$(baE^Ch;KFbUu20sa1>9CSchuK$u#YvAx9{o~#&u{!XpR(K9 zUh{_gk%5{7v8{0X^Qske)w*q}3W!52u6fhK})xwqrA=%B#mI@6&v`@xveec>4m& z@E?8bc|P&T3R!sJN~%d#iOjLWXO^F`GKSkX*A3Mz1boGQz+unLrP8vBWf0hnD<1zBpEjbP%s!<#mawSC$*<%2~ zL0@e=2ih`;10QBsJt&{oGBZC1KjgJeE?OVpYzAjbrfg@{G0-rPc1Mz?&rP*Az4h(w zCw}rL+pF$-HSKtS%NV587oh*%wwiznw#4t;uVO2(b z;WKI2JyhJPK-J(@LpuOBT=?9@xmY<`>CM+_3=DCP!>jI$nJeg>L80o$c^pMpqfI8R0e{*%*jWf$Jp>+8~=DL?&tuAN4C<)Jkh?0^TVcmM57QE4(t`}h-&$JpAy zXH+!q{7OYuOmxB|wm*kB-e1%W1vTJ^5zy(!PaZ2XkXZZ>F75@;g0BKh6I+5vRVqUo zrpQ1N@3Ucrp$~Kr5@OIf%9*QnF17Z5x*ea>|D@(#OFAfsg*iAA>D6cOP zzv!#5qM->_R|lD>UxTcoh!xAAgyl5HEk~EuxM1k$BP?xdnNDHrx6^U%@h@3No5A{AEg7&5)4|w96!!!+stC0<-5o$F(|ikh?@6{cCtz5FZhXDd@AUn z13!yK-XQS}TaEbLicLzZuiXbl803FL`r!IN=GjND**Uh@_R)}e4VkcO2V~1#NZo2K=xwWms za6dNVKHCdzHG`;j>>&(Xv_Czwa$0-{zB%*faEy9Z-Jii&X~uyv?yHMm#T}vwJ+R;e zJf3UE;lCXib%vkd+jad8PPS(zne9_9t#>*7)VUdEypOh>8~Hx>^T*qVKk^BNGA^}E z>>qa~e5}1Py!it<`yME^lGDoV;Ou1?{kMMGTiYAo_*!6%xAn{d9zD+tH7DoK&(FZ8 zHEdz0^Gchj4eDNL%g<%<%h>{O>NuYTq+{!+>OS#_kGJpm_BXYAI8cwFknrW{eFxej zgl*frmGWdjhXQ!wsb|_39{xgm{P8C^H|Obg*UN9=bHOifKmCt?s;y;!Yt})Fah5(a zfZ?)YhF6(EhX$A!epAkJ%r?T-*h9~(3;DxOp07hr-MZ?FHcsiI>S!uCwRhV#9b3z~ zMT70Yg@BPViD;Q2rouZw$!;Eaeo1^f#(@~QJ;)MVP zd$k#L)kyfOvL#dmb|g zK)5*O&>tPYxVkgFTYqAEQqFd8ouT$;*kZk5n6P3?h=mub6CGG^kVW5hy?u7jOI?-E zv~iba?JM~q&HZOG+r>p>1&*b$oRts`t_eq*%b!G8OQgpo_2w4 z{b%3yM$T<`XWPknjFCOc%JN>bnyn#o<19aCw%z5=@Z8eT{(kwbyW8}cqwU~Vp5)+C zK0C=@WeL6x9eK|cx!_qRglU_H7cf+r^4%>BYnTXF$6of7g<~X_&<>&;@7mylr99(rO78xus;MLR`~k&KD&~U z_6VbS%7fKOKNX-$&{)!xbc`TlXjdns6i}sGP$Vih4}wr(6kIGiV#%f0j8te7uAb~wIEljYGn_Kr9@o8-)CIs~LQ zT&1WBK2e60p^OM~6-;@Gs2*W2{``QU0@Uafjx+N%%zoR`&Yg-_nX~>$buS0=;_|2i z2cD-)UDm}iCk%DGLzDE0)A9~wQPw=-!UyR9UJcgyT&}#SxO7DsO)3N4Y2iC1B#` zyMvHe)uAH>T;!ne319j&aH?Fu2`W*Fn(Oe>Pv7!c>>tng%Q^F4D1Q|_Z!uVgklcni z3wXNkC{c(IXUc4VTb@I~4DhN9NH+kJm!Xw>h4&qFWvJlsTsbRP@=%XxSp+6!XoY++ zXOcx^CQ1Q&p}&Da(G%n)Nk*3!gEyp$jEo{){a{!h2wezyDPRM@MT7@7e25;w2-N7) zFrTKqU$dq@qi8CP&so|`lP;liQmwuDq3*)BGK_oviUsm7x@q8Hm$S$-DGiT|fFB5v zVR5NrrEApjAeMSe89sM@iu_`8fHT{Xpk)@_Vw>#XqQ&bk6ad6}KTr|>d`=74^CF-= zNQ<4#IrP^>maIB{Fvg6RFdP)4J3$|a&c~(m%(Tz8U2IV}cJ4e+Bxb3z9sYTK_Se#J zf>wD_9eND!7|Z&h6J#D$!$T@(=bdHr)PG|q1vOR?xBE-j06dnKnkg zSJHXA!rs})sq~vJ@KqqT1N@OzO#ZU>8R)Luk)hTJxslFFo(ppTjV=YZzgGPnaB)kW zaJ2wub$scuC)=HSHZy3r1Y`Ua?VI->ZvXbZAK~PC_NudF|LMa=+yDJ<{!RPDP21W- zpMRu1bCA^)tJn{J{%rf-`Cj~)Q-@fob-Mlbhd;|{<&$mS(PM4x%Kx){|Mz@XyKd74 zIt`PQ1D#V25q$F51MPVZhdX$TCB;ivZcisyO}vT%o20#%=iof0X&r-6XHEn`0mQ`1%zLF32t0>pY}9qsw_u zXB62~re|jutY(?BG9Qj|vEE&D@Ed(>-BVs1xF6JW28}$u-A?@^0~m*n9cg#%U4x#- z=461ub1qySZ72SLhaP9Iz*%}+tN5P$`F7rIB8NDs-(?jp{csB{u+}c;U_JO&^;6o5 z9_`DsuT79`xAJ2CtSiRpHh|}~C`Lrf#WM+(LC-ScJ5W`JF9HL;0nk{W5>8+K zUIRdSYtw`t?!EoAGF;(|4XP(?9D|4GAO|wisDM~*r;UYwBu3^5!e5@wGg)_u6&=-{ ziokS+kq7zhJ$Wg=oDo7C%c%ws%qO}*+q`lZ`gq}uvSyp0`pG!3D70w%h)+}-^65GU zTv#zd`+RZsQk(MpEh5XWCQI6lFS`vJiB&x?fS)TPTQcPB{Ig$}kAN0wy& zz52=(GM+V%b3}lN7jUS@Gbb`A_{KMWd%KU>`Hh^P;&OiLKpjXfPkRXf_UqVv?K}3C zCXL(N^tpD9Z`dAr{IPZu-xin|>mn+nMsDMUhwUb#-d z=$+?!jbFbQOPI@0=yoFIP0@sc+OQ!@%@49t!~Dn(VcXG=0)Rg(n`8jPk7U=8Lo2IvbP9jb&JhGO`ysXhh^Y zeD>2Zn>gWAJmNoo?07zDnD0r4R1Z+8J?+YnbUD}%zwTCMTq&i0h)REj8sRu8xU1aRl@NOrI=z8`_Zpf}d#%zX^QLHP4}wH1bQHDlg(z7V%8^syZyM zO2CyzS9b^~d<1C*2h4X7kay`6Z)QbI9K@lXm%4jhptW!aQ<^Kzz^BCHIq8ZY9Y#na zO*z{J9oN7Zp5y0b0d8Td@X_<=0e?YgAo}azNiTg}&N`0J3qF$@7QS$|{Fbn?LAonX z;=9(7N(A{Ak@*|q^!uVD$!h4yWg$c`{cZHnJ%&5};o+dut_ckd!zDq%wE*=6(HCJ1 zTtqKOSL-bFi53 zgspSwvz-swqv`3Y759gaW4|1K@+nRnKgOp^*^`X1?Ed6s>{VXNZ0JQ!dcQKm66niQ zZH!Jm$3wBb1w&Q1=v&KYZWwTLsXdq~m(fMGlOiQA;7`%8%F$1&5sf9Rc!AOxH55G^ zRR%NhbkOe3TW)4{drdq1xrf^t=Jnkd?chpu3tK{Ft@d>TED8j z^RK>*rL%X|UUv@1o1r7SWS;Gt987l$9hWO?35)U10fBQfEG>qo>uy}ve)>o5gg5Tr zx8r=K{lP~*!o6F>&#y<5TUMdS6@1QWJ)gG|CU1QsmcFna=RrxpdIjLzpklPGJK~w2d4D zxQuUu(~WA&Ihp?TZ@9nx;_jD`*Q0cxw9i~7k3B~ltw>6vFrBP%rKl&FOREE7%7OA@ zTPv-$?-${>vZB4TCx{Dg4Zj^q1{2OS);w-IXt?cf{AF{*ormjTiYt zIw#1aO&N8Gcj2*3W561J56iPN=wW@!on2P$@z+@&9DtZW|0u%JBE7;a{<%+FTU~wO zKt;h%VlIaDJY9g-sSoA_7~F8|5vSdhChJI6Qb;->)T%tVePV(#DxKrW_0^BKK*!s2 zwQP5_@;&@;_om7A!H;~jJ^si;?ai;hyWP5HSG#HNP3;q({&f4JN1tWo$p#K1ypX}W zqYPlZ<(uzoH}Boe;fUky`DfG_AcwDW9E6*%3`i$~J8m73FP58xn?;jw#M%p2*oFSx}iC(5Y&^T!LcGDtv&Up`rOe)+%zp5pH+Cgt00 zpqJNBCn>jl_L7dhpFLcO9$LF*J?+b>_OiWu+K>MDKWKaQ>;YHR0rQc;NI5ONgqVk~ zcUQf^uTd@)YHRH!l@Sfjx@9Zcg=d~=$5*d!*D*>vW5c+dWpET2tD#UcR=N^;)0G=N zbdNv3yZH%WW9cXQsel_kk1Qd-1j}=I8g0%u#5jk20N?oONbxL=f`fv~h$*L4t8`gXHmoO`1RrcKRONCV_nvi@6%YEa{&`&Ztts$===ZuK6 z!66meh3QPA*rNP`HNlJUFQ%iOqijO!Kx}_bD*OhQJoT3s+=omqL?=e&E%_%nLBJlt zktsOQ4WZ$M@kJd2r^DmjM%K=!BAv1?h$fCpo&hEw9RN|OyHr#KnsOzql%mlKuvfXS zGSsCEs4kgx1CIRExK_S8-A47<)9q*Y9LWra)Y+-FEQ}{EagK2suJJ4{mqZneq0?8` z2oKiaHQ&Z@IaS49X#Ddzr7%X^rQtQ2bk-I3#);pPOS23OSe|Yw9P32UfhTdrsiHTp z){E*$Nr+6YaQP&^O;`1ZuorQ{(0R*qfR~3M)!#~BMM`*2<6V4}pYYyr({cCFU#|}d z2&hUwM2&agSf<9O?pS7#5$-zUS`L3OYKod#mUw*WCg5SO1c`^$G@ zDLZFMl{-53KB0uB>PG~jYVU7(e_`TCHO(*t5zNUb`VgAGG6)d^DeCZ60Tn#uPeu1gX zX7$+sJ#{KrfNxsy1~nJpbvhDVT85b+->p*vIVn%|p2lUhm#!+~JL%|~8FbBxoLh4` zVEpXTs$oee5W%ClgwaYoKfyE>9O!k%xtt+i>eTI-Q*@sHu&uek_O=xmwdmj(1~OLi zS+nKjacb&ByFAVu{gn&t?weQ^`~0c)`R9+dC7eb+tDK+%o;bX}{mplNOB=&DUkWYbEN^$e?#dN>`Ux1)&IOQ` zow}7rXb`&t!B^P-?J{;}XqR#j*Gg6hIw-T8!|hxyFaER-(N`3X&YN)htrtLi2xMg@ zYTCkS8#Z0vj-ENxe&lEVdHY}g=})vf_H4zzS=sKneXrJ^ldJ*fvpBFb$8Zikp>##%j_ zL&)sp+1aIx?R1%zQm8**!#X-R%%a10zy9M&Gnspt+1B-Jf!K8W?I3aKcbVa1&M1d( zU?2EpS*TCCvpvyPy37^~TJ_M<>zMe{Aq(|Ajj;HK&vw4jUINcFe!^|tx)s=zt72>0 z;hkg2w3dp4?W_1q;xblsjOWliI=&1%In!;sYu)YbKvsu9lQ_z@DL$soLa*{`wtVla zapaPD)K8}!daX;FXWorxpmE7#l@X8e(y#D&Qon-@u6k7-9dt@E=&Cf8Z}oAtH--u? z*TglQwvlb1c2LbwBO~BWI?CG4zV@^*)8+!Bw_hDkhzdmWCO*!uLGKvPGD!UR3y*Mq zp&9(fcaZbk^bCVNtf~|@IGM}lN8gFMN)>GTPM&Vx^M*IJcYf!$ww;^HmVVtEU)P>x zwaf23@JY(@7%NAPw(T6Ow*hS6^V&!ZAAYVw>;tIad6*OP>m#=X4a{I{b{vY-Pnif=-;S2&K%~ z#~2linyD;HfzX-a?-I+R6i6$(vyN648&^BR+qP|M*I$2qJ8AyiIYEl-REc(^W^o7;~NJ*1rxR1Ke6iauX36KsOfssO&zV0MRgmGdYp5t$J zp(A;gYMv1sKdlVz)o2bFVD)acuem_-2BXgK7B^TH1#t|A_r6C zVSuH_V%W}FD-+I;+p(2@HkfL{x|e)`j%@0$lVY885Ds1&iY#RxGH7G2Tk3K;X(Zx0 z3{DTYI?LzflmY!Rs*l`hBsiL0vS2=vO+ny`SpV1_y{*$ko-PUVpz@$%R4E#^rK_x7cDEKSA=UsIU8gl6E_08qBdVDdW(Cx(1W z2$uu`Wt7zgy!sW-1*x1{gu;9^}3A(odH~{svGnN-^M#+si|Q@=oWnXL(v6 zOID4SSsVSGjaeWtX;Ria$%zr^33-uA_@Mtl(4r{%^z;K)6RpRTrnupLHLr)TYi`A+ zm!ivZG(p`1KOVl94!7KtnPgYB1o^P}x%4hl5&EQ1rS4v0O9EL$h*5H$RF_Xly2Da$k% zc{iT*yVrT^y*5yE0%7V?+pB^{r?RpZI8aw<8FZ^`SKgIdJDUzJg!92CPGzaup`4Ts zE?46CtPXHhXjaBjhm|?$(%vYV;3sv}_OE8rp%MDTC017u_4X}@hD#sFu+9`;*8MzimSRV2&!^xK|xhHu@?UwJrvgcTF(f@9at-R+y-_AnXSYj%)AZpqsh~eFfB5yt)8&5AyO7}>d%}#-PSTGc<;ThZR^?7?*x$Bk7kg` zWk*)E<0nrc*U-X>FTd^}jnVngC&pYy%AJ!iD=}(b!B7+NlYGs zVJDG@p-sa?MSEFcR|x@I!%F&vrIHnzl_M2(03Emk9{qhZUlnXR^9(HTCQO4IXXjL< z>axZxzXZOc-SqroP#H(1>1bvY@Q_Y_Y3@#imw$jui>~-sczZkohcM|I`M$)%0(^l> zcc2dG>V1fVU*5eK-jgnR?sSDt`OCk&mCn3a{{8_YydAtvH%d!P%iK?iZ0BTNmr?rD z&klD+e1U2DN>^p*v#hg0NN0j@Wy_Ig`H;a9RN(aa3px12xOV7QvGh*)aOTA_?2W82 zA`9lhGF6;#W?z$~=Y%ova1f&2)7k~er^yq-Vt@7uR8 zX>54qSZil4A~R%TMaLIdv*)ALbLiVlsf zJe86$vj$5{-9k*gY6L|eQLxs12iiP<#ZxyWAsU0;OTZ6TAg=l?yG>xM{*ris_f-ZaudvXwm#Ws zWq0c22~H1ZfSrkjjjNf(DVu4CEX-QmpHf&+~ssmW?8O0=WG}&?M|`{@e=mW@h2Z|FT3I9_9_mw zd+7P|?Ied;P0(RfhhK3yz6)>RqZwCzY)LAg=G!-QqCek<{Kzi4eJogQr;Z+JTUN}r z@BYrWx2-FewSz|wxAhq57n!YJzhPZ?qXAuABw@&{au|fT`o(sN$q=?UETz4eX36*34cqBhUT#1A-~K}TYj3%q z{o8iNn2=b#BAv%8er_PtR{pCUat7IxxN9p1Y8Ac#lN0xrFn}%f^M3c6pR_X?LoTsD zxn=;$cEwpxt|hNb5~_JvEqs*{`1?iWeck~;4ZVN9x|uBW;uARvKe>)105J- zm2zx5RfoK`17nAi?rh3b#HBxgKMedCS4UPtSGcEN5AczYam!x964Shf3f>JbSDfb! zc?yYjOAO;1E?bt9&oi{uA9&yc?XzsxSZ5Ln`~pki&oeRPfyc|2R=Z#H+9@aJ$~Zr5 zIBft2vTd75J~+SHB$m`vZal-A{3&GooPyTgzNl-$Q>AJ1sptb`I+Txaxu(i9S&P%tA%&YCAe#TLE zRG1}3$^3uhz3H#!$93mdx9`@s_l@06HaAJ67SgmNTb6BVY>&qS!}cKa#+gAp0rD!q zU=rj_fV>C-43GfHyC8o+g2c$=MUYH_WSm*NjWyP2Y>ARcaVI4%%_iCVzIWeyJD<<@ zR6WmgZ#OAQGH5`md!OG@b?Tf`r%s*P>&F0D;w7wB!5Jq54eBZI(wCD(&KB6l09@L> zbYz7SmxJmzIT3#Uef!&Kw)NbyeU3jH1KJ|1S*WGk14j;%FSM~qFT9M|H<7KCU3ac5(XVU*a!QH`1jbma zl)Y%Jc}Lo{AFJSYC9{K!>zwPbZ=c(D7dhaRb4wUNw4S(0|B#P0v}+6wX95&ixlP0+ z{QQF(nqEgl!gM!i>{+imG?1hNp%39r*8I5d=p+|?p{d4cj;yL(f|tRKT!s6%2|BXST_qh-gvxayAh zte{iT@$8)F5Y-SrXd+)}h*Me1i}!kvF+;iOrz^0je8M^Hi}?mH0-p8{p1ib5fIhG1&o zn_wrjdi;u&nzMX>uXIcSW-$+$E4Y%uZ0JCt&ThnMnkz%JZOU7na63?~Iunb_TX)fM z)~5MwWy9?pGB=nqufdFz0Ztx)W2A>i!lo{1(1YK|Z(-%Rbf@ZEOPCo_<-;e#S?yaszqJGxxkO&@D}mrG!IT`u$2)=6SsnuT_~$;$xjft2 z9tJpWQIEL7(nANS@QGh?l|zk;cBb5T=;6p{3!QuO&u_Rp&3^SJ2jcBI$al7HwSWBk zf6{LJ>Dzp3mGgi2TwD(E(5L_aKmbWZK~xnq?k-zT8AkBd3aomxkF|u~HuPwjRgTmy zbiU!5Q|)h%Ub{W>tcy)=z59 z5}l5%_`4_h(+?eJzy3FWjZ?Poi!42iE~^f;b;=PMLs#9?PmLM^3!ds$5Ki zG~gW^(#_xwLCF$D8F}UkyxHN>Y}(*RQ_*T6^ZXH`~JxKGHt*sn3C?wz@eOVO!Mt-BmEw%dWt&UErX{Je^Z# zdWE?`{lDf)7I-!tcCfG8CP2m>?B|4%e@@U|6OWlg0p6gJXEq-fQR6CW*{tSleXV$b8e*)Nj~5+rY6);ge_L>4HnQow+F{DN177o-;~@Z200zz|t9IgV zT;L02tjKi5fYk4hhN_xfcJIO4x7v5;)aU#0(7()ADm+Zjj1T zRF6$S>@07koh1`q6ir=-XL(Dxz)v{y!|YS{a#Fp%;LJhd$ayrhCjgsz8HXzse8NNT+cS^^{B7^4` zaao}7-=R^@ur|hlgDp5o_QZEzY^yBAf8+~aW=5C8JkU-v6d)reb27R|PH9l?&Z*h# zB=|>kQGyL|3$K-_>a5FE&BR&g(;1=Ax)j;HDKWO)=$dvxW3)9kiB|@Ekxy4xpzXlv z?|`R$h@kFwqHQ8ZJnD$q*f4TZhj48uzW>6M?$nK#O=5`6QBebuKeF z=vq!-jqueC8x9y__FYQbN=&D|8BcoiG_dT@SDNqCfXnt2P@NK9$l~W?fXZ(K1_u97_R`ZeSefNX1p14{wB$K2c;G+9 zAurM)P&k7JLcRD?Og6s5e*g+bIMb(G4NJ7pC_F%g_MmSuv{RjY6b>hT@%WcUKRlGY z3;`(r;^Pmvp|5^#UVP%VtlQ8K_ksNf=-4017ZAi_gHM}~nG5KtujVzQgqf8|T1nHW zu)`a04%noVAuMh5A#=Nnkp|lj}q=~>Tj4SmLVQ_ z6>qt5@2|N{am@P8J_iCmW@S1XKKmTH!$Se-`aOD5J{zu`TLI%gdG}S@U}H{cfX4wu zXY;iEHr^cAb=jnKlYZJeoxEn12x+(MXD@roh!&viLGrkZL>Z~uL;o^>LcUqPl%TVT z))&^3x{|kaik47zb_HKyW~gyMn%|wjarpxKzE8FT%#LkmM)~H&bA+=Ji4Mh1I>sx@ z+uJhf*oCd%!SvA`W{(zG3c8!}u|!#!rwm1(;N1?o;Y)M^*ZFMQ=Rf;7_AhU5M~|Or z@4WWi_NlM@di$-Xf42S8uYa3%&^7GxUOGcEt86HrZf&5G9W84b8~x`q2+Lk?(rYI$)~4GtIh9xMU=CW}bvsvd9W2U|u|aseSYJ|KIk&{@raCs}@o} z0j{R!2dsb6U1TMJGv#aWmrrexURM^lRn1O#Im@Sv`6KNlN}KE5^5P7&{=vyT4p4HA zt{lF|%MMW0(bfJ4SU{0<5=|`amU$x&{z!}RH;)k=GOS6Zpa05lq2ru$Wt)I}^(+Na zPk42h?L4KdAudy`Tyl1Suh1%b5YMw@9q6sPPTe!D%1pS_GZ6Rvo=*Q>hgg1x9UFV- zt1Kf&Z|r#JRSg{?Q-)n{T(rANptQ7k}=lwtL%Bd+ZZOat6ei zi&xs~ufN4)*@+xPe2u;Ich+vUfA<&PXrFxa;kI`d?LG$iUVry!d-au<+Sk7JZ}Q2{ zPdxHyyL9mq1N+x$%dvV&p5fJW!KT?Ay@eg#m1XHu@-B%lofb5}K*U=QBlUbQM1rWl z>SO7-hj+W3b0vdM^BjuD*COEa+}YFZi6@?DkAM2p_1QXX&51MT+SOBM38!y?yn4>& z9_k_N6At<*4)yj^as4am*jHA5xcG$ehq5sGQOtiE8-qvp{P!G&-`C0)i0|CUv@kP&WL<@D*zyu~7M|4*e?W2m--7E|&;i$FNy} zxa>+Jqy*zkpAX#A5aU1%jomP?4!GpKciysuh8XTMwc;?$Wr`-uK?(OaNmu{+cJ^Af z7OdJJBHZ-l81PE*2PAKXf-&-iL#R_pS z;606%R^oO%R+74U2TJ3>zm=aIUT2l0Z-rzKfccI1cC^(QiB%<^mwGPmgyqqwRQmjr z?rEi!js0+lobA^|1}>L&>VrE_?zjY79p4uSXA}3c#H~hB4>7)v+=sj>gDd?r7>%4rNq-7OrLC?Ns;mVw z_N)_TvwRFMnvxGhhfy9?)@O0t^SR4Nfw=-r%?lmN6D+LIa9gG>xyp=?{@Ykuxr2`8 zRT`4kGj7`oWo$^c;gH`R*runbX#;ZC9>|kimQ2kjpB1rm?0}f+q{A=*a`HR*n$J-Y zYP~P)vL8xkR(*~R*djXX67ePO53>w(g}bKj$}MasdcB9)<3$bu+(xH+1)M8<=4p}7 zmMu^wwo)f;1K62*w-53f`pO`KVlaQ{-08Oe#slqVp7>n5aOK%{^8Dp?`g`ANkA3-X zwEy(?{!aUYZ#>)n=RbMAefrQ5nnxZaOufsg@GzUU#VrOMZm-fQXNh_a!$-!qnH<>0 zvi0pGd4Z1i4QA?p<5z#K{lXKEwJS&8Z11v9cR#%iJNwJbOj`%XrqlUNhtuS{?B5PB z_)Df`&mDMn8L*w0ZQuu#&Iz)z^W>X#mu-~fh1yA)1ycM8?~lF?hm0(5V+AACJTj*} zXj*K1F~)Np@|UiXAJl=Y34l)`n-|s(B8T1_X>xzJGsLbyTV_CDfevXpR#vReBP(cYXQeM~KUwMWbf2x?y$d_OULh^tt;cl(t(gy~a+2J&Q6E~_|X%arRM`JUKvzU+UD&GyoCLxP4 zh@lT2$!8x$?`j8C?Hb#49B8s=P>6$VA!E+g&zOh_P|a+3 zV|>!3`0=iCZ*{p77WvMVOYNO+{6#y$NbK&8XlbunS7|W?$Uaf%wq<99mq%|NK8I6JA;;Wgw;=H(1PQV*SqsCtuAi0B# zMymU9%d>RS`O{-K3n_REQ;zdnw=uiQfp#>oY*^jO=%fgPB!$jSx!)r8@I5g(o4bo8 zLT?{ETJlg97=EMJ`Am9vahbIv&W@a3r4zTC<%||w_f~qypl1?jSRFaG^KTw&U^VjY z#k50VCvySAqfyDAi5*Cub65zxnDG#DihUX+B4C726NT*k69X?!aKJ^U`Q zjg5qv*|^{lA5nuhhPvPr4q`9_Hk^nne%xZnf;xTy@&b5Z^K3ry-gQAb%4qCUQyzX= z$co{_@l)hcHMj<@R7~({Jk#PI#Uy-7qj=&SMKer5g5z?yAYRf-e1UC>sUOBE@FAT77&t~UEIT5WzAk!8I^T{1LNoZ)KGjYfXd^K}4 z*WQ2scm@`2Brk6FJKuh5{1%;d8~=1*=zQ78y28FY%eXpXhu-w3Q3fvU)}%9zFk)x$ zuQFBT!aTBw_~syvuF|Ni%rj)$2VjIvl5-KVcpe#QcoH?jyUc`~bpvnwx(tkxNBC5u z(|Z%3_!2lx&%5hvmLr5uFgVrZ}S~on1GX+Gr&a?|E&pH&*L3miI^!RW}|?{zbEO&+<;4V9$I1~-{egNtRW!z_7_ zvI(!_ZkcrHXgXi1zlHG~8^Q`Bay7V|U332P4)^WYTKa759N+j}I>-KQX6dh^?}v^Y zXYki*IAD30M*;?zu#_LIp40b-1hR-Q|-b1d)nt&-hb@H=i8fK`&zr7 z)9)8nJ+yWieP%|I!HDQgUjyLsdh5i=fQfQ}W%Wg!w&84|(*DAC3-z&i6qylkq*r*I z*WZY)32Z!Yt`Z{`>yUo(81KM{BbJ@^1<|PoZeX2OuTbiPxjq|IB} zdFUXcOExYc$}@chjEDt2u!+z6!z{&Lp&e>{B;U60JOr~=3W!^}$PL{7<={VziW5pY zu%(Tu{m@2c)O$T})?Xf|8EgrxWO>M-a5}wp)|a;J9b|A;dO7W1K7*O| zF_T@${03W;LJzo|w6)JN=x0H(d?8qLpOfq9XShP*=FLkCY^}Hd_CNoJ?N@*4i*04W zb}_oSxYG60jUdg#F6|V z?r2Bl>l@_l0Y1IxK<_^K3aiZ4pJ!$7K05fj_v|Kb7Ta6&IbM9}<#v|O-+3;OUkXz< zmzeOne96IK@)!q+sqp2+G9L~rUxfKdb{}KMek#To>?ngOPzBBJh&t1;!r^%*&%W1Q z|K``)XIJRlKThZV&JIR}IrNQvQf8P9LkkYzU6oKE^UVy*PycvKiH@hCbH1ZkY=Mi3 zloNv-5%X`34*a}EfDX*%%Y0Uj5&7MW2+}K!!7y%7cPUcs@3502eU;W(FB`-*eC@c5 z(Wqm`-c3{$+Cm`~XHbQUBd*WY*^(2e;1}L_7PpnH9V-otu&I>sONYA4Q(VGIY#KMd zp{r-oOn7E-Nw4^}*fPPTco5x2k$B|Q8CE;>cDm)k+2j~=jFJXRp6$$gAKMY^7=#vR z#bvrJ#2O4c_FFMvj+B~z`bRF%ci+9ddlD!&_GmfNPs1<+2+E`Qw7O6igptq5uOw%7 ztE^Q5fBt-jR(B$aOS!j8z`X~FR|CIzo}HVDFl6ksHS9^9j&=$a`IvSjAlMz{HW0x(JA-ElTzs5jY3x*Xi&Weh^u z5Xec=gq!AaC9`gr@G9PWU|5Ka5~o3to}tB*SZZ)1PZeFj?z$u=jOTrj9ze5q=}2{! z7JMsL%dF{1Iqdnei&=cXVBw&ow#JUw0_9bB2iWA-nZM+B=PTPd9GoLx*Vr!`2fd-! zLw-pSFQb9fg#mb_PdvgvDtDL*f6)PX4jg`v5KdPyy$+vv=OW!%HwzV+5SYO|?xoi@ z=BjZhY$(=)tW02KP(8MxZ#?r054H;!A}_($Bx<@9oIGPES5#5m~}$DxA+W_F0ui(bOQb)fDKBgJ^+?3{+NAt8F6eQ z@6HebmQU2VMBWCi2lm}rTS^_jM(4oc-m`orYU>g!PRoqn$!;sp4IsK;M8!5I{E zr0?5xAK1uqX3@6L`JY?H7K@hw1c+f2Ng}swRe?40Yzq??`btkM*I#+Aoj!l6{rbQ6_uB9M-QRA1=a(vRSf@MN37 zI*r{q1|=+k+u@Zid;2ec^-FE-#<}+Pv6tEtj~r^(-@n$r_uMn>I0q8Xvp4q+_4NMx zS=LTmzXMOybbixWP;Lm;Kg)n}wJuODmI3o@3+*ne747^M_NCLG!Es5sul4~+C64|< zUk^XT)%a5S0>ra`Q3`tAH++&>3OAfF*IuZ4QF3T9sG}|(^ z>}P^AMlPvLcqw_MTaLQOl70cqr%JhZ@d3+do&AC19PsA^X@CEKi?&r#=5iXWQe~zS0gp_USga=OCSGPI_F}M%G0;?1RUN=e8%1 z@}}{LG8s}@r1tnGv0R+J(#PhbUSpw7uimKSsmv_QGz!k0c(1+i%r_|<%k9g*_P6NQ zQ%DH&BvwJvL7~xmh0d-^nwQz@vXzk}JEUn4(-C%0m7Rd>lU9+7k*T4=cv*?2p$kK` zU*08I9*{D18UdI2%e$X_u#o$GR6Bi+UTHi=2hFs{m?rH5%P5?-f#j!7%+H=XI_<;2 zieDKjB^#;o|z0-jl7C1P@9GOoYKZ_+ADN?3m!&lY-h zVEEaPELoL22E6%SOM=S~S4W5Rp$DQCzrT(d=z1?gb&b5behF8Nq*;jmEG{2A&fuN_ z8}I7ZGO}~!!w&WwU1a%Rwshb>94LZEejJbr-Vx|s-etz$Y+!#L=@Arh1t>Uuj5D1+ zbo~KH{gFr0m%$|~t@u00H@@~v2oxp9rY{HW*E>zaTet58%-|=1B z?$#mq8dABEzO`jm+EA7qu)D%(;pVI5NZa7*B%OzHMK5fODNotqr;ZHXO;b8wq*)v( zdp-RnL*rIj4NJ@vUp!Iyi5$hP6WANDADr?59MG`kQzu)VldJTR`QWKI$oobt6`^Q$ z9y%}KKF|2)zruqOfB*cS&$G{H(_~J7JlNKHeegNn( zbvD{+(4hQg)31;CL%{ow=t^H|HI_47uEuhOhf}aF-?d)Nb|*T>o;FS}dcsORmS{Qv zoB;qlTrwV;LKE`iek>mCpC8{6;P;^ImH`ujBOJ-ChrGHbr zZ-C?$C;xAUmqY6d?d3oFYJ2ooo^F5RH=k|~y>q;M>kt3Def59+U)mRb`)oV%_@~>K zpFGlj_Nl+$F0#!0mDk^B$KO9m; z@@Ie6=B{#@H3!HY{>;Pe{yn?e)%T7wtACZj1jagEHQB|oBejA(^5892OV?_o@4%wUW`Dm8A%ci2k73+%)BDckItjs}!0OsX8d;8z2`tD*cp)onUX7hM<*egoXK3huc?vOb zc(0#f71t;7jl4HZV*dF*&6`kKpwj-md1w@%W&_-tC0RVo+iuYhnVXM7q}z%k{m-uaG8 zI&2$jIAkt35(0=wrcV77zQ7<1Y!_dELPOs0v~81#JYHQr=V|eG@Y6=$b~PQVWt_SG z?BRXw)T!gN2k*3%J#+1)S6^rO{JU(EX?)-PT03_9Y~n@=Sp z?dUu2wpU5tdD_00 z834G&r|!0Kh@R&_Snh43khD5yL*76h?Iyn*Sp8{qe=QyR68jK0SxZJ+*=TUw&+e%5 zKJ@3xg|qF|fBlE;ItSMrdGhmZ;oy;WYl+S-o%;nwj#JK3AXJ`YWmhtvqi!M6^=%L| zMt(LED%-7&t(5H)Is3?{7!~08x8G=g@h|>GTckof{JAHy2hTW^5cp+=+Y?%G9*QAO z4>{YnYflV@jepbS=jL8J^=kH|ddj&YQe%`a29|ij+1LBbk4x1a3B|*yk-EP zcdDG}bV*NjMqw*(@R9_UJdK|jQR3<^OmNU3_vG@-fFt`XYo^gte0N;H`sX@E$H7+Ky$mp)#i@ZEPF}+=cYR%I8EPQ%gj8jigBJCdjuAm< zp4!3GsHr#IJGjI*(vpC2Nn~G?eW-v6WWY~d0ae8`r76A%uM^;k7ygw>WO6UsmiLmS zI#36+s7E%5l^M9j$)(<9spMiL{7#tQ(E3I^~_c8``zE zdyTqb3tPU}LwSe2()s)y9c&J)vtBfxQU{@9;S@Z|x!9BA@m#XozO8TBfzG09=1IBB za%<4Qyh0dwuV&!XWxJe|O&xY~?JCPv8MH>%J%?tAM*lLiUQ7J6tm|wKnBPO*;-8$? zemh11KG3I3)r_FS1J<`TIvMCEP|g>Kx7V^mo&UnW`j_o0->`r5XP#^i|HuD+d;X>G zw}1Hu|D+vy;F0zjmi`}j;Gwqv;NkX_&py!RzwoKH#eKH&tul&?frcw*-ft&Q9&6wK z?zh;l|8m>Eds}`14Be&l3%#AwL zvbjz}I*(i*#(E6@#V0rbB+C!=|HN zDw6&aA{|?i%1hAp%cP^x!6rAtCs6_`&h7{>taOj(yo|spOu~DZaYvlgjZ?6WXM#O| z#+^;$U?#F4aL_I^)3{0})-m}~p*7nKzO)Udu$$xh?*8Q;$_;cRu4?d&v1jcI1y&0D zN`Fj5r9-_kL#j$q7tLbTt6IY^%sH9QM1 zj=~cUJrf5{2EL@NM=spO0q-drQ+VT7!4wpH+;ocNj9ohbQf?a*mO*onvLf4bJ1Z!iA+Z?Vau%EEVAjBEA zA-s3ubiQG~n}Nyb5P0XYVSd@c6%02Sc$jDKHAtZg+x(~#z&q{F7o8BBa8qwT$=APz zj(z2973-1hiSXWJ*g{L5|S@Pka{?xOR@ z%sC@tS$<9?M|mwQU18KBN28-i_*Q|d@XBgB@G2!V8SeqY1{!|M*01r+#8)_Q=A}RU zleUk7cs^tb#_*2D6<8J1yyK@-BDsZ#BrXJaSKtp_%+ZZK<~1Jnq!K-v*-aN{C- zdIsJJpL7n~TkrV;&eqsbzj~EDjC5AFu`fs-?;sO-Gu_)602vLx>*$2bg4abmXs@<04FaJE*NRSEAkG_j&I1wGzT5>a3z8I6ne((`Q!NtSydrT{rMB8 zus#TH$iV6Iz#-JE)8Cn35B!lgmIK`Bmn z_1*NVe+df_#SpDmxUv%d#Hl=TNB1(|q6O#QCbrlkx2aVR*&lqFay2C=VbfCs4wiw+ zb7A|S0#DK_#=~TlStIHh(83e1E-&@ezl0ZL1+`0_GYez5k4Vjpa($3(VP)SzlmTnXHb^}c`vV$jh)IZ9XJf?mKz8*J`ycDK! z1vJ7MWPP9TK+q3z!kXXelQeImPui|U8mZ3KFVlHnr;*9nE_l_W%jg_S$8E^o)}9!@ zmvM+ici_>1l}ZO`Aw&I(egkvq!U*!RKZ2&W}Xd(a-Fh`3NsJfm34aTBohT06T4vC3IMXiprnc{QL@qb?F__I!{F7 z)C}BBRwiz3OWXIgqksI>_U}b)9tCxKi)p^iBGn7kG0 z4?fg(96H#R_>#;bWzD+%3ZJoB<#*-8iFS+ag4=g2w_p0rue1jq*w1Q%xpwONZ?w0c z`F7h0Z@Wk3<-^?{OqPE5GTzHic`M7DgTac15y^BR{an5H9>0!n67W$TVy6qE zNK$?~EBA~JjCnnDIxsRyYgzOPrfN7N5*1%xEq!7;h%L~@mBsJQwhbJcotY8eV!0Wt_L*8GE_yN zg2PsbuM4gtHNKGI!guu zv3mUIa1g-@eB?3FiANdL)@Ub!LtY_d9pvG9odE$0 z4~i$Qk#F99;x8Xl$G!wyg&QMdCyhpq%IgWVi)5B3px^OZ4pgLb%-Ax-&9X5*!-VqP zpfhv%8{cWqzWn`m5B$u}wB;j*(Fm62&$}GlWqhiFi{enm-~hik$wG@iWhKta zzZ6biIwvTqP%h28$+v6Ye(w49-k<+vTRwHBeV%V9u5#E+yGBQ~+X=KNcx|w*?`%~^8fYqtBl0eN%rEkacQGln{}HR69*(55U{bOr^|lkIjt}a zd0@i}xKjwBrNqW8y$xDBWHn<_4J>D0a;84RA|69aCwig6KGT@7RhT;qcSdt)68L)aB2$R)Em> zgJyY}BK@H*4Qd7lUiR_*((~x4OQzK!^K_g$AYuKANARmWI4ebY7!BiiZn&5(;|7|G z?@9(UPbyEvy63}NBh`$up|bB7aG-V3jCv(qZC^6AohOTGD?(_x`+`s5?O z!Hj4O^RI`8LQgZP&1*4F-2UdxeAYj5>;B^LKW^N4nT0WI16+XXQgTWtw5EK4AaSH$ z1Ei#@57M~ZNMSgDMEs)DJWkl0P=li)6F47j z@Fbet@{nL6j&uZfXcz@4D{s@k6G~mebp6MHh3>=Rl6mm@exjsFyKGTrSgmz$t&wv>`gil-8LpK;Z^1E$9t6%{0#G*=y|k$ z@F6Md&qfhK@8IA*>-6ugrxv*3v*|tqTT~72nlp(*h|e>yg>V8eLAn8C);DRGc=R;& z_n;|VjZd%Jr_lW=$djYxK|HM42d6DiQ^u333GTaj-%Ky$HuDWoXLl-pa0ab~Y!)qf zQ@WsJ2^e7_Mjy%?QmSTzCXW+9{LTC1OX{qi1w|}i(QV(=1L6w5?qR^2^dclIr2G#y zh`=*{e(JYgyp}V9zm9i!Zs5;U8BWo$9h1Sq0-U5NcxMt=gBT!AQGj3K&2vcK3WJZ% zq`Rur^S_>Z`8AfUzufNI^9AfkP5jso-?w)={e$i8_?av1^re@nn=hoj;;70zc1?a# z)Of$;DggPS55-A3qy?h(c`&|dlR+!MM6ey4z5w@$%&~EbproWYcr!uC6X=+SB*b`` zyp7GqhSG+Rk3|MgudzK~=dLa77k=q!`VQMT1n*M2&MIl`mHk6){Wexoc@XMl{Lk^# z0JlWJc5J#9%w>niv5~e>ewfzE5pf++6P<(8MPrJD%^~^ z69pjC)h`8)rmD>QX;fdme5t+t=l{CB!*a8SzVwB5_=(T9KqinB1MAKXT-OblRVM@`-kh3U&33H|kRiDEPT^9PmJVJFj-cY(&(j zJjVCK*~2OxU`zS9hi60vJsV+pC(uEHG*Ad1op@&zZH%}qe-Zr7m|wRO4U9N__q)M` z1Fi>d(or)g7RHW`#!g1*2@|LO87k0u*8!uI^m4#qd(F#bpuErIhm!Zm-uJl#nRK{ z1JV8Vyn5so4|%G=nmWHg+1rsyK8c6u;iS+2FYf*#z8P0(4adP7S%E(y3|#SU^88hY z7kvPwdFvpL5MxkCe0JW_84n*le#d3%Wo7uNxnMJP^_CGU{#Ss zo*)V4ANmp;GqL)+H+9i+Ya%@`&Sxvc+t>|>%kN0Rc&ePQw|edf^-678VHGzi(IYgJ z$wqyvB$w_1(@_aG==ePRgXbQXN&KKNE>Vhs_?Smos)?UvexCimK?>?E%nnM{Jh{r} zcq}{SZ4E5J1r@t_<4P+#qBYorUVzJTY==T!kzVNnaWZ;u3P`^);a?lp1)97Cym;^i zTx^+H9shXZZAy}wjRC^w{bRUM_C?`yXwA~D0Qky7(vY&-?VrBNAl&tM!DGM-p7EG` zBp@n6yyQPF4Lm>A9c1c)^_4SD+I=f# z^WSoArmA=9kZDbsvm?OrbqAP~p|FvIHjKDv8oE^tw{%jq6#)Tn^nw|C>b-{^JVL|v z7Tc6W`YL%8{pVe;6lvA5!M&5dBkwfxaU9gP-)>(PE z{L|GNCPmuXVM~y8lCyNQNBe3o>r==9<6)bA%UTK!d#|!&Yd42RT{w5Cz5ajwL3``) z!S?V|pKE)Vz_@?U&h{|N>Z60SaY%gXA(!{wX69~{^j%?q{Ph=3w)4l{Za3I_yN`0a zlaBZ@<;sDGb!d4?f7B#O1|B)Yzl2?_>6`<=9yD+%i9s==Xwpzymo*wwm$ z9sG5Ws806_Z_0!c?R9V$Q1BOvp*9F`-~4V6eng&P=r9lyXWlmCL%~Ou4mMQeww<=$ zjSFYmH;v_D6s6$L-Y@pJCh0K_KSYKhHT|%PiCX)^qK9$1X6SxvQOrf43df zzyhn5n0WJDyX7hR>wMx;yEnhgz@YWGcGzFG;9|3&pYoToRl4MWpTlw5(Mf)rOkL76 z%9W|}m+4c2FoxJwPx$u}df6vW+v45hr}_NnH(4Ehus#0Rr`wT-K9LDRzc!{VK6{=s z173fd0Ue%7fBk zh^bU87%{{)F3AWBlAU{c2*6V*F)Hm6XgizR@xD%{`T9F=wHJ=Q-k$r@eQp0^kGDsk z{Mq)Gp+jMBauWBY3m4kSci(Ae-#FTCzwusMJjNb0 zI-n18Xv5mt4Lv2UJ%g*o@UKp+Rsz^w+rZy?)Ir!+`}Mu~gPccu}6 zM@Ep`6TOpz&)j40!4)oP&5WqBKr59_HC#(Rkpaoqcx#|XN7sgt&W@Wfc0h+@J?L%V za36nW#gL&z%7W*tu6x~c5;?QwzB^DMoG{~{Ay5Cm!>qlHESJoiNWUFxMy10m17WlB z%1&J}(R>3&9&Fg??Bt2p)dM!%JQdVJ>QY}DN)86P1h@|K*hWWCT%@m8N}vmG`i*pk zRefjbB|1j5q%Oy1UOTuU!}D8NGG-Z3U(J`BEEAI_%b708>^e1MR4LfV zM8bMHH-?B~MpjXtdLRBnu3h9Cq7Rr2o*(ieA0v)rrR2L>VP{+)(`i5rE|iqZk3G>= ztC4tY62+?L%D++I8CC4-cZ^FRtGaI@fee9aMM5-fc*Akg2%P*-vFJ8s+ZoPk%}sw4*OG#S%PQ=i)n!VW)m!+kb(-O?n|{J^JY+8O4c*sQ~7il!YGEsP9!~fvd`m# z*Pc#@3?32`c&G}(&-UG=xuy0${dfPk{pv4&hQmEsC3lPE_BTAhmh>|y|Ni@@`5fE@ zR{I=d#-5d)e!Yrvf5UzX>xtaTGiQGWCf8hgkHvE76D9~&4$rnU+?(j3a*kOLRSRI%?gk;HUlFQ1leZT$qJ zH^-i7FaGndwO97;Z@WM9Sew6ZZ`;a=u`9$`U{8i8+^V2{Cg&E*@=dgyAT`PTo_Oli zDR^0LH~k!rsiIMBM<)A-!8OYVM1a6?&l4A)Y&`jsKbPBQaDjYtd2R+7$XCY@WJaf9j+q(L zl}>@6$X;0UK%B}hKi<9TG#DmQ*_g)A?qR}=0hs_Nf<||0jD;T+l+i|~Y2Z&h0z$U{ zlCTLs02r1Ig9+Agw-QnZ9Bgn&zMoIL{w@PVz&Z%yAtb{xajSj+06+jqL_t)AehJH@ z^tAcZ@eRP4yQ~aneEFXB8)1T(-wxCye}El2Aby{xg9|=`2eKpm8hqtC+;~r#!!zlD zaLo*p7wD4%LE)t*A@!io{AO_toIlom%GyK+{DQ;W+}12f&!Acegn06%c)vGQ(N$$= z_`T&{ow6c4~^T0p+J4B~j+EY4ch_R?~up5?hrY*u#r5jjz7HosVfAH1=2kpT{ z(n*};g*vVSXbM+eW7v z4&Hr_-6vnZ{q1MdNw;othFqJaZpnud$sc~o!fwGDg9meNQ$yEXHm{D~@lYpQk+{rs z0kh1OA(z9Vso+Cjl&6BX=9F)4?kIFHVNFtQa|0$T^8mO7J!_Xa1})qtn%OJbMbzN! zHi!4FtkCY^`|}ypAl~X3_S2ub;77R9o*@CU!)$+@9k5Pan(uO3Zr$8Z+hUE?hPO$8 zDN|OS1%LodcAVT+`nv~^B}3~ULLlLCSm7<3RVEXIgiVn+*xOa95dRR@!XhX9ilMr1 zz|r{vSa?Z?&&Y59mYtACc^T{_M&JkBz3)SJ3?24$0@+!Uv9K7ra-!3x^ECuJc~8&} zc_|tdDbzaESv2}r*wlCU=_7CClXa*5|mNRMmgrtEN^&@>VgQbnh5=h=}pX#qHu2Vi*T$BmHa zlXuw+IR3*Wo@{hhLX+2Ye3K5*6X-ubir~~$f`#t?axQ;5b+v$_ui?=!IVql^$kI)e z@_UC>J#NLN8OW*}+TGjsF(1B{h4k1qKp%PFPC5!pb@aZ{R*ZpD%b;50y-e<+6c27GF ztOKbUDOVm~oWj55Um46P*UkqK^x>x)_j>zDy?#s`dxcqsKtbk|V13AxC^T7NMwsnU zb29|a%;;4{rEPS&%-qKQIwRG~W-5xclg{%UPJ}tIyu#r1YPjH;2&&bKr6M~}XpPWojIv)Rv*I#1WN^W*2q>|ozyV8O=3c1EBsvz)}4 zFJ&TbN72*y9E#X2OErkA@T=5ze8-adNx=^n%CwdZ+bFU#pBYd5^!Ly?8$#}ZcTc-~ z*jXxm*tY|WPI_rv1ItiG!tG!tkKi#$CTogK8^6VOY!mp_*_$IyE6Ef#SM<>@+LtHVv+NOce% z_;Xi26H(z)?;AjPDZSGdB0W*+jLx)&Z|>X!g76<$x%t8yOl6{pYY`pvbQ`ObA_ zvuwPJGuVn&kuM%gT2q`q?vr$saT?{6(>;fFr}KLB=sT%oQo)38DRmxv=dDYkKj8!4 zmASL&j8u#~aYF{1?}cw*?eVY^E?;z@#)?w=HBW_Zn2m-CuNhez2dmm@Ak{l@3z#LIc`hb`yEFz5c<=n1ih3-W z%Aa+>a37M)4gymXH+`1gq@5+>o7~8%8n7yQ%2eAq1_Nbm$XR^yrH#1R522m+0#CX&$JBGi)$2yTX|UKoC~OKf zo+k3a?u0Kc4jOsTllIvL}yyu4rg8D$}M5s?%@He4vL!(%3gi*G<)mX%-X}s zdiJ~`cfy7an})Oz%nw7z4`u16@@koX4HCMqvpV>lW3pO%wPJgMyC+b4Sl$xtfF*42 zA`M6nd3EKGcGX3>%iI^yafkY8oAQGm41|sx+i<08AAPTqnk3f#fFbU;I_udLRP8qYB60RFD%om zDFAQ+oS<_VxhT%6Qw%QH@HgsmlAC9n05BQZsck_3cjEE&M{$WtT%-FualuzUL!T2C zz~a|DE?(x=K*MeiyxX2(^!DG{u_s9v)d$ z(;4)$b6`)$XtN)6Y*Sz^PZUiLuM*nD#|obML(2T5a{jzJt7Kk7G{>bIE-&$vEJ%?r<_o z*%(Jr-n7jj&qbK~W+!()9q!(}lfUw`mr9G)3av&{N|BQZW&}T#O3hJuR1HUUmaNSE zEQ2`*jLNmdGCn)%>m0hUh0I*x1lVnK26nKYgn!|%|dQBf{XN0GuiJiDCb7J~!VogH7^ zmcz}?(&4fbdyR(5x$|_s__Jevnh3gHZM0TiQQ#xugE z>cE5H&g!qzd9!ev&Wj9ocp|2&5?pqpq3|zxPCWnA3u%?ptSGGf#~>Fpq2@3A2G+b9 zvGgZcINjtK`lE9id4?tQQ@ZLa;RC+(undrV51NB7!xM*)8ja;Hkj&#IBiz1&KYJFT zCszZPb~FxLx=KrVsv9afo9A8Js>;R-9K8lVa8d*GDHkgsCaP}@m#8%SpE z;N5p+D6FEANAc+~l^Ov*jw`_ggM2tx=Ly=DVLKjnGug!_d2X2|Z*F7zM(2Gi_Q9D1?Lg%j@SSc6LV3WsLXj!|DPQ7@w7eUJQ+rZw z3M^$YK)Do*@yqr1Alc;St8g2_$}h6m>IKQSYJE6FEDRWPFpTzLdBoLYttL=MvJyYtzHsaXK>K z#6IIDuO+9F&6alQGK0Bv=F?zA4w^qty!R7xc+#0hhBUOR!G_Fk(V?dPa%Ru%FwQu; zvcy!VZ+23xCrTen?iqZc5szj{ws*v{n+RX`TrL^Lc@W!aN=D`PAELYSoF(=8xpNS}a>p7=RF;`C}cH0V;T~ z4qm1`;2;O3E9QH_G$G2gRbbEoaX8BWfs-L3*W4t{zS=2Qd<+lFvs!H)`I+}?2-iPl zJdZ;83zx>{hj-ER9)&XnqW6kZPot|s`tEP&4^Y8TX)WCe)DL+n+(lDvah-hbdPpd@ z5R43cPf#9sN4rH`RJ4BbH< zJ!;+aLK?V7R6gjZLaMX8ST7{~j8;XDSt713+U8fO&6B}HI_AC`)y9z{Ty{dOhyCN# zwoY0H@+3}xqdw9jEC+G}c*k=&I^PrBmykd46KS*seXRh!EqK0{uTS+%ZbHi>R*)sl z9IjlR=$829HHiRNHi=|B+rZ9RYuDTYw6KN7KK`apI0w`nDCE!&(!mNQ`ae(Jcd-5Q zKl*C>jlcbC?a}*oVnRK*`$jwZ=3DKP4}YrdX6vs9l>4O`2MCtHzp~vu>9oHIvww1x zHsNkQo9E}{Zr@Ty*8R|2(iY1v{9%FU4e-NX`^i0gA=5Sb3Z}uniZat)c{e?2|AWJA zPZ{tgZE>cD@T{mprjaXm?W(lRM`a-!kqtwhS=kJaX)72X{V=*d|{dAm5@#fiILhVQ_3qG@Ic9Jm??!j}vnkVTmpcUfv*r%LwJCq7W#BI^DW8#Vc z^V{WSi7Qr&!u7AgS36<6cIx43ri-QAx2+!J)3YP*1kQM~!) z_uHXEhw033O9REz>2I<6z`_?t0k9yeXc}}m;|6_0x$vUWTeR#f`R+-QIS9uNVF#=D zzEI>e1h|}X&wCshjxB*JI&$cE7Q%NLO8 zdfUMvN4g=8kyi66Mx|2UuS$zQbt|!qnAnx(R0NS|zZBx&fj4oR7GsBwxHK?Y7G+Kz z*cj7b$xkX@;@Dv|J<76pDze3gawb1OXdI24IAie8wcv%GI+P4I{iR%a*Jw#6xZzEg zB<1R7J=Qa0uU_2Xu(>_#y}ZG|lC#^MD*;P|mb85GQ=eq?_H4VzN%}5@EuHHIJc$># zicR`MtLPQQ@f;R97f4EGNL(ZaNXkz!SQRYK@*%!7wtE@|mf8DAS73p24y$H^Yh<=o zM?ge*gfOwis}A}%$L0!OT2Qaujz$`&<17inFy^_tu?J~)#9l{Z7Tn0pvU!@nyPCstos`|jhR_eGK&M)sn zHhS}?-4(4r`A}v**x}9Fz;O4^vYE6bT$)uLV+)~Rhb^{8K7k=Z$~2Lp z7xLr39mZ;$1|-;qt-^1!Dj{Opp^Qc=hT6FSa4C~$4 zyGlsXU>&Kyc}J3@dXFbdjou~Q2fA0qj*xEfwOcO zeAaJ-JJ>aB?O2{~zNVf8TNnc0M{%Jm&&X^t;}+>u-V7Y-d@xFfblVoRQ>}hfc@E%D*;8T*;%3y~i18iL5(ZMI2nr-sMKd%P+jm2J?KkUkGi08a$ad z!c#<(wgF|o4zgqaxA{f~)sCnWYI77aSM;!?m2$5hT7u{!5H8D} zd8MCa$WG~;t5nu0pC0~7!dxX4TOYf?^3ANWWHL=|iEpdN_>qD72cu)aVdxi#`M0(a z7P={azL*Mg%*I-^7v(Jh(50Je1n%IJQU)UkmPYyHZr-@}Slv`MQgTZvfzaj7idSi* ztblTkzKLb=(BX&M+sEH*-+tlyZSUXwV!QwFk@ma4`}eV%cH;RQ9`iWA{Pff9^7?b_ zPv7}VY!wre;)mCL2M)GF_dn3yefMp)#$IIg)Gj9NI7uJcH7jm%^Y z6iI3H!@DQ;GiDHZ7#`8v-ooBG7_4mP84TIGvV-<8gAK+u|Dmt6#Suoimh=55+kGq@ z`wb$bAl>FrI+eqMfb3KFgi-f-Ayc>$V1cmWQopw_v+jc(|2rs+g+s;9XA>ysc0Ap? zuklYujd;dYBjP8ap2^WFXYW67FEz$JefX=ka&5{2Qml?e)$hONeQ#>s<~x$f%K zE9@EE7JFNR2J@M@a!>gcKG7hkMqxM=w3h8T;>B#Xybx|-un>Eyy@g%6&SHeuG+t~Z zbUu{JcorfSN&_LCURc2A?5CBou-VHl>z25ODR29z_g@rQ!qX4+&E)4Hu3_(gk)U(7*=3~4VmM_{OV;EIW(Fex=uBcF&ivYOjeLZeQd)IqKsj_ufpp-jK!#Ya= zOZuRTT5^RalZNZJ~8+X75Em z)0+^>Ri!Yz#D*yg!T1Y5%2<6BvzLnLTRACoR}py$a6Ao7EW(1P)0S#55x5a!(M=gQ zbMs&HQ>Va_WQY{rB@*7HBOxLoB^B9snNk4UX+iN zoS{m(;oCY-I+hXZd{+ec2`Bm2UfZ#>-gS_cl0X5gwvBj3UV5)$fiJ?1zjyhy0n@`X z*#HL>*VGGB^nJF~;FdMR^8=~({x*Rv%oW>EpLBI62K0Vhr>v5$nL4TJCwQ_UNceCC z>l<{Z-kqV&%M44E4|wPYub~rUvp|JT84jezGtvxHVofiE%+j9*-1Di#RM?U$J#O;v zE-D+T7R)`-PCW0$>1-P_fU<15{LPZkE3%oO<3Uf~)xnSMrf5g}DXE!kEFRD~(^fO+ z&``1ChhEZ|x6{6mGFp>h3mkxHxv~6Iodi7P%gD#t7CN(*eKpz@EOSgAYHulm zf#0%)fkg)m(g_5L082;)mUxO9!mP8t_8+uQ$ur2MKM_PGp(#IejVg(GMu2a zt&5!p$S>_6V)~X&R8+r0M55M#@~6sGuk>R|a*P$yzfC2q$ZLs&8QPVgOW(3?{+b&Z z&@tQ>M`>&XI)ja}ILkhVAz(^{CHZvhnY~ZOvQ#;rPZA&65JO@CGUsPp3YgvyQyBn6 z4;gi5iM*A+OH{NBt1y(2V&aQZeuKBac`)8t_Ov|m@F(!DrGC=#lwUikDqadHJfPDvTby z*_iV4Kc>@$mdopPHn{ZDc*c+rr}oee{LbE0V?Gg}YnRaSLJs1H(LnBzIcbxRbb>l;4LztP@JG1t

1QnnqkY zM&bxDc`Bx)!Are+2X?}@5oehX--XkWPY+1i&Y_4Nhpk7TanHaH@C-fa;CdELXj;japG+4Y$;Z6Kr$3dgn0WIbFB87|yW#rJ@_E61`#M(8pOexHNGTk$6^v#tk6CWh6Z zX~7CvW!D&$r|NQ%DLmnk$DzyV)KkyoPvnDuDB?DHBtHHY(bR=L0}|{-qN4R{(bm`@k zuk(po>j-}~#I>W&>MOUboJxTw4oYhtXj^sGhi(TOUvkmU5;)Qg3S1-+Kk4SZSPmVx z1!UzPxIKt!7ae%_ar#?kcAeH~W}udN_aMI1Q$bv_$u`{OS2JsVTaFCITqlh-+Lvss zv(3PEjU9W*TYoB()V0NfoWh3P0GY{zm+u~LK3U4MV2vTaUim=X0=Y*&f zI^Te`?#VxII+?bOksRW^d<_{goIX#(27l(yM|D$t@}U7QYE>VYuA&*76H? zGZgXDTQ)ZH6nciux`A%oCt)2={FT%ur^jYon?UMSMn)Tg{IspJA)-iTv3I1y>j%)V z4U;_EK%2-T{_qFP{71QlPu*wXW}m~Oy6^)S7}(N=n4;X6#tsxzT!5WppiD{lQ{O7X zywTny18v(li#&hFFE=sSLq2Dajt-|2KiMkEiW*k{d7x(O1kpWv!%m)gU+sC8g;P!~ zi;I2=n*l@hW63hgcP#8f*bKd654q=)<=Js(#bx=mP3N9=+p$IyxBY^MQgL?v-5M3XWIGo;+a?q~oqE!ox&$1c$MFtg`r28wYRA@XyVB^X<78US`&wFVoL$YY#pA5cc;v zTV2melyu*2Zy$ZPJ@SbMnYn+6ZLl}mB_$deFoh(34c@hvS#2ENtBgS{f5{~67d9wAbq`*) zbQ@)QEyEc=!5<(5>VQGXUB2cRe2|8HlJs9}!gObr{9R8tqo6&fe2RRBSeH$?AEGbF{ z4<%Pg9Szf9gbxQQy7CIEm^5PYBCP3&!Qwf4)4^G3kQw+#h6Ke(SRiVJf{h-Q%OE3X z2c#`772miy#Ex0?G$z33zHB>x?$HhdUM-B$g1?1zM()5Rj+$M-NCLmYzDW(RoMe^- zcsrPW!p_9WyQ>d!cn4|H@O2R;%>bn{Y93v^e2K&Tmh&ykF{?uAB17Tgrh*?nkQ z2xWrdLmr5z#C}w#`V6Pk$6wE+5j6GhKA}na6MY89h!D9bpW(s1{O--~Jy6WV{0NV; zggSW20UVenlsYyd43TK*X(JqHboGv%CExwLojPs#(ysU?-{R5^s9!F7PR9y=ihVD8 zB@5w5m0$v98bOXOZLEBQT5 z+0QI3(*bX5Fk&_3vvlNL-V6^-(iKu%hJQ8iXi_K5*oulMC-ppKBYygeLuVfN7%kx; z-aX7v!#BIgH^e)9$5*&24@R8AcW*o!VLH)Hu=p##jXdbL(P!ZCE^p4L@87?hZB~4- zhS_^)HyOTbrz(X%M6nZ~d9`A&8f{HuYMqX3|c} zYix;l!=9Zin2G;JeuZ_(sSREm_cl(KsR#Bzdv0y9?b&~*EwB{dj=g8acovVVxEA2m z{iUMiHF}|qU!y_qsm*=~CgmhHO`3M%={!)E3NJr)TJjYTn8;lQ2~61lKJ6g@hncPp zLHP%v#O;*pNGOo?=xcu}UqgiBN2eit@n~2&^LA1^*i0M|RLL-p(ucpnbI{&(DQb6l zZ}JdNSOi?$ma8!8i_gCDJnTfYlsNkNtJDQ5u;U_H5&I`6UPt*X#QJ`?6Z-^z1kSs3 zKRnt8gl>*C!8`-M(J$1yS7Lh^Ame$$4*`|v8GNOK8$3iITp8reL3h7fSeT7Xq2cxe zUFWMnx!x6L)&sppfvder4#oVtk_9R(^M2;7_u6On?Q9S1TS4Z0wvB_RpL^$2`^^4b z9A>@NUgVsPtDMELmyYMTYjl8Ft+Hd+_V&n5zG`J#Yn=m`;U{ftSux#|Q9t24cgI0A z=r2>w)~>a$^Lc9^+t1v$ADgr-9em5*?c00@-u9AgQ~$~Dyq~>PCfEh>nPlq#Qt#pS^Y-CS6esg!0X~*v;73=N!7f-dX{>A^tWDnbW`1IY99dKl}b?F-EyVVXJ z+>h;9ZzoQjpwB}a7Q1`wonv(RkF-yI@>9&*ze{`3m9`ve%2^_JpeKJ$4y~+gCmke< zjyzLGJh15pdkcz8+_?;1msP5ydv2c9O~^1#F_GTdYF%EVY%3?_;5G`OvYH|GiC5(t zc_%1xMsworpw<>T_4Aw`<(BSjJ3?S9_S3+pt5PfFpHBBNcI>-=$&^)=;ydDFq3~yg zG0g#A%xvKa<<%lUd5XPBj1(9OjmndbJ*5CZN2Q}9LD3s!WcX+}R)tmgKp9vS&gE(0 zLnbJM3nhjUE^D{sm1PAAB1JLh2$CR?2N@Vl&f!kn-|v5(e&6@rxicJyD|(mgd*A2jaQd9n zr@K$*emtAwq=ax*;;iK1PWqH#=!pv~;sPcz#GV0ytNqZNw^$j21DVPL|AHq?J-H>b zh%8~|PGm>mAlaFqlzP{Awkw%5w6d15Lh7ni)CZ zNLocQB);-5KotxB1WnS^!#JA$F4uQ{3O|8s)(9Pjw^?2679n|0ZiX-Y3MeaOSPS*Q z^K8f`dGF!)C0^&NNENb~em&0hyp7v&O~9v4t8-MH(9T2_bvV0nNZ-6gwR#vRQ!Q1PV=c~R5}F_Dp3q0Uh;AXC_W4=-HIjj2hyR_JNv2I=-K%>=O<**P!~p~ zFlu_;wUm2AY@E zf8;UX&>gl$@4;n-2v&I=^OJVGhm4sB67`RtU3KuTZuDFAH6g?iE!uDgc&4k;hMPZi z?lSJEaoans0CFQwfV0h3uBOQ|q3UD@_i0~65cw8gmWen`N&V~7*@s)fJ+8)}o=?m< zq3mk*QrfVUl<~Qj+2+4ybDM7;fI2aM5p5f^y|H<&TYm>yzS0iJ7k}zq^TcpFQ4jzk9C!%e%X}EUSdrL3WrA+d z;hjmB&?*9f9KiKS2_W8xmB3B_42Z1nSDHzJGwdUT6S2fG8y=%x;cs4sJA!1e(DyS0Qk%l zeIORCjvSt98&@rD|K(4atMCGF^mQ>1Ht zTepgv?9mM##Z;FpMju^b7sSeyeCccX9NbKbfcp#=W>1|tLZALf`_?0mw5=P~wzX?l zwUsNDwv&81PPraBbhN$1PUBbKwY%NS>irXYp2)y|{rYtrJz7Cub}{(;B(*!3VT*^u zb?-@YoOOwne07Rn>atikDeJI(iT}Ykg)di)q_r$M7PIZ9YDXI zMFsUa&3+~{5(E0VmkkI{AGs^QUC`=Jry%Ci$6dm)4aY?_b^&21`ToH(-}`|*HRBQk z3^UXA&5VyS&@$Ll7_2}xCYFYP7}yI6g{r)%7zUEl1E{O1iDFz3dA?&_ANYot*aYt6 zq{|O?BHGi{SQsg^bNTesWiRfb&`@Fs0OtT6IMQ*J0kIAF&Ye4%L0i&Zc#&B#(+HrA zOa{3ys@rYwi@{~Vb^tbqn|B?sD-2n%qp3-wra%-@ysEQY+vVk<6hk#)fKUsnLrEvt zN&z0jgtrske~T>q@G8$BL3G2w6e7m6Gh#gDt7s)|di!9$cc>hk=2AQqh#f0eBJAi2 z??i=k9eg?w;qCxeCQM7VHQD(Ar`wh6sfow$1bZXCJe=fA_;NaQ${?M3D(zhI(+VF0 zZz_#$Pp8B3Qa(f4<%RU=Coy0Am6BGO;HP)eTG*tgyP)My|I4|3{>B|QwkIBcBHP;S zK&DeqdNXJr(xcoW`{ac)(eR6(^tIOnMadilNnds93nolXJd8RrgCi3wPUvL!1a%0R z$eVILiLzIzc}bp=Eb@}P46TCgyF?%rny1e1{l3f*fql7IwfBI_8(k;lH$8DGL2SS;oe zv(CTU8`THuj+&?2qD{7X&%*Ja+{;S)IDovs6sV8KIw z(-TZ6%FCHeE<6TBR~pyI{$hmJbdTbJiX$3Kg%{dEc6wi7#_>l%dPO!PpI8R&%O3Oq z3g=&u8zM||Oh=-Na-AfPc<($IIHn?&ffWPF;9;BWJuKe!;jy)JN-1lWDeq`W86Zzt zw2NM~WY@DHkxL&O3YNblM*YySnD8n*}KyJYdwXNvtnmS4*zIsyHZORPg% zpK>zLsvGO+(2@q_;qC)JqZVKYS{Ugbh;B2``xpuNW0R1P^F{sr=O~o?eHF$}GFUI{HzxCl^=={wII`Z?+$O%PZS*i$CMe8&_^>_ujq*81An+dnXH0 zZ)odTb+%V`{NxljyE|~S>@~t(-JW{(h4vpm{F(Nxho8@`F?I6Ai+nbd2!HSI{1WHU z=eGyG_(eW*y`tTF@2gpJKf3!H3%^ zj?8@HTaPh_hiBS0njuG|3^p&d6-zI*U;U-`Fd*L1&NA7sm}9%2{NyL8e^c!SKHI$K z$rsyG&%D6p)CbxPBC)$xSr`qO?+ej`ukx93@^(_6%OPAT@%Tb2;=&|QsIK+46FSa{&Y$ZQ0 zwP#-3pY!>z*mYywn2*4Yo?=mv30)^>QLM?YGh8ITZ0REI=sMb-WRk|q{yc)P3Vo}7 zI>aQ#ZOCCEV}{4r#o?z>b1w-wZVTY?fEzci&!yiB-4%5aS;CcV#Zb(V2Raqs=teX8 z2h4o$2liCNtk(OEuzi;DR7vZpqKJCnUESzGkpU33V>pGz#dfwqgjmJLV3~owZVOEr!hp4LP8=W|$R0U*xIO*!Q+z&REgcTF zte}x{);za**5KKO+;2zPp>;c=6dV-$iKtr1sO|fqW13(h14sm7r=f52c2%8?FU8LA z>)<|={X4Eh{o+Cl30g?8|1TJ_UJp2`^dcH+&L5gpR)p98v! zr1$LE+L7Qbm<}ji`J3vi+wi2{0%q89!J)eqkhz_yizvC8p>s8yZR2<174fe_-%aE-_RdU!(zA2|llW?TZfC*zdm4h8bab}<) zebSMP!Ovq3RV*axuLkzYNu2345htk~dQ|3Pmt)Eg(Yj10$WOBtXFdZQc;m{S$1I#N zUAKNM`FcEO&{nTmLtfH=Fp1>kin4GQN-P7P#q9){8R?%0xxxzRX{JZ5bW8+Jvvvo} zr1LP8C6k3n@>w}M`fS;)!87n67Uz)ilGEU4+57VvV;0u$grVxX`KauDNmtqT0cbG5 zQ}QyL&W^LVoq$se1L&9+!e{yk)B&*;odL+#MA(FHtl~|c0F&~PZV`6n56@NiOOIJs zRxnHNJsA$byZ|$CQ3aMA%X4<3Q2y0J)}0KR(2vR_v}DIRqkLvCBd(Gg^oeUaorqKi z#U-5#dJ0b1$enoNOa$%Xks5Ku(dCtnWYUYDo|6n{?|=q@BjM_d9w6>SGYkp?Es+&i zg%cp-z!pNws>ZmQN@w{ceYPLA75rKE3vPIZkB+J0=NbNincz9Nd6Z;l1Pp-EFzvxE zZcRJ}d-)8{+5Dyf#1U3zlA8%exU|P+$fsmP<+JDKUplZagLwz+r|Ar|6~XGO&R3pZTn6@+4kEm*sdvGIiR)XNkHhDzDb@2Z<(ACl=1+mxIB90 zr*h{pp}&xylg@K#hvw3*x%}pP4(*p)@|j&NWOi6VD*uw~ZH74;eNO?JpH4091GueA zegZF(;o=~U{fp{p6raKvkfc}u2U+T?JjxKBMT>&x=b;Jhse#*EE^w9nu5Fmrj zeMcRL$hBbYgGFvbS&Of#Ym^rSH+oJ(RB~24mG?jm;TDM4vb1v#`P$_En2lSNi~&4a=Eah5;Woj13mC%HRn?(+8F!%s7KK2JY*ZhLnB-gd*bMQz8n746KC<*ckPZTH;l zkwy5X|F&-R+;)1)s`l{8`AjBUZa?$xx3t&(@Q${5>qd3~JlP(5d=HCyOBvjwZ_c8B zsHGRCPH_*wk+x~W(zfGxjYsXg-eKF+^C)Ak+Y^SLOoxom5nI)99bjo)ndy=DhD)7uX2MBlkW-P%oC z7Pg;z*X!EuJ6@5Af^!#+w3m(?Z@=;j@8c7kYuX>*|EKM_7mu`OpFe~?W$Qid_t}eQ z+WE7m_>#x`_VYjgGwoHcxPePMQD6L=$oMMXyZ?`W_(y!n>(=)EpMH0H?9o@W-~0Xl z0N?A|&;8;rGB`iqe)m6qu)VOKN!Zga4zYMi#3hU7wfFqQPq5?qc>Bs1KG%Ncoo^<~ z=d?fi;}2yQ@O$6+Q*A%HEWYvWhq*6>b#yxIKlPrUXnXg*)V}(S$I0(`ZRzqA>Fe!3 zc(83+zoPvYzxnfR{aTJ%uz337^Ut^Eo_nsXU%jS%=F^{}jX2ld_n-eX={iT>_Gr7E z9UH6Hu4#`yu?HDG+zuW&MqbR}sKE-#35lbO*`9cm&QFr2Y$MN6!R!Sze&64ZK3e_W zrgD(E6@R3J2SsEDGo2$ia+YXlUj}7^I=2lszAqGz&gkCwl}d?9BMh%HllJaMsH?yt z3Y;*yafvm}1_iO~1Fi|B*b9xfMV@BWz((4R%32yhJ1!byMY$P|pB-rnw*zli8|d=X zU^*SefZ%rUi1HxZ!M7%z1Kvrmom?@?FTZZOy*d(uQa5?f^-?%j=Ntq&;3FamXuQIn z4kv=OW24OFRb$6gt7P;sEcv599k5Iw4B^tZ!=BDRy!$B()4PCeJa*1JuWNc#67?2uYcL3wrshfB1Y+JW(Va5LOq`}WFN;~wyUE-?Ap9PeIOgfQ= zvf`uyV%?0+Qf>}nLu^PJ;kxyTngyn>$jhFz0uCJq z63ShC1ch*+iVNN-KYB|iwt^3^$P3JvMN3!_%rN@YpwKAA=cr&Ntmx#jR_TCaga_IR zQGJ(sW*8N%$P}%lR}KRk@aZ^YGzlSWWQMebpOL2wUIA)U`4xTSz&n(A(myz1wPdc4Sz_5$^lHp3%imcwlO zbb>s>WnfR4G~b-ycH%O+%(ewgnIPa@6R}sRD*2I$MWL>d8$MLy~ zT*~C&-SX(y0Ej?$zjv@u=6G=*jpf?`enqxi(6;xoKzpT;hM$cJA!JZxLt2$*(yz%a zC(4{;uQZrfk)Por()7sX8a?NFmKQ|!U92sB*3PlMGFR{LvQ#2NEby2M3Byy-NEtOz zHWDL&gmc`!yXp4HxA7)T51aJ6(w?%achXrnD$UxJle}wqYKbsxI|q)mXz)+n^IblJ zw{GxsKjQ_bz8D{q5jxxz?^yti7bI5zU#CZp+}}j&IDOB?R|h2xu?Ajymy_{I2BSf? zumi5d=`stK1EG`=k~5+i#6VaUI?+U^SjmU6JIoSgTJ#~f%2k!W@)~ewp$zO2g@ng! zrp}*cfPV_AOWXeaFK}t4E4#EMwkPm-o-OZgS*MbOD;LgAT|C?NbC=N99(bT_-+n{e zdc*Rzg3q0;T)L{AIyS{oGQMEpy-^I6Pq9mA-nQkrVC^whr*FS`SKG1%H#g4Dy|l1x zTD_?K?E8MK{ld?_w{6(GHg#^(I=0rcGQWh0yhF#&P}kY5L%mr@dwGgQtXpo_)E3i^ zf9Qd4wr_mx8|~c;cyHOUsZF7W=CJy_ddY?Ms@t}}apK=kE5}-M7F43tUL~5_b)} z_3k^{`VCv!D{o-;0@?H<_r0cl>~miS-zkm;oEhnx(-1m&_84vS5%5iM%zyzfXXV$g z+tA+j=6l+myKinsm>}5q?6d9pC)ujcy#~v;FmL_BIc@!xrR~{Q+}?iggCA>rcd4CZ zS1z{@v=hMJee2G4%dX{Z;rS!&uH84Z*W7(ed)kXSlsT|xwf5V zcg9LCS-tzV?d_AF`fPjOPrjwCTE*R888b9KiG88H`ktNbN8kR#?f&~e)V}%PV<~_h zpR&yPrLX8>75Y$yE&5eEMkUqk_`Wu#{(Ek0Y)YF<2zpQ&W)3+s{xKNI^t>$`KVw+E z1&^Axu`&ZeiW*2(MycSd=@j~VsLu7o*wWMSr2vyZnDw`q24H)9tWo0h`)jvJ()N`t2jh3j5H=+u-n=4Hqk9xHn&|j-%Ll+ivG4 z$q3>*VDa7a*BNT_XUwadPMYFfACn?nS$f*Wu+lfb&FAH8zxVc22W9>|YGJ3i*$b>9;Zgy0L521=BF&Q;cY$gb7vjz z02)ZR2Byan4H0zqbPYJlQ*Xn&9119L2Bdk#dq5y6JarYH@!&D|kK&Etg$pb&CQUQq zE4&E{PU4o_0umac3v9xNHm!nZc@B6gCh^2N!wmEzlNmupXNKq1oTe#ZK0DF^jtKIY z?w?Tn!;`#WchIhJ;z#|y=h>GiYiv1nm7ED@C-fZf+GeN=)B|?XylMI@9aeYpxC2Q) z2mGhl;;CJEciiHyJkVBjM`<-fh9rbr`5uHOr?!s@@}g%!u{-DMWloovxOeD0pL6oU z+r~NbV82n^UWnx?eC~j7pyY%#KR?yyh1=&y+c`cHb%6;2`zH=moXj?jrk9dH2cNg} zqPkl0_l~3dpcH3Kc6JB(I z!=lS5F@{{f368`qyv7`rumL~h2A;4Cr1Y!2EMBHjOj@h%1y>Lh-t-qJd$z$>Hxl$W zo9SWwJsZsR`VBOcxn_`I$=5u&@>hZ{@X2RnF{Cqy2D_8@rF(}rI#hT1KjM$O=tRFV zk>wp1#;c!p%BuaC8NZ86q~(Wy?hT|B?P)H;JACv)d-$QJ+QEY-&@ao7rAK|ZkeTW_#mX-SJKOecJK9oKcaJjAKXUw7 zbd2R< zwryG2Zgo39y6LuEH?-gQ)n96V{jYtXZC}e}o}AL%wPi!w#9;d@_XW)3K7l23FSX+b z_P2TGPVyO0Xk0wiKKZfx+kyRu+g-c1w4FC>q#U$%@TI5Q-FNM3|LmXqR{OiZ@hfe^ zig|6_$|W2f*irpF>bQFQE>_=n?b^t#{%6}4KKs$O=aFxqd5|#^s&m->fAftS+dJO& zy0&yayD%uX^U%ZYaem>+huW7u^Qm?tyCvTLo_7Mbg?wc47rC34_9d@cl`VEZAm%^G zihXY&)I}=dbkcYZ>TWE06_G%gf{R+nBRY{vZloSBe%+BciAvmp>F-1cumM7{Usn0XbS6B46_LLT8mxyoVM3<(arX*F;1FDypc*?}upK=G|~ z^3)n--@|RBye0I3uRp*n>(k-UuK<{T(jBde5YK^2aZ-bO$W)%ex3FF;;(ZS(56XmJ z@*tdz9|Nm+6c=%)BOw0HS&;VxfU9VEk)9VLo;cwb3F<~uY;2z{M;u~7iGZ~9U4&YuJJVs!!re;m-yoE z!FuzXfWoC2`*t3}n?VB-;}jp_6J8k%X(ipsi2-rakAl*-aPuCK00_BsQ@Cd1sY6VE z3*Y$<8{N^tBqgm0Q+&_xoCxpMQTn>a6>o4v&f+p1L$c6U@sY50-v0Sz1&@YhlKR*S z4A6IT)M`F$A?+b;rsqwi+1oy`**u%LvrkqV$8sjk4AA8U*bBD1Bk4?M zK5`rMYC_0^WG(r0(Z+;9goE<T6d0t6ZaCI}EV(2STF(z4}CdCj($3D{1QX^BFvw zKZL@MsUVc7@~Zx)M3mSHr@_Mbj$QW*BcYK22VX`JSZ~{-)F~X^6sHt50H? zGsGQ)fytKs&ZGQJBQ(MlOHspmB}|21`)PhzG%61&z1f9h2EdJY3&yfD)EXn;Z=9>s zEnEO#3QxBsbMdP90T>?OGp)(|N&lFeGlC$Ht z+|lm1`|gl9bLL|E#)FTxC!Tz|J@qsf&@ss{hppXnm?YfAmpFd!KYXxl-t>#?GF#sk zFI&&I-B-26+?#Ql?dnqu*q5S%Z#P1hjS1NzzhVXSj&i{sI>*cPoIG%W&~|GhI}(2Ajc-Jjr`n&~e?Noj z+uKby-P8_ozWsSt?6+-S&pCE3);@TY3Dfy}+H-MR#6_a3`9i^q4BY)R>E(;wcXFQ3 zT5~S|@_EA#-P``~4?fsF_R&9WZ-4vSIi@g`9jz-?tZZ+2)0wjp6zO#ytzj!@s?m5$}UdRJ~ z!bw9o->w>${EC6QyUdxM6X8RD&&+#<{@jqJtnL$c;SyIvSp5K} zU5kaJ)fH!N+c)0fBZsph?W(>VxU7nkKdz#fM=1xy!!ow(HdNj#C^YP|WikMIv8SLE z4uTR#UaCC73(DO5J+Oa2H;S$RpOZ1BQAJ{k%k+!=%!lF!`Sd)IN6R+6M|MOp9hRAy zrel;B^Df30eCq5p%WKGYD7v#iMZR(4#;k5B``kw$UHJ4*la5l*<`EjfMR2FB6ep6F zc+($3n##hFcrzme={T1B7)K*7PHd%xAaXkVl!^M}B3r2fRS#vLOgsPjmRx{RAB6Zs zglkw!e%Ao#L7+}@l-uZMpzdU2zS*iz_ye*2+IapF$d?r7k}c>b|=LOmD;p3!loN1a5}WU>l4%Zw|dPS9o_lf3x38&LS4^i@7pS(h*CgJGrDsbdl*(Z;m{AfJ8Z zRG3luqRtgAAu3K6mG02100Z-9jULsN5w7B|xJv}FVYFAhE#Hz^f_U`2lx8mv6{kb= zH?#o?Zy*Z&6pWI8>F6P5CvSwo3=-+iE8d}hh3}AJ0#lC2+e&xgHB|#gv&6iHSLbgg zNTHqSJB!Ydxen~%$FeRDIos^ylY@Ks%EhsC zKrO?4veM)|I__KDv9LYaJE$WpL%Qc%}h5#!I_Buqi)-wbH{=_e}P^;5VM+ zyEWN1-oF~yQ|E|u$s>gfPMolS9NUUT3Fnauu^iN^6C89EGQyz`Um9r^KizMbv`=U~ z0yE+MPFDG_-uHZ)6(0VC37-Ij-QnGZBVQw9+W4!QV`w&WB*=lwg74<6wCBa)Hxr>&#F8Z$ygK;(dL!I-~AI%x1uQYzZ;9PnF^ zW--(Aswm|-Q+}O^q_Ggygc|`VXVf9unT7MHSDbdY&aPg(qW$mx=J(r!4?Nmlf6pu0 zG6u1y7{EXI)YI+hXZLbZ+y1uok3Pbukk_}D_U&zVzjAl`;WzzIKE>wb)Sf4vV9WSH z>ilWG<<93<8KAd07utq3E8DZr9c=&ffBF}k>0Z~Ke~vTmUwgE@|9x*~;JBHA;{5i) z0WRQVg`H6*1KI^`DLVqZIsPP*3db49Z{#-lsSEV481i3c^?LKh8#p%(tvM@bBR8{{ zvYGF~?{8oI`nTG;&FkAy&VE1f_|t8}y3K4gzpd@sxhuK0mfQGu+{9&dj~s3b*;#O$ z%jgz!V<*CC?kAW_+kA$dP8;~Tz)>#KbD3wwy4CH+ z-}64gFSg(L-T%=3!9VzW?C?Y$FK*;sFuqXYq$?MBUs}x0J<7?R7oKj5xq*Mf_Kof6 zndjT31@z@f|7ngyxo`Ehn{R3Fde=|24}S2E=`UPrH?mvw#IZB%m^jduvmesiMcX&}E2Pe?`3(=2z_B__s za%{j!56kWHWh>jKKmBR$8F-e9{^;YLxxkT&(;P8a3|@BytGW2BDiaL7pHX$C{AVf7 z-`8G$Ap`p>6`BgA)RMxs9r0|~CHAUi_L}-`*T-fh4bcEgHxxY(^+m&{Qm~=X?W>xg za@e@q`LiL@zhKlW-E^K3!owij44QK0gczvBN99)ytaQAIk@0G~NTW!pBZd+E*@%YQ zbZ#B&c^MEBZCNES+&??3Qj%>8r-Q*WUI>Ee17*Y0S->wH6y9Ds;o#c%nJpx)H&n}8 zZB>+e;*o&f_^QMu0w|n?(>yyK9HfN?o(_jw7ma5_r?Qqeai`;HEbRK*$uTW%omt6D zoVd@U*xWI&YSk*vDQ(7w88j|!bH>hiHJEfI&$HfqwuJ5Uc5aq2s7E+#{UM#?(*n}C zgqcz~cA#$B=QGPHU#{qQOMcHjw_S?Ew7Yf5&u+<+w2YUwA5LsED&-{~?ed)bfVb*M z;6pwn#55;(3@>bX_IM>Xx4Huk4$@#}4M&wZa9}T)7QO(2Czp)zwln9?FD1kvcUOQ+ zlQNfwkr7@(q+T*(V_t?Kr10wYF>wg$F^Gjsk{md2a5xfC z{+5mG(vY4Rqmf7qe);Dy%89a@mhu~TjdLO%@Nwa9kR4i}j za^t{K8KhIpd%$K)OvyX4z}~4=*tMUPJH{9o8^Eo^4TqGV$%ybZL4XZYeYKZnw`WzWNVZZ`@va=V&_*)9Hl=|UOzIuN>+{nU*b)R&AZ<-$7n(a%3Sg4#_-EE2!y7^LavKcyAg>I=gp!aGgT04z@l(_f2j{)`t!jECuizf9~| zXRQwd@1|#9qkwr1(Z=o}fiwLD2wTX}R;lk2gJJ?KlhQ2SM(BcnNY2=E!d79O8o0Fb zi#&LnMqQ<=hCt(w1eF2?$PmWsxRbnMuskohDHFG6Sgp6*+7^k^0rQ0mlrv<6SNa1g zc-?;5&iD?1yKd-{qcv~;){3XuSucSkKi3#w_ zY~`&EFO%wyhCTn!SzFVT0jKpLV&)ttp!~T#*6w1KSAWHMje2STk(IG~E37NWWCYxq{ zzRX*7n=*-x>Gc@+wBPVl=m(iYw-#08i9QQByqq~WLQH7Omai&f%4^8}@Sl7W0RL;7 zq!N%T;i3m7B1<({8N5B9co{_x8vHssgRf?Q=_RH>D*dyAgJ{4d4>Nf)PNgJB2NYxC zRd&Yi*pyuo1UUBOo#iZLp=3WG8mC9l!87?{KIDvxlV}&(ryqHy-L-B-+qr2aeeAVu zBWJYtzIeR-Z{NPZJ%93e+sgOj)^Ty(G6tQS8O)t!OZ_8{KE>+wnf50S{9$YV@L#vK zdv!iT*-lKgg&Qfu3zxNvtd@K0d%$%KhE{}?3G`=thJAQx&8Cs{gd`{uixF) ztXiJWz8&Vs=NT50)~s1UU0Bf$a!&u?iF54)y8#yP>9(Yql?WGb{{4qP**^I3kG6Z* zO73LA!UfA%l|Rw;^Xa&cf98SQX|-?vvG&ZNW9==h?%#gfO$=uF+6;Q{;NjEl#l1(l zHJ&Z!m(I2+KV!%C{+0B7Kl`aKwUftBvnsx{9p`Al@+Irq{U7=SH|)QVodQoi^Gy4r z3n$x~-uMQNEZoGUeoNYk(^L7}-;2*Z!@&i1)Ol$ga-K7HN!zk^b^D_aeYl;cT;Fr| ztJ-mOA#OFMSCCU2JcA+mEzcIRV7Wu+t}{B z>sF2dEa#|FYX^{x`R-@V=P{Wxb?!vlxSmz}=bl67{!shzcmH@UPPDA30$JQ|kL}sl zUi$0r;WQ9PPHeWewK-fT0}j=_+tro2%O_H2PAaS&$* z?3}Z#&H$!?r?bbt8$aVAtlQ1g5d&7yCNk%YIc;)QF^6CbUX3pp{rss#CI}FI8A@YF+3_LOig-!2fI9Lpelk&DDJ{j z1M+c-QkM*?U|!?&I*32TWir+u@2l|aujdZ+w+>rByBzJzXgcPg8_}+?JO{Y$Gs8Jz zyZZ+pcrtk5owAiVxT@>=Ys`D)n{XoOuS`>Ka673Y-^Fv4A;W}m#{WeccxhU@_w;^4osZG;HF0vbRk+})pd z8nzy!+X1R|zx2H_sQi)41nz;A>wQVli4t{xwLK1M9i&nyU_Kmm^m+5>GP(+p#2LaO zM%&}URK6iP8M()h9`VBMX1TRf&I}gy1y~X#o|=phtI6bP9?C>$$%zhl(8|+Qf9ds!ocMsI-3n%WB*UfWhMRMh0|@t;tTD+|MmB_*K!%$R(5w@bb^nz6Aeb5+aI8e@@M|I z2x1#+d*)ph-dRy49$fBVHEqD1SlKVRTNk6gB|!OwnfN-*W_9R1ld zeAeyK&0A8=TpT;cr1m-bdsQqfD<;mL3lNL4xCA$pw<+}3iFS;E_*~A7 z-tYXu$J$NX*3&1af5Yxi?>3poYWRv}YglNR!|_hiMBn>Q?*DB2(EXp`=KPcNH%}10 zh#eKb%K(30JHq`uU;FyExdH#7_Re>_t-bcX*Ydf){cX?F&$qq%&ydHbsJ~|BMUu!p z3EzIA{iA>UKeQkHk=L}lZoi4k58;LT3!ZuA`S#LFFR^psKzoP*{$ef#IL4g_+quB{ z^{?l%hZ{B_t4G_{zWNO=)8pbrGRvb9mLD(mbq9yKf?)~=W_(ZIeG zUqp%mK2K+O2_2lSGoqvrdMWuq)M)0)65c~zjGGi-2#kBA!7Frxb6N%#rpnZA7cUJM zsG^>rp?;tyU@3l`{Z|pJ;5&?Nv5%2}aCsHaHY%=))?k;4g%Z-Qv(P)*=~NF(Y1-|~ z_KuyMYa=*du(R!F@fI_n_Kf)nRyvk*8HUC!>gi-BJ~;TZgJ@?lN*vxwo0!6d%F1~Oo^|owBR-8fLfYNvKk3%4y!>hJ z@pN}sacFdF_g8v|jne37FDVn=dfn@3k8d3F)WMCDlr=fvphdc@`cco-gC|&#aC=-< zRDl&w=cT6$E~Des9W|*a9w%382TwZinG~ok%U(7Xfe*YJ-~Wzxl)WQ~o5~3TgJKBW zH1GK09c00onf~(bBn!QA432T$OrVOj^AlO&BO3LaGISfJ-)dKvbvew8|8m^Y=y`6u ztYXeg;0WQ>c^-kxw8;GRM(c3!ltf!r`1!Sq==ZdB+&FC~jH6CY;$Gy&CcnpQ;SolC z=H*w)%5=GVE@wt7=gjQl(0tJD54*-VLk7H*sE?-eVUhYf07RB<>jkV zR&AA~pYj`c=?xV=ZXP2e_TsDOxqL~Zn+h#g>e3J}#Hs=5B!fNTRo)K8krGsul~~w? z#p?o{+k;b=+u`Nw+8saslWo(T_i)?RdKz4I&dp`z(zE$f{Mhol_Rzle{KH>whq%CO z@liVTwk4dW%^d;ouWaO1AtqgECm<50OXd-9x9Z>RSK&LXDi`xjVE!Y!IE`$YCQRs8 zc`&s20K%w*=}upTcm4uod@W@pRg;3caY$eUS1?yRXM~p=CZGoNqMB(EbqJps_T9J( zC8?Z^Xh%GmHX>ZXw{T(b%D1~eDt`v%k*~H9j=`P$>T(p{gz2#6OAH9K&t=8-JYPRr zy=p;w|NDQmZJ}H15);=fCp)Yu)hboA{_IJW59_2q?fUmPx;6S)L%Zqt^zUIA_~Q-^ z+A;N|eHH7Hacy#Kcd~2MSnf*MWPpJPJL9Y-t)qG#Re@1hzpbC_m-D%pv~}BtOu+ov zCqCXj{P9n+BVuJ_ba^g2Dd6`!dR!ShQL+NQ>ysTf$h_gP?Zu@mbM=h^F12akHu+axxnDePq1}CXC~f4FIe}q4CasbkSQZ2F@h@v zG{g)MXZMEcN&$=)4=o}FK3)}211)0XOa)X$;BY`sS;dcvPDPmOtT2VT@C>NLLp&RO zEw$3@YO|da6c0E|p(`hTdsojs;H~X~;2k;@Dg`?-{;5coF&N%?^Uawkz^k2k?o2uy zc8Z;`)~_3RS1u|E1Jo~eB=Q5NVNtS)qrKoAB-^pHvg+3xZ_{j?;*B(zK9vDK!(1Pb zPOSz~`RRU$hc^JQrl2qJr zi1{+pZyfq^ZIK)KP!k^25nku2J-1HVVA)Z2pyuRD8X0Nxb5K@X42euCih8AJHcrNI zMl#3Cd^7sUPt5vZ(tHi}X)qNWKBy%TwsHD|PLI;_pm-IdJXBfNbuH6*n1m6pI16u; zAHxT%lb{p!szlO{(~Hl0B0M>9HtPBVhnQ)1UJ;am9( ziJwe|I>$O=zB{0hR+1@Umri|MkIskK1<}sXNTi z>_Q?zIU_uz$vEOy&qz-=WhD-OHHoBN86`3FA{YF+f8e?UnaR_%!M41nPz{8AP0F^% z?ZLXcfsdF;7`@PSBQuF><6 zeO=bdKXocPG3l!ET7%H<0`YZGzZy`4Ng!`zYT9j2mBW@DH_mbQ~@FJ9v1UG!1r(Dol^HF3##78BO*Y&-5<-4-3@KAWdL(Jr0xqA)Irox`bG z>hWAU*xrr9p1LH-N76D-4e6KpNIh06J?|Klq^#ohFR1fUZsyyN7nTp&I&}>N9aiMY zHlr@awQRZVH*yJ+#3rsh2e04`-H20t8-wsH0e;6+1n+l*ngn?HF(zYQ)qWMU%C!=I z)tJ)*#M5#0w-AwsxFWT<4KDA>f5EO-ZXMKobO$P#*e-Dm`~uFHw~Kz=f>l;l+>bI5 z?B&U3?Rj_o%v+THi*)TX+Rt9FgaxRMP=9`g6+I8Gj8$;jtS?T=y? zPlpkQV7lEy;9H}={gr(7l8MQVpI!kWei&{HYy5%K=#AIN7*}}t&@OJ>GkNJSzBR>{ zCD}Fl>XjRo?8jmgrah`F0f~m}p#d>>D1{P;oW$_{4SnWO*R6*a7~I?T`Z?TuB9pL8 zyc2G9I!%9a4vU@YL;F7Nxblds$Bk|8y>QfVj>r1k@p_2~2PbgPPB}iXpKt$#_|*5s z49E>TbB0gtGTC_Q^aO+_$qabi1{AE%lnS3cXb3aJMmGbL6!B7MRsb(fTgEx>C7Y~%qliIk;gk11 z6PH3QPyP&Jrpu0jFm@!Ig|fgKSy~oa6RLeQ5V#8Hil{$}d z3>N5AMXCxJKX8X9@SBRWY^{-NS4`Yq=oaEWs5d=!z^$|zx6H;24P~vgIS^pC00R~~ zK6cRZ**qp0=BEZ3!}!C1o{oc^_}(d-l0E}+E2bSLSPsu58&iXmIy3Kz9f}(TVFMt( z$dL%j*8!@ZcJrp>nn6a`kTzRJRfYUPEzn>YH$e`jV z@Tf`(X7OhZ3j5FN=-xB1s$MS>C5zu5Df0g`B9 z)xY4%Rlw@aLtF&<`q#d$?cTkc?Sv2If*~j5qDuJw3|HyiVDp4f;=RV8QlH zy%fGEPs=!Sx|r3TDbBVZKkhCxR_s!)l$#UBRi@1ojpeB4sqgp_7CVk13j>?16DIkE zmjW?w3>7dIvv}}F4~pk3{gP#y*0z-^>C8^;&x)J=b}HrDxS4<-=mzJ2D}=A(QKjPA zfTFw}II;BXb+W58IWduyU&dLzV^>?Z^Jcc}Eo;y5z2`4}JkddM2M;>3 z80b;2`4&gVd`&ib+Ks4uaV99}PR|A+moc}@iKUck{D7NIGV>IU&p{aDq` zh0=kuKR~(VFFZoKPeNJjDALI^c^D9l(T2;_Bb=2=By-e&%jZm*E}X7*B-@Z`j!j_q4n3+}R#` zW8>cN5>!)vQXAQ60&z9icX zGkXIQ`)rTO&<@kHS9dxR(hZKNt{{*fFK(L8WjRYI;Ae<5o1*G5`pUE1TNw(Lw}a7i zx=n3C8?Lgo0zyVE(nxukpq&N>^)^xtqW!tOKdXauIvm(LppCK?N4OPpRSsu82c+SH z2ePe3Oi~WC>vF;BsDKL7SN*KubiNsQyM5cU!;7FjMP513R`ID=#UVi}v3a+M!A%AP z*zLSItLhdc=^01MWnkR~?ycufam%TLdu1#x)270dro5Xr@pc*37A3m9$VPc)i!c)f z%0+&JcO|-~+Z4qp6q&e&F%LAA4`m-eD{@v0gR6McH}G19_&rW}nYTq8(ZfPwB#vn^ zh-Z&- z#q;2OjTdkol((2O01b&AV7Y^i`6xJPGDK5$JE0Ly;)f>^Dqqz((_RglVZp=BGZSE@%erE@x2#%E7jkJ$m1Sp_sb>~y zOjd=o$dq}@JJPTqRO$_#Fh$LTmd$)G)A@0bqY;;OX-PA>6n=V`ZjJGT?Z0?V`1kNW zu?uRB`D)VZ@DR1x|pEKqhhMIk+c5CuJwTV4E3_s1?H7 zgvXs%_%hVpMoyl7olj_f`tx6CH*#*U(q~>xQXJx4$16#rqq%O~y0jfmIvwQVBlT_J zEM5wg_DT135SR^Qg4LPXFa{s!@UraWi!P*5-??<4)!$QWS+xwMqs@IZO?!~oe~W}ciV*p?b`CLtdk$pn7dIZJ3`hUzJMCfPJay+txI&)8AO~uMVm)E zbjeTL5$-_XqUAchZ&5-E-14TGnf;OtPs2NGbPpq3#dMIs1JmDE0iWirG<(0v0C9P1 zzbk5|U^e#yF%f>^h3DJF{m=8===}iQ*)Fp>x}3KC*zX3e%l)DPv?ja3!a)G!hDL0T5}*LzM~7Qqz&Ay>h}nmupg% zdmGs6vhVDklq(|Wc3XYdHIboppkj^Z!3~Uvb|NnS) zxy|h5Zhq7V1{@47RtQvS#P!K8b#?*XTAf(K$Jn`Iqq(l z$8HiQqp0F(BQCPd{l!D4+t(i5PkZXhF5A)1ooV|I9$~xnV*16G+Fs7CZ(qBtJ;`U? z80xnz964n9C>Or1VCDZXi8;#_bY=pqq`di24py#T$u0Bf4px@iS?-8`>Lor@?;S+! z7TB_)-MW2ETfLIIKIrQ&SnQT@`r^4H({kb@(s?HE*@4Do-`pKdVr}20!$hEyvP^_| z2LOBD;gubwoTFEdWFi7Qxxa%+?S(mByEJ{>^yw(4e(mET=k*=@GMuJ#dttVHi~6Lp zwa^7Q@29ek%;z#e2ko`^MI;;!@BQ3%DMzRG(2~qHT&5m*!QOI?607CBye@oujDXIm ztLY0lpMQ~bIo9#stHt!ky%>8Xi-}GE*tf9{;8A4jk!jL?k~U^3$9m?&YsM{HHtPK( zxhDm9n?FiQ+$`8fHVfHe&tU<$^O9tDYIvssf$+)x4f5E2hIf3CZHzhWLKtj!N0n>2 zMAYyFKCml0VVyi!&PevI-M6$8N6>Gi9q;e}sWOTRTXzn=-?y*t(ZF7jmWeVThZOus zgLG*FR#xHpjiV*9VI6dGOPe};A_TNU{KT>_l?fPO9j%ImGL>)@l=0HBz|TS@;3W!w zZhlq+;tp=?!Gf1tPaMcv3H;`{s}c@AO`CqscB^cq;sD6>mqOGJdR;T(va)$$ogr3Y z2g4dy$@QE^VNataBO3W2j*U|Wbv9~x!@M;8^WX3BswkL_%&MX@YVw!P6mbP|0JWOW zUU>WaNiM2$mQ-GjajU(brIVx$Yuz;<6)F}yns#aUeRuf`ufW=9Ln3s2pWxFW8`kq3 zQ9AY~I0M5e<;X$Y+4_Uxt;>^8OUx>!(+>@mlj*cEaj@t%XXUi){IXJX@Q}vKR7B1u z%{-S!xx_yB`%YK|#U7wp9vxPA^QhbfnCReA;VHM^mnMD=dNg?g82U-VK(tT{JXszJ ze(+8{YIl%W1IOw_rUNnnDX$1U?tw1(7#_iAUfUR~=Te#{_B;_jGstH0NPfZ-^2y*E zzKNIyTC2Z-`+7}hJ7Ix|EW<$HN#JG0+vY{0sF47c8h z3DU{CNxb8;lR+a?w@kbfJMr}l&%9G>1W%Nq4ep$53+M|E;)Q^%m5Aw5CA1K_1R{p9Dv?8Z{>-MDS5$Rqaxn;uV@T#pgXHpkAM zoiaO>UYO}NYE9{j>%nvlm`Ry-u#p_$TV7{_32f!>lXZlIOB92A$^n|f8(;jUOKZp@VW~&mR5`1BFKp1GOu3V-U*_uMUCB;fXfugy zJEZw?nzU0gy$1}_)p(sxo#HO4`7v+d6I<< zbclJVpXFM9%$tFg=%?7_k9^owsgffV`T)H5XsAvVUPN3w6tB9~bZ`J$3*eJINh3 z@a`msJKrwDE2-gqrak$>OYQhxz9Pc;c~Ze|NxSh5K25i571enWa$*-ReZ;c}Zw`|O z?rfN1tm4|xdCt?`LlHS(zN+r zjJlM2!B(zXok@$MhhAvE@K@j8?zw9>*;11V&p!JSx9ER1XKql3(9>F>-TH;LeDaWM0c6F1LER7HL z+}ba(v{nEV`f2Y_r$BkuR(rOy16PedSP7eCSS6N~DB3jb(#?!AaOu>92yt*%!$om) zP>CY3Bh)+8DlZ$`{1Qi8!B!a3FoGPDi38p?hMJ@g*cEgDorsVh&&IfQ)`n7?hq*k+ z0l1y=b?esV(`nK)JRKa<1v+t`IF51yuagkHb5>iGYVa`+{HjLdKla$;Q4n_WU7>gK zz(J_9fa0|yVg>dhLTBSHFbinqt%jnuH%Uylg9Ulb0Ef3*eNCJH8awhMhqghcMsVkUddP$efZo<8Plh0Q zO}>~H_+{0MgqTjtb~^ObH!oe2hOn;kDINzc8q1)K=tas#pEL`$@P$ppS22cl-g}z6 zd)6objo<{B04_c%mLv;qAU-e=zeH27bW>^XVcj?H?%9EHR~f0yHgBtrDFX*WRsJ2M zTTlFDKrsyHgo!R1_}1QyaSiWAdylK#JQ3b{tKGCG%}fqyCI|4cn|e6ZRnO#>2*f`W zR3r65Mg-&ZWcGXszsX}jf72#YS#1qmMK@iO zrs5Z8;R|fyznU@n%;1^s5e0xvhxz4%%V-kgYRF%Pzq}8|!y!?XOa9blHQTio>n=(a*JfBD+Zvuh8yUBtZzDGv-M%END zEafhLr8H>>o9;0gIHcD!3^)xHzlG{Ljk^hw7C%=>G>5ozNyjSM#l#Yd3Ff7wL4LJ;)_f93i^t?t9wGjT^`aI{bVhbvZ{Pn36*@rGw>PdCH?{)Gl`u z92cj;#a5~5_G!sTB-7^&=A5Uc-?Zn+XWE9Xr3-`Adg@j&~)yWY`0@RvW(Hf&js4r`pFKFkrBmBej)itPoq?0=^H=_kI( zeI=LL%GGPxS$dY8HY|dS ztbuoi%uIlK7t!ax_~rJYkA8~V*!Q({n>aQ~d?&ar@t!k}firZc*oJ?Z!M)qqFERnO zci+DDz;n;EUwaQXz`y2RZjE2Tz;`8=L!W71`qDSsm%jWUUxeY<(GqxZ0)p-9i;&q| z2H{RfEoQZxk{MBWbs*CS48Bh?Xg=BA{`%Y7uAMiq7`CP@rGG4s-{7|Sefy5LO`8}@ zFJHmxAH2ZZ+=WY7`IbK(v;$u7=LL68UY%zGWFBSy*{7dt%eYuz_pLW`F(2ifW_;g) zBMjP^gIK$YKKP1ukv{Y(Ci^@xCx1)1n9f!BIj2uT<23#CDQ@XMRuiCe7PXg{c$hnf zFW<~V@U$}*&>`#BQNNH&j^3R=fd2yIvb;U{%wz4gTXwWp+<8a%af`owyRSX)wf5+q z$D^wbW`bp2JIrLpj;%~$Fh+TnvasiYC&^TIpD|gpVx8%vbK;4!JV zh36{E$ z>=wIytOZ7l|Z>TiQswUJ$v?~Q|q8UX(O)TJxz9c!x!ODlxyTL zOloB74mW-xZ)fmTc+2uhEu=hjZnEGqNNN znj)iYu;(G|1YPkk_-dvfeQBd;qZV+zJ;40V~CFmaKVkuTvRKg;TsNE16y zqey_MFDPH8xle#N*w%Epm5gcyU%PTMOrza+-CtaW>F!2*$JN7qTMvzIos?f!Afp6$ z*`f1q4jr7-IdFEG@>~h*Zz&bMzz8b@4{h4RLu@0^)ael}qF0s+ZHKVZQ0W-TwCwqp zv`G(G<)N*occ2~O_+Med%)n3ZT>)`bkC}NVpy)`G&{o;%@)*+!L#2{N^iBDM2AJ?4L}&%TOk(SGXd3V}9CBxEh)O1Hvfy_1 zrQA5ZkX6c;9)GOevh{|xX!W|bVa;YoGVS8tC)$ArztWa78L<16cNwFde&UICaE0*4bxy(&9)&;mCDc)}Sgd2N%qoK?rW?zknZdW+HdhYsvdza)JV z@_eq7`*i*}4~aj$M#_m{9yQ>R{$TXbF!^Geko-Xyk*UPOf4#Lk!L*S}8`rYZxMt%f z2B~M#pD?e*^_|Q_Qoa-DUubxh!&yj>#!()`UgdXsDXw^t(JUyg@Dio<2Yj|Y`D^kudM#X(j;nw%c}WX#f0w{D@4H<#~$BwVJ&J~w{BuWgVlLt<`=R)|AjBNfA#Nvx6Ne&WZg!Naq$`K z3-*VZI5^Lq^x8%1L@52_v!~gqaEkj2PPKRc*z4LWZojo{+qSVS}#cpmT}9{FE%4HQj*&6$uup%GG}|_uX2QV^z#=9?jvPJS9(nX}@?bwZ z3z*zMewM9jN9eP#<2RMSVn!LW+zL@YUOxcldp@vNrV(+3uGE!%sU5v4BPQPZ4W^GL z0@po9?;yk_&gp7wwhouk#8(_>?=}J`2*IKn_);9ZXTeni-x8=5GXUVp1-PRs`^wHor#CJ3mhUrj_DsJhE-vDpK zR+-2^t)e>^FoM70+Y9gHUm6Zlr%*)3@%)a1hLb02)xXZ`yX{DNCJ1`cVn8phnhdDC zv4P2|wp+tg6iiqYPqHHIpqch4mS+i=1~uIws{TvAMTb(hT;x{+C1dpgwh)PwS6szg z=Zi#Dd4rb`awF+1nVJvYvhGBSemM?7cu(VG0>^%qC(}mwwISEJQ({Yy!OuN5IrEy~_;e&%$ z0`x3^(8VP#(>$qe#*qfwfHQQlclw6*!L|c#>ymZZdLVxDxp*AM(LL!WE`R!oW76n9 zIruWn`YDaT!i({Q^Q@$4OCF>X&ML_OXMlTNTQWlp85KNO5QKFpeBx=x z-9j|xx$Nqnip>kt`InM$2(u6WRxGz3h#jv?=hW< z9Oy(C15KbEd;SI4OncIYoQ`ws$;mNg;!Ypm-<>gaV;qX7%SYT@W>=$QOv|ljM>`tx z!Fp|*VR-69Nj&b3*SwOP@l#GHGhBuPlOBaP0D0F{P-ffJyo3+v5qZeKL~HYng%6h~8verRf)k zE;4{v!nxdiU;JcSjIP{x%PZ*wFK>sQe5$?htuMAS&p*lMp;%pf>>KSk1G8g%J9_Sm z``R)F2!8W>jyp=MpO~cYS`76t7$0g)_u)MwH9ASKdd3N;m9%q<7(AS2hnaHq?7Mni znoj6gw{6SjrHvoAwZ<2Z<=#pDZlb3cKt-l_j%5XB=psKC>{o}DvHE+O&j@=D!>Fuv zB>x|ND?ZcY(=?Vn9(j!Y#xhWtRg1=O+LAMQO!rszGciYwv|EcAaBbpVkooKeT(x$6 zJAU*KN|jLXgtoMTK#%Eob*J64Q|Cc(da&jkdq#=l;?SA))*pF8`{|#4cU#Gz{xCaA zzV**k)!s*%X_rB+++G}6?#`fcHeIwh*m$X0plaI6~p551`=o?&~#|pBa zWHZIA+`2vcU9a8Ue*JI!QoEBu{dta<*th-q*T2Tf|Fij~{5B?f?!MU`BPr!v3hSkb*$i#ms9F& zh8chB*ZwoU>AsU=0erT24WFrFlI<|}rMQ!2-MVG$Vt7y6$*TJw{PBmF(AdwU!+F{^ zcvP^y`Fy29K7W>DtEbM;k2=!+?yvqb6BoC&)qG80-8w!$&B8bHAMFxt_-<(JzHMjw z*vCH8UOIT3qqp2{PkySadzo?E;C&}_wc9xc*y~m-Z9nt=cePFMvvcQ-4BnSB;BM_l z-t@{W+#Nf9s{QgWwDxa*`*-*f$9}#)e?vRUXY(#2qq)A_S-{}iogXKe5Sh!_d%sFD zm;AbI*R4$U-N8hKeUU1Lg6}_Yh@B9~h$9#Kk-w7_d!K)a{AEY4$9F7SOze1sO1)tb zj4ra^#*8f8eR-f`%lPVlhq3p-ZXl@C$EX4zzUHN?GA1&@g#ZUFz@ZsK(BRzQ(sRER0GoGyiFa?08n^GaUq>i7&oj z^KE1eb_d_F=qa48z?VG{6Gt4XGAd&lMLda;fs*u7L#i>A7q>9G-P!G$Uby6d+rfbf z#6j{Ctkmz_ySJ@jOQ#+8oQY@4PhFT-cqHJZAPyGO>8eD8R%oDPZLk$szc*k%Ul$Oc zx3s$|Qs;j!=8`^d6t_|K!Y4bUU{4vyAc5pq$L;)i3u!to$XcE~^PkQc%3PR;51R6z zz{VYLo%{u;3z-PlVS2|kphR_`GRMnbK$iRf?_|D;z5mAOhb~Xzn^*poUpk`r4OwCUmDh&J6S7Cvx7>0Id3yxeDyu;zSUNoznI@+( z&t;n?Ln2L+$0V>!VTM;VHgT6v$J4`wo$QoVc$L>o4n-!)SpI~Twr}E5R&*O?+OO9H zQY6#j3`j?ui@D4sZtcl?g5M3 zsk9e=`dR;cchk#&ZtcYjod|SNw;R^$t^UG^SNuIrbeQ}~7aFG5u%tUYf|J%>()w%q zdHd)*0#d?N=GKV%2OhU!xRYkz)TK(-00gj;kjAmzD_2d`GvP}Q^>kNS^bhI*mdM7z zukxzO%_t3q4NQqW&@vUi%cH1bpJob1Vx9i9;F%5)&yHv&Wane zWZJZ86BC1nv&!RLDkkgCYZ7-r(D8J1lj+y4{KrNIka(K6cDziJI1JIxL0fPnZppK! zJ8%O+VQqh6DxmB$p2i)hhL)~g#w08{!|PFbuG_Y@-xDL8Iyp3HD`~NVt4LLPI?o-E zG*Zk9X#5N@oHKY%%}|K=`-+%+Qx7ca`t_)KPa0__4xV%9AeT(TCFqbfiF81`l&!Jz z8MyBKvp;MveEF;G(jqPfJ9VtB;au=~+pwu4?a7b*9$4nJ)$>-;p+}dnYT8(loWrsv zYn~w+)?rH773JAEtG0E5Q^8XCCj4aF2_5p?I_(#SoDlRlo@F7JsqaWL?)i*Dtgrsm z`1Uu{sdAE|kKm9e@xeGZtq+n3(?H>j7l{2j&%#V1oMJ$Fg!Fg}k=09Zk0d%<(!kNZ z`&$lXnt}3!cS_!b`@6SJ((m^Z1IRQb9_j?ungQM6cI?mrR(_}28-L^-?atl1+QW}O(e@oW!m6_i zY?cFc1$CBH>n9il{@1_xYwd2%ySsq&-~-=iU;6wP+ZVq4c~+Od*%ncLR;zG z*WSsXe|h`hhdi6>#2n@2lIKGsoNN6-yXs zBRlA=*|ZLMa%6{zwb$HxClkR-+Q0nQ|2OrBf&F~$<8YFb2?*~KVBCy8a50e2VIDit ze(|sUT-&;lLH$*c(oaJZUpuO%@w?%7Ma@JB#e*5434*b*iQoC%GEGdiPBu=GVDOZ%pcBSHMRZis}yAs(| zi7Y8JS(HUdT*L(=KoSHwP@XY*G8MnG5_zzUmS*GGxe01#rg9Y-qIYvo zk`8Zppf_ofOie2kaseVr(xZ?jK4&Qvva0~@?5puiBW9|h%Xi~OH%?eALqbTO1A%+3 zBaD1>afOWnvv<$CjNRGvr=EI>j?=>{>=09MS0VJyZf8s-BJxAt75ptLw-y-g$-yZA zIdkrnA}-BhuaNmuaN|!HX|G!re7etG_-Q&9^P=+a;OwDKDxfaCbR~lEVksstT1=q? zCV4tO%a0fp#G{`=fv5Nz1{>%Q^m8ELqjB;^enwrZo}Eu&E&7)8qwxqlmJ8n?iGP%D zRXD65;;rS$iwOlL(@ZqPZqWH+ovO-u2T074#%cue?u=5SKz zUQNIH`(2&y(TCW^c(3?PBl-x1UhrjqV;_@>Rp2ns#1WfXCr_>K z@f}{~$^H{#U9+mh*|e4;vI^;}`{jZj_oREKfON>?U{inxJq;Hl@px}xl2GW$ej{j> zruY_z{Ays$4|x6Kw~fHp2FM&oNGnnsZ0TD>)3f4l0d(NTuYN583;Z>t6>&Laf!{vD zI^o_@`_-|lqvbMJ>xF@@Gy1E(FHIAwXcNJc_(>`oE(AC9$r<--Ihllb;BzoE%RS2= z<9q06=3JQo;gF81^K zCv|CH((vUNqu~o9DuVV(>a*jHMyhV=$_fk;!Q>z&TDYGBMfXtjFy8YXYigU|CJS#O_Z5>`%qp;Ul}6mMw18O zmUEHMR|pGu)3Jk#C+|FijO)c&E}`$)&xBsxwV+xr9dV#-Iq#OIferoUWfrBrn+oCC z2%eG9hrC5ml27VNGd9?)r&-SJOsWU?_Vr;*g2%SsSSq0?3RQ{j;_urKN_SQSg&aE3b7;l0T@4L$73221=Ze-H=h3S|9zx&oL}elt;e)xpMHO=gPOg^9XzSkCyWz7t1evTM>)Va&$@)$Q}v6@$7oPC=I-;H9#dhq^x%f0v9gAs%?HO4NM zuVTde?&DuCFJCy#Z6q^gBj>UFm;c2-DhKx8TK4bTR(|$F?<}AG>_g?uc~(mzYj~xg zXAtx;4l5^|W%cfdKlFCCVBAzzOkHI5eySWgI8qKDeyJQib|kI?_4Z`r(Yb2)kR z7&HHe;>;LzlsoUbtK53)t>wVpU967C!^u7Lu$!|4;?O+%J0{w!qama4IN2@aH z_X_nrgMO@jZ-`>=AY>1a!;0MVn?L$~d7OQwZwO{|tTR-W(!0_g0YQXQ90{7HW1eN8 zpbbR?Ub9Hz8$Z7+IU9swCJ|16#u*Hp|Dw@|4B!~>1!+LrQT4FP7H7*h;v@osO^Ct7 zW`tR{;v@KO`PsRd@0ew^T7lY?4VJ$~ z7UNlN8h@;ZK@;DAh09zAWsOh!5qzW$XW9+Tm2@!>Ia&tKI_n;B3?kj?e2uydt+o+~ zv<=8>E$hK&{KS>{2SL0m_+=aD#8uy~{{)BmwET4PJiUCxUw!dg z^qL!KtWH>+G(%|OjC_kxm-!*{5gzSRxabcE<|$+t`mA?BYp&X`Y;B9x`JFV`R-hu% zvAs~vv?E>ht8v6OGM3D8bi~eLD1DJHZ}CgvNj|g1n&5kY;i4LUWSa1p0(7lQqcl z$-HJ=s`*X7gcV2pNgEN3C#vWpd=;5>kw+oBeHeMR=>KLPO)Wb8a0|B}mnnbqfHz>RY7T*|*;a4P0nFUPt zO~#SlcuHGq9JL&9M$*qVOZjP-k49fozH2($6NXmUm_e z8fw|MLVnaN|1iZu`x)+g&^pA<9iAQ+|fIJ8K@}(B;uHWdkRgEB{%` zdN{>Bj85R1NAdRjhha{r_jL6x4qwA$z`pBl_H7T9m(QGHd3`U-tD;J`SpOIx>o6Y|UoW^cbycJ5&&8s%?0=Ot_#o-D`Ca`HQS;;k2>j3sZpWgGR9 zGbC74J9-tR5V`a$itQw`zg;M|Q?z$iaSU+=#bvf;4718<9ee9NXl{^tb`kl~Q|N7v zy(lYFD5D$KZ=ii)d}6Qp3r{~?jvYD7$@s_11Zl3~6!<~*n0H}dJ#+eOId$R)w6IEM z4gDQ;dmY!(of`&c@X{`(kI5|L@71fpsnKMZgYI4`U;4|hV60%7I(pLnU3Zt;_xG0P zo_MAlJAANw;6ooSKl`_TnUz^woeF=IrzbIT^--4{kNFRy7s?h^cX)xRju~JofBM<-h;k|EB!H zFa8Q=18gQ=ob$w1hr@@Dme~o7Zh2s!b=V4H-+zfSzUaux8m_>*zpGpb2c z*jS08j{=&7**U1-b8RdZ9f376UiDQ$f6t!1F*rI1x#W46z0n@vVcH=O17ky$ zOgq3(WO$cqy%l6sf`m6bXeLf?L%V#n0fdrA$}XknCxw^5;dTIpe3kc9KD>egvq>n= z&gN)zkY*L)89F@g1(kNMUovfH-zBIe5Y@8iph+)Ds^u&_3NWUdgL@-bHF4`zaG_w5 zelOQ!$PX2gewN~xmIj>^M-sP0+5qLB`E>A*NBPV>kntYEmi}1&uukgd$^L6NUDy3U z(ZNLnPi0ZQn!l_Ukh|0wCcqNcsz1`zl!s5tGn6lx+BoSBWuxtZT-yPFfATMRC|G54 z@D$L_?}{d$U?;N1fZ#HKNsnnN6r~cVGAd83FB)?+ps37yYr!acl;Vs7j5Seqv=PIc zku~??Q_z$~^WuMTFLs%peo3?6#!fi>;tv}13V-l4!HFt_9pdQ?oKNdww2=T!TC6{@ z@}L!2L|G2k(iK71{mJ|ZVv3ch$Z0FT5gHkih6Yqm;`n_HJ0h&}Cus~oB3Q?LPrmRf zUjlK$#czC@0%;g*UB%Bhng2Ang#v_s)Po31WkzLOSld9>iEJ;Gs_IvHCYtYZ(~VunOx_JT=_-{xeSP2V|*N_b6zS6KJPT0?s@J&EPPXBp&&z{^l$8+G3o$ zz#y-Z=GC5&ruCXw_95ameH8-vD$c+wE#eFp9F4b5KS0w7R^Q_#`DS3^@~smn@ru4C zVUx~UBkW=)j&Q9sn(#p2y8(%_2{GX|NxVhs@za9nc#)8f&*n90%S7#$dQr;S`M(za z`|<&K;Hv4yv)vx72fBc1@=`%78{|v${nQETv@5P+T!2=?ELY=KgHb$*T`$lV1!Wyx5BWc(@FbjPD4L|Vn01RT6XNeT=woi5NXGXKnxUN z&=yuYA{IaLnup&>S*x^?wy0S?+V|-jtS64RmttOy+@xWd z5WFg`P7*BBS98iaVqEYR1r##tXYbrpdHC?*@=t#2H-} zS(b_0c5O?{d=Cz!fqI($U?qz4!~_RDo;hERA3If!y>x;VhF&Mv%~J7goPLf{jVl?0%LR_~Yfs>0$PVdzKTcQ)v%YH=FSSb?YgV@2i(DvS>;QTRek`HC- zxoHn5oetxZD_~cW;3#{)`!J%-PA#w^U^`3Phe9Xt6#Y5+m*Fep7%sSek8`8svOJuG zrhX5IWIVn~-M<1YD_5^7!|p!^C#;18lz&eDA7VNE4ENN1?Q4%6_=7D}EFF6_i)QNKb_>pq#`R6&M|C}r-`)|7~__KTQk zJHSKcX6LU*DjWtx_iBxx(Wuxib;fPEfCo!>URzwXt8T{;mM{K7uoh9^XkiRoA)wVr zNoX5jxoRP7lYEV)@^t$2>2mz|aZZQ4E%vN))SLu}}ApnCY zW}o4Ml~VKy!wyZ(B!r^Kx7jgV04uKfs}PbEjIqymO~^`2b>g3K050f&qb zceSU8;urifWeKwPSd{SsuxPus8aE%G5PjiIP>h!Tk5H|Xz7f4O(l$UIV~J7_nXmU;ePCez8VA>fBCw=?kyq=(_NQy7yG&kM&;c1=Le-PlgDnwFj_|_&WHc02 zOrlMzm?}0ys*@M>J)eGqBAofq`OG}TXQmrL30UEpB5UAeu?!u1tn=0r%OUCucx^w{ZI${cJHK13<;DLh+6v3r ztR*Lmn^TjXO|U9%S{W=XNvDsTnL`PNwvZFVW0{*JgkqP=$9Lp20>Nw96UJYTH;z%# zWhCmf@xx`iiSIxzY2rvHxGhG$xvX5J3H2%3+%&5iCQaTdLFjVT5LL89^;EfeI@b2x^DEW8Zh61AEPdsO3qkh;2D#vttXjvZyp5&&i)n#4C_xL6k)wSQM&kyqK zzy{A?WzhM9V7y-3c719?Rera9e3Ku`hgf{qxQ=XG6V~#``svK{0;@czS>^nt^X0eR z_qOuk_rI%bUE5W*^ld0-*@u4Q#plZjmcIA9D$7+NT#wenN))$CdI+m>A!|p<$fa?X zVV^1U9Q^iEANW9d?wNxaDA%yclN%IPa$@|%Fx!h>F0a4u&E@_F-W1BC_sh>L94{A; zZHBKCR9$7pR+E(7c9O>`Rxgpx`p$g#OsaDecx%`>1h@6YIHc zp_li|7!huJ-5urjJMJo{&YUY(QNpi!cRhRed+BH5YPu+u1y(Th#;NbaO+f)zlR{xin$qJ9PV1$*+;r^ zV8_1|KXlZjI-kbzuNng~W%0D%{Hji0g$l2}@b3462VdZNvE4~4 zh(oZY6$#VJQZkX7UZx%?r7%Ec)IZ@<00_DONg>>D{(&ci7y=dUbJ?rQU0w2?es=ca zaY<{?ZDm&}H4Va?saF|RsdFjRO0Tm+$sgrZPKgMi891F38ZWGdO+NAT`(XcbZ|7t&(@+;wqQ1d1~eZpUPRO`voG+)UdnE;n*)i_bl2@s!u^Za$uMp|_w zq5wtOX~Z%<0&r93EKkePwq^V@l4)2|VQIGs@fpXb{xz%Ys#$8NTi?(GVXBJGG|2*0;8(@n`ngURu_{uXL}9L6BHMv5^eRHJpCsltA5me(qrrh=|`&P``5k@voA z#}ezW0 zWsWvxankbhUsN~^)v0=mD^tyUCM5Np3esdf+e@c_143umjT^{KpmDy{J>sTV(wjyu_hq%m9*+RjigcgD~HXGGIkW2`lrQdOq(YB1{!-g>Oc!=Aj^XKF2 z7|T2QHu7vqJHcS~v!*pk)<=s*Qm^FHFrO0jS9Kk6eN7(m*5UtGMZGv)LwHBMso^y# zA?kaA)vpSf&*gkA-S5R2Hz0Yjiyvd##%)Y)ZQw+Eq}?)h>14Td_7MB5r?~D6m;qOs z%$E~q&X&FFIaoQiN}7^0;uz70wF2WzFU!xjY~EgO`S9(W|K#26FPA5uc%1&Bo73!{ zEdTs}`n_`BJr9)OtCQuqBTtp@JjLO8moW^k;;?5LfQBFCJ(cncmq*J+RtId~xu@KJ z_Z?-^+Eu0hyPUX>a(?R6%Ou@h{^U>otbFQIf5>w5w{bP_NGQbPTopH|5=`Cf!uYVD z!c0BuMv;B-=qV1hyHxIZ-S+aDC%zFq#ifBZj`JMOr< z96WZs%#OOZe27V{tE_xcS*J&_vEtU!rVhPyw0!&V)#c{h>p45%b?h%cic#RU*uTD( zL+G3=eD;~=%HR9-UoTs??JSRc`)S(AYPK*8aFzhuWtg~e!p!!viayK!(yLF8^^TP{ z-1E9PAbW%@2y54@<9vkiI4rLhI*%TEsl4-@Z!i1y?O|{IWeSvjn7Gm3Qn;bq+n3Sb zAyJa=^JULARt~t;!gk6G`ee6T3n)E|CAPnlCytf9yV)lJvF?*I!J z;U>5;aj<_Sr|G|=Jn{JB<=p6L^0tj-|D$aG!H~hJ`71m{pVdPl8^C{h4CtSsT+hbJ z1pAe$$cL_?%z*4+D%Q>A>Nnm$_U;BM_7qk0AkoxYjLXJP7iTZc2;hm()p{F@w}SIe z1;w7+0=Gme7Ev0t?K2Le=|J=B|Ddz zylF|3LVZ}vP@+R%0>m^GrmIt!>LFogACRQtv}Bjmg%upw=&V>CueH%->^5e{J^LHe z4GR3GQBH8pg$la+d2D3eNR!!rJYv&V!;lc!s{n!qJh&b~;0Sn?YF z*(j?}7>Ycdj?2o;uZDm)Tu)^o8ZAqAh%YZ)h98FDLco1|LLPSgPsL|mVMs25SL4V-*w_)+m!UiqE%$v0fXL(8%9!Sbzb&9V~S zKXF9=6lrDI*YAom@o3!1C4@DO1EB9JNw#h4wdYj0qQmxWnjs`pPZhuoH;!#gf1QJ> z>6o>ukR?nSG^M4|W4~kGbn#nh28VbI3&SIELU9u}?_PCf9$cy@z24KEsf#<%wfNMa zOwT31@;}NY{4=h2lg0!VpJ`+*NWUyM6KWFUVVq7EFqx^y+|qENGv}SL{^q4TSmA#Oq`alAl6M?D0zZR~zq3!2zs5%aqpk^OeTaI8(8qh$ zaq2R7j4QA>6FU(p(hx>NLn5}Y6 zT-rsBBz}Rzf8q=cSKOop3EhnMF@sL0+>kHIz?+Q8_n=WGfX6YxRWU)IWIG_U;>zo; z=GneB%Jk*>d)`>~J@{ZLEGaH?C`er%8f${a&%DFn81us~X4~;MaY4v)n-B#D5JC%CDGr7LHj_Q2`(M7P!IJp2;U_YkxXk_ zfb?aCBVPU_Go&f_uV*E#11esPejO(cokdk$h?x~(hkp(KL7$nWYY}()_%8q3Jnsxm zdKddtsw`99mk+E!5$u75Ecakl$b8wgX-)a#PkpxBbNjCH=G(TGef##7kAHka`RVbg zJpX}qeDUHHmRvty4j+6Db)b>W0;6X}VKicPdicsj`O`oDLiwo=zPIc>u%mqNr{7)1 zuAD`#F6Gbu{in*?-~LW!aC7a`6jrTvm-u*r%vL-lj{|hX6A1c59`~RxE|NZZ0+?$Pk@+Z!mE>Ax5Y#AAyWR@8t z83}7VoAc}jRw#^5xD@_dW!Ki9DO)-0?JaM85GC_!oM8XR!(SwSm&^bD&;MDhD(Gd^ z3>UhjvP73UGsa(8!_4q4)&GLe)dmTrLqbI zc)Wb(Q=cjS@W1+pnK7TCJ?2WD!p#5=mEZoI|GK>8EpO&#tqbMA{(a@b z`3vYj$QG2pl_uJWcp>o=+iU0@nTT6m-tfQ!?8{$W&av`i8l%r3=PxLqKKJZ1c zSb6Zlx0lDCe3}&y7g!ui2j;Sh0^zLylG#9XH>N zSF3M`Z;Ic}*j_INKSl`RhEiAKH_wVO$AOBa`nI~_Hgp{@8jyhCy>@DWAzR&S9JU>dV=%%$I>oFqjUd||1}YAP2!&wt<#U3Wa`6Tvd9%{Gj73}uBF-#y?z;|w zq)DqPSRpRpXPC29&O}6f(h`SxiP8Zuy5*Kla!*C4=UJK)l zzj&ru2CGt^GjoomEbFF&xWdvK1+5{hfwAA21~kUZ{*IkHz%d{DVNF*dT->p@k#y?y zc5>Oh{ieN!S(m+g_m+#SY`AdoV(jfVu6eG6Mm>P8C>I*N1?67b{7#{t;PB6V;ap*3 zCkB4=B|Zhl5tcOR{2pTF-iEHlKbD>&s0lC43KAeEd5tabt5q{3i7$i-9uXe2`VLMz z55E&U=@pMoc;BQs{qSh&Py+#saRNHR0zwZWTW=b~0<>I|KlEr3wj&EA%Ce+xNQ-~7 zwvx^l^A!P2ej8qyPvcu>b%CqN zU-BUR!uVu5fCUUs^I%>ryFM)8R}t=9o>!Imh!2EMJ9tw_rBa&tCZ81_K`mF~wLD11 zlyt49bcnF=h_a_hv#iovJRKlGM?je9bzGoq;&y_Wh8R0zhu|+C>YwpC@cS;mvi?~g z^B_G9TRPjh?byCYm%L47-S04}!C(D#QSYh$)}i{Yzv1#!ytda#uF7Iwl{S-Bc>6i& zm;YgqM9_(}R5*aIb1Ma$0$yrh(?_u{gzzW*Vgm1nhB z$Pwf$m;YCx()uIF5N0SV6Z;9}jV4dE9oWav1Om$antceCGoN>}y@PPWvR?q?s>1vJbXy*mfDi^z#L0pOY-g-|&>S zrXZY22Rm`;!v&80^R^S0!_&uK#YoQG-AvK3WVw{HFTGg0P(b=jBNB)xoN7-T+RPN~ za}Hd&SJnlwv`ZN!YBJN?@GB+(n3)`%nk^e&cXR38v|g=>;|Scg zKRRl2V_=YB-e!5}QeTz(I8Or_ z=fG__Iu4ACTxPkm{a?=HNBuy#aCxcZL2|Uq}~wK3;?Zg!;-v!iXU+- z^=pSNddt?`5kVe&k8u|v`W`++TT_Z`HgRflHLRj?Gq=h-+SxM^3^Y~nv;5| ziH3vXk#kvC%`EWga~D{i%|U7#r^^=}dZ@hVjdzwezx7S!zI*Rv`zZUrS?cc6_zM?D z%U2(Mm{Z&zM#;wr#NPTz4riOAQg>7K$`mXSh`d~8kNNpa6XnpcbJX`0oB)4o`Q=~b z6nK&u?KdtfFr%^Y_3%=0gn!(2&sfm!C!aR_4t!7S-zA7i`eDf@TtDS!O$zf|tK z>yEPifm_SUp>^e5?|y&Tuwi3)&wJj>3GR24yY9LdrE^U=d6vWQP(+`4_IVW1v*5A6 zqBN*`jB4Z?8JWB1d%0rn^y!P`@$WoW_UzooEc$!cGB8xW`OR;H^7}Dp{qRRVN*y08 z!{^vi$#V`o9x!;}@;Lj?=^t2~?t=m9(A^irM36R`}+r0?3c2~{-Aa$ z^*vzh{X#ikApTEWk2azT?gAf2?w$&!i zdsIlCc9<$X&QwJ%1E#&r2xhU- z<&{m=5$l>T5+={0E<%U2C9O?Di$2oN+>v5@_#0FL7v-)mo*6E(#v{BN80Zr=6Y^aP zE+@jW62z4!3g*^}K?eU!zNQi>WnA#Z>J?HqKG|BHo zyeW!HmyhNny%zl@?nPehk87eeHQ*ZmCY@#c+sGEb)%v&Cclod6MXi0y!(88&xS@3} z#?fx`@cTLlBK=p$oAInu_Epvs|5l>RYiOKdMk(;p=3Jg`+w;1nAr5MaYqW@4XJS3+ zU!GWB-D>93K28_?vwboy>uqftm8kkO+_Y>*_91C-kp5ZroqA}ir?I;n)%wxxGInrU zyOaY~F#GLlcDk#en+NTJZ`0*Z9){u8FY7mPVx?kDK1l>dI$DtuS;QBIfj)VVC%Vq? zvVEJLMiLITDP8PEehKAg^4TX?ev1+VkKJoN&Q2{H?$K8)g4bzMI2t8Cy+{wiqiG>=#z>C(DD^8fuz+$e&nl zOIUU0L06x=nl<_E3IuP+S#a$%`C7epC{`58OK0k5D2qOfyb&Rc8;sfJp0abI!Rzow z*+XpqXUs(jCayPLYZunxCxs+e~bKEzVUJcemXK+aYwtl0jNdM&Oq>{=CWeX zT;`X_>N@?>=f?f6h+; zD!c=`_OLo+x*R)slBMFC%a)Dn;s&0xTp72CQ}yYJ%2^JgJHvAPFrIN1!2GOrm3{9R z9lXLXPW4~Ko^}o*{-b~Q878PcR_?uPAI6I<VY{70LRZ>E?@cjqvfR& zr^-dH?z;Q+ z^qVZLr+wPT96NidJn`&{<;d~V ziSPrsde13Iy=@t*|c>MdyTmpqS#laChurajYqqSV=!TG zuu(dwI#PwObP%UAI4nO0kUkK2GcQ|piJI2Hl zDG@gY{lJ00osJz?3=RpGXt4StTsWYp@H(i3fXe`=0_eNSn99F{vVU5tz2ZeIL0?pE zzKE-j>4pn0@&J!gsTV{}(I9NNG&q;cIE&%_K$U%!B$wJdJ1wm$oYIl79(b1ut@ss+ zRJ6qeV*(?9SJ!OdU=U~3T|%eukuw~YSMm?FB+@tEVSOYI=11jS9)==8c^DQ# z972M^paK;VO3*S*CwfJR2)Aj|CORcg6ZLu(XFe1fwd{&7c`P4@$X`>wJnVS%HxB=s zXTFO!3@4;5ot@6F^hx7`b*#<^26mA(5S{TNEJEsAJ2dNcyMBZr0IMJ9iYj~T!to@eJV%I?*ucX?fz&oH>dozY~WvF>f%=xSslfUgRQCU}Vbw#c& zu@{ivS-!pps)k3Y2q%rTeMGviz(?cPatx642)d=Ull~@%N7A0ckeSZ(GQ4?TOF6z^gtVE8@=o0_$C%X|H9*toz+O=zUjHBZyo*Id*bJNqK zVZ@0f;IU&=f8T2A>H;TMv&Yi$lKM8mxOSDX$qE+dg%H6yoY(win~C}twPu#tGprs~0AXl8#pqdwvvCE@go__4K)s^1J`ZZKfbXLTi{s9!-s~8q$ zIo;ouvl7K#oruI3|1=t|rJtNE-+l7MXe3*=tS>v5So5|m$Nf>{>@jBGkDWTla`f|T zS)jdOWM6?2t|7zm)VAk%?cV^#h;EFO8bQAD(4*z(kt1dQ-i_t%yKlh|vAJAfi^S+C z+Y}!9R(Xt-0+%jd#Sdd2`al;3O^r65MY4iEVgjQ^H|_G4eK(hX_5XdLY(}~M)nE81 zD}zeeaMSj(otbuxq#6R}>5~SbV`O5sJjTI=-+A&G@=gCu-o@+v^Ol!-3KBB(+yft| zKeX!!I=oHXPVjS|_<8yUw;w7iX!M`O$a5ARusQ)lo|BR4KTZHBqu30r_N@t6-j{0{ zc)upx4N>e{TwR7`GMhFQovd(SZKk9`eO<))MITuxO=RQi{7k1u`>WH}_Zkw&W=F=wHX?C2DTRNipmP-08%YwAq1l|J6Nw`X_*SN`&M+$K(!P+ z!i7=64COK)1eiJn>S3C6!0;)ENwwa_Ldo>nAN6sDq;wUpSY$ zICHBaI!EWa9*b9P6wcz?ur6P|92Rl$ym0Vf%+#y+yX?jD1B6%MuQS7u2k=Rkd5^}4 z;ASTi-_WQrU==5k%8SE?k3@qW0GCc>Lsew9WrQo##5~F%z$;IF++#sp8K`ET!Uu^NJr;&cy(4%VW}l#Nl;V5Dw%c?!E>1x z{#j-+({iyRlTQ+F+Tkp(jz8;{`O;69^jgmOtzYZ4!E2cLS?u)74m+2%s_2;ym9kX& zEO%#KvrH`$Iz|M*>NJeh#MSrCaZwX}_KI$(%pZWz&Os8b#;?y*3 zXF9_TO9NBZIsNQJgL-KXNZCgoc#l8h0B64`$Ly1$y+>T@PTts|h2FC{RJ=@E=e0o< zr{Ct~`*)^sZ7fK{bz)DL7APouHoT zb!%*lD~%W@WTU6XPqRg8kkg^v}2FrJvM1rtw67LQ}T3Q_G}QuG^dbdO3%ZKX2RYW!n#X+dYJC zetv?!=qj`AV{wMoTDI-XBQws?N8NJkZRNt*6XkFJ=07bTc<`38cjryfKMjG?v}b5* zqvLEDn(Kv5a!%d`IMZs5>;5#1$6vq64n*7FY!Ol96qf3fJizMD_Qt<+ji&68X@Ki!nf|Y-qXa>SB+HiU7zIlzXAmI4Vl= zMQf-EwCTI7)x0?Sb%h3{<=k@tPMyqIdD9r?x)13#KU&fi$b=gn9wyyP$7ME#r}72G zz^k~YP)`RAyx;Q2^fVl-U$;IKdk5N}0~&qSfmdGCVlqwRhJgiKK2=g(Vq}`JM-!g8 zv`OK>G^Xk7OfwYSMv!!AV)D^hK;S4i6?@^$qn$$g-SqRjD$(&ByeEt}e(Mw=Ry~PTz1vin`IZy-L?tkM z^C$h9(1hs-j#q#9i@f_D_@!I_%5&c16Hocj)GK+Ravb#Q9~CMGw~V2_(uT2Z*}mmN zjpwuWMHSX>VZ`gR_AlZTM!Hha&Tm>pkS!a`N5C|3eHV{Hcg)C}1@PXoth z*ZlAjaHbcufJ^vbO@w6qv~DZJ6BI(7??#O_-L&VZ|Fn0VIR0vmv|k~r{*~NL+>w{+ z(PYQZ%tZ~zXP|xs{EH#~1An~&jghAs){)oiQJefEQpBUa2^@oYn?uph0%-k_$62Q+ zYsMdA*vH#P5itzPz4p=ghar^Aq=$=fC;Y(shZtPJi0Rp6|;@z2nT7t(oC^D1_%VC5>wDq$P;*hj(~pP%n+p)@9%Bw^#Tv zy3zl84WDBsV=}XllZ^j!oQ2b`Vg;sdgk{^PSQcm}GYHaC2>XtG?k}EX`F$w%;ObT3 zif$BG64AioUV6&{K|-x9NVE(jCZ5m|d2q~#xa8EAI8l$l4kz9I>8uK($qX|?i{agw zNGA)NWU!3gVl$5=Blgvk-Q;BthkKYI>n;Ubm@y z{>zV*FMj#+8sbmryr%($-!B$OEaKK0YG zr2JVdLRr)AFAS6&2kyq0GgcmZ;dI%s2E}*NuCi(i+rg-BqbT@e9D?UEd}pjxY8Nni zbz!Ko!Yz0X3`(<#;4JliHGAH7ZrxIL@7u*{pv%m7kCl_G4De9AbF5M^{+e}c8AXR3 z9ly*<*r70l4Knr&LYv!1y$;&#IHp%nnz!!SUp~HXKZ@+R@{MQCu#Ep=?D<~L?HU@* z206KYXbo4?#a0n+prTLma8C2A4Ce)t9vIt2UOj<+1CSUy=444PpVaP-Kb!>D61+595kdAr?F$ag%avMPpay_(jMcnB#GZ-<> zB1>~K)|9j2t7D~1{~)sUl!i67-0{3tYE{%;Ku!o7lSWna_Qz z{P~x@$%=}%l>6_$uXrup3S`rB7cZBue*IhJ=<$;nPKLNqW1x(2ohX_Ibhr^Vx|3*| z7cN}j5W_E)d+xrEl{@Q^&3hRG*k(k3qr4vz!NBXMJ~PKY{weB+`qC(S@tvSc-4YM6=OZ6JCt6&Y<#hgm5#u@^x}27yy>XS`z92v=&{6hQ1x>j6#(#O8 zc~?NUOvf0!qOJgC{qTS&>r+)8Wl-?QdXZ=%EkEn(hfc~(Uie6#cllz(gte{-(cugZ zjQRA}ekjV%r{B_G;_)TKwJwqoj}iC@_>g8zeX$EnfjIFSTFX#6;~l@GJ>%M@{Wh$w zmWet+`*8pa*ho9$38$;^e6R8AyF!L#7i}SE&wOY5wzg59CN%6sG+e}int1S9~zDmc;aIgSvX%3(Xa1^7L@ zWYX>Yw4*HN*A8vHb%1qbqZRx&!L<>1l4+9y_PQnkHj`I1$nn+Icqyhf4^#tCoEI`D5CZ%wnh6qi{0`Meh2Ps3(>Aaws0Jf zdIF;j@rZv784W2p*4SngeY)dHsCPX0?sD7Bx0UJfVXoJDsyy?xFO)mk7kq@fxBD0m z=LR`{hA{&zx?DbgrmSCJc|J33D)&w^EkL^pxyl5H<4?Ms)uwUr-?UQTj61RI-=sD8 zLlDfW?ZG)Zw)K`iloe;~9hbbS&M}5J&c$K*I{iE#(FR9RNLF$1)hdO2(sx-sqAm)O z(iY#$MivEh!bah*#_z(cAtQ9@2gxcFgg$6SgpTpsG17BRRGy{JbiopNbG2KXd%*r- zbteemTZ5uXm1(C8V>^y|Q`;}FF(|Did@f6#;!ou!GDWzwd1aqB+T_85 z$SN%3^}cLPj|%v1LF`A^pK>yR%!*gu4-z&D%^v>iDnELhkg;MLU+~lV!GHcL&yBjs z1+qmxukf)HP^NUa;6umv5976y1d^|P==YpdXZ-Iu(qceNSn!@h7CE83hl;U-L(ZIi z{_UoPDoOu2X8{+MB=h{LIj+TVM=1+5*0jg>selHT_| zhC!g4I=ybg=BR5US7|$>F@=F`Y#c>*9%U4n&^Dyv>u)&nm0N$|iAE~qwlP)+6}Ho? z90cFCJ>}N>wsIx__s+9bWelbDr6WgBMvugO?P08Dw!V+Hu$sv_<-Ac=-g-n) z#Nangy(O}Zq-@-}zwFpMP~OH&{{VfLvh}6mQD(R&S#6*ZVHic(z4c5mp->O>W1P?k zMH>uRhyGxSRZEw+YI8j&!|&XC8~5A86ZoMVKh70?)3dBr0q^kSRHDDR zKl0)Sa?z21!7h#ACp#7~($VLTz<^DoTftQnUGrF=Sl;3AyFlY)JiyOE1HqI6_8ZWs z=(!9vJIegcG%^(vNM{j>&z?GzEC!G2qT?2)9{dOwf&jFsSa;DNrC*mP(3&`KG%^PQ z$LWkm>kHw5Z)x?>2ooxh!i&ew;NsX(Md%lejF@y3b-yUH(s3Z?%>V8 zSV{&BHg<(_oyz_sjmG?Ve`F}>Ha_DM9%M3zIa{j|FPwPY!=eK19yA4XzkOQy6_Pxh z#_YQ+T6q7eVIi-#b07ylmP`lgpsyLcEiA2xv78^Ei&)-FHw+fQq!5;wbIC*WkNmF{6rpll$jU*Kqq{4}i|L&ts7|P0nk-*ax z%Sx$d{F|H{qy7%YyKtG;28RX}(njwb=>+_ooTi50kHMf&``{I5w>OMp@3(dCNakmM%mcM2}4}lmhXYn%D{VdwT4Lkx%qceG-i~&-Y?20gA7|$1Ajj5~t z@oZP#3~WQRzB6s>lV0)D3QOE=UPeHZ&=SaY9N(J2S_TdB#V|kOFLKdlQY&pUV>`{T zMR~H&_)klUzP1&`7o*{XZ?&S@dBby~M*m9riCcqe4+?;F!1G-kuO<=Poso3|mHXEh z@LM~yftgu^)M*ZZqd$&z4l?02+SWF2dv+Yv+1Hs$ws0u2>OzCFa6wxXEdGr721>fL zUATCntX`$XykC*4a{TK#_b7j>Y zW{XkmRYV-eVp~9rJ7OiLP2R1YQsk^)d0=xNef4K(`u7H;-IDpjaW2fQMEXMnBBG1bk+L(%g`|TIt22Xcjh zj*P^3Z`Utt;k9y`vQsycA=Y=ZOpd^Ye8TJ>q6bP}e;FQ|EYBRdRNj5hp0a5OLjhX_ zyqA2Klg+mv++Vyf%=LrJk~$IO*aA6|?AaY+mfkHJJsdFb%u6qoO^oB~*Q_ez`%MiCOJF*{uYLVKVS}EBY< z#;GvWTR#1i6W&uZT#Jn1%fk#uI1p}xx*IJNx&Pe{zNy@P%YN$Q00*CKpl)P4bT7B% z)WiPzn5}nAW~`cI`THza%MnsA3DQ3xS3;1*MJ3}6dDSK2z$=GahkQ@j2693s@zj1C zKl7{*ynu0Nc9e6ZMn}rvg_p}fH`h~h+eJThM5C6cxW{-y+`2WuS$~JWl`DHF zy4pP!a5Ek(NA^7vq`!Y5_K|yw#7buSH{Z0oY^J`QV>Z8U-~vWDl=F~Zb9sF)I#5nX zX|%QgJimiw?3~~~N;_PGk#ill3iLDaHqab+JqulKmpzNY#Pb1^X}yBaEAQM2VLvmw z;H@DTG2{(;*95$rV)?&iI71&WOIvV@&Py8%m3-I;Gu1oi9Xug z{K6QMdK{X~Szgm)D={uuExcMAW6r?ZvU}%1*}r!mbSQ6ny|OEbUCqSS;A!%TA<^>_ z_Uze8-EifR)dxc&29Vt>t-s=_{*=RdwqVe)P)>8@+{>5Ci!UB$Rgc$*uPjGSoaUN8 z#siEHuH@;39#{gfK<>9aFVe<2p0lg z^B$c<#auhOglbYpDMnfLU<-v0m-H#Ds>J%|z^`B;PV=nrp&;vW6P0U~NYN@Zk2AY( z#dMjE*Ebl?gXP5MAi9B$(2mD_iCZ~Y-T}_5=MEh@L?zD|YOjbfAEsx#l~@`ZawBa| z!FFlA4cz7T(kS2T6t&W+(B`b0wB|B%>8r|G7#)JonV)+2UN7`}a=v^Jr+t(e^Iwz; zdA9?4`#avj(xjE;;YS`}zs#1PNug+2N1TYwv(r_@#juKAB~f0y z5hwzOA<4^1jgb670y&QX$+{vB?98pt!sok(oxyAQgr&uLzsQ*e1B3k4sxD9cwgad} z6XB&voF3xVcF-d!xXi0>=^^c%&hO-pzVgLK%}+uu`2;GlErv?izv{2~sBNgyz8tQ| zj{r*kxEAevX8Bl$6=)1^U;vMAGGctaGdxhVehiBk@}Nm0-~)oP&QNerUq~bB8etKS zxRsU)Co@GAzd-|nKs0>XO~8|y)fGSgSqCIf*D|(bfdo03PJ2a@z|s(kA#igl4MxU4 zVLR$n5JI~Re38KxY^BqvOP%ecy8518ZT~ipD&*p48*;I~UyD*K(ik4TTy8mVD`R30 zvuoV7j4-lh!@9C_^SaW*>Y@3$iSoub-CgGT7PwRTlV$bnaM`wrac1;VnWIm2`;r>3 zOWW<5!5nmDos(Dk&>rXqWA@lCP8KzP=AsKNCB+{+3AfJ7qUg`4s4!NqS-p`+z2y>1 zh9}42A$yKvei}rRDDR_?Fbu6%CN7nAjKS--?I>44$f+gBSPOBmt-|?gR^8op&pl=1 z%{Q0*2+;GKh&?paUtapo!{yxZ!(|=ok2OfoV?gj=JvwgWjl70XUJpQvr*%*E%y268 zcJPje5*O$F!0b3&6CPMbX3#v_{$-4_mk#stfZ{GEP;}n?z+L4Z|IROzTlVflsApUy zKXb^6&ph{1`P#!zh9P4HWpEW`GtKOx_iPU`gX^Jsy<9VRiMy`<(_efacZk0=?!b06 z!8ii_p(95*)a=FbLu~2Hf>GIjC`g#SB zKb@|AH}Pt8K_aNrqch&p_XbZzw=}r(yP}K^rZeCb-dmOK6~bHICZ7F7MDdHXr`d4UGX*Ci{|kR-$@7ixnhkm;tA*_4m=PY1F|9`W>X;m`I~Jpq!GHRFZLV z=2gs&cdka|(m&3-aR0xD2x_#m?kgkpA$PkJzqe1NH&@LdH9-$6Y;7Ol(x|BtZoee$ zlh8GB;c_|k^10woKYSS+U@1R5bymI?C4TMt74%`F$lWTu&@TNb_?FA$q;f3z@WcPv zEV=1|{*`Mh=O~})$#K$FUWZobT#G@?S7l=L4D|u^g7NXOpl>BxkXAEu?!l+S$dayD zn9|5+o2S2WY;gO51gMZ(7GtcwnCEjSa%7=OLkU1M?SgnoApA|Fsps7(SJb88LIzjy9 zvN2)ww?VmgT?ILKMZ#W7=T&s8u-uLDu99Yh93CDCtCvguRoZJFOw$2YWi&cJ_#3kd zq~&tRP^f^hgNR7xiM%-@(#ydc3dma4Du--L;#81{{d6+JtN`zo6tVXa`ddPu;W}V! zUK%7cLYzK*I`ZhZ1Am>h7xz*pt84oChKK+86TCB6{!hY_49mR7tUENN^$~b@>(ZxL z%2FZm;-yQV<**=^Rbg!KaGsoX&DqJ=uLXqV2+_eS^XFd(j?`h_rA6VhI?J%-g2-S) z(%TB?d};D7@j&^IRtkad{A;l%UhK>=-Q=64(}0=^AJJ}j8ZIt7{SjuMtS9cZ7fr-6 zqUrezCk?s`sQ3e;Z~{YG;#6U$1BMpy+vytHdS`i&b#I>@*rV`2j-f7^8}Z{oo?xOXV~}m4knq)|IEXy zV-}*7vv|p`P98{b``dPxMv`{Kq_V zCt>y7bn!A-V6(1DnSQ#8Ylyq+HFW>!pMJLd-aq}l3`Fny_=n%a%A=Xx8@VQg~+{D=R~>S6Yo(Fu2USeH4`BKi+8` z^nHY(2WvPN+*7h++$JLv2n<&_+-jO}Xq4H|i|nUg&5Zg2!nq31MU0_+9M-jO@2zF` z*6k>+j75yKE1h{n$R18w$T=;VGJ^fIca)zxda9fro#bTf73>>ke|!%!crK48&;1zIDRCJd^~rXx z(IS`iItw?$L0l^_227W~`>_v|U;gnF={w%Y3P?cDCGQYLi&g95mcl?#zTZZA|jRy+tlbaqv^=ijI=T>|N5nD}Xo)Z$r7rl^GY# zpHHQfcW2xcl)QG%S#W1Ke1<|xTm>eV_}gLV+?Pf|AylbUYX~quVOa-WTq;&FRlbIz z77VnknywPsq$`Cs^W@Q&~2T zIZ#B@{AuDgT<-_~SM>x&x^#hy(K{7hJ7lf1p15o0neTR@H7)lbY3ZAQ&zrYwitPki zBE40>xbne)B|1HM2}5!Ph89@66*_x(X&I`3h*uXg_cAZ)POvxpgXr+j&*grNB}mi_ z0U~Shli<9X^_EY4(X;X-AzSdS4pHbb_%fZf^tt@WbdryRz@-B(dI z@P7CjAz5SrtY6}4;{K2y@+hfG{(bMs1)&LE%ckb114)!eMa?q=9m1F9G2n~`j+Sfi z$?t&YJL@+PfvX~xug1#AQSydU|D((ud6jF&9wg~tnyW&wc}iQ?&PWRhI?);+fnM3IXtVU8~%5r z$ZTHK!=C7YvgZ>&S>F4Od&;LU4t(X?&&4e2n!zE|yZ%^SJi%4~x2q|VEvQ+Me*X8_ zw1KEa&_!N!`Di`_Zo(sQ(N7a5sINaXM*@|c<j7k>)|lA|x|HsYZ^5G6>3_2h zV8FM|FwT17`=*Tpq9MCw&KJ!rwWW(jVPd!^6diY!A*%x0dKmER+ z4CRf2<(351VERjB)_xA08@_Uhw$BPx4ssr!94Q;vE;GRy7_*Ey9^Bm5KZLB2t5S02 zocd=U5DZ5-hF*=x{>5xQG|aHHzl#GesWoM4j6>Miqd$kCpr5wnfqqEE$Rn&&L6Kgu zg7X5*vlDR8=NfsXyn2pOS4_-t*e42VuYk}+g$_k_mZyh0DjRyrzFThHeiEw?0JYC@ z=u!ra1M^shzOcgckyK3K1$qRh_VKO0WIyS0d*oy%Lc6@3imfLTToa1HK|N!BVVrh` zL4q9Ek67tqrF7GGbBZQ?g9cH8AXB}=ZOFYC<}`Fo!iUN65w_;Km9?vE5T zE6X=z0%&$+!7zso_OfMi_ntjvE&Je)az)_9^Owpr2DA+r1%{X?vrl){KjN|~VE}r& zX=4-I5b%Hf{=X$pA1klBWgmO)U7_{!DtiE+qMAAkyR+y6VJkGte!35LCy`eG zaFCN#pKrbF%YDk@DqjfqT6H&2v6roKnLoL%i<;y>*8a8wZ~#%^vanQ&TxO}2DWb$L zC`489G=A4UvKpIgt8?lAGF5`oSrHu1D=EA#3TuNwwhD^46QTvzz_cGO6~yucokPr~ z`{zJog?47$<=xTQkXQY*$VW#*gU=Z$Dk}}kuu6YexWQ-I8Vux%?>#&{1SAXzq@iLS zCkO+p67JqZ8({Def{C4Yqmi2qLnobvr_h=|8-jO>T1I}mtX_Jng)SA_$Xb-2^v3K2 zu+mtK1B2cVPb1D{{mB{eNr8E)@iZ*#+_@721J@prF9Ioh`6CI}a=0lb@YJ^@FnC+9 zj2ii-*G*+xrCXkoe|myw@X=w}aZueuh$0R>zxlYxiUU_M?Ag6Lhz~&%+;+NQ6d?g= zth4gcn&l<9>ATm+`#AY${ZeGBB>M^c63X>m;(!pY_1EOO6A?Hop6VT#!!ui04Hr_M z;0y80lPf`lj~TCusiCvRv%EUX0&@7yMk7q5*TiwDXf+~*wVrltd{^QG&*_2XlkMAQ zr>psd#DF!t1#6;>t8F4b$x)NG{xvM#1<#%wA)WpHE#*mrm@MVVb-Z8jY=ur_+{OX_gDF;`Hg55 zS0M8za+Gww3ZCVHGY7$;C?8>hS4r%0QGTd?QCdw|Et^n7oNz4`0GRn$Hb!^`+rZmG z%}c~-eYav={y2j8|CYh>ZbvpY% z$I1YQSDi*y*}e{A05ewe99-4K(%ls(m2`99wa-(*govPvbWDt@s(%*(wX=L-T!0$n zSZHp-BQAm|5gko19T0|~j$l8|_;t&HU1j&`O(+Tjnd!zaeOW5t^@k9mbGe58C=U^oav zi`j=Z^R3XX8(PC%^PEdiSTW$CyQ~{T37RbrefewU%gnBOPxj_58_QjH+*aQAo_Ce? ztJjvFc;IzqtSrd z;IePWy7F7U_H*Tp_dHwv;w#@SPaozUZ1y>OI{K=GYEB% zOn?=sRx5pRt$_TjzX9t<>!pVL=$=cHuB2X%0$~=p4iE8lxL^_A)Mj`>AfWDv_m+rn zKKEStC;#Y|$}fKSy=5gZD#LPeitQkSgZs*DcidI>vn>DfU;H8pI@c!?CSzBi94l+A zXHWU%OBboHr^<IT+_H5QGu#{! ziJ@Y?n-li=2NtRqvb6c8PQ}P2AJ_5VOz-)N6)}K;N2QS9(y*gEcb3> zB8r2phgP~mhUNcE94d>45rO9nh80)d#wr8aAQEuQw8u>WwCM>B;k!aRA7%D`$0knf zhriSGNt1MPmo8r5dcuw1WJ{ECJ$+)(2dPdHDd&z1Pleub{P;rIyLVrC{eAb83-m1~ zkDV-6xYBMOL!J4WVs>7=uA3DI%KWxZ``iT#3jgc>@vqBG8`qSZ_wMB2Zmt#N(8WQN zd@@3~#yj5W7tND;jVyDOf^wyLqcV@3z4&HW#q`!U-$&oKE9#Q+t$k6tB^9^veJwn0 zpkgn(IvL431ss9`6}MfHQ}B0?PvyQAl;ua&SE%LBcs44A&IW5VsaBb^1Xj{`CATO9 zILJuHlX?MmoMblMK7!)Lua!plFV09<6;7(~P*jN-O z9PGmoKt&Z+CyiD4ily%jJ{9M89x+a z;G)wHj$-W#Wj<$JVo#2U$ZH5ZJePNreG}Fe&^jThLxwjn!8`KjQz5I{o*s6{V+|YK z|37)}0cYuP9Cp^u%+BVB%^AB`WDtP>2#5d}K#(FBM2cb*DN-h7Te5VL&bEB#J6X1D zOLsb5kbgc|K1sB6KFSIfB}ybgfDr%zA_I%XF0eW09ATbTc9XibQE3AGR?$tV`vrdd7^I9%pWT!%4$)nV_ z^&kq;m1u3wntyqb#CZ6T93h07d5fB7v?cy978@85&(Qq+`f3zjc8&!l)Mk4b=& zXB_!$3G&uUQzx~orGAJ%MrJiEX(LR@!C&F$(&tpZ$@C43#H68X6|_sf4SLpXLs#P( z)o)c8Z8$a9G=fa9l>wVy^UcSMV7UYdl=4u1NtFvD`@!5r(u`y z3r549ttay@c<5D8ZUw)@LzW-7jtw*xeoK4IB$ja`8ZQCqwF#+@_{hhI+C5+`urzg;EYe8sF5q2N()EPff9^;rnvPH$P5EPWK?1CwE`KlgDC zRLk>QckWG%u5%dETeWx|lkI7|pN=CvSni+P!Cl+*fAn4BP>E+`NP~B&nbFYA`GvXa zn5)XXbb8Pw`)lzh+_{di@b^c$4VZr~0s~{0#^6->pML;)K!v~Yh}nZ+RK*$vSqA^^SZwrk_cORtFUJn?Ki`~2p3?76LINcLfYdkSZ)!9~d) z7-^ghZ3cx4%k0>n{jPPzM_R~4m8W=XoKHlk&c{(+HR!ed6)|xd1$Fd$23Mp;#%;s8 zEnp;olb4Ca${r^5|iA_aK@TJGSqPE3ddJcY(L_JdbPA zeh7^Xg*}g!n!m=@#v=^dCi*xwa{Tb#*w=G1{^d{pSiJk4Z)YcXdhFVm2X#RutCZc2;&+krww?GsCUb2x8(4#6LF9$>n>X|JytK70!`<|6VFlJ z`}W3?t7gZNIn(KH)xr%lSm&gMjRy5*aGXb@*BbrHjYi7m;^A@ZWb9(jHy^oYHU=!0 z+;mm!-@7~h_?`!I?7!}k#q{lHF*DEeynGkh2R5HU7D$#YSwUW>E{WAEmS&xo zCYrS`2S}CXm!BUX_ZkZJGAU%_#|~C`=tYhInblLg6bY7bgysn#oR~oytYf zfQd}W&u*m%!&&ykm2TFKi)SY%4yrnZQ}IwxcOb1aa-}^dO$uRr>H>kkmQP%h2IT2k z8HIfXLGkt6y4EbEIuA@XD$VTQhEfoAQs!Nh)?rSzAg=wZ_>#2zQr^VZ4vc&hI9;SD zkTa4I$8Z(K7(wY(AV}x33sM$HESLG!bModOZaUA?DO0AvE)C&DanfSEs$b%L>J+;; zOd@KT^s5t`giS0bsXEiTs3O5Fuahi1;Pmubfe9T}H5 zB4wUDTIVTfH#D|>efL<0=j$_^!MCjLHjOj$DKr$eG^;Kj>np$Yu?+I1{xdECWnqKz zODFP_KSius!8cyQ77qTF&v@3EcuH&E%XN30_aeFcSMe$I5Pqdl=3Kr+lm!0d?pPb) zGB1hL=GT_;Z~w8CuLXY7}zi3hxuCag}bqwm;{)!2HkXr7oIe z`C}c*!&wPN)QJLhRsJ%0h7=I^W*r!(iEag&tO1h?gT%>s44(2wv4kuimONUpo9=C z)7SQF6OQmKN7FV0%zxIMP#u6O9MjfkVZB<{jzc?)gbmF{g|~1gTpp6f=_+pZop8%B z8qEaT%BQ5wBsFrTD0G!q3l9_;n5-@+)uUjgKSe0?h8D*N;8daC`p$(}{7b)3GB&?f zInt|^vtZi_7jxUo}a2>#UyUc8#e-t}5^JZ~got^nEu7*<8 zeI}OadpHL_jj^wjbGcZYqY4$q3y;@)Wzj<0LPHJ2rD`s?7M{*f=0s4_rohKV0LKb8 zu)&3mKP+$`+Pfc1-dt66k{!1rJ#h}>cY~;}yNfp);dMF-0h2qq0SE1~4sLvz!P(n= zSk2zKZByKI^UZN!-~Jdp(@UJrIJk9l>|VbX_4i{jfolgRp|*aSozMOSbIWy7EF{<` zQ~0D67`1pOkM9A)-BAb8oYzpoTp)+0mPRAFLrm^m>`g5~<|AqpYUHd_OUV>U+XgNJ zOy~B4*|X-NYV86#x6IV@2ZOWNxt^49Hp--`+eeJc^#ic8k#Q+*1TQ+Ts2OfAZ7A;(qyUdR~`Uv-x zUmKTRei=fdn=H&n$V_`qb~_%OJa-x!7Sp=pkN^9B8gIJeW{z(_S$L+aZ$=t$oI7_? zEWP`U@wT_z8gGC5hWIN4$$Rd9j=SF%Mi<9Rn0@42&wj=8@M?Ke6znMAMGncx{#z{=iY&nEIMtDU;9TNhP{Pa_S!JLmE#1@U#o{lpVF&9ZsOQb8;_U# z5h8yXx4>&vd6Ql^`n`x580>NYZiDXx=pxeLmI&0&&h)mx)k1d zuM@sf7FU`bu$U0gVTeXevS z&QgyJep!w(xl=IERT%m58h+&hhl9Gb2EU>QTxYM}GBcJr^*X^n0#J=W!BUowU|Eez5?bq|3M?zY0C%gUXALu;qNLY|!$2 z(SzlrT~RJ~$>j}K&Ry{F=z}Y)d)Q$y19!=+H}fi!YM|RDar!B2RNV93uf~-&ZM;Iy zcK-9(Nx2=WwAG-KJ8aS=d0*bqHQ)*k@-w*bXIce&4H#-?!aM+(@v|OV>1um4t*+FN z@S4|zSK*pp=H&zRR--lGN}BKCxA``hzKUEMtN|d+{JXGwsW8&ldL>%IF?t(f(l4EL z-Ih;%GkN(8hYF&?E%cZ66^x-Z+`7%yn0<3lW~Q%kn>>?uGGhbU@Mz-IpMqO?E3teAB5>@}Z5QHYo2WFj z3_fSRtvo8kSNB`;9>$ehtcmZ4vReoasiC zsn9}UQS0a~B&*`7hM0cEPD@|*&-Oo#lTOOz6Z5O}>2L8X_?cJvG+EZHn_tUN)0X-( zz)v$45J7Zn9ItrmM}5>WbP7WJcoq}fu~t3*5Z6ofqERpv176Xq^ay@P8_&9Lz6k!;5 zWdb{R63f>op%E(Z{ksmtylZaeHX(Ku>AugNz)&97#GP~JkHvsK79RGqBfoXyhM2bi zRb}|kO@}ilPo^M$(ahO#miJi*%bsu5pj8+1FOQiIq4Mi>vgce?5VxFrBq2)~at`M_ zuGEt}V;ipXgIceS0~6TogShnX+8uH#2pqQq5juA6*crFquoO**h4E9L{CNC7pZ#2H z*|Cq^%8qz&-L_aX<5I>F)OSgz<#Ny4x=3Jt@{0@h#W{20FL|Z%tv-d~#*vGt76x+0 zY!*is%;<<&H(wSjSI&=T*FPWkJ@_2z<7n%-N&=it&Re4iof-!N6R;E2CC!U zDgX5cpJ9an!4ta^3ZO1F4YG4RfyJZ;xM|@xe)1=CItuE_)J=~Fh-L==o``>j3ytX91{FVD-&Dw3Teb;eh zpXsz!G+MX@4y55Jud*D7$F^>dfAfz&5uf?=M`AjAOfG($L9^-T5o~L523<|vH(Y;3 zTyfbYaqm~Z8Q*&N>DaXO0O`@z;b<;3k^M?pq;&HvV)yPH@$tKFiFd#2T``|y0krs7 zIuGmm&}HH5r7?8n(s%=QIPQMOo$=>?eSbW^VModfYA1DK7hpVU@h-%Zfs%9%=&-ZTknWJ|NIx@o^L%7b1#}Lqp*mkrF_bz zObBwy9fK?mbaH%P$BylB%Qct8Km7D(;*wR1vC}Xe*#f%b-ty)*qT$sOk3IQx{K=pH z6~~PB=VH+~7F~L|AJHQ{I{DFd=s1$?vb|A!U)rY#eSh3*BG_l2FrrhDtTg!7W#=N{I0$GKeYEE1Wo}tA;k@^=dGlouOk|bq)r0WJv(hI>_hF zvc-e>Er0^KNfe&5Y=-HhCmuy59|6`tJ{m-GGGqsvlVqa-SDNI6h$jbM&!f1opkbm( zlUR`^O*dy-^ivqzy?b};+_^IcG6li;7}e1N{~0amH+fYuDCizx1@R1{?-?#+9l9_uY{U5>(k8q=OYApC;Pwbw~Sl*DB&0uo4i1c8cbz;10fV1MB$3J_T^Z3L$b>Ik-_64zQ#i}@l z`uz~+X)jrMNz6q6TKCM;?8zhj$5^@b2&`%%{)jbIMLOav z7UihgZ@z1|OgbursDf`jOh(1pF(SuB(~#V1aw2}s6-(oH|L~94LA)YXFP$A%ptAds z54}Hr^WXhmoZxz|kG<)(_{^t1!Y*No+FbjE761zm6IkFF(84!7(drWvWU@zM-jmce zD>EFPUlr8xqm6g5@*&%eXK`lP9IiFI<5mQvTjP;OUx>fB_iM3s`|dpR+leJ|jUILm zGRC2uk@HdJq~l1J#t?y3aA*owG9lmZwF5W%F46GwQmzTFedUYdUnsp*U(>={rEky= z8d&dabmV3UJJ8+C-*@jh7@zx3e-@KI{=v9x`62{8Eu}{wpK`RlH+JnmmhF4vw%xIC z(Sm}y8jkSW*`5<|%MDi|7+#m>%-22hT-^WQH`(=nnCsO}#^HkpW9#;lWS;3{jmN65XnUB1&57%;Ud1(bbK=YQek&e->N$+$ITt<^6KpTEap~z% zgrSbUSU7)ntXMK9-to3uAI_tYx+|oz%3zLvTKAhCr*h4ci+Y$ z#7*(J|MFksktf&2j49a4fbXiz11VEB%1u;xR^DxQWBIj*{~db%8wvK=$RUQEMWtcw z2lCy<-w=~1*%_!(r;7KY`4`1h^h{2%8a094MUBPKbqX!x*@2H^CA)SiN%Iktu=D}G z8TirF-}3fS-|d5X;%a0bYDr252E2rC8OMgEU?;QYsx?unpkt>e!{rJ+9byLqa5>Me z5XtHn6Nx%uk$V-0WJvSLyeWU(?Xgseuk_^Eyv$RzMe$RRbGI`GQzs6LqSDWJ?#!D{ z7x5KFYdM6czpG}#^em%(7himFT8Uq?hE5M0wUC(>ixJieat)Qi)7=-ZvQU`TrNGQ@ zPF!k6LT}NI2mF2YW4^_We5<~%$(bY(O!a*DPWot#)pI@4v?aVkd+W(G($kWR?JRA3D9`m3T+DZv9%Dlo%hxgs z#?-wU7-1z;eB7zuvv&^*I1C`vPub-p9`Q|3e}$=+{OWJ5nHOV2y(P_z3}35x(-fdS z8?JDk6F;I=^>O|EButyMINK)Z*|kJ1z7}4;beT_iywGjoplWEPj z{u)nSuzSw5NpMqA&%)}BDF;4n5?-?@uRa8?;{9)f=dJMxZc$7Hxxk<-Q4oMAw%vLnW*FM6r!J}IC6#(7rkysRrN$~PxLY2SN*n&IfeID4|08A7pkqEv6Wuan1Fj8x%cRa=*3u^be@S&KWomM zILG9A4yx>`(hhO_QGr~W20f>HupEyCZpR^|@P=+uue8)syfRLJFMV~bN9Q3fWI2aP zb$xKixri0-CJ67^FR%`0q2;%G@9y|dzyJI3na_M87A{$UIx*_G>=5obb}Byk;UD8V ztn0F(v(1DR3a&TnXlYzrg{SkoJ~^fj`-!n*L+O(|BGF-)plzo-1zHr71p}`8 z!(!U|-*$Oiec6)u`ooXL7aw>e4xGU9Hv+>XEUyo;1MHpTwXWoy9Jk29GFnktzNA;8 z@V)&4g$ue-VM#a1G|GR>^fg{v+?>}LnK1i`oG#ryxeUyDz? z={l^RU!sym97I_C<`YkFZ1X4@8IxoEp4|w37iW)QU+ffM#ZD8($yKKl?&_?ZC>;`Yb;-uZFZ_-#y7_mt5>ifus;s7=&|Pj_OYOu z*8obd4%GdHecNp}Q$y$Cz}}s)pGA$ePd^eHUwAh5?%5ibTzWO1D=})lB7Wq3KgLcu z>h#xN&SJ>9ru3b zpKjDFU%oPyU3>{PE@)dEDe&0cSMGl_PI9|NVV@#`BJTj(F=^ZjYI$DRhnN zrR|N2-MhBuVz~A|G!}T})mLLLV_GblJ0U*(sUJs^;E!Yd3)@&Mbuokb1~A2jkBZiA zdSq_pE1PQD```6Pn$v6TvdOoA`j&kIlvTJ;SakKriH|#a4%UXJU_|Y7xMQz?r1j7#oK=*5 z${lGTUmBa*GUBq%v(SZR<}0oA*VSMBs`F_W3!mzTkX9gm{96XKFQ%a~<<8)aov2ee z5OP0g9(5r<>0_s>Gk*Tj6IL4JBqc!$yu`_e)|dIW<4ioW2etxyUI}AC^oG{vYn!m% z3*F@f#6{vbDXdQ3v<-N^UISZB7KTG>tTBG2Vg8rcBfoi*9dQY*1Qw6)_qXJICHN56 zGGsgDIe)VZ`7&G@;kLQqc< zZJUM9`I}LFYRX_(1G>QU)%IdI&rQCq?5$^C8hE8zNnu;Bkqk472CiA;bAv$hliq%1 zTyrcB>0kX!mv}X?YZkt?KR3anV6>GPfC{9C*^Q9Dhx2MjvO@Wr|F+}Y4y}dJsB9}f zEgH5b@)`Uq-7;yDzQi}gkDg5c@k`%JrvjmbpN92_W}1?pFEmZZ0_sm!g!;0(TkaMQ zjIvFRW9CnEKaMXMAHl5RtABwjlqN50F3~AC)jW+`@GWV4tFGihdMU1aT&^SoBqynvtZ!j zrL=)#voB0L4xngwmcfC;vJ$U@&5UuAdgClRX1!>UxyWz=;k=h^&+$v<$1K(Bm(J&? zDhv1QvJVhP>-cK*dRM(h?Pf9_ouaSrK`po!8$WX}ls9k1{Mdr=t#i=*_19d#FNl@>Ir*f3Objh(yYR2TpX$Km-|wQY zG(Z^7w3IzH>F~4eXERRyFaPVGVa)4T+rK3 z-9+H2IpX>Gm5ZmwqW9k!H*>D{ukU*x9$U8~_8;%z+&?!RF}C+1oesLulx!;<7*okN z>k#;b*UWgdE4(<`_qBNkb}evwHto-5WHiTI;~G|f4ZDyV4TE^nvDGVNqXH1T;rL$E z&)os0C3Ve+*Dvmldmh;ozyH0;X#;U=`ySGe7Px~Lx0}H3 z^ZdE9)5zP#O`Bui?(L|dA4OnCa|10Bufdy$_T&W4m0x<<)d=bAv_G?fMK+9UQqdQo z9pxiH zUglc&ef2AG&9yhiwO3zHJ`++n?&i3si+3KA9gl5?0s4`vmd(ac-t1Vr_Nmyq;hEU6 zWdlbL*3!O)V(GF=n>qbZ?AW$5o?(IH%4@FUb_b+t&ii+xncy{$Y^zWm))3cF19Q;= z>_@~|7MIn;-GD8+^>OgfPBy2y;^LJnQw{#x_kS(z6L^39k1zRH%$qq08lT4?-qbjB z{1Ea4w+T2egI4FLrx_UCTh7`4vwcTczp7_WI-WR{{ zi@y|CzwUZ485fJe!-d8ZXcScjw7qy7>*T33al=)Y<#COL7*?D*adK?jv_AgwuRk9f zHaySy`Ze5SaUwqblRp<9|HP-zn3>4ce0{M1V|v@SpN~Ua*_rlNfSgT}{Nz)elo)1X zo}f(=P=5aof4_EuJsq!9bT>r;OHkW>wtpHwJ$g>YXn9y%#E8qj0~mMcjOhqU3i}Es zovzrEW&jv=)%K$u*^%4)OPAuxQ4W#Wr{KqcYv-b&468O{kzNc`{m<2LLqJ5>hFfS? z5rvffo$2v2G&?WxC47KE%VPo#5aMrmafD~VJd5RS1E~~RD1(3;#Cs929du-1SF%&6 zVE`7iyB7+CPWV)d_pbYMs5H6ao)JU}mse_t8)-5RVY6@`tg?gAi2;f^GztcCELRH4 zf%EKH)uDlxX{Cv)BxMq1T36Z!Xru!JwfYs{im{tb`Tc!#!>GIhBx)^`B(3rYs|m8)qw8>V1{swvC*4hJ zNZOQkU?`uAGz_=#P1to@EWagU3HQ4c%&yBxzHfdDJOAKwT~7F$O3GOF)d|pqbh}Ip zt210U>C;v?-_x%N%pW~`7~zU%g3kmcO7lp}@?w+S->0m*+p zTBhc`BytBDfu8=uJ|tDoEkl;Q4Tf+o zUXW)R#{s<8-O-OJ6${Y8@d2!2AKDKuj*ESJ_D1ii6I^e{m3O4=WjC-JHFpihbx|+U zfrdzGek>T849+36TjSYxH2^x8LwNn*Su_YlekuYm5^|0&mM`0d<+fnJb8e&nefY?+ zxb^xgaXWc=h4%^9|9-N=4!-OSZ7$^ zaO{(lq^hX$oi5oR^DOV?tN>=DLi17!*1H-HX+<2GpJ&0wE4HRUuxnPK?);McuPXI6aPmx4}V#N9zOrHSP>< zMcBrI)?fX_U$L+-hZ`7<(_UPdL#RgEMlBHg=qa-%#>%D35Nc`L%*8coHy)Wn%MRm( zhkCeWwEvjIV!;$t?cJ4kH`{rq3u+pAq=7O2_9zh=x8tS(b0tT6Y(J*!rmu6J2<_+( zr=m)(wfR8|{BjTBqgMIYB>PNvW4 zJ$*cH1W}lGv&(tDi+}c2cHyUcj>ha68d^`T+PyQ&*Gl!eP0^y}s-x8}XAB;^~ zHpl<`%fB2S`}im0BCZeIg;ByGj~mgBl;_SvTd`G6@TRRPv~SPJZ`-mZwrw~Y4}SaW z@dAbkJ=(K$@v7vtKl(4f$E^#;;*K}n$ynMQo6%-)!|^P~j7%$i{bY;J`Db~z-Iw-O z=#t}f#{0YdRVBMuRm#ysqW$KeX7hJ`<`8Cs^+yYsKFZM43{1zt2`bjBE)+029W<;0 z60448$6<%ypUyK>RVXk{u`H|~=^PM=U!6}1`oa@NcB<(oEFj9Di~@u7vikV!fG5+# z$=Pua(16adGIV}2yWh@M6%KVdN*A1bbuc!ER5c~JmSX!5h8-w!0!?@s%)!+LXNQAd zAFKRnbv{*?0A%M-!8$@YXbgMM00@*O_`6GQqcB|IQz1=NIt8sF7>OpOr%_hn%D6u3 z9C)O;f@gNbz7uB0<*t9)Kp>tSO0G;3R(IY_FDy|#kH3SwLTs+c3xhEIos@Y*z)8Lf z4whTEna;G5T6*JS$C`Avq4P<435P%brJM15@w?>&(m3IlfmYmzMf%(^;W2lVjR#Md zm-r_QnrB|~y$Iq8oz|1IW&%JtYR6FNCn$M^t}1sc+|5^D)*YEnXUvYo6z=Donzjcx zF9c1kBe6B#%!ilqoXOhC1@xA$1?b5Jqn*cUDDrQV5aslRU*Zd^(8PD^Ast?lDC;YK zORP*&VM**JEFbt9#z_F>t&%$70bZE39!pV5{`#eV6Q>2!{F*=g?C)9*paqr>4IKMu zAKP5w-O$Z~@n523JihcuztS4?F7#>wTH*Q=$a@Q1LkBrN)A8F1#K)vw^&_72YV^1E z$BB_KN4SFL2(J-&jS3m_)%+TCM}+4UP$PVZ*C2eMG{ez}Vcf>$qvKFMlwZr_*q42p zUc46$a9s3{aN>`L4)nZ?6N~{oE7T9rmkCbHOa0~x@AR$omoBQG&mCo8l860yp>d5@ zUX!kd0jD@9%4?1<=G)}KV~%kydg~nTYG2Ik6#Oveq!dJgUivF1hHFLlOP&K#|iE4#EIkeY0yQ-sKCVxeVP%Wvu+Yo2&@Jh$u$aL+xvBYx@U zKOJwxO1E^n_Oj)%a@q3u{onm8#(U==C`CN<*qYdTtcQh-X^dB#4nD(TG`pNbDG*3W z>lz0D=_@}wM@ZJBlC4wYh(q1jv3^V`@1<5AX_FTb-D({fHi4Cq$MXSF*u6P!;<(15MJr<4&Xcii_wm@cVK;W_!2>>YAE~6KQ+B;BQ%+gWEO^BUsDJD^@H=MmWe(om1EVI2y-}97&;l(ZVG;-}5NPd*AgV zsGIl3<4-)p?G*ds@F9)eVK7)7c1k~a%CtaKpv@o0n*1{yPlkU6P7&hqPqlKng#)96 zoh*t>;7Z9eT*WzO-U3)lYxOLkU_4HHUK$L{-Fk?b{UO>Z&J_>R*1J+$1*4qPX0mXA z@xHD}@V;fksyzL{;bVt6DzE@}w(nrx%1sokR~$Lb{0v_2qrX%=UaeQ}r$2`gy)&n% zyMc~awqQB9Gyla7$Qf?3aM5eY@)cBQXFR)h9fJL#I7ywK15f+gT%^TtpT91?c!lL8 zcj-55jQ!*LV)OIQq6x7j7fkG9+%!`ocE!@mI8LxH9)9p4%Fnre)ba=WPqN71SYdlA z&aw}&Xi-_W1eCXw8I$U*&?eR2y`R64VBb!TO4ycP(vB|(Et96R?epg(T>t8An4PNc z>FqNw!c@r5Zje4R&sH`nRoR&n$8JS2rTmcw2G0RiK=|hMGR5RBvWdqMA`z6{~3! z-tlgnLYAwG_c$dyE)ij$- zgqb+`4%~7jm^@I@xI*cqMQsolQ@obY39zbXF7PPS>vDGly4rb`x#lM7VsrwlfzvOAk;bMYykk)D~KOZOUJYjK_ z0UkQ%qLg8ojb*M+fO4{3Ko#!G7EWO{q;CZTm}Mt(*(;hX=c3~I7b{soNXYyiCo-dL~z zCJmj`gO37y(p5aj+$$ez|C*3R=t6F6G%pl;gn#L)ggpw#h*;&tSdN1)&k?a5XA_Uk z#`nxOADRel1C7DB(vF*U3rtavN90F^9dSy5xEY5`lUb*~6E@RSS{o_^-}9SapT(iz zkvwD^`;Tn@hFDJ}+_BAZBI_&DI({Uu^b=qEP*r6+QgZ;|gT8kr=i1%L?n7wlMY!(< z@m#b9RxU0BBFkfLgfU7oCTmR8-9g?7N87dJD|{AbbNqrI$05j`N1Kk#Pa3Lyd9i~t zj$Ntqj4d7v_g?PtsNQPXdJqAtpG^WRzZCj09;kvm!9HD{bZq4+yl%>Jmh;ALpiE$b zjjAE}ppgbL9mMfktMN_$o0~A;A}OSBmdO&~k@NuPlbpXb!|5~FEu{@R{-`c5ElYbd zCFy~gn+Gg%Fa#nHV+ac?TKd!4$7jquXB+>cNT#~g@kU-)0Z|&Ud%815ezKP z6oiK#y7jUc96uC)@F!p3yf#LJ2efSj-(b@~b!V-l_ftnMpxMslXYD08k1G6UJ1}2A zWz0=}ln41we|M@9wTiX=ufUl$VU3-}e&=G|!8 z+;H9N<4t$}aGZ3fAH4d3-EQ96NQ4b^=GZVT-DPqKS9WTl>dO z^hWr6?ubE)~-D#FhJ)@NlkVgof6B2@QKq%co3zR8j z($ZaK^czvbmINLoI07#8?4x@MP5+ zCS}ZIz=mmPR1OG+3nw`z)5tC4K!@&x!_{Afl&-GkJbDvH2FrVDfnYp4e9P)0fDOi} zim=l%K54{JzoZA*mBGPy)ls&l$MmO8(w+P|N%3faI}$#paT{onFo`VFXMS`hb%(v| zpa|Q}*Fm&&unI~QW*PL1(eB(yu+bNFYK`zIFuJf%&ibDP53e#~w?6Z>Q)Iw}9u8~@ z^TJEmgqKxz;SZOuJ-7O7nOlMao=F#BC2Z>mXF2hc&#WJ5p{tWPpUt;8^Y+6VxMdyj zlJ%CJ#%%^Lh=kWmIfrRMRMT`Vby0Qpl$Z-0SQ=6BO zea$)tL;KJC6o324TtLb=8MS}$WM9*uUt?yyG%q>k^Q^GzFp&KZeY*WDD10JQK8?n74Pw zY1Gkk#~2$urs?NgF#|8-F6YKMY_EE-^zI|gG>(XMvD4SjIC6qKz2U|(I3%(Lg@6iv zd=%<);hEP$ALl6e<)XE?xj>8LL4VzY%CqCxM2_p(cZ+W>%mOUi0PwA^oQv_BZ5hAR zlwf|f|G<8VxjZ&)TpQaFkluCo-OQc3uw!#1E@t=s9e3Xq2iakLa?Mr@rcK2{H(CYY zrAyM5$IPSR%!~h77RUa45D&`6k832XDX;)R5sn@|nS#US&6^mH`Z1Qa5CdXMV)3Fy zc^z8^T4NokF&m%FR1CT;%=@#?prX7RLuEq)qTo=fn8Ww7HcA;@bRi#r)vAA~O zRiDJL3G>x>d}`-flMToCE>E@4-z8cG*SzcRs5Gs9vcai6O_rzPYI;A=HksQ;3Z7t_ z0^|?8z;CN5G&F&wse8Yu6ZxCu&JX&SE83O1SkTSl&j0=IKO6u2fBXmBRevYPMc6g( zI~CgyazFdo|0_Q7;SU3sO)Jt(U^n+LHW=KD@|Z{`0-F{WCv@Ksyz|dv_c`TjU8W!*AQMH%@W(evkw9 zUi+rd>_XeBMYG}?-*_OFFP_1*e6NoiufLw1_AaiTJi?;EeuUYF(e9WXZ+*+1G)wpb zI?bFhoBR(!6B-_P+iq=N_6hoFW8gG=j-r0N|7U(Gc3g9L-2aU)#W~KnA3J)Oo%en5 z=o82cll*Ti=oIf=SI1`%mPQ_+6VXraed@4D-*xbB8)V#(4aXy7~* z-&wmQ_Mh0F^SkVS>@T6|c35;%A;^z;q&D77pI&Xk~C_k6j#z6$cw zr%y{SUn52-;uN|6;8@fuKoD>MR!A;ytsIhceGJYEb)35lZ@F$(X zlYd|oO#1fYa`kpiddg5s=O-^mJt$AB- z8N;tyKpyP_Y5;pcgumbDf^#q9thCY6wA7bw?!4F!7|+CoH%cEO(DrxJW*okgu&uYY zOw-Q@M1dF8$4PIIkJ2NP47)5*DA zuw`&dL0XAPY78PwdUpRDeYwv5+e{pDRU_39oeP?|;lR6mxVPVNE-xtRjs$|pt*(cG0|Oj7S@M`u-k(cSEq9s)O9sV=uBWdg8zUE?TpikRJJBn zXC3dHe_3qj5@ms+j4|Tk4!6I#Ge-TGZW@~yo+<7_)w$BCjNgTp$#=jcYL?fXNy`++ z&t!c~rp&WuP3Mm8$=C##6c=%C_1?WZQY{}8vdz1w;ZZL0)@8NiSHALIUTjkGkc%z) zWPeejr18Te2=e<59*GTGcEtJ(n=p2^KMtWzeGJ20Cwnk93~??({dnb)d9iBc@>sfL zQQUg#8)D{cGz&O>vG%#m9EIQI9Mq7oOF^^PmNe})G+GX}bQi+%#se3iIO@^~J@@QA7QgWuzZHM)Gargu zZn-^fe#33KsiB&<{IF%~E`-nH2)k=yKPvF!*uiy-kma&Rp*?!D!2m~8=FXnSPI^!L zhu{9a_`rMK8h6}&WBlY#ekN|b`NrH-S-pBS^VV6hdGof|yk%#s=id9L)@-7WqF(9a zPGh`s8av1GInphQO;cj)&du?~FMWwCCJ)8U*Iyl1TyX_>pXYkh`S4Uvy!owfk87^J zE;el3$gcbDv|hglzMIO?8SO-*h7OW=9(#eF=V;&PV#daU$KxAc`$l}?WABam7tP=b zy>G<2=hi^NCGm^D@Q=|Txs^qSr{jh7FT^1X0&d@aFnZ3>W+}CcgdGUFwgq`lEzz^g z!`G}`A9vh#Ykcs7A7JrnPJI4PKNnj!Z@^0a&iIvo{mZfX($#s3(vE#cV(o?-JJc^AARosO+(QAsQ7!^z+2vW7ceiSPR_?tY$0q%u&bFOf zIv;kfsbRuo;N)Q*e}LR;BG`{bFWa-u-|PhJ%(7#kqi#A11Il1+#B7l!X*rX0(J2~7 z3z`mm4vJm0-W;f54%t{IYqS2H-*p~hhvDGe>1q~#E-c!|D*V-a6AlNv2H0^PhKil91?v(n=jZG>BLYoVA8w5-sV>)%{?bkd+;=fIrT+QDdLr@`_%QK=J* zY=X(?xrzzc7HM*@Ed!dlN()lw$Bxa9lZ`r|l%aLzEsjnoaCb2nO?6xMuJsLy=ZQRt(wWqN6B zy*PsFfFVSkdFo0&zUOQ6?!Zz!^iNdy(nsSSWx`bAq<{=w`I~vkN7B90)N(YAM`0;| z$PXoN!}$PQ-brUhM9gpy@Ku*MC!*vnzmlKjQ+SommNS!<=xy-vAPeau{f%4clZ!;a zvJMsEH7u#KV@yYW@|Jj;wK!Cxb>=PhY6SG5HfFsS3&qk2o*}OJ7|)%T+&SX8`U~Im z4#MBfwWsm9PG^T`U#90(+RgnH8_* zU3l}Q%aL&sdS+1ShR1~C7nLHcQWjy_=Ij#@G|1eKe4z?+#-r&aZm@siW*l(#MibkH z$m?TSN(B9i)8GG+SM?qK)jv_vOPu)0G{aF^PvSKij%hOyKO@TBN>v`RTs~TWEJTfv z5Gsi3`O1D11Yh9)O5EtOyj0qDl0_`{Y-KQ)QU znca$w{bF25w>g@yfH+m zTCah)A$FwuPNh`-AyA1{HnX^!r zWlYlmnUSQI3kW$s0-qcMpo7Uxt0ts7e$KJtVy-#nT(Oj0zH}AF#a71|t_yV1ehLA~ z%Xj)a2W|k|~^Tp{YQ59aDCpy1WIAfM+p+xB)@% z;E6NXNpQ@Ym^Uv>XK`ZAtan(+Gg-9LLE=FghS9EM#=G&uJk zJ{~{u^|(PR%TNd^ zovkzr1o}xOX=Q1ed4}FE*CmXX8F{R@S;q#n2kObYUJVcAhDk#<&j**8ZJvM zuw{{N^4-YPA&HcY{kYPk&@3Nlvq7yCjcclkf1vkZ+9x`A=uCY6^WTmeZ#sh|{8gx< zPrwM=;W%{o5NGcX#N*Gr5Sw-!Wp2c^glJF5fF5luWRx#aac9A72#pq67`(72e)G3} zC$??7le^$w7ppG4EN0KrO8yAA!^~p8ZHaZbkT(Tlou2>pB`k{}qNWktqZSUZLL*?4xJ$o?3xe;v{ z`T;FjP+k}E%AM~;)=+En97lT=&zl>+^VvViTLC`ykq^d?f8x_|3XA(QIP&6I^j*7m z#isSZVrTszS_miET^|_7(ICq2tq)mv>MUCbe0b5^#q4e$j?ez#AIGOY{(-m(_5S4- zFGpD3lWlp~@)dan;p0y~7n}ESLa?6@S6_R5d;FLv2uHoU<`wzgw->P75XC)I$XlgSDFjuK3W#!r-*C67xh;Ii6 zPr+0+^iI!^Iq`$9jBmB&F1`t9xC;Dvro?(A&NN5dDXsNfB%$=o4e8tmp9+7YAssiSrsX^VB$w z#d1(|Ro=;KIg5_3i4Dh}pG==c(i>U{FF(Bd+vJ*IhS!0NfTWdCoQUMAqNMf6~JWq3nh3C5pV9{0v;{(k!?W)#o&shqUU?dUO3A?k(-NLe*w8!q)qVgN887pchib$o{`dT+$=^ClioSXTELXyiK8<@Rm>HjZt1IcP zj^bxs)aRsW(n|VC`;yA%>PnpYCJ*^sB2+lTp*&e;_|AN?kAt~O?2>Q!E^%5r`c1|O zPaF~t>b3H>G^lX|W*+<`-1ILw;8k2x4qpsul^Op`*%UBgjFrAX$?xPVp3FaUA+3Hn zsW68AyeoiaAJ)V*C~2SY3mz@B@XNeO^J-ltt!-)yAQkU1g1);~gI~d#=w?=tZ_1k< zP1#D_P$u8ONtg7>{sy6v@g}v1=xek+;!&cmPPMwcp4CO+GAZ+2xGpN&-}|x8PMaeI zY737h>-25aZ@!6c;THw-R#?+5IK_5+a{)T3U&}+9EM^1P@y>iT^4o)OKOME;X)N>~ zJw6nh`!QI0@EBKWq4JA?E*D>|e|4_3yJEjY?}X7hc!PW;T`800a=dk(Q0m@q>Ei_7 z8wAFsa0o3mIz>C0c4h#Pz<%Bxdal|VL~VDRcgL57V{x=Rd5pndU`TuWeD7g*NOM{P z0y!p?xk(|0hWf0n97m|DJcG^xa?$uI;}pR;ZjWd2U()0eG5i#GRP|58dE{#rPO5z> z?H+pK>2XByc>OiY+$#kdZv^+TsL zc*mG3y)0AVF6+0{v(!Dy`QPU^ZH@;YemI_b=9zdL<6YC)5nQ@>F*}FzW7TS}A%nh2 zMew5B1A(w~fb+s!@jDgO-+7$z^}cKu8TK9L8b5AAm_BuK>_O3B)ygY^Ywu$m0@y4n zec2CPA2(fdSv<(D@z=inR6M`+Ai@`Y0(IBJe6p91bSR7Rc7Wz7cTj20S{aWSnyE?%?NXuH`76RBcPjDjt|$Q5z0GMz3RKiR zJRl$G>ij#$0i!m30?m<1=Qb>OB4>}_ZN26(P8RpwY&eBMI=OwrhW!Z6Pm*8;cgxR> z=U>f~+;(7_zn`Fsraru^{8vm4`? zO*?X-VDW-EwB3mqVLQtX_{rF{>u{XlD!twTtoCD1VTg9@8TVvV5YMB6;5rVi4XL{3 zxvlhDljs}J?AWj~wLKQjhlkK+Ig1+qrmZ{S$*sr&@*NbB4lJ%olk*DVbPP@v`)IE& zba1KzKD#6ycx*$g-}GDYo_F3ES6*>B#)a zG#V2VXp4j6oRe9X_Q~`Gz_X1ji0?UgF#g4_{(Ah&|KaE2s;ig8)EU#`hwiwY_RV#8 zSQd zzcs;LB1`S;yyRT|a}s1Pz)KGPJlUXg0G92koH`g6frN(7z-x-Lvap z@(Q11rQF7EoUx>%w3|G63h~6D;9qzDodD)!iAbq}-}*(61vg#gJpl>JGF8MH42_jE zu%0bLB2?3oX0)Ghs*|rwqAUI;Xx@d(t94(T@Ok2^U{{_KHzOD?(-xjFUy7LNQ*%Wy z#PKKL@Q~UYL`vSvdbe{g(90y(_~u)L>;%!u3*dMR)4_mY*P`99SL>;UC2jB}hX!}J zmAX=JH%z?TrA<7Imu0G@uXT}VWSDSO<;*rrT*=`lzidnJfPCm6#JNmu)zs%p!^^Ff*FgC8`S3=sqGygV^6vV_;p61taBKsfn#!p;LW8ahck+%M3SR1TY{g_C<>eMeY zp*;pJza*YiPwKYPx9FMlE=U!6F(E{dmqtko`XYCntzX9+7yHj*ZFwT&$QgFS?bl81 zIFj+~USyYg95 zIj^wo!r#EIa}5Pp$L4;Fc4gVXYa(TtiIDs>yPW?A*Lq!Z)#|up)x{XZnh~>5d!NFb zs|UlyPd@Qfyzs(Cgb20&m|MXQWF#hupY6)GM3G;AUqIliwZ;X|fUl||& zWH-B~)3KyJD~*Pw@j?{;wBs5Ae?7rqz|JiZpeetsOo09pt1o`&&T&ur&b zEp&88Rr_Dv?lNJmyn9ktESobq-hJmyarKp}M>`8d8xZ4mVe z#ZD~E@8{|?=fn%=&LvE(L1|=rDm)^6ZCi5Md$51@FHG>&a4C5s3epG_ zCjIL|Ancel9r?kvE$tdjrLP$m&pfvu?GOcIuCwH?hXu63K{t$w=8CY$lr#1SqqIBY zX&~A8$ar{S>a<1i=u=x_-s}T;9o>Gk3?^e3PYd(?)cc;@yAjGUcFdKEs?1YRj9JoF z;MrX0fV6-IZ`vYl<|H>_^nu@;c}pPBceyr;s*nb=t zv=0^)JPy^5n`5=(W)H6nvSA5o4WC~K8;26x_)FwWAE z53)k;pw{U`fWfnyfn+ADZ$sRfnS&HC986sa6Lt}%d@e$*s#E6~U{g_=yzFFLFzB9w zsutEG`*^m|8DD4m%0RwXY|Fs!B&7(whSZ5%s*zGQ)!tGi4}5YFq5&j~99RV?b=v%! z5h(M7TsR7Zt7pZX6zOu{Btp`ga*}%@mkqob6cxPnR5i~$w340;!f(KOrG!Q=^vj*| z1`o?-xDC>Yf@z%~n`fQ_B!xzCZ2S(unU)6bLPtNHpF(}A=R1fBi}*QE^IQaQ^T*fx znmj8FGIAv{>015-ELgxk)66qYY3f;1h znPGzlaJ&|={u$FuQjLhmIv5wUhwH5&ccwFoEK&}RCQ1;kutJTDmFOpJeZ`fsmIQw5 zO1XS;g3C_>SJuemAVf4>@*d$%vYa&fTMQYI1U|7I^8Qxhrf^h1CR`tf@$zlhB`*xW zzUXPVehQ3X*mmGfKAXBHUl(F5PtB|THZ^2HN|lnPz%3#9-SCn0loy4aS4?80>OJp$ zZ*1JSDPDN~`Mg`%`hP85sf$`8LKcY&5PyX)9kqn7a9?c8Q|m0MoZ$w z5m4*2p>OFMM7^PV(xHsyDW=)BvKF9^LQC@|PA=G(URyB6(O{yy;F;x3n|I{(Utjw2 zS6Re36$|Fij>Vj9AEZ3bZrBcuS-hXVfYDjucjPoR>kB-xU-6ee`yMwfmM&S05VSap zT4JAXTsxCCkzhAuP z-ne|(N8-}O6QiqNem(dTty%{D3*Qn~U3OV~@xBLQ&Bh&Qnhr8wWoH@zR$6o+ z#2^uuISB%1&Wy8vqaw4M z_OQ!Lijt-64tyrUbCX#xoPrQL0gKrEEY57*x(8u*ciM@VH47DY`k!9r(q}LVIgU1? zy14CFG1OAY!{fA@K$UrQq;uyE@^fzA!Q68S3kHXeoWfx8e)=*rc&2kl1#$}<&o$KK zIiP@wT;Wk3&V7&bI7}YXU=HLw2)In4QS&Ds8nwq|4j(_2YVGb;fBpXNa24cC=1lJF z_rwtz#}Gnq$2d03_~elWcCMWh+Qw2N0K;_sEM}a6_c+hYdIHyBQudx6Zck#->g(Tn zg#O|jizLS}%!gq?j`>WUFb$q16K>qdmIDoKd*hI;9D`Lb0Az01d7H&~`mlfXtN$)O z{_%IC5yO!NZjYFX{N>s96WG%DCO2Db+_;TCNgE>5p=Rml#aH>ve#gE0PH@#I=&s#+ z<6r;UzmHFS;sXfxt76fTIT+WY&x3g;Qj9h0x5d}K{vfv|Y+Vzv5y^Gw)jUzG9}qXP$9zo+Z4(~uHfbYu!LET$X94jY+*&Kd4cYB@P3y1U z8m$}P{7m=UIk9Z+yf|_6M4Uc!gq{0|F?T5zOcyR@QqRgC_b1xn9NO|iY+3VEEaS=r zSFF)2cOi*J#h{qqFeZ~j2h+3XdQo%ZTrW9!4!qBiffhCywfl(}WN-!T9IAKSFt4lX zPC{h&b|<#3URU8kxDMc{T1=P>XTBxeff(T);lH(@k;S#wvm^1v$MlpxlTN-Dzw+y| z^fQ8!0n6j3?BbWSKr#1Br*P|lmsj@W!~=TJd8qC*nO*uGXy-)7301{A5%G&WQkYB+ z;b~;gj&ulmpH9o{?)1-MMZBJ=CtLC=*9eU#Kg;TbCl^>Kzt0I;yrmC*VoNod6j#bu z%A6jpuZ-8E+qHXlmb)w(n6m5u`y_o-Crlno!4`a|Th+F$6LB)rJjYAN=dl2J&i{1$ zI%%+{ER!Y&UgH(m!uL60SYLe1tJF;?Nttw1fC+WPmmviq3`h5D)YAD?Q6|^H%)E_%^T1 zr!9>jq*b;B@-;l^UvVXF=9vU-fb!hpyOOx|UdtoUv=?AG`E#*o_VkN#(Dlrle9^*X z3|wEWR~y>HASBlXh*SJ85I78B#8WGcnfcP5X$95tdy&ToSiTI?p^4k}Qy%%whbCYY zgzSx->}4Glz8n=LlN;QEQ1MI94JYwjU=Y}Z!_9!Qy(XfiO#mf>o4PkI%b=i_Jl4FI zv?Z*?7cB%#Ra}!hFq?dvI9Z$;sf3dA7yyV9feT={p z@NAvBtT!JSXRXH^16_D!*5(-C;;c6wI9?5~qh0zt79oi%EGO5JD)Hbo7t9;j!f)Z1 z&jqKFXUSg>>6%xQCa%8w5vG4xFQzZ^1P#PFVbp@RaZYhP(|PW3o->1eMkcFs=FVo) z>6pkE!vxxia2MkV#mGLDlIDcmMFDYioOXP49Grl#sMCKCOY2kIfg9rd`9h8eaE)Hi ziF0x86oy5ak4$IMuj=yv_-O%qJokdT>%~NcNxPGLjo0?F4+G#w!NtTwKjUH^ndXO@xdqUWG{coT~ng5lI(o)%bklRcUXXIKqy1%iTZ-CEBMxWLfAZyK+05?`7ZeYBj+7Fc3^;#>VoEK<4=M&5k?UR=@eLySrqSm&kx6q zufGoA*SW2HYY==(l$>LMw}v;*lJG2bbe48<4mEfex_Z@0$pTs@rF`;^*S__!F{t+M zz(lXtMZl&FIi~|C*VJL#0ZpM^7S(!zDJ%t90?D8G3XQoBo*7g_hQ$FjPx{HLp9P?U zJtyGJUit#>qIXe}1)u#0qG91T2 za52)dTL-q*epK@N&mH5)$vBKuQZE>#^G1l%lzj$^B^~hYxnA^@*W9wL{xxC;zo&fYGcrj^%5 zXdGQeF$v)_mR=fNmtZ(!#qyYQ>~!p2zloKcMKPI5r-o?&a4rMajLv~rymD1M%PQ1y z3^vRs?A!_NPXtb`V9|i{yfdBnfW3(;sKCzw!9kmjYa;61lQ5_vUi~Z#48Z8!G~lvg z4yOgjIJw%K3QJ-DG4tA{(;{2?|g28~B;VbN>qWs;9{C!t~l3J4~--%bgI)q~-Dy zvcdr2jprQU?9cNU9GT1+dWEYRx7r;r&nZ(l%g+Gsa}h+H z1UsQCiyjqs6X%~mD2rwF)8d)t**N)cd_L0EPTF57MYPN(<27}bwMDWr`1z(YHnirG zanr}Iq;{4i>yEn6%e)dbV&{%wjY?nM|l^pqrRHK7|V@GpY&`({24pxFgW5=J{P{pXyRxeCEuG>@kzM(UOe-Ctgpn+l&yFPv5DG*{x|a814^&s zI?%l69MFwM&H#}J<}6AgDUzZjiVBuA(nz)(#yQM-eLOR=*7lw`J7;%i*X!BYGc)U5 zAKT-x&e*c8Rj>k;MJiAfNimZkK@cR7a|XK6=-m5#x8D2v2MAJ>Nbfl-70~~CufnZc zw{C@dtLj#HoG8w$KqK*IJ!E%{F((IO%A5g=(MjQ}*AmUfm9@lbR@Dm_nmy1LM<=*S7Ga{d zgH&>g`YS|~GHUeBw%$b@w;{+__tw18wrxEemtB5oES|?C ze7c)$z1^{D<)XOl)*CRGKf+eqeR0oy55?!c`dy6l^?|>_9oUHoF6+9kt3(dGbJ(dO zkdM3e%8@f?1(X+skp(fC%Je)^kRM6$oD+?WPGT#eH7@2{?*mUh#~tR=2vQ0<%!&A? z0kP!^`r{M#Kgzb@zm1Rnx4#w(G3*6&1QZoB%qN|LAlNNpLHXUczb>x4YGd5_wY%ec z4?i2N%q1n(1Z64P$EAq<95kZ(ptK7OV<$-PsSe2j6LFj0aI1GBs1+G{p)*ZfB1wg&IXsVMh>HAfu%>2HWP#u;-3;%uFnXMK!So?@O69J>Xp!keU|+1r09bWd>Ze2i6o?Jal&fSRTt$P}!K=Qt^Sh-*8x zpU8CJC9LueZWO|PPa2#-G3Ua?No1i(ZFks@z^m>6aK4!RiD&C6uRDZYtaC@L!frb| zoV(#!6?%R6b;ym_PnMuf1TeFaopYBT31(AN=Lek*&B8)`n^nc&e%Z z-gETylK~F~Z^24t*Suv2@rzl3?~hfNqAA5vJ@-bSsTqnft}LMoiO&9>XkD~Au6XM^ zSb&ny8rs+qRod4{|Qm}m%T@x9#^tdt`=5c8%yHUyc>Mr#@QpM$RFO(aBi zI&6zEms*?@B!dMXfPMvimbT#ZJJaLkW9FiNw`iV?Yx|P8@Dc-@3pgR zrF_N5yb`B6LiGe(!x`R;VqFF!xQcaNr*{(!<78Rs@bcYo{`7P5QQjS1z|QiN;3g22 zkBIqKAyk*8;3%IITm`9L`F3*Z(Gge33jGwmlM=!*FX82D4Kcl6_UGJsGx7|~EJ@~X z9a*LA}# zK40`A?fGZfUe2AD(oJP9Wfxcz9AC}9dM1qX;8XMU%jI9AH*Zzk}JXi;LjI}QL1Gn5H9 zyw2pg@B{rTW6%^rw+aoNI|S`_b$Lb6EPcn&}U>9TC0QEpVPRkXlMp+F!$^4*i!NTaAGZ3e^>w66PBB62Z9V=~= zyN$Weq$~X3HVc6#M@8_kU0Hc`dyyv6ha5z?yj#!Glz2W|VRviqFyp;(HJ;l_9ZSnh zMZ0iodN6@MaOhy1o>tn_r?3(a!V|``V#7#YXzyFv>`-f=NoOn>qK~2!>ax-b8XqJHy(^H zef_?;=aJ{xF~JQ5D1asqW;CjoN-JpzPAV`Q6|=nfP$}tenDdH40t;Q<9Z{moX#g)mT8UVpWldq{A2Z)znZG@g@14j+; z{cBfcm!HkBjVmnYRyy=T z?Nxe|9j!$PFh+l*>|q-FyPQ`8N8XztOnXOFqe=N~f_CPSTz5cg1FemI66~^|>PM%s z1E38M<%A>04$|IT-AAsXFB#!>i#CL|b{N2w{SJ;^bat`}3F--xtuM$P?B1T=!%hX2 zCU~WC38iuNuT{lZ5v4YK`H66^iD0jhI(tURn4PSxP|iV%lpQF(shwi0#uSDzJb&ZB zmV<>+;o6*}$-unJEP3{XPT&-0D7vt84{Ksskrt0oKh@n4$FR)!&|P;$JKCg$OXkPg zYj5Dp%<`DE@Inq}Jsih}9*?=b3t(=VC=6tmd4@rH0tV`CWzd=89FVK`P+*!4YZlx4 z)zVIb-8~lCunmu_+x)g!H z$*n@CLS}MX(!g+DGNPTe8a%aB=|xOxz(HA~hQgRs z(ZJKXcJd}X>7(F3&Wgtb6NpaFS`wxLM>?oTNtfg(G!X}h;WNvX<#56wrI?T~L9Cx; z@{tszh8-Mj!loq#`3t?^gfHL42;vNFa-yE_3ykthBGU;2kFw=-CdBe3DkWONuW2p5 zFLJ`*-&rp4tm0M=VftDR*o{1l+kheNg(oObCaCM$EX>CaT>?nsLNlXD8#-iw3fFjr z7k$H{a>h%aM8>=MtHPvM!T>>_&(0~W- z?6`HhT7b$JB|+w!^;G9C02 z^s?$blenNz(UA|~lu+@b0Qgx);!z7y_NC%(ygE$Wb>fyZ1yD}h8tF@DM*4w2ByP~| z{E=r$P=#BUzBYao$jkIsVMaVPURK(kbxM0AvL$w>+=%U+Y;FI>)yncH3ie?PC%HxY z#KB!$Qx*F(Q$}^}^&n@+n`blRL*+-b{wz5Js zIBy1Y97Cq~|8v$8nF+-MSH6&fsu<=qF&(zGu-^R#l5s6hwyQB4QRB_ zI+OG&FB~^1ZkC&=JzLS)Wq>98U3+)4TK~p);^D{R3!nciD|Ov$!(JI1HeMVHmtT;= z;R&{Om#INnpLN3SoN(N>0nlVa@hUIYc&^+Hvpss0YwJ!i&pXb11@g!I1@kfVHZS@S z3Y>r1FS!yw!oouj3Iz%c>~`W$#}4iq@8Zt#ks($ADSzgbeSrEk(q zNZC@TZ>d)i(p;pmG*Y~^?YQ^_v%hZ1y!iXi-xZf^TpMq^Y*}2z{pZ*6XAMbbn=Kf} z<4^32PkiCtczp97ltwJ(a2{U4Jv(_~34fe2wsa1}|Mur!j?aAIyK&`Z>+|0B-VSgb zA4&ss^3d#V>WsX#!{OY@zQVphdmO@Xk;%5-#Y%KHE4V6{G*~%?(KpX-cOvk$w}TmH z@ooDP&}9Ym_)V@>)eTxV>@lx2{cVTzhBZ_-?p$ zkF3ueY$hFE>C9VaeBb>OTb+Koso0QD!{|bjUGj(%8ML_ANd=e}tllU)qD1nuMiGeu zyCU1kGfpOHzvd(_n?k<#?I*$6L%(`gdWso1Nk^-#{xb+7!~CKq@c}ColZ#S zWTEZ=eX6m#fFlC8-S*bly=xce)rWG6yH?_Jf`cYsORRQKWpx6Eg=16b2d<4KCo0gx z?LTh4v!gELqtjvwO<_eR5i+TtObRNRWyj3-On&+(_-fdN!O8;S?5GlEegT4f#lePR zTvt0iW8aH_?j*=gs7#=&K@}Wq-vPJ0$`AZZqqSKlcH*T{z>du{ovx%?Fx(jDm3jv_ z-oOgMo;`bL@J_nQd-WxcZ)gKDatSRFzTEBoKb^uX8tHRjd-H>9>wk@NEkCL9Z3wMw2e}Zwf?pTJp^m z6rYK`v8dO?$25Ldj*3kM*^Eyel26lTK9)Is8Yvs`N_h229+~Bfqc!6HpqDzSJ1i7L z;Q}Qb%~Lo>f6aO|sNZZ@)`$ z6{!wP#+{P3N=ZR6g{sW98F^ zmO&*!4ckfZ3=Yl3Te5| z#ZCH39OE0-tSm|Y1X#hU5X!O}AG~cVH4UraAL=2FKeVe0N5z{>6BI~j2(k=Hx@9Q%#W}W%mPm{=F~LH zzC=GV@Hf957xK%=A%ZCacq-Xtr5S18-0iZ4az3#P@YghUUW-9L%?^{*Oe%% zLWQBjspU5RL3RrIcdD21kXfa0TUbF#oXsbfHNnBej=wy_(f8UFp;1m|E`h%abQMMJ zs&!>-f~~I8EK_P#UnKfjeV@jXcgv#Xtk7X?nz_yxMyyUCydaXt5JrXCJ@?8Cw|Cy$ zxcd6*xK_QJd$|w9qDwC4>^ch-NapRVa&vOwf%g+7rJQmf{*ji6V{QP@wj}N@}U9qH(QZg@dKBjGgF=(r`?hy)mKi2pk z*|Y`xhOl5xJ#%MvUH{H3wU9pxLHiJRN&|DYY#LlnCYRU24sN5YWl>?Ae#hn1xjn7% z{&(FJ*IaceS9{$Zo3Kp2oAdVr%(;#pA10Ms*KIS*z2IQqi*iUIUZ~FHq^Y$+K9pNq z2A$o6PmnO zZ{lD4;(OzwwM$|d3X?f=u(3q=glz?d$(-5kam5uE$G+p^ag2NCozJ&3m$xnCR&Ty- zvn>exz3e{OabP%}e(pQ5?ZlzD<$}KW>G!=gk7vx~*vYY@$Ko(n+YcW;6c0c02;0z4 z#09HX$Bx~*Vl}(-Zn@=F%G?&acI}O=o43Ua+qc7W9T?7CoY%tLeB%}IOTYZnTv^DC zS}fX~`$_zwCpxnyY52D%5`^~b3Zfe9A29N^b^d1 zg)uyQGL|n}8aKZ2_0VuKcD(R>96xpptNp9EQgJ;;I(lRK?mhA7Ll2>}>diCYJt&LJ ztCPFvyAV9-Q5ch;fr=Z*?OvPK&MEGMU&IX#z1&ZKjJA(LfbbLSwsFqw(PZaQ&i7S7 zsMK)Ru5)4O+e%nb%6YcE?1GXtr|GAsk$qIqEMB}g?P>{Az88*ihsSW!mKeO+O1o3J zsIo|>DG$1Z)bS7uov3S$o~Y0;Z|hV;hh5C`-3qV6yWwg+)XSD)TcQaiyBStE+c#Tw zi9=D7V^!$ccQ{9EgKy-aasFvpf7WzSO3(yLTO{#Oj2Ir~Dn#+Goot;vZUdR|u7iIp zpVIjs$w|RxDmw7e`P70v73G9;k^v;E6z0kyQ^A)(PQfp??!jDEjFUa9-NAN}0k{XF z3hORh6WgCSlp1Y~=uN@EYCT)r8s~rw15R_+Ljkh|n8s1#CfAJvuZvE;RpSig?R79Y z_!3Wq+&bvWeIJ=Sn24i)&CafK^XAQTP%ZKHx4)gv=Wsm0xe&kYB+hVVOyq4e@|6BQ z?R-bkUMnou6B*C0I7r!O-L`H+cCw)Wo&phcNyP(sx@pe1`U`LQ^5vj49mkKKD0w@` z0$chU$H_?Ta&pMGgNEmmySuStz^c0RcBjCx<);F8;Fk=RnGc1|%X`PNP=jz`vx+$b zP6*u1;vK=ZIsN3Ny8i1rbFxpvNPf>rWEQ5Bt2wt)r}$)e^|Z_qga7AHt~u#z^#0-; zYBFX975!eL%+3R*${&8ru?srXbt7#caY3V|k95IFpBdUoz5?f53hQ5zNKD_$vjUpa z%9{2Kcp2DWrSfI|by}XeD&%NAgKZ7QN=tm|JjAJBU166fQ~-rQdcW_4)%oh<#9Ei- zG0(~+-qm~dyT%g_V5L%!k;1g5NI!7%>3!R0Ibha4NgD$5nF#umFPXNatK(PxdIF%v z(}*QK;k>7k#wg|^{`Io}%e?C_Av<2^YJT^<_D?)(WDR&t9e_)bDyZ^WY0tKCcX#EO zmTkL?mr2)*?RiYDfn%J|DTFAj*K|msFvpHE-svwa6~=Bu&oqoXuBe%3uGlk9CtZ?4 ziadN1MlELjX5D67@kShCOe*6g`BrI&Njk^Zau!wPk3v$;G%0H;7r;xBnwLrfK=MI4 z@@G23oP)UnbB8=D&D?`8WMZc2jE9!rNvuvGzP7<&-P!;7OyvXgOCw{%OC>Ie{GMb^ zFvVF}Iz^5UB0Qfw7Q_3GM+^3Y5>FH<$3bAMr!8)O$J=7=+U2ZPpN`G4i#^Q6)~#E|S>K2SY}J0x zd)^aozU57^bLY<3yZ=x;`oz=m$WzaA;{bQsBlvj6-sKtlx)gRR{s#*YNg5^|d^xV1 zW^S?<;cx!Z#j)^$wH&j=$kym^{NZ1IGM?JHHGch{{Y+f4_5$XE+}F(a+TbMNQQ``vN(y${EOPwhYu#y$dR#3dbt_1`q*r|7I!W)1}Lk@IDqxSqa# z+60O!-sL5ah2&OzzH3k!m<(O|jr`7m!yJU0C<`Dz^5GrkSter?=i3mpxoFMGxbfNx zStvV&K)Wr5uwbu}r;TH9E&LtF9>fdV_r%tH*t+7Ld5_0UQwL)jYpan0nDG3x9reNt z%Q$Y^)&b6#2mk;;07*naR5B9peb?>r?w@))3xFdCj@Ud{yEc_=w)wZe^=%07yW)~d zF3y#2)6SmF4qgCh=Hdm6_1VeKZQ)P<>@VV;uiq8lx&JYCkgSbQ{y$&BsN=rav}IdNB6N?j zOQIWNcMoma8Xx`V;N-dtc@h{^Zo_8yMk`Gwo!*MIHjV;+jF6NitZ z&^Q|F*Q|?8Pi~H#yZ6RrS6rTR@^63pTe0QYXXCAJdn*R!R>haU_6@eKPx1#}pm3UH zKMUUu4xNk-{M6gx4Ji0FJ^olc@z}%hvp@T@TnV`#zWBv2r-JRGi!bKtyaTa)+ctJk zxvR1pqnmR8Lwy3Po83M$eUx?tB9<;&5g&N}yHGL&%CtjqF#itHhIgd=Vqc()qpYUl zwhJSnT__X1#i|WMk}W80lP{=Km29KfS(%R_^0G@ViNRBx_s4ai0D1he$H5_D<3$^& z&+*u^YaepOAXg#w#Ko6f6h{v2iDO4liqYV_`f!N8?1?8I<4D(;xb=oNR?MB?e&T-q zaRhs7-#=V-92Hs1Kww92N1a2l-A8uXcHTC3yC0_o4vy0_5Vcfo3}Du<4AIBA`6)U8 ztS-dLHLK&);XTp6aB<98wlcS?4e#5@y^(tYI}I4DVA~WLw^?k*PeXZh01g!NG%;sj zZnUscKMn?!NmgFyyJ&xN&2= z?z-y`Xu0Q>hNj^duU$|;K6vm@c4D34Pe+(57|slUrDi(Mw(w==>_o@2`>6>duB0@+ zowuFXX;#;5Jg$%!Cs#_qWt44VYRt+cx}rawUt&wTx(Jp<#X(M}R5C~>CSG0>(N8C5 zehx-%PjWJHf(e0|J-6Yz<3degPD)Zs?1ZJ%WlmP0RX+pHvUN-8JiD{uZ)X6Q-CL9c zg>q7_q9S++t2jf;yMDgaAsL=RKmHk3J$)yVf5tA)jD6ORyk}Ugot7NB`YFtrI3=v{ z+l+L>^PCs+&jIt5L^dve)mWR5UP-bF*{Vh}+00K8fX^8~4Ik2(w4MMp($o{ZYATYcn?LiN@|6i>4Lhe|)G=+*iJ|4^C)WbT}2C5zhp| z)>V0#&Qv~t!e7a^#<>8@6q$G8Rz9;#iM#pRA2LBRT^)z6GkGq*&9=(gvc9Ad{`R!ORdH*4%TreR z002nqFP-RAuf^ll{F+Chy-+NJm)AquOMg{EH}Sd z)&!QyW3PED>0GVWU=xBpPu88XoNbi=RmUlOZUIX@COqkzH1b*Sv^omSE1H74aiyIk zvj6c<<%DtFM(Y-I>mgU^8TU9Cm*Jxb(UXkno{>iSMP{Ww`12jTLFxX1>6KZgr^q?c zw~p|b5%`iWHSW~D3l8MzPK9a4RCf`8Qo>X-Fu`$vc?jv3Z@7{z^Q@4qSk1(nl`+b2 z&5f_an)dQovVK*xuUr^sw(pK3XHIcl9ybF4uaCQ*&%|JCduD4q{`_rS4mqeYZZsj~&9}ZK?)uif@wIQ= z$Mwco*@h6~tV+7Y+IHlb-E70e6&IcL>DK2ZOP0nj{KC)0+Q*;3VBMy8a?3t;5cY#t zPuz0J_3^-CJK}He`bd1~PyaY>#IW6&VRD3LISmpIaEJY_y+^q|_as7UKRB0b>Pn?r z?vk4pzB}Q84s1VJgXnY+U@Cs&yU|Zj{#optaPxyaH4TGwATUpH{9zt~?CUOF9T%=& z9c#b&aD47---}~I+Bafn3RjZJPtukb*$7;0)xP+vAH2!cX&QJQI(|I2e>;*aN0N)VozuNnL(CI(7fBGAA5FJ{MLu>h#PKtQ*2@d{rmTQ zGj4k08{)cau4ArR=I?7<5$8`Oh|081gz7V_sz3A0Gcj-8LXL7QK^ynxXhYb)>zm(C z;qch;qwK`k#9iyxu<|_~Tb|w&7hJF;)~s3vjiE5I0JGs(w|-;%i{Jg1@p~Wn{kY`P zOLHE5^)=UG>E8S2+2PT_0v}fA$G8z=-32S+mfPMIhiNaTPaQ=d-58f%aars?gaN^W zQ*qJ83t6e}i47ap#_L~yU94UE@8h3-@WU*?EsHMNTwB-Nc;?ydz_!nEi#a=6IS%}R z4}K`ttXYnLyo)qzV>!DD=Jd^pcPw}Z3ab$m5(At=KON6**&6#1#&5gr&2iDi7skS+ ztKw^11NYpvJ)GR|I=wc8{E_&|*1hqOHEZL-3s$ka0i17sQ})sGSg3pZ9e1SSa@DF8 z@x6QRWhcYQ*t7FUJdfr1J%_gB^?Fn6eCX?+n{-SY6ZG{%D0Et8Jrx@-~h_wvgxkEfr0I==Gtug0C9`uq4_|HJGMWo{i-GL+rRZIDF-cHv;>7F3%AHN?y~rY&wZM_*0Df1KR)}pFT|rL zC|0go6xY4sbr@_s8lU*==aGf5!^f>5C)lCWg>k;Aj?p-D^hB)WCbjJ6WpY`qJbog6 zUvt6UexR9vb{%!6V)tivrDagh!PtQyw&$Rh9Vi{7)>|FS(lRVs`zegObfPKj?dRM( zovoc)YEl`r=n>d*(?_FVJ3VJzrZFP3={w(u_MzhpgnekY57L=>*JIhMyN zat2Rn^noocXuPxnYW&)0o%C>3-qi>PekVL?zdh5Vus*>c=s>APzKv~jot&jHzV~AK z)Zj`QjsT`B;(2C=4D9mLke@RG@D)~0EWt7HB!06qu1bJKY|Sz5aRvxA-a03eMXA6f zqx$wr3FG1%WQYA7XM5<`|Q@dXMQ0XQsIfWb)NK-o<`IoT}@Td zHxl0&d1g?{XavbmMR_6r@SZT_tn)eHm#`U-z+~Xe34)$duOP*LAe9CsPM!5j=2n%pIbPODCa80I z$<&R2(l*$E!en0~RAw(;cG_;O^$5r!wwETKlFE*rSy~cN^s@}om4D5+n88f(z$Yi7 zwdapWM}fWyCyuYoom-M~QxRU3S$@)4*5tu_m*3Mne~eN-<-ZySg~5_;rrt`Lj3fNa zqvR!kM#>6c)=34ghEXP)z{#`)UIUfPPd=;gAi(;o(`IL9WD%pEsaLA?G8_N0O;@n( ziSR0}j+9@N4Hyl$>1Ss7Kl9g1JW?5uz>6Z){>@3G{=Vl}LtM}C+1;zi6o=XsS_!Pc ztNojw3f1YVWHru3kj;dmR$SszIK_DS7iDOnoAfI6V!HgFbSX3?J_&045|rt|Hw^`4 zRw%>yS5w_QUMp8%`3rRLa7=Lwv(I0_Efl`*-n~1oI?8rS9X04@0-OT0xOrwYw^-wE zUAQCc1QR`BsxYvxa;zHzHqogox4{?XLH3uxvi!Bnd=hf;kp}Jz%sAv>xaqB0-{l|2 zqeKfh$)^M&h9&*nt>>7W{4UN4W`GvItk>i}742-*XD*|;#8k{PcBF7s4Mi?kXN{N< zeBvW<^^-pfXZcgH;BElRfN)nI{bN!>6qODmjP-Nlf|cyd8)l~+D`p;Rn_!~70D*V! z&fW3kQ(I%s>LrY~hhsirb356>dtiTbvjR7A@L(KcMSKA_+Dv2pUDw8n^dwhNiP!ij zivkGG-3sRj2I2)`78r873j&@3Pv=qg&r-v_dlU=ZmO~!YSe|tw%~GL*zx5z2%WOMw zhhQ(tpq+d6#((z*e;Dt0%T00VWtXMEvt-GV=tdZt+t(hiyZ-elm>)TH7=c|OmR*(9 zXA5(_L4>TFhXA=n+~f^-Mxo#OS-x~hyl3&;xR%w;Z`}1jJn-l?(jWj1j>VeQ7aWbmH6VUe@MyzulW&jF4u3}YWc zH;q!pa?97Y5d_Nz zKM}7LVNzij@)bl#U)n#sNm-q%o;Y^A+LGVRB~jjzAp8d6pi^P*JVPf8{tCeIo_!de zrYrLVdBpf7wdK>kgx8`y_{3B3H-G)NIb<<+W{UD(FDkk#b}Vh22XEyA@kN_A!8 z?NipY%?`uMrXQF)4`Kla@ME)1NBiuSn73pg_U>gjLEBXP!ms>%thsP0TjQUIM_IKV z8C!>u-6hOpHKr$bPb1i`&D$EJ*2IM4M8v@SK31CB;uy+_E_Rzv!DnYsvUS57UhUV@ zHyh>9iL9%2>(+`T{U8fu>`a-346zht)%)M`E>^(3X^Z(iF=k`=zaQB|J{n;cgY{`& zH%XeU+g^x^FI$s4TWv>k=CX1QejO+jS~+fGdi%mV5XwLFGaq1Az=Gu8Ih4P<2P2cS zjsR_bktpW)zv5x*3mZmnWv4$z4v`TzVp3@ zg9UsP3T&~*28QX{S@;{6*A<(d-W(tQyT9RftdC;Xte5t)6$Qh^@$Prt5hE%SDa(e9 z8?4^A`R1GA9q)V>M^QTBrZ?Rh2M(Xcsy#;@u%g*Fdn^vqUtRzD8{*1K*2lJ;d*j&Q z{V{h=KlrSPH{EzcTz7K)SgannsV#6wR!7t=!+WSqN< zK4viX9^C=_(tb+`{k5?C`6vxQ&mUVy>Hm>jqXE-Yl9<(#+MZ&NwbngL)&{pyXLM8y z3OrL&NK01W&TAs}?TKLw&kP*Hzy*T+xMw@M+4jeo`V)J1vOVoc4DQ_>qes~qgh800 zt&hfHw6LcR!{l^wDiNH-rS(VB4WRX!X4QNYMt72@bCGTv+bT%Fd5ML)c4l(BC7JFVf2Q)w@;y#BmaJjs66?9j4UHpyz@94@NHxa%O5Ud6c*OEb*E>N~Ed|#lN&4Q^}`BO$=)|l}BCw znOr>0-|~n?^_p?SRhU`UA{^IgN;vW1F%ucjel+_{@HadKmFBee?{yvms$4;ffP!tp zYJ?eBQK7~IktXBh1Yfl4nUj4n8Kk1YWM)SGHLiY_yadS`xMy76foO`%%1L0RA-=** zmId4`o5EqUt5P+4y{h+upTD{pJRE1Vt76~pv90Xq$y~Z;UHi^I?YB6d=&usMTU4?v zmX$x@c)xcm!mQgg9m7V>Xh6@i#vB1Fhu=wG#@d3%Ilt0Qnn8EV50)9BhM!^NpL|S^ z{+=sUp)<|ustO+cGCr$;;^$5T^B0sW_!*Zeb_$fF^=!BAPMj6`cbmyR!J|zQF@DlkV)Pon>=^+P#G%NMc0j$}&e4060sVi;h*w6SU zZQXKhJ)@-nOev$ZRG3j2AIrKK_Y268_jS+y zVEoaaf1HUR<0XdQ&LAL~ccGtY_yeBQ&v#%Au!^~8*|J>NQc-^V2=}F%htYJz&o*FQ zDv2sru&8mhAEmDOC%2_wPrX(}0G|0dA7@?(J_{Etj(_<2cjJHgi@%D0`Jvn6_y5)J zvTNXIeCjiw!g$J=qbkpa<)i))(GaPAdQH#ZqfYs?!6Dh z>#w^!)?d&WZ+^?|Y{j?!F^WiK+oyV$xmPHH26SO1o&4^;`g3!&toQ_FIY5mBuDj zf;x9{C(rg>d)WFvo1MXH2xFHm^YS*1IoK9hrsvNi4-khf`IFWu3yXssD-ph@N{(V5 z;lb}e5LaW@V%cJL$S8Y(X9xYm@@3cpKn7|JCCCKE z|DM~nBYyGcKNLUnp`VKVySKzY+<$-U-n%zG^q~*N#TQ>fo~?0`Hh2(w7w>)Fds9yE zIF&Xmx}fz6b}gJ3+yNalqCJ5jNo;&jx9q`2DR3q}_1RCdb6_WV{Ij^_)>|1jq|am= zqRn1;<&_*ixD6U$^niw^0*Z#w;xvJa|gjPI$J)o zK`Ojtx%ieAIoTtBft10|r=4o?lN$JBSPuH+r*q({o#A%y;-TOqoZ^SKK~1g^mT?Fm z+_=Kdl>(Is&>-nb90xB4XVYbw?I8S?PT+6dnT7f03XBznb7H2Vz)om36ARDPjI%vP z#lkR?fLvvBa3i(DNWlxDG`R{CQ7U}Qso_~77S7<^@)V5`v6u`&Q_FC60&x~w{eAK) zUzj$(^0mYW}uE$rB_Lam*bS;PlJ&&`0 zC>b{gR#;VOq)9V<8Z;`zOFHT&O?~Dh*gQ=~J9eVzpBY)tHV5C$x`CH{p;mNE0P zY{su#zWdD|&~hS}WhA}u%`ydH`Vadhd9>hIUs5ReBTP3VnF;o-|F*%%-B59ZG99zdk*DX3g*^bVW>uC;_BqSk8#nl!|nBM5m!J~f$hXvrGSbU4cm^gsw*s= zb>faR4Yake9a*J8sdLL&u&E;EBgX*!r4KP0yRR~|{D`x(PkS*;3@wo`<;SEgd6yjm z%vw_U4lvS`bjD?lz@*&zsmrXAUV)xo3~2I6;W06^{Dr^i3#CtmxaIW*8zYpyk2wi* zk5t4n6PG_-c;F|~Pe8X$R%B;!##fs_9SA&AjH_M1oQEBowjt=oPN>t&N1kIbt1CeH`Q*^xlIUPh7k-c0KV}Z2t5!anaQ`urjzL4)5LAI`q_Ba1Glx+;7W5?rr_dmdy^PRDC-=SDAe`lOzMf?nNht?L35#+)+l!b8O*GXG- z?goizZxXZQ0}{+V5Q3QOA#Z^zD~v4@ap~Fx@k<}RJwE%Dd*bf^pWc z-t*BvCiQe&iM4l?N$w)Gb4aD2<(CB6s56)36IY$rvZDCx*5?r-Mq|!A#x{^CB{m+P z{v~SS1dw#VMR7o_66hRAUf>CD$+s7+9*B3n>H7HOo!`rEh1u+R;Qf@XiIo#hgLA(D_f=k92P z(ACKogWN+ticr? zi9i0||3m!ufAG7kps#k#wc*%t&-I7TW}Cd`n#*XboT6Z!dCS}06<1z=BXjj01nwj8 zo%=S$!6WPxIL;0fRiV zw}>=XaMe79#_VRbVn7;&L@LGLpE2rej5d|Kg=tqsARUi4UUgMmxbZ3!7E`f+O~`lM z`w&MN2C+l&PTE>4I|tym9)x_z=#G&tR>9Rd+Hc60j$>!&C&uX4+Bmo0#}1tl+LB~f zFS={*!PxxlHk2CeocF&q;XJc-TP$D)^ZMlrVvyDO$1xuH&2Qfu`wkq1Ml3FN_0w@N zm#58jcJ!h|numeFOJd$YD_3ZuxPbQ$p-{S$GyCf=yeR3pY17lOd(ZAzvvvbYs)@V- zV%`8peCa373=d^lyyak&%kBHHb9VUXA$Dv;%tP7mi@*9yvE`|!r78haY8OXelfFN02RAV#9?SlHFzNF$gk=Vq*+mY=aLb#xR~|`vM!=a>_4>nH~_M zV#C_&$MMz;MR^Ei5K!n3Hrw_TlYxOzJBQv$1=GuFABOCktdkn90tRr(X)RuAmPN z7UK^j&Gab{Q$G01{w)9eDYVhU|NN`{fTc6;*{=4e5pvQ1B^-znaEV>u@@_PeI04DY zydL`L@J}TJ>7=EDPysFSo&J3HvAsyYG8mYiGL{i1Cnc_KuvDKr z0bHeZHOJcsiW8y);j6}}3aK9kozEG)P+YuA;_7iu^a8w;tw782SWq3$@>+#eei_#M zQ$=s~I^Vk`s$JGc{qc&PGihHG{UzvgZanMJi9)t18CjQQY{snN{gQMqF@CgP%RN&k zB3|&w2{0AmR(p?s$U~1j{76prUA>b(vTjOcW#%=USBA;U(C?K2I6D@opG)>1Er&W4 z(308sJ{Pb#<6UaWjO#RKqtyImj2g_@64~Hwq2&H@Gu+xWo+^CuK{p|Ukb_< zX4Xyq@gSgi)m}LI8SX!yPFx#XimRq>J`S`(%r;`4^yB%?t8iu%bbLFx#)-XQiD$l5 z$cj(pN?&Z&#m{FQsz7MC0+*2Nw>(bdyI~s4GkzKYC6T+U3Qp!~SUowfGHX02r}2|e z1$R@(-@+5`#KE7cqH4HFF2gH)jhJBa+x$yd!f_T09>Nt9g?jt-+NF|$k5Z?`eeGS1 zx4G1~Sv@MP#Uyb9cgNZkj1n8MW-Mh=>QS!+^Ren~Tz)N=_GYM+Z2u#yK(%VslGkcV zUPw}xcfOso^1)Q$*XuvQbyrSaAbM^+OatYelHgy@-06Z+CIEYsMq(ATJ z{3zb0(k0r!De3fs<{5y1NLfdSFq^BSx9>W}x%JUlyQDL2zx|H5dvE;Fzx$7I+bv#S-OGHTEl#m2uHn7| z2M@<~cAQ*%;igphS+ce3)}aL05S{E;IeK!MRrfYlrrA+4=5=@+ci`55KmDsaV;g73 z*REcPLSiB|ZF(eDuUNt=H8(J@^K=Nsh(_B~4B6)_UABt;p(}QxC>R;T09^N6u95^_ zw-l4-LKI}5{?fN|SIJE`-bkCB#z^Hz-1*h-##-!tZCtZ1Z~i*YPKF5Se8}#}_VC4Lpg;DEooaOi~`mTo_-4xede*?F54RX9;Gs>v3 z_{`_O#tQsww$iVUtteAAJ@sr%zUd~;u@A)cSo)v8csb|czZefc`7E*&#uQj~mDcvr z6Damxcz$af!+_#46eYj-tG^N(?t3)8{FSf76C4M+>Z*(2ajwKZM4h21n8WS}?NV@1 z2byyG7*{)b)4(7$B~A{Wfsgv)yZ1jDH@@kHxB?1v?M=mDb||e|!!87l z44odGj>XH@<}rq$p`&2Km80+_y&&{Kn5WFs9AVL-zqY~}V>UD@trY}*g4}B(*xUBc zKrpS9|-Rglxc$)2PeOw>W#kCs3oW(Yk4tsGJKP|k|p-l5< zpaZU*m_4n6eHN=AmCV8L#M7u{QsIEC_4|4oqPPs68e}W_Aop;ha-%~tuKDV!N7F}5 zI9X3ufAhv`p`Ri8&x9GX@l9~jOAIrkDxUsETJInk^zIl|w0iHkUs95|{l3E(z*sy?N} z(YK2=GvH#E50s0HCb zSgtUcmpe&JYad>_njcGHOYWuQ{Q5~2`Ka=$1$@(&(n;HzuL}(`jQmWJ5cw%WdcoKD zsSGAgU3biTYjR|wEN_*+@DflaPl)ODTK^=zj%WNcEBpK6s1L_Y@YSd0zk*bulVga6 zTBUI+*{ug6yFK5DtwOwgx#Ou@Z57;91h=sb6o^!Ydp>>uckr31^E>oIpA-Hori z49nmH@$pZ6G46TjX$1axj2m84=(g-qha{tJOI_DAHETIWersVdXnK zMXA;8weGQoofn?RX2(ADswfGsliPwhOXKU`d6v2QrdT{Mn@tUM>uP~oShl-v18?0WLsYs_CpXPX-{4ayE)#Fz?Rjv*tz#m zE@XD0n2@x?LuaC=Yc}Wh55({N!T${1Cu43u^rX?)ZvN!YK8{e0%?R!%T^&!BcoBN9)(ij+07AwPm=%cUE499cO6QOMRDjb{l;WR{Po{_ zCZ61MMcUtZ@ZqQFFIwVFH@^uZczv-KoVIZj#ID^(>Bqbt)3Mj`qvSyO@qhp6-^S3- ze;|$VsleQQ;8Z-n;~sVqU@RON>xJD%;=qx+;tg-SJ{D2WdrzE>!-r1A0gh;&Lg|C$ zCKhEG=b`5rcVOFp!CPf6Lpw`0_va_W&CFt6O?gX8EyQbrqj%{nc%y^QZQ~k@V4xgi zu%2QSy@kKi3`WlTScgEWS# za@iHhB@O4hnsp5bIdpSW4Q-b9*bmY9l}Tdh%8chAo-SYf)+0GB!|LEh#24jNrLP{% znCMkQvny`Es^T_J0%h_P>%aT<2`JMM-lGXvjRRsqh%UKUvx#B^*TydzvgeyqX z`)7Rr9Q+%`s?=!H@g=sz$fowUgER

&NWYf=U+D2_b3T9igw2n< zqEMB)I4mn|RvQia+b1YYWjzAMH1+#A)qnm>UahbAyd3QfPo#c?j1so#csZY|@_vcX zDup~==+X=#>-HSDrM`((1FYd!&jvl~@C10)MCZ*3>MGA3rl{jzkQ}qPpH{AF)j46dt)V$2wBFe60$#N;8XC*_*Lo5 z%R9_VZY8a9fnIevN__Jvu~I23ZsN&5`{=~8kxxcU{1Wi1{4w9MtzD#?Hx`=s;kjw= z8dh;wXedsE6cnHp^k*`kN)P;u@3_#4^yRkk>WdOMBxB^&N) zzV(x1jroH|;w3`nn5b2GXL+qN2uZ|LR9i1)P${AKi*M4HFa;wA9ciuL?lyCE0iN}D zbrm_DIS05I7ojRw>sdIMU`4o%Z%_jbg)DJUyeaq47L7{G>rgaig8+ z-09)`RhLIZf!@JovBCs7hcE`5owqxf3(HdT!KrpvGX@Ji*Y$0r#GQa5AE;U4{ zjRdbX>td_>wd*&6yZtY1!FHl-fY2r%EuW(@rX?1Tc7<&b8hFdrFc#~F=quXVIh5O? z(CV4^o>aQ5T*i(TXzGmy!>3PTh_Z{7b&d&g1j9M1?O>&Kh+uE~UPiyT;4Js7||!IpY%YlmLiC22=VHG#p!7Od0{fmcV@ zocPxL&&1)cJQ~BuJS*q-VEE1s3R;72@&PpM;5G>E^FvX`IeTck_n=neHQqNT&#s?D z0V8j*QOdRN6oJx=n{_}swuIkpi-)L{6#7xyn*F38iv38(mkA3J8fY|q#5Xe+#Of^+*CEthZ07%G=JM#_4HoALOucCU?Ke?D5_ zS5JU!$o{!n(mI8fyLE01vVFdN!LnF*DT9iG6%C_>tu6}pZdaNl{uC8&m#1+BSNd9M z8m=;U38D!0Akc8e7n-59 zD=-Rl{i{x{IZ8&YPf-`V|@QASH0%Muky-{o%fua^DMdZqz>qRvoU0qWrKEL zhmO$1dp{lE{dUsjY$h8Dc{o|H127*uZ#!TooNmLkV=noZXTgtptnjHHi5Fz@YNec% zHAOIX88XR?yfSY6vzq8!`82uZs_B1za7G}c8TIo={DHnXXbY;Y7huW*uD)3pwhM2N7)Aq| zv#E-g9K19#>7-sKJ!zYqU3A4^mlxkd@l@{C^+04MK^04mASA#yT zHfk(ML!d;Yzp_78xGOu1%Jp&Jm3^K9WMZ92)VL;exlOEQA(T$(wcN%MMC9coRy9SsMiHf)B%VgPiqSa~mFk11`f5z2l&G@|h zn|;4Jfur-E4-1<$ZK;nOGZ zS4hTiRthlIkGxsHm$Fqk@Tlvl)Sc0UnE_d^R;^jpPGLS3)Od(fo}XpT;qihLSgC~^ z!(442;q?V2)h8wHHzSYzl#x8kb;5rM8y0PCplc|gn&n+Pl2TGgUFE^b)$ z3dr8tW8dwzSI_8LAGWLZ6tp3e-+$~$=3qy- zvTJ`ly<;!ys^f9Z#c*5lh!$Z)6=%Z#Lf`UHTU+m$Kr*3Ss!DZWA={wGC%Q*wRDp?r~m}KEQ<-LM<3>G ze={|Br&w)tYdt(jy(_Fsv+U=HJ1cKVC>+#^keAt6Ntq$3j1O?LFKqz+Gtcy~Tw;aO zPk32hrN7D`(wE?pMiwrxcL~wt;=XV00zvZQmVy-*FV4H`w`_ebW>cnKj{Lfc zUElO^;NYp4x2Qk5pp{n=o@R@`hVObX@-~}0;agb=S6Ma+ZeDlSf|2Pl=0ly7!(9o| zf7%2as)!{hR^b1+UN zWWQE+GE5@iW6Y1#6Bufg&hzKD$C5<@SzpfIPjQuB3yO&D*<1|{?~RXhvk`p-HpsbQ zVnwW5i{U!(8>f7;u!o`0K6ma?`mXUfg7NapHe3XJ?wR05t=Y5PeF1+m=ksPSy1QIl zmA|K`XKfL@?do+1nGsxnh5sEixA6>ru^`v673b$=F5m`GwqkGv{p1m z^D)>kz}=5M8`faO70r^3P_A}lL%^g}G+>}2#!rcp9wJ8?;?YgQUX2esKFL@+zY8jMY!yC6sPU`vZ6ry2z!y4CG9joZ&kh)B0`2rNfAbL@<;srQ zd`O!Vq%NJB<_eZu=xA&zbsBkO<^@C1@H5k9dRakXPQMH-5i?pDxb!G-GPg!r{j==l z$4?wEz_FPqLY=`SBc1oh>@(i^B1^XyrP8Oy`IY7(kmk6}?=Q+AdwWa@RA|& z0%i9Nn&zrmexz4Lk{X(^>rV0I=~LQyfguqJ&)KqtP~gnGmC3s2m%abkcDs7j>e#zy zPXaLQ!UYRbuos~MtMHUKEA$n9ub(7qqJ36%g~|`}Fx^ba&y$jHYx5Pm7e%gWrLLrA zKoxA07%NwL&KED!R9H3@H0i;&{8`s&*12phOu`bK>X~1K4U)bVJfS8G-%P|GuRa=E z!z(|1?FSMrX)%AXS-(`BNB;Y0=)4W1{A@D!L3BF`{M(Fw~HA3!sNAPNZ&to2Leg=tvE7DU0b zv=82mo!OQc3=0`Kamh5LJOUHnh7&BG;z&-ol25(~u#vB2DCry)Z3m{Q>)@>T=8*jx z5z|$93R-yP--JR&scTIw^_|D8M#|*vATC48q z$J2akI*MbCXAsx1I%%uj>;zqu(i6-FJf|&B7?+&$UmNA_;;`(3zTOz<>(4W~F>V={ zArLQDPRYEGzSO>XC(h8TcJflzF?gnsN145uMuDC+aJH*Ms}^@Gj3E5ERhM(v+%Pk# zVgo~ENppDDd=#)-oGC+ycHqsPU?tMIiYwI!TP>ZfF@%x2L4=4r3Q4)gh~L9iUQ5`v zkM*?}=1y)cytffQ>1p}F*Kyn}uI-()U&>CF9G_%0lYCMU3oK8(D+oBxb9Y9z0}zuh z73kdF?`|#om8}O)#P9s)(HhqXY=b7-Rb~_i`UQ ztrCvi2CSH#W@WFhb07u~u67?d6s+Y03zgssttBdXgA%Uf>D)slhsqk+K>3#~A$(&k zoxWg{mB!X8MDKob{DPb4gM%lMgL8l?HVbs-~%*RGg`BQNg31(X*~I z7b>>mQv!;QbVR^9a*}iE3**B-`~Fys5I6}P-TuC6$y*WzYsPUBy4`robMcjLJsDrU z_c<1f5wa1Oy_?*5boR0ELDrh^p^Z+(7Oe+9vLE)A1pyz% zKz#KpU&kQg3vv0nWeAl0v4gAf#;IFj{pbJkuQ+?JLFkTn93{r4O;6@gfX6mHk4+1X z-7@z-z$*JZw(Gy?jaRa3U=04mfH&pbzJFKj;i|>8T%9+E?fAP797e&^9amhso-^$W zWADC$afp8Ke(s$2oc%_W0?QZ8i!Co~kA0gC#+=KS$932mn1VM?oxrO7Q~R+p*Bcx9 zJ29l!9f!F(ZYOu!%YbWG>0ZvxoG#>$?fZ{LZ`b1&#z@^(EdC!me1h}$3sG)xD_B==96EFu#nWUg?(dE{?0|O1 z!&5Kp;A+YN6kPMD%W3*=Z^`h;)hH|M{n$Y0iIXTb4s(s^vPE7S*o9&SJ0aN8*g-!u zo1GGi*`d?J*@8iiKpa9rG#}&U_S+sO(lF@3lc%AnEBhVnJi;IzJ8fDpM%mv-*?Z@r zFhEgH|JcE`;H@nh5r=Q7=RuAkxEmW#rR~su@>O1F>Vwns2mU0K9~jFBRV#f(asRO+ z*&n@XR~KFKW%r7Q6_kS~P0M$GT#>h*8b+cXu%U2WN6h7qhC6oZ7}n`w4z}v|bhG^f zO_SGV%wo`=_B=diJy@@&(bHP_kN$`b19-rl=H5xKeIQn}qLpR84e7~=28TKP=wGq| zO*NH`F_keG@HB=by6NzNR&{ye4O1w0$PRR>v`IP^@>i*Va>5QX%V8OlPZWF|%pB~T z3{XCp%1NZ!G2f@?6mo$fJ55XO03mUzeDFQKxk>;4KmbWZK~&MNct|AP%%r^58KwWs zkAeOr66d^^SaoOVSA}ZnKt-I9LQE`7mM5RUBh0evR|aO|IGCB6`RPwxI#2+>LE5;iG-sTC{3+<=zv|tHyc)qD-W~V~ zc)ydLKFf!{C4u=@uIaV*s-9KmMyOuv2sKUW@A^68KLfuGJMXg~cHW@cQfg)-j+h;9AI|S)XGZkMRtqXV)0l@}6UwQR&LDjoaq>m4I=DH6v;_v9)w|&IlOOU~ zV&u0;OFONA88;_<_IkE^)9T3!Q4&_wh!Q_Ma$-uKmaFR-QK+R3j9(xZ0Et8PGkzO~ ze$Pmx%k;o$E_eN&%1`QEk|e&F0?aaPHJ$**No}sYi#t4#;pPF4=_=~r?^lgk_8NL* z1{KKiZdr*YNlcsRO_u2kE_J$mRzZnl)}M(R(FrXy6+{CJFSd_*GG6i*cjC~O*8hZ` zV;VTsbjfGpmOXcYX~O*P4}W|J!?$#Wi1k;d@k4wHrp7E^>2=(c7}Ll`xGB|fx*BH-KCfJpL#yagcfr)(`4p=)REF^gNF zy`y@H`SJ7+g}~U2VnVwiVoJh9RrtP$Wl@F{xJeZ<5Vk_GyzdbJjfKr3 zuTJJJW8Bo^?nQ6$>0?5@5-avCC=reh%u5A=ee3||=36m#HJi?J7y-JAIm>cZ_%wz+ z#^i$oh#3BwjsrV)q#!hlIY}>*X>S=oa}txTU~=ZS1Hr+ohrQA+Nl2cqEKVVTD&V%Y zDP)5yf$XV}Vm8F=pOenc%PeyBmo%0Nz|(@hf(dE|?$sWN*&M^#xSo|y!Z)s4!CmE- zGw*vJTer`|qmMorpXZuB@2>AdOYuAk;9i82V_ebKJ=q-_*dqMxN1ljxZ`&3NFI$`S zmF)^TnWrO;{X;Im;H9ESWl*~o={XzT&$;P~F1!Fif$;_%hJ~G&nu}Tog%Y^7v(4UH zm!=U!HQ+2S*dC{ZkD><-fef74UozqB3Xe42J6W7>b` zqEe}>!mFYSe9M&m3=>)v6;5ok9e~axv`Bs<-Y8ZC$HkXFM}ks;(5n{qiCg@cS5yBd zSa}^hNt=b&Pn{f!d%y9;xa`u4xx*YQ^(d1L44y#w)EU=s_xNbb!Z>ieEjDd=9$s}- zSe{{fJUk=M7qq1hIq(oa3z6;JGUDvdbJ5IWe9+!{Dc4V$%r>PC0%d^8q^dvh_=)XE zE>$@rKc)dpg@#;Un&kF{<8jAr*K;5I4atKsy)G_UvnW3Dk>86O-*|Pr{T=U(haY}C z?!5C$amQP4jrYChMn!;B6kND&VcdS(HJn9X1%j=yd*{CR*njz0ELn10{Mv8)I#%Pm z4`te(mCm;=A9uFLrJ_m^Lha=?{J>F5<5Ec9fF$-Nz0XsJC?K za%>@-iEn-T;W&1DD6jqg>37@;zP)U5Kh0HsC<8HaclDLmv8}%gYx&<}2f;AHcuV}w zue>{sB8)#yS-a@>7IKyGdX7&VJ9;u6dF+{-$F;<8yyb=sob%s~Vs1EkQ7~Qx{jR_M zby?=kTb_$ge)sXXdHssG8u~x7WgGQ89UIoHMB&!O8UN++;Nx532wJ>FbNktHKZqi= zn?<3cv4Zy3OWh7(Wq;HDLvetsQQy2_eau<9B<5rDAlV5nP#v4h2EWi^D0S(7>v4rB zl}nDSKmLFJd`$#zD-Me;hm7CM)lP=Jh8?x366SO)?-7XL_N2W*EfBM?NIQZCC= z&gO7NpE&wvIf+xs?3ZQ6qe^1=XPg=9V}co9JJ}!Xn&ULTzf4N<%Iq3ZOh?9`L(5jSy#G`=U@5?=Aovhtm2^~YOR7q2uX-RyCg%MI6xTaFL6FG_B?d&03c z`I86l{wejCJV6*%W#&U%a>iajG_t8aU-U>t0sNwK9w6_iWGp-eL;$*?Jdr|eHU8sQ z&Xto0nu~kkKl&u%IT`otzgM|VV*F{G#fmdSu3Z~FsbO~M+%Bx(k}$y5GGtvb&k=`Q z(Rbbf54&pVK7O|jE8NXe%Zc*{;uNd+gGWxqNjEE6YUUlTg!N#den71#E1bhF1ryqf zf}jI|r;Q_zt!$NaH$)r8#}s^3NGNbmBlx&Jt@Uha)WVAWEQF|1j|De{kIdgX!Fj96 z2*ML!vVA8F{SbFhsJjf~T2F@8${dC4E7vTE&wTa^v2tJ%p?(?nS}%{etlqg8(}FRt zm3O>3uD|vgmuR@Mt2Z8e_|f=_zxfnblNGxH9U4#Dc03IUN=FefPv6atU*4rZbW}+r z!$W5UGgo!D?bt~@aL4!n=bVQS{-CetuoXL}-M&8--A)G{qZELsdHDZ zj@J1Y2jm>FZQJe5q7FADOnIaT@?b$h*)=g8%JnAeewk5 zW`&sT+ItaLyU3>-#oZW6y3}F-w;W$7bjsSwIuqgi67{5$_2{x2#Vm>ea6QA^VTf(n z3l=WO8#RhSOfV&_n2T?#SG1uZoKi8v>Tb^Kt<(RPy7vIG^tui+@AP!{^yJVJFgasp z01R>>01|>okOZR=#Zs^-$|`BCElbwQTh>~;WtY9HEtPlWb!jchyQWtvmr8+@C{m;Z zl0wddIKW^6FgfR(yQh1<@0|a>e%+V>1|;O#z1{D<|G(kfbI*o_+dp81#=Iyt)xa zcz?P5wwublDePVoZ}h}&nBw{6>8GD6`+5erLavviDEFWaKc+kY1HT+~cYEK$1+>qL zd&~a)Zz7DkuKe(aZ(%39l<$4-d*xFP-d%3GezB#eEgdf>jv&Chc(P0$+gFxyg(5qq z*p^sOzVxL}+U(H2DP`4)S>?IspQkQ+!TpwU-#xdK?|$b|#=rjZi@)^q2q$2@sED^W zzg3=i;^{Jf{;aZ`EABeEO6<|c9xHd;epC6ifAVv2H~p)xt}V|3OHHGtFzw@SQh0E# zyo~*cpZdb*%a8x$=Q-wcusrp5PjLO_UT8nPeDQOiEWMLQb9=(Ya^LEQ%Zin&%ff|N z{fGa1_St8+j&d5piLr5y{jQz+%U8bgN9C#KUoOAT39VO~)XE5i?#ngCu4&h8(c*hzgn4&$0MFii!*8Cnlh(Cxapb zk5!j2wsM|N6E_$@akh&Q>l*M#U;;zIKNR?5yzu3oFjb)3-voDO=ojQKJ%;=s* z8mCU~$3?2=)q4&IQJsE?F1vUxU);s=pJ) z6;g%w6~fGcpbQ-zC*H)VMTa(Y48*_EzlO9Gp(!2_^FO2bY+794d?nZsA)*b>Um9Nq zq1r}b0pCg%2u7U@)q{(XoK(HTcq+$lj?)hfcVVKslt(n2WL2vZSr;`j0j6_-9D+P> z@V(|6=tjYs!ZkR&*H5KI5b3=lUuF0Z%=btT^+Ne9BT;MHeUDTT9Ca5@R$#*LHP%8c z60{!PQM}95VStOT+9(*a8ty3|H3e(sjc3qb#M`nGM2%y3l&?wad#$rt-Ws<(opl>d z&@R&Wb%7jho`rQyn~^AY#Lt~4!-VMqHJB5}hbDo=2^?7PRa{1(o*?m*xvuG=4~av~ zkY8z-H8#gaTq8T^oe)Q zKME)(u>Kf}%s$!{kLDX~jB=$QN^L)c1PV9Zp@o?n zz-V0uTeXgh7ud19$W^?f*;(!8{Sr)k7i!vrsQS8-&I%fpdYB)qTF)4dn))QJpkw#_ z1Qw$^&~)_bUN4HC(iEz~~y%!yt;o$?~s$>$l4Eaf9W<_uf~QELl|MTr;a&zv_C_ zY+1v>(23LJiKDQpeH**>hss}k`!TNW)Aj(i8MtFx;g6uT!&IGl*e+Xr9mdo7#GXu?7Up1i{3vIGdr_gr8a+nM;w*3jH_8y@qyH-#Qb@qM z^EmbhE?ziQUgJ8lGoOA4EeOXW@{a42h)bS`76KQ?E1AuU{GLP8W9^1@<>AMkDle?t zf>6P8;b^n;9VU*~bfo|(=Rn|DN7SS3G|MIfPdid$!f}nZr$&Sfvsz4!9bgDZ>fSiK zDTKO!QM!pR<1VB7J#GOso2n@982Yw81XG60{EwmV1#Y#m}%T2zPqe>eoguO zL-&@?eD)_`iq8@%PNT|_MT^Qg@L0cgeUahYz3WWefY5=^MmtpO<25u9D_86S=fgm4 zUe+6Lc!`(?{teg?N) zpvvAmfh+#7?EjtD%OCz<{}yZZQ_ytk;b_FJ(tp+?19PbRfiiPSXPMaDSN0s*Tb}sd zHt4{$l=T0j2e)zz=MX#b*x`Uqv!;$OXw{eRe*4eLp}pH-khvQC+>zLz9L-V54z8q| zK)NOKXP4K}6x#Oo`m$l&TFSu9Cg)Fu#)j1H?&vQMAgGwhnV2V@e6sA_xt^+0n8@z` z#iL~b1{NnHOc+0BN?Gz#pDWKl^9+K4N6TY>`{(7p58uzO{={;_iiKz+4RVVB_6ue% zD$5s5D=)qHV%fWQcX{%=-(XJ_8~OhIz#j?Y z^6wuAV?PqTcNEPPmJKANUcXB zx*fySHL91{xnkD`yqMbQXk-emPVxiJ2EZA`WN5?iV@Gt5Hl5?4ixnl>)p%Zc^d1R)U2xJ}fb0;KmulQG}G4W9_>!&{ZJIpojL;fSehef{p%TU@Y zgf|p5UeIhr88gRs=4*MPeT=A)%jZ&k+u)F&f9d%3zpeZ=q^4~Bnr}vLYZJ{x+tfxY zZuZ*Q6Id>I{M<&b` z-m$20s>U_>w8El*_>=F|yDL)R>Or){9Kxl|^Ky?(T}1BUI}#1U-{E;hK+yrrJM(9p zvjPR{Z}U7dbu5}jhGn(ABT1mxbg&>VV1wB-5Ah7op&SI;^2)>!DDx8Sx-DOE%(gD7 zE)OC>{HDL*rjz+fz(X*y%nI&gy8O+!=^sMBNSib;OmC^Fpg<4q74YG}MX3i|1_@TQ)*ej#D>Fq7$@yDOULOvF>Pja?)`ZeW;KmHI` zgI$CfuOa)WV~mb^w!j`gqy0 zvmb+NN6Sohauvu7#EneUE-+%ppA@5^H@BN{C;9sF$P>?$=TI*`g-0j5!WUSVo&q1RZ0?PtjvoB*O$alvGocO$0uZg!pFF{JkCPUJ zHp{wKUkEjCX)=gWwo}IsmJS%&MGIz>X;|Oizi&@4y}P#`gGt}W-S*qclaK#x`L$p9 zjdC+8>NBR!ENfqTv+Uc=S^6DY%g$~6v}Nv#XV-u4zJ29i{13koW5n0K`qi>w#esom9=Zvmfoo|$}fKT=eZ7UTlu};{Xe-UejQiz^>EgH3Wnp3bFJG! zvO=41cVa=LQjo-X^3&N^-W%iuKW!)Pa z%JIWTF=)7@9NhC6;H_qzbr|*k9p$a{>&gu)S8zstM)}@%A1&Lq?to_f<-qO-%e?t> z%I00$%6@DQ967MBtXRGZRr(8P2s~0wA3t1Pf$=_e=yPTEjNY>Qzz)*vU`*;S3ktO~Cb1ptF${GgboLYb6hc$SH`MAU40kWi^6#!y#Isj!0O z{PA<^bVT5K9 zH;z`cW<>&}s>MqK*`(F+H<*QngZRs}s=w@_0@s_eu$;F7#_3 ziaHcE7tS$2({Fi>Lbpo%|IG*Mrq%AGRnS)4)784WGR<>=Q|ra*iK3IB!mYm*=E&d3 zqs=q>goyabQ2m56gjoc&QW-KVtcFB+;wyY2o)I0`9r1ygu%o#|-RtLVCpFIs%HJr9 z3oYxq1=eTAV=xE{_SjufcvM}56U;qr3m~ob;bJ+;gV3a_dqZ)jrNe$0*8Kw12yqdl6;)Os+ znr_Iem8AV4Q}Z41%_%|nUbQ+B$&6{*j7nT1`yOMwwQm_%Rx{s*`Y^wiqqYg_E8{nQ z#s)~Mz9JMD6|jZK|0X2!PAE<0O-R7uS;jdTqulW|*nIVO$5JDCu?}Eynm5{T6p$TO zo#T(!=7s}r%V2Mmm zP`MwC?I3mkCa~q_Z9v`F51Mun=KGZKX!ij3MxbD1pmP^i+N~ScBAtx46EKX$5-JRq zd28K8#(l@rpabO{12cBXT~0t~*TC7>wU1X`bptCmC|D1Pv&_A;2fi8wrW*tSnXu}_ z-*PpSX-Ji83CC#9Jj<+V*}M;g=FOQ?e)FIFdb$4E1qB&NxRYpa9X)c4bIpHS9{=vM ztf_XC|M>MMV_ulV+~B-mK5BZ}$jmD+h`bXQzeOv~w6k;AdI!Ce>^7dp3i(`iO?Mx> z2xIn-%ZdfFVE0P-`JekK1T$UbyIkQl4lyt!#xdHSVw<<*TlP`@6FrbSmd zOFjx;T%TS~{h%Vw4bS6+(%hek>|>zjY_3?Seg%I_F2V{;Aov2zY=^U#3f8H_B>hLK${Fr|Fw z;cu45QCq)u#Y%RFkC%0C?=G)z+Eu#dPbv2-#k%>$9)uYPy|`-ngvV95O#nF<(4eY~ zlaFm#M6~5_9zoO@ZE2Agb`4=n2Fo0-a2pG)IuL+pgu5Rtl?xZS$_!f!8qu@;D&Mf3 zDnPItp35JNDuUV*GcnqB-@UhRtd|>i&@32W7dP4u`E^5sOPnJ=$5oNH+<1Mt{<>?+ zu3bCJ^UuEk6TG!N^s)O;VV}blb-T*CwJ(%?d-j+6Kk|`s|9y9qyKcL&Yb54K$f;lkgZ*z3uU|GKO=JKU~@Dm7vPGKx>4=}fcAnt+t z@8S&q{bk+j8-c$QpdJbjy}6E29@Ih&;3pb~pFOFI%>V zUG04#40!grld*Yu<4vnLrZ5FT!|P??qPb|o%tbgc5rc=bum!Lc;m*mjW5*UO)K6d+ ze0(s@T`=AA=Ux--pqow1o!d4cM0g7=mYv*Be;94b<7M@A*O%3I+{6`z>k%$2z%1I7 z^70GMl*NnYmF?TMq6WW_V*&@utXZ=-0^N%?KxbLKa#7i}WkXr>^rHwsdw_MY95`?Q zxLeCjH{DpK^-kk?d>MD38-d$v<;E>5%Qj%`L~s&gFk{xNS+mQ+#dFIcjxcnM@%W4y zQnY1+5Nlq1f;Kt|hJQN!sRu)XeP!ICG12sSM(NQf z%Lyzz&f;GCNi6pI`(Usy5!ZA244U@-QJg_jGJT1O>>LyDXeKAmt;M7S5)O*`=fF-8#LruqyGgaKARCuZ-z6d^0gMVbS#lc?82IH@@(`fJ)C32`$|QbjA1 z7=&Me{>Dv|;yd77A?j6lHyD^Dv4t&u?Jjd^_u;uc4$szK_|@ML(F5VOG*E`MIQZ8kc>dqIf5UWvan5HbJ4861F{ z%=n4dCU`_pLyMuf^(pHKsL;C7Gv>6&3z%&Li1P66ul-n;3#V+?)Kc_&Q8a(UR54Y> z+N+yjH>3O)(ay6T9T%jBYS3Xd90syIKjBAtqfAY~^u$%PDo$n?l$MSLGVaLiNH^o? zY)j(pm1M@L^M>IH938(rhYZ`%;4e(llI~)t&by<3o?WuOVCcrOBNf-03BJiA@*z#& z5cxnA%9!QCgD@H0I4jMVDh{I<+d9Ehp_k{ZFP%mskTvSKPSlVGy-%AAP*J`_-r^$j z73Z=)K5nLjh6K#2xLCeH)>4;f-`dWIVtJ&Had`~uqqwGxCf3RL zJI1SstzTeg`N_k4$Tuk|{du;`;BC8&wGQu|O^){C`U`ZlWAO6M1Ldc`@Y!=~Se}1%ec7~qKl9}HGJokR7-#DY8dB#XDs%1Fs}`%(W*c#Q z3%Wx4pnu~J(p0F7 zSJmsHbukYEOM_+B?*JQLm+T|b5TcrI*r6iW3XCh&$TN&Zg3l$4MjF-p{b;Z-KlXKx z&~hDH98*>E7VQx}TAA;nz#7!EwggS92e!r^(dL653M@8l+*tnlZ=WkKY&eQ4IvW6< z>Bj=Pb|5s0X9;ZE{waKN{VqfYLf0G$SyY?f`1%WF{tOtxF55TAx*kEEa2fz-IkPVw z&p!23nS0HQvUt&oIGUlI1vOzffB@52%8`S6$}4N0DSz|rgXN$7vtKWF-F16e3gdj> zz@f5q$qf1kw{5Y@yleLx?7%;RM!?eYk^6oP_3)Wkls~|(^1irgaz^i51ZN!MIJys} z{Z*{a_mt0n?#IiLMRQ<`4^UqNwQ!=odIpe+==6LSBS>-;23aeIK%enW>yw5Aw z-LM?>|0QMare1dNpO4-3yYIfa+;h*T!SBWpQrvL;(z0;=qF9@4SpNpMPrSyC__6Z2 z&wsAWnLV3Z0NySeH?1#=7R@X_`lFwK_7^eI_j=i}3tMM&&Y$|?r_iYB#RkB$<+-Of zmpgA?Uhci`zOZ(`=7ncr?%zfLH=+DPZb|TllP8{d0^!_VgcWy{8@cgpA3}_E+#qm( zUH=}AoZNfwz4YVJ9C_G_Er5=)dezeM3t#%_pyO*VJwp>5KvR3LOq(?WoChfTM&KPU zcinzNx%)$RhkE|HwQFLmS-BLUApP+m+6;Tpf;f&*&in7ZDbDI2IItI?g_;SQxN+$k z1d5!Aa7?A*FGX8Vt)n^@*v}lFVqT2_hQ?)EYB}0XIQ{%YhiH3t)JsRpt`GduI_Xym zrCN^UAz-DC+wzm&@Ht`T+|Y{MJkc6S3;Wq|hx0~CHBhE5xwiD&u)55-E z*X(&^*&TP4&73DWvS$aATPaiA9i&rwb}0@!F=*rjN99^^RI;){C%Ir69B7mP;;Gc? z0+zZ*qhdFH3g^9m)pC`-S)izkY!vAcD#lKNR#J^qpH0grhO&TTr5h=HTFs@ESM$&U zQ{VBRt-Mbc8Jm6UQ}a!q_FUSZuaM1qUjNc%@kG+_zbcWKC+9L^3_osaoi zGc;}uC5-2wMHCO{=F#>s=1}~$ghL?mDS$Mv#EyEY=}cv?xWB85IBhX5n_U|W!ZV5# zXoKILuKl?UbUe0!8hT7fhR3d0lqC~JNCU5yC3DX31{q$2_HG$x{A98+YG~p>FqwPL zpL%_r>hYkMUigM&;DXYVfY*OHAM2chGW(pzo6S@{wAoG_)VWh4{3qd{6pjv%5T;VHsO~ z+jRvVfY4jgx67PMjFmC)&2UVIoae!!pM3@0wQ@ zqM2-)D1uCs8pMVteIIWXk~jma!8L#LMgJ&2ugM$XQeygkqgfu2ud_EuLf7=)x;zhEaDh`rl(B= z&eUJ{16M{qcHm4$9P3R-jQAb?m5_(~4S%btgyly@$=_@T=_hEJ0rN2bh-X6LS{P~J zd2mGq;A2r$SNl4&$LPy`#bH5@TsU3Z{cHPcBSdJHlMbp*SYSZa?c6nL))67Z5xc z+{amZ@3hY&h|L%aK5j^`>;fk1E*Kk1sjPrsH$Pk(i7A+aXb9DK(-D;z)@}YtCtia- zUG%dU$0?Xsn<@BJ6T&F5gUrIrdO$y$x&{~E^`T-fGhmtL&YN52%w14s&X`s{_R)`( zXJ1^$m1Bp{4uIk37Jv)v=pRF?bNUp{q|ciY^GmGZB&3;y4Ok`oz5eRTQkLmwlbzVghAZ`rRj>lHq`4;`hv(591Pq?}zo zbyBH>`_Z;Z9wjmlp*6zV)49)&ceY!vL1Oz1e;%I*nnGI$Q$}NDy!0uo;d(gMxY>`W zLzts67)^+^EqzJDgV$U$1v?BRgE8-+-CNtPR1t&nEhXve@okl6dsS~_$WPL8o}UkQ zH1I4tZYgSeNQMS|0(`9xLxi8Mk8%!xv+Y-11pPB5c=PPYgKkP_>N-8#u;}ixYVoS_ zhkyKNd3nPI>V+!_S*NRE(?z)l>?;VdqCF}w;7{&C#wz**`8iIW=9t8J#5|aok`Bs_(mC z=9iS|+(hAr&Iw_T!LxAZd&dRNi;rPPerwsWZ6mwQi`aFZ0URni9Bql?!lzCg1MZ3P z%Z^MMudpgrf@Crs$(to|+-cFvkV^;qn3_s*D8rePgE+IBxj8_*!> zp`Nwxv2XX*^6WE@mZgj5ltt{M&zs##J3uO-;Ep2Km4o1;Bdfp$E`B;M_d@ckEc()>w`? zU?1SrQPlFEDL1TIQEs^DjxuxlWXb?@4u96kcrazsk~rFM^vD4WA7b>7BLhG7`A@-c z?}+hk&YZbrEH*W!O__*l{Vuc=)-C=Y(@BW2dyC1vNKxL!>mv+akTz!=ueQ5tC;8`D&!N0n;Y)cCf=^9OyRPZL+W zYsOPJCQN_jEfpBszqK#W-Nk*KF{s);%nvw@2R6Nyt8FLaw7lQrq4vA?i1vd7gOG^2 z7-2$j_!yvrI)Sz(K}O$88i_%&JEjx03alay&RJ9@Al>X_Fx|RkOWCn`GaceYc5D{^ zlc!IEftXghnG|MDom`gRa$|XehI#nVp~4lGocSQnkVZ>%35JI>iv^(*ixb=>Ix;6R zkYGBg4iaB!pOv*>@xpRaJQ>Ja&T_OlVWb2exHO!&SCa~iMiZG)_NHEJ2;uayGJ`1T zWk~LNHIdW12^^7Wd)U=Jn`g8*VDTTMXn}1#TrITsjAvHu<&y@|D*mJFhGxDlbd=Z! zeekLs#?a_2hV!ZZBjFm)>|$}_FPYnkqLWB-0|P$4Z7y+452F|{7t8tVw|NHa_}1qN zj!3n9O|h;J@p9fIjzZLuTrSQP{3t}?PIx@zTlK3n8Ah{qP&G?`uhvD}q_Oojx8KO0y+_p=zb4fb$llzn z)T9{44z2NHr;UbUoG2jiHAw3mtP9x9ms5wdc`s)SlccJ$s^Bo0EaqJ3%N1J|!-K9w z_SrT9f6zG2tiuqAfefnYI$4l)!%(P+=VDA6jb(M~oz$05sn$SUH)W7%8LCS$u`aV{ z0*|8j&{U?vk@^u|;VKkWlW7!8W!FU*md>-BuLlpZc9-2N7)VJkH4K0`&o*`^7obEAi-nzN`?O%U`9lO2do2YjG!SDX(@(;iKWmJaG zp&mSk>(wrl<80=fXP4Y_(dq*@H?TSm#M)Xf zbF>FE9T293<^);xp{da|h%q;I_kZT!e5EX#F%=t7GQ4aOQAgdZXE{a>@nCrA8#XaS zSNvKB_7h^dPL;J~uCuM$7G)w7c-Ty&cL?gOZ(IigoDS}lx2&Ew5Bm=Ub-}pwp$T)5 zE6HS##xrkD!sfz`JsO8Q9?Y`_2<>;LD9cG`8`s03w(KstR_?j|J=%--OG91ar0|2X z%CLZ+dCMRv6o4AENttWjqu+ut__&#N2^wctrXb|2Fg}g|5Zn1Bk7EIb_+%e8COT;+ z-T{B@g309;cBMCM-&6)s#qOuxFH$Zk66<;34U$MB*wNP=LlhY(kU`K9f+UL2hgNO> zXx1UX-MwcQcd4H)`*$CPpTL#_4CB1{^U8nv%Kw8^^~cMC1@mCe$AvINO~SJn@^+WI z3jx!N-udOLfA-g?!7nWnF;qF8TO1%m%sKn^??q^HrmR|deYBHre&espEN3 zred8QoE=jRqK>YhXZ7_r#`*HEef8_Ce_+HB2u+#7wToyjpFw-^)TvW!YV^Ro-ppD0 zUFBS&M?RRjDF1SHY8XGy)Gd5ID(yvsqj{FId1WtP<5ZT z0A7sa#hMZ?Jw_7R;(f8`Z`#?kNnSALBa63-ET2Jo0s} zO^QXp`6-< zUT)9EHu@K;aX8-b$+0%a z3$;>GxI4r*IA+D%#Q5r3!gjB~+jgI6ofFU`VLS>!5)HT$rc+XO6E8NMz}dcLT7|Cu znqE5xAN%NMxLWb!jsnrY9m{yMnS3Db?~kzuLGcV+MV3LL?zG8V$Dm}d;9rSoCj=Zr z$Lxg2qiK{~G@9|KQ9Sm@ODNKhfP#Jc;wd&|tZb5YUiFUPQCx$f1M%I(*#C@bdA zDJ!`8;MK>T;2J%yBZ)!D(Z$8TDq#*l4yO(Z;DZoB3#|@bvGYL1yFea~ddJi$Q!wCi zvRpvg=AtH$v<##ZW$G$j^Xq#I#z+up`ngDnR9QX^3`JBDo8G(`(lSPP2(toB&}O2K zbkZ3fPx%^tSNm1-Zsh=sk=bP)R}1m`h!=%vO9u|IP-xnM#f&z=Ea0!jjNkB=zKuU& zK`ZIwhsnXenE0r_799>B3a<}VTG zf+;|&v>gNUZ=Ozcs@uPYTH4Jw-^`UN%gcZG{XZ!G=*vHcp`J;ozWp^4<0V1*SojNz zy#3DVurNI3OO!btoA-Aq!ryyP)B3KMPkS9)F;We%j8VtcBkRq#Y|BlbsDy~R9*TRV zr@*11->|k%g4kJwfv|34AqVVXINPYIYk#hORt^2Jx~zNC0L9J*JmH4pRS@Z)zrjcv zi~egG(;LTMlLv@Q-TLlAvVM{UQEzWA*XqoQ#ZezSBpO}Hbmm*#@MoK<___$qJZn6D z8#LQ|zQ0Ga905z325v37B;ZNPC%> zxcvquMiuA5vE2dZ@ZrN@aeEXE$n)?l2U}GvEi2yU;o?&D{-8sYOL~zG_?9<6)Te5P zEIxI%$3Yg5s)^g39IbPnNJ0qDNcPS?##x0T=Q$G952NME#r*Ymw^N4D6^j3+R%23} z_zou1-YR=$ns7vFo-%%Xn=*ZCnBE%JbHOZAziS`Yh|QY|V=pMnn02qfg2S+!+dUSm zpIPkK-T#1Bj6GbgUwK{RJ_cCY54Z?JWfMQonPQFUd6)fU)@9yAfS!9W*p@E@3{4#c z&Vd`da;)1pQePf_=EZX0$Y~7Roh-MkUQs^xsZW*(T4jcD)|i?*sCo23p~?WvTTl51 zKmD1qY{{bXpZ?3AmqXm+JsCCdV`o{v$`GJc>REe_l)&G^3{!8U>m1!(R?Nn_IM1$Q zp)TtV+79(o&yq_whcm0pUJ}ebzez`Z+-0W@VL%;=>=Vv=F#_1Wprchomf*_nH^255 zp>?pnJ%;7;t(>L5ZSl0SVAj+SYN&2LU7HFpy2jVQ?bdDE%b)zkx5|3X{U2vXyNexS zbqM-gmySl`Zt_&>fH43jPt7^oy=9c48Ot0$5eD%rg1V1A_+a^opZGZCfXPJg^4yx2 zQJ>ykPQ%chK7JzB{I+6`U<6YGuASsh^@g9!lh-dg zGu~(z>-h^8hVW}5YZ2#-DO0DhlYauEZhyz-;NG%*%er#ijdz!ie)K`q+IJ%y=r6sf zrH|2pxMpNz`=iE@m4-PHh=_mL5F zjdTF*58b@Ei`copz^?Zj<<*zh2P1EPjLj~HbodBH=-5f0GkXDNEf0HY>puea?VpTV9DYYT)+5QdFJUg9Bn)U6Fi0U@Y6!5dge671U>FDc?Mx;%OCvy ze-7AF*hH1#cifo5d3M9* zug97c+Fd}1dCi>p<;I)uDc}6|-;})v4s!+a>Y%x5{*HrtcJE>*ehs%R?4iu3vGP9` zt%Ft6KdSZ!<~(+yyU?G4#ZP?lQ{2LIzP!0^Blsd+LwgAesKg&jT`*G9{-Qs{(GLkS-jvD7<)YEzI^+WU-96}59U4)#-8B@#M&{+xBLceXCwxOkU-M4Vh0wy zV@#sLEYBN;%XB7`i*FsE0>B4`zHlXj5>nIw=;*5MFiFP>CnrNE*4X_6ziyVGxU@YM!vs4xL1yyWgQtVO=3|&F{DG#C?A;ol+9QFCM@0? zI`SNJbW)}Mq@cg;s+N^n<{Qr@i0Af@cTyoDMLfTVoBvQd^R7^8y!aJ=>bqrFYGhzw zFwFC^FVf)MqFT;y@l!F0(g&&)*;c$^xd6L5lDc4x#j{}Af@+j2{+bp%rMFJ1_^jHI z3ugP16PSLg%{!>M2y#G-{79>@N#lACw3hN0E?mSUG?_{9Oj)vMVW{BC^gsCVPcpe- z`IOxTCDabOsx!I3@S_yed@4Q`Bc21Zq)$A4-(Nz!N;s8k|+{G@Pclw zm<=7<-iM5kiPD=Sy6imQi??>Q0l ztn@N*#Uh_74p~pp+#B4jH$UUX!t}5}Grl_?C%Kbd|JeO#h$4LRS6$KboWDY*pl?=2}VTw za*pE6sUv0T%+B(a|M9;qE3r+5Hhwv>_fUD^X|&)TI~DP)JFCp25^5iu#&$qIwx>=Y z^f-iZxDHg%FR?Sdv-4mGYT%#2OPdmCJ(0f%x;r_Kd(9tz>dn%N@buH4|9I?D4#HgT zK5(Qw_Ux-@SfG)>F_J;jojrA~Y}tOK9NT*o0G6AbS{TB+?w*ZS2h2Kcv{OwU>im(X zUN8TKzQ6MN>oC9uqtpdMJnCfW9CNOmg|QkBU3)0Bh7gaQKV2qiSPw>fz_mA!J31AJ zP#*}js8wWR_9=Fv+2y~8aI&A9C7kd2S<8=O_g1xgHFQtFBzg_6?R3J#DbY{nFIX1y z-}k=vXzbo=|7QpMi07rpvqL@^fxzs!^AR4OD33k9%aySr*V=JjT++4)&l1IBC35M;xO$b>ei{uzn+5wi||d zUYRjtCbY&NBe-@jE~tv%1ygzadbV;>9VFC^aVa_+(zEc0)s92g(OMuvFUzTVpO zb_g-%&YcHSKbd>uca^oTzd^YN0{>fYy@R#ZNzStGXYQPe@x7&G!MvsLU`NW4Lp!1^ z2*)wnwVQZMM3ug`m)j7a>-O#YIO1@Qt0O0drh{4sYB8KXb%tX$v&zjk-idb3f%43g zFO^+8{}O@8wz72DbujPKL#x11Xwkw2W$EJU%D2Ax-SQuQ|NrKg!mJoqmM>ctx1XIj zdJbF=_8~a>o&W83%blFPU$}HG8U>SJ%;|fy0}b`foj3ppO*zEdX= zI*qFM5k^7$i_t<4h^T~ajFuYvP~+`jk0xR1zWg!pL-Y8OMa^yU+Sr7nP8_>oUyxCZw%cErMsX%YPd`0q1WkmY!{{1vp5MU!)Ch z^KEd-Xi%;#d4O*N5p^%YJQL~jWBkI_=@2vTRAT6@)n>?B<6I8y4mmniX21MfU_vy0e zwM85jKJ2AM^Tg)z--CL@y#ppqtj)KOdH>fw-KF$L$C}Xn@A@^#9h%aGM>kkF_S5<41vh7 z3?o^5SuKX=uj2{1gkN|^Icl6p@O^%XyOa*sz_*OfLH=5Xr~~K|C9P=VALVngPgoUT zRyc+Q*fz8?ll*oJtFFnN+%Dtv1eRC0EnKvSYnIpnWOr`@{j;_M^QyG3MX9vQg^MMr zE&xXSsPiaCGC9T&mb)aD*?#N1t8@3`JQlbK4i~hjh^JTUTknWAGF&>@&KRG9n$XxC zWtkJ5{!l)~6w4t)SA|wG*)r#jH>zBFhqo%1-d`>={K6b!T1 z(`8*IUO_8hrSJw!%q!Laj9L74GoHDlu3*8%r1#hlvW2PYziW~6FmBk}iZRwoR{IPd zG|LQJ=Sg1%5G;fp6LY7XxJjZIP!49EU`T2S+n)POt|wWJ=5QvFv`KAc@n$dFKypd zzWUX_EWh*%{~)Y(-+RZM!I%kJcJ|Pbqh;sr-LbRj`S4Bz5}nZ5dO6E^Xc4nsY%Qsc z2i<}$sS)9|eR~d_DBpSH31FQldpYO+#oMpPI{19C4W>_xmrKoh%^h6ZE|iGAC@lv1 zJGm=+dinW(_|s*e`y1uiH#WoIjVosm3b-pjsPSh1P=60f05AHnxMA4Pg}?Cn!Bd7@ zq#e<+9hd?ajY0ZFNg`hDTPX~(y=0p)6JhFH*E-IPhEeH)sUPH4nbVg}l;8ZNe^Tzf zb459Nm>psI)lE0dDXW%z4jOycJwlA=dJ5d7WncL;+6(vHb1#C9Q|!JncfvFtfyv*n zVFSCV6R~)|ocgoRIQP;Apwotpo64X5`Pa%_l+m)o%XmtG`XvrKq2tC)5+n)3R*EDufYSXN~m9&ud&A_^t0gUAA(}pr3l|c8sF01Z`r$22I(_yFj~B zn`HDj7&c&fGsEdqFyP~;Yx;&qSB^4QxVwDr>}kflO&HQ!!5nf5VaaY(y6=Z6lQHfu zGiGvhkiMf0h1Xtw8U`J8aMb0eO`i?JcQ#bMCn6Yd{5pR86hh_0vDQ(=J+#TVD$t(n zM&g*B@$`|C<=H1rVEnC=Gf}howQ^1=6Q)itQ-P~i@dX5AdpSnpwA2wB913$_8WC6= z*uNP@dR`bF{?o60Cjhvw{=kEG#Tx4@eMupL45VwXPL3q(-n}Nqjb3))$3buVEwxv^ z{q2Xr6O9bCB@Z7tS)O@j4VnNm*|A4ZM?bXrIZpX;hhI&BjhnVmp03cQaaaEW$7qfq z2)IQ1a;N<`f`TK5kCj(n(Ng~c+SR0Bo_jGQ*xAXk%`;qQ*`>{j4mNhqmNolc4|@YM zdgoBjXjCI8bxho|izC(@&>utV-3U1+PUvK(|4jL#ul#X&;gtp)N183~8b#YXNa$k~BkNJQm-SnlHSLs|auK~r|(prNN{&haKEV&NNZmS_^ z1%V1$6s8W)KJ4MHOC1sV9mn~z-}j&?;YO8xS>f%zef!HTx7-}#h4W0ta&%~1dNeQk z4)dt7-u3qbVeBnPT-8CNjZs%TaPb4f3q?3DhU9|A@8G0V%27tkthQDJZA_3%j&z7o zsLasiIJ3qTFEs88+V6`jCXHayNlNtaDsXIZrw#Imd+oBzaw4pXdD> zlH7mFqC~LL+4GwhkOp^Q1VPoPL8Q49m2f6s2Ks13F=$g>z*t4Lr#zF9gLZgCAb1jJ zCksCZbR+YLB?w4G7~^bRtOOpw48X)s=GI(>Tr@7i(iz6Hu=(VaR71?G#?!CD0j}x& zfJ^liPEI<&(bF(N@aF`V*_g&4d;>&Xz?vok_(cZYEKVYBl#el)38i+nSO@`7dIpVv zV(=bRUHH^i(!Ea`Nx?= zCj>f2->AHOy(=H-))JfBB zqRJWo=2PQGs_;nIR8p%R!~z<&cg=K=jPS8*QdyLu;1mf1M%F8ff+hwz~&Lr>BmUF)HG@GCvr zUZV~(PkljiSiVM$F_2$z_anXStKu1Tz=9yg3*rb{+J=jtd>)piuts{AHd94d)LAW( z0pu%lIeF6L^5|oal~ZWY$cWiCTIq-r?@a-7Tu&eb(FZdFeIgBC?qryuZO1rROqtAv0BeoW=EKL4DEq3pN;m5f zZ1^NT=IFEIbH;JOSQ&d6)l2Ml!iTXi?k^|VmFqvHIw*@s7=Cw#J7^2WgRA3wIO8h2 zQR7iDjr9TJ?jQ{ewyPY4$)3A#F)F%?%VE|t$Jym{EZw41NHf! zG{r#JVqM#oL!<(Zs&>En`ug(9#%-+6azp1AfA*)!qL~=cg5emAMyRyv8qKwU{AtPE z_9?Pqt(|vq@n)s@vwO-NEW%&kd;mspxpWM?4%W2S}H z(btI45YHzbp`jhdHF6VRyB9>z-hl$ApDxx_;wq|5f9mY%EL-*;D<8k}#&Y|0E6a(U z`^)$K`Y+0cx86ckd3O2u$3Bf}{4tD;&81AhV!eAoT-gQQzHM7M%P#ZB9=NwGUbYA( z_bfY|)4BR>0Xx~}L)$~*A5PpH7~qT{_<-p3J) zxbqI6Y5~d=t$$-(nTw&i`ExiT0C+aM%jjEIh5d!jSKcZcw(ccO&XJ>F`a7tTLHLN! zIDp0-{XNt*0xQTlpg&@-6R6RjW9PLSq0v-0!u#+0NUT}hT|a*O2m;};+^xQ<%%8sq zgN_Iv=%d!5?fe9`zBCN1ioG@5Nk3FI-gQeC{WP!AR?y)ZDA!;LFzpv=ExFO*yYL(X z9CKu9&jU}b#bX?g*s)_9SL5w$%?rje?ev+mVYFw5KqNG9$lo=j`TXNw?%{1PcG&mq z-dzrJD?*nLSNlgU}XO2dYavtIL)@@taQ9p$Jh5ej^FJ9hxIG0@MZ&00{V zOq)^mAKX{=?%N&0a_u3hg*lC*ZeC%ha7Y8@IxXL;DlY?U-%?Q9gVwb-Ye9#E6h`C!McJ>{*zcYPoF-C5G+@Q9X1Zyty)(0FWXuj*`#6g z*QlR}#=EFnpE(bKx>XN+`m2Ev?s`i2LaO=D+8B_W-<`iK?->M03O}s3JW2zqJjeRk z&To3+R+sSV+tvMw-UsNSbXiED25uJ80m{NBisG!rS+Gw(lMzQoO)0tO%QT45Pe-4~ zKr(YGs`#7Vjs|_rym@8C>eWDVVV;w72P!N_FdQ-NRA<@q_LeelaxVnu{4SGq=$1h% z8v$J$*btct@-EUYcJ;MzI|jAQ0V>v!FPS?H{4g~lb;b^A4Afb&BzB;ScT{#1(!oAI z;b&2)Ao@{MkPL^%5Ui}IuqZbG5*$Aa<5npC4h}jyhYPxh-@x&`rin=P%l!DXJLwaS zfErd+Obs#5b{FwmFnAz1@M`(_7M_0Nc=I)1@;&_Zb6O&yY2zol+|VEuX`vY9vA%-| zH7)7%i*oDlJ8`Rk!|-6J1=|ohvf#@cui9O0)b@DNkv~u{_g2}4^3>13VTp!((gm^STP2G_GdUzZh^C(|D9TILUG>Y~D}OhMM?@Iu zTl=T@wCaM4YMF8ac51TrS!Kix}fM_=fLNLYsNr|{O#K{XLA#F(_R|?O80D| zL%76yThbUe5@-Ty`<6C3qx%$NLyQ&pFqS7WhGvY4oA{c)6KmpO8Eh|!fBKt75c*~M z@M!z0bZdD9I>c>tyjIBYheSL4qJ9GpaY(g2&++M+;suUbR%vfL%DEuHkY5wgc`E9w z&J#fuV`W(a=+%6+MUT|dfHK*qr_dJ@mv;vwT}3PD$1m^ECJ4x1RA1TQmWHvoWn8Gj zBN-^qoVr-^{OGx}C*m5a=vPg)2^U%fu5Adnqa_Z!TOGN{U^~;N%{8y$G`w8GBsOiu z(ZfFI$MznYe=?OU#*4Qm8IySDP?bG>id``3Xaab55J$`Y)}}_oBBp(r$Gl_PHW;B% zua@8bB_1yFW4E4kv2I{Y>tYAXe25(CwgH>#z8vpVagVuyaPRA8ea-rX^%ME^Bdq9y z!8%RY+~vzzocES(s7N1X*Kq6MePu%LB+j`{V$nUhTm!RoX7?_H2&l`m>nne$a3T$p zv0f2BN)jWgl`M_*h&GZ7P~M1BpP?*iq>;}0igk=_oHS~49Y-zq#%mXqU;eYtl>Iw4 zmEZoI-{!n2_f;>L8#|Mmx9lq0xe{-n1LI#%vpd#9v~`6VsJq7N9GHb>MZ2634m`E`XT zmx2lL2BvYGIfl?AwryIqt%3%;T55m!RA3N6n$^(E+yntCABIAs-5C<|K={{ZkZPCfcyoxl+Uo<6B5(TVXw4PN%cPh4OlPj&6lsJ$OMi9tbj>Ye9o6*FMo zy#nsG+i!{VmTxS5giaX!P~)4zv~Ff_K0KX%(VCiH`+-h>-B7>Cchg$~I-mXMgpsgm zb$L_*0f&OH6zXIfV5o;t#$YExwr+lF`e={QAT7J&!G*Aapgn>*&c&R^m|$DvJL2U$ zSm#1|G2wNNS7lyf#%o`DErjJHh`xQEaZk<4lWIMHvYRy?vr-V^cqQZSSe`;CD8RTF zYj(pzc$=FtGP%J_^XpjV$FjQCQ#(h&f%vIW(TN~xBAd69se`oT0hREV&Z@>=I&+Ts z1+63s=eknO4jFepau852;yS<$(6NJoPC}3->q^b?T9cJR*8Pynx-!`?hqryvygQn; zfFoc~nDi98851L7Bz3K&vwTs9BYG;m7pOLuf02a_;}fO(Npfe`>wL)r8S(@*4S_n6P9H5_BempehUo6QR~gWfG;mYHpWMz3WD0Y&<*lU1$%SLybr2O=m2a z`omgx2U2b)Dv%zk^g!J5*-5f&dgVeS{VcAHHtumX%;>n-QKT}BYuYTojo(hiq(t7? zv9dv#E<2x1(*}woZsz4nn=^7m2+Sg$Ij5K3=4pJs($kkKIDkboBMy(BWof>fam`pZ zX8(1uxXQ=yYrGAKdQa)qa0WioL6;n)hEgQh#64-|K-=EoGNV@6YQFFGD|nH9A1e7T(Qp_!feVd+!2yvrYn@9YcmE|=?5dlc`P8A`y8OnpFf?rSfA0(Y9{83tIS3$Eb$8|HG`@7T9)xhT^)SSvWw&ZYJ090 zgcGvg3fh>Ik$fv4*uz3W%dIY2Rih5WL{1p&?r0rfRW##4nCL^|VSd6^9m*X)C!Djy zb@6yPXL&N`OnbRF-?v`_TDs}7e_I#Sp9{tjfc1%8JnFjkmXr0=|>I(xFk8B9ztV)h*5v1Il};Rj zsb{QL$YI};N$F&vDKm181?=dH(2K=j4~(rlK5i1k_&{3Y$gB(iZ-8Ccez>d)EMOO{ zydLIwRC!~|Hr6ud%X#W!0!-h++ion&ZoZ|An>dYiZdcjOy6W`0mr!M9eWdV0?vOIM zsI_f5)B16JmLJN(v*iee-%!gm!exoG9VobP4jaQJ%4@q1mY=)zmh$P(Jy53fe5@Qg ze59;@^EFho*`;$gfQDw1yF0NqlE8=G z6D;zdN9}jl-owlX{pGs(3(Ajt`ct8?DNp4r$5*yZRYfh7%szGGIejP_n?4MR!5Ctv zuk6{6ns)5`vj!tx2rrr%U@N6?`C^(vx7^k^P*9EvjJBCpzxhG;DwGFHvSZ7p^2$puQomck;WWF^hsxq5E6cC`>OU_xUB9gS*pGcCw09o|_cFlk2ke$# zgrV&mH<`IeQGIt=x%}Gl@b{i9k3RBv`NTsX#i-gXW&ET$%u(~~+zz6JA@lDMz-3F8vcBMm2%CNysdJ}&%hqk>hU>2n8l66k zZ4ts$x4wY=3g<#K!W=WCXUvC`y^hVXuC?9xCl1jsq)t|*by_#@^z%LA!S1`(6Eg@Z z&J)p^nuxZPwgJq`O%k;xy4h`)e+g#Nu@(UG1~LD6c$hZfk&20YGGFr_`N6B@#LZ82 z`MhxPqO$s?>p24OV64wHplDvFVCeVnKTx)A-CCY|=GpS*>yLBWL{0l&=a(D*%KQZ@ z$*hBG0B@#!Pm0?P++=c-)^(&V$M&R;wiaBEdKG5Sp7FyFpR=CYX<+JnkNMfx#%0|4 z=5Io&FzQ%8RO_u60W#(#@Cc0{*R%XNjvD`ibRQsN|4!6~k&0HV6ekvsG(N*@*ftg? zDH&Tmf`NrG=tHuL=!Rc^zqxtmwJh^!tg;$+k&ZEc$$vz z=p=!QBj&;l>}SPc3gO3E7T>VDg!`y6>$Z!%Cr zxH|a=+V<+C=E5|0;8zy(StG`oy4d9>5%I%Snm5D^x@E`* z^W9|A4lLSnctq{Af_(E6$bwJ2H*^W_2ugqv7R-|Id>h_hDx{`Zt+69w3mY)eW@-c= zWZr_xJn9%EO$>`gGIgq}V^WqS`+EfVMdZLpFtO_AEkK3`p0=6B%lP5aFMK0z;~jvS z=K!L|<(vyP#*Pp?7*2cgokC_2ZU33h^0?R%_b3}6YrUsm1OGBvB@EJy>~Kwzcl|M+ zcSOL4eq=!OQOg+9N%n^pUgAq1vIxSk?;93cUrn7@K<6D}S&rBpF;1j(68s5q$EKWpx+F>)Aa2?YI%+1^r#8z-VCL9OJ-P&bA&Vj2(R}x;tLbivdUm zK?nfz9P~(!NS|K~r82P1|NT7%&L#neN(aaEe(=`tTpj16yT=ozOobU>{m=^o)q|iy zBYIw)M#V&bOT-&mNEe9XpM5QbP~y#pF#TKuDMT23kt=sm7k03N)r*n9CXpL z^#uf;3P&I)*&#UXqYc3Ds$t#7I^qJ0`n?zg8?VL%*Fl}(TC@H84zd_tP_Dh>?$U)3 zu2I~hY~H=7Zy(#av2>nBaC#2rh-#B*jzYw^Z?xu5+L*|)SlPPhAN9GZ3u5_XRLiEI z)^(NVP8VY_dlQDf&Y%8B83hA4XL@g$cmGFYY(EF{bOKKLJKuexJp9P>7)F~=cJGJL zW7pPmyknRzyvFNXv-4&v@)jjgQQOmeUVrWN@;xl!dv5;a%{$5;{OkX|tXMp`3~)bv zheto@bYg274d!JhG(8{t)hL-JY&;Na*S;g=<=3}yhW8B^Kz35?mrb?h1BnDNRBT?F z_wWoVq~H7eHlOJCR{-H^B-YC0KbCXSvtdlX@`rz1x)D6xdgF4KbyV$lu~UBVXsAig zo3lDl7MxlRq3S%yb$HC38hu{B{!Mn{xqqF_Gc{dh;7+l7zkB!2vUcs-^5rl6V)@)> ze+0&9EbSDve14@N{AL+onQg0KqZI*H2WsLI%FJow%Yl8{%WJP_C~X%E;%@4YYtlGZ z|2GeR9gFY_xjEs#D|2U0D7W8sU3qKA+hzS*s3)V9(t)Ogj7b)qGw?^XuQjDS{oHfq zrdzJZzSbPt!jy8)VXnmOT3aX{IOEl^>=;gP@*P*XSF-jLIWsGJle`6 znCF?Co1Z*oTDkMiJ7M5mgR?eKzy%1IePZ&tgth;-xnAxF2HEZgF-)LQ*bdbGTVqA! zNh140xLR>TeI;;njA(Zd(c`@_pV95?FRl+AFFdy`BBql+=*C8YjK1? z{_>Mw_yWffpp_Jl<$`lj3Mxahh+~zut>pVuzjwSRycz$+#5JDnF|=gl0m)b4rt3o2 zk=`Ni4NGz5AkXr2+6*{y_^44C2fNF3v@H}=t$XtgU=LDn7&GNqgGZ-5Zsj`BV?6$j z>Y%}jtaPd*u~9V6#|+Bw+{w@Ip;#HYR&^xj%l;Z^jmXEAXr476AVwVPQ~Frf5g3UK z{ovdO$k<;FDZ5zywTMEYB={(#%TSq;l8%NAd%%ZAO~vjjj^#YQ57)Fa zal!@7eGn~wD5|*BHfs5;EA#MU9q6RZ8H8+Fkk!jwtz4u_pNNw2;zd8;&_^8TXJSct z8dt9<8D7QNHZ9C*(Oj#tDR{G=WFJYaq!D=Ir+T0RdSF35TA3B5WUbCJ#k+oOxYY1> z{Jv+r5oNMY8fV=Nz2Rxb!#tXo#yfE{!>sqFB=K%o{8a)nhPCRaVRnpY99=Sb@t9wD z*Rb%g9-DaCW)fbgXF@Zfgyu-lFY7$}XV&s?ShXesQkFA{VWvF9bNx+p+Uq2I0&Tt` zZhM?s*Z3KyEj(job~(P*wr`KnWtmK5esyfhY9OxlQ`>{F9bDU7jjxv_%f(tE5akb? z+Y-FTW0tuYFB*KLsoD?G$H^lWS7rh1s9zF=VIAL%8_cf3v<}i`U(C4T7kKGYI_t1@v8HgQJnMKB(YuU??O)|zZ<(W=5vnmLW4^eVd^Y?sA9sPdB1iR z$}$QG=Wkt2g$F6{8(KUG;VN7MuT{^y*D{#8`kU{VG3n`3M9wsJ37oi%q>zOt= z!Y6a5wd(7GtU1C;eS>hc9ZID@U$h;o(pm5HCun89?%vdeo^$?rb`b~JUA%~YC(nJO z*krJdp`+c(G_mer{L}slYecYe*BN@Vcs`Bax;Nh}Kk}nLj_N!2m7m^C9B|;g{>Hbq zl&Qd(yLbWu0R#!$+1)v9N*OrHCI@xZkNT=ivJj&}_|37N+H$&sAo*?DWCc5XUm&! z?I>$EZU-(naYKT4i+k4o4D>)PfiVh;;Nk$TYJ|83*v0+OPp)}^YwoZ>&W`e@?!2zt zx_V`Sd}St_)E_?UFjN%(hA9&kL+s*B(Aq{^Vc%YPsWv z<=mivF)}nz7cH0%(}dx%eS0vZw}NN-AWK@$GS5JuvS-%;4AmY-Fy&hKT-*)r9D9;; z)~Z^&eif6WM=@r|9J_hTc7!Y?th4XN7D5;i4mu_+X?oyv9%c%|Y9|hGROJvKci^!| z&YCamxlq8HZ@86f#7~dDl7ryYB za@SpV(uV9SXW4b_u{3(QFYWRQjqdyG&tb5n@ZeGx4 zqE8RChaAsELp+EVeWHmcG5th+W*;_vs`=Bm2-2BGJ54h9-o366FUL3=U;Q{{J$qgVNfLEa`jM7? z?1j=$54V_Cu)bH{+GGbA4!Ekx>u+6DX0bW#=*bY{f*M#EBsxLgPJ&6pytp8mg0& zy5?u-rII3j_%?s}!d!#sZJLP2L#?ZKBs1dsa8l|6ahF46sE{-)26t5@Vu9kMCWG!M zV*zQzC?QkNjKDD1T{P?-tZ-apChLP?zko%^9;D+F8maWfeyo6M!E(p;G8(n5bHG~r zo$r=j2D4G9@m%Who>LlFv^UPyXu%VSx;qD*NQp-=LHnlxjBzX?B<%&%)h=>2V}Kn4 zP{Lr2cN1bwl<*c)RVmdJ)wfvjAoMOYS1B#Wy*5+YuOwig=rlsQ5Ia}O}n(N zl(ZV|F3MSqzsP{AKJUU^EJHxW1YuD!rKR?Xw%ovUA#YyZA^Y&d50hsfMt`_#^)!=d zxJVpyaMCfgP(s*6*=69B&U)s|{DkGiXiTEUSIs^thj$`mV7OYY`W_f&wnJVco`ygG zmAKg!vOc0M05s~@K=AQRC)nEG16S(Neh+{Mi?pWXJ>o}tF>eqOTx4zr=H2*5Y=+dR z$mWHgNJo?qbl5Iv!;T{^vXzLNj|*cN3x9Ft|40nL`oMLnWz0lhA5AQ zwDn&j1USB$Y$}}e9?CoL7<$e4L#PM|m*vXmia&nDv)$(({?f$yYT^slltbWc6V4Y+ zTtcG0iD13OTtbW(W8Z;8&HV%V1&McL0UqKLI7O(4nV&J^p?S7`a^4ef#}YJz+3oSp zWEf-^Hksuf`tMj(V%ZsD4F-guc7O^2PD8sPOq%>g`o9BFacW$HTBTpo-=zrSSqKv{ zUbJl<9iN=z9eZ75UxGPutm{FI+pD1_VU7DV*KY+Y;*L}Fk=oxAKSogMD9cmPFki<| z$AZe#$J~dXjoADRSF2$V>)`McY;ZWUmQ&t{;PJ?d=V0b1mT|1ZM#0=b`Z5-)-Q}nP6pSqbI?lnP<#rDI zAAfF5d3DovXg$81WPSMSzx17fmw|7c(Udc-Oc+?mNl=e zEo)wVqrAOiAL`}`bfiCVWulB1>$xbLC2P5N`m};aOGfuAD3{O8Iw!+K9hy@g zp~b^IZxOCX$n=fB{5p1_?k`K`&nU~5F63C;=+b-p>T>kNrx6yNrYvbo#T>dkGRJ(~ zhmpJ^7_e3PF>ZW!*urov;Z$f8(Y!g${qCzcwsQYRekgW*6&75AkB}CJkL)eaJ^y$Z zwwrYg#{b4WWK&^jr40bbX@JotV?3gAte5CF5*T0GSe(1I;;h3&jxhVTqPTd>`JX5b z9nP`xE}h<2*zgWUi@H~xMldmF_)F$EZH+kxw8mm04~>z=%Zy{p0YHSA8QzXdv5vrZ z6#SNL#B=AaZ#7z%dFA{n9Qike8WvAmWoOSE=ca_Wv4OUgHil74jta;-xfWA^q!z?z z`j2IDJkzku z&Te^m?6IfI{sRYL>dyrY6=q#z4v}WjM}QOKDC;m$cbrW}1YA-leS{yGG_S2XX!>CF z&UnpRO#`580~LgIl71Nl$~W)QIoJDbx%(IqTe*DS4|26Xup2^c=&1sY#=wgbl#49D zWt5c&dzWf3`Lryry7P=$haE=in+)Egm~?Enhj;BLFZ{({l<7+rmbojImRZ*>{(q@^ z6Ck~h>%gz)zzi^h!F>`S2=EdQiION$qHbBTtyof7mh6os*>Y?r-Ywgeb=JG(EqgbI z6MHw_O5#M`O1#Nt6IUvZEZZx4Wm(ou$)ZS6q$nQZ0fGkz5Fl}1GlLn-k>BsV?(h3% zFaQCPs!e+4`~Umj{rdHLuV3F6$fnBQe)02OSX@RK!TtW@oUF+bsa z1%gDibWci%P5SW*zJ!eLbZ?!J?#N@tC$9k~)rde@g{ktW6b4KPLI?16>>YrYXpu%} zundee2sD{lI~ZGh!tmE*C+QFqU}^7!=vb6RZ12EDy^&wtLM@G3+_0>kY8StSomedt zH7!izIXk@4(qa#=i#{SA@T;rFWx>}v_2Sb#m(6kj5{0TWSjxkZWaD>#p5NkeshDr8 zSPux33O+MkDizTYsZOS;mA-rO*Rrhj6nBvC+qW;`jM*|~tzyX;NRn6dUO80`E$~M< zeb)*o8@q^%iXwzms~5ZvlUcCe(w_`Ce{%3E<}xdjY%^&xOq`a(aT$#^4AgG*FNyEV>a!R!46(a6*a^6VxxR6)#SimmM6{* zy4=$(eUsz~TiY>U3eD;u)ij1Oj?<;Rnr>wIKy-fW=vm(%rK2(rkcZpZiHM3Sbdi)n zC{pE+=zwV(Mwz6nl%10u>aqefuUXdVA2ar}N9?5cO|o>;i4aTGz*BVrK>r5J!@OgX z0bCATojLL>r%fLzV|03)o!r8#+eT)~Cr%wJkFYm(-y;vj>Z;?%SQSM>YlJ<>Q{JP^ zthpU%l#sg5&OBG6(b)EiFi-!VMh;WB&qF6{@k=`?T+=JHu<;mQeAxDxV<7khOK4wp z&GzyW|G`JtZ+);l{P4r&iD&kdPki|O<#+$(zbyagSAP}yxhe}-ullm1;4IrTjX6py zArgmc_=!8QQmPLBIiZ@+i!h`Htg~8>%aU9A?tg-zq{<&yN@OAPm~*9bv>PN zI?bRk4?5dvr`FpXuD<#jPCj=wp3XNqypj&DXWgjZZV$0@=9v%&xkhjQ{v!++6>cwh zp=`hEDrA{7sfVc#wq<5xo82_BchB?k736#LNIe}JT7%BdaaistPNQENZU+uLR}MwT zjM;wD-nxQZLFbJA0&T|KyB{rI`pQ=sVAxh}<}kjq=)hA?Gubz~g;fT$MK~;SggyD5 z%l|a68Oj{&?@d2Fj4@KcPs|5kdBt+o%93N^bA?0 z*ivNHg@K14cBXYDT@slomSstFXb5c_#;TeGEEaJ}L-^pH5&4awJkWSPQ-%wGaJSsZ zx)UF^N=UBdmJq#$q6s4&+X0p}UK=<=9%gWp>kZ%dhS#%wW0I8=bk0d%`SEXtGSk~V z&dqZ7JACGH{MoqI-N_hNM_Ue#GdOzi!1JL8$C<1>8>jh`hNPW+N6S5z=TG6T?s%}^ zZ~yjh)A2tSv-A!$9X*Erpr^57(;hs040~ugOvzDpq#Gak2IL|Jev{>Z>DF&8NJz6I ztFAvt)Pvx@jnKDm9 zb(q<~YgdhxAx4WPPOwjpEAcFZUEX4Xsx(&KqwFPexXpWE%{+rt6lU~U1{=;%z|B&C zc}<3mhJN;CWF|0OO_b1fSTmJ-4ba46(7R5#1-B=mM|8W!81L9PB>&19fT#|mvmYh_4%MZ zaK@GK3Rb1AzX^=N8{O>@LbzV|k!flnNyC9O_1lJB;-dhJGzK>)bHIbfUG1z$i+hT! zc%{TqO|KPkX2uS<4Mmq5U6vt!@fu;WgwCPcksjc*p!MWYMC@;jN6VSRAe0zHM7MKF9sz$e|5*gj^v@`DnUt@$*f5 z%BXdg;y@eoEATaydg5K$+HfxIdugtbPa7!o@E@khG(UJ&x%h3oow#8p^LmDr+wc=6 z(xrYIu!B9&i86lXCGGhTtWtraIyORMCdw;Ev+=g9GQEt)ychDq9v#b&tEmrNz((@~ zzZw&7Y{D8vV>Vpt1Gmtf_zbGB@ivbWDE;!;%{B=au^5+@hNs4nWuFZTsnS?Bf(M)_ zFQYJDb;|_()Q^N#R|pS(L5H-|U#d;g5Wp9ERPrtcl75v5Kce9kmZUYUJ}a*kwvrGp z9>IFZUO>KZ(@*JLs*W4-B^%SgIFVDYG4DkRR_7*vSH@*}By`$MC(Ld;phciwyWfjU$PMI{V*rFed%uP~#kQX( zp4`JJ-B+RO(P}1M2j!{P*}p!(3O|>v&(m%gV}{<@Os|S_@ZUqYyasH90g7dmm$7X~ znxqYym5Cku7_MDk_%r-A$>G=%#CZrv@s%`^F zI6J^jj3CLF)t`4eA$#(N#x`+Y$)n}q)=^kH z5H&^T$0g-=-+Lcd#cc~5NwRA|002M$Nklq_dz7oke(mr7!*a#;ZRPRD==_uR$GAV-gKDEKfQXbztms2W-S+zU z6Hk>}Z@sD9{`Pm3zhF{sgb6nfgL4qb_Q}2X-(UXeZ~bO@-}`=yI%v3@kU&f})W^$|~G5WXUzNSv%CBaw8(xg{d;nwc=lt80Yumo7nG{V=cPY<$HR zF9EHEF<8x44p`}>Jx$i-8OkRmMkg$vp*O}^;q4~{h71w@TARN}1C&Q7An)cE^`~;0 zESooNL3Y~!mOi_b6+bot@@J{aU(~xfd(JRu_^uk=5bw}is+kaPDPg!Dd?1v2Z(*KdBk?1eoYLNv{faEjYLLH5;5)0Dk!^O(Sup^h;i$QR@9 z_+OqSrF(f{E&|=9N}IoYKr|l;($0&s_HDVkg_5UDnrbc&vY~0k#8LO<-1tc{(_~pU zN}<4k9w!gKP$u_3Lm@w3c9J1ia}C}Qx!(>xr*4EYOp|c>M`y^&ka$Pv1P!yaW7>T< zWX?gBp?ZI-qeSPZMCT~{9Z@%of3e3bNlso(pvsEx%2e1aAXPLKXoOKyJNJ$-S!inV z?Mc%#41lxQG6%mZfeq+>-S~-DSQFp3m7%gwHc=p;Aj&Qp-670gDl&totc_J!=Ub?b zwK-k%T`Lhwgrx#Xch&3|A#5N@*A-D zpQSVJ3{CsaXlodSrXZJ~GT|0J#bFKLXs7mEiQ=q1_{l&nuOFrY7N^Ud;@~FW9Cef? zmrdCaHpalEe5x!&eZCt~@xX6|-8sh=OM1!5#?)V4z*U1|R$dT?TD_>D$OqI3X7u z^zx%(Fx0;f(~)t_=Z%Jxr=9q&@G@;P&7!OZSU62A2WBAO_x!xGvpE1@X37qXyyHe% z$$keba_BZ}t4P4ts|QQUh;X@TBchK1MGxb8*E`->?!No3a+Jw|VfK3yX~b(ew8EQn z;AdbUmoiIwY+Ir1ayD=^htzr9m-NJG_l-#7k|rJ|o9Wm!sRN$4Jv2pX*pGXOF6KAU)e~fe*N|> z(WZKQ&!aJOx^?^2G_UeTk--tJ&!XWxLp!LCgRrJ(0FOXMA2{Zi3ALUXV0D-WRIM62 zT~@5yQr1%&NqrPkbaZCn9qGVYH;tMIBHf@}c@8u4d)?dT8DMxWCUMr%RvO#Btz6Hq zyz!0E?vngbI@s$twSTa@z#s>FL!*(|!1r+3!hUk&w3{_S$N#Zyf1>X?m{^G|jsuadS`K%X+4oG=zyf%Ps9S0y+nI2RGX#D9`Dw zmg7ecamX0kL{<$k*tD#?n?t9!Uwtidk{8kl(eXkJU4=&)^6iS5{rmTqpa0RH;n1<= z<+K0pFSu`f4_jTw%XhhJ{y+YepD#bfA!*A=ljrs^TYqjhci7LA)nj9Hy6G&@pyl?s z5Jx|G#SZm6y0v@HGvyb5{^NujDWCe|PnV~k-3R^^<=(sRE+766KUO~Y;~!>#Y%Ih! zOQ-zs(K8HE(Jo*`jMwGKz4xv!<2I|i@A?ii=$kmmZF`wGdnWYY^>271D@?}FgZs)} zZd!0#4=cWDGfy!<17qmhnd3*xp~1;AyoNi~+3s`t)Hu3#knI2m%jpwm=s#?y&97#h zgO{TW(mBvg-vc+xuWd{;yqc@EpLu#OOU}t3ieKGFaNRVLQsRT+tl!BQqVScu z#Q@5_Yg+mOY1_~8&HQ6p(cw;o@?A~fB23`It?HL$PDBEJCq*-yvFpyagho_Jy?W%J zc;mtEXm^KqcBT_P0@bjfN=IJl?iPbVRzf=vGCj@76x?WVZpPJ~v;`>(vUHOd@jJB1 z;B95Gi6qK;2215%n!LAunOkjGi!(bnLE5-ViEUc6N308M2QFj4PkwK|{jIT*WPmL> zE9l=jkhOyT*Wn{v)yP$kwijF5%KYJ~lWDeF+sTeQ>;nsr%4WXX2kv3`hF|L+`Ov^k zy2)X<>CP{`u^Xm-Xywl`uoI55&~PzhZ(%1qrlRk}6OJ$A@d|hBJKP0HNpe!BJt}A# z!0z2}<|qt_>Zow+6H@>b4nyp-nP5rHj91d}J$L39!s#oUSynNyY!!*do-a!4zH<|F zG{#Xd6pG3x8vnpq?YIxj>oVx&ry>)X%QXt4bu$!9USBdrCuN?vS#*^GMd*$!wb}Ye zuPX7#Dk^oPVe)C_a7nbh7`OXH%%ENs;=Y$DaI3u0a0HKqtBMjco50(cF-4owgc3n# zzys@Bx!K@uOZA13hRC>jHlw>9nD7gmb{)EY)%nF=y|`Z-`h18^_)3i(pO8U)2dT}@ zyOnyl^QBlYgawasR(G_EqcdWi+|_3zp%Za)ctzexk3>nGrapNYV}4~vA-rGYp;Xk3 z#+Trc?()f>hkf`R{8ET&cRT;NrM3YE^?|m!F#)IzWeNUi0c<^AX3~)cFatYpQ zG0_Q+yA_dqwv-T;v>L{E^W9CAPS^`r68-|7I)hhi7c-A+(+-* zvQK+w|9y22ogyC7q=y`0z%gi&i2Ph=$#iLH;($-G(AQEC_=_H((v%n@||?&uXk|IazdT5 z43m*8H&{W(tfG6{9dHVM@yj$2NyC$R5VCKaN<(G1`__%}PnZzM5>g?Y_#+OypQZEr ziBEi@T*b9$U-iUx>PM5RetU97i z63sWGOwxmfmWDy2f~oWeoxs|5hygY1p|ilmmX7Q;aHldd@2)mB^>yOj%dY&2jd1!av`YmsMV|n(eXUYlgs2&F28cqX$1E+z{ zvQPHR(ZglAhh?#%aR5ID2O>>XG-(6**y^#ej2jGwaU-^fGnTd^2Wp7a-EhxztI3n~ zle4fW_YG{P{O*H~mOuF9C(C=^{kC!ycbShYAE8q<9Q7BA1EM27?;iSPoV*@~mBA-* zdM&bNG8DF6P0zE%fCwIZXfOA)f1g-~%2UtmEx+`Ex0D}w?>mD48~xT3v1FfKpWCn> zdiaU*#jkyh#HS>%VwC<1KIGtbvL0^1y@4O5~=r^AEBdu#~pW;_q_XEti;<@?)chQ%TrJ9E+75rkCqR8 zJCT~Q7lnJPc~ z@sF2V{*zy1`Tc=%?{~gkzWk*xmB$`^kiGjq#C9CEWIVs0tsG4B@wa}%x;X2{)7SUz z-5>Q{ZH=QR2tNvHn2$W2<&KH3&P4t+4|S5wNjXY~9=)&*auu0*J`X9(&b=jFhO2S3 zFr-%}P7_d|h`YYA`-fxq7jD988ZqLx45XZ)JPBtLQNwD7jtTGR{#2u&b7)7@%>b5`#AbOu&*iIpBgg zSWQI60}9znHv^l_=u;ke-@OyUu3)uufAIO|V@dz3I5)x7n;{iwZIh;R=%=eUI&}a7 zup|pv29emq=q4wYgP7`^GA4|&3*q_FuE{WI&u2jC&wsS{aklNUxMSbJWw3@WQM{z* zE8MYPNL4U}llm8S7*rvg1@aIUh0P<}V*d*x(2kZ`VD-&0t2DzUqU@)!+A=Tovj->| z`(RVKTu>T&w}`{hy?Gm{3fDr*(Oo+BD$yLvajd8vNpqhD`8Gyx+#Bcee=7~s4d+Pk zXkaJ7d}jmFPcxyAk+?N8#GYbYEkGmT;Lm;eI6yqUqvISM`|RZTZ2=r~g5R_V{jKyEZ<9qA_l0eO$EqE0 ziC1BGy^e!q9-L=|*9I=Axyk1_U?xUWTpcn#c?uFjhE^)b68c*{>P;8JzEmT3FJ|oc zX1Sq$n@q-Te$MacOhRl+gQOkIQ9%H2i&7Ir8$Lg~&*Zgzhqn<`6W;{N0T1Pb;oG-R z@djRbZ{XmXtt?r4^wCGNT(ayk!irDW)H^KIuFO+E8*M574sPIDT)j5K2QNX3Jornw zM4Z*V!#MF|hp_S%G>N%u;)_RkRRWZ6#w(n(8Lx5KcoH`8MOkcltUrws2eI0=58cF3 zLH(#<6IVF&Jc9n7?`Bn29VF;MtwKcIV=8~TbgWtuC~#D0=?QxAQ_o@`tCz?c%DSls zSq=RPyizcUh$vdR$zy0(keqZIe}|p0>Fz+KXJtsc-{=zG8V^%)M#WCF=`bBL_vUd! znHChfhG{|wU|-(|lLB<+naTG|kXV67tTx!3Ma_tf#2Liw4v;fbZn%YB!jlb8 zd2TDE9Nch{!+q_`X$N_4wKK>AQ+;JEayn;OG0U=a=nH)}JdNT3_D)MPLZ+Uek&7&s z!@ma(A3A=VCFc*6pa0c=THbowZRJlt^=EN#=Id^{rEKOFl6jULKe79fveNV+{!x}X z_c73tOu!QjXgQe1&prDq=SFFgQD#Tl14hGa*1E=an`vb_ApprS&qaBJ-L#*DH@9%P zB>untpZ=_T{u|#eTNr>?%T~(VKYe3ayM9Bt`@RRc{_GG}&e3@Q=P+pd$;Xym15Ent z*s-zP{hbHP!9yom9=^LAJ3JoCxNo>>Q~AWt{A5|fSq)xOXoof?Y3#Hen<#hPb#M9B z-QO$E9pYf-vxuyZl@Tn@o_ElJvcUAPLm%a~I)GJ83{8Ru`SL%0eumKjqgTLS_Z`mF zPyd%>E*w7c1@S0jx33&z@aL^>e_Od`D_0>Rw^+?Wa97*ic*6}0J~4?Ue9+-mz7=%9 zM_7V>tXz97gDv;nUyd^f^tQLYB?h|eFb%S5_V}^m<(_YUyWG!}f2U4NvVwz&G19>; zbRM1??ONK_<|W(P-WR{`=nKR48k2_aN)1N zcxO3qXg`B)qd;?DcK_+}d;je(m37{*Kp$hz(@&K9@A(>Ses132!0p4V`0ek%pWaR4teImLyR_Nf^4oG)eNykGx0{~{uk!ffPuLh>BQ;mB zmCCb}rkP;v9~^}@mv2ZX@}ejNG(veGVNB@a)!%Q~uZL?%+=?__o_OLh27aC*jAuH` zkUm$HT|2L3n-uBFfu6&x?wDgm7c~Zh!E@-(DOPc;K@U#EjSWE)eMRLf?Pu#&5x05S ziS`T?{iM|u5jn{k#K}?c4f1MQIx0YZm3KX({|OHv$B?x!Jx1Xf#wRb!ju_B3)v9cb z+dQP~e^BO?>)0!c#$$c^nk8l3f$57`=nDJywW89`@-)X#S)81Ms}eDD7Ienx6y zS(N)hg-5tn9!6qe;*FLAmBoQnzvR5$_<0I(U{Mno4Yt z0`Lrbf>k}{+7UK|2${$N98JcRjDy14&K_DZhCejo))K!$hMNjwqFGs`LS@5QrJ9HX z#o(uo)U}4cv|F*Od}bsoa_LtALI(JWD++94iMNV{9CKE?DV-!Fz10PWq!eN?R<4HA zeyJuibp)y5 zU;|aXL$blVBdpH6JIH1Q<9Cn+o>oA5Lalp(oK??5Ozj&+ax`qfjYTU;w=^{xf|7Uy=Yb_- z4>ZAnbhQq67PZD?dYG1YLO=f?NVzBJ0Uqzofe2slsXTb!FAU2Li&pbYqN3OY+j49-Hpq-cYMSY_SGR!4_~XE{2HN{3 z`$bwnhuet0{N*puDJbRoYpS9ybPdq4ksHg_VeBhuPpn_Rg2STN%Ezhrt5%K1 zAyCTR{pc&)t^{AbLNOkf%G>Y^or4Z#sh%kZ8`aZv09*~_N*eEapR=Pm?S5poDOUjsxwS;ur*vGguZaYv5&yI0r@Vc=9v(11R<|7f}M-p9eiK*<0HD6{%v-jxoP z1(w?p2_!`N&h)$b@%WCkCL`(b9Vsx99v+V_?%!B$`H3j zedSAcl)L`+u5#O(-^_jUqs)q*U=`i-bhMB=D_qYo!|s_6;&5Aq2iuWTg0MNyry61l z-N>3U%{d2OXBq#lZEMS6245b0;FuxDu{@R@k*4#&)Ia{u~ zdUN@SpJ3I&YT7@L>Kj_w!1xw4?rYcH!6sgF zb!ac{Er8_?Kk}q>g&i43nM7R~8Qx4Ep(UY(1B39w^0SQgJ%bKWG{+UkPClh^4Tp!0 zGe~Gz%E}|lSC&{;tk}g%c{MS9h(ih=Ef3sx7pp=Zp$w!04(!v9Y$)$|*L%xrUULg8 zM%ePfN{XSOmCVksFS|KASvY7rZ^ko$)}z~Z^sw}pz}}rB+Cr@ znFBGK?{^0o2v9(-2(~n7f~sV6&(E3YuUU@_oY~HfPmUmN+EF6SJ`^ zz{qJTkQEZ6TCqos1PEs5sr;?T397=H(z6swkrrkOjCrrwU7abpjI5dmUScWmrQjdNrP!nvB{TvqPb5uAAbq+T>PZWL7O|(=bJoyn$+)>cT z4^FsQ5sz|sj)`UEHO-(wn`yMuZsMBuCYF_?_d+TQ8=~G_Yr)`%evSfJcoPrbL~I0v zGojNx?a->fNW(~1wbpONod!$C-rO$bt?CEI0i5;>7wDvsPtzuh0Mb*xgESugslZm~ z(rDvs&}%Q?t??C|&x)qYQ$-ty60LF}lJE$7e0O;d8cCl9lN|6#Fzp#Wg69KwF@_0y z00yni*>{U8qO&-qfI@+T{)9^!gzMnzMQ}m8cp?HG&?j6=S8>TorCZ!Kc^gN3Su|5~kua{X>t5Q~IUZrBvFT1+dZTKGPjLuH;1A-H}(M9VUam zkV(x)ZD2t+$%&L$BKq)`q{~aF)PW^fS?mx*n|25HglsM^&^r(PM4w7yefgh4? zp7EC44#|e^{f^eCZmq=4pc#M0oh}rymN!WP1%TJ-Rz;Te5=J#<`6ve+A;`!I{IxR#hE%_gC>X*zl5mshF1pu`QJ6+ z*`X=o>3U-85kO!`PhG_x)kp^+u9Y|GAouZ^4oM5xASTF4H1S+OPQg8fu0EGz{7H`-ts+6198=e%SYK?zh+gGT{PF& z{zpUBMq|iGrs2axrtRXvVaV@_buVT)}N;PsGJ+hyjF&^^hAq*rabf+h2-%kU^$rK*gTt{wY$+uDP7 z&nSwO3OK66`dX$ecN6qU4%^y#MS0ydTgs+2A1m*;{oP!FH^SK}M`=4vmIE&wD9`LW zzzq9jd3-M?Y;zsn82hx3Giy4;$>(9%XS$<6I?O2rW9tQ4{=icj*TnJ?x&tD zzx+S`&*fkI-JdJ3p<{oT0}4F}-kTg|k&UN@JG1IO`Y8^ML~EmMJ-mD^`C+zv^PBfa z`dL8PZkux3tGZ45*QNF(C2eP}AViSreHwU15Bip&8w{L`ty*6Wvr1zBzQ@azTei`W zo+`&5ezJUr)^BC=K)k9= zu#U0J>>%v8UceGMOgY=U(M5GD>V4|K#NUl2JC=#RX75G~^bl4d`48Lnc@QSW#Azmz zPL?g3x1f{e|GZk<8ZK~{+2B#!wi#U^)aO+cx`SwvEgvU1^I()^Ij_3FT z5_ASwVa6Fu%~cN(JVH0T71=_!PTbY`MP9FP$9}2Usu1w9!qm8AEd=HV31KCmVC>wR zDb2NWjEN8`HLFO#ms(MuhKh)CG5ipYN>Dk|!(VHsfXGV5i=pCo%m+ z#YaKoOn<{Gyx5%)iw39RG1_}gWDGM{rB-^oM%+DLJ@&5aW!OX=IGO~EtyWkSO*F=} z*SJE_qk#b=@21>}&e>p3x@>3@Hu*-l&`!FFN?h{j&otvLtnYBIKs8Fg(r7@e$s`sYtsV6U_qGEFbu=C;H;@GS}4oHPOkd1>$F5iqR%y|24huA`Fg8kEed+MyROZj_pzJmbCz51mdhQ1Pq>6>a^ z(=J#^ej2%^Y0`6vd?t(MJ&iNycTl3`8K69AI_R~*>Xsb-jN5#rF@6~^uehu#(;(fH z%PVO@=N2Jc$}K@M?j}FogjLqkANs9b2fzKR_V^A!{TA{N>Y)N#|ZW<-of8#$73- zf`sfVkKzg5Uj`qGgNo0_o-39>ACgX?rfiMhPJV2AV(I8CC)7_)%$3s=M}`?=(m;B1 zDx<%yUdY403RS943E>w6#$J)ZwYd2%fp4|ts{63(n)LdDu>OR*3kzWjg^t}(olV4#y%ux%|Lkp zjWI|`n9PgFn0zY!H~iG?<*)zd%jJr7qufGpC2pg13a%)xy~-Z;%sT%s|LXrL|LnK_QTgCUK1_%HRt90Wl~eHi&?8Tx7pw?Dzea}8 z3(EQN@d;+lkC!Qy#e2Q9bMJkp=}@D0D_QAbzs*TDPoQ@I)$~*69CUYrW_G5JHim-* z$dnrd)DQK}EoE^%q5I_-ELyW>V>!+;g3o^84wg&IBh!qC7B*Vm0O2=&G{y^)n3r^~zE{m$t0&Cc7YVzmN;8@4yRZqK&Wkb6GJ z(;k9t`_IX_+1ZIm!`Nn1+aN)dlt#j;GyWpQLk@gI+IQf>p+X3TtP&bKI1*2Dsqgk# z!**UO>Qa7^&}%wqdVmeuKD7sYbs)S0hRv0nfgSzD-8|itSjv?Ji4}t`uHHMzm3L0W z4lqDxhU&^i-4Ks)*p|x`TG0)3k_?MystvOxWDQ$#&XHCQw4G(^#5f&$%aBKz#b3K| zby>k`C06s7xyh6C6Im_A>Wx0qaP8QNa^%nevoKdU}^5rzwx8WK%CKz!_5I|jj_bG7wr`;R(24~d}e&+4ROT^C}ixmvx!Mg z^QW9rHsNnHNiuFP-@L*d`(QI=ByCWda_c6xT{(p!GYM_S-X&xdQYZ(~r$nF-p@ScV zhRWthuNo${5NO(`g~e?dv-Be?7{ReZWacjuHo@)K+sSc>?;y(5XD0$-EAUiZ;KC%O z5*0SyL8o76LUd?Mp!mayKWTQ0fw-HoFz`3wl`Isbnke+(Ee`z)<;c!s$R`T34DAW| zK~ql(Hw8_I`V>ddvcQ#(Dx-KW_Pg|Nc}p!*-Zfm%q!QL|EYZmdfQ+}(nXl<9s6R8P zCJIMsZv`aw&;$KjfuKLI@*N}T!dm<4E}Vu}hmLf)IL9?u1wHQ--aaJuMPLowK%2dh z<@aK`bi1(02pc{*@8U9l=o3W^S;G6?Iq{VWQTeHJ%FY=s?do$JAWgdHZ*sID+I$6jU(YFc>C{=_swOV=s^1 zn>#*E^(p+cOz@PsO{mXkpTch~05J6l=Ka8DWRKxZ~~k&EOywCOb1)0 zu<}}L7RDLA#A$pjOeX}+;x&d4j^F$RWJVs}(w&V8%g0V=EXtwx`<1gBeWnjKWz~`Q z!UzNA0@1qS$WDRsbO79rg|}cVqjP2%c6P!6KJby~&eFyH-N0pnnohauEu5;L&y!)0 zS3NI4$CAzl3090hKm4>)7G*1)<|$_N&JB6b^&p2%PL@*~4z_;%YIy1^&l}uM6Z_!d zF!)fT{EI4m8nbfy|39@1I%X*09e;* zf==L;F?+kr0R&?7x;oobEbBtP^w5adRf--&JUhY67mCxz1jsCd5-Zt*>VkqH+=e`; zig4a-4l&f%b(H||c|h?vW%K~2jB~6px@ta1S>=qq^$OJJgnQ7ZKfiNzP)9Ehx_Xq^ z)!+Q*pDeH5xs7svnmy4g%WH1Bro899Z!a4+tziX3f4O$+hBCXgl$|@aa~;{i^3^+^ zVDN!*iOxZ84>O;*SCtMfgCV;%Z7P5Kxo?$!cgLME5#%{e-ZxH+WG8r(HwU@tV5nyv zcIZGs5*&pF_B6^|lia1-i$60=&O#aT2V*2n>~^I3`&e4cpv4rcJJzkgvOM+t-twRS zSN|RR**{Wle$A`7+PS|xbpIpe8+ScaZnzp@GNYbmzU*R9<++_#mWh+6!G~TjiyC{# zNq=SM01;Y3m^S#Nj95ZUyH?pvqDRZ=2v1G1jiZk%rumztqcTMsW&8|xmJcwaPw&DB zdAHnpz2Kn}<{u}+*xNrr8+>pjahgLs)t&a{xUm#+mGsXqh9L`)Yu4$ z3}cEWkHSW0IOwT_TKNFr)t?TE?BBP)?7HrHoT7$|&{0p2zUr3<^b48@XHj9H%1FGi8Y`fDB;zqy5q9(tCwcD3NDv*# zBi(^I8OT;ZutL~r4(_n6>Os)D?b-8W;8?R}HRY!RSICPq34}Qcy}mWdMEQ2&ON8O~ zQXj8e$6n@xov>69>BhH&`lCR#)8Nm)Mt?N2__DC_8m4)c{*cQVkYz~)duMEH#R$HY z6-EIV#&*phg>@hM-(o4R8;0<6Nu3>d_1Lg3%gD~paC9zP+=dTFjXan9n$(aT!iPQ1}ZbtbD1!LIot>ee%!~ee-K> zRFsWY_NC{_rndy?h z2-L#)VVH<#QDhD9#oh!9xdRuOobTi@@r9p_EuwMe%TBtLjs=~Sl$~|IZ7`3Gtzu?% zLlh*+^uTimI3#x!LCsU(C(HmHc|R;z%s0;B+i)|s=%4`?z`hn3G{zth_mw{+y%)GOdZh0 zmejw+u8Y25&cCFo*(;24i}>|dw{fp@FD9u=i8>de>P8e{YQT;k81lahw}efKG)>P2 z*vs7VvbrRR>OfV%DA$}N^GdHNDlQvH!!&ea&pzctmrih2TI3~um!K!6WpCPc1QJwA zXHXmXB)!p{rDT35XaI&a=ubgsxkCOlj|3+2QPel&gNz$~ffcX(=ZrsGRobJoLcquu z!qqad(IpOHO`~2@$;PSC)#P49D=(IdHK1~g87jd<&fBzV^3~a2uZb|>D!u3X_rks` zdt=VG5y=vAxEzydVsL0h_BO6uP2@@1p87sWhtGjWXYGR*;_|JDjwtN`N)3L-pOOgv z8*TVB-Nt&^#;}o=!JKreC%8fD6m$(PbJY`#R%VNbShhJs89Z2*C&xKC%$^Rh6m`Zl zl}CS&sh-9bCn%C$@rG{Uf9$Z^S@Zxf*qK(`Tt037WsZ$*Z_+hH+r%@ATybE$ zDNE_HUVs)>28`2=TCsuw4%bMM9(L^Yi(~>Wj7h^U-QXV@W13G_Mo@6igx;0mpy)PUsAOF=qD7U|6J9&w%s+^X8 z?C3<h%B;}om{Bt0n+ z2%l-A&M4O9obrG2)R}VK_1Bk=|IEiC?dhKZS<3Y{UtQk$o`dDz{GXpHk3YVbQ}2(L zYj$odCpfMD(|`6ER{Eag+C&DU=-iK?Z{~yRU$u))V3h#+xPSli3{oFpfA|=a ze-q5qv!wy#S6+D~2l*W;&mTNYzkw|T959#@DOI1yF(TasS2j(0eI0|IcBCB~b~4EGAk63X0c}TmZj-AF*K+OW z1cOnQ%?=!!hZ=jnP0y^0rM40bskTkS$O}do>$2|84!io0JUW12Tl|V`+k)@so_j7k z@!&bbpoA;GJQHL8foGy^+i+*BJhfC2h2KkjyfPj8qzV!`mJT@`mnxV>G-8d4!7#$i zl4yCI3yn*@tsti;NX{Z8N(v5%SrG~1NSnfSADAOF^V~Z*Ktt04-23a};2D%|koa0> z(F17gIP`GwGxl0i$^NMdKaZ&YYNznc1PW@|XMoQ0dD(N%d1_a9BCM z925Eg4rfFx2y+muRw&3VW+K$1I!I*UrCzm;@hJ)oXZ77@^gIXOIASSj^5$~QARQ7R zm5P!A5I#dMgU8Tz83`5^a}sH_L}hbX{E7tL9E8xgy2S&voSEOmRXfk_dluPqjR^w| zra?67p*@w{f}ea|dG=lFnZPAaFKQMu^`Ze1z;wAJBbb$1=z^UCD@*e^X=uLhF`@Iy zTG+s!;Q|CJ|1~9q>3$^&zk5uCzpwz*{m45th~VZs8(Ptzg0>iBgce7yEwf_go>?Aa z8lz+Hy~W2*9AkMS*U+e)*73oU^aUH054`#A?YJ6k=ATNpq+0Om9>8JY(d(~o{qDSV z%e<;zOBdhr)O5gi4mcW~7|f>QIye(4T2osqAHV0ftxpBh&7saxMItO7@VA?^SqpPidWzn&fw}-4g`TG6$i&Osd}_E z$UiR0oTT&aA$lHAIzywBt*CT>*kjL9X_v5%(4lt;xhokZ&$| z;%;&32T@{S|eBdyGL=C7!ucuR`g7MQv!TSvzjBw=u8WTw1*)0T4P_=3T6bl@QgELO6nSEIshLbxkd9BEGKcrQ4)YlUS8L zc}8ljACb#AGxsAaHY9OMk@zWf-d!h_BJC3`QtUVhCS{a zk|zewwm8e#3hL|tt6@Adz%sxX9Lrlz8F9xqzEQ?L`#BEFyEY~zR=C}keeb84f%V$F z=MEg_@ZD48#PRWR&CaXJ3a(I`JA0}Ok%^`^tfQ^La(Xa+`72*7d!F3Q{q$R6^@=C{ zKfCupoEtGgCvo}mEN5L|Fwk#5!wHn3IOuOUCJmL3^3Hr`6HHz4*=r)5 z08z#XxKMo}n$+pV9>6Y%yf?y3xyA9D23_)d@IrsEV0uSIZ(5NqwiC!}Skj%q4t~sV zX3v?EC(6pTlu^hq9}NLu3~WuQ3yjLBH=rk$KZy=3|5yZtOTHI_e~@UQ#f!w-~Q zyLK{IG#V>SoHS4vzOC2QVQIy&=3nDAEhGf%%QUY@#~yMjEon;~vk<57G(+R-=#HIt zR|7?b4e>%p>1;-(5}IU*n2C1af#KCwMz#NE~(?R;^()=;Tpj3nP6&18*xG3v-PL zYo^6D`jPWdQCR5dmWgM$EF7~!j+uHA%EYvi&Q6C7NaEnpS&k3h_(LWZVy!V5l?!x) zQh_@%nvlRLA(wE3R`CVV;7o`hDIoOd8bC0Wp|0~~*;L}d6KE1wxQQibtZsfQGv7Y( z6E2NBR3F~*nHfOkPMwG_RxJ3(=)bt507#f9P!cne2%LcBb1 zZ2Yu11kpQq4uSJQ(nNTlS`5@<4Lh)E#>Gspe~Zr$mb<2ZkQa~CDPh!`ah6L;-wDL=ujl*vn)rrto5FNNWgo9D%3@a5Gm+t__MWgOF88yjt(lJ4J z5-UK`Dy+KVccUxHPw4@!!#8jZPomL3>4_c-@%ra~gUdLiHBI9;>CN!XkEo<7{;bS} zX>ih&d}bVhR~P9HzYJ>t(y<#+meFT47&AhVU=TfKQo0iqs zUj1i)F_ei?P3S$y>^#LF0(sf(N#>o14}SWsN06Tb15CBC(jeOujb8@@ViE%X0S8nW zScp{=qvoT$Va4;0TAdf2Y`#Mmf)n_Y9v@Xtlf>lN^pEKp-qF4#KHql6r`SvD5?A%3 zfBBlS^UAg5`m3*t16{xK6b*6)CPwL8Egt}WK!LyJzH;LvVCWb!jeWfXHncqSkbmPb zAMv4%DFPqV*b+wL9zBDw%!8&$5FC1EJJImDT`hGSfN&#lgjb&GMxn) za-PCj4qQA2PfQYUg`)!mbF`Tr;1IsQ_{{%9Uu2%`WSi(zo>Fk!7ytl307*naR4O;$ z{5p7SXMfn)a^>JCXHcvoUrt1QH;ImUV6il-cUkVFUO~zN<7epT0@q9UNF}*2V5m~+ z(|JHkg$=qIaiO<br!o;6sl>uK`UczcfBGdvJC~uY1F7 zF&GzNf$4Kpl6*90r+$6{y>RP?H-d5KIO~PfHLtU?bAI4CRz{pV%dHoi%Siv~&^wxe z)u1DecG7;DqWE7GxF9B&qVQmCk)P(uPpa1?$xMP}9= z=W__8j{@98u>N!GWeo{5y!Fbm9z_|tVmmH*BIhI-f1VsaPR3*irwnZ1N)!@p`q+_N za>kMj8wcJ6>mD%$?`U(Ypp7z(RHhu8i*G25EdWz=l%^?g2CcQlQGqgy6(vhX7^sMj zHjY+6QIIE+s7NgcGX^W6TCk}I7%N(BCML-kZqd2LT?LAUbcUZ65PTsGfv{u-rO1DnS*04%74GXvULHeF4>XaJF3&V1;W zocHjL_53)Rf0r&}3^*;#8GOkb4n0UhCdxxV-7O$`K-z#(=s7qnXdR$X-Zs|kt7lRn5Aj10GIKy@TVdq`YiAU%a$!$qJng9mizmyP@N&RAU?{- zs{GpEj|3nlKEq9SsMRIhnr_rYxFnhq$0dPYHjpw4>ZB8UNHavMo+l5LeA1vcPKm|z z2w=n4vLHA$4MgZWcu%l}gb5HaEp&dduTC)N1a~WoGa6Q_IJgXsXw*mgF)AOOGM2(Y zkF$P~WtnaRT5HrvBCxR;h;&U8uv+yBXL;@Q>%yjMdz#kGugj;l>|}^1&BP)0XN|Ty8Eu57kNovhRtP)i5u6DUC5+{ zPW(KHBMkuQUG#KY<8uXojRK?l-?0r<^}1sdu}7$XGAXv{CtWc3G~}|MB9C* zL&!K47wm9i7?_KR7=p|o%d>Pc4L8Q#*kv@>Bjnj}D!DYlcSM-b~SRM1_uisT3{{9mXKOd_?R*a0H+tkAh3V5c<0DO9HysQ5P=%_ez zjb>3-*e-HLUf$SFL;9@ddcx`1W#y5__m=$!4{*2mIC(qs`v{Y5(_EEj=h^|KY1;0S z6Skd^Nn{1v2+V$};2dfDsgLZ2;_-}pL`^Enyv%v((6s zrf-dI`PW4DwM=Ni0#ILd4M)=3`rdkWo-$^Nfg!$VuPvto%T;u=HJzYgF$FWy=t~Sh ziy5WqBNgU65RbtT-8uIHgkc{=)-J6-c<{+s?Yv>_2vK>cA|U*7Aj~$faifK_ZWIyaAD+<-sarW1*({MAcNn0hu88naepy0a8rf`v!S$=+ z3GbKm_yKh6gG>mO+WHI9LmEM_os`biT2ziI$O?q6QDIhX-dcv3y<30dtIFW2<>jFV zzr(4AM;V!$B&4H@GiCj1_7bmJ!KsKNW#diPmlvMwFDIUVj*%X(=a?=dD4AMdA~@pR z2VNC4luVn6=BGwl>&rxPZ%`l0afTUbA(x{%mVd_F0uY2S?z=Iwx0!nJ$Luqn@$P_| zSx8V|Gv1s5i`jl?>>a@jf06sEG&MVc!zH~s$OG;|kH8WE7Qrw2To^tjwa_iU9vYqojQJek^*X^4AP+R3b{MM#|leb@0M_h)UANX%H%oif6IZ zdS!1sy-DQvr5ZKFhPrz0VJ16w?kZPYv6XvmAB;TOM!?cMpxK`se2(x^d_CYEsuIMSBy5H`%Tv{W|gx+Wk=L(?;O#KCeX{Cb4n zD~s@~;nRNUPvZ{35=0u*XQJ-JuTI6Cw77YDh!v1!)HJgoQtg13w8Ro|8f9UR=#wA$ zXrx74KnPRo%&<#M>I)dRIq>el8I_H#3L82Cl+MBk-z)D6 z)9~Ux9T^y<@exVHS7k#~{Hx0sGg5ZG5uF`b%UR<&!-2NWu-Tw9pReR}<2Z~FJ+m>? z21A-0l5deL#NFhvz*V}HO+?z`6JdQQH=fam&F_Xd!r+^4ArqHxSL1rMoOPZ4(V?e< zBrJfoV~wHdol)>DL^R<1G#K$my~%sFb_yazo!yKBPMu|^v&oO*TXgXYbQOo! zGPias&e|@cEQ%E?5az&R z3dMS&6Jdl60(;|0DgvKzXyo7gbL{Y88vY!H$e!`#boT5hTLwmYWq}ZI5vb7}A3n@~ zE+j>NQ4m+9h66sW3{Mnd>*|#u)fr97w=0rxyuiaClJB;Np7Ps{u`CxqJ(J=@O}hiA&4eCp592UhYSE+op*U}i_3KUKbY?-O*ASrx+SkkcGq z39|C^gA5Fu;a3ju+fjzESzUH<<=D}2G=pspLu`#W$5sb|lv8xP9YEN)Zh6_XYBhP; zHV1Lgc6P6`xAm;#AjFeQx_$NDC)ryvU#`A#UD>#LEfa6$V;a>I2yxG8H@dG5LW<)?r8CxgcOzk6?a?6JqnQ%~(?CVvyb!ph8NvvwII=${Sh7)NLKxc_0;R6z zJ18X{k$OP2<-2jm;9D>isB!1IYL>XizlPJ#yT=Esd4yTv(AgljiO&f{G&X5u_ znP@nYQDT&Y!ePc)c$Wg1kvZ67Zfvxyz5cq=$Nj5+^e2DJo}96A|6L+Al zAhXX>ARRt2U0%KG>ayj^U1bYPwI(@)=bR%mQQljGAtwYj%N~$O2xC^z9hMbp3bv*% z5P3rP$}6ub8@6n6c#;w9OrUlMPAE5tYRA4iiemwv%Gln{%;i#i3-t7l%9L1zQCr$< zfgLkx3?=N)hXM&36_DV<>zOq7fW3&darYu%J>EeV^!OL?NiU|&Xmv0qK~SVJ2S~#4 zAwQIVb#L4pL8(afN2Q{^tz>-q^FBI-C8`oZ(%IB z=ctuza5}TSoI=3Bc4&G{WMpWMw7?^1Z2;iua-t0a;y-y$Ul|K$9unBa)rbvw;HR#J zT~rboK{LGJv?*V8);*riblXVQOj2+}1DS7U51hrBr-LmT^I$eGt0X(P!!ya!+G`?U zufvPmMWJ3h`1RDDN6QC3@WFE94L6j#@46e>X5;XkwQQ47=AMx4Y>5YI$(ejRC?UZq z1Ku@C(;)Lr%=zHjd<5u~bq&y7yl-OwS&9ka$yU>m0&dHk!i@4{HXESZQOc?y@Qw@w&_=vNqg6vj0noMIUV+bUIUhp9bMW-$7Z;j?kgZ|H{w5H1eRyIMR); zXpncI!n>od;!DWHlFyDCpFwM+Z30G&%F~!|Z{__AGu_r@ZqsrJ?ScIVnHlCh1MaJ~ zvF~;T4}v2EA)~Yn+LficlyMqiO^F~yPc2GB30C>na?67Ujo)R~9){>r`qowhJc1^x z##b2?4~i0P6X^0<vBY zQ$u#XyN}(dqVl1FpGSHr8KOF@H6E_7GPo_LpD( z2R~k}-nkW;*fvKS;=b=aRK9rkBXsUpF%!#;1*2<;8!4k(rkpoXsh^XR91g}d#_3sB z3Lt0By(>pw*jFB5z~t6l>&rj<_>Y!Ru0wl@YYG4Q>kpMvoCk30bsLyS;nth};TS-6 z;Na{u>42b3S(D4H5j%HoFQ5Kje%QJhQDS!33zbc>k z%%3yMe7u}EafF%OmE@Z#&iUCJ2cDhaMj=<_uB8)cZ*zu$3zObe9;85~UnCx%|35OR zb-~I)s#R4yqg=ph?lGSv&PcWz$Z3hxCa$v~F0l8f9 zl(|y*x#EeG_UtDHXy`6Qe9meEl0`@3Z@2@@R~+n>6y|1k+hoiDh3@SD8&|)M%h7F9$(WU}COh?AeVZmD(Go}U37y0-BckEMW z3MPc(t2SQa9(fuy7DUs`&N-@K0Y!3`Arfa9`)EFQ=bh!yv6EEzE6QV!K3;~IO&y;& zS&p1KTwZn44P`Y4W1OHMnIyqhZNIXt;(COGhdeNhQbjrNGXY}B1Coz&G#+@E68@kq ztO8?+Jz7-cYuB%5zYv`}=&}(t$AK~4v74~jICM`%<*+I;;K3sa?`R~IMm8d|GH98= zy=~EvG^4oOh%l`&(-PQst9bEVWDLk&WgkXlu|sjdw(*+elU@b<&uXhS2AmlzXrH(r~>Hmt$A1Q7=TI8M5l5aztnBxQ8KHN`|04 zDacNJ(}_qRJqVUM(g~K9&hvcwjj9G+2(=hgVlk2$8o|5CC-j1ED{cphhRFx6`WWG= z76*u?xbi6TfRO=68mVW}Yr5%_`eY=0=+R@+MIhXpSG;|sUN;!u9b*vj_2^|K(z zE)79|R=WP5kI)Kto|DAo* z%gbgab39mU1t(m461FqFfCp^oAW=J@o~}tukygfsN2Q+jrK>jc%Yn}o-p36?di5u42agu6rIUfAaNTE1&+IUoP)_(=FvN%km%J^K3cz!m~;? z%JR8bIjK%?kRsv7nfczwz{$Jc_WJVEANfFe)2%nrQHB6$gmWY6g+m3c@0V@iWxX@GeDR;1|oAIRtSdo#xdm z#-R0V`OTB3$|H|GUjE{*K35*xy_XwTHd5D*(RJo_D?0h?1_%}<)mic*M-G?UZ@;bF z%9VFcvq;zYJKtWe*t)a)`Jeqw+~lx~Ll}4M+Esq+{kL=NBwJJ>tb6XCEqC7ejk4#7 z-MsH$QsIvB(T{$#y!tgamA4$fjivaXaZ(BDBO?do$-bG>;|UV8G;aNq|?-v6nJqY~Q|HepF9X&d^h=L0JV(oh2WU z|MZE$@W>+ElE8|IY1(dXv7F+HLUFVl7kP=VC`T+?%ewOgNonn%S-Th|{mUq5&w0!XWA1Lp7$Gg}%v5r8cyzTApC=WjPNYpjn z;bB|Tc0ms0g4pQ#2z2QoBrn6D8GVG@bC`t1WYci?+`9ucsc;* z768wiXe$Fw(2sS?nemDN%o%w{;Ek4U{TE)%`9;MhS6U@lp@Y>gw*T3m@ z?l|31`WUG>#*!KDGhE358Iz0T|vR19yzOQX0)&m)1nMIGs!xYb%%f&KQJxc z3LO@jpO z#Vw7>Oru`=d-Z4t%}K((fC zd^?a}2%>JDegP4IaKt$XZ~8b-h3N9=tRjwaolQS8D$Z79Uah={0Tf9CIQYoFjHlzC zpFQ!(gt7LR_)b~rDkYV55%aC1UP&RrZD%`VkoV>Ld8}?2}EMW&%vM#*H5_N~{7VuKui)Ba{ zX|r=C9WG~7Kg6w@`7&w1p%s73+$H6`5gNMJ7>XdIhuedU!$JMwD3hFhrS2zPyh_np zfd&A1$#lxHQAJN(mk{+K2L+UA<|l0S0EkB1y~a*PuaPp#4~=^SvQ6?M=%xVdQI; zPM08v9-XFLg#R?Z{`Z$MoG5I7qaC2l@~|285Zt*kL`RUI8`5oB+7TII0DENBN^T8V$u(CUI&j9M7ZF)(S?)Igj+&bzBkij4X{id;2_nGg7KQRF8kfimbSG==gVjR@{8rQ z+}FN-(-r0ROF7ya*i;BDnS?|xgk?y7ZV{KUSp z_xRzcV+IC?xE^jtdFLB%Dci5uQvT|1zDk??5mv_1p(pQ8^E=BDezGo{Ava`Xmb>Sf z{pIie@LS5S{Jpz4zTuhwk;|EpNJ-L808ran+7pOdgyo$B){cSYNKbdS|4Y?GMW|w_bWh zu-k$jc;EpBC5Fm@1BXaU$|&-U=M1>T(E;s9I}=8|K-Wy0C^L0yrY4y3xHJ=3E&=pH za5cifusF`{ccr$*lVKLqXt@JN9X6ZAu75zlczfME3SXUeMR3zIYBdRcA#ic{BU?(` zuRl<4O8e%W-z;lc<$dFgH**m4R;!Y@?%4?UO(RCPe|TK(9;rEKuGd}y+>4Qt%i`AI|aYx}ZeB7b(if{LyLdfhK>e?>a> zP##R@t3G)}Gs@nxhjyIfv~envzB%qB^s0keQMhNybnhd>&$DN0c-csqJTYFL+WUN2 z#~ruR?5jV;H43q(g1mLj4L6q```|}7m|zPP3YmA98KqH9_oU(-B9pqu$0i322bHaZCb4xA=%7@7vou*@{wGz9vb z`D5nv&>ZN71OhZe*s>CmkOh;)PU3jQmMwXaweMR=rP@pL`P}<`zu&J)k~b7)=A3y| zzwh^b-@EVL`|i7M-$JH&x@YdK$^*chS@dURXayfjp$X?0xk~B&Y>m7rrATskYcGS7 zj?N~f9R$9y$6qTmp)AVFj1yQg4uMN8Qp*gT1j63=h)iSn2Cmbu+9PO#t17j$3>(;! zL=q8K02zv({37?@&PEgkVs?b_BmUwE$iQzyCdaCTj~1Msp)*)`Te;>bzkFi%Kp`WS zjW~h%NnfFa(Z8`Z@5Uo!67=CK;-cbVQdTL)&>O?yRU3geDjXe;Yd%08=_g;-VvU@F zsF~TIQQ+wXta?WnGrkQ)5r?>VXQMWG5szU5cViEnxCIT|Vy1<_Sesv_iL+qxTHgjy z2f+r-rtn3V8|VQl98(r(ZxTBhw~>o<~npb~q3=^~AKy^r-u(3;<-4K3D`N4(6Pg(c&FC zSP=_L8PMXV#aBbOk-y>n*Tk#ZQ9!YuDqjiL546CgIA)m z^7DjQ%)JC7}BHl1hDaJM36o>%b&$$cuN38=DeWGw|ts6ZSXqd;{aWzQHEaxun5Lwo0Lm@$DA=Rnf}0!%J>|zQ;)Gi?V&q8x1sui?42kYC zMs;tR`q$2APppixKAcYj+Pq9d&rZ7uOQnk%hF&Etbu#J7noDuztA~TG>cErbgT&>j znzpUF1Vr#5ArIB{>e(!#;gKvcpQXhTb7tFX)Zm&~dh!F?1~?K5nZO8x|4sl{ui3Ed zW|j|R$$O*Vsh`LQaA%=A*h;(c0i!9epYb-1^5Wrnp8o9ec^k^+H8xh2qs&zGcP%X^ z&Ydz-@tZEgEEgWy1ePNzkGOi+!Cm{$#J zEbRhSe3&NT+{D*LwWWrRjYktEprADkkA_hPCXxGaGx4Jix-?cTbfU%3q*8nvR+?xn zNzs8Dt6v)B8($4`>a1-u%dC^f^VXzjtV1W-Fvwldz=oSiYdQt*?hi&^5dusQC*(1~ z;L3S6jE|hd457ZsguncbK_EY2Ed0_dVX$kWbrehxM*1=UwhFI;d3c|J z&T_-Vv9m|YpMLnuW!p7Zl=r^pot$#tRj#@Esxr*U;L)}K((=0-zK0n+f6>-0*l5=m=t3IOtw6U|1byOzW4T9%P;=SPn3NH# zmAAk1UF9{m-&WrJuijXO7S1n!`H9b$gLK$t=H;BcqOy#3MXPdN0M8%#{XZ)2e)s99 zlkWTGx5`()elL>n>;<+6kRKNhEhwM(^e2$S8_F#=U&}Th1cq!kZn(OvSghB~w>MEge1*DhhR)y(aX!)KKlgcbn#o0OeX(qD+k$_-^d+O5Y6Y({JODF0sNy-RG}y zN{{-5W0bGxPU<33B)|4E5j#m4vU~RdE-_n+oIG%G0eBe{R6i-3&$D!XY@A!0xYBa* zAnD1nkQvT>*w0~$Yt~*(8Pbm)xkAEKTn;A6fm#5MqeO(#^Ui-H51cDM^^-rvR@#9Wu&L((SwD<$>zX$`#37)OZpJ6$l=X&b*+f~&;Te{+ zH-c)(E4VV4vBzZm?jhIhl4PI8Kp_P-)$54V8C~a5O^X@01N!a zlmDdB4jVkyPiUFl(#<#Ux`pzly@KXD7$ixg%%9AKy@8Tg@NU?4$cPi45e|=ttwC!r zU@sQWHip@@Kpo7s-Gej;)rQP`;SvoRp}ZSjy;UH_S}t;r4Puffev!_hH}VfMWf)9? zmCC?W%?6|xEBEq_JwCy#&ho7u#WFA|7QzZ@;^R>zZkC}uT~720N_%t%BIRsWQx`fscG#jQg&D^1AaE%c=_v?!niEJ}s9BmSKI$Uo}}?CBIb{GLFcb2&%g- zDK4?Ohz1Lfv^S35J=fs#(bNzizi9{%Yb2(dSo%FadJ$}Sl;*aar= zUf`Pib~s0lG(P4ZjAd*XJ4l&0`Ax`RuhQydvD4l_cfML^NT-xor|);h9=ap1@}}vu zr^{t|M%;L)@20i&mquB|j4pL|c21kL1}-Xy7Gr!?9t~Jc!>?Y6)9^{B#!X!_zee5! z-a(nrO&dnikNU)Nzy=vJ&hX|Sl*YW5Gb*MCz|zCi^oaoqzNMA=pJk@sQLb3VfX`WM z_h=di_1iSKIuVfTp6{T-!eMv-Sp^ZxH8QfhY)Ubs2oHmA!wk}X{WI@#UOx_ z3ChTsRQZkpNw|yh+!z5LuSm17;+Cn=5#{hO7nxG=s&;*lwc4eJD+ZJ;B8Uz|Y<~zp z(Kb5Mz|O{>xT8FhUtq%DN0n=kZfKzMhR_6D{op&SJkmW;#WsqNS z1s^LSWIP5LvTlxsUzB&oP|OV>5hzdIx&*$)i_dh3HU*Bl`vXN-)j56+x(xL7mf!iU z-{6qBMdi$?R0DOnLahZ)g*40?U>A?z^|_*s-JZu{GE>S=K8`U1J(zOc!7L(iWf3 zR$Qrdo~yCuasxx-wGb+(mfQ9uWUasc)md+Q^9D0}qTWXV4=9VFssKFBW|!uX}HaE(**?N^Aa zI`a+?`K`b$J3jok;Teu%f@Fe0ONKFnFY{#5F+Xen=b6jbv2XEFnL;F$K~gq_X@i-{ zA|gQmKs_zp*%g-yO-#`#r$axDO6-^-HIK|1v|7$z8TwUD$S zAG30R&KHkGb`;76P9rWed(6xeR~rR3rh7;2JkXJ2N4ZDkA*r%)1IyXYQ)P zg{DBm?+{jF^D{-8h^$(wLR!eDUMc@3tik7)2+?vEPa<_zC2%K!aE_pr=O&EaIuTvo z{xyv-(l-2fw9-F>9$13Ym~Fx>crYM1YZeMb0jdX5=Vhl$qygHbLE<*9x<0#+RvO?V zNDvLD>K7D}NF&2Myv04@?p1UKOTChR3zEo;#)Aqi8aiMzcvJwSyFA-4b@fqn?kg-X z=7V5EVd0*Ulbz&K|5`velO`^G1l2^?z?XJ;&v>LHMca~p21zm(aSsfEumQZ}%eY?B z^BFucoMFu)OPE1&pHv+1B%^SSNMkSem%jAH$j=)#a8f?A29m2Yu=1%)>};3@#xDj- z0Lr*GEEq^)bK^AEE&Lm);aBCYtj({{8NuCjj|MI@qdXBYF#c8Dtmz-v@T=c)RP8v2 zk-ZDeTxKhT?iUYHA&izL^jAyU!LOum{PIKY(cL`5z>|w(+YpY^V_ZYTOucR%BxD1} z5pQo9$?YhdpiBiBoiOntqXwxMvBN=)q_i$-q^_xPs_*LF`08vtW;>@Rjy2m`K9~>H z3HhozWiSuQiH@2rL;-_lB1{p1zmgYo*rnO&s7HsvE7Mrk5?6%SQA7O_v-#vtW_w29&ou=jEgqIBPxV`bi9@Qsd?d34llkHv%&G3a3l z>kQiXuiQ+S%gtG7~>eW_|C6r12mqdU+PxIH6Sv8 zJ`s98lQ?MymvRnVA#Jg=+=Q;Uqa)M8APi}Nj4O<`L_>KJSei$WOx}b0>Pev!xS54N z&oye^T)+byuI#W~;3p6Kyn;^+&@E=v!Qm=Ejt>3FGPGq~S-Y0@EYWqgbmf|rEX98`bXqJPu;`%es#UAd{eBLL zJ6TR2+s}2g$ID7ii9bZA$aa;yuUWIU+|BH`o&N8B(_6}|FT152IXPC2ojO3;gUdlb znkVKN+weEvaZTJIzyH9ga&XU{^2Ae5(#hISy}=e)80uzb*7I5%Kv=VOHM8j(>7c&| zI;)w9UsE=(A66oa^A`U>Kn?f5G1sNtCs*3oP8g>C-1AjSQ zmF9&s)S>E{d`Pdt!)0Z(vJpDu2Oh0_Wsuoe>Q@cs+x%sovVC@hvgCmW9xiu%^PciD zwn?v8y^dAYtB{%7f4G($WpO}o-I^=Q9@=#e-uF;+Z2Oq)_b|r8`}cFkQh!;+3Xu() zw=h||jC|p$7gkDe?t+J9QV5q5$4->TAAf>!xre^sqIeH-0AoLT{My&OzP!#jpo8gP&X9gT?@c=iB9vKnTNASk<1b}5JSZ{${;42H?FC++o_WjOGSprSmhG$hq2 zKxFPU)DB8yy_a>|9F8jL7xcb-9s6M1M~#J*nqNL}<7dU^QqPzjQn-T0FZThvgx(IZ z4SFll`Hbw{d^1-dkidu7N55{}hBAfSF7qUb>`EK7$|D-f7^9PipLn9IVZV&Rih|FI zn_u)ApobntLp=8mHwX1`*oh}8%C!e~sn0IWw?GV`H@rt;O0UEC8OleTY$#aS+Srw5 z{IJh$uoyf#f??4PWe`Os3^8ew8_gVo35c`))eqiR4`~-_U#Vh!UyagY+ z8<{p=I#i>tygrLj7>#M$s>^eG2Nn5gcyU?2_lhc?6DLl_3|#W8+-GQztZVX;C(t4@ z>|v84;Z7*w8g*Y46qc?-GgP6Z{Z zC{I)bpnL{qJZidBo-0LZB=#1y=9|Em!PMx%cJM8~k=OXPe9}~&jJM0wUH+z9Zrvap zVbr(f%a=#k0|ySqVT|IolVkp^Gxv$h*eRtNH|f+EV-1u3T7$>Nt;I`x&wUsP!(oh2 zhe_$BpFTE_Ev}-I2do_+hvz5eCxvX=shm+5X<6oXl~c-^G4Uk++o{&`TW4Wyhw&($}^r|Okura1hyOoQKV z;i68)9_3&o3}qd8nYVUt%aIQ>H@*cEUYG@OBSS9Nj53vS)pU*qH*m9PcQBEvZyu#Q zRv+-QQ6+n4I5%bEh7AlRF5u+wy);76UwXBc@hTN0fJeh| zdSu3o?Z#`j(ZQGL>}ZW~xAUU4E6NC0$n8CLvRr%Jjpc?ny{Rz0TUOG(>X{rV<2xQM z`@TfyK4zeiJF<4rgQH91u+y38(~*}{>4+Ddd#@=oe$KA;(&%>8V+=q?%;dVpRk>h~ z_$dpcOpHa=*cEnKLlWViVX7GLg=XeUyrV-w@J!gilbv{R^BIXJSV%7&c}9mCO6p0L zA?X!KSfPRuf%y-Q#(|eM`8RJnh>>SC;Q&7#C}u}EjO`N#M^K&^m_nzFPfS9Hw*gB& z)N|VlPBKa1;zplVI6?df_^@DSWPzIdF%ldUI%btA)$|s(Bpv>oV`lB3t7uOb|Yv))dy^vM7y=(qqNHy(_^XZP86G3nQZKK3rK|G;XT1@OOo5eM`wET8z~U$ZUXq3G;6P`zi*UfLih z%1*W)JpAx>1{XF$waMG0iQ@H8U#}1zW)(vob_R%MmeQnCIJc}dwOS6(U@^AO&zP&K zsg$Zq=D38o(65H#O&l8S!3umwJ`{b1jhxtuuQY0#!tl1o960n0w86o}<;d|ptZ+RG z6!K?+(++hEXaz!Vo){=sZoP>?r|$CL{oiC|#r?D=T=CIOk;D~tW9PWRU}YItJP3XA zyoun*5&2)*^7s_1Hx3=-9E6^wS%v~*KTQ2Gjhu|Qj+FzWv^6c?<-u8g2Pda#?>M;D zGNPA86Wereq!!LqLah)NwFC;_LoFI~wht>>t)0f3x8x^{IqCA6%h$2L2wyTAg(C$> z6^}x+g10k7x{+9^hF0Ea4Eti3C7^)mHDmERN1^oE+is5pW&p38=ZcPT?=qy|oX4J~ zX)>H6%@6#;Ka{Zp`^&)QE6X^ChYf`qfRfJk3>_r2z@|d*W7TfQVgN;0z%n0ds937x zQX>mBWK&az-loGkO;YpSU>7Z^t7VC&a-9!vqyAQK4Y6(9Tf4{Y9fDa5e7o1aQDr z0?Nog-eIa%=#O3HCWOKbOyQ_Y4XC538I+>$rlAus zIN3?Dq3E|GqQYnwXTWH0(#r2_Sfk2zcx6mD@)%w%lVMYS+41P`Y(sU#tL6BDEg_#2R+#s@LNCkzQvmkw|VTjn_whFo++)I zlt&{|%cKC&7x|hmaSG>5_JCEsbv7vFj((FT)zL`vUz}i1wLGewu`H{+S9V@mz@KHJ<)1V3E?qO6+fWuQ zUQEMi5m$~L3B0C*Wss|_;@~mmp^p#!_%ph~<=YsiJ%k`EM*n9rt#rv~L|g)=fuvc( zWB2@$WlNU@pWX;@l0BtyZh!-{0c)V(Ov|&FOYnuW7@nKC2%LF5692hj_)bAp&Zj?>_GyNm}~+Trj#4B?`FZs4*bV#C)mpO6u!Oyi64j8}BT8+ZdG?G%QCmbr?r z$pbjsx!3r%K6Zd%)yh>g)P`fbPA{DpX*>HTKXDF9jaY>2e1JEgov}&0HrAc_U&`vC zA#~f>9bue3H6J)zukkQ1YIVve_d$AV3VZwca^S%L5r%l#R?#TOG`=%0M7sm`&d#TP z!YYRd(UfD_LpISSNc=*m>R!P*f8nCCWPt4m4nV-mvgJ!TEO=8{$;_9Xn9bL7`^bsm z@^_#8Lb;k5&8x0w?=UmUcD6>iF1UOBy29n%AX^9>2T$34c;Y~rq{G+i#0s;y6HZV# zqCvrD9`|~tX_mkujc7|bGiygO%03RRnwav?KKI4e_@}%hufTX@Q{VjMhjNZmpHKby zAzS?|Z$qy@*3v5+6;H@Tsj5ft7T+QlmRB`xxDLn0Gs=wM1&1bVg_8f4!7;OIEobD@ zl(1cho0S3v8-Lc-4p3!%J&)N$XYs=~gd%LlPnvPqqk+R1()jQ}_zO&s;nC!oj9Vj| z(4F)fBabZO-nzf}^he6*um{mCM7OpfoqVGgiLrHAzPP}Bw7 zEj~JYgia3w0L+LF@belw>j`h!x$nNGIUsMOJicQ)t7*|e=yuaN>ZSfY$Nu^l_{J?d zz-LCHlf0;$Dq|=2wq{K2{kwfaJ#wo_PtQEyX(NSRdBq^NTb(;ojvhZodF}dGMAGQr zG|T4S_P+O&_x-@z%1{2}PnPw}?vK(LSiER{`R?z2T{%5GRX*{l&vQo4i5P%fv3f;0 zePWcdVZ8Kl2G=PL*;~)x)&S>FJiY75^3894tsFkGvs`!m>tp%-0hV*H9u zbMviUW+WOoK5CE}#*i(XfJHj7lE&3o$GB>7_tU#r*|ELcc=OA^W$TrEz#yrz^P0j1 zwA%<&&eOTxuz6bXjRIh=R>+D&B{R}(JakWeRjEobbXX>#V>L#)qH z2OMPpih~o`Dk1)xZhA3gv*#gD+ERXb_@Qmaqn!C*z6>Lph$j~QYhKFsQql++q&L9k zeZw|>f#ebo@cI`LLP$Y|cgPDF`?dtIt)-{!G235ZaFUnwdJeQQ)H6OWd&k}g$eO>< z86EgdPylv7iNA?zF|%5TTY+jky;65OFJ61+>F|Br8@U*mvotV!_;phVQ7Q#OD=+8N zXBfRc`t;M~^pj7P^IT7{`x{>`>)9hS52cx*uu*WKL{{W61ZbrJZANZ<_t2sDKt3CU z9>!w=dLWmxq@H$vo?kQqB4On;jd3yos#3%X1RQMmsOYtWZ-HNpu+cEW!HOjk5r5$| ze*3dw6)F%yY=;jZ;c(Km!q}jxE)^!pKtzOv{=;fhVjXlZLdA6|jj~U`R5A z!J=>s18k@11W9+eY8+=l6EMEP6X>J^oQ+Or>cwq?Pd@5Qf&QkaIxSo@bg(<{5Df?j zT4;z@lImDA2m+V&D?X%QG-AQymJ;tU9!DQ7pp>ogapqCG14yy*LA>CoX~k#YjcCbV z{g%O&nJpQ>fNLTdFxd0I6(Sr08y*^8fwKYZL>~YbKBS{D7*UE!;54&H>(;F;n>TNc z3W3Pv>ICFtK2dfaLMeJX9kKlZIVo4;ti0kaLZPAsCUip#+cO!{BlzOcijrsuR53Wf z)i3}r(4)Lk=8?|4Eu=M}4@R!Bhedny9rz^HAQsfmB%ILUg)W3+gDWwn|1&)=1*Z(- zmso>Od6l^C+NJ2;d1Yx9)*;F%;vQ*0#S?====3>GqjrGG4per!GN16QQENp>yeYh} zJgTyU`d0Me)WktvYv)uTJA1JtAHL&VEA|$L(&#`MnDddeFD2Cu!2hSL zuqJoPsnZ1C9d41<04SSkI^8OKlusZt-RHAZR`@~oOb#%ccKFbt=-68>)vzgfai$Js zkEF>@$hVVTCQ^W=UN!O$m?oj4Lx{bP*=Oq!m&Ruq(3F3TE*j;UvQ9R|yJh3pCyXM3hO(2J8n zple^6PPK!McJ%F>267v0+0iv&T*e;q1xHj%Ku0YA{@@Z%<6}GIJV+hH&H5wj5C;|F zkU{WxC7;OLD!BR9OCNWrG*_&`EPSek~UjNY+4#u*SQs7bbfMfk(B5EaF4yX!0$r z&N1Uhn#TZLrA5jN?!aN^g+_76=L?MB;* z>VpFz^O#i@&I29QN0%MDiot?ad7vTqtG5YP^ONOJ9e_740ucD)5yHw(F+{t$(T9|t zvbHW_RUe9W-WA2{h+hN_{$WB-Q9G+M`Ow|>(#<+jN;alPWo!g3-8><>2E_ zGDFWYqMbX-nWvv9SF&Gdzy=%@SnpzsFo;s%T4^pI<3`0wA#7o6M)q0~Pl2{_H$knW zT~6hwX3Q$uz`#Exp7JwUR018X{97X~xS2rC@T+htgooYK=$pu$KNDILg*$A90<{ve zvG8ic1$gTr9~xzrs4At3q(ZcUBz(uS(r&9-hP9I#k>(XJfm;64Ioz~D+lEdK)Ci25 znFB}t4B%UA%FGUIYh?m%`bYeDx40J=k?UfkEsXwJK~G!6k+eoHB1#QlU?h#Rqi^NObvfv;g@=0JGQE%i@HNiHHS|8vDkJ4(VWpa8 zN7c6-5i5|;iH4rILkQpyZ}Qhc1BcLG-lmUXBN?0U`64amh(eKOo~$@$1qfeVl3w}= z-}-KnD19#Vgiome>$1CU8UyaHpEqw^GzOKIjVl|9*`RMT8T>_jE1~)pSKAItn2zsD zu+j=L2R`@{Lkqy9w+6t#PBh@bpPk%1Ku*{gs0pDOKal$C5OU=x-ln%8i84^PSk^D% ziE|AkgrW$Zv|P$u+^>^Pg$Q)=7dU;T-k680?CmtU;z&l^n&cslUI*oVbr~{@jd=69 zy4^OJ*W3Je=t&#s8Ewf{Z+Ru^ zkvv!vYbQG)opjLpLX3D@mHR~ybVlGJ-p|P?Xj}*>>Q1&h)UX9y-9lG|C*9}A%%YuS zPCTbxv@W)xbmHU*8XP^*!MFUgt}|RM*J8HD3P3!KTm!#$dF+U*VY052L-Ub&-Ezt_ z&brq$tD>_`rWz#;-FD|-d2WUAU`=OVOjG#{T+$;RLA$MdvSr1Z?|3FHtqvMaG}mi7 z2xLPr2I%oiyx_#1akVq99x?DrM?*bwhH4S*hed-!xH%wU!^{W^D=%4An3u$qVzOMv z9T(kfV~1Ut63#CV6$1*sUBXSdgP(PYa#{!-WxD&o0j>=@UlzY?wDbcre2#0?jvc0B z=?ww%$|(;YWtM8miZ$iYN4{CMU3+cWv}`4(qMwK>%TBTEdGAwCmWk1+vi6FNW%Z^N z<-pD-%L!IKdR5d6OY|p5Zu6^wr|Iksl>UXRrerpE1ACEkw$BuxZVL7(58$&i zUqzXg5jN5QXS~B|WE7eHVND4tzc40fCMw>fH||ju5H8vh0I8QXy+o4evVk6H*Mtvz z5w77b?7E7}cPEp6;}ag0!Nx7%XrHpGWyg*^rDr+YRH!FzX36^qD?U89c^(5nQ>+-Z z{TWv(lAlB+CfkSVfIQ2edYc3L$e4ye%@38G$ZruY%iQ28YQ=H{j0aXz1;Sy zo6BGP`5&^(c~1=196QQEWZU2iklxl6B6RQRCH0}rN8 z7b_JObB@C(gFkle-}CMdlxwcPw*1APeI&L5c&hoXd-Cd3yr}N&= zN*0!H{~aggGo4>nEh7BnaQU9syogzNJMPEIEiZd1`F0U}E~FE`o!MNkaP5heUgPk* zX7%c_Y4fJCb?Y_Ud;bIn!tF*r-rSQb1(m<@wpcL*Lcf)$%>J`XEf=00NgJ{fRUxwc zXos$Tu!c4CsO=Pvou7vDJ0|mdn{N!L5k23ji{{aEkMG9MiI>}Mdv$s38wME!?JD;@ z_;C5yr#@Bg`St@0$}DC7JCmpk7TGS130DV8C(f30q{++_1GNnJc#{O{LzqB7lhDcD zfrSh>b(bZq!W$Y|R&IRpE#>O1+qmBF>hjY+{cmH|erRwRD^CU)@EI%r^zg%xHhq-M z2N)Q5nD1L(@$x)B1wI!ta6HN~f7|S~)8)S!t@it@gZ!D^Mm*z)y#bB5H};TGMZi1p zwehA16S(3DH}EP&2aX)5u4O@>0$j?M!(8T$eF`KPYXnfGqK^WzAurL~kL49`2%5z3 z?$3EFJ~Bqq85v!|tii6Ye5E{a=bdFfBYpGu9%ot3c?u+s&M)&Asat`vY+JFs ztn6D*&f+%BJ~NfaLV=nNop;#~9Vuv^W7N)*?;Wk5gs%HbO~W1<4(L{VyJ{e20E~n< z8e?)~aij3DgV%$kjHZ>n4IMLmDh3T6@FyIhaQ9~-`ZG)x3S?6%yDZ>kH46*L+IR-R zEFNSfGPdp^U&2x-wlaH5=0aX*Kp*hw0}{TYAzH(=@P-Fq)dOqz>7Fe48Ag!m2IIQN zm@1Z5MlhH%sDCmNCJV|yAWYE6aKdYRS@|g&eZn*^?aE3ogZc=2^VaDC13>Z>&q#*~ z)1uipm^Qiv4Ui`dpJ9u%w9%P+Plc5q)1(>P0E{xEWu$0h#91Ia@#3~n^uE;W$g{WA zD|65%r+vg1g$y`DrZ^;xq$3<4LDNP#Wb6p)TRYqpwu+;T7U=;f%8XCjM_Uay z+w~$}4KEk*!AY(!gURU5Ms$JO#b~8ljiVjp{AHPC+FPetM{DeWd&je@?d+H<7k}zi z-A|oNWcajS{ArjBn~a98ip$wf-qN1WjHYb?Wu1ejjYjjWSoIUug!MaYqQe3QjYED1 z7mZ)o=RAyCc!SSImURr7Ap%=|o980UAtXsVLIX5VJp;gf_VmGN43b~?O;Iq|-iYl6 zcIK^uvXcrN;k;H?J)L6JK*#_LYzh>JPTEu%J9`?MJ}4r&FEdqpnaLeuw*KI$qbzk@1>AUfjM>OT zYnPQJ3unsGSG+n-3tzB&UU_=Q!CXm6njATLnAu>KZnMI%*Xw}k;CFcndc;i`Iv_(F ziT_MzWyiO*mSD=cWfW%1s5gG|6F$7!-{FRz#h@vZc$A0#ehI4_>o47(;xhsw|V@S8b>``TC%{Hf3XW7&U2BsOVY$;^XilX4Nfec z<0Sm|ec+9BsP2nv8-I}N?!3D0lb`x@%t(7UWIvr+C%P8&dJrX@dRE9j#=y=44?R-e z@+M|oSxNWjfAQz#%m48A<@IlPOZna3dq=sR?Hy;h=Y7$lrR9N#_fmI{p^uYgoLPD$ zJY`&X2hQ$=tSad*_uR9+Jjn^=@Bg8pIt z8|S#3IDR6o$lHJDSlrrRJj7;P9Tw|_&v~o}`SoA_AlKloX0QFaa-0<>%Cd{4+i@-c z?Wc2W$8|vASAOE{WeHmnCK%9|7(HDcVjuU};R)h@oTdJg<;`!tjo%$*=i`r+&;R}B z$~W%5o4B1uzx!i$caToxAZ6bAwQE>yFi`Hj_ueQE)l&x?O%2l}On#*O1wK2|`?;V9 zk|CXh4oS%l9+?W*;jiH^?CB$jK%IW+lQ_kZc_ZW3aup%J28-b%{^H5MQ4V4}&Fu3A z4sCquiCyf0-xUK*_uh9uhZ{akd3CxR-G3->{P2&xr@RIEd&a`qV+`Oju+l|d85mk# z_Hp~d-~82|vL2gd^c-kDeSU<&oEM>YE6SQX?<#M5+dJsoZ(){xF}gn(ZAh=wGhNgP zZ!x&`+UsI~`WRa}+-l`ukpo~O@aTk+?M)Yt$K)4fbmTqWwsBk;>(9C&S7J8<5y82# zK_-^%h{KrsU3H<>O985^LPqtg{T9wY>Bgi(+v~F0E_27e;jQX~0?}pAk|0sfALZ$7U@MA0+WA2j?^MyN0}Ye8#7>V4eK#KyjS-p+d1C^4Qyo1i3P=Z^$!8DPX44R8g;e|FYT8p6bP z3tWo;{C6l#sEJ;v_)fb|buwbaJM~j2!vfWcB!JJ!7{5yccIw_-s0&GD!DqZ9@57Zcd*bm& z%NyVL##k=($AA2h*oW7eAqS=r`dsw?>~CdsF(cpAC*C0dWog4z7oMThY}aAAa_#t3 zT+wNTbTdPb`Zs1CEV$9$H(AaCRRsxv1&&{;(t0my{+n@GM&Qezrr-P6a?rm#2 zOg7N14A-n#Lr2bKy&QDNIV7^`fK!CUZlg2|xZC>m+U~Qlx+ncg zTgv7hJD(2P*7UK_TM-!~IE+U+&*sCpNO-pE^ZAN2ZA5cnIMYJce+GdIkv@MH$Y-NQ zK2lF|KY5m4#vybD-LU)_>};WFnKkZ~hTRU7{6C|Ng~0d#Pw0}$k^hM}!kcSy zx&6Y0GyrLCo@DQOKR5QA=4v?OJ~Y_R4Ik`Frri?PL9*{XJ8KPoUWhA9Lp9|jJtCnj zs@!a!Xykrol9+Q+G_43u6GGP5yGJ<@de1TB#C5=&3Lb~&k#8MX9N{GNiN(<7tedmU z7ULQFpC`Dga)LbU3FxPpDShgR9i^Aak-bmsWM4G{(oAAJ@z6-Q^>wdg+4L1$FHGHY zjG42ikHr>6xv_4Wpo4$*>;xx>bBNwTuG?dkhkP=6A$Pp7lZNLb{t6b;B$81TPyLSg zhF{eg;u`r>*#Q}{2?RdEE$UfhrK$457M@A1^J$;}%?GrA4Ej+w@?GDv^|OWn+5nLp zZA9AQU`I|=ALLNUw|?L2%9>@ApXb*j-&5sdpZO|eDI+=ip|`Imw$pjDQx~#w54s(E zZ*X!|sCsSLFFUMArx4q?i%CG(UZ-wZP{3U^_TwVvg_$R<#+$^ zqh(S5va)jdI@(QxF_`s3@BiVl`HH?WdWJl}7Mi`g9_Ns@d&|KCd&}3qem4UaUnoEO z@BUqR^{ZcvZ0S%k2=Rq4e3mwdr}Z;H#@2!p$Bz^D@ff%#H-_9C{Igz(0YL}V<`|Po z6X}`O@6a=HUZWQc35cg2@r@o?3RV-g<}>nEhes`w+Rzz3^J@A=vq$8SIcwnNjk{r~ z5#p?diRm3>-Nq}+OJ4F4PRIXN)W=(|zBtaej022ET!nDK$;?xGq%Yd zCpzkkj?Os4Kq)hyyf$S5S&&;{S`pL)LW)aS%I}Gsjwp;$`FZe|%Yse7DLV916iTEl zbrgJ3;Km8)&@%;002}ruhB!4gZmlq*lE5RCrQP6(W!Gv*hp{4YR>F+nKi$0W&Gw2J zQWaOZEGWsI1Wyc2RyA%-*eclQa0D8eyOf#D$AwV(%Tp4}%CjBDEbdoSD&d@Pil<>P zUPd>(1D7$;h_`t+-^Nd;I(QOtWTOoV8{C4Blf0RyT<8^R4}y7SRgnfZOOXENHb zXWE*fjQ~Hw2Txc6%tsJt(Bm1EBbBTjAx{yv@#!*F@u(9XK2$TV=SO5`pV2^Yd0?DN z$t=7^(C@R1hFidlv7~6R+fKv-sV>qZS1JS-!9>O@8LIqddbQ)6=><#;mTX`2S$Pyk zwOCzQt*REX=&swPJX`XVVv_sUL$i74NDx~DK zlSmG-$yst_JeDq98s&z|s4Pd6gSt?8RzB4(u8^sM(Vdsns+^xm=9MdPJXaHgrvQgO zNKAV?NLzT2rH999b0HDy?>0ut|#0Lu|jEN*mVX)w2Cr#6q24x(2Czy0B zAKd2~*WE=05)sBvzU86P6^l6WXfjrdlwOxG!WicoOcbF%GSnc@-(L4NCX==E^Vd zboFw8FoP(-OcHS>@}Wz(ar12#TM;?I99gjbo^ST2o<31VIRNb3^msWPQ=YiPTMz!8 zYwPNjUY6Lq4RHZ<#yNoSJRLt*A#^k2_0R+Nvaj_>S;n&GGe^&sF=jTq**C4w?a+*p z=g%_Xa-0s`Oy6*H>}RN(l$#xU^BO&#Sfya;r~53Uw*n6nAFc0nPq$1IfFf~B?^cM= zm$_)GuN~b)UuD~&V|Yj-1`n#%RaPV=k_g<19oHI(1PD?tbw7LZC`;OxBG37BLZ`|X zKKGgOPY*p>M$aBDUwVjHNy69LB&AmR`!W9tOf3XdY*ex?4)Vb~oot4Na6cy#6)pqwg(GJWUx+$6Ra+ zS<&jijVnDS;Cq7neefs;Pt(!wf%fJrx0X{QUFCN_^cQ8@md)jrueycKZXf4093*|u zvvi%A*r&OJeD8^}=fLSQ)5EGR+U~AalP}wb^I1ZTDzj>VZ36r@UAd*)hio2s=z;R` zmt0$3as#ue+!O!s!#i1dn|$ot`4mgHca)>2IDnDs&JK>b3dQa;D`^qQsZ+xo5V@lK z*WdnaZp>LtRL++nPQ0fJUS4(E>&jpK)u+n?4?Yf2_UV%^&vJd^{KECs1L!{a&(#KA z@A%Y{k8>l$R<_?VdpkPJvh3m5W@MhVQ|YZm&i=dl;V?G02))Rp*Gd=vc8i-;!jSp*^YZdywWx=s>eF(R^5XgJ`CLiX@#w@mF4*E zz!C8$&T&Q>Y2ghy>hc%A^!Me?JHK51`yc*gx$(vuV&bNsZ4x_nJ`pRvM%hj=$Rw>R z>h|v2M_czCE1x*B7k!8o)$lXGm7^OrZ!WtJ9;GblExY$URo?TS_m&_3@t;5sM$4x^ z^>?g5*;Vep|JyMs^uPo6)4^X>zUPf^iv8+OJozNNoM#2bnX+ZeRpdLa?xl^reEBlM zpNzKy|Bz!zs=I@WlU4ll7%80Q!tq;s}SfMEOK|CQhfx z08MC?(Lg61l!>N|T|L23cYYxw{i{#~ekNnM8t9qes$T;y{uo?>c8eDF@TPHUJj}oH z=C2+A8q4r0_jI#NUc{)lhZn^)TTuxT4g4-NU_?G`uepr3C30cdXLgaE#Y;6cKCL*0 zhxI@jJC4rWJ20!86?Qc0oAT9!5N9hM7HpW{&#4;?7>N>dNWv-QEbGb}q^ww6xKa2c~R-?y0dPH)+?aT607i_1y& zFE3uTyj-z%Lpe)lZXs#9bOrnA`CHz*B+|2Mgfi{Ku~O*R_p=pel5~JU$~%_*L&?Et z&s?0lh7o`Mbd9vfKXCJ1dF}G*HMWf2PltK?t^?)z zt?SrBem$LtE#(JEpI<&R%E|~js0=JV^4QMum!JL$Cv-bgFMn>?6F2RG===vEaM#$R zUn`z4Xnv4~vXFzy4jvpS>sAhywX2qur*@+U-H(=x<-{=Q%;9B|$`{_8R(0!ZFSk{BxA-*Wsh#~tckU@;YZsOc8`iM3 zWTJfX@4i^R^re3+*K-Zov6FPHaZ~pD4{#;~D*{RnH&ijGJjMADlT#@Z*9lp^d3%m4 z8P74%=PeK;9{5Umv0~+la?{N(VZiAe9lisUFXzkWKL7bL*mpJ^XWOf1#BOQ?6N!nZ16{hwwI)LV5>p>4R^EQZRmk>YmoB31u3#;j{ zHZI}(FY{2ZgHq=+<(B+K>LB52fU8Phop@*HwAB34;T_f%4pHbL9xeQA+qtT5^X4nd z54`<-46-~}hFDFpk1aqRn0WKeH)8i8%jZA;nexE>_mvgQ_%EcRevC6k zY=^!3-S3Wm***7st1=q=yYlep(WB_4X9clsg|b$@&DWNn#>4iG<+@4WBjTHMZt)s_0 zq>hfc4L}7##Yhi7mT=5R@Sb2fLucM=Wda>BdGn{$WHhll@UT!7`Tg$$@*yK$0+ICAfqAJPxRZ8&Vnhj4){@CB$;^u*-%YCY?~;}jzH%Z@bdk<4B#1} zdB#im=eM|0F1lIJrMq_B>$h+YgaqH%7qNoIJfh5msSVYnmKY6l*$wQq_-N!2c|Leg zJ&<|~&LIEfEn*T8wPUY|<&c&^5nnO**EXS7&{7K80yGy|+UcD%zq06HPE45(nr(27{Rf!l|8{UfY2jE4=g z;F1PxTfZbO?u@&gsPv131=E_|7sB7MBFa(h1RF$G-(K3r1{hAHSZ>RFV}g z#vpLaG|M~K*K;EJ#*G`xV~;+@>LCvBqJB$%YZKxDYcVioxIn}+5c^fj?n=QoVUUdt zTXo+V$23iuPOzvGT2W4{DNiuk@y4%~QxcVLSHZ<>C4S1s-RZk7U$v!ZX^nnl5v+XnlF*fz+?b%V@+E*e@Kon3j48GGnWPUawfE}wQVmqtmn zSCm2WZ~WEG?ASBw2_HGwX4`__SjKORnfJ3?*LD63*U)h#SO}9g#}sWABo*5aIZ&Lz z9hS5r=m9!BQ^;xwgADykxF?+U&)E3c@{(8IS{5@Sf8YMSWi^N9U31OmGBSL!oaMT+ z^JhoP03FkXh^BXdL#9+6=qd!$(KegsiL6|?lq-S<%M3RJccCA~VPf3L4AYLbSWBpl zY(vJi{HyZEk^hV+#k$%LhYA*r8ucmnp(zn3FySfS4X_RpdA6CAC zRCSgYbSKJJJTf1(-wsMIpiMYDJW_uDcYe40hkySI<%TWSaAN}f;D(Sh$#Q?wi(kYc zbjQn`cRxZ0vztx~b5k5RXS>n)BK6zZPRpvOIgsHDeo=;F5890kLdS`>e6@7jwuGyV z?O3zAV)Wbl%3D8tN4e$2Ysz=M_Lb#tKK2RRd&@iD{mwXa?(VPOl{1pyv=g;}{rMhL z?U_|mq~V#>__iS%Q1q9dOo)5o4XQnv5h&skYLWeum*o8X8G_(KEnR_p|Wwq`nb;YEQ3)C`j#-5K&Pw^eH=em z?!E6m1_w@*EgM&re&W~9wP~vv09d+gQQ7{;!)49drK}84!Mn=p)$3vqtCwr{=8?}2 z9^B7h*cEXo<`4romy)Q{zlgMt#5`Cr@EMiw=gwe$SPno7q zhubS&`O319j`+a?N6SAlQy=F%P$n#0vb0>aWlPykAMdGMyIGy_5L^9L$AGa1^13yp z5B*Umts`QE5SiuBk%O!lSy2A|@4r&M@r?(|+ur&EEaU&K@}g_E5w?pPTaJ_;dH+r2 zJ@0)lOZ8Wm^K7?pHRbhNw{pER>VlNE*an=5v`;l;MUZ5m~m>7+%Ds<~L| zRliHWYk72Oi0A5K#Gl+5m>}S#l8k-vD6AEjf}A8%QQ}3V*-J-i9wVk*j>3WK>}mJQaOy2f z`OotmQl_F9r{OxzGH46U1&m@YfTv05E5=^-WOPw6MotB{SI=aeAOk%ITkMoNLK%yK zNC*o63x1U-Mq2rfFu+G+0e3rdk708KLt_{DHH2N~dk)UAj@>*imnk%yjFvamHU{2r8r;?Gj!C{f6cE;v+axU|}*W zjuGA@(;nXm5TEs1jw56ZE=)M4obp4*1egWegqh_gXf+Y1PN3=mw$4cC49zUy+VYLm zs0{iRjCTxn5HTBa0~|UgE*oxEbk58>Gi75)e2xr?+|E^o2P-;bBdM1|ZRQ$rMOw(V z#2UH@H}`vP==yD-Cf?QQS>A1Ed6RVFQ2(`Qf+a2ZrTmh`U{XD3kkq#!%u^Pofv$zA zViehT&SXlq`M;1-#<6yaYn)6xK4!Q^K9Kuu`=$b9;$;=s=}=4Wqn`eB4BUm$X{k zv=bIrO#{~eG+)6lY_!7#Y{w%21&D}+Zd4k{cE!Zo&Ue7U3HhcPZFP$k2@^P~f6xY@ z;cSSdF6Xy?{;KJ)rqcxu4P*!H8aCdY$QqA~)};{53Y{NOpSIm2WD^M+(l&@TZQ8^E zcbtQOr|H@H0jKO{nt|rPa#5a|az*6IrcEwv(dekIdN%Yc*hNqVFX0bP;~Y4VliQA> z&cIRGTLwBtA0%$=hhG6B5p8&lCn@ALw05b7G^ zn~>y1aecY&B(sIbku&?p2Ny3VE&Guf(@nH%T`_9sejfS~`GJmNv^8sdq;D*IqmOWs z{K*GAdM*XsbnXL3_ij1KY-c|mb9V7f$28p8)(?2acpLnYL*pL1g=VYBLU-@H$TW-AJ z#&Y#F*Oa@yad+9g`AWiAhI3mP%kZPUg6zimUdYn?gQVSez2>{hTi^D!vUBI-R0HMET9%_+VMSY*~5Jo9-w#zUYS7J3k38H@)~K&Pw2h z7u=HP>Jih%{-t?uxH*a5i5tsk2a}9uH)UTnwv8gs@wO~@t|nzS2O3$WZgi$W(sniE zrR6;b&-47eJRSQ?^9x9~oKY4>CX}ERlBcJVjiWY*aWACj9<%fOTomKX<~%AVm*RJm z0Cm}(r5Uo0!obc_XrrlOW+U;mdd*y~6)hckOJOVjZv31noubh36h;q}8Dal~1<=BU z?7QbZMx()zpnmouO;C}N8o{e?N0rW-!q|fdbWALj(uApY^SGUKKsYyk z!MgU@pczKGVQc&YX*?pXtuXMek!oXw*CtH(T;eecL`BZ%CA1%wYgwUtxK=dqDC{#G zvr}OFYr)n@rKR8?^-t4cNxF@D^$UOm3u`=xzp)Kx9=X&Pw+=Z77vJKHK(imM@C{sa zMk9PX6VDDIAiqvz@EW?>;U?daS#itlAbe9YDi24mMRJZkM8?ws#l2Y`oMWZf!*V`# z#16eE9Rvt@pu@U{UN>#ljZYI<)1&Hf4Rf(~>bTe=1rr1u9bc_r;_Ea)NGY$+5k3kSC7|g*=8(XsAvRmnjLtS%l$xdVpjskD_Xy?jw zwhYXcXTr~>VLVgEt)rzipZZ_KF>`COK8rDo_1XgJ{kZ7{yPf=T+72`QOca36JCI#I zYUjv<+>sCno^%1bhb( z9Qa6GgpN2u_D#A524n{ePdY=$4j4P<&fqVE8TS}3M7E4blqc`KpQX$!d8S?(KCr)x z9OA$#I+a{8&Ov>2;@E2+><2b%K@3?cf2GQ|@o*sH3^UJT$i`Xwg-r7sWA|-mz6G|% zui-IXI9mVd8G2>sEo744QqeEtO9=fE03L{oJ+p8FPD=12y&x5G@jF1!7iA(|UfLQ< z)rTf(;chu$nHjj@FY*^8+@oGi<;iyF@aa>mgjibs%g_E;*>>g1GIr`v>A~G4?o*tB zFv@cL6)RSj1ABLs-FprMzJ<)rb@zjh{p<`=g&tX^M&}|r_Lfl&ETs;#I~JMd>Yr^> z%jJj*8S*?MFXtnkbdX7b8@8-3Pwd`P)~&mt?AW`nY@$4P=R4lTGUX%XuDicg4zW~! zoX)d*+atQ*@{FHlD_p8h=M4Q`K*!d>0teg7hj!Y{lfkQoLde z0Ao+t0}xvjjUy`qkmvlF+*Z<~96%B}Z@TbrcI}}&K+9Rm$MunoCaHto)^ZA&|Jnce zvskA6u6MmFR?y6&9e?|4uVX-BV_C}#@n^qqCpv+QSP3}6HWoCAZ3&B6uDzVj+$ok~ zAB?-s9qj0X2e*{$C4F}9-OUQMk#h9#aGAJ@Nxo%F^1(}N6=r7It(K=b%-D9BdSgC} zl|_7*7C6l@MCN&#=O5yE66geP7>_ah`62Q>ZYx%- zAe~0p_H&W}tYu~Kk|l9%pxZd^`S!QV%U<@f^5!?ax!lJRdi5qc)#|flE0epAJi46& zAP<)xdGGrfKpZTaH(yz9f7PqX%WipD`Ot?y94j&2`Hpw8?BA7B-R1V%ZjTid4?X-y zEbl+f6?c30?Jd9mp+6`OvCZ?xKJahK2S511n5?kev+l8t~tS-oVX6df}PM0t(BCZ#R79iflq=lbd1(gGuupN5&8;7xV|Huc~l z3QDb_5!K3|86M$PRnrP$r?vz{WsOGKf4OfbLdOzAbdBiNihO zL!UI2rTX1^S0o({&miU&)H7LHvUnz-|4;duw`?9_LZp|Frp_10^SMRT+!&4e0MB&O zE%Hi!wh=XSsvZW(NVF_l+8Uif)T<~E1>_e4pja(;qamyvooeSd!HjRxH$6k=fN@~e zJa68&VdE7w&R*1&CpB-+Wm!&YS*~5(zLbgR$&YcGBWigHgP++T%1L?k10!00vx0Se zBw2AcjbXx78CQ9VN27cE0vkyD$IT9=`SE#~3z&Ldp`RD9(T&atZ)b5mB*=m5tFGD- zX&(cF#6RjD;$fL%#}9Qdf+=_S4ISY7xtT^j;_C>I!P__j=j_yJLjx?ISte$hD(g%G z8um1m({O~n%G1-HD((y-^)Gd%oo!)_XS55TP`L_D|v-@!6^5IX<1BA!e@!28QVb90?MVgT3J2__*xa zS*^&Yjr4@^JMvwNG13ORX^Zy8szwKjT}f!W!GovfaqoOL9VeC&f`Ghkh(yMV*(hd< z=R1Q7jvn|Q0G~5yaRv^D!Mt zWN#Zy6qz3fPW2J)3d^c zyLCT*$}Hhb_ckJ#KM)0l!4azd=S;D0R!V+vd@Gh^?bw+o|q9tYj z;k}fvUFF)1Eam2BBUS2usH01h zxQ!Dr+sU@weaplQo%0zQ@~%)Bwj5H|#7|oFG;K%gAy=<>7Qj66w9DD2xKY9_D(=be z1Fn}grYOf)mQPEQs~C?^7qLCoc=Pc5ibb5m;|#5xMNh9^%yJaA)t9|{kCn&hII{F0 z&XYKN@DSw&SDc+6r+rUc;KjpU+4oCZ*1UY4J>d8A`x+hjU0lQWdIqzXa2?)cIeLUc z`j&DQ7l*MeVlV${u7;f8CYV9;%SjH8wQiN4Fr9A`sAcq+<t6W9B z+jyA2QM)Ls+ORkf$-to}cAg1{t=2DD#-g*-Exn8kddADzb&JcEZ7)V2N_lk0lcdX| ztoCCy5cQO0wbur&TD2<5Syu+CgZ8P^e^&==+tge5HKkkN>#r*s-(x$6x!k za?^`mRDS;Ff4=4WYV=7y$6+ zDlaE2?9`ujg%ahQ3T!^Jp0Rmd?YdWE^eqIV-QMAz>Dz`AUcCtTS!pl+#L-Ap&;S%Z zWD7us3!lsSXo{iBg;S1071{_H^+GyPY3isluo5RlWzHwF&7<&e-+?J&;Wa`c@D&|# z4uQ>)LNcfcVCTG>63xOc)sDoWjI`o+G_ap#X496gvOe8-XfGM7;rVBr1ZNcw%ba;hkQI zN)ipyXq0LPwkCcO*OAx~&hRz>;;nN8t{8OHG=TZhepaw>@k2P3JV8PMwexc%+e{G| z5bbxbWi$dvCma8U>6AyOy@ei&RH8u9qKHBcDl`u9ug9fK$}W8~6NH@Gu?G)~gzVLr zPLp^uZbnMlKDA$jrq1v;+X$Co>nr?mlK+}v0|HQW&<0|k1sD1ja&nm(1y?)1vKxX3 z)WT?@;fj0UP2q-oZ3HS?f6+nH9wGA4!C}iaaG-yp$vC&)EujD3f)-TiDN%oZE34)m zUyW-OdU`cJ&+uxaOFglYXr){tQ*~#V$`0=!BOfMW!`Cd>`hj=OUPTD>&kDsAA=I$= zMI#ni8(ldvop2F%twDnZ6f;Nar89qq9pNm20JK0$zbKQ*6uMiUwfUF0fwN5V>$#eU za>S_}A~EH6G#ue6K{77-w1Z?hkd0qEfi}v?cLMO!E^ircd2aHWuErHp^HT=NyrtaC zyUHVE6Oipk29>XfLCfPpSpAd77SLt3$b~kF>(C z#bHyn%pxDKEr?lO&+Vf#wK_sH&LLyb!$;V0S7hpx4L$d%W}4aQ}}1C3=RX z_?}B-qk5XNlgKzssK^xo;@^O2YW)@UG|n}R9CVOY%cvw6(=KfCQr*;J>Aro3SWY~G?z2*b4(23#!%x`*f{Oc! zBN2$Tad#j|uGMX4CL@0XXB#5UM8VJ5`|kNuG3YwMs*&^P*)(TJ4bPk_|NH;>Kgvzl za7g0t+49kk|3jP}f9;mFW%Ua7xYN!Sd9)*u>9J$SnXNtzZs;|)l(QiX#zsi z?Im{VaCGp8a4xBj@)EwhMJguk)OXUfhiwMlG42GLlSC85$MkY|(E+HKz!MgiN%Fc| zbR*x>rZ?Z&>h{1qQzFyHNs;sA+uy#Y-1L&0>9})JKPyIhI6(3USNxr)(|+ji3Haln zYz})hFSwo88Qe)a=-t%2j-f0k{u2zWj8C5COp>e1y0u#qa4;Pj&p3wAqtT;sYl9C?))jN%+FZT=!_Azu||5P>*aq!=2=bfVS+ZsFn$@& zS$=pJHIq6_M;LW8`X_VTjOd_!F4EpfKL@TniQY3L+6R^5mnCd*+DQjocn53z zo#FhRW1R8v`~U5~m)l&mNdyRCfnt6$~ZkZZ~n8#jc!jhE{R?88{kgdtw? z83sL8zj9R=aVB1VYm8#putcrW5oi4yun3diLbt=~*7==yrr zG4O0-9Q;ePhRGim0F6WaZsIaK_(i^i$2sDhI3i?&FGbzvBfo(FG+Z-c9eD9*dCqo@ zub`9eL81d>wiT&VV#cchc27@iD?wJ#QAjQ#-gY{wJd{KJH#!6^`K{?(X$3prHe5hR zr$x6yb-WD_fvQa6qXXcDSyK-P3+;@ncxTgSMDW50{ELK2{R>j599Y}(30o71NTrkx6{1>T;$!LZ6{SDtH!-ewH?+5PD_SZDnE1S1t$D0=V~#@lZe;VxCxg;^c8~v+vezNi_cLsKi#BKt|b6d5Z>46EFSd8oe$O z(ODttM+4Ui!gsZ+_ZhD?GGlIMzSY>Uhk~iHYU`-+548>d`Y>HAlWm|%NxNZVDQU#3 zLgqX4;UajdUUWj&)kU3d+N~nmF_`On;dhPyTp!c19`r_6GSaoi+cGEY5(0tzRllf% ziDS!uF5>6(eJQRouyWOO#?$n3V7Ol8>9YIi1pBtWfkzu(c4VfQC3AMTtIMUkp5p?h z7;mu*1hH`n>`5r-k%o3O(=XQm7-9AvNZ zAbaqcWu&{bn3+5e4jUX;6df5)RCcz(*(p`3%hiJ}lC}d3-uUCKzxH5H=EKdpHtX97 z+CXQxMt5o)+0dc#z%@H*?mg~eraYQcgn@ue(rNJ|XWB;5{xI%fhlU-RXmfzief%?Y z+y)2|2mCSk(8oDKE|NUkT-hsZm2EWa<;{3F0YZms{(L)ab~M?O%F^vPw}|gS+DbN+ zCoD_&i$K!O7{UW?fl9x&>2?WbV^Tkpo=$#;TgZoW0f8sEM;?TRxYHltS!m%va)uKw z-ePQU%1AW=8di8-=9@U=kPn@GTDEkSo9?q7J~P4~$slJL43uB^@&5+g7t0_2*(b~U z-uE`HoBLXM-w*#p`IC=)I1a6IaMZSHuY)LbTs>FnJn7)c5az{RWb2B^DazW|uE(TS z3|5gAGqi6f*#qvLba`{;vq#yJUmOgZ&r zuD)(HliBm=_;RBC=t%|xDBs}NCH9jX4Cj^46X@48*YVNxrR~fFgoznT&|OiG^0Mq# z>IhV+z^ib!%1Idz_A>LXJ8L%Le)0M6Itu;?R>HardLH`N3(bIM0Ej3+k0CDyl;Fww zXdyHA{cKY_eRMeV$u6QCnC1(Z$^FnDeWZN*>E9}E;B>8hl%7y& z>UZ<`FZ!xHNHp_N^Nz@M^4jDt;W{~t_-B00R>sglWM|*KLeBC$`b=nnGvyk$H638E z%M}maw6S~dp0fSk2gpK`YSi5#D zUBk(sEuZoh?Hu@b#h7g@_x(FKV4brFI{mbN900JBZ<*oGe6QZC@oCzr7ik`j=@%+M znCjjxcl6J2jhGu;8BQ8=q}=%b^Iw;@V;}rvMB*6_GlHY<6h>4K3`vqlE~^+ndAgk0f1pf^43|F8 zc2m&&-_*ScoL)zD;9F8l>ekxY_g$73+1SP#-ms0q@dDUD5&}bj00|)ryxEc;lVq|@ zhRn-4nIw~BV3JIROhQ| zw1yIgLC!?g&TJG^(*>>3P&Na2g(Z{$Sz!@x2u0KQgxxSomNh9X$Q9YFB-$AtKt9q4 zAA*z>gOz19wJ-)tt7G#%om=AR1QaUqHnJ8n7cugP&WDW#m9SxLaH6xNa5oW{F8%zp zv5`LQwJ=}}6NTPNUtjnZ0^d$bkd|SyFob^-hhenVLP8YS?fi+_hd8x20sLqP%#iwZ zm?m6?Z@X9g(w-|O7BWzgu8dQ>HI^DzJG{0Ab;~ga?sRa7%mG7ID0oX>3s_6aQaI|B zQ3XhViLo+0JdMAhp?L{%T7!SemwX=zAzeddZ>az9uZXJBfoGs=A#D@Vasnoj8V<-u z#FyzCin|?lsQWAbWyPK%ZXQ`U8~!&WDVLE>zqQo2fSAfZy{Zhg?Wd-zlQ)4NaA-Rn zY{Z;#;4S`WFryO5(6KU&wUQQCfD5WKc%-YAPbcWI0U<`xKFZD^@XDrXu_LMf)@@tM zC6`?Q7C5o+uMW#JBZ?;rw-`U+V0`x64eMM*RrTW~GR$!8)81mB)g#akim? z2ZVF5C~dB)N|zOFhRrgq3(-bdlveHSs4KoqOT;CO!uW9-qhB?Vb^t4_l^6OaTmtLf z_G`yg@x0Jm>6DhFM?7t4^Gv)k7y%-_@s51KPrf(^aIoxPvTDnZomaxOQJwNN#4CK^ zCjlZ%WC)H;+H2a94_U7%Gp;-;yTU1(uFwc;n_>rR4;q2h415yhZb#UTscxI&D%d5G zic>noEBz9n{Dz5_Z58q1Ug3l9v{%->ymF9|A-?BR)`BUX5g%Xn0leZ$oj`W*9n^K5 zILK~4R`giO^VSF_ail{&0}c|?O!;yE$0ETf2Hmj|2`{o7$~fSFiM-;iy94{0r}Ahd z1K;Cl{vUy97rjioG}q^~#N0ADxq)tetYdeXzH>sW86pbhbAykpV~F=H5jyZRmq z{p1ULmNVm_)rGWUF4BQqy;kG7k?JJ;8ekWSE4pg0cU2#eCxm6hL}4RAN0_iE91ZB> z9oa!%?AyN=4fwk`HrrihaYW#$XIGa^>vxw6FF338cnk)u_@jF!acpK>Ie4@n< z9|L)JJE+w4?OZ`OckbM54}h^<_%;J`ZT;>h5QZ+LyVp7Z;^^V`1_ z6G`8`|Gx6*%E!u0H{OIs{-u!@*58(=ZQHk(Z5&Iw`ZbpaeNS?>|4X0$hjPv9Ul;9B ztuLYhfe*QZMmebMt(?g^Mpo9kB6tRTHCmPNkuD0uv)uid@Uqk$Rvx7bIUk~7x^)}bk2;TI7EtdI&p@E56XDX0}Q{)O*q%D84QkF(0X>T$i%V2_~ zd|+=(!q@z*t}oZSow??`vJ+d=MX#5yAfOQelhJ(Fj)ZyW1d}U3(a=&>L+KLlEZZrI zvcLhd${lSiUw7U0Wim>k?!W(j8ay;RH|09Zx(%6eWxOFP5~I;A=*UmM1r0a7^$XK@ z)X!mW(`&diZJX(dG=nE#Bt$#E${Wi|d`B>$q#<#nOsBnJRYak?Ve+RvzirU7g9DC^ z07-{I!6iB)k%k5){WG3`YTT=TzB7(Cl#r)4nTGUBdkx#f4-vQo8HtZUmV-7sSLC%@ zcekux&p>Pf8queeF#wrXc~vJy#ID;*H_~FPP0TGMnOE{&erRgCZ6`x{8*auwi2>y} z2CT=~2CSc9YXal?~`n2Kg?>Bomf{ZJ-e*k!Izy~`v$Q!mC@cHBRuc6k1f|kQp;84kMRl{ zlgp$d_(h@d>NC$gJ0Kinu-7F_usicSIpD@cRux$p9UMd{AvAZf^Kc~Lm=lOJ#43j? z9bxGG*oN}6lkO27c^I8edVNa?}E2K9)2qS5S*jDbCx-A6L+9Ap(b%ZfT- z0Jg2Nj>(94;>JhhYs;;}VjRH82YDRu25Bk``4GSKX+0~>%7vhlhkOmUz}4_kwAFyG z)vn?unD{;09+R8;(}xTG8^-v32fm<`^x@)l0Vqox;J)>VQ>KYuc}+MnVnjs_sj+3%KT~LkmJE}_tVd@rTs)X zV>V~cDYM*CNBs1mS%B-}iaPUdfMWpTP#PS^R!kf+*?07CVGPd%*rDVO`0$}-Ry(H*P@c*OleQ#MZABDwia#3Ml-{Jk`>v#Pl=df3nyT0-D z^2lTNl{dZl#`3yruPW2XKcLE8U%!{_|3}N_E$hqWmtDlpoQuno8YoLugOz>S6`iq?_$RWb;fzGdQ}YIAE58?n#*2O&Rek}sx2oBZhP~s=vTNg z`Yv~T`OC4h@G8Q)2=Obw{O`-}{oe1DH{Nzz`T3vw`LcNNlJd2$eXZPa=a z3-E0+51g8snR({vcvLE$338>o`dK-*8VT_b)*@g>!_KIfj3XKvzM=`C@|Ly~k$g5W z+Qy`bfDH}eZJd3z>{yH;aMp0u-}uALM~3KxbKtH}+eq4g(3go$m=&AG5H{Y~@d6fy ztb#K=0pz2J*H>f3ra0eGtHj{7oMcor+I_sP2Z~bV)wP*LP^6Cp-U6w3aQl5Km6{|XQ zTUuhL%L=S%9la`Ffr*KkK zaiv?^|E1cJqG4Dv`B7)vS#b-bTlIhQcYcS7?Sth%{@SmVg-e&xMm2I_9iH47Lho?e zPe)tjoq65~U(*+LAMphGR^HH|qobssgA&8JdQ#t^v6vM@&wd|a`|@b6C2|r=zwB zfg(ftcb2cCT+cRR*5vZbANe!3ydNz;{{DZ#S^N2>plsfDsBC1X!)ONGU91R?B%f4h z>Xln+WOs|b`R0O>H#xZ_J^NV_&9A9bvyO5wodf(35Fsc}!DVEwi$$!-GpDgK|K0K% zAKO(v@Qz!{g=fvA4liXN$2g|Xm|d1ESrjs9{wtT`IDYD+?#$^^4xex_} zBbcP%Z}LR;8nA;$L3LQ=1c*m&Uw{4eoS&YBqBiTW5#`6;U&@!h{PprTpZzjtwK-2u zXSEMyn@_SjzhLe~ECN#JaQ=SM#A)TW+umGyzu`55C(87hy~wkdLkuv1-OJtQlQ|>K z1O*c|YuB!VACt&i%aEMPJoor1NsYd+G8TCd0|aOh2B$E}4ZMxXJN+@rVN5WFJ)DL- zgsR~?#B~VF={|;pQCzA+3s{E^j6pa~0A`s_W=pZQF=Zs)b3A>S?f zSB3WcO9J0YR_fi3{~C@~cu&0bv^xi+c`|wZfe-w692MBGVM9zbdko;VTi%4;g$3nf zANv^cdmzfb3jLh8P^O*i$~qzWBd<@xs)lP(3rD^;4goCZ3>_H67oHv51*w0}kGF;G zMOj|Kfjvaa0b9W;xMMe?YyymrodY!BP&C(K?@rY>DlCa*ZB90Y#Hj?LvD z8Z*~Ex2|m7u!#zX^G$?5GHD`P@CVCW?ya9mrl6*QtvB3PPn4d~i#Q2?oEc|35pI28 zN`V!68ZNieP%%;`(!N-^5(th`UoevmU1X*OvMHP42WU-&)|kn*QMO_AOo^Qn8+kh! z&e+FllF0{e%yvbNnVp&Ot(j?&$rnk8j1|V8Cg1fdVbbT+r;%Y~q=d(3#${R(l{Vdc zi&dcNr;TQs1}i#eG&=g57DpGtnp z`0)I!R0gf_h*Y&n#jV1$9UHeqn)w@H+Ypwgmtrb^Bd!iyHSVF<5}-3ocIfGBSVrk! znBX|eOdYGy%}$DPs=WEVV#T>-;lhP9z&p$1k3UYMI5&(3^Q=@fqHf&=nu+D%ImVQ|Zm9pD@|`t26Hgad4dNp9+wooC;; zfme(frWIR9NW%?vHy9y;mcS9viNDsxy2J7e+IR)n_wlH-C7PtgiC9;X9E7=2|E9OT zwfr#KARpnpqQJXwv&V=rFDbBfqo<-{n*OP7R*aRd++V`fEo^x%1p{ z@I+c@Ya&gJOd2Ne*1#Qa;|&Tr(ANQFqy!>`@fU-$j@%&X}8*$_=81R%a&m9el?!xFtlRJbZ-2=1+R@Qg#wY`f7b#MVRBdz!7d(?D|8R=Q1VBtf93ud^9at6q znS!`+2;6axH*~7hc-L<3O7H3|11Rx30i&{vQlDri4kxN3FXW?i`mZ1Ov}eQLSi@1b zgwenDi83F+Kv<#kJBG1|KSD*w_>S0&v-yR06So+oO(y7H`Iau^12ZO`-}euI#9>E} zF!HLp`)%4r(7_x$K{=wl?We!FY~Gae-){f+<-rH;DgWl*{Cs)ekG`k$pp5Oi4?kWW zes*2iy8kdoIG7w^MS3LX!jH1WT}|ND)iI%nJUQuOeh;89G16P>Lg|*Kpk9jg^+7s_ zKXoZEvBK7O`?a%Y&o19y`D{6H_%F-v|HjXk-8=V}&wlC7vSz~?VAVd3oRSdco>B`v zvN@K;twVv- zLRsM%W%s`RxLR#CZPlfhTwLzD`+kl+9A?|~?D7Q$lk;XzDX%(v36lsZakA0lJ}Xw7 z$NlIxF$vdAnI?T`-R?)1#U!rCbM=13x#yJSXD%U-tFAS5o;Q^KzGgbwc~mot|yhZyvl zFs8CD+_Z6XOblFp`Q_!ef9JQ+Yciqy+OPk5*~OOsKl_vaTFymt{ylf!6AJWH&^l$> zl$fkE{npuIZ5Jso6Ts&YL)#%&_CNEv&y_2|`Afg_OJ(um#i4v})vD)6oBG>&LUCf# zTn2A4{mC@z&1x!N5U6l67oE(hxh|g~FR(;t9)`)EF5wzsU#`b1IIx#Q2#(gMO?)&0 zFgqF@AVRSQ70l=!t`eC%vvf`CEn_%Ozl$yOcRctIg>GWmuy#G=y`R~jDdjj@YbH#a zhM;UL2ez*-M`uhc6Z#I(sbTQWRWQ!L9(S8la82Q(F(p1%3`RK0G<1uz5waAxCQCr(w{d5rhN}blREl8-%#NV$rd6dY!be9q zINJ!aI2seQ`59?RoIx5mjL-it4ZY1*%Z(5%rwr$(HhpT~>gGG$e6~aC{vwQlOo9zI zf2J|F>zPLQmyCQ7hy=+n+6*Txq7VM+2JXPu!bxT5%8J`2-jhT7r+k zWXa}FS~J&@%t%g?AY7^~a<_g2WMBq)1jw-8=QCtvcv#RHLmDH_$cLn*146izwFIp= zQ=T$EZ0Kgrm`P`F7H1guunlcbOi(&N4AbOW&G#52Q5i+&-MAvD$~@3ML|#q!1()

0wOtW zxvltwvYt*pW_hl8(1|bYLK{yz{lO;OPMdyV4S;F+H?()s9RLllg-_TV#74Z-(Nky5 zVnTdJbY33$?sp@I^|y=oJ^MejD-4V$ zuyW!=v7O+J=yaIHak{Z|0*}(^_T1_*lvTz3_U5B;8c&rg@y39s;ge}-B3G7!RSn~$ zE#w4$gNJkD*GX@uy?To^;mv;rK%A@X9XEnO0_Tt!5gkK;-2{#bN|!68Ui0Rab^#2$ z3d(}NjFK%YgVgcWgg%6z$F%5A{{)y^ZKeZ4cLphY=lg28Rfo}rKKH*b}zg?u^0K$`puJV9voH!7Wg0F+PT#mJG+zYt%d(mnm^y9tpHhKm(>;%V>-9`W+6 zTT7k=RmN*wK$^@4Cp!biaN?+VV7vVz=TIWwfHh6}2MvBUbcRS{SCQbj(F0}e?ycn= zZ+?Hd_10_4O|QSEeBrZyU*7PV50o-xRJrMz^U4WsOxTP5f+O5-KXMdBhATCu#m_g}oNd>Reoci(p}A?@TkQFRh!(uZP_K}D(K*$zKv&J@m;KT#fecw5=B z@i`_1w#91s1Qd&1|N1wSi!Qs8Rn<44ux?!W+!w!&;yz{vMvkGpdYlG5R;-SC_1$Rt z*sHf}FTe7U_mpd|ygbhOuX^G;L^}ZfRa`5#xlG~6*I8$uTP|VS^+!JZ<6LpqTR!=z zFEE)fQ1;R9cjkemzsM6OB;CpI2v?hJ<2t*a{^_4#klt7Bz3-v2@~QR65=Uw&oAS^) zZ_)gj<&%H?*X8QV&M&j4PeGQCmqiN~l(Ww{CsyWIRK~b4^g}0Y$4b|Y^vu7vw*zb=p(HFDKk`J&u28%qQlZ8BZN=}id9_^6Lmg~0c zM1V$+46C*I3@<)gAo^?cul8{0cqj!e1Rd@}tbo+|vlEy05H4R$0N+_=QpRfJL92q; zKt{ZL1zkA1>(8B5Pd@Qr`Q!ikaVo%ZT#twcdK6qa_YV6ne(6hP)w9o*1@jlgb#%Mg z`SUpU&%4$BoU_g>AN{xgww%kP%bRY#v3%qsAE6!_h@FG>Pd07Z6nah`eDJ|IlJPbs zti29TlK%Ry{zp0Qyz@9paaXi;+c`gfkR56pHm)!0HmqlY;LMoJK5*awGBhT30IXiU zx?Fk5W#vO3`cRq9M2+o^1OGLv*F@W7TjIE9loLASvtzp2W}0f8BJNgw)9|m;z01|* zsAG8#HxQm-PvbWn_Mh?n@(=8x*F=WVlC?Mu6oV#&!x_Ut7-s>pr9ZAc?w!$Mb6OWeJpqj!! zdpz-}b=1~LwvAv$%~>_i+>ZdS11=>AM3V*s1%@H6o$=_=rcHZ(w{II39r|?RZ4KAU}G=%7<_M>MXGN>JKOX z)6#l|Lq5{8!=Z7Gz^6EegR-EBN+$@2N4Vu`MA zDIP0E@dn(&nU01E6XCH1?J}8wzH;S|4kI0TgXnMBjX@pq z=m5*Dx6`Lj3;(ri*NG+0#KjS!rsHBNBkzW1pb-a=ysI%ix@Ux~c*DuWMw3pzPa47m zf2m!;Z~9%?%)v}!fnm2pgL#^859>pJHanavCA#7 z8vzM&K#h_?66ke$a#ESms&X{TsYfStVCawx2q@EEKN+OaV4b9oBY%unok1gD-k=AU zIp04Dy#R9kD0CgO{GWus&^p0A(hPb|avs{0*Pk5le17sZN@DZ@+$!AzZYO2jAzFiJA&4zWDKo9Z~czyTN_n z@Sbw$!7re^`7P!6QSzOY!uP)WZLCIL7T0$@vhwLNcoba>$Ji&z6?Z2Y0I3wN3#EH1 zdb9uNZiwUVqH&jm{4u}nLqbH>Kh`li!DDEYJJF|LB1atu$2dT*TzL(ii&d7T*I#j7 zS#awW45U_-VZ0BFY`RgY+qt3y1H1C^-_i=;3w(XnBO`N~}!CT){ z_U$=X?)w%K0LM^J$;6aAM@Jv|=1l|#nNT}kK7Y@*%2iihS>E%Wcb5y!e|5PR_`mtg zm&y_RySSm^ILFBL?b%oQn0Wcr-+i7l{+z2m$gy3v+K*vp?^Rb_M!QJ*l`{B6spLq) zMCv9c)A)G<%nnwTEfd`=6z)4nSs`D%UwwcHEhiv7nxfKA%L!P*C^MZOQGF=?CPKe> z`$%iNMd@dD?q+MqKha~ zzWCxlV+comy|i3>@g?Ogx4o_Wmp}L;R^~UAx4rcTxl(j8lTM>p$$u)YuUoQo zNt}hh>#lF0YvHDH-F4R@Ppi02a$$M=vByw=cvmR@_4+)w(2pjsx9!-TdQqUuV<%q0 zr@pn1{=1KspZ=+zF7xNjV{*z}EdAy7+izzF!G_p|@6Ll`$Ea~#bc3fcIU7tS$D?r| z@ut7BAUK!okcmM;1eu@ zF#brn@r}2YOV~a!l9l}Ny;IR{xw?!*TkGVpJ>|f=0~AYI$gQW-P}9sc+=;l-DJSoG7~_@b#z->8I0 za}KuTeTvSYX(i$ah8rIdlizkyq%F3K<6yfZXDX}|X`;HYl#f-|2a(J!q-)2kpcg@~4kKOoO9VjOjS^ zNlYz=NV91-XyY6mf9-)XIad9J2`?WF9^I0aSQI`#^ovfB6$_1f*!8M(Hi1ObVUmAs zhZcO>X^2hAO>3=yhIlp~5o3+6Ax*DpHSd!Cbc;A~kd}-ni93QBGQM8C%kA8l*XS+mry@BF!Cx z@1&(tlvssHuH?(lz-K&!jRvG~I{WqZ?zgP2U8bwpbhYPy3j5-ty#xXsF#c!J8{1Mc!zH!~!F%yRgO(T@S?@nbjaZ0BNHM{o?*n5p{!@{^aqxph4N8n*zGLa={JH1!ME=; zwLG;xlYUS&V-jG225HKJ@cgKIY{TpT=~we`C}zA!sv;3^ttfL~<7cL!dNlM!x(s7_ z(k=2sd*i07X$XjRVj`Z*2ag{dr!zCQoW(Hp8C=G#>0G;=E!3Qg3vjVL3VUiPI!9{=jj;-_rp(1 z|9H0LcC$jMmT-r*@+2nWp(!RS2$)KHrPCjMjcB`)PmzwGHd8Z(G-;lsXA51rx@>_$9vi2fU$vwr$e?E64z zn}be?aA3{Ufn^JLP1Fv-10K*DI~JiyyCG`+$V0zc#)3x%>ngj#Xn__uPy9?qkjCgk zq-W$w7yS23G`W>>MH>6*gDG<}ShaOfs_urE^n?bZRQmjPg2I(%cVD=Y>uRw2?Hv5# z4ZoZ)bL%|yDCx5t1tldD9KADd)fHeEQ=jS!CMGb!`jFg)8QlU;OtUjq}BS z_33{q#}6Eit?Hi3A5CPg0$bMxZfCEQX}N-f$2J^nQcDxFb&PqQvJvzuKM~S&I^9Dc z!Ygwlk(&(%2Fguuxvjk6;w3JSha53}LgV{pu9M~pMFz)CBP}CN9x9h#dRckn z&DWRvzx9o>WzFVtlokIY`*%crv1iv_RyAjo`|rK4%$Yl{-1b91R3_1vKE~?&vBPYu zhc-8F965we56dqzLJzLrT7KcZZ!YuaPA{ugK2Y}W*}-b)(`EJQXOX2b4F1S{`r@0m z?9 znUp!spl%jB4<;kiN6J0-+{0wzNhU(pup?k6=_pKiY+(EUE+$^Ma?`O36J#fm5!=q} zCn|jKoOCFQG4W@)jBL#ONEvUJ^QgBB)|mA716v3?i6zaJxt8&}DF|9MimzqFSA;cK zzyOhs;gj_%P96_3j>a?aG{{Md!^K#Lv zFJ>p{&9x}~eWu*;+44j+2P^DWhlX;{g7eaHj#aTQa(-mPPp((6pf2794ybs3oN4@=wkAMCF~Fkm;*l}&!|WF zXnwrDPxCSk>`$e@Dk~CAVnSJn$!-|tJB$g&n5a=OyPwAM7!~EHv7Do4@O-knt4v_v zK8k_+ndiN#Tz1{nsKKP+cfd_0)5W&92`Jv1!S?)3C{CC(9<7FCEYe2fNHu2TLsZfd z|HLCNr7H_W#107GK~mDAtH!U))}ij+^DGW$c&1L9nrAZ5&hH(G6VM(SGhaqraWwI@ z;{~NmWr@`l|L6tZg;@ZwBAJtg_YMG?Dk`iCdN1(*6EMK(fKngsJ{k*zqT@C?bHbHhkq*ymju3s==3z!#$dB!X!4H zIGJ~8EKAzzcb5Bzr*Uulw2%Ou*cv3QSGYzxGKMI_lu=ij4C3I*n?G#SVo*;5ZTe@- zoEaUFEt@yfX;Lu}g96|!e7Zu#J`3g^|&-Cy}l04AU6hs|nS`s+l z*n$2U9_>i~*os2a-0~3~U&@E$4})aWXwxi9>vuK0m{?0m@ebHuhn! zz)28!nIVnLuWG72Y1P#*#^(xoHO8x3VhXatYY3_e+`rfeUx=CDdbVF~Q^vKPFaa8`%mz1}F63zo}m7c>E=K!NIugwypymF{F690ig&Qddaa93T%$0QE^$LSZ4uyZ^NsuVlZmg}$lVOGi9Cf!qdr}UO}&pcha4s(yt5w@sGF@xD7@P9lV z&Ov4_Vl|jW5jqG=T#P9Pc*o=mop+Bx_A$U#8@pTfg{_l1P!=q1nmN*B0&wHkl!koE zU-=~?ssScL`)q86#YA-jH#{TmV9So0^_=`4JrbQj;8FL15n3V#xmn306cbUIKAx@Q zd(n2Sys0NZ)W(`Wo(yo0a4p(s?t>r8u25HMkJ67jd2$qWBYDi~eYcY*^sBtre1Jab zx?TIq&)@h1<%T!BDh8mQ8(+438G{+_k|&CpGsc&<{m2iNy+^yspZ?XIF-Shn0P83# zfn!lhM+WAka@18$+t^=of&{xGTGA@Vf(^kx`*rfmiJ|0&byL(qx~Er}$Ds5NfB$#O zmN(v1E;;ACGM>TqXf(w;VWGU$`oQh-?h={6EmM;@^W4ofa$|r|yZx+LGgv^|6$71a z`rLiT`pS44sx`adsX{}a6B_zBAAiP_v1RM_oybdfS+aCl z*|_eR=#Nj}eDw+XpvNdnUF4tFKyFyK7Ug+6<0`!I^z&6(cg=-tpEi%1d{QdhvVHbh zXO|y*+ihj%_Fd(%?><^S^XX5QhrYXtn;K?t4PQ6Mczan?W08=FmjRScdJUWPzvXBG z3f)-5Wy|%{vhuM<%bovwb=k8IZTB1_nA|%%R(TH{94xzb?qI@TDQ(Ia;@QiDsJj;W z8Gtc~!9LEd3`be1v!I{fm)Uoe-rWv1DX zgKgdxj%p;-3>RmU>ZU3p-TYL_PC ztHKb`Ho^gtCcccO6(-_rB9;nqG$yuw2TtUI3N~laTVzIbk?tl)BnP{2op=Nkq}8Bk zmj^`a57Gi@bu;?xdhj-W{}E1qVS+{+B|C77{ZtcR5wm{s_!ZUSuE%c>$BOBSZGwNI<77n;ySA;}t&ASsk0S zMjg*YN*F2%bD?q8-SfW$b63&TgU=Ui;opK;Yg!p+b}(J%;d54q>af8 zI%A$!bjzFHp;X3(n8wl$LpER;wxvw5p-Fs32W0Rkc!(8meodK&`hcT;BK}eU06+jq zL_t(ev>}t?q&lb#+G8MtEjl9M(m+I7+Hm2;!}J(e#VZBT0yZ6s795tKiMNAuD=hgC zdMR+TevW}UPymNOc)xAlN;`uA(q8kzc&c4Lzcm$ie8jg8{gS>&XalQTcKYB;8b<@wiqmgtiB;eRR+^GyE$Aepe!jq4@@y|UOk%^miiv*Ka7aRQ`ipt zMCg|ky8`S0!)xQb_Rj6du{y$-Cge`J1?G56#&h4bJrmQ~4C*6-MAnXi@8S6paNozn zcFPGcx^dB=k2CAgyGMW|0X%ojWT;XUA-LX;N?&7}j zZU!}@9jKWg(l`+DlXn2knKP>lFo2pghU+k)(N!mP8o4N7e<%i}Bsx$-q-Cxh3c?1JbwPkBfGGsxF& zeGAPnDi=$sr?8uj=%W!IHV_J9U4S)w>FbGuJP5upxEzm;sY#Ot%V$4-ds+49%5v^m z%eleeINRY-1jp*MN39Ivjsep#j>##{KD#4f*N!d7ADPN;23pHEG4V@;vBTgfJ33~e zi{;F-&M5oYxiOl_4s}PIU@&Jp5_i^9t}WY>SY+G7cKAR3lRqm9XZOOBJ|;89lLu3{ zC13+QWip0|1aAg#;$#%ZNXD>bo{Izc=B5D#WA3)dsSd~?zuax{M}PQ7rr}kb$RmXwdD@9_1}5dcPN*WDTm`x3V4W}G-Eky%?^eBgJmzBc&1IC1r1|DIo{F32NClg{OQ9(+Z2@O9XdF(Z0+3~_pzHdu6ldS!TP~=L}T8V z8Ic9ZiN*nZv{!saHo?C%)FKgGVEg$;H50zKF`h4o9ekNz$7J7ZAqF8U-`0lcB(VX(ogAZ`+;+nFAE%*J$ z7^I)26^5GAEn8~;qWyz8y zD4Ts0IaaQbK*Bn>SMfR@^}n4Tq%-@Q$uAdD#4kTxG_A5QhH>pk`CR?~f0DQR7@RD)jRVhPsRG4-0US1V4sKg)!#;$w# zGToM=k^^>flPqERHo#4Qbf+_vt8UxZ4?V#Bn;<@54D;osnn?`ROhOJ9D8mws!Lf9dAaNdt}e;?KHI+{7tf8_l}9UK`q^C26SP zq_g6QH)UEsP3^#mzX1#P&PRqGn&;_{8-IZxpr)zAD?Ty)Sqz@XR8 zJ$*jz$95H;!JnNsXmb)L2HVgU@)u0zgFK4?8}e!1=x16JCS|xL!p^d|00lRb3-nuD zp&m)+&xMaM@S_i2xoz0E9AsGgj-r5c4LTrVdp(1wey&#=#j5&fRx(erC3)pWt_Xhi zX$EnVpmG$ev0N?8b#-&*E-9;bqHUTL>ZNmLkao7OyX95-z^p<)2d55%txFEj0d)oQ z5Jx9DrjLKq*$3X-38{p3xzRFo95T<8VbiBiFsZ2rvaZrCym&|bkRQPh!R^7=2k9nX z#wah8Q}r7G95_8Yo}FkGj&OG(Mn%f|_U(`US(nEp7{o@MfS-B@a>oswepZS}N>g7F zhC%6+Nxh|q<4PyVYTXXC{i)W^j%2KCYJgO|-9{Q7*msVg{$( zWzVkN(OKWSe_u=@^batZK-}I|;VSibc2)GTN*Bi*g>dVl4?oA$s zVa1+-{)CC+V+9?QtcDkq*m2C3$)tO~^GMmfYgd_#a&6|g%8bd~<*Lii=ENdLaM3mJ z@T1Q#h9CfReCNqEtOoC8!sbL-Fmrra$~AcknB~>8_Fe(HVZ+1Nr^AEE(A8ItjXh3W zQ=n~Pj3K0D`~)uLro{cyMymrff7~%cN zKOL}(JL?Cnz~L6~*b~+mpn>ne5^rpNh>KU^(V`WXz}xXHc)$}c-eKjD3xEl4-%J=v zq}4#+G3C;lbzP3H#P7J{1QW8#D@8KuCZ_`i7|73HEBJEUoeo@+}zwGx+M2@`T?hbBEc;`Fc3GNS- zAAQ%mpf@LT)~;O}^6wdaC;fCcZOV-GMl##v&ZhNC!A+=WW;#zjf1HNP>OJnRepTdN@J9x%-d*r2@$n{XLEDNB271JbHsG}CF}lcZLZ5w!)@0vxMa9kc{)Q8aPJ z8+;0Q{BVb*QK*STO50EH=@Qk7@i#`CVWeMawu7UC54@UJe&~)dNbpI37j0e&?2ASk zfSH7>RCQ=lfXz4~H9CJ!W44+Rr-UGa;8R4DI5VG(p^-M6TfD3>f#@{Ys&B*<%*4g8 z$Q{Y- ze1w0I;wQkHg4P)4YL!F z-dCT4c^e`dWIB`9nIMk%i7)Gd9EgNRM%d7lG8ObTG*-G})slLn)&wyLCf>MFQ&SeIMJX|EHWhKZaY zD&4C|+S+^%_rRUh`E9t)FaguhI>bE_72ZDDei3ua9dr%yglGp#TMehIwB)-T`ZTsS zhU!_<<#*x$EBw-4{X)b8Ak$dGw%?UcO=24l!@KQLT%N`C$|#moXwO-_Kg60bZNEE7 z)b-#hK3xRz#8t%>f|OO;nHCY%^W}Y82C9h;8hw(k?kocy7Z}B$wu{c_aaJ4-PC0^t z-y_lCgfN0N`C&%*F3PkT@B7(aegduh zeTViDIOB6dq>sMONVc9%m^rJ=K67DNbm>K9`=0&fZWIttVUXX$gh~J5W91-QrN_;k zTdw_q+scdu^UIz?+%dgrbs41pG-dX*vi-sP%87kP%25WX$DKGJUtCpEtMtjylQ`?j z*6V3wOP?cq2c9I(-9Ax{NePx@LnO}h;TLquk4%q~a`r)D01vOD)2ts1$h=M7B?{e$ z#6F#)3+Q=bCu#ro4!r3o&p?itnBeSY#2u?Z6M zM$tDMJ7z2^wwwoM@OFqRmisxIdlcPFYD{0mmRzfe{d@ODd{ejzZRWJe^hu8~aNk~@ zVE{2}Y;Ba{vJI+FBDs4Mo=e(G|NKVM`3 zGPyyo&t%Rcl496WTeY~6YQd2CiS$qCyXYdq5wlXb+iW$X6x z)?2PcHusb-eE#o3*TFm{MVxFt!fL8I9?m;&1zC5zJjE4bdk*vme@1a!#EA+x#>7Hl zkT#xy-qP}4{?mWpuJQTo;&mmIJLl27|M(NnmCf4^#7h5JXD*2awSxzbl=r{$2F`pV zW9Y@$v2{y%5{>#ZQOKq?{yxI^(}sw)-${X-1WQ_tPmp*Aj>MbvfGTM7ML&VMFeV{l z?Bh4EUGl^F&ALK8J#5XVu9MCY$mW(!TjD5-3SE_%X;UYcjZ8lN{(t_RvTp6_vSjh1 z@&sk-2v-YkW7o*TpS-VJeEwDCQ+=N*Z+`QwtkT~U*WZ2S)1NK>nPVn*-f?HN(Vofg zWdhFKhfXf3AaC2&t;CNuHjdvUACnbM6g$A5!*!59_QChDz5fApHvB|f59y-D6I}DV zdd=!MK5)T>7epWzYb##^m-!;EFv%;J#dpm&+X{`}(dRHru-mt??NhscJ?2-##jRMu zbHaklV}+5A8BO3z2dzUK8^7m&y@CV#rb9r@Wy3AO&T5$0*ouz;SP`3;euThTzT?a| zvxdYq6r;*QG;nTZC4R~B^U64Bv_D;PU~iklY%yutOGDs!RV&HZ z#sQrQ23}35$UDM?gO28BPH{C&QnD`N= z^ja`&P=&RFVJ9{e%7DZb6$_<*0Yli@390YI7i39Y#MPpQI9l|OkVs2Fw3@7N zuP~-SY=#KWpdnrJTl@2x7QT$}dEvfKkEG0}rjwoyxAbfvYK7munf`p7{OaGb&MESifjmHlmk)-K&Vg|Ysq!s@#T3R7GElIcRF-OC^ z5Gk36EN=l1Fu@FInXj~Dz9!i=uz|gXjYx#B?&O0<=Taw28#4!$;7tcJF*F&Hogob%{glx@ya9VHa+|We??7v!ugAI;crh`yL_TH zOjw;eB6Nbei#lAmF-u{BT1PA zR{3<`&)abB7VvG6kU!C05>}p!W0iBl#3^Oo{JEtM1!>b3FJsH|IPkG`e$v=7>zw6f zzURZ)em`>FY|d4WLsR&HvU=3hX^%Hf3UmA#d*iN1)$&S!Fu_OaBlR$_d|rB4J^pvMUR5sr)$__2bTA#|{I_!B zx!zE6$Kc`!_r$w%)Bf0f4?JAft>1`#rm<*82PJVhm>*;Se$sxLJ4Ps`Guhrdz&ZMZ z2M(2~Xi)EC6?^-^J>VG~gW!U0g9&WqpFU+Fd_P{c@7PxM>{uJeEho~~>|t`_827;| zH#29>;I}L^ryoSN?|$gXI8I@|@Bn%aMxa!TsaNV|`QQQ+<;C(LajwFL2+_$W-|UmA zRBM2v05Qo%Yv8U60beZ#@9tyI2k1SKjx&_m>r%H~!Qo{|CzSzJgZ!BV0@O z>hhZ(`>k@}1+OmOeeB7yaN(G;Wye$H5QB3#9}@*iy!o%}o(!30>pDAJ4kCl^eEScU z>AgMW&p-Z$W!LU)oMYcu`e>ql?xVk2=AzYn3p>cxtlb1}=tDEf*N2{nT517*Ij=-Tf7%BU?0a_=ns_TXPsHbBL{=T zJ-TOdS+aCRnK^q-nKWfadEkL>F<7O}iovUTORU>vq_WvClvlJFW+OfttV2xeJL=C2 zZ>B^zAS0ZaCK8`1@taqNOo#fA72B&%k;jTk^M*U-{)5?tdkf3m-@J#3#)IXSTW+R4?uo1J9((Mun9w(&o>`Yi-IO=$1r=zz@aoSx;a~mC zzl;_A3(q^hT>ZLhLx;#=%DXxNmM=dm(s&dc>LzlBmWv{_FJU^xEnj@cA_DKq4+rki z{sH1Lfq?e?{2ishHFU7$C3_fO!*<`6vHpa{l=ZiD1*uY*wLqwp( z2FuD{L5epOp^5P7i%|52-I?KITn}Q!J5{Z?gdfSQ*$KAE^l+cyTo_O52r{-Z9X(i9 zKJ-9&>YI0!vCLR^F^f2xGaKFDkFAO}qSkd*`ffMvU`VXm@U3^UFf%}Qg$@37cJ$J< zGF0ZKv5pvalOAKy73jVY1@a(Y$E?U=0z*c^dO5@DR6w`MKH_ZZz6r+ia)UWUL9xh82-h7PswG1)sZ*9i*d?wSF5I(K= z43X&~6*yKI$u!A{wrR!RM3Uk1!wNC;JmC{pJM0i!1Zk-4i~u0RHRvPm=y=w^dH|pK z(l`cu4biv-&IUgLf_HjhN!K>KWx4V^;fw&@1YhKhu(+jjo4CLyO7ZjSOmKv0>d^=d zZ!AB7Drqoy7{gLdqr)wLFqpA4ByqhAt1k}fGq2JwfS^aEPnPpO8XqSr-BKyNb-*k$ zr7h}j-kKoI6#6L;W9 z$mCn4p-H-UA}-!Zql3gu2f>0aVuY5aj0f2$nZ?E;O#JLaZ9&TTw#40g$yDml>@B6_b8`yrh6EW_D-K%MzMYW5ch2l?i^Ki(^-Gy*=KU48+;Sd zXD|U?A7xT}nqDP__K`)Brh=xaoui$s~}nejw`-E{kk2ljB|vnd#)n2-36vZ!4n{}RUBruHO_ z6IrLZclE0B=O2Dwx$UOcvG4;NT|CCXVek%ngChENkE7*$-LsFDqq~lym~nIDp?$P& z`j>I`mN1d$BT&9PX?o~Sa02J>o-NUb8-r%{1A7jzm3(BGKDDu0z|!Hf{2XVdMm~tUtGYGaBYUSl;%ww=%G&1J7dBnhks7%=_2xWdM!b51=zD zt};Xs!f^(%_G!Dgl8}))cv$g=E=yNjDM)<{R19hn+DNMpc@+ATVp7A&0QpqP7PgFk z@GWmFEB@7o$iD&3C7)XsE?!W+^AOj<{q1LBS8QJCN8gn^9mmnu0|$?md6TA<)$4bb zfBfp*<(8Y?P?jxRUY@z_9c-ItQixUcv83hcXW-|CZDr%ueQcxOUk;-%(A9sp#gAk+ zg8B&DYH$B>@BTw&E@$$;cJ~8i>Eb!?;|I%S7hhPu@|7>cucIjAn^Z2l`kJzP@BXrC z-PUrjZ)DlLV?X%NxPQ`t*w|2{=@r=)CG}k>M&0bTn8%Ka87QkhKpdC8=IV0$m%du= z`|dMk5#?d>l<_EFyC5bnP8?@|$IgU_Ow_#L4X-N;nBchg-mjM@o_vJW+2_iuFFq&A z∈)%WJQ_l?jH;ah8AFcy@R&78y65ZTY=Z%0&za4{!^>`t@sISq>Z(So4X@F|#7S z!ft&9j2>A-3WN#Z7I+g3ICxguSkI-`ve7O_8Kyo16>&7^BCKu=84+jTz(Iahkx6;6 zMb0>gwq>d{${nsyMD+4KeFC2Wq>p+bCg`L7BEO@2lGgBc*B{c#B$SaOUZF>29utk0 zxjhGVvTJZmx$dSL%H3c2r*gyVZbWfoZ~28^{Af9ot@q2%I5P(2^XD!qfBZ*(TK?v5 z{#ThcZ8}GW=5X!ZW60^Da`VkMF`$1Va(tpZ{`eCp-b-!yGdX6cqCM+PC+7F}bLAlu zPjOord1*>a$1arjz57Ss&5n#k4A>`^KmUurVCTx*^3Hd>Gj>^j=Chv*-3#hX*|mFD z4955D-kteUncU)BTI8EQO{;GuEb(bh)V&gouQ$b6VQ=~5y`NJG^G)L#!>}F zzlat7guL)>)0_=qOhy=Y_+*IaFxV)Q20PDDNTnKNLdYv`BB=2onvoACS%FmG>gs(~ zCx+@UAc|CpFv$+j`5k$|Tb$8>^-Y-w-s@WZbZD8ElE~BXQbblnvbz&k2W&W}9JQjw(m1!B zs)O$;2m11zxQC{(9WauXx!R=dR9Y%@ru|fE(m$h)XAQuccx(D9?>c0w6&FRQC6ATG z(w-^hsiWNr@t?-vZSJM7u$2xwU53u|Tfe1=0BH?=Sw-1=5{F*?0-3lphHFx;Q$t2b zOa&3F(*WbHCM{jn|N!(Q7xFiZRd*d$eI1k5iL0 zECipD0-T_6uekhx&+-_iAe)?-W-uAL9&j@a%Bd?QahinH$}ALF4kC>&CV8h)GSp=_ z4!)~g#`RDP$i2#HGy?;P4{+#KAy+pvj%I5#oe@h$Tr1c;#_iCgk%wg@c&kImh3n0& zoEt(%qzBoE;XhH?2QvLmv?)_j-dq87RSj9(!B*4JWq;Yjpm6+(bJ1BuS*Mdbz?SR7 zjIjETu_ga-PucP`gD(c%vZ_h^m}QVrvzqxKhJ0{`#Q=A)=k>ifnsv!966(aIi_aFxl^{gugR(N2i4_(AV^HBBQXU>;8~p?ZpNF_A@i}&R!mv<+ zWtpE&r+)-ISh8eE+@AF0lTWfrJ3jbqo{u4YM_94z?>oSe3(kA@9c1CiE+l!&jKOFo zG>##Urc}L-Wq^SvtM2wuk1)YAbMiE{_cI`+&N%OkdF75Te6H-?zJdGJuPBR`oyCO7 z=zaphI7iGi>?3PvlW$ag<^+BI?v zgN}*i$*0zFv|xU@_x>jt_^v5$zTw((#cN-e1G2rl%c`{u=$ZUkw{cf_^oiAF&BmSV zYMMa*oZM&Efnx5h3@X)gP^i-D!{~xovTS+z+Bex%i?Xw;uehXq@F#zUx^_g_!OH2w zE1xV+KevH1@)O8Ewkn_K0UtZdj!>?c=#c+0W*`9`&za6KlP$=@5|bao5~0l0{1a^>s~eso_UcY6Ak2?%G92D`e}9@Tu^=#9R#D;*Rzw*U${p)WouR8xy@|KKt;^^d2ZcN~a@2sgYA+a3|?uxAs2OfMkAgy-{nf423;rA@F%BesC!J;=a4KCB-}s7ftWLU>@r5unl8K!G`q4hDCnsEqIg zyQ&|2;J&hV-@bB)8w;jRn^J!CZ9h~#^iw~^4vtTj%PxCu`OV+>zstw}+sDht|LhZS zGs>JfbIKdvbW{1)|N39WE}?B4>A2^fyHQs8)$*n{y@kR3Elfy_55M*6*RgYBW1P)* zQNjgex7|TB=}{>)jk%KLuo$I4AN-(1c-b9pR&n3kuX zc{cpkuU}uD;~0v4so)LiHIH(PM;`)wP6VeP+>(F%?1u#3EEE{qI**~N6!P42&yC{) zYu2s_`rYZ}V4s>khOB12y!ZLfHLuLTzM;xQlhXQ?LLmcSex=>c(uVDiw5Tu`Rn*9n>jVs=`Te0BW#1|oh&ge|>nOkwPQxby!dQd^P!VixI z-O5Y&6fgt$AyRS0BXAp^H0N7;rma4MT!Y{czB+)b!s*pE89u|dU0=}F;C(@uSJ<S;~&ws3zsj?{tk7I@ujg2^-}}4z`2U;4k?tuAt8- zz^BYq^FsI|r;rt8FvAcq(voYuY<#rwn(-lWCI}sTh{P;RFVu#t=-FWkXC& zS2%*o@2GHrOZ27!gS+qGePhosxI%jy4-muXjo<;Ckz2mRRwwuDgk>B7ln)#N#u()d zmt~u(eBsb%SX6w{rbcm*- zF<&oN5M3=YPG^-}y^jeeN%JRdrXt=o9Su@^V#h(Gvf3jlf!j*U&a`nDK5-=C*eR6O zgq8pP0WXFs9}$Ln){cc`t&Ib?DsP0qqvhwSpRlpDHL>N+q>PFBF9&7@t2o7Lqiz^i z#BwlN(=P`agGD-_FdV8q{Phby<-4Y#zAK97f45?ZINFgmA)54N#HRQ8F};w__ZzO_ zjPx`;Nk}@av5g7EM6~msJGA|jV7GW%2I7svGxOVBChUO&kM#zL!e2g0=kuUHZJaN~ zvC=IIt-qc0R-3XD3@Sz94xXUJ!S)II8m_SA*=LUXvGN`DKJ+?JBe+zqVsb`WVF7lQ>C&2kAu14`sp9&^Frr zMUSQBoZ8@ZvtO2VOv1?nes(zsX7|Gzl7w?hFRTd->bn_me&gP|nYb8J&N<_308f@D zo_Vs|`SpJ)>sN1JC&kp5knk#Gw+9a}K$|dgT3NPaVJbIhyVK#+>=AM2{%@cdm!UT%Xs&>;y{RMlm>c=fgpcKlCwSFku|$xS2iJ z0?!w4WnM1>ltX>;8X;t|MSjGDhh+^0IRPV|%rxmfYud!}OTY8SWzA#XEthas_yls< z#b9gNZjYGE_0yYn9VvhDziuz* zEMLs^bnu!m2icw5Jr*T|Xx!h$z`Osrn!_0oj-7T&H4cR!sB*8T9S)Ydvf+J<|BCb-4f{P5h^30(0F!}-3u6vr5;mzdHq1c_FhJQ!> z89UZmrm==Gli+dl(P3|#PI;M^!W*t_GM}wOnljmVn}5}0)N&zBts`svL5b)ansR)i zz@!Oh;tf0s5MEJ!afk_Ud96FY7IpYV2@m9Gm1I35qIGVB!C3W;3klVsl zlRL_^ne)qQU-!DQdF$q~Zr$4QsudTPU;ou#DIfdTe=3(;azzm0blI|y zZzr~vX{Y{HkB~dUEyL<_ImnJCC-xRCSX6Gk_07SiaqMQY?Y6J8V8Md&%(JV|A;B&Z z>Q3uocb3W5SbSiMO7tUxVag^9lUKpx%2SWgP&WCi`QW6cI{`fkU>USuW}m`iXQ@0- zzSl8A2d|ra`hH%o=)k@bBxBO#AUhZm39%AYJ1z=Mm>C^OAwB7qQ3}p6&bpj9)Q=97 zk%j874DQ%iCQ?}}m`bI{cBZk+7WFXGHj+m7ATzE`c{sBfTl|C*8u3~<)1 z>K0Keta!c8*+EL3h!IuAy3>HII%D>UE7S zBVquM<)I;ubW>IHh!xU~jCZi7sc}V&_)CMxWKq^Pv=KD0LPs1C%5-O4C1A#-Z$il9 zOp862bgucLytpFicl?p=x?&%^i~$RsVcQpAD(`A~{I2D^A%zYn@k($+WeoWjv{f7+ zsA)|)Yv}g7K`|uGz!{Mz{`hV^jF$B49|`sSLI%3pXkG}g?H9QD3>vC4AHhG7Re?k2g)7}j1REVBl1vgw`)fkoH38FAADrcKL#dx z4z-K^(jm(ANw(V`qaU?x?@qRu?nblx!Ls(@M@rA65#`9hp7PdP|3#cD@24|MH;kE# zqjXN8gh@TOw3;{F)C&%HV^PK}ZpWpKEC&rT*kc9ehl zQ$G`DSwHcKPoUktmsQ*&oXdU;*v+v6$MPbVWuc7d;}TsdQYdE&YCW%oY5 zyE)@~!ktv!1_g)67gxn)spZ23eCr#3`{1N(NDO&d0q z2hb{i#ii%N<5^LU8g?{0I*y`IzH1aWQGs*KhCOA|*4-!^>@K^Yal-?TqD#V^8Wc)a z6?g7NK3L)Ry!$a$<)ztO0P-@+Gppa|p77?Ye)^VMcCx!q~cqR=({T6kG6W`=K1NeFEinXQG5}MmfL^lp_rO z`CTgB~&(O`Rwi)QLY_zIc*Sn zF_=VTRK+Up*s^Tt(zupwFOx+SY|{JxQ1>R_njTkuXLa}OzP;~@y0x`hk|j%CB+H9z zV_SHI0I>;}gqewx7@japLc%;DCV_b-$%KR~lL!N z*|PSQ)ZJ3=`*yo;_xyhU^Vau$_o^j%kux)O@Atm-R-HO^>eQ*_)LMGVNe)4D<%Fw* zk00Ysboel5f(D$aZ&PYX4kq6g^WHBRihM8o%6N5ZpL*{xugx!nle@K z``P>V(KB?w*uJFwCa(MurQzq8&`NmX%w!Utsf(zevj?1V*pp(&`dKci3*e)qu3;OG zheWPqkIbuHbz6Hov+8F!≺Oh3$ub_=noR z;2Oi5U;66yqd)q-_B$W^?e>;8|DATrt+%w@yLPn?-FYX6H$K|-@7u?0{!vx|EM+Ck zH??c8yDmI>>s#NJ5zRpcFvv`=%IK{*Tbj_upq5B`-O zY(Me$exluR#~tbGeC*>NqwYA|uDJ3F@_BFWxA&??^UD=NUX9mzJIOcu2FVK;(0QJI zJnq)v)>viCBkFV%dslos#kK6~xN)OyUU7xFx@zTllzTgS^RlS$e09%npkfbo3Xyaw zG$CH%9MMSYoeIW^+tTZusLNI?Wkl3w3}}&-b6=^IN&syb7*VZwAwo{e@d?3JLDET@<``>}?q;rxye%GOREkAq=K5y= zv~#LJ^d(}!f`1CTZv&`wgK}&Pf$2OF2GfPcN+z)m?)q7YcN`TO2z$)ZV2ecBd*#sa z^a?^W)k&o>Lx?nuHwu%jHtf z2_%XAQZWDjaI?U7-l)LIW9Kzuim`JOA`{`U9Iyh-TR7ap$(|u|LR|{c8~_o_cgS~_ z#qQbV!|#NU08H{9muL9nSCkEa!YXr`f&L1uyU8e-N~ky#=m?8pf~x8W-Rq~j9{%R1 zrM`=f;@t>Vei@3e`PE0nS^jm39@CK9eKu)+6FfnvIaGRf6@iUh5qN2@+TSJ8>bSXaSs#6Dc&EIwidUFGY?H zYC8M_9eBqiKd>b{57R&R#4+?MZ*i}@*I)c`GqN}g9O6@+rbF53n?NOLsI5CKFe3-f)Nfe@#?t4a@-Re?sM?^4NeD)e9J@a%97h0+_$OB zdbL~b*Cy~en($?ucAkM8WG}f~1Uw6MUxTywCeol>hri4`s`Qu!ztg#eKEI{!%xM-= zt6bsd%-(`1S|YO!9M0AW-l8ex9r?24RhhywhA{M5@B%m3P(GAH3(M4EHj%GX(d0m} z^DN26-Rr=-_xmEtr%yqjGg9^?SpU$DoH*Lft=ibmaUg{HnycIPYhKhIx%bJojsd-sr}i^@c1yd8yTKp6=e~BHj`tcmvrK)GKKf^PW1xrONrN{Q8qOT|C=$DcyE zJIMZVPgZ{$O5+y7?ITYXw%cF#lJ@y~U&3DChZs;@o4CB={XF!pV5QW0wu+uZuGVhY z+*aU!fP?DJpuH~UZuM2mF18)lT-LU5V*EEV8GO^t*R?eaM%?p-``Rxt%YEO2EG=gi zbO!!gRx~MZ$X*7n!AtJMQCU5F@KD=MeyVJ}7vAn&Qs zIcK4@V@#l(B|}xpXIXWz|L7UgPh8~Xi4&ZDPd)C!{uvZ$G$xkHBYO)}>g+RO<>$4P z)2tF%$O;O}@;UanUu4C=8O|cu^ECA>1I!LqEnw-sGBLaBc*)eV6)fvt-cFxqh04;E zQRQbU1yILjbw?!a+xkS14Y_3IS40TqXOFe1$qjH?w2laX#=M4Lqy`3am;C zfYu8YHswewAn7;4|H3^4!QHZ?Nn52w*on9k$LL!c0Z?FuU-G{KC9Lp+C3w=V886P- zt%JQ%vrNH)O#*n}kNiz>7Q!e!H1Yhzq(y{#Wq%E zY;Ax2um4pRCpjpjkshuAWmVGmeD`;fs*5P+Pq$zGYA3TK9dQ2TN%z%IL zK554u-oPjGxz}$}lsX);ti2)wysf_t=gJ1RnR&*C=LEQd&BOGp>l_&CN%xVHcO7bRQ7(cbs{olE*It z4gpPwf;Ucn&Xm~!woHO5xU17UDE0;!Dj6%As&Ew1GKI#fMw{+sE8=j|86$4#OB#Ih zlNUr@025EVVoc$H&A`BRAOZTvIQ`xC8~-kczo5`*Fn#sGQT{o~!+6k-iY2HeY%78GYM|w&bD_SZn{3A^j(p(^(-Vq~QDGRc# z_-dH^@$Lh&zCAoA--NXT-C=@wNCSkB25`xT;PF*4n?~a%qQs@On*{G*-BIAU@$i3y zrvu<50Ab}>wPkiz28wY1$_yw+rpTLc&}Sg0^Rhd1Ds?~0 zK#Cm~mk&ot2M}8gD=Wc5iW--b=3hU$Y9hUjK%-w0%4Gu(k04I=Y)Uuz;9l)RZf|01{AhrH_j7!X!M z;e}~-wWjr)W!{yfIr% z>~}6=Vrq&!oJMv$`1uSIQ_H3q99m4Bap7n?$lmp*cYYSdXHk34U-+|amyB4O`o1zVHO` za5fb5%%C__`iwkGk2DWAVm%BgHegJkr ziNEiozur!;;$zdA%b;b7lll*#m|jmg=a4t9blkwb>qigmYlrqf&49!i4)Plgv1D-K zytHYUSgbxbb{R30cJstiGp<)A`~{0I91ti5i$w>cTb$vQytzpE%e#jW$jLX$MFPmt ziaY%n>}d;u@BV(v?;2Q-t08e3%Ba@-kR{7t_Y(&&>I^!L>n>ZsOKr=B747w}etA1`bVshb`)B{?C)yAG z;19LiZo7>Y7iWO^Vmq*R4_i@Iv=`raZI-TY;i|gVyyn%kZ7ABaY&}vqD8mx4bj2dh z2)Q1bX501GZU+7W+m0N(!w=bA$CixMulcK>wy ziJ$lfoW{Sa{nY>Y(>V{ocFKMHD(P{h(!d0SpB7^p0&dXYiiHx-`^-78J-d zMj7$5-KafIo-k{|PoLv3JQVH~?8BMiY7i^l1q!z$5;oT;Xf-}6Yxn0{7^gUGaR$59 z!?Ybwdz8d`o{__Fm}tdfN1}=y-;^Rm8CN@hxGSXmS;_*dKwDtVAxxem2r~0kOGgQ# zL;VjqSup891vZZehXo;>Vq-83V#4BEJRNrgWN;I3J}&7DYy}97B~-ohQ20QR%18V* zWK}ptTr^6HLRPbIfer_>iQ3A-p8-1G^pkSw)^rl`kw>MiDjH$r>j0atF=W}syfB`a z;Z?!<$NX^rt-eir8Q+x>-lV@OOC*L;S>JX}h2=2-Cp0`9*j2a&riCxSb^H|z&u2J{ ze4fXWuJRbB6FYVp+vfQVM11eoJq^jV5E#s8uqPM5+j;yE}HwA|*wTknqYav}_+sFEL^41s)! zx)_xAsGNgDneo6Z-O`EdJcJ&6LxeR}8W=jC%jmp1qOF$=iZh7Sa65zN$T)5`co?@K z1+NW{1C)eGeBg5reMl$192VxAFm?_lA%4=wU-{@M*1{oWp>GasyyGJh|Ei6ufMSwy z-pJt~t92Uxp-HJt8A^N|kMvmWyDWB?1vFLziCcV_eyCl($|Rc@a3GMY3{+C2y~kS+g?N;o1Lo&`g%Usv+wEa*f{k3X zBABHdZ}nC zH%I}>gEPuSmo!`NXOLDYRQZW431ism90&bCx@ki78e*z4|#d%r}6((;Gd zD)bHj$hUL!bL{sdsNM+i6pFoAeJ(-yT8c8c7CrK)^2z|o*6r7}%XVDDUG_JOBLW+Xe*02DnzhTQ8&~zAV-Y7%4(fnco@`|K{f-UXhy>5Q zde0mYf8u49`2v$D^233?6`Z$pj%@_L@f*L!a@X}aXwBOL7NM}3hc1Wp=ggS{g3ii0 z!{-v=sz*>b8Qk>T5w8Swg2uc%#W@B`7Eg1U_O%=`x3&HBPydtlqwo9Q+S}j8zF`!C z|MHp7k_S_5(|T4xaDV*_gFx=@b(MvKs4fe>NS-+GX1tOQImt8WyU5b=M^JbkyZ72Q zefDW)*RO2TE4Q>mEZa3t7ZYFxz9WzXk_YzlRE&#X;P`zvep9Hq(Cd z1Mg=kGJR@h!*9I)3TD#J*K9mF~gwL^O-a`f#Q_n4=U!G#70&m}3`Gvn3 zFib?|1>_KM>NV2j>E6z6TF$MnqkK{}ycysEZ!!RRfJX9HT#KZizo{t{-f>Pw#yO9C3OiBPjq7bf*#Ck#!8L@f z`onsHwo%#)JA|LaBbPg_Nq3Q1M~TjQFLf5Y42+JQU@Xd?EwG1`>+eD0Pd~i}IXgi< zoo|11=kIYq;482FD+FXWI6ek3rxHo&_gI2Uc~j8JWDRg);ZMkrNbx@ zNTy}+sJyaZ89GGUQMIDDsG^ynMN^6`Cvku_Hs+b2(7(iU!BDg6lw5VyfxcY zf|iidf?qIM(1qg2u~x9%&kji`@s(!7mf#l8w5Kx#ZE+6@V0AbBp~blBJI?s% zu78yI_!V8L+~I>?Qdh2gOc;Y!_z6c~4KY`)aJv+O$zb1bJ2a%yCL&41%%#65E}!8E zlO}`AO@cfFZooAs+$BHehMo^HM)TZo^TX9Qp*x|M2AJnMj;#{Vku^KlptNP-D`z3fytfyXiUrF+L+a$asmKXUg2lYE&7U#{^P{0K8f zA8$VsM;BDnI6+^PBWj{l=2j~zGDT$#=2^bSWzlq5pSUW>y?{1ehE*wYpl&&Cc0`@2 z%3f4DqAsg99tR$s84blEjgep0WJRa%Qn1PwS1i^Sliy_zP8)m@U9;`DODhRTdI-~{ zKm5nfFd6*vomi_5acQR=LmS*$rdIx?P*>!EPdKpVJ>W}&Tl7oWD1KnNz3O}FXm}R` zE%HKtu}fd%z`Qs|T+Joq==VM2$Wcw?Po)ZrZdd2ZPyxF<+A}NeDn4slmI!SxlM{>iV3B zYcgPm9)Koa-D?sY|L$D0*bd9L;=hrmeZwsS&$Lg;GTb9O@(cvw-FyOr>4kg9b!jcR zE4;<;Awl6|0IGihqyuIPTrb(@R? zr+F$zs~*C!3p9Aoa%J&Jl<+_Ej@PyAS8YRqIzd?@ov_n7!Tr@LQtnH=>vQ)oYC(AG zA26ObLgO_WA~SB6cYE*rBJQ_e$xNT+*}PQNrmQotyNp`pde5FcsY{PiPV6Ik8n#zu z8D=wAD?5uU{BoA&BPx8X9srk0 z!5NeZ`&nn0m^y`GxPa{wo*M7A2v>cm=b9Gzql|fo)`}JD+b93zE@m1pYo{LC&2sq1 z+x}zIOp4KOzKCK3oa|dbm|9gLe_V+mvr(!MmMx_Fr#|rE_JuD!(!PU}@i%ZD)ztF! z?HAww>+K*1g8lr@{G+y+l^PyQ=|GXIXihPRaSlAES=nJd>#6k)yk^yu{qI2_T~%Q_ zW1o)15uiE z_R2KtYZs*?$EC*=79`d9u@hV-<}YmwUyC>hP+pwnTE|^nSH^T7D|y*M=nD+3)4{$)=W)#xJ%qDwiWZgf0m}~i#IItTz8sa6r z(wmGA6GD&<^S*S!uL#yQ$5aY*^`|W7)gMC~O7h@0fneMo0Ingda0V(oA#m`+9vaF& zjsr~vV0g=k<(Kk={B~T1bJdIBwvUlpzI{6=Vn5~;9M*W80~S3)Z`XAj-~0yqPG>CWWdcqJlk&viyRm*t*-2I3z7o~ z4$_=rn}jr-rHo0-5(WfTuUyI&nd5BN*vyKg9qeh}&2K;T%S=1C?+~<|YWp~(@9w+r zZnxildwci0-;H!Owt^t*)H@s4HnZFMfw+5nUwI>c!jUR-VK8okk-pS{mX~KU$vfcu zvkVcY_fZV{LYfyuv7aPJ+KWU5hz}BAMwkFA4m)(S7ETjF!WO~Ih5VLyAdSo8Dd1X|Ngh<#WOqRZe zsg-HM7(T7(M(6-;HU|KF_Ut|G)NzCbLjN2~{DkcJqwiO4L^#QhxgnEhaT-ND7vL-SN}kb}74HW+&FGN?A(z z;!*DByX%9wq`UDJw!AycsG#5nP9c0!gu!25=?tYKIhB55tfjsr-kLu{n&l#8?CB7W)yVQT4r(9U}lo=R*rLe{xNGs@4@ zEx09#rcB-sztkm(lX|59M&YubJ-Fa8_;SKF>rCy?izD@%c8o>Jn$>zslWHqr@Q{Z? zy_-BKkihv!Im6A)p|x(OE%M;E$ThIdw4@Fs9(>|#9WKh^8y%kHpLhy)DKS;=Cjbxq z%5=*-qQu?3I_SWk9#B7DcAW66vN<)KD-l+VJM|2;3N?Muys z3>1#g8`=}}1$=a*6A1wO=&RV1_@v9Sa}nhy?Q}ZCvQrtZ`o{EF?gAToBzY)dA)@MLOte9v8eF@MG-tw%@jT{RZk8XVwf;w39R@WR|usaY)roH{Q^`^;=%uRt-H- zS>jJlvFM;Zuyb!ZWz~QtTLZE8JgYS ztCHhP=P&>2AGP1$_nq%~XIsARigx1Ms&;Y)E|8`i04I+LlU1+Kelc4@P(X-NW&a#` ze*1OTw}U6ow!ik%|GwR}ZFRfuij8bRSksOlfRBd{aKIlkme4{@MWH{;R;;5(PM}P| zb#O1?l)DAoMir!k0re(RZ{R#rYH~>Kawq=||x!ksC zWm~&xJ%>bIU^U27xxakj)OnV6Pqn}DL;oWKK&^f9Q=e#ef8h)53-{cU0iPG&^b!Ve zR)dSf{x)yTK>DuTyP~AJG~0f?QIv9D(w_uCQ%S68y_6vkSTALiiuj7SY{a4Kq=Ank zCoKGTY-9H^e6Jg=?tA~D!->XU^;5OiUGJc{@g{EM-nS7NUt+}~uj;$p0;6@rPd}d9m=;Yx z>!;Td^N>F`lIQRps?+Cy_)5G;cw`gUae{|bQtP<(w*uZM;{&2vjNTx_O*XK zDpJVwnFCzbh zupCNr<rRz=%eEb;C3K4IG@HoW&H>!Y)hsbYvG?#K!+S89jif0qr4H)A zUvbr_yZB9uZo-8?t(cxhad~%glv?7i_NeekTZJw7PPgHOPv-zdM}Agkg7D-`xyuLY zA>fQl8ddC*Uhz6@$^RU80D}h)JL4glxYD`jqx^auXL_Vdxd0z_-@>F0bc7j``V>~m zSAopK;KeR~y2)~1Y4vZYPhAdLRep!-b#MO$WeR|(O($VZ>;&G#RgWP(0}K%h8u(7c z#Cxv0c|>Q1*}|N+0Gx_SDLv&U@`|?TsPArnws?9v`db2|&v)@6F8P+&IO{Yroz9en z3J4v9g@@v(GHV{fAq1jO$ya3zIDVnqHz9~UxP2>QaU8|=wObO$fL}6|O-LvjsHaSa zFh#{cZwRXV%J~xnD7fA@%OlcgIGk#5iVqZ$@WojQWgT9)%|phz8-x})c1OKbS}M&$ zT^T+|#lQy$J%?g6V;clMwiz?w!OC{(2Nh#3dqb%^)TY^%=n3YVfL(#&=_&hXP=cn} z$G?=0@N(dm!p~U%=G!Q{!E_}rNSA-V@Hn>@3P!y zZ5_LZneGQ3d?0&nUAjKa%1rl_Uw-AS?Tz2eVRI;?k3X?HgC2`fYRxN^Y`34PZ}3Im zRyS=bDK5=F$Etv{oW^~C>%G1dW%Wfjzp4F=AAcX)ATG8qKJqxHxx2KSG;@vNMfSTp z#*-=^i^`G;ZuK{9ALOh8#+d?aZ8*Xfg>9>sx4p+sv?o5dtG(j#weW&F-j5s(T*)x` z&T7{c9L%?mn-N?ZpS~c7m#~aoX$y}DF$+!SNlYf#Q1;BjG!oD5{(#EXaF46)J#-wq%UNdZuU@$EVGD1EXA6@x&g< zEGr(9s4Sbt?TSFll-o+k{faN1e1_KEhLV>EowcKQU+*+L38mB$QAEN016nP*1J3_Gi7 z&#g?{!^HBjb0=9&#Yp2)1_mOS&Rk(;++&YPhr!zKxlH#SGBF*GxJ@ve@2>FJ;H~6J zsg<0dxCCKv5W$L3fl%Q$l)_$dlTLZUuh=v+?D8hO8VHNOLZ5O|nT%WF)DI7FItbEd z;0!65;!)T&=_Ch2xK+l!Pf;aTm^n>NZ5IyY@m+ zHbHtiC(sQcCgU4{jr`_Y3~w1RAH?goadtW_H<~neMZ|m*&-fNcg(|P$8*!tjWeAoy zD?ZUzxN#X5s>*KFU-2gb%ko0%tfCd_j5D|j-Z0iPURza4y-G3V+PcOL9z6FP5<8@x z^z8m>JB@z(HXa+$#Z2Y-PGgB{wnPzES5}KXMYXh6>im|r`m%dqcxmmOg|Z9Z)2e;a zFv@Nx(7FfbU{ty0FLfghkrLm+paD61ZwFQ*FZ*>$B0{@#r!A04> zdQ?F(k+AwMJe~GY5+~4C{ZQ>o^2kJVx1p z$xnT{o#1wXn#DiYF5h-Vu4a=3OX2Mj`b*1Ms=bgAm~+lDlcfDD`*x7e)7YK0cNNvr z<*QLxSuV_yZtG?1HJA75f0jM<$JsOdr~mYKwKu={C$mCe*{XGI)#l5&X6|hJk01D8 zyYHc0Ol~b@DgP`>`dQjB<+hi1K8xNELm z-8OQqqX*S3aPY!G(8bGmYp?p$KK(3;l=)$uqpZ7Mei6#}snaLZxA(sCMT9xZDg0}f zqnt12tOHK9zks6dp^z%-i#eHp0r4m*=bzxG%E zdTv#C#VcNsGZgOP>cqFd{mopbx1JQ(rZ6bR9p|p%SjE2lW84%ma}j-HXq?hsr5u=6 zO9UymSPVwj?qD``lVaaL5?*aMsw)jpdFGp_j4kEdcUCg#66E?1v5UW{*R5yE(QfL3layJ9Io-0hy8YPS{##jwf8F)hvx4Pv_Uy0Zwu@sa6QB5#Po&Q! zJyIMaddW6{m_Fb&!M%~+z}&z+`$IhPjXHrkr_A8??18>2pRZf7ugYQ|E$LPOZJ_vY z>4iCmv9l>7?9iolC0(^=l;(&`${{E$AzHdkVO%dFdzgn3Duc#D_OFAEFi{;t__AfWB@^vd5ywak;>*t{^Bw+!EAV3G7}4e9#4-yX-FLN@f22h zZTJ}Dn`gRTXdBT}K%s8}-nfEqly>8!Yy;yG)*K)cK2)roRtYFvrA+!AQp7j>bco&h z1bo&pDnD6@MtnAi?n!m@cNv|hECr=u_0T4pe^1c1BVr?+1AuVNVWvSmk%(9;)t!gk zsW{d-QsvfstQ?T4;(w(pDM&tFM1fA7XxfMR&^Ew5yp@_EZPs~1dNX?t#u_;{kEGY` zmatXdNuRM>=1fMh9T)z^qw*fV4%6SpAs+ZqR2sHcl}Vz!%N|0~X84h^oH&RR*iL8K zgaL`P;Ndf7!rGleZysZ?(9mh0!}C$7ZZYm|f9AW>)qRZLHpRDXmFbWd! zxWXHHg1C;%kVD*k)khIt(48zpcKbxoxJ71%POkBy%c|*i z{l;xvL-qN#hg0kiF|&M{gUdE??b(SFr#Uc-89fFk?PD1;2-Eo<%dP3IQ>!mRugb&> zGq&!hj+{Y+dw5TuKAS!ECl;Ip2`92MDC!}188`yBOUON#YyE}|IZa*sX{%tWhm$Vg z_NL`1quz#eikV~6I8EPl5q;BHmeXHE!CVNPd-osC6_o&-tpFNZ~M8g{x?7Pq4uT6Idp8@W$nNb1_xGdf=8_#-t$-?yp})yr18-r~SB#fG!+1kGCn{H_Led(3$U;o0t zNx$5DH`kJL^t-*8YW@0&-(BLYC3-Hrx1urt-;Z=7hxeoB*16-+i<)-$M>o*`vOWGO+ zJf`90!;kN7zyE4RLWx!ID+*pMEui3p4cF86!x252@ta3HaRFUwF^E+K%gQ zAmvCsNAD;~UM$}7ppwJ4o_%RNg$ zjFkhlrtGGlTy?1cNcsR|3l^~9+gHKyG1UbsMAZ#71tY9+co-psC62(MyQ#3_ zAf}>6VE!G9jLry*X-S%e;V;!nhz|jYMA*W?8@m#ny2d(`Iz`!5t~r%5XJTAH7U?2U z)=#yUz3k=feee5QZ51cwYaaOWgYC{czX&~)b?Sf>tYT3fQYQ>LUXfhwe(IcrG@+Fm zKcPCV&;PKM03L98dz$j4$w~zEh}v>ye3n#y$}OJdf(^5t#G+O<^NB$_ZYFybg9r1$>ON7@sQ zJlZbjzQiSqR&jWq2bG*_%ZV=?GP#!+>;08H4U%9;lZ~eprzY;hqcQ{`AUz70qp>I0 zzosx)C_K!{5!)H;J=;xh@cJBZ`mzA{Q&>QT5G$YsAh!&a&KdSe^NhlYXUCQ9ZwNQ8 zDy$=T;z?X1YU;Z>=zvoqEMx^Q9Rt;Q35$!5xYxTrJKmzQV7lFR5L5)^{5;QrNh7G@ z%7A6$dTGm;?&Os~&lPYYDr1?Xz3>m|7D@Q$%TAbY{08I+XFPGMkaM3C5lwg)S(y*{LVaI~f2Pw0K;r<{B<=Hghc~iRGAw+TL#lw{9RR}A&-4YT-p}zY z$cj06Ac9cRsVRs7V=x6oC=%7}2}O`exMxIL%q}48#*lE&0MxxO8AQ0;&kV0J>u%ZB z5uf^tb#CMXVF42=NThiPW!W?s1=Ty64eSA;?jcj5$Z5}Xv{Zl52;&p8yL`e+35syWc1VBxAjGbtprF5odf8rl|-FG1=j~bMWF0lkQa1DwM$17 zeL7AfyhSBxB~Ec#p8<=+(GjUIRXIyjFSEqSzt@z-V7DF6NNZLn$UW)j=Q|0)KXeTB zp0o%bM&oDaUz7G=;9DGY>y}HrMKQ+=!0C*44}hwk*I^tWxitO^^fT~v9G7^@6RGoU zy3-ya6XI}i+*#Za^`Wa^rD1M7^=;ZmegJgR3bub0$`Ma+7P2V84shWq_vFol+bFL< z<3N}LEXR+XY8#nBb5>;!N{dRq*9D2;8)e3W*gb}lQyF6#ENAxZl_4h%Z1+`IJb7LD zonevz2`xS%=j*pP6g9t z%3bE+6#}$`GT~W6=8{X#>wrt+0U!16MQFZAec{ZWFqTvMFYaY^mOnC&n_C6E_d16H z@-AZ;w7#LMNF0@)SWK0;bsQ9TZ5<}*_5sc=YwI(+r?4V8O&P9-R!H^F{8~Eg2pms?*+FE%TwzTqUO4+LUw zj|>=m^kbiFPdxq@itMrW+Sk9az3i5o+xNfsz0|oJewRP^NLtpeVaA)~>ieF4qFsB{ zRqb#7weM@U-Fho&;2OXa9u&BY8O~MhZFk(>{=)aZv;FMP|6=>}eUCCDzMc3{zL{NJ z06p^T4DAf!fV`4vvuE1r6NlK-zrX#!yWZ4Z^~zgmqd5Bj#d$HZx|u^hue$n*_FupE zuJ%v=)i1P9vO3{)*WHNhvuI<H!b+6O=MM{PCz?;Tq=wXN&ca2q5mdD&WV(~Do$ z?!EUu>RS#lWQ)heStb#g(%-;M29^_7-kt)t2P>{zxtv20_aY}V{FpFAURJGM1>b8R zfaGFGEa7~6n56^dUEC>ka9Lw%DO=)&kU*n*A;gXJ` zQGeTO(Ms7c6tAz9j$nFVq(_TkdHZiw;43z=})=U=rz_gmxVnny1obxO)l5KIX zytA^Wp>T)?hc58GD~-Tg5C&oQDvj0bZ?$n3lj#gBR3t3n#M6aS{zzcOt-RYIfKve* z3v*9{uo;m{prTcQ2)~GHvI}7N9;zWsVI%d zG}b$QJah|9!UehlXip51G>)o6{5N4>6djnDLwg7Uv)5EIaYn^r!P=2Gy>rz*#s z?47jAZ+v>VxOE)Q@)q`4;U+!0j6VyWui3d1+Y!halAz!ZULz9Y(c$XdE8-eHbABcM2x(RF=EbF$Hgd)iJ5YI>Z?P3!m5*Q;$n0`jDW4z(|Bh$Eb!4@3 zpt0V|kIu9Tea${vm1D#Kl911b{E9tq(o=~MGA1PDVY!UOQ21Go*0*(s%ESRy4O#a% zv*t2WJK~o8bKXa6_nmlqhcF5~_#Bw5IJ^8mM+z&tz*qS;KaQcZs9#JPnso=YqY#AG9$yepYV}Oe68bjmrva- zRKd&Chxp4g6&pKx!X9PD&8<(h2Y+53$-~fREYD*?-vDF62Rdydlo!88X3{R`R}e?% zvpA})t#GEfwq~$;!}gO|HalrXF)tc}R;KtS&XNBp{=seZE#Navc~|Hjk9^jcmJzK< z_wYU7w9Ggte*PS@nykQkF-pK?mu+o(c0ZLtiX|-DeV*u_Nzhm7QY4P>%RBe-&T^KI zcX6+#bH91Z^0t-}%rDUKb&_K9=1oxuRlpq-SMd*LlW^_GoWeQ~?JGaI%fB5vfAYnA zn`LSG%o*(rDluhyigJAtJ}h+!Hiz2D#+-^Tt(|{~k-Wjps#?X~=@a7>Z?^3~Yf3CI zo_a1KbJM^2q8tLt#+h2)FEF??uK2OTpD@5A593n+%9VJMu()@tZiX5R7J_4_r&wwE zWmaPRgCBZN`?KHm=G=<3k}L0)!?GK9T-{!O`)e6ES=b(Z9G zgV*fYmvt82ffZ-F-G=)3;j``dnW=W&+U5AW&1#lI23K%Z+eT=e&edxkk~!;aq>v7O>&H(cIc|AsfVoe$jAwrstk-Lv=Z_QBu3v)yph%_y+zS@ps>El{jdmfT0V zJ;ieU7wy>6{>(eSt-b8#7m>&#?Th!`)eav%h*HbS6!QIs8*gkkzvLzDr~dc9mu&+7 z@;`hKg&&?XExypB>)k(n7FvN_Kzo!^?Wsq9;j?qwHZn z$Y9N)3kTY_zWufB#W!Ew{_Vegf4lSJ_qTPd;#$W3{!^!pP)}8jp{y@QQNI#pTLtZl z_ubw8@WX%9Zn@=E?OosXuJ+D%eH#NTOWSAu3)>BL9Z2~9{A<74)-RuG>sGM*8eX}Y z?Xs<#+d6JMxJaHaU=RN+`@LNWswQkrpu&J7pv6 z$ou&om5O>AO1ZJk7q^4Mn#m}h58qef|AHv?k_^vcWMZ-qA&r$xP`R#7rCuaR#*mS- zEQMJ>WoLz;@^E^Jk=%_N+KOwgZX0iYaXUtz^uz-@bK2*rQZP0E5WjI z6u;?;py6&tWw~n#zaz!afl0@WclcBcD&A-(jGamaNrBG~Sovwe(pF3Qs=(mz3?run zE#(3@@$#Pzb1;SNiPJR2e{k=}43gP4&NN8Q@f|ayy9@aEJ)}n zny<_V*+Ut^T=9k5q_b}GjC6F9P<)PEy3gEq!UXQwAdR&AI)u237lmsamw9eJ8pJ}Z zkvEqne2(j!j|6N=_`NVhO9K}R(?1QdD3~& zv#5tN?y+4Qmo}4e4U7e_bELu~PqgBkGz|sZIFo01Raysm^*e5cF%a(od8cVeSW?z$ z7iw&RJZZ3eP4UahB+GPw%3ri47dYY}Fa0*2)DiL2uhXGj-tg`b5A>->7*|Hp0kGal z+%(9RWA}`DpSjArvz!LEt|~Ojt__!aek*=n+A6O47@mnREUBnFjGelK2A7RJc7ArE zHK~gRntT2VlR-*h0|Onf5yhx`?q28(Mi%zrvP-Qao9;)V0=u3?f&xD zHnZp}JU;zSTW2uSO?cbRO&iv?M<0E(-GBf6p~t}%&y=Wv?vC|^e|OTA7v;4p-{-WSQf!RV-Ro;w~ zAG%Zq0W#wc9;L*2XgtGM%Z>`L%Ds3hefY-|Od?JSs_pYzUX|&vli$kqg|=mSVY`oO zr(S;3j<$6Z`E9*IriJ=| zSyQiIb1=r$9g#B#@%p;sY@={#ytKJRK^Z&Apvl^GtC?9}lW+S=OHuO8kG}UceJFAJ zqwJ{gdq|jlS`QIF!;GM_+q2B5uj20R9K=Vzb}2LU3t5(a`qWugC6JE{3LIo0!^16) zGIRZH-~6ZAZMWUV0f!6Pc4ne~@GpOV`!mO8+x-vjYX9*!KN|kAQG)z;*3lcH*j54E zE|EXS$_=-%cD|oHdZ4Z6R;ha)e1yBYkF>WlyKPEuedVj$N&3x4S^4r24hFmVrt8~n zFTXkU_99j`oH=uxgT@ZE@A~#{Z`-!4ZV!Cvv+a=w?{B+z@8o8IW5KnU^nUtNA8K!Y z>)YBpzU@2P_q_X^?JR?9zy3QPK>=p=+&%a3%TpgcK+kQpmY3JP@?~w)+BNOSQ@h&n zL!3;{EewYa?aR!mhu}T%rJ44~qxZBw^{(%3Km0>KK;Hgp`@#cHM%KN#fZXNBA7xDi z4UIelFJ2dTf}06`<^8|fUVZx=Z3PD_Zr!%6ZQJ@(yYrq0ISXKETd{3Jdz5?CS1?et z6dCh8gF~O#2Ys_`1L<7HWZWVq2WMDqbNAg}$W?~kyMDzLS0V?q20UOpFP78 z{Uh*@vl6(Tu~u+d+NxcmCluL8vq#`ef+S~#0x*bwFAk|&@z?Zvu-APGw{QkYF!5<0 z-dOP;`U-vwru>2Q-vq=AVMh_;IM^#*V3Tj^36@tlj(pF!3WM+LlSlTvLtZ%BMBQya z`v98lzwrfMq9x9dG1LS0UHCJ7XTc=_iHmR!qGi$pH*r+oBnb%hIgrtnWyGn!?LnP$ zgOhP347|4=#J4TFb!_Mn1L54dBTp=QwbF$x0t}R`+qka1|3Cca_DjF=@7j;N??@`krkihS ztG8d&SO&Kk@F$+3 z0O}WRby^Z~NH%Vjhu;LbSa#%T=F3fkQ8VEi&N_Iu0VS8 zIee;Fva2nsCw~681m667~;T9km|%?!Mo_~cyXI= zgb@%^p)Ua|($r=`nP0#Rv7pJ$0Grm4mUY6q1T|j7OVc!%yFXT}#DKWfltY;TM3am$Ez-*Rv?` zE0}Sz{MzxbAvV3%MV=MXmwTB_y4z{3*(SfmI+T^v10XaKa0k;VmDu5m$bckED zn9hr|3p(Iu+aR2#*Nx_cFm_z@a~p&4bUuqeX-l|)C|`vpxJHk`d-SbkfD?z-3R?N! z;qWTDcwY)dhnxSdaOK+5C7C&W8X0gEM=31MG<(=ok<&YOJ+7orGy|=^N7Y?`hJcgQ zh1QN?BJ9ZO%tXzgN}KYi3>ug1tmVdx@4U4=aydQ|mcX4)e&ld2(lMe-8oxniQjRQJ zZgp9}RzGLHmvM@?dwy4-82LR5k&0w)4{_iuQvrkENnhGo6?^Lh^SU!uFXRxAgd%N` zFTXCR$gv%Pfdb2!cYV9u_BhIuiiESxF_d%fX!qLRDR zsDS6b{UwZf0P6E7UbFU=tq;ImlN``Ndch1dPhZ&c=Lbmacf>UUqpg1jIDVjuI|~!I zb9#0A!~gol_WPgyRJ(QiW+rUdqs^Z6#SS8%Jg!;A)ojd!(>?bx@+cS9AE_-!r)9Mi ze3lBc)Sff9=^vUV`H`9?%7A;RU520i>5$?I9K&wlTDz62I26u_CEOhhaS*JhN!-e3 z&EPKL)c#c{C?^7o7ql$~9(qu+&8zdXEc<4^{S*gvISI9eYtuF|QFZ#%8J09J<<9i& z%toI?k=)M}bKIrQfq`qdiq3NewqLciT>;HE-*6Q=^4a#gcYdTDVe-nu|IV=dKern( zl0enO&;9%=I;0g|FJD6ZY-u>mfWgoG%s+4K2fn}Uxb8Y;x|s+gVTTSKW?B59DBR&4 zZb%9A&a_S3b$|Kgt_Wb@h?(_WPd>z9fKRu>M-HMubBG@JEuUY$e+zQBxUJo?y zL%Z_IZEep%=!2eWnw_Q6QYzMh=@6e%x+~BeT z*}u@9*!39YX+?X*tG>D2!eM`p?mS4HdxWqsw<}Y~pm&x(wf|7N^|o8uYhUw*c3}UB zcK-tp^FGLV45!-8osXuTSkL6%`E#e+5w^y9HpCgq(Gf{h2LJ#-07*naRH|jG+Qwz; zxyp{KVNp9idglk*J)ikl4)k-t+kNy$4!b>r)d}Vu`E5P4jLWEC9edU581@?zU+ zKFAXlQOl<8D!X;N3*04aW^@&K?DeWrqwM1}HkJi{apRG93drD$9M1`0P;kag8SnU% zdCce`j1Ij7mZjXP-K;Vq0$2_Gt~$^z&gA8=ipaJvWs9_HGPtMgMexZd<0Oz_q)WU> zwUK4JApYVPxmJF{Shr}addK+r=9d>xmfnQGK_08r*ZBtaA*8$9#cNpQ+PXFfu!g?W zle9N(V&!bq#9oo0jwm<^k@v{$_5_O^=?Fb{AT%Jv=W+Rbl$OZ&ppzuwL;NU)OqA&dst zS|U%3=0t!dm^xw+j2!qZWtCMWn4HwYKdfONSnUN-fFn*IRgmZug2#r;JtuaWrfK{g z-K;zj8|j>A=#sgKWr!3!ft4Q@< z^&fsX*dY!)UNsOP9r)W~i6Q@{b@&|KL4=d0{4B^A!}^ZJz&aFPdptoJ7`*TvrO7ZN z5rN@?xCDIwAH6DBiLv4xf>eg{0piZe)FcZ;N1mpO`kK5$0D=Pw3 z3WqoGn6AX9r$)C}O17+m!Vkz%q3B9Qffi)ICm(~euULnqB(6!g|0ed56H{Dd4aCWb zfiC_0&krJ{vsRr*AmIkWi>LYxT;$z5WPuE79=`P(%2Ut}VR|&ecia)7au|`}r_uUL zaiI*0xYN?#UE%YaC@^`1My5poN_oQ0 z|G41?AO3=LQY!Cs2xun*|H5f~8GevgSz5?DGk&<+S+_IeOpW(lYi#IMFg1p=BSgtf zy(zyElLQ2Rz(%wTUwKKtb%&;2^Jt9EfUmF)F3=4S5fN0oxz_D zGzRZ3<2QaOop}$=LmI|Fm$sRgLCvGuGFhZTM&m5+(~l>qK%kpTP}9GquYxyA?j00h@Bn3&>%Kt?J-Dm9ESh4r*?8P%@1baP z;=xLK86M!S@CB3)WeMLHDJvrrO=p-XGg7XEQ)EhxDlgOSp}=ovo5i^^tJ=OJoFISl zc$C7$EMY&(((?1OhY8PK@Rjtdc5+%fXD?X_qfkMUt2dmDQ^%N@Jq@p1&FNu;OI(ftTb*w^I*B*M{f%bu4 z`;B(Zj%!gmxz0~^8y4QLAh~aR^-b-*2foYz3-$FZ+fums=`0HLa`uZ~b>-#kp?{LW zfn#m8=L4V|8-C{GxpwuHS7gPQGv}vRwtozz^cc#kXF)8U=3Ic}MQU5p%oc>DtJ)X8 z^kuF2amH1+yNHKKch?zTuJ8x_dk$$Zn*KLcKfSe$yR_h?H-oTKeY47 zwuXK3Gv^!(tJN6ZQl*M^v zK1Tt@{(7d27zQ&^>Qi>gZS)k+P|u59q^7@&Z!xKHA*slaeo>I2waNgcfOJ|8lLqP_ zL#e|EuVU;V#}ev3w@hckfH>UhBCfO_3;;^ALS@)d`~xpS10JS#F?lMKFxI2dKXB=j z4)U|7U3>7EZkT4<+?T~$Co5x?HTfePP8h;tNm%e3#&+CzJTJgH#r9+)t4RL4@BMS_ z#uwj^u!fu=eft<}yXDqfxUqqiDxAY1U*uQs%V-a;2-Wqa@DTz`Q|kQ?(o-SkGU+c^ zpN3Duf&;nsE#8}v*q85a7dKzg)@;3sr8o42Z&TZbX*`xOkD-4G)`H=t_gy7nOkp{4dh_DfHQQ3Ee5|vOob$y6u>lM03%MAr@w|7ElPP z!)1mIMk^pf`AcIbAHgGhH}Q+MP>>gfJD&YYczYSrjzist>z6o$=z>=9UK|99*AO3J z4CjM5B->_G2#nw%w zW*#o%1R&uCFY`8HX}}&8euZz$+u%(YbH4zE>303~)}>b{zT-Zbrtq4m2A&T9I>g%D zt&A$4C9CX{Xad|H1g&s`Lq*$tc@GJja4D>F9KOzvxp551k$W1@P}b&0pNFs3US zmClk6dE8~p_G#eKklrc-h8-#M$pslA?h32F`I0=$l5{xz6qg{*Rc|4#GgUosty$QCwvSpRq~_(Z=TMnUv{=8S&oqR(UjF^2tEfTf`-<&XLOR!diH( zr<<3XF6>|ZC?ww_?3ex2K!Ye z(s{zI%4oH@Bf0r1X#mahn#fHk6?qY*a_g16&e}tGR==p|tz$;=JmoESDBHTJP}5JS zLkWvbmFjxZ8dBy5QyCRmLrP((v(Dy``N9voAl1eoFQA{Iy{9D8A7R3Q{>OQjGH5`0 z9;VUDA^uX(?KfnrBg?kWFoQbFUh}gkcGAr@=(doKx_iQxke>A@k)BzUl?Pyv9<=s$ zp3~klYl@u?S`^Az`f478PNlFIvX=Pv&<10)Nrj zU0}|jtUJuGXd%n)*R4t&x|n{|O13^wEa8LueSx`b6@zUxxMttc*;HfOv4aDaS*}0B zOzrWbC)(3{_CoR!mS{6LK)x-CB7$-Z&s12Zm)B|U)&-W0i`1dc)T{KVP%dO|x2L0f z*p{m^9LTxprW>J`Z5Zs0pXD4VWmx&O9neC!~yLAn_j-mr8%O|J*-N^Siwx{3(~1_jZ+*qB_-};nnRfZsjhu-v-LAaqa%Asf+qr8m%KGuP zjv3es$mvtNp9DAg-B@kI9+PXXzMLX@I`VLk_kIQ$INb|2tU#2wE#dev23NMWC->}Z zZ&`UqyKLK)@O`H3dg6)X@dAjrKt7mnX>%ELTS&RE+$-EpAX;9nx8$#NNn}1>CI8BX zc~lMS;08Ya`SG1Fmi@slqQRPA3LtJ7AjOLa1K_jb^2L`?^GbXmS2hbL@f$vUeCm+| z(%-t4bw==k0ukp7RM;MhTX<~KD8@kyl1hu78Y9C^+bOx6^9K0)N zz==bBD*>c40gE0m7{7y*(t=M7q)4jC6}Hzg5Rp&HKn5ikc=bjD`$o1awtrvz;(hJ6 zf9pT9lIFb(2(4xC$b4JU)^FU{_B{P`2J_NJQ9tBLQ2bqOmL>o4Y9L-Zx}GCd@&t17 zsIU&1yqN@oeWcf2@`nBlzgiQQ_)#j zT2s0o$-QZ($h7ka;65t172M~!h$T;_7-8POcORARR8Fp3wQ^1S?sxxLl=>ZX5KghL z<}#KSF$&0mC6`lKvz3PZ`fBx6qY;}p6BwL8`D?(6&acj4I!PT;>CP`iSOr2ytt%0X&=hXkd7X=a#}1; zY=D+b4uQyual*BC+N8qopofkQcPanCjviVtNoNhZB_C|GsC)XTsd)NGsVM9%1OV>)Hq|~iLlPvc&GGIW;E>ddMMBm>*B$L5@-yEjrLN;yb;DX#%K7C zrE+F)!(F~~s014V2xnY{!p<@LATJWK0tgvX3J+G@31F(zAvX_1P)K+QP_&z$eo3c) z!lw}~6v?X!YJG10LlFVoo}g^nuqy}Vb7nQ{mLw|hNGpH-m)uBq@nF6j8h;VOtH6XD zXicye_%VuPgjW*Araq*9OwZW&d2MrWJumbKK;C*FSj8}1#>puZhp{7jDnM0SdmU*%m> z(w&@!?nq1Aee^HWW{qNtopiznLuxDvqEe~BI}Wp9fWBZD;_>U;VwB@)WR}&1t_+ZL zWfa|)fe8FibXG8fx`q?hmoRy95#{js$s_GNv&Z@#1vgivuXJ#zn{4KAzW{NvpckRLtT9Iw*Uk_Q9m)0BJq~uay z`@efRfnD5Yngd|x88A4SAX z{46&UtXa!R{N(xibzA9!vtofmsizh#XI1TL;-Qc03J&tk?HP~;t>h2a`B}eauml0r z%^6m2X*o?ldB#B!Ri66D_vH{8HU^t;=U$9A_97Z$UEU@7{t18K-2K!`B$ z&1TR4I#xOyLkV{a#fA;5+h%_2wp`Wz?Jxf-D;V}8gAB@`53J(pKJ}STx6kt1%Vgqt1}fGwnBjJfyY9NX-AV#o@!>Uk ztJkb;OWDeBe)fbS3qM#3V?UepT0pAZ!Ak!7XUfVA-NUk|myo6d7<~B}8{vC-#(Qk~ z$52rRPjJZn!rPzuMy@Po6@&EQ%OmwC^!62#qRoma0y*ekr`+3rq4Xmcp}ofqOr_P> z!Dj|ygt5-c#6ThZ-ho^E`Ca*+mECr?FGC~ z8&5gGF+8=-@Zjni;1{10Fb)#etiAc>z_P1l-tdMuA z6xR4%d6T}Kbb`}7G~Jmz2;CJ=>VEwFOM-;sCnLn8b@)KE*)jxO`dMdaQvOF=3vk@O z*2lP4_qAe}2sdQm$OUl;@g6kd5-CTt7BQmdQc<{0=8!44%L#>M8I|AKWmD~>on>4d z6*j@%jcEmN_4cdlAQ5ukLp2uT?vfk1wuXv>mM4-CoO03zn4gT*R2k_^Qy`w*%=ZhK z3F@-8GwCFo55g(T3eBit$K6re@~t>R14xAFLZDA&x*1O(eu<)jl-)QwG5A|qIEMvr z{(P6=Esg=!FcC66b(Uv1#yv1SocML9Z(+2Fs@%$5m~?8Xp~Pz;)^y(X@Z~!BtniaA z!dAF}*twpguW*ClbGb6|ehy2~I0`w!F*m+3?F03J!!F7G@~RJE`>%Yyf~P^}MmeXW zV`cyUHPdCG=fCfA8z}usXjWDPAJQM00+DV#FZ~+J8ehtwveyM`h%RV~m^rf6^Uj$1 zfi;P5h_ixAd?L+f6!L1D@;y*lc!9GMmWIaGg`gMg+zux3U{9XuZF+#S@z6Nxo-(4{ z@R&}@h=1XWm`HmdcmNtYDoDbBJic*{wZ40h(c3W6(Qy#E&)!R4%`8>@ci`YbI=;-d z(IK<0Qi(F`Kl{br?PZj?P)Tu zLXxoMj#W}7%p{Hp=Wmd;A~()4PfaM%$+mg4eS?SyE9~ssK{8SY!BwVIq#P)h&!dhG zyr1S4oCOPpLHdDQ!}UD-#?UE4l*cY>6>$_7in!%P`EmBw8@` zrmgUezWt<*7`b)}c@vr7Tk-LsNZH0$_H++|8@_-FEdVO?r>CF^#e9MESdRER;}O!# zvTnR=bKA@wQdjfuL&2Rz$y$t}I?ZhI;BGkz#K z48%C0;lPG_#Luz(I;#lSws^sM6I$$x+4(jNQ3!?i+}Mw>^r}V zS@wrBOTTOPE|%x2%zGa;v;HWo*0U*B<^<`_fzHHdT1%dh7t(w5$kBFe!BOy_oFnI_ zxl7wR$9vM<2k!oN2U+EXX>zZ=^t+nH)gn{ePrr86vfLMM9!!&-g)D(Tyl+#272HQU^w$}Bw-T^MOS zfucN1dAwrF#&(`P0Q>guX&cvXfp^p4y$$kj|JLucANb3!ZdYHuqa8bavF+da6tkP` z!RKH=hEEu9s4{$>fruFfG!D-mXp4>=ZdcsIjCwoNcI|qiU9;l~@*HIzp1U1r7Yg<3 zUh}$k?X^4F!#j7S4nD#;01iSdw{WFQso1+3U{Sm4?z`IG`0*ca-@z&7-~I0If$~M| zAp7h0>^lq}*;c`-jeSo(g(AMR{lkCozp&y1xn}jjSx)``%%?ul{_qbzh>Xs*osaKi zrvLW#-oNyo_APIJYx{RU|8Lr7Km8d+mNNhjwg(@4sIBIIq(DAVT z@k4*N3S|&s05e(-TXZRURvugKXulljS4mYKU8$BqbOuzE(~hfX1FyIT{8ExtL6hkj z>{b4axabYh!iT=fP!&FE@y|MAfU;>r1Zz~&0fe;3QKh?+S{Xk=u zk9EMLn5++wdt}dg<-rFZOr4?3Y+@251FV!a+x_15n{Ef`tn;6W+{Xx zIB|3XxE)!ygRY5y!YsI3zqs~C7n=S(ym79^MZ)&&)LnVf(v2`PNOm!f8)h#DNe5ks$`e2GZzc82|kdx0a48 z_yVYNs0eL9-~dB|u5fmm1Fm$}QdmeJx7#eT@JqOTBiSQ*mY{~zMs16UlKw|atXO6-0Am;+`~BCuzwbL|&RE5Avd{V6cbB!-T6^ua_q+SHp0RBCmk*juOqi56-NXsa0qPpWo81^{tKW<~-3DNbx$Q1kk(}+vXZ~tC8MptcMKp&a8QZL^;#9$-GMx}XYqe>ZhXyGCb z1IwQoius?zcBg_K3^a3KoJ+sqnF&1-!}4r8c1)W_*PONItYujozWaqE<=Rw{p3b}j zcUgVs#2AS+;4Azz(D7t`lvyX_SIwTZ6PTB7D>+Q;F#Fi= z+p?W~q|6d?bt8>2j&f&!g3kOxwg|3UeO_D53dtqhXMS`q_psAIB}&n<-5>|Brp?Ca zLJpu>v0yPBd)f)<)YGx23|b=Hj!Z`8GDfkbwzump=@@{9`dNQ+$@RK@$vhOT78B5)8ii6?KZI7@7`=N&( z$n4!}>e2n&2ft%SU1hhF)uEPoaah-yCeJBRK&Cl2K#{MCZXNsUh1t&xzjAP2zuy`6 zt~=wukNj}&@zi{_2QW#cdMGFBWLImr4fF*0}6*;vG>HEf9~3L%Pr5%wuya*R1+=I&tE6B>?rGt1zUv zm+e`%-29yO#y7sU{qb#o&_3|~_jA*O>E7Eu@$pZ#fAo+3e*544(pwlrp|iVj7d)(N zTejcd7IE<3f++?aP^k=#!nZS!$0;Z)mK|j*=2UyfU-{qLpWks=`}u$Nx7fq{%A8lR zl_k%oNy|_D)ZfY0ge~A@UcVjM#9#r3Q7`2{ztqWa=Mrpjx{Bi0U-?Szljm-Fbm)Gz z>2BS=w|(k={5d+ptSTM-L*(O+|JA?TuDz1&4#eexO8hTq7p*_H-F)M9?K7YLc>B`b zceP*nrJrf<`Zxcjz4}$JXs>zAtB~7X^k_@F5}mpJS}XH!-5^`0SvYP6s*yKfnx-sn4Zzh7kb@KCS|V zaps@5A5Q;GKPG1t*|vg?xRguDpuVl6^jb(jXf(GV7fihJ4Y!RG#Bgu>$H8OM{=+}~ z!=dxz|Ht2GYgzqq;YAm>7ryY8$ja3@2PhBHc3-}AjP1N^ttOW32aV}>^|@jCIk=nr zBTWA4-$Y~OrOx_&lcx*-kghFk!_mK+lACeHem(4|zQ1!F`$`i$B5)F%0iBErApRKr%cJ5YZUxQx1hw!(6tIl2#-3569tZ+cB!qC? zTkiVoRY{?6robqbu%E}61(2i;8vB$Dep5x|tyfQvRQfvmFbxO)CRVccgB!1VI9 zD-noy;Oj}JP3E7nQF!A>eQ-#h$iw##Om#8R$H6OdS5|&-Ci%2E*-h!wAlpe|9l&H$ zRwWb};Ga11h2I2wJ;qtz^3dZ}qm|moIw!J`K(~uxutOVL!t%C4k44XJs-CGd4vd9T z|HO8<;XT20@gxh*+Am6D()!j>=Tn^4Y$w8HW$8o_&uf&j%oZm4U`fith{PGp5i&t= zj$q@P^lr39Bzi<9mV1*;i2wRcMlh7}TSd4ag%in$@?bG;tcK-R_@rlAB~aySCQml( zZA|zPwxi(Nx;pp#Lvd1Gx_dqJ$kg3P#U@NMKRYmBf9e);h4-x){OH< z+Q(_g({*AN(bJ)87MMMMSt2~mrt>54Z0Em>87zk-;rMm5>PE*e7$*A3$F0(2plu7@ z(6JfA%3@%u>_^oSYj_N}rdUe9fWv~taSA?;z{+vnt1jKp<}F>;9(`C()`ALTfG2Ocitint&8p&x>$mF)|6{5jhT z_A+p}lqKZnuowHh)O#M9wVK1SOoko%G{9+hItkMo=#~UUX}Itn%Jy{*lbfQ$?2`3) ztSqrUaUj7{(_Lb(5ofXhyX`;q(}VY_ZOC>_db@@%rZazH33$+@gQQ2gQ`E;U&0oS& z@7!rGKC<})ZQ1Yz>|*L|XXrfy?}Rk*n|6Tdz@B!B{qPIWn{!vMY}=V-UX%{biFW?l zRm@I*x?RC_(YJ8G^h!>jx6`wTW%M`Rcq263TP-n4KLM^7kgn+Pb8*R@~x`M=k`_NfOr{O;EFv;X*Cw2Lpg6nP$N*Iau; zd;AM`qX$gb(V4P7w$o%i?Uo$BRp&6fdd)T0q;q5k?IO0~s%h&lxVXLd4{u|Tg1lbk zpbJ|fOe6g-&&yfF3JBBbZ1q)FU(IR$>)Y#J|2opMjyP`1u#-9uy;(#2l?;k+X&0;m zH}E+?k#caHK|H^urqPa>VO4fZ1LQ-Q`YjP(-1=d8$zERt4ByY@cFi!iCdj?*>?uy&_m@QkD(0)Z~O2}p0r_rbwFGF4b1_Uv_mg# zCv4%FN(K^PO;S2Sugbjfi-xf=L$n|=eoqrY_DlTU2Y&GH-(#cd-*Kf6ljx*=0tf0M z6M?I5KO~T=-*QsB!*Blg-)s**{78HM2miRe$; zL1fR^3Y2Znw#VC*99r^|KmGUHm+!fkS^U$S*10bqA3OhBwm#DCz4MFhs+G&z!G|7h z%PDx%DnE40P^6Z|gd>^qRlJqZMtlx39E-9byHcd^pf%%gQ>k&pnUNYYSf!DkF}o7# zM=r`j`0xN28!m+>kQEkGgRk=GTpE#|8Lh8rN^pUKXHfPK7{wA2Q_3XoDodd)y9Gmc zDdiB>;~={fAWK=tFZF?!yaxZGKhOe3wn9g?>?)`YBa8#gYpAn=V>1^PB}n^ z29cx2juLxvunjWFM_09kmq~^u$px}JW`T@!-TECKDz%lC$S}-}W!|yIn?xzcZkGqk zuh3^0!<3uA{G>YxSB;k9!MHt7jN{LI7RJHg^5e5ZJ>LEO&}Qi|afLG-*74Hn+;p72 z>w_)tl}CdBC0%^RHu)%?C*ch3IFq(X@b8dasX>)r=lyK_p2>hRF=oX-Gd!ZeTX`j2 z$ldoMzUeNBR<1T~G`>Apw%^*|66ZsQm@S#lDfG%6lQQNv$$XDTy}lz)`0PtY#czF~ zN@vD&k>Br=?I`V*!|0C-(J4mN7~@-S72!9&=V5Ux-~OvV{8@LzHE`eQkyZ!$t!q?% z4`;*!T(%?l=jXROvqMDf`XZLa>`7mEk|m@3*}*=_K*0P}%iA#y7duAui*LN1d&Kv& zqX!Og?bx<<{*~9XSHI=^+X9weLy$w$IN6*f=lA}}2ioaF%n(yA?BewDOFZ_Rwp!(b zjaX;I>9A6NxWv^}0!ScFYY{tCZ~#31LzywW+8oxEY_FuO)j@S6$a)q2?Fb!Y5BW6v z^bhO<_tAr#`o5Y$o<`?wC3~X(3J1$EJI!8j@0WHP(PGy8dqteHt8aT7XNu4f`_!jC zPRDac+r4`?2ZZj+>Lhtj-Hsex1>)pOmHS>7$g46h9VJ1L?LzeMFiW^y4!?&b{Hxcj zrlW61vnF!Ln&gT2?8v$j$^+EwIN0{H19gA_AqOVB@#%^U8`^dzo;Dr#r1iRW<0$Q3 z^U-?Qa^P(yQw(yL$8I681L@vx%c^N`AWZo$Wede|256V_b|8YDTb9aSpAZLp zmyWuG|1<~I9pp;L-5kdEAAjRLl&Mqg#V>nR`@I)@tljsuud_^kIadd+Vb*;kaXEp0 z%Py|!JIJKm!nTyv03KRh^P;FAxEC={efwuV((b$O{&p>AAFO6I!6I+cVsPQyb5^xy zU4K=(@7@R7@+IfB58U>Vwqp501`nRwRxpsE9CMf;C+i>JteNLM|E6}$^;d({0h*J< zKPUNj7`P)Gj`*DCJrDi6gjFM7&481G10EjeK$M-s+GDTosw{T!K%=oN^UDmZ0*Q9x ztyME9P2AXxmJY0MgZXI_pZ0WOd8e%7XT70`{>CO$#SCg(#g!Uk7%uB2GN$;dZ+-eL zq~oNkYtn|XpW}bz^eqSCl8%4M5Ty%^Y6D4xEhJoN_tKZYtbPCY ze?RAEe3L^LA8l`c``g>IZn%*xF}vCyzVChQ5BObw?R9O_V;e)$Z8|4U(oY@IoYe%@ zWt1z^Sn`?RNe*<%1I9EY9l*Mp$g+GSE7G{RfwHH5YDV9ViMR=PnvZ9uV?RNBNRM)j zkm0zNcSYI&A`o&a75hmlqWKMpDIaC zy_9Eu^)VQt^0Gnf63&>UtKgEoLFdDGzQAX}@GhAllMRb>)Bvm&hE69q6Y3)v<5ku{ zY4BE|4eu2|fI_e13(7I?LzwV0;)G1mk%k2$A{zWv%8^HiOg;iF!GM&ja0!)|#W<|e zNZ_yV8EPa9;o}(P74He(9zLKN1C4A0uE8z56~n+*EVT^M0D;Ev9e0uIybR%^K-rvd zfMKRfoO75lnFOjw-Nb%YBxAS^f428rkmV=xxkAM>=|5>d8k}LzX!C#Ys`o_*J1LWoh(56EKw?H!n2I7=PT|WU*yq* zG5RV;d?c+Kg!7l#mGDXlrg&>omMeDR2v_MFq}~%&z&*){JEA%8UaW;c;KH9_o#ue6 z^J7qE6v8)4o@tO|sW5PU98WO=;xbV2+Bo+kBilvSG|9#|Z*&H#0<|26L+IcMXf=aWfR zoRvQVt45k7i%}x*w;`#lO~11xE;%-n?Cex0iw-><7iTQ9^qwxV%a9@VxWg)vZ5(##Mvu6jkFFs{FfD`XsaF%F$U%ufB8By8{F2uCk4u<2}t@ zclXshm*umzkA%e9NQlrq{i(Ex711t|?$SJsd2c z6Se5b{tWCvmgB!OUh4k#U3RIy3lsO&;#Fq z&146>B+I}7x8b?U328-cb}HRF?TrANc5)4x2?zG$AN#ZRz2E)1%$#~~*&4PJxJA?k`> zb?gWoJ@Q~N9ppXx9tUnE%iPzrKlt$N?GOI=Puq{a<1O3|K5%5 z-Um0egWOIv&FYWi=%oCQuC)dxgHhz^Y4T|QA+~#QIN?wJgI{WY@iotHuX@>w+PU0j zb>h@C*Udec6=W>GZTCO2scqiI83^F>dtsN;tt07_;y6hk;T11?d0T(c1q|p=k5EUb z@fM4dTywYeaXMjiRJXA2-`gAh>|>v7k3I5WRyV9a@0@nk<(IdI9=tCH2rfpR4i|W< z#WZ{Q-CE(m%;C)(#O(k$d43Mt87{m0Qe?cJfjqVrY~`R?h^ZTAGloR3%)hh2&GL^9 z;+L|YT<+Kni7?}#D{{?y_{IfSFj$Eg!jCuui@wsVL@uf8oSg1j1ur zWLC7487C?H{x4a~KrsWa*)BoQar}Bb!>w1nmfQ}t=cKJ)w=P>lBzy_mX5RFsH)qR@ zWo`{+?7n;NO?yfl*1OiR^$jDB{R3zEVe)7LP(}x19Qib!b*C#QR-Wb!s!W(uw{DvDxE8@&8@sDF6#NQ_c?Gs6*AGtbPZ#-aqwoMGgM zjFgJ;yG5&R#nMf12gtCZlPEkuF*Za>G~fLCwMhkF;VRrwFg#PJRW?ePcssA%o_HV> zt8v4V?%*fXw?KJI6RV2sUj^`%Q(^qqGXcB`uDitV5pb(Vrk;3ApDmf?Db#aA`3!fS%}LyKpTf)R1=Z#o|cZhaCR4ONp#a?)%~pR zFrALL%m%YtyB}r4tgm$|3uWc65L*^NHsCef0cXR6>3F4Ke9e#~eFl4HCc#hYQK))i zo>Y`?4@go;r}7!-!nU#=xz9pjQU+&$fU1^rs)?n8cHSI7+wbfp4QPLc_A_dr2+iuy z`0cXOA03^M(M3s4pSpC<;Bsz{3B;z+ueY6QulAbefI3?g2bn3=y);*`5rGbetMN!6 z(AANRZb%gJbse;#T=04cZz`lu+M{3^;ou zIM;2`5wbqoN5}HZU%G>n@Rzpdvp@L=ZKEkVGOmX7umIKiD38-8xiw?c)^?EV!Y*BP zPMbPJR~`D(Sv5ejY8deHrVR&Y_Uvb0IERbnG<>>Xrp#;lZ1j3MdbR0>a$_1Se3oo@Vy_($&jY3jXQ#*0=lsjq5k1v$kQw20B?M+GlUSJ)Qgm46Jyvy2f<^ zn;zfPKJ=jvu|N7~4pz32emz?^r{TeS*Z0zXbOzo0$m#bs{)fV9HfW90huM<6>2+QW zfZ9%VhBku=@H}}Igq?lOHg0bE>}PLJ=iTMvD?P6O9pAovi%8o|&%TL63%9e9U>Ei9 zk~H$e6Y=HCRS1%|K2}!qS%IN6oh^Ul;YZsVmWaCw!h`$vvKQQ~0;^Z8C5=aNMc)4X z#AlGj-xPZkmazx@7k}kf+fV%HkF^)Q;k#LKzP_zre+erO4!4&qcwRcqX_HeIy6k;E z@;c5|jsu6uOO~^*Sk4t-$5*#^|IY30(hDERjQ>#w6qse-#_avxLo7{ZE5?-RClA#< z+YluHZX#_-H%Cx9T7( zccvLA@xadV3eO*C{FO(!M29Y zo40b<-{ZM@+re*7^tV1TPr8X7kuFVih?3b&*Rdg>d*_|~>DWr$s_Ym1M0plc03XUW zdRg_f-cmA7ucreFtaU^T9@VK9KP827?03(@#!;|gdAWl+wNed4DI+Ht$SPdK56uwL z5r45KdZwDcy_mtP z?9z0w%`+^lbC1|RbI%Tdwe{u%2V!2_Zu{Ve+MD0}=636gUfiy~;RY*c4pe+3W$_60 zyMsoLKmK^G2Xz4N$dNktC3Q5|($<5Pdaqvivu)sDK_!Y;2`Bs(JhEm>hy!yQAA2l3 z^$8dGbO5(xHl#6W1MJ%{&uGU!=?OC>Y#VF}#GJFEX(lL;G^EH(M^+qR_G9Hp+%ZPm zj&Vxp0+tz_U?0?@pTDC$axbTcu3XE&49k0%q2KZ7BW=rr_qVlF@+&A@=TjM+rouaP z{9s!_C1^%5d>-kFe@dZso{Fupf}BNgR_M;?z%+4*-33j2?N%&@8F5WINLL?qv9Jgr zxEU(=IC30uD~S{s0M*fMMwJ2{W8EEyLr0qpPt*zwxDzzIv1i1`H(@rCqAa*Afbwd1 zqNFj>3HJso?(T)9TYbxmyyY(e*oJ^OlK}nXN;DOoI0HZ^7sG*`>tVca-xTdJo}_r} zoUnCz{XNbrec&aD9K9xDYMmSJsDK)7dWSTZbsQ(Qgqh~C|12Wk0cX)OX?Coo{ggP6 zRUrdjrCVJOPLz@F*basGytnTv=U>$75f~Iq)Gq5;)l>WbXNL0 z@4mZ{Hyev-IMXOL$a>5)+Awjj(#DE$?C9tIUFzO0RN*VHlqD1;Ybrvb>TlWV?oPMf z6{qtZ=t2-#mYfF|@!1Ge|9DqzCYBH?bP^iby4`T=t8v{b-r&wV)O)nN6O(A>ryu-E zQi-0ru(VJeR}Xc4M`g)NJXU+dm1aI z6S>$?FX`9wiKrz`I-icOGaHZH@6IYZJT95Evt=j6c7aQqGvGwH#^sI9*yr0hlqdb8 z|B!!j92n!No8S&j^R{St?U+2vlQVq_=m|JMaGcH}I|k_x*|9+fs0)tKNp^Yj0vnS< zonRR-Y3fMo+99364w1+{-*dm+rAOZ73`&vmrV~#b-+0uIz=R8faUo!C@1R2@j`XqM z?@{)UE?&GU9hHMuTtTPYE6ExYBP=l{&d$Shpy))dT0;9}*GBex)A1D{b;L0mp!-?+ zZQ{Zs5q;aSbr0%-m8;q6Lr0XKGxn!xFDWz!N;BwS+Cb$mWmCME^7UPI8~dlZ3w$k0 z-FNKR!XE5@-ro7Qf1({Zw4bZu9?R1CJMO$Ia@|Qs*1FAsqQfll-nn~cyY#Y4+kM}7 zq}_Sfo#>hC53JXYa=Q6;mbP<45|q*zC!d@(vz(W{!&#UcdKAd5xbj(c;dN!{JTv&U zdcuJWwlUGEb^pEi9H2S~tz%xx2Y)Wz-@R*RmUTaH|NZHdx^#R6gCWimS`SM?KC0fa zym?xIvaW;T=5cPqE^xR9c((bwKmB(pLx&l-IgqU_-V%U-z(t$O^B0?4Msay@UaR z#cem8_@i{ZJ!fM6UIw^W?X`r#pQGrPb)=mj<#5bzig&uJy9^SXjuNs(WXW32eL(im zT*L~I4IH+oZryRuBdoI6(pG1c1A~670GY=C)G-DZj(UE;DsQ{uh5(!K#Ff@g(z0Rs zW$oVk9%#S!-rvg=u7C4y{+}FpcP%nr!4e^(PYfa{^03MkWdc(;m`(==!NMr zE5b1{CWT?kNXn{0OpSGN^|9Wj+D^m?`Kg>X{*|`wZd5Rhqqy!Dbl;V@?C6_$M61k>G5|Qh8%KH?G1&MC{e&Zx z0WR-u5A--*j~^mbLh5gEr_vShsDR)RS=BjZ?craHN1JdY&A{2`Cdb znH=0BEx|v7QqlrUddkMX*`{=@bZ>Upq`UC=6kok3!zb;*iHFqcgAKg@#48>xN5xBc zBFqkkFyV3tvtFo_9asq`ZAGs?^&Z=aKg-NW1Htl@e|emhzV5aGBi~}H z*;2{?k3ew0Ik48P9(d&kSGm^=Y3*;ePWBFaKX`szJFa3URI!S&ra`RSU`<$ES(V9+f)DAq6PoP$Zidk~m9DV}~ntNKapGb&HgNoR*nLQlW^ zgsv=8KX)GHqWx|84f5`EO?BET-m8w?w#U+C93Yojo&*7kIG6tmZJkk)Bhz6OYb3EVEyIBfP<8mGo zAeKXy7_U9&yta=<>NoHCMq38X)pW{tZoZ!-`J3tdGPrWYPAVtCubpZaa}v4r#3?#v zQ*=;0D3HvE3><*5Q@W5t);Qyxc9naeE#qLYIMQBw(WUrJwHt1HcCH-zZ@=~1?Q7q>zg@zt^99S7W`DgD#NmvW9XHGF)-BuU zTpnf#^?4k`TzlSgZi52CI1r;A=8(hi2Cp)sofMRjPk-ttsUqzf@z;!6&2XAZJF^xpQ{@ zPyY1J+I2TPr@i*|ug#T=a{9<)d)mbpUzEY8!_Zy^O;5!qij(e{wTHnrP5XO_6%;mu z4g%*Pic|WrwIecz9!*bX%bDe8AjA69bh&(e3jJ#y(h9!QbXXjm;QA}RGlqdDgI^8? zEN{zJ(N+idUe0uw&mo2LxM^ZOg9(hIAqzT!tovu2Dyw8HIqnDF#$e5Q(s1czmoww~ zeaOfa56kF~eYJh_n-7yGbX?KT!-x0hn#2>7pPd}sH_iLhi6aaWSRavgw$pt58~3zF z9(=IPr8T}l>;#Pn0PrV?0KmCP~r#7PEofGT_ z9_7<|$GXk-LYM%wI_Bnm@zve74O52?7}Ya%Ap^eXt0u6)VT$Tk^;&|52UO8jIA zg8D`d#`pR>c?*B|WkOg$jcr z(@Xk(RVyePGgV+5<<(etG+j2nMK3@35c(k{&67rcqO<`XGp94W^R7ZuSV2{WcP|(z z07-)dW$-s%AeEOql`FLLFLY5t{ZwK-Q^1D65v(DB_fd+C1yhB#!gNc#(^Vc8&cVME z)H&M>yv+7Kt9t@|#MWHE1ctXt`WQm@1dh&hbyOzPS7}jpBe{>Ulx+xz+)X?t`BI@e z2H)=S?Y&E!GkJ`jRKT3btHElCEPYjXX9-}=cu(x95G&2XTG^(6;WemJf`zcsP4S?N z={9EZUGclF^*6zhUEcj6()=6y?55)=%)oU8#Up9&0pcP|-pn&Q>~I+x)=z?kk`El_ zq_T9@EM;=U!jQ*oQ%{D5ZWG zDmndXHrk1~-l3OLQdP7<8*6aq5qknh0vNG1gbi>C#rP9W9mO{~+UZQlrKh37NfUP)UI`BNT|+mIYz$vNWqp`Omicp`AZ z+IfR5i134t;2L>M0FSH#qa*j3mdL@h4ze2K1hz*HjWgpu8J{j&I|bfWqY2ucCpcUd zte*JG%twkqC)$~qo0|Mu7DoAs#c#CLq${0% zWf6oRP(SPdPcj0mG@_5%(Mj7&Cu!FlX9=y#gWV3GF7~ZHHGxn%E>223aE8FxFC6u{(}G9xTHU^*?E2Jjy}9;M#FMi1+% zbUg6*_V$+VepUN{x4yOQ-m$s;(UmJfX?()S6#*Z@7vPGwLRyV02=F9Wx1VBsjCePTLh2M^~lL(<_rp9 z&uRNkUZEo{|GxO*o7xLr@PZ6x{NgYDQoF%x*f0+~_+V}XNL@}m5BfU>UhDm(E0(p* zk8W%~_BVg3z3ngmB@T+ag|auVefIO8Z;x(#q}_1Cm88d6cG}P6wfm|K-+z$h!0dZJ z%?!S6@_7vQxO6z}TzE>mjl7Bs(freN`j4Y0C(u(wl60Drln6wNK9FvOb%aT}X=Xu< zc*1S6>L>b)iUSFKI$5f)XH_hqbMN7S>apiO^z-<@sH~%2p8uqcRVh050w+)wH!J&aW@T)5h-PUqCX@yyIM?FYpn`RZP z{&f-Xtxe)8HRDje5(9zsZ;Vt|@ksbUN8rE$Yy>d+RF^}BVDnu6+S1`l zKJ%&Ssnos1SD%Da7qzENVJyoMzpk?>&-kl5Ri<%Z!jg|r=S3cCq+|RAT$5P?xqA95 zya6!L7;&c#gon<1CQXPRw1)EwFM*9BrB2G$LbhJGYQ|d*q?uJTEUmJPNZ}CMUar38 z>h}Ns!+(&2HsAHH{}qRCzOB8GW%=HQ@Lzx9zqT)OAiG-^y~5J62$|rrBVYX0z=rnZ zlYIM!?0dVhY8L_`6hrZ0z|2gxoC=q%H@qDLG+*YkLM4fmQRCG^%hNK?NXNb^NLWe! z@F2zIS05WbQ`{TO%(fkIPN`3>Q}&ONAX;3M5tfG-O(~)gR)F&nfO9xUwsTUx9|0`LAW!pH$Y`6xk{*QNRW8fGodUurU`7iVHFUYz6!_d@V>2cnKFD~Woo9|J z!1?Zh^CM(S zueecyRB)sfe`$6T5eOM{L&bq-hlxT3xO}>TRbef770&cXuk8J;kNoE~Jn$RbQZcMX z)vyGx{Ki0mic{J(01$TTF#~sz5Kbd69jN?@AN|BSrn;ZGee?8s+tI6h1tFzK>=*E7AEX zk%^@n)70bOAC@hj1H|wuRuecxG+^wOw@IT@nfbx=qnty?s5k4Q?8mrhxD3q(svi?) zPK9-Fu|7m%>@+|qQW&uw)i-tWBwhS9kvjl!&JkWfg?DtjL_8~YC`*ZfZg)%jNLMp*GGS7JnUm;d7(3r@`Q{|9N*b?Y~9Tu5W2)K18btn9~O8( zqex+;LH5OE`RhhlIkmjn;BYqeG(RCu(Uv$#`(lbC?w6ig%%lf1sJPv#NCpMPBHKN7 zf{4ES+|_Lfd%d^s+t^mn;#tV)_L4fxZ~ZmTY8x(I-@fqa&(W^pO1V>95y$GsMXpL< z&>|BP%w8@O*I^#+&$XilUpWb1oq&E=hnRB9pL~-h=|_2o^vJ&{^Dph4w5Ig&;7(+~ zb%8F0-u2ms+6(`mpKKRid|vyv|K=CzU_IV$|Lj-V9iRQv_SUz*t=;~GJKL8Y+DQFH zTy$47&Xk{KHum^wRvx&zAy@vPG=iHy_6?XSv+I46Kg&= zm?EzS4{=-5;p6PfJ(s=QYjb_5%Vv+#LG%jI`K&TMaBxq1-Rpm_t>j9*haP&QU3>j? zY&ls;XMY__ZI?3$!D;{0yUx@rt0Ux@-#kyqKlj{o;^%DlBDSHPVpYWAB`eawKf*O^ z-}60h;L7I>p)+Ib7lA-}e=^~9CLoVg$zy5t^z3VYHq zB+7&(Pf{)-K==ozdc~_8z6Kd2aq%U*!&jhC!4(8?`TbF$6Fu+3iPi5Y@#{NOB~Cdz zkXZE=aR`r`hwozNF@xTOsY_lXZhalSDh5K?^aegIsn%e*tD`Mfy;F-|2pQ;GNu;9i z&9`i*t5Wy&FyBeH^+WZA?E9%hky+qW&BD?98ezkD{7{qV%3=m+<}X4%80*mmtTf3W z6@x^s3OUYT+4h~=+6%ZfV)Yv8M+SbZ9K8O{LD2K~{q3LliT10%`YY|8d+te{Efx7O=UI8#=ri#$8RLp1#kT1S`|!>yxu1Xqv$ zRNv1~$9~{rHgytKC*CqjWR@#|)V93I$oYixnPT?6I?)kcm3)#$@)RbrNkvS>l@32q z7kO|8AKk;8h`GQH{W&Xg->4OLEw?hy(GKuajVq=oLEQ;knU9B_W5%@(!c;klUEz5r zdKD7fePqUY_sF}v_XJR_5|K*YCylAmRwz{*DxxWPKOd))G!c*1!7 z1(3%;cl1)xCg5W&2EvCA=^=anOhc#D!{d*4?;x31MMhZuCBSFmog7TL5n6%Dr3{!rA z>4baWQ+yYjGnwuDB#$~i=%1aG%!xyuj4%_QK2OT@G#VYdvsTXL*x1!LTW1HVW?B5` zC@1v2NY}gLNQ{Zc;GZ-B9}e@FfWg{jTH)qo8FjD1ta|9cAq>l#;d$fk@=D&on;)a- zJ22_w0bCuy!ezarz>2jlJ6*lxmt78&ePlb437tDT6EPEEgNHH8I#3y79C)&RgV(@8 zzz=y(tFkq1rd!k{yGo}yl5`GXMI=B2qa&YcbU-3$(3?2j$lV#8{~<8x6J^|$+Of3o z48o3>_XsU91{%hdPxCb134H!_|QQTYlF-auJt_1e$wbd`b9M} zYQEa3cbRNtR*{3T>rFX$%3fZjKOMCA3Dn$=62uu{rm0K`APpG(NP~?wbhW;fNUo6pF{i8f>xVe-z%O#;%`Z61> zc{0#2pZMkqS32pSlS`ndvxnQmjr4a$a~I2#UE+F_CB4d1y2gtvg03{hppkzUbg}TX zpW-{iKvS~4KC)5f_mEfg%s6!(fU}(B3DD}vA|@9WGwEPkW!wlHaD~p$u^&jPOGSrg za6>dYIrKcHum~sg{Uek0;7a`LN z;A@w8xO8D#&eGG%o^x}%`G#k=X|DYG(igwnR;-_HYv{l*E5cM3oq0OL3utiKkzWYi zY3gY*Gx=wo?KN_4Lztqo@1LnixiB@PDL#1{xQlS=^oq(Worz3e;3lZU-{xo z+U>W0roH4Pw{V~R%i3@M)_=S&a5*);Ds^k;n_6n~_cKP^WI{3RdwciqpHSD=J9sYDLTegZpf&(=2IqVb| zavdEz$@vJI+QvJs)JbBHRZy>H%wPMHmY5BcYk;iKq_2N@ov&UWQRFe_vy)vT*eqgR;RmXP^%kb=Rw*iM&ibvtFL%Yyd^d@m;5 zTqjBUncenTp3e-MY6y)b?cxhIFnDpSz4yJJYWHp2)1GtfC2b{#>K$glt6S=_7}hJb?v|W=l|O7 z_`+S}B`Yc9nSqUytS(r{3G4D>k{sxCa4oexGOPhO>jrd>{PL$9vIpLLF;f0{bfaob zIQ8!OR^_MzPQ2B}8F30phxgro;u6%d+4I8u?w!j~xWO^KTvXZBOI+4@U=5y-4t&81 zBYs;L;`Ic2-Qt$jGQiH@**NM`6jdU{v%mr-ZkMG4>tr_n(nvb^UU-dXf!8~2oWU<0 z;pm4t=uciLKPoYHzc&s{Ekx(maJAt#@4c795jVE$uD`zh%+LG`o%~hp?l0fX4HOp# z?!pT$Xpe9{$Gar$+Mps;GmG#WU)@YIpUPMFNH2e}GjMkEsyZ#QFG_{Qmb01NFD z1~Re)4IcsQKL{X?v zkVujfm$5~kn7mUt>YnkFZ+^(CWY7`SJ82tvm3&NhI``7{FKm{*(ohMhhG(Ur`}h1y zBpI17x(b!JW}B)+M!quuI-VJxBha&1dU_+v0QIy~4B4BR{*DPcl1kuU??Dsq;2jW* zXc<1FTR*Kl<5#Jed=8+JkY0?If*CxX+-ns73BZMW0$6!bU!r%~hx9xF<|i54)8F%Z zoYrEEC;yi4UPdPAE6Zq4z|7Br?;14;+ZpQRN0`a*K6)HD@PH|mt9tFMTfq);81f|a zQF1F`!y_jV*ir$;s;xRWVoOr;oJ=KLBrJ~t8?05YnWP>w0mCENU>MPT^>lR@XP7#S zb%6~=2RQ9$$g6H+)?X0RM=IDRcnVa7^Bm+ba5V5+EDk9N(H>p^V>v?&ufksT;z7*# z6Xs{Y@We!}=^ui#FNF>q06o3Fg$?}pk-V7ldqG_5;9hq|7U;8g5hpHj(s2Vv|Cn}u zyPW!ry|ibTN(lUx9#*{KX9nE2?Eoif(D>~`~9;hMc%r}f;MZ_cb@EghyKh5n@T6j>U^TBT?FWlyf4I;}=4PeyFs(Kr8#QmRRx^6j_o9{45&c19qaq5&abSLR#JGf$F z(uV3{8vhrpKfkR%Z#8HCFdIX=z=oRXE-711Y5*~^82m}{AVbq=ej^w4mUouI@8@bg zX6%#y%=)^&{p0}}fO~*t)uYQgZ8E0xpc5xuQV)M_V_ZN_Z~lS9Z5`L8E#S`jWmjL` zrkJH)|J)nfqGc=EH#m&W)9tUlY2Ng(C%8PIL@Bpme{k`974?XZOu=Txg zAncrT&&@2nax+hJWgaVJ`m$%x=KwsftXs}(vIAb;OMjG!s)d{pFwIKPfBzr;J%_w) zWHj62>r^zH~NR=vmF+4`fjtv#&H)9n|~x!<>c7l+e5z~mRR%fwu< zbh=%1-m12o#Ze! z^Uiy>IJp13R;MC!ug*(_PI(5YSI4(dszA5N{fRGupDf!f9)&V zEib&Ok!<=Fq>taTuDP~dedXotBOiG`S0X;x{@(xnp7zdnzO%jd)vs!A|G~e6t{vfw zgwJyo*%h4a4*KIkBD>X%^o z?r9xGQEKWee(F{HMLYlu@j8B4N?buE4dDG-lJaRdafKc6jsx|Hv3zJ9;R?Qj7a(y6 z?CB_ZfYQIt18{wyw^CtD{fas9hZiVCXSzFeVAX?BB_qjaIMPu@+B50*_KlF%-WVPZ zN>76`E2zNZDx1|@pZO?fC;Zy4{aX96zwy`Gb=O^+y5dWB-`zg^p%1t7D7TMu?V*F` z)n*c>9G58@&q_-7HudqV!FH|6!$F^+-9g!#kAk}ft2+4F_#-WYSc0o&^(hF?fKl(C z5i?3Y7VSwpIaK$X`jOzk4nF_{Is%g)8b#TzLY^2VmqKNDB|W&@p5TY9H)s@~W+4@f zAK6{*Z*qi<(?S=~$knJc46rKVU>gq3o$;86Kf@nKf+~D=$_!LLB7Z<9`6}60n0E1qCG43GgDGpd^Blq=b37vXk^IN; zdi+k*XvN0_OyZ9qpQdG;D$_Br_cU=$L>r@>@GNW5QMTk8G(8l_O5TQqZX1VIn0C0V z^wf1{KQungCuJdQ{CG$A4Z}W$5vbtfIU%|+Tu_LyEIc#oD@}!A9D+K2EGeS`kLc?N z?jq1fij5Py;Q*xL6`semk`O{iK9l&3H3UrZC$_oFAdV3--8LADck3e>^J(DX$3a^9 z8*Y8+tYSvBc_+Oi0<$T1PAjc~bvbA^`XCG~m9BxYkqq_6FQhZVn;SMF0u1nY!RmY!t zeqcqv-r$L!9wRdWH1c~o7P$pi(3x%)D^pfhF_X7q#qylA?fzmr6V5Ez5l}XrFXbOO zlrUy7Akvw}xaLjB852P+VRp*vv^>nGcb41&V3-|-f*tS}Umr6-)7@Gr+s02Gse{x3 z_9FJ|-Pg|LkRrp(hh?m8>ob`q#xi92RBxU67~u|q@9d+Oqe_lxLca!HJjiYuxsN*a zG#;(9oN1mvMO$UQ+wPpPb7LO^{&Zj>8(fhy*yhul>GoJ4B(3@xtNzmJp|P`aC7nPH zB0GMZtuxcmApS{a?2pVlLLKVfPvgp`jYS-E!j<0wWb6LY)6BjuU>o8&)&h9iHf% z4H1H)0x9IARX;p@39HMx$Ihd?cA4Nk@Ln=F1@G=Nf9^Gxv>*M+pK1T!zxr7^T(4}~ zw{2@5{_vl)FMai^?HDTx_Q9j)Cs}6svZTJtzzg~o1C6dfx~(BlB}^VFrj8mwaV9PK z3zR?+CHYA`;8k^&GY`3P*4^vq9(rg$?K?Z%>UQa>SFbH+x%u8b`_N}rwU7^9o2D*F z$uvE-aU-+D&h%I3HOr0R)0GAL_U+FKPdoI=YbhOi=FUmOqUPV{K6iV&_ujkPnza|x zxqp~#3YP?KKZ8C;+28Kr%_rzAcrc(@u>k%~u$toPtFCCTe)Y?^#%*6tvA5iL68FB_ zK5OEWRF~f?Hg$UmX|{{NMfDZew`h;jQiKk8myHxoha8Eo;juC+ip#I&qq<7i=q- zq66jG0Ena=g&*&rUyQyiasZB1A8u{f{f*7-S=T?0@4^D|_Aq)d#i4m?I7IEa$a!0P zm@5XYgLbl1dmpp=Ze2UX@_h47Q{@he`3!FJuD0W;Kjb{g7!M8uqo3f&t2CoP@(RfJT3OSFAkM@T`c9i$~z<9WP`DDiJ4t%TIS~@h^P1u>^Jq>T$w4=}wz0z*T>B zPJ9nZDIRfKhT;hwzd%K9L@5+>NzXQ)rpqIaJO(BO(i-NZRlg2rxi?=X`7lE27GO(` zJ&({i^2Md@dnqrjg34+ZVtZ}pr#|(m_TfMKXuE|oEUvt=4!ivP=RVt(0&h82*Bls- zUM3mB#3VmGtptSU0H7n(k4VC8=kggn5X3D_@PBfULB4VDY<)I?DQPH7-~RI%>DZ65 za%34Z=2HCA2$tbLgw1S&A0mFIS+a9NW#>)V&gh!+N>;?w4>@U-SXr)bW~WL*Fn%Je z%!rwS|C<`VHPHU^&E~ebN+AFQCbv9uY8=-ce>NX7@%d zUCI^!qwp{jOBqd{o&)Xx;6qv|`gp^S1&CmkQMbnDJO(AoHFy{>#P4v$PVrf^s{ops z4&Ez=cntmnneu{4LF1I45g%nAjq;74r6tE5oXzmAAA!?yS2Z2 z3`Y?{ZgxNcRNBK~j{)w=-Adco`%D`+2c83KN^#Ff27<2CPR5?_>3J+%hn;vEOPt2A zg3cRzVKB}>50CC=oF`*IcZL}CnZZAZX1nLY9b5yS#fb7Qjz;i0=gtNoXTs|CPkpK= z*e4kQe8j&H=JOmznNH?SKsyuS;IEtHUBb$*hv}b>gC8SIl@US*+~I>L!sP>kN0v;9 z+kf1CoP28nCob8h-l2HM48e)hSxf+UyVwNn_KNjnp97J^w$4$fYW0vZ&i=Tp&2$FC z1C^+IhYzBw6v6=vhPDsTSr_SVw#fS=ZQsb;zT?u=jv(}exlp4>wUHhe&y+YxNU zETTcgfsOU9MED>)XiPucsbJ+#aY*1?@S+HUUiKEO3-cGVxg`>wX0d&;Nw?&ds& zLv1A;CYqbMD?FnC3abssE0?`jnJ&7MFXn0oBac21sAKBN|U2tyX>mc3*;JxUgYnZj)f*)H}m_>9@WjEL9 zZQ8WGEm}_bq0B-cbv&P-wv|)hZ@&5Z_SPSKD}zHdD{s0UeRw0Q9=0WI=E4*@>|1;b z&?T3jpTphmUJbSzo~~H8mX3(sY6c-#9q=cg`)0eI6&@?Nvhw(8Cb8%MIk^>CTE5j@ zaM`}C_6<6PF3n@6-qj?VckXRF7|6KghD&oO*Y;QVtrKjMzN z=(ulauXy=)v67cP{G?NTldo^Gwd2*VdUbozOP1Wu`Hk(f?EQCu!K?Z_aLrkI zx7OOBcW~3eos$fxRb5F#X|D4ff0TJ7OO=M zxI7ZozM=6_S;R;B1FrBQX5&eVpG6?1;6^SZfyXvP1qW-&mvuqn`lOuK4E#WcctJfx z6H*4^Dn@nfQq&lcu@W{bFVkDPu zor5oKnYsAVE85Tf(|_7_@7>e>!+-qs_Pg(WZ~F!__HTQ~JF)`&p@$!8=dffygEipx zZ(v=_gNZM8)7|+oNb06TLGTYha%7$8_uIP4uqg^_@<%>XHyU>!lLVCe+j%}C9s8LK zR0bx!K4jdEIEku+`jI1X2rc>}Oyr?Jz~qcL0y)mlCg+s#EkKCK15s2mzO_+Um;KDA zlA7itloM7@khzSyMno{DeOWd-hzNQ%l2a zta!Jm_m#pn4Q%(Gj7=3XD?J(qX685uJFXNy3K{;w_MZ%gGu|-~kT8{o?j4SKB;EvW z!}FW)(<*!~G`=T)ez4`Qhnw;Wk7xKT{%5B`Uhxxo%s9N;lN8S5U{4^5Dm7$a+gE9bT-D8~-Sr7_3 zami2T$*}N|Fr&_@SH6{;MvM-Ep5&p2je|yV9b2mIbZ?Jvm{&;$ZsYWhsU%95JXv{BX5kL9ywVwOJ1W-OWoT^EsFXo50Kc+Q$h^!(CA05HB;t?1- z^UkVu8QO74=a3GEs|9jR6|>Lklr)rwx{?3Nj-nYl%6;$z#H|nIw#*X-Ee8qg^m^Eq z9iM}T+(rkwG%SNTZXcEZBj<=m^G62!Oa6>OzCBySW+T_eAZZ@l8EgQvC*m(<3BKn6 zc=)e(rmKwd;NDvzGAmiN8OPqRmOJ{`v?^6w-%z8v^N%#t4X;vH@A z>T}vn90KRQaQ94~M&D1%c?yYEzapmQmX@ zY51q?SJ`zL`yOUHm*v33$|*aMG2-H9nYF>|sejw{>~C-Tfj72WZhdLH|GxX$w#^&q z)LzuS@B6N19fBW}k4E=Xygji~zLA_L`(lMvQnWf{T#|~Nc-K$&B@>e<|&&7wl zhbKQdEaleU*;!W#Jov!B;ivu06l~@^Ah=o%*HihkxX+Wm)+_+NFLIo_*tW z`Q}>735(d!N#1no=bz$`KN7KE$-H*{y7M@7{`u|sH{SrQT9NwFkA9+k^pkgS!aV~? zTrqc;rTGWg8sY?(SB%X=2c!4M)Xw~Lbd*&Lq~{vD_0N%H)$ zO^>$E{*N!TcmKEB;ApB{#^H7+PB}Avv@K^FiTQ1NSb2CO!jdJ^z+A!p_^S#lFlfBttd zh;a#Y$WzL|3a)^3m4@F>S1fsm*_Et%Shac?_3w_{d~l2<{}yNUwXZZp=+R-nA?CfZ zIz>LxA+A4@T%0}Mp!Z9PhzWhZ*rJ!*hO z&mbBeM$kypSJCdBOI*=Sv?676cm&Q^mY0-y-loR7O*$H1@>Hpmop=-t<5HKzKv&Y8 z6D{&$e7|Q25Jpdo?>@L-`AfP1!it>-;U0LINf_MXwNAB;w*093>W?$#`{>LsTecKE zxQ<&Q9?JmLUwG4-+CTn>|FFIA1-G;nJ)ILNsro?~ z3WJgs?{egr1K&i-Nv&wJ+l{`2cPC&5*#z>Lc|0>6`^tlfG!7n=20xDT?0{40+4x$B zpfytne;yyo1qjYUbA-KPhpAW(Fv53~OgK#eJ&tgu$eei;9`CKR6Yp0>!FkAwI9x8| zlAo1~Y98ZIq{V)nphIthip7Q-9|39QLuG8<49Co)hMi! zT^%L1^42(V?C4@X0AMy_qoBM^d+#hni3ztHr(+`pVD!gQbd;M;-Ztd?i?RWSb13V^ zAw(FJ+5n)^@sGaS^i@%5#KV`4@pc8Y^MV3Sl9z(0J4el^K;2t3u;NuQJ z=$NMPB4+q6Ss6aSRG=h)oA4{2(X--p=NL{N!{-QJhw&}kz^8DNK@;}iHt}aQ6JZl@ zBbf~Gbay!?Mu$Bc;j_}48Bpn)iKJ+Ena_lu+f}@EDHP6v1j`vw&h!~T444o{rMLVF zPsNnK$Rp7PKWl0T7w-c;UL%=xc@078&TQUBd}C2vbjwaY7^xP7a;*vSqopG8Sjz>p!Groa_o6*nGlQC2NQcKK{XJv;mI}X_ja3Sx2Qf;J~PN8scsybYe+G58J81`?8( zu^YMPV|k1)Q=e4irtjZf=o z{jH-pnJf66^{I}$gk9o1)S1V5iUH~;0%XnqDhYT8e3Yj~sAPPnng~|X4_<93NoYmN^4wb7G=rb@F!9jMkQKRj+GcW9!5Z#@ z_D*@_8NEdhlxOlvWXe1`?K1qS_UQea+mHX%x3nv+x~l#9ul;iS(%pBq&wu9b_VG{N z*1ng9_vb%;{=FWrBCn9j55TfJsAy0I`5KXwMqM?3j0 zlXsvl4SC{aO;XPH46bV%8r;7o_qS#&_B8CW`S;9xp28#Y|Q zfDiDE!|oW+aK)H)-8}T{#n;~4e(qoXE~^gqx7WVz)f|MmJNLFf_~;|;g)jcD$SdCl zzK5>Xm`A66(R^;FVEe^YS6$kk^W3Z3s)bxFw=n z_t7Dm$AOW^nKSf=$E^g49Bgm_FI;iQHkBP)H?qWiVSDG_dRx2sre`tmgt{K(s>OW| zx5ePS;ra{Ot+)JeyOsU$@A;iSY@fUPn`}3@Jo#{n{qk(wC#|m3V4#-S&ToGGp7w`- z_+AcJd=ZBUz7&0g8ajIE#VgzEU-P>5*rPkzH}1WcykT(Vl6CD9pZFitCrjG<_Uz)W zdR7Y4uUNTa5qUY?Uj3SvBJbt&MHaCo!0RiSx95<_{hUv*Z{M!=_@>9`-0hG4+VS79 zeJA;AAA~Ido_B#>M@gbBrAz8%3d*48>bE+UpMKV5Dpsi-{>h3&sZOcEltpz^AfME? zIhUa0!Pk5a5}s+3^ma4u7)TTzUDkx+Ag|#^++m?UY6U*

Aq=IT03aiXXyKkCE=A zCy?+bzu`4RQ`Zk@5>GI(5-KJfm9n_yWeB&<%c!C<Xwd7IC(&hDX+NmT~V(1 zi>c}t0*Ftoo4P=rPcgXU_t8Glc`U=k zW11qc2qa!l`(Z2R88c>L3AQp#m-kURT5VV|hC)wG(vEZY>q(Zocn>|Fo3`Y<^=;Yt z>+&HxN+*6H`@p6bu;j-*qeQU*cog^=A!9ERdv+LLY$q9!-nVsYTfm;Ed5p&71Vt4j z*Tguxk;qD24xpqd1&ej$t{jS*PzgIytP)v_Dvp4aLIUEO1_m~1xU|XwWg4B)cL|mm z8iPdzjBJQ&;qeQek7JZmDrG88MN~1BWcDr*r{f44W2O?ZX3;tp-qHlE$Nx%?Z@y8gAH^fnX*dvAs>5Q!cPBKU;CY>S$1T5Mn%xs{EpjZhX8ka#Z z5o|#kk(`Y-a0CAU$xF#{0>M+Y4gwhCnIny7!6|!Bl+v?AeRAFqm{SDbf@-fYXA4aA~$PP1>Dt@P1|Ow)+Pa4O12mqnWn&M-~JP^hN`pB%tb@ z`iNFO6t2ndjW`OU?=q25ckqs^2RS4S`r#hDf^_6BJ_CGcx8Bk<;a4OJP~7T3Xe6Tb zDjg9z7Yk_w_f7_L@R==M#-3Q0S03gxYx7t+c_RzMv5|+3bZI$rFOSykcAJv>22_H9 zf96d(t)NvFsiOxHl}7lW9qB5!Zj`fW=xilFm6N~OW>UX;7;t_KlO*gts`*~>oB+fs zJ)3y~j`KhS1vl~wL*<>)20mq2h8bV-#g%P+m58*`0RzGErF`odz^`iXcn0gb@LI-1%5m>DYl$EqJJUd%Z<#sZcN(O(;&Zq!{d^k$fM+Hdh&)eL-i<=Vo%$J(yL=p{U5Wx~L$`FMbiLfiHwmaN~{E}?__n%CUIUj1v^Kl-_^ zq+XfAvuYe-_dCg+C_SqF+cWc~70nFiYD`Ir(?L{Il))YcFeCH$B*PZrjne zKEA2#-npIeC{_xwlIPjaetvuDi(lEUyXMOFpMUc`?Y57xvSblw4xsA}5Sg#;nLkYj ze#zn$?U4sJwXc5pKe77YrgrW*Ym?`U*`|J6fBpq+%hv52ezuW>G3d5x3EL@-GU$Ci zH%XjiK+M|`PPR{c;uGzjuYHO8%&!a%_fv1$xHXf4D^@zV!VUpeO6}ggGo3EK2brmN z<{X_WokM>x)(s8_on)ZWo`T;WJEYP{8=w5u7{{M_kUC8JV6+7)UK9StQHKfDCS!$1 z9?G9;1qcUxI}$CHOY|DvG|w%$r4&fo*8#+qC(-`s^nsHW@o2Rq;ksFjt-tts!N(Uch%ruG9_J`+q*zV{Zd-)C1BaBbq z@{D%ui;b`cf0c4i;`C!c3Q;6P!`t?hwJo#~UrHPn z4tYQg@TE241}~#$?hB%)?-85r(Eazfd+)fT?PtVuF@jWsbN?$#4IL?Q8ALj_#4f%% zcg1m+rW`xU>nN$Cb5Z2P>G@b`OCi-CSTn|z0@^ixEIceB3TNTKFE~+*Q~jeqz$OCz zXDCetl!A|7!(G7+Vvwf6Cb_8lp;5WZCEl)p@}o1fv;dcM#J~9U!x^~H|JD!bB>s%* z!8r0H2jDszim){inpV`1sI$cx`2#ob-xF7u^dA9DScY`Rr{q$6Pk@|ZePUiDRoE)> zr2PzZb9i(fl-1mP&k^a#ddUoxS&8YXayAe#+MM!yl1vcSG={oq%=e%WcC?1OT*@Vn zo-n*~*UmIdyKY4`v&n&~4<3xPOoY-K7@i$Z|HvB{D^@=cy<>zWJcee+APsdmzi4za zTY7d>eEV1Q#EmNntuzN%zM;ZG%E*3XRt@hCYMrl4 zPJ%}n_>tAvU@(oDrN`fNIYSIJtr=WWH@Yr_E&S7o3Wiya@I1@!X*mZ(ytFC3q;WzY zPSQB7feRa4=Ake}%)NU$y8FqnFhrdJN>W3Ah9{1akNOhvQvzgk0z>S|HXvzWmDQB+ z`G(&E>{Gp9{RNp3mVd8La~62()*aj>y@Li7S4*L*$N6UaTg0;8ZiLs=tNVkQ|Acj~ z9^q{7Vyfay!VK|?+i`&4`eh)3jtCmWz!0aeA79XxF_V5mncL}h5Z`i!(t6Lkae{Kd z>lI$^S5H54z$q0!d;ZL3o3LrHV>wAjh6Nh%X*-6F19m%mzSYl@Ck~{2qd-o>mpc&m z)6tybPGl!GT(&Ph)m;|ygV$~!r4!h60w@dSvHYdn#)X5r(Td^t0l{ z&Jy{zV#TsF@OvHM>H4V?h+uuYWy==YTgZ){aWb5B|}|wzUf{x{xKmi`)JH zh(LG0Lv)IfTP@X=HhD;9D<_2_4jcLV*eiZ&ANqj|U6ndTyEiM3NTxD>?B1R2FTDA} z_WC!x9=-Tj`@jc3!xhi#+F|6O-pRMs`5`)~&*GZ9AN{NEZtwr#A2IXzVfO$3#T?9c z-PKp5QtEl@%)Mu3p_3?%v+8v{_58Mf-{JPR-|^OV154lc?b_USZ01n9 z2foQ3_pi0hEO(yA2g-92?)%35Z8`hvpLOH&+8e+7b&YIp_doC`*9-2ZP0b9sWeNTA z`oV(-jhKcw5yAd z8hK;6ta?|aryiz!sKe>BQ9dmfwkB$dq6)@PJd(H3dv%V#GU|liF}^w2f-m_Q^}r8b z1Mo{6qKV(_GTo#OK}el1-_#K4G8wrB0jLk)Ut<|G?^6~P?%+2N%1a!nkyI*i2dW?v z&p7fap4hRWQ&P5VcA7dWaeSBrXvRo8KV5RcpSn1NR~q1Rs2F>i3@@HKn!?xP)gY(D zic`y!gO(YL2m^JC1s=Kb@XtQ_vG&C~?`*Gm-D^_M+l3YB@Lmlo93CAC5jD<2C_Te~pZQvrv!1o`U5W?bwfb(uR>i z5>hHa!bp*oB2uSt^O3N@g?*akUrRZ)^7Qh>ZR7UM+`6%ddnqq%E0;0z1h{BadS|3o za)8GY4rMt`;oQG_M?0}&d)r6D;20U=616P9LYNL3oOIdKFmf#x@o0J{zg+#PqG4nY zzFdMPZ&9uR1hi#LhoJCeC2a*FoU@K*qN6eHV+uSE6;Hm5W8v2XFa872z#A}~#w1K) zj32?H3

-t3bMAH*TdyOSegMoE{ZSl=2`O{4!%Rt}}u~eEthIHbpA|W6!ZoI%5|$ zTzU))&j_^;OW-M)fuSdiW_ml~xqwH39cc8fN`r8CK0DM1{OMc5;J_O%ZDXFFCfYD; z9(@~}KaHqeSLC|qanSgfE&c(&jiqy00`-blzOsGc3twn=e({Sryd;f8^=J^rh#h4V zU9V2tD11U_@dM5Vm-&}J+;`{N-$ACEL_*2G&2|gG|co?y4hmn+< zAeiw0Xkd7Pt=SMW+;Q}@&VEa)8^R2hKUWEP7r6YL&vJYZK-`)sP5{E{uWRAeuxeyhH4PU-ed)QeVqo z)wczuEbt+(Y!HQib9j)EA6M&P-8RV0GiPPoSMTi0Vn*aW7)yU)>;P!DA+6hi+T=a< z%nVCQ84YP4IGto=hS$?^49TvjCOnDfZ8rFa9%`I*&`0$5T#}II$Dg#FeU4 z#-7xaQ=UmB_9U*@k#|Lsw^)`XYqczkk}OiBHcH${5DT&Izyt8!!~A~#bNhSW13`+E z=yE3M_r81kcAq|d`t<4L^lDrK@1+42V0fgCt^hqR&I{H(^PcC2i~L)G67N2Kd7K&5 z@V{n+4V1hh-<&mZU;ca}#&R=$JA)c=`F*~bFH-`}hv)-?^IQisS;~z)ox=pQF9DCi zp@K1keTsqn)7%xV{JGzF>a0t-9YS*twLApapCyX4tNe^4STFI)XZ*619lJ$FDEgks zU(*=nlrFk`377d#(Ak_~B4gRAi@-olyrqjenOJo_P5RwPMYJ6m*pX4qDV}+oRc>IFs8Y0tEdhv^$7V` zWpu1AFwOiNFmS*lJRsdyvmg53{F|R^@A{D+YFoEl&OZCy?ZF2gY+tEX|x;TspPpu z@f0fxKJfluYB%3p7Gt( z1JY&*V!(ov&9Axcy7sUC_0P1ge)Y@kH{bK#_UL1evFHBkc9c~E2bf_$f?}^MxavaQ zxeda@FCA2&ktA=aTi7=6)UHFU$e7@C^h?;rwlVen6f3!?nzCZTw!!woy2=$^9{%V} zB-0EuWI)Rdjj4D4(#iO38-=U9!x2kZ!(0DxeiNVqdVVoVbz%gD7cPW zIZppwgc#xdE#zFXf)$H$LV36 zabW>e+AM<(gw0JVNTW2({{<&;NP=iOJv~kRZLI095kbLPuBrm{JAEKryrII1^~M*y zsNM0BJKIM-`ib^|4}Oq?Dc{qc*tNU8{KdDXO*wk_NL$CYn6>NIr4F&r;2=e3RON)2 zi?&$C9y8=}bZ~nyb&2&x(g?2J){mk6maH#~V&8M% z0whSV6>&F?!Z8k62MG|)8GQ@gzNdD!JxBJnhZ!|Iz<#pJwq8#t?(Ad~TIRZx%tCsM zk^hS}ZorL`PmdpMtEm7kf`J?GU&7%cJrlg5WtPgacgz)K1x7)FuULyF1=lc@T}7pe zJvocBfaO-t3ZvahSbTOCr>58!MSNBYW|GDZW&~k?lMlg%pY{|&?7?U}V~u_qg+xY0@d$VkkCMfvOb^8-)q2JZmF;_Ogh0KFI3Kz3l)6n zx6^Ffp&{2wzK4S7zc*pl5d@!HS*vpxFH_H8>WI64kOM#G3te%G^De}Ti$7s z*Sz&Fz*2w+l6}hhd&0EgJUhUAab?_U_Ob3bvb(KZz5;g+?>l=E91a4AXF%0EfPh)<7X5uu42gZ}b$=syVv`s@_H-3k|#_yl} zh?@#2hs2?f-S_Z=?T7!TH&XboChkYtfByZCwjY1jKWP8<-~EU7_(2al^E?L1E`2`` zWXZe=cgig194HetXhh!)T1p}5M9Oe}>G$_?LmDwEkt*LV!<9!X*wQ)Uwu|9FQWbtz z0BNj4NLcEeN>9aaUaO!l&Dju~=8n?rpsV%fEd5z~!OFVg>TI%jR6dP2c}{x7VP+&9 zgj>Q)^CIth#(3Adw;?R&yaca~n_j>L+<|57`|ia4^--gj8x7KCM-8?XTS&T=-xVHBHVC-=0AFW=an zI>27!y(%6k9pveT&DXZi-1TP+C!rK?y0)$3RCx!FyvzRF0(hd_L(TN`X_Wdk?dxo< z*tg?>wrtUKuA@E&Ka{g4pWM-wO)lYpz!eNa?`B{8SKIA7Zg0!hOv1loTw%AgU3%$y zR>g3h0Qi*WMXZiFbmU+r0RH;-|F!nY*WA(WzUS`t!9V_B+re1^7hQA(be}}|R=J;P zpa1HEZU0F%bp}{CG5_sve`&k=%1hBXTDxM~mbPW<SSffp1SD!)rFyS%ODkfo{S zwll=Bav9eYFsj}drHW$B;UhLwE={S$X;L{5t5uVnG842`3Ty-^<;WJ9GQc|$=09x z?E$8HKJ885gr7qa-1FSTQU0bgJhT$RS*ood<0i};njxlfhxzvU@>##+arkIZ+_Yc7 zgx6#4JugPkVbmA^)}#P}i<|lxC$0l*=-27#3DEJm8*t1;AB2Sw>-ls)ccgQWH6jh~ z$LQ>-(v55(9?KGGOY)G{A$X|aVSQj8+aTB(`|_8+oQ8X8I{Y;0=CSzw51Nk4v{ffK zD8+BN0^T@$+8Hn&=~OO~H^gDMf)edezJ@X{u5sR^%$fJ%@IBBgUQNe?CH|3DT_pko zc)bU=eDjbuso(*$v8(bi!0L%Hy@@Yh9sls57dX=ZQ+8D}G#;#E17RoE1Fl>?EKPPG zJI&G>o)UNQ-;mJU%MS6IZQ{1W=>SX}g2lH}LkQs_7kn4(X4HT!uOYs?O4da!4$b^{P+1>TQ2-F&N&=jwFOd~^gfX9- znRTF`<1iw56WkSOlrOqh8Y~w@bE+tEPvnmqK^f(8_{LhaBAj+`hC zOyUeACSS~w@IXg+<_!bZPbcU^uSZe*op=9g9ppB3JWA}1H{A+uCV4KqtgT~-wlmDx zzDeGjhewVaqrT(nIOOImeMWhCh8qk{pQ)K`uRl&b6gjNfeQAZO`BP3$vxUK#Y){L! zj&sF`r~2#e^77;lb%?TN-_G)+?2!;?sJaPOGP`?%L8-+kvF^cV0FgeZs}igey|Z2g zaplU|F148aTS#B`6n$VB-}yNHj23fYy)g$Lx5D+oMGg?-%|hO|lsju>Xh* zVD~I42W%EEWtlQF)Kl=!s}Q$dxh=Ec%DwHw3Ka2MZn-&%`=!~CTFtu|JaG6q=P{U;$zW!+rTQbtFO5>UC`Z6 z?rI0&|0Mg44eKmxYGq_^A@n}<;5XWj{=~c6Z~yv#YPY}WnzrTAx3{;x_3iDh&wr`C z_kDlVPLf}nFS!`L?P&kxfBV7q8kXvxJ;fFWR=C{t=})&W-}~nb9xZCuUc*&*uX}BK z!<+7GfAa^wr@i;Rzs>m$oT$%XecmQ;%dIzKpW#Zu9q^le1cMf*Ie1S+G5JK9u=~N4CUV8hv>?&*Ii_!f1|R-ckXI8 zgU3wtuHn1m5kmSb1yYy+NpVqcn9lwlya#y~39!aXzr&SFQJ#aywxQR%)H6gNZ46~4 z7DEy!e3MrOi2*M4D};^c#4Rgv2yfcN(@oOKhcuWL^T|~_#w0Bc>LhRQw4SrB@Gw(~ z1?75*!J4Dg-yG7)*6*!XY~eOJf!v?WimQ$6t>3csiqvgKxYfhDrRPbddq}?- ztbvB4g->0iFF$C?djN0%tq$4b@JQM#56s(t;6Qujov+{!zs<5H#V>F$o@^}L@c zJI_1Rc>$EQ&?Z#_L9s%nLU0xZTavBpYz%YV3a5X%4}Jm5Vr*FLd@WwMlq{kmvopX| z9;X;_v$5F2-IY5TJ$&7p-`sAy{Uw}CdS&~g-+6ydt6a+n_980fsbh>>(;4+@9a=3a zEHavSXQ*&ysTiyrihm^(l_k1BDKGa2Y1DJwo9W&;n#M4=ps2+4996+)axKMoX2m^% zj?g;Fn=4RgRp&CdGAwu!jlx**&C!9)43!3-{Lg&@D}6)Qbk?woqYL@qIl?M@;+u2f zTckc?!zxY+oPgrunS)Cb78o*Ph%#`dJ%k0kuy^#*I%n|XKW^jBa{%*f6zjxYj|!Kt zMlmwd>c4c>2xkhlQBiWMAlNI(|0tA}aoR?Bp|?n`d`jL9@%3mWJ)C;BLIzMTgb8P$ zXEBAl$54RtSZ4xWU^5^8g^)kbI4vIu;$uh)uNwKpqJK)VZ(#UNb&j?8Zx_*$Uf*`G zF6CrW{rX`*Von^O)2B@gl}^2IpeV&dDu6j-$F*jZRDK1pgJxYe;XYDu8D2hX zsu4CVg3{5=e#Bug#SSo?9k(Y5-qV$UqetN}`Bf9)F=m%%{s$wt#*O$$Hr`O)!(cK0 zf{VONhr_A>N9{_R;q0J_S3WraqNza*ap5<7dwo;j2e-&^^)!4@JtU}{ zJ6zBY2=u{SisVh_k9nfqvSr(WkY&|@y!1Y5%endCDialcm%w_q#?GC4((at$;J0J6 z<4aIdXiC%Rv;Ppf%}0=)LMFYE%Iou-6`jPM0UP;*>G_uYG(FNo{B{;c}n zcVC-0&iO*%U8DlE%+tfU?vg*_GPZM;S!VqgkrvR{C92LiaYbQSWSq<#^T)OI%&)Mo zJN+iGP#-J=4}jr0nMlWUD)+5VkdISzPLD(X1pT$eTz}^EhG*cNaMdPP{o7M4FJyo* zM^;k*v22|D_JHKY3zxU!r;rg8-J5Q{wjDpbhl8b-ajN;Ewte?e4uQL@ZCbaAz1t{; zD1|FYugcKF4?m2&9H+B<9A%tA7s5}0Q-&>LW_t-Ua^}1JGgpVyef7vg>H+1Hn+{OO zFS}xMyNPAGhdDw1(7}UI?oTjKy5q?m?ZjzTXn@21WDZKBA8CFmOS(r6nceqZbO%G9 zAX`+(7qegc@Zl%9HtqVho_n!Ro#Lc<1_qXsF6&b7u2&AulIN}_0%huM^Y1igN4@yP zx3xFF>5c8cfj#X%{qnDZi*2X$XP0wuqbnC?8SGieA=8VHQ|m)Vr98)C<>bQlk>CCG zcFRrI;B=ZaJkq|fV^@3h(I?v4)$3E1&gC`)vWwZwGbqH%>4PtD)}6teX$A}&gqUKo zZAn%HSR!WICqDLt_7DEiyV@Jy{GIKt&waIhB=D3$3kdOA(UY7*v1i|* zc0GsjEnl^^?SAqhsuuEu)p#pW{v9-OaAY58yO;yBCmEPp=&Ao z9m>sB+pcOayXi*w#!3v_-2P%Ad-=<6YkLn)v6|p+2Dgv5Yp=hiz2p1e(XQDvnfw*@ z#%r!^cay(gy6+1NZhV#77XG;X@DKl;=IQv#t8KwupZO$Zc~jeR#WwI$#wXWiLh&dk z<(nU;C`8#}i=5X%zt(n;K-#U#TzRaqt+iG4JO0QCuBi_!1jA?1hL|lH8OYR_XRVI|j>W>!x2-MMQea_|uQS2pI2G28oleuQzC__}b$qU_QDd^sT=}3>G zeG6zhx`=$JRyT*#Rgt=oHcpu#G zY$z)!gMe63$?#JAEi+Vrlye)%UN`s-JfKm41~QWuMkfm56;6{lc$*&WJ*R}%-qR_X zvfBWgKmCU_rqk|+ei~%}V_a6~;x|qCFZr;1kH_1CChiK&lRtSyxX=)!eC8cr6Px&a zcAB+oOtWTq)yMdApr>F4g;rXjIZ=e>00nmj7UUNJiWF%;aiL>l+?kyrOr1+ogO>YP z%4jEga&lD~(8{N(*E(P9Osin6W+~elwgepG@EOf``sIu8y7{je=T+Rs5^6^wJTK6K zPxx{$EC4=z4Q8;AmOj&}i?|Z6P&lOO8bXAec@Fs7c=H!}2l z2lq;YRAAyJe1J#rg;!@W@aNkg18Qus3a2TY_3r5sK9Y~6Vkp=#6vkQx$8PU3riW}W zexJb`oP5&MIoL5?M+@KM9wJQLTpb{>)U2+wrmdunbk;)b%F>fNcc(t6rOI}q7+hi{ zpQ}Qaa*!AEmPSzqx>8Tj=3aW~rOAh*D0z17#NXxjeEx)MB+B@Ob?`nNUEXP%Dc?O$ zRhFWlq8v^zgX%ryE}7O}g>EVJl}n@jEn^A(!~zvX6k-%)wm-Aioi}%SEk{|hYwwdsPX57P^_g$;!NCQ~=;bU(TXA0D8-RDN%C~%BA26|VW0n+_O`dZt=;kB+uP?p|7YZz zSpkpf-zqnzWzE_(D4Vrn#H;WWuKkCOa@NYF08F6BKgPj$N82~P_LX+`-Ct;b_Sw(2 zfApjOFsVO_lDeFMpK~bF9?s}ifz#ye8{YVa_NhPl6#Lk}(k{RBifoJV7K=}Q;#2MC z|Kq>q4){CUV~_1f-!30AY*{?b=+68@p~ z#KRA@i#Ic{u;>IlJK45B@krZx)m1E$e>kn;bIsQKS`K-<$%*vH(;O(Mj3v`Z^4_=kMapU^-@>jf! zL4$qlpGIk1bSqlVCjR`l29)5&!va{_w^cYJ1mUjCcH>DoC z45j;$O_#8ed>o#rLl!*|;l`?a> z-N(Uw-}^n^1LMuZxoupA{dNph#$Sx-WLYRpY>jr%$mu}~V&XHKL_;D=vb2K&#n@#= zp-*x+-hqS1+GSfdx68L)$>CaWY%5o-;p9)2yiuWUx$XuI)i~1DY`L->WTfS!6$>?B z6nij=dj`fWqA|#+{EKL}0Am?{z-z(}(T{r!cIYb7@-DbJ zTFO%bvu=g+>i*6Udu2aH2ljk#p8KQb-q&*yT3EOGYc~r>r;iDU%#^~tw4lh*P z#QE)*gts6M_`V%n|ILRT0V;tagsLuNkh8$v2v(KIS8X3hmnmx&8_B~7}I;u5z?Gl4>jWg}>zi$4=) z8u~kM!*}p#*9^4O0ErGmdPFgR_!`+qJqBT)$rO&>;AiCn4X)pkX4DJpxsUK;fp}?j z)=v86o1F|khi~_yyZ@B?t!W^wVSCz>e)7^VF27$v2idIvPqCcRYg~elXYnJ?gsr59 zX-VHGuSUr#nuIg`i6?6e`mjj>gX!aGCIVdEK`IN>LB#S!=cKY`1A z4A0;cchgqzW3E`E_znw+Tv$KHqJsYZbsoJs4_DIYC_MF&~vpJ4e@Ddujj zDL%-2dDI8BAct?1SIG46Uj3|-7NL|oKyZkCz9zuIEVmBYkC;X=bbFplZD+HbU45Ea zJq93D>Q{IVwyO+K?$2d<1S+0Wk9{_NAAVsG$%_N-6hzlwBlP#kw~FM*EJ3_6{qO*NZ6RL?{3E@JiS zmMvF6$0TL*RJ-b`tGRCO+V++=zp?$+Z~bQWjXMNzmbAlt!mNP*3s86uv88J-be?EG z{uBSSz5l)MX}|OS_i=*#zV^gp+uMKm#b0QD`|tkk_QaFhIrV=x11ZQ6+aT7nba|S= znG+1km@^9*9AmtwEucIso}6f(Wy${Q-t@n=pMJ~#(cb$T?{2^FfB!;T#(~(oo_wI) z@v__7Kl{m_%yRsb))EOPnaNEViNwx|w0P*Sf|8_gVO#(Bx zpO`w=_Uu1_e9UB-{hnP|A!~miFMvuXCUv+k*!g1Z9dx>JKWD zQtsd?1gCXS%;p)WkPsUqOsWU+!ND$-b6xe0KbdOXFaYTqt8d#wo+B^6(`E}Jh9IHb z5rNi%@6N`DV~l09e|JZ4CtQ7(LLVn%|}Q1@u$w?F;!qn@g3=88UXi!GBB)J(2mv|r*?ojZ1H zZ@>Gyzr$*)i@Ay6Mz)(=g~HE@5z3=&$shjV2Ppdt@RG-#H(^+}hDt-Q!msM%`Xw)_ z{fjO)cbXbdB1 z;9E?ilJOlf;M!YmrtxB=R%TLaXDBFMHzPxB>>UAdk6SXpnk+O)US*25rx`1J1oY`< z$S^!2bY>bqXCGa9&!Yz$d*lDjK*pd))*%_A?`N@u z#`EGx+UA8R-gl>j=^w-Ue7E!YbsqRP{d_tN-!#boKLH}IWV2;uF!Ig{ToErhuS!rs zRms%YkXUiKU(=40**d17Z~fRI{7@rMsW_VBUR zcd!s}^p?JS7<~osZN3GluZKjB4Kso0;ibE=EUA!Z z`0zLZwM)IU@Do-4Q6H7;SRWz({LDx3*Etepud?7)mg2v-RIa96Ry{>W6a{XUb|1p| z06!hloT6-})EQCRRuX5Yc9aMS34O>8Ru#QVlQn;5T)(q5H zwox=aNY9yIgQ?)F9A{O7bu;BT=^_s6Z}ZH!R7w}FUE7wY1L|xu{VvnTf69Tp9{6oi zwU>P6t9VIVZuy%wKGJ2IaEATRdydbx?T3!HD_1XU|LWiVVie;4{9Es9FS_O$;(^7$ zSA9jEQ}--qf2_QezbCn~+<_NYfw^kP2_+AkGe3{D*qZ;<*cG~x$4t4(*ESmUE5hAyrivKJqdkG9--8_ zN7$3PFS0L8G^dVpjtMfq82R7G))4m&ujf?n?N4lPuX@Gp?V`1da!ZP{-QV~9KhW;G z@2gCJxdH`wmm?_UE(bWw^>l03ZfGC==%-M4C)*GF;19Hyzw9N{` z*S^-i_VsVH(;Qm0cmI+0z#|V6b|qUVkP8MCU=g%{o578BXIr;UN1tk!krdK!7Q zylPw-;Q+}`|J;9Qmu#GDS6#g&s|yY>U~=~-KgU4FYU+~}?U9EcCSRu8z4v~JGcXpk zO&6_c>yX!t@MQC*4V=3F;`YQ750GwT7WsByYSSef!{ZekX7I6(eTW+wu4^y3<4(#F z<%_|SEWbxjQHGT%^U1*^axQt7gj;-Z?~|BW7#Qk%3QPsE8>!IVjsBEZ@?(Tgf$)b+ zTm6k2X~+O2j>=@t?~o4a4l%)U+)K{&4{jV&E`w;GId);SSPsgex3Q)raal1Fr?|_M zP2AR(6;`{}5fa)7;QF_zFqnAq6Vn`?Y@;Nt4n|t{Sf&;tKPvaaS3H*es)r4EkL{g*>+iK6`H>%?%ueP^iB+rE_XW(WUj54U z^FROZIj3O{^0zZ}hi$?f2a1=WfjAN&zUFI1OwwRRomo(6G_}f$gM`*|k0Zy{SFRp4 z+owFwBlVLkQx1HC@7pw%>=)daq$15_W&JLB8wi&p6!DaVcFx%#U|nM7QnJRLAaay} zXbSJPjcxn(hp0$Sa&l+wkMN)mS{MF-XWz>?6zH~eZG>S7nQOty9(y9s=zfSOVKL_i zaXK%(orygo%qHEsyWl015m@XF8pwP13R)T4n0U{taA$IQDI=FE0KrjWVI!}g>QtC3 zmI5*Ex%kUI7QexWF!`MZN!*z3#@kr*4_4oaOF=Bqxo6=OK7Rv%c8$+K6xiSzuXyO( zamGG)`3jDw#Wx1&~_j`BchL&jjU zobJkGcTgU5x3gknEmRcGE_1wXL`J3y*5DA_y7@~4zy~KjDGbUSUfAubbQz8pkAfi} z;mz~vIE(0f(_y=887KdMO2fD*JOw|RaVKe!sRXNvKD79qxW&MSCdtLuMsqOQ0=^Xzp&3+SxbY1Z@sO6|%>Hzv#Ub(ehmm}lynC`Tq~ zDBuK^Po-cNNb(Gz;vY1pquuio*Tj2%JoxvxdFz`fiMT_GFId7m?07`(=+H`^{zYeX zd=h@ZlbjVVzk(@ReMWZXJ_p-CL8mEz!h1;(UyFPv*fC1?)exxOd|1U>}#YvN+&GDh`XDO^oLxW6Z0*(8GQdFn z_qDIxPxvw`QOdV$y{tX@wTIgg@LhcgSJN@*VmJ4SD>t#q)Y-WW%nW;86xWk3U&(;Q z(F~MCju{A;I!fN2XSUpVX$DEZ@|7>3Xq;+q{;P}F|9yFT=z;Cbu0Ph6Os;DjnMf!G z7Eo#@SmkkG->$Z7;%vKe%Uhv=nM%9MD6tQ5_xn+1yf43eD`kefq@SEKq{#nV|H&4H zV<$K_f-9y!clQG*zmK)oyy_J!U%v?+EodMA1{N+_ ziRh`c&@YE~4k$UXb%^WmF1!3nmd!uae(*>Bar@u@{tva6-En*SJ6o?|3oZjw1vvO7i+Z+qeHo;$SrcDc!4@Q!mEBQW>%&EcIaM!)~b3Rj|ZJYtfgaRP^Mz80<3?RB+>#w`38rhG{UAT(yGniaM}{=YUx+cSo(E8fdz@AGB<{cwC3Lwx z+U->?$=}O9dRJ(yqP#1!JC$i}jPSs`Yp=V$edGSGv-*TpS_~X`u%tW+?V-{d#e^Ae z@kVFqF@JQ^4`0IgU49EGYub-ewk8u#EZ4B_YTCqB>r@q#P%(4Isk zfnWyz}6P(2Pu}^%QD>Alo z^~AC4k8%8Dnk6z*9GbG+k!~t`50_EE9TBl}AktYX>x@W`F}o;}<%3BNZ|pmbRS9QC z!U40vs!n4cd9M)|6Pc^+!0&!A4|{R%#`H|>|8Tz^6eWGeYlcPG!D+|3$J*VJ>m%3l zO(yGB{{fL-B`iZ45=O4$Y+8loRW2Q7cLxQtvT)Xc4BH z`1Oy!fH(N(_$4E{3HAMBAbie$&bQK11*fNLF4*(4nOJ4TP;+rTKOBGY(3N*DWIW2U zohIJ)jFcHF*v!HcS@9NrL>Az&tPzHKpekr#s1q=DsJhGwlLkc(!dNxx*Yi8ygHYl+ z!~?7_iGwg$YygbQpLo)F9_V_u3bWJEVT?oE<0gK_g%N%PD_s7I-U_SJ{O~<3;vI!8 zWY9`_`Q@{RB)IiuAGMC>H+h6E@E1w-woHp(JT{>=r25AliwajdJJg+a`ZNx}+JTu^ z<&2&O9(jP)>A=Mu{8U0msUcCq2Wy3C`-oJleI>IJj9+)SUe`2n*hfZA69_Wm* zVU#bOHv|mbaz#$+o^a_@m<~e`hClrail>PijQEEv>rR0meT-WI2(}@-pCekdC!SC; zgc@X&ugdF^bHj|MOX{+^1@~Y{=Sn&UG|%wrarg98`Uxjrx{+Vn^XQJgJMyP_j04TH z7oJLg4?O}1?cLRP;q76B(=H#RGdv)HDoVDcR1h@Po~cp(=8F4wRi_eCeJfr0X;+O49gGq$e)2yKM7ZxGtRr%{3SfJwvGsv-st z=%dI{>6~CKu;s$~$~w;Q(lSb$=>pbr75}^|Kd=UmZ*$8qU^3d|Ol&@2rEy6^I)=j0 z=~KyfR@goIXXs0uJw-o<_*7VDI7H0>H+rRnfd-hRLN!aL_!NcW0Fw(7muzb1*oXZD z18oZ^la}8p@T|LJb6bDe6>ZHGmt~d20rrxg-o3XS18xyl40=YuDf(fqMt}j-NiG*> zuR6=y*I&G`ef>`#Y@49r7}dlAW}rPADYpnE-%SUpjhGCwLb}3p(@NU9-8TpfmHd8+ z)db$_e8)>}Yf~qWwnw+`N8wuEZoK)n_T{fW%uMxDX=4Z^3o~v_ z{ks*+6mM(Wwry>XKJrMrhkfhIS#E!X{r7+HhaYP{@nb*SUiHeCMJZNUoMyu3HLv{+ z>c;i-X{Q*BI*u&4oyn`WjsSW7y4`%!Eu?iV_riYxrDInHZtnTwpE9#O z+5Ya|{d;ZORa@vTGr`5akF8f;(N=%y!8SwrShaQ)>Ge7`7`YcyEpIOp&uw40xC-<~ndk)jrUBj|^;$}W>0c}NAi@?y+9K7hv z`)LL&P95h~m9>|)TdujXefT2}v7dM!%KbK09C-5mVw4>2tY>NeBM&q1aERso$7ga# z-3bO7h9R-!wZ+xETFXk2Eu`NqWr`2gM0?ToSGDhW^Bd6tKHk3ez(c7=p4z>?ot#|M zwq3r7Lk-vGc8LA(_2Gvfrfu2PWw^mRn@kc>LrIzLX`s2^T#}zrh4QxYGW?JSR1Dvo0&V_^B|b5v@8)yLC|j!IQcV z=4Te&JT?mcc|h zCUeAUv*9mJJO@q>M9T1TNj8)nI=gGY%tU-5pnCnX^ad=;Pg6P*@d(>cLQH-$tn-*y}#G;z~00Rq=?buWEJ*hiK*$L=(uOiR+( zLzYj`I_EV483P}88;ey$e_^KR8c{zNPfysKOYun}&-Y83#{s_;`xp%`2)=KHhHn<; z{Dglq_~+&?*2p&Lt_r=vRmFy!<1X7}i*CaA%1SvkL#!-y%U2MZv&uOxJOaj}mXQ~n z4NWyf2{!jA?|fH$g+F%UNIW72?wM!p2_8BMZOAApM)4#KxD~#Ub1b@*Y!;eyaPg4_ z@y_!Hw$m|$N}72D$5?W3G5om8{CLN|gsOOqatLGC(5Bm9!sPnu4VK|-%zRr9IZ|#= z-JD@M$*h&855Cwq9i$_^pAlzA!>tpq+_sIGu1Pv}Q&H^GfDe&Mk7*I7PN6fM4S7Kt zWw?F-=wF}K=Clh2(g3G_8veK$R(Hb%;%SfgkGl##m_f>dv%7_exsRvY1{%AE@mACW zA$TMOdL%9$5YY!`%CCpM@VkdEyr!)p37dYYZ=bPpUu3 z?A4%u>AdTi;0D(Y$zvSA)^`9L` zeh!kN-P75t6%WqN)5XOd9x_WhOW!GB)p%6wfrDE5LF{!0*EHpE)rO1O`YX2P3?c{G zpt9Y2&llUZFMD;n`qi&$OD^36j+u7J^)G6tAAhoa`NJOu7yFu*Gx@^4WDhB>JcS?H z7;JEf|6zErnSIc*+GX4hEX?q83&H|Ar#;E0PndegQh8x-k55t>naGlOFf9Y}N8j~R z?RBrYox#F|>_eSI0bCDFT(!n2_>XZb(rf7y!x%z(@YGq9wzb)>>Oq5^>@L5I(YnYL z7!lmo>1*lUKRW&*=O%HYj1t)cd+MnNBhDTzQEweN@jPN`K6!v zna|vXa`+&t8uye8a0)VR~izt8aNj`})`KXCL}@l*L^r#cQ)g z!2RKMxZG*>?5<#@Zf!es_;9=Pm9LDf9pii^Pvc)tdc9>~5+VD(@B5zi$xnWwy&0UZ zdi5*XeP8-w`_n)D6YAw9?an)2((b+gK@?$5@MmzvS@mU0p_5w^uHAN7`L~PY8MLb6U967Y|p-Z+!ycQ?Ha-{;0v#vt#>7j5;}#J@4&Za|5>0@86sQ4jQJv75-_;9&3H`jQ9;smH|zcqVthDUI_ks*g1U0Gxsyx1Osj( zgI~4R1|GQvj|1)+aap&F-wM*{Nj%a{T|JRIGK*GGxra*^lS3O z-qWRD_puy|OgX0gv$pf!HpR&0WcUFdm;2imneL8rgyUPZys(NrX&TZ}8BPPWK*opT z2m}6AC@6Uhw>jZX77&J?qtl#5x`Yvy)l`V9xNgEd5VzfQJHEv%_p>=#_tcKZ+P*!z z+d4*;H*&xIIY%Hl#O0g}qLGb(VP*^Ynb77*3K5>^R4aL8v<0STvM}>a37wfB!!wID zbDEiklT;9#63w52;&m%E@?s-l!$JeuGm!LG#{(R}U*8o^;jd2q;3B;MJ}rYKavq@~ zGkji9qPHJ&M*5z~#7C3>5L^Kh+UYzsL%=;Lj9}hQj{1z%GsI~5O2Z_bOn!@Pr2%QE5-E8W!S&qo7nBV$di7iQlim z1Qt6^z1|3oIJxB2nRxkTU8lQy>|H*oyZINTi8}nHFMVldv+NM5w0+|n-^dC88>&_}X3qdh#2002cSPE;8v!cMwa2+Bz z{iyiHyox5H!gt(#2pYFJD!c3acToV;`A9;B#n^ITCybUH8k8yV$rSk%UI~M1k5`+L6yD=E zF_ii6Bp?iUY{FN{$1G4;(nb za_*H(s+?)34loD>_=V7?DdLtc2($@-6DVNOHCBQ_L=@moVG=WM;D+ za5=`n!vPdn2W#Y|gIb>8zL$eW9mF|w@Gx@fmB}8&%qoM^N88Oe-_YLp#@BO4`){=m zefSUCwyUlr?4tIiFQFJuZbTVA)=sg!U-}ih8T!izOZuU2dp-N(IsEI_e&>%_%(1v_ z-Fyjs)YI*C?7L67lpm2r@`OBIz&Qu!*aG3e%?4(&y*}>oU5`b1T*Ds!g$(4l0@d>n z&apz{EE(Wn!g6Nqm(XW-)s6giC6`w;%4?7^*ucSK(07W1uy>Qjz3_@L5ft$%$HJcT zAV&wMz`2mYJO{8&;!Y)DZXvHIkCdm?tTwoX<@i^_2X6~->+7C9``d^9=wt0SfAjrZ zO?Mds23~#1iRWBV=rxfO)FsQAa9g&F8yvVHz}pX&FP~sV#~SkFNb<++&8HZw*uU>! z^ANvHEY-H2nPA}JBF<7kHw;gY96rgL6>RX!c2Q$HXdPxd=P%-pJgV0yW4*j9XMSJE zSSBnRwrJ@Cl|#}zKS-4y<49TZ9fUs7Lx^8`DxSdyzNvhd`%wNMBmDux2h6f)SuiZL zr>qEzy8!rE4?Ama`)evH{f6NSKfw%Z7)|vzV&#FG&iEPDK~o1m6At?9M_6~6$AT%J zE`iUWLBbTT@rp^>akm@=BjG$e53C(xcuRV%Mx3h)SXoV5^Y9}Nwa@?g=ecQNEA7k* z%F`MqWf!B^-^k4mFQJTmxv?>eyalI36Q5LQO`3-o;x*Wl@{xlUjjr-Z8+P!-ReV^@ z7x`hECxinLxvn@+-`?YeRqW5FMPYzBR?ZO=Q!^Bbbo%f&sWNSr<)Ejj@YZu5=sK9Z zl+pdgOJpurk&w~kbUVtjr!U`kZ%)If8xBm3qHmu#hrcvCfBI&|9!N_E3f^VRlKXo!BhJCy*-%PO)6abec(Kn0uQlGYKQ& zA#BB*PhgCFFx{hn123I}EL4E_8OFxe5AEj%)Lm0><=&RdzYBFE20!_HZ1Jn6D*>TWpxV|)*&M~Xgh zhRccM_>JMjrKCS7%=>cH#0go$;avx8Mt8W7#h^K@^4)3wRfMlvwz%1j_g#( zz|r}mdPo>C3}|q$gEU4&&=(KIsaIC`5WxIMyz;*r+|#*A=hx089arlke*P_B7Sp@k zm$Ec7he)DuI9_i(#(WNRGGom?=V_D^zgL3kdVCtaQ-ubbEUni^^7vDcgL)O%G2 zE+k%gwTOPiX=cXZ42Q3w8d46Ab5PhaJ}$a+L)&+h*;zAb2uts9*mg)5+&lr=z2SG= z{Y5&h>)PAi_;YVMmlxUpH9sV^*BM6)$Ug`%X5 z2uA!L2r`f5IC<>05b1X2{uK3{NpMApGU>_Kt5$Q@I{7YLnR@1$J_jWB?c389U9us3 zyXT%ywY~ceu*Cja6n+K?$iqn#?hMjU805bLHA}gvY1zUREXUsi&Z=vbvD2)^m_fmH zo5g+ieJRWHy;uHIpZZvP?D4ChVLdCMPPLUM*h|j22y0mK?@9s(JZ9K4e1`kyt#i-7 zr#0)@a&gI)_@Ck`y?dY7)n0z<_2iu^8%VzjD(5pS=MMQL%lR?Oj{Z*EY$HIXS1Hva6xrvuLxTNEk=!sVc~bLW%oBOm!FTN1Xm zm%Q|4?T3E&huWoEu4%vWYwzdk#F@5wk^}wN!~e&>|J$u?ysB+pG23pw?y`2%4OgMi zFJ%yM2?uenVO7PW?TdGRx?O+6%Tl(L727XmYl?h5e3*d%uIzK=km+%|n)0@YL4q*C zB$8f#hDo0vH)YJ^TmJdSKg;{vMA#UX_ ztDuH-6^=?<>R-1vfhT=FsRz!u!!_azOmI6023q5@p5w#*i2jC|V7Yh4J&pX^{)HoX zU?+^L6EwjY8~I3maqV^2wHt4^fq}s_FH<#seJ#1Tya(tR4Fnefhj&oY(vQ-ylna~kNPmdkg*QOX@Uc+AYEtg(GMZsPw zYVyMme7&80iX}N#M~u#fIWmm@6fPnw)+4xbOD_dfW||Se)=Yk7iW#NQ1}-5CRYI;! zA#>)+r9_V2IdW*Bve0|as!Q|4!2o9BF;+9q=xX%eIQhWnUIvE&roJma?Q<~YGw#*} z+rWVnaaoeC3SneDBHu&g1I7cCMn-{H| z8~~r5j0zU_XQ1gqaf~8+{+5!dfyNgY_w%RbnL<1hqn-)=Ik*oft0Aj~W`3wa7RkJn zE#$`_sSdH{Pkt$*{;Ugn_zPMqe0X(5)-hRyKh7E8cJk9bznlMcTJ9M~$HZcj6$V=SH83!Y9u zc)=HLNo_m|fpPdJZIK!Lv}*!um@$~{7XQ#1mmvhMh9Brdngxr(E4EIcv{jrsRrmr7 zbU;NkFD||kT>ys%cr@bEgumj`K{^so`SquumAWCC?!mj`>G1~Ehj@HT(ePH%%4O~u zI7>S~QQK2)ht65xYlc<1QjvCWTsi7XMmS7eEBR&ARW#7CM1D9^&+MU{Os~uH6!N+@4<(8ouKSmdqs;BzyRXge*xqiv>4vtP z!^39Ip5U50W-|}%X$x54xPbvU64Q?`@4YV0K?`#`Gjw>$hY1wh)cx4a z7kTdtF#&nQXZl#nP`1s-<@UMgf4Pi0c?g&aw|z9XN9tB}m%Nb%aytY`GQd*F+jw)R z94^*<-Z#B-=MKJ#UX=>#zuYVWSCol+@4v78FF*7@x3|9SJKAsl+Anj+-^bh9br-R9 z=@bJF=BX=FxQdRY@as8s|M+nahC7Q~xWD`eaa^2(UkEo`>h5HnU89k~(|K zhW+V#n}!MY`fDZ@%0upTpFrWBIE9_OB7Yb2Egi6gGy|vnqxEM%$H6M-Fpph*;{fj& zwmo=&boePxDWVQwNbho1Vk}(f(suW$n+FWg5PB&C#eg6KloyqGm2bW!J*rBP_e;8bQu3xaGE&wCi4UQ+vZ(4z^F<_1O%{TzBo&?H~Q| z$GBOGYX-ryXV>HHPd@o!wm5JF;i@g|JHPX-oI&v2oSy&vTm$$UQRvoka{d|0$AN?U ziIH0eh|{e@&h~mpwgAwVKx;5%i>b7LIT)>x0dQ04_y z>?_FwX>u0fw=hRhRy0hMHG3FuF}A_ulS*L~2jxwpm`_ky96P$B9o@69onH8yvFD zSgD?AFl|nx1cuuAz|)f+t<h^kP-O=iG3JkuI5&zX*c?aWjbD;ji}LSBUx01Zec`!QyrP zV;mQL^2yNkDD*u@-1~qPNC+Mmj<@6a@95q6z?&`yA{q`PfxUqlu`Eon98$RKgz{Y#da=_H;64g$ zUfXx;6|{2LJLL(VEU>K9uOb}y3VO>|WN4tTmoXuF8R~gdB+t=32itL1c@LEk)!|cl zL-WWaF2htTqaUl*X9sG4Q#=w%elI?*89BqWsc*zIx`N$9Y#qk`B!Ng&n41?7J znjpkpw3?2@#oH*%lhnh6w{5ZmZlmjd$<$?#X}y>F)W)B1HhdF{Y8jdLvi2Ez--~9e zBVnpFLnnDJ=i|7HRL4QkA(kO<>bb-t zBK!v2i3gX$HRmS=%{Z-6X}E6YY~?=Q!4anOe*|xw{bTGMx8V^8?L|u9OLoQrNY&sk zh2y{_bp_k`nXlj<$6-huWo+mg@MzbXUm(hEP~}ID02HqNEt--g%VsH8(ruY`wVS-~ zJvD`*j3S0aMj24<0P*oF2~MW{bH3%~SAaP~cawwD{7CFK#=zy6jUQ`bb-Y;^@_52T_ui zGShmRCDYR=fzFklJk6OJPJzP*>2=25J=yj>jn%UV(lMtWWqiz80!z;-3AEZHh1ipi z{5j?1Fn)JJz-h6et zz-eaujZ5X;gHv51dHrll>pxzO&tW+pX>Oue}p&cebbY z9&hje-QUlFehyA-ym&*lQGEAze^-0UtFPl~M+OARddt%-H(%R6`q2-v?PP!ZrCIqU)e8a92TSh{SQq*iH}WZ1 zK-iV=Yz0Vt0RaQbL|CZvEQK*t7$dZ4FPci>WYBU@Dk~lkC61w=;3tIpv&;+QFF*qx zzsJ+o@piZ1Gg|TRN0!3g8sNhd^_-0b-R5^@DpAd ztVWkp?!4u|NRA)h&F@6;e&7#2(Ei=e{~}8L=JvBc`?Kw)n>oait=-=CV|kR27{8GgLma?5~@~U%1t4IRuXiVhPJ$7Q6JNcmkf* zP9EIT_Oo=%(OwnlO_yE{P8wb~@3NB(i^)Kw<_x2tXTd+QVgrq=g^bQ5jnFJZ1d?`c z)@4GB27{b#aGRxJuyUMMU_71IS_rF6!Z{l4DhwrP9(1yQ@BUoDvYwIEM<0B&tzW%1 z4MdjHnZYJs!iTKR(zfI(PNt_G_!iDFuY^cJ60~|CmFa|&FTz$qD#4bcJ)YQdh>Wh4 zD?wO5qp&hlVeJJJu?$_IJ5nqrjcFK+IEGI_#(WB3B2Do zt+~o`(>%clzWL%lBxST#dUXC(ntDZL$Eh1ar<}-dafRoW7jR|?7kLtee+VNE!zlMw z;QpN5sd7;H)8i3WI`M?*aoYIC5P^;D(~apFgdm=#L1Vl;%_QRV9Xm;h0)Vga72FVB zS`(;bw$mm39iKrA7aSc}UqDm_(nbVtBIi+Z9;&3Jn@;oK*3;mug0o8=Mpiti^hrxP zkJPc%5Rxq1lCIwG1!oR3Re2#ES0$AKQTdo3H`1yHuHZ6m?Ew+@oZJUyaMxatWveejCJtY7_7TM3S6=;N3haIKR`W_nOVN{vCp;>}4%8ETg z^Vper_rMC<)2V39a3VQmGE+O#b|2o`_OiFXJ#~yU;OGg3Gw`1MuLitz>pEuLR4`d` z3m(m46vrhfo!0OEyg9&GWtCA+zLp~n#+bi-TZjEr2MA14H}Y5c=(56R>VcE&w?9Y5 zFLU4kaHTb&pc~3y&BC^9@#?m1>x;Om?Rfj>$3Fw99Gr~ue~bg;PVl?_hMSog+>#kV zONwVmSVvlJvaA@Hx1Ls^4edrCa~PbsiL<4yz3v8<^nZ>xwsCl=t2p*%>HMv?-VANr zDuIG>=)ghB%Ay>e=b?wEUAj&lx@~H)yn^0YRs*bLN%>;@VOjD*(VoWd#MzU~d>_fc ztobv=HKi&>_IX{wVjtUm?&%lXei9d1%GQrsePI-?x=5XgjJp*jXG~Zo(fwyQhrm1I zQ_sQ#5A9PKHGhZ*+OcwO)+u2alsI^Z^9YU{C0@&pZ3}V2dABG0m-qc%`>pr9AI1LF zEX!AMpJvZA%c;*k#kpHMG9ci}AD7xYB$aZBOwu%Q+rk~--pefp2ZHx=pZ#pR?%Hi^ z_t=Eee+##6oq%U`pLxzzfQb$oU47Lx?ZF2hNZwojoHD=ig}y*Nc4mrvVTG})S(G7Z zRi>2h)S|m=|}xa~R&>m%3IvJS_M^Q0<%eWu3ec0Y7+{riL)R4zw+^ z>{-XmkdIxym38AE!C`mniwARR^e>pAQ&@>ipUnOVaVB1!5u)+3V|{EH6O*!Jxe;cr z4YDp#{wppJg^tiNl*y_SK>$dP%Xd#pXyeGyNLB}?c;ZFb<@Q+ zwm{j(IA@X{b1am}t z0_+WLbv?*rGIo{%e%KNO zV-LgXS3m9bVaHgXi?z$!33&hoNj?iBSW*lkA8n7lMLsH5<#5O;`xBOLntl%C0w~Xw6fPj<< zWo;;zR)moO^IjSCF9Ikp{Z*#Nt;<)!Q+-CpEomiV2{wGqlQYm*E>j)`(V6Ej*NsY( z=*IK3=;~$ZY2hl=1)d;;zCvuHWFt67XW2~pK+rr4)c_mkh%CTt*vhTDR-i;Pf}Dq_ zvv0m*1sJ)B)4HK%q=*yroj&Ul8$y3lW45Jp#as9?LmEhnaHGaoMEp)N>t{n9WqwGn z_)U9nWT}Q@I-du`bFU$aIfrl6X1wxU(&i(r!x76b92j|zEJTXk|DKL{Z}>QTUzoaa zJaZ7?g`e=Mf&(Y(0#eToEv*0DjDJ6S+&#q8--)yHBIqlEXHCjHG;5{tk0lOI&0|+ z{Bp0gr3F-P5)!TRMkJ0;PhBfDl}R0OD4Hw_zY8&6C5bKk}WYa@O1~**i9^3 z*>-X^(OT~Q-g4(F+UE6}+MoW{4|07SC(18dkFt22!}6FZwQoZK&WX~@d@rTnWxcMl z?%sB1mijCi%!0Z6n?Q`bwT_upi8QbI(@di<%&>>G*V`(9nHeP9EUSU0nE70e0{W&q zU)C<)ys>S*7DN2m3lEV<_Fu?zrl5PQ^&|3vC3b%kk)0y@;WfE?}SP`Bgk+24HG*4B3IjNEVBxS>6{{mJxK9eh>BQXXKU^p;X+>^edjaCDdz&P z_y4J59L#r;Rj|nGlbpzZmCM^1h&qHExI$)fl@eOAvzjxlvb3CZE|Md2&&rfbXJ*x{fBn~gt*!XszumTN*)+(Eb*mZ%qd8B*2^EPX0`Rj=~2@YR3ZtOpWLWLPiDiFnK>m0P}{ zE%^9KJbVw}@y9jc46BhQ%YtEq&$ojzAayX!@|Ut;y#cPO14LEu_I0c?4BL&XV)}r$ zbw%$xgb=}Sb2P(0t+NM|O%NT*?%yIL(|=gv{#C@ofEFjXP6cG53sPw3Sq|?gM>!573mh!XkdDJma<@(3{t^?t4@OPVuoSH~7{4wsoTHI`UUavTv2?6=&)yEk$4QZXCro zA-m`Gc$C^Z&*!;=EAaCi$3MdLaR=lE;z~$A`FnQ$jmM$<)puUw_HnT1YB&5)mQA+CrN=Ix zb~&+5D)LK~PF9EYoXhiv8T0Iy1^}SsiG(F-g~)vEc{}$Oo_2T0ULUp5ZF3m1|LoXz!UUSnMA3 zbY=;Fk@WOiE+ka=rB0!o@}Km&a$$vv4m0Lwv7_&x;L-O%v7R~tzv!l{;MO1&Pc(|G zfXt)=gfFo}%3>-+Ae$G;kNkDfyR73 z2N5&lOS)ZY=%mREs~gXua4)1^B|&o%UA)M0Q#<>E($Hth>;y03FgAH;A4z_8p2`RN zM-1bH*XG3{_;G+f+NE1BY5(x=zpJfXjWS4Y)T-T%uBVryGjV>w+4cv&_Xq7?{9nJ= zUjOo&>34wxd}#xaFZ+Ee_ws)QgD$oar=~~)eXvq~V4!>fan)Ngy4xL$kUH~8xN2Lp ztF$Sf4(6C1jp3`$snY9R=lid(T|@e%$U2iwp4xwi^Pya}?mhJr z)Su|x(1KD3kBwRxQ(?+Mi`1>|!QV(f_G2IWIPslpFM84KStaF_c^fu*b=~sz)vw;q zfCu~V*RN}9xgu|d^d01I#VPv9XG#B0{j-1AF5=)pw-Kyl%feGTceM}w;YV_N)5#OZ z+5)z&8o5_dJF&HtNvUZj%g&K!-syec-Xm@H8@r(Haefq%wvlTRuW6I3H?krD-ja4{ z&y`~I)X&k^&CD$2!|fHh2OM3}Rkh6Qq0lp+a`tq)cl*IMbBsfHfpFuE*RVu>OZy(0@-qzNoM86+8;?A}-gLHQ zux(f6Z4KKEc0RSA!}NZmz5K;Dw`;DvJOf7Sxw+ttZ+LzC*vCJ_L9hEbMgJ0z&vNqp z`tW{=?JaB8uF2U7D%!hI@^MAcUwtV8r21c;ku;!-J|r2oHahGyN%0J!JS)G8}}3$Nmok zio$lBD&L(hm0x8sxCo{!29Xp}FszR=up%DQz@I$mxcZ6&Cp2MFaCIDF>V3ovn*4w4 zy$76T$yJ|SoqKZLnVs1*8>E%ATCJp2+7()mL>5^F850DU&je$eVBqHuFz~}B7z36G z4j_Xq8-qbYNFaj}%3_tnN}KcSVEI7TXpKx zsZ*!Iso13}^#^jE8F<3vfIHK|k7rCxYoD&pIW%ZbIy=Wu1${|_H2Whz?EgrsWmh-z zbQXD8K>u9Na{G6@>uu#f|IY7~Yp;7ox#O`Nyj6_@F&!RydW z{UJ|k4%W!YiZpSJpF~;NCnw`bnxLiHO=8VcflPAp7akARFI}=O`1J%S_L6EY5L?V#J zBT9cZ3`S=lh27b!ETO>elBlWxxZI;QTxOb?=wFs+v^eCC==ddRyeph<+-%hd6MQJ7=2}7cl4mW9c7K?}h`q*Kzavn(#9hz|n*g{coG6UMUo#ziJ_qg1|FOI~ zhMSI*6XR={Fc{wWjbj;YOFjqTAE!MP!a$lICz`)y!OT5nNs;Sh&upZEjp@mT5WrDB zEk0KC9jgVVINMO_RLfc~zf(rR8`J^7TH}m38ke5=FoKFBPWnkxR~7;%5itf(rn=Ab zyawg1+HK@2{wT{K*a)Rsbk!a!j~-n(cO;|{3mgt9@0AP#*ARRU(xknG6>l${`B?c; zaT`aaqf%&k{nfbjta14^{%XQAt+<&l^XwN^iSc`kRZttaZ+w;xY-ZdV{k|n`0FN#j zF{l2>*Jpl2K?uG+Y@%7_)_kq6E6p_xlCXql4Y0i%p57aa|9uuT$ly80`5cD|J{YIz z4f_70qbUwO{MFLrXPNWgz)$7Oys9%eW)w{+9X(}ghPK(xrGruVp|Fm4)!H(CTdq2e zE#Z)OtN0l}J}(W}WIS~bzL~8xK&q-%9xH8`k)my_`(tZoSVhr}yPd>_+vS=YxD$K* zh6!L@zRsR^RvD~fk^q&BpXrqv;*p#Xc&-dspQO)3?bynSY0M10^3C8uI>lg8PF18_ z#drec%xya`jvw_Ce^R%W_!sCy%pGT0F$(Wfc3oN)Hf=7OS<=0YyT4h#P7wM|C`FTy zGl}wRe}@Q}NIlKg#S>+okpr&_o8=4v_t?ufXX{mN(l3GLUfGNAo65S3G$;JyrV?!( z;zWmiqRb`|E|V}$pzw25=5Y>0^Dsb9wf^Ks?<{xS`N^_n%O>Js@B$@$g!)HCR%P|l zUE5IfnU$s=$wP_%q&D&h} z2F<2Z`OAP0{<6jVX|tq6N;<2;V3;$|p<=v>eb?()xiOEj>XmgH*R16Ly{)9d8$`JC zop|d3kzVu2suWM!_ab+2Nw4*ue9fQ-eMtuaTpB&Y^>pd(lDF>7-@KWXtMrX?NlKumS%O^kn(ZprH z%gJ+<(NO}fVHSIIVY1x+0Qe}A-}U9sEl>HuD_FM7b#^oX58VG?`Q6`tQ~Ag{?kG>c zX*X%!#2F0mRvhry{H;Hv5T4lHD_4u`lb=Ij{=}Xm+%7OyzW-%6l^x(bgQC87@BZ@N z-uTz$)c%v@<`-O=!MN6vQ`ymJd`zH+u)z|nSX%Qw?*7bHACTz+I?#gh|q!96Kn4~Hsx?)Kg?P@jrEkkZaDk)`6~EK;DU@ zrUsinX&||faX(cn@qZKJQ3yzQS57CA!i9ubO@=`WPp34+#a@; z1kE1U!^x~LiaecV@0j;&=3o*kYp?LAO&tY=idv<3*3msO-^zNNpTg-CA2MN-Q9Lu& zMkgarp4QCB=G}MPQI0)uPq~Cq(kUvJGwjc+%TcH#z-HqZLq~dt3nO0Ub+lR{i&&G@6y1RS2CSqPpF3@vA8Mq>o^S~*psF- z&cszicll%#1E%>7IIV20h?e+^uI5|cIce;F;@|(M*>E021G#WsU-&;5&mhh|_D8oh zGTOVv6I=rgdE+#U>={L&#W`s20X$Ai%gxU=xU>(D_t^$N2foU>r^quaNJ9O#%zN_q zzWs+;dd8-C7^Qa3Hbs=fs4wNDCaq_VB~^vkmaMY8qvP)!(C>Ei_ICb?qdC z13S&k?d;-AIem6Nhn>+^x@dbj^U#A_)iqhB?tQo{?0cx3;9l|5DDNA%mmYl|y!BM{ z)l7_x4%6RZ1%;cnO}|U2Ekg3j)rgZ3(vY6~O!~qf`BZr>zhaXKU3%ix@&xzsag+d* z!u>3_|LYHZtbCX|+D|embCgrh=UBP9iP=~CgBNev%5`^M?Z!Rr^c}$%Marwl%oAg> zFLu&x1*`_KQ(rsd%8{M_n#T|q8B$3}y5M!^)1|{SS{K;gbY+Iu|9P6W3QCnpXr|*)t8?&+hEC3WYQGDueb@RqE{**TeekjjGHuI}Km!Edf>dnsQ{{ z*z4Ea1}Z;u&?Ih`?%GvWr;g?psTpoRKz7E#vz;0I@A;u0E&uA^J`RX`dAaBAyUIfk z?aK;;E$~qsD)lmPkv{M|OVTGs7Rv4S-&=0J@%r+@7rm%lcG*spp2@OvJ16RMlKjF= z&njQ@vM(#|egDVGul=Y0S#G^^PkG+8yUR4UL3n832!j#Q>i~+&>>aT19EzEf9Bj=> zihub%FDchO?a5`=#XHJ625h{oU^N3EKk|bo%RAoww(@U({dX8B+fdeR+zCEpn(HoS zXSu-vR?NW{``Vwnx&B6E$bSDGRsf8$g#IvR zUac-$*3&muq*qPciWK6$b%?-3DTa~c6k82<;D6bWsLZuXJxE|kgaclJ1CQ0SQz>o{7Fis zQRCbAfs}_C4AkAUc7Ec}NM~pjZ^Bgk)wlXfyY==s+jP!?&$6+F6)p~5-GBf6IVs;O z6Fom<6d7?4?m0I;yL{`n`~$Xfye551&m^+UW(6Z<+(azOWZt1g+G1Lc)$g7&PBhmMuw6-efOO? zt<&Z1tw5Z{zF>hyNzPJyFnVy4SGX)Ja>_CX+qqoGWjkipY4DzLuz-6|UEY*yH^_ux z_SDbrJC^TlTs5it; zE3tO++z+gLYpO6OD!=#QbNGN0JktE{wDWJg=@y3l*Auh^sRVwsZ2+N}LKJv{XLeh(|A2V4-rUL&MnduJ?Ja zB?RJ394>#gv(d_XaDunSD<=el78-6l7PZlCC@VjN5|4FMwi(e=u>)Xd-L^XXly}Ap z?vQOlJ0q4_s*|whT;B<=Y%Fy?|Cc~5K(%&J)(@Xub%-07*naRGnAvdkK~hql^3`^ka>036cx@X!M;g?jCuM zGm5^fC_SdKCeVTU$Rm-faM__$etUT)FAWe=!|2!Z$9>SAGz3gO)`0m;m36chvS|OtrRcDQ{n+@4S{nFGql8QyIm!D(*(?G)J^9?Tf)<^KK&i3J zj@o->pk!f+J`qa(o_D^h9C<5>I*K%F+soP$%-ExhuvxM!a%GtDtfKET1VO9lYq__2 z$Q6?&fJo+;NXem`_KC=wbmChFT@Yxid~zVSTV>GI-?J*Tx>4t3*1W5C>`xs5?=XG3 zO&9GbTQ9z(jDGqq6jzpk&yAu0uHlq^>#@bM=k(#S@7PSa!5LkaxT`mKYP+-DDt;=x z3n*)+*w^kJdu2$*8*gUrg_lNnQ~7Pat3cHDM%qIkJT!gse>F zE&KK!E_bl~Vgrh9o#2um#6sVEap4pP#~mvF;2XZEyzu6mllIw}{pH~!Q{|r9rf8AR zGB~lZTye#d$~S!NOUsSVeOmdYU;X#x_g?>j@*EEF8)h{Dr#hyL%Hst_frpu~p5bch z?Hh;7_x{6gE!SLiaXE2pUpe^5N61UB#&ec*bGh=$Czr4Js+X2$J?q-?3%~NJ^6@+G zE7xBAWcZ`Z)U68YQ%>@kz}LU=&vN+PmCW8RFj=?z%B#y)fBiSY=S}72o4%kNIrO$N z3!hgpi|C4pgNKfBXdt=++i+K}T1)zOBNlVzt#5ftdE}7?;4|A^R z$KL$3?AP+4%*CXBBVoS9)5;Xy`9{{15k)Q`y1dt+)rI0TbgTQKh{K~gkdG8WTl^^l z)+@?*6mSse7X_cV(T03fJou$gfc)pSFXM**!#UZBm?90N2S*ii@hZPbpXq?+8n5z2 znIcT;3KPw@akjyUI2jV8rrAd=V#Yv37|TVBM06%`1L!+HIRu<#J4GjOwTzBaMxx#U zFFjCGo^`{s$|r97bosV#`R4NU>z~7|2p6+7e?w^X{1jIOZQHzsS^Goij12UGFZo8@ zApMde&+DLG<&QaR+AB>-iYZIxnKo?Q)BLJd@d)pro`ZGD)hP9I`~!bsj|*4qdx?~M zMX5d=y|z-HWdwHN^hvH`aWwNV%dR*eLnh2{#mCf1DtoRXKsZi`2iAMqX@o{49O^u% z2HiawW9E%faBN7~g2jQggrG57MaFu#%?SH{CYbf7R;F>|{>gb7DTH-`gZ1iZ{NRkx zkkJVIBAWZK3ImM{B&1TDThE>uM|mizXNk{Dt<0_|%Rw2^L53*QW{O7PH^Z&q+kPBJ z_abbadd2kwlc9)Mr$Qs@l$qt z6~2h7-ynRm_sW`RBVV=bbtHvWyt?;5FA}~a0$3HwDo0-?;cEbYWO;@3ed&g{3@hRC;)IUZGFGb zovqQ)r?HDm9>lTl6CORLoUAx3v!0C;c_AXdPqE7FB>Q65Fr(>VYSSzscWN08fI#YF}gRZ~sE=z3+V>)-x z;mP%L%#?c%v7Itk|Ji6}^$~pOU%7YjoD8F=e zINkp6^i(-<@DP^;FpC=Ebq0nBjzv19vn)@xA9Na}2qw}mqE9l#Qc^}6R)K3S6C3LH zcIT-l=)dSzobiV?2UFclFvcW{^)*B%?RLIZ?49+BvP|E}+NPEVX*MscQ&b*sHx2f$ zI=L~gO}l(b9ZpD>lwZAl8v`Uq%SS)@(Q^3MahAmrf{mefWtGIMi{(sxxDe4C+>fj=bPECFv;Q5$Jkdt%=K`q z+bS}FMdh6_L|F~XQI6JPhN+@R?m^BZ3W8N+^MpC+xqgH zXFnaeI9(3xeYiY$|9uQZoZ$XJ1Tt51- zkC#9Cqt|kZ{wdBE7%3NR-BupB@BWmZ=@TbNkGx~>%dNAlbXl`{h&WeqJ>d>yor4A0 z&T#n96aycJ$oDz&V4{5T6Q3^6yy4kp_f=Q$JzkE^93_A10F1gzl@}-?z1r0S7WheJ z$~QJLFEU~htS8kWG8^l6@|NJ_zh`5Rz=RN12}@amhfM)iA;q!!$qi&LPN^Gf7-Ot; zhV^QdQ}Kjxe(DJgmSN>`!Fm8$tz{NT0Kf8|Exwj{bsy*xhw-@;M=JfctRx9MTt#h} zY0A6h%3=m&>XL8*2l-^6tb|S)c>oh#rmH7Rq44J#UGeRB&V+aa!B&bj>oyjingV*|koxW;D$6hU>LjQeM7G=)t*DLp0><7n&pwH!S|t#N`(u~4|T zt7m|9nXwK1Sx3GxDMXE^>JY?L5Wp?|7^?zIA~g}s9k-O;f$zXq&s0rOVg%D`y$ndp1z8doJKU-nx z#rgPA{ar{hO6eKQBV{fb*vX!DU8uh(ca~r(v%pmLX|*1#21|-<&!KtrD>;DE@DZ?A zSpwB6*d_VeN8H0RC{cabmVz!dp{df{VDj#WwGN6LL8fU62Z&1=glp8dw~;TgFQ^rv{e29T+CiKH30aC&9Ek`HgUCiMoz~Prx>dgS=m@P1nUggnJ z(CUDDz&<@)$?!tVA!vHN2LjQ)j?iUD4ixiaY7+ zl4Q8r(W&wxOw4keI1bLj_jy2WOPYc5=*O#*argMC!-}ROy60b!8P9q7(Stj`r6Z;9 zX?o+>_o>|MgFLzo8KeW}zGRo%dzZI^MyELeUFC^?W-M#xIWyx8Sr=WhDw)&~VqSLn z=X)@ZTF|_EaE9~OH!XY%EBaQ3O{@88=GcbjJF{GFFJu+qDwkHF3z6BSEdnWoPF09 zqabZS0b_G~@dRl1mb!P^l?h%;M)x}_0#dg@#9K2 z@@mc6HF;~dV{2Mf;;d`nkP&{YFr%(WY zSC=@^p;7CaxalSr4OgHhT?M%g9NtNwo_r<<<{< zfB8o4Wp{hP7M7T&ybzQ08Q&=snrpfCZO!CJIeKVsIk@k^a)f>6_ug|a{c7+sfHFPx zNIAwqhYmCqmex-*VRr3Pt}Q1{uP+aHARa3VOi$8;T+B?LDK}mJv~u~b%gfx!QygSH zUG8Bi{b3H}+qdrkG$N~{WzFgh?5Stwj zoJt;Db>)?;E|@B>{=NTJF2DS;@+DvT((=yte6+m#HGf$49h@$k)^CLm!k;c5{^XtI z=skzZMZ3nzGoHMoT){zo-n^l{VVdu}^R^tKw`0fE#4*N|h4-UhjF&5}xT-3041k=3 zc2}85UuITO{*|2!n#(=v2$kNX>5=Jld@!e zQ2nFp5YjSao+%3&`#)qo-_<2}L6H3HfRw4$Picy9t;fJFO#^ArJ>@vqo1b+u=>}io z;cXv6S+|^MYQ2s8nwGdon}c0l|0u3O5cgK*Qf~pLV(V3x(qC~B6X1z7C7d`dNV@dg zt8X0J13$|`whQ5A7*|ZV3VfDM1uIM} zhe?DH@smfSSDNL`DB-MYOlh{uSdR!Jok@S?n_(->A`8*HrKxeqcUPx_H~Grj)jZlY z#`#2;3s&qyjE^oIzM9Z2P&m(0fqUAfOU-Opywc8V<-B8X7I#PQOq8dxGO&qa&JY{l zjv86l&3a`Wj2x%pblH~sAqdV)Jj<7;Ku*q`pyD`2)8&e2KoSI4;Rh$iuOn9!7W{@45W@<`&p%U>?*wA+6*SoR%u~o$yYDNNER|%}c{F1!;5H~Z zsK<;9b1E)TMj`f7cm5My;?j-pgsC?9852wWs{TEnc#AH@0QyaXKOXsMS3rA4yOClX z-01s|*0>s8I{HSK(A{^6Z4hRe*Eyf&#}cIHKy-0@Hb~Ed<1;yRNna6ckX0)JeO`F< zbM^@(R|Ym2>X@aB`&Y|K#JZDWE3#Ti*37T6B|XAxtRNqaQvE893Z0mcrIb);iLC3T zQFiz>5t5$7bKVI0v?Oc~#&n3Ik2_wZ)pw$>Gp8lxrv~h$J-i9Va~{?Y;ti5PUz{wX zqHHGi<>~7@^-Fx+J7pf8_~&vL+FqXNR`bUMSN|4(x0wZSAX=anHg$W=^O~uKtDbrKFe%+f3tk;X zTVV|qI9|1?6K9p79*Pb}U;!QsTHP9C{c7=6x=n_JG}EOwNJw#4L06pM393Zc0<8G1 zv37|}5ODLZ^b_o{p;-Zc?eLvG$*J8a_pWYh9l&&$WoUlTCXKCQ5LlCklZR;0W9Gx}S`IS17baNabGQ}z(Opu0 zH7AxI<%%&GWIeB`iha$i1@4T$X2;fYKl`M;itM6IJ5#SsF{!fuz`?S0%a(Fr;b7U! zK5b7oA3jOnkp5-(C=Fd2trJ2yamaVNpIw}F#!>}CnW*>8+mEFG2|ukvrE_kYJn+Cf zNL*m4y|Atlh11}xifEKOyqC?hYvG*jKaylf!jM3 z8~d%&>n~*wtAiOT)h_X`vwp5%m_UK%aJLiQ^5lu%t`tS-J~mx$eee6qcYN1(l@~n! z1?9F+e6qafy?6-|23J2S}fbcAKN08qV>#Bx^m_)%gqn&+fUvMqjay$b#Eux zcdjhlcke?C=FFF!S6p01*Q_hYkDbibgjtRb&ygGn&fvuiXCds|xr-3hi-jenOi?mF1z$ebnduDXN9G-PBH!Vk+liZ$9wBHAqqxu{t(nUpo^X`1+RC z`3&YDPbjj=y74j z@km(sRtIq#{niNjB`O}(v^4oOXz#oer|EG()$k6CS{EzV^2wQZbvDbTS7}yb4!hRO*&mMCCy$VYF*+PYU+B*hXVof&B0M|Xi^t+Jb;kSXsKz+03(Sr zoV;uUH?DGU0K&9c&p43tM3^T=u_tvV!A3Zv)}ai+XZg$VqsQ^9d$Z1_QFp1mdvQoa zHwse2njkaALVz7yBQ!uRfv};>J|Y|yb4M)~+#AO7BRdMCoJ^Uk=Ew<`+K*7_y2ni% zu(kdvP&he)l_e9zq5v#*1&6$?LJCk$oP~r8o_1W$NE4XMWDC6+vyl@->yipGs|#Nx z(?B@zQ`mTbn=f!H0DfzB3|ZG z0fG#x@n~=HRo~t-&gVtY1F4pV$FE1hS9!NWWXn)q*yp3iF*v(+Ve$M84XscO7-cdI zn}VVYM(B7~p^yAo$tLd!YE>RF06g|(*%5gKAb5;NIB>On_m&4MK;3GES&0dZm19Rk zEmJiPaY)vn8T{_W1wh<^H$Iw&!64NhdP%eR25|Op#D5@|^t4ay_?zzKCUkd>NgMXO z2g++N%plIr(T36)h9Nq_cGgpGgm3-W(il^p+VCwQzK8fRS|DFO^;1#P*o!Hiec#83 z^|65wZ)Qe&OkEbN^KZ2D@Mbr;k4A z4C_|FHt1~dTnEcxx3=eYmQGAhXZAizSt-lT?4Dr>c_u@U&uV;Ed-A147~*uP{xyFF zW2|<;3}WY6Q-c$#!xJ<~nlmw8^~Op-I(p8~m|p#*%QJpdE%<$faj{N31$S-S4n)t0|J$MmDSKvsmRmPBHc@W&?q4L#%IY(5BYPM{4iJ0ojmH{ zYtDodoU)y|(EbD+(o^g=W`lW|bXy>ml6yl(h*P!Nlq(mOd*ie^vu|X_kM4ctAoQm5 z53le_o!YX%CCUq|rZC+qF|M8ro;<;q`q4KwbzA|{gpY@U_#mn=v zC_>{L0_RL;<&*EABRu>gt*7izbCBMLZvAk1;~V~@JoN{^S4Jg2@vaI2fmWkLkD&;j zVs>)AuSM^j(tl>TtIW)o zS!Q&rVg?pyaSLXPvzEglu0lSR>yTBN?K67f{eura7}?+R$lh}Cjvd?ru(hmZ>*ypa z4eWQy+b;R=i7gT+Ci31D6_cx2!OFLLzfZ9(VP=N>W?*U6s&(WUD_5tE(I;JBe(uM9 z8O40EeBVF*&hkZHbYr>cMK_jryyIi#RloTk%f0vBQ=WC*HSm>f7|52AaFp5jg_-Fx zbNmPj`!w>-jRXuNtX{*)g5*8BTUq-5z=IE!yYIfIJo)K2un(QB5R~UtlcS{V41-N5 z(I_dZOKaI0atdYt(2+xB>c9i#@csvLNFBmTnrO#?bNRk|*QXiWx%{E5GBF zEW3YJ`Nd!OH_YB2%aZ7O@42U3cipua1X;s*Tl@CyA$`Z9)G0g4$1L)wsS0v!Yw3{0 z%{+6x`9@~jG1m887l8fCkyf0Rf65l3Ftj>JZ0jVn&P#G|Zf?DwRcMPbpQ_Pu(8 zmB6ah=Z|AD5!A&Ks zHepMNtA`wX5u*byn*jhw-q}V;!`7`^jVa%jL-W?UOw(mi z-qP+iDC=+SNmHO|I>IOX8tr4$+aoBLmiyWlGrE=298{mhqf+=;1UMh4$*6q}S&}cn zOejl{RJv_qEYuua;bC>dD)o$NxqLm#i%1Xi`1NFZ4!yIGx^&)TdZ38NtvF9Jg6BRs z+E`}s$xxOw*)%Ou$<9)lFF5)FbA}yF#Yg6f*I9eU2=eW1cq0x|^E*p}tz?ty985Q?!qY5w(fr*ySD5)7c$7t(BcPhS(tv?$GM}K@LeK&4YKJ#)|g5 z@GCgBu;B|Z4ej~BLyZ8B26VoF=W$DXKEkK-0G!WBV(r~L5d@qM|NkksCn_C}#)>Me zaEi?8@~e%~=F_s(Nlq$p(jJ+&lv8a3z~ z^jjjZfjX>IZHZmoQ=|@V3n>O!X7Ry%lvRrvO>pFBrALozQfl;I|w<5KJGOS20^s< z;v0aMw^_nS2hcXs&XqIv3Y7yx+wZ=TtUEM=8?2}#l@^LCu$(C;wz=)^r> zosd?rR<0`{DTksHw!9zp-~*RvQ&(B$jA^McT4|{r>{?cx{~aZ*L_tTGG}E_Pjc+*7dW-JC5)xc+V}dr8NjGs-%3q8&R|F`90bDeDI79#;^I(7$p|eMquz zfyMI-&Z5vRx?ggL(F5!<-+>L6v>!ckBv*mi8MPl0nu$mHy+_?%PU;fUoqh_0g1YiR zzJe|NB;MjxK~kA_39+4OXQhEoC%5v%dR@HkS(g{{W&5QY%iZ_f9i-NKkL=x(Jh}9; zOE?5;D+i$M=X$b}8F-P~;>kb>k;`iz`O60s%LC|kr9)=zoG_xFIX}huPuvo~XZWWw z?ox2?qMu~He-7BQe@N(hu$XXQHo^RRbAYn+FarYjK5#!gMEPd+-Z;E#eI464-8P`I zzjyE698|WN{-lE(A=9V%1)cNsWj(ZQjps&@7v|-`Lq}M-Fa_UTrq5~)_W;B1Osb79 zmKT1_bIUlh)d#uqZ5^k>b6y<>)m>R`e%_6lnMZ_>OGJyAb(dTpW2yYv3HZRQq{_ac zWp*qMv$bQ6yWzRN{*i|duowP0EM>kpaxg#djRb7_I6YkzD`d~@8Dne}S;K+VhmIaZ zgpP7u{YmIzg#uSXo@PJ43YLdUIuM|7Fy^9dC{OU{6a~v$DI84MaS{8Coh=7OIq+b! zpZVc`Ro1aJcgHKgoqU*JIsV1vJHP9d<%+96Sbq04|BG2w2MdSG)1Lm6$X-_CQbH!^ z=U@Mf>vDbH8~^lm<<-CaYvuP}^Bd*2{=I}>JPjF6{`=G6>tjA6<^BaL8kDOS{{%dkVH`C@7X-)1_=H`1ov@}TVTGoLLR zc}7lanZhabD6cBh(KDbc2XtB&Vj7-apNqKTZrzi1y~7I^Eo%+F^|dlE0jzbaZoVr` zRxNc~N>&^YR{C1mF)gkD>JP-#@=W#z#x(VeH1U}USnQ34p8tTwxb-)64vv}cHAyvH z);X4mL1R?%CbST{E0B4`WR(qro(}Zcwrt(Dqug=l9c3MZX|7%{z22;5`P#GhVFt2R zvGsUNPRZT zpu$>ihsYp;oa^#+Fny2Le!+^pnbBu9v*lz41z&XF_y-DTKD>rUbV% zsJw$SZWVVg41TFpI#_(6tmcuiw{SJqhDWHr2@Jr(Hv_sFc$s_if3$av)9^KL=zFvP z_?@pKv~mzB?Zwhq7njEpS067p>VMBES=RgdTv*84K}KIl6k$Qfhwc@0J@z!mnh)_y z#x9Sv^T*G+CY3!P30+082F0!fiNara#XI5(gl{A^9>UeeK|~@MGzRuxL^LkGF|915 z!pC16KAV3&aW{;!08RNf9*vc=rhWki!s>!O1dC03t+QG>6R3McS=K%v2q}}jL=)ah zqGLefZV?)cUyIX^_ygN>6Zdihob)v)>zHcquywQqg19{sq@`6lZM23wX9QFC=wUIa zuh!t(_{R+_;BU#(9=Q0`_?Gwuwz`{*)sOEkTwXpBzT#T?Y^hr6dd^peuf;v+A4%%s zsFV!)R(qoFcosMTH< zK|f&UR0n&PIzOJT(9q~^>FXgnAJ03W!HkNN#C9c!?*?VsdiKsHRNR*NRk$QN6lk-P z=6-4qU|Yp3#VI;d9@gaYayyY8IOdXDXDH?WEZg|(ON76KuQ}t!UF)%QEU_(c&D}*8ae6j4_IRKA zHfCNotg`P@_jS5|IJFq`g`4zv`!$c0VD!V&G}Hlk>A+5Wb0`k;kyikiF?E^s{3%Xq zUtpi;G$(woUZ1mtN`BCtw*q%6k4B%4?G=w9>_~@)#A}ConElS_d!b-@(6ZcWN`@Fznp5}lUSOZ*erA)m@7PKGM(&{G9z1-o zy!(CcE>FJZ$vN=KE96ull&Qnaz^+@jmQHwGC6eX3#4A2=o4?lWrk<>i;$x=RgHtKD zvv0dF!7_Pg>O586a4JY32_MDfiWAYaGX<0x`<}{}_$E*Sa`m0Fh?uQgHl&}rnYRHS z-gB(ncmLtwuxd_yfV+5HJ}fJp3HOjKl?vUA(^>o697UgV45i$&6waWC9B1U~Wy`A_`-Y3XY2Q=I+dYH2W4s+N0y49>GV7tSm zD9j$tH;(eXnpFZ`i#RkiU7r8^XOtZ~x0l1mQFagVJ9e0fJC?tXG1JbV!~z2v6DaDV z@aPof_Y?=(*%f}^p*`SoE+6?Ik>jLck{SPxfBa+R72o(x942^iInD}%V;ov|;`pI* zYWirIS;cDDD2n7zbcfOM+yC=7Gq7S_dV9lhRs_$SnlIb9RpCp&_)E&CKlQOP&Va(( z-u4z`g25gRK%BRcqBI^le5kzd{qM_t6AFv*kv?HY_|)KM5@GjO&HA=p%+D zUh53?BJ;;IH~^!`VSLgdF3S&j>umEps{)g5WK-d-br`$`&U6zbd^7d=vg|V$rh8S` zrIfU%9|DALTy#r3@W60QXKHn}^;!B`9jM@EQQl31;Z38)`f1*QE10u}`f_}HhC}q$ zmp8utPs*GA_nXVz_ugOL|KX20>{Bki^pf(WFL`k}a9|$?Jl@WVkxP=Vt5&UM#m2$> z9FX?sfRZ#?yyca7VVqe(8lOH5jg~0$(C6TQ=X#t(wia0SzkZ$PcX;?GgTj=bIzS`! z7j7L%bdJR#=8Od}fICZ03VP=K(7x5ZpQB z%(M~}_CI_9mkxb)xs_X0Yqx?rVmMmRF-A7P0lLPQoD zqzbjPU~hDEAG%;{2&;+EVilLXOd;uLchpg#)d;8ELOy6ZP$6nuI&?qjsqr>iI1yLZpi@AeUpF8w`3 zU0ne(XA<12X=g`~;?^wI|`f0==GSE5< zA-@KeWX%BS)uBC8%e9Y{-y!Dw-r-%V(1|B>0vh+kKPa0$4&on(8bEk^(!N_lNo)n^rF2HXcf8jkb1HNVIF?&vxPS9Oo`5CQqQWGibMfLZMO$beCT!2cn_>B-&X91aiYK{VF}g zV<&WuNfNt8ne4#AB6vv%9cl=*+a&!^$hXUJ{f(lSs<459nO!=ftRV2(va{^RpYsqw zvd4STHEniMUZ#g6D)7}65xQdF|2+Aw5|#Q0-qt0)^xDiqOj9|t5u zf#r5BSFk<(`WsN}-&g+XeeaA?a^o|eO~-px?v8f}tux{$Sz_*hh6k$Ukh63qr2sml z30{PrJR}U#OjjpoC)x5ToOsjm)*pQON7-WXNyRJ!Qc>)5XMg}VGbUR?;j#B+yY+OA zZ515-kD^$$*71pTEXQ@=19>NJNE|W9D_67fqwaPPL-}`rCHsegI5|gNK!@8#EQfRS zvolbJ;Jg*Z<=(sRWsArWRyf?l{`M0nxf^&-bMO0AhyyYWjrNN@RLpqqd+4F^LqG7n zZ)Quwl@ZW~9=N;QaQ(IA zJHGSVh<~Jf;`Y1QQ-79$1y*5jb>YI<^^s?}A?}S_6ZpL6z96&tAGq~ac!7RE-rRlP z-g58#hd94r9d73R#&X-I?<{Y4!yC)9Z+IH#F|04!wrnoDc3f6=T)eBi_q}(P7k}|B z<#Om);M#1@K2Rr#GK_rR|G)#~!yo=gx#EgTvOIr|RR+qUd$pTFYJK1YpE`sGKsv{4 z{;5P-hj{3=#=6GAsk)s9Kk!86;5!nQe8VN_Oc^AYVFKg3OFIsPt?+Kkse?P7^Py7N zwcCkN)*=mEJeEUoh|_@tOJ3yKd=d`40$46R(*wsYEJ~;YR-~g&kb(pPqugr+PMpGM z7m2hCBcBG;7T<@-2b@>j0CuIxc^-@>^UH$3BptoZreSN~3V z&%57UuD$kYk&PJ!aS|u|mnLs=NnZ*c8iD!iyDs&wd^@@u81_l^T zGN5#d{r<|HgG1pFJapjZi7-!yV!wnC`D=PGD$W_{g4sIBpkaQTgO49eSP*X2X{4ge z06V&6OBvg-y{x)uXBl6+kt+yP{N0zOnoS`>I7itxQPxkEEmvMz7CB(!_K$vo)AhL* z6b5-hY!zQZ@LxsF&`XW`xS)MSuJv^$Ri9Zbq(WnQHp&z6n~muJtRhAgbS0X|9|w55`gQ?G$;{ol9}&m=ShX*pA!~%F0=k`--N@ z|6p7ZVhI*t1yi%M#@9f^(SEu~N5k9Rk&ljk?Uv^W?@6bBVJbZ(+-2)$?3B?raaNNq z18ykHu0FKuKwkhg8%N?N&XhsYrBNO_uKHE!0W@_hc-@9DcgBt`;plnLD@6fji8Lp} zkIZu&)B1HNH|$4dNjF-ZQ^hFPgyZM_{(0UkEYGb%3w*1DQaj=T49bXg;uwnJ*({Sp zVSz*`vp(=@V5jp`LdhXq>3g}VlGJ$h*TncL4k+eoy~))~*flvL4P%~JNViIpBGbJHj0%jOMh z%GZCxH?q9?;_~Ldd~(>^^mJ!?ulFQJG)Jh>3pG>s_C}$>q>6t4SPqiJU?(LFL&W z{Kg+Z#hv`FDnI?I|F>Lm*%jq=uX{uJ;5`qNZ$OFg;J#7v(%JPKW=+7Imt4jP^Y1S| z@+1Ge{NgYF`|_XunLlv@%j@VzrEc4$xl!OnbF_8vE1?nH!-*~$ISdTwjLZW zJ1=4&5hZKOMHiJTuGq~9>7NMCFXDUGu1mOHZxj7|w*^5NvRGH1P$J1^)2Muop~$*Q z57_3*t_42E5MEjLOWpW?c`+oMOC z{}sNbqv5%b_Y*~0Pf(b4G3q*Y`Be;u zZzipfN5d)X;yknR)@-yy3zIYgG+#5`-AY5}XwL%6)m+X$2d)S_sAaHpndvev{KF)5<`Bu z41c-v5}3dH_zWEAgrwu6ysTv^QXAe5^4C0Q--9y!86sKHTYMHfe+^%KEC1D9&s6HX z?X*^7AWBya*o9RVn*U&wgKn0w>X)U|=Y{XZFo>j=ZXLrT&^BC_scZ@9xwUw@H-L?A z4e9dl=AL&LQyX{#4t6~4h>~y`BRl4m76&2InZ(^rs2wmHQt7e-(EKWVg7qGW%1SM~ zFacUkPqkLSK^``{fS(%^%pLj`OZv$~XPPv=s+0iHx#`~IXoesSo zBVw8J|Gl3u=TT_x^9Udrdmb~$kJ!Z*&=nBlT>!P!40%Y|zPc2DAK88aPSeCOm@?Q}}IGOjU9>sY2tc43lU(1@zJSJ|mEGL{u- z_dFnJo?tKLm}}T6Yp&cgpfjHntQxFJT4hDrX#6~Q&vSgLY<7JT=?%6S4l0bu z6Aft=uYILv(vL~L1|VWpubGl~QVB0yUT&w}Jd)3@K2j-y{opJtufCi;vJbMP{Ak&_ zVH-(S6+Q>nfj@pMu}l|5c=JdKW{!UlUW#?aewi>j~p()`l{b7-~7#AU;f2U z{aiV)Z!fc$$Qs)wMj2SS{ZqG>`yV{Os*j0s-vj%~6t@J7ungZ7B%vX6DKl;hF#m?Z zySDuEpZMAGlRx$Y<%fRkC(7UdmTxV0-tj5+>TfTbwp~>2y7z%{$6fcAW1PPK&?Dev zIsPItFauvaq->7%N*-<5x;Y2<{pp{*5u6j{>%abM%Vn2eS>EtxZ!LfM*7uXwo_%Fr zq6jm1^2iX|4ldnZwsY&i^wiPv%fIw1_|29}FWbR^XdK7~U%iD(Udn&-=| zbR8)d0?OzJX{6l}X&JRKIG4JSNuI(#$gX>?4czdzcg5YP zYjO8oYr1Q+qz8*!$bh8v4d2cj>cv{=jXp|S^ByJ_4y&QgfUP1Ozlcn+#3%9#Y3oCKJ~^yj}{uc%CXBBl}D8- zJ5pYwwrX-A`wkUsx}536*=h3xa(^NUZt~n^;V~%$)xFVNWui~3b%`CbbPB~{_)czg zYqB6*>a9**YYgB425q(0EmR(cb*9X+HO773!^|wo8#}6JnY~{?%NCDR$p`l@=MZ4( zDEmP2!sr{162CC=iZ?Y`X!43JVXLWO#!#+KO>t$|ef!JNy|y5#l9{v&1cx~)0oe3*I$9STxOF*MW~+PLelmju6cG)bhh@{HjN>L%+W z|6IM1`bha8p7f>2ms$FBtk?&R<@amXvnTyPdG)J*ue|gnFG7(*L1n^c>i9|eYU6a2 zxucx(kDMr)Vacrup>2cb1lX5r+mTe*7RIVvv{_2?qRN9rY8t`3J8OecUaUiHZ=8j@ z;)*Mn;oZnd?hm01aHySiuJVPlKE{l;r*IEJpMBX8CXXhWEq8T-3WNTWtD%kb&9PcT zyfSOKLhp>dzv_oS`4mdwy?j$aa2v}O@ZNRTU7Ys*^s;^TRa}R6nw1P^STV4c>+hZe zova+7-|DtCw^EF;`eKx2^E0dpS+j;^?04@iKlAgyTE6^?Usx{Lb#WaiIZ&?|^d$RZ z?62SR$kB3wZ6Tu!9-l#BZ37VD3AD>+$Bxd-53?F$J&Q`tlrQ@Be^!3{TV6)K-BMPs z-_D_ehsvk#*u%{JDHLkY}kjr^?PD#?jstHSHlCCEtx!uA#2L8ZQ4RY<&);K;4z z20kCcJWEIUQr=kKZXj4m5xx2HsVLxx=la;rZ24KpfibBX)6M zOK{Wgfs^`M1DlRH&VRV->TAjizTm~>qMesqPa@%bg0FVHABCX+8XeE#NHZLvzZJHm@sZI6ae-?8@RQmg9hP6&W~6oHn8g zn*Z`h{FdsIUChdvm8y& zx5jUP&eo4HNcxc_-d?zBF-*S!!!7B64uerCH6E{K#gh$$_gcFo)W$ZADe##gs6oTC zI%{u3ZAYOhIP$XAALmPmJZUMfbouP@CVojw&ogN`H%QO_b75(`2yVz}{I)Zteso%k1+!(d{~Fv4cpQ5gP&2xua_Fi zpETv)uBdSE2?foqhxRvA6ukC#jy?9r=pQ+=KDK5{`YUSTQT9*@>51?ot>9Au8%ELd zB=$*8DQD|)If|k(!$8XP@xx_o)f!evu3`RUylkYew2JU-;-TNfp?D0WoZ>w)j$-df z0ScG*moL)k{;IG3sxp4@HRb33^B)F3JuUp8afIF%=~nTt0~?ixrnU01p9fi81dT+S zj=z01`&-sYDi?Ni%^O!4*$KCPpJl*7rFe*w-o0Y@KmXyMm*0HN>&lCsbq)AAOprdI zGpFwTSJ71IP+2hUQz%|l(W&_p789q+-_ks;G?HSoK(GLkKyAOgc?Hh8Bw2+ZtDkvW zleA8*8jTzebJ(*L^61z^^2CF(R;^plcemmcUY%f8S|wwQgXF>h+&mOIgFet>FB9ze zNegM9yfC#HNpNqy?mY7EEA)fU0kg%k#N&zd{Qm3j|8aTkpZsZg_EWDe+c?Sp=+yCS zO*qIs^;ciIEi&RXnd$K?29@i5__^(MBX`;(mF10p@mDFA8#l1+0-D_FWx5X>I>teH zO6LTMFX`bujBLmYc_Q6zJ@6#*)2yOBaA2A}?rY1J-T0jH>es)w{ObRBTlu=1pHa4M z+MKvO!@%tcQ}AYfaV>+@=mBS@$?jDsoXRzGd<;aXB);i?|9RQT66$Si-EpwQb2w%Y z?hTx|b^Y~EFYkW$$0-ud8gsDTvE$|Feoiqz!y(+9Kd|fKt<2PKAgo&=O1b}@yURhA zUt9j7{E@b;UcZ-H6*w4>_iZS6sJ#rltjaQfS9-{N+e`vQ)>V?{&M=5Z`S)Nw{hdTm z=TSc}$70~Ma_GtnJfkpXX+8j+ap1re5CK*Gm3#BopL#$BrNFCQzYGBN;FT3*n$Rt5 z>Nn*m?naKUc#)}|VxHI%DDK8CKMd>Ok8#U)6tuXfJf;o@24K^igE~zwG->R2NQg4+ z&+ysOATD@j`4?8D*m&fnFzh@EU7kmvJOA+uJs^~yb+Fe|%1f!$NN=^tj>zM-4<0y3-O08iXsb9Y zUovoGbmk>It@);dX_iJT$iHWl)Pd_qI(iBI|ye5gO8C{LUObQns+yY?6p9G|sx$)nFFDWkwjBs?fl6?7Ae= zVz2PcUjY5hC=Wof@Oe;4_G;m#Ftt515oR;a1b08gpyCc~O(@cIS1yS^u*M?+p(Y;+ zvl(w$)Kedg?iwr6c;w4R1#D^YGaU`QprD25k7n9{3^rKa zkqzY|OzcaMEX}WDZuRd1cKmE^$?pLkH*3olQN*o_L;Ccq@>_AHlbyV(6~1{U{?;g^ zk-^bA!O#iY!3)=D5nHt_PW>wR;1%^UlQb=HU-Gd8 z+L%pWO+!bo$OnVqp96hx_aHK1Z7_ZNQ=zhBKsyUI2UzP2zMTY7Ey3NzuAlDmvhi#X zPP)Qp5cn6^I2_o&Dh2mWB}S z^UKt{U76;7`jUL}(PZZ_nEE*O(8%`=q~<}-r&^R1Wuujc`emobj-Q<@`7H!(YC3xO zagD48>vs4{{|6m^g>nmu+1357h`q15Out{jd8d~NfpoBo4k!0#r<+Cu|jm$(sW zRRRMMKb0m0q^7Ilw1YW^LODx0@)-IVW(8L>E0{$>&}TB8g_mB>6jIS?=a}GB={5>X z+(~ckev(%FJut0qRj@;kvdbjLDQ*mKFQ|(8S$OG|Lzq^^7A8@KCUV{H8I|8LmW9(d zn&$vuR?DjwqV%FPfp-?g-dWlCp^38Zp@a0g7R$-?o49gmHJ#1HvVp-tmH$QJOBW+b zCUq#w0oJWwQ!d)RwLIn8CzVa>S8*cw9NQ15S4cEDLrTaSX7`fsUG|y2C_!2<=43kj z+Q}^atcw=eH(;LHkFxEtz7o2IwH`tZ#r-5Fl*58@^{ySv_Ma{fu{YZpd-q#!M8O^+ zPe#By$$*7<=2=M2j5|Q(tfcr7f0Ug{bIpIbZx9v!Dg$*!GR|=`eUZry&Vf#s^g2_1 zj1>d>4j!xWN%#@(fzK)d6oYV?`kC2r`;aQfGu*s1%m8fm&8INc&cAscxwP$7xRpnK z_CZsQ@Q-Uxh%7}aN%dy|P^sO|4EX*JyrbOn&Oa~BE!RKk z(w2;zmoUc6_RL9mIL)9AGvzZgoE2a{dxSms6GP?1l!phRd_lPKH#@fqIcIekr=kyW z2w*Ko3~14(=Ob;fW!3?MEQ2P!5AU6#55HJ;ZQ52iORwC17qT~WIEs^l31`si#yRz0 zo_Pbr%xUhVN5)i|OtJ0E+O=yq7;k;K{m#3}&;QE5E4#U-?%B_NF8mx}DgOhxl5aw} zXQ{P=TeshRUm4}FvR&L>F$TX*FeATy-2^KTxN>m%2+Qjq;^wW>*`nfhput|c^oyyx6)D-J&8ux$vc0|BU4KJZH^nLt-)Wn%>08T;AC+f@QH1=`&#eQ#YxxolE13@YpVbU&G2Vxw&7&H~Gx~NE>;^qVgk0+=vEw5J8ANtUT z%kC#Vt*qa45d%ZqaDx2Zd+$Bv10VQc4qJ33nLMF5!7KQ|ukzOVNV@|NHIBx!FkGi( zczq?GNwa)1-NC`T3z{IOsGr60M4Bf?v6ss8(515@mvhtXGa^l9l9dFaKtt##+&s%? zxB`dD#pP#bsW^^tlBvtDD4{9%o18_55ms!*VUupba4G2+8M_9YHlTAfK4x~xle7S1 z{PHUqfn5ZEBtryQfY~}&5zO*iAf6E#13MhXCB0U*;;%7tJr51VN%jFLTviCf!;D%Y z*rQa`$zY=it;Wz9aOme>{*{R4ErFOpe~H#LZXKLyFqp=|w$u#Zz&eP&!G#yS5999; zH@CcNyi1%u#~({#ge3E}rhgfIE%A?qo@GHFOOU^VslsJ`^vlb+T&ZGHrKz!bNgj4V zl--yF~ z$(kBfFTzBj^3{kNjJAe{st&y2F_2OddXwf0rS$VCyu9G2oNFEA*Jqy!L;I_oG`x}` z!<~hd-`+3mjF@H(+usf!K3?{7Qt>7ZFG?QRCY!Gk6T+(9>!xgXm36&RH}IVqOMsmP z8muoY8-5!`Q_De3T{?#~g6dAp{TU%}5r;o#d8}f*Qi&b{?f)D~0?NnYbU8WBGIv%E z?%n4E1brQQC(=Q5&eb`|pknVVnY2|RI{t>y&`Vk?&G_P`*v@f{m$UAcZz6Wm90i@3 zUidc5;D^)Aamc-MCMc}Z%pcO00Y*aD zS5$$LA1WMnw#~yCl)X7u4#103%+lt}0cLiG7*qibcbmgAXq4aHrS5G@t5p=?$r)zS z&A+-50D2@uK4VeV>Ze#V?VEQ;v?9_{P{jpU0;iv;;$xnpC_pw!qI;|>w5^dd;jUx| z0q_9}@Px*~A1|MIa`#o`<`=%O z{O<4m0SEtmnBu^I2}0m1jjwp=&CDg9EXUx%>1pnvpE_K&uySB@WTAW$SM05#U3~Lj z{6%@+``*i{f}_yvvURSy<~D$>9Kd+VrI(b$NB5W6Lo;bd>y`~zugq3KfHJs`T^Y^l z3clr3X4fs7@W=ejoAMvU7JuV8a|WKk7x`2oMgL!{4{xshfaR zZk=o$MK&BftMpK3WpzVRM;P%-ihT0T7jCZHYPj)Ec>65MhD+eZZGE6pu1OyUWX7Gr zT@eGDbeRW^tl|WPm0o=X0d9o)LjDpVgOpp!e|hz9m)9}a^^!07%JPLTerdV>>DQMh zKj}&3H-F>TIf(OJ$eY(a3NHd_&Z|Rctkr~qj&F!i;@3Cs?UVRZN8;#t6xOK$^o21! zO{PpzFRtqSxSo|`k1OcXKqhKAL1u{iRmN$=S98dn%SUFpV#2-YF8La#LYQDL{XEL@ zBukda845oNJGe%u5Oat(J}ZO_ddiqdCl#VO8*31zP>`geJ>nlNaNruMt{# zE+M0%K5p7uTn)%HR@w(4n{W3P<+210;#nHwvapZk69m>b&4{m`_E6o6-z>C2c6E~@ z&dylL3!2A{AGH$@K6EtO#fM`I%57--y&;AV( z2{FEgUc4bri}_gnv}j#!`fkV%FqL#=37@{_@?d{szZ(xs`gybQvq^baXnQ#rh;Q1* zRE?}9W$2fA{a$cnLaUBrp9K< z+$iNtMK}EtXjiWI`EBu~4<8eHBWd`XHtC}7?EU!8Z54Kc`8ly*)w*VKEmzakCBJrL zH==-`eQ|Iw*X*%RdMyVJpPD^ZPPq4f+m^C_`ZNcgtu9ahf?LXVW~9!-JC)Q7a_!AuP}p!ymxffcgnf~N*3NJU-G<3EW#d_AlRe)^j&N8Ys|37G&BMwrx_w`H z;MhKts!Lho&qN12Sm5eAF0&^!_JIgvx=mMp7O84aT6N=3u&UVSD|H&Ky?&H@a)8pj z8ya;VHcRTM$b%C<`+FjR1Jv)<_bSl1S=rmc=QqJ&d=nGS@-t8Y9=#1Ej#$9cmN4sN za?O)a)Ib7AAPoSfF}RS&Y=iJkKDk`m{;h*ghPOSORMD3fLYasDqR4^=i6xwLf-`yD z@vV!ezN%jv$R>DT^{Z_F7Pmr#CUDswK1m;zefu{)_gNfth(Gc{aVxic;Y-RZzwSd( zm`pseA)mFq@U(buIGAK$$Z5B_A_ktKBtu$gH14_`%d%PX*-5&3MI|>QP#)b%qk`Ph zq@1F%!V}A{>E+Wi9*94K)$$s6!({1lqQZ}0Q>?puxq4LEqzNOsw%p1y^-}<)l>i_a;X6&az-`>4@%Qa8FhQ0M`avs6V=_$%RS8k&p zNWb!E9bmiaDg~8AuR7G-K9q9g$e#Jrj7nXW0aiA-GeSL;Iu8^jl)z~jDfm2i!A2V!b{MmWB$S8M$wu1cE& zCF1bc;$8huRGK@V48NoGN4pj{*^1NP8=sqxMbiA8l{`4Qnz@Y{CnT~-tyNU z{7Bi(V9s-Hd^TG)c9yN1xe)<*3!TZkn)iMuy~Y%}M8?l}`LFiwJ1_lluSvjy5w0_O z8OFc9(LMmw_xP-APl#f_oRs?QQYa6|VI-AIo@SPNg3&!Yoi3f5rIEC-Y}l~2%+d&X zQY$ycAR1Ov2#O5jdx%lQ1%$(b00fD{pH|YVS?bayDk4B-w3UMg@hMD=S!TAG5kv4~ zJ|7k~&h|*jc+9%_xhjo8GeaLu$H>&(@Xafz!g4B`wCv4Yv;y~#+XJ& z^0Dy~BAWZ>nx4OH_``q26b8%Vl%CGMlovue8d_bOe6?>~n_Gog3K!`VZ!g0w9{msP zc4EX~Cs30P3}t&MUcw051g1ulXW$G=c@|gT(%>QA9o+-q)moEP6F=Y?%2o^n>JFbE z{ZtGfSY{neL#l;k^bGQ1Y0!$jmo`3aE@Q;dGg!Jv(SC10>^V_Rq&7f>P5eZ7Rh=?pV3d?b3tnjddxQbJ_Rg|6a zTgL%a+qQ7H8?&qCTV`?4!kVcdF|`}SGnPoTS zKKnEDqsBPvhzZnkn8}y3D#N7l?9pikE=W8y3~`RY9Qk#e>zSUib7%R=ulS1c!Qc43 zxY=KFR(6P4X(sD1)B@JIa;=p)_!u|y)iiZHs5A2>flgj0gUW@}djFlgs1T&s^Q^=x$12b zbhwg$nM(H0yEonPA{Lc$XYD;$?*ywNR+0A$Tw`cI)@d*EVrUrdBFnNMr{5#Tm3AC3 z8OX@$l88(4NIn^XbZd`NN|{v=96?r8?EQBV&NK-#3LR%r`bSubJ&!K1sQf{*rN;7i zh+7UeZ@q{-=Pq&f!!y%q8v%tT3)^DTyXsrq?vq@?6uZVu`JT zgD=e7j=1sxAf>^)3xD8~0|mx!91gnZ=QiL>hyoo%9j-cCt!yY0=rO>muQZ+m7I$$u zU=u&$NZx?U!wH=*J&OWg>8;BB2y5pJBkz3+FCFAs@M%|;lP2n@8b3J(&uYEvV1+9v z;00kF95w!mqsm5A%IiSUkTdF(C)2)2JrQDzjj-BNpAebf%5T!m8wZm}-cVN}H^O>G ziE++bujXf(%wE#Tw<`-?_ElfY4Gpj4y2Z;FfE!_T#>w)!*Zxs??H~P7R{MBWqq?g! z8-w9%n}GBaZ`ujyNy#A2kWn8%*Lt2%{L3N3Ywy?n4QJc~@x(r!5XF8alB}3j;K^z# zh$^U_R_Q&dXJD`=gnD(z>a~-MtZ|wsLSdzCgEk7xI70XTvG*p>nqAjj=c!l2t9eqX zR4SF`!IEuxk{l0-9URAY47L-J5XeL@B+v^83s@_wX_{`J7g-D;0Xp4;I0+q^P6#AG z+;Q89C+x(ICwY)%&2vdLNj1;)UJd>G{r5fJ_q|tDQb{Tg2|iWtyZ4@9pS}0l=bXLI zXy>Rf+A+!m*<@A79jyqB%u>J@B&$Lslq4e;#wS%0=1m@x5CJMd$bLA5opia665K%8 z|M62ejqA`t1QP%@?pA8QtxUqK&djt`fTE!=^z22f)8M-mAb+AWdN-Ay^~^`UM{oV* z>?cX)raC*y$VWMwh=0y>^68ubBPbX2ay}3#hMq+tjbrwT5We(W4DN}#-#4Exm;;^b z{dpFX2}qdF;l0alWj?o1=F9FRf+hcfMp2H_rM!vgQ{NbByj%BT><C=~!w|>1YRUNQSsAr6wsH(p#S;WcVDD=)WNQ5$;YzM5+t}`U;z>?2XO@^21pZ-}ATz`wOj&Vew;v)(1iUQ+ z^fdm3?HG+J`B5B2G8q)!bKdhoux%;w6k~oc>V=6Xur03)FQngcq`?6zjWW|@W*>Z% z1K}iFzD(cwBK}1}pwTpnJtyM* z|KI!hnrd60*wMa){q;9;g`YfI$7+?+ryhadC#V)P?dEGXw~w)$dKrUKFT3UDwv@f~ z8n6z`-S(tovLE!?NsD&C>Q-QGe6)LLl(KHxK(GwH-BKzjda76AOAXSVi?-+lfG`)TaMx( z?K*<}O*$uFXD9L0=p{7u7k}S{pP6~mi)&UqD}%Ia))5VL@v+{Ur<1FSO;2Y#VpWK3 zIN;S5FbITy)h7laJk!B#Iz+U6b~S~!1VtW!C4X(}jxrg0)z#Owcfb4HEOwdZz{O8c zSC_OcTeh^n^cR1ORUVt$&;HCm2lh(f)Hb7Rdjf`MKFIdoCJDRRAv2IC)=%E^5f9$# z8Kx0rXuR^`_wb_sMRZ>U!@d(@g{Mj?`q>b9fha z$~5_Q;V-btgE(t|1SjHz1`6Mb?dlH8Br7t8M*l*x?)1G-+%F`rZ}>RRx%^B}5>fIx zyvs~qBc~G*nr{Lus|#^s@DT!KJ2~(iFFPOd4D6Ek$OUoCre>%~XF;2~Dst+PD2TTm zg-<(Hm8rRv0T2G0+MsfYl-J6=`=8@U1o0TT$ppNQ>SK>2p8b84XyRou{e-t^X0vzD z#!A{NQ|b0S9h-^)^~E-7Daw#_>X?UM5$^!xVx$M)||ya}= zEX7VES=qG9Q&~L9VYw=w?xA)@NJUs>uH=_^(qb9#>@scL5KHSvDayzMk$N2}__i_n zkuN{?SHj3aSiF>CTR5ELusrv~o;r0bM(s4Sj2_U%VpWt>VDO%T2Wj;e_k`<&UHRrS zKk5k9SKBk`GM(4BiSI&;mXl0FpGE;*c$&k5IoQmJhlMDtr&yXE1WB-nJWp^c{L)1j z``lxGlsJc<-qV(IbMR_bHh5C{EZ4uSU`FhLPy8XPC)w_><*K#{1N}4u0#DrerMCZ} z2ij$9lk`@gnOWM+=t2x+EOBtenQ&*Mxpf1?R&js4bEz{dQ9hkL_Nh9AArg{6oo{F<1IM+syaP*P8VUx(k1~NlCFg~x%dkzWjL)8^ zRSx1m(vOGwb&@6X-ZZ_~Z7nk)x|h{G8@RIWGsx(fcHMQ? zwJWZ;GG}&}$I+vQISHS7aQeFT;Sc|}cIO?RZ`WOYWqaLgZj&JN_5JPbfAX!Y_~9Em zpW3-g!gA=WD;pf>xP*ZY@poYD7y}-NSq9vQ7&)qT1%^;|{d^Dgme34WoX~U|L1Ym@ zkFiX6j8<3(=*X_}t8OBHoT(O;t9AM^@EYuqQ|db&T!*^hK4?2GV^Go?e{$#@w96ZHo2&+qMpm7;!pF&A z$<%nyYL*N%iktYrL;lb#`)*j57HYx0?XAFr#zJud`cE9RLivnHTW9%Gt}3_GcE|ab*7hx5&5(Htw$Hr zT@=G!qgn*>;}ZgXUktJfF@`-P;?zlIxMe<9shpz0SVBi3H%`)t7=IB5Rcm!Bt=t1o2TAs?be7V4%N+E4;)bs{il{3H-!= z5@V7^Fb4vBkAMu{{ZZ-atG`#a@}~HPh?^n*6)=7M9t7WR!d3{v}8HyJeSw*2qV=O;GWZmr35H04nLE{2I4{hB6{bzAJfs;i0mw zGk$LfRT3xja4)Lm8M#1?b0~=(xG2lEH>q#>s8Chi^J~(XLgnGPh($P3Srw>wOhQ#B zs&;CU{<$$O;48=h%Q6_{0Z(`jT>Xd>MVc39ymFFv>h(BIwNu2MAhO!FjzcG=*Ae{% zUTwMWqdcn+1U{f-+6p&SIlo5;ch8IR3{5Ogf>;dxL+E)?pvAF65zb^BXzFk; z1lgXpcYz(0-(OodnITyCAO4r@RaoKL%dGe$zm%@HNf6Hoc@tWHI`zP#U6+%+%Gr$` zWiPh}Toq29BEOJ5uTOCs4hKFmLu_0P3THcA&9{X9xa104QEc6x>`aH>rQgzqeDwAKE<{utY{P!SKScht^X^ z;1m7gGWeu%j{s*Sp=T5wXQpx4@&#=_GmMWv@^IV7A$uACuYJ|+Z4HL~CqDdp@A@g5FRk@nxnlkx!{MZSM60f0S*}8o_23BylSkS>BF#K2P zHoi_7>3Sb5iZ0-}OjcRt)m4@nP#(Ihr}&)Vly)@k46rB~$B()18^Z+r#VLJ?I8rFW zim@Mlo8EFV-=23eGPAhcCX_(3BfZJQvG6He#kal*gGS3uBUxoWNu$4*zaWV#-js84 za%nvq;=7(?xHU9kl{jhiuYoG$$9I0+f?zzO9bg9e))!rcTyQe}j-4E$cLi7K9d1u- zdy;$OA8V(-=S{;+2KM93m~trOUX1&LOsXwiLiqzknLUO9<=yt~v0lmcljX>~v!aJ{ z)dGj?Em=XH&d@94u1s+6wuFI|<;$zQ$Vyk@EThiOIB>vi21hs?QX_Dk+i;N!xCv~} zidYF>*}i*hKX_ma@+U-~VS}^vmDMWuKe3yo_WRJisSoJepS|;u_R3ptH!)Ms zK6+&FQ=j^HyY{-P+uPpy=JpiV;cY$jMCGMiu?<7L0^oz8$v}mJMl=qt1_;fBd&7qV zOUkDPTX+Oted>Hr@}bQ#tMf!kMvODf!G0C5bYkUHUBW)xm3SFcBA&9M5ne_&asb~; zZxTBHh?9OlaVb|bb%ZM__Qs`la1z;@?K~Ox)hzruh=-g5&{E}1-4Y@@M zkB|_GVjKnL%K%fO-KNe)yqxdm8LkEg@dz$GM$%0B3;{k6q$#xtlT+yKm0IAavYm|` zj7%0jt{eDP@+>7UXT=0ve)F-f08LCYQU86yPN-^hGTt@7k6Y|ZExg0oK5F(RAD(**uONJ&B zrmQDD#_#hRt;z2WJB>AMfzJA+zwsiaLtBt~mv+KV4?L-F%1O%Bn4~d|vk~!+CRQ*D z8+`}*6o#`&t!OXc*BmZ}t2#3YNw{O!$w$Hm=cuxin$0?I z)UQi`lv=(egN1_iJ?(G_z!)zgkIO;17zg<_;u`5j?{lL(`&Umm|M~1GzX~zN1Wwki zF{RQu#E}^TLwr0J85toy&JHgbFvlZ)=4V|zz+UIfMj6K$6P$x>Rc@u&+Vw7&I+^{+ zedb!Q_O;W@S_@xT{;Bf&j4arX{I_~Pb3#7PZ(PTVf#(sriOgs-ANzt`)MB~Us;l|+oW z@C{(Z)mSyIx`zs~r@t?RJY#3VBg&yLk!Su69Xs5XGTS*l!?j-A0q$PawH$>bbt!O8YFvG?^VeEYdJG^}(WVR`EDFD|{gSkVJ067r#vz()ooc@WRyv8nPNC**d^JYxmbO;zC?_ z4L?+|{fmYPPn|9Ac}Zhdbso7p@6rWf z?JsIKZn`Y{@n;$Aay5-Ed*z`!hOgygIi+5578U~o zCypO#pSo`shd3_b5XdE5tLRmXQ|(jly}P~i%~!LsfPL*ObM~JrUaU{2G3qVC4u8dp zmF+M7*k5RW<;Q;lR8M6Y{Wi81JpAa^_WqB2vh6vrudP|Po@L=v$la=T6vN*$uvT(F zJS?)eQpjp3<_(Tj@jNfSN~t9<|(`Au5&B8^q_pUBwImXLQ}WgsmMA{bunsP@d< zJ^uPT%kFB1;76hu)YKsd1;nA`-Ze6FD%=_)Gz9QGw|9Po-^Tc z`v)I-sJ-s>uV=-_7Wi}~=Mmj=_dVRwvL^#5=9Q~dt=IkoA5r$*|MOk$}I%%lG=LO5LO7X+_{ALZAm9 zNo$(n+s6gDo+gnMr%5N^;d=zQdrZcAVeiVc4TOZagi+~N#D}lGe$$=Jf%Aw$=h+Ks zgp}?1ZqjcOc9ts+Wmyu;FXerT%HQK94gezyl&kGY!l1$TC_pMA`CoabegRi9>vujz z&;Ffs063c(($4pk=FYtNpy$UO!d2v+-Hqc&ll950?D&!&@4dbWtMlyH;eI2>kSK|n zhoj|*pXHK1gy1@H*~pVlC9>KQc~vd$z?*ZGk&(`F$>=N;&WiRm@fb7W{N>we@LBOE zQo*<0E`Bu-Uce09np|Oa7{jt1-;+Mnc76ZxquJ{^!~Nd6GPbKMlxGb~m3`)|(~qbe zb{bWPTng;H*;1v#XL=3dQdX6Hq4EQjv%pwV&{Q9h}-{x5}&h;J~5}@8OD7++d*qRtjFxr+?d#2p-$y~jq zQ_5t)l7K|#$1s#^6xL;4g9o0>!DhMZQuHbo&12{-YEM4=NW1j%%VT&y`M?A1lFe7= z5aY|amwq{iiFrH0!NUg#2Qa*wfwmKDp+9 zJguu5@ErQ)9p)OMrXu&Au$;Cqke_{ z#F`69faPClwA%7`dij>(gBwM4jJf!zR`2t!;oCli>= zr!dKocX82)H~6uH{f4VnwqN_Te+#{TrhVrdZ);2W=Un<#o7cAQ`@ZjO+jnjc&rBzT z#V}$eH%%-!eF8Z+* zw_+r5xR_T%aGl*0OPbwZFFjNa>Z4m#m@S>TnFQfD zL$9$YqrKwQuWJ9{H{aVH+i{3`vxI9Nk;P@J(Ct0D>uJWPjx(ruxLry9#}Dsmzw*of zrd@x-wHWkkn5jR;DmS*KaI1k6ORH9|&TOsQPAnI<3bp;p6y=rrNyd4~y(%NiBBg`B zWuc2$@$~vWav^Pt#7%i~X$XukTtnYM(89H5 z@+0fuARe6$K8qvNE9jRW(rnwIeQ0~I2)io=y4eBTS$tY?;(#OhNlUKJBaMR$4s6vH z8z=r;u~20}@}Ov*zKezf7qbk&xXs1GEX~hV*H>SAP5Z6i{LS{$KmCu|YhLrMTywZ8 z;r27Lw147e{nd4PgctOssEA7V*+1qkG5(jg&;*XQ)qQeOnEn;+H2@wiPSGA>SMIf;ekD3u0i-(N4B z;8hSS4>Q9Biv;sS!S%S6H-3pwaSKg7N+8NNpLwmcBj5ABlrZ+-f%p+W@UJX*0&(KK zr?_ZOvMvFx*>;!XIGbo=lLL7?oCpIxC%1ygDYkBijve4BmWlO>VMCB5lE9N1O4Gq7CxS<(bCUsQmVY9b0eQFzt+2So0ccx zmBknzkS`uUt)$I*o6BK@3xWa zJc_RB7c^=Ln(b5$2_1lSocnWBCg;LSRG*<9Jzsn;l&AUD9qGlH;mO^pj8@<>Uo#`c=e)>6JDP-dSGxho^&hj4&`L z;z}i0#N>@zEG?ZJuxCCRD)t$qvuNEy&<%L=v|Q{v#3A_TM>}d8;w)<9DKdpz5mz1< z#z)fdl4sx^Y7cd*xTfUy58ky9k5rBq!2;@7v$l zzU_72!o=GlWPOIi5}#;C_n(P@|CTqsp?&9@-q_y$why&`_P_rMXJN5zWhqx!d+$7h zAT`Sjo|K1aHQ^rJv8~w{H0-?dt2+FYAa~ z3{pQLqZ+2vHR5ML4_u6w|G@WO24TV1Z9MLU&%Slwdj6U?JIEn3BKsuG3QN;6Lf6|A zw+a~731aJ^IEia=Aa4iwNSb^*ZGNl$$sdjR1*~RqFTcDJXLW+>ufM)sea$tAX}xqX z=Y;JSd=}T>mog`c4(1jA>T~`tXyft|9`*PcSQ!#ZQ}}00-fP>}AS?K#ZVToGx{G7j zPa-j*90DvLMs63f{|c$M3m_&!0L3yP!ow(?=35Rw(4X`&zm^QiNZ<_2st(YGtunMx zR#c44)m|zGK=~^mI1b&A$vP^!MS(W8@NNz_cpe06H-W-YD`pUXs_mXx*>82kfkvmQRn{pXY%2 zg1m%FUN$0D6dMlN=`tSovUo6tVRe$Q@f@ing8UtnIPn}+GT`-M7WtrUtI*3R#KN-+ zp@+E626Xv&L3I8xPCVx2z})lDdM-Yup&A27%HDWQKGWq09#@ZvUtWzHQK~3uBa|C! zhw_nk<&1ahcCs822-{h*t{4^w(+y%X7{LSR3woT3)(c4}Ri+Jo(ltbxENJ?Fr+p2Y(gtR_Rr7^3S%Mxi*w(6zf&1qo|p;@+uu3Jhi~PZ!yo5)0)*l z>12YS%dTe8hOH5Uo?u2VI+GR@@WR_WlR+L zA>IgaEbXKK06+jqL_t)RZH}ktM>83+^>I9NYo=%aI(y|6QY!_#kZNEt@S=MCc`1E%Ka5&>~AMvU$HR!sD^ z+y;`WED11uoP!e4H%%`pe2bheUXh?t`jLO~0V;6{wld8-JhjNyE?eDh_!HmTKL6P} z+gsoCU7QuMwr$(Kt3CSYBaw0GF`b6eQu>G8ySBG?edp`iYhV5HwrA%f%yhF=mQ@go zFm7CharYM=ZcjdXFZa8@q<#AvUdIytmF=JZt6yoy(cM?AP`CGhRtI*RX=c?3v-P{# zH+KXC$ki6Awi&=$?|INSgzqViag){B1{G}gl$K^5Xnq?cxx(%1K zn{T|a-T%O&9Ikgs`^tk`+ry7P*)HLF$TO@cV2urD2Apggxq)NN3gi(v*>C;8?~%vu z&&>VJH@^hj7Pp-{o^A&Y9HxDm<)BHntk9<}S+b1wzyU=M*jt(>LZ8(Kb*LS3gbXS> zvy5Q!fOjCr6ZCVPx06@;$N1;Px{=#!n9R~mO=C=k@ zfXx7icxD?4nQ17-kOY#r)SrVSz*WBEr`$Pv>>hjDO3E5p@b(RHs`eS!pk>?Zd0`H8 zS{pob!2wSNZiFXwNW%{IzBqKEMdx%PVu&%00ruz zb_RI+gkWi$1@9CbFis7+lm60%mpRRGc*W0rb=iu7kNE2JHOTr_`HN-wsh{cO)5UZb z#jqdn2QLYcAQ+{m1=`;U(RlNOS1YQ7NsIzKbByJ0jF_dtlLG_Qy}%0oz$n5EmT8HW zUp(~l-vomUAG=Ct^uAYX2_3^i@N@5sBgc+(DKG;9#Q0$r|eqcW7Il|S$BS0l}ap*qqU@lI06OO**j{E^4c zKv@s0sLv4bk7!V6eekx_r12$i_Jx3K4`884-FqO5ssAeN3Qq-a1&BT;Q(&3*R{j=H*pk zL%b-WL+m6!4~#hg=YCiYV^^6;znyXTMxZkVQ`997r0gBuC?|OwAn-^FWS~K>-br<4 zRdH0=_pmYVgi|p?U4F)xeKp<+#{uWz5xj=?UdE!*@jV-lLi8-0g)!ef3r&+rCg10S z`D%TS@*KSkv_;_O=4!ucY4xZn+xZn^ZjxvH>aY@VsJp)FFaKTssAA*6Qr6+cYd5j% zmA$YS)2ml+XfJ)~i`!Sed|#y?e&9v(LP_M?KEs(TmD3FTn@8$U`Pr9b8y$ktWnTr= zw!^+dZghDyz3oQ-7C-&GL87PWvpOEW=1JK}Z=VAkE!m?S0Ja=OeU`iB51gp;V3s@M zMOzci69Pg7PbV~zj`U>+3deutlx6Sd_R28KWZuCQBY&0`6y$9HxVSTa(pm_)LWh{L?LEpNc>$r{`InX}vo4?MaHHtr5AC|$( zl^7`tmNR?Bm352RGrbsNYMMcUWwaS?ORU*?57xpkLb29pc*i^6)$Z8(pW9w1Y~&;8 z$-k2rc~#G#5j<WaN}qc73abSe^y(FEbC|+f2u$QerQXD@BFTgj`e^t{UiyodTR`zmp3;?> zc8x6}(9@8Qf6&jb@5&Du3_OtDG8oitluf@QxA2gU7!~$U-H1~6&9!|(CvJEddm6!Z=WyvYZcH3^YH=dquzxeNdx4r24o7?xi>uqi8)~(#t{zW;^F{-3=0ej?UILL3$o~PUO zFS@k7?|0tYzV-F5X*ay+CT>tT)$X|Cj`ql-+o->68(6j+UH%N$GHyWT54NZG9}Zos zm$T}JRVUNXvSb-$$SMY}-d@3361U%eEx398-AT6K9N`v$eeM4H9;`{c%p8~gL6bol zF2+zqUv&VTe0DyyyB%bI{|qaPlr;w>m7g4-$G}K*5)xX@8B7{jZ$F*cck0{;4BSXF z#MbJhnmJcqVuX^`K~N{d?AtS=OdYjdi`)Uzyd5+ZX5?&;6OC%~PCDW%(b*d>G308P za%g*J{kCn%5>`rvnw1pEkl`>g8e*q}~yh0|Uu}*9s?&!k_jVPigjGJXcVNlrW5} zOnNrLK4f6U>UC_l;BMEFOc(xA;ycrsW&1vCt$ zft}${4+W$~Tu4j7oN`2lxqF#lir#4_Js!o{fHKr*M(MA48mAYCj6Ij@!eSvDV|aZ@ z@LJT4P$^EbtZv%bf+REp8UXU}yTcPc-sIybm<>H)K0~J!pUQ%)j1maT!~+dRGj5s+ zo~oGdr1LOp{aooacR{y2YBL*(a$xh_E^kKM@Yyy-j) zG(UvflMET0FE3%3B8ticGM4wCvW&x$K_ZtQiK}}cy8%!h!9id^;oUI(`v5>8mr&}a zjcV0X5s94Ha13}Q%K|!q-Q3rK;<=u4zKn6UJ72nD;oLOOg2GwAgZD)F7E3f(Fb!yr zj3wiWB!t8l~R0cg&+djZQuaY{*3Eu8$HGd7!QliAQ5=)Zx zS9mI;#~J*0h9k-!MyraMagCvZX^#>5fEPuYdZ52XiS^!@A91WzVPl?Dr>x{Z65#lg0%^TVDkB;ntA z)8#EbC>c@oRW@*oXs;HWRQF(Z%o%13;>AZ#wJR5`H z1Fu%IG}!)eAt%v8XydHzwu*s?8F+DorNuK$UaUa@W;?b=pOc0s%Ky^ET#bqHy$~bH z!|$R6Md4>3t;?I)EA2IETdusez5J!Ow14xy54OuMS;eg9er91c?41~K7GA)>p`6lA z!0!|6an`?-UTBNbK3+v6uVYw;e1F2N!0|0S@;SWN&db~4E1rykI5S@>Eif#JXqfSd z%DaYind5H4*YKO-DSoz!*iSh|7a*9F7ripeBR~i2L zPyf&DrfaWkXHIa&0ax*PZQX{A8{4||>vMpmE4UcOA~7e;A3D%(y#5-Nq))el`*tA; z$OLuE+4`+d*1hf;Y7VHqg6$a#k*|YCc5pb|RJ&x|Y6iF#w4HkoWdQkf411SdpJ-QJ zwzjQbx2EmK8284884mH=!z}(&Pd(kXVMN;}f8yhR(7ydod>a%_Vc;R_rx{>)@)2PU-$xBc$c?j7;Fze@;Cz#++*K391=P6 z>>cl@Kf}tCCG53t4)8D=F4c%B<8myY=LW7LNA^;NUJ1)g{>IBV1)ciAfPzB^RMK*Qa-L92;TPaPm{+nda86OUtT%{?L;Xy2ug7t)&8f7H@^8eiwLUKiwUdRP8BFeaXE_k}?* z-V>iyNXu3nVw=ah5&q&NkHj%;1M;|nTTqsRzb%2=KkR4vd0#zW^Cn5~ECl$<|Newl z>VLH@g?kPjM0Om+@L;~2D@K1NjmndKn|NPLcaaSHBDM&&$*DI-u}-sGtDT`D(a>j^ z1&3QWI^;nac9IfgC*Wv)j5n#H>}>3Xk`6FsIWEu<1B{?c30IzeR-^CR`5Z+@Lv_+k zeGs=eujnTomms< zdiv3mFmfpo8F}^>fDJ~Tg=Q`~bbdCt~ z;-BkNl>GbpySeyJ8uj899D8|JAzxIK=jJ{Jt-pL$>D$FMQI-_6Hi4%C!o(%B6XwPamTb zg?J<=6aIMxPt%w^83C)5zibnuEpfG>D-4&Qub|jqfGldOImv6~G}m1%;%0D`1iJ#T zM6yeUgrJn7h|7n_98c*>K19~fJ^Qv{JZdR#20>8Xfp>{iZz+z?sH@4vj)rR7$Hu84e6A3%_ zOelT~yoRqNskR+_(*Ns$OPK&SC_#t3tN_AD3*V3=HhPl8l?0?^ z_Fvj&T|Fv)ld}-VeMSy!Gsz%Z;+-}#^bvrp`4{-W&T10kh=AAyf8mjrG7}V%lXO%Z zarIr7IHt!1U!UM+`ua}fgqtdIRFMpE0&z$fVs=srI#*Ypk_m3qB{24`t_^Y z?XSMQed*3G#|RWh<$48s@=sDeJGMPZnH_J3j~-$G$J6B3waYHw%yj6nY-lWt)(MdmUD>RJKy=I7=Ut? znzJ`O2Lk@1eYZEgiL2@MooJu=;-d_#dB8O*)Tlp8IMtq30-RX3?W!AAiMW5?@?Xr% zt%o}9+jp343cHbo)2txa%#89XW_b5-D+Z_OW7uuyoPa|t*?*e0%b8?noTc<*ANxT2 zfgkuWRvO)c!Arddr&G!~M%pwhcQo#17<}^(NsVsrWG{IyY15WakFkz;@_wykVl@eM zO5@pqPv7NJ>KApwxaMzM>x2d=K#@!33}*2jgI<4J)j!$<+bipoyi|-B2Bw zIHx`kIO~8S@y-7@qahlf{uw{EoDGDPobW{+p2&fRr)fBj9MwqGh=(CK2a#M!aPrg) zJTk52XZ-{EP>*YGzXOu;#DO7T&<{9(QS}x;B21zf<2_0@l$GO(g6*9tb z>xS>L;-mvZs}{0Nsn4n;-}GT3FAY3SGX1)~vB6yioN zz_13(3kEY0%#;HklPk;2CWAuaO8m4XmKV-%^)m-vbV9C>d_M1=i(=TPdI{FU>3|UDEZ5OLqihJe9hH9>r6+x6W+hch2VPdSsLay1^}O&Zrk%|e z{Ua9xkR;*Vy%ct)_GERZCzXoiQ&b#)4QVPbf4f0%k`l0b3cuqwdKvi*7@H0MA_M{> z$t0%1FMf$=jPpA4^IzyE)*POU5gEb-%3m>{Kh6vLYaJjBp<@stc>)JY27Djz7Oxt0 zNBN-ASrK{#u_3gvn22ihasmsp&&}7A2YDyjkYvuIBQ(eJkMM_VfZmZDJ_{*h{##CS z%i~#+Cb-JP&R<5Bvq87fp7a}sTF&G}nU3=&oia}&Ju=|&8nqSH1>*zPa`Xzzu1uMu zaP;>tvfw)(7h1G)@Cc0O{*%0l8FLbM96J4l7Y}C_1KeNUc|?9Adqz;{``RJgbF#f&!P0w` z)SNsI7S6J`%sT^hYGBIkps=YVXBAqsvw{$1Q03e@qx`CyWFMq`448O;+-hbwy~BRPC2QK1mtWE@ z-?+M6zHT{7;fJqP+j(k+FCZ#4%X15)%@ZRu6 zUaLnNv50|yB?4st0gXL;@eF{&7&xE)^1~QDhuT^U`=?n(?aAV&nGv00ki}bugs*WB zrJASq^kT|GzWZnUc@PpQZq_80{* z@bS~Yj9$mpU7&;$Cdmj(DIz1{qTINbJKTWoYOiGGfD5mF!C~Up5@ZJ_LX`QdbAXfh zh^qL-7zZ}Mk_W#7JZU11gAWOwh$BtJ6BGpI-SkGx3aFv4RH~%T7-;~FKctm54W}bJ z_p*B8czg7*{aop`z1?=(tq2kWYYRCzZsn?+EbkytOh)i@U~SvZr?~p-K@PWLumjmY z%8aKgCOyb*CwIAvhg(%Gx2JdS#pq{C4TC+a)-Zd&izDNMtI;eIWr%ANS(^Ri6Hm02 zEEp4}#?mon(KYlOWS&K)J%?dt_6&#Eako8N0yKsWaoF7%Mz4;rI>77dEc=ut&lwE% zrLI0(8+7Axhlr_op*kzZDZ!%w#)jVoLqa|4e)p?OZd07 zHLU9KW(t?RJDF)YSa%Dyr^nYpY`twu{eYj!p9ZS!PM_t4ixzIe3^%XRbEsp)Ri0w- z^0clf$5}-}GV7i?a&3$7Ku>3|t1hkJ;6RtUXGuRa>y+KpOJHRt9{9qtEj4cqPUXr0 z4)Jh8Rv0?Jt>enXQqJ=T-js#;>1=;9=t?}mhZo|jt2W5C0&2+9JoF3Yp@Vqr<(F>x zVqQI6Dq6nk$2j8aRt>i;)$BO=QLSB><1Jgu7KL}h7vXkKyn964wP9f;0w@+T`;j@^k!0V?#npXaoIPjvI^AS*ODxEipXlOu? z6J;5B;%~}tV2qNPC3&hCSXrg9Doj<*ga)BR3vh)tm;weFtp=JnbVEZV0(c#=Df$Ey z4+4yK9@o=Il+>#)SN0Q$IzGY}g`WrD*VS7-Lqnk{sv*Yb1U34ma`?0&*k~wIj(lc6 z&UTRq7&Xb3aV#4cxrvikLqJvNlCN>xKiY34FP+$;B|MqK7&$tl?G{*eR1C;y~iFC41Iz>6nBoZXM+=Bt=)xcoJmi zrUaI&f#mUb_kS+W4)wXDxtMVa`$-z=ear{jSj*nd2y9WPF0LcLWXX^4C!F5)%gUUJ z%lh?~w3}Y`YG%b;R$hlVEobI%|K5X{?Xqlb<0C($6`Jp=61`uI@DBAQu+uLSJ}9Ot zdtOP${2j_HOEYm(OH?8?1jqPwIr3@Wo>?X8j`^c{rY@m&M>+St_%$n+Wm*2>Gc3F1 z?=*LRFP!3DWh~#tT!vVT1n^s|xzN5lJS90TpoJU(yqRiUmc&(@=r#lU2T!o&GMj zuLBq1D`o3UU}n`Aw2)qvdA9{*MF!=cY~&#sI8ae|kSE4!EnB92l_Yt|h(TZBB#vS! zUcn6*F>>+sTjYJ@b;u_~_4gsHqVkJ>$p*hYPN9cC1%Vs;6DK-0ykNCP+k3oy=?h|w8v+Tw0#GUw#(OCl9|*)+(K0YNYIfyDI?%6LFe__x04v#`**WU9^Nd2FAfG< zj?U0K+dj=Tb&EJSZia!NlMK3@U{<^qh1jzACyg3fi`zcpfA({qV@dv+tj<`WJ@-ArfqpBQt!FPcgHlya8uqj3jIOr9u22id2zT&e(P9qOW42d=S3bPr z6|c-HhTVIfiec*@#2N;#PF;SAZ3ItcTaSIKTZh)Kzchn@2f%F)g8~+ndg(H+$b)Yh zbIUkrF!#5^CI{Dduo#%Ljq|VUHRVfLuE7&=G5!h$?S$(V9BH5c8OVW`;sdVM zq1}6Sw+HUOmn{f~NQ2FU(JxE~d=&aVDB%A5EbHgYj=uC?nbVdEY;d<;x2>t{SFWqR|4gcX}a<2yZCw_<`rAEFeq~=?dDW_Z0lp-KEt7nt2tZZ3AR(LX)nL+ zH4H4T4z1!Lzv}h@#jgggj-Rj&FaRVEm=IaT6?h(uSappANuzuY42SjBZ1L7l{PdED6LgHKm|;F{&6=l^`AUkT>E`Bh!4FL>H#>K~frMnOu#f zxy)Ew=p+|sWQ)$udv+1(G?YEhK;Z|xY^LmKlqPjpjEr2aa+o|}}y8T7<3Gz{p;U;R>Eqh|q; z{}yn*d{6kmmwd%%^wwXhf?6KkXZ#$a=i50VjH6z>w@$+aLY(B!1tvK=T9}%jIbkKC zoeS2N^68QCjbD{Z@w|uiXZQ=~;0dUqgi;ra_d|IO*%&Xc*0sTnFq`l*NdK`+6r3tY z%TqWsnsfxoo47r1zdLQ>Ae>&ji7SwC_J+=JlU(R9=R}zN2yi?)Jo6SeY2h#Vr=j=T zgcaWLiI+dZ$%k>eJIkX7Ogu{gt=URCLF$mRBq|0DeyJ>F)Sq_DZBTa5A-}Z!xp@w> zNPp#Qnd^B@BbTj=6ch8zq`^hFxD!9k_5(s|IDgM54num%#~p>0QFsV>Eld{kBzq0Ap) zcIn|Kw{zXy-nN5x@4EN?a`^+=@QgtaU^#0k;p$LbCajpF0Tl@FD!wj<4hD=I>Adb% zd@|T3v8KhRWIITiNqFm`0=xg{RFu011G@Th!K}uciD(1O%XfZ_&x}%JMc+DAUwMTW z(t#YB?=&;J8V~9jCUN#z8PHiq%A5Sr04`A}dQ{-k-UCCYk*4wA>9xI00R|5Xl5zxq zGoQW#SX4}zhXV?hbDqQ-$tzI}33C3JFHa5bTV8T?`&&QuPut}m*w}7;#f#hLzxe64 zVGYa6cRk%c{prtQjIs|MzQ|>>T8I&ogUmQ|@5bx4z_&}=_H9o<8*s^U3kK7^z5CjO zciq?i(a-)|yX4Z%?aq51rJkP2$_)>a0}6lA4leywrC5>=ohswe);pM zJ04WMZmlbKrrO7T|M%NZ{oS8xx4!&k?GHcwIR*+m7iJY(0gko<7(F!;>ClDH%B?|%X0U=dgI$iUVY7rxbuEkB=Pk?Fyfz#BpX@!&D=2J!czS!b$zs6=AvL+u7m6479j9NZ0#fWoDWa z_$_M<^)l|^?a;0<%l_8r^X4z6P~K;EQ! z@sqljya>YOwK5M3>v6T~=0fdswHb8zPyRY!U?1iH(i2ZS0gqe}CLmVXu+>G`(53z8 zaO3m*eyWFierc1c5P=ksv{Uj=el4IwI(>{oH5|c(r>7V4g8q{plwuh2z=2tUy+ zyEI@3fbWLe`PFKU3Lm8_aP?b^I*T*PYiF$}jXs0aB!IKuM`dz$P<(pXoimt>%*#BV z%^9zRqQ{I+|KJH9gr?wxi230awPq6L<|x}siKsZeeEh2SaigQ3ISrYN2pE-vumN%>cuAj86!&^~f%%t?L zuqg61{;b$R7I-G@@q9g(Oh}vm24yI5^iw_uOgju|@?Y<$eb@D0{e@$e!m(59&hMbY zGrUQvftDcy+a0>kG^H1HX0xaGo z&cGkSgBRiT9QYJ`hw>JPcqf7YJIz#o;riF(5ATUn-l_Z2Y}~O#_y)jqpksK+3jgrP z^m^dZkq?~qJBldqh%(24##~@?LeKt~l#zi0V*ts#awxnzHfO_mAwDCyOjezMiM)cO zG|#8@x#uc`ED;`_BW8th!W-w&OH1VsGmEe?LiX=?EcMZL#{x>d$kH~I*iuTDvTk;o zfqxH>JL+L@L|oz;_`vV9mEozupm*xlAV;MXvyYf1|MnL-luG#_d~&u6fI!AzLy?vQ zUYitT6)G`W5JAGi@2OrCTn)qW#u~ zKhtK{UCW>h%bcN$GqDKAB!K^chi(*?GAQ~j6_xPJ>JeYQ7#9q{#b+tMHF#qL4fo=S zp(IF~<#k+(P{5CKn)bsFZRZ|8@H=uS>Dz{tZT*$&+gk8i1TJB{>+s=~E0|96J_Ro{ z#%M(FW~ne)W!9ejJqT0axyeYW1XZAq5O}27hyYK!&`_KRHueV3HJ>FJf&_3|_2ijl#+dtV}`HGjbAAK(q zcC#FscmzZG1bkrdEdpI-BoXpu(NgY^WnRm6?fR=$V1T`- zefiU0Xn*IY{#N_Rzy4R-b`I2gf<60t_MB)tc5r~5#@i`orm+d)AZ_)UOWQB}+yB_E zzwyQGH7~!RefslvwyoQ?wIwUpw0j?ZtljhA!)@?ia>=|aAdG*U3E`@` z5RY@PL3|fcf0wVQS$AjC9e8l%!%9|q$j9y5cC<~KHnl(X_II=&_`V;&m_E)*lS6Hr za>BsE5^fD~>&F=ec`PgWTr0$@E+-!g0$Qx4b+!Qr@NJQpz`AEu^I3j)nM24S)JOTt*tk$%&>n`X8G44;$ z;Xy0~>MVW!g>jNxM9W~6S;r{nD;+{iM@U$p54P#0{#0eZKubm9zUGyg&ywDk2g=9!200Ln%o_vY30%b&pzyYlR*Me)|mg3mqBw4|- zA(TfVB98tW_%g)GBZDMHF}gk^G45F|{)Q#ioZ#{~N18dYzPcacAl?q@^l~dYdI{$AaO`Ce2qYeV7VT_ta$I<@A7 zh@KsqOr8zI{A7`pbHW^u4_fDj+LeO2Fikg(U+@DYayiLY>sgOlDTca;XJ8W^EE3Uj zF(-a{olIb*974tb<3ar)PLw9UC!8~4wj(uQMgZ{&yg=(CZHS)(f6~ZS_Cy|Ph)?_q zi$u=*xNenS|Fs_K@;isFc&F_NJPk}>2X_-!g5m++hUJeS!BktsuRR5E?R0(ms8vI@ zXLtx}aCseYNM!u$6F3EiHma7Knz8ZS*J$T{a^Jov@G606b7{{quv&;Fhl#9)9MAO# zVI#cqHIZ-#1wHd8fd7#x`2#rd>^w@iSr9jlN0g?(8_J7-T$>td4B)T+2d?m{Jjd}1 z*!VZl!>FE5G6GC}_a^!L5XP|jn<)oq-K(DG^gLhWxk;bz*V$Rl^^t4RmOp}OkmGsg zHt^omL)8c%OV{#D&MEs|-sPw5=`5*AoY-g}snjYE_6{d7IF>PUV?VnXgFe^eIctML z=WB##$pY#7c5mSt#{x=9x$1q zl6i`>fY0O$X!$>kSj@!6tlJl$TRl$wXfew0x4!nacJI!E?bkkjFNgTScX)XUCDlXo zIK-dm7&*baDbpoVn~Y{)zLR6I)Af=0$GkO7UGW0e0- z{nTG#py5((12`fyl;hd<-#+%q_7I0KPI2YhDS3dU?eg@L2SjL0Yu5{1%fW1lon@FE zW@i2sH{IB7e&^dzyxHH)>H)80{K&_CA7j|}mAQ=|?KN$gM$aM#0K!MPr|u{=l#{fZ zPj{73`H`{zImf6H6HiXR?Q-gpX#CrjxagaPLpH(%G@|J(nm z{W{mj{o?=q3+?;<^xL8ROuP5qJ7Yk=h8TEfC_Bq<2BYn+d+u+)_rZ_0AN|qqZ!fy} z#>`f0_^kgQnQ_MG+PCK*cf9YW4se?OQC6{#rF^bI8uJ&oqHPMk>|=@g$&*LgAAIst z?Z^MZ54Af!|GD;iANT+U-TwCa*MCR*?(cpVd(&5NaNoVubp`A<$wp?A*C%^V#Gj_z`=NCue_>xF?+g`d zfwREY4QO`Y+ex|{>_>Te4d1``S3lowzUiiR?KRh=|J}tI1jo2X-m?deW2if8>>%DE z>eB*li&#Lr;C<(|Z5dRc-Z)_7mIQ5t6T6|2_KZg2n|ZJ@LI%6!e{!bb;; z;9<25d~1(n1q)koxZmAkUcP)SusNU*T#hgZl~o}?_9g>o%H1Bbl!1I#0(knmZRL_B zyVFhz&zWiCn1^kQD^N1PpiJ`TxB7x^31#Tugg6~#kWcya{1SBrS2#Ej>NyBUj~vT( zgJsKCx5Hewx$~(#)Ir;2+cdT&kl!(GMvxbaxs6~sgG}UAggA*kChgXbW5}d`wguBmPPeU3>}Y%U9AHpo zePq@f50Z z4?@({uQj>qaZT{Zd-DnwiT6T(E}mf@Y6dFBih@v44UMrsz{REi0P9sj8=>;mWFqUATwz~_!$+gil?6EbTv!tfm9Z_6;k7# z#1m--NC8psgK@qG!cEW}c@0r}iT98>&z@3Palx^CeJ$S!xN}l}gM3&B;tKCHTI|rp z`&|64MyF&$?ERKH%iYRX&!XCJ-Q-u;Q{K<`JBMTQKdiCcZxZ-3LOfSs2Xd~kub!W| zK3}veZOL*lgrUOfd@Z%l71}r4GB4^F?kHBh7;hplul+kP_~3txjl}JounmAu;fJ71q@V4_*dVbj zu~QFy#I4S{1_(}$Iu~FjPoEu55m4XdFQr-DN84l`!gl|f#*{{lOTnDM7cZC9Ss%YD zE;xdxPs^@QO}_g1X?Hj25@qnJhrdHYUVRhq@M&J!?w8;J#w2XtQx-&wGz5%4g-h?C z=coDR_jBbymv{I|VT9NG#^9s#cO{l`sXK)7wvyQ!m$iC}LuA!KDa)F)%Bm-Q*X)go zZOMZQUSJc)H08*t1Z1Rh7{~ry8F$uJ1-2`(L!vx{Yip)%RWK^l+)z;nbK8nDXd2w= zEkUsQf8h_hOaxO}Rpf#ybvfaM8^8P$sQ(K_9{LS%DmbA7z52{^rVo7lU51aTb8^wi zc7#3ui>6!(kFhV)u(*~o({2n7FE3>lJ5;mYf6{FAccy5D)d;6(A5Kyp8nGT=7K@75 zUaxoXz+MhZTi4$BZEt8F{L0g9=P^!>R)4ekuv6y6fejcO8dFw$y2RLl6tfS`{G`dj zAXT|lNp}Fp)kL~dc)_eQDhVN_u!XlM@XT^ucjNW#wpZTF3?qXs@J?fAn%U@o`>Vf( z5rtx(L%zHTgm#uy2oxc%a2qMpgFY%u{|-R+HP>C&zUv+DYA25D2hNdf7unB@w#3-5efID-uVHf)f`&!*u7ig(s^5e!(i0Cnp-g$4^BrG{9wLd?!|JKv35-bH z5iJrV&jYv8dbWZyTpk+BZQ||fE3cy5TYKAE-q!wyAOCT#nmfv#_Zev8zV>a8f*Xb+ zARP3Vo?b;UW011^d+mmW?K2z{w|(2z_9H*^1MR!s@=k8D*pV6G#~CoW>nr!S-TRNV zqulp+it_U;2iKyA&d7nYb^Qd!ET%u=Iom$);ZL>gPi|{J{Aa(n{qUdviMDI|E)J?= zYryC3YM=SSS1`0rw*7}@+YauJUx3`XXZz?$bnBsRD*~su4(%;(er>z;)*FG|+6q?D zy!nma)~@3E#sB!9-`DPb^l6saduXO2=;`ewN3LTq@ex^6e#a?0ca06z6Cx;VQPJ80HS1EoKYOV)?GH!VCAn z=e93ok(P(Lk2i9+l7siA)>yvu^YC8&&u|!~2C?mz%i=ZEU0opV8q>Csr>K)t3#;Eg z0N*{M;PBzyz%FAreY%3nfBg=!%I3f!ukTxycGdxy1!ouxqduJBDni>L&jmSk>R^my z4Sn;`j)?(}$Q`H66(?ozu&XA(Rob-Utg8nZe2JbzDX(Dm-J0nN=Oc$swmWy;lfe?p zPb1#!q(NRUnb4X%tN`o^0+2$TarVbuH zm>KOVLjD95QYfiTY zV*SFMj1V2`OpxW>k8`5(N3 zUwIB;`jkuTD$U?gv6D0rMlp%w=$bBcQgdzO`*&sLuk^)N!p4B~3L?G?-icT+%6I&m z2EKn1rN^pg{~7>|kn9P*ah{SW8&r6lwU;^0JcNh5&!KZbyURs?1^{8{@F#fqe5o9< zOE!)^ipR=JJb7j%!1K-Ik94{&U#T6>ObKP_zb>K0(w_e8q*d4TpC704Dp=!mW5`uh z{X5V3AjZk69`^6lv;Oh?pUG|_&-CfaG%kB6d8#=2PdYLqC7na#@9ao*a7mJO!gey9 zC497lwZqlVj?_+eZVB);kCyt@ADF@*jUC0ZrR0UD1FSBGbE%$J0U6J$e!S~OGsC&s(tXz+9=9CM!qxl z(wXuu#(}?sIm}e9Tpm0fbTkee4Ue4l4sR$|>8-jrCOACcQv*$YuVBCUvYk8HFa6U0 z*=GOz54KxxzMgFo$CydxO0{hdx0|ltlmpaUosm^faseFttNZAy+#n8Tp6IFkd0_J9 zRnzVLANnZwv#)5czWwEt?M!>{fvp%6C)z7+yfz2MEkDE71nBmPIE{IijRTr;$IwL< zEbowpz=X~apl7+cG|Gpf)!*=;M@*|AR1VFJUKN(Z$6yDUU$DYD)-rnB&wr_0< zDJSdGs+9}c-FH3EKJ=jvwapvXab+CFlprvkmn`5mhv{_;+&s>J?;_rpw%KE?{p>$} zPuqOuhIZK|X2aRa;y}hx_OmM%M=_H8V_6O5#jLKYB4C35WQIIg!aHmqp_7B@zzvI;Pc9{9lLfi=x~sD8iH&f0har^51pd#V~|NlHEAbV zL2})7*RWTegY1Owed*AC>q~EJ3zojS{mjq*O54AOt-b88aMrmGuE?uif8=lRtxkTo z&bn0I8TE~~Wa9=u0zA;K&36Q=YnROeH%i~@B5F?kR`i2?LHgGuya*DI3y8Ap${dKwfQugjE z^Ui)RU4}8NOfS$tCI1YNk~8(k!*QK(^r}ngbw*uU>w0mGS_ci>_s>i|1?WJXtnfS& z^HJYW*EmJ}oo04DZ7=fVVdl|62(z85{HaIaw3s??NjqqlfdfiKBYMROab-mSaY9S# zi1f2(9~|8t=otcTXP9NS{Wv3zOBsclT3C|}+KVR`+;Gc{t19}o?b`lOd9Q3M+X-m$ zyaLbvpeoW9xh;eNA69laIN<<^?erm55X|!JnGmkVP%eNHF|hX0TESB#)|SxPh_H>E z+|>D$_xT9#{HW0K9H$bduF_NrevME8c}z}fTc8eNmwb*PjnY1kmy2T92jfn)G=vCP zhA?!eUo~pwQ|Lo!;tFAS?+N-7!5H{aK7I^odXz9EA4AN^hrKJ#ya(@m*VoXQ3_hh$ z0=$qL@HOEG$uQrMB!RgX#L=d)F!XrlR)DQ3SMgzx=O#d82WF`~*?_V8izQv2b zbX;~`cC7rxk^U(A(XPGrT22n$z(GUz#!u2xzo9-fUKwirDlIL(1 zMKL-7bw#J2`x?(Mi{#aJd-v{c%chqT;BIdma;z*kTdVSk*%%qufKs8fp7>`yi9GO| zbiM3(mV#LdwRu}dGJw#_dO{d9@-mB+fd_RL^Di7Q(@>llgg{xWWw_ujW+=lMZ~zZa zk9PTY>S0JMe4Jr)zjb;!{evXW2^X2?yOd0*L2psoV*rEK04{?CJy}4hV6%5LsunY6 zhtWw6g8H@Z`2MzO^X9gV{l`z<|3F)@i0i#D0v5rmrJVTgzG&yK-Ijld!}6AG+0d@J z`rF#kyC30Ny#p9c7;f-ft7;)jqL*-3;Bl@b`@-k%X#3mRwhX@+j6F}=*AUPxa7{Ky zWq^}9<+drWB-^!nUwh!8oovPj=1S&@F)psSYJILQn?je;ps+2?hr@}v|&NcnNb&@#o40ba@kp2+__M^CgjyylhdCYIx`<`Cs+?tXvqi(iaf?rUGT z>;87>y0ubCn~Xs`?ckHwdTYSqsby{D(sk^mUyqS_q#ZrTtqYttx0)-tcI@J`_kA23hoRoS6b2%@uHmBFWJFH-isuU%C|PityUWi^bI1H4>dMKsdCN82s_<}I^}u%Okax0^ zp0Yp2;9W$A^qzX}>GYRzz@D?cI>)W1m#%ET_mThBK6l5L+U>XBo;}#}U(J>V4~W~zQv6T+{vQy|L4e4wv)ubRMDo&&E8A_adJ8l7OJbO9-OBZM zT!FW4!$y{yvv(S!-8N;{)@@m3aP>{sv|T$MYY){W9qpwzUCYVq%+hlhC$*~`;(9{M zcXTRCob;#?3de~Y7!C~abl&#&E&_~2b`ZGZXO)?=wlCuFMasL$dKP|fB8#+RR;Gl z4maG!K$Uf0drO?xu3@l}`sVe8)@9r5r+08=VMipby+!D7xeVZU`f=MZue4m?m(lu#$KU<0+T>R#`&?ObX za_r*l7<1!)J-;k>bvgN$Vzlh(OsyCyS(bxADG&V8IYe0_x`}aJnID(VT#6D67;!@y z0M3mx`DGBGCu3L#^F2Jx+uVcSWZLKSK4kQq(tKk?p2O4PM3oIB$(M5D5*fdZ%dN+n z`<&$Z+>rj2a;N<2pZSf`)SJI!EPA@Lo)U2`IY_~t75m&C6WNUAk*I@z>L2eK(i-hC z9E23Pu1=#qolRim+aN1MI*Ur@V4)QC#@&w8w#M(Ck1)EMKq+1wFJ;v~N5&m=w0(8d z-9PuIIpze}FW87?eYxf@30%1Hbw9oH>x<2vdietB3NO z8Cn%~XXL0W$fxC{4ESdo;y;zRMbr;xU1Ff2`75i|ht#1VjcNVUKX-%!Ifff)&0aZA z*zoLxq?iqlN7Wf;oZZvv%VO^Wt0DP2crh4UN04zU9`o=_OCJ2fuVz+p}#OcPMlC6o%MB6l~8p@Cv{u zcW-Uq`Ia}g&DUJno;tmxZQIQWqG5{6D!*^r(|Q> zaTVWjj6;kaQIvFelwrA*i0iEYCk_Ts+wB{#Hpyz`yy!F%s&zwxqJi>bTtzZgKjj z^GS@nmn`@1!Y_rM(25+~iLdUAq37*SRsrn?WB}I-F*9eI)J3jZ|siEe4l`oHxN4W+3MEbDl?-Ar@v_XWEgy92&+- zjcEoB783W=>0ySJ6*{|_<#s>3;*iR~9{i{F&$ds0^o#A^zxR{vicOb;-&$5$2$$77 z?A_jffLUwmgR4SZMPPe!iau{KJhx>LGq)||AW3+&$T;|Wr~RduENWl5>(lM8{f)of z-u)MUREfw;va`%?6}sbdUuggMpZp^RKUkuEcwf8yRj+A3@`Hc2UCtG2YgVnyAdfTR zANlCV+rRkPzYmYLP#(wIwb#9<{n9W09Bo6*jC<9YviS#}_+PuhD^79?- z>Z`AA|KRWc&35gz*NkLl8HfA5{{tUv|LSLcrd@r*Ev%?HMj0(@zwxU--!@%-IkL-$ z2eb+M{hVF!%m4Bh+ih=rHHYUUc4!46|+s%)D^keP6{KwyH z8?V^X_U_-wR)(wEfBN_T2M5rt%=QRz^MJe$eBgK6fB3ccwU@o(8tNnm2yT0#{mXy) zKcPQt%*?wtnC#`up7*`?z3tIQ9&8&oUCH1EcflXn)qdh{{AK9bLcAl?cVr2f`uIow z5d05wPQu!@ldTx9y!}<}-S7T$;N>|Lbt8(`8E)PBWc#oG<^Lz|JpeR2j>F8Fotd4m zyEB_}UMzA32?7L2kOU}-AZdyT46zHLB75e4p+j|db#=e4>gwwM9-Rp1#zqG7 zXt+Dyc1Moks_xrY4zOL~!Tauyg-aI4ENnFNA3qj%efXVm`|Y=(o{t6!M=H9S?=gh? zFkJZA&wLJw^cXvg3p%fIY^HnVILfoQsXAi9cWzNT=NOI~j!h;KhepmZorIRhINbEb zA0cd&JbShM-#}rKKIbfr2vWCOylk5kTk}5MRlrQ2aHfZ!{r&tId-JRE^ds%yFVd`? z9c*U4h?wkFC303w9>DN)+T}oXT4S@tMv^ae*hU3XB?8f|_!|D8_AnRgK)0wRW)ja z;h(T7|I?6N`@P8BW}1%Cgx}n7F9PH2!F6k&J@h5}N=8IJ@8Z1V3`<_(#CEB1?IhWW zO7Rm|#>jH%mu)EB@~htq9tGt86h7*HrB}i&5zO$kde$lGGL$?{Z!dd_uyZxsV&U|g zj;|U<`j?`Y$S?7lG*SW0`epxid?@ss25?x}qY6o@rM?wjD31fU>B>rcLdy@S6I-2l zu#8TAQ=QPf&L}6qMM_nUOvpvJb^XjgBV{>Cd3NpG6+4(rTR2ykj8Z1f@Rys~V0$vT1?(I8$K8yXROEHN`YAIa2qPn=~n(!-LZ z@I1ZpB2LIi_(Tzo<<;SHhVz4M*)nn?)R=XuhUW`BNRK7I7l`ziHYn+j(r1%_#b$bv zuHn*?uFJQ(?C(sCHzKN0QjP#B?chF48Ew^_<&_1h;B3-8CcurP3UH{CYPk3(KS{X{kCg;Uv**`9}UmBr&k7&NevUnnXGcMa!)=UDR=bH zk(lT|!O>pyE6QPcRn;{=@1+lva_ZM`j2%ugUFq_hXL+stC@Z4lTBECIOFpc%Fr>q?dZT;I%s8}v2PYI^ z4II_yqsLE1t9x8gfj)k8FqSWGi`ld018;UrrW$fq1dVHLaj@!&Afvzk2(Z}$-FFn# zVfJccrMvG`U#kDxKWPH+$7&j@n8%KujMrU%Rs7^n|8y*X0djkg{iqwY{`sgM|JrZ- zt3W}Yz4?v}e?6 zAB@(Gan}#OH?F$ks(9$hKZ!*c*&0SYca&A%nz45UH&N=C?Rq^p_xLl7<)Y+)TWsBA?r6c8Bw8_iZ0xTRtc}$uT4)p{6 z1Wff6S6<=A1Z(lE0#oK;v@14k-xrsx;ix&X#d-yn(rN#hBWP6Yh-bF$NGs>Njt#`g zZ3r;rUtrWwM?pYT;Z4F8cN`~}zbqSm>=(Bl3D`bjC+Ow}Js|ahAh@$19U_g`?I{L2 z;`wXGAA11o1tA~kR{A~6X$S17pMb$9MP@YseNVQ}iDk<)ns+>Q?Nhz`C^V0K284d> zFyWi#-fha7TU@k*Kzo1-j~*LCTf{8~kPyH2I03_dYJmOP(5@Ej9Xk%PK)!m_GPba_ z!W5q5c*iX;nmgllH{KYpdF|!#p%1?=KKHr*Mu`UEeeZjFTyn{34FBzp{*&wrr~X%8 zeQmt+9dBV<$d>r>SMH8`A3792`*S~o2FS`dbm&kTa@)Ii3x)$wv_PIxNb_=Y#eU;D_rqYnn$qY9sRU~l|`PySrI;f>ca zUJhkEx7OWw<8>U*r-8Vm@vVEm9edD-__0rZByN5EweTwgY%g%z-7w|2I4-+%HEl8g zynCY`!*X~0=&kYko3CQbYC{0jlliK#a^;m9*xK?0$~CRAZ};~2iJ$(-_}~ZMmGwM& zer(@p}0*oD$~;mS3PF9vFbP_!5Kb;S1|~Z!Ltc!mvDV)2EudmtHBMZ79br1ijPyED*tk;WBF$O zY9Z7Ui~PXyo>P&gh-GThUytC-ClJ)vcpiq z#BEcn)%0TF8|{C#n$&>K7IrqjruNS7d>se>8dQT;>ag$AyKQo&I}R_fouDs&GzwK)OFV2S?7V}g8jPCe^h`$MY}Gm~#hEW9 z$8s%bA;+vznW(wf($J*iGP~nL0PW|XUHX6%LUCnZ5JoMmvV4W<@xvm#f~Qi<=E9m` zDZ}&<)^%)dGX1nnJKQpy`xk8^87lYUm9Z*IY_nw9r^9?D@4{-7*oxrl`enVqN8{t? zN07*t#W=+(K4~bY6E3htAb7vm0Oukd2sUSZM~N!Gyii^ThL3APQ%NG+?{c}~48;6C&s#A2UmPH<>9 zaO*zHzP=$CMHy9B#hH-XPL3Qlc-5ZSe!y+Mn@7?KjVJvy!ZJtO^>k;P1XzVQ7I;>+ zD~9ezZEx#h#f>AQ=p(aWd}l(OU07M3)k!?|*!RNN_rkbzAY_<8v!HJTLt&J)6NaLl zI=QDjf8^ucxljtL%{B9;OcW|{+-d7R_J4B>Q;u zPoTUi4&?Z`D?G4^cr4uvR;zaI+#d6v-yCbMx+VrVmh6egACEWPbW3zmj|UI#Oe0~Z zV03ymtdH3X7RCnZbl=y%5&NEcJ}#R*7ejg&;iE1cFt9R7o+<5qbNgj0aThI^9c`@e zox&*Fj22cq7h?R7c4fD1PRtJ;KA7ss6YiBhx<4Mg_iHc~p5J{k+kejNIjjmtT)kpG zWjUPR2hXN{cuVdx#FnJ8dyl%H9NH+?2utC5AQwn`(3tL`1+y3J)i#guFh|}EhrLTN7{@&mH zJMnw};h)DB|M+up=*Xe?#9zHD?t9>VjFJsic50F2T!S`cq)3s5vIyfjR;!5t@$yb-z`3-gFoxn~yDwa{ zAg;aPs_0`?cLV{3g2ijEzY+lB@lDk3J&8m5+0TmapWgi?@@|hMtXBWv+kP+}ee{uR z!jmUqN>R5z03&|*&|y}jPjZys3but@0=)iMw`MQlgB;Dc8G)DrgyCGB|I(N4&a>jL zM)=a%@v(T~k%#jb!u`O}(!W9g4U68-Sh#NO`gq-IUxR=GZ3f1h<;$1E?%g|+*0e>i zecRR?tF&}~?R8fpJ8fr6&E|N`4cFw>rUM7|(&nRa8j3EPZ7&{kbJIL2i8Q4e^tI>nGx| z$DfM96I-yN4`a=V0)w0uuzj0H6&}OV{l&5IiYuYXx5q)wlYi>ThvEb8eLuLK1iuJI z*#5AK{O`Q;9r5Njya6G~`{R*EAI8ptHXX2caqvP4>+H3nWjAEYkKPmV$vh81wlqPhzr4|xn{^2PN;q*b@gnz zrc^oDHo+-KC*LX$C*ZY{kuQ^R8T@f30jKh#;eIW1aWG7Hb%OfdoMG+veR`L;vu#9h zlbfOs+DV)nUgN%Mg0teb3C2r(Y|dF4%J({tX+ZRDjz2BJLMo%^{Rrh>RRDX zgw%Z~doReV@n`?gl?l5~#wZc$rY^m+37FANb5$Ds1Y866(dV3voISntQ%K7@aWdLD z`YfOtF5x!bGMz~a9asKYmNEuZ)yxk?E$paiH}j>??$5Nqepviyq=jif)dB$fLn$v< zBQqx@PEyQ#st#4&O}84pY0bNVbMjQhPJdy`RM%={CKu*~cFlDz<+6T${7OB2F7J3S zhSqJ;D2q673gyR_NuWAw@EDXEf8VoRrs`s(zEoCEBVeXc=u;K8#=!s(m>@W+>Ar0ll|-u zgcUc1Fw>{;KIm&UtKyz5EJ!UjtHwKT4wJiqqc9LKwVdnTj^+6d=(UT2cEkM6W@Wz% z26!ev{n>s9dD=jeBDsXQIz#3&H@Z;~i*Kpf3-8pegX1d#rT}+p;ON9Edx>qAx0+XSgbX+AbH9*Ek z+F;($Iz3g!x>*>Y>s>h;_ID`|-9ca2f%28Hw5L0>FwA@H?0Np`uw<@zH(ni9!zrRY z0(3^u8L7!hW74zRM8?455CSE{0eQN^D5n<8VB5zeHX(+fje;=62;`cX*l)?jZ9AC( zf<)@xijZu>x{I*-KPQHcZi~GKk3q*Uob!7z-id&U{-Qu{kX7=BAAXb-WUL1QZ}sZ6 z>Az$9cKVgZ=Q=UYHYZlCx|o&wKcP%BVcu8AY^=j?+qxHZ{U>8S0=VTX*e1}?19RMt zQ0=*R{`qY=zAb^_J$Z5iXpnn3! zb_@P{!46~4yv1y1d0RY;je*A>f0BLX*hRnwz&KlQzH!fYk`@;)Udqb-Is}5rSdLpo$TCsAhvBY-^qBx zt+&OxwHv70qxkQm&wx)C1X?=dfd`%-&I~lIy5p|9J`~$;yd}Paiu`4lU6#y$dpmuW zzV$RK>ODP&5G1X_C}l6k9OuV9fA$?1>^=k>a}ma=u0I0fJ`m48xf#L6iCDQ}19^4Q zw~xmb1O{qrO^mmv_5H7X<=$9=8veD{+!zZNE(aeEL?0SP&tgkta0u-ows9Opknt#Z zTDiA2+3lth39vod@Bke<~!r6f;o>d6nDKr8pl7?|9xcq&u^5^YMxO)7lLko>l;$b$;f0=5}nceGQhx>X`XqtrJnE z5>3Dk1dSn)1eTeIb%yy&qtqW$Arc{_!8EiVq5M_|TcFcjGpss{cxQ`hu;u(-a^g~g zhUA&RsA{Kxq>SuJutbEb7XIn%NM(}Fdo~1~uL4eJ_L5_L&)h3|xnNBoAPL|vr#mYe z>gv>O0~YP$sYT;g8Rx{dbQAhkK9eZZP4(P-ZS+0+V5ZD#)iTv{xtY?>c!qH+{iH68 zaSUsI*ROJVmkhG3z9gSqd)D#J7R*LhS9fD2#IvqHmdqv;{)?5^s5?$mPNGZYBzbC zf2yM4nUmi9So$KqD#o6A5{>GD5AJPD%2EY8{hd^>3ga`3Mn;@MMU^cc2|yT?S0h9Z ze%`7)>KG+zxz>Ko_hfDuqYC~l-qdq*yaM+$pJ^{ru+aR}xixkNuM2bfr#9+nxh`=)mEe zG+K98xD%(qZ$;Z+f_X>_I2+(Ns7W*rX2Li>!hYY*Ilb|=JKhqTF{E|>JztLv7hfK0 z*IpDot5*dk#?#9DI+*IQLkHp*aXKkPD=Mqw)YFx#HVW^a^74H)j}ca|1~E9+kN*r- z)((W*dxlv39s{XujA2)?Vky(Rk5xDE-of+AWlPxaJVx4~wD#?o;9l8QRIxX%Uxs=< z*6wHZDEomSpGCa!*t&Hm8USnoV5@j3M#aLzr{~nmx;H?pCE5l@oj^C)Un_Ef!h&Otc-t&>ir#W zdOb{EH-d)#ILKyOWT=1)1-{*G9-s2BP| z#h4#rUbG}+g29!!3m+(CP0_-02BQ8!+(6 zu-Ze~!hX6ed+rE0Mfv+-zAb|b1EX0u0_}7PXehhbEVvbx{`xSUP?{51M?ZWLgMBcY zM-bBOrcGN>6IZZv>?=o8g4Oi{2ad;6Pd%Hf z?V{kj-+dm&bRp{IS0QBRK^`%S`p$_RyG|ewc!vB?CkIKV==<)?zxKLoF$A}Ov0xBw zl4J4cW1DgeIC0_xOuAO(pF$`w4;o$zj@e#wqMQ%EXV0EA0;m>&LIc}mK4sdlVSSup zHG1Tr+ao4p>yBshxVif1QH4|*kDNDuA+QD!z&)0Ytp5Ogp&w@2bLBlg*V7Z0EMFFT z_U}dz_7r6)^rt;C>!8Mt^uBua>bUvVx1e>fJ078q;|Om0=*tRrAAaOn;0~g_Fb8d+ z4jAy2@$@sB`E3H99EpdPQEF7RZ_ECo?Spyq7~kIh{@A`_2ftmEV_`Di=vZOL<52`B z+c<7;UJB!EJI9%2E0*Mnyc!SkbP5_3po#-2#<3|+UV#P`xYpYuEx&O}pZ4xIs?77e zkAh3*d(xC+bP-bXZ6Q?_m~Wf@GZbF)^8^A7MJgz{{BpL=2%A51Io+Mf5yWS%l?wRoYxGf`-8#F`JWzcXj5@~eQ{@k zs!YvwIU}FbAXR0k(ixOsxD;>%l>bJm90RBz!vtZBfs8RNd>k^O8Jm!wOnq)qsA-*h z23KjNPd@?~J;O?$m_m~w!sW`%w6*hH=LaeU3z;6qgAbb%Zq-y(&r_0IMJ)*~=+*jA zC<^08&$5aee}3rol8HObuPzN?joR_dXE5tmpfD%oW1MM;Rnw1o0re%+pyX}D2FkLS zT>Q?Q3k1Qonfcb54%x=}ftr@BFdD$8g?*pCW;>yCD@|*$dJ=VVnN}M%Pk>0eFDj6p z4=v3!H-+u%w^z}glP>ATcYpOaK|fs%FVaKxUZdQ2{Nt*-;l{(qW44^Ijxd3o-Nou$ zM@NjXf;Wa*Ff%n)R9di%@0Q23_6eAB<`xs4y-rzO{TYMN9%KdjKtI!d_BT6O9zs|r9h!}M>sfbZt1?>& z5DMf&7DlJXmBB!5+qx(AJ-<6H zLT$SZmG^Os=#8`TX}_HTqddkqrUs^SpAL?$o57^`*zu#R@U_P79ot~OXd6^j=k%~Y zA3V-RrGH*eCk(}L@Hrz_>@BZGw+8wSV}y|7yqJ9sVMJ{%E1nur8)v_>miDu(q+h*k zaqQc>2{jjQ8Ve)$*U@rNHoRsIu{aYlUdw?7&0yz>X*cmD9x zsMXJckwRER*~MoWZ%V&!NhE_b{{8x-ppaF~Loj}KUbHd(#>ajXybZ;t{>49wyYKx* z{NrEw)wt^FtKue3)8yNpMqEfJ88(y?-=!f)aeq0ky~z|vVN4&BFP}h(9~nQ z1nM_11w%ZKa<09`_FAy<;8@_Xk*SIgJdIY`mP7^~odGrdVaEF7Sgzl)^H7|EeuinQ zVfuq7HCX>5d{Yo+&r%G4!@pP^ckzvS0B`fIeevW|dt*U2tNx=W06mz348XI`zO2?S zSUAb*^|82m>GF`lhopJutb4Y@^s}n$ade(Zf0&i!6DNn`HP>Aet58{g8f}=z9(xQS zkXkd;1DJg<+Y1-Uu*LdlY3C1-v!L=;7_&j zw%EZc{VliN!k+sp;}Q&UKKtymXdG-p5V8-U2Mjsm;z?BCXU%Sp58U;>xCFzN9;bKo z=n1q79*f8Be;8(b1R3JI6ljRMw=Y{AD^{*W*fa>&6k!n~hM;PdH$ zWokh2iB6Q)s%VZe6g+QDUPclD>9`Z6JT^zfr+8No#ZJQFZagn}_qoK$*BX}Im8+wb z0l11lSPqx~$w86<#VnNYfpvb?rHX4|33L*nzl~E2$`FSEso9xV)+aM9Va*ea%)?7M z!|UhDi`&_Kr^2T{oe5!jjKA1-t1FY?M?h5;KLQfD?U9o;-fJACAO7{bc(;Cy_j6Pw zzX?rc`T+jW;2l=^6I_KO7`GZggj@2L# z(ka8@1O-SHJSRoP3D0q=v_)O~rlKV5WaxqGBwSb;5wbm6SwS*?+cd54TX6C@8=PjC z=le_!1wrD;NhTRKCfkmm`ZwZ;LC4w-IAZ+@@6ku%w70jn;M79k%wLx!tY3;(BdmJmHZ8(bz$QTe$ z586>MmGpz3b|SdtcSKq@x5A7#IV*YR7)G3Y%gGy&Bziowe<2-BC~UBAu~I$+Q#e9< z%cwg`w{#0RE^NVER`gr2lFjOUyEI9-{70T%kyJ*+k_ivx(ec9kDO46m%C^rN&FO@9 z`-EdcjtdT?$P(I6qxO3VR}V7=jl=Mcas=JPBrEyQpw&p@Pr~5Ey~wWOXI%k26J~rN zYQa0$vwIjz@}sHF&vpR>7Bktu{M@6D#WSdwFT}ukU;o7zVN0Y(-@WNAx8?rYFMs`^Y>i~XnSAHs3;6NR?F9-;L_AdhFR1K8 zZ=P@i zd<>b%gnov{4)(!lK}Q|n)A33Kx(aO@`)!bB^T(}Ffz(!Ly!abIM_T@?r@R}hcud7H zilbZ-S$?Dp)7MhbXP`Oz6kK1dp3NTU{fFbx-S=^<+-$})$_=ADlNJ3oY$j+^L6`Z^ zKk2g2AkZ3&J+v>)0#nka2PF;a=Xb@Q<;d?XX;Xkr!{*jpxcG6G|6%TB9BaltGo(j3 z9^?^gz#QWkOpDwCKF25A`_EbEXna_g)Zjo!K>+8zV?#mwW|x;}N#nQE@qN5(k?8E| zftkl(-e^Cn)Qmm$FJQG(h7rm(mlF}X=PZmqXlW*U`DgVkh%2tT9<}bVc;LYYDMM!* zVGsT4b(bULppOh;f1_s+4ER#CU?x!~XKU{8Gcc8h(tg0Ql^21>*%+uCWCeRWVT^kS z4KKU$I)rZ=Znt+IHEc;n{V*&2Cs9RTx_li%gMQ+{U(BRkQ0E^QLYPLM?U}nE_8&YM zd-ffsjGkgJo0aF)z#XH1pFmS&knIIM^vU`3AB1iv_s9H2D-kFxCA=SdnmwE%FfaSr z3{Dv6n!P9v9_eSrp1tzyulJj##?0IWOQRcx{lxJTj0@V&SjZ8Ahhfz3k2~(TJ#M(+ zX4<5aexp_V&Gg^4=$*F&vTBJ3*e0-a>7uylbvMO2wmu9G*&yBV94hkKqG)G}z#&e_ z_`)B53B%)a;!4!wd*&`=`$9kIRv?&wJU!zcgMAwCeCD|=jCnJ1m4Eg6jdA4qkVEeCwJ-G0nCr3lOiX=PR4D! zBJ3i0g{;DORstLQy_01+gRLlB|DD{}UxXu!LIV|mj5pP6hMm^8NJD}~evR_mS*JC2 z4c|tSu}yu#s-R9FRLeAtL6x^r8?KZnOPvgT#v@e!EP@Y|$MOlnkAtDLv|C(BlTPHa zp5l-gj)AhH`3E3{Ch6@LLMZq-M%3CZ8OSAZ=D>n;%+ZMs^Q_TQixxXKmXib3WO{LM4u(A=vv&%{Eqgs9mHmoQ%FZ_+ZQ}Kj@Ua= ziv)z0)*wI52XwzRrI#f zCz;GT-^vwB%Dj+OvPHdZ{Md8f!hT=-B`TqlE;rkMfaiYSQDDg+=G4tRtQLRrbTZtz z_-%Fgq>v|NMp&n{Z@Wb+_o%qUzehivK7o`mQ`4-m^biSa~{dcysKh+)GiTJ%IpV^3-uA z|8tnHaZH?Nl-W-HJPF96uupsB+SgGp(&Q5T~Hh{ikX(fDuv$nf1 zHs*E))%H~t_IS8SCdy^}q3%qCMT*-lY|FM}CSl}QrG>-io8x?OEaq{n-YAUS2>nd; z-=!Sa_r-gjh`;*n$KwsRT^*NRY@eik8Ebd2(x}DrURKlwVaU|mo?vCTOv?Cfv67w! zok41zx&WRNpWpyP39)_q4)zA0h)@5~AI1CM^MmnoKmRN7_IJELe)C`d8&(xj5k?3y zgt0H%T)}K=?wFSMGFI!aumY8D)cA*3X&gqyzY8^K+cD|Y_`DSLUTKjxFXERl1x<#R zA4RVTBmMHF1Z6-8O(GzjV6r~hlX$QCj0sx6wJX{}9)$Pp?OhmidA2WzyCK>c^Idoh zQMMXxl^?0fH;H!vW{A-JX=P)^BF?SWPdTq?*rapD*j??=)YTsx}rlk@=?j~r+0AFix+bILT3I?X5%6jY{_^NT#d17e;&s%PZa3+oZu9b(ISp9OY~LC;Tt6??t-AvHZ^w`wM(s}Q&n*da zp*tDkAvBMk-L!-K_-qTpuYKljve#z=J(aK30>n^!G z)@|7p{imKt4WL!nH&CFM7X3MaW8|qV*zI7vUbF~!y$EP9ug`XyVn`FMBLoKH;vGEZ zYCPYI>?0u9VaIQi6As1t;{9Un9x1hw`DX zQ`b_yx?K9_z+~nCcOOkMGQ2vd%NW!XLGw1R`n{@}5b)2Ce9l8^p>)4dyS^(3z0G5rDHfByI~ z$1@sydddD`-YHgn9HY{7Ki=6^4Ct!U<&g$(KalT<}%Rv z!8eY~ZNep$QZ{>0kIRl#)NG3y^|C@sU5qLY%mAqL$A&^Q`i({BrV>^$?EbsU}4D`C&1A zP8_QeXP=?NzJai-IhFUdvM!@Kw1K{D=YZl9=|} zU}g2=mrqu8uR(sj!V=_OwpVew6#Z1b&F`+&mCZdCJGVQsMf%X7AK+>t2 zb#_6+Vzj|rFyGFTz$}Mla|p;XX3?n!_Y^cbhcXgCx?$`)$P39)nl)4S&?c`6t|sIJ zcwvMk+^c;7)n->A`8m-&bm(C0K#jN`%iXRb_Ar@7&oj%_$BKM6iy5wB&BThnWBuYq zsO7^%&tO$@kh$A9>c90l+0N*!Q{CsZF0DH1FwDb&{rgjkMRnn?e&tKCfE7LsfSu&n zDz{vChIVdUMD^9N$uZ5@ z{Pu7C7I^sU&<=a256KYqvL}BldxVd|AYgTWdE2P2z#8P3r}$BT1WiMFZ_D^^56Ps+<5aX@%q=@7Qgx1|1lP!wb3SFI`(MP zP5PxSwx0}uW79aRdE%`T!*rb;y>alsffR1EU=UCzO}M|dxI!cNmT!o721Xg<>@{_` z*w;;kPvK2}(-^n>^vSqQ_e@_3n(;=7U&m6&A&dr0f_yf5#xYy!mt(LV_**)|6=;wv z47ghmSY`Je^yD`R+@wGcniZbLTh*{}EHLgM{*!1m*!Qh-3g|=-`>WLkNa1gVUyV1K zPm4T-bPS$zO9b55Obpw#d7N4HpDcWdYdiT$k<*xA3Xh;O7`sW@$TXb@yCzvlU%X-k zTSgEJz>JO2LH8d)0Cs#kd$?K2N0q*#YZw?Xb1=HDrgszf7=p@szWq=vU$TQPe6}-oQN?4 z3Bxc9Xtd9ct{wyfSl*umzcc7Vy$e?(gkd)bd&oQE*pw-iHj9UNoX-3t@kA->xYU~sYkG&)oDAdL~iUFbkkSS zp0Hgg$Kq9sW7CfP2!$Sq8(w>3%wN7X<}KNlrD?^cDlNtgP0Zb7A=p9F2UBp(MK37Fi46$fjJn(8y{e$ z9Rr;+F}633mOv->dH63|IS}pLbJ3WX6Fu`aga;k9b1DVfsfIY>bCR(BW2d5h-lAl_ zA&g|qI}k!>(<5mUTqivja$#t6Tn6X)Ugn}14-aY8pS+80mVbFSx_{XvfLrEmnJ(c0 z$8T1Zh6fVV{RrB0+-{^6ioXlv&Y!W*ve>EUcvgUc&kuneTEDEA1tu(+J3F8M{H$lg zH9t2zU*v%_31?cg8WdTahBl+=rz_1-p3(!KB7GFuXK^%$lAmN|$iRlqdT^O)+LEr$ z{SS0kuXb-Dch)oByJ_vHoLHMa#Qaj*LP1xs?Tq^p|kZF7?@ zWGYp?RRHLj%sq3Ml0dhq6=xHO&SqB{Z_206r>2)_;b&{*DY~k_5UG=Wv~5h-SzwLT zE0@J39K|*Vrg7x(-q?F`5Bs+JIT~tx9`Us8`K>YB@5)yx9@Sy|q>j*vT8h$`TjVW! zdkQldPkGm?(6!IJRq5^S(wQ_Qqcq9p-Z2<^O2j0b6&`@MA#jkXbrRiTTvW)_9!Q?v zx|5G9aYA;XzmL7SeF!MJ=dm)!eewJianV(*f~8gN=VA=JPr%T&V*&80E3b&R+gi@>`(_{wh`mXEA9X=pV>-UcPKu zsv2wf>Ihc$H7e)NW8vzpKs7$3m*x@4=Q(H_j0_F1A`4RmlDjBx3yfSVWj?fjZ~W7L z`cLBeYp;M=1b?g;_w@7tmy|Mlte6dBMP2QOnM~+M$Jjza`Wa08ix5dc5;%bNVC`6y zoR1)2F!t`;4bz73VExkg*^m8`c=@=v5MePg1GV#Bgku=dqg)z|JHblyqfc)IH@l!U zu-7>kA(R3=;0&-QpHnpElBNaW@L`U2lrBz`%w%;C@47I z&)5gP6c)^y$My_pWsIcD_*|8%DOU5S~){ks9a-C~+7a?X+JLB*? zy`k&iyjO8f^ZOonDX6eRARNib0-p(R(~J)Z-e19~oumnO;vk!#gr5y1l9cdjciM9k zsAm5bOm3jB0tZJkaynZHYN-T|U z+tdtaNk7G4+H5)4+4rk>B@6mJ`J^BIr5^~(kFDcHrlPoYV;QIPwdOk1vC=P#UVKU_ zJa8#gsKKO9eZe#T4J2KOUI)IUd$Wc?7PSGd)Xn-?H^&K|%`o%fvGz}4Ct-${I8#~Y zv3H3u)9YXG;KaX9C+xCvUp_X80m4gs%fV_rlM`XfDC8h7Ea3WApeFEqel;%UVtJ$` zCn1T1%-TzZ`>K9<+raqT5 zycSB;am2g$f96@NhO<(uigCiQaQVHfW11FE%b(?)^8fyMs@tHnoNcOel62w(2J;w0 zT)`b3!xA%iN+zFo_jqcR`}nbwFji&tUR<8Lr7Db;2CZIR+0C}{9Qjt%X0@n3e;x*< zFp|}``RSN(a6c3AlhM{Q7ISA_5xq>BAK@(dk)20k4y$MwYOnew>3P-`grgR-0|}ZH zvBFSfXQ+!;)vE|QOAU#d@j+Cy!IY}h-@*#vOlb|Z^$FDDSqRI%oW}TImYrWYFUrLf z#!3M&|7RaNLK4jNcf(Y!SihDt-dDxCWh+>`Z72o%;}bJC$w^I6@W#R@N;3v75@|Q*yg=4L45|Wls~?^KjvSI zCGm~RbG7~i=T^@EY(SI0MLpj$z;|vN!5|oF%yXBM7h4A4cszgJ)xkZM^|^iMS|^%l zC>S-$Lg69~!kny{jTS~*94C(nwkyEhMa+wM5XvwS+!H`0Q-np!vq6v{!xS7-zNCI!^&9e+m0;$4yp-i$kHM~-+WbE}# z5QbIZygT|*p`<;VKOKy-P8L3m;=vfX<<;?E6uOW}QY*vnX|28K93;y^xfH(SRtozQ z>hlw+VviRE$m1aq;HVujk_<4(SgpVF7ATO!DDZOSpGK#jcci@p zzqb>NNqY{mx4w^q0+oL35wxBf&pqmsoE~AX zJaP9gH`!i7~q?nF$er$%^yRYBW$~vNx#xo$LOdG|9EO#3?byuaONNat6{VZI$^R0 z*}kArIqe+mIeY{d%qytN;9$Y`#1LC?V5~tULPKE<$1(c6#5Mv9IC5|>5q%^5z+!6~ zLO1uI5A+|y2q)Viz@5U&maf@x5*q`3`}q#c!l);91>(_XVlm^%g82*LB>AzCBJB+L zT^>8sA4}L)Kt|c#qYQ4lDBqAy{II+rppkNjqm&&$#x(OjE^aq&YMC3;Niu=Y!WQLut~p<|F*t<>UEeRs*^a zcW_+wnA4%v__PK1NaiXGWj<}7GG#S6&;oNS1F(}YSJq_qZ3{mRy0T)-Lq*etu_=td z&klGwdB_1GlVo05I?HGrTSyO(Stui4O5~<%#`C?(t10M=s@Aks@-8tGB~>Cp)NwNJ z(}2Cei|GhXSUyxv{8@HCHo_H0wTfZA|Ijd3C>=v`i$e7gNE}pYWP02d;rJqMr-U0$ zgbQ5rmO;{$50n1BG0yVwbwcebS+15;YL2#7ndlT4&2($Z3+|{-!BhE&317Svx>0Ds z2QUj!;&~N+1$RWILbhE)C{QX`kWajZ#Z{@M=xD^KV~ptQjBU z*f^~UGbwFr)c_$XpiFq}6SG*I&3)aDE8y7pQ?9h1-e9e%ZGH?_}4p zKn7dtP(9zdTwU}WXYGsp8E#sFb8>F!jAxwLOmaKP&lTPr2PA7I!!0s|_{*P+F(D_i zgFs;>n4mJvhizeRF@lnr9=*mY>Gjv%5VJ5!wfV_sV+X>i#TcaXw|doznA6MT7j252 zCos&#-utDf%c3lwD!G=2i5!J8b8qxpvU3lqD%Z&@kw4Qrgdq!Z54^`{IW~Drm~~W; z@0ezrTi3F^OEqZ6LBAiswcV;;)-^GLL9&y_;-`P=#}IV5-B^_=_0(ma#W_0ow{LS%=|07aufq$hT=eo0m*psr z`D~l{^IPOR!IUyd;#t8?Zu28tfrovei0#Bu=>@6g&vV-4at%4P9cDCJA^dm5vXc(NKcY%_ALoE+Z%?={=v9Ci4n>%R;9;SIiJCJI?NX^h__@zmDA=zh#*`;4bi9L2VPmhamU z)=k1}Y5>!3>gWXX2Xysi>OFd~6XBJD5c_N2sfpY|(~96w@y0Q>s?0#WU<~b_q2W_# zAh0qIGw=TIG5XOES_>WzH;kZU6q^+arVboDj3&)2gs-#976AwbGOq;+azzBU&!>Vp|nt?_7(Lq+|hp=nW zqXqk!vFjjv{Er|!B;6pwg>hE(6(}CyjQYWeW3++&3{3>K7mRY=J!|y90)G>nY{D2Y z6B{6H7_w_c;!=+{j%QSpazby=N&cmviT(?0>CtgL1xDadfn=`o)BZW{asab2iJLT+ zb*{o1&q5`fUvWhKb8xSSu}{QMxEvsp@<9N9#bSk(bd?V(Oy*unb#H>mbC@b0iA2at zs9++5bix!nrL&4j|MQZF6_jzy08jvnbCF)fOwR^d3G~lKv!m9H;~*;_&uOQE}-XZic+z2CHsr@myXZsrfOsHlRk;( z-m>yu=(tR<>Osm0P!4O^j@d}0Y4k<&A#t`TFclUQrVODTeXBM5hmpv~zE&ERyY0-o zUY5n8`AZM)=XOai8B7A}%FmDLX|DOzJepjos}ZU)@KlO1mB=SyCN);xWuI>Wlqk+i zRcvC{V|~IUtQLS|evA>~)r=r2=;b6xmqGy|R^UnJ#Kd!*v|)rK!`S>9Hxoi$6MpaYBoYITmu~U|5U& z^SpO3)9$j*!4Pz^$~%iyyEzDW`V40!JuQQm!X;Dhx$nf5w1HSLaD-b=qZ!{Z!eLNy zDL>%Yhb6eGjx*`AY6H}&{q}EF@J*{RJ!YxQTL5S}Chsjwj?*v`3~LLFfk)e&VlV#g z&0FI$|M|0VeE-4dfzjBwel6jnas23^*!9$7v1;wwSi5>97Os!SQC8o3w2Y5B{fH}? zj1!hemrMr?kbCP}m?-P(nBw?io4P8$m{n~xg$7_K1~9gz0IZ9nqTp6mxrK0dp{RZ+{x2TvxCS0E>sH>Ykup*IuzUe&Dv(Cqv^}vgLQAJ&q;0 zKFT^Ya2&&b80T9umoagitphMobJ|%YoF7Y;Ek|%LfDmL}tXa1XmHhtr>ev1Z!N}rR zgLVGzKJpj_6*=)?s0Rz&hmu)&9xMC7F@0+mqq)GJj1Xd7j28~1;lpvplGK2s6dKzr zC9*#_W|enwBTlBAVdBf^&;!4GtlB6mm6vMVOIjjx3(~`E1Uxz@;v{^Frz;TS!r68GlQxe8WG0u`7-!{uE1Ln6$reDU^tz#gaHizlP zr-iZB^lDwGvEqvEJQ{yCS|XD$^ZghlltG^X9k+oy8DW{XZnkJhlY*GcSb3D2BgQOF zjIbXK54mE`$~Y?d+V4;uz6dKYT*?0XevH<+pMPSOyojsee$TP$4{fRe;C3dzSwqm? zEQF6{Hbfkay}1hCPXBg%8be^`>h*|=mHf5BJP)F+q7X`WmcJVzUl--lzK1wEj)A&a z&~Ybl6?Az-TaMw3k-4pa`NRkUI87Ny2mSQ-PMLae*fEPO2lU_ZNepx%SOD?h)qD_G z3?8TKh`K1FHZU+eK%8#qf-w_Aok~#5N8yAv00uBdsDQ&Z=$Hczu#iv1kjY|{j}fAe zvU%iRCqj?xAlY2jP%X0F3|HUV(h2qT?Qg)NW@WoDmqT5N@hW%fr|XFLoEI! zYP{+1dp=J=tzx9d)H6`%U?Rw$DaCt%Fa=knHCzL(X$UF*+#zKn5^mXZl9~5}N&ta2 zM8?k&CP*j58o@|uEQ3-q_QaDoaxx-JT&ZjIA{a8O-b#c{obrq0wOTTf_SzKwe(hjr^NT}N+R{=;>P$%k0Jg1a zm+%_2au&qmmA;m-q7Bn#k?rFZjg>K?hFb1*sCkrfmyENG>%uiBu^h&2D&J|ryp%8^ zltSs#C{|(WUEy`#p98;>VCdR%^OL6Y!@}JUp>ak~XLF_9kCyl^?NV|zU5;1y*Vdh7 z_!FKvTh?leiUi_9Q3abr3CnPa9eaZ3B?smss|cf6?HN>Ejg($;vr>}rYc0?LVC zt$E?xrQCd9Nn}f zC+*!FCAaMx|07m$OxLPqt2vqAI453@p&s57{rmUCm%e*nEM2iWPQm=nn}fPJlk^ej zdYp>XLPpzUnAN&Yt$Z_i*I7)*H_M-WlxJ7gT&Ztcyokv>N87Q2Ze6tCzjfQT*pH#T zS*$WTxptNC6im&MB}+JqTD5u^bXN6XLb|$V!1TaWGr52K@kfY%T{11B!_p2biKqHw zBP;MD!+lul-UG99G6e-PAC~3V;S=%XW1MllVnrJ2k~z8ep1Wh<_?69uAemI?(hFhKp{U{; zzoaR`>zvfn-ZF`Uu?KC8OXqe#S4ZOBE!$%;!kbk~=d)#EFt(s_eFewVO|nYe&4~ru z_v}fb*T&^bY1_friLmO(frGJbCFj5QE{egE?43uT^z@#cXo}OxRS{n>J6^kXN!ptD z_II9**mjI<7chi#XU3K57RG(|;RjQ{bosovV$B9$ZIA{>^;xzjjNWjZKS7zef&pa^Va>b zaoxOFfY3_=dm41yy!&9Bcw%?N<@00R!roYpDtZS(uWh^b#kOzl0OpKX@>*V|a)HqqWWay)Lm=F;q|Zc7-YPkFMA+BojHAE%!&Vlf_pKlZE-BMebjXdI)Lon6@2 zK>I*JNDn7woI>;E*&RnIBU^(Ab1}g!3if?%ZOlg?*N%__FY1Q90}TJQv~%KtPZ^*XHF+00RnRAt~*}hWs2cSu(Wxhs4{iSdI%RCP+dT&|yEm|Bo7t3(x zHv-_NGoM%4y&}fm%GRz?@v6`z$ibWydj>Dx9c(4IJQ|3`$w8~GWDTh4-W-(A;<52i z@RLX-jrsdmB3Q2G)a9*|*L(@91`%WBAd?s`Wy+6t7T9#c5^&Xocc@t??|M%CSR zs%fllXX~4^mhE+B?ekj$sQR1pYUA)6#W=HIe^EZ*vQY5p1xUP{4LKPmpZP z&9Bl`(pJ{5Iiwk4Rfe;`YL1otA2<%=W}2(=8G-i-zBny7D==%knbv0~ZZf^Ow-7(a zn%WsI^I>{n`%zYX4DYOC3K&UKgab1DW!&xKEafFw#9gppVG3GQRn=(>PGB;o&G{Hs z+Rdl)b6HCZ?1MkbT5xWmi@%1gT*0j0n{kqH4I#YNc(SZDqknq1*ezhZWxL~%`0=%V z$iOo%8Jqyl46A*_sd#rPQ1H#P0bxwDlO~0AT3H%ISOP5ftKstdXz~6Ra8p$*b+vV5 zq}aHexRZv5M-Jy|)nX=QCr=*F6$D@c61UdvMcVS^SHJW>C!4O04Gps@ z&E#2&@slusovQ1izKIBjF^4`!2CWFB>eGIh%Q;u1+=WS(L~<3&JBW}u*Lu2iD;-+= zx)1Y~#nnGa%gT!~ycHUxy$xXt%Zapj;n{hLXD++%7EYLzJ>CJJF})rp&K*2=<|-Bj zzL@lnbDn(KPr)b`9X^gS4)n9iJr^c-4o7AUAH!Y%?bF37UMqrtb|&%NXcV+9;FyWZ0-vVk669y|nAWdMM+RhQL%|cjePM6l>_Mv3K`&jE^mdb?eu~6|a2_ z#>5WB!9xeY2SNeu3P2YkXb|i7UF=o%JMqQ4zZlPN+JyQq##_;t=;7`v=ic4B!09;q z>3f*O4>GAQtANAoQFffzyLV^o-MD*YoW_>JKygZ(L>WNs0fiG2z z_wC&sOXkmx+i$-;?tJ?l@x)U*(G1_L!rtNX}pM5j_zi&Pq|KJlJjpfT0#ee$GpNmoUyYD-&JKlQJ z)i8P;@c?_WWxhZ8i$4Y4+v9Ve`7iPH2e!mgSNz$t{*Qk4N1zE;>oK;5(Z~OB_m@%i zJ`(@r@Bc7Dn^jrQ2k*NtzIy+|@%Mh|y=ZYP<8*^#@!!Ar5PRp@N`y9y8p*Q|*tm*3 zfPm=l{*Cv?)mL8%dpio_y(RAc>eu4&-8}sXwp-)JKK#~r?6Jqu-& z9*mtB@_YZAZj7J#@ehF08F|+G^ILYt-QRsYUbAWuS_m-yJ2u6eUw?gk{KId~Gvq)2 zrTgQewcYfU*~z32u*GDUK6B~D6>;YsH$?Bx%tljSFn;@wz8J5)^rE=!^;gGJ&pd|~ z)ls$*uty(UE?tDxe{kz*0%P>^30D85U2PW3!M?*lz?)*zw!Lvb{ov}A3ou_X6027%g&x}C5AMD%ZrHFK?HILd7-Jpa7<&{j z9zJ>$yDJm1kUsV3)@`v5&6&H^s$GJ_7#E%v^!eSILh(33^Vlqvhd`0JZT(~mY$`_GFJQSIGj|Tw5`y^ z$gOCJ=&~O$PNhM{ivGooeOXP1w6kD!>@KCtWV!@WJ-r&YSH##i7o;w$gMT6?OJ6<& zGWJ$KCuUSmLIeZJgV*VrVb#yVX%0`c7T}5aj0c=XEFS&v(Ni-h{Q*$Js0X2v&LWT? zF>Rb`5VBnUoPg8`D`@r20jD&it8g5xfSOHVQVN{XSVAnW`Kg96{oYiI=|SIf@8TmT zICLoMoy)O(}POe;{NV3^kmMHf!3(agX+o)dGI1l+zV1ie{^2Cg zk9bkfqwON3@|F720zQk5Gp9B*uv)R4g2@Pt!MtXu`{A|EGO^XAQC zg34ruIBEhoY4usWo6h$$t5*BG2u>OZIQK){ck4`i_hf6QdWAzPa4r`wC40$)%cw5 z|H|KO7gu{{Qm#3wjG{Bzj^C`=ShGIjx!$h0LSK|qG`G?LrGacunBSxgvaeU)Z3*{m zdUtU?A#xBs`p1j^XYaR0k|j8UOIb^LJjk=Z1w zz#fk!6Uxrp2rP5UI6HN1Lmjz=3Fj=%>UOny81?fuEQ=SMGiT#?DQZSM+6p!P2ECgv z-g>qo`<@#8W~#5??o^IRPfoudDDwvY8NMr8*jW3f#X6L zH_phO&6)Es72?x&SD-V9U|_P3g_aZEn=UB5oR|ZE> z_n!%Vv@HXuq}`RP)}`P{b$rL}xs0)=*h8(bbQvqE9&>kyBkqnLIfQ!u(bOvFAL@@s zH*KS>U~m`p##+)WTrh{Tz}efZdN!@o2?HvF;m87Nsk@~sKc9=MDMkM#`Y_y|3Aq=# zsr>Y^&O%EsF9n*{GG{W)lwZ;-9(DVd5F?mD^{Xda)w?UYrjvHfpv?J8&IwN-s%(?o zIYI8JmOr2`NP{fXl9n4Q)eaTg4;_tLZn`S&c=Kh^4h{EV2=Q%ixh5{X^5R%?(eilf z8($Nbt(p@nS^_$8w_p%a5dX+=n}SDeBiG4#roB)7^RzxTRU!uH^O{x*|H_xa>wmy zxXsb;w%cA8pa0BfiN7S?_V(Mb>##rGc*{fa<~O}9RxEFaVSRgC`RV@}fAHzM!AnQ{ z&7b=5xa5*v)Xxz$`??|Nt4bI;e~?RVZ88!lQPM&r=o+v88Z@P+vB`)-SyUw>-~ z@IUpbe@S0xkGnp6C%C?oqglTk_k8PN=y(W$!5H;pn*kO2$cNq+S6{Q1efVgTyW${P<@eer(=0v>XUGIrM`IEcjGkNjFP?e?Dc+?lKU$A0>w2uhYC`0AlQMttX+-;PiH_V2{U{@O?44R3rC zg4EV{&->pMpZvc*6(_&U$2X4I~KJ>x&qA7%e#i^6==pzrs3dVrN z2-5!3AN^5$;cNHC&wTVlaou&-K|89x&xoGhxtv^cApYz17+=0e1~a}gw$%NjvGNa1Cp<2O@s@2PsW%s!hhh12`F# zODP`pHR21n68>VbUI4&ff*^6hSPm|@Bw~0LS2#Ze=UaQz*D&%9?E2k2s;nA!{VtRf zc5_~5!Zoxm!I`12o)7ufNS>C7LrJYNY*3btOQUb{oPKr1e5s#}ZyVOG3M-RF($90Hj*1mr6g;WA zr6HQ~v2biJ<4eXd^D2KOyCqKX6W?M-$hKF#I$W#nXBe=}Q)5~>kLWRc!Q6SM+_`_A z2`ppQ025CqUWVnzsk%?EJl^S*z%JCK2AVWusl_+ zvQm!%sURtz&weTGT;QEOMgft{c&-SQf1&$=!)&@zxNN5vNt(g7<*Va_>+hx1;?*fZ zGt`2Xx-687M<>9rMj6c&+*24J^Q`qr1c072aIytPNhX=q4(V3j^6ZUU!%a}TIefUF(1W1)m)Bhn!tMWgv>4T1M61t=sepq3zKdyb!^Kc=Va=EM{HO&;==@p z152KDB%Sxd1XWe2#%jNY3Ij~*bsWK0HZ8=j4;>^Yu=E%(}u<3#fzaG3gs#oI5+|Wrq-m^!riiQQh=8;JPhFzut02t8?Y&)0UGX@`@WjT-g%1SbTb((OKB zX>t}q2!`?$TsVfQLBRkV-L@BFaPBSU+xIN0{r~&l`MLPWU;SwO^3Q)Pw(Z=3dNPYZ z#2v!0*_JK4ZHQajICst8`U5Kz_o@xTBx+R=K2?##`~sbcNOg zRAN_gvc5#)RXEmOcN&By_$B&OsP7d8PD=;Yp~+-;6iig#xBS-NZ#l9pxR*Wk)madN5ZhdVGo;VPPyT{_j z>o&&G_r5j$ZO*Y;=| z8;U;8fPd_f@5Yr^UKtmyS{CEWm&DOS$I;06LXJnTL8D}WXRXtf+`m5yI=b}Yb@A@E z-yV10{Z-l%+w9tcpz)-YN$dd(PISey&pylwc28{FxG^r>uoim^L-D1reH}XQhKarg zA;QfWE;U}tk&5$X-4+9VM`PRO;kf*w)$#uKy#reT-SIoW|GAh+y&X26c!DB-#d7UkywI1}o9bQ9c6s#ozsfpNglSdNQ7Q`mtECVm(5D)o3)R z?!PNe9O^?mhH(XBdGlH2X6t!8{p6Ez$;B7No8Ndnr(E>8J0Whk`XbUCitDaihW5<| zP}}d1XP?`~*rDwagk;&zk&GY&>0`UZ#cQvLpZNG+kI#Sp^Jr3V#yov#;XKZ$pVyg; zwp#<=edp`r^2^tzroz_eACHx6ZMf;RYvb4c;r|(*`d9xi{ofu;KVSfC=Un>N-E>XN z7*9Zt=QUv*Kss zv!DH9eDQyNGgdC+ctDR?q+h#?pi6qqr*iS#FH~;#CYKVcicoa}=Ozq8$s<-?B(Ti> zIR+FVf%IMXSqt3gZzf9OuTp0wTuO(iGP^Lh^J47lNuot@g6SwkJ^857JV=Hd@N+O~ zRL*c~!!Hq1!V@b3sa*AqOK(wNiV78t=k%YB5Z+ZcDvswe8ddMpZWZ7%iC}QC{0u4{ z$1+Q|pE{&D#Z-)!_T=DwdY)%X zS5?;A3%SJISxQqSf1#x34m-V;5`WT-GYHx%>4V4SI+RXPAT~drI}bv#t*U!d#JbA$ zy(#F$AM1KIRiTupFd$A|tWT*EMUaNhaA)%)QVsiz_^+;qT}G0f%Dz<2YoXN=*1&t+ zM$OeIk%?G5jcc10*s^IdYSN{7>F=bBFHSlO;6n|hdTfTD@tVT(ed^Lke%3UVr;*MG z*P{fKe(hVCuGH75TwdZ+RZQzwOK_dk)RP&_=A^ZUP&k2ILWjOPKeWqOD9Ua zSXzaRx=ce@jq4h(iSsJH@SHTuMD<~e%=4s2nZ!HUbp>|O0Cd6|xc8DD6= z7NAw0c@tOV-8^*J=EbY&nx*0WZ1tFmW?J!UyxbPS)07ans?$_-KZWUv<^L*xtg51) zrMyjvU(O@>BuuMujw+Pci{J_XW$s-;^{r5i*H{JA_JO*wr$JEJCtJS2okTRwn%F`V-gHTX)|dC7%-q}GdQO9Qy=3>8^U!u zGt_rH>$na^aUs_Azwx#I8P{HSdA#SXZ_2h*tR=Sg9vR2F_`is6-v3mrS&Q28-oum~ zL52H^B@lk%LYU%E{5tmJ_(NXiXB-=@ZkudG-we+b1&$DktKLnAE7uZI=TZ7BApl4i z#`OVLe}}Ss#j9KimmznXtuCWe2IDoy^_ymBJxA)Kt}{D|hD2&tfYS*yP_$t+F4Ebr zT^N51*D*fa^!l6QAV*<->%MzqJxuc)G|?1pbrSW)8*hl~zx_aLd;W>IY{RPPMkSmB zHDk+jo1*Q`+hEXpVbEC#W-s^(_nRX`=!H)2c;oHlIS~)t`*8FlfZDx#PdxkNGr7P2 z-~Z0<$KU+%zaDpe@Gju-{iO8$#}3l}BG#>26W_S+;aChU&FY3$>2rfa2(YjSf7R7j zvJZVEzKa_F6<1!x7LJp#fA_xFvv*(o!S8)K)~{KWjQxAw^Bz>zSHiR&j?aGXv+>S% zzJ)wi17j3zrbRH;XfvHU3S+x4)~#8ds{DKR?8VUK^4NdiL~P!)DIR?2;rK&V);C_X z0qv)?asBnz#rpNDW9j0B>}h{93jCBA$=%W8v*-uIsWN~3#Bu0&1Z|Rj#wLVS47ID5 zEa2piHnt)4r!YbGw|91X?AnD!0?jrT75?k4zb5t{#2Wu$(nCEb+2+^E;=xT9FNt6O z*Z(dqyJ8&zgtc+qwO7LEAA$K-lczPldC!CK{BzIJSBGNx(xvf3@BJav`WMFU{_gL` z|4-g~Ki2rA>`I^i z)F;xp6Nl2n58j(b23CdDPA9%BcCPPAKk@_Ln;Iq<6R4*a2bV65rYAo0skCF~E$Qw% z?@5op_Z^%ba4{V{ayT`RpaF$O13nTQL*%i%y)ln@VKVO=6*zeeU<`+)9e-!Ba*|IN zHeg}WP%p>T==a{;s1@^jI z$0yILl+tue&BZjYbbRn=he!)EIUM;MRJ7Rn>J|e7ae1VuBr<22LAVkwk`$rkgo@Ys zuOd^L4!oLLOI7 z0(B5~QZmS1J9*uY+3uTe3W4Jcrgu7f39qjV7&S%lT>Dm2lEDi^)ugIElD14<`@yUx znEPbOWsWi~1BuX*W>n5}fpyT5y4mRb&sCHtsTdHm z;G63d$w^~6C!fiZnTu00F@N{3Nja9;u_; z2r+x4$w-)Pfy**;N)p5i<3))(u;N2O-JJyU>}pUrmlQ|TovJ8(6cBfmsx-cdgU?{Ec%B1)em0oCpje_P6uvj$245QCDXw#h4@0dh%bvJZ_U7FSw@qof=QGg zul~d+7)WO#YVumQTs}1|@>r*=$o0D}kLC9ONL)_ludsw!7FBt0#z3y?e@UbG z?qnpuS>hB(P=O-2Qg9WwN>E*ztHLo7=Mpl_s=380E~2y2OQn-0-MDXKa@EN`?`fPh zjiZ1XVWQX=f@KymLl^_m+@GkAbpo8YSIevV(W26RYg>jmuMG zY2fUsG>f|>O|$%Q^I&qs14iZ#?~gzvcG`P zzB+yCGoMSJ`TXZlG^F&Mk3W`fyY)6apXY4=PM&py)yN9_2LVB83gM# zwn=D;??%&Jj%j1^O?$<71npE}=(N!}oTk+B%{0o5gsHAA zM5)1VDlew-ysgP`1JADJ`@PciSaNA`(u0YwTMl&AB|pkf3Z{c>iO9z`;zgXT4gdU~ z|4Mqt+uxHqyH_CydC~ywIlCg=dfV;kz~KwP??^kgx2L1Wk8^b2d1%G)VXOqps}7$k zA*@mM{%)PLjDQ(X@Z_&HwY4Io%I!!!B8XfD8x!&I6z~2-lSh0tuVDd)ph{nf=$xhs z$8rp6C0!o@kA9*01J9!}e*Wdc>^mqR5-^1s@ zI~ZezaC-Pvls@(m6kW922#ybrB6#oKy&LP0jp-oA9&X*bCEaz`y}-g*B&dyZOk5Y^ zfIc`zCN8o^emIU)oPjU=zRn;hbI@A!*U@2=6CADa+A9a(%?{w~!7oHdYTdpiJ$TPu ztZ08Mef)D@P2chGBdHm|-hO`neRroPpZo%Rb}6>V^j|muzvz`7uk-v{&1(G+E9u|( z#y7bSrL}7}Agm9hbsN@!$ANn2OcQg0^Xl4xPLJ_(Rf%&5!{oVA}**fspyWR<$FG1Jg^qxns ztQg(G%K7i$P;w>hc{)AHDHl6;Y)v=av@1RL!prGz{@Smm?HjhG`}W+05)bo!WUw)} z3E>bEe}OTMu4N0)+ur^*`o{&F;MtFD_t|vsy?bcG7=VJG+$MCExwuNryAbR<+Gf%! zwj}ho<8%+Do6bMoGGj}rcx_-X^-He8lN0o?5Mdh#4Xy>G%ET7=5=M<@#(`KIL7Aa7 zWSr!nRSg|qWv*LF96uV7A5|3UU!+ClW@G+qU^|!FP4f6lFnOYbQ~r&(9Ko;YlJWc~ z*-_)Sa4JB{(`O+Z755)i;m_4P>f=v56?uG}=gKfk=p=B=ATzh(DpEvvMDt^86p-)b zW0}Q!&K3_2$g#2yZXTuKUxrkcVy(=e*G067Fp{1n{Ya>hsSI|Mo2ekcGOzjOzseNz z#YUW?vY_T95Mpf=jV}lAGHKA4i235mG;{A2lp}(=%q@8C`&LsXZ!EX2Y+e}5%Ao2~fdqNvt^8Z0l99>`MY8f% z;rlY6xQ9lbJXyHNJx64MCry(JsoV=LAUO9kql2Hx;P{b;?F_tvN)hLK)PqbJZ2fOe zpTibF#fxpA&?pZ@8p30RO#BIuM&2_mGq$2p zWDk_YrNk_N#9K}iZA^UNYa|JsYzp1gdGq-Z6u#m1OFv3}RI)z+#xN!)(tg>O$ORqi zv8vB6Ql_g9jX=XKu@dKZK_S_8$hbIE@F5U6SD{Wq8=rUz2|Ho#Y=r|A_D@W58Xrr@;$NwM z4IQo#`~ulC1)`WrS!F$QoEbBZBYg6#_u^s9PhF*5%PMX^Ud(%XRTi5pm|0(2oMAih3 z*`_##jRk8~*06x#o8U^3tA??AyWj`InN1+rTSo5tQ7K-7BGAe2g>@|P57I@v;qtcA z#5^YIMPC8NzTh`zh1NIF@W4|~r1Ktahe@ks)0ve=P_?#jOjQfBVuf?cnL((ZL1?%C zw_xwxz-qJ-OB4HeTN|;KpsY)*=%HfaJ8frkFTRsowp1ZNjJ&iz;c6^RVFIrZ<7r2E zYfr{dLAZf)!JSxZ4HU=RvAx2&jp7yCRd?&!-q{^1)0;P7`b;^V@2&8#e&bf~Z;v?X zFo|Mv0_T5@2cD&^RntW#^^*wYjtwf&?Roy`kj^v7LpUUJ4`$G@?E^SkFLmHEfn*^V zX*M16P};{c=|fl+3d#=jDy68X=<%tAN+O3<%BrBw5!8Ax6 z^;fX+=*AN6F-w~+j%o9(U(&vJU#|}Ufh2y9Y1kA-E{M=bnx(Ljsa^;8*l`7 zhNJS_y3h`9g~bE)QIOYX2+L1Jgn=c` zn}|R2M&f+8?k-#yo}+B%Y7*xW5kQ#vj4OZRvF<0wT8s$;HZLk&W@t~%uI+mYSxq=i zYvla+6?~&wSasjG@8xv#z)AcVtWHmU?kOB59#7rW``)`QrXvWgFYeo$ZejKQt~+iG zM``_d&OeF=b{ATB1MAAbgA)D%wcQDTWD4(BE(2I2D|6ig`DunOVS&Nv3{ z46ErqD_LRw{1?($9J-An*mi*H-3ay{`rwDcJG`d*p8jwWpAq^KL4J*X^xntclOBHa z!>sy`rGp0#gpUkZ5fk=PX~Txi=_@$$JL%~UEGV8@c@8Ur+tLR<@V!{&jiQj)oOW)z zDSh-KA4NgRwh8`f=3tJkc@LE|Z4T}mg8vIPbq^R}CIr59g(2_BhB7ir%~wnIt% zr@z9s1-6SEJaCx0%_0=7BdM zkK<$FkDhoky+k`VbIhpUu3h+{_z(Z?-*ZIezfSM}uJ@!8KmbWZK~(QaZ+ZB!u$nR5!2_?R{&Oej(^y&4_Iqx> zEp1%Yf$s(9T`J?sJBl-uiS}`=3|x$kJ98*~MTHD21M}Z!g?N?wF&?XgjA!#Xx5`3) zYzd0I@-kyG7Ag$TxetVlEEW8_G1oN<_M#^2q=fqsu>zf*f63)Ov2wy` z1ueM-bfkIRKZ{kPh_kE;jcN)C95U)Pq04;aW8%j(D#ID%txB#phOyzRr=+8aF#-*$YZ~^>C3D7Og}Nso|6BUNl0ItLAI%RCsoGHbFO<|6VQ-)GaSS_&{w*04Z>~s7Oa3)-%0=m0E;QJ<^9v z0-~jrPBXmZR52_SxwmMyOJ9q+mt+w|(v|e^9)HI3XS=Bs@X~ityc4FNr5}n&224HL zPjd$J(AS?ylh3~dNNMJ3F6FY47J`|nL&+d)xdIrhCgIpSO@aJ$Ohj2t$I6m{fuz9T zbB7ok!g4Ql@1e{#PAyoud1IRBz#}*ldiSL_xj9#LhQcIQ3qsDtp}`P(b(-hNLGF>) zDVAmHQ^Cn?GXk7SJgwh)5ts&t#tXz#vfo$2-BCC%}pzkdKl{F!jfmsg`{E5cQ= z%(B9#kgif=1_HPesbHl8#93&f(nM27d4Th66tS?#{a(P0|(M?{PSN-fBWzMa{8VR zyq`R`ro+H`;Cqa*T4C{)4mt?QT}*(<<;BM zV~>3YCh8l~vBSsHzP+!e7hirY?SJ)T0Bt~$zq)Sb-4jHl=gyl|OrCAie(s zAHcMIb9(LN6DSEVv*+l&r@s7k%=`DCNSjW*eLd9U4rsC0DtcfKMDOB)1%b+rX8I20NtPX>=)9vUf7=o zN3^o)4#nnWJ@EsfA{xtYQZ|vkFzbJ6%+isgID*Vy!qKb7#v zPg)0S|H{7LAQFEnt9b@44`$4Fes9!uT?BiPD+i6}!2E=x3_5O@9N2-WkClp>kL7hm zKp7Dvs172g3*goG*Zow$$`ecmTjA0enp&xSiG~5wD6R%SJ<0k}2xm0h!`zHPIAfaA z2k7gG>zqo~k|5JGC#VfKqz3IJ$rfq(2^d9n%Hg|g*Ewh`_-b}Pm{Oypuk`%$dQlbn zB)q`~U+x`Z&(vAYMwP$2F~2F-VG$f+$^Sufwlw|FoMe>yaL07TqUUdww&MjT5dipmIG^{G>c#rMa@^< zd|@^9BRc3@_OYN(O&%YK^Qamppss`|EITeMSow*0Jy%d`k?NE%1CtWR2&}=4_uQPc zH#i2WH5p@kE8ClJ%gp0Z&Dc_=zuJ2}8aX#%fkR2l0;aE`VRikjX3Zf*vWUyd2f`y$ zPM_oFrmg0>-cLaz>tc~L^t;~W2(N6vD`7|B)!+gTzX`TuNlgK``r$rolQ;?U{W2>& z^%Rrp)sU#h^@+s3x#VuuGl0JYQ=5fdvSUi~^oV^eL^grp+W=GkW?z;{XR& zv1;zhDRIQBGH4cO;9r9FQ#g5RQ+8K~WR>yK8ieKEwW()qZyJ4mAA52+F@R{R>mE`I z9z+44z^wzqfr0asH5um1D^LcUIH9RMssOerG?Phlco&z&Z(wjNwRSN^p{O`FG@0(Y z=YjO||M-^?iuR|^J@M)E3@fW1C+GNOfqrW>$Jc|tbdqkaqRT+;(O!j6{}U3pHv4LBQt{N(ZlF$BxCys)~$LXHNo)qr(6Nl#fD0o-Zg!xm9xNYAN{AGk%+RQAbu>}vTYZyP+(ME zvUP>2Dtwodk&uT1b@KfJDsV{vl-HzZM3bO7M>3i_>?|%OM_!;OzsW!=$ftjh% zI39A-n(p-WNA89C^m2H70>^p!1n|ha6UPsy+i$y>)$E(o6#ZeCKK$(0pJqHB#-sga zOxHWo`~TwG(`~!AVr7Lz5577)Qqt9Dx8mrFqJiT;A9>&wd>p)nss2cub$`b#x21k8 zCw}uk{^#_a?|NrA57bKKV*eQ|2o9x#`(I9Pdh~p zIJKk~UU*R<6yF9X!+(M!;A;BMruCa>uYBxpEUd_5EHJ7VR&+Gx3! zLiOoN2vN{=`Y8ui!9__WO^ag7(#!i|#hS*y0Kre@^$c)1`RBrR;I6B`pk5E4xq$25 zZwS!367mZZpwRr#`T4TAw?-#Ie!SertV10y_uaWQW4XMYVZVXDxjC0Ea2f4X_8Ea? zURfG!U5Y59?0Yo@3b+C=hcDd9H5DolGHWevb!9H{l1r+=qmp*v(kn?8dnoFXSBOkl zOsb+Nf2wt;t$Ln#Ns9S!Dheb+61=@)gcff02IbOBWIXNFmWMo|d)t_-X}Kw!R>_;V*qO=&f0ulHk7Htl^Qugp4g z%W&kk&W4vy-2M1-Y2v7`D_v}J&807L=CP>CxsIW&tj>n7jR-TJF*TH2lEvkxM>5Thf&*tMuffCg3RcP5)@?~M-LD{Yb+HW{!H`L&6Djv% z%Hj&+*3mjgACbR-Z@-Sdok>yjMP3M(*9}(C(AR*%ucrK2u+JG9S+Uk^+)1ePYD5@p z-l53AjvfHCG)&XzgMZu+1a*Tsd#R)R(&BFAbC04)_D_=meK=e_1^DXv5S4ss}KUUG*Hk`cpT%nzHa6SUKiPN zA`Qn7q(08EWHZq8hkx|1Q$LRH+qRh%$|Lx6fPZu*=bjFzI35Z7{%1G|iry3qfD?dd}-t$w=SL6>6wwbNw3u!1Lg8dDJ zm7uD5WA0~pl`!M;B^19oev5=6KWmL~8a}w=mK}J8??dUNv-Qr@x)y%}JX@9{h9Z&u z%Kgzf#M}BTl<_zP%&Dmjp~TkTfx=vTL&>AkX2;fb(QesN&TW(M4#HonCep=aIYN(b zWx6@YocolDzN}Ppl{xA!Dab%~jdXNR*(b&Tnl11pB;b{B<4*l;Crh;~DJAEjuc3Y_ z1Os{{A5jr+{mao+4D6|1jrZSfM({vzue6OZ+M@`+A-(N8?xSyjQwAL?<)#oqDQZ$Q zehVmpN~x4HvwhU#H7~vMZ9t>NNCP>eJ=FVIADf!ug9iGr$X2dor>skik6JIZac13v z5A31u*x>Sz_Uyz#=y!sLmzFXf zg#`9AHg2HaB;V5`Z}Q3{+^Ng3k@FimF- z!|@8tr}@kb$4Js-G+wYsQNx@rH<`#>B|?>w7k{A0%2iu}&jqRxUmI7+FyBLocEr`a z%$IukVKsOL7cU#34py#AC>S}3ad2`_av%;ZErbt89>m|EW?vA; zWkm#YEGuO+RSeisk=jNyzk^!YN6I#Ez*`8m11Px`Oi%-V4h-{D@?{_egJ(RVpOHOy zJ}|4|Fb7l-TT@mwsmKMWGAQyAmiv7fdKGs86h-+M6LjbX`(#>3SK!M_xsKI3R5C_! z0tsy5?TVke>g1O!Oym!)uw&xOgw?yNQY)Hq;u5$pVP|EnR&c%o{+xi49x$;U&^CY8B8~6-%|$(GSyVNW6!k8GauXHgC_qNo+;Xq}J>yn>qs$+Z7s|Kn zvd*<|3rc64oH^B9WzD?v7Zu3gi0pr(tWjO2>+%wPh0YLdN-r^2@p+!fyCO+FU6dQ4C?n~oYW zxzoBU@OQw9|Ni7>?-55H)mqF(;$O()reUJ#{>@pW2h%x;ckeyB;3+T*17RINI#>Pm zBClDw1vT>ANO<@>g1JKw;Txt~zEJdmR|pi~=y%SEeFMjLg%u6yDVFb@N5WwePr2PI zS5Y=+*J~Qj>gfb4c3LR7H+pDfkp0IiIIDYYtjsBdyH9mJj?FG&3LFl{*xTQTaD17v zbi&uQvKRAVFr_||;5x~-)w8=N5iXk9GpwSgjTLuS#hu8n#1WS;bqY91o9XOI!G973 zhkPXeUA%Z9Rz-DyN7ZB1TmIAHdqUUh;@vd66GMp=m!@D1UG@Zwk z`{03BsAEs~2~d$TOCM;~q5|=1We@r>K<_qSc!5Li4V zU>fB~BQ%REcqW=Sk45rHbV=?q7!yTbgRguym@AUx$C_V5!HqCWNL#p)Y`=3pmU|JF7zl_f;7i9~1+A<)R!OECIs1@;b~&%%&3-7Z{3#48 z)LW|9=)ESky#Qwg%#w3w0pC_Ft8Myt=U(QG9!Ub>C{+7ye(w|sZF0R#U;gnJV+dzN zL^}JtagGs=0J$!N;6Eb^>M9_ZvqpS|FD)C{CZd-K7o_YbZXeB}ZMANGI~>zm*lv`u zq#x4v6?EI7UwNqmqxwM*6%tm+TW9o3o{NgFppS`@%0_x0IAKXaq)bMZW{wtgjBLYEU1LvD;Lo5Pjz?$&-eZDE0zZC?6$fs0!4*%%bqGiEO)F4rrNuRJT@wZVk$wO4~Wi5A#> zPr(Qx7kDusFmTHd8Kqp#;`m%+tY{V>@}1u@peAn7QshGZ$7mMRDFG~!D;V5NH5Xy! zxLy-_10F4R88}{J$qtCNr5^qRf? z=D!8f8616sI{VKnLo{Mh$csig;LVp`kO7v0BTYc5rj1F6ui_o(@Zv+@56z2uWDR`r zC7OeYFsiVvKUW5pQ;I+Y=GS?DO~Vy%$Qvl|E@UTWUJ=G~d`x+9B`IIz@*`pbu8ebr z5fF+x7%JmYrXd~+k9ir|$npdjie3@qA7^I1~S{hvq_6w!W z<;{)Flmw5t5p&*4Jm&=Snm^#>U|7`Z%4F9uq@I5mmiX8P??okYO){Mwi!x8X?&58R zd59z3@`_WLfJ8hhIHv~B35Rc($j7u)o*>TgRUxZ?;9SJZC*tWO&Ixqh4_OGs^A-BK zE0HtGb0J`$uoO?d*^7fF>#aPufZsHe+D4psrS9I;(z7Zxv;Vn~)#N4w)FyCrr8_EP zbrD37Ipdq*kx+RhC*yBjE4)q(gRdo!{ph zC&Iu;?*HzM_Ny3zg7YEEB4n7Ad-s`7vFa?iK32!aFu6xNPNB|^nU!++)uD2q9j7^?SFANT(J$>t$Q*;40x1;;(rR%^sEJ&~bux&b^p{Dqn zLc0yLy{7mYatD@z?2F}wz@F|)GvniE)8tuQTgUKQiXz+CYB!yLfn-l{Fds_ zQ64v)V}(SIc>(2y<2K%#kSz59LN-1pF%zXAX~?jE0>d_TcpaV@i+kDr#@o-VYfM3K znx}Z9Vo8ez@8VQ$EzVXyc{}nHeJkd;jMpx1Sq74s*((f{SAZ&*i2u!`~3yISb)}%+@^iXV>^2>vbMll!R1-j--UM00R zuDJ2zJ^ERM7C%Lr{8sic-yHe8a<9wJ<*%3&aO27MIzSP6y?(A)uon^0%V-xb2FiHF zAZ1)7o`>AI$w$UYxOwJWm1;X{k1I0AQ<%63iJ%~(4~qdSAe3-S8ciY+)&R!yxR}^W zWg_84&Ai#8)Cj7XMO#fT@!Zkyif@`){LK4pc9qmy60MSiW>^L-t#&PJ2gJx$39LNi zqHAfoBr@L~39L_r6ijxa3Wk+cE19@_p9gL8Nxa3|7osk6 z^43qBa%4_Q{uqlEDx^L<;G3O4ZtZR zY7^vSH|#ffTY@ff#W*-0PIX}=kh;J{pkAM-+-HClbfavDcQt%=RajUx$|?Imu5tbi z^UShrf;6#K(PUeCf`bB)#|bH@c^11))okRFcS+1xDew0;W zNKkxJTpfzVToEy_xS7s;uGK{_KRItPCc>ypw*!6%5iq3=^}=i)++4VrWh}6K_q9t$ z;nfcP0ST0`-C^JWUJ+eUb}_j=?j+-+#ILeZmB4Ab%aLm^5#a*nfpHE+V>dOcNqv?SM@5a>r3`&YYj^^8iY5wUbyTh}> zY)?=h!tq$FJgd+FXEx`>io2E{LnstJ^{M}XhxB_>Utcdtd4oA)JTKz$h_N1|LxW7^uA4;|=6b zp7S~WxXpWI+T|$I);tjveGa}2FxM&5df~^_Iuh6 zS&=@~z*+6*)1kws(^Fs9+1fFbB{(glQ|co^Gi}?Q=I8sfJdQD6pJwqtY$55%}ik_L{69G@Hx>k{i4mU0O9A?O!Mh4?mynY+g|DwL{F zlRvd^!GejuIO>r69&M@kt0j?p+M7rp$B0MI;T<^o_LxNJCeMs=+@8X^eJNYtqSC%FDr~9LI6S2k~brD5tdWr`0}~_Zti@Uzxq~&*26Y_zBJX;*Yb4Df_*J&#ZUwO zJlO~ZeY{mjMV$4CLCHW{BJOjlL6~Dxb~;eT<F)<(_u zZ1QNE`6B0r(RO8VF?p}VgH7O9Q#g;g-71N$@u3FxH9}f6JN2k5De6TI0xNA0VevVg zleh}Gq*FEI4SuSt#L{Ii+*Ve$;E;gHvz1#E{-TjpWHRXLJ5O_i;@vT0!2%r*s^w+A zH2pPPf?E;<3HV=@ZSo3#%#%N=P~e%LtN6tPq53+{Q-KU{LvSz!&rXh=%#6JOxI486Thf;v>$|Zv2Fs)F1ay`;GT9v zLtU$}fMC+Ea!|png*MRI!?KhCoV;sUq<@eY%P7+@|5OS%2D$1Nf;;mw`O3Cc0de{A zcxqtltu)bOKKscrp4C6bLXV_->Zzx2LN|mt{{%eCo_qGn&mfd{uk1_1=g+ZPK88cE zlbm7RlQwKxn||O!KaxK3Uw;pw-#n}!@+aNh$KQ$);Zm%k+aMVykjAn@VI4Z+3t|8M zm(nV1h`)<7)mOD$PRCBYl6qKizGvr#bmFG->5H%7M3D2Y8NmatZP?5_Q&Z(pEFk(h z4zCXj<4&wb6tty7?kCoh+Q<0nGnb7KtykPLgXEw{;E#dEd-^oM4k_f?H z0lIxyArnV^@Tp_L==eo=raAS&Pdcp~X6x>S!4arqyGjKG=pNF~U{!#^eH1MsbZ`Xm z-ilCf`)WDVj;2GakAZV4lb{brwY8&A>Y^T|qZMM?iYHvmveG@qO83lcGv8)b&mp8+ zUI0oem6Vj>N7FZ5NT4{_^wpNF3pXpuIhhL7)v}M~S zQqcGL_KZ)Aq}4s0>HfR!E(Cj(wIG=VwqSEmDA^s{c=4V5wU=ei4XceWGSvsw!3dx= z@%8X)BCh-6H4F9`BN~J{NZ7czX;NXea#Q8-7#Je7te~-rlP+LJD`e1R`j}Ah6UTd4 z9%ak8aS6V7tbH%@8dhmo5;{OS2)nn$dyXWL;Ux59;YUOhnSt{IbgYhWwi4z#F-X-G z7A4;BA19GPgFw>?`;c$tZ;92M;4*r_dxcIslrZK`EbC|JHBD5Lw3@rbHF8`nLNySp zj};LH~b z6erIFO=X%$Q^JxvYOi8kDawjWx#QO+y7E~dwT)KhzcS?#Aq6(Iu;$A_d^wWEN(S{R zCr1(}^L_z~ThPhy0x#d4B$e;AMJyL}X=(}a$2jHKBs}JxacQQgNBr$Oc5tTiP)tm6 zwFzOC8itQ?riU}v+u7de)d%Mb&J3M{bIN$vtZGJHzKU!KP-shseju){#Fy1pR zrt>xacyXjG!wBZtegd7vg+B$p2Ar*p&|qWGJ+0o6+F1Qn$Z^$el8OHm&k7?GOv>+m z``c3=rs<>mUPv#$^fFcmOu~i7%nI2C;eiP=$^p-x_bl*fR_s0IDg-oygmJ8RTyYF~ zftdT9y);|aan_!P?o40$+P?IUe&%QK!hJ`2dH?>{&T!)FKzilqsk|Bru1>)7>KvIN zgvtq5M-`@AZJpp~xEY-FHQ`WhY7(Pol#5L$grtD0ca}QEI5&=m@(>6hi>sgdPVlZE z>io^)vQBZ{cn=DuIOdP`8^$}grqQnGPmCjUJo`Le!r@C+K{ssPmQI{H&%AF6^Y8%_ zr0fw!`J*7A(4&Gu0ab+rM2NmNjiUf*B2T)?Iyo_(4j9?eIeKtK#7 z8p#ZnZf%-*(0c^045m+kaCA6@5Dgt&ZU64a-<@u~Z8zZvu<+aIQ|F+m+smdnGI4+E zKtNs5f|vE_k?3#H7COd5G1W?*R@z-5)ji`g98q`n{Mq#IeYd3t?!7y$UCn6^c)ve# z!h|Be1Vz3&{lK9XxtG9Yw*>#47y^^_*fnoI+Vf_W}g1 zN*k@@%=iYBgSOua${51h$G*6_2dCoAE5j;4C!n*GtAbO$HQyALKW<-Wp)F=-C(}Kf zHqz{lGkKizXiK+S?7C@d@PSA9xqU(>e496KO84AzcPJMwa%7*|w{E}v&h*urrkrU` z**EGHoZ_kwuv$+mhoVwzpM!6IoC0Dc;{H3trq|6CCU;LPiWuYTaXg&Kk%;xwA zyFxmjkX=_)&5NsN?R+2)9XuGgTb7e>g|vmP+B#;TZoc~D+!Z0K09KpVpsT^P0CC-J z4u@CGK6N~LHN5nC(O$faT6!+r3QLu}NKT@H7h@7B90PKCf7{zNp>*{$e@i`AdW^}b z0+=g7PQdH~jtcUW{YJjdyd6v)@R!1HsrXttm{z{ho4U^1oUS+_)Lc9i{spk8Mlb*q zW~QMneE(f(Zedc&JeiQ9?>Q+4p4hwJ+!grPGwafW#IZd7l@*aLhUUNgYcW}{GQUZs zM80AnBOWtsX`_Nb2>wGVAU%Q^d4?GSX4h^>_douDl(yZPkbHFApZB?gH#6ukxsPR1 zCif6MHLco|nmSge%flzABa?F43S^uBg_*5e4tlZr8J|Y@#I;p76ZxseDNZ&RVfBwa zzNEK)o+G~rIZDAdi~G3-v1*E`|L)y4r*<65wR9X$$NLA(Ikrn-Y7zlH zjywZrovkUP*=8$P0d)@hg(p9qzW(f&(w}_wE7XI!OzT8ii z@l^nBLiy0ek$|o^o;r7w6~&!F&sX-pm_Ga?A53q3>;36$|M|3W>pkhr*N>+C$M&*{ zx++cT=ON%gcjlI;1rTi5CP3S@w{@k9=lWUU9R+8&Q0r2fJo|;B=|hqwv!s@lBC;5p zr4#SLNitZ`FHKdwB2&Ej&5*8nr9LaLR2mp2e24sa7OH$rSiV_!4hw#)0*}%)eb#3} zR8k!1bGG9o3LyEGDhnzUTRMxIx;&EBZCIHeLa5!jV=ED~>*XQpj)lc494~hE!8a?@ zCIsnkeDeUS?ZXI~T?p@a>xGEsRb#f=AW)97+KX5nZT!BszbV~+-`%OZ0~2#h=Vu!! zt9v$WEh5>I)%dE%vr`hlvI=C)vX*PNX=-_7fVi<=abtxYUXgf)kif^0;z6%!>OMFfN}xpDwam?tXSHR+>;2 z*e;9&z~nnk0V)~n{--bWW1-NO9(&}W)Z2-l5G(=0gdWPQ$Jt!p#?`6e`Ipkk^FwI} z_zf-i$^h0RFtmOV*GB5Pf;~fyX`>v=H_K}O%I=nQ`^_6uA5J9OC@1_CP_{fgGK^(F z-@0_{_^I?wV0R#t>zAXI{Im2|$53`eV71enI#A$^jSaG&o_fyW5VK_#3$IQbQ|c?B zIRt#o{*N9#ibD7_-u7=#$4?wggN#32d_(lL(a5o-%!1%8nhP9MzFl(6B-ZZGf z_T@u)mlt!M$QVhhan*d)*s_E&WbQqeTLWWmg6s4S`LFFNJGD?Md*YyG14Im+FN28M z=NL#JutIPM!)37x)UiVEh<8Zhf(fF$crHc&3GYB3>X_PBK$}X9p!Zc>QA(yz!19+Z_&zJ1VoHeP0 z5m)6Q)1eG5?~$dbaZS=lT={5JBO*ENSBtn|)f6S*KcDw1Uj{oBKV@C4CAFo|M#$xB|#=#)5?X&291rkY#RYB*02BluWh(AQ`H;j;3I39CMALTI58r}>tSu(z`v z-i=cuh*uZoYK~5i5G80jgjA6&XZt=c`&z6%SH{V!*;2qhgJ8xt-f}}2kGlm^K7BwZ zQ}&x_CZx@L_f`5+^ANB~8iRfGz2IN!>twhN{n{~Eh6bgg8(UCZC6>YOHvTFJ=*EAae2%<83H=FcP8#~y1c+hiwqyrMiEa(M-f;SrUI*<9ak z0{Q4Y1%1zYR~h4;YWLB%cr;uwP&nswfJr!Efg-3B$`e_lJJz9438F7gE=kH7AmjbbjUiG&`ST-by z&I#rJX=pIXO0)BI_pMKavp_5hSfOpOOq4tdMt;-->cvY0W3Jz6R0K`A2^GBcARs{ccnFbE7Qe+Q{e|_5E;ma5#PFo%f}8JaP|oypWC` z*vA?0=Ma>KLy0mtGM?6*Ka=jf@1eBjeUGFkp8QIBZGh7hnmj5I)Rkj^rgH(uQ?C={p{KGx8KG(a>XdW}JFtOB;_-?B)!6h?h33?g{$tKY9kb z=k@_ZnuGBQJXLbZ&nn5bZtP7DzZpeA8{1{h9S>7{9rUThIdl3V2Y;+bSiS=V#M$%} zR>Oxq0#5>h->eD^tPQd043~8Q>R~dB8g1zOb9rj}T2MrGDexcEtv~VJ& z$F4Z|XKfsNqR>i7*!iwpX?_LAXuvoS&m{pI2J*$-IR0X_oP>TSK!01az6s>!9Grt(5`29aE@5G*!`YDA-SX-XCYl z<}J!H`*prbx(K#X3V8Y~x|J{!EO~)xO$G<7=n3?tfuJY6kC%< zX!6lA5w6L3HIED8SHnZ{Q;9{La9dMQPM&$H+EO(MuIr;InHx4^a}9mP}> z3p@ukiHlWz?m2ZyClg#bZp2vPz_!R$;WnxpwVgUJ3-t=KX}2#efL=Kcmc1kJnA6Z^HC(*PtHNuM*6>_FZJILe!gumivo4%$ znK6rvi}lS@t%r>fRVeFR6Sd4@uOit3jW7p7&^G9qkujHCm)mG*7&Xl_2eR#$gECB> z%XjFYiKuHR3iK@q25kr^Bdo%9bgo2b)0?_`VcoCIbb*POo~~o%3N#h-gZ_cCKTF}6 z>$Z5h5=-t>${evG%&X4HVl|s`6x5Um^SqYtjeF{;i$YbbPLomG;+qTsJZ7uWl_6lt z*Q|2~0=_!s#Ez#;^~*+nMZ z&wcST=|0bj-?S^8KXn$1n**s$0hqnNvj|kv?AhJ^&|Rtbw(V(Z^c+Ifa5%(+?115j zH3U58M6E1lG&5nIxQK~xBR+;`*D+Qlbx+mKDq9Nld-hAgCNnGb=D{jxm{;q${`3 zktU=w@JBVKrga#A;D^8lB!6(8Q{ySx9{3XztSXL)BCfr#pukLbLj#~boZa{+`g5qa5tr%zRhVh zjv9yHVYj4@+fK9iv}owyyR1N}UkSF8K)*Zg*o`ngm@bbFrlEm;a6HMX_fh&CeV2b5 zH*V&{oAs${MOV6m@<)dz(y5EI5pkZ{u39R1dqPC?gZ@ICh0 zO9^p*Izo7j-5CgI5uEr?+U&SH{F`h22EXczvHGI zX&r4fK72AA=^sw7=~R!p*f-_Nv0XQ%JMVrV9cKGPPq*86Pykwa_+i#RNr3El86mQ@ zgJXI55KO~E@}ccr^nzyLNr zKkUyknU-K$i>V~YSLVTT-VyT>Tay2C=NS3RP-I);7W}+Knl~!?x(N0`5kD$Y(H3Hq zQ8OA9rD43v$?QTEBUknEg?#bZf-xQ0gi-_-a2)~+fxT5GP_CaiR0`2JwGEOn$N(zO zyz1b=e~c}`C^AbPg=$j~M6}u->!fFCO}N603$0>Il&mvwGGaX5=&K&R`qGROon>Bu zdYN`HxMdnLL~ZLbmXWphDiXQlbt1Wnu^jFCT^Fyjft}^HmTpu%k?&uGTB`n4UbLYOi9Hgb0 zK>aiQx8YTwW%VlK1Ly|EF|JWt#~wdC{uma^8&-|Dh%ngk$TUmTab7Z9nJJT7r6rR_ zfadolU{|8WE5B4sK7GBim`V;GDm-IhC4e&AdPnD|uRtwG1tJBfB?~gie3yA^0nV4^ z283Cya!iOuwE8!ooYw;~zKtcxqfMYOU(Yh=^}q};RM7U8Z%>MS#3rNnhraeq^alUw|=bCA#Aj}d?V;_fwQW2E%7+Z8oJ0TI07^hw2nDPc$Q!8 zzULnHRG&^KPo7{UcbIdk*M{|wi!!b-D`dKY?r~T%2n=nkEXL}mb2{k;QNtp`ah7-a zRpn-w>KEgz^mA;B`DCO=fT#YMPdy@3I8c_jmZ-Z<&Q$uKAaG0to}RZAP*uik+_)vZ za`;U8$p7=-(@+2G&!(UHxqlR6nQ&e`GLUxPa$DNF?==*QyxlDT06+jqL_t)nIA6n0 zL2Dn!{y7aNq*`*2W%mg#8y^L||N#cHeq;y6cWT>HO2rqboqc!cwr#9915=ce@`U@X?3v z2nU4c`Y(hjyLK)*KGamZe}HWvSORo&`qc|Bz81pq!*6*9ChDtG|G9C{^te0PfwYal z)=GGa2HnCQ{k7}Xu+P3fwsSa+j9}GqmQ`;ZD|%wXiIc|>(kIw9FqOJ`S#hR~bFcL~ zU;I&D$7gwB(}wl<6u2Gb!-;g^GLyDQ#d??gWaQ~EI$7g%|$>01@gLwLp4zsB&zfpqZD0TczpoW3v?N})^e z!5Dq$)|+-9;J-C(+0vMfo;VlnRxnqzk#iRNi%PaNcy)Atyo(3t*<$kAtFNXZR_MD| zdW7Rt`rM~Kkv{apKaqCca%TwGo)F-9_I3ybaQVS6kVg!kp>?A#oCs~!BVEce$Pd|$n;tEw2^kN(eD=gpt7r3sA zU@s$jIRW!SmCs?NrQ}tJYizmC)Be1ys~BYHl?)KM!$%`U39vu_^2bR5chbi`?g-EL z5D{hjmY*WBTD+D64rJtYfRBdfogyMfWah;>sPP(yne?h@ItOkiDlrMEKm?ZA=M+#hMDUu!=83p6=^GYO z;u)465~m1IP;-K7kmhOfR_+TKwQsLlEKM%^k$rqwS4ot469c0LOeD>ndfwC#Sd%{T z&dY=(3f`+G4qnOyEDU?G7(vZj)?%56BVWdX%r*HPJA5tsh^ge0eAO0K8(u_Tms`f_ zx`0|H5NkKL)Tl9S75p?ea+z?KOm?H-Qg8+TdHKAiU=qeSxY*#jWJRuT0(noI%6lH$ z9jmUg9IBaXTCH!U3vh}c%W&*-zqMYJRcuBi@vc%j@n&WnD=Y46ws#0aTmruWP=reB zD4+_Tr|MP4RT5RB@>3;2H6rlfm3vmI+3(77xD!#%U+Tdc7uhN}MQZW(fqMl^QEbi; z*~*+n?P|m3;8>rjOc-~2kEx}aPfp@lKcrj)S>C!KqR#7v&K!-s-px$3cd;UN8Bg09 zCbY5{c8vYagJ%w=!^fXbYgk3^b;TGHTZJJcqY##-nI9=AdrYAf)1liSt8r~BS$$(m zg~H(G&D+ygpL-=e_NKdN*OtW8I_kf1|j1PcyWj$vG(E}9pMO} zLR?%WR{;0qqDxo^I7f4p-g%wdkesW9Ag}Npj78OerIJ&j**FE2h_i;I(G=KAhkEXF zk8zv1sLG5uN1gO;0kC=GYlm=zJJSPjQSyp_H5%JA-u1}P{VF9<`3Y2Z}B9RarkbLXLf^J(z> z1!Wh6`<2vPlWXU-sCdX9^AGvLItQlKsOB;}_^ZlfS}}OafeQeCK!Cr=a+AIj#!w)v zLYc4<{^{yM*e8uvII$8;ny@h7SLKYSC$w?;fot;F85%3_I3R2S=jOs%S3yp}Ucu1g z=6W$Dx33tiI3}&j{oE@5TIf*6j-JKb8k6i*y$IQ->0>BF;K7y5$@@>A;pjHbIY-&h zjSq;`c%&a=<+zn?A|4GGCn%tt7$=R}InJXLn3+6}*Zlzm+EMVs2_F17jlyCDxI0$q z&HXeh?ytP^8e0-LN)LW=)n8##Wkxwp+4tHN(h*QDqPTL8cNToB z_Os&N)67k!P;N|MHF~=M4t*5_n7PKaSi+ZrwE^=&yAvZ&^e#|N2?s^ zVj23?7#SK)CypOayKWuE+`l^%DAN=06&6V)U#i5?GkuT8*P&o(ygY`|4JVo~|7uPc zn7ypRO)3)8WrYAo8*|e6e61UvGhc;Z5PK=zR&c&iBp9GAx0#9Wuw{5jFGEQmv z0grl;PY=qL3mi!}0x$ZV*mK8Q(n~6Ix>nI2+p&Hak3KCEIUdzsZqsor_+RC^X2Cuf zu^4c&wlI2Zbh^Ah&5oLd8F+KvD}rmsop|;m#Q?`Z;J+d$KA6U2v-biZH$VEOX;zTp zUKyY*u?P!H%o5oU%)vW<5Q%}QWBGn1(VV8#UUT0wq3hGs zrhlWK%jS1b6F1*0A7VnBFvdzf5f0SBCrdWQ8(oW~%gg<0Idor~*8)P+-?lGWcNt(! z8Og3>nF9Ixh;kfweWWfBst36=k!n*=a9)is>M0_Eg%7H@8CET;RQ%+zh45=BzZRE2 zqvx`o-fO=Xm3JywwCemA7WB%I1)b(kd1YuO`<3C>AtW#<+b!TxiwK;j!J-b=q0s9H zqNKkd^H=lgfmdi?m5XXeTNZRN$T6`E^Ug~+63Y%3^Og|5y~g?Nl`q08KKIDVPX<@Z z8~!=D#LQQ!KV>MyipG5J_K?ZYUDJS2cNxs^-{?5{ z5m@(<u_EHw014*>z?gb0Q}EtPHmC zeQseQJ-ebaH6#4Yux}ahg?SFbEdsM!BwQ7@ECnu4)!4RfOB$KN%QrqdIuY)>I@hGn zKKXR|hd=js($D?O&!i`w_+0wp(?8DYD(1#G7JKR|U*$fY-uL)}Ov(|K5i;Bx-pC4n zX9t1-$HA@c?MgckOvadJojh?Y?cBMUBj&z84d9{slOO+N+O}2tz6kZh9IH<4m*Y5tv?Wj7BBIR$$pHx$|fk3_=7~$i*GWMe)~iD=W4Y=yH+F$ z>TbVOcy`s-9GdrLxU48*QJ`OeDFh-{M%z&~v`{vp8D`ci(%bL9Cw=DWed*sn@l5)@ zw>^?JZ^2xA=u$dAf~5n_-`Xcoys*-%qqIf@lsKmzc#UXYT=@;$gYU#IvxLsj+;87C z!^%BvFv1ah;%-Zty#M|wQO9+ zd)|(!6E^#8BPP@e_>q=8!So2~TEb3YD&Fb>82l7lB4`Kqkx!#^aq&Z?0J#IsEN1AP z&^WeHP`=!&g2MN1d_G(}KaSFd)#kN07jz%|MCQ#iXHL@oTiIH6ffeg})6F}#0h2aB zX6Qh9)z&tNpiX;Ho_-lTN4*Q-{PgMm^h(R+)YFL|&r0y}Mv*Nz=10%p?TV=qRxQXyoUv;dPN)IalstKfRTA0Hl|zi6${h$4bB;W2l= z#FhyK{MNRnv~Jz%w0`{>c%>_y?$>nQF%T;c%EWda{I!B$m7gsao(#~?+n3H9JrMkA zpKPH`gslv;y03>7>W4jK_7EEDt;74#W2zZPK{rPxo$U#hiSGxTym=gyt84$I(UCmIN;Tvf&1XcI117+Mk|Os_9?{orj2;O zcU#Vd{&Um|66s#&IH`f}D|2Ng zgRJaVU>5zM(m(3UdHrt|P_|w%UO2B{(%#4j+qR9geegE=!A)H&=g**!=V`yVQLt{wbf9$;_`;x?i=u? z?aHf@dryvT0bU#PqRVIkS}4c-^7tTv!Pq9efHRTy*tafLQ5EJktx}-QM_{!hV0w*V z8tm%!?|$^RV?}hshRv7~A4I@mH4ck_3!GKnw|Z@O=WbwyZp)h=Nc~LSKlRB^qqnf9i-G49$93ZAhq7s0BLecGXDrR^17%Ec>T$XkqjPhj1)@`W|!SCh$hvO)*R!hp>t=`7{_?E z(Tpvu+{mIPL$4;%X-X}~ z@o~?YzmSgo$>Fs6v76IYEj5_8tJDEG>g8OWqXntsi8BKTW%fIw_)~eH5@3oln-~mQ z;i2OvjdmlmoA3-<=4&~V)wD4$dVjBnhvHMXLJowPVoL=xK<@B&^WQ3y$SElh9j;o`p z$^#nGhhmaCs37uaL=`a}{irfa#Xu*Df?=HT_2MI9Vse!J(iwk;4(z91y;vJ`q|<}! zHRqCdC4kNA77)oZh%&ShB}WUmjUrgP0SzJ+CSvM4jm%$Pac-Pv^=?km36HqMyQL522I_^ zfoHw6a+#rQl?-rVDEL;a>Y~0_8NdT=$Vkz)c`swIsyUxfb{E9hfwIK;H?YdO@1@b8#xeOjTF@tycXm8VxDW@8SP5WMc2KqQ3iJfS8}dF6 z{JDCNYiK?G{9Frig3Vo56<=}2Rc>LvJ zmP))-m6puE>;z@K&0yud#L>DJ@3v+6Y>J33)0&>E{AOer%dF%wljRa#$1imYzMrR@ zd4d)!AnISVNbU228LmS_g`QUni;7k2R(&eL*k`@UcJ$e?unS?&z0=l@k89erd1IKH z4q}4r{J`(6E2pjuA`g+DzToWEOFDBaxF>>^{;5qp7f<_Y6+=;u1p|bOM$f)xo-vIh ztw021oO3f#AQAEYF<)5d%6JxK2YCD!f{m zw4XhDIt}AAZ1fBl0o=uO-y`o#uO8f=e&LsX2}fbu(?9s>pG?m_^9{_7*QduH ze_#6aAAKr4`?Wt!-+FB*;NX-yt=))u|DHQp{hbOE`yuxHI?o!w)cV+={b~OzFUG2T zH~VI%kc1VYod@h0X`j+eq$M`u@*ZJ1@x z;E`RP9!B79U=_a;p+|UU&YdG276o{`Z^jQo-|AI_vn67XRZ)}0#lk0sxlo{j`!?M2z-y2ZNTs#Zj{zlbU zm8D&1=P^vO&*D^0-tfz$lEyi(d8O$kEj*mdpro-oDeT7nZ&u2Wqo8@{)=lYG|M5?y z&wlpv>7$>1I^Diy8>Z|kS?Ckdw=+McQCD_7=>R%I2Z{@&#>hBM7xDXW(~iyQt~=kB zKK`-aWiNeK>cFSKuA8=}Pk!Q$(@*}5zm|UJhrd5P_laIZpFVju;TJCTtm;dzzI;5!ymo}}&W^S0tsmwL`_t(! z{)N8^I&JB>Zyv;qeE?p=S_PU;xa|X32fYV$M9P5x=kXozwXZ*$R&_O|b!>w;b@B)b zhKbb6KKZ^r2{eHF+KInzI5{N5O{J7WZ*^n z(rzkYgk@h)%sate|C#YF1nwpjFeeCS<(<`gz3poO@#>3v)4SgJf%Lr}cz^nnFF&15 zVTChAonxD-GMf$0MXhL?ODOBGq9CjlVP4J~#l+uj30pU94eOj<`u`cWU-WkOrXT&$ zA4~fW9ZP@u)#nO@h>ByCJJoN7eQ<(0$o5`&?5{qTeItkDU&CtC)y93hKVOqzZ{@6f z3^FuA5W-FbBVA^|4NfB5hRGkc+`%FrKe;UZRR;HU zbT`M#bP6;DuQ&V~dk^>?QKV=#oW6UYv zYqLdPB%r`CMwzmVnskdl7KoMgTqJQ$Vgc2}`AuHP8S|J@_Jtgl$3^Qw&LVqGZzcn3 zA;#;XKRL(pGDVq-LVNv@B_7qf=h{o280P_987oVY6>-vJ?gzC@Yh2_n^DKp;=}Kgl zO8YwE19Tnyf7Tj*O}jWt7>eu20?y*_!}JN$S5Yn3Iv^=V~l`h zyS6Y1og86x1!mC%R})^QchPV17(r$ksgBOerGYfn0I z#eW!HJ&Ax~U8SXM>uT&Y!bq6=gP>)(+UV-P=ECjF4PBAdB0!?LYCMV3qmflql`Lb! zqv-;xx6Q23_vjc-fh&%(LkPiKyNfLevzIU}CeMg_ue*9u8^X~{tiH=`%!W}6WbsFw zzzk+^UwAXC>RqhVUqYanz~{jf$9{EkyjrY;l0O=`WO`~8<0@8-n9`Sd~2A+ zzjk0Cbs>ytBCp>72oSinuj`FDwd@?Y$;%+*dGxL{Jh6X}2dD?gI@*eDPb#mob^&gd*X8!pk^$9HgC9 z5+Pj9az?s@lQV1sjVjLLv~535Cuce0@UQ&vUr6tG*W1%ae)~VC-~12%Io*BlX6Q7Y z{_fxVMON1L;4twZrt?@YaZ<$axgnHM8BbTDHQ~43e*dQ6|HH?QrDr%@;RiqP&h)__ z`l0lZ|MDB@nXi5s=a%j1>1V%{{@Jhn<8<$R_hIpH3Vh&U6b!?|c+6)IvuzdLMNpw$ zb`iJ=tP>|srF-wZBmLFC`q$E@Kl%IVbD#PBbki+&rC0G?@za0*7t#m6?}O0?Ls8YD zg@*mf@gR$g!q-}ZJqF>(t^wMNv!!9nTkc4I>4QIj!sQRrH=cPWZA5X>&yjlDH*ZZJ z{_uy>+O=EKH&H;i(teqK;g$EpN2^l<_=&!A39|@!K|cY5@bi{U8`JX$@?$7^)~#Qk z&T_iPBo-y_eEYisrw&&5<=2rhdtc9Wi}utzRdYflNCfYhaERKEtt4MaMDL8asF%KL)4@?l8$aesYUj+ zG+PPp(o6z!Ip*ZgmWxLR9N#UU(s?vE7fpwZ7o&Mbun#q%_u?v0k2gPTo~84Y{(t1X39x3zb(q(0 z-`~ued9&{T1}lk;1PBn|E{T#TN|qwap(RUB#kS%~l*E-v*-50b632=YJ1NI5t4g+0 zt|(OP=mfZWEMpq4)t2oTuqmG;*Vm}tQ4SPdqw!o){N!PB+;hGS(rcxIe(_2j$UpAbBGaN46l>O6{BQk*sxZEyXom{-6kb1m!Z zv2m=XVajVgVkH&0V+ici2*19&G`XK+#ok2@1?!nG&t73=dWw0{tc#C$1jjiR?>hHs zi^wo%QUAz~{&4zr^eTertBCK%S6B!0XJyr=AKy-UXj${_L4_^zOT;M<*V) zIZqtnT$rPyqwLpyD9ow9{cZdy36Fs+zqd7cN8kV#l^N0~Xdw=~>)n@q4Rd=}8$)>Q z=ua!1{julXGN-FmM1>;-;(4|{Eb>{w(|QLc;ccugFLxp|&S27wiFrTP6I~pwx4;$! z6-`UF6L5mJcn&@WKUeMTG6SsKFJKvP4WVWZp97jx4`8~iVk7d%Dg2kqJmnHBiSi?` z7gajYh+$Se;IzDsdnB|{6eG&x;`>s(QedF6Nu!@e;HIxbq3iK$imJvqV!Ba(?e9+Sa z&Drlg!|MAO?ey>?52fSyX&4^rOuzUa|Mm12fBw(IQ)grEH}ZS>8YcdW%d|6pDy#H0 zv4Ax}SpZZ}jF&C&XIKrs!fN^Uk%9ET|Mu^t|MGAAwe%~jdjIUt{Q_+^&uTF%&g=<4 z&WRBhaO&65J%qx7ttvB@*)D*POn=hRo_ypsW_K%~7orV&aZ0%_{q7%pJnh}TJN@my z`#+^GfAP=Mdf`>SJNBR-L-}=*74VL3wsTBfNSDVjMQ`tCY(++)VYOg!1>Ny2`^;Fu zvSgUkE6%1Lc+b1j-}?vuD1G|R{bZajpcnghyyG#d)s?>Rr7xyaoNJ%pzYY`$m|}yJ z^VV#w;`l9nm*CSj@bATcz{fuMx%9Vx`ER8E{_p+$^!d*|lU~NLUt8N^`tXl^7-xT5 z(hjO1#%h}C2%KnQ`CN@GB)US5`Iyc!%V(zsX8MHoVtFZdWCi6gk>@@42` z#DTovZ(3oMtDdEPU*cbv-&-iSUYA?KHQKZwQhsk6^a?fM71+0g?QPBsUi`~14lG^{ ztidy&TX=`)@7v2dlwPYsFZwyPiTkQeN^9G1?bQC*UYn}7X(Qi8L^44P3Ic7yj4~o9 z`sGHsbBfJ;3(!WpaoV7X1v=(k_qtyE`f-_d*9BTdW<+hBOS(!|d}7AZS4>h+&G|RcAT4m;zz0w*xL=PotgC{Fbj$b6_t@)!eS?1+ z*xrs(sd?4@PFPpipKE8e4X+`@>uky6(Pn1ZBTfCCd^@qzyccKIU?L3)^}t71wa3k2 zXa+O#30!in!dv1J-nS8E+Ykt1)eK=z9(9ke@jk?FlwAWNRHOMd*{UKU-1gk;75uTu z;jgoMC=8T|{x9qCsBqUA~ATLIn=nRQQIwV!t?za)WIE1MJsVI2&T$d+amEtNEe= zICU5A<&}Ouxs4R=Jw8rTZk+{EJbQ%^;FoqFu<0K>aWvaRy282Rvn$fcw!=u5{s@eTbviCdlg^`Hl|ukt0xsJVttz67q9atmd|i!s079 zCbt(W>8^G!u@Y-N-D9r;A?DoRs@HsleOKIV-({Dr#f`LXZQja$=LzF*On$fe{pH=($G>rNA&fN#o z-}wjsJiY(vhts>>{WM1=ZcoQgon+;9iuPc;!^~JZe_<+(Vf|x1`B`O&b#_t3F$jV{ z-?sFz&wM3l^Y*troWAt+=hJsy{APOZd)|=_-El`c4xfJfvwzBp{tVvX@iVa0%?j`} zlu#&kq?0^gKT-NtMqw*Owi}1E@XJ;#E&k@O{gd<;e&oIB2jBN@ywq>S`r|};=8IoS z=UAb?isQsd6lAAPUBz#KZK&sbywStA9#JSS=p|o^g9+*~JlM%mdVA8}{-1w6{UYbs zKltDSX*U)M2`i76UOARde&;31=OhWXAe=nQQG}SjtDID^vjTkEFYal7&_(#4pi%gT zZ+`86`Hl1oANlc6a?HXnBPfTif!mAEeKS4(ofp||)1HoBjPLx7e`@V;A; z!l@=W_YB}L&wfCg?O?0Lul(BIPk-fS|NZpgpZEz*ZFm=3IZk4&HIu&jwa=t)efwpU zf3s$-XZC07s(IVknKE1$QcrG^w8<{ii%U7?Us2NM=u$oW-;TWRhz8JG@FE0CAEC%PtH~sf*5$x+PBv~Db2H|2-&z+sX z!7wf#;y$NogjZozssItM9tIQ#Lp6vp)FNE(aT7Xy@C6kwDqA?f^2M!!R2L1YrZ=3X zIN9r9&H zyNz|AIifFB&9asUZVD>E>g{X)%#^B!2I(Miq%}e9YDrfMe^s{vYX!d+4EP2LF>y1R zOcl;+6IUUnj%3XE)-t@R3P5#X`neIlO%yjoZ_^R0%M$l0th`)HRi#UySEY%2(#Axj z0f!s!BU28H$4w(tOZciY)?nPit<`K?8{krC6n&`TgiNGd_eTEj%bPj{Tryfj_cL%CZKC(d6=+qdk9aE0Waxhy!Zu+r$h zZavCNPgmJHnWVd7?CR^8^GoTIfBL5!(}puFOtE*2?nrkYy^~|NzJ-vFK!PCC)rYXl zB!3Pqf!jHqkSoZaWM$Po^uAL)3tSJ`_8YfE@)JV4i!RRn4ELSu>b_33%X(_ij!3!&5o(N6ZCD7v}zuPVf0z z1$g|}AWrZU*cII7XD&fjRt~94%s-uz^6?~rurhFd8bY00Qrg+iKR{pTNLMB~D;-*n zBMfzR4yEC~?eq)E0YB%!%9AQV#1Z`rGFE;+YFVN1(!-HxgTR}_LEJ3+sbj?&CvIc| zLR6i5__qWYPDGvqE2!rA?Go_xGofO~J^$j)B5>qYp`n9DJ@+Fu0ztaVJvhUIghxlW zrT_Kcei9!HL+LO4wUY=kX|CbwHHI@4MdlWcu~r_|0_rI~(j0r~SM4ra$@Ii>#hcr6(VI3#-Pn>9>FP6RZsHj3fQJ`$yB<|g#)`s61+n||~M-ivZ@GQIfH zu{1ja?~?E8_!QO+lWZU1jC&pY(NK%vDJ^9X6?5{r%CJL+4yS`yEF63JyXoKjU%!WC z#<$Z058Q_%z@BvZB1b)9dC@c2oqqH~AEJzt>6tG)hvUB9Q1m$ll}lPUb~rZ3dvEsZ zwg~o3A~`g2MelS#C>_`v?}@ip`SBvmcS;N#5pGzeH6{sTO1g}x)(X8*kM-`gkr_JG z+`_0nx3gcw7gv}|!Eg&`@8-}3PGO4Vxt8r{b3GEl0aVYfU6!MeZ|hb##ZBNt0D;zJpk55q?p1}{0&ufRfm^%QLm;LZ zHwSh-Ff9s9zcw4CH;XOhr`BvEg|ntM3t@Uln@YWChWZw*Fkgt_vVX znsmL&tecg0q%&W7se;%L0-~m&G0~!)PP%+QPqOOk{2*3b6)^*yj9<`40^Y<`r=L(V zkF_Fgn*3pP3yH}+{tH+M(g4gYSZOAClYc`($QU@G25*IAO_80lI(c^NkBM(pU`Dyj z2R25&RJCB&><{bbDd~(=q3U}@7@5cHTN&3_ooDil%pCP=r;g5CV)g=%JomB(yWl~+ zsSnkOiFFtAF8k`jeD1TZ0K0^l4pFs zx;m$&NA`Zt769gt!g2*v6cxx7s>9?Sfm-Kx?xj~apP@eDZylARE?l@6@Z170jM?xm z_wt^<5J~~z3TGCN6iZcf0HgA|8{!s(@%3Uz~L~jp3~tT{og&- zdq%gXr=NIx`pP$7pdQSx1waj#p~W0RZW}AnOB{!HmDTg{2^=i4g1&XQhgIzD={ql+ zOfSB84B-}Q684r)&Y~E?9KEBH69=G`$_IHvB&D}r+}kO@69#niH#%}4J^$US=?h=| zqx8;)_NM~}w__fTBhNNg=UM5#dX;n8SzTXT=InQb5fua>5AZ9=x)>jpDSOs!2(%v{ zF{@{V8C(|^&ZVs=Q?~3rkiPTM*>wCg+eX;3GKtpX@)$gcC4r|Qbah}&0rLqvTMk)9 zuKx;(jW$-_RjN&3xzUbRXQ$`^{@;L^pU!~Tw;QTi`R zSB5x0p&X$7+X&O#e^D>|y#w^erF8bv<+P>0J?-Cr7|Vc}^wHn@0~`{n6ySsicz9xB z7NvqK^(@%>L9@89q{2$LAjmb(7~@L)b{yp0ap%!=6ssOjWBB7g`B*x8_H_F0%g1B8 zL>3-Bj&V2JYVJw9_8(zO!liWV`0*Hzw0@{x&39^5P(AWZb}xs&>MIY%(G!6|L-S(5 zfPxO>%Mylw`|SV@APyYuzF^QGGeo8ZUq*Cp_{^~+4_7dxjl961HHl^jR}`sZ8+&lJ zkES6^ae6s!qMyA|-3+{psI+Sym>lQ=2pT!}fh<$T0uu;5tX{o%K89CC>y{rOu#UKL4^eVbmVph16872f}W+b^z(A^h2o3Mmx6<6m=1wL zzPJIV9mV(h8ZgD8kb=a-Ux}Cb%G*1lo)2oz;Y%M*C6Jw_|8yraXE$e3PYvL zW}NMlvzjt+ub!))8r=17ZHq9yv*Cr{%!tcx@y=H%XJe>M`c#+{JPLvVFT<{YZt|yI z=8f`~vg>)SUrY<$WDnj9I+!n)7gflh16WHtUJrc9(}25CVoQzI%jM@{D}Kp!Y5BH| zBA`mR5!ma7S2U8DGDGFmf+VV9gB(|ife=-$24pQ^GR+J^d1pPCYc|zC5pc|Ib26t z;Fg>@WqxWDM>>TzhH!qf6DC)*4jnug-l$KWIu(Lmz>3LX9xHO0lvJZl;T!u^jMEmf znxKt>>o*m$^`KSv8MdXi;$O;Km3+-(Ll4FFXWLXIeXQ~_k?&-(=Y*^iQ}8g~cM>W@`oDLX-^5}w z7dbNXiU1k>c!8r06L&zQd{?cNYZpns0M9C@FL0dJ9QgEiv)3Ad43A*sAO;6rq%gi-Um0@QVHNC`H2Bl=7obh?gLMmK#1eFqBiJuLZ9FTPs5qEwXc-Crg>7v$ zUv2blrqyC1J{kE2Y+)HXHhnwxP(``5a>I*Sp7yY zj`Qo`EfqoeeQ8@#4*U}zNZj6znf(;Sl3tVej*hMD+dxpp^5hbx`mXX*D{5=QIDS!W z`X%}}>Oi|Wwh?bbx5H=4ZXIBZTJZ!7%DOz^cz{VginMW#r;Dv2_MJP$6* zI7bvt;7B>r&TSykt*E;`H{d#icaE^c(qxQnE|O!*P#-=Y98agI017yi38`%`oJpn? z{As}Z)6>)!A19*kXw%onb`q>!G_(KOSHH&gm|ct&dr?+^Cl(wpzI+B@el%pUE12Ow zfBba%_~)NZy*jRhf$ZBeC=j}#ftNUjqKY<)?xODy3TwOrWau~9bxVSMriDa-gKX^l zDx>qrs0(i6h|8CKyx93&t~A1?SA*uh8YeWGW6Z$d(=bm=0C0q`XAcv>(S0#M^)Lv- zdGXQ1s2V@Jt8i>NpBzjX;dw_fDd6Qix@RG6IXszGa9lCP8KKuso=9UazX;=wv+suv z)&-OEqH@qxJMC~=;KhVMJ2iQL%TDH=J6x26GGGxW8YZ`^gEAlUMo|3be0h+}0p)wW zFynImlInK-R_F&hrG%IWln4s))~;W_%2WBR$8CHM6bgxQpht9^Mxm7BAX~fgq|pp~ zqM&+dC8POjnbx}%1mSByte4i5zVL4ZGuL8W2-gp6;@vC*-mC>T^7~T1VdWaB8#u2A zs+Q`yw^3~Yw2(laycMX;A~Td$SQ~Nt^_!qVvVb;m@RYxxUsXhY%XDrn(?kuPt_lh~ z8qB}8^g4u=*b-5G3r@A)@Xt{_TeANmwqEm!SMDdP0X7iLkgDj7=vNij@?(}V7S$sn zJR?x`psoG^sRVJJn( zM20YzC5;n>EC^P>8pYS18wfTcH@>N5+c;5)X#&pKZYpyCF-O#)%Gzl6AWDYsgu0yw z$H7P+R5Xq!!drQ$;O4KXE5P;Ob?%!r$&szRlY4nUTAk43M%2R_mB_HlcLS4_w5#%# z!~z74?XIc4?@?DeeeWxbMPHF7gbU7zdY(u4u24`hJKv6#+{ZJ&o4GPS=Dcguw?c}! z9_3&u8~tY){#9Y`95@Z3q-ZFlNRn}4{>@F)s8ou$a%;HVGAhf@`j-i~__3MnYmvvG>OEVfhPcU;j^SUxU zh{^p`&MqHi0p^~2?v6fj8Rv9knA6{R^xpKy+aG6gKcCLw#ryIV&EPR7W;JhVd4`Wd z62h{AQ&gUB=;X)uWPIQg6)+MfR*g*wu2HGTLrtiPX4etSJkc$1Du4Uf1Mj@l`$;T1 zCs8)ahwintiSL4s@Wf5t zcF{<4eJB|CNat9&cW*jKT3;{6NYlA()H$&`1>7E>GG>Z>^ID~P#G;<_r)Lm;Q8X?4 z41AIV14yspG2azgVaj72DjO046m?vL?yN1x%CVLYF09ErA?y+!<1h8FpBfg&S;DK;9H$HV0^XXxf9xB5~%SUU3ao!n97Z@d^uKq2lZx~>Ndo*CXya~ib6@dts zi}q2Dv&+gTXj=KokT&v&G+fem1a))IIoc2YX&;2`K33P;6nfe4;C2Xk$3;eYF^@k4 z=-`l=_~)-4_T`6AL;x<6#D36+^$O1Gps)Nk%L?=gZ6E;@yHc7!n5GQnvmiy85<|iT(^9Ysqm1 zC5yDwa6*MvyOs^mIa-ePSRjq&`8qW8SUihyOqrgVOJ~kpL=iWZo_Xf$^ws%v*IoPb zb{vp-`S?Z3Sc;YXYZK#Xd|?tLLyZTJq>mtwv!bu*3XRu=2Fk!$7)s6e6a(1Mk-O6V z2i}&3cO6U}nA;>?thm{PD_|!WLk5IpqQUH3(P?cci=bRr;&V8-5Z>YDBpSAFbSjPR zy)#W5xFcOU@k%=X$_tn`jiq5ae+NMQblIDDNv*^xy|92J(iFYOK&d&{$OvXBl;caq z7oL}OtY7&>WSAf6Q?8P3y|9wz#=p_AZ=9?(g+4LQLJOMD)#0cOA+e=EcFKq zZsUbqO6J)PSF$xzmXM9nh_nt;=8vz9(?*O;^hRISmr=($-^`TqC|dt`(cT2awPlz3u8moPMIawvYoh7_%~xbIbYtl2r6wO497&s3 z1XLjf=Vt6p-H|=I|GJr)^^3{fsx)?&meTEOwKSP0YXM*^9L@B?`6;Pg&6>fa)_tvB zYSr`pSXK(y!>a$1+rT9O`}O;3QlZemdi(y136k%_xN@5sW*wzojNvp$rX=45RK5AD z+|8fWktLHUjH^F4b2aa3@#`cHyee*M=DE=wFoUsbuvcZV+OZ#%cc>^j3Ds0r0lz%Q z`Yl;-*2(002M$Nkl!AnI_JiB-I*;(607X6*8dUtxG09w+zM9T`=d0=3 z^PCZl@X!z5g%j%dTBh~M7}R4n3S55JqBq$%o8Q;sUo8{#sRF&=@RC-Jo}V z2;Agp`|1d*XuYiX&aomlY`pcd9NQn5mf=7w`t5>gj*JhD7&9UrPxwn(SRNtWHlLOhmYc@ zZwLjAIIfYEPp{x#@bE8I)T=Pd6W ziiBERsA!8ikk3;N%qOlrY&-B2i-@ye^0>+xJ=5h-?ia{^_l|+|na@9$cKyysdWt>l zySDbGZNq(RqtH`(O6RX!49A)K4veG^e&{{v*?;s;q2G4e0$9ws6)aU&^$+!94v)nF zZP$rez9$bT$je6ytoF(tU95gDIJU4FtT0Q(L&(iaqAbK~ZICTe{!0@oBg^Cg1xPo$zB;eUA;@4+upJ2a@$!jOtG~?aD?KxPgHS;*;|wpq z+-~wJ&{ii8I#+=)_^e7`f22}Tw^dQM|8Y&V450Y<;VVC8G8$e*Hdi-j%XKQcUcJm( zNGzOnvPF{bsV|Uh&;pDbI5%$AV!L78*CyQ{WEFMnkd3Q;-w1reZVE4#-`kH!sqb|N zUKJYcf#}Y>D=vlymbnXn+bZji(y}sux?`xAY~#;@L0I6T?WB8FF3t##am* z@xeL~*i3HyV^prH>@ZSSzmP@Q5CV91-9HZU^ham_ona4Mp$(NC}Y?5 zx%J90H>r)18Cvj)zy@?nvTYX;4ixIFtcr4Z!jui+f^a9`n#wxKtRpCl)x|Ul*ytvh zv=&)^wqQTj7uIx+>Xx5&=P=CkJ6Wk(X8tjahx4vI+taT5j-(Y#J&~tU4|~IVhH)rG zKKDhd{9giJ=9CEWSOBJ(wBxP!rcT$0ZJQqpjE43HK8W&b_}$EHCVzuO zidO#1S3xIWnWR)XW-KPD%FlJL3Jg4;Z-tXE#4T3&5dxeCxdNwfZhz(|_b4Z5C%mfM zSoub=v5oW7Jmhb1c_Z_Vi+?&ZK`1K^{IJT|0a2d;6GhGcU}7 z410PRH?oO2LU0HL6y!XRb}Id+2wHi6z7_F9y6TGh795Fl+;M?s&z?Q$t#5rOU13#z z1wqmIT^3m3O%xCw>oEvvg(jWtEs{=w z#_a>)wVpWr4!B=>0r(2ejkW-akw76VRCFTJKErSah-x`M7H9>UB7Mrd;u)0|w3^zEQ`VUYvlyJXsQ&-CtK; z6@J@8$j!oJ(3$v5U%9Iq3oM_ppm(s3c3(-q@=rdRo;dQy>5c=V>6iZMN7B7_?o2Pd z@N)XZ$Nnfi@#ItK!G|6Wet6`q5Ar_1BF6c?aOr<4AG&bl)`n7Jg^ssC{Zs(z>3$lI z>e5<1&YY)fi|sy&MOmBLvOQK}-6RPr&uu z_Oh5~;s}>W5-mSPUeg#74!_MBikuuK4q;IjMMyVuDx_BM#DUDVsqK{=8IqWPPbE+R zt|dd}`>JSV4AF=N%VFL|H7t)v`O`cQ4dEV{h;X+n@E>)PmMS2~4OyaQIlUqBm2m8* zkq2C*A@!;tkc;t>IE85IpXo#>i?_@4l{Ut7)VY)g98Vx|@FZO~ym<|U)6^oS`W^U2 zKv^?@bInKJet&udr-Skr&@x_87jRHf5(v;*7P^EC1}b<%fJU?v@|-29xR~MS$U%cQ5ft^IefSFAU^z@ot<=dDgMh|I&aJupo)dz2%S#}nfqf<4DX_;OQ0 z5Q8J&Ls60YXN3)@1X?+t_!Z{Q_vM>-VKfdVwvKfRkKdN^GS}S@6v=WM@huWQl&fmD^7v|gqfgc=Dv)@#ta@RafL>2t zzprIAxEk7`F4d?PDPm%@s@MiHg84f zOxxm;3juzH42H)JdGHs=Xs^Y3~D%rpsUcdYZX- zE)6+xwmzA7@l$YF{o9HuvGvNA$oTcEdYfA|PmO5GiT6Jf-#j<4>{YOMY+fa2GsIQB z!V9)*ctWSG6lJ3>5u1T3==S$xs$V&$bG2S2fM?w2Gw&y3wcl0L*p`7MrpKKztwPXU zj=a{yMUpUIhxU^bQ^6mx!Y%!Re{y{-HTsV@(gv;qmMdf3e6r$_-aY(-9>a#!kbCQ| zayGdR`Sh4?KXlbyfgV{o=6ZkpvCjk$78TR>?L#=$o5$n#k@Qy1xt~Yab>+C1`nf78 zJwj1Q8MZ^1A`>=?(sCKah872U^;dY;qraDVLZGv0;2VXnN%#DN&ps{pwNE?hqt9i@4}(m_mF;ThHS(@79Z#{j`>?U%=+Y~AY$GV($wMY2HZ zd&@z9*5QwFi}A~OX(x3GffbmLC*X^lcYa3*3J_O?6)=70sU!)9ebSk9)jxP-;h399 z6I+qwV^Yc2_FWYT_7^b;nS;*aII5z>G14}+Q9_Xb=uizrm2;RplL1C^23!>e%0^K| zqs_;I*lAKPe&Q5xr5AT9+q{t;!izDUG!aL1jM>yL`Xhq6;bB1$L{dTHqG=YY13)`; z!D?Il?6*3={MaWxnRbr;a5}hcYoHto8EEM?X??ILQ_5k|Bwv}HZtd1FsF!aVQ)Lew z;@cLh_i$)zwJuf#IrW?SyHM$tYH4T58X?&d_EH?M(ugMDg10yn_Kkfk)GM@hz*Hlf zFCNyrDA;myMd}GeC}MJ8?Y5rkX6|D^&xKW>c@QnbHbAcxKDDgUZYp_e=JlTfpIVfI z)rLql6U#1vOEU-{o9gFgkgC!GNni~C4af$r11}P<4XzS-wc@Q-5-{`K*zY4_H_)Wym@>!a}( zD_6`>oRj1+o5?EzbT^aCIVPZsv^SzEFb3ITNFG;}=xml@kqvsTqF@6Z5}MXadgQNo z5K&dPp6-vnEOrB?H9p#&_DzN%7B(9vV;*A(2P+c%#pU2^$eB3*v zS9o*Lr-7S=9|f!~1oS@4XE`Sx8f+cG7Xho&u0|g^c!;)N;SBl9P5bQB?pPZad1FZb#MV$({_^}RowwHf%JxjgfSG&QwXK7f#aE-u>VFNxeV#w)EH| zk1!67ru_#Gb7neoX*6PUC@NNZwSIL^G-cDj#9lSoGIQPW!p#kD!Q^fN&m8a%>e#nw5m~Pz`!~KC33b(sQSP4_Mh~=heKYosYtIgNR^RZ zJVrU*s6^1xhEx$@>0wPnMYOmQzWra>%5mH}`p$RW9ehGuH|L1TV(bmyRe&`Gi z;R}F5RPYa=0Qxt7@`ZHz#PReOfBL7=u94xil`R;9EMp=hjjccjZK;AyC6)Mj z--A_0JAM(|0-}n-y14M$jUSL6+D{5}!z;GA3O7_-nGd*ovtG9(*heRUGQl&v6&*}` zSZ44G!5+R02BdLe#k9bneTf0QZ||XW*TZj5gLmDJ?HYqWULV`p!=?ipo6k$LdNois zi_8`b$5;Hyp?rK1JCu~myrH-yBF2S?Crv~M2Z3G&jy?NZIWEsLM@Q3!}za+z=NtyAY}rT%a3eDXcmB%PXDv zh&(Mj+odIr(&UrEmw^*-6zUaiovEKf%L2X?H198F`|bml zRxSqVOTw{$8et8}v2~1ndiuV^-eKDygdWmA@x+rM(9hs3PJu65E5JA4K1Vw$wCIFw z37V`ZJTVVdxN-mc0`-zMT^u)P)%}Y87H#X;o9UE~B~;j?P01haEP==q7B%uN<+&nk zd+QfN;dFj>CO(B{H0#gGTH9WMlY;0M!9$iU@xezS7u^OH8|~@-Jv-9x|IsJYhd%IR zdi3Zh=dy1LIrN(xS$FQ@=`=AjmX@~+awMXQX5xf}7k#TA*#W2RX^N8!X7B(%gBQI? zEh`i{DRw7Tw|%t73_|~wVfq_&wQZCDw5YJ|3YiW=iha@UfX|8m`YSN>r7$y{`A?e0 zqA*VOIuRJ%vmG4(I4U>vtDsP;4+P6{eu*th(9nV<`5gPj6?XgCJKjkFnuLcUq2f7+ z8%`0GF~w7J@)#=#@5U;~Ybk_KFy_~BGYBc4Ogn?Q)y3!_ZSmMmlXxXsU%^XLn{aUwn2y4bdBQ?w{Y@B&=T5pK;P{2j=o5F zDw?E`mM-z`;@MVjLpjw)ef7sMi*>WdjZeVa`qpUgT;T+QZQwo3(Rf%}kjJeRY&yaE zr6(QPdo-Q8G?D(>fAHJkN&m>9J!y0sX-U_m;)?cIUSdlR_fs5w*9&bIV6HjZz1OEi0=ZYaQys7ekwh9*C8;&;iX$OXg682T!o)~_P&fU-k0Z+_WSMkmIV8j z%0_1*#15^{TMa%o9<7>Y>HO0WtnZHd(jD)3ZyMNtnDGDy7;U^P`Sm40SAjV)AcyN1 zvK^>ujgiZgk%)-2Ie|$c%mkDZnfUR}Z{zKP?(GVNq5*bVj*VEv9CZJ^BLsA$S&q}t z`)kR`4Hp_J>Z8|J@eK2O2M{`PyliqIIq4hny@o&yEE*(gguGEVc9zv;m(E1EakXmX zPDen=!>!RdybdQq>jA6oTLDXt)~giI8v4dQNh^8lRpQoKM!!aZ zmKqpw<8NTWSN!r_p4TgWZNE03V{NIUG+i%efxmv-_j+j1M4_lgr;KwJhMaV{&(e2> z!p|V9zW3aFZ+hvamw3;(8i|z}6CdXMF+s~z=3Ab0ir7Ll3W?_^brsjjUcyVZJibhL zc<5#xq1eh3a||ZjtWb4gLL9}|5Cw;TQLCqDh*CzYY9kYsG^PJk2_nDmPG|A{^95|d zgK{-&2{gmZE0I3uy5{UTPeAm`Id44VY^D)jjKM}!d8L&{g=rwH(B!iw$}0$A*Vse9 zd-t9YC}t1_E#7ySg7cYkXG56MN<)FcHO(j%xUpD*qGw)nY83_u;h{tbnpr>RS_)|y z!CbBjEVLP6mQ(QawjP#AqcwqB0Cd=h={or8)bHZOO9&f7WL5ad76)5g4F|@>ix)A6 zM}SBA+BUL1J@(jR>Efj;>DZ~WaqO`RKnhIOBkDsvJi<|)(rmn=Lr>_`5&X1T=)s3T ztS}<%=z~C^YY6jp>2m7qS@<5aejJMCIVFNDTLKmkOg-y-Nre+|pa48beHE^tNf$!C ztF8JrkOuDM@1UQRIv0g%2=NMi;HyBZbF;i(Jo8ZWIq)u*{1o(#FrEM@emfil`>979fpGj|fXVRzt>`&9l z3s+gWA4f3DTNIp@N2{XD=w#e%N1#1_>SEfyZ4`%U+tYzV`)Id860NXb|3%Joznb

|aKqk)u zhh@TlD8o8X@T_neR~+pbe68dI#wrUG!2P4{w&e;(Y<4iNOiZEpAkUHgBWd@Zdty6> z%8aX6nM~t!a(Y&m;wZ2vPrPkEl|jCP{KQJVtpu;j)B2`V_+I7=`fVsjIvMY}m!@&p zIFe>L8RGZ8@Xa)e_08eko?$->@%pGU+aajCw2W;X$V9^KVHJJ}WyUoAHFWYgqn`~F zV?$eq@(E>>HGwexwO5Yee_}B02d2m9bt!wnllqF7r~h?!Z^7RJybdj&`^IG0!E zrS9E#a-<>5%}X;hYBC^$g=bP{P>v)4%@)a@9FgPwuA)moek6Z2LC8H>cz!YvU%B2f z?uaHA8cE94=>qJ@PyoZC35o=!B&&m(H`Xc6DCMct+ZRF>J|d9`U-zp){tZiZn2-Xi zam=APcEilKHNq0tUSL*)oE8+T)bW$=TcR6))(>q&b5q)@9`?O|pXpNC*LGUlh8xs^ zOdHXDo@;#t5Yxq1o~qA9yOpr$D!=L)-@ut2^?6qpOaWFji13LOFZL)6^ zl{9(0%DCpbDQMcJ`a)^s12-M~$#)&JUF3?nyL7iN2^zt2b~1gPQwZh|+7m+VTeh>` zo|WZa`qf`gf9!M`Ag}Z2kuKRo&99G%n^w*Go!SJtE-B+9FNI&2a1cu>4|jr z!5!(zC*O%se*iw2!~$fDBMT?eorg!$@BpjwRL!k0n(@!iBYPkOGr7-f4Q~aXSU>u! z0<+4N&i2LhtN-~&(!m3qgn;6qjXnF*tXS{aJCp{#-IiWt>p&O6Y&g|K7@wTNI)e7o zks@RRwiYH@>*!BRff>aPtLbmO|88Uj_F#}_>5&KDp85xon;2)b3hCLoHH}XWq+{@97nU>g zj8!w%UFDeVV|%0gq0%BN2k{GkQtlMTPxg1Wp=drt-3L-1NLsIPwu>Fchs3+z@s{-E zuY5Iq>bdWxU88K1VXO3D_bBzkaUnh<9Spp{E4&=dy4j9$sfxGIGQOlK?*6%FNRD)CG$vJ|-BYAnjlA3=9 zTwho{SPak=D25K@=AM|83D9ol<$#}^Jo!>l8R4YF&M2C1)MfdZNH@U1WI>Ny8&hYz zUti>#r8n`-7_5y6elnR+v_q+CV=n)OZHO|jX5vGE3dw-fZHQ`2B1J`EwtGR1}X|1nisoPuZ}+J)#+w&7pEv)v~R~%!HGUmRm*!XyV`oim~6f9$h7J!`eGz5<6{O|tg)g# zYsk4KU=`Hw&Br{f$~PH5+gpb})<%KdiTw)p>D^B~oqpg$KbBs2 z{)H?^lD_a?;dkNro`Hfu%CsqI@^e+-CdiWWm4u~D%5(mWG!zrrZP}VMKLtt! z2Oi4pnzTkV`YThuz{I_2j^1qd|UtJJDCD`~j_eR^=gJu3Ta@iSXXi*$@;a6oqfD-QIU22pRcQBxUpjvo zfeG{4(d`HwOPCbTBEXIzg*jKmOrAr{U4a}N)>OAQz5fT_$Ey8YI)3csbo$IG1PTTG znGnuH*hDzbxH^w()~(RU-=KxHt1524RH@+6b|VP(`wtulq3PPS%ix5mJbS3!6W`^& zTsrotQ>W5rKKl%5u3}*`mrk5KMZKkitDw#aX=&QESe^uJ5JKFJ5Q-EPM%9&hKDUzs zvHSa7wLg6LFhU>mVdkBB%-51297=+>?bN{>nx$bfvXZHB4}l@r^V`neRbh1@l$lnO zbCm|23QAR*8g8A-SR`!eA%0YVb|nE^oZH(nor4=zwLSON)75?p2_*p4l6#Bt3m^oT zCx1MzTyyCo2e+qR`PsjmMz{8*6W{%II(Pb9`s`=Eo_bi>{_YFUhd}&}w>`oN`Nj0L z@0>|f69~Hqb_#i#@Y5*lubxVKcMK!cKNYL=*Dk$8U1rndwM!vL4h;^cj%{t}%GC)L zl{xWXCimT_GwtmPb5=Hqopqr7z;$|ID*fzV`tfw{J%`f7*r{~o5<(z?=`2EPYU@pR z9@!3k=hIc30L&mn4`V{!j_`ir%2XQMg8vNYru7FLMLk@lpGns^!te2i?`36qANaGH zybEg!%IQ`}XGL2JjJd`3bk`lb)0S6Gr)R$OEmo*^!2gUQ;3a;6BlzifZ*FcJI$lj5 zc>2Ng_(N|=*Djn*GgFsB*`*+l<|OsAWntHrZmf(o??=%x0}PHuluxa3?gJ21MgYDm z^ONIaX$Nic*hBYg2%nZ_a0-qkL4Qww+P=3xT|M_aN5vgUKlS53i1KYI{kvzr!7+@x z(=y)W^-UqJDr)7SE_oa}%uHP4ILw~(Fn-hajIyN}D-Ch#>2n*9M_DeUJ-d&jhwuN% zH1dakkUswTucQ&OcBmACU$f&rWiQ_aI!?!VDW{MvqU?M69gn2Dj_k(A!nJhoUHj;t z9gH8GJhBa^j+~_N!2OS;=f3>a^x0>=mbS2JKhJgz1^PI3g)vO?{f;hpl=gH}%>N&* zTNdmkl7owCCk16*+hKm_O86qeyJr^;?O{*-V^5{IZM)J8rbT@;-4a?O8?Vb3ULG@O z0MMcHIJrHT{zG6bO}$*f+#D|!nC8qy70~6^ z@Rs`qKE`ZtnE^xsmwM(6k{fJ4s@kts$gn za;sqLWW{m=9(fD@H(?iqtVp@{H&TcSmy@{?7Xbk;-<5A^XB`Wi@|&|dSr0y_a4}cG zr9f!;HM>^<1Ki95XAgI!AWX4Pbh+p!i}E*0ga4TaEg2pTKke|TB}!!Tzgxm zOvF||vmby86k!TVM#a%d)#}a?6N3fNQl`&&xd)&o`Ya_OXDI+_=_kfm`9=MK6Qf4; zNWD66>NJnwlf#WKmm&GhoGV+^t>ULfstRYHZ3p*?OF!>jlnAfU3YUZlM~G2BkPTtX zg;~O4Zbse2wp@jG4a<1tIIT_M{a|Q?u;tlK&VQ`A?YDs4ZyT$M?jKjM_d0X>Oq{`1zL^=j@-RB9?nzI*_eaydefx;hY}$F?9B0pug&^(< zt*gEE@q$M<5JMo>WLtVkXHA&382I`(zK*B;?dj}U%#5#GNe@5#2>IIC0&qD5{Y7|Y z4zuzu&)g>5mX+@IaO7<2FOIYu57Ca&L*BFQ!5>!N#*-HGE7FG&BKXJs%9whqFmNm& zeF*8?12y7=E&pg*?iFQ-11qq?igfa|+6GCDa)t&X9ZC=8^^3Dp9LvY{BlgVScXUg7 z=;#xX=Vw0rBk6M={{v1XxR8dskr{yZ;Jx>yhweFnEC6g^ff_ig=$Q=XXQL=#Ca#`C zv4J`N*!gsI>>P18C}hRH8+l?YTP22BJ?_;}B{U%<(QxkzQ*0!aKoP_XU zocQhDJIIRfSAcycoj>zRn7S_@6i!Vqq}}@tr@edk1!}_q?>h9f=w(QxPj^1@R zoxgB7ow-0AdWLN!U_w8dFdTi;+6zmV-ealo#1n5z!yP!2JU7Lv^hNv)pu9jKs-wyQ z>fN!mH+5kJ&^7Crz-m5CF^9ZT#>|; zBWY!JjO`PX;E&0FAJ#Fz+;?~zZGJu-d*Kwq{bBqNjHhpL8bT+>gN7s7pr&w9*inb2 zCC84r^p>|AL;*KKyK!0tbbjUKucmDrm$`fQUMz05Vb!xOec{<}roDTH(*1YuNM|li zQ5R2F;B*NX$zgFBx^}d)jheoA!+CVz@%{gGTLgQ>`4H}D5MO%k<4H@LL)t%_diG#$ z^!Vc`?bwOe%R$(S&c;Bau}yfqhwzTa4ipYRaXCgsNPcv9DwpZXRll!?trt$gQBFzc zuY-R!ndHG9Wun@54A3zixX0e}OW8Zci^>;842IT*!j^oA#Fb0V!yfkq5u>a7c;Q5a z321~{NCn~sKP6eC$Qz_Lx}>$(H|%o6cE-2rT7y%mV5Ey_3U@is?=l5h1twzFhUFaf za52cQuX?EWIi?x9Hg7ZT_S^+E){>;EZoPb8m;{%GY%)$05#r3zyy}3>Y)lPil{k3S zq^+5oU~cBF27XPpb>mtKj_TDIqSUuFRfZh&@V3Csnb#B>0VT~kl?Kq)c88R##+bc{Wc{jvICcv(>@0zvsLJeBJgKv$K>V_b!E}$=Ya}T#Lc8#)kh+0&L0?Xi}*kmK4d8E;%^*@H^)rl9mWX3&(c5F?Q-+1ha{R&jaXdX<URo}I1H>;it z=^CcP(Jw@mVkKSh2KQdMzZoM*^E@&XAND&EPNG0_1wQIY<)!Htzw`xGfd>%ac7@}* z^WZ936tKG3BRw#%6&x__-HL!hy~Dg2+PeUyqd?D)9~s$-kdmF(xfMa2+{4_X>Gdot zq$pEV+J#^b-Fpx+$FSfyefkuZ2&Y-)#cF};ASUJ>$ERW;_F=Q%9CC7mBHI)o_?(=> zJ*u2&j&K$j&6XF`babc3al>sJFS%4&w6h}WmWP;^)9-SB15w)CPqy~p*7is6l?Gaw zWaoF4BR$Nt(o-}YGA zzh_U{H`-``O)^JY{XnBO6@W6z&Vf7ZX_Q~-DtU14cfKp_JFq|Pz)Sm?vy*8WOON(W zd@?X}sU)%XJy>{{e*pXy)@LU#V|j2HVYUs0!Nqj!mFM9DtO;m)`@@kt?uY+J(w6N9 z(mNh`Absu&-$-MV@|WJ@wWeT{gSI3`Y1Wnw?%Bab zcA+G=8-couz5njY7(kF7pF&{g2+8nk;tF_tgu6&Tno1AdcK}Q2*)(zOYU*pBO($MC zhZ5~LO0{$88m8_C_p?3Zkw_0`da5@UY)8hksG?l`nFwJlP{`~(&Y5E_dO1ikCm+d~2X=Vuv1e8Sjud%ISkG0#bQ6QEv!@eQ!Hm^M1D#zxyRng6a-xqgK z^VTm{=l$ylDr!dJU_lSvu_x_+;_=jb01$wwh@lOIY%U@w^;>qbw(LJpf%Fw8^6_jxpJQs7WA#yGLVnNXiQp)B0~Im zF$MaR<#0+yP!+ElqX4&wy=m$g8PgI_kF4D{A=Cn|dn;ZUx9cW*Z6iTD+PG22Twhz> zE7u%aIih(%&k|>>FOggi!<(1+;<+B!h+dDLwv+Hov~H$G?ioNI$O?XVk>hP&+gjr{4=yTliRFzi>SquKgAptHpKf`Oukz2CXJ0sTOnt0p3 z;z7bd>fr;`J(tA zg0?LH8h8r6TtRCdn!H_N4BPlxQ{=`;*NqW&)I9)Y8XJ~rZkCNpZ0mu;%d z&9YnbzPhK?oCNm4OhVhZ9-Au**o_L`I7fqjOFhf@1rR4`@vhb<)aX{~5O8v%XM6~VLMj?HvJhAbk9TGz z*b^Vt0Y>w#)EjvS$lT}h^Tb}0ZgFrWm)pEzg;QN-611x#ZgmBsji+XKK`WBkvm8Z4 zD32-LM}Lz>4Ln84Pb7<+PAnDb73kfPx6IO4SPwuCy;OHaIEf;Qf&!UEhmYqes}SiR zt*e+Jcp;>Nv|e64@3hTdQNI3Cty9Tv5nj>VzRhawiSFbhTq1BAG`LfOrVS}(1U2L zu_BGYU_ISmKQ%QOelEnX3t?N6`vvx4t8{qRQ}0Z7+;Io1e*3}{TOr&d>#mK>VnVF5 zt}U^ZW?E-uuN-5g^&+dK1ECDC%s%I~;Ov~yejS!M2vJ*6T+Fh4z@xsx(g6WhM|Wq> zo?-R2FIMu!L(2eHpH&_>=hOk%k^()nU-Ecp%(rJ?mPM3ZD+;Jwp|pVDF+Vjx-h|FJ zLh!$|0~h<7Jmxr`txq5@X^nIB*7nuMMOFsD!?dr;2!)~$g1Ptj>V+9sOtDziY6Ins z+XfWyWghoktK@L&gjNq8E!Nf5pZ4rIoW}8H|I2^#|4fIT_;UKdqxYr{zVm@}H>T(Z z4(!0O9`&HX`*BjZh{=7=kgcoJLCS$HTR2Ii5AW&%KHX(otuR22`OlI@pb)$E)nkAH<}a ztq=5(!QLU9z#+3BkgvGXk0ZHnf9)&eTSx~FA5Ehp?7Q#2m?nU!<*rIKck9UW)Izlj z0{3~0$njWDy?Sv5If7%x^K2_wVe5drI*DT7bD#SJ_${QvM{u^s*sya;Uu+HOpd+hP z@pAMMhe0e@_KfaES-|Qu0`xfE`#ZYeeQ>moy2t$t%As=?&!)$peku(hG*80QZZ**N zLHL0HR~1F=(8K;TfRBTIXnXe5D_BnBX8?Hv?Pq}00R>+a7aAqRbKLDY)-x%n3`AfCDaUCd$$?lw?bVDqcx;7bZ9^s zd~~+qK&DClJTHv!-U{P%!6>E;`~@LXR7J&4z1Y?wRz2Me6IosqwF<`C$4r^c&}VJl z+ZqB2u@ck(+Qdu}Wm@rFL)F_t%TiyvT>UaW53aS0^#mK-7kJI+R=CaZH|B0NewhyR zh8Ub~uCCS~@&`dn-gu~0j^~)f)q-yFHuqKG=DVs@n=Q5mJ~Xd~*#u;_FWINc)x68` zktgCyjOCe;c*DH~Zsv;u#Ykc2=g3LgM!p;z-?{JC5|=nZ7XT$Jeu3hos##O+tpk%M zXR73>XR9!2f#5@}%B^t~&aHtr_Y@#%NaUJJg`mWyfJNWid~!+9yz2MO(3`)r{Pkd! zcCR8^k{Gv9zJkGx;!C>KzbyqBSpv$hVFJ%r@U|0d6_iSTe#IrKT;7GX_hXejZ)vmlDHyV%h-owHsN_?ql_vHd zK1{IW)dExnUXG3ef{yY2C5`nc8<#=C(CJ+;fEA zVi#AH*7`~xKa>m#dB1&l{fAavOPp|oP~jHEPF5dPjJRiBL2>WC1L=2u>tClk?>?ID zx$mCzC!hF4`mqoHR2skm))Z+-grGt}(tu(uSpm$IbA?6~U>*Y({*Ay)!Q1`K{#tL_ zJPW4e*uSyL znn9j$554Vj_UuKJ9eZeJeHg%dz*(T3VFh{xb*4Hb&&1)zy}})=(95gVFL;%3+c)Y< z`rNkUqYi~9<2{9JqvAvJc@+{KjTY(x`<7{=Dhfd0CqO!q^Y=yCR$o{O-I}+@%02Y< z7&!Swv8WB7TG_cFJfY75%)0j;I2d&L{FlF(p8fovrF}bk(uaTa{pr2$es|hF+K0lT zpZfNuDFk@1iZWd3RWH-UR+bB#956X?H4U*U-iyOG;d;V|${O({)*;|3doJ?T0|CY-r!nd}V`va7A)F|BVu#M>+L?!_?AVD%dhI^6$dHeh z<~!K>F$69H(1>U1(~Y9)D$Wdb__}-FogvsCK72TJU8DnBXHCL%%Hu;6o5-DHJ#NJ@jBYfB9jXSXNW~9N}KHCNGaWFhEjFUh31;vfLHaxO3{rQjlboy6GoP4#5-U7+RM2tDKk%wt(P1LHvB5EHcYT4!V+4UaZQq1Kr8$T-C+7!qT6@7 zy5c;qhikNbRcbLGY(YY_tIk+(UK8IEu=$7l;#-aA=JUU{DWOa?iES;XHC&oX!|Pwx zk(5!@jnZxuetpO-v4Dt4MI*4l+=#};m$>?U13-oc;u-alrk1A!Rav5ZCy9o)T;^#8 z#@#B0st@|ow3N~UX44P3U7UCcD8p*p)KO_bT!l^}{I$5Ttol3dwJ78DhS_Z0)g=?N zab!;1NK*Ba8>O!madUh^>VRG4x`}dXMc&%&%^@84ie~h}z;`v$tDo1RXTMZfRv2@Y zGw-XXk0HdYutMqH%GlzjP|D;KiIwu~gU&8;Uv%|8g#HN0Wn{cENkefgQxj;oxtf>} z9t@wMDjG$vY|x?_V|cH3f~Ues97SlJDytKIuSUO#yv-7FB;U1;tRUrFK|!85JD*Tx z1ZK-fYk37Jm!b1LC)QJ}V9!B=1q8;cIP8syY5)L007*naREe5mrFw-4t>(7fJ9n^e zAEAo5mJa!rv?>7REPLH2G5zgerK_9rMsQrG@qRz>^a9?-ul}~6a?r)S$SzvMI2ZL0 z`%;%ow@i^7R+89`QXzg3`rJRRRMUw7Gl2QL^|cPRvw2))--5aN!;e3b{@us^Fr8y1 zaFV^cr_P)TJ(14!CMNajj)FteS@LKx;VSLcfxZw@77;iU^qqq_M!O}_)#KQ&?usPy zvBFoGYckFuU^1ESCXKwHP&Mxv<5)OoPTz}w7+Vj3dGgrFSou{@GM|lZU4%449Te<$ zVP)XHc~@TDLZh(Uj^L<(uFz;Z=Pf4CoN{MTB#cj9!vp?3L9erz5T8R>lFqJ13%`R! zFAF(;X)N_`-HR~R%hAwSBhXUvjEbH7kyipOyGGnQFZEI}AUiAMy8J0zc~GT_j@i5- zEdZ=fen&>JRx|REJcOUDjHYyy61L;w>>Li#y4c6QH53)LgY#hPYJcwHqu_6N@xdUT z(%9cll@AEWu5u3!VXBP-v@y@4js({$?p0wGuU1O55P&_kRqa1aH;xZd6o0(b1#&g$_*njdE@fiCim zG*IZYEyc$(+t1U8wZyVH>)M^Lh0;@^u!ODDmlMC&9=+lchyQ99;p7d@_$-FrQUMpBSbVDO6p<_dp81@A%p7zjI zYK`Pc{d2fqKj!>0v^d(J{G+c3=a&2SA5P0N96QMhzm`XyP_m2d7BeU+uAyw}?i+yj zJJaFAN63Q$j$`k7*zS$44ti{-&D{zETv-$x<^AX*QQD2aO#l6Q-4?;##)!cpUK(Ag z7Y*9px4wm!&`!)N)GE@j^hsN6g?om-Dt*qk9swPQH-8lf=85LJPS!fyl5bV=MtyR) zgMv?tp%y{Ht?r>RIr0 zqExu9$xE6jKcmx#j;yu(_IWSyU3;w?xHj23A<`zpt`)XUx;G|>)^(s?gIY5@4_DX6 zu94lFS5KUm={Zd~!g3sKySleZQXv<*ZujVoH` z_VJ-sh3ZAt3gC5q$|$|gh2DnZZnj-0a{V!5BV0Dqqndex@0yR6*7DSR*eJZ2BHz6} z4YOHn#L4kFu!>CFH6MsIaARoEmrTKp6Gnvs1%T+&g!2e|X>J$++!-dwY=)oVTcrEA z^>7>)Kasq8Ebt=;9tEt22Kvtx;Wh69yw6PrgNh+hO&C+e|}-L!n7 zw2UCh^Xw!zrQi_-`;~>K@@Sga*2ml^R=im`^F$!U<1Cm_CjVA>j>+y66Zdh1sc8h4 z2?Uw8t)r>$z|qvnq*zD9)5Kq6)pwSaV~-4U4{<*$Y+E?8YRkSuVX`}qfPaN^uVlMpk;;wx*LmtcUQ-vvbF22ykVk*W(IR3K;MHX9cft z7zbR1);U&drLnNA)7EX{4&4w*GqxN(*YEErl+R@p2DNg z3XQ@P!@OOGd*;bgtk$o%twF(_PxiwApTLhxZeg`XHjs6T2I3*=Nu7hoO<@AbNLo;l z&w_ucW0;QEhYeEK$^d-Ls$%; zR}jXWb7bN}=>cr-=Me0);kBL+N=tXj>P-iC?N48S@k09D-}oQX5B-&Q;ZtEC-FE=r z1(;@cyDG23!1M@(y_DTg*_SV#C!Dj-5r+GrVFxR^!aZ~5YRwl`T;rK=aKAQ|{Ws)xOljN5martb>&`oImbf?gx1H7J1%%-) z4}j-m-Q*j`7)S}fv;UlZ?OSPc%bKLkS5Qc}?PFvMc)Ai#9!QiPdiddV=`u$@PDywA zVKqM4PPSXL4{bD0V*A%3TwDs|?E5!~8Yy;-JQ~rB8*Q0yf_I8D|Ed|1jqC(!kaCt2qAK&dC7`TONf%MTt#qPbL@A=;!FtO_{j`tP5;}V930}||fGuaxLK?`bsDe;xUEsLFBlMvz zd`oZ=g<~_cf(4^pY?+_|{ZgM8!zfugyXp5AUqQIK(%V7~9R3+ratepGIjaf4#s^w;eX?5obAHbf@s#%W&fL7YsmpF?rDi$Tc& zKa0P)V@cT6d{tX}G#HX=+%R9<42Bb&i(j zl6>`VP=r8%^PgAg95Xh11yY+$oGVYskGx zatCUGA1Mh}u#fYXnVc!ySzZ>Tpc?ar4Axb7`UbG#beaI0Y1$NqGx!k93tAQ(_z>W` zn;*CQIr$Wrqmq}9%o0MaG>c#-sib96DiUSIQ#{16Rs_j~V5TNK@5Mbr0yy&o=R%~4 z3jtVcG?OJb1Z&&YG8dWn#u@HR;HMA_##t>KLvUF^kRLvJPwL&aBaI^reC@=U^xfm9 z(*?{~FJgA8M53V5he_)k9;scayYJ{7tm^f!y0$9~@7|fFE^>qzt8haI_(Ra5m&vVD z9@eR;gL9u;Kj~UQgSi2tEvSmxMvP=b<6e&{76eGZdoKpkn z0CevCzFV*U|L;aO2{6dwtRK+-t5@OHty{Okt-5t9moC?tB9jyQ0d^|~*+p~G-i)v_ z$hWjMz58?H?oF1mnox5r`^|4~$Ox9@x^&7ZpzdLWFL1+*(UsnV~C zyF$hwG*PfuX!aJRuxgLsFnEHq)a(X3VfRk}9+6awz+F)5&z*dC(^VnYfSf!ygK+(O zfoVNi$5UA}F`szAL%&w9>tivZ7h!12wk_#b&if^dl`TjQJa8vF#q8cAEGc|R)VOL6 zoB$ZY`!E)`XCUZ^g9i3|JVWh5g=f@z*)5*V{8(zaGu(y{giU>DrfE0Na90a2;638; z3=eb%Z`n3Tg;10q>ZB@z@WtD3$Cw&VRxz``;n11D{3lSnfDs%^!@-FPIy=$)Yegk} zkfRV@`Pao=;c8e|OP1U8YJoJd3$1}ZcU%WqcpBjDbr;7phAE#%8$#V&p>fD>)YN;h zT`+U@g0%5{Gt;hp$J37P18L#RrSOuAJHVr^ZE4>9?rjO)IB@MX*QUoFeIR||>t9Z{ z-E=(yKUVTFzIe&S8@Tf9f-uOqbjkAc!nS>Jc3zDet=Fs89y`%2(qwHC@4Cl&Jd0k- z&R(9L-~43Sx#iiknjQZZ&V+Z-X8PfekACcfL7TgNaDVFWK1n$|27qk_-txBn%rrDE zbX!NA$K0{*ORH9`O^-jaH@&d=>2&Tov^D626ry+T+?qc9^S{E)3`;Q1w~58MUh2LV z0>VG!UK9^6FPtpjM;i+0Gev*)G-%h#u8o_Hwj-u4`t39AC$AoYFt$U)AoUrL)_ zl(z0U5cMLzYq!9~wgJy_Ku^>+$U}Umrylwj4Gb=w&k=^sJ!#YCXVQx0E8tUh=viFc z#aZ^1tCpr4ZhT8R)OjLp-}@5%4t>rH78k+OM@BvuI_vL``^cn8%xt2cizj52;D6FXqUrlC$nI0 zB}Si3eZhkH@of_-@5;OWnlzvuO(~C8Iw1iH^a>12f4`@~Itu2-QT1wB}b&Qj)&RyFz+`7nOo@vZw;u9EdQyibWYiASw^ z2oDeyoa|qKn>gc9#cF`2zk~S8Az%SaQpG8G;A1Bjlh|4h*8uv*;4G8KT2@t&8_T0t zpd1bn=05}qUeIlLRVLvC&*(5j|5_Y*ZK9s1itDTP0H4HRkgfPNUceH7|JHG1T$32{mL5 z&k-EW!@>_pkHn!!M10ldW869S#?OoF5Zx=9#-%)m=wM%py!+1v# zM%qv-o{8$~fu57;@dqDGo3`yt-R#C4M;KBKeFoP&IVb5SpFV`iVFZ?*<#l|Vkwi|NWEJ>)$XoeUG+*$7h# zpwNPkHi1+Y zb6JBb#8=;Qm zu~4I>_|7A!SF<2<2!n+eT`-#d^}qhD^tPMck{*2E9)$g#bophMri(UgzyRFAbj%g7 zsVtU2EAKgvyntn$*k0_fwEduQ?`y+6(7hlQzOKIRZPfodZbLW{v^>dziFG;*PRdFOwk}3C1KY)tFmi|Og-b6w zi`BTH^oyVQ<@C~~XVM@1r+>?C_Og((F1`HnbnET6rykCopTwGfS6456D_7qk09(IV zD+eB?s+%~@BW+KjMd4ANZJgDA@4K%{H{bHs^auaff54Lce%kj;v=o-4U;WHy(sKHt zum8P5`r4Pji0uQ6 zRnk8VaQx=>TR)X7LAL_CE!D?1RWd?=6B3a_dLFd`|Ih; z&RW8f7w7Dk%%u-`n6|ttwXvYt%}oYB|EZr%H@@{P(7rP*=Q_>JEb5#*!D2!519>cg zsDP*5DZE-H@dV48uV1!>+-KXz`N+SzA~<~BTtBamU~ieF02NQa9D}!1p$o>_21Qs< zsgX>2)St$XAao=EEYV`6o67dAjf104EMOWK1Cos*!-~AZS%(;vH8wk97+#N)Q|DhR z*^V$qUc6Lc((-@E0FRun(rwgWr-{~fp zAYSm9wbhvOL^UyypYV$RM97q|+y;Zr1qFjhQeqVE*YpOMG(7ERB9zA^Hi{4@uN%uI z4>cytIE>|s3?-tCja(%(yyT|WxRRWbN0sbVyrNw)m}jJOo>Bkel~K=71KB|3v~vk| zs>&B7DrIeiD>S|vx{4b7oQ7Z01^p`ils4l*)DjiPD@G_0&*VK0=(x`_f%Hmo1N2y? zsU^u|EESTyjh`2Pa=qFA7WBfE0R~s)6vPum<)8f~`mIHpC~yM5dcG3`p6V5dkM}mu zS9r!n$-MRoX$&SmCu{yGpeYQxa~kJxncDUB@dNkDywNfqVz92rxuCbul>4Au{A@K4Aqjmk^$RPTYNBG0?Eg0K7`R5gPDgo{)i= z!hnXyxkOCcogVRIxb7Tk!MdO6aSyZZ6HGk2!F|bwjj0J$;QOC=Dn0SSi>U{}=L81H zh7ovXafO;wjY0mLlh|i8VNJUkfzwh9BFrpbcOjOnXQsO!x+fhux*}b3?pbNUnsZan z?(J?yh-E|KmSP=Ws39suc^;```1P^f%wWFa48$`TOa- zb5|nRp}LJ)u&VXq)2&r)(yd;zCWN>igm8ICZ2%XEqV7T34WIJFu0Dc92rn!uyoVja zbJwm#Fg%d9ZOK=K-FweHF~1XrYQ-9XlSdT(EVJb?O#kL)&g^1+ybS?Yb>qH%?n`GU zKJ%|e#N4GP5r2}(mgpQ+K5-Gmx$80nj^kM0_u2N+&UDu5WgMND#X`uGw2iyWr&G7* zE#w#lX%U@?roLpo{G1#fLq}x50RZ4 zZt{{-YlYP?jK~5~q=&xKIO?JLvswwEVFN(RAA)VQ!7k~9l_^TJ?Qtz6Cb%&~oG*&|P++u!qnv~u-1X&?3^=FFKDG}y*Y_EwGy^vUd$`6z<# zAjfH}DGgtGbH)flx;){PdB={PNY8BAoX%deI6eCGv*`o3ygR+;_V=bczjtR^&MgiL z7cNfQuws7zjf(z((bU=56^j)vvM6xdrv)t#%rx9N;5B$0^XOu?dn&~K{txa?|NPf} zIsMTe|7m*k!3V?O-Msk=<81%YP0vvu9-XEV!F9;ahqkAE3S7K%pP})^Cg|-kq1kAj z?B+_#x4r%CX~V_;D&6;kyV1&-lNQXG&%(n{`u4ZK3!P44II{z70@{RiFWbn0IAYO7 z{^!r@^E9}3_NqnLooG&%vxsrk)mL*{!BgoN3kY+t<+f_&S)ewJ;}i4H+}N02*m)R! zz{n%@>;fGm4frnZ*skn1b8f+nIgGrszKU&)r+Vd&H|Ou`C)iW|7*nNN)tBV;x{5H4 zYBhpo;=UZo>QU`&6zKh<1E=GO4&BV6(*rD>hKyhpP6)Y*SI@5oz3w%ED-Rqn8~OIq zsh2bLzC)mg6N6F4feU;$*5cK@UfyL3821FOkx^#Y{5?U|;1ei~15x6S z1N-VfCn~poKD_B-Ga|(gd}_5fCM~|>aLqv8fM4=;g|mi-t~WaG8hq-FiP5XdPrM;V zJ*`0Xd6}oyCX5%UUncV3T~KaI6_K1AfNGSkI07|1ptI3c_W#ZzOyMxQ9}#4s`*V8k%snei~=26*hP6+J#WGFN9}tnT;Xln4m)g1#vf2rXZMSp)w2j z?yhUS-ZS9?ESzlLzKtDntct^XGiS|YmwtM37yY@-&#}vkP|e+BTCn$#_wr*Is<|Cl z&FSdKs@*IUxTuf~rWwWk)=Z-ij$IgtQpmrCQBDMm9_|Krf#ZGeeS7Laz&Sx(H*u|4 zJNKDuMg9;%*^8*7H?;t(;+f1=3Qj;_3LJa~Ck1(lqrZZ;=iy@^M#S|uVbDiMeu4`L zaKR!LFNh$1#_&5FQIX7b-P(l?3QNL`v+B%$J>FpHq_2-E-Cn6imcdWLazQ3`bKytf zdNd&FCU~BmUIa}{vqc%q-&F;13vB|+Da8OJEW=fEpN7zU0!AUwlmY#q9`E=VYZzIpPbdcTu=U#dkA(!J32&2cimwrDM;YV1M=wk6~RC^Hc zs2Ut%>kSGZ%0f;{>S7mu4huTpz4y^{*AE^^x8D2?G}z~H{`)9GdS}|V|1dlM8XCmt zAHu2zoALVsNIwPxo3Viec~e@NvqePrEus->fe7P z?cNVucB~JfzTVZ{M>m01je@vGOL&JS5_~uc4b;~0g1M8_#Vl}sao67T>;KcgO8>(@ z{>8L-+1c10=wd;zCv9fYWDmk~n%a&AfJcTXY1Ef(AKszvz2>|byftE{p~fzE%A2{t z0=jG54bj5luMpU+J-NL}Z$`Gnl#v#h7k4ZC_dRXOG_jolffJ~61c*j${#zW4* zC2&HF$0vF9-xGi@jVfqbp^*nABj?6lGR%#xv6Q(1*2-8SzTR)}iuw%vCn!XfpR}y{ z2ow0f{{5{o`H+$!u@&)@;XSjdy4jdq7hmN39kfWm8Sh7J8{l|Nb|9&~bok`r6gY#O#sQRKg?{X#BgU@VA(>oSpco@S~>^csh0^H=Ty}NwX zqbs^9kX5jEp?ntiW*_A)XG^to<*Ky)va8dxKe!`(?pt@I58r-kTCw4(w14vxX&U#U zw@gO`mU&g2VMa)?eloh0*JAT0&T)LwomJ*t=A+=ou~{b2U_cyc?B7)Ih&qN;UU%2b zq}`pp*|X<>SxVbE8@y!6vdB}zVvDeleuQ(kn>N3YR;*Z&_CLLyEBv_5jGf{m1KycV z+1ZVKfn8H~WzE}s6b?OC@1$Kz{NfnLBrCdvVK0PF=W7~4JJQ*io_XeJ1f_vc$+tXO z5ErQ|=;EmOrf!5U*L!FNxERB(a+!-(ED^$}yVss0mk=QY5Z5#QS=h#20_B^&dKGHz z2$~4?s@-qAg#Sw_dWb%dhA7RHIUBaSOjD1ImQ;5l8RCA zkHs$hLpXOaI3#~?_U(p0iDF(Q;e#6jN)8A?UY-_ihHYGFYkfw^fun#Q{6KsKIj{N4 zyY=LcpF9$8(t78(I0i3BE9vRZE(<35d*^!8pBRLCxViHe|Je_=TxMKrXMh04NesnJ zf!U_P6GyvFgmKCB>(*f`Z)f_Q|N6Of<;Dx(g{f)Ro}*kV*NXjyK2*`s{y|hY!H#s3 zf;|foLmY7_8bAuXR92|fw?fmdo}sjQ^|@GxKbF3J$GvI8g`DX|J0VS(onCxtFTB^! z0>Ba4D+@*Zd0Yrdxe{(Qs!iX8{eVH_lLbpxu**J@jvv^SX12_ZTM_>JukT1p7IsJu z(xUyqVnsj4YIbpjpY{~;RfC!EYWAp&p{%PRI6Zgx|@wRurEv*2*gDmzPJ-8PehNEfWyteeCOnu{%Bc!Y=9w zdm9+#oWd1>E>_CcKKA*6zHOx8AvZ#5k#a~>hyJE}b3U(+U|$hHl1aQE20s#}BANBp zK&0$j4b8+l^|7;3^?n2+2wr`WckC7P9e7C(11F5G$O{6Goz}=$SmDW=coCuaHNJIE z{Nzr`u#BgZjc)GD)N-ngLlrIKI1#ULP6H?z#j@qp4FNTXWBmeOBiHaBA3pY5TKYt1 zoSl>Y8a42UG?Ql_%!oG;(vw1;AfRO7dmJoj=3`?jWz7vMymK9nNd$lzj7XIu{uq9P z9<{tD%FwdpPQuBeh~`?)Wt=F*Y5NJ{W%HgKQm#h;)cAg)xMol?F(chR<(5@C)0lR-D4f8(Bpq?zyWs8v!9j5b+iHxY<&5UbA$aAet#N$_gHrNKW^jsKn; z@&qLTwd`Bt=n7oe~GHxEaV`3_>i5@bJysL0ulskqx+|gbM z&x7MQ7?IS#sXXowX44c{for0>&-3s9mJ z{+Sfis}5+yp}2ip7@zXiUBY!&PZia1bTPa2T0GyeV`o~#)kVg4tnX*1tBtG1hM54y zz2H^||KmEO?4Xymgc*JjZv508{?uC}%TWxdzB7K&Ka`4Q>{fUP!3RIBf@hmOsO~ZW z&q6)<1JhXfjZ4@CemF90e5)r%a4|qvw8e;$=L3p}{YW0&7$?(^SRZ8{Zo&F{$J})9 zQ=8NMPj5-n=gdicsI&`VxS148c0&yofH^mCs@z^3HHCA(PGSd`mkgtZ>Q40_!qABR zZCqo8F!IOWyeoYg73O)1SEv4ioI_=jtze^yvIeum^5E?$N*!pyjWOx5ORo_RQ3e&xpWsZV`8tzNSdL2M{J z`Xs8!JGs&dBW?Y_aHqI`7rWOCsU7anBMA0zjg?v*VIdspK;wDVhy0|`JcW7Rs_`pa zG=rEs_D8XHE^jTEKc73f_hUV~BY3Zqolk}Mb~Gg*0XzJ8*WY3*yefqDVURGas3Wvl zhkcw8mNXQVyz@0*NO!?2ctpkI-S3Q-`Lc-^SHx+!&#UkD@7Waw!B(zX69SvU^R}&9 z*=gpQG4hxR{d!r*(ayk#ycyF9Yh0m>9ap3&1^e*kCy#?7O)bPAfm>X7qA#k|W#+wD z2q2!j)3suguh~Q4WJZ;-Bj#>*yPti`KiH|S#aQU%q5f8jH zTqjK(hlHiy2=n%^4#&7APX4p4hMx;-0Vm@#je4Aiy7?5&Q)^K1FuTd~7A#}oXar%G zg%C1#C))O}N_;bRB&NUv(@0kA{{(2iL!KVr4yyDh}oaf+k?M&*;E90BY`TG=f7rHU&lyCQpo<+0nI4)RMs2K+pvV_EEn)E1i3Z26s0x-ilL9i=}; z7b$1garj$}Cyejy-QSxI9@-iksrFS`m>*;jKn;fhHIk@<8A#`Y9QPP>K@jHg5RD5_ z9+w#&p??5}UarNP$+`L~F1`#+1lr*63^aeZCU6KV|L{S#nnElpy3iKd7cP`w*wMy6 z%EF0tuWG*wdCg5T=t~CEoG&WwV_;i!F;h>gB=_nXc2x(W6cJm}`TqLCHl z<8OH3Ff994emNv!<&H|mrt!m6-u*bLU{5EkpMO?NtVY7Tp3$+Fi*Lf>dXNBK5Xf&= zj-#V1c~z6IIzx$N!&4!c)3Ex*fT_BTtABR-U08q=S5qn)|N3fBj?ex_=g)lFd z76M8Ksc||_DWj>%6Lrv#SJanq@hkC5+%tX)x5^+ejc=jU9O2481$u=W2xL4dq0#;O ziGJ!d%{71K2n(SxRY1f;zY%`Bvm>B@E?aO=`)8P)!M!$)np1JQhJWdP1>EI#U z(}8WA26&C1G2Sv!bF5_N&wH2WqxGioGKCB$p`HhwiF=scKLsfl(A^czV_m&4j!{0P z{fFCc9sK%^KYl{csuDO=25gm%c=#)*C@{I(s;mRJr5_^Lw{s2Han9I|I(Y_!GmB`W z2s~c@XP%N%Sk8Ccs}~IyCiEcV9DC;mu_+gumfF z?@xnR&>KRKP_i9 zbEm+@Jgc#m-oo8oo$R{1W9#E_0>Hu-Uh~Jf{P2Za@KnH*_CrH1ZiqK(#yrwXzK4w9 zHOkd$N7Fsuzngl)I(}ce2dEEaWIXDy5ciDrZzc?L~!GRi$`&{%$y2N04&$j<}_ z_~w)6#3Tx&?AJk*ycL{zg>SHC1m`%=PKnF1MVZW9oHeL%_3u6(n5F6R0lV!A*2nvRht>6_X6#r%<6|tO%|c^hb{psY zEjoW%a35vCV(=(JEY{SU0W>vmYevO;fV~76IcqtBO|EF1KUNl=;!d8 zZruQH0DSvhpaMs4cbEm9_LIZJ89&WR)3Ea1W*aao9n{svmAIiPT0 z4`EfgNH8eB-~+3YpS=|Al|`6o?7|NY&SOz4A9b*9TmTbsr13Ev>{w z4Zv$S<*`v0d}KB7l|5ZxYN0--U~PXIHWrpGT$&zvRqesA$?U z8WP-+p|+4PGB1m_@baIy<_s!7KY7Bt`U##4B=ir@9O+H=`}zp>wo)F)#yXKEAWQ_x z5IV}ADIvFw+D?c@E2E4c)Q_M-B16KKM7O4S@%A6wh8q|#vi;RaT)B}?_45h54Bt*M zIxSUjqDAZPQ{MTj{N~QZ^yVq1`QJ(IscgY`jb9pcafRE}H&tuOfEGnCb3h9{f9p|y zOdm{aV0psX@Ll{TdK0Z4bK)|LNoM@`tEUKE) zh&s+WwmeaV<6@lAr}&KpSrOy(p~z!}ehyGR(#SzF1~A~)-K=8DjPaEBsVEri+$ow3 z4&9A-Mp(cY;|-tJVOGJlSF{DcswhroBKjEEh5K@{JV;k~l!P^ilRIovI||@WyYxB~A9rl>ZXF-SsXgwbup4E#eT5iQbO?O- zD9}yfmz2>JZ<6?BON}}*gapQmfvj@pEc0*1n~0}88B(NRr4dFgBs_EOIxo82MDYIj)O!BimXXIym$(G1MDKo6|+3y+LVcI#QS ztA?;qcEaMbqP%efd;4+RE+FWmkP-rr5^gkP`f+e#njdc?$C1DgI7|ZE$QWpmfm2>f z4$kp5K4JWMe%qa`K_=$XYLs2UF4TSp*v0B%l0J1Q>gi0#AAMqT8sS=}E+*Ce%%oxm zl|1|>-M})6Z!Xc10^6{taolcl%$muLG!tg@UFrK&nFS7K^iLvCwG#Fc>c2liW%b?b z&rJi;y^s65=_iHn1l;qt(YNF0F0(keJm^{45!7O{5kSCmLs$PyCiw^x?Pvys+A!e? zTp$Wt~5q24yI0Ju#uz6|o3p+#L z$#T2K?1ZBxg@)Ih*JV1mBR`$Veh515A`{2RUZdzZEdNM*d1>BU&RugBw*y?}bIX8t zUW;H`yQ=Vq&;&TnRe?k4_kRDk5n8pQ)Rp${J&;~}Zd>~Lx4swjzUq>7>6Uk0i%S1) zcJ|qIMVPz%vMaf+?1^;fz;+g>I+z2pvq+v={}$&ijzhTE05z~)PMuKCoyR-V4<6c_ zZhqHw*cMm>7N|oj*!7=Cy+;nGSsYDhpUJU|!<^w}=e2(jSnSw(JYgyVti>Euu%uk0 zmGB=LCh{NrTr@+dHF!dPa5tF1pbs^}!pSH+p*48vWPL|pg^))8>4Ag)aH!ma9qqA6 zi|a7>jPppld=F;YR(4Ot1z6V()Q|Q!QgxBni469*4TZ3==SiDiS z#IaD#0{JD*oy*hErk@?@F0Ni|nu74p0#noIJXE{En}wmQ5fTVTJ)XVdJPasmQ63%y z{n!9EZZy8!HoYm!TLWl@X^4KUiF#7#R;c#&1oL$9XW;^jGQz{+eiF4AjbF~-=7-?% zAU1La68&JjWcGxlsen1LWf{rq>5vEH|?7g{Cz5w!i~HM|Biv=O>O~ zb)N-7ciD&024ZOr7YiA{okE`U8cJ`0n^!nuT>_f}s>DMh1bC+;%1YiI(Za&f$ze5z zSO9aiz(0u#9clDw2K?r+ls0J6B3;l#ngXr^1N52XviYT5X$iM&*k|<&aI}Jjgk0tW z7#W?Kc5;UQ+~wB>AG$_5Ol3(P4WO4tu8eWUcEXd#GT!m^=Kgto1pA5x6A|Q8zv5Hg zjRb`9(eUkrw7_Wx?}XInCfh4@Db>l&4j5JOyb&?BnN z_ry=`Jo2FL;2m#|6Rjmam8a;o=4iB9p$6M;Ty7<3XjzRd)xIZ}iQLL9=s_7e_+ zCU|n$gl?bW;On0|1cEL2M&7|Jfej%A!@4Vc8nOy{MUHt;_pGpS+?jHMDVC9@4k}{j zAL#?IXczWjIx7lP^s=7|6-&NLdx&@eAh(GIfIsohI_{I8`ic=sx`s-qyb66XW0ZL1 zEnxrNsOMCCCeP_~3YpVYv(NZ7*@W`=|Rpdi#{Y@8b$kcLwjx0Mzd}nxgWsMblXom_H*{EJl zZv^}GNMk2o!B8l&{pLsbKINUi@^A424*ijn+o=c_3f}Ijc?b0Xz`cKYKa)&#H*mmedkY2cOeyGWR z<*&b<&O3i?y6J6Ku=9#QJ=C4LkM^cr+jgbj{m;LX-v9pF(yh0?Jw5lr^Xb8d9uGe8 zT=m9_FHUPQcKGBI&$3`}1gq!Xt<9B$?8vV?YdPx2)5G{!i}nBzCa%8fs`Q8d_rFhn z^x4m*MT^f4UPI1?o`|&UCO2d7YtC#0Db%x%_Y9`F923yg+!U`Zqhf{>Y*?sjMvEZo z+e+du_cxg<#G z1*o6AX-N4k2*@!g^ zkb+DB4q^pGqTfWshsP`nKftw*k#PC#@eDs*9dQ9eUb5{PkDn;Br9kqc%yLwoD^bzr z5OlT7F6gPHW1Sd#8d@2)DeeoTP0j=q;c6YA4bX?ijhalgCur_hapX58p*>W7LCac- zH;v7eQAyA98YiK}j=uL*oM2r|wctsxV@4rqV>^JAlc zyz;s})@h#L)WPOFVpu4hK|L_|B{O6lm&_Sm7JhXm5vZe!u4fgGl>o$56f z%D6~%;NcQ>v~!|`0O5OFobs6m>UwAyz=~kcvUCh$8D2on{gY)EEBmVox;WM$RXN}> z7IzJOVtk4T_)M;zaf0g;{n5DgkozhJe;`03zlAkEpA26*HRNu5W9Gof<8}Qpt48n* zS)Xw}zyV#J4Aeo}2~Z>IxonkRW55|^mb1zHc7{n`r|7Rls8>!SpVSKvzm-R?vdznGLW)~jXUf`j>H;aScv5K2Ciyv2)us!%)8x2(=y z23({>^KUlSH2vs>t?4+{w&!;&;hedX+YCGZ1_dJTJa@^?Npg#{(#HPLGtJS@(0_Vf zwiWt!Vxj)U1N+ih>sO~~2)8{wN5PKsxMVZLBzY=*YjhKQo3@FKk-%S}g8H&w>B5lz z^m)`JZfVtv5UAR$2K1zilkC`~!#x$1Y3KbT2rq}Z4(zI>E7Q3fE>2H9{X}~3kq6i@ zx0lB-AoIAMUQ~oJK1~1NCCOj;#GEu^~wEM4s-72gg+bDlXj}!4{+Z8 zD1PfX6Wxxb{XHRguUo%9{l>reO#1Bq^LuIY^H-*Yi#xcQt0OI2yd+(E)kWz){`UWp zzW3elq$i$yj75hYG$OQ;-iI~vgQ>Nx1A(tSU4k*ZeftkUM^(g8KgOc^SHJS5u+;u5 z|M(X|c$|S&=h5Rw(}D%_(iN9qk$(8#8`mv1O(uP(jJNHxtZNd#r+zKfC`OZQ}1Gnh(&*J-vs0i)U53xfqiYSHy(A`$I zGaXN1o4ATkqj4G_^a!ea6!a!hsNfS%*v$w~A?O1mvI0zG4F5)aKWh&$%tv*6@GxG~ z8_4yu<2#4^H=(t%YfEREfBrnmi(G;qU{lVJXW;TD*u;ow4F8;+ zkBoBGKD0fuubif!C|{`~(8SRUF)@W(Gr1K08lPS65L$&TU+1)b8J=^5mPGYjcr0=d zmLIeRT$HK)(Q<&m0#6C%ZTiN)hM;hYf$?*GIkd$0OHG=Bv(R%1bJ>eKr^>(C&ualO zJcqUW)vH#g`DlqSvm%02iDnvFCX&14pKB`PV$6b*aT=czujJi`tMN={Sf+O!j^A)o zgq1V}2Hp|hyh@mUlRfrD5s_EMm9~#CZ=0bC&<;?0z<#`X1Zr6IiT>qHhYb-C**XCs-bkz#CEx%%kNNTL85F4o}{KjQq1n`bkfLbyf z;~wMNn;2C$!R1_6tk%=X*|42Fs}g2-tV9VW^49V9&ySS?h3-*rxns_gBWtGwzB-JA zBm2Z8hf&W#NxsOPfZvA8hq9|eWOnYOehX8&L-WPbnv zKmbWZK~w-`ToP9O3c8-^h61eTaBko>zJTzX}=Mls=MZOl+8WjkX3Bu367jShLgSt=l0oO;^yg2(Ue$0_fYkFf^=i;BRZ2QiGvhZV=Sxl#ob#X$A+o}zl|1@^S=s?(nb5|J{#5uuk zv{tjHg=O!(>94;0^>o!$SJEdji{p;?Vb1b4a~8UfKB}o%m3AiHnAO&ZUM`p$EO~K3 zJn_tb;)Sd5lLEbEHC$ZsCJdi^t9jYZ)n&a}58t<+Hv%&P>j4CE4STiDn3w+SPd}e7 zzT|ui?akuO`2*>LKlRh;`fIOXjyE;ke#0-M_kZ%nbisv}qndm;UCe#io{#Rv3j4fy z)6<$YYtT5E5mz~`SiUsDudWNI$suZ)0I$=Z;`Q4 zoluKszf5_f#&}2n4S&VXwBLldFcR|?cC};S1K-$9wyxYkW?UU{Cl>lOp(3pyHHR^? zgX;m+cyK%sE{sCH@Fs8T!WxkNd3+$V_)q@zq;Fy&%RI#)#)W90xetg^TQ~7Z=H%-pVy2`1q_hr6TOM%(9RIZg zVBchzIk<@7F1FMFl=VZsa_T(7RE@V?SXXg`kp;9z9(p)EziD&2;f8C{f<<$=l99QG zT?9q3?rlXv)9sT}=j914N4Tf}R4y*e?b0}6V;&i!j9Dpd4zo|wr;^`*k!z5C17Gv3 zmzHuwypp28&v+4)a*_w&GLEJsZk3@&B}}gnKb5}4KDUe2NN-ITM0+CVLuBZiF%n|- zEw6?E1K)Iy9P;CTstRb#Sf&WZfY|lMP>*4lk7rh*--w2S2e6_cR5fH+9lVu2#v=z- zbr=9A__0ALq}iZd!9K`2Esd`%;=atbHqJp|Y(ltNP3>m|KJo}S=G^%A3K>n1_uqS+ zDFvi=rn4^lC!g%Azkj)ttk;t^DHL1Q#(EmSg0e?s zmM>dII#hs}u%2Y++OuwX;C`ioTGtK@=33RAZ!*e0;XUq$kjBbxtZV5Vv2$wsl`#6m z1lY2O>zp}l>{#`Nx?W5o%qjmj=NdniOiNbf+qXQ~g#~G?KZ~o^iZwnH@xLW18cG%* zyMbmI)&1|dv4MKo?ACqFj-Jy5!yq7Dg6dK%NRhT0})RFa+dAEY;D?4#CI!ik#`B#`X z5*)X*%E_%iMhwP!=N0-DfyMlEJML?&Dlb0d9dLK@U+D=902p}zOEvsZ#igyQ4yrZ# znRDl)W1Lw%*4xLf>@5894k%maF$XI36mI~=0##Ms;71Y8Ma<~vS^X)1i?c#)nb=Q3 zSe}Y%eHVTM>=ZY*x1n-}U6L<(vlkmMmJwBIp2j&UdnCF)e-VYj>m_EVy_#`Nw|Y7VbIUMcOTC z*;&g&)qdBm{c#_CFB%VObHw#r%s%FFhWYUyJ)U-9kZ;|(wdv+tZ%yEzt7Zg}f0 z>HZ%+5c5aHnM3TH?%cI2eegpcN*gy^2%X%8ZcgW}!tMfBlC{rSn9f?cB+W(m+Od~8 zDE10et@g}#@GbErNG`cf+uI%n%V}Bu;`MHLIBS?rH;eGz1$t`C-aFJo2P%Zr+iph)l(17qFtz8qYl1& z#qxBRTLFIk|M>lM%k`I~bI(18x?p_7_~MD4W8ARNim|s@Ad&e&O#^Ya4UAIHO)VU` zt7d?+XR#1MS^H0-dC=X<0!|Bc)IwAe(61-}%NsCt%;SY4k7(;dzHqb7_>RpQZydtr zmx7|{)TB_=e!5oc(YmnR!iD$|hpQTAAWXKhkR=@3KZvj(MB5`*SwJ4^# zAjV@|Mc(9@`=4A+HJya-kvW=QX#GrQ(T>j$@@*Tz*VLUxCN-uv8*Ky^_H(`2#|hiE zIV&w*a~XX2V7mXwKTQ{3crJ1c*Yt4=h`j~cjYn))$bgT;(Z)}e1BV8R+gk-ftI0)9 z1$$t+2x=c=J(^BC5N@v6zguR|1kZdd!MT|WG0xkhxqM^>*2`4deQc0e7tr5hCHY1) z=6KYl3lsjyaxODiUm6V^9_l4O`a2h6$WqqGr9h51p5gn6dgJww$dC_T#<=JNZg>gTr4NRIhj@RcUe7*u&D4- zVKyq_%2=jrc>FA|8@y{y?gXlUlYml#T*};0 zxd@|2#Ncgxoyk*pqGTLA6!i|w$SCtno!9iN@~An_EYCB+Z?d>GGS%v&j#i`zT1=LD zGJl{Jct$zhVoCE%xO)1k9^z~%Zrd|W$6CyAeFdEzVDhe+lT6)CGOg?qp0UmKz4Gj{ z)AHrZ*-=@*pfw{s_~3&WXnF}tw;eHP0Jh?foND~9;dVk%?~Mhl5*Gd`^&Knf6_8qW zj|W=5qfC;32?l+M;2qF&k*m~!015m&&BwuS4rf*S*bQ_?DkitQ&8Ofw29$MgN6Xu6 ztQxhFeCL*gXH`Fj2TIlV7&vd_#{~K5B|fM7l)5s00cRP@Q}?Sp8^TH)-!-1Bc@j~g z#4D(iLncX|sTzQ45VE5o?YNLrJ|~MxqZuFMcdqxbA!kazOzeOL#0FS}a3X1$3Cg2h z0|Decf}Hp%Xol7sZ~fc}?CHtJMx0C*;aTA%1WO}jW(;A)zTNNeA}q4^&A$-Ljc*(t zruCs4za7ov4b8K8(%umnfjP~HY)#{_DE67E4)55#BOU1KP8Tj%kcKeo#^eSJtvO?6xb9Tyj@?iSngx4=9O_KV z)}shO9iIP2AUnZiJ!1P~o(QLLhq)@_PPBpLNkt98S@ZKLXXoLg@B(P1Tc9{BYsCaF30@7Wz;Yu2twmtJ}W_%v}g|8cGo zvv7%P9~U6pO-WBb^)z_)rJfT5(5gMP%*0y0mf0ERytBI*{v1YFnSwwF8KdvEZ*#nq zC43qeWc-fZc!k{%yr2{F)gf^1L(RUash#5)2vdZOI{pC2dD1KdLXTziV%1&E2mKW0 ztSiT>LBp^V^4cN(Bwt+)z zBrd~H+zgCW_P`$}I3}@p!Q6C&8v?c;>`XH$@A_qnpkq@ybhL}R>1U;F`wz!r#O(HI zY2KW6v@d3*1D)I~!F6^QtX&)J_`yv((^npRiZ;oj%KSxX@m!9n96g@eIbyMR{+zTG zLz1mCn$p6#vtyA!?U85p?@i|~UcmkF9G7UCK|8abq(6YiMn~B^8Dvp`d+Vb+f>-R9 zT+kf#ng{C48^x9^f*zFBV^@c{l2RFJ4m6p!V6j~hu;f#1PxQjJF7k4`ka6NLbvPT| z)aHR25#97*i=pix1|W}MH=~_OvfXQ}^7!#%X~EoC9IIIz8k^E`7sn7zLc7`{16uk1 z;I4hvBD{GWKVgDBorFD*lWM0$(?jU1(5vS}E-tqHlP_p9{PW}aK#p8{zA|HSBESXB6abDq3{Wu8`P203{ zk=j$iiB;a{2XZ}TTHCf=xzDhDc~;k3EPA*$$-9hQtv`I^2yd0Xc;pwKDoy^F_%~1U zs<4K#l>CAU6@Iy}#;v#};@1L$PXZDXhnOf=RFqE-AL(SGmHV~QN8~&*Uj@bu`BxZ? zc^Tgwu(H?~#}9xR{2Bb8Y2ME0^Dre#9afKOA`&yzZUI{Pnamj55K}N$*c|f4T;gq1$_Lvwz)RDj^4nA$@ zxgA%?2O&vXXi%V-O_h(Y^5-}k{VqVl`aP3x1%)F_KHJ*ngsQu9a2K~!HFomtZk+vA zJPkktCf}KFGoR)-Ija0xqU)2(AFir?v)f+X$*7g$qMTp0L$Nl!-{xf-a{Pb%@yF6x zXRW}Z`8>uHG0PQd9AleEKd+in1w9g54skV@Ig9GQrLT&6;}Jl+*iGECpL^VwuB^rw z=00qn+ZRSV1ZIptW+Wl`FI9wV*@#wy=_FdelGeG2!mZyS=z`ZY`ksD-h?58oGuV+G z1_ufR*h)ACe!!{nFu(j~#=>@&o*hVqBl=m@UbUb;4Wa!c3yK=^YEs~*eu-G6%`iQ; zZE0LQaq-bWh3jFjG^T8370)q*@zAGbcNsigz_m{^+_L-FS6bF0*i%%VjH3%L`pa`} z&a}272#}A9NYY;oE{z`>Uv+G+ykjLIg#Bp<2PaU~UodZW`ltW&*H{>COM7-7;7Yv1 zSo!B(Z+3u3j&)OBtf@1P@T_*9i&9#4V+Z&+XYmKEceX!!yHBRAyZ6Ly<*}Z=v}Nn= zvd6f9#V8j7QU#zWUX)bL+OWbn#MD&0D#f99sY`h(PE56FuDZ&2BN84nqh= zqtb-(n5%PR7m1?O(mMD6dRQvH!$@9)X8v}(X{M~wWr!OL1~@`7wXYfL;|RD&XQ7P& z-GYwPs}6bp#K|o93QF4h=Uhsja`FSX>ahakN#gipUDRr;io$Cebc*qv@Tf9>h36Pf z{Db}7F{fIAp!tK%ThhP(wVzG5-||)jd=_cYz<=oBr_+D=FMpiYtX!Es`SG8L1(N^p zJAagxEnA2Y#PibiH{6iE{he>8W5wXc3TJ^c6+!FTJ|uS*~O znUAo@KQl0Nhx^`pe~`ZM?K{(_e&%D$?-!&$_{0Ck{qAVzqP~5@bysur_E`GiV~?k| z-FR*Kxu5%FYC+n3;klR6Uw+{m>A+#EzjM#}^*3xxpZVoar#`Iq|BHi%(*r+zD1H5J zzMDSt^PfoPakQYj=VZF;d-tS2`SY)&`3T#;_Y40hJ@Leo>Cq>*u*h>V-FWSlz_^j) z8$XO=gxYghzHCYQ#0Njb@s2ywakNQpyzByG5VSmg`U7DLp&N~&KCJM6n2NmIVvS^n>rG4HvCTXRlsK*MSv!>{)E)-uJJ5{f>0jiY4i{|L0##OO`H) z9rhpIcVAp3_nA-sYI^X22h#WNdpP}*kAEn=h|$O$yLP8v{FzVESGS@CcrZQn)Klp@ z_dS$m%$m+32{&UjwWR~huWozi6=~J#<>?z=`w~KTPpH@Td9xXO`m-PSKw7bEMcT_E z*WccGcY6A{=hH{te{1^W_1Dq=9Y{a8|Kaq^mhCJmbs*HY#G*`dvqycjT``nyeb+nE zh1BnhFTRvM_m^Kvmt1&$n!8{L+Ay0~C|F22&rgT2Z*kMcYoebXL^j*DZCkqU{vWas zf{{RW^Y9 zbUJniu{uwWl7)LahN>!HUKa!e6P=6|r(gA#I~&8S$sEVui5~}L)jYELjk^o3Hu+Xn z&W)c=@B@zudU22UFL=ml;hq?qF}|l8Z%m?sfN0^af96=P3g(y$ zY9BTD*=7wYPr)Gv5*q29BrsVcl61~= zBrRctPyy~1s72$1E!RT`$HK45B>b2(GHFw-?=1}SwpFbbyMlY*&@-I1WRfS0f_p)# z;T?58CcK)2h$ne9WEZJ&)M_On3RHQUQrIl%SWi z&A@Br=i9C_pRdd`G+EBKjz}$j1+#=iwiS%Xd7y3he9hDrI~vzzTkuq~q&v z+;>HcTtr(%Fd$SRApg&(LvPD3)U*$xym zeZ)DkCLiIN-I#^^D8FGPzerZ)Z3_M>UNt1sz+JZP(sh;PO?Kv!QG5pn8g zmvgX#IS^N44YOnK8P*}JP7m8Tp&DC+`rtdZ>cud2gmEw%3!Eaa0B_zE9_A$BgpYOj zR(1|Uy%v9;V#`Qe6*_&FoqF-I{>)1{Q|JiK?L`5;1;K>P7z9?d|VKKljN`q-|TaBE&bR9ou)LqeqVh zK2b*IEz?*W@%;Z_sCiS)pj=i-woY9wk{6_bWsM_gE@*H+y46s|(x_wRu`W6o*PY=J zu6R?p55b)s=uzw-jH*7ZS~E1%^7#zUv$H6qT@2^ISr~VY6PZ$c`2-xSGbcas@TUIC z7cs+~=kGa2SaGjngqB+N1~=e=pZsWz^kc&Sgwon|XQgEerg4}3OA+?g8!m$8A51-H zOl;V&D6K#D7RWo4e(4jxnQpuNt?51Qy*#a5yDJuUmpVBx#^r$Gt>JJB9HcT zrZ3)cXS(G*?@AY)w=DH_arBMyt>b2j`7__1I$EcscfI{Oc6hmZbMQmy-~6XPNFTcW z*7WIr_|epTygwa8a9nftS!u}}Znt1#f9b-7>4J0DAw<6f+joQK;D+Txrj3`Z$DRbofM(4|AOGn4 z(rq`t6HS1&bm_%w*x^s&YcGt~I7hSNHBSa_CT|eTw z$2lHpX-!*>phd8ZIoFNnr`7or6gtpNI7p!JM zqb-g|-TvO&(w!{g{Kmigz4YzR{G(W;TZA^pObvGOTzk!x*vwdxKL5qPPK&53H7h&< zRn62QPWj2a>aS1X;QaMw{QU_L>@zVH)MG&8{L!caTI{%brh*QwqIq=M(E&(*Dj+%p z+;%9s=>ki|M5jk3<+Nv3S`Rzz+z--o}7dqKX!7t!z~OFo(8|{ zBW9NSjd;YwzwzMnppe7NH*jc(n|K>1=VOs_p1$i5gjI#r zd^7$9s)KFzsUp0QFEYxs$v8&47?-*D`d1@tL@i}{Ipj>3!>d<(M_Vh&tGD6SPCQXh z1ut4kwA~yOlZ7f?EXe^)B5wy zkBPGrCwJ`4D=;F1T>gy1DZkr2kCJ(#dlEcfvv=e% z7K&a$%dy^*c~9s^x`#1sxjU{@9}ht7!yM=enVCfQ@&BHJA^Oa{0mjtaFw0c zEW8;v&ffzh#zo;}B$%AS%SDi=+H$~-3^P7P&2-{h{~DV0@C;6FsKyY4;TS&xzUh^E ztMkYRa9*9Js;iG}CZ-zkRsV^s%v(o!$jDqt5oHj9Rt#gKYTdvtGc&k@lX5%4DtOAwR^%%Q-u0VC*YAjwB&?_0PlRw9r13j)Z^PSI)11r zFcm?)9~F1i?mY`E&F0K*P2c#&ces8IYxN!TQU|KSeFMAGFoJwX$4usgE-a7-ycnwB zRT(_)P;f487b&K-YNSvC4Wq_?Bz^N+-$?UWKv=M7UYa$#9rgZBcIPdpXSXpr$Zq|B znupW4A)u9AZfGX0G&@iP`(Scls+#W{*{ffhpi2{cAYc1f2O7kaMSh+OKL*Tm#q4)kLH_^o8Gag`d zv*14)`g-^I&F_3`nuF^40LL_Le&=P6hyp3>@7i_-O1U4RzAK6bFV78B)`RVx>ypQlW7 z5QG<^Q80v-i<%)4A5KiGDWj_AZP*!58)nD$z07sn*c}e zue$t-bpHA0qt~C%+H>VJ%TO-_}S?n{LBXewpvV=U$izg4|lOa zGL&}g*qJW9?9%k!Ti=m3@B2E}Akr4mBsphJYx>fcznU()WHpN|tJ3m?bJN+&7o?TT z=Ob`WN!zyWO<(=$H`3)BFHJYzcvZS$;~H$Lr1Ur6{0^E!v(m;Zu0!Ku1IL8ASYXqL z=k&B?`_ApYR}z2_cw=ND7XIcXW~W)5prH(=MnB8SyfQLF+#~BB3D1fufS*wtGkQ9 zXakOcgpS)YyQ&n~DGjK`WOVbYKCyGWu z9x#l{sx|{p*`09kTi{t9I@?{lc80Jgh#8zIbMoZGz&LsE7q5v66O#^tYV;tVJh0_S znFD*MauO%<29n%4=JE5CEQ;rtn6KkU#)4&yfEjcG2j7mnnS%(b4ZJxR)SR6h0 zi&rgr=9k)MgF~n$&-s;TF37C$*XztnfcU|5uNx> z;96MeUBvmu#SWq@$O+PRTgo3EHO3m-l5)P0v0!;}d9yp`qo2r`GIplQB&9@}>>Wh{ zc13sT66NPzT#ZS^+wh!QJtUJ$yaHeqAYA{Oig(pMd>b#~R{r@rqQy^R?#8b_govvM z@R+WIy0}u@IrI(q4cy1UB~y!i>NBAysAqqF1AogGUUmOc4t)y!>hN>CAa3!Lp8Ttm zN(ec%@8T-aYwt1bt>jt@eFaBVl0c{6^a@D|T8+^g-LH_`3N9e(<(~uq5$pAm^dZdS7eZ)ck_E{K3-CmYEOYG{rCv88P(7}& zG63Y^Rk!ec`|FsSh0;8ZaIO}CekON{tA^@=q4DZvG&K*&vtQRO@z3j-u27#dpRwgRQmg27D}macq~B5DAB640c-y^tv0;dQ6biz7!u!m$6t(2p+#1k}%Knb6FQoPBSEc(**N_so9O17nx!|1&WDrtz>Ro_aj(-M5{y z*NfBq#dFi~W1MA2W8m=a{b0*|+iVAqLPs|zG;lZMA_pNZ2-|&7b+LPCIi#n%@$pAI z>(MdNIGPZXmlXJ2%n+V+=uwI3s5{#ThOj9Ri#o)OO%d*vb2nbC1L+++51qXiet57i z7A>ffOlOFvigVTu0IO%t$4p0C!>g<{PG{T>u4bDx zYfgG;$3BG1{pl@NUY%Od;*&*ZceJEi-g|30+B99FVnB{^ZRMrbI+yu zmtVrJ`8uvj+?oFBFFv2%dj0ii2CPio{a2-Dzi`5;n?eaWhjr#mr z{%ippt>>AN)+}4fVh_@=^~hCzGdMnCJF%V1n-Bc(hiN84`NbDsLfW&_*6n+$#Tw?6+o3o^5lH$@!n zJeb-sy!U6H`&@eVi6_!8{?b3B9<1XbZj1P8`ofnv9&pxr7T1=iox2Y~pXTUyEt{7h zXbkkyOD;(r;B{c%KE5FdW%4$M_uY1DoW~zzL8EaH8E!p8reQ;7vW_A`0t9Zg{vNX^Op{u$>^%WS->5aKBsEJA@H;uli?^9L3fK+l}Eq&lgnM|I*=O|G0JEHXetQ5BjfyI z?h=XeF#s_MXtJZ=+X2a)d5f*;ooaFp#JDrdjP;M5 zhrkfuz_m)2!4fx;XBgFouwud*VZb0=fH%CNr5ZN7S&80%@IZQ&0Y>YvJ}%DX__>ZF z8``e$OzO9|2RwdYj{?%<5hmXlA?KO%w^;IER89bh=zQ}oWidEBDnQjlN}%#UB-3pg zeaN7=GY{&YK?YdD?T_*kz{y_PWIi)Z`KuzG@(MU&l`{(LVy8`d#8XE;*A>Mv&ni9$ zL>(4dWb97K<}^Hl@>RS>x1`QEL|qg}cxB(>@$zq4Zw-zyYcPdf!7pVBUKrEJa+I=5 zRZpMmEpnC~fl#i8iI4+>95twnv(PYn`FXhlSy4QZBls5lvv1>X6|vFFB8~@cH1jLb zUoP(gt5!xmCP^4@GVew*qUD(W=C%@Tw<@~}Zu;9VpJ0OKb$1GCL+k)q1<`j_xJ8+9 z=QfEWgN$NC`AR(!pfhKY9l55+-!O8t-NZO;?vCqmRLNsL2u0-Y`0j$RnG7QMw6S9u z*Qb@{hW{xKUc$~lrsOMk6&V*0vONAVN-4UG2NSYH7%;Nq(2 z=4TB9;8`vUZCPx~j%6-j2TaBtt@4rt{AoQH4*pAH%RLexfWai|J1O0F{8) z5DO8J2mY~3?Hd|KUx3?ml#Il-wA?4eh%LUF+b=i*JJ+Af&7N>2uFC>ZH2W^BZnr7L zY{!o=9lq#c{BDK*gX~boV!U$!K<07+1^NL#zU{SehCAqCzQB|Y#&IFZqgh^GI8FKh zM-4CY^~`w_7TA|9V>fiLgDb)AP7gmegk|E8Q(fGvbRcI~;Aj$K!eG)Q%K)^Ze1u*1W_JErDPc#P>i~)0#MN!8%PaKv4?tVg#1FC~JD;=UN4h)@J_U8- z^TEC;ZQZ&p?c8$!!4;fQuOG#5o}2ebrcN-)({fo*{it^e7j;i0=Q-1eBabu9A)bc_ zq%nNQoJjxZ-k^sD4rgGPF7?9`EIbU7poKDo;X~SiZPkSf`6mbnPlTIneVq47Uo|!= z59k75>Mr;}qK7*NOK*It57SFU=T?@Xgjp!+3p|mQsh~D+NNL-P+o9QDdgi%p>6)wG zifTEuJ&vHtwr?wXUtZC`-cx6 zO5J?-VWe=!_O0pIQ4C0e$(q*o)CGS`LG@&A>oknO%}Q5aetBxcMi260>O!kxJSR|Oj z4*Idq!SuxAn-Mg3VBg{-8WA0->u66}xojm`05gL=v)jG?a4tt)oY%HeH)sc7xNhFO zS@^fG=;HCxwpd8=`nH)IF=?MUHNEp)x1~oh^!@oSd^z2I`|at1HD{+|Xa*eX;#x<@ zsrJLs?qlqPKhIT+7pIkLR-}tJp3jc;@{Q?lzk4_K2M(~4 zzLdU4O@iL^iI05{8XU#AOP-(;fFbj^@F6l%+l5w$E%yTX$@O z7f`OCy*%^Glj+(kuBM*Xhy4l}!?xxoYfGzF8gmSW<3UZF&0l}snza6W_~5BWIMy)= z?b_3-<#XVD7rLnK!ic_Q%>T}w*F~_GHn#n;!aLR8o0S;bdz_!M0lR8Q#5@_Dn2-*7 zF(C3Qv2E-VJ%TS4(^w}l_?Li&gpnJ-q7L%XpGQdCYx@p>H~*qU zr5FbCWExn+EWif*$lEfw=s_d~0Mo|63QieESM@m4f_8)}bW#! zWw}<4K9T=o*p6roWcr|Fbgz<^LPrwaYXZ)>3|D;BwC7uJl zmW5S6(>RSZ_l&&;)P(3Rh0_YpodcLL}jyUEme0xUx z6uhHIMv3f%8UP}`?#NvjJXsTgIKhj;5gZFz3?}lDW3Nx}njHWWM^ic|2gYO)JY+-& zBTqSTHcsGyEAr>VvRQ^WZ%Q6cNP;)yPr^KFY2INN$@1{uHkK#onP!$%T$<%c^6~mO zh5T-G-sFqCcoR7SF+V|fyo6BNxFO=gZ-r+S4*cvghHif&G5i8T3>wkKEw|xDsj~Cs z;)PGReFw8-AN!lYrHWA1j9)y!jz_pW0FXa}w!Q-|2P|QLHE^TP!9N!DGO8eu9f4a0 z72PToL8Ymz>mWC6OQU_s+>aCm`6Ot8GOXWzwuAVrqRyF!YH|ni61ZoLTE1B znBdw+1uF8ZqL;9YLZ+pD^;~nmDsR^OiR@<)1T#F_8$vB-*V{0dG|+#P7@X}z;2Ipj zVz=#8W`>d(N1-W5*hjFBMOzbU>{#)36v{;rGhrLw@s@c<@T+wT1b!q_GxcZu+qp=WbL2N%33HY|ZOyju-BgfJ* z41Bd20X$pTO|iQ4EfqgZmhU!w$v5LMwSMLojHj+{PVZ=QHzF<_mY^ z6);?+l5VP2YgyjK2zSICw=^!;fdF#Bg&WgCRKuej6uz$?A)GmjHi8sXG}71${N8@9 zT%(L9pmA*>iZYhIgc4_ZTK*W1p$)h-Q%7Furv`&{FM~88)O!pAG6mJ8vvc#Q+$%rI z?yq(1;>K|AaGKk`An0oRVU7owp9>-8A)Zlg>M>teDL}^$D=}9mzc_&(_~|x)tf4)L zaZp>NkGYXSwXrX^X)6wG_%s{-y7O-zX4iWKSCwHMo-50q-n1vp?AV4qhx5}WjKytv z@x^pAXRQ}4n~!|ao}PPtPg--%IjO5}M*7|V`nh!O>Q(9b>u*SN=C-nEG$&1m{@=g< zv2@*AZ^Za@Z+i5RAE7aEG+lkgrD^wp6KU7BE$J9W)~>wl3e@BmrE|{RfGT@uT8-NL z?tMo&E-}Ck@C^yOacSG0<5*fh#u@en=~}GzKl=EyY0E9QU~ukGdgkdD(e&?0kNoKu z)AaVAL;GV{df&U3q%He;(<6^P_5X4ACO~>!*MZ*ceQ$I(8XEx+JHS=oB8rQwh13#h zY>#AnOgpljaqNm+am|!7sbnf1PoHUJiSpdHUt*g1 zeK-N8${+mO&y-vD-ct77ahtw291II(gc160zxZ>~gCEBng7 z`;-5x{Kr54v*pKr=5H{HKU>_QZXDsmiidKUeKS7yXJ05k4zKUpwXwAJuPPG=h*cQc zH!}^NneOGKSC2wJ_=0xH&Jy7y+_-9(WAwgV-gEaI1wTU>Si7nGDN9ba?7XqOYwx?t z`Zd>K7kuq!!R?$4FvnZ=fe0*`S1V1 z|HLwh4&)!3@_DiYW%W{4$!lJahBtoVg&#lhuL{ZVchGO!f5Y{C;|p;@FeAWXQgDS6 z*NT&2b)J^Tqq2@2JBrX&V77AHO9z{sjG#~qwLey5D_Cl3S-0)nxFPEkbbn_!g)j~G(XupDlFmZ{D|_|iFO zZBp>7ufWAJ5*AYlc{a@YP}zw#!TZWR`9|3CnA7j$Ti~N&WBum8L?YXv`578KP6qO7 z)QJKs6qNjy@#Htdlis29n#O;Y1;;|dp>5Dc0+!!^X`18_A;~Z1Z%Us@$FpGpJ)UWY z`4;i{nsI<7A18Jh!?ZDTg+RY091RTfCOLoBThODTcfhE=M|tDfvJ*X?g_HGenDyZF zOv6-KQ#Pfnib@YU%auHspt^~?brP3weTY0VpTIT3{kHOt(tHaACF0|h#ujIr_v}FZ^*!INer@_51aBlUS=NwQ zBtCx3u$A`!NMxN$K?Cj@K3lKfT28UK(#7#h<$9hyFWQ~R-M~zP%l^ndBp_8hqf9VF z2cHf-Wr%&V$C%kK$B|j$VA;8>FXdIfW*s}NInM5e7uqm>-55;6-<|Ar%0=6WbZjsO zo_r+7C8oCC!ZhIiSR32tIoeqma!KA0&n5W*lQ(EX`(FU>HVn#3M-P{=XP+snXxonF z+22iK;JG*00%h!E3hVKU7t3qsI28lKashc0JO@vKp#=(^$-L4SCeMoZB#nPoJ!%Ov z0H)ZaY8C5cQS#y4qeqW21@=7abbHG%_&cT6GWWBN_^v(MOZTM<{9P=)0B}@z8ADE| zsFu4%so8rhm3`_wo}<;FsX6OEHmQ}>Y$MB6i<@Yi|J4anCFE7N#dRwmF#;7dQviHBj zNa8Ahwlh*c%WnE}>{337F~)X*@a7!yA=ai-F8f&Z7dPZp9-6T{uAVa$js)-lPxmgc zPd42}cGaJln5Jxu;CJ;SPdm#P$CM2)h1+yaf0j=c7D>Y*4NAf63G_EwfE<_dCfi5F z?vby~FrD$1X^FDCFGS9^w4a2wL2~N{a$>}VG!*~=@)kX8&{oHmv~os=RbrnZZA}+> zhm)Ndk>Dl&3Bqv8FYl(VXdnr=#K~~mu<_$V^s99o1Lf;%Po^U(POri8!YhZ$qu+kI zwDqhi=cZcYh``_e%;#CQaE#IAo^t&BTzTlx$8q8_8)LqMo$n8n$DVi&1009QY+L#C zmmZDL`^ytc<{NexZEfOOKU92aiXbXI^-vJo)sq-~bJX z|J?qA<sYn1oMN8=j}LtO@n<>3U^}y6Mvxb!oH%i=?0e}z*|+~?HaXtLG8dM= zuo>Y+>fr?C)0SM4KiELsO-vtq;_0%PeGIl-zY!VM&3gT#oKo^!In25A=a}vA5RRI0 zmI?Is53zp*gE;N9Dd-{YXTjn0*)cXEyuj}J=gMuj-oPFJ+Y0`ykVnCHik)akw5jlr zXL~SAo#UN&>E!wTFV?!)VDbOO)aR3@55*A+NW2DF>~Py?xH;1Morwj_D*?cRFWyMs zPz*CD!-a8)Os8Q7U}xcb#F4mMie!bcJ$We3hC!E9+*JfHNP$<6 zsQE2Cw{*?{2M@6Hk7NutxzVC z@%SFtQvMwAwPUcj;11kwJ^pk$&fxHD&ro9MShKTAI4Wg&h3!-XyF{lRu<0B-$TKi7 zZ!UlBlEhadL&MR!ar2!tK*-nWfX1pE15&E1N1D+2GsVYy2UELH52G_P9^{X5>h0H= z6LcjX^NtZwaU`L%@PGcPoEV4P;E~$PZh*9E#ygUc&b))B@g3SlIw1g(Fw10lj1P6< zQi;sGBT{5teTtj>reJh~71#c?z_(5li<1E=o(jCHM1ik}P;Top_y#T1phakJy~(q7 z@Z#4Q^=7?@5%KxnPThEAS+ZPFV#?6!S~%!6#|V{EK%GHhJqg!~C_%F*B)p+QmUZY9 zN9u`u;B4}%6bBO|HMv6@FOjXnYk=ugNxU*r#;c=R&b;6em`xt^%5w401k&dvok7v| z@|$suB)sM}XP*>-@zpq7gh_Khg>g;ZH6HOX-~h~jQgBTmw#4)CL&#n)~QBOV%fsYu2%ucq;QXfJudYlXh? zTKyQ=mLMJ(FFr(?q>s64>CScl06+jqL_t(#SVRik0~T>Ih4m%;j1~_(TL+CWKKUH! zs=&O}i85`*@!4?YZSrb3S)%RvEoFysDp1uuI6S^bEXyE*L?T6nYeM#We$1!l=bE0) zG3)OQ8UnZRT!X0YW?BE$q+5w15mw&nr{+4U%M{-P)O?wodJho(P)2X!5@G%}o-<+2 zW~fV$*-H({lg5N?O(zt69BnQ}P%$Xm*^JgbYm^n%Z?s={#VgCMyx|)>?PzV^Ku_7w zvj(O9G6vfWUlJqZYlwt#%Clld!(V4XYrq4h$PnGNn?_io4>BmR6?f}gCss~tmmicr zUdnZOtrE*YdlNTu_aV`a_%>UOQi>NcPna6{uBGk<&s`fgmWQ5y8Drn`xS3f7N>0mn zaKQFyUuhi$J%A%@>o2p=sfM1#i>*`Ix1kJopcHqZ1p7R|ZqTh5atqAqot(H>w(j8A zJ{+EHj&4&9@$<6$N#OuSc{2~|34#VLp$GML#j|`Hqrj#T2JfjLCw>)JK3FrtOdX|e zHBl8&E#XtX^Erc?8^Msixb3UeB+#eh5}@h8q}*D+dr>0J5a&wjSN z>*ia_G&3r0U>}61o_`HP`~qv!H#5k#Tz>PPeWu*KYX?gk)-ZkhEcje5qoX5b=lUIS zT;ad?{XZ}3Is4r`6j($N4x7V&`2w`xL{6=xfAIS9!mAgdze_in0)FyL`N}{3gR*1o z>au}d<;QTowH?3^W}3M2=5t^EQhE0+yV-euOF6|L-#nw-owPHj^?&V=C)r(o4bF%G zX2uLKYJ92ur@#8&mis?=TiL#K8@$+y{yD-l_NDT_e)DRAEW_QJz^q1h%O`F)8 zU~qf+>{nhYUw&wRS;tHmov_2JhjEN#FFeEM2Mah!W@wx8UR>T~Xch7A~or(&Bq;xaAt%IxI zqhj)hUt_%emxhua-{@Es-gFx0n65L&t`42-BswV*g4hsiuyg{ru3M(`=#((%_-Ka| zMzTE!aiv>4z4s1PopXjRiwSbV5F$oU25_OFkz+viczc5gz#-e zgV2z+L$L!;0HR z4BUy;d_8W)PQYpM8g}6UCLfR9@e=Ru?%sfHr>lb@X{0iQ@)CI2iAD7I5w4fq7qcON z*TFQL;7P-wogHRO$}U62g&3gdbsc+;-w97a3+8+kp41 zBf~?108*{|nr)p=J(?D0Dg#ufORPaOj>4BP^OA=0cxUjaN?vYsBu+$(j>*{vGZjyT z(O=Os;+Uy82&@Xv5Z|S5O{<6)`5Dc$ep9&*y3^L`%JUs!#=DeCCquT$gpyg=hJ{hn z6DBcBq1Vyk9z}_=@+zM3-Be!Yn@@E*a;)G)gvcY2tKw%cznRVv$VfnYR`&QD^(UW3 ztjsIwhHomjb&ddXK#ji*P=*_~Dv!9>#)PF4GkJ`*27lRZZLiTrNt5*AH!`asn?Cu> z4`KKj5^W}ss=g<_D>SI!1zhm4Okx)J)pQZlyp)ki2lD4J%1B70BrzhzHQv<>l$D?*x{o8L27d1C4SVo*HR=?&l_O2Q}o z>p?`6Hwcbz%|DiVg(lWab@^~rwtkG_HX>z&s9z%sED^4ul9W>@2d2+XH*jFMU z_^#~IP|tMXOrW5_3j`^bqEBL~X&AGiw}=(FAw#1=qKxEVA~UM4fKkDX50p8nY#)nb z6IiYCK91J~c4@zT=bmye%J&x-c^h7LUC74B0z3mO0Fl6U{DH2p6oW7xbp{yQ zo$Z&UEqz1`L=dNwejV{2`br1WuJ5_&rqaVy-xdseXFKTh?SS@PK-9hpm{z>B*LYth zzWGUu&Ymtt5Xntv39{NauKTT0$9oMc>Mp({fwC^mK-?{l^%1#7EH{elzJ6VK@x_-| zpL{C{`Y1bi-^jY$(=j4w{JB}y(t@+=j$@ew>Fsx%*=L=)?%004OTB@AvF;suTMqG; zHx@8*joXEuGlik1kv_(hZ23Sq=P{0>ueaWjZ`};cL_bBjX~W|b?ZIk`_9iyqWZl^weAXdi8&3U_Fqs%$v~P_5!S*HUUZN2<%2Yka zdsUVwDd`qi^W8JB8r)`?fpV6(z+%dMKclmb9v?n_nRVy=<(5r57;T?s)cOo{%t$-= zoH;*9Ty#1%-s|ed0A-rYIi|0x6LxhEmHxIt_HYOk!JlOmJ^f`IhX^}ZVsx)A*Y_@$ zb2t*F7RFh}-d!%SJYs5Y5{Fq!S;x-w&pdaqwC_L7Nc6Ut#bMvLY18I%l2Q53e)H*a z^V*(r9b32W+I)Ta=zI6Fv}2r&;f?^lEk^#QS%R@;!y4$bT+WVh^d1Bl8XRRt!E8Bj z=zQ?WD(Y@%WIgNPXUl8H#zT)@WT0jmI!v)_B9@R~gY*w=h)v`6k3$Rr9N;S!AUk=zV-a+GI;bdH1+g@zHll{(VqHnDh-WX z$7uZ=O93u~Y(8*gJnFIsT6Ln+FUp_l*y{A8=_Ji2+R6+z(5uW8h@+<2_n@P1P1$#N zth{n^f+_vX_lE(T*)TCNRX)RVi(%@hr^j9E?E@It0bVOJ3nWSpn+fjP-c=5rx=>yL zj{#;)^^wOc4uuyFjZvRn82dx)sWeue+W!*HGG-Gkyh8u7jG@o+3w7Vt?lQwZ7IEC7 z{4USsPsn=ZX!EtwqMAeBInUphVIPW+6@);Gj>}O&*6B>0J5$adA7aPJO-$ipG?mKl z(uL`t9aM;???$@%dsC~Y(Hk0qP8wH2pfO5p*xPiOheFe-UsFtRGb@eb4jR!$JnR~P zPU~{ot@3M*X;pR>3OVn!a;OsQ1}Yk=wJ=i<2kp$G!Z+7gIdu%-uRtT6)3QQ|FdkuE zFU8i5++GHfMM>^Yg1UMhqhbzJ`&jWinD7=H0mYKWJgf zP-eLMP3U#|u5wBmP`>;w4~I~9)gSSx=qq84Q$FX?Z=_%&YUV0>O8#5*P6gZYcI<<=N5io9Vx`e&M~ zD`44ntouwJb#D%V1A&nj_gn^`VNgZ%<^`~X6^{ao{Dmpdz$fsEgb}yqxzr_B!V|bT z<`sO&qp%v~1fVGbE)OcEot?Q0ddN=bn477IPvR!DEVEBM=M6adWO);d{H;E(+_KQ| zo(5(O09>@J>Wjz3t`2zpy$Mv6=j-EK5fUiY7+1I_F|LT_iPL=MH+wyoulqC-WXMMXK_bnou=(t z>~0oY1`V3Zu=0*meD8w6e%JUlbZgAF#7k!FzrdMy=TJE}GSNV5e{0olGTF(^s1m%)E z<(|fj%NgC|PuyY@xRHaELOTbp`wmEZX9u`J-VC}}7t_*va87hk=4m#s+Piya*)_`g z?pI$a-So>UfVSVrvZ>;HOv+S!2Jg0g`!T0!PukE3%YID`g=XNi!mHAg2no4*_MJa~ zM^*V#(a<(vbl1Rc7#S>&JpCNcv+UBn3pq2*;K?+47}M81C!Y4{dh~uq=BCljY@;zc zPW~E@j<{OS;%4{~JEb}L?x=h6m1W8LwcZ_(*TA=5on#cy&Aa-i`$O-$gyUrzV^94; zSsOP>R{|0@C1ZKrpMzTXh*}N$aC;z@4z~ydk@D*Fuemf!IR|q=+iHkTREEUw}17= z%f0WpgEQ$@v8m!>>2WUu{>@@1T(~@4USrz-Hy-|G`SY(nUYHTzXOARgndMqPr?ilbS|6*eS;&&SoS7jhA(GMQVqQ6Ds7O}w)~5GC_CP`YVD(#=}5uG-k&z}dFyZ{sYHh#51`zP+1S z6uoSOh|xWLS$hf{*ki<%f~4={D8dD1db+V=S3gtixlgj}VTSs#{4vl%y($~KIjv%Z zfx@1lRh%+`%>}J4u@68m-*HD$HaB8S&Jr(qMIP|E(Ug4t0l40hVP7kdSCqS%DpXu6 zp34@DxvAqP%KYXF>{z*$^+7N+4GH-I{UX5?Al~W=O|Y(xOsb&p>H7!$I#l$wUSiFY zWmh=s3EsSUbJ@OQI}B&zbJLMzcm=e=ZgOg}QU*|lVNN@dFxU~IKI`KRWdnf)*m!o+ zAj904%*$ufXiO{Y?WnvItSuV$Bn%^jg2yO79a_S4>NbiI9j^^bB~`(w&^9lLq_OCq z9iK{zc)Qt*otEV_%)0{GFdJid>WP<%Ee%pnHVs_LE2zyo1-2eG1S}2E^IG-X*?E{( zC-f5qJD=K+$#CcfygBoxoZ=(?6~f4&d^WB5i+g=HPs^w?#mi3KZ^9L49W&x@Jn7^& zxyLDI;$?VT01pF*uuuTNf9K8}p%|QD7ggy$iEIcIx75nZ5jGXK$E! z>p=0j&P$qA{~L6OxWH4))YAv0z4@9hgb*~U_a><8DKe~nESvG;4?)Xol-IPDGUx{$ z#`8IUGLGw7#ntkNi{E_~NGRLnZTY0BG&YVj4%{ezotK?)J*&ZQ(rXMpuXV(nDa|#aHgF<&yg{$c%z3{FUR?+DyDX5 z^1B@@h zizBLltFqn=EsYC_f@{aNSUOON}TrN#s&RHWGI@YW5 zt%fBY^%Z>0`wCyGz(~)$>NLIyS047N!p&@U+Nt!Gp3z=; zmKXdpr4)!AjWvkjd(&&6hiru}>i#E*ZaVuM(wYabL^Ik0kQ`ZaMxe&MbhaimxT8-4 zS?e?UR>JLDW^le5Cf`|d;n^O1j?$TlSk^S;Es*xB-$;w_%p>l=$r(u<1oa_PnMqqN z9689S-=^{lpZrMq`V0Fx^L&()DD)ch#=#I-bjK(gv#My7Rpd{5@Z9p~`}r!Rq>Iz3 z*E1D)a?J=54xYxSZ=1VZ?qR3v7N!fgF`7#+jUfZ7-~xq6E3KgiI0sdvgYZL68BRQ8 zZEQ@3avkxd1938?P(&{2n)oJMNf4xnWPFbRKybGlzDi^3NgZG<=d3^T{7dDpSPOl} z?oDyN_8FWYIyl^oz6TjMgP|Wdzza^D_gMqBn>_5xysSstkvyfbt!$w3$Ol}h2m4qJ zx|63*GD42SoGHli$twDqai+{$)-X{m2I*$#&)P8JbcDwSe1yrPj+EDX+L*U;)uo1x zg!^6R!HQ!NK6ma2c)5X?b!+DYT=F$VpH~=(M950fsH3P8M@XTOycYc=<A{ z9PvoJK8;O`CbA8ECmsI4BCqH_H0J3KLf4?oq31$tXFr4!g**aZF{P4YMy_R$AF_lZ zmgNEm`Pg?jB6vf@#XArPo`Y{%;cJ&|R0D=fOow-=flCl4r!G=Q8nhUL@Qe5ce6!$E+g$1oGY`j;LqC37_2JRFUdA8r4+5g~mrbtGP$jCfD8KEI81_CxGxF*S7=qyBPv z^3b93t3URE@;5&DACw!mt%_2$!mm&Op0Pa85l7q5z$(^^uPS$QR{euN^~v(t&;LdF z_22s6%T3$XW00?o_BQWH1sK)tE7ZyH2reyY$3fIadYvRuhYn{;7kJH9FLB_v4vhF#HYHR(Dm$qvW@Eyqpr^e-WE=vxDsWiEV1@9(yS7WrPdd?b z;G1k?EzER;)RYfdLEar0=CSnCda<+&E~0){2fm{kvoGu`8*d-Llhzx@*@Wjt z#(;=HRDl80e==skXv!l5y~MsU+d!cfWX<@zndg8Rc_=UxAX&kdrBNQ9Rs8G(>=Z&s zBQR$1$T`ja;fEiN&fZ;a?Ko!GRKF^#45>(&#-+IED8ySIv`4b9F-*sE5p3WL*)TNYvJ*kFj()sGje#$7m$j#?4o zE(|*v*FI_dI1R;)%y5s8(b(4uuJXDX+&u=yPIZhCZrNNzT>LMCqg4=!ydSt!a#Wl^ znYNoFy(&hQ!A?aZeGHFr7o#b{ccfW*NqRfkx*h^&J2x6^ZB*JB5FzMdm^k?!7XZx1 z`j1YUK&NslaHXwAxdwMmyK^dc=4F1VG&0SHyc~fGM@%IY{Vu(o4u`1W-crtAILl@x z@&dw@GPTjs* zV&0b7FdLZRA=s%O^R!;<497jk6rQsD*%lP^**?4r!#_vyExYu0l%!4{3O78Vv6lv5Y&K&^77BQi=aZ_H4~Zq6c)imx*0JMRanU|hOdtw<4oBwTVD3jjcL!bN<^W;VvzK@4T}P9=FaLHTBi;1O`kJJiHGM)( zs6RTQa9;3Y~b(;8i={DiZUG)ZF=eA;jyc37kVnNf@hmNDrwLZMkbDsR zVHnZDX|Fer$}5 zkjR~H*~VI;zsRzOtZ&7E&U#BS3d2weNVi24yO^~{x+uR?1xME=d+87eg%g8*87nSBdnyGMwqUv_WS8ETL3K+e2Q+>(WxXcuBtsat81r=xLeb86L9@5olj!9&vWP z0HA|Q69-f>ndZBOk>Fz-3DwTATtCFoSf??#_q~Qe2|Z@fE7}K{83+!P6dVC*{_v5G z2=Q(~$#+`6G6_y*9Y5zkcQH#0d{?s>+Zp6;FN*n@lPAgt?|M&J4Qh+0PnCXX)dPLR z+d8sO6g{11GOTr}L0~<#16v+T!xRcfUBh#vlebN$aRGH3bg>=+cw*dm7Jm)?nwLr1 zxa6Y*kZop&e$aKpM~@uGVN3r>39(zUt{6;dVIP4-j0>l(D-)G<_6hDNZyzgS>NnQ6 zmoq(FE@}Ib?=C>=K1O*rF;F86PfyVRS6pt4V@Xj^>AMd{$p^3S(bcALx;SKmnD#@ z){}pcu@Ed~-18S>Tpb+TlrbY~M#~(1;<;0&S>~~Zfi~BeCp=}pxU1J$zad8`t2y>U z`x$0f&beWrvjj1Ooe9y9f$*NkQ??i%+;wa?%SqZseFWWdP)S)4Mi}4fdWXpp3-YH% z$q~k+tTDQbauu_fK(viIZo?RL_J$20bw}G2G83La(=4r=?cPOsW5k^>&vsigd_6qD zk^<_v6CRqg9)h(23Xd_e=D5?!UB1ycW)8?`E{Vot@~X zryMj8&n^bsXn$=?p`V{DN6(!q|LAW$SbpM1KfseZ81CG)=%h7D;JT!UbU~7lC%!W>88@Irdo=JJ0EvyJm1)R+bz_$r$@khN(v4T@P@M{1BRu+Q z%Lz{W@b}KXv{SzC%bip`DurGF&lO5KJ0-TG{9S(OK$#vvm~7t)Bc~U&RZkHAWEii8 z@(|2(B`T1)mT1@baAi=unIJ0W8sDm*kRv>Y$FPn@U?x>a(wJlx{_h~;)8}k7?v#Im^BEN=j_Ph$vp$R*l@>c4VQMrh-1;!`6)Gz8zF%g_ zl$}&3N78gNJ;pE@d^H|-pB??yy&v8)7}sNh6qZi=6269cD44{x0}G?j&IzN;_wn#< z+mP&73T44NOx${U{@HVEMnj!Aon1xH>Gv8hK1V%}CY~vS_(WqxsI~-7*%)m=(%C&=okVofp zt--MCr9vx>!Vsg5gz43AUhqBMk+PvkLlfc1hpxf$uF|3r1L5gBoZjS- zKWXTQgZ1rf5&6XU!dBo~AL1>(I*jbtqa$JZlN&qIczc;YZcXIM|Uayf@amTHeW4tI zpT@cy+z3~^5!6U^0*zn9i#P; zG_?M4l+Xrhe$!|NWY8!KLbBFzqwEnUl{@pbGt3Tk1y)TzWuoxBoV6lt<)Ls!fSV&# zwoCI-iB*m$n<78k7-81AxC_U8f`6n5myoS3mo~)(AnV3J4Q}I$uWiHSHKJl3wx62c zjqAG#Lyc?QHk5Vp(-g{$c}Yv#x%r8c?LZosR+>xaZt7EGZW8C2&Mk59QeFsGMjBnrb4^sroe7(F!xmD4j0T87N1-F|sf9tY2YS|SItg6j}lLnyY1xu>|`h<() z;LYKhDV**=hXT>_-H9+^w_^z7q&e|kd%1= zH^66q9ebw0Up6b-SF|zmn?vD8JB2`&QyG>0wr$k5ZRr-U&@6-a!BXH)`+!zDy_pY? z%t=hkmb5n)F3Tq~U2z#8V%2ZZm-xih@etIcp0G1YFZ7)P=NbC%0p$OMGbhV1%hW#g z;SZHR{L`@#RRnkWZ}`Ls7P%smNy;c#1Y*T`Gs- z-Dmp%@DCHvxRf)LZ{>t(s^kswNL*_t!sRL-GhMU(7jlL&%0oUYJ5A?uKS%Oh25HLJ z7*9FFv!j$A+ooI=eDE(BgyF!u{O_oqvS9*e_$8cuwt4IP1oU#JZAV=lI8p9TPO*-e zzN-f(vKz6v)_#a}{waT*!3bWoGabl|9-60p$`Uje_Gxx7A7UzS7{SP4ojR6So>Jyn zhZV^rTRNXGbUNVyHziwcVMZWlsVy-BY>KJSw!LMRxh)b$r+l0R?NmF<=| zmYYBMyb~Q}ri)|zJpPxu>vEbjGEX{d&{?0x)le5XodWhTE)VP*pdVuN*nV9Z*oz|y z2@XHoR;beog&Fz<|FUh-f59IRKgz7QwB1I0@gxsRfi^*U{s0n&De#uixjH*pI>Awc z6I0aLJcC=n-Ncf{A=ZpLYhY@cIM@*`V|?lIg|cw=tW!0ac?W-(+3;W)qTkp=e2=Gl zb^oEVmR;hv;n;xFF_`5l+rRx*J8QSkmt(BmW}bU#V@-CPzJmj@V9;|uq)f%yOweRT zz}_1+P`^%dSNEX}Ah*wspDDloD-V{BeeiA^b_{X=d1{)u1l0F=XznI)&ib^Eb%4uy zzkbW+vTOGq)_@Pj(Rm;L(A{Mx=eqyq|M*YKp%W+2p;!U{o^Wbeo=?a7B2(Dgoi#y! zZy!VxiQ>u+?t_p^IZ2_8h|JL0(T)*rT`%dpCxIt*^s1+T!}20aMKEmJVwnWMSi=xA z7Nn2;ojk`qXHmk()Rq1267c5Xnf%TTp|spiA_SZEfKCyQ-c&DJh6ajY9l-6*zyx=v zlOt?T)Q`N#hIbnKlnla?ClOlWN6zsZ@4-1bd2D0UEDo>qG*~$EGLH(j zFiEK{9PCG0J`&G7%$+Mf2-S-)gX`A_d*}STErz`cqMZ!YPKN_Q5en=FTG}q2FXx|s zrfgshMcc;pbdF9fp+QqCS*a3!g?2G*t(kT*z+0qjioRwb^>dYxl^2y|b@Gq*sM-h< zFXO`mHUc^f6~a-bGz|>&a)d;GD1M7Du126ro*m0(Hpfu;K6>;>+0(K+lv+CvjUw%zKhn*__&N9u+&PGL6r7R2}z7MhPY8GYl#eJv3sOur^G#hEC zU@3r3oH$l??ATdG@EF@M>4i4_VrAUwfS4!#=y4R5ojt{f@`nJRJj26lFrstjMeqhNg|8u? z0j0A+;b2*YheyKTU%Qs|RseeZ@o%yd>jriXU5hj06nR>I8Atw*w?ZJpbC$=tbp%>( zs)m}pq5`Q?z__mK+q!jIq&a-}VAP=olt!_J<2Xv;1r!hKPrlJm6t27Xss#Ie7H@AK zhPE>_LivKW<`JWi+%-Bi&{lCoiUwvHZYZ4KBtH#6CwV})(n_9pw0!&a9c9zT%_uXM z!il3(>*kyGQYRbWrK9E5S6>OImU*gNIbALdG399+ZGn9&;755#Lp0g~8C;yb6!@7& zp3-Tf=h=4V<}Qx37}sk$oK-5~%%-92qwGYhVR`=iSd`CB2XA{D&=Y~P z4ijhb*jdNAPw3}mdBjm#$jk0NYdKDwI1cTpZ}>wVHJ-ep!$}2IKCs^78}zn~+qR>t zBd$&oUz9h>c^xA1o3g48IpsHbONWg4$xk|BH1=V*;N!ZU7m%5z6^AsGk+;GFU(x`iTw8xJi-?kUp+)jhQvzs7&)4*+;qM zJL%=0hJbhR6lcp4bVf#n0}9y?dz?@{>&@?$-F6~C@wXnF0T#|U>&Up^BhO10Wp0gQ zBR%1^OO;MbBF%hP7D*=^G(5#fX3&%Oy1ed)Y?!=YT=A{zSEEcGvrNvGkf+Sw-gb&M zY&^BI9vsx8?EHM>_}N%`(#}-VHWb8G_;45n-MaM%GHIaPP8=;ef6&uu=l0}Qg)|@; zfApzD1$$(i5LH0X+G$b}*C7lzDrj z-}-ah#UR^h;K`d)@z=56%lUCO@9!$Q=cgRs{ixl_rLaaHjvv3 zZ!pS+0RFg14S|_Stg&#L?0N%=72ZmIv;+r`)`CQ)wAv zx;g!)BlvN;4E3UZAb-d7dwB^oMcH-AVr{+pPdfRb<_RWAM7}!7rKz7)lKmbRH=j)B zzX;}gTmi?YDsJRpF7gp^EvMzGo(=Pv8b!kd7wSZVM5k*P_2rf8?&Vq1QjauHk&X6Y zTaC5w_TR``+n9VMPd)Lir%MO3CAxSAT+I5r=RJ3YteN82F&#f=&zz@i^#SWLWv2bZ zhx3F>EPt2jE5?|m>Uw;g2QAE)=x4ffhoijqdsSO?W{J;UK~L`Xe>$e-=UU4+?TKEN zK}!06^c2&=-WX)o4}a3Y!bxoD>b(h8yhQEQw9k7hZK{txWd>Px@hm%!Q~q9@(Y9+a zB7foV2fcJ0xx2a3wUr6|I6NG&AHOhOE{|WJJu~Y8M~7OgeQn4G@UPpw^{?(>TU8Fn z$quyDxFA+Ia?CBtz(a)bL&k21*v9nu7Y`mPw`^NmZrr{O1KoY0I?M5sr^+{8dabPC zeIuLIIS4VrrfNU?*FIJ@u4Sz|OHB$(B<6w9i~i#vj5>+4WbK=daWvW^k3UmRp1nk$ z!g32ng4VFXTqZk9ZMg#H`*- zs9`VHD`_a91>#x!eQI3QOJv&!d}lqRM)ZB+ECU3MpoF6zb9ndK@LaWH0M8v`2l?KX zvbObIrDY9AFtD4V!YN3qK!|74CxNSK`#v$cR&sKzYfogUa|OPeiTIB?kIPE7qYS}A zhzjP;oxAY7oh>IBjeqvJXE@XJTqwgD_c!dhsT?}=8XX2liy;i$(95(cfa}(62mz5J zLJN3?N6NPCJK}pNoIx}dlD2ZgO*eC=B@ot7?0}(Q@w)NmTOwVImeK%ghk-_iG$hMt zK+@5M69J^NETM$T=FtHsv#aPCC(;tWb?eq3j{@2>zP$Io_wrnKMoE`6n0=;kWVFCp zdIB!~5(bT%0Abzr?hmA*6f_1u@D)xdgy2|r3YODL42^18?11a~sPA@;rb(rpc;r#X zkMtr^UB*qJl!|99tfgPw$p-%tKT?s_`U_)${8e&&H;(z6M!fwV`SZ=Gdm4Si>`bac z=ydrpJhjGMMF*P7e$Hly^zgm(BPqf)J?6qzVV4($Tj!}G#&4Uh+Zo^NG((vO-`?(# zavjIHh+Dv|@T=cPM>a>Dr{b06GM<<44bLSK(`Aq|Rz2#+%~Fih+p{Y0*6GmBdU89u zFtX`Thll3kn3<8`QNr1rh)%L)xr@<{ong#h=7fGB`TKR=RRg+=m-)QjiqD9ju1}+mmOLe&DpkXd&~~` z+@F1h_?*hYS~i!0NY9!kLpZ=<#`J>)kF(f+Ww9G0p>u|JL9?Mm?@i64U zk!aDb9I+c283_lWBm1V69;R>^O2`9p&31$Q3V5c?HY{ybQZ%Aiw?>b=N>(H|9>_Ero5uRA;VJ)2uVLY3eT9tkU7A1`zk5x%378Lr#qt#H!V%w;StzvNW!c=+sdk)+ zo9lO#&+?iuJ^pDFx}0Gam+>BY_+gY?RVsB!Yp^NIq!Vef!yZipZss9 zUL%i)M*!Jb&iqr3SX+Gj4ww8_U)G(rxO#@hvdW}tWIJ~i@eu|LE^{BE&fN|B>~r5P zqqn@P{M;uWDA#QpEr0yTV`cxLlV#7&Tcg}6>+>kuv(Q7sX_;X?uqs3F*Y-R1FcV<8 zjGtuZZJfHJt9r|if9!#>iJ2akPaZ2hQy0o0_3K8)@^%N7teX)oL6lIQrAfsP%04ga zOd~=*vEQ*|mOtnobj-focz*FWN*~FM$3yj;G5k(=iq%NN4;P`ti?-``LLwP;?GiqZ zQ+0-(@>A60KW9qmq;Wvv^w|s1{ydIMc@w~dD$Zm~5x8=MIt)$>43BMHd)>x}V_&FY z-p4xovz&LnZ~q~7Q0MqF`j&$)yey=09kUNRx^QA5`)r495Z4Cph?9Orp#LU~=t`eB2ae+m_zW?dL75XL)KCYVz%xIcm(oGmVJ)hsiLVBI@Q7_!?EHz#cF6;6 zyoUjq6U=D+#ZSJ!{M_IC$wJeIpK*3G7;mATdg96QTfg(q%0SyisIX8zc+cJCQxD!# zRzWgn!HB*szcLBq84(L!1h(E-ZoYAA`SsuYoifnHAVIIPnZ2`GrppKJy@QeXfvBUF zrJG#hP1~^Dt3Q*Li{?V#Tguw?|4I2rzxB_{2^<7{4DNK`?D>(8y`LlE7>EKZHVg!DW4!yf|GR{M2ujzyF{AX!+$|`58_# z=qS5)U043rul$GQfBx-%Q%>L%804tA0UV91&}E#V*UA1wxhH@+pL#E)rj9jO)eWWb z8v1|xAE*9L(Vx36xhx}kWl{e%wBqFvW zgJ{ggn5NQN-~~Nx$|nC}GZOO`0{MXmf7UiwS-~=t;rU~P_%pswz8lZBYP+#LMp_^I z54?&q{qT;z-WJ0?*IGk9=sd#?q7xjUFx@&=2C3*SrfAF@JycFmIU_eRs<06c4T4d| zsRxJ*T?_N4x zys{YgANlBqY2@q<4^zsZdIkkmD}hd1N#kx9rFh~I_l@xFONu0#bOStvrvt{z0 zJaFarI$nJjhJV+JTbH~3R;Ot$NAq+2{d+A}O@BpPEePmhmK;sW`br*ix))wn_(LTd z2}SH2(F^4WhLQi`4?!cpX$aCNh-)}CO4b`+S0O1ef&<06W%JzF}A0`k%zu>-e*u=DrQNC^H9{0r^n zeS9}B@quQ-A-@c&+8!^KPbZ1^roy&@pK#4XBTywu_?E-AC7c-DB+O+U(#G@}M2<3i z>|-A%j!K4YG!=@-AH2QSf5Pq`!UY$f8Pf}>9MT# zGvc8!<%p!P!)O!PD0|YwI97rV6KSIXS6}WSUmX?w%1Et13$_GYNWGPtqdj zs=~ce9>3dRu4P@Nmm62=WN;KWW?e+bnxo;)%n^==TaPa7aQA29Y4|u*THe*6ptI7l zI|^;wX*%t#+qRec-g}=#qvPHLf6zJeEPtee!2Tc1amiL;7qf3d6qT1MHRvv|p&nJ?-OWmR5C6Vq$pNMpZS zF6rfR1?em;rGo}`jK~8_`J|B_PCVe6ccdk6@s|eDIMM>svROYmtfC##K77}>F>muU z5Bb*brWI+QHS|4dO+(6c+T!Lk>ca;QayIpN*|Bw7(C?||_mwT1wwBxOxUJlBE5#`?BxF7h+?xSko)c!bItFwi`vafkGhvkTuj11tQR$vE4o2I*wO@ z{VuPQsEQ+<<<}P0@7v!iUko#@eY{6Q1y7nM3ay0`y7lt=>Q+eXW*UDG^^6N38JHvF~ zIq>Kk9YWb3#u2ex)^faAw>$$c&#^|g6SyC`?Ur))o?T^>qFz4qav7c&D}xyHo>8sL zv^#CX>1jb+2kwZlWr7l5htUwfd?rvCqr8z%j1z%=_Z?bkY{m#WpMnAr$#~U!gbQ_r zcFAW(lq0jB2wGWx1RJKZE^LuCwRj{%%dkNE#_}UvhuW5Hn`4LkLx+!$Sh(hv@J*Ke zAtAKA7}X;zjcoXux>XLW8eB~tI2kuwU+%f*ebJ_SY0qnZd2RXDW8W-aee?;=|7JEE zFlI2)+!VT_lLWlG30phuUf!9aT~3~7=2`Gj6sMw-sEGrAe2YF3Orsx#{)^5qVd}Z; z47K@U9}dlAX-7gygDO$Qw`{`Zp2an0q_XVF_4+NyL0Z>f4~~wo5#dC+pmE-cV;ao~Sw2y7jUo*FRN!iIw9FNWNiME-U&NT<`8UO4m%F^)VfA5Zq}%DuYG z;%l8!@Q9heq@vw*vOfF5_*nViZClIF|Ll)5n}sNhpwBWZubaUGPZs#_`|d<;{b%KO ze)r$RXnbqI@yXP0XTmPfZk*oWRBvTd%036?JRt!`JuJVCGtYnS$39X%_rZGG*>WX63$5IWW|UBS?9y-0ESo-BFfvEcY=hb`||W%+__o-CWA5 z9PM3V0D>6{_9fI5{T_p{@P~3+CW|)B7yA+SBe9?3m5aKCS3?)2o|XO9sml^P?Lm3D zw8$V1kuRL@EL%6R=_2(p+`cK}h8&T*?OT{h1`M5L&Put6qvPc1^PFOVV;z{wZXVgD zY@*F7277=>zgJq$Dq5-N1!pS359 zs$z`LxUxbTuZ@S5IJF?NQiBO14xuo+LG@*0m4O#wEWPIKFnlN^3bHCsVJU-5sDkUr z{Sb;`FjaDxANdonn(OL!lyAF63g^Zva!}-lSI=iVDDw$Lqk@u(Nsfd_OGh0d9{GD; z=KR^f(fF=wuX2`Fmd8%Q=fK8izIzcA>HHRPB220$1exFGq)|2)!-SOIl*2X*aaalS zIeVF`xv*>qF~h{dGFF#)NDN^b>IajD$E}KU^{py^H}TG$p4+N9002M$NklUD`D0|>~WrUg*(%LKEEBF8lWr=V*_B25C zL^9Q#HqeUFm>p-NY-DZRFg6I*0VE1ZyDX!0cU(J>t*ELXJ{VQ_$BJJXP?Mj8Vu5)=xTG^Rd{~A5v2$6Zn zKI()=>tCqJLHq`qDx>0)mxh+{LoVnT;hQ6}hU7jL-j1fBNZdr&EvvGJ<(J>!4w&a5#>L-I5Uh~NHeE0IwNBdrTxN%^X16VgJt#bIt&w* zPl2Cj0r6T6tQn1c*SZT+ zqeTR782D5a&S$gdDRfn%_*_GV2-Xu=kUu;LziHg}v3zlg_H>!qT~4)kv|XLk zdaO5|wXHeAx}=j7-k3qYxKsS_+EGTGal)e0n_EvC&J{8Z#|dTg8M`lN@9d8lw1ci* zEB%W6QDdqcWp*A@uwOlSq5RTM{!rPtn*FNA&Xi}Kc^cPebUDL<*?SX=1P>0cFYmf> zS6Mf@y6ih}pj@OK?Y(s!BkWI=R}MVKneuDdbZ?mba=KW4$`T=ts=GXKu{`nAV`b}> zE#>1s`bmz>V`+R?3L5v9_1!q%Ry#`q zC&Ae<GJ76ez?5*j_u_){^1{#_uO}Lc{dI@s;J!a zp4-apUwtHI-Szb&vzXuCj&V<~3T?>^n$ApQd#ia&8LlCI`oz(4{_tx&Ln28J56DL? zIIErfu)wSWmzj8kq)zCVnP;0KJTyHjP#%&8+)S_qdFadx^$6vkx*%?3AhBNn|8#ij z;8}D=n6dyFZ=bQK!}2V5zMVdD0-5W~$Q)Qu*KsDZ_EC$oURaAbGY4dx80>ur51~(p zJcZDamb?=!hY4M(;2Xtty=GNm*wKe-&mImT5-qQz#UZ`^wpic&6XAw+yp+ zL<{T87pZ6kPrJqhqXr(U;CfKkoJoAXP%YBhil~%6o>}drLSiwpy=HJ01QPQ=4-;>1Q-GaLYzmP%lJNs zmAQNQ>|?y~;?x;Ci-<|%iVLK&1N99=xa#=v!jFy9tL|tsRs>Z)`8|I5iN@Rf`E}1# z-i`3rL#%OWM7iQ2(`)q9*UGw=#HH?8Qt_!{HQnp_t0=Zo=qi0v)Od{e6>SJ;(9A{{ z-|BSY=5zhdQ}q~RB(9xX#4;`a@{J@lS-3Y+#{hIdi@$SKP6M0b@D_FIJrej0_;s0u zYhJO&vx2A-#>>&G*IlGnsi?1fN*tpMeh&oXwg!ggLT8vl$+TBM5T1#n%zkMu#1)ZE z8kd6FjrojgyR!4}3gykvK*rXPVKpXpShkYJcd`?=8dskKmq@t+Pi4?c_|d+2uG2(# zlt{XXzgN=LI02L2#KGT{@?~uCNyk?t4cxO1GHrxb>92fF9y6A52gu;5LF85E;>cLz zV$?n_zg9fc_-NR*u9Y$+)HjNEt+YP~VRiYN%VOAfr$eOVC) z#La)U5l7^mO%QmZV5npmred3T3n&c{(}jbGdt9Q)KXJ;q3Da-B$Fc`TbK(e2^438l z+*+9qJOY$u1aD^H7-pHJl`_nwB(cFDg;+x2_q&%4feDPI36y&`vz%a7gG!mxo;B_d z9LA_dQQWa>3kvvf$dGWxkT%KIlBGia5U+ z1MShro+vNB{2EjvPs%&QIma6I`%df!FGus(@C=8=G{bprZgqKlf8=}9O}8^@yN>5Y z)>mHy-V)B9_2jPsBs6J{F&4u}zEziNp`oP?>vkORT8-}PAI2Wr%xOX#dv_tYzJ}ntz$iSDoQwVo11ftHj_+|<9svjxM;Q7<<( zY(r6JD;sn+99ona;)6O{@sYRu7Q6gAMMj{olqW2CLJk(OGgMd#Qg%G7{vj(xJyE3;<%k5!O>lj#yTdw zvF;f*wYsy>SNz3|gC#{D=;26bTcVHmq(I0eIR zmiY=tWI~U1$8+nMdg$!S{XnLenQMJ_;+T}jBV(djZh0%Pj>3So{V3@zh$F_ZCGYmr z#0s9_n|&)Zm;v8IhfkHKo_-DfbdQa(^5k<*mS6mvr^|ys@nG3~)9&*Adv7CU%KJ&2 zkUKVAU+&nkr<~q-Q+a|Z`^S!-hSMW6Co)4K9`+ zy7$(yh8^tNDB}$KSe;-E{iRus+3RX6+c|0B=9_QeBo;PwMlSDr;l=X!V~?{-|M~LB z!(YNdaTg>1pDZVioGdTz8!tC*T37z;PrguY*s&X@LMO9u2Fv>>XLG4?{j zVbDX{v+dd*f}h~IC1gujVDK-5CXTwMZ43HR`RXjd2xf*W@#%LT- zhAfKGAzDo~C$Xcwxlcz2ZOUT?TcD4$XvZj>rQdSUUfMZ(%F z$IBz%z#De#M7i_+`|%LT8r7&7dBrgZz-m-#JRq2W>7!Z81m@m|<8$>Q9`&$yMs!MCR(_kXeIqoR(TX^406V_#)}Wdg}poRy7J&K*)S*qb@&Xf~dRT6+&wmjkH(OzzA1I zx;joHF%Q>7rh-xBZ}fPq;hKh8jaO$yp;oZQSc9aFmV8>r7r@om3QqEI#;@g6eZM-* z|9kHtW64h1TPGUF@z*G0Vq7~P!l*JHBO%gZr5=5*@%CBghk*IxE)6wugdLY@{TFF8 z$_VG#FpVTfB>k963Rr%D;qB}M4d{Tyx5Ny%_TK`n%8(i4?~;ZQaW$wMIdbDr_t0Z`!nx&1v&=nyd$NixMRgA;+yBg5!^}`@)~b zmZdk?wf6oALpccrDy60HOQyYtLB+XzsOnHvGX+}TU#X5&L~IILK!Ci*ooT2rnJoD6-RxMF8UJan>tzrj$2%{GVNU&$&aCg11qy7n$N;X z!%(9>4ajsrw=(V55%?iS>D?qPW>i4gSo%Zinn%--0OyEa{PQ`V?2E)%{*Zibu6x(J zx0m(TttDUe&X%%?jYzj`+fue|-&$Th`yy$xomjI_ARHBrhHG^2C3s32nx8qwU=esp zXz43mbPA+Cl!XmPjkGdN6gzSBMXnb|@5YWRVCUnNVbxn5Sj9_R>O|te$SGyj(7M3# zGLh|PmX8iW+q5+EPkdaW5_N>(p@gpxdQlprahn!J~uG<197k zoo%Lb$ZtVz@{U3#`oJa+tu2n$GaqKXV-&iKv9F9_m>?5h5!NsCnzKK-2-JKyXQ~QcKcZ}b2mp#?!oc!>MIA!$rESF;X`bO%tn?!^1~l5 zpC11r7><>H{d=D+KmYST!xDjhj`rj(mGu zT<`~UclUYuOM_eK;#u=fWmmS(E3<K% z9SqYqa;6a5l+YII6S(K}yG4)s+!f z=FVHDO9(>o-8Z4V6EAE3`@TXRQ6W-H@1>4nq=`8E5fe~n-cRB~F*Sr<6da)2I zc!9|K@_4yKL;vPizE+<4%deKcu7R>?`>t{w(^GUJxZTMzf=EwK)^=i{pkAsPzR((Z zMZV;Djmyxw4E5(LV>Xb^&jCM58t--7`d-7R?^mU+gSo#^il!*v_3_QXNE#(sjQ?iS zSdsrvT;Dl=JByX;JI7s#_g0^-1-Ch@`8i=njW?qf!B@xo4)3o^TjNX`d-CeLytu+$ z###B6SvJ2nJvYOT=ap|)!mIPWk`p2hc#tYO?1)vtiLgM>r~1m!E1}finvto)-pW1G zzj-KcK4xOkT#h$`S2KK{o8L{}^xoj#rm#1Y#dnJn;56iFxOorOY2>*Aq|uJ*=#5X` zt?c#p`rb(RCLZcEugjFQ&0+PkO8S*xT}twXR}DTQWbctnPYkHiL5td8j%cI_@-)+^ z=5rzhNPgt}6~j7G5=ievhv}$keTi$-|Jl-S}D(4fr4fbhJ6PGYsUIoFf2)33ZFIHbRMD>pnx*5Slsr!A%I)a}3r1n}hZCvKExl%YJ4exZd>Y zOXZkkfkd>0c*#1}k?O~&Be3*SmdHA-X`>uox#F30&ANgtkMgIJp^eQ}gB=4NY0&{SlEZM;gJ9+sO59M;%`ItF1^d16=Ogbm zN-FK5L72v-%OPBrZwlnGDO}oBg>S@(pbC&q4DnuI zcFP&gx!3UasJ||B@Nn``_N)%*ZzF>rERXuPyx=U2#l;DXT1S2tN*}a|3L{$VM`3i* zI4Gne(US`xScSH9S-G6aR9F-4vLa6TD|>eDDf?eM$da6+7}xXV@BZz-Q$GCRyJbdZ z_A&{aY2I`2Qx|-2*WP!>z7q3`?1=-y8tuDx?~FFRZ{Lexyb#mpcW&9lEMoU9;WP#I z#tKBPAS$rgJaLrMI2`5e#2$G5h3DhsqY+MIQHHogOJmx>MK_hThj13(+~TEjky%Zh zY^XQHX2a43`APaiPlya!NTg#$M6^>L!q0QQz>j2KNFE1?53EP61_u zg%#)e(ut~^(~zH|ZOaGZ=#nq%N=K@jl{%AC2ZU|OC1sA-TmSN?gSl~(Bu29{WSk9U zUAwoBe6xfQb2Cc!l{s_r1V%L!0TuC|rG3s)7t1aIr9Kyo3~%IYkK`FE+jsl(+|<*` z=g)$gfz0j=pkdq-*DKnhH0M1Xsg@u219cKMDBtSV6f7F4ez1Pt7QP>XUgok6J>_;TRV?jSNg8sTvjoCr3dD>5>%>U z#N7(f-Aq-a7b=-Ao~@O}U-dvzJG(ZeD~vcfcCMT`a;WTo`biA>zbH!_FEi+xMjC${ z$!CYp)IxSWLSdrg@*hdP*H=CxgzJFdCf~#>LxaES?+EMQyZZfgchW?%Iu$SVHIm{*21s*NaeQr$UbiZ`Nx;n)6V=#@Dnq}Tt}>EBH3 ztK*Qi%4p?_Ps;NeE^o96%jZ?kvhll0g8D+FjX2c{&;F}nn7)Re&rRO~s$T;l_c~^L z2>eK%!RD8G8sR)QqBcE)P@S9jIojzcx_2)XIY%Nxp=+d%Px(U;Liwq`0mIARD6cOo z8T;1A&sY(gG~UBVj_(yrV^*G(8ocS_YKBSTfB+ng`WVHj@Cd_D==={_s_+3ogHyZ= z3nN=Yn-9{$siTf^-O7e@{&^8Qis1-Ny{w{M-XILGnpT$EvIs{77>JSBaQ|XcJ@XZX zNO{$dxN+6>lCeb2$|RJ}KIL2WwE|{sif#Uygt{|60ct`Fc5y@<`~+@M^SnDshIxU` zVhE8PU8DYEh6kC2v29}030+k9*C{>$m+FR_efO(Z#Y zfn_#~*q>#({Lrcm?BlUmUfs8kqvE!gjck5*kh&}k`2w)gHU7aB@XP`>j2t_{tc2U&bt_Z&r_2BOr=N-CM-BomFpH?4 z84B)k;w6kW90krGxy+`ZT^NujF=Q8R;gkyKHO~who6VvpS>TA+xN$AKWL+<^gk-W@ znmk$Vf8d_-sh{~N_&k?>5s_oGH}U*>YD>+`Y9M=j zwQYiD_}7^d(pp)j1K6b}8sfI&Xp3O0Gr*-Zm)M`fQGa>L%Vuj^mm2Q3(v94a3?(!a+m}q$?pT>+PpG6iN^QjRKVeyS0q!3XYL?#}9 z{3l(MW75HxKJZ87W@V9-UTT(q$}xUS{}rqoYEIX7N#{YQ9rS$DE5 zLqX)Owgrxyz+1>-rKxkL*~EimA&wm@o$FsKLri-bHpqu}T9G8}8c4#Wx~Hwuxl zbx24Er-sC|DJni$LFUQM1vcT4{Da#J=P`c$;l1V!(gq_|VT~wtObr?Fipwv}l)U2O|0gfac)vLW zLTEHaZ7$Q*-Ogf~aBRYXON& z_+H^@{>JmhuRqmg;;Y}QPqy9aiqZ81+%VF$o(uH$cA)2GA>`HLRETLqK|N9* z%Kt{c15ghNy+cYo>TMzA%$x-`a%cj9(Kxm*FrXweT~Xll#2E-|!3^&xC(dwm*XxV3 zd-AJzHkNk!l%gqkdc=;LZ)-}5aklnk@;jWh!)D`8mxq0g+T(z^8#(g z@7Q^z-?Wb$V|-rCPYeyfJ&!_VvMY%o!}pswX@IN@K9JTD;lbzfdwCus%;=WI;GF64 zOQT-wIS@)%<7y=P-*SRf2RgKlrAN9Zr#!UD8z{tJn`B=k7V|(^iAN3^Jh)6m;BS1L zVaCw)eAk!$6%u8U*Sdnq)QFoPBO74k;S~lf;5I;iXh0#KAU`hic7npI@iKU0JpVzj z6v@B&3G^%SS=UqrL6mq^6}e)3Z|c-iU9_Pa{V+bb+51jB=m)ryrvmhg8kw)^;0a#fBEH?x#I3- zuK49#3+blLST9#{o5hY>wsVpKbr647lVI>LyU)!O7^^c3EIf<-ar>z-3V;<)j; zp`Volyzs)1%=nX^)WG5C{`yN8`L=l(*o_PaT7;3~ynGk^XwQDzPKLP@$7;ImE=~`< z@Q&7w9cHft*HzHydVk|`MzlPkGJ=3$Tktl{8T_PknCBpr8BT&db>d{Zg3-T(QJ&?D zh%Ki=tz;?G>NT8DN~59RrXJGKc=&<)sa)1^fn|7?E?#Iy55L%6*|(n+0cTiZbf#V6 zx}r67=$m)nh0wC+pHZmAHu~(rTd{3Rn`ViP2X-(#O~a0)S^QQ42=f5HC@=UzsXv1& zg~5-=RbDDskaU=Xpe;liMHbq&jUV$OUc^w@jA!9YJYjAmb{$oJ2CiU5(HmcBrk?@B z2tc4Xqv~t&z7)jJ0S_7N@x&vY)j1e_=!A$A1JU>*5Lx^RXCbe5JGrhr`5I5luITA_s=?@B3wZVE92!E0@*CxQm;;x6)yTf-FJE|_*o#G06wciE0 zUk!fTzw#|D{F&#x(GEn}EpJmQUMN36jPfFUFKuOsaOf?c1zd@5{S5NTx3DpsNauRq z7(-`-lJep~#WnekJz#;XbVvLP-wH*jBvQp*h#MbqnM~YR-gwp9FyqH~9_71O(D7D# zD=a=0Axi8*iXFQ?Qqd_X|8cmnB$BSYk&fEG%nKhmIF{F5cPy)v7l9*O$rs-P!VzD@ zYnr6J8@xCoj_3NWpj}68b7XmXSCm#y*#KSK@UZ zf@p{+F(y)UXyEI?SNZW``q>k#n1RO`Dpc3PWvFc*>4{rovA)G3ZvK$R;1eg#JUD?6 zS`4ux?Vuen=@xwbicPxYd&zC~Uc)b!gt{bG4WsJxKySb*9v}poCOG(DMSYdK`4(@X z6e_hM@bU|!X zw6OG8BkWx0bRX>!E)l=NK2}!^I4TexK#OFD57I-vc;NW4ERw#TeDfFi9*9jJ94aJ; zv@t53$@DNeW!{-lQ#r-{Yj3sKE-lxVa}a8+fJY4ia5kz6^66?cd|^QPuQe~ zP~}_(61EJKTY0EBTtdLNY~IlR+yC-s+nJ-Uw4eEFKhxg)ws*JPci+~w+`KVY8ve$| zej}&zv)G(f6=yg}{Q}!(*0zJs?{EL~mpPF0VXQ@^Ug>^n*%e-Ym9bzMLt|gUiIX1jC*f5@wSpFRw5|-7rf4v$wTXhyv-mY zm2eS%m$)T?O)IP>SkDr42AWHrKF)F|-75zV zw_o{{Uui%7694oW4)UCTC23AlZ_T%7J9ucGs{+Jf zeZ9b7#WL(e({#Pm1=^cQ8$sS3PP|l=gDh1$Qhkgv#6MOE^tM_#%E5s0f-nbSgpv~u zQhLpBZZ@Kf%9+NE-K&S(82&#b-#-+?-V^W_W1L@R2xj&6oozXXKb$zso(lFqO<7Q9 z896$BrX4$hu}$G$M!;tov0BaO)VhtEx#N%nC@4txw`YVEJf1e{jQ@!XXWG+;_F=fY zKf^I+9&mgWOFTAjA})v8?BkT(J?ul7WZC~TD+3q+BJT1w%^i-bS1>Y%V0t)%_c32! z#BSD6EAY%PqO^!Bhgcg@BhMTN;V6>Ae>uvGRUVNrQJj^{!j3YNQcw4gu;G(|hq^NC z5~FSo3Y4NE9wRDVzLmiBMm~ONECV%y;pJ-ATlStr7-wL zp8AZZ+yfS#1rPmW^i)Mx>8%-`Dzc)ZmR5o{je-OguHli7(94@Fwjp$6Pnm z0}@%z@)3gPo*TaDyKqAxXUTzXR|TM?#19g`jbk4kQ7toE9CuV{@QUmyuim z^$*R#4faZW@LTwJ$Fx^l5DYFq#9Y@9MWmxbeZW+Oq$cb^rGqw`=)e;=yT0IDfaHgk@ z4oLhra!Q0aDt#fMsEjgKVfE>68EC!jF?*d8*5iDUAL$=H)3W{Hq=01stNe zTJH3?+Akg=A6#U>cj!~m9(`AC2!L1isblRe91?uw#$K<_OHhwPjG}>bsPXjo)w>MT znV^nxC`Zo1*9Are<3Lj{E0_Y+hFEUWC|2ur;psGwRs;;#7cz4-og-e3d5c3?iY$nI z6xPd857MRYSc0zOp>AmOz{5uclRy7?n3ese?Wtv1#x~*jxjn&s{%MbZ&1}}d6FCqr zkc|86B|vF3ry3~s2jPNkjkH>RlEj~b3)1evsOBxW{3bZGgh71q-w7E%?ds&7MU}$^ znF$wR_SZ7OGLZ=pzM(~Yt{#D4-lUVr{V!!fy0*F69YT{pX1jT>ra2hEMLhVFdJKJ& z&gf#;d)S)?VI4=WyyrFdwyjLgtY5ztKAGgjw)y7G7$q!kX7-_K{T$P9g!c zP**B#dFIjq788TYp_m zvYdQrcg!=O;($$Lq>8=jCNxu!HczBuMPzV>nfpkKZ3jYj6Ll(;N>B@K+m&|v?Ypq) zD0|Y?Fn1y}13uvb2`C@1(c4vKE_ltWTV`sH{w#j#oJ*NxRp+w*_4WYu!Z~DX4%=(b zp8f5!zyC$fL*oEe1`GY0H(VO+k4e`-Q4iU)UP+eq)@vA*UuD-eHu}E#B_Fn%xz&L| z7t8M?gMk|M4p~Ze^sS+O;W=_f7k{!g^8Lk~X<+S=+>& zktt;gmvt7Lc*!ii20mBdc~!$CBdQZroJbd=SQ(B^c}Ws%m8lf|PHtX2$Kf0o5GYaU zY)GuU-VMyuemjOBeEE@&gVzx?;xmA?9C}twvA=_v`6UyKDj^h>=Y@F&5ol1{_cJ%g zy`}8mU&hr6Y4A;-G;%PCqxuRFw5T9dx&{lxlTwc{1iZ^vV&o!ZOD4Sn%jGT%M3`@I zm>-4RgE!`f)e6G949bzRWJ}>1GHAt0XUB8gnWn&38JPgYpQm|LL2$Ohifsk*jDrkB z$Wz%0j?j+by5K5I!*3eCT7d#Xh3bltblMm#XEfAng1ooV<&8NIBfQ`$r&&foDFbO2 zmkNZ9O;xsm7sU=psl26P$yH$WOWY^`QWwsQ$gHRx#`yIojp=6rkYx@|6m}uxNB*Wq`y~<>P#nG78Gasmplv}qsOSYf=oDH`0L0=ki*M23A$k%wW~2V%9e`6 z$o2Od)7Zh(t-f8CY`t3E#*u#$m=Vu}e-(aw%jt}#IriRX$W%|OBPvO%D_;t*R_pj) zVPny+dcBI?QHTRTqYqv>j;d=_hpc-lf7XW~+_u42e&Pdi!@E!I_f?T~&dhkQDDVM! z^`EO4Hq^%U(<}R%C_vvG>js6%iEzd0I0(16sZ-m9(28;k)OtGGTsz7LJ#I zKx6rJEcKLP$*;YG)uz_q59tp1N^*%j;N;Pb?8>D{mEpZ$EE!+gp&?{IP-QgN)kxT6qy8P3M5MFzOQGgWILg;Fo#^FlX{jopBL1w$!7ao6!fdX!NGMkX-fL#rWn}5D7%YheZ zOM!{&Pd>sozms>%XWa26AG+u8s@KR*aPk$9fEzft9&)I5$~=od46zG|SI(TxoqC<6hx)=3ag- z$*K#6KZpZ|ph12Wo=gr&CtG8koHI8USUItSCGcl=o@#CDqV^a6w<(x!`+p6>lho6LuN=(G?kf1On%VJ{oN|ATYd*CvbgyMV=^^&s zzqId#Hv7icu^QRK=RBW-8iOsd_k|bQ1FyTUJ+t?@_UxW-aJv0w>dq`za2{{FcI?Ux zAWN}*UUScDxN%`;TMbQ{H*asNrq{KT$4_FMU*Hyw)$KHsn$DE(dto0pKdj~8yp60N zIMp6~^f9jAT+blIdgOYJ)g(`Fv&VXDqMGqOcJx^3=@{$oZ|{1$W#a^f&Ow>gOl+#l z=U`Em$=mj1Fp)Bd?Z!6hILaEKZcC7ZC7#f#V{j*OY8hq{tPJg1ZM3M$eG0j;qF9%$ zW4_xah>sUf+*ddA3=&6hCOHb}+U(I#|1w8(ta4ueSfr`ee0V=h|UG{Gv7*hz`GzaZ$ zTgq}SrtWWo{wvtwp7Eiu*oclgMu?L>o#IZng233l@Q-way+9-4iIASkd;HjuoOZcy z-#+%wxKymR9h~C6T=y?|x~mOH?Ippuhn|ZpB~fEH&7^Ci&7Te8kaW`b$8Z~=t|a=M zjs!scN~vb_&_NEDyuidd(Gmd%XHR1^+nY*ezC@0~%=rhIr3RO@MbSvZ#|;PIv@zU$ z$L_Xi^Ja|udwGDa6<2(tOJ8 za)!zeot=Q+HF}3k(Wst1J=6B@Ka#v{BJJIG-WhlsES2#LqCi*joP623lpE)_`Rxs# zp~cIjj$Bm3M|~B+$yN}X1KT=V6nU`%VeR@fnDXN54sdB{nzp|Zg=M0+>htQ z5_7axr!0jjz;&86eky$jn>b5?^u;SKjh4)O3^2m^mvn)VQ1O_ibZ6hIas=;`jTmub z^!2h3w#%$>&4IAWpB;#FSl&H9Va1SE_$5EgJMsKU5`TG#p7b&+cc-s4w(o`7U|vOWN!lqU=ZrX^2nk;*v+54qvjzH3Um-5olcH zQ~Y+ME?e`!9q&&bxqvRnqpgg~PQ`Cq;WAgG2yn`!(2kEr*z!t-TG!aq@mn*8Z<-(T6}6C2qph5=imxH{1eB(?!+~`o8*|Q zrSlGUh{qK`(re#D9ki`CqIgYbgrpEuehli!2gJi?q}l_7c|v`#jWZB}UBe{>E>&H@xG4_O5rmwLSUdqwV2GzRC&XuWK7w$+;E% z#69C0coW>yZNF65DqYjo$s7A<`~6ki?SABiSD0aaw!QVOZ*Fhrz`VDho1I{J`PaYp zwH&TDjZt`lNgCV9VbUHN>tBckXZkpilSj)c<(F^$_%kz|jC|)OJPB-=YlH=NtyjMN z>39}E>uoGTK$IIo^zLP$Y`8Ss{!adQ-h!(wmeEgn^T9=o%0mpEY-FGHG)CY&@`(MF zyxWJCzGoY!ZlFA0!nj|V{GMlK^!z!lXGE!X4}Y#^1V$pHq1trbDCg)1=)}y*WdKGn zdHCX<=h}br!4I}=Ter2lc5Z9yS<>#j@@+eAYJc=cKf+1=FJ|U{ij@ZYU*6wddiel{ zvaMtp{2G>xA85z8Z{CTjS>*N%Gx44yaEwFWw%oj_-Hg$H8QEC9*2DhLap1uWa5D_r z%p(g+*-hC^) zm~1B)7$Au@xqMao+7sX4j0gsgs8e5i{K@u~x4xxq*|xRq*m-;Vk&mozk3aHgXlRYA z2iazll?AN&xy&S?M(s2P{v-obhdt~N`M%|rZ44NkY%fzzC&-&CBGj`Sm{I3YPN(>G zMqXXSyjlSIYuI}Wh_bIttfuUil9wfvnUfF>!ss8I;GJfLgy)o)S8u17TFN1L@ZOt6 z7O^VHEe7((ll@77MhK(IdaRM>K!6jS_QB~7kvR?!jE<0Y;tE$4u59ml&%3B!bM2Am zUM74wHzc?MoAw8O&M-Kl?c|?>iPk^csN>jG$B)c1FtC$t4NRVr4q7j113af=F^{PpZ)CT+H-qfi1F{THHFX-xbAwRsor!l2+;H;mDvlUrb8&NB4chVyb{&>3W5{}@_5-WIRV<#=$)6#mo)4hDeMhNWWtKA@-7jil~j4g=)$Yw<7)#6 zO=%$lSMZ5MWaCMH3?}mHK_N$voMfrg3H+uw@MaSo!PYcL4yL%LM!NlzC*r2Ul9iS7|lA@A6iBM2)i}GIQzVl30U|6Uf7fm_)Ob-qUELhHlBQtZ|RiHSIXQ`R>}-G8+gOS-{}xWxznH>Pv2{x z>;PQOlyps7S>ew#%xj*0lfJHGxpHMXE7_ALZHYs8mPP@eWm1G&X4Mh6C(nalC==u= z^iV&=zrZ7MA&)2v%iMRq{2?!uw)wM;^*WWn`~*1hB44CsXJiMcJe+5boS5vKR&wI2 z+j+Wd$fwj9IzXv0FC-9n>C=f**UQy+4P%v9VN!B{n%`C6mp%tJl+BGBH??&)F>63) zXeXONA9yb8Y2@_;%lnkoWpu=wHg8I2J2S`iF(xuNX-}OCBlzfnq~pL#8O{O^0Rt_a z{thlg$tkOrSlOgZyCuqwn%pHH&MI23+n*W*#kzT3O_XdbMd~pjLeGtYOAy1LvSP>yWY}^Rp~#Jbm(XWN8_STit!`NxUrc zgWfJjDKt`6Su^<+%+5%cdmC-r&a;=YubdLMvmYuiDm>CC9tQ{gvz$`CW(U{nWgpZE zPlmb%V6rK%_5c7t07*naRCs4w=n`Uki42-rUeHmT2o^r7p8Hj9p>0}#>tW+@d%O;1 zyy1QHP*TzhqTKkN&w7sD%OBB+{?)N|psHIUtTIVm7*Ij_^)8-c0lbcVT@R1XfG%*- z;fr)chTi`4Kc$8jY82-+Lx;a68C>|jLIMYxk!rz11JXET91r&8toHTXNks$#SpuMIKi1J*< zxm*x&sQzRJ6UDXG`QRfkZgkjEPJN`hLA+i5Sc zr}gsO<#vXp>9)mFEVq}J^3H#?y+v6e2Ks@@v*b*#!jQ*sJ&X8=f2 z04;)vi!Lu7w2OAv%Bl9HN1wo8e}B7c>x%Xt{pgQyOTk*&?bd$uKmI}JZ0*F^i|y$> zue8D0Nb{0OWYM4;{7hRci3;QXTZp!MeNfbcs7@M zwayZEK)@N}HEXxD7Z03m$4))X$@-iXwhX(3$whU`vu9`9QC5MRI(3pW0%qFBKKXEa z*E`4#5o(*0Vtk=Xax7OB6SL*F^gY5n$TuDH$Q40ZdZmtKrsV!v&ls!`wd2WndB zM8vo3)!U}0SEhfo9Hqn4_)G8e9E!E@+`e`;{cO$_;d_MxBE)yA1tLQ_?8SF-lm6b- zHp@MGK-`>1K=+IObD_QNp4-^Au)Lk&Ai_)7d6!uUaT+_rvl<*Mltu^mTm`a-zgdj? z&wuHw?W@l`(eB=LEA?}VK^o4DfIjUi2Nn8&YE^`)9w|79`Yv>c=(q1|Q2bNGa}T^_ z$e%KA13>eT->z_~!g=CjoHd0?m{}hD^tHY7uoeeg2*BV*K=Csy%Ct3{)?p4|*CMxr zL9640Sd4rswtJki%$8Ozql!q3OW&%i<5~zBvkMq;M~_}^k3IfuJ9TD;nY3wyaEj$D z2rEL(NB~I?pNz~Su^I**zM%5xUYTi5#hk^^^01bdUVO2A`qRJHKJ)vZ%PE{zo(m|G zhmRbGP8vyimhpWi7$Uzu|wrW=1@L z*AWG$oFO;h_v#jTSAz$xOrhQbs}Y)aB7_EzI$)wvUn?3GnjsB&FjxMdT->AYBseIL z_!{58fieMc#rv9(mBuPp>6l_ap0iPQLK=XsToApZ+tREun{4xw0R_Ka z!tym=K!#W#1rCnNyYi!P=|I8-j7e#jqC>Jni(yawvNQ4!qeHJ8;P9L^$m>M=p6~hI zcK6+PWe}#zlXRJ`{4DyVuv2I5i;Tzz^jC=V*&d^~4RHaZK3Cag#tLQV8z?@{JhLaA zw|>gf#Pq0}sU zyi>NqIk=+2ql_vybL`=iZp+?$$x~^xeh8}qA?;P>6)qpgo!^F+9BV+y<7#7-vzwSD za=>d7N}+%9E^;#Rq0k4_jhGOynaKei45q> zNPjnc@E$$Nqqec=>GyR&Bj|b=XU^5{$#a0l{lzC;-65yxFM#2h8R}7fg;|K}+X6Mz z*P!U(hV=IY4A33w+Awj|zYbmT#S84Ug$|IiVk(`6$lvIT0Fy8(e7~T6g8VHZ&JqRy zm#W~6MPx+|)(uV@S#3iHPO3kr39NJqa6!Mp_k`-rAa~m)UZwhfJYie$Z6=?ut zK%Bp7oafI93A;7Kx(s&tHSQJm`gR#~i9R&}J&nERWMmFv7Gv1Wf#RZd1$gru~oDe`iln|GacQHGQp=;ybNboum4eWKS{zdNjTs<(HG*~bi)cACC^9c_u_^YFu; zZx1|hf7^BIZS8ZP`&`@e>^}OpWo-rZZf1sh&KALvv(iH%Ti}p12RJHCInHb>_0xfj zFMRP!?e!d>w~js8E^VG6z2hejaj>&9rWg~neKB5=zmgsCjB+*LRf&~eahK~n;0xfu z6Bt@Lh)+F&qh9qYJwa^Zpg;gA++sIv(iyK#@h;lLVx7-+Y6irOe1M+ z6-MwfR+pV(#`-jOuCKVl{&Z$lJ;B^-&>XmzuMRMI(xYu??m@?IDYLfn;|v3^XVJ-~ zSFpsN@=y<(AM~e`uSJ5h?_JF*&!=D9+kWw%{G;~MfBH|g&D+-HEUYJ9JV5`zfpoN` zht8gApZMHo>C4cu&z){Z!2g=<>)P5ob~1~;llp;t4mjn7?~2}Wwg>!+fB7%lKm5nP z(ALnGOt0M#f42rNUB9XQ$^Yihwl}=)e)<}WXvD>)-_^zPOz9D&3-RsdRFTx#)5pO- z)5z>Nd|Za{yKH(BcE}nAj?dBGGYPfCzHo*E`D?&_ex5zym*~&fvV82=f%bp>@;_%V z<52s^kNi+u!HSTzYcz&2iaC66HK*(E-@l&|{$GRMvbr5SbSMMj;ZdKAnW~qPfU@4#k6ygZ}k?^TS8s5?sOOVTlnnW-xbdVjr!j=J20?J2bqksCg5ye{5BMI zCk<$765*;|(SxmVb~gI(ux~QHK4H2&+u)E7ipIvnaIq5$p^Q37;ZM3m1PQpJ;DAqq z%7#UyTcHu3jgBYj&m%bJ87*?5+dPTBNW*PMmdfm?BMr|LYp^)@chSxfqLz}*G>WDN z_eqVF;iZ>eYL7Eg=wT5XXn0i2JP2Z9v1b6(9yOP-*_c@wF0m{?BO?x+(kQp2ukU{| zEQ*+n7=cy?o^enBdmADK8R%39It)rBxK;LFoEZ(4AqQx<mi zI00}5iX;)}R454fRR-ul!zeE$2lnhLn~K8z)9I{+4yoX6$Zy;ItI$rj->`-kV)W6-pNN8MIIT1GWjag;+g3g9@ZrfD1!7wg}+xQo5xzhe8eMs}Mw~hc3&`flFyh zIa=@Vlk@UVJSy#mojH4uG|q(=n>Ou8{-t|%M!wpvk&`O2v^j?ks#H6(?~0IBQ6z+4 z!fc7<m$_d4UgN3BqRRAd`@L2GOP-MY0WO4>Ip;ZM}T2$oS zy5gXzY3qcQ|F&z=oc}|)l>A#3HS6z68xUuUkb69Xh~4H!qpQAyM(mm?>U zQc4(SeZEW#IcjMU*x2WXwJwB0AGf8=W+&>;XcyZS#sg z!>u<}_Q=Ih{~QQWzVtU;(=;76|UQtwGf zURTZ1j{rieizvPnC-nC%G4mc!(i-ud$m5{{M~jHW5CIS!jzs)SXUe16pK)-*1<*mK z^+f{7`+1bh#ax@Vdf9qbrm~b2CEPuwfku{6HpB{g;@V$dnq~DE{f~7>qsjiw*4n$A z`)Wa-!9g*)&Cx+R%hGx#Pi0J2>II5+3|fSDW>tBUk0~eoF4ER1#*rP;QvOtomlH!d zIzLbSLynH(_myY%GTV58D~p$-LqQXwdbt#aw4qRu%q0KPC}I+ZvXq&eCwV-o3}h_- z@wM*NptQzz4MZgXnQ*YJ^aq+&^5r1ivUZgH#w)lV`$-Nbd*-=4?FYaAeHbY#+EaU9 zY^GtD*DrF zjuYCKOkwCD3m26q>bh-Il^waIZ**1eWfXx+3{ow{P&ZWG%`gk?tm!m^1=8pNi0S~Y zbhEFWr;R^{k-crz*7jQubFX)fRgXRE?!Cttr;WL7_xwilNR*yoNrpS zqJ7Vs?{D|qzP0`3zxDT+JlKiY({^&^S=CDWp=x8ygLwo6GU>bZSF)tt=TM>QLyzw` z_iY>Y#R8ZEL*UU>ZsF7Bo-aMZxB|N&{18r?8@DiOZxbO7)5=@I1$SA7dpt677UMw} zJ68*A7}?=ngXjw1A%mY|j6fYa?J^@qm9SQqs;q*~>nv;)s>n^(qGz~(hRH*1%&bdS zJVeElJD0P3b9#DJRsv9Sq6AZoLLa>@vCGdvhQYHQHUQvCCu1tSFStQrmsrBeIqqI8 zO#TKXvp432zi)j6$Q~{U3ELS+ zVc(t!n)qy9E-&UDr&<8}Clj2I{J05C7+KU#|s#3h_C!z+)x`^^4mUq-H=QqK4d zNerP^f9ctA`YhLdh?{hUQ6l-s|9Xy~tA!f)k1vrT0|E?4`@qkD4u7SdzvQWN*a*gr zcb>*KA2DX^oFyQ?^=8s4;U*&%zw2FGzLf!*J zN8E!MT2&a-m(0WglJD|U0cN0pGr4Vq9bU|~C;6}Ou3U)UvNIpcm$7`2 znFEzFm(@?Pl+pOYcrDi2wH`La6++B9ST^QOC;u*9Lh*-AuRoH-mW6{I=Hb%ml1F(^ zf3%;pPyREGu=Nj|A_Q@vMycUl!_0V|l$;p~4zKr9f3nGt!Y*ABHNllcmr#CleK2J~Hn`+Rc~dskA%?^5jAvTX2$9xPX)p)g z+wD_jUs<(mG7tbVd3MnO7j&%8eC3JuZ$9&Qn_Rn#IIAcS+du2L{i!%qCrQHu?e4qoW)E{~|LV6t+qSzLA0yT4@s>x)<8nNC(IM z$Paypw(K0+Du2Iy>QkR=Kl}y*vu*{pXVXqTOAWN2un9Xip zl7HUu_kZ}&gY@qHc^`g+GrrDuTz$%i!K3@kr>e((@V?lg1Ke7m$+DZ;Hrl4=jvi=#`mg<+_Tl%ut+6V*J-hc<`^wj8 z(-u!NFuSasI(v*XCfgHx4z^$XjlbUhv+sLzyYK!x!RvtRTwBQ*S`MGhWBghNPBFM} zoW0v?Zr;&0URl}>976B6f2BV(e}DexKH6?#@ckoie*-snarGMQ&ngUa?_PI#`6_0$ zr|7$ugLiV(@^;|ZVd^OR^vST&JV8D1FxWZj`5YNr!hn8sL7KZI@FQ&!a_Fj3n?SGj zvz@*)Pn_Ay?ate7Z-4t|f4+V2L+{U4J>~A*-}7GD#GBd&KJfkRsi&T7Pd)uOtBjAN z?Y@Ztl39&ujQ%Y*?_yT}<@U~ZzLUY@-R*O12VS{oRr)^L0MpK2D!=cwz0?9b#ABOd7)jvp zh_ggZWcd6Je0T!$;8ns0tF7nyj=Aol*2FsX28bYi9f<1UyRvlxC+a{hxuNJWxj{Y&?3xjfVWu;Ps%YB^6EOx@f7;L?L^XU%o~- z#B;T)AR6^Cei&~dZ=;lmC^TsxH^MlokJRypAM)*1nX}xLx}KAaJ;`?C2F_(*lzDd6 z*<2M;l>`2pk6wqBK@zKP6hjjp%CcmBpfCgxmw4mO)fO@E2OJs}cKQoWI#p^k?(B>m z$YQw}9Zh5ki!YsxiV!r~xv3;-kV==Gng*whOgLeD+7vUQ@!MxB&A-b%RoZL$W96|J zNpxb!1C^}|!jMMtOh_N;?s?Pbaa263B6xSTj2w@_4?T9y;&PT%xXeCi@Z+aaX1&%B z)|qY%`s93^LAMGjKw-<|K$&3|aE)lVGrK7vt3Bd5?Fegbc7d7U~5 z|K&|+HzE39WieY9D3r|lNrHbs-G0X%tXjFJz4op<+AR543caL281l*>c``}@WwaXu z=OcY4X2%OY2s22JWE;u3a)@B@4k(3gm>Z^uQHZ=2FCPA+a&q*Z|}Fvr?Qedii{%q zoD9B}+1FL=bC12yPF`NtrY>TPP{T5~&LH^}tu`27xnbUb7H*`DXq zZ|kl48N8*;v&`K>Va8LrasbgfBG0@&aKo+Z+wcDFrx^TP+TQ*~X6iU${8OL&IOpr^ zX4-H5_QRx)F??Zh+puCY%kd}L!DF16 zM7uVRt}u;}{gLee{1RV z6gcV(iL>PUhu-@7wte%OHpj|>wX502!L0oZw{h84Y`Tf_T`1?37@n^jKG^m@ai}d~ zAY#|n_0@;N%Q6rtOY-FTUQ1Zf!m<><=I7r*d@c7lESwh`(TD_5_};f_D@ zqaSW}+_5`X`M?ww^@^Kxibm+%&`Q`}IXlZH9_dfEZo0w;SSQ^=*O>6R{A z8U8!xxcAwY+PgpSqwOOfIN1Kp?|rpxyJb!G>eGzGc?ISSZ2+1;@g#z41zV^e1^J!* z`-fuK|NqJYg))tp%&+FKH5bhY4C=MwumKH*?R(D za5_`WG8ykXyo`cOcb{-O0h%}(FKaC-BLYP~fPq6L)gY&G0vMqy`EWGaUamT>LT+<< z&3EWi^o6u5AP#scmp;dw`N1Vy2{L~g@!~AlKmZUF;;Wb7Cu1Ef;dY{WB)W*>Di89= zs8Z}p?<6|D1!!wa=Uq{4m`Z_!j^ZVP4Xx0)fv&vvZwmnboBQ4PeG6Y{bPEA#2Z$eD>Pra^C3Jj? zvMhS%u3hccTX#lr(3sx0?*%%Yb20S9od#aR7~=hBno_B=E~!M>d8@?6sN%hhjDQR@ z0-yiVSd`eADqm#;4)wq={G`#91TntoQ0zEWm}@V$3a_Kc8uqjY#Br&4W`598Vx*;> zNo&ChqhV^24J`R7USTu}`AEKuYq`oi$A)RX$02_yGw(frFmT8}lCC@tcz6+wxXPF{sa0=$G5PKKgm>CMPV{Q)5TwB9cb()7M~HkN@#@JvJ8O*D_y}V3NZ{wN>1t{ztYT~r!aT< z6oWi4?VeVrFmZ;k!cwTE-#Efsk1)*`Ja@a3$|K9FF*q$#<@)zN`!EARm)cMK#E)~z z@mBV{x)sL37K|s#W`d5l=eqM+zFEJl&z7O-+-C!U{ioq9cd z?*Z_wkfdCyjC<}2m(gvvPI6$^Bac1S4zbOT;fZ$e9O0bK?qJj<&akmghkvGT5IjjL z5Oawcyg9C2o4a%#o(#zo= zFQdUdv&Fv!j*J*Q5~=ZUz{?5NBXvK&$D(&{;Q~G$c2#^oNM$_S@5Cb4&bUH*8Dq|5 zDi^j>%8mLi^@{h{MDW~Y^h;;jqsl8-Mff{(WwD zU^)A;by;O_hLugPzyIF$U;U|{V!I4*^asnKVHvXE>V*s>r9COW&64gXfA9C&|MCmJ z(B5z_D+HkXlJ)@UTkjn>!|Emf)L{(BlPsZMO52q|b>c>bF-FrzqrXqHT3}}8bk1#> zWsA!xuIZXwx`yTXoK{ai^jjbMH|?Q^9&C3q6MyTj+j21Un;v|yJ^tvU^lj%cs$a;- z_Rl=~BxePkZ}+ks{|8v{bclnkGxWUw(m|TIPmexp;utf6_)wWx2;=lX}90D zn*qm}^p_hqZpN_YnsHVxyPD%}23l|C>Ond1{NBB^+q5B+;O^abwtMfrx4nR2@8pN{ zn1%!O_PftN|9ox;TT0!VpE=)_-?A;+1)P<4<(G#EXL}ra$YHh+tYRC)?%j7}^?~i= zM#8PPM-Cs#xn}l3_8)yv(sb-MJQ&?8MJG59;^3aA+mhe^RJ-TiyV}P;`xSV=7F+}s z7K9JtRo+uG4B+Le>OsD~8{B{RhP_-4=lvO4yj~J~>T{Zrox`Wjwe2+Q)USf`+5c?W z;x8)R`7fMHj-tX*>Y}vpqp;9qd1zkZ#BU%Wel&C_B{tbns3b*$-qAEA&Q?7W+9HApRF|_2$=@E1Ck+VNIiZ6!yT2YoL0FpPYxzgcSg325@-# zKK$`WSZMWQgr;8nCaeehv{^Nk-niG2V?%JJ6JXx^Gv0EJc&UB$Zdw{XukJdZg#a1w zv|GIPw1$|&=kWFK`GBS%|5l@u=!gvYQLIZI$50ge%*VGzr0{kg-?}To--IIXC|We^Hr$@Teu0kP1BzZz zd16U)Ep7L#3ip6{&#cOsEprudXPFJX^+pA?My6FtFjfO#xrJhXcvmtFbGA^GM1DE~ ztnB&a%xW2+cF@jzyF}F)GdpjWk15~MX80(Nbo!DO!vsY@qjJ*Do%CGR?98l&q%%Cu zVw+ZsT4xlbpTBO1NTK-@wj0fc*%24b6|T`*;V75zmFA_4K!}njC9h&LV{A(yUFi~+ zv)aA!Yu7NBM!-4szs_6a^7e!JAP&&VbnJ^c?(74po!BU|Q4S@6#~ zr7|hH&L8DUIi6yM)m1H-abq?sgKI2zwT>$ju9kR=E1`boXa7dK>&{!5;o+x=^}wmY&``4s;XPdwQkd-9of;xq?nVMt!#%3c}A?)eNKs6oPo8$}(?T^J zZQ0a$nlTR*PFVsQ&Wschwi2A@ybZ1r_RvK_rr5VmttO2cSWtti+l-`5 zKFeE(;K#JvJ(IXDqt@`8z)+jA4dicf7+jS{aEY`{gF{rA zQC_>{*7kG%;1}Cp|EvF9`^lgDsdntdQHxf?+A@67`Ag6m#BN&WgGt495QOd*9Ul(?9kjoLPn8izv9}=$#L> z_JQ|)Z~N6>`)BR9e)kdf!mn%haU;ULw{sOAba~8!gDq|w%IYWSpsXx&>_$tXP2PS> zd-p>Rw158bPg0I-Q6kPXRsQ+Cd)jkPKh++3-Q8{7YG&KXFSR-O2Oa%_h9E1;m|0)R zO!N0}3jK2!)N?MYPaj}*?R()L!yv0ysJn2W?A)og@h0SrwnM&NV4&?Z#`h%KLL4Bl zuUou?efk)mQ>+j;bogZZ*uVW`d*BUkXmjw*EqP}-B=2*7@Y(kK3(vLt?!6BK{I+)c z?$_|Qo7=va1fjkAolkzEz2-IdrJhYru3!-0E)EjBgKz5*8Mlu64;i&AY=51#w%k3a z&U#{7acPwYO|tD^SSvT%}%{{aa)(Q0_ zS4>~Y;kYa4yALuO?1Uu_?RM{j-bp7yCPeNMXBhTjv#cL?G)V}f754b?V{IRIMc%z@Wjn)YoYhMq zuI9^Mi_!SiyxO_AcZjM(M}nUtlZJ!O%3ck1m39;p8aewQx_09EMyF)MCrB!d_;o!F zZ&dUWmP)Gja*9uLUf4lFuM8Xdt6N#SM>4r>Es>0*zPU z1#8@jY@F-x#mg=L*E!Phg50ZAn-ab@VcsF41HchT2Ve8rB)iC)Z93$XVt6b=VR2qj)u+RGF01>muGgo?*>XrKj> zlB7pkD&s1AD$S?pBs}y*BY)Fc4#y$P4#18%gBjF0xo2LIFP~}*YGb_H4kR53;=AX0 z1dE@EdmyBKF>a*AG{Og|5|3p;n?eU={RJ(D)*NTlnNDO8GphJyiMj0o3ayI1vSx>2 z3o%dQG0%E1mxQ^edtwpyKGShJi!6=i*Cq2-La+PO6^*7o)GyMP8VCq(Lr$}IJv2!# ze?4Cg8rV_aylG=w$$h*IOk9GO+Ke%*>2&R&RXA04?9jb#=8!XRVAszjnC3YwQU*xe zG)%YtBt?oe>^ZEId}X$o2sKzxbjrI|4js!fIhWg=JLd_zEWd|F_gbqYgtzhzrF{y+ z+vRqPG1xTTmjk0*+1V%mq?p-%3~l$`xz|pTG!D(b`|?~Nuz@|<$0;N8xr}X9w#)0+ zuMgZ2mJe#UC@Lx<%0*7=<=e9eJT=<`Ka~NXg5UN%?bkqryg)^bj7P30KRIKtPk%uh znxrcX9Kw{La7X<7#dw7n2ccqEYG724=Cy`{4gP0mQ%Crv}ko@3P&nIv-Kv@ zEL?%wDX{;QMFmujC7{!YzYIMpgWft5*&wb1>Y2fZFQ53-XR~iQSGAc3{^ta4=&eCc z;^Aj`S%xw2m2>`5mxnec`6CUDf90`gk~Zbsr+M~a{erjB!?!r|#Lqe;exG`t=L$;8 z%z+38jBKkcUvYY_hIQm5gGpyOWcDJ)_abHiEl>B3D{DDqjPH^i5~G|_w&X`6r4J^> za4X zwm>!N6DF1V`RCw~Wmoyyv1M)hKYr;~+qtvHp{cP%`at{W|NYDD9q)KoJ96mdtSVT~ z7J`!utmGVyIe4O;N1170I_szGspMCEFS^#yj-F>Z_W$%h|8MOhANgUHey?rk7#Mu) zvB%qsFCXS$N3Ig14RYYkI#gR?;5;&O8QQ8ICYLD}%f!aR++OF*9xiMXLdJDK!}`0g z1MC94Z#v`o5O^%Y=zZJ|5MY(Rj?VVLKFLX{I_MM_Nt(jT1 zg}6Y!bdG`43L0VDDywoSa8es1NeRVib0>j3*DWNLE7s`h;t<<6>q?TKe-i|nr# zGth9P{o?=m^X;hz?{5#?e|Ouu@uoJz>HFt$Th3+d3s$ROgx|bnOS|jd*D`BKy_Q39x=5EezmVk8M-daPPh4tNf_j*aqs95eG!954M||;gz=!*e590SHSOc{Oa%N zRcy^;6`r%`YsjAitCwg)r_l{OB+tS5waBJho}DyuAYw5CjFZbbFb`eh?Aa3;NSMU$ zJmqs1-C=@vxA>hrcDQZdvXK=#kF^O_!)d$Cb6sAxR4dpzGGX1f?$|zmH@WX1!+t1< zG43m>c1JEjsg8auFoId%3S^0O$}j?EVJhGikB-)sGaW4r8Ne=8TV#i5N6gH=GwybP zs(Hc1PxeP49ezhKqH!mwG>leC5q0HBs9K&|l_G#fG_gGG0)lB2rw5C&@C^Adj#2f` zTmAO0g+T>j61&o|f)T0X3If9OZGiZafxM3Wpz4{IF`vBR7bQ@<3FIeegyr8*e<~WZ z%ae-Oy(*q@$9k?pmEVFJ`@PzC`0|m&Di8JBxiJzS{_P^{}x<-ucu*_Qz;(RaQEUL zLGUt2oi8|*zewW*thNHh8n&P!-tJ&k_UMXkSoKZf@$gF#=HgKQp zS(eACKxQc!b+ndZqR^pCX%JY~E;|qeUi+&kkJ3q+F=l|1ml?4RDJp}mn9(Rh!6%+Z zu?nVSidUTSw~Q;44P@2*Uhc#53QcF8-4`Z|9Z;5X6IUhAnS!r9_5>Z20uN4?dP1l2 z&V#*$HB;|*lt`DILLa1r28k$nT96T0Xj)baPZO3dak)%cr&1{mcH&#6GUtWIp}VaQ2xcZIsCz`{`;RqyVx6Qviv}pYcc-*qW6oUJ^)J@CzO~K;XM8 zEGC%6IL9GH&T?F)L)AFX7xq!zC@l8Z3hr$~3F#;HLvY&O&KuD`T#_Ng0C1K@<&r z2Y4J@;8QYF*IbrbhfjJo208$IlBeQQ!Srm9@D-ey0m87K!I&}U&T!i%xZnK>M*kxA z+Iqm9I5er8I0)NGD|nM9IjDAlUotts@GVWcqMMHZbw3nl-lI? z&6_TRn95+j;*&f;QDr6%WC9)u6L||&(yXCSa1N9>AVzCU+X^Jgw}Xqe1D4xK44L2j zIGuGRN3%y<-;!*@gBSzsamDWxbqh*Q^7Iu!D>4)wk`KaP%Z{>mhCqRDhpy znL|dGGZT4&trY+3&;4S1?Q3_F-zDVN)hXU9UNfAwPafKvx}aJknZ&mtk>qN#27ev} zke4CP1AhW+aLIFrlwKHbK=`TuH**06b9gK_LtdH|9#tT=H{5C?eOV~?GGOQ5;q@kr7HWyFP%Tte((eDXb;|Z zd;9S}`jPh3qtCT-tfp8*y;=k=S1fJWx|v%HZjOvd$IJU)ZhJ7kUto6q40X|^|C?FH zzk&l;Z(1?gPF-fOp8T%5nVV>4&$q9A@$>EY{^#2Fy!|b06|>0d2<~mS&-};#=%2LT z`Rz}%|KYFvk6f`g(~fbK^-=~1EGFF*2D&utFSC7S>EwKS;Pv;mTefU&550js@|)Mw zkIl8i3^aT8#zeadoQK-3UAxgSuC%W_@-%VWlkZl9DjP%&8Mn`8={WMfff?-`J9oBU z`_+%O#~%4QILRx^<7(+I+68*p#aL>fy|22%RMcZ@~!Of6vhEqo$v7fmx$(YwwKZ=Lxp~_yZPS)*8T@c!!9kGwU-#y;!?wvQScP};P6q_y@DU}Z zKGSmym7st24KKPa*Wq`C@?J8dR6@~irzj0VAp&<)&B()-d zka64LXJs(2*(nI{_uYU%3`0R*>un|c2A7EegG3per zMi92YdZcj*hW8sMI4X}$7+?kofGCV zOVz$rr!{{iKj8G@cf3x0a%Euow&f6xS|{Ye3a2pp1r}(02+b9 z*GxwpB&U+5@m_|FN`;4-on+bB3n&IGAx61yMp8@S^mB&SQR*$*wx$zw@2u@iW;bAh zM*kT`_Eqv?wy8K1o_9M`=usBJ8we>y6=L*}CVm|4E=N282ZkmNFzTGNxoNO~Sw1baN74j1&PPThkzPE}4xt`hc zEOfe0?qZhMNtnRGjY3Z};Y4iuR?+25xud9c+v^5k-RWyz(}_6^QLnP!v~ zXjg%8;K7;2;EjwpqfrAOnZZ*TK^9a>!VdsPaz4C=Bz{t&A_7p@qSnIlov+TIAr~^t z7CD9h@idAA&I~XxmRaOmoW=!@vRuyEY6?SIra6Em8Q;mXX?8i0rr;X@L#jXB4G}w? zi0y#ivMnXPK=~%MkOa~^@zM1I8zm+_{M0Ii3KzF=l_!m~ZZPz=sGyLbVj!?3cZ#|> zL}#b$J#D&Hl}KX-Uqs1Y2Ag?N29r*nmT%37y9(qya^b<8x8HGl4rg*zkbE(1XNpdq zK9l9!$1pOcv+aW=yU2hCY%zz)!P^*hnf0o+Xa&ZBM>Tl`m9uH$TEzf_GhT}O1o7tG z?}-evE{SWlJZQ}dBAq1z$v5=J!J7zKctHMnDsw|%$~4?H(g2gNj>P!<`7bVU`H@*8 zJi=7`8Z@Bn0zUu@tlwn@vOR2T!oCSZ z#P+r56ipHhzM@U}Ex+h*yf45=uVq(lmXWHIEL*Gr4p#2;@z@PY3o zZ4bmdLt8k(0brY8c#E0s&feX4yCMD*YWYf&L6d zmsg8Q_++{uD&81Sd5?Z8oX^DR*spz#z&e`MfBp>nx)~gp zWy{T)3Ag2OcqeH*|Kbbn(Py4P8m8NM@bAk^hrGmj9XgziODD94`?CO?;eJ{M&cI~>gZNFtl`}!kKAY;op@%=34H|(Wd zVIYG{d0g!rTL|ao&(Z%}X|KQUE{y2ew)^(&T*HU)4Q{W>UbSmmJ4?IKZo8!&IIyD~ zX64)@^tVe~^F|(Qo2Iq8lmRPa^vtN%`&H6Ap2P^N>6 zNM>X$axY$Zw1rg^cQatJ$Ze27czy2EdtPc^{^Hk0ePf0mX^VUNpQh6^6}T~~rTIJE zl?L@4mk5oG)mX83@|M^P(0_(Y~(qWPn+4r!OPk*4$rS24vImpH=e`qRAd zFW@5X{#QSH_Drj=8cw9(6rV5s&+l*MDtE;*lLXfY)d=B;Lg^DA6!qXv9wArZF;86#e{NqfGKCyW(kM4B?=nAtXg{VOciGp`XU9!3mZup5idN%P&QN@Sw4b)RR{gr*zul0)a}5SG`GRctc)o2SzOnKrBuQ zZ>43#zajam2g(OPMGC<6ZuKj8m1SsF0VJWwANlm@stK=?128;y1;je`%&D+A6Dl1J zREWoAb@E(4)6g)tY$V0QdrorzpQq`HR}jw*P)R=~9?H|h@>DRLVVp!^vhQ{vKovM+^6v7 zng5h4aOAU~gQ@aJRD*(0Ui+eqi8GFGJ{G?96h_F3$k*UkaP?hb1y_)UCNDq--;jUH zKd(VE#O@wG1s;^7k~kHn@{7S*0Ai1~7$P%6-a~Hu^p}Qe8~XVfMsu)3+A29s`eAm7 zG9Aa|?E`bn+$sY*FgEVkeK+OLY7mW8WXWGnc=a{ z%%fnRZ*P6`n>oyHdj`;)ja}pvK=8q^DIwwo6e#M56E<23AzRm zk$%%mzVlxB3^PVQ%8>jinHZRw{1!+>6k;fWQOy2g*i}w`MSjIy@l=j|6Gu0iO9qTt z7;MwLgPS=++C1WtAGeOU+Gm1;hduYe88i+5E6j>5S%$%^!D|{xPuxXi#~JJZjC_I3 zfRDOc(yg?8&5B9n$vz}7863j60Ox89nIne|K@T$GKqZFUX0Gm9yM8m*p>ZV`%bU+q z{?6WcYPMSm?0cN~cP`NLQ!-!#ZVw*Kb_DY2pdKC^u!aFj8}IdcOPEcaWlM#I&78}5 zX-8IZz?uEorHh<;PWdXArLO^IMaHEV$MQ7ftm=0Kj`)xW`GG!VKkqyTxbms;8o`d3 z*nNyON@eh@{9Nzf<;#$g3nQc*3RT5(OU3NyKf%C_&Oyj4^xs|)xWbiU80{M8GZ>)q zL?cr^+V9I3`yDW3K*WB}!MaP#makm5lD2l1K>_4y=1P0zxJ%i|Bm7)CP5*l3d^>jP zWIM;6{3l<2vHg(`JivAaTz8-E9pwhn%Ktr#Y09TAKX$(^)xx@m5wL&82VIbMCqJiBJ3vMm@9q(R=Lx*39%=Q7qd+xobty!}YqkT^X z747Fdo8}k;Am=!oZp$sVq%CvXz`p1Av3=xGyAtXy<-`g(S0H%niv6Aau(xhZp=Y_W z#Y25Ja3cOv`efTj+d=EO1M%s1sr&v*zo0A_4i5D=brD%xM6{2t2_CA0Ran6q+!=JI`>d@X>asz51&;+QH@P)d2`)xbgc2;nF^~t?l ziN_!eu&(wqU7KVF<}$bdx?cW4@m=uq9c$QEgXdCGmg+F-zKjC1@T-%G2&S}b7b(BI zSK%p8es?8i2&8Bc!K({6LTM>i1M5{R>Am9x;@~!HNF$I2jynQzsSpCj4bKo{r6^HP z4>;F z9995!K#9MU;PMGcMR!Fj8htm-PH%+?YZPPWFL)}uY4AL zJzT>|9*y(WFbOx(wNBnh=(YaWeiuMBTNsc-gy^}(?=H#oP#QsGD)fzkbkK!oKZpsXjhEPvnRK^{9J_$ z{WOY>{t>4zPmakvX*U-nJNV~i@RNSysX&hgF^n+qv4{l^-}1^jBD{y&Y-V<1hW&`P zhsIZtxXkI>CaA*W)&ge{C$n6bMXMOyfQiAMqRX^R4;RkyI(!ab6&88|<&QKE@IxfO zh4jy|lU8SQF0%#08R|7CgM0Vxjnc4|rSlrxDvR!=*E##HLFO`Q6@>5vq*ZU(PT&j% z@W!hdx1n5fueJ&ngFq;IlH)*+=OTzBgG%^W?#7dF_d}b8%BM1#CHfSOw3oy8|KsjW zfIYvi`p(*c-P7xkjuo-t@A=*T`@dGVY=ToY z^6$O>?{}AT&pr3tbC+}1B*s?~IC9r8f+J4~qTr1$&|^W2Q`t0s(pe&a@hY=+i0x$5 z%tq1JktYsbQdKy8^COOmQ$i}D&?=nXfzsW46UDtf0+2 ztn%h}?S{44XMDzUDX1UMo%cXN&lYfYi~$nwB&Td6+JvPYNnFOQvfCv}I?7FD-?AVJ zj5mXnxJ7vfyz*DY5;$;N09N=6>cCg)#;w%L|Kg*cYL7qje7o+N9Z|5CGx+d>f8j51 zFy>5KziAt@m#5pwW7BOl%F9X=x+N%m=b15186zII)iPg6I#B*rqO@}+N>f04xaItacDe)>xbKc!^hjE^{mdA9}dXl z3O$uq$fQZ7(3@~9&TemD+uy7EnEmGLgn9C5Id$$bwqm3%Hm&r1QdS{yIcZ#ha%;Qn zRy?=4IiSCa{pha#F#jjHLUGkfRuZsEz}_Q_j3UVddC^}-rv>sjqX zyvm*D4tQO&u3<=KJU_@Zp>-MbzB&a`W<+ueR(_YYEMF#rNx zu5!Ea#=Ttacynm_+#meDcYS9Y-WllfIq=#64k13!4jnj@vS(a#DE$sltp$&YyjRa< z3zaN_Px4H5t>RpQ<+QnOkF@ReYv0FqH~9{bEsn6hMN<~LZoPr5kTp{wSP|(53^d5&VWd2GM~oi7+(?E-<@c(j;1$ohv{Bh*eN??&sqOCaLM2{ShC}4@s*n4H8 z$KvquO&)`|Ko4it-vKjVFw=|kEUEcGTbO&Il2Zj{u)SvL(AkeIm;fVXr9c&e#x^U0E%Du~p9lTJf_bGl{ zY_Gj~sO{hX8V>LtrS~Get)3Ucb^cZyMhZn^aci%qLkc1>*oTk)rYj9Lbl6!*BTR#< z(k{>K1ia3kLl3%hPpfy>nh!mHJPp@;b#Jt8b}|gB-88z)+7s?wLT~5a*`%C^Ox{m% zg^;wkm(J}6E(f&}XNS@}x3iHw*UT`Q*UE*n8IH<0n-t}qG}-ycHU`Yeot|XV%Htnk7`VdvXZoK20hh3|gneQhfTRz1s>k;fi;j5>g8o9Or-JAS-< z;9I__-E{NK?P~VBx_@?x?K`t`$B`e>!2rJKY=TtE*Cm>uf@Tuvn}Pbr%$$$HLaEl z-1vnrohd__i$i5u{Km$=VdRT`qx`}k8eobAPn*kd=9a(@z}B7&Nhc@StIp z`_=1MzE554QSeW{@>2Up|L`BRpZLkY)Na4&miEp&?`r@1r+=m0b>rRK&~TnZ;!aQ& zUuus&`E>Pm?D1T2r?DK~Kro zkng0^Z1iw7GMrm7R?yaSH6J&3ET;}Re*8$=_u4*W2^iZ|+cyUU;GcYO+u%yB)U%Co z1==RAMLfuz_s>4Jlr4Q5plc&CHuN*7UzW3-W#cB#8n~8I^e3|?-^1dbf8hmIoNQ>j zw(LnPo_}HAOgZ+$D+Xg{l_&huzka|{pSz;K+j>%`qS%XP zf)zH)mQKRQT^Z2W!SyaCTE9Ug)Cufi89<5&1VHZ<%h8-+L` zoOD5J71qQO{1pyg=@_0ec83npef=)D1xmcShEEH=Re*H2S`5GtvaE5^xm!WjadfBt z?IV3-&=oFe>QIHLsPT<`KrY^1psV62)*EslyCbPA!7<@Su5WHA`~_3^2#rDcOqxcC zH1CYN^Vjd-*`3}zsyFei{53(H_W=gIcH<2#8p4}_N7~*H_X5G=rb?Tk`5Uq|aRg_u z@R=FFU~+G_T}u`j?zwRx_)63$e~3p*ht zGR6ZhfbbW20}oOV88jbyehCt}ufzvmUbq|DCuPYny66~|N}D_@Ty~JcV#+|206dLD zv~>?OK@DK=A+GqxW$YzL!X=W0=&+7l3@?nJ!#lo3=n#*@1;7a7X1s}dpu4+^B@q#z zXp;!rGJl!}Z|yvCLZ0gBlwt^k#Ge7e$-54$79?;`AFPmH5?tS|^vSP$RBlp*viFPbyfnzP1#WMnahfdG6H7Fh4cJcVrPqt&Hj#Fm= zi!w8b?EUWVeyr`iEBs3$e8sV7AFLxU48^)0 zCOv?pd+-U$P{(-xov z5N)=2K%;|#Dw`@Zwhh*uVm}jkqP_rl2DzC)k)0#l6stX4itQlA9IF>RplsD@lpE?B zS!arrO3jjPJ5;lSxJ4j^sPq)80~IG-tNdfI&o^L8C6grcf=;qyTCbl*#cz|89ozT} zl(1}H1&c5@CK&q}WM&1k>Yhb$|83W`kNo@JYu9j({ZIVZhugcj`t9Aff3f}g zzxj_Gq&M9*v#)(Mv%!anXDx^4nRjO>pYts3fBKoH+ZVrhidpbo?e<%5WuT4I(rLR- zal*Yb=rgBT*~^zyFc|1|8ECWpQ!yMRwg!Z~Y0H6O+kXegk1(j^mXC{=Js8$Oo+S)S zsNCCP%yY=6w*oi-;&zQ!_Hn=bx)tsD7w6mOKC>?~^zVJ&1FZ0ItC@WYSA48&`}V)o z4!rU*C+=?#?;RXFa_kT{%)CZh$@QHKo~hSZ4(%to#XyBxdf)TFH?)s`{NrY2+FG|2 zoo3aLgDtkV=NO=H8-NG=DwJouUKH8MDihmU_^nc}lqelJH;6p8Oqv(Uqd)&jHmKK- z{|We}49syJLhsW@-Ud1e5}w&6NVh-n3)>|zxNY;4CBpfu!9B_}_)Eu8M)@Hl(Wf-W z4n2IU|Arg&ZLSk1KbE8HFI~c6yi2Cq9d~~N*NwJz;s}Q^BY#N;1XwN!E=6NM?Uqm7 zhNlzT?Qfy)*G{o7PQm3jN&TDoT`AZQCV~~@F8y+UTyfn!Q|_~}agJ~SxZ;S$1^TsxSENz&;g>Y{2OjCfI)=p%y6O7WJ+d!~9YHdhKj4oTT!P1|o5nFO zrgU+9a$+2IvG2H#iO@dqj!*bW=)t9e21X;W{M&fwU$Es|JXydabRJmUWiIezh~;5D z%HBX1vYUgpY|H_$tl7CsLr+6lCsqSbZKM)^#*PC0r8Jot6?e&Ul4&^Az=b^ff zE?2sH{3dJYh?uuzfb^&|#)ex440^f=W}RWVb(WWbaXN%&*uP%)rLX4R+dbUBx|Zc? zDx=123@XS==@=a2Kppd5UYbS~XzLkk6qSYLHdf(-r&ueqmXZ2umQ#KWV>+tAGe7Xa zSHIDNQCZ2*Ch0lEb$qjb_$4~FjMzi>D)tX<-@Y}=1zkFLfIFDIQfJ#$JAy~r6#kr+ zEr0o|x=F;^LJiTGQPxSgkp??aDmKb@_D_-zHm6_ zO^Xe^@3Cb5B;tpVD(CsYN(s>W#n=SbPu4X3efLn{!9z*MEJ3UH_bgEcLgKdKQ z_?OY)nfDr0l4BmZ^1>_1(mAD5C_Uzx>5Sr*ayjrpVdWVOTExan@cQr_EZF5-g;+4e zfAGud0@9K83BV{g2C$AdFps2^f?0zRrZ0X$-mw+z!g~lDYJ?#dgI8W-GcJ%+nGmn> zbompIpP!@vIP25Ihn&jVNU|US3Y=zDE8&z0`4~(_ToER|g}4h>(lXS2k+sA#U>+)E z^G0Ne8bb{R5FXwo7Q^s}+c@(CC%!mJkMgk+8J(Ux+wQpSj&|!Uw=i?I0e+loH|)JG zHz~M$*Lr%>dX}4`kT^(pfh`?!YAwrePq9ziRJyPB6z5Y+IsioioUuIg`myZ4_v*%- z8`tH4E<5IsNd8$CEE`zBC6%EQe`&7Aa*b(7i*DU7X$V~LH*!*el0J>86TmMIW0rR! zw0`7YTyZyoxEn}%{PGjOK+vkcGND@(QdJ(yHcFVwkRN;Ug|=?vb`BEV#`dHGh-+B49hU<>mVWrCAu0J+^0Bk-11rjHbf5E!iRD{$lVgkz0ZXU?2#v} z%NZ2RN-Xl%*>vj=mLbaa8+8fbUt|i-sEFReg-puEJdgCDg5YM02RjJr5sppbQoj;fB9cH zb<Jc@}4;5KqFBl*3F8SWc60Ui~&-EiI2?XUmH54H>c z@E6)63@YtGY2R}7j`R^u(Jr84XHaGt19&Gno98fX-K#IZ(w=|jDORz$q#gMrGV|i- z;UjFn;68c}sUx44GbnYAS?nmxly7D56srvmf#b;G*W2qHZZ}Ihyk>EhLB5sb-wOEQ z()t_<$Y7TJ8l`gOl9g@x#OXG}V8C)t=|9hPn4f>}LH2m>gcq|Y@CP!;w3$8h$2h@V zx$tniXP0>?QgV2Zogxz?3C-%p?7K;8BFkz<@qzzjcfH4o3FbDmW#^4rptvPr;*4B@526^CXj zB~q~oAJSI9xRO8o$g}EaCuEf`+I8zr2ht_Rw%6-pQ-7GpxPzYh(*6%H!NC_EI-tFj zzKc)VUI@TDFy~k$Y5ko6dI$m>`EVen!WzcDkKmS3hUei4<%qpCnH=EUi`m%|?aVFb z$U_cCRk3F~(OC{ST+U=rZf7E_{fh}JYx0+pPTZCP%bkVOc!}>V`Y4lcxu^JDSzrb1 z(x~34NMg+KvB&I*(_l#WLC^#n2UoZ%I~5sC^(!}ppj;Iv#UN5QK*eVe-ohiY3U32u zM9!@FlvoY{6Gt3@rxK-r1Pa)Kwpb2sn5qPnNE2WP81&c{>;dIfIJ6Z^#SSs!kF*U= z9X>ST*6kfUDeu9%Xa5S6hGmGW7%>DL2NJG3U*aC;?m56*;ggVpVyJ>Rgj*E6@~l#V zM*_h=8_*%qgHvLOxlrQWZC4;*k@JvW1Q}HdMkkI-(JZ2Gffb^=#A{Iu-Le>Fu}utJ z-rf*zM{vnk42J1>p06;M&@Egf4?~w1!QS{3F zoj)qzAy{z44TmTep~Y9lW-e%~C55_0VuMqg{&k;eneCLRXhxX=R>jw@j3f1voQUk` z^#=A4y5#*Tmfbp%?`ZoO_TbvM+L)c0e}Scf>@PH|jfL?*-#}8nBUUaXq|&CH|Ku6r zM!c8OxCfmW2ZP_jY#h!yyRUDC&egKGGh4{4wqW-^;1_8(22U z^)DzT)+cskt5&hj8Bh;#Y75tlD$!Z@m0QwhJ(VEv(vB&0mS-b)C{Ha_qq!G)T zI{1=nxhUh$KKFck|2KVO`_te3J?)?U(|^)ld1W7mU2!!P5q{vCzcB}Fo@1~6R?dpB z(+mdKWk*q-*_AF?l3$WY3X%;N^XPu*Q*IrOP|1e@3eUA-8ITt~qre$N#7gU>#gtuxkzb0{lw98hWbbuc4`gAv0NH(g9H^F8Ox zA5Ols*Kn9f zi`A}&f7%y}OygM6GNcdp3mm3buAmp^MOGW|HxEtXcO`~#dtGJ@4nvOY&q$YBvrMmN zs!Xtw%vt+0D1PSoGG+=r=(X|&`oZl=AnQI?4~WY|THY5{s2Q`ePT8f7s;kMM3py4a zQ^1otqql+OpU{>+Q_#yOboREh_g$iZ!;8>nP|f1((eTwJG9Znb)om(f+yyS$4O4h3 zUI!>$;b#4u0eS$OQFk@OH1+r@2F@JdUG5TbaCp>Q;gTM4k@t9H;2+*Bg@;F!yLujBTMYp&bF0emdgrhRwIh1ayYME#Wv3Ot>ycPmg_ z&yg4NEahk1h&WHMGQf;t8U2>+?TM$JVN1_x%KmB&?_0;f|5fdipZR1C0QB~Z6UP`7 zJa?eobkkni+?n>}C!T7PFT)S;Do2k#`c&KZ(!O^1@Ok9zBm;wU?U`o|afkh#?e4qp zX{#qTw}%;^cy<52_U+&PZJaIeI{r^&#o%+#Jk88|%V53-#qQwLeg`G(vpBdj$##VG zoI_!nt%)3T$`yCyR|aS3GkEBs`DDJS?0WE^E14{xmitVgk~t}h;~)S>jCtOYEz$;z9`|ji3sm)Yp-qIE=lNs>C+t_SP}JB^CQ( zZ!z7@SuKIF5^$^#0lOrl%%c8uVbC57)++oo*I1-JLvt{=C%gdskR=2J7wtYeXpgZR zt3oY0jL%15A3bBnk()5xLYSlhhctBBdVB*=w^k5sqtKWQFKHquhOpA$ccdl^XAg$jV@ylc)pR=F@KDrmc^#HaP@eH zNcCS7Bq7SBgM=TKqizV?;TGY!oCO+&{9Y96Vgf3lZr~kd1@=)ix?>+eM&C{c_&WTeG`%?u?$xc~v@X z0Hf67?tbqRoJPNiJKCq1t=qhr*#c&tZMZU1G%!o5$~ZVAMwvCZ60d*CO&Uer{l~p% zhr$>Zr%#rp!L(CMFHG93|0Y+jKq;P~@j`hQ=YT)^%{lnb4w(BzbM+fx?Ne5S1O6Tj z_`5Ok)9Vs&+TeOpzk?ytX~TY=4zryE8**p8ebQkCUN>p<1_9mdXgL_Ga^L}l-abI@ zFH7%L`t^5!#Lj~!0y|r3Ji5DI{{o#AJ2mq80v+>G3yiV&n7HLnI@c;!4!+Q7p<{BC zs{y^2*iHuM!=t2M9*6HjV;Flzb?=zl$S9u(YaZt5OdA0Vh5;@%%)Lw`RPw0cdhpKk z*ay`0A&sM)S%{?YiFim-kEnwfILd+f3bn*pz$pZ&>vb`kYj8t2l`Fw;Oku;Ub$HuB zi`>Rv58(*Fx6{}=e+CMV@UAc@z``a15o-1=4pCIsD~`MhBeaUUKr2Y_YAjj|p70nf z6a7G~r=EI}S-fYM^*Y4N-jS@_SX^bJ(%e_Xj z23&ZU^i(+6JIV)f@u$=HBYJ;P$P$N>ZLP40BSZZQ4W+H)1bQ;v?@EeYu6#N3oT38zH`pHi^Ebm-G3Rg ztqwG<=DY-NLzt(|%nUZ+tl!+H>;YsR9O!l+727CA_!;ZON|YAsCDNmx*R`sg_>|HE z36jY#3Q=TbpcD9bh{&gxIS8%^A^D?nUkcIy1YF5kFHa*yEA1Z<@l<&#GXcVrvcX59 z?{XJj$s{4PNT@bw7$0!ZUOxuHkogN2I1Qfscd%y(3ZsY4y0y&#p5xTH8@Fs8mZ6&~ z{E^n6H!kAPuJUHv^_PF(+qpmf?Z_KmCm7`U{Ns|` z$U&4Fv#o6U^kD`UI6(08&$I_W^F;D_hC>BkdHG2D@*~f*4}bVa+Hd^kueIO#o!?~T z&=fP!$Sm!lit3gvTPQ=WRuv+T#05r<42m51-DUHHj@vQH{8rm zWz>F<1MH>blegIQvrYD^9C!uoY4SSoLl`F*JapKyY+WJ#3XAM($K91L1w(!lXY@D1 zT;PTQ>kI!J)D_lp*C$HiKG0DjQ{~@2knk6|^}^Lb-lpK~1Irn(IY+urai9G;6n#sG z*LS+A!HEH-I{g@hU-{$n_4K?&6?-$n46zeJ1CC&)b4dor@vF?C;23gL!Knw6#%>+Q zMSSDVBeU+^qM2VR+m5^Yjc^Gdt|8VTd*EfGI4L@cNO(T0D zA6efJnLZt+(i0b)D$M1G!w2Wf`COjp!nBybmxt`Gp<%FGYSy_hcIbs~Xu6W;049uC zA(Gy3FJM?~iY&^|0e-RXB|H%3kMLBwBB3DSi-SD!PgMC00%j#`g-+K6P^cOz^FYSE zu=!5HC?et+gcV#xoNie*Zi5wA6hS(oDf1OFGMzZ=RPe8|FJ0LpL5Iu3+3d9S#>E5O zynA-%&Yi*I>FjnECb>#wJ^Kku(Y5pH>;wpnxX2yR(9<3|u%tr+P#UOo4NXd=PL_mE z!u3QXE%Kbb(nM$4bv_5^=Xxero9#SDp5oTsfyF5)J z&z-YI8^aP zFSDjADboJsuXPt|i%YKL5lrOL4#d^_MKq|0pNMrK&nO&e^t zmY0U4%X(gqJbVYn#ZNQ;9JMd$k#WKFbJ_MulrCrO-Jd;$Ja8s{X6A)S+2QNiAKq8) z$>YBx31_0jA1(~}9uy!8z6Fky%mjQ0p3pH1YOsiv-@&eI=@t@n3r!egA|d3Rd);eR zwpJ)?+|1Q&=MTfbIh6ZjZ6o)sFG1PQU~?jX>k&O=gFz6MY|rxh^MCQrGi%Lta_r$| z{RI5-;I|8H?c|E~1Aq2|ZPU(e?WcbBf6Gb{d8d+m)t0U8UH9MLuD|YDmgk>kwZJJ> zg>cv^itnqO6#pD6ZytZ*Nft)1#b({w_RQ1!7<}Tq76ys8ZQtImyY3pUr`t&0F*wb& zmlG)NYnj>K1P30tZg2apKlA5Ujk2!ozV;?=PoV9fP;FrQ&ToJ0Kel`CxwY-tzJcv; zyV?Wq`NsCtmw%nQhJ*eN9BEf^Xx`z2uV{)j*fCbG zJ@CML+P8i1TeD*A^Pm4h`vL=wo)EtlS$y{S7b4?7{KG%YK;x6`U;fKqZr||0x3t5Y z`?KeoYgwv)RaUn-*tCj4IGaPSeRH+MN(S;h;ok$s$*2^Y$l#F4)|dV)YknLr%bcP{uABGiOJGTO1_LsX=jwp;+sIcd5P_{sc*K#iVfo;v-Ey751mewX zI&PgFX%Z%V0P2(RunA9@^QMb)XY6-zJtwP$Jcx1mY6d=ta+-FZP6gMIT4%9Jj|#}a z1xZr$l8$_lMTNUNVAfbvV|a@_Zvn-A#OZ;xvf5u&RA%lR1=&Xd$o{4tWcU_zKo(y3 zDLkW$3v7qfG6Y@-v5?VbI^Gp_s4#ob0p1FZfuj)?u~`Y(VI4gYr1%WT${YwH7<>X= zl;TD_>1^XFM5m!sV}%pq5=vj2JbewQFeA>uSYYB2xWtHQ>^l_1#4`il=BX-~EkaSTGOHi$3FNSmf~r zOJqvs{1$LQ zQcODq(&v&<6;A6KXOK6{Y#@G5%01rJuU(%RedVr;R0iZgna)ooF!3jnyrjGGC)I(` z4;>^sW&(FyCUfBtaB#pw{-!>`Dg4kE_f?G2ALB%Cm!5g3l#kcp zItfU${=^YPMYCqyBG(!_VFRob#f?CAB78cGjkS-Rf-FVFY#r@62boo(3d$EGE{#vT zz&L>7fQp?I;f+J(-#jpV&YVrq;nA#27@vPVymtM}duIn+y9#8l<3c!b;-KR;(x<&}eP4!G!S*a1_ebD&SRq%rwoeVvpH z*z>7$jNH3_VN0F>7FxkkzDev5cs1K5Kq6i0G`}1bgczfp=!sPQ8bB<4*A6rp9y&#`p?TIux9E;*CgW)-BVHB}ar6%Ry|R+S#N zGkI{DhnuOGxwU-;<^C*6hT8#D;K%D&$uVqJC_rl|C02mco51>A;uZtG_4vhZx(HW; z0hYbNJL$vP?L8O{*1HJ@OuT)Gx5JE36#iI&sW8|w`XX=~3tAj0z`7MG`6%mGta3d( zeM;I}FyiI`sq%M%a~V9-;t1vA0#^@mZ5#vO%RQu!{m>2;Qp+TsesJwP?e2g0#K$;n z?z`JgW?v@|9k#S{I2|{=R5RWlc-P(S&wTR-+h^Is{_Hcawzu7~6J>U7yN|0YEq$n$ z#TZC+&?mFPtRVRkw_5zqKl{IOwcP%;j@vPoFaUpo!Mev@e6jt_zw^`Wo%h|_CKyDx zm_s4uxdVP)yUL0(FiR;D%kAhiHh6RfW%9X~4!2MIr_Z)O_x&FNVtISt`@XF`_1J6e zBftDx+?a87d+76zw8x)%s$IQn2mKKy3Am|2K3k6G=HS7FQ|*Npo^5yCc}x4zAN_08 zRlC}wUwV>opUZ&I+!@aEVGsHKgZtZO9{NoC6I_k=_x|4B=YYVS?dN{(XWQHEdN<4V z?+VUrk74D(aoTt5sMil4%DwmNxaQ7VWXvO1S9k!QioOF_uCj1tlI5+RC!t*12Xb3o z`c9-2teN$+=W!<-2=%XaM%c0&L^-l= zqtb8qOqyWNssQB7fj{%+JmvK)1NZZ@n!!mH2t?zQSzCkr>%0^n7qv3 zfpq&bFN{EXb&V20UQtGFksnxddqV_C=wpQ2a+*$ zKf_fF!hBVaL3`X+3II&@uaErSJdV!Gd`F-IjV5a3HXw{wRl*Bt9z`}XRMHj#YkxEN zQNXXEVHEq2oSqgtLRWfv{)c`MTn2W8_ew~<8uuWPkMhMbVdJk{)?Y6lDVr*CbONGa z=x>LIj-E3{)#)j!4dV>F`1Dihv$N%rx^xUt(zkBemWJpsC)%1H9wd_kj=*apmOJTb zq@-&td-H5VT(XvmpT@x_2fs-%2we8&(!4YV1oFzO8}{A+Hb#b7X6_xe-Ot9(Jm@l~ zCF#Shlu`YRVPN{Wd5Ew4NVjEG;ySFsikWfGpabbpiM8pPU~i(Gmt#jc2Y}fmw-k6S z-mzoH=y2HphMEC|@mJoAqc@6?9gy&!#@n#f5r^merJ=Td14cTsm(M(ezAj(F%SRRe zu26?B#eg*0)foqO6vUxH2d7IXeFU|xH!Yr!n*kbP$n1|D34U3T5$J?4k%7xV0G*J! z=axL8(RUxUod&o&3ZYT^K-Pl$B_??=dd7l}+%9JbTmicRVo|)n$4$iPJYNQZLE|q> z_a6))7^Mr@m9O#;QxqzBR<{QfPc1iI^VOFl+M#nM$7of+YWC^sg4-tBozcg(L?Gzi==X zUm_nK3%dXOW*yW*_HMu9_O@p2nr!_z4c#tVz2S!Ib0)^R^&3g+iuTZ#pC;|%0$YeB zz5J=rDYpk+dyOU7>|JF`&PndFfB!c=keSFYv$QsRr!2Va`h1i#S3uY~rVfx0=}o?x zE+R0R{x!nkSx7~h44MaP@ePMd&=N343wbM zIZ!HZqpX5KYE{0ho0QkO6P$8R-r1qoFMJDV=V7%YAyj%Lc=*W;|6(J#{0C(R8rck7_`3|G3=Xb>2Yp_`DPdqmxw5XXJ#~ikJbCX5j!Cw#^%Y#s z+`rD2mwEVlVfq4B<8jR!a$x$zAvRet$06A3*KBP6HixH{ITz-gmJ5%+LPc?ZcYj@cJk=)_AvYG|J0wjzy0`6 z{1`WE>`K{ONgcC>^Kdq9-OlOw2ifO8(VltjNc$YK_-og%X&-q1d)tS9?8n+W-}%ne zOD8z=bDG2b+_!&(0m{RN52qZiq2(l$dFWk5MC<)2kGoF!o$;6RK6@7a1tSyDQ(s)w|tzQE1)*tDjsQI;I&GEDkZ zLs_W0HbO-__Qfhb%Y%5VTiwbhe(MIG!Ut`(WzN=nNFXCF4%E>3q0Zno3s%m2{BvL8 zKuyXXcl>$S??txSoIyVOipAca>~RJ8*U9Uxr`V?^peo>NgBDq4dzSW3$G9%WCSmC$B`gbBD`({hSyP^HU-(+FGs`;9^=vdaHUf5>>=-GpR_YY_5O0O=a!(KF zx#5Nz(g}QwgW^2(+`VO6+1KZu>{nlXjQ|(8n--a;jc{4^lJm>jJMMWKOX$~UwAxwX zmtJ~_1KrqXN5-#Vw$E!~guP%#jEd8NTl3bWGbyh&)) zJGI0#gaaox9jRs%97{TV&{yH@#KI@inU0^3fv-%`4Enf5*@B1CX3%hBj+gXX@TYU4xUpvCiY$-STcV5`3c7Vb?gD$(1KjNwSlvwfi zDjy>Z?-I5KYMf~>t;VU@DK;<%Ru-fljgko=;O}(dmB&2kPwMDy`6GRM?OHN#P~*`x zOp%F~eab@~g^DC(0k9~OC*CJsO35@z$JFF%4q$RN&2mHjkzDzTD&HoTtfHLEAP?q8 z$=pf~n|to5C);iYtLy;I(FqFwiOLSV`&m6}LPd85h4)C!c{;$z z`Z@X<-r8{^_09D+!l&Qj_sDnO~C(46k-yFEr0E(c~c6ij~%nwK~Z% zVI5&cWn5-@C#H}Gwj9_7QdVrkH?SoAByHrf71YP< zHyWf_3{ty3W`|%IHx7~C59mL5Yt+dnbrFPJ3j%(#y388F~8ExsBUG1vt zxa#t?{m3fqILq!gaT5J6efHV*i(mY?_RedrZrAPD+O}=rT0IAY`E#Irg6$;B;oVZU zSgs`{|$lvG#4>`o4D6_NypwtOhtW-=2Ez6%K`+Z0j~% z-3}e+W}eqiw!2B&KmXWgI2T}B&JftWb9>v$`2Y@vonWBxD1-LGfx~Egl$Y}P! zqwu2izPkT4wnDsyT%1RNUz_tXRx{ACe#55J)t>Q{ zKl8`_f;ZpT?w{f63FRO%cEQzv*2^Wck!eK(fG&f=D%bWCQlDs6*(b5eNZhCk%(n~@ z=x1BSU%BBv)EC;tWmyr{6^N@>(@&t>pQX%Mx6Ci$>cr)ofIq*Yy$0XTa)trJ5>>}F zxAU=eh(WuEG_S~d>Sqc6`gz`ZiaoqfrVM#dW;1)ty;ojB4!}AoWaCdNxdFB+JOPFP z9dP6{Rw)LpaERX+&V`UV@*9QiKn5KAjAw8zOx2lGh|@V9Dtd|#VQ83qM))vSpg6~9 z!;659DsDU2NpufZ#qaWHI(@(n35u+z5Q)8q8jNF~_;!#XK~?xd)j&^m%Ep3yO^wwM zReZ&mfuQiK(k3tBI-X%)fr_q>UOtGtmR}+<@4f=ED|io7h3wuD3&tS{qhLu3U~d-B zrC~;a7YvI)2Ao|E6Ym1(l}(+7MaWD-Rq};L&jKvPYYZLCD&FDm|A=`iCyvnaWro62 zt(|>etzu87&^_8-Q+5G`L!2IRbPm079i!OWxZcg#M@Mg;d+xa?_ERk7%SqLA(mb_U zh0Zc^^^P5Z^$@unln31#Su*I1jEAcU)0IjUA(eNpsBwS2oxDRR24|tc5%PWe_M_BK zS7TuZjI^i>q{EUV7n3TV2Yz%`#9HNkRBrJzY$?6fQO%O}uv3|{953+9QR}rRF1O!y zYewd0&zz=#a~V6G>^ZLAVYcDAYp)~i)>YN09c86~_xdItXCcP(v73oR+?79=Ek6-H zM#&xEz+=TqJC@R0OZzL`D(v<-rL!7hXLnugAaDHHIbKQw>w}R-m%#|kcJ>?q@UihX zPHD`50JN__Q3zkHoWzyRfc2wP`18XT@1obla7r_BaGVpG&#+|AnHwq7#~=k)mdGSN zc1m==^clGn+DpC5-hl>k;yAzuCk)=DyXpz3r}c^DVcuk8yuHIh8W7m3^}= zNq-y5LD#U~_}_l)Kd}6EGoAFBT}j@cXaI^pb-$T}fek}yOcyZ^iLXzkQ*M}^dKQPO zx?~8{Apj{n6+V2Seo(PIew4ke#TTn@RvGBM+8~+J}AVg?}7JVLKPzj3nQh+d+8Ji~Qz^JAForRMRD=muyobir@A5qO3kkuU7$gqp-|qs z>l)hE>Gt!#`rGY&x8FwIvuft>X|9x;ru{h00e8naw3hIbTiXYAt!f|t^q0BA{z(*5 zlwIV=`|BqeY+H*WyPOpk4%8_nlN^dSN8fnGiuG+Rf8J_vnzr$#t=F{aBZt~+&mU~l zuTQsUsVj}s`g9d$8Z4CYS(JMQmmMr%N&T`FQ|&ZYt9c^+XP9|E`QQIf?Wca~ziE4R zt!dl0t!qE@LqE{o|K4}Er&!hV;tMY&-(9{gKks2u!2>wgtzo+X=x5lIe}Q`Pk;k5H zk3YMwEuY%l&MZ0IR;=05HgBhVvaN2{rup{q|MdF|R9tK?y#NdYk6t5(ZcqEh_BCdt z9n^9)gtyU5!FzA;SjV{_H&OrZMrog#n#^RyNoM(HX1Jo4tbFmMm+8m6f|-LLskRRt zIZl2o=PUxw6R~W9tLhnKnKEv9T}c^HrYTL4AEY=kYTBZZ^NsvP<_actlH%hZX>di5 z+de$g=py|A<$wyJ1ag(8DRZX2+DT+YgabsJW+gQVdI zJefIzQooWFWey~9-i3XZOn89D`p3bPDlfz_s9A~RE&h5-D)#ccvbr)wK~av9`^d(k zNB2wJ27qMfBH$~-ibGUBhFkP#9sE=0={Y9YMO?vT^j`Q8vQ(vp2wnx*YE*CKyb~`} z=uOyB;3Q33#ap=2{th7Vvoh|Opld|_h{lQ~JS@-={nFm~)V+eNzb;!Cfb@SXfX3kO z;r@$!dxUb3r&~uxxe<=&`=-wu^7t~)Vc&QnF9Y*tPKl$_2w8=y9Fm6w)|R$(FqgyS zv36ADi*2z(oZ}=5#vdJxf6UD?b;ajOX(mX*4J-}@DrYP21Q`;gcXcX^0bAlGB(N&< zQ;ZyM=8jkQf4Q8~88fevvl6$_m}hUB%At*k_Z+WeW@HT`;;WgVyy~jW%(R@O;byjo z@TX{myvD|BZdAbEdH;P`mg}j_jzBwmw}E}M&QRK^H&0#u>1qL&Y*`-dn7ABs*VVhC zWZK}nNmnu3=Qtg z8o{qQIwm*XczwJ6dR8ouo(*jse6pi?hE6J{_oCoCJAZ<-yEOD5gA;Z{vn0{Osk)_{pkiRBKuO+S87BrvP6+d-HjFKy7Bbx%iE z-qJ|h*|d`)yr*l2?>6c*+#Yn~46*rO2jdjim)S91pt<54YQDHDN9JLLfmRO9af^k^ z4L5A$1Z0+Ho*>VJqZb~!lkujNM}9BJ=ipYK$Z9vr6!}FGM^7&|MNc^g*C68~ya_b4 zTMLOHfaRcaA^aSfJ6+;5!XCMHUN+JHmj`p6pS-YV+oH9k^6vTxz`%nL5Y1+v!s? z?dqL7G8^OI+iLdOu4ko7lqK?1I*T=OMSA;Jn#ngnl$FlFAyxSG^cS4(I8i2w9r~Ao zrb)MQ7qA}X&+>iM#;Nu&_g~+B=N;|aKJ+2>q~6X-o=qA2^IAm@#Bxi{BzvXhVP=Pr zRm;~TX*$Zj;G;(lQ%9_0R*1W{k)^Z1dsx^D&p*#y?d#jM*X(Hzz5ZyeSRmah_kAyU zI6%Te=O|sK89IA{{rU)GW#8T7s9QM;Ajral{Ls0k)+wKkCkTY<4)v85B|b{Ab)CxM z!2eSC$PnFeD>*gd3ajEPI;~Yc%-_L|n|&3P`&Db49b3{)Q9qwS9=S&>+hkG@W3dJ&bAHfAStdf3+S}LA+NH=Ec zktm?1L(WjnlM2FB+9lXJL_Y_K0V3>nrd>sB#y@2V*WC|pUkf-MNH2C)2?ZU;uGj5BK~Lu*9`xRNMS6lyiZ zEMFHC`{F;bChp|Z5Do`DD=p9#Wh{0uS|1yMG@FV1Yu8woLQ;9F8~81tJo;EpgDOOc zhabGQj+VdX6`7TCbB4h$9|uXi3eQu@jYCEARH-- znuGdgX5C@{bC!CYA!qGeWRE}l;g1|Y+-}&-3ZEUD+JldL3EU{p^iOu}-qRjMA^-3G z&Oc~B{kQ&7yYsedP=2{R~!#;TfZn=AwZ3ENPE9X(9A7wkxgO5DP z9{#iK)dNR4b)PzH2?Hfl>ye|AOkix}PWFTCw|?sr?e05oWuN_aWNInf77nAN(+;B? z`!lC6xT1s@wr$_RUQ=iOgMi2j8w{Z)T6Rc+9&i9x1 z9nJua@^1e|y4?boTP)zM^5Am*J|JhitSs1Hadn1+3T|QPg95s5U=YSxdLQBa=}&Jf z;av8gvy6x@1BHaKpJhMAe&8x*=as>NVU-~Di-XNB#h>9C!Z`-p5Jd*=H@4T0&9#Rf zegeKywwJ8|hV6;)X`a=9bM*UGQrF9!402Nbr9Fv~xZyF4$*jTtR{Ojq75mZ51>8>M zY!+BURc?&(z`Ezn9y52*LjZ$}Dpozmag^r}WZdHlB9K}WVWz^%V}v6dWeG?sVZ4Ad zJpl@FnE4;ksn=lBSaed12f<9(0Q2&{kQ*qWI8_6-C3_7|=~(q?(gYRq%n?#*$k1cAfH6T$WUNVk+7Q zOL31gV|PoI&>mpFpUd^dZwLMa9sFa*7~$o*x|LkKynLdTe7gkA0RjgM9Pw6hau!E7 z!>SMoKg)K26Q{nAhEe)WSEUKEQa~VKV1D^^#@BZMNtkr7$8+Dh!@vTG!z5!@*>#pg zXZI320&l~2j@kOvs~t_RrThj}fw@2jVuINes|p)l(Wv;s+#+Il>mH=}#5NFb>~l_S8tyD#2qjgXsE4&0<(dG zp!|Ay@=oI|DB>@?_#(4JFEEHQ$E+471S78waP8TBJ%>IXZ{Yp4}%== z=O*@@fB8#~im=^%&%Ind<%|x4D{Gkr;n1st2VLrEXU~BImrXN3L!ZvA5l4?5raUa= z)cMJFoKB`smu1s6%9qeD;mV!mM2CSd0%0%P;D+z$iC^)d@@!y$IQXx@B%npZ$0fPz z*)RJ0k380{r4xJiU3X^i>kD7_0#``A6h-ox=bq(YrP|J7$JNL5Ie2BAbMVmN_NyQH z2zzB!9A?^DX22X6nPC5F6l1o$WKT7ndpnL6DU(*zlY>2@22vA&X55qZOWh4=nIC_G z48UUIxDU{_Z$3d(a+05QnqPJ*NX^MJ^JtXda%(WZaamA#Fmzi^z(g#>sCeNka1{ zT|qct@+02{UzsC9!qp>k@lsaIJ7}FMsqCZR^GzZN=mU_R@15DfP-}>X9i9Vf5;#P94X&ju z4_|>2j^<81b`nzT3s4@NNuF>}oBT(vrlOC@< ze1#*H8xqWZ`y=hiC!fr|c@NLq$n|?(!MBMs4|eU^$$;fi_V6Fdq>0=0&M;WzIYq8m zQt4j3dM=7|4cL!jUY9X&tWqwlKY|q;X6xOY z^&Q+80;VK4xrrJKXMST8?kF_VBd6`ue zwpDJYL?;F~K}hn5J)QnB|0@|s;r<9=F2$u>CHQ3smw(lnTpTL$K%mfU_y}^a z#L>Nzb^r|T;Vhe&Ro%92OJ-;Hz4~f8cXsd$=1iFfyR4)_ceMA+JohToklV<(AKrb! zJGO6Qi5u4~(aAXQ8V&N1BW=fy?fiDOg9i@L(Xg{YXN`4dD(h*`fK@5-lw&(bOHp>5 zDRETVCB{8%-a-4~;TJQLtWv+E9j}9KSjxZewS$DWgEMrJQ&33#P;mYDyHw6>%q;JA zG@Ln29W%yXja^YM&X&CE?qOce!mB{9VVT_#W*676yl?N`YoUcDX=53q4G9KO3*oAamCVRz%8m7`3J+l&7_p;t zoV}UKf;>2O!fThdB`;jHU`P8DOJOZX-pMU*9RSNiTgd9<2N_U!EGbh^xMJ73E0MP|1;2hD$Hd!r~Og(d4@y_E@_Xn}>db?{pp zz`&z@;Z?A*NcW@}=#&@Xe99xdupDY#4NcYsDp*(1solD1Lk0j1|H)5%x_$l&59cmx zXTRJd?VyDn)Ok9B9*DUVd2$6}04n7(9Nc6*F@s`<;7J(i zGS7y3U{U_*Emb@wB>X9>Z)KoA@$Qx(NW#R-%ixvZO1I`Axbi)Ej4yFoPNh$!9QrVi zco!IDXplASgG>ic!eioVhutSKZhSqh!Y3Sfh<_;wkO#)mXa2mIVuCna?hgA<>ZL~< z3^=kTS*1ey6b(JBgDuaY6`aDmVl|2s<%9ajdSey$)Vm#PDTAl3E>Iz?RR`?vrS5WIW0k85 zpwo84ddGIgav+Y{K0v(MDKlAJ0D-v%k2vLDr2vvbRVTfdj=??rsWg_+_h2&dF(=XC zzdTL-5)fX%*xxJ}6&$yKyOoT%WY9nfH9GdfXrH#xkN%JUZ`(A*HV2e=g0(5y zFIUH0M4_eCVyQmy!K(=d3ASwGP(7CQD^G6SvwfUr<;6t?+R)n}mq8Q;TrP6@z5;Nb zGA-R9A2~h0)V!emzsSHpyje!RUbK&4Oz`3q=PP{X@#Btyx5l+~?|xuQ`(OU*ijX8q0YC8gxkCT-okrLAYCzBO(GVw=S4 ztnOUOKKl!##WRPNGBC5m{06V9NIdk?I31`kuZ=GCXc-bW)C}LZ=I1S=*qadxtR^!e zY;_Qp%QvYD0-)fVVb$nh#$LkLGpO5bbPA_10GYe>4XB>L;#cvCv0$_dTF+uzht{v7 z6LnRfDleE3?!h;-Rov23xGJ1)9t(v}=%d=<8(cDA#1Ye^;0kNi6iQPUhfjkW0QkEs zZQv0o3JdP_4<3C*BWz6C>X8PYcu5CloODg`z@E56qk#1km^6-ar~6*vJK(;8@8B$u zPp4&!-p-5ATogh;V2k1ev~&-KD}SW>a!;bToW~_@6}<9f-0RZtJvG8y8l(1c|8Bl4 zY29-?vT^ema^(Z59QS=wv+%a@RUKXu(I7jz7RKsm4FVHa(`+NFlHdsL9J78ZFuGF@ zr($=e?R8FfJ;mv|b9APBT`aUu(UqRuOQah)WX5)j zeQxdm4fYNcR!{k5HXJ-v4&*?U)y@e!Khkeqlj0AA%CK%FUxXyQX5IUfGA(^+qzAqa zaE@Ht$+Z)8jI#mkJe`_8-gfM~f#qhk{QPxB?H#%I+>R~W^_wf3P+(Mui^hRw=nZ3V zP2On@5tduMyq;&4>vPt#lzB_8`t!g*2UX5E5{{p|^#DIRxGF?Mn!R`~b3P6-NAxqw zPYkYnaDd?c``^W(Kd;jHIK@&;Pvl*i)fFc%o2HOGCbnYU{GU4A@Iy}xCICxZ2Z#}#?ohEv5l@M->N=VrVguxQ+3H_kYQxj z%<&e9d9FpW)1sKT$9OY$GQa%tE6hy4%<_1zXI#Pz*fh&I*Ky+aOnx=XRf_#O4w1Ao z=6M8mlwUt|psi+BTDg_?odv*7ns_~cZlSFspgq8pg^((H zWLz;_yyTS;gy-5xk93%>(M+WEigskp&Z>%6?T3^vOPIWyK?(B;EtNn!w8|`}l_PIQ z=*&Lw_Pg5K-+oWFDYzX(8FgUL`p2cJAN}Y@*(d)p^_u*pvxidQ0EWtAE&Ws`PqdqF zx~aYM-gmT5eex6ScRulPl$Z?+JZ)^JSW3Hu*}a6!X9*pgmr_3% zN_h-!%PaD55d~0%$#Dnk-DQ-GmE59m_B@9IQr;~4%NbOT^5&`R$e3-(>eXvFC4QRv zjl%>{{yaEPf~5tWjM$~m`T$vWKtVbNT7(JBI=I3hNv?Dk-62xqh?n|@@U~kRVlQ{R zNo%gAG_~TC&jwAM;w&}s4m25`WjJSsLr<_Vzv7+MaDJM_;jyyVei4DWbUfw%zUQi9>LESID0t-PU2AX8tV?+|_>J z@BfwdpMLK__`SNl{OY0hWoBJZq3mv$+R93qNqB8;5|p$~uHoRf3(IKtj!@6ev^5*t z9_9g-@PK+yTHQZyotf)6J7Y^Qa2sZnhdQ`#-Ec+50k-FT>$~r4Kl?KuXv^kLwl(Cl zGw!=~ZZp~K#r?gKcsUR zGx_uI>O3p3Ox$t?oX%oa?reiyJvGm4^pL!`!-%0QG7t;jREn46u6O%jOW9VynL;OM ztC7m&#f2 zT7UNf2cWW63cI0r(j-(L#WGaoqU2i~wJHU;CCDA+Vm}i%7cLxwF64q609G<-aGr8t z{FZZzx$W0-;#rMsou1}eN*J=rJ_-Xv7fF``%qbHg06zJR!$4Eq-#V{qb^d=&uYxgp zs8p)DE?1X2**RzKCxza;7)%5arr;`%D)WL%XES_c(NH!`W~X6%#HSoqC5uDyS|Kk= z2Iv7^fiFzyU<~04#)^qbeDLql1wWCcBWi>^z41&`gI#mN0&C3m4Bs>um2%@shl#h4 z{V5Z|Y-be5nnlsKu%&}Q$7bOHss|4PyALqB+a~f9$U-<{UvQ6+*El8J?Q8Qb>U*4* z#9kQ(jpOw7L{&a@Di&P33;qO4(l6(^0QMD3Jzo}sNm1&z1=1D+3^vU4>aZWs!IkDO5P$SJ9gh8ukN$qPFbvoy#m z(JJ%its~6Ntvi44CwhC$q?jN`?Dh zyX=IGl@-YYUju6sFR#T9D90aZlVR4g%9w%Wl5!xZdu!=Zrh{ew0swdq&!JT%xbyTZ zGcm59FmECo;Iy-*xs*dY(;NzkQV|J&p`DMJ#Yk)@!$cwlUNxq|?aA$)N8q*vqtBo~ zWL?GCPAy71e0LB{nRhjY3U#NSIk@aGKgJ&OdG6;HcU_AIHquCnv+q&lxrrdou7n{S zvY(fOM|RBWlya4ea+epGb%l4%s95$?s&&t566KW2MVM^Wpp$0j&H)hnVh|p)<nw*=b~pCBxwx(cgdn{cY#2tJ|;q^MA!bTPKj?^>k(}Z*-^J zPb`hl6~^;XHWp+HyHDH%v{b_|{|6wF&65}J0gpl@(AXzP1Kjb0PrM@--L-*5IL+a6 z0q7T*BF*AXSt~+fmlvHjL*x;~2&Oyw1rze)a(knydd3dCGKDY5U0x59L126Wfy~N6 znl+y-zr-u8`lZm=(U4Z{{D!2Mrb<_0FTX&Vj~aaODS?bU#laWx`KQubu(*lW4!%Bw zQTEcugYM-hpBE^r*0W5lrp{lcYu3F7N2KC_@2F+A_ z9rThnu2x9hOvIsqFqTE@hVTM+;jF_=pR!nkHns^;S4peX38x*p`JG4e6ka^0WR$qz zBOcR4_{cYA751!#z%6luT{)JXB^k&#(_TLCO7OEDhc?#3N8M(@VCnhkww5git2w2f z%x$k8IoN*WJKsxNe7^n0zx!C*%>eNAS6|bv-MWf$bh3T#cYOn=yYB`sH%ri_nl|ek z2j*A8yZ79Cb9?W5?m|IBd4BmIgJ*xxPM=xUzVM|N+UwKD7&u|I5n;~3msxncVkJwl zr>OhSvy9yBc+~MLsB^4?a+U+KqwHlhhfLzhI~B6^pWG+eaw<%O76P1bl7KBmx81fb zXV$nuM+t~X42K#GcO!# z4?p>dwuQ3<)=hbTJOk3MLLkmFXqYq1;GadooMnJ8Tib}I=P?-$ZfCU_#OLb0rL=h$ znSFNV-7^XN+F!BoDjU|1)?+DK$Us)3SSKk-#xAS5^30LyBl+m>9( zq3X9*zpa>nBfKdZq4_QPyd@NSg?urK%jVmqBIy_?P!X6as$|(4LR~qJ-VAo|BQi}3 zk42#JKf=7=5t)z_#n?x2O2r|K2=7R^hcHzP3cCU>OkeIMbYUpqaT*eTFGLi?z)^S- zbL?>%F|VlUR$?XWIBqP18!(lC#RvrO2_h*gjG+T(zy0ZPbvMcCZXM=p_Z={g(nGBL zn}jRJI^@YBsxL>;*MMs2Dq`LkK_~qZANh9KnDzK$KE)Q^1FppN$HM!@zzZ%5au!7u z+EoypX-lPU-79~nWu?oGp$h%%8cx8s14JWomXq#v^F&!Y?7}!J?991WmsnY+VWWkz z^R05@EP?y+*Kpm^3GS)2jGbUPt;IsQ&%s70m{E3(+sJWuupn_bkbvC|m4gTF?N(`U z7H}G~d(t+rN7=n?);}&u?@QdlBr^W$N%DN?0 zP=?$~`}EUKx4Z7TyIsZ7%2)Qi#6HFC?Zp>g0Nz<6XDu8kP!8lnk*1>S(n1x-De~9V z0-5Da=U907XU8O+5O5H`9dCn+M_TQ0XHWGgU+|0!R2)67!FI)uJhl^Le6|Q~L$I^F z3E6P4!8XYO2x)bxs;dS(P)huEB9)o5@TyKrCVv>zP#JgdgI){qst}>r!+YgYT;>)1 z65^vPNm{C|w$snvNc_D5$@JAK7u%fbT-m>IMp}6?{&{A3TtT7I?+Mnmf`IcSh}%8F zDmKml+Q!-mOdb%gaDC8A9{0f_nG{%Pu&YNDkr`!Jn=`Xg-b;q^5IUWcR8mPhTcZl?>9eiW9ESIwK`bbl$T4KxLjz>(dYYUTYiov}>>1N!fAG1fEd_ z%!hX9WNwXcK+jboPdxcl+E!P3Jp0nVcGHbFwHt1_Iop2@qolji#eB3LagfSEm>t`; za^icry~GL9%J@6(znAkmZf*baH~wAw6yr{lk;c2=V=h7p2M%_; zdz||FBouKZ8Q4rm+^w>d3+n;g(kU;Wk$gIMv;a@oWAjoC2DX|VAv-bs0RFTlZ+ zgsGT|HwA}_yw72H;m|@@XzO)Q#88fcxG$sEntBTPvMi(Thla>DaLR+}o2I3*a{0%%9k{-FN93XFGc=2qM7lbKgE8HktDf_~aChB{6Z#dhC$mkHJcw=4R ziU`X(v$x#!zH{rQcHf=XpopGrr(B`MVQ!u;aGpAB$)JK4s=xh3y^ z|2MSvy>oZ_u5W!$``zFAUCQi!%GTPpiTmNVZCT1795=JfoNAAJ>5=yQv(IKZxXPn< z&!44ky6>IuX}kAa+iu*mwH>&5Pdh%hlJ=GX^@pEptC($e3!QD2u<~^??Zx!z6RgfV zR=lOms??jGNi)pxZ(y6kRc5E&hgsUx-PYrl4dnM4?vMZUAAF(Ruxm^EhWl=3djR{* zY4^P@cNe$s+;;Ph_Uto{w`X5|v8`OUgPGqo?E-^1&X_YgMI8jctp}`cFHE!zz^t<_ zf|i+6=U9Tz0e;lg7Z`}NtfbDOu8+(|sC(W>w}bqZXRcbgaFP07+RguE)HkHn8U2e4 zmROgnaLXA0yAYA88bGNcg&ZJfHUs=CLHsnyFL3DsP0E9$SO=u`Cb~EPOK@T^E+<}m z3@C5!`T`I@fO*>SD796)n0Dgy;zNMVjFkpu~A8&Bjr&C2-)Y1G^AzJhGyx`z=stJQlL@>HeS##w+o( z{QoHLR185+T%A2*X&lE@JXlQ2xc}G6+$*`SCZ;#Q=+M*AJ-hvnOJFgeWFs>5M?~1e zgwc_nL44kXK;@Hkbe<^hSsJE0Ka~sK05HQ!$61Aa%^KYBbA)xyagWZkd&A~eqE0^ba>Z>z|-hV1f?daH1SVBXr@~7bF zCT&y91bZ^RYQk|2v+=hM<@jCBFcY6;!_$vdv|Q?blG#xk326u}!Wl;&pu?D_v%YM- zoFKFDFogV&CA@farcVYgVEtm(M}Oo^R`8MEiPcE@yP&npe9%3GcRcaSGuY4NGL$4@3pJz+!xw zXXv=ivafFid72bKYmLmyb2=Wt+KJz{Zy$>6RMO>Ef~$94-EO)0<}AxU&i=mjDF5b# zkMiMCf5WMaIw0fWZr1%SLAQpPM=tENJ78eLZ$8bS^vf~%l{%L2(&P!s-*bIug2hrI%HiK0Dm6Hi%^!RIB+q7;gSLyZ_a^9fB5hh$?ply2RP1> zRc>^+xRPa*OCrmzwy|6tK&jZXdsq7_|HuE+_H&lTKmGMzZ`(I*P8>^67Tou{YR@M4 zxu0422il+h&hKasfANbsgh~0o^Nu^ClpWw4icK6UweR3D>KG4vbB4&}_~+Yp2C%;S zyS}4s`Tw|k^Jq=4t3LD8aBtn3hg)-%N;PRH$+9fTk_Q<(lSUtGG5JGHY48g&pWZ4)QOSWXqQ_b^qtLomGtNM9<`+dLr zRkxTkeDU*CS_XIE1O|6hCX z;YZnbzoeZeZy8WpX`#Bpf^-UTeeh8}`WYgQ<(&_1<;cVL3RO;Zj|*kq*NwCd2`l(6 za=`jN{Vlu_?r|G9``-QH-@_<3gPC3*VHz8Kynx!}sd&Oce7R|?YSfuEXstrYGIt?^ zbu;x-{!M(pi35N0Qc!uX0Xg5)uk;nbjUuuTs_?wK%0xIgc;~5bBUOAi*FMWHVGSBQ z2v;uzsCrf7B!Lp2I4YJD>eIFZX&&xVD2PvK&jr4A3zjD%Tm(nklndbEijW)$N?7+d z+i#ey+3^2-+G6XNd&8wy@FSf8p5oeFRhHHMiXVaUpPMt6@|JWmk9u?YNME8`?`L^9 zoTN?{U5bv@p)6}Al5K|NV>!*BuFs?I`_eOe+K>IM``Y_|@a{&p!ZB|rSrX650K_{z z<#DtK>F92M@1vh+pLy`%cGt!w?e~83|7o{g{|oJnw{2}J7mc)!eB`5T^4Q^a>*j6k zx-}Ri1V0tA6VxGB13mZbGualSLi9L$qtD~_fxq>`Z2@#$F`rccdv|lDI{T=XplBoy zXKA+-YAxXrw$r%9YJ@&y0R%XGVk+C~#+YrF5YpK;)3O{~VFtgTJp+T#jWGw5z|C<0 ztBkay&I+7=_N%|w9=iRZcJtQjsP{|SrVUHm=B*prU3cBl)@|6*e)ZRWyFK{zeQhm$ z?4|ScO{AldM}^+-4DFZYeEPIXc4%&rjB#enblXsxZc@|`ta;K;As@ve_}E4k2iw;2 z-nT34_Yu>}S)D{40h(1Oj-4tC@Pj--p20_@sI>CGe$@t)LO+QTufm3JI$oh=Pxyo* zSkeT5GE0=IxXha2=tw_-3#RzXbfswVbnzhssc(2E=_CfXpw{8xr>lu!5+{BF4cwqW z@)IS1Jgw5CgD-wA{HLZ81{y#IS|9+C9`tq`6na!r=?|-Z;B9%yAA`$$nA2DO^@6DE95Q={{acOd)u7ry`!xLrEQGB+>N==`K@Ud!jd_#UVoxNjM$ zMQ{J;rFY8Uh{LBU#{gn46T3f5Wgz8a4h+{3_FxT9sB6Ldj%Z2 z3xPmJlQH;ZAX2Zr6AduJS*MA$Lw4}4Cfl-8K+Dp=3{F6)F&qBU+!l@wxHKx`?5P&#_wC<@ zHvU{&etCHWT03oFxs-SNj_vp#WHu1(dGG_q5SdJ+u5zsU-MjJZ$f-;3mjNH&8I%C5 za5cW2koAj>44f5wK%;HsC^D_xo=2F{F2MozM=O-wvh8M$wprTdo_3>>d*siw7hl|- zygHkpTVEf9-q%f^etVT0-#9qf5Uxu~ErS?R!%ci$$)Et3nRK2Sy*rCgXZ>~{(Epj= zoiFTY_k7@WX=Ao**_@d#XS+NX+&$o%Hg7_aaug$H*aYb4BQ5-ik4D-&Km9hWoICS$ zfF=Cr7-+`=HF-SGtcYd25Lk0&jI{}t_51DYtF%)|V19h>^I5s=3*$=H@_VU!(Xf^| zGKaw`ktJ*e(fap1wk=FBTYVG(|MVpM&0xh978f}Wxn=@6+ED{^;Otqx8fm*g8D3&G zY$+=+-1eYlZgEwxapqp0lip(LQ#bQ53H?r>I5>Fd5PV;>Qd!aqJ@TtUe4d>ELbNEa zR7No#p@qcd*Dh~F-F2*t5+bvCGHX z!%w}~-hJP9uv~Uq`@j#qw|)K5N8A7TYropoF^lRlO_e{hQ6_9;#_`klKhW;v%;?RV zHrMPuN;^tF%DAJ@=&N6SIA!3GeU2r{oRi8YjAVtb6EV0a?NwDdm^?(89%tY5EVclx zTC<`ZW1s)R3m%zg&d6W}q<-Wp-{v}35g=t)H(e!42*Zr)8TMdfXU#u4`WJ16qfPfK_9j=4x)us0)TGiQ^CB~FJbbY1~rOPw`|B~)<@40 zSNZAQdKIuEvn_w>v1yu*4sNoP_Dy$Pt6s(5ur>rdBdk{7z%g)U=*ZU~Z~DVqUh-;w zgiBjyp?2{z_%}JV4P1H&&ws-hj|9QhWx&pIB22RUUbC%CmA2y;SW__8$f8Q#_1AA| zhmRbBXHL;Bxl~w%Sk+l)EVIuY8ms7t;Kx%`tasvOdezQ=AHSp?&I){!^R({cmkIa17)#oK2n8M#t{$yAjY&wWZ7Fw&kp{8K*5BVW0lu z=l5dq{CE^7vq$H(nR8|%)T`i?S1}k$8*~ZdZ)fOp6lQb5Gv?Xi%;iUaG2N>;nEZ#5 z@=I-}Vfewa|HZ6AnAiU7@k8y&7be=;RVWtcoI%+-zy073{ZM<&=C$qpANb*R{}ca~ z_8R($!;%7i-@1cZwQZu%*=bVbzyCT>1o9N zslTuaST*1d=Br|+(h$}vl)nE9002M$NklCkr^kXpcV6O=js@pR!*uybgo@Ec>>zY*)1d!~-=^^suRcG+srF

8y(NC~)ln`S~5e#c;q>VK9pDSctKNpP2+N1u%tAJ8Uh& zTYn6zQb6ITADG#(rV}$?=9N77tNIpD-0C}N#A%v%4s;A_$5ZV<@27jg^yxDACGIh& z4cxbHUps~onIp#zGSFlnDDaF&VEck4?oJ4*2+UBJh` z#~&xo;+<+Yv2=Oe`t=Bj&IXs@=Riuj*&-icBRsVbLDu7-G6)Io45S(K zNy~ng!M?AKIjY%zl`U>PIe6ee+dvs@eATV(bD#Z8%0z>cB5NEKLLOna6T^DW+{iC{o#9ilu{l(=+Vq5GcKzrJnSxUucny$|cx+uQOL z<839&(^b+L#<=pb13it8si<&9cMIFCVpE=3spBZrT49|c-~9JAjW;eG zam^#XzQg43#g$h@uDWQ9s;~JrzJUSacYx_V{GAXuf{#K&#qLw+tj0=M!I7R!(4`f44!Cv7)#tAN?$aE26SnXwdPrNL zfK%uOApaF+aTRW*#|M1iFYX<<5*j)e!}7}o^0vcizl>)PZVC`{7A%VL=nVbK31*44 zC*o0QbFnqDZ22mHV0oK%E#*Nh>+@{3jkpKjRc5nQZa^0ThDIhT?yjA&Z>hwpT;wD9 zC;b#Yxo~rfQk01}R9{nwOKUIFb_O|VPzQk!u$G5E(=<gu9)!{&AE`Db6uY(Bf4+n@aL zXWBd8@%C(2dGwLT$?4qo;`95kqjDVDsoeBr4wj^A!k)4_&AIUt6Q@yvo@`G%@oZbS zW-{#`l^K}WN1=@6jNl)|5&1!AHJ>3F?V8(%&e{G`zwN)RpXM=FU#{J!GrJN$bTN=T zG*d-^eK$%2_TRJi3+wyWqg*`E_8vy@ykt)M_aA+zec|El?eG5VPqsB1wzYS^?M>~o zpLrl<>sF$wzd*%~k0*)H0EYiX(p3pF;enYL!kgt&w=gTS{p3SCBf@aFq+!GArxE5M z(It-4i`|h+tcqiX-@Wyhd1{xzCyi$P#9un4cdNb`F6W^21F5Q<(vM;kVI0W*$cl&mbGq*&2*(=_n^)14^ zEReqf&m?~pvh`VreY@zTc#Y%>S4!S*J1RN_9_c6)OsX!?u_4SjyEZnqh+>+>z}mCr z6@D;UHH)Ry#L4V59icNFTC-Mgw9!}N?K#QESqA?ULaZ~%&aS&u>i~Nmr-0?m$WnxH z_sBblbJoR1-3~~>#4~r@<0ou|jY}?R#?3*$GfdLMH=nBo_gl# zwvWB|TEy2F-Vu&jb7tEu51APSIR!xNEVu;U8IYL_VpPCr^I#5f%->OjGLJdb-7{~U zF)v&$A`BwHVIkN3)xtDS8S(U)G`n%^9j^H39k2Nuw2uJDUm9TyxpA(rv$+nmR;?Vz zP!#*sXJ2AQ3nNeP(^T*iUF$-Ekz=X>nNd6~} z($Z}hUT#Nl(C=||8Z%VLunxQ$q5fU(`hL!(|2jNy1R;50*_&YL{}NU*+=EcOXU}d1 z(O*XhUyTA}Zri`s>>-|MP!=75E##??PxNtu@N%()VYcemXE+DPvh2 z-1k`fu@C-4+p=X#W+_*p0E0k$ztq^V^96YEXqL+sFEexLY6LR9Y{}9H`_AsGh*4qZ z%=ZQS=Ce}4RWirH`53dGbLY%LA$1r9)tdGTzy2$2!-nfo>a1mn{5o=vumo)%gM9O$ z;R^C~{OB&WSgXXC&GP(xEcu;;NGIEq?XmXkb1y^@HixD5Jw2n4qHdj{y*Wdfs1(o; z)+EO!O}e#%G-gd+W<|kQQJCzdY_wy55JnxezF*q41D+nGOj&NOb#P{BJ!(s<(F4H? zK19h;J5X9IpHJIm}@{<=c8_o8ZnP+VW%T4GJ@Tu3j4TRCW>&qo* z9{pI(Jeqd)%Vs=eJt4k9bqAJu;Y;qLXYhA2R{c!%Ma2cuB0tlmjXryp2{TqcZCSUm9oV;{{nY#4)BfeZ{?)d5!;KM| zj~?CMKJ&RRw0B#V=P#zMTh46uing8Aa`)f=1@_a=!@%5jR#vga2FdhK{^Wsn{dFta zec$~igywT75>L^`pU!ryiwM!4K(m5VTaI#y&Bs3ehjr#UioQ7um$joDsks1J&mChH zoT==Lr&Db9DJoJ!Mfw0vWueb-Tad-7jSXkVGxi{VRcAtSNGd($7pX#9N(5JK%wT3* zA$V*aiUHg%koH_G;?KOe5Jln4_RBy2Kd{2*%k6{r{apL;fAG_7{pQ zg)7I-q6D98M^IRvnqmTiazL*`Kfr!_+F4JPIgbL+^0&-s{CG00FK>%CxXq+Lb9EB` z?GkOqAwZR&5rLI-G(W%Kw)_Mxs^=I08A7!TwfB=}W-Xg^-{1}ty`LSPfPo`KW9 zSIcMJalEOGB*&QxfT^YYOpbQA4I<~I@V(OQmGSk85bTFZDXFWtY_Q;27)vX_UZvHv z@&D!m>5Di4U-D)s8`duVH-otbRqkBn&|Jt`oO|-5+&d+Z`0|)+tudhAf`)~!sm@j)7ypQ@)0Rysw=ew_0C)0oT zFoxswZvR!EJ!0QRB0Y(cpP~50le$j-vSi9!+ZpAjFMrel_q_XMJZCo)*c8C+($X3D zq#<{Sqk|NMrG1>^K8q!_*>{fs=NYZ^5_GJ`1AdgHpks8X*~=!R*&KVq0N^s(Z)YhT zFlBIL%5)eCz3vy*%}c{(6YN{JGtp1nR`UNv}y7Idx-8l+JV$eA(sxvK;?#UN=t!p`N(3$a+w>V-3t zQ8>(DDYARJ6}V?1Y@n`SR)k}h=(HVEDtI`!QztKIkuc55Lq7Q?zl1Z4PiOrPGKg8t zUgOhjmsrEB>=A_c1C)V#-LK!cAsw!RN(T$o`4-*^+#0)U&GUOFB7h&>%l>9&))n|& z+AkajZqB|hW_y8U=Mg+Hn&hf*c;o=HtXcv-gy3g+d1`^^i{A+b+5U9ji(sd4=aO_S z5yu!K`EhA@Eej{o-~xgL6FLkWzs1X-^oS=xr5`1aP=Dm;K~7KD+K#gi{M?yS?UtLj z(!`^wDgI>=3PMf&QO#LW>(q-&fA45<&j6nUtAN}F> zz3+S%iZ_%}qDH1>8#L-C(8Dob4+An1_!x_T4Yn8&XM!=WO@^K{Q z_^P&j*ZvITXVbPwH^;=**`!6-B*;DA2xSqVhdInXKi}Vi39X~oU{vE;2du+hLQDEx z*a2+#se%};!z)p^=@Cz!dXd#WUIh_i-b|w22rov)GjEQ=3?a{Ym9SbouF&sQG%<>} zm{z3{3K+RhqJNfm;+7}eAgYr)6%P9aY(ha_S_r_s+J?C4UN+OHgh)b9@m6th_)pvgmP=+7tmMFl^WCVcbqs zmcMC>BiL6N8ZLMxF4z!9Q0COFEdsT#P+8W~Ge&9g(M`X!-F7D^nxt_VcvZkDz80Q+ zfPJ#YElppgp>{toLDC+7W@o!){oMAC{>i^--~IOQrCmmO3O=m3Z<}toiF&q-zHur_ zX6bPNCET+w9&RfaUg89b#jFhChq7+(0gi{;`8dZ;-avc57&{f%z*)P3)n9K5U7mXC z84O!K&#Il}D0_EjCCrkg%iF{x`5PT?=SP-+`#iSPu>~ysAp#kANClZRlS}oHd`j;S zH~!vqAV4DVw7oVw50|n-D2axG0k~NFpF%-?n0{pnW3dac(7yZ7x%R$0*SGh+>)!V6 z?|Xe)wfJ)T$Y&mGcb|avm)I@r5U*Fz*&mA-q3gH+{Wt?GJFTA*` zee(WC+UxJyMp_sIwQr_vwuq>f)nCGI_JQ&RBxSq;*IjZ}-|~l_0AzWO@T(bc08^gg zZ+U0Z1h|dk2xpCG=R$WT15k7?U?SkU8@D9CDp2hgZ@Jkc`;N6Io@NCXtIJlbS=Y|1 z9Giur8B6>sNiExuPZH*jm0l`Axcco3lGArdYv6kNP7IVL;#_=6mfP{x*Lj&jG;D=1U;LS<-_%^+r=e6DYG?evP&$FfWfbeHSG15 zd>_WK=rjOWi57}D2D2^?*TTc#U6cWczvxTgOcN`F3;l{jSEO@|qWOy^`z_;{?E}JbSRlUN0Tj1?!B)gvs@;RfM3OWO`q+K-Dzjwn~1oJDmX%4Io zu)->MIq*tQ07ySq3fPe=EN=skty?yO3jKr@Hx%K4Jqkj~DU0MxQnO!~Go?*G< zp+n53GguMsMR0b2EP*Qb;M4WUX+liYGGkz9+0}I!;oegR&b8~-tOD~K|>WN z3X#t8tCVmIm%5-;Wau-35IyemaRJ`)nMcuyqnBF(oGnp-=jsy$<}xOD zslDk9cef4eRwJ-K79*Gn+>br-FmxJiTW`WpB*J}44B9$yK6dzEI|4tPX4d>Dd;H(> z*0;60Uwc>R>;P8F$*$~h3A0KufAWRADLqd^r$yMKc!KNB5h?|;wt!)qAOgnykK z^W=gN!^5}p*m`h*fvSo^t?%1rtXy+l`_n&rxc$R_{eQPttzD4g1|v+_M~Z3J9+>ZH zhpcespywNXroa6fToojr@STB{PP$c^)$(-dcf2hA zmRUaIRiP5a_%eF;(F@qZ&c(yoY5m1VA%CXJn>+6g9mnao^>D~t?=O(y_oSs0e+g8c ze#=AEh5<~$#<&tBK@8uas(U%+p?BiJ8+|?oPjISqz&$t`mN6#$%zpAag9vl@YXSUyo=<8S*&E}6;I z2}f<>h(7tk;dX-hxpdw2;D-Nl~Y zvbZfZ$GR4?p>Nl&dG&;_=nksKIUl zhW^IpE(&h)Y|eZScrD`Fj?1ffa9NG>o+p9w)CXFJEsJN_+m!AqJdjFKI zw6KkiAkVwPxW42xbx6Av(v1>{8-byX-=r-}>H^VtR(;8&i8#gG)hpHarCw9^#0Y$! zuk`Ec(am4W{8*TStD}Ajn41lf14$de2+bBG?+KQQd`0X5n3sAf@Z1Z4!1%okjH|t6 zs6mYWy>v}i2Tj0)73mUKDy=KiOE!jJmM?b!rt>vc?`qzM;s*s?rri?4h7G4Q3|$^m z;Q(1!6DoA<;^F99aH#-%)up>IyR28BE}F4)uPp%OSmBL32vmTsb-yaDYX$jcx58cb z0qwdM@r?VB=haCBE5he_wP#{~`?r^b)x+@2PZk5Z$kKyDIw2ej2xyq!llG zyTEM7U+xNgum|#q3TM60ae{51e4h* z^n2dz{hW>S={d8)q8kai&X!~!Hf@J9d^Yp|&0r_SI1v(647jAv0nnDso7-AuJ(saG zP$6sGx^>yxtblskt6$9$w(<7GFF%wt6tr`JQ+2cQ;4q=A58xslaPI3&4I)8<&a3>% zCpcxGMji|odUl``US0CXcp z&LEd;LghcDGMqr=qVB=pPFRHb2N^B8JCJZMsak(69j{@~=4|mXmZG~9aRG`Ed)AaE zPZcAFFz!~kvow$5a7H&u7!(Y)<+HIaY`)#+H-o|6Ayx;R#7LFP^;fMLqa4;I{9Kkw zIsN|^8@s-C9W2?cswQT7!RvsK>mi`2Mk1~WX5vWO5MUEE1%}WFoko(%#zLvrG zGPXXB6(*{1L) z$^eC%u!nU7`pOHIi^r5{H$x%fx((~u*SoxJWu|T7HMg<9cpeJ8UDPS~k@n^kLYw@) zfUHm*kzC2w2D`6;P|pS)Syc=`{ldg?5f4qf_P z^U}R@#Jg2ohhC%gK~!dqSy$INjb3%lPbisaM9Te^uOL2yl_hDwu^&55*9%G z#K{-Fb%GF~h2e!ibfq3!u{xN+1Al`hY+n54MF;Ckq!d^WH)qJ_(&o)XAvZa3lKOHS zAs#F39CJ616(6fst!CTGapGcFlsYvF{#W?Vv8vPo4Qj^9H?R?7fNxqL(_PjJuR^2q z!O66XZz@j-MOXzv!+IqSV`EwH5=&xizq2eHH_wfqIi?U)<(RTGfBdXZi)ovlpdI*y z?`3cOovi91x?uw`ke-zV^;r+fV=Keb{WOeJIoBw(;?m*x0$y z_U=F4cI>Agp)MZUH<|58bEs>x=rb%bGibier_U6(6+QpbMIYRYIK0)jfmL3l+F3`# zH~P_@qBzXjHrl8q938ukcA*!N`lnL{tML1g5B^B|vv2%LJ9=;*<-LqHCyt1?=cn`MfSi@bI1cGac0kPkemZ;l}>PjhsHRZ15rqdQ-HYukF=@^<&_ zH@EB8ucl8u-ah;3&t&pKI^A^R#`dOrzoU)NNB&>G^B*ZsCo^WXg^X=RISJu>+B4II z3eY%9|2y84ZqX}cS{jqhxU&=3K2t4Y~Yyt9} z`fM8Uqdun65Ic>W3KHM>*%+As?Q{^r%|6F^m@xz4ZJ$i@Z`#%K>MJW>asb7VLZPtx z8T&ByHH*ojOQdV$bGTURy`P!NS0A+tCY0{A-ljh~Myn)jL}fgA(O)i^t-pG=0Xz2| z)9@?40gL(k_AdYftFWp5i>8X8mel`H1K?NAV{B~Y~-^;`={EHO*`?ccqex_aJQcvBl1^!xY!8?2;ZHFPo z=dbSeO`wBuHTZNqY0#x{_<)iyJilmY@%5M(`ZoFy8((qdorXF%6Gu(0dy!q@H9bRI zOC&)~Ex$0TQcN(ZQsEN6wQfmgtCI>0m(0u?~Da4dCID3rivJ-eKv^G>sW zPGLx6Whx3Blw?hvF@|U?yh_(hc6si?@W>T9Kmc(U9|tZ9!U}E?TDx$<@~4}EmO|Q| z-Mcdj;_Trlg2rNmjD-k>o~?YGJ)jECE{UAW;Gr(}Dbhl~AU*wc7rWuhbPVLfJSR_N zM8P{t{1p-rnwM}4*gbdOMY@ZaojIN(isnK)l^j|;FWMnoVwb?J4_c94%%Im9+Y1bY zWnPMt4wt3bT;|{MRhW0F^BIIkY2mSCmbJp^#Duf)TIP3IJu_zr>mi!Ra%BKAqlA8K z4@d*^;3@-Wg_k0n`JKyWDvPZq?>!6)ZTRYfSJ2h=5XOLH|<*UTGq`C}K1R! zf$!`jwK*#|cJJQRK6n5981~u}S~_d5(nLOyr`+ms$DMby2OjtWs~bMv{^39PhbUX- zGm|#f4(#5+IoyAgRU%6eI$U+I7)9Q3@IFnMEn7McAD(NU_=DeVcfbDLwt3^0wuZg4 zYuP^VjYGSb<$`zRqm)CnVX~9?te&Ory-PjuD(wlq7$bBnREq7n_J=g_|?8;TuorxRuk;wC2``3Ur0i< zEE%_L84B0urQ#*E%9#0-9wx_MjUD*tf^_KRyQ*#i4yA8gMd1pWbo%H%BP~@N?n$kl zdd7hV`B6ZCrYb7!zg(rD!8>_bAzuC#H`_dqKwSoZE?|q+T#W5$2-BnQoRxLCzQV_4 z>bWzp(%e3(>^)TaCTzWyV8NHN&@FX8C@E@-3ovjuT>g?5gH{>n<&3AcIqYL?bL}@& zw5S9oxSJPg%_Trv{?XzF}THAAgeeQFr{dP}ukPg<8KpqMu z%H0fgmv8>0%itQkN;~_t3S<+WJ`OrBLb>_1XI^Ok>i_t6Sp0u$yKeoe*h!fS?anbX ze}eXC;e6^h%kSUz*4MWG^hcj&mizhkhBw?!_&2o4!#mrO*%#V7-umXYYQ+)&pUbHw zk3aELd;H1g+UGv?vG%%q-`;-ohu_-%*>8M|WAwJMLV{IWbKnEYM0}GCaiSPgSKvA8 zRg?qqw2a^p+f+C}DkwDP$-7nG_IQG}>Xz%*GWoES_WlHAuqE3AmM&V}w%v4n+qHWS zN9Eo`dpJQJW?_)_HElmL{D1VhFK64=S@?Akze_VXodr7pMLvLsvOeqT-}+~j2%+O3 zR*IV7XZ`7*7*qZ=AHkdVs++8+yv$fC{sqExtt0j~!m(};jaTCe2OO!D#t#f#C4%W$ zZ}C;><(TfQD_Dqc4N4nL*ouS0-;hgc|Fyp?IE!Zb!X<@DVY0ldj9^qJ1WOaF8rYg8 zCM<;>_6QIwLU)BTC{#af_4GG5k9w8eI>#=oUvL2dd;>1=$}3O;CII4Y?8Gn@aSQ`Y z9zwqQ3Y_@hr?=^FRX%(ZSL0Vj(51f;9KZVS;^SEmc)=-X<1$D)o`Vnx5KEkiF6IhA z9SojzRrvZeOnnbQ#cdEcZ+^!u`R~9~W=I3eqUVQ@A&cXlw1yX{4P|HwFC_nh@{ONcR=bfvZA`Y1)wcG`<~z z@tiTrY%Vh_vk;V=4RE#_q_U*nb79?&@3JoiP=zinXDi6K3|~R&0LR;TzPEcMW2_CK z)BMo$(IS)vxhUWBpkLCW%BAPc;m)Lgmj{EZxN|AA+CKrj>&)c!3ZwgcmZl#(bT9(2 zv-Iw_zw^%9Sx!CP4zpZ-|Na9ATSu`@%-%-!eF`rE8?=)ys6v3`uYzCD82QkK~}8|vUOgGmNOE`b-0#(OTz#ezEn-pdSv zoz-(OH&fs(p7rtTlIMVih*E4nKuL zMytdshFneHRtuLLTGq}kX)rM}HOZg1%3l($&)lU!_^on3@=9904<-1m*px>WeAIc70Z{AfA;4?s}U@{TL|J|u`BG4A?Q2c z$*BUAh0Apv__)%*8GMFQsjII1aBz9_$YIjuC^MGUdZ|p1#%^^u!m(D%P$HdT_Hq{d zIG6Ht53<_|yv)-=mL$6@Qd-BZ2GY%0%F5LY?2>64H(wV)Xy5K#D2tZC6Q{ER#Qn)n zFw?hl=XUactZm|0ystj=5KB#uMNlz6Dw7nu&Qr$LU2Q;^M-A~=E($bS-&fH3rCa!TJSbNJO+Yh7bZhc z_#&5ev0k{VFyPyPEA7uPFUkYX&X%!E+e-1UzWWXY;AH0A0Wxm3o3@n{Z|Bb^AGW#j zw2CQlw2cI{_c(!h+Xgr8wQacYY5li^lmrWa>U{QafEMA3#C_B@bC$HwKSisPQ zOK6hdyd|FfYL$mHS1B4{h%&|~Mfl&XOxACee{Ny2-EnnJuXwb8M%bq1@oMZqrVh`E zP`GmG>b4T$aNE{x?Fh%tna>MnU9mDB7;JwzdZL|VWe?4L`}C(i)86`)H?}QnmSF#4 zJS!QFu~mE5u03tj#*K+Pms#N7`@N60H@@+8?aN>O63W3^`E!;f{o8K71%=ueCs0i0 z*wEF~;pca2lSMTOB=SdoLz^!Dp$hMz39K4tc)Dm7@)@aKq=$Zn5>5i+#)}G+57^lbFy0vZDxRx3UK`xy}S%?uu(pgSB{`k|+wJb6#yS<{QlPauW!jnAo^;BO@O`+etj_nTf*e>wu8*gOx z9{VO(@^f|bYhH6l`X87WzQI<}o)_BKf+g+tSKZW3(ARwB(P!Fe>4 zNw3B^p((hEvsFqzQ5F5rH<`f?N1WrQPk$wxZILg+;7^5cCSwfW#VHz8EMd*0Zlp~z zUak`AO`xL;VWbnDBF0m>={$W^^}TMq=;6Zyjy=2Yyu8A1uK>YbqSuvY$|$9kLUV7= z#S4DZooiVV?z6!AN}CR^O0^n-yt|)5W+Ga+mC(Ff@Y7fKKJ1i^RM=jo>7~RWQ`EPN zohL%0 zJZuDf_?Pfq-~=h0dCjGNw3gNef{Am%sb?jppD-#{`unL1uX$EFT~r~9a77^u@6tuQ z3~zpuO}}*>aG0hqhOVLg#w)}A;SlU!FR<; z{NOMh@7sM7-K#IP`+Xj#UnS2QK&^q}7}W zeCL@NKZh`sz02^}Oa?y=x)iz`_&7Vi^W?6;bVlPaOWGCe7cl780=5GYr(awuU9-y8 z<0^$|(iVOWCRG6R^+aNZ{sfG{Ii6)(AXFrrT~P6GnPA$L3{f%Bmh(z(= zF>x-nT)KF??cTWu8e+r@`YDuXwRw`fEOelu02kQc1H>CNx60<(n+?;*#uz?03{ofIPK!?Yit~%|3OFS%JqaW|dt6>r8Xa zgmKop!Ymn^K|EQ8m*mseT;$z6S6%Q~&b)PQk{k-~^Qv$NI&rIS&?k=!8ki|}Z?_;+ zRAd=0gDl%)l^yaeoDBV0nL@e9tL9mY?ILFqwhz*D#mdEPl;GYMbh;_yv}~E3~^b*jd(ntSr&uyN2yXupIB8-r2jg>(;{O%wi~{ zFle1QlR^J1R~(e$NPcjpOuiaLG2kA1j)H)H3Qy~@gK!P|S)Lc+!DSvpN!gn(jXd3k z5G=p#cEbMaiG(xmDoYxzh;k#*;21Y!R6c zoCyZIDke~zV9k5YnziuN31~3R?BE!@h0+h8+NLd=+DT@@CRu5)9Oa3I{8lVk$iSGTq#CKDJ&JJbFp|bpekksdZ)`8f74)%1 zkl*AjQ<5*l?XsEfl)$I z7M1v4MtQ0Q?(p*}VM0ZZAQz;}Gl5CpFkbdw zPITEX*tYYaD1k+LW4b(|U{tV=y$%Y@V<$Bt7DZxc4Ub_s?IcDnm$FJ_Is3pDQ`F1n zFJ-iQnWHpaCF{&G>G7LAZ&CZTfAb-l1o}kUy+*JE>F=IJ)JXsqqt z@hlDhY1)>Rz=X!oWj@07Qv7b;b|VV#eQgqj{0*#hdgvQRV-zsP@xl(^N7;*8cwe+| zvaPVsFt1{r04WjkMtRV-rw)oI`8-Geunt>5M={{~nk^gK8}7aXI~S9*<@7&{pEPK? zV#S*F^b?PPA~tFkE^P;Q?QG}iUsux3&8JN{&9ygfv7fxKS@mReYpf z!2~Rxwv$fws8qJ^^RgPH3Wlb+#a$H5R$)+1ucZ4cK(L=Cr$nA6eUaRXo*5)7f+a*r zR-<0=Qm~d#e{}$?$kW#ldDnY2I(;*QXt`%d<_X%3eWP_;xw~@*@tGso(zN16-FsYcYN?`}IcYm^~&ev;5F7T42B^ z%zHVQP)n}6_?D22rFnZ=!aG~zkzWd*(y9i)9X&|@>Jqk`4CmfT@vcj^;=9hFcQ$nJ z@Aum)M2U-ovOeFlp`8Mnmn6OzAq|V+%w8)r&Ecoe=1iie0gTYG#dw^}C3NIbc!Ev@ z3f)0S_!$_PRYPQ8;~-zZYJUvp((E;>S4TiS!m@7n+?zGKbB{6d=tAk^v1Zn%*=&Ds zHHLe)4QKe}41nfx{L#LBd&2`uv6SzCL^78VE^(;KPT6Js4lp)uDx+?btWC4-|~2*dHDqkT|xpl3jx5Sunj9t-%@|G4ClK!h|NqH4O3c$3P+A@CRbv z1!&o%KO)=&!mo-B2lxtF3Yl(~@DuL7GPzx_?(CjtH5a#tbccac~A+4~^lKGQoETIFt!O@N9&3hmI;j z%)522IGB2a^1(RToj8MmC}*qWfef^%U-FqOVLkH11O;}56<4~b$k33WJiC}961Bd6 z>EcXgyV;jY-SLRIOXplEGcOjiJ=$s>0=h~bk3d|#hU3HBv&uGs82US~k69>`5#Z0(xg95{eo0PvoT03{792g~IY`+HsCp*;inR(>$QDgz#W{E2qw-LFmAOki+QrG&Hm zCr+GVHNt!Z8-z0Gaul9kHog?g|1Y$S8?S3C;nh!k{A2B&H{8QYf>Z7A(H)d?&3{;VfWpSd+xVL!bZ}x#^O3>F0a;oCLr<{hNH{Dii2SHMcp7Fa|HjaH2vM zj^Rz{A0d{(u0puhxIKc;B%IiHh0Y8VZpgRVb`DQ88+p4dQ0NMDpwFPu$|zc>?R3u4}n{Q=qFIj3kYvPhRFIOdLN3tV<{&7hx$M%kCUSdYG*^=QvKz)^$`qw?ib2WFbPU`~p42)Z~04@p?Bu z`V%2|bpiCm%{pdVV;Rn&T{WDB^JcJm<~-$hineg}IqP!qiLJkYxw2c_cTf@?FSN|M8izR%@eJOqD*3E0$o8R>M_V0e_z=*)@IQgfkzuU@o~p8hCHHsVv5ofsAj)>y zF>C`^k5z78WHw&ACMrF5?RbHiC657n>qu>NYxp3F5t}0uh^{{aV30kKLm9%gZ z9ys-U5qR9JQz|^N$DTGLsp;7#-@)yYdqqEJQU3a07C=XP3Zn{)vJ5k)qp{bafYi`L zmt+AODPig0`A$4t0;r&c9}Skuk>E+F7)K8-{kp`hGetSJANlO6<5-DAEK*pGK15W@=U{VO7!sHX64eC{3oX!mjSq zu8tjwcJTp`dJ4rfdypL@^4migG&rF_K{Qn5!cgK-?uB2+XZn;wd47v~UuIVa>l>x3 z-T%_xqCJ$S!0YIl%y)Sjq%-tAC_%Cx{PgpEKsCOH!Vh2!zw`ti1RZkds2iZbanLVk zMi501h;ZRxf{vpX-c8#jzIMho#LlQo)A?xlFEI1zjN%9yo=X)A`7#u3COP}WRlkmby?N9wJfwK~G5!mNh; zs&z297>*xKH6bm>xIe%U`kUB+|5Jba|Gj!rn6z=_3d|l=eIct;AZkRqrK|3JBVZ1 zQJa_aoWXTQ|DyGsD6N#>O_x`aZ?j0bUt zo@qB|!zwI!P8@GUFiyTJa;kEi`0ilyIk+l#g&jEZ;!4kKkA#kH4a=T(&p}7=X8Uza zB_s)}B-WON_DE@0000$07*naRHUt& zJK8?-(cdS(+FQBYKKsDu+Z*n=3n6_jc215nQ@<4hm3ufg^Z9l!TVj6v$A6;z%c^N*>WFA?Pri0Qj3w&6A;^@PM7WbkDVg2Mg z<7A>|Ad4eT1;>|My-N?D)rBLh5L3tpfbB(;&2F)}crud&_CHfoC+P%Ir!<;1I7B0uQ zXE?>cBL){S)@mqIHe*Qi{OpOg@2q@he`Nb4P7q((gAy1Eq0W?jgDv@f;nv-J%g*Ef;#^j0o| z&sXq^)#DX$4M@(5?-nopQ}zvJwhc#_K=-rCe|8MgBbBX#)3r0i6vzI~OCr^Sd;HQ6C6Fl$yCwID zUCWHiZ&1MnSKtdy?&2j)>(4YQmiTppnxW7N6;*zQng-@uSN97lcn`4aP&6;oue|Xu z4GNy`eheknzXtfVJccpo1791&wC{i68-yBQYZ-X?6i4xSnX7_#ak{X9rPH^F8?cG` zG6C_Dwh=Z7YiG##FG8|28~!XiXDsZjU9RR?=uTRCet85G3TrN%pXYnKR8%434Ci&b zRNXzf&R!1lO?WkF(itUnkgz;SUp&-QU!X%)fZ4QZBZK`pZ4bwKSsKEdamp~@$$-^P zz~k2x45sL~6_oTd+wKJiV!mDS=jwqdfapA~<`XF-UMjrAU%_678jSJe&r7(ee=M_3 zUB*SFjpMEiMi`VU94b^hlcExhVVMRE?cW=3~o9^Fs=3C{30@kz7Jr_aK*){R8 z-HcUc${^`mzd*t~>R)aO*DNJufU3~EX7ws&WLG5}+XCyPX)g8nGw=|v$DjBHf`dY< zD+^q9xhS)twp%Jw#NRYj1WX~IUbmi82AHkYsN4YrKote%DMyVlAnfTWKIYLho#kK4 z@@Z%1pMCb(l#je?p54>!QF!wZ@LdiLp+j45DLOn%P4HI(bax%UNb^CK;>(obTD~YY#n)ai!O{+ittH{r<;3jNtB(lXEBo zj&p*}@}Rsj!Ju8Z^X9uvg_SPMk}J$S`Rw-0z&nG!lqKs9B$u*0Sz+A$zQ^HNXXuZy zTv;J@;`l+9|Bs`fVX%9Nl@F(}I6ikNxVk-N3Ou&q#}S6$EKkouv7v%(5ytP__b=^L zOiUp_Er4cj@0psM$4LWI$?qaob$s}@Ka7B}DPe6>tk)`A9QAx$!C3oD!j(ccsQlcBBY}YWJh7)$<3(>6+D`9~NO1J4nb6Jr&dl?d|?GPS><0!;z^ z2*$q-O|smYJl@Dj78)iz&+MLp`URHcs`#7@uRZ+2a~>(t?%uYZnLkeinQG4;+~4+{ zzSQpCu%Vr2fbVi|>jDK0f76b@E9SM&u}`mZ<<5WHx;j?AFLyWQOI*WV&`|!iu2%|r zN>|)_C-H(;(#ERIFnF-(>+oZW3)rIi;J=F zei#ADKI`Ct!`RBe0{o(JqK`0Rdx-t#^egOUpEHN;GQctq{+VXdO=99jqH*+AeF6BS3?XRo1ToJ_z0(jqO_8pdyKG3vETCSvrkg&-^;$`7R9QDI5%9suHAmyEo}nDn-=e90Nb`| zC98N|H~)1p)+yXmY*l#jsb|`&UUf_QC~2qQ`}X_pLt*wH$~}&pdozaI4o|kdN6)om zY;Bo6r&frh3@y~I43c+fQ2Y;V;NO&u?J8pq^G`uVq2cNT^DSAUM61Z$iwBAybQHc% z+j-U;$mjf(BD`R_T1wxuj6t;dv1jj&wrFG=V|cgWTBm+U6Z>ApUbR0N;>Qsc#gd3L|Ie_1P4*6lDF)GSiX~yls|5%i8;B(Jo^*!9M-a{yk|US29a~4C9D2_b7vp zplqOzIS)V*pQX~z6@%0rY1d;>WA&bId5TYP0vC7`jKN-7RSZ4`mo7c`4jhT=p9Rpz z2#*J5mE9n0UOG%V|2PGx^~qn2cdT2|E`mM$?`4$4?h}gZEC2S25$vxZb;sDWL8&yE z0mIEgDwg05lk1SOwvf|F!tgdU38Ms1I5Ri4KN-Rsp5B^ z)j;c2m46zx(fCRnZ-G!wc97i_Y=XQFRtzthw8udh^{s&5Ksb5EzY7w`1)|~XefwNili2~%y`y>ZNQ6*^ z!2Ppg_OXqZ)Z?5EwgZ*;78r?5(;F$-I?v^VT|J;WVxKUX5LASv=y#QzXT5k&L+Um{glqU z0Chl$zxW;@m8Z+-LNe3yMc))ov5j>!v-RNM%(QtGN3R4AL;7B|;u3?QnsK59A&xj0 z(2mJ`IBV+w&cP$V2rD4=ZGzWHjv{;d+2;@dId&;CI2ipwh&pv@Dud5O2;tf#IS&mL z9s`5u5hQpPUX>rqzsJwz)$S8rv2s<)D`zC5L~t*;mvmM@@Er6Ajrh4|{5*;j2P(D2 zqJ%HYa}onRbHR53v)IleNiS)mkYxTc@B+U94|epF9x8$y9BRefnd^NFo;4z88M(*a zTnJ0SGXh62?CDLY4pyA|8yQW0$+P~`gAxMh=O2YzG>JoK75WI;Lg49avCEiUy)Ykx zaN)kaDdhl`Of0 zS4T%pyEt?<^+n~5e7PLPY_1bQD1aI?Rzr z!F_7#M7wV7vi21FYXAN3emH4plyW}%*iGBnErm}N81qrKp(|*cHm)L{$d*$WzMIXl zT1U3i6P`=mz2Syi+UnKIavn3%N9vyf?6DIF;8qm|ZmwF956g%m*8Ksx++(^3uQEhs zltdCOM9UydzyKAV*q_G1~Qa5#iUL3K9qP+jl;f z`mAu`s9H8iUq+cyEAlTd=@CKG0O1#$9)ZJs(GE+b2n4D?gUFn4rD+l9j8$KLgw z?E@cpFEgdP+CToM|DxS;(}wnU|K9(I;%E^}M;WU80n`QR_Doh-?Aw2={Tj=gAA9mC zw%^QamspW>8M_z%Fc=9_?;63wg_|CZun{+k+ucD!I;Ak1WXv7l@xdX zEw5ZvzXGmz0%8=j_^W73!oaug*tgk_EoaroNmdx0_H+jo0Px>@jE!DidJzHnFvlZK zwJGY|WoB4a5M(@89cJ*Yq`ccF_>|gU!K>f?9Op;}m3r3SxEl_?Y}+tah)(|kjWlfO z=@o9M|OD8*kX!zWyxA5$f}7aMw1E z6tM5L%%piJ!n=wMmG)lYGuj^MseqsMfPL}SQ5pf_7`JGY2wk}gGGGJ5{>oK9w1vXI z=&U_`?j;1=wA<05h0ZINugr?LZ#?=$6wflbO3qWKIC2i&a2wU4`HQf_u`<66>()>Y zm$ZXNzueZXSkSf~JVqTRZ=~<)p?-T!&`7z1m&M=V4eF$u9C!=PW>q7_hC4ZNsvSSV zm}->M3ZD2{yZz>M7&SfIe(V4Jrx+~!k@lKbzZNC>vh>%B>DL`wSjSxv^y*t~YEL}< zTzh^OZQIP{;392HIPcpqsb|9Sp0rffv2KY|^|`o$hzjW_0`wRVHj%&SCch>#fykTr zNq%uoTua)^dyheV=Bu1~F9Rl8!O&B|-qi@8X~jaF>6FIMIh zj$9qasPYMuSXLCG4Oi6yD>4pYvMND~GVu-Dhbym?v%!lo@U>Cs;&(|AviD8wd`Hmi z(&&8!*0W^?9$16a6R+?mhFR$X4LUB;@n4@j2vik8cYbtS)3FLG!55wdGqI-;=d)w% zv={}aG}CI^dT?sG3<^dfbp_5HmINz=Rv?O!J+UGNc~P&=|(3=$CmyS9xY+mdSnTD{MI}M z^$uzf_L)&S$Y94=Kxc>+A;4U}@#Y9J&Tt;*eBATrFLI>X0p{&EK8yi2!=2>YL7Dls z19dk00^tqmKd6twgUpUS13g9Wski3C#99f^J*5AK}{#L zIpeHS!-2~!x7>)uNN8FjL!mw9iQF&EZb9QOh&fP5QT+lXc z+7vn{R9d%HFsx?aXuqIc1TRZrxGn7SSws|mrBH)(GRmiLqU`WfI{TNAQ-@I8C5`3o zFOdS$(-jULI@Fe7NKLXjW3PZOPsm$YNq~(3^J>bLoBPpKQpl^$N~z#-&uonC0nakl z5Z@g9eRgGn*pT7$Tj3W%jFEV33GCGf0$6erbishs$+m0PCB1N)n_xuzqM2;l= z5zcEqkM(E`)`|brKjikFpX!QeHx=p%Sjgt(-@wT#oVefW2Up55*6cz72%GD^a#|xY9)-%NhD3DE3rXeE++CAar+3p+KW>wqwVR2*I;vU25Y? z7qkuR?U$!LPEw2K+J^Y@pFfZ?g!Oo$q_mFGR%ImyX^<>=to~FU8mdxwSO;}eXd@v0 z8qt!EZD15eW}}2u0df7hmF@bq%d>R%{y%wjJ8=r$Ig7mmgrNl}L#S=UmfM`IA7wf4 z+V+Om-rio=zC8lbSHJpH`^8`UnRegnZ^v?XYqxCpxwdlQy!MGtJ=Es9)R`Gm>+&(^ z`@j6m2ip(5?;UN;Vy%R8f(86ZOV?JgNB8G{_9xmHvv>ddzyD9|CbmhOrkz!}QhVE_ zLDh-8@lkn(GSr>qku=Qn6<6{;>|$*qFGNVa3QYa09ws=qeszuYv)oYjx(dQrRQRl7 zvAv+pvBk9gwcW1zOt3Vw#1tpu*awMP->xP_(<#KK)2EEm0(W_-i4|}ouK9G^l1ee> z#YbreN7#3NivGrJ5wJv*nXaT-vvwt?EbK!`#Fm}eb2%E%6Bwwa@LBI5NU zOQCD<4i5T5F+BWgaRpnLo4ybF>Q<#Q-LV&X(?RpIdj@&_?%FJ!e*2*9(6h% zUL0$S+f5rs+HZgOBkkvY{)gLb+irv}PzplheHfD6L!Z53&ARs3W8dId$_H4o|JHWr z9XGef9{C1Jv!_t1&1~0ixDFw6K8nUY>GQP<^2@*c%k7q1w{d*lYue6TFShmTH?k7v z=Jx8_Zf}45sn53;|NObMiz+fFPtd-BukC1bcC-IZ*bRr2RpwSStwUeHWEGrXNa z3crh-hdj_Qa?9hp}dz4c&#@T+x68{xTnXz9wr#=1Rk=VZpYVe5)mCC2M zxE;^bWsQ1DwW{ytgR3%?JaoA!_wHWaCcwYM=%ShBK5Bt6HqdP=t+xXx z(@>3*D^G9bVBenD08E!N9jL;;!ta0m1$(LA7fwg)6bSD=ow>=kOh${T0O2LGr@-+v zdI=lTfU1gi-w7Z*UW~_Y5K`cLC49nhBQ1i&Elq*Z43=9L-UhgbqCd=6+W7!65W$I^ z&%!4D10ebtQNIFgPG3m61aiKwk;H|0<6@rZjV}v4afR(ScPgp*w=2HP)z?=aZjjAhe2^U%QwS2)U2Vg}a^-rb9AdJfdj zBh=P1Wwqy6zGW8MrTphua_oRs17!Z+X*TVyE>t_GA-TR;=4o;bE_eW=M zhc0Xr3t4$_R^uW(PY~W|=J9hs?hIyWYzqx&IvVxzvb>_PPhIKik;uoV{LF*1lxI*F z~0r+t0%YnuA;SmO7Yq=3aw-9tF3KW%Mgpj(CdMs=a&m zQf3zs##cuPmTtc0kMAF>eRI{Rv^s5;n6oT9$k&& z)`$_51AE~kcIAiIwc5n6Cr+3qGly8^pELVnTe*A-u!uX;tEk3*ayyeo6GK_Ff$#wi<=DYieOC_3b`xh&J4$xJsb0epqhjlr=BGuw$v41~oC zj6%<3)xzdQJX27-rE}HY%X&#ZoFR034@C?wnJ1J}tg1MRV8}FTTe5I&+la96`+szQ z`_w1@xIMlaq3ecK?R9tE5=G4sW>6n{Vh6(gLg;gnnOLJ?KZLsXme<|YRwC42!f@8j z%%Z;K^>?&C`prF#h+s3_QeV7Vu9H#U&xRiyYVm>>xLNylnbdWYF{Rzm9Avn33W&QfK?I6mfa|riyQBbM)n?XDf z?&=ODSj0>|#V6HZvxbCC3-ly-QZn)KL5lhEsbDsJP zj3~xF1$`X}AmCkQzxLAh(N8|u+SujxUiRCsTfdO{af&_gyV)jkzMW)-e<^M8=O6sj zDD>XyP`8Zt#84oz&A z0!O})SX`E~j(PUp`KC=|hQ7v_gm#&mG-vjIl$9_GG4l7RuYaw5<04<_X44i? zE|)H;P!%(B3O;klyQ?kibJAAeGb$eB(>z|X5*nIsR68huQSQ?o9%aSWO*gFNy!sp4 zLdHe&-#fp3b&JIXK>+|HY<&X4qSb7-z&0juc*s5|F8EoMA&J1 zmt($Zuw7DWgJr?hWksMe@;BtvRfd5}A2?544L_X*-@_jSsD?yG-jqv7BM}_A;54I2=(yuk94MWgX?!Wn2SB<2^#F(A2)s`>oP!u$DtMB% z!7EJfZ<$y=eSW$yd|MCfOkJis6JtgWw4K!($J+D{zV|&ja%&BSurAAyz<@CAoOrR;S7q)1k2c6FW5&VkbzoHGXMxI51#zfWz$(Zpdqgaa+!VTg7<=D zB5-rOVx9Gx38D&s2DK!5fmS#X?g?vB+@fq(cx@4un5tamRSihb!Sehk# zp7DJSp~I!rDowWU+<_9p_PFq&Lrd@XmqWIg}3jn7KN9 zNE*=|kfw&`<@_xFbRTtQz9|P+XsATh@R@?YhWwIm+=LOqwJRI* zEoDNX`tVc4^T-F^nR%@Y;Z8n+k8c%@;N6?$>>!Z+?aT_VU?zDLvsmWcak@AX5P?vI z2e>jrI-3;*Dx@@^wFDzn&i0PYWBoY_DhEi;WIOna@&-P4V235A6q1qw?T5;VHbbG`rTWz#t2kE) zb5Wyq2#OljbLLy&UL0M`q6O&GNoXO>RR-9vOt8{J1%_j*$;pZ2&H7+dZ`xkyKd7gk zUrk#vdlO_hiEw%>Gwomc;-?uHua5HX@);B;C=0YQeVDeyIs%f!pQLV3?%FIEA79fRdE{%f3u~ghvYpAQ7HH&F1u7 zR8E-IS;}q}1K>pqS26qb4QxuO*kB2^eRg=Pt9#^K_OgDt50(JFBuvU=+7oA&MgRZY zy$OtF*>&G{t83}*s;=s-df&I%I4fs39FiK6!$l@ViXy2<)RIURoIo;^K(LL#3Sa|C zY$JAH*-<3HiR=J^oJfgeNwFw~q@>{tcXBu!4rlG2-uHd2ed((Fe*gR4SJllSDJuq| z(X0Bt@4fr(dhWUBo^$TG=K_Bia?6+QbeRT4!W?b5X?x1rvJOj^A>jX&uY9ANy>h<% z^v51A_uspx3?V=qId-&s?(<(_uk@O7;qo*JqgCZ1^y=}4?kx=x(8MfI{lUNyw;e1t>Vo|m2Xj*ogZza&o%Z8mw?yz?jFi}G3&PngZ! zRC(#1_qrvh7vV)y>TdWoy{nr6C|v0jouY2jYB4jVep%_Q6{;^NGklO`w>%ClYHF0b zb`go5Bd+a*2HJn%n)gfC9?PA|J3;9=Ju<X#0xGGmeVW{@F!7db+Ltd z)$lN5xvyM>&QBq%_p&!!zY99l^N_y1cWf(PdhYqMWX%9RPSyfL_KCA%e+5grOE^BA zqHVi(ZYp2+!k5Y!_&AmZu{2l5%5*Wx^Urq?#U^m6SKf=Yk6`1kth=fQKH0w zCA7(MMn|DQT%)tTH=DWBABfhb&zxsmxcY&u}P&=&t)^4;j9DEW3 znK(Mhev)`AgnJogU?yKv`Mhw|C%)TP{3eN%(2>t9;6$MC6u}$@trA!#Z^>pGZ&4l` zFH@1myd)BB<^%`Bh#MlUFy?)|Vg}0lPKY;r(yk`XLS8Kr6QM~^-z}tX>()*XO%`dZ zHMdropi)koPm@_Pt@ZXhg$S5D)ZfGm!6mS1V~uNk?u1!eIiA~`n^#Fw!-&hgRRxqL zg;|XCbFHtj#WcZJ<$j@aH>Y8{xJ(81y}^Tk6)t z3xmzQX!V!5gkY;gF?~SZ0gUgyf37u(IW^;>P0|9SeO~n2>Gnlox%CAf$DTkF|0J54 zvb&nQ9HHJx`~nWW{?niNM0w8>?_$#5$|~hR1in7bN*(2Rm9H?t-@uX9K!0D3wc4|L zC#$hnv-0clOA6Y0cORFD=040EWi4kCl)+aaunA{9M~@ysU}rC}LOB)m_@BO|gPd8t z8iAm@oH}&`#;YrW$hIw8(V|~qU)lb$5vIfQuB$xl1<8b49fLj_hpPq!SLUPnuYuOW`ea;@PFx*l@?Xy$<(<2BnN7AT7*7Fk zfHRq0CASVojvOI=Eh4y(f@llBeq0@0jS%Y!{R|AirOTY{j9~Ao?JyqKmjnAlhmO!L ztBa)9TrFI(lEiA1Rvnu+Z;843iIXP+BZXiY9{XIuMDu2Mo_S;|BSkBytRM#vpnH4z7Y z9<8RpaS?^qBrslsiKa@9`yP0RmF27KsXhj5a3)Bb#<6ga0T=#un$uWTabV!2g0)V( zxZQ9&n?j!!S^B_46t2)sll&)_7v`ez1~E6&Rt>Dk&n^x~f9 z!&^W5#yZ49K5<*-(}dCheOg$Sd3f%(uy^!WH!t}(E=n*Ie=1bmlA$F?6bTgOetWk)9N7OV zv|t(c{pD+4f2M5RvJF~P9RZ%958P8P(OWSM6nbQ6{JX?6glB>y_4aU?7D+RI8yzCsJq%@Ue5nDbJR-FZ7_U5=(`S`B-Q7 zHS65!*zt4a;^mRDdh1$zY_JVuOgb@vxxVf0DW}By@7AuQ4hSWh4W|?B$J$VCYI|~H2d9&5?{~jU8kzwh{A;hyT(%Ijkhz1abAdp> zO$T47uBaEZReS?EW>7{=j*LbCvj4PXasfg7HBFm~Jeo9Ln(KBRX+W*M0`@`$>e#Sg z@wcX~Z@uS^a_3ZvL9gvjt+m!~T*Vph)A47q9BZC#d`FC9O))sIq};!6OBB&#SV*kg zxE0!u(1%i5#f15px47+GU4@e>^tNU38hml4^IE899vvKkX=fYpk$Vmg+q-U7ywt- zw3{xgDU4VDlTRmEvH<3$$vBipN7YUt`X*pdGM~}M!2R-#@$$(}KUubKT!#=2onS3~ z7R#7X1nF*w_W28=SR{OnQ$^UqgCfIx+zK_s(Rj7QixBfSw6Iy{lmbs?OVfM_QKXH<|acO*; zY}>jGnyNySJfO{e;HL`KL5`!9e&O3;acZP7m36-gu=W`E8#QSifqtHbV2F ziRTEZn6Qx6@#!3{a%T#-wR60%v|mGWZp&^_ac{WWzxslG?ZMXttgkd35d%apaitPA z5D3EVI1F;wagAV~u}QqFK$xJNF?bQ?CsMoVjno#)v+*cHqKe9pN1sWP@XDAtc~m?# zAs@<56-Z*-T9jzVAS53LcC`EEWfa0h$$HP7<&i=2ns+tBRvXzwT!@eWOZ2Mc*9pgz zsY%{c#%iJIiJK%%+5Dt#K2quA$d{8!DwF`*R^j9zs%YcF(L``@j8f%KP5;L|MtoB4X#op-k)X`#W(&&}fDN7oWdVc?Qyq^)08qI%oD3Gin>d8kaZXt< zR57)8?uNnVtA4=E9NlMLWLXsi6P&m%MUA@*%v9h@ZQ&P>|t%Jh4tNN!-a>P@q`$f%M+A2;e=-F@U*>*9E zvmwu3*WB4vVVUg_81LPCcC!b211p8!gz=~=vsO2_n2Li_2swAMdZc-y`_9)*442mq zA4(hrW&2X+g2u}VbF(6BKHu#!f7?hko3bi)hZdShS`Y?`cqprEuxwsaB_h~H7#{FR z9}#X5n1so3W#$^I)$Wrv+|_*Hx`NXJbZ$6=lQtb*jRDIum_d$?O|q{X3liX?V&cTH z1Hh*;qNWRD2SX|RefH1Gn%JK{DB&8I zsPN&>c8X(U3!~@${3`q;Jz@57gdpO^*_3^qI*I#LSTaAydp#jT6&2%$zhn;1h9>gf zQx8=7%plCGth5N6c+Y=e1HE$9ewOk*DP%Pc@}h)E z#^S%qBFz3dPktPsYIFpl73(6@Kj3CR?VI7e^mAm^Pd{R<0G+-6{yWQHe^2?$AAF`f z`RPxWJv;Z6jjOhoom)4Rciq3WJpaloF#PynSjwplFzSa7yv8^`1%2v8fwsN;_>Z!O zn0j2|$h~uyua=YN-S&WG4J*5Iz-wVXvz_f#?`Z~C6J8(M2)F(krD>zl7eC$-kr&~& znn>Xbyl?VW{??y|u)K+b$ALaPv*YigdzMpGu)es8fHZ-kZA|(AzO6xU?AOs|3TN91 zcsDNYAp|I7nYBM1p2TWWmJ~udZ9lmR>_?iQk2Y~*f__>9Y_6jOas_-9Tg!9;7r!nq zU156!h_RZD+0>JXs+6;%ge@;U7cQ4a@3|LqYG@dAAs)$F(1>^9ix)q(J(P<3INwWn z^WJ;vl)4fxxNb7<85;_v(s>nL4C>HgtFn~&dXjA)4?VD>{MSGD(|B;dT6z&ym!h0k zsC@GSca;sp%gbF`HkDuf)nDi6HntKCabg89J$~YRdFhqc%6)sb;FINg`TEzML;1Fh z?J=Bqfudb28|TZ<{^_4GPn^y+DwSp%@y@Qb#hKHW;`ni5>Q%h+dz`5&%pBFnICQl> zZEbNx0C+WRl>RE%dS$%uEKN6D>nGu0zl85jERr_A0j5u6X)mUnypwNr0Nb-#1Jsq_ zDA}o#{&r?P%7;3RPR^EZe)}M+)~43dic@{uPH6ck;EboU!P6Hn1Cze8Z|{zB1$s2d zSpK=6`xz9JgV2BW;a}%CJhnV_bxq-00KYb~H{e4C%Q(tZ%go}FW;E%JN})36go7kUBeM?eM~B@+;_2$+m*R!wK0cuQk=jlK!Hkzd;*hTh0)ck zFe^mJ{Me6t1f|3Ksl!#uzFLkRKUPkhIf>(}Vd4*=q^QSM9~vIE28>IaMej+YpbT3cu03|x#RxC@e^hD?mg_k+?4%^VLHvidIKZV zT!Y!OEUh$d;zVp6^_aj{!g=Z>W7Kugy{p@@T7UWK^)MFB7q|3R@~o|H+pkHxtIpC` z+vBArfiSRaSKY)jnN0U!$4Uam-9Ch>k){jA0VM@>T!90sdc52ug8dD0V&5Zit|H_s zILgc_i1zg2T^@mQh*g=DtJXx|T#qO1W5B_cjzNwZ^Bm||1Z~R}5Y|%#i@#l%LW(sZ zeKbU7#rkL}X?*L|2Xm>CLx#{+$-LX9Y*B#;6gG7pg~=zKt2)-nw)fyfO9hvX{Hh5% z9{1_V!+fc}0=5#Fa8=3ED097*mNl)&S0BOob=F zKN^;x#vjKR>;_HI`7*j{lH7;9$zkq>{QyqBX65d$fKtrYCJ zKYQtSD2FWz(C{VTVAUw{vbls+ZL9q*&*4~0ESjS!Fcb==Y zjV8%5>pE$}9KPt8jC5v|Tij28ag= z0MwrPG<5-=Y=_^KYS!x2@o%+wS1aE@3PA~rAuzJq(@>`G-5Mf(>KIX6cdONPl$!JO z>vE36`{O_Pbouo^e7d}O=XRW+G5!z`!9ohHbg7nC$5X8VugIr``Qo~zPDB#=w#5oa zr~Hcm*wk6S4x#N>HYkveBXD~1#1rqntDt&_6^DKAkQE2nEmZEmV^jIXU-{ZzZJyR~2MZse_w+&@}B7Wdu7KEE~p82l%)rB>+-4W*D(`6>*b;IxT z#PAD^nw!;s4uUtznWf8yfS|B^28JG z#j@ev^7QAP#6b}Y1G zB$@m*_*%>n{*`Y|?f!}i_LGBG54I9KSLEjTMBB|k1T_gK79DJ-rhiRiydVrO7|NAQ zm?wXke1Z`TJ_H*WE1-Y`)qEW|{5ANJGV*M8UKAFx5=^Q!mNS>R>P&7_puQ%5Z=9g~ z<&!wMr_5B;@S3&1);IfB(}tS7*2O%@r&fX&)|pcIq!#8$+S>M}UQM=5gbeOFcpw^q zp{Q@6gocZ_{0m(#;Z;{RKIGf_IJ9?75s z`-S)IU0|07`@QLF3#E<{R|N*O#U~CNF8}TS@ZYn_x~IJM>dOdmoZ+hg25e=>+_x%I zp*i3LtM&tEr?10M?%K6GOq!bEojZmQ_;z7F%P}l44SK^)Uyz3m>C%S?T(hh!_*u`2 zY44_uS=CiYa0O6P+9@U`C$sHacCt?p<^ciU%Ol`MhcRbm|9CwU9FM=}&X%uz<*VhH zZ#-K*^M%isH|@J0EXGL;&X?lw4j?-Ty7t%#5+bN=3K)Qizlcrn2LJ__*yC9Z2R7X> zo)rdFFpg%M1g^+rvSHHJ36Sk{Qns56&-)Z0GB95Gt8r`zcf^q?@SJSJjhYXzf^Scl zwQ5(OjAIP*_pN=W32?20%6FZku@wR9i)FxT$BykVYOJ7g?=ffB5nQ)z+ZtMV6?0C_ z2K(@$j=Ud6LK!PQ3dr-^*-P|wFMU41b_ktGEu)|JvT}2|Jpa;5SX-<`NUD3|6-?_` zv~IN>nj-hGBI23MH(}DJ5N86`a=rq~_t8o-b#$qks9Tz!B7@4k|WK zlE5%_EdkeE5drn1(5A0lNw>|yEle9_+s-H_Xordj>mz*?*X;i;Dz25s6auuz6Q<9> z4c}`5?_N(=bHqP?`xwuTb^cSHzftV+s{$f(toTQsQ5MkoI$rWj0jhmln1RmmU&@3`(kIP#2W&$L%q(@MgXc=tft7L^0;6P-dSV|S~t&}zuj45m;R z(e1#@1|byEe?15f?%8%o+ulAbesoTG6CrvI#e{XYF$(FftkW4l-7#i9CgKyowV}4N z(hXSQat@*Xr#|>z#?+Sb&wlk+$~gOByFd7dgn@D}N=9km3b06LuG1=3fSG&`>Za_6 z?E=0N;M>6qm&#A?+QFW9EM!=*e#=|mRqnj|LE5AMFk4pAFK>P5q4N2so-A`CER^5` zZRubi^maGaP@g5YuJUJp`e)GOrFc5Om%Y1s-CkODZQG0a?m=ox4*@&JiB?QBE=?0S zj55Zk3NV5JVn|@iCzvx`9m++R!jt_Sryj(QWdwPL=aReQI2-7|6}C_il{HYc&w~gMa3f&v0AF40eDJ_asfc|F^}-6 z{yLCuxp;01BRon=(n$;KTWLL{HRE0Uk{B?0bClg5{rfMV)LvIU{NZ;&*Qf^gA`McQ zoFmaBE4bV5*j|3%iFcQO@X!A@6yqz(BaiMbZ+>t$N3FfJy!h??@sz)jqb~2ee-D0a zdfD1>lJeY2#VS1t*&~PDSAGM9?nxZHT`eE|=*P+rJpQio)YD&LE8Pf|b8AZf862Zh z_a)$&&2vaO7Hhl2k^0fPZHBEfRdFGWQyIW`BtZ|SM}+1H9_D`=E%Y)Tg<#;;7 z;|h1hXU03Y>5-C#%`*sQ9f!eXlw0(gbaoyKi#g(XY@o1pp{d7hDwGx44DEIhD1_@= z?-JXun9AGNJD30fKmbWZK~&1oBS*?tp{uJ<;;k6i3Vmd&;h1!j4>Z0#vB%?KrA_(( zl5WLni|0uMa{ERca7-!a+Lb-{O9*|Jo=aD`RE#?xMOi_+rO}Qt=Ma4^+{B7$1j~Q{ z=AhlXc9;GYt3tO`EykMYr~<=D&5lsg~(fpQY7vr{bEH5h0q#PI}+T|Fq%cNMDSz zji9w!Q{lXDnR{C{ea&C{v=HZwai{eAhPl$A*0zDROq`#rtbjz~NLIoaOrUmyEZhcp z=q3h$jEpODUL6DysqFp)^V`JF2(fz!&np-ZA0mV&g(xEf;E(qXWYcp?`OOW%h8Zsr z>wSWn@HTGJf@ls-r^_Inam>oE_Ln&AGg(#yq+aB2tbAMPrp&an&D)lwJ~c1XdRev9 z-TUNV9qL^jaNMU!l^F7h1b%Vlhj0lWVQtlF-cA1eR4u8YKD0@>Y4Tmji@S_B-qnhw zkebA_)}dZ0t9@w05}Pb6+K)fP={)A9)~>$gJLUL9JBiyqnzc|cz3EIKW$ zPYG!51QYRso$ z$TR~Rhp}}J*8qEGW!e-7reNH3cqgN+gFRQ_r zWXC*@c%EPH>e8Au>&xAD-5rL$Lg{ANwQDz)0B3WQ*Gg9K$6;{y?A{q~+#mYThsxXk z^r`Z%f9wB1_!&q&JrA`Co&Y4Us{&&SHQ^v?+i%h(g*+SG!$1^R6;t3PR**e&pew|8`a|N;*e=UQtTb+eAr3qw~Ir!ms9qbxdUy%!Iy7 zgi2p^RHmSK{ygUiPppiIxO^BF0WyqGp6pxIuSDd}yn))w=DI5omDnC>bD9G#iy`J2lm51$j zg&tv$&R7C4#G7`NGFv+6qbXJw6^N~~47_uz<0lLwaLh^$LWSd61%zWyShQyQu9U(> zQx=&ai1}V01HxN;b)UHV+jAr(45oDtdNy;C3WBVX5?Jd&U6Enz1C=NTk6s0b25=aM z`RZzfbH?E6!F4eI_-kO*Y?f6gSvgHwWhQlAB^s+l$O;}6k+~NyYBZMb%Q20Lx*_72dmOi~a@tFlvL}TC_}|7|MzlrmC*ihpsxPi6b8R zv0MQn-nCaoAAKTxJ?3*QX1b5Q^{pH$wzsV4o+!WZul@zJjg_`lE5Y|m^ero92pKb^ z=|)pGJBRXt^XF-Cg_r%tc(WPz@7z(gZ{HCM7vXaad|RS%cSjl_Lh%6@dygd*RZA851*O1j9qk|gq~9(A z=*M9IL4A_=2M_LNjBcc#SEoEJq9)-#oIh5x3NBrhPa1U7Ua<1x7YDWBb z-fSNiYH3LGKKSf?6OX&vpEb6$LU|+>7%`wb=7 zw=i$vtcEyR;tU*mf?kqXDYQ87)8{Q#G`~R@JI!a}<|i4N)|(8ynx6Xv$x-L>iBFKq zckR$Hms)_xB|Gn6&fw-b$r%iZV_NT%jrBCxnXkSN!6$(w)rpMo{QFfuGKDo^lPv8e z5Aro#5?D^fbbf1{D;bowHA zdfPj>pr+n=V_rT7AE-~K5a0UH)USzVsH?@d*E(?aC6{k2lTiiN%O_8l4Ntr+ll2^D zUTcQvq;T@oN%qE`Et@cf*VDRA^jx)cFa5S{JDJ4T3zpTj!Scvk-ok`6jmG#Y0>wnx zzGEw(#(eQQ`#}*fbWo!ZFLS+i?V5yHlN{f}1Uf~2@bWyFM$t74Yp z@plt!hjL|7!QM+@AuD%jgY8Lhz7&kzCUN@AX#`XDI**Nn5jlJ23>Fx}n4J%$56^)Y zdM3}x6!ogGF>~98f`&ZYvwnfqffL7%!+fxc3Ov@}E!>ZN;rY;-SZ7s3m{E~1800~% z^6dDte&U^qq+L6=m7T0^%5=H!J-Q9+%=cDhd(mGIj%H8%(hl5%a*c zB~cx^ZKX^fxK?_Ul|}N?JauIJJjX8$!(?9LXtwJJx@%Ar9%IYKsf?*X6mnM(1ZEI& z`#7qvGL_ays|hUt=raUi>t!2M9=Vc<%N{E@1D9m`i4ki&)sD22>)~0?yQ6d&G+|&iHWO>uYRH znPHp_QpX?u$VbbbUC=vdm8*B3%eXI<#_2Z$3A1?pyGoLMg^65{NH{E|f4!c&C zAN#S7L-Tgx^y>i1uJu{LOI7(=#nzFS^r9?4??<-*XM}TC2x9`0XOI0TIqIFOZU-_r9PS3MuW?_DK8eZ_-Hh;MS$1M-DNr zwVLCMc<96-_UzBhfJ0rJ>>-7CVPI4|)^az;T;#Cr`b*sn+xh@1-SfiK8d1J*aKIO%(UIY+igGFwr)o8J5JkKxPZTruJmJJ zFu?X8>$7^*I_S+swgw($t{4U8^UQOeqJjb&1%PG6%8<5op;#4{RZxiUsRds)RTw$f zRr;Fh<;6TSQMxA{=>sNw3h~aN$REON|0+u28_+qojI4vd(s7^)fNN}7RI$*9HQ#Es zKrSENT%Oy{@wHe6&FD7=|0b@A*X>Q@-hqj=@wdNj^`=qY)5#8W?kW<=+!2@j!1;tFZwY<`Q{p?>SPt(+ljf%BY!RYXVj*2J zN}e?Z&zZ1@R||30X!7x0jc-VZ3i(-6C+KJ*n>JQ6AL82f{F|;KZNi$`RgQdNk~2=d zjGv_SF>Uc3;SMnKO6PacWuCSX zKx9x6=;WGm&9BC**_wAdtjWyB+pebCgr?*qHm~~B){8uZyJdKp54SOGPS~xnfncKD z@;Z^kUhzy($f^t;2aAlcRg`mQmIu z0?zgwJIV+D#{0`Z`<34;ci*`)&e6nkJ&oJ+?8}6ywj5zQOTBwJ4@w#|k5JZ)LmEek zj<^J^lcQs69tTx!BQmi4BfDI}(LYzAvND`!h7tJ(#%9FjYNuri6F({z+Wt)*#0#@* zG5I4=9U#O@w*?l~!8-NXCYTQCrGn5HeiA%7(4LHEbtZZH#Pe*0y=56sI7|@kuLx1= z(A1R>tLr}cm8)?S#igQPr19RZP@GkE$c?MZoq7>3_oTI5rtx!u;}FMD00@CA2v^Pr zGBksjTHBw-5f-+=OE{QM#cxBbU&Ys}tTa8sHVpkV=#^e3GfE563U}M+YO_~$idQW` z><7z;(3rVJfxgz4PN7hQTz-U&UaqxFi1h|_(Yc$)@@3DrBo@5!QkYfwvjoO>jMWnv zF^@}fb>AZc$0tyLA?QbW1fF~JnR_tZrr;{L{d*Gynx3~kn$EiQa@Kq|%(z~*rx9Qs zD;{U%ij?(-^`t&^6<#>GMM8XDh9~vl6a8%2!Z!{p6>do{Y!n2RA=u_@Zj?aPn#NUd z%duh1xz5ADBT6TjRnPXG)XW{TT(8_efM4TBML*x*TU!I z$&Y}xXIWiPAWdYYaGPF?sOxHf?UHk6d_ zc=Qo02-cO~{nY2mI)xG#b0whA_e@see_9C)@*h~xY62@RpM&3a2HMH(yz}jEE{{I;W|T!Jl&G!ich@gd6;&TH7!(t-MGu9qvRILD|b;MI4K)Y%hL>B~5$3^f7T<};L zQqSqn0D7D)3(%B`N3}jJeK#-rVDXjwjRr6l7v18cu@|Rc<_P{zfjc)@DR%C5{9ZVx z5Qif|oqtll`6y@VsW(N_a{^~)mX|+!`uVb-t#^+-@@A~v?kzia-NgwtFE9qB=>@@b z1j`t<89|$*r(Tw||AcN|xbo0_!KX%k;8kkJ**DDkyD@?X_M0 zYIaXc?DyDa=mUope#%tIt)t0mJ`avEzGFpUbh8lv+(@saXIc2dBIX#*djHYSe!RT@ zad-m8Wq%+21KqUk6B9G|`Iusx-ZSNw|H-eE-D}sOJXIm()2979unvWhY0vbI8XWG zWd*{$Cj9Z1Pya8&Oy8|cS8xJ2HjV|*B=Z#h0`A*&C-vUUX$lv?8!Qkyj^s@~K|a$Mknbk0NfYKT4qox-pArw&ef ziPNMdD=5@0@slTMJ86=SlN4#%%c_`f>f?hK@0lc0j*r$|#w+kKtshzVnywv8hWjR2 zHu=`LHH~dy+$6|m7_)_!_YT4ZZK3d}gUy&;mgl$H!+OVW&8T^wpISz}?R+=I<+-M< zuUbM;>&zP}*oGNn0d_Th=R27s*F|lptu-$@vx1<;F{rJz_w^DJ2qj|Dw88u)6<;m9 zd}aFNdVAzW>8Q-&r`Nd`=Jdn&jaQReUaPqbT$0WTzkVfZA1$hbQO(LAZ`ySJ`V3+B zI4>vd0ZfKButM*|*@Xb`zz-#}f8>!zvf^m_H6znpUqR#&LZHXRs3CWyK;|-nsCW;q zD`fBAzaOD#3~l%@3IetZ@X86VSI^q+3tz!8HPD=b(>-aA0+?~^Hz!l+P(PENE2>WL z3P#c=^JwW*oy2PY#L=9?ob;~lnO>0D1^#+D(Yu-`LuZ>TCp8AHUKI;djU@D)W7+!U zB0$E*crD%sPYJL2)qH(t9pa3u=|jWvp+53`l$GKeFn`wBa-w9k9?7R#M2J6@w}BPM zr3iv&&z*yD#1r_%iRsL8U&`6q*#)w% z6w?qDITq#;dhLFGw+9#~-Bhp^cNKiKkX(+*wzSf-=;vUBXAn@A!FX-kzJ>FPkCtzK z)a3SzlxI?D+Z-Ag!b2?kzemJFkPIf)aktCug7RhVv0%W+et?agoc zxb};Ark@BioeH0=n3HeXcCLK>8|TZzZ@B~KQ&oZ04NaJHTMmq}!uB{!_rAOCMELJ1 zCpgkF3NPlhN8a)v%y1753fE_>OOyV_2i}`H{_EfRP4@M^9U6mj0=O)NY5v@kFsH8Y zQNc|Vbb>zK3U{}EEBQBcm~FQ5yhMd**U=Uwu# zO18OX()sPwB1P14l6m{Wyqh!$G9NB=25!l5%i091!O~AH-P{*`>C#xa4(*Um=*L38 z2a?uqR=>@wr;Bs#arXA=!Rhjaue@B|^Vq}XO?T~uesBcb%>lMt?O*y-@2t0>AN8H|U@zQ1Zpz$nVh^r$gH}r$z!lTMtmBK2yT;PcHA^qb*gi2yFb-e1E z$Sd=F=uy+wgf=)szopr>8=fInSUo6h;i=rpb(#}zR!&T_D6<-xg2zM=gft#Oti_OY zL<^-$ZV~$87t4n2_eGI$89FfsJ=XbZ7Sm{7TbDFCI4jX$L^4(@DmM3q+Q<9_K1u19 ziSl2^v++Vi9qY#AV@65D@8XO1bAj6HtC5|^AX7y zfMnoby=wk>aJYRKuIaPDK+toV;bT(S@OOjG0&-^d6|>xYrX{Jxt4E2 z!|NdOU41rweKM(e*LoRl?VCJ}1YC{NmTUCHNxgjXrS*0q;?{hHT`HY~H44GW&b-q% z#xXES39T@5!bpNVo0Tv~v>KeZO~M3o&-+>)d1P=ez@n2jRcte=Wm;M5(1~MyJXctx zAt5qt-pm*Eeaf|1;Z(21_f1fK+U~TDZR8d&YlIrUP_u;I_Ek%1VSC%lMUOHB6mv_1 z0-mO(zHDkt9Lu!c^|CGY3D0fNqMQwM0yj-wcW#VSACh&xh{pss2~+Q0`6-;uoMn>O zy=zbTu^<1*^6lrp%>>ZTBn4vz()6)1F*oNiXQZ#bH9wBlFw(7$=34X$v?4W?mIK?)wO%-1E;>-^(nxe{c)hc!eL8G{VBZ zuwR6+CgIjAd-9SvjR=jFPRn?!#g|!FgE`+CR>$2!VclHS7zDnW(+|K+&~UF@-y9E+!p^Qw$+Z#s?*`1EJK(?VS!b`rfpkF@A_jf$S}f~cI*JvS|^QzSQ@={jFY)#<^TMHPnT0?uVZG76;%H)=F_VYx@O96|6iXhFYP~CcJA5LI{pl&ord%0e?}33ZCu~yL$pLS zL)K}v+H#zRhA~z=QH8<7cyb$)^t37{C9NuZj2qqx-0(LRgXCy=3idU3?-yMbm`dFe zx+ubboZGZLt+TYI4)(ucG~VN3`w=8*EzRO1O-JcND|pWsF%7pJzM`pj+G!rd^LiEK+m!IR$d+Hj6Mm&+{_oS4JPW%p9Q`O!DgG z)S5YP^Cl+gI&=Kr|KRCz_pVpUHk{{8gC7F}tFc(xQ67Br+bC{XS&ty=wvikBZrG^L zl$9u=E->bC$jX?X#B85wg>t)Dk!F6G$1;p@T4^U0RtmVKq6l}lu`~SYI?Y>kVeQ-}%w~{#!K0>qnQMMHIuUu1> zgMW`c@=*ElPrR=jKY9jhH5Apr!c%)Rxo_uq_rM43sNXF3Yn@ffjiGECK#@i4Msv%M&-;E~mrSF~<7{3c;l)r8UbxaT3J>aGK^=%oS|aSjNIf z|G*3u1{<<4B7e}`UCr>FD{NDp+bX@!eQMqS9hlrA+*40troMg~%QOpD8!B!X*BCXg z#3F8J>n&-_!x2P05*a)6A-|+DBd?~Iyssf|xbHWlU>{=D06!}nP3O7qRH7%>Cw3sK{p6MD3@rqOmQeau(#2%6WXw3tVv5Q*Cjs}O4@BCZWMdw_N>eSo7<|FdUxYYXP$5fR;4m@kVwcfR^iO{C!p*D#;DW|sCz$R`}b|<_h zUMQ$3I9=Pk`_8zP4A|~uN7)&))K8(JhLL#TCNT0bP4g>vrsKh9P0egW?mMp&l$r~o z=1Owzg@L`1rgvV}{5nP3ZXSG27HvL>R+;@aslN+tZ6gxc7PvTKbMGq!JM*u^yNNDr zLfmU&+nKuB-VQDkm&Y38bu#Bo{=RDj-`XyIEsu%z8WXa|LG`g8Yy{_d(+K7FzUcw> zkFLr}FLMq8!E{z5jib=+F*)ubbANhZSU)OO!-2WLIAr}@J9i&>p^kF%5Q z@b&d&2vb`b3G6^bzrN3dGAZVl!2m!pRd2aZGJ@BUo-Ff0GI2M#_f z=z*bvU1gYJat!RGRl?56SOGv!xK6YxBn)?D+IQ_`9P40#m9|v;szQ1bi?U3sV6Ew~ z^>M{nO8}XMN;?(4U4==-@=hf3Pa5j#aUVx%8OQAnS{sNdGWPDvbDU|Z;BjDQ&zvsD zjvYg|Lckz@%hP0k8TA}TA)tkYry^WLx^xv>I<3PVi`LA4HGMyfV1Dw%*}$WY0qdor zfuqYf!p_xWkG#8l`BF?e_w3nS4jnp#sqqE+@<4gu!3Xg&yt>StJe71oOz&(HS@lp@ zg)t8n?CK6k~K%vXZ7}F3{>AD})|-2oo9jQ$X5E9G_F$rY!Hn zoN39xUthBdA3ShgGG9KzJM1aK?NZz&3sYA^TxIV^;jxsJaLd=KK?TUj$hEB4%z^_q z`6yMbTDQHt_{y_o!=}f|&;R^~QIcRfiNVRWYnR!sfYV8Z;<@FlW?w76^E-cxfM)Yy z!t4jSbPnNP#dPmdSZ~U|NnPCcEGIiR=$BRh4S75IJ} zTW-i|9$1_9)|Gu2TTETu>+7ESaupvCDDGCR9ipG6V;Q3Gaq;3gI}d>tkNm(-hmSJd z;?O#jOntOTCs3_|LmZ?~(_KtbGF-akY?yA1+m8H$oi7uef7 zTWJKn01Sm00TU3+5aqegXyNXFvOFdDGov+1tEr>wO4X_%h*Wxc!IDmopb9s1uIDXo7I;>BWKt zTHA$C;>xRV$`O{VC`(Ud_?NTaeJQ5$T777i?3nA~EO}wDl(A($@swxB-aKP#9yl-K zo~PhT_K{OZiNk8PH&i^~y{onZwp}`BCUk3rd&i+;5crz8;{=7oAV-gh8=6Y9z&oy+>H{prDDCjS9yD0lwJ{7Lj2@SA5;?zwX)hV>C9v*@YuxgKj zO%Lz$;HqBfTUy;#LFh?SZn-Q=xVH7?CN!`EJloW~G>qGtuVM0^{^F35xlI1n`OLZ3 zsGc_A8S3tPcPoKgiE{KI0=`1@j%{1ZDJ(_~A3jo^e0s9H@WQt_cJN11y}oSS@s^eQ z0^TCTKKJ|!<>gloa>B_v@{t&UN8p>=KvdSa;yw>inF9wb&lP|BQc~25B2CjMHce44 z6+6_4`dD}AmcP;!X|t!8WD+1WbcbKtEqw^`K<~t56>=&J|H~i$hvg@K;e+KL{exd3 ze-&ic%U8ef)$-t@kLFm`l_<^bx??Ab=+lfj6izt$Th7)eVd4BKEObEYnfH^>i}?F+ z+=I7MQ~a{1AsmjLI9@iRR8)E9oa@-Rj$+wyYQ3rz3?vTTWdI*5ZX48h$}BvM7Cmmy z693&kD8DegVVL<9ev0{63mkcc?&T;2$vD}CxFTzJVF$qQ&j=2j?$d_O(C9219f zSY@I8uJc5#$Hv(2FFjn2m6OWLXG9Od`^Cw_r`O6N=_|a-v$nu+NuV zYK0Ry1cI`8G)oaZSDyLeeF(7CGELIgSkW{Q+4|IEHGa~oj4;srn{+9Xu;i0{Xhcb& ziwJxh-?Ww~j7VtxlAf=$jez_T9s*|s(zIfP)eI~x4+3D~HXXy5XWAu|&Bd?zHTNAj zqznUX13zhd(;jorb0x?NsfpKQ>+2d`Yhr@jC7mzL%Y3L2gunI);a=2NlV%GIW7?!? zav)#sQjTepz`_zwT~qtSCrRL+PrZTsc zd0X6tT6pI;SSYgQL4HnX?InD;Pd2w@-A4J&-#{pdlI}YrB*b?u{Ck-gS7X}FJjnzF zqsuIP=FEA7uC=VFt;__YBe5BnFn|Ehy|J!vyO&#h zb2ZZa%Q76sfBBV{E_p? zdZN*1f~|W>Ss{WM5%voE*YPf_`7af5GzQlKIP2pLK|=^`Id+aVUx4AzSAxobz5DjX zOMl%9SeYB?G)e2#+}K9*5mwc*5M~JHY&vXQjpuPK5!^1I4}t7OZ&pL1ETZ05Q1D!$ z{ZlZbW*Gs!og^r!(t+mJvYTeedWa|Jh6b4@6g-od?ojRGk zde!)@(z8!qL74uNc9@4u*(Ll9eD3Kd%aLQxm7P1caK`X1#t7%Ev-LsG==a|L5XYI_ zlVc;Fdipu~#{HTqkXZG{D!`Q{HY&rMQ5$aOkmStUVS$6Xp2~{6yaRtxe)Iq*_w=jq>c<~IS;MK@z{0V3W9(}Ba}6H!H*8#2 z4j(+oXFqKns9Qm3!~D&a;3Q5iNwb8$8A5^351kl5d8d;(6+Bwv$ZMQBd4fIsn)FuM zsZwwX0bIesmHvJd46A|Twd>=+8Uc53O)L%cBcM`J zGytQ|maJqX%`!uI0m^}R(g{4GT+Pi@%0ErmJ}kKu5XeuZzyR$Tf!3#ujG<~8QR!5{ z8YD`Ui`UE6)hNF{ccRSx@VzvVamQbb@Zo<1j(8^|{rd}F!t_7pl|C{<>#wkp&NxCHvC(1DH zy__2~0gp3R@=_5L8rx}Og^S9YW#DG~evr;FCoNkJ?O8&HRFP5MEsUJazUlRdZUm^!8ghKq$qsN#B zE=9rq+JP6#{ugk5xV4mZ>-Un67I-VlMwAHp+YpBG1JZ%aCyXr>XZC}0qNKzVLsVw# zq)*={oJo9bS={4t+^w;j|4Jp{$3wC1&8olE{lyR&`!Z%@ly!;jM zd@m6X13`G0J;;Kco~V4)cP+{!c?xn+CO==rVTcog?<+CQZG$*wCc~97d1!M>DJjTg z+&IbbNu7CalbdVJS|Z=vdqZ5q#n;Ld_+0Z(-HgL0NS%A*8fG4b-&$7o!W)nOx%Nd3 zvrV0M+}9-5kIT%H4ZpeP!AUz|{Fu;kn#;VL+RdfS*SFrczhqF$12C?xRM;g_n~hPL zD+Lf|(WAG?k3jxgoNF2Ql--nH@0+wq=T|55)G2QRM8g-})$n|O=U3C7&I{7lns!1u za0!fR>j_(&f7_@VV{>(I1AFasu48?A@K`ULWK`e|!vLH>FwnVI>z!N}YnFE72Hy5zzV&=P zgW1|F!oUauhQ~Lly?^0_R}fs5l`YJ03a6UDy9Z1Sw5!gWIOgoyRnA$bEIqUL*`Gjg@}!p6Pn zPNE9-w$C<*hYHxiQzm_(Y&usCd@o&5h*AJo*pZGAoVxg>_TBeRuF^aOan0MUtLa-> zX_y?KtHHs2$~B#^@z=P1Ts^gKym$QiE_H^%_||jJl~bqBz#t&BF@AOO<{taC!)u7@ z8TT+I2rIEbpe0ji{`;xFLfb|B9qin_JI>5xCgT(exae15XeFNUDOaw4ZwF2ub*_MA&mbvTa_E zFb7CdSNlV_uVml8iX%1t?qkn~XnNP7ItU_v@6=SUw#<7;6`M}JK!C#?7lO`~6hpi9( z^dppAzT^t%9Q}<0MFq(SuAWRVkJGmo$}?a45_QJ^0t&8cI8qwJCxz{r!0F%3`K`1? z6LOM)Q?^Cg7{KMb`V#2T2^uTzZc)(dyIT#kBmgwzMItMP;sN4vFNwjGtEe-0 zh!8%>o@o6cXo)Zl)7^toU}|bCv_>naZfLK0W&BeE&FU2@`mhX8@G@^5gh~&jQQ~(m zN1ci93NIcV>Q;bNz@YkvsO^%LRr(<zd+dT{#eXFgbm#bT6&@)h}Ni zEeFnBDyy*)Ts4GOciO~kOzFaqHp=&a4^hzas35wGaeVUpmGW~x`rh)Ned6(gjtB)R zo0aBuO4^Td^xiTDu8+9=2*;FTYLg}9^)v?wJbiY8XC-rLe90$ z!+-wge_p=)<*(p~Z$EIuU%|HR<%#$1DjCD@b@5pvUI_=ss9V?u;A^PTNBo_-V;=jA<2E+UWvm)OMB{b6QgLB{|Yy%>9Mxcok$`?&|@J={6g%B2xY7lP6ja3n&;WQovyU&I86=vP8e>zov^#xXM^|&pwpgAx3um{t#zqf4J6cc*^ zBJ4C3^|JqCs+o?fD;KVE=z-tKxf|hM^SA@Ay;e4&9T&Q;V7uC=P~v_xk3thuL=A;l z)ev^WWmXO2v6eCv{?%@KcKb${|2Re?l}G+!L>9cM9Nb z2g&&Q@oI5V`Vp%FmVJ=Qs{`5-F^gCrZe-bU^C&% zXt+Y~na_L%rshmmx3yB(xN$wqjqnx*)3GoZLIAOR`2J)jt@ixgix)1k`b7;rQ&@)9X|Cw1g%%z5O@%w*XP25NP>5d^6^{ee{oD`!iws_8O6 z_G4OxE860dZSB?66JbxqlJkmZZ>wzHuzp*4<<(c%y7FRH%M~=oMtjQW1Sbs)?Evpl z_E7IJ_GVABhui)5t|q&cpBX00WnvrL-lC6&muFrmm)RaPij|0hyYN-OcbkKby4+`b zjuR42p-5Cn9LDnK1d2oR7{S4(O1CLYWj&V8K9JrxkE#ruUxs31lGQ8(peVO!10c=i zv(`hin3})oj;%1>A1HU(dvty{tBZhi-j|bwIQst~R<~Sh}F6YG?t) z>cgbJA8QNyGf;45MVQA@qA8X|b9@jm_S{Q5h_wN_l}xGjy`!-034h6wl#WcPF#XQQ z%V*#D@iK0kfBWn^!+dAHZQiC;H21m9BXOIDHXg4-M?t$vM|rlc$m+>dBLr{TGPv!O zVVS8D5$q=y8iYwNi8W(4rhG#c>}p)o|79<${(6^n_={cU0G+o{Kt+X_rsN7`8~NDo z+MhKyW4p?mwo{1Zv~>`_Y;${gpXV0fz90eQC|5{N($t93qN*`0hNZ zb2%+`JPLCb-c3buHCwOa7K(=eTlr2;d&%h;SlRHF<1cG|RzWjwE!CuZ3V_mShBRZH za`>~KTo6#{i0(0KHskase&^B%`5bXdo>#s?rIZd8wem4v1<@`{`X@1sKYILp`CotY z-LEOfrS-MI{t%wxvsk`(Py5N{iTQe^^W+$PMH^_@I z&POHdM?Uf){DHiueEo;Nj`IBZa_9)#%PyQOySDEx4?XZ;dFSJgBm8e>MSq~|+q;Lc zJXFq}K3P8XsZYhT{-(_+gnsltDO5`{6T;3d+5^kkJ(`8a79)BWK5GO@hhKOkxZ~5&^OHxq+j9b&2Hi>yAucS|u zrk*vROD2!9=S*uJ$(eUG^E?y5f~*aH{#vkcntR)xH#JTubyHw00czA_DUr>x2EVDk zDN|3wNpC%PF^4IUiVEAiB=BQ4NS+8AR^s+6@63P?>CC&BC21;R+D6z}&o)NX4o?CKRvBqpzV71o)JY=>oernHQPtDEO9UM)ZMiI10u-uw{O z1;?`@sDP`Y!^u=aO~TVUX`1Xuq0;?u zUcPq{uIWff#`7>g?WJHGoRTq;xgwu7%(N;56o3ue15@!Rdkp{Q|K&Hz-3m73TWMt~ zl=d2CSqj&K)H(M}9W>>?&Pt6!>LhqDiAQ%=SjB@I2GLm_*Vq z`%$zg__&Is7h%2eXEmNOWIkLOk;xM#B7Vj~gZtjwCVyo_Y}*t}iRPpVogRCqkavSR z3Wrg)37C_@oU0h-r?4x0X&7%Zk`gY>2(2M+-|$lfKkij*m>)rbM?1#ScMxLd1mR?! zGJbQIT8c}K7lTz|*q;ig45Rdiiiik!3UN5EQc>E6urBV7j*<@op@O0crie70D?L7S zn0@H0unNE#6cls`641~}`WBoq?Q+T-u5k230L|nl5GWN)^`9{^>fTL+7gogU-q8jQ0>om3P3DC9EWC0mMIdGm zcvS(!c}wSUl%9U@3~uZ!z#+;T)VY_Q_;EHzn@*iN6CBhc$U1pO^y5G9uJWZXeYrgI z>>;K|jud2zhYA>JiCclR*imRd{MtdB5*~%gUCSv0Yvae`-h1xLO5@2RuL27c9rS?; zNtx$s*RP?-Vmwgy(6C@Z<0u@8m>}mDGv8K{0Xcz`=6t=n)i@%@z|J zd~VtVBaf28aVJiQ&*Fl7OtlojAtUrv-yteTcWm1c{8foJgVlpLGsXBia_9gGwF@XA zS3pZ}*d+~Pd@K+1FRi7c$yi)j#&&=ql$guNLxIV0Zyg+8@tRIN>9+0mc+m-PYk1xI zIP|+o|A~9jLagW6`^Zp zRvVQtZ@sKVTa$%4)wii73q|IU_DHWNZy}W_Yo=Y634K}I+QoSju~Uw57ILYjO2>u1 zoJJNB2m_?m}6}(TM3@~`ZHzA z8ny}cO|ysoa{2Z*UMeRJT`rHk{oQ3?)w=TP(GzSRgNNzkq>owrVTgasC2j|?T@&Nf zkg?PQ&2&y^g?sMD zGn%4mo}{#oJNYNttzX8kncf=y277vg2=>dS`ae#B54zt*lA4zmzsZ&I2rlX z+!SUxW}0{Am&hhIh$<3htN6_ddQ*-sh5YST(kG8LpGCjzZIdXBngcQA6WG)v z77vN*S6jbI_!F04A)Sl+wiYeZ+<8HM6+VVo-&^avkgmdw*SYFX3aJ6UXxdL zD6B%ZlVh5ar?zcPPW~irleW#mxVEjD(uzgYm6tW&Br<9GtxaRrGF^-FOB~~Q)47O| zM4j9$Eae%6ERwIOT68jfGdiq9bJg^&Qr((=o4$?r`oGDB0#LSt^F1-Wm(kNS(@A=) zS+N~poPn=qU6nDAkOw|CzzCQK$-JlBt4x_a>7!AvHu zzPr+<*KXUkWh>_VFxpxS=uAd0_?r8#hB;q3#Fzyi9nbFF7iJ2<3Y3;xojZ9>_DosD zaeUo413G`{7y<(fZeKt21cA|s(g6)n^?<9e;+}o?Au0^H%BHF3Qh+dP+Y$aDL)pK3 z=bd-JcrT0A+f`qgb%n%wF0K3iwKP~7A<}(qQ7&ZvI%a-MnwsrtdgtniX0(+-k$zbx z8Up|n1pOGt-gNcCOIoF{WEq;u+ir17p*kyp)IF91z()EhEM-)Lm#fH*GfnPhsPnpE zJkP^K=xy75f;uzmf>H0q{I?63#L*#rXg^NDU@ha_9Pj}RfU!&my$zj|)OO+Je2Trg z(onY$Oh-{7_Sv3%r|eiskYFiw_AFml+3P-SOpNi(&=1_(v)N~*!3Yn02PXd7_V%)$ zZKLURz-D7zVYOWf_IhguNdj~IDXfGUlF`vyuvQwHE7q%_IK&O}MW8fFy6Nh3rDcvo zaZbj=1~~@7KiU!)6RuM}8PQNL;OF*+)$A4RQ^^1hQ<46Im*Gs3HMTHj<9M9zn{XZgKM{WW`rHN27IpSFYf7sENd=pZ3bjVj3p|+v zzj=h-HQ>%z6bz07SIHQ@2ypY|!j)0>fnLT;6v2@)H5H$k8OxR%;XI020Chl$zo*tX z@tGlKYvb!bKMWAyEDWO@M+gT*i65bp7~;;tRpBv5Je8R$9Pkbmcq`Bgo3w*|*1X=n z-?)C5drl8HaS|bT9VcOIYqE3Rr!d-B6*i0;#)`@e`_X%kqS~>|6FZKUT|0Ni8R5CZ zC=tnD;n(A+T;aMnGRb~u7;)OuO+U3;4l1EHFWW(xl=PG0#}lOxZD^ z(?11-7deqc_-ImWy&V_n6K+&`m~Stz9MCBi0=+auD=9taufXp>1TkPK)=!`i9Y-;z zY4!`yIr~jI7>g@lS(P-v4j8$QH}r?{Jkn8r5a#PXU;D=~C!DqD5^vqFd>+f5aTIMU z!KZ%mb^N#}qNjEpce?FD>nZ0d&GD^o-F|~2id9X}Jc^xJ@D(Y9G@e$VUj(+_;LAfx zG3kw$E%I{Du~!6zddIgguW|g%HUvVVJZ)f~an3v2s&ADFA=8nso;-pQT$&(S0c37I^ll`nw)aj;UV4AY6gS5)_yWKNa$1KLMYhZB7-=_x zta&&$I_CYjO$lp!+KF{dSATi?!~4q5{K$LCzkB+{GO+aj6ND&M;;qZ39_1^d1vp(lJ z&v~}<9JUUL+xCVsU1vc)a0vJ@XH*F9;T-wD^FRKdW!L78^6&hmf4w|$@Zs{z9psQHVpoV;*&c%YA-tAor|XHw-*xxEH}EfQWE_N_m%QIB zYq&=m4h-XI$eQeS1^EV*p(?RGep4mg6659R7F$rDi96@co+-yaK3=}@jhD*9M?B(_ zm?ywZMM0N}7-&Q2Gik+1klf25`Q#EYk|aHSdD)c@4xpvz4>K6KdCLx_>m`m ze_pRj&3=wszjlD@a6&*pT-HSxi#ZlhtP6c;m3Yuiu!?0D<`7vHB^C@9L5YY&$FdSh zllRVMf6J^I48nnx38+McB4pZ_kO=_A+c^k?Gq7p`O-_AG92Ed+ye&&a_gEr-SGOX| zlWf#-Ybt&Qu|#yAw@78pwTEK8PlNsShFh6ae~^cE1pkwqXHr|=`q0bwKH_IPaZ)r7 zLjWyfrL5%0>oBAc$9OWB-Qp~#xmL<*AEc6|?)Di!Gm#|H?K8fGLx_CJvmM-+hT*E| z>|N7t^D!=YZaN#0zv<7~3eC-Xb9=SlCh?QsEBQ@PpQVU3`79&x3Vq+C zPvZ8^XFY4**{-JI7AC%G%Ry`+g$rQK;B%9weYJtPuWxzYj&I7ay(A*f+UKUNr$&#b0gjYm7(a0^-0EF1%UIm_N_8fTE;C~OO}k9TL-Gl&fZkmm5ZDc z{mIFTSZ!r`VGg@^&p+ML6rj5BBybz&~kUwJB-WT2AIwH zd86MFKLI6b7YvLH#?1V=1jLhR=%F5tFfZ$kYz%V_Ax02@jx)xS&~aTffmYgV(-*L^ z`9sC2za6WJcQVbD7EW^1j#v5{(+>Bfy~8m?)twYU0$i~J(b9(_B>^~)(&?9%kF`cx zr(-yVuy<(RZkVm9>XuJCd%?kNTTlqWRCO?xp0Rw6W0^YXhk0#VqU6(9>2THs))1e& zCtsWres>Up?3W%}9$lsYq9Eqj$Oy}n3SJdQ-6)WjfUAA6#l{Wrc*uzfwy@wmAoJ$_ zQn)~Ho-F|`HLf?DC2buls3IWSUkXjRjwSDONmfxXuPZ(;JV)BVg$9l52L}bsB<|@R z`8YV_i3ipFb{Q-53~=cqT77>%W7Y{1N&PCG=EMPlMOnrW0@FMJ-t;OM8F4?U_(gkY zWFP%dkkHaThXp@_W}j25?Sl;jA3ISvs089CYcUEp=8tam^D2*g=trwK*rPBgoRpQz z5?gS<+ik?l@brb(-}*^;Xz#up@FxIO(6O%;s{|T1snc@MRM%Xvr#vIB$l_}Da#Snj>9nRGD z+Bhz7)wnc;FBE4~>H*PD^dMAyxjtdtqPzFbwO5edPg?#5o6)b>)imRp% zXUV1vv zadU)@8#_WJheDh1v+d$ZXg|-~i*LLcd0y#G6p7Sh%!Bdq@hEvzT&bkgtL6&9*mSEl zV5x4~uCpqH`dE`{+w|J1!D(r5U|_qYsVZ|a_fZ^8Ll+c2UDKlM05?<|YXZq2=mu}S1w-2);Wb+$67_iAZxnO*Nq8r--T6L7#UoU8Zt%( z>Ybgs8O3r35x{o?aqDsO*$wT#~}76qPN!U%rEm?n_9)DNH&fKbKKU;3S|lz;7; zFO`k!+5R$1q<;(s2M7{60>1z5fA-(uLAZz0Li202JUNn1d9}zTYI_#Fb1O zU9@J=md!Jm%n0xYqyT}voLZT1-A3hPnvpL9$a}3Paob{Y=?b(A@>^$jgJ2P!70f9w zxMZD7Bx_w}1@#^nD&zbzdmHKO=TF|Ax z3MuKg?Moj1`oAgHEcH1r9fMFC?s;Jn-z6#EUMp$q&-_h0*Zy8}Z#m}aG#HGPHs!WS zYTnfvY>$_qyuW6Dn|*ECdf&p?_n9L#vp>1$2g%I0k~jCOxLVurnRa6Ij&?U1pxe~y=oos6~5WhxacbF>`vtG##|hFX}K zPG-xG41pslY*bRJuw+b7})Iw!jY#P=tXc=!58@K*ts*~ zkG2G%&SQ`o3XD)DB@V{AQU{-a>3z6bpSJDwovn1icklOomj&^tLa=$0!l{qG8MU}x zzy_RYUHJVR)cC`SjC7Y#+q+`efiWfzs$#pMDZ|>0w;;@hGAFeYz+@ zOWm5G)iExlx;~0uv{5{>EwM^8)K0Ilg}WTF2J3t_Tfq1Vyp3|Nr(|XTa2(z^ zLOlp{xPt3et{^kKX();yx0`r*q?PrHK7B-=SNIVZwj#t#5@CI^lb}*WTc2g_#M;a| z>sA2M1z!uXR%(?K;^rb&t|-aCmOIciO-m-XopqjKKhozK7c zwX$Q+K@|91coZy`E!+2%|KLCRt5~lN(;kE+aG)~AF#HH_M^Ly;OmJK#O!k2ThstJx zecofd7GOLOHG#2MXutTT{q0!T7ca|5I6bewsq5N8~W5#k1D+)ya!0d9H#C@i}rLuKY|1aXD2 zUKOIu)!-S8lomKgd?sui6EE?(;vypInQm+gikv%FCn_ zU;_TNz-a1II32n?7<^G!w0N~7xvVg&rP`ywR90QRb_Gw3ZH)U^a9tRv)EWgx-15){0m~L2@@c7*9!gskn5&@f zHkr8uUUWOr4Fn|H?7sLBj@X=@zF4kv?56kTiJ(gv<`q7+&5z|epI!Hav*YBLD$rd5 zCsf>8kKP)#XA=Cl!L|pz9HMM+9#Ed^n`@+HTc!fA@J#u@#C1wnYTJ0~^eMJuTrIAf zra1!*yUqA3&^s44;TdMI$<27S*&gF(c)2Etvk96^&wO{}7{r!F*q;cE;I&G!b||Zpk@z}+F|g^B$F!ZnRun1H2e#(jzR5bIvVG%N85-S2dwR?6?VHNYJExHsP;lxE z(5wvxAkA2S@coSYtEVoP|M;)`PT9A8Lzx)AR)*QnzRU>#T_`DDKtb>q|J*mqcVB)T zyvH+%c)6~z_FdeRHg!Y4!dFA19E+?wzNDp@4@^1NbC10Bois*;=RFjCTIs_VfDht? zikNwnkSghCSYJQ*-~%G_?+G3&u)8%)dgC~T{s*6&)Ae%PCfOo%1%=-dbp9?%P8ABC zNZ`0mLnmBUZ12Rxhf(T!f{OU*x*e)T`L12Ywy~bgoJ8P?74HwVBGNxT;tbRyZ~!E9 zvKmj*bNep>Nbeg&khUjKb;eGtvQ(jD`|G$`f4$b^=Kk89VGuKL$H0CaF zFm6LGDycYV9x;~i zRuzdVvz0bcC+!HoQqd-hV&=6kea9dB(|(#{O=oFzge!iEq)8V{3^F!}AWG);ef@6B zs0*jLYTjBKMJAcEO~jY*cx$=b@Nr7D6M;7?S0=#9uiCVgx_F*)EX#YV_41o%(Y!%; z^O|S*wr=~C%GwOcRoi2B-?f$Sy;5$I%!ax!uuSr{DT6QXYEzmYO(~UJi1w=~YEiY% z-q$qsDU_9@!m7Q@*OuMf*@w37ylvmpg0$b-YQCDomccmjSC|E^O*-GNru0|6+P;`J z>B%UQW%(6GHC>yxO;<}>?UCl$vD*RPL98a zMoR(6ON+a|ZGX+}-^ojEA@BIKJ%}}|4C2#`_$mrr$G$9wmaPHc*8-)mh1BE{WuN?S&W0 zQ%^rr&YwJ9KKF3(W=W>c zbxP$9JJGTPsA#2|bkBtLQ%G@fALh~pQuy)Pan%)hX7&zwIO~1;ZWvybU(OlF7QqFf zvTlv2%%Np;i}xxzSx}v`%mC&a7DL)_<=UmPX$u}QM7Qe1lCM%ILK1obang0VUpP_6 zBwHrLxdgXzJX*reZ9FnaKNnYVaD{Y}fY~-FjBOw)zxZ1fBGTsCFS{)#&3 zAp$-EIE$CMak|w;g}@A_dw6f(1_n7IZepg~VXIDuXLuJqX;e5UtT->JRNUr9#gO05 zSG^BU9=}*FUAR~tIk+PXwpLUHty>-einUI!hm8m_p0uG=)Ui`2aGuIgE6jDn=v$`0 zoujtN<0CyD)8LZMQv>EH@G985<;UQc9)IW<8IQs|3JreSV1>#k@3~()C#6mGm{5fn z;0g`YtIDGf4<9~^^>+ko;^olG1kGeFxD`O5+cA`eiDQ=Oy_apbA1z$GS6QJ_paaF( zI%uXxSax;KF-Et_+=s^yE*7Kgu#H;lrQ3Q?xkp);+x|CM8 zomdftkw=1^KX*P`yF71QrLl?taZGwGd=z37eiR~XyJM#SCLd@z6)Ac?-2{K0eDY~( zs`N>PhKdHgBW^OL(i1QHZC}M%fb8G!vf{j+Hqw!61Orv*QlWYX#nS$L`!cmv&N%*- zeTnU8H&9%t+}nuvl;dH0w8-1uD1pc?ZL!XcoH!z_TZf|LB0*2}($F${^3=&FfIj}@ zI9^FZ!4K1AjF|UYm8(LTc7k86QO*9>Ij*&MIqlI~;o!l8!Phe=4Yc-u#OV`S-G^~C zcgXF#S8%R@iEU9R7WOI}22h@Y&cUNsUwy4S^UTvxXq-H8s{HVWoVvldh{s=f@x^SN znw};G3ZRs;68ciDCDu0i_uD9*=TIa+g7?kra(CIcbGUqZ5?b2@PTGgXs&qshtQW7m%gGve@GKK4UU@{^vtN-8IGL)!!r3y2;>ZsBt+=-ZAb1luVzFnscwtjzP*woSPC zpp6?Oy6onW9Uw0g3eCO?p8Fl=AZoWEte0WvE~AycL)6=`xP{>giQh?I9|61|OrnmA zP}_1RaS#w{6CQ@iFXQDuk+|X@-wiTmVz7whCqHU_lUgDlzmur`RbRv&^V%v%aPsD-E)=)a^}ktt4t6@J$*QzjUu{ACE1rTBn<|zT;CP zMO#0gw5z_a{q&K~>*bhbL1-SO%)GKc{=5J3{n}?yA|y#g`$~9xKq?cisVm7+0ClD_ zd9wQF!L$$lUQJo=KI47h%t8zx)nz^^$DU{kKee> zf;SoKKq6Wrtf|G8!Ev9x7O!;((6*?y%kO$GgQmq}3|H&QP`VG3V{CAnb`ib7T<_}H zkom9m)FW+{S@h&0#C5NE1p5tPZZ~CN9mcg$re8PDt0)I{Z5_ppj>z`7(%HT+Us$`W zPr+L2nhd1^gnnsSx@4fFC2GvIwAgl;D;I9tD--8@kYN)S>`lg8jRp5mNIqWfvvX0d zuCrCJua+R034dqb87W=V!*J3!>8rRVQ)e23;%HIuNH7^*;bx#9gAw9&O*LI**N*LF z6pKyWqdJVhGgwBjw2Yzf7~vjO078Z#hQTd_nvg%+%^R=GZ=2pe$V30stDXO=_}IQ_ zvosm`GHu41`wEvj7hDSzj&z$;$jN%(M8JdQ(I<|ULB`Jg^YMZptpNfRSk9k29U)*n z0fYAJ-HlauPdSG2<}&9dcOtNM;tJXU&ce%q7YLAD3Rn~m?9@9e9F*Qkp5yK=^9x008hu5!PEYCdmEY{1x^5$FLgUPcFELBVs(2_D?g78$K$o%#h%>^&*pFtwo zS}`zGZr)ypAa|`i{mhG47I&5Jeeb6T(s*;wA5TV*vgn>_gk<|5<2{G)Dr2aCted{f zt?jb0GKtO$tx8=4;xoN%aSjaQu``NraGeO$b~Lz3`wR@FM}&YLLRt9kyYH2M22;D) zdB}4uRb${`6jjg#g%Dw-VxfATuqIHB0V}Tqhu`P4hsy|%&T-vK-McL)6|%`3c&qGk zjwrl$v29{vaxVM;drhFJHSSNSsQ>`Kq-!fzy6Ri5>k5TaDAkzf2xSWP(t=>G^PBd! zc_Y*}c-c5nLH}%T_2? z;VBICPLS@-Gby6*sG}FW6vhTQ`{<*Oq3;{Yk%y1a4+W%|m7~QBFc?_UR_h3T1$R_P zRAmAEcl>FK>qGU(fZs&9@d@4v-}>e^%i)I}LYXm<_nsi4XM~o01v_y^oOUgdPK(ge z92Lg%{Ek9{vGN2Nw@}$1$L{gR9?zO;IpWj=bHyNxj*Vl*u<)&?SXI2(cIToWpQ$jC z{%Ey#OcXjzvwJrl0l@GEYqPj$nVwD)<6A}nzJqyaTjkyLh>&)f*Zb+IS%m0KIcC%o zZ~h?x;(p_$-^f;&)8K$@(slf;x8BaWKQW>94;tXwOtU?$gTnYGDCWQj-eh;nKmE=h zl`lT~6rNez%Rm>3vKh9TaAF9(OZ=B81?)0>#WY?V2R8N*E&i4ATVH(|nmr0Wum)N_ zd>A{vIQ3$o96IuF`SAD|=0D0Jj{m$j4-ZX{L+7g73xsjz2=JtJ6{Y~yzAGWrz^2SE z==yDr<(r*l4JMtiNKjtZ1N&9IC^nT3vDBY9d6J;Ohe!*}!Dw*o*fEqHKcX}ga?o4_ zbWizEneyl(k1@tiL@DChB`vsxqQk&=*RFy;c-DP<{CF8cF{dD};wW&T&hZ;4x|owH z7~B%1wO((>5l&j!zGG|YhNn@ee+rps1vC07m z_(~J&`sE<{%$$M9n(vyfZW}grsHF*W`O6$;uXh$ApMw&gIU@Z5ybWD9DV7*GT@t;PaA(o_(d{$dN#H6$cCycxTewQ8DSK$!Q2EtI z4wao-M$53CDYHqyH<@{F zA5)*N^2`)ePzy+Lam`O%B+_ab^frAmCEH5bwksw2-m7U#Evd;;r)2v+sqBnxY>Lb~ z+m>cF&ztuV_AR+-f9mje)2`&H1@M<~^xoq6qBZ$lTOc6szbZ6*RvTg+UR9TC3C(5Q zw&$}hsB3U$P4f13ZH|>^_LFkfzO&fR6hs`u)GJ(Tjx3~2JMyG?oTHnp$V;}mRZ~0lu!OPpLPGgUNp|*8Fib!!jUk8 z12B15HZO9f?1giu%5%6l>;5;gaWMN!wHSNJq{ytfXI<^{CC(RjzwhuyqM>#&8BRITPhVHwpre!c!UIViz2x+)a237|clvpyN7B5VE^>?+|cmbNMg-i~pRX zWIiZwzwvh2zkgpCDCt5E#70fH^r2T*UaGG`oo?1uuy^caxMZYS2FqtM;;qHR1=4$; z$rw3Ct9Zd!0v{C!GG3PDrxgNBr=>_dx9uuH9RIrCn|>k)nKo8v(rEdVk@YAwPaqg3 zSXh`HDp{aU>lm*g#sTwe*@T<^$Yz3gAprK{z0gT~f?mEAXcZa+cy+^TaE+SRUiP!W zygU|t^Q3leZPEs{O>L?*cuJe<6Y^Rfu$0RIGPCQmo8l>Z*ttxH(q=R0d_l99xPxZqvhJIDaM^+5tn8nw7b7sqqfw_ z`eN;+0X=<0(!V-aM#i?ntd5j>;9x%jp-hI1n=btZQ=4Cy4i0Fw>SSw_7Hi8<*i!&V z&?5Sv(#QSc2Be$^-xM06Id z0wtN>bHn|}cw4`?C+uW4WlF^1i@ZqG;(64Z?g@Qa=9-hCBNUGFFV! zod`L=ANcB)trcDP=z-wJfLVwljQu*4fdr9+KDp(<_zsR)1f(?2zE{}tH$YKT%TRs@fzqmw)>Bd(Bdomz@34Z`IaI9=SLS-<-5}OyS@6 z?j;sRwq1oLH{hSb|Jl$!`<(vM9+HPPyAOIB3e0!keuu4Cc$ID1ovi{_Q5GolDtx=u z!h9-FBJeQhv@|^@PI{p5-z}{d_5jN|CrIzMBWbvE%HV=fk2e!k@b~s0+0~Mbu z?%5Av<+c&is5sC=t{1v?;>3w43-;hDt^&ig=PKLk=H@-FHKk_FvkVZd!2#))a8TI? zKLT7W+qJ3><^0SnFnHs&c+wnsnJ|GM4*aFbIy zaG~$(xmVtJ?T;Amt@H&Rf%^KphwPfBoP7e)-Lp zehmvX?P3dWS8qqTdgE^S^z20@A!{13SC;hJm7%v8b_(oik~(mZXVG|Z`SMlpfTMDEY>V<}C-}9Abyd12?ie3o3_j{R-~A3_I+fEa z&YU?7&vK{y_{Xo7FC2X`0=^zk1{YSSr$NAuZ6thl?AV8)Wn=Jk97Dz}lvD{`D~+ZP z2Jduiq*2Bjo0`6Za^MEu0GrAlJn}ZO-min6OnEG;w890D0d&qg_gcE^3e+hP69-5V z-qNIzm3&ZXS>6Xqfgt!$aZq|pZ}=& z7wY;P2=*7iFH62-G8l1Hi;zR6RZzmVMC8VG1eKU3c*HEk z^tnT$<)J;>Vb*cI#d_1Tgl3+zuNQGoF_71siv)-y8iCpJMsNl!tL2NZtJmti zea$=G`%j@E(I!lvWVP@0zQO4{HyfFykh#dsPhpablv5W`Up8ftG_IEXv|6vGsCwVD zv3-|^5@E}gIZH7@EEVOoe{6?&(ii$}nNc$MGQWJnbIWhb@^{`PQT}8hSox_oFxkjj z%U^lrvsb502ZKZIBQF2X`K}`?q zTZ?E@kqE|{v=&|wsVS<~nfCBLmu=->r$V@zr*1MmT zRQEucd#y`ZAee9SFoXLK9H7`v7Lz-1Ejx1LF&6e~C$i58!4NNi9FNHG(+;jS<#ea6F1`;_@vNd9x@1Hn8}^ z z-~6p|;Lzdn_PZampPa25>)AI7OuE==;`$)-q4lMXskBk6C2p-S6o{TEI<~M~VX$n# za@Iwo-J7j&Y*0tt`Fl0cz(_gngSh*(X*R%-C1`9LtfqtVrtr|qwi}))lP@#2*o!Hb z`a7_6A=J;)o^BLglm;*0V2W!{RzVpimv_(*pqDww9-YvmO7BnxK<}K3Ei-%@%k?#c zTm=B}=pMX^eU3$tm;jl_jD`7KyZhIBj37c7f(;2%CxEGN;+K2QJ!;bJO40+Z(DD?f zG`()~%Xowc8{45GK_1HaeUCY;w}>wtJFS1>q(b1ylPA~%eFnwqP-w68rWM$Yvq1A` zc2(Zko(ON$r$>UP7*RuT%6zs)&jQK9HP(mk{RN+2x8H5w>a@q@vm)mGOnMQA* z_uhF2JY7b(+fl}8t7S;vE!TTt5)T4k(1XEBSU4wI!9R4AdNQw6STNAH@qm5hm6ywx zzVuw#i*T>!+g)Nu$n%LyDmGkuy~GK}r?XRKLWm#F7$>~$ygYrwsOtt~yG>k+vv^Lq zUXPA#4t(66GK2!B3ii@Lu*Ych9EZSeGjNC#9XQ>gvxhZz3akD-*3~-*%KZrRtmj|{ zd0ac0$IM^z4WNh~jOW8**$K_9bgG@Nq6LxsZVmDs&9~JCEX_lQmJg=^8725VKt;RnQ&(^hf_UK^`ygetX%!e_y-? z-9B;=g~90PR>pp3dF$PGsN;C}AH5RwuCV^P_WI3F{wUz9pq+tEOkcf>N6ad< zcdnCZlWk#rs??dbaanGRg>?wXm8ZO*j7$*LRA{IQtvX+Xv3I{%*XKmA2k`ZO2FO8m z?u6h3+g#LLAedN84rUAgL`nH9&_yj8n$d2e1)n>2vFt$$_ZNQsD`k*iKR8yQX~RW` z#cBcK;qesGlU^(VF7PrhqSX?J=20NrvFPE3lpsnHF&D+2vIPP$#NOfU1kU<{SKo$+ z6R-pK-3`N=W8oJ`bq#i(acjL532X2?zQwB$1isV1+9w}-h3QEmdus3e&I8|?WKI71 z*5cx-!Xj6(+C=7A^D&K&n<5(QCrMMbZE14UcA1zf4{JM|xVF~IznMVo55Kwc3}T&Z zFdr2L{N_Q%)0~-OO})uvHU6fj%{U8(3Z|x2`Qi@@houK5OXZA^uD+}F*jn0AJG7dqDWEN;GIG2&orG&O<;q?AOgQ-w z-_j8B7|a6iaY^T3vUH1fv3L86jF;cD>?w1hwoVmfT2|3-<4QV;AU#C6GS;q- z%UH~DwT0LO|$QIo_6n%gerb@5ja8OOFNNl~@6!kBhua7|#Y^ z+^XfxJ+oL;fNvFSYA`(+!!Ur3tGFVLarw+khE7J#-|k~|0XHC*&+p>F;I;tI%oX<5 zt9ON#=PsGHt$Si!c0ajZ4>FMpGtfcl5trB?K5Mb}mdgF(D=tRWffd9)7oWZS%@~MV zZCmS$yvp-hj@fG&9aw2BHTX|m-aBq^Akcf5afN%_<7MQ|;Ta-RdFasLa(K_qc#UYa z|M=v|a{lr)_H%x%JoTktqW{a~uRyO%vWiFF9LD_l3Aj61zsD~!5K zYJ@)aIT8oLF;p-&BC~<>y0CWT$V8=B@Y87XUELeNL82mKO_5o3{gB}m?=4^Db&q?x z!OaBIvTJ;32v?ndl^!sk$>3Nbc9M@e0eWxmM$TrwRet~SKf<$wBgfXmaI=M=*E+y) zt%C~r23yNo3La!AoWEFp7MUNjD8c#&K6x7katXIq_vS0lnht)S`NE!A%By>5DGTOZ z!Nd0TvBt^-IzrCjI-e>YDyRnE@oMSC+re~IYBMYS0cRSl-~sP=V4Mv6VCfq|A#3x+ zTXUf)3ev(yCURl|h9ApP%1bLWnuD_h(h@!jsvtoMAHQ`i`9#kMS)vVaWSUbqt@c}h zb0c0e`ss)Gzlich#@;Oz#@`XoG8WWf!|k8nj+JynhS_;mUGJ-+E*2&Ft)f#4yO(M7 zHZq#Ov_^%b1?3b3;le+K$1bdpu}skyX@J(Y;7RDlJv;;Mgzl)26nxgJWpti^V_N^E zDZ*%p{#vK~*0W8o5gBgR7zI<|rLbG+krC}D!kZ}=MiD`qWa=Gva)d@}fXR3u5ZmuM zR~>h823`w6H}!F^=fQ0(-mky<3i#NM_YZLbDBH1WJ^t*!EWQREAuaM5;L|j^4u>P8 z4f2fQj)K)jX#NKuyq_SgMwu5@2BlN*zl9f$YmqRqo%Uaat(fXOkQR!oIU*EGaaU-P zmT6Bq=_xD$Ki8M5R04UwFYRz`G}ofujXVTb{H}yv{{hVSDV@`vlM1g+Mx% z<8h@;!a~J~xbKfey|DD?V9Zq5EusV!AU)i(;%2WptOc-Q8`C6$D)gcg@2Le8Ofv-a zRAyL@0@WB4Qz(f3*5Cf?D66j%d*!3@m0y0IdD4X^*JI`X`28OdY!eSF{?R=8W?N~6 z^94MTPUknzp>X{6mye_&;*@j4_G-*PMq${6_Z^Ij;;p>3;~BcZSbq8`F7rg6-@ku< zwm5WmPvV6GpMe{_^!4DOLu?bFgW$Gaj9T#JpWG5CjlRelH-*!XEa$t+wmo#9hdurD+xF;v zxPUQpo~;S;eA3V;2?0T9iv6Qp6`;~=fk-#0vwHC;gGod57!Xe4h}!}*n8t&Ee0s=b z)G1pWRgs-?m}|n>cRX3S`k*IzMrFLH%z2SSD=9wzH$d|9a5Y2Ymlxj>?`l2FlR7vc zi07GVfzo|cBB~Z|ex7~0oMSmjWZjpZeyBYC=p&^QA%5!SRgPw0N;BaXb)!VPv>s+9 zdp|=`K{y88#Y}c+iSMc(lI4*tVz0&&E>kcB9UzLxw-3$XU;OG<%6q4;mv>HHBG?A` zn5aE4wV5nVeldzG5gS45e6PVgiMbazSucLpXSr!!RD`Wq+a@HPS^1f~+(%<*DS6>b zKVH6+oqF(@gvsYknQOi>0g|`*lXsR=6Xku|0F&^zc|%o_7AKL_R=BoBwf$_r(;{G2 zFEg~|)NhKq?{YGy4U}uU(*#mPdv{;T`or>9ib$SSs63cF@L5UBTQWNqYag|FEZ1x0 zU6WRbwpW|RMrKUGg^Yij%glD5$!orpXCIT<7sAgs{-MVKTpr|+KVu2xk?;J}y7&zt zW7r?K=ucC;3vDf*ME>V@TybknwJsB{X|HYZN!3(0KYZdt3XwR=qCkJE!VH{W$70@x z)ojbyCJ1za*}hYzS=H{~;-$N&O#Xp``?Cm~;W(iWS$N#PwSi;Q7FZ;D2wJJep5@<4 zat*@pS(i+oxTt`kOQjzf<3;xDx=6^ps6>zI30Z-FcV5)n%-U+&ZnqMHx@UDjmzKj>b&0G8Eb0-nBIr|zWRTo3Y zC5tP}r&dE5Nw*TXcg|?gS~_%X)y+-;S}U6$T{>l0WqjN(sTTf;C!R>!>o9!^(lXjw z*maLoc+|q9Fd!2zp`FeQN@SMNMApJ zp@^_-T`thlI?E4!0#mm);I)Wgwhko*k*u>2!+e5fwjowP5r9c8x&YCY%lq~j{8p}@ z9@r!;$y>jg%P|-9ZLZZ4r6mqn&ExD9zqFut>-s)7#klp9QLG!M&s}5>iblWA;+Z1bup%tilhE5pH3c z$|$hl%wYDV&H``ucYCCrZs~4kQ0QL<>5KwC%sxgL)Ok42#l?X#Jjii(2zS%d)uJ}X z(Mu|!j8L2{A>bb!qYce`x6(jVdO;m&U45i0^7?)R9zZioIm5$S!EwhOK>*&r7hGMB zb!ujY6%WDDIvryL=Lk07N8dW?W9;U6KEj^uMYbl?GspGrkd9E0a9YMLxmFi7UUuW>7;Avv3c^Fy7YEv*0x>*>#iu? zXo}1t!llBHG%d=7bb)!ub5|(-q#SSBcFRb%S6W6rjxAsLn8)o#=?plXHlbW_4h=A7 z%QCg3j~55u;afze&@Zc5)&dP-lk5=+yiYYOGU zP=Wnk`lu&>a8&?wy9uy>(RMyNB#x)nTw$e0h?Y(9!nt9PQ@Vw+5SIn6Hd?kc%JEO% zfo*$gK^ORI9<6DPm$bwy!ZDTEE@@+qdV?oZv8fbOQ3K^Ev{*)61*h~wE4G5F#u^3t z^^G8}a#C7r+!WUnFWawIk#)>qaOr0L304J9$5h3Vm|~-o1ss$12xs@)n^t9oa8aPv zyTEi2YDg#T6d%%71Qz>W={vB-)mcGU7xb((z`%UN%m)MiUA%A}g>j8JpkU)Wt;11< z0PpmZdd*uEb_y^mOBggUn>L$9oL3R3veuxA9^IGtPdu|%t>CBS-?Y+V6%^h}(}kZn zrf{vNLFlmW94mNN-RG|$@Co~zKm!qQ?1Y&(XIt#Icw~JEY)HR_i}s2U%HUmat;n;eS>qS6A^`QQ$M|D3_H#Szv4^C{eqjg3I(IIb4jszv*^ ze)Cs|v4SOfd1E=Ue-oaC$_yxf5AH7;dS5MXzjqq9_^oVVVa=pWiphBB?I)h3BXp*& z2Q-VzzW6*e#`L81ku=gga~Kue5~YGpWu#*{hr-Q0@>e;jXAG}01znZ&3hsB9Pl*S? z7#KT4oZGkW0P8XH00p0E#Br4gdeOMGQ9M^Uat#k2Jz;dGH;|;|NKe{!3Uk|LgT+U% zA9;um58bZfR%dCFe98356J_VVM-w!7j-!Dq4Hb84|8hDF^Atd_g{+Rb#*?Zvs4-6# z*b3$GW=5_TPOj6+R>r1Thk|#RF;}4+g(d>NUJ?~o1ZY~xA6vP4H8Vf$_g=bUD&@?ZVpq4Mk_ zhs*NBcv-?Fr)OD>_cCs@y18jsM?=Nrq_{fP5*?9O0t_w&k(qQs87l<6C14(f*NI1f zuKv2=kM<9i=a1|yBQQqafBWMy0pR@*3Eq@%8MO7(o;L=p&DoXPqES~UmZ4Fz@8TsRBNJkvD+7!f0ahi?rp;J6=%EYSUG~DZjMjkz zd$UJaCZUhub_!2pTelJMd;*$KgLh4!-Oi{`j&K*IYp*aA&0-=vTtH=vbQ{(>a|z*o z>nMBC$@}Sv6A1KoSzG{JK%&1d(q|hvfj>rs)>i-JTZO~z1W zT&1Yvs8zh&J!UvB249mRr9akths(Rx zWc67r1+<|L_*^Ft-pfD!aTz~tP-6ox@W^ z=Ez`?dv|V+(3H9ux32yg;7J9R+d}MldcQ*RD=Y+;pcO9G*M%$hx^=qF(q1A(JLGp^ zro2zPVU)DeFJG&co(`VV$>3ElTiIkbQLW*AiUq|n2M*Ub^+1c6*6?M{(bJ*=OBuX2 z2%c-D(U}(zSoQP}w`BHnQUGtIPxi}C6ieWk7BkPj2K8u{Zuh=l?Wb*WeY0QoE_b|7 zFJ-EwI5MRndRlL*V4$0}ZnIvFiDF&_ndR}2di?lCexj~vwQV(%IAcPS%k=VbzEGbE z0}Tq&nDr=ce80%HoIb{~6X8LZ;#i-cS>j$$o_4u?s0#mh45|R)#SGpp&dbCZpd_tp zGTqWf=dzaCA>u-K=CnaNwPw2i{1%Es&ugEC1_;*(a^$Zr_0DsZepTSBLNsH8f-vW1 z6M#%*lQ?(yz`?R_-@eRg6^beWFI>F97*B-0w&UfPFpbHhM?|&qX%Q1T(hY$duMKH3 zv|FLUy}pjK!iB%}Qo2d7LirL&M}l<$1N2KGNA{TuR~3s2r&`gaAqu^TYgnkQTmyMC5(izMOt0WBJ-NsG2xWL5Y}v9qboVZ9@d|A!MY0v58Eb_b z%Q3%rChZN+3Ji=b6(tYt%bbx$N4TzV(Thxa?l_rW?-y~PdV1h(0B{{2aV$y$`hSZt zSnktmTIr-~jcv{tQici)mEu_gp;1#>t8o=KzX}e^szRuB5y%qZUR-cK7(2qK{FTl# zTVsjW3t%p8`mUG8VhF4l7soqFI(Qk!%jeROKIp9N7FG-)^)jbOt7i;d2G?Ax@R)(G zs7Hm8jVnq}+CdTIa~v2Q*B^vNb$9cO=REt{H;wIxa_A1*Yp?OqI{;EiRd^!c?Q49N z#l@Mj5nTJi6OWgVPhB8@C<-NLvR-S_0M~yTBkXOXeXg|2zJR&X44%mwC3q*}CPo?* zQaa#P8rx_L6xURbx^oMRTSoL2dG)n7Vx=D&BYq7$hHH3)cG9}`4`B$xyyR8HnF=GQ8-4N<#U71yizG=hHa>HX z-$pUezy503v<>AgUe0rPO7t+!t}C|N(*%~7D=HOfR&b=3F>vf%55QPF*DRa(8W>Gg zSiF60qHITjz87Q5z=jb7HE3zCo;7-%0bk~rV9u?-ggt$9p5*e~%1!Nu_+#6DQLmqS z!M+0i{t@y4sD0AxOKktBZM#9 zyGyiH2sOk%m0hZ8LLRc3gk-M$|AT{^8eIy7UxZ}dIj9_p55?uF*=-#z#IRJ9H@O$VsWU$)350LUO?j5xKC@1kpw!)#!~2yP;Ip)=mMtSAv1^){`qCC2(1ZN0 z@3@zcHWSbm)V6uEdePGSNPB^AEx0~wf7LeIC!Vadam|mkv8GPW)$Bg3mlWmCd{I|h z=1P6GjDjC5oA-fplfLcG{Z%>s?US~E_M7~^3}IRsF;}EICh0I~oAT?p(Tp}b&)fRj zcWI>WVKf|O+hm$Bt7%3p%)L)*uL>gHQKoc~vGa0l+@F_nS38n-Hl#MizvOKiRv8(X z66)B9mC!jRu^+^mHK#uui+KXEu`oLinSp`PB8z~Gio*Ya1N+LEQ)kK#fAnfObl@;4 zShTQob$4qWbq}4#R!PoaS}DWeLZ5zmoHKcc0UwMCFzv$|MYDIFf^w=O>;jy;ESQ(cQj4#`2O%umGCKTM4n0SsCilR^VB@u)J5;%MCPn{=T&=F25e zxd{&Crg`jh$H1>pnfjdH;p+Hq=c{8y<4D-zu6PB_%5T;R-ig<}FzpJvTF3Q_`0@+S zmtC7Sl#hfYX@6TcdydAW^o@pzz_CMi>oasJT7Ee(HMNi_5rcQrZWDRPhdc zz?!K2J9Kg%UI}*zMU8q1g2U*@E4t8y;r!VaPcmTE%*~All3El zaYHLyORd9p_(!2nfiq+6p!=AA_0A;xN*>#8KmE1J2+IB-g&JRS%W|D-O9@IIK9Jgvf@7X_xC4wqo~uM;hQYyVu?Gzk4+ zUL_0Vr4B2kU(S2S)A`qn6>fn!EG~&d3iD?2y*z`0tyW|O`)vey^mtFLz|xQP2$?%j z0BwM_-bP4MV3hV4tg;({-SVP@5N@==ehYsEjo@k12Ja1AD*SW82kGRM43hZau@95i zy}-87?TgitTKix-LnpvzVQimbNe<3dE2O7NxUI*rGOD+hM+KCtDAw$sZA&mf@``H? z{S-{T0<=P;o(#f3@P%(<40ZY5OS$g3p2T`+a7f#C;UdaRgnO;FDh%wew9RcT_fSd+ z4`FN&O807KUeO1Y4F*poM+8OV#>K5Le zF_At8&!CqyH|6)?wX=2G7WRs>&zo@(7gTteRz25KPy7y|&)`$(x)=@b$7~6L5!K>2ceK@)kA%m-cOJ zP1{_i7jBgq`s-;h@>WLGx6{HjLOk?_+tibJ&sgRi7-3%>cNH9tmwi)tSNGl5z_rfb zn<(VSW||t8!f-+t#+qV$# za(Il0{2XbFXT_3+I@?Lv!q^T&p3`Q2<#K$5xBaM!le)g86XrC*zrRZ-(;yB`cE4R#MfpT5-y--}X6|-+9WH1vZaqfGxTI$~5QEnmldZBwWe7 zn(e_Nn%qgyRJ*3q)xNBja36uFBi1Inzi{7yGO3~VueQg(E~4qOfBdY#yzPz8%v&2J z0baRG8yH(sgRoTO9I2^m%Jx2WTbv89S=y^ju<}s6sJP*N;97P~+!D36EDNebMuFVO zj8XyKFfxz2SGp(@fu8czg{c(Ng5(mRWiI>Lna9FNhER?1GILfpF|ATAfQ!s+7eLkS z6<-u$Rcum^GshQn<|GilKFfBlzoj!Z^a- z1|~A1#v|y3;emZ3x&2WgjdFms3mz;u*M;KBI<(>|0F4Z7;eA!WxG&XpXc%GZ=1q@< zB%!dPmh|6m-aF6i_6oz9X9$Q0kKHJCdSQ+xIm=k)Fv2Y@ay_*il~4+qJp|Yr9D><~ znY2uWcNybbcoK-Wn+cw%`|<3;)%4k(2FCPRoHgL2M|1V`7!SfZLYru>LYCXbC^B`C zE$gtt+YZ3AY`?^x0mK$s&62)#2E zM>+m6dwOxxm%fM_>kuk;u=Pi`V3h`1Vf7MFVD7_pSYbohw;oisBXfj5;)`kLIS%aX znbVqt#gdo=$6fa z8=@vK7S4LrtV02JC3)?ezY0nR7j3C%< zFK87?Dsn7O5^I~K;Z<1!eQa>$HUj+KJ-f?+eS0F{n^zp&LEyGir%&g&LzU0Y4{4s| zxORyTw#|NPaC3b&udu5g2kXin%2m;)McTxAspyH6xG{`ZwunfRcxRt1U$3#&NCwC< z2C~)NthYnVvyGgfqw;$h!Cr-o9%pkiDD5v3jFQOjRVgX_pbD(p1|?mGLPSN_1eW?` z1ja3!H(85lYMbLnI%^9Qh;dkp?Pci=T2q3g9NN|Kg%^%Ht*7!lx2rrf)WLHv9o=f8~)} zKcrh7D9q}1yPM2=;qFJJmhYuAx2Q|SnhGArNacz7^sG>kCtiEm-c`j6h*AIBV#<>K zQ63)ytV$c)71fxRuH&!N-liGOGxA9+#Np1S2pFiY*%TxR?QxIPDhJqw|N=9nl( zU}P-1K%7njV`vFvcnQ)pRmL{T_ z14|g1t5vH3NDHNq_&DB9ASZwete3>MQ)Us&Ks`XaKvvH$_8t32I`9bSfVe;RD3fS@ zvb>80ZfJB{B6UjGD6CozC_Matg@SmMF?RAaC}-u|O4R%(Vm3+5khbM_^H9{JDV3S? zSz2Tn!p^rzQ6F<}JwCCZ7R|$OSf_8AhY3efP+Rsjvr=C1oo`I46+Sk7p>uVLJIJbt-zsLO;2BjFiM ze1k4(+O1!PQHze}-D)Aebn!A}V@W1*`-~Rju*jv+AFHC(+n_3*MbApFl-d84yAEXJ%bF{1@m57q86X4)I z+{PE1*gh_rvP;sppJ>w$X`oH)kp|bi)3Lox;r3P-xkITf!)T zL()r`oBn}rtTxxcC1XpdfRedH7^e=EwpFp9m6$d2vcVi#W5IPQqJ1jT!8aK6)2A<% z-JB3GL{wy5z$2`)7A9~lZ7~3)0zEAY>;rSkhyZ}AKFy>}j2pP<+!Tf?>J}GNz`5Ul zGl8E_mUFLrzFs%W(+H`+QkP!$Vn=}2Lx%Yb0@!8BS5c)9uhK+UaRV_4k6NFw$%nRx z8qx7feE?>J|zWL=N__~b`rtC6nj>z{u&+oy{0L{I*>2a&B%t_{eDn1m;pGo5tcdG&mAQe*wCx@G72$_A|%a z*RL=)kFxCso>ub+3tIn&umam&g|2qn%SPZTZrgTg|K;(^Nu$EV;HPd+(yK$f7FTER zzPwJE1}?lx1n?OGpl)P53}~v7V-wq`?2tmZUR3r=9MC`{kEeUTO6!WxS_!petKjZH z5WbReVUWsr4|QP47Oxd*M{%*%qJ84zr{FuMD@m^?vpv2rG?w|Pr;Q2)3B9z&;F}Bc zeH^5t=varb5}tMFOC`@pd_2%+Yz364D* zWeeHfJv%sN?r7r0=t=g_L4+!3kXzLB9NB{s$apgD)%KXe8WgV17w7#HaO}sQT|A6S zJSee*n|Y;Ao#oV-Q>32e%^p$z$kg5Jf-qL1m5Oq8EVhb{;ragMYxxb%_#rha!Y@ zdfMD2K7_~3Zbq5zmb1+C4rms8wHU;CT?747@I^8B+;mSZ1&Sl<5Ntung(aJfC(&j}|(p{MW#&AHVDm}fN4`ykhk~>;Nu`=6BN%{D#hdiI2F&Fp`RD=p6zjP;=hqKW;?<9`cQiG^&&%|WHI)S%1@d^y?D)0 zMqoy5UG#ks54CAdFIZlj7Bn-<~4Ai~W$+G|vHAu@g+|OJPs&>?gSdm&678xt|V7af?#btqDUb0G=5NH={lZ;(G z|5Q%^2m=hp@?3X$_`t3*4r6{}=1%Db(M4+ANMu0o!;AFC9*S7}Sb6Cr;-|msjo6pp z{%jfC=1KC_is-3K03R3Z8rGEiHimBz*wuSIkLJ zH-UTOH5fW93oy{SVQPhu4!V*#d@k||J`S6VdJhbZ_1Kp->aydd1x`i8T^NH&0{yrz zbO}1Dz;0%-*ZeXDGNXYPZ|qAIpsmA7Y&lo%DY+pT&BL_AKb0vVJ@;N=1c9e?*Na>K z^5MP3+755QH{V&juY+s(HoccG{41lW4yL1Q2KMK$vi_6r{z3W1b0~<894P%1w{dV? z`IRppEss3Gnjx);%pC%>jVC%O@MP)J{VFMPXxn0@D-I6jQKE@49+&c#Zj#=;d*q;OjWOx zp^aGK2sWvuQ)^dTb>&h3u6>eml)3YAY{iXUlrG|=!bYp;s=`PWx_iM9K$p3=$ol3! zO84HE4j4`FO_U2v0bg&gbvX}s2qS!FVg`X{tl%8WbMRlNKtDns#0Ek0sW=WyWL|6Jf9Dr#H6J6QdpXbU(Jr?LXd$!TT75bY@T@EDyL8(%ELMEiDRGf9 zGU^p+C`lx=UG$Ij-4URZq-k)&ulB>O_Yv&LUxj(gv+*XPEzAw~nfkMbZ5iv>cGOSw z>{oyEqw?~ruatApqj6l#%Pj;k_};-M_LPUWAs7NH1scagflceFLY?I(AW0V^xHQNd z+$NXr6j)7HX_7*tR#$lv1O|k@d(a&N&JCm344qNvAH>QC-kv>kA%cwp^&&wNhZ4|{ z(}868`FHv9#n1}-X8Bs_b;Xx{*iLa%YyK>JjTYc52);7s-us!nOZ~xtlmO1rCmJjG z6+)wEq;C=M=lY|ZSkG3a?w&F32O=P9e9>|#y`M*Ma2LT#D{%xRO0yjCU;1LZ6{OwY z?x=Vs{lw($lxv;@Tjhl`)S=d^X#@{}bLY>NQ>Q;+i`OI6t%79(?bnK^bsZ%w?bb@} z$LEW96nH+ofk^%A-@h;L(bGV>>wbOLERSU?C=Q(y;+I=}jK87x7bmQd2PFdor6u{^ zz3DQJ0#{{#R_09z(?`E>v^;#|5u%k}U~Wx7TY&2XN@nVI3qicgzzG#$;-TZL^2L4X zIpPkFty{Oo*;aO`4Dj5OOWgjpkue-(eX+fpH;=|b{qgbRu~JK~#S;m#inU(ad-43m z(EXQw{c8w;Q{}BUUoR6_{f9XXWe|Eah~mWcTi0qMwBLf)zJldloSBCgcda$(-uygD zIOdvtRIw5FY-o~-hhFChsH{?n zjo&E0_QKP6u-y_9Fz1XPt@Ngqj`~mBl*TJ}_?$<1E}c?A zlNH&FT&7pC5+yNs?4^?3f=%MMxaQZm48nkSViqqW%UHf2uEgTuTR53H+uEqJmolVh z>sU`a5zM!OUq0(4Ncl3t`V2=2%2R6aP%-B}=ZxOhy5-XidhNC$mABlZ1h|JGXOyn!Hr97p!=$hniZuqw&C^rH1yhbGnmH(EY_({~ZR54Vw>>`gm-_)r$Ex}dU$ zpM5tjvLc8s!!p`hUS!~AJJ3>tB$nia@Z$pGLhOVxoi4C0?bX$Q0FMRJ)pG8Q_@A@=(`CVD2CZ$Mj!Con- z=1oCzTC}Qtm7gYa)~{4*dHk;bleT@C=gBNV_>AkmdfWH5hx?{U^{MsQYQJm6^)EFv z=_*XxGW@39Yuf0OSkJt9@M;Tr@cC!`PJKXE!=%a(GuC(e14?A{^42ja+_xvE*?wAWK01BwOa1IV|{_6J8xQ6c9y)zc@+XR2oa^!rKnbWG`@3_gcfXXP!94I*C z*ew=D>(!-H8lmv)w{t009O{%=n4|syEb8?V_I&)GkFb)lWdA3^m-M0@Rfdqj;?)Dg zu!#k3`}VEn?p6xOi@89>K9pO*>5 zH%Yq{(y9dvEjhwu2g0C7|4c65VZ1B-xkr#Rh4C(6X1`^A93cgejyWh7xR1 zY=mj-EuWme4A)f3V~2OeYOnRXuX_m`*~a*Z*Hs|5y|%x)E_2inOBu~nmghP5z$45U zLT$BJyT+kd2#^_T1$BP_0NpRA*;b$>UWSp8Mo0!yFyGm`Pr5GFP8Bm?R%sChyERyeb2WAOv)-@ZOz?(Z5$^p4fIQ24 zGm+mM7SsO8Ni+7vhfSYqdg&!=AKN-MB0!%yhd_4cc6ss3zf`tyT%o6OcwN7C13GjM ztLo+Q-GBZ)o^V14%1(<@NYRb_+BHv1Fs1@|XpeNsEAz=Z{m-{_stP<% zFAZFPKG_GyyawCq4X>mdxsBhuZ*PR~Q{cXNudo+eWL8*LXi*s;UGZC?!R?PKnG|$A zAt8!S)&~13u8sgR*9C*5dL*01lzxs6HE`(6?48g)h0qSl5I0pOIPQ8eL@0w6i#G~( zx-m=7Rn)GJFt{F%s9k0M!Ts@oc=_d**>>alx9Rg4cQHd^1i* zU270_r!g8ahSQX3$~ z6L53gSUGe0Z2231<8MZJzL6uG-JWpb)F;{Rtst!;+BI&FtwL_I)5>qG7x&BGMk!$c zTRktjIt?i4RyeHeSkFDJMw&Z9Oq0+I){Th?))=0v@JZ|s@MRkTBK7if-FEN$&}5D8 z;=1kD4wV~A%w0VLB!YTzI5%C}=UA8Z1{B}q&7C(JP~!H(gA5IC;e&!5{GSC6??4Cd z+{XCU!+MXK_Z$MF$MOD~f8pOK&wlX$!CB4Hc3$Ya3kJob)QFxswbhB${E*eJ#gd!Xl}lJC!O(`>we2G z`W;%}de#X1rmI3Xch*gLuH)HmY@k-#VS$wGI+AwUZYp!#@I_UUH+&txeX3CG`#L|M z?esBk$Y&5)Dhusl$XNGol${-0c<*Ty%uV|0{86Z<1m+Lv87J!zS6nw#IxRqBJYB#O z&b+!%kaqTSi$_O5e-~QoGOFx6No<8<-x{X^a z$8r6v=RXI}D&&3+8uF(%;b+0e z*aWDeh)i{m27>C5bxUZ59wjRMuFdPq%}b}t1nyRyaD0mWT28=Uh&00vq0r?@cdczO z-8*({j|SGk*231Y0CfbBbzhNbSE(=arnMebY5YwVC$GPmtY6Pky-&;PZhC&$Vk-=tqF zPnsLc=4D&O>gx*2_P1@be@PygGvv7M>3#{u7=*kZk4W&sLXL z&@L`tT3%ZwM3KhipJU1;qvm@riI5jh{IhbO-%Y>TG&NoQYj#JeX5!njQ&j$>ocn&K z4fU~qtCh`fvdSTVpi3yVTmXWnEkR8CEZcJVh{#?(5~HZsH`R&-L5J9S2C)Kq_Pinh zxqvwjW#;;sm;;0oq zGF7@43KuOdS{;O`^-1itxah{IP_I>^UFcg)xQn4mJ$s;aMWuuL;}=-WTucL5JLNbv z-~6Hu_dw?b8esekY(MM1#VZ-9eJ6%o$NU@a5i zqAgT}t7E-#HSi1Sv=1xz+Fu#N3S=MovY}B<2L9K!rolGaM9n3gaBi6nnCL0Qf1mkD zIRf8zsk63`C%9E^Ca~d5dFQkZ=Nu?fr9H-Gb` z^3!)ummj|RUfGEEm64c@>v9YR{CEHIHwnV`4Exxp*av+Bcj-&z+u#2e;1+@D?&1QB z=hmP9jbASR{$Kv>^2w*i%O@vJ0NYZ&^33BROgVA-9Jt+E_UzhGZr!*P##GCeObLdd zv^#FNEFg}L4BI?{mwmHOj+5h2uiDqlO3)``V^-`h__j9R5)hZ%XqOC zvaRf%uBrU9PK7oFv`iDm6?A|pCIY+jdjpCs+?DTP<&T1Z`UJ5KqYgrv1f7tv%M0$D zR_;f(?z;b2p#&zaqXxS)AfHDBPEOn`S8ov+`qFvY>&XvTqwg-4s~?^#h5eiR5AF&6 z>9*;yfgLnV`s!S)18obWNwpoqDbKyh8cV11kmp|Q`;{NI-iNl;|Mr3M1T--7N#-m+ zRZji{LGkq;zl>1u+jtv2nWCKnq8?-lp@%?Z7tWRAKYk-{Rmmsq(yd-=^AdO`JyW2R zMpmZN`d1*y*tnHPYbNw3bBy*tcP|2?FMs(tJe;0Li;o_CtQ4?ks1|o+}@H^fAKOHgJipAm~hFevNqEi<^G7iZE`@W9jfLrwmDVRMfg3 z-}oN;_U>bx`a@eEd+ad;@T)l^-s8rkKekc2B`@WcMFYddHI_1kotAX1yOWc6SAvTw zZ&d(q+rG2x*}o@y+4t<_v=UAV`S|#;a^}p3SOW(T`gYOgbqMb_6SqXVDF3FCldy!q zMffp~q5FCtIsUq6YcYNH`De-&T)zkL%GtGZOL^=6A@9wj{5r1t&gw>QXf(FQzV84D za1(cmlqiW>E!n2xcu_pDlQVO2;&VLCnMvlqBr`b^CmGL~nRwQCGPYwYb{xyHY$vuX zS&}VMq)3aDxGw-mfY_JD+E{u+_k2Fzdat_yf|TTCB6?o;@ArGJUahxo-MaVIty|xE zI<(FG$)1@###Rsk=#gQzw_19kD5WFm#?ZIpC@>DP>c45@roh6s@7#GKupBJAcHL0^ zVB4m05ct0M!V4UyxfecjTeeea0nv-^2!#)EX{y8e*1h8Py9$gwd-fvS-->7UHEG92 z%20{BanpwKrLX)ELd_s^vwO60wue=j<5uNuKMD}Hthhy|JsCyIFIV-oBp5n%0;S*} zTM6(*fZ){A+W{`zP!1JiavyLLi^Ub^c9-@-cMNqN;))W}-}=P2^aI{RqCjA*bO?1E zdpRFFXJ;-}m?vMyUk!6Cx^N&ptAD~dR!TlYmqP!^*TqIDp6{=))yAWc<sV;qmu7Pkb+JIqn(g+eXXIM4%$kwX69V*H2f5>xaZkNP_96~*6k`k z^!_`_6VJZF7(HLcF2e6D!M_A;_T&iLMpI}Xy~09<3Iw;bImVpeQlG@)i#FJ%=|FC; zcU6dA@6Go{*!R3(9~e)=3Iw8)L63!JreF&&AM(hEO`A66=ot4(MG!C!%nwshI(x#EdxaY&w^kc$J*8DgIC%15Ao3W2Xo{mTWW460ptIadY@4%x^JrVA zU*x{FKXF?CHNS~l6Vy5xza7D|6V%Elj<;8p6--ZPUI^a+yp1?3zPIhwmMsCh_G)vx zDx7lK@V3hJJ$-t0KI$WoF0t&hOK|0@A+a z*YBD3x3Hk?O1@0}$&YE9dn31*m}`L4j1t3%=2gq~&VX47X7zz@L)a3h*3Z~x zsUR4^Ft}9nYqCymxpxvsCVtT#2!8}Ah_@4i0)d{j6%3s~91|UkP0h;ZGjY4sHcidC9Z-*gbygGiJ1l>C0IM$qACe2ko1$D=xOronNn(=wX zJRBk})1YuKb~`|jajXxy?TpPxQ`hi%#)_?I&5mMj0+lUK6=D;^++a5 zPq2E$9!CO`u^eab@sVSvusj%IKXj!L-vMaf+WK6i1l@xlamys4Gl{u*9p^i)Yz&3g>3^e6+5_d(;v@#i4 zaV5-QtUx~jGa%zAO>!m5NnMKs83Gx+tR4^+`~VhO0C?F?;+<{CZ=S_(Lj3ndbK`c5 z8j&Di5)3B3_eQJ&IgcP?7!lJZk6H##xqL6arU{e^^5_fmH@*4ukZ;Q&;hau{ z0-WSMdEhnn!P8e1a)mxyJivZ>@U%~BD^@&u$>%&iUOcME!ra5%!)mdf??(<@EI;(u zzQ5eQeO0+E9s$$gi<9M(Kcqvz-2ebU07*naRPeF#xb zz8eAP1sKa=nEo{|*W1g%1BdVcyuYl$BIWbH|J!(7zMMV%_H%c4#aCBO6|(G;c%G*T zX&W8a(t+%Wq~VS?amTnaimuAh5aPi+Qb&ckQT@Vz;|fM2qd1RZTzJaE=oMD2NV}Mo zx-fHu2WEg(^Hqg<@l2C^!K=_y&nC8u(v#B+XkAfauA{1%AFT^YA%~TDW+e|n->z|N z8!^HZJK- z=YQ!}%V`ABHCS&9=*^t*q7tLG7mwcH*TMw|b_m8Yz9X#s+NaVY$G0o6eZ+U{TV@?! zw8;tyXfGZV?x!$i)(qWt`l_E5OvmiL{jbyStgy2Xp|GoS;Wysci)lC8f`F-GcjLy5 zSSv1p4jrNx`U7FmBk^2aleS0?r6u8uFmqP`>w(vDPB_nYDCw!fmAH8$N0Z)gpZuFY zfd$wrQ2>f7DlT4m39ADXBc2YRf=dfE$7XPdN^3>nyy#qc_%KSxq2oDv(7E93*`6rO z@4e?Ptip~(5O&Y~8TQ#f`>k(sO2}Tqwnp)!wU~1W*p{*8oa<4D``_4yKbytm2`q84 zs6$Op9a*<-H42y&<>s5lleeb{=;(G7VR}AepdUq;^SQK1TJPA`w?MXZpjc4QcZ-Ag zqJ@B#Eh@X$tyxo+F;}`b{W5-ejH7izk4km~LTQ*oHNq`V<%D8(68B2 zM!!y6!qNq=>xIrD_{ zGIU>>*U-bXjW$zDk_&IQv*05FK0?|jIks(D0%kG5Ib>l!LVbT|gLI(F@yZrL$FQd+ zxiDmo&S48!@X*Ybei)>7IS7PqlGPGSbTB)*X(LXj z`a8-coKV4?WtDJ*!7$E*>PkU31XB~;4g`Bw>er$9Td>G;ADQ4~aOiYd!R(bsvplKi zdnP-zV>-c-shxs>cRc@`f*-C1^%%E|boFHdtbj%NN|X*-y9aO^Iejs!7ZwSx8_i zd!EO?u&?AEs(5Yfzsn+$oUgXN(h~A*VbHcYM77B}VRE}RyM-04tSvS<@BHv?=6wxU zOP`p$Cx(SJzY@nbho+$Rr$!_{Z_L*;P8NKVk7j*p{#`Xx;I-_QPfm1dmU@uA@l(I1 zsATOI#9t>#5@^%A@;t=~ramp4WS)8E8CFc53Zvj8M@2l2LA>PY-t#2%k3epCY2DDY? zTYnsojWD;}OiH%T38J;05k7VZSuj1wP}j+dDVOn!)1+o^@&!zl_rGzB$(R*V1V{H% z4##m2`?qm&r8gS4WVoNRDh^=qfKgAE4y9PN1m5nkmzmMjS$y|$Qk4O;UNR?vJ9XOs z#v7an@PlD;j$-EMIn2hb+XQ6V$0ATlyUxS>E9}XNAohk`g)st@p1aWz$V-u8J#?nW8#>EIKU>j zW*qN>PmmqjC^L}@Mm%Z6=SDh{?8n^-@bE>C>z5&B$#L$lK3FyrgXnPZ1a*|@g67h(SdeYa`jIuu5n zq0Kq-GDdDSS+$bw8o+sYm}8EpuXtzMwL-BEgBRevxFiFnz-Rx8yRO(d2kKv@10Mig zFn9_+qeJdpW;+1$XJ^+$*}jz{h2|-Exk9h<=pxMSQcQ5iI4R%|^}Ue1^~ydE9M;Q! zH*NOBhbjP3Mi7BH4?JTsrJe}<(kANVc(;G-uXv4y>DEM3rpvB2tt)D#%_^^^Z8Bpc z7hE_z!L~vyd zAXNMzw2tqJv%!&6QG6kc{N8+#FZh)h;yRV~jC%J9Yi+Un)aCLI{`QZQ_uhX`=|%9K zQW-{jHDf(}2J0gHFSw@{SI}gQf)hqoMTvr49jkS}?Evs~oKp=hznaR}2FHl-scJx)yp&-&g-B<55_N2k){ zk@EZh@%PGm9(Xq^!fbT{UXF*GZn~x1edq1vXMgs8Vl^43k??qv2-%{t^UoZS3wS%0 z?2|e0lH#lM1XN}&d$v6JxBR{(1T3U-@_Ck;fk| zciwUbLjyM4d58QIaIK?4b6x#ZQEJ{OX6Q#P*!J(+&uJw4%a8uZUk4Vqv8sHm+_Y;e zu<9xgK5%FGB9=jWcJHSD7iZi%uRz$Ms1c@?CB0LSc7D`q3?xF?h$YdHL*)m4;0MZ$ zJGP=+KM3vUDfdz5AA0!1k=O(CWl? ztXsDhp?)Pwtc3{O!{FEYvSsUF%;_{SAyM z@PU4FesZpl?-06B-ry8_=+AX)e$Q4v=;$e|8Rj9xdtBZU1j)Xh$+GXY=Oftfy7315 z;()U#Bcx3i&kvQG!S82Y*o)i%zt8y3JS=?!rmaBf7!~XeU+GEcAMcHmIRo6cUJ;xb zTMF|k?N!*?NA|tbv+&kzUxH*lmSs9=e&u0klQe-pV^nK^8qc|agwyeONcxr^b5W#K ztf&Z*izI?c$dhz@q(ch%!p*Y7TM@-eS|psM>7HWX7DD|X%|+glpVWb@eP9~5O7vmn zrf{zx2XVt~OJ`8_OftWYKzA0QAadMI#}z@OWiu{G62I*ad)YQ}P>lR({Evr-}9E+kKn(9dOyx@3>1mVw^KL zKr#^q6a?)UAQS9WT*lt|b)}!1{M+ym1h?ir>Y4q#!y2O|vtHmifA>!dw9& zvNsjNvJEZY@ZJ-wf?%G~t)o5%g>9&VE{rcVX~qlhD3?Lxv&h&oAUxJfWNRX~xBe0_ z@9Rp%Oa#mE->ZpY_FNL5l+rx6%!Kb|t{S&3vdMSmbuw+TpANn1IYl(>u;Oio#GZ-A zot10aK2ztJ7}J@P$_e!^<7&;)|6F-rr^oKv1jKvQ-ts(J9$HCM(4cx_)K*YpW^&V(e+^`TK+fd<|cunSDAZJm-$;(Avn zo2**-Xq9-Uuwi`^O5H~+;kW&2ZPi>mQS5njPkH2PkCMY=*|c#}x#NyI*~@%G)zrhl zsU%yrbO{XVYM2TcObE4;Xl*q2-Rv_&*k@nh0IRDqcxvy>Tk|}HoKDA~=7YqowQAtFIJ}^rD6PFOxXW>2@lPluZkKG zc?46#Gwk1|&f{U?G;7xCfb)ad+owg5?YMGfI1HSEvdTW&D9k3BRTpWAleU+uua++j za zMHw;)Di>r1EJKD!CSRqcAImeI0-}uF6sreLmWfAS`EHC~uL>d1lKd24uDW;`;V1)w zH`JkC-1tvE70%!^aoW5fRC!lvV@(&qid*9t-j0_le3>iQMP{P8_lZxPxT6gSmV~~J zso%f&Z~j*K!H+zE!0J4MK<0`sO!Ea8*7NN1J4T%2F#9jPb^u{k#S7-6(0-jljxp!# zShpC)`qi>^1D?FI`sUte=bp~842zTd@4Xx4)1feKDvWxVJ4RTozwBOM_SL@h{BvO% zox7GZKP^P?cLlxau*={@XZQ zWH4&QaQgHs<-T|S?J~KulwbbWzeri^f9<%4#lV{K@$Y}2j9}Jy@Zf$FZz$tB+{)p2 zg?#`$+BRX=Xle`@vic~y|^k<7uhs)Rr8yr@GB4}Y(Xp0^n|=;%$*3Yp8Wb>)GLrjT)wA54; z33=}o#7u1S^PPR-I5DmatfzqV%wJM=-g0NT^R{ieQOG-gyH zDcmgIesYyv!9bzcJkK)4+#fBYwplzZ>Fv)pp? z%~?U!^Y>ifvVH6JvisFn%LyzkR^q&mk($+Nkc9qvxP0OBU#ax{3a2+9Skyh|^d0y! z0e&mctJIr=QqRvQE2WY(X~hvNt`z=Nc0K&bPlSeT+qMyp>bI7E`rrQ#<@ML`;17M) zA(%poidL1V(!3}Sq}AXI|L|_m6xuK7SFc=KUVQGka{SOfd{-sSe&4_r=UjEzv?&r!kp8N)W5Vl}lahc=S5J;SRsQVn~s8b-<=eep}>BOm@iS-E@(3L8#T>AO!Z(dGyUJ~}#_qZEhmHR1~X>eb7!46@%(Av@39;?I&y~XNc4>~z)!_C z@8~!QL_;gY6tB<}kXt1~7rcXX(7AjL%5|f=DsNw#Qo3&5juYqbc5d^f0xKz?ck*vU zHUU@Ynm1%-KAF>_@CHvQSL_WPalRmq@KteA@uXVfRfPeWA{Y3+8yI-SM-TVm8yTmT z;W&)~hCE;tsV_%vGS*d+T*P;UN@P!bNSVYPLjfw>u{UJv!@0}>uB6L9x>B!CjkW96 z(I5C2Ldns~n1Hf#QV5Gn@*m+nG}FiN?LxK^vPh(b#g$I1d@g_&C{D*OyYS#5F0Exg z5$^(9(pLqvi#p7k!0_8$!ngtLw~P9p{5|COop1q8Cb0BKQ(f@FVFI#=oZ=l`reUmB zu@9&p#`^53;~ZVb{#BhCp*fNb~`T6idt*B-*9-Ts@AipLlGI4XL+qzZD%f4go31&c( zTqeWzSaz#zOQy5Gz{Ut`7R;4_O(N6PFOg1&5P=cq-^?|0Us029^Gja5^WJPI-}-v_ z&Via233>BZl3yo6%LHAW!ZK=#*$t`nXu@YDs5Q2Zv`XTZD1Nn-sxho!?%Lp4dHjXk z2Jb2u+7kb)`CeQ5+9q2xtNj7`ObNo$a$A_D-<#J~&6jx(jEs}_WNhAb|9*`;U3Ob& zlSh7%fo%kqL=2vRml9o%R#I7IzCCzAuV(=hM`5SI6$?v0*^*SMW^T=^kPl7~M>AU| zrU6V%U5QqhQrNY4Cvf+Qy8rG2A9$#2+O#=Nolatgxq^M?H|*Gf>D|Kgwnrdk>_zET z39@ys7fdIUN8eI3_&CTpf}=V2N=7JV>{_l9i)Ff!IR|E0Vb6Mbxlhvx#qsO@`t#K5 zB>OGhua{ME;4H*#SFYwqz`4RNT%;Z3NSo_KB$0xJLijVC3WAQ94vw<2G=NhW1)i9O z0na{GDqNkhIo%V`1wD_Oo_Azhi{#$@Z!%_%S(Ou7Dkxa%cxy3xC!d1}{-t01MfPa! zDUUz)c;G8D?&Q9Ny`Q@Y*A&sM5eiWbc4?2MnlcXJl0t?`5StihqA(z)Z{ORe{L?Ng zCLOH!W4{M)$-`@=XSg?kpX6F!+II;`M89&w@62u98&A9x#~M6q!EbgEaEQ=Qg!;@2 zwf0t}9YaY&hB7MBbIX@uId*E8Bg*b9pM3ZOg{_vQij zvF}xGojiG>Jo@M(<@slyfjP#SixtOPZoVN5qx-dA$Fkxw!rfd}C}cz)eDJ;Cd^?&L84{0*(xq%yyVoaKx2xg~ABf%wMiLo;aZrZ55UY^UAM-0+%kFWUTd- zEgNz4HhPky!*J4g_Au6FTA2tX7-1|gyX z9(oT|pM_U3pTerb5oSlWj2w0?U?Rrp~Igf|kOpRy}7{tuVikDV?H+$scp-Mo1{{j{Ey-ZzprG7rr6+;R{5 z%~v5nfBkEZ!*nCSgS2ihsW_w(RPXc%pa@3`+zv!P=|oSQt6t6Fvw(@picOn0lvj7Z z0)@1i>t?Ty4Yp{v+hc}d24npz3BvJ{ME#K z5qqJZc>L?-5dM(1ZQTkTy_{9{_tC~b{*%YcvK6a=hsv!A!&rMDAZZDZ{o2riZUkG$ zg5!FUycaGQEH6CwJc{5G<+j^yLa4hKrEn*>uIc}6x893D$Jylw(DH+IK6E@wTkPvf z?=mMaCW8mm*CWRSSdFcJ`DUUt!IPlOB<2>*Lp9$12d$GZnm`5Ynxs^j)?c<0$l@V^O+rNKbxe1!K zYuC1{uumcoyV^dVt#&{0H~)+Bb3ga{yd&d zxTsij;Z7yB{JrB@OBWsCdCcK+&yAz#*^1AUv-A`E1!YM4J;L(T$)lhJyaaS)4C`EZ zdTCGxN+5B>BSOiZ54?_S6M1`8S)<-dgVH}lbUfKZM$0_PUFZ(^`Yb#g4~98*oX6U~ zmM|op?0m{{@kAP7p0&NTRO=+oB8&h(=I0eUN!@*xPFo%Y@mv)UkyQ}h#V7lQmrXjO zY3WE>7G9QN6|)R}<21*7dJ;n5z?VwBSS7RyK03v%LgJufjtt7kFee|K!Eytdpw-|c zeU*Ls08#5E=T5h@$#bgw(E_R)1>34cbD>piAH%w{i}|>dMcQmv0><{Uw8j%IgtwP4 zc-u=D66M>(dfP1izkUe>-zgVhZ2)YIgYdz zPh5q9tfY}gB@{Bt?3KC9svL~eRJ2K&^fOsQ#5Do3Q4ZFY`H=7!XwCBFqn81>cT%Zw z5*+5scjRGv{IqF|&^{0*15jTZr^&~BxeTAayiXa^A%CWuv?cYLNnY#jbK8blzgDZM z?{vJ>qph5csA*-uX!>8yMZRs;?eCwbpf(SG+m_V)c&h(-yy`sl117yJsHqYs}Y6(`rsrhGolhux{}pi=#wj7ll*4Ijfv0Wikwj64Hj!1 zS1g@G>!eN*vnSHf~vziRo`BN-BCXVhn5>2p;~cxRj@ z9Y5y~06Y$fg}%Zu^JNb0x{NvLfx{;_r+A1nug{cW80>Qh@4yL^ud0QLtB*^tG8-B?h9c@rdHuD6>?@wfxWZpc z`VQx9noPv=(dgxW!Fh-sO z<@`zZPh&EzaGn(w_J()&3}ny$7<+_AP(*n4x%*lIAJ;Bf}>nWf#~TBK0zy zUg=R=$6@x7Z?5SJ(^Ok&-Tc-E8nsjJbwX)fw6z9gDo zE$wOF8$^b6WtFi__*?|L$G-kFE0(8$?Qr=!KlVxJ5qr+R{3kJ0|LILzBOud&N^eNx zDxq+2TGMcKqfyU(7;>&S_t(HaN5U@{MgcEIDBKSxX6|lx3o-R32^!HY3kX58Tl$4Y7U3?ks-gr1sX{? z5iY@V$7ae%SluJ8vJZ;RDHz{k+rx6$(#_@He)>T9(ZBI2#`)14H+SQ%`^vu84+qBj zDiGGrksL@ z3z~=KCP#-4he$$kCtKfqe&Mf?PO6yaQ96N?~Vq2l*lx8GI1 z^5w5Hma%k&ZB@DAXwnL{7b~Ky`m&uX0%OWk@bZY;?(*alkD)jp#wud4Jn$aGJP>{WB=-mV@{1xvti8)>Xky0hxw}#)TF#CfxcVKd%}06b`Dt`qcw$ zqu5oRe)`E+i40)vv=v3xeJDD9`4@hpY~6Vyc!+?ALVb>_j){s>U&jbjgo&K>CpPq&L3fM;J+aLcfSFwMsvy z6iTdx@&g>nM>rC>h6CGBHwAabq*ultxFfz9mMv4H5$~)gQG@%r=Q(pJ=_HHFJAL>N z(b8-ToHnkDs%}w|R}m)i4ZJeq7allW z1z>zeI|}t-!dZ+^zX+lULncyz@?oB*M}v6^8d=sl=rrjxrt$p9tW~XBhEe)H!UA>E zyz(;jlA+gIvUyE8;GL4u>dli80%^x$RZ#b@)*;`ZP&@dnPc9qW+&1rgtZyBz-1Cs% znHNn0!ySSk^&#A!l7-`DpWi^xJ>{?cq6l_kh7kE^Lkx8>UigU8@cqf?|&6wSGa{nr_%tmsy)6zkE?v72w5d`=U`q7=d>A zzSfg`NOy(jC3xaJ&ROGMc^vcDg?L>*br{R9lVyn00ES_BPp~igG(zba1g;A*d@z8E zITES6dw^|KI%5PD2)F&LCJ4W$pL(WjN03^AfHjJfpH67&6n&+_$gLq0;Is_2xI<;j z@>T1~kA3RLungG8zRpAtGuw0{)pWv-7P7`%c*C!LomWN8Aq3R852LC41+ zrqBvf9v!7shI@ClR&k|EL9@RbVFsOccL&E6_PVEjJuq>q+)a}I(a+X38TzLYI9M{vxgnQvA|5L9H$y73vIss2Ig z=W#~jtJXLQuV<;JN0QBl7OYya1g3Bvb>|2wy_f@6<5>7OXBv0+;135lj-njbl17F3 z8Tx4wJhV*ohrk&IRXl1wu`p_c)D}%Dt{6ugXhQj=#XS4P#j_BpxJzJO8t%*4R}(;9 zuA*CB-@F9~4b1T{`$NN{*~Ssn14gI8DJ@CdgADhajLh0xT&Z{akX6!4xR+ateD-}t zgk#=65=pwlzgSbojWu?qkti9feZBKpbwoLHaV!edrEKrG@7~+luCu6ojeXPi-g7(Y zr^>U>?e70Mi-vLUq8exz?~i*!(*CJN7b zitp#xvWFl31oJ^30yn1DM-Nk9Ov%~qbnwt|wt);We&*9|1RP-<+EMvH`$ifo&90ht z_&xg5a@^p2?o2T?# z90oSlSK8~*%U3{dSJ}@Y$liPR9p%6Ldw&;8o70SG&W)#E1_s>6J_d!m{tr;%CH-Ldh^z; z;1Y^FgnpIN)=`?~M|h9mPewlxZXwZf!8y+30j=Ne-LC>?_fG5lQ;VGylzX~t*}MrQ z5dKPNwE`ts!V|ci2si}h;xn`d{B{e67O)D3mvD9}eVhXg(y{2mMf1wj-+F?2AH>q< zK9seC<*vK$EPo1akB-qd&b8p5mIj$4C~pqdaVj6WRG#q8&lUIreUgl$gzUjD)}>2l zQG7jvKZXZzHn|q-lP6iNKVIJZ-j9|CzwnLn@_zi;u!4UXB`6goS3h3}(KxP6wg zIHLImhn$DSt&BG~jEpzJJ-V{SW3`!qAlKE=~E}b z1?$eSgz$cr<_QI^z7Jqwr9~x8rxUzUy8>wAUqG1sjfz(m|(qy~=s2#V?N++On) z9_N~{H$4gmubNrC|4;n=&Jyfr0V}WskRqrWOp$7UNnjkN_B@lk6Dzz9eNRWigmpo{ zoMc*rc9M}mflZ7-sdXh5A%ZY$_L2ibt!Bn3Ar6F0Vh}FNcQA&zHkW2{c5q7lB}_7H zBczw$hqjW)RfUTP^vhXsS#*v7-f4d9(LCl?2R6Ut>DB()z8cVkST?sAoV+k?y+~_$ z4VG0>?z2}-YrDMKI0?4NAp&haiIP}tx;A9`x5;Pvxw*MEhxUC7$M)G8T<@A)*Sxo! zwta2orxS)G@$?pznT|L6<~xns^uwFVoSoO7?>^>xO?B+IT(in+@xk`D{Ut-<6*wi_ zC*WYPU%Z%s?5wy(yWVAFqqV<2QbtT#!DS~u?_;52Kky&CYx*QfO*`w#*xp4u9WL}+x=$8aU|y6xOd%lE6k&Ni8&gFy@nRyN{eG# zSOgBhOrhUORan(Z1S=SO3UAAnEeZO#x7nG(y@SgC()A&8_$$7%t1?LW>;d5quqkglpahiD#ji(+7^7F0Z~m1Q@DWsAl^U zI$ENm#rcm`0Vju=4+p+1dst!sU*YYN|Q>h^9Vt(u4VZk z+Xm+80Lmk%4x<2A8s|ml5jadYjshr0$H654_6PyNX2#+KN{Xe+t-Je;>o~hG%oYX4 zm0M@~WWdpcp)RK~`TN3eFjjj0=B5H>dzf8Vn1@X4wy1v!8RtQs~#u6wkXES4`IKNNiJikzdNy?2aB2P(CwxSYC#eN{lBlGLjY zTo_^e9zAvf@8t*auQ7zM(t)$m|Hz8>_sLUJ4%;C5*vg1PV%~iC7~q!`-$wWoRioI2 z|4|6E4>NxOBY7}a=?)z{5~o)>#(Vzxmr}m8$n(|DoW214Uj$7;5d|&>w!p}~G`%<{ z&LCnXZ^4>4G+_jO?OV@2hYt!AI0%E|@KCSe<6H=N@3^EESWW z7l9Q{$q|@22JOBH%6xtQ;qtlP{e6U2#yeXkJab(-=gR##j(h6>N2TMVc-RmB2u&4F zTDol=p@Nx@v^WqZDk@y~5q{gYZDDWu3i@muQ~%q_3opG~PMzJy@q_!Jw3JJqQ*rS@!Kzi}20qLkdXztdHIa2#go8I7z73r`#|r2E_-#3Q^h6YZWQn2! zj3FN~ZE9+b#Ui_yF~Sw+n$%VA@*^n1H*eVhPIjPBI)x*=W2FyEhVxj_y^7cIO9-wJ zipeEooIa!Hcv68}g;U!t4H6b(S~CED6>n}gShQ$0?RCEBEZ_R()9l}WfOwcybFzY7 z^mPt50#EFTG~z`&uR7*zgTD&+DpOoQJAoMP$N{Xui(En8N!7FxC(>ne_J zyTn4=Gtaz$h1D7?0ysT@a?XC`%jL!!wv>|>#yQLW6qTf{^gV-?qe=Pj>|TDycg7Ee z3#*h1Zpt5dDLeQProzTbT2H4|+bnHSN$aHocMO_tCpsUCFIuXoI5u-jNEq-l56hLG zY4ZsT83(3yfy6lRXQ6=2Wm*7Fc(uGUe#IE)dn&E0kW5Gjtn6?5P#KGc(f3#zv1;Cj zcK9+%z8FmaA6qm|p=f%8Z5$u_@JA^| z9KzWnc=#;*;h~pa#7c)TOEOOw>!I!4)TMabDpoZsQ7m4B?>q$kotnVnP|Gl8KJms= zFd{eB=3e)k7QSPzcaC6hhl$0_B_g@{&;t@_?lghf9@{C<*kI;&8O9t z;CH|vd;CPrreUU>YGnY$Y~qQ?bw8m@JmqD=2ElV5oDI^;TSh2oMqLIKX(giWp$(G5 z$#izGSI9D~KZu_RfeI`_li6|QIAu{Uh!n#+^(BCKOqdy(O;wvV=O-hq!hx7(>33dH zJAUiro_B_FGksql4Xqbt`Od2<1#A6k$gFSS68O&w^R`WVP4M*|XQH-str<{a+lZ@^ zk)Xb_7>U&EbXQ0H?w`zSrbgd3{aclNy)3S+ru}){%ZPFuTuqv^w}w!?tJ8^}sda+u zJHOjBVJO?InmB=5@=MBk_f~BoO2$B9kuOBOP8du`O#XS-rcM6Sl}-w)dvzcAo{tj* zp9vzw1Rp;bI#@b~HhultRplZkoNHK}XE;*<1yanl#)n|knM5&vyXUUEV2UttqrWs) zcT!M5RcO;(EJr-0DydW$AO&v~6IR!40K&numSyx$!whMr>Tz_uLZGQDt**!@fSf&d zfytFsGnfN~WRFkMQHv9b4v5SxxYNMGqAhD4jI)!JW_?sKOrhuey06UDNskxnRk9(y zV_UPoOE8bZ)fI^d0sz4|(|vihvtfQIrx(UZdS}`&Vk#C%7ljMI)j^regtSYhvRXBq zhf%Wa<{u%69GrCP`MwBzG*nn_-m*C+ZYls=!E*9dc(ng@;N!k$VKI7TB=xc%H2+Pz zutt(J*blC*si4tus0y84>LFuVdxptZX2&YnI06lC@i#A;FWXSl2r1*#Z(rB_^}r%Q zfqoOiT=`>iH@@bReC6^djIB)1bO<-VBJcRtTkrF%YW|}idrx`)gYPPfNj`UK3#$ZJ zTF{0O+B4hp#3BM1=}faxgXiE)Z4{sQ{`{JFzy z4>-f>49DfM;@XS3esttymX$mdcbaU=(ArB1GIP3Jh1Vq0ttcoWVCF9)1S$x6Z~y3s zZ0~D(%cR@b`sNd&LJm`1oWHr^c>$qbv*nA_<18!NOIG5{&pNZ0x|XEy0*s~{f6^m* zG4oj+Q&l*vbSk*n%yrT;$F_Z*iulWA-A!Ndk^nnR*gJR=QJU$BJGhTBXO!^GC?}qJ z`kC^HkA1A%dDqSA#Dpxu+1WA|Tu^vRTNzKT63PJ#*iSONq?aV9z)NL_C=8_q(mLBH z&1hIj7Z zTIE+1v*Z)HNlY){t?*5=%76I%&zH?OUfZ&HBlWg_&n;KBBV`6zjWL6pYQ zFv=<%DJWh^`xSO7JlLXv(B#&tN7=ITwMV~L?z;2c2+Ip&@#0o9J(F8a(b1J>ddMo1 zmE({=KB2L|S;c??pQkLw1j|6PZo(y{7; zC4K-XpbDhI7>AE2w1ndYEGm4qpDlO8`gNQX@S(uw>{*ne1dn4CbiIR66LevodAvwiPk=|x%a`7ittJjQ5Qw_z3a6eq#CISWt-j+D=R?u#fs zE&!wD;NFQS9J&xJo%3ip z&iQPAT2e+&ci`vXkIJ%DTcOvh%EY0ua`w_G1WEV+#?Kt){V{QjV#G&rI|yfo@R5de zF;1+D^P}U;uyK?kS}VB_F?&9A{A$tToUUb_3lx{}dtrK&SjKg{RHc)ack)WL4t>zm zY+)ddaosz{sN)_*a5L7yw7@Q7T!aShQGz*!`B-;px#fh%IWR^jzkw zZWLC|U5gjXUpZ$Xt5Lsx;3&=0Ik6{{(H#1pvglL$-*fD}T$I_ncXv4jAE*;hY1-;_ zYs)I|Xasm2I>^b^HIO}#v3yuE5) z)Tai|XkV^&V7F1P_bW<%k6m&E-}9Ff)@;~$FJg^>*b8E|!4W%CuCif@!DK&&NzTC$ zB1y;8)TWX-ktx9RD64=Xs?%caM75>WiIw;arV(F6Qov`pGfB%Nxgt|nL9#L@5f(4_ z@-N8mn1QhLQbr$jba1;`2N?~)?qkxQ17qb%k7!=Ui(=w?crA>t-=ZdN`;v;tCGl!T^;OMDW-gtT%<5Odyd~nSqUi(T(!S{;+cYBEb*`knCUPbs^OyxE z?}Jm*b-qq!1cf0cQ^%1)#wglY_xZ}axblCLbEi+@DR=*YqcDGa(5?@a8@AoZM8zsL z%q&I#v2;tCN<+q_1d~psE6aeaS=$ z9dJLe=8~;q@RdiuRm$cyXbHMGrGrTfA!t1wo!76x!#H%v@ov4NrB8l!;taegz&-g2 z*iL@7O~y%cO_?(%Zs|`}(s>6P8v(zAFiq_hsLkI#v~OK48H1MTI7Uk%nXGtl#^ltz z6u4v(obWxeN2bB{gju65mZ`Obxv8MY$~{7(ipgQjj4#n&M_JXrMTv#W)f&r@p)*8$ zO#ei{GN6tD0N_s{?ILXCodFOlLnUBNVb-+MBt_IYPsH-pUj|pctej3Ar0B2 z9>#QT5Q*ySP?aB$V(fyJae8fwcn!USsmp=qPJ9ca*Um25CWjW@`Ite?#(S)ZM2iv!8i}}2(a7T|E zWMznRc&W3_fjr$ohRoxy+^2fz&@onwU|?Y`FKG^olFAuI#mXfV3+_FaA&#KLHjeY> zj$k&AM|4)~L6Y?8Wf*qc`hi2Ns|}>ReFS?tiniGg_HpJOaKSo?RbF+D%xxZscKwU?)vIEWp1>81 zE^G1QSVfT4Bz_9PaM{w8^78Z=v z`B?S1pInnw$Fj__hbw0{)qC7e$qSh`QS{*FfQO0%htys=6FKi1KF#2M$P2-cL-#fq&K z8^Z|ry(mw2?|rpA`WVN5qKLQ%y!-J@GIa7hemW*m&JA;V!!i_22kAqUKN5ax#W<_= z7C)`KLOU>KH5RfF;dPvG{;z-a|0$a{;J0F6F_l3vhVxuct2usLUkMy<$hJSX-;f3P^cu-$qu73-AZE~1;2j7%=fH`?NznMo>qE;9=My09F@pBm;d|~aRH4MsD zI~5#p&Wuu@I;dob5O0-(hqNZq96Jj96;Jh#0tET1zi#VTwQ^PJH@CkBUmx?!%GE5a zP^U5W#_RVb+X2Z_zh}MSK`37GhFs)t5B+EV+fP@<=ag6XyiyyOPLlutKmbWZK~#3` z+R3~+AH2I#R)G7T;8?~_|LU*dZv&db_!ibWr>sLAeg|Q`r+a=`#IddCIK>9Quz<;Y z#>pNNC~M>ciA{9AU0fBud}=$)P3l%@E;sL}3oL%8Ty{Z496|2H>G{4QzJ2MQGzpEG zJo`xm1{?in&{RSu;mH61VRFW)lM$EUP6iS`kg2x*nOmXIK-fj3*cZ4=C5@ROP zbnI(y#5ph9k-{tDib6em@G*v!y4v`_`*wiCNpvHz`@Ws)2htS z-0#BVg}jrwQ0RBhYd3Vu^wQHw1l5I@fcCJexNxu&L3K6E%~1A~&L2Q=$z<84~{K?_F7(!|Jq`eM~cR86t+>bkj}59gih}aOgk)yflhu zZU%LG>8HXs5j-M&F-1=@5a?8up?0Y?M@MJl50-+4tbli5+UozeF0wuc&##~Ri zI+(NlEXy^}0k#MQHrCOWOTY<3ehq!o)!5f@n5zeGXUD*=~^XO3xMBuwmk;h6p-o^!fF zRH_>OfeNSJ>E9+@%MX~Q3Z%5Bsk`)~1Lj%t*DK9YZMN39mSwX-k6IY;YxXK(vg%0O zCM)164K=N`sqwVN=mbYyED=v_lelcS`73}ZtXrOiDXgUjpiRb?Cz8RhN6WcCU$bLZ z^q^5FIu-6sBMgL--pw5op@YCY3hxFU=I`xvUs`0-*V0dw7}7Xlt(71mvx;b$3v z1vpv-&9;RVmeX@VZMrYh9@A(kFoj}c0=P`FhZ}i2@Sa4`os(S%H=f-mtZN7tzKZ;-TVf8uvO_*a(0kbM?YF`I#;sfFKjm`lV zvBiPxQeWq7ooAX~>Pj51idW6tPTDv>>i6 z7HIDE*Sg^R@Ok2?^l{4unbWskDq6HKt9S{VDHBu$L+Y`P1FY`O>0yh2`}wgXI>NRD zEup3+FLUIgr$aDDvK2(!)4EP)ep92+Owy|i_5&sdzO@f&2X%M;(O1YgTPqYaBjh9K zuEg(15A;+#RKBqbj~_oCA=|!}9*7!RzVrc81@_Z83s;$Ld%bLn@swSh6LhAkp93MN z>Ai4WvUHF|j6Qs|yc~YQ{&6dXvWu{G`&N|W%@_zy3U4w|o~c`%CeXwgmvJbYbSkm55YZaYtga*A17lP_pkN9#>yYUT=PJb+qd|)e?p1)tQEb-flQ-Yk|3=SB7DTlNW?$y-0v^SkS9{qbt68yTw3^>K z8FzCob`PGmb3QoZjXpRueo+xe{u9 zXULpoPa;gDOq=^|Tcw|6o#k^L;a+A@p~#6s^R_A!sWEo1C#%vpc{)#8C(G=6bajP^ ztAe2RQ)T=n;|z0X=p-JHpJDZ9I|_=q<>p&&%^2`rA;%Tl9`b#C_bcqjyHwV9F3o$H z-Y`w{XC^J-CN6LV_JmuS0-hfyB^8U(4jCukr8cCIacPp8JePU-k>*ADK^iA{S7F@m zFMUj35l5JK44%&4go(-(CwS?g0==egV>lC1);){EqopuOKm9ZRRT;oJjd0Z)|6Du{ zpF4LZ&P?O9uhyc{QkrF5bF~%sAq}X()8Er$L5fo0F`YV%tZ=HsfDGCw$xgU1HzeO$ zkZ{hU@Gvqj181IPnC7u0v-`k_^2igrNDR`MZ|7S2e<&! zI}{pn0ve%kQs-J$inU{r>C7seLZsNEQcI>@;e^cnB%IskGBlUSa_v>46ADn$A4V_( z`UYi|d)jUHBy)T(eR2kea<88{%5fYM;J{owjh`q#@#7D3KJ#GtrCv+04%t1we8i2_6+RYdng+*l8CYeqodn>5or49)}Xj*v}&G|-h} z1u)B|Iw>>4AMLGWw@@Jh|H8TE!(%#(GzdrD8g8A<$9^AnoLWtv{ak$qEr5j15I z(K@()+DqK9@699T*_5eLL7HOS(i#f%**xX{EWq-xT3T_o zhw>D96rAc9)2cvtH-IzS)F*jScAD;c`^W}+5m?(UegIlPrN66GvhCnLUghat?pxeT z1o14Nk^#s3!q5UJi2qzUL_PPzEM#)MXAZFqjU|X$slyy|p zdp{~`g=;tSuG?QchhEeBs+94VN=L4B_u@XqAV?#Gc?mn`7vZS_$ZCkE&a3)VaJ!A$ zlm-V^p-91>2DH*61$$8}_Vg{tIG%tG`3E?8r^OdAOnWNag8PKq*7OVc*DWdbz5I43 zegRk^hY!#UT<3hwUzyvfW8HdD;gd>R8hO+?7$uq=Xa0hYU*R@};_u1?asuP46Kkd} z6k&OT!ef+iGs@N^_xjsLKMq5=1mghgI!8Olb5ADu6F9yXhMv4I!igkZz+&aPH8~;0 ztxOv>aDoLq(J)G07a|XF4512NEwjW?VPM_0HniW)VeJ*aE0m(p?|bQoZO=j`W6t)8 zr_Swe=kVF%afgP6vbfNi{<|9QyVRKmiA%OfM6pcAsD@9@5%HK$huQyHVz~Y0B3mTb zk3e59!LnqK`4FWF>D(GZFQH6?-(&l9rPa_l@XS*X^z~538>LacR$%&O(wf3W7I`0? zILr4qpWF(M_2Tm{lzp%5rEjD=z!;M6_K``fKI9|Ov6N1nQ)=No7X^pb3g&Hnyljtu zH0Q6(^$rp2YX@8nbr}O!zR`^FanGWi7JMCB?1_yuIgJtorD!6EZ?+VnUJ06_^X2u0svx7aPBW$ z7fc<;w~!_mY5vlX%Idsj=C!W1%0{BLZCxZ9CT-f2diwR2c}>SKn_SIL;63Z@cX<1q z6!aZt_2-Nxp`NbIbfd1HY2wam|Lk-IxA<{YYG9qqUm}S!UM)Gz+x9EJzOO_*kBNQF z7yVXqF+7>pM$80Wlc0HQ($#$HcW|PuLauv&mj$OmY==6rwzf+VjH2k5^vZQ+9HuwPu!@x>=^A%Sp|g zgu1`h-F!wdpPhpy-&I-Z3NMK3u}sxb9#Lseo#=ee>(tLqv3@OG@>kmBWqXEM!O-zo zJkAo&Fw4^nUuA}UGl99N^eZOmGBpbJFe3h*Id`rMPOS(d=Q-?in6x!#J&V_MJs-!x zpRlJq^9_AY;eMqVyrZ=((^`Woo(2fBk+sGnyZSzHE2P?F^#y5KT;b7Qys&2vilo=d^8PF3=3U!hEa?kgsvvrX^XZolE-D+=u91IWj-gM0&loFD zc><0ylI{_9zLA-5`2Q&}Pj#c^!Q6*E-95$-KqXlQxA>4W0-)#sCo`*g_+MlPUu!QvvkAfy0ddF`QYg zgVDPH4j&Bj>sXN==)~H<{Db$YJ9LsR)<;ei5bSR*0c5Azx;f1Gvf_!Dx4f_IH^#MB z#=JeBmqN$LwH&t{xj%FS#i8DwZ|5BCPvRVJ5hlkc=;z+f?ch&$*|uXdbn7GKH$V4T zwqmnVg*9J49p4My$a6SOGhTp`aPv8i)vP1sS@g6JXW3SUPyT4Xc##ScoE{_(FY7MP zLkjx9cQV7|&nFCZVwp=rhb*WGYwxU(Ly0IgFYlXY!yRkYgxGr3{*-~A=_3%F{;+Rt zn^(przqU!?%ikym5Jn=nH)TpwqJSW-NyQiO-25G5mJxbqg@|CjRZ!ruDa#kRCyIh& z$|jzIiT6oQJ__K~LIL3LEbLM!fHR)i@l(_AuFW&T1?7YKi~+-`8>dI84Dsl>ssO3+ z4NJb{)n08i&D%n9oMHRYUvSqx^ko(Bg=gh)t%Qn=R#BWv5kGAtMR-@@Mi_=}*;eU> zb)KGoY`bkFe}!?2ijv2%BAzv!UE4k*uo5eMW8TJ+zg0k#uGt6kSlL#9yNnY;Eot;e zBMt2C5g&1&$vmgCPRn)`*z#*V#1jEg+nxN$$Nth^j&;lFQ#ieoFLx`1ZE_y#WNeF% zwnI9jS-iZu=h=(*u0B^dGfy^itLE4|P#)t@Jmp>ohveM+Q6K3C^^|V7(muu*rgmv3 zK!)B_Gj9PA{-2w+oZt@OLRh%St4Q1B6P7MnN^<<#Ajm7&d+e_`zYw0stqSMx$sujj ze}#RfpzEsm5`=SVgmX#u_mijn+RpVVk1fqSg`?voupq5?w0+xFOy^gY*WZA5;bf8p zc%avTr^+X}N*>NRU}wD@wY1B~xHr+|JI zg{SrRbbTH$+#01vwFVGRt(Sf0m4H43+f8^`t7r;0#u(t8#8wXa_t-k zfAvDGz#hhgfgr=12|;4bpU9;7)xw21;{h2R3?iBY(MbX}I+I2^KExN~pbUw%1I9tA znV^GJ23v-y3+<5QXwvE=tnlt+)2A&aWq4VRgF!|r`!+#9^U=9j8z&L}OkZzCOG~Yx zd|QT>b@5jC)PQ_XKM9Y7NWf~mCZLVd#DDuA$)06OOmhGB(Z4s}UInKHmV{NfU9ZZs zT58$`=Hg~W0Ro#mr(rrfo4jjspN{7ZpPE4vyXiUd7pG<_WVrFUu8Qw-Lf`hwB(}hD zld4Z=RTGQ%w&gpzh$e&P9?Qk^)y%6QcHH2&Zv0#bwsct2D?(FUX||K1f`UxX2t@uE zX7b05Pn0(f9*j2FRc6h96@VPmPGVttxp!QJd684Ko(*hTMVySElc_@5WoUq}=eloh zavp*P`&lsub}}L72vd6L53|7drWop}(9pD=-`taDCyEKOV~-~0_&Mj>z5O2fg?U_G z721xo&(c+-bHgJztlO5ex7};Mkp0*r94V(4=9x~SFzVn+S1&@Cdq!=JG)jTda-Fap zTeUheLzO}EUBaywFs#fQiU-n4pJWU&nUc~8P{x6VMfje}kwI#^Wrm#eWdPiJZz+yq z`^G(nZetikh}3D;7r*q!C`l%?|kV~ zz0xK-$3$MfbBREPD%Y%c2DNdG=c9kLK^Rh4$}lt!c|ZHEzLy?fIM1<&2xRYh*S+P3 zKJs8$w`>vZsf^SmRvo_e&8P6)yke!JAN09XQB7TpW#!;8@D>C*HU{L7ekh z$4U0H0-x=$yTnDAa|JlxRmFr>2&}k)ldz9TufVRi?#tvocm6WUy#Uj80X&3RbWD<$ z$~{+XWhg5?K~Z4-6cS_hOcQkA#^|ACHDC9>7yWh+&n9Y`o*VA-Yn#2dfZPNOd6^WM z9DPOod2h4`q|X1e>p05EzyI)GEAP8~DW&ore8JsL8K8eS%e#IKuFDiGu0!tw`D-U^^tX>mQnkt;FYXn62 z9L;Z}GnVJ2MWU;4F}H2o%{$v19H37V7d|WP<(-VTj!IiV+3&uS2Gq;EYx-o#Sav^r z2U{Y{({}h?T(N(wil*%C>UOpsk*7RcKi>DPi(^e%ZF--jm?jkOlN;eY8OmE2lPY6P8HE+klc}IN)O?~EO|~_6X_`lTSqDR$BaCU?r3LndwR69H z_S`$ttfTc2?(~Uuvdo!_e0&sXOluxQv7e|ibtXM9m*#jRs`+L6Ofn!s(%GltL{;XR zJ^%Ge=H6OPgF}{KT?o~3%kkt`>_(|<+4ZP7UW)e>36oZQwSUYq{l~K~5eE$Px0Yev zz>_R&k4i{VKohEf>0D(V6?df%3imb7R=Bisb#ALL^WMCJf1x+dgSLRhK9!5i-%;LB zs`w&(tjFZlHds#;?AA-ULHgEdeZgJ(UFUkVhL4Pja1>Uxp7w?OgmqKkl(!M?G1Ip^ z{%i{^3H;pBWnGg8@5rTjrnc1Cm3QY>;tu^7d!8F>7!{zT+Q%)@p$w(TQn zsoNY{rC^=o@kJtTBZGLEw{%(Mwc*O&_Nl&))~;QX(=7Jw-_M+|AK3L0e*k=?X!35V zonNYAH)PC+KAmF^#_>_VHV;`3z#wc5VHb=PNuzD*bp^ojM; z$!{nA)Lc~Rhljeryq^9hpAqWln7R70@{V8e;hlZS!M-CdiDicaL!i^yPC79cg<%lM z^(3oPuAE=XF!ZW}P6VkFd0nYvAfqW%OC}HAop}nSe==iJwtAgSs^i&-@43CEC7DJb$m7^|uW)i{#VB{7&+j zuIIIbuFd3nzbWZ@FWxdN&9khwjc*mRtxp4lhL>w%OW3(><46<|fri>v!tJZtj|R*D zz+%5$t=sqMZ}O2SU3E3(2Jf24S2bs*xT})A>4CH0^@X zn>$c0b>rX#!B4mjqioRB-YhFGh7yoTu7`bRmKi@DNCs-TUFDD28WXf|cd~aiC^}MjDYf2gSvSqE!J6E8)ge?I=}hY&zY=e z-XsF`43lXtZQ}Z(CL?-fo{V6Sd6~xO4JPxPq>0O3XI9>S?(h6~`QQV$m4$SevY&g1 zCC{tYuPXoafBsn<(Jjg<0G9PIUkVy{X207&aT$1@p!R$n2+jZeoib-1{U-O{>~%%HaLf;Yx_bbQP^I-G|axm zXo}_I`a=J$2w%wK~rB39*1`$*iUg9 zLjU}-Z1sYie=UYwVXhTIGVS5+2n+PdvkQ%R2kl%)oyPFU+}EdxHNGflzf7Gn(DxpCtP#^)3s zyMYO9n!-%K?rA3t<*ATi5YkSWZsAzpxxVaI(De+{@+04eu#^9P#Fu*9qPs>N*eSoOiFwDUP}ST7`?NRI$)#V3iUmQxjV)lB%gJHKrdK8Wl!VxK-q-K+$TXu6~m* z?NLybZ^=DnX_X{QrHMRIcJ-|wEp<%f7_4T_nWll1QE3T+KdXkqK(JW9$|%=y9+Twc zS(S-({40Qx034zksm{hb;p$Iy_uedE!pVeyH)6`Ks z5oSK?9C;L;(7GA!+*$jUniAOdul3F!VdAUSND9d9c(crQs{ys39(;s3`8xkt->N8a zE~+q)p4ku6d?RhmDmn^mPcIOseW&ugg^P2db5W2^MB-|d>!Ilu=*2r}eFPsK6@=`k zD0OMOs=2zA!G20~V%5Y7zmCDcgHYilO^7f~6k!q=Lg1}$5B(9o8~P`VG>0}v>tkHo z>3pS7?6dWk2Gu@r{5q!i1K^gSqI&`7*t;b)$}7rOF-(rcQCT5=s90*u>K(-7X&+Q8 zhvuHKYuziJI+s`4m@y1Yv&zr=z{IrTxH#Y(O#KX(*P!~4hsrZ#43NeON2H;T+}=owO;OtE^|(Q{P%IlM9pflr4MQJ{%td zZj>*r<|X65C;Q?xW0zLCM_y;c!Z&raP0%&*bQ~T*OEB+M4mfu^Pe>2RG(3#;bOF&% z`+k501^dPQ`+X>sm08xUU5oiVrt?^cxyS!BXT~e5cnN3wCqh5gm8({*$Z13JN#}6z zdKrH*^YJ+|4@I{V zbe`1mOL%x{QV*7cI%GU`nyq7u(NQekR^ps*66@& zQ34|Z+FyQ2jAb_ZIL1O}P@3>b^fg5txjYE-4fDYOcZFX9pl9B8mCnw0!m~_25{Kk# z)(pT9MebXs#g|UXGQ-1|oQPmv5|`}t199AEa_KUAEnzg~cx;gr#(2$7aH~>~q`lr( z&9!OcbOb}&+BJdAV~sBfY6|f+w^zlUez^8Ulh>d1hr(q5t}6Sj^0MRF#$8>zw@T53 zPbc~|@n&9|qBhy@>!q)6LnIQjO~G&dpZT56qRA&e^}Z4diMf$#oF zeF6-l2IAhear53h+K5Ia9=KDZHhIpxPF}MgXWvf~H9Lz;r?X9+s6Ta>4x62@y>IH* z#xa-7&HP4_%EXf+!I+ria0y}Bl?RV1(fUd!Ln(tq@dnJ8AxZ8pps7`$aLhSb_MzR4 zP_6`Qy%_TfR4oIiL%STcMP5C4=+@a;%hWi=ZEO9=EMsZodsh!>q0ENAnl!sQ*@pr^ z4SsbhV{tM#wVRka7~I^GUzj2$lQA^XNDai7i9ScTv7sBZ)nhR`ne<2Tm^I&h%z~@LcT@5IUDL-AayP8el7k$4?2fKCInFFN2#f?=p?cRxK;QUOUmg9~{6Z6yLssQDD=o~l6R)R}d(;Np(;5Y(wR-C|98MC?qSmEw?6R+)3?{iEM z?Uk{&4`e?5bqk0>Qypivn{{>+Wj*+(5l2xC#Uet*$S|GYdxa~tehN93>ruFUFqE3! zKDO@-YE7Xyt}SN~yb-GJ+O(eILM$i5d}grDZOF^vUAwLcUL{HMn9N#qov#&$=* zstOt5Xgq03<}K)~Mgfi?@hd_czh`+iGSAJ%kpU{A70XCx}j;i ze5CV%y{rWbW0yYj@(g=<%np@84h~Z1KQL6y>?40^KZ;f2CSFsIc0Q}ZqkTY`wA-Ad z@y=z!(|$9Kc#y>;-UlAUG)?YFROdx48QivNT=&VdMFh}|Bj8#a;|9;9Gt5E4-ad%p z+_{pu+O0bFl}e^4kN}4CNhhpR;Dj)DwVNsh$Ep)HXdv;$hrF|I_!Eb$zZI?cRdK=k zQT6mmz(;<9P}*6onCL5EKsbr5I&~5Uy{|Y)5Ot`1P-iFZ$v4Mc$I8cIeZyrk@^h?I ze$M)U9|(%W!)MC6RZH2XwWaKP^+n9uhj?e(fuZ%bp`;~?&{BWx-B#8RCp{I#t;N{& zu$^sp_NOny8C_^Suylb$*qfKX?VKh|>^EWNz4LcJ!nzH%Ukq~`n2#`X++Dy4swK%k z46`C`ANMmCEPx&76xM|-NP$Vs{mp8M~HZd743Zj z-ceu9{_mWtg*AvG?k@xZ^;qpBuHYjgbaKRnO!~-WIuvAZ05}0?7C&#I4|A3!AQ4`D zS*>>vEg2q+6Nzr}0o#B@B}UQ2`53Co4gVsu1H?EEjvyq2N2P!hyq+GNNF00_EC}{> zrP35qc!@a^sffh@@%X8^5}meP(>-B%1RDM}*SC3nRmwK5a7z=edOP#b5{j7+?nv|J zy(F}6Tkz}x-mZeP<4xbUt(y+`j&G_UZ1jfkUzM^FzUd(PJcvi%gb}2J0x!cGAf=iA zFL!Sqq}g>9c;4Li%C)wvy-HQ3eX(T8mW3r`;~g7go2F@KH{DGP!AuX+G0`y-J<~Bg zj)8ypgPsV$&=buvKsU4vhCu>syj!+pZI)CnsrIa@%*uV=_nhDF-0x+6l`2^>FfkUd z>dWta@7?v>bI(27J+};Ck%8Q{JhiPd#Lhddj}h5i zBrJVwSEOP7xu6+jrLdYvKRotlf<0|MGxGZ?%)0H0HQhQ`C@4IpDX(ag?S-+SKABM$ z#eg4q?7xdQt&D}YmO?CF3vV;7*lTF()hKHfw?2>Uk|FYJVy*QHL=Bc9(oMSoi@LN+ zp`@BNBR!W%^s@)tjnK?ZOvOvhuTO9kNOY834d%}t$W2jd{6M|n83X^q$ zd4?s(XDUJ~rlTxfKSLu9eB82-$95%+AlO%+plF2l#yDWDb+NB^kDD+eccEa22R!pC z$E_HbNSWW+r=ky$eCtp2SDe&xCc|nSL8ePtv`e)F z{;PyxAhbZ59-K_)&t8ag>~Fv4R$LD26JZ!>CGXjf{@k;#u%~ex7!n8y#=`yTHhKC$CD%D6E`^9ZW<9X*x~A3l(- z;11c>*B5vsZmJY=eNi}HM}Z~yIw0-V-z1rQYjjHe7Y^I&dv2sg<`!p(pG{(Y(E z(n}#6>jpc{`q#~~+wMG>>U(NaYxmyN*p3i}Cx%Kehug9?2sY=ubc{l{r%r#a6Y+a} zt)Bgji$wJwOlMCIBY@?j6J2w4zqg$-))`NoHyQ5YXl$RMna*qL5q9E_X`KtsWvxrR zU`{!&vf%1D>;`@s7#twI$3iuSGGJ*QO2RgeS@?hk812E)q14gUl0Nk>K9r6gKO72{ z85A|oKle)dua7@Lu*7Bp*XnkiBXR2{9hZ$P(8l(9m44?h{|bcSW&Rm+o?9*9@+57H z{SU@-Ng*cNEOT zMcZOfN7F0hh+D?lP!P^uL|Sv@tDsdd^UgrWS!=f?N{eKmEzkBU*f^#&D3qkypm*kr)Hw%?+m(-F<^m4}0<4kq;)mudV zOAF)#(ZUTxX&Y@rC<9o3{4GBx9@=sLDIic3P0B)@_-9=aWQ=bG%OwO3anbP@A17ED z0usgMF@d(^ywZpm#t^0e0he{?7ajgr3bvXSldt6xQf5ND}8t>y!4*a@-I)~IxmjJF`f#~;F|90D*YTQi!D5c zg|oOCN-xTCy%#rxrFgIVx_P9h&O_;pN@FkA{(901Q;#52>E`(A8R-1go5p$WTDwS4 zLYW|8H%lCmk)dJM7QDwCXBW1>6%}1o5f2HBp@xiK_M6xIWh@1OZ4*AkL8xLaF-A`l z{E(+5E#lGUcC@CJ`LNnYyadM0`6BN#kKrKtNEsPdE8tz4$txab1(Wp(d+|2r6;&#G zRYPBty`-_c`UiOl^*6;O9&BBbr4$;eCS0yOx}pl=rB#ce3&CEjkqC%L(9u9@2i(26 z?GUc3z1IRU$6(CV_H?jEL;~X^kSItz{ML;GR1QLrC#Yp+0^?#V0~82i13_ky%}F*o zG!kX`dwq??hshuzbwP6Sd7i8;NzxCQ8j;<$#$~(t2g;Wo{N2ASE8N6o&Or9fx^7T( zQESnh8zlL@A6aGyM%!}cI{5o{uIz7L07K4I>UA`wtSoPNm6L4VL@#1|1f(wufJ&(2 z?Y2KfG9Q=jH&c*T0-u3U%FS=9zOLM;D?iUwn!>wM9@B3El6O%+Jbc|h;@hjPDB=ds zUzPAR9*|Yx+QmgC-&VSqIDZ;oy42?Cx~$8(%&@|Ir3@w+^l*Xn@=qp2;lgwu*E9O6KRG={KQhnyBf-`ATa0t zV@J|F3;E#SV2O!R!6BbJJn{%K*iPCvm|m%eqY(=w=X zK*r3)SRq5fUEGuL6J9RvG8m$xF57-o0_fsbRn57&Se+{Q4L^q)J}!T}&!-4fhqhgd zVe5`g7FZcx7w`aBrjd+m#xnpCFv;*Ug+IOWed#4%;!l2AN)ccAnQ)E0!+aOCC171D zCkl&FU;W2sIYvdrS_2Q_?REa@V7kyhmN?)joqq1cG|o1Ic`WLe$0pPLZ@n|^+1ZMF z{bV}z!prGO-xyKmhY|9zn%8Aqbw6M`QJ%+$F)%)SC4>tDJQ;O-cyx>-pHP;-yzC-M z{-w)T)A@@%VbPgEiL?yUG=(?WHKM=I>h;0cxweR(GE$E1`dZ${s5M3pfX2qQ@c7tR zZwB^@|;Fg^eD`P6#kNSftn-zxBGM=OzwJ0^eyR=Jwi zm}f#PT#lI^4r7drunz!>y{gw7-|BSu=r%(L~3?*Cf zs=-&zt*&4`Y&McoGX3yT(Q+OZS0)6-FA_^v@>tncb309)b4#mp>2lvS0{#($0#6== zdgpNqUKWcSH@M0c7(F_axeRnTj~lH#f=W7rWy#n(x1G}pFTyecOp)IEj*j;DDA39L zt2k}N6GXmZ0D59TsZ0aqgR&4VFCx$3<@m%@;7?X4WFfDMK&5+k@1`AiMSyz>&9>*v zSx#_300@g-5K`$JV@H1rK|YsBIS5dk1R8tLW#aW9aI8--j#2}ydkV{*B%uI$iK9*3 zLZJ7O(b5$t-5w=8g|GA0vZbT)R$A$#XTA$KuphaZK&uL!Mi5uXug5c^=hCH6rbb?P zHs5FZhyY8wl#?wZ3+CdS%7d(&+KabK3+HDWJ={6y-e=2J;F-V$Ss})DfwnPj&Q+BY zwz+_ZDCBd?&-`8m+iCVhj3;5FRnjrh+huHI1gqsdS>OvbL&q8hK2d@25N={+2>_1KkC}bUkFgLGrSFnd=U(0(pn)n2$d;*)l-{dz%`71kj_&d2B25A%4Ru-U7w6Sq5vQKGz7%7!b4bz2ja57Yd9H4E3dJx zbU)Wy%(e{<3AjVRztm}^+UBaQGc_M3+_ zmv&U4Xv%nONt7urSeE~2qra_b!|}9!2bxPb>(PW(9-}d1w?q{Cy`8DMt34gtzbjqo zXii-%+0#vYabA^5HFwkz?Ut`8mFYM*@5N{5v0h3B1Ah7Cmt!m<1^~3&vTTL@31tl5 zdCksnRk0$Rqdf72J{UJbfj+}N_e0@cMV-R3Xy5$A@QSRtz zqPL{$i?mCnf@_KEm>ky>cqbh(Afxywe)$o0;Z25uH+Ue*w9k6f=pp93HfXbSC=^VT zR93zCQ$$14~P@{26g$!kF&1y6{&8JG^hCf z{zkDecv}U=GbZgOpCpj}f4PcILx5~g0OCds5q74vou#(&RWuuPDV|0;iN@wtAa2>S zASxy(dsd_`YKh;)d&(%>^5cE+d^3|zOPBA;e){yf_7v&1r70eN-`{0jE$X%Cf}ykf zGE`n#Vq_c&rbWTb1)V>@&ptx%Z9f2w-+UYN2Cv1iD0xhdopT>s!HgM*DKk%wfm|lc z0}DY`2gu%7mhULvMtCvS&VLs(7jhQ^UCm~(CQZ-b0*z2F%dPUk)<89ELfDIb;daUy62wILC;;K*%2Bd;K))`i)1(Haka!Kl`p=xXD^D47r6{AH=aR! zZEz<2#pl13cEQLm8q|m57_ap9r?b5SX@)IYjd+DL)mEgNkDo}p_a9DAojOaOjr{uQ>Tuat0ITC(SQ_MR5rK1Y3>U*y&OQd-{V>B98Hdr)ajf~Q1t^yXVd(W1X=H60 z92&%%qlNwS3(-e~MZ1y(pvqvp8y4#jV%o6`^?*Cs3Kc5}>6{0`sH5{>x^Uql0gw-@?h9Dak7{vTBx+jt}IeEm+u^6nNf;}I_7ZE zbUt+N;|1-LVK-*Yrnd_7DJ;6I!vl=lzx%NdraKVoua3+T6mdFm(jZC)i8lSn12?CC z^WXl<^z)zkbb3omds<`cHXB{Ssoaui&JF&6YXOg9t^pV62fT;YK)#qiDDU~M!aHdR z26lkJn(h~s2ie%bRUG(sG*_ir_H{!QVxEL|hPVh*uXRqixi{HMSjv+av!NXCjWR70 zPxXQ`@I<<(u|lC)#@(%l=J%s_iXZtJ%dxxp9fA+#NaNhTRDwK?thUC%tQ6oQ<_KLR++Mj*g6mS4&-8ckp4>Z96(^I-

z9#e3vDlz@JeJYq3B-$4EZV$<$fZ#LfpaO*-g{{07xsezeO~EJXQKd50G74CRa>O|T zjBRtKN*Z=}#A5{#m2V3ecRU`{;9owM{)SbSGL0H;6!ZmXgO*{}4(E((007Q3o=n+` z#kBwhEAN_6z$)k~*tOPW@6~`CR&~d71Q@A!i}^|0Vtjy;W!nbV(x#>y_anA8#B;_J zy41kcKe?Zo?R(!2UZ788` zz3t|Rtge-I5xBTcO^!o!Q`9j8L>Q-g?goGh66CpU3>Bu~y{_HO7~yS3nHNsXST*=Dh`y*Z7IV$FuuGaF)ViwC*y`CFV(xXc(*5wu;!k?XGe-ktx_L6!H_tozCh zYsd|budo(Ry__Rn!dDNA5b~{y_bZfdP|yrRkIADaJXeqpk10AQZhIMX%${bYDrE^v z;HHn9*1O%l8i}TDw|2as3i}H4i8F=Oz z}B$1QosG zW%T*)8{@VWy6tCBFsj`C_;1?^`xq-h+`PKfnCo_T^QNdNG88|)$G2s^(X=-z=8fcq zG?$t#t%`g8NKlKqUD7tMc)t0oNV4^y^xoXXLbV0)+@8D`dLs*Hn_Rz^W9z1vtMsxrlb zP60+%S@(H=+m@)x1(3O-!fpd=q=Y|SlFZHY&UfeP2Iiqyd}x47wgR~v1j|Zz0|WyT zCGwkkWfWW#3X64SKJYA{js;|#8YB5*Rd7ZsFju%Ypb2SB zU-}X0H~&O}fN1HF&=5DbUp^7;d|6g}6`Au`mZ@rbh_H^y8J8wz<`7gelcJJK>j9~I8DXgmCaUFQG zfTg33K!XO%@|dTaPTZPWIWDgs#?1hdH8n7A2>W0V${L~q6AW&W;}TuZno**79HaB0 z4&2ugq2i#O2*AR7Y;+_TqIQ@^10g9GXI#|k;y8$N8|hkqFK51=VGJyZbqpqFZh^@1 ztaBGGU=6AoP49T;-Ms1~Kf;?wyNc_Ke}AaE0|(EXhJ z;4wqy)Ro#YwC036sq>!sD3dO3DG16yBZeUOY85V79hqNQu+LT)_v9`tuqT~Z1p@<@ z89Id4E{=u5eRBnYd1`nlhST$tC+1L;U&lSv>%3WB{g*+Yz2Ji*ydHjpUvOpH|6h&d*M{VFL01%2K-g**CJ%C zKm%qbu}s^4U@1QWpPu>^-oPYtDp{jtT zXH*9U!SJ`%ql|=y8b?6V>v0*Ye&h>`5f8Hfr|^+UK(@|lAX&rfk4EbjmM16(Jv?owDi=e@1~0vFXGM7 zl|4GBTcLI@bl>CdKzn;93PQX$ zz@rwoeE~Pe)>BR7QEhL=S!gunxy?eQjq72i7w)Up4SSV#_Rt<(uXpl3$L7$hWH(#8 zn(%T{>8L`&d2C)S!mbGlqzc|D>9W-o0UQBOrKhI}C}^HJb0#9Q@7}#D%FZ~BHv%+R zJk(=FWk@K;9e?1MNm9mN$AXtJcEVz=$`fhy;#~qyTj)E=a4gBYfO7-Ny?$hdA@Iw- z8$+bJ62&I#+y?j*TYEt>%NNf)yS`H83Z8&o8QM@n62x*3++uDrHr=$pb4OG9_>X=d z&7iP){4XD;eiVnak0t{XwpCGr^H~eEo(&o##S!7eqY{ox0e8G}=z}nG)a|={Qt*~W zc=qDMF zBS6%{I^|fdYeb<>HLOd{E$8_t^KthsqT{>8656cGydIUd%lR98lRyCG_5~p1e$k#V zhR6$gF$dhzQ{O;cv`4xu9;pCp!o zcfOV5RvbsFkx$WTpY;gfDxLxP64K>YK)(FJo8rFc%@2NK9gRTAEkfk^mp9#XAbsd zf~v+lCN9V%5w5D>FdFud)UYQ`>xvpuwX5J5#B)b#AxM&uqQ|hnoO$IOxwO7-gFk9E!%}_6K8D-X_~zs^4U#+o&@)r+89)^UAWLP@ctoBrpAO z9P^c{C8bpaLhuG+8TG`t7R*UbY3*@mhBtcMAZfI1+w;r>*s`rf)XIvq;U*q$Z7;Zu zC8r9l7jzWMr({RB^5ZSbrg`+~|A8q#vR9Hb$23G1=jA5jty+-S9v1*2E5TwFApA0S{M!lyr-nwFE#@fXrBBe&_d2Y9WtHQei>@u#& zmADA3kzTl0B48AYsEe&Q5X_d1;>xh$hP0da@rL(Qy}?{};a=4p7g~bo%Yr$R7EwmP zf`q&K{M=M5_zQC~>bRuA47s?<+$*emPOVlo1@K7P%hC$yzEsa1pM`l>8Q>_&1Qb>vEyqSn$K;6Mzm&#_06zm)8H z=CB-L90F%#Dhl$43H{Dxt61Iq9eFlikbv496zMbHD+oxJdU{ij`C%L?fQy1d4gI^; zb2VM;?@RaJev>UHjzCI>5AI6~tRXUkEFe^)LKhcD_X*3$@?FV#w1D+(e0nAIv9G!T z*YVn_W(3Maq+gXNSnOHLR#&RilizwV)e&f|zKP(l2&c8I6HP>tmWfgz)9R$4d+(k1 zpfvFK#5I&b947>BRG?(GJ9gJIdsQYZQAt}z1FpEZWUsRSoj_&I0k@si)w5>eg)ld> zoF<64JU_@$e@oM8W{#K&l;awyvfN{zEQ=`_W8(buZ!?bE$c8iSyDwZ3pjkEN1$BsIf(B@!7 zJ9ZxdpK#e7?oSu4yhyr+P}X1SWnVcA;o_p(9%@tH(6w~x;zgLxjxKP7N5r7kbrDjH3=|lO?c;+7;#*2(-W{VDkpMkZm-|!v26_-_v znZ#`c{tl%a)+b%BH%71?0u!mY^HHU~%0FFM&69;UJp)MrynJWD?k81XQ*oqVEW^D4 zJ*{lgUAl^h)w^(=pF-eW1eZF2srWVuE^QDTOGO_ii=ar-%RysEOs!}eW9?Wlw(fPV z1fT7PTOOCGyOK5*Zmb=hZIs=DkUg0$Ug`}RrQ3Qa_)xeS{d<{w(iKlVP>IUajng-V zMh3yd%1|sS7${`a5@JPH&h(of-Ruh8z+D1{XRyGjS-L8r(sLMR|>;V<^NI}hhjELPPF zhvLz;O5;2>&GD3`=I8oQYjv`2w6d=#Q|Y$bZ%)7do1YHFy50x0j<)Nqi#H1SoZIpcSxBx6?*ivcA=Epr z8X8GSJ&XxT3FR4fe)%e%aYvtRliQWh6gt5eN9m73w#vWooRa|1Q}I9pgS6RsVIIpg z)=TU~r%mFPa57ypW9)ICOCZewz)k+vq_kuLDpx249Oa^hs@mqpeiK!b9 z%vm(1br4UZKI?9hk66H!t6Ihe2AhS-KvG)o-ES*VQS;{n7D3f)sWlU^TvQJ3KM3Pe zm-_qqlNux!W`kk5-$XYmgVE@$yN;H8XnZ;iO|gfrVJFRD`+!7)awRR-T_xP|X+}Ta z`fFP{AD3U(XDH8Hp6a#l1KD4vj@Qopns1`z5RA>snf+SV=Bv`pYo;yUTafn>9luM@ zef;-wIn@~<2Z}3*Pu%(2kt_A9tb1jz<2L`fLA!Dh`85cZ+h3N&@hD}>V7NgUk-St; z@p^k(%8D$SyZNZdv-#k4ZcI=4&V{(5F8;T?PYEO5XyO zE-EsCMZ=tEii0eg1$4s|p2aHm+B3Hc!7l2jTBGd83hV;y+(%L80_H~n*e0p{c7Y2w zG+f5&SODq}?tQ10+HE}UE!1mdOv?jInMW_VH(xDqEW(xt{c(}CESs8@8H^qGw%m&% z<448~e{m=Mp)%tO=<2_4Z3sGrx?z1W9oVxY9Ysmmd-+@%>_-4+kExyxTCQehr=d9r zQP34N*HI2MCE!bWF04MYpENpXqi_yJl3dp50AE0$zgYRP?K0U~on*GWx8LR$Rx;A| z$^F?fdMa3q>boxNVRE#%IaU#L$gw7$?GzSXxu>Fm7F!l$$Cl?>KCF7`1a}b_qn7}n$7ylW-`wlU!$l$a`%a}4|n5L7(X}) zJk;}<^9p`9A81TR_jQS#39o$CAok1yC#|nu!mGZjDUD%eo1R8!!!3PwX&5(f)*vET zJ^R8dFgr82;E$!=fss(^x|i5JiJd#T&|S5qsoBwV8E>+a$B(g2!E7UBS&qzy4F3{^ z)z(!axFP(sHO8p~YpVp5LvUH<2sag0u6qi|x`VfO?twYt^n$@@1TgZ#ggd`BV0dJp z-IIRy^fiQDl|2Y^;DhUH^N#uu6c$j0 zI)F7NZ%-4tmM^0nRw?icRH1yWn|VYU=-)CXZCxx~9#r_G4J}mSwf)F*)_Orn+@AYV zMeY7nQNJrS;BMQ7@Ot#b$<%i_ABCiayBSOOc+4A)U+TaMf!G|QSbFLRxH&tsm^zyB zcAJHTwb^km6f$0bf}ylm?}chC=ko}yow4miYoN*s`?(A2?|Pk4t`)-dD$sMK zF@#KA|K01aVnR!v+bQjb)?8_scxM;F%Lte&3{Q+>Wyd2)KF@XwWQ96~%64KCc!sv_ z=|1kh2d#{N*bpqGyPw2A?@R!odT z<4`In)Ve;YoOaxonM=mGG61AoZ6?511EK9exudejHOnnG2FfNIF5v5=gNI&*?)ZQ{ zI`GAM=Wpkjzs(;CTk7iTyB0<}&xJQIT=%~2w41UmgYJR*jBhnwQ^ebt1OJ0JpnXnc z9QEn5JW3vajeII8oUfS|Vav?y1aPj7XbKJUU>D<9><9XmdIM8Lc{m`qC#by_6`FK z8*hhn^jkVB&m@itlgLMzt$6WRrnKSGrSoxo-&^m0ka5oY_@!Bnr|V=fMr7l%F8@oL zC6p9+lc3kzQcDu9hb~J;(tg$0_VMN`uw;mpA9+%5n#!}dYH#hiO z3A~Bm960Jc2;~ZNUpVIaqcJupe)A&VZ#^jc{eye^125RW3UtmZ2G)g7E%+W>u5P>a z=Jb`XJ;m`+oCl0Xv88b-)wMvJSkT#&!r17d1oP@B@?XSqxc2Ya7XrM3yTZLhc4T-Y zi0qEmtRZq?)2-1u4YVcEbmBG} zsv(U`uB2<@9JPlPq6%vqDyYzs1yATC+J4bUg@y0y504m4HJbB(gNs&wvtvgjc27d=MpBZagW= z>A(Qv+$WwFZ7h{vw8#2lJhtceX_2S&eWSi@HMXqoBHv~!%WiCFS<M?gS zFqbZTHyuBUOLIHtzt*y42n#Bf54Gy7SG zw=kF9dCBMoBNV?NjXYQBXg>nJz|%!gC5$fmF1{WGiW>#OCc$v#J<3c*LD=U$75N;u zT&Y$>7zz5YvP#W1)t#7)j&vHE7B9iEU%568|XIS+)0~zcK*n3Qr zbkx0?2KjSNI#+L%V66TBs2*=BsO(Z$rT0_OjO#!N2- z_eU!%&l`IK8;i6>!A*ffFBEBpuG+fq<}skwASnjwYD_nuyg8Jdmnb(BB*F%Irr@R` zWC5JkeOyLgnx|63eaYTW0wV*niCYSJ!byQ#fu(C_2OcdPJ2;5zKNfT6s20wuN@5() zKfpozn9I8RqNw!JVCkg?jr2{$i8M1}kpMFl00$A)y7zCe-E%OEO73e{Ay?p64fW_X zwZMreDp&OYwaqG%S5_=n>!=0z`Sm`~1H!Evu5ZQ?2=5C7dFP?{ z#;gupn`IqWST`Pl+fjw9aYkx6&TtilqgL!AN8yuc*TB#yw2Jvkzr=?aL$+EtP9nDJ zgkvzrx~S)X!O;{@0WfVV6m6ZmMnTPC9aJhW|3R~s{#vbEIvn*KOPRIb#; zyjYE(iqBj+mrkF4DV;uhI=%1x?@9mq7k@GR(l7rXY&AGST`9fw{=3;KvNx0|FTVIv z(8eQ24y7lacq0AdpZX{1Lm&DO`_p@>CiSTW`KC2<|MJL*3oZzH%0gB*A8we7d&ccN~OeLu(6Kz~%M&bO{U1D0}{DTe{LJ z$GSjP!6*d&~g#i{f+e3Jt2D#k8SL+2eA0VGcWg*`C~giRKp1A z*1m@8WNkxBnm~{{bFL>HJG_^6<37p)-h1^5-p8>;74V3+s;bj)(5R z{dgc7#(ZJzN)GbTp)<+vg;W8ZbNucL4i=T zh9w(!XB8HSpnBp+&}|gcp2@8>s2b~PQ!`fgm2nt$aZ~r*Y~>OE#Mx%nOU!HG4Y9sF zmYM^w?DL-;<~g*XVlQn3hQPnAt%<;nSYj2l858F;s7ATjg5+Mz1q7`n&VOI17$yb= z!RT1;#Y2{UEdKRaYSvR%Ye#ze+s~#49(;Rx%RP6bTTXmCoj!FT_GByMg3>5Q&eBhV zRw{6d$T7T|e_lmKH{WmGY^MF*Hy{}J5aoO8MG-+eMLznO6&XBZOcYd|r-6BNKJR&U zJZz`)Divj6KL4v_#kc3bra~g|33u+BRv=KK6%u zOx_Gu`Dua}YW;7hCm1CRw#>O@w%{TxE~#)*3E?y05EKU7REe<0IIEzwE%nT+E?lWq zVkn3h_*mnOm8WLL*Y=+a|Kd`zu8&518_TTK=9OJ?XY^H$rAJG@|APx(4pg4 z$9KdLgfXrtJG8Ji)isj_qZ93P%#C{?-YYETvfW~V7Y6WkOzRNTqHTDbwavAp@lk@} z!GBIpjv)XyBM8B70@qM}AQXk7+I0%ZIvd`hjGEBcXI~*ap8uw+bw1qIJlG!$?)HJr$B3oKL58bt(oj4-$<^p0RJ9MqeS_@R=FrqB+LlN$q8;Fod$TPh3=+sGJ;OUo!+#V8e`DtUhY zGtb8JJ8n6E5(JMfls)1>C}kPHX_T@P1V|mi9sLfDy%RQH`r;ST{rBIS{^>vYsq|-m z_UGxyp<@V@9rU}B6F!bbyDwkri*|X!%JWS=3KzFa=`AI^l#yoHW;HgB*AjsR-IC`RxX)iDl{hZ0ub{{X zIz->rS>zS$SA+%fR5NLGxi_xI3TbOmhPq9w4ux<%aSYtHrl*fMY)pq2Uic15j+fK@ zZ+m+@qsVAqv|FLd2R7YCZ(jb8Ut#qF?#slz389`juQJOq(}UVAKW%MocsX7}c{c$q zXYHZ?3@BUbQ1Z}cPhJ{l%h8fJ0)A}(CzX~Oglk!sr4cG7;tCLgAN(splgIfkCwTMx z71Q55SHM35UKbwsdbyYO*wMpjfA=ns6ss1*XNm=>sR1o8R{PotwK5WI-IjFyk(l6e z%C|?Bs2pg3Xm}Km3u70WRw;`X564u(Bcbu$y)Ig^+^?Yv*X4_sBQoSDR{mkMp(3XQ zQ$m9$Tx4>O<;prP_|rt>oWL~+Zm*I>ZUgO?f_+{fDBQjUf?3(NE8cB;_6C2th=luc zp6RcX>jrhdPLA*Ab@Y`gY*X|##*^Csa0vua;8r_|cSSwLf?E78|K6U~-xf=OWf?ysjYP|fZ`+c87KP}G;^QI#<0}x=&!Bhx7uVUk^6vi9z9tUEMQ((9Kxy#F_w9Bfsx^J z-+V!DqiXV(MvpX1E(o+x2x!`U-piPUYaAIXVcze!?bdYQz`<|{biR5li$aY|Tri`N zUWUrOTr#FC2+UtCG>eNcTeL&r-QYSd^tO$X^P=fO>Tj4_pX-z=!>~Clat{9FU0!W% zy{isP6-=iZ>?Pb_WmM34W0kE=Jy(Y!z>^+72He@Rhofc&ha!z#mX7J_87_eUUZt3I zI482u&TrbK5+y&AvlaJfGig++$c%XjD;cFoOCbv5-pgpq#OTte%VIN1&wlq_!^CS< zb&=2gq7XsAI9W$TQjZsw?)bt`M03=ev)-D-G4wm0m~QJ5oTe)!h_ocPWS;xC_?ReC z-k=oUnJ%ZWzED7vlq>PnLQ7YaXoL8#&~#`=Lwe=hh4jLygXzSv1FRj;as%6u-!`wp zBvpd9y9h`Hk!NuLhuM4SR`6hUt(UDEs|r8757@G&4=8~LSS%4N78a`0iQDf=H{Wu5 z>e_b@h0bzn#TC}$=~fY{bd#>+Twg8UT8}gJ>j*tqR}mnpkbXDTJu4i1K=rVWHlYe8 z)}tdgh#|AIVzhSmY0^@Z3Dq!iTEO*o3(pW?C7!dMX}w$9K%kz_0c*p8#~>QpMy6U} z%shef;DX~jc?w>cqf}_*l$mP!3Fcufs!fl7`N?$u0}rG_ zhhfB9YWP$mP>iL&eEiSTp@WCgrM|&5gTf`4e#epSi8F8L5)^Orf-Y=X;&Y~q+t7o+ zP5T$>6R^zSYFJ?r`kaRbdz&RrLf#&MpsTlp7X_HdW+-5&h}05l@Ht)XceJ{fy%M2s zI{Ks_FhU#!g|HlyPXk2_N)L_?+})P`({DYN4jt`;;olSVP#Wv8e2eaDX8g@VShpyv z9)ZsZ?OtK6hwgnfawI7cahKU!84o@Xih=#e9o zO)L-k>O8AKV2v#RC=s>9+PAfpxm4Rxoemy608Q*bh&CwKdV2o(7t&Y0{>^kJ`E1rQj)*3Y)iolx(-Qe}ml>5h3Y)gaEnv%7ZQUAYoGS&r zIMNdZWO!pR7VFT;E@-JV(x9iKqk{w?+zTv`1)y0KoTO91b|}3(HlT4pG!#2B8Y<7O zUb)1n0w@azCRdB+mCevN(7v-NedOaGPXFxZKAxWV##8C9I5lNt^di>jz0^e_Vxz1h zXG~AwC52N)6W&A4yW4JKO9C$W=g*!+(7!dEdhvy{AG-6%55Frt|D6}pxr-O0AI{++ z&V$#$XuePX=5Jx$?~d3D&WR9$8N*OBu&&6zgn&;EoY&5C*9~QrMFei~QZI#tCHM=x zak4_FKE3mY9%haB32?6;`bwNJ(&*_iz}TKUcRpy$I7j?SRD7;bKaFSEEOWaO+FVVn z826^T^eOn$Fz7L!c?k8?$T+(;AoL@Lxdu2-oZF8*_88tmyP)ky=mQsNK!vyue6hlK z!Jk-TT&LixOvDRMypVsJ$KV$ogR1U4YJB9jbvFy0P9Ao7jJLLnzlf*Zg8UQeAMBI@fGK$@~kF#T;WODfOr zG|An|z>oQB8Xo#DCQ>O=yt}?Bo6RTEdtxQ(n9sb}{qg zedHs7;~fGlL|=`+8u`nYuduLN2Lchq-G$PRZFNqq8pKWIA3w$?MsdAIlZ}N-D~kPs z(7+IoFtS*OxXSZb4XEFO_)?)@JERG|Zp78qlrmBjKspQH3H>(j909E$H!xpp6JUjr zeoRh|;4VqfuLB%;hhni6K}H6-5(`BORs$Jk3zuHVMB9BzQ{tm07JCY`%&>OJ;IhD) zzJQBKg;~%uGm|S694v^YGmzj8wC>G#I5hKZlv$7E^ek-qrd36z94MPSz!P2L-m-+N zcpw8T(`<057#rRSA7Pr|WM=btmF5t?E!W49C*D)fWC_XZ>1XOPO9H9*w6Ep{uD|GsfRpYB_> zRkkfaDBdeL08?SFAhv`Ms`WS`JOfDgjw* zV|fiESIa!wf%QwF-E+gWl*e9a=9IV<=SwplGcdplOXESm9FH#CR27)zl@t`iLxb@& z;MW`h*G`@|klyv^JAp?-di0&|Ouzd(e?)M&Q3UW#U@EWY#y<@)2|L zU0UZ<0)-zA_^tv-+GAk4d+xa_z5T%l;l&oxH@@*y`jgN8IWR!6sG#YbrR-_kCX6+q zt?eYOR=7sIQyxkm_~5(K`@eH4{q}GFJ_5H# zcj6Vmw{HHnbrGRb*Lwq|`7C={fzPxXPP^g^DZubkJaM2r-Ifn96Md&I5jC=n>=>}}|2w1=x+5u#VDJ6z z5K{H<*pDUr{(J9Apa1K>Nss@{GwE&j-5yGZajd`%2v-d#W`yewVlBjW2i6OPF4v6( z-0u6~g{AM-(Sp@_2V2nU;F;a)e*3LI9D)7*_kaH%p)(aIV{Qxh&S@9}?>t`4Wet$S zOQR@b9dX>mjVg!}J_q~*F3^U<`*(%`O<}u*U~@MEpUYQz(;t8Ki|M|5IgSA?Qo>DlL=K_PJ!o*p`j z%l?iX9jvLw%!$PTn5r;P0qdHWl@K1&Isy)_fuC-bJ#pgJbZAdYdg0kGrAHopG=1`u zA4>0f*L~^NKmB{@zx?Gh>Crpy0)ob~Aix}+LcP5sY1bZ3vp|9I;)|!#eQ&t~MP)5} z&CipnlBoF{Z`i$$_SV90OrdBTLCHkWTiRk=AJ-=pHNCxk;1?bW;G65WYkowImqzh% zzkKjdD1e<;0%R3Br{}>ExVXkPFV_JBFp57HE?om(uBLy4(&E73qqOb$^zzH6q2*QS zrjsYwj?$Sf&_?uVl!eTMf>b5L5S~%XtZ8*9$g1QsD%|FXlE`_?Z-cb1p_Ea(trA!3 zdOcfm?1SyC$q?vXr(;;w*D%KfU*(Nd;mVZnuu2_&UZS+Ky~r!~?z>D4;x7OOki zJd2bBX$52v@wCnlKx94t(Zxa~fC~xqj71NPBLr`W$l86lSdPr_fZ#nFxL(Sr=`IES z(g*(V32of#V2nvc-tYUeo;P@jw*4tDw7irpqQFxNr;X9q8`QTcXjqtuZ4V!bc2Q>JE#CY6 zs*5p+igHgj%iKha*XbecdL!3nxhCG8$97YULYh}mV>E#uQ3H7tA{E+QG!-ChcL-BZ z9p{yEOa@CK#i-c1EZoL~U8&9jzL7UzmEUCnv8Y)!nz+i+LK@u#wbpp_j?AN)Y!{Ls z83+jqHRdGgX5-y6Y7nsynrO=eTWmr=k^GavuIk>X+q&7@awF60VrGZ4wH_81rp~r? zaXz!c&E-p%!fHVw0Y~#za1@O0+PYg-!!)`d(r8EZc=DXP*q6F+W9(v~P3!Z)h>fp} z#hJufq1<;UL#+@k^KMr^N#q%#dokp;($%rh#bh+UhQ@&LQ z8*i4dl3(th!*vhq1dKjVqAxZLCRJ|Zw}f)nh0D8yaT7f zZzIfW*{eo~ltW(zKj+vJEVg^XL0~;y@)B<|4v`eF$-FJ&p6Qs&^fkepYt5?%kDNOP z59~o{HHd-%%ge;IwEwUQdG;Ky5@Zdl|FN4|(w%SFpZ@Ci3GhV(e*>sBVJWP_G8bNU zRMJdz>-AOw`<1Q_RTN9E1mkCKTXScO=vNsBPD#v{S>bQFY?bf{?~CXU4d`lLaguNH;@#X zZd37DFzbwQ&>h}3Fy}t_;g6(eo_;!x_$ya>*KJ&+)!|i%6Whn$IP${%j#*uRKC~fuf zY(_D$!Fsa_Z&-&gBD^#hF*50yr=Cm`qk1JYrhoCXKNDkg>eOlGU|ssZ{^RdprRB5& z<{JO8jN)RI0&diY_iy!+Gp z-}~-#;x~Rf{pxT0L3;51J884DK_wwdG=z4&v^;yBnTxWxDaJ)5gk$L#sYse*JnCxp z0~@w?a5Be%eLK^A_uL7NJPdyPTI#vjL*AXNL+$~eMp$FtK5eLEjnGR#C4@0G#4Y<{ zU|WT_1>)TdVJ&V!@m7oS{*yoRle7=d3zRdr;lcEO{_1~7H{Ehu7U&Sg=xL0_f4N~q4x7H|rh05FB$9e18c-+1Di>C0dG0yOd{mRk&X#O7$? z1S=KSuK5eVT=-_;-gY`S5ek`C22DNn!ZYcnBYROe)uu0e_IJ{WTW$)$_<#I`Po$%} z+tVL??%V0WuEXd6P|U2>reU@tOw5iz$MDF)NZ8-c@qldgc;SW9@Fk7u_S^14nKaK9 z2exgn{l!TCwn0zeP%bjY${UW4iV@e_DJnzjtN~u@ws>Jk@VOXo`Ns=zte|)^nJ{wiFC2&3jOYbUaW*?cu zv!!@4-uDi2v>Y)9s)@g$=kY2^eZ5JjDcZ8ZJ6aj>g6eozW8I8{3RVpUDg+J0w-b8) z#V`I1N|o01{`bE>lu^3U=YG=F61mLlzH^85fw}Jsy>mRCa*!Bi;{mC zju&t8KUM#p>&?*z0AB|C%=o)(%3h~-#e*12FA&m z8GIMT<}|ffk**BSq@JN!wi0rNXiZBnY!zr{WuyX`?1CM8qlgtS@J|^qEaLC!lIbW) z4yKoKi{IO;C|Yr&?^pLn2AYwgpD}i?QRwTv&usu`0k`}sgYGp7ENe7FUdq7N4I5pS zc-yT+=QROgamDz(elv2(MLOY8R##C>*`w=k%M(P#Qm5j%_dK*rzpl@D{jUNR*FW9- zb$zR%NXpCqB5NssW_(NaiaXZLN}0!z#gTc@+1AY7x;7$%Ph;`aqea};!ov}25atl< zLqd#cNgJ{RVcB6_=ZWQo)s#BI)r`f<_t8iHSg&8aH@AYf3I&-0wc(-hj&|8b7-9Y? zh&cD_*uShtPd%2M8Z_^NoW*^PeQ#>wWw@Qwx}`=P;BfSoZ+}M{yeF-#F*Sg_% zxYom9*)G#-J&U?+C;!4?M}K6(93$ZqXM1C@(~4^V9htu)hmWS+d%8Jm`ciu8xtDmy zUR>5b?55NYJm_l(t{Kuiqkmee`Ih+z!4w8eMZ^c*^GMo{b@n{){OY%#XAMQO&;Im` zAL0qwD0vfSXjkcBr13uJhVY8Ce8)KYn+N%Sd|OgZlfO+K3Lv>O6Iuo^^Dh74n^%QL ziQf@zTBQijb-SH`kr+qtp2kuzj@4&qbQBlbE&?1LgyyI8;@L~-nO82sXd!Gej?#5j zmiV{^MMc0y3o$%;>g5QakAC=JEY>^Ix1V__jd0Ak)L!1#M-~RgZ8bZ zt{pJ9Fi-+TM>TcdvWUA>TwV|BUfuA3+W3*fSfX4k#?^!&3u^l3R< zjc0H%o*?RVos1exqpsWaw7U(4%VV+>uw26wKehSFIn5%l`dX^(HjTK9M`9wNUs;khtnt&70eI44OU^| znqc%MNBd!<`)Q?CN=|x+J`uI~%20a#)FtK@3LAO5z^j6G*JJ@0#Gcd#)3FmL>3c0!?QvXn zM?$c44*LlKhqfua+IQ(rerLIv7J0t>FsB0;TfsfbDm{TmyGnmjU|hmzHaV3!}cTtjy3xkCI{!J8s<5 zvy?U5m(C)DN++)pGeoaOy$!?_>8cLjf>4HiY5=V-AA5e7bdn@)cfBx~p~3b%q}?FG3l~B$wyw zx%h2(!8(}zb`$`0=`C-$6Zho)5Gb@njtmJ8PYA)&1=^{=r7)?&KxK>G0n!fVo5~gy znC?~9vZ$-R?;6-|KaXCxR<@P zT)TidI3k_W1$l|nRZbqiDLwo{C}!BgF~R=homfUEfrsa`+ir?OIpTH%0K+KCD+>$P zCojKUFY+46yy4vxJn&v<)Zs(>_>IB_dT{SOZ$VhynSSllf1HjS-Uq%Y#Os!zd9t(s!PJo-GVJp&fWx zAc)!Ce7VL3CdT^eop8=4YzS-0N0GXLLT4vI?m(Fc3i#-w52J)Vn0^}t-frmWhV29Q zLUF`cc`}3X1EOr&7YaAp@0JL?D0FQf!lU3QitaiT^&1P5>B#=hbO3LOcRcuTY6F(P z{kgBF-53y;jW&;$ma>57sw-gkUcHv|8uZB0J$v@Cb?W8_Nczlk-@*O;Ld@+YC1F6w zP{&;MUIPU~4g8#Q;*;KgORPt8;6HSgH2e=d6vp;TW1-sSSbzBK8m%|t8bY@;zZFaM z`HPoOezCPj;hA!5YctydPohw10sbmz`v=%I!pSYOD6Ea|5^=%^Nb0Ep6)0K)hLmr; zegbxZqpWexJLfk|Q9zexbDX5%FR>LNlyS$8Gd|)Y@e<%;?8&A9f?xhtfjEVA{mPZA z>7|!m3T2YsCVJECVJ!5#>gC;x!9!6<$=|2|ufYx9(>U~&R_QzFDGMmIR%1-1e{<=* zkGwP8dGnD7j#~+_kO~PpQO$LxxWuvRFMn@;c72K;lwWTy!Ct6|&GD5HKNx>ttxJ3h z`$DD=6fRyO7z|9hMA$Q+4eTM~8yfCnQFKvZv30Rh3md|HOh_zZp%u(T-@qXuyhH33 z@%!^W6Lg6oh)*81OX0f1BwEs!1$XzU%6SwrdNN4ixpH~%7{=mfL zS6Nx*k6(44^I7kW{=KRVk-Sv)_9|ahHV-Vfl&(}$PE|bIp2z1VEdN9r#-RLJ*}Vka zD}O=G;wH}ppXa`L#}(}{^R}y0#Xh;V1~DK1VhI2D4Vjv6_gqkOr5XRZgnx1 z+{hrhGAd8GKQGGjkBM?B-dPVHl4{|rVJ<4v!-qgKaF=H8_FaR9u;1MUR6)na2EmWY zTrByJ&r*Hv?^wyA%egKYQ>`CbSro3#8tsd=L}|HMp=4CiK+~Z+Mprff(cnN|I=~jA zMqDBlZYVk!Bp1d~VHOzAWSoSDfxyB&518u?E1hydl{t`62#XbTP^EwiuneLLtL}U4 zxGU=V-;JB#?!DdV68km3@TISZ#@>D7OIWOA5~wlPAK$`_ zBG~WgOlJ}7zy9s#=nL(~Ej^E^Y3Z1vWCk1e-q>5N{IYcK@BGR2P%{G^NkVYX$^9KA zScLcfC^GWx?^5ZTH?}3b5O^cQ;bj!?2`qVId?sfW_(qwF;4p?;piFMpuHC7Bcq~1A z8Vl;udKx2u8w)|e+5N35H=Sa(uS$@>SCX?N++4dRfMqNzKdaLcB{mpLkDr=?8RbFK-S?aC}Iwz z2j6iwbuM8Estf^kVtgLK{t8NJy;c|#n6xF_ezo>{T$oI&o*kXUmC+Mp1S^s*%TA+U z^h*j9J0ci`lUIP&d*AcV9hQ!{cNJQ@*bboOvXi5!!6_~HdiGg&_TW?QCk9RTe zhv*{_{;_sev%mk;3;pTp#jEV|Zo?8uwDwod^N#H&%pGx6t5yX}TkFp5boTrhmNCGM z%Q6j)y2BHMih@QkA9a!T?DK0^&v6XxC7AJUw(FgYarWrHv*)j*FMj1oTunJP3$@9T znw%0I6!c~jQF6DV@A1dq0>O^O$NSG*B8(FEr- zF40)CTid(RFhakc2}9u86oK+|clVriOOs|sBy`Glek<5pjUTsw2s_7E7k%lG@r2y> z{TAHhr=Z1quv%%@5FhGwy+z4%t)Hmn?r#u(!#bV&QOs@24s3uWG z8*$qpb8gYv)wLHZ;>W{!y|_4zW%Y4f&F^MU@SgO_%NJ1yO{LQ>pJPn$&4JI;!faWg zI0n963MDEdB9c7s6!7a&kS-xm%uEgAHjn2F3Z-v6@z<;|E%AF0MNNEwiSakwXC7r) z9v>Aqx*sdx$F>1*S~q6BFJc}tEW^XSL~9>ruGOQgnG6pD6=<#|;>GD#&QLZA3Epe< zRq<=z4Kn9^>SvF;$2@i-tlPJ0)@9f0@$svafC2`qx=Wkevy4pt!V9PHP-qW@Vqfnd zWh&?)KrwfUwJlELKvCcrC^V{A2z+E*-2yN+cm}1z`BaCZNzV??Lf?O2U;6HM&mf3* zBJ5s{`K*FKl+fyH3^}r$XVmj&R+EA)ymIpX2#B ziXs&ml_=1rq2pTXS&@+m+}`79ISs%b1tK&%qP?@$sbo=UvCe*cEz}zIRyi@D1p?ks z$5xr4{`Ay0pGcQ`2G}Np_XAe+DHOj|(CRg4pL1t+j$n%H3!lPEX_WW}!pQgn1B~~n z)32bUdWriH;0x^mSEUTua6xwHP{=hrb3F$*O?nUlXklX+0K`tyWc&12Kdkq%P0xS;;70Y z6*#M&pK zm;;_@oIsQ#Lql+sEy;F!9Ertc601~l%a4S-8;An6C(4V+Z59d98imjc9WUHT8p;GiG=14 z&F?(HTQ2ktr>jG31!!UqBxe(^RucUf#tLa7>Inp)4Eg%+>k{`x!Z&=8AC5tym5jo!lrMhsto-}BAEex@qDW+c`M%T=3oSL7ClIDQ3rtgb9CurPqMZ~R zMQ@hB^}e`^_C{UBlj7S<*5z;Em!D^5k0%OPEG9BI`4VR!t}s699QT!jQtm`BQ6M)U zjslPt0{7suU@+%4(9q_7<-X>g@RxSydTl@Dmpb9X=G^g}k8Djdn3P(A zioImfNOR|oL^(c-Sta4JEq;U-os#L9#M<=?0e0@W^On%0dt~1XRAONb^|)Zi6@AThS)V@{5+CG+I;ZkM>25OvPl{(-uVb7|8TeevLhme(R>XhH zil61rBPs8_^2;bA8tdGPp)MM2F{Qf8vJ~y72T_a+WgZTh7i4mNRDicjTH$bkJbiI2 zJx0JfkCmIoD{GXs#ejKLFj2;E$+)Q{K-`eg%e97e1IEY|K-OHEzU}9%d$1a$+WHj=*bm_tn)(rVhT~_Ub zEfJ>FL%+0`Y#`iNhRmOWP;Ja%;cVX-OWL9ZFS}!x@(U%JK`|N3mI2mF#}5=t2j4Mn`O)@RC8Ko3!0>Q@T7plJ2^7XL|R$A5Hh&cQ3-hS{fN2 zO;0}kWIBbHMNLz81T7o9JVbQ&?D|Xq95rfam3`*<7t_NJ-J9;b=N_2cL)3w?1$bP(bU95SobaYPzWKy+?04P+zR@!pZ8?HBaH&K$vx3O|&Im^{i|jS-r!Q;iCw}6`agqNZ zg54u1C5F;>UU=3<(f2AWdo$p!3RKpWFxChG+_u3BcA@Z0gB{FVqlh!I_Y8vG z;e$KUkAC>W98K4bmHtBd(?9*=^tnI#^YqU?`QKn&y#>L#3V~;dlLM|$4s(_MBR=G@ zeIE*mM<{y$#nsqYKeU|VH?h9X z%ugXyBj9312qe-#?KE!PulQXKQ-0%I|#OfXpHr*Y%owW~GCeDTF+ z7>98L%H0US?Q8+)MS*h|WyfV8Ow132ZOb(8I%}Tw3j0|C=LvHKb5945h8;b0B>lqA z{WJ=tW(3KZ^z5@w;tu`_mh=PZE%)7tAYPGn60Q6yN`od&`p{d!_GyKeUb&_PzW{vJ zRynecbK%9M=BC#4!Jqv_0ykDLC;G7F_A;*<@i^GW7~t)K=R!A%y;HCBK$n_;Gsnlm z7n`3KLJ`Un7F$G>VKyw!YM|uAjLym@YzR^uiFpp-|6=;RC<#AhyLF4Nu;`nHoq8PB z0)K=;L_uBp!)q>y5&!AXPLva$|LebsqewsS!4I%~WM2g6jRevJ{^_~c-rg4ZnlNm5 zspP$Q{#?3pxd$(-x;U-Dqf(7%uV>;q4XFjL%6m)9?M2`*0gp5jBxw{52xi|`AU(KT0&`uyFg2O;0^3tA}cPE5M z95ds!5QaMK0K;pGZ$pvgnk{Ot752J)k1gU)Sr2-=jlh!wzDT+ci)0E!xI}2##sp&@vH)Qmz!{7NfO6OT|ZM`pR z9WPC9+2!eT+9Ky0`Hmb#8AVaszbz=5U*3nJbe{P*|Jm$UIXs0#6j@4IR9BQ>$DW|=CfTeBFuaDukwV2TJq>3MRk@79f&emToo)}E26*r@V~Dum5;x&0>E$KBRqT@ z0b@+Y6)8=s#+ZeX#_+9ME0Jbd$oq%KQ}xSd(#x_EQ=g7cXOe#Y@^8 zZO^arSW1t08I}3odrAYQ*Ud|whhnLeE=q`O89$>9yer~t@G6Rw#^)mA2@iEEr+fqe z_b`USN&(E~!nj$EM_Zk_IFL@9JkGhyBWa4r@G?wV9ep2o9KDrklj=w9+*>ez#RtAa z81)-?hyqzsHWgM5p2@H{&hxVb6~on3*U%Z56~{1yed!~Np=U8qj9(*2**DXpKXM1S zgD^6@fW`3|46s4-u>Q7ofiD?f!-~#|mkA3c;>J2nWKHG)-g zDP2BCA34dUrV54|;dKfjzra_T5my$NSa11dYZO-W5zs0qZ>)>BaPyt%)xZ(JSR@95oH@I+?r#|*vEXKQu|rdU1~!9y5Yl8 z3f|?puq|(R34t4dvrG)UZ7HHvoNA~#s}Q2Le z9Zk;3y8jF9;cn`Q2UWJPR`{p>t?TcUf8j;ZVrlU9QN1^qubmr{Kf-!=TIb$j*WADCh z)*L-Wvr-_uFBo^RS&ORlK^i|Xp^}5(dI&H}Y`3}lo_o_>ci)36J^?bPM}g}^L=V5r zmWMv}ve)5>Re_MHRaJpU_j~7~mQ(S;7zVC?T9Na*;L(AL>6_pBc6#((52gb|aIZ%& zefF6rfmw?6;<@L}kY+s{Id%*;a*mYcs87dDIH(lYatdZdJ5?ZD8oo?DS^4By?_C7a zJbBAOoVF_2R&kJ%4W4J6twiC|Mu4|7VTl*ko`z75`?$wyMgT?14&@~H=ZO&$#C@5^ zBW{T}2#49;@R5&vBpuvGKn+eZ8Dwk8V~;;Zo4R8!Hu@HnL1$6KV&Miq-FCEUysf}r zBKvb97AO+1b6Y_uLUZRQI3qK;~W!~Z~xga+h#kQ>ng7F z79OBqdc&xYS9#Rido|W_Jp&zM=eZdzuPDdmHq#x~6XqQK)3BmJVuf*>2JfV(y01%@ zG#2Q#uQ79(x}{HRvCg<=u|hx#^!y3Ah`w5O&|aReV61UZQw>2NJxb1Uy-Xv`P`+|~ zF@BHRa{kL7{$V-_9^HQXZFmZHLqjrd3Ie?r4HPQ<(=+-N0{vaQB*!4R|_Fep$x2Yhcd%*iO|aDQ%yt-8-6tpK4fKL*8t#Zq5Szvg z+|WQA17}o0@T+TB2xVTGd^Hei7XXRO@e?P|=JuhPW&we@idje9?m^>REfALo+?3rr z$euFJv7DG=5wGt+@rP!Tz!kdQL-HtFqLwzqg8=scDB^HZQps?_>OW+ z#srG{q8NWWv3<$p+`OFpOz`W+!`kVaD^!W5;FMe!?s6c2qHbreZ*|Kjo1pKV$EnR}K0 z=9ZKvD!siCaPq6IvW0t*_5UUBO=C4puKT{H?|yIZd(YCt84icTeHqE3NJ<19nY3jq z5&|=T4cUp~5BVfm5}e5J#{|e{S+Wx+0RqH`5M+U^#I|G!vLr4d8HJ)W+=esLGo#tM zd#3l>ef#c9e!u^zdf)feQ)Ir?!!A_b`mlD9wcbC~kY0 zh||k3@*+x}Cq3SnX#iDwxfgf`(EK|Z6VY;5q3`6;2VCOeOrF9vgB3a(bdY>P8p71N z4V)PUNSz@MEEon~eNd7o!*=^~2Z9EXjqZD0ZB9#^;5sL-jL zkZY8W1Dx=CfKJ81p19dbxpYw+<$bF%dm@oZilu%Cj~Jx;4myN^vkJ4kFNrwz89a%> ziwFO>tS~9uHadHW!IH=4WL;3VHXZNoj<<#N(9(a&h`cuprUE>g=uMf{Y_aYH#tITS+e9)zL z(svp_!tl9h=`4r!yx%f-Q;F7^BA(qi=`ZS*GGOCpx4tg<_Lknao%aKiQ zeFan)4KHcNPr^u5f#6r3V~goS8bvUC#%H&;8C*3=EE-1I{rxTV@|BeJ0o5O>qbP z0s7?I%NPRW3)>OKHCGdO^Yis% zf0wr7Y1@xJ_KxAvcRY+@$2D>o;eYM7zBv4k|Hr>&ChpvDhjzcpV6n^Aah+LFy7<&1 z-(i_}Px|9)K)lL7uX*&T^Ix>K2XwCtj)oB>~0Zrd9nc;A4(m8q*3dX#aupus=- zC%-g&>B~QW5%O@Bo{NV|y`7}lq&^+II^a-->PjxreigD7g)j#feSf(!%bP#``LF&9 zP6>B4!Li|yhZ%Gt&;IC-USe>5G}{NRv7FaIhpQf(EuE)5nUBr^)e`xFH05v0#aWqo zhjJb{c4qj;|Ky(y|NLM5v*D-z=6?>}N1?@Q#N&`JmW1EIKqY$Uu*Cbn`mg_+;V1sur&)DyA96q$yvHE(GFwr(nvQLsTg+{b-hMBTIxUjfCqtE(ZuxrvJU4`3J)%KlK-eANklvxGmrm_-$dJ_&xGCh{1>3 z2EfmQ+7=FpkGQE5E6Zq?e3WH5ycJq6Xl!9XFE9W0XTLmLeBm3z-~L-aJv{c3poElzw`4WR)&sm@^WFQ_Up==sXy>s3?Ju%(u5;riaeB}?m zKK$&@{lf5f{`OA}kG}mu#sCXBIP=1@FL4{d5tens{S1sxo;r){a8l1h8EqpP(OH7d z_A2`f2fE&Bf=Gb}I4n-N47+Z@+b^(%YGucXy_wc}R@X)9onFDRj*8#osu>Xtx zXa3TQGVM?Y+w>>fyR4X|eZ9^~r)?&TrZBh*<2vW#{3M4zzMF|(TWfAQg2vLva_I8d zp6jK268Js#MeYB2cW**mykwPf_3L+L=jf;~GUndMzrq0!|LWI&8*A5k8au2#T)DHs zO+qXWqEVbiI4r@~s15Qa%!2TPdsQTy&G2A_J%r&JLf{6=&1P7-H0_=x2Qb9lp|iby zs|3RpPr4)y3kQb-SOy*NYt_?2XoGS|j150aK5TICk~pUvzVlRUTEDg!+0BqV74HFu zH$6w8J_Dsdz{HlaQYvT_FgA+Lyp<#Il|D(CpGslN^~qlZX|hQ$PyNN<20vh1cy)B* z0bD!1fD%R}6c>d>I$6_Ljus~%`WN|{S%jNld~Nw93UES$#46YYtCXe0`3_$xnz)#> zvP$gu@An!(Df+cn^EYA2L;3g(iamBislQex#F)ryD12f=H230Q+_5}C34%8xEs~dcRe38Oxmll4C7feZ8g8#PI_qT^oet^C9 z3v>Xx+nged^0Rn&kweLDqj0Qdro{ti>2an6Rs9n-ePffw!uN7R_zL> z{nNhe_&s&mj#NXMorE*gwr#pJU^B3?0SS{1Vcw0;X2YRwON%Flb<$6hX4<`HSlMS# zrd@`AfR5OX%Y*+MysLP)HAiJBXKWB=r{nT{6>61B4G^|RJ8@-(OUz<$$Sj2I(y}?5 zQO1cWj_%&#${ah#SvtWTXZAqVrQTn8@)<1jSB57(^uggExIOa7J5dl8X;9; za}b<$%+fvUI)`adZ}J8eLOE5)m7T~-6jSMMkjn%`d>$FIgY{ge;wrs7wH;Cr&%rFe z(9;2n&tydXu+0; zz82LXvi#yQX!+Hvs?c$QmVCU*-chfb(irB-i|n7JJ*;#0_ZL6+{P5EAtmc3}Z{KpM z>^2Ipd+D!dn}z$Q?UT$`Wov_()69xdKKX8UPI?qRlCorhAOY>)kuYBnOCvQIl&#)vIMRMiN3f>~6)L8~U zw};c`IF|-lKn?L>;LE{D*BR_NsPOg&XA;FHGlbwKAF70E6!Z5q*IIr18($yZ`>uDe z^!E&SLsM2MK-HX-Ja_N}2Z6Dqoig8MW@wuwx{>6g`m(&;HKqzS`bmdUc6kgh_L%u4 zui}LAweMHnAq<;8buO;HhsekYuygtKwHwH|W3+wn^7fr=>W`|Vwpjbb4E82%U1Np@ zHD&e&_pp0&fV`X)D`qKA(>7C&cfjYMPMKgGEAMVIh~A~W7WRZ$ z*(r#Me82>bGw7sB{$8Dzy|nx;EFFpbxO$aag;20L#eufMHFd~sOTNVn+E$Z&n;KyR z4tmZ65-}O{wkf_&tiU9sae#+m`21t+S=KP%z?VTLv{Jtp~+s0V*eh%VO4t?qOpUqx%&pU9YS%aLDP_9_<`Z{H%Ff@{hw`4Ef zjW_-Yil?i{)S=FvyN`kJ>%%|(@BVvE^8a{@x9*#FwTf;34hKEgxlbB8Xxq$Ci<9+r zpb1&auOUy+a8!(O(&hah{?PCm1J*Bp`AG~khmi|RhEZmD<=C-P7$n%j!B(Fb0yW0a zPj&r4Jf(v)uGM1nx(GY>u-||7{-pbrU-`A+p$8wzOuqZX#p~k5OEExtu1(H`$snFS z7hGizG4v;T3H4w(#K*hU53_gu`4_GXzx>PpGl#(*$X)UG-G3i`FEV?J0iPM@Ee4zO z^n;j!fTEERIRWll0C6@vhIT1I0c?xm%k)jd@Yz53*6rqLkP7xW!uQbyD zC7sootSjqW*%=2PIN%R`Lj&v6cUltt4U!62`dLoW&?Xg=QcB~i+n+Rs#2AiDgPgP* zTBxgA&_!G!=2HEf^TM^Q-t4f)b{KV}c?_=NmS#BItSGsrwLnzy#oiOlRnbo^1naKU%2Oj78THwSGT4fAh75J1V8I8WA zlArHAS6uhKhxeOe41d6cSkCA`j(I{83x_N5k?KSq~JM+)p zq~Q=2BCJ%{thig4MnD6j%WTZp83e0bW2CeW8@1BVV1$(}kEGN)f{f?9B$UMPcQJK5 zl0r5I6b;WtTTEZe3hh#bD^#8D0UVg-ofJuIy28PD9nHe8r|*ymZw)RX5d?sDrb>q= z?JZ8wLR0auJi1=wE@XOMRWibr9C{{ToOd7rBW3WL@I=X%kn5qpPNp<8;o{ivNFA8Q zhLj_%Q~)bW0{ao9wpGe9C_=tS5dyJZ_3gj23mi9 zv$Uy80($W)4(XN5II-z?kKjmzgs6(4@KNt7gNbX-4cH!ZbyiT7&2l=>nINt+~zbaF;nxJU&lbYw1n~joZ9<`C%h7wL)}Qn@LsY7VBYxwcvvtT*Z4uDi}zwZWs3+HMqJ7s zMI=a}fXkQW11;PG-}$?g7kS0_<~J@wkJI5>X=#~yBr18~R|DUUUqP@;F-lp{mZiCh z3qAD5$x9X>TNi9Ik$IK_T;Yo&tg7&O!&@A7bQoikyyKyS9!8{5=kA(&L^<4w!=fzz zCQG6(zjli@w9TrRCF;0%bCZ5cMbQmw}MRs#@hC{Nhu-bvW zz3i9VWTtnH+bC|>AJ1WQI>`P?;M#wt&mdc8c%vA{NakToD0lFHvf0}0#=TTIX=I{Yl@4fu$%kcHB;rJnz9#j7=H(ke&_Y{MH2RPXA>P-v~;bD1jqQX+>{#E`Z zo#E5QFJXpcDpjgql0}M1;E(pyuX8gb^-Nn!`%0Z#_XS@=;OpG&KAk~7>8T%AiEL3n zx%N;ZuyV*UTS+c6Jpi4js1MVYj3Hf$Vl9FRZNhqzmK%Q7pcjJ%(bm6e)EBGQ6*{&p zUzJscC&2tvTCTz%%6ri%K%+WqcI^@ z<6-FX;6wTU#x1U(1n=yTN2c5E?k>9$i++KV_q|@v!H`H5bt%3G@}^-^(knlD-@C=R z8HbObWeez$;hE=OVR`cz!ges?A^)MZ##RaFz{dVAMjFa)I~A%mDNOqvf25JP+vjFB zdsxKKvCeY)TWzMHI)zwCz?U8Gs!wQ7KGHZX^w|6+7=GySe zWsQO?!N01k?y?LKyjkD}P1JiTt@udqUBZ;OfC3IiBtC_+D^th|T?PWOSgqu= z*;y&-CR8N`0B+VoCjOOAemr~8pMT*w3{Tgf)2-ndj9N|#y!$=x9p3l;OWf}9ZD@y4 zoaVT&+H{Ns>Ut>KH!hbt#<&$S~qYm|gw}|p@S%jf%tuo0=a0uw}@t1NbCyXN> zNv{|WFr2KThwQDY6CiJ?7xTP}+@428CQbc%Z<|JVQhU(hIS zP}xV(S-HjnWAGfa?=}D}$?JEwS)PaGY6WI;P(cgVax1sX{4RxAp;K|jUiNay;f5`m zee_fFoOVy#RV-242vTSKB7_yhbQn=&g(H44QobiR2;q_D6Mh4u2*&bDiiB5s-@RW} zylqf|>J6F9lGgNO693*QRc^qjBoSbh){rIycq&*el0o0WO*V++NnFbvXL;?NTZReu zy`%t9TA1ZXI=%_>S=R^l$s>eofDB6vzFIkxC^XWqMQDI}+%e>yxQF;&bg9HWJl_2a zx-?;6p50A6>Sggda-AL(bzFD--QOaQiS`4k4!vSde)p^;M|b*FUIk-6q#kSHmjp$N z4nzQ;-OESR3`*i%(5!hBlYCLI|^DfA4eU&A;42YdcQ2AL$FlXtc`_jl?jGP6o{dRPlbQYdI?10W$ zkU8QkG9dS$9bIN@>|kxrbV{^t3rO2`u+QEv^q<40jt-B!{ej`>=U%|L$1>|>PSd`A zWtgG!Tw@TRQmu1Yxk{QdB5Nprsxw}cLus-S!I_bHWRD82vmuKNE;LYhz>w*bP1o7$ zJA=YQFu zEcoZRe$6F}D$&Qe>Ss$s0nUNFGeFK_s_t&p+itlx9 z09l~?8WHSt?c5<&KJtJAcwe2FwVg{%4Ilb>IFoU_TFa&XOOSb+4&M9HRa;azR>Av- z_+-#RBI^Yw|JDqsc@-~JzI@ACnkfepIeh;@V5WYvJML ziG~|&Gh(L9!p)qL=het2vb+w0`S?!0)$YU>#U%&} z%XTK8y8P6uoEX$I)3HfgSja#QK7v2DcDOofml<1?M$$80VPNGRL(-7WgSediP$WP9 z%#*{y`+f*saOp2Y8D`SO&n4emoHXt!$PUc;sq%n^TyL2i;8n{@u}9^1Hm3#xDsdWZ zFwC(8a+iM587i-Dv5yYF z^>2QCc=eB;8~&5O@tNTSGhHr)zItnYc!|SpuQFRd!}44QR;k657qD^qq~iGX*|%|? z@xZ&WW?p;zq$-AK^(z0EntZH~7G@p$SkRq877Ru{+KKXFhry!@W?YKDiyTO14%*}` zTb7lMu`T)rb?I+?3h&^S?5ssvG^{4=a(!pR$9$}#S~;W~M?OO6x-|$m@@Xr%*f}^U zr(%!u%QB&SyBFL&z!qq2eQmh*^2?m>aFllrdt~3N+g4n)=pErE6u(fV!2}JG`e(2> zQACjT&TLDNgFx|f^_1->1CW-+E8%LeVPaijEzIDk5ACXp6k`Mjpco}N!_&%n>nbw4 z!4{#QNMidAoir;)36N$Y%Jowr)8{qD<9PO7O!KaU~aX& zeVOw;&^E(kI+Rr5T{ON7mjshprIzhhz@PM31l4^aDx>R zFTQ#yt2E}(D1l}LJd=-w86%xxw<1%HqOXVv)@*^)U; zU$ud8Ws_~q>TQeWwdkq@R#rlj9Sztt7OCfU2z3|H%p?WB_Fu+xm70b{^^a+I6$)ZJ zTOMw*t!#Vd5V$e90{$1-n)09h^-m9f?Z-Y*d+QTZ>b$ib9P+*I(jX{?zft62E*phb z>_aTs`{4WDiPG@bhtGcgi^JEx_3SVY<4j`>+l2vTA(a+H3(>g~ zm%3o%)p5|n{0pQoE7S6OW7+_i_^KF_xZoqBOuB|oDJkYvLf*DgDJy;rOzgUf2L&N~ zc~?Izq}Lfl-eGq8)UidZvtHN3V3>jH;)3_h9;Nd}Koie9+}E+%y3F0B;Lbd(BK%!W zT-OZQMtydmOh*X6sC=xgl0O}f`^u%GGv`^RPnpCvd%_8zE2VR0e-`0OEQ53=a*0mo z2U#w8m(>HeZoEF6ePDk0p(h^a?%R_rE%mS+_!fknSuo#z-KF`c9J&0_YpCvG6?SmG z;lLGtjTm?6WL~H2M_dhrRob%zp5Wjh6}<~DUZlfzxukR8z@^+*xHJ6#MvG0X)=X=F zElzEatIhy645tqb$C=?g1-wIal4|@OQuB>(G3ci}hdBgjmT(oB)E7uPJ6V0V`}tfA z0Zs65`R7dzredykc;S^xb?_%yo;>I>QD%EFK6vAYwHbvU8mQDbXk4LQc9vPfggj)Q zLC|Cb330(y#q2nWJj_#gjdXXD32X(xP<5uOMb}APaw%>woW_^;8{0r zZ}{oeekPSGc~PFTZZaEcLLzFp51#^0y7&or!xA4k3GQh>8Xa1`^&1ex2Qq-igBrX< zuj2|V;|Cw1`p?I5RO?7aAVv#n?YoQ_Vk{mNvz}F!=|h}ZK>o{v2bqC5#G#2RtQONC zPsA4A=HlEPJ?&H*%VfdM!|2f*s-ta&D55L4L z&qqLRYWP2Y<(c8{{rsmmH0<2)dtdw#N)t1xp{q3LEj@({jz0Cb&=@3bcMf!1UTGa3 zWP8o#)GCUchARi^ti)kO!SPdz!`Hw12g5^;K14n)b;dYkpG%wC+F(EA)-?_RoZ}?& zxAW}Q91KJlw&Yd!noe;?^%-t$*k)#bbBlw`?5E*J>sgM{N(CD$p-#uXW zihQ|>F-ybPVV2`A!r#Y_&u~t{^zf^{`!zfI&|@#glwLv$TP3C{?6&tgb%b93MU_g| z>l}m+55z5JDmX3aexG>&}r-toi~KJk) z><`}FW6LA*$APQ4)#@nrGrP({Wt@RSWHC8toKa^PIUa)}$`bm8 zY^%~RKs>huI7o3YFCSVk|Hdm0;#EZmkqTY&Op)-bGB=5&EOItlIU;JVjA-<={!@QG zjM^``0mF9him-Ckjzbo{9JtTJcQdS@vCq=*;lM;=-8OZJd7_oUSy~Nk=3*Yg<~i_% ztQ-b5O@Q%EnAOguOuY*-d=kjMC=2+a4Qo8mu zlw19S(@4=N+$Kc1A<~JXhnet1?kk^Qp6yw55p_8xQ#V-Asaa+Y`R0L-+Z;f->o$e7 zLu*`~K!-rLzzf}O9vy|%36xFU@eZBA)f+dNSVaa+b5;}mn73oRcIEQ$nZNp@!(aZf zA7P?_vJu~M1xS?&gx{L(Eitg~Rg(q^!?`z0A?SV^XRi(|92lPXz&qL3b8h(j?|pgr z_22xR;rg`|lx=436$ApHVcG~4(9Uv|z=BB;3MytQ-*-{s*Vu=q5{{&VfjP01`#z_z zCL={)7?qsBz>C8yR;K&!u(Odnw|Lf zxcbMn-=LE(#mGGlk5V*vFtA0gDr&Ktf0Yv&5T}kP@~$kb3!k8SBUb!Jgfk<%I(;p#wB|W= zCGLhO)EjOoPoVMD1UP(lhr=Y7Sw431ID4+pwC5O8pG-HuTh3 zXVtt*{5msg%M3!@(|3b=R@ayza9N&wuEHoz=a>mRckT@P0lD85{2a_`lylIWUpmel z3PzjsR}#dZy@T(4{O!Yg9)D!``q#fXoIHAPIDh}C;oa|kBm)P>s!|}GwE#Ht_()yj;laA_F|fil5R_YpgjdV|AUig2`UJ9gV6It{auma^6>R_6e#5*M3kP=EZc{gQq(---@{d`LRtzNC4%4DcW>DQ zBC5vm9ln#$B=!$q!sHp~pEw5kDJNxoC%DB=(iTdX84Ig@eD3YABAMQgwBpxx2o43e z(h0lL*dd?*LPt}GYi4mmA*dvNC?r)T6i5cB(tC|MJH@p>XV_P}!!=PyIP`F4hCTEv zS2#rJzTrpz*54fd?%(C`G6vBOrkp|3(Buriv!@R|be>b-A02-4Uw>g>f)8%l7~V&J z_{;zFBg4boJ^u7F&$Gwz1x_-5S1YUZC>bf<>8DZw28XyQG9g(_qakgXZ2>L~{Q<76 z+TFVgUI&M7ee3Dr>8CDm1>gIIpZ)otW>)c&Ty^xDD5joI;l6*`FSI#%^2qSXzxY$b zd*1VKW^?{6+f8-|cd4p-zP+KqLv6j9ac7?Eyf{#9kEOyomA(u*;8LH|voPybvc%`1e&lsh9rjZ;M|c713Pqua?>QxOgiATHrWPs2O?m5b$t2g?h(s z_Dk~%zhvfHo}t`^+28veepRLjN1haipv;$b8e9k?j#X=Y2Xn&`Uij%Zawe)+=`YAW z_zMgP6nX5bDP@fEXAWbduv~RA3tzetQlsrGvu)0t_ravtRQsX{FdJMhNbzW<>LAz= z83d|^Xb7q8A1ou5M<|0^pd`J6A4W?-)4rge&mo=j*9#Qz=y1%u3cTngJ>VPKXjV%x zNXZI-(61#V@5ol^MmqC|OtOB2gTI4q(YAd{BM%94aHm1WDq6q*t*b3q;2OOLKI0c) z#OW}LE|xFw45pCMD=u=8^6FZcK{FY!>V+r&k>Zkta@A^)PH)4(5t!1q%ht@q!fP=+ zLY~|XVy?-SFKA%7BfUsl7*#kFgoctd88+PTuyRP_wtxyNKT03^`(rbb-ttEF&_l1v z)1<(Mc=j(r!*2rttFtAg-s4UGVqW0sl5uByy~jMKxzl&Kl|XbxiFxUu)GK_>mk)l- zm-TtU!Lrj|J1F)l(<}*3{-g^`;y2pGm?ErD2x>u?U33@68m$n(h7QU%;^dF|h*1t+ zn1{FJmnjCw-d2!GqOb7E)lYo*W60O1hG)5&_R&Y)4&2(>=as9`uc2dYKZGCEO>hq2 zGl*|_Mem@z{j3PbP1b2-hFHsAHaKMqbhq)v;6T~+%fY!APh?w*UPdQPn8~ax|pJEyP>U9rM#E>w}HZE`RS?6q*tGBKXpZW2R4?pp#j}OP$TA4)-kRiMm zY(eNP?A{UsdmCJwKQLp2ZCaU@VZ|AZgrGy`xKAF%W1FQQue|a)0}k)=RPA(D0IM)o zBKMvyvNR-1d4Z)+mBDO)i}P5-SYx`x3BR7)t^D5JUCRI>gY79hG~&Z_W?zi&-W6E3 zHE=~xqza5{ zOOr`{#?hIZKYaTjD(%-Mt8jA$)v}AXr!L!BR41+ArZcd|;$u>sehLtOyR#mQpukE7 z!Z0KJ$FY2uBqdP#uUj2-=4oS`Tq2bE7H&Qoa#Vt;N8%dR(}+t6YW)<%X2lmuoOJJT z%}3h0IjRG-#hKy928hF=b9(1u(cq;E_Ysmz1tf#90Vo zIUsdrqWHJUN2Itht|}j$Rz*e27R$VN5@uP%sg>3O@k|=i>C1c3SzaxE%6_*7SDNh* zf&c(O07*naRGKBc)q$suj$BVmS%sR;MxoD(uyv;GeBiy-W`FhCB~I@>!K~ckz(gK1 zY20tmerwKB%fO!E$2lqB!Irx$-8yw*i35{PQMW98!y3Cn+kB1d#cnXzUu8ykgQcFD z+&m@LyJSyt>ac@HKOUNAzM+MA$U|0oql-Aoz4Oq12fAykcfbFA92UgNH?B z-9Wsq=yg@feB@neX_(8ryP_2yq!Ke5#SE4C&7#=5*ZH|uFAYyU{q%4K+CKjhhx;KX z!;935`+^mg%FBGLH0fMFKH{pK`0OlI>I7M0n@Jl@eA_5xwqCF9@BnN1 zl8G;TOvi611|t6Xud~h*r(XFcl=!-ql=s4`(xLFtW<1&3LkhdH?*W5oFwjuBgi(kU z8`IOw{4kra%WP*Ugc@gEmBQ)`W@#OmIIHcwyk67ha?8V<9y~kCQbz{%&ph=E2O=ID zKKju|Sn_-jn!tB6Dx4>Rr>Bu`Z5Rk;He6fg-u4$+sq%xTIINAU zSzmabW$q87WO+)qD_N{@IZ_bNX;gUdPq{5M4uYvXT9zY+kFo6WVg_IDeg8Yc{B>>P ziQ&Z;FL3qj)!|1z@s8ocKftNS&bXqq-@J8|_zdhlL7ka&7-o3(Np7FHeTlvKXTY0# zpy_Wt1$!w6K(c3(1j@+BFi@~>P+p}bz{iyU!elv2Zp4|Jd3bo+`SZh1efrb%>jzV% z-}>gahcoB5hofg6z_7?xItE}GP#9Seu3V#h*15mdD^Jn^4)Lj69w*)tNuGiygAX3z zFa1c8aFaIw#y`IMC+}Az`cYQmXz+1hIL(TkoPQ!7D&EYZ?oHKamsJeKZ-oaO-(ZL- zei{O(90!cKy3kXuwrn@{<%M1bk%2-SaEgv$KPDvhtcsZY-`k2gjh<7mR!m?_p^z&( z8AU-)R%B2&Qw->HO&0uwtpzetpWvx(0!SabRJM>}kMcHg5(?tNpC_ zFEO*HVaP$YD*+iy> z_-km4KlI5e59vs|@w}baxb@`5O^o~K11DJ3b)02o2box1oIOHc$Lu`@+)PMNnXc5D zVmUp)B2!#J$OG{h%wrT@W#GQbgv2V_8t<}ta2>q2om}O5%3I5~IGbi+_&fj6r-o1d z$P>dU^vwllXmAf zR%fE6w80^tC=lXATI2KqL&_3i0S!q|#)2`9=5HsIjQHl2fAcRm8EAl?;db^>6wHTk z1(szHAKz1MVg`STmg_md#dq@+inR27ywoljM3Adkcn7q&YY0;K^+7SfNm=QuVl4~r z`qO!*6IJnoH!45&Ss$V~vNy zj-5d%MM9(34trk@p^!-%2ZZFouhD}S&%Sh83R?q&zriuHMTrvlc2!sm83wL&f7QvUSc6CQw~;o3@doekK~BczFtKxI4$%g{ zjc_J#vXm`pz|+z@E2LwdDCORDA1(o~D>Fs3L0*jKN9XTNEWVy9>+-KfO%ESu_1T*D1t{2M=6Xj4$H&PrRC)mCXQJUe*GGBeV+CBVU{@rB!Q6LvrK zcMs*AVcn?CRM4_N6WG?Fb*XZzUuKfb9_LSQ3qEU=x82xo`=AYpp=3b8Mn=*J*GvTTpkA0 z523RTsVrtOkTc9+9%Pntmsts-QUquSEf%IxbWq|>9Xp$q8uE>&X?s45b$yrHB-}or zapfyt`toq&wWnBK&P>MkDmoA+5;HsE>KLzxTj5%*ogHqX*h4`YSoMN2`{j$Tu?O_5OS%MJT2S&85|Hy56H7M$2iZymuKZk2KQ zZ1(eq7u1shiH^&M^lQqd4Z@wN?F zrf^H-O7R!($*|`DEuC?uJTVqIiQuXQ^ou%W8wkpJ=stxm;sI_h@9lV3d$s)(e^PtV z7u*Bx3EZ>X;ha*6OX`rUXe;94yXSmpjOB%ajeT0RoyofIr6rR|N+`uGe!yQOPhDsz@Bmn0xq@Lg1{C$bf|o&Od$w*w*sy#?`I3hP5pQ9)kN7)5;WB43kKA`6 z$ev!1;+=tY;6nlGp;mMVs?)okQ*PspbPMY{f}h+(iul1nIiY?d&&u^ZANx?=3PosJ z^`0y8@OPz;&TV$VD>x}f?Z-(=eMj~XC$#m~l28|-Bv|F8a^8F#+u0vlCUHJ^>JamD&#*8UWdf5 zG6|=}IY3)>>Age?SsP5T^7^Kl}%Oe|Q%w3pdv95VXM|qgRGU z-u^JR44oc+@fUw__@!U|ryQQg%BbUK;4clKma@v~%=Zjqn=SNu>7wCQTB_q5;p_|f z+iiK)pN7O3l4QBm1v(LMGJcU3k;=S-w|ZVxZI#X(ZPU^<#uwmK@hlJh99uD6>AdA~ zdE#zh$XH_a-ki(!p_gZux$@bY$hMI0l~4A&*TEfX7?aS;DuBlf{aq zdy#02X^1GJVN^~Mb-(NUNf?FYA26JMGN|!3*(bQg(h!*ddO(H0+oiy3G9$md@_{vY z*u^TgMMvv(6?J!|>vbU`l4ggQwHo}Q#CsnjpUmdA|qje5g2(vTV8{i%3IZFh46cWcUIsrQ;;kifKK`@1ew&G#xLPIE?hC9ps=Tp-MGk~++6nGS)N2-U= zhMXFH@<(-k))~td6?7<~g$IYQaq|0kCQ^Rj1MdYaunG@L3KoR+l4Jr+M{E*(a}(%K+3Qv=5h?Q)|Ih9~Gb5Sgh@6me}(S zp|WqzHY-g$tWH-0lJe7E9Ev*qSsKcS!4C9{RUa+s8kkmAmWO2ykUM>v`(m;F&oDUX zWg;?<4C)&lEUInJR%ZM3^lJU;V;*h^sBJr*2Cc%Nk#L1&#O@Vy*>dU}6qEhhJO zS`Jho4dr%r$EC;Qq(Vb{J3NgBE_pR4@6ownR?BrJKR9C@rSyfp-5&m(ztB~_ekyW$K4{-__|M&To# z^&!1e{whGDM}bYjdCbgac%#Z@sAc+hxh&rn4`@(MdZ1JyFCBnJ#)vb-aAl60-=~qs z3o4Pw{y)6%>TsMx=XPmRw^2~2zTpsqsk>{phOKm}#BjTn2(YkZX-o(2sJ3+UgoIb@v!D_AYxem*5}q z#7GD2McQ)a#BhZeGz!n~(3^^T^fUO=PezZzU!@McN$(7#d;d4-cN~Bs?dVVDIDB?z zc;@LV!=+cRVxaTh_Jzoq>)bbgn%f-|oU`04v$|q`!k%QFO$$Y6i|{&%U9Qe!5bMf0 zPd4_H=`~K)_mC{*hyw-N@-}`yc<$)%>%Z|E!xNmJ@y^ z&QrtGA-0TQ)N)n8U2dFk$)_?y8N(Me;KQ>V)dhRCAKMyzvQfjQjjzIWogS68-fTb0 zA7~=o{Ft~sSF186G4S(>P`7iy(Rk6vTF;D1U1pmZ`!)!02H*YL#!H_{JC*;HWnscR z7eA(*Sdtd*;Mi4pS=m$7pRlY@Kvtw(Lz~tN3m)kU^H79*b(9mQzfUP+f7ioePK1&@ zkw|ZmnoJ5zaPCm0sk~@E=-}6~ZJ>v#%-g23&5<}U0Bcav5Q4uaWAAZ>N^T?RZC#Ay zYqM>IiLT^3A8`=Btg4YFc)H5d#*=;$KAQu!u|s1Epw7U1(p7|u6f`QRMVnrdP{6{JEOGIBI&8qHrHBMGbpf5^4^#*kW z5eeW8W;Z@73e{SI*at=ZiT-us(!IQFj_-0WvAOjTq?-bFWY zQcj7be?>DR^JY7i*)5btA7S!X>8<=!D>d(AVCg50Rb;{ACr=GG7=xVPn!Se~ImPv{ zr@%t@t_+T~-8^vm@bJ-(d~EpgS1$xMH3I({$Nm+l(4h_ytn++kSjlK#q)eV)IvV~s zz+r>71J88HN)=ERMR`2^n)tU*PzOKh9@^udxRlQ#YNRn`CK8~t^+@Vrfz@QTi#h9+ za;|Wz%Z(e{DnuvbO!^{5xdn`@9*W%0#_Q;z(%-Jp1?}oDWt0-C;{xL zo`4Zp^7N%%s|?~DI*6M@6&OLrGGC?4Hh0~UTfMjRp$k#%s7&L#dB-4xzi?BSdJ0bZ z+CeGAtOo~Lk;s9WOh;u-$4YtptvXZ4czQe6;ee-u^W2?FcsfO4N=xY>5=04p zsYj8(Lq#n(6Q}ln*{K;<8VI6jAKHMLc!&2$etqRNgeXgJ9c)s3&SPtNBS2jT4-8Lt z_uhATZkPSE0SbNO@!->V))(J(d!%uI1I35kBL{|8p1UwS&a&7g_E{}3a7JZIKDN=o zv28Rm2PXM$kba#d_m*n7nbn@7#=*hr(%#^*p9kz)=#OS@^{rI#55C}^eCG6Y)8JHt7#a3 z(VjIF?qY>jE{J>hA@z^KV_Mp^hJqM?K*|}jC@Anp_=LF9qPHPC>B3F?Y+II7JS3za zQ6e|mS}Sh6E5OwkoVHFn_sp*`yQ_b$o&iVOwFev7eyJMp1vj2`X-h&Rk81xs=Rdim z?YQjkAXn_IaYFgx-0JY|#~z~m;BFVsfV2kov{MzHJ&Z-pbWOk(l0^vbCd5FMhmyZV z1LcDBF1cb^N5&CoW?guLLK$)jmb`Bo@zzPA&=45@#v>v1)!SWrYa!OWP6R8xhF$=~ zK>WUUKAJ)Jg=a31m#Z_}cCtG>c$ArO4strf%Ja|s_@{>-{?HE%cQE*%iL$(q6Mb2Z zLd#?z!@!<{lU{xC1+HL(W(-*F+`7Rn5+@nl9AKY4v)a?^!{tj1RH-*-X*@CC>sn_~ zlA5~3fOVAty|RhbX`FYsx4Xa$mIrOY!wxq1gnp1hdixw1CO!3OZKh<2Wi440gNfx1 z1*DsD#`2?JbMm*cWcmPubNZ`w`nyXPxd(gu2xmxeYBg6ucW zE?#I#xu0qjyU=*Iw@?z4EMhr{=vC< z_)|&vRR;k6K3DO?H_>`r-ynobkbR6iRmKp#3=m{#S>ccL{m9UREPk_$UTRKwiF7JUWJnL7CMg~5fqjN}0^7mP1zP-@qZ@(;!9Jtzd z>xyO*aDiWX3TeqC^+(ig`cKnjfD?TO!vXq2wh`bzM>#BWbp|G^tgSO$@aEV2MxR8I z)?>c1z@|`-==zeNV)UncxrwCHfZyT|;SxzW2@{5W1-wRm+7C&SqKy&dUOzljr$DD2 zdqp(uoU)`ZgGOF&C@#X34*r@ZG=m03-$r{v7MNKzkBUpUbc%dJLx}F$=s?GoNr1pJ z190%4LYVgy{mtScX?+J?9T0~cqCQJLL3?Q}AMlBOT4WA>^1pq2wF4+2PQa>xK9y-2 zbQ#;|mJ_BC|!{FdqIjbBzw~3|lFMj;v!{yhnbKN0_t5PTG8s4Pi0eg-g zy#2&&AhTqYL;k3zwL2Jp&6~PYXEaZ~6JGjOiYR8W+pRS5o(_@7`hqd)dy9Ro6eVBMhRmgN3o& zA8$MxXZ92Fn+l(US<-M2QYzFaP&s{6g;VP_95O{?lHXMPx0rdeK{)W&N}Q!MHhv<^ zkymEjA{OUh`BKL{>w7;`1W zCx$c>CVn>P2x`)c3qf&#FP{E2zYI7`OWex8;zHIx~ zYWXoWDvj{-WBRgaN|(x0T*cWAe4E1&bqYC!P9H?+XCCdpW*JGpijcJfbZL__*?TC9 z01mE-K_30Cx`D3gm`3?Bvqk-=tf}N~dk3TWNDqGV2`tjXSI%DO%3q@J-@<*iY=(J| za!BJl;li`*lWr^TbV!UEHzPR_n!-=s1x)@GqV+59Ne}VJjSqwfHyIK=d`)=X@fViq z(y>wQn;5#L8AL8$xjLMA^buMl?L~NSkU~3?gyFlwSJ1RNPJ`v@HQL-w_SHK>wR-n1 zdx<$n1$u}7X`>4K;wdN%zxWpy^r|f34?TSaxbTf-N9MlFmtT2#c!wkbV*wr&et{Q|DJYA;4B<$-#ot!e<1ewNuQtW@MY<=PpjK(M_*G(G_2g04Fc+p0)08FLPr61J8}s6%N1QzFKiYo;n_JxxcKZ zDm6oU&yv63nA$XE{`ktX_{M?bUK+9Q)+O~XuNlue!$p2c7ovD7e#J}>amidlR3()s z-@VR89xau$%z#7sG+Zi<^i!^oA9Anr-u5=j92YQ>u-)YRSq2&Km?fd+hsRIP43}T} z*6{qd*;fv%^JfnZw>X{s0E6<)ZQ@et^T^k!z2jWhx-i^&<%Qt@tG3)*e+UJ72^w0) zyX?JO^$vS6v(Bb3MXYAs ziIvugs7p_I=h#21?Q>G$miImfB-ghBDv)tIT#dhsKkPuU+T- z8g8)I<^2>_OdjE2zqPwt!>g}c#E5Zvxc|Od8RiV5uxZ%oYZuv*d60HF!xjVY7oX#d z0#8@=n#e_HvWInD9M>7pI}7c?h;3Fvon&Rh)8BkLS5Xp>Eq0!i?TONgw#($3Yu{Lb zw+K&cZrz6NDG{Y2f9fKl(S`_Je77!npg#PTxqR*I%Q$jI{pJx5Q~Q-)AE8s8!<_mP zrx+{s@3e8+7J5o10a!(4D{+)>T|2{t$it~4Q1-~_dbgbm*01_){``cG;Vt7ksi2Ir zUhR|IYG!!h8UWDOwB>qP%rp84zrj42D97cy7TF(y4N9@}_dRJUj;VDupdf$SFp=d~ z;hK2cl_yD8GCp^+gOkQlS3TKZn`UjB^Hx}GDZl476st%O&`Mm(@Cbh4N6U$P6fyH- z@YDPF$ZNv-Y9L{|f@gC>Ibyl(=aendR=PEsS-zA_J*4)*JyqNc-zqL3T5H*x!Z9d*iMuEV2VW4KqQKnL4g#zz{N_<&Ki1`PL?!eIfv=U@QEM(=TY9%M4!Y?S^wz)b_kBNZM$8?GIb$|cVT6<9eP zg&m8H$EA<%W7}f308t%AwZW=Pc<=O{vwJ{P&bn0BS+H7GgEz1gFe<|J1{0%Xs93od zYRdt-0)jw0feZqgg0H_bmN{jXhL-(93TXJ>0d&DE!DEBkbqPz$$3mwQAb%uYHBz2z ztbS~4V^_G@G20oa?9t6es9LBDMl!H)_7K5MT+10&FQymE~;H7ku zq_fj=K&9bC@P1roW&G?BYdrOrtmcO7?m&eEqw@gZ@pG(@3c=jQy-fhYQ9hzLnM1)4e)ib|OvNDH!P{byUS*0; z;`1wT{iUOIQynRZgPJ^0eBgW9s7Uf0T9GF83WfBnWsJ27#etIT33O6+A1rqb3cwv@ z$Qhde3(P8kGp=q!615e#G$F^P9KaGsqoad+Uv_x$aYLT6vH9Q1AUK`$<15bu@#r9+ z_Fqb0e4=26pTVt{Pjcx3*7Ezz$M)gxK3T%Ma4JS#Mqj1q6%WOe#J(k;YMj9-D_&^N z%CFa7z6|eTD1?6YC=Q-Xvv}b4@bU{^A3nE!h4wXF^2m&@XYd*a7y{ALg3I8^f~ORU)+=u(5rM!Jzrg zqxj_@N$P3w@bqvjGt)|%x)M^d+P_qr&uB6Il6)$E>1I$Ip;p?S{E~hM;%XR>=DOlX zpo0HAGp4TAP^c}kM}CI=_V$&|mfyK^lQe7t*jO5Fa**5Z&H`6UKF+|N*%fBq=h>F9 zup|#s#|+@-oT2AnJ_lRgHNS_|a-KXNd-yEp5}X`%nY}Gub9E4gQTWakL7rH>qt%r6 zRkkpkJ9`EtnS=E>li=vlV;tsrQ?W)Fh)^gZZY4b9AYVZ=pSoI$MF@EJ&dA9VFQ`OXZ(LV!wCJl1H6oRxS4>T-jh$U{?z5^)Y z_e2dB%jT*q^G$95big6sMmK0}C$b^wEr;PHTQqW%+#?WYxh?0UtF~r={Nz8+i8c|r z;#ErXlb+%i-Gcrmx{UD&vt26ZV+6N-1r94xF!EX+Z+wua-G(4PI;h{?hIc$%kG7oy z^pb2`&Qbor7qxGCw{Jf~1Wy-$ARcWQ+sSn()xC=+w##e*HZ%86GjMeY=JW zvPzrUL#B&F8PUT>Nk0{=T=6^lRl1z(2YFPCy_?n zZQG?2RM~B_8KjcGY4ZiFz^|Ml*_36y;cYl7nTrGo98C9)k zN`pS@RtfpI2HnDz2IlQ-thh<%YGsc9Y^a=gUbu`NsCu!u#^%_Y_w<3QcxXnq) z5hE|}kp#Bc)PZ~<7-^UP;BJeGK~~}>9+A+&l{s7FlRiZwrEQcberBM*lUnMI8(eee z;9mNr=aCkY3Vs;&9D{KU9$~h3)1E$c8Uyj+;REk^aCqW<4>72x@1)=Gyco|DDe1)) ztLUrNZOK&-0O)t?M1ah`$J|?NU~dIXR05CvEx+x>hHZ!pY{M%NpYFS6$kMo4O~T-C zKl^uVv^EHZBLg9nkST=oI)i@)C~B+jL6qGU1U60^jV>JpK?+|H%8By|HzbW>PqY*c zF17dinh0s$Bal&6;-{jeLP{Pg7p^*p03o&bDEKzBYM|pFRB_#47=G82 z4`ab&3Us4J>6Q=Y;967%cp@Q?uMshB#n8Qr$S)lj36$0OnCchP<;`=OYj4x z_^4Km9FJgFuN_7gmc-AW+G+e;ne!&>#t{d@nerZ1`PLmQ4dHVlh$evJ9&x&TsvXB=}4!z66<){ zgSbWM*=7YmW;$q#62r2ZkWUmsVMwWj=_f99AK;~GPHEv0tiKz#hp+wNSB7;Cs`0wH zJ9aK)ZYS53D^u=sJ-_CeJc6lIY5W$1M5kz8am2@dsuVBu@}d)M-fO+$EU+&4)}yV@ z^nQewAj_%~;Dj^$P2I?UfBeMN%Vg%k&jvHZ&4XXPD~<9<7aYWck21+C{YK8X`tw_L zNc(~23mCvu5=%yqS!*YF7v*FCy_3NR8V}}OW$(V3Y4-Xd+P=mooo95|27HqrQj*Ao z!qWgD8Qu+UutUm_fcnaJQK7;*J(bB(I4D%)bBk~GmMN=F8hqbXP_5BUJ05A59GbPe zI$XKPl3}bF9-x&o7wiW#>>y`6_hlLU9he_l@_;Ru)=v*_d&eWgkrRu<<;%~L-zulZ zFL09mp(sUnxfW96NoHo~i&U;uemn@u}><(v6v+tk!*Py%(?3I<<;T2o(EN642x z>6n5h_Qs>ZWa`dZ>rUP({*u2-pj3O5tMmdCuG+tRHj0m*fBGd(;)S#_S^Q0D3IO9Z zp_a+4nZeXh(oDajJ_eZZ3k4^v0R@Cm%88e6{Z|}}+g)MU@$SC;SK0(tV02$m?(oVl z!O%LqP8#KAoB?@nVR-hm=GmW(JK0VMNV*=b>`op5>euNOU+jQw-u$I+AYvVQCLIH& z;);i{%{b4#DU;Nz_!!E+ZQOyT@p9!IZNva)l^u{z;_0(Eno(gQXa`c&{!J5@3c|{c zsK|cfw{*fVP3c+m!-5N*eBsm=qJQa0Nd1_;y?0o?;yO-&&wKwRn@a0<{TtZ)l5`X| z{kjQogvElpaM_=_f5mNaAmp@BWN% ziyxlW4}s<_)E@4yvcTVjf}?WP`mK7Y{;Dt;<6>BF6h5x&v%Os6T=D{5GuKx3X^flV zZg~Ehzt7^(UFz2NC_si)U6(NqZ|P@YKxA*%Er@CY{2{A!()>t0wY=r|3QM?ydOmr^ zyRt6Yl3;|(D2?(S|0;*!!t&R&HON+WhF9^_&$MNTkp`AcLkH))pwIMGKpG+E9c;I@ zq<)n%N{FwQALWwcCgpVwEv7%nst7=8KrtWbuf$fm5^GV#N7l z4CZI(3ua~y5#O^%l%oQ-9F|-B{v^)$mG(QQGR~hbH_?Oq`9kc^9-CGf)SdNilW)U8 z-fLO5%BKvtlYMF9%7gV}7vhz$pLTZHX((Kl)AF3orT~vRgmfA(r~EIYD&QRym!(Xr z7FZCb0^}^#H19dkDrpLSgj5Dyz_8WhttBi*1@pt@+ppv^@<}=Ct>XE--+{M@_=sN@ zLV_)!DC}zBm9D5(!lyDEtyD1Y4&3xYRYEizdk~%p^F8qsF5FS-QPjkRCiez)JPSrk z$B#nd4UzFlj^Yx>TV!9AIbPsUQ234jE8$p4h(9Vu#fk@>((KLhD}mR_UqB{`P&6#M zwC99&{0htD3mCDr)kl^GPnzt1T9UTNh7S@ zW%hhWIFQZ(rLOz+bn$%Cua-d%6NZ05w`#8QPmj`5gf=Zd!@55O>QRGluM4AQhS9i* ztcOwaRcXxEPdeQR{|X()8D&=VD1^hfiPL$`m*P_%TArwndL~}~DsZIQ?@i32h4G|i z%HVT8@FrZ9`^7^y{P~Sh!3aGMgtv##jT~W>z6`n2YlRthmjQQU$&S~qnxBdIb#JTky|aF9bK-DiHAw&h^{+_`hCJUL1p7l$kC zyR;lGe|7nULOhKbYj;%+Ut{ooW4OY$o9ow?hohW}af?}Vw`@4mdW!=p-MY5T z=kSq*;h~2fBy5U2R)BRE;{k>xX53ws;6Y}y+(EswvNb&W{4;EUIx@We`Z6q&Qi2@rsgc+s1|F5TYyU`t32R<7dQ2tt4rSF_<@%^DuU2$3nPF%esXL1;}?1+o^>&%AtCuU zt2fXapS07KK5-i2BX~k<_!Q2Cm(WtrtWhd|8FYlO7 z0vb&5(XaBE^dt>+Fy=k!KyAU7=GXD90gwLH<$f1v4L6^~Cwal=9gZmy2Jq;TW+H7V zi*bDJc^FqDI-JS(Jo6=P<&0Hy5k|m{!VL?k`WmGfr|&fFWvxM*ZL#nxtc_nZ5&kG| zUep6RuIAOTO1}NQn(81?$pUuQn@RL_qD0HF+isMd;CaVtr| zOuo?AGWAs_9cBQJzJ%T3h{>em4SHH+^KxsQvRm0dGtUh!7>Mmp2+f3y-JR(*l+jAE z!c*gkR~fppW}fR=U5yt0MDNo0;bDDF+SGOr#yiMVjRc;5=B+9*ya<)D*eAJqsU`=& zhj^avu*5;k2j};OL!9N~iXLa{UCpPKF#hluSM|`}zPsOlUz+_?`|e==*~j`m9@sPh2MtZvXtC~7#R=K6CR=MY=MJ$T8Z%zw{_04h5ow9 z=ZaT?MPmSovK-4nlP617r#yyb-bvq#1`cp|Orvw=L@V>ii372#sU}s+ol<@$J}d+) zN^tIJMX%8)Q1ut2xd^fWZQco+{KDUkxyCYY7D-GyZY}%`cy|9DQ16q_64HZ3FE~ub zD5NZl^zJeGZv=9pl)yEH-J+esD2d@F_qUb4-aEYg`T1tq%rkt@qUAl>%4Gb48qjb0 zMRj&1f>uCS+gi&ZN};bBkPcgcP&ZCqou#MFV6 zDDZVtiN-Tef}UZy`E3T}t_E=Cu+A{ZEiX_+zbTfiuHE74JeOfIGk%CY@AA9~+a}A{ z)AqO?X@NuRxHu>$$6FK+-+S?e%bcIEJlwwNYK;T59|q~1+`q%}`n#NivBE%nm+PHw z-CCvXdHO!r8?h|kK41priwn*flyf>V_sl)@^ySd}ko)MFby-`btjzo$K6)Jd*SPPV zeZTmmluZtIEQOdQoSQ2#Kx7b;I-$<#FS~fHy{=-e>-C~cN1jCHfKJ;A z(&=yP;_DrOCZx9PbmQe; z0!VLv#iDf-)0C{vZv|49EnbUTGB$zxUsunw#H7upS8B?)fUuQ>L2{Wp;DuQ1=L9=pFqFwCA3D(F3SyarD9=Uwh{S-0sb zewC}JGU1mzttXeljCrb>8rz}3w-tGu9}r!}-JS3Qmn{4Rq{#MQekn75-Ss*$UGQ#o z-d7{o7P9RQoku6X8D{;tHCKKyowL<@$bDr)!7O;DN&8B@7p;oU(!;f@A&Sv_8hv*h z6OOO6*016d6Pc*9Xd1Wrs;}Z#@C&Idr}b+(BytAl@IR9|n{1uhSm#Pd`naW8?vvLj zz_`kR{4`rnX3)WAxUzEw+UBe-@OLZgH2Kak+2c7XsekUm9uLt%re|NH_%m7PGA)R3ngu>$#L4-eE=?Tb64%;s%x-w2jhFgj8$%!bmy*Y7lTavf<)W2f{EI zX-o3Ws5)fe(RdsXxYx@L#MzW>@+d1k5sjNNRg>+-ix7xH09rcH8y7uZ<1YgzTr2m4 z505Pl83b(0DEaJAkz~np8Ctr;)`CcIN-LPskGl8#&iAt2e)u9*@{;!&$HRw>rd{D0qb+GmGFWOEzk z@tqR4G^2KEx%N5By3gZ{?*=Ec?~r3)Km~ryvR-+Zz_|mKlKr{=P8t9vvFWJ!+jH-O zc74z*0AZ%4s{HD3HQtgperRP??1Gj$$f%{I^(T*f6A_&*;2a2Obn-oCmcW;BD)~I9 z5ZhMfxhipi`?{~P*M52VCeQMjdv%$m#^CHMNL{N{*E*T*_VVj#D;m@sWZPdjvl0-d2HTaL(!c2RMk#zHM>A<@G?%$;R}v!1fg9T@L-);qbwW zudNJsI3LL#Z+-nnXuP_{Qhw6zFg@f-22cKQ7RR(I)6Tw1J@MuEOP*2iESP@$m7}bw zpBhm0^Fkux_0NAx103Z=y|v^*qtg87U#>xyj=`nsJP}5T$v-l)rIV%sz;9??FfE7Y z10*nX?|7S&3C6kloRj676igVwy}lY2r0Fn--)4o4BWZ+|Z1{~E$#wA*H`DrD`C3xX zQApwu*j9c45I^1l%)6ODSL?AL2#pVVivyR=Z6ln`&om8o`BT54YeA@>7LSN&F{X(l z|Nh9Y{8zoZF9o*RZiUUZ{>8AAQC&>@gsQPem~D&C$Ot2i(vE~-3n88j8Q04Z>Jb)J zV|LRTEjl;)@DhE9fSQ!)@(nCnS%l@scn+*|@~+{1uethWA&KTnnC+pQr2w}W4Zu(I zNSEAs4qXDj*Fd7@t5P;R^-1CiuTq+2J(*{3Bf=lWZDsIK#8gOvph^f*1J$TQf+eh% zN4SNndFXn52)gAiENR|eJ1&v)gpC4B4j!Q=bkLck(n*UkPo~m&&oG#%=4BD&(a0B# zZE<7#e6`wpJ(+dYT}n|PlV<#7{)va|mn*XToWZ&}yniC7OcjFpPR)WNG?TwlmxSe9 zfCe&U7id!W&~wmFo^qQ>9_!1(x4O}L(v6zFo=Id`;cg5K;<|@X)!V?j{H(E$hAZQ# z-y`cW2s@jupTC~hvw;3}c;Nsy<9J4avRi|;V;%b(Ka|r0V=W_{?kod-&dEd0kSi+y zq>-1_F~=XoEW#`>78vNy0n`3*4rB2&hUzj#5TVJ`$@1-|&Hj)-`I~h1^XJojUk~i9 z604>fW8-Cf9Mr?2#ngSTj0}#oTc(2l_=4$pv9Z|@brIAy8pE0C??%274mL6y0D=Dc zm-H|>8%dGij_@H=3U#kn>Jxt z7BLJsI1vv&>HKVyc7k}=e(rFnlBdP4FqkpiG!8y2sqJd%AlD?(wqCjP^6-`a_y1w3 z@atJ3yqfFiN1LK)8zp9eTYZM-M+4QbVk?-^a7;@hM50QYYLgl$B9y+(c{&xq;cfH<-6P;(7 z^_b%DJq^#wE|*xZb5))&GkYiy;O#Oa;y~DIqg)MUnKZCDAhd0`7u3Ok`L8p(uW~GI z8q+j#*{-@vd3^y!X8ReWPtysE$AQ3%S+Xq$VMjbivP25o*<-351 zQev{w^D3zz4r*&CVty@8;#R*RFN;;lfEqj!$7o^;j38|kz(wp(UFW5 zf1b>T z4H4?A#<#7<-!NyR@$4}Dl_vfcG%3ncy%Y|GNMIy1ayNj@9w)A*;S-*ahRv@7B8?zZ zZ^{jE0z}KE@DoIEHW!&6TqE~eIulqBKD9!D=LSLOJ3Z{%i#(2v--7ui2;NAS@>frbwi%;&>Sni7CAU|Vc`f9K!@ow=ufhzUTmaKwF4gRafbg%T&Kxo znm;Lw$+Z9fJb&L0?5o;(McD{tW1T{WXWnI`9GDm3qZ&axEpAwpM#2ZCj^(m3Uxbv+ ziT7O;D}wp7+x+{CIiRN3;tx- zIL9&c5~_y$f9;)Fb0tY~ol%9}duF(aqD(K8ME(DNL77Z%q8VQ#aY)fjM$NA2;q+eB zI^Q|&k&$`t1um*k-G%B1ATuL8e2*o=bGyK@N7BY;!`(EPbHWdXe!Qp z9+Zc*92M(akj5#U+k5ZvNBX{EgnX{h3Z` z8g;rG_fkI<_L<&8{#+k&`-TAH#V>WD;0~e2lKMJ&`jr)p89&A^S-iK)oqq1Tf57k2 zi;fRc-s;4{&!v2-ce4KZfB*dEzx?gr>iy(j-~9Slzq3{AJK@1y zqcaKH&e05U6OHlg3ju`?TJo}yR%cPDzxEJ$lKtl#SjH5M{?(5)Svz<}9t%Qfz4*g- z+T7QrJMX6Rb>~0mf*9`=az6P+Ux)YOnv%<+2%Q)Y2;sby41x$exYLcEd;woSe4leKBr!;9F1Y`(#Po&5aMGd?mU`rMh!MGR>D zp0sM<3C2E(j|g20Z?_}Ws$@fFe6Le`d;zWUTlqkMPv67`l;X^v*38qhGzi!KeXb_MW_VJ zjL%pXb*iseU+JKEW2hmzTk#zFTKCvsW$RT7*NYh!%1P*qEXG48^o9nE?%xdU{s39y zQP+Ak% zcf|~T^F@PROT!z1u<_ifjAbKM$+fKyijj8>!L)qo^|SzLE5>3fl^aaN&-maZ117ez zk<#9lH1gn(2zDJ)aO6)%;!XnkwiR4r46i$w|HRjE1@!bo(SSpL=cnixLn01+^JD-< z10MQ}a3PnJzEA(B56eD2>??WXZHxODmiS zKh?VKC%S?9v25k0t0a4_7v1Cwi{9D#g%_$x7llN9FeeuVqB^h6|J1tVCo zCA2`h){z>aZgc=h*2hy#%4hd*s^sicZn*RtIx%`jnl%6zT5!?ld^*Sf0_F+o%#{2Q zf%1%Vp6?|nls@SU1o@v?5M?U=9jr?$yB_{+8uA9I6yZ?Uk-~Q|0-uyxD2LDla_J5}@dea7+l=zuSPAXg!^W*yp zBDRzJu;wJQ`8qjzu6<<8t@ecQ2(YVZJJBf5T*TOggSi~~%H5pruHA_~@GWTrrF9s9 za~bhyiLGmwT~U4K9BIP_egn=N%?6*ik5kgN?J!9UgnhE@|llhK?jqr3ghbr!Z zQ^$IZhdEg?`Hmuif#wIF2L!bw)9buK(1KhYdGwur&C_OR&2pIbBcwX&@&OV1kxY!@FHkq1XB$wwo_`racMQ{4M4>g8I~NSulpLb#_q3g>OxX9YBF{bU-3ibms~ zz=)JJqWoTE_fegZ`&-_pwM|Q|7&cIYg7}C{WIn|OE&M}C$U08w;LaU+vX=Ow4}e- zFBVHMn|{JveQ>0(yR~ z^kaQ2_9vhIiEiHfM9T3LC$DnSf6|9+lKtY`YwT?BL=V$PVLb7CGuai`(@yT!bA!=U zs}VgA)j@T)&=VeyF{;)lNp)BcAh5ZTrhfIFt{kO1Xc488S2}+NK&B_A)C?f5I%>R# zALZPk;az<%*=p2%q<0bNOa$y)LFVU>c*Kjz?1k>yXo(~qde2h$8DuQnG$;syG{U$T zfMU;Bz#vR%n{ZqlyY9veR@GG8;f9dE6Lwrxs_q@X&4UjBJREPLLOC6d} z&+e2D(6b4()qq7Ul(N{$0c~E&TgL2>vm7r1n_JsGm&vmoQ=gcClW&^#!yaE=62eTQ zt|7*=eR~Q@Cl*OgbZpzrWFib4Ip8%`GH{bTDPpN%G>oGdJ2i4NPUw@r|Lk|V8~^#u zU;fo!`PGv@>T%v*{py!D|E#Zn|J#4}?{EI>&;R`9XZo7hDX z_h+R-^QAr7(5es|N(a4ko-1&c(M zFx9&Rwv^oHTGq#BjATHdAq3g|G`M!Xca~_VD{rHP9 zha2xU?{Qlh6YW;KUZMiw#hXs=$QC2m?1f46pO8+e!7ln9h7u z3I35L@A*PcbnE)|N069jrIY#z@hTVV(5o-B6eHt{?_?nAcwhJGqziCe6396TR z$_hJ3ebMQeKBh_=XJ$vBql^^*T$rrldWt%nccUX zJMGU!l4rbAmBQt5G0 z^P?A#@ABhtf0JB(B?5$p;tfWmwcF~mEc3ir_1Qi_?qZcX3fOoCk*J1KmOq6OTm!A zdn^339Sb*stOpkYtdAxQ2FClk~Ao^<+84zz4Brk?Dk( zJD8UiWqA6W@m1075}yprESQaSnK6CLdX;=IPyI2|7k?f0ZBY7y+A1`eVYFLUaDoaV z{hFV(`h|XO&cE5MFKYi@9}D}JU;Ij6!~XfrztLB*|NJlh^5&DD=%>6CwEu~Iv(#U> z*M&9S`(-S!p$p%n-~)W0=<)mab%Nmw{QT_7-~avJ-Tc!({i7bg|7ZO+`{(+y>NEY+ z)^GI~{%;l3>vvW~{GIe*5k}{7KeBPrQ5NkI{%N0g1(vmaKGIJ|<;XR}b;ExWlM756 z-rQH3DDAT0H2m`Mp}1|Y=+McGIa!isUdOp17>(K3&23LhzX@mXwp@7h9vs&-?(EM( z>MFPxS1O_`TyXdc}IWy-)`95j#mLus~Qt4;ulj_~6@?Z92U$esCP*QRgufIahk_qUDr zoJ+Gnp}T{6|F(?C!BA9)u1)8%eAo7KPA0DvU+A@l(=8p}O@t=DZy)M0F2xcWdtXYx zlTBwQ|7w!mDELbU{lVpDz$_D&&~CM{{__AvPh2KZ?%yioxA11{YkkSxPxl#nDN1Rt zx17u7=pxoi>>4lnnHN>1uSE`AB%@b!KoRl|@_e+l5E~EH`gguwc_(OSu_aGsWE>0>%d#}% z`evCH;~(m-GHYkn9O#KH94V7RAD=m|dS58$Bla~e2%_a;59=Uq{*90J(zdGiFPUgQ z$vQ^>;KGls8Z#KB^4yNYPbj21)-}AZpJs|~S;u!s>j~1)mmX=&T zV9L{x1oY_ZpTyHzj0-&k{M^8yue(m`GHy)9UScX;z)&pn9DL#Ocs+9nPsC96t6kVE zUY~yQsb16kQ@yYMGd+>1UrxFGh|wUQbCH1g1AT`fG3QbDZ<6<;Dms|`$OHS~hbcoN zGVQ9v(7Bo9xge=d<{(*}jsfE}ql9C-y-&a6;%rPdhSp>lBXbOTAql7^?;)Y$r8a?)(~e=j-6?_DwGZ zf=}y&89F#uys3%a(!F6EDe7n)rm}G`Q!vH_X|r3`YxN8qSA01IbGM$p&lgm=qx9vM zpDO_W&CPrN^z)mKJgNWe=3@o;A1QGEgh%W7=$BrPu{e!IPKsZCu8-z@_FH|NOJCGi z5KjRA%m4c?e$oXUpKFZ#@?UjI%68P@5A6rw^reu(A~n z0Cl3?iwI@7NT;1`rqX3&?O2$n`GTXfc>5)HGpa2l(_+QW_4x86odrtR1^5Yl0VbW( zo~@l^Pc-z2bLj|8nf@Yd?Kq6_Tje94Q4b0DCO%@t7qmpbycCMl`5i}RV!qw4dVFF9|ckKLpaqBuA5odN4c zop|_;AQF*BlhMgSCm%zj7j1Ogub5U>Z-FjFhVP>!(QmTLm!1Nyx4e>)9Xg5;r<&oIxi*DR;A5RD?T)T z0V#9OHt^_;aOm9b%22|K4n|9V^EIAoS!Z^h3Yc@y7Vo!Dx*VQCf)r%^=pD3Hr1Q@v3MPC5he4%L{TRt`_=)_k3MCS{E*2e;j9<#WR6dmye zwz3ZCwr&2*SFTh10Ukz%K7ORl8W#!VF)KL2r>xDvbJt4_oUntwN_+#I19Hj9hfig% z>N?pT5%B~w-!>vxM;8*lfxn-mBv415HtIc}D2rV{@Fi`)&*R0{a6rBu^XFSil8;N_ z#V^Br^2twCr&proS5bSzbL1^Txi^zy+neG2=D4oF-rX7p&kg9VCx|)@lN3EneaTmm z_+Xwotxo`BvUc~^{ zhX{OVuGHnOr2=|nGT0R;`Oc#-7?=z)E(9=WP~T4yFz`V2l}7=OsdTpuR8wxWDQ}R< zUVI~8i0nHV)CD1j6$B0J;|ZWEM593-!U0Q$!LOVbs%e@`9%tAeC`WN8Rs}DzkVrD~ z(i&J0Uy#I~9{;E4~zx~~>Z=U}`KbNA%@;Qm*cTnr3BOSigop*j7@9S^AO24LW zYvVC6bpGm#FBJ5D?qJ`qv*^TotE{3^DxTM~wM$Uj{H=dfK&`P*ke;?u$Ka_lVut$Q8;2uyX=9OuPW`kK zw37&7?vrW-V4ITYExnnms@tZgeDj32aU;;!3lo?#)2#)LoHmRBe6ElMP|TW8+xm1oNru-g@Fedv95r!PIV|K zJT_p`qm#>x&(ZdSl=f@gvkpXOC^F{BnXl*V@U&m#Z0f*vJL(7k7&-uVtz>cj^<%1B zAorBSxiDkLcYrjebNAoUyzJ|{^;w7`OKl@O9+`!8+D3trqN?_=1m2y{Z};wP<$a# z(HHWiYwL&xsLs~dO(#&2ZNsl6uiO1t zpZX#}(b`vnXIw;o2StN-_}LTU)$?|2l3vzRhr;JhYuYFJk+(ebg&sUlWYH^L5Pj9R zJ=Pm@l%heM--OpNc(K95cY@8=)uKteZ`6Tvks>xkW_Y1%@tyQAUxGxfyAgt~u+!%X zUrgA1j9R%MC`9G4gEeykQni`*lehgKdqAddyGVPPCz?kW>sEY_%j z`iuA0N4#VM^~3){vknDwy?hjzmR|l=%p_WC5MKJxrZoAvh6hIHqzmcjfvw*R=KT+K zEDd|6V-Lb-T-_xIU?8ibYb5xJ(+hoBnEv`g@5b{JBuvu&&3aB68bw|#(%B`$fsX9Iy}yn0k42aym&9?_Cx(_m>$9Bw}Ri3 zPD0XP`p)ksb3Woq7!rE`g`R;Rdc!@!qnEM_MlUMGV@!0Qn*@E8l|7uS!b>)5@G>DF z7aBfF#)ps`EHUXZ@Zmerm>qc}=# z`IhJPku7v(p~RM;Te&*v14&;nV(q{-ciAu}K8odc;snG8mZ>}^7%xJtUnWdX+)Qqj z>_2=dJNrt$Yqg`N^h6JO}3&UJ*|^=vXLhO_#oaldME!YeF@xUE_A_9v@B{qkski z$h%@$bV*UwLxVr@m0W@O_D$OzJ83I?8D0IG#E|1d=?AW5Xg)QE%BPW^X5zkFbY6U%Wj;ghhWue;kuXyhHlz8|dOM8Rkd0^CjOJ-@rrcgAYy4DL4&L-Be9hJxt@Wf?D(!6WTHI)Ayi;ceB@KW-geA#arWKdVKkO}WmE<&)<--2K2yO*So!~v#L zCA!%L=v77r=JAtx^v%dtn@WHBa^#Uu9k9N+h05^o1r61=ZXDfa);&0uRAutU-O;4) z`21FVHJWFh%p3@>N>*IDYnWwT#)!DE=ik;xP#Y;tg`&P>z2P%5$y4mU=sq`%8I&=) zcE(egWLUD^L*Hr618W{Qj;&!;5xwJ^y_&(TX(MzSv3TL5Y-w|B>@g!m_g{E~5Bo_= zb6UI21Bx+^Ew@#!-0XpGR7fDn$&9;-ED*j>!13i*pSxoQE68N+0U_LU#;V zq;PTu&ZEM7*_dD=lMC+#YH{I5tAwHx3Mb`0F+AK@o-~+L;LBu5VlmT!4-?z-TfNK1 z=vDGWSd$!j=-=a>#VoG}Fv&8hqc^s}nhBQ4mV__B%>q#$Ao0Z5LpQdKNluf1Cqm(5 z(HD6zg`4#@*V+l#fwH@M)+=Bd-&n$Fx<0lYt;Ni8K!SiolVYX7!2w9`>0H2BWRmD4uY!ajBFOnG(JMdqzzJZpr0eNR2)1+ zgfPqZRbk=t*Svh<_JqI5Llx{o59GQf#GkRjSi^7BJIGNV<0SrpKZYs22)1Yw{i!vq z6T12_F)o6cFKreXZZl&ES5XOkNnCtDx8}#IIBg&E0=kf5i%!qjAXROhb;kc&|0v}2 zTfa^tOnl)@bR4BO^d$NWiGF2UOUG6sixi`17oBsmj1JU<&T5T5xm{SJT_Rt?L3W#R zgj<3d<(Y7lXx)tS&;&<*rJpLeaWDoR{YjOmk4^Dsc;HX)g(OV;og*LK0z`>q5A+V4 zxFnUepf#@Psf^AD1_WQm5gRs=_*Mhsgyaj8J@!;a&j{DWAnEs|=6S|3=z=ez$IwTlAkaq{7oDs(GL#|z+;=wOFZ5&4Pf$TXo3RG( z%)97;N^B(Ki+4W_LmBz#M}O~m$2tg~BlC9Vh>SUC(jV#f%^4ZVGe2c)rku89+~|ok z%|Rkpu%h3<(6Q$nQL41n|73!^JwjOA{I?Dqr#uSuO(bd&;D5 zbit6tCG^Ol&7SLGy)VW_HRE|#eP;tC2e^G<^XOcH*^lxqdbwY#t?{E@8`2}B?IY}Q z9%BwE!3X}AZW<@ni*~cUX+st52gc_6zS)2R`-FaBzsaC25?~6qnLws|nJ|vguXw`3 zBBI9!8XNcy8MI609<`JD1ayTg68hU_tL<(a^K0GusG%-@MVpe1V}3yTc9(UaNZEO}UxEVNshVMQo&%%X;hrgz$ zu!6e>;PisH2Lva19;@&2mtPSa=OoV&nx2TrM{aN!wFEJ=GICk`uoxofgr7H%ls7N& zI}RyuNI9u+LPe(Nc_gv|dn0HEEt59^27x;Ro0A%H;o=jIjx2ut6oT?uv_ywYkb;R3 zck-nZEED+l<{* z^RfNUkv70i^mBWtOrp+HVwB3svlfCguai8&(O>OgIjv0bLBFnt7ChDtR=RM2x6SyJ zz6Y=5)o0XRv5x&ZRUb_%RcZEd?o1f(2K35n2!AMfl{dPEx6W`UH_z`1(W>lCytxQOo-yUVDL%|ebN@?lowkiP;1oNdCGUO( zU(uSkpyt6?Ge2&&6auj^~R9(uI%DN>zIUdis%CUOr+2Uda=|4Co3S1?KfQ z>>3GMefJ1g_^R zgvq#6VWb{ov90TDvoVFszZjfs#e?G6H|s?L?n;e9U4g_-G(r@r?8E$k@cbUw{!*ecxhdgYl-KaJcf=Vhk?*@%yYdZjs zoUwAR!Sl`Ncl6Nx3cju#_e*%!F;-xIbqlL|jv0ooTARm0FB}V|6ZyBgGtl^)(3uoD z39?{Ju(t*03I%oY*JHy9-Z`-{NiunH(gwdzE(8yrKvhQ|X1=;;z{La9=}8?qY}7-` zqJ|02cL3lo?Z@5svLC+uF$Wsidl6xu2y*3^I_9n1QRVCW9YB~K9@;p8`{V^~P4K-a z_7NQMV3N9AL7)L|8snml>Ov9T zbH54$kd)xBgK@8|9nIGTj0e3gBMngoR<(b>SixbnsEbtC& z)WOUvccifm1S@5|vJ_|OK#ESt#a{$OUZBxTB5e88181y|_r)yQSBZtNX@!5=?};ft zd>|ZXx{PHi=%4WfkJtb&QsY6xMm-1KsiU7j4-T7atq0bq1b|&Fgcw)h0X*|a_qFgX ze-q4@I9>^M@X1@3;*Sq_WWIfaKIWyp=LdAOeo$g73+EYTt;d)bs%3K&2Nf9fB=Dk@ zO$vf*Qd@0kx^lMfb%DF_oHs7=#gt;5u^26-dwp$;deIrYIkZpkdXi~}>uh!2< zwR4-AV6(OBk#kI$|2Ce-`n$`;&w;(#LB&}@`qw$$cs^;yv5(7tgHr|SVB_1#{4f}d zQtY-#3E3dD4pSabJ2uFVyhm0mcVylA^zm4KU-?z(j(p)W>v$|5@sH)l(&NbY$5UQ` z{X^UOq`$H#%1JJ>v>398*3WJ2I=5z*K0z?iu+VaFtrMgd?)nWp$^=!OD2=bX)GYo4 zb5J0T-+cR(-p%{U^h_*1scJFGLi{h$`R#Cd-oTDmASu0me_?~$>1GHV68fN2OHvH?u}2M zQeW|JxH=F;@6w}mMwcu=rN2(j*oageVqVZRV=vLe)>-~udMS< zx$#woM~y2V-De}$bykJGm^*gx%)%WRxeMp^7Bc?u*bxu^iB{+i5}g4mSlUMfEP|^X zS)0z?hK37?r)c=IAJ8%8rwx^FTV*MX&DXr4g$bBa2EHEC_@~-hjF?I&M{3K7|Nt)~ZxHA1724K4V(ZfX`L&GQ?S?FvUD<8k59y)U$Jg|!d zOXf!w$L$YgMjaT;JB(M583$~pw?L!XEPlWQICCpF&^TBPJ0ZrOv_10|^C0!~JDvpK zNODjwkNKQXV~VaD|IpWs=C;U8+;sTmnI1>yqm#K15ub@t`Z)OIRWHx&@RJ=L6O*sR zs^{?S2Ft82y1O6net8;?-PRqkTj4`-!Bmn2B zvy8u7AY=ag@WYSX_Vg**Ab!mw_O!(Z?-yK;;(z!7UvN&@?Xp8B&2 zD*KOu^Uw)lq{^$F;gAyj1ST~nXE4}4zKK!>Is0r`Ae!xj^AZ^l8?mPAk2XD>?tM&@)`R0hsbFvQP zs{I3<_sz*j#l|(M%Y8~ui?3Heh3e&!2VjVYb-IG&d({X*(N>B7~F+tMheX|V9Wq!Of0E) zV9ynO>X^lJvSiX=@dAiPJ-w1(!Ke59`Es~Vx^Rb&4ooPSm~z6yEOS>SQ@c>S&|`7Q zBiFt=A{w6v5TeB0qi=QLAVpw-!{0Kh-0++PS>YsEzOpQ2u#E)(3Ah(CqVGk5`H6iW z;gu6>|mcKRP3}*u~vA>V+<$hTs*)>x=2!sT$_V!_6}B2 zuM$cX%q!~c3}C*!i51_Z*!yH2_*@&w z{=hLx989N7L4v1(_4iXCSyY-pSim9NE`~){VE6+uL5a`FlQ{Om7)^Q+N`FAO?ZY1T z6N600&h}x0^0bHT7ej&!+eL-SwncdsEG)j;W_XY&6YMkI%uI5FQ+=&)VAp&j754CF z^}*dbiwh5M`4jI1hTR8h;i(3S-I+())8%kD4ZRr`bD#koiSd>$8nP&n~dk4eUSHkyo$-S8>)DHtmtwZ<_oErQ*S!s#^2Hw<1-lw9*y zMTSHAee*CE%f@F=r!Qd)`XFYTTd-AS;k~T+spl_9>67>|ZD3|F9DeQ~+jA1_+vAh= zmd`?`R#)G|j~0Y53*_R8<_NV9?O>RWygSZ^DE)J%qKW*RKN6s&FOX*p_n7QF_H#+--8aBux1SPd-Hrq z4nHCzeN4QHkAEjwbhI=oAg^_FfXziXoo8q}K8l;)ZQpB3i`dV$o1B>I2^yW9b)-(g zN0HDb_>g4V?JD)3mjr_~H^8UhX*-aiP=XP8k3D5*Z_A}F{gMj=Akr88v0m~fYbGj; zbc7wt=@SE8ne=tq0$lM%ZXuYu^syg|!CHs;hdEgnmZWo=vFYAsw0w?v^#&Q)5VGar z*nj4)D$fhTYTw#Dkd>~^Qq&l_Hg(__+rk0<>9golupEX-fp7cPt&c`mpUS)KSf)R> zq1vt6*W~3%Y(Sij?WK+ToazQnMQv0&s%2jsoubU^5)Z z6aBHS8P9N96`m74*+M=~9m=op!YoJpPd;LYRG}$)!n8kD`Z# zG1yJ06YEpEPdVKS@x`+f2Oh~L1!iTAXsi6rdSC_iZ?b7Ulhlx(#~Sb+@rJYN;ABLB zimoKbiIdcI99bw_n~=pKq$f$qnJ4SP2EJU3=qC-Bgas3>PeeV@TMuyAluA`jT%E=Q zJ)dBVUNns;-c6P2xt_c6(r3tnXs#z;CpL5Gx>l$;Lq^?PUnhS1A?}DFjU)7tCO!jp zIm5|2iz4`jHYbU#40Yr5(Hw_ASOlEPXxu)6fsB?z*%nwJ7PUQDz=6lYz5@#|jHR}H zsV`2$*DV4VQXRMKR4`Tt4;$~++3ps3r-skEMi<&460+#wu63SHp`Mdi%~0Y{s0#ehY6e61d>6T5$NRlZ_z?LbFP zDiJQ{u3FkwY#cxloNyN}7X;uJebB$R**AB%-OQI*qIwo3iJ+SbR46r50 zKII}4Jd6;WzJSJK%>FijX@k%@;WL6hx&aq0@P#c`V{%p6~Sp^O%& zqKu#XB9H_h1$4BH=r5G^X7_=Nr{S?MvW)PB-gM@ZV3@uzk2lJU8Gfk(9g!_BOH}UQ z_uX3XunC?7`KE(beeO9QQ4>CQS$PK>8xwe=8@}YV8F&+P6KMAN#75OF7PgH63igZ- z$5N+_K*$M)bpl@bLK|hkz`A~9ijNQ4(EybnW35oanF4cQ@e8o_JH&#?YB%bJ*eXO! z(FmvEVD31nkc$~}+k?-@Vg0bDz~?)9iw4qj9R%A39}*aF<>ozGMsh8 zIf7G7@Q2;Jt5RR<@{WxPda{zVc?iTEl8ZppBehfCf}r-!8b8qX;s#Id(!Qm6EbRJg zB%Y^3+gV4X)|@tj2XVK}0662hZ4Xij24|U^U)YJE?Jg>UJiSD`Jx;zIz)#@9X?Bla6c zKwY*;=jan$0yj2O2$$dp+~~tXn^x5QI4(v|!k=xw${mndb~KSk^k}qRVWG}+orE@s2CbvciAlzS{U)eJ|kZ0co&FzKo+bNXgA z=M~Yb-QnVziJebR#pT{ZpRdj3UTh(>evPXZkpiQyGcLQz^A15Wny2rjYQ||BpxP)I z8=V@X%hYgDYV$|eTsk7}sP`pY;OIIzv`|kWRq>$1^<3hC%@3zK?Rha;?oNCBd(mMA ziP+x9d6O$l(Oi$eQC^dyFC476hHT;d$ULwD`>PwAp?Yq(GR$6YsGZ|_ms$^zHlIQ^ zo=7~$1$ZwMsBg{4pToZd7y4@@PTVYH&*;gj(W&*x5sGV*PXIIPHgm_I5!!>-@MqC` z$_z*r?lTW?&rj1?B)5E&!aDtBMSajx`Vk<*dJ?_AQ!-T;X~vIz4?0~CgxJp6o}F4# z0a>&Bt~y5>JbV>@#cy7es4r}RKJ^4B`hEIuzqIY9ksrWGz!JIku|(08P}^TCCy*hq zuVdf6vY{7@VD-?ic{=_S2i<(IJ17J^qe8Gduh$$=i+s zXg-qZjj^O+*&p9$e97xVtIhKvc?IuWgwfIMsQyZD?nm&s@X~Dz9bOfTwoAazg&F$A77hh9<9In z-_D+f&$##SR~yo&@;Lc@xT=57MPtUwF}3Ui+I-S~d3PJPM`M~0}i`ah2{&UPdvm7dB`Z*tuACRYF+T>yKH}anAHb`>k z+97@Ti1|3>c|Ls{j*H8?=mAzdE4{-WI6o2WC&az^*H7xTjN6kxT1ktuvue)31No>sASC`<+l^1bSTmd#$wy*f$5FAkI&tBb+T7p-xXIiAJ7Uv zf*697+-X(-B$}>+H`YGquK2AMa(eHTz#iP(wagI?kG4oWn_9&HLPQcu923knHD@^LSIE)XUJR9l!~RPV5wge-Z(yaLJIzCwqgkN9A$ zaI=NhcXbu8v1B$Jzw#6UTovH?ac@Xe?O-4OSU2H`H&xX2ol^;cu_|5T%I@3f#48=& z>8T$-kRbno_FUf&kqQpFq9aVPiF#zsQKn79X|8F$dss?GF6VGISo7}VR%7SS#j|?s5FWX3$r5zssh>;r zsL^$O1lB3G(ppKBJ0FiXW{#>$Cn<1Innb%X{`OS6QsJKS@}|d3k-poIZH%J|^Di~t z8D+~+Yl-+LTx2t%x!d@fT26DbPKbqLrV6@km(jKyBeW`Bt`MK8Kb2(RfNZXw6 zJLkB*3E0uTOFnrMvKP;{#RDs_zq%zZ4UqHjhfI~H98Mv#n#Z9#*B$eBb9zDf-7SD8_EUD))KUhZGgF1>XcsSzbXv4ZDHGTL*cMLMr9~8La-t0$ zp;h2P@bUaPcl>lWQeOf8_S>)ZF?ns~NuU8g@sco3yaWcwrJkSe^Bs5Y@(D;V%!!-; zn4k!Kz$ZNJJM{@bsYpPKLeRj6cgB79P%yfd*emeL(E$qYoC~-;Ss*sZW78ix`Aos1)U_+X|9I`9&LFMxcdpXDS8|5p0G_kk{W2%jep zU|}6~^c_kuLmn0Oo@E%z3><99hq=>hw;i3CO8OnuPki0BTpY*+Cys9C;tAhu)bJEa`VO4%O4lpveA=5nA{pptJZP0rK|5bya!vro z6nP;NlzTpbPQGxTlmYo>0sLeeeahodbhNwjE(2q8z^@9%Z#e5nvJ~rsQ_>R1?v~|< zU~MRVHsQUwF5V1eUzeIwCNuSE?HNd&kIvNWL1v82*QQGvUZQXO*@9!feL#O^>-s*< zywAb9{#ds!?@L8<7D!#@!{&V7kvZoyU1VOU=jx9zd^79P^?f{*`h!8b8JRqMu@M~s z-j^O?%QgIt@*cwfNZaLWZE5`D@iBBb@_e=O-5%`PK0Z|Mrn_IahjPB3;}PS{OE^k= zm&z-!e^6_FU!9EsCRugZ&9ASbLXTHyJAcvcI|R6@m4bl)_wu_a=(M8s8!B|BkEbLJ zVFBnh#a;UBP=aW>X7Xf@NB_)D*w=ZPuWB%;@tW4T>x~aB)Y>NYQ+CIUwZf$|{6AO~ zvdiSN`K#5=YoWvxP|WbIGT0~L1;eWy`{ zm-~WP%Qk3$;1BC<7;TW?%y9XQ3j~TS%{#tS5YNR3f_U0R zbm1&IEx7SD9taE}*-(Q#e-Wy zZ@zvCz&6EhvL362KLYr$RNqKYKLUC1BwmMX^h@N}IAyJw^v70URO^po9-l{dusG7z z3hMeXebWehlBj6TRq0~Ga_rIxIe?42Cu|s8gV!Wh>rSbSS;vRqLek3IMb~xh*B06E zE?;wm#zvh%Ze7k)6)4?`5p_RqNRY>d?$@S`clz$8^Hy$N8*W2#JO_u*K84>5JH?r6 zFXzw6+pt|*W{{7RyJe-;a5qzl#ko@g5wiYS81Q(9QUN_W z@Kt;61QKBL!918aU{$2x36j))Dg1eAAA^D0v{7W6%EBkAftnWn}LTnviVN8WTJ;@9K1q+E$~nf zM~N55Bj2shmG(y{Rl& z1dkY(0G|el93RnJWjriR0y3mx9X5c6CT29% zS9WG=5SZcFM;oxyIlQRn`4GQipo<$r6YDyJL9+Ni@rOqaqz4z=FmqJx{tf&v=9G4{hqt|^$>8`ewA@P@)s*E&JXww%|q-j02#8+~xf622PlfYYe*(noF_EiYPmHvZVc(~Vv zdBH76`RJ%BRJ}Sq2>E*64`h3_y03)zP-Py9e@>}W9v&|qtLN|!Fgif>g+t9$oMp`U z3FXRcU$`25Xh#R{^vfOi$^zZ^G@S*WqCEhj(GhGN9-sTHNOSMwT=)IvyWOspdcJ+H zrG7lTyFGVz?fqK3F8%!y7RLAEffd+)KYm_PmIvMn51cS^lfTH_N(a4OJc_T5&=HV0uu#D10A35m+(G2X zyTAmX;;SQ12k0_^$~u%@_O%z8=m=kJMj*%_AiFX-AaA>Mv;vgQ2i4q{5wR&BARwLzPERc87|& z*fL9>x$0sbJ2t(8Hq%>hNv6#rBdSBEz9l040GxcD{_LNzQxo$|gJ;h_?Ok^?TwS}@ z2T6=hltD!AEw3`8i&wl#)IpSJ5hZ#?FQdF97?Nl~l;}Zp5@Kc$Lx_^1_Z9@B&M?{? zUsmq-erw%z|Ga@Ye; zz>0bS&Ni1rU*lqF!zahqx9BmMb_@F$Q`#sI^w4`>OkZ)hiC_qMzxyNh)uIb$lM`2o zxawkm9N9T7`eqG2$f?Tfs7EG(!005cs*N1%>SSG6yP`8fHDei~0-4VUKEMSx;UZq1 zEt`8*%MjLV7tI5L0|exS+POo(9WGCo_DFulre^>y@#+Pj^m%>EidC>CnZzCDa!;Nq zQ~CnnYIs?G5C5lLOfU6g=z+hk{Q-siw1l9_+lNq+wR~Px#N1Q0XdOx%jSsan0aiOw z{Rf$qEw2yBUFm(ntocs#Szq&2c?OkUo+xLki|cl`sprsXF(S)FfDne*b&8#cSF&!O z$}J1oG{%>&{ymMe3L1~}pQrPNOUQJ2NtQZCDb%S|n8{*G`)0ncaX41)N)1pSJ}Yk! zG>;e{Z}0bhFky1R(YGvjp)?mJbp7a#@Jz%*+Vmif*elTY>N@$~`8dx|_Q7mYaH|od z*~R0WH+gPSGr5-8$UPxhH?3U_PRM5|>y_JWUC-+;D$Ha!?YBbLaVhclx=9bS?PU_d z3|VJ#$x`P9Y`Ox=0=kJ@UhT<31O_&_qpwgL@er8-0I67Q3-`REk@v#t6|eZauYQ^Z zJgZOdZF0S4gMp2Z+vJB@j|S#Pm{;>S;%`aXnNJqkfS{nGh06g6oFQ1dSyQlNUbizICNep!SKXvV$6BzmWVBpa>x`UUQQ-Wy#pTmQ}U` z#HKP&gGGH-iQ;=8>@a|tTxe)Bo$~!-v}98M^dY~%iF6~4*}BS+CTaV|_>Sows%iHQ z`B{dAMc3|2J&x1}!xx6q5?Q&AL;}ngkl!eyu+-fZ0G;rKcdw{?rbgKl4C}L!t_U`P zTjVu91QnW3R_?hH_kVq3CVN(#=&2DBpdftwj6WrgAG}F5cSe^@aj1Y3SL<*%oe&yL z2uY$Gt*@^5q*pB$4oXU&4FqmZU93Y-wARnEoE)!imM!5**7s0MhbY?3e77!%rcC0; z-ncWo2!W-0ET|i6-t2ryk@`qqC2D@g84>}MhHWxY9QnFZQb+~jM-Y`vT)S)a7ux-K zk*f1L^jfp%q!j+%KMT+^8UO}bd1?zr(F1;za7>Movazq-ya%JRp^MXsj6wyy^i;E$ z7B`v;Yh-haW8um%$|sCZIUL5@>+=M-sTsXwIbYmcYtJ>1nLwMn%wC9^`|^Yg`ZW&l zs?J?hxj;1k>II9-a^fgj99+yPs)C_o&+W*M#TR{D>eolvh4tUuZie|7AvaX@)dxS8 z+d%mI^doDUPc4jIAGNF>%4kPQKf`Rido%Q082rrfN21c1mRI1(EFj`w_U;GlIn&~s zxi0(40k5IwQmFzWLrh|8KV<5Hzh|R&$&a-$ZnH`cW4yUS!#Tk>N}%XfzI+aFeyuOYP%MQT8-Uz;Ggs7qMD6q zshpz&7H`eb*@B8b0t@jusqcFFwXDMzB!TTIfCEv{va#PiP!T{j+$%I=ivpn??fI>i zp(+yMKo`WkNk5L<;U_F>Jr_xr#9_@v)A1h)$;TUm4OZJ;l4|FdzVV5?>R;9X=0$vqeQR`~PxaGt(Q zhgW91(D^nd@K>qkI=u;tB$W#gXYUOLPZ%$#cN{pQ{*-%yACRYV7pFi~h(@TZsxeh) zl(DNKy|HDgW*Ce}{_am2ijyW8(3v**nURwy+n+a+QL{V@W;^yvjU_$r={85IzUF$5 zm+-d&(a7!x=(qc*>9M!3$DIOg4t?!UR_`DR@%ZZfoc*4~c5p3t=PZagkvE6P&wQ~G zy%LT6Nd6&fGKJ!}!*pwoLJ0M_bXYUeR&WT@rCpZnv|Yt?)6G{WYQC)`7(0ewWKviB z6Z_E;ewHW~aSly#R@MO8|@w!TSFjsyQk~~~3 znan;+{4veO*SWL7j&$F+4cZ#SK3b|GS-pkqd$iqhVUg`ulNFf~{=hybT@!m=UMNiZ zt+yq8?LOow1)g>?SX1MWV5>To{j6?`?L`2_?%7AKcN`BojfRmkb%@Fd{=AV^Bg|gM zV|y|@-%;p>c}O|Ht*&|qob-OG0s(v-0ofe;e)9M5@u9fgw|??|a}_uIopOUT8ic5j_@DF(!c4Oi=WX8t zNYV_HDik*M&M?Wh-m8;dH4LX<)$6Mu{uqdIi~`A5=#oEO;8*%inO*L1=he-O>Qw~K z4mX=pxBdWQ0A2?;-o(83!&I`in`6#bfrD#`YHzVv%TLm-&SO(`R;ym?wRFogq!Dki z^tV$HHn-EWL~JMU>v}@W1l3h*G9Q^j?f{h2cFL!@S$K|mewnG}oBXyVc=V3#81ERPHS%3N1BK`hBH1QPFi`7hiwk$YnqGRm*=0P_gS`oGxXhveB>OyvW zzz;v%9c)jJ;_J{5Wt%Fu1a;I5*@kW4CDVM8J3hlHD#)AWR5Lc{ZWG5 zL$$3F9Zh7;*83`JP*4$Q=Ls?(GEe7vquq+fLku^BQjm+>gar-IfZR`I#cRUA4t?Ud z2CE!e-sZMptDxhQbEu*P2{8(E^)R$?sGC^Kl>#w;$^$%#=j;;+zW7*K+&HHgy*PU%RR5ks8u9{`y4(A`O6PE z=5#*)F!E=<0)<$R;65EQx?ETCyIlJYWwjYKwcwibfl?Mjuh{X=$ zWrvP*D!{_}+dk9n>YaEuNowhB?43$4it(xgx}f=rTg#^3Pq^1)`(sz4VFSb=wMYy{ zKz0Lo=Kz9oKM7=2E^DNqja94-+|i()fks zk~-)Z@7yZNb+MFQd6qOD7n-7Ly$o}ol|w24XVcE1vqu8Lp0i5Ix5YAIZGz$Vy9!0E zW4(>>vYTDW&izf5v>g5;&To{zhgNzNGOhVGgq}(5M)C65Lm8XqQ!wpD(;{dOOBD8ntW28KuJ2Kp~*oQ>-x$^Yab8)u1oqkQ46 zBgd+^^jFrWle6OvV=C_}+VGMrHHgp(mrZBbeHy5+@)-2M?R)W;)6s3)9h9lpa9Jh3 zZTLaPwSIDJ3c$kQV!Lsr-Z|JI*x^U?l4hbTj52Vzr!dB9TQoFH4G#RSa)YL;-PAs| zw5pvPsH4?QJE5&F<24(m7)5{UYONfvC5ZYgn4kieM;3A2bA-|WW>DlvMJ z&Qxf9%pKs5dUCirX=}$5H1Wyxr61YHnwRX`>eVyZgr0`ck?^SPzUhx!pf5bN9Ejc4 zwnltpRe`s6_}?JOi^(4cV_{;B^0KgH9apa1iI!+djw3zNzheJrBJ`6>fwX$qsz#({=v|~!d(fv8!{w`=my%(lklZ)YSlP6lH5o=w z2dx7(J3MX%`$nlmf(nr^^-JXp%`;7uuBdhAjD1$BclbVOFT+gjS2lWsI0Cx zKO&uyXW9HP+Q0#dWlA6qwhuIU|9pf7cNiA44r^c-*_h^gM3>`=_7CfbvE&oCK_$uj zz*Zu)DzZO1Ewk)G?oHahSBp2n@4H>I#yh=Jk`HTyS^lL9m@rTIgX;U*SYt2%GuTDH zpd2+5;_2BHh!XQB6yFve#EU4xICA4}jI~S;lpRA36#F8D*E=IAf#BlLv!%`NEU+zl zKP=r|>C|7Ew9!kG=51gqu5;PR&gKH34!%!!? zrSQlAHYWp99=gvhK!|^&>j!{OCqqc`-F(}+&a|(!nrwMYR)zas+fH{h8n*7KTjZ0K z+Ev`Uw{mGOe*rdgsbOQpV7!G`J};2I5{Ij#%O*b_quJ!Sfz;YmRgJ}|PGkGyPY$4m zmxkb6Q@Fy-uLh|h==P#g#*1=4pjat)!6ZQYTH>IBK)%nfU-{^6AlV%GnO)FH5x znmF+tao{O6*vHElA(qnWA3TVB*z!SwjeWK;@9D*FIsZ<7206^sMRH>$CNHVOrpYtm zNBTRkY3}}Zo@4+4fX zM{-JByL6|2!Iil7F9O%|>9Qi?z}!O=kY$-421$u*)?@X#)UkJFN?bBStVQ$ONL8yuZjbXo>OcJ^`#UWI z1x3(Wr~a1D|CE+3Mh9ZfD;mFj@h6g+X8`ZqnvRQPk((`;1#d;Jqod-H8oO^7lXZUa z`$x;;QF3R+pFg(ObN)E%uDk9Zd7k8%z4tSF_Ut|Lo0+_QWTeA!=IR+1 z78VZOhnl7=EXUulupB$~*J5)fxciSEy{GhgTb}IOl4lJZo>`AX z)~4>?l}*#UFyb2{m2$c^Ut(1Qq)U&6scr^?*EwA8 z42{fji_OBS@BXyYxxi%gd%7IsIP-pvOOtth{P6rS78XaL`zKjgUc5Sa)F5pQnO+I8 zT}s7rlW>UM7aze3&B6!NrcQp&Pt3L~N)Pk6Tk*8m2m%(EBncta@qXw(Ay{t+UbPZD zPx@V%A@r|C#&Qgzt)*Ycw6rp*4HgQcVi~`ayr~Be%6+$VfmPp?t|{DK%(oUNZCq^) zH=@2wVW;nH`jS=$BCx#s2Vi0ebp?-FU>{!GyF)3el4@uusp+$2j?I2c?*2$~41);7 zh@p4U*bfkztxONhzImM;Lct{L+Hf9qq30aU@0!6|wguB2BNCkxo5a{hgPmjdj;LWa zM?_C1Q4GBCk~+qSz%<2=9e%_0*Bo&_!NuK*CPhszP0P?Hns7VVvb@E0$iCuIGonzr zZRW$Wosr+ol@fCIeKk*`lJ_OO8S_0HY9Y$9*&Pnr-r!+&R;Hl8nqmsLR`AsBV9EkF znv}=OrzIA&>sLI)MGN5PM@ojuSBRJ5gn5X+!>sSFS}Y)%*NnzX-jsQNX;28}H4R=J z&%Jpx&YK%I-!Skp*fdr=Br#O6puNuXvZP;C=0)*F!hrJxSe4t4uOUqv`goRXgssUvDI$~UzBe0xHUi+ipIz!(% zyO|sN`@Ci}Q~y}bvI#S;2Ee=r1U|No5=YdrNz?w#OwbBXrH> z$=d$K73c6O@zPLvS>58B*==4a1%;}#vT=FFD)2*^L^ymnc|grkyHl{o4Io1(6L65} zS!pW4?dO^49MG!uMC|u(s}RaOyNY<3D(&-&BOuON%$W|UjY`oP)<5{D_igX?b5Z$w z(%Cmubf?Vv{T5U&@>TCxC&}DHN_e091U2pI(S|fCHr4#?LId|*Y!79u`n7f4kLmf< zoCPymWQyY4>nJWw8QwiQQ7kT_M$$A3Yu+%)votw^iJd2u4#c4h2C>6D+n}BkE#-Q= zZMT_%Dl*$RX(AS-A~Z5D`qJrbuA-p?$-;eO9d;>HPg)YHuebfPK3Hkh&v<>e^E}-`b3Xfrh1p)t4jr~bK2B~U zFa@I6XvM9UpQJE+_Lc_E)0{ucpDXuEd}T*mSK1=aO=(>4Ch^LYUTs>${J^TAue874>6`zO)B`4x8xsRSPRYOY{%75u8(b3nQj9A2~XI48%Ka}?OTc-P7 zv`iBr>cq{;L`>hLV6S_t1|dKzr`S~iEZ3fFsG494^73YiOF_DUKDY7Be+P{~pLPDO zxuAenZ9>p#oPj?5<^yHJiDI!B^)8bDMf0`#r8l==-)4+T^9e%o28Onk0p?-OhKkP& zo>SPX1>oD|j`l>iUs!?H%6s7X(o*l%cY(pK>)TKhEO1b6lX~+0`Pa%3@N}83*$@0$ zF>>(wtgqqd5uW5dFjYk2gm;wZtv} z5pgK8*n7b!!YS*dk}M#{K7ZQsPd$gLJ*U>+KkwdXLPO;$BG|SvH4%Z$PwLP%Mw5H4 zf#dVre02NnNlwbXTv8vgq_g|g9?tTUt?E#}OlLCsM^C)zb9|>I;@EKt$PtqP5RBU2 z8Q`(3tg1uLj-A5RVQ11}mt6L`Z-x%+sWLQ zy4Cf-p&(E>RPbKY!W${*;rpBXo_NmI&-su-aQlP1rH)Lhj)?_Ji!k4yhr;^(1RLtK; ztG^g8c$EEZ13hhcGPylbJGAP?R(AOZvmOavQ|Yh#){}RZi94`ieE1=|~} zyC^B{slV|h0HqrM$zs1=r&ZP$8s0_b@(>#SR%Ze^4<=|Blx$PUS}bm>x*>Du$nyXx z;a~K~yE6XZltWsZsYV*|ly~=rcFV@GXBGXn&1PeSY=M&uYRn+(nm1>BoFn*>Jpj>> zH_|5&S6y=*CGcKoJqH<~akr7<^VDjD#Z;jd0xITCeRxr8wdn+HFsV91mtwrRZ$e2M zpV`_VpMM)_b_=0-#_ih;ouVcT%>qB*HM#C0^_GGVA?!M_H>&B3(A`sU3gVg-}Z|AGneN@Rhu*-=)kpLA+jOp=|{MZy(Qkv-{Ope%)^~BvV@FoADTX= zyzmbxOCb7!M{xM#na*U83TpuVMQONC8zjv4Qx zbYrW=THlnRc6*b`;`1iMthXpwcrnm?`&e=CZ;qUwR{?>Ks>Ukw!as=XM+R%PLa(z& zDsF!v85v#_&%gmc`C+Jcj4p|Q0(<~$DPIC*WVa5TcoVvcJY*{KQgKa=2%!EJ68%_ zP1CJ-&Nki~XbfU{MuXUxi6$v&VD!TNlln@r4mD{jCEK*ZS84cw*}u{~u7yv3`#V)3 z^<@a$G^IUJv$xoa*zt;-si~&`sr)9Pfw9w2Od^Ql(lAJE>5PXK6}4%0a+A zuU0R?Z=S{@jcQ|u^twQ2Y54F%VuGIkgN|vhD>DblJQL;^}@cI^!o9lm_7A1>ldahXN6)IuUorfsp+X~gccdBr=e ziv1O>l$Rtg^FmHsudr6~tg6516&KF+i%h=Dw)khs$5;{sxHR9v)caOvLTbLy$vOvKFc(rSJ;GaY5>y1yzn1HP02!o@zrWOncrAguE_igU_=0FnHHbrk7IS+ zQJ5_c)$>igq@#gpu^r2vaBF5y)HZTx)kd|YnU8=KUrve zUX0$!cQAO@;+8toZ%qG^6_-Hqi`X+>lJ;J8&avZUN@v4m?Z~J6ZX%l`@CVCW+xxG) zQ%cd_sg^n$6e9Py&>m)`Jo2zMi)N7)1{cX5D-gh*Wcj|wCwxDEJ1arGK5Tvy+ zPH}^>o7tZdbYnwsg0)Dt>(h3@_zgJf3Q>?60fA7!2Tu};41o^-x{tmrN!QQVrQdpLtL_2)zCh#*t5Io7Q`v=C;Fg#y7K0$ zZSef*fitIA3}Pl2lJ0N=89a!iiCfxSP&0@UXhJPX6~7)307_>3aQ`Ut zCE%;XDiWQ7`8c|3;SRlQ$iG)@YbvfiE>ld+z~M__iis6wU>Ahqd(biZaxB8$ltc+< zQRP=laEy#>IZixyuW!ack!Xv1jT@Kb9Y%}olG1Ww&30IP zoYz*bpF7`{pc1n7G>(FLy#58zd=Rxh5~VIn{i113!^}T7&=I|uJ6wFS%R)vKKYAZ% z{L6%OZ8k*ymM8s5p?4a;`fLt15*DPY?6T8`({5P2Wr{vGCKD0qyByr^;rhvuma+jC zG0gsn8H} z7r^SR`CpME$#IdpX$ueCjD?Cg&eGF9^EhT4I3 zoN3$}io%1_I#A$y?A>LM_uH%GC2pzeu_YiOF@KAsRQm(@f@FDlqv?;t=eBzB4wX3$ zKqLdvg;cAvE_?g*CLI_l@1dYRo7uj8vXPUioObsGKPQW|L<0IK`@kDUtUZp}j3 zx@vxc+M;IvY0*`&@l(E~^BiA1(#>r}zp+>jtS(x+`N6c$up+BE3&B-yFoFU*K(W{& zqe^GpfO9quQp7OH$h)h}b+&0~db0AOZ#8NGEOWAa7(DP3xLht0-x zPMm-XaxU)MG~j{+L%9u-8*%vh#DMkp#uAX^0&>Hr(p5|cJ_NURQ?pq$B-?D*!Ps%? zWic~WfEq?R6x@Pf{cj&Rj#3SC3b{tY72T_V(e1xxe{A*(dNS6?oYQpX@qTM>`%?6k zTQkTf7V2ELx6i-yAFoDzQ&jRC2`2fi%HBVJQjT=RiBs6;WmabD9NX5yQ1sO_9}ZXT z<*;)6%0(8I_V*_*Txnft3S_NHz@(;0C9Y|g_+ji_%YTLUG7rs^WV2i(7xU<4VO9GN zfc|z8^F%jpTO4B&&czzA zjeh)txT8Mcw`@=TxXsd&iQjtc`z$7(eRO`WGs|T4oqa@fJ!fLw+v*0)hkJ=lOh&ID zCr+9Grfy;*kkmo>o496vbf~K8p6kBq;$ITzIa)T!vs)RL0WqiRcnYaA83P0kS ziNQ90BMIo?%z%^o9Q<_t?^E9NFK|lVZ>Lqj^@kG2<{UpwX7uRZfJ)9Ls&;H}Jrm^)UYI?GRe>YVi8HWx?pP^n>+FlG5uV zXH1D>Nvbk_PE!IWQR2Iep07q}G_~!>p|x#f6z!@1EITaaxov@cwmg1ym`3>Zb@v2| ztSebgQKCCL44$v5J9E&c2QQ?Xb!f;ts7U0l2iT-0sA%3yv@)?gyLk(Q6?sY{3(KP4 zZr^LHPTGytIwWlRz}KtOfScwvja0h(Ms~HL1GIyo?woGBlxNG@0u*5QDC8lsyiazo z{+=?28V_7{Q1_Sw=i=Dn50~M^kcf~T1Qxe{CbI$(GW7=N?MySj;ROKk+DCfvUBMz4 zr`sjnaT(r}b0+Hcq_DPkRunsHNY07j^GpES^77!P+WA0E+3mp&`h%eK81tbJx6qAv zo!WOt539k?r9)j}-8$y7!t(fuYLg6%>7E{uWvl0;DzlRcS?j^9k@6 zO$UbvgvhNztXsL;%sq|Nfs9Fvz_vck`ZiV>6Z%*5^*2I4Bj+Q! zPIKR+&0f1gLA^+64{tfadc}jE`&}<_w~tQ+&FjklwR)t_+R-5T%H3J@%06fJUWUXHVROmVFm>I_{xIE zm<%@177(xskfZJC{Y1ydJ)Dy~rzb53ciFAgu{F(s&X{(l3^mP_g5^qO9Eww~R$puC zmqH68k>9H4?fES3NuF}=aslNP?Bu1bBiDTVn~Zi|A7J4E9JhnO#w+`Tx4r0gjLXO`T^bd0Pw zwi7V?ig0{d#us-PL6&Rw^4q~axs31I*X(wy{RWYxb$_SUnpSoQyEmy^^i~`>Jlm}C zob)qpiEo-)_2GUp^4JFab!#tLSy1V#wBla*m)md$c%zxED5u2gBT_2bN;fsvyZc*1 z`8k-Vb!iB1oj5R1Esr*G%tEx-GBG)xaN@N??CgUGm8AZ@4@AO8{u&wDU1#@z&#cyzjy zcHFB}6NtN{UJ<;NrZ)4QzN{KO{{7Tm+G@XGFh@3|v0{YM`J0%SNGGUH*Ms;PhFyRt z9+TaJO27noXWCdNf={^zR}w4{wTvVxjQFV0K5tF9cwvRQS1p<0M7HSb?L4_B-WDg) zPYT~_5BSB7%x&Yn>&5yk`E)eXpX|I!9hnufsu(}rs4QaAN&L`OcuJv+aT7+nQ%63* z;?w!cHKDaeCxY|I!R8zbym>g5!CoNwE5ANb?k$;{xg}bi-e-j#8C4~vHg@Lie-bkP zZ)55IbHeSYlT}hgBOR6UxQl(~pJ^4>sF=!RBHqY0Q;ZvClPs4%<45y7uq}fE!!fj; zyX*TC_K@S-<521Si=)ZThEbamlG6ZX9likQh63(%$u zVPv+U8jl;O%cGU$ax67Zh^7_agMNW=W4}>M851 z`ua?)G}Yz*%EJAV5UcJ}>r{IvKv8V;f!F67zT`W9JbhF)S}MMf322CQ=13K{4ZOC~ zDEiX$&@HKwhUg&~z+}h)?2s(_%)2Xr35riN>tEX(Se-NX3-Y}mw9;D#^nO@8mMqml z_KUQ#wCQohTBm6jr-@rX%!1K8ApCp#g1V&F6aQNr|IkjA`sWy#G(Q3w@hfzmBZ?)% z6yN8ln>Wv7kAG@coMCfoASOJgq&u}G)PAxo%txtb`?`-|6(L{Qt4u6K2frQ0l6s(z z=u3nKmr^K(Sbw}n-erw2ip@rk7GGRkNqqaHFu$(;6IRgxibb3|@ak00ZOK5-7JtzT zfbR^zo{)4eAQ|kokV{oWT&y*C1jTI&ucyi6Qo|a4kY94dzxmx5O39*t5BE7njH|}i zVOF{`h)n`f2GFwKHv{&zE*}WDd%1}<3NON-hx_q&FH)d#J2c5WT6rVMn)vP(uyMy* z3Af<^;E#c#$1e|V0jT?C7aHgn+G=hA2Y5UaQBF}?ia!QG8^2gX-J+a0=F5K3xz5I_ z+WwAtrgM01+j55S>RMLCV-vQA!5HtSr^hcLz=-Ci2%Z&G^x`TkouVsTSR!&^4)!wWiw6B{i7aIK3-p$;sVVG(=1AZ?Z^5Us~k zADcO#2Tm@t)xr1%m;I*|{Z1gm6Yc5VrbSq>UYKy!I&y0e2!{W43_~P!=fVABS*H}; zN$w&|4lUz=Ixw$rL~|p`mjd)7Z5?#MI3;J^FEj;Nl^*=~?Irt&VnfN}YbJgG76+}f&phsGRXdN|>S5PcRsR8|= z8LEB<^~Q$bvy2BZe%&s9s0#5^7MTKFWKI^bdKQe@C+%k5cD*{CxdHSttK$o`UUPU8 zV&u9jT;8*Y^ebqn71>H|h%IN@;A)YvW%sD~&R{F^s3D1*)aZ`|E176B$&94+)aSEQ z1#$D$GLMlm0`v%cevpEG6@8BH65aK?mPJ_YtA#gGxBj6>{_xmaX~wka0DEm82iW{b zc4ZzQhP33zlqk286yVsvYjWLM>iken%~`j?FR@a38aCfnd*7tJ+Y#}KpN5!yGzJ!+ zXVz+SRn8+t?)eg}xTXgl0c%Vp6`YlEftI98lbGyO4mWHD)X*){?HTst?l*|ml>@rV z%R0zaT`X1uj81H#Hum-Qm|U%=nSL5uw%t7i0Hz#L6TTbB9NYLJqf5*lZLXS2-hBTQ zv@^^TRi~fle|FV1BU>8F6JWi8loUpt2-!zAj6hKt2tHoUJcx~T`mj7^NteW_RMJ62oKQ)%d_`^0^D5H zFu_Sb?y=I1h+!t$5oe~OL3tU-dO>tNcmDg-2|`x@Ic$Nv2O3Vn+fS; z58W;J+R`uDC$`?qR^{}%Em8n&s1B4ynneG6AI>0X)?%v-!{?K>{DQO zLmYt{4QZ#6_@gqEA@eIG%>sh85|Luhi(MHO0s*=%Nwnb7qUDNwpE@c1v(l4)t%Gs< zjwNVUnb^JS+7;M44&?$?WG4lezs zMu3NZXZr^YgqNZpG`5Veep_4>T!q1VRK&bvNyO})@zsTvSl02aS-EL|{Rmm3U7WU@ zcm`qjobu}3?rT;1J-@~24s-+@Wl1ue4tcO~832j(!* z)*2kK2U683+K*41AP0(sF>3PB_nZRPqyb)};R?VNSBwKPbL+ev1SYkG1O205mx!2_ z31#$|qk6qQiC?kZT~#YLoCVNW70f{55zQb!ky1YA#2**kre)|T6P zj2$QZH2R9~SI8FV+TK1EPe=@>u||^2t|;#wKVeFFH{xvV7c+xldN;DKZvM9IeVt;& zuF9W!?Q+R&9X}>6K6fGPPpM2U>rs)+<^QgF=Kn3B5PCfgH{@EYG{z$cxwaugkE8E^opQDck%R-jCLzP^qV8lSZVK{}eNAJUf zv7|fdRaCR>sa3`U`jUv%@-#54gZ+n)ITMX%8aW zr@jd=s?7dvIDCY-heFh-Px(_HX|e0uKz@e7l%`F(9Cbuvc3Om6?13QKHrYIREPJJ{ zHnDh_g!^0+y21<+KkuhZ!*-0ZSa3_i!G^ynbkU=kSj0g*HDl6cu~r}8Tb56c!+(+4 z{@}a*Wa75w03c#go1f;vmB1?w{BWtbn>6|^@-_Km!0$b8 z?AN?6OJ*GMCI`ml9km6fBk;G)?h(61HYg7!Xs!0k1%=!Nbt7dyLGypN()>EkLc}Z8 zK(ne9U73(C>SO@VzG9#wjT0l%v5gj2WOOLVJI+*edGG+aL-%M!tb~tEc%Fo=J|c*` z@wtf9YY}RTj#zs)Ls~OzK#{8DwU=B-gHTYnG{8S`dRTEY1mhn8KDyA& zEW>!JC8H{f!rv)UbAXOs#)2!>2nXfZtCby*kJPCTXQ;Zkg8|$tha%qW#{d|pSz57I zA8K2`4Vr-rehI;aI%BdCD&z>u?Og(K&t_iNIhS|(A)9)Xh2cfB# z1}lYhh|N}_1RPQj zsOPh+eF9Kh2WoE9x@e+tR%*D#1MvevD_~3a*F}q;hgLAzt~KxwYZ@m%6p3V&&NP}8 zxVM|XU3?kuxRwoWAaewMArI;Idx(L>G4#|RdWtdH7)*UBaFEbhc#(ZbQ{? z^Bu+T&V>uh#^i{Ox3mcO1XvdaxdxV3S$%FVu+*&)NdwyIVam$>);}veO7sr~fd9_h1K);hM(fVzM51RRo?Fo+ zB!s$`Ue4_2W)ik@^e)0kUuFo)tIKV~am^8)e`M$1IxrMMx44mn7@2rIE{wZT<*9RE zKhs&fC`{#6)}0pCTrO(`1`-ICvrWtn=I%e0B&bg1CyGMsym!TFS`q}4M=3>lj7o-w zpBChp_D%2cB?{2Ad^f{!nop)l2zz(eVY)#`5fD(?G#;wR+k9ffFqDWBVy*2YWPd;k zAcd@u#Gvr-1X2Yra-ReZSCjp*4Ddr_)vY9QVZrp5bFAn}dPvx25YkHIQ2jHAE{_Q8 z!N=L4E6|@92Zkgxv8ah2-MQ1G%u-YWt9-q@zDSr_DShrWpXL0}D<03N)Bz9pEO98kXwz}^%b&v>BWi2+4J{s2i7SSE9zL!8f zj8nCX$777I!tCg+1HlCa1Hpv-cp7!_VR}YirqzjO-dhimHETIj(zm*zH#^gy9{92A^YArlUF6#;Pa~vxbf;%>1mrdb3)lxVk8a z5$OjyxS7>MSkdTMz6_rgxe7RLiO-CajAUJN?vG+tT7>W7K>Mf>G_mB~_;}AH5uXc@ z`(_WjgnJG;y(BIHZn;r$%;H`B&k>y9u&*&1b`22kX4liS_edQ-6!HlrKS)Mf%#sWTZ1F~{lqwt=Y0~Kf4_F|CGm9_~&B0ww zJ>AXp?KEILV445Bt~b%Msr2cefVkzI((q};`I{EEeH z(~@YS1DC6I=*-Dc4oT%1WG?EAad&t#vM45NM{${KhH_DXzXyG(1iMV^3~TbI15H_{ zq~O7(zUK~Sk3GQMjFf>-CT!C@Ua9G|t4Z7atFXlL5ELNSW#88* zCt8}mY#Vp`u-I?0RHmEAW89q`3HN2a&@``gaAN~v+_?qFr=Q07pPu3xuUxeNeiecj zcRUb#viJ0g?kQ=QV83EsD(7p#18k{sD(b-_firC+e?+BI^;M9YEkF0<|%o6L00sT#UOl2HX@ zX;o0?XYWxlgvQLV89U5}F+D>|n;)4vpQ>$qKnCkMPb{6V1<6ujBz5whKT2piiMwE) zxX_odR&*Z2T;J=F*>kK*7#Va?a{22A+n)O;$3SY3N3U}ZR0#`iO-OJDzHeZ&o0HKA z$zCk$EDBzHgVH91HrzVsYA%ZCp#Orzg-z@o@yS`!6k9MgB{F~cgc2WNaZ4)cuw zl3u6ok%F|w0qeV1Nys7nwZ_61bynY|T-Xi|iCtsCF&3OQB{+jI0Y=R)zCFC+PT}~S zrNkg-ul8qe%-{sE2U3k}9ZpzuQ8SG#`mb0ruxiM?m?6=IN-`7FQbcZD)M(%GxEE05 zKNZ%wSKMz*7IvrVDsJfIE3;;-<|UrSvRwTFRNw7z|w{jWvVJYhR0hC$=bR3 z@%yYrwlYT*Ff1RVxLZLHBHLB_!ij2^!+Us{&x%Igk$9MQpMRBXKjCUk?94Y-FQGG2 zx-as*R|dskAH`tQ^ejt8q(L+IqZAXi%{|Oi9wawLEN9BRZQ3&=bz7l?A$#`nM}PCs z8S2%SL2WeEgK0Ybf2y&kT+bvzmj)?D=?ErWX~PvY%cUGiKG%@{yZ)m9YMTA1h}=YB zcf%hdQH~ogBpRlQm)zLV-8N;0%9Vy(HD|?wXM7E354ZgZ@N%56*!D&81tuw>g13QU zr0h#;q&_TsbpS(YEKTt(%+@iJu`lwUt#oyq_3Pk26-w>uDD>INBwWhzXXcB23i=LV zQ4f!h=!*;_{@xGyBQ*N!=#7Kcus`CIHpvQQN_V0(ZHM#i>{WDX2k=?=>G-Gc7*K! literal 0 HcmV?d00001 diff --git a/bsp/gd32/risc-v/gd32vw553h-eval/figures/programmer.png b/bsp/gd32/risc-v/gd32vw553h-eval/figures/programmer.png new file mode 100644 index 0000000000000000000000000000000000000000..ad7ba084d1c014bdbb55bd354329851a55ce1ff0 GIT binary patch literal 55778 zcmbrl2~<*R_b_gC8`bPKI;7TZu(F)z@s_u&oGMGp35~=7kQBuf!OF5*Ib=EGkk{1A zgbc+2#mv-H5Qh{2g-pc((G-OQ(GRP8-}|oL_pSf`Tc2xX$8*lJpFQvW?7h#!3y!w( zTa>rR$jHc_JNw5a8JTrV8JV?`O&g?l%w@xDr2nmfU$Q+VgYDQmA^qbQzmpCpWn{_{ zWtV)`OaI<{^XxUajLg>etN+&QI&%KDj0`>e+#e?|-}0K0pk5!ON3b@tqUER5WA6BP zuR*?v-LJhN=Dy)8)kmbKG@!TtGb4k$79yQ3YLF5p2~RkEtND3zQ{VJ%7lXF#lfA`TqUC7RdhJE&%)BB`8YnqHJ{jB0jnVwOolcUTFY) zE96j@dS}{`ZT{Y8t804(G=po6`m|JREg8$q&$p&6Wxzy*f-=kH!~fux7snE6Qv9rh z%u*{x6w+QSAnNkQqW`jE+MWOsR{Gff%a?WfXc+4q2)t`cI`nT+uhk9bQ~b~?LJZp& zHSLgXF>m(7H%EY^!0O3Rkvl<2Px(Fdj=?cQKNqWQ9{6jW~UgP&aT zPeA{*_{8|H1ENlG$U?Y-^{1t;V{^lRiAsz*+7`<~k9&Z`RCJFhHJI5d5IL6)E$izI zM2ld@fmQ4ky3XeW_TnN3MqH|wG-x-;QT;F~ShAawvGtsJ+1Ykj^w$aWvbAK9Qwj9i zH&ODsKPYc09xx$HQ7gKH=4(=K@HxlIM>C=v$D9RW*T%Ct<(h=lI-%d(C5IzSV$K;{ zK^wC4N@-~%Kw{O+1&gl!x++n`wH}JVZ+iJc;j-4N8&yK4zuk3yHm`mG<>O~=NcXCV zU!qoyzFp90Upw)^qr1Jb(cgs*G=UCX(qYpIkJ~)H@HoLh+c%1%!GRDW;S?%Afg3K zGp@x~&Rb>byR3>OZ?G?q2f@wr!k@Xf91^Ndqf$)R;e?nGPkzB{R|x8%{I z_+H_i%i5R-Ylo=lvl1}2udi*dkagf3pky``JH(IQ_1zwzuGjLR40z*--3H7OX46Vk zRbA9kyr*$n;aj>I^;uwHxZCaNX161`0%xwVVWW%H3l*UHA2$%&k>{IDDA%J z+2R~JA;R5KBoIl;Z`fZk>r<&)J`ZhCb<8)m(!WKWZ@Xt2$FF{$D?A+La*XO5;blKG z@T^+(#r@?gG=_Vcs{eU9HqI%x6Orr*9I9ftG(f_~ik6ZTpdF^)8MVLsbb<8~fmn1U zBzj=-*vjvWK8hgD^W{Yw)w|QDE?DIydV2?&zpF#ctwB-!ZzMPuNMeV*h$ZMp(96_P z>yD$mB7Uvj<58=(I6Dxw+sFkt8&EdjZRL^C8DvKTka(<83aFNd7%n4v^~LrxuKm?< zGe`u_P)9n&(2P-aE+}k*YlQDJ(=v!4^HqgvN?&%j3snc#Z1PbyF&3Gd>-YM*75j5V z8iTk*W_YmSUt4Ye%g$%12_w_qS@2xj`KvgOQc`qxR7#7Ob6+>WNI2&Dwr6*P)9F>40x1kFUv`Mx)uZ#K7T zxfC5|<6K*VeoBf2(qAMr8yTfJH|LP=WKh#{F^@w@_RrcU_eSE1lG8uuxIou;M>;bm zl_qw@SkTVgIsx4ZO8g=JJl}(Y4oKRZkx{m;w|b_s{^qd!Y<-uK=k);B*k<7~wW2K> zj_5K27UQYrXUD44fEAKXubih5*C;l*Xmur^>)uKgSe|{fl^)dge)U3VmPhEtob-Be>D&U=k&F!95r`rPt0NVFP&?RaAi_6(}J&z zS^1$KNnTDxP!Lg2=XJE+>a%!DqqOQWzZZ!2{gMRUWJD5+t6KyqnW{4EOX8AC%r;_6 zucIxfQwu!KP%ZHE59!%F95iBCQ25A%u7tF0{EY+6Y{(2{4;tJ@&&}ZDU-xK1Ly|C$DQv z|AlhRc~9F7`wO^%R}!p!!-rjlE>^mii!&%0?l?Ngq-1I7K4C|XZh^$7F4RiQ_z0M%9$Kd-iBf5zVZx)XLIi=2Eq zvY|2qCua(Lx)e$q3g}yB;@W}(v z(K&sZyC_nCt8f$lh?gg{%Zx!Pc}Lq&-nW0oraec=Mhsv;i(WO#dg`x^Z(C%3hI8o2 zbZGgQ+u(F9Xekx(Ga%M%+Wb#U-CzFv|4+Ps?M;YY5k}Xa{DH#$d!2g!PpQGbbBWij zAhB^Y-xzl_quJI4dRI$H+%9@hUjX4sz2<8hrUGmYyeT=>NvEV=*M@_g>edn5E@pax5`Xd@{mggT#%~@X011s)M1u$BT0&xx z1}HQE(~}e9r6j2M_0ggwUh>@3QmZ$&#e&bb=bvR383$7>-afp@ywIRivz!z0!g9rJ zMGPdko?+%XnX{FhOlFKLfOd25x#~UL)ekvl=?mBdY6->N;qTPx0^oXyIkUx7$fY3M z3z-rt^K0xtHHY~c5;rEcdGhsmcxnwWZF#{;*h;NRpq={eKn*$V{Y|&3NfJMGYq1c)km)Q#%|MZ|g zf6wg*0p~RV%T3hI_sDXIa!Pzyp?rMNcMLyzf8{;`HC#*y?&631a4Zj(s|wn89n% z3TuXN%M9<;c{a)FGfVGYbQcclzh|Y3h7E9jYZnGotkcrKJqv@}dJWhw@IoD)e&Ezz zkpBT2Q_xgn1h^KV#rt-JU?=pA@=T$UFA}Cca-XQGfK-0y_NTNeMf@NGG`L$0QCXDE zGk|q>2o_D!7Lzus=r<#>I0dn0x}EvZNE^ijS}ZPFv%0{~-iMLkq@CR;2Za#ez^4PZ z!V+MCRE??M#r%&s&oF+uIhrcnOW-FRLuM#nmhR6qKacbQK^D-@t%wOp;@e zrFuFvtY^jRTLgM`DT>p=%PQR9*m4LzsEL_=X%^r2%wxq8KN;`cymKofcp}Z0VAp(g zZdjfQtUehT;&^CXuBN%b%%rq_?d_ksyJ_JNL9{M_n|(4IDLjZD+#Y0^xR97gV-HQI z@axa8+Ez--GRS(?r4d{d0O`Hd$I*<^V8p$e%L;I)2M>y|H%$;5^bG4++iI+kP*8Js zeM+QnH=a#*6!TklR21iV@W{wUrn2`!Zcb%uQIYTaV9xG2Em*(TMA)}arM7*AZX2vR zm^Zz+|JJ5Zl||EY@!xi*`=QIl6ZRzi^6s|d*g3W8US%`=S6$!27B*}!$^^6v3r!8{ zN!ea2K@h2~8Ww9&XnPylTVJacxfdan6SCYLnNP@(yAfn(()mzTjZWo;su> zJ>-7>+0g)5_v7lg97yHImAB77k7Z-%s|R7}&s9aT(T}Tl@4X3Yeq8R}fS3Pq^+qQh z`s3>M{r@A#jko*QHru7Iy(8tPA0ETh{UY7c`+@0;g|uip>Fv+k-bu09EAs$E=xUOc z-bg*YLgGZ>(^hX!={zW3c3gZAz%J*GeW+(kAGhm|vZL=vG3@u*8Xy@A1J*o5NV2{O zrF3{l6fTLiSLrY(?=P(<2H6{TVRLt^przCvrzS_QtpC3CHHZZDkHDCLMQva-RGuE{q*jOp0#;X0#nA7k+)3Zlf@hz6WQ{Pk?UAv`-f zNiF?T$2+%3aL^TkAEXE@Fg-W%Eq}>T+=WpKXc>j&x2#&x)E4Ju$sTuoW^Tkn_^CIG z{9JTr)KZEoMth|}y=AY=?UIHu($_bO6N%A>6{jm#I-Lv^qGuF<9idXz8{$hGh&S<;EZU?XcxC_ERg3j@O_yq5 zeUs!}t* z%7@pBsyVGh?GO0@WFxy>QU+2?%T(FJ&p02V{fNxX2@Bdi5Uy?e25X3mPIG|Q+nz!3 znu@1gCkk8*xLNl3sOqxV!KE-$9s)-Z8c;}RsWm@ulbU6d3ze5i{OZ3~%aV;kEyPp!O?m4LHh|1m zX2_&K8g=3cR$b~VJbl{gSJvX?RrNOG>IBNC#`nI5q;*yATXo*N7_#ix*TqB9JUmpI z1$n5gJz%<45aH;~!n<6NJMT&@|XTa2Jre$J; zsLTm8oX@xjmmr?1A!_oIwt~cwaJ=EDXSLA^W5GpwV$l$FKCnu5NDGPh9%yb$IDr_b zrL`5*(Fsz?B$vg#EjV2<>O!KAnd%RMxi1zQu#_v+>fi1F!?UJuX-IlSj9{riGDlw@ z)#8}O1o_S@hBv|hFn&;C`Qy&56SQav4KuSmJrjf;u|?l_Qe-e%9Ov}iu4Sf-(|LU# z5rCpTD91A2+@Pw?y%DuoUV2LM`w?P?Gp2ebbdPuyygTtz*Fj--!9~1kcr8(nu|91L zjQ`22OzRY}C~HVd3A*_onbh6ksg9A~qQ8>acd^4)4?{KG*CGTB*-Xk-b2_(nh)r*XlY z)hgb=?H=@oBp=KiW7LLbE?SqY+}=gD>TCUSHXJx zVl6Dm1?SX?PgzX5Wo87o~Hl!w3iD12C8m@nOEiM;#H&b zzs&zZ9MqsB3YK5{h#C{BLsyVHmxY?E>jkn+S03R)ya_(RH@0s(HAYj!Wb#@UR-<$q z-Mr1l%b-(qv2FUn0cvK?_$y>|K%VPr{^q@Mq{&rkH@7WEu9F3ku8f^>hyi+s$_-(f z;@dNB(HRYxTdH`XG=$2CWu-yo^KI!-!xF7hEo@PUtbB@zm|j_Y-|;eh)c(8i^#fKl zaN`HZ3@Fb#+;^~pa3Fp5g2v!K9%}WWRtC@e1y6P$kJSdTHnF^h2~wK7S}4rsrQ&yx zjiozHX|H0m?#p#DB9a)csl*BOGoNy4S^617O1Sc2D}s<^#P@ggzrTB(yBhIiWDc(; zeJ1;U*a30PcZ^q^vJ~isbZC`M4oYzCUguinbwA8a#hWnn{>iypyb79>XWPER@V0&j zX}o`jer9~>{g0I!S650aAK8HKMBbLj;N|yh_?IVD_a-RZ-&jPMoekjcQ=9(n-(L7O zeYf7L)%38Z^%|L(zL7F98w{TugpH5AFb(f9m4fx${L>MxBNNU#e5IcQS5d)_beTuj z;ZZ9fIBz@>PD~XrBpgmfK4+Xk;gFmZe8uWdJ?cF>+%=)1vKI-U{Ogc0S@CM>b%fU3pJeWce zpR3VEiX)MZN(ZvRJMt`d{Ri-eUpB@t2W?4urGt5hI&)|Dc1#W4vM=Glrx_K|f{yE9 z#$;9ns79Yds_SgtUfD|Zb6!OsTn=Nwf&kWA5=Y-wVz|Zosi`*p;q!S4s3RDy(Yc=v zYYoW#k97>*Hl%)LdVgQFkp}2i%iLY19Djl>bGFK;hY$&UNt*G4koUBJK<<@KY}b`q zL~BM|aw&|uSyC-6dYHcgtSkUvBr&m`xR|8Am~=9yJGn^DO7(}Fr2;zLQI%<`I;BTc z9WAT<8ub@l4QkuFR624$IAVvYXd?PnXD@$LD?Of!pn97R52l2T-I54uRHea`;WH{1 z-s*2hyg>k<7e_hSGf{qgLSWw3Mv3ki00e-Fu5O*0+dAd)R3%Fx14==F7V zOCOFqQShJNXo5oyn>fgRyxcOsYMe8v4?JhCu!6yb;yWX4@7&SUH-Jm;q&nWUFFYDs za-~0yz-*{1n;t>`a>B4{C|&(5^N)JAmo-4tr4C)@;g-%DMemSwJk~Y>SXp|OJ7`x( ztR-Y=JFEExTr!xu)C$Sz?w#IaC8k4`35T9pg31e|`Ec&?d=bW09c7?qNNKSWlyQh8 zF7Z8dB=S>PUdS=P!OFvZeH!kK9IP*JR6E%77pbrs*Gnz9xf5ciN7d>?aBBQ&vugl{ zsOjUq(6NVQ%@EfG>-vRKiVAP3{ZG!EaZ=nHM)D1BxNpc)Q`)Wbu~#oCf!)=&kF+Hl z7#+@ljG`8(D~n%!PG;82)rCQv zDY3AKcK1wN)TriAHR3HCW0+TY)kCY#KQt2@!nG- zyzkp@=vZDU!!!V0EY?0Q>0&RMHwj9yZ6$Fy?Fowte5tJ+-n9Sz z;ItG+y`I=0Ri}8ui_koE2mIKz8|N#%2{Ctg67Ms1<0W5JR7ei4hb1TCl36g|3*I8h zV!yWXIBO;<%dn`d^g2qV;Q_$E1xOU-Lj|O`9Ea;gTx2y@;7U-|%1|uPpF*B((eO`AQ&J zV1yvh%!wyMUV_lTGFF+TQ+w#nW#z^*P(k#cZ=D#4n(liso!GDrh{^$;G}yoMxfh3Xq=G<>%3}1~>5oz;%Dx;hReUa`nM_DCZZf2YzdEGPt_~@_Ol|gGkZhDy zj^X^yVS34mfBz!@-dqLsB+&c9-z<#Pec)5Aa}Am5l5txbQX6zWoA>Fp2#EC3D}PKd zy&h^~-MVr80g(CB)1pzv_GN_d%?_(REh$f?cCG3Q_7%M^=%rHar@d}9h)9&^G}i(| zJP3op7cn2Ba~YM^el7IL7h{vmXQq{=Wdys*0zkPI6H>o4*FH4kA1&bm6k7E9*o)b0 zdKBL{8h*V=gRQt*LKl6m%u*fXa>*rmQa zghj>c(p=8<#dfrc^oma`_@Thqc>riBQyZ;&*h^+6dgT=xCh6-B=%^mAzW&2l}uKST_gyHZPQ-%oWUW1TR?5j#C*fcf#w< z%X{Km85eR>Qzw4|l*m_Y!b?P4oUxO|>>vHreWhPSK?Jm%L!y~W&771VZwvmJZZ-lH zGD!wEC<-UoIhI`HXBXRJ1lSGH=GKY+a(5^+$3SD*oSDkPJUI2Y-K^2ttW@JIa*Hv3 z7x&U0Adb37zR*^l(52ko6{44|*IcY**h@ydN;c^TLNoLluDa(I(*?@9AB+lhDp@0y zp&J0u1Vw=-=QlDT&;7$fHbk;16CLJ}Xr@*d7L}%yenZNz+Z1Uj&tpSrt8Aeo@r{z1 zjbgF`B?7t;ZGLD94Ve3GZ?KVzQtphb80V9h8aj12@K9mQ2z-*?~?IWstOK`&(&+x*y7QQdNJ{ zFyBa%#5G!5^kIhibx=+wG=rkccuNnFf~lo<`0zei$(!O8@`NT8^Zw8Uz$G54DBGL2)JH0^pj}Su-Z8att z4tHx2>#ulLUa*Uedx=2!*4QPJ`2(Rgi$(wf@pvPz<>>3|LkPk`&G=R8zX}yhU&u39 z>;ID|do%k_wCOzojnw8no3$gqmV9*m$ma;Nt`cM8_eVuvyR{CiF6W=-8BoAv^Oim( z$dv?~k37Gmvu}i+&RA$5hwBVxDpcf~_B`0BT$JJaY_woQT>%&{dTD;>E+t95XaT?R zM|BvnPHJp~q#^zpouaHH%>vk;v)PadZ62uX4V-OC4rHVUZ(LG z&^*0rba^|pGS%sVe~W+a1HMrG=B)$R2!g^c18c(Ji2*32`x=)2uX*$sS#d9%<5<4X{=Ks$bvPm+algBiu^qsXgKVEK`ux3ypO* z=bB4vBvKXs&To(P<#5dd6XEc&=ORp>!$tRQUvCK`imcQ^4x4=YpM!<;v?8tENaGe@ zwZ!93HP|Jsp}t$QdKi)E*S^8>Lh=mDHCB%k9v8o}T)ZBHtiLCHT=kd73%WF`Ov8ke z_}LUDOF-aIU}*TQPi5V!5n4H&C)qAV=<}nHUqNCpK z55E_OHnf<$DjjQ)EYN_fhqWVj=q&BkV+Hoe9v=dG0UK`UWVvve->d@rkZg56nu=uY zXj9#*;D{L>?%|xYsJ))XJt(h3%s_62Vy>N1d=k4Va-2d&(pvM#F4 z{k3Rr9=u`xwP}2_6X=cpojSeEaIUR$$rupzi@up+Eg5{h(7lcKnjA!n<060812lM# zwTY@9^Kg{6al*)`rr=#1IT;xvpf*Lo2mtCs(B4fJMDZTcz0iJ4$*}S+x#9FOxx>1C1o@0JurK1nZ(9aLgH_F7UIdqJ%p2>Cku(i;P|P6FE_HtzW~-!O?#1 zqi1Ggbq?v?ZTM7L|74)gJ>&hxA`LMAn6py*JP9@sf_OUPhd>!)L)3%EjPau-W&t79 zsxWl#!k=ZT8My9&Qbzdj#Ar&(l}u^Vqd(3@mkG+^?f%+;4ZGwRD=I#f;kg@xTsOC; z8b#Z8g>#pwGD@AOWj{Vrmtk}fdqTY2Ob9yKAXQIayl1^tCF+DnY+-FQq7|}wP^9c| zviKE&4J)Z4VM^6)dh!!euu&;0hti45VAX^C)O1_@*!?TtUYM2*(%*o=VRd=a>`4!U zdvLC>*|4wWEXoekouI-F1|!7qFK5R>+6L|)4_}5xt~4gTuX+TRIycNse-LsPbpRIR z<*v>qsllvWuYp~|c-8Dy7sl3>2&v2zjhWoX`Lgrj-}+*M3&zUP2eMjj!k7@4dphrN zK@fp9V@g!p+UilnFvdg2cL$?1+^z2x0#s@F3AQlR2Rxl`H?OZtl@{k^KzK2Ti2JM* zQkf)d1Awv8QbvJo0f#XrRgD}#$GN>(^l7c*E1R7n@ANlydETSZh+#Evq83^Alcy); z<%9RcxvL=ZQk!);KW^OgYM5;@RGsY?0KuZ2%2@qXHPvx})X^3@=wk4dW_%6?!5XeT z2UI`oP0&s?1tD)rG-&U=X9?hga8&8;1-OT~Gq$t<8&R^O;xR}C@uz(J+n`+lK={-p zsgvIz?cH8Mx2NuZZiU=+HhfLJ>=e=4I;E}ZcXwa$9n$)V5*c&9wNcMW zS~%5m6Rb%>m+n>f>^=@d({Jl*M-(IiuVaKQ1E`Ue6=;Aki*#PLAC^u4|5nSXrZLX> zzNK9#fdkBUPz1kYJopd4$Il0wzsFD3?V}*3$_?2*+nA9LPdW^l0hy|R`syv;G~#`p z*Jey4$6d?RBMc}uHyfH$<4erc$bt@iDn!WEtOj3x%LS49bHt1cf5M*Xe@JP{^RJhN zZ^R$ZjO1?W->F~E+^wi^cP9Pt0i8xjI4WN04_dg9rSS&yX#+OINy)wAgMFq7o3qf% zhq%{CHAjEkSU>F{r#9g85?Pm-{g43e_LOb1K5(&?)DgiWcO(Yua$42D#vur6H0cgcQL$BPU zldiUbR8m&+kJbD{hxsd6(7PKXzTN<#?)j1ZNITcII!xD98(ojL{JZeEIz;d@^5`e{ zlLG(A=n#K^WLLv}l75nZ=6`PglLX21%dg69<7!|3XKp34ciVpwWtp45{{!p)W0AD3 zJ%gHaF>19GFC7iAF*0Oola>~}tG+{7sug$GW&)PTu%>*g)r`jShBN*IYuU!SH)`Zr zZoI7&ip-nMP6Lvwe1+vjr{?_q-`^Us0EvfYBtHBTuxP-K{%0DR*UM>-{@S9uy0uJm zXLxxS_nS45KXftw#18}`$b{LE!9AHXEAM{xIxN3WY8Yrq6f;Tro;6_uKak{L6X7(# zDi{;#pp6u(Uw)J{nXCK~Z2LZY@h<4cyWdSihA8a}%6NZIu%uN3qyO_F_?v&)?YA3$ zR>YZmlj)>|VRa~LR@Jjqx$J(G{hs*y&}8a=12;5k0-ZU*qP3$t-q`l?l37@NsC^D1(k#L zhk8*Kw|r({pz9yigzeq>ETzjTpifNoqqJ7b1vbxnZA$Cao>Hlw2jh&`D|Zx{^Yxtj zY!d;|i<6XH`6wRy)>PTo{$Xjk!YUwQMT{{{NVvOU^jPQuOEP^0qg{8o4^B0NMKv0~ zZcFuNZi14ARUP33*xi zf~>+8m2yS0*T;V4baGBoi#lwOSkLVF+ND|oZQbwk#GFj?aM4WOqZ;mouof0TpmwD? z)bo;gs`0F7Ewda+9sRRmB>WJ%RITt$5VkV%#_FG%|#lG7Q8@Qcq?;$ z&(ic;V%-4EF8sM97>9etvBeX=>M^+G`+A+26LUq`vU?A^QOmKtCW-VMcj2Y4Gl~4S zH{6kr$X7OF)lX5^siZAtVOy@{2(JB zk*IgR=UXr6XvfVBHLlH~wiovWfoF&X`djsQNgV^)5H})eD(o%I0p*~xSFr#0bbNB3 zP8ig|WJb2ZOIF1-XaE^!U0FO+=P(HYs}Z@iH!XMJ&Z#*0E)CY~V%rW`79zq>1QcRy z-OY!eNNcNvAf)!)GyQSize}(LKVNSm&LcPbwcP6*+u=-#>_RL^a1sJTJ+9Fg1w5Zl z?2#5hsiL+ihz5#ky~pG-p-ey*nJ< za_)N41zKDfhL(asE>C-y@AyKE-pml3ik=RelzSLQ=}#X9cO&Cf2lr0e#CtY$7$2); zZMaZ;+5C*K42tKbQ#a%M}8xnAq$?z7muxd&?fE1j^J41Zv2^tH=~x>_UYuO zG?6a}cHBETm z@^DN!$9=_2?cw?w1({ETKZ(G+>9gKe%JV9d#+5yN3EJhj!4S-|GK7UdRH(kS{}#hk zaogB|#~kOeVt$|EcKXu2<)|Fa$NHSjLxvA=0gBJSnsH6_RwU2tTt;u$=MLDGKCcTy z6(y;`GkcE4P2B!E=8~D8{9OrpqsuIjD@8MFJZ+6~l4ir9%moPdHWt+-P)d*{0(`Ue zSMQeLWUdo@!jtG)JcvSE6;su59hVi{08wBt2Oz@ePUu}a>zl{t3-m&I&Qh<6CwM}v zjdF_Bo2X#@6%wRk5rsNny0y^Ki%Q3x`v$J-q>d+Q2qw#GUI-ob$cel^ttX|$u7AY{ z>+ZjV=cUMc?UHG)A}kJ8--=Ph8CUGN3(~&}4E|mE1zEPE-1`^rJW#N^GwoK#({B%U zuqeRGCa{9`7d7)Na4tr+w_+)4h(J5H7?6`zgp!=f9;x6llJbm(ORI&x*?{h6^_)z5lu&#u;6=L=-)yEW5s zdJXK6?4LGIJoF&E1*Nu+pC;TYJdam^sXOrFz3b^_f^T|y8v+|u0+hNGzin*%ERr8K z+>xYG$@|m2o`f^W>F^&(e*BOz?}a&P#nuPiD|MV>Ab9-|{z2Pos%L34f4r7Fe;;<` zL=0W+jnp9WmJJiW){L(+u{~wwgI%ER*_tC%}i` zQ*?AidGXWl^#$QmYb7`RBlLbfcax>hn8dXk9!+2xcVa#yDu^uE_tSu zm9@$>58t_L%eg8+h92MHEh#~1=Bs)ZOk^2)Rp8!v0iAP{KwS5U9RFY7XUg^W!yN*V zT77;97PDN7oedt>4qtxHu=jEY7pZ^?>!%_<@Qvu;&WyZ+)*8_{hwdZbs0lX#E*@KS zW6Ee6o6~9N9e(wtstqj%+nc`U1hE#L3!8g;YX=KD>du#m(}5of~RG!CqEezfwKv?sLTw%=Xc8t2It)OI^XqmIO#;Em~B>{ML0;Jvmo ze(jZv9kMyQMl^4_)TCuxT;Eq+9`~#MDW&X0C9n0}TT*u^x<7esv@_H_r*{_KnJWL` zcMr)%19S?l{|YOSX}9pnNvqGFPYfQfHE>h{bMdDm>d^NY-BHycYm~NwwQc-Pg?7N- z1i!+X8zUtKIbLYDmc+p~OCS2LW@EjYFZfaqkgT$6b-{)osUH)oU))3oxX&6YAF-@7 znRc8|gicSbOM5ym5`m-Jstabo!p!(%rVqB)nN8OvzY<0s9-i)~Zz@V8j7=&IF8D<7 zfVbE!Ef-u{A{9zrv%)i-RGc_jJQRy-jFzDx)n6%Su6wgC`HLpm==TKAEgeH`W$_iT zU-7C|PaXxtEZu0SK7oviz((>KY3q%rD_@3b(>?_6JW z)anQ&JvV-~q4ch&pPM8-a+rUfQg|U#;R|#?FNpQQ4Z|u=W*7kfk{SGp^55#Y4F*@1 zE4QRl+?jxv!!gJ@jR8{;;e9YtYskdV>9>TV2Y1YJ|#yfi3HzZ{5@>1`EmCpUT zOv{KbCiue^-SGvgKn2f@z_KUJc~Va0r*S&!G5V@$%|K|N*Pve>wWoNpw5`ekbCLIJJxig16-=tS*rM$=kO@cioV`L-7*qA=j4b!_vq)XK8)$nc3l z@V)`?p3CX^($6@QoH57>nwoe?OFP@v+EvT4+)t`t+S>Y7m`1GQR8e@{CU86B&FnWL zW|@d^ij=T0l!44e=&gf=y&!m`ucN@{BG*AMm!ekZ9Q$>pnGqC3kZiob^0$?a^((w| zIb1E29jeP7-wngww|30+6DJiXOia*>P60}4ho3z|Tc_nWr9w_tIkZgqBZo4Ge zp!;{73&6Jc0xnWce_L=-NlCu9>$n@dAy}K;-tvo{Q<-$*^|Q*)nt7aqaqRW;d09Cn z>cXhobEW7zT_Uv%O%2s&I{3NO`PnCvZb}Cn@IXppMs1Z!dXpDWX`6~& zX|4$=$dOSNUd7)O5vU!b?VKqL%qSymKcIrG{xhD~-rm_R9MkAVOT?FP^>I05bhnc$ zt2u*kV0ip%M1kpfrBWa+>@to0(Lyv|UdKXe!{h0TMPugaRHJ$tDPBXh9y9g?2Gszc zzt90erm%oA?mzTS1`!8+jlxrmAiJ1%lobQl&u!V6#!5N*OC`bF|4f0bS3Kf)9nfYt zE;P(wS}w*Yets_#Y>+OUE%l*nNZp%Y(xsj-DILtU>S4cYm6Ki*FoD;T-WTcMNbm!|5t2;$3M`=Mx3jt(Pk{ z^;f+{sW_RTZ9fX3MOEc#;Y#Mh|EFk(8;D(a+C>F5p61Z=u{hYbY3wKl!FcKi6DG)er(% zwo#0C0Di?~$7?#!6nl$S_BFPNLQc5U+ioxNr8WvnEhx_ap@Y*jH=qa|@bo%=sj{#W zW?obm>bavP)_^u~^@|C3_^05UGoK|z%ufU$duLmgu$IK0-y~035qYKmp{RVq^Y2i# z=7+q}d3NtM#;`0ZVqe;&mGO^kx*}8Je$VbC=kSY$(q?Z?w-P?c0Yy4Sy(#C)6!wHVC<-DACyb1(Sa0777`CsM6$i7v(b%hGJN!d-35wO; z6LlK0Ostiwi&|Me{_7Z_MBiw4yFNc)qSbJOe;%H!=cd7*9sXySjNXM_wT-P`>87_BZ}$V5?WGg) z3y(g`-qTxFej_-J(*X=tq$TwhuUc)k%||#qn}9h~Y+Xnng=W=g=`UWZ08T5K8>d+n zvVtV5zKNyi7RdKs98$i5+0lzKNtz#<5M9pR8`#n&GbK~-tqn7=*Q)-Yv@7{GRBaRV zw|?u?tKv&jZt3m{yHD|94TW)iiq38JCmUXp(-553mg`q`{|-)bI9VHCa*)^NZkjKT zwNY7ayz}&7MHHYuR>=}|cH8Eb-C0aVq0z4KcKh_My%^$q#io(qSMn)J7mc-*qcdj^ z=8Xeq?ygDNua)P1Z^5nba9y^nxe)7_s8o6sd^-KA&7IlwVa_v3CbkG=7LRN_dWe=#M0RQe@E z+ic1gZT@@HDD=6t_&Q%6Gh%OB?F^Aa8uK>3dYxxi2KEWE?ANk2MgzGbKr~xht{ZDP zhr<++7P~mcD~&4-d)_2W)Gy(3)XHb;MH=@H#qG*zg)XO@)02Fm;!$;h{~>) z26xWNIBo@Sia9ZG)FHx(@&a+5pJ#^fJZrWwcc#Gfk~OI|0fhnjHjBF9xntDR@X!3? zmKv1a;pl~WO2SG0XYnVn4;un8-Q;fCnr_<|F`sggGfodU_K?!T__hc{62< zZSHi-zFyA7MQ66YmvSOUIJ28YeJXO!7!Vzz?=801sy}?YK!q+O@IABcS8+3&MPCf&9JNbd5*@MvC0d7iYxaH2wQQs3{Cz(I^qd!RQX##Yam z_RIgRvas#{)iRQCN5}?FBex=A4)u|C z5_fa@WIuLJiX*-Bsz9N}y0tMz(yz(VuW-H>I`3PoAK3s=61C9UmhI~JRrxW`EXF##qsgp5l*W*68JbKkH)+i&~ zS#;7?*w8dkwqUjM;h5E8t*uvy>F@=5RSkoE-q%?Z z>D;=^=U318iiNgn5eG5T_vvSx@6&^dQ!eJ3?zog1H;csNE>b*LFe7U|E3RxyVF#v~ zNuidlGae{uJoVNK=T z+bHUcWmFi)83k!Nj-XPcw@@rISZE3=DoqT8me2wTq3Vb*jue#|AfO_k0zq0r2muuh zHH02W6_G?rKw3iQ?BJ;A_&opjJ>@#*I(+a;+n8-MS*Jv?coZ#z>r5vYY?p@^F zk;%Q!w%ugc{P?xOY$ z-K84VViuDrOuQHNg6W-ZA7KoW?(Z$5I2t+dmdYn4Q@OFB?!QQcK>IUn5YFN{rnEwz zken_%S7jfUs-5aQ{r2!fUNRwvhYnd^$H?VXwnOHZDBMe9bf>{NzWK$--W?w<@!z`` z2UK>cxy9K_p`QwIQ6R~jD=d$+KsiEndzo()`y?NIIECGme!q88bvouDhZ5W0(&BvO ziVekJERgX2IwD6xip)KMVsByiwTBnkr_nSS!H$jjUSHnN{qLkTH!bOi!S~NS=JCi3 zi)KW{=H2?oa{~QP8P~gnJvDjy4Pi8+9S+4B`>tz{5WndPNruapwl-m7VseN@Qh)hk zhpPs8`=*O-s2wWCv>wl?dRH$0Xe4N^%B4W|zJ1?x)7vC!vC7W)F6!%rwGCdnk{t(Y zka58g1pgG>4ST_6F%UiB+n(j*V-XAF3yy!v`(#WO59h{5Y%PG!G9CAm z)5r4$JL4Frzqpm4>TYHgM=pJ~IvixIyFHvp@Sfx~;ZgXaqIM{9VTt0Eui;rM^y5R| zoTRbDWV4P#XHxmem!ziAntQ;zmQL7ug+GvL;r>>QLAFX=Ae#3L67E8}H!rPZylpD7UbUz>6EfyHIp}k+$O{x?VTEA^*9%cR7 zW~fa)4S}7VACN?IfkBXUAVciuamBBGA&P+ zJ*B9q6xTSKypGj2Nk1Ok`6%~9UTF2$^Q!mEe{B!1Yi z8-3FW)riUPciEa9#Z^?Rrl|4yvv%@rmn9k}~D69GSy58b_MHUC0+*(la2SDO9%kHxw z>tv~=N-3fBuNhwPA)H?Ey6ttnUn$GTt7_Y4F8cOt{wYBW|1&F@zGZ)F%rrx6{$={J z)6@xoV*^;;JSeVT-ykVhW9v{f{59p|O>=ZHL3Zj++B%~&lwUKuinc~;vE#P}R4 zbR*k>Uek*5F-cNRXrJXOPIcmFoDk9DK)AI7Ld-dD8pbuRul86%6>PB=-hXzP*ExXF zl#OxR;}g}QIX1XKc9FP#q356}QF#BaEuQ=;UMl|%q69(=8zpaF`Z?neukOj%tdLwX z_x@p1*7)^6I0ybzTDe$|(^Ia7mxHEQAaFJ=lEEOzI=GrvyH`Tn!9=6HUU6_7KkyQs zHcV}|S%)sWXmZF0qO}yrd7kIeB&_T7GLelx0R)VxXrv2f@M@u zVU+yvZ@l8oz?nO{6bdFZW|zklj*{N82efCtmpNQ znC`O&Cb=;XY@y@D`23w0(9QQ7()D?F*s~TS%Lix9v8MF^oph-L?B&rBZ$)KFcA17$ z?=j*GyPI@XSy16`wd*nI?fx`pniV(jn%sxUNL|!qcmaDg`FklQw|8`Udiazrqs@iE ze}|U!tZ7<2TUkol`^gOH)&1Z`I3>O)%3`!kcghMjeLWZG6hO@Nu zX$4rF{LZ=e3iZ`R^3C_P3xYA5;Op~pH1FhJA41(g{lzyHRoo@G`?gP9_j|~X9#{Vs0%Dca)SeS{l+7kJ^}g;}Q}ZZB(3Xu*_aOI5(2FgN17UzvAG?@&R+ zZ-x21p*fbPW*gp4ligKZ{HV%E2LBGw=~m6H{|g!kVf#*vH1229pOI&R=wzaOTOKbFDs;vL$F%BV++ySuh}oZ z5SH`x|Jp*{aRFoJ69YUhxKP7uXd_|(qXs*mA;>R6a$IKR_FTemp_Scl_6UIS78i< z9?3$~Gvk=gpSGfYiM>Jylfq168+CYs5+|ZV>N-jPM`MGo z_z&M*3A}h2Cj?S0k}shNVQa;p3G@d_BG(D3l3^zSof93tryzlUny?Cc%>OW&rG~ENr}p}h?;!0)0WCvUgE}PXLDogy3Xs4OAcQN_>-liOHKZ`w567%SaVwjI%VJziY4$ z&Q@BtKU;ZS&o0VslUI5QkveB>dHXaU;X1Qoh;+?Y#z%WI)Z+s~23*~>tIK4~kkn%l zIjD0)jqbLBq1tO|;_30Y%pB5q9MU{E>}ZzfF|bCJlsDtN-F=I4*yMdw+A+I2de6Jc zwp4Dx)**00xW@m&0-@?F>Mu7i(;CvfDq76ED*kk~;fxy$ZmEdz(F(x$L7U8VFx^;_ zJfIR#%gKp+!PWI{UMr4P&OeZo;$GL96b~MWTMRKBsP2lj7} zvzpV_YKG>4+nHSBvJ-a(Z5O9%<1m|PXEYnxkUl( zRAn0DaTQBc+49AiP>UA?ZX!1$EbUw^x{^0>FDj_*dhM-T*r3rbxdkITOlY)yhe?oX zcK5x0Z98O!JJN!K1;Rp34eom|F2UQoutDNLH!ewbPxBpmtG;J6)6p%*Lr&+ObPCsj zKSv{b@52WWGp8!!?w5GlOnc4{Fmnd6tFJs?_7kKsqMnR=tn8*R&m9HejS=&*=5kqg z)wsBHoAem=_z4oGk+G8G_r<}N?vO%nrSx2RX;)8VJmN`eu#yY>+kT|$-@y1w9g{le za0^F-nc7i#_SySv98Mj&OzdK*KJ7{wr{1TTn%ckAX+54ojYDzJ;%UPkSJGV=sAKQlOigjM&c?-J&Ih6Z)lj1Iun}5U&nddj()`XR& z+8|vkyBBx#fJ#XP=#g{~I>?P(>m?cAWkv0o_lxNiZNP@FH{hu{=FVfOhp^oVGV^@z zKpn1RNn|lx<5)$TeoBnf0i$T$IRjlxUhGK-D0gdTi^YD$>*>2jPZY6EP_KH`_2N?w zWVHjZc2}~*;I3P>E!hS|#Y-1zWZ_)IYSGF5K}ybTqg{(-^LzW-y~z!pO#%cM9_c^t zf-{3?gjc*)SR8p6k&*2-Y7M4?;`ofv`cTGXaWF9vzf!$}UB5~yL&mRo&6q=69OqJ& zOH!&;NDI_u)FfRPYBf0|OP3H0LN@+qqEQqVg^-SauK#t}T9CCX{rz)*tz1h^G- zsWK;Lux1BEu)N^53{6Q+=qjg~m(1EYm?Z=hOwr39mK==k%{dXf-w%1(z`t6v`nLTEiXpMPlZJAi?o-UBBtc0<&u_ie3k|8 z7dT6`5j~+pJHz)da^F%<0&ze38I$B9#0cS`fA?sS(LB`0{B98_8H?yjdAL+ZK6ue# z8r?)gB~F+R(dcaiy39qoe0aa^`im&((#BbY^?_x4#QO~)yvt#O3!%N7V9xvtuZtk3 zW`Vtn@2RMg5|C{3U0uuY=qhV`ZIX?&kxjKmy-{}0K>XXSQ@wwnJD&M-(=GLQvwnf(!VpGrZ=U2-X~>3ASSAK>H^X(y51OPIo$;cisqYMKzjT0w*^Rl z8o3CP>Sc;5@P24}=y8H3_&hFIS1q0WQojSFma9T2v#5_%S5L6JqRc1s`NY)LzB+CJ)vWh#{Dgr%WfHT^xL(6ybr8(%kwH69M`cwBrb z(>z~}a`j0;T;6E1nWt5tO#(`;6b7M_lUjGV|4lS>_;R1J$x};%KWEhf}dHi6_ zd?7(22mUT6;3UlgYXRi)Te@fwS+pwW@K$1yA-8G&^p+v5QkIWb&WL!~`>>dS9PlOu zEa&*L3~f*;KFy2~`8T>#KO-ZmI(Mo~7n!e)m_BMZzI&>l=h*))%MQo39N@1cFn>Or zetJNTGKo7yj^&!>5h+UQUUCxYA$fTeQuMgm@sZ)qoj-V_3kW7a#=6Em4F`=2;Psx{ zFLI12&3V&F$!&Vp3GUoB?_Qh%0T4+SG}H7ivN~rn>!9g-&P#jR)+M{~_Qi(%cu(KP zNb|X;SuUOI3L82T)+0kR)*I)~P8I8)txU`famG<^=^hTwl!QnZG&xT)rcT1Ar z014Rqv^<3_^TM|sUZ;?auxPrmyILs-VTYrjTbddfC`QH9p2#>pb06lGk78b#(RN5k zwFgcl@DF=626Jf1X99^2Di?dC%Qr0TaCJgl_KgnQ;4)OuoH9L@RaZ@%*o(SRJTqD5 zWFO%h++Kd4&`KC+*HLs+uvK8x@>auVNV-)i% zg5i(Bno;Z+FZ1&XNl6VDo0k2JZ=Z}6Pfp@J^H2~^I0`&Lq$fl0{Pb@DqI`(;)&@wlb8twF1pHqHq>vzXwC;yZR7^sa8 zc{QQmZ}^D8yQVuDm#K~bmDLp<8J#}U*pxQo?hBs9Issl;6x;(O_HTR6_9e6^CO-yt zPrCtgQ+&Xl{T2f&FDxmJFN@gwuugEr2{YTR7s~Or*LY3xm*%%0vTA^Gh;XHFwWsZc zAYtX$avFOvj6)l^D1C@U>|k1B^0Msm%7aHe$|nORGt5E;b9iaXwCQEs>|P|JG$sq( zlok9oOVHQ^ePZA0v_$68mfq;#<`r^Y^1knmZBPR9AmB1g5E`1)R-9wuVdomaelph4RZTw~VeHT@!{yeSMVOjT z*K!7v`{eE{=>+X(cy3x{GZ+C?7f9mwMH^PjOuY*LThcActAj;u=bb!8gV!;e(!n@8 zC=xUn5$kn`pC42(K8s@p9gH-EMP%{33c;4M<4LIF7!5XaLlE zVKJ`Qqj`U_i@aVBzvnSf>^!fEiz(8r3ii%rbN`6aMat=;N?~D-jC{(bnRp{a^x>1~ z&G%ClF{76sd6f;E(@Au?`ad}!;=&E>RX1fvwh%F+o$sTnq#&R~pDbbf*_WJC#vRaT z9Fs7kql#W0uM1a}%qd^;pB!>puu7u=M#5&(X6bCJ#TQhaq6PVC!t69YG{j_#kjI$3 zN!FF@%S#6#y|t}O@GUjd0r@XwmIV?^NSG6+XQ4n7t&srvIf6%Byun@Gjyz7A^GS1> z8RoF77J4{a18aJc&sBD%xcs%xCp1Nk@z{fsga+em`n?7{k8y4LO9G|~{XK2t>07Ok zXcAOBFfJHt04bP${`VNQJ%>3uo!YKn6|uZ@FXljskP$I9Rv07LStD6gzwIoSz{^d- z9R9+qxzQ|3S6L(WtnZT#D>Djvn|Xx&Cx~&B$Uxd%OluBHsd?EV7=7)tSK@C7p(;D0 zsiS4OklSKpYZ{Lq)e_Pdc$walnN3~iNTE*4+`ahp(&eG$&QJx(k*=)aIZ}H>mg0qRBII?mSedGEJp&HO&utVz|Pnk+Be%UEI8aiDQr&-_Qn{biRL z(rn7Ub z*LPj4UF*#ty$?f`z2MxNYoErE`2J)mn z*eVsjLWuj`GE{o8_MSmE4yAK%+B=b0P`Z28_L@@GXOcB+I=_pIss0}lIAsBG+%dh)mDB1D_t7v$XW`Re3u^B-{V^#CX@w z2j80^NLOY%wwqDEdkS7f%``Qomwd5dY{^~MJ=M`28U3DiB({O}y!T|ph9V>^hH{cS zE%#73{FZBE5pp`16qyqLgU<^n@;3pxb{Y z>UnwJUy~IEi$Qj!jxuIrl*vRwC6m@f+dANQVS4^W#u7IJUJeasUiUlb0L$_C6;13K z)*GLbm3G3i+9lVH;*eQcWj3L(V+=*g<0e`TE^{-D-RTdjnf5AE^X|F0>U=i8d9~B& z_jlHT7eC+8&fwK_P)#Mgi&uUu`2i=hBj9B%+wZ5_Z?DAs_;QMAW%jNK{j1Mkq3Kw2 zHM<+ek#mDJPCa;eKlQ0{Xe?f|T#e_k~P4h=_KTb_zo&YdZU3)ix!v37*G>Qqin zyJKGvikj^JUo-*5UKCce)S@4cF36NGwHL=trzBeN@(f2^GWsf7-3&658z$9ts*e!& zg8xD}Wc8)}-A|1v+WU68X`0L*z8C>-ButdnZ3UTq7DZ7P>qn}l+RZjP{H?|aOy=|o zvRaRKxEwjI+zk?}xp}DL{%i1obtXINA1?m({1O8C;`X zEFA+yk4$xIMcuJp+KYZi{79hnu6#Ea^9|t?<;qf(7t_U#x(48%xZ}SuVNZ2_Q_-pE zrD3&fiSL66xEIb?&Z!6wOmQ)<5doH!M#3_{a9yx5x6Do{giXVBXUS4kbk93d6`ep& zl~#$gRDc58Ar~0*6w7Y$qT=|%Bv6znIBqi6cDu-58i?rZfWBS(6Sz%B=}6XQf$hN! zUJ^`|$YI9P&lQEk8*0_MN5%Vq%QlH!M>#pq%2MEs}psEeFCJC(0#3aoaql9s3U*18<%lyu0NDI z@Boo79$_*&?6e%Lmt4HmGPcmdO|O|vug#W%4diDu?mYA38Ld;QtPRovW*&-6pBl(3 zyXdL(`p?$HGR)=m1<;=oP388dZVoi1v-Y$P-+O6FI|6d5Q!K13YqWQp%%$`PvuOby zIW(29us=?8#0_0|9THfCwkj{GS&9=R4*xN5HrzmeZ=U{5j~DG7sBS;MQAFSLDSAmb zZz=`k7BSM0#GjLrMnW=3B~PR$H!M<9v{tw)gb7{|P8SDE z&%D09x#Z}a!PQo*v)fBasMJspR_xT>6IJR($-KmD?RT$#1dueN(fBk3{7369!D1;$x%{$scvrn`g}e z`el#Xq`he3q7ZOTR><{VqXnWOh^OFWU= z|Li87k0~2=-3d)xdsnV)=H*=1)egKz;KM8Prny@K7S5VM|dxe#U|aRY&j zDRkW6?48?k@<7q;%yi+1*O?&J`l7KPq@w1`0)eeB!qJ`=DrRm0(JIf`b12>M_XkC$ zKy_nmKUbk19qS@zJA5KtKH^o#GQ0m^3aCbEF$XLg!#ab>YOhG}``giOlv%oHl>r=s z0lG@;kr{$#9lP+zb%X+TooMo&17`hEn4FIa5^y8=@z=)@M0OtcLBFMdMD$ZMl!EBMH{7g0VM4bwyKN9l@RB?^J4u=DRwd{U$zY(6jOT zx8IR$T2nRKv#2q^9+#yO14EAm#gFMSf)@qTm9K-@n?EXnn@Y~OkjSYDFWF4c zcG+e`pALXZ@NiBZTZ5^gPTST)=Gho-^77>uQ&VsX34~9R7CAGav*)QsVcCR09^2ia zY4bpV_lb~7R7?2{ED-0km07#9=k|uB^EN#WqK|H_4)5E6V(ejOOEd}snYQRpn|_&s zYksO*=aq41v^mhF8H!io@aaNo(GFCpgW9v+DqdQi57Tp$sWfo>MwK0<&`wppG;H8s zmZ-=4BJchul zGdASS3&-3#a_r^4wt4lKjC!NW@2i>^0d9b!!GVo(C$JkQn+0b1b`61c6`)L)OroKb z;KKUSu+wud6^+{r0Z*&X=SUvvluc&iOu$N!znJnLAC-&WzGj4vqCsLln%|`=@SVJ* z5L)3Co>ZR>BZ4m%dg~J1Zo6jmtGq3*tj^?ngK-j;|H1Lu1!BO495mtKZovQyLoYQL z*07z9Zi^uR^_g}J=en0K(=V_b9hodLRQ_R=h%fYC&Xb-@Y1kfnmb|GZH=RFS_?Bc> zpVI&#CL!=y-Zy%UPpq(v{_Ck{Q0nW0%W7%GH+#ihy^UCge4jn|smBn|=xxq3sC>bH z_G+qnLgZKN7Q?UsngckQ=+`9JH=5L*EHCy1yA z#p{EsLfFnbQegq;7f>47D^nea){6O_`y`x!as11*u`I;TL*@(g^$k4Z9wwBgBIJ_2 zeIh?`2zw{(o3E_*6ZH<*_MdG|Yk=B&&<~!d?(U{|oH9OW&fqq)O{b5)!wXlqxpqLS zMJc&rukWpL48MpZKc3#f=uJKXGVquSc}4%jI3Ddl-;&37#+9y+GnA~d3cm2XI)iTk zEY9}vX>3fdn_`2v@QHcF4MzHV_fddVn7vC7w2szeG|4uD87j&L1*l-n`+bP}e6Dyr>9!S>=1-U7psVYsI3;A6^wt_{!?H zYk?lu5|Kq0gBJXprdx-j;H!XJSf>8<>$W~47+w{(H491Z|eih2%N15d}n39cd&p0E5B!r;cZIBH6U^hhX_6SKL@er^#Rih*?p<*WX9czE`19ih{U_&?V@05Y z!ACjywKL~Q`h$W{^Yx3?(uO{7B`^}N|Db>a$)!0n0xgkkHgkA$J86%QT7g@v=04UR zf`JX7W^e2zXiBwa@4=c=8@Zs{g0Xl$Dkp2CD&~Lsk}CzF1urb^0FQy5hezw=xc|Bt zG6Rr6o$N5uh<9+Rjx8gZ&%?=RYs2`NDw=mmKQnH2W~w<>F%AG^kCqFjLkqInt76JU zci_J`MD36e*Ukw@g%IG9FHLY?_#1M_Eh-6-xGd-Ya!Z7vJ0-7N9ePMe8f)m6Y1M6Y zmT{QvsvuUE5F6&O0t1zpY)q5){#U38pe8br=L%&4U%R~OIHtZbJ4A|X%^52BoEHI{ zW?e?x$N=S1b15U0G(I^HLN4}+`=e#I@D3^_Y$_%qmvq^nuprj?jUGIb)qjrE-~CXc zrHL*xl36r2!rI!(xaobM#fFQ*0W;k1Fkm+UH;Sj|~AUEfX-z$hG-@>w*Yg-`~$jUZD;YTZQ<@ z00^B_wO=-&FF=@-ivJD_3CXUO*AZG;rH6!Y*#O`Fb`?>Z8sP6UilwJk8ipS<992Tv zbqvQ*&AOmezI16UHtrkm$Mz!XB*riT1jdTem%H8oIWoiosHzxlNS}h3fNCEp7!BK5 z&Ywh3W5BpJg-ZZGs_0{@G|*F^O$d`oV&1pcD%OW%QrXy>Wd({fB(`7-RA!>pQN#?C zU+*4W)ydnZ?u|3)UFeCG_cGQ$acF=<&mhslUjH}^&MKQQHYyyRyR`V=(V3VF5~8MseDB7EFnipLbCPB}c28nXQmAimgJP#20iX%FpmQEk@6w zdBjGKi}AxCfO(EjQ~@x_`?5+Y$(*gY;!=z@K+UIC5+;wy;kwKDIHUrWruX~&Jn(Q1b&ZD(F;jjx|6RJa~u>o!&LVyWc zAg`JjgY*F!thO!%DN8t{`7g{zERUsUE%s)?jF)Grb&1*{BOvGlx6jj`KWc-QNj<%z zVG)cRVJ80FeEYD&;F1dS)tK`wi#hKz5reWk(ijw9<&VTS3rirNJKnR^<81ComzGr^ zW}CdE`#@bV80E05(mknOYV>X!puI#J{29P|bG4?Fq*JccFVkT)rh{a~mDIeNA0^?o z`aG(|P8}R8({KGo7S!MEGds^osXb3Y2yhcgZQ(`pOM-W!(--6_ zwPO23{VD$a72jqZ`;823h7y>h!x${KIwUnz46N-F=ctfocR)pp2KD*W0bI-%l|69@ zPCtw-zX<{;*%x-rR(t%Q(F>5Le|>yJ(BuOb94&(FwJ(B!R6jIgFmLEat`*|L*rx`u z!h=TIGhoy^jk2G=o;q+HOC>qIru&O>J}`W)+Syc?$T@~R0Dhqn5PUjRl&fa{$11Td z!b5f1fYUtOtW8~cb;XlU2LpKgm1~-;STh1>gtBk^ADr&xG2kUVVPC#vYsw}FvE}E< zg&T)L@1ut8IP}oBd*!7LEQ>U|XB=QOaFuf%m3P(p!7Jh7I-1y56hubE7DM15cCVIL z->^JvH5rhyRa24a38C{%sUuHh$zzkv+9-Bq&{xjQ3}wF z?_cy&Mg|AVAZz2(5^(LkH~DeLJ0yoQatGJFY4L_CJ)))L#HY47I`Q>q#(#(iW&52Q zo)6v&jx%)UjaR5Vob3SDT`)$@2`yTIbqA%JE>@bm&YmA+wg?)_#Oblo zMt7@oVbZRU?D*}u^@OlHKAXmKKV=Ufpc zXd}S;_37SyosL+Z*<9LOW?sH>i*BXytuvqYYq8Qx*L-gSDqreU&!N7$Cr^#^n~u{a z>qTEHhIv59TByfD=R zS1W18OSSd@(c;UEl2iP#2=bP|S7k_k#booe?*H%^$1X#~vrY3DGqju=v{vH6Y}J9N z11BXwm|oc6FGJZ`e8jm|m)*MVNZ01}TS>;`Ti2|#2T8c8pm$p5DQQ-^$qe0QnXab6 z+m+sA!+H!>K~K=tfunzP)m8h-U5zb7;M+-QX4GxBA%oCK08re zgpK{vAFr8cg-Jln)} z$K(cn#qbbdIyt)m%2@T2Cn{3tt1~e#S#eQV)t_TJW+l^W^x?!p+BF)$J1+R^qw6XX zIYHyEc5bUY>#$>0sw=zYPbrW*$Q@V9pTU8R5P5*Oc^3CYWJm*ah&1)n(Uf1mB`iNU z_#!K0m30C1i227^`C4s(aq?_0OCP4Yw;n5OA2)X5DFGQwXNE{h@YK5VCM?Iw3$wBp zWxxAY#76|VuyQA9Z5y-BJB*?zxZ%kpVqqVmZVk{s*6c%jqg8{D!S?QGSuh3=8pbt8 zw69d(Qp;3qM+n8or3q5MYaytBmnZLOoao_HNb*Nw&MzOnjQnOiNe^1el4FtX^qv!U zRUws3GL_PAPf2Ydv5w2Fpbudif3(1pgNk})NAGAes79>$!+nFiyP=Ug{^gVE`2s;U zf?PO~A^rOAUb!ZTFswzc)*y&s1TY(KX%>(`ltO8I8c6s<-A0xDUoW>`4gv>22Jz|q z(B8;0s;^8_9GZU{0<&7&gJ)g74D@0ZbWq?9bWu5#G}pucdNJ*OftkB|pO`-H@`{$)IV(@KkKIB7l! z;ItAGiMfVJ>7?l6+q*mS;YV$*>)r7@@S=zR7e&< z)a1!b1k7Bz9+pq|1v%8)Wonb8$=vsikmfpoxX7+F8t*ooJduhF#uJ8->0zwPw~sdl zuMbmz(c=Q?;XV3zgK)P{p;RjWxupP3>ENTBE85PYYJuJz`~J0rdVuL1*$Ity;OAux z=NJj6V!7Rz5Rz6T*+pazn0-B~6-_+?l?V^Zz`)AT|9}SAgmiqG=*VM#T_xurfHC(| zgqyU(Z2;KTvVy1D0m;*1uTQVmmA482wBXOkUTiiht(G}4e{G(%bs3z(TWpdrD^n*E z=+q2=q*pBFTYi6=A?5xB_VUwgTFx%QxJi!tyF-UFF745Lx)XxSi&byZC-;EdQmH@D z07}S_)ov5y12Bt_rF6*rJ>Y7L7%kdou3mCOV*?CFZBqm;{4cqmUDJ=zQ_&EQ6)&Xr z#^t_eJ21vAV>6qx7+X`Wjdab*rx9V{J_+^_Klz=uEWst{6tYgEVi7?!S9)d5wyjWV z{T%L~f_C$DFHPL|d-fpE+|AQg--OJmPo}7OInq$q;f`BdV;SWg!?li_o1(ynJuyf9 zJ0@(**u;a^pF`LT13)Z7sDsro!Iy6Vlt$Q9FU7n7cr-5``U3U%5HlWj&*Yv~mbds@ zSS!1S3gpo>vYfq+wlgU3KzpgKP0=R_mpzF%*B`vN3J11R5_B0u`I@kXp7{cEcU^Ou zX}lU_xKxAe*c*A<)<9V7mlvkcFK|sTe))D*Qkrv*bw~YW)pWGD##6rq^mt%oRXBlN z5oR>(W2tW&F8KGDz78@2NK8Sm02HM3{q`$lmvb8W$!i)?r^+mgGD0#{+@ch;ll1Ru zbUV_#4U9SAe-6!*TrZZYrqU&kPjm=E7UN@yzAfWVZFSOt$Vx8GPRVWvF4E?upQ0;y zEr5?W^8Ko#_*LZa1|Mpr^V^*=%Uk?MQL@&IQ!kavQ|LI*+xXDa)==F&py~@c6lv*Nk)C(ssUqbF04_{!j2B@6 zg1f8K%$It}C#zX-knauGb&KnFt|3+3;U^>(3n~$qYlU~DZ^u{BtL zB3YBiR02UDRDJpLNaaJPrH}0?(n1oJ{69q`zB&M3K~1VGD1MnH4iNw%HT%~qy;tlE z0*GuC7Ls_&B_@v!=L@Q{nG=nyyS*dnkJXZUOnvM<8A)b!dgpP+{YO0&jf4vo32^Z` z?=9iSbq0@_XU0DqeO(pIkBiyUoZmDFw;s+ujSVuy1I1f+0QBgYcu!yn7X|RGAnx_n! zHLGeh0LV8_o}&!XzvTffS(8dasVTJ7_00J5lgYc8Rc!YMDJ)l7wl&HMYu&_3I(Xi|@-f z;p-XV<8plQv0>n_@3#5~5{vxY|E**Qk;q(~OA&RkYUa(YjSf##Z>`Sh68$&ws-Xec zCWa}YyeDAWhjwZI@|HxQMA1W^bsS)J{v-9ia`5~vKMp6jqv?`N#ZVkU4ix z&O^Hv_oa_gA3}?lH?RMu0dlojphR)-39xe{ctxy(Ga!t`LW=DuP>s0ANC#T7C4cDe zwi+^#DaE9*#idwFEpU84i;;wY=#8G>5YrpXPR>u)-N#61%O9LtK1ExK7xDQRBT>4 zuLQMG1)ypWt;%Qb)~^*v2;x|0suMBWbX>Z@=;Erxhg8R!1d3qkwkBY^z<6=Jri>3g z*;da&xs<<&gVDJTdNops8SRCDNU?^=vYL$InrlZmem%XWWdxNjXNZTw>rBplBJO#izxvbF0CC^=SPm96 z0NG7NOn!tDDD`#u^RDueJJ{*Fa-h?7-8xkL*OxFc z0jMYgP}_`EYO(ZoFKRF+<;TjO|2I z_D_%=2bnTGUwHG}(jbZJUpQ3DWe<92zHf3K0h=;z_qBA^9RBvxaJP^W6v=%8GM_~3 zKo-=B&#;<6n%_#xyO|Hh!Q4Px)@D4c2vI%Y;2LCG$KKK;!)v!Y3PKwWE6QQx!|cxN zF{-g6$ys^6JhwDqeBzt_RmB4UQR%TAU4M)L+cB({Ho%T6HS>|)OxCvr>gQ{p`?`Tt z4h4si+L^<)^`mi4KOZX%11PPU!mj=}Jq54caXyeFSl@ z!vKsT^~an^F1Ga9Jcj1)nfvi|$>?u~(6DCh%8mct4aA^c*`3iI(`-YvTJOA&vc;Pa z5YBB;oCHW`*{D%YP1dJYz^mZQwWSV*ax=1hpstsWt`3?X}r)c>EOxl#YKq{`QSV`RtNV7xsF`cF4Wr zN9>;;X93N=&NEjXFe88FO0Fxi&;p;JvS5jP7Xpi_mB0`L(Zu$aN5|#ZM53|WNN9ZM zM&C7CD2N9@cJEdpknc+}mpgjXUxfO6aF^`0*)wrt?rc4SOX$%Y_x>lXko?Q`Zq_n3 zjPoa!qkP=cOy;sv^{ylApT8XT`&~yc38W=_s@;?`8s)UGG)ea*fOa>(AhN-1RtQ>9 z=xAi<)nd$>s=c;Bw2?1MrSoPTHH4OQ0NR?{HK9H z3F@n6=1(zbex^0KdL0ZOlF!l_TO4y5h-E%tX)@@nWG&;a#VDT(T|P~b0bxJxwqUh& zSDZ7JO|j7xtp2w14xmZvm?b=)IN%Trq%83Emfc&icAlQ22i3+fe}Z^#A|vkP??>D{ zOY>@mhUDNM9bdi&c=A4P*Dn~)&vuw@f{uGYnTL4!Z$$&iavZYQh2Fv=W?OZ+H53a1pu7TdrY1tTMLBtB|A)^n9 zF<_}Wgv=kajA!ub1GaVf2x$TuH2?s&+hR*>XDkt?>`X?27!GUsU|JOY9I2v7_V#_D z{BI9Sil1QYt8FLx4#%#R)}KYyjyjgHT=OMq_;>KUei_K`<@v+_=o{}2xmV;12lFOx zKZiBBp3`JJjvRVd#Tk#gzisCn7T2z=VCK^=sU+>P-cZ=@6)c;GtqhN@NtUQ=~;g5K5$z&tnT`@r668{#ix@#-B zQhT&dyOog7hoAnOKK_O80|&~%#SY6d?r)7(aLZLGT->1F?cO$8Xr77iN+Fv+HqVjj z${5k{jfKVF3NU8zgh4s}K|86ip35M{6KS4m4As1J3yutZLP>8f%YsWMv|==wa3pegjM|;Ha~Cm3f~cA@n1jCb33gs@g_9ZY37<1x^dqf^(0Tn6Q*a^ z;~{#yv>`fS^Rle4q60b*61W)%TylRajHY)k44p?T&Y)utq`@c_dXCS0Q$E+2e}NsZ zY{=6+ztno5jzGjxc8^NpmuHH+ySn+brDQLb0pBO9o8PVR(9c%CX-6}n-nQn>(~bg^ zT0abKt-(N-`Hlh|$B<4B{p3sZ?fwRU6 zna>a$4WBS5JJLQ^etR(ah*jOW`=3#yFLEh(-GD^6igw?55u%d!b52g~dzk=YCHpiP zsOmYo7qdqsnG9?oYX0kB{(s9W@&7uf#xsq7S|cX?*V7M>g8&ovP%!sf#ImCjcH3*)~@N<{G!jsJn3WX(z=Lx2phnZI4^ za{A{~_78Gki)|y6Q_YrUB)#nBKQW= zh_{-vsr(r3F3!HSE#GEq>3c&#lo0t8|N619pVA3B*^I8(fsk3u8r)LB@-PKf&Zi)9 zIJZsI22`o|rWV9Scf|kSO(zKHeKNS-8Lu*C$0B1nLRW zvJ}IHu=x)_4bYH&(vw@gs-DZEl(yjM*8# zVeu{UJ$}!BInloAK$o_f^o&C(Y2AV0ws_6g*b(K@!i78Gg@vi%lytrh2Z5glw(8n{ z+bU^o?l;fZCztWKuU?PKfXZ`TPDR^*SWb2yED^A|d z*k)<^A&XC$$j_jABL${k<2!&w^&?&S-=3Y$QFotjRGw|TPii}-!{E%n#c<(HL6Vs( zQOntxSXww9HT5{+m-xAlcS!U#+g>PV?qKOQk_X&6F<)cjnOn=bs3FCy_~T(8 zIER4nV>L355C}Nz!!4xW_=8-1C-1+n*y(0uhGR4E=SP%O;KP=1D&A+;aNg~j^9BHSZf@r{LlEVgL-PsnL%DgoB<-Z$na>^}9KCdsPy&xx?DYG! zY;R@6a=4B|Ee6g($m>wd`;0T!3n@0&1wXmlLIC*{i&ikh=JdM=#_yBS*+Rj zkJ@&8pa>G@Kx+bu2w)<^Nb^YmzF*k}6dWR?zhnbt*G@WaSNmHK2&BQe;w1>VTF){P zaX4${rDB>}CMp-TG|SuYA!&Ik-y0XJI9A;ny1e0^Mq>Ouq84ZO{RZn=r)2r(vNk$+l-O!zqO07IWJW2;DH`5ca~xBc6}ta&V-f~fGQ{tz z)0uG=AJ!+|87F$jRz%6>-1Gj^rpR0H^?K(jR6?6O^QLtfy%1Yz{;kzH%pV_Ax`MOw zK+X@IPu5Y(FUP=?h#CV45oOSO9=X+Ko4JM^5bTI(RlypoqL$F~f5u)1Jw8d$!QLE{ z9SH#Cz;5*4BvLeH+3ytsvqCCm6QSbz!>hBcQCUlJM(WzISb1VSoxGm}b8iAr{3CLqz7`EaK`zCxS^ z9lP!lH|wZtrQfaI<0fAAVc z?nhm-r%d-BXcYH&g#*g(G(>t&z)Ynwpm-~`lrAbRkLHg{iB6O9kq>)uU6caNcnB2f z-O^y-!xyqCpru#;^tmGuV2(R<&aWJWTirrqR32e^yS$epaIe%g4tyN;ssxIKOEYNO z2*u9jSt}EFqnhfb7I@KuXpAMe?x%-o*b-tPaSy6=u^Dr@_Vm9a8* zkfx$yK|rc>6_rsbDx*=lgP}+u(n1MMQLq3J=_R0|FiMHEP(lcZbV7#^LV^qeLI{x# z34yy0%#1qaeZOz5yVhOzKgv1#?E38A(|%7zUsrSHzHp3dOF~8YNtt5;OF@^JKWNXS zCD|ty^G<6F|E0qO5Qrn@z)&+^vm_BO^)J-|%LfY!bkLW>i;@HISj+31hnUUBs?-uVx4_d8^8h-24G6=x}X z8!LX0$~r06$g~U^6pU-_bBi4q*^f%lF|qy-u4ZNe%@^?-W6*b&SA)#Kki6d3wFhU@ zRgae=J*^O4)t1DflAcpb#%SW7xd(r7D;Z=)$C>xGRtD$xgOkT2cJNJVtQfh=HMG%x zTEKp@1lbO7yXh-Z_(VA(0H-y4zVL(oWbtrn^1IAm%J(?a$iwChU)2oSJfm@HG+e7 zl^>-rL{#ELS{U$Oc9*uN{Fz2N*d9K1Z2pLcT(zVpy8CGKsIv(peBc9`pc92A!9A;_ zq(-19&r*YLqO*){IZ|xBLgE^ND5Tcb0j9F(*lHkenRcl3)IrheqwZ!R(Z5WuKx4mg zpWz>>v_T62kNFCNaa%#?j5X7Dv_F;|**x9n11!lhF2xltD>|*d!M3D*OQ+udP!?(G*zk^I!8?}!vC&88TuB(>m7W-;!>E^J{O&gYdRu2q zer#*oNnT$QIW0PBYEsYn{d4Ar1^S{5g&=+rRMlJaHO~9*27H{nT%^vmd@OIPaE@5l zd41mMocP_JbJKMZ7p=sE#@ZWPg{H4BzA&u>h1bfF-%G9 zQA5QTl!NIiBQ!zG%GzBTRr;`3ETL*8$c%BaB=p|?miM3x?Fn*_x19dL>>VuXn_!L9 zje2jZgzIm?Zx9(I%4ihRodBGZB6Zj}M#-a1WM!s8p-(OO+$cI*Cz~EC&ISotgyyc|T05T4jLX0Bvmv4$9%BfPH!obYCRT*7&Y7g3iJGN*zaJ4) zpS`{u^F-g3X3hIfBSRz(u5UPXyK}|ngl{%BYHReIO8(3|#|QEb4)l^L4*toi4iqVZ zVP{PvJ7SgTcg$)28`;g5T|ONMus`R%tz6x9;+5)?8whd5)T%1V8xC|6-Ff|m`3tCM z-2C%R!apf|q?2-$lGYwpIV8u4vZ1ls(yBfUa7_HuLT7fq5%>HQhAaXVZS{9R^r8T; z{(dVhr;ZPHY>22Q2s09UBli**!ykk&Ey@fhIi@3(cS7+udWf@6QsQ;)Pf3uU5oRgQ zGyx&U@y>Gx|KM2vyLS3NqjmqIxtQ-5+y9}phk=CrG->y=$wZo#y@6NYjj9JYP>i!E zUC+zb#b2d!o1>&5)?E~cyi$$g{HNdXpmRB%X{>w?Clf6`>{eh_kx$(q6j_6gpzq_tbKHNQD`FbZQ?tXH017U-a6QWkQB>^qW%ZMl!m9 zBHW~msDTC>z_Nm?(@A+i>(Dsk!Vt5tcVwcl6i~WDEGd2+nPG~Z$iE`pGr%Y*xsbyc zyQP+*wvBW^MB~tg9x62MWG_#+;X_5&&YJ^Kwj*(kTjeS za45_UpjQ~VuqVJ8J^f3r)?mliErSD+3#y*=tcXqNtOGkbGAKpXO|*5fJ_MR^t$l8fpZxo4O$-gCb$x%9CsZ4vN6T8K$) zqLEt4EAtEkQA7MXe@#f8_(O32?asa+7vk$qyJKCT@buAfyl`EvgP-Y$iq0Y8sLIGg zsT6nq%~SH{d~BOSE_-?^;AHXT9eQ{XY;aq%N9Dk3OT+&-=qrjOkf+|qjm;YsToi0HV3-SkB2_?O3n9I4*lXC^W6NLC3^v}n z{nWlv-hnQWmVqP-ujL2F(CJQDNqEzShw|3 z-U(N?{nQbRxP1*%cweAPxAdkdcN#D{H$idfC*>l3|#eg&ShUv5sc<9(H& z*K7UwQ&cM`z}`Pi_bV>{PPJ-yGn45~O7k3klNzVO^pH%Myv)TgClW6?I*BJJS5>7_ zR$+o`t`0=??7SFi1#egfTKf-)w@C|=sqwlJK8oT>lq#+1tN~&Pi}>E*6W|Pb;e5p6 zjP)4c^BI2|tE&*>5;Aao?ulZ?#c8)ND96>G_U~bcSnUN57c_cjBKgbv4HS^$yjH$E z!fL7 z?vXGYs!OB`nZ*jERvmYEZKeIt9CytZWUs*98U6bxzU7+H&l$XN&&iaDOse^mxIZJX zBs5NDZseB3&pr^x4C#TEm(|tX{zjAv_5QKH{JH@n4nk zjG6H|*&uQW`fc)Pw8zACX8PN>`c|tQNd1j0@TFl;DPJ$2a=6% z=d?xrG~vvC5WLf(W4wjS&S`jB_p`faO#`|sQybbfxIdZF{(9ZEVa98u%6pnK`8bD2 z5rpLl$-O?LWYLlU+-};-W>fZ$Hsl;L`L_?0%SWBN0Qqy?@xX*vI2qZwg*Z2d6biW9nY#Kr9JF18!seg^#+&QlWAI1=ip`-w~bEQe4}g1yk9ISVX_fA zZRl@#%f9!>8h+mCu8r4|{VjW-DcVfa(QscPxb=e8ckpp&^dled5Q{ zw!40YNbZ-dXYa%=jJ21=11RldC1NkJWPGz!Un)Ed(x5=mVZkMP5%kzMRY9Rs*SY!i z?0WFecUDL%_ELVXsmxcknN6ZCFr_$(Nxb*v9;;#Rdgd$b$#e~F8~L#=V#!R(dr(ie z$CCo5&j2`RqCJ*1kgB~9yY#I0mtBkc6K#fC64=_MB?c_})4uC+7~{XyB?$(C3TQui zeDw<;WLl8qf4zF-HZ8p>=E)P}|2z?9=&LNg0yZLL*v-E_A-FJSSefi3^B(EPwzsfP z^!V-3KvtEwz1DoMpo*Y`7P5rfjt|roJ8Cuun1#I3ArCL0x#0nBkWalF{>_PFC_jq{ z7c#eSV95qq=l7-RxB$#Dzu7(4jWw%Hoan7NXJUGv=1V0q+cl=zj3^?g;w?tpLwrq+ zr{SS|rQdI-01potbY4cGsdWz!zQ>o`KkB_TL|Mh2#k+#aJ=3!Sr_JvF*yXlt*FT&e ziuu`nvkPT9RhvIF(5x#FqTBZ?;8hA!)ljo*`0eJN=qM}rrt!iqFChAX$dBKAt7Za- znGJn=>ZjQ(N;5DCxbo3jepXO*A$z)J5vbvmR7duJTt=CP=*slvyXsor`xTL`?gdXi z1-r={t7;JXbl)WpGJh959=T6b&hZ9CowQ%Y)&Q3%qgY!yX?+e3+E#Z?0&6h2{}{@y zWIPi8A=wFBOtMNSAC?IqOH0U_wrkc%OiW+M(pGam*CtYT$>#b1Alc9}8R{f7kZnf}P!@f3-u#8ue1SsW?xPCT3ZP_I3$<-R2vqLz zI5+SHZgb0&rn(B|zm;cAfTy_Q{P=`4S-^np*>o*EZT{|IchBBgFBf&V$}6)>=riyL zhj<4c0TYmxz5a-MCI^WXK2s+mL|kx0E$$q;CoDSIcO%cn;Xb-th-yb7WMmk}P8P2M zz__C!0ep3eGX2W)!XR1YAY3+~O3mlpU4TF}r|XdM>wGf`{U*B9dScn;UYSTe1z=kk z)=lxbzB$JXu#vBVneG8QN0vPA45+9q7P(Zb3*t+3Up27?Nm08$05f#Rt)RTRi)dsk z8j~X5$nCJ73Ja!x?s^+hGk~a{epRy1YB21mJ=*}6Dz{Ulr@BD2g5JIY_T0*Xf<~zj ze<5HHbSs5Ub9p+`13&x=0jgC2cJ(c~wTZ^ur|@2mEp?%RP#codwPH#=sVpHQ|24*1 zHYqx{7i}fbk2&Y$aJy<_Z$N8!-rQAs7Ku3%35fb%j=5UNL_M++_qD-XmC~2VSKw>R z7hDTs6$&RwsU(`4dz!w6=3j&8NPt(m7vdZg+M*g8rhkNtLYtkpSo5Z+7AQz~ymQGg zshDCQ`9g8xZt1T5X{NZy7p>aqrft6-K#M*?Y4^__9WW%?7(=07QqH50tZ$|VbKE=0HPWk>kWP?GJPyQZ&bOtlzd zf9D+;x3pQck2j-t!z@KcLTTdRu{OX)bQDy>e4st&ZV}Q5gKd5iAP@E+3=UfoySUyC ztY5BY6?xWj!U5~Ir%g9ns#C%lFHv;DhZF7|w7+sI-EK$-=m=qD#vl^j;F6_Ili+-h`FIpo)`G!(^ubA1XPd$NOuv@TpHjf8xv!T z9kjVs?wD;D9+t~MC`6>?GGz*e?WFSalUXc6Z3HFmBR( z)g9u5JemNMK;qQKj3>ctu7&?{9M+mpxJ==Gd@12D3|qx zZqv7JMCR*CHB3%9Qj~QZ8gcZ|T2)YPhpnYNf#Bl508X3vP}|#^408v)MCb6^E>pc8<6lW(U0^jg3h^%oD-lttJyCzd*9ot zACs&C?ywBi%r&5C}Ce(pU%<|CLAU;!${?6yt=oKAlm(JI(iB0Q{(2LFqH?xV$6yZ{q^1NtJFvRby;C}r-)r0 z&s(}fz4Pl(u7D#_^j&ycM_wUonaAvRyoF4%6kB)C(Q5MoF>MKNDfOe-c!_X<6!dtOmgz&bSdyYt0M50}zK*Nx%}n^mIRMcAr@yV* zD%i-LzmE|1F5vGy17hy)6Z>bQG%k;1$h6a%c@WgA3icc<0o&ujb_aEex$v=Hp|fHs zK#QW4KrZMdH*zC{qdt0ngYvi#%0oYOh-L4xSn!sEIDueye3?Fjk`!6rf&AYtODxIS z>|;5{mF-T&nS1VHp zW1kqi;y8C8 zKt+~%2^nkwJVq_G3ppZyib5_!mfuSBnZ9wqX=U8XZ~k^`t2u_PbiYY;IV`7OH=qsx zg6w{SEF=p7bv-O+Q+OFt($#nQ#AU7p1ScD{sDxu<1CgB zKw4S5JYD`*U0urMR6u27tv|S2%s8~LyR$J%c6*ER5FQ4aBDHD7I)v=ltJo&$JhkQY z1XCBrtKFeUw=d^?oGeg{bGV)w$L{OcsP5uZ3RQr$A6*rEjf%pLj{=A@Hwk{^73IgX zNb^v5-s@r(g?(Li(j7oUvc1h~Iu#pduflQ1+A*Iuuvt#&kY~W#;%G*tT9k_X!ktmp zalsa(BQo>l`xC8RyHiB3QtaJ9Iu)@`r-3|*XyWwu2q6nBi$&XdJh>I7Q*L{(Pz8VLs_`&f!n-2^9eLai|Q-9;0*0IPFZ(b30CnU<;S&$C?iJNx3y zWM!m)hfWTzb|zjuT5o~Uq37<9KX`}jm6mD#f)l1%&mK-@59>&9FF}z?`kUmy=3u7` z#I0uP{;)}D#%J|Ayr~^j5FsbCRrogQ{wkMx^b@utFE>};Pa{fd24=UhJm40*&$E3K{OK*0! zhv#1)daXjBn=lS(l#;p00ri;9r-LA@KGEBv$f#4b!Eevgy1G#9;KqUSqc{-}jA*QCe4w{c-p0QQi-h7KQgffaR>(dv+Idk1T>< zl1ubyd217BR>F~F<6RRja=P@~31W66VQ9XD)8i`MXQuxwoum-fkeg<1!%Z#{T$xaY zPBC3un5%>1owU4S&hFkY*BfvbZQ3hp@30y%@b3Cfv-?YNR4r{Vko~g7n3Obk`IMrr zi~jpwGFHa87$tbhr3W0-_15aZHAl7ZcdUzazvsrA`|O@5z^{JJk_e0$prh91=a@*? z0s7Ycnxq3IOa8o$5qBTnw6)wuA$j$5r5qu2;KdXUf5ee!>65iF+IG{Kk3A|ehYx=nts&al^KcUzUu(XSdEjZ58<36stGjE@DD;^1)>RWm`#JX<|I9n`wSa3_3Qd=S_CFU24Bwzdc8U3+WV{quyHP}0O`eh z-YFI{V&=o_W?JrZM%SJG_r^^rb8aawH>lu;G-xqWnFn@hF~wR;!{0@7lAm;JCZphs zoAZZAf~0yRU8sY7vmn)OdHWb!i!_`)Z25U%@8jWx7efnUrfDF0fZ8EKBK@WwlUAq;nonBm{hWFmDAP<$j-j2wk- zpB3c?j;qY!>?7KUpmc?&=lvOmvYdN2=(Lh~59A0= z^`}ZEE`I8!Pe=X5dc%6%+oB_#^%!(v;w^#c8S$J_Z<%-hmWPZHDKtXOM}(Q&(5NIkMgT&U#OS~kBFW9!|T zb&KcRCmgD2SKdIpRhgl0giiG4`PP>cocqLH6^^-2w9(IZ8-n9JPggyqK38%qbrXdk zhMjrR5y#V7*$D?cqQWcJ-fzG!e_#{3tYi1u-d%Y*%8K-G?%No)xrj(S+cp0VLsumw zJ}X_ls@sF;V(|JnqW))&>GV%7`YRXF22BPfU;usAM0}RkWsBbrs>nf|QvaqoC8g3* zBU3zkCvRuj>j5R9qJm{#?`MPEhUY&jBa3l<4Ir zHR*7aMwUU1UJ@ONZ?v+#?Ohm|-6s~jHzlu+?868tubrx|Td>VM|FNfG-ELECZ1D!a zp3M6+X6TCf{3zJQrOg|XP_;eOZUDPPS)%a#+bf7ojE%OZxck+R&(g@8#t zi-56L>{}a00Cy1l_NAhUVI217n0Qm71EXwyf1q`e;*=(GX|LslbLf$Bbb9mB%?@Fw z&Qo&qp#2-_>rO2?uGb0M_B+^tulXHaY3*l&9oc;i)BXT($;<=&Mu?+Pxp&-mlF4gV2Ao;cTw*S&M(Mx(EtaM-ribA?Q zKwrMgkPmtd2IFm7g0jocji@YP&DF~~UC;mgr9Td90fOak8&+2ghg_zMZQzoG=$KFzInx z0(R#T)OmnjSJe}KjbSHZHzAS>HPvtQOfx#PlyVrmKQ?TeseP4>CXhTiLX#wUYDcD? zFC3LC2s^P|U=Js4i}uuTWu)4~%*N#M(zNPWHD8VX{g-bTGoT&d5S zc5mG2xKG;pp0nvHhx@BGBqC)JD{iU27mFrU<=l;{eq3UQ$xN)H%;wW@uNT($iS z804XV>`j+`M2NtiZ>&{5c`5>EKk|p@ur-(ec<9pzg1B(H=2M+8U-&f4Um79ue9y!o zx=)#TMbf#1`6ob!!A65No)$*3%UmaWe$%Wi~@-WHlb#oUg5={_i6==o`}kzkLs2QAhgeY6kx54 zw%m*$%2xKt^ZSP{CXwE1E#j=X>PhDxkB1_(=S-)D8htalUg~7NXLb|xA<-z8O9T_Q z8^=NX6W4S)CFvdO`m>d0yA~a9MohXU(Ivl}oEx}A zP^sC`+gyC8nK2oP*jAx_E>D{@J8oS9P4z10&9!I)A2YPPF(aareVJ`-ekE9v@p;^q z&Mg|fj)v0=La?t%{4uTJpCMpZ&z~+ENqj*FY zWqv`DnH)AEcl9AFDSyK}<6KqC2!_S|GQ|v(q?aBz@)k*DDN-#t#)L$1iyTJCZ7N-< z&Xfo(-%P#gA^P5uTfj(TnP#%SF+Y;8uUnppb)w0DzhpOm>Qa|YxPm{=YwO-0z($|Is5O)CfnLpnc#c}MnIT}-P~qC@+!F#(cY zPgNtJ_QG10UtIpB+-0ei|0lmRm;uq*iOt@G;eII>L|EJTd?^#Cu(A04uy-06kDeeq z(F`tn*g-;8272=GmF>=rH&q=@^E_4~h^asb)Pu48-}tlHv-a$w67y?m*5d|2nG&Np z6#I9^=5RRt$uJ?dB#D08$?d9{EOvr^=J5K$!FLJDFMKrKm)B0G4G+}Bx5uMWJdH`! zndCL_b^@Z!4?FfuF zolTf2WM3mSzOu!pQZZ)cQe-PH9&4in;ZS##XTreK0x@}g!Y?^^ZS25D^ifXTBc2^8KO^k(C-gAy zAW5*Y>ZxW*=imn?@jVwVS8E3K17~F47I9MoUGZ$uMU!0JHM|;1npamfK#oQc?00F3 z9cMFyNn+{I5;XDP+R8)rCL37};g>&-xfVITHOCj?W<8y8^<#q_hBGP!6#8vp1y(;s z6z<^Cv+>*u6O(+>VJh3#ooPt3GGFv9w6cqK3opDpGH>Pf>!GuIXGEh~59VTZ3*2eu zsmJQeky_VEuBOnPnGqb_8-)0ohh^F?fkfZwg71|yVb2PD;EN6VfSBRO*;Cy;OR^#+5WKj1ytG6=#b=*(svdF^AVPg*+UTUsz zIOuLbeVxZJbXMh_B(28MJ<(5iWH&KvVb$;}VRiZ$*;ogBf7FAmc zt5cL7C8{H}s4j8jo82>NK~SkElC9$>twu%jMoSV3k~%8SYRvH3u{!l>(Fb@n39s-ien=1hZx4tcEm2q8 zjg~nRRuVXY?=$8nMtb5mm^@Gu8xk++nVdN2C;*CQM{jUx69Ncw0*u+1MKFq+3_V`j{v zebR^DYc5>(AX)lou;)J&I7iptcjZrZ!eF5%X@Qy{8=fU-XBzdKS|b_yUVGy?$_VVH0RDirv0EeNE}A7 zdsEW74baH#C`HI172o-sVN%b+o7j~e-6f0j{NZ?QuhiJCB=E&M#z3P=n&&6A@9LSo zIaSx=W6I}Z{oX80WBrsa!o-6L&Z%puEimFOy3=ffJQjCAsHruD{a$rw{LOvpHG&CB z)9;24i|w9<_vNv{;a{7%+r?l{tx+(0RjL3 literal 0 HcmV?d00001 diff --git a/bsp/gd32/risc-v/gd32vw553h-eval/openocd_gdlink.cfg b/bsp/gd32/risc-v/gd32vw553h-eval/openocd_gdlink.cfg new file mode 100644 index 00000000000..1791376ba7d --- /dev/null +++ b/bsp/gd32/risc-v/gd32vw553h-eval/openocd_gdlink.cfg @@ -0,0 +1,42 @@ +# +# GigaDevice GD32VW55x target +# +adapter driver cmsis-dap + +adapter speed 8000000 +reset_config trst_only +adapter srst pulse_width 100 + +transport select jtag + +set _CHIPNAME riscv +jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x10307a6d + +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME riscv -chain-position $_TARGETNAME +$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size 20480 -work-area-backup 0 + + +# Work-area is a space in RAM used for flash programming +if { [info exists WORKAREASIZE] } { + set _WORKAREASIZE $WORKAREASIZE +} else { + set _WORKAREASIZE 0x5000 +} + +# Allow overriding the Flash bank size +if { [info exists FLASH_SIZE] } { + set _FLASH_SIZE $FLASH_SIZE +} else { + # autodetect size + set _FLASH_SIZE 0 +} + +# flash size will be probed +set _FLASHNAME $_CHIPNAME.flash + +flash bank $_FLASHNAME gd32vw55x 0x08000000 0x400000 0 0 $_TARGETNAME +riscv set_reset_timeout_sec 1 +init + +halt diff --git a/bsp/gd32/risc-v/gd32vw553h-eval/rtconfig.h b/bsp/gd32/risc-v/gd32vw553h-eval/rtconfig.h new file mode 100644 index 00000000000..d84ae18f2ef --- /dev/null +++ b/bsp/gd32/risc-v/gd32vw553h-eval/rtconfig.h @@ -0,0 +1,417 @@ +#ifndef RT_CONFIG_H__ +#define RT_CONFIG_H__ + +/* RT-Thread Kernel */ + +/* klibc options */ + +/* rt_vsnprintf options */ + +/* end of rt_vsnprintf options */ + +/* rt_vsscanf options */ + +/* end of rt_vsscanf options */ + +/* rt_memset options */ + +/* end of rt_memset options */ + +/* rt_memcpy options */ + +/* end of rt_memcpy options */ + +/* rt_memmove options */ + +/* end of rt_memmove options */ + +/* rt_memcmp options */ + +/* end of rt_memcmp options */ + +/* rt_strstr options */ + +/* end of rt_strstr options */ + +/* rt_strcasecmp options */ + +/* end of rt_strcasecmp options */ + +/* rt_strncpy options */ + +/* end of rt_strncpy options */ + +/* rt_strcpy options */ + +/* end of rt_strcpy options */ + +/* rt_strncmp options */ + +/* end of rt_strncmp options */ + +/* rt_strcmp options */ + +/* end of rt_strcmp options */ + +/* rt_strlen options */ + +/* end of rt_strlen options */ + +/* rt_strnlen options */ + +/* end of rt_strnlen options */ +/* end of klibc options */ +#define RT_NAME_MAX 8 +#define RT_CPUS_NR 1 +#define RT_ALIGN_SIZE 8 +#define RT_THREAD_PRIORITY_32 +#define RT_THREAD_PRIORITY_MAX 32 +#define RT_TICK_PER_SECOND 1000 +#define RT_USING_OVERFLOW_CHECK +#define RT_USING_HOOK +#define RT_HOOK_USING_FUNC_PTR +#define RT_USING_IDLE_HOOK +#define RT_IDLE_HOOK_LIST_SIZE 4 +#define IDLE_THREAD_STACK_SIZE 1024 +#define RT_USING_TIMER_SOFT +#define RT_TIMER_THREAD_PRIO 4 +#define RT_TIMER_THREAD_STACK_SIZE 1024 + +/* kservice options */ + +/* end of kservice options */ + +/* Inter-Thread communication */ + +#define RT_USING_SEMAPHORE +#define RT_USING_MUTEX +#define RT_USING_EVENT +#define RT_USING_MAILBOX +#define RT_USING_MESSAGEQUEUE +/* end of Inter-Thread communication */ + +/* Memory Management */ + +#define RT_USING_MEMPOOL +#define RT_USING_SMALL_MEM +#define RT_USING_SMALL_MEM_AS_HEAP +#define RT_USING_HEAP +/* end of Memory Management */ +#define RT_USING_DEVICE +#define RT_USING_CONSOLE +#define RT_CONSOLEBUF_SIZE 128 +#define RT_CONSOLE_DEVICE_NAME "uart0" +#define RT_VER_NUM 0x50201 +#define RT_BACKTRACE_LEVEL_MAX_NR 32 +/* end of RT-Thread Kernel */ +#define RT_USING_HW_ATOMIC + +/* RT-Thread Components */ + +#define RT_USING_COMPONENTS_INIT +#define RT_USING_USER_MAIN +#define RT_MAIN_THREAD_STACK_SIZE 4096 +#define RT_MAIN_THREAD_PRIORITY 10 +#define RT_USING_MSH +#define RT_USING_FINSH +#define FINSH_USING_MSH +#define FINSH_THREAD_NAME "tshell" +#define FINSH_THREAD_PRIORITY 20 +#define FINSH_THREAD_STACK_SIZE 4096 +#define FINSH_USING_HISTORY +#define FINSH_HISTORY_LINES 5 +#define FINSH_USING_SYMTAB +#define FINSH_CMD_SIZE 80 +#define MSH_USING_BUILT_IN_COMMANDS +#define FINSH_USING_DESCRIPTION +#define FINSH_ARG_MAX 10 +#define FINSH_USING_OPTION_COMPLETION + +/* DFS: device virtual file system */ + +/* end of DFS: device virtual file system */ + +/* Device Drivers */ + +#define RT_USING_DEVICE_IPC +#define RT_UNAMED_PIPE_NUMBER 64 +#define RT_USING_SERIAL +#define RT_USING_SERIAL_V1 +#define RT_SERIAL_USING_DMA +#define RT_SERIAL_RB_BUFSZ 64 +#define RT_USING_PIN +/* end of Device Drivers */ + +/* C/C++ and POSIX layer */ + +/* ISO-ANSI C layer */ + +/* Timezone and Daylight Saving Time */ + +#define RT_LIBC_USING_LIGHT_TZ_DST +#define RT_LIBC_TZ_DEFAULT_HOUR 8 +#define RT_LIBC_TZ_DEFAULT_MIN 0 +#define RT_LIBC_TZ_DEFAULT_SEC 0 +/* end of Timezone and Daylight Saving Time */ +/* end of ISO-ANSI C layer */ + +/* POSIX (Portable Operating System Interface) layer */ + + +/* Interprocess Communication (IPC) */ + + +/* Socket is in the 'Network' category */ + +/* end of Interprocess Communication (IPC) */ +/* end of POSIX (Portable Operating System Interface) layer */ +/* end of C/C++ and POSIX layer */ + +/* Network */ + +/* end of Network */ + +/* Memory protection */ + +/* end of Memory protection */ + +/* Utilities */ + +/* end of Utilities */ + +/* Using USB legacy version */ + +/* end of Using USB legacy version */ +/* end of RT-Thread Components */ + +/* RT-Thread Utestcases */ + +/* end of RT-Thread Utestcases */ + +/* RT-Thread online packages */ + +/* IoT - internet of things */ + + +/* Wi-Fi */ + +/* Marvell WiFi */ + +/* end of Marvell WiFi */ + +/* Wiced WiFi */ + +/* end of Wiced WiFi */ + +/* CYW43012 WiFi */ + +/* end of CYW43012 WiFi */ + +/* BL808 WiFi */ + +/* end of BL808 WiFi */ + +/* CYW43439 WiFi */ + +/* end of CYW43439 WiFi */ +/* end of Wi-Fi */ + +/* IoT Cloud */ + +/* end of IoT Cloud */ +/* end of IoT - internet of things */ + +/* security packages */ + +/* end of security packages */ + +/* language packages */ + +/* JSON: JavaScript Object Notation, a lightweight data-interchange format */ + +/* end of JSON: JavaScript Object Notation, a lightweight data-interchange format */ + +/* XML: Extensible Markup Language */ + +/* end of XML: Extensible Markup Language */ +/* end of language packages */ + +/* multimedia packages */ + +/* LVGL: powerful and easy-to-use embedded GUI library */ + +/* end of LVGL: powerful and easy-to-use embedded GUI library */ + +/* u8g2: a monochrome graphic library */ + +/* end of u8g2: a monochrome graphic library */ +/* end of multimedia packages */ + +/* tools packages */ + +/* end of tools packages */ + +/* system packages */ + +/* enhanced kernel services */ + +/* end of enhanced kernel services */ + +/* acceleration: Assembly language or algorithmic acceleration packages */ + +/* end of acceleration: Assembly language or algorithmic acceleration packages */ + +/* CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */ + +/* end of CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */ + +/* Micrium: Micrium software products porting for RT-Thread */ + +/* end of Micrium: Micrium software products porting for RT-Thread */ +/* end of system packages */ + +/* peripheral libraries and drivers */ + +/* HAL & SDK Drivers */ + +/* STM32 HAL & SDK Drivers */ + +/* end of STM32 HAL & SDK Drivers */ + +/* Infineon HAL Packages */ + +/* end of Infineon HAL Packages */ + +/* Kendryte SDK */ + +/* end of Kendryte SDK */ + +/* WCH HAL & SDK Drivers */ + +/* end of WCH HAL & SDK Drivers */ + +/* AT32 HAL & SDK Drivers */ + +/* end of AT32 HAL & SDK Drivers */ + +/* HC32 DDL Drivers */ + +/* end of HC32 DDL Drivers */ + +/* NXP HAL & SDK Drivers */ + +/* end of NXP HAL & SDK Drivers */ + +/* NUVOTON Drivers */ + +/* end of NUVOTON Drivers */ + +/* GD32 Drivers */ + +#define PKG_USING_GD32_RISCV_SERIES_DRIVER +#define PKG_USING_GD32_RISCV_SERIES_DRIVER_LATEST_VERSION +/* end of GD32 Drivers */ + +/* HPMicro SDK */ + +/* end of HPMicro SDK */ +/* end of HAL & SDK Drivers */ + +/* sensors drivers */ + +/* end of sensors drivers */ + +/* touch drivers */ + +/* end of touch drivers */ +/* end of peripheral libraries and drivers */ + +/* AI packages */ + +/* end of AI packages */ + +/* Signal Processing and Control Algorithm Packages */ + +/* end of Signal Processing and Control Algorithm Packages */ + +/* miscellaneous packages */ + +/* project laboratory */ + +/* end of project laboratory */ + +/* samples: kernel and components samples */ + +/* end of samples: kernel and components samples */ + +/* entertainment: terminal games and other interesting software packages */ + +/* end of entertainment: terminal games and other interesting software packages */ +/* end of miscellaneous packages */ + +/* Arduino libraries */ + + +/* Projects and Demos */ + +/* end of Projects and Demos */ + +/* Sensors */ + +/* end of Sensors */ + +/* Display */ + +/* end of Display */ + +/* Timing */ + +/* end of Timing */ + +/* Data Processing */ + +/* end of Data Processing */ + +/* Data Storage */ + +/* Communication */ + +/* end of Communication */ + +/* Device Control */ + +/* end of Device Control */ + +/* Other */ + +/* end of Other */ + +/* Signal IO */ + +/* end of Signal IO */ + +/* Uncategorized */ + +/* end of Arduino libraries */ +/* end of RT-Thread online packages */ +#define SOC_FAMILY_GD32 +#define SOC_GD32VW553H + +/* Hardware Drivers Config */ + +#define SOC_SERIES_GD32VW55x + +/* Onboard Peripheral Drivers */ + +/* On-chip Peripheral Drivers */ + +#define BSP_USING_GPIO +#define BSP_USING_UART +#define BSP_USING_UART0 +/* end of On-chip Peripheral Drivers */ + +/* Board extended module Drivers */ + +/* end of Hardware Drivers Config */ + +#endif diff --git a/bsp/gd32/risc-v/gd32vw553h-eval/rtconfig.py b/bsp/gd32/risc-v/gd32vw553h-eval/rtconfig.py new file mode 100644 index 00000000000..79d8de523e7 --- /dev/null +++ b/bsp/gd32/risc-v/gd32vw553h-eval/rtconfig.py @@ -0,0 +1,73 @@ +import os + +# toolchains options +ARCH='risc-v' +CPU='bumblebee' +CROSS_TOOL='gcc' + +# bsp lib config +BSP_LIBRARY_TYPE = None + +if os.getenv('RTT_CC'): + CROSS_TOOL = os.getenv('RTT_CC') +if os.getenv('RTT_ROOT'): + RTT_ROOT = os.getenv('RTT_ROOT') + +# cross_tool provides the cross compiler +# EXEC_PATH is the compiler execute path, for example, CodeSourcery, Keil MDK, IAR +if CROSS_TOOL == 'gcc': + PLATFORM = 'gcc' + EXEC_PATH = r'C:/Program Files (x86)/GNU Tools RISC-V Embedded/8 2019.08-2/bin' +else: + print('Please make sure your toolchains is GNU GCC!') + exit(0) + +if os.getenv('RTT_EXEC_PATH'): + EXEC_PATH = os.getenv('RTT_EXEC_PATH') + +CORE = 'risc-v' +BUILD = 'debug' +MAP_FILE = 'rtthread.map' +LINK_FILE = './board/linker_scripts/link.lds' + +if PLATFORM == 'gcc': + # toolchains + PREFIX = 'riscv-none-embed-' + CC = PREFIX + 'gcc' + AS = PREFIX + 'gcc' + AR = PREFIX + 'ar' + CXX = PREFIX + 'g++' + LINK = PREFIX + 'gcc' + TARGET_EXT = 'elf' + SIZE = PREFIX + 'size' + OBJDUMP = PREFIX + 'objdump' + OBJCPY = PREFIX + 'objcopy' + + DEVICE = ' -march=rv32imafdc -mcmodel=medany -msmall-data-limit=8 -mdiv -mabi=ilp32d -fmessage-length=0 -fsigned-char -ffunction-sections -fdata-sections ' + + # C Compilation Parameters + CFLAGS = DEVICE + ' -std=gnu11 -DUSE_STDPERIPH_DRIVE -save-temps=obj' + # Assembly Compilation Parameters + AFLAGS = DEVICE + '-c'+ ' -x assembler-with-cpp' + # Linking Parameters + LFLAGS = DEVICE + ' -nostartfiles -Xlinker --gc-sections --specs=nano.specs --specs=nosys.specs ' + ' -T ' + LINK_FILE + ' -Wl,-Map=' + MAP_FILE + + CPATH = '' + LPATH = '' + + if BUILD == 'debug': + CFLAGS += ' -O0 -g3' + AFLAGS += ' -g3' + else: + CFLAGS += ' -O2' + + CXXFLAGS = CFLAGS + + POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n' + +def dist_handle(BSP_ROOT, dist_dir): + import sys + cwd_path = os.getcwd() + sys.path.append(os.path.join(os.path.dirname(BSP_ROOT), 'tools')) + from sdk_dist import dist_do_building + dist_do_building(BSP_ROOT, dist_dir) diff --git a/bsp/gd32/risc-v/libraries/Kconfig b/bsp/gd32/risc-v/libraries/Kconfig index 682e10d342f..ac4edcc7a68 100644 --- a/bsp/gd32/risc-v/libraries/Kconfig +++ b/bsp/gd32/risc-v/libraries/Kconfig @@ -7,3 +7,9 @@ config SOC_GD32VF103V select SOC_FAMILY_GD32 select RT_USING_HW_ATOMIC +config SOC_GD32VW553H + bool + select SOC_SERIES_GD32VW + select SOC_FAMILY_GD32 + select RT_USING_HW_ATOMIC + diff --git a/bsp/gd32/risc-v/libraries/gd32_drivers/drv_gpio.c b/bsp/gd32/risc-v/libraries/gd32_drivers/drv_gpio.c index 8d3df301d42..ade2d7b405b 100644 --- a/bsp/gd32/risc-v/libraries/gd32_drivers/drv_gpio.c +++ b/bsp/gd32/risc-v/libraries/gd32_drivers/drv_gpio.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2022, RT-Thread Development Team + * Copyright (c) 2006-2025, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -183,7 +183,17 @@ const struct pin_index *get_pin(rt_uint8_t pin) static void gd32_pin_mode(rt_device_t dev, rt_base_t pin, rt_uint8_t mode) { const struct pin_index *index = RT_NULL; - rt_uint32_t pin_mode = 0; + +#if defined(SOC_SERIES_GD32VF103V) + rt_uint32_t pin_mode = GPIO_MODE_OUT_PP; +#elif defined(SOC_SERIES_GD32VW55x) + rt_uint32_t pin_mode = GPIO_MODE_OUTPUT; + rt_uint32_t pin_pull_up_down = GPIO_PUPD_NONE; + rt_uint32_t pin_otype = GPIO_OTYPE_PP; + rt_uint32_t pin_speed = GPIO_OSPEED_25MHZ; +#else +#error "not support soc" +#endif index = get_pin(pin); if (index == RT_NULL) @@ -194,35 +204,74 @@ static void gd32_pin_mode(rt_device_t dev, rt_base_t pin, rt_uint8_t mode) /* GPIO Periph clock enable */ rcu_periph_clock_enable(index->clk); - pin_mode = GPIO_MODE_OUT_PP; - switch(mode) { case PIN_MODE_OUTPUT: /* output setting */ +#if defined(SOC_SERIES_GD32VF103V) pin_mode = GPIO_MODE_OUT_PP; +#elif defined(SOC_SERIES_GD32VW55x) + pin_mode = GPIO_MODE_OUTPUT; +#else +#error "not support soc" +#endif break; case PIN_MODE_OUTPUT_OD: /* output setting: od. */ +#if defined(SOC_SERIES_GD32VF103V) pin_mode = GPIO_MODE_OUT_OD; +#elif defined(SOC_SERIES_GD32VW55x) + pin_otype = GPIO_OTYPE_OD; +#else +#error "not support soc" +#endif break; case PIN_MODE_INPUT: /* input setting: not pull. */ +#if defined(SOC_SERIES_GD32VF103V) pin_mode = GPIO_MODE_IN_FLOATING; +#elif defined(SOC_SERIES_GD32VW55x) + pin_mode = GPIO_MODE_INPUT; +#else +#error "not support soc" +#endif break; case PIN_MODE_INPUT_PULLUP: /* input setting: pull up. */ +#if defined(SOC_SERIES_GD32VF103V) pin_mode = GPIO_MODE_IPU; +#elif defined(SOC_SERIES_GD32VW55x) + pin_mode = GPIO_MODE_INPUT; + pin_pull_up_down = GPIO_PUPD_PULLUP; +#else +#error "not support soc" +#endif break; case PIN_MODE_INPUT_PULLDOWN: /* input setting: pull down. */ +#if defined(SOC_SERIES_GD32VF103V) pin_mode = GPIO_MODE_IPD; +#elif defined(SOC_SERIES_GD32VW55x) + pin_mode = GPIO_MODE_INPUT; + pin_pull_up_down = GPIO_PUPD_PULLDOWN; +#else +#error "not support soc" +#endif break; default: break; } +#if defined(SOC_SERIES_GD32VF103V) gpio_init(index->gpio_periph, pin_mode, GPIO_OSPEED_50MHZ, index->pin); +#elif defined(SOC_SERIES_GD32VW55x) + gpio_mode_set(index->gpio_periph, pin_mode, pin_pull_up_down, index->pin); + gpio_output_options_set(index->gpio_periph, pin_otype, pin_speed, index->pin); +#else +#error "not support soc" +#endif /* SOC_SERIES_GD32VW55x */ + + } /** @@ -329,6 +378,7 @@ static rt_err_t gd32_pin_attach_irq(struct rt_device *device, rt_base_t pin, rt_hw_interrupt_enable(level); return RT_EOK; } + if (pin_irq_hdr_tab[hdr_index].pin != -1) { rt_hw_interrupt_enable(level); @@ -433,14 +483,22 @@ static rt_err_t gd32_pin_irq_enable(struct rt_device *device, rt_base_t pin, rt_ return -RT_EINVAL; } +#if defined(SOC_SERIES_GD32VF103V) rcu_periph_clock_enable(RCU_AF); - +#elif defined(SOC_SERIES_GD32VW55x) + rcu_periph_clock_enable(RCU_SYSCFG); +#else +#endif /* enable and set interrupt priority */ eclic_irq_enable(irqmap->irqno, 5U, 0U); /* connect EXTI line to GPIO pin */ +#if defined(SOC_SERIES_GD32VF103V) gpio_exti_source_select(index->port_src, index->pin_src); - +#elif defined(SOC_SERIES_GD32VW55x) + syscfg_exti_line_config(index->port_src, index->pin_src); +#else +#endif /* configure EXTI line */ exti_init((exti_line_enum)(index->pin), EXTI_INTERRUPT, trigger_mode); exti_interrupt_flag_clear((exti_line_enum)(index->pin)); @@ -572,3 +630,4 @@ int rt_hw_pin_init(void) INIT_BOARD_EXPORT(rt_hw_pin_init); #endif + diff --git a/bsp/gd32/risc-v/libraries/gd32_drivers/drv_gpio.h b/bsp/gd32/risc-v/libraries/gd32_drivers/drv_gpio.h index 3bfc37b3638..d415309a950 100644 --- a/bsp/gd32/risc-v/libraries/gd32_drivers/drv_gpio.h +++ b/bsp/gd32/risc-v/libraries/gd32_drivers/drv_gpio.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2022, RT-Thread Development Team + * Copyright (c) 2006-2025, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -21,15 +21,27 @@ extern "C" { #if defined SOC_SERIES_GD32VF103V #include "gd32vf103_gpio.h" +#elif defined SOC_SERIES_GD32VW55x +#include "gd32vw55x_gpio.h" +#else +#error "not support soc" #endif #define __GD32_PORT(port) GPIO##port - +#if defined SOC_SERIES_GD32VF103V #define GD32_PIN(index, port, pin) {index, RCU_GPIO##port, \ GPIO##port, GPIO_PIN_##pin, \ GPIO_PORT_SOURCE_GPIO##port, \ GPIO_PIN_SOURCE_##pin} +#elif defined SOC_SERIES_GD32VW55x +#define GD32_PIN(index, port, pin) {index, RCU_GPIO##port, \ + GPIO##port, GPIO_PIN_##pin, \ + EXTI_SOURCE_GPIO##port, \ + EXTI_SOURCE_PIN##pin} +#else +#endif + #define GD32_PIN_DEFAULT {-1, (rcu_periph_enum)0, 0, 0, 0, 0} diff --git a/bsp/gd32/risc-v/libraries/gd32_drivers/drv_usart.c b/bsp/gd32/risc-v/libraries/gd32_drivers/drv_usart.c index 328770af418..2b3f8881d15 100644 --- a/bsp/gd32/risc-v/libraries/gd32_drivers/drv_usart.c +++ b/bsp/gd32/risc-v/libraries/gd32_drivers/drv_usart.c @@ -1,11 +1,12 @@ /* - * Copyright (c) 2006-2022, RT-Thread Development Team + * Copyright (c) 2006-2025, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes * 2021-08-20 BruceOu first implementation + * 2025-07-11 Wangshun adapt to GD32VV553H */ #include "drv_usart.h" @@ -155,11 +156,11 @@ void UART7_IRQHandler(void) static const struct gd32_uart uart_obj[] = { #ifdef BSP_USING_UART0 { - USART0, // uart peripheral index - USART0_IRQn, // uart iqrn - RCU_USART0, RCU_GPIOA, RCU_GPIOA, // periph clock, tx gpio clock, rt gpio clock - GPIOA, GPIO_PIN_9, // tx port, tx pin - GPIOA, GPIO_PIN_10, // rx port, rx pin + USART0, /* uart peripheral index */ + USART0_IRQn, /* uart iqrn */ + RCU_USART0, RCU_GPIOB, RCU_GPIOA, /* periph clock, tx gpio clock, rt gpio clock */ + GPIOB, GPIO_PIN_15, /* tx port, tx pin */ + GPIOA, GPIO_PIN_8, /* rx port, rx pin */ &serial0, "uart0", }, @@ -167,11 +168,11 @@ static const struct gd32_uart uart_obj[] = { #ifdef BSP_USING_UART1 { - USART1, // uart peripheral index - USART1_IRQn, // uart iqrn - RCU_USART1, RCU_GPIOA, RCU_GPIOA, // periph clock, tx gpio clock, rt gpio clock - GPIOA, GPIO_PIN_2, // tx port, tx pin - GPIOA, GPIO_PIN_3, // rx port, rx pin + USART1, /* uart peripheral index */ + USART1_IRQn, /* uart iqrn */ + RCU_USART1, RCU_GPIOA, RCU_GPIOA, /* periph clock, tx gpio clock, rt gpio clock */ + GPIOA, GPIO_PIN_2, /* tx port, tx pin */ + GPIOA, GPIO_PIN_3, /* rx port, rx pin */ &serial1, "uart1", }, @@ -179,11 +180,11 @@ static const struct gd32_uart uart_obj[] = { #ifdef BSP_USING_UART2 { - USART2, // uart peripheral index - USART2_IRQn, // uart iqrn - RCU_USART2, RCU_GPIOB, RCU_GPIOB, // periph clock, tx gpio clock, rt gpio clock - GPIOB, GPIO_PIN_10, // tx port, tx pin - GPIOB, GPIO_PIN_11, // rx port, rx pin + USART2, /* uart peripheral index */ + USART2_IRQn, /* uart iqrn */ + RCU_USART2, RCU_GPIOB, RCU_GPIOB, /* periph clock, tx gpio clock, rt gpio clock */ + GPIOB, GPIO_PIN_10, /* tx port, tx pin */ + GPIOB, GPIO_PIN_11, /* rx port, rx pin */ &serial2, "uart2", }, @@ -191,11 +192,11 @@ static const struct gd32_uart uart_obj[] = { #ifdef BSP_USING_UART3 { - UART3, // uart peripheral index - UART3_IRQn, // uart iqrn - RCU_UART3, RCU_GPIOC, RCU_GPIOC, // periph clock, tx gpio clock, rt gpio clock - GPIOC, GPIO_PIN_10, // tx port, tx pin - GPIOC, GPIO_PIN_11, // rx port, rx pin + UART3, /* uart peripheral index */ + UART3_IRQn, /* uart iqrn */ + RCU_UART3, RCU_GPIOC, RCU_GPIOC, /* periph clock, tx gpio clock, rt gpio clock */ + GPIOC, GPIO_PIN_10, /* tx port, tx pin */ + GPIOC, GPIO_PIN_11, /* rx port, rx pin */ &serial3, "uart3", }, @@ -203,11 +204,11 @@ static const struct gd32_uart uart_obj[] = { #ifdef BSP_USING_UART4 { - UART4, // uart peripheral index - UART4_IRQn, // uart iqrn - RCU_UART4, RCU_GPIOC, RCU_GPIOD, // periph clock, tx gpio clock, rt gpio clock - GPIOC, GPIO_PIN_12, // tx port, tx pin - GPIOD, GPIO_PIN_2, // rx port, rx pin + UART4, /* uart peripheral index */ + UART4_IRQn, /* uart iqrn */ + RCU_UART4, RCU_GPIOC, RCU_GPIOD, /* periph clock, tx gpio clock, rt gpio clock */ + GPIOC, GPIO_PIN_12, /* tx port, tx pin */ + GPIOD, GPIO_PIN_2, /* rx port, rx pin */ &serial4, "uart4", }, @@ -231,11 +232,19 @@ void gd32_uart_gpio_init(struct gd32_uart *uart) rcu_periph_clock_enable(uart->rx_gpio_clk); rcu_periph_clock_enable(uart->per_clk); - /* connect port to USARTx_Tx */ + /* connect port */ +#if defined SOC_SERIES_GD32VF103V gpio_init(uart->tx_port, GPIO_MODE_AF_PP, GPIO_OSPEED_50MHZ, uart->tx_pin); - - /* connect port to USARTx_Rx */ gpio_init(uart->rx_port, GPIO_MODE_IN_FLOATING, GPIO_OSPEED_50MHZ, uart->rx_pin); +#else + gpio_af_set(uart->tx_port, GPIO_AF_8, uart->tx_pin); + gpio_mode_set(uart->tx_port, GPIO_MODE_AF, GPIO_PUPD_PULLUP, uart->tx_pin); + gpio_output_options_set(uart->tx_port, GPIO_OTYPE_PP, GPIO_OSPEED_25MHZ, uart->tx_pin); + + gpio_af_set(uart->rx_port, GPIO_AF_2, uart->rx_pin); + gpio_mode_set(uart->rx_port, GPIO_MODE_AF, GPIO_PUPD_PULLUP, uart->rx_pin); + gpio_output_options_set(uart->rx_port, GPIO_OTYPE_PP, GPIO_OSPEED_25MHZ, uart->rx_pin); +#endif } /** @@ -319,7 +328,9 @@ static rt_err_t gd32_uart_control(struct rt_serial_device *serial, int cmd, void break; case RT_DEVICE_CTRL_SET_INT: +#ifdef SOC_SERIES_GD32VF103V eclic_set_nlbits(ECLIC_GROUP_LEVEL3_PRIO1); +#endif /* SOC_SERIES_GD32VF103V */ /* enable rx irq */ eclic_irq_enable(uart->irqn, 1, 0); /* enable interrupt */ @@ -442,7 +453,5 @@ int rt_hw_usart_init(void) return result; } - -//INIT_BOARD_EXPORT(rt_hw_usart_init); - #endif + diff --git a/bsp/gd32/risc-v/libraries/gd32_drivers/drv_usart.h b/bsp/gd32/risc-v/libraries/gd32_drivers/drv_usart.h index 5c5c1af2ad9..6a6f75697e6 100644 --- a/bsp/gd32/risc-v/libraries/gd32_drivers/drv_usart.h +++ b/bsp/gd32/risc-v/libraries/gd32_drivers/drv_usart.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2022, RT-Thread Development Team + * Copyright (c) 2006-2025, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -20,18 +20,18 @@ extern "C" { #endif /* GD32 uart driver */ -// Todo: compress uart info +/* Todo: compress uart info */ struct gd32_uart { - uint32_t uart_periph; //Todo: 3bits - IRQn_Type irqn; //Todo: 7bits - rcu_periph_enum per_clk; //Todo: 5bits - rcu_periph_enum tx_gpio_clk; //Todo: 5bits - rcu_periph_enum rx_gpio_clk; //Todo: 5bits - uint32_t tx_port; //Todo: 4bits - uint16_t tx_pin; //Todo: 4bits - uint32_t rx_port; //Todo: 4bits - uint16_t rx_pin; //Todo: 4bits + uint32_t uart_periph; /* Todo: 3bits */ + IRQn_Type irqn; /* Todo: 7bits */ + rcu_periph_enum per_clk; /* Todo: 5bits */ + rcu_periph_enum tx_gpio_clk; /* Todo: 5bits */ + rcu_periph_enum rx_gpio_clk; /* Todo: 5bits */ + uint32_t tx_port; /* Todo: 4bits */ + uint16_t tx_pin; /* Todo: 4bits */ + uint32_t rx_port; /* Todo: 4bits */ + uint16_t rx_pin; /* Todo: 4bits */ struct rt_serial_device * serial; char *device_name; }; @@ -43,3 +43,4 @@ int rt_hw_usart_init(void); #endif #endif /* __DRV_USART_H__ */ + diff --git a/bsp/hpmicro/hpm5300evk/SConstruct b/bsp/hpmicro/hpm5300evk/SConstruct index ce70828c063..5fcc825f590 100644 --- a/bsp/hpmicro/hpm5300evk/SConstruct +++ b/bsp/hpmicro/hpm5300evk/SConstruct @@ -15,6 +15,23 @@ except: print(RTT_ROOT) exit(-1) +def bsp_pkg_check(): + import subprocess + + need_update = True + for p in os.listdir("packages"): + if p.startswith("hpm_sdk-"): + need_update = False + break + if need_update: + print("\n===============================================================================") + print("Dependency packages missing, please running 'pkgs --update'...") + print("If no packages are fetched, run 'pkgs --upgrade' first, then 'pkgs --update'...") + print("===============================================================================") + exit(1) + +RegisterPreBuildingAction(bsp_pkg_check) + TARGET = 'rtthread.' + rtconfig.TARGET_EXT AddOption('--run', @@ -56,7 +73,6 @@ GDB = rtconfig.GDB objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False) - # includes rtt drivers objs.extend(SConscript(os.path.join(libraries_path_prefix, 'drivers', 'SConscript'))) diff --git a/bsp/hpmicro/hpm5300evk/rtconfig.py b/bsp/hpmicro/hpm5300evk/rtconfig.py index f7a81092002..ab7d843770f 100644 --- a/bsp/hpmicro/hpm5300evk/rtconfig.py +++ b/bsp/hpmicro/hpm5300evk/rtconfig.py @@ -12,29 +12,6 @@ RTT_ROOT = os.path.normpath(os.getcwd() + '/../../..') sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')] -try: - from building import * -except: - print('Cannot found RT-Thread root directory, please check RTT_ROOT') - print(RTT_ROOT) - exit(-1) - -def bsp_pkg_check(): - import subprocess - - need_update = True - for p in os.listdir("packages"): - if p.startswith("hpm_sdk-"): - need_update = False - break - if need_update: - print("\n===============================================================================") - print("Dependency packages missing, please running 'pkgs --update'...") - print("If no packages are fetched, run 'pkgs --upgrade' first, then 'pkgs --update'...") - print("===============================================================================") - exit(1) - -RegisterPreBuildingAction(bsp_pkg_check) # toolchains options diff --git a/bsp/hpmicro/hpm5301evklite/SConstruct b/bsp/hpmicro/hpm5301evklite/SConstruct index a4d1f600062..3a656aa15b2 100644 --- a/bsp/hpmicro/hpm5301evklite/SConstruct +++ b/bsp/hpmicro/hpm5301evklite/SConstruct @@ -15,6 +15,23 @@ except: print(RTT_ROOT) exit(-1) +def bsp_pkg_check(): + import subprocess + + need_update = True + for p in os.listdir("packages"): + if p.startswith("hpm_sdk-"): + need_update = False + break + if need_update: + print("\n===============================================================================") + print("Dependency packages missing, please running 'pkgs --update'...") + print("If no packages are fetched, run 'pkgs --upgrade' first, then 'pkgs --update'...") + print("===============================================================================") + exit(1) + +RegisterPreBuildingAction(bsp_pkg_check) + TARGET = 'rtthread.' + rtconfig.TARGET_EXT AddOption('--run', diff --git a/bsp/hpmicro/hpm5301evklite/rtconfig.py b/bsp/hpmicro/hpm5301evklite/rtconfig.py index c45c1190989..dc209cee21f 100644 --- a/bsp/hpmicro/hpm5301evklite/rtconfig.py +++ b/bsp/hpmicro/hpm5301evklite/rtconfig.py @@ -12,30 +12,6 @@ RTT_ROOT = os.path.normpath(os.getcwd() + '/../../..') sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')] -try: - from building import * -except: - print('Cannot found RT-Thread root directory, please check RTT_ROOT') - print(RTT_ROOT) - exit(-1) - -def bsp_pkg_check(): - import subprocess - - need_update = True - for p in os.listdir("packages"): - if p.startswith("hpm_sdk-"): - need_update = False - break - if need_update: - print("\n===============================================================================") - print("Dependency packages missing, please running 'pkgs --update'...") - print("If no packages are fetched, run 'pkgs --upgrade' first, then 'pkgs --update'...") - print("===============================================================================") - exit(1) - -RegisterPreBuildingAction(bsp_pkg_check) - # toolchains options ARCH='risc-v' diff --git a/bsp/hpmicro/hpm5e00evk/SConstruct b/bsp/hpmicro/hpm5e00evk/SConstruct index a4d1f600062..3a656aa15b2 100644 --- a/bsp/hpmicro/hpm5e00evk/SConstruct +++ b/bsp/hpmicro/hpm5e00evk/SConstruct @@ -15,6 +15,23 @@ except: print(RTT_ROOT) exit(-1) +def bsp_pkg_check(): + import subprocess + + need_update = True + for p in os.listdir("packages"): + if p.startswith("hpm_sdk-"): + need_update = False + break + if need_update: + print("\n===============================================================================") + print("Dependency packages missing, please running 'pkgs --update'...") + print("If no packages are fetched, run 'pkgs --upgrade' first, then 'pkgs --update'...") + print("===============================================================================") + exit(1) + +RegisterPreBuildingAction(bsp_pkg_check) + TARGET = 'rtthread.' + rtconfig.TARGET_EXT AddOption('--run', diff --git a/bsp/hpmicro/hpm5e00evk/rtconfig.py b/bsp/hpmicro/hpm5e00evk/rtconfig.py index 2c9cbfbda49..14789f56ff4 100644 --- a/bsp/hpmicro/hpm5e00evk/rtconfig.py +++ b/bsp/hpmicro/hpm5e00evk/rtconfig.py @@ -12,30 +12,6 @@ RTT_ROOT = os.path.normpath(os.getcwd() + '/../../..') sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')] -try: - from building import * -except: - print('Cannot found RT-Thread root directory, please check RTT_ROOT') - print(RTT_ROOT) - exit(-1) - -def bsp_pkg_check(): - import subprocess - - need_update = True - for p in os.listdir("packages"): - if p.startswith("hpm_sdk-"): - need_update = False - break - if need_update: - print("\n===============================================================================") - print("Dependency packages missing, please running 'pkgs --update'...") - print("If no packages are fetched, run 'pkgs --upgrade' first, then 'pkgs --update'...") - print("===============================================================================") - exit(1) - -RegisterPreBuildingAction(bsp_pkg_check) - # toolchains options ARCH='risc-v' diff --git a/bsp/hpmicro/hpm6200evk/SConstruct b/bsp/hpmicro/hpm6200evk/SConstruct index ce70828c063..bc5059c9370 100644 --- a/bsp/hpmicro/hpm6200evk/SConstruct +++ b/bsp/hpmicro/hpm6200evk/SConstruct @@ -15,6 +15,23 @@ except: print(RTT_ROOT) exit(-1) +def bsp_pkg_check(): + import subprocess + + need_update = True + for p in os.listdir("packages"): + if p.startswith("hpm_sdk-"): + need_update = False + break + if need_update: + print("\n===============================================================================") + print("Dependency packages missing, please running 'pkgs --update'...") + print("If no packages are fetched, run 'pkgs --upgrade' first, then 'pkgs --update'...") + print("===============================================================================") + exit(1) + +RegisterPreBuildingAction(bsp_pkg_check) + TARGET = 'rtthread.' + rtconfig.TARGET_EXT AddOption('--run', diff --git a/bsp/hpmicro/hpm6200evk/rtconfig.py b/bsp/hpmicro/hpm6200evk/rtconfig.py index d9c6d27fb6e..28d0b94cb9e 100644 --- a/bsp/hpmicro/hpm6200evk/rtconfig.py +++ b/bsp/hpmicro/hpm6200evk/rtconfig.py @@ -12,30 +12,6 @@ RTT_ROOT = os.path.normpath(os.getcwd() + '/../../..') sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')] -try: - from building import * -except: - print('Cannot found RT-Thread root directory, please check RTT_ROOT') - print(RTT_ROOT) - exit(-1) - -def bsp_pkg_check(): - import subprocess - - need_update = True - for p in os.listdir("packages"): - if p.startswith("hpm_sdk-"): - need_update = False - break - if need_update: - print("\n===============================================================================") - print("Dependency packages missing, please running 'pkgs --update'...") - print("If no packages are fetched, run 'pkgs --upgrade' first, then 'pkgs --update'...") - print("===============================================================================") - exit(1) - -RegisterPreBuildingAction(bsp_pkg_check) - # toolchains options ARCH='risc-v' diff --git a/bsp/hpmicro/hpm6300evk/SConstruct b/bsp/hpmicro/hpm6300evk/SConstruct index ce70828c063..bc5059c9370 100644 --- a/bsp/hpmicro/hpm6300evk/SConstruct +++ b/bsp/hpmicro/hpm6300evk/SConstruct @@ -15,6 +15,23 @@ except: print(RTT_ROOT) exit(-1) +def bsp_pkg_check(): + import subprocess + + need_update = True + for p in os.listdir("packages"): + if p.startswith("hpm_sdk-"): + need_update = False + break + if need_update: + print("\n===============================================================================") + print("Dependency packages missing, please running 'pkgs --update'...") + print("If no packages are fetched, run 'pkgs --upgrade' first, then 'pkgs --update'...") + print("===============================================================================") + exit(1) + +RegisterPreBuildingAction(bsp_pkg_check) + TARGET = 'rtthread.' + rtconfig.TARGET_EXT AddOption('--run', diff --git a/bsp/hpmicro/hpm6300evk/rtconfig.py b/bsp/hpmicro/hpm6300evk/rtconfig.py index 8d80351c7ce..dcf456c802c 100644 --- a/bsp/hpmicro/hpm6300evk/rtconfig.py +++ b/bsp/hpmicro/hpm6300evk/rtconfig.py @@ -12,30 +12,6 @@ RTT_ROOT = os.path.normpath(os.getcwd() + '/../../..') sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')] -try: - from building import * -except: - print('Cannot found RT-Thread root directory, please check RTT_ROOT') - print(RTT_ROOT) - exit(-1) - -def bsp_pkg_check(): - import subprocess - - need_update = True - for p in os.listdir("packages"): - if p.startswith("hpm_sdk-"): - need_update = False - break - if need_update: - print("\n===============================================================================") - print("Dependency packages missing, please running 'pkgs --update'...") - print("If no packages are fetched, run 'pkgs --upgrade' first, then 'pkgs --update'...") - print("===============================================================================") - exit(1) - -RegisterPreBuildingAction(bsp_pkg_check) - # toolchains options ARCH='risc-v' diff --git a/bsp/hpmicro/hpm6750evk/SConstruct b/bsp/hpmicro/hpm6750evk/SConstruct index ce70828c063..bc5059c9370 100644 --- a/bsp/hpmicro/hpm6750evk/SConstruct +++ b/bsp/hpmicro/hpm6750evk/SConstruct @@ -15,6 +15,23 @@ except: print(RTT_ROOT) exit(-1) +def bsp_pkg_check(): + import subprocess + + need_update = True + for p in os.listdir("packages"): + if p.startswith("hpm_sdk-"): + need_update = False + break + if need_update: + print("\n===============================================================================") + print("Dependency packages missing, please running 'pkgs --update'...") + print("If no packages are fetched, run 'pkgs --upgrade' first, then 'pkgs --update'...") + print("===============================================================================") + exit(1) + +RegisterPreBuildingAction(bsp_pkg_check) + TARGET = 'rtthread.' + rtconfig.TARGET_EXT AddOption('--run', diff --git a/bsp/hpmicro/hpm6750evk/rtconfig.py b/bsp/hpmicro/hpm6750evk/rtconfig.py index a79c03c4464..14ba9b7129d 100644 --- a/bsp/hpmicro/hpm6750evk/rtconfig.py +++ b/bsp/hpmicro/hpm6750evk/rtconfig.py @@ -12,30 +12,6 @@ RTT_ROOT = os.path.normpath(os.getcwd() + '/../../..') sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')] -try: - from building import * -except: - print('Cannot found RT-Thread root directory, please check RTT_ROOT') - print(RTT_ROOT) - exit(-1) - -def bsp_pkg_check(): - import subprocess - - need_update = True - for p in os.listdir("packages"): - if p.startswith("hpm_sdk-"): - need_update = False - break - if need_update: - print("\n===============================================================================") - print("Dependency packages missing, please running 'pkgs --update'...") - print("If no packages are fetched, run 'pkgs --upgrade' first, then 'pkgs --update'...") - print("===============================================================================") - exit(1) - -RegisterPreBuildingAction(bsp_pkg_check) - # toolchains options ARCH='risc-v' diff --git a/bsp/hpmicro/hpm6750evk2/SConstruct b/bsp/hpmicro/hpm6750evk2/SConstruct index ce70828c063..bc5059c9370 100644 --- a/bsp/hpmicro/hpm6750evk2/SConstruct +++ b/bsp/hpmicro/hpm6750evk2/SConstruct @@ -15,6 +15,23 @@ except: print(RTT_ROOT) exit(-1) +def bsp_pkg_check(): + import subprocess + + need_update = True + for p in os.listdir("packages"): + if p.startswith("hpm_sdk-"): + need_update = False + break + if need_update: + print("\n===============================================================================") + print("Dependency packages missing, please running 'pkgs --update'...") + print("If no packages are fetched, run 'pkgs --upgrade' first, then 'pkgs --update'...") + print("===============================================================================") + exit(1) + +RegisterPreBuildingAction(bsp_pkg_check) + TARGET = 'rtthread.' + rtconfig.TARGET_EXT AddOption('--run', diff --git a/bsp/hpmicro/hpm6750evk2/rtconfig.py b/bsp/hpmicro/hpm6750evk2/rtconfig.py index 0071195b00d..e37092268b9 100644 --- a/bsp/hpmicro/hpm6750evk2/rtconfig.py +++ b/bsp/hpmicro/hpm6750evk2/rtconfig.py @@ -12,30 +12,6 @@ RTT_ROOT = os.path.normpath(os.getcwd() + '/../../..') sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')] -try: - from building import * -except: - print('Cannot found RT-Thread root directory, please check RTT_ROOT') - print(RTT_ROOT) - exit(-1) - -def bsp_pkg_check(): - import subprocess - - need_update = True - for p in os.listdir("packages"): - if p.startswith("hpm_sdk-"): - need_update = False - break - if need_update: - print("\n===============================================================================") - print("Dependency packages missing, please running 'pkgs --update'...") - print("If no packages are fetched, run 'pkgs --upgrade' first, then 'pkgs --update'...") - print("===============================================================================") - exit(1) - -RegisterPreBuildingAction(bsp_pkg_check) - # toolchains options ARCH='risc-v' diff --git a/bsp/hpmicro/hpm6750evkmini/SConstruct b/bsp/hpmicro/hpm6750evkmini/SConstruct index ce70828c063..bc5059c9370 100644 --- a/bsp/hpmicro/hpm6750evkmini/SConstruct +++ b/bsp/hpmicro/hpm6750evkmini/SConstruct @@ -15,6 +15,23 @@ except: print(RTT_ROOT) exit(-1) +def bsp_pkg_check(): + import subprocess + + need_update = True + for p in os.listdir("packages"): + if p.startswith("hpm_sdk-"): + need_update = False + break + if need_update: + print("\n===============================================================================") + print("Dependency packages missing, please running 'pkgs --update'...") + print("If no packages are fetched, run 'pkgs --upgrade' first, then 'pkgs --update'...") + print("===============================================================================") + exit(1) + +RegisterPreBuildingAction(bsp_pkg_check) + TARGET = 'rtthread.' + rtconfig.TARGET_EXT AddOption('--run', diff --git a/bsp/hpmicro/hpm6750evkmini/rtconfig.py b/bsp/hpmicro/hpm6750evkmini/rtconfig.py index 0071195b00d..e37092268b9 100644 --- a/bsp/hpmicro/hpm6750evkmini/rtconfig.py +++ b/bsp/hpmicro/hpm6750evkmini/rtconfig.py @@ -12,30 +12,6 @@ RTT_ROOT = os.path.normpath(os.getcwd() + '/../../..') sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')] -try: - from building import * -except: - print('Cannot found RT-Thread root directory, please check RTT_ROOT') - print(RTT_ROOT) - exit(-1) - -def bsp_pkg_check(): - import subprocess - - need_update = True - for p in os.listdir("packages"): - if p.startswith("hpm_sdk-"): - need_update = False - break - if need_update: - print("\n===============================================================================") - print("Dependency packages missing, please running 'pkgs --update'...") - print("If no packages are fetched, run 'pkgs --upgrade' first, then 'pkgs --update'...") - print("===============================================================================") - exit(1) - -RegisterPreBuildingAction(bsp_pkg_check) - # toolchains options ARCH='risc-v' diff --git a/bsp/hpmicro/hpm6800evk/SConstruct b/bsp/hpmicro/hpm6800evk/SConstruct index ce70828c063..bc5059c9370 100644 --- a/bsp/hpmicro/hpm6800evk/SConstruct +++ b/bsp/hpmicro/hpm6800evk/SConstruct @@ -15,6 +15,23 @@ except: print(RTT_ROOT) exit(-1) +def bsp_pkg_check(): + import subprocess + + need_update = True + for p in os.listdir("packages"): + if p.startswith("hpm_sdk-"): + need_update = False + break + if need_update: + print("\n===============================================================================") + print("Dependency packages missing, please running 'pkgs --update'...") + print("If no packages are fetched, run 'pkgs --upgrade' first, then 'pkgs --update'...") + print("===============================================================================") + exit(1) + +RegisterPreBuildingAction(bsp_pkg_check) + TARGET = 'rtthread.' + rtconfig.TARGET_EXT AddOption('--run', diff --git a/bsp/hpmicro/hpm6800evk/rtconfig.py b/bsp/hpmicro/hpm6800evk/rtconfig.py index 64aed40637c..31a6e62e5ee 100644 --- a/bsp/hpmicro/hpm6800evk/rtconfig.py +++ b/bsp/hpmicro/hpm6800evk/rtconfig.py @@ -12,30 +12,6 @@ RTT_ROOT = os.path.normpath(os.getcwd() + '/../../..') sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')] -try: - from building import * -except: - print('Cannot found RT-Thread root directory, please check RTT_ROOT') - print(RTT_ROOT) - exit(-1) - -def bsp_pkg_check(): - import subprocess - - need_update = True - for p in os.listdir("packages"): - if p.startswith("hpm_sdk-"): - need_update = False - break - if need_update: - print("\n===============================================================================") - print("Dependency packages missing, please running 'pkgs --update'...") - print("If no packages are fetched, run 'pkgs --upgrade' first, then 'pkgs --update'...") - print("===============================================================================") - exit(1) - -RegisterPreBuildingAction(bsp_pkg_check) - # toolchains options ARCH='risc-v' diff --git a/bsp/hpmicro/hpm6p00evk/SConstruct b/bsp/hpmicro/hpm6p00evk/SConstruct index ce70828c063..bc5059c9370 100644 --- a/bsp/hpmicro/hpm6p00evk/SConstruct +++ b/bsp/hpmicro/hpm6p00evk/SConstruct @@ -15,6 +15,23 @@ except: print(RTT_ROOT) exit(-1) +def bsp_pkg_check(): + import subprocess + + need_update = True + for p in os.listdir("packages"): + if p.startswith("hpm_sdk-"): + need_update = False + break + if need_update: + print("\n===============================================================================") + print("Dependency packages missing, please running 'pkgs --update'...") + print("If no packages are fetched, run 'pkgs --upgrade' first, then 'pkgs --update'...") + print("===============================================================================") + exit(1) + +RegisterPreBuildingAction(bsp_pkg_check) + TARGET = 'rtthread.' + rtconfig.TARGET_EXT AddOption('--run', diff --git a/bsp/hpmicro/hpm6p00evk/rtconfig.py b/bsp/hpmicro/hpm6p00evk/rtconfig.py index 34052a80e4a..accc54ed8c1 100644 --- a/bsp/hpmicro/hpm6p00evk/rtconfig.py +++ b/bsp/hpmicro/hpm6p00evk/rtconfig.py @@ -12,30 +12,6 @@ RTT_ROOT = os.path.normpath(os.getcwd() + '/../../..') sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')] -try: - from building import * -except: - print('Cannot found RT-Thread root directory, please check RTT_ROOT') - print(RTT_ROOT) - exit(-1) - -def bsp_pkg_check(): - import subprocess - - need_update = True - for p in os.listdir("packages"): - if p.startswith("hpm_sdk-"): - need_update = False - break - if need_update: - print("\n===============================================================================") - print("Dependency packages missing, please running 'pkgs --update'...") - print("If no packages are fetched, run 'pkgs --upgrade' first, then 'pkgs --update'...") - print("===============================================================================") - exit(1) - -RegisterPreBuildingAction(bsp_pkg_check) - # toolchains options ARCH='risc-v' diff --git a/bsp/hpmicro/libraries/drivers/drv_sdio.c b/bsp/hpmicro/libraries/drivers/drv_sdio.c index 58088c14f8c..f820c7e0d3e 100644 --- a/bsp/hpmicro/libraries/drivers/drv_sdio.c +++ b/bsp/hpmicro/libraries/drivers/drv_sdio.c @@ -97,7 +97,7 @@ static hpm_stat_t hpm_sdmmc_transfer_polling(struct hpm_mmcsd *mmcsd, sdxc_adma_ static hpm_stat_t hpm_sdmmc_transfer_interrupt_driven(struct hpm_mmcsd *mmcsd, sdxc_adma_config_t *dma_config, sdxc_xfer_t *xfer); static hpm_stat_t hpm_sdmmc_transfer(struct hpm_mmcsd *mmcsd, sdxc_adma_config_t *dma_config, sdxc_xfer_t *xfer); static rt_int32_t hpm_sdmmc_execute_tuning(struct rt_mmcsd_host *host, rt_int32_t opcode); -static rt_int32_t hpm_sdmmc_switch_uhs_voltage(struct rt_mmcsd_host *host); +static rt_err_t hpm_sdmmc_signal_voltage_switch(struct rt_mmcsd_host *host, struct rt_mmcsd_io_cfg *io_cfg); static void hpm_sdmmc_power_on_via_pin(struct hpm_mmcsd *mmcsd); static void hpm_sdmmc_power_off_via_pin(struct hpm_mmcsd *mmcsd); @@ -152,7 +152,7 @@ static void hpm_sdmmc_switch_to_1v8_via_pin(struct hpm_mmcsd *mmcsd) } -static rt_int32_t hpm_sdmmc_switch_uhs_voltage(struct rt_mmcsd_host *host) +static rt_err_t hpm_sdmmc_signal_voltage_switch(struct rt_mmcsd_host *host, struct rt_mmcsd_io_cfg *io_cfg) { struct hpm_mmcsd *mmcsd = (struct hpm_mmcsd *) host->private_data; SDXC_Type *base = mmcsd->sdxc_base; @@ -174,9 +174,17 @@ static rt_int32_t hpm_sdmmc_switch_uhs_voltage(struct rt_mmcsd_host *host) return -RT_ETIMEOUT; } - /* 3. Switch to 1.8V */ - hpm_sdmmc_switch_to_1v8_via_pin(mmcsd); - sdxc_select_voltage(mmcsd->sdxc_base, sdxc_bus_voltage_sd_1v8); + /* 3. Switch to 1.8V/3.3V */ + if (ios->signal_voltage == MMCSD_SIGNAL_VOLTAGE_330) + { + hpm_sdmmc_switch_to_3v3_via_pin(mmcsd); + sdxc_select_voltage(mmcsd->sdxc_base, sdxc_bus_voltage_sd_3v3); + } + else + { + hpm_sdmmc_switch_to_1v8_via_pin(mmcsd); + sdxc_select_voltage(mmcsd->sdxc_base, sdxc_bus_voltage_sd_1v8); + } /* 4. spec:host delay 5ms, host: give more delay time here */ rt_thread_mdelay(10); @@ -213,7 +221,7 @@ static const struct rt_mmcsd_host_ops hpm_mmcsd_host_ops = .get_card_status = NULL, .enable_sdio_irq = hpm_sdmmc_enable_sdio_irq, .execute_tuning = hpm_sdmmc_execute_tuning, - .switch_uhs_voltage = hpm_sdmmc_switch_uhs_voltage, + .signal_voltage_switch = hpm_sdmmc_signal_voltage_switch, }; void hpm_sdmmc_isr(struct hpm_mmcsd *mmcsd) diff --git a/bsp/k230/.ci/attachconfig/ci.attachconfig.yml b/bsp/k230/.ci/attachconfig/ci.attachconfig.yml index e579d18af98..5a9ed754a61 100644 --- a/bsp/k230/.ci/attachconfig/ci.attachconfig.yml +++ b/bsp/k230/.ci/attachconfig/ci.attachconfig.yml @@ -1,6 +1,10 @@ scons.args: &scons scons_arg: - '--strict' +devices.gnee: + <<: *scons + kconfig: + - CONFIG_BSP_USING_GNNE=y devices.spi: <<: *scons kconfig: @@ -13,6 +17,7 @@ devices.i2c: - CONFIG_RT_USING_I2C=y - CONFIG_BSP_USING_I2C=y - CONFIG_BSP_USING_I2C0=y + - CONFIG_BSP_USING_I2C_DMA=y devices.adc: <<: *scons kconfig: diff --git a/bsp/k230/.config b/bsp/k230/.config index e4c479c1e6a..47d11534483 100644 --- a/bsp/k230/.config +++ b/bsp/k230/.config @@ -941,7 +941,6 @@ CONFIG_RT_USING_VDSO=y # CONFIG_PKG_USING_R_RHEALSTONE is not set # CONFIG_PKG_USING_HEARTBEAT is not set # CONFIG_PKG_USING_MICRO_ROS_RTTHREAD_PACKAGE is not set -# CONFIG_PKG_USING_CHERRYECAT is not set # end of system packages # @@ -1099,12 +1098,6 @@ CONFIG_RT_USING_VDSO=y # CONFIG_PKG_USING_GD32_ARM_CMSIS_DRIVER is not set # CONFIG_PKG_USING_GD32_ARM_SERIES_DRIVER is not set # end of GD32 Drivers - -# -# HPMicro SDK -# -# CONFIG_PKG_USING_HPM_SDK is not set -# end of HPMicro SDK # end of HAL & SDK Drivers # @@ -1624,6 +1617,7 @@ CONFIG_PKG_ZLIB_VER="latest" # # Drivers Configuration # +# CONFIG_BSP_USING_GNNE is not set # CONFIG_BSP_USING_SPI is not set # CONFIG_BSP_USING_I2C is not set # CONFIG_BSP_USING_RTC is not set diff --git a/bsp/k230/board/Kconfig b/bsp/k230/board/Kconfig index bae60bb9902..92c78665606 100644 --- a/bsp/k230/board/Kconfig +++ b/bsp/k230/board/Kconfig @@ -1,4 +1,8 @@ menu "Drivers Configuration" + + config BSP_USING_GNNE + bool "Enable KPU and AI2D" + default n menuconfig BSP_USING_SPI bool "Enable SPI" @@ -32,6 +36,10 @@ menu "Drivers Configuration" default n if BSP_USING_I2C + config BSP_USING_I2C_DMA + bool "Enable I2C with DMA" + default n + config BSP_USING_I2C0 bool "Enable I2C0" default n diff --git a/bsp/k230/drivers/interdrv/gnne/SConscript b/bsp/k230/drivers/interdrv/gnne/SConscript new file mode 100644 index 00000000000..4cca7123719 --- /dev/null +++ b/bsp/k230/drivers/interdrv/gnne/SConscript @@ -0,0 +1,19 @@ +# RT-Thread building script for gnne component + +from building import * + +cwd = GetCurrentDir() +src = Glob('*.c') +CPPPATH = [cwd] + +group = DefineGroup('Gnne', src, depend = ['BSP_USING_GNNE'], CPPPATH = CPPPATH) + +objs = [group] + +list = os.listdir(cwd) + +for item in list: + if os.path.isfile(os.path.join(cwd, item, 'SConscript')): + objs = objs + SConscript(os.path.join(item, 'SConscript')) + +Return('objs') diff --git a/bsp/k230/drivers/interdrv/gnne/ai2d_dev.c b/bsp/k230/drivers/interdrv/gnne/ai2d_dev.c new file mode 100644 index 00000000000..fbf922c7d6b --- /dev/null +++ b/bsp/k230/drivers/interdrv/gnne/ai2d_dev.c @@ -0,0 +1,227 @@ +/* Copyright (c) 2023, Canaan Bright Sight Co., Ltd + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND + * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/* + * Copyright (c) 2006-2025 RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include "drv_hardlock.h" +#include "board.h" + +#if defined(RT_USING_POSIX_DEVIO) + #include + #include + #include +#endif + +#define AI2D_CMD_LOCK 0 +#define AI2D_CMD_TRYLOCK 1 +#define AI2D_CMD_UNLOCK 2 +static hardlock_type g_ai2d_lock = HARDLOCK_MAX; + +struct ai_2d_dev_handle +{ + rt_wqueue_t *wait; + rt_bool_t is_lock; +}; + + +#define ai_2d_log(s...) rt_kprintf(s) + +#define ai_2d_err(s...) do { \ + ai_2d_log("[%s:%d] ", __func__, __LINE__); \ + ai_2d_log(s); \ + ai_2d_log("\r\n"); \ +} while (0) + +static struct rt_device g_ai_2d_device = {0}; +static struct rt_event g_ai_2d_event = {0}; +extern void *gnne_base_addr; + +static int ai_2d_device_open(struct dfs_file *file) +{ + struct ai_2d_dev_handle *handle; + rt_device_t device; + + handle = rt_malloc(sizeof(struct ai_2d_dev_handle)); + if (handle == RT_NULL) + { + ai_2d_err("malloc failed\n"); + return -1; + } + device = (rt_device_t)file->vnode->data; + handle->wait = &device->wait_queue; + handle->is_lock = RT_FALSE; + file->data = (void *)handle; + return RT_EOK; +} + +static int ai_2d_device_close(struct dfs_file *file) +{ + struct ai_2d_dev_handle *handle; + + handle = (struct ai_2d_dev_handle *)file->data; + if (handle == RT_NULL) + { + ai_2d_err("try to close a invalid handle"); + return -RT_EINVAL; + } + if (handle->is_lock) + { + kd_hardlock_unlock(g_ai2d_lock); + } + rt_free(handle); + file->data = RT_NULL; + return RT_EOK; +} + +static int ai_2d_device_ioctl(struct dfs_file *file, int cmd, void *args) +{ + struct ai_2d_dev_handle *handle; + int ret = -1; + + handle = (struct ai_2d_dev_handle *)file->data; + if (g_ai2d_lock == HARDLOCK_MAX) + return ret; + + if (cmd == AI2D_CMD_LOCK) + { + if (handle->is_lock == RT_TRUE) + { + return 0; + } + while (kd_hardlock_lock(g_ai2d_lock)); + handle->is_lock = RT_TRUE; + ret = 0; + } + else if (cmd == AI2D_CMD_UNLOCK) + { + if (handle->is_lock == RT_FALSE) + { + return 0; + } + kd_hardlock_unlock(g_ai2d_lock); + handle->is_lock = RT_FALSE; + ret = 0; + } + else if (cmd == AI2D_CMD_TRYLOCK) + { + if (handle->is_lock == RT_TRUE) + { + return 0; + } + if (!kd_hardlock_lock(g_ai2d_lock)) + { + handle->is_lock = RT_TRUE; + ret = 0; + } + } + return ret; +} + +int ai_2d_device_poll(struct dfs_file *file, struct rt_pollreq *req) +{ + struct ai_2d_dev_handle *handle; + unsigned int flags; + handle = (struct ai_2d_dev_handle *)file->data; + if (!handle) + { + ai_2d_err("ai_2d_dev_handle NULL!"); + return -EINVAL; + } + rt_event_recv(&g_ai_2d_event, 0x01, RT_EVENT_FLAG_OR | RT_EVENT_FLAG_CLEAR, RT_WAITING_FOREVER, NULL); + rt_poll_add(handle->wait, req); + return POLLIN; +} + +static const struct dfs_file_ops ai_2d_input_fops = +{ + .open = ai_2d_device_open, + .close = ai_2d_device_close, + .ioctl = ai_2d_device_ioctl, + .poll = ai_2d_device_poll, +}; + +static void irq_callback(int irq, void *data) +{ + rt_wqueue_t *wait = (rt_wqueue_t *)data; + volatile rt_uint32_t *write_addr = (rt_uint32_t *)((char *)gnne_base_addr + 0xca0); + if (gnne_base_addr == RT_NULL) + { + ai_2d_err("ai2d interrupts while the hardware is not yet initialized\n"); + } + write_addr[0] = 1; + write_addr[1] = 0; + write_addr[2] = 0; + write_addr[3] = 0; + rt_wqueue_wakeup(wait, (void *)POLLIN); + rt_event_send(&g_ai_2d_event, 0x1); +} + +int ai_2d_device_init(void) +{ + int ret = 0; + rt_isr_handler_t old_handler; + rt_device_t ai_2d_device = &g_ai_2d_device; + + ret = rt_event_init(&g_ai_2d_event, "ai_2d_event", RT_IPC_FLAG_PRIO); + if (ret) + { + ai_2d_err("event init failed\n"); + return -ENOMEM; + } + + ret = rt_device_register(ai_2d_device, "ai_2d_device", RT_DEVICE_FLAG_RDWR); + if (ret) + { + ai_2d_err("ai_2d_device register fail\n"); + return ret; + } + + rt_wqueue_init(&ai_2d_device->wait_queue); + old_handler = rt_hw_interrupt_install(K230_IRQ_AI_2D, irq_callback, &ai_2d_device->wait_queue, "ai_2d_irq"); + if (old_handler == RT_NULL) + { + ai_2d_err("ai_2d_device interrupt install fail\n"); + return -RT_ERROR; + } + rt_hw_interrupt_umask(K230_IRQ_AI_2D); + + ai_2d_device->fops = &ai_2d_input_fops; + + if (kd_request_lock(HARDLOCK_AI2D)) + { + ai_2d_err("fail to request hardlock-%d\n", HARDLOCK_AI2D); + } + else + { + g_ai2d_lock = HARDLOCK_AI2D; + } + return RT_EOK; +} diff --git a/bsp/k230/drivers/interdrv/gnne/ai_module.c b/bsp/k230/drivers/interdrv/gnne/ai_module.c new file mode 100644 index 00000000000..b9d5592aabc --- /dev/null +++ b/bsp/k230/drivers/interdrv/gnne/ai_module.c @@ -0,0 +1,49 @@ +/* Copyright (c) 2023, Canaan Bright Sight Co., Ltd + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND + * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/* + * NOTE: Currently untested - nncase cannot run due to missing mmz library. + * The mmz library depends on MPP driver, which relies on deprecated RT-Thread + * kernel APIs (rt_proc_entry_create, rt_dma_chan_request, etc.) that are no + * longer available in the mainline kernel. Awaiting resolution. + */ + +/* + * Copyright (c) 2006-2025 RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +extern int gnne_device_init(void); +extern int ai_2d_device_init(void); + +int ai_module_init(void) +{ + gnne_device_init(); + ai_2d_device_init(); +} +INIT_COMPONENT_EXPORT(ai_module_init); diff --git a/bsp/k230/drivers/interdrv/gnne/gnne_dev.c b/bsp/k230/drivers/interdrv/gnne/gnne_dev.c new file mode 100644 index 00000000000..df1934dbc09 --- /dev/null +++ b/bsp/k230/drivers/interdrv/gnne/gnne_dev.c @@ -0,0 +1,237 @@ +/* Copyright (c) 2023, Canaan Bright Sight Co., Ltd + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND + * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/* + * Copyright (c) 2006-2025 RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include "io.h" +#include +#include "board.h" +#include "drv_hardlock.h" + +#if defined(RT_USING_POSIX_DEVIO) + #include + #include + #include +#endif + +struct gnne_dev_handle +{ + rt_wqueue_t *wait; + rt_bool_t is_lock; +}; + +#define gnne_log(s...) rt_kprintf(s) + +#define gnne_err(s...) do { \ + gnne_log("[%s:%d] ", __func__, __LINE__); \ + gnne_log(s); \ + gnne_log("\r\n"); \ +} while (0) + +#define GNNE_CMD_LOCK 0 +#define GNNE_CMD_TRYLOCK 1 +#define GNNE_CMD_UNLOCK 2 + +static struct rt_device g_gnne_device = {0}; +static struct rt_event g_gnne_event = {0}; +void *gnne_base_addr = RT_NULL; +static hardlock_type g_kpu_lock = HARDLOCK_MAX; + +static int gnne_device_open(struct dfs_file *file) +{ + struct gnne_dev_handle *handle; + rt_device_t device; + + handle = rt_malloc(sizeof(struct gnne_dev_handle)); + if (handle == RT_NULL) + { + gnne_err("malloc failed\n"); + return -1; + } + device = (rt_device_t)file->vnode->data; + handle->wait = &device->wait_queue; + handle->is_lock = RT_FALSE; + file->data = (void *)handle; + return RT_EOK; +} + +static int gnne_device_close(struct dfs_file *file) +{ + struct gnne_dev_handle *handle; + + handle = (struct gnne_dev_handle *)file->data; + if (handle == RT_NULL) + { + gnne_err("try to close a invalid handle"); + return -RT_EINVAL; + } + if (handle->is_lock) + { + kd_hardlock_unlock(g_kpu_lock); + } + rt_free(handle); + file->data = RT_NULL; + return RT_EOK; +} + +static int gnne_device_ioctl(struct dfs_file *file, int cmd, void *args) +{ + struct gnne_dev_handle *handle; + int ret = -1; + handle = (struct gnne_dev_handle *)file->data; + if ((g_kpu_lock == HARDLOCK_MAX)) + { + return ret; + } + if (cmd == GNNE_CMD_LOCK) + { + if (handle->is_lock == RT_TRUE) + { + return 0; + } + while (kd_hardlock_lock(g_kpu_lock)); + handle->is_lock = RT_TRUE; + ret = 0; + } + else if (cmd == GNNE_CMD_UNLOCK) + { + if (handle->is_lock == RT_FALSE) + { + return 0; + } + kd_hardlock_unlock(g_kpu_lock); + handle->is_lock = RT_FALSE; + ret = 0; + } + else if (cmd == GNNE_CMD_TRYLOCK) + { + if (handle->is_lock == RT_TRUE) + { + return 0; + } + if (!kd_hardlock_lock(g_kpu_lock)) + { + handle->is_lock = RT_TRUE; + ret = 0; + } + } + return ret; +} + +int gnne_device_poll(struct dfs_file *file, struct rt_pollreq *req) +{ + struct gnne_dev_handle *handle; + unsigned int flags; + handle = (struct gnne_dev_handle *)file->data; + if (!handle) + { + gnne_err("gnne_dev_handle NULL!"); + return -EINVAL; + } + rt_event_recv(&g_gnne_event, 0x01, RT_EVENT_FLAG_OR | RT_EVENT_FLAG_CLEAR, RT_WAITING_FOREVER, NULL); + rt_poll_add(handle->wait, req); + return POLLIN; +} + +static const struct dfs_file_ops gnne_input_fops = +{ + .open = gnne_device_open, + .close = gnne_device_close, + .ioctl = gnne_device_ioctl, + .poll = gnne_device_poll, +}; + +static void irq_callback(int irq, void *data) +{ + rt_wqueue_t *wait = (rt_wqueue_t *)data; + volatile void *write_addr = (void *)((char *)gnne_base_addr + 0x128); + if (gnne_base_addr == RT_NULL) + { + gnne_err("gnne interrupts while the hardware is not yet initialized\n"); + } + /*clear kpu intr*/ + __iowmb(); + *(rt_uint64_t *)write_addr = 0x400000004; + rt_wqueue_wakeup(wait, (void *)POLLIN); + rt_event_send(&g_gnne_event, 0x1); +} + +int gnne_device_init(void) +{ + int ret = 0; + rt_isr_handler_t old_handler; + rt_device_t gnne_device = &g_gnne_device; + + ret = rt_event_init(&g_gnne_event, "gnne_event", RT_IPC_FLAG_PRIO); + if (ret) + { + gnne_err("event init failed\n"); + return -ENOMEM; + } + + ret = rt_device_register(gnne_device, "gnne_device", RT_DEVICE_FLAG_RDWR); + if (ret) + { + gnne_err("gnne_device register fail\n"); + return ret; + } + + + /*rt_ioremap maps the size of at least one page*/ + gnne_base_addr = rt_ioremap((void *)KPU_BASE_ADDR, (KPU_IO_SIZE + FFT_IO_SIZE + AI2D_IO_SIZE)); + if (gnne_base_addr == RT_NULL) + { + gnne_err("gnne ioremap error\n"); + return -1; + } + + rt_wqueue_init(&gnne_device->wait_queue); + old_handler = rt_hw_interrupt_install(K230_IRQ_GNNE, irq_callback, &gnne_device->wait_queue, "gnne_irq"); + if (old_handler == RT_NULL) + { + gnne_err("gnne_device interrupt install fail\n"); + return -RT_ERROR; + } + rt_hw_interrupt_umask(K230_IRQ_GNNE); + + gnne_device->fops = &gnne_input_fops; + + if (kd_request_lock(HARDLOCK_KPU)) + { + gnne_err("fail to request hardlock-%d\n", HARDLOCK_KPU); + } + else + { + g_kpu_lock = HARDLOCK_KPU; + } + + return RT_EOK; +} diff --git a/bsp/k230/drivers/interdrv/hardlock/drv_hardlock.h b/bsp/k230/drivers/interdrv/hardlock/drv_hardlock.h index d62f6d8f798..74fd0c5e5ea 100644 --- a/bsp/k230/drivers/interdrv/hardlock/drv_hardlock.h +++ b/bsp/k230/drivers/interdrv/hardlock/drv_hardlock.h @@ -39,6 +39,7 @@ typedef enum k230_hardlock_type HARDLOCK_AES = 7, HARDLOCK_SM4 = 8, HARDLOCK_PDMA = 9, + HARDLOCK_AI2D = 10, HARDLOCK_MAX = 128 } hardlock_type; diff --git a/bsp/k230/drivers/interdrv/i2c/drv_i2c.c b/bsp/k230/drivers/interdrv/i2c/drv_i2c.c index 627db8e2e4f..778624b5d6d 100644 --- a/bsp/k230/drivers/interdrv/i2c/drv_i2c.c +++ b/bsp/k230/drivers/interdrv/i2c/drv_i2c.c @@ -33,9 +33,11 @@ #include #include #include +#include #include "board.h" #include "drv_i2c.h" #include "sysctl_clk.h" +#include "drv_pdma.h" #undef DBG_TAG #undef DBG_LVL @@ -43,6 +45,42 @@ #define DBG_LVL DBG_INFO #include +/* + * Note: + * - When DMA is enabled, the PDMA driver requires both the address and + * data to be 4-byte aligned.(Address alignment is handled internally + * by this driver, so application developers do not need to worry about + * address alignment.) Therefore, when using DMA for read/write operations, + * if the data size is not 4-byte aligned, even with DMA enabled, the driver + * will actually use CPU polling for read/write. Application code should be + * aware of this and handle it accordingly. For example, if the data length + * to be read or written is not 4-byte aligned, you can split the data into + * an aligned part and an unaligned part, use DMA for the aligned part, and + * use CPU polling for the unaligned part. + */ + +#ifdef BSP_USING_I2C_DMA + +#define K230_I2C_PDMA_CH_INVALID 0xFF +#define K230_I2C_PDMA_CACHE_LINE_SIZE 64 + +struct _i2c_pdma_cfg +{ + rt_event_t event; + rt_uint8_t ch; + usr_pdma_cfg_t cfg; + device_sel_e tx_dev; + device_sel_e rx_dev; +}; + +typedef enum +{ + K230_I2C_PDMA_EVENT_NONE = 0x00, + K230_I2C_PDMA_EVENT_COMPLETE = 0x01, + K230_I2C_PDMA_EVENT_TIMEOUT = 0x02, +} k230_i2c_pdma_event_t; +#endif + struct _i2c_speed_cfg { rt_uint16_t hcnt; @@ -55,13 +93,22 @@ struct k230_i2c_dev struct rt_i2c_bus_device dev; const char *name; rt_ubase_t base; + rt_ubase_t base_pa; size_t size; int vector; rt_uint32_t clock; struct rt_i2c_msg *msg; struct _i2c_speed_cfg speed_cfg; +#ifdef BSP_USING_I2C_DMA + struct _i2c_pdma_cfg pdma_cfg; +#endif }; +#ifdef BSP_USING_I2C_DMA +static rt_err_t k230_i2c_pdma_read(struct k230_i2c_dev *dev); +static rt_err_t k230_i2c_pdma_write(struct k230_i2c_dev *dev); +#endif + static rt_size_t k230_i2c_get_timer(rt_size_t base) { return rt_tick_get() - base ; @@ -76,7 +123,7 @@ static void k230_i2c_enable(struct k230_i2c_dev *dev, rt_bool_t enable) do { i2c->enable.enable = en_value; - if(i2c->enable_status.en == en_value) + if (i2c->enable_status.en == en_value) { return; } @@ -87,7 +134,7 @@ static void k230_i2c_enable(struct k230_i2c_dev *dev, rt_bool_t enable) * 25us) as described in the DesignWare I2C databook. */ rt_hw_us_delay(25); - }while(timeout--); + } while(timeout--); LOG_E("timeout in %s i2c\n", enable ? "enable" : "disable"); } @@ -120,15 +167,15 @@ static int k230_i2c_set_bus_speed(struct k230_i2c_dev *dev, rt_uint32_t speed) dev->speed_cfg.hcnt = period - dev->speed_cfg.lcnt; dev->speed_cfg.spklen = spklen; - if(speed <= I2C_STANDARD_SPEED_UP) + if (speed <= I2C_STANDARD_SPEED_UP) { i2c_spd = I2C_SPEED_MODE_STANDARD; } - else if(speed <= I2C_FAST_SPEED_UP) + else if (speed <= I2C_FAST_SPEED_UP) { i2c_spd = I2C_SPEED_MODE_FAST; } - else if(speed <= I2C_MAX_SPEED_UP) + else if (speed <= I2C_MAX_SPEED_UP) { i2c_spd = I2C_SPEED_MODE_MAX; } @@ -140,7 +187,7 @@ static int k230_i2c_set_bus_speed(struct k230_i2c_dev *dev, rt_uint32_t speed) /* to set speed cltr must be disabled */ k230_i2c_enable(dev, RT_FALSE); - switch(i2c_spd) + switch (i2c_spd) { case I2C_SPEED_MODE_STANDARD: i2c->ss_ufm_scl_hcnt.cnt = dev->speed_cfg.hcnt; @@ -179,7 +226,7 @@ static void k230_i2c_set_addr(struct k230_i2c_dev *dev) /* Disable i2c */ k230_i2c_enable(dev, RT_FALSE); - if(dev->msg->flags & RT_I2C_ADDR_10BIT || dev->dev.flags & RT_I2C_ADDR_10BIT) + if (dev->msg->flags & RT_I2C_ADDR_10BIT || dev->dev.flags & RT_I2C_ADDR_10BIT) { i2c->tar.master_10bit_addr = 1; i2c_addr &= 0x3FF; @@ -200,7 +247,7 @@ static void k230_i2c_flush_rxfifo(struct k230_i2c_dev *dev) { volatile i2c_t *i2c = (i2c_t *)dev->base; - while(i2c->status.rfne) + while (i2c->status.rfne) { readl(&i2c->data_cmd); } @@ -211,10 +258,10 @@ static int k230_i2c_wait_for_bus_busy(struct k230_i2c_dev *dev) rt_size_t start_time = k230_i2c_get_timer(0); volatile i2c_t *i2c = (i2c_t *)dev->base; - while((i2c->status.mst_activity) || !(i2c->status.tfe)) + while ((i2c->status.mst_activity) || !(i2c->status.tfe)) { /* Evaluate timeout */ - if(k230_i2c_get_timer(start_time) > (rt_size_t)dev->dev.timeout * I2C_TX_FIFO_SIZE) + if (k230_i2c_get_timer(start_time) > (rt_size_t)dev->dev.timeout * I2C_TX_FIFO_SIZE) { return -RT_ETIMEOUT; } @@ -226,9 +273,8 @@ static int k230_i2c_wait_for_bus_busy(struct k230_i2c_dev *dev) static int k230_i2c_xfer_init(struct k230_i2c_dev *dev) { volatile i2c_t *i2c = (i2c_t *)dev->base; - rt_uint8_t addr = 0; - if(k230_i2c_wait_for_bus_busy(dev) != RT_EOK) + if (k230_i2c_wait_for_bus_busy(dev) != RT_EOK) { return -RT_EBUSY; } @@ -245,7 +291,7 @@ static int k230_i2c_xfer_finish(struct k230_i2c_dev *dev) while (1) { - if(i2c->raw_intr_stat.stop_det) + if (i2c->raw_intr_stat.stop_det) { readl(&i2c->clr_stop_det); break; @@ -267,8 +313,15 @@ static int k230_i2c_xfer_finish(struct k230_i2c_dev *dev) return RT_EOK; } -static int _k230_i2c_read(struct k230_i2c_dev *dev) +static int k230_i2c_read(struct k230_i2c_dev *dev) { +#ifdef BSP_USING_I2C_DMA + if (dev->msg->len % 4 == 0) + { + return k230_i2c_pdma_read(dev); + } +#endif + volatile i2c_t *i2c = (i2c_t *)dev->base; rt_size_t start_time_rx = 0; rt_uint32_t recv_len = dev->msg->len; @@ -277,24 +330,24 @@ static int _k230_i2c_read(struct k230_i2c_dev *dev) rt_uint32_t cmd = 0; /* If no start condition is sent before reading, then send a repeated start. */ - if(dev->msg->flags & RT_I2C_NO_START) + if (dev->msg->flags & RT_I2C_NO_START) { cmd |= I2C_DATA_CMD_RESTART; } else { - if(k230_i2c_xfer_init(dev) != RT_EOK) + if (k230_i2c_xfer_init(dev) != RT_EOK) { return -RT_EBUSY; } } start_time_rx = k230_i2c_get_timer(0); - while(recv_len || tran_len) + while (recv_len || tran_len) { if (tran_len) { - while(i2c->status.tfnf == 0); + while (i2c->status.tfnf == 0); /* Write stop when the last byte */ cmd = tran_len == 1 ? cmd | I2C_DATA_CMD_STOP : cmd; /* Write to data cmd register to trigger i2c */ @@ -303,13 +356,13 @@ static int _k230_i2c_read(struct k230_i2c_dev *dev) tran_len--; } - if(i2c->status.rfne) + if (i2c->status.rfne) { *buffer++ = i2c->data_cmd.dat; recv_len--; start_time_rx = k230_i2c_get_timer(0); } - else if(k230_i2c_get_timer(start_time_rx) > dev->dev.timeout) + else if (k230_i2c_get_timer(start_time_rx) > dev->dev.timeout) { return -RT_ETIMEOUT; } @@ -317,14 +370,20 @@ static int _k230_i2c_read(struct k230_i2c_dev *dev) return k230_i2c_xfer_finish(dev); } -static int _k230_i2c_write(struct k230_i2c_dev *dev) +static int k230_i2c_write(struct k230_i2c_dev *dev) { +#ifdef BSP_USING_I2C_DMA + if (dev->msg->len % 4 == 0) + { + return k230_i2c_pdma_write(dev); + } +#endif + volatile i2c_t *i2c = (i2c_t *)dev->base; rt_size_t start_time_tx = 0; rt_uint32_t tran_len = dev->msg->len; rt_uint8_t *buffer = dev->msg->buf; rt_uint32_t cmd = 0; - rt_uint32_t cut = 0; if (k230_i2c_xfer_init(dev) != RT_EOK) { @@ -332,12 +391,12 @@ static int _k230_i2c_write(struct k230_i2c_dev *dev) } start_time_tx = k230_i2c_get_timer(0); - while(tran_len) + while (tran_len) { - if(i2c->status.tfnf) + if (i2c->status.tfnf) { /* If there is no stop flag, the stop condition will not be sent at the last byte. */ - if(tran_len == 1 && !(dev->msg->flags & RT_I2C_NO_STOP)) + if (tran_len == 1 && !(dev->msg->flags & RT_I2C_NO_STOP)) { cmd |= I2C_DATA_CMD_STOP; } @@ -351,7 +410,7 @@ static int _k230_i2c_write(struct k230_i2c_dev *dev) tran_len--; start_time_tx = k230_i2c_get_timer(0); } - else if(k230_i2c_get_timer(start_time_tx) > dev->dev.timeout) + else if (k230_i2c_get_timer(start_time_tx) > dev->dev.timeout) { return -RT_ETIMEOUT; } @@ -381,14 +440,15 @@ static rt_ssize_t k230_i2c_xfer(struct rt_i2c_bus_device *bus, struct rt_i2c_msg { i2c_dev->msg = msgs; - if(msgs->flags & RT_I2C_RD) + if (msgs->flags & RT_I2C_RD) { - ret = _k230_i2c_read(i2c_dev); + ret = k230_i2c_read(i2c_dev); } else { - ret = _k230_i2c_write(i2c_dev); + ret = k230_i2c_write(i2c_dev); } + if (ret != RT_EOK) { return -RT_EIO; @@ -410,7 +470,7 @@ static rt_err_t k230_i2c_control(struct rt_i2c_bus_device *bus, int cmd, void *a { /* set 10-bit addr mode */ case RT_I2C_DEV_CTRL_10BIT: - if(arg & RT_I2C_ADDR_10BIT) + if (arg & RT_I2C_ADDR_10BIT) { i2c_dev->dev.flags |= RT_I2C_ADDR_10BIT; } @@ -467,52 +527,372 @@ static struct k230_i2c_dev k230_i2c_devs[] = #ifdef BSP_USING_I2C0 { .name = "i2c0", - .base = I2C0_BASE_ADDR, + .base_pa = I2C0_BASE_ADDR, .size = I2C0_IO_SIZE, .vector = K230_IRQ_I2C0, +#ifdef BSP_USING_I2C_DMA + .pdma_cfg.tx_dev = I2C0_TX, + .pdma_cfg.rx_dev = I2C0_RX, +#endif }, #endif #ifdef BSP_USING_I2C1 { .name = "i2c1", - .base = I2C1_BASE_ADDR, + .base_pa = I2C1_BASE_ADDR, .size = I2C1_IO_SIZE, .vector = K230_IRQ_I2C1, +#ifdef BSP_USING_I2C_DMA + .pdma_cfg.tx_dev = I2C1_TX, + .pdma_cfg.rx_dev = I2C1_RX, +#endif }, #endif #ifdef BSP_USING_I2C2 { .name = "i2c2", - .base = I2C2_BASE_ADDR, + .base_pa = I2C2_BASE_ADDR, .size = I2C2_IO_SIZE, .vector = K230_IRQ_I2C2, +#ifdef BSP_USING_I2C_DMA + .pdma_cfg.tx_dev = I2C2_TX, + .pdma_cfg.rx_dev = I2C2_RX, +#endif }, #endif #ifdef BSP_USING_I2C3 { .name = "i2c3", - .base = I2C3_BASE_ADDR, + .base_pa = I2C3_BASE_ADDR, .size = I2C3_IO_SIZE, .vector = K230_IRQ_I2C3, +#ifdef BSP_USING_I2C_DMA + .pdma_cfg.tx_dev = I2C3_TX, + .pdma_cfg.rx_dev = I2C3_RX, +#endif }, #endif #ifdef BSP_USING_I2C4 { .name = "i2c4", - .base = I2C4_BASE_ADDR, + .base_pa = I2C4_BASE_ADDR, .size = I2C4_IO_SIZE, .vector = K230_IRQ_I2C4, +#ifdef BSP_USING_I2C_DMA + .pdma_cfg.tx_dev = I2C4_TX, + .pdma_cfg.rx_dev = I2C4_RX, +#endif }, #endif }; +#ifdef BSP_USING_I2C_DMA +static void k230_i2c_pdma_call_back(rt_uint8_t ch, rt_bool_t is_done) +{ + k230_i2c_pdma_event_t event_type = is_done ? K230_I2C_PDMA_EVENT_COMPLETE : K230_I2C_PDMA_EVENT_TIMEOUT; + for (rt_uint8_t i = 0; i < sizeof(k230_i2c_devs)/sizeof(k230_i2c_devs[0]); i++) + { + struct k230_i2c_dev *dev = &k230_i2c_devs[i]; + if (dev->pdma_cfg.event != RT_NULL && dev->pdma_cfg.ch == ch && dev->pdma_cfg.ch != K230_I2C_PDMA_CH_INVALID) + { + rt_event_send(dev->pdma_cfg.event, event_type); + return; + } + } +} + +static void k230_i2c_pdma_cleanup(struct k230_i2c_dev *dev) +{ + rt_uint8_t ch = dev->pdma_cfg.ch; + + if (ch == K230_I2C_PDMA_CH_INVALID) + { + return; + } + + dev->pdma_cfg.ch = K230_I2C_PDMA_CH_INVALID; + k230_pdma_release_channel(ch); +} + +static rt_err_t k230_i2c_pdma_read(struct k230_i2c_dev *dev) +{ + volatile i2c_t *i2c = (i2c_t *)dev->base; + rt_uint8_t *buffer = dev->msg->buf; + rt_uint8_t *buf; + void *buf_pa; + rt_err_t err; + rt_uint8_t ch; + rt_uint32_t recv_event, read_len; + rt_size_t start_time_tx = 0; + rt_uint32_t cmd = 0; + + err = k230_pdma_request_channel(&ch); + if (err != RT_EOK) + { + LOG_E("i2c pdma request channel failed"); + return err; + } + dev->pdma_cfg.ch = ch; + + err = k230_pdma_set_callback(ch, k230_i2c_pdma_call_back); + if (err != RT_EOK) + { + LOG_E("i2c pdma set callback failed"); + k230_i2c_pdma_cleanup(dev); + return err; + } + + read_len = dev->msg->len; + + buf = (rt_uint8_t *)rt_malloc_align(read_len, K230_I2C_PDMA_CACHE_LINE_SIZE); + if (buf == RT_NULL) + { + LOG_E("i2c pdma malloc buffer failed"); + k230_i2c_pdma_cleanup(dev); + return -RT_ENOMEM; + } + buf_pa = rt_kmem_v2p(buf); + if (buf_pa == RT_NULL) + { + LOG_E("i2c pdma get phy addr failed"); + k230_i2c_pdma_cleanup(dev); + rt_free_align(buf); + return -RT_ERROR; + } + + rt_event_control(dev->pdma_cfg.event, RT_IPC_CMD_RESET, NULL); + + dev->pdma_cfg.cfg.device = dev->pdma_cfg.rx_dev; + dev->pdma_cfg.cfg.src_addr = (rt_uint8_t *)(dev->base_pa + 0x10); + dev->pdma_cfg.cfg.dst_addr = (rt_uint8_t *)buf_pa; + dev->pdma_cfg.cfg.line_size = read_len; + dev->pdma_cfg.cfg.pdma_ch_cfg.ch_src_type = FIXED; + dev->pdma_cfg.cfg.pdma_ch_cfg.ch_dev_hsize = PSBYTE1; + dev->pdma_cfg.cfg.pdma_ch_cfg.ch_dat_endian = PDEFAULT; + dev->pdma_cfg.cfg.pdma_ch_cfg.ch_dev_blen = PBURST_LEN_4; + dev->pdma_cfg.cfg.pdma_ch_cfg.ch_priority = 7; + dev->pdma_cfg.cfg.pdma_ch_cfg.ch_dev_tout = 0xFFF; + + err = k230_pdma_config(ch, &dev->pdma_cfg.cfg); + if (err != RT_EOK) + { + LOG_E("i2c pdma config failed"); + k230_i2c_pdma_cleanup(dev); + rt_free_align(buf); + return err; + } + + /* If no start condition is sent before reading, then send a repeated start. */ + if (dev->msg->flags & RT_I2C_NO_START) + { + cmd |= I2C_DATA_CMD_RESTART; + } + else + { + if (k230_i2c_xfer_init(dev) != RT_EOK) + { + LOG_E("i2c pdma xfer init failed"); + k230_i2c_pdma_cleanup(dev); + rt_free_align(buf); + return -RT_EBUSY; + } + } + + start_time_tx = k230_i2c_get_timer(0); + err = k230_pdma_start(ch); + if (err != RT_EOK) + { + LOG_E("i2c pdma start failed"); + k230_i2c_pdma_cleanup(dev); + rt_free_align(buf); + return err; + } + + for (rt_uint32_t i = 0; i < read_len; i++) + { + while (i2c->status.tfnf == 0); + /* Write stop when the last byte */ + cmd = i == (read_len - 1) ? I2C_DATA_CMD_STOP : 0; + /* Write to data cmd register to trigger i2c */ + writel(cmd | I2C_DATA_CMD_READ, &i2c->data_cmd); + cmd = 0; + } + + err = rt_event_recv(dev->pdma_cfg.event, + K230_I2C_PDMA_EVENT_COMPLETE | K230_I2C_PDMA_EVENT_TIMEOUT, + RT_EVENT_FLAG_OR | RT_EVENT_FLAG_CLEAR, + RT_WAITING_FOREVER, + &recv_event); + + if (err != RT_EOK || (recv_event & K230_I2C_PDMA_EVENT_TIMEOUT)) + { + LOG_E("i2c pdma read timeout"); + k230_pdma_stop(ch); + k230_i2c_pdma_cleanup(dev); + rt_free_align(buf); + return -RT_ETIMEOUT; + } + + rt_memcpy(buffer, buf, read_len); + + k230_pdma_stop(ch); + k230_i2c_pdma_cleanup(dev); + rt_free_align(buf); + + if (k230_i2c_get_timer(start_time_tx) > dev->dev.timeout) + { + return -RT_ETIMEOUT; + } + + return k230_i2c_xfer_finish(dev); +} + +static inline rt_uint32_t k230_i2c_make_data_cmd(rt_uint8_t data, rt_uint32_t flags) +{ + return (rt_uint32_t)data | flags; +} + +static rt_err_t k230_i2c_pdma_write(struct k230_i2c_dev *dev) +{ + volatile i2c_t *i2c = (i2c_t *)dev->base; + rt_uint8_t *buffer = dev->msg->buf; + rt_uint32_t *buf; + void *buf_pa; + rt_err_t err; + rt_uint8_t ch; + rt_uint32_t recv_event, tran_len, flags; + rt_size_t start_time_tx = 0; + + err = k230_pdma_request_channel(&ch); + if (err != RT_EOK) + { + LOG_E("i2c pdma request channel failed"); + return err; + } + dev->pdma_cfg.ch = ch; + + err = k230_pdma_set_callback(ch, k230_i2c_pdma_call_back); + if (err != RT_EOK) + { + LOG_E("i2c pdma set callback failed"); + k230_i2c_pdma_cleanup(dev); + return err; + } + + tran_len = dev->msg->len; + + buf = (rt_uint32_t *)rt_malloc_align(tran_len * sizeof(rt_uint32_t), K230_I2C_PDMA_CACHE_LINE_SIZE); + if (buf == RT_NULL) + { + LOG_E("i2c pdma malloc buffer failed"); + k230_i2c_pdma_cleanup(dev); + return -RT_ENOMEM; + } + for (rt_uint32_t i = 0; i < tran_len; i++) + { + flags = 0; + + if (i == (tran_len - 1) && !(dev->msg->flags & RT_I2C_NO_STOP)) + { + flags |= I2C_DATA_CMD_STOP; + } + + buf[i] = k230_i2c_make_data_cmd(buffer[i], flags); + } + + buf_pa = rt_kmem_v2p(buf); + if (buf_pa == RT_NULL) + { + LOG_E("i2c pdma get phy addr failed"); + k230_i2c_pdma_cleanup(dev); + rt_free_align(buf); + return -RT_ERROR; + } + + rt_event_control(dev->pdma_cfg.event, RT_IPC_CMD_RESET, NULL); + + dev->pdma_cfg.cfg.device = dev->pdma_cfg.tx_dev; + dev->pdma_cfg.cfg.src_addr = (rt_uint8_t *)buf_pa; + dev->pdma_cfg.cfg.dst_addr = (rt_uint8_t *)(dev->base_pa + 0x10); + dev->pdma_cfg.cfg.line_size = tran_len * sizeof(rt_uint32_t); + dev->pdma_cfg.cfg.pdma_ch_cfg.ch_src_type = CONTINUE; + dev->pdma_cfg.cfg.pdma_ch_cfg.ch_dev_hsize = PSBYTE4; + dev->pdma_cfg.cfg.pdma_ch_cfg.ch_dat_endian = PDEFAULT; + dev->pdma_cfg.cfg.pdma_ch_cfg.ch_dev_blen = PBURST_LEN_4; + dev->pdma_cfg.cfg.pdma_ch_cfg.ch_priority = 7; + dev->pdma_cfg.cfg.pdma_ch_cfg.ch_dev_tout = 0xFFF; + + err = k230_pdma_config(ch, &dev->pdma_cfg.cfg); + if (err != RT_EOK) + { + LOG_E("i2c pdma config failed"); + k230_i2c_pdma_cleanup(dev); + rt_free_align(buf); + return err; + } + + if (k230_i2c_xfer_init(dev) != RT_EOK) + { + k230_i2c_pdma_cleanup(dev); + rt_free_align(buf); + return -RT_EBUSY; + } + + start_time_tx = k230_i2c_get_timer(0); + err = k230_pdma_start(ch); + if (err != RT_EOK) + { + LOG_E("i2c pdma start failed"); + k230_i2c_pdma_cleanup(dev); + rt_free_align(buf); + return err; + } + + err = rt_event_recv(dev->pdma_cfg.event, + K230_I2C_PDMA_EVENT_COMPLETE | K230_I2C_PDMA_EVENT_TIMEOUT, + RT_EVENT_FLAG_OR | RT_EVENT_FLAG_CLEAR, + RT_WAITING_FOREVER, + &recv_event); + + if (err != RT_EOK || (recv_event & K230_I2C_PDMA_EVENT_TIMEOUT)) + { + LOG_E("i2c pdma write timeout"); + k230_pdma_stop(ch); + k230_i2c_pdma_cleanup(dev); + rt_free_align(buf); + return -RT_ETIMEOUT; + } + + k230_pdma_stop(ch); + k230_i2c_pdma_cleanup(dev); + rt_free_align(buf); + + if (k230_i2c_get_timer(start_time_tx) > dev->dev.timeout) + { + return -RT_ETIMEOUT; + } + + return RT_EOK; +} + +static void k230_i2c_pdma_init(struct k230_i2c_dev *dev) +{ + volatile i2c_t *i2c = (i2c_t *)dev->base; + + i2c->dma_cr.tdmae = 1; + i2c->dma_cr.rdmae = 1; + i2c->dma_tdlr.dmatdl = 15; + i2c->dma_rdlr.dmardl = 3; +} +#endif + int rt_hw_i2c_init(void) { int i; for (i = 0; i < sizeof(k230_i2c_devs) / sizeof(k230_i2c_devs[0]); i++) { - k230_i2c_devs[i].base = (rt_ubase_t)rt_ioremap((void *)k230_i2c_devs[i].base, k230_i2c_devs[i].size); + k230_i2c_devs[i].base = (rt_ubase_t)rt_ioremap((void *)k230_i2c_devs[i].base_pa, k230_i2c_devs[i].size); k230_i2c_devs[i].dev.ops = &k230_i2c_ops; k230_i2c_devs[i].clock = sysctl_clk_get_leaf_freq(SYSCTL_CLK_I2C0_CORE + i); @@ -521,6 +901,21 @@ int rt_hw_i2c_init(void) k230_i2c_set_bus_speed(&k230_i2c_devs[i], I2C_DEFAULT_SPEED); rt_i2c_bus_device_register(&k230_i2c_devs[i].dev, k230_i2c_devs[i].name); LOG_I("i2c%d master mode, i2c%d clock=%dHz\n", i, i, k230_i2c_devs[i].clock); + +#ifdef BSP_USING_I2C_DMA + k230_i2c_pdma_init(&k230_i2c_devs[i]); + k230_i2c_devs[i].pdma_cfg.ch = K230_I2C_PDMA_CH_INVALID; + k230_i2c_devs[i].pdma_cfg.event = rt_event_create(k230_i2c_devs[i].name, RT_IPC_FLAG_FIFO); + if (k230_i2c_devs[i].pdma_cfg.event == RT_NULL) + { + LOG_E("i2c pdma event(%s) create failed", k230_i2c_devs[i].name); + for (int j = 0; j < i; j++) + { + rt_event_delete(k230_i2c_devs[j].pdma_cfg.event); + } + return -RT_ENOMEM; + } +#endif } return RT_EOK; diff --git a/bsp/k230/drivers/utest/test_i2c.c b/bsp/k230/drivers/utest/test_i2c.c index a6a379dd86f..f319fb4c11d 100644 --- a/bsp/k230/drivers/utest/test_i2c.c +++ b/bsp/k230/drivers/utest/test_i2c.c @@ -48,7 +48,15 @@ * 1. 测试I2C0主机模式 * 主机模式下，主机向从机发送16字节数据（不包括写读地址）， * 然后再读取回来进行校验，共执行两次，分别是400kHz和1MHz速率。 - * 注：使用的从机为AT24C08 EEPROM，设备地址为0x50。 + * 第一次写数据时，带一字节地址，总共写16字节数据，读取15字节数据， + * 第二次写数据时，带一字节地址，总共写17字节数据，读取16字节数据。 + * 在两次写数据的过程中，如果开启dma功能，第一次会调用dma进行写， + * 第二次会调用dma进行读。（前提是BSP_USING_I2C_DMA宏被定义， + * 因为pdma要求地址与数据都要4字节对齐（地址的对齐问题会在驱动 + * 内部处理），若写/读数据大小非4字节对齐，即使启用了dma功能， + * 实际也是调用的cpu轮询读写，这一点需要应用程序注意并处理） + * 注：使用的从机为AT24C08 EEPROM，设备地址为0x50， + * page size 为 16 字节。 */ #define I2C_NAME "i2c0" @@ -88,12 +96,12 @@ static int test_i2c_check_pin(void) { test_i2c0_deinit_pin(); - if(kd_pin_read(I2C_SCL_PIN) != 1 || kd_pin_read(I2C_SDA_PIN) != 1) + if (kd_pin_read(I2C_SCL_PIN) != 1 || kd_pin_read(I2C_SDA_PIN) != 1) { LOG_W("i2c bus is not idle, try to recover it."); k230_pinctrl_set_oe(I2C_SCL_PIN, 1); kd_pin_mode(I2C_SCL_PIN, GPIO_DM_OUTPUT); - for(rt_uint8_t i = 0; i < 9; i++) + for (rt_uint8_t i = 0; i < 9; i++) { kd_pin_write(I2C_SCL_PIN, 0); rt_hw_us_delay(2); @@ -104,7 +112,7 @@ static int test_i2c_check_pin(void) kd_pin_mode(I2C_SCL_PIN, GPIO_DM_INPUT); } - if(kd_pin_read(I2C_SCL_PIN) != 1 || kd_pin_read(I2C_SDA_PIN) != 1) + if (kd_pin_read(I2C_SCL_PIN) != 1 || kd_pin_read(I2C_SDA_PIN) != 1) { LOG_E("i2c bus recover failed"); return -RT_ERROR; @@ -131,7 +139,7 @@ static void _test_i2c0_master(rt_uint8_t *buffer_w, rt_uint8_t *buffer_r, rt_uin msgs[0].buf = buffer_w; msgs[0].len = size + 1; - if(rt_i2c_transfer(dev, msgs, 1) != 1) + if (rt_i2c_transfer(dev, msgs, 1) != 1) { LOG_E("i2c transfer failed"); uassert_true(0); @@ -149,17 +157,18 @@ static void _test_i2c0_master(rt_uint8_t *buffer_w, rt_uint8_t *buffer_r, rt_uin msgs[1].buf = &buffer_r[1]; msgs[1].len = size; - if(rt_i2c_transfer(dev, msgs, 2) != 2) + if (rt_i2c_transfer(dev, msgs, 2) != 2) { LOG_E("i2c transfer failed"); uassert_true(0); } LOG_I("Read data:\n"); - for(rt_uint8_t i = 1; i < size + 1; i++) + for (rt_uint8_t i = 1; i < size + 1; i++) { LOG_I("0x%02X ", buffer_r[i]); } + uassert_buf_equal(buffer_w + 1, buffer_r + 1, size); } @@ -174,13 +183,15 @@ static void test_i2c0_master(void) buffer_w[0] = 0x00; // memory address memset(buffer_r, 0x00, TEST_BUFFER_SIZE + 1); - _test_i2c0_master(buffer_w, buffer_r, size, speed); + /* if BSP_USING_I2C_DMA is enabled, test i2c write with dma */ + _test_i2c0_master(buffer_w, buffer_r, size - 1, speed); speed = 1000000; // 1MHz memset(buffer_w + 1, 0x55, TEST_BUFFER_SIZE); buffer_w[0] = 0x00; // memory address memset(buffer_r, 0x00, TEST_BUFFER_SIZE + 1); + /* if BSP_USING_I2C_DMA is enabled, test i2c read with dma */ _test_i2c0_master(buffer_w, buffer_r, size, speed); } diff --git a/bsp/k230/rtconfig.h b/bsp/k230/rtconfig.h index 63d97d8f2cf..e0a4e114508 100644 --- a/bsp/k230/rtconfig.h +++ b/bsp/k230/rtconfig.h @@ -503,10 +503,6 @@ /* GD32 Drivers */ /* end of GD32 Drivers */ - -/* HPMicro SDK */ - -/* end of HPMicro SDK */ /* end of HAL & SDK Drivers */ /* sensors drivers */ diff --git a/bsp/rockchip/rk3568/.config b/bsp/nxp/imx/imx91/.config similarity index 95% rename from bsp/rockchip/rk3568/.config rename to bsp/nxp/imx/imx91/.config index 9ddecd59f09..b03e676ecf5 100644 --- a/bsp/rockchip/rk3568/.config +++ b/bsp/nxp/imx/imx91/.config @@ -116,30 +116,29 @@ CONFIG_RT_KLIBC_USING_VSNPRINTF_LOG10_TAYLOR_TERMS=4 # end of rt_strnlen options # end of klibc options -CONFIG_RT_NAME_MAX=12 +CONFIG_RT_NAME_MAX=16 # CONFIG_RT_USING_ARCH_DATA_TYPE is not set # CONFIG_RT_USING_NANO is not set # CONFIG_RT_USING_SMART is not set # CONFIG_RT_USING_AMP is not set -CONFIG_RT_USING_SMP=y -CONFIG_RT_CPUS_NR=4 -CONFIG_RT_ALIGN_SIZE=8 +# CONFIG_RT_USING_SMP is not set +CONFIG_RT_CPUS_NR=1 +CONFIG_RT_ALIGN_SIZE=16 # CONFIG_RT_THREAD_PRIORITY_8 is not set CONFIG_RT_THREAD_PRIORITY_32=y # CONFIG_RT_THREAD_PRIORITY_256 is not set CONFIG_RT_THREAD_PRIORITY_MAX=32 -CONFIG_RT_TICK_PER_SECOND=100 +CONFIG_RT_TICK_PER_SECOND=1000 CONFIG_RT_USING_OVERFLOW_CHECK=y CONFIG_RT_USING_HOOK=y CONFIG_RT_HOOK_USING_FUNC_PTR=y # CONFIG_RT_USING_HOOKLIST is not set CONFIG_RT_USING_IDLE_HOOK=y CONFIG_RT_IDLE_HOOK_LIST_SIZE=4 -CONFIG_IDLE_THREAD_STACK_SIZE=4096 -CONFIG_SYSTEM_THREAD_STACK_SIZE=4096 +CONFIG_IDLE_THREAD_STACK_SIZE=8192 CONFIG_RT_USING_TIMER_SOFT=y CONFIG_RT_TIMER_THREAD_PRIO=4 -CONFIG_RT_TIMER_THREAD_STACK_SIZE=4096 +CONFIG_RT_TIMER_THREAD_STACK_SIZE=8192 # CONFIG_RT_USING_TIMER_ALL_SOFT is not set # CONFIG_RT_USING_CPU_USAGE_TRACER is not set @@ -154,8 +153,6 @@ CONFIG_RT_DEBUGING_ASSERT=y CONFIG_RT_DEBUGING_COLOR=y CONFIG_RT_DEBUGING_CONTEXT=y # CONFIG_RT_DEBUGING_AUTO_INIT is not set -# CONFIG_RT_DEBUGING_SPINLOCK is not set -# CONFIG_RT_DEBUGING_CRITICAL is not set # CONFIG_RT_USING_CI_ACTION is not set # @@ -176,26 +173,24 @@ CONFIG_RT_USING_MESSAGEQUEUE=y CONFIG_RT_USING_MEMPOOL=y CONFIG_RT_USING_SMALL_MEM=y # CONFIG_RT_USING_SLAB is not set -CONFIG_RT_USING_MEMHEAP=y -CONFIG_RT_MEMHEAP_FAST_MODE=y -# CONFIG_RT_MEMHEAP_BEST_MODE is not set +# CONFIG_RT_USING_MEMHEAP is not set CONFIG_RT_USING_SMALL_MEM_AS_HEAP=y # CONFIG_RT_USING_MEMHEAP_AS_HEAP is not set # CONFIG_RT_USING_SLAB_AS_HEAP is not set # CONFIG_RT_USING_USERHEAP is not set # CONFIG_RT_USING_NOHEAP is not set -CONFIG_RT_USING_MEMTRACE=y +# CONFIG_RT_USING_MEMTRACE is not set # CONFIG_RT_USING_HEAP_ISR is not set CONFIG_RT_USING_HEAP=y # end of Memory Management CONFIG_RT_USING_DEVICE=y -CONFIG_RT_USING_DEVICE_OPS=y +# CONFIG_RT_USING_DEVICE_OPS is not set # CONFIG_RT_USING_INTERRUPT_INFO is not set -# CONFIG_RT_USING_THREADSAFE_PRINTF is not set +CONFIG_RT_USING_THREADSAFE_PRINTF=y CONFIG_RT_USING_CONSOLE=y CONFIG_RT_CONSOLEBUF_SIZE=128 -CONFIG_RT_CONSOLE_DEVICE_NAME="uart2" +CONFIG_RT_CONSOLE_DEVICE_NAME="uart1" CONFIG_RT_VER_NUM=0x50201 # CONFIG_RT_USING_STDC_ATOMIC is not set CONFIG_RT_BACKTRACE_LEVEL_MAX_NR=32 @@ -204,13 +199,13 @@ CONFIG_RT_BACKTRACE_LEVEL_MAX_NR=32 # # AArch64 Architecture Configuration # -CONFIG_ARCH_TEXT_OFFSET=0x200000 -CONFIG_ARCH_RAM_OFFSET=0 +CONFIG_ARCH_TEXT_OFFSET=0x0 +CONFIG_ARCH_RAM_OFFSET=0x80000000 CONFIG_ARCH_SECONDARY_CPU_STACK_SIZE=4096 CONFIG_ARCH_HAVE_EFFICIENT_UNALIGNED_ACCESS=y CONFIG_ARCH_USING_GENERIC_CPUID=y -CONFIG_ARCH_HEAP_SIZE=0x4000000 -CONFIG_ARCH_INIT_PAGE_SIZE=0x200000 +CONFIG_ARCH_HEAP_SIZE=0x2000000 +CONFIG_ARCH_INIT_PAGE_SIZE=0x8000000 # end of AArch64 Architecture Configuration CONFIG_ARCH_CPU_64BIT=y @@ -225,7 +220,7 @@ CONFIG_ARCH_ARM_CORTEX_A=y CONFIG_RT_NO_USING_GIC=y CONFIG_ARCH_ARM_CORTEX_A55=y # CONFIG_ARCH_ARM_SECURE_MODE is not set -# CONFIG_RT_BACKTRACE_FUNCTION_NAME is not set +CONFIG_RT_BACKTRACE_FUNCTION_NAME=y CONFIG_ARCH_ARMV8=y CONFIG_ARCH_USING_ASID=y CONFIG_ARCH_USING_HW_THREAD_SELF=y @@ -244,7 +239,7 @@ CONFIG_RT_USING_FINSH=y CONFIG_FINSH_USING_MSH=y CONFIG_FINSH_THREAD_NAME="tshell" CONFIG_FINSH_THREAD_PRIORITY=20 -CONFIG_FINSH_THREAD_STACK_SIZE=4096 +CONFIG_FINSH_THREAD_STACK_SIZE=8092 CONFIG_FINSH_USING_HISTORY=y CONFIG_FINSH_HISTORY_LINES=5 # CONFIG_FINSH_USING_WORD_OPERATION is not set @@ -261,7 +256,22 @@ CONFIG_FINSH_USING_OPTION_COMPLETION=y # # DFS: device virtual file system # -# CONFIG_RT_USING_DFS is not set +CONFIG_RT_USING_DFS=y +CONFIG_DFS_USING_POSIX=y +CONFIG_DFS_USING_WORKDIR=y +# CONFIG_RT_USING_DFS_MNTTABLE is not set +CONFIG_DFS_FD_MAX=16 +CONFIG_RT_USING_DFS_V1=y +# CONFIG_RT_USING_DFS_V2 is not set +CONFIG_DFS_FILESYSTEMS_MAX=4 +CONFIG_DFS_FILESYSTEM_TYPES_MAX=4 +# CONFIG_RT_USING_DFS_ELMFAT is not set +CONFIG_RT_USING_DFS_DEVFS=y +# CONFIG_RT_USING_DFS_ROMFS is not set +# CONFIG_RT_USING_DFS_CROMFS is not set +# CONFIG_RT_USING_DFS_RAMFS is not set +# CONFIG_RT_USING_DFS_TMPFS is not set +# CONFIG_RT_USING_DFS_MQUEUE is not set # end of DFS: device virtual file system # CONFIG_RT_USING_FAL is not set @@ -269,7 +279,7 @@ CONFIG_FINSH_USING_OPTION_COMPLETION=y # # Device Drivers # -CONFIG_RT_USING_DM=y +# CONFIG_RT_USING_DM is not set # CONFIG_RT_USING_DEV_BUS is not set CONFIG_RT_USING_DEVICE_IPC=y CONFIG_RT_UNAMED_PIPE_NUMBER=64 @@ -277,7 +287,7 @@ CONFIG_RT_UNAMED_PIPE_NUMBER=64 CONFIG_RT_USING_SERIAL=y CONFIG_RT_USING_SERIAL_V1=y # CONFIG_RT_USING_SERIAL_V2 is not set -# CONFIG_RT_SERIAL_USING_DMA is not set +CONFIG_RT_SERIAL_USING_DMA=y CONFIG_RT_SERIAL_RB_BUFSZ=64 # CONFIG_RT_USING_SERIAL_BYPASS is not set # CONFIG_RT_USING_CAN is not set @@ -295,12 +305,7 @@ CONFIG_RT_SERIAL_RB_BUFSZ=64 # CONFIG_RT_USING_INPUT_CAPTURE is not set # CONFIG_RT_USING_MTD_NOR is not set # CONFIG_RT_USING_MTD_NAND is not set -CONFIG_RT_USING_PM=y -CONFIG_PM_TICKLESS_THRESHOLD_TIME=2 -# CONFIG_PM_USING_CUSTOM_CONFIG is not set -# CONFIG_PM_ENABLE_DEBUG is not set -# CONFIG_PM_ENABLE_SUSPEND_SLEEP_MODE is not set -# CONFIG_PM_ENABLE_THRESHOLD_SLEEP_MODE is not set +# CONFIG_RT_USING_PM is not set # CONFIG_RT_USING_RTC is not set # CONFIG_RT_USING_SDIO is not set # CONFIG_RT_USING_SPI is not set @@ -311,26 +316,10 @@ CONFIG_PM_TICKLESS_THRESHOLD_TIME=2 # CONFIG_RT_USING_LCD is not set # CONFIG_RT_USING_HWCRYPTO is not set # CONFIG_RT_USING_WIFI is not set -# CONFIG_RT_USING_LED is not set -# CONFIG_RT_USING_MBOX is not set -# CONFIG_RT_USING_PHYE is not set # CONFIG_RT_USING_BLK is not set -# CONFIG_RT_USING_SCSI is not set -# CONFIG_RT_USING_REGULATOR is not set -# CONFIG_RT_USING_RESET is not set -# CONFIG_RT_USING_THERMAL is not set # CONFIG_RT_USING_VIRTIO is not set -# CONFIG_RT_USING_DMA is not set -# CONFIG_RT_USING_MFD is not set -CONFIG_RT_USING_OFW=y -# CONFIG_RT_USING_BUILTIN_FDT is not set -CONFIG_RT_FDT_EARLYCON_MSG_SIZE=128 -CONFIG_RT_USING_OFW_BUS_RANGES_NUMBER=8 -# CONFIG_RT_USING_PIC is not set CONFIG_RT_USING_PIN=y -# CONFIG_RT_USING_PINCTRL is not set # CONFIG_RT_USING_KTIME is not set -CONFIG_RT_USING_CLK=y # CONFIG_RT_USING_HWTIMER is not set # CONFIG_RT_USING_CHERRYUSB is not set # end of Device Drivers @@ -412,15 +401,13 @@ CONFIG_RT_USING_ADT_REF=y # CONFIG_RT_USING_RT_LINK is not set # end of Utilities -# CONFIG_RT_USING_VBUS is not set - # # Memory management # +# CONFIG_RT_PAGE_MPR_SIZE_DYNAMIC is not set CONFIG_RT_PAGE_AFFINITY_BLOCK_SIZE=0x1000 CONFIG_RT_PAGE_MAX_ORDER=11 -CONFIG_RT_USING_MEMBLOCK=y -CONFIG_RT_INIT_MEMORY_REGIONS=128 +# CONFIG_RT_USING_MEMBLOCK is not set # # Debugging @@ -439,6 +426,7 @@ CONFIG_RT_INIT_MEMORY_REGIONS=128 # end of Using USB legacy version # CONFIG_RT_USING_FDT is not set +# CONFIG_RT_USING_RUST is not set # end of RT-Thread Components # @@ -1475,22 +1463,15 @@ CONFIG_RT_INIT_MEMORY_REGIONS=128 # end of Arduino libraries # end of RT-Thread online packages -CONFIG_SOC_RK3568=y +CONFIG_BOARD_IMX91=y +CONFIG_SOC_MIMX91X1D=y # # Hardware Drivers Config # -CONFIG_BSP_USING_UART=y -# CONFIG_RT_USING_UART0 is not set -# CONFIG_RT_USING_UART1 is not set -CONFIG_RT_USING_UART2=y -# CONFIG_RT_USING_UART3 is not set -# CONFIG_RT_USING_UART4 is not set -# CONFIG_RT_USING_UART5 is not set -# CONFIG_RT_USING_UART6 is not set -# CONFIG_RT_USING_UART7 is not set -# CONFIG_RT_USING_UART8 is not set -# CONFIG_RT_USING_UART9 is not set +CONFIG_BSP_USING_EARLY_CONSOLE=y +CONFIG_BSP_USING_UART1=y CONFIG_BSP_USING_GIC=y CONFIG_BSP_USING_GICV3=y +CONFIG_KERNEL_ASPACE_START=0x1000000 # end of Hardware Drivers Config diff --git a/bsp/nxp/imx/imx91/Kconfig b/bsp/nxp/imx/imx91/Kconfig new file mode 100644 index 00000000000..38ff35d75da --- /dev/null +++ b/bsp/nxp/imx/imx91/Kconfig @@ -0,0 +1,29 @@ +mainmenu "RT-Thread Project Configuration" + +BSP_DIR := . + +RTT_DIR := ../../../.. + +PKGS_DIR := packages + +source "$(RTT_DIR)/Kconfig" +osource "$PKGS_DIR/Kconfig" + +config BOARD_IMX91 + bool + select ARCH_ARM_CORTEX_A55 + select BSP_USING_GICV3 + select BSP_USING_GIC + default y + +config SOC_MIMX91X1D + bool + select ARCH_ARMV8 + select ARCH_CPU_64BIT + select RT_USING_CACHE + select RT_USING_COMPONENTS_INIT + select RT_USING_USER_MAIN + select ARCH_ARM_BOOTWITH_FLUSH_CACHE + default y + +source "$(BSP_DIR)/drivers/Kconfig" diff --git a/bsp/nxp/imx/imx91/Makefile b/bsp/nxp/imx/imx91/Makefile new file mode 100644 index 00000000000..f9b884d9d3b --- /dev/null +++ b/bsp/nxp/imx/imx91/Makefile @@ -0,0 +1,10 @@ +scons:=python ${SCONS}\scons.py + +all: + @$(scons) + +clean: + @$(scons) -c + +copy: + @$(scons) --copy -s diff --git a/bsp/nxp/imx/imx91/README.assets/GS-FRDM-IMX91-IMG1.webp b/bsp/nxp/imx/imx91/README.assets/GS-FRDM-IMX91-IMG1.webp new file mode 100644 index 0000000000000000000000000000000000000000..3fd5b168742e81ac2b76b70f0dc58c90bcef59cd GIT binary patch literal 74792 zcmb@tbC4&^wl?}}8`HLJ+nTnGY1_7KPTR(`ZQHhOTX){Q&pzkG7vKHkM%;|3$fs7V zsLWcKwJO(ovJ@r6#0W@$0BWK_@~ZM2>d*iHfZ*=|0SdSW21p1C%fkZyJp};6S{Yh9 z0wV$d);3NKia&)2)HO5-AT|I%089V~fD*u|Z|Gmt3(SAVqVRuYw)p@6$Kzjl-2cc7(g1+wU;qGP?SEt>xc~q{5CG6L zZRqUa^6xePSbytrpivM*umng;m?uPjR0V7n!duEXCJgQbF)#&Jol8qQ53umsbgw_= z-QM&4rwrfUe`g876(JDdh95Kwhzb()0hljKJX?yikeH~X!K1VWIo#Cd{Sv7!Aa2uq z_yK?Ox-8x&>y!T8`?a`)fmo@H6)7@s<3_ z^Z>u(JO1nO-TCu;?tADf<)iuO`@Z|3yXW2QyK!%P;k)F!@vHi?xekAV@55*PefjnK zGkfH_{~P}m?)3VEzw3MC8~H2o`{xIJT|^(9_o!?2x$oKc^>^VD zf{EthX$aU4JVY628)UVh`e+nvGGIQYTx{HWsDh zCF1aPzT&SXk^y_5HUKZS6G__vK@;8ht8&q!X_5SnlG09!rk5y3lpd}@{eJE3?b|p8 z&Cmv^XeBXfZK{Y=9n2Ci3mH9GHm(_MAuT^>pl8NZVXW!gCuJtFQot~z!_9x6PVvz! zpN!*2BIF>cYtYkIt0!gDt#*rZ@MOpQP(|%1p^C3zy~Al_UH)iOvDnlR(O3qKXI+3H zqd2;*iW<%)!ZZ2QOI<)55Y#m`n;zI;Qk?$ybEQg>wQ36pK3ZNZ3$>dan19iXMNi9# zCmH*ZUkBE|1D#iEMrO|ar6e~6%SFM8&$|tJa$}L21iQeroQiHj#?1|{W?i*|mf1R}!Cjaz)MSf#+eox_g zex5^^65D9{vB#D$Q^iEabcx^p4BAde{KeJL&}NfznIVTS#q>fmk1(6Ayzr3aUJj(O zS7sv7v(9UkqA!@3+r0%WgvlS<5#Julp8v}bZ$!`#fbVOp_k6ct|fz!3K zZlP%QLCgqb$mA~_3WraaM-dGk@RbO+YNOAMXaRy6+4|~`t86+93FEdv=JWDW!+AAV~w$vp6?&wm=0Efr;#QaviynvmmIeefx2rT;)1wj8H$ z79ER}%=$lNeLWIN+kO3}X}qx_CE9U@kf9}J(sarI35NyRNc-3U{El?woO|}(bV`WR zcU|emdM)R`&1uH!i4R1gx6OtGSD?h#49jU(jV0yINu@EN21yoMt5!Yh)GB|}w9oX$ zg_nHrq2K26?a`I?3&vzEh^p;CCOPUR(+jvGnYK0=&QYBTZg>gq{`8`8Cseuf=oQZYO!H=yvrV<~At)~dd0hL*ihGb| zVYow(Ncd$XS7~)TRU0vX#6T!18k(X9ABDzZzTaJ|^iQpcI3=Sa(bqQD;SgfLIv7w+ zdZe>{DG;E4_)^XCBvq9g^mdoZIb|Rfpb%M_1h%5EfmN9YXu*MQDXz2Iki>MLc?WeF zgOarzLD|{Ypb$Ffp`RsbRpcpsRnUgWs#S{xNt3t!+h~raefbT;uA@R#P3*q?K5ue9 z>1b*^at-np4BHvp7(MX4j>SNVg|c54DS7Ulh)W&oly}jMTBa6{aL~3ju%I&5d!bU( zEy#XSNU_dV=DCo+R@naQx&NA=;=)g)S9b(D`eS4eUOUWYMJVI9crx-ZP+mRjV>|uZ z;}D8hsAJ4eG|td`PEp2Ax;LfND~}Cf_|c0UyNDWi|Z> z`*XB>nmaJZ-%q(A*3iKCAdF2*%oHLdcX%smflkdaJ)KX&rKqtegC*~a+ly8XPZ%OZ z>i~HEE_v_wib?2})bsixInF19zOy9qL?sNpZs9i(+EiJx$35_J2;qBQd@-%;*g-un zAg4z56bLyK>;KG`zjh1G*w4RX^lbaniJyemt{@l<%rr6eVC#2(#}pv-Th{r!!HPN% z@@@#B$_XB<#Ibmw&d@%2lM%SXSUi|d2>iV9+-@?+@gU}#eeQ*4iH#U1F^&9lJ;1)% zH1A%U!&R^pt>Xtla+#r6ghH<0OZK_=sX1)2X0=p4Wyhr>_w4sHtbrEzz+@0{R7=l3 zj{bip4CgIegXt--TSz-BGh6L?F?K`tus$oRla!)`hye~68&H~TE_GcPKaR%nLq?+` z!AVtz=>vodT>R8?IIAH6Z(>I=%af_oI=U-?izCj~xBy?Y%tkuJv?AymqbonyBHyJy zdhrRJm>6;PNaYcu$Nl%TG z2o?AWj76qzgyF`m5tZ8@t!a8(m{=5}L5W_SKEhq{qP!TxdRPCux7p!%tx@ANgkQl27*f`7lX7sP|;SUNZqCg0x^#|FJ7dH1A6%Fh`#{gX{BalETqAr z4e3lHW-o@~<-vh9U(M$Xf_LJqjyqyXsh~?@)^-6ywVliy!0{#1#yrb=29A+IgfH4N9tdJ+`6*rS6-QO++l zOU;oiP_A9T=QiEZdTg)vr{Tla=x>d=3Q)B#?pdwZS%$U8GkmC%%HNh}0AXGF#O+!kj0hX>e@=ELU?eP+Zt>*|X-ZD(&N zrx`KK&e@r%F7hes-l^-0Q@xe29~!pX9Q`kfo2}gQa@y!N`!eV$E1XBt-=6-+T;_y6 z_{8a#!YJt{OCmE0?T3un|8~F~XXflbDi)g;FtIkZQwuGtL4+Z4M1CnEDaze@RFr3G z$}?=yzX>)dVc8EP)pjk8DTev?Mb5n!Fy;#=hE%9;w@%wFs_K(N{%mC`=BDE(i%!WG zG6g;|CyAgKRdQ8O&*=ev$6-ugRZVvdSa{liO6f;o+db+0W2+3tx9dU7f_Kh-A&7;K z3~_z$cLF&i(`I#d0NfBBM8B5H?-jpKc;lh(uGmxj+w@ ziTKp6Ei}(0TfkMAb*#u}F%t{OYWGjwWTBiPq<<}<%%s;}cLz}`VH)B)VBg`YHBs2CQa;eMV9M*9B+h6Gzg5FlI!0Ej%R2A1FwfgA$vkEzf5*J0KpYv z7LHLjIFzKK&R*Mq1;0ZqdIAiCD_t-5ITEjp>+8U44O~R{CHkA^`u8PU>Tx0O@ z;DB1l<)2Qx7y>J$hEP+uWH$f(0d^D6f*56&6V1)3GgvozkAFp0Z!QSnHU+VcB0aDR zJ3YtFYfM1V=)Dwmlp>qVFf2s{)|G*s98Nf1_!=)%OkqEXXjYExEW`}oTTI9?bF2O^ zp;G?fOhlv|j?O!-PkIS^iw_gVY1acENJY_Not)G?=>o;jt@#<931+&h3@g)kK2hs5 z-dd$~@>Ck&Q&y(k0aP?Eq6?=_8_(bpmf=sp04DMLiG)>&!wcp>Z(Qv55-l87+6-(> z7*3b-LVwQ+BLtJ{XIhGiEXBD;rqKxFOj`ajlyD!tTk!7%RL9d4^m^xjtupw+G*!7qm3w&U!_5QqgwGkucjiEXB=Ak%&{tMZOA)D{<#xOLzM48X+@5vD-vNEKJ z>H0dKOaeSKd9V=nYouMXWKvw4*j($%upMvA(9VLo$gu|8*NGx#eoev!<~|Op0g!G7 z>UL;cjznUsBBcb$u;s>KZdP%Wb?fyA?EjAMESR|39Kjk^nj7(2R`3yQabUeWdvNCY zpmpPaQQt9n1C!Gl5)15|3?tQL8(dHB5tbv}M&`aMn;ybgZ~T@b*iX8nKH87_))x)& zJUFjyv|B64hMf{?T!KM%&`1Qr$Z8VYk#3=}ty^gRLV5N;f1UzH3i5Afq=L#YWSl-3 z!rY#|C}|h^q#fC@-m}ws)MbEP{QcH(5*Ijw6oNv2D(kw;H+|IkS>oj%d#*%b(Dfr= z?lAUq!O=-br9JvgIF!3c9FvPWi@FJ_wutgtDQgZSeRLuuBgh9ld3tXTABq0KGXyMrIap<+hH24yEs21N(QOP6tq>+4jeZD}Op?W-j$uK zxsShmxwIexve({T(1J7URe1A-nXH+D0?nMKX&&w%_f7D2N5kEzXlwgyHOwtUfw+yW zQhpd*4OanSQTv=Z`M%$Hp1SsiLWh}l zEmUJms-LN}U>$-{$Fn5hXxILmxakETN6$NySZ+Xy(_C`lhTm z2UP~OhFnuZ_>RpV9c?2kB&k{I2q*|pnO9B2}Bg?H|Y@pi0xxsdJ_%8<h{?W6wg8ody|XA?^fbqTv2l$8z3X0q0jXSym?-DTqStp~9$Xc)<{!!+`K6E*4U#hV`S_hnJ& z?5&vW$$WT&Ea^`DALE$XWUe9g^B=)@c9!ex4iey}-Kr2=S02#1^i=0m>-}S0Md2^PIu>}(F3p3QT zST{|03c>Wq#&|g_EF_DgnvzF63mPv-0WQ-<@gY60%^G2s51)fWsPHyrXh7Ru9C$aF zCd{Ih9$57(hXZ-z$R@`l;S@+$!d(^{fy$Oz6lOhm2iM@tpad8+euM zg6CCOP4m$pR zQ#;R($-f$w;G2KAv}$2F!e-TRyE6h6FA(V5yPd+0v&AKexq`FsnOF3HKM_wBlo#Pq zS6GVWSLCDPu$cl79E$OyXk?Ro>m7rs*4jJS9M@R3z>^3@>3nY|`$MulQP*)ui+<0% z`I@2_A+B0^(!L2)L+2+84Uzb1dEQQ$MF=~!qsfZK8a2usUJYm7X}{8p_0hh9pX5^f znvDrypr5xdscYuz;vm%OQI$ZjNW81TT7=wHexcuJ?&T9PcNv?VvgzuWwG&tP9L(5w zwaXVUoY$}SlIgh#vop?+Gd=59(Jy@*KM@M%<1Dd)Q_?O>PYy=Gp{}_D@=Fnp#PaXu z4t%{k4vmA(J-1>Sj@Nl6>-ihjt7fRAtbc>Lj^p?%<@EJ_>k4phxX?+)P#?DmoXEp3 z&Y}K_^i8KVA}fgR$JNFsr?bV9mf%VxGxJf6l+rfmWte8KPEQ-m>uY0*A(pEv?V%LM zBx!YHCKa683h#R%ccMkWWgusOT>VuZF@k1dZq#VjJl}D1tNp3WWTF~4y)}bB z2@$1!g^DcUzU|H)+@e+8dOH$<28+$lA<^M~=Fz3Z2Z{LHg|do`oe!DfD7$P$rF2G6 z6FUo}r!iU;5q!0e$@qp2oh5V1_QLf*o)dxR*P5TUXcTuig?n~gh&Ty_G(~ZkXqkUY zR;4&yf|HUsF!#ibYY>qKAoW4Gz7_0j<6>=R)KIh>$M-Hf%Lv&>b300;|6TS%N*O{G zlRIF(lv4nj1e3})oQ6-wOn3){g=9zd#=r2xp(%x{&4Ax!*I4jRl$qFMNQ!mciJ^Mt zG76A#xOM~>cmjQj6|2{IExC*0!bvwab^=d&b<7h|De|$w$o)|3*LM5{YzRyq5CQqY zNlUQ$Q-lIg%+0D5VZ&qA3`wdms@qWb+wD(B-WqG_4SX56=q9ZW#>L&+I4H_5eKeeF(qB*l>kSMy=zJ<*e2^x-7&ylsWo zXJIvFXd#TW&E`j%wdd~dB%zhbCSEYeY83iJmlTrsgF?Vq)po=g>ynUG;5KSo^!QpC za#KEtzMDPw>}*5>A?#E?K9$TMy0@>$_IoNW6c;8MSe`Rg&#ws$QC}2>Ya|mUv5K_O z+QqqW!RFsir-dSDUy`D9t)o{P#a-wqbbDaQ5rygY;ezHRA`qt1iG?u<9Cnd1#x>X* zs$nD{2-C@|W1UUcivquSexs^}*mSig$+$H0!1fP3V$Ui~i{z0ImKdAg*9JJYhqgE0)XbKY~Fe!FCR-n|@f~8d4iy=jc16CLQ@& z&026Uv2lci?u%mA&)l zb>kQ8Z)qBaryw|x8Z#!6i#!bJ&2^(9vGfPsj*0N(L;(ln+f{B)#NuF^h@ahc{a-Q~ zehA3T<-?xg6{JuR6bO=yX)C4g1d1L?@UK4tJ56>Pkdx&{HjYfiz~wf2Z3U_8aCOxR&(B-$_xu{g*_;e$+a- zRS`%SH=|z~mg~?Y<2Q;#Jc{>gLat1+p}9H~OwflYmY2s8&da9i$U6N|q$!c1iyXv( zfr0;mH+qjC{|0f1hd2(vY{VI-jdRSF2vxH;Cm)@1s}EqTO7MAl&~9i=lx5zFG+JR& z=c>DO)CKc$9p;l1`Dsibmxs|y-xV9evv~}H z6Mpz&cG7ACuPnFQT%EdL+hn(}VUMju8?G(}?|>=Vkw4WrHlBAXwT)i$*Gzq<6QJ8= zLx?|Jxi~|u@ID2u+||4o9d3gc!=rn`Hy!gR8+)SrEHd73b{i}{OZy%{5G6iTK6niy zwLFb($d~atTa^t{xm|jyD~2Iq3;<*|Yh7dbpcURC?n_u7H}$N~OfV7%-TO6|rL3w0 zCqNVjzWdBfB$CAs^zgtkn`LB(6I#T)ht5pM| z-SuBfmwYt80#((Hp^Ob+xmucD2|la+-K!$<+jaoVX=iCe^U8DcV)W46fCL?(w$vS( zJ+GIX^95eaSg<7Cyk1SInV^?PBVVny4Jt2bA=-*xwO4jlX=0a&9*=^7VO!*bTtZkQ45JHK#YWsL1i6bM`Rg1HyL!Ua7h{Jw{H4|wT{0cY$(2{g>(x_o*b-&r*}7$lFK^2WoA+ve9_`PbO$@{MuRkX*Ic8R zBl$OV;>RsgV=XZa%jSCtN>JM*CdZJIRRPEI1MHKfa~feYWpCb zuQ;_@JYjym*6Wke_Z*nNjcOXq8-Vo_Ov4MyXX@%#FCVY0i|A-;UiAo{I=yQ6!osID z%4t2dJm&@0cP$L2VmpmW)^+xf{<4wO2lG9G+Hj{*p&$w|V~hIi!#SkM`ByNoA84&s z<#iS%xtErW*$qa=tw=mBQFKebx-ldlqajkjmJ|&vB(6%|ojP{UEIHI;#Br-sXl-RLPEfO2vs$U+cT| zE^seVp0V&254~99mP-D7R71jTGt3w12O!hwq#T<6EZQ**|FeESGk7}Ez{Oer%Mc!k z&m`2(#L)18mS6ri>+&BSOLR*Tb%FvD}_fq(@Dh zTdXv1?94Erv~Vd<;RwS0LIpOv);Y$)w-Ts{Sjz2{%-*#9ER zkT&p&tHewowQT4@!BNwqaPls>dOk?${Y3XXMK$T`Qq{0k;tAH#`^0=FT8(1P0(KFi%2jzu}j2 z_|U<;A|aG~^`COi?EKVm>i!p3_LnZ)LlRWtQj;pqWXxijdKg!3=ECf~CPk5%-&}-l zt;49>r>#J9PxCQJ2%D#aI(=%C)@_Z2Xj)DlU7r`gq$IcP=9#$ewmbhpA`Vrk2F3P& z()|+LtL}x3tDS+8x}(whHEL;giA{D_xuHUgsbOzcPRKjCc^19Iq;o2L|D?uLi%Vf3 zP2UoJtmpZaS>3KI>YR2VVZEXFN*TID?>4u-w6>ex|3C_E zzwZh8F$~E$6!n6pu?!KtNQi7jV&LDgP(Lm1|Jk{Jwj~tD{8zTsFXev?=syth1@QGv zCGcMxO8%*M$6Z^w66J^7l}>P}EcRXA**K3t!|Of**!cin*6s<_m_>+OOGb}uoP$(63gEROp>Qp_ z*3r&<_G|-DJ-~v*Hs41af{yvMdTVT%LLoGw&C9O%OY-U;%?>mh94sQxYb}pDdvwf| zPXDaw><}t@^=x@owvtytRCFQ`;=*MHP|O=u7)h3i-(Q4u!cVO)lh)hC(4OsdbNfI( zz&vUEYEkmC(uYCoHkl7sR(2C$YfSBqLjvVA}gF z2_BU>t1IBr$~mXZ8@FT2A{dz#V8%RKVFVE1xxdHd(MtJkBd88c&0tdiNWNho}I&5pK@ta zecGZIr=b9G*6B!DWB`G*AtpcMk&XQRg58eTi4TgjUsM=n*(B9H^XY-f0IYe+0Npxv z#@bY2y5*JS!)-BjWkFEqC<-A40i;R4At7cNTyvROUxPwtU%GjkaWGk!3IA-#qw`Zq zg5DE*me6_YRC<>S9|Hj3Q@i~5mv>3?54f43Fkukty+G`ba^^`}exqG_YUGU6dg6W{ zbp1d>rH#GOuMm}nR>4wC5&}_~R=Ee7;tSqpxw=*{YSwyBLmlSk0uiSK&+wpEhHtpQ zv-lB6`$I0vqbfOblc@%qfQ5TPR(4-k4WX0{;3AN3Z`y(6p!IfnO{{ee9H07GA?vv+ zBHCzrSTX0UNZaB8Ov2a0?PIH!V;)o+4BkD3E~jp6OfTgP<)f}|1~gy5wm>Kl`(=t| z)wA1LosNAABH5)7u{>#x(#p>++R)}xp3lwh@V!j>%T)1$GBv6)Tp>jP!F9sCKbo{Y ztpa$Uv}B{FT07T1p})-6I!4m-ij{gzUm!#8?f$C9wgu^^qhLgHv{&BBlFa`UcHi+y zHK7&^zMY%?moHe!Jp~r)%GKOpf}xPTzKpxNLe)K~m5xr z4*NHi@j_o=a-`l-&$n}m&9dHsC<#Lc23T``m2tbs#4jlaYL|p9w6as%IH2%45l(FM zWxmK$+c4v!DHv~0aAJ%+aQ)G~uj(sc(CCD3w(x6D3?kfy*ny1MIAh?sfLXX7b#nx4 zF(v+o(9Usa>`#K?6O94c9D`>FoT-kie5+{(DN1^Q=5#WKlC0rSZ>UdWc+dXW*K%W! zbRM0vZ0PftG){T-kWM<5H$^;NioF$okoFjlPr}OK^O}D#p@b~kYzACyziA4}!;dET@Fp8@g zltWp{aJ1^o7SM1Y+cn1V;>u@ZJ1p$vwtWC5QTdJ;3>n?Gk72D^ zPA*ksNZ=&cu}9eqSJ*frj|Sb6lia{99|h!pj@w#Wcu?-Pj9R=2t`5I31Dx=EeEezC z8;a(1#i}QSU9i3DJ=0pJKzH${9V8e8ghELrVObp|7rYaw<2j96RBeeNRF< z?GG%cpJY6I=I^~g8tJD4jY*?*hd(ABVGfN&Lpv1n6>IE?YSjk%fL`p}tD(_SUsq7Pbo})Va%#?gL*_HWhtZJ?lDGJ*LSh|%Gx-KAAVmQ+s`yQuJhhA|!FT*fRcHkzKChX_H4pIuyc zk1{P8jI>SDd8#xoQfAgwCN4qe5;EvDb+4kXqIcZ#k)cOAAUkmRDFK@zllCbCBCL2Z0(s`LEr2A~S`D7wlgs)hwaAM8##gm3$lDvr2}5|t5!8t&0@ zDDfNORq`5da=9|Xh?8rhoPNq;Qd5U+9p<)n;1P}QkJk0OSnU8Xkq{s4&sUFGMyQ1q zdvy0g#IWX>-9k6$GQ~`RAl{MYG9iYU>lj~C1!qJ92O02Zh44Q@%AZu*$nnQP%gkK$ zRV9JU%rUAzn)FIb7bu2@9tNGh?m`PwXXA~v$IYS!&Jl*m>QmmXQBwF34H%bf~!YEn@HgWFDOm1fw6|Zb* z7bfn47UFKJ{t4kDcY9P8h6;YtQuGH>4t?XJCvAu?RhlGxL^ySPIYD^0$ucpnh5g9k zEzaCQCh7Ej-w=&2!XEPca=Ek%pnbA%Zl6rO3{Kp4uWEB<8>bNyJ_4_2T6>m;I)evA z1EKU z_^U2)C+faOz7&d*`vo!4km)$yiZ-3oDN@2Z+ovJL>e9EP+M6yo<;FE1i4Bg4q24Sb3{xyx9&+3 zoi=lGo{fYE-58lqp5FyU5>8E49|YJ5?1l)RIhDMF3}9C}F_NX&mn`1pX}mPmcqV^5 zz2P_}5Mo==b>8_|m(E|5?HtOCHtXTTF@PHxH9d-cKKhKekH36ksNad)H4il2xQqi0 z^*>dN<~)7kw<4z9xjhDiR~D5K7bmm}5mN)+$WSu38I4^@>>HGlAK(_k*{BIH5^n~m z>W~6#FDw}AcAgxP6HAUXx@gwKb?}y`unt?NC@I4AQ)fQ=Jq zhJTZkgfiH~DgomwIu0T@P>?w|a?u~L2rbVfD`o-!$S(EWwi8GsPrq95VwBZMWGV{Y z0#8*^3{bv2*|G7XqciK{M^m-#2z%bX*(O={}I(2@#8K$|p;XXJF3-2Lq*H`;~;(Ti%KX9_b;;%U1Ey5Uqp- zV%8Z39zvC)iQ%lK-|FXDmXM))0x{M}dbWTe=>r@}Xo|E?3LdDGWDM!2aQQKelOGTd zG`;IE0W1C){U8slFA%L)UH4<}N7}2Oa_rJK1Je=M?t{0hPL|!Vl#=Cf8n{ zq={1u$oW%ECG^VImUMDKJIKC#Cxi9CI9wIn7Rd?6K&NDb=##`}H}0L2*f(c~&SNsh zj%_gJVK<6r^zc$bb9_OZiY`FF4zt_}PwVWpF4p^M>0F?~{T^4#$r1DhjH;5f!AdYy z5w;NJEAP`NAzuSbV(Tzz1c?-acUh@^*$`YH)uCIM@1Hyv0F|Z=HYVtA(&6kcci^(8 zTpf}18%<+IxsGV`GUGoX-gJg}U9$C3Py}92-u^xsdGm>Mivp(KNu^4O6?X-~zJA6!-6~#sv z&M(f=)Q_(V-H#raRf_F%L(M4t-MsxnJ|TZ5gzF3=yZWXilUK+K8}eX5rx)U>M*9%=AkBxsP|ae-qZZZqE$a)tPNQcMTCb0AO&gTo zAvsO-xZbASM;1)el*`{z{j#DKpP`?Ozy}pZ!?uDux$e){MLWjiWoutzpaT={QpR6< z$So-v*duZC{VWr8ZijzvA9aL2jjtl!3{e&FECk%LZrTlPNBmgOhK8Y+=S)tsRLbYA z%#yp+9ege=IHe~?yF6}9_Y+S@_4LrNUK7OM2sFBX4275Tt2QbNWn9l0i)a^8$z|2W z*-Y;#G)(q%0eO|1=D$+&?%0u99`0@PX{H?j()J=GTs6)(I$!&3nubl|6fwnuLI^U( zm5WreJ3X3Xb?Rxd{PkSmoNbA6dN4&Sn|X!wq2*qz6YNtKbQj&a6IN4-RXTi|N!fr| zST-iP3nXH97Ix*@^gEI3M*Bc42_7}U=LPCoAhMI+VVMQ0l|YiP zV}L(wn#}xuS--q#1$4mlSszFA#HBe1;fplQLgiiCkB?(^+qc}#9Lk-Sb+~NaPr$JkjfVgq>&ZSuTIAV*at8?81iFKq; zBYrf8g&fF$x>$E<@~S&5Z0wh1PWDU1m;X?iS(Jm?IQ`9`%(W$x!IblL=~b+eiot8P ztq>w!Cdo6m=Q#EzjfU|QeD-kjXuOQq4hX~=10`U{Ii3h(s$r%-7EACL4DB^Bwt(P1 za5o--XRzIBPs&3#e4dL!H{IanA;$YT*iprpq6~@tIYeq83FKxkw4e#AkuH1n*%t89 zbPw4WUTVho^i^MGa7pr*sQ$yXbq{%l8>@3u#VjKtcOD}#ZFMKMt~UWRb;3l9K2V!z zHlkh7C|{Gx)|rlu`Q5vNeK0#YagySgFV`ksCcdmCAhxaO~dj_5uHKkzuk!iKReguVimb`xWL73Ed&$Q7-`uRZ=W^?y$ z7U--*({aISY=;Hu#L)eu-9`tsYtLyjXWVqkk}!4P1uJ`u&3#VBx|JY2g@k{09%bR^ zwa76l%%$#Xl?XQ=&5{5oM(<+XKEAqZe7FY&y@~VibZFoG7F?ga>A&^Rz{Ya>>Uv4% zV|KsiC|mzCORb#aBkpF>Z3fNX4>O|i&nJ~Cbfy)89Gk)oVv$@ zp#q2xSZ|kS^`nyqH`#BJuN~ZZuQQXH!M+l>pqF)B8B&R(dm#G>F_~dJN>>8_(`d^M zYE+4FH2U3F))zw*5XUnE)h>fdZg8b=RVOSzjN-Ci*>E!lC-xmO&Gr+6o%e7VGM?TS zD7MqDSYV(k~e}-WCzkQAXJm*%BFEvDQvxtan@PySfN4fCyEOTL|dxH z%5Fj8B6$B|chpT9{(Wpqg8)n!+i+I#p&tvR%CQV#tfPnhObH*K3omXEJ0@gk>vle{ z`_^X2*sUX%t<%bsDJiG|)iX`V;-A;OIpWhO5Fx!t?9Xc9u)jMgKYw!&@99oY#WL$cMhh%ixVO zEhqa(A)MM~m7?)XV@!L_zLErx@UZD8uN&7^swjkN@t*;Lf7F2I@yCW=4kQU;Vi-+| zdJ!E_YK9h?u)LG!plu)l7`?*tC!}{I9H0U9Z%((FWrOdHeZ!V|y_aqerE+f-qEIDY zX&yCC&OKsVhzpfsi(MuLcGC2ob*?&-4^y%EWLXO&ayoOsi%r`VA2f4?3!$9f0lcMf zqmv#4$jA{>h#8wJS=oykqLR9G?$xeFF*~=8;~_VP=b`I4Qcd{nZ7yfMDU7`goXW> zQR`1F@Yi#) z@#M?Fg9oV}_3Pf`*hU4pKNuWUFE`V?$gfIizj1C8j7E?|=N6s6XpRI~$`1gr-y34| zu<4$xh`l&n)Aaw9$O?|#XiZnFCqTj;TnNy~D!IEcrrx`I#R699Yqu@4vj8~&RG1Bc zd$%YYO-JWT=)UveiMuLmQoxb?h6W*apj$ zjpE6Bvlz)-i+Ne*L}3n<1>OfHtQWHv(XeIx-uLJcDww7TdNy1e0cL~YJKBqz!006m zqDLi;H13BmnyeF5MZxZ$+(@yPEUs=nqFjsD-&8F>M|L!Uto(9v5bgks&i>Z(ef4-% zZ-oX34V5ZQHhpt`OXDfBN=y8)ttd)GiP$N4%7cc_bPf|5`o=DXRzY zAn~mCE|l{{C)E{$%V^Z&l-^ifx;@7I{XrE94K|@aXlVt!a$b^?^iQk5KGCC}s4bO` zbdaMHnJBNVW{?teKJX?TV!v}*j~Y()&#m~_<7oMpt$E`JP84CS#(LM>`Lze7+!phI zM`afKzsW@+7Sz*Py_L(lyM<{7D_ey@#IAQk1~K?vsWowF2wOva4V@9g)z)e$* zi5gSFxczhY<~7t_+FgI7@emTVmBO@$5=dK}vtC>g6*KF81i-2>*D&TB*05%4WT4OE z(*Wy&F7XXeg3Th&;2`={2)>ATN-Eh5N{@Zdm(3sBo0>(Jx`SV*%QNMLV&5=6wstSdnT#;Ym^|n} zceKI%z1V@;IK}YYd|-uE4t&i;TnbhUdSGen4-(;udm2fH@GSt%Y(C_RjwC??vjYIi zvkCPg4xXVl_;{-o!gu-N<&8w5KP%UPcWx<6Jjq{F)CNelc*M`?1*?{T=N=hJnkQr=E9(7 zpG8x1z-zZEiwT9(uD&NV7E%#|$g6&W>BKzo+@u@#HY1q41D&n&)!q-J_daq{)tG6hI&P=sIvyd2UZQK4;k6;W1#?rmSq{*eY=b5ow?f? zE8OIQh&97&FP84Lpi2+sOn)I6XL!pBd+bj9Njm$cNqMQYtIw8f7XZL^SD~c^>XX~? zK)pP-{`i7eF!_x*iONY}GYntEgPSIrnI?z}^DtRg=%_lW{Kx*?W;U0`$%9eeTg7_v zgAR+(^;82zsrmODN2kjvxj_+u?0f0=yW3y@Q7(MnS^H~A(AUh@ggze5|P`zp;&bpH0!jS`15gO__~=3uXLt>0qm62>k5QdgN{$B-+AQ(VwIFN$Cl$xAV|5 zyiunC!=du3KZ5ZUjBnliyuzM7C)uOJBFv8Qi~0A=s)cLf8~jIAOuz3wCHeKm#2kIo zIrEQx$#1by<&p|eHTjRtROBrFt~oV}7uTdWJ`972bX4dgD%?5!yhtO`K?fg-RPq-Q zn(QJDJvrEp2UwivYC#T-6vA1Kc!^;h8p8XpsMRZ>JQWG4dr0CqRNPNRZp?!#j%E98 zIw-MgWdD5D^M}{Z)<%BG;4A`R=k-~#;~CiN6FL_1gU_QcK9h^u$AMjySXE*V7KjhS z|7nEM*hTlJ$>6Y(ydYt}XIi2+EruBN14XK*zc<5-dT|m2(o+F0l(YFVi5t_9P>lU- z{8QaH^WHW4o_Ltf;Jaix**v8c8P9HeacGcifq;>1UJ^yJtys#aedj`mb}!wmOGz%u1^FCRF#pmoy6Y)oisy z%%<;cdO3ru{R)?29ucOnOPS%T3h=S@ibnkChmYESm}_CQklg+lc|_$w%PDGJ&1BLJ)c^%kv z(q)_ha;R^jIRiPdBXY-1wSxppK9J7nz* zoEqq+x7fH0(nnMmoLIfOKd=M(sh zwo=Ke0rCQKtFq?$zt2h_p7||Qfqi#!&PL1zAT>6qNydACG}ZwzZ$+0vdgc*Qw|M6G zzoSdhnh)yMN)&b*4}xPt+_i<=u%c@(J_fJmM7AXekq6WMZY#8JNy91NqMXZ2sI?kA zAbWC)`F{W{K+?a@YJGwR%#v3^bs*;)WGfU3;g3s)%sjuvs@OTSjR-NcYiSK{pFVry z2;Vy(;#C1eS}j%xT04z|OkT;2w*GqhOWGLoSi{UZ_B`_uxqZ|*RI8DOd%AWl6B$~Y zP#7+Vpy4=ruS%cgw(iGi;wLE)M)1zpC%T-MQ#vGS&w~18*{0th=D%wQMIu!{MnC!# zQll$XBN(z}c4re|n{65DupHkUZlz&{_elWAF>0oE6LO5h9Kk;fQw{@=Lx`|vbM6(D z2uX&oMX(H~*(io-R%}>M=nUNy*Gw*h%Tz!PwDXfv9#8b*6YpBE!phFcO$-jALo_WB zi7+f(U!XS$ll3RM{x@JaMP2Ublt5`KBTk^6 zWC5Nb;xNS)6{4x4ITE7PVG{*L|3XIpBMGUQPL2c>rM_zE>*mD;!|?XYyML?ZOw`TG z^ftQ~qJjeSRcKV21__Y^4KFDvgg92{+>7u3M)xp&*b3DuIe;9|0rHS26i=Ur6E@)x zq%_?>Ob)I|@VzFOz-u)g#C=#cvJm#s7aCRa7Mzaila*kIx7&dQFgJ1F%xNgLFhKS} z((`p%uZLJTK0hNYORFtN z)B`RBvbs>D@pj$q#2hfa%{&GM{%C}p-CbOgaC&-DCTV?1bZ{}5=EV&;HN8eoSZ(8M z)*`EZ|3lYEDyuz>$TXTCa5M|V0saG9H=5gYWFnoGDoBg|W1@I#;#H{@huh*SS38sl zB)N})5-iDYBsGE+EYbXc@YE)I)=PgxdXzu_0r}ssa04m+6DmCTV*5LJ?h9ne#9#IT z(zi3>maXpLFN*K<&JT-!Jr@W7?qO zRGv?tq2Gs z2j_y`KX2n;)IBX)sa3MgrhK0&fuo9#SA_S!MK1WC-Us!80-V_sgb9&m z{=&;3iHi5hS?lxxYH>~L&Y*sf^o-dDW>tN`utOhRrZ?X6QqaR_jK}0Ooy@FE#GK$r z?lk09N8oGwl=QK35D4@p_Q_dgb-d(cfT@KMFGTb+#sb-xCl#hIZ;4X2#yViZ334Gu z6>`~s*Ae(``t2oP`QQr@JgGDn1nddlQB<0j%f52chVrNQj_Tf9ZbfezlCOOL*Q}~* zaNF|?qT&t0LwmyPmT;qCmSd>4*yoJ!XU^$(?MJ@s|Hv^u%5Ps;-X-lIdZX@<<7#ZF1Qcb1|(i_o!Yn3KUc(Y+)2DN*)43#5ge#!;(dC146wifq*<{q=y3 zVTd}lrnxR@G&8ZN*d!o^=DlY%kgX318$u>6rf^)s!tHUcNjnR{qL7#tv*LNS zy=n@sM(q0a?ggf?2aW^ZMsr4Nf#f7PIfXLe4g7T+6t;r_3`mm@xxQ?%QS7$RlAMgc z(8-k~>-09h2q@-VYJ%?zCZCWs5=o;rTZ!`|eEK_3ZnORTO*JDNLWX#-+$fZdVI|xQqpshI|MkJjwhrk405pmnvz^qjtJ&^~-h^WW z*9#SR$5mjxC6_Y?Cx`6yKwx53V-b6D0=BE^a2__k;=z?$Pr1(V_2?jSS*yQoPN3Pz$08p8n6~_nc{;sg@pC%%mt6QU6LEgR*a_n8oPs*Ve|MrU`YDz)O z+tj7q0GKcPyQ@M&z7Rl3wi}rf(rB?EsY)lVjW9{?z%`t!FzM{O4hctMb+)ZRStrqT znDfMc3;b1p9{U#)eYc!pyp>_Ac8%ozLAJ2JNWOa$%7 z0`a|?=x_t}0GNyAwFnk>-43T4$4R7IN#g)m6f#C-S4XoiO;60E1F3VK&Yc!h<&%|0 z*IJ-{UU#U!X`)eG{)I68=xt64)|kZ8v$WJLioQ0p&UM=`)8?>cajS_CSqvXGTN1)w0l#S$7} z>_A_u7L2n0wc9ZXFzOrfvJs%1NiHi9b!o*E2*M;x6A69IL=A2bXpke3`g; zRy5PMP%OQNbGl3A(^)p^m|E~xH#~;vcNgT^_PRO=M!m1q~a^w zUGlXk2mAT-yRQwf`riEMp0(ODv{CX9gX*Z^eqAbtQXm%gXc@Sl+8vXPp8w8S!GHzSx85sP{?lil%7(t&s;Lk!7vG@GG@q1 z4oGCRflv|~`Mneq1YT(6qq7mh28@zml5hXDXHvR%u|G(}iK5zkV9!l+Tir8P*_*lQ zse%k`wD9beb({qM9@a?I&5@lJkTFeYlyZQ6Th zSQ`$rE7V-qBG0zOLN%D4KIJPlt$H&EG-io67a5j7Hm-qVt8Q%${%U_Rv-#&VsUM!B z`tNUcKw96KOq^YvZ0aG>@QTq$UIpKLD4BBN(z zxhr|fZU3rq^CcW7^A%WYNCK-#SH%0ZcS55+Ruc@*Zb9r_>1?F2fw`mt&Zq1%}-)QUXjZyEUx3Hi^ryP0v2-tS>N!b z3l#RUl11X_coZ6Ojuv)syQno56Ccs~lMk&s&)JMH-*} zeJ`y9eOpIs!Sc1J!r~+$=|vyAV4;0Vst0?b&%Z<~!uf;Sd@fZSJNb*Etb4H-v>u+( z*qq5PR|o8F-pjcU3&&?V1s$;t2q%sCFwMkd0~}S$=I+^>6DE^prQMx+kSQ!P+xgm; zq_n+A9_ml?67b_M>v1eM%G2R&=Eal0rnbt!qc@uT0@YfsLa@8hXzoxLJCsYz=MiQUmh1B-iScB z{}nS1spO2=c0B+SJOWf;ds_>(%^EDVsG)TgD4V+lp2PQjR9LO9WD@iryv5piT_|gj zc>D^8h5BLbFXq2IK>vKamM&3AHdE3UL5em(+%MC453F(Zs?8k&&sYgfaPx&3jmhBA z0cYHJY#4z_BU%mM6xJbF`i?;=e$6;7J}y=#BTAx-=Jp)Bg-x5^NEkC3{?SUu$I4Lc zv53PBxbj>E1J1CLW?-nW|4K9)M=$A`R$QcYy^bjIRUS=&5H<~9Xc)^YjR+lpv-E^R zRQApDiUJC;b01UV>mrpDL6q=F!F&uNZ(RGXz~I?zy}oxkdYxAGXpVd|J|G)l?Kyw% zaf^gg4MsVUheXh@*U-*ivtMkuW|us$E)MB@LE`ZSW#A}dnWbiyqhocZ_wP!H|rwp)RYY^STKwzR_a0T z*nG01T?08l{V=ka)QDdhj*v58)#LIKSaYrtM|>O87#_HSjgmmZcI?5n}hz zJ@3#}(UOJTi9m?>r-&2~qW|g7-7_EE^izK7?MqU%UVB1O^j#?jC63B2avSG!lfWut z-Dj#Goj4KDS)OCo2Jgm;th) zE`YOf^?ezcun0B}oDr1MXeVlsNS$g&Y`WpUa>yV||KDJ`)QZI4 z;y5Tm!${g)5fhR3IZ7^a9pR^G>EN&q%kkNn9%=tX%cFyHYR+tOR-l32%-BV5UTtmv z8Z`#9rF{r8cYQx~9C{uR?`ThPKUaC!PgM4V)x52cd9E}i+&`}?V)K%Au0`+iE%=$jq4S|J+Bl-+W#es3*Pj6u3W-L0SZ-|4Mc{(U>x}irlq5I{EC{$6B=%%ce@W4@)4jV;bvzMVQL6AH8Y8 zJr&EpD%bK?42QQ6Es@6KqbmxO8d8l)rNRuvqX zwNnLdPMjfrC=L1PoZ9misaAGZCtZiyF7LS~Zv?N`sXga^=c^cvbB_#}XL1{LMS$hCg&vEJB=3 znaXGK#}4s5n(Ey79yh=*+o;Q8&>-j41XC3BFcx&xxiv!GE5tdzVgAC zZOR4ubNaY@=Hhv1Zspuohvl*UStS(0!T5Ej14y@m?|5!)h_(L+ioliGL^UEl=2%qY9%Fk*4zy83LFp)i z3Ao)r@W_s1;M_Gd!OM0hoZo@K13LHVy-RmL76zxW&1l74feN)4g*I`Z zVxA9;%Wz6bapQ00tDZTLNFr>%5>hE5Q9w|MlfQ9eA0Vg-)hZH>R@MS(Mpe&GQOH!& zA#(d1(r}wzU`7wJb3!gN8=^8)_E?hL4Ol?Ou0dB&eH7M*QK~r!p>p`5?dbX&b`N@Q zg358rf+!KGAUOXb>W_5qqK6PZ8thU9`OiUp z_td3^2cyJ_O=SPbVeCQ1e42p|bsnB#Q(wF4T0)hCJCYaS@kvW0iHGV~G0?D2&;P55 z(HRAtKjNee?Pck-O*87FrR(`83pikmx!lOH_v7mj#MW*aPRER%Ion5M(`2*Q0C<*j zQTeyj7Iy_MM4&pOB4R%8NK*$$wcCpjWrp#y+N>e-y?0T!AWNUehh~x!z2P+kGBAF zp-6f3gDST3MB!zVaq8FIi~L$j6J9S`t;U_n`CHK(dqxZvF%+_{^Yv|&7i%!{PKJh6 z@$wZ&fZ}6)bTO`NE46Q*?pfM%)VbE!dxqdDj0A~;UELppp*Ecqi=`cI(aM79W4$!` z1K6h&fHl4Vo5!G?5jtrEvkJba9vuG*!5#4mQjUohn$}ijTHIn=3%$V@D>DQofUDb3 z@&nvh5vMf=Mghi9)-UrB+~Px?+iQ)M1Lo z;#_c1uQAtC-C8>Tq~zKhxE3BaFN?^w+Aw?*sX^5Cw0~?`ban)TWzawzcw1!@JKR!nMM`2L_y1tv^+Ui1@x`rK z5`&mdT9Frl`F>-c*dAVUv;4=rwoODC903-m@_kGggTapk?YV z@{2760r*(C0^(ZkJSPH@CR1U1XAfh5NVw2qt>gKGcQvv1^k2ouoi-)f+jxJmCUxEK zEZ6iuG~mzb`S6?V<)iy|ObyCPW6k61_sygW`b2lbbiA}+!;<4z4e`-V3ajgEcJXf! z$Pm(V+Hy6)`AWh3K7nlh;rv%HMVczLU%wZgyz`PkY`D1WLHC2DR$ZJoOw)?Yjpevo z38c^Uvz*Xcw9{kq27p#7GULUYju;02%qjb+zW8%z>O*51i$V+kyJ*gZ<924!U~bm% z63X-**PE<^biOh6L7aOsdIBFac_xbbK8rkgDc7O_NY0N;yeBuu1l}Xnly<5#2c14_ z|HU{BSbNRB&~u5SkGIhu?c~!~Yusw%75xg@Qk>`oViP41@a|wEnZQbd#?pd@O;(s( zT!ykwC8gb`6uf%llFG{|?#IsvNhw}(t9Mb4`A#ry+wl8@dy=AyDaAAgb>oCvE*BC^ zKr)BMBOE+?2uoWxui`SCGvf9QO&IOHM`_c08X^qYXXz=#0yh!z1@f{n$%cCC+NI2G0U)o&H7xpGs zVCXr`8>+PN7-&Ml()u4qAwe7IL0BSea<;KZJS=z zkc*}wCQdhYSXC*w{;$btU%)#VcgpB`E@7_E)GAfAQuv%AhtKatkt$U)!I~tIn%f7} zqdV+`8@MC_?oUN}|8A%?ByKs^qR`Na!?pd!esh?d{o)p%@sZVnR=j{5MgU}^o%XH) zuoJD#d(vb#>Sp7_yBq!NP?026xT9x>P%CyBUt04IS^|T&a3hlS zxB{GZB3ggt}Ah!pvs;uV&?)4Xnbtc zJ^~#%0hJP?zmg3n3ui}dkvSN&ygkHpWC)YllTiK;XmWL4F{8Cf*Sr&RbXa7bS$7%d zZm-X(zfkmiL&BR-i$_gpxq1MkRxc_ zzJSMLl&7(EnQsH#tJER@LvNipmk3)7n{501iRN)Nqb+kwuBss;H@DdMdZz`u`;Qg5 z3OdK4rQY$>KMDD2THLN`?NZU%uPF4pZwnm84R};*eTy&&a7@f-hRT`o63&fb;_L8@ zW0`xies;a+3({A5D_6oF;B(1zy=FNmSEFU?$QDifjmn#q{Y9!0@8wc;r@{!{q6i+D z!xnN99Q@CACX{)?iwHFkA(r9zP{OfD0cBA{@7RDfm0%#E-^h*I=OV6jbjJR+9vS4R z>RNH%0;WSQiZE{nFn?f51d*Y#0jUQ{D$J_>A=q%X({idGqK>5O>KKl1D_W&=XWq z#F{AP0FmHgo8$7-ok8`s`{G!5 ziWGmldE2K3m?;D+LH?5oVhWPoIu%t%6wr^lEz>T1XW0nV_UI zT^EsG9!Fy5nqZT8QNd52YnTmZ0|ccg54Q^>cPaxyp08Tn5O=ZJFe1OQ!$~CYwB3(9 zRH2&4|G8MC#!OtJY|MZG&^_1G5gOklyu<$;VZmP}y7(_rpdwqPynWAgNVmwOtI0ix z=dxv`G4X)RnXUM9HdOvn&tFuI(6js2jhhzh^749w-Kjl=F=}Ojzz1c({y}qB{*bFL z=0(!GVhyko9o|u01Lt{KD;R;ccURPngsDVUztb3H)cMJ7j>2dGb9^b1dRs z2=PQfE!J;-BUks*eQRx;r6R$L5qakT*7g?AzpVO7de;`=&gw!q?)eyZiSmd=N*4&2 zRr*-G>^|YUqW7*|!IGeLBR zXRzyd@y|kO9&0T(U?*WPK#chaq6l8FpVObbH=8m#)%pz+tnm;i*Tg~)fd06fxt3Ke zivWF5^os7AM+5;JO_>6q00&QiZWWn-2$Rn#rg~G&M3TicRowUy?w20Vfh}p^$r)x2 z Q>{;hRws<0eJPQ9K7Fj(dGV8Ql*`23}vYwh_Q+6EG~>x^Ec>SrIX(o1kf%qn!P z1*dlOD=(2KZOO8631aeCXihlIxdKQubLg*3ZFR_vHm@p z#*d*&F=>}B8eFdyo=T4NBM=UaR!za?hY0>rKl9pnKXQRyj-gPPW)&9#O1`g>MxP$jwWcWjoO02LKs zs_BC|(OZ@GmmIJd-&-61Gd|mTx|;L&t=~C~%n5KelML8*t3`3o)zHMqM8tV}&ct&J1kUv0=y>0ClRb>ROSe^`c=<8h8UbUbF>fLR`N3e$+%`9tl1W1uCY*mC&Jq z!rkJz$Q7&1@CZW=C=S3=tqk*eYMqj$!}H&U9io|vS(7~LAY|}J^u($myZ$wR!=^q zcwJo67V|XzTY)e}zm|@|s?+6&DDbbd&r^0YJ6{t!2*oq{S(x9SL5ssyn?{26w+5ZX zYLzSXr=2>oBsz(w_s^l%c1eogt|3S)R0>e%05=v#;dnszRo(TZD7#PW&B)$b3}YJ+ z()e#%(cJv5Cq~Q6p&DL=HKd7q%4*wvHHLbLU%wDrQdGdN`nAbyIbafVc zC=0VDF_V{A=<>M@t`HV-#z)vbVGgWkBCXXf)Ad#=Y{ro6y(uF7K#qpAkxP~Z54A5X zG!d`5Sx&d!dN$Rm{!A{&z^#zjMXDX_p<_`Pyidp3^TF7Em zy17J8JRc6;sg9wNGs_FELk!L>07pZ7lB!(eT@sgl@YQmy-J&M&bOAj^iA~>tt}rW; z6r+ZCu|8awXKncclE1&jX&Mj+B0tT3Ml~*f1;S-q4v9s9DOqQXyQV!Tds{d5=Nhj( zLm)rBtP}@H6e(CumTd6pO8UpWL>wo&-4x4X@K1$(@>4eZ*UM2d4*d>*F z6oGkybx|#Tx%z1+ZxLdc(XQ&`uWwoU{ZYu{3K0RVkqF|DKsC46dU>24K#A7XNPz$)fAyAf=lthg9(7Nlg_8= zBeL;z8UEr~xF)$Wjh)gMr1EzMI#L^T;39Vqz05!v{h<^4q9!9g1PCH12kFe&L% zO3_K+?U`M8kC@oOJW6VZJPO44>*YE~dz_75%`(%~jfgo}*!_Pk2CC}sAFDPVutI4C zGZwi{s4&=yRkD0twhT+IFFOYWVbXw=%d|~)q$FAJ<*qqU|+wjjFR{!0kfik;Ai9hd6cyozdg2?gV=X_y0ds_ss%)T1= zgQ&vfM)G~tXQ_l2J*7?-0DOHR)TNO5Wa_u}H3EzEnu73^99@2bbjl!fb%_zll{mMA zq`&s($dg4@r22JHDW)WU;Z2$CEj%k`nytC~jt@}gUx#7f57K;ha0^}9YjYp|($D7| zblQ8C^1;EC`(;ta`ufxy&JdY+^5_e^qkXGw-ah6Q8I_y)tL3}8po-8tT`9 zif8Z+O>zhF0};^lI*-Ahn}Lv#=L6%v~;{uY;M7SxK~=NoP<| z5-Zl&_@$Vz93UpdR{l(kzc-=S!|@=i4#~e7Iy~I zD}On)F(P+bCkM`NjLPeRTl=1vtRt+0o6`UaHsOaeQPR6m>Y!!c{_S-Xt&*%O)m|bH z3Bl`*F-D$K@7QC4U~~#nZn+!VrypWX+>&9p% z5k|2C5378-ckPJP8;aD?O{fMRp^5?1?i-`^b_G zt7TC5y7CjoJGo`$VH2{-4@{$%FL(WPp%D6J1(n^2Tz`f?y& z#V?W_?DRKDP^<^755v?Cem^l7I!P|>>2M?h*-iVtP$6ydm{#ELjq)E>P$1y#PZxOrN|khiYJAjv&~$&0hCAJ_U4BZ6 z(UK_D3OfEAfW92Hl47)Rmnfc-XwsR^UES-0xe7?9HLjO} zeL>(FU&109Ldjz@pMkKM+i&{(&p9N*%$BO{V?`RrDXp z0;9zJEaZ~9Ww#X@fdF*jObT?n=D!bppq8KyNN|lqE3fYtCkI{-hBkN?zA8UNt?vKeNp$z~W61CP$#@!8-3Br2El?i8+cE zq(Y=CQ-sSgoP~KHC#OVJaK)RABI&hYqF!9`99@DZAsUCc-&iHQa`|k;V@k=`3JkGX z2is?m(M*hYOgY#7Oc$oqKKlHwCy-=Hx!!1Ur=mu?m0L9rcbRDY22H<1gzPO5xsZG! z-zRof???qc2!ty}0mW|hBG$0iUs&BwcpAbWlkUK)S-wT%-e*os$T}Wslf!4WTN)}TC{FBFQIagi(O<>@vHLq4$u5UJ zsMVl;{I%yCpWZJKEMbgD5dVC~_+D$_c>6eNlss9;2z~4&|)vSn0tmHW#J$t8EKzr)vJA&=St4j^|qvg($ ziK5coN@N>#Gy}2G6zshD=WfI0klR_10D^eAFIG`Q>stY_7%aJ+^H9pSao3L)R>yBL zb8qLxFh2l-{*gPwOmMRq!s@?aC|&E*O|TTJsa!5!H-)RYEy=i!ZTR?)W6gAWk`UG1 z6Rq6&aTs+>R9y2R1ws~5M86shpyJC}tqZS_PLq)QK`~EhjOQ2l#O12vp{;7N8C+Ml zg60hCdzmR_MfPs={i%l-)z8G1ww{{DiZUr^jP!rwxlN0f*e;7Q0LWj*oU@RdNSLdu zq4+}5o)Jcz@ZlOec{}vlnIsv z&`lN)u~6jv7g{>?f(&`qaA@Rmhdz64K0bMr6QWCgm-OwR37jM~&@d~~VB&F-jjvJ- zt`E!7tmn60>9%TBa`SqZLxQ;n0>Dmqikv`h_0N=uQx7Bu)a1z5z=-)N4sZN~SVLDw z&}$O=(nYP)ABj`3 zCJ~zhmmQ3+`M)6Csfi1!%AI#m+_@}fKKSjb^?gqmRot^v6G zG0eKp{>?uext!@x5eG<6$wR7kkta$f`c;Y89DiU$DR8R9^-N`8#PMB8u-Htz+Jy1j4ZA5| zu37xB0NuSmPEtN~U;SAAGI*#C!LdfO0nqIpaJT{D)S81{h;=a_Drh7>_THnaL7)UQ zK(~1_vKbM<7p0f`(mFi#H4(eZJqgIcc##C6sfn?J!I*!0zlH4Jg2Tf^bNwjSeQRc_ zw1CsTS4h31S|V)>=O$z^W(;#3fpTkY$WO}gV7nB#_eiKs0o4S!WfgW{C0r4|Kx|R! zq+CfyRddCrGuSGcgV*OtAED8dPvBSWp&I)946?PEn#rpCX?l!g zQf8gCRLdNAMxeNZ4k8Te%3TK2lbRTvmS9agq}!cjRVshW0jam*MCB>8PC=lq!3<^n zPM~*(Seud}gubtdPxqUc{7VmF`0rs4AKC~JWUeOmly&6Dwf@$0BbT{(A;eTasxP@Jj9 z^&g!{gx5+*ieEf0IYHg{;@W!w^5E7)OA)-I{i`cwJG~n(1fCLEE9#-li>lUZcOm;ud8P zYaO%!OVWxAiQu{Owtv@R5)Vmp{_#)jp4litGNIJB!@6|>+9iq#cn0!Oj7fybi1#e%31*S)=kO?FgJ;ag%vW<2K=UIsGr0uRkWFsraS;xQ$nv- z&F9XEmeKaXiLjCOJD6%`XJ=oBe>GT^tfGg|zfaOgE{f-D|k*y^Wdo7CEWI9dD*EWTZa+C2QuRF(AJyb=Z8sSs2eOaf_H zy;)jW76%D9Yef@nFf;TGzlM)n=P0&ZEKJ+oxUsrk)-Tk{*boO5PBgXL$LnGvNKXVi zwgs(Qv&p7d{`NR~>2$PA>ZrDSJd13Phvk8mtv{)rs;^Xd@}^-VMsbus*g$hhO`qFX zy%Dv`;Z{~l3VGR>M6%&QXyw3~o>cYK@7Hri(Onj_;T>Db zh<)g=P?;_WjQ{1ODd|kKVVRW99Ja6g2=_V9@4N;O+^npKl#(DvgRmV`uYh2SMnc?4 zQcduf?TsLqhtrjjDvFNHk_sljG0PRq1=dGYw3Jp~w9P>-X=%Ni!%A@W1}0Qb#rajS zMx?^!38EqCkpOp+F9Ywa&ZHE3BX(>#NMHW(uLlF$9w8ak!KhK|RS9~%7=DAOVk(%J zxY-(eM%_~}%R|aQngAmXJn%dd6D>FpZ^+ir!7-(tpY;5(GsdOrW|JFr?aE`Ii2X`d z<}Ph?wd4j$gLYr4)V^Uuc#IOd{sp3X)wY`t?CIeN-$w!Ge5FB@HRboDESggbANHG7 z@qe4=ct8|U~*8-BG-dy*%bu?cl^0RH;4kN{%|`8iBbETBRJ2WRhV9u))K zY4l5NPJ@|6{>RwVPH~8ag_(ai%K)%tk}p-pI_+(U)HIL1NwzmKt`3oZY}wdeh$y(4 z_7+e-IO_kM#U}|}r=r07jAWR3ou~y+^?{-#AJ#^|kI{n6sPJixn zzEAMi5uRbZ-7Z%u`-H6ya2Ti=-~kx}DbazP$8`;T6x4$FB^p*t7r)i+eLWGGD%rRV z|7bYy)(fC43{rvhcofopIFI^8r zgF3aV9^+%y0CY#8fqh74% z=GC(&0C8Fu!gOgiv!d^J7&UV8v(`WH ztO5Ag|M%9$L)OyBG+g}56CsfLk0^(ihebfHR^m)TW{wm`pm#54o#R>4n7}h05sj#Qf!JnPMKRnd?gj#V~wqqTu_!?+f5^dEOoo4;^5z6qraotI3~8p+dze^M_071r-_d(C|sE=2MwV@_z=v> z45vSMa^3y2B?dHH!sE{WW>XZ(E#9zC&;2B+=XDHmVOKAGo>pi&^bL%tp1j!9s6d>y zD(bWlT4Nmz{G;HoGNxitcYNMR!a+`?Uum?^`fUDetixFadzWF4X4WM;w$4|Yf~#bS z`m9dNV;_L=zet&3bKJPHYDFQx|@N6^m{1F9qz_p9bTZ3Eg^=9$rD+`1|VzYZLW@+(F)fC@BJkd^LX6&@Z~ zNsN&M6yikdI3NJ}WXW>9i0=fg!T%T~vPGy|e`5^nTynu$<0h(Od~QysK+^^s`Ml}Y z_b~=uqGxTu2)At)Uz_7_87PTbp3+lf#B*`qzB=ao<`;c|ja15&PuAGOl$@X7Bi+eZ69 z(^uKMK@0}w7xxiGC8~L9EAz{|oI97Ue{=pp$-B137o$2`4pcqr~dM43{5`7^Unace4 zHndmZXTeU$#FwKR8d4Po7HhO&N5TVO&c-Of00Fd^gRf5-7I%KLZ9GhKOj-}}8fWd^ zHAs4TcF!^ja`R!<{YD?UOfq*hnZfMITg$ls(1_h7+yB?^Euu>XiI$U|7TS<*KZ>W4 zrawA%(iq*b!s7-}ZZMrlEsF3E0%NrmD;Y5%lQQs$xhmz`4AMH^p1G!6vc4QPXljTy zhr5hORL*`o6;SKNY&$x;EC->4MdoHqoAz!@fmA25HC-!U?`n;GA+rLiOY|(NqZRR# z1-IM^fC3R!&5P{}BgU91b#&1*s*8qkzhp%`ZY!aIkKgGcHay!NhZs2148V~P>pBcB zwe+JU$X%=5M|Oc2l51Ivc>s&B$`v25skEL!6J>MBIHi<&q+gz&|0W$15{=W)`8iFS zj*64GmY{)l990Qtd>(KCz*>+MNUFB%5~%}uYaF7W`}TG^mccAs*I+Pq`*-p$kR+y}Gb#cBSt9MR)!s9H_159*R8m#(ZffYboXhr&VxiA~|saT#T26@sOv z{%O4Qo&$|Pw9{x!Kmt@u;bj1J6@{Ir4IeN#wkfA<#E(xB)ktSbqf#pz+_x=?@>FQ4 zOEolHy#CbB4oOV2USzOgILSRy3^~e~ zRzu>j`2iT{MCsEwHF{$J)x5A0a}*`NX%5a*kwLgYI;>Wnp~2QRn9sqqC22F`4O`#2 z;vC9_*2MHTY6YM#?)c|vI*8<)e(l4e;Tcg}{`p>sb0%aM+sN|I-Kscn*89BEh zM9(_~m>#zpoooN(y5o0^zbs@H0V!EWsZ(-3wj@Q6(sI#~vka3aZ)xKjz8URfYAyqkUe@-(tU<)zDORBZlvp0f8aW{1(WE6b*!*jh#hyOQ5kprd48vSc&op6&J`RAVTlvanp&`2zB zU5rpH&@X|SXp$DaSDN#5`JsQON<6%4lx3JMJ6CLcrTyWw(?;+EVj`k!ZOwc6~{Y#vY#HMf)LD5eF zDRiqX2&0U3U!!t;_fepaD!tqb@Z4WtFTjpiaP`HlN*G4+f4Wsj#r6+YyhT9igm{y; zbT#EvFLi+2?N5_JNEUU#fUd)J2ndbX)uGo3xz{$t97ZHCC2+uwUDm(rIn{Rj)j~Zn zjN@TTYaaB$gxuR+qE@N0u^GYjdncVK?}w1mm<;yHWmIID z+aNPzZbp`GF&<~Y*>=RccB$csK0D6&@~=iKiS`T<iNtx0%FUNxj**)fVgUha2;l%H^*y0t4eTIm^~OEUtRM7PezBu*5|aR(xwG2AsHKRHp?+xXa6_!_X2BPNt= zlj~wHYpn^iKE+V;=Egd(qn~VY4EE}~i9Jqdvzx(Rgq2LtC|aI#)Nn%0W}f)mpRPBZ zR4PMTqDK)9Mch?+V+H9Ky_v&yEuc z000mUXFXOm@9GHuZ8`(HDoAnxyl_85%Y7x^9qjXQ0prP*hlYXZ2ZIWTi|irvD%vm* z(`i~F^l(XXNL=g%DqiZ(7?@(|Z=Va5T4IX#15+y7ap01(|J_=^QtEbPwqM8gKO*HRQ~L zH01fV%6wL^;(wC6Tl{V{&g}I;qc~TJkFm1WA@1vxtj-9{QOEKxG(ZqgK!j84`~ZM} zFnNOB&CFMo51mA17hvsvGMMHxVM(T(_`sF2)E)j8kt9Q|{RxOf8~#8D=jc%hL8Tt% zDH~p-!#2d>(w(4|xnZ!xA=yqHEFFelpRz{p{S29_UubU^jwdcMYwBo^?7J9b5yR*% zSWI+EuV$H(XB2P$*m>%H(u9&Ni1hr3mxxcW@Q>v_G()n07`O9vgjoA zKBGQi48<^Z12BJ``~5ixv-a+l2VXX^Mu$@ptu;dod-_7sIz=3`5J*a!Ku*Gs92mnR zA#-jSpshS?Fjt7|82_+av|n0$GBJr&xwC!nayT1UzjBUW6S!s(za8jzvhpf8p8N~u z+p)Tz2OjXvQzoRCO~EXtN50(+)Sno`i`uZ5_~-TjrEq3ToMCNnZ{wfGP6UId78u@+ z`4^d#0LfR0RlMfqM3AWSJfegyji0?k^{U6}e#uCas)bUd^923lb$u6q>*Z*=_btp6 z6tntdcToyJ0bU>`-M=%~$KWy{!3I3s>4Uu&zF6QH=I3JXC4An&e!`b!at}YGK0L0_OHqsWS=1UOfol87Aqp zhQ}I{T}4N*Gpi|}PqSONyO;nuf4;KQkn+Z7EXW?`+sXNmu&@`Dt-d~%R1{mWoUVs< zewc{Q6=VuHTB;8c^rJ|wg}rtrXMQ~RZRPQ4(!sn)s=+{Arpl{^HQz?h5Wq2aVUfXF zc$_|I7^sb*R_Y|gtb=oYeS!r3yA}u;3*6O8r%=B7Wt82 zY|qV=H1cL!wbvU_hcj&^EmR_VZ~~ks+%NOM4KZ!z#s8}LQLa%Z^!?U=mC(X3T z)BQ+nyuOe|e9}WP^T_TU8)laUme?)vC#LGTVmi@z*WTTEl$`)xmrtz| zIoA`eq^?Jg^9ko?m0T_Gesx_CHx$?QipWQJfIwCOjC1wFTDk1iR)bxcaLC5NQ?uJ$ zhC~<&*vQi=}oWm#Aqm0uy}ge&CnuCeQHDs zg6P7`IekDk25I}bwO<3*-xk_>Z?;mcoy-Rb3d}@E>63@35=av%FloM?n~wbhf1HDc zdkiy4B3C7MYKHlCwnE3{f$ha~J*TBr7H-VXWyHv*4$xRqj-xSCVpw*%7f1@|H|5R^ z>cT-dSF4Eg{MrXM87{t@u(C;u4v4%6h>?lX zHdp~D^zD(5i>o^uDS{2*QtZL#X(RbDqTc-F$ z!>_M6edmIJH~}lZWLGjxa?GHSTN^4;4Y|;FhQkH;K#l*GY7lW14zdA%@mMeC@u zPBlNdUdxU-rjw0O#u4N>99?a^ukgvN*yxE6eHeN)u>{kDW1kj3U%q^Poy37HWM1#! ze?w3VV3mE$z&`n$YQXuE_JFrjBNerGwbL1D@peWuQ4Y%0aCQV_PPi<6fV3g=P9~zy z`E7Yg^Ga8$U$nzF-iw$cACI``r{V*hg?2?d?O4o{V1wywcSnCMNMri;DR#0N+sajP zfhy8_avIUzL5p9KDpuwRSg(m(+7gU7#ee``aE?YZtc~)E88b(gz(W0Q&glTlZ;8qY z9P?%CsAHsa(!~It%(wiFsDGR>^iPb&K=VH4h^QL0dkz_u2yZ3>m(~c%BbezsfGY8Z zZX@`CEG!@`kskHFXEH^N! zQU-3pqw6g%cF4k#IGACIG^fhfPA5-)0cb66R1G$5!Tygt2tS4r`L1e zD(m+fhg?~Rlp&H#q&^2mrg6AKM3ECSDT+w5@qnB7r^b0?T2EFK_NS=SpC`g8lPV~H z7|0I;9LR_v?z60yvaP7BE5$bpstak5${v%CLd{?~R#Zl&0kq=XcZ*dXgJ)@?<)r`H z=cny!kC%TST;#zc6mPwcBN$gO>($quI=Z{@7R8|b7p@LqG7{7xzZ_{Lzm&7g(f~9K zh7Ezv+>{$zd3;)Zf1ivuS0~_pW81RMlkW34EwJZqQLjkNe{4G2Q2wc3?0*tYpM)V{ z2qDpgOO8KmW8BYSt!5}A!Mib^TG?RLkY{7&ISi!=sGPQ?Q<)sDdj zEv9F+5T2$A#|0{?t0g3QgN`44mRR`qrEaOfnH5U|2QtCT0bwiE?KK-}k*)HOlSQ5n zBJV83{-8{MgLlEAG?UO3L%$;Wk;E|*RPyxE#LC>9w&d3nHz0UZ^%?@Stz_j@gp^c) zlD4N%VlF-zl`JFiK)ZU*u>6CAxmxibiqEmtMY)DTY^;&V#NHULqzdXv2AWzh#^IUY za`mE_g)}4KX!}7KAVK(`KbX$9g<~C19&nNzv0J+I^MI|CvE|=>kd@us>hQIBCoN3d+0q)|I^au~Psn;hsRQ#)LCUUl z5+7(0faikJsXpk2AquVY47wt32^ZiU^g9b50Yp2S77}bOdD1L0rS5i9v^7~E!{^T1 zl)KHx>m?zdL;%HxuQirpyR248y*`A(1#q+j7N7o!Z|YU#RBz>B4R3!r(e9qk^jApa zZO>QmeJj+~xQTe=Sm*KUvUeNBD{7uJ{6mw1gqb73Ohr~Nx-GKa9_5u z-70nE6>g>JI%Ti9e)|YGHn+uh2T(P1`lc6C8w(^v@ulUZNbRf5-5rul@OwbhAgSoYyrh;j2MmU&EW6Y$grEof$>(0P19QwDHeQPA4fDT!|-PY?ce9PZYYUn%K~$@BqZqo0n-N) zqS^O_dI;x)1iTN70BcR3$VZt_;r=@eo_u71em?W2jrKQUIJw z!dW_TOBN+W28O5;<#jtm$$l<3`tM%{zhCpIi_-*YIWxibjl>2o#ZoQ$CNWv60>0dq z;Dx8F3A-IKT=RRfljpm>%C>y#u982yl~}9O!9gp@eDiS6=Mc#uUvY&783!>jCfbm+ zQ?oK!bioaxCu)iX1mTn<=mxSn;BmIC`zgYWI|X<(r|}aHyRv1I5y}Wppzp-4z{Y_l ze@Xm&^#G>3s$Mcd_I6~WX&8V-0KKMzIX<0s9RjvEYaxX3p0e*4Jlv}}4?vVxoGt94 zM>ab@w3h|Ndp#juxA}Qg})Nbz7?LVJ7pA{(OHP8CNISktPpT> z%cOP9GNGCFL?4O!MQ4&pW*}pu8k6Gz4 z8rSg1&h|k8O_=sJN+-(Q-_0I5o85k^6b&hz>yh)(Q?Dl;w!!Z7$wlQa8K+#7c{qRu zMEpB^LXinnfADKTy1u)W1%aTBFY{PH-nU8RgB`1B{hTiq0yxOfdF&IvRgFOU8p=c! zuZ${X8ue>j5P#B?sQyK%co@7FxOkOB8vzP$3bSRz!v~W`u+LUd&x3KWS6XTA$CviC z))D^(y^KVLH-Bcu9*}3_P!t;mtM@lg3*y9ZpLxpt01-8Pk>5 zDPnxcY1UbjX9bqrw%;m1biAwYm=S>OcJg^Uu4k2}uN$chHxipNU@Wj#?>jW2J??sP z_Ri&|X3QK$GlTxcY6mj%a-kHK3XeYVSw=)v7$Q1G!)5V27H!}l1xU71h`4K&b|2op zr1*pZJ45v=E%3541~uEAa(skOGecaA4OJ6)^Ymf1#+N;}bU}h`*Je<6^}x8_%{)1Y zBoKD0l3YBKzsn+EZ$T%E!h!(D&FID+W0>qcUIpD<@0LH}e|4ocvLYn9alsPh7S9qp zkiPq~l5bqI&#zK(p`1UFv+afaAdRs9d;b+&Bbk)P0(uSOdG3#?{3xPrq6a>^+gap~ z_kbM;$I7#y_(_NZv!2Hjrs1Bdz}#TOMR+ajkR&Sr51xV(ukSb(Ut;8?g?$t&V}Lx> z#TdK6w1pk6uItDni8%KxbTBwpKL>Z0LJB(AQj#e5c_JRsMlm_zuBZPX2#?_Rhi5h1s@dzM4frWVj2kfmv(mNJdzw>hKB>B6$(l1w%mXU$A0sQjH@q}t^KUU zFV4_P#s)wQ!mDwtCOtIIk#K-jWJF+lyaTNJ(NWQlX z+@7D0Oy!;9I9wRudg0B>Fc}>PCjfv58JIBNYkYH2*_0MC>{<3)&HX1iqItOZ<(UF?MydZz#;5kVbt>MdSU_Jemn}|$SnVLT3BZ?r z3=nnmn&1A_-9+{@m>$+Q^epssrF{j74evFxQwDxiBK0^$i+y4S+Ak+NxJ{KF37Vw) zI6yP@+-D^X)*j+eK+%8<5b^Cf@jg>9>l@yA|4Tb%kFszQ32gJ}vrehDcqW1ve|aP$blX^o`WpRPi!ZyfShM!`rR@$Q*c*sc9%<}8P|*u(w&D^TcgFdh*F0Vyf;oI z#&xxrDwN#@3{7tsZFX~rV8usAOTw;KtQvQsJAe>StDTJuxb9{MVki0r`WdPSB$OG3%eE5%I7 zCP;J%y1?P>HAxYcqHTQXK$!`&p?m83uA^DDR!(*PL4NByKA$V|XSpXg-`tUyC3J8@Y`14aRmmcWEdy!gVQdP$bDjjy6y#p*YSSig@US@ zabnoYlcpe~WbAF@`j^0tak%-&c>K-*rF#_=j@4*$nHf*V?8_(^SVCW3p)(51jKydZ za#kowbUPNE_W4Om&Az4eJ;lrvgWA85WR5YESOjyOpT6YW{L(pOcCAjULIQ(fb{KvLUGuIQJaigy%h zEEDX*pe0`xlyDup3vDx#N5?W9@lMMAEnWRui99||>KEbDM{l;-Av6cuZSqvV4mE`9 zpY;Q4{RKj+i@5|{6H)!bWq4@=9Sm&P4qEG%W6WcLnC71)=MS0BHZ*HqJWeg}jZ? z{AYcg6+$(8){&{wMFntN>o|l{mn&*(lxT8xZGifgEJlC;j5g7u&#n)L7g}*x42OF_ zKZ#m+1?PeMpb5zk#6(fvn@vNuJ9(x|3fSNkL3%F{d2=OSLYJCb7B6G|N+Yd{%}F@% z@iOzB-46M*2(K z%EEQ1)#!oO2APs*9wcNF;U+zInJD$vjr}PQs41iMEiSytIVffCny^+06sRLK#<<_O z+fiER%`qLWx2Mi@-)Bm%!M!G4Z@V-@QU zx{|`zEZ5bNDEyVeWo^Z23nK1q8Yqk=uN(+Gp%5|$g4^BU{Q#b zAw}{SYB1a;;QzO)@8Y^x-w7Z%f3cb@6|5CDQKl&zCeDN_sIfJh-a-J;WKGPI#nf+$ z1GDDwZNclZvzAhbc!U^;aAh7q$Dc)-SIU`RXituZfN`!7t2!WZ1QH4Xyp9CiK|+{Q zh_9dI&(6+*;^4&81{Tj#1~bPJ976O>M2Ll6Up*J#k$O>Kj)Ye>7QG|Q8-!f<X3gC&Z3i1QstzlXQmrs2JMywaXzA!G0%EY;bf^A!q*qOpwgt z8-CZl$}B*9_p`xR0eCmkiP)0H;Hdm)nPdZPy8k@v+e9ehoIzc<*$B?jIl7`y1$RcN z(=U`Yx-c;A(5ryIcDKe;cCV{kCNU^>mL+a^Z*6?KqN1$P<+qq)<8&yljXlBx5hMAj z>K_QkRWY2OMAV9*cl|HJP;<47O=SY%$^ONz0WY)BBL zxByefP-K$^1e=(Q8F!szk7w? ztw&B|B2}jma4VxXo`12yLn7+1mIu*mwk{tgAGo+30T|||G)rBxQXno0hUc}A(lBU3 z?~ZDv79$VlbORs^0uKO3;(vreJ~h=Dr$&C(o&H#RG6T||b~2~3KM(-%SSyv$v!sSh zs%Egcn?Hgz?aku@3f`qXg?7K*FLA+(hqgUF*;&7mv#3KOoi8Je+kLBX?Xpn1Z93ad zJxP=Dezkl8RBk*7UM%|@+DLvT+)1*@C}#gf1du)c+=mqxe(i;jtoBHy+5AD#L-bZ$ zROM@EC&OJni9~Serj6duy*iQVFd^U41lbYYSQuwn8m|B`Ilthu&F*n;%RSpsMZP%J zM5S#a5$a%)1Ddz$D%AOTy84;@ZsD4MPP{?i)o%}7m}j@vL|q|AdJ$WBYp^E#doMH* zbUaIEw)X;vyaYOP1P{TzE>S+VT#ieanVPDIQPa zEDpziold>G{QNi!qZ4hJzW6ikZIXO7Ljsxr}C(#sr3Ebp9^D{mmU~Gr;ZyJn& z$A@3dpM@{YXC59nTsl4|ps||PAx(T4plN@@wHXON|2t|ehV0GU^bHtw=yay<5PsIO zx_zdWoDDgCtnG9)WR0nZL*QI&MOu(9hnBA(D#ryLY=8U zaYb6TOdcycvv`?J)9foTNosChiMefel8{A{)vDDrX1%7iK`B14`~ zcqy(Kk{xd~lt`|VM?yd?dH~-wnls)gB$e_jT?{Oa{il5f!8)FveFZA2$3hZutX@qA zB6)tdRDw|Te^%GQu%=lCvRG5f1M}%(qXEYXCr6P-cdi~tY6XV z4{bG>;nf(RLZCMj3D??KQ?kto>l z3oy#B$rk&KOestX|5+wTrCeUzWBoQLA}^UHMozDQaAlPe?hgvR$@3EEfluv3$7{Bd zu1@eNp5y%>%fD5S^C6a$@NVh{S%3OmS9nGtfgL>kAMVb|XYVE6Jk%0hJAhoy$i8$G z%46kzP1Z1iX*5DA#4HtGFE7NJRaTECh1#@-b*S(6Ujzn} zCBn%&!>9E;o$xJKJiHquZTw+pgupP(Mlg3 zhoN|sW+p$kj{Ld3ndqGSF*Nv08Lx!Iqw`ptw$~MUmYcZ zhMW6Muw#?}00tEBLbS$G-_kqkJYfzIijDPp`>c4$2D+8TTp)ka4W_DZweBbzSo!|7r1M+O<(?Cf)t}RV{5p z6x>VhnJ-7&o znF`g07kc*QrHE{?byVy44sD;35?roB`lZDU^Ab+udM^vDBC3S%jdY%b5D?`Ip@?ZpH%zYsTn zY{EQ-fS5_gApy*6c#l#Q;aK)#fN2(;6%+P9RO1|L&b#NMu<6!S)kk&Jy9w)PAX$)y zbuMHiXJMVzW2v~M6HYLF6nq#vUcM4_29%Rw*1Jd{aKHKC(g8ihtw)r z455m66(W?E2=7EqU(FNjKKFg`Vr67QK_$BG2iT8h5{`Ig&G3{bYg*6C^(w|kO=RHc z(DiabZ$}yQGz-~Vz-y6LPGV;XBk>w--;y9%^R1y^&ufon#C<3!aJG9h&45Ldf#!r8 z&X=Icc01~nenRrcF+dJ%{L@)a=mn3e_iZZ)9fjY;&XHpsEsQ-7U-M_f*NtI>7Ix60 zedwHuXqF0oqK4KA%aZ?kF+m~f7K#7O3$&!az!#QjYIC$4m6!!#vB{eohco=nAaBd+ zS$!4;Jbr-OMg=P_yZU`}qn(-wfn2M+hA%cVdibd|Yqy$mV3o8EkHPWX6Xy0{M zvJr}=dQ#f9KBcBLjJqa6#j~d1gVwQ^EdaQ&%fqrkxKHuC0;VwLHOD;KwW2w&Jj-zl zxbNQ)JM1$cGx>aoF0l8mc>I^Q<`CC^qvz`DAp^0sAW(ZWWz$17GkI<*DU;KYwYB8H z!>gSiA}6g1i9V4LgQGackJD= zfG8mBgopC$=jcPS)jCVMYWh+w38z>_cV03+KT&sdA(#52u5rk)p@8}=0N=B{uL$0> zl*KEa%f|Tqn4xE`>iwbvZRm-PK3jYtyA4q;!DV_d%E}oA?2jB0bF1e5#`;AtGy^>d z8WF7h1wxvMPUpL2QsWsA<#({Ls@HxGX7YaGUBj#!w&lyH(BV&4PPgx4+_cwNpSJ=3 z0;6Rrjd|_$e4zBY4UQ)Mjh>4Ype4O%fyn0E{-6`76kSR2GO}xK-8uP zJL5bFaB+;Uj=LkC0$tT7z@MUja$##gP zoTt=tfgaA%r?CS+$J5|r4`DvjWe*dE2gdKJTL82}xixXcshrG=zF4`K>X2@E83w4Q z!X*6}Az;C0RTCR(O#dwA4@aDI*c$(jTW_EAD`_4}JluBuP>9yfKprxFij!8|J_lm- zSBSD&xL%9lS&t5YgZsOA-hCCl${|lVjOxVc7$a_E!#|bP8D2|NwJ!05wIHVO8mU3l z1Z{gvPyFF#$fVV0*Mr`IZ``U+iu6R>nvyHkLV#U2i~OtxrhTx6nW=Xo$2L}bwM)9% zK9ykri@|eO6FgCFSjC}U;*T(HZKd5SNX(tYNbb2Ga@9=drwl+FcAb=cx@Rlz zBf?P!)&xccBNaaOf03i>s|hX$c1iHF9m4 zf_oTuhCXRX^rr<()F6%NGmK$3wj_Q~Y$azlRN9cY>2n!LnOi*qCSOPDl@KuPS}&!+H1#eJ|l`J`VnF8GC#K9R`Kbu8wE zTBc-SF1k-hFl-xKgt@YW!_aQwp!yvEry`W$=ROzija&|K;L1+{EhihDBTdKA*mmgm zKUAsWCf(2KlA45-f+MWn8CPYw=+3UlTeirgjK~^cIGL%{kMGC+1{bjf6BBSR%y5r7 zt*m0Osd&s(dEpnKghxLB^1>fdR$|=Ub_7|LLF}(}V5ofOR~FgTvdU0n0jK4#ESfdW z1%xa~%?IKhVmh1>n3A)76NOC9HJKDx_PsH$XEKHiOGca{8P|z2*_roYnw&K}mK<%r z>FPU>K^^xau@H2uD7aZ&e9=A1uY0G_3Q zB+11}Kr#0iSwi@NH&en}WxDaLopVj|40YI(2d2=?u7#oxJvVjc?=8+!c^TOLhMB-Y zKaSK(Ep#KcQ35#zIA8&k|6NC|!9zQUt*-OBWrx&H)KSi%T` zKK75#-?X9J;Dic7>Ma*(rWdoTyc7(%nW{ui!}D}b%%?Y@)Gu0za?blxzn%Hb0K;oTVi|uo=Q_v*xj|O7!2?9vQJ?V|8T5#_8&KZ)*cGK2&*Zz&;r^I6F&?;}6 ztqP)_GO0DT-NK(|wOB6qaI-Tw6p+4ic$?_ouDaMy9OU@*J6$;Tej*8@hO`ha?S;EB zXYvjj&5(_4Lk!sJcE@-K%X~|@dvTB4wz5`ch%fb31(@wDBb;huMSqnlTne7o8%e&o z10risq1${6Q<1zb+6lH@;cMV-Spzqq*h_s@s5JV)G`{1_6GFG3aKoC#fV~#RZyq`2 zSd-F|q5uvj><^Q_t2f9~CA8w*v2uA2l2?Hp7LiFo&g>Jr;d+EeTLndF47R0SjHZV` z(5*+6Q7!hBeWmXoF5zt?e zOx}}=1P}pLJjINV<}+J*p>=|Y78Px%XnxQ50Ol8MPgAZ7Ma-X)e3q0Dg3iE4LKFYy} zXZOMcALq*$agqyot*Ibh^5O!Hd_gq0d7hA*t%D6M)056e)%{YnUDP0ss$S_a%KWgl zuXT8u2?0WjoU&@A{!LXI`5)wRxY{3_lw;<1cf2Tq-Q-8cb@K*l+HI^u5q5%5CT^CP z0Mou-0CEuGhiFulofJ~qDh{_jSlD;IHyA~YYH+RLf7c;D-sj%JV#Lc+c%a1=4<3nc z-XZ;AM1j2@w(qvJ9!v2VjD1b!*K|VrDg`xxE!cQZz(<;DbaVMcaw}alYw0G*Yf+Rj zxLJrzq&H&Yaq}1KJmDz63u@&%@svh~inIdMLw--Iqka0~QU79l7>}8G6OOzuQc6FS z>&`XcJ>b{F<;Gw1;j@sdc!xY;DeuFcodyv^hCd@j_YF2*ZVY68D%tR(SnVG#2dBq4 zTIBq4aO#t4bOyaBA%F3}XV6v{ESX~Vju_siSh@clT6&pe<-}&J!hy8$b1bsj0YGFCzVf27|R{Kb}eOuTVxP7eMhkcfSY=^Nic4 zoQSPd*2GvKY0n5otOetCY~yMO^w~qzVYI5o9~Zivq}>+G7?YHa-6%`VjiaWEs-M2p zVuO~UCy{+Z-qic)B*`&aC1naa+Xqp+tf*Th&DGdeOUrq;iGgy`Q(gPjT{geZ5F!#8 zC1Jt81K9uc)8_^%|8tk>GSw+Gtbj)Yr;!Va=%TxoWD*UJ{)p;u00Pxb#LdLYS!b2_qz$jbG85uu2NQ zJ9zni&cGVAnvPhn^r%_leljLEbQ;MCYq}tGJ%rXINb=S$yK=IT&4P2=JQ$3`c8#;0h0Ca`*5cr?8Anxj1UgS0>THt zXIAS(xw(gs9yd^G@&|TmDj}-M3aL(O;3;nI2H-&#Eeb#{;SaZ**n#rpE;oopCPXqh zZ1@AxX}TMD-P!iPxY2x2pS`%*V_Y;xRmr0U2Uog4B1Ow-N8}_}N3K3kV~;N4wu6LO zS!}gvH6QblA3=sOD zDL-x8g~07WM6QEjH8m56q@yF|pai&&FFc_P{6Maf;I+UeGVyzS#MKz&wr14w_FTKp zWR?jq24|eT|6xh=#YqBi!iVkpzZNLtP8tgoojx1O8x>8=#3mKb7UGpcFX zqpL#Aio9Py?h~To@y!a}4*zLxw|`M^)dT{0>l!Dft`5DGgE^iI?M;p8>h`PNjG%^q z<5;O8dgn|RjEk*~Ho?DegbOP?8>h_pozNA9HFT>x0LWL?<%%?>eLH6fQJ49w@BA;A z9c}P3MN+nFEzi-7`-FqPa&BHr>zxU=LS(DxBuUl9`foH_ybDpLRz6~CYuKV8FblZ_ z!%fvO@Wc6)XimU>N7DnG|74K}ZysV^(UqaJgTBP^7J9~tpR}+vTmul((`kk(iMOkQ z=UiI^vG@RjSrq0*RLXATYLD^U)ahVYUL|RuR4tNCoM;fF(;s^Iq)U$OI`%s)E!8CL zLY?c5@>uK5%E3r@=cT7P2ubBZli>tDrij3i9?qv4BKPAjRw11NIH^3w00#eNXN_FZ zWcJ!pT_OyBI$5;nk<`@iynXNjiCEb#VXYJB)*5DKUg{c$RDMxj8}+VM=#sB>RRDGk zl50KT(9vj3^z9~OqnLu$y_;UIkqin69_TGw%|Z2ZUuP!+_pg^+kcE&iO#%fsW3KN#HC<_l`Mii^CA_g^{6^MVV=@%k# zx=6}y(6IR1IOvcUXBdD1dx_jjh4`(93oA9FIxUh*usl;Hlg-7#ShRhVF90H`L$==B$(VnVw(nELTU{$Zzem6%yu!3LBfG z^QXCKr^ZZix(XU4*tA0!HtX{Su0LPk$Y4E|HX^uEHIxX?VC?CmPU@Z`ZkBOAiQIKR zLkJga{PLfNe&K3?+-uXj#Zkh@Z}I5y!0nMU$vQXsH~%`|t6X_qfFawEBNBO4w?*q~ z$QnVwZw&&FFUayIzn*(Nv=E`TT#AP3)~exuok-!u_K#2$h%q2@l(Yn+Xu%UXB%D^( zeR(*?`L#tlwTKDtU%OUAkV9)R?9Fcq+A+LPkuw*0$b?+tx1_YfFCV*0b5!p_x0!vb zz|mMN@*Sy(M|hRY<9|vj080%yWdukWtc%_}i|oxBc(I_zm5F{TIa(4LFd}>cULI9j zLBl5=61)O4Q(gXXN(&A}+4gufE-p5vKr$RvB!)YC?oS$0U;L zGv`f8Mq8SPW$vnC0+lw=OpyP(QUF=-nQr`2mUvy82f?4A(E2d*P4tk!An%mU<|PHqzP6>|szFOuGga{OJMZ^uHpTS5 ztN=FXEFxkrZXfnjM6(#-3F@FDcQY%n;K)Sln7gcpG20>~Wl>#3zNQB;e%kC?1en4k z2tZS<2nF*OqnTXnYszK(6QiWVlZssFQ335%bju@HmXmHMvtS6y7Z3K{to)I7UEr^z z9+B*CJ0@l+v0LMje7oS<`Bltjly|+Ie%j}3B+0Dsp^vRzcg2TRIn;m&!S#-?RUJn2 zY0Feo-#`v0nZ|rcsH4;yqy&0%ac5jNm@!BQ7MYrga}EItglM~q7ORBGFYxQVb{_z9 z`K9fa2@82sA!*~S0(oLK7EDrpSqy?{GY6LqOCBlH*JY6UPZdro1)G>+JZeUq0=xlx z99UjA5F)Ve!!0{j?~4*!A6RRRwlpG%-6){mMKhv3e+bOFlzB1Bljd>Ihe10{A3LZ3G++zu18yw_vW1>bW*&mLTD zUc3yUrKZRhDvne(&C_hw@jYxNf@yrPQ5Z09Eh0( zf2mM1czgb`SEC#`JvW>D>;(PKfB;sdE;s_R9PQ@qyOr@8pK~!%&e>x#KIR2dQ4)g3 zaRr#|Au;6U8!$`tCrJ(wFeQb)0JOjg>g*@h<*v@R9RA7H=|~cfvpO*mm%eslyY>GFo3+%PNnc zLK5`Qi&&!x)^ly*tbq1u{ts<6KCRuOEw>Mo%nfxhkY{LHK@y37suO`C){LYzc{A}Mp3on2?u|7YaMMrKg~6HdE$>Ta)sTEqx#hSFA&fXSkG zLutcYo!tCjh{~`Z(+ zRSjcbllLf{&{`bgoM1-q7QP8wP!hnBFZT~=3{7b13?sYNR@-qN#$B6y4*FI%lGFXY zPKg8JS$$gd;3|WG+SKYA8sMcG)WY;6v#;Q8@f3Wos1A``1 zb?eUlH_H#pMuNxcm&N$=U#&qoqr*|BU0h6{06##$zpr8F9ILenbwc(Pb{8+NwQ((YC?-ME-(t^UOLv6kA%(A zU~AKq+knZ~Bjtg;Va=!EE*e?ZT;R;MYnE)EWJ;=4r7o(YzO=B zA!&LY`<_4pX!r}~MwQewN4L`P13ns6j)#~^t+VWqGjVC~QAXCCgdD4a0Z@>JZvI47 zq6nv*jNMPV)W)iGA1BeWnIY+8PgWX4j}d)yW<0bh{L?t$>agepE^LFM6Ccrjcsv84y4XBsU;IO;Ntj(9_PaN8N7xfB&&wG-^`TE2p_myxh z`TCKid6Nxgz`)rs=*o6Vn3j++Dk*XbR9_9?ETI{%B3*DMtkx$W5rt}**`rMpFAJSS z<-1<*gA0cAOu;w=6VKM8?7&#&J`kR37xy~#c0?PnT*DJFaiWcKwkkU~$e%q9$Cd^7M?s5kYzPbyqLV#jag)L8JZH2wQM+nom zi|2Cc=^mt(dne-Zn55kgA!MbOPaCg)hRD7~ZSX6hDVpA;vN9Qeo_*>&25S-jq;D1q zuD+88d*C<# z1bY7dxO0``h~?{smYI3lFHkH~-8G1Cf8}V$_j?E{nTCoYch{o~DoR4P_fnMDgdUX@ z@nf3?ILoJG;x1LSHtyB5ZMnXjC=Ti zh2Vf!Z=)YF01?cN`|{@V8UL=R6z0DTw4Z1+Jwrq+a{UFdxj38u0s^L3SK|zQCoRtsLD)X1T=Ohe zinsx3D(O=@wz&S(;yHR&oQjOWn9|EUC054z%8o^rHes*G%_29CV4uGR@%)4y8k-WP z_-i=k6Qi=EDjDqsy;Yu4hNYQC9$j++c&|$X#Y~r}drXacK*yVrvLKFty;M6}B%A)l zWCS5}(PmW1wJ%{bt#LaijK~{^KuhggD>kcCgW1q6AQ@6!j39i)nkJL>AF+rJQ=5iA zhE2-?Cr{F@SNo+D#X5DQ3cyzB!|u8GD!ne2d;O~~;Kan-c}n!uyx6|Qz>^+myoNW)zY2rdAl1nMz^|%7wvM=+RZ`xVPj7WvoDH5@ept_D#NA1%WV_ZX%VLj zD0_E3Pehroj|qFHKl)$UxM6#Pm~XF@Vx71Zk6p9K5yf@Y^Sa{>pMfw~#1OL$)?gzX z(1@mXmPg!`We}RV0mT4XY&6}JW^)P<6(%J)9l^06ueDe{`lAdg`c|e@R5@d=yfa|-#sqk;4 zyZ0>?zW*pd>lVBos-w|`^hCbaPE^mV@r)2ovUR`!|3|b7RZyC=BvM zqpDFv6>CQ!JrVOq5frya;sog?urhO6H3_{<6_T!7&k%LS=<6TEl9Deyy4K@?1!&AS zI}vh$Nwk+n`OpKx0Ok=Sj_$^s8R9$11ExmX%rzmk10`{Nbz;MKN3Rf=y>P12q#%= zd0$;aK)b86eYs@`U;k#)QvxtEo;*jkK*!!IyPl(3oW)PmARlx=@JI#xp@o||E_g7L z#|IU$svzl@N-C`Npv9-CL$`AIhXjhL2*TVds{ zYCE+68OVcf^6vZ7BSf*~UFe{;#dq7UYZu*T@*g~KK=k*ULYdT~6TCKFI%UFZBFxER2^ z%6GS7J1lx*FkzLD>kJb#c~O2LeCkx-_pwi2sP8es%Ith6q77lve%DxPMwcpk{>mgH zgKB8}(iMWoev7aJyposirHdG90jQ1Y>DM~qwHdWm2<(c>6c9a}cSmbW&;oPD;q4ZSU5`WYz~`Ypuwz^^@6DaJ5&U%p zspa*7?5?J?^d2NB@GnCJ2oT=c^ik7fep@-(!85Dvk_V49Oe789Irqe|`vve$g6-k5 zKG*vSqQJGJI0^H$4TZmKLcE%tqdhzX?l#26&W*kV+J(nTaN*|KT8-rAThmi&gCq6i z36NzM7y=2cFx8Wt%l>U(F`bL$jz2@&JE?5pBM^gaj zCL%YzEB(;qi|wA9H{V-@f*j|L_d#bij)oB;*alO?(N{-1%^^h3!BnDs7l zwr}9W>(&}jYGtkeZ{_db%qKk6IgVKaZOd`3yhwZ{ZL#`+Z7zd#Zl|7uj%xtlX$jxa ztPyJn0Fl2?Cm_uzp?=KPNuQVWfqG6wzrn{QheJVawbQPj*%ySxCcyvI`gLDARMF-8 z)jydB6DBQM4ftm;vmEFUDdHccV%GsGJ`1;rfVAeyO1@e{VuaDAsA6|gETPHX3K${- zWogahV~M8`nIT5P#`_SqA!dldK96l7Xry#!&|7K2J&P$V=uC)PK&)wh3k(kyqoSo} zuoiuQ8RP=P@&Bm`E?%lms3w-+wv1$5u7$j@S^?OITuK#inLdfH{9rXgp0+y|3o_}(Qe5>YvM_b6;G&RBlO1FcLAn)c6M zTlgu%4NJPizP6`{oWa}w#i(<1-dwp_l; z!3BARusVT;7p0g%;Ewon%KgWWsl;UiG?hk0D|{o@;4Hk4{yzzN;1-+~xb|5sl+dy8 zEg)dkhq|5$q&g8OBIDS54MCHD>lpX-;on#hX|I#TPQm}@y$RQ&@R~PF$p-lErq$& zY)@*!{W|z_H6+!hG1J_&-^5s!<*1Mfv7|iACTkHe`eRkzp68?5?-r^(fiQ>9Y9kG- zd~cseTqYZ4y_X7U>u$M#8ZLIzxw}=w2&&Y~=l`4^EM!y)CuRDRVxQ+x)$!bmA=x|u zt{5-l@^dz4{k4rr)$KymC>H8@^2dqU*-b)YkU)A5bhv3<_fMR@#q>g>Kw&B+%7WbQ_h?}N<*o&l`Kp^Bxwpe<`ZFeh1V5W{Ry+>+!Q%;~D2h%}cj&_(+*Tqn z1GDcg+m~&9(v|v$PpJTHD#U5Ge?kbb-nNxjedB2%sML=7z~3*xbMfQrU@vS^rURnD zKps_ug5pkEqa$a$y6{@aUmx+qAE(W| z?1c>GoJre>MqVo75(Ggkjssr9i?b0%v65q5>8#_54RuI{<_*b%g-q(Ep(E{2Xg#r@=j#cRUp*T(?yVV7fiv#RH7 zXmav#f4t1@&3nPlJypJD)kjN5?F4wMegpUApt0ylqOSdiP~wZ5v%Q@6l-uG+=T%&> zXjSBnS2}t>sIflu!H&G#&9V#D#!fx%QSvmcSgPa7UC&NbQrx)Z3jO992p-s3QPCX zPpE2@I~Kw&GLl~;NDy&000F;u#DNO9CT1j0iO2lN+4U}$8siVyn0W#>mPWr|-Hf23 z@f8F&U;GAISdY)b_E=w_dgGYFfvxuH8@no2Ff6w?2@JGrovurY^@;YC$i>ABxN`bQ zyU_`i+VS{m=0=nbsk*@Ooz|>*Z$9!C1(B-9!rYZP!*#bZW^@4wD6_@J6`f7T9&#p% zJLU3)rGBQ|1AC|crh(jcNt!UsE`p1jJT zFPQB<`S(e@Qn~%OHtdP53mysH6QM8Q2L-0mMUa?%Qmx&eM72?a4xhV2 zg?m+a_`P~a4B-q46qocADBpzMnwTc3Vn`jfMei6ft zEs#YtYhS5EWf(j~9wkI6ORfe|n7`=grWeuzy;7UFBrdaYha{#pgnHk19X^v8MaWl+ zgW5Z2?}EB6aesoy^YWlq06v3Tjs%Sb=v3OB-PI{GKH8k#3N!e_osi8J)PAvdISvaN zc<|+B8h1Ss^NxfI6>8Z2KBsBw=CVIsy80lcsF|P6qUy{XEaxbCS2E^&Z5vhWccc-c zA>S(hv|ntrlA#rGbw_bDiZ(+pr=vX$Tq^hl4iXp_^JS(2G2lu>_nIhCW}h=^eDl73 ze?=pn*~fva@L2~E|Fl21Ji7^LOXmQH7anC&CY+nnToGQz&*!JXgF8Z$4o{`pU=`P2Iimw5&heP z<=|p&R;Hn0uyW=ue#{al`^p~%8;}_9FI!S4eecKOm}8#J2XF@roh8`ece>iUCip|w zQ{)|0pIKU-VW3*8TW!(m3AvM-fsM6xRV$2Hg7PdO*d7#>jJU2$NJ!2S(N{?oYHW50 z7pcPkA}or?;SNFQZ-_Ykp!{54f^Ky!FHv1#HH(LH<=&m}xhyZ#w`YfgrUdAw)RP3G zFd4j(ddDM(fj@5PVA7g#tQOi=X}=pD+Aadn+FOzr4Tfnw6v_`A%*>u$WU6nR?!~{O z`)Y(B*Z<~)d+e0z^>{eZy@3!^Xb2U8c{5CLr|tj8^T+m!zD9hkC;twNYW z*=F)SIgXT{S;rs_X3M(qV&G_svnY9xjJ@m~3DqK3cGwA$&(nZPvfy%J<7L}AaAiF> z4|HP@2h15H`)%o)sy35y_n*<_`nuZ)eJPQ!az+krS3CWDOM#|VDr;jrj4g7~^#YNx0vE!T zp)b9+^AWa8-JUAFqOll!HSQLoojKa&|H#q67tjs_RDFN(@uPFyJF3cXe&`3dqC~Tw$_?$(KNR;jA zQZ+3Sx{}p5LiX%vEu>2OJqwy-jev{6H@;*s5bnMh8oYrAp!Ow}0XqX-q<>Ua_f>Z%Q8p$vqmQ z7+sAN+vqjy`znpgm*~te&MfmE z?U)n-Z#6C)9|xZVozR zcUUJv#JRps%8yN^1aD@AlB4K~Q0O)x6*u&fy-76&FM{AGOPhGDZXi3EkIA(-{qE`% zK)s{e$BHI-(i)yYISB7O@LpGmBDnVeRAu9Da9qeCQk>P2bMnOeldrDZC|tsW%#f5_ zLnuldUdm;=ND8H&T@o7n08~xHGLs4FH#T>-6U7-r@|ahs?UE|1N;!kTD}I0l$k<>K z7vQ>TpZ-Ad^G+wndQYVapVfGn*qUY(VC2?aJ2>mtbEi9kB7KoUEnG~WrhY-6h0A<5 zax|!_RN-=3GZPw~Z6+6J^|Sv!J}%hD9gA49NZd8mi<()sAZz`AIlD6|9+|)WqT-k+ zuOIvKiL6`6rXy#c=vt9fYwS!9cYlH zd4i|$VEY1` zEV+3N*S}MzO!QGciLJd68Yg#F_ze5Rpyh=^p}|ms@yf<1 z$#DfI3TF)_lk00$lFJ6<&sMJ7r%x$I&944KPnDl8wiw)HGbaAqmY= z`w_~Hw4g@ytuo+Yh(hw*CkJS4TbpV^Syyoa%GyX! z>!yh#+}Hp`9&B>ajC;DUxo-HEHIYbBSz0VfZh0SeqyZp>cncoQyLEzC;flX2T~G_=A|QdPt+-3nam%ZH zTfvK-q>M<(mf7&x;oRL&OELOqMo+)SA1vXH|Ec6<#FN>aLz=gIqgXOIGhWu>^hWz1 zV%QwzouQ?z$>nTKS3=SO*g}t0b(wwj^;(;?p}4!K`HxQNlC69f=SgG7J46t@9Sd^Z z$D`qtF)W>5j}b?ks6cjKo>_a)Tij~}D8z$O@N!`6g_k|3kh9G|9?d)bd?B{9T$E!) z4T1D~^nF{^@mJF|Zl#|>C$%LqJ`uvvBsI02yU$J143P@b8XqNL2B`L6Cy{8H#?^xn z#wWq4oGjLn`TnKItJqy;f&ss`I=O`~0I~G19K0W>Erwb^i+NO{5;v+2HZf&qbJa1t zJv+|By7=HO3Oq1IKLCOEAIEe;$06o^pA!OYUx^jwx(d5wf}h7F3DpmX?!O10${Jz`(0bE_K^w!PX!}~r-_+MUuWn3iNQutFQ0MXTXM@$A0tV> zq(TUY>=19!mowhb`~A)BicE)_(`tzUlE8F(0Qqp!KE3WMAL&cvMK( z+aB>LHgETw)R4QzpRBP(6G`lJRJ9f%a(Xqe9Qx;QiADPe;^$^C^ncTdOhs`>Fu5f6CrS_sZMIvW0`arv&CWMxG?gRMS_)hDXSL zH<_s?94GFjS`%H$mXCv#KfGsSmmGbIVRMRLFnE@Y*}K(I`3w*?M@B!CT77c!X`V%to^3qfq_E1RghGfN6H?JLVO5sfjDJFlk3b8xyAHySE`Mx#IpFc zUCr4*L8V$q5^qU05M^lm5N#~f2Qsa~7>Y$!TN5$*RP5N zp^E^FAd+UtixvwX4Nxf=kmr+}8^lm)O_xX6o4YGoj@B~vQ`LUMm^{o|NgZs_o-~5m zEJ;Zb+7WtV4ga;DR5*1{$kp()dZkox;FMDC0BoOhDmv5B+ zXRPE;Tk>?{LN3Ge>9APEVsll*NDXmjhmHrXaIl~GR4$c z9IwpOOSz7vhibsxPCe)YWYX>1hEkGoK*LO7%?IkpVn6n%3nP|$r~E^*4}{j&OU}^I z?>~UFx=Mg$TLPBXBtw{~Cq7R2f!!}lPS4if5zl`HYX#GBYagpddW;`|q#In)5!^pM z7fJ`%-N)K7%M8yCOGfA0|BZ(D4F=p0+d0XWtV;1gjPYNlRpy2CLmZ8hGwav%I(#bS-{2$;j$X z=;1m|f61F-uT}j#&XLJ#EQGo`o zqPmP!TJ%hd-cgcbnC+-H&6HVEMlCmD1inyQ0Krh4_NeBT!1I$WePwlv@B~z~IZ8!O zbBSxnRWt)GGIlHkScD20*20`0{%1iex;)stpB=oeEu@0JpiL^Myo)h=l`=`#BD^|{ zkcAj`q;2OY++lIMywu1xFG(&DMq)BqfO=r4E&K|qUH@aF^U6o`B78YMu~u?2mad>78Z zm9enXDl5m|JgoYTkI4_uw#`hy1S8g(s~`4a+5-0F>oNUQ=BzZpvsEOjo_p=7 z$6n&t3KJZ-_!deO4?ZT8EfrRu(+14aF*+gF77 zU?4ih5Ur1^Zs?AOk|}N518i6gNL&Bf^sZdZaChTS=v@abz zxjDGWNs>Cq2_pi*IDowm`QnI4bhGgs>1othDWW~Tkze3Ya>PyHLTKVlv*BEq$ZeB) zZ>M1y_>p0A#Tu>BG3m5>=Kk<&R8g~I6YZ#IZ;hsypwY=j=5;49EgJIbtbUC&0D@kG z_i8f+%grY4V4;z}!=H$JZl4qh3LDT^$;@-cyuW34@!i&YdU%B?)E4lM!(lZP+~ePc zFq%}xluu?!ZrJ`U9~&FPzy8$EsIO;SP5;1erc@IQw2C)gy=B|?-#NW08R8evZ?8SV z(muPVcsx#djyY2bEVZHo=?EDk(_UuD&{8`KS8l#u&y!9kyyqB0%JV))K!a^M4#%)gQID=1oG9CjZnqZ<9X{%2QVxC8Qr zP^d-$6SMG?zFS&F)C0!mHhZ|e;c#D6!*c!nF-xvm$$P%}nbaE0`ayeyG-MWiTYCd* zKTCJ6y|GE+y}E;sxh{r-zC4tRysn3C34WuK>=%D{YQqbpO`YAUuc!LDXax|wZj+{} zV{8N*wN>7S7?&1yWR8Ko+Mm5+qEn>AAhVlXwZ`5+vX1B0U~kY_z?ieM$))L^PE3?v`xXDa&7g!^7kL2~T1N}wl{ zFOQm_FHm-27GbtoL#iTx<~`?Qc^vJ;fQ!|EVZmh?a>Aq1`DPK+>!g#Rp`%JkZ!4-Q zjgR+#&(>BwbgwXZE)!Lv^+hT6sAHq2mgsrp?*cE;yMS99fL)Hd2e@AvvKJyFd|_dt z?_~L{Ai{@bKoy?84#)qoWC?nP)O~*RE!+K?Z`kBo23Rv}9`ZJ|Af;qRN-i&}{6OdN zIE$As=SY^3rgJ6>`KR-bPLo6c0~P z<0d2-jFHLxVc?E0BMf#Eonzfk-5D@d+(5ZehBHEK^5cp8M zC1T(}BkOxhs0YI`;Yk0o*C~MT@&YjYFP6$cu64x~2m;+kCVeJrqBnpLe!do1yUPEH z3;eB|`1Va{6F63QqUl|5Wm?%zaJmIHVT4V@0KP$gcGxnkega*E_)y-~83!|dkI$&G zD|-L3! z!?q)N0Ml|C4s>TN?Z+f>`$XhIA;jRe?iiTU{X|dy&P%`K zWXwg~y~$~YQD{md7WtVq_AfScH@yS`)sy;HNWi-}@5P79Z%62WGFQHc3`Qa=G0F1H zvElfAeP%nb-S#)}(n61#@$?eX8-lo!YKWwhsORLzr~I#UgiDh!U&<(((iN#^7SiR)7n5CEXE`uKxlyb4aag2uPo6C ze<<@10l_uK{=TT5(aY(%1_P#cJX7yg_VzIx;S2y_=!onQlpC$b3A{~CkuG$W?4x;~ z!2y%e`V7xvp;25FA)A{)CG}bd*xB&x8f@-V;ER6cKR%DE&t1+M=rF~rmtci=>scT} zFEsXKFdy~fPaw}HYRO6zH5*O0luG}Ens&n7U1bx6gMR4+*c)wWd@)az5MLk!`jCf> zp~Qr3x^6dg@qQ_Mi*TwwRSvK$VQbfSc!~}hy7vPMOUM9f8Pv$zNHv|Tx2<*KN6biGM} zV9C-Nx}}ZC=<#wwwrsO>Mp z@4&?Vw8j^5&f`8h3?Vz?cXNA8sX1RD$+4U)JIiZ3!XAAX{o-86%%(R{GxeTEz7ShS z0-_S`L7Hq`G}I6MAiL7R&6bK~M3D?2yw2~3BiAFr`q&uIZP&iVP}FOSFADL&fX*z4 z9PfrOe6XL@?fNEG2YGX5obqnAi1t5s zt~M=*zRZ>kcjWYUb8Vkav<>@~(bTKu88v3QnJX5QaSFqI2TDQZq@(ZGb=Y~#oGUarO(6PfGsBIc?%ywU`Z^s zVp0EQSE4!Sp+)H=tGPn!jeao2ptKLjjfFM_$!I9Z?w!>RC0xt*N9{XWW?!0w%+G89 z4!qR+TAO6GAeFhi875(Sj%2sqCRot2f>uPwk`!3-{76fvD$p4~`K~SU4Yj~|+32F^lB>_MjBPIgzj}t7&rHrKJZNGek2ZhI-=n%H_ zx?_io$OO!-J;az|^^sl5Q)Mc+FHmD`p6gY0W48LoQjzC+hTog?ffvAw`iP}nPNDip+W~Zf7!ClZ zyuY7U6rLjSxco?qj7|$>{CFvKzg5ab_G=}_{0ryF5?ZH>?}MD6k1hx+e-~=5@QFI6 zMbGNK3fl961?$~mQjqXea)u5W@UDYigy72CuiQ~Qdz*GpG|hBGkthUF%pZ7?@RdHm z{(DsxQBg9Y_Bqhy2t?9vg-8jDdK(o)s81es*9|Nm8o!&#N4$B|`@gSH$|^n2P|qeO_g3<($kSU)R?HZ8fXMk5YX_ei1)vNTsAP1Rzabe;MX-ex9Uwx3z|!5GK5T4z`ue z1n*|bC@|Ebk1=G>pHko-)wpu(^YNh8y!{YmJxg!}0HhQuVgXEH@g1QlJ7k23f3Cut zdNZgqi+nt^<~yefjs7--l~T;(q8kdL4NPQGd3z|i(L=20^`h-T8U~};T=(2#1O%z_WKVk8<7Qg zlo%(qtp*~svDL#~^XYjW==V9pS%w(lIw^w<#k>4+R4w|A0jl(dJY* z%X{*%job!YGNX)Az)4um9Pxejq+meWnQl>d85E$Ab&dNjy}RN~D9vb=fO499*hAXW!ju!r)~pG9 z!R}1S_f0RBnCAmiKoaq-Uf@Iu`pCg52)z~Py{EjFpX=+HirveafU47F`~fa0w(J~% ztkIWUbn0lnS8SIO$}AxD=0qumIx#k-Udqw-yl;>)ycnAu)6+ooGqvhb-&i2=J8<&j zVCi3CaZcf>p`e3v%|Fm zr}n0WBPccOdlFQb5Q0+UJIdb#B)pV>5^B~vMt6UYl@$F01n7A+ zbM#*YeC}eR%jYuPE_c`l^C?4!Ju9^=@#+ADpxth17P8+UJmDvBSQqrgrVe>0i8&Oh zA)O)fhR%uADcbjaz2tCn3TI@Ll0%3;*LU!~x8o;HhP~i$H$hEs&Il7%!0w4=uR>Bv7rY) z2Z5lmT|v=+2viz18&*v20-o~q%&>WI)UC3Q2lFHU6vN|Th9p5xe;Eq=jM@vL>19RF zz=|#2u^A`c=XX1cCH!Sm;xd@vk1anbd=-N4atkrKqrm>g^meQz#n>AT4R{O8Ppg#On5>q&d+8^kO|kL>E(@$Szf6zK{N zp0EjE$Z?zNjlzlYzfPHrIYvoih{#p7;&6bwA%Ui&d_hFAf&KOQfSI}(YRMh zfgz+grjmH1C(jw+oU(qF|5e?RL^$D7y|MfXQX&USoZ&VDD^F=hA;g6;2h=YUlU*H4)}>{R57?nC4}Da-6M&O%nRCFT)`dnK#jDDNaM z{TL+2Wz~+;46XM7nbR0P|<*Ryz|b#FgW0O(wrG0^w&+` zrb*jkw~7K2F9V{^Y`FPW!?@=j`g?I`Mo?K93-f_?77s}1VN=4S=lzy7$(p*vAFH<+ z{zKT9vJ&z=AULM|YLj2m;B2q$woY_IFziXbkO^Kt_=S2litBa@;OX!pw`=`~Ny&>k zdSk8SZ2N^6PPe6j*g;up?ZTA30&w zgc4v)wS{|<4T%d&Dvamxn(L06q)&%NQVM(j6(ZEk*_QN=2>p>KnY+vk9&E5yqf{VC zHRR8DsZ3`IkrK&t4yWiGzjB$7Y3AtqH$962LUFWytmXb9WfQxc^dVC*7~VYBn(N0` zr(N4-i%3|&LeTdyKwr|E1*BvxH)>Z=_u|)5 zAJ5~2ZB*n-$;2V8)j4OdI1C+*(U1ZQGi$12C;u=mG3hZTng~JX5$=0pbWmK>6k~k6k&;q)-8sVOdQfE7GJvb9tZ7{rb(tK+9;5#Uky~H+8;aQ z7g<{m%Sj^JMMuCyUE^ryKP@wF{d$qwE16Y0%dT#{GhMAQ4%Y2RW1tAuGNkZ$tw2ja zp9_p`=1eiZjbzSu7}a-7WaBLLNw)#IAQ>W<6RXutMzwC5k9_+Y$2KG7ne6psML@Nn z)g!wZc3B^Ihn4%nd1dw~FJps(fQ7V<2@s_9>-ECwFu*+8Ri*S; zT|V1F@S|^Pj&>pG;&7<--O>6&QYG%uCy0e_1e2uiH|k-Kqfrfl$UrlTFs|i7wb1yH z8T~6$AAA&)BQnNxJLwNb-Z?gjiL96wwB)nzK5xwd9)P4LPCoUME=g|=xZMy3=`2LT z2$~7db41SlKF^JT0nU2uQbF2D)Eitt2D^WVVqo@k#s?${{X@|`z!xMMbSE?s^<1t8 zAp_w5JA~Z?v_R0s)il=<6a4h|%OV>SU6Mm;CUZlc6lw}Ei)6$*F`fo9(R{oIE5?kF zwnYr?XM?afpwr{JZ&D}y4<1J}0!g=Wf7qg^NHL0*d3ZM2G3YkHtPmE-kLI@pqO{E84P$c}3M#pWymqBh z84xA$POnM9c90w<*mO2=hws>-TQy11oyRGmWbB|_DbU)ql2`$;YJ+1vTD!g9QfXCv1m?uw(%I z@~f9`CpO(%aLKb1QRC?R<*fGn4W_fWl_Ka_Wyt)mRe?TRh)tsXE09(U2!?GR#^x^) z6EI+QZHBX6qXTD|^l!|7)16DDbJ*^Ub!zZ%)J^5rbA1oae99 zWc;u4+4Hs1rYs2PM?b1^3TT~G*V5X&m5U({wK>=YMcZLlhK)&FH)e-x@T471)wWAX z@W31gsGXyg*mCV=JQ_FEcyk<-ptAQm?{gWP ziho`Q%Z^x|kYE=CuKvx&lPhj`DVs)}RUhE&A53iyns9*z@K1@P4`OyMm?|#BoBy}{ z-)*pQ(fTKivpyd|;4GlnndHukjm*}X*6k3Nj44;RxKxpbzn10=)xyXnQIxxzm$h%8 zVMo@kGN_14V$_l=0?UyoigHAFmJV~j)DGB0| z9+crC80mdni}Hkm&FJ&_J~~fX1dWzR`Xy6r<*_1>zz!v40;!5tM!}Df)}|Vm-Jvec zNHL@fykVkU1YN26Hko<(oP4fuH-2~~wza_ekt&2iI#KW`lo|JO9`Jh^Bk4O^s1bJ; zm$IPM^=`~$3K__jBw0OGsH68{Ie(p2UqpPBgYND(8qALuv2+l9OvB9eJ zvPRH}Y{HK^azkR-m4|W-(V@5dxg zh*7f1&htKAADCC0T#aO=Vd+uPi>yVmU^}Dqc08+B1o?pl z)B36pO)j-dyOd&qRU0257>hn;acUHu{630mDEKhGt;(fP)wa9e;2~IaUzX^+l5poT z${;|5mu$vrFrg2w%2~*LcML803G4<>dpU?F`DU+mb z)@LajF*E7!t=mdYn;x<}z!~`20!{q^jk-_(8xW4%n|bzO@|T;M3l{|~lT=6^0R>!d zm*@nUR9Db45^Fo`y^9}dfVmVF2}v^j+bsl~7&}#W0;z2HFu{z6DlP&5Fc3@IL@q3{ zzL&=RBYn7NsJOav&K5$L9NLJg_nXsw-0=2d%*5l+mm1f(00EsL<(=&&;_+1GZC(3h zuytTJ8c&||C^uMt!Gh=FjWO`i?>F}_C4DA3jS)Ya8I6KmNZBiGPLQ(}C9^Bx9@9dC zrhSO}N>0UWi)*;djypk@pKeg}<5xxOm@#mfW7}0Z6Jbk-=^vn9b(<4iUxM>Yz=NNr zEWFf&OCLyxp;$aM{{DZSX_Qi&1k z8oh_JzPM^sI*Mr=8m);ke0a~791|$bvA*{M8UHE<*L>6|NlEs z(>d>Qv$2Fxr?tl>D`K`ifBCO1cy>p119uLP1$&AHy&h#A*_M0%K19%SpzP!{A-l1g z=oWv0S9dnWBydGlav-=g)fzoYONd6V$wbEmfoky929Nvt5=8ey@cT=HyrSaMhlb^U zG#T4u2~BVCk4tjySZobO_Zg;RYadGNdb(Rh@aJy5M6!l&rL28I06kSxuQf)6 z&Ya3*A>!3AKtsqWzU!@pS5HCCAjfQ6y|g7S5PvbKn%Yttf3cib-7+x2YX#;eiPw<$ z6|q$=>Ty7~1-x$Lhk6d20Ps)!9Z+=uKpYZTEt-xN{Ku{$s;Gf$?TRqwn(_-z-vXLj zn-ni2e-PL>S>-h`WFS|{(qp%-MxH;{taQUZjPn>srN!%#%p8X)it69;kG0Gh-Knf) z{47&K!NZ6dZP~4f!Y#jGGcgAh-{L+D-BU$>b|<# zFz26`An&}>1J=WQ6t|hc^y>9Brw=6Pd(Bca%=-vMj-Mh@2e8)(dxB^8RtSkxKXY2#Hvt&j{6igZ&i^Ob4RUKg@w3mmPvU_V{&e>MSpnhalh@9r zbY*Y?@=D`djSBEJqJfY#YTugs)yry|K=E=RUw=$F^s%HYxqI%)ODN+#8pBsV?)s*V z{o=)K^%hpINLdh1pGlPjxjH~1kU-&$y?Zc5E1bSwdRg(D)#ThJ4Yh}LmxrO|Deh`X za+;;+og(M8p{XR8t3_F+@flUHmrwnSY&gEW)CcieH!k39%m1J5VJ(QtEFlh0RKU@uNfJ}?<#d;;b)L5%f`t$)As5>pEyObvio-OF>VK@9<__NJ4aNKvQoSj@tBV}W}P?k!+i}u7-eN!CemBglh=Xfdl($!&n)51^zeRNPif*I8xNrt zRK^c-|Hr5CE}u?op&@_5`W*{-l>jNWH>eA8k9beiL@>I>hE`+ZEX#IZ!Oc7)VI}-$ zI*#Mct*W|rS&&L^il|$#15gReEx!f{2Y3fl9)}n~Xeo^xe#R&h$JpYwaMYWwqvU>y z$(^8y7%p3o$s(bBS>09|ONnU*zrLC{zY%Z_7L#bqF_R+jI2optbhA8iv&>Pt%ua5y z#kgQ`x344VRhbJVA_|%E_z~8^2D(tvwTp=dxy5`=ffF18@XKqWN4Vi?ab_ME2D`o+ z33aG7%SOc$uWKq)BT^gNlI45FrDf#@v7-+=cU=9--xQ#)c0~#~IJJKcw>;RxQB5E$ z=pD8Zk8+>T$RR^Lyn39`?#0=lqI?Z)yEmb+vk9cMu_tFy>!-l4uoAR&o&Of1v58PP z$J#nREEAG!+JoY3K}d3FX82&_l9HpIdu}n^GcwYq@>(ib9oeQiaD)hOyQ91|AG)ra z#mNzD!ar*xF+k5=vlHjxkA)Z$&Zn7I?%33;RPf?85d8q~?pz?+P#0TC)4n{m_k=^_ zqUnP3v#_{%5C7Q?IxxVrS6k^lpQLQ=dtdWl*&u4bqEWT)4ldD`{xq%*rVn>ek1k9m zFsF6^*pw{#>zFxHs8FWlgLQ*xrF!WBU36!6B0vIaSp071?!-^^p5sNuArq68(}hZZ zCnVh>&cf6P%X@d(J~WBjr|---M%RmKINlNFDCwDLUTVNRqhcMhL`#Pb0tQ^436-E`IJ<9T@D-R_$m+T2-*0iI^d2Xs0nMSzPF~Q= zkJ-h^qJ%?vTINKhA>fMd$--&jU9ej}ORa`<1L$`$v?(T}t*DB>;^~2aL9Wj8LlfvL8I!h6wX6_o&d*T=r&BAur{ zKRy_XeC3V#wX17Q$F#>*pVJoMKjb@LeakOk0hM+?QB2>nG&v!BxiU}rN<@fvH~-!YLsBrD8J9EcEv@cu~z zqM3!l>ads$Vg?iCsac~j^2j>uNB`UP#DK@aCN?D(o@@o0bYCYyU6B%H?xFvhIcfrHF<0xOoKyDS`7cEb( zCC}GU!&BL-K?OEkOF+m}{hKJ*YpkD{C!07ZC@DV$*3)$7CNdg6@#k#Cuc@Evv2oQ` z)w-0PF*M&@kDZ`4Yp>)rO%y#E!MZC=B@KRBT^|xgEFX+KL$D9biP;jLQgrxOM$|iw z1QPyvDF(EL^mP*jiKOVz^t0(0UJG!v$$__Ni(sdwkNh{m=w6=aKyrC#H+wSJQz1 z5GE0%O`RYVYrdRai0|N&l-%Tz9v#F)#xy#uy9CB+DDj*9KsOK zjZS%H5`qfZc*_~nU)U>t)|V&(Rs|%$dr}kC9%!-Wsl7D*UKcncjR&G7d`om^0JNyQ z5#NE=9g4bQ*3f^8aE4+0h$U?a?%{edW^Q8twfF!q_;vi)jv%v=@}M z=%TVjIAHR&XEM&>!=VXf1!g)$YxQSUx)jZpz%9}WQg_3}t#zZg>=^?ySPKT;XSG&H zqO{&ztnEe7b>U*n#6|d?#l-*BH z_4nL~91-2(G}w)WIp?uyb0k_a7bMutSR3P6u=7&S)7i8;N5>mC3dr{KSyy%h7V6yN zX#o|~!QPAu`P<09yqmYZVyP8-nFr&!#$1YAwXku`MLIy?l|sB64m6h8xJgTEh20I$ zyOrnhyumgFlt^%r;PWlpE2?(mc=VM?lzkn)DSNdH+bj%p)LF z5jsLMu%EWdz82R#{};$IR%!wPTCJBQ+oo6z@wgbWLJy6WY;&hb2d z!~KHL&z~Sqj9R(cqTT*DKY`1Rzh65T$LrEU!;g&yXReeFy4=}zOSkbU-!_6E*rhZ4 zG}6IJpBI+uCD$oPP;bZ})K45$+e7U_fG$wf1w5*Ookbxpiw~3RWm&EfN&om-k{-GS z2__9_u{|{0TMk!ptBc(`Frz4$!WB?Hol0uc8Dj4~FPNz>W5!{8k`!brOzu6ay}s;U zr>l!}IMW%#_`E$Qm=KqH5;JMLque|en~6zK>61qU7N5L};fpd~Wz^{b0Kz&12*|QV z7yeXI(wQTLUCI*6zSl4IuTZp{jK3{S;Tl=%CjrC|F18Z>EmYJTYpH4A@&I;F@-$)4 z5f)66@SYa2zB+4+e+Svp1PqWOq3DE~I1N7uz}Sp#7IANk8X%$%Tu&n7=3btR6cl^B z3v)lYZezhHG6yW`D^rUl#2@=1cqna7{n9=WQs5j=f#*eo?fj2H1KZaXai*p)^0=*s zIAgQk6R@sl*aks&Y9e|~jjhcws!C-sTl%Q%@+_lkU-;#fn&06mH9BGl7SS9P{oyVx zyjlU&F;5Dz%E61D&u}t0T@~u3&BvD3#bG^AOiN zs?rEG(FRrUaQ1yYfFO8!w_tpvWRXGi#&{jC&|3~^aut5UoK>_@L8Op~AT=XvF)r`% zj=V)Apb7_`J>{Q2NE*{SGp&hd_A#ImxSX7gx{z5qq(*o~MhN6TrAQ(z$+!|bG%b8^ zilK`$wLOJ{_#;Q}BfUX9CsQ(!ei>p!Qxc+JxD?^^kY_=g43#*ycfzSzdtMv`;=NF2J@XzqS&2Xm9(J_N9>$3{Y>Grfv5XQN z-11^SiVXY~G4{Z1JE*9QaGf~QgJessJGp=e&Y=LCCrA}*&^60MAubm~i}bmAYc9Qv zMYfku_E@3DsS!I4zmSCTz4=eQjQ*ptIIbh=N-UVyK>@1m%YlnkIYW`^>w0v<&Q;Ei zTgaINJg=N^LSr9IL1_%APp*1DvsnLy^@2f%8LQdbO!{gwkchGn86&!cY&HyS1I9#2 zlkjbJxs4E`nQ)vBH!#w_3tP{^adSU1A_#u0uK*9?&zHic$zIl0h>UXZh?$eH&~gtSXIyf006=iW^R-5oRj+oX?~&hvBSKu4F+WN6Np`)xciSr zce~(!`o;WSsJG3Ur~7gIH`bF|I7+8i66Kc7m4c~Nf)DXY*KKWn!B+VB2|~7HS@F zE6Bj%5cZL@oN)FWcPNOMLYE;Ny}42kqdfZqUB zuo#))L18nNfB*ox=B(E{h!phQ29`E(io3;TGCM}G9%h{oEr@Q zA=W-aB!=!4&vak-YIO4Z`0xEm?>4rFlB3GyAf@QhkMz8YB|c}`A&m3@Ia2yLc3-pZ zZorf;$SNeuALyE2s;NIw3`L!z6F0+4XrPMW=rUK$GxPB*G?*mIg2rZ|+0VouFQP&U zMxf5je9sowhhIkk00000000WsG-te}9xNbO87aI(9c0gqAan`DK8+$|>mDs{4+J*) zhh}YFS-+b#YNA{uP>Y8}y{j+gcmVGp{;s1{Wr-YH7?)Hma}cZ<3HCbeNeu@X1@M`|A!}qR~UM5VpJq`xwnN%^{fs)0ko)`d6i8tM7YN9KFc}WUChem>T}& z94z>+o=24^OSfD>E|7zfL2$@FZOXx)5_a=*7nyFFvB`Z6T7S8bCIf_CM8{3WHsUjI zBajnwv(BSUsK_X4K->wJ#W}G1^3*IOZnKnzIT{%cPY*kerq^sLpUsy!5SKU~0}Ol4 zSy!yInJ^eCrwR{mVsM+vO&?jNW9&<5!p2%^QjBJ&^mPdl-lDXJ574zYs~_5VI;V?y zT@I>)5)(=Q00003p<<^pMo1V?>AjTcwfpXv2_bdcOK`IH9{I{*Lx0AF*;YC2NFHlKrKFLsiig4Q!RfbS@NlvrrJzxIg5zY7qGJZZ%} z7bXZp6blZ+u{Qb2x^LIB7{qo%&T*8_5TcI1yucYb1Z;1d`6euG;R1Td_JF=9#_df0 zuam8CD!R4#OAg|J(6y4p85%46x~!89egg0Z!@K5Sy-eTAo**%K6(f;@~V< z{Y?ZZ-YN{`VYC4(EFqqJA$jZWIs6ceeZTz!O|8FXX147+2wR%pz`I|{O=ncV>>g?XY!P2TB0&@ump~>mR%JZYnm}?>2O#ds%+`? znjt^WPk9Ej==P_31#L->slUzhFg@+__b?8N819}Qbp_xjd-f?o6KF_ZgT+*^a ziTj{N$)5W9W9{QmOqww=sC#w8UG(#LSsTMLRW>r<00008&Tl^dez|_JXMM@Oz_CaW znu&9USD*9={zuMfA;i%PI@S|p96-vw7clt4x#7Pue5i3KZ#? z=K%`)tyKN=*uQggpu|q4wgdH?VfIRsC?y$ydn=yVhKtrl!B zm2MRDEjS@vD)MM127X%_`HvAle)Iz;BH6};Em-oSFs=`ImszSU`mwWgoe-p$^*Heg zHAwl?<&mJ>JfHcMMd-gcH^pF-JggAGZ}&iuokhXd_~C*Ms@}BK5oQk@=B~CFMuZ0t z&V?XS!4Xhd46^s#eQ(b0_CCKOT}A|eT;5o^tx%<9F8mk%W8Z2#MSZv_vSY(B! zr%$)3J_qLL+hm~Yyzh5i0_vV+;4vImusUBcJfk!h(zJ)hPRewbY<;Mm@mmu(U8qoN zL1pbX%D)kL)u(&)luu_*!M@9pRxYpO;C#egKknVWo$M|V2Zz3z(BLc`IyHag+hir_ zWKb4Aw}0?Rr+PzDw_aE5Z%%;N=lFvB-$mv?kl?BU61I@MdIxit6Mi&RBQEHTk2xOf zMD90Q=W=QT`8xx?0$Ut^H9u^!)#`Dz$C3XkHA;QIlbS(Fg)n0xTv8pNKEwXN8k_Mp zArDJCapy^&OFIVXtCEHWE`cmTqkyIx=f{9iuTP*;vm5-Vko^@{?kls|0n_ z2M@W6+^i7%f62(nyXpl@ALuO$N-8^T65~4}A_BU1nu1y?5*&|BZ{UQam6M~n_lais zm|<7_`JeECSw(Vy*>(fXw+4a{y_cfc6kBhjqCunxw*u-#+aa5uT}>UJCR#@u<<9D1 zK+G6U>Td;M?Jo~N>S@OIQgE2Qbl>N3D#Np9?OqHuXiBUO`u2{Oqi&e6T@s%nX-0P` z6N3`z1Vgnt=w01O!7nKa1#U&@%owy7p`1Gw_I#iDWuZbG8kyo{oj{M`D<$l-<^^;e zX=9w>PZSj7DlqbLGNQNx&?i@Xgjy^RcNIE<-z~Na)mVdRDC^htzmG79@+mFuu7e1! z#X#^COzMgIHH>{ZFf3;&<>uwN*#s`ua9&;_!}3qMNiG<+O-` z9bTxBZjN8C3p;e;aAxm}))$89M5Q-LE)`lvt zTSCYs&=LyJM1t=4Z_(${?;g#AYi!9a94Hels{X5EI zLfPY#KKfbkNJOyxvz9Q}LnI8ZXh2A|KV1iwdZU>jOwa#jyvhVMt)Ur8amvHfW$|s^ znoMI1HpOe-TPfFcX9a+P-(dv!u>UA zsy!v!<)ZDH9uQeXt?t*tYGH(p$f82kC+vxcyAm;;rQFUf%OsO` z?z9gp;uhH@Duy9dV$|j1W``KIEW^xYxMagrZv|VU7xYdo@L0;SI8nfKPh!+{B4!6o z7X@sjPJir2%+D<#PQw+i;`^dk-1+3eOShhTgFj{V3CK&~to;IcKUj@cmsDtaAfk{5 zhPI=GQ|+wNERY}kG zhZE9Hv%@Lu=cad{Ab*=M93WP3{#Js89?Rm6+;U0rG*&@yayv?g?$YP? zFE1l%ZA(;{o*Wq>AJAaBD7*}|&)4-|-AndCGk_&@CoVh%nz3Y<)F}*u$k*8jeg`t_ z1{|+AWVgO9XV<65pP(P*Sl{@)S;_fN1_a*45bin$*V9vF@DIwh-wEZii{2`YUkir7 zqMos;cSpHlwrC(^ezU5^%z70S`UjNIw)p-miOR%wcCEx1!a-{S+`?*H-pOVZUVC92u z9yuTw5C~>MN>!i-l$6J2J#4xTi#&UV7>}oF0tXr{2)tcSPeyeD%UG<041I9d zw|-QzUft<@WVgXtp@L}J=xc`9=ssY}8&>a;$T@Zg`3Zl?_T@)y!O9YQc1U~Xy3JP2 ziez)wEKqV93B*{42dR@FQ=clm36OxSw_-IHOFqm;)!k0Z6Ktec?d?)ArewjJ00000 z3_!o^FadT7t=Mk`;1p$tR#gHG91clUUVRP6b}In@C-ExBMWuV%sNFm~ggc!cKLV8; zN3e11)k_Owb3}Cy8Hgwd1RySPo0Kp5#66*P_h<)mBlQ>;=c6xluZ99b79FjO)ksCjUk=Xy03RXTv%Vy%=3fVp}T8@e1VsZ4|)I?yoV zD}?6|%W@{5NHTOed=`CXT3fmkbQvVlipxk+;#-s725y_VLc_9Quqs`LoT8{&RPI4l zU8W!`a36&PmQ!IowM>ih(ro1SLiV8mMy-Joo}{gURqr_&lKv@pk83w+Yl1mJJ4HK5 z;LjZncT!s9=wU-N6QpgQKdnO(17v37n*A?4&0Rj9UomJ)21Y4ej{FmO--ZggP}l)2 z^aus}D#m^A%SM}&1FIYAd)2wT5rIAsN5~;^-gT#(u(U5iX^@Ik0x6c0R&t1PNHIG9 za7Ic{vm@4W`wR|n^DTzd0m?+-NLhG!z2i|_N5gd1YaNoJjc~m1+0WJ#iYLr7smYVd z;m@iPd2q{%-;p2>mJl#aY&5<9ZCwfNTua_GA5-ESgY+@A#8h^SUP4)*^z4qgp(j1-4nG z6>Hz38~KPB<&e$aOY-`CXO|J zz}k-;GX{3$iHu`N{zPZ~>}I=Y3-+i-ZQH1Vjc`*1sgQ1W{h&@1?FiYcpCjohy*B^= R000000000000000008JNMC$+m literal 0 HcmV?d00001 diff --git a/bsp/nxp/imx/imx91/README.assets/image-20251210021421740.png b/bsp/nxp/imx/imx91/README.assets/image-20251210021421740.png new file mode 100644 index 0000000000000000000000000000000000000000..a15c5b5fa690e0d7641d3fd33baeae5d5cd7e68d GIT binary patch literal 11017 zcmaiacOYAD`+lgRMX4%kR_&U#TQyoj(b}~MC031^A$G0WYDK9Pd+!~i6cuX3-mO%L zS+Qe%Z2*AaJpe$+ zLrRDr**NkUz#jome*_7T#`CjG2KJK?jB>LG5cL{N z$J42j2`OH`6aVhb$jwPBM2&D=lR8%pe*{jHZ<58nz`%E@aS>X&UJhL>!TI0P*6=tm zcGic;`EG1gfO?{$qO|Td26$i&0uYxPnJ3tQqJ81=GMEN zFV|5Uk{3UQFE&`WZBdpw(kcnRoH@?=C|KXQh4OU+(V;bP4>%p>|OqGlD`QDE6_H5(spL&o9;^Iri z+83dX@^kF@+Lz0k(d>s)1v+G`ZMCkLh49QL$KMWpPP0H4qtbjZe@UO?h~az+-~AzE zKB%4b-f7k7ae*nNEX_i+HKp9e`n|I0u}Xz;^g&HwpKV+@HXcA^k?6R+6F$4bWx0irQ4} zT$ibDcb9B}75dZbY#g)kU1F#2U`!(vb=O>K(%;3U1|7%JW;0Vd2iI@xabXJBN^B)V ze_H`;b?q8>oIR%jPH7Aa$-2m@B*5atwy_J2JmUDTn(AKA$kNN-abW^Ay8=P}E68M2 z%WiWYr3QR$?}-0&FK+CTTP4B&&CX-_+FMbvh|d=+TW8g4( zKt}dR9OsX&-Q%9V3eM&NN&EvZ&tOSdVDnC zCrMF@df{A@ndJOe`)03_it42fk0gU?!d~zCyS4H9U$eyuqt$zmosLubm1p7VrfLaS zL*eS+dM?wHTaN0?k+B&XL#%TqUR&ciXXnilZt21f8zaSUj~s9#ISMDT4i4OY-xex< zHMn0m?Wlv>R4Ou%X^$LP=_3bVLe6c@bNH95WfY9V{g&+T9=81^yy)$LMx;74@VH3J z4={N@*1s>IrsVm~?QjiiG7H=58)A7C=Z{s^XfAoTRW7+?;``Pq_mi!QYzAq|JKrU~ zVKX=SIVSIuv+7#qWbd3ai^X~y&mzK(6N}<3?@pI!b#3H6amtD^n|Z1<$kj_N zmuM+pRrBa0T8c+h>q0$&BQkg22gjj;)d8v`SlyYnW47O(KKZWk`(wuwkF`x~C{Ih3 z@8R~Sj=Pnhq%bmNIP-X@S`u`UzA+k#RzA2^4_EojF2t?kx-~x0TEEtXomupx zZts!IE$whW<8r9ws~vut9_z7ix z%;t+t9ENU~1$y|2om+6B{61s2KTLg)A>fDG`M%DP?_+<%BQv>>@aui>mGA6u?jh%w z8CHo>E=-=3g>%?P)+wx*NXoZQjg?l=U(C7!m=1@ZLA z)ib+(My0;H2m5NJMaE}&bY92Gl{7dnKuE8c`YJ5vdn>pwDXS#0z)z%UTm5mxe$IY2 z*<%fuc}Y3ZE~&3Bz9(3)pE?ei%%>rHlGkRN=dEy52R0E(Z&a#2(^|s+YgaFR&z?%@ zfeJPH=ncs&rg!(6UM4s2r$@kf)ZYa4WBgNPT(+wVmyc~}^6xA~hX9my!acU}(J6LW zD)J7cLN0#Cg}olK)-X|3e*qy}%d!W5+nA>UC~__(5y+G9C;&pV!T_YX|K4&yU8A^DR-EA$P>W z84v%ozH&n%x$Y?#=iJe3*KF+jRm*BPQwC)^J#v20uVnG1{mF8MRrajV*cvE6#~p+t zPGEKksXRSTjOlvr?_nkV$tgp1oNkP#g>!*q*xK3}8?e~oG0-&PQlBDCc0X-<;o-vd zrJDC}n%n5C!-;(#0x!vhR*26;->-1;nZoho2mvDr-0SSM8Nt>xhk&DXWfx9{C4GVQe5JGM#PO29tFiJEs+>TE1De17tOJwEij5TH~Y?)gmNb)(|^47QWeryK$j5$84IU8Gi+0qcx=)*s7ihuV}Qvz zhl&cFd;wl);mib#YD;ceJNkOu{gUQ?^5t}01|{{$2vcn-JuZ~CBw*USsHb{V4%5%+ zpUWjQgpg|HW>bQ8lJ~Qk5WfZH0>pGZ>Y?^$V+(&G zTIJ@^s|XdHSP<8w6Kk8Mw^$xi5#LhRFMXYDah3#KDA^%c%*^gVcMZ(`U6vBB(bz7q z4nbj(fiAUvKe^lY06M`l*@LCo!!cX zyZ{m1j~4ld*HwABxa^*+X6dI8r(^w_zE5DIl{$ z8OR>*Sj!P0x4%9?J3O7OQ)WKjor4>kkzeIj+d9n%8QwVk51xGG@=Esz|F!6UbM^o0 z1`bn%*GK%*qVOqe!=&5nk*H|m!l7&VE}YoL+PW#_v9K_mklDUw7`CTNKVMkFAQ$|Q zj;g6UoHE>B({p38{Okv5XQvk<#Xax}yIkGqr912IJcV>$c3`@2Y++JsjVG2**q!jn z?WFYkxQJEs+tzag47%(F#uKYy9Ai~H@nczgCo$B1nzdL%Cbn!O5P4Oz(}>@oH8hk zM?SD=BmhWZ{^#$2a%JV;7LjS9Rl??iHoEvg(ptLhRaI5>4*N?5V>aJCED7f0<1?Ej zcwbXj_p9mm`nvsq-!8g-$}DmF{TDG6Y9We@$8No9((+Od@4`%5J?m#+Y?k)`~y`BMbQ^tomNMvVZap!v_PrUl|Kfy^vxVp>@Dh4#6 z6U2V6V5MpyJD9?(%!=}IZ-+;Gw9pAnV&&dBpnztuFd!cmQVm-EQe(|ps$uQu=!pH( zO{oUC*6AgK{l@-Thxi|HT}}>UVq~wvJk zp{nZsLa0Cc+BMsUbs;B<7Lg49Js0{|+voCs}wI(Aibh}`*w5aIV#@o$xqlL@*)+DDrqAfsDK_&N zvjxC*HF%gH_3g1W&UmFakl19RIs3hjQb)F-qY*o=^CGXQ~v zvKUd_VXD%rUi4s4c@a)*z6c1bR^5K&s(rcy7VqdA5GNLgl6>pM!qKVSnJX0aPc&$T z#&n719>p%$_lLpy`u2*3Z<^H%-*_K9qGv(Iqlv1}_J?=(LsK}BVyl{J8aAg(sOOjp ziHqDf4vI^PqhvM#{7{aOQO&uUfW&-h5vvsEW;Swm{TT{Vp^BEq_wng!B3(n(?8C5l+Z$Ey@(vaVqJ{_v6V|*UGKq6wkjqex$wX#r^CF> zFt2X%u+=P~hnHcW@f+JL(3@M_s!ZB(Q~NxbI$#SCZl(~KCA2w~6Ys**YBQWUF)?wK z(PyYes=X53mBU^hTgAcyMv_F?Y60@6GYKzNATU=mpN8k2Fqa6K^^v9?)h&I$h$xBi z2C3LYj#20CN~&RAw}?{*G>W+!-L$a|##r0efzX_u{2%H$YE;Ksh{)sOP{S@el<#KcO`A$MZulqr5@lXd3U=BeqAL~6h*P8H&EQ&Fm zGEDvat96^ zIkcmbt&@}B`4fH+^l)KawK}IB@;Pmtbbl*EUgnpg@@lr!Kbp z8Mjc%8+?%2n0D`rWyX8NdxcFy7}v(e2L4>w{$e%k8=P44hT(W1g&b%z(2BNxX{|=J zqnP=n;zyW+o@KVj5uvXZetz%x&I&ajSW7?VSiy&>^3}+C>78T7K!)+m2-pDUL&Nct zO|w4!b>SuNws_Woc<=YJ*nsA*Wq=8mufLU*FbNDUJtxY%jeWU17PEd|Ee7ND%&s57 zR6rm@mLGv1nsaWwxQJ}waaS7leiz3lA&aEnTb!tMFl}H>;_yXR@MzCGUfbD3y3f|0iwBG}t#DbH_5w-3>D$+jHB{ zhoiPA#!cabz!%dxNv*$GgN>(;t7VW~f|J{US^CbwuJ_z_r( z#-*)k*?d*DtxE13ZfX%1+pzNp3~%Wj&=u?7qK3vidk}?>&L}zpQg*-Fnix<+_Uk0J zA1oHVdAAtBq)mOAIz>7bw1!Bk><3XTmPu@#f&A-&w+YGQ>Dj6PAu3^=4?AXrV$yG{ zOI`%=Af3UW6Zk5{NBLhFtHCv@Y*oPHvnEm6?L%yLuinBwzdfpWPI%XKLXVS3V)zje zEh*F8LK!x*`qz{}0+Dxsw`DGcTh-z?Q9Csxn3}zxQ@V#Gz^NAa;$|D+DZ4XVWODviH|r>$TOn(pXBHxkV2l` za2ycws^j9I(#NjIjMn2~c(x;VY}nQH?D`=Zg5(7;&-~$m@b**&)HE`m90TJF#w-bJ}&o9>CJBQlWKUObbN3)=d3X~ zIq54tr9|sN0^~lYp*Rj6UzZ)^3OimUI4CPGe|5C8w39CoXE+X}t+^0vMC@$olhirX zX>$j^S+WG4YU;Bm%}Qo?OU|F++)I% z3QT-3)V=rT`PZG^@!HFqWOp#GlV9gSL-hBdee1QKZ6~G&sIo~#xjd$M6gp*a;-$jm zUo-y!;mgjl9g6f-F=U5w#FcsEk4(9v&f^~O@G88V>VI=-NuJ91UtoSBqomV|BZ5w^ zg(erv8pw{>Un*dm&ylMpv3zQ{jNjM}}eo#cucBwNi$eL5KA=XS?3`r^N zVrYeRl$m1&lU5!Sb!tusDWvedOED9xKU|ULGi{wXhiAX8WHvf@k`Ej%LIE{{a+a-b zU1rkE3e`_^4tj)(IpKCqOOG-txjz>~+_7kFp@gp^lQ z&@N2$Z5SsVvW2Jx>n%? z_aBBNKKE)lrTLchJYTMq$M7?9fnHDajADF_B;ApC`7-2=Yndfg>dUSz-AbQAhLJ1G?}z z^!`i!s9Aq?y@uG`O#wBX@(Wt6VQv&Gk&{Swwgd@`zO8 zTFFh@NTYklZKS`k6*&<1miraA}0BAT0y*{PI;}EV=FwkkiUfj2 zkO`>aDwj~W3V48`FH>q!4MV{65x4+%A5oMc+=}e@{r%L~0w!&?)t|IQ1{? zaFwpE@>Z$=Y1wWPsnDufa#*itVB$9bL?BZKugoQI0FM~hgM96zX=wwM9baknxoozJ zfC=eEopW=}rVF(xP`rh2c>A27zVHDr?xliVb75mq>F&jL*U>B_?UqIeHMy58j~btr zUNFD1RSN&D{HAefPrgW)I1BkhH70$Di{hux^5^nrYC5I7GZ|gWp7C1x6(>oU>ZU&R zM?}?xV}B~fYQ^LLYY2k==!MPqJv)E%l1_WQ0Iij?OHUOz%)4HPlbXz)W$iiZYab}h z`z>^w*b)EH!Bs*SkV%QePl$b7p1f?b;W(wO$j`@kIq0@@Q`q$lTU9=$G?uMg@OH&E z<>*^gyVLDN9YIPWr4LjF#*4Cnx1wc;Qc%}E;2GQhLeyx*0TxzT*QmHsfLk(;TKXSX zAT0%6B|C9u$v?l~{{io5X7eGol&vY87%o}5qiSkT)iFr?@CF`Rbf$XqDV((Ev=VLvM2qKGriKOgnU7c7(Is6CPfak%X+9@arWm;bG!hAlM@ao(x!P^{uFtdT(*F&TZnpLr!FxC98E>)D4_N2M2+I}w)`r^%B6 zn0%PghT6!}EFC=+tt#~xrG1U!U5!)w?TB%~jdy0(;XJdoHgV{*zqqx~&jfyjPWos^ zcwtx-GTzmY4E&X2BI|5Yt^00_MZ}?(=z!aJx77i=Dtc02?)r0f!!Q%sx!%sPuoy=D z+Rs%^8ZPxA6SJaLQ4dV^PM+av1!qGnpF7=II^TwXyncqBWnp66Ee>t`Ek=>C5Da6_ z{ZMhqyrl_*i%{u=6Owvx_9^sx4O>T0m1=}mi2`)aASY7K6H)3tJW6K4oJ5iED7C)# zSlxNDoh>e?3g^`)@_bj^|Iw`);TK6co-4tu#%Trptf9Pg(VS^dczRhwhrWMT+2`cP zlU-g#Z1TdG@~>wv zi+vm-*`4VZ2F9eRc1R7VPLK&9vM;|C?N?aj60c~5{dfpsj!u4VXluB%D|jk&O_=@) zWAxgR+K#3Ur$dzQ5zdOto@JNtCLi9$W8GZh4`#CNH7Ad zRT$k|T0h(?CObcE)ctDQD_b{Hj7qk>s#0lqW6iqt!Oui_Nsa+c*-a1fx$EXM`?j{$ zI)^r+F-Zw7AMpZ+fM1TQ^l2rE#P3zxWs1Q1TLxIu)7#mQukBUCAetg~TravT(xp{A zA$>tqp8tCav6>_TNi5QLp zA0zX5hYp3U`^xEIO@m_61z@`R84iOqUVHMtVDA&OnB&~nt;FDo!c($An6-pU$pYX{D}K4>{0jLlML-DVMmh9F z=?YuyqcXu)m~*j3o|`Ei5upMxUzzO_%KRwlA!&+|TF>5*fK^#aWp3(qsC8(GUCXbt zzG3R&T%wd(Hc(qZ7a<+ZVF;^&q4-U2%@fj@+(U97=c(~urePq>9djnX!LV&XP+-|cSmp4!5G>W6iHoH$m>({kr9Zwn*<7IqAS~-6Ix+Gqd zb$EW(#lmJ_Wb}ZNbRnDkOCYbDdxQv4u*J)h9HGBK^z{DW*4!%=4O;O)E~lk-nT2Xg z>OHA8>vh1~Yb?xme^YfaF_1UN2R>Sz>1>bAk zs33ox|2ev1-a7DFh)|P=ZW^D7Wh&M4Uv8r}alfOzCy)uVt%RiUzlQ0yFcsgsQw6?5 zqkRQml{au(8MAC8yzBZvdF{SoSQ76#>L6;e|7PR`Xn>ZlTEnBYuo6RQqj+r}V-+iW zIRklFE}{2`x-y7rHOz!w=-a5aa4jsQE#!etp|EaHY#1Ws5u`R5HNFlHbmWwsnRf8c zI74prm|t7CGXNL-9#Zk7*7An+wiI>-tdcMP7M5{spYDq2;Zchmd8n{(+h;hjFvowU z6b%i3^%B%KG)T;J1a!Dd0-~qz{O1#%h?HR@!6BW5w%@vk>23sF9|_4yd~6@m`H)+s ze&0A11*1D7(5cRJYm$~0+ECk1MufdwO(IFW44G0Dn^Dwvb&a*SZi|zWHj=+as!?2aJ1{vuq9G(q zW5kN1c4he=#;BByW>*>*nA3k%Qb2NRQnKl~stXvFZughxv!0@+F;E5ifiVj)q7R{+ zlOK%h`CTrB=k_cPZs}5(zt$_wup^5m`FrCV@ZdE@rKo>ujQ^oGGnmS!2gDCSJ3E9zC->jzZ@F~J&dNjOiuB}WL2It zZGO`_yObp*Z?Qb*Sh}RM>d{Y@#oD4|kNx*=ik(#1y}znmGeewiw~pcaUsNI8WoZ6& zhR|RyyXI8t{NS7E|~t4WBEn`Zpw*DO`pg z268nx%!qvYT7Bgq`b>R^AMnOdXX?8XNd+(ry70W+>7^M4coB*AVvtN{d_Y7iuYmU* zDlS^WIc>tS(@*)&GJ+X&Z31IehA0+he{GnIY|9OrLDea`zP*BP&E;Pywp}-aJo^3X zS-;=y=`tGfo0_WQ?xi)Y%jIdGM48*A2^4Nxl5-5i%lJ*CP8uZPwoyeCKNTDniYc*Pg8JBd-(CRntcI}U;{{l z_RoWPkXE=bzkP(7$)#U-?#0Joa#&`NwBjP#iWU|VvwDuMGKjPfOR_tr1|$)0Rq zH(hzq`~S&Qohs&U`=gT{dOm{W2eTe3zM z4x|(;yS`^6=KX-kQFR#yzG@CJ@WIq(GL}ERu2vbnVJy-hP(9gc9wH?)$kfAtMzOnIGYw(|3*JbMQp$$sW;ERw{9(yzg?3yVy{Lsx`INsfvP5g~W1|QkU|GnJyFD~_83;fAhgD%_i&FWA>^E_1~l}!bq?VS5}sN`QK zR;Dc^03|1^H--g3-`r1ob$E==_x~!OR@v?E_Vr4e`E1n>NnbOME*Nca#G&w_c*GEZ zo_(*fNF(#H}DOs{ET-u@ES9e45aZt^1K zYvaQ?bDIKIf2$$J_0GY;!E)oq$O|z+O!21Sbe2}ks&uNU7I?|3I(J0Zz~U%CWBD4>8eV=37k9ALOh z;o19V{w_|Z0daCLs=0)puB06inVEs5G;PdCklds*)jwTf8H~M&gD7;Tj|e<0L!V@} zCw!5cfof<5=q^E$e%Zb#7U>;c74B8+E&h5ork|N@7O;0G1*y*1dC_0HnL;r5jbUj| z@N#~=wWlT*s(hSXRN~TVW?}Pg=L%?ss5}(m@`VVNlWx-h?2d$<=)Ah@`HY+|Rs*t3A}8m! zAJmWI&RRG&-9O$u%oybkfUJx`JTDhPgNrs>ml==>zhlUbvKDm!MsDfySlutwXV&oa zfaKCmVD>UU#)j^EZmZ*B!bX(RQSOZ7y2`baipA4EanAn7a!&IR+jH1tp_dR~|LIP7 zK-1~Pc}LbfbhSI`lF1Jvx8-|wBzpqVp9=7~oUD{-aeVu8j42e~Dkho0(ZAH>_E&$W k(;}kzO6tsf-g`;1C+|-h{sZ?J-`fgM0jeujJU4&;A3u?a8vpbACG3^D%DL0*r$Hdlx#!Q6v_PPv-$9@w z0)HI^-buf*Gz+{O@z7Fv3@Yy9SOI}B-R*w=T~%)VG3sC~UH zDj%8}++y(H!_B4n;q9z5ek@+cvR;nL=_WeXmEI(zI_|Ig-Rw+s;1|$&W?2{r^j3mrf++sf-0``SjC3w(x~aOJ zAh(h{;`4IxyYUea=-P2PSoQc&jfil8C~#1zNoO?NzAZO-5Nm_}-uXj8H^ideL88x? zj5n>q`sol1*I_BvWYbZv>83Cl9*_ZlZ3i>{nP}0;bNF(>(T1T?y%ql}pr7uG8x+>T zb8U*ZQbv4C^+hfvkW!ciMfuq6+CLgKs|AVqJv5I?S0{+zY#t2m7t0lggc_)lvPd?K zkldW1Ot-69McCAc5p-pfgMHjrJdJM6c|erJrep*|T<$h1AP9aX0$7BW+Ni=8vhJ;XhJ?S+vcIK4-x#s=7 z5`EDk-4o!yHywwQYX&3t+sWNv#$%<) z)=Ahq?3F;KqH8lWp^A3caUQ4HL|u@j627p6-uKws0^P5y>0dSCAE7u zcV;u_+HMN|Bu78UG(V9(H$ziz*{B*an!JlIi}*S7i(7-8={ELh|GxI*9Yw>nYxYHY zXM`OeRO3v{`+k_&BF}If@Js+#NPJEX61x3q%Ef)28#MdD_zO03?^{!Y$QF^X5vS5@ zYTX-%k`Wb|G+9TQisN}2^qrw8#BJd(<;+TrPqktgP)Z>T6 z=X|0|+ob}tH^?>_#>}rgcX4T>ij5aX2y;%Eep9u$1dIAauPqWw4W?7aGo!=M=#3`m2OQ9yKL;xR9!DU%9CYZ;&7Wd7806P{7cu=xMn#rP~&`!@wl#E$9Y}3Vtjq^@HdEpAO5oeUEKva(OGA< zPOKUBuIwJ)T?7%XX%uc&qh+0^wpZ7iHmFSa0;j5(?C=D}Nf0RQ&4H`nz+Uo5jb!}^ z%tT-)Nu=A&38(@bDVAk#(dGP>qT^>kAiM>+m@%A{TnxF5u^UYs6cK4StPlzA^11s! zDfn`MDRoulEZ&Wey#%o!z4YAT{85kS;HQA~5!kb5JJ+v~;a=}=D^>Xxvi#K+rE zHT-ft7q##?b9V~t26|K%(&M1HSO8d>?d%FY%=M9Zknm z7^3xyt3L`SFf1CHxK_<{ebl0KglvAvne+WD(UfbJFRuCthnPe?Q3KU zu$Ik)x7Y6<-J0HL>57kboTgioSfiz->MaXM#669;@}Ir!=j@!WWcKm3T&tj5%LcIhWcOGS|&kn2>BH_eV%H7=TO=U0<r!dB3IV()J+j^p?_l!gaHWP@_~Qf9h*hS9ul zZcT;D=fF`ys*x+A*Y@7?`-;XCkL2AZ?u6$am0Ads9lB}NsMljPAKD7B%1|^v->n{T zb!zi&LX`81;$eGj`K@~UE!@0^rrHnBzm=A&B@E>-?3`v^`MEfac+p7k1OwCrwT0G=g#e@hm5$y>UYVhu=aJEd`-Mq@NBrFS1$J zsBrEm~j?StN*1V-Y^YJCR8$Y8tU-?8a z)qL7PO7t2X4hs!Hjz-gMZ}7tQ*PAr7`i%J!xqxqfYuEj+vR^6}cTL{Vc_!INFe`%o zf`>~px--Xcp_Y}h$Gpua2Xk47)BZWJp<)oDWAP>?z+Q*7d;>D|7dSlNho>wn56^QR zp2jCRiR?Q^!^cN+%oP|<#HtNbOfaOiM)ScR_ufoCDs*aqRJ7WB{yYM6yBX!JIf& zx${ql%@*9^j_(R=)#(r6oHWB_oeRkI>VN0wGkPdS?fLLI9lubA8{IMJx6t>#ld8e?H!&_6w`O5=e;3-2G^rtTRHR9Kyf_en`V|0l8Y zK7aK@fv-gA_ic}8pw{{VANN6zUrb@1EVqmf-ef?0H@Yp#e!a^Nq2N*ruv)<Is`PS?7V0_2LN2@NNoGGI93?mj%|^(kV??dGLG{rn=&x}=f<1) z6(h{l#t>JbmDwWPC&+e=RWos(0=_j{9l{=~o!lM)Z_eLbGAMnNhGd(emcJ6*THE{E zuPH1||7p|4Qw|&Bq8fTQS5sVN5=D;H-bOi~y67Y}evCV58Mm2+HV%8HI%RC;x)<5G zXDzXv;gSYDy`u8EE6lhc(=M<8c#QpM{A}7TtEpB~2UbWus&am#`=;DJ#c^f_s=4Ue zlUB>;uaK>`p;Zyb(cEgTSxM}fve)P@xrPvNh}v~#(>;&s`GMLJZmH1yu*Sve@ABH) z#FU2zV>o_ypA@uv0>s1b{DT_+sFd)}t7cKYFWZin#2=lP*2f}_f}|gvUZsr6LAGyP zxRiDR#|nDbAIk|B+thqbLrjh7Me9c7nd~Od@=3>Tp9ak;$+`KEM9zygGew?)wC%8< zrkFrKV;2dOI^O=pj%wix8ez$^+2N-$6!*2=((+M7mV6r59sIWvEXjz^#VRk-FFp$3 z2R;0l#)&L1deM6SRJp`==MKe)B=*Vh(O z|HjjF33MZdrcKw%xjgk@Y5d10Y`MeDvZBya=MVe@E#7;yyWNg9M&QtKFaPGf%}PuM zfl^}6P(IwPu5he^h{^S;KS}!K1Jx`wP2{mKX1T!cM0Cwc>9&f@Uq{HBPy)jp~_l|J5#k8|i$6R)b1QWN5>W)*G5hDSeDb5-Wx->n@#rt-s4 zzYdQ=w^iq&{<*BAdL#-`a%*4v*`1jscF-`}eqe9{cq8F+GUd zy?MDKpe^Zvs{PTMT$e?g0qUW8KJZAUR|L~jwfi7YVQecmQM`R^dGQX{#?=JoT1&sFj7~#$~kyTW+kN_Svy6nZ92zXlnNA!ocQzLRZ59 zl)k@P36Dxjuip}GfFF!gcQYHk@M{Tf#2oRB8K|Tnd{?b6=6&UUm~i^Jf_ksHu5VeL zunkQ8CN!GU1WIoyDpjyy9>|D<4oo6d$M&vgDkA0fFybZmPk)?^Yr!aPca3P)Y?ofX z)DVe`h}=4{8WJbcPh_gQ^XNf1=FEV(rR9d3rcPR2;AMU7js0_tp()hGwk2WV{)}U7 z-Ae(cNf4V+5t`HeS{KRfA(WybXdy07P%DdeYx5q47xL}2dgQ~V;Zov{LLliFCLm9c~~ z+z3_fMoMR$2fX&tLAkF#h4jq@9=e5ynZcDP1p4C_naqA?Pbay!DA1|99cCUb)6>v> z^2lIK31dICNUBxjcu07xz-&{x#{sU9t17)N+Cfy$$v45snOjt;L zY~(21?!uHDjv}O5W4x%jSK1CfkDJL*+*&O}n`pjRs=llIY|6E8%1jwv+HZVy}vll1~#9 zUsUpb3oaBGu^#BPeV(PClUlO7q#L*xa^Sh45BI~LXHlrPqoEsDQ)IY95#%?+api#z zMXAnU)REg=(j^vX{T>b+E=###*N3jHAunT7F)*^{fIOFXuDD%f%te7!{T_`>+oN2f zEH-SU!53@LYm9j+nA)B*?Zd^~J&ujrujwFV!sgO#vQonGAjxTc2=}I)F)Id!mzyC> zA((uF85|REj{^UyD%z#lX5Da$0`o~8QqK#mMlKrdrR)C-d{ShbrfSX0uA0FRg}xm3 z(dji@Q$0TS^Gu*yqV>DWeTd$HRWNDc1bd{de2z>;Jz{STv)q#M`r~%&7U9fp)7}%k z>AVcY!(B!H%Y>DF1?XC*UuG?Wytz8Z&8-)EEB5w=Mq=c4xW;mzU5cOSZM@WMq`ui1 zk!e#XT~2pj&u+B~bGVrIdxyErBd}cVin(4rs)vcvQHgMLcqA!_2w*ga{ zrS#$Zuh*Gu?_c*j(EB}+;vIgW5G8Iz@(yIUw~pg5aUd)xVBI*0DPE2{2C{=x$zM3HBLltL6uGosuO@ zF=szQdM?pMRxYymF=Lt-u3D!`OyX^6KA$D%4bngM=O~@&eQYLJw%YNg!iHjXr3GrE zceB(=LI3iv%>@|0t&9Df^*gfEFFT`b=;?+ho-1ABW-!-xebcE8NpdcJxEY=- zabPH`^TDT!QQKRj8^P)NXKDl7b_XMrlo;95QWm2O8A$DZ&x?{YD9=8QjjE)SGhn%c z6HyVrzTM@gnuB^K>p>r^z{Y-oP0+E!1KMD!83qI0zPx8fV9;XB<@^@2u7n<_S7pH2 zRCK`{U>;87)x1VTvQED*rtrtW{71Ghzn2k73Lk36R9xs|{sI*A3mccl{oWAl&5ndK zHN{|Zf5eQj-$~B2E^vcNPW;w_#89eP;LZe+v3YuW0oJ0hzs5zM?bKF^2@MrauYXwP zeY!d?6zY3gzU0GneFG_O>eymY-jIHis2L;h{xWv53z0$F z?wp(6=c!W2#=`>$P*=@^*!|2HB%4#K0GsYJ+HO7FltY*9>R9wk0;V}gEICuWhmN`q zxwRxA1o2*RD@*EYf-PQV>CX`_IoL82KHGF!@r|%)oonX7iua68`J_Bpeg6U_=6wl&PSLhVRLS@TY_H6dtYVzEow&UQ+aoSU^eY7B znbq#=Y@TTy7|w%?tJZC2>Sw$V^p?@5`3O6ZeLnT~onSy_7mQ~@;dSq29(515N*u7I zUfhXHe_4TDedPX7-fKh;{~#YZ+UtQ%RB-id1k^VRC&Ox*B>g+0PE6y{Q@jXL7Z2cT??21D{3n8V5 zKal$Kqmoj>OY5G-<7k-@$0}0-K5_EKRyz6j*RC|EH1Gu8$UL`%%k(|i6M|M!w`hj+ z%Rmh;!03Y&3N8k^;nz_$%XORYLR^pm`yJFIZ_KSN?zKJwMGLzUDA92z1|!k&HH_}|~g2~Y9hdugKy_p<5vDDzLX z2A{}+ZgSvgdeco8 zXGdbQ&9?R~pyvs^ti;v~SDTgP!e(6xoKyxb1y>unXp7hCf6>lqhLC5c0O^QTVG8;n z4SvqJlo9N!JoD4AWC{(B?2#npWdLjKU8rTTB_fY?Ck0k7ZB}SPk|mS$nq}_bRkVQSSwX zSPP?b>>uZ3!`8m)03xB*g$~})5H0y{{Eh$Y$(n@3+DvF!z6r+9B}KH&-aa`NmXrYD zBJki^q#o5qvwT=w+o2JUhN$5+?2~EO`HxDB8)v)6ukUZK8dkXj=jr7q2Wzine-!B` z2GIMfhW$`6JeoVGz!5)iUv13k+>cc35urSj3j)u}Hm|!pFkBrKw|7GJ_Zzs{W>=Bc z-aXNhpky^m3TRz@{;R-dxa$b$_2S|hCC}3QOw1?NLjDHWyQ?NV`C3|6d3n%!QDZGg z#MYew$c>-(B@s!I!s_;R)N=)x(Qb8rj#0}3l6h@>i7s)ns7-wUZ`gQvf~I=|dtw&m z5#gU$f2dT#oX-{)jl8hV8@F4&xTju{^N~}iBtZ0Eg}vowz|WZ#iK3GvBkTsN8s7MN zYkeV9Nv&Tt@p;)q=pAb<(YluIc{hPE0}9TizA2^- ztQY!~L)B-&(MeccnL^3{E+J%VS~A(u#{GR-s9pL;3|`YRVD5vH-YuI8lD!qXALrUV z{vBLE1gCT0Dd;G;K( znwXNvx~<=<=*t-&Z_FA*e3q&Eh5q-O9Pag|SxrZUL8T6*aR+oFR|6Sg8@cvi4tgAq zYnz4s5y`LX3>K(VtRl94PX}Ulw@F^rMjM*#pYxxI@+Xm>H>g8GSr(auf%TnTb7hp`|rB>`mWt~?KvhAG%-$i%=Vc`a}yjqsI;W%6W$($0UFfWsVFiK_Xs z0X{XsHvzS;`8?IS$j=}|0c>Ew!6L@Y|6o3*n(HG80hesduqq!OG4*zv{INdjLza{q zQLbt7NRmhM#*1jdu5Mfdffiyte!%gWncLj7(e+WK2NQIfRE@gAZtLs_B4mTUuzhg; ziIw8Pw2-W^YGh(3*0~JN!%}N;FVsowW%99-7$)c`}M7T@XKv0iPe2b&y<=# zqjbNfYi~y5z+C#FxN&mmtvrV@;3xd`ST(`#j#=s968g2KbFdiEkf{y}pcAh*_d=O5 zu)UosGn0uxaYVsEQS+ucRX0ep)5a&-?tH!*pubqyQTSY+fK%5st|V7Q*uiRZ37{OIikJkh2G7bWzJOQ&Z-LAU!1FdSz`|}H4-NvhA5N|M(16!h$qAXO z;JM^1!9}((U_1XeQRKtjcF!@#ihLK|pTJjizIVctrY1@?=PF4#yI^HRd4}mp;VMZ^ zEXJ*rri{c0iT|u@n$#$koxLVum`>vmP2uiw&?wgf20P*~KooascwpOEeuxYt3f+*M zl})-|olOB>SmKUT--brY$S5Dm?St{}ntQN@+&*KkpLQYFT1a2N`BaVmm;?e)f0ytgu+aEM<$UXnTJ97jd zqq2)=Zm5yk$%#s_JCS2V_LtLq8W$ExyL1I8K^-ICurcPURcef1*{{FKxRdSVhcm^R zGUgVk-uE>J_Vp~i3tb9;Gk03=Iif8o&@AQ~rd4FASm6cmoFbf`LXYU%RZr-%+T z(}6fMrQDBHr8fnn3^P0L!l^$OG&AxY%j{R(@Aa+gHZPCM0(YM}P>-KQRT`5h^8T~8 ztWRrgtZtvJ(ktjZ1bNpdlUITA=!owpiuVp>$zhVSBv5R7fLH7Mky+Hqoe2H{03M;` zL>bs9I`z$K)#q7bPZ!zy3*Q zh)ojB{F0`T2WxaHdIn0@LC^;9Y|hj0LoEVO6J7ZboA6bVF}lfrv8SOXqw$XvIo_au zTcgg?%G)0pSXyh4^C02OXaU9~ka#Hdxdt_vMkT;E?@jyuvrWoI6(4M^)e4j}c`vnQ z{-g6j=(&J6qTexT#$0`{(7r$hhH`zAE6Wf7)AIb0``x{AN;}I-#_(&KT_OR-VbCpq z?h}iixF!8#fJXE}dvY-S-(zA0cGIC-N2jTq{XKdJcb+W&%p4c^*Zq=RGtMMhpw2T7 zV3p3^h~+%UMz8lXXUIQ&Fq{Nv1YCjMF(;)I0cGx}@nP(SNm61MzTJv6^(D#a3$yg+ z3zWd~x&)BB`c!qjsy`eV>ZySNm^9L#+*J+%Mg=WMat?SLlE!joK);dgZ#1K$-!^dy zAUC_2GaA*Eb{XEJJZ3R!U{>lbl& z>j%5sF)41Mx7eaB#E2ch?B_7Npx2$ToJfm$(Ln7^(!1};>slys6xA+a+uCo>;Mma$$dJK;+(eCI9Z)F5j+jB+WFU?}D!>ji!E zGEBsq+8dN@7^>m%u~_N4RdXYiB$~HEz-uiQBqOpzvRhqBX0WA_Fz|(SZTAL&qo!JH zjW46@p}C0W1yBm__@-?Q7Kzt2fLP{y6H@Dsy|{Fik^J zo@FX)=e03$k)Nfl^ogKO*we}9<~18WQA(k0M+uQgOQKY)2g8BhSr<=H8Jll3Z%RK3 z5)8)>#jPrM_NYE#?>{|T+kQ6gd_1!gfYv}{NNwrV&}N*G=wbF}CFR(kYMWd1$jhUT zp92Zw;kl<-o4rMD_>o@ryvaK^Lw{=bKlJ2&-E2*s3s+~2Ht20T z0HgcICII@@z#1snuEGO6V#F=WzP(#sH^%rtVp??v1FCft&Wj(V7# z&(#lgtWx}zyI5cB(2nMw+c$hZuW&J7y6p2%0WP4df}o?8K7p_~!x=KPeGe~RHe8J< z-4ASBb2a*#I(rNx_!?RSN&e9yAM=8RpbkeQiZ8ezEFMU!<14YT z%UM0ml1Q#xQc;w-sh$E)u5EhfUd1bVev46ZmRF(T@HTD6qCP!5|3%~e^q2x$WP4M= zsVZ>-;8yC(Q&NgmQi6u43Jn`9OS`h8!5YaUc9h19p=DeDd^6+on?-+tUKdBEQj@h} zFJ?X>|NO+B2qEXeEWCW+OXc4bT)TjxdP)0%IK@wFP)!J7guM__B0Ots>c-%p5d2zGtenKJi_OROY zt(KBZc&N2M3_W%&ctihHU?I;}?=7EuGwKk9{EZR|bzuUK@w$ue6lbR^f&|kI1Vsk- zN0g6fPlIIc7h%4R$O?V_p6u)a9(4i$NyJ5?^4%M8nV>8nr=!0FaFXNZM!Kt2zwyU_ zEF>pUAh#f?(`Q2B?C#;CN2u&j!UIWF5Lkr8RSI*k94*O!c^0ZV#*DI3TwC{Gm#qj9cf` zT`PQJ)|i|v|I!Yhe;pYJ+a1LDfCCvFaxtiFYY4z~0S^l7J1M?;&GdjiqQS)#z^2kJ zZqIZ;P*P5FyGddj%eefWSliPm!VP^ANhPPA#V)2x}Um}n)#1q zGgx!5JG&E8%;ih#RZr6MA#;WEU5ydoU_#h0fgNX&-ux##wt9S1J6!F-t@~~0?;+J0r&Z_UjsV1Yt!bNbW{xRj=CA4l!k+$&AEN^y za)&l%<|G!cy%cYA>Pl8hBaJ)8FN)L8*S=ArbBs#T4xuP%L$Nl1sA5h(q{wSQQtOTifz;KKmAY<^7=7h67fZ|E zu~v06>K&x5E?fa0jJ)jtJ8QUT=%tC)FqALw$_+Ax#th4_;`|W5 zlVGl-OAZ28|D6|G=nu^H_gi~Z{|q0uC+;V!aVJ>rAl##;!H_^KKxYj}^cT&4`9tKm zns(#Rt=EqJYix~4ojfQwn4rs2&}%v46_El&F7;K+J`P7?dbDS|3s_p8jb8v~DX%V7 zJtA0Q5_CtANM+3LUG*e)$7@<@jdMPD^9vA*rZlN) zAq%l2xw~oo8IM=ls^ZDF_Sopn63dpxFz2vM_YD$}Jhw zR^aE}vDRuQG;fS{pML%RP*u_QCsw!vf|$b9Kn2(k1|B~!y&v;ldK$2mla|aJaHHah zc`6wCmgUM?Ott!%wInubYUp4TUm>w8`-1WM(`{c3M`n)v{!_emDOv3UZ}&voJmw>9 zR&iC@JuQT=?oiarh$`0TW00yX$MA8V>GsQyD4Y(!|;{1LHaASzUq5Cp@tOO&#Hh z$3U-(7$4Yx8$5?DS7Le~i>f|_sI_Rj`b6}q=BmDEzdPvdr3O8?^B)PqHJn0wk;ENH z`|4W4TB!V1)(+vyd3Z!*p&b0F1J`B^V>u^Uac8i)f!wyHC+U9WXk@rGao>?X^gJ0VAd$(a|r_1rxQ&IhV9)0`KhPE?N%O{ z6q=yf9Plr*@Kq!~SbBjRRq%MpaQ-{$6RjvZxur2CvE300)y73 zumH+VmC?&YU@>x-)(Ht$>;5gZg<@kldK632*>mQ<92IO@l{^~M)&eEJvF0<2T$?Ye z$a1R(*z)Vn=uErZMCdV7WkEr(vzPjsBNzGST|8j2s`d9!qJ#1JYNK6la$kJ~*SZc@ z2MV)$LtSdk7Ki#J*1q=O&S%<%$aL1I!IzcV_=Tt{U^2p1`216>z1gjRd}iLLmL=99 zHD(-P<;x+rZBs^+HYVgI=uu_IQXSdhFMql-1gI>6JH!9o)j&@V%uU zf?9ud>fBPN^-<76MS}uB(s&(J7$^t`U_WIIgAHc#pU*yX+~)#-%jtLjSdjlZk?*7b z?E9}L^#8~k|Ns8tAZg|TF0pKguX`4I_oW_gT3heIpA3hI=#qgVIc7!3>MzxKz|>O;3P7& z2C}vup30)pH!MF-$(Z7VxV`&VR-o_b;b%By-3RGErGT#LtXEvMyD=`*dTbU=eHbM!>G^3bF zMq{>}#_imcbY(*zU};yQL)|=IW>GI&WhJp#bG5s{F6gdxo?+rGS<0C{TQKNnr&noo zX6Ua|VA&K4BWULO$XT@B;%uu9u>KfjD;uahk$M3pU57=3G^)d6lV_un3)*|N@b z=I|ADw%}c5*Yh7FVT}_Ae|CfCJb?Lx^{-|j?}w+9BNqyyHY5t@b|@e|UGr}~{x@Vh zc_!cp=#>cy9Z%?z6|6FI)?*SfOk9Lcir~Y7BfI`@CjL_IH3L~Mpx>$cP%6$^e|+dx zN11SIwT8=bwGVZ}8iWBO`$a+u{+u@O+3*Kkn={iff!jb<{Uk6Vp3nx9AQ_>`>NEoK*K)IW-I{Nw>{tFuS9$=Gt6>Uqp*UZ0R z!8!V#YHBz0i$5=Qi%sNCM@TCQYJHK>Ew48haaOIatHbdM_8fp$e#}i~|k#9AuOMId=ZbCh4Ht~I7{(-#y ziQ{G>gK8cDewlW|?iO6lT+&*t1C~th>~eEmjXw=APDBGAC#t=CRFVAitNW!IITXNV zU%u=H?v_84Sp5;ubrjB(82wQ_fSU2mxLM&+>mJ}YR?VEjA9@-RDb8+C>Too^K9NfV zR~cfgP?CNbHkkcUBJd2nHWP>ryiX-n^o4Zd2|73=1faq?a_O77v8PF~QVC-~50k}Q zUq;!JVRg?lT|*=J1U7j^K=)=ISp|n3HXB7_;z{q40;O|Hu7hUpn|DH_wZbJc3^gD> z489c;(G;K*;bsMPk8r$gl)5ih%q1j)ShfXIUWRT|IxGWBSj_w|)BQT?^^XH-1NrmP zEHQErP9HLm^|0h%Itv1M2v%YBdl1vC+LsyV;@9S#zEiJrjOu2#W2$xcM4zTW(%CL1 zzkhNZWN~GM!p04E_tQx?l497lcXW85P;=t(J3Z-FiMuTd+0~K$Q>aJs#giJ! z^vj6rFGelROhP}z7(<^iBf0v>Ex2PYNE+GIp$pmwxfVr1VFc;DPaxCx9C#i#o(cm7@yY)B8 z>S%CN#DQ;_U~0-*#^vTm4-j|yd}9Ss`k$l5(?9z^H%ZlqK=nGtKI7Q@U{g@U)!tM= zw1BsVBp!l4H3_Y?TECA!CLr;mL+J>SG-&PQnfYPyJXm`gWb+Q5BvzzNZ0NA{-rd8q zD7YM%y>)>=Nf{ADB`OR2b~Kn`iEDW}eLU}Bida>w{k|MLw3lKMmu}* z;Kjg{pfZji^b|?ynB{1Cn;@Gm{MmA?rt7sQN!AS#&I)OS=gR@VzVl}@9*6_Nrs*nS z$|^GIQp6Q7rVR~T(u|TU;W>JvA|sx_)>6Pe=aQ$9p#Jc%SGLc)yt~g>!!gyW=hl&* z_bx6|l05az2JEM>Y%v~IMmGD@=)?9AB5x6e96pj(Zy;L{NI9W$X5Mx?FjF;RoTSW< zKL6>ugWMn%%A1+{u`tW+=Or~!xwvjH!oc`Y$y4`@OwJPe>@5JDO17xCYZNR2ZUK+J z5E^wcf$8#KRbg9ia+>#qy;C9Kf(+p^dx5Brg2&{@`>)RjonDTxcvWnCE*k2icbKOqIPlS!i z88f?3>u^u{=v$LdfF$^CpxM?X%-uHhrBBeMj2e*Z#YNKs_}4a_cF%%i#1n6#pVZ#t zy(oJ*YZ8E!f=`=R4$RN(9?Q@yDA`X??tk(Q0+cSj$4!T(>DEAM?AT3NRiNJSJ^TZh z*&hjRbpCXITFJ^ZFM8+=0(1|XdVKy4n(Jm6K2@BP?& zIq%EWk+vIb!EFFAT35<^-!>m;T7!v!O=sTW0{4J(vnILATETrFkm#N) ztlw7~CIf&iJ~cPHbE+~eMoO32Tkl==XNQ}*JCtf}o_VomU;YaJ{6f)=KF~&>uv`=r z@b!j;Eyu@HqPA8)Ax?dacpQ|>YlaeGcj*$rI6qU@7rIlp_><5R`Fs(T(Wg~?eaImn z`$5}lt7ZPu5uh3fSuI)G-@l4fE=v9{S}XG!_a!!%lf&_32_Zj%pQM!3n4|$s!Y9#1 z6=?sU;)rYM8JTh(DoRlG`y0OQ7QrbkDZg35#QS9Xc&JuJnE%B75$F)b&f_4|$k9=X zM_a0Of*iH2?&Pb|V;!Z!T>k8N05(egD>-@)Xj^`1U92IZYFzB-Y3yDE_{t>WMCS^z z;St5ysK>d^khAiAnhdhgCB*Ely*Xz;#h-D;>wjU@wSu){57k>ZkHRhyKx}>6dnXR>3{ft0UFH%CO%wL_zIp18|g@|`29$^XTA0!noF7~w9oJh zJwL0gWcb^E{LhxRj z>czdF9h}?zD@5a07YPaL>ud#9Kra3}zsYN4OSnCpk|9>)0(1r`?9y2kxRoFx0?%(H zpafPfeL`{*^zc&GW8($U!2BoyX+u}gQBE-bOr_X*JwJDl;o|l8LY2CPh1-{G`CX{@ z$(4_lZar7}=JS0>tF9)351(nKu4xNV^^4bfFmZ?4n%*v(P)NU$GfVbYF3>;KB>D!d zLJ7Dq8x`O_pv7}p+l4~76Zs6F6uwlR=!#_+APU~V=^$+pcFKNr*K#WChg&Qko(VTk zzvM65J+q>jE#8^^vaP?bW91^hwbY2g3ymv%Y?Ip05eR(02HTXNqq*# zbwse9@0j3v$&JqXXYeaY+qi(#Ua?O@rPi=pP6Z?`-NIRRCqc;v*#Wivl_o%x;`Czg zwcZz%K-1n+Kjk9DZ?nO5>8p&HThY~QmyMzAE;YB!xZfvFk8gds{#S9>!iE%(cF-^E zd{H_K)ff;O1$qqGmm0`x*GxlNEJY7yB9y2OOil+Bzs03bGa1eWB=UmOw?`Dk2{{F1 zR!C0v7%`2*roiuStYEzv=xwlh5hMG)h;Qxe>-k`@1m=0^;{rh7=&s;+!}|}glc<6x zskCRvyRvxL!>5M{)x;-j#V~{F*$gj?oyGyrqxe5~OPJ-;hMK9WK~~EIkj&}+m$dW9 z4rhumbcbj;rV$ex?h|I0+kOFw)YwzrG!@nZqahfJS!%FdZc25eSP2mDiOyV*VB|NH z*=(HLjr<%i8+b3bK)X+Z57yOpy%uDPaQCD zW=h^P0VzcZD`eb-!G)150$T}x`FYWDKyR4`{;k6x)~x+aJ92AYTYL9Ua9ey+)_$qYX>KfsW2UAqiKqKYu%%Oe+%K)9-OK7568tyR?>coLz0 zs-m{m*J#N6#mUJ7^w%0d0hzsJFk8$>eiHo&*mxTxV{jOr1fjY#y=lpSDg=^#qcTPm zn2fUeFa>OZ^vkg}|E=SH@<^>G)+**520hGir?xFxrpYgbLV*hdgpTLeh#UXg#FX$d z@tRpG3vcSXKLSh^tya(B;c)a~{r}ky(BUf^TsF(@xBnDW98vjkD{$n^<)DduD`*AN zC!5;=z@4$%*+Sly@QLjN4$v^jSg!w=e&o8|gzK{;K+A9rEIe5Y9Nz(s@afLDV4t88 zdn&fJM|0Lq{^qnO-NgTe~DWM4fa;%Zh literal 0 HcmV?d00001 diff --git a/bsp/nxp/imx/imx91/README.md b/bsp/nxp/imx/imx91/README.md new file mode 100644 index 00000000000..7a89cc674e6 --- /dev/null +++ b/bsp/nxp/imx/imx91/README.md @@ -0,0 +1,233 @@ +# FRDM-IMX91 板级支持包 使用说明 + +本目录包含NXP FRDM-IMX91 开发板的板级支持包代码。 + +## 1. 简介 + +### 1.1 i.MX91系列处理器简介 + +i.MX 91系列采用了可扩展的Arm® Cortex®-A55内核，其主频高达1.4GHz，支持新一代LPDDR4内存以延长平台寿命，支持双千兆以太网和双USB端口，以及面向医疗、工业和消费物联网市场细分领域的丰富外设。 + + + +### 1.2 FRDM-i.MX91开发板简介 + +FRDM i.MX 91开发板是一款低成本、紧凑型开发板，采用i.MX 91应用处理器。该板配备板载IW610模块，集成了恩智浦的三频解决方案，支持Wi-Fi 6、BLE 5.4和802.15.4，适用于开发现代工业和物联网应用。该开发板包含LPDDR4、用于快速启动的eMMC存储、PMIC以及扩展功能。 + +FRDM i.MX 91开发板是一款入门级紧凑型开发板，采用i.MX 91应用处理器。 + +![GS-FRDM-IMX91-IMG1](README.assets/GS-FRDM-IMX91-IMG1.webp) + +开发板主要硬件资源： + +| 资源 | 简介 | +| ------------------ | ------------------------------------------------------------ | +| 处理器 | ◆ i.MX 91应用处理器
◆ Cortex-A55@1.4G
◆ EdgeLock®安全区域 | +| 存储器 | ◆ 1GB LPDDR4
◆ 8GB eMMC5.1
◆ MicroSD插槽
◆ EEPROM | +| 显示器和摄像头接口 | ◆ 并行RGB LCD接口(40引脚扩展接口)
◆ 并行摄像头接口(40引脚扩展接口) | +| 无线 | ◆ u-blox MAYA-W476-00B三频Wi-Fi 6/BLE 5.4/802.15.4模块 | +| 音频 | ◆ 3.5mm耳机插孔 | +| 连接 | ◆ USB2.0 Type-C连接器
◆ USB2.0 type A连接器
◆ 两个GbE RJ45
◆ CAN(HDR)
◆ 40引脚(2x20)
◆ 扩展接口
◆ I²C HDR
◆ ADC HDR | +| 调试 | ◆ SWD连接器
◆ 通过USB Type C的UART | + + + +### 1.3 开发板和PC之间的连接 + +在FRDM i.MX 91开发板上调测RT-Thread的过程中，需要使用到的接口有： + +1. POWER（P1），USB供电接口，用于向开发板供电； +2. DEBUG（P16），带有USB转串口芯片，用于U-Boot和RT-Thread日志输出、命令行交互； +3. ENET1（P4）或者ENET2（P3），以太网口，用于网络下载编译生成的RT-Thread固件； + + + +## 2. 编译 + +### 2.1 下载AArch64工具链 + +从ARM开发者网站下载AArch64裸机工具链， + +下载页面： [Arm GNU Toolchain Downloads – Arm Developer](https://developer.arm.com/downloads/-/arm-gnu-toolchain-downloads) + +例如，64位Windows主机上下载： https://developer.arm.com/-/media/Files/downloads/gnu/14.3.rel1/binrel/arm-gnu-toolchain-14.3.rel1-mingw-w64-x86_64-aarch64-none-elf.zip + +例如，下载后解压到本地路径：`D:\ARM\arm-gnu-toolchain-14.3.rel1-mingw-w64-x86_64-aarch64-none-elf` + + + +### 2.2 下载RT-Thread Env工具 + +下载页面：[rt-thread.org/download.html#download-rt-thread-env-tool](https://www.rt-thread.org/download.html#download-rt-thread-env-tool) + + + +### 2.3 下载RT-Thread源代码 + +在Env环境中，使用git命令下载RT-Thread源代码，例如： + +```sh +git clone https://github.com/RT-Thread/rt-thread.git +``` + + + +### 2.4 编译FRDM-i.MX 91目标 + +在Env环境中，转到`i.MX 91`的BSP目录： + +```sh +cd bsp/nxp/imx/imx91/ +``` + +然后，设置工具链路径（Windows Env环境）： + +```bat +set RTT_EXEC_PATH=D:\ARM\arm-gnu-toolchain-14.3.rel1-mingw-w64-x86_64-aarch64-none-elf\bin +``` + +或者（bash）： + +```sh'' +export RTT_EXEC_PATH=/path/to/aarch64-none-elf/bin +``` + +接着，执行`scons`命令开始编译： + +```sh +scons -j 8 +``` + + + +## 3.下载 + +开发板默认固件带有U-Boot启动加载器，开机3秒内通过串口发送换行符，可以进入U-Boot命令行界面。 + +### 3.1 准备U-Boot网络环境 + +将开发板和PC连接到同一个路由器。 + +例如，PC的IP地址为：`192.168.0.101` + +在开发板的U-Boot命令行界面内，设置FRDM-i.MX为静态IP： + +```sh +setenv ipaddr 192.168.0.120 +``` + +或者从路由器动态获取IP： + +```sh +dhcp +``` + +成功后，可以使用ping命令测试是否可以访问PC： + +```sh +ping 192.168.0.101 +``` + +成功则表示网络环境正常，可以执行后续步骤。 + + + +### 3.2 安装TFTP服务 + +Windows系统可以使用Tftpd，下载链接： [Releases · PJO2/tftpd64](https://github.com/PJO2/tftpd64/releases/) + +例如，下载portable免安装版本： https://github.com/PJO2/tftpd64/releases/download/v4.74/tftpd64_portable_v4.74.zip + +启动后，设置TFTP工作目录： + +![image-20251210021421740](README.assets/image-20251210021421740.png) + + + +### 3.3 拷贝rtthread.bin到TFTP工作目录 + +在PC的Env环境中，将 `rtthread.bin` 拷贝到TFTP工作目录： +```bat +copy /Y rtthread.bin D:\PortableSoftwareApps\tftpd64_portable_v4.74\work\ +``` + +或者： + +```sh +cp rtthread.bin /path/to/tftp_work_dir/ +``` + + + +### 3.4 下载rtthread.bin到开发板内存中 + +在开发板的U-Boot命令行界面中，首先执行如下命令，设置TFTP服务地址（PC的IP地址）： + +```sh +setenv serverip 192.168.0.101 +``` + +然后，继续在开发板的U-Boot命令行界面中，执行如下命令，将`rtthread.bin`下载到内存中： + +```sh +tftp 0x80000000 rtthread.bin +``` + +下载的目标内存地址为：`0x80000000`； + + + +## 4. 运行 + +### 4.1 通过U-Boot的tftp命令下载、运行rtthread.bin + +完成前述步骤后，在开发板的 U-Boot 命令行界面中，继续执行以下命令，以跳转至 `0x80000000` 地址并执行代码： + +```sh +dcache flush +icache flush +go 0x80000000 +``` + +每次开发板上电启动后，均需执行上述 U-Boot 命令，RT-Thread 方可正常运行。这在需要反复调试时显得不够便捷。 + +为此，可将以上命令写入 U-Boot 的环境变量 `bootcmd` 中，从而实现开机自动执行，便于后续调试。具体操作命令如下： + +```sh +setenv ipaddr 192.168.0.120 +setenv serverip 192.168.0.101 +setenv bootcmd "tftp 0x80000000 rtthread.bin; dcache flush; icache flush; go 0x80000000" +saveenv +reset +``` + +其中，`saveenv` 命令用于保存环境变量的值，确保重启后依然生效；最后的 `reset` 为重启命令。 + +执行效果如下图所示： + +![image-20251210220620728](README.assets/image-20251210220620728.png) + +### 4.2 通过U-Boot的fatload命令下载、运行rtthread.bin + +另外，也可以先将PC上编译生产的`rtthread.bin`文件拷贝到MicroSD卡中，再将MicroSD弹出后插到开发板上，然后通过U-Boot的`fatload`命令将MicroSD卡中的文件加载内存，再执行跳转： + +```sh +fatload mmc 1:1 0x80000000 rtthread.bin; dcache flush ; icache flush; go 0x80000000 +``` + +相应的也可以保存到`bootcmd`变量中： + +```sh +setenv bootcmd "fatload mmc 1:1 0x80000000 rtthread.bin; dcache flush ; icache flush; go 0x80000000" +``` + + + +## 5. 参考链接 + +1. 维护人: [xusiwei](https://github.com/xusiwei) +2. AArch64工具链下载页面： [Arm GNU Toolchain Downloads – Arm Developer](https://developer.arm.com/downloads/-/arm-gnu-toolchain-downloads) +3. Tftp64下载页面：https://github.com/PJO2/tftpd64/releases +4. FRDM-i.MX91开发板介绍：[FRDM i.MX 91 Development Board | NXP 半导体](https://www.nxp.com.cn/design/design-center/development-boards-and-designs/FRDM-IMX91) +5. i.MX91处理器介绍： [i.MX 91 Applications Processors Family | NXP 半导体](https://www.nxp.com.cn/products/i.MX91) + diff --git a/bsp/rockchip/rk3568/SConscript b/bsp/nxp/imx/imx91/SConscript similarity index 100% rename from bsp/rockchip/rk3568/SConscript rename to bsp/nxp/imx/imx91/SConscript diff --git a/bsp/nxp/imx/imx91/SConstruct b/bsp/nxp/imx/imx91/SConstruct new file mode 100644 index 00000000000..456429c826a --- /dev/null +++ b/bsp/nxp/imx/imx91/SConstruct @@ -0,0 +1,33 @@ +import os +import sys +import rtconfig + +if os.getenv('RTT_ROOT'): + RTT_ROOT = os.getenv('RTT_ROOT') +else: + RTT_ROOT = os.path.join(os.getcwd(), '..', '..', '..', '..') + +sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')] +from building import * + +TARGET = 'rtthread.' + rtconfig.TARGET_EXT + +DefaultEnvironment(tools=[]) +env = Environment(tools = ['mingw'], + AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS, + CC = rtconfig.CC, CFLAGS = rtconfig.CFLAGS, + CXX= rtconfig.CXX, CXXFLAGS = rtconfig.CFLAGS, + AR = rtconfig.AR, ARFLAGS = '-rc', + LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS) +env.PrependENVPath('PATH', rtconfig.EXEC_PATH) +env['ASCOM'] = env['ASPPCOM'] +env['LINKCOM'] = '$LINK -o $TARGET $LINKFLAGS $__RPATH $SOURCES $_LIBDIRFLAGS -Wl,--start-group $_LIBFLAGS -Wl,--end-group' + +Export('RTT_ROOT') +Export('rtconfig') + +# prepare building environment +objs = PrepareBuilding(env, RTT_ROOT) + +# make a building +DoBuilding(TARGET, objs) diff --git a/bsp/rockchip/rk3568/applications/SConscript b/bsp/nxp/imx/imx91/applications/SConscript similarity index 100% rename from bsp/rockchip/rk3568/applications/SConscript rename to bsp/nxp/imx/imx91/applications/SConscript diff --git a/bsp/rockchip/rk3568/applications/main.c b/bsp/nxp/imx/imx91/applications/main.c similarity index 100% rename from bsp/rockchip/rk3568/applications/main.c rename to bsp/nxp/imx/imx91/applications/main.c diff --git a/bsp/nxp/imx/imx91/drivers/Kconfig b/bsp/nxp/imx/imx91/drivers/Kconfig new file mode 100644 index 00000000000..3ca01326427 --- /dev/null +++ b/bsp/nxp/imx/imx91/drivers/Kconfig @@ -0,0 +1,23 @@ +menu "Hardware Drivers Config" + +config BSP_USING_EARLY_CONSOLE + bool "Enable early console" + default n + +config BSP_USING_UART1 + bool "Enable UART1" + default y + +config BSP_USING_GIC + bool "Enalbe GIC" + default y + +config BSP_USING_GICV3 + bool "Enable GICv3" + default y + +config KERNEL_ASPACE_START + hex "Kernel aspace start address" + default 0x1000000 + +endmenu \ No newline at end of file diff --git a/bsp/nxp/imx/imx91/drivers/SConscript b/bsp/nxp/imx/imx91/drivers/SConscript new file mode 100644 index 00000000000..356b6faf24d --- /dev/null +++ b/bsp/nxp/imx/imx91/drivers/SConscript @@ -0,0 +1,15 @@ +from building import * + +cwd = GetCurrentDir() +src = Glob('*.c') + +CPPPATH = [cwd] + +objs = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH) + +for item in os.listdir(cwd): + sconsfile = os.path.join(item, 'SConscript') + if os.path.isfile(os.path.join(cwd, sconsfile)): + objs += SConscript(sconsfile) + +Return('objs') diff --git a/bsp/nxp/imx/imx91/drivers/board.c b/bsp/nxp/imx/imx91/drivers/board.c new file mode 100644 index 00000000000..0fcea165f62 --- /dev/null +++ b/bsp/nxp/imx/imx91/drivers/board.c @@ -0,0 +1,83 @@ +/* + * Copyright (c) 2006-2025, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2025-08-10 Siwei Xu Add i.MX91 SDK + * 2025-09-15 Siwei Xu Fix LPUART driver + * 2025-10-08 Siwei Xu Fix MMU Enable issues + */ +#include "board.h" + +#include "serial.h" +#include "MIMX9131.h" + +#include +#include +#include +#include +#include + +#include + +#define DRAM_MAP_START KERNEL_BOOT_ADDR +#define DRAM_MAP_SIZE MB_SIZE(256) + +#define MEM_DESC(vaddr_start, size, paddr_start, attr) \ + vaddr_start, (vaddr_start + size - 1uL), paddr_start, attr + +extern volatile unsigned long MMUTable[]; + +static struct mem_desc platform_mem_desc[] = { + { MEM_DESC(DRAM_MAP_START, DRAM_MAP_SIZE, DRAM_MAP_START, NORMAL_MEM) }, // 0x8000_0000 + { MEM_DESC(LPUART1_BASE, LPUART1_SIZE, LPUART1_BASE, DEVICE_MEM) }, // 0x4438_0000 + { MEM_DESC(CCM_CTRL_BASE, CCM_CTRL_SIZE, CCM_CTRL_BASE, DEVICE_MEM) }, // 0x4445_8000 + { MEM_DESC(GIC_DISTRIBUTOR_BASE, GIC_DISTRIBUTOR_SIZE, GIC_DISTRIBUTOR_BASE, DEVICE_MEM) }, // 0x4800_0000 + { MEM_DESC(GIC_REDISTRIBUTOR_BASE, GIC_REDISTRIBUTOR_SIZE, GIC_REDISTRIBUTOR_BASE, DEVICE_MEM) }, // 0x4804_0000 +}; + +static const rt_uint32_t platform_mem_desc_size = sizeof(platform_mem_desc) / sizeof(platform_mem_desc[0]); + +static rt_region_t init_page_region; + +static rt_base_t get_sctlr_el1() +{ + rt_base_t sctlr = 0; + __asm__ volatile("mrs %0, sctlr_el1" : "=r"(sctlr)); + return sctlr; +} + +/** + * This function will initialize hardware board + */ +void rt_hw_board_init(void) +{ + rt_hw_earlycon_ioremap(); + rt_hw_earlycon_print_hex("sctlr_el1: ", get_sctlr_el1()); + rt_hw_mmu_map_init(&rt_kernel_space, (void *)0x080000000000, 0x10000000, (size_t *)MMUTable, 0); + + init_page_region.start = BOARD_PAGE_START; + init_page_region.end = BOARD_PAGE_END; + rt_page_init(init_page_region); + + rt_hw_mmu_setup(&rt_kernel_space, platform_mem_desc, platform_mem_desc_size); + +#ifdef RT_USING_HEAP + /* initialize system heap */ + rt_system_heap_init((void *)BOARD_HEAP_BEGIN, (void *)BOARD_HEAP_END); +#endif + + /* initialize hardware interrupt */ + rt_hw_interrupt_init(); + + /* initialize uart */ + rt_hw_uart_init(); + + /* initialize timer for os tick */ + rt_hw_gtimer_init(); + + rt_components_board_init(); + rt_console_set_device(RT_CONSOLE_DEVICE_NAME); +} diff --git a/bsp/nxp/imx/imx91/drivers/board.h b/bsp/nxp/imx/imx91/drivers/board.h new file mode 100644 index 00000000000..de5153f9234 --- /dev/null +++ b/bsp/nxp/imx/imx91/drivers/board.h @@ -0,0 +1,34 @@ +/* + * Copyright (c) 2006-2025, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2025-08-10 Siwei Xu Add i.MX91 SDK + * 2025-09-15 Siwei Xu Fix LPUART driver + * 2025-12-10 Siwei Xu Fix ioremap issues + */ + +#ifndef __BOARD_H__ +#define __BOARD_H__ + +#include "imx91.h" +#include "rtconfig.h" + +#ifndef KERNEL_BOOT_ADDR +#define KERNEL_BOOT_ADDR (ARCH_RAM_OFFSET + ARCH_TEXT_OFFSET) +#endif + +/* defined in linker script */ +extern unsigned char __bss_end; + +#define BOARD_PAGE_START RT_ALIGN((rt_base_t) & __bss_end, KB_SIZE(4)) +#define BOARD_PAGE_END (BOARD_PAGE_START + MB_SIZE(1)) + +#define BOARD_HEAP_BEGIN (BOARD_PAGE_END) +#define BOARD_HEAP_END (BOARD_HEAP_BEGIN + MB_SIZE(32)) + +void rt_hw_board_init(void); + +#endif diff --git a/bsp/nxp/imx/imx91/drivers/imx91.c b/bsp/nxp/imx/imx91/drivers/imx91.c new file mode 100644 index 00000000000..64380f07a19 --- /dev/null +++ b/bsp/nxp/imx/imx91/drivers/imx91.c @@ -0,0 +1,30 @@ +/* + * Copyright (c) 2006-2025, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2025-08-10 Siwei Xu Add i.MX91 SDK + */ +#include "imx91.h" + +#include "MIMX9131.h" + +#include +#include + +rt_base_t platform_get_gic_dist_base(void) +{ + return (rt_base_t)rt_ioremap((void *)GIC_DISTRIBUTOR_BASE, GIC_DISTRIBUTOR_SIZE); +} + +rt_base_t platform_get_gic_redist_base(void) +{ + return (rt_base_t)rt_ioremap((void *)GIC_REDISTRIBUTOR_BASE, GIC_REDISTRIBUTOR_SIZE); +} + +rt_base_t platform_get_gic_cpu_base(void) +{ + return (rt_base_t)rt_ioremap((void *)GIC_REDISTRIBUTOR_BASE, GIC_REDISTRIBUTOR_SIZE); +} diff --git a/bsp/nxp/imx/imx91/drivers/imx91.h b/bsp/nxp/imx/imx91/drivers/imx91.h new file mode 100644 index 00000000000..fd8452c10d5 --- /dev/null +++ b/bsp/nxp/imx/imx91/drivers/imx91.h @@ -0,0 +1,46 @@ +/* + * Copyright (c) 2006-2025, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2025-08-10 Siwei Xu Add i.MX91 SDK + */ + +#ifndef __IMX91_H__ +#define __IMX91_H__ + +#include + +/* 'ARM_GIC_MAX_NR' is the number of cores, gicv3.c required */ +#define ARM_GIC_MAX_NR 1 + +/* The platform maximum interrupts, interrupt.c required */ +#define ARM_GIC_NR_IRQS 256 + +/* Number of interrupts in the Vector table, interrupt.c required */ +#define MAX_HANDLERS 256 + +/* interrupt.c required. */ +rt_base_t platform_get_gic_dist_base(void); +rt_base_t platform_get_gic_redist_base(void); +rt_base_t platform_get_gic_cpu_base(void); + +/* interrupt.c required */ +#define GIC_IRQ_START 0 + +/* gic.c required */ +#define __REG32(x) (*((volatile unsigned int *)(x))) + +#define KB_SIZE(x) ((x) * 1024) +#define MB_SIZE(x) ((x) * 1024 * 1024) + +#define GIC_DISTRIBUTOR_SIZE KB_SIZE(64) +#define GIC_REDISTRIBUTOR_SIZE KB_SIZE(768) + +#define LPUART1_SIZE KB_SIZE(64) +#define CCM_CTRL_SIZE KB_SIZE(64) + +#endif /* __IMX91_H__ */ + diff --git a/bsp/nxp/imx/imx91/drivers/sdk/CMSIS/Core_AArch64/Include/CMSIS_Include_core_ca.cmake b/bsp/nxp/imx/imx91/drivers/sdk/CMSIS/Core_AArch64/Include/CMSIS_Include_core_ca.cmake new file mode 100644 index 00000000000..5b5997984ec --- /dev/null +++ b/bsp/nxp/imx/imx91/drivers/sdk/CMSIS/Core_AArch64/Include/CMSIS_Include_core_ca.cmake @@ -0,0 +1,12 @@ +#Description: CMSIS Include For Cortex-A; user_visible: True +include_guard(GLOBAL) +message("CMSIS_Include_core_ca component is included.") + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/../Source/cache_armv8a.c + ${CMAKE_CURRENT_LIST_DIR}/../Source/mmu_armv8a.c +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/. +) diff --git a/bsp/nxp/imx/imx91/drivers/sdk/CMSIS/Core_AArch64/Include/cache_armv8a.h b/bsp/nxp/imx/imx91/drivers/sdk/CMSIS/Core_AArch64/Include/cache_armv8a.h new file mode 100644 index 00000000000..f7d52f74269 --- /dev/null +++ b/bsp/nxp/imx/imx91/drivers/sdk/CMSIS/Core_AArch64/Include/cache_armv8a.h @@ -0,0 +1,131 @@ +/**************************************************************************//** + * @file cache_armv8a.h + * @brief CMSIS AARCH64 Cache API header file + * @version V1.0.0 + * @date 21. January 2022 + ******************************************************************************/ + +/* + * Copyright 2022 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CACHE_ARMV8A_H +#define __CACHE_ARMV8A_H + +#include +#include + +#ifdef __cplusplus + extern "C" { +#endif + +#define dcache_ops(op, operand) \ +({ \ + __asm__ volatile ("dc " __STRINGIFY(op) ", %0" \ + ::"r" (operand): "memory"); \ +}) + + +/* Invalidate instruction cache by virtual address to PoU */ +static inline void icache_invalidate_range(uintptr_t addr, size_t size) +{ + uintptr_t cur = addr; + uintptr_t end_addr = cur + size; + + /* Align address to line size */ + cur &= ~(ICACHE_LINE_SIZE - 1); + + do { + __asm__ volatile ("ic ivau, %0" ::"r" (cur): "memory"); + cur += ICACHE_LINE_SIZE; + } while (cur < end_addr); + + __DSB(); + __ISB(); +} + +/* Invalidate all instruction cache to PoU */ +static inline void icache_invalidate_all(void) +{ + __asm__ volatile ("ic iallu" ::: "memory"); + __DSB(); + __ISB(); +} + +/* Clean data cache by virtual address to PoC */ +static inline void dcache_clean_range(uintptr_t addr, size_t size) +{ + uintptr_t cur = addr; + uintptr_t end = addr + size; + + /* Align address to line size */ + cur &= ~(DCACHE_LINE_SIZE - 1); + + while (cur < end) { + dcache_ops(cvac, cur); + cur += DCACHE_LINE_SIZE; + } + + __DSB(); +} + +/* Invalidate data cache by virtual address to PoC */ +static inline void dcache_invalidate_range(uintptr_t addr, size_t size) +{ + uintptr_t cur = addr; + uintptr_t end = addr + size; + + if (end & (DCACHE_LINE_SIZE - 1)) { + end &= ~(DCACHE_LINE_SIZE - 1); + dcache_ops(civac, end); + } + + if (cur & (DCACHE_LINE_SIZE - 1)) { + cur &= ~(DCACHE_LINE_SIZE - 1); + if (cur != end) + dcache_ops(civac, cur); + cur += DCACHE_LINE_SIZE; + } + + while (cur < end) { + dcache_ops(ivac, cur); + cur += DCACHE_LINE_SIZE; + } + + __DSB(); +} + +/* Clean and invalidate data cache by virtual address to PoC */ +static inline void dcache_clean_invalidate_range(uintptr_t addr, size_t size) +{ + uintptr_t cur = addr; + uintptr_t end = addr + size; + + /* Align address to line size */ + cur &= ~(DCACHE_LINE_SIZE - 1); + + while (cur < end) { + dcache_ops(civac, cur); + cur += DCACHE_LINE_SIZE; + } + + __DSB(); +} + +void dcache_clean_all(void); +void dcache_invalidate_all(void); +void dcache_clean_invalidate_all(void); + +#ifdef __cplusplus +} +#endif + +#endif /* __CACHE_ARMV8A_H */ diff --git a/bsp/nxp/imx/imx91/drivers/sdk/CMSIS/Core_AArch64/Include/cmsis_compiler.h b/bsp/nxp/imx/imx91/drivers/sdk/CMSIS/Core_AArch64/Include/cmsis_compiler.h new file mode 100644 index 00000000000..3b8d8ca33ee --- /dev/null +++ b/bsp/nxp/imx/imx91/drivers/sdk/CMSIS/Core_AArch64/Include/cmsis_compiler.h @@ -0,0 +1,92 @@ +/**************************************************************************//** + * @file cmsis_gcc.h + * @brief CMSIS compiler generic header file + * @version V1.0.0 + * @date 05. october 2021 + ******************************************************************************/ +/* + * Copyright (c) 2021 Arm Limited. All rights reserved. + * Copyright 2021 NXP + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_COMPILER_H +#define __CMSIS_COMPILER_H + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang system_header /* treat file as system include file */ +#endif + +#include +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/* Define compiler macros for CPU architecture, if not yet defined by the + * compiler default macros + */ +#if __ARM_ARCH_8A__ +/* Macro already defined */ +#else + #if defined(__ARM_ARCH_8A) && __ARM_ARCH_8A == 1 + #define __ARM_ARCH_8A__ 1 + #endif /* __ARM_ARCH_8A == 1 */ +#endif + +#if defined ( __CC_ARM ) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined ( __GNUC__ ) + #include "cmsis_gcc.h" + +#elif defined ( __ICCARM__ ) + #include "cmsis_iar.h" + +#else + #error Unknown compiler +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ +#define RESERVED(N, T) T RESERVED##N; // placeholder struct members used for "reserved" areas + +#ifdef __cplusplus +} +#endif + +#endif /* __CMSIS_COMPILER_H */ diff --git a/bsp/nxp/imx/imx91/drivers/sdk/CMSIS/Core_AArch64/Include/cmsis_gcc.h b/bsp/nxp/imx/imx91/drivers/sdk/CMSIS/Core_AArch64/Include/cmsis_gcc.h new file mode 100644 index 00000000000..50b706a6ed2 --- /dev/null +++ b/bsp/nxp/imx/imx91/drivers/sdk/CMSIS/Core_AArch64/Include/cmsis_gcc.h @@ -0,0 +1,269 @@ +/**************************************************************************//** + * @file cmsis_gcc.h + * @brief CMSIS compiler specific macros, functions, instructions + * @version V1.0.0 + * @date 05. october 2021 + ******************************************************************************/ +/* + * Copyright (c) 2021 Arm Limited. All rights reserved. + * Copyright 2021-2022 NXP + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_GCC_H +#define __CMSIS_GCC_H + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __FORCEINLINE + #define __FORCEINLINE __attribute__((always_inline)) +#endif +#ifndef __INLINE + #define __INLINE inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif + +#ifndef __STRINGIFY + #define __STRINGIFY(x) #x +#endif + +#ifndef __MSR + #define __MSR(sysreg, val) \ + __asm volatile ("msr "__STRINGIFY(sysreg)", %0\n" : : "r"((uint64_t)(val))) +#endif + +#ifndef __MRS +#define __MRS(sysreg, pVal) \ + __asm volatile ("mrs %0, "__STRINGIFY(sysreg)"\n" : "=r"((*pVal))) +#endif + +#ifndef __WFI +#define __WFI() \ + __asm volatile ("wfi") +#endif + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + + +/** + \brief Get Interrupt Mask Bits + \details Returns the current state of the interrupt mask bits from the DAIF register. + \return Interrupt Mask value + */ +__STATIC_FORCEINLINE uint64_t __get_DAIF(void) +{ + uint64_t result; + __MRS(DAIF, &result); + return result; +} + + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the DAIF. + */ +__STATIC_FORCEINLINE void __enable_irq(void) +{ + __ASM volatile ("msr daifclr, #2" : : : "memory"); +} + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the DAIF. + */ +__STATIC_FORCEINLINE void __disable_irq(void) +{ + __ASM volatile ("msr daifset, #2" : : : "memory"); +} + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/** + \brief Hypervisor call with 2 arguments + \details Makes an hypervisor call with two arguments stored in x0 and x1. + */ +#define HVC_2(imm, x0, x1) __asm volatile ( \ + "mov x0, %0 \n\t" \ + "mov x1, %1 \n\t" \ + "hvc #" __STRINGIFY(imm) "\n\t" \ + : : "r" (x0), "r" (x1) : "x0", "x1", "memory") + +/** + \brief Multiprocessor Affinity + \details Indicates the core number in the Cortex-Axx processor. + */ +__STATIC_FORCEINLINE uint64_t __get_MPIDR_EL1(void) +{ + uint64_t result; + __MRS(MPIDR_EL1, &result); + return result; +} + +#define MPIDR_GetCoreID() \ + ({ uint64_t mpidr = __get_MPIDR_EL1(); \ + (mpidr >> (8 * MPIDR_SUPPORT_MT(mpidr))) & MPIDR_AFFLVL_MASK; }) + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#ifndef __ISB +__STATIC_FORCEINLINE void __ISB(void) +{ + __ASM volatile ("isb":::"memory"); +} +#endif + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#ifndef __DSB +__STATIC_FORCEINLINE void __DSB(void) +{ + __ASM volatile ("dsb sy":::"memory"); +} +#endif + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#ifndef __DMB +__STATIC_FORCEINLINE void __DMB(void) +{ + __ASM volatile ("dmb sy":::"memory"); +} +#endif + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __REV(uint32_t value) +{ + return __builtin_bswap32(value); +} + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __REV16(uint32_t value) +{ + return __builtin_bswap16(value); +} + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("brk "#value) + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ + +__STATIC_FORCEINLINE void __NOP(void) +{ + __ASM volatile ("nop"); +} + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) +{ + /* Even though __builtin_clz produces a CLZ instruction on ARM, formally + __builtin_clz(0) is undefined behaviour, so handle this case specially. + This guarantees ARM-compatible results if happening to compile on a non-ARM + target, and ensures the compiler doesn't decide to activate any + optimisations using the logic "value was passed to __builtin_clz, so it + is non-zero". + ARM GCC 7.3 and possibly earlier will optimise this test away, leaving a + single CLZ instruction. + */ + if (value == 0U) + { + return 32U; + } + return __builtin_clz(value); +} + +/** + \brief likely/unlikely() branch prediction + \details Gives hints to the compiler to favor either side of a jump instruction + \param [in] expr Boolean expression under evaluation + \return The same boolean value + */ +#ifndef unlikely +__STATIC_FORCEINLINE long unlikely(long expr) +{ + return __builtin_expect(expr, 0L); +} +#endif + +#ifndef likely +__STATIC_FORCEINLINE long likely(long expr) +{ + return __builtin_expect(expr, 1L); +} +#endif + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +#endif /* __CMSIS_GCC_H */ diff --git a/bsp/nxp/imx/imx91/drivers/sdk/CMSIS/Core_AArch64/Include/cmsis_iar.h b/bsp/nxp/imx/imx91/drivers/sdk/CMSIS/Core_AArch64/Include/cmsis_iar.h new file mode 100644 index 00000000000..1011994e119 --- /dev/null +++ b/bsp/nxp/imx/imx91/drivers/sdk/CMSIS/Core_AArch64/Include/cmsis_iar.h @@ -0,0 +1,30 @@ +/**************************************************************************//** + * @file cmsis_iar.h + * @brief CMSIS compiler specific macros, functions, instructions + * @version V1.0.0 + * @date 05. october 2021 + ******************************************************************************/ +/* + * Copyright (c) 2021 Arm Limited. All rights reserved. + * Copyright 2021 NXP + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef __CMSIS_IAR_H +#define __CMSIS_IAR_H + +#error Unsupported compiler + +#endif /* __CMSIS_IAR_H */ diff --git a/bsp/nxp/imx/imx91/drivers/sdk/CMSIS/Core_AArch64/Include/core_ca53.h b/bsp/nxp/imx/imx91/drivers/sdk/CMSIS/Core_AArch64/Include/core_ca53.h new file mode 100644 index 00000000000..f8e58439d0a --- /dev/null +++ b/bsp/nxp/imx/imx91/drivers/sdk/CMSIS/Core_AArch64/Include/core_ca53.h @@ -0,0 +1,108 @@ +/**************************************************************************//** + * @file core_ca53.h + * @brief CMSIS Cortex-A53 Core Peripheral Access Layer Header File + * @version V1.0.0 + * @date 05. october 2021 + ******************************************************************************/ +/* + * Copyright (c) 2021 Arm Limited. All rights reserved. + * Copyright 2021,2023 NXP + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CA53_H_GENERIC +#define __CORE_CA53_H_GENERIC + +#include +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ + +#define __CORTEX_Axx (53U) /*!< Cortex-Axx Core */ + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CA53_REV + #define __CA53_REV 0x0000U + #warning "__CA53_REV not defined in device header file; using default!" + #endif + + #ifndef __CACHE_PRESENT + #define __CACHE_PRESENT 1U + #warning "__CACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 1U + #define __FPU_USED 1U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __GIC_PRESENT + #define __GIC_PRESENT 1U + #warning "__GIC_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MMU_PRESENT + #define __MMU_PRESENT 1U + #warning "__MMU_PRESENT not defined in device header file; using default!" + #endif +#endif + +#include "cmsis_compiler.h" /* Core Instruction and Function Access */ + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CA53_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CA53_H_DEPENDANT +#define __CORE_CA53_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/******************************************************************************* + * Cache Functions + ******************************************************************************/ +#define ICACHE_LINE_SIZE (64) +#define DCACHE_LINE_SIZE (64) + +#include "core_common.h" + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CA53_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/nxp/imx/imx91/drivers/sdk/CMSIS/Core_AArch64/Include/core_ca55.h b/bsp/nxp/imx/imx91/drivers/sdk/CMSIS/Core_AArch64/Include/core_ca55.h new file mode 100644 index 00000000000..573a6e90704 --- /dev/null +++ b/bsp/nxp/imx/imx91/drivers/sdk/CMSIS/Core_AArch64/Include/core_ca55.h @@ -0,0 +1,109 @@ +/**************************************************************************//** + * @file core_ca55.h + * @brief CMSIS Cortex-A55 Core Peripheral Access Layer Header File + * @version V1.0.0 + * @date Nov. 2022 + ******************************************************************************/ +/* + * Copyright (c) 2021 Arm Limited. All rights reserved. + * Copyright 2021,2023 NXP + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CA55_H_GENERIC +#define __CORE_CA55_H_GENERIC + +#include +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ + +#define __CORTEX_Axx (55U) /*!< Cortex-Axx Core */ + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CA55_REV + #define __CA55_REV 0x0000U + #warning "__CA55_REV not defined in device header file; using default!" + #endif + + #ifndef __CACHE_PRESENT + #define __CACHE_PRESENT 1U + #warning "__CACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 1U + #define __FPU_USED 1U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __GIC_PRESENT + #define __GIC_PRESENT 1U + #warning "__GIC_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MMU_PRESENT + #define __MMU_PRESENT 1U + #warning "__MMU_PRESENT not defined in device header file; using default!" + #endif +#endif + +#include "cmsis_compiler.h" /* Core Instruction and Function Access */ + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CA55_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CA55_H_DEPENDANT +#define __CORE_CA55_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/******************************************************************************* + * Cache Functions + ******************************************************************************/ + +#define ICACHE_LINE_SIZE (64) +#define DCACHE_LINE_SIZE (64) + +#include "core_common.h" + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CA55_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/nxp/imx/imx91/drivers/sdk/CMSIS/Core_AArch64/Include/core_common.h b/bsp/nxp/imx/imx91/drivers/sdk/CMSIS/Core_AArch64/Include/core_common.h new file mode 100644 index 00000000000..e197390722a --- /dev/null +++ b/bsp/nxp/imx/imx91/drivers/sdk/CMSIS/Core_AArch64/Include/core_common.h @@ -0,0 +1,138 @@ +/**************************************************************************//** + * @file core_common.h + * @brief CMSIS Cortex-A AArch64 Core Common Header File + * @version V1.0.0 + * @date 06. Feb 2023 + ******************************************************************************/ +/* + * Copyright (c) 2021 Arm Limited. All rights reserved. + * Copyright 2023 NXP + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_COMMON_H +#define __CORE_COMMON_H + +#ifdef __cplusplus + extern "C" { +#endif + +/******************************************************************************* + * Register Definitions + ******************************************************************************/ + +#ifndef BIT +#define BIT(n) (1 << (n)) +#endif + +/* DAIF Register */ +#define DAIF_F_BIT BIT(6) +#define DAIF_I_BIT BIT(7) +#define DAIF_A_BIT BIT(8) +#define DAIF_D_BIT BIT(9) + +/* System Control Register */ +#define SCTLR_M_BIT BIT(0) +#define SCTLR_A_BIT BIT(1) +#define SCTLR_C_BIT BIT(2) +#define SCTLR_SA_BIT BIT(3) +#define SCTLR_I_BIT BIT(12) + +/* Exception levels EL0-EL3 */ +#define MODE_EL_SHIFT (0x2) +#define MODE_EL_MASK (0x3) + +#define MODE_EL3 (0x3) +#define MODE_EL2 (0x2) +#define MODE_EL1 (0x1) +#define MODE_EL0 (0x0) + +#define GET_EL(_mode) (((_mode) >> MODE_EL_SHIFT) & MODE_EL_MASK) + +/* MPIDR */ +#define MPIDR_AFFLVL_MASK (0xffULL) +#define MPIDR_AFF0_SHIFT (0) +#define MPIDR_AFF1_SHIFT (8) +#define MPIDR_AFF2_SHIFT (16) +#define MPIDR_AFF3_SHIFT (32) +#define MPIDR_MT_MASK (0x1) +#define MPIDR_MT_SHIFT (24) + +#define MPIDR_SUPPORT_MT(mpidr) ((mpidr >> MPIDR_MT_SHIFT) & MPIDR_MT_MASK) + + +#define MPIDR_TO_AFF_LEVEL(mpidr, aff_level) \ + (((mpidr) >> MPIDR_AFF##aff_level##_SHIFT) & MPIDR_AFFLVL_MASK) + +#define MPIDR_AFFINITY_MASK \ + ((MPIDR_AFFLVL_MASK << MPIDR_AFF3_SHIFT) | \ + (MPIDR_AFFLVL_MASK << MPIDR_AFF2_SHIFT) | \ + (MPIDR_AFFLVL_MASK << MPIDR_AFF1_SHIFT) | \ + (MPIDR_AFFLVL_MASK << MPIDR_AFF0_SHIFT)) + +/******************************************************************************* + * Cache Functions + ******************************************************************************/ + +#if defined (__CACHE_PRESENT) && (__CACHE_PRESENT == 1U) + + #include "cache_armv8a.h" + +#endif + + +/******************************************************************************* + * GIC Functions + ******************************************************************************/ + +#if defined (__GIC_PRESENT) && (__GIC_PRESENT == 1U) + + #include "gic_v3.h" + +#endif + + +/******************************************************************************* + * MMU Functions + ******************************************************************************/ + +#if defined (__MMU_PRESENT) && (__MMU_PRESENT == 1U) + + #include "mmu_armv8a.h" + +#endif + + +/******************************************************************************* + * Timer Functions + ******************************************************************************/ + +#if defined (__TIM_PRESENT) && (__TIM_PRESENT == 1U) + #include "timer_armv8a.h" +#endif + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_COMMON_H */ diff --git a/bsp/nxp/imx/imx91/drivers/sdk/CMSIS/Core_AArch64/Include/gic_v3.h b/bsp/nxp/imx/imx91/drivers/sdk/CMSIS/Core_AArch64/Include/gic_v3.h new file mode 100644 index 00000000000..b3a229a8a82 --- /dev/null +++ b/bsp/nxp/imx/imx91/drivers/sdk/CMSIS/Core_AArch64/Include/gic_v3.h @@ -0,0 +1,949 @@ +/**************************************************************************//** + * @file gic_v3.h + * @brief CMSIS Cortex-A53 Generic Interrupt Controller API header file + * @version V1.0.1 + * @date 05. october 2021 + ******************************************************************************/ +/* + * Copyright (c) 2021 Arm Limited. All rights reserved. + * Copyright 2021-2023 NXP + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __GIC_V3_H +#define __GIC_V3_H + +#ifdef __cplusplus + extern "C" { +#endif + +/******************************************************************************* + * GIC Data Types + ******************************************************************************/ + +/** \brief AArch64 System registers to access the Generic Interrupt Controller CPU interface +*/ +#if defined(__GNUC__) + #define ICC_BPR0_EL1 S3_0_C12_C8_3 + #define ICC_BPR1_EL1 S3_0_C12_C12_3 + #define ICC_CTLR_EL1 S3_0_C12_C12_4 + #define ICC_CTLR_EL3 S3_6_C12_C12_4 + #define ICC_EOIR0_EL1 S3_0_C12_C8_1 + #define ICC_EOIR1_EL1 S3_0_C12_C12_1 + #define ICC_HPPIR0_EL1 S3_0_C12_C8_2 + #define ICC_HPPIR1_EL1 S3_0_C12_C12_2 + #define ICC_IAR0_EL1 S3_0_C12_C8_0 + #define ICC_IAR1_EL1 S3_0_C12_C12_0 + #define ICC_IGRPEN0_EL1 S3_0_C12_C12_6 + #define ICC_IGRPEN1_EL1 S3_0_C12_C12_7 + #define ICC_IGRPEN1_EL3 S3_6_C12_C12_7 + #define ICC_PMR_EL1 S3_0_C4_C6_0 + #define ICC_RPR_EL1 S3_0_C12_C11_3 + #define ICC_SGI0R_EL1 S3_0_C12_C11_7 + #define ICC_SGI1R_EL1 S3_0_C12_C11_5 + #define ICC_SRE_EL1 S3_0_C12_C12_5 + #define ICC_SRE_EL2 S3_4_C12_C9_5 + #define ICC_SRE_EL3 S3_6_C12_C12_5 +#endif /* __GNUC__ */ + +/* ICC_SGIR */ +#define ICC_SGIR_TARGETLIST_SHIFT (0) +#define ICC_SGIR_TARGETLIST_MASK (0xffff) +#define ICC_SGIR_AFF_MASK (0xff) +#define ICC_SGIR_AFF1_SHIFT (16) +#define ICC_SGIR_INTID_SHIFT (24) +#define ICC_SGIR_INTID_MASK (0xf) +#define ICC_SGIR_AFF2_SHIFT (32) +#define ICC_SGIR_IRM_SHIFT (40) +#define ICC_SGIR_IRM_MASK (0x1) +#define ICC_SGIR_RS_SHIFT (44) +#define ICC_SGIR_RS_MASK (0xf) +#define ICC_SGIR_AFF3_SHIFT (48) + +#define MPIDR_TO_RS(mpidr) (MPIDR_TO_AFF_LEVEL(mpidr, 0) >> 4) + +#define COMPOSE_ICC_SGIR_VALUE(aff3, aff2, aff1, intid, irm, rs, tlist) \ + ((((uint64_t)(aff3) & ICC_SGIR_AFF_MASK) << ICC_SGIR_AFF3_SHIFT) | \ + (((uint64_t)(rs) & ICC_SGIR_RS_MASK) << ICC_SGIR_RS_SHIFT) | \ + (((uint64_t)(irm) & ICC_SGIR_IRM_MASK) << ICC_SGIR_IRM_SHIFT) | \ + (((uint64_t)(aff2) & ICC_SGIR_AFF_MASK) << ICC_SGIR_AFF2_SHIFT) | \ + (((intid) & ICC_SGIR_INTID_MASK) << ICC_SGIR_INTID_SHIFT) | \ + (((aff1) & ICC_SGIR_AFF_MASK) << ICC_SGIR_AFF1_SHIFT) | \ + (((tlist) & ICC_SGIR_TARGETLIST_MASK) << ICC_SGIR_TARGETLIST_SHIFT)) + +#define GIC_REDISTRIBUTOR_STRIDE (0x20000) +#define GICR_SGI_BASE_OFF (0x10000) + +#define GICR_TYPER_LAST_SHIFT (4) +#define GICR_TYPER_LAST_MASK (1 << GICR_TYPER_LAST_SHIFT) +#define GICR_TYPER_AFF_SHIFT (32) + +#define GICR_WAKER_PS_SHIFT (1) +#define GICR_WAKER_CA_SHIFT (2) + + +/** \brief Structure type to access the Generic Interrupt Controller Distributor (GICD) +*/ +typedef struct +{ + __IOM uint32_t CTLR; /*!< \brief Offset: 0x000 (R/W) Distributor Control Register */ + __IM uint32_t TYPER; /*!< \brief Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IM uint32_t IIDR; /*!< \brief Offset: 0x008 (R/ ) Distributor Implementer Identification Register */ + RESERVED(0, uint32_t) + __IOM uint32_t STATUSR; /*!< \brief Offset: 0x010 (R/W) Error Reporting Status Register, optional */ + RESERVED(1[11], uint32_t) + __OM uint32_t SETSPI_NSR; /*!< \brief Offset: 0x040 ( /W) Set SPI Register */ + RESERVED(2, uint32_t) + __OM uint32_t CLRSPI_NSR; /*!< \brief Offset: 0x048 ( /W) Clear SPI Register */ + RESERVED(3, uint32_t) + __OM uint32_t SETSPI_SR; /*!< \brief Offset: 0x050 ( /W) Set SPI, Secure Register */ + RESERVED(4, uint32_t) + __OM uint32_t CLRSPI_SR; /*!< \brief Offset: 0x058 ( /W) Clear SPI, Secure Register */ + RESERVED(5[9], uint32_t) + __IOM uint32_t IGROUPR[32]; /*!< \brief Offset: 0x080 (R/W) Interrupt Group Registers */ + __IOM uint32_t ISENABLER[32]; /*!< \brief Offset: 0x100 (R/W) Interrupt Set-Enable Registers */ + __IOM uint32_t ICENABLER[32]; /*!< \brief Offset: 0x180 (R/W) Interrupt Clear-Enable Registers */ + __IOM uint32_t ISPENDR[32]; /*!< \brief Offset: 0x200 (R/W) Interrupt Set-Pending Registers */ + __IOM uint32_t ICPENDR[32]; /*!< \brief Offset: 0x280 (R/W) Interrupt Clear-Pending Registers */ + __IOM uint32_t ISACTIVER[32]; /*!< \brief Offset: 0x300 (R/W) Interrupt Set-Active Registers */ + __IOM uint32_t ICACTIVER[32]; /*!< \brief Offset: 0x380 (R/W) Interrupt Clear-Active Registers */ + __IOM uint32_t IPRIORITYR[255]; /*!< \brief Offset: 0x400 (R/W) Interrupt Priority Registers */ + RESERVED(6, uint32_t) + __IOM uint32_t ITARGETSR[255]; /*!< \brief Offset: 0x800 (R/W) Interrupt Targets Registers */ + RESERVED(7, uint32_t) + __IOM uint32_t ICFGR[64]; /*!< \brief Offset: 0xC00 (R/W) Interrupt Configuration Registers */ + __IOM uint32_t IGRPMODR[32]; /*!< \brief Offset: 0xD00 (R/W) Interrupt Group Modifier Registers */ + RESERVED(8[32], uint32_t) + __IOM uint32_t NSACR[64]; /*!< \brief Offset: 0xE00 (R/W) Non-secure Access Control Registers */ + __OM uint32_t SGIR; /*!< \brief Offset: 0xF00 ( /W) Software Generated Interrupt Register */ + RESERVED(9[3], uint32_t) + __IOM uint32_t CPENDSGIR[4]; /*!< \brief Offset: 0xF10 (R/W) SGI Clear-Pending Registers */ + __IOM uint32_t SPENDSGIR[4]; /*!< \brief Offset: 0xF20 (R/W) SGI Set-Pending Registers */ + RESERVED(10[5172], uint32_t) + __IOM uint64_t IROUTER[988]; /*!< \brief Offset: 0x6000(R/W) Interrupt Routing Registers */ +} GICDistributor_Type; + +#define GICDistributor ((GICDistributor_Type *) GIC_DISTRIBUTOR_BASE ) /*!< \brief GIC Distributor register set access pointer */ + +/** \brief Structure type to access the Generic Interrupt Controller Redistributor (GICR) +*/ +typedef struct +{ + __IOM uint32_t CTLR; /*!< \brief Offset: 0x000 (R/W) Redistributor Control Register */ + __IM uint32_t IIDR; /*!< \brief Offset: 0x004 (R/ ) Implementer Identification Register */ + __IM uint64_t TYPER; /*!< \brief Offset: 0x008 (R/ ) Redistributor Type Register */ + __IOM uint32_t STATUSR; /*!< \brief Offset: 0x010 (R/W) Error Reporting Status Register, optional */ + __IOM uint32_t WAKER; /*!< \brief Offset: 0x014 (R/W) Redistributor Wake Register */ + __IM uint32_t MPAMIDR; /*!< \brief Offset: 0x018 (R/ ) Report maximum PARTID and PMG Register */ + __IOM uint32_t PARTIDR; /*!< \brief Offset: 0x01C (R/W) Set PARTID and PMG Register */ + RESERVED(1[8], uint32_t) + __OM uint32_t SETLPIR; /*!< \brief Offset: 0x040 ( /W) Set LPI Pending Register */ + RESERVED(2, uint32_t) + __OM uint32_t CLRLPIR; /*!< \brief Offset: 0x048 ( /W) Clear LPI Pending Register */ + RESERVED(3[9], uint32_t) + __IOM uint32_t PROPBASER; /*!< \brief Offset: 0x070 (R/W) Redistributor Properties Base Address Register */ + RESERVED(4, uint32_t) + __IOM uint32_t PENDBASER; /*!< \brief Offset: 0x078 (R/W) Redistributor LPI Pending Table Base Address Register */ + RESERVED(5[9], uint32_t) + __OM uint32_t INVLPIR; /*!< \brief Offset: 0x0A0 ( /W) Redistributor Invalidate LPI Register */ + RESERVED(6[3], uint32_t) + __OM uint32_t INVALLR; /*!< \brief Offset: 0x0B0 ( /W) Redistributor Invalidate All Register */ + RESERVED(7[3], uint32_t) + __IM uint32_t SYNCR; /*!< \brief Offset: 0x0C0 (R/ ) Redistributor Synchronize Register */ +} GICRedistributor_Type; + +/* Memory mapped GIC interface may be disabled when ICC_SRE_ELx.SRE set 1 by hypervisor. + In this case we will be using MSR/MRS system registers. */ +#ifdef GIC_INTERFACE_BASE + +/** \brief Structure type to access the Generic Interrupt Controller Interface (GICC) +*/ +typedef struct +{ + __IOM uint32_t CTLR; /*!< \brief Offset: 0x000 (R/W) CPU Interface Control Register */ + __IOM uint32_t PMR; /*!< \brief Offset: 0x004 (R/W) Interrupt Priority Mask Register */ + __IOM uint32_t BPR; /*!< \brief Offset: 0x008 (R/W) Binary Point Register */ + __IM uint32_t IAR; /*!< \brief Offset: 0x00C (R/ ) Interrupt Acknowledge Register */ + __OM uint32_t EOIR; /*!< \brief Offset: 0x010 ( /W) End Of Interrupt Register */ + __IM uint32_t RPR; /*!< \brief Offset: 0x014 (R/ ) Running Priority Register */ + __IM uint32_t HPPIR; /*!< \brief Offset: 0x018 (R/ ) Highest Priority Pending Interrupt Register */ + __IOM uint32_t ABPR; /*!< \brief Offset: 0x01C (R/W) Aliased Binary Point Register */ + __IM uint32_t AIAR; /*!< \brief Offset: 0x020 (R/ ) Aliased Interrupt Acknowledge Register */ + __OM uint32_t AEOIR; /*!< \brief Offset: 0x024 ( /W) Aliased End Of Interrupt Register */ + __IM uint32_t AHPPIR; /*!< \brief Offset: 0x028 (R/ ) Aliased Highest Priority Pending Interrupt Register */ + __IOM uint32_t STATUSR; /*!< \brief Offset: 0x02C (R/W) Error Reporting Status Register, optional */ + RESERVED(1[40], uint32_t) + __IOM uint32_t APR[4]; /*!< \brief Offset: 0x0D0 (R/W) Active Priority Register */ + __IOM uint32_t NSAPR[4]; /*!< \brief Offset: 0x0E0 (R/W) Non-secure Active Priority Register */ + RESERVED(2[3], uint32_t) + __IM uint32_t IIDR; /*!< \brief Offset: 0x0FC (R/ ) CPU Interface Identification Register */ + RESERVED(3[960], uint32_t) + __OM uint32_t DIR; /*!< \brief Offset: 0x1000( /W) Deactivate Interrupt Register */ +} GICInterface_Type; + +#define GICInterface ((GICInterface_Type *) GIC_INTERFACE_BASE ) /*!< \brief GIC Interface register set access pointer */ +#endif /* GIC_INTERFACE_BASE */ + +/* ctrl register access in non-secure */ +#define GICD_CTLR_RWP 31 +#define GICD_CTLR_ARE_NS 4 +#define GICD_CTLR_ENGRP1A 1 +#define GICD_CTLR_ENGRP1 0 + +#define GICR_CTLR_RWP 3 + +enum gic_rwp { + GICD_RWP, + GICR_RWP, +}; + +/******************************************************************************* + * GIC Functions + ******************************************************************************/ + +/* ########################## GIC functions ###################################### */ + +/** \brief Get the recomposed MPIDR_EL1 Affinity fields. +* the recomposed Affinity value format is (aff3:aff2:aff1:aff0) +*/ +__STATIC_INLINE uint32_t GIC_MPIDRtoAffinity(void) +{ + uint32_t aff3, aff2, aff1, aff0, aff; + uint64_t mpidr = __get_MPIDR_EL1(); + + aff0 = MPIDR_TO_AFF_LEVEL(mpidr, 0); + aff1 = MPIDR_TO_AFF_LEVEL(mpidr, 1); + aff2 = MPIDR_TO_AFF_LEVEL(mpidr, 2); + aff3 = MPIDR_TO_AFF_LEVEL(mpidr, 3); + + aff = (aff0 & MPIDR_AFFLVL_MASK) << 0 | + (aff1 & MPIDR_AFFLVL_MASK) << 8 | + (aff2 & MPIDR_AFFLVL_MASK) << 16 | + (aff3 & MPIDR_AFFLVL_MASK) << 24; + + return aff; +} + +/** \brief Get the Redistributor base. +*/ +__STATIC_INLINE GICRedistributor_Type *GIC_GetRdist(void) +{ + uintptr_t rd_addr = GIC_REDISTRIBUTOR_BASE; + uint32_t rd_aff, aff = GIC_MPIDRtoAffinity(); + uint64_t rd_typer; + + do { + rd_typer = ((GICRedistributor_Type *)rd_addr)->TYPER; + rd_aff = rd_typer >> GICR_TYPER_AFF_SHIFT; + + if (rd_aff == aff) + return (GICRedistributor_Type *)rd_addr; + + rd_addr += GIC_REDISTRIBUTOR_STRIDE; + } while (!(rd_typer & GICR_TYPER_LAST_MASK)); + + return NULL; +} + +/** \brief Get the Redistributor SGI_base. +*/ +__STATIC_INLINE void *GIC_GetRdistSGIBase(void *rd_base) +{ + return (void *)((uintptr_t)rd_base + GICR_SGI_BASE_OFF); +} + +/** \brief Wait for register write pending. +*/ +__STATIC_INLINE void GIC_WaitRWP(enum gic_rwp rwp) +{ + uint32_t rwp_mask; + uint32_t __IM *base; + + if (rwp == GICR_RWP) { + base = &GIC_GetRdist()->CTLR; + if (!base) + return; + rwp_mask = BIT(GICR_CTLR_RWP); + } else if (rwp == GICD_RWP) { + base = &GICDistributor->CTLR; + rwp_mask = BIT(GICD_CTLR_RWP); + } else { + return; + } + + while (*base & rwp_mask) + ; +} + +/** \brief Get the Affinity Routing status. +*/ +__STATIC_INLINE bool GIC_GetARE(void) +{ + return !!(GICDistributor->CTLR & 0x30); +} + +/** \brief Disable the interrupt distributor using the GIC's CTLR register. +*/ +__STATIC_INLINE void GIC_DisableDistributor(void) +{ + GICDistributor->CTLR &=~1U; + GIC_WaitRWP(GICD_RWP); +} + +/** \brief Read the GIC's TYPER register. +* \return GICDistributor_Type::TYPER +*/ +__STATIC_INLINE uint32_t GIC_DistributorInfo(void) +{ + return (GICDistributor->TYPER); +} + +/** \brief Reads the GIC's IIDR register. +* \return GICDistributor_Type::IIDR +*/ +__STATIC_INLINE uint32_t GIC_DistributorImplementer(void) +{ + return (GICDistributor->IIDR); +} + +/** \brief Sets the GIC's ITARGETSR register for the given interrupt. +* \param [in] IRQn Interrupt to be configured. +* \param [in] cpu_target CPU interfaces to assign this interrupt to. +*/ +__STATIC_INLINE void GIC_SetTarget(IRQn_Type IRQn, uint64_t cpu_target) +{ + if (IRQn >= 32) + { + if (GIC_GetARE()) + { + /* affinity routing */ + GICDistributor->IROUTER[IRQn] = cpu_target; + } + else + { + /* legacy */ + uint32_t mask = GICDistributor->ITARGETSR[IRQn / 4U] & ~(0xFFUL << ((IRQn % 4U) * 8U)); + GICDistributor->ITARGETSR[IRQn / 4U] = mask | ((cpu_target & 0xFFUL) << ((IRQn % 4U) * 8U)); + } + } +} + +/** \brief Get the target core of the interrupt. +* \param [in] IRQn Interrupt to acquire the configuration for. +* +* \return: +* For SPI: GICDistributor_Type::ITARGETSR when Affinity Routing isn't enabled, +* or GICDistributor_Type::IROUTER when Affinity Routing is enabled +* For SGI/PPI: The Affinity fields of the MPIDR_EL1. +*/ +__STATIC_INLINE uint64_t GIC_GetTarget(IRQn_Type IRQn) +{ + uint64_t cpu_target = 0; + + if (IRQn >= 32) + { + if (GIC_GetARE()) + { + /* affinity routing */ + cpu_target = GICDistributor->IROUTER[IRQn]; + } + else + { + /* legacy */ + cpu_target = (GICDistributor->ITARGETSR[IRQn / 4U] >> ((IRQn % 4U) * 8U)) & 0xFFUL; + } + } + else + { + /* local */ + cpu_target = __get_MPIDR_EL1() & MPIDR_AFFINITY_MASK; + } + + return cpu_target; +} + +/** \brief Enables the given interrupt using GIC's ISENABLER register. +* \param [in] IRQn The interrupt to be enabled. +*/ +__STATIC_INLINE void GIC_EnableIRQ(IRQn_Type IRQn) +{ + uint64_t mpidr = __get_MPIDR_EL1(); + GICDistributor_Type *s_RedistPPIBaseAddrs; + + GIC_SetTarget(IRQn, mpidr & MPIDR_AFFINITY_MASK); + + if (IRQn < 32) { + s_RedistPPIBaseAddrs = GIC_GetRdistSGIBase(GIC_GetRdist()); + s_RedistPPIBaseAddrs->ISENABLER[0] = 1U << IRQn; + } else { + GICDistributor->ISENABLER[IRQn / 32U] = 1U << (IRQn % 32U); + } +} + +/** \brief Get interrupt enable status using GIC's ISENABLER register. +* \param [in] IRQn The interrupt to be queried. +* \return 0 - interrupt is not enabled, 1 - interrupt is enabled. +*/ +__STATIC_INLINE uint32_t GIC_GetEnableIRQ(IRQn_Type IRQn) +{ + return (GICDistributor->ISENABLER[IRQn / 32U] >> (IRQn % 32U)) & 1UL; +} + +/** \brief Disables the given interrupt using GIC's ICENABLER register. +* \param [in] IRQn The interrupt to be disabled. +*/ +__STATIC_INLINE void GIC_DisableIRQ(IRQn_Type IRQn) +{ + GICDistributor_Type *s_RedistPPIBaseAddrs; + + if (IRQn < 32) { + s_RedistPPIBaseAddrs = GIC_GetRdistSGIBase(GIC_GetRdist()); + s_RedistPPIBaseAddrs->ICENABLER[0] = 1U << IRQn; + GIC_WaitRWP(GICR_RWP); + } else { + GICDistributor->ICENABLER[IRQn / 32U] = 1U << (IRQn % 32U); + GIC_WaitRWP(GICD_RWP); + } +} + +/** \brief Get interrupt pending status from GIC's ISPENDR register. +* \param [in] IRQn The interrupt to be queried. +* \return 0 - interrupt is not pending, 1 - interrupt is pendig. +*/ +__STATIC_INLINE uint32_t GIC_GetPendingIRQ(IRQn_Type IRQn) +{ + uint32_t pend; + + if (IRQn >= 16) { + pend = (GICDistributor->ISPENDR[IRQn / 32U] >> (IRQn % 32U)) & 1UL; + } else { + // INTID 0-15 Software Generated Interrupt + pend = (GICDistributor->SPENDSGIR[IRQn / 4U] >> ((IRQn % 4U) * 8U)) & 0xFFUL; + // No CPU identification offered + if (pend != 0U) { + pend = 1U; + } else { + pend = 0U; + } + } + + return (pend); +} + +/** \brief Sets the given interrupt as pending using GIC's ISPENDR register. +* \param [in] IRQn The interrupt to be enabled. +*/ +__STATIC_INLINE void GIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if (IRQn >= 16) { + GICDistributor->ISPENDR[IRQn / 32U] = 1U << (IRQn % 32U); + } else { + // INTID 0-15 Software Generated Interrupt + GICDistributor->SPENDSGIR[IRQn / 4U] = 1U << ((IRQn % 4U) * 8U); + // Forward the interrupt to the CPU interface that requested it + GICDistributor->SGIR = (IRQn | 0x02000000U); + } +} + +/** \brief Clears the given interrupt from being pending using GIC's ICPENDR register. +* \param [in] IRQn The interrupt to be enabled. +*/ +__STATIC_INLINE void GIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if (IRQn >= 16) { + GICDistributor->ICPENDR[IRQn / 32U] = 1U << (IRQn % 32U); + } else { + // INTID 0-15 Software Generated Interrupt + GICDistributor->CPENDSGIR[IRQn / 4U] = 1U << ((IRQn % 4U) * 8U); + } +} + +/** \brief Sets the interrupt configuration using GIC's ICFGR register. +* \param [in] IRQn The interrupt to be configured. +* \param [in] int_config Int_config field value. Bit 0: Reserved (0 - N-N model, 1 - 1-N model for some GIC before v1) +* Bit 1: 0 - level sensitive, 1 - edge triggered +*/ +__STATIC_INLINE void GIC_SetConfiguration(IRQn_Type IRQn, uint32_t int_config) +{ + uint32_t icfgr = GICDistributor->ICFGR[IRQn / 16U]; + uint32_t shift = (IRQn % 16U) << 1U; + + icfgr &= (~(3U << shift)); + icfgr |= ( int_config << shift); + + GICDistributor->ICFGR[IRQn / 16U] = icfgr; +} + +/** \brief Get the interrupt configuration from the GIC's ICFGR register. +* \param [in] IRQn Interrupt to acquire the configuration for. +* \return Int_config field value. Bit 0: Reserved (0 - N-N model, 1 - 1-N model for some GIC before v1) +* Bit 1: 0 - level sensitive, 1 - edge triggered +*/ +__STATIC_INLINE uint32_t GIC_GetConfiguration(IRQn_Type IRQn) +{ + return (GICDistributor->ICFGR[IRQn / 16U] >> ((IRQn % 16U) >> 1U)); +} + +__STATIC_INLINE void GIC_SetRedistPriority(IRQn_Type IRQn, uint32_t priority) +{ + GICDistributor_Type *s_RedistPPIBaseAddrs = GIC_GetRdistSGIBase(GIC_GetRdist()); + uint32_t mask = s_RedistPPIBaseAddrs->IPRIORITYR[IRQn / 4U] & ~(0xFFUL << ((IRQn % 4U) * 8U)); + + s_RedistPPIBaseAddrs->IPRIORITYR[IRQn / 4U] = mask | ((priority & 0xFFUL) << ((IRQn % 4U) * 8U)); +} + +/** \brief Set the priority for the given interrupt. +* \param [in] IRQn The interrupt to be configured. +* \param [in] priority The priority for the interrupt, lower values denote higher priorities. +*/ +__STATIC_INLINE void GIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + uint32_t mask; + + if ((IRQn < 32) && (GIC_GetARE())) { + GIC_SetRedistPriority(IRQn, priority); + } else { + mask = GICDistributor->IPRIORITYR[IRQn / 4U] & ~(0xFFUL << ((IRQn % 4U) * 8U)); + GICDistributor->IPRIORITYR[IRQn / 4U] = mask | ((priority & 0xFFUL) << ((IRQn % 4U) * 8U)); + } +} + +__STATIC_INLINE void GIC_RedistWakeUp(void) +{ + GICRedistributor_Type *const s_RedistBaseAddrs = GIC_GetRdist(); + + if (!s_RedistBaseAddrs) + return; + + if (!(s_RedistBaseAddrs->WAKER & (1 << GICR_WAKER_CA_SHIFT))) + return; + + s_RedistBaseAddrs->WAKER &= ~ (1 << GICR_WAKER_PS_SHIFT); + while (s_RedistBaseAddrs->WAKER & (1 << GICR_WAKER_CA_SHIFT)) + ; +} + +__STATIC_INLINE uint32_t GIC_GetRedistPriority(IRQn_Type IRQn) +{ + GICDistributor_Type *s_RedistPPIBaseAddrs; + + s_RedistPPIBaseAddrs = GIC_GetRdistSGIBase(GIC_GetRdist()); + return (s_RedistPPIBaseAddrs->IPRIORITYR[IRQn / 4U] >> ((IRQn % 4U) * 8U)) & 0xFFUL; +} + +/** \brief Read the current interrupt priority from GIC's IPRIORITYR register. +* \param [in] IRQn The interrupt to be queried. +*/ +__STATIC_INLINE uint32_t GIC_GetPriority(IRQn_Type IRQn) +{ + if ((IRQn < 32) && (GIC_GetARE())) { + return GIC_GetRedistPriority(IRQn); + } else { + return (GICDistributor->IPRIORITYR[IRQn / 4U] >> ((IRQn % 4U) * 8U)) & 0xFFUL; + } +} + +/** \brief Get the status for a given interrupt. +* \param [in] IRQn The interrupt to get status for. +* \return 0 - not pending/active, 1 - pending, 2 - active, 3 - pending and active +*/ +__STATIC_INLINE uint32_t GIC_GetIRQStatus(IRQn_Type IRQn) +{ + uint32_t pending, active; + + active = ((GICDistributor->ISACTIVER[IRQn / 32U]) >> (IRQn % 32U)) & 1UL; + pending = ((GICDistributor->ISPENDR[IRQn / 32U]) >> (IRQn % 32U)) & 1UL; + + return ((active<<1U) | pending); +} + +/** \brief Generate a software interrupt (Affinity Routing version). +* \param [in] IRQn Software interrupt to be generated. +* \param [in] target_aff Target affinity in MPIDR form. +* \param [in] tlist List of CPUs the software interrupt should be forwarded to. +*/ +__STATIC_INLINE void GIC_SendSGI_ARE(IRQn_Type IRQn, uint64_t target_aff, uint16_t tlist) +{ + uint32_t aff3, aff2, aff1, rs; + uint64_t val; + + if (IRQn >= 16) + return; + + aff1 = MPIDR_TO_AFF_LEVEL(target_aff, 1); + aff2 = MPIDR_TO_AFF_LEVEL(target_aff, 2); + aff3 = MPIDR_TO_AFF_LEVEL(target_aff, 3); + rs = MPIDR_TO_RS(target_aff); + val = COMPOSE_ICC_SGIR_VALUE(aff3, aff2, aff1, IRQn, 0, rs, tlist); + + __DSB(); + __MSR(ICC_SGI1R_EL1, val); + __ISB(); +} + +/** \brief Generate a software interrupt. +* \param [in] IRQn Software interrupt to be generated. +* \param [in] target_aff Target affinity in MPIDR form. +* \param [in] target_list List of CPUs the software interrupt should be forwarded to. +*/ +__STATIC_INLINE void GIC_SendSGI(IRQn_Type IRQn, uint64_t target_aff, uint16_t target_list) +{ + if (IRQn >= 16) + return; + + if (GIC_GetARE()) { + /* affinity routing */ + GIC_SendSGI_ARE(IRQn, target_aff, target_list); + } else { + GICDistributor->SGIR = ((target_list & 0xFFUL) << 16U) | (IRQn & 0x0FUL); + } +} + +/** \brief Set the interrupt group from the GIC's IGROUPR register. +* \param [in] IRQn The interrupt to be queried. +* \param [in] group Interrupt group number: 0 - Group 0, 1 - Group 1 +*/ +__STATIC_INLINE void GIC_SetGroup(IRQn_Type IRQn, uint32_t group) +{ + uint32_t igroupr = GICDistributor->IGROUPR[IRQn / 32U]; + uint32_t shift = (IRQn % 32U); + + igroupr &= (~(1U << shift)); + igroupr |= ( (group & 1U) << shift); + + GICDistributor->IGROUPR[IRQn / 32U] = igroupr; +} +#define GIC_SetSecurity GIC_SetGroup + +__STATIC_INLINE void GIC_SetRedistGroup(IRQn_Type IRQn, uint32_t group) +{ + GICDistributor_Type *s_RedistPPIBaseAddrs; + uint32_t shift = (IRQn % 32U); + uint32_t igroupr; + + s_RedistPPIBaseAddrs = GIC_GetRdistSGIBase(GIC_GetRdist()); + igroupr = s_RedistPPIBaseAddrs->IGROUPR[IRQn / 32U]; + + igroupr &= (~(1U << shift)); + igroupr |= ( (group & 1U) << shift); + + s_RedistPPIBaseAddrs->IGROUPR[IRQn / 32U] = igroupr; +} +#define GIC_SetSecurity GIC_SetGroup + +/** \brief Get the interrupt group from the GIC's IGROUPR register. +* \param [in] IRQn The interrupt to be queried. +* \return 0 - Group 0, 1 - Group 1 +*/ +__STATIC_INLINE uint32_t GIC_GetGroup(IRQn_Type IRQn) +{ + return (GICDistributor->IGROUPR[IRQn / 32U] >> (IRQn % 32U)) & 1UL; +} +#define GIC_GetSecurity GIC_GetGroup + +/** \brief Initialize the interrupt distributor. +*/ +__STATIC_INLINE void GIC_DistInit(void) +{ + uint32_t i; + uint32_t num_irq = 0U; + uint32_t priority_field; + uint32_t ppi_priority; + + //A reset sets all bits in the IGROUPRs corresponding to the SPIs to 0, + //configuring all of the interrupts as Secure. + + //Disable interrupt forwarding + GIC_DisableDistributor(); + //Get the maximum number of interrupts that the GIC supports + num_irq = 32U * ((GIC_DistributorInfo() & 0x1FU) + 1U); + + /* Priority level is implementation defined. + To determine the number of priority bits implemented write 0xFF to an IPRIORITYR + priority field and read back the value stored. + Use PPI, as it is always accessible, even for a Guest OS using a hypervisor. + Then restore the initial state.*/ + ppi_priority = GIC_GetPriority((IRQn_Type)31U); + GIC_SetPriority((IRQn_Type)31U, 0xFFU); + priority_field = GIC_GetPriority((IRQn_Type)31U); + GIC_SetPriority((IRQn_Type)31U, ppi_priority); + + for (i = 32U; i < num_irq; i++) + { + /* Use non secure group1 for all SPI */ + GIC_SetGroup(i, 1); + //Disable the SPI interrupt + GIC_DisableIRQ((IRQn_Type)i); + //Set level-sensitive (and N-N model) + GIC_SetConfiguration((IRQn_Type)i, 0U); + //Set priority + GIC_SetPriority((IRQn_Type)i, priority_field*2U/3U); + } + + /* Enable distributor with ARE_NS and NS_Group1 */ + GICDistributor->CTLR = ((1U << GICD_CTLR_ARE_NS) | (1U << GICD_CTLR_ENGRP1A)); + GIC_WaitRWP(GICD_RWP); +} + +/** \brief Initialize the interrupt redistributor. +*/ +__STATIC_INLINE void GIC_RedistInit(void) +{ + uint32_t i; + uint32_t priority_field; + + /* Priority level is implementation defined. + To determine the number of priority bits implemented write 0xFF to an IPRIORITYR + priority field and read back the value stored.*/ + GIC_SetRedistPriority((IRQn_Type)31U, 0xFFU); + priority_field = GIC_GetRedistPriority((IRQn_Type)31U); + + /* Wakeup the GIC */ + GIC_RedistWakeUp(); + + for (i = 0; i < 32; i++) + { + //Disable the SPI interrupt + GIC_DisableIRQ((IRQn_Type)i); + //Set priority + GIC_SetRedistPriority((IRQn_Type)i, priority_field*2U/3U); + } +} + +#ifdef GICInterface + +/** \brief Enable the CPU's interrupt interface. +*/ +__STATIC_INLINE void GIC_EnableInterface(void) +{ + GICInterface->CTLR |= 1U; //enable interface +} + +/** \brief Disable the CPU's interrupt interface. +*/ +__STATIC_INLINE void GIC_DisableInterface(void) +{ + GICInterface->CTLR &=~1U; //disable distributor +} + +/** \brief Read the CPU's IAR register. +* \return GICInterface_Type::IAR +*/ +__STATIC_INLINE IRQn_Type GIC_AcknowledgePending(void) +{ + return (IRQn_Type)(GICInterface->IAR); +} + +/** \brief Writes the given interrupt number to the CPU's EOIR register. +* \param [in] IRQn The interrupt to be signaled as finished. +*/ +__STATIC_INLINE void GIC_EndInterrupt(IRQn_Type IRQn) +{ + GICInterface->EOIR = IRQn; +} + + +/** \brief Set the interrupt priority mask using CPU's PMR register. +* \param [in] priority Priority mask to be set. +*/ +__STATIC_INLINE void GIC_SetInterfacePriorityMask(uint32_t priority) +{ + GICInterface->PMR = priority & 0xFFUL; //set priority mask +} + +/** \brief Read the current interrupt priority mask from CPU's PMR register. +* \result GICInterface_Type::PMR +*/ +__STATIC_INLINE uint32_t GIC_GetInterfacePriorityMask(void) +{ + return GICInterface->PMR; +} + +/** \brief Configures the group priority and subpriority split point using CPU's BPR register. +* \param [in] binary_point Amount of bits used as subpriority. +*/ +__STATIC_INLINE void GIC_SetBinaryPoint(uint32_t binary_point) +{ + GICInterface->BPR = binary_point & 7U; //set binary point +} + +/** \brief Read the current group priority and subpriority split point from CPU's BPR register. +* \return GICInterface_Type::BPR +*/ +__STATIC_INLINE uint32_t GIC_GetBinaryPoint(void) +{ + return GICInterface->BPR; +} + +/** \brief Get the interrupt number of the highest interrupt pending from CPU's HPPIR register. +* \return GICInterface_Type::HPPIR +*/ +__STATIC_INLINE uint32_t GIC_GetHighPendingIRQ(void) +{ + return GICInterface->HPPIR; +} + +/** \brief Provides information about the implementer and revision of the CPU interface. +* \return GICInterface_Type::IIDR +*/ +__STATIC_INLINE uint32_t GIC_GetInterfaceId(void) +{ + return GICInterface->IIDR; +} + +#else /* GICInterface */ + +/** \brief Enable the CPU's interrupt interface. +*/ +__STATIC_INLINE void GIC_EnableInterface(void) +{ + __MSR(ICC_IGRPEN1_EL1, 1); +} + +/** \brief Disable the CPU's interrupt interface. +*/ +__STATIC_INLINE void GIC_DisableInterface(void) +{ + __MSR(ICC_IGRPEN1_EL1, 0); +} + +/** \brief Read the CPU's IAR register. +* \return GICInterface_Type::IAR +*/ +__STATIC_INLINE IRQn_Type GIC_AcknowledgePending(void) +{ + uint32_t result; + __MRS(ICC_IAR1_EL1, &result); + return (IRQn_Type)(result); +} + +/** \brief Writes the given interrupt number to the CPU's EOIR register. +* \param [in] IRQn The interrupt to be signaled as finished. +*/ +__STATIC_INLINE void GIC_EndInterrupt(IRQn_Type IRQn) +{ + __MSR(ICC_EOIR1_EL1, (uint32_t)IRQn); +} + +/** \brief Set the interrupt priority mask using CPU's PMR register. +* \param [in] priority Priority mask to be set. +*/ +__STATIC_INLINE void GIC_SetInterfacePriorityMask(uint32_t priority) +{ + __MSR(ICC_PMR_EL1, priority & 0xFFUL); +} + +/** \brief Read the current interrupt priority mask from CPU's PMR register. +* \result GICInterface_Type::PMR +*/ +__STATIC_INLINE uint32_t GIC_GetInterfacePriorityMask(void) +{ + uint32_t result; + __MRS(ICC_PMR_EL1, &result); + return result; +} + +/** \brief Configures the group priority and subpriority split point using CPU's BPR register. +* \param [in] binary_point Amount of bits used as subpriority. +*/ +__STATIC_INLINE void GIC_SetBinaryPoint(uint32_t binary_point) +{ + __MSR(ICC_BPR1_EL1, binary_point & 7U); +} + +/** \brief Read the current group priority and subpriority split point from CPU's BPR register. +* \return GICInterface_Type::BPR +*/ +__STATIC_INLINE uint32_t GIC_GetBinaryPoint(void) +{ + uint32_t result; + __MRS(ICC_BPR1_EL1, &result); + return result; +} + +/** \brief Get the interrupt number of the highest interrupt pending from CPU's HPPIR register. +* \return GICInterface_Type::HPPIR +*/ +__STATIC_INLINE uint32_t GIC_GetHighPendingIRQ(void) +{ + uint32_t result; + __MRS(ICC_HPPIR1_EL1, &result); + return result; +} + +#endif + +__STATIC_INLINE void GIC_CPUInterfaceInit(void) +{ + uint32_t i; + uint32_t priority_field; + + //A reset sets all bits in the IGROUPRs corresponding to the SPIs to 0, + //configuring all of the interrupts as Secure. + + //Disable interrupt forwarding + GIC_DisableInterface(); + + /* Priority level is implementation defined. + To determine the number of priority bits implemented write 0xFF to an IPRIORITYR + priority field and read back the value stored.*/ + GIC_SetPriority((IRQn_Type)0U, 0xFFU); + priority_field = GIC_GetPriority((IRQn_Type)0U); + + //SGI and PPI + for (i = 0U; i < 32U; i++) + { + if (i > 15U) { + //Set level-sensitive (and N-N model) for PPI + GIC_SetConfiguration((IRQn_Type)i, 0U); + } + //Disable SGI and PPI interrupts + GIC_DisableIRQ((IRQn_Type)i); + //Set priority + GIC_SetPriority((IRQn_Type)i, priority_field*2U/3U); + } + + //Set binary point to 0 + GIC_SetBinaryPoint(0U); + //Set priority mask + GIC_SetInterfacePriorityMask(0xFFU); + //Enable interface + GIC_EnableInterface(); +} + +/** \brief Initialize and enable the GIC +*/ +__STATIC_INLINE void GIC_Enable(int init_dist) +{ + /* Only one core should be responsible for the GIC distributor setup */ + if (init_dist) + GIC_DistInit(); + + GIC_RedistInit(); + GIC_CPUInterfaceInit(); //per CPU +} + +#ifdef __cplusplus +} +#endif + +#endif /* __GIC_V3_H */ diff --git a/bsp/nxp/imx/imx91/drivers/sdk/CMSIS/Core_AArch64/Include/mmu_armv8a.h b/bsp/nxp/imx/imx91/drivers/sdk/CMSIS/Core_AArch64/Include/mmu_armv8a.h new file mode 100644 index 00000000000..b081c922c15 --- /dev/null +++ b/bsp/nxp/imx/imx91/drivers/sdk/CMSIS/Core_AArch64/Include/mmu_armv8a.h @@ -0,0 +1,248 @@ +/**************************************************************************//** + * @file mmu_armv8a.h + * @brief CMSIS Cortex-Axx MMU API header file + * @version V1.0.0 + * @date 20. october 2021 + ******************************************************************************/ +/* + * Copyright 2019 Broadcom + * The term "Broadcom" refers to Broadcom Inc. and/or its subsidiaries. + * Copyright (c) 2021 Arm Limited. All rights reserved. + * Copyright 2021 NXP + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __MMU_ARMV8A_H +#define __MMU_ARMV8A_H + +#include +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/******************************************************************************/ + +/* Following Memory types supported through MAIR encodings can be passed + * by user through "attrs"(attributes) field of specified memory region. + * As MAIR supports such 8 encodings, we will reserve attrs[2:0]; + * so that we can provide encodings upto 7 if needed in future. + */ +#define MT_TYPE_MASK 0x7U +#define MT_TYPE(attr) (attr & MT_TYPE_MASK) +#define MT_DEVICE_nGnRnE 0U +#define MT_DEVICE_nGnRE 1U +#define MT_DEVICE_GRE 2U +#define MT_NORMAL_NC 3U +#define MT_NORMAL 4U +#define MT_NORMAL_WT 5U + +#define MEMORY_ATTRIBUTES ((0x00 << (MT_DEVICE_nGnRnE * 8)) | \ + (0x04 << (MT_DEVICE_nGnRE * 8)) | \ + (0x0c << (MT_DEVICE_GRE * 8)) | \ + (0x44 << (MT_NORMAL_NC * 8)) | \ + (0xffUL << (MT_NORMAL * 8)) | \ + (0xbbUL << (MT_NORMAL_WT * 8))) + +/* More flags from user's perpective are supported using remaining bits + * of "attrs" field, i.e. attrs[31:3], underlying code will take care + * of setting PTE fields correctly. + * + * current usage of attrs[31:3] is: + * attrs[3] : Access Permissions + * attrs[4] : Memory access from secure/ns state + * attrs[5] : Execute Permissions privileged mode (PXN) + * attrs[6] : Execute Permissions unprivileged mode (UXN) + * attrs[7] : Mirror RO/RW permissions to EL0 + * attrs[8] : Overwrite existing mapping if any + * + */ +#define MT_PERM_SHIFT 3U +#define MT_SEC_SHIFT 4U +#define MT_P_EXECUTE_SHIFT 5U +#define MT_U_EXECUTE_SHIFT 6U +#define MT_RW_AP_SHIFT 7U +#define MT_NO_OVERWRITE_SHIFT 8U + +#define MT_RO (0U << MT_PERM_SHIFT) +#define MT_RW (1U << MT_PERM_SHIFT) + +#define MT_RW_AP_ELx (1U << MT_RW_AP_SHIFT) +#define MT_RW_AP_EL_HIGHER (0U << MT_RW_AP_SHIFT) + +#define MT_SECURE (0U << MT_SEC_SHIFT) +#define MT_NS (1U << MT_SEC_SHIFT) + +#define MT_P_EXECUTE (0U << MT_P_EXECUTE_SHIFT) +#define MT_P_EXECUTE_NEVER (1U << MT_P_EXECUTE_SHIFT) + +#define MT_U_EXECUTE (0U << MT_U_EXECUTE_SHIFT) +#define MT_U_EXECUTE_NEVER (1U << MT_U_EXECUTE_SHIFT) + +#define MT_NO_OVERWRITE (1U << MT_NO_OVERWRITE_SHIFT) + +#define MT_P_RW_U_RW (MT_RW | MT_RW_AP_ELx | MT_P_EXECUTE_NEVER | MT_U_EXECUTE_NEVER) +#define MT_P_RW_U_NA (MT_RW | MT_RW_AP_EL_HIGHER | MT_P_EXECUTE_NEVER | MT_U_EXECUTE_NEVER) +#define MT_P_RO_U_RO (MT_RO | MT_RW_AP_ELx | MT_P_EXECUTE_NEVER | MT_U_EXECUTE_NEVER) +#define MT_P_RO_U_NA (MT_RO | MT_RW_AP_EL_HIGHER | MT_P_EXECUTE_NEVER | MT_U_EXECUTE_NEVER) +#define MT_P_RO_U_RX (MT_RO | MT_RW_AP_ELx | MT_P_EXECUTE_NEVER | MT_U_EXECUTE) +#define MT_P_RX_U_RX (MT_RO | MT_RW_AP_ELx | MT_P_EXECUTE | MT_U_EXECUTE) +#define MT_P_RX_U_NA (MT_RO | MT_RW_AP_EL_HIGHER | MT_P_EXECUTE | MT_U_EXECUTE_NEVER) + +#ifdef CONFIG_ARMV8_A_NS +#define MT_DEFAULT_SECURE_STATE MT_NS +#else +#define MT_DEFAULT_SECURE_STATE MT_SECURE +#endif +#ifndef CONFIG_ARM64_PA_BITS +#define CONFIG_ARM64_PA_BITS 48 +#endif +#ifndef CONFIG_ARM64_VA_BITS +#define CONFIG_ARM64_VA_BITS 48 +#endif + +/* + * PTE descriptor can be Block descriptor or Table descriptor + * or Page descriptor. + */ +#define PTE_DESC_TYPE_MASK 3U +#define PTE_BLOCK_DESC 1U +#define PTE_TABLE_DESC 3U +#define PTE_PAGE_DESC 3U +#define PTE_INVALID_DESC 0U + +/* + * Block and Page descriptor attributes fields + */ +#define PTE_BLOCK_DESC_MEMTYPE(x) (x << 2) +#define PTE_BLOCK_DESC_NS (1ULL << 5) +#define PTE_BLOCK_DESC_AP_ELx (1ULL << 6) +#define PTE_BLOCK_DESC_AP_EL_HIGHER (0ULL << 6) +#define PTE_BLOCK_DESC_AP_RO (1ULL << 7) +#define PTE_BLOCK_DESC_AP_RW (0ULL << 7) +#define PTE_BLOCK_DESC_NON_SHARE (0ULL << 8) +#define PTE_BLOCK_DESC_OUTER_SHARE (2ULL << 8) +#define PTE_BLOCK_DESC_INNER_SHARE (3ULL << 8) +#define PTE_BLOCK_DESC_AF (1ULL << 10) +#define PTE_BLOCK_DESC_NG (1ULL << 11) +#define PTE_BLOCK_DESC_PXN (1ULL << 53) +#define PTE_BLOCK_DESC_UXN (1ULL << 54) + +/* + * TCR definitions. + */ +#define TCR_EL1_IPS_SHIFT 32U +#define TCR_EL2_PS_SHIFT 16U +#define TCR_EL3_PS_SHIFT 16U + +#define TCR_T0SZ_SHIFT 0U +#define TCR_T0SZ(x) ((64 - (x)) << TCR_T0SZ_SHIFT) + +#define TCR_IRGN_NC (0ULL << 8) +#define TCR_IRGN_WBWA (1ULL << 8) +#define TCR_IRGN_WT (2ULL << 8) +#define TCR_IRGN_WBNWA (3ULL << 8) +#define TCR_IRGN_MASK (3ULL << 8) +#define TCR_ORGN_NC (0ULL << 10) +#define TCR_ORGN_WBWA (1ULL << 10) +#define TCR_ORGN_WT (2ULL << 10) +#define TCR_ORGN_WBNWA (3ULL << 10) +#define TCR_ORGN_MASK (3ULL << 10) +#define TCR_SHARED_NON (0ULL << 12) +#define TCR_SHARED_OUTER (2ULL << 12) +#define TCR_SHARED_INNER (3ULL << 12) +#define TCR_TG0_4K (0ULL << 14) +#define TCR_TG0_64K (1ULL << 14) +#define TCR_TG0_16K (2ULL << 14) +#define TCR_EPD1_DISABLE (1ULL << 23) + +#define TCR_PS_BITS_4GB 0x0ULL +#define TCR_PS_BITS_64GB 0x1ULL +#define TCR_PS_BITS_1TB 0x2ULL +#define TCR_PS_BITS_4TB 0x3ULL +#define TCR_PS_BITS_16TB 0x4ULL +#define TCR_PS_BITS_256TB 0x5ULL + +/* Region definition data structure */ +struct ARM_MMU_region { + /* Region BasePhysical Address */ + uintptr_t base_pa; + /* Region Base Virtual Address */ + uintptr_t base_va; + /* Region size */ + size_t size; + /* Region Name */ + const char *name; + /* Region Attributes */ + uint32_t attrs; +}; + +/* MMU configuration data structure */ +struct ARM_MMU_config { + /* Number of regions */ + unsigned int num_regions; + /* Regions */ + const struct ARM_MMU_region *mmu_regions; + /* Number of OS memory regions */ + unsigned int num_os_ranges; + /* OS memory regions */ + const struct ARM_MMU_flat_range *mmu_os_ranges; +}; + +struct ARM_MMU_flat_range { + char *name; + void *start; + void *end; + uint32_t attrs; +}; + +struct ARM_MMU_ptables { + uint64_t *base_xlat_table; +}; + +/* Convenience macros to represent the ARMv8-A-specific + * configuration for memory access permission and + * cache-ability attribution. + */ + +#define MMU_REGION_ENTRY(_name, _base_pa, _base_va, _size, _attrs) \ + {\ + .name = _name, \ + .base_pa = _base_pa, \ + .base_va = _base_va, \ + .size = _size, \ + .attrs = _attrs, \ + } + +#define MMU_REGION_FLAT_ENTRY(name, adr, sz, attrs) \ + MMU_REGION_ENTRY(name, adr, adr, sz, attrs) + +void ARM_MMU_Initialize(const struct ARM_MMU_config *MMU_config, bool is_primary_core); +int ARM_MMU_AddMap(const char *name, uintptr_t phys, uintptr_t virt, size_t size, uint32_t attrs); +void ARM_MMU_InvalidateTLB(void); + +#ifdef __cplusplus +} +#endif + +#endif /* __MMU_ARMV8A_H */ diff --git a/bsp/nxp/imx/imx91/drivers/sdk/CMSIS/Core_AArch64/Include/timer_armv8a.h b/bsp/nxp/imx/imx91/drivers/sdk/CMSIS/Core_AArch64/Include/timer_armv8a.h new file mode 100644 index 00000000000..4ea2ef53942 --- /dev/null +++ b/bsp/nxp/imx/imx91/drivers/sdk/CMSIS/Core_AArch64/Include/timer_armv8a.h @@ -0,0 +1,145 @@ +/**************************************************************************//** + * @file timer_armv8a.h + * @brief CMSIS Cortex-Axx Generic Timer API header file + * @version V1.0.0 + * @date 05. october 2021 + ******************************************************************************/ +/* + * Copyright (c) 2021 Arm Limited. All rights reserved. + * Copyright 2021-2022 NXP + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __TIMER_ARMV8A_H +#define __TIMER_ARMV8A_H + +#ifdef __cplusplus + extern "C" { +#endif + +/******************************************************************************* + * Timer Data Types + ******************************************************************************/ + +/** \brief ARMv8-A Generic Timer types */ +typedef enum _ARM_TIMER_TYPE { + ARM_TIMER_PHYSICAL, /** Physical Timer */ + ARM_TIMER_VIRTUAL, /** Virtual Timer */ + ARM_TIMER_HYPERVISOR_PHYSICAL, /** Hypervisor Physical Timer */ + ARM_TIMER_PHYSICAL_SECURE, /** Physical Secure Timer */ +} ARM_TIMER_type_t; + + +/******************************************************************************* + * Timer Functions + ******************************************************************************/ + +__STATIC_INLINE void ARM_TIMER_Initialize(ARM_TIMER_type_t timer) +{ +} + +__STATIC_INLINE void ARM_TIMER_GetFreq(uint32_t *pVal) +{ + __MRS(CNTFRQ_EL0, pVal); +} + +__STATIC_INLINE void ARM_TIMER_SetInterval(ARM_TIMER_type_t timer, uint32_t val) +{ + switch (timer) { + case ARM_TIMER_PHYSICAL: + __MSR(CNTP_TVAL_EL0, val); + break; + case ARM_TIMER_VIRTUAL: + __MSR(CNTV_TVAL_EL0, val); + break; + case ARM_TIMER_HYPERVISOR_PHYSICAL: + __MSR(CNTHP_TVAL_EL2, val); + break; + case ARM_TIMER_PHYSICAL_SECURE: + __MSR(CNTPS_TVAL_EL1, val); + break; + default: + break; + } + + __DSB(); + __ISB(); +} + +__STATIC_INLINE void ARM_TIMER_GetCount(ARM_TIMER_type_t timer, uint32_t *val) +{ + switch (timer) { + case ARM_TIMER_PHYSICAL: + __MRS(CNTP_TVAL_EL0, val); + break; + case ARM_TIMER_VIRTUAL: + __MRS(CNTV_TVAL_EL0, val); + break; + case ARM_TIMER_HYPERVISOR_PHYSICAL: + __MRS(CNTHP_TVAL_EL2, val); + break; + case ARM_TIMER_PHYSICAL_SECURE: + __MRS(CNTPS_TVAL_EL1, val); + break; + default: + break; + } +} + +__STATIC_INLINE void ARM_TIMER_Start(ARM_TIMER_type_t timer, bool irq_enable) +{ + uint64_t ctl = 1UL << 0; + + if (!irq_enable) + ctl |= 1UL << 1; + + switch (timer) { + case ARM_TIMER_PHYSICAL: + __MSR(CNTP_CTL_EL0, ctl); + break; + case ARM_TIMER_VIRTUAL: + __MSR(CNTV_CTL_EL0, ctl); + break; + case ARM_TIMER_HYPERVISOR_PHYSICAL: + __MSR(CNTHP_CTL_EL2, ctl); + break; + case ARM_TIMER_PHYSICAL_SECURE: + __MSR(CNTPS_CTL_EL1, ctl); + break; + default: + break; + } +} + +__STATIC_FORCEINLINE void ARM_TIMER_GetCounterCount(ARM_TIMER_type_t timer, uint64_t *val) +{ + switch (timer) { + case ARM_TIMER_PHYSICAL: + __MRS(cntpct_el0, val); + break; + case ARM_TIMER_VIRTUAL: + __MRS(cntvct_el0, val); + break; + default: + break; + } +} + +#ifdef __cplusplus +} +#endif + +#endif /* __TIMER_ARMV8A_H */ diff --git a/bsp/nxp/imx/imx91/drivers/sdk/CMSIS/Core_AArch64/SConscript b/bsp/nxp/imx/imx91/drivers/sdk/CMSIS/Core_AArch64/SConscript new file mode 100644 index 00000000000..f1ba1757af9 --- /dev/null +++ b/bsp/nxp/imx/imx91/drivers/sdk/CMSIS/Core_AArch64/SConscript @@ -0,0 +1,19 @@ +# for module compiling +import os +from building import * + +cwd = GetCurrentDir() +src = Glob('*.c') + Glob('Source/*.c') + +CPPPATH = [cwd + '/Include'] +CPPDEFINES = [ + {'CPU_MIMX9131DVVXJ': 1} +] +objs = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH, CPPDEFINES = CPPDEFINES) + +for item in os.listdir(cwd): + sconsfile = os.path.join(item, 'SConscript') + if os.path.isfile(os.path.join(cwd, sconsfile)): + objs += SConscript(sconsfile) + +Return('objs') diff --git a/bsp/nxp/imx/imx91/drivers/sdk/CMSIS/Core_AArch64/Source/cache_armv8a.c b/bsp/nxp/imx/imx91/drivers/sdk/CMSIS/Core_AArch64/Source/cache_armv8a.c new file mode 100644 index 00000000000..06cedd94521 --- /dev/null +++ b/bsp/nxp/imx/imx91/drivers/sdk/CMSIS/Core_AArch64/Source/cache_armv8a.c @@ -0,0 +1,137 @@ +/**************************************************************************//** + * @file cache_armv8a.c + * @brief CMSIS AARCH64 Cache Source file + * @version V1.0.0 + * @date 21. January 2022 + ******************************************************************************/ + +/* + * Copyright 2022 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "core_ca53.h" +#include "cache_armv8a.h" + +#ifndef BIT_MASK +#define BIT_MASK(n) ((1UL << n) - 1UL) +#endif + +/* CLIDR_EL1 */ +#define CLIDR_EL1_LOC_SHIFT 24 +#define CLIDR_EL1_LOC_MASK BIT_MASK(3) +#define CLIDR_EL1_CTYPE_SHIFT(l) ((l) * 3) +#define CLIDR_EL1_CTYPE_MASK BIT_MASK(3) + +/* CCSIDR_EL1 */ +#define CCSIDR_EL1_LN_SZ_SHIFT 0 +#define CCSIDR_EL1_LN_SZ_MASK BIT_MASK(3) +#define CCSIDR_EL1_WAYS_SHIFT 3 +#define CCSIDR_EL1_WAYS_MASK BIT_MASK(10) +#define CCSIDR_EL1_SETS_SHIFT 13 +#define CCSIDR_EL1_SETS_MASK BIT_MASK(15) + +/* CSSELR_EL1 */ +#define CSSELR_EL1_LEVEL_SHIFT 1 +#define CSSELR_EL1_LEVEL_MASK BIT_MASK(3) + +enum cache_ops { + CACHE_OP_C, /* Clean */ + CACHE_OP_I, /* Invalidate */ + CACHE_OP_CI /* Clean and Invalidate */ +}; + +/* + * Operation for all data cache to PoC + * op: CACHE_OP_C: clean + * CACHE_OP_I: invalidate + * CACHE_OP_CI: clean and invalidate + */ +int dcache_all(enum cache_ops op) +{ + uint32_t clidr_el1, csselr_el1, ccsidr_el1; + uint32_t num_ways, num_sets, set, way, operand; + uint8_t loc, cache_type, cache_level, set_shift, way_shift; + + __DSB(); + + __MRS(CLIDR_EL1, &clidr_el1); + + loc = (clidr_el1 >> CLIDR_EL1_LOC_SHIFT) & CLIDR_EL1_LOC_MASK; + if (!loc) + return 0; + + for (cache_level = 0; cache_level < loc; cache_level++) { + cache_type = (clidr_el1 >> CLIDR_EL1_CTYPE_SHIFT(cache_level)) & + CLIDR_EL1_CTYPE_MASK; + /* No Data or Unified cache at this level */ + if (cache_type < 2) + continue; + + /* Select cache level and Data/Unified cache */ + csselr_el1 = (cache_level & CSSELR_EL1_LEVEL_MASK) << + CSSELR_EL1_LEVEL_SHIFT; + __MSR(CSSELR_EL1, csselr_el1); + __ISB(); + + __MRS(CCSIDR_EL1, &ccsidr_el1); + set_shift = ((ccsidr_el1 >> CCSIDR_EL1_LN_SZ_SHIFT) & + CCSIDR_EL1_LN_SZ_MASK) + 4; + num_ways = ((ccsidr_el1 >> CCSIDR_EL1_WAYS_SHIFT) & + CCSIDR_EL1_WAYS_MASK) + 1; + num_sets = ((ccsidr_el1 >> CCSIDR_EL1_SETS_SHIFT) & + CCSIDR_EL1_SETS_MASK) + 1; + /* 32-log2(ways), bit position of way in DC operand */ + way_shift = __CLZ(num_ways - 1); + + for (set = 0; set < num_sets; set++) { + for (way = 0; way < num_ways; way++) { + /* cache level, aligned to pos in DC operand */ + operand = (cache_level << 1); + /* set number, aligned to pos in DC operand */ + operand |= set << set_shift; + /* way number, aligned to pos in DC operand */ + /* No way number field for direct-mapped cache */ + if (way_shift < 32) + operand |= way << way_shift; + + switch (op) { + case CACHE_OP_C: + dcache_ops(csw, operand); + break; + case CACHE_OP_I: + dcache_ops(isw, operand); + break; + case CACHE_OP_CI: + dcache_ops(cisw, operand); + break; + default: + return -1; + } + } + } + } + + __DSB(); + + /* Restore csselr_el1 to level 0 */ + __MSR(CSSELR_EL1, 0); + __ISB(); + + return 0; +} + +void dcache_clean_all(void) +{ + dcache_all(CACHE_OP_C); +} + +void dcache_invalidate_all(void) +{ + dcache_all(CACHE_OP_I); +} +void dcache_clean_invalidate_all(void) +{ + dcache_all(CACHE_OP_CI); +} diff --git a/bsp/nxp/imx/imx91/drivers/sdk/CMSIS/Core_AArch64/Source/mmu_armv8a.c b/bsp/nxp/imx/imx91/drivers/sdk/CMSIS/Core_AArch64/Source/mmu_armv8a.c new file mode 100644 index 00000000000..fe75a4f2672 --- /dev/null +++ b/bsp/nxp/imx/imx91/drivers/sdk/CMSIS/Core_AArch64/Source/mmu_armv8a.c @@ -0,0 +1,720 @@ +/**************************************************************************//** + * @file mmu_armv8a.c + * @brief CMSIS Cortex-Axx MMU Source file + * @version V1.0.0 + * @date 20. october 2021 + ******************************************************************************/ +/* + * Copyright 2019 Broadcom + * The term "Broadcom" refers to Broadcom Inc. and/or its subsidiaries. + * Copyright (c) 2021 Arm Limited. All rights reserved. + * Copyright 2021 NXP + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include +#include + +#include "core_ca53.h" +#include "mmu_armv8a.h" + + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +#define __ASSERT(op, fmt, ...) \ + do { \ + if (!(op)) { \ + while(1) \ + /* wait here */; \ + } \ + } while (0) + +#ifndef MAX +#define MAX(a, b) (((a) > (b)) ? (a) : (b)) +#endif + +#ifndef KB +#define KB(x) ((x) << 10) +#endif + +#ifndef CONFIG_MMU_PAGE_SIZE +#define CONFIG_MMU_PAGE_SIZE 4096 +#endif +#ifndef CONFIG_MAX_XLAT_TABLES +#define CONFIG_MAX_XLAT_TABLES 32 +#endif +#ifndef CONFIG_ARM64_PA_BITS +#define CONFIG_ARM64_PA_BITS 48 +#endif +#ifndef CONFIG_ARM64_VA_BITS +#define CONFIG_ARM64_VA_BITS 48 +#endif + +#define LOG_ERR(fmt, ...) (void)(fmt) +#define ARG_UNUSED(x) (void)(x) + +#define BITS_PER_LONG (__CHAR_BIT__ * __SIZEOF_LONG__) +#define GENMASK(h, l) \ + (((~0UL) - (1UL << (l)) + 1) & (~0UL >> (BITS_PER_LONG - 1 - (h)))) + +/******************************************************************************* + * from zephyr:/arch/arm/core/aarch64/mmu/arm_mmu.h: + ******************************************************************************/ + +/* Set below flag to get debug prints */ +//#define MMU_DEBUG_PRINTS 0 + +#if defined (MMU_DEBUG_PRINTS) && (MMU_DEBUG_PRINTS == 1) +/* To dump page table entries while filling them, set DUMP_PTE macro */ +#define DUMP_PTE 0 + #define MMU_DEBUG(fmt, ...) PRINTF(fmt, ##__VA_ARGS__) +#else + #define MMU_DEBUG(...) +#endif + +/* + * 48-bit address with 4KB granule size: + * + * +------------+------------+------------+------------+-----------+ + * | VA [47:39] | VA [38:30] | VA [29:21] | VA [20:12] | VA [11:0] | + * +---------------------------------------------------------------+ + * | L0 | L1 | L2 | L3 | block off | + * +------------+------------+------------+------------+-----------+ + */ + +/* Only 4K granule is supported */ +#define PAGE_SIZE_SHIFT 12U + +/* 48-bit VA address */ +#define VA_SIZE_SHIFT_MAX 48U + +/* Maximum 4 XLAT table levels (L0 - L3) */ +#define XLAT_LAST_LEVEL 3U + +/* The VA shift of L3 depends on the granule size */ +#define L3_XLAT_VA_SIZE_SHIFT PAGE_SIZE_SHIFT + +/* Number of VA bits to assign to each table (9 bits) */ +#define Ln_XLAT_VA_SIZE_SHIFT (PAGE_SIZE_SHIFT - 3) + +/* Starting bit in the VA address for each level */ +#define L2_XLAT_VA_SIZE_SHIFT (L3_XLAT_VA_SIZE_SHIFT + Ln_XLAT_VA_SIZE_SHIFT) +#define L1_XLAT_VA_SIZE_SHIFT (L2_XLAT_VA_SIZE_SHIFT + Ln_XLAT_VA_SIZE_SHIFT) +#define L0_XLAT_VA_SIZE_SHIFT (L1_XLAT_VA_SIZE_SHIFT + Ln_XLAT_VA_SIZE_SHIFT) + +#define LEVEL_TO_VA_SIZE_SHIFT(level) \ + (PAGE_SIZE_SHIFT + (Ln_XLAT_VA_SIZE_SHIFT * \ + (XLAT_LAST_LEVEL - (level)))) + +/* Number of entries for each table (512) */ +#define Ln_XLAT_NUM_ENTRIES ((1U << PAGE_SIZE_SHIFT) / 8U) + +/* Virtual Address Index within a given translation table level */ +#define XLAT_TABLE_VA_IDX(va_addr, level) \ + ((va_addr >> LEVEL_TO_VA_SIZE_SHIFT(level)) & (Ln_XLAT_NUM_ENTRIES - 1)) + +/* + * Calculate the initial translation table level from CONFIG_ARM64_VA_BITS + * For a 4 KB page size: + * + * (va_bits <= 20) - base level 3 + * (21 <= va_bits <= 29) - base level 2 + * (30 <= va_bits <= 38) - base level 1 + * (39 <= va_bits <= 47) - base level 0 + */ +#define GET_BASE_XLAT_LEVEL(va_bits) \ + ((va_bits > L0_XLAT_VA_SIZE_SHIFT) ? 0U \ + : (va_bits > L1_XLAT_VA_SIZE_SHIFT) ? 1U \ + : (va_bits > L2_XLAT_VA_SIZE_SHIFT) ? 2U : 3U) + +/* Level for the base XLAT */ +#define BASE_XLAT_LEVEL GET_BASE_XLAT_LEVEL(CONFIG_ARM64_VA_BITS) + +#if (CONFIG_ARM64_PA_BITS == 48) +#define TCR_PS_BITS TCR_PS_BITS_256TB +#elif (CONFIG_ARM64_PA_BITS == 44) +#define TCR_PS_BITS TCR_PS_BITS_16TB +#elif (CONFIG_ARM64_PA_BITS == 42) +#define TCR_PS_BITS TCR_PS_BITS_4TB +#elif (CONFIG_ARM64_PA_BITS == 40) +#define TCR_PS_BITS TCR_PS_BITS_1TB +#elif (CONFIG_ARM64_PA_BITS == 36) +#define TCR_PS_BITS TCR_PS_BITS_64GB +#else +#define TCR_PS_BITS TCR_PS_BITS_4GB +#endif + +/* Upper and lower attributes mask for page/block descriptor */ +#define DESC_ATTRS_UPPER_MASK GENMASK(63, 51) +#define DESC_ATTRS_LOWER_MASK GENMASK(11, 2) + +#define DESC_ATTRS_MASK (DESC_ATTRS_UPPER_MASK | DESC_ATTRS_LOWER_MASK) + +/******************************************************************************/ + +static uint64_t xlat_tables[CONFIG_MAX_XLAT_TABLES * Ln_XLAT_NUM_ENTRIES] + __aligned(Ln_XLAT_NUM_ENTRIES * sizeof(uint64_t)); +static uint16_t xlat_use_count[CONFIG_MAX_XLAT_TABLES]; + +/* Returns a reference to a free table */ +static uint64_t *new_table(void) +{ + unsigned int i; + + /* Look for a free table. */ + for (i = 0; i < CONFIG_MAX_XLAT_TABLES; i++) { + if (xlat_use_count[i] == 0) { + xlat_use_count[i] = 1; + return &xlat_tables[i * Ln_XLAT_NUM_ENTRIES]; + } + } + + LOG_ERR("CONFIG_MAX_XLAT_TABLES, too small"); + return NULL; +} + +static inline unsigned int table_index(uint64_t *pte) +{ + unsigned int i = (pte - xlat_tables) / Ln_XLAT_NUM_ENTRIES; + + __ASSERT(i < CONFIG_MAX_XLAT_TABLES, "table %p out of range", pte); + return i; +} + +/* Makes a table free for reuse. */ +static void free_table(uint64_t *table) +{ + unsigned int i = table_index(table); + + MMU_DEBUG("freeing table [%d]%p\r\n", i, table); + __ASSERT(xlat_use_count[i] == 1, "table still in use"); + xlat_use_count[i] = 0; +} + +/* Adjusts usage count and returns current count. */ +static int table_usage(uint64_t *table, int adjustment) +{ + unsigned int i = table_index(table); + + xlat_use_count[i] += adjustment; + __ASSERT(xlat_use_count[i] > 0, "usage count underflow"); + return xlat_use_count[i]; +} + +static inline bool is_table_unused(uint64_t *table) +{ + return table_usage(table, 0) == 1; +} + +static inline bool is_free_desc(uint64_t desc) +{ + return (desc & PTE_DESC_TYPE_MASK) == PTE_INVALID_DESC; +} + +static inline bool is_table_desc(uint64_t desc, unsigned int level) +{ + return level != XLAT_LAST_LEVEL && + (desc & PTE_DESC_TYPE_MASK) == PTE_TABLE_DESC; +} + +static inline bool is_block_desc(uint64_t desc) +{ + return (desc & PTE_DESC_TYPE_MASK) == PTE_BLOCK_DESC; +} + +static inline uint64_t *pte_desc_table(uint64_t desc) +{ + uint64_t address = desc & GENMASK(47, PAGE_SIZE_SHIFT); + + return (uint64_t *)address; +} + +static inline bool is_desc_superset(uint64_t desc1, uint64_t desc2, + unsigned int level) +{ + uint64_t mask = DESC_ATTRS_MASK | GENMASK(47, LEVEL_TO_VA_SIZE_SHIFT(level)); + + return (desc1 & mask) == (desc2 & mask); +} + +#if DUMP_PTE +static void debug_show_pte(uint64_t *pte, unsigned int level) +{ + MMU_DEBUG("%.*s", level * 2, ". . . "); + MMU_DEBUG("[%d]%p: ", table_index(pte), pte); + + if (is_free_desc(*pte)) { + MMU_DEBUG("---\r\n"); + return; + } + + if (is_table_desc(*pte, level)) { + uint64_t *table = pte_desc_table(*pte); + + MMU_DEBUG("[Table] [%d]%p\r\n", table_index(table), table); + return; + } + + if (is_block_desc(*pte)) { + MMU_DEBUG("[Block] "); + } else { + MMU_DEBUG("[Page] "); + } + + uint8_t mem_type = (*pte >> 2) & MT_TYPE_MASK; + + MMU_DEBUG((mem_type == MT_NORMAL) ? "MEM" : + ((mem_type == MT_NORMAL_NC) ? "NC" : "DEV")); + MMU_DEBUG((*pte & PTE_BLOCK_DESC_AP_RO) ? "-RO" : "-RW"); + MMU_DEBUG((*pte & PTE_BLOCK_DESC_NS) ? "-NS" : "-S"); + MMU_DEBUG((*pte & PTE_BLOCK_DESC_AP_ELx) ? "-ELx" : "-ELh"); + MMU_DEBUG((*pte & PTE_BLOCK_DESC_PXN) ? "-PXN" : "-PX"); + MMU_DEBUG((*pte & PTE_BLOCK_DESC_UXN) ? "-UXN" : "-UX"); + MMU_DEBUG("\r\n"); +} +#else +static inline void debug_show_pte(uint64_t *pte, unsigned int level) { } +#endif + +static void set_pte_table_desc(uint64_t *pte, uint64_t *table, unsigned int level) +{ + /* Point pte to new table */ + *pte = PTE_TABLE_DESC | (uint64_t)table; + debug_show_pte(pte, level); +} + +static void set_pte_block_desc(uint64_t *pte, uint64_t desc, unsigned int level) +{ + if (desc) { + desc |= (level == XLAT_LAST_LEVEL) ? PTE_PAGE_DESC : PTE_BLOCK_DESC; + } + *pte = desc; + debug_show_pte(pte, level); +} + +static uint64_t *expand_to_table(uint64_t *pte, unsigned int level) +{ + uint64_t *table; + + __ASSERT(level < XLAT_LAST_LEVEL, "can't expand last level"); + + table = new_table(); + if (!table) { + return NULL; + } + + if (!is_free_desc(*pte)) { + /* + * If entry at current level was already populated + * then we need to reflect that in the new table. + */ + uint64_t desc = *pte; + unsigned int i, stride_shift; + + MMU_DEBUG("expanding PTE 0x%016llx into table [%d]%p\r\n", + desc, table_index(table), table); + __ASSERT(is_block_desc(desc), ""); + + if (level + 1 == XLAT_LAST_LEVEL) { + desc |= PTE_PAGE_DESC; + } + + stride_shift = LEVEL_TO_VA_SIZE_SHIFT(level + 1); + for (i = 0; i < Ln_XLAT_NUM_ENTRIES; i++) { + table[i] = desc | (i << stride_shift); + } + table_usage(table, Ln_XLAT_NUM_ENTRIES); + } else { + /* + * Adjust usage count for parent table's entry + * that will no longer be free. + */ + table_usage(pte, 1); + } + + /* Link the new table in place of the pte it replaces */ + set_pte_table_desc(pte, table, level); + table_usage(table, 1); + + return table; +} + +static int set_mapping(struct ARM_MMU_ptables *ptables, + uintptr_t virt, size_t size, + uint64_t desc, bool may_overwrite) +{ + uint64_t *pte, *ptes[XLAT_LAST_LEVEL + 1]; + uint64_t level_size; + uint64_t *table = ptables->base_xlat_table; + unsigned int level = BASE_XLAT_LEVEL; + int ret = 0; + + while (size) { + __ASSERT(level <= XLAT_LAST_LEVEL, + "max translation table level exceeded\r\n"); + + /* Locate PTE for given virtual address and page table level */ + pte = &table[XLAT_TABLE_VA_IDX(virt, level)]; + ptes[level] = pte; + + if (is_table_desc(*pte, level)) { + /* Move to the next translation table level */ + level++; + table = pte_desc_table(*pte); + continue; + } + + if (!may_overwrite && !is_free_desc(*pte)) { + /* the entry is already allocated */ + LOG_ERR("entry already in use: " + "level %d pte %p *pte 0x%016llx", + level, pte, *pte); + ret = -1; + break; + } + + level_size = 1ULL << LEVEL_TO_VA_SIZE_SHIFT(level); + + if (is_desc_superset(*pte, desc, level)) { + /* This block already covers our range */ + level_size -= (virt & (level_size - 1)); + if (level_size > size) { + level_size = size; + } + goto move_on; + } + + if ((size < level_size) || (virt & (level_size - 1))) { + /* Range doesn't fit, create subtable */ + table = expand_to_table(pte, level); + if (!table) { + ret = -1; + break; + } + level++; + continue; + } + + /* Adjust usage count for corresponding table */ + if (is_free_desc(*pte)) { + table_usage(pte, 1); + } + if (!desc) { + table_usage(pte, -1); + } + /* Create (or erase) block/page descriptor */ + set_pte_block_desc(pte, desc, level); + + /* recursively free unused tables if any */ + while (level != BASE_XLAT_LEVEL && + is_table_unused(pte)) { + free_table(pte); + pte = ptes[--level]; + set_pte_block_desc(pte, 0, level); + table_usage(pte, -1); + } + +move_on: + virt += level_size; + desc += desc ? level_size : 0; + size -= level_size; + + /* Range is mapped, start again for next range */ + table = ptables->base_xlat_table; + level = BASE_XLAT_LEVEL; + } + + return ret; +} + +static uint64_t get_region_desc(uint32_t attrs) +{ + unsigned int mem_type; + uint64_t desc = 0; + + /* NS bit for security memory access from secure state */ + desc |= (attrs & MT_NS) ? PTE_BLOCK_DESC_NS : 0; + + /* + * AP bits for EL0 / ELh Data access permission + * + * AP[2:1] ELh EL0 + * +--------------------+ + * 00 RW NA + * 01 RW RW + * 10 RO NA + * 11 RO RO + */ + + /* AP bits for Data access permission */ + desc |= (attrs & MT_RW) ? PTE_BLOCK_DESC_AP_RW : PTE_BLOCK_DESC_AP_RO; + + /* Mirror permissions to EL0 */ + desc |= (attrs & MT_RW_AP_ELx) ? + PTE_BLOCK_DESC_AP_ELx : PTE_BLOCK_DESC_AP_EL_HIGHER; + + /* the access flag */ + desc |= PTE_BLOCK_DESC_AF; + + /* memory attribute index field */ + mem_type = MT_TYPE(attrs); + desc |= PTE_BLOCK_DESC_MEMTYPE(mem_type); + + switch (mem_type) { + case MT_DEVICE_nGnRnE: + case MT_DEVICE_nGnRE: + case MT_DEVICE_GRE: + /* Access to Device memory and non-cacheable memory are coherent + * for all observers in the system and are treated as + * Outer shareable, so, for these 2 types of memory, + * it is not strictly needed to set shareability field + */ + desc |= PTE_BLOCK_DESC_OUTER_SHARE; + /* Map device memory as execute-never */ + desc |= PTE_BLOCK_DESC_PXN; + desc |= PTE_BLOCK_DESC_UXN; + break; + case MT_NORMAL_NC: + case MT_NORMAL: + /* Make Normal RW memory as execute never */ + if ((attrs & MT_RW) || (attrs & MT_P_EXECUTE_NEVER)) + desc |= PTE_BLOCK_DESC_PXN; + + if (((attrs & MT_RW) && (attrs & MT_RW_AP_ELx)) || + (attrs & MT_U_EXECUTE_NEVER)) + desc |= PTE_BLOCK_DESC_UXN; + + if (mem_type == MT_NORMAL) + desc |= PTE_BLOCK_DESC_INNER_SHARE; + else + desc |= PTE_BLOCK_DESC_OUTER_SHARE; + break; + default: + break; + } + + return desc; +} + +static int add_map(struct ARM_MMU_ptables *ptables, const char *name, + uintptr_t phys, uintptr_t virt, size_t size, uint32_t attrs) +{ + uint64_t desc = get_region_desc(attrs); + bool may_overwrite = !(attrs & MT_NO_OVERWRITE); + + MMU_DEBUG("mmap [%s]: virt %lx phys %lx size %lx attr %llx\r\n", + name, virt, phys, size, desc); + __ASSERT(((virt | phys | size) & (CONFIG_MMU_PAGE_SIZE - 1)) == 0, + "address/size are not page aligned\r\n"); + desc |= phys; + return set_mapping(ptables, virt, size, desc, may_overwrite); +} + +/* OS execution regions with appropriate attributes */ + +static inline void add_ARM_MMU_flat_range(struct ARM_MMU_ptables *ptables, + const struct ARM_MMU_flat_range *range, + uint32_t extra_flags) +{ + uintptr_t address = (uintptr_t)range->start; + size_t size = (uintptr_t)range->end - address; + + if (size) { + add_map(ptables, range->name, address, address, + size, range->attrs | extra_flags); + } +} + +static inline void add_ARM_MMU_region(struct ARM_MMU_ptables *ptables, + const struct ARM_MMU_region *region, + uint32_t extra_flags) +{ + if (region->size || region->attrs) { + add_map(ptables, region->name, region->base_pa, region->base_va, + region->size, region->attrs | extra_flags); + } +} + +static void setup_page_tables(const struct ARM_MMU_config *MMU_config, + struct ARM_MMU_ptables *ptables) +{ + unsigned int index; + const struct ARM_MMU_flat_range *range; + const struct ARM_MMU_region *region; + uintptr_t max_va = 0, max_pa = 0; + + MMU_DEBUG("xlat tables:\r\n"); + for (index = 0; index < CONFIG_MAX_XLAT_TABLES; index++) + MMU_DEBUG("%d: %p\r\n", index, xlat_tables + index * Ln_XLAT_NUM_ENTRIES); + + for (index = 0; index < MMU_config->num_regions; index++) { + region = &MMU_config->mmu_regions[index]; + max_va = MAX(max_va, region->base_va + region->size); + max_pa = MAX(max_pa, region->base_pa + region->size); + } + + __ASSERT(max_va <= (1ULL << CONFIG_ARM64_VA_BITS), + "Maximum VA not supported\r\n"); + __ASSERT(max_pa <= (1ULL << CONFIG_ARM64_PA_BITS), + "Maximum PA not supported\r\n"); + + /* setup translation table for OS execution regions */ + for (index = 0; index < MMU_config->num_os_ranges; index++) { + range = &MMU_config->mmu_os_ranges[index]; + add_ARM_MMU_flat_range(ptables, range, 0); + } + + /* + * Create translation tables for user provided platform regions. + * Those must not conflict with our default mapping. + */ + for (index = 0; index < MMU_config->num_regions; index++) { + region = &MMU_config->mmu_regions[index]; + add_ARM_MMU_region(ptables, region, MT_NO_OVERWRITE); + } + + ARM_MMU_InvalidateTLB(); +} + +/* Translation table control register settings */ +static uint64_t get_tcr(int el) +{ + uint64_t tcr; + uint64_t va_bits = CONFIG_ARM64_VA_BITS; + uint64_t tcr_ps_bits; + + tcr_ps_bits = TCR_PS_BITS; + + if (el == 1) { + tcr = (tcr_ps_bits << TCR_EL1_IPS_SHIFT); + /* + * TCR_EL1.EPD1: Disable translation table walk for addresses + * that are translated using TTBR1_EL1. + */ + tcr |= TCR_EPD1_DISABLE; + } else + tcr = (tcr_ps_bits << TCR_EL3_PS_SHIFT); + + tcr |= TCR_T0SZ(va_bits); + /* + * Translation table walk is cacheable, inner/outer WBWA + */ + tcr |= TCR_TG0_4K | TCR_ORGN_WBWA | TCR_IRGN_WBWA; + + return tcr; +} + +static void enable_mmu_el1(struct ARM_MMU_ptables *ptables, unsigned int flags) +{ + ARG_UNUSED(flags); + uint64_t val; + + /* Set MAIR, TCR and TBBR registers */ + __MSR(MAIR_EL1, MEMORY_ATTRIBUTES); + __MSR(TCR_EL1, get_tcr(1)); + __MSR(TTBR0_EL1, (uint64_t)ptables->base_xlat_table); + + /* Ensure these changes are seen before MMU is enabled */ + __ISB(); + + /* Enable the MMU and caches */ + __MRS(SCTLR_EL1, &val); + __MSR(SCTLR_EL1, val | SCTLR_M_BIT | SCTLR_C_BIT | SCTLR_I_BIT); + + /* Ensure the MMU enable takes effect immediately */ + __ISB(); + + MMU_DEBUG("MMU enabled with caches\r\n"); +} + +/* ARM MMU Driver Initial Setup */ + +static struct ARM_MMU_ptables kernel_ptables; + +/* + * @brief MMU default configuration + * + * This function provides the default configuration mechanism for the Memory + * Management Unit (MMU). + */ +void ARM_MMU_Initialize(const struct ARM_MMU_config *MMU_config, + bool is_primary_core) +{ + unsigned int flags = 0; + uint64_t val; + + __ASSERT(CONFIG_MMU_PAGE_SIZE == KB(4), + "Only 4K page size is supported\r\n"); + + __MRS(CURRENTEL, &val); + __ASSERT(GET_EL(val) == MODE_EL1, + "Exception level not EL1, MMU not enabled!\r\n"); + + /* Ensure that MMU is already not enabled */ + __MRS(SCTLR_EL1, &val); + __ASSERT((val & SCTLR_M_BIT) == 0, "MMU is already enabled\r\n"); + + /* + * Only booting core setup up the page tables. + */ + if (is_primary_core) { + kernel_ptables.base_xlat_table = new_table(); + setup_page_tables(MMU_config, &kernel_ptables); + } + + /* currently only EL1 is supported */ + enable_mmu_el1(&kernel_ptables, flags); +} + +/* + * @brief MMU mapping setup + * + * This function sets a new MMU region mapping + */ +int ARM_MMU_AddMap(const char *name, uintptr_t phys, uintptr_t virt, size_t size, uint32_t attrs) +{ + int ret = -1; + + if ((virt + size) > (1ULL << CONFIG_ARM64_VA_BITS)) + goto exit; + + if ((phys + size) > (1ULL << CONFIG_ARM64_PA_BITS)) + goto exit; + + if (size) { + ret = add_map(&kernel_ptables, name, phys, virt, size, attrs); + + ARM_MMU_InvalidateTLB(); + } + +exit: + return ret; +} + +/* + * @brief MMU TLB invalidation + * + * This function invalidates the entire unified TLB + */ +void ARM_MMU_InvalidateTLB(void) +{ + __DSB(); + __ASM volatile("tlbi vmalle1"); + __DSB(); + __ISB(); +} diff --git a/bsp/nxp/imx/imx91/drivers/sdk/CMSIS/SConscript b/bsp/nxp/imx/imx91/drivers/sdk/CMSIS/SConscript new file mode 100644 index 00000000000..d6dd3c32356 --- /dev/null +++ b/bsp/nxp/imx/imx91/drivers/sdk/CMSIS/SConscript @@ -0,0 +1,13 @@ +# for module compiling +import os +from building import * + +cwd = GetCurrentDir() +objs = [] + +for item in os.listdir(cwd): + sconsfile = os.path.join(item, 'SConscript') + if os.path.isfile(os.path.join(cwd, sconsfile)): + objs += SConscript(sconsfile) + +Return('objs') diff --git a/bsp/nxp/imx/imx91/drivers/sdk/SConscript b/bsp/nxp/imx/imx91/drivers/sdk/SConscript new file mode 100644 index 00000000000..d6dd3c32356 --- /dev/null +++ b/bsp/nxp/imx/imx91/drivers/sdk/SConscript @@ -0,0 +1,13 @@ +# for module compiling +import os +from building import * + +cwd = GetCurrentDir() +objs = [] + +for item in os.listdir(cwd): + sconsfile = os.path.join(item, 'SConscript') + if os.path.isfile(os.path.join(cwd, sconsfile)): + objs += SConscript(sconsfile) + +Return('objs') diff --git a/bsp/nxp/imx/imx91/drivers/sdk/devices/MIMX9131/MIMX9131.c b/bsp/nxp/imx/imx91/drivers/sdk/devices/MIMX9131/MIMX9131.c new file mode 100644 index 00000000000..3e8ee8ce918 --- /dev/null +++ b/bsp/nxp/imx/imx91/drivers/sdk/devices/MIMX9131/MIMX9131.c @@ -0,0 +1,24 @@ +/* + * Copyright (c) 2006-2025, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2025-08-10 Siwei Xu Add i.MX91 SDK + * 2025-09-15 Siwei Xu Fix LPUART driver + * 2025-10-08 Siwei Xu Fix MMU Enable issues + */ + +#include "MIMX9131.h" + +CCM_Type* CCM_CTRL = (CCM_Type *)CCM_CTRL_BASE; + +LPUART_Type* LPUART1 = (LPUART_Type *)LPUART1_BASE; +LPUART_Type* LPUART2 = (LPUART_Type *)LPUART2_BASE; +LPUART_Type* LPUART3 = (LPUART_Type *)LPUART3_BASE; +LPUART_Type* LPUART4 = (LPUART_Type *)LPUART4_BASE; +LPUART_Type* LPUART5 = (LPUART_Type *)LPUART5_BASE; +LPUART_Type* LPUART6 = (LPUART_Type *)LPUART6_BASE; +LPUART_Type* LPUART7 = (LPUART_Type *)LPUART7_BASE; +LPUART_Type* LPUART8 = (LPUART_Type *)LPUART8_BASE; diff --git a/bsp/nxp/imx/imx91/drivers/sdk/devices/MIMX9131/MIMX9131.h b/bsp/nxp/imx/imx91/drivers/sdk/devices/MIMX9131/MIMX9131.h new file mode 100644 index 00000000000..d9632dd7f53 --- /dev/null +++ b/bsp/nxp/imx/imx91/drivers/sdk/devices/MIMX9131/MIMX9131.h @@ -0,0 +1,138365 @@ +/* +** ################################################################### +** Processors: MIMX9131CVVXJ +** MIMX9131DVVXJ +** +** Compilers: GNU C Compiler +** IAR ANSI C/C++ Compiler for ARM +** Keil ARM C/C++ Compiler +** +** Reference manual: IMX91RM Rev.1 +** Version: rev. 1.0, 2024-11-15 +** Build: b250112 +** +** Abstract: +** CMSIS Peripheral Access Layer for MIMX9131 +** +** Copyright 1997-2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2024-11-15) +** Initial version. +** +** ################################################################### +*/ + +/*! + * @file MIMX9131.h + * @version 1.0 + * @date 2024-11-15 + * @brief CMSIS Peripheral Access Layer for MIMX9131 + * + * CMSIS Peripheral Access Layer for MIMX9131 + */ + +#if !defined(MIMX9131_H_) +#define MIMX9131_H_ /**< Symbol preventing repeated inclusion */ + +/** Memory map major version (memory maps with equal major version number are + * compatible) */ +#define MCU_MEM_MAP_VERSION 0x0100U +/** Memory map minor version */ +#define MCU_MEM_MAP_VERSION_MINOR 0x0000U + + +/* ---------------------------------------------------------------------------- + -- Interrupt vector numbers + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Interrupt_vector_numbers Interrupt vector numbers + * @{ + */ + +/** Interrupt Number Definitions */ +#define NUMBER_OF_INT_VECTORS 300 /**< Number of interrupts in the Vector table */ + +typedef enum IRQn { + /* Auxiliary constants */ + NotAvail_IRQn = -128, /**< Not available device specific interrupt */ + + /* Core interrupts */ + Software0_IRQn = 0, /**< Cortex-A55 Software Generated Interrupt 0 */ + Software1_IRQn = 1, /**< Cortex-A55 Software Generated Interrupt 1 */ + Software2_IRQn = 2, /**< Cortex-A55 Software Generated Interrupt 2 */ + Software3_IRQn = 3, /**< Cortex-A55 Software Generated Interrupt 3 */ + Software4_IRQn = 4, /**< Cortex-A55 Software Generated Interrupt 4 */ + Software5_IRQn = 5, /**< Cortex-A55 Software Generated Interrupt 5 */ + Software6_IRQn = 6, /**< Cortex-A55 Software Generated Interrupt 6 */ + Software7_IRQn = 7, /**< Cortex-A55 Software Generated Interrupt 7 */ + Software8_IRQn = 8, /**< Cortex-A55 Software Generated Interrupt 8 */ + Software9_IRQn = 9, /**< Cortex-A55 Software Generated Interrupt 9 */ + Software10_IRQn = 10, /**< Cortex-A55 Software Generated Interrupt 10 */ + Software11_IRQn = 11, /**< Cortex-A55 Software Generated Interrupt 11 */ + Software12_IRQn = 12, /**< Cortex-A55 Software Generated Interrupt 12 */ + Software13_IRQn = 13, /**< Cortex-A55 Software Generated Interrupt 13 */ + Software14_IRQn = 14, /**< Cortex-A55 Software Generated Interrupt 14 */ + Software15_IRQn = 15, /**< Cortex-A55 Software Generated Interrupt 15 */ + VirtualMaintenance_IRQn = 25, /**< Cortex-A55 Virtual Maintenance Interrupt */ + HypervisorTimer_IRQn = 26, /**< Cortex-A55 Hypervisor Timer Interrupt */ + VirtualTimer_IRQn = 27, /**< Cortex-A55 Virtual Timer Interrupt */ + LegacyFastInt_IRQn = 28, /**< Cortex-A55 Legacy nFIQ signal Interrupt */ + SecurePhyTimer_IRQn = 29, /**< Cortex-A55 Secure Physical Timer Interrupt */ + NonSecurePhyTimer_IRQn = 30, /**< Cortex-A55 Non-secure Physical Timer Interrupt */ + LegacyIRQ_IRQn = 31, /**< Cortex-A55 Legacy nIRQ Interrupt */ + + /* Device specific interrupts */ + Reserved32_IRQn = 32, /**< Reserved interrupt */ + DAP_IRQn = 33, /**< DAP interrupt */ + Reserved34_IRQn = 34, /**< Reserved interrupt */ + Reserved35_IRQn = 35, /**< Reserved interrupt */ + CTI_CA55_IRQn = 36, /**< CTI trigger outputs from CA55 platform */ + PMU_IRQn = 37, /**< Performance Unit Interrupts from CA55 platform */ + CACHE_ECC_ERR_IRQn = 38, /**< ECC error from CA55 platform cache */ + CACHE_ECC_PARITY_ERR_IRQn = 39, /**< 1-bit or 2-bit ECC or Parity error from CA55 platform cache */ + CAN1_IRQn = 40, /**< CAN1 interrupt */ + CAN1_ERROR_IRQn = 41, /**< CAN1 error interrupt */ + GPIO1_0_IRQn = 42, /**< General Purpose Input/Output 1 interrupt 0 */ + GPIO1_1_IRQn = 43, /**< General Purpose Input/Output 1 interrupt 1 */ + I3C1_IRQn = 44, /**< Improved Inter-Integrated Circuit 1 interrupt */ + LPI2C1_IRQn = 45, /**< Low Power Inter-Integrated Circuit module 1 */ + LPI2C2_IRQn = 46, /**< Low Power Inter-Integrated Circuit module 2 */ + LPIT1_IRQn = 47, /**< Low Power Periodic Interrupt Timer 1 */ + LPSPI1_IRQn = 48, /**< Low Power Serial Peripheral Interface 1 */ + LPSPI2_IRQn = 49, /**< Low Power Serial Peripheral Interface 2 */ + LPTMR1_IRQn = 50, /**< Low Power Timer 1 */ + LPUART1_IRQn = 51, /**< Low Power UART 1 */ + LPUART2_IRQn = 52, /**< Low Power UART 2 */ + Reserved53_IRQn = 53, /**< Reserved interrupt */ + Reserved54_IRQn = 54, /**< Reserved interrupt */ + Reserved55_IRQn = 55, /**< Reserved interrupt */ + Reserved56_IRQn = 56, /**< Reserved interrupt */ + Reserved57_IRQn = 57, /**< Reserved interrupt */ + Reserved58_IRQn = 58, /**< Reserved interrupt */ + Reserved59_IRQn = 59, /**< Reserved interrupt */ + EDGELOCK_TRUST_MUA_RX_IRQn = 60, /**< Edgelock Trust MUA RX full interrupt */ + EDGELOCK_TRUST_MUA_TX_IRQn = 61, /**< Edgelock Trust MUA TX empty interrupt */ + EDGELOCK_APP_MUA_RX_IRQn = 62, /**< Edgelock Apps Core MUA RX full interrupt */ + EDGELOCK_APP_MUA_TX_IRQn = 63, /**< Edgelock Apps Core MUA TX empty interrupt */ + EDGELOCK_RT_MUA_RX_IRQn = 64, /**< Edgelock Realtime Core MUA RX full interrupt */ + EDGELOCK_RT_MUA_TX_IRQn = 65, /**< Edgelock Realtime Core MUA TX empty interrupt */ + EDGELOCK_SECURE_IRQn = 66, /**< Edgelock secure interrupt */ + EDGELOCK_NONSECURE_IRQn = 67, /**< Edgelock non-secure interrupt */ + TPM1_IRQn = 68, /**< Timer PWM module 1 */ + TPM2_IRQn = 69, /**< Timer PWM module 2 */ + WDOG1_IRQn = 70, /**< Watchdog 1 Interrupt */ + WDOG2_IRQn = 71, /**< Watchdog 2 Interrupt */ + TRDC_IRQn = 72, /**< AONMIX TRDC transfer error interrupt */ + Reserved73_IRQn = 73, /**< Reserved interrupt */ + Reserved74_IRQn = 74, /**< Reserved interrupt */ + Reserved75_IRQn = 75, /**< Reserved interrupt */ + Reserved76_IRQn = 76, /**< Reserved interrupt */ + SAI1_IRQn = 77, /**< Serial Audio Interface 1 */ + Reserved78_IRQn = 78, /**< Reserved interrupt */ + Reserved79_IRQn = 79, /**< Reserved interrupt */ + Reserved80_IRQn = 80, /**< Reserved interrupt */ + Reserved81_IRQn = 81, /**< Reserved interrupt */ + Reserved82_IRQn = 82, /**< Reserved interrupt */ + CAN2_IRQn = 83, /**< CAN2 interrupt */ + CAN2_ERROR_IRQn = 84, /**< CAN2 error interrupt */ + Reserved85_IRQn = 85, /**< Reserved interrupt */ + Reserved86_IRQn = 86, /**< Reserved interrupt */ + FlexSPI1_IRQn = 87, /**< FlexSPI controller interface interrupt 1 */ + Reserved88_IRQn = 88, /**< Reserved interrupt */ + GPIO2_0_IRQn = 89, /**< General Purpose Input/Output 2 interrupt 0 */ + GPIO2_1_IRQn = 90, /**< General Purpose Input/Output 2 interrupt 1 */ + GPIO3_0_IRQn = 91, /**< General Purpose Input/Output 3 interrupt 0 */ + GPIO3_1_IRQn = 92, /**< General Purpose Input/Output 3 interrupt 1 */ + I3C2_IRQn = 93, /**< Improved Inter-Integrated Circuit 2 interrupt */ + LPI2C3_IRQn = 94, /**< Low Power Inter-Integrated Circuit module 3 */ + LPI2C4_IRQn = 95, /**< Low Power Inter-Integrated Circuit module 4 */ + LPIT2_IRQn = 96, /**< Low Power Periodic Interrupt Timer 2 */ + LPSPI3_IRQn = 97, /**< Low Power Serial Peripheral Interface 3 */ + LPSPI4_IRQn = 98, /**< Low Power Serial Peripheral Interface 4 */ + LPTMR2_IRQn = 99, /**< Low Power Timer 2 */ + LPUART3_IRQn = 100, /**< Low Power UART 3 */ + LPUART4_IRQn = 101, /**< Low Power UART 4 */ + LPUART5_IRQn = 102, /**< Low Power UART 5 */ + LPUART6_IRQn = 103, /**< Low Power UART 6 */ + MTR_MASTER_ERR_IRQn = 104, /**< MTR Master error interrupt */ + BBNSM_NONSECURE_IRQn = 105, /**< BBNSM Non-Secure interrupt */ + SYS_CTR_COMPARE_IRQn = 106, /**< System Counter compare interrupt */ + TPM3_IRQn = 107, /**< Timer PWM module 3 */ + TPM4_IRQn = 108, /**< Timer PWM module 4 */ + TPM5_IRQn = 109, /**< Timer PWM module 5 */ + TPM6_IRQn = 110, /**< Timer PWM module 6 */ + WDOG3_IRQn = 111, /**< Watchdog 3 Interrupt */ + WDOG4_IRQn = 112, /**< Watchdog 4 Interrupt */ + WDOG5_IRQn = 113, /**< Watchdog 5 Interrupt */ + TRDC_WAKEUPMIX_ERR_IRQn = 114, /**< WAKEUPMIX TRDC transfer error interrupt */ + TEMPMON_IRQn = 115, /**< TempSensor interrupt */ + Reserved116_IRQn = 116, /**< Reserved interrupt */ + Reserved117_IRQn = 117, /**< Reserved interrupt */ + uSDHC1_IRQn = 118, /**< ultra Secure Digital Host Controller interrupt 1 */ + uSDHC2_IRQn = 119, /**< ultra Secure Digital Host Controller interrupt 2 */ + TRDC_MEGAMIX_ERR_IRQn = 120, /**< MEGAMIX TRDC transfer error interrupt */ + TRDC_NIC_WRAPPER_ERR_IRQn = 121, /**< NIC_WRAPPER TRDC transfer error interrupt */ + DRAM_PERFMON_IRQn = 122, /**< DRAM controller Performance Monitor Interrupt */ + DRAM_CRITICAL_IRQn = 123, /**< DRAM controller Critical Interrupt */ + DRAM_PHY_CRITICAL_IRQn = 124, /**< DRAM Phy Critical Interrupt */ + Reserved125_IRQn = 125, /**< Reserved interrupt */ + DMA3_ERROR_IRQn = 126, /**< eDMA1 error interrupt */ + DMA3_0_IRQn = 127, /**< eDMA1 channel 0 interrupt */ + DMA3_1_IRQn = 128, /**< eDMA1 channel 1 interrupt */ + DMA3_2_IRQn = 129, /**< eDMA1 channel 2 interrupt */ + DMA3_3_IRQn = 130, /**< eDMA1 channel 3 interrupt */ + DMA3_4_IRQn = 131, /**< eDMA1 channel 4 interrupt */ + DMA3_5_IRQn = 132, /**< eDMA1 channel 5 interrupt */ + DMA3_6_IRQn = 133, /**< eDMA1 channel 6 interrupt */ + DMA3_7_IRQn = 134, /**< eDMA1 channel 7 interrupt */ + DMA3_8_IRQn = 135, /**< eDMA1 channel 8 interrupt */ + DMA3_9_IRQn = 136, /**< eDMA1 channel 9 interrupt */ + DMA3_10_IRQn = 137, /**< eDMA1 channel 10 interrupt */ + DMA3_11_IRQn = 138, /**< eDMA1 channel 11 interrupt */ + DMA3_12_IRQn = 139, /**< eDMA1 channel 12 interrupt */ + DMA3_13_IRQn = 140, /**< eDMA1 channel 13 interrupt */ + DMA3_14_IRQn = 141, /**< eDMA1 channel 14 interrupt */ + DMA3_15_IRQn = 142, /**< eDMA1 channel 15 interrupt */ + DMA3_16_IRQn = 143, /**< eDMA1 channel 16 interrupt */ + DMA3_17_IRQn = 144, /**< eDMA1 channel 17 interrupt */ + DMA3_18_IRQn = 145, /**< eDMA1 channel 18 interrupt */ + DMA3_19_IRQn = 146, /**< eDMA1 channel 19 interrupt */ + DMA3_20_IRQn = 147, /**< eDMA1 channel 20 interrupt */ + DMA3_21_IRQn = 148, /**< eDMA1 channel 21 interrupt */ + DMA3_22_IRQn = 149, /**< eDMA1 channel 22 interrupt */ + DMA3_23_IRQn = 150, /**< eDMA1 channel 23 interrupt */ + DMA3_24_IRQn = 151, /**< eDMA1 channel 24 interrupt */ + DMA3_25_IRQn = 152, /**< eDMA1 channel 25 interrupt */ + DMA3_26_IRQn = 153, /**< eDMA1 channel 26 interrupt */ + DMA3_27_IRQn = 154, /**< eDMA1 channel 27 interrupt */ + DMA3_28_IRQn = 155, /**< eDMA1 channel 28 interrupt */ + DMA3_29_IRQn = 156, /**< eDMA1 channel 29 interrupt */ + DMA3_30_IRQn = 157, /**< eDMA1 channel 30 interrupt */ + Reserved158_IRQn = 158, /**< Reserved interrupt */ + DMA4_ERROR_IRQn = 159, /**< eDMA2 error interrupt */ + DMA4_0_1_IRQn = 160, /**< eDMA2 channel 0/1 interrupt */ + DMA4_2_3_IRQn = 161, /**< eDMA2 channel 2/3 interrupt */ + DMA4_4_5_IRQn = 162, /**< eDMA2 channel 4/5 interrupt */ + DMA4_6_7_IRQn = 163, /**< eDMA2 channel 6/7 interrupt */ + DMA4_8_9_IRQn = 164, /**< eDMA2 channel 8/9 interrupt */ + DMA4_10_11_IRQn = 165, /**< eDMA2 channel 10/11 interrupt */ + DMA4_12_13_IRQn = 166, /**< eDMA2 channel 12/13 interrupt */ + DMA4_14_15_IRQn = 167, /**< eDMA2 channel 14/15 interrupt */ + DMA4_16_17_IRQn = 168, /**< eDMA2 channel 16/17 interrupt */ + DMA4_18_19_IRQn = 169, /**< eDMA2 channel 18/19 interrupt */ + DMA4_20_21_IRQn = 170, /**< eDMA2 channel 20/21 interrupt */ + DMA4_22_23_IRQn = 171, /**< eDMA2 channel 22/23 interrupt */ + DMA4_24_25_IRQn = 172, /**< eDMA2 channel 24/25 interrupt */ + DMA4_26_27_IRQn = 173, /**< eDMA2 channel 26/27 interrupt */ + DMA4_28_29_IRQn = 174, /**< eDMA2 channel 28/29 interrupt */ + DMA4_30_31_IRQn = 175, /**< eDMA2 channel 30/31 interrupt */ + DMA4_32_33_IRQn = 176, /**< eDMA2 channel 32/33 interrupt */ + DMA4_34_35_IRQn = 177, /**< eDMA2 channel 34/35 interrupt */ + DMA4_36_37_IRQn = 178, /**< eDMA2 channel 36/37 interrupt */ + DMA4_38_39_IRQn = 179, /**< eDMA2 channel 38/39 interrupt */ + DMA4_40_41_IRQn = 180, /**< eDMA2 channel 40/41 interrupt */ + DMA4_42_43_IRQn = 181, /**< eDMA2 channel 42/43 interrupt */ + DMA4_44_45_IRQn = 182, /**< eDMA2 channel 44/45 interrupt */ + DMA4_46_47_IRQn = 183, /**< eDMA2 channel 46/47 interrupt */ + DMA4_48_49_IRQn = 184, /**< eDMA2 channel 48/49 interrupt */ + DMA4_50_51_IRQn = 185, /**< eDMA2 channel 50/51 interrupt */ + DMA4_52_53_IRQn = 186, /**< eDMA2 channel 52/53 interrupt */ + DMA4_54_55_IRQn = 187, /**< eDMA2 channel 54/55 interrupt */ + DMA4_56_57_IRQn = 188, /**< eDMA2 channel 56/57 interrupt */ + DMA4_58_59_IRQn = 189, /**< eDMA2 channel 58/59 interrupt */ + DMA4_60_61_IRQn = 190, /**< eDMA2 channel 60/61 interrupt */ + DMA4_62_63_IRQn = 191, /**< eDMA2 channel 62/63 interrupt */ + DEBUG_WAKEUP_IRQn = 192, /**< Debug Wakeup Interrupt */ + EDGELOCK_GROUP1_RST_SRC_IRQn = 193, /**< Edgelock Group 1 reset source */ + EDGELOCK_GROUP2_RST_SRC_0_IRQn = 194, /**< Edgelock Group 2 reset source */ + EDGELOCK_GROUP2_RST_SRC_1_IRQn = 195, /**< Edgelock Group 2 reset source */ + DBG_TRACE_RST_SRC_IRQn = 196, /**< JTAGSW DAP MDM-AP SRC reset source */ + JTAGC_RST_SRC_IRQn = 197, /**< JTAGC SRC reset source */ + Reserved198_IRQn = 198, /**< Reserved interrupt */ + Reserved199_IRQn = 199, /**< Reserved interrupt */ + Reserved200_IRQn = 200, /**< Reserved interrupt */ + Reserved201_IRQn = 201, /**< Reserved interrupt */ + SAI2_IRQn = 202, /**< Serial Audio Interface 2 */ + SAI3_IRQn = 203, /**< Serial Audio Interface 3 */ + ISI_IRQn = 204, /**< ISI interrupt */ + Reserved205_IRQn = 205, /**< Reserved interrupt */ + Reserved206_IRQn = 206, /**< Reserved interrupt */ + Reserved207_IRQn = 207, /**< Reserved interrupt */ + LCDIFv3_IRQn = 208, /**< LCDIF Sync Interrupt */ + Reserved209_IRQn = 209, /**< Reserved interrupt */ + Reserved210_IRQn = 210, /**< Reserved interrupt */ + ENET_MAC0_Rx_Tx_Done1_IRQn = 211, /**< MAC 0 Receive / Trasmit Frame / Buffer Done */ + ENET_MAC0_Rx_Tx_Done2_IRQn = 212, /**< MAC 0 Receive / Trasmit Frame / Buffer Done */ + ENET_IRQn = 213, /**< MAC 0 IRQ */ + ENET_1588_IRQn = 214, /**< MAC 0 1588 Timer Interrupt - synchronous */ + ENET_QOS_PMT_IRQn = 215, /**< ENET QOS PMT interrupt */ + ENET_QOS_IRQn = 216, /**< ENET QOS interrupt */ + Reserved217_IRQn = 217, /**< Reserved interrupt */ + Reserved218_IRQn = 218, /**< Reserved interrupt */ + USB1_WAKEUP_IRQn = 219, /**< USB-1 Wake-up Interrupt */ + USB2_WAKEUP_IRQn = 220, /**< USB-2 Wake-up Interrupt */ + GPIO4_0_IRQn = 221, /**< General Purpose Input/Output 4 interrupt 0 */ + GPIO4_1_IRQn = 222, /**< General Purpose Input/Output 4 interrupt 1 */ + LPSPI5_IRQn = 223, /**< Low Power Serial Peripheral Interface 5 */ + LPSPI6_IRQn = 224, /**< Low Power Serial Peripheral Interface 6 */ + LPSPI7_IRQn = 225, /**< Low Power Serial Peripheral Interface 7 */ + LPSPI8_IRQn = 226, /**< Low Power Serial Peripheral Interface 8 */ + LPI2C5_IRQn = 227, /**< Low Power Inter-Integrated Circuit module 5 */ + LPI2C6_IRQn = 228, /**< Low Power Inter-Integrated Circuit module 6 */ + LPI2C7_IRQn = 229, /**< Low Power Inter-Integrated Circuit module 7 */ + LPI2C8_IRQn = 230, /**< Low Power Inter-Integrated Circuit module 8 */ + PDM_HWVAD_ERROR_IRQn = 231, /**< PDM interrupt */ + PDM_HWVAD_EVENT_IRQn = 232, /**< PDM interrupt */ + PDM_ERROR_IRQn = 233, /**< PDM interrupt */ + PDM_EVENT_IRQn = 234, /**< PDM interrupt */ + AUDIO_XCVR_0_IRQn = 235, /**< AUDIO XCVR interrupt */ + AUDIO_XCVR_1_IRQn = 236, /**< AUDIO XCVR interrupt */ + uSDHC3_IRQn = 237, /**< ultra Secure Digital Host Controller interrupt 3 */ + OCRAM_MECC_0_IRQn = 238, /**< OCRAM MECC interrupt */ + OCRAM_MECC_1_IRQn = 239, /**< OCRAM MECC interrupt */ + TRDC_HSIOMIX_ERR_IRQn = 240, /**< HSIOMIX TRDC transfer error interrupt */ + TRDC_MEDIAMIX_ERR_IRQn = 241, /**< MEDIAMIX TRDC transfer error interrupt */ + LPUART7_IRQn = 242, /**< Low Power UART 7 */ + LPUART8_IRQn = 243, /**< Low Power UART 8 */ + Reserved244_IRQn = 244, /**< Reserved interrupt */ + SFA_IRQn = 245, /**< SFA interrupt */ + GIC600_0_IRQn = 246, /**< GIC600 INTERRUPT */ + GIC600_1_IRQn = 247, /**< GIC600 INTERRUPT */ + GIC600_2_IRQn = 248, /**< GIC600 INTERRUPT */ + ADC_ER_IRQn = 249, /**< ADC interrupt */ + ADC_WD_IRQn = 250, /**< ADC interrupt */ + ADC_EOC_IRQn = 251, /**< ADC interrupt */ + Reserved252_IRQn = 252, /**< Reserved interrupt */ + I3C1_WAKEUP_IRQn = 253, /**< I3C1 wakeup irq after double sync */ + I3C2_WAKEUP_IRQn = 254, /**< I3C2 wakeup irq after double sync */ + Reserved255_IRQn = 255, /**< Reserved interrupt */ + Reserved256_IRQn = 256, /**< Reserved interrupt */ + Reserved257_IRQn = 257, /**< Reserved interrupt */ + Reserved258_IRQn = 258, /**< Reserved interrupt */ + Reserved259_IRQn = 259, /**< Reserved interrupt */ + Reserved260_IRQn = 260, /**< Reserved interrupt */ + Reserved261_IRQn = 261, /**< Reserved interrupt */ + Reserved262_IRQn = 262, /**< Reserved interrupt */ + Reserved263_IRQn = 263, /**< Reserved interrupt */ + Reserved264_IRQn = 264, /**< Reserved interrupt */ + Reserved265_IRQn = 265, /**< Reserved interrupt */ + Reserved266_IRQn = 266, /**< Reserved interrupt */ + Reserved267_IRQn = 267, /**< Reserved interrupt */ + Reserved268_IRQn = 268, /**< Reserved interrupt */ + Reserved269_IRQn = 269, /**< Reserved interrupt */ + Reserved270_IRQn = 270, /**< Reserved interrupt */ + Reserved271_IRQn = 271, /**< Reserved interrupt */ + Reserved272_IRQn = 272, /**< Reserved interrupt */ + Reserved273_IRQn = 273, /**< Reserved interrupt */ + Reserved274_IRQn = 274, /**< Reserved interrupt */ + Reserved275_IRQn = 275, /**< Reserved interrupt */ + Reserved276_IRQn = 276, /**< Reserved interrupt */ + Reserved277_IRQn = 277, /**< Reserved interrupt */ + Reserved278_IRQn = 278, /**< Reserved interrupt */ + Reserved279_IRQn = 279, /**< Reserved interrupt */ + Reserved280_IRQn = 280, /**< Reserved interrupt */ + Reserved281_IRQn = 281, /**< Reserved interrupt */ + Reserved282_IRQn = 282, /**< Reserved interrupt */ + Reserved283_IRQn = 283, /**< Reserved interrupt */ + Reserved284_IRQn = 284, /**< Reserved interrupt */ + Reserved285_IRQn = 285, /**< Reserved interrupt */ + Reserved286_IRQn = 286, /**< Reserved interrupt */ + Reserved287_IRQn = 287, /**< Reserved interrupt */ + Reserved288_IRQn = 288, /**< Reserved interrupt */ + Reserved289_IRQn = 289, /**< Reserved interrupt */ + Reserved290_IRQn = 290, /**< Reserved interrupt */ + Reserved291_IRQn = 291, /**< Reserved interrupt */ + Reserved292_IRQn = 292, /**< Reserved interrupt */ + Reserved293_IRQn = 293, /**< Reserved interrupt */ + Reserved294_IRQn = 294, /**< Reserved interrupt */ + Reserved295_IRQn = 295, /**< Reserved interrupt */ + Reserved296_IRQn = 296, /**< Reserved interrupt */ + Reserved297_IRQn = 297, /**< Reserved interrupt */ + Reserved298_IRQn = 298, /**< Reserved interrupt */ + Reserved299_IRQn = 299 /**< Reserved interrupt */ +} IRQn_Type; + +/*! + * @} + */ /* end of group Interrupt_vector_numbers */ + + +/* ---------------------------------------------------------------------------- + -- Cortex A55 Core Configuration + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Cortex_Core_Configuration Cortex A55 Core Configuration + * @{ + */ + +#define __CA55_REV 0x0000 /**< Core revision r2p0 */ +#define __GIC_PRIO_BITS 4 /**< Number of priority bits implemented in the GIC */ +#define __FPU_PRESENT 1 /**< Defines if an FPU is present or not */ +#define __FPU_USED 1 /**< Indicates whether an FPU is used or not */ +#define __MMU_PRESENT 1 /**< MMU present or not */ +#define __TIM_PRESENT 1 /**< TIM present or not */ +#define __CACHE_PRESENT 1 /**< CACHE present or not */ +#define __GIC_PRESENT 1 /**< GIC present or not */ +#define GIC_DISTRIBUTOR_BASE 0x48000000 /**< GIC distributor base address */ +#define GIC_REDISTRIBUTOR_BASE 0x48040000 /**< GIC CPU redistributor base address */ + +#include "core_ca55.h" /* Core Peripheral Access Layer */ +#include "system_MIMX9131.h" /* Device specific configuration file */ + +/*! + * @} + */ /* end of group Cortex_Core_Configuration */ + + +/* ---------------------------------------------------------------------------- + -- Mapping Information + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Mapping_Information Mapping Information + * @{ + */ + +/** Mapping Information */ +/*! + * @addtogroup edma_request + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! + * @brief Structure for the DMA3 hardware request + * + * Defines the structure for the DMA hardware request collections. The user can configure the + * hardware request into DMAMUX to trigger the DMA transfer accordingly. The index + * of the hardware request varies according to the to SoC. + */ +typedef enum _dma3_request_source +{ + kDma3RequestMuxCAN1 = 1U, /**< CAN1 */ + kDma3RequestMuxGPIO1Request0 = 3U, /**< GPIO1 channel 0 */ + kDma3RequestMuxGPIO1Request1 = 4U, /**< GPIO1 channel 1 */ + kDma3RequestMuxI3C1ToBusRequest = 5U, /**< I3C1 To-bus Request */ + kDma3RequestMuxI3C1FromBusRequest = 6U, /**< I3C1 From-bus Request */ + kDma3RequestMuxLPI2C1Tx = 7U, /**< LPI2C1 */ + kDma3RequestMuxLPI2C1Rx = 8U, /**< LPI2C1 */ + kDma3RequestMuxLPI2C2Tx = 9U, /**< LPI2C2 */ + kDma3RequestMuxLPI2C2Rx = 10U, /**< LPI2C2 */ + kDma3RequestMuxLPSPI1Tx = 11U, /**< LPSPI1 Transmit */ + kDma3RequestMuxLPSPI1Rx = 12U, /**< LPSPI1 Receive */ + kDma3RequestMuxLPSPI2Tx = 13U, /**< LPSPI2 Transmit */ + kDma3RequestMuxLPSPI2Rx = 14U, /**< LPSPI2 Receive */ + kDma3RequestMuxLPTMR1Request = 15U, /**< LPTMR1 Request */ + kDma3RequestMuxLPUART1Tx = 16U, /**< LPUART1 Transmit */ + kDma3RequestMuxLPUART1Rx = 17U, /**< LPUART1 Receive */ + kDma3RequestMuxLPUART2Tx = 18U, /**< LPUART2 Transmit */ + kDma3RequestMuxLPUART2Rx = 19U, /**< LPUART2 Receive */ + kDma3RequestMuxEdgelockRequest = 20U, /**< Edgelock enclave DMA Request */ + kDma3RequestMuxSai1Tx = 21U, /**< SAI1 Transmit */ + kDma3RequestMuxSai1Rx = 22U, /**< SAI1 Receive */ + kDma3RequestMuxTPM1Request0Request2 = 23U, /**< TPM1 request 0 and request 2 */ + kDma3RequestMuxTPM1Request1Request3 = 24U, /**< TPM1 request 1 and request 3 */ + kDma3RequestMuxTPM1OverflowRequest = 25U, /**< TPM1 Overflow request */ + kDma3RequestMuxTPM2Request0Request2 = 26U, /**< TPM2 request 0 and request 2 */ + kDma3RequestMuxTPM2Request1Request3 = 27U, /**< TPM2 request 1 and request 3 */ + kDma3RequestMuxTPM2OverflowRequest = 28U, /**< TPM2 Overflow request */ + kDma3RequestMuxPDMRequest = 29U, /**< PDM */ + kDma3RequestMuxADC1Request = 30U, /**< ADC1 */ +} dma3_request_source_t; + +/* @} */ + +/*! + * @addtogroup edma_request + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! + * @brief Structure for the DMA4 hardware request + * + * Defines the structure for the DMA hardware request collections. The user can configure the + * hardware request into DMAMUX to trigger the DMA transfer accordingly. The index + * of the hardware request varies according to the to SoC. + */ +typedef enum _dma4_request_source +{ + kDma4RequestMuxCAN2 = 1U, /**< CAN2 */ + kDma4RequestMuxGPIO2Request0 = 2U, /**< GPIO2 channel 0 */ + kDma4RequestMuxGPIO2Request1 = 3U, /**< GPIO2 channel 1 */ + kDma4RequestMuxGPIO3Request0 = 4U, /**< GPIO3 channel 0 */ + kDma4RequestMuxGPIO3Request1 = 5U, /**< GPIO3 channel 1 */ + kDma4RequestMuxI3C2ToBusRequest = 6U, /**< I3C2 To-bus Request */ + kDma4RequestMuxI3C2FromBusRequest = 7U, /**< I3C2 From-bus Request */ + kDma4RequestMuxLPI2C3Tx = 8U, /**< LPI2C3 */ + kDma4RequestMuxLPI2C3Rx = 9U, /**< LPI2C3 */ + kDma4RequestMuxLPI2C4Tx = 10U, /**< LPI2C4 */ + kDma4RequestMuxLPI2C4Rx = 11U, /**< LPI2C4 */ + kDma4RequestMuxLPSPI3Tx = 12U, /**< LPSPI3 Transmit */ + kDma4RequestMuxLPSPI3Rx = 13U, /**< LPSPI3 Receive */ + kDma4RequestMuxLPSPI4Tx = 14U, /**< LPSPI4 Transmit */ + kDma4RequestMuxLPSPI4Rx = 15U, /**< LPSPI4 Receive */ + kDma4RequestMuxLPTMR2Request = 16U, /**< LPTMR2 Request */ + kDma4RequestMuxLPUART3Tx = 17U, /**< LPUART3 Transmit */ + kDma4RequestMuxLPUART3Rx = 18U, /**< LPUART3 Receive */ + kDma4RequestMuxLPUART4Tx = 19U, /**< LPUART4 Transmit */ + kDma4RequestMuxLPUART4Rx = 20U, /**< LPUART4 Receive */ + kDma4RequestMuxLPUART5Tx = 21U, /**< LPUART5 Transmit */ + kDma4RequestMuxLPUART5Rx = 22U, /**< LPUART5 Receive */ + kDma4RequestMuxLPUART6Tx = 23U, /**< LPUART6 Transmit */ + kDma4RequestMuxLPUART6Rx = 24U, /**< LPUART6 Receive */ + kDma4RequestMuxTPM3Request0Request2 = 25U, /**< TPM3 request 0 and request 2 */ + kDma4RequestMuxTPM3Request1Request3 = 26U, /**< TPM3 request 1 and request 3 */ + kDma4RequestMuxTPM3OverflowRequest = 27U, /**< TPM3 Overflow request */ + kDma4RequestMuxTPM4Request0Request2 = 28U, /**< TPM4 request 0 and request 2 */ + kDma4RequestMuxTPM4Request1Request3 = 29U, /**< TPM4 request 1 and request 3 */ + kDma4RequestMuxTPM4OverflowRequest = 30U, /**< TPM4 Overflow request */ + kDma4RequestMuxTPM5Request0Request2 = 31U, /**< TPM5 request 0 and request 2 */ + kDma4RequestMuxTPM5Request1Request3 = 32U, /**< TPM5 request 1 and request 3 */ + kDma4RequestMuxTPM5OverflowRequest = 33U, /**< TPM5 Overflow request */ + kDma4RequestMuxTPM6Request0Request2 = 34U, /**< TPM6 request 0 and request 2 */ + kDma4RequestMuxTPM6Request1Request3 = 35U, /**< TPM6 request 1 and request 3 */ + kDma4RequestMuxTPM6OverflowRequest = 36U, /**< TPM6 Overflow request */ + kDma4RequestMuxFlexIO1Request0 = 37U, /**< FlexIO1 Request0 */ + kDma4RequestMuxFlexIO1Request1 = 38U, /**< FlexIO1 Request1 */ + kDma4RequestMuxFlexIO1Request2 = 39U, /**< FlexIO1 Request2 */ + kDma4RequestMuxFlexIO1Request3 = 40U, /**< FlexIO1 Request3 */ + kDma4RequestMuxFlexIO1Request4 = 41U, /**< FlexIO1 Request4 */ + kDma4RequestMuxFlexIO1Request5 = 42U, /**< FlexIO1 Request5 */ + kDma4RequestMuxFlexIO1Request6 = 43U, /**< FlexIO1 Request6 */ + kDma4RequestMuxFlexIO1Request7 = 44U, /**< FlexIO1 Request7 */ + kDma4RequestMuxFlexIO2Request0 = 45U, /**< FlexIO2 Request0 */ + kDma4RequestMuxFlexIO2Request1 = 46U, /**< FlexIO2 Request1 */ + kDma4RequestMuxFlexIO2Request2 = 47U, /**< FlexIO2 Request2 */ + kDma4RequestMuxFlexIO2Request3 = 48U, /**< FlexIO2 Request3 */ + kDma4RequestMuxFlexIO2Request4 = 49U, /**< FlexIO2 Request4 */ + kDma4RequestMuxFlexIO2Request5 = 50U, /**< FlexIO2 Request5 */ + kDma4RequestMuxFlexIO2Request6 = 51U, /**< FlexIO2 Request6 */ + kDma4RequestMuxFlexIO2Request7 = 52U, /**< FlexIO2 Request7 */ + kDma4RequestMuxFlexSPI1Tx = 53U, /**< FlexSPI1 Transmit */ + kDma4RequestMuxFlexSPI1Rx = 54U, /**< FlexSPI1 Receive */ + kDma4RequestMuxSai2Tx = 58U, /**< SAI2 Transmit */ + kDma4RequestMuxSai2Rx = 59U, /**< SAI2 Receive */ + kDma4RequestMuxSai3Tx = 60U, /**< SAI3 Transmit */ + kDma4RequestMuxSai3Rx = 61U, /**< SAI3 Receive */ + kDma4RequestMuxGPIO4Request0 = 62U, /**< GPIO4 channel 0 */ + kDma4RequestMuxGPIO4Request1 = 63U, /**< GPIO4 channel 1 */ + kDma4RequestMuxSPDIFRequest = 65U, /**< SPDIF */ + kDma4RequestMuxSPDIFRequest1 = 66U, /**< SPDIF */ + kDma4RequestMuxENETRequest = 67U, /**< ENET */ + kDma4RequestMuxENETRequest1 = 68U, /**< ENET */ + kDma4RequestMuxENETRequest2 = 69U, /**< ENET */ + kDma4RequestMuxENETRequest3 = 70U, /**< ENET */ + kDma4RequestMuxLPI2C5Tx = 71U, /**< LPI2C5 */ + kDma4RequestMuxLPI2C5Rx = 72U, /**< LPI2C5 */ + kDma4RequestMuxLPI2C6Tx = 73U, /**< LPI2C6 */ + kDma4RequestMuxLPI2C6Rx = 74U, /**< LPI2C6 */ + kDma4RequestMuxLPI2C7Tx = 75U, /**< LPI2C7 */ + kDma4RequestMuxLPI2C7Rx = 76U, /**< LPI2C7 */ + kDma4RequestMuxLPI2C8Tx = 77U, /**< LPI2C8 */ + kDma4RequestMuxLPI2C8Rx = 78U, /**< LPI2C8 */ + kDma4RequestMuxLPSPI5Tx = 79U, /**< LPSPI5 Transmit */ + kDma4RequestMuxLPSPI5Rx = 80U, /**< LPSPI5 Receive */ + kDma4RequestMuxLPSPI6Tx = 81U, /**< LPSPI6 Transmit */ + kDma4RequestMuxLPSPI6Rx = 82U, /**< LPSPI6 Receive */ + kDma4RequestMuxLPSPI7Tx = 83U, /**< LPSPI7 Transmit */ + kDma4RequestMuxLPSPI7Rx = 84U, /**< LPSPI7 Receive */ + kDma4RequestMuxLPSPI8Tx = 85U, /**< LPSPI8 Transmit */ + kDma4RequestMuxLPSPI8Rx = 86U, /**< LPSPI8 Receive */ + kDma4RequestMuxLPUART7Tx = 87U, /**< LPUART7 Transmit */ + kDma4RequestMuxLPUART7Rx = 88U, /**< LPUART7 Receive */ + kDma4RequestMuxLPUART8Tx = 89U, /**< LPUART8 Transmit */ + kDma4RequestMuxLPUART8Rx = 90U, /**< LPUART8 Receive */ + kDma4RequestMuxENET_QOSRequest = 91U, /**< ENET_QOS */ + kDma4RequestMuxENET_QOSRequest1 = 92U, /**< ENET_QOS */ + kDma4RequestMuxENET_QOSRequest2 = 93U, /**< ENET_QOS */ + kDma4RequestMuxENET_QOSRequest3 = 94U, /**< ENET_QOS */ +} dma4_request_source_t; + +/* @} */ + + +/*! + * @} + */ /* end of group Mapping_Information */ + + +/* ---------------------------------------------------------------------------- + -- Device Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Peripheral_access_layer Device Peripheral Access Layer + * @{ + */ + + +/* +** Start of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #else + #pragma push + #pragma anon_unions + #endif +#elif defined(__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=extended +#else + #error Not supported compiler type +#endif + +/* ---------------------------------------------------------------------------- + -- ADC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer + * @{ + */ + +/** ADC - Register Layout Typedef */ +typedef struct { + __IO uint32_t MCR; /**< Main Configuration, offset: 0x0 */ + __IO uint32_t MSR; /**< Main Status, offset: 0x4 */ + uint8_t RESERVED_0[8]; + __IO uint32_t ISR; /**< Interrupt Status, offset: 0x10 */ + __IO uint32_t CEOCFR0; /**< Channel Pending 0, offset: 0x14 */ + __IO uint32_t CEOCFR1; /**< Channel Pending 1, offset: 0x18 */ + uint8_t RESERVED_1[4]; + __IO uint32_t IMR; /**< Interrupt Mask, offset: 0x20 */ + __IO uint32_t CIMR0; /**< Channel Interrupt Mask 0, offset: 0x24 */ + __IO uint32_t CIMR1; /**< Channel Interrupt Mask 1, offset: 0x28 */ + uint8_t RESERVED_2[4]; + __IO uint32_t WTISR; /**< Watchdog Threshold Interrupt Status, offset: 0x30 */ + __IO uint32_t WTIMR; /**< Watchdog Threshold Interrupt Mask, offset: 0x34 */ + uint8_t RESERVED_3[8]; + __IO uint32_t DMAE; /**< DMAE, offset: 0x40 */ + __IO uint32_t DMAR0; /**< DMA 0, offset: 0x44 */ + __IO uint32_t DMAR1; /**< DMA 1, offset: 0x48 */ + uint8_t RESERVED_4[20]; + __IO uint32_t THRHLR0; /**< Analog Watchdog Threshold 0, offset: 0x60 */ + __IO uint32_t THRHLR1; /**< Analog Watchdog Threshold 1, offset: 0x64 */ + __IO uint32_t THRHLR2; /**< Analog Watchdog Threshold 2, offset: 0x68 */ + __IO uint32_t THRHLR3; /**< Analog Watchdog Threshold 3, offset: 0x6C */ + uint8_t RESERVED_5[16]; + __IO uint32_t PSCR; /**< Presampling Control, offset: 0x80 */ + __IO uint32_t PSR0; /**< Presampling 0, offset: 0x84 */ + __IO uint32_t PSR1; /**< Presampling 1, offset: 0x88 */ + uint8_t RESERVED_6[8]; + __IO uint32_t CTR0; /**< Conversion Timing 0, offset: 0x94 */ + __IO uint32_t CTR1; /**< Conversion Timing 1, offset: 0x98 */ + uint8_t RESERVED_7[8]; + __IO uint32_t NCMR0; /**< Normal Conversion Mask 0, offset: 0xA4 */ + __IO uint32_t NCMR1; /**< Normal Conversion Mask 1, offset: 0xA8 */ + uint8_t RESERVED_8[8]; + __IO uint32_t JCMR0; /**< Injected Conversion Mask 0, offset: 0xB4 */ + __IO uint32_t JCMR1; /**< Injected Conversion Mask 1, offset: 0xB8 */ + uint8_t RESERVED_9[4]; + __IO uint32_t USROFSGN; /**< User OFFSET and Gain, offset: 0xC0 */ + uint8_t RESERVED_10[4]; + __IO uint32_t PDEDR; /**< Power Down Exit Delay, offset: 0xC8 */ + uint8_t RESERVED_11[52]; + __I uint32_t PCDR[8]; /**< Precision Channel n Data, array offset: 0x100, array step: 0x4 */ + uint8_t RESERVED_12[96]; + __I uint32_t ICDR[8]; /**< Internal Channel n Data, array offset: 0x180, array step: 0x4 */ + uint8_t RESERVED_13[224]; + __IO uint32_t THRHLR4; /**< Analog Watchdog Threshold 4, offset: 0x280 */ + __IO uint32_t THRHLR5; /**< Analog Watchdog Threshold 5, offset: 0x284 */ + __IO uint32_t THRHLR6; /**< Analog Watchdog Threshold 6, offset: 0x288 */ + __IO uint32_t THRHLR7; /**< Analog Watchdog Threshold 7, offset: 0x28C */ + uint8_t RESERVED_14[32]; + __IO uint32_t CWSELR0; /**< Channel Watchdog Select 0, offset: 0x2B0 */ + uint8_t RESERVED_15[12]; + __IO uint32_t CWSELR4; /**< Channel Watchdog Select 4, offset: 0x2C0 */ + uint8_t RESERVED_16[28]; + __IO uint32_t CWENR0; /**< Channel Watchdog Enable 0, offset: 0x2E0 */ + __IO uint32_t CWENR1; /**< Channel Watchdog Enable 1, offset: 0x2E4 */ + uint8_t RESERVED_17[8]; + __IO uint32_t AWORR0; /**< Analog Watchdog Out of Range 0, offset: 0x2F0 */ + __IO uint32_t AWORR1; /**< Analog Watchdog Out of Range 1, offset: 0x2F4 */ + uint8_t RESERVED_18[72]; + __IO uint32_t STCR1; /**< Self-Test Configuration 1, offset: 0x340 */ + __IO uint32_t STCR2; /**< Self-Test Configuration 2, offset: 0x344 */ + __IO uint32_t STCR3; /**< Self-Test Configuration 3, offset: 0x348 */ + __IO uint32_t STBRR; /**< Self-Test Baud Rate, offset: 0x34C */ + __IO uint32_t STSR1; /**< Self-Test Status 1, offset: 0x350 */ + __I uint32_t STSR2; /**< Self-Test Status 2, offset: 0x354 */ + __I uint32_t STSR3; /**< Self-Test Status 3, offset: 0x358 */ + __I uint32_t STSR4; /**< Self-Test Status 4, offset: 0x35C */ + uint8_t RESERVED_19[16]; + __I uint32_t STDR1; /**< Self-Test Data 1, offset: 0x370 */ + __I uint32_t STDR2; /**< Self-Test Data 2, offset: 0x374 */ + uint8_t RESERVED_20[8]; + __IO uint32_t STAW0R; /**< Self-Test Analog Watchdog 0, offset: 0x380 */ + __IO uint32_t STAW1AR; /**< Self-Test Analog Watchdog 1A, offset: 0x384 */ + __IO uint32_t STAW1BR; /**< Self-Test Analog Watchdog 1B, offset: 0x388 */ + __IO uint32_t STAW2R; /**< Self-Test Analog Watchdog 2, offset: 0x38C */ + uint32_t STAW3R; /**< Self-Test Analog Watchdog 3, offset: 0x390 */ + __IO uint32_t STAW4R; /**< Self-Test Analog Watchdog 4, offset: 0x394 */ + __IO uint32_t STAW5R; /**< Self-Test Analog Watchdog 5, offset: 0x398 */ + __I uint32_t CALSTAT; /**< Calibration Status, offset: 0x39C */ +} ADC_Type; + +/* ---------------------------------------------------------------------------- + -- ADC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ADC_Register_Masks ADC Register Masks + * @{ + */ + +/*! @name MCR - Main Configuration */ +/*! @{ */ + +#define ADC_MCR_PWDN_MASK (0x1U) +#define ADC_MCR_PWDN_SHIFT (0U) +/*! PWDN - Power-Down Enable + * 0b0..When ADC status is in Power-down mode (MSR[ADCSTATUS] = 001b), start ADC transition to IDLE mode + * 0b1..Request to enter Power-down mode + */ +#define ADC_MCR_PWDN(x) (((uint32_t)(((uint32_t)(x)) << ADC_MCR_PWDN_SHIFT)) & ADC_MCR_PWDN_MASK) + +#define ADC_MCR_ACKO_MASK (0x20U) +#define ADC_MCR_ACKO_SHIFT (5U) +/*! ACKO - Auto-Clock-Off Mode Enable + * 0b0..Auto-Clock-Off feature is disabled + * 0b1..Auto-Clock-Off feature is enabled + */ +#define ADC_MCR_ACKO(x) (((uint32_t)(((uint32_t)(x)) << ADC_MCR_ACKO_SHIFT)) & ADC_MCR_ACKO_MASK) + +#define ADC_MCR_ABORT_MASK (0x40U) +#define ADC_MCR_ABORT_SHIFT (6U) +/*! ABORT - Abort Conversion + * 0b0..Channel conversion has been aborted, or channel conversion is not currently running + * 0b1..Abort current channel conversion + */ +#define ADC_MCR_ABORT(x) (((uint32_t)(((uint32_t)(x)) << ADC_MCR_ABORT_SHIFT)) & ADC_MCR_ABORT_MASK) + +#define ADC_MCR_ABORTCHAIN_MASK (0x80U) +#define ADC_MCR_ABORTCHAIN_SHIFT (7U) +/*! ABORTCHAIN - Abort Conversion Chain + * 0b0..Chain conversion aborted or is currently not running + * 0b1..Abort current chain conversion + */ +#define ADC_MCR_ABORTCHAIN(x) (((uint32_t)(((uint32_t)(x)) << ADC_MCR_ABORTCHAIN_SHIFT)) & ADC_MCR_ABORTCHAIN_MASK) + +#define ADC_MCR_ADCLKSE_MASK (0x100U) +#define ADC_MCR_ADCLKSE_SHIFT (8U) +/*! ADCLKSE - Analog Clock Frequency Select + * 0b0..AD_CLK frequency is half + * 0b1..AD_CLK frequency is equal to bus clock frequency + */ +#define ADC_MCR_ADCLKSE(x) (((uint32_t)(((uint32_t)(x)) << ADC_MCR_ADCLKSE_SHIFT)) & ADC_MCR_ADCLKSE_MASK) + +#define ADC_MCR_TSAMP_MASK (0x600U) +#define ADC_MCR_TSAMP_SHIFT (9U) +/*! TSAMP - Sample Time for Calibration + * 0b00..22 cycles of AD_CLK (default) + * 0b01..8 cycles of AD_CLK + * 0b10..16 cycle of AD_CLK + * 0b11..32 cycle of AD_CLK + */ +#define ADC_MCR_TSAMP(x) (((uint32_t)(((uint32_t)(x)) << ADC_MCR_TSAMP_SHIFT)) & ADC_MCR_TSAMP_MASK) + +#define ADC_MCR_NRSMPL_MASK (0x1800U) +#define ADC_MCR_NRSMPL_SHIFT (11U) +/*! NRSMPL - Number of Averaging Samples + * 0b00..16 + * 0b01..32 + * 0b10..128 + * 0b11..512 + */ +#define ADC_MCR_NRSMPL(x) (((uint32_t)(((uint32_t)(x)) << ADC_MCR_NRSMPL_SHIFT)) & ADC_MCR_NRSMPL_MASK) + +#define ADC_MCR_AVGEN_MASK (0x2000U) +#define ADC_MCR_AVGEN_SHIFT (13U) +/*! AVGEN - Average Enable + * 0b0..Disable + * 0b1..Enable (default) + */ +#define ADC_MCR_AVGEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_MCR_AVGEN_SHIFT)) & ADC_MCR_AVGEN_MASK) + +#define ADC_MCR_CALSTART_MASK (0x4000U) +#define ADC_MCR_CALSTART_SHIFT (14U) +/*! CALSTART - Calibration Start + * 0b0..No effect + * 0b1..Start calibration + */ +#define ADC_MCR_CALSTART(x) (((uint32_t)(((uint32_t)(x)) << ADC_MCR_CALSTART_SHIFT)) & ADC_MCR_CALSTART_MASK) + +#define ADC_MCR_STCL_MASK (0x8000U) +#define ADC_MCR_STCL_SHIFT (15U) +/*! STCL - Self-Testing Configuration Lock + * 0b0..Not locked + * 0b1..Locked + */ +#define ADC_MCR_STCL(x) (((uint32_t)(((uint32_t)(x)) << ADC_MCR_STCL_SHIFT)) & ADC_MCR_STCL_MASK) + +#define ADC_MCR_JSTART_MASK (0x100000U) +#define ADC_MCR_JSTART_SHIFT (20U) +/*! JSTART - Start Injection Conversion */ +#define ADC_MCR_JSTART(x) (((uint32_t)(((uint32_t)(x)) << ADC_MCR_JSTART_SHIFT)) & ADC_MCR_JSTART_MASK) + +#define ADC_MCR_JEDGE_MASK (0x200000U) +#define ADC_MCR_JEDGE_SHIFT (21U) +/*! JEDGE - Injection Trigger Edge Selection + * 0b0..Falling edge is trigger + * 0b1..Rising edge is trigger + */ +#define ADC_MCR_JEDGE(x) (((uint32_t)(((uint32_t)(x)) << ADC_MCR_JEDGE_SHIFT)) & ADC_MCR_JEDGE_MASK) + +#define ADC_MCR_JTRGEN_MASK (0x400000U) +#define ADC_MCR_JTRGEN_SHIFT (22U) +/*! JTRGEN - Injection External Trigger Enable + * 0b0..Injected conversion not started by external trigger + * 0b1..Injected conversion started by external trigger + */ +#define ADC_MCR_JTRGEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_MCR_JTRGEN_SHIFT)) & ADC_MCR_JTRGEN_MASK) + +#define ADC_MCR_NSTART_MASK (0x1000000U) +#define ADC_MCR_NSTART_SHIFT (24U) +/*! NSTART - Normal Conversion Start */ +#define ADC_MCR_NSTART(x) (((uint32_t)(((uint32_t)(x)) << ADC_MCR_NSTART_SHIFT)) & ADC_MCR_NSTART_MASK) + +#define ADC_MCR_EDGE_MASK (0x4000000U) +#define ADC_MCR_EDGE_SHIFT (26U) +/*! EDGE - Trigger Edge Select + * 0b0..Falling edge is trigger + * 0b1..Rising edge is trigger + */ +#define ADC_MCR_EDGE(x) (((uint32_t)(((uint32_t)(x)) << ADC_MCR_EDGE_SHIFT)) & ADC_MCR_EDGE_MASK) + +#define ADC_MCR_TRGEN_MASK (0x8000000U) +#define ADC_MCR_TRGEN_SHIFT (27U) +/*! TRGEN - External Trigger Enable + * 0b0..External trigger is disabled + * 0b1..Enables the external trigger to start a conversion + */ +#define ADC_MCR_TRGEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_MCR_TRGEN_SHIFT)) & ADC_MCR_TRGEN_MASK) + +#define ADC_MCR_MODE_MASK (0x20000000U) +#define ADC_MCR_MODE_SHIFT (29U) +/*! MODE - Normal Scan Mode Select + * 0b0..One-Shot Operation mode + * 0b1..Scan Operation mode + */ +#define ADC_MCR_MODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_MCR_MODE_SHIFT)) & ADC_MCR_MODE_MASK) + +#define ADC_MCR_WLSIDE_MASK (0x40000000U) +#define ADC_MCR_WLSIDE_SHIFT (30U) +/*! WLSIDE - Write Left Side + * 0b0..Write right-aligned conversion data (from 11 to 0) + * 0b1..Write left-aligned conversion data (from 15 to 4) + */ +#define ADC_MCR_WLSIDE(x) (((uint32_t)(((uint32_t)(x)) << ADC_MCR_WLSIDE_SHIFT)) & ADC_MCR_WLSIDE_MASK) + +#define ADC_MCR_OWREN_MASK (0x80000000U) +#define ADC_MCR_OWREN_SHIFT (31U) +/*! OWREN - Overwrite Enable + * 0b0..Older valid conversion data is not overwritten by newer conversion data + * 0b1..Newer conversion result is always overwritten, irrespective of the validity of older conversion data + */ +#define ADC_MCR_OWREN(x) (((uint32_t)(((uint32_t)(x)) << ADC_MCR_OWREN_SHIFT)) & ADC_MCR_OWREN_MASK) +/*! @} */ + +/*! @name MSR - Main Status */ +/*! @{ */ + +#define ADC_MSR_ADCSTATUS_MASK (0x7U) +#define ADC_MSR_ADCSTATUS_SHIFT (0U) +/*! ADCSTATUS - ADC Status + * 0b000..Idle + * 0b001..Power-down + * 0b010..Wait state (waiting to start conversion after [external trigger]). + * 0b011..Busy in calibration + * 0b100..Sample + * 0b110..Conversion + */ +#define ADC_MSR_ADCSTATUS(x) (((uint32_t)(((uint32_t)(x)) << ADC_MSR_ADCSTATUS_SHIFT)) & ADC_MSR_ADCSTATUS_MASK) + +#define ADC_MSR_ACKO_MASK (0x20U) +#define ADC_MSR_ACKO_SHIFT (5U) +/*! ACKO - Auto-Clock-Off Enable + * 0b0..Auto-Clock-Off feature is not enabled + * 0b1..Auto-Clock-Off feature is enabled + */ +#define ADC_MSR_ACKO(x) (((uint32_t)(((uint32_t)(x)) << ADC_MSR_ACKO_SHIFT)) & ADC_MSR_ACKO_MASK) + +#define ADC_MSR_CHADDR_MASK (0xFE00U) +#define ADC_MSR_CHADDR_SHIFT (9U) +/*! CHADDR - Channel Address + * 0b0000000..Channel 0 selected + * 0b0000001..Channel 1 selected + * 0b0000010..Channel 2 selected + * 0b0000011..Channel 3 selected + * 0b0000100..Channel 4 selected + * 0b0000101..Channel 5 selected + * 0b0000110..Channel 6 selected + * 0b0000111..Channel 7 selected + * 0b0100000..Bandgap input selected + * 0b0100001..Pre-sample voltage - 1 : DVDD1P0/2 + * 0b0100010..Pre-sample voltage - 2 : AVDD1p8 + * 0b0100011..Pre-sample voltage - 3 : VREFL_1p8 + * 0b0100100..Pre-sample voltage - 4 : VREFH_1p8 + */ +#define ADC_MSR_CHADDR(x) (((uint32_t)(((uint32_t)(x)) << ADC_MSR_CHADDR_SHIFT)) & ADC_MSR_CHADDR_MASK) + +#define ADC_MSR_SELF_TEST_S_MASK (0x40000U) +#define ADC_MSR_SELF_TEST_S_SHIFT (18U) +/*! SELF_TEST_S - Self-Test Status + * 0b0..Self-test conversion is not in process + * 0b1..Self-test conversion is in process + */ +#define ADC_MSR_SELF_TEST_S(x) (((uint32_t)(((uint32_t)(x)) << ADC_MSR_SELF_TEST_S_SHIFT)) & ADC_MSR_SELF_TEST_S_MASK) + +#define ADC_MSR_JSTART_MASK (0x100000U) +#define ADC_MSR_JSTART_SHIFT (20U) +/*! JSTART - Injected Conversion Status + * 0b0..Injected conversion is not in process + * 0b1..Injected conversion is in process + */ +#define ADC_MSR_JSTART(x) (((uint32_t)(((uint32_t)(x)) << ADC_MSR_JSTART_SHIFT)) & ADC_MSR_JSTART_MASK) + +#define ADC_MSR_JABORT_MASK (0x800000U) +#define ADC_MSR_JABORT_SHIFT (23U) +/*! JABORT - Injected Conversion Abort Status + * 0b0..Injected conversion has not been aborted + * 0b1..Injected conversion has been aborted + */ +#define ADC_MSR_JABORT(x) (((uint32_t)(((uint32_t)(x)) << ADC_MSR_JABORT_SHIFT)) & ADC_MSR_JABORT_MASK) + +#define ADC_MSR_NSTART_MASK (0x1000000U) +#define ADC_MSR_NSTART_SHIFT (24U) +/*! NSTART - Normal Conversion Status + * 0b0..Normal conversion is not in process + * 0b1..Normal conversion is in process + */ +#define ADC_MSR_NSTART(x) (((uint32_t)(((uint32_t)(x)) << ADC_MSR_NSTART_SHIFT)) & ADC_MSR_NSTART_MASK) + +#define ADC_MSR_CALBUSY_MASK (0x20000000U) +#define ADC_MSR_CALBUSY_SHIFT (29U) +/*! CALBUSY - Calibration Busy + * 0b0..ADC is ready for use + * 0b1..ADC is busy in a calibration process + */ +#define ADC_MSR_CALBUSY(x) (((uint32_t)(((uint32_t)(x)) << ADC_MSR_CALBUSY_SHIFT)) & ADC_MSR_CALBUSY_MASK) + +#define ADC_MSR_CALFAIL_MASK (0x40000000U) +#define ADC_MSR_CALFAIL_SHIFT (30U) +/*! CALFAIL - Calibration Failed + * 0b0..Calibration passed (must be checked with CALBUSY = 0b) + * 0b0..No effect + * 0b1..Calibration failed + * 0b1..Clear the flag + */ +#define ADC_MSR_CALFAIL(x) (((uint32_t)(((uint32_t)(x)) << ADC_MSR_CALFAIL_SHIFT)) & ADC_MSR_CALFAIL_MASK) + +#define ADC_MSR_CALIBRTD_MASK (0x80000000U) +#define ADC_MSR_CALIBRTD_SHIFT (31U) +/*! CALIBRTD - Calibration Status + * 0b0..Uncalibrated or calibration unsuccessful + * 0b1..Calibrated or calibration successful + */ +#define ADC_MSR_CALIBRTD(x) (((uint32_t)(((uint32_t)(x)) << ADC_MSR_CALIBRTD_SHIFT)) & ADC_MSR_CALIBRTD_MASK) +/*! @} */ + +/*! @name ISR - Interrupt Status */ +/*! @{ */ + +#define ADC_ISR_ECH_MASK (0x1U) +#define ADC_ISR_ECH_SHIFT (0U) +/*! ECH - End of Conversion Chain + * 0b0..End of conversion chain has not occurred + * 0b0..No effect + * 0b1..End of conversion chain has occurred + * 0b1..Clear the flag + */ +#define ADC_ISR_ECH(x) (((uint32_t)(((uint32_t)(x)) << ADC_ISR_ECH_SHIFT)) & ADC_ISR_ECH_MASK) + +#define ADC_ISR_EOC_MASK (0x2U) +#define ADC_ISR_EOC_SHIFT (1U) +/*! EOC - End of Channel Conversion + * 0b0..Channel end of conversion has not occurred + * 0b0..No effect + * 0b1..Channel end of conversion has occurred + * 0b1..Clear the flag + */ +#define ADC_ISR_EOC(x) (((uint32_t)(((uint32_t)(x)) << ADC_ISR_EOC_SHIFT)) & ADC_ISR_EOC_MASK) + +#define ADC_ISR_JECH_MASK (0x4U) +#define ADC_ISR_JECH_SHIFT (2U) +/*! JECH - Injected End of Conversion Chain + * 0b0..Injected channel end of conversion chain has not occurred + * 0b0..No effect + * 0b1..Injected channel end of conversion chain has occurred + * 0b1..Clear the flag + */ +#define ADC_ISR_JECH(x) (((uint32_t)(((uint32_t)(x)) << ADC_ISR_JECH_SHIFT)) & ADC_ISR_JECH_MASK) + +#define ADC_ISR_JEOC_MASK (0x8U) +#define ADC_ISR_JEOC_SHIFT (3U) +/*! JEOC - Injected Channel End of Conversion + * 0b0..Injected channel end of conversion has not occurred + * 0b0..No effect + * 0b1..Injected channel end of conversion has occurred + * 0b1..Clear the flag + */ +#define ADC_ISR_JEOC(x) (((uint32_t)(((uint32_t)(x)) << ADC_ISR_JEOC_SHIFT)) & ADC_ISR_JEOC_MASK) +/*! @} */ + +/*! @name CEOCFR0 - Channel Pending 0 */ +/*! @{ */ + +#define ADC_CEOCFR0_EOC_CH0_MASK (0x1U) +#define ADC_CEOCFR0_EOC_CH0_SHIFT (0U) +/*! EOC_CH0 - Channel 0 EOC Status + * 0b0..Conversion not complete + * 0b0..No effect + * 0b1..Conversion complete + * 0b1..Clear the flag + */ +#define ADC_CEOCFR0_EOC_CH0(x) (((uint32_t)(((uint32_t)(x)) << ADC_CEOCFR0_EOC_CH0_SHIFT)) & ADC_CEOCFR0_EOC_CH0_MASK) + +#define ADC_CEOCFR0_EOC_CH1_MASK (0x2U) +#define ADC_CEOCFR0_EOC_CH1_SHIFT (1U) +/*! EOC_CH1 - Channel 1 EOC Status + * 0b0..Conversion not complete + * 0b0..No effect + * 0b1..Conversion complete + * 0b1..Clear the flag + */ +#define ADC_CEOCFR0_EOC_CH1(x) (((uint32_t)(((uint32_t)(x)) << ADC_CEOCFR0_EOC_CH1_SHIFT)) & ADC_CEOCFR0_EOC_CH1_MASK) + +#define ADC_CEOCFR0_EOC_CH2_MASK (0x4U) +#define ADC_CEOCFR0_EOC_CH2_SHIFT (2U) +/*! EOC_CH2 - Channel 2 EOC Status + * 0b0..Conversion not complete + * 0b0..No effect + * 0b1..Conversion complete + * 0b1..Clear the flag + */ +#define ADC_CEOCFR0_EOC_CH2(x) (((uint32_t)(((uint32_t)(x)) << ADC_CEOCFR0_EOC_CH2_SHIFT)) & ADC_CEOCFR0_EOC_CH2_MASK) + +#define ADC_CEOCFR0_EOC_CH3_MASK (0x8U) +#define ADC_CEOCFR0_EOC_CH3_SHIFT (3U) +/*! EOC_CH3 - Channel 3 EOC Status + * 0b0..Conversion not complete + * 0b0..No effect + * 0b1..Conversion complete + * 0b1..Clear the flag + */ +#define ADC_CEOCFR0_EOC_CH3(x) (((uint32_t)(((uint32_t)(x)) << ADC_CEOCFR0_EOC_CH3_SHIFT)) & ADC_CEOCFR0_EOC_CH3_MASK) + +#define ADC_CEOCFR0_EOC_CH4_MASK (0x10U) +#define ADC_CEOCFR0_EOC_CH4_SHIFT (4U) +/*! EOC_CH4 - Channel 4 EOC Status + * 0b0..Conversion not complete + * 0b0..No effect + * 0b1..Conversion complete + * 0b1..Clear the flag + */ +#define ADC_CEOCFR0_EOC_CH4(x) (((uint32_t)(((uint32_t)(x)) << ADC_CEOCFR0_EOC_CH4_SHIFT)) & ADC_CEOCFR0_EOC_CH4_MASK) + +#define ADC_CEOCFR0_EOC_CH5_MASK (0x20U) +#define ADC_CEOCFR0_EOC_CH5_SHIFT (5U) +/*! EOC_CH5 - Channel 5 EOC Status + * 0b0..Conversion not complete + * 0b0..No effect + * 0b1..Conversion complete + * 0b1..Clear the flag + */ +#define ADC_CEOCFR0_EOC_CH5(x) (((uint32_t)(((uint32_t)(x)) << ADC_CEOCFR0_EOC_CH5_SHIFT)) & ADC_CEOCFR0_EOC_CH5_MASK) + +#define ADC_CEOCFR0_EOC_CH6_MASK (0x40U) +#define ADC_CEOCFR0_EOC_CH6_SHIFT (6U) +/*! EOC_CH6 - Channel 6 EOC Status + * 0b0..Conversion not complete + * 0b0..No effect + * 0b1..Conversion complete + * 0b1..Clear the flag + */ +#define ADC_CEOCFR0_EOC_CH6(x) (((uint32_t)(((uint32_t)(x)) << ADC_CEOCFR0_EOC_CH6_SHIFT)) & ADC_CEOCFR0_EOC_CH6_MASK) + +#define ADC_CEOCFR0_EOC_CH7_MASK (0x80U) +#define ADC_CEOCFR0_EOC_CH7_SHIFT (7U) +/*! EOC_CH7 - Channel 7 EOC Status + * 0b0..Conversion not complete + * 0b0..No effect + * 0b1..Conversion complete + * 0b1..Clear the flag + */ +#define ADC_CEOCFR0_EOC_CH7(x) (((uint32_t)(((uint32_t)(x)) << ADC_CEOCFR0_EOC_CH7_SHIFT)) & ADC_CEOCFR0_EOC_CH7_MASK) +/*! @} */ + +/*! @name CEOCFR1 - Channel Pending 1 */ +/*! @{ */ + +#define ADC_CEOCFR1_EOC_CH32_MASK (0x1U) +#define ADC_CEOCFR1_EOC_CH32_SHIFT (0U) +/*! EOC_CH32 - Channel 32 EOC Status + * 0b0..Conversion not complete + * 0b0..No effect + * 0b1..Conversion complete + * 0b1..Clear the flag + */ +#define ADC_CEOCFR1_EOC_CH32(x) (((uint32_t)(((uint32_t)(x)) << ADC_CEOCFR1_EOC_CH32_SHIFT)) & ADC_CEOCFR1_EOC_CH32_MASK) + +#define ADC_CEOCFR1_EOC_CH33_MASK (0x2U) +#define ADC_CEOCFR1_EOC_CH33_SHIFT (1U) +/*! EOC_CH33 - Channel 33 EOC Status + * 0b0..Conversion not complete + * 0b0..No effect + * 0b1..Conversion complete + * 0b1..Clear the flag + */ +#define ADC_CEOCFR1_EOC_CH33(x) (((uint32_t)(((uint32_t)(x)) << ADC_CEOCFR1_EOC_CH33_SHIFT)) & ADC_CEOCFR1_EOC_CH33_MASK) + +#define ADC_CEOCFR1_EOC_CH34_MASK (0x4U) +#define ADC_CEOCFR1_EOC_CH34_SHIFT (2U) +/*! EOC_CH34 - Channel 34 EOC Status + * 0b0..Conversion not complete + * 0b0..No effect + * 0b1..Conversion complete + * 0b1..Clear the flag + */ +#define ADC_CEOCFR1_EOC_CH34(x) (((uint32_t)(((uint32_t)(x)) << ADC_CEOCFR1_EOC_CH34_SHIFT)) & ADC_CEOCFR1_EOC_CH34_MASK) + +#define ADC_CEOCFR1_EOC_CH35_MASK (0x8U) +#define ADC_CEOCFR1_EOC_CH35_SHIFT (3U) +/*! EOC_CH35 - Channel 35 EOC Status + * 0b0..Conversion not complete + * 0b0..No effect + * 0b1..Conversion complete + * 0b1..Clear the flag + */ +#define ADC_CEOCFR1_EOC_CH35(x) (((uint32_t)(((uint32_t)(x)) << ADC_CEOCFR1_EOC_CH35_SHIFT)) & ADC_CEOCFR1_EOC_CH35_MASK) + +#define ADC_CEOCFR1_EOC_CH36_MASK (0x10U) +#define ADC_CEOCFR1_EOC_CH36_SHIFT (4U) +/*! EOC_CH36 - Channel 36 EOC Status + * 0b0..Conversion not complete + * 0b0..No effect + * 0b1..Conversion complete + * 0b1..Clear the flag + */ +#define ADC_CEOCFR1_EOC_CH36(x) (((uint32_t)(((uint32_t)(x)) << ADC_CEOCFR1_EOC_CH36_SHIFT)) & ADC_CEOCFR1_EOC_CH36_MASK) + +#define ADC_CEOCFR1_EOC_CH37_MASK (0x20U) +#define ADC_CEOCFR1_EOC_CH37_SHIFT (5U) +/*! EOC_CH37 - Channel 37 EOC Status + * 0b0..Conversion not complete + * 0b0..No effect + * 0b1..Conversion complete + * 0b1..Clear the flag + */ +#define ADC_CEOCFR1_EOC_CH37(x) (((uint32_t)(((uint32_t)(x)) << ADC_CEOCFR1_EOC_CH37_SHIFT)) & ADC_CEOCFR1_EOC_CH37_MASK) + +#define ADC_CEOCFR1_EOC_CH38_MASK (0x40U) +#define ADC_CEOCFR1_EOC_CH38_SHIFT (6U) +/*! EOC_CH38 - Channel 38 EOC Status + * 0b0..Conversion not complete + * 0b0..No effect + * 0b1..Conversion complete + * 0b1..Clear the flag + */ +#define ADC_CEOCFR1_EOC_CH38(x) (((uint32_t)(((uint32_t)(x)) << ADC_CEOCFR1_EOC_CH38_SHIFT)) & ADC_CEOCFR1_EOC_CH38_MASK) + +#define ADC_CEOCFR1_EOC_CH39_MASK (0x80U) +#define ADC_CEOCFR1_EOC_CH39_SHIFT (7U) +/*! EOC_CH39 - Channel 39 EOC Status + * 0b0..Conversion not complete + * 0b0..No effect + * 0b1..Conversion complete + * 0b1..Clear the flag + */ +#define ADC_CEOCFR1_EOC_CH39(x) (((uint32_t)(((uint32_t)(x)) << ADC_CEOCFR1_EOC_CH39_SHIFT)) & ADC_CEOCFR1_EOC_CH39_MASK) +/*! @} */ + +/*! @name IMR - Interrupt Mask */ +/*! @{ */ + +#define ADC_IMR_MSKECH_MASK (0x1U) +#define ADC_IMR_MSKECH_SHIFT (0U) +/*! MSKECH - End of Chain Conversion Interrupt Mask + * 0b0..End of chain conversion interrupt disabled + * 0b1..End of chain conversion interrupt enabled + */ +#define ADC_IMR_MSKECH(x) (((uint32_t)(((uint32_t)(x)) << ADC_IMR_MSKECH_SHIFT)) & ADC_IMR_MSKECH_MASK) + +#define ADC_IMR_MSKEOC_MASK (0x2U) +#define ADC_IMR_MSKEOC_SHIFT (1U) +/*! MSKEOC - End of Conversion Interrupt Mask + * 0b0..End of conversion interrupt disabled + * 0b1..End of conversion interrupt enabled + */ +#define ADC_IMR_MSKEOC(x) (((uint32_t)(((uint32_t)(x)) << ADC_IMR_MSKEOC_SHIFT)) & ADC_IMR_MSKEOC_MASK) + +#define ADC_IMR_MSKJECH_MASK (0x4U) +#define ADC_IMR_MSKJECH_SHIFT (2U) +/*! MSKJECH - End of Injected Chain Conversion Interrupt Mask + * 0b0..End of injected chain conversion interrupt disabled + * 0b1..End of injected chain conversion interrupt enabled + */ +#define ADC_IMR_MSKJECH(x) (((uint32_t)(((uint32_t)(x)) << ADC_IMR_MSKJECH_SHIFT)) & ADC_IMR_MSKJECH_MASK) + +#define ADC_IMR_MSKJEOC_MASK (0x8U) +#define ADC_IMR_MSKJEOC_SHIFT (3U) +/*! MSKJEOC - End of Injected Conversion Interrupt Mask + * 0b0..End of injected conversion interrupt disabled + * 0b1..End of injected conversion interrupt enabled + */ +#define ADC_IMR_MSKJEOC(x) (((uint32_t)(((uint32_t)(x)) << ADC_IMR_MSKJEOC_SHIFT)) & ADC_IMR_MSKJEOC_MASK) +/*! @} */ + +/*! @name CIMR0 - Channel Interrupt Mask 0 */ +/*! @{ */ + +#define ADC_CIMR0_CIM0_MASK (0x1U) +#define ADC_CIMR0_CIM0_SHIFT (0U) +/*! CIM0 - Channel 0 Interrupt Enable + * 0b0..Interrupt disabled + * 0b1..Interrupt enabled + */ +#define ADC_CIMR0_CIM0(x) (((uint32_t)(((uint32_t)(x)) << ADC_CIMR0_CIM0_SHIFT)) & ADC_CIMR0_CIM0_MASK) + +#define ADC_CIMR0_CIM1_MASK (0x2U) +#define ADC_CIMR0_CIM1_SHIFT (1U) +/*! CIM1 - Channel 1 Interrupt Enable + * 0b0..Interrupt disabled + * 0b1..Interrupt enabled + */ +#define ADC_CIMR0_CIM1(x) (((uint32_t)(((uint32_t)(x)) << ADC_CIMR0_CIM1_SHIFT)) & ADC_CIMR0_CIM1_MASK) + +#define ADC_CIMR0_CIM2_MASK (0x4U) +#define ADC_CIMR0_CIM2_SHIFT (2U) +/*! CIM2 - Channel 2 Interrupt Enable + * 0b0..Interrupt disabled + * 0b1..Interrupt enabled + */ +#define ADC_CIMR0_CIM2(x) (((uint32_t)(((uint32_t)(x)) << ADC_CIMR0_CIM2_SHIFT)) & ADC_CIMR0_CIM2_MASK) + +#define ADC_CIMR0_CIM3_MASK (0x8U) +#define ADC_CIMR0_CIM3_SHIFT (3U) +/*! CIM3 - Channel 3 Interrupt Enable + * 0b0..Interrupt disabled + * 0b1..Interrupt enabled + */ +#define ADC_CIMR0_CIM3(x) (((uint32_t)(((uint32_t)(x)) << ADC_CIMR0_CIM3_SHIFT)) & ADC_CIMR0_CIM3_MASK) + +#define ADC_CIMR0_CIM4_MASK (0x10U) +#define ADC_CIMR0_CIM4_SHIFT (4U) +/*! CIM4 - Channel 4 Interrupt Enable + * 0b0..Interrupt disabled + * 0b1..Interrupt enabled + */ +#define ADC_CIMR0_CIM4(x) (((uint32_t)(((uint32_t)(x)) << ADC_CIMR0_CIM4_SHIFT)) & ADC_CIMR0_CIM4_MASK) + +#define ADC_CIMR0_CIM5_MASK (0x20U) +#define ADC_CIMR0_CIM5_SHIFT (5U) +/*! CIM5 - Channel 5 Interrupt Enable + * 0b0..Interrupt disabled + * 0b1..Interrupt enabled + */ +#define ADC_CIMR0_CIM5(x) (((uint32_t)(((uint32_t)(x)) << ADC_CIMR0_CIM5_SHIFT)) & ADC_CIMR0_CIM5_MASK) + +#define ADC_CIMR0_CIM6_MASK (0x40U) +#define ADC_CIMR0_CIM6_SHIFT (6U) +/*! CIM6 - Channel 6 Interrupt Enable + * 0b0..Interrupt disabled + * 0b1..Interrupt enabled + */ +#define ADC_CIMR0_CIM6(x) (((uint32_t)(((uint32_t)(x)) << ADC_CIMR0_CIM6_SHIFT)) & ADC_CIMR0_CIM6_MASK) + +#define ADC_CIMR0_CIM7_MASK (0x80U) +#define ADC_CIMR0_CIM7_SHIFT (7U) +/*! CIM7 - Channel 7 Interrupt Enable + * 0b0..Interrupt disabled + * 0b1..Interrupt enabled + */ +#define ADC_CIMR0_CIM7(x) (((uint32_t)(((uint32_t)(x)) << ADC_CIMR0_CIM7_SHIFT)) & ADC_CIMR0_CIM7_MASK) +/*! @} */ + +/*! @name CIMR1 - Channel Interrupt Mask 1 */ +/*! @{ */ + +#define ADC_CIMR1_CIM32_MASK (0x1U) +#define ADC_CIMR1_CIM32_SHIFT (0U) +/*! CIM32 - Channel 32 Interrupt Enable + * 0b0..Interrupt disabled + * 0b1..Interrupt enabled + */ +#define ADC_CIMR1_CIM32(x) (((uint32_t)(((uint32_t)(x)) << ADC_CIMR1_CIM32_SHIFT)) & ADC_CIMR1_CIM32_MASK) + +#define ADC_CIMR1_CIM33_MASK (0x2U) +#define ADC_CIMR1_CIM33_SHIFT (1U) +/*! CIM33 - Channel 33 Interrupt Enable + * 0b0..Interrupt disabled + * 0b1..Interrupt enabled + */ +#define ADC_CIMR1_CIM33(x) (((uint32_t)(((uint32_t)(x)) << ADC_CIMR1_CIM33_SHIFT)) & ADC_CIMR1_CIM33_MASK) + +#define ADC_CIMR1_CIM34_MASK (0x4U) +#define ADC_CIMR1_CIM34_SHIFT (2U) +/*! CIM34 - Channel 34 Interrupt Enable + * 0b0..Interrupt disabled + * 0b1..Interrupt enabled + */ +#define ADC_CIMR1_CIM34(x) (((uint32_t)(((uint32_t)(x)) << ADC_CIMR1_CIM34_SHIFT)) & ADC_CIMR1_CIM34_MASK) + +#define ADC_CIMR1_CIM35_MASK (0x8U) +#define ADC_CIMR1_CIM35_SHIFT (3U) +/*! CIM35 - Channel 35 Interrupt Enable + * 0b0..Interrupt disabled + * 0b1..Interrupt enabled + */ +#define ADC_CIMR1_CIM35(x) (((uint32_t)(((uint32_t)(x)) << ADC_CIMR1_CIM35_SHIFT)) & ADC_CIMR1_CIM35_MASK) + +#define ADC_CIMR1_CIM36_MASK (0x10U) +#define ADC_CIMR1_CIM36_SHIFT (4U) +/*! CIM36 - Channel 36 Interrupt Enable + * 0b0..Interrupt disabled + * 0b1..Interrupt enabled + */ +#define ADC_CIMR1_CIM36(x) (((uint32_t)(((uint32_t)(x)) << ADC_CIMR1_CIM36_SHIFT)) & ADC_CIMR1_CIM36_MASK) + +#define ADC_CIMR1_CIM37_MASK (0x20U) +#define ADC_CIMR1_CIM37_SHIFT (5U) +/*! CIM37 - Channel 37 Interrupt Enable + * 0b0..Interrupt disabled + * 0b1..Interrupt enabled + */ +#define ADC_CIMR1_CIM37(x) (((uint32_t)(((uint32_t)(x)) << ADC_CIMR1_CIM37_SHIFT)) & ADC_CIMR1_CIM37_MASK) + +#define ADC_CIMR1_CIM38_MASK (0x40U) +#define ADC_CIMR1_CIM38_SHIFT (6U) +/*! CIM38 - Channel 38 Interrupt Enable + * 0b0..Interrupt disabled + * 0b1..Interrupt enabled + */ +#define ADC_CIMR1_CIM38(x) (((uint32_t)(((uint32_t)(x)) << ADC_CIMR1_CIM38_SHIFT)) & ADC_CIMR1_CIM38_MASK) + +#define ADC_CIMR1_CIM39_MASK (0x80U) +#define ADC_CIMR1_CIM39_SHIFT (7U) +/*! CIM39 - Channel 39 Interrupt Enable + * 0b0..Interrupt disabled + * 0b1..Interrupt enabled + */ +#define ADC_CIMR1_CIM39(x) (((uint32_t)(((uint32_t)(x)) << ADC_CIMR1_CIM39_SHIFT)) & ADC_CIMR1_CIM39_MASK) +/*! @} */ + +/*! @name WTISR - Watchdog Threshold Interrupt Status */ +/*! @{ */ + +#define ADC_WTISR_WDG0L_MASK (0x1U) +#define ADC_WTISR_WDG0L_SHIFT (0U) +/*! WDG0L - Channel 0 Watchdog Low Threshold Interrupt + * 0b0..Interrupt not asserted + * 0b0..No effect + * 0b1..Interrupt asserted + * 0b1..Clear the flag + */ +#define ADC_WTISR_WDG0L(x) (((uint32_t)(((uint32_t)(x)) << ADC_WTISR_WDG0L_SHIFT)) & ADC_WTISR_WDG0L_MASK) + +#define ADC_WTISR_WDG0H_MASK (0x2U) +#define ADC_WTISR_WDG0H_SHIFT (1U) +/*! WDG0H - Channel 0 Watchdog High Threshold Interrupt + * 0b0..Interrupt not asserted + * 0b0..No effect + * 0b1..Interrupt asserted + * 0b1..Clear the flag + */ +#define ADC_WTISR_WDG0H(x) (((uint32_t)(((uint32_t)(x)) << ADC_WTISR_WDG0H_SHIFT)) & ADC_WTISR_WDG0H_MASK) + +#define ADC_WTISR_WDG1L_MASK (0x4U) +#define ADC_WTISR_WDG1L_SHIFT (2U) +/*! WDG1L - Channel 1 Watchdog Low Threshold Interrupt + * 0b0..Interrupt not asserted + * 0b0..No effect + * 0b1..Interrupt asserted + * 0b1..Clear the flag + */ +#define ADC_WTISR_WDG1L(x) (((uint32_t)(((uint32_t)(x)) << ADC_WTISR_WDG1L_SHIFT)) & ADC_WTISR_WDG1L_MASK) + +#define ADC_WTISR_WDG1H_MASK (0x8U) +#define ADC_WTISR_WDG1H_SHIFT (3U) +/*! WDG1H - Channel 1 Watchdog High Threshold Interrupt + * 0b0..Interrupt not asserted + * 0b0..No effect + * 0b1..Interrupt asserted + * 0b1..Clear the flag + */ +#define ADC_WTISR_WDG1H(x) (((uint32_t)(((uint32_t)(x)) << ADC_WTISR_WDG1H_SHIFT)) & ADC_WTISR_WDG1H_MASK) + +#define ADC_WTISR_WDG2L_MASK (0x10U) +#define ADC_WTISR_WDG2L_SHIFT (4U) +/*! WDG2L - Channel 2 Watchdog Low Threshold Interrupt + * 0b0..Interrupt not asserted + * 0b0..No effect + * 0b1..Interrupt asserted + * 0b1..Clear the flag + */ +#define ADC_WTISR_WDG2L(x) (((uint32_t)(((uint32_t)(x)) << ADC_WTISR_WDG2L_SHIFT)) & ADC_WTISR_WDG2L_MASK) + +#define ADC_WTISR_WDG2H_MASK (0x20U) +#define ADC_WTISR_WDG2H_SHIFT (5U) +/*! WDG2H - Channel 2 Watchdog High Threshold Interrupt + * 0b0..Interrupt not asserted + * 0b0..No effect + * 0b1..Interrupt asserted + * 0b1..Clear the flag + */ +#define ADC_WTISR_WDG2H(x) (((uint32_t)(((uint32_t)(x)) << ADC_WTISR_WDG2H_SHIFT)) & ADC_WTISR_WDG2H_MASK) + +#define ADC_WTISR_WDG3L_MASK (0x40U) +#define ADC_WTISR_WDG3L_SHIFT (6U) +/*! WDG3L - Channel 3 Watchdog Low Threshold Interrupt + * 0b0..Interrupt not asserted + * 0b0..No effect + * 0b1..Interrupt asserted + * 0b1..Clear the flag + */ +#define ADC_WTISR_WDG3L(x) (((uint32_t)(((uint32_t)(x)) << ADC_WTISR_WDG3L_SHIFT)) & ADC_WTISR_WDG3L_MASK) + +#define ADC_WTISR_WDG3H_MASK (0x80U) +#define ADC_WTISR_WDG3H_SHIFT (7U) +/*! WDG3H - Channel 3 Watchdog High Threshold Interrupt + * 0b0..Interrupt not asserted + * 0b0..No effect + * 0b1..Interrupt asserted + * 0b1..Clear the flag + */ +#define ADC_WTISR_WDG3H(x) (((uint32_t)(((uint32_t)(x)) << ADC_WTISR_WDG3H_SHIFT)) & ADC_WTISR_WDG3H_MASK) + +#define ADC_WTISR_WDG4L_MASK (0x100U) +#define ADC_WTISR_WDG4L_SHIFT (8U) +/*! WDG4L - Channel 4 Watchdog Low Threshold Interrupt + * 0b0..Interrupt not asserted + * 0b0..No effect + * 0b1..Interrupt asserted + * 0b1..Clear the flag + */ +#define ADC_WTISR_WDG4L(x) (((uint32_t)(((uint32_t)(x)) << ADC_WTISR_WDG4L_SHIFT)) & ADC_WTISR_WDG4L_MASK) + +#define ADC_WTISR_WDG4H_MASK (0x200U) +#define ADC_WTISR_WDG4H_SHIFT (9U) +/*! WDG4H - Channel 4 Watchdog High Threshold Interrupt + * 0b0..Interrupt not asserted + * 0b0..No effect + * 0b1..Interrupt asserted + * 0b1..Clear the flag + */ +#define ADC_WTISR_WDG4H(x) (((uint32_t)(((uint32_t)(x)) << ADC_WTISR_WDG4H_SHIFT)) & ADC_WTISR_WDG4H_MASK) + +#define ADC_WTISR_WDG5L_MASK (0x400U) +#define ADC_WTISR_WDG5L_SHIFT (10U) +/*! WDG5L - Channel 5 Watchdog Low Threshold Interrupt + * 0b0..Interrupt not asserted + * 0b0..No effect + * 0b1..Interrupt asserted + * 0b1..Clear the flag + */ +#define ADC_WTISR_WDG5L(x) (((uint32_t)(((uint32_t)(x)) << ADC_WTISR_WDG5L_SHIFT)) & ADC_WTISR_WDG5L_MASK) + +#define ADC_WTISR_WDG5H_MASK (0x800U) +#define ADC_WTISR_WDG5H_SHIFT (11U) +/*! WDG5H - Channel 5 Watchdog High Threshold Interrupt + * 0b0..Interrupt not asserted + * 0b0..No effect + * 0b1..Interrupt asserted + * 0b1..Clear the flag + */ +#define ADC_WTISR_WDG5H(x) (((uint32_t)(((uint32_t)(x)) << ADC_WTISR_WDG5H_SHIFT)) & ADC_WTISR_WDG5H_MASK) + +#define ADC_WTISR_WDG6L_MASK (0x1000U) +#define ADC_WTISR_WDG6L_SHIFT (12U) +/*! WDG6L - Channel 6 Watchdog Low Threshold Interrupt + * 0b0..Interrupt not asserted + * 0b0..No effect + * 0b1..Interrupt asserted + * 0b1..Clear the flag + */ +#define ADC_WTISR_WDG6L(x) (((uint32_t)(((uint32_t)(x)) << ADC_WTISR_WDG6L_SHIFT)) & ADC_WTISR_WDG6L_MASK) + +#define ADC_WTISR_WDG6H_MASK (0x2000U) +#define ADC_WTISR_WDG6H_SHIFT (13U) +/*! WDG6H - Channel 6 Watchdog High Threshold Interrupt + * 0b0..Interrupt not asserted + * 0b0..No effect + * 0b1..Interrupt asserted + * 0b1..Clear the flag + */ +#define ADC_WTISR_WDG6H(x) (((uint32_t)(((uint32_t)(x)) << ADC_WTISR_WDG6H_SHIFT)) & ADC_WTISR_WDG6H_MASK) + +#define ADC_WTISR_WDG7L_MASK (0x4000U) +#define ADC_WTISR_WDG7L_SHIFT (14U) +/*! WDG7L - Channel 7 Watchdog Low Threshold Interrupt + * 0b0..Interrupt not asserted + * 0b0..No effect + * 0b1..Interrupt asserted + * 0b1..Clear the flag + */ +#define ADC_WTISR_WDG7L(x) (((uint32_t)(((uint32_t)(x)) << ADC_WTISR_WDG7L_SHIFT)) & ADC_WTISR_WDG7L_MASK) + +#define ADC_WTISR_WDG7H_MASK (0x8000U) +#define ADC_WTISR_WDG7H_SHIFT (15U) +/*! WDG7H - Channel 7 Watchdog High Threshold Interrupt + * 0b0..Interrupt not asserted + * 0b0..No effect + * 0b1..Interrupt asserted + * 0b1..Clear the flag + */ +#define ADC_WTISR_WDG7H(x) (((uint32_t)(((uint32_t)(x)) << ADC_WTISR_WDG7H_SHIFT)) & ADC_WTISR_WDG7H_MASK) +/*! @} */ + +/*! @name WTIMR - Watchdog Threshold Interrupt Mask */ +/*! @{ */ + +#define ADC_WTIMR_MSKWDG0L_MASK (0x1U) +#define ADC_WTIMR_MSKWDG0L_SHIFT (0U) +/*! MSKWDG0L - Channel 0 Watchdog Low Threshold Interrupt Mask + * 0b0..Interrupt is disabled + * 0b1..Interrupt is enabled + */ +#define ADC_WTIMR_MSKWDG0L(x) (((uint32_t)(((uint32_t)(x)) << ADC_WTIMR_MSKWDG0L_SHIFT)) & ADC_WTIMR_MSKWDG0L_MASK) + +#define ADC_WTIMR_MSKWDG0H_MASK (0x2U) +#define ADC_WTIMR_MSKWDG0H_SHIFT (1U) +/*! MSKWDG0H - Channel 0 Watchdog High Threshold Interrupt Mask + * 0b0..Interrupt is disabled + * 0b1..Interrupt is enabled + */ +#define ADC_WTIMR_MSKWDG0H(x) (((uint32_t)(((uint32_t)(x)) << ADC_WTIMR_MSKWDG0H_SHIFT)) & ADC_WTIMR_MSKWDG0H_MASK) + +#define ADC_WTIMR_MSKWDG1L_MASK (0x4U) +#define ADC_WTIMR_MSKWDG1L_SHIFT (2U) +/*! MSKWDG1L - Channel 1 Watchdog Low Threshold Interrupt Mask + * 0b0..Interrupt is disabled + * 0b1..Interrupt is enabled + */ +#define ADC_WTIMR_MSKWDG1L(x) (((uint32_t)(((uint32_t)(x)) << ADC_WTIMR_MSKWDG1L_SHIFT)) & ADC_WTIMR_MSKWDG1L_MASK) + +#define ADC_WTIMR_MSKWDG1H_MASK (0x8U) +#define ADC_WTIMR_MSKWDG1H_SHIFT (3U) +/*! MSKWDG1H - Channel 1 Watchdog High Threshold Interrupt Mask + * 0b0..Interrupt is disabled + * 0b1..Interrupt is enabled + */ +#define ADC_WTIMR_MSKWDG1H(x) (((uint32_t)(((uint32_t)(x)) << ADC_WTIMR_MSKWDG1H_SHIFT)) & ADC_WTIMR_MSKWDG1H_MASK) + +#define ADC_WTIMR_MSKWDG2L_MASK (0x10U) +#define ADC_WTIMR_MSKWDG2L_SHIFT (4U) +/*! MSKWDG2L - Channel 2 Watchdog Low Threshold Interrupt Mask + * 0b0..Interrupt is disabled + * 0b1..Interrupt is enabled + */ +#define ADC_WTIMR_MSKWDG2L(x) (((uint32_t)(((uint32_t)(x)) << ADC_WTIMR_MSKWDG2L_SHIFT)) & ADC_WTIMR_MSKWDG2L_MASK) + +#define ADC_WTIMR_MSKWDG2H_MASK (0x20U) +#define ADC_WTIMR_MSKWDG2H_SHIFT (5U) +/*! MSKWDG2H - Channel 2 Watchdog High Threshold Interrupt Mask + * 0b0..Interrupt is disabled + * 0b1..Interrupt is enabled + */ +#define ADC_WTIMR_MSKWDG2H(x) (((uint32_t)(((uint32_t)(x)) << ADC_WTIMR_MSKWDG2H_SHIFT)) & ADC_WTIMR_MSKWDG2H_MASK) + +#define ADC_WTIMR_MSKWDG3L_MASK (0x40U) +#define ADC_WTIMR_MSKWDG3L_SHIFT (6U) +/*! MSKWDG3L - Channel 3 Watchdog Low Threshold Interrupt Mask + * 0b0..Interrupt is disabled + * 0b1..Interrupt is enabled + */ +#define ADC_WTIMR_MSKWDG3L(x) (((uint32_t)(((uint32_t)(x)) << ADC_WTIMR_MSKWDG3L_SHIFT)) & ADC_WTIMR_MSKWDG3L_MASK) + +#define ADC_WTIMR_MSKWDG3H_MASK (0x80U) +#define ADC_WTIMR_MSKWDG3H_SHIFT (7U) +/*! MSKWDG3H - Channel 3 Watchdog High Threshold Interrupt Mask + * 0b0..Interrupt is disabled + * 0b1..Interrupt is enabled + */ +#define ADC_WTIMR_MSKWDG3H(x) (((uint32_t)(((uint32_t)(x)) << ADC_WTIMR_MSKWDG3H_SHIFT)) & ADC_WTIMR_MSKWDG3H_MASK) + +#define ADC_WTIMR_MSKWDG4L_MASK (0x100U) +#define ADC_WTIMR_MSKWDG4L_SHIFT (8U) +/*! MSKWDG4L - Channel 4 Watchdog Low Threshold Interrupt Mask + * 0b0..Interrupt is disabled + * 0b1..Interrupt is enabled + */ +#define ADC_WTIMR_MSKWDG4L(x) (((uint32_t)(((uint32_t)(x)) << ADC_WTIMR_MSKWDG4L_SHIFT)) & ADC_WTIMR_MSKWDG4L_MASK) + +#define ADC_WTIMR_MSKWDG4H_MASK (0x200U) +#define ADC_WTIMR_MSKWDG4H_SHIFT (9U) +/*! MSKWDG4H - Channel 4 Watchdog High Threshold Interrupt Mask + * 0b0..Interrupt is disabled + * 0b1..Interrupt is enabled + */ +#define ADC_WTIMR_MSKWDG4H(x) (((uint32_t)(((uint32_t)(x)) << ADC_WTIMR_MSKWDG4H_SHIFT)) & ADC_WTIMR_MSKWDG4H_MASK) + +#define ADC_WTIMR_MSKWDG5L_MASK (0x400U) +#define ADC_WTIMR_MSKWDG5L_SHIFT (10U) +/*! MSKWDG5L - Channel 5 Watchdog Low Threshold Interrupt Mask + * 0b0..Interrupt is disabled + * 0b1..Interrupt is enabled + */ +#define ADC_WTIMR_MSKWDG5L(x) (((uint32_t)(((uint32_t)(x)) << ADC_WTIMR_MSKWDG5L_SHIFT)) & ADC_WTIMR_MSKWDG5L_MASK) + +#define ADC_WTIMR_MSKWDG5H_MASK (0x800U) +#define ADC_WTIMR_MSKWDG5H_SHIFT (11U) +/*! MSKWDG5H - Channel 5 Watchdog High Threshold Interrupt Mask + * 0b0..Interrupt is disabled + * 0b1..Interrupt is enabled + */ +#define ADC_WTIMR_MSKWDG5H(x) (((uint32_t)(((uint32_t)(x)) << ADC_WTIMR_MSKWDG5H_SHIFT)) & ADC_WTIMR_MSKWDG5H_MASK) + +#define ADC_WTIMR_MSKWDG6L_MASK (0x1000U) +#define ADC_WTIMR_MSKWDG6L_SHIFT (12U) +/*! MSKWDG6L - Channel 6 Watchdog Low Threshold Interrupt Mask + * 0b0..Interrupt is disabled + * 0b1..Interrupt is enabled + */ +#define ADC_WTIMR_MSKWDG6L(x) (((uint32_t)(((uint32_t)(x)) << ADC_WTIMR_MSKWDG6L_SHIFT)) & ADC_WTIMR_MSKWDG6L_MASK) + +#define ADC_WTIMR_MSKWDG6H_MASK (0x2000U) +#define ADC_WTIMR_MSKWDG6H_SHIFT (13U) +/*! MSKWDG6H - Channel 6 Watchdog High Threshold Interrupt Mask + * 0b0..Interrupt is disabled + * 0b1..Interrupt is enabled + */ +#define ADC_WTIMR_MSKWDG6H(x) (((uint32_t)(((uint32_t)(x)) << ADC_WTIMR_MSKWDG6H_SHIFT)) & ADC_WTIMR_MSKWDG6H_MASK) + +#define ADC_WTIMR_MSKWDG7L_MASK (0x4000U) +#define ADC_WTIMR_MSKWDG7L_SHIFT (14U) +/*! MSKWDG7L - Channel 7 Watchdog Low Threshold Interrupt Mask + * 0b0..Interrupt is disabled + * 0b1..Interrupt is enabled + */ +#define ADC_WTIMR_MSKWDG7L(x) (((uint32_t)(((uint32_t)(x)) << ADC_WTIMR_MSKWDG7L_SHIFT)) & ADC_WTIMR_MSKWDG7L_MASK) + +#define ADC_WTIMR_MSKWDG7H_MASK (0x8000U) +#define ADC_WTIMR_MSKWDG7H_SHIFT (15U) +/*! MSKWDG7H - Channel 7 Watchdog High Threshold Interrupt Mask + * 0b0..Interrupt is disabled + * 0b1..Interrupt is enabled + */ +#define ADC_WTIMR_MSKWDG7H(x) (((uint32_t)(((uint32_t)(x)) << ADC_WTIMR_MSKWDG7H_SHIFT)) & ADC_WTIMR_MSKWDG7H_MASK) +/*! @} */ + +/*! @name DMAE - DMAE */ +/*! @{ */ + +#define ADC_DMAE_DMAEN_MASK (0x1U) +#define ADC_DMAE_DMAEN_SHIFT (0U) +/*! DMAEN - DMA Global Enable + * 0b0..DMA feature is disabled + * 0b1..DMA feature is enabled + */ +#define ADC_DMAE_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_DMAE_DMAEN_SHIFT)) & ADC_DMAE_DMAEN_MASK) + +#define ADC_DMAE_DCLR_MASK (0x2U) +#define ADC_DMAE_DCLR_SHIFT (1U) +/*! DCLR - DMA Clear Sequence Enable + * 0b0..DMA request cleared by acknowledge from DMA controller + * 0b1..DMA request cleared on read of data registers + */ +#define ADC_DMAE_DCLR(x) (((uint32_t)(((uint32_t)(x)) << ADC_DMAE_DCLR_SHIFT)) & ADC_DMAE_DCLR_MASK) +/*! @} */ + +/*! @name DMAR0 - DMA 0 */ +/*! @{ */ + +#define ADC_DMAR0_DMA0_MASK (0x1U) +#define ADC_DMAR0_DMA0_SHIFT (0U) +/*! DMA0 - Channel 0 DMA Enable + * 0b0..Transfer of data in DMA mode is disabled + * 0b1..Transfer of data in DMA mode is enabled + */ +#define ADC_DMAR0_DMA0(x) (((uint32_t)(((uint32_t)(x)) << ADC_DMAR0_DMA0_SHIFT)) & ADC_DMAR0_DMA0_MASK) + +#define ADC_DMAR0_DMA1_MASK (0x2U) +#define ADC_DMAR0_DMA1_SHIFT (1U) +/*! DMA1 - Channel 1 DMA Enable + * 0b0..Transfer of data in DMA mode is disabled + * 0b1..Transfer of data in DMA mode is enabled + */ +#define ADC_DMAR0_DMA1(x) (((uint32_t)(((uint32_t)(x)) << ADC_DMAR0_DMA1_SHIFT)) & ADC_DMAR0_DMA1_MASK) + +#define ADC_DMAR0_DMA2_MASK (0x4U) +#define ADC_DMAR0_DMA2_SHIFT (2U) +/*! DMA2 - Channel 2 DMA Enable + * 0b0..Transfer of data in DMA mode is disabled + * 0b1..Transfer of data in DMA mode is enabled + */ +#define ADC_DMAR0_DMA2(x) (((uint32_t)(((uint32_t)(x)) << ADC_DMAR0_DMA2_SHIFT)) & ADC_DMAR0_DMA2_MASK) + +#define ADC_DMAR0_DMA3_MASK (0x8U) +#define ADC_DMAR0_DMA3_SHIFT (3U) +/*! DMA3 - Channel 3 DMA Enable + * 0b0..Transfer of data in DMA mode is disabled + * 0b1..Transfer of data in DMA mode is enabled + */ +#define ADC_DMAR0_DMA3(x) (((uint32_t)(((uint32_t)(x)) << ADC_DMAR0_DMA3_SHIFT)) & ADC_DMAR0_DMA3_MASK) + +#define ADC_DMAR0_DMA4_MASK (0x10U) +#define ADC_DMAR0_DMA4_SHIFT (4U) +/*! DMA4 - Channel 4 DMA Enable + * 0b0..Transfer of data in DMA mode is disabled + * 0b1..Transfer of data in DMA mode is enabled + */ +#define ADC_DMAR0_DMA4(x) (((uint32_t)(((uint32_t)(x)) << ADC_DMAR0_DMA4_SHIFT)) & ADC_DMAR0_DMA4_MASK) + +#define ADC_DMAR0_DMA5_MASK (0x20U) +#define ADC_DMAR0_DMA5_SHIFT (5U) +/*! DMA5 - Channel 5 DMA Enable + * 0b0..Transfer of data in DMA mode is disabled + * 0b1..Transfer of data in DMA mode is enabled + */ +#define ADC_DMAR0_DMA5(x) (((uint32_t)(((uint32_t)(x)) << ADC_DMAR0_DMA5_SHIFT)) & ADC_DMAR0_DMA5_MASK) + +#define ADC_DMAR0_DMA6_MASK (0x40U) +#define ADC_DMAR0_DMA6_SHIFT (6U) +/*! DMA6 - Channel 6 DMA Enable + * 0b0..Transfer of data in DMA mode is disabled + * 0b1..Transfer of data in DMA mode is enabled + */ +#define ADC_DMAR0_DMA6(x) (((uint32_t)(((uint32_t)(x)) << ADC_DMAR0_DMA6_SHIFT)) & ADC_DMAR0_DMA6_MASK) + +#define ADC_DMAR0_DMA7_MASK (0x80U) +#define ADC_DMAR0_DMA7_SHIFT (7U) +/*! DMA7 - Channel 7 DMA Enable + * 0b0..Transfer of data in DMA mode is disabled + * 0b1..Transfer of data in DMA mode is enabled + */ +#define ADC_DMAR0_DMA7(x) (((uint32_t)(((uint32_t)(x)) << ADC_DMAR0_DMA7_SHIFT)) & ADC_DMAR0_DMA7_MASK) +/*! @} */ + +/*! @name DMAR1 - DMA 1 */ +/*! @{ */ + +#define ADC_DMAR1_DMA32_MASK (0x1U) +#define ADC_DMAR1_DMA32_SHIFT (0U) +/*! DMA32 - Channel 32 DMA Enable + * 0b0..Transfer of data in DMA mode is disabled + * 0b1..Transfer of data in DMA mode is enabled + */ +#define ADC_DMAR1_DMA32(x) (((uint32_t)(((uint32_t)(x)) << ADC_DMAR1_DMA32_SHIFT)) & ADC_DMAR1_DMA32_MASK) + +#define ADC_DMAR1_DMA33_MASK (0x2U) +#define ADC_DMAR1_DMA33_SHIFT (1U) +/*! DMA33 - Channel 33 DMA Enable + * 0b0..Transfer of data in DMA mode is disabled + * 0b1..Transfer of data in DMA mode is enabled + */ +#define ADC_DMAR1_DMA33(x) (((uint32_t)(((uint32_t)(x)) << ADC_DMAR1_DMA33_SHIFT)) & ADC_DMAR1_DMA33_MASK) + +#define ADC_DMAR1_DMA34_MASK (0x4U) +#define ADC_DMAR1_DMA34_SHIFT (2U) +/*! DMA34 - Channel 34 DMA Enable + * 0b0..Transfer of data in DMA mode is disabled + * 0b1..Transfer of data in DMA mode is enabled + */ +#define ADC_DMAR1_DMA34(x) (((uint32_t)(((uint32_t)(x)) << ADC_DMAR1_DMA34_SHIFT)) & ADC_DMAR1_DMA34_MASK) + +#define ADC_DMAR1_DMA35_MASK (0x8U) +#define ADC_DMAR1_DMA35_SHIFT (3U) +/*! DMA35 - Channel 35 DMA Enable + * 0b0..Transfer of data in DMA mode is disabled + * 0b1..Transfer of data in DMA mode is enabled + */ +#define ADC_DMAR1_DMA35(x) (((uint32_t)(((uint32_t)(x)) << ADC_DMAR1_DMA35_SHIFT)) & ADC_DMAR1_DMA35_MASK) + +#define ADC_DMAR1_DMA36_MASK (0x10U) +#define ADC_DMAR1_DMA36_SHIFT (4U) +/*! DMA36 - Channel 36 DMA Enable + * 0b0..Transfer of data in DMA mode is disabled + * 0b1..Transfer of data in DMA mode is enabled + */ +#define ADC_DMAR1_DMA36(x) (((uint32_t)(((uint32_t)(x)) << ADC_DMAR1_DMA36_SHIFT)) & ADC_DMAR1_DMA36_MASK) + +#define ADC_DMAR1_DMA37_MASK (0x20U) +#define ADC_DMAR1_DMA37_SHIFT (5U) +/*! DMA37 - Channel 37 DMA Enable + * 0b0..Transfer of data in DMA mode is disabled + * 0b1..Transfer of data in DMA mode is enabled + */ +#define ADC_DMAR1_DMA37(x) (((uint32_t)(((uint32_t)(x)) << ADC_DMAR1_DMA37_SHIFT)) & ADC_DMAR1_DMA37_MASK) + +#define ADC_DMAR1_DMA38_MASK (0x40U) +#define ADC_DMAR1_DMA38_SHIFT (6U) +/*! DMA38 - Channel 38 DMA Enable + * 0b0..Transfer of data in DMA mode is disabled + * 0b1..Transfer of data in DMA mode is enabled + */ +#define ADC_DMAR1_DMA38(x) (((uint32_t)(((uint32_t)(x)) << ADC_DMAR1_DMA38_SHIFT)) & ADC_DMAR1_DMA38_MASK) + +#define ADC_DMAR1_DMA39_MASK (0x80U) +#define ADC_DMAR1_DMA39_SHIFT (7U) +/*! DMA39 - Channel 39 DMA Enable + * 0b0..Transfer of data in DMA mode is disabled + * 0b1..Transfer of data in DMA mode is enabled + */ +#define ADC_DMAR1_DMA39(x) (((uint32_t)(((uint32_t)(x)) << ADC_DMAR1_DMA39_SHIFT)) & ADC_DMAR1_DMA39_MASK) +/*! @} */ + +/*! @name THRHLR0 - Analog Watchdog Threshold 0 */ +/*! @{ */ + +#define ADC_THRHLR0_THRL_MASK (0xFFFU) +#define ADC_THRHLR0_THRL_SHIFT (0U) +/*! THRL - Low Threshold */ +#define ADC_THRHLR0_THRL(x) (((uint32_t)(((uint32_t)(x)) << ADC_THRHLR0_THRL_SHIFT)) & ADC_THRHLR0_THRL_MASK) + +#define ADC_THRHLR0_THRH_MASK (0xFFF0000U) +#define ADC_THRHLR0_THRH_SHIFT (16U) +/*! THRH - High Threshold */ +#define ADC_THRHLR0_THRH(x) (((uint32_t)(((uint32_t)(x)) << ADC_THRHLR0_THRH_SHIFT)) & ADC_THRHLR0_THRH_MASK) +/*! @} */ + +/*! @name THRHLR1 - Analog Watchdog Threshold 1 */ +/*! @{ */ + +#define ADC_THRHLR1_THRL_MASK (0xFFFU) +#define ADC_THRHLR1_THRL_SHIFT (0U) +/*! THRL - Low Threshold */ +#define ADC_THRHLR1_THRL(x) (((uint32_t)(((uint32_t)(x)) << ADC_THRHLR1_THRL_SHIFT)) & ADC_THRHLR1_THRL_MASK) + +#define ADC_THRHLR1_THRH_MASK (0xFFF0000U) +#define ADC_THRHLR1_THRH_SHIFT (16U) +/*! THRH - High Threshold */ +#define ADC_THRHLR1_THRH(x) (((uint32_t)(((uint32_t)(x)) << ADC_THRHLR1_THRH_SHIFT)) & ADC_THRHLR1_THRH_MASK) +/*! @} */ + +/*! @name THRHLR2 - Analog Watchdog Threshold 2 */ +/*! @{ */ + +#define ADC_THRHLR2_THRL_MASK (0xFFFU) +#define ADC_THRHLR2_THRL_SHIFT (0U) +/*! THRL - Low Threshold */ +#define ADC_THRHLR2_THRL(x) (((uint32_t)(((uint32_t)(x)) << ADC_THRHLR2_THRL_SHIFT)) & ADC_THRHLR2_THRL_MASK) + +#define ADC_THRHLR2_THRH_MASK (0xFFF0000U) +#define ADC_THRHLR2_THRH_SHIFT (16U) +/*! THRH - High Threshold */ +#define ADC_THRHLR2_THRH(x) (((uint32_t)(((uint32_t)(x)) << ADC_THRHLR2_THRH_SHIFT)) & ADC_THRHLR2_THRH_MASK) +/*! @} */ + +/*! @name THRHLR3 - Analog Watchdog Threshold 3 */ +/*! @{ */ + +#define ADC_THRHLR3_THRL_MASK (0xFFFU) +#define ADC_THRHLR3_THRL_SHIFT (0U) +/*! THRL - Low Threshold */ +#define ADC_THRHLR3_THRL(x) (((uint32_t)(((uint32_t)(x)) << ADC_THRHLR3_THRL_SHIFT)) & ADC_THRHLR3_THRL_MASK) + +#define ADC_THRHLR3_THRH_MASK (0xFFF0000U) +#define ADC_THRHLR3_THRH_SHIFT (16U) +/*! THRH - High Threshold */ +#define ADC_THRHLR3_THRH(x) (((uint32_t)(((uint32_t)(x)) << ADC_THRHLR3_THRH_SHIFT)) & ADC_THRHLR3_THRH_MASK) +/*! @} */ + +/*! @name PSCR - Presampling Control */ +/*! @{ */ + +#define ADC_PSCR_PRECONV_MASK (0x1U) +#define ADC_PSCR_PRECONV_SHIFT (0U) +/*! PRECONV - Convert Presampled Value + * 0b0..Presampling is followed by sampling then conversion. + * 0b1..Presampling is followed by the conversion. + */ +#define ADC_PSCR_PRECONV(x) (((uint32_t)(((uint32_t)(x)) << ADC_PSCR_PRECONV_SHIFT)) & ADC_PSCR_PRECONV_MASK) + +#define ADC_PSCR_PREVAL0_MASK (0x6U) +#define ADC_PSCR_PREVAL0_SHIFT (1U) +/*! PREVAL0 - Internal Presampling Voltage Selection */ +#define ADC_PSCR_PREVAL0(x) (((uint32_t)(((uint32_t)(x)) << ADC_PSCR_PREVAL0_SHIFT)) & ADC_PSCR_PREVAL0_MASK) + +#define ADC_PSCR_PREVAL1_MASK (0x18U) +#define ADC_PSCR_PREVAL1_SHIFT (3U) +/*! PREVAL1 - Internal Presampling Voltage Selection. */ +#define ADC_PSCR_PREVAL1(x) (((uint32_t)(((uint32_t)(x)) << ADC_PSCR_PREVAL1_SHIFT)) & ADC_PSCR_PREVAL1_MASK) +/*! @} */ + +/*! @name PSR0 - Presampling 0 */ +/*! @{ */ + +#define ADC_PSR0_PRES0_MASK (0x1U) +#define ADC_PSR0_PRES0_SHIFT (0U) +/*! PRES0 - Presampling Enable for Channel 0 + * 0b0..Presampling is disabled + * 0b1..Presampling is enabled + */ +#define ADC_PSR0_PRES0(x) (((uint32_t)(((uint32_t)(x)) << ADC_PSR0_PRES0_SHIFT)) & ADC_PSR0_PRES0_MASK) + +#define ADC_PSR0_PRES1_MASK (0x2U) +#define ADC_PSR0_PRES1_SHIFT (1U) +/*! PRES1 - Presampling Enable for Channel 1 + * 0b0..Presampling is disabled + * 0b1..Presampling is enabled + */ +#define ADC_PSR0_PRES1(x) (((uint32_t)(((uint32_t)(x)) << ADC_PSR0_PRES1_SHIFT)) & ADC_PSR0_PRES1_MASK) + +#define ADC_PSR0_PRES2_MASK (0x4U) +#define ADC_PSR0_PRES2_SHIFT (2U) +/*! PRES2 - Presampling Enable for Channel 2 + * 0b0..Presampling is disabled + * 0b1..Presampling is enabled + */ +#define ADC_PSR0_PRES2(x) (((uint32_t)(((uint32_t)(x)) << ADC_PSR0_PRES2_SHIFT)) & ADC_PSR0_PRES2_MASK) + +#define ADC_PSR0_PRES3_MASK (0x8U) +#define ADC_PSR0_PRES3_SHIFT (3U) +/*! PRES3 - Presampling Enable for Channel 3 + * 0b0..Presampling is disabled + * 0b1..Presampling is enabled + */ +#define ADC_PSR0_PRES3(x) (((uint32_t)(((uint32_t)(x)) << ADC_PSR0_PRES3_SHIFT)) & ADC_PSR0_PRES3_MASK) + +#define ADC_PSR0_PRES4_MASK (0x10U) +#define ADC_PSR0_PRES4_SHIFT (4U) +/*! PRES4 - Presampling Enable for Channel 4 + * 0b0..Presampling is disabled + * 0b1..Presampling is enabled + */ +#define ADC_PSR0_PRES4(x) (((uint32_t)(((uint32_t)(x)) << ADC_PSR0_PRES4_SHIFT)) & ADC_PSR0_PRES4_MASK) + +#define ADC_PSR0_PRES5_MASK (0x20U) +#define ADC_PSR0_PRES5_SHIFT (5U) +/*! PRES5 - Presampling Enable for Channel 5 + * 0b0..Presampling is disabled + * 0b1..Presampling is enabled + */ +#define ADC_PSR0_PRES5(x) (((uint32_t)(((uint32_t)(x)) << ADC_PSR0_PRES5_SHIFT)) & ADC_PSR0_PRES5_MASK) + +#define ADC_PSR0_PRES6_MASK (0x40U) +#define ADC_PSR0_PRES6_SHIFT (6U) +/*! PRES6 - Presampling Enable for Channel 6 + * 0b0..Presampling is disabled + * 0b1..Presampling is enabled + */ +#define ADC_PSR0_PRES6(x) (((uint32_t)(((uint32_t)(x)) << ADC_PSR0_PRES6_SHIFT)) & ADC_PSR0_PRES6_MASK) + +#define ADC_PSR0_PRES7_MASK (0x80U) +#define ADC_PSR0_PRES7_SHIFT (7U) +/*! PRES7 - Presampling Enable for Channel 7 + * 0b0..Presampling is disabled + * 0b1..Presampling is enabled + */ +#define ADC_PSR0_PRES7(x) (((uint32_t)(((uint32_t)(x)) << ADC_PSR0_PRES7_SHIFT)) & ADC_PSR0_PRES7_MASK) +/*! @} */ + +/*! @name PSR1 - Presampling 1 */ +/*! @{ */ + +#define ADC_PSR1_PRES32_MASK (0x1U) +#define ADC_PSR1_PRES32_SHIFT (0U) +/*! PRES32 - Presampling Enable for Channel 32 + * 0b0..Presampling is disabled + * 0b1..Presampling is enabled + */ +#define ADC_PSR1_PRES32(x) (((uint32_t)(((uint32_t)(x)) << ADC_PSR1_PRES32_SHIFT)) & ADC_PSR1_PRES32_MASK) + +#define ADC_PSR1_PRES33_MASK (0x2U) +#define ADC_PSR1_PRES33_SHIFT (1U) +/*! PRES33 - Presampling Enable for Channel 33 + * 0b0..Presampling is disabled + * 0b1..Presampling is enabled + */ +#define ADC_PSR1_PRES33(x) (((uint32_t)(((uint32_t)(x)) << ADC_PSR1_PRES33_SHIFT)) & ADC_PSR1_PRES33_MASK) + +#define ADC_PSR1_PRES34_MASK (0x4U) +#define ADC_PSR1_PRES34_SHIFT (2U) +/*! PRES34 - Presampling Enable for Channel 34 + * 0b0..Presampling is disabled + * 0b1..Presampling is enabled + */ +#define ADC_PSR1_PRES34(x) (((uint32_t)(((uint32_t)(x)) << ADC_PSR1_PRES34_SHIFT)) & ADC_PSR1_PRES34_MASK) + +#define ADC_PSR1_PRES35_MASK (0x8U) +#define ADC_PSR1_PRES35_SHIFT (3U) +/*! PRES35 - Presampling Enable for Channel 35 + * 0b0..Presampling is disabled + * 0b1..Presampling is enabled + */ +#define ADC_PSR1_PRES35(x) (((uint32_t)(((uint32_t)(x)) << ADC_PSR1_PRES35_SHIFT)) & ADC_PSR1_PRES35_MASK) + +#define ADC_PSR1_PRES36_MASK (0x10U) +#define ADC_PSR1_PRES36_SHIFT (4U) +/*! PRES36 - Presampling Enable for Channel 36 + * 0b0..Presampling is disabled + * 0b1..Presampling is enabled + */ +#define ADC_PSR1_PRES36(x) (((uint32_t)(((uint32_t)(x)) << ADC_PSR1_PRES36_SHIFT)) & ADC_PSR1_PRES36_MASK) + +#define ADC_PSR1_PRES37_MASK (0x20U) +#define ADC_PSR1_PRES37_SHIFT (5U) +/*! PRES37 - Presampling Enable for Channel 37 + * 0b0..Presampling is disabled + * 0b1..Presampling is enabled + */ +#define ADC_PSR1_PRES37(x) (((uint32_t)(((uint32_t)(x)) << ADC_PSR1_PRES37_SHIFT)) & ADC_PSR1_PRES37_MASK) + +#define ADC_PSR1_PRES38_MASK (0x40U) +#define ADC_PSR1_PRES38_SHIFT (6U) +/*! PRES38 - Presampling Enable for Channel 38 + * 0b0..Presampling is disabled + * 0b1..Presampling is enabled + */ +#define ADC_PSR1_PRES38(x) (((uint32_t)(((uint32_t)(x)) << ADC_PSR1_PRES38_SHIFT)) & ADC_PSR1_PRES38_MASK) + +#define ADC_PSR1_PRES39_MASK (0x80U) +#define ADC_PSR1_PRES39_SHIFT (7U) +/*! PRES39 - Presampling Enable for Channel 39 + * 0b0..Presampling is disabled + * 0b1..Presampling is enabled + */ +#define ADC_PSR1_PRES39(x) (((uint32_t)(((uint32_t)(x)) << ADC_PSR1_PRES39_SHIFT)) & ADC_PSR1_PRES39_MASK) +/*! @} */ + +/*! @name CTR0 - Conversion Timing 0 */ +/*! @{ */ + +#define ADC_CTR0_INPSAMP_MASK (0xFFU) +#define ADC_CTR0_INPSAMP_SHIFT (0U) +/*! INPSAMP - Sampling Phase Duration */ +#define ADC_CTR0_INPSAMP(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTR0_INPSAMP_SHIFT)) & ADC_CTR0_INPSAMP_MASK) +/*! @} */ + +/*! @name CTR1 - Conversion Timing 1 */ +/*! @{ */ + +#define ADC_CTR1_INPSAMP_MASK (0xFFU) +#define ADC_CTR1_INPSAMP_SHIFT (0U) +/*! INPSAMP - Sampling Phase Duration */ +#define ADC_CTR1_INPSAMP(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTR1_INPSAMP_SHIFT)) & ADC_CTR1_INPSAMP_MASK) +/*! @} */ + +/*! @name NCMR0 - Normal Conversion Mask 0 */ +/*! @{ */ + +#define ADC_NCMR0_CH0_MASK (0x1U) +#define ADC_NCMR0_CH0_SHIFT (0U) +/*! CH0 - Normal Conversion Mask for Channel 0 + * 0b0..Normal Conversion is disabled + * 0b1..Normal Conversion is enabled + */ +#define ADC_NCMR0_CH0(x) (((uint32_t)(((uint32_t)(x)) << ADC_NCMR0_CH0_SHIFT)) & ADC_NCMR0_CH0_MASK) + +#define ADC_NCMR0_CH1_MASK (0x2U) +#define ADC_NCMR0_CH1_SHIFT (1U) +/*! CH1 - Normal Conversion Mask for Channel 1 + * 0b0..Normal Conversion is disabled + * 0b1..Normal Conversion is enabled + */ +#define ADC_NCMR0_CH1(x) (((uint32_t)(((uint32_t)(x)) << ADC_NCMR0_CH1_SHIFT)) & ADC_NCMR0_CH1_MASK) + +#define ADC_NCMR0_CH2_MASK (0x4U) +#define ADC_NCMR0_CH2_SHIFT (2U) +/*! CH2 - Normal Conversion Mask for Channel 2 + * 0b0..Normal Conversion is disabled + * 0b1..Normal Conversion is enabled + */ +#define ADC_NCMR0_CH2(x) (((uint32_t)(((uint32_t)(x)) << ADC_NCMR0_CH2_SHIFT)) & ADC_NCMR0_CH2_MASK) + +#define ADC_NCMR0_CH3_MASK (0x8U) +#define ADC_NCMR0_CH3_SHIFT (3U) +/*! CH3 - Normal Conversion Mask for Channel 3 + * 0b0..Normal Conversion is disabled + * 0b1..Normal Conversion is enabled + */ +#define ADC_NCMR0_CH3(x) (((uint32_t)(((uint32_t)(x)) << ADC_NCMR0_CH3_SHIFT)) & ADC_NCMR0_CH3_MASK) + +#define ADC_NCMR0_CH4_MASK (0x10U) +#define ADC_NCMR0_CH4_SHIFT (4U) +/*! CH4 - Normal Conversion Mask for Channel 4 + * 0b0..Normal Conversion is disabled + * 0b1..Normal Conversion is enabled + */ +#define ADC_NCMR0_CH4(x) (((uint32_t)(((uint32_t)(x)) << ADC_NCMR0_CH4_SHIFT)) & ADC_NCMR0_CH4_MASK) + +#define ADC_NCMR0_CH5_MASK (0x20U) +#define ADC_NCMR0_CH5_SHIFT (5U) +/*! CH5 - Normal Conversion Mask for Channel 5 + * 0b0..Normal Conversion is disabled + * 0b1..Normal Conversion is enabled + */ +#define ADC_NCMR0_CH5(x) (((uint32_t)(((uint32_t)(x)) << ADC_NCMR0_CH5_SHIFT)) & ADC_NCMR0_CH5_MASK) + +#define ADC_NCMR0_CH6_MASK (0x40U) +#define ADC_NCMR0_CH6_SHIFT (6U) +/*! CH6 - Normal Conversion Mask for Channel 6 + * 0b0..Normal Conversion is disabled + * 0b1..Normal Conversion is enabled + */ +#define ADC_NCMR0_CH6(x) (((uint32_t)(((uint32_t)(x)) << ADC_NCMR0_CH6_SHIFT)) & ADC_NCMR0_CH6_MASK) + +#define ADC_NCMR0_CH7_MASK (0x80U) +#define ADC_NCMR0_CH7_SHIFT (7U) +/*! CH7 - Normal Conversion Mask for Channel 7 + * 0b0..Normal Conversion is disabled + * 0b1..Normal Conversion is enabled + */ +#define ADC_NCMR0_CH7(x) (((uint32_t)(((uint32_t)(x)) << ADC_NCMR0_CH7_SHIFT)) & ADC_NCMR0_CH7_MASK) +/*! @} */ + +/*! @name NCMR1 - Normal Conversion Mask 1 */ +/*! @{ */ + +#define ADC_NCMR1_CH32_MASK (0x1U) +#define ADC_NCMR1_CH32_SHIFT (0U) +/*! CH32 - Normal Conversion Mask for Channel 32 + * 0b0..Normal Conversion is disabled + * 0b1..Normal Conversion is enabled + */ +#define ADC_NCMR1_CH32(x) (((uint32_t)(((uint32_t)(x)) << ADC_NCMR1_CH32_SHIFT)) & ADC_NCMR1_CH32_MASK) + +#define ADC_NCMR1_CH33_MASK (0x2U) +#define ADC_NCMR1_CH33_SHIFT (1U) +/*! CH33 - Normal Conversion Mask for Channel 33 + * 0b0..Normal Conversion is disabled + * 0b1..Normal Conversion is enabled + */ +#define ADC_NCMR1_CH33(x) (((uint32_t)(((uint32_t)(x)) << ADC_NCMR1_CH33_SHIFT)) & ADC_NCMR1_CH33_MASK) + +#define ADC_NCMR1_CH34_MASK (0x4U) +#define ADC_NCMR1_CH34_SHIFT (2U) +/*! CH34 - Normal Conversion Mask for Channel 34 + * 0b0..Normal Conversion is disabled + * 0b1..Normal Conversion is enabled + */ +#define ADC_NCMR1_CH34(x) (((uint32_t)(((uint32_t)(x)) << ADC_NCMR1_CH34_SHIFT)) & ADC_NCMR1_CH34_MASK) + +#define ADC_NCMR1_CH35_MASK (0x8U) +#define ADC_NCMR1_CH35_SHIFT (3U) +/*! CH35 - Normal Conversion Mask for Channel 35 + * 0b0..Normal Conversion is disabled + * 0b1..Normal Conversion is enabled + */ +#define ADC_NCMR1_CH35(x) (((uint32_t)(((uint32_t)(x)) << ADC_NCMR1_CH35_SHIFT)) & ADC_NCMR1_CH35_MASK) + +#define ADC_NCMR1_CH36_MASK (0x10U) +#define ADC_NCMR1_CH36_SHIFT (4U) +/*! CH36 - Normal Conversion Mask for Channel 36 + * 0b0..Normal Conversion is disabled + * 0b1..Normal Conversion is enabled + */ +#define ADC_NCMR1_CH36(x) (((uint32_t)(((uint32_t)(x)) << ADC_NCMR1_CH36_SHIFT)) & ADC_NCMR1_CH36_MASK) + +#define ADC_NCMR1_CH37_MASK (0x20U) +#define ADC_NCMR1_CH37_SHIFT (5U) +/*! CH37 - Normal Conversion Mask for Channel 37 + * 0b0..Normal Conversion is disabled + * 0b1..Normal Conversion is enabled + */ +#define ADC_NCMR1_CH37(x) (((uint32_t)(((uint32_t)(x)) << ADC_NCMR1_CH37_SHIFT)) & ADC_NCMR1_CH37_MASK) + +#define ADC_NCMR1_CH38_MASK (0x40U) +#define ADC_NCMR1_CH38_SHIFT (6U) +/*! CH38 - Normal Conversion Mask for Channel 38 + * 0b0..Normal Conversion is disabled + * 0b1..Normal Conversion is enabled + */ +#define ADC_NCMR1_CH38(x) (((uint32_t)(((uint32_t)(x)) << ADC_NCMR1_CH38_SHIFT)) & ADC_NCMR1_CH38_MASK) + +#define ADC_NCMR1_CH39_MASK (0x80U) +#define ADC_NCMR1_CH39_SHIFT (7U) +/*! CH39 - Normal Conversion Mask for Channel 39 + * 0b0..Normal Conversion is disabled + * 0b1..Normal Conversion is enabled + */ +#define ADC_NCMR1_CH39(x) (((uint32_t)(((uint32_t)(x)) << ADC_NCMR1_CH39_SHIFT)) & ADC_NCMR1_CH39_MASK) +/*! @} */ + +/*! @name JCMR0 - Injected Conversion Mask 0 */ +/*! @{ */ + +#define ADC_JCMR0_CH0_MASK (0x1U) +#define ADC_JCMR0_CH0_SHIFT (0U) +/*! CH0 - Injected Conversion Mask for Channel 0 + * 0b0..Injected conversion is disabled + * 0b1..Injected conversion is enabled + */ +#define ADC_JCMR0_CH0(x) (((uint32_t)(((uint32_t)(x)) << ADC_JCMR0_CH0_SHIFT)) & ADC_JCMR0_CH0_MASK) + +#define ADC_JCMR0_CH1_MASK (0x2U) +#define ADC_JCMR0_CH1_SHIFT (1U) +/*! CH1 - Injected Conversion Mask for Channel 1 + * 0b0..Injected conversion is disabled + * 0b1..Injected conversion is enabled + */ +#define ADC_JCMR0_CH1(x) (((uint32_t)(((uint32_t)(x)) << ADC_JCMR0_CH1_SHIFT)) & ADC_JCMR0_CH1_MASK) + +#define ADC_JCMR0_CH2_MASK (0x4U) +#define ADC_JCMR0_CH2_SHIFT (2U) +/*! CH2 - Injected Conversion Mask for Channel 2 + * 0b0..Injected conversion is disabled + * 0b1..Injected conversion is enabled + */ +#define ADC_JCMR0_CH2(x) (((uint32_t)(((uint32_t)(x)) << ADC_JCMR0_CH2_SHIFT)) & ADC_JCMR0_CH2_MASK) + +#define ADC_JCMR0_CH3_MASK (0x8U) +#define ADC_JCMR0_CH3_SHIFT (3U) +/*! CH3 - Injected Conversion Mask for Channel 3 + * 0b0..Injected conversion is disabled + * 0b1..Injected conversion is enabled + */ +#define ADC_JCMR0_CH3(x) (((uint32_t)(((uint32_t)(x)) << ADC_JCMR0_CH3_SHIFT)) & ADC_JCMR0_CH3_MASK) + +#define ADC_JCMR0_CH4_MASK (0x10U) +#define ADC_JCMR0_CH4_SHIFT (4U) +/*! CH4 - Injected Conversion Mask for Channel 4 + * 0b0..Injected conversion is disabled + * 0b1..Injected conversion is enabled + */ +#define ADC_JCMR0_CH4(x) (((uint32_t)(((uint32_t)(x)) << ADC_JCMR0_CH4_SHIFT)) & ADC_JCMR0_CH4_MASK) + +#define ADC_JCMR0_CH5_MASK (0x20U) +#define ADC_JCMR0_CH5_SHIFT (5U) +/*! CH5 - Injected Conversion Mask for Channel 5 + * 0b0..Injected conversion is disabled + * 0b1..Injected conversion is enabled + */ +#define ADC_JCMR0_CH5(x) (((uint32_t)(((uint32_t)(x)) << ADC_JCMR0_CH5_SHIFT)) & ADC_JCMR0_CH5_MASK) + +#define ADC_JCMR0_CH6_MASK (0x40U) +#define ADC_JCMR0_CH6_SHIFT (6U) +/*! CH6 - Injected Conversion Mask for Channel 6 + * 0b0..Injected conversion is disabled + * 0b1..Injected conversion is enabled + */ +#define ADC_JCMR0_CH6(x) (((uint32_t)(((uint32_t)(x)) << ADC_JCMR0_CH6_SHIFT)) & ADC_JCMR0_CH6_MASK) + +#define ADC_JCMR0_CH7_MASK (0x80U) +#define ADC_JCMR0_CH7_SHIFT (7U) +/*! CH7 - Injected Conversion Mask for Channel 7 + * 0b0..Injected conversion is disabled + * 0b1..Injected conversion is enabled + */ +#define ADC_JCMR0_CH7(x) (((uint32_t)(((uint32_t)(x)) << ADC_JCMR0_CH7_SHIFT)) & ADC_JCMR0_CH7_MASK) +/*! @} */ + +/*! @name JCMR1 - Injected Conversion Mask 1 */ +/*! @{ */ + +#define ADC_JCMR1_CH32_MASK (0x1U) +#define ADC_JCMR1_CH32_SHIFT (0U) +/*! CH32 - Injected Conversion Mask for Channel 32 + * 0b0..Injected conversion is disabled + * 0b1..Injected conversion is enabled + */ +#define ADC_JCMR1_CH32(x) (((uint32_t)(((uint32_t)(x)) << ADC_JCMR1_CH32_SHIFT)) & ADC_JCMR1_CH32_MASK) + +#define ADC_JCMR1_CH33_MASK (0x2U) +#define ADC_JCMR1_CH33_SHIFT (1U) +/*! CH33 - Injected Conversion Mask for Channel 33 + * 0b0..Injected conversion is disabled + * 0b1..Injected conversion is enabled + */ +#define ADC_JCMR1_CH33(x) (((uint32_t)(((uint32_t)(x)) << ADC_JCMR1_CH33_SHIFT)) & ADC_JCMR1_CH33_MASK) + +#define ADC_JCMR1_CH34_MASK (0x4U) +#define ADC_JCMR1_CH34_SHIFT (2U) +/*! CH34 - Injected Conversion Mask for Channel 34 + * 0b0..Injected conversion is disabled + * 0b1..Injected conversion is enabled + */ +#define ADC_JCMR1_CH34(x) (((uint32_t)(((uint32_t)(x)) << ADC_JCMR1_CH34_SHIFT)) & ADC_JCMR1_CH34_MASK) + +#define ADC_JCMR1_CH35_MASK (0x8U) +#define ADC_JCMR1_CH35_SHIFT (3U) +/*! CH35 - Injected Conversion Mask for Channel 35 + * 0b0..Injected conversion is disabled + * 0b1..Injected conversion is enabled + */ +#define ADC_JCMR1_CH35(x) (((uint32_t)(((uint32_t)(x)) << ADC_JCMR1_CH35_SHIFT)) & ADC_JCMR1_CH35_MASK) + +#define ADC_JCMR1_CH36_MASK (0x10U) +#define ADC_JCMR1_CH36_SHIFT (4U) +/*! CH36 - Injected Conversion Mask for Channel 36 + * 0b0..Injected conversion is disabled + * 0b1..Injected conversion is enabled + */ +#define ADC_JCMR1_CH36(x) (((uint32_t)(((uint32_t)(x)) << ADC_JCMR1_CH36_SHIFT)) & ADC_JCMR1_CH36_MASK) + +#define ADC_JCMR1_CH37_MASK (0x20U) +#define ADC_JCMR1_CH37_SHIFT (5U) +/*! CH37 - Injected Conversion Mask for Channel 37 + * 0b0..Injected conversion is disabled + * 0b1..Injected conversion is enabled + */ +#define ADC_JCMR1_CH37(x) (((uint32_t)(((uint32_t)(x)) << ADC_JCMR1_CH37_SHIFT)) & ADC_JCMR1_CH37_MASK) + +#define ADC_JCMR1_CH38_MASK (0x40U) +#define ADC_JCMR1_CH38_SHIFT (6U) +/*! CH38 - Injected Conversion Mask for Channel 38 + * 0b0..Injected conversion is disabled + * 0b1..Injected conversion is enabled + */ +#define ADC_JCMR1_CH38(x) (((uint32_t)(((uint32_t)(x)) << ADC_JCMR1_CH38_SHIFT)) & ADC_JCMR1_CH38_MASK) + +#define ADC_JCMR1_CH39_MASK (0x80U) +#define ADC_JCMR1_CH39_SHIFT (7U) +/*! CH39 - Injected Conversion Mask for Channel 39 + * 0b0..Injected conversion is disabled + * 0b1..Injected conversion is enabled + */ +#define ADC_JCMR1_CH39(x) (((uint32_t)(((uint32_t)(x)) << ADC_JCMR1_CH39_SHIFT)) & ADC_JCMR1_CH39_MASK) +/*! @} */ + +/*! @name USROFSGN - User OFFSET and Gain */ +/*! @{ */ + +#define ADC_USROFSGN_OFFSUSER_MASK (0xFFU) +#define ADC_USROFSGN_OFFSUSER_SHIFT (0U) +/*! OFFSUSER - User Defined Offset */ +#define ADC_USROFSGN_OFFSUSER(x) (((uint32_t)(((uint32_t)(x)) << ADC_USROFSGN_OFFSUSER_SHIFT)) & ADC_USROFSGN_OFFSUSER_MASK) + +#define ADC_USROFSGN_GAINUSER_MASK (0x3FF0000U) +#define ADC_USROFSGN_GAINUSER_SHIFT (16U) +/*! GAINUSER - User-Defined Gain Value */ +#define ADC_USROFSGN_GAINUSER(x) (((uint32_t)(((uint32_t)(x)) << ADC_USROFSGN_GAINUSER_SHIFT)) & ADC_USROFSGN_GAINUSER_MASK) +/*! @} */ + +/*! @name PDEDR - Power Down Exit Delay */ +/*! @{ */ + +#define ADC_PDEDR_PDED_MASK (0xFFU) +#define ADC_PDEDR_PDED_SHIFT (0U) +/*! PDED - Power Down Exist Delay */ +#define ADC_PDEDR_PDED(x) (((uint32_t)(((uint32_t)(x)) << ADC_PDEDR_PDED_SHIFT)) & ADC_PDEDR_PDED_MASK) +/*! @} */ + +/*! @name PCDR - Precision Channel n Data */ +/*! @{ */ + +#define ADC_PCDR_CDATA_MASK (0xFFFU) +#define ADC_PCDR_CDATA_SHIFT (0U) +/*! CDATA - Channel Converted Data */ +#define ADC_PCDR_CDATA(x) (((uint32_t)(((uint32_t)(x)) << ADC_PCDR_CDATA_SHIFT)) & ADC_PCDR_CDATA_MASK) + +#define ADC_PCDR_RESULT_MASK (0x30000U) +#define ADC_PCDR_RESULT_SHIFT (16U) +/*! RESULT - Mode of Conversion Status + * 0b00..Data is a result of Normal conversion mode + * 0b01..Data is a result of Injected conversion mode + * 0b10..Data is a result of CTU conversion mode + * 0b11..Reserved + */ +#define ADC_PCDR_RESULT(x) (((uint32_t)(((uint32_t)(x)) << ADC_PCDR_RESULT_SHIFT)) & ADC_PCDR_RESULT_MASK) + +#define ADC_PCDR_OVERW_MASK (0x40000U) +#define ADC_PCDR_OVERW_SHIFT (18U) +/*! OVERW - Data Overwrite + * 0b0..Data not overwritten + * 0b1..Data overwritten + */ +#define ADC_PCDR_OVERW(x) (((uint32_t)(((uint32_t)(x)) << ADC_PCDR_OVERW_SHIFT)) & ADC_PCDR_OVERW_MASK) + +#define ADC_PCDR_VALID_MASK (0x80000U) +#define ADC_PCDR_VALID_SHIFT (19U) +/*! VALID - Conversion Data Valid + * 0b0..Not valid data + * 0b1..Valid data + */ +#define ADC_PCDR_VALID(x) (((uint32_t)(((uint32_t)(x)) << ADC_PCDR_VALID_SHIFT)) & ADC_PCDR_VALID_MASK) +/*! @} */ + +/* The count of ADC_PCDR */ +#define ADC_PCDR_COUNT (8U) + +/*! @name ICDR - Internal Channel n Data */ +/*! @{ */ + +#define ADC_ICDR_CDATA_MASK (0xFFFU) +#define ADC_ICDR_CDATA_SHIFT (0U) +/*! CDATA - Channel Converted Data */ +#define ADC_ICDR_CDATA(x) (((uint32_t)(((uint32_t)(x)) << ADC_ICDR_CDATA_SHIFT)) & ADC_ICDR_CDATA_MASK) + +#define ADC_ICDR_RESULT_MASK (0x30000U) +#define ADC_ICDR_RESULT_SHIFT (16U) +/*! RESULT - Mode of Conversion Status + * 0b00..Data is a result of Normal conversion mode + * 0b01..Data is a result of Injected conversion mode + * 0b10..Data is a result of CTU conversion mode + * 0b11..Reserved + */ +#define ADC_ICDR_RESULT(x) (((uint32_t)(((uint32_t)(x)) << ADC_ICDR_RESULT_SHIFT)) & ADC_ICDR_RESULT_MASK) + +#define ADC_ICDR_OVERW_MASK (0x40000U) +#define ADC_ICDR_OVERW_SHIFT (18U) +/*! OVERW - Data Overwrite + * 0b0..Data not overwritten + * 0b1..Data overwritten + */ +#define ADC_ICDR_OVERW(x) (((uint32_t)(((uint32_t)(x)) << ADC_ICDR_OVERW_SHIFT)) & ADC_ICDR_OVERW_MASK) + +#define ADC_ICDR_VALID_MASK (0x80000U) +#define ADC_ICDR_VALID_SHIFT (19U) +/*! VALID - Conversion Data Valid + * 0b0..Not valid data + * 0b1..Valid data + */ +#define ADC_ICDR_VALID(x) (((uint32_t)(((uint32_t)(x)) << ADC_ICDR_VALID_SHIFT)) & ADC_ICDR_VALID_MASK) +/*! @} */ + +/* The count of ADC_ICDR */ +#define ADC_ICDR_COUNT (8U) + +/*! @name THRHLR4 - Analog Watchdog Threshold 4 */ +/*! @{ */ + +#define ADC_THRHLR4_THRL_MASK (0xFFFU) +#define ADC_THRHLR4_THRL_SHIFT (0U) +/*! THRL - Low Threshold */ +#define ADC_THRHLR4_THRL(x) (((uint32_t)(((uint32_t)(x)) << ADC_THRHLR4_THRL_SHIFT)) & ADC_THRHLR4_THRL_MASK) + +#define ADC_THRHLR4_THRH_MASK (0xFFF0000U) +#define ADC_THRHLR4_THRH_SHIFT (16U) +/*! THRH - High Threshold */ +#define ADC_THRHLR4_THRH(x) (((uint32_t)(((uint32_t)(x)) << ADC_THRHLR4_THRH_SHIFT)) & ADC_THRHLR4_THRH_MASK) +/*! @} */ + +/*! @name THRHLR5 - Analog Watchdog Threshold 5 */ +/*! @{ */ + +#define ADC_THRHLR5_THRL_MASK (0xFFFU) +#define ADC_THRHLR5_THRL_SHIFT (0U) +/*! THRL - Low Threshold */ +#define ADC_THRHLR5_THRL(x) (((uint32_t)(((uint32_t)(x)) << ADC_THRHLR5_THRL_SHIFT)) & ADC_THRHLR5_THRL_MASK) + +#define ADC_THRHLR5_THRH_MASK (0xFFF0000U) +#define ADC_THRHLR5_THRH_SHIFT (16U) +/*! THRH - High Threshold */ +#define ADC_THRHLR5_THRH(x) (((uint32_t)(((uint32_t)(x)) << ADC_THRHLR5_THRH_SHIFT)) & ADC_THRHLR5_THRH_MASK) +/*! @} */ + +/*! @name THRHLR6 - Analog Watchdog Threshold 6 */ +/*! @{ */ + +#define ADC_THRHLR6_THRL_MASK (0xFFFU) +#define ADC_THRHLR6_THRL_SHIFT (0U) +/*! THRL - Low Threshold */ +#define ADC_THRHLR6_THRL(x) (((uint32_t)(((uint32_t)(x)) << ADC_THRHLR6_THRL_SHIFT)) & ADC_THRHLR6_THRL_MASK) + +#define ADC_THRHLR6_THRH_MASK (0xFFF0000U) +#define ADC_THRHLR6_THRH_SHIFT (16U) +/*! THRH - High Threshold */ +#define ADC_THRHLR6_THRH(x) (((uint32_t)(((uint32_t)(x)) << ADC_THRHLR6_THRH_SHIFT)) & ADC_THRHLR6_THRH_MASK) +/*! @} */ + +/*! @name THRHLR7 - Analog Watchdog Threshold 7 */ +/*! @{ */ + +#define ADC_THRHLR7_THRL_MASK (0xFFFU) +#define ADC_THRHLR7_THRL_SHIFT (0U) +/*! THRL - Low Threshold */ +#define ADC_THRHLR7_THRL(x) (((uint32_t)(((uint32_t)(x)) << ADC_THRHLR7_THRL_SHIFT)) & ADC_THRHLR7_THRL_MASK) + +#define ADC_THRHLR7_THRH_MASK (0xFFF0000U) +#define ADC_THRHLR7_THRH_SHIFT (16U) +/*! THRH - High Threshold */ +#define ADC_THRHLR7_THRH(x) (((uint32_t)(((uint32_t)(x)) << ADC_THRHLR7_THRH_SHIFT)) & ADC_THRHLR7_THRH_MASK) +/*! @} */ + +/*! @name CWSELR0 - Channel Watchdog Select 0 */ +/*! @{ */ + +#define ADC_CWSELR0_WSEL_CH0_MASK (0x7U) +#define ADC_CWSELR0_WSEL_CH0_SHIFT (0U) +/*! WSEL_CH0 - Channel Watchdog Select for Channel 0 */ +#define ADC_CWSELR0_WSEL_CH0(x) (((uint32_t)(((uint32_t)(x)) << ADC_CWSELR0_WSEL_CH0_SHIFT)) & ADC_CWSELR0_WSEL_CH0_MASK) + +#define ADC_CWSELR0_WSEL_CH1_MASK (0x70U) +#define ADC_CWSELR0_WSEL_CH1_SHIFT (4U) +/*! WSEL_CH1 - Channel Watchdog Select for Channel 1 */ +#define ADC_CWSELR0_WSEL_CH1(x) (((uint32_t)(((uint32_t)(x)) << ADC_CWSELR0_WSEL_CH1_SHIFT)) & ADC_CWSELR0_WSEL_CH1_MASK) + +#define ADC_CWSELR0_WSEL_CH2_MASK (0x700U) +#define ADC_CWSELR0_WSEL_CH2_SHIFT (8U) +/*! WSEL_CH2 - Channel Watchdog Select for Channel 2 */ +#define ADC_CWSELR0_WSEL_CH2(x) (((uint32_t)(((uint32_t)(x)) << ADC_CWSELR0_WSEL_CH2_SHIFT)) & ADC_CWSELR0_WSEL_CH2_MASK) + +#define ADC_CWSELR0_WSEL_CH3_MASK (0x7000U) +#define ADC_CWSELR0_WSEL_CH3_SHIFT (12U) +/*! WSEL_CH3 - Channel Watchdog Select for Channel 3 */ +#define ADC_CWSELR0_WSEL_CH3(x) (((uint32_t)(((uint32_t)(x)) << ADC_CWSELR0_WSEL_CH3_SHIFT)) & ADC_CWSELR0_WSEL_CH3_MASK) + +#define ADC_CWSELR0_WSEL_CH4_MASK (0x70000U) +#define ADC_CWSELR0_WSEL_CH4_SHIFT (16U) +/*! WSEL_CH4 - Channel Watchdog Select for Channel 4 */ +#define ADC_CWSELR0_WSEL_CH4(x) (((uint32_t)(((uint32_t)(x)) << ADC_CWSELR0_WSEL_CH4_SHIFT)) & ADC_CWSELR0_WSEL_CH4_MASK) + +#define ADC_CWSELR0_WSEL_CH5_MASK (0x700000U) +#define ADC_CWSELR0_WSEL_CH5_SHIFT (20U) +/*! WSEL_CH5 - Channel Watchdog Select for Channel 5 */ +#define ADC_CWSELR0_WSEL_CH5(x) (((uint32_t)(((uint32_t)(x)) << ADC_CWSELR0_WSEL_CH5_SHIFT)) & ADC_CWSELR0_WSEL_CH5_MASK) + +#define ADC_CWSELR0_WSEL_CH6_MASK (0x7000000U) +#define ADC_CWSELR0_WSEL_CH6_SHIFT (24U) +/*! WSEL_CH6 - Channel Watchdog Select for Channel 6 */ +#define ADC_CWSELR0_WSEL_CH6(x) (((uint32_t)(((uint32_t)(x)) << ADC_CWSELR0_WSEL_CH6_SHIFT)) & ADC_CWSELR0_WSEL_CH6_MASK) + +#define ADC_CWSELR0_WSEL_CH7_MASK (0x70000000U) +#define ADC_CWSELR0_WSEL_CH7_SHIFT (28U) +/*! WSEL_CH7 - Channel Watchdog Select for Channel 7 */ +#define ADC_CWSELR0_WSEL_CH7(x) (((uint32_t)(((uint32_t)(x)) << ADC_CWSELR0_WSEL_CH7_SHIFT)) & ADC_CWSELR0_WSEL_CH7_MASK) +/*! @} */ + +/*! @name CWSELR4 - Channel Watchdog Select 4 */ +/*! @{ */ + +#define ADC_CWSELR4_WSEL_CH32_MASK (0x7U) +#define ADC_CWSELR4_WSEL_CH32_SHIFT (0U) +/*! WSEL_CH32 - Channel Watchdog Select for Channel 32 */ +#define ADC_CWSELR4_WSEL_CH32(x) (((uint32_t)(((uint32_t)(x)) << ADC_CWSELR4_WSEL_CH32_SHIFT)) & ADC_CWSELR4_WSEL_CH32_MASK) + +#define ADC_CWSELR4_WSEL_CH33_MASK (0x70U) +#define ADC_CWSELR4_WSEL_CH33_SHIFT (4U) +/*! WSEL_CH33 - Channel Watchdog Select for Channel 33 */ +#define ADC_CWSELR4_WSEL_CH33(x) (((uint32_t)(((uint32_t)(x)) << ADC_CWSELR4_WSEL_CH33_SHIFT)) & ADC_CWSELR4_WSEL_CH33_MASK) + +#define ADC_CWSELR4_WSEL_CH34_MASK (0x700U) +#define ADC_CWSELR4_WSEL_CH34_SHIFT (8U) +/*! WSEL_CH34 - Channel Watchdog Select for Channel 34 */ +#define ADC_CWSELR4_WSEL_CH34(x) (((uint32_t)(((uint32_t)(x)) << ADC_CWSELR4_WSEL_CH34_SHIFT)) & ADC_CWSELR4_WSEL_CH34_MASK) + +#define ADC_CWSELR4_WSEL_CH35_MASK (0x7000U) +#define ADC_CWSELR4_WSEL_CH35_SHIFT (12U) +/*! WSEL_CH35 - Channel Watchdog Select for Channel 35 */ +#define ADC_CWSELR4_WSEL_CH35(x) (((uint32_t)(((uint32_t)(x)) << ADC_CWSELR4_WSEL_CH35_SHIFT)) & ADC_CWSELR4_WSEL_CH35_MASK) + +#define ADC_CWSELR4_WSEL_CH36_MASK (0x70000U) +#define ADC_CWSELR4_WSEL_CH36_SHIFT (16U) +/*! WSEL_CH36 - Channel Watchdog Select for Channel 36 */ +#define ADC_CWSELR4_WSEL_CH36(x) (((uint32_t)(((uint32_t)(x)) << ADC_CWSELR4_WSEL_CH36_SHIFT)) & ADC_CWSELR4_WSEL_CH36_MASK) + +#define ADC_CWSELR4_WSEL_CH37_MASK (0x700000U) +#define ADC_CWSELR4_WSEL_CH37_SHIFT (20U) +/*! WSEL_CH37 - Channel Watchdog Select for Channel 37 */ +#define ADC_CWSELR4_WSEL_CH37(x) (((uint32_t)(((uint32_t)(x)) << ADC_CWSELR4_WSEL_CH37_SHIFT)) & ADC_CWSELR4_WSEL_CH37_MASK) + +#define ADC_CWSELR4_WSEL_CH38_MASK (0x7000000U) +#define ADC_CWSELR4_WSEL_CH38_SHIFT (24U) +/*! WSEL_CH38 - Channel Watchdog Select for Channel 38 */ +#define ADC_CWSELR4_WSEL_CH38(x) (((uint32_t)(((uint32_t)(x)) << ADC_CWSELR4_WSEL_CH38_SHIFT)) & ADC_CWSELR4_WSEL_CH38_MASK) + +#define ADC_CWSELR4_WSEL_CH39_MASK (0x70000000U) +#define ADC_CWSELR4_WSEL_CH39_SHIFT (28U) +/*! WSEL_CH39 - Channel Watchdog Select for Channel 39 */ +#define ADC_CWSELR4_WSEL_CH39(x) (((uint32_t)(((uint32_t)(x)) << ADC_CWSELR4_WSEL_CH39_SHIFT)) & ADC_CWSELR4_WSEL_CH39_MASK) +/*! @} */ + +/*! @name CWENR0 - Channel Watchdog Enable 0 */ +/*! @{ */ + +#define ADC_CWENR0_CWEN0_MASK (0x1U) +#define ADC_CWENR0_CWEN0_SHIFT (0U) +/*! CWEN0 - Watchdog Enable for Channel 0 + * 0b0..Watchdog is disabled + * 0b1..Watchdog is enabled + */ +#define ADC_CWENR0_CWEN0(x) (((uint32_t)(((uint32_t)(x)) << ADC_CWENR0_CWEN0_SHIFT)) & ADC_CWENR0_CWEN0_MASK) + +#define ADC_CWENR0_CWEN1_MASK (0x2U) +#define ADC_CWENR0_CWEN1_SHIFT (1U) +/*! CWEN1 - Watchdog Enable for Channel 1 + * 0b0..Watchdog is disabled + * 0b1..Watchdog is enabled + */ +#define ADC_CWENR0_CWEN1(x) (((uint32_t)(((uint32_t)(x)) << ADC_CWENR0_CWEN1_SHIFT)) & ADC_CWENR0_CWEN1_MASK) + +#define ADC_CWENR0_CWEN2_MASK (0x4U) +#define ADC_CWENR0_CWEN2_SHIFT (2U) +/*! CWEN2 - Watchdog Enable for Channel 2 + * 0b0..Watchdog is disabled + * 0b1..Watchdog is enabled + */ +#define ADC_CWENR0_CWEN2(x) (((uint32_t)(((uint32_t)(x)) << ADC_CWENR0_CWEN2_SHIFT)) & ADC_CWENR0_CWEN2_MASK) + +#define ADC_CWENR0_CWEN3_MASK (0x8U) +#define ADC_CWENR0_CWEN3_SHIFT (3U) +/*! CWEN3 - Watchdog Enable for Channel 3 + * 0b0..Watchdog is disabled + * 0b1..Watchdog is enabled + */ +#define ADC_CWENR0_CWEN3(x) (((uint32_t)(((uint32_t)(x)) << ADC_CWENR0_CWEN3_SHIFT)) & ADC_CWENR0_CWEN3_MASK) + +#define ADC_CWENR0_CWEN4_MASK (0x10U) +#define ADC_CWENR0_CWEN4_SHIFT (4U) +/*! CWEN4 - Watchdog Enable for Channel 4 + * 0b0..Watchdog is disabled + * 0b1..Watchdog is enabled + */ +#define ADC_CWENR0_CWEN4(x) (((uint32_t)(((uint32_t)(x)) << ADC_CWENR0_CWEN4_SHIFT)) & ADC_CWENR0_CWEN4_MASK) + +#define ADC_CWENR0_CWEN5_MASK (0x20U) +#define ADC_CWENR0_CWEN5_SHIFT (5U) +/*! CWEN5 - Watchdog Enable for Channel 5 + * 0b0..Watchdog is disabled + * 0b1..Watchdog is enabled + */ +#define ADC_CWENR0_CWEN5(x) (((uint32_t)(((uint32_t)(x)) << ADC_CWENR0_CWEN5_SHIFT)) & ADC_CWENR0_CWEN5_MASK) + +#define ADC_CWENR0_CWEN6_MASK (0x40U) +#define ADC_CWENR0_CWEN6_SHIFT (6U) +/*! CWEN6 - Watchdog Enable for Channel 6 + * 0b0..Watchdog is disabled + * 0b1..Watchdog is enabled + */ +#define ADC_CWENR0_CWEN6(x) (((uint32_t)(((uint32_t)(x)) << ADC_CWENR0_CWEN6_SHIFT)) & ADC_CWENR0_CWEN6_MASK) + +#define ADC_CWENR0_CWEN7_MASK (0x80U) +#define ADC_CWENR0_CWEN7_SHIFT (7U) +/*! CWEN7 - Watchdog Enable for Channel 7 + * 0b0..Watchdog is disabled + * 0b1..Watchdog is enabled + */ +#define ADC_CWENR0_CWEN7(x) (((uint32_t)(((uint32_t)(x)) << ADC_CWENR0_CWEN7_SHIFT)) & ADC_CWENR0_CWEN7_MASK) +/*! @} */ + +/*! @name CWENR1 - Channel Watchdog Enable 1 */ +/*! @{ */ + +#define ADC_CWENR1_CWEN32_MASK (0x1U) +#define ADC_CWENR1_CWEN32_SHIFT (0U) +/*! CWEN32 - Watchdog Enable for Channel 32 + * 0b0..Watchdog is disabled + * 0b1..Watchdog is enabled + */ +#define ADC_CWENR1_CWEN32(x) (((uint32_t)(((uint32_t)(x)) << ADC_CWENR1_CWEN32_SHIFT)) & ADC_CWENR1_CWEN32_MASK) + +#define ADC_CWENR1_CWEN33_MASK (0x2U) +#define ADC_CWENR1_CWEN33_SHIFT (1U) +/*! CWEN33 - Watchdog Enable for Channel 33 + * 0b0..Watchdog is disabled + * 0b1..Watchdog is enabled + */ +#define ADC_CWENR1_CWEN33(x) (((uint32_t)(((uint32_t)(x)) << ADC_CWENR1_CWEN33_SHIFT)) & ADC_CWENR1_CWEN33_MASK) + +#define ADC_CWENR1_CWEN34_MASK (0x4U) +#define ADC_CWENR1_CWEN34_SHIFT (2U) +/*! CWEN34 - Watchdog Enable for Channel 34 + * 0b0..Watchdog is disabled + * 0b1..Watchdog is enabled + */ +#define ADC_CWENR1_CWEN34(x) (((uint32_t)(((uint32_t)(x)) << ADC_CWENR1_CWEN34_SHIFT)) & ADC_CWENR1_CWEN34_MASK) + +#define ADC_CWENR1_CWEN35_MASK (0x8U) +#define ADC_CWENR1_CWEN35_SHIFT (3U) +/*! CWEN35 - Watchdog Enable for Channel 35 + * 0b0..Watchdog is disabled + * 0b1..Watchdog is enabled + */ +#define ADC_CWENR1_CWEN35(x) (((uint32_t)(((uint32_t)(x)) << ADC_CWENR1_CWEN35_SHIFT)) & ADC_CWENR1_CWEN35_MASK) + +#define ADC_CWENR1_CWEN36_MASK (0x10U) +#define ADC_CWENR1_CWEN36_SHIFT (4U) +/*! CWEN36 - Watchdog Enable for Channel 36 + * 0b0..Watchdog is disabled + * 0b1..Watchdog is enabled + */ +#define ADC_CWENR1_CWEN36(x) (((uint32_t)(((uint32_t)(x)) << ADC_CWENR1_CWEN36_SHIFT)) & ADC_CWENR1_CWEN36_MASK) + +#define ADC_CWENR1_CWEN37_MASK (0x20U) +#define ADC_CWENR1_CWEN37_SHIFT (5U) +/*! CWEN37 - Watchdog Enable for Channel 37 + * 0b0..Watchdog is disabled + * 0b1..Watchdog is enabled + */ +#define ADC_CWENR1_CWEN37(x) (((uint32_t)(((uint32_t)(x)) << ADC_CWENR1_CWEN37_SHIFT)) & ADC_CWENR1_CWEN37_MASK) + +#define ADC_CWENR1_CWEN38_MASK (0x40U) +#define ADC_CWENR1_CWEN38_SHIFT (6U) +/*! CWEN38 - Watchdog Enable for Channel 38 + * 0b0..Watchdog is disabled + * 0b1..Watchdog is enabled + */ +#define ADC_CWENR1_CWEN38(x) (((uint32_t)(((uint32_t)(x)) << ADC_CWENR1_CWEN38_SHIFT)) & ADC_CWENR1_CWEN38_MASK) + +#define ADC_CWENR1_CWEN39_MASK (0x80U) +#define ADC_CWENR1_CWEN39_SHIFT (7U) +/*! CWEN39 - Watchdog Enable for Channel 39 + * 0b0..Watchdog is disabled + * 0b1..Watchdog is enabled + */ +#define ADC_CWENR1_CWEN39(x) (((uint32_t)(((uint32_t)(x)) << ADC_CWENR1_CWEN39_SHIFT)) & ADC_CWENR1_CWEN39_MASK) +/*! @} */ + +/*! @name AWORR0 - Analog Watchdog Out of Range 0 */ +/*! @{ */ + +#define ADC_AWORR0_AWOR_CH0_MASK (0x1U) +#define ADC_AWORR0_AWOR_CH0_SHIFT (0U) +/*! AWOR_CH0 - Analog Watchdog Out of Range for Channel 0 + * 0b0..Converted data is in range + * 0b0..No effect + * 0b1..Converted data is out of range + * 0b1..Clear the flag + */ +#define ADC_AWORR0_AWOR_CH0(x) (((uint32_t)(((uint32_t)(x)) << ADC_AWORR0_AWOR_CH0_SHIFT)) & ADC_AWORR0_AWOR_CH0_MASK) + +#define ADC_AWORR0_AWOR_CH1_MASK (0x2U) +#define ADC_AWORR0_AWOR_CH1_SHIFT (1U) +/*! AWOR_CH1 - Analog Watchdog Out of Range for Channel 1 + * 0b0..Converted data is in range + * 0b0..No effect + * 0b1..Converted data is out of range + * 0b1..Clear the flag + */ +#define ADC_AWORR0_AWOR_CH1(x) (((uint32_t)(((uint32_t)(x)) << ADC_AWORR0_AWOR_CH1_SHIFT)) & ADC_AWORR0_AWOR_CH1_MASK) + +#define ADC_AWORR0_AWOR_CH2_MASK (0x4U) +#define ADC_AWORR0_AWOR_CH2_SHIFT (2U) +/*! AWOR_CH2 - Analog Watchdog Out of Range for Channel 2 + * 0b0..Converted data is in range + * 0b0..No effect + * 0b1..Converted data is out of range + * 0b1..Clear the flag + */ +#define ADC_AWORR0_AWOR_CH2(x) (((uint32_t)(((uint32_t)(x)) << ADC_AWORR0_AWOR_CH2_SHIFT)) & ADC_AWORR0_AWOR_CH2_MASK) + +#define ADC_AWORR0_AWOR_CH3_MASK (0x8U) +#define ADC_AWORR0_AWOR_CH3_SHIFT (3U) +/*! AWOR_CH3 - Analog Watchdog Out of Range for Channel 3 + * 0b0..Converted data is in range + * 0b0..No effect + * 0b1..Converted data is out of range + * 0b1..Clear the flag + */ +#define ADC_AWORR0_AWOR_CH3(x) (((uint32_t)(((uint32_t)(x)) << ADC_AWORR0_AWOR_CH3_SHIFT)) & ADC_AWORR0_AWOR_CH3_MASK) + +#define ADC_AWORR0_AWOR_CH4_MASK (0x10U) +#define ADC_AWORR0_AWOR_CH4_SHIFT (4U) +/*! AWOR_CH4 - Analog Watchdog Out of Range for Channel 4 + * 0b0..Converted data is in range + * 0b0..No effect + * 0b1..Converted data is out of range + * 0b1..Clear the flag + */ +#define ADC_AWORR0_AWOR_CH4(x) (((uint32_t)(((uint32_t)(x)) << ADC_AWORR0_AWOR_CH4_SHIFT)) & ADC_AWORR0_AWOR_CH4_MASK) + +#define ADC_AWORR0_AWOR_CH5_MASK (0x20U) +#define ADC_AWORR0_AWOR_CH5_SHIFT (5U) +/*! AWOR_CH5 - Analog Watchdog Out of Range for Channel 5 + * 0b0..Converted data is in range + * 0b0..No effect + * 0b1..Converted data is out of range + * 0b1..Clear the flag + */ +#define ADC_AWORR0_AWOR_CH5(x) (((uint32_t)(((uint32_t)(x)) << ADC_AWORR0_AWOR_CH5_SHIFT)) & ADC_AWORR0_AWOR_CH5_MASK) + +#define ADC_AWORR0_AWOR_CH6_MASK (0x40U) +#define ADC_AWORR0_AWOR_CH6_SHIFT (6U) +/*! AWOR_CH6 - Analog Watchdog Out of Range for Channel 6 + * 0b0..Converted data is in range + * 0b0..No effect + * 0b1..Converted data is out of range + * 0b1..Clear the flag + */ +#define ADC_AWORR0_AWOR_CH6(x) (((uint32_t)(((uint32_t)(x)) << ADC_AWORR0_AWOR_CH6_SHIFT)) & ADC_AWORR0_AWOR_CH6_MASK) + +#define ADC_AWORR0_AWOR_CH7_MASK (0x80U) +#define ADC_AWORR0_AWOR_CH7_SHIFT (7U) +/*! AWOR_CH7 - Analog Watchdog Out of Range for Channel 7 + * 0b0..Converted data is in range + * 0b0..No effect + * 0b1..Converted data is out of range + * 0b1..Clear the flag + */ +#define ADC_AWORR0_AWOR_CH7(x) (((uint32_t)(((uint32_t)(x)) << ADC_AWORR0_AWOR_CH7_SHIFT)) & ADC_AWORR0_AWOR_CH7_MASK) +/*! @} */ + +/*! @name AWORR1 - Analog Watchdog Out of Range 1 */ +/*! @{ */ + +#define ADC_AWORR1_AWOR_CH32_MASK (0x1U) +#define ADC_AWORR1_AWOR_CH32_SHIFT (0U) +/*! AWOR_CH32 - Analog Watchdog Out of Range for Channel 32 + * 0b0..Converted data is in range + * 0b0..No effect + * 0b1..Converted data is out of range + * 0b1..Clear the flag + */ +#define ADC_AWORR1_AWOR_CH32(x) (((uint32_t)(((uint32_t)(x)) << ADC_AWORR1_AWOR_CH32_SHIFT)) & ADC_AWORR1_AWOR_CH32_MASK) + +#define ADC_AWORR1_AWOR_CH33_MASK (0x2U) +#define ADC_AWORR1_AWOR_CH33_SHIFT (1U) +/*! AWOR_CH33 - Analog Watchdog Out of Range for Channel 33 + * 0b0..Converted data is in range + * 0b0..No effect + * 0b1..Converted data is out of range + * 0b1..Clear the flag + */ +#define ADC_AWORR1_AWOR_CH33(x) (((uint32_t)(((uint32_t)(x)) << ADC_AWORR1_AWOR_CH33_SHIFT)) & ADC_AWORR1_AWOR_CH33_MASK) + +#define ADC_AWORR1_AWOR_CH34_MASK (0x4U) +#define ADC_AWORR1_AWOR_CH34_SHIFT (2U) +/*! AWOR_CH34 - Analog Watchdog Out of Range for Channel 34 + * 0b0..Converted data is in range + * 0b0..No effect + * 0b1..Converted data is out of range + * 0b1..Clear the flag + */ +#define ADC_AWORR1_AWOR_CH34(x) (((uint32_t)(((uint32_t)(x)) << ADC_AWORR1_AWOR_CH34_SHIFT)) & ADC_AWORR1_AWOR_CH34_MASK) + +#define ADC_AWORR1_AWOR_CH35_MASK (0x8U) +#define ADC_AWORR1_AWOR_CH35_SHIFT (3U) +/*! AWOR_CH35 - Analog Watchdog Out of Range for Channel 35 + * 0b0..Converted data is in range + * 0b0..No effect + * 0b1..Converted data is out of range + * 0b1..Clear the flag + */ +#define ADC_AWORR1_AWOR_CH35(x) (((uint32_t)(((uint32_t)(x)) << ADC_AWORR1_AWOR_CH35_SHIFT)) & ADC_AWORR1_AWOR_CH35_MASK) + +#define ADC_AWORR1_AWOR_CH36_MASK (0x10U) +#define ADC_AWORR1_AWOR_CH36_SHIFT (4U) +/*! AWOR_CH36 - Analog Watchdog Out of Range for Channel 36 + * 0b0..Converted data is in range + * 0b0..No effect + * 0b1..Converted data is out of range + * 0b1..Clear the flag + */ +#define ADC_AWORR1_AWOR_CH36(x) (((uint32_t)(((uint32_t)(x)) << ADC_AWORR1_AWOR_CH36_SHIFT)) & ADC_AWORR1_AWOR_CH36_MASK) + +#define ADC_AWORR1_AWOR_CH37_MASK (0x20U) +#define ADC_AWORR1_AWOR_CH37_SHIFT (5U) +/*! AWOR_CH37 - Analog Watchdog Out of Range for Channel 37 + * 0b0..Converted data is in range + * 0b0..No effect + * 0b1..Converted data is out of range + * 0b1..Clear the flag + */ +#define ADC_AWORR1_AWOR_CH37(x) (((uint32_t)(((uint32_t)(x)) << ADC_AWORR1_AWOR_CH37_SHIFT)) & ADC_AWORR1_AWOR_CH37_MASK) + +#define ADC_AWORR1_AWOR_CH38_MASK (0x40U) +#define ADC_AWORR1_AWOR_CH38_SHIFT (6U) +/*! AWOR_CH38 - Analog Watchdog Out of Range for Channel 38 + * 0b0..Converted data is in range + * 0b0..No effect + * 0b1..Converted data is out of range + * 0b1..Clear the flag + */ +#define ADC_AWORR1_AWOR_CH38(x) (((uint32_t)(((uint32_t)(x)) << ADC_AWORR1_AWOR_CH38_SHIFT)) & ADC_AWORR1_AWOR_CH38_MASK) + +#define ADC_AWORR1_AWOR_CH39_MASK (0x80U) +#define ADC_AWORR1_AWOR_CH39_SHIFT (7U) +/*! AWOR_CH39 - Analog Watchdog Out of Range for Channel 39 + * 0b0..Converted data is in range + * 0b0..No effect + * 0b1..Converted data is out of range + * 0b1..Clear the flag + */ +#define ADC_AWORR1_AWOR_CH39(x) (((uint32_t)(((uint32_t)(x)) << ADC_AWORR1_AWOR_CH39_SHIFT)) & ADC_AWORR1_AWOR_CH39_MASK) +/*! @} */ + +/*! @name STCR1 - Self-Test Configuration 1 */ +/*! @{ */ + +#define ADC_STCR1_INPSAMP_S_MASK (0xFF00U) +#define ADC_STCR1_INPSAMP_S_SHIFT (8U) +/*! INPSAMP_S - Sampling Configuration for Algorithm S */ +#define ADC_STCR1_INPSAMP_S(x) (((uint32_t)(((uint32_t)(x)) << ADC_STCR1_INPSAMP_S_SHIFT)) & ADC_STCR1_INPSAMP_S_MASK) + +#define ADC_STCR1_INPSAMP_C_MASK (0xFF000000U) +#define ADC_STCR1_INPSAMP_C_SHIFT (24U) +/*! INPSAMP_C - Sampling Configuration for Algorithm C */ +#define ADC_STCR1_INPSAMP_C(x) (((uint32_t)(((uint32_t)(x)) << ADC_STCR1_INPSAMP_C_SHIFT)) & ADC_STCR1_INPSAMP_C_MASK) +/*! @} */ + +/*! @name STCR2 - Self-Test Configuration 2 */ +/*! @{ */ + +#define ADC_STCR2_FMA_S_MASK (0x1U) +#define ADC_STCR2_FMA_S_SHIFT (0U) +/*! FMA_S - Fault Mapping for BGAP Algorithm + * 0b0..NCF + * 0b1..CF + */ +#define ADC_STCR2_FMA_S(x) (((uint32_t)(((uint32_t)(x)) << ADC_STCR2_FMA_S_SHIFT)) & ADC_STCR2_FMA_S_MASK) + +#define ADC_STCR2_FMA_C_MASK (0x4U) +#define ADC_STCR2_FMA_C_SHIFT (2U) +/*! FMA_C - Fault Mapping for Algorithm C + * 0b0..NCF + * 0b1..CF + */ +#define ADC_STCR2_FMA_C(x) (((uint32_t)(((uint32_t)(x)) << ADC_STCR2_FMA_C_SHIFT)) & ADC_STCR2_FMA_C_MASK) + +#define ADC_STCR2_FMA_WDTERR_MASK (0x8U) +#define ADC_STCR2_FMA_WDTERR_SHIFT (3U) +/*! FMA_WDTERR - Fault Mapping for Watchdog Timer Error + * 0b0..NCF + * 0b1..CF + */ +#define ADC_STCR2_FMA_WDTERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_STCR2_FMA_WDTERR_SHIFT)) & ADC_STCR2_FMA_WDTERR_MASK) + +#define ADC_STCR2_FMA_WDSERR_MASK (0x10U) +#define ADC_STCR2_FMA_WDSERR_SHIFT (4U) +/*! FMA_WDSERR - Fault Mapping for Watchdog Sequence Error + * 0b0..NCF mapping + * 0b1..CF mapping + */ +#define ADC_STCR2_FMA_WDSERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_STCR2_FMA_WDSERR_SHIFT)) & ADC_STCR2_FMA_WDSERR_MASK) + +#define ADC_STCR2_EN_MASK (0x80U) +#define ADC_STCR2_EN_SHIFT (7U) +/*! EN - Self-Testing Channel Enable + * 0b0..Disable + * 0b1..Enable + */ +#define ADC_STCR2_EN(x) (((uint32_t)(((uint32_t)(x)) << ADC_STCR2_EN_SHIFT)) & ADC_STCR2_EN_MASK) + +#define ADC_STCR2_MSKERR_S0_MASK (0x800U) +#define ADC_STCR2_MSKERR_S0_SHIFT (11U) +/*! MSKERR_S0 - Error on Algorithm S0 Channel Interrupt Mask + * 0b0..Interrupt disabled + * 0b1..Interrupt enabled + */ +#define ADC_STCR2_MSKERR_S0(x) (((uint32_t)(((uint32_t)(x)) << ADC_STCR2_MSKERR_S0_SHIFT)) & ADC_STCR2_MSKERR_S0_MASK) + +#define ADC_STCR2_MSKERR_S1_MASK (0x1000U) +#define ADC_STCR2_MSKERR_S1_SHIFT (12U) +/*! MSKERR_S1 - Error on Algorithm S1 Channel Interrupt Mask + * 0b0..Interrupt disabled + * 0b1..Interrupt enabled + */ +#define ADC_STCR2_MSKERR_S1(x) (((uint32_t)(((uint32_t)(x)) << ADC_STCR2_MSKERR_S1_SHIFT)) & ADC_STCR2_MSKERR_S1_MASK) + +#define ADC_STCR2_MSKERR_S2_MASK (0x2000U) +#define ADC_STCR2_MSKERR_S2_SHIFT (13U) +/*! MSKERR_S2 - Error on Algorithm S2 Channel Interrupt Mask + * 0b0..Interrupt disabled + * 0b1..Interrupt enabled + */ +#define ADC_STCR2_MSKERR_S2(x) (((uint32_t)(((uint32_t)(x)) << ADC_STCR2_MSKERR_S2_SHIFT)) & ADC_STCR2_MSKERR_S2_MASK) + +#define ADC_STCR2_MSKERR_C_MASK (0x8000U) +#define ADC_STCR2_MSKERR_C_SHIFT (15U) +/*! MSKERR_C - Error on Algorithm C Channel Interrupt Mask + * 0b0..Interrupt disabled + * 0b1..Interrupt enabled + */ +#define ADC_STCR2_MSKERR_C(x) (((uint32_t)(((uint32_t)(x)) << ADC_STCR2_MSKERR_C_SHIFT)) & ADC_STCR2_MSKERR_C_MASK) + +#define ADC_STCR2_MSKWDG_EOA_S_MASK (0x10000U) +#define ADC_STCR2_MSKWDG_EOA_S_SHIFT (16U) +/*! MSKWDG_EOA_S - End of Algorithm S Interrupt Mask + * 0b0..Interrupt disabled + * 0b1..Interrupt enabled + */ +#define ADC_STCR2_MSKWDG_EOA_S(x) (((uint32_t)(((uint32_t)(x)) << ADC_STCR2_MSKWDG_EOA_S_SHIFT)) & ADC_STCR2_MSKWDG_EOA_S_MASK) + +#define ADC_STCR2_MSKWDG_EOA_C_MASK (0x40000U) +#define ADC_STCR2_MSKWDG_EOA_C_SHIFT (18U) +/*! MSKWDG_EOA_C - End of Algorithm C Interrupt Mask + * 0b0..Interrupt disabled + * 0b1..Interrupt enabled + */ +#define ADC_STCR2_MSKWDG_EOA_C(x) (((uint32_t)(((uint32_t)(x)) << ADC_STCR2_MSKWDG_EOA_C_SHIFT)) & ADC_STCR2_MSKWDG_EOA_C_MASK) + +#define ADC_STCR2_MSKST_EOC_MASK (0x800000U) +#define ADC_STCR2_MSKST_EOC_SHIFT (23U) +/*! MSKST_EOC - Self-Test EOC Interrupt Mask + * 0b0..Interrupt disabled + * 0b1..Interrupt enabled + */ +#define ADC_STCR2_MSKST_EOC(x) (((uint32_t)(((uint32_t)(x)) << ADC_STCR2_MSKST_EOC_SHIFT)) & ADC_STCR2_MSKST_EOC_MASK) + +#define ADC_STCR2_MSKWDTERR_MASK (0x2000000U) +#define ADC_STCR2_MSKWDTERR_SHIFT (25U) +/*! MSKWDTERR - Watchdog Timer Error Interrupt Mask + * 0b0..Interrupt disabled + * 0b1..Interrupt enabled + */ +#define ADC_STCR2_MSKWDTERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_STCR2_MSKWDTERR_SHIFT)) & ADC_STCR2_MSKWDTERR_MASK) + +#define ADC_STCR2_SERR_MASK (0x4000000U) +#define ADC_STCR2_SERR_SHIFT (26U) +/*! SERR - Error Fault Injection Field (write-only) */ +#define ADC_STCR2_SERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_STCR2_SERR_SHIFT)) & ADC_STCR2_SERR_MASK) + +#define ADC_STCR2_MSKWDSERR_MASK (0x8000000U) +#define ADC_STCR2_MSKWDSERR_SHIFT (27U) +/*! MSKWDSERR - Watchdog Sequence Error Interrupt Mask + * 0b0..Interrupt disabled + * 0b1..Interrupt enabled + */ +#define ADC_STCR2_MSKWDSERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_STCR2_MSKWDSERR_SHIFT)) & ADC_STCR2_MSKWDSERR_MASK) +/*! @} */ + +/*! @name STCR3 - Self-Test Configuration 3 */ +/*! @{ */ + +#define ADC_STCR3_MSTEP_MASK (0x1FU) +#define ADC_STCR3_MSTEP_SHIFT (0U) +/*! MSTEP - Self-Test Step Select */ +#define ADC_STCR3_MSTEP(x) (((uint32_t)(((uint32_t)(x)) << ADC_STCR3_MSTEP_SHIFT)) & ADC_STCR3_MSTEP_MASK) + +#define ADC_STCR3_ALG_MASK (0x300U) +#define ADC_STCR3_ALG_SHIFT (8U) +/*! ALG - Self-Test Algorithm Select + * 0b00..Algorithm S + * 0b01..Reserved + * 0b10..Algorithm C + * 0b11..Algorithm S (for One-Shot Operation mode); Algorithm S + C (for Scan Operation mode) + */ +#define ADC_STCR3_ALG(x) (((uint32_t)(((uint32_t)(x)) << ADC_STCR3_ALG_SHIFT)) & ADC_STCR3_ALG_MASK) +/*! @} */ + +/*! @name STBRR - Self-Test Baud Rate */ +/*! @{ */ + +#define ADC_STBRR_BR_MASK (0xFFU) +#define ADC_STBRR_BR_SHIFT (0U) +/*! BR - Algorithm Baud Rate */ +#define ADC_STBRR_BR(x) (((uint32_t)(((uint32_t)(x)) << ADC_STBRR_BR_SHIFT)) & ADC_STBRR_BR_MASK) + +#define ADC_STBRR_WDT_MASK (0x70000U) +#define ADC_STBRR_WDT_SHIFT (16U) +/*! WDT - Watchdog Timer Value + * 0b000..0.1 ms ((0008h * Prescaler) cycles at 80 MHz) + * 0b001..0.5 ms ((0027h * Prescaler) cycles at 80 MHz) + * 0b010..1 ms ((004Eh * Prescaler) cycles at 80 MHz) + * 0b011..2 ms ((009Ch * Prescaler) cycles at 80 MHz) + * 0b100..5 ms ((0187h * Prescaler) cycles at 80 MHz) + * 0b101..10 ms ((030Dh * Prescaler) cycles at 80 MHz) + * 0b110..20 ms (061Ah * Prescaler) cycles at 80 MHz) + * 0b111..50 ms (0F42h *Prescaler) cycles at 80 MHz) + */ +#define ADC_STBRR_WDT(x) (((uint32_t)(((uint32_t)(x)) << ADC_STBRR_WDT_SHIFT)) & ADC_STBRR_WDT_MASK) +/*! @} */ + +/*! @name STSR1 - Self-Test Status 1 */ +/*! @{ */ + +#define ADC_STSR1_STEP_C_MASK (0x3E0U) +#define ADC_STSR1_STEP_C_SHIFT (5U) +/*! STEP_C - Algorithm C Step Number Error */ +#define ADC_STSR1_STEP_C(x) (((uint32_t)(((uint32_t)(x)) << ADC_STSR1_STEP_C_SHIFT)) & ADC_STSR1_STEP_C_MASK) + +#define ADC_STSR1_ERR_S0_MASK (0x800U) +#define ADC_STSR1_ERR_S0_SHIFT (11U) +/*! ERR_S0 - Algorithm S0 Error + * 0b0..No VREF error + * 0b0..No effect + * 0b1..VREF error occurred + * 0b1..Clear the flag + */ +#define ADC_STSR1_ERR_S0(x) (((uint32_t)(((uint32_t)(x)) << ADC_STSR1_ERR_S0_SHIFT)) & ADC_STSR1_ERR_S0_MASK) + +#define ADC_STSR1_ERR_S1_MASK (0x1000U) +#define ADC_STSR1_ERR_S1_SHIFT (12U) +/*! ERR_S1 - Algorithm S1 Error + * 0b0..No VDD ERROR + * 0b0..No effect + * 0b1..VDD ERROR occurred + * 0b1..Clear the flag + */ +#define ADC_STSR1_ERR_S1(x) (((uint32_t)(((uint32_t)(x)) << ADC_STSR1_ERR_S1_SHIFT)) & ADC_STSR1_ERR_S1_MASK) + +#define ADC_STSR1_ERR_S2_MASK (0x2000U) +#define ADC_STSR1_ERR_S2_SHIFT (13U) +/*! ERR_S2 - Algorithm S2 Error + * 0b0..No error occurred on the sampled signal + * 0b0..No effect + * 0b1..Error occurred on the sampled signal + * 0b1..Clear the flag + */ +#define ADC_STSR1_ERR_S2(x) (((uint32_t)(((uint32_t)(x)) << ADC_STSR1_ERR_S2_SHIFT)) & ADC_STSR1_ERR_S2_MASK) + +#define ADC_STSR1_ERR_C_MASK (0x8000U) +#define ADC_STSR1_ERR_C_SHIFT (15U) +/*! ERR_C - Algorithm C Error + * 0b0..No Algorithm C error + * 0b0..No effect + * 0b1..Algorithm C error occurred + * 0b1..Clear the flag + */ +#define ADC_STSR1_ERR_C(x) (((uint32_t)(((uint32_t)(x)) << ADC_STSR1_ERR_C_SHIFT)) & ADC_STSR1_ERR_C_MASK) + +#define ADC_STSR1_WDG_EOA_S_MASK (0x10000U) +#define ADC_STSR1_WDG_EOA_S_SHIFT (16U) +/*! WDG_EOA_S - Watchdog End of Algorithm S + * 0b0..Self-test end of Algorithm S conversion is not complete. + * 0b0..No effect + * 0b1..Self-test end of Algorithm S conversion is complete. + * 0b1..Clear the flag + */ +#define ADC_STSR1_WDG_EOA_S(x) (((uint32_t)(((uint32_t)(x)) << ADC_STSR1_WDG_EOA_S_SHIFT)) & ADC_STSR1_WDG_EOA_S_MASK) + +#define ADC_STSR1_WDG_EOA_C_MASK (0x40000U) +#define ADC_STSR1_WDG_EOA_C_SHIFT (18U) +/*! WDG_EOA_C - Watchdog End of Algorithm C + * 0b0..Self-test end of Algorithm C conversion is not complete + * 0b0..No effect + * 0b1..Self-test end of Algorithm C conversion is complete + * 0b1..Clear the flag + */ +#define ADC_STSR1_WDG_EOA_C(x) (((uint32_t)(((uint32_t)(x)) << ADC_STSR1_WDG_EOA_C_SHIFT)) & ADC_STSR1_WDG_EOA_C_MASK) + +#define ADC_STSR1_ST_EOC_MASK (0x800000U) +#define ADC_STSR1_ST_EOC_SHIFT (23U) +/*! ST_EOC - Self-Test EOC + * 0b0..Self-test end of conversion is not complete + * 0b0..No effect + * 0b1..Self-test end of conversion is complete + * 0b1..Clear the flag + */ +#define ADC_STSR1_ST_EOC(x) (((uint32_t)(((uint32_t)(x)) << ADC_STSR1_ST_EOC_SHIFT)) & ADC_STSR1_ST_EOC_MASK) + +#define ADC_STSR1_OVERWR_MASK (0x1000000U) +#define ADC_STSR1_OVERWR_SHIFT (24U) +/*! OVERWR - Overwrite Error + * 0b0..No overwrite error + * 0b0..No effect + * 0b1..Overwrite error occurred + * 0b1..Clear the flag + */ +#define ADC_STSR1_OVERWR(x) (((uint32_t)(((uint32_t)(x)) << ADC_STSR1_OVERWR_SHIFT)) & ADC_STSR1_OVERWR_MASK) + +#define ADC_STSR1_WDTERR_MASK (0x2000000U) +#define ADC_STSR1_WDTERR_SHIFT (25U) +/*! WDTERR - Watchdog Timer Error + * 0b0..No failure + * 0b0..No effect + * 0b1..Failure occurred + * 0b1..Clear the flag + */ +#define ADC_STSR1_WDTERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_STSR1_WDTERR_SHIFT)) & ADC_STSR1_WDTERR_MASK) + +#define ADC_STSR1_WDSERR_MASK (0x8000000U) +#define ADC_STSR1_WDSERR_SHIFT (27U) +/*! WDSERR - Watchdog Sequence Errors + * 0b0..No failure + * 0b0..No effect + * 0b1..Failure occurred + * 0b1..Clear the flag + */ +#define ADC_STSR1_WDSERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_STSR1_WDSERR_SHIFT)) & ADC_STSR1_WDSERR_MASK) +/*! @} */ + +/*! @name STSR2 - Self-Test Status 2 */ +/*! @{ */ + +#define ADC_STSR2_DATA0_MASK (0xFFFU) +#define ADC_STSR2_DATA0_SHIFT (0U) +/*! DATA0 - Test Channel Converted Data when ERR_S1 Occurred */ +#define ADC_STSR2_DATA0(x) (((uint32_t)(((uint32_t)(x)) << ADC_STSR2_DATA0_SHIFT)) & ADC_STSR2_DATA0_MASK) + +#define ADC_STSR2_DATA1_MASK (0xFFF0000U) +#define ADC_STSR2_DATA1_SHIFT (16U) +/*! DATA1 - Test Channel Converted Data when ERR_S1 Occurred */ +#define ADC_STSR2_DATA1(x) (((uint32_t)(((uint32_t)(x)) << ADC_STSR2_DATA1_SHIFT)) & ADC_STSR2_DATA1_MASK) + +#define ADC_STSR2_OVFL_MASK (0x80000000U) +#define ADC_STSR2_OVFL_SHIFT (31U) +/*! OVFL - Overflow Bit + * 0b0..Not overflow + * 0b1..Overflow + */ +#define ADC_STSR2_OVFL(x) (((uint32_t)(((uint32_t)(x)) << ADC_STSR2_OVFL_SHIFT)) & ADC_STSR2_OVFL_MASK) +/*! @} */ + +/*! @name STSR3 - Self-Test Status 3 */ +/*! @{ */ + +#define ADC_STSR3_DATA0_MASK (0xFFFU) +#define ADC_STSR3_DATA0_SHIFT (0U) +/*! DATA0 - Test Channel Converted Data when ERR_S0 Occurred */ +#define ADC_STSR3_DATA0(x) (((uint32_t)(((uint32_t)(x)) << ADC_STSR3_DATA0_SHIFT)) & ADC_STSR3_DATA0_MASK) + +#define ADC_STSR3_DATA1_MASK (0xFFF0000U) +#define ADC_STSR3_DATA1_SHIFT (16U) +/*! DATA1 - Test Channel Converted Data when ERR_C Occurred */ +#define ADC_STSR3_DATA1(x) (((uint32_t)(((uint32_t)(x)) << ADC_STSR3_DATA1_SHIFT)) & ADC_STSR3_DATA1_MASK) +/*! @} */ + +/*! @name STSR4 - Self-Test Status 4 */ +/*! @{ */ + +#define ADC_STSR4_DATA1_MASK (0xFFF0000U) +#define ADC_STSR4_DATA1_SHIFT (16U) +/*! DATA1 - Test Channel Converted Data When ERR_C Occurred */ +#define ADC_STSR4_DATA1(x) (((uint32_t)(((uint32_t)(x)) << ADC_STSR4_DATA1_SHIFT)) & ADC_STSR4_DATA1_MASK) +/*! @} */ + +/*! @name STDR1 - Self-Test Data 1 */ +/*! @{ */ + +#define ADC_STDR1_TCDATA_MASK (0xFFFU) +#define ADC_STDR1_TCDATA_SHIFT (0U) +/*! TCDATA - Test Channel Converted Data */ +#define ADC_STDR1_TCDATA(x) (((uint32_t)(((uint32_t)(x)) << ADC_STDR1_TCDATA_SHIFT)) & ADC_STDR1_TCDATA_MASK) + +#define ADC_STDR1_OWERWR_MASK (0x40000U) +#define ADC_STDR1_OWERWR_SHIFT (18U) +/*! OWERWR - Overwrite Data + * 0b0..Data not overwritten + * 0b1..Data overwritten + */ +#define ADC_STDR1_OWERWR(x) (((uint32_t)(((uint32_t)(x)) << ADC_STDR1_OWERWR_SHIFT)) & ADC_STDR1_OWERWR_MASK) + +#define ADC_STDR1_VALID_MASK (0x80000U) +#define ADC_STDR1_VALID_SHIFT (19U) +/*! VALID - Valid Data + * 0b0..Data not valid + * 0b1..Data valid + */ +#define ADC_STDR1_VALID(x) (((uint32_t)(((uint32_t)(x)) << ADC_STDR1_VALID_SHIFT)) & ADC_STDR1_VALID_MASK) +/*! @} */ + +/*! @name STDR2 - Self-Test Data 2 */ +/*! @{ */ + +#define ADC_STDR2_IDATA_MASK (0xFFFU) +#define ADC_STDR2_IDATA_SHIFT (0U) +/*! IDATA - Integer Data */ +#define ADC_STDR2_IDATA(x) (((uint32_t)(((uint32_t)(x)) << ADC_STDR2_IDATA_SHIFT)) & ADC_STDR2_IDATA_MASK) + +#define ADC_STDR2_OVERWR_MASK (0x40000U) +#define ADC_STDR2_OVERWR_SHIFT (18U) +/*! OVERWR - Overwrite Data + * 0b0..Data not overwritten + * 0b1..Data overwritten + */ +#define ADC_STDR2_OVERWR(x) (((uint32_t)(((uint32_t)(x)) << ADC_STDR2_OVERWR_SHIFT)) & ADC_STDR2_OVERWR_MASK) + +#define ADC_STDR2_VALID_MASK (0x80000U) +#define ADC_STDR2_VALID_SHIFT (19U) +/*! VALID - Valid Data + * 0b0..Data not valid + * 0b1..Data valid + */ +#define ADC_STDR2_VALID(x) (((uint32_t)(((uint32_t)(x)) << ADC_STDR2_VALID_SHIFT)) & ADC_STDR2_VALID_MASK) + +#define ADC_STDR2_FDATA_MASK (0xFFF00000U) +#define ADC_STDR2_FDATA_SHIFT (20U) +/*! FDATA - Fractional Data */ +#define ADC_STDR2_FDATA(x) (((uint32_t)(((uint32_t)(x)) << ADC_STDR2_FDATA_SHIFT)) & ADC_STDR2_FDATA_MASK) +/*! @} */ + +/*! @name STAW0R - Self-Test Analog Watchdog 0 */ +/*! @{ */ + +#define ADC_STAW0R_THRL_MASK (0xFFFU) +#define ADC_STAW0R_THRL_SHIFT (0U) +/*! THRL - Low Threshold Value for Algorithm S Step0 */ +#define ADC_STAW0R_THRL(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAW0R_THRL_SHIFT)) & ADC_STAW0R_THRL_MASK) + +#define ADC_STAW0R_THRH_MASK (0xFFF0000U) +#define ADC_STAW0R_THRH_SHIFT (16U) +/*! THRH - High Threshold Value for Algorithm S Step0 */ +#define ADC_STAW0R_THRH(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAW0R_THRH_SHIFT)) & ADC_STAW0R_THRH_MASK) + +#define ADC_STAW0R_WDTE_MASK (0x40000000U) +#define ADC_STAW0R_WDTE_SHIFT (30U) +/*! WDTE - Watchdog Timer Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define ADC_STAW0R_WDTE(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAW0R_WDTE_SHIFT)) & ADC_STAW0R_WDTE_MASK) + +#define ADC_STAW0R_AWDE_MASK (0x80000000U) +#define ADC_STAW0R_AWDE_SHIFT (31U) +/*! AWDE - Analog Watchdog Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define ADC_STAW0R_AWDE(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAW0R_AWDE_SHIFT)) & ADC_STAW0R_AWDE_MASK) +/*! @} */ + +/*! @name STAW1AR - Self-Test Analog Watchdog 1A */ +/*! @{ */ + +#define ADC_STAW1AR_THRL_MASK (0xFFFU) +#define ADC_STAW1AR_THRL_SHIFT (0U) +/*! THRL - Low Threshold Value for Algorithm S Step1 */ +#define ADC_STAW1AR_THRL(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAW1AR_THRL_SHIFT)) & ADC_STAW1AR_THRL_MASK) + +#define ADC_STAW1AR_THRH_MASK (0xFFF0000U) +#define ADC_STAW1AR_THRH_SHIFT (16U) +/*! THRH - High Threshold Value for Algorithm S Step1 */ +#define ADC_STAW1AR_THRH(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAW1AR_THRH_SHIFT)) & ADC_STAW1AR_THRH_MASK) + +#define ADC_STAW1AR_AWDE_MASK (0x80000000U) +#define ADC_STAW1AR_AWDE_SHIFT (31U) +/*! AWDE - Analog Watchdog Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define ADC_STAW1AR_AWDE(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAW1AR_AWDE_SHIFT)) & ADC_STAW1AR_AWDE_MASK) +/*! @} */ + +/*! @name STAW1BR - Self-Test Analog Watchdog 1B */ +/*! @{ */ + +#define ADC_STAW1BR_THRL_MASK (0xFFFU) +#define ADC_STAW1BR_THRL_SHIFT (0U) +/*! THRL - Low Threshold Value for Algorithm S Step1 */ +#define ADC_STAW1BR_THRL(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAW1BR_THRL_SHIFT)) & ADC_STAW1BR_THRL_MASK) + +#define ADC_STAW1BR_THRH_MASK (0xFFF0000U) +#define ADC_STAW1BR_THRH_SHIFT (16U) +/*! THRH - High Threshold Value for Algorithm S Step1 */ +#define ADC_STAW1BR_THRH(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAW1BR_THRH_SHIFT)) & ADC_STAW1BR_THRH_MASK) +/*! @} */ + +/*! @name STAW2R - Self-Test Analog Watchdog 2 */ +/*! @{ */ + +#define ADC_STAW2R_THRL_MASK (0xFFFU) +#define ADC_STAW2R_THRL_SHIFT (0U) +/*! THRL - Threshold level low */ +#define ADC_STAW2R_THRL(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAW2R_THRL_SHIFT)) & ADC_STAW2R_THRL_MASK) + +#define ADC_STAW2R_AWDE_MASK (0x80000000U) +#define ADC_STAW2R_AWDE_SHIFT (31U) +/*! AWDE - Analog Watchdog Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define ADC_STAW2R_AWDE(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAW2R_AWDE_SHIFT)) & ADC_STAW2R_AWDE_MASK) +/*! @} */ + +/*! @name STAW4R - Self-Test Analog Watchdog 4 */ +/*! @{ */ + +#define ADC_STAW4R_THRL_MASK (0xFFFU) +#define ADC_STAW4R_THRL_SHIFT (0U) +/*! THRL - Low Threshold Value for Step0 of Algorithm C */ +#define ADC_STAW4R_THRL(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAW4R_THRL_SHIFT)) & ADC_STAW4R_THRL_MASK) + +#define ADC_STAW4R_THRH_MASK (0xFFF0000U) +#define ADC_STAW4R_THRH_SHIFT (16U) +/*! THRH - High Threshold Value for Step0 of Algorithm C */ +#define ADC_STAW4R_THRH(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAW4R_THRH_SHIFT)) & ADC_STAW4R_THRH_MASK) + +#define ADC_STAW4R_WDTE_MASK (0x40000000U) +#define ADC_STAW4R_WDTE_SHIFT (30U) +/*! WDTE - Watchdog Timer Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define ADC_STAW4R_WDTE(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAW4R_WDTE_SHIFT)) & ADC_STAW4R_WDTE_MASK) + +#define ADC_STAW4R_AWDE_MASK (0x80000000U) +#define ADC_STAW4R_AWDE_SHIFT (31U) +/*! AWDE - Analog Watchdog Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define ADC_STAW4R_AWDE(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAW4R_AWDE_SHIFT)) & ADC_STAW4R_AWDE_MASK) +/*! @} */ + +/*! @name STAW5R - Self-Test Analog Watchdog 5 */ +/*! @{ */ + +#define ADC_STAW5R_THRL_MASK (0xFFFU) +#define ADC_STAW5R_THRL_SHIFT (0U) +/*! THRL - Low Threshold Value for Step0 of Algorithm C */ +#define ADC_STAW5R_THRL(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAW5R_THRL_SHIFT)) & ADC_STAW5R_THRL_MASK) + +#define ADC_STAW5R_THRH_MASK (0xFFF0000U) +#define ADC_STAW5R_THRH_SHIFT (16U) +/*! THRH - High Threshold Value for Step N of Algorithm C */ +#define ADC_STAW5R_THRH(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAW5R_THRH_SHIFT)) & ADC_STAW5R_THRH_MASK) +/*! @} */ + +/*! @name CALSTAT - Calibration Status */ +/*! @{ */ + +#define ADC_CALSTAT_STAT_1_MASK (0x1U) +#define ADC_CALSTAT_STAT_1_SHIFT (0U) +/*! STAT_1 - Status of Calibration Step 1 + * 0b0..Test passed + * 0b1..Test failed + */ +#define ADC_CALSTAT_STAT_1(x) (((uint32_t)(((uint32_t)(x)) << ADC_CALSTAT_STAT_1_SHIFT)) & ADC_CALSTAT_STAT_1_MASK) + +#define ADC_CALSTAT_STAT_2_MASK (0x2U) +#define ADC_CALSTAT_STAT_2_SHIFT (1U) +/*! STAT_2 - Status of Calibration Step 2 + * 0b0..Test passed + * 0b1..Test failed + */ +#define ADC_CALSTAT_STAT_2(x) (((uint32_t)(((uint32_t)(x)) << ADC_CALSTAT_STAT_2_SHIFT)) & ADC_CALSTAT_STAT_2_MASK) + +#define ADC_CALSTAT_STAT_3_MASK (0x4U) +#define ADC_CALSTAT_STAT_3_SHIFT (2U) +/*! STAT_3 - Status of Calibration Step 3 + * 0b0..Test passed + * 0b1..Test failed + */ +#define ADC_CALSTAT_STAT_3(x) (((uint32_t)(((uint32_t)(x)) << ADC_CALSTAT_STAT_3_SHIFT)) & ADC_CALSTAT_STAT_3_MASK) + +#define ADC_CALSTAT_STAT_4_MASK (0x8U) +#define ADC_CALSTAT_STAT_4_SHIFT (3U) +/*! STAT_4 - Status of calibration step 4 + * 0b0..Test passed + * 0b1..Test failed + */ +#define ADC_CALSTAT_STAT_4(x) (((uint32_t)(((uint32_t)(x)) << ADC_CALSTAT_STAT_4_SHIFT)) & ADC_CALSTAT_STAT_4_MASK) + +#define ADC_CALSTAT_STAT_5_MASK (0x10U) +#define ADC_CALSTAT_STAT_5_SHIFT (4U) +/*! STAT_5 - Status of Calibration Step 5 + * 0b0..Test passed + * 0b1..Test failed + */ +#define ADC_CALSTAT_STAT_5(x) (((uint32_t)(((uint32_t)(x)) << ADC_CALSTAT_STAT_5_SHIFT)) & ADC_CALSTAT_STAT_5_MASK) + +#define ADC_CALSTAT_STAT_6_MASK (0x20U) +#define ADC_CALSTAT_STAT_6_SHIFT (5U) +/*! STAT_6 - Status of Calibration Step 6 + * 0b0..Test passed + * 0b1..Test failed + */ +#define ADC_CALSTAT_STAT_6(x) (((uint32_t)(((uint32_t)(x)) << ADC_CALSTAT_STAT_6_SHIFT)) & ADC_CALSTAT_STAT_6_MASK) + +#define ADC_CALSTAT_STAT_7_MASK (0x40U) +#define ADC_CALSTAT_STAT_7_SHIFT (6U) +/*! STAT_7 - Status of Calibration Step 7 + * 0b0..Test passed + * 0b1..Test failed + */ +#define ADC_CALSTAT_STAT_7(x) (((uint32_t)(((uint32_t)(x)) << ADC_CALSTAT_STAT_7_SHIFT)) & ADC_CALSTAT_STAT_7_MASK) + +#define ADC_CALSTAT_STAT_8_MASK (0x80U) +#define ADC_CALSTAT_STAT_8_SHIFT (7U) +/*! STAT_8 - Status of Calibration Step 8 + * 0b0..Test passed + * 0b1..Test failed + */ +#define ADC_CALSTAT_STAT_8(x) (((uint32_t)(((uint32_t)(x)) << ADC_CALSTAT_STAT_8_SHIFT)) & ADC_CALSTAT_STAT_8_MASK) + +#define ADC_CALSTAT_STAT_9_MASK (0x100U) +#define ADC_CALSTAT_STAT_9_SHIFT (8U) +/*! STAT_9 - Status of Calibration Step 9 + * 0b0..Test passed + * 0b1..Test failed + */ +#define ADC_CALSTAT_STAT_9(x) (((uint32_t)(((uint32_t)(x)) << ADC_CALSTAT_STAT_9_SHIFT)) & ADC_CALSTAT_STAT_9_MASK) + +#define ADC_CALSTAT_STAT_10_MASK (0x200U) +#define ADC_CALSTAT_STAT_10_SHIFT (9U) +/*! STAT_10 - Status of Calibration Step 10 + * 0b0..Test passed + * 0b1..Test failed + */ +#define ADC_CALSTAT_STAT_10(x) (((uint32_t)(((uint32_t)(x)) << ADC_CALSTAT_STAT_10_SHIFT)) & ADC_CALSTAT_STAT_10_MASK) + +#define ADC_CALSTAT_STAT_11_MASK (0x400U) +#define ADC_CALSTAT_STAT_11_SHIFT (10U) +/*! STAT_11 - Status of Calibration Step 11 + * 0b0..Test passed + * 0b1..Test failed + */ +#define ADC_CALSTAT_STAT_11(x) (((uint32_t)(((uint32_t)(x)) << ADC_CALSTAT_STAT_11_SHIFT)) & ADC_CALSTAT_STAT_11_MASK) + +#define ADC_CALSTAT_STAT_12_MASK (0x800U) +#define ADC_CALSTAT_STAT_12_SHIFT (11U) +/*! STAT_12 - Status of Calibration Step 12 + * 0b0..Test passed + * 0b1..Test failed + */ +#define ADC_CALSTAT_STAT_12(x) (((uint32_t)(((uint32_t)(x)) << ADC_CALSTAT_STAT_12_SHIFT)) & ADC_CALSTAT_STAT_12_MASK) + +#define ADC_CALSTAT_TEST_RESULT_MASK (0xFFFF0000U) +#define ADC_CALSTAT_TEST_RESULT_SHIFT (16U) +/*! TEST_RESULT - TEST_RESULT */ +#define ADC_CALSTAT_TEST_RESULT(x) (((uint32_t)(((uint32_t)(x)) << ADC_CALSTAT_TEST_RESULT_SHIFT)) & ADC_CALSTAT_TEST_RESULT_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group ADC_Register_Masks */ + + +/* ADC - Peripheral instance base addresses */ +/** Peripheral ADC1 base address */ +#define ADC1_BASE (0x44530000u) +/** Peripheral ADC1 base pointer */ +#define ADC1 ((ADC_Type *)ADC1_BASE) +/** Array initializer of ADC peripheral base addresses */ +#define ADC_BASE_ADDRS { ADC1_BASE } +/** Array initializer of ADC peripheral base pointers */ +#define ADC_BASE_PTRS { ADC1 } + +/*! + * @} + */ /* end of group ADC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- ANA_OSC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ANA_OSC_Peripheral_Access_Layer ANA_OSC Peripheral Access Layer + * @{ + */ + +/** ANA_OSC - Register Layout Typedef */ +typedef struct { + uint8_t RESERVED_0[2048]; + __I uint32_t DIGPROG_DEVICE_ID; /**< Device ID, offset: 0x800 */ +} ANA_OSC_Type; + +/* ---------------------------------------------------------------------------- + -- ANA_OSC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ANA_OSC_Register_Masks ANA_OSC Register Masks + * @{ + */ + +/*! @name DIGPROG_DEVICE_ID - Device ID */ +/*! @{ */ + +#define ANA_OSC_DIGPROG_DEVICE_ID_DIGPROG_MINOR_MASK (0xFFU) +#define ANA_OSC_DIGPROG_DEVICE_ID_DIGPROG_MINOR_SHIFT (0U) +/*! DIGPROG_MINOR - Bit[3:0] is the metal layer revision. Bit[7:4] is the base layer revision. */ +#define ANA_OSC_DIGPROG_DEVICE_ID_DIGPROG_MINOR(x) (((uint32_t)(((uint32_t)(x)) << ANA_OSC_DIGPROG_DEVICE_ID_DIGPROG_MINOR_SHIFT)) & ANA_OSC_DIGPROG_DEVICE_ID_DIGPROG_MINOR_MASK) + +#define ANA_OSC_DIGPROG_DEVICE_ID_DIGPROG_MAJOR_LOWER_MASK (0xFF00U) +#define ANA_OSC_DIGPROG_DEVICE_ID_DIGPROG_MAJOR_LOWER_SHIFT (8U) +/*! DIGPROG_MAJOR_LOWER - DIGPROG_MAJOR_LOWER */ +#define ANA_OSC_DIGPROG_DEVICE_ID_DIGPROG_MAJOR_LOWER(x) (((uint32_t)(((uint32_t)(x)) << ANA_OSC_DIGPROG_DEVICE_ID_DIGPROG_MAJOR_LOWER_SHIFT)) & ANA_OSC_DIGPROG_DEVICE_ID_DIGPROG_MAJOR_LOWER_MASK) + +#define ANA_OSC_DIGPROG_DEVICE_ID_DIGPROG_MAJOR_UPPER_MASK (0xFF0000U) +#define ANA_OSC_DIGPROG_DEVICE_ID_DIGPROG_MAJOR_UPPER_SHIFT (16U) +/*! DIGPROG_MAJOR_UPPER - DIGPROG_MAJOR_UPPER */ +#define ANA_OSC_DIGPROG_DEVICE_ID_DIGPROG_MAJOR_UPPER(x) (((uint32_t)(((uint32_t)(x)) << ANA_OSC_DIGPROG_DEVICE_ID_DIGPROG_MAJOR_UPPER_SHIFT)) & ANA_OSC_DIGPROG_DEVICE_ID_DIGPROG_MAJOR_UPPER_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group ANA_OSC_Register_Masks */ + + +/* ANA_OSC - Peripheral instance base addresses */ +/** Peripheral ANA_OSC base address */ +#define ANA_OSC_BASE (0x44480000u) +/** Peripheral ANA_OSC base pointer */ +#define ANA_OSC ((ANA_OSC_Type *)ANA_OSC_BASE) +/** Array initializer of ANA_OSC peripheral base addresses */ +#define ANA_OSC_BASE_ADDRS { ANA_OSC_BASE } +/** Array initializer of ANA_OSC peripheral base pointers */ +#define ANA_OSC_BASE_PTRS { ANA_OSC } + +/*! + * @} + */ /* end of group ANA_OSC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- AXBS Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup AXBS_Peripheral_Access_Layer AXBS Peripheral Access Layer + * @{ + */ + +/** AXBS - Register Layout Typedef */ +typedef struct { + __IO uint32_t PRS0; /**< Priority Slave Registers, offset: 0x0 */ + uint8_t RESERVED_0[12]; + __IO uint32_t CRS0; /**< Control Register, offset: 0x10 */ + uint8_t RESERVED_1[236]; + __IO uint32_t PRS1; /**< Priority Slave Registers, offset: 0x100 */ + uint8_t RESERVED_2[12]; + __IO uint32_t CRS1; /**< Control Register, offset: 0x110 */ + uint8_t RESERVED_3[236]; + __IO uint32_t PRS2; /**< Priority Slave Registers, offset: 0x200 */ + uint8_t RESERVED_4[12]; + __IO uint32_t CRS2; /**< Control Register, offset: 0x210 */ + uint8_t RESERVED_5[236]; + __IO uint32_t PRS3; /**< Priority Slave Registers, offset: 0x300 */ + uint8_t RESERVED_6[12]; + __IO uint32_t CRS3; /**< Control Register, offset: 0x310 */ + uint8_t RESERVED_7[236]; + __IO uint32_t PRS4; /**< Priority Slave Registers, offset: 0x400 */ + uint8_t RESERVED_8[12]; + __IO uint32_t CRS4; /**< Control Register, offset: 0x410 */ + uint8_t RESERVED_9[236]; + __IO uint32_t PRS5; /**< Priority Slave Registers, offset: 0x500 */ + uint8_t RESERVED_10[12]; + __IO uint32_t CRS5; /**< Control Register, offset: 0x510 */ + uint8_t RESERVED_11[236]; + __IO uint32_t PRS6; /**< Priority Slave Registers, offset: 0x600 */ + uint8_t RESERVED_12[12]; + __IO uint32_t CRS6; /**< Control Register, offset: 0x610 */ + uint8_t RESERVED_13[236]; + __IO uint32_t PRS7; /**< Priority Slave Registers, offset: 0x700 */ + uint8_t RESERVED_14[12]; + __IO uint32_t CRS7; /**< Control Register, offset: 0x710 */ + uint8_t RESERVED_15[236]; + __IO uint32_t MGPCR0; /**< Master General Purpose Control Register, offset: 0x800 */ + uint8_t RESERVED_16[252]; + __IO uint32_t MGPCR1; /**< Master General Purpose Control Register, offset: 0x900 */ + uint8_t RESERVED_17[252]; + __IO uint32_t MGPCR2; /**< Master General Purpose Control Register, offset: 0xA00 */ + uint8_t RESERVED_18[252]; + __IO uint32_t MGPCR3; /**< Master General Purpose Control Register, offset: 0xB00 */ + uint8_t RESERVED_19[252]; + __IO uint32_t MGPCR4; /**< Master General Purpose Control Register, offset: 0xC00 */ + uint8_t RESERVED_20[252]; + __IO uint32_t MGPCR5; /**< Master General Purpose Control Register, offset: 0xD00 */ + uint8_t RESERVED_21[252]; + __IO uint32_t MGPCR6; /**< Master General Purpose Control Register, offset: 0xE00 */ + uint8_t RESERVED_22[252]; + __IO uint32_t MGPCR7; /**< Master General Purpose Control Register, offset: 0xF00 */ +} AXBS_Type; + +/* ---------------------------------------------------------------------------- + -- AXBS Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup AXBS_Register_Masks AXBS Register Masks + * @{ + */ + +/*! @name PRS0 - Priority Slave Registers */ +/*! @{ */ + +#define AXBS_PRS0_M0_MASK (0x7U) +#define AXBS_PRS0_M0_SHIFT (0U) +/*! M0 - Master 0 Priority + * 0b000..This master has level 1 or highest priority when accessing the slave port. + * 0b001..This master has level 2 priority when accessing the slave port. + * 0b010..This master has level 3 priority when accessing the slave port. + * 0b011..This master has level 4 priority when accessing the slave port. + * 0b100..This master has level 5 priority when accessing the slave port. + * 0b101..This master has level 6 priority when accessing the slave port. + * 0b110..This master has level 7 priority when accessing the slave port. + * 0b111..This master has level 8 or the lowest priority when accessing the slave port. + */ +#define AXBS_PRS0_M0(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS0_M0_SHIFT)) & AXBS_PRS0_M0_MASK) + +#define AXBS_PRS0_M1_MASK (0x70U) +#define AXBS_PRS0_M1_SHIFT (4U) +/*! M1 - Master 1 Priority + * 0b000..This master has level 1 or highest priority when accessing the slave port. + * 0b001..This master has level 2 priority when accessing the slave port. + * 0b010..This master has level 3 priority when accessing the slave port. + * 0b011..This master has level 4 priority when accessing the slave port. + * 0b100..This master has level 5 priority when accessing the slave port. + * 0b101..This master has level 6 priority when accessing the slave port. + * 0b110..This master has level 7 priority when accessing the slave port. + * 0b111..This master has level 8 or lowest priority when accessing the slave port. + */ +#define AXBS_PRS0_M1(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS0_M1_SHIFT)) & AXBS_PRS0_M1_MASK) + +#define AXBS_PRS0_M2_MASK (0x700U) +#define AXBS_PRS0_M2_SHIFT (8U) +/*! M2 - Master 2 Priority + * 0b000..This master has level 1 or highest priority when accessing the slave port. + * 0b001..This master has level 2 priority when accessing the slave port. + * 0b010..This master has level 3 priority when accessing the slave port. + * 0b011..This master has level 4 priority when accessing the slave port. + * 0b100..This master has level 5 priority when accessing the slave port. + * 0b101..This master has level 6 priority when accessing the slave port. + * 0b110..This master has level 7 priority when accessing the slave port. + * 0b111..This master has level 8the or lowest priority when accessing the slave port. + */ +#define AXBS_PRS0_M2(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS0_M2_SHIFT)) & AXBS_PRS0_M2_MASK) + +#define AXBS_PRS0_M3_MASK (0x7000U) +#define AXBS_PRS0_M3_SHIFT (12U) +/*! M3 - Master 3 Priority + * 0b000..This master has level 1 or highest priority when accessing the slave port. + * 0b001..This master has level 2 priority when accessing the slave port. + * 0b010..This master has level 3 priority when accessing the slave port. + * 0b011..This master has level 4 priority when accessing the slave port. + * 0b100..This master has level 5 priority when accessing the slave port. + * 0b101..This master has level 6 priority when accessing the slave port. + * 0b110..This master has level 7 priority when accessing the slave port. + * 0b111..This master has level 8the or lowest priority when accessing the slave port. + */ +#define AXBS_PRS0_M3(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS0_M3_SHIFT)) & AXBS_PRS0_M3_MASK) + +#define AXBS_PRS0_M4_MASK (0x70000U) +#define AXBS_PRS0_M4_SHIFT (16U) +/*! M4 - Master 4 Priority + * 0b000..This master has level 1 or highest priority when accessing the slave port. + * 0b001..This master has level 2 priority when accessing the slave port. + * 0b010..This master has level 3 priority when accessing the slave port. + * 0b011..This master has level 4 priority when accessing the slave port. + * 0b100..This master has level 5 priority when accessing the slave port. + * 0b101..This master has level 6 priority when accessing the slave port. + * 0b110..This master has level 7 priority when accessing the slave port. + * 0b111..This master has level 8 or lowest priority when accessing the slave port. + */ +#define AXBS_PRS0_M4(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS0_M4_SHIFT)) & AXBS_PRS0_M4_MASK) + +#define AXBS_PRS0_M5_MASK (0x700000U) +#define AXBS_PRS0_M5_SHIFT (20U) +/*! M5 - Master 5 Priority + * 0b000..This master has level 1 or highest priority when accessing the slave port. + * 0b001..This master has level 2 priority when accessing the slave port. + * 0b010..This master has level 3 priority when accessing the slave port. + * 0b011..This master has level 4 priority when accessing the slave port. + * 0b100..This master has level 5 priority when accessing the slave port. + * 0b101..This master has level 6 priority when accessing the slave port. + * 0b110..This master has level 7 priority when accessing the slave port. + * 0b111..This master has level 8 or lowest priority when accessing the slave port. + */ +#define AXBS_PRS0_M5(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS0_M5_SHIFT)) & AXBS_PRS0_M5_MASK) + +#define AXBS_PRS0_M6_MASK (0x7000000U) +#define AXBS_PRS0_M6_SHIFT (24U) +/*! M6 - Master 6 Priority + * 0b000..This master has level 1 or highest priority when accessing the slave port. + * 0b001..This master has level 2 priority when accessing the slave port. + * 0b010..This master has level 3 priority when accessing the slave port. + * 0b011..This master has level 4 priority when accessing the slave port. + * 0b100..This master has level 5 priority when accessing the slave port. + * 0b101..This master has level 6 priority when accessing the slave port. + * 0b110..This master has level 7 priority when accessing the slave port. + * 0b111..This master has level 8the or lowest priority when accessing the slave port. + */ +#define AXBS_PRS0_M6(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS0_M6_SHIFT)) & AXBS_PRS0_M6_MASK) + +#define AXBS_PRS0_M7_MASK (0x70000000U) +#define AXBS_PRS0_M7_SHIFT (28U) +/*! M7 - Master 7 Priority + * 0b000..This master has level 1 or highest priority when accessing the slave port. + * 0b001..This master has level 2 priority when accessing the slave port. + * 0b010..This master has level 3 priority when accessing the slave port. + * 0b011..This master has level 4 priority when accessing the slave port. + * 0b100..This master has level 5 priority when accessing the slave port. + * 0b101..This master has level 6 priority when accessing the slave port. + * 0b110..This master has level 7 priority when accessing the slave port. + * 0b111..This master has level 8 or lowest priority when accessing the slave port. + */ +#define AXBS_PRS0_M7(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS0_M7_SHIFT)) & AXBS_PRS0_M7_MASK) +/*! @} */ + +/*! @name CRS0 - Control Register */ +/*! @{ */ + +#define AXBS_CRS0_PARK_MASK (0x7U) +#define AXBS_CRS0_PARK_SHIFT (0U) +/*! PARK - Park + * 0b000..Park on master port M0 + * 0b001..Park on master port M1 + * 0b010..Park on master port M2 + * 0b011..Park on master port M3 + * 0b100..Park on master port M4 + * 0b101..Park on master port M5 + * 0b110..Park on master port M6 + * 0b111..Park on master port M7 + */ +#define AXBS_CRS0_PARK(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS0_PARK_SHIFT)) & AXBS_CRS0_PARK_MASK) + +#define AXBS_CRS0_PCTL_MASK (0x30U) +#define AXBS_CRS0_PCTL_SHIFT (4U) +/*! PCTL - Parking Control + * 0b00..When no master makes a request, the arbiter parks the slave port on the master port defined by the PARK bit field. + * 0b01..When no master makes a request, the arbiter parks the slave port on the last master to be in control of the slave port. + * 0b10..Low-power park. When no master makes a request, the slave port is not parked on a master and the arbiter + * drives all outputs to a constant safe state. + * 0b11..Reserved + */ +#define AXBS_CRS0_PCTL(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS0_PCTL_SHIFT)) & AXBS_CRS0_PCTL_MASK) + +#define AXBS_CRS0_ARB_MASK (0x300U) +#define AXBS_CRS0_ARB_SHIFT (8U) +/*! ARB - Arbitration Mode + * 0b00..Fixed priority + * 0b01..Round-robin (rotating) priority + * 0b10..Reserved + * 0b11..Reserved + */ +#define AXBS_CRS0_ARB(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS0_ARB_SHIFT)) & AXBS_CRS0_ARB_MASK) + +#define AXBS_CRS0_HPE0_MASK (0x10000U) +#define AXBS_CRS0_HPE0_SHIFT (16U) +/*! HPE0 - High Priority Elevation 0 + * 0b0..Master high-priority elevation for master 0. is disabled on this slave port. + * 0b1..Master high-priority elevation for master 0. is enabled on this slave port. + */ +#define AXBS_CRS0_HPE0(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS0_HPE0_SHIFT)) & AXBS_CRS0_HPE0_MASK) + +#define AXBS_CRS0_HPE1_MASK (0x20000U) +#define AXBS_CRS0_HPE1_SHIFT (17U) +/*! HPE1 - High Priority Elevation 1 + * 0b0..Master high-priority elevation for master 1. is disabled on this slave port. + * 0b1..Master high-priority elevation for master 1. is enabled on this slave port. + */ +#define AXBS_CRS0_HPE1(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS0_HPE1_SHIFT)) & AXBS_CRS0_HPE1_MASK) + +#define AXBS_CRS0_HPE2_MASK (0x40000U) +#define AXBS_CRS0_HPE2_SHIFT (18U) +/*! HPE2 - High Priority Elevation 2 + * 0b0..Master high-priority elevation for master 2. is disabled on this slave port. + * 0b1..Master high-priority elevation for master 2. is enabled on this slave port. + */ +#define AXBS_CRS0_HPE2(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS0_HPE2_SHIFT)) & AXBS_CRS0_HPE2_MASK) + +#define AXBS_CRS0_HPE3_MASK (0x80000U) +#define AXBS_CRS0_HPE3_SHIFT (19U) +/*! HPE3 - High Priority Elevation 3 + * 0b0..Master high-priority elevation for master 3. is disabled on this slave port. + * 0b1..Master high-priority elevation for master 3. is enabled on this slave port. + */ +#define AXBS_CRS0_HPE3(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS0_HPE3_SHIFT)) & AXBS_CRS0_HPE3_MASK) + +#define AXBS_CRS0_HPE4_MASK (0x100000U) +#define AXBS_CRS0_HPE4_SHIFT (20U) +/*! HPE4 - High Priority Elevation 4 + * 0b0..Master high-priority elevation for master 4. is disabled on this slave port. + * 0b1..Master high-priority elevation for master 4. is enabled on this slave port. + */ +#define AXBS_CRS0_HPE4(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS0_HPE4_SHIFT)) & AXBS_CRS0_HPE4_MASK) + +#define AXBS_CRS0_HPE5_MASK (0x200000U) +#define AXBS_CRS0_HPE5_SHIFT (21U) +/*! HPE5 - High Priority Elevation 5 + * 0b0..Master high-priority elevation for master 5. is disabled on this slave port. + * 0b1..Master high-priority elevation for master 5. is enabled on this slave port. + */ +#define AXBS_CRS0_HPE5(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS0_HPE5_SHIFT)) & AXBS_CRS0_HPE5_MASK) + +#define AXBS_CRS0_HPE6_MASK (0x400000U) +#define AXBS_CRS0_HPE6_SHIFT (22U) +/*! HPE6 - High Priority Elevation 6 + * 0b0..Master high-priority elevation for master 6. is disabled on this slave port. + * 0b1..Master high-priority elevation for master 6. is enabled on this slave port. + */ +#define AXBS_CRS0_HPE6(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS0_HPE6_SHIFT)) & AXBS_CRS0_HPE6_MASK) + +#define AXBS_CRS0_HPE7_MASK (0x800000U) +#define AXBS_CRS0_HPE7_SHIFT (23U) +/*! HPE7 - High Priority Elevation 7 + * 0b0..Master high-priority elevation for master 7. is disabled on this slave port. + * 0b1..Master high-priority elevation for master 7. is enabled on this slave port. + */ +#define AXBS_CRS0_HPE7(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS0_HPE7_SHIFT)) & AXBS_CRS0_HPE7_MASK) + +#define AXBS_CRS0_RO_MASK (0x80000000U) +#define AXBS_CRS0_RO_SHIFT (31U) +/*! RO - Read Only + * 0b0..The CRSn and PRSn registers are writeable + * 0b1..The CRSn and PRSn registers are read-only and cannot be written (attempted writes have no effect on the + * registers and result in a bus error response). + */ +#define AXBS_CRS0_RO(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS0_RO_SHIFT)) & AXBS_CRS0_RO_MASK) +/*! @} */ + +/*! @name PRS1 - Priority Slave Registers */ +/*! @{ */ + +#define AXBS_PRS1_M0_MASK (0x7U) +#define AXBS_PRS1_M0_SHIFT (0U) +/*! M0 - Master 0 Priority + * 0b000..This master has level 1 or highest priority when accessing the slave port. + * 0b001..This master has level 2 priority when accessing the slave port. + * 0b010..This master has level 3 priority when accessing the slave port. + * 0b011..This master has level 4 priority when accessing the slave port. + * 0b100..This master has level 5 priority when accessing the slave port. + * 0b101..This master has level 6 priority when accessing the slave port. + * 0b110..This master has level 7 priority when accessing the slave port. + * 0b111..This master has level 8 or the lowest priority when accessing the slave port. + */ +#define AXBS_PRS1_M0(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS1_M0_SHIFT)) & AXBS_PRS1_M0_MASK) + +#define AXBS_PRS1_M1_MASK (0x70U) +#define AXBS_PRS1_M1_SHIFT (4U) +/*! M1 - Master 1 Priority + * 0b000..This master has level 1 or highest priority when accessing the slave port. + * 0b001..This master has level 2 priority when accessing the slave port. + * 0b010..This master has level 3 priority when accessing the slave port. + * 0b011..This master has level 4 priority when accessing the slave port. + * 0b100..This master has level 5 priority when accessing the slave port. + * 0b101..This master has level 6 priority when accessing the slave port. + * 0b110..This master has level 7 priority when accessing the slave port. + * 0b111..This master has level 8 or lowest priority when accessing the slave port. + */ +#define AXBS_PRS1_M1(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS1_M1_SHIFT)) & AXBS_PRS1_M1_MASK) + +#define AXBS_PRS1_M2_MASK (0x700U) +#define AXBS_PRS1_M2_SHIFT (8U) +/*! M2 - Master 2 Priority + * 0b000..This master has level 1 or highest priority when accessing the slave port. + * 0b001..This master has level 2 priority when accessing the slave port. + * 0b010..This master has level 3 priority when accessing the slave port. + * 0b011..This master has level 4 priority when accessing the slave port. + * 0b100..This master has level 5 priority when accessing the slave port. + * 0b101..This master has level 6 priority when accessing the slave port. + * 0b110..This master has level 7 priority when accessing the slave port. + * 0b111..This master has level 8the or lowest priority when accessing the slave port. + */ +#define AXBS_PRS1_M2(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS1_M2_SHIFT)) & AXBS_PRS1_M2_MASK) + +#define AXBS_PRS1_M3_MASK (0x7000U) +#define AXBS_PRS1_M3_SHIFT (12U) +/*! M3 - Master 3 Priority + * 0b000..This master has level 1 or highest priority when accessing the slave port. + * 0b001..This master has level 2 priority when accessing the slave port. + * 0b010..This master has level 3 priority when accessing the slave port. + * 0b011..This master has level 4 priority when accessing the slave port. + * 0b100..This master has level 5 priority when accessing the slave port. + * 0b101..This master has level 6 priority when accessing the slave port. + * 0b110..This master has level 7 priority when accessing the slave port. + * 0b111..This master has level 8the or lowest priority when accessing the slave port. + */ +#define AXBS_PRS1_M3(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS1_M3_SHIFT)) & AXBS_PRS1_M3_MASK) + +#define AXBS_PRS1_M4_MASK (0x70000U) +#define AXBS_PRS1_M4_SHIFT (16U) +/*! M4 - Master 4 Priority + * 0b000..This master has level 1 or highest priority when accessing the slave port. + * 0b001..This master has level 2 priority when accessing the slave port. + * 0b010..This master has level 3 priority when accessing the slave port. + * 0b011..This master has level 4 priority when accessing the slave port. + * 0b100..This master has level 5 priority when accessing the slave port. + * 0b101..This master has level 6 priority when accessing the slave port. + * 0b110..This master has level 7 priority when accessing the slave port. + * 0b111..This master has level 8 or lowest priority when accessing the slave port. + */ +#define AXBS_PRS1_M4(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS1_M4_SHIFT)) & AXBS_PRS1_M4_MASK) + +#define AXBS_PRS1_M5_MASK (0x700000U) +#define AXBS_PRS1_M5_SHIFT (20U) +/*! M5 - Master 5 Priority + * 0b000..This master has level 1 or highest priority when accessing the slave port. + * 0b001..This master has level 2 priority when accessing the slave port. + * 0b010..This master has level 3 priority when accessing the slave port. + * 0b011..This master has level 4 priority when accessing the slave port. + * 0b100..This master has level 5 priority when accessing the slave port. + * 0b101..This master has level 6 priority when accessing the slave port. + * 0b110..This master has level 7 priority when accessing the slave port. + * 0b111..This master has level 8 or lowest priority when accessing the slave port. + */ +#define AXBS_PRS1_M5(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS1_M5_SHIFT)) & AXBS_PRS1_M5_MASK) + +#define AXBS_PRS1_M6_MASK (0x7000000U) +#define AXBS_PRS1_M6_SHIFT (24U) +/*! M6 - Master 6 Priority + * 0b000..This master has level 1 or highest priority when accessing the slave port. + * 0b001..This master has level 2 priority when accessing the slave port. + * 0b010..This master has level 3 priority when accessing the slave port. + * 0b011..This master has level 4 priority when accessing the slave port. + * 0b100..This master has level 5 priority when accessing the slave port. + * 0b101..This master has level 6 priority when accessing the slave port. + * 0b110..This master has level 7 priority when accessing the slave port. + * 0b111..This master has level 8the or lowest priority when accessing the slave port. + */ +#define AXBS_PRS1_M6(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS1_M6_SHIFT)) & AXBS_PRS1_M6_MASK) + +#define AXBS_PRS1_M7_MASK (0x70000000U) +#define AXBS_PRS1_M7_SHIFT (28U) +/*! M7 - Master 7 Priority + * 0b000..This master has level 1 or highest priority when accessing the slave port. + * 0b001..This master has level 2 priority when accessing the slave port. + * 0b010..This master has level 3 priority when accessing the slave port. + * 0b011..This master has level 4 priority when accessing the slave port. + * 0b100..This master has level 5 priority when accessing the slave port. + * 0b101..This master has level 6 priority when accessing the slave port. + * 0b110..This master has level 7 priority when accessing the slave port. + * 0b111..This master has level 8 or lowest priority when accessing the slave port. + */ +#define AXBS_PRS1_M7(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS1_M7_SHIFT)) & AXBS_PRS1_M7_MASK) +/*! @} */ + +/*! @name CRS1 - Control Register */ +/*! @{ */ + +#define AXBS_CRS1_PARK_MASK (0x7U) +#define AXBS_CRS1_PARK_SHIFT (0U) +/*! PARK - Park + * 0b000..Park on master port M0 + * 0b001..Park on master port M1 + * 0b010..Park on master port M2 + * 0b011..Park on master port M3 + * 0b100..Park on master port M4 + * 0b101..Park on master port M5 + * 0b110..Park on master port M6 + * 0b111..Park on master port M7 + */ +#define AXBS_CRS1_PARK(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS1_PARK_SHIFT)) & AXBS_CRS1_PARK_MASK) + +#define AXBS_CRS1_PCTL_MASK (0x30U) +#define AXBS_CRS1_PCTL_SHIFT (4U) +/*! PCTL - Parking Control + * 0b00..When no master makes a request, the arbiter parks the slave port on the master port defined by the PARK bit field. + * 0b01..When no master makes a request, the arbiter parks the slave port on the last master to be in control of the slave port. + * 0b10..Low-power park. When no master makes a request, the slave port is not parked on a master and the arbiter + * drives all outputs to a constant safe state. + * 0b11..Reserved + */ +#define AXBS_CRS1_PCTL(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS1_PCTL_SHIFT)) & AXBS_CRS1_PCTL_MASK) + +#define AXBS_CRS1_ARB_MASK (0x300U) +#define AXBS_CRS1_ARB_SHIFT (8U) +/*! ARB - Arbitration Mode + * 0b00..Fixed priority + * 0b01..Round-robin (rotating) priority + * 0b10..Reserved + * 0b11..Reserved + */ +#define AXBS_CRS1_ARB(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS1_ARB_SHIFT)) & AXBS_CRS1_ARB_MASK) + +#define AXBS_CRS1_HPE0_MASK (0x10000U) +#define AXBS_CRS1_HPE0_SHIFT (16U) +/*! HPE0 - High Priority Elevation 0 + * 0b0..Master high-priority elevation for master 0. is disabled on this slave port. + * 0b1..Master high-priority elevation for master 0. is enabled on this slave port. + */ +#define AXBS_CRS1_HPE0(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS1_HPE0_SHIFT)) & AXBS_CRS1_HPE0_MASK) + +#define AXBS_CRS1_HPE1_MASK (0x20000U) +#define AXBS_CRS1_HPE1_SHIFT (17U) +/*! HPE1 - High Priority Elevation 1 + * 0b0..Master high-priority elevation for master 1. is disabled on this slave port. + * 0b1..Master high-priority elevation for master 1. is enabled on this slave port. + */ +#define AXBS_CRS1_HPE1(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS1_HPE1_SHIFT)) & AXBS_CRS1_HPE1_MASK) + +#define AXBS_CRS1_HPE2_MASK (0x40000U) +#define AXBS_CRS1_HPE2_SHIFT (18U) +/*! HPE2 - High Priority Elevation 2 + * 0b0..Master high-priority elevation for master 2. is disabled on this slave port. + * 0b1..Master high-priority elevation for master 2. is enabled on this slave port. + */ +#define AXBS_CRS1_HPE2(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS1_HPE2_SHIFT)) & AXBS_CRS1_HPE2_MASK) + +#define AXBS_CRS1_HPE3_MASK (0x80000U) +#define AXBS_CRS1_HPE3_SHIFT (19U) +/*! HPE3 - High Priority Elevation 3 + * 0b0..Master high-priority elevation for master 3. is disabled on this slave port. + * 0b1..Master high-priority elevation for master 3. is enabled on this slave port. + */ +#define AXBS_CRS1_HPE3(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS1_HPE3_SHIFT)) & AXBS_CRS1_HPE3_MASK) + +#define AXBS_CRS1_HPE4_MASK (0x100000U) +#define AXBS_CRS1_HPE4_SHIFT (20U) +/*! HPE4 - High Priority Elevation 4 + * 0b0..Master high-priority elevation for master 4. is disabled on this slave port. + * 0b1..Master high-priority elevation for master 4. is enabled on this slave port. + */ +#define AXBS_CRS1_HPE4(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS1_HPE4_SHIFT)) & AXBS_CRS1_HPE4_MASK) + +#define AXBS_CRS1_HPE5_MASK (0x200000U) +#define AXBS_CRS1_HPE5_SHIFT (21U) +/*! HPE5 - High Priority Elevation 5 + * 0b0..Master high-priority elevation for master 5. is disabled on this slave port. + * 0b1..Master high-priority elevation for master 5. is enabled on this slave port. + */ +#define AXBS_CRS1_HPE5(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS1_HPE5_SHIFT)) & AXBS_CRS1_HPE5_MASK) + +#define AXBS_CRS1_HPE6_MASK (0x400000U) +#define AXBS_CRS1_HPE6_SHIFT (22U) +/*! HPE6 - High Priority Elevation 6 + * 0b0..Master high-priority elevation for master 6. is disabled on this slave port. + * 0b1..Master high-priority elevation for master 6. is enabled on this slave port. + */ +#define AXBS_CRS1_HPE6(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS1_HPE6_SHIFT)) & AXBS_CRS1_HPE6_MASK) + +#define AXBS_CRS1_HPE7_MASK (0x800000U) +#define AXBS_CRS1_HPE7_SHIFT (23U) +/*! HPE7 - High Priority Elevation 7 + * 0b0..Master high-priority elevation for master 7. is disabled on this slave port. + * 0b1..Master high-priority elevation for master 7. is enabled on this slave port. + */ +#define AXBS_CRS1_HPE7(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS1_HPE7_SHIFT)) & AXBS_CRS1_HPE7_MASK) + +#define AXBS_CRS1_RO_MASK (0x80000000U) +#define AXBS_CRS1_RO_SHIFT (31U) +/*! RO - Read Only + * 0b0..The CRSn and PRSn registers are writeable + * 0b1..The CRSn and PRSn registers are read-only and cannot be written (attempted writes have no effect on the + * registers and result in a bus error response). + */ +#define AXBS_CRS1_RO(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS1_RO_SHIFT)) & AXBS_CRS1_RO_MASK) +/*! @} */ + +/*! @name PRS2 - Priority Slave Registers */ +/*! @{ */ + +#define AXBS_PRS2_M0_MASK (0x7U) +#define AXBS_PRS2_M0_SHIFT (0U) +/*! M0 - Master 0 Priority + * 0b000..This master has level 1 or highest priority when accessing the slave port. + * 0b001..This master has level 2 priority when accessing the slave port. + * 0b010..This master has level 3 priority when accessing the slave port. + * 0b011..This master has level 4 priority when accessing the slave port. + * 0b100..This master has level 5 priority when accessing the slave port. + * 0b101..This master has level 6 priority when accessing the slave port. + * 0b110..This master has level 7 priority when accessing the slave port. + * 0b111..This master has level 8 or the lowest priority when accessing the slave port. + */ +#define AXBS_PRS2_M0(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS2_M0_SHIFT)) & AXBS_PRS2_M0_MASK) + +#define AXBS_PRS2_M1_MASK (0x70U) +#define AXBS_PRS2_M1_SHIFT (4U) +/*! M1 - Master 1 Priority + * 0b000..This master has level 1 or highest priority when accessing the slave port. + * 0b001..This master has level 2 priority when accessing the slave port. + * 0b010..This master has level 3 priority when accessing the slave port. + * 0b011..This master has level 4 priority when accessing the slave port. + * 0b100..This master has level 5 priority when accessing the slave port. + * 0b101..This master has level 6 priority when accessing the slave port. + * 0b110..This master has level 7 priority when accessing the slave port. + * 0b111..This master has level 8 or lowest priority when accessing the slave port. + */ +#define AXBS_PRS2_M1(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS2_M1_SHIFT)) & AXBS_PRS2_M1_MASK) + +#define AXBS_PRS2_M2_MASK (0x700U) +#define AXBS_PRS2_M2_SHIFT (8U) +/*! M2 - Master 2 Priority + * 0b000..This master has level 1 or highest priority when accessing the slave port. + * 0b001..This master has level 2 priority when accessing the slave port. + * 0b010..This master has level 3 priority when accessing the slave port. + * 0b011..This master has level 4 priority when accessing the slave port. + * 0b100..This master has level 5 priority when accessing the slave port. + * 0b101..This master has level 6 priority when accessing the slave port. + * 0b110..This master has level 7 priority when accessing the slave port. + * 0b111..This master has level 8the or lowest priority when accessing the slave port. + */ +#define AXBS_PRS2_M2(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS2_M2_SHIFT)) & AXBS_PRS2_M2_MASK) + +#define AXBS_PRS2_M3_MASK (0x7000U) +#define AXBS_PRS2_M3_SHIFT (12U) +/*! M3 - Master 3 Priority + * 0b000..This master has level 1 or highest priority when accessing the slave port. + * 0b001..This master has level 2 priority when accessing the slave port. + * 0b010..This master has level 3 priority when accessing the slave port. + * 0b011..This master has level 4 priority when accessing the slave port. + * 0b100..This master has level 5 priority when accessing the slave port. + * 0b101..This master has level 6 priority when accessing the slave port. + * 0b110..This master has level 7 priority when accessing the slave port. + * 0b111..This master has level 8the or lowest priority when accessing the slave port. + */ +#define AXBS_PRS2_M3(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS2_M3_SHIFT)) & AXBS_PRS2_M3_MASK) + +#define AXBS_PRS2_M4_MASK (0x70000U) +#define AXBS_PRS2_M4_SHIFT (16U) +/*! M4 - Master 4 Priority + * 0b000..This master has level 1 or highest priority when accessing the slave port. + * 0b001..This master has level 2 priority when accessing the slave port. + * 0b010..This master has level 3 priority when accessing the slave port. + * 0b011..This master has level 4 priority when accessing the slave port. + * 0b100..This master has level 5 priority when accessing the slave port. + * 0b101..This master has level 6 priority when accessing the slave port. + * 0b110..This master has level 7 priority when accessing the slave port. + * 0b111..This master has level 8 or lowest priority when accessing the slave port. + */ +#define AXBS_PRS2_M4(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS2_M4_SHIFT)) & AXBS_PRS2_M4_MASK) + +#define AXBS_PRS2_M5_MASK (0x700000U) +#define AXBS_PRS2_M5_SHIFT (20U) +/*! M5 - Master 5 Priority + * 0b000..This master has level 1 or highest priority when accessing the slave port. + * 0b001..This master has level 2 priority when accessing the slave port. + * 0b010..This master has level 3 priority when accessing the slave port. + * 0b011..This master has level 4 priority when accessing the slave port. + * 0b100..This master has level 5 priority when accessing the slave port. + * 0b101..This master has level 6 priority when accessing the slave port. + * 0b110..This master has level 7 priority when accessing the slave port. + * 0b111..This master has level 8 or lowest priority when accessing the slave port. + */ +#define AXBS_PRS2_M5(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS2_M5_SHIFT)) & AXBS_PRS2_M5_MASK) + +#define AXBS_PRS2_M6_MASK (0x7000000U) +#define AXBS_PRS2_M6_SHIFT (24U) +/*! M6 - Master 6 Priority + * 0b000..This master has level 1 or highest priority when accessing the slave port. + * 0b001..This master has level 2 priority when accessing the slave port. + * 0b010..This master has level 3 priority when accessing the slave port. + * 0b011..This master has level 4 priority when accessing the slave port. + * 0b100..This master has level 5 priority when accessing the slave port. + * 0b101..This master has level 6 priority when accessing the slave port. + * 0b110..This master has level 7 priority when accessing the slave port. + * 0b111..This master has level 8the or lowest priority when accessing the slave port. + */ +#define AXBS_PRS2_M6(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS2_M6_SHIFT)) & AXBS_PRS2_M6_MASK) + +#define AXBS_PRS2_M7_MASK (0x70000000U) +#define AXBS_PRS2_M7_SHIFT (28U) +/*! M7 - Master 7 Priority + * 0b000..This master has level 1 or highest priority when accessing the slave port. + * 0b001..This master has level 2 priority when accessing the slave port. + * 0b010..This master has level 3 priority when accessing the slave port. + * 0b011..This master has level 4 priority when accessing the slave port. + * 0b100..This master has level 5 priority when accessing the slave port. + * 0b101..This master has level 6 priority when accessing the slave port. + * 0b110..This master has level 7 priority when accessing the slave port. + * 0b111..This master has level 8 or lowest priority when accessing the slave port. + */ +#define AXBS_PRS2_M7(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS2_M7_SHIFT)) & AXBS_PRS2_M7_MASK) +/*! @} */ + +/*! @name CRS2 - Control Register */ +/*! @{ */ + +#define AXBS_CRS2_PARK_MASK (0x7U) +#define AXBS_CRS2_PARK_SHIFT (0U) +/*! PARK - Park + * 0b000..Park on master port M0 + * 0b001..Park on master port M1 + * 0b010..Park on master port M2 + * 0b011..Park on master port M3 + * 0b100..Park on master port M4 + * 0b101..Park on master port M5 + * 0b110..Park on master port M6 + * 0b111..Park on master port M7 + */ +#define AXBS_CRS2_PARK(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS2_PARK_SHIFT)) & AXBS_CRS2_PARK_MASK) + +#define AXBS_CRS2_PCTL_MASK (0x30U) +#define AXBS_CRS2_PCTL_SHIFT (4U) +/*! PCTL - Parking Control + * 0b00..When no master makes a request, the arbiter parks the slave port on the master port defined by the PARK bit field. + * 0b01..When no master makes a request, the arbiter parks the slave port on the last master to be in control of the slave port. + * 0b10..Low-power park. When no master makes a request, the slave port is not parked on a master and the arbiter + * drives all outputs to a constant safe state. + * 0b11..Reserved + */ +#define AXBS_CRS2_PCTL(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS2_PCTL_SHIFT)) & AXBS_CRS2_PCTL_MASK) + +#define AXBS_CRS2_ARB_MASK (0x300U) +#define AXBS_CRS2_ARB_SHIFT (8U) +/*! ARB - Arbitration Mode + * 0b00..Fixed priority + * 0b01..Round-robin (rotating) priority + * 0b10..Reserved + * 0b11..Reserved + */ +#define AXBS_CRS2_ARB(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS2_ARB_SHIFT)) & AXBS_CRS2_ARB_MASK) + +#define AXBS_CRS2_HPE0_MASK (0x10000U) +#define AXBS_CRS2_HPE0_SHIFT (16U) +/*! HPE0 - High Priority Elevation 0 + * 0b0..Master high-priority elevation for master 0. is disabled on this slave port. + * 0b1..Master high-priority elevation for master 0. is enabled on this slave port. + */ +#define AXBS_CRS2_HPE0(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS2_HPE0_SHIFT)) & AXBS_CRS2_HPE0_MASK) + +#define AXBS_CRS2_HPE1_MASK (0x20000U) +#define AXBS_CRS2_HPE1_SHIFT (17U) +/*! HPE1 - High Priority Elevation 1 + * 0b0..Master high-priority elevation for master 1. is disabled on this slave port. + * 0b1..Master high-priority elevation for master 1. is enabled on this slave port. + */ +#define AXBS_CRS2_HPE1(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS2_HPE1_SHIFT)) & AXBS_CRS2_HPE1_MASK) + +#define AXBS_CRS2_HPE2_MASK (0x40000U) +#define AXBS_CRS2_HPE2_SHIFT (18U) +/*! HPE2 - High Priority Elevation 2 + * 0b0..Master high-priority elevation for master 2. is disabled on this slave port. + * 0b1..Master high-priority elevation for master 2. is enabled on this slave port. + */ +#define AXBS_CRS2_HPE2(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS2_HPE2_SHIFT)) & AXBS_CRS2_HPE2_MASK) + +#define AXBS_CRS2_HPE3_MASK (0x80000U) +#define AXBS_CRS2_HPE3_SHIFT (19U) +/*! HPE3 - High Priority Elevation 3 + * 0b0..Master high-priority elevation for master 3. is disabled on this slave port. + * 0b1..Master high-priority elevation for master 3. is enabled on this slave port. + */ +#define AXBS_CRS2_HPE3(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS2_HPE3_SHIFT)) & AXBS_CRS2_HPE3_MASK) + +#define AXBS_CRS2_HPE4_MASK (0x100000U) +#define AXBS_CRS2_HPE4_SHIFT (20U) +/*! HPE4 - High Priority Elevation 4 + * 0b0..Master high-priority elevation for master 4. is disabled on this slave port. + * 0b1..Master high-priority elevation for master 4. is enabled on this slave port. + */ +#define AXBS_CRS2_HPE4(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS2_HPE4_SHIFT)) & AXBS_CRS2_HPE4_MASK) + +#define AXBS_CRS2_HPE5_MASK (0x200000U) +#define AXBS_CRS2_HPE5_SHIFT (21U) +/*! HPE5 - High Priority Elevation 5 + * 0b0..Master high-priority elevation for master 5. is disabled on this slave port. + * 0b1..Master high-priority elevation for master 5. is enabled on this slave port. + */ +#define AXBS_CRS2_HPE5(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS2_HPE5_SHIFT)) & AXBS_CRS2_HPE5_MASK) + +#define AXBS_CRS2_HPE6_MASK (0x400000U) +#define AXBS_CRS2_HPE6_SHIFT (22U) +/*! HPE6 - High Priority Elevation 6 + * 0b0..Master high-priority elevation for master 6. is disabled on this slave port. + * 0b1..Master high-priority elevation for master 6. is enabled on this slave port. + */ +#define AXBS_CRS2_HPE6(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS2_HPE6_SHIFT)) & AXBS_CRS2_HPE6_MASK) + +#define AXBS_CRS2_HPE7_MASK (0x800000U) +#define AXBS_CRS2_HPE7_SHIFT (23U) +/*! HPE7 - High Priority Elevation 7 + * 0b0..Master high-priority elevation for master 7. is disabled on this slave port. + * 0b1..Master high-priority elevation for master 7. is enabled on this slave port. + */ +#define AXBS_CRS2_HPE7(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS2_HPE7_SHIFT)) & AXBS_CRS2_HPE7_MASK) + +#define AXBS_CRS2_RO_MASK (0x80000000U) +#define AXBS_CRS2_RO_SHIFT (31U) +/*! RO - Read Only + * 0b0..The CRSn and PRSn registers are writeable + * 0b1..The CRSn and PRSn registers are read-only and cannot be written (attempted writes have no effect on the + * registers and result in a bus error response). + */ +#define AXBS_CRS2_RO(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS2_RO_SHIFT)) & AXBS_CRS2_RO_MASK) +/*! @} */ + +/*! @name PRS3 - Priority Slave Registers */ +/*! @{ */ + +#define AXBS_PRS3_M0_MASK (0x7U) +#define AXBS_PRS3_M0_SHIFT (0U) +/*! M0 - Master 0 Priority + * 0b000..This master has level 1 or highest priority when accessing the slave port. + * 0b001..This master has level 2 priority when accessing the slave port. + * 0b010..This master has level 3 priority when accessing the slave port. + * 0b011..This master has level 4 priority when accessing the slave port. + * 0b100..This master has level 5 priority when accessing the slave port. + * 0b101..This master has level 6 priority when accessing the slave port. + * 0b110..This master has level 7 priority when accessing the slave port. + * 0b111..This master has level 8 or the lowest priority when accessing the slave port. + */ +#define AXBS_PRS3_M0(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS3_M0_SHIFT)) & AXBS_PRS3_M0_MASK) + +#define AXBS_PRS3_M1_MASK (0x70U) +#define AXBS_PRS3_M1_SHIFT (4U) +/*! M1 - Master 1 Priority + * 0b000..This master has level 1 or highest priority when accessing the slave port. + * 0b001..This master has level 2 priority when accessing the slave port. + * 0b010..This master has level 3 priority when accessing the slave port. + * 0b011..This master has level 4 priority when accessing the slave port. + * 0b100..This master has level 5 priority when accessing the slave port. + * 0b101..This master has level 6 priority when accessing the slave port. + * 0b110..This master has level 7 priority when accessing the slave port. + * 0b111..This master has level 8 or lowest priority when accessing the slave port. + */ +#define AXBS_PRS3_M1(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS3_M1_SHIFT)) & AXBS_PRS3_M1_MASK) + +#define AXBS_PRS3_M2_MASK (0x700U) +#define AXBS_PRS3_M2_SHIFT (8U) +/*! M2 - Master 2 Priority + * 0b000..This master has level 1 or highest priority when accessing the slave port. + * 0b001..This master has level 2 priority when accessing the slave port. + * 0b010..This master has level 3 priority when accessing the slave port. + * 0b011..This master has level 4 priority when accessing the slave port. + * 0b100..This master has level 5 priority when accessing the slave port. + * 0b101..This master has level 6 priority when accessing the slave port. + * 0b110..This master has level 7 priority when accessing the slave port. + * 0b111..This master has level 8the or lowest priority when accessing the slave port. + */ +#define AXBS_PRS3_M2(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS3_M2_SHIFT)) & AXBS_PRS3_M2_MASK) + +#define AXBS_PRS3_M3_MASK (0x7000U) +#define AXBS_PRS3_M3_SHIFT (12U) +/*! M3 - Master 3 Priority + * 0b000..This master has level 1 or highest priority when accessing the slave port. + * 0b001..This master has level 2 priority when accessing the slave port. + * 0b010..This master has level 3 priority when accessing the slave port. + * 0b011..This master has level 4 priority when accessing the slave port. + * 0b100..This master has level 5 priority when accessing the slave port. + * 0b101..This master has level 6 priority when accessing the slave port. + * 0b110..This master has level 7 priority when accessing the slave port. + * 0b111..This master has level 8the or lowest priority when accessing the slave port. + */ +#define AXBS_PRS3_M3(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS3_M3_SHIFT)) & AXBS_PRS3_M3_MASK) + +#define AXBS_PRS3_M4_MASK (0x70000U) +#define AXBS_PRS3_M4_SHIFT (16U) +/*! M4 - Master 4 Priority + * 0b000..This master has level 1 or highest priority when accessing the slave port. + * 0b001..This master has level 2 priority when accessing the slave port. + * 0b010..This master has level 3 priority when accessing the slave port. + * 0b011..This master has level 4 priority when accessing the slave port. + * 0b100..This master has level 5 priority when accessing the slave port. + * 0b101..This master has level 6 priority when accessing the slave port. + * 0b110..This master has level 7 priority when accessing the slave port. + * 0b111..This master has level 8 or lowest priority when accessing the slave port. + */ +#define AXBS_PRS3_M4(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS3_M4_SHIFT)) & AXBS_PRS3_M4_MASK) + +#define AXBS_PRS3_M5_MASK (0x700000U) +#define AXBS_PRS3_M5_SHIFT (20U) +/*! M5 - Master 5 Priority + * 0b000..This master has level 1 or highest priority when accessing the slave port. + * 0b001..This master has level 2 priority when accessing the slave port. + * 0b010..This master has level 3 priority when accessing the slave port. + * 0b011..This master has level 4 priority when accessing the slave port. + * 0b100..This master has level 5 priority when accessing the slave port. + * 0b101..This master has level 6 priority when accessing the slave port. + * 0b110..This master has level 7 priority when accessing the slave port. + * 0b111..This master has level 8 or lowest priority when accessing the slave port. + */ +#define AXBS_PRS3_M5(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS3_M5_SHIFT)) & AXBS_PRS3_M5_MASK) + +#define AXBS_PRS3_M6_MASK (0x7000000U) +#define AXBS_PRS3_M6_SHIFT (24U) +/*! M6 - Master 6 Priority + * 0b000..This master has level 1 or highest priority when accessing the slave port. + * 0b001..This master has level 2 priority when accessing the slave port. + * 0b010..This master has level 3 priority when accessing the slave port. + * 0b011..This master has level 4 priority when accessing the slave port. + * 0b100..This master has level 5 priority when accessing the slave port. + * 0b101..This master has level 6 priority when accessing the slave port. + * 0b110..This master has level 7 priority when accessing the slave port. + * 0b111..This master has level 8the or lowest priority when accessing the slave port. + */ +#define AXBS_PRS3_M6(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS3_M6_SHIFT)) & AXBS_PRS3_M6_MASK) + +#define AXBS_PRS3_M7_MASK (0x70000000U) +#define AXBS_PRS3_M7_SHIFT (28U) +/*! M7 - Master 7 Priority + * 0b000..This master has level 1 or highest priority when accessing the slave port. + * 0b001..This master has level 2 priority when accessing the slave port. + * 0b010..This master has level 3 priority when accessing the slave port. + * 0b011..This master has level 4 priority when accessing the slave port. + * 0b100..This master has level 5 priority when accessing the slave port. + * 0b101..This master has level 6 priority when accessing the slave port. + * 0b110..This master has level 7 priority when accessing the slave port. + * 0b111..This master has level 8 or lowest priority when accessing the slave port. + */ +#define AXBS_PRS3_M7(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS3_M7_SHIFT)) & AXBS_PRS3_M7_MASK) +/*! @} */ + +/*! @name CRS3 - Control Register */ +/*! @{ */ + +#define AXBS_CRS3_PARK_MASK (0x7U) +#define AXBS_CRS3_PARK_SHIFT (0U) +/*! PARK - Park + * 0b000..Park on master port M0 + * 0b001..Park on master port M1 + * 0b010..Park on master port M2 + * 0b011..Park on master port M3 + * 0b100..Park on master port M4 + * 0b101..Park on master port M5 + * 0b110..Park on master port M6 + * 0b111..Park on master port M7 + */ +#define AXBS_CRS3_PARK(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS3_PARK_SHIFT)) & AXBS_CRS3_PARK_MASK) + +#define AXBS_CRS3_PCTL_MASK (0x30U) +#define AXBS_CRS3_PCTL_SHIFT (4U) +/*! PCTL - Parking Control + * 0b00..When no master makes a request, the arbiter parks the slave port on the master port defined by the PARK bit field. + * 0b01..When no master makes a request, the arbiter parks the slave port on the last master to be in control of the slave port. + * 0b10..Low-power park. When no master makes a request, the slave port is not parked on a master and the arbiter + * drives all outputs to a constant safe state. + * 0b11..Reserved + */ +#define AXBS_CRS3_PCTL(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS3_PCTL_SHIFT)) & AXBS_CRS3_PCTL_MASK) + +#define AXBS_CRS3_ARB_MASK (0x300U) +#define AXBS_CRS3_ARB_SHIFT (8U) +/*! ARB - Arbitration Mode + * 0b00..Fixed priority + * 0b01..Round-robin (rotating) priority + * 0b10..Reserved + * 0b11..Reserved + */ +#define AXBS_CRS3_ARB(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS3_ARB_SHIFT)) & AXBS_CRS3_ARB_MASK) + +#define AXBS_CRS3_HPE0_MASK (0x10000U) +#define AXBS_CRS3_HPE0_SHIFT (16U) +/*! HPE0 - High Priority Elevation 0 + * 0b0..Master high-priority elevation for master 0. is disabled on this slave port. + * 0b1..Master high-priority elevation for master 0. is enabled on this slave port. + */ +#define AXBS_CRS3_HPE0(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS3_HPE0_SHIFT)) & AXBS_CRS3_HPE0_MASK) + +#define AXBS_CRS3_HPE1_MASK (0x20000U) +#define AXBS_CRS3_HPE1_SHIFT (17U) +/*! HPE1 - High Priority Elevation 1 + * 0b0..Master high-priority elevation for master 1. is disabled on this slave port. + * 0b1..Master high-priority elevation for master 1. is enabled on this slave port. + */ +#define AXBS_CRS3_HPE1(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS3_HPE1_SHIFT)) & AXBS_CRS3_HPE1_MASK) + +#define AXBS_CRS3_HPE2_MASK (0x40000U) +#define AXBS_CRS3_HPE2_SHIFT (18U) +/*! HPE2 - High Priority Elevation 2 + * 0b0..Master high-priority elevation for master 2. is disabled on this slave port. + * 0b1..Master high-priority elevation for master 2. is enabled on this slave port. + */ +#define AXBS_CRS3_HPE2(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS3_HPE2_SHIFT)) & AXBS_CRS3_HPE2_MASK) + +#define AXBS_CRS3_HPE3_MASK (0x80000U) +#define AXBS_CRS3_HPE3_SHIFT (19U) +/*! HPE3 - High Priority Elevation 3 + * 0b0..Master high-priority elevation for master 3. is disabled on this slave port. + * 0b1..Master high-priority elevation for master 3. is enabled on this slave port. + */ +#define AXBS_CRS3_HPE3(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS3_HPE3_SHIFT)) & AXBS_CRS3_HPE3_MASK) + +#define AXBS_CRS3_HPE4_MASK (0x100000U) +#define AXBS_CRS3_HPE4_SHIFT (20U) +/*! HPE4 - High Priority Elevation 4 + * 0b0..Master high-priority elevation for master 4. is disabled on this slave port. + * 0b1..Master high-priority elevation for master 4. is enabled on this slave port. + */ +#define AXBS_CRS3_HPE4(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS3_HPE4_SHIFT)) & AXBS_CRS3_HPE4_MASK) + +#define AXBS_CRS3_HPE5_MASK (0x200000U) +#define AXBS_CRS3_HPE5_SHIFT (21U) +/*! HPE5 - High Priority Elevation 5 + * 0b0..Master high-priority elevation for master 5. is disabled on this slave port. + * 0b1..Master high-priority elevation for master 5. is enabled on this slave port. + */ +#define AXBS_CRS3_HPE5(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS3_HPE5_SHIFT)) & AXBS_CRS3_HPE5_MASK) + +#define AXBS_CRS3_HPE6_MASK (0x400000U) +#define AXBS_CRS3_HPE6_SHIFT (22U) +/*! HPE6 - High Priority Elevation 6 + * 0b0..Master high-priority elevation for master 6. is disabled on this slave port. + * 0b1..Master high-priority elevation for master 6. is enabled on this slave port. + */ +#define AXBS_CRS3_HPE6(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS3_HPE6_SHIFT)) & AXBS_CRS3_HPE6_MASK) + +#define AXBS_CRS3_HPE7_MASK (0x800000U) +#define AXBS_CRS3_HPE7_SHIFT (23U) +/*! HPE7 - High Priority Elevation 7 + * 0b0..Master high-priority elevation for master 7. is disabled on this slave port. + * 0b1..Master high-priority elevation for master 7. is enabled on this slave port. + */ +#define AXBS_CRS3_HPE7(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS3_HPE7_SHIFT)) & AXBS_CRS3_HPE7_MASK) + +#define AXBS_CRS3_RO_MASK (0x80000000U) +#define AXBS_CRS3_RO_SHIFT (31U) +/*! RO - Read Only + * 0b0..The CRSn and PRSn registers are writeable + * 0b1..The CRSn and PRSn registers are read-only and cannot be written (attempted writes have no effect on the + * registers and result in a bus error response). + */ +#define AXBS_CRS3_RO(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS3_RO_SHIFT)) & AXBS_CRS3_RO_MASK) +/*! @} */ + +/*! @name PRS4 - Priority Slave Registers */ +/*! @{ */ + +#define AXBS_PRS4_M0_MASK (0x7U) +#define AXBS_PRS4_M0_SHIFT (0U) +/*! M0 - Master 0 Priority + * 0b000..This master has level 1 or highest priority when accessing the slave port. + * 0b001..This master has level 2 priority when accessing the slave port. + * 0b010..This master has level 3 priority when accessing the slave port. + * 0b011..This master has level 4 priority when accessing the slave port. + * 0b100..This master has level 5 priority when accessing the slave port. + * 0b101..This master has level 6 priority when accessing the slave port. + * 0b110..This master has level 7 priority when accessing the slave port. + * 0b111..This master has level 8 or the lowest priority when accessing the slave port. + */ +#define AXBS_PRS4_M0(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS4_M0_SHIFT)) & AXBS_PRS4_M0_MASK) + +#define AXBS_PRS4_M1_MASK (0x70U) +#define AXBS_PRS4_M1_SHIFT (4U) +/*! M1 - Master 1 Priority + * 0b000..This master has level 1 or highest priority when accessing the slave port. + * 0b001..This master has level 2 priority when accessing the slave port. + * 0b010..This master has level 3 priority when accessing the slave port. + * 0b011..This master has level 4 priority when accessing the slave port. + * 0b100..This master has level 5 priority when accessing the slave port. + * 0b101..This master has level 6 priority when accessing the slave port. + * 0b110..This master has level 7 priority when accessing the slave port. + * 0b111..This master has level 8 or lowest priority when accessing the slave port. + */ +#define AXBS_PRS4_M1(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS4_M1_SHIFT)) & AXBS_PRS4_M1_MASK) + +#define AXBS_PRS4_M2_MASK (0x700U) +#define AXBS_PRS4_M2_SHIFT (8U) +/*! M2 - Master 2 Priority + * 0b000..This master has level 1 or highest priority when accessing the slave port. + * 0b001..This master has level 2 priority when accessing the slave port. + * 0b010..This master has level 3 priority when accessing the slave port. + * 0b011..This master has level 4 priority when accessing the slave port. + * 0b100..This master has level 5 priority when accessing the slave port. + * 0b101..This master has level 6 priority when accessing the slave port. + * 0b110..This master has level 7 priority when accessing the slave port. + * 0b111..This master has level 8the or lowest priority when accessing the slave port. + */ +#define AXBS_PRS4_M2(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS4_M2_SHIFT)) & AXBS_PRS4_M2_MASK) + +#define AXBS_PRS4_M3_MASK (0x7000U) +#define AXBS_PRS4_M3_SHIFT (12U) +/*! M3 - Master 3 Priority + * 0b000..This master has level 1 or highest priority when accessing the slave port. + * 0b001..This master has level 2 priority when accessing the slave port. + * 0b010..This master has level 3 priority when accessing the slave port. + * 0b011..This master has level 4 priority when accessing the slave port. + * 0b100..This master has level 5 priority when accessing the slave port. + * 0b101..This master has level 6 priority when accessing the slave port. + * 0b110..This master has level 7 priority when accessing the slave port. + * 0b111..This master has level 8the or lowest priority when accessing the slave port. + */ +#define AXBS_PRS4_M3(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS4_M3_SHIFT)) & AXBS_PRS4_M3_MASK) + +#define AXBS_PRS4_M4_MASK (0x70000U) +#define AXBS_PRS4_M4_SHIFT (16U) +/*! M4 - Master 4 Priority + * 0b000..This master has level 1 or highest priority when accessing the slave port. + * 0b001..This master has level 2 priority when accessing the slave port. + * 0b010..This master has level 3 priority when accessing the slave port. + * 0b011..This master has level 4 priority when accessing the slave port. + * 0b100..This master has level 5 priority when accessing the slave port. + * 0b101..This master has level 6 priority when accessing the slave port. + * 0b110..This master has level 7 priority when accessing the slave port. + * 0b111..This master has level 8 or lowest priority when accessing the slave port. + */ +#define AXBS_PRS4_M4(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS4_M4_SHIFT)) & AXBS_PRS4_M4_MASK) + +#define AXBS_PRS4_M5_MASK (0x700000U) +#define AXBS_PRS4_M5_SHIFT (20U) +/*! M5 - Master 5 Priority + * 0b000..This master has level 1 or highest priority when accessing the slave port. + * 0b001..This master has level 2 priority when accessing the slave port. + * 0b010..This master has level 3 priority when accessing the slave port. + * 0b011..This master has level 4 priority when accessing the slave port. + * 0b100..This master has level 5 priority when accessing the slave port. + * 0b101..This master has level 6 priority when accessing the slave port. + * 0b110..This master has level 7 priority when accessing the slave port. + * 0b111..This master has level 8 or lowest priority when accessing the slave port. + */ +#define AXBS_PRS4_M5(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS4_M5_SHIFT)) & AXBS_PRS4_M5_MASK) + +#define AXBS_PRS4_M6_MASK (0x7000000U) +#define AXBS_PRS4_M6_SHIFT (24U) +/*! M6 - Master 6 Priority + * 0b000..This master has level 1 or highest priority when accessing the slave port. + * 0b001..This master has level 2 priority when accessing the slave port. + * 0b010..This master has level 3 priority when accessing the slave port. + * 0b011..This master has level 4 priority when accessing the slave port. + * 0b100..This master has level 5 priority when accessing the slave port. + * 0b101..This master has level 6 priority when accessing the slave port. + * 0b110..This master has level 7 priority when accessing the slave port. + * 0b111..This master has level 8the or lowest priority when accessing the slave port. + */ +#define AXBS_PRS4_M6(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS4_M6_SHIFT)) & AXBS_PRS4_M6_MASK) + +#define AXBS_PRS4_M7_MASK (0x70000000U) +#define AXBS_PRS4_M7_SHIFT (28U) +/*! M7 - Master 7 Priority + * 0b000..This master has level 1 or highest priority when accessing the slave port. + * 0b001..This master has level 2 priority when accessing the slave port. + * 0b010..This master has level 3 priority when accessing the slave port. + * 0b011..This master has level 4 priority when accessing the slave port. + * 0b100..This master has level 5 priority when accessing the slave port. + * 0b101..This master has level 6 priority when accessing the slave port. + * 0b110..This master has level 7 priority when accessing the slave port. + * 0b111..This master has level 8 or lowest priority when accessing the slave port. + */ +#define AXBS_PRS4_M7(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS4_M7_SHIFT)) & AXBS_PRS4_M7_MASK) +/*! @} */ + +/*! @name CRS4 - Control Register */ +/*! @{ */ + +#define AXBS_CRS4_PARK_MASK (0x7U) +#define AXBS_CRS4_PARK_SHIFT (0U) +/*! PARK - Park + * 0b000..Park on master port M0 + * 0b001..Park on master port M1 + * 0b010..Park on master port M2 + * 0b011..Park on master port M3 + * 0b100..Park on master port M4 + * 0b101..Park on master port M5 + * 0b110..Park on master port M6 + * 0b111..Park on master port M7 + */ +#define AXBS_CRS4_PARK(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS4_PARK_SHIFT)) & AXBS_CRS4_PARK_MASK) + +#define AXBS_CRS4_PCTL_MASK (0x30U) +#define AXBS_CRS4_PCTL_SHIFT (4U) +/*! PCTL - Parking Control + * 0b00..When no master makes a request, the arbiter parks the slave port on the master port defined by the PARK bit field. + * 0b01..When no master makes a request, the arbiter parks the slave port on the last master to be in control of the slave port. + * 0b10..Low-power park. When no master makes a request, the slave port is not parked on a master and the arbiter + * drives all outputs to a constant safe state. + * 0b11..Reserved + */ +#define AXBS_CRS4_PCTL(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS4_PCTL_SHIFT)) & AXBS_CRS4_PCTL_MASK) + +#define AXBS_CRS4_ARB_MASK (0x300U) +#define AXBS_CRS4_ARB_SHIFT (8U) +/*! ARB - Arbitration Mode + * 0b00..Fixed priority + * 0b01..Round-robin (rotating) priority + * 0b10..Reserved + * 0b11..Reserved + */ +#define AXBS_CRS4_ARB(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS4_ARB_SHIFT)) & AXBS_CRS4_ARB_MASK) + +#define AXBS_CRS4_HPE0_MASK (0x10000U) +#define AXBS_CRS4_HPE0_SHIFT (16U) +/*! HPE0 - High Priority Elevation 0 + * 0b0..Master high-priority elevation for master 0. is disabled on this slave port. + * 0b1..Master high-priority elevation for master 0. is enabled on this slave port. + */ +#define AXBS_CRS4_HPE0(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS4_HPE0_SHIFT)) & AXBS_CRS4_HPE0_MASK) + +#define AXBS_CRS4_HPE1_MASK (0x20000U) +#define AXBS_CRS4_HPE1_SHIFT (17U) +/*! HPE1 - High Priority Elevation 1 + * 0b0..Master high-priority elevation for master 1. is disabled on this slave port. + * 0b1..Master high-priority elevation for master 1. is enabled on this slave port. + */ +#define AXBS_CRS4_HPE1(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS4_HPE1_SHIFT)) & AXBS_CRS4_HPE1_MASK) + +#define AXBS_CRS4_HPE2_MASK (0x40000U) +#define AXBS_CRS4_HPE2_SHIFT (18U) +/*! HPE2 - High Priority Elevation 2 + * 0b0..Master high-priority elevation for master 2. is disabled on this slave port. + * 0b1..Master high-priority elevation for master 2. is enabled on this slave port. + */ +#define AXBS_CRS4_HPE2(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS4_HPE2_SHIFT)) & AXBS_CRS4_HPE2_MASK) + +#define AXBS_CRS4_HPE3_MASK (0x80000U) +#define AXBS_CRS4_HPE3_SHIFT (19U) +/*! HPE3 - High Priority Elevation 3 + * 0b0..Master high-priority elevation for master 3. is disabled on this slave port. + * 0b1..Master high-priority elevation for master 3. is enabled on this slave port. + */ +#define AXBS_CRS4_HPE3(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS4_HPE3_SHIFT)) & AXBS_CRS4_HPE3_MASK) + +#define AXBS_CRS4_HPE4_MASK (0x100000U) +#define AXBS_CRS4_HPE4_SHIFT (20U) +/*! HPE4 - High Priority Elevation 4 + * 0b0..Master high-priority elevation for master 4. is disabled on this slave port. + * 0b1..Master high-priority elevation for master 4. is enabled on this slave port. + */ +#define AXBS_CRS4_HPE4(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS4_HPE4_SHIFT)) & AXBS_CRS4_HPE4_MASK) + +#define AXBS_CRS4_HPE5_MASK (0x200000U) +#define AXBS_CRS4_HPE5_SHIFT (21U) +/*! HPE5 - High Priority Elevation 5 + * 0b0..Master high-priority elevation for master 5. is disabled on this slave port. + * 0b1..Master high-priority elevation for master 5. is enabled on this slave port. + */ +#define AXBS_CRS4_HPE5(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS4_HPE5_SHIFT)) & AXBS_CRS4_HPE5_MASK) + +#define AXBS_CRS4_HPE6_MASK (0x400000U) +#define AXBS_CRS4_HPE6_SHIFT (22U) +/*! HPE6 - High Priority Elevation 6 + * 0b0..Master high-priority elevation for master 6. is disabled on this slave port. + * 0b1..Master high-priority elevation for master 6. is enabled on this slave port. + */ +#define AXBS_CRS4_HPE6(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS4_HPE6_SHIFT)) & AXBS_CRS4_HPE6_MASK) + +#define AXBS_CRS4_HPE7_MASK (0x800000U) +#define AXBS_CRS4_HPE7_SHIFT (23U) +/*! HPE7 - High Priority Elevation 7 + * 0b0..Master high-priority elevation for master 7. is disabled on this slave port. + * 0b1..Master high-priority elevation for master 7. is enabled on this slave port. + */ +#define AXBS_CRS4_HPE7(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS4_HPE7_SHIFT)) & AXBS_CRS4_HPE7_MASK) + +#define AXBS_CRS4_RO_MASK (0x80000000U) +#define AXBS_CRS4_RO_SHIFT (31U) +/*! RO - Read Only + * 0b0..The CRSn and PRSn registers are writeable + * 0b1..The CRSn and PRSn registers are read-only and cannot be written (attempted writes have no effect on the + * registers and result in a bus error response). + */ +#define AXBS_CRS4_RO(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS4_RO_SHIFT)) & AXBS_CRS4_RO_MASK) +/*! @} */ + +/*! @name PRS5 - Priority Slave Registers */ +/*! @{ */ + +#define AXBS_PRS5_M0_MASK (0x7U) +#define AXBS_PRS5_M0_SHIFT (0U) +/*! M0 - Master 0 Priority + * 0b000..This master has level 1 or highest priority when accessing the slave port. + * 0b001..This master has level 2 priority when accessing the slave port. + * 0b010..This master has level 3 priority when accessing the slave port. + * 0b011..This master has level 4 priority when accessing the slave port. + * 0b100..This master has level 5 priority when accessing the slave port. + * 0b101..This master has level 6 priority when accessing the slave port. + * 0b110..This master has level 7 priority when accessing the slave port. + * 0b111..This master has level 8 or the lowest priority when accessing the slave port. + */ +#define AXBS_PRS5_M0(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS5_M0_SHIFT)) & AXBS_PRS5_M0_MASK) + +#define AXBS_PRS5_M1_MASK (0x70U) +#define AXBS_PRS5_M1_SHIFT (4U) +/*! M1 - Master 1 Priority + * 0b000..This master has level 1 or highest priority when accessing the slave port. + * 0b001..This master has level 2 priority when accessing the slave port. + * 0b010..This master has level 3 priority when accessing the slave port. + * 0b011..This master has level 4 priority when accessing the slave port. + * 0b100..This master has level 5 priority when accessing the slave port. + * 0b101..This master has level 6 priority when accessing the slave port. + * 0b110..This master has level 7 priority when accessing the slave port. + * 0b111..This master has level 8 or lowest priority when accessing the slave port. + */ +#define AXBS_PRS5_M1(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS5_M1_SHIFT)) & AXBS_PRS5_M1_MASK) + +#define AXBS_PRS5_M2_MASK (0x700U) +#define AXBS_PRS5_M2_SHIFT (8U) +/*! M2 - Master 2 Priority + * 0b000..This master has level 1 or highest priority when accessing the slave port. + * 0b001..This master has level 2 priority when accessing the slave port. + * 0b010..This master has level 3 priority when accessing the slave port. + * 0b011..This master has level 4 priority when accessing the slave port. + * 0b100..This master has level 5 priority when accessing the slave port. + * 0b101..This master has level 6 priority when accessing the slave port. + * 0b110..This master has level 7 priority when accessing the slave port. + * 0b111..This master has level 8the or lowest priority when accessing the slave port. + */ +#define AXBS_PRS5_M2(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS5_M2_SHIFT)) & AXBS_PRS5_M2_MASK) + +#define AXBS_PRS5_M3_MASK (0x7000U) +#define AXBS_PRS5_M3_SHIFT (12U) +/*! M3 - Master 3 Priority + * 0b000..This master has level 1 or highest priority when accessing the slave port. + * 0b001..This master has level 2 priority when accessing the slave port. + * 0b010..This master has level 3 priority when accessing the slave port. + * 0b011..This master has level 4 priority when accessing the slave port. + * 0b100..This master has level 5 priority when accessing the slave port. + * 0b101..This master has level 6 priority when accessing the slave port. + * 0b110..This master has level 7 priority when accessing the slave port. + * 0b111..This master has level 8the or lowest priority when accessing the slave port. + */ +#define AXBS_PRS5_M3(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS5_M3_SHIFT)) & AXBS_PRS5_M3_MASK) + +#define AXBS_PRS5_M4_MASK (0x70000U) +#define AXBS_PRS5_M4_SHIFT (16U) +/*! M4 - Master 4 Priority + * 0b000..This master has level 1 or highest priority when accessing the slave port. + * 0b001..This master has level 2 priority when accessing the slave port. + * 0b010..This master has level 3 priority when accessing the slave port. + * 0b011..This master has level 4 priority when accessing the slave port. + * 0b100..This master has level 5 priority when accessing the slave port. + * 0b101..This master has level 6 priority when accessing the slave port. + * 0b110..This master has level 7 priority when accessing the slave port. + * 0b111..This master has level 8 or lowest priority when accessing the slave port. + */ +#define AXBS_PRS5_M4(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS5_M4_SHIFT)) & AXBS_PRS5_M4_MASK) + +#define AXBS_PRS5_M5_MASK (0x700000U) +#define AXBS_PRS5_M5_SHIFT (20U) +/*! M5 - Master 5 Priority + * 0b000..This master has level 1 or highest priority when accessing the slave port. + * 0b001..This master has level 2 priority when accessing the slave port. + * 0b010..This master has level 3 priority when accessing the slave port. + * 0b011..This master has level 4 priority when accessing the slave port. + * 0b100..This master has level 5 priority when accessing the slave port. + * 0b101..This master has level 6 priority when accessing the slave port. + * 0b110..This master has level 7 priority when accessing the slave port. + * 0b111..This master has level 8 or lowest priority when accessing the slave port. + */ +#define AXBS_PRS5_M5(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS5_M5_SHIFT)) & AXBS_PRS5_M5_MASK) + +#define AXBS_PRS5_M6_MASK (0x7000000U) +#define AXBS_PRS5_M6_SHIFT (24U) +/*! M6 - Master 6 Priority + * 0b000..This master has level 1 or highest priority when accessing the slave port. + * 0b001..This master has level 2 priority when accessing the slave port. + * 0b010..This master has level 3 priority when accessing the slave port. + * 0b011..This master has level 4 priority when accessing the slave port. + * 0b100..This master has level 5 priority when accessing the slave port. + * 0b101..This master has level 6 priority when accessing the slave port. + * 0b110..This master has level 7 priority when accessing the slave port. + * 0b111..This master has level 8the or lowest priority when accessing the slave port. + */ +#define AXBS_PRS5_M6(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS5_M6_SHIFT)) & AXBS_PRS5_M6_MASK) + +#define AXBS_PRS5_M7_MASK (0x70000000U) +#define AXBS_PRS5_M7_SHIFT (28U) +/*! M7 - Master 7 Priority + * 0b000..This master has level 1 or highest priority when accessing the slave port. + * 0b001..This master has level 2 priority when accessing the slave port. + * 0b010..This master has level 3 priority when accessing the slave port. + * 0b011..This master has level 4 priority when accessing the slave port. + * 0b100..This master has level 5 priority when accessing the slave port. + * 0b101..This master has level 6 priority when accessing the slave port. + * 0b110..This master has level 7 priority when accessing the slave port. + * 0b111..This master has level 8 or lowest priority when accessing the slave port. + */ +#define AXBS_PRS5_M7(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS5_M7_SHIFT)) & AXBS_PRS5_M7_MASK) +/*! @} */ + +/*! @name CRS5 - Control Register */ +/*! @{ */ + +#define AXBS_CRS5_PARK_MASK (0x7U) +#define AXBS_CRS5_PARK_SHIFT (0U) +/*! PARK - Park + * 0b000..Park on master port M0 + * 0b001..Park on master port M1 + * 0b010..Park on master port M2 + * 0b011..Park on master port M3 + * 0b100..Park on master port M4 + * 0b101..Park on master port M5 + * 0b110..Park on master port M6 + * 0b111..Park on master port M7 + */ +#define AXBS_CRS5_PARK(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS5_PARK_SHIFT)) & AXBS_CRS5_PARK_MASK) + +#define AXBS_CRS5_PCTL_MASK (0x30U) +#define AXBS_CRS5_PCTL_SHIFT (4U) +/*! PCTL - Parking Control + * 0b00..When no master makes a request, the arbiter parks the slave port on the master port defined by the PARK bit field. + * 0b01..When no master makes a request, the arbiter parks the slave port on the last master to be in control of the slave port. + * 0b10..Low-power park. When no master makes a request, the slave port is not parked on a master and the arbiter + * drives all outputs to a constant safe state. + * 0b11..Reserved + */ +#define AXBS_CRS5_PCTL(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS5_PCTL_SHIFT)) & AXBS_CRS5_PCTL_MASK) + +#define AXBS_CRS5_ARB_MASK (0x300U) +#define AXBS_CRS5_ARB_SHIFT (8U) +/*! ARB - Arbitration Mode + * 0b00..Fixed priority + * 0b01..Round-robin (rotating) priority + * 0b10..Reserved + * 0b11..Reserved + */ +#define AXBS_CRS5_ARB(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS5_ARB_SHIFT)) & AXBS_CRS5_ARB_MASK) + +#define AXBS_CRS5_HPE0_MASK (0x10000U) +#define AXBS_CRS5_HPE0_SHIFT (16U) +/*! HPE0 - High Priority Elevation 0 + * 0b0..Master high-priority elevation for master 0. is disabled on this slave port. + * 0b1..Master high-priority elevation for master 0. is enabled on this slave port. + */ +#define AXBS_CRS5_HPE0(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS5_HPE0_SHIFT)) & AXBS_CRS5_HPE0_MASK) + +#define AXBS_CRS5_HPE1_MASK (0x20000U) +#define AXBS_CRS5_HPE1_SHIFT (17U) +/*! HPE1 - High Priority Elevation 1 + * 0b0..Master high-priority elevation for master 1. is disabled on this slave port. + * 0b1..Master high-priority elevation for master 1. is enabled on this slave port. + */ +#define AXBS_CRS5_HPE1(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS5_HPE1_SHIFT)) & AXBS_CRS5_HPE1_MASK) + +#define AXBS_CRS5_HPE2_MASK (0x40000U) +#define AXBS_CRS5_HPE2_SHIFT (18U) +/*! HPE2 - High Priority Elevation 2 + * 0b0..Master high-priority elevation for master 2. is disabled on this slave port. + * 0b1..Master high-priority elevation for master 2. is enabled on this slave port. + */ +#define AXBS_CRS5_HPE2(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS5_HPE2_SHIFT)) & AXBS_CRS5_HPE2_MASK) + +#define AXBS_CRS5_HPE3_MASK (0x80000U) +#define AXBS_CRS5_HPE3_SHIFT (19U) +/*! HPE3 - High Priority Elevation 3 + * 0b0..Master high-priority elevation for master 3. is disabled on this slave port. + * 0b1..Master high-priority elevation for master 3. is enabled on this slave port. + */ +#define AXBS_CRS5_HPE3(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS5_HPE3_SHIFT)) & AXBS_CRS5_HPE3_MASK) + +#define AXBS_CRS5_HPE4_MASK (0x100000U) +#define AXBS_CRS5_HPE4_SHIFT (20U) +/*! HPE4 - High Priority Elevation 4 + * 0b0..Master high-priority elevation for master 4. is disabled on this slave port. + * 0b1..Master high-priority elevation for master 4. is enabled on this slave port. + */ +#define AXBS_CRS5_HPE4(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS5_HPE4_SHIFT)) & AXBS_CRS5_HPE4_MASK) + +#define AXBS_CRS5_HPE5_MASK (0x200000U) +#define AXBS_CRS5_HPE5_SHIFT (21U) +/*! HPE5 - High Priority Elevation 5 + * 0b0..Master high-priority elevation for master 5. is disabled on this slave port. + * 0b1..Master high-priority elevation for master 5. is enabled on this slave port. + */ +#define AXBS_CRS5_HPE5(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS5_HPE5_SHIFT)) & AXBS_CRS5_HPE5_MASK) + +#define AXBS_CRS5_HPE6_MASK (0x400000U) +#define AXBS_CRS5_HPE6_SHIFT (22U) +/*! HPE6 - High Priority Elevation 6 + * 0b0..Master high-priority elevation for master 6. is disabled on this slave port. + * 0b1..Master high-priority elevation for master 6. is enabled on this slave port. + */ +#define AXBS_CRS5_HPE6(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS5_HPE6_SHIFT)) & AXBS_CRS5_HPE6_MASK) + +#define AXBS_CRS5_HPE7_MASK (0x800000U) +#define AXBS_CRS5_HPE7_SHIFT (23U) +/*! HPE7 - High Priority Elevation 7 + * 0b0..Master high-priority elevation for master 7. is disabled on this slave port. + * 0b1..Master high-priority elevation for master 7. is enabled on this slave port. + */ +#define AXBS_CRS5_HPE7(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS5_HPE7_SHIFT)) & AXBS_CRS5_HPE7_MASK) + +#define AXBS_CRS5_RO_MASK (0x80000000U) +#define AXBS_CRS5_RO_SHIFT (31U) +/*! RO - Read Only + * 0b0..The CRSn and PRSn registers are writeable + * 0b1..The CRSn and PRSn registers are read-only and cannot be written (attempted writes have no effect on the + * registers and result in a bus error response). + */ +#define AXBS_CRS5_RO(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS5_RO_SHIFT)) & AXBS_CRS5_RO_MASK) +/*! @} */ + +/*! @name PRS6 - Priority Slave Registers */ +/*! @{ */ + +#define AXBS_PRS6_M0_MASK (0x7U) +#define AXBS_PRS6_M0_SHIFT (0U) +/*! M0 - Master 0 Priority + * 0b000..This master has level 1 or highest priority when accessing the slave port. + * 0b001..This master has level 2 priority when accessing the slave port. + * 0b010..This master has level 3 priority when accessing the slave port. + * 0b011..This master has level 4 priority when accessing the slave port. + * 0b100..This master has level 5 priority when accessing the slave port. + * 0b101..This master has level 6 priority when accessing the slave port. + * 0b110..This master has level 7 priority when accessing the slave port. + * 0b111..This master has level 8 or the lowest priority when accessing the slave port. + */ +#define AXBS_PRS6_M0(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS6_M0_SHIFT)) & AXBS_PRS6_M0_MASK) + +#define AXBS_PRS6_M1_MASK (0x70U) +#define AXBS_PRS6_M1_SHIFT (4U) +/*! M1 - Master 1 Priority + * 0b000..This master has level 1 or highest priority when accessing the slave port. + * 0b001..This master has level 2 priority when accessing the slave port. + * 0b010..This master has level 3 priority when accessing the slave port. + * 0b011..This master has level 4 priority when accessing the slave port. + * 0b100..This master has level 5 priority when accessing the slave port. + * 0b101..This master has level 6 priority when accessing the slave port. + * 0b110..This master has level 7 priority when accessing the slave port. + * 0b111..This master has level 8 or lowest priority when accessing the slave port. + */ +#define AXBS_PRS6_M1(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS6_M1_SHIFT)) & AXBS_PRS6_M1_MASK) + +#define AXBS_PRS6_M2_MASK (0x700U) +#define AXBS_PRS6_M2_SHIFT (8U) +/*! M2 - Master 2 Priority + * 0b000..This master has level 1 or highest priority when accessing the slave port. + * 0b001..This master has level 2 priority when accessing the slave port. + * 0b010..This master has level 3 priority when accessing the slave port. + * 0b011..This master has level 4 priority when accessing the slave port. + * 0b100..This master has level 5 priority when accessing the slave port. + * 0b101..This master has level 6 priority when accessing the slave port. + * 0b110..This master has level 7 priority when accessing the slave port. + * 0b111..This master has level 8the or lowest priority when accessing the slave port. + */ +#define AXBS_PRS6_M2(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS6_M2_SHIFT)) & AXBS_PRS6_M2_MASK) + +#define AXBS_PRS6_M3_MASK (0x7000U) +#define AXBS_PRS6_M3_SHIFT (12U) +/*! M3 - Master 3 Priority + * 0b000..This master has level 1 or highest priority when accessing the slave port. + * 0b001..This master has level 2 priority when accessing the slave port. + * 0b010..This master has level 3 priority when accessing the slave port. + * 0b011..This master has level 4 priority when accessing the slave port. + * 0b100..This master has level 5 priority when accessing the slave port. + * 0b101..This master has level 6 priority when accessing the slave port. + * 0b110..This master has level 7 priority when accessing the slave port. + * 0b111..This master has level 8the or lowest priority when accessing the slave port. + */ +#define AXBS_PRS6_M3(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS6_M3_SHIFT)) & AXBS_PRS6_M3_MASK) + +#define AXBS_PRS6_M4_MASK (0x70000U) +#define AXBS_PRS6_M4_SHIFT (16U) +/*! M4 - Master 4 Priority + * 0b000..This master has level 1 or highest priority when accessing the slave port. + * 0b001..This master has level 2 priority when accessing the slave port. + * 0b010..This master has level 3 priority when accessing the slave port. + * 0b011..This master has level 4 priority when accessing the slave port. + * 0b100..This master has level 5 priority when accessing the slave port. + * 0b101..This master has level 6 priority when accessing the slave port. + * 0b110..This master has level 7 priority when accessing the slave port. + * 0b111..This master has level 8 or lowest priority when accessing the slave port. + */ +#define AXBS_PRS6_M4(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS6_M4_SHIFT)) & AXBS_PRS6_M4_MASK) + +#define AXBS_PRS6_M5_MASK (0x700000U) +#define AXBS_PRS6_M5_SHIFT (20U) +/*! M5 - Master 5 Priority + * 0b000..This master has level 1 or highest priority when accessing the slave port. + * 0b001..This master has level 2 priority when accessing the slave port. + * 0b010..This master has level 3 priority when accessing the slave port. + * 0b011..This master has level 4 priority when accessing the slave port. + * 0b100..This master has level 5 priority when accessing the slave port. + * 0b101..This master has level 6 priority when accessing the slave port. + * 0b110..This master has level 7 priority when accessing the slave port. + * 0b111..This master has level 8 or lowest priority when accessing the slave port. + */ +#define AXBS_PRS6_M5(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS6_M5_SHIFT)) & AXBS_PRS6_M5_MASK) + +#define AXBS_PRS6_M6_MASK (0x7000000U) +#define AXBS_PRS6_M6_SHIFT (24U) +/*! M6 - Master 6 Priority + * 0b000..This master has level 1 or highest priority when accessing the slave port. + * 0b001..This master has level 2 priority when accessing the slave port. + * 0b010..This master has level 3 priority when accessing the slave port. + * 0b011..This master has level 4 priority when accessing the slave port. + * 0b100..This master has level 5 priority when accessing the slave port. + * 0b101..This master has level 6 priority when accessing the slave port. + * 0b110..This master has level 7 priority when accessing the slave port. + * 0b111..This master has level 8the or lowest priority when accessing the slave port. + */ +#define AXBS_PRS6_M6(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS6_M6_SHIFT)) & AXBS_PRS6_M6_MASK) + +#define AXBS_PRS6_M7_MASK (0x70000000U) +#define AXBS_PRS6_M7_SHIFT (28U) +/*! M7 - Master 7 Priority + * 0b000..This master has level 1 or highest priority when accessing the slave port. + * 0b001..This master has level 2 priority when accessing the slave port. + * 0b010..This master has level 3 priority when accessing the slave port. + * 0b011..This master has level 4 priority when accessing the slave port. + * 0b100..This master has level 5 priority when accessing the slave port. + * 0b101..This master has level 6 priority when accessing the slave port. + * 0b110..This master has level 7 priority when accessing the slave port. + * 0b111..This master has level 8 or lowest priority when accessing the slave port. + */ +#define AXBS_PRS6_M7(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS6_M7_SHIFT)) & AXBS_PRS6_M7_MASK) +/*! @} */ + +/*! @name CRS6 - Control Register */ +/*! @{ */ + +#define AXBS_CRS6_PARK_MASK (0x7U) +#define AXBS_CRS6_PARK_SHIFT (0U) +/*! PARK - Park + * 0b000..Park on master port M0 + * 0b001..Park on master port M1 + * 0b010..Park on master port M2 + * 0b011..Park on master port M3 + * 0b100..Park on master port M4 + * 0b101..Park on master port M5 + * 0b110..Park on master port M6 + * 0b111..Park on master port M7 + */ +#define AXBS_CRS6_PARK(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS6_PARK_SHIFT)) & AXBS_CRS6_PARK_MASK) + +#define AXBS_CRS6_PCTL_MASK (0x30U) +#define AXBS_CRS6_PCTL_SHIFT (4U) +/*! PCTL - Parking Control + * 0b00..When no master makes a request, the arbiter parks the slave port on the master port defined by the PARK bit field. + * 0b01..When no master makes a request, the arbiter parks the slave port on the last master to be in control of the slave port. + * 0b10..Low-power park. When no master makes a request, the slave port is not parked on a master and the arbiter + * drives all outputs to a constant safe state. + * 0b11..Reserved + */ +#define AXBS_CRS6_PCTL(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS6_PCTL_SHIFT)) & AXBS_CRS6_PCTL_MASK) + +#define AXBS_CRS6_ARB_MASK (0x300U) +#define AXBS_CRS6_ARB_SHIFT (8U) +/*! ARB - Arbitration Mode + * 0b00..Fixed priority + * 0b01..Round-robin (rotating) priority + * 0b10..Reserved + * 0b11..Reserved + */ +#define AXBS_CRS6_ARB(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS6_ARB_SHIFT)) & AXBS_CRS6_ARB_MASK) + +#define AXBS_CRS6_HPE0_MASK (0x10000U) +#define AXBS_CRS6_HPE0_SHIFT (16U) +/*! HPE0 - High Priority Elevation 0 + * 0b0..Master high-priority elevation for master 0. is disabled on this slave port. + * 0b1..Master high-priority elevation for master 0. is enabled on this slave port. + */ +#define AXBS_CRS6_HPE0(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS6_HPE0_SHIFT)) & AXBS_CRS6_HPE0_MASK) + +#define AXBS_CRS6_HPE1_MASK (0x20000U) +#define AXBS_CRS6_HPE1_SHIFT (17U) +/*! HPE1 - High Priority Elevation 1 + * 0b0..Master high-priority elevation for master 1. is disabled on this slave port. + * 0b1..Master high-priority elevation for master 1. is enabled on this slave port. + */ +#define AXBS_CRS6_HPE1(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS6_HPE1_SHIFT)) & AXBS_CRS6_HPE1_MASK) + +#define AXBS_CRS6_HPE2_MASK (0x40000U) +#define AXBS_CRS6_HPE2_SHIFT (18U) +/*! HPE2 - High Priority Elevation 2 + * 0b0..Master high-priority elevation for master 2. is disabled on this slave port. + * 0b1..Master high-priority elevation for master 2. is enabled on this slave port. + */ +#define AXBS_CRS6_HPE2(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS6_HPE2_SHIFT)) & AXBS_CRS6_HPE2_MASK) + +#define AXBS_CRS6_HPE3_MASK (0x80000U) +#define AXBS_CRS6_HPE3_SHIFT (19U) +/*! HPE3 - High Priority Elevation 3 + * 0b0..Master high-priority elevation for master 3. is disabled on this slave port. + * 0b1..Master high-priority elevation for master 3. is enabled on this slave port. + */ +#define AXBS_CRS6_HPE3(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS6_HPE3_SHIFT)) & AXBS_CRS6_HPE3_MASK) + +#define AXBS_CRS6_HPE4_MASK (0x100000U) +#define AXBS_CRS6_HPE4_SHIFT (20U) +/*! HPE4 - High Priority Elevation 4 + * 0b0..Master high-priority elevation for master 4. is disabled on this slave port. + * 0b1..Master high-priority elevation for master 4. is enabled on this slave port. + */ +#define AXBS_CRS6_HPE4(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS6_HPE4_SHIFT)) & AXBS_CRS6_HPE4_MASK) + +#define AXBS_CRS6_HPE5_MASK (0x200000U) +#define AXBS_CRS6_HPE5_SHIFT (21U) +/*! HPE5 - High Priority Elevation 5 + * 0b0..Master high-priority elevation for master 5. is disabled on this slave port. + * 0b1..Master high-priority elevation for master 5. is enabled on this slave port. + */ +#define AXBS_CRS6_HPE5(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS6_HPE5_SHIFT)) & AXBS_CRS6_HPE5_MASK) + +#define AXBS_CRS6_HPE6_MASK (0x400000U) +#define AXBS_CRS6_HPE6_SHIFT (22U) +/*! HPE6 - High Priority Elevation 6 + * 0b0..Master high-priority elevation for master 6. is disabled on this slave port. + * 0b1..Master high-priority elevation for master 6. is enabled on this slave port. + */ +#define AXBS_CRS6_HPE6(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS6_HPE6_SHIFT)) & AXBS_CRS6_HPE6_MASK) + +#define AXBS_CRS6_HPE7_MASK (0x800000U) +#define AXBS_CRS6_HPE7_SHIFT (23U) +/*! HPE7 - High Priority Elevation 7 + * 0b0..Master high-priority elevation for master 7. is disabled on this slave port. + * 0b1..Master high-priority elevation for master 7. is enabled on this slave port. + */ +#define AXBS_CRS6_HPE7(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS6_HPE7_SHIFT)) & AXBS_CRS6_HPE7_MASK) + +#define AXBS_CRS6_RO_MASK (0x80000000U) +#define AXBS_CRS6_RO_SHIFT (31U) +/*! RO - Read Only + * 0b0..The CRSn and PRSn registers are writeable + * 0b1..The CRSn and PRSn registers are read-only and cannot be written (attempted writes have no effect on the + * registers and result in a bus error response). + */ +#define AXBS_CRS6_RO(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS6_RO_SHIFT)) & AXBS_CRS6_RO_MASK) +/*! @} */ + +/*! @name PRS7 - Priority Slave Registers */ +/*! @{ */ + +#define AXBS_PRS7_M0_MASK (0x7U) +#define AXBS_PRS7_M0_SHIFT (0U) +/*! M0 - Master 0 Priority + * 0b000..This master has level 1 or highest priority when accessing the slave port. + * 0b001..This master has level 2 priority when accessing the slave port. + * 0b010..This master has level 3 priority when accessing the slave port. + * 0b011..This master has level 4 priority when accessing the slave port. + * 0b100..This master has level 5 priority when accessing the slave port. + * 0b101..This master has level 6 priority when accessing the slave port. + * 0b110..This master has level 7 priority when accessing the slave port. + * 0b111..This master has level 8 or the lowest priority when accessing the slave port. + */ +#define AXBS_PRS7_M0(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS7_M0_SHIFT)) & AXBS_PRS7_M0_MASK) + +#define AXBS_PRS7_M1_MASK (0x70U) +#define AXBS_PRS7_M1_SHIFT (4U) +/*! M1 - Master 1 Priority + * 0b000..This master has level 1 or highest priority when accessing the slave port. + * 0b001..This master has level 2 priority when accessing the slave port. + * 0b010..This master has level 3 priority when accessing the slave port. + * 0b011..This master has level 4 priority when accessing the slave port. + * 0b100..This master has level 5 priority when accessing the slave port. + * 0b101..This master has level 6 priority when accessing the slave port. + * 0b110..This master has level 7 priority when accessing the slave port. + * 0b111..This master has level 8 or lowest priority when accessing the slave port. + */ +#define AXBS_PRS7_M1(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS7_M1_SHIFT)) & AXBS_PRS7_M1_MASK) + +#define AXBS_PRS7_M2_MASK (0x700U) +#define AXBS_PRS7_M2_SHIFT (8U) +/*! M2 - Master 2 Priority + * 0b000..This master has level 1 or highest priority when accessing the slave port. + * 0b001..This master has level 2 priority when accessing the slave port. + * 0b010..This master has level 3 priority when accessing the slave port. + * 0b011..This master has level 4 priority when accessing the slave port. + * 0b100..This master has level 5 priority when accessing the slave port. + * 0b101..This master has level 6 priority when accessing the slave port. + * 0b110..This master has level 7 priority when accessing the slave port. + * 0b111..This master has level 8the or lowest priority when accessing the slave port. + */ +#define AXBS_PRS7_M2(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS7_M2_SHIFT)) & AXBS_PRS7_M2_MASK) + +#define AXBS_PRS7_M3_MASK (0x7000U) +#define AXBS_PRS7_M3_SHIFT (12U) +/*! M3 - Master 3 Priority + * 0b000..This master has level 1 or highest priority when accessing the slave port. + * 0b001..This master has level 2 priority when accessing the slave port. + * 0b010..This master has level 3 priority when accessing the slave port. + * 0b011..This master has level 4 priority when accessing the slave port. + * 0b100..This master has level 5 priority when accessing the slave port. + * 0b101..This master has level 6 priority when accessing the slave port. + * 0b110..This master has level 7 priority when accessing the slave port. + * 0b111..This master has level 8the or lowest priority when accessing the slave port. + */ +#define AXBS_PRS7_M3(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS7_M3_SHIFT)) & AXBS_PRS7_M3_MASK) + +#define AXBS_PRS7_M4_MASK (0x70000U) +#define AXBS_PRS7_M4_SHIFT (16U) +/*! M4 - Master 4 Priority + * 0b000..This master has level 1 or highest priority when accessing the slave port. + * 0b001..This master has level 2 priority when accessing the slave port. + * 0b010..This master has level 3 priority when accessing the slave port. + * 0b011..This master has level 4 priority when accessing the slave port. + * 0b100..This master has level 5 priority when accessing the slave port. + * 0b101..This master has level 6 priority when accessing the slave port. + * 0b110..This master has level 7 priority when accessing the slave port. + * 0b111..This master has level 8 or lowest priority when accessing the slave port. + */ +#define AXBS_PRS7_M4(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS7_M4_SHIFT)) & AXBS_PRS7_M4_MASK) + +#define AXBS_PRS7_M5_MASK (0x700000U) +#define AXBS_PRS7_M5_SHIFT (20U) +/*! M5 - Master 5 Priority + * 0b000..This master has level 1 or highest priority when accessing the slave port. + * 0b001..This master has level 2 priority when accessing the slave port. + * 0b010..This master has level 3 priority when accessing the slave port. + * 0b011..This master has level 4 priority when accessing the slave port. + * 0b100..This master has level 5 priority when accessing the slave port. + * 0b101..This master has level 6 priority when accessing the slave port. + * 0b110..This master has level 7 priority when accessing the slave port. + * 0b111..This master has level 8 or lowest priority when accessing the slave port. + */ +#define AXBS_PRS7_M5(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS7_M5_SHIFT)) & AXBS_PRS7_M5_MASK) + +#define AXBS_PRS7_M6_MASK (0x7000000U) +#define AXBS_PRS7_M6_SHIFT (24U) +/*! M6 - Master 6 Priority + * 0b000..This master has level 1 or highest priority when accessing the slave port. + * 0b001..This master has level 2 priority when accessing the slave port. + * 0b010..This master has level 3 priority when accessing the slave port. + * 0b011..This master has level 4 priority when accessing the slave port. + * 0b100..This master has level 5 priority when accessing the slave port. + * 0b101..This master has level 6 priority when accessing the slave port. + * 0b110..This master has level 7 priority when accessing the slave port. + * 0b111..This master has level 8the or lowest priority when accessing the slave port. + */ +#define AXBS_PRS7_M6(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS7_M6_SHIFT)) & AXBS_PRS7_M6_MASK) + +#define AXBS_PRS7_M7_MASK (0x70000000U) +#define AXBS_PRS7_M7_SHIFT (28U) +/*! M7 - Master 7 Priority + * 0b000..This master has level 1 or highest priority when accessing the slave port. + * 0b001..This master has level 2 priority when accessing the slave port. + * 0b010..This master has level 3 priority when accessing the slave port. + * 0b011..This master has level 4 priority when accessing the slave port. + * 0b100..This master has level 5 priority when accessing the slave port. + * 0b101..This master has level 6 priority when accessing the slave port. + * 0b110..This master has level 7 priority when accessing the slave port. + * 0b111..This master has level 8 or lowest priority when accessing the slave port. + */ +#define AXBS_PRS7_M7(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS7_M7_SHIFT)) & AXBS_PRS7_M7_MASK) +/*! @} */ + +/*! @name CRS7 - Control Register */ +/*! @{ */ + +#define AXBS_CRS7_PARK_MASK (0x7U) +#define AXBS_CRS7_PARK_SHIFT (0U) +/*! PARK - Park + * 0b000..Park on master port M0 + * 0b001..Park on master port M1 + * 0b010..Park on master port M2 + * 0b011..Park on master port M3 + * 0b100..Park on master port M4 + * 0b101..Park on master port M5 + * 0b110..Park on master port M6 + * 0b111..Park on master port M7 + */ +#define AXBS_CRS7_PARK(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS7_PARK_SHIFT)) & AXBS_CRS7_PARK_MASK) + +#define AXBS_CRS7_PCTL_MASK (0x30U) +#define AXBS_CRS7_PCTL_SHIFT (4U) +/*! PCTL - Parking Control + * 0b00..When no master makes a request, the arbiter parks the slave port on the master port defined by the PARK bit field. + * 0b01..When no master makes a request, the arbiter parks the slave port on the last master to be in control of the slave port. + * 0b10..Low-power park. When no master makes a request, the slave port is not parked on a master and the arbiter + * drives all outputs to a constant safe state. + * 0b11..Reserved + */ +#define AXBS_CRS7_PCTL(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS7_PCTL_SHIFT)) & AXBS_CRS7_PCTL_MASK) + +#define AXBS_CRS7_ARB_MASK (0x300U) +#define AXBS_CRS7_ARB_SHIFT (8U) +/*! ARB - Arbitration Mode + * 0b00..Fixed priority + * 0b01..Round-robin (rotating) priority + * 0b10..Reserved + * 0b11..Reserved + */ +#define AXBS_CRS7_ARB(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS7_ARB_SHIFT)) & AXBS_CRS7_ARB_MASK) + +#define AXBS_CRS7_HPE0_MASK (0x10000U) +#define AXBS_CRS7_HPE0_SHIFT (16U) +/*! HPE0 - High Priority Elevation 0 + * 0b0..Master high-priority elevation for master 0. is disabled on this slave port. + * 0b1..Master high-priority elevation for master 0. is enabled on this slave port. + */ +#define AXBS_CRS7_HPE0(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS7_HPE0_SHIFT)) & AXBS_CRS7_HPE0_MASK) + +#define AXBS_CRS7_HPE1_MASK (0x20000U) +#define AXBS_CRS7_HPE1_SHIFT (17U) +/*! HPE1 - High Priority Elevation 1 + * 0b0..Master high-priority elevation for master 1. is disabled on this slave port. + * 0b1..Master high-priority elevation for master 1. is enabled on this slave port. + */ +#define AXBS_CRS7_HPE1(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS7_HPE1_SHIFT)) & AXBS_CRS7_HPE1_MASK) + +#define AXBS_CRS7_HPE2_MASK (0x40000U) +#define AXBS_CRS7_HPE2_SHIFT (18U) +/*! HPE2 - High Priority Elevation 2 + * 0b0..Master high-priority elevation for master 2. is disabled on this slave port. + * 0b1..Master high-priority elevation for master 2. is enabled on this slave port. + */ +#define AXBS_CRS7_HPE2(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS7_HPE2_SHIFT)) & AXBS_CRS7_HPE2_MASK) + +#define AXBS_CRS7_HPE3_MASK (0x80000U) +#define AXBS_CRS7_HPE3_SHIFT (19U) +/*! HPE3 - High Priority Elevation 3 + * 0b0..Master high-priority elevation for master 3. is disabled on this slave port. + * 0b1..Master high-priority elevation for master 3. is enabled on this slave port. + */ +#define AXBS_CRS7_HPE3(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS7_HPE3_SHIFT)) & AXBS_CRS7_HPE3_MASK) + +#define AXBS_CRS7_HPE4_MASK (0x100000U) +#define AXBS_CRS7_HPE4_SHIFT (20U) +/*! HPE4 - High Priority Elevation 4 + * 0b0..Master high-priority elevation for master 4. is disabled on this slave port. + * 0b1..Master high-priority elevation for master 4. is enabled on this slave port. + */ +#define AXBS_CRS7_HPE4(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS7_HPE4_SHIFT)) & AXBS_CRS7_HPE4_MASK) + +#define AXBS_CRS7_HPE5_MASK (0x200000U) +#define AXBS_CRS7_HPE5_SHIFT (21U) +/*! HPE5 - High Priority Elevation 5 + * 0b0..Master high-priority elevation for master 5. is disabled on this slave port. + * 0b1..Master high-priority elevation for master 5. is enabled on this slave port. + */ +#define AXBS_CRS7_HPE5(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS7_HPE5_SHIFT)) & AXBS_CRS7_HPE5_MASK) + +#define AXBS_CRS7_HPE6_MASK (0x400000U) +#define AXBS_CRS7_HPE6_SHIFT (22U) +/*! HPE6 - High Priority Elevation 6 + * 0b0..Master high-priority elevation for master 6. is disabled on this slave port. + * 0b1..Master high-priority elevation for master 6. is enabled on this slave port. + */ +#define AXBS_CRS7_HPE6(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS7_HPE6_SHIFT)) & AXBS_CRS7_HPE6_MASK) + +#define AXBS_CRS7_HPE7_MASK (0x800000U) +#define AXBS_CRS7_HPE7_SHIFT (23U) +/*! HPE7 - High Priority Elevation 7 + * 0b0..Master high-priority elevation for master 7. is disabled on this slave port. + * 0b1..Master high-priority elevation for master 7. is enabled on this slave port. + */ +#define AXBS_CRS7_HPE7(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS7_HPE7_SHIFT)) & AXBS_CRS7_HPE7_MASK) + +#define AXBS_CRS7_RO_MASK (0x80000000U) +#define AXBS_CRS7_RO_SHIFT (31U) +/*! RO - Read Only + * 0b0..The CRSn and PRSn registers are writeable + * 0b1..The CRSn and PRSn registers are read-only and cannot be written (attempted writes have no effect on the + * registers and result in a bus error response). + */ +#define AXBS_CRS7_RO(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS7_RO_SHIFT)) & AXBS_CRS7_RO_MASK) +/*! @} */ + +/*! @name MGPCR0 - Master General Purpose Control Register */ +/*! @{ */ + +#define AXBS_MGPCR0_AULB_MASK (0x7U) +#define AXBS_MGPCR0_AULB_SHIFT (0U) +/*! AULB - Arbitrates On Undefined Length Bursts + * 0b000..No arbitration is allowed during an undefined length burst. + * 0b001..Arbitration is allowed at any time during an undefined length burst. + * 0b010..Arbitration is allowed after four beats of an undefined length burst. + * 0b011..Arbitration is allowed after eight beats of an undefined length burst. + * 0b100..Arbitration is allowed after 16 beats of an undefined length burst. + * 0b101..Reserved + * 0b110..Reserved + * 0b111..Reserved + */ +#define AXBS_MGPCR0_AULB(x) (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR0_AULB_SHIFT)) & AXBS_MGPCR0_AULB_MASK) +/*! @} */ + +/*! @name MGPCR1 - Master General Purpose Control Register */ +/*! @{ */ + +#define AXBS_MGPCR1_AULB_MASK (0x7U) +#define AXBS_MGPCR1_AULB_SHIFT (0U) +/*! AULB - Arbitrates On Undefined Length Bursts + * 0b000..No arbitration is allowed during an undefined length burst. + * 0b001..Arbitration is allowed at any time during an undefined length burst. + * 0b010..Arbitration is allowed after four beats of an undefined length burst. + * 0b011..Arbitration is allowed after eight beats of an undefined length burst. + * 0b100..Arbitration is allowed after 16 beats of an undefined length burst. + * 0b101..Reserved + * 0b110..Reserved + * 0b111..Reserved + */ +#define AXBS_MGPCR1_AULB(x) (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR1_AULB_SHIFT)) & AXBS_MGPCR1_AULB_MASK) +/*! @} */ + +/*! @name MGPCR2 - Master General Purpose Control Register */ +/*! @{ */ + +#define AXBS_MGPCR2_AULB_MASK (0x7U) +#define AXBS_MGPCR2_AULB_SHIFT (0U) +/*! AULB - Arbitrates On Undefined Length Bursts + * 0b000..No arbitration is allowed during an undefined length burst. + * 0b001..Arbitration is allowed at any time during an undefined length burst. + * 0b010..Arbitration is allowed after four beats of an undefined length burst. + * 0b011..Arbitration is allowed after eight beats of an undefined length burst. + * 0b100..Arbitration is allowed after 16 beats of an undefined length burst. + * 0b101..Reserved + * 0b110..Reserved + * 0b111..Reserved + */ +#define AXBS_MGPCR2_AULB(x) (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR2_AULB_SHIFT)) & AXBS_MGPCR2_AULB_MASK) +/*! @} */ + +/*! @name MGPCR3 - Master General Purpose Control Register */ +/*! @{ */ + +#define AXBS_MGPCR3_AULB_MASK (0x7U) +#define AXBS_MGPCR3_AULB_SHIFT (0U) +/*! AULB - Arbitrates On Undefined Length Bursts + * 0b000..No arbitration is allowed during an undefined length burst. + * 0b001..Arbitration is allowed at any time during an undefined length burst. + * 0b010..Arbitration is allowed after four beats of an undefined length burst. + * 0b011..Arbitration is allowed after eight beats of an undefined length burst. + * 0b100..Arbitration is allowed after 16 beats of an undefined length burst. + * 0b101..Reserved + * 0b110..Reserved + * 0b111..Reserved + */ +#define AXBS_MGPCR3_AULB(x) (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR3_AULB_SHIFT)) & AXBS_MGPCR3_AULB_MASK) +/*! @} */ + +/*! @name MGPCR4 - Master General Purpose Control Register */ +/*! @{ */ + +#define AXBS_MGPCR4_AULB_MASK (0x7U) +#define AXBS_MGPCR4_AULB_SHIFT (0U) +/*! AULB - Arbitrates On Undefined Length Bursts + * 0b000..No arbitration is allowed during an undefined length burst. + * 0b001..Arbitration is allowed at any time during an undefined length burst. + * 0b010..Arbitration is allowed after four beats of an undefined length burst. + * 0b011..Arbitration is allowed after eight beats of an undefined length burst. + * 0b100..Arbitration is allowed after 16 beats of an undefined length burst. + * 0b101..Reserved + * 0b110..Reserved + * 0b111..Reserved + */ +#define AXBS_MGPCR4_AULB(x) (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR4_AULB_SHIFT)) & AXBS_MGPCR4_AULB_MASK) +/*! @} */ + +/*! @name MGPCR5 - Master General Purpose Control Register */ +/*! @{ */ + +#define AXBS_MGPCR5_AULB_MASK (0x7U) +#define AXBS_MGPCR5_AULB_SHIFT (0U) +/*! AULB - Arbitrates On Undefined Length Bursts + * 0b000..No arbitration is allowed during an undefined length burst. + * 0b001..Arbitration is allowed at any time during an undefined length burst. + * 0b010..Arbitration is allowed after four beats of an undefined length burst. + * 0b011..Arbitration is allowed after eight beats of an undefined length burst. + * 0b100..Arbitration is allowed after 16 beats of an undefined length burst. + * 0b101..Reserved + * 0b110..Reserved + * 0b111..Reserved + */ +#define AXBS_MGPCR5_AULB(x) (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR5_AULB_SHIFT)) & AXBS_MGPCR5_AULB_MASK) +/*! @} */ + +/*! @name MGPCR6 - Master General Purpose Control Register */ +/*! @{ */ + +#define AXBS_MGPCR6_AULB_MASK (0x7U) +#define AXBS_MGPCR6_AULB_SHIFT (0U) +/*! AULB - Arbitrates On Undefined Length Bursts + * 0b000..No arbitration is allowed during an undefined length burst. + * 0b001..Arbitration is allowed at any time during an undefined length burst. + * 0b010..Arbitration is allowed after four beats of an undefined length burst. + * 0b011..Arbitration is allowed after eight beats of an undefined length burst. + * 0b100..Arbitration is allowed after 16 beats of an undefined length burst. + * 0b101..Reserved + * 0b110..Reserved + * 0b111..Reserved + */ +#define AXBS_MGPCR6_AULB(x) (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR6_AULB_SHIFT)) & AXBS_MGPCR6_AULB_MASK) +/*! @} */ + +/*! @name MGPCR7 - Master General Purpose Control Register */ +/*! @{ */ + +#define AXBS_MGPCR7_AULB_MASK (0x7U) +#define AXBS_MGPCR7_AULB_SHIFT (0U) +/*! AULB - Arbitrates On Undefined Length Bursts + * 0b000..No arbitration is allowed during an undefined length burst. + * 0b001..Arbitration is allowed at any time during an undefined length burst. + * 0b010..Arbitration is allowed after four beats of an undefined length burst. + * 0b011..Arbitration is allowed after eight beats of an undefined length burst. + * 0b100..Arbitration is allowed after 16 beats of an undefined length burst. + * 0b101..Reserved + * 0b110..Reserved + * 0b111..Reserved + */ +#define AXBS_MGPCR7_AULB(x) (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR7_AULB_SHIFT)) & AXBS_MGPCR7_AULB_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group AXBS_Register_Masks */ + + +/* AXBS - Peripheral instance base addresses */ +/** Peripheral AXBS base address */ +#define AXBS_BASE (0x44510000u) +/** Peripheral AXBS base pointer */ +#define AXBS ((AXBS_Type *)AXBS_BASE) +/** Array initializer of AXBS peripheral base addresses */ +#define AXBS_BASE_ADDRS { AXBS_BASE } +/** Array initializer of AXBS peripheral base pointers */ +#define AXBS_BASE_PTRS { AXBS } + +/*! + * @} + */ /* end of group AXBS_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- BBNSM Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup BBNSM_Peripheral_Access_Layer BBNSM Peripheral Access Layer + * @{ + */ + +/** BBNSM - Register Layout Typedef */ +typedef struct { + __I uint32_t BBNSM_VID; /**< BBNSM Version ID Register, offset: 0x0 */ + __I uint32_t BBNSM_FEATURES; /**< BBNSM Features Register, offset: 0x4 */ + __IO uint32_t BBNSM_CTRL; /**< BBNSM Control Register, offset: 0x8 */ + uint8_t RESERVED_0[4]; + __IO uint32_t BBNSM_INT_EN; /**< BBNSM Interrupt Enable Register, offset: 0x10 */ + __IO uint32_t BBNSM_EVENTS; /**< BBNSM Events Register, offset: 0x14 */ + uint8_t RESERVED_1[12]; + __IO uint32_t BBNSM_PAD_CTRL; /**< BBNSM External Pad Control Register, offset: 0x24 */ + uint8_t RESERVED_2[24]; + __IO uint32_t BBNSM_RTC_LS; /**< BBNSM Real-Time Counter LS Register, offset: 0x40 */ + __IO uint32_t BBNSM_RTC_MS; /**< BBNSM Real-Time Counter MS Register, offset: 0x44 */ + uint8_t RESERVED_3[8]; + __IO uint32_t BBNSM_TA; /**< BBNSM Time Alarm Register, offset: 0x50 */ + uint8_t RESERVED_4[684]; + __IO uint32_t GPR[8]; /**< General Purpose Register Word 0..General Purpose Register Word 7, array offset: 0x300, array step: 0x4 */ +} BBNSM_Type; + +/* ---------------------------------------------------------------------------- + -- BBNSM Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup BBNSM_Register_Masks BBNSM Register Masks + * @{ + */ + +/*! @name BBNSM_VID - BBNSM Version ID Register */ +/*! @{ */ + +#define BBNSM_BBNSM_VID_BBNSM_IPID_MASK (0xFFU) +#define BBNSM_BBNSM_VID_BBNSM_IPID_SHIFT (0U) +/*! BBNSM_IPID - BBNSM IP ID */ +#define BBNSM_BBNSM_VID_BBNSM_IPID(x) (((uint32_t)(((uint32_t)(x)) << BBNSM_BBNSM_VID_BBNSM_IPID_SHIFT)) & BBNSM_BBNSM_VID_BBNSM_IPID_MASK) + +#define BBNSM_BBNSM_VID_BBNSM_REV_MASK (0xFF00U) +#define BBNSM_BBNSM_VID_BBNSM_REV_SHIFT (8U) +/*! BBNSM_REV - BBNSM Revision */ +#define BBNSM_BBNSM_VID_BBNSM_REV(x) (((uint32_t)(((uint32_t)(x)) << BBNSM_BBNSM_VID_BBNSM_REV_SHIFT)) & BBNSM_BBNSM_VID_BBNSM_REV_MASK) + +#define BBNSM_BBNSM_VID_BBNSM_VID_MASK (0xFF0000U) +#define BBNSM_BBNSM_VID_BBNSM_VID_SHIFT (16U) +/*! BBNSM_VID - BBNSM Version ID */ +#define BBNSM_BBNSM_VID_BBNSM_VID(x) (((uint32_t)(((uint32_t)(x)) << BBNSM_BBNSM_VID_BBNSM_VID_SHIFT)) & BBNSM_BBNSM_VID_BBNSM_VID_MASK) +/*! @} */ + +/*! @name BBNSM_FEATURES - BBNSM Features Register */ +/*! @{ */ + +#define BBNSM_BBNSM_FEATURES_GPR_SZ_MASK (0xFCU) +#define BBNSM_BBNSM_FEATURES_GPR_SZ_SHIFT (2U) +/*! GPR_SZ - GPR Register Array Size + * 0b000000..This version of BBNSM does not implement a general-purpose register array. + * *..The number of 32-bit words implemented in the general-purpose register array. + */ +#define BBNSM_BBNSM_FEATURES_GPR_SZ(x) (((uint32_t)(((uint32_t)(x)) << BBNSM_BBNSM_FEATURES_GPR_SZ_SHIFT)) & BBNSM_BBNSM_FEATURES_GPR_SZ_MASK) +/*! @} */ + +/*! @name BBNSM_CTRL - BBNSM Control Register */ +/*! @{ */ + +#define BBNSM_BBNSM_CTRL_RTC_EN_MASK (0x3U) +#define BBNSM_BBNSM_CTRL_RTC_EN_SHIFT (0U) +/*! RTC_EN - Real-Time Counter Enable + * 0b01..Disable the real-time counter. + * 0b10..Enable the real-time counter. + */ +#define BBNSM_BBNSM_CTRL_RTC_EN(x) (((uint32_t)(((uint32_t)(x)) << BBNSM_BBNSM_CTRL_RTC_EN_SHIFT)) & BBNSM_BBNSM_CTRL_RTC_EN_MASK) + +#define BBNSM_BBNSM_CTRL_TA_EN_MASK (0xCU) +#define BBNSM_BBNSM_CTRL_TA_EN_SHIFT (2U) +/*! TA_EN - Time Alarm Enable + * 0b01..Disable the time alarm. + * 0b10..Enable the time alarm. A time alarm event occurs if the value in the real-time counter register is equal + * to the value in the time alarm register. + */ +#define BBNSM_BBNSM_CTRL_TA_EN(x) (((uint32_t)(((uint32_t)(x)) << BBNSM_BBNSM_CTRL_TA_EN_SHIFT)) & BBNSM_BBNSM_CTRL_TA_EN_MASK) + +#define BBNSM_BBNSM_CTRL_CAL_EN_MASK (0x10U) +#define BBNSM_BBNSM_CTRL_CAL_EN_SHIFT (4U) +/*! CAL_EN - Calibration Enable + * 0b0..RTC Time calibration is disabled. + * 0b1..RTC Time calibration is enabled. + */ +#define BBNSM_BBNSM_CTRL_CAL_EN(x) (((uint32_t)(((uint32_t)(x)) << BBNSM_BBNSM_CTRL_CAL_EN_SHIFT)) & BBNSM_BBNSM_CTRL_CAL_EN_MASK) + +#define BBNSM_BBNSM_CTRL_CAL_VAL_MASK (0x1F00U) +#define BBNSM_BBNSM_CTRL_CAL_VAL_SHIFT (8U) +/*! CAL_VAL - Calibration Value + * 0b00000..+0 counts per each 32768 ticks of the counter clock. + * 0b00001..+1 counts per each 32768 ticks of the counter clock. + * 0b00010..+2 counts per each 32768 ticks of the counter clock. + * 0b01111..+15 counts per each 32768 ticks of the counter clock. + * 0b10000..-16 counts per each 32768 ticks of the counter clock. + * 0b10001..-15 counts per each 32768 ticks of the counter clock. + * 0b11110..-2 counts per each 32768 ticks of the counter clock. + * 0b11111..-1 counts per each 32768 ticks of the counter clock. + */ +#define BBNSM_BBNSM_CTRL_CAL_VAL(x) (((uint32_t)(((uint32_t)(x)) << BBNSM_BBNSM_CTRL_CAL_VAL_SHIFT)) & BBNSM_BBNSM_CTRL_CAL_VAL_MASK) + +#define BBNSM_BBNSM_CTRL_BTN_TIMEOUT_MASK (0x30000U) +#define BBNSM_BBNSM_CTRL_BTN_TIMEOUT_SHIFT (16U) +/*! BTN_TIMEOUT - Button Press Timeout + * 0b00..5 seconds. + * 0b01..10 seconds. + * 0b10..15 seconds. + * 0b11..Timeout disabled. Long button presses will not request a power down. + */ +#define BBNSM_BBNSM_CTRL_BTN_TIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << BBNSM_BBNSM_CTRL_BTN_TIMEOUT_SHIFT)) & BBNSM_BBNSM_CTRL_BTN_TIMEOUT_MASK) + +#define BBNSM_BBNSM_CTRL_DEBOUNCE_MASK (0xC0000U) +#define BBNSM_BBNSM_CTRL_DEBOUNCE_SHIFT (18U) +/*! DEBOUNCE - Debounce Time + * 0b00..50 milliseconds. + * 0b01..100 milliseconds. + * 0b10..500 milliseconds. + * 0b11..0 milliseconds. + */ +#define BBNSM_BBNSM_CTRL_DEBOUNCE(x) (((uint32_t)(((uint32_t)(x)) << BBNSM_BBNSM_CTRL_DEBOUNCE_SHIFT)) & BBNSM_BBNSM_CTRL_DEBOUNCE_MASK) + +#define BBNSM_BBNSM_CTRL_TURN_ON_TIME_MASK (0x300000U) +#define BBNSM_BBNSM_CTRL_TURN_ON_TIME_SHIFT (20U) +/*! TURN_ON_TIME - Turn-On Time + * 0b00..500 milliseconds. + * 0b01..50 milliseconds. + * 0b10..100 milliseconds. + * 0b11..0 milliseconds. + */ +#define BBNSM_BBNSM_CTRL_TURN_ON_TIME(x) (((uint32_t)(((uint32_t)(x)) << BBNSM_BBNSM_CTRL_TURN_ON_TIME_SHIFT)) & BBNSM_BBNSM_CTRL_TURN_ON_TIME_MASK) + +#define BBNSM_BBNSM_CTRL_PK_EN_MASK (0x400000U) +#define BBNSM_BBNSM_CTRL_PK_EN_SHIFT (22U) +/*! PK_EN - PMIC On Request Enable + * 0b0..PMIC On Request is disabled. + * 0b1..PMIC On Request is enabled. + */ +#define BBNSM_BBNSM_CTRL_PK_EN(x) (((uint32_t)(((uint32_t)(x)) << BBNSM_BBNSM_CTRL_PK_EN_SHIFT)) & BBNSM_BBNSM_CTRL_PK_EN_MASK) + +#define BBNSM_BBNSM_CTRL_PK_OVR_MASK (0x800000U) +#define BBNSM_BBNSM_CTRL_PK_OVR_SHIFT (23U) +/*! PK_OVR - PMIC On Request Override + * 0b0..PMIC On Request Override is disabled. + * 0b1..PMIC On Request Override is enabled. + */ +#define BBNSM_BBNSM_CTRL_PK_OVR(x) (((uint32_t)(((uint32_t)(x)) << BBNSM_BBNSM_CTRL_PK_OVR_SHIFT)) & BBNSM_BBNSM_CTRL_PK_OVR_MASK) + +#define BBNSM_BBNSM_CTRL_DP_EN_MASK (0x1000000U) +#define BBNSM_BBNSM_CTRL_DP_EN_SHIFT (24U) +/*! DP_EN - Dumb PMIC Enable + * 0b0..Smart PMIC is enabled. + * 0b1..Dumb PMIC is enabled. + */ +#define BBNSM_BBNSM_CTRL_DP_EN(x) (((uint32_t)(((uint32_t)(x)) << BBNSM_BBNSM_CTRL_DP_EN_SHIFT)) & BBNSM_BBNSM_CTRL_DP_EN_MASK) + +#define BBNSM_BBNSM_CTRL_TOSP_MASK (0x2000000U) +#define BBNSM_BBNSM_CTRL_TOSP_SHIFT (25U) +/*! TOSP - Turn Off System Power + * 0b0..Leave system power on. + * 0b1..Turn off system power when Dumb PMIC is enabled. + */ +#define BBNSM_BBNSM_CTRL_TOSP(x) (((uint32_t)(((uint32_t)(x)) << BBNSM_BBNSM_CTRL_TOSP_SHIFT)) & BBNSM_BBNSM_CTRL_TOSP_MASK) +/*! @} */ + +/*! @name BBNSM_INT_EN - BBNSM Interrupt Enable Register */ +/*! @{ */ + +#define BBNSM_BBNSM_INT_EN_RTC_INT_EN_MASK (0x3U) +#define BBNSM_BBNSM_INT_EN_RTC_INT_EN_SHIFT (0U) +/*! RTC_INT_EN - Real-Time Counter Rollover Interrupt Enable + * 0b01..Do not issue an interrupt when RTC has rolled over. The interrupt is cleared when this value is written. + * 0b10..Issue an interrupt when RTC has rolled over. + */ +#define BBNSM_BBNSM_INT_EN_RTC_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << BBNSM_BBNSM_INT_EN_RTC_INT_EN_SHIFT)) & BBNSM_BBNSM_INT_EN_RTC_INT_EN_MASK) + +#define BBNSM_BBNSM_INT_EN_TA_INT_EN_MASK (0xCU) +#define BBNSM_BBNSM_INT_EN_TA_INT_EN_SHIFT (2U) +/*! TA_INT_EN - Time Alarm Interrupt Enable + * 0b01..Do not issue an interrupt when RTC has reached alarm time. The interrupt is cleared when this value is written. + * 0b10..Issue an interrupt when RTC has reached alarm time. + */ +#define BBNSM_BBNSM_INT_EN_TA_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << BBNSM_BBNSM_INT_EN_TA_INT_EN_SHIFT)) & BBNSM_BBNSM_INT_EN_TA_INT_EN_MASK) +/*! @} */ + +/*! @name BBNSM_EVENTS - BBNSM Events Register */ +/*! @{ */ + +#define BBNSM_BBNSM_EVENTS_RTC_ROLL_MASK (0x3U) +#define BBNSM_BBNSM_EVENTS_RTC_ROLL_SHIFT (0U) +/*! RTC_ROLL - Real-Time Counter Rollover Event + * 0b01..The real-time counter has not rolled over. + * 0b10..The real-time counter has rolled over. + */ +#define BBNSM_BBNSM_EVENTS_RTC_ROLL(x) (((uint32_t)(((uint32_t)(x)) << BBNSM_BBNSM_EVENTS_RTC_ROLL_SHIFT)) & BBNSM_BBNSM_EVENTS_RTC_ROLL_MASK) + +#define BBNSM_BBNSM_EVENTS_TA_MASK (0xCU) +#define BBNSM_BBNSM_EVENTS_TA_SHIFT (2U) +/*! TA - Time Alarm Event + * 0b01..The real-time counter has not reached the alarm time. + * 0b10..The real-time counter has reached the alarm time. + */ +#define BBNSM_BBNSM_EVENTS_TA(x) (((uint32_t)(((uint32_t)(x)) << BBNSM_BBNSM_EVENTS_TA_SHIFT)) & BBNSM_BBNSM_EVENTS_TA_MASK) + +#define BBNSM_BBNSM_EVENTS_EMG_OFF_MASK (0x10U) +#define BBNSM_BBNSM_EVENTS_EMG_OFF_SHIFT (4U) +/*! EMG_OFF - Emergency Off Event + * 0b0..An emergency power off has not been requested. + * 0b1..An emergency power off has been requested. + */ +#define BBNSM_BBNSM_EVENTS_EMG_OFF(x) (((uint32_t)(((uint32_t)(x)) << BBNSM_BBNSM_EVENTS_EMG_OFF_SHIFT)) & BBNSM_BBNSM_EVENTS_EMG_OFF_MASK) + +#define BBNSM_BBNSM_EVENTS_PWR_OFF_MASK (0x20U) +#define BBNSM_BBNSM_EVENTS_PWR_OFF_SHIFT (5U) +/*! PWR_OFF - Set Power Off Event + * 0b0..The power off interrupt has not been requested. + * 0b1..The power off interrupt has been requested. + */ +#define BBNSM_BBNSM_EVENTS_PWR_OFF(x) (((uint32_t)(((uint32_t)(x)) << BBNSM_BBNSM_EVENTS_PWR_OFF_SHIFT)) & BBNSM_BBNSM_EVENTS_PWR_OFF_MASK) + +#define BBNSM_BBNSM_EVENTS_PWR_ON_MASK (0x40U) +#define BBNSM_BBNSM_EVENTS_PWR_ON_SHIFT (6U) +/*! PWR_ON - Set Power On Event + * 0b0..The power on interrupt has not been requested. + * 0b1..The power on interrupt has been requested. + */ +#define BBNSM_BBNSM_EVENTS_PWR_ON(x) (((uint32_t)(((uint32_t)(x)) << BBNSM_BBNSM_EVENTS_PWR_ON_SHIFT)) & BBNSM_BBNSM_EVENTS_PWR_ON_MASK) +/*! @} */ + +/*! @name BBNSM_PAD_CTRL - BBNSM External Pad Control Register */ +/*! @{ */ + +#define BBNSM_BBNSM_PAD_CTRL_PAD_CTRL0_MASK (0x1U) +#define BBNSM_BBNSM_PAD_CTRL_PAD_CTRL0_SHIFT (0U) +/*! PAD_CTRL0 - Control I/O Pads + * 0b0..Deasserts bit n in bbnsm_pad_ctrl[n] + * 0b1..Assert bit n in bbnsm_pad_ctrl[n] + */ +#define BBNSM_BBNSM_PAD_CTRL_PAD_CTRL0(x) (((uint32_t)(((uint32_t)(x)) << BBNSM_BBNSM_PAD_CTRL_PAD_CTRL0_SHIFT)) & BBNSM_BBNSM_PAD_CTRL_PAD_CTRL0_MASK) + +#define BBNSM_BBNSM_PAD_CTRL_PAD_CTRL1_MASK (0x2U) +#define BBNSM_BBNSM_PAD_CTRL_PAD_CTRL1_SHIFT (1U) +/*! PAD_CTRL1 - Control I/O Pads + * 0b0..Deasserts bit n in bbnsm_pad_ctrl[n] + * 0b1..Assert bit n in bbnsm_pad_ctrl[n] + */ +#define BBNSM_BBNSM_PAD_CTRL_PAD_CTRL1(x) (((uint32_t)(((uint32_t)(x)) << BBNSM_BBNSM_PAD_CTRL_PAD_CTRL1_SHIFT)) & BBNSM_BBNSM_PAD_CTRL_PAD_CTRL1_MASK) + +#define BBNSM_BBNSM_PAD_CTRL_PAD_CTRL2_MASK (0x4U) +#define BBNSM_BBNSM_PAD_CTRL_PAD_CTRL2_SHIFT (2U) +/*! PAD_CTRL2 - Control I/O Pads + * 0b0..Deasserts bit n in bbnsm_pad_ctrl[n] + * 0b1..Assert bit n in bbnsm_pad_ctrl[n] + */ +#define BBNSM_BBNSM_PAD_CTRL_PAD_CTRL2(x) (((uint32_t)(((uint32_t)(x)) << BBNSM_BBNSM_PAD_CTRL_PAD_CTRL2_SHIFT)) & BBNSM_BBNSM_PAD_CTRL_PAD_CTRL2_MASK) + +#define BBNSM_BBNSM_PAD_CTRL_PAD_CTRL3_MASK (0x8U) +#define BBNSM_BBNSM_PAD_CTRL_PAD_CTRL3_SHIFT (3U) +/*! PAD_CTRL3 - Control I/O Pads + * 0b0..Deasserts bit n in bbnsm_pad_ctrl[n] + * 0b1..Assert bit n in bbnsm_pad_ctrl[n] + */ +#define BBNSM_BBNSM_PAD_CTRL_PAD_CTRL3(x) (((uint32_t)(((uint32_t)(x)) << BBNSM_BBNSM_PAD_CTRL_PAD_CTRL3_SHIFT)) & BBNSM_BBNSM_PAD_CTRL_PAD_CTRL3_MASK) + +#define BBNSM_BBNSM_PAD_CTRL_PAD_CTRL4_MASK (0x10U) +#define BBNSM_BBNSM_PAD_CTRL_PAD_CTRL4_SHIFT (4U) +/*! PAD_CTRL4 - Control I/O Pads + * 0b0..Deasserts bit n in bbnsm_pad_ctrl[n] + * 0b1..Assert bit n in bbnsm_pad_ctrl[n] + */ +#define BBNSM_BBNSM_PAD_CTRL_PAD_CTRL4(x) (((uint32_t)(((uint32_t)(x)) << BBNSM_BBNSM_PAD_CTRL_PAD_CTRL4_SHIFT)) & BBNSM_BBNSM_PAD_CTRL_PAD_CTRL4_MASK) + +#define BBNSM_BBNSM_PAD_CTRL_PAD_CTRL5_MASK (0x20U) +#define BBNSM_BBNSM_PAD_CTRL_PAD_CTRL5_SHIFT (5U) +/*! PAD_CTRL5 - Control I/O Pads + * 0b0..Deasserts bit n in bbnsm_pad_ctrl[n] + * 0b1..Assert bit n in bbnsm_pad_ctrl[n] + */ +#define BBNSM_BBNSM_PAD_CTRL_PAD_CTRL5(x) (((uint32_t)(((uint32_t)(x)) << BBNSM_BBNSM_PAD_CTRL_PAD_CTRL5_SHIFT)) & BBNSM_BBNSM_PAD_CTRL_PAD_CTRL5_MASK) + +#define BBNSM_BBNSM_PAD_CTRL_PAD_CTRL6_MASK (0x40U) +#define BBNSM_BBNSM_PAD_CTRL_PAD_CTRL6_SHIFT (6U) +/*! PAD_CTRL6 - Control I/O Pads + * 0b0..Deasserts bit n in bbnsm_pad_ctrl[n] + * 0b1..Assert bit n in bbnsm_pad_ctrl[n] + */ +#define BBNSM_BBNSM_PAD_CTRL_PAD_CTRL6(x) (((uint32_t)(((uint32_t)(x)) << BBNSM_BBNSM_PAD_CTRL_PAD_CTRL6_SHIFT)) & BBNSM_BBNSM_PAD_CTRL_PAD_CTRL6_MASK) + +#define BBNSM_BBNSM_PAD_CTRL_PAD_CTRL7_MASK (0x80U) +#define BBNSM_BBNSM_PAD_CTRL_PAD_CTRL7_SHIFT (7U) +/*! PAD_CTRL7 - Control I/O Pads + * 0b0..Deasserts bit n in bbnsm_pad_ctrl[n] + * 0b1..Assert bit n in bbnsm_pad_ctrl[n] + */ +#define BBNSM_BBNSM_PAD_CTRL_PAD_CTRL7(x) (((uint32_t)(((uint32_t)(x)) << BBNSM_BBNSM_PAD_CTRL_PAD_CTRL7_SHIFT)) & BBNSM_BBNSM_PAD_CTRL_PAD_CTRL7_MASK) + +#define BBNSM_BBNSM_PAD_CTRL_PAD_CTRL8_MASK (0x100U) +#define BBNSM_BBNSM_PAD_CTRL_PAD_CTRL8_SHIFT (8U) +/*! PAD_CTRL8 - Control I/O Pads + * 0b0..Deasserts bit n in bbnsm_pad_ctrl[n] + * 0b1..Assert bit n in bbnsm_pad_ctrl[n] + */ +#define BBNSM_BBNSM_PAD_CTRL_PAD_CTRL8(x) (((uint32_t)(((uint32_t)(x)) << BBNSM_BBNSM_PAD_CTRL_PAD_CTRL8_SHIFT)) & BBNSM_BBNSM_PAD_CTRL_PAD_CTRL8_MASK) + +#define BBNSM_BBNSM_PAD_CTRL_PAD_CTRL9_MASK (0x200U) +#define BBNSM_BBNSM_PAD_CTRL_PAD_CTRL9_SHIFT (9U) +/*! PAD_CTRL9 - Control I/O Pads + * 0b0..Deasserts bit n in bbnsm_pad_ctrl[n] + * 0b1..Assert bit n in bbnsm_pad_ctrl[n] + */ +#define BBNSM_BBNSM_PAD_CTRL_PAD_CTRL9(x) (((uint32_t)(((uint32_t)(x)) << BBNSM_BBNSM_PAD_CTRL_PAD_CTRL9_SHIFT)) & BBNSM_BBNSM_PAD_CTRL_PAD_CTRL9_MASK) + +#define BBNSM_BBNSM_PAD_CTRL_PAD_CTRL10_MASK (0x400U) +#define BBNSM_BBNSM_PAD_CTRL_PAD_CTRL10_SHIFT (10U) +/*! PAD_CTRL10 - Control I/O Pads + * 0b0..Deasserts bit n in bbnsm_pad_ctrl[n] + * 0b1..Assert bit n in bbnsm_pad_ctrl[n] + */ +#define BBNSM_BBNSM_PAD_CTRL_PAD_CTRL10(x) (((uint32_t)(((uint32_t)(x)) << BBNSM_BBNSM_PAD_CTRL_PAD_CTRL10_SHIFT)) & BBNSM_BBNSM_PAD_CTRL_PAD_CTRL10_MASK) + +#define BBNSM_BBNSM_PAD_CTRL_PAD_CTRL11_MASK (0x800U) +#define BBNSM_BBNSM_PAD_CTRL_PAD_CTRL11_SHIFT (11U) +/*! PAD_CTRL11 - Control I/O Pads + * 0b0..Deasserts bit n in bbnsm_pad_ctrl[n] + * 0b1..Assert bit n in bbnsm_pad_ctrl[n] + */ +#define BBNSM_BBNSM_PAD_CTRL_PAD_CTRL11(x) (((uint32_t)(((uint32_t)(x)) << BBNSM_BBNSM_PAD_CTRL_PAD_CTRL11_SHIFT)) & BBNSM_BBNSM_PAD_CTRL_PAD_CTRL11_MASK) + +#define BBNSM_BBNSM_PAD_CTRL_PAD_CTRL12_MASK (0x1000U) +#define BBNSM_BBNSM_PAD_CTRL_PAD_CTRL12_SHIFT (12U) +/*! PAD_CTRL12 - Control I/O Pads + * 0b0..Deasserts bit n in bbnsm_pad_ctrl[n] + * 0b1..Assert bit n in bbnsm_pad_ctrl[n] + */ +#define BBNSM_BBNSM_PAD_CTRL_PAD_CTRL12(x) (((uint32_t)(((uint32_t)(x)) << BBNSM_BBNSM_PAD_CTRL_PAD_CTRL12_SHIFT)) & BBNSM_BBNSM_PAD_CTRL_PAD_CTRL12_MASK) + +#define BBNSM_BBNSM_PAD_CTRL_PAD_CTRL13_MASK (0x2000U) +#define BBNSM_BBNSM_PAD_CTRL_PAD_CTRL13_SHIFT (13U) +/*! PAD_CTRL13 - Control I/O Pads + * 0b0..Deasserts bit n in bbnsm_pad_ctrl[n] + * 0b1..Assert bit n in bbnsm_pad_ctrl[n] + */ +#define BBNSM_BBNSM_PAD_CTRL_PAD_CTRL13(x) (((uint32_t)(((uint32_t)(x)) << BBNSM_BBNSM_PAD_CTRL_PAD_CTRL13_SHIFT)) & BBNSM_BBNSM_PAD_CTRL_PAD_CTRL13_MASK) + +#define BBNSM_BBNSM_PAD_CTRL_PAD_CTRL14_MASK (0x4000U) +#define BBNSM_BBNSM_PAD_CTRL_PAD_CTRL14_SHIFT (14U) +/*! PAD_CTRL14 - Control I/O Pads + * 0b0..Deasserts bit n in bbnsm_pad_ctrl[n] + * 0b1..Assert bit n in bbnsm_pad_ctrl[n] + */ +#define BBNSM_BBNSM_PAD_CTRL_PAD_CTRL14(x) (((uint32_t)(((uint32_t)(x)) << BBNSM_BBNSM_PAD_CTRL_PAD_CTRL14_SHIFT)) & BBNSM_BBNSM_PAD_CTRL_PAD_CTRL14_MASK) + +#define BBNSM_BBNSM_PAD_CTRL_PAD_CTRL15_MASK (0x8000U) +#define BBNSM_BBNSM_PAD_CTRL_PAD_CTRL15_SHIFT (15U) +/*! PAD_CTRL15 - Control I/O Pads + * 0b0..Deasserts bit n in bbnsm_pad_ctrl[n] + * 0b1..Assert bit n in bbnsm_pad_ctrl[n] + */ +#define BBNSM_BBNSM_PAD_CTRL_PAD_CTRL15(x) (((uint32_t)(((uint32_t)(x)) << BBNSM_BBNSM_PAD_CTRL_PAD_CTRL15_SHIFT)) & BBNSM_BBNSM_PAD_CTRL_PAD_CTRL15_MASK) +/*! @} */ + +/*! @name BBNSM_RTC_LS - BBNSM Real-Time Counter LS Register */ +/*! @{ */ + +#define BBNSM_BBNSM_RTC_LS_RTC_MASK (0xFFFFFFFFU) +#define BBNSM_BBNSM_RTC_LS_RTC_SHIFT (0U) +/*! RTC - Real-time Counter */ +#define BBNSM_BBNSM_RTC_LS_RTC(x) (((uint32_t)(((uint32_t)(x)) << BBNSM_BBNSM_RTC_LS_RTC_SHIFT)) & BBNSM_BBNSM_RTC_LS_RTC_MASK) +/*! @} */ + +/*! @name BBNSM_RTC_MS - BBNSM Real-Time Counter MS Register */ +/*! @{ */ + +#define BBNSM_BBNSM_RTC_MS_RTC_MASK (0x7FFFU) +#define BBNSM_BBNSM_RTC_MS_RTC_SHIFT (0U) +/*! RTC - Real-Time Counter */ +#define BBNSM_BBNSM_RTC_MS_RTC(x) (((uint32_t)(((uint32_t)(x)) << BBNSM_BBNSM_RTC_MS_RTC_SHIFT)) & BBNSM_BBNSM_RTC_MS_RTC_MASK) +/*! @} */ + +/*! @name BBNSM_TA - BBNSM Time Alarm Register */ +/*! @{ */ + +#define BBNSM_BBNSM_TA_TA_MASK (0xFFFFFFFFU) +#define BBNSM_BBNSM_TA_TA_SHIFT (0U) +/*! TA - Time Alarm Value */ +#define BBNSM_BBNSM_TA_TA(x) (((uint32_t)(((uint32_t)(x)) << BBNSM_BBNSM_TA_TA_SHIFT)) & BBNSM_BBNSM_TA_TA_MASK) +/*! @} */ + +/*! @name GPR - General Purpose Register Word 0..General Purpose Register Word 7 */ +/*! @{ */ + +#define BBNSM_GPR_GPR_MASK (0xFFFFFFFFU) +#define BBNSM_GPR_GPR_SHIFT (0U) +/*! GPR - 32 bits of the GPR. */ +#define BBNSM_GPR_GPR(x) (((uint32_t)(((uint32_t)(x)) << BBNSM_GPR_GPR_SHIFT)) & BBNSM_GPR_GPR_MASK) +/*! @} */ + +/* The count of BBNSM_GPR */ +#define BBNSM_GPR_COUNT (8U) + + +/*! + * @} + */ /* end of group BBNSM_Register_Masks */ + + +/* BBNSM - Peripheral instance base addresses */ +/** Peripheral BBNSM base address */ +#define BBNSM_BASE (0x44440000u) +/** Peripheral BBNSM base pointer */ +#define BBNSM ((BBNSM_Type *)BBNSM_BASE) +/** Array initializer of BBNSM peripheral base addresses */ +#define BBNSM_BASE_ADDRS { BBNSM_BASE } +/** Array initializer of BBNSM peripheral base pointers */ +#define BBNSM_BASE_PTRS { BBNSM } + +/*! + * @} + */ /* end of group BBNSM_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- BLK_CTRL_DDRMIX Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup BLK_CTRL_DDRMIX_Peripheral_Access_Layer BLK_CTRL_DDRMIX Peripheral Access Layer + * @{ + */ + +/** BLK_CTRL_DDRMIX - Register Layout Typedef */ +typedef struct { + __IO uint32_t HWFFC_CTRL; /**< DDRPHY DfiClk, DflCtlClk HWFFC Control, offset: 0x0 */ + __IO uint32_t CA55_SEL_CTRL; /**< CA55 Arm PLL, Anamix PLL Observe Select, offset: 0x4 */ + __IO uint32_t VREF_PSW_CTRL; /**< DRAM_VREF power switch, offset: 0x8 */ + __IO uint32_t DDRC_STOP_CTRL; /**< DDR Controller ipg_stop SW control, offset: 0xC */ + __IO uint32_t AUTO_CG_CTRL; /**< DDR Controller automatic clock gating, offset: 0x10 */ + __IO uint32_t SSI_LP_CTRL; /**< DDRMIX SSI Slave low power signal control, offset: 0x14 */ +} BLK_CTRL_DDRMIX_Type; + +/* ---------------------------------------------------------------------------- + -- BLK_CTRL_DDRMIX Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup BLK_CTRL_DDRMIX_Register_Masks BLK_CTRL_DDRMIX Register Masks + * @{ + */ + +/*! @name HWFFC_CTRL - DDRPHY DfiClk, DflCtlClk HWFFC Control */ +/*! @{ */ + +#define BLK_CTRL_DDRMIX_HWFFC_CTRL_HWFFC_EN_MASK (0x1U) +#define BLK_CTRL_DDRMIX_HWFFC_CTRL_HWFFC_EN_SHIFT (0U) +/*! HWFFC_EN - DDRPHY DfiClk, DfiCtlClk HWFFC Enable + * 0b0..DDRPHY HWFFC is disabled + * 0b1..DDRPHY HWFFC is enabled + */ +#define BLK_CTRL_DDRMIX_HWFFC_CTRL_HWFFC_EN(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_DDRMIX_HWFFC_CTRL_HWFFC_EN_SHIFT)) & BLK_CTRL_DDRMIX_HWFFC_CTRL_HWFFC_EN_MASK) + +#define BLK_CTRL_DDRMIX_HWFFC_CTRL_HWFFC_SEL_MASK (0x2U) +#define BLK_CTRL_DDRMIX_HWFFC_CTRL_HWFFC_SEL_SHIFT (1U) +/*! HWFFC_SEL - DDRPHY DfiClk, DfiCtlClk HWFFC Select + * 0b0..Normal clock is selected + * 0b1..Div2 frequency clock is selected + */ +#define BLK_CTRL_DDRMIX_HWFFC_CTRL_HWFFC_SEL(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_DDRMIX_HWFFC_CTRL_HWFFC_SEL_SHIFT)) & BLK_CTRL_DDRMIX_HWFFC_CTRL_HWFFC_SEL_MASK) +/*! @} */ + +/*! @name CA55_SEL_CTRL - CA55 Arm PLL, Anamix PLL Observe Select */ +/*! @{ */ + +#define BLK_CTRL_DDRMIX_CA55_SEL_CTRL_CA55_SEL_MASK (0x3U) +#define BLK_CTRL_DDRMIX_CA55_SEL_CTRL_CA55_SEL_SHIFT (0U) +/*! CA55_SEL - CA55 Arm PLL/Anamix PLL output select into DDRPHY + * 0b00..Normal DfiClk from DRAM PLL is selected + * 0b01..Anamix PLL output is selected + * 0b10..Normal DfiClk from DRAM PLL is selected + * 0b11..CA55 mix Arm PLL is selected + */ +#define BLK_CTRL_DDRMIX_CA55_SEL_CTRL_CA55_SEL(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_DDRMIX_CA55_SEL_CTRL_CA55_SEL_SHIFT)) & BLK_CTRL_DDRMIX_CA55_SEL_CTRL_CA55_SEL_MASK) +/*! @} */ + +/*! @name VREF_PSW_CTRL - DRAM_VREF power switch */ +/*! @{ */ + +#define BLK_CTRL_DDRMIX_VREF_PSW_CTRL_VREF_PSW_MASK (0x1U) +#define BLK_CTRL_DDRMIX_VREF_PSW_CTRL_VREF_PSW_SHIFT (0U) +/*! VREF_PSW - DDRPHY DRAM_VREF Power Switch + * 0b0..Power switch is closed to prevent leakage + * 0b1..Power switch is opened and is set together with DDRPHY[VrefInGlobal] + */ +#define BLK_CTRL_DDRMIX_VREF_PSW_CTRL_VREF_PSW(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_DDRMIX_VREF_PSW_CTRL_VREF_PSW_SHIFT)) & BLK_CTRL_DDRMIX_VREF_PSW_CTRL_VREF_PSW_MASK) +/*! @} */ + +/*! @name DDRC_STOP_CTRL - DDR Controller ipg_stop SW control */ +/*! @{ */ + +#define BLK_CTRL_DDRMIX_DDRC_STOP_CTRL_DDRC_STOP_MASK (0x1U) +#define BLK_CTRL_DDRMIX_DDRC_STOP_CTRL_DDRC_STOP_SHIFT (0U) +/*! DDRC_STOP - DDR Controller ipg_stop + * 0b0..Clear DDR Controller ipg_stop signal + * 0b1..Set DDR Controller ipg_stop signal + */ +#define BLK_CTRL_DDRMIX_DDRC_STOP_CTRL_DDRC_STOP(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_DDRMIX_DDRC_STOP_CTRL_DDRC_STOP_SHIFT)) & BLK_CTRL_DDRMIX_DDRC_STOP_CTRL_DDRC_STOP_MASK) + +#define BLK_CTRL_DDRMIX_DDRC_STOP_CTRL_DDRC_STOP_ACK_MASK (0x2U) +#define BLK_CTRL_DDRMIX_DDRC_STOP_CTRL_DDRC_STOP_ACK_SHIFT (1U) +/*! DDRC_STOP_ACK - DDR Controller ipg_stop_ack + * 0b0..DDR Controller ipg_stop_ack is a 0 + * 0b1..DDR Controller ipg_stop_ack is a 1 + */ +#define BLK_CTRL_DDRMIX_DDRC_STOP_CTRL_DDRC_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_DDRMIX_DDRC_STOP_CTRL_DDRC_STOP_ACK_SHIFT)) & BLK_CTRL_DDRMIX_DDRC_STOP_CTRL_DDRC_STOP_ACK_MASK) +/*! @} */ + +/*! @name AUTO_CG_CTRL - DDR Controller automatic clock gating */ +/*! @{ */ + +#define BLK_CTRL_DDRMIX_AUTO_CG_CTRL_SSI_IDLE_STRAP_MASK (0xFFFFU) +#define BLK_CTRL_DDRMIX_AUTO_CG_CTRL_SSI_IDLE_STRAP_SHIFT (0U) +/*! SSI_IDLE_STRAP - SSI Idle Strap */ +#define BLK_CTRL_DDRMIX_AUTO_CG_CTRL_SSI_IDLE_STRAP(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_DDRMIX_AUTO_CG_CTRL_SSI_IDLE_STRAP_SHIFT)) & BLK_CTRL_DDRMIX_AUTO_CG_CTRL_SSI_IDLE_STRAP_MASK) + +#define BLK_CTRL_DDRMIX_AUTO_CG_CTRL_AUTO_CG_ENA_MASK (0x10000U) +#define BLK_CTRL_DDRMIX_AUTO_CG_CTRL_AUTO_CG_ENA_SHIFT (16U) +/*! AUTO_CG_ENA - DDR Controller automatic clock gating enable + * 0b0..DDR Controller automatic clock gating is disabled + * 0b1..DDR Controller automatic clock gating is enabled + */ +#define BLK_CTRL_DDRMIX_AUTO_CG_CTRL_AUTO_CG_ENA(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_DDRMIX_AUTO_CG_CTRL_AUTO_CG_ENA_SHIFT)) & BLK_CTRL_DDRMIX_AUTO_CG_CTRL_AUTO_CG_ENA_MASK) + +#define BLK_CTRL_DDRMIX_AUTO_CG_CTRL_HWFFC_ACG_FORCE_B_MASK (0x20000U) +#define BLK_CTRL_DDRMIX_AUTO_CG_CTRL_HWFFC_ACG_FORCE_B_SHIFT (17U) +/*! HWFFC_ACG_FORCE_B - DDR Controller hwffc and auto CG send ipg_stop allow + * 0b0..DDR Controller hwffc and auto CG cannot send ipg_stop + * 0b1..DDR Controller hwffc and auto CG can send ipg_stop + */ +#define BLK_CTRL_DDRMIX_AUTO_CG_CTRL_HWFFC_ACG_FORCE_B(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_DDRMIX_AUTO_CG_CTRL_HWFFC_ACG_FORCE_B_SHIFT)) & BLK_CTRL_DDRMIX_AUTO_CG_CTRL_HWFFC_ACG_FORCE_B_MASK) +/*! @} */ + +/*! @name SSI_LP_CTRL - DDRMIX SSI Slave low power signal control */ +/*! @{ */ + +#define BLK_CTRL_DDRMIX_SSI_LP_CTRL_SSI_ISO_CTRL_MASK (0x1U) +#define BLK_CTRL_DDRMIX_SSI_LP_CTRL_SSI_ISO_CTRL_SHIFT (0U) +/*! SSI_ISO_CTRL - DDRMIX SSI isolation mode control + * 0b0..in normal mode + * 0b1..enter pause mode + */ +#define BLK_CTRL_DDRMIX_SSI_LP_CTRL_SSI_ISO_CTRL(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_DDRMIX_SSI_LP_CTRL_SSI_ISO_CTRL_SHIFT)) & BLK_CTRL_DDRMIX_SSI_LP_CTRL_SSI_ISO_CTRL_MASK) + +#define BLK_CTRL_DDRMIX_SSI_LP_CTRL_SSI_POW_CTRL_MASK (0x2U) +#define BLK_CTRL_DDRMIX_SSI_LP_CTRL_SSI_POW_CTRL_SHIFT (1U) +/*! SSI_POW_CTRL - DDRMIX SSI power control + * 0b0..enter no power mode for SSI + * 0b1..power mode for SSI + */ +#define BLK_CTRL_DDRMIX_SSI_LP_CTRL_SSI_POW_CTRL(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_DDRMIX_SSI_LP_CTRL_SSI_POW_CTRL_SHIFT)) & BLK_CTRL_DDRMIX_SSI_LP_CTRL_SSI_POW_CTRL_MASK) + +#define BLK_CTRL_DDRMIX_SSI_LP_CTRL_SSI_IDLE_MASK (0x4U) +#define BLK_CTRL_DDRMIX_SSI_LP_CTRL_SSI_IDLE_SHIFT (2U) +/*! SSI_IDLE - DDRMIX SSI idle signal + * 0b0..means SSI is not idle + * 0b1..means SSI is idle + */ +#define BLK_CTRL_DDRMIX_SSI_LP_CTRL_SSI_IDLE(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_DDRMIX_SSI_LP_CTRL_SSI_IDLE_SHIFT)) & BLK_CTRL_DDRMIX_SSI_LP_CTRL_SSI_IDLE_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group BLK_CTRL_DDRMIX_Register_Masks */ + + +/* BLK_CTRL_DDRMIX - Peripheral instance base addresses */ +/** Peripheral BLK_CTRL_DDRMIX1 base address */ +#define BLK_CTRL_DDRMIX1_BASE (0x4E010000u) +/** Peripheral BLK_CTRL_DDRMIX1 base pointer */ +#define BLK_CTRL_DDRMIX1 ((BLK_CTRL_DDRMIX_Type *)BLK_CTRL_DDRMIX1_BASE) +/** Array initializer of BLK_CTRL_DDRMIX peripheral base addresses */ +#define BLK_CTRL_DDRMIX_BASE_ADDRS { BLK_CTRL_DDRMIX1_BASE } +/** Array initializer of BLK_CTRL_DDRMIX peripheral base pointers */ +#define BLK_CTRL_DDRMIX_BASE_PTRS { BLK_CTRL_DDRMIX1 } + +/*! + * @} + */ /* end of group BLK_CTRL_DDRMIX_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- BLK_CTRL_MEDIAMIX Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup BLK_CTRL_MEDIAMIX_Peripheral_Access_Layer BLK_CTRL_MEDIAMIX Peripheral Access Layer + * @{ + */ + +/** BLK_CTRL_MEDIAMIX - Register Layout Typedef */ +typedef struct { + union { /* offset: 0x0 */ + struct { /* offset: 0x0 */ + uint8_t RESERVED_0[12]; + __IO uint32_t LCDIFr; /**< QOS and cache of LCDIF, offset: 0xC, 'r' suffix has been added to avoid a clash with peripheral base pointer macro 'LCDIF' */ + uint8_t RESERVED_1[4]; + __IO uint32_t ISI0; /**< Cache of ISI, offset: 0x14 */ + uint8_t RESERVED_2[4]; + __IO uint32_t ISI1; /**< QoS of ISI, offset: 0x1C */ + uint8_t RESERVED_3[28]; + __I uint32_t PIXEL_CTRL; /**< Read Pixel Control Register, offset: 0x3C */ + uint8_t RESERVED_4[32]; + __IO uint32_t DISPLAY_MUX; /**< Display Mux Control Register, offset: 0x60 */ + uint8_t RESERVED_5[12]; + __IO uint32_t IF_CTRL_REG; /**< Parallel Camera Interface Register, offset: 0x70 */ + __I uint32_t INTERFACE_STATUS; /**< Interface Status Register, offset: 0x74 */ + __IO uint32_t INTERFACE_CTRL_REG; /**< Interface Control Register, offset: 0x78 */ + __IO uint32_t INTERFACE_CTRL_REG1; /**< Interface Control Register 1, offset: 0x7C */ + } BUS_CONTROL; + struct { /* offset: 0x0 */ + __IO uint32_t RESET; /**< RESET Control Register, offset: 0x0 */ + __IO uint32_t CLK; /**< CLK Control Register, offset: 0x4 */ + } CLK_RESETN; + }; +} BLK_CTRL_MEDIAMIX_Type; + +/* ---------------------------------------------------------------------------- + -- BLK_CTRL_MEDIAMIX Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup BLK_CTRL_MEDIAMIX_Register_Masks BLK_CTRL_MEDIAMIX Register Masks + * @{ + */ + +/*! @name LCDIF - QOS and cache of LCDIF */ +/*! @{ */ + +#define BLK_CTRL_MEDIAMIX_LCDIF_ARCACHE_MASK (0xFU) +#define BLK_CTRL_MEDIAMIX_LCDIF_ARCACHE_SHIFT (0U) +/*! ARCACHE - ARCACHE value of LCDIF */ +#define BLK_CTRL_MEDIAMIX_LCDIF_ARCACHE(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_MEDIAMIX_LCDIF_ARCACHE_SHIFT)) & BLK_CTRL_MEDIAMIX_LCDIF_ARCACHE_MASK) + +#define BLK_CTRL_MEDIAMIX_LCDIF_ARCACHE_EN_MASK (0x10U) +#define BLK_CTRL_MEDIAMIX_LCDIF_ARCACHE_EN_SHIFT (4U) +/*! ARCACHE_EN - ARCACHE enable of LCDIF + * 0b0..Do not enable ARCACHE + * 0b1..Enable ARCACHE + */ +#define BLK_CTRL_MEDIAMIX_LCDIF_ARCACHE_EN(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_MEDIAMIX_LCDIF_ARCACHE_EN_SHIFT)) & BLK_CTRL_MEDIAMIX_LCDIF_ARCACHE_EN_MASK) + +#define BLK_CTRL_MEDIAMIX_LCDIF_CFG_QOS_MASK (0xF00U) +#define BLK_CTRL_MEDIAMIX_LCDIF_CFG_QOS_SHIFT (8U) +/*! CFG_QOS - cfg_qos value of LCDIF */ +#define BLK_CTRL_MEDIAMIX_LCDIF_CFG_QOS(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_MEDIAMIX_LCDIF_CFG_QOS_SHIFT)) & BLK_CTRL_MEDIAMIX_LCDIF_CFG_QOS_MASK) + +#define BLK_CTRL_MEDIAMIX_LCDIF_DEFAULT_QOS_MASK (0xF000U) +#define BLK_CTRL_MEDIAMIX_LCDIF_DEFAULT_QOS_SHIFT (12U) +/*! DEFAULT_QOS - Default QoS value of LCDIF */ +#define BLK_CTRL_MEDIAMIX_LCDIF_DEFAULT_QOS(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_MEDIAMIX_LCDIF_DEFAULT_QOS_SHIFT)) & BLK_CTRL_MEDIAMIX_LCDIF_DEFAULT_QOS_MASK) +/*! @} */ + +/*! @name ISI0 - Cache of ISI */ +/*! @{ */ + +#define BLK_CTRL_MEDIAMIX_ISI0_ARCACHE_Y_MASK (0xFU) +#define BLK_CTRL_MEDIAMIX_ISI0_ARCACHE_Y_SHIFT (0U) +/*! ARCACHE_Y - ARCACHE_Y value of ISI */ +#define BLK_CTRL_MEDIAMIX_ISI0_ARCACHE_Y(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_MEDIAMIX_ISI0_ARCACHE_Y_SHIFT)) & BLK_CTRL_MEDIAMIX_ISI0_ARCACHE_Y_MASK) + +#define BLK_CTRL_MEDIAMIX_ISI0_AWCACHE_Y_MASK (0xF0U) +#define BLK_CTRL_MEDIAMIX_ISI0_AWCACHE_Y_SHIFT (4U) +/*! AWCACHE_Y - AWCACHE_Y value of ISI */ +#define BLK_CTRL_MEDIAMIX_ISI0_AWCACHE_Y(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_MEDIAMIX_ISI0_AWCACHE_Y_SHIFT)) & BLK_CTRL_MEDIAMIX_ISI0_AWCACHE_Y_MASK) + +#define BLK_CTRL_MEDIAMIX_ISI0_AWCACHE_U_MASK (0xF00U) +#define BLK_CTRL_MEDIAMIX_ISI0_AWCACHE_U_SHIFT (8U) +/*! AWCACHE_U - AWCACHE_U value of ISI */ +#define BLK_CTRL_MEDIAMIX_ISI0_AWCACHE_U(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_MEDIAMIX_ISI0_AWCACHE_U_SHIFT)) & BLK_CTRL_MEDIAMIX_ISI0_AWCACHE_U_MASK) + +#define BLK_CTRL_MEDIAMIX_ISI0_AWCACHE_V_MASK (0xF000U) +#define BLK_CTRL_MEDIAMIX_ISI0_AWCACHE_V_SHIFT (12U) +/*! AWCACHE_V - AWCACHE_V value of ISI */ +#define BLK_CTRL_MEDIAMIX_ISI0_AWCACHE_V(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_MEDIAMIX_ISI0_AWCACHE_V_SHIFT)) & BLK_CTRL_MEDIAMIX_ISI0_AWCACHE_V_MASK) + +#define BLK_CTRL_MEDIAMIX_ISI0_ARCACHE_Y_EN_MASK (0x10000U) +#define BLK_CTRL_MEDIAMIX_ISI0_ARCACHE_Y_EN_SHIFT (16U) +/*! ARCACHE_Y_EN - ARCACHE_Y enable of ISI + * 0b0..Do not enable ARCACHE_Y + * 0b1..Enable ARCACHE_Y + */ +#define BLK_CTRL_MEDIAMIX_ISI0_ARCACHE_Y_EN(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_MEDIAMIX_ISI0_ARCACHE_Y_EN_SHIFT)) & BLK_CTRL_MEDIAMIX_ISI0_ARCACHE_Y_EN_MASK) + +#define BLK_CTRL_MEDIAMIX_ISI0_AWCACHE_Y_EN_MASK (0x20000U) +#define BLK_CTRL_MEDIAMIX_ISI0_AWCACHE_Y_EN_SHIFT (17U) +/*! AWCACHE_Y_EN - AWCACHE_Y enable of ISI + * 0b0..Do not enable AWCACHE_Y + * 0b1..Enable AWCACHE_Y + */ +#define BLK_CTRL_MEDIAMIX_ISI0_AWCACHE_Y_EN(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_MEDIAMIX_ISI0_AWCACHE_Y_EN_SHIFT)) & BLK_CTRL_MEDIAMIX_ISI0_AWCACHE_Y_EN_MASK) + +#define BLK_CTRL_MEDIAMIX_ISI0_AWCACHE_U_EN_MASK (0x40000U) +#define BLK_CTRL_MEDIAMIX_ISI0_AWCACHE_U_EN_SHIFT (18U) +/*! AWCACHE_U_EN - AWCACHE_U enable of ISI + * 0b0..Do not enable AWACHE_U + * 0b1..Enable AWCACHE_U + */ +#define BLK_CTRL_MEDIAMIX_ISI0_AWCACHE_U_EN(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_MEDIAMIX_ISI0_AWCACHE_U_EN_SHIFT)) & BLK_CTRL_MEDIAMIX_ISI0_AWCACHE_U_EN_MASK) + +#define BLK_CTRL_MEDIAMIX_ISI0_AWCACHE_V_EN_MASK (0x80000U) +#define BLK_CTRL_MEDIAMIX_ISI0_AWCACHE_V_EN_SHIFT (19U) +/*! AWCACHE_V_EN - AWCACHE_V enable of ISI + * 0b0..Do not enable AWCACHE_V + * 0b1..Enable AWCACHE_V + */ +#define BLK_CTRL_MEDIAMIX_ISI0_AWCACHE_V_EN(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_MEDIAMIX_ISI0_AWCACHE_V_EN_SHIFT)) & BLK_CTRL_MEDIAMIX_ISI0_AWCACHE_V_EN_MASK) +/*! @} */ + +/*! @name ISI1 - QoS of ISI */ +/*! @{ */ + +#define BLK_CTRL_MEDIAMIX_ISI1_CFG_QOS_Y_W_MASK (0xFU) +#define BLK_CTRL_MEDIAMIX_ISI1_CFG_QOS_Y_W_SHIFT (0U) +/*! CFG_QOS_Y_W - cfg_qos_y_w value of ISI */ +#define BLK_CTRL_MEDIAMIX_ISI1_CFG_QOS_Y_W(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_MEDIAMIX_ISI1_CFG_QOS_Y_W_SHIFT)) & BLK_CTRL_MEDIAMIX_ISI1_CFG_QOS_Y_W_MASK) + +#define BLK_CTRL_MEDIAMIX_ISI1_DEFAULT_QOS_Y_W_MASK (0xF0U) +#define BLK_CTRL_MEDIAMIX_ISI1_DEFAULT_QOS_Y_W_SHIFT (4U) +/*! DEFAULT_QOS_Y_W - Default QOS_Y_W value of ISI */ +#define BLK_CTRL_MEDIAMIX_ISI1_DEFAULT_QOS_Y_W(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_MEDIAMIX_ISI1_DEFAULT_QOS_Y_W_SHIFT)) & BLK_CTRL_MEDIAMIX_ISI1_DEFAULT_QOS_Y_W_MASK) + +#define BLK_CTRL_MEDIAMIX_ISI1_CFG_QOS_Y_R_MASK (0xF00U) +#define BLK_CTRL_MEDIAMIX_ISI1_CFG_QOS_Y_R_SHIFT (8U) +/*! CFG_QOS_Y_R - CFG_QOS_Y_R value of ISI */ +#define BLK_CTRL_MEDIAMIX_ISI1_CFG_QOS_Y_R(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_MEDIAMIX_ISI1_CFG_QOS_Y_R_SHIFT)) & BLK_CTRL_MEDIAMIX_ISI1_CFG_QOS_Y_R_MASK) + +#define BLK_CTRL_MEDIAMIX_ISI1_DEFAULT_QOS_Y_R_MASK (0xF000U) +#define BLK_CTRL_MEDIAMIX_ISI1_DEFAULT_QOS_Y_R_SHIFT (12U) +/*! DEFAULT_QOS_Y_R - Default QOS_Y_R value of ISI */ +#define BLK_CTRL_MEDIAMIX_ISI1_DEFAULT_QOS_Y_R(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_MEDIAMIX_ISI1_DEFAULT_QOS_Y_R_SHIFT)) & BLK_CTRL_MEDIAMIX_ISI1_DEFAULT_QOS_Y_R_MASK) + +#define BLK_CTRL_MEDIAMIX_ISI1_CFG_QOS_U_MASK (0xF0000U) +#define BLK_CTRL_MEDIAMIX_ISI1_CFG_QOS_U_SHIFT (16U) +/*! CFG_QOS_U - cfg_qos_u value of ISI */ +#define BLK_CTRL_MEDIAMIX_ISI1_CFG_QOS_U(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_MEDIAMIX_ISI1_CFG_QOS_U_SHIFT)) & BLK_CTRL_MEDIAMIX_ISI1_CFG_QOS_U_MASK) + +#define BLK_CTRL_MEDIAMIX_ISI1_DEFAULT_QOS_U_MASK (0xF00000U) +#define BLK_CTRL_MEDIAMIX_ISI1_DEFAULT_QOS_U_SHIFT (20U) +/*! DEFAULT_QOS_U - Default QoS value of ISI */ +#define BLK_CTRL_MEDIAMIX_ISI1_DEFAULT_QOS_U(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_MEDIAMIX_ISI1_DEFAULT_QOS_U_SHIFT)) & BLK_CTRL_MEDIAMIX_ISI1_DEFAULT_QOS_U_MASK) + +#define BLK_CTRL_MEDIAMIX_ISI1_CFG_QOS_V_MASK (0xF000000U) +#define BLK_CTRL_MEDIAMIX_ISI1_CFG_QOS_V_SHIFT (24U) +/*! CFG_QOS_V - CFG_QOS_V value of ISI */ +#define BLK_CTRL_MEDIAMIX_ISI1_CFG_QOS_V(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_MEDIAMIX_ISI1_CFG_QOS_V_SHIFT)) & BLK_CTRL_MEDIAMIX_ISI1_CFG_QOS_V_MASK) + +#define BLK_CTRL_MEDIAMIX_ISI1_DEFAULT_QOS_V_MASK (0xF0000000U) +#define BLK_CTRL_MEDIAMIX_ISI1_DEFAULT_QOS_V_SHIFT (28U) +/*! DEFAULT_QOS_V - Default QOS_V value of ISI */ +#define BLK_CTRL_MEDIAMIX_ISI1_DEFAULT_QOS_V(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_MEDIAMIX_ISI1_DEFAULT_QOS_V_SHIFT)) & BLK_CTRL_MEDIAMIX_ISI1_DEFAULT_QOS_V_MASK) +/*! @} */ + +/*! @name PIXEL_CTRL - Read Pixel Control Register */ +/*! @{ */ + +#define BLK_CTRL_MEDIAMIX_PIXEL_CTRL_PIXEL_CTRL_MASK (0xFFFU) +#define BLK_CTRL_MEDIAMIX_PIXEL_CTRL_PIXEL_CTRL_SHIFT (0U) +/*! PIXEL_CTRL - Read pixel control information status */ +#define BLK_CTRL_MEDIAMIX_PIXEL_CTRL_PIXEL_CTRL(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_MEDIAMIX_PIXEL_CTRL_PIXEL_CTRL_SHIFT)) & BLK_CTRL_MEDIAMIX_PIXEL_CTRL_PIXEL_CTRL_MASK) +/*! @} */ + +/*! @name DISPLAY_MUX - Display Mux Control Register */ +/*! @{ */ + +#define BLK_CTRL_MEDIAMIX_DISPLAY_MUX_PARALLEL_DISP_FORMAT_MASK (0x700U) +#define BLK_CTRL_MEDIAMIX_DISPLAY_MUX_PARALLEL_DISP_FORMAT_SHIFT (8U) +/*! PARALLEL_DISP_FORMAT - Parallel display format configuration + * 0b000..RGB888 -> RGB888 + * 0b001..RGB888 -> RGB666. Truncate the two least significant bits of each color component (pass through the 6 + * most significant bits of each color component.) + * 0b010..RGB565 -> RGB565 + * 0b011..RGB555 -> RGB555 + * 0b100..YUV -> YCbCr 24 bits + * 0b101..YUV -> YUV444 + */ +#define BLK_CTRL_MEDIAMIX_DISPLAY_MUX_PARALLEL_DISP_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_MEDIAMIX_DISPLAY_MUX_PARALLEL_DISP_FORMAT_SHIFT)) & BLK_CTRL_MEDIAMIX_DISPLAY_MUX_PARALLEL_DISP_FORMAT_MASK) +/*! @} */ + +/*! @name IF_CTRL_REG - Parallel Camera Interface Register */ +/*! @{ */ + +#define BLK_CTRL_MEDIAMIX_IF_CTRL_REG_DATA_TYPE_SEL_MASK (0x100U) +#define BLK_CTRL_MEDIAMIX_IF_CTRL_REG_DATA_TYPE_SEL_SHIFT (8U) +/*! DATA_TYPE_SEL - Pixel link data type select + * 0b0..Reserved + * 0b1..Pixel Link data type comes from IF_CTRL_REG DATA_TYPE[4:0] + */ +#define BLK_CTRL_MEDIAMIX_IF_CTRL_REG_DATA_TYPE_SEL(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_MEDIAMIX_IF_CTRL_REG_DATA_TYPE_SEL_SHIFT)) & BLK_CTRL_MEDIAMIX_IF_CTRL_REG_DATA_TYPE_SEL_MASK) + +#define BLK_CTRL_MEDIAMIX_IF_CTRL_REG_DATA_TYPE_MASK (0x3E00U) +#define BLK_CTRL_MEDIAMIX_IF_CTRL_REG_DATA_TYPE_SHIFT (9U) +/*! DATA_TYPE - Date type to ISI control bus [11:7] + * 0b00000..Null data + * 0b00100..RGB format + * 0b01000..YUV444 format + * 0b10000..YYU420 type(a) odd line (not supported) + * 0b10010..YYU420 type(a) even line (not supported) + * 0b11000..YYU420 type(a) YYY odd line (not supported) + * 0b11010..YYU420 type(b) UYVY even line (not supported) + * 0b11100..RAW + */ +#define BLK_CTRL_MEDIAMIX_IF_CTRL_REG_DATA_TYPE(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_MEDIAMIX_IF_CTRL_REG_DATA_TYPE_SHIFT)) & BLK_CTRL_MEDIAMIX_IF_CTRL_REG_DATA_TYPE_MASK) +/*! @} */ + +/*! @name INTERFACE_STATUS - Interface Status Register */ +/*! @{ */ + +#define BLK_CTRL_MEDIAMIX_INTERFACE_STATUS_FIELD_TOGGLE_STATUS_MASK (0x1U) +#define BLK_CTRL_MEDIAMIX_INTERFACE_STATUS_FIELD_TOGGLE_STATUS_SHIFT (0U) +/*! FIELD_TOGGLE_STATUS - Field toggle status + * 0b0..VSYNC field toggle mode disabled + * 0b1..VSYNC field toggle mode enabled + */ +#define BLK_CTRL_MEDIAMIX_INTERFACE_STATUS_FIELD_TOGGLE_STATUS(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_MEDIAMIX_INTERFACE_STATUS_FIELD_TOGGLE_STATUS_SHIFT)) & BLK_CTRL_MEDIAMIX_INTERFACE_STATUS_FIELD_TOGGLE_STATUS_MASK) + +#define BLK_CTRL_MEDIAMIX_INTERFACE_STATUS_ECC_ERROR_STATUS_MASK (0x2U) +#define BLK_CTRL_MEDIAMIX_INTERFACE_STATUS_ECC_ERROR_STATUS_SHIFT (1U) +/*! ECC_ERROR_STATUS - ECC error status + * 0b0..No ECC error detected + * 0b1..ECC error detected + */ +#define BLK_CTRL_MEDIAMIX_INTERFACE_STATUS_ECC_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_MEDIAMIX_INTERFACE_STATUS_ECC_ERROR_STATUS_SHIFT)) & BLK_CTRL_MEDIAMIX_INTERFACE_STATUS_ECC_ERROR_STATUS_MASK) +/*! @} */ + +/*! @name INTERFACE_CTRL_REG - Interface Control Register */ +/*! @{ */ + +#define BLK_CTRL_MEDIAMIX_INTERFACE_CTRL_REG_PIXEL_CLK_POL_MASK (0x2U) +#define BLK_CTRL_MEDIAMIX_INTERFACE_CTRL_REG_PIXEL_CLK_POL_SHIFT (1U) +/*! PIXEL_CLK_POL - Pixel clock polarity control + * 0b0..Pixel clcok is not inverted. + * 0b1..Pixel clock input is inverted. + */ +#define BLK_CTRL_MEDIAMIX_INTERFACE_CTRL_REG_PIXEL_CLK_POL(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_MEDIAMIX_INTERFACE_CTRL_REG_PIXEL_CLK_POL_SHIFT)) & BLK_CTRL_MEDIAMIX_INTERFACE_CTRL_REG_PIXEL_CLK_POL_MASK) + +#define BLK_CTRL_MEDIAMIX_INTERFACE_CTRL_REG_HSYNC_POL_MASK (0x4U) +#define BLK_CTRL_MEDIAMIX_INTERFACE_CTRL_REG_HSYNC_POL_SHIFT (2U) +/*! HSYNC_POL - HSYNC polarity control + * 0b0..HSYNC output to Pixel Link is not inverted. + * 0b1..HSYNC output to Pixel Link is inverted. + */ +#define BLK_CTRL_MEDIAMIX_INTERFACE_CTRL_REG_HSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_MEDIAMIX_INTERFACE_CTRL_REG_HSYNC_POL_SHIFT)) & BLK_CTRL_MEDIAMIX_INTERFACE_CTRL_REG_HSYNC_POL_MASK) + +#define BLK_CTRL_MEDIAMIX_INTERFACE_CTRL_REG_VSYNC_POL_MASK (0x8U) +#define BLK_CTRL_MEDIAMIX_INTERFACE_CTRL_REG_VSYNC_POL_SHIFT (3U) +/*! VSYNC_POL - VSYNC polarity control + * 0b0..VSYNC output to Pixel Link is not inverted. + * 0b1..VSYNC output to Pixel Link is inverted. + */ +#define BLK_CTRL_MEDIAMIX_INTERFACE_CTRL_REG_VSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_MEDIAMIX_INTERFACE_CTRL_REG_VSYNC_POL_SHIFT)) & BLK_CTRL_MEDIAMIX_INTERFACE_CTRL_REG_VSYNC_POL_MASK) + +#define BLK_CTRL_MEDIAMIX_INTERFACE_CTRL_REG_DE_POL_MASK (0x10U) +#define BLK_CTRL_MEDIAMIX_INTERFACE_CTRL_REG_DE_POL_SHIFT (4U) +/*! DE_POL - DE polarity control + * 0b0..DE output to Pixel Link is not inverted. + * 0b1..DE output to Pixcel Link is inverted. + */ +#define BLK_CTRL_MEDIAMIX_INTERFACE_CTRL_REG_DE_POL(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_MEDIAMIX_INTERFACE_CTRL_REG_DE_POL_SHIFT)) & BLK_CTRL_MEDIAMIX_INTERFACE_CTRL_REG_DE_POL_MASK) + +#define BLK_CTRL_MEDIAMIX_INTERFACE_CTRL_REG_PIXEL_DATA_POL_MASK (0x20U) +#define BLK_CTRL_MEDIAMIX_INTERFACE_CTRL_REG_PIXEL_DATA_POL_SHIFT (5U) +/*! PIXEL_DATA_POL - PIXEL_DATA polarity control + * 0b0..PIXEL_DATA output to Pixel Link is not inverted. + * 0b1..PIXEL_DATA output to Pixel Link is inverted. + */ +#define BLK_CTRL_MEDIAMIX_INTERFACE_CTRL_REG_PIXEL_DATA_POL(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_MEDIAMIX_INTERFACE_CTRL_REG_PIXEL_DATA_POL_SHIFT)) & BLK_CTRL_MEDIAMIX_INTERFACE_CTRL_REG_PIXEL_DATA_POL_MASK) + +#define BLK_CTRL_MEDIAMIX_INTERFACE_CTRL_REG_CCIR_EXT_VSYNC_EN_MASK (0x40U) +#define BLK_CTRL_MEDIAMIX_INTERFACE_CTRL_REG_CCIR_EXT_VSYNC_EN_SHIFT (6U) +/*! CCIR_EXT_VSYNC_EN - External VSYNC enable */ +#define BLK_CTRL_MEDIAMIX_INTERFACE_CTRL_REG_CCIR_EXT_VSYNC_EN(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_MEDIAMIX_INTERFACE_CTRL_REG_CCIR_EXT_VSYNC_EN_SHIFT)) & BLK_CTRL_MEDIAMIX_INTERFACE_CTRL_REG_CCIR_EXT_VSYNC_EN_MASK) + +#define BLK_CTRL_MEDIAMIX_INTERFACE_CTRL_REG_CCIR_EN_MASK (0x80U) +#define BLK_CTRL_MEDIAMIX_INTERFACE_CTRL_REG_CCIR_EN_SHIFT (7U) +/*! CCIR_EN - CCIR mode enable + * 0b0..CCIR mode disable + * 0b1..CCIR mode enable + */ +#define BLK_CTRL_MEDIAMIX_INTERFACE_CTRL_REG_CCIR_EN(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_MEDIAMIX_INTERFACE_CTRL_REG_CCIR_EN_SHIFT)) & BLK_CTRL_MEDIAMIX_INTERFACE_CTRL_REG_CCIR_EN_MASK) + +#define BLK_CTRL_MEDIAMIX_INTERFACE_CTRL_REG_CCIR_VIDEO_MODE_MASK (0x100U) +#define BLK_CTRL_MEDIAMIX_INTERFACE_CTRL_REG_CCIR_VIDEO_MODE_SHIFT (8U) +/*! CCIR_VIDEO_MODE - CCIR video mode + * 0b0..Progressive mode + * 0b1..Interlace + */ +#define BLK_CTRL_MEDIAMIX_INTERFACE_CTRL_REG_CCIR_VIDEO_MODE(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_MEDIAMIX_INTERFACE_CTRL_REG_CCIR_VIDEO_MODE_SHIFT)) & BLK_CTRL_MEDIAMIX_INTERFACE_CTRL_REG_CCIR_VIDEO_MODE_MASK) + +#define BLK_CTRL_MEDIAMIX_INTERFACE_CTRL_REG_CCIR_NTSC_EN_MASK (0x200U) +#define BLK_CTRL_MEDIAMIX_INTERFACE_CTRL_REG_CCIR_NTSC_EN_SHIFT (9U) +/*! CCIR_NTSC_EN - CCIR NTSC enable + * 0b0..PAL + * 0b1..NTSC + */ +#define BLK_CTRL_MEDIAMIX_INTERFACE_CTRL_REG_CCIR_NTSC_EN(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_MEDIAMIX_INTERFACE_CTRL_REG_CCIR_NTSC_EN_SHIFT)) & BLK_CTRL_MEDIAMIX_INTERFACE_CTRL_REG_CCIR_NTSC_EN_MASK) + +#define BLK_CTRL_MEDIAMIX_INTERFACE_CTRL_REG_CCIR_VSYNC_RST_EN_MASK (0x400U) +#define BLK_CTRL_MEDIAMIX_INTERFACE_CTRL_REG_CCIR_VSYNC_RST_EN_SHIFT (10U) +/*! CCIR_VSYNC_RST_EN - CCIR_VSYNC_RESET_EN */ +#define BLK_CTRL_MEDIAMIX_INTERFACE_CTRL_REG_CCIR_VSYNC_RST_EN(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_MEDIAMIX_INTERFACE_CTRL_REG_CCIR_VSYNC_RST_EN_SHIFT)) & BLK_CTRL_MEDIAMIX_INTERFACE_CTRL_REG_CCIR_VSYNC_RST_EN_MASK) + +#define BLK_CTRL_MEDIAMIX_INTERFACE_CTRL_REG_CCIR_ECC_CORR_EN_MASK (0x800U) +#define BLK_CTRL_MEDIAMIX_INTERFACE_CTRL_REG_CCIR_ECC_CORR_EN_SHIFT (11U) +/*! CCIR_ECC_CORR_EN - CCIR error correction enable + * 0b0..ECC error correction is disabled. + * 0b1..ECC error correction is enabled. + */ +#define BLK_CTRL_MEDIAMIX_INTERFACE_CTRL_REG_CCIR_ECC_CORR_EN(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_MEDIAMIX_INTERFACE_CTRL_REG_CCIR_ECC_CORR_EN_SHIFT)) & BLK_CTRL_MEDIAMIX_INTERFACE_CTRL_REG_CCIR_ECC_CORR_EN_MASK) + +#define BLK_CTRL_MEDIAMIX_INTERFACE_CTRL_REG_HSYNC_FORCE_EN_MASK (0x1000U) +#define BLK_CTRL_MEDIAMIX_INTERFACE_CTRL_REG_HSYNC_FORCE_EN_SHIFT (12U) +/*! HSYNC_FORCE_EN - HSYNC force enable + * 0b0..Do not override HSYNC. + * 0b1..Override HSYNC. + */ +#define BLK_CTRL_MEDIAMIX_INTERFACE_CTRL_REG_HSYNC_FORCE_EN(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_MEDIAMIX_INTERFACE_CTRL_REG_HSYNC_FORCE_EN_SHIFT)) & BLK_CTRL_MEDIAMIX_INTERFACE_CTRL_REG_HSYNC_FORCE_EN_MASK) + +#define BLK_CTRL_MEDIAMIX_INTERFACE_CTRL_REG_VSYNC_FORCE_EN_MASK (0x2000U) +#define BLK_CTRL_MEDIAMIX_INTERFACE_CTRL_REG_VSYNC_FORCE_EN_SHIFT (13U) +/*! VSYNC_FORCE_EN - VSYNC force enable + * 0b0..Do not override VSYNC. + * 0b1..Override VSYNC. + */ +#define BLK_CTRL_MEDIAMIX_INTERFACE_CTRL_REG_VSYNC_FORCE_EN(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_MEDIAMIX_INTERFACE_CTRL_REG_VSYNC_FORCE_EN_SHIFT)) & BLK_CTRL_MEDIAMIX_INTERFACE_CTRL_REG_VSYNC_FORCE_EN_MASK) + +#define BLK_CTRL_MEDIAMIX_INTERFACE_CTRL_REG_GCLK_MODE_EN_MASK (0x4000U) +#define BLK_CTRL_MEDIAMIX_INTERFACE_CTRL_REG_GCLK_MODE_EN_SHIFT (14U) +/*! GCLK_MODE_EN - Gate clock mode enable + * 0b0..Disable + * 0b1..Enable + */ +#define BLK_CTRL_MEDIAMIX_INTERFACE_CTRL_REG_GCLK_MODE_EN(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_MEDIAMIX_INTERFACE_CTRL_REG_GCLK_MODE_EN_SHIFT)) & BLK_CTRL_MEDIAMIX_INTERFACE_CTRL_REG_GCLK_MODE_EN_MASK) + +#define BLK_CTRL_MEDIAMIX_INTERFACE_CTRL_REG_VALID_SEL_MASK (0x8000U) +#define BLK_CTRL_MEDIAMIX_INTERFACE_CTRL_REG_VALID_SEL_SHIFT (15U) +/*! VALID_SEL - Data valid select + * 0b0..HSYNC data valid. + * 0b1..Data enable valid. Not supported. + */ +#define BLK_CTRL_MEDIAMIX_INTERFACE_CTRL_REG_VALID_SEL(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_MEDIAMIX_INTERFACE_CTRL_REG_VALID_SEL_SHIFT)) & BLK_CTRL_MEDIAMIX_INTERFACE_CTRL_REG_VALID_SEL_MASK) + +#define BLK_CTRL_MEDIAMIX_INTERFACE_CTRL_REG_RAW_OUT_SEL_MASK (0x10000U) +#define BLK_CTRL_MEDIAMIX_INTERFACE_CTRL_REG_RAW_OUT_SEL_SHIFT (16U) +/*! RAW_OUT_SEL - RAW output select + * 0b0..Right justified output + * 0b1..Left justified to 14-bit output + */ +#define BLK_CTRL_MEDIAMIX_INTERFACE_CTRL_REG_RAW_OUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_MEDIAMIX_INTERFACE_CTRL_REG_RAW_OUT_SEL_SHIFT)) & BLK_CTRL_MEDIAMIX_INTERFACE_CTRL_REG_RAW_OUT_SEL_MASK) + +#define BLK_CTRL_MEDIAMIX_INTERFACE_CTRL_REG_HSYNC_OUT_SEL_MASK (0x20000U) +#define BLK_CTRL_MEDIAMIX_INTERFACE_CTRL_REG_HSYNC_OUT_SEL_SHIFT (17U) +/*! HSYNC_OUT_SEL - HSYNC output select + * 0b0..HYSNC output level + * 0b1..HYSNC output pulse + */ +#define BLK_CTRL_MEDIAMIX_INTERFACE_CTRL_REG_HSYNC_OUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_MEDIAMIX_INTERFACE_CTRL_REG_HSYNC_OUT_SEL_SHIFT)) & BLK_CTRL_MEDIAMIX_INTERFACE_CTRL_REG_HSYNC_OUT_SEL_MASK) + +#define BLK_CTRL_MEDIAMIX_INTERFACE_CTRL_REG_HSYNC_PULSE_MASK (0x380000U) +#define BLK_CTRL_MEDIAMIX_INTERFACE_CTRL_REG_HSYNC_PULSE_SHIFT (19U) +/*! HSYNC_PULSE - HSYNC_PULSE */ +#define BLK_CTRL_MEDIAMIX_INTERFACE_CTRL_REG_HSYNC_PULSE(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_MEDIAMIX_INTERFACE_CTRL_REG_HSYNC_PULSE_SHIFT)) & BLK_CTRL_MEDIAMIX_INTERFACE_CTRL_REG_HSYNC_PULSE_MASK) + +#define BLK_CTRL_MEDIAMIX_INTERFACE_CTRL_REG_UV_SWAP_EN_MASK (0x400000U) +#define BLK_CTRL_MEDIAMIX_INTERFACE_CTRL_REG_UV_SWAP_EN_SHIFT (22U) +/*! UV_SWAP_EN - UV swap enable + * 0b0..UV swap disable + * 0b1..UV swap enable + */ +#define BLK_CTRL_MEDIAMIX_INTERFACE_CTRL_REG_UV_SWAP_EN(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_MEDIAMIX_INTERFACE_CTRL_REG_UV_SWAP_EN_SHIFT)) & BLK_CTRL_MEDIAMIX_INTERFACE_CTRL_REG_UV_SWAP_EN_MASK) +/*! @} */ + +/*! @name INTERFACE_CTRL_REG1 - Interface Control Register 1 */ +/*! @{ */ + +#define BLK_CTRL_MEDIAMIX_INTERFACE_CTRL_REG1_VSYNC_PULSE_MASK (0xFFFFU) +#define BLK_CTRL_MEDIAMIX_INTERFACE_CTRL_REG1_VSYNC_PULSE_SHIFT (0U) +/*! VSYNC_PULSE - VSYNC pulse width */ +#define BLK_CTRL_MEDIAMIX_INTERFACE_CTRL_REG1_VSYNC_PULSE(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_MEDIAMIX_INTERFACE_CTRL_REG1_VSYNC_PULSE_SHIFT)) & BLK_CTRL_MEDIAMIX_INTERFACE_CTRL_REG1_VSYNC_PULSE_MASK) +/*! @} */ + +/*! @name RESET - RESET Control Register */ +/*! @{ */ + +#define BLK_CTRL_MEDIAMIX_RESET_bus_apb_en_MASK (0x1U) +#define BLK_CTRL_MEDIAMIX_RESET_bus_apb_en_SHIFT (0U) +/*! bus_apb_en - Bus apb_clk reset + * 0b0..Reset bus apb_clk related logic + * 0b1..Do not reset bus apb_clk related logic + */ +#define BLK_CTRL_MEDIAMIX_RESET_bus_apb_en(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_MEDIAMIX_RESET_bus_apb_en_SHIFT)) & BLK_CTRL_MEDIAMIX_RESET_bus_apb_en_MASK) + +#define BLK_CTRL_MEDIAMIX_RESET_bus_blk_en_MASK (0x2U) +#define BLK_CTRL_MEDIAMIX_RESET_bus_blk_en_SHIFT (1U) +/*! bus_blk_en - Bus axi_clk reset + * 0b0..Reset bus axi_clk related logic + * 0b1..Do not reset bus axi_clk related logic + */ +#define BLK_CTRL_MEDIAMIX_RESET_bus_blk_en(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_MEDIAMIX_RESET_bus_blk_en_SHIFT)) & BLK_CTRL_MEDIAMIX_RESET_bus_blk_en_MASK) + +#define BLK_CTRL_MEDIAMIX_RESET_isi_apb_en_MASK (0x4U) +#define BLK_CTRL_MEDIAMIX_RESET_isi_apb_en_SHIFT (2U) +/*! isi_apb_en - ISI apb_clk reset + * 0b0..Reset ISI apb_clk related logic + * 0b1..Do not reset ISI apb_clk related logic + */ +#define BLK_CTRL_MEDIAMIX_RESET_isi_apb_en(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_MEDIAMIX_RESET_isi_apb_en_SHIFT)) & BLK_CTRL_MEDIAMIX_RESET_isi_apb_en_MASK) + +#define BLK_CTRL_MEDIAMIX_RESET_isi_proc_en_MASK (0x8U) +#define BLK_CTRL_MEDIAMIX_RESET_isi_proc_en_SHIFT (3U) +/*! isi_proc_en - ISI axi_clk reset + * 0b0..Reset ISI axi_clk related logic + * 0b1..Do not reset ISI axi_clk related logic + */ +#define BLK_CTRL_MEDIAMIX_RESET_isi_proc_en(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_MEDIAMIX_RESET_isi_proc_en_SHIFT)) & BLK_CTRL_MEDIAMIX_RESET_isi_proc_en_MASK) + +#define BLK_CTRL_MEDIAMIX_RESET_lcdif_apb_en_MASK (0x10U) +#define BLK_CTRL_MEDIAMIX_RESET_lcdif_apb_en_SHIFT (4U) +/*! lcdif_apb_en - LCDIF apb_clk reset + * 0b0..Reset LCDIF apb_clk related logic + * 0b1..Do not reset LCDIF apb_clk related logic + */ +#define BLK_CTRL_MEDIAMIX_RESET_lcdif_apb_en(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_MEDIAMIX_RESET_lcdif_apb_en_SHIFT)) & BLK_CTRL_MEDIAMIX_RESET_lcdif_apb_en_MASK) + +#define BLK_CTRL_MEDIAMIX_RESET_lcdif_axi_en_MASK (0x20U) +#define BLK_CTRL_MEDIAMIX_RESET_lcdif_axi_en_SHIFT (5U) +/*! lcdif_axi_en - LCDIF axi_clk reset + * 0b0..Reset LCDIF axi_clk related logic + * 0b1..Do not reset LCDIF axi_clk related logic + */ +#define BLK_CTRL_MEDIAMIX_RESET_lcdif_axi_en(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_MEDIAMIX_RESET_lcdif_axi_en_SHIFT)) & BLK_CTRL_MEDIAMIX_RESET_lcdif_axi_en_MASK) + +#define BLK_CTRL_MEDIAMIX_RESET_lcdif_pix_en_MASK (0x40U) +#define BLK_CTRL_MEDIAMIX_RESET_lcdif_pix_en_SHIFT (6U) +/*! lcdif_pix_en - LCDIF pix_clk reset + * 0b0..Reset LCDIF pix_clk related logic + * 0b1..Do not reset LCDIF pix_clk related logic + */ +#define BLK_CTRL_MEDIAMIX_RESET_lcdif_pix_en(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_MEDIAMIX_RESET_lcdif_pix_en_SHIFT)) & BLK_CTRL_MEDIAMIX_RESET_lcdif_pix_en_MASK) + +#define BLK_CTRL_MEDIAMIX_RESET_cam_clk_en_MASK (0x400U) +#define BLK_CTRL_MEDIAMIX_RESET_cam_clk_en_SHIFT (10U) +/*! cam_clk_en - Camera clock reset + * 0b0..Reset camera related logic + * 0b1..Do not reset camera clock related logic + */ +#define BLK_CTRL_MEDIAMIX_RESET_cam_clk_en(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_MEDIAMIX_RESET_cam_clk_en_SHIFT)) & BLK_CTRL_MEDIAMIX_RESET_cam_clk_en_MASK) +/*! @} */ + +/*! @name CLK - CLK Control Register */ +/*! @{ */ + +#define BLK_CTRL_MEDIAMIX_CLK_bus_apb_en_MASK (0x1U) +#define BLK_CTRL_MEDIAMIX_CLK_bus_apb_en_SHIFT (0U) +/*! bus_apb_en - Bus apb_clk gate enable + * 0b0..Do not gate bus apb_clk root + * 0b1..Gate bus apb_clk root + */ +#define BLK_CTRL_MEDIAMIX_CLK_bus_apb_en(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_MEDIAMIX_CLK_bus_apb_en_SHIFT)) & BLK_CTRL_MEDIAMIX_CLK_bus_apb_en_MASK) + +#define BLK_CTRL_MEDIAMIX_CLK_bus_blk_en_MASK (0x2U) +#define BLK_CTRL_MEDIAMIX_CLK_bus_blk_en_SHIFT (1U) +/*! bus_blk_en - Bus axi_clk gate enable + * 0b0..Do not gate bus axi_clk root + * 0b1..Gate bus axi_clk root + */ +#define BLK_CTRL_MEDIAMIX_CLK_bus_blk_en(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_MEDIAMIX_CLK_bus_blk_en_SHIFT)) & BLK_CTRL_MEDIAMIX_CLK_bus_blk_en_MASK) + +#define BLK_CTRL_MEDIAMIX_CLK_isi_apb_en_MASK (0x4U) +#define BLK_CTRL_MEDIAMIX_CLK_isi_apb_en_SHIFT (2U) +/*! isi_apb_en - ISI apb_clk gate enable + * 0b0..Do not gate ISI apb_clk root + * 0b1..Gate ISI apb_clk root + */ +#define BLK_CTRL_MEDIAMIX_CLK_isi_apb_en(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_MEDIAMIX_CLK_isi_apb_en_SHIFT)) & BLK_CTRL_MEDIAMIX_CLK_isi_apb_en_MASK) + +#define BLK_CTRL_MEDIAMIX_CLK_isi_proc_en_MASK (0x8U) +#define BLK_CTRL_MEDIAMIX_CLK_isi_proc_en_SHIFT (3U) +/*! isi_proc_en - ISI axi_clk gate enable + * 0b0..Do not gate ISI axi_clk root + * 0b1..Gate ISI axi_clk root + */ +#define BLK_CTRL_MEDIAMIX_CLK_isi_proc_en(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_MEDIAMIX_CLK_isi_proc_en_SHIFT)) & BLK_CTRL_MEDIAMIX_CLK_isi_proc_en_MASK) + +#define BLK_CTRL_MEDIAMIX_CLK_lcdif_apb_en_MASK (0x10U) +#define BLK_CTRL_MEDIAMIX_CLK_lcdif_apb_en_SHIFT (4U) +/*! lcdif_apb_en - LCDIF apb_clk gate enable + * 0b0..Do not gate LCDIF apb_clk root + * 0b1..Gate LCDIF apb_clk root + */ +#define BLK_CTRL_MEDIAMIX_CLK_lcdif_apb_en(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_MEDIAMIX_CLK_lcdif_apb_en_SHIFT)) & BLK_CTRL_MEDIAMIX_CLK_lcdif_apb_en_MASK) + +#define BLK_CTRL_MEDIAMIX_CLK_lcdif_axi_en_MASK (0x20U) +#define BLK_CTRL_MEDIAMIX_CLK_lcdif_axi_en_SHIFT (5U) +/*! lcdif_axi_en - LCDIF axi_clk gate enable + * 0b0..Do not gate LCDIF axi_clk root + * 0b1..Gate LCDIF axi_clk root + */ +#define BLK_CTRL_MEDIAMIX_CLK_lcdif_axi_en(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_MEDIAMIX_CLK_lcdif_axi_en_SHIFT)) & BLK_CTRL_MEDIAMIX_CLK_lcdif_axi_en_MASK) + +#define BLK_CTRL_MEDIAMIX_CLK_lcdif_pix_en_MASK (0x40U) +#define BLK_CTRL_MEDIAMIX_CLK_lcdif_pix_en_SHIFT (6U) +/*! lcdif_pix_en - LCDIF pix_clk gate enable + * 0b0..Do not gate LCDIF pix_clk root + * 0b1..Gate LCDIF pix_clk root + */ +#define BLK_CTRL_MEDIAMIX_CLK_lcdif_pix_en(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_MEDIAMIX_CLK_lcdif_pix_en_SHIFT)) & BLK_CTRL_MEDIAMIX_CLK_lcdif_pix_en_MASK) + +#define BLK_CTRL_MEDIAMIX_CLK_cam_clk_en_MASK (0x400U) +#define BLK_CTRL_MEDIAMIX_CLK_cam_clk_en_SHIFT (10U) +/*! cam_clk_en - cam_clk gate enable + * 0b0..Do not gate cam_clk root + * 0b1..Gate cam_clk root + */ +#define BLK_CTRL_MEDIAMIX_CLK_cam_clk_en(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_MEDIAMIX_CLK_cam_clk_en_SHIFT)) & BLK_CTRL_MEDIAMIX_CLK_cam_clk_en_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group BLK_CTRL_MEDIAMIX_Register_Masks */ + + +/* BLK_CTRL_MEDIAMIX - Peripheral instance base addresses */ +/** Peripheral BLK_CTRL_MEDIAMIX1 base address */ +#define BLK_CTRL_MEDIAMIX1_BASE (0x4AC10000u) +/** Peripheral BLK_CTRL_MEDIAMIX1 base pointer */ +#define BLK_CTRL_MEDIAMIX1 ((BLK_CTRL_MEDIAMIX_Type *)BLK_CTRL_MEDIAMIX1_BASE) +/** Array initializer of BLK_CTRL_MEDIAMIX peripheral base addresses */ +#define BLK_CTRL_MEDIAMIX_BASE_ADDRS { BLK_CTRL_MEDIAMIX1_BASE } +/** Array initializer of BLK_CTRL_MEDIAMIX peripheral base pointers */ +#define BLK_CTRL_MEDIAMIX_BASE_PTRS { BLK_CTRL_MEDIAMIX1 } + +/*! + * @} + */ /* end of group BLK_CTRL_MEDIAMIX_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- BLK_CTRL_NIC_WRAPPER Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup BLK_CTRL_NIC_WRAPPER_Peripheral_Access_Layer BLK_CTRL_NIC_WRAPPER Peripheral Access Layer + * @{ + */ + +/** BLK_CTRL_NIC_WRAPPER - Register Layout Typedef */ +typedef struct { + __IO uint32_t DEXSC_ERR; /**< DEXSC error response configuration, offset: 0x0 */ + uint8_t RESERVED_0[4]; + __IO uint32_t AXI_LIMIT_WAKEUPMIX; /**< Configuration register for axi_limit_wakeupmix, offset: 0x8 */ + __IO uint32_t CACHE_ATTR; /**< Configuration register for AxCACHE[1] override, offset: 0xC */ + __IO uint32_t WAKEUPMIX_QOS; /**< Configuration register for QoS value from wakeupmix, offset: 0x10 */ + __IO uint32_t CACHE_QOS; /**< Configuration register for QoS value from A55, offset: 0x14 */ + uint8_t RESERVED_1[8]; + __IO uint32_t HSIOMIX_QOS; /**< Configuration register for QoS value from hsiomix, offset: 0x20 */ + __IO uint32_t TIE_VALUE; /**< GPR for uncertain tie0 or tie1, offset: 0x24 */ + __IO uint32_t OCRAM_SGLECC_ERR_INT; /**< OCRAM single ECC error interrupt flag, offset: 0x28 */ + uint8_t RESERVED_2[4]; + __IO uint32_t SSI_MST_DDRMIX; /**< low power control for SSI_MST_DDRMIX, offset: 0x30 */ + __IO uint32_t SSI_MST_GIC600; /**< low power control for SSI_MST_GIC600, offset: 0x34 */ + __IO uint32_t SSI_MST_WAKEUPMIX; /**< low power control for SSI_MST_WAKEUPMIX, offset: 0x38 */ + __IO uint32_t SSI_SLV_CACHE; /**< low power control for SSI_SLV_CACHE, offset: 0x3C */ + __IO uint32_t SSI_SLV_GIC600; /**< low power control for SSI_SLV_GIC600, offset: 0x40 */ + __IO uint32_t SSI_SLV_HSIOMIX; /**< low power control for SSI_SLV_HSIOMIX, offset: 0x44 */ + __IO uint32_t SSI_SLV_MEDIAMIX; /**< low power control for SSI_SLV_MEDIAMIX, offset: 0x48 */ + __IO uint32_t SSI_SLV_WAKEUPMIX; /**< low power control for SSI_SLV_WAKEUPMIX, offset: 0x4C */ + uint8_t RESERVED_3[16]; + __IO uint32_t REG_RW; /**< reserved, offset: 0x60 */ + __I uint32_t REG_RO; /**< reserved, offset: 0x64 */ +} BLK_CTRL_NIC_WRAPPER_Type; + +/* ---------------------------------------------------------------------------- + -- BLK_CTRL_NIC_WRAPPER Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup BLK_CTRL_NIC_WRAPPER_Register_Masks BLK_CTRL_NIC_WRAPPER Register Masks + * @{ + */ + +/*! @name DEXSC_ERR - DEXSC error response configuration */ +/*! @{ */ + +#define BLK_CTRL_NIC_WRAPPER_DEXSC_ERR_OCRAM_ERR_RESP_EN_MASK (0x1U) +#define BLK_CTRL_NIC_WRAPPER_DEXSC_ERR_OCRAM_ERR_RESP_EN_SHIFT (0U) +/*! OCRAM_ERR_RESP_EN - OCRAM DEXSC error response enable + * 0b0..DEXSC will not respond error if there is read error on DEXSC + * 0b1..DEXSC will respond slave error if there is read error on DEXSC + */ +#define BLK_CTRL_NIC_WRAPPER_DEXSC_ERR_OCRAM_ERR_RESP_EN(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NIC_WRAPPER_DEXSC_ERR_OCRAM_ERR_RESP_EN_SHIFT)) & BLK_CTRL_NIC_WRAPPER_DEXSC_ERR_OCRAM_ERR_RESP_EN_MASK) + +#define BLK_CTRL_NIC_WRAPPER_DEXSC_ERR_OCRAM_EXC_ERR_RESP_EN_MASK (0x2U) +#define BLK_CTRL_NIC_WRAPPER_DEXSC_ERR_OCRAM_EXC_ERR_RESP_EN_SHIFT (1U) +/*! OCRAM_EXC_ERR_RESP_EN - OCRAM DEXSC exclusive error response enable + * 0b0..DEXSC will not respond error if there is exclusive error on DEXSC + * 0b1..DEXSC will respond slave error if there is exclusive error on DEXSC + */ +#define BLK_CTRL_NIC_WRAPPER_DEXSC_ERR_OCRAM_EXC_ERR_RESP_EN(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NIC_WRAPPER_DEXSC_ERR_OCRAM_EXC_ERR_RESP_EN_SHIFT)) & BLK_CTRL_NIC_WRAPPER_DEXSC_ERR_OCRAM_EXC_ERR_RESP_EN_MASK) + +#define BLK_CTRL_NIC_WRAPPER_DEXSC_ERR_OCRAM_LOCK_ERR_RESP_EN_MASK (0x4U) +#define BLK_CTRL_NIC_WRAPPER_DEXSC_ERR_OCRAM_LOCK_ERR_RESP_EN_SHIFT (2U) +/*! OCRAM_LOCK_ERR_RESP_EN - Lock bit of OCRAM_ERR_RESP_EN and OCRAM_EXC_ERR_RESP_EN */ +#define BLK_CTRL_NIC_WRAPPER_DEXSC_ERR_OCRAM_LOCK_ERR_RESP_EN(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NIC_WRAPPER_DEXSC_ERR_OCRAM_LOCK_ERR_RESP_EN_SHIFT)) & BLK_CTRL_NIC_WRAPPER_DEXSC_ERR_OCRAM_LOCK_ERR_RESP_EN_MASK) + +#define BLK_CTRL_NIC_WRAPPER_DEXSC_ERR_DRAM_ERR_RESP_EN_MASK (0x10000U) +#define BLK_CTRL_NIC_WRAPPER_DEXSC_ERR_DRAM_ERR_RESP_EN_SHIFT (16U) +/*! DRAM_ERR_RESP_EN - DRAM DEXSC error response enable + * 0b0..DEXSC will not respond error if there is read error on DEXSC + * 0b1..DEXSC will respond slave error if there is read error on DEXSC + */ +#define BLK_CTRL_NIC_WRAPPER_DEXSC_ERR_DRAM_ERR_RESP_EN(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NIC_WRAPPER_DEXSC_ERR_DRAM_ERR_RESP_EN_SHIFT)) & BLK_CTRL_NIC_WRAPPER_DEXSC_ERR_DRAM_ERR_RESP_EN_MASK) + +#define BLK_CTRL_NIC_WRAPPER_DEXSC_ERR_DRAM_EXC_ERR_RESP_EN_MASK (0x20000U) +#define BLK_CTRL_NIC_WRAPPER_DEXSC_ERR_DRAM_EXC_ERR_RESP_EN_SHIFT (17U) +/*! DRAM_EXC_ERR_RESP_EN - DRAM DEXSC exclusive error response enable + * 0b0..DEXSC will not respond error if there is exclusive error on DEXSC + * 0b1..DEXSC will respond slave error if there is exclusive error on DEXSC + */ +#define BLK_CTRL_NIC_WRAPPER_DEXSC_ERR_DRAM_EXC_ERR_RESP_EN(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NIC_WRAPPER_DEXSC_ERR_DRAM_EXC_ERR_RESP_EN_SHIFT)) & BLK_CTRL_NIC_WRAPPER_DEXSC_ERR_DRAM_EXC_ERR_RESP_EN_MASK) + +#define BLK_CTRL_NIC_WRAPPER_DEXSC_ERR_DRAM_LOCK_ERR_RESP_EN_MASK (0x40000U) +#define BLK_CTRL_NIC_WRAPPER_DEXSC_ERR_DRAM_LOCK_ERR_RESP_EN_SHIFT (18U) +/*! DRAM_LOCK_ERR_RESP_EN - Lock bit of DRAM_ERR_RESP_EN and DRAM_EXC_ERR_RESP_EN */ +#define BLK_CTRL_NIC_WRAPPER_DEXSC_ERR_DRAM_LOCK_ERR_RESP_EN(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NIC_WRAPPER_DEXSC_ERR_DRAM_LOCK_ERR_RESP_EN_SHIFT)) & BLK_CTRL_NIC_WRAPPER_DEXSC_ERR_DRAM_LOCK_ERR_RESP_EN_MASK) +/*! @} */ + +/*! @name AXI_LIMIT_WAKEUPMIX - Configuration register for axi_limit_wakeupmix */ +/*! @{ */ + +#define BLK_CTRL_NIC_WRAPPER_AXI_LIMIT_WAKEUPMIX_ENABLE_MASK (0x1U) +#define BLK_CTRL_NIC_WRAPPER_AXI_LIMIT_WAKEUPMIX_ENABLE_SHIFT (0U) +/*! ENABLE - Enable the beat limit on the access from wakeupmix + * 0b0..Disable the beat limit + * 0b1..Enable the beat limit + */ +#define BLK_CTRL_NIC_WRAPPER_AXI_LIMIT_WAKEUPMIX_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NIC_WRAPPER_AXI_LIMIT_WAKEUPMIX_ENABLE_SHIFT)) & BLK_CTRL_NIC_WRAPPER_AXI_LIMIT_WAKEUPMIX_ENABLE_MASK) + +#define BLK_CTRL_NIC_WRAPPER_AXI_LIMIT_WAKEUPMIX_BEAT_LIMIT_MASK (0xFFFF0000U) +#define BLK_CTRL_NIC_WRAPPER_AXI_LIMIT_WAKEUPMIX_BEAT_LIMIT_SHIFT (16U) +/*! BEAT_LIMIT - Beat limit number */ +#define BLK_CTRL_NIC_WRAPPER_AXI_LIMIT_WAKEUPMIX_BEAT_LIMIT(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NIC_WRAPPER_AXI_LIMIT_WAKEUPMIX_BEAT_LIMIT_SHIFT)) & BLK_CTRL_NIC_WRAPPER_AXI_LIMIT_WAKEUPMIX_BEAT_LIMIT_MASK) +/*! @} */ + +/*! @name CACHE_ATTR - Configuration register for AxCACHE[1] override */ +/*! @{ */ + +#define BLK_CTRL_NIC_WRAPPER_CACHE_ATTR_WAKEUPMIX_ARCACHE_EN_MASK (0x1U) +#define BLK_CTRL_NIC_WRAPPER_CACHE_ATTR_WAKEUPMIX_ARCACHE_EN_SHIFT (0U) +/*! WAKEUPMIX_ARCACHE_EN - Enable ARCACHE[1] override + * 0b0..Disable override ARCACHE[1] from ssi_slv_wakeupmix + * 0b1..enable override ARCACHE[1] from ssi_slv_wakeupmix + */ +#define BLK_CTRL_NIC_WRAPPER_CACHE_ATTR_WAKEUPMIX_ARCACHE_EN(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NIC_WRAPPER_CACHE_ATTR_WAKEUPMIX_ARCACHE_EN_SHIFT)) & BLK_CTRL_NIC_WRAPPER_CACHE_ATTR_WAKEUPMIX_ARCACHE_EN_MASK) + +#define BLK_CTRL_NIC_WRAPPER_CACHE_ATTR_WAKEUPMIX_AWCACHE_EN_MASK (0x2U) +#define BLK_CTRL_NIC_WRAPPER_CACHE_ATTR_WAKEUPMIX_AWCACHE_EN_SHIFT (1U) +/*! WAKEUPMIX_AWCACHE_EN - Enable AWCACHE[1] override + * 0b0..Disable override AWCACHE[1] from ssi_slv_wakeupmix + * 0b1..enable override AWCACHE[1] from ssi_slv_wakeupmix + */ +#define BLK_CTRL_NIC_WRAPPER_CACHE_ATTR_WAKEUPMIX_AWCACHE_EN(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NIC_WRAPPER_CACHE_ATTR_WAKEUPMIX_AWCACHE_EN_SHIFT)) & BLK_CTRL_NIC_WRAPPER_CACHE_ATTR_WAKEUPMIX_AWCACHE_EN_MASK) + +#define BLK_CTRL_NIC_WRAPPER_CACHE_ATTR_CACHE_ARCACHE_EN_MASK (0x4U) +#define BLK_CTRL_NIC_WRAPPER_CACHE_ATTR_CACHE_ARCACHE_EN_SHIFT (2U) +/*! CACHE_ARCACHE_EN - Enable ARCACHE[1] override + * 0b0..Disable override ARCACHE[1] from ssi_slv_cache + * 0b1..enable override ARCACHE[1] from ssi_slv_cache + */ +#define BLK_CTRL_NIC_WRAPPER_CACHE_ATTR_CACHE_ARCACHE_EN(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NIC_WRAPPER_CACHE_ATTR_CACHE_ARCACHE_EN_SHIFT)) & BLK_CTRL_NIC_WRAPPER_CACHE_ATTR_CACHE_ARCACHE_EN_MASK) + +#define BLK_CTRL_NIC_WRAPPER_CACHE_ATTR_CACHE_AWCACHE_EN_MASK (0x8U) +#define BLK_CTRL_NIC_WRAPPER_CACHE_ATTR_CACHE_AWCACHE_EN_SHIFT (3U) +/*! CACHE_AWCACHE_EN - Enable AWCACHE[1] override + * 0b0..Disable override AWCACHE[1] from ssi_slv_cache + * 0b1..enable override AWCACHE[1] from ssi_slv_cache + */ +#define BLK_CTRL_NIC_WRAPPER_CACHE_ATTR_CACHE_AWCACHE_EN(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NIC_WRAPPER_CACHE_ATTR_CACHE_AWCACHE_EN_SHIFT)) & BLK_CTRL_NIC_WRAPPER_CACHE_ATTR_CACHE_AWCACHE_EN_MASK) + +#define BLK_CTRL_NIC_WRAPPER_CACHE_ATTR_HSIOMIX_ARCACHE_EN_MASK (0x10U) +#define BLK_CTRL_NIC_WRAPPER_CACHE_ATTR_HSIOMIX_ARCACHE_EN_SHIFT (4U) +/*! HSIOMIX_ARCACHE_EN - Enable ARCACHE[1] override + * 0b0..Disable override ARCACHE[1] from ssi_slv_hsiomix + * 0b1..enable override ARCACHE[1] from ssi_slv_hsiomix + */ +#define BLK_CTRL_NIC_WRAPPER_CACHE_ATTR_HSIOMIX_ARCACHE_EN(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NIC_WRAPPER_CACHE_ATTR_HSIOMIX_ARCACHE_EN_SHIFT)) & BLK_CTRL_NIC_WRAPPER_CACHE_ATTR_HSIOMIX_ARCACHE_EN_MASK) + +#define BLK_CTRL_NIC_WRAPPER_CACHE_ATTR_HSIOMIX_AWCACHE_EN_MASK (0x20U) +#define BLK_CTRL_NIC_WRAPPER_CACHE_ATTR_HSIOMIX_AWCACHE_EN_SHIFT (5U) +/*! HSIOMIX_AWCACHE_EN - Enable AWCACHE[1] override + * 0b0..Disable override AWCACHE[1] from ssi_slv_hsiomix + * 0b1..enable override AWCACHE[1] from ssi_slv_hsiomix + */ +#define BLK_CTRL_NIC_WRAPPER_CACHE_ATTR_HSIOMIX_AWCACHE_EN(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NIC_WRAPPER_CACHE_ATTR_HSIOMIX_AWCACHE_EN_SHIFT)) & BLK_CTRL_NIC_WRAPPER_CACHE_ATTR_HSIOMIX_AWCACHE_EN_MASK) + +#define BLK_CTRL_NIC_WRAPPER_CACHE_ATTR_WAKEUPMIX_ARCACHE_MASK (0x10000U) +#define BLK_CTRL_NIC_WRAPPER_CACHE_ATTR_WAKEUPMIX_ARCACHE_SHIFT (16U) +/*! WAKEUPMIX_ARCACHE - Override value + * 0b0..Override ARCACHE[1] from ssi_slv_wakeupmix to 0 + * 0b1..Override ARCACHE[1] from ssi_slv_wakeupmix to 1 + */ +#define BLK_CTRL_NIC_WRAPPER_CACHE_ATTR_WAKEUPMIX_ARCACHE(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NIC_WRAPPER_CACHE_ATTR_WAKEUPMIX_ARCACHE_SHIFT)) & BLK_CTRL_NIC_WRAPPER_CACHE_ATTR_WAKEUPMIX_ARCACHE_MASK) + +#define BLK_CTRL_NIC_WRAPPER_CACHE_ATTR_WAKEUPMIX_AWCACHE_MASK (0x20000U) +#define BLK_CTRL_NIC_WRAPPER_CACHE_ATTR_WAKEUPMIX_AWCACHE_SHIFT (17U) +/*! WAKEUPMIX_AWCACHE - Override value + * 0b0..Override AWCACHE[1] from ssi_slv_wakeupmix to 0 + * 0b1..Override AWCACHE[1] from ssi_slv_wakeupmix to 1 + */ +#define BLK_CTRL_NIC_WRAPPER_CACHE_ATTR_WAKEUPMIX_AWCACHE(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NIC_WRAPPER_CACHE_ATTR_WAKEUPMIX_AWCACHE_SHIFT)) & BLK_CTRL_NIC_WRAPPER_CACHE_ATTR_WAKEUPMIX_AWCACHE_MASK) + +#define BLK_CTRL_NIC_WRAPPER_CACHE_ATTR_CACHE_ARCACHE_MASK (0x40000U) +#define BLK_CTRL_NIC_WRAPPER_CACHE_ATTR_CACHE_ARCACHE_SHIFT (18U) +/*! CACHE_ARCACHE - Override value + * 0b0..Override ARCACHE[1] from ssi_slv_cache to 0 + * 0b1..Override ARCACHE[1] from ssi_slv_cache to 1 + */ +#define BLK_CTRL_NIC_WRAPPER_CACHE_ATTR_CACHE_ARCACHE(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NIC_WRAPPER_CACHE_ATTR_CACHE_ARCACHE_SHIFT)) & BLK_CTRL_NIC_WRAPPER_CACHE_ATTR_CACHE_ARCACHE_MASK) + +#define BLK_CTRL_NIC_WRAPPER_CACHE_ATTR_CACHE_AWCACHE_MASK (0x80000U) +#define BLK_CTRL_NIC_WRAPPER_CACHE_ATTR_CACHE_AWCACHE_SHIFT (19U) +/*! CACHE_AWCACHE - Override value + * 0b0..Override AWCACHE[1] from ssi_slv_cache to 0 + * 0b1..Override AWCACHE[1] from ssi_slv_cache to 1 + */ +#define BLK_CTRL_NIC_WRAPPER_CACHE_ATTR_CACHE_AWCACHE(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NIC_WRAPPER_CACHE_ATTR_CACHE_AWCACHE_SHIFT)) & BLK_CTRL_NIC_WRAPPER_CACHE_ATTR_CACHE_AWCACHE_MASK) + +#define BLK_CTRL_NIC_WRAPPER_CACHE_ATTR_HSIOMIX_ARCACHE_MASK (0x100000U) +#define BLK_CTRL_NIC_WRAPPER_CACHE_ATTR_HSIOMIX_ARCACHE_SHIFT (20U) +/*! HSIOMIX_ARCACHE - Override value + * 0b0..Override ARCACHE[1] from ssi_slv_hsiomix to 0 + * 0b1..Override ARCACHE[1] from ssi_slv_hsiomix to 1 + */ +#define BLK_CTRL_NIC_WRAPPER_CACHE_ATTR_HSIOMIX_ARCACHE(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NIC_WRAPPER_CACHE_ATTR_HSIOMIX_ARCACHE_SHIFT)) & BLK_CTRL_NIC_WRAPPER_CACHE_ATTR_HSIOMIX_ARCACHE_MASK) + +#define BLK_CTRL_NIC_WRAPPER_CACHE_ATTR_HSIOMIX_AWCACHE_MASK (0x200000U) +#define BLK_CTRL_NIC_WRAPPER_CACHE_ATTR_HSIOMIX_AWCACHE_SHIFT (21U) +/*! HSIOMIX_AWCACHE - Override value + * 0b0..Override AWCACHE[1] from ssi_slv_hsiomix to 0 + * 0b1..Override AWCACHE[1] from ssi_slv_hsiomix to 1 + */ +#define BLK_CTRL_NIC_WRAPPER_CACHE_ATTR_HSIOMIX_AWCACHE(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NIC_WRAPPER_CACHE_ATTR_HSIOMIX_AWCACHE_SHIFT)) & BLK_CTRL_NIC_WRAPPER_CACHE_ATTR_HSIOMIX_AWCACHE_MASK) +/*! @} */ + +/*! @name WAKEUPMIX_QOS - Configuration register for QoS value from wakeupmix */ +/*! @{ */ + +#define BLK_CTRL_NIC_WRAPPER_WAKEUPMIX_QOS_PANIC_AW_MASK (0xFU) +#define BLK_CTRL_NIC_WRAPPER_WAKEUPMIX_QOS_PANIC_AW_SHIFT (0U) +/*! PANIC_AW - Value of aw_qos_paNIC from wakeupmix */ +#define BLK_CTRL_NIC_WRAPPER_WAKEUPMIX_QOS_PANIC_AW(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NIC_WRAPPER_WAKEUPMIX_QOS_PANIC_AW_SHIFT)) & BLK_CTRL_NIC_WRAPPER_WAKEUPMIX_QOS_PANIC_AW_MASK) + +#define BLK_CTRL_NIC_WRAPPER_WAKEUPMIX_QOS_PANIC_AR_MASK (0xF0U) +#define BLK_CTRL_NIC_WRAPPER_WAKEUPMIX_QOS_PANIC_AR_SHIFT (4U) +/*! PANIC_AR - Value of ar_qos_paNIC from wakeupmix */ +#define BLK_CTRL_NIC_WRAPPER_WAKEUPMIX_QOS_PANIC_AR(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NIC_WRAPPER_WAKEUPMIX_QOS_PANIC_AR_SHIFT)) & BLK_CTRL_NIC_WRAPPER_WAKEUPMIX_QOS_PANIC_AR_MASK) +/*! @} */ + +/*! @name CACHE_QOS - Configuration register for QoS value from A55 */ +/*! @{ */ + +#define BLK_CTRL_NIC_WRAPPER_CACHE_QOS_PANIC_AW_MASK (0xFU) +#define BLK_CTRL_NIC_WRAPPER_CACHE_QOS_PANIC_AW_SHIFT (0U) +/*! PANIC_AW - Value of aw_qos_paNIC from A55 */ +#define BLK_CTRL_NIC_WRAPPER_CACHE_QOS_PANIC_AW(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NIC_WRAPPER_CACHE_QOS_PANIC_AW_SHIFT)) & BLK_CTRL_NIC_WRAPPER_CACHE_QOS_PANIC_AW_MASK) + +#define BLK_CTRL_NIC_WRAPPER_CACHE_QOS_PANIC_AR_MASK (0xF0U) +#define BLK_CTRL_NIC_WRAPPER_CACHE_QOS_PANIC_AR_SHIFT (4U) +/*! PANIC_AR - Value of ar_qos_paNIC from A55 */ +#define BLK_CTRL_NIC_WRAPPER_CACHE_QOS_PANIC_AR(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NIC_WRAPPER_CACHE_QOS_PANIC_AR_SHIFT)) & BLK_CTRL_NIC_WRAPPER_CACHE_QOS_PANIC_AR_MASK) + +#define BLK_CTRL_NIC_WRAPPER_CACHE_QOS_DEFAULT_AW_MASK (0xF0000U) +#define BLK_CTRL_NIC_WRAPPER_CACHE_QOS_DEFAULT_AW_SHIFT (16U) +/*! DEFAULT_AW - Value of aw_qos_default from A55 */ +#define BLK_CTRL_NIC_WRAPPER_CACHE_QOS_DEFAULT_AW(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NIC_WRAPPER_CACHE_QOS_DEFAULT_AW_SHIFT)) & BLK_CTRL_NIC_WRAPPER_CACHE_QOS_DEFAULT_AW_MASK) + +#define BLK_CTRL_NIC_WRAPPER_CACHE_QOS_DEFAULT_AR_MASK (0xF00000U) +#define BLK_CTRL_NIC_WRAPPER_CACHE_QOS_DEFAULT_AR_SHIFT (20U) +/*! DEFAULT_AR - Value of ar_qos_default from A55 */ +#define BLK_CTRL_NIC_WRAPPER_CACHE_QOS_DEFAULT_AR(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NIC_WRAPPER_CACHE_QOS_DEFAULT_AR_SHIFT)) & BLK_CTRL_NIC_WRAPPER_CACHE_QOS_DEFAULT_AR_MASK) +/*! @} */ + +/*! @name HSIOMIX_QOS - Configuration register for QoS value from hsiomix */ +/*! @{ */ + +#define BLK_CTRL_NIC_WRAPPER_HSIOMIX_QOS_PANIC_AW_MASK (0xFU) +#define BLK_CTRL_NIC_WRAPPER_HSIOMIX_QOS_PANIC_AW_SHIFT (0U) +/*! PANIC_AW - Value of aw_qos_paNIC from hsiomix */ +#define BLK_CTRL_NIC_WRAPPER_HSIOMIX_QOS_PANIC_AW(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NIC_WRAPPER_HSIOMIX_QOS_PANIC_AW_SHIFT)) & BLK_CTRL_NIC_WRAPPER_HSIOMIX_QOS_PANIC_AW_MASK) + +#define BLK_CTRL_NIC_WRAPPER_HSIOMIX_QOS_PANIC_AR_MASK (0xF0U) +#define BLK_CTRL_NIC_WRAPPER_HSIOMIX_QOS_PANIC_AR_SHIFT (4U) +/*! PANIC_AR - Value of ar_qos_paNIC from hsiomix */ +#define BLK_CTRL_NIC_WRAPPER_HSIOMIX_QOS_PANIC_AR(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NIC_WRAPPER_HSIOMIX_QOS_PANIC_AR_SHIFT)) & BLK_CTRL_NIC_WRAPPER_HSIOMIX_QOS_PANIC_AR_MASK) + +#define BLK_CTRL_NIC_WRAPPER_HSIOMIX_QOS_DEFAULT_AW_MASK (0xF0000U) +#define BLK_CTRL_NIC_WRAPPER_HSIOMIX_QOS_DEFAULT_AW_SHIFT (16U) +/*! DEFAULT_AW - Value of aw_qos_default from hsiomix */ +#define BLK_CTRL_NIC_WRAPPER_HSIOMIX_QOS_DEFAULT_AW(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NIC_WRAPPER_HSIOMIX_QOS_DEFAULT_AW_SHIFT)) & BLK_CTRL_NIC_WRAPPER_HSIOMIX_QOS_DEFAULT_AW_MASK) + +#define BLK_CTRL_NIC_WRAPPER_HSIOMIX_QOS_DEFAULT_AR_MASK (0xF00000U) +#define BLK_CTRL_NIC_WRAPPER_HSIOMIX_QOS_DEFAULT_AR_SHIFT (20U) +/*! DEFAULT_AR - Value of ar_qos_default from hsiomix */ +#define BLK_CTRL_NIC_WRAPPER_HSIOMIX_QOS_DEFAULT_AR(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NIC_WRAPPER_HSIOMIX_QOS_DEFAULT_AR_SHIFT)) & BLK_CTRL_NIC_WRAPPER_HSIOMIX_QOS_DEFAULT_AR_MASK) +/*! @} */ + +/*! @name TIE_VALUE - GPR for uncertain tie0 or tie1 */ +/*! @{ */ + +#define BLK_CTRL_NIC_WRAPPER_TIE_VALUE_AIPS4_HBSTRB_MASK (0xFU) +#define BLK_CTRL_NIC_WRAPPER_TIE_VALUE_AIPS4_HBSTRB_SHIFT (0U) +/*! AIPS4_HBSTRB - Value of aips4.hbstrb */ +#define BLK_CTRL_NIC_WRAPPER_TIE_VALUE_AIPS4_HBSTRB(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NIC_WRAPPER_TIE_VALUE_AIPS4_HBSTRB_SHIFT)) & BLK_CTRL_NIC_WRAPPER_TIE_VALUE_AIPS4_HBSTRB_MASK) + +#define BLK_CTRL_NIC_WRAPPER_TIE_VALUE_XCPT_RTN_MASK (0x30U) +#define BLK_CTRL_NIC_WRAPPER_TIE_VALUE_XCPT_RTN_SHIFT (4U) +/*! XCPT_RTN - Dac_cache_r.xcpt_rtn and dac_cache_w.xcpt_rtn */ +#define BLK_CTRL_NIC_WRAPPER_TIE_VALUE_XCPT_RTN(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NIC_WRAPPER_TIE_VALUE_XCPT_RTN_SHIFT)) & BLK_CTRL_NIC_WRAPPER_TIE_VALUE_XCPT_RTN_MASK) + +#define BLK_CTRL_NIC_WRAPPER_TIE_VALUE_GICT_ALLOW_NS_MASK (0x40U) +#define BLK_CTRL_NIC_WRAPPER_TIE_VALUE_GICT_ALLOW_NS_SHIFT (6U) +/*! GICT_ALLOW_NS - GIC600.gict_allow_ns */ +#define BLK_CTRL_NIC_WRAPPER_TIE_VALUE_GICT_ALLOW_NS(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NIC_WRAPPER_TIE_VALUE_GICT_ALLOW_NS_SHIFT)) & BLK_CTRL_NIC_WRAPPER_TIE_VALUE_GICT_ALLOW_NS_MASK) + +#define BLK_CTRL_NIC_WRAPPER_TIE_VALUE_GICP_ALLOW_NS_MASK (0x80U) +#define BLK_CTRL_NIC_WRAPPER_TIE_VALUE_GICP_ALLOW_NS_SHIFT (7U) +/*! GICP_ALLOW_NS - GIC600.gicp_allow_ns */ +#define BLK_CTRL_NIC_WRAPPER_TIE_VALUE_GICP_ALLOW_NS(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NIC_WRAPPER_TIE_VALUE_GICP_ALLOW_NS_SHIFT)) & BLK_CTRL_NIC_WRAPPER_TIE_VALUE_GICP_ALLOW_NS_MASK) + +#define BLK_CTRL_NIC_WRAPPER_TIE_VALUE_ARBAR_S_MASK (0x300U) +#define BLK_CTRL_NIC_WRAPPER_TIE_VALUE_ARBAR_S_SHIFT (8U) +/*! ARBAR_S - GIC600.ARBAR_S */ +#define BLK_CTRL_NIC_WRAPPER_TIE_VALUE_ARBAR_S(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NIC_WRAPPER_TIE_VALUE_ARBAR_S_SHIFT)) & BLK_CTRL_NIC_WRAPPER_TIE_VALUE_ARBAR_S_MASK) + +#define BLK_CTRL_NIC_WRAPPER_TIE_VALUE_AWBAR_S_MASK (0xC00U) +#define BLK_CTRL_NIC_WRAPPER_TIE_VALUE_AWBAR_S_SHIFT (10U) +/*! AWBAR_S - GIC600.AWBAR_S */ +#define BLK_CTRL_NIC_WRAPPER_TIE_VALUE_AWBAR_S(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NIC_WRAPPER_TIE_VALUE_AWBAR_S_SHIFT)) & BLK_CTRL_NIC_WRAPPER_TIE_VALUE_AWBAR_S_MASK) + +#define BLK_CTRL_NIC_WRAPPER_TIE_VALUE_ARUSER_S_MASK (0x7000U) +#define BLK_CTRL_NIC_WRAPPER_TIE_VALUE_ARUSER_S_SHIFT (12U) +/*! ARUSER_S - GIC600.ARUSER_S */ +#define BLK_CTRL_NIC_WRAPPER_TIE_VALUE_ARUSER_S(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NIC_WRAPPER_TIE_VALUE_ARUSER_S_SHIFT)) & BLK_CTRL_NIC_WRAPPER_TIE_VALUE_ARUSER_S_MASK) + +#define BLK_CTRL_NIC_WRAPPER_TIE_VALUE_AWUSER_S_MASK (0x38000U) +#define BLK_CTRL_NIC_WRAPPER_TIE_VALUE_AWUSER_S_SHIFT (15U) +/*! AWUSER_S - GIC600.AWUSER_S */ +#define BLK_CTRL_NIC_WRAPPER_TIE_VALUE_AWUSER_S(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NIC_WRAPPER_TIE_VALUE_AWUSER_S_SHIFT)) & BLK_CTRL_NIC_WRAPPER_TIE_VALUE_AWUSER_S_MASK) + +#define BLK_CTRL_NIC_WRAPPER_TIE_VALUE_ARSNOOP_S_MASK (0x3C0000U) +#define BLK_CTRL_NIC_WRAPPER_TIE_VALUE_ARSNOOP_S_SHIFT (18U) +/*! ARSNOOP_S - GIC600.arsnoop_s */ +#define BLK_CTRL_NIC_WRAPPER_TIE_VALUE_ARSNOOP_S(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NIC_WRAPPER_TIE_VALUE_ARSNOOP_S_SHIFT)) & BLK_CTRL_NIC_WRAPPER_TIE_VALUE_ARSNOOP_S_MASK) + +#define BLK_CTRL_NIC_WRAPPER_TIE_VALUE_AWSNOOP_S_MASK (0x1C00000U) +#define BLK_CTRL_NIC_WRAPPER_TIE_VALUE_AWSNOOP_S_SHIFT (22U) +/*! AWSNOOP_S - GIC600.awsnoop_s */ +#define BLK_CTRL_NIC_WRAPPER_TIE_VALUE_AWSNOOP_S(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NIC_WRAPPER_TIE_VALUE_AWSNOOP_S_SHIFT)) & BLK_CTRL_NIC_WRAPPER_TIE_VALUE_AWSNOOP_S_MASK) + +#define BLK_CTRL_NIC_WRAPPER_TIE_VALUE_HPROT_GPV_CENTRAL_MASK (0x1E000000U) +#define BLK_CTRL_NIC_WRAPPER_TIE_VALUE_HPROT_GPV_CENTRAL_SHIFT (25U) +/*! HPROT_GPV_CENTRAL - NIC400_central.HPROT_gpv_central */ +#define BLK_CTRL_NIC_WRAPPER_TIE_VALUE_HPROT_GPV_CENTRAL(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NIC_WRAPPER_TIE_VALUE_HPROT_GPV_CENTRAL_SHIFT)) & BLK_CTRL_NIC_WRAPPER_TIE_VALUE_HPROT_GPV_CENTRAL_MASK) + +#define BLK_CTRL_NIC_WRAPPER_TIE_VALUE_DFTRAMHOLD_MASK (0x20000000U) +#define BLK_CTRL_NIC_WRAPPER_TIE_VALUE_DFTRAMHOLD_SHIFT (29U) +/*! DFTRAMHOLD - GIC600.dftramhold */ +#define BLK_CTRL_NIC_WRAPPER_TIE_VALUE_DFTRAMHOLD(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NIC_WRAPPER_TIE_VALUE_DFTRAMHOLD_SHIFT)) & BLK_CTRL_NIC_WRAPPER_TIE_VALUE_DFTRAMHOLD_MASK) +/*! @} */ + +/*! @name OCRAM_SGLECC_ERR_INT - OCRAM single ECC error interrupt flag */ +/*! @{ */ + +#define BLK_CTRL_NIC_WRAPPER_OCRAM_SGLECC_ERR_INT_SGL_ECC_ERR_IF_MASK (0x1U) +#define BLK_CTRL_NIC_WRAPPER_OCRAM_SGLECC_ERR_INT_SGL_ECC_ERR_IF_SHIFT (0U) +/*! SGL_ECC_ERR_IF - OCRAM single ECC error interrupt flag */ +#define BLK_CTRL_NIC_WRAPPER_OCRAM_SGLECC_ERR_INT_SGL_ECC_ERR_IF(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NIC_WRAPPER_OCRAM_SGLECC_ERR_INT_SGL_ECC_ERR_IF_SHIFT)) & BLK_CTRL_NIC_WRAPPER_OCRAM_SGLECC_ERR_INT_SGL_ECC_ERR_IF_MASK) +/*! @} */ + +/*! @name SSI_MST_DDRMIX - low power control for SSI_MST_DDRMIX */ +/*! @{ */ + +#define BLK_CTRL_NIC_WRAPPER_SSI_MST_DDRMIX_idle_MASK (0x1U) +#define BLK_CTRL_NIC_WRAPPER_SSI_MST_DDRMIX_idle_SHIFT (0U) +#define BLK_CTRL_NIC_WRAPPER_SSI_MST_DDRMIX_idle(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NIC_WRAPPER_SSI_MST_DDRMIX_idle_SHIFT)) & BLK_CTRL_NIC_WRAPPER_SSI_MST_DDRMIX_idle_MASK) + +#define BLK_CTRL_NIC_WRAPPER_SSI_MST_DDRMIX_pause_MASK (0x4U) +#define BLK_CTRL_NIC_WRAPPER_SSI_MST_DDRMIX_pause_SHIFT (2U) +#define BLK_CTRL_NIC_WRAPPER_SSI_MST_DDRMIX_pause(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NIC_WRAPPER_SSI_MST_DDRMIX_pause_SHIFT)) & BLK_CTRL_NIC_WRAPPER_SSI_MST_DDRMIX_pause_MASK) + +#define BLK_CTRL_NIC_WRAPPER_SSI_MST_DDRMIX_black_hole_mode_b_MASK (0x8U) +#define BLK_CTRL_NIC_WRAPPER_SSI_MST_DDRMIX_black_hole_mode_b_SHIFT (3U) +#define BLK_CTRL_NIC_WRAPPER_SSI_MST_DDRMIX_black_hole_mode_b(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NIC_WRAPPER_SSI_MST_DDRMIX_black_hole_mode_b_SHIFT)) & BLK_CTRL_NIC_WRAPPER_SSI_MST_DDRMIX_black_hole_mode_b_MASK) + +#define BLK_CTRL_NIC_WRAPPER_SSI_MST_DDRMIX_power_control_MASK (0x10U) +#define BLK_CTRL_NIC_WRAPPER_SSI_MST_DDRMIX_power_control_SHIFT (4U) +#define BLK_CTRL_NIC_WRAPPER_SSI_MST_DDRMIX_power_control(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NIC_WRAPPER_SSI_MST_DDRMIX_power_control_SHIFT)) & BLK_CTRL_NIC_WRAPPER_SSI_MST_DDRMIX_power_control_MASK) + +#define BLK_CTRL_NIC_WRAPPER_SSI_MST_DDRMIX_iso_control_MASK (0x20U) +#define BLK_CTRL_NIC_WRAPPER_SSI_MST_DDRMIX_iso_control_SHIFT (5U) +#define BLK_CTRL_NIC_WRAPPER_SSI_MST_DDRMIX_iso_control(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NIC_WRAPPER_SSI_MST_DDRMIX_iso_control_SHIFT)) & BLK_CTRL_NIC_WRAPPER_SSI_MST_DDRMIX_iso_control_MASK) +/*! @} */ + +/*! @name SSI_MST_GIC600 - low power control for SSI_MST_GIC600 */ +/*! @{ */ + +#define BLK_CTRL_NIC_WRAPPER_SSI_MST_GIC600_idle_MASK (0x1U) +#define BLK_CTRL_NIC_WRAPPER_SSI_MST_GIC600_idle_SHIFT (0U) +#define BLK_CTRL_NIC_WRAPPER_SSI_MST_GIC600_idle(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NIC_WRAPPER_SSI_MST_GIC600_idle_SHIFT)) & BLK_CTRL_NIC_WRAPPER_SSI_MST_GIC600_idle_MASK) + +#define BLK_CTRL_NIC_WRAPPER_SSI_MST_GIC600_pause_MASK (0x4U) +#define BLK_CTRL_NIC_WRAPPER_SSI_MST_GIC600_pause_SHIFT (2U) +#define BLK_CTRL_NIC_WRAPPER_SSI_MST_GIC600_pause(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NIC_WRAPPER_SSI_MST_GIC600_pause_SHIFT)) & BLK_CTRL_NIC_WRAPPER_SSI_MST_GIC600_pause_MASK) + +#define BLK_CTRL_NIC_WRAPPER_SSI_MST_GIC600_power_control_MASK (0x10U) +#define BLK_CTRL_NIC_WRAPPER_SSI_MST_GIC600_power_control_SHIFT (4U) +#define BLK_CTRL_NIC_WRAPPER_SSI_MST_GIC600_power_control(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NIC_WRAPPER_SSI_MST_GIC600_power_control_SHIFT)) & BLK_CTRL_NIC_WRAPPER_SSI_MST_GIC600_power_control_MASK) + +#define BLK_CTRL_NIC_WRAPPER_SSI_MST_GIC600_iso_control_MASK (0x20U) +#define BLK_CTRL_NIC_WRAPPER_SSI_MST_GIC600_iso_control_SHIFT (5U) +#define BLK_CTRL_NIC_WRAPPER_SSI_MST_GIC600_iso_control(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NIC_WRAPPER_SSI_MST_GIC600_iso_control_SHIFT)) & BLK_CTRL_NIC_WRAPPER_SSI_MST_GIC600_iso_control_MASK) +/*! @} */ + +/*! @name SSI_MST_WAKEUPMIX - low power control for SSI_MST_WAKEUPMIX */ +/*! @{ */ + +#define BLK_CTRL_NIC_WRAPPER_SSI_MST_WAKEUPMIX_idle_MASK (0x1U) +#define BLK_CTRL_NIC_WRAPPER_SSI_MST_WAKEUPMIX_idle_SHIFT (0U) +#define BLK_CTRL_NIC_WRAPPER_SSI_MST_WAKEUPMIX_idle(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NIC_WRAPPER_SSI_MST_WAKEUPMIX_idle_SHIFT)) & BLK_CTRL_NIC_WRAPPER_SSI_MST_WAKEUPMIX_idle_MASK) + +#define BLK_CTRL_NIC_WRAPPER_SSI_MST_WAKEUPMIX_pause_MASK (0x4U) +#define BLK_CTRL_NIC_WRAPPER_SSI_MST_WAKEUPMIX_pause_SHIFT (2U) +#define BLK_CTRL_NIC_WRAPPER_SSI_MST_WAKEUPMIX_pause(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NIC_WRAPPER_SSI_MST_WAKEUPMIX_pause_SHIFT)) & BLK_CTRL_NIC_WRAPPER_SSI_MST_WAKEUPMIX_pause_MASK) + +#define BLK_CTRL_NIC_WRAPPER_SSI_MST_WAKEUPMIX_black_hole_mode_b_MASK (0x8U) +#define BLK_CTRL_NIC_WRAPPER_SSI_MST_WAKEUPMIX_black_hole_mode_b_SHIFT (3U) +#define BLK_CTRL_NIC_WRAPPER_SSI_MST_WAKEUPMIX_black_hole_mode_b(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NIC_WRAPPER_SSI_MST_WAKEUPMIX_black_hole_mode_b_SHIFT)) & BLK_CTRL_NIC_WRAPPER_SSI_MST_WAKEUPMIX_black_hole_mode_b_MASK) + +#define BLK_CTRL_NIC_WRAPPER_SSI_MST_WAKEUPMIX_power_control_MASK (0x10U) +#define BLK_CTRL_NIC_WRAPPER_SSI_MST_WAKEUPMIX_power_control_SHIFT (4U) +#define BLK_CTRL_NIC_WRAPPER_SSI_MST_WAKEUPMIX_power_control(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NIC_WRAPPER_SSI_MST_WAKEUPMIX_power_control_SHIFT)) & BLK_CTRL_NIC_WRAPPER_SSI_MST_WAKEUPMIX_power_control_MASK) + +#define BLK_CTRL_NIC_WRAPPER_SSI_MST_WAKEUPMIX_iso_control_MASK (0x20U) +#define BLK_CTRL_NIC_WRAPPER_SSI_MST_WAKEUPMIX_iso_control_SHIFT (5U) +#define BLK_CTRL_NIC_WRAPPER_SSI_MST_WAKEUPMIX_iso_control(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NIC_WRAPPER_SSI_MST_WAKEUPMIX_iso_control_SHIFT)) & BLK_CTRL_NIC_WRAPPER_SSI_MST_WAKEUPMIX_iso_control_MASK) +/*! @} */ + +/*! @name SSI_SLV_CACHE - low power control for SSI_SLV_CACHE */ +/*! @{ */ + +#define BLK_CTRL_NIC_WRAPPER_SSI_SLV_CACHE_idle_MASK (0x3U) +#define BLK_CTRL_NIC_WRAPPER_SSI_SLV_CACHE_idle_SHIFT (0U) +#define BLK_CTRL_NIC_WRAPPER_SSI_SLV_CACHE_idle(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NIC_WRAPPER_SSI_SLV_CACHE_idle_SHIFT)) & BLK_CTRL_NIC_WRAPPER_SSI_SLV_CACHE_idle_MASK) + +#define BLK_CTRL_NIC_WRAPPER_SSI_SLV_CACHE_pause_MASK (0x4U) +#define BLK_CTRL_NIC_WRAPPER_SSI_SLV_CACHE_pause_SHIFT (2U) +#define BLK_CTRL_NIC_WRAPPER_SSI_SLV_CACHE_pause(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NIC_WRAPPER_SSI_SLV_CACHE_pause_SHIFT)) & BLK_CTRL_NIC_WRAPPER_SSI_SLV_CACHE_pause_MASK) + +#define BLK_CTRL_NIC_WRAPPER_SSI_SLV_CACHE_black_hole_mode_b_MASK (0x8U) +#define BLK_CTRL_NIC_WRAPPER_SSI_SLV_CACHE_black_hole_mode_b_SHIFT (3U) +#define BLK_CTRL_NIC_WRAPPER_SSI_SLV_CACHE_black_hole_mode_b(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NIC_WRAPPER_SSI_SLV_CACHE_black_hole_mode_b_SHIFT)) & BLK_CTRL_NIC_WRAPPER_SSI_SLV_CACHE_black_hole_mode_b_MASK) + +#define BLK_CTRL_NIC_WRAPPER_SSI_SLV_CACHE_power_control_MASK (0x10U) +#define BLK_CTRL_NIC_WRAPPER_SSI_SLV_CACHE_power_control_SHIFT (4U) +#define BLK_CTRL_NIC_WRAPPER_SSI_SLV_CACHE_power_control(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NIC_WRAPPER_SSI_SLV_CACHE_power_control_SHIFT)) & BLK_CTRL_NIC_WRAPPER_SSI_SLV_CACHE_power_control_MASK) + +#define BLK_CTRL_NIC_WRAPPER_SSI_SLV_CACHE_iso_control_MASK (0x20U) +#define BLK_CTRL_NIC_WRAPPER_SSI_SLV_CACHE_iso_control_SHIFT (5U) +#define BLK_CTRL_NIC_WRAPPER_SSI_SLV_CACHE_iso_control(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NIC_WRAPPER_SSI_SLV_CACHE_iso_control_SHIFT)) & BLK_CTRL_NIC_WRAPPER_SSI_SLV_CACHE_iso_control_MASK) +/*! @} */ + +/*! @name SSI_SLV_GIC600 - low power control for SSI_SLV_GIC600 */ +/*! @{ */ + +#define BLK_CTRL_NIC_WRAPPER_SSI_SLV_GIC600_power_control_MASK (0x10U) +#define BLK_CTRL_NIC_WRAPPER_SSI_SLV_GIC600_power_control_SHIFT (4U) +#define BLK_CTRL_NIC_WRAPPER_SSI_SLV_GIC600_power_control(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NIC_WRAPPER_SSI_SLV_GIC600_power_control_SHIFT)) & BLK_CTRL_NIC_WRAPPER_SSI_SLV_GIC600_power_control_MASK) + +#define BLK_CTRL_NIC_WRAPPER_SSI_SLV_GIC600_iso_control_MASK (0x20U) +#define BLK_CTRL_NIC_WRAPPER_SSI_SLV_GIC600_iso_control_SHIFT (5U) +#define BLK_CTRL_NIC_WRAPPER_SSI_SLV_GIC600_iso_control(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NIC_WRAPPER_SSI_SLV_GIC600_iso_control_SHIFT)) & BLK_CTRL_NIC_WRAPPER_SSI_SLV_GIC600_iso_control_MASK) +/*! @} */ + +/*! @name SSI_SLV_HSIOMIX - low power control for SSI_SLV_HSIOMIX */ +/*! @{ */ + +#define BLK_CTRL_NIC_WRAPPER_SSI_SLV_HSIOMIX_idle_MASK (0x3U) +#define BLK_CTRL_NIC_WRAPPER_SSI_SLV_HSIOMIX_idle_SHIFT (0U) +#define BLK_CTRL_NIC_WRAPPER_SSI_SLV_HSIOMIX_idle(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NIC_WRAPPER_SSI_SLV_HSIOMIX_idle_SHIFT)) & BLK_CTRL_NIC_WRAPPER_SSI_SLV_HSIOMIX_idle_MASK) + +#define BLK_CTRL_NIC_WRAPPER_SSI_SLV_HSIOMIX_pause_MASK (0x4U) +#define BLK_CTRL_NIC_WRAPPER_SSI_SLV_HSIOMIX_pause_SHIFT (2U) +#define BLK_CTRL_NIC_WRAPPER_SSI_SLV_HSIOMIX_pause(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NIC_WRAPPER_SSI_SLV_HSIOMIX_pause_SHIFT)) & BLK_CTRL_NIC_WRAPPER_SSI_SLV_HSIOMIX_pause_MASK) + +#define BLK_CTRL_NIC_WRAPPER_SSI_SLV_HSIOMIX_black_hole_mode_b_MASK (0x8U) +#define BLK_CTRL_NIC_WRAPPER_SSI_SLV_HSIOMIX_black_hole_mode_b_SHIFT (3U) +#define BLK_CTRL_NIC_WRAPPER_SSI_SLV_HSIOMIX_black_hole_mode_b(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NIC_WRAPPER_SSI_SLV_HSIOMIX_black_hole_mode_b_SHIFT)) & BLK_CTRL_NIC_WRAPPER_SSI_SLV_HSIOMIX_black_hole_mode_b_MASK) + +#define BLK_CTRL_NIC_WRAPPER_SSI_SLV_HSIOMIX_power_control_MASK (0x10U) +#define BLK_CTRL_NIC_WRAPPER_SSI_SLV_HSIOMIX_power_control_SHIFT (4U) +#define BLK_CTRL_NIC_WRAPPER_SSI_SLV_HSIOMIX_power_control(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NIC_WRAPPER_SSI_SLV_HSIOMIX_power_control_SHIFT)) & BLK_CTRL_NIC_WRAPPER_SSI_SLV_HSIOMIX_power_control_MASK) + +#define BLK_CTRL_NIC_WRAPPER_SSI_SLV_HSIOMIX_iso_control_MASK (0x20U) +#define BLK_CTRL_NIC_WRAPPER_SSI_SLV_HSIOMIX_iso_control_SHIFT (5U) +#define BLK_CTRL_NIC_WRAPPER_SSI_SLV_HSIOMIX_iso_control(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NIC_WRAPPER_SSI_SLV_HSIOMIX_iso_control_SHIFT)) & BLK_CTRL_NIC_WRAPPER_SSI_SLV_HSIOMIX_iso_control_MASK) +/*! @} */ + +/*! @name SSI_SLV_MEDIAMIX - low power control for SSI_SLV_MEDIAMIX */ +/*! @{ */ + +#define BLK_CTRL_NIC_WRAPPER_SSI_SLV_MEDIAMIX_idle_MASK (0x3U) +#define BLK_CTRL_NIC_WRAPPER_SSI_SLV_MEDIAMIX_idle_SHIFT (0U) +#define BLK_CTRL_NIC_WRAPPER_SSI_SLV_MEDIAMIX_idle(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NIC_WRAPPER_SSI_SLV_MEDIAMIX_idle_SHIFT)) & BLK_CTRL_NIC_WRAPPER_SSI_SLV_MEDIAMIX_idle_MASK) + +#define BLK_CTRL_NIC_WRAPPER_SSI_SLV_MEDIAMIX_pause_MASK (0x4U) +#define BLK_CTRL_NIC_WRAPPER_SSI_SLV_MEDIAMIX_pause_SHIFT (2U) +#define BLK_CTRL_NIC_WRAPPER_SSI_SLV_MEDIAMIX_pause(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NIC_WRAPPER_SSI_SLV_MEDIAMIX_pause_SHIFT)) & BLK_CTRL_NIC_WRAPPER_SSI_SLV_MEDIAMIX_pause_MASK) + +#define BLK_CTRL_NIC_WRAPPER_SSI_SLV_MEDIAMIX_black_hole_mode_b_MASK (0x8U) +#define BLK_CTRL_NIC_WRAPPER_SSI_SLV_MEDIAMIX_black_hole_mode_b_SHIFT (3U) +#define BLK_CTRL_NIC_WRAPPER_SSI_SLV_MEDIAMIX_black_hole_mode_b(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NIC_WRAPPER_SSI_SLV_MEDIAMIX_black_hole_mode_b_SHIFT)) & BLK_CTRL_NIC_WRAPPER_SSI_SLV_MEDIAMIX_black_hole_mode_b_MASK) + +#define BLK_CTRL_NIC_WRAPPER_SSI_SLV_MEDIAMIX_power_control_MASK (0x10U) +#define BLK_CTRL_NIC_WRAPPER_SSI_SLV_MEDIAMIX_power_control_SHIFT (4U) +#define BLK_CTRL_NIC_WRAPPER_SSI_SLV_MEDIAMIX_power_control(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NIC_WRAPPER_SSI_SLV_MEDIAMIX_power_control_SHIFT)) & BLK_CTRL_NIC_WRAPPER_SSI_SLV_MEDIAMIX_power_control_MASK) + +#define BLK_CTRL_NIC_WRAPPER_SSI_SLV_MEDIAMIX_iso_control_MASK (0x20U) +#define BLK_CTRL_NIC_WRAPPER_SSI_SLV_MEDIAMIX_iso_control_SHIFT (5U) +#define BLK_CTRL_NIC_WRAPPER_SSI_SLV_MEDIAMIX_iso_control(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NIC_WRAPPER_SSI_SLV_MEDIAMIX_iso_control_SHIFT)) & BLK_CTRL_NIC_WRAPPER_SSI_SLV_MEDIAMIX_iso_control_MASK) +/*! @} */ + +/*! @name SSI_SLV_WAKEUPMIX - low power control for SSI_SLV_WAKEUPMIX */ +/*! @{ */ + +#define BLK_CTRL_NIC_WRAPPER_SSI_SLV_WAKEUPMIX_idle_MASK (0x1U) +#define BLK_CTRL_NIC_WRAPPER_SSI_SLV_WAKEUPMIX_idle_SHIFT (0U) +#define BLK_CTRL_NIC_WRAPPER_SSI_SLV_WAKEUPMIX_idle(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NIC_WRAPPER_SSI_SLV_WAKEUPMIX_idle_SHIFT)) & BLK_CTRL_NIC_WRAPPER_SSI_SLV_WAKEUPMIX_idle_MASK) + +#define BLK_CTRL_NIC_WRAPPER_SSI_SLV_WAKEUPMIX_power_control_MASK (0x10U) +#define BLK_CTRL_NIC_WRAPPER_SSI_SLV_WAKEUPMIX_power_control_SHIFT (4U) +#define BLK_CTRL_NIC_WRAPPER_SSI_SLV_WAKEUPMIX_power_control(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NIC_WRAPPER_SSI_SLV_WAKEUPMIX_power_control_SHIFT)) & BLK_CTRL_NIC_WRAPPER_SSI_SLV_WAKEUPMIX_power_control_MASK) + +#define BLK_CTRL_NIC_WRAPPER_SSI_SLV_WAKEUPMIX_iso_control_MASK (0x20U) +#define BLK_CTRL_NIC_WRAPPER_SSI_SLV_WAKEUPMIX_iso_control_SHIFT (5U) +#define BLK_CTRL_NIC_WRAPPER_SSI_SLV_WAKEUPMIX_iso_control(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NIC_WRAPPER_SSI_SLV_WAKEUPMIX_iso_control_SHIFT)) & BLK_CTRL_NIC_WRAPPER_SSI_SLV_WAKEUPMIX_iso_control_MASK) +/*! @} */ + +/*! @name REG_RW - reserved */ +/*! @{ */ + +#define BLK_CTRL_NIC_WRAPPER_REG_RW_z_cell_MASK (0xFFFFFFFFU) +#define BLK_CTRL_NIC_WRAPPER_REG_RW_z_cell_SHIFT (0U) +#define BLK_CTRL_NIC_WRAPPER_REG_RW_z_cell(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NIC_WRAPPER_REG_RW_z_cell_SHIFT)) & BLK_CTRL_NIC_WRAPPER_REG_RW_z_cell_MASK) +/*! @} */ + +/*! @name REG_RO - reserved */ +/*! @{ */ + +#define BLK_CTRL_NIC_WRAPPER_REG_RO_z_cell_MASK (0xFFFFFFFFU) +#define BLK_CTRL_NIC_WRAPPER_REG_RO_z_cell_SHIFT (0U) +#define BLK_CTRL_NIC_WRAPPER_REG_RO_z_cell(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NIC_WRAPPER_REG_RO_z_cell_SHIFT)) & BLK_CTRL_NIC_WRAPPER_REG_RO_z_cell_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group BLK_CTRL_NIC_WRAPPER_Register_Masks */ + + +/* BLK_CTRL_NIC_WRAPPER - Peripheral instance base addresses */ +/** Peripheral BLK_CTRL_NIC_WRAPPER1 base address */ +#define BLK_CTRL_NIC_WRAPPER1_BASE (0x49000000u) +/** Peripheral BLK_CTRL_NIC_WRAPPER1 base pointer */ +#define BLK_CTRL_NIC_WRAPPER1 ((BLK_CTRL_NIC_WRAPPER_Type *)BLK_CTRL_NIC_WRAPPER1_BASE) +/** Array initializer of BLK_CTRL_NIC_WRAPPER peripheral base addresses */ +#define BLK_CTRL_NIC_WRAPPER_BASE_ADDRS { BLK_CTRL_NIC_WRAPPER1_BASE } +/** Array initializer of BLK_CTRL_NIC_WRAPPER peripheral base pointers */ +#define BLK_CTRL_NIC_WRAPPER_BASE_PTRS { BLK_CTRL_NIC_WRAPPER1 } + +/*! + * @} + */ /* end of group BLK_CTRL_NIC_WRAPPER_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- BLK_CTRL_NS_AONMIX Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup BLK_CTRL_NS_AONMIX_Peripheral_Access_Layer BLK_CTRL_NS_AONMIX Peripheral Access Layer + * @{ + */ + +/** BLK_CTRL_NS_AONMIX - Register Layout Typedef */ +typedef struct { + uint8_t RESERVED_0[12]; + __IO uint32_t IPG_DEBUG_CA55C0; /**< IPG DEBUG MASK BIT CA55 CORE0, offset: 0xC */ + uint8_t RESERVED_1[4]; + __IO uint32_t LP_HANDSHAKE; /**< LP HANDSHAKE, offset: 0x14 */ + uint8_t RESERVED_2[8]; + __IO uint32_t MQS_SETTINGS; /**< MQS settings., offset: 0x20 */ + uint8_t RESERVED_3[4]; + __I uint32_t FUSE_ACC_DIS; /**< Read-only version of the OCOTP fuse-access-disable bit, offset: 0x28 */ + uint8_t RESERVED_4[4]; + __I uint32_t OCOTP_FUSE_DATA0; /**< Read-only version of OCOTP fusedata_mtr_cfg_0, offset: 0x30 */ + __I uint32_t OCOTP_FUSE_DATA1; /**< Read-only version of OCOTP fusedata_mtr_cfg_1, offset: 0x34 */ + __I uint32_t OCOTP_FUSE_DATA2; /**< Read-only version of OCOTP fusedata_mtr_cfg_2, offset: 0x38 */ + __I uint32_t OCOTP_FUSE_DATA3; /**< Read-only version of OCOTP fusedata_mtr_cfg_3, offset: 0x3C */ + __I uint32_t OCOTP_FUSE_DATA4; /**< Read-only version of OCOTP fusedata_mtr_cfg_4, offset: 0x40 */ + __I uint32_t OCOTP_FUSE_DATA5; /**< Read-only version of OCOTP fusedata_mtr_cfg_5, offset: 0x44 */ + __I uint32_t OCOTP_FUSE_DATA6; /**< Read-only version of OCOTP fusedata_mtr_cfg_6, offset: 0x48 */ + __I uint32_t OCOTP_FUSE_DATA7; /**< Read-only version of OCOTP fusedata_mtr_cfg_7, offset: 0x4C */ + __I uint32_t OCOTP_FUSE_DATA8; /**< Read-only version of OCOTP fusedata_mem_trim_cfg0, offset: 0x50 */ + __I uint32_t OCOTP_FUSE_DATA9; /**< Read-only version of OCOTP fusedata_mem_trim_cfg1, offset: 0x54 */ + __I uint32_t OCOTP_FUSE_DATA10; /**< Read-only version of OCOTP fusedata_mem_trim_cfg2, offset: 0x58 */ + __I uint32_t OCOTP_FUSE_DATA11; /**< Read-only version of OCOTP fusedata_mem_trim_cfg3, offset: 0x5C */ + __I uint32_t OCOTP_FUSE_DATA12; /**< Read-only version of OCOTP fusedata_mem_trim_cfg4, offset: 0x60 */ + __I uint32_t OCOTP_FUSE_DATA13; /**< Read-only version of OCOTP fusedata_mem_trim_cfg5, offset: 0x64 */ + __I uint32_t OCOTP_FUSE_DATA14; /**< Read-only version of OCOTP fusedata_mem_trim_cfg6, offset: 0x68 */ + __I uint32_t OCOTP_FUSE_DATA15; /**< Read-only version of OCOTP fusedata_mem_trim_cfg7, offset: 0x6C */ + __IO uint32_t I3C1_WAKEUP; /**< I3C1 WAKEUPX CLR, offset: 0x70 */ + __I uint32_t OCOTP_STATUS; /**< OCOTP status, offset: 0x74 */ + __IO uint32_t PDM_CLK_SEL; /**< PDM clock selection register, offset: 0x78 */ + __IO uint32_t I3C1_SDA_IRQ; /**< I3C1 SDA IRQ CONTROL, offset: 0x7C */ + __I uint32_t FASTBOOT_ENABLE; /**< Fastboot enable, offset: 0x80 */ + __I uint32_t EDGELOCK_FW_PRESENT; /**< Read only Edgelock fuse, offset: 0x84 */ + uint8_t RESERVED_5[8]; + __IO uint32_t SSI_MASTER_AON2WKUP; /**< low power control for SSI_MASTER_AON2WKUP, offset: 0x90 */ + __IO uint32_t SSI_SLV_WKUP2AON; /**< low power control for SSI_SLV_WKUP2AON, offset: 0x94 */ +} BLK_CTRL_NS_AONMIX_Type; + +/* ---------------------------------------------------------------------------- + -- BLK_CTRL_NS_AONMIX Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup BLK_CTRL_NS_AONMIX_Register_Masks BLK_CTRL_NS_AONMIX Register Masks + * @{ + */ + +/*! @name IPG_DEBUG_CA55C0 - IPG DEBUG MASK BIT CA55 CORE0 */ +/*! @{ */ + +#define BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_CAN1_MASK (0x1U) +#define BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_CAN1_SHIFT (0U) +/*! CAN1 - Mask bit for debug halted mode + * 0b0..Block does not enter debug halted mode with CA55 + * 0b1..Block enters debug halted mode when CA55 is debug halted + */ +#define BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_CAN1(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_CAN1_SHIFT)) & BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_CAN1_MASK) + +#define BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_EDMA1_MASK (0x2U) +#define BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_EDMA1_SHIFT (1U) +/*! EDMA1 - Mask bit for debug halted mode + * 0b0..Block does not enter debug halted mode with CA55 + * 0b1..Block enters debug halted mode when CA55 is debug halted + */ +#define BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_EDMA1(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_EDMA1_SHIFT)) & BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_EDMA1_MASK) + +#define BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_LPI2C1_MASK (0x4U) +#define BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_LPI2C1_SHIFT (2U) +/*! LPI2C1 - Mask bit for debug halted mode + * 0b0..Block does not enter debug halted mode with CA55 + * 0b1..Block enters debug halted mode when CA55 is debug halted + */ +#define BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_LPI2C1(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_LPI2C1_SHIFT)) & BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_LPI2C1_MASK) + +#define BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_LPI2C2_MASK (0x8U) +#define BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_LPI2C2_SHIFT (3U) +/*! LPI2C2 - Mask bit for debug halted mode + * 0b0..Block does not enter debug halted mode with CA55 + * 0b1..Block enters debug halted mode when CA55 is debug halted + */ +#define BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_LPI2C2(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_LPI2C2_SHIFT)) & BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_LPI2C2_MASK) + +#define BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_LPIT1_MASK (0x10U) +#define BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_LPIT1_SHIFT (4U) +/*! LPIT1 - Mask bit for debug halted mode + * 0b0..Block does not enter debug halted mode with CA55 + * 0b1..Block enters debug halted mode when CA55 is debug halted + */ +#define BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_LPIT1(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_LPIT1_SHIFT)) & BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_LPIT1_MASK) + +#define BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_LPSPI1_MASK (0x20U) +#define BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_LPSPI1_SHIFT (5U) +/*! LPSPI1 - Mask bit for debug halted mode + * 0b0..Block does not enter debug halted mode with CA55 + * 0b1..Block enters debug halted mode when CA55 is debug halted + */ +#define BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_LPSPI1(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_LPSPI1_SHIFT)) & BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_LPSPI1_MASK) + +#define BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_LPSPI2_MASK (0x40U) +#define BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_LPSPI2_SHIFT (6U) +/*! LPSPI2 - Mask bit for debug halted mode + * 0b0..Block does not enter debug halted mode with CA55 + * 0b1..Block enters debug halted mode when CA55 is debug halted + */ +#define BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_LPSPI2(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_LPSPI2_SHIFT)) & BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_LPSPI2_MASK) + +#define BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_LPTMR1_MASK (0x80U) +#define BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_LPTMR1_SHIFT (7U) +/*! LPTMR1 - Mask bit for debug halted mode + * 0b0..Block does not enter debug halted mode with CA55 + * 0b1..Block enters debug halted mode when CA55 is debug halted + */ +#define BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_LPTMR1(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_LPTMR1_SHIFT)) & BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_LPTMR1_MASK) + +#define BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_SAI1_MASK (0x100U) +#define BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_SAI1_SHIFT (8U) +/*! SAI1 - Mask bit for debug halted mode + * 0b0..Block does not enter debug halted mode with CA55 + * 0b1..Block enters debug halted mode when CA55 is debug halted + */ +#define BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_SAI1(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_SAI1_SHIFT)) & BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_SAI1_MASK) + +#define BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_TPM1_MASK (0x200U) +#define BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_TPM1_SHIFT (9U) +/*! TPM1 - Mask bit for debug halted mode + * 0b0..Block does not enter debug halted mode with CA55 + * 0b1..Block enters debug halted mode when CA55 is debug halted + */ +#define BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_TPM1(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_TPM1_SHIFT)) & BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_TPM1_MASK) + +#define BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_TPM2_MASK (0x400U) +#define BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_TPM2_SHIFT (10U) +/*! TPM2 - Mask bit for debug halted mode + * 0b0..Block does not enter debug halted mode with CA55 + * 0b1..Block enters debug halted mode when CA55 is debug halted + */ +#define BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_TPM2(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_TPM2_SHIFT)) & BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_TPM2_MASK) + +#define BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_WDOG1_MASK (0x800U) +#define BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_WDOG1_SHIFT (11U) +/*! WDOG1 - Mask bit for debug halted mode + * 0b0..Block does not enter debug halted mode with CA55 + * 0b1..Block enters debug halted mode when CA55 is debug halted + */ +#define BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_WDOG1(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_WDOG1_SHIFT)) & BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_WDOG1_MASK) + +#define BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_WDOG2_MASK (0x1000U) +#define BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_WDOG2_SHIFT (12U) +/*! WDOG2 - Mask bit for debug halted mode + * 0b0..Block does not enter debug halted mode with CA55 + * 0b1..Block enters debug halted mode when CA55 is debug halted + */ +#define BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_WDOG2(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_WDOG2_SHIFT)) & BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_WDOG2_MASK) + +#define BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_I3C1_MASK (0x2000U) +#define BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_I3C1_SHIFT (13U) +/*! I3C1 - Mask bit for debug halted mode + * 0b0..Block does not enter debug halted mode with CA55 + * 0b1..Block enters debug halted mode when CA55 is debug halted + */ +#define BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_I3C1(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_I3C1_SHIFT)) & BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_I3C1_MASK) + +#define BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_PDM_MASK (0x4000U) +#define BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_PDM_SHIFT (14U) +/*! PDM - Mask bit for debug halted mode + * 0b0..Block does not enter debug halted mode with CA55 + * 0b1..Block enters debug halted mode when CA55 is debug halted + */ +#define BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_PDM(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_PDM_SHIFT)) & BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_PDM_MASK) +/*! @} */ + +/*! @name LP_HANDSHAKE - LP HANDSHAKE */ +/*! @{ */ + +#define BLK_CTRL_NS_AONMIX_LP_HANDSHAKE_CAN1_STOP_MASK (0x1U) +#define BLK_CTRL_NS_AONMIX_LP_HANDSHAKE_CAN1_STOP_SHIFT (0U) +/*! CAN1_STOP - CAN1 STOP + * 0b0..QCHANNEL is enabled + * 0b1..QCHANNEL is disabled + */ +#define BLK_CTRL_NS_AONMIX_LP_HANDSHAKE_CAN1_STOP(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NS_AONMIX_LP_HANDSHAKE_CAN1_STOP_SHIFT)) & BLK_CTRL_NS_AONMIX_LP_HANDSHAKE_CAN1_STOP_MASK) +/*! @} */ + +/*! @name MQS_SETTINGS - MQS settings. */ +/*! @{ */ + +#define BLK_CTRL_NS_AONMIX_MQS_SETTINGS_MQS_EN_MASK (0x2U) +#define BLK_CTRL_NS_AONMIX_MQS_SETTINGS_MQS_EN_SHIFT (1U) +/*! MQS_EN - MQS Enable */ +#define BLK_CTRL_NS_AONMIX_MQS_SETTINGS_MQS_EN(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NS_AONMIX_MQS_SETTINGS_MQS_EN_SHIFT)) & BLK_CTRL_NS_AONMIX_MQS_SETTINGS_MQS_EN_MASK) + +#define BLK_CTRL_NS_AONMIX_MQS_SETTINGS_SOFT_RESET_MASK (0x4U) +#define BLK_CTRL_NS_AONMIX_MQS_SETTINGS_SOFT_RESET_SHIFT (2U) +/*! SOFT_RESET - Software Reset */ +#define BLK_CTRL_NS_AONMIX_MQS_SETTINGS_SOFT_RESET(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NS_AONMIX_MQS_SETTINGS_SOFT_RESET_SHIFT)) & BLK_CTRL_NS_AONMIX_MQS_SETTINGS_SOFT_RESET_MASK) + +#define BLK_CTRL_NS_AONMIX_MQS_SETTINGS_OVERSAMPLE_MASK (0x8U) +#define BLK_CTRL_NS_AONMIX_MQS_SETTINGS_OVERSAMPLE_SHIFT (3U) +/*! OVERSAMPLE - Oversample enable */ +#define BLK_CTRL_NS_AONMIX_MQS_SETTINGS_OVERSAMPLE(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NS_AONMIX_MQS_SETTINGS_OVERSAMPLE_SHIFT)) & BLK_CTRL_NS_AONMIX_MQS_SETTINGS_OVERSAMPLE_MASK) + +#define BLK_CTRL_NS_AONMIX_MQS_SETTINGS_CLK_DIVIDE_MASK (0xFF00U) +#define BLK_CTRL_NS_AONMIX_MQS_SETTINGS_CLK_DIVIDE_SHIFT (8U) +/*! CLK_DIVIDE - Clock divide factor configuration */ +#define BLK_CTRL_NS_AONMIX_MQS_SETTINGS_CLK_DIVIDE(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NS_AONMIX_MQS_SETTINGS_CLK_DIVIDE_SHIFT)) & BLK_CTRL_NS_AONMIX_MQS_SETTINGS_CLK_DIVIDE_MASK) +/*! @} */ + +/*! @name FUSE_ACC_DIS - Read-only version of the OCOTP fuse-access-disable bit */ +/*! @{ */ + +#define BLK_CTRL_NS_AONMIX_FUSE_ACC_DIS_OSCCA_FUSE_READ_DIS_MASK (0x1U) +#define BLK_CTRL_NS_AONMIX_FUSE_ACC_DIS_OSCCA_FUSE_READ_DIS_SHIFT (0U) +/*! OSCCA_FUSE_READ_DIS - OSCCA fuse read disable + * 0b0..The chip is allowed to access the OCOTP registers + * 0b1..The chip is not allowed to access the OCOTP registers + */ +#define BLK_CTRL_NS_AONMIX_FUSE_ACC_DIS_OSCCA_FUSE_READ_DIS(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NS_AONMIX_FUSE_ACC_DIS_OSCCA_FUSE_READ_DIS_SHIFT)) & BLK_CTRL_NS_AONMIX_FUSE_ACC_DIS_OSCCA_FUSE_READ_DIS_MASK) +/*! @} */ + +/*! @name OCOTP_FUSE_DATA0 - Read-only version of OCOTP fusedata_mtr_cfg_0 */ +/*! @{ */ + +#define BLK_CTRL_NS_AONMIX_OCOTP_FUSE_DATA0_OCOTP_FUSE_DATA0_MASK (0xFFFFFFFFU) +#define BLK_CTRL_NS_AONMIX_OCOTP_FUSE_DATA0_OCOTP_FUSE_DATA0_SHIFT (0U) +/*! OCOTP_FUSE_DATA0 - OCOTP_FUSE_DATA0 */ +#define BLK_CTRL_NS_AONMIX_OCOTP_FUSE_DATA0_OCOTP_FUSE_DATA0(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NS_AONMIX_OCOTP_FUSE_DATA0_OCOTP_FUSE_DATA0_SHIFT)) & BLK_CTRL_NS_AONMIX_OCOTP_FUSE_DATA0_OCOTP_FUSE_DATA0_MASK) +/*! @} */ + +/*! @name OCOTP_FUSE_DATA1 - Read-only version of OCOTP fusedata_mtr_cfg_1 */ +/*! @{ */ + +#define BLK_CTRL_NS_AONMIX_OCOTP_FUSE_DATA1_OCOTP_FUSE_DATA1_MASK (0xFFFFFFFFU) +#define BLK_CTRL_NS_AONMIX_OCOTP_FUSE_DATA1_OCOTP_FUSE_DATA1_SHIFT (0U) +/*! OCOTP_FUSE_DATA1 - OCOTP_FUSE_DATA1 */ +#define BLK_CTRL_NS_AONMIX_OCOTP_FUSE_DATA1_OCOTP_FUSE_DATA1(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NS_AONMIX_OCOTP_FUSE_DATA1_OCOTP_FUSE_DATA1_SHIFT)) & BLK_CTRL_NS_AONMIX_OCOTP_FUSE_DATA1_OCOTP_FUSE_DATA1_MASK) +/*! @} */ + +/*! @name OCOTP_FUSE_DATA2 - Read-only version of OCOTP fusedata_mtr_cfg_2 */ +/*! @{ */ + +#define BLK_CTRL_NS_AONMIX_OCOTP_FUSE_DATA2_OCOTP_FUSE_DATA2_MASK (0xFFFFFFFFU) +#define BLK_CTRL_NS_AONMIX_OCOTP_FUSE_DATA2_OCOTP_FUSE_DATA2_SHIFT (0U) +/*! OCOTP_FUSE_DATA2 - OCOTP_FUSE_DATA2 */ +#define BLK_CTRL_NS_AONMIX_OCOTP_FUSE_DATA2_OCOTP_FUSE_DATA2(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NS_AONMIX_OCOTP_FUSE_DATA2_OCOTP_FUSE_DATA2_SHIFT)) & BLK_CTRL_NS_AONMIX_OCOTP_FUSE_DATA2_OCOTP_FUSE_DATA2_MASK) +/*! @} */ + +/*! @name OCOTP_FUSE_DATA3 - Read-only version of OCOTP fusedata_mtr_cfg_3 */ +/*! @{ */ + +#define BLK_CTRL_NS_AONMIX_OCOTP_FUSE_DATA3_OCOTP_FUSE_DATA3_MASK (0xFFFFFFFFU) +#define BLK_CTRL_NS_AONMIX_OCOTP_FUSE_DATA3_OCOTP_FUSE_DATA3_SHIFT (0U) +/*! OCOTP_FUSE_DATA3 - OCOTP_FUSE_DATA3 */ +#define BLK_CTRL_NS_AONMIX_OCOTP_FUSE_DATA3_OCOTP_FUSE_DATA3(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NS_AONMIX_OCOTP_FUSE_DATA3_OCOTP_FUSE_DATA3_SHIFT)) & BLK_CTRL_NS_AONMIX_OCOTP_FUSE_DATA3_OCOTP_FUSE_DATA3_MASK) +/*! @} */ + +/*! @name OCOTP_FUSE_DATA4 - Read-only version of OCOTP fusedata_mtr_cfg_4 */ +/*! @{ */ + +#define BLK_CTRL_NS_AONMIX_OCOTP_FUSE_DATA4_OCOTP_FUSE_DATA4_MASK (0xFFFFFFFFU) +#define BLK_CTRL_NS_AONMIX_OCOTP_FUSE_DATA4_OCOTP_FUSE_DATA4_SHIFT (0U) +/*! OCOTP_FUSE_DATA4 - OCOTP_FUSE_DATA4 */ +#define BLK_CTRL_NS_AONMIX_OCOTP_FUSE_DATA4_OCOTP_FUSE_DATA4(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NS_AONMIX_OCOTP_FUSE_DATA4_OCOTP_FUSE_DATA4_SHIFT)) & BLK_CTRL_NS_AONMIX_OCOTP_FUSE_DATA4_OCOTP_FUSE_DATA4_MASK) +/*! @} */ + +/*! @name OCOTP_FUSE_DATA5 - Read-only version of OCOTP fusedata_mtr_cfg_5 */ +/*! @{ */ + +#define BLK_CTRL_NS_AONMIX_OCOTP_FUSE_DATA5_OCOTP_FUSE_DATA5_MASK (0xFFFFFFFFU) +#define BLK_CTRL_NS_AONMIX_OCOTP_FUSE_DATA5_OCOTP_FUSE_DATA5_SHIFT (0U) +/*! OCOTP_FUSE_DATA5 - OCOTP_FUSE_DATA5 */ +#define BLK_CTRL_NS_AONMIX_OCOTP_FUSE_DATA5_OCOTP_FUSE_DATA5(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NS_AONMIX_OCOTP_FUSE_DATA5_OCOTP_FUSE_DATA5_SHIFT)) & BLK_CTRL_NS_AONMIX_OCOTP_FUSE_DATA5_OCOTP_FUSE_DATA5_MASK) +/*! @} */ + +/*! @name OCOTP_FUSE_DATA6 - Read-only version of OCOTP fusedata_mtr_cfg_6 */ +/*! @{ */ + +#define BLK_CTRL_NS_AONMIX_OCOTP_FUSE_DATA6_OCOTP_FUSE_DATA6_MASK (0xFFFFFFFFU) +#define BLK_CTRL_NS_AONMIX_OCOTP_FUSE_DATA6_OCOTP_FUSE_DATA6_SHIFT (0U) +/*! OCOTP_FUSE_DATA6 - OCOTP_FUSE_DATA6 */ +#define BLK_CTRL_NS_AONMIX_OCOTP_FUSE_DATA6_OCOTP_FUSE_DATA6(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NS_AONMIX_OCOTP_FUSE_DATA6_OCOTP_FUSE_DATA6_SHIFT)) & BLK_CTRL_NS_AONMIX_OCOTP_FUSE_DATA6_OCOTP_FUSE_DATA6_MASK) +/*! @} */ + +/*! @name OCOTP_FUSE_DATA7 - Read-only version of OCOTP fusedata_mtr_cfg_7 */ +/*! @{ */ + +#define BLK_CTRL_NS_AONMIX_OCOTP_FUSE_DATA7_OCOTP_FUSE_DATA7_MASK (0xFFFFFFFFU) +#define BLK_CTRL_NS_AONMIX_OCOTP_FUSE_DATA7_OCOTP_FUSE_DATA7_SHIFT (0U) +/*! OCOTP_FUSE_DATA7 - OCOTP_FUSE_DATA7 */ +#define BLK_CTRL_NS_AONMIX_OCOTP_FUSE_DATA7_OCOTP_FUSE_DATA7(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NS_AONMIX_OCOTP_FUSE_DATA7_OCOTP_FUSE_DATA7_SHIFT)) & BLK_CTRL_NS_AONMIX_OCOTP_FUSE_DATA7_OCOTP_FUSE_DATA7_MASK) +/*! @} */ + +/*! @name OCOTP_FUSE_DATA8 - Read-only version of OCOTP fusedata_mem_trim_cfg0 */ +/*! @{ */ + +#define BLK_CTRL_NS_AONMIX_OCOTP_FUSE_DATA8_OCOTP_FUSE_DATA8_MASK (0xFFFFFFFFU) +#define BLK_CTRL_NS_AONMIX_OCOTP_FUSE_DATA8_OCOTP_FUSE_DATA8_SHIFT (0U) +/*! OCOTP_FUSE_DATA8 - OCOTP_FUSE_DATA8 */ +#define BLK_CTRL_NS_AONMIX_OCOTP_FUSE_DATA8_OCOTP_FUSE_DATA8(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NS_AONMIX_OCOTP_FUSE_DATA8_OCOTP_FUSE_DATA8_SHIFT)) & BLK_CTRL_NS_AONMIX_OCOTP_FUSE_DATA8_OCOTP_FUSE_DATA8_MASK) +/*! @} */ + +/*! @name OCOTP_FUSE_DATA9 - Read-only version of OCOTP fusedata_mem_trim_cfg1 */ +/*! @{ */ + +#define BLK_CTRL_NS_AONMIX_OCOTP_FUSE_DATA9_OCOTP_FUSE_DATA9_MASK (0xFFFFFFFFU) +#define BLK_CTRL_NS_AONMIX_OCOTP_FUSE_DATA9_OCOTP_FUSE_DATA9_SHIFT (0U) +/*! OCOTP_FUSE_DATA9 - OCOTP_FUSE_DATA9 */ +#define BLK_CTRL_NS_AONMIX_OCOTP_FUSE_DATA9_OCOTP_FUSE_DATA9(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NS_AONMIX_OCOTP_FUSE_DATA9_OCOTP_FUSE_DATA9_SHIFT)) & BLK_CTRL_NS_AONMIX_OCOTP_FUSE_DATA9_OCOTP_FUSE_DATA9_MASK) +/*! @} */ + +/*! @name OCOTP_FUSE_DATA10 - Read-only version of OCOTP fusedata_mem_trim_cfg2 */ +/*! @{ */ + +#define BLK_CTRL_NS_AONMIX_OCOTP_FUSE_DATA10_OCOTP_FUSE_DATA10_MASK (0xFFFFFFFFU) +#define BLK_CTRL_NS_AONMIX_OCOTP_FUSE_DATA10_OCOTP_FUSE_DATA10_SHIFT (0U) +/*! OCOTP_FUSE_DATA10 - OCOTP_FUSE_DATA10 */ +#define BLK_CTRL_NS_AONMIX_OCOTP_FUSE_DATA10_OCOTP_FUSE_DATA10(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NS_AONMIX_OCOTP_FUSE_DATA10_OCOTP_FUSE_DATA10_SHIFT)) & BLK_CTRL_NS_AONMIX_OCOTP_FUSE_DATA10_OCOTP_FUSE_DATA10_MASK) +/*! @} */ + +/*! @name OCOTP_FUSE_DATA11 - Read-only version of OCOTP fusedata_mem_trim_cfg3 */ +/*! @{ */ + +#define BLK_CTRL_NS_AONMIX_OCOTP_FUSE_DATA11_OCOTP_FUSE_DATA11_MASK (0xFFFFFFFFU) +#define BLK_CTRL_NS_AONMIX_OCOTP_FUSE_DATA11_OCOTP_FUSE_DATA11_SHIFT (0U) +/*! OCOTP_FUSE_DATA11 - OCOTP_FUSE_DATA12 */ +#define BLK_CTRL_NS_AONMIX_OCOTP_FUSE_DATA11_OCOTP_FUSE_DATA11(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NS_AONMIX_OCOTP_FUSE_DATA11_OCOTP_FUSE_DATA11_SHIFT)) & BLK_CTRL_NS_AONMIX_OCOTP_FUSE_DATA11_OCOTP_FUSE_DATA11_MASK) +/*! @} */ + +/*! @name OCOTP_FUSE_DATA12 - Read-only version of OCOTP fusedata_mem_trim_cfg4 */ +/*! @{ */ + +#define BLK_CTRL_NS_AONMIX_OCOTP_FUSE_DATA12_OCOTP_FUSE_DATA12_MASK (0xFFFFFFFFU) +#define BLK_CTRL_NS_AONMIX_OCOTP_FUSE_DATA12_OCOTP_FUSE_DATA12_SHIFT (0U) +/*! OCOTP_FUSE_DATA12 - OCOTP_FUSE_DATA13 */ +#define BLK_CTRL_NS_AONMIX_OCOTP_FUSE_DATA12_OCOTP_FUSE_DATA12(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NS_AONMIX_OCOTP_FUSE_DATA12_OCOTP_FUSE_DATA12_SHIFT)) & BLK_CTRL_NS_AONMIX_OCOTP_FUSE_DATA12_OCOTP_FUSE_DATA12_MASK) +/*! @} */ + +/*! @name OCOTP_FUSE_DATA13 - Read-only version of OCOTP fusedata_mem_trim_cfg5 */ +/*! @{ */ + +#define BLK_CTRL_NS_AONMIX_OCOTP_FUSE_DATA13_OCOTP_FUSE_DATA13_MASK (0xFFFFFFFFU) +#define BLK_CTRL_NS_AONMIX_OCOTP_FUSE_DATA13_OCOTP_FUSE_DATA13_SHIFT (0U) +/*! OCOTP_FUSE_DATA13 - OCOTP_FUSE_DATA13 */ +#define BLK_CTRL_NS_AONMIX_OCOTP_FUSE_DATA13_OCOTP_FUSE_DATA13(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NS_AONMIX_OCOTP_FUSE_DATA13_OCOTP_FUSE_DATA13_SHIFT)) & BLK_CTRL_NS_AONMIX_OCOTP_FUSE_DATA13_OCOTP_FUSE_DATA13_MASK) +/*! @} */ + +/*! @name OCOTP_FUSE_DATA14 - Read-only version of OCOTP fusedata_mem_trim_cfg6 */ +/*! @{ */ + +#define BLK_CTRL_NS_AONMIX_OCOTP_FUSE_DATA14_OCOTP_FUSE_DATA14_MASK (0xFFFFFFFFU) +#define BLK_CTRL_NS_AONMIX_OCOTP_FUSE_DATA14_OCOTP_FUSE_DATA14_SHIFT (0U) +/*! OCOTP_FUSE_DATA14 - OCOTP_FUSE_DATA14 */ +#define BLK_CTRL_NS_AONMIX_OCOTP_FUSE_DATA14_OCOTP_FUSE_DATA14(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NS_AONMIX_OCOTP_FUSE_DATA14_OCOTP_FUSE_DATA14_SHIFT)) & BLK_CTRL_NS_AONMIX_OCOTP_FUSE_DATA14_OCOTP_FUSE_DATA14_MASK) +/*! @} */ + +/*! @name OCOTP_FUSE_DATA15 - Read-only version of OCOTP fusedata_mem_trim_cfg7 */ +/*! @{ */ + +#define BLK_CTRL_NS_AONMIX_OCOTP_FUSE_DATA15_OCOTP_FUSE_DATA15_MASK (0xFFFFFFFFU) +#define BLK_CTRL_NS_AONMIX_OCOTP_FUSE_DATA15_OCOTP_FUSE_DATA15_SHIFT (0U) +/*! OCOTP_FUSE_DATA15 - OCOTP_FUSE_DATA15 */ +#define BLK_CTRL_NS_AONMIX_OCOTP_FUSE_DATA15_OCOTP_FUSE_DATA15(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NS_AONMIX_OCOTP_FUSE_DATA15_OCOTP_FUSE_DATA15_SHIFT)) & BLK_CTRL_NS_AONMIX_OCOTP_FUSE_DATA15_OCOTP_FUSE_DATA15_MASK) +/*! @} */ + +/*! @name I3C1_WAKEUP - I3C1 WAKEUPX CLR */ +/*! @{ */ + +#define BLK_CTRL_NS_AONMIX_I3C1_WAKEUP_IRQ_CLR_MASK (0x1U) +#define BLK_CTRL_NS_AONMIX_I3C1_WAKEUP_IRQ_CLR_SHIFT (0U) +/*! IRQ_CLR - I3C1 Interrupt request clear */ +#define BLK_CTRL_NS_AONMIX_I3C1_WAKEUP_IRQ_CLR(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NS_AONMIX_I3C1_WAKEUP_IRQ_CLR_SHIFT)) & BLK_CTRL_NS_AONMIX_I3C1_WAKEUP_IRQ_CLR_MASK) +/*! @} */ + +/*! @name OCOTP_STATUS - OCOTP status */ +/*! @{ */ + +#define BLK_CTRL_NS_AONMIX_OCOTP_STATUS_BUSY_MASK (0x1U) +#define BLK_CTRL_NS_AONMIX_OCOTP_STATUS_BUSY_SHIFT (0U) +/*! BUSY - OCOTP controller busy bit + * 0b0..Idle + * 0b1..OCOTP is Busy + */ +#define BLK_CTRL_NS_AONMIX_OCOTP_STATUS_BUSY(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NS_AONMIX_OCOTP_STATUS_BUSY_SHIFT)) & BLK_CTRL_NS_AONMIX_OCOTP_STATUS_BUSY_MASK) +/*! @} */ + +/*! @name PDM_CLK_SEL - PDM clock selection register */ +/*! @{ */ + +#define BLK_CTRL_NS_AONMIX_PDM_CLK_SEL_SEL_MASK (0x1U) +#define BLK_CTRL_NS_AONMIX_PDM_CLK_SEL_SEL_SHIFT (0U) +/*! SEL - Select source for PDM clock + * 0b0..PDM root clock + * 0b1..SAI1_MCLK + */ +#define BLK_CTRL_NS_AONMIX_PDM_CLK_SEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NS_AONMIX_PDM_CLK_SEL_SEL_SHIFT)) & BLK_CTRL_NS_AONMIX_PDM_CLK_SEL_SEL_MASK) +/*! @} */ + +/*! @name I3C1_SDA_IRQ - I3C1 SDA IRQ CONTROL */ +/*! @{ */ + +#define BLK_CTRL_NS_AONMIX_I3C1_SDA_IRQ_ENABLE_MASK (0x1U) +#define BLK_CTRL_NS_AONMIX_I3C1_SDA_IRQ_ENABLE_SHIFT (0U) +/*! ENABLE - IRQ enable bit + * 0b0..I3C1 SDA IRQ disable + * 0b1..I3C1 SDA IRQ enable + */ +#define BLK_CTRL_NS_AONMIX_I3C1_SDA_IRQ_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NS_AONMIX_I3C1_SDA_IRQ_ENABLE_SHIFT)) & BLK_CTRL_NS_AONMIX_I3C1_SDA_IRQ_ENABLE_MASK) +/*! @} */ + +/*! @name FASTBOOT_ENABLE - Fastboot enable */ +/*! @{ */ + +#define BLK_CTRL_NS_AONMIX_FASTBOOT_ENABLE_FASTBOOT_ENABLE_MASK (0x3U) +#define BLK_CTRL_NS_AONMIX_FASTBOOT_ENABLE_FASTBOOT_ENABLE_SHIFT (0U) +/*! FASTBOOT_ENABLE - FASTBOOT_ENABLE bits */ +#define BLK_CTRL_NS_AONMIX_FASTBOOT_ENABLE_FASTBOOT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NS_AONMIX_FASTBOOT_ENABLE_FASTBOOT_ENABLE_SHIFT)) & BLK_CTRL_NS_AONMIX_FASTBOOT_ENABLE_FASTBOOT_ENABLE_MASK) + +#define BLK_CTRL_NS_AONMIX_FASTBOOT_ENABLE_BP_FASTBOOT_ENABLE_MASK (0xCU) +#define BLK_CTRL_NS_AONMIX_FASTBOOT_ENABLE_BP_FASTBOOT_ENABLE_SHIFT (2U) +/*! BP_FASTBOOT_ENABLE - BP_FASTBOOT_ENABLE */ +#define BLK_CTRL_NS_AONMIX_FASTBOOT_ENABLE_BP_FASTBOOT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NS_AONMIX_FASTBOOT_ENABLE_BP_FASTBOOT_ENABLE_SHIFT)) & BLK_CTRL_NS_AONMIX_FASTBOOT_ENABLE_BP_FASTBOOT_ENABLE_MASK) +/*! @} */ + +/*! @name EDGELOCK_FW_PRESENT - Read only Edgelock fuse */ +/*! @{ */ + +#define BLK_CTRL_NS_AONMIX_EDGELOCK_FW_PRESENT_EDGELOCK_FW_PRESENT_MASK (0x1U) +#define BLK_CTRL_NS_AONMIX_EDGELOCK_FW_PRESENT_EDGELOCK_FW_PRESENT_SHIFT (0U) +/*! EDGELOCK_FW_PRESENT - Read only bit for Edgelock fuse */ +#define BLK_CTRL_NS_AONMIX_EDGELOCK_FW_PRESENT_EDGELOCK_FW_PRESENT(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NS_AONMIX_EDGELOCK_FW_PRESENT_EDGELOCK_FW_PRESENT_SHIFT)) & BLK_CTRL_NS_AONMIX_EDGELOCK_FW_PRESENT_EDGELOCK_FW_PRESENT_MASK) +/*! @} */ + +/*! @name SSI_MASTER_AON2WKUP - low power control for SSI_MASTER_AON2WKUP */ +/*! @{ */ + +#define BLK_CTRL_NS_AONMIX_SSI_MASTER_AON2WKUP_idle_MASK (0x1U) +#define BLK_CTRL_NS_AONMIX_SSI_MASTER_AON2WKUP_idle_SHIFT (0U) +#define BLK_CTRL_NS_AONMIX_SSI_MASTER_AON2WKUP_idle(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NS_AONMIX_SSI_MASTER_AON2WKUP_idle_SHIFT)) & BLK_CTRL_NS_AONMIX_SSI_MASTER_AON2WKUP_idle_MASK) + +#define BLK_CTRL_NS_AONMIX_SSI_MASTER_AON2WKUP_pause_MASK (0x4U) +#define BLK_CTRL_NS_AONMIX_SSI_MASTER_AON2WKUP_pause_SHIFT (2U) +#define BLK_CTRL_NS_AONMIX_SSI_MASTER_AON2WKUP_pause(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NS_AONMIX_SSI_MASTER_AON2WKUP_pause_SHIFT)) & BLK_CTRL_NS_AONMIX_SSI_MASTER_AON2WKUP_pause_MASK) + +#define BLK_CTRL_NS_AONMIX_SSI_MASTER_AON2WKUP_black_hole_mode_b_MASK (0x8U) +#define BLK_CTRL_NS_AONMIX_SSI_MASTER_AON2WKUP_black_hole_mode_b_SHIFT (3U) +#define BLK_CTRL_NS_AONMIX_SSI_MASTER_AON2WKUP_black_hole_mode_b(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NS_AONMIX_SSI_MASTER_AON2WKUP_black_hole_mode_b_SHIFT)) & BLK_CTRL_NS_AONMIX_SSI_MASTER_AON2WKUP_black_hole_mode_b_MASK) + +#define BLK_CTRL_NS_AONMIX_SSI_MASTER_AON2WKUP_power_control_MASK (0x10U) +#define BLK_CTRL_NS_AONMIX_SSI_MASTER_AON2WKUP_power_control_SHIFT (4U) +#define BLK_CTRL_NS_AONMIX_SSI_MASTER_AON2WKUP_power_control(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NS_AONMIX_SSI_MASTER_AON2WKUP_power_control_SHIFT)) & BLK_CTRL_NS_AONMIX_SSI_MASTER_AON2WKUP_power_control_MASK) + +#define BLK_CTRL_NS_AONMIX_SSI_MASTER_AON2WKUP_iso_control_MASK (0x20U) +#define BLK_CTRL_NS_AONMIX_SSI_MASTER_AON2WKUP_iso_control_SHIFT (5U) +#define BLK_CTRL_NS_AONMIX_SSI_MASTER_AON2WKUP_iso_control(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NS_AONMIX_SSI_MASTER_AON2WKUP_iso_control_SHIFT)) & BLK_CTRL_NS_AONMIX_SSI_MASTER_AON2WKUP_iso_control_MASK) +/*! @} */ + +/*! @name SSI_SLV_WKUP2AON - low power control for SSI_SLV_WKUP2AON */ +/*! @{ */ + +#define BLK_CTRL_NS_AONMIX_SSI_SLV_WKUP2AON_idle_MASK (0x1U) +#define BLK_CTRL_NS_AONMIX_SSI_SLV_WKUP2AON_idle_SHIFT (0U) +#define BLK_CTRL_NS_AONMIX_SSI_SLV_WKUP2AON_idle(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NS_AONMIX_SSI_SLV_WKUP2AON_idle_SHIFT)) & BLK_CTRL_NS_AONMIX_SSI_SLV_WKUP2AON_idle_MASK) + +#define BLK_CTRL_NS_AONMIX_SSI_SLV_WKUP2AON_power_control_MASK (0x10U) +#define BLK_CTRL_NS_AONMIX_SSI_SLV_WKUP2AON_power_control_SHIFT (4U) +#define BLK_CTRL_NS_AONMIX_SSI_SLV_WKUP2AON_power_control(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NS_AONMIX_SSI_SLV_WKUP2AON_power_control_SHIFT)) & BLK_CTRL_NS_AONMIX_SSI_SLV_WKUP2AON_power_control_MASK) + +#define BLK_CTRL_NS_AONMIX_SSI_SLV_WKUP2AON_iso_control_MASK (0x20U) +#define BLK_CTRL_NS_AONMIX_SSI_SLV_WKUP2AON_iso_control_SHIFT (5U) +#define BLK_CTRL_NS_AONMIX_SSI_SLV_WKUP2AON_iso_control(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NS_AONMIX_SSI_SLV_WKUP2AON_iso_control_SHIFT)) & BLK_CTRL_NS_AONMIX_SSI_SLV_WKUP2AON_iso_control_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group BLK_CTRL_NS_AONMIX_Register_Masks */ + + +/* BLK_CTRL_NS_AONMIX - Peripheral instance base addresses */ +/** Peripheral BLK_CTRL_NS_AONMIX1 base address */ +#define BLK_CTRL_NS_AONMIX1_BASE (0x44210000u) +/** Peripheral BLK_CTRL_NS_AONMIX1 base pointer */ +#define BLK_CTRL_NS_AONMIX1 ((BLK_CTRL_NS_AONMIX_Type *)BLK_CTRL_NS_AONMIX1_BASE) +/** Array initializer of BLK_CTRL_NS_AONMIX peripheral base addresses */ +#define BLK_CTRL_NS_AONMIX_BASE_ADDRS { BLK_CTRL_NS_AONMIX1_BASE } +/** Array initializer of BLK_CTRL_NS_AONMIX peripheral base pointers */ +#define BLK_CTRL_NS_AONMIX_BASE_PTRS { BLK_CTRL_NS_AONMIX1 } + +/*! + * @} + */ /* end of group BLK_CTRL_NS_AONMIX_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- BLK_CTRL_S_AONMIX Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup BLK_CTRL_S_AONMIX_Peripheral_Access_Layer BLK_CTRL_S_AONMIX Peripheral Access Layer + * @{ + */ + +/** BLK_CTRL_S_AONMIX - Register Layout Typedef */ +typedef struct { + uint8_t RESERVED_0[64]; + __IO uint32_t CA55_IRQ_MASK0; /**< CA55_IRQ_MASK0, offset: 0x40 */ + __IO uint32_t CA55_IRQ_MASK1; /**< CA55_IRQ_MASK1, offset: 0x44 */ + __IO uint32_t CA55_IRQ_MASK2; /**< CA55_IRQ_MASK2, offset: 0x48 */ + __IO uint32_t CA55_IRQ_MASK3; /**< CA55_IRQ_MASK3, offset: 0x4C */ + __IO uint32_t CA55_IRQ_MASK4; /**< CA55_IRQ_MASK4, offset: 0x50 */ + __IO uint32_t CA55_IRQ_MASK5; /**< CA55_IRQ_MASK5, offset: 0x54 */ + __IO uint32_t CA55_IRQ_MASK6; /**< CA55_IRQ_MASK6, offset: 0x58 */ + uint8_t RESERVED_1[164]; + __IO uint32_t DAP_ACCESS_STKYBIT; /**< Dap Access Sticky Bit, offset: 0x100 */ + uint8_t RESERVED_2[12]; + __IO uint32_t LP_HANDSHAKE; /**< Low power handshake enable, offset: 0x110 */ + __IO uint32_t LP_HANDSHAKE2; /**< Low power handshake enable, offset: 0x114 */ + __IO uint32_t CA55_CPUWAIT; /**< CPUWAIT settings for CA55 CPU, offset: 0x118 */ + __IO uint32_t CA55_RVBARADDR0_L; /**< CA55_RVBARADDR0_L, offset: 0x11C */ + __IO uint32_t CA55_RVBARADDR0_H; /**< CA55_RVBARADDR0_H, offset: 0x120 */ + uint8_t RESERVED_3[8]; + __IO uint32_t ELE_IRQ_MASK; /**< Mask bits of Edgelock interrupt, offset: 0x12C */ + __IO uint32_t ELE_RESET_REQ_MASK; /**< Mask bits of ELE reset, offset: 0x130 */ + __IO uint32_t ELE_HALT_ST; /**< ELE halt status, offset: 0x134 */ + __IO uint32_t CA55_MODE; /**< Control the boot mode of two ca55 cores, offset: 0x138 */ + uint8_t RESERVED_4[8]; + __IO uint32_t WDOG_ANY_MASK; /**< WDOG any mask, offset: 0x144 */ + __IO uint32_t ELEV1_IPI_NOCLK_REF1; /**< ELEV1_IPI_NOCLK_REF1 clear, offset: 0x148 */ + __IO uint32_t L2_OCRAM_STICKY; /**< L2 ocram enable bit, offset: 0x14C */ +} BLK_CTRL_S_AONMIX_Type; + +/* ---------------------------------------------------------------------------- + -- BLK_CTRL_S_AONMIX Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup BLK_CTRL_S_AONMIX_Register_Masks BLK_CTRL_S_AONMIX Register Masks + * @{ + */ + +/*! @name CA55_IRQ_MASK0 - CA55_IRQ_MASK0 */ +/*! @{ */ + +#define BLK_CTRL_S_AONMIX_CA55_IRQ_MASK0_M_MASK (0xFFFFFFFFU) +#define BLK_CTRL_S_AONMIX_CA55_IRQ_MASK0_M_SHIFT (0U) +/*! M - CA55 IRQ MASK + * 0b00000000000000000000000000000000..IRQ masked + * 0b00000000000000000000000000000001..IRQ not masked + */ +#define BLK_CTRL_S_AONMIX_CA55_IRQ_MASK0_M(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_S_AONMIX_CA55_IRQ_MASK0_M_SHIFT)) & BLK_CTRL_S_AONMIX_CA55_IRQ_MASK0_M_MASK) +/*! @} */ + +/*! @name CA55_IRQ_MASK1 - CA55_IRQ_MASK1 */ +/*! @{ */ + +#define BLK_CTRL_S_AONMIX_CA55_IRQ_MASK1_M_MASK (0xFFFFFFFFU) +#define BLK_CTRL_S_AONMIX_CA55_IRQ_MASK1_M_SHIFT (0U) +/*! M - CA55 IRQ MASK + * 0b00000000000000000000000000000000..IRQ masked + * 0b00000000000000000000000000000001..IRQ not masked + */ +#define BLK_CTRL_S_AONMIX_CA55_IRQ_MASK1_M(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_S_AONMIX_CA55_IRQ_MASK1_M_SHIFT)) & BLK_CTRL_S_AONMIX_CA55_IRQ_MASK1_M_MASK) +/*! @} */ + +/*! @name CA55_IRQ_MASK2 - CA55_IRQ_MASK2 */ +/*! @{ */ + +#define BLK_CTRL_S_AONMIX_CA55_IRQ_MASK2_M_MASK (0xFFFFFFFFU) +#define BLK_CTRL_S_AONMIX_CA55_IRQ_MASK2_M_SHIFT (0U) +/*! M - CA55 IRQ MASK + * 0b00000000000000000000000000000000..IRQ masked + * 0b00000000000000000000000000000001..IRQ not masked + */ +#define BLK_CTRL_S_AONMIX_CA55_IRQ_MASK2_M(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_S_AONMIX_CA55_IRQ_MASK2_M_SHIFT)) & BLK_CTRL_S_AONMIX_CA55_IRQ_MASK2_M_MASK) +/*! @} */ + +/*! @name CA55_IRQ_MASK3 - CA55_IRQ_MASK3 */ +/*! @{ */ + +#define BLK_CTRL_S_AONMIX_CA55_IRQ_MASK3_M_MASK (0xFFFFFFFFU) +#define BLK_CTRL_S_AONMIX_CA55_IRQ_MASK3_M_SHIFT (0U) +/*! M - CA55 IRQ MASK + * 0b00000000000000000000000000000000..IRQ masked + * 0b00000000000000000000000000000001..IRQ not masked + */ +#define BLK_CTRL_S_AONMIX_CA55_IRQ_MASK3_M(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_S_AONMIX_CA55_IRQ_MASK3_M_SHIFT)) & BLK_CTRL_S_AONMIX_CA55_IRQ_MASK3_M_MASK) +/*! @} */ + +/*! @name CA55_IRQ_MASK4 - CA55_IRQ_MASK4 */ +/*! @{ */ + +#define BLK_CTRL_S_AONMIX_CA55_IRQ_MASK4_M_MASK (0xFFFFFFFFU) +#define BLK_CTRL_S_AONMIX_CA55_IRQ_MASK4_M_SHIFT (0U) +/*! M - CA55 IRQ MASK + * 0b00000000000000000000000000000000..IRQ masked + * 0b00000000000000000000000000000001..IRQ not masked + */ +#define BLK_CTRL_S_AONMIX_CA55_IRQ_MASK4_M(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_S_AONMIX_CA55_IRQ_MASK4_M_SHIFT)) & BLK_CTRL_S_AONMIX_CA55_IRQ_MASK4_M_MASK) +/*! @} */ + +/*! @name CA55_IRQ_MASK5 - CA55_IRQ_MASK5 */ +/*! @{ */ + +#define BLK_CTRL_S_AONMIX_CA55_IRQ_MASK5_M_MASK (0xFFFFFFFFU) +#define BLK_CTRL_S_AONMIX_CA55_IRQ_MASK5_M_SHIFT (0U) +/*! M - CA55 IRQ MASK + * 0b00000000000000000000000000000000..IRQ masked + * 0b00000000000000000000000000000001..IRQ not masked + */ +#define BLK_CTRL_S_AONMIX_CA55_IRQ_MASK5_M(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_S_AONMIX_CA55_IRQ_MASK5_M_SHIFT)) & BLK_CTRL_S_AONMIX_CA55_IRQ_MASK5_M_MASK) +/*! @} */ + +/*! @name CA55_IRQ_MASK6 - CA55_IRQ_MASK6 */ +/*! @{ */ + +#define BLK_CTRL_S_AONMIX_CA55_IRQ_MASK6_M_MASK (0xFFFFFFFFU) +#define BLK_CTRL_S_AONMIX_CA55_IRQ_MASK6_M_SHIFT (0U) +/*! M - CA55 IRQ MASK + * 0b00000000000000000000000000000000..IRQ masked + * 0b00000000000000000000000000000001..IRQ not masked + */ +#define BLK_CTRL_S_AONMIX_CA55_IRQ_MASK6_M(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_S_AONMIX_CA55_IRQ_MASK6_M_SHIFT)) & BLK_CTRL_S_AONMIX_CA55_IRQ_MASK6_M_MASK) +/*! @} */ + +/*! @name DAP_ACCESS_STKYBIT - Dap Access Sticky Bit */ +/*! @{ */ + +#define BLK_CTRL_S_AONMIX_DAP_ACCESS_STKYBIT_A55_MASK (0x2U) +#define BLK_CTRL_S_AONMIX_DAP_ACCESS_STKYBIT_A55_SHIFT (1U) +/*! A55 - A55 DAP_ACCESS_STKYBIT + * 0b0..A55 core can be accessed by DAP + * 0b1..A55 core cannot be accessed by DAPCore0 works normally + */ +#define BLK_CTRL_S_AONMIX_DAP_ACCESS_STKYBIT_A55(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_S_AONMIX_DAP_ACCESS_STKYBIT_A55_SHIFT)) & BLK_CTRL_S_AONMIX_DAP_ACCESS_STKYBIT_A55_MASK) +/*! @} */ + +/*! @name LP_HANDSHAKE - Low power handshake enable */ +/*! @{ */ + +#define BLK_CTRL_S_AONMIX_LP_HANDSHAKE_CA55_CPU0_COLD_RST_HS_EN_MASK (0x1U) +#define BLK_CTRL_S_AONMIX_LP_HANDSHAKE_CA55_CPU0_COLD_RST_HS_EN_SHIFT (0U) +/*! CA55_CPU0_COLD_RST_HS_EN - CA55_CPU0 cold reset handshake enable + * 0b0..Disable + * 0b1..Enable + */ +#define BLK_CTRL_S_AONMIX_LP_HANDSHAKE_CA55_CPU0_COLD_RST_HS_EN(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_S_AONMIX_LP_HANDSHAKE_CA55_CPU0_COLD_RST_HS_EN_SHIFT)) & BLK_CTRL_S_AONMIX_LP_HANDSHAKE_CA55_CPU0_COLD_RST_HS_EN_MASK) + +#define BLK_CTRL_S_AONMIX_LP_HANDSHAKE_CA55_CPU0_LP_HS_EN_MASK (0x2U) +#define BLK_CTRL_S_AONMIX_LP_HANDSHAKE_CA55_CPU0_LP_HS_EN_SHIFT (1U) +/*! CA55_CPU0_LP_HS_EN - CA55_CPU0 low power handshake enable + * 0b0..Disable + * 0b1..Enable + */ +#define BLK_CTRL_S_AONMIX_LP_HANDSHAKE_CA55_CPU0_LP_HS_EN(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_S_AONMIX_LP_HANDSHAKE_CA55_CPU0_LP_HS_EN_SHIFT)) & BLK_CTRL_S_AONMIX_LP_HANDSHAKE_CA55_CPU0_LP_HS_EN_MASK) + +#define BLK_CTRL_S_AONMIX_LP_HANDSHAKE_CA55_CPU1_COLD_RST_HS_EN_MASK (0x4U) +#define BLK_CTRL_S_AONMIX_LP_HANDSHAKE_CA55_CPU1_COLD_RST_HS_EN_SHIFT (2U) +/*! CA55_CPU1_COLD_RST_HS_EN - CA55_CPU1 cold reset handshake enable */ +#define BLK_CTRL_S_AONMIX_LP_HANDSHAKE_CA55_CPU1_COLD_RST_HS_EN(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_S_AONMIX_LP_HANDSHAKE_CA55_CPU1_COLD_RST_HS_EN_SHIFT)) & BLK_CTRL_S_AONMIX_LP_HANDSHAKE_CA55_CPU1_COLD_RST_HS_EN_MASK) + +#define BLK_CTRL_S_AONMIX_LP_HANDSHAKE_CA55_CPU1_LP_HS_EN_MASK (0x8U) +#define BLK_CTRL_S_AONMIX_LP_HANDSHAKE_CA55_CPU1_LP_HS_EN_SHIFT (3U) +/*! CA55_CPU1_LP_HS_EN - CA55_CPU1 low power handshake enable + * 0b0..Disable + * 0b1..Enable + */ +#define BLK_CTRL_S_AONMIX_LP_HANDSHAKE_CA55_CPU1_LP_HS_EN(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_S_AONMIX_LP_HANDSHAKE_CA55_CPU1_LP_HS_EN_SHIFT)) & BLK_CTRL_S_AONMIX_LP_HANDSHAKE_CA55_CPU1_LP_HS_EN_MASK) + +#define BLK_CTRL_S_AONMIX_LP_HANDSHAKE_CA55_PLT_COLD_RST_HS_EN_MASK (0x10U) +#define BLK_CTRL_S_AONMIX_LP_HANDSHAKE_CA55_PLT_COLD_RST_HS_EN_SHIFT (4U) +/*! CA55_PLT_COLD_RST_HS_EN - CA55 platform cold reset handshake enable */ +#define BLK_CTRL_S_AONMIX_LP_HANDSHAKE_CA55_PLT_COLD_RST_HS_EN(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_S_AONMIX_LP_HANDSHAKE_CA55_PLT_COLD_RST_HS_EN_SHIFT)) & BLK_CTRL_S_AONMIX_LP_HANDSHAKE_CA55_PLT_COLD_RST_HS_EN_MASK) + +#define BLK_CTRL_S_AONMIX_LP_HANDSHAKE_CA55_PLT_LP_HS_EN_MASK (0x20U) +#define BLK_CTRL_S_AONMIX_LP_HANDSHAKE_CA55_PLT_LP_HS_EN_SHIFT (5U) +/*! CA55_PLT_LP_HS_EN - CA55 platform cold reset handshake enable + * 0b0..Disable + * 0b1..Enable + */ +#define BLK_CTRL_S_AONMIX_LP_HANDSHAKE_CA55_PLT_LP_HS_EN(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_S_AONMIX_LP_HANDSHAKE_CA55_PLT_LP_HS_EN_SHIFT)) & BLK_CTRL_S_AONMIX_LP_HANDSHAKE_CA55_PLT_LP_HS_EN_MASK) + +#define BLK_CTRL_S_AONMIX_LP_HANDSHAKE_AONMIX_COLD_RST_HS_EN_MASK (0x80U) +#define BLK_CTRL_S_AONMIX_LP_HANDSHAKE_AONMIX_COLD_RST_HS_EN_SHIFT (7U) +/*! AONMIX_COLD_RST_HS_EN - AONMIX cold reset handshake enable + * 0b0..Disable + * 0b1..Enable + */ +#define BLK_CTRL_S_AONMIX_LP_HANDSHAKE_AONMIX_COLD_RST_HS_EN(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_S_AONMIX_LP_HANDSHAKE_AONMIX_COLD_RST_HS_EN_SHIFT)) & BLK_CTRL_S_AONMIX_LP_HANDSHAKE_AONMIX_COLD_RST_HS_EN_MASK) + +#define BLK_CTRL_S_AONMIX_LP_HANDSHAKE_WAKEUPMIX_COLD_RST_HS_EN_MASK (0x100U) +#define BLK_CTRL_S_AONMIX_LP_HANDSHAKE_WAKEUPMIX_COLD_RST_HS_EN_SHIFT (8U) +/*! WAKEUPMIX_COLD_RST_HS_EN - WAKEUPMIX cold reset handshake enable */ +#define BLK_CTRL_S_AONMIX_LP_HANDSHAKE_WAKEUPMIX_COLD_RST_HS_EN(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_S_AONMIX_LP_HANDSHAKE_WAKEUPMIX_COLD_RST_HS_EN_SHIFT)) & BLK_CTRL_S_AONMIX_LP_HANDSHAKE_WAKEUPMIX_COLD_RST_HS_EN_MASK) + +#define BLK_CTRL_S_AONMIX_LP_HANDSHAKE_WAKEUPMIX_LP_HS_EN_MASK (0x200U) +#define BLK_CTRL_S_AONMIX_LP_HANDSHAKE_WAKEUPMIX_LP_HS_EN_SHIFT (9U) +/*! WAKEUPMIX_LP_HS_EN - WAKEUPMIX low power handshake enable + * 0b0..Disable + * 0b1..Enable + */ +#define BLK_CTRL_S_AONMIX_LP_HANDSHAKE_WAKEUPMIX_LP_HS_EN(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_S_AONMIX_LP_HANDSHAKE_WAKEUPMIX_LP_HS_EN_SHIFT)) & BLK_CTRL_S_AONMIX_LP_HANDSHAKE_WAKEUPMIX_LP_HS_EN_MASK) + +#define BLK_CTRL_S_AONMIX_LP_HANDSHAKE_NICMIX_COLD_RST_HS_EN_MASK (0x400U) +#define BLK_CTRL_S_AONMIX_LP_HANDSHAKE_NICMIX_COLD_RST_HS_EN_SHIFT (10U) +/*! NICMIX_COLD_RST_HS_EN - NICMIX cold reset handshake enable */ +#define BLK_CTRL_S_AONMIX_LP_HANDSHAKE_NICMIX_COLD_RST_HS_EN(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_S_AONMIX_LP_HANDSHAKE_NICMIX_COLD_RST_HS_EN_SHIFT)) & BLK_CTRL_S_AONMIX_LP_HANDSHAKE_NICMIX_COLD_RST_HS_EN_MASK) + +#define BLK_CTRL_S_AONMIX_LP_HANDSHAKE_NICMIX_LP_HS_EN_MASK (0x800U) +#define BLK_CTRL_S_AONMIX_LP_HANDSHAKE_NICMIX_LP_HS_EN_SHIFT (11U) +/*! NICMIX_LP_HS_EN - NICMIX low power handshake enable + * 0b0..Disable + * 0b1..Enable + */ +#define BLK_CTRL_S_AONMIX_LP_HANDSHAKE_NICMIX_LP_HS_EN(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_S_AONMIX_LP_HANDSHAKE_NICMIX_LP_HS_EN_SHIFT)) & BLK_CTRL_S_AONMIX_LP_HANDSHAKE_NICMIX_LP_HS_EN_MASK) + +#define BLK_CTRL_S_AONMIX_LP_HANDSHAKE_MEDIAMIX_COLD_RST_HS_EN_MASK (0x1000U) +#define BLK_CTRL_S_AONMIX_LP_HANDSHAKE_MEDIAMIX_COLD_RST_HS_EN_SHIFT (12U) +/*! MEDIAMIX_COLD_RST_HS_EN - MEDIAMIX cold reset handshake enable */ +#define BLK_CTRL_S_AONMIX_LP_HANDSHAKE_MEDIAMIX_COLD_RST_HS_EN(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_S_AONMIX_LP_HANDSHAKE_MEDIAMIX_COLD_RST_HS_EN_SHIFT)) & BLK_CTRL_S_AONMIX_LP_HANDSHAKE_MEDIAMIX_COLD_RST_HS_EN_MASK) + +#define BLK_CTRL_S_AONMIX_LP_HANDSHAKE_MEDIAMIX_LP_HS_EN_MASK (0x2000U) +#define BLK_CTRL_S_AONMIX_LP_HANDSHAKE_MEDIAMIX_LP_HS_EN_SHIFT (13U) +/*! MEDIAMIX_LP_HS_EN - MEDIAMIX low power handshake enable + * 0b0..Disable + * 0b1..Enable + */ +#define BLK_CTRL_S_AONMIX_LP_HANDSHAKE_MEDIAMIX_LP_HS_EN(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_S_AONMIX_LP_HANDSHAKE_MEDIAMIX_LP_HS_EN_SHIFT)) & BLK_CTRL_S_AONMIX_LP_HANDSHAKE_MEDIAMIX_LP_HS_EN_MASK) + +#define BLK_CTRL_S_AONMIX_LP_HANDSHAKE_HSIOMIX_COLD_RST_HS_EN_MASK (0x4000U) +#define BLK_CTRL_S_AONMIX_LP_HANDSHAKE_HSIOMIX_COLD_RST_HS_EN_SHIFT (14U) +/*! HSIOMIX_COLD_RST_HS_EN - HSIOMIX cold reset handshake enable */ +#define BLK_CTRL_S_AONMIX_LP_HANDSHAKE_HSIOMIX_COLD_RST_HS_EN(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_S_AONMIX_LP_HANDSHAKE_HSIOMIX_COLD_RST_HS_EN_SHIFT)) & BLK_CTRL_S_AONMIX_LP_HANDSHAKE_HSIOMIX_COLD_RST_HS_EN_MASK) + +#define BLK_CTRL_S_AONMIX_LP_HANDSHAKE_AON_TRDC_CLK_OFF_HS_EN_MASK (0x8000U) +#define BLK_CTRL_S_AONMIX_LP_HANDSHAKE_AON_TRDC_CLK_OFF_HS_EN_SHIFT (15U) +/*! AON_TRDC_CLK_OFF_HS_EN - AON TRDC clock off handshake enable + * 0b0..Disable + * 0b1..Enable + */ +#define BLK_CTRL_S_AONMIX_LP_HANDSHAKE_AON_TRDC_CLK_OFF_HS_EN(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_S_AONMIX_LP_HANDSHAKE_AON_TRDC_CLK_OFF_HS_EN_SHIFT)) & BLK_CTRL_S_AONMIX_LP_HANDSHAKE_AON_TRDC_CLK_OFF_HS_EN_MASK) + +#define BLK_CTRL_S_AONMIX_LP_HANDSHAKE_WAKEUP_TRDC_CLK_OFF_HS_EN_MASK (0x10000U) +#define BLK_CTRL_S_AONMIX_LP_HANDSHAKE_WAKEUP_TRDC_CLK_OFF_HS_EN_SHIFT (16U) +/*! WAKEUP_TRDC_CLK_OFF_HS_EN - WAKEUP TRDC clock off handshake enable */ +#define BLK_CTRL_S_AONMIX_LP_HANDSHAKE_WAKEUP_TRDC_CLK_OFF_HS_EN(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_S_AONMIX_LP_HANDSHAKE_WAKEUP_TRDC_CLK_OFF_HS_EN_SHIFT)) & BLK_CTRL_S_AONMIX_LP_HANDSHAKE_WAKEUP_TRDC_CLK_OFF_HS_EN_MASK) + +#define BLK_CTRL_S_AONMIX_LP_HANDSHAKE_FLEXSPI_CLK_OFF_HS_EN_MASK (0x20000U) +#define BLK_CTRL_S_AONMIX_LP_HANDSHAKE_FLEXSPI_CLK_OFF_HS_EN_SHIFT (17U) +/*! FLEXSPI_CLK_OFF_HS_EN - FLEXSPI clock off handshake enable + * 0b0..Disable + * 0b1..Enable + */ +#define BLK_CTRL_S_AONMIX_LP_HANDSHAKE_FLEXSPI_CLK_OFF_HS_EN(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_S_AONMIX_LP_HANDSHAKE_FLEXSPI_CLK_OFF_HS_EN_SHIFT)) & BLK_CTRL_S_AONMIX_LP_HANDSHAKE_FLEXSPI_CLK_OFF_HS_EN_MASK) + +#define BLK_CTRL_S_AONMIX_LP_HANDSHAKE_NIC_APB_CLK_OFF_HS_EN_MASK (0x40000U) +#define BLK_CTRL_S_AONMIX_LP_HANDSHAKE_NIC_APB_CLK_OFF_HS_EN_SHIFT (18U) +/*! NIC_APB_CLK_OFF_HS_EN - NIC_APB clock off handshake enable */ +#define BLK_CTRL_S_AONMIX_LP_HANDSHAKE_NIC_APB_CLK_OFF_HS_EN(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_S_AONMIX_LP_HANDSHAKE_NIC_APB_CLK_OFF_HS_EN_SHIFT)) & BLK_CTRL_S_AONMIX_LP_HANDSHAKE_NIC_APB_CLK_OFF_HS_EN_MASK) + +#define BLK_CTRL_S_AONMIX_LP_HANDSHAKE_NIC_MEDIA_CLK_OFF_HS_EN_MASK (0x80000U) +#define BLK_CTRL_S_AONMIX_LP_HANDSHAKE_NIC_MEDIA_CLK_OFF_HS_EN_SHIFT (19U) +/*! NIC_MEDIA_CLK_OFF_HS_EN - NIC_MEDIA clock off handshake enable + * 0b0..Disable + * 0b1..Enable + */ +#define BLK_CTRL_S_AONMIX_LP_HANDSHAKE_NIC_MEDIA_CLK_OFF_HS_EN(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_S_AONMIX_LP_HANDSHAKE_NIC_MEDIA_CLK_OFF_HS_EN_SHIFT)) & BLK_CTRL_S_AONMIX_LP_HANDSHAKE_NIC_MEDIA_CLK_OFF_HS_EN_MASK) + +#define BLK_CTRL_S_AONMIX_LP_HANDSHAKE_USB_CLK_OFF_HS_EN_MASK (0x100000U) +#define BLK_CTRL_S_AONMIX_LP_HANDSHAKE_USB_CLK_OFF_HS_EN_SHIFT (20U) +/*! USB_CLK_OFF_HS_EN - USB_CLK clock off handshake enable */ +#define BLK_CTRL_S_AONMIX_LP_HANDSHAKE_USB_CLK_OFF_HS_EN(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_S_AONMIX_LP_HANDSHAKE_USB_CLK_OFF_HS_EN_SHIFT)) & BLK_CTRL_S_AONMIX_LP_HANDSHAKE_USB_CLK_OFF_HS_EN_MASK) + +#define BLK_CTRL_S_AONMIX_LP_HANDSHAKE_A55_CLK_OFF_HS_EN_MASK (0x400000U) +#define BLK_CTRL_S_AONMIX_LP_HANDSHAKE_A55_CLK_OFF_HS_EN_SHIFT (22U) +/*! A55_CLK_OFF_HS_EN - A55_CLK clock off handshake enable */ +#define BLK_CTRL_S_AONMIX_LP_HANDSHAKE_A55_CLK_OFF_HS_EN(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_S_AONMIX_LP_HANDSHAKE_A55_CLK_OFF_HS_EN_SHIFT)) & BLK_CTRL_S_AONMIX_LP_HANDSHAKE_A55_CLK_OFF_HS_EN_MASK) + +#define BLK_CTRL_S_AONMIX_LP_HANDSHAKE_ELE_CLK_OFF_HS_EN_MASK (0x800000U) +#define BLK_CTRL_S_AONMIX_LP_HANDSHAKE_ELE_CLK_OFF_HS_EN_SHIFT (23U) +/*! ELE_CLK_OFF_HS_EN - Edgelock Enclave clock off handshake enable + * 0b0..Disable + * 0b1..Enable + */ +#define BLK_CTRL_S_AONMIX_LP_HANDSHAKE_ELE_CLK_OFF_HS_EN(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_S_AONMIX_LP_HANDSHAKE_ELE_CLK_OFF_HS_EN_SHIFT)) & BLK_CTRL_S_AONMIX_LP_HANDSHAKE_ELE_CLK_OFF_HS_EN_MASK) + +#define BLK_CTRL_S_AONMIX_LP_HANDSHAKE_ELE_CLK_ON_HS_EN_MASK (0x1000000U) +#define BLK_CTRL_S_AONMIX_LP_HANDSHAKE_ELE_CLK_ON_HS_EN_SHIFT (24U) +/*! ELE_CLK_ON_HS_EN - Edgelock Enclave clock on handshake enable + * 0b0..Disable + * 0b1..Enable + */ +#define BLK_CTRL_S_AONMIX_LP_HANDSHAKE_ELE_CLK_ON_HS_EN(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_S_AONMIX_LP_HANDSHAKE_ELE_CLK_ON_HS_EN_SHIFT)) & BLK_CTRL_S_AONMIX_LP_HANDSHAKE_ELE_CLK_ON_HS_EN_MASK) + +#define BLK_CTRL_S_AONMIX_LP_HANDSHAKE_A55_CLK_ON_HS_EN_MASK (0x2000000U) +#define BLK_CTRL_S_AONMIX_LP_HANDSHAKE_A55_CLK_ON_HS_EN_SHIFT (25U) +/*! A55_CLK_ON_HS_EN - A55 clock on handshake enable */ +#define BLK_CTRL_S_AONMIX_LP_HANDSHAKE_A55_CLK_ON_HS_EN(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_S_AONMIX_LP_HANDSHAKE_A55_CLK_ON_HS_EN_SHIFT)) & BLK_CTRL_S_AONMIX_LP_HANDSHAKE_A55_CLK_ON_HS_EN_MASK) + +#define BLK_CTRL_S_AONMIX_LP_HANDSHAKE_USB_CLK_ON_HS_EN_MASK (0x8000000U) +#define BLK_CTRL_S_AONMIX_LP_HANDSHAKE_USB_CLK_ON_HS_EN_SHIFT (27U) +/*! USB_CLK_ON_HS_EN - USB Controller clock on handshake enable */ +#define BLK_CTRL_S_AONMIX_LP_HANDSHAKE_USB_CLK_ON_HS_EN(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_S_AONMIX_LP_HANDSHAKE_USB_CLK_ON_HS_EN_SHIFT)) & BLK_CTRL_S_AONMIX_LP_HANDSHAKE_USB_CLK_ON_HS_EN_MASK) + +#define BLK_CTRL_S_AONMIX_LP_HANDSHAKE_NIC_MEDIA_CLK_ON_HS_EN_MASK (0x10000000U) +#define BLK_CTRL_S_AONMIX_LP_HANDSHAKE_NIC_MEDIA_CLK_ON_HS_EN_SHIFT (28U) +/*! NIC_MEDIA_CLK_ON_HS_EN - NIC_MEDIA clock on handshake enable + * 0b0..Disable + * 0b1..Enable + */ +#define BLK_CTRL_S_AONMIX_LP_HANDSHAKE_NIC_MEDIA_CLK_ON_HS_EN(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_S_AONMIX_LP_HANDSHAKE_NIC_MEDIA_CLK_ON_HS_EN_SHIFT)) & BLK_CTRL_S_AONMIX_LP_HANDSHAKE_NIC_MEDIA_CLK_ON_HS_EN_MASK) + +#define BLK_CTRL_S_AONMIX_LP_HANDSHAKE_NIC_APB_CLK_ON_HS_EN_MASK (0x20000000U) +#define BLK_CTRL_S_AONMIX_LP_HANDSHAKE_NIC_APB_CLK_ON_HS_EN_SHIFT (29U) +/*! NIC_APB_CLK_ON_HS_EN - NIC_APB clock on handshake enable */ +#define BLK_CTRL_S_AONMIX_LP_HANDSHAKE_NIC_APB_CLK_ON_HS_EN(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_S_AONMIX_LP_HANDSHAKE_NIC_APB_CLK_ON_HS_EN_SHIFT)) & BLK_CTRL_S_AONMIX_LP_HANDSHAKE_NIC_APB_CLK_ON_HS_EN_MASK) + +#define BLK_CTRL_S_AONMIX_LP_HANDSHAKE_FLEXSPI_CLK_ON_HS_EN_MASK (0x40000000U) +#define BLK_CTRL_S_AONMIX_LP_HANDSHAKE_FLEXSPI_CLK_ON_HS_EN_SHIFT (30U) +/*! FLEXSPI_CLK_ON_HS_EN - FLEXSPI clock on handshake enable + * 0b0..Disable + * 0b1..Enable + */ +#define BLK_CTRL_S_AONMIX_LP_HANDSHAKE_FLEXSPI_CLK_ON_HS_EN(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_S_AONMIX_LP_HANDSHAKE_FLEXSPI_CLK_ON_HS_EN_SHIFT)) & BLK_CTRL_S_AONMIX_LP_HANDSHAKE_FLEXSPI_CLK_ON_HS_EN_MASK) + +#define BLK_CTRL_S_AONMIX_LP_HANDSHAKE_WAKEUPMIX_TRDC_CLK_ON_HS_EN_MASK (0x80000000U) +#define BLK_CTRL_S_AONMIX_LP_HANDSHAKE_WAKEUPMIX_TRDC_CLK_ON_HS_EN_SHIFT (31U) +/*! WAKEUPMIX_TRDC_CLK_ON_HS_EN - WAKEUPMIX_TRDC clock on handshake enable */ +#define BLK_CTRL_S_AONMIX_LP_HANDSHAKE_WAKEUPMIX_TRDC_CLK_ON_HS_EN(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_S_AONMIX_LP_HANDSHAKE_WAKEUPMIX_TRDC_CLK_ON_HS_EN_SHIFT)) & BLK_CTRL_S_AONMIX_LP_HANDSHAKE_WAKEUPMIX_TRDC_CLK_ON_HS_EN_MASK) +/*! @} */ + +/*! @name LP_HANDSHAKE2 - Low power handshake enable */ +/*! @{ */ + +#define BLK_CTRL_S_AONMIX_LP_HANDSHAKE2_ENABLE_MASK (0x1U) +#define BLK_CTRL_S_AONMIX_LP_HANDSHAKE2_ENABLE_SHIFT (0U) +/*! ENABLE - AONMIX TRDC clock on handshake enable + * 0b0..Disable + * 0b1..Enable + */ +#define BLK_CTRL_S_AONMIX_LP_HANDSHAKE2_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_S_AONMIX_LP_HANDSHAKE2_ENABLE_SHIFT)) & BLK_CTRL_S_AONMIX_LP_HANDSHAKE2_ENABLE_MASK) +/*! @} */ + +/*! @name CA55_CPUWAIT - CPUWAIT settings for CA55 CPU */ +/*! @{ */ + +#define BLK_CTRL_S_AONMIX_CA55_CPUWAIT_CPU0_WAIT_MASK (0x1U) +#define BLK_CTRL_S_AONMIX_CA55_CPUWAIT_CPU0_WAIT_SHIFT (0U) +/*! CPU0_WAIT - CPU0_WAIT + * 0b0..Core0 works normally + * 0b1..Core0 stops working + */ +#define BLK_CTRL_S_AONMIX_CA55_CPUWAIT_CPU0_WAIT(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_S_AONMIX_CA55_CPUWAIT_CPU0_WAIT_SHIFT)) & BLK_CTRL_S_AONMIX_CA55_CPUWAIT_CPU0_WAIT_MASK) + +#define BLK_CTRL_S_AONMIX_CA55_CPUWAIT_CPU1_WAIT_MASK (0x2U) +#define BLK_CTRL_S_AONMIX_CA55_CPUWAIT_CPU1_WAIT_SHIFT (1U) +/*! CPU1_WAIT - CPU1_WAIT + * 0b0..Core1 works normally + * 0b1..Core1 stops working + */ +#define BLK_CTRL_S_AONMIX_CA55_CPUWAIT_CPU1_WAIT(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_S_AONMIX_CA55_CPUWAIT_CPU1_WAIT_SHIFT)) & BLK_CTRL_S_AONMIX_CA55_CPUWAIT_CPU1_WAIT_MASK) +/*! @} */ + +/*! @name CA55_RVBARADDR0_L - CA55_RVBARADDR0_L */ +/*! @{ */ + +#define BLK_CTRL_S_AONMIX_CA55_RVBARADDR0_L_ADDR0_L_MASK (0xFFFFFFFFU) +#define BLK_CTRL_S_AONMIX_CA55_RVBARADDR0_L_ADDR0_L_SHIFT (0U) +#define BLK_CTRL_S_AONMIX_CA55_RVBARADDR0_L_ADDR0_L(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_S_AONMIX_CA55_RVBARADDR0_L_ADDR0_L_SHIFT)) & BLK_CTRL_S_AONMIX_CA55_RVBARADDR0_L_ADDR0_L_MASK) +/*! @} */ + +/*! @name CA55_RVBARADDR0_H - CA55_RVBARADDR0_H */ +/*! @{ */ + +#define BLK_CTRL_S_AONMIX_CA55_RVBARADDR0_H_ADDR0_H_MASK (0x3FU) +#define BLK_CTRL_S_AONMIX_CA55_RVBARADDR0_H_ADDR0_H_SHIFT (0U) +#define BLK_CTRL_S_AONMIX_CA55_RVBARADDR0_H_ADDR0_H(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_S_AONMIX_CA55_RVBARADDR0_H_ADDR0_H_SHIFT)) & BLK_CTRL_S_AONMIX_CA55_RVBARADDR0_H_ADDR0_H_MASK) +/*! @} */ + +/*! @name ELE_IRQ_MASK - Mask bits of Edgelock interrupt */ +/*! @{ */ + +#define BLK_CTRL_S_AONMIX_ELE_IRQ_MASK_NOCLK_REF2_MASK (0x1U) +#define BLK_CTRL_S_AONMIX_ELE_IRQ_MASK_NOCLK_REF2_SHIFT (0U) +/*! NOCLK_REF2 - No Clock Reference 2 + * 0b0..Mask interrupt + * 0b1..Unmask interrupt + */ +#define BLK_CTRL_S_AONMIX_ELE_IRQ_MASK_NOCLK_REF2(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_S_AONMIX_ELE_IRQ_MASK_NOCLK_REF2_SHIFT)) & BLK_CTRL_S_AONMIX_ELE_IRQ_MASK_NOCLK_REF2_MASK) + +#define BLK_CTRL_S_AONMIX_ELE_IRQ_MASK_NOCLK_REF1_MASK (0x2U) +#define BLK_CTRL_S_AONMIX_ELE_IRQ_MASK_NOCLK_REF1_SHIFT (1U) +/*! NOCLK_REF1 - No Clock Reference 1 + * 0b0..Mask interrupt + * 0b1..Unmask interrupt + */ +#define BLK_CTRL_S_AONMIX_ELE_IRQ_MASK_NOCLK_REF1(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_S_AONMIX_ELE_IRQ_MASK_NOCLK_REF1_SHIFT)) & BLK_CTRL_S_AONMIX_ELE_IRQ_MASK_NOCLK_REF1_MASK) + +#define BLK_CTRL_S_AONMIX_ELE_IRQ_MASK_LMDA_32K_RESET_REQ_MASK (0x4U) +#define BLK_CTRL_S_AONMIX_ELE_IRQ_MASK_LMDA_32K_RESET_REQ_SHIFT (2U) +/*! LMDA_32K_RESET_REQ - Request Edgelock reset from 32 KHz clock domain, active low, interrupt request */ +#define BLK_CTRL_S_AONMIX_ELE_IRQ_MASK_LMDA_32K_RESET_REQ(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_S_AONMIX_ELE_IRQ_MASK_LMDA_32K_RESET_REQ_SHIFT)) & BLK_CTRL_S_AONMIX_ELE_IRQ_MASK_LMDA_32K_RESET_REQ_MASK) + +#define BLK_CTRL_S_AONMIX_ELE_IRQ_MASK_LMDA_RESET_REQ_MASK (0x8U) +#define BLK_CTRL_S_AONMIX_ELE_IRQ_MASK_LMDA_RESET_REQ_SHIFT (3U) +/*! LMDA_RESET_REQ - Request Edgelock reset, active low, interrupt request + * 0b0..Mask interrupt + * 0b1..Unmask interrupt + */ +#define BLK_CTRL_S_AONMIX_ELE_IRQ_MASK_LMDA_RESET_REQ(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_S_AONMIX_ELE_IRQ_MASK_LMDA_RESET_REQ_SHIFT)) & BLK_CTRL_S_AONMIX_ELE_IRQ_MASK_LMDA_RESET_REQ_MASK) + +#define BLK_CTRL_S_AONMIX_ELE_IRQ_MASK_NOCLK_32K_MASK (0x10U) +#define BLK_CTRL_S_AONMIX_ELE_IRQ_MASK_NOCLK_32K_SHIFT (4U) +/*! NOCLK_32K - Edgelock FDET clock not detected interrupt mask */ +#define BLK_CTRL_S_AONMIX_ELE_IRQ_MASK_NOCLK_32K(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_S_AONMIX_ELE_IRQ_MASK_NOCLK_32K_SHIFT)) & BLK_CTRL_S_AONMIX_ELE_IRQ_MASK_NOCLK_32K_MASK) + +#define BLK_CTRL_S_AONMIX_ELE_IRQ_MASK_LMDA_SYS_FAIL_MASK (0x20U) +#define BLK_CTRL_S_AONMIX_ELE_IRQ_MASK_LMDA_SYS_FAIL_SHIFT (5U) +/*! LMDA_SYS_FAIL - System failure, reset chip or Edgelock + * 0b0..Mask interrupt + * 0b1..Unmask interrupt + */ +#define BLK_CTRL_S_AONMIX_ELE_IRQ_MASK_LMDA_SYS_FAIL(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_S_AONMIX_ELE_IRQ_MASK_LMDA_SYS_FAIL_SHIFT)) & BLK_CTRL_S_AONMIX_ELE_IRQ_MASK_LMDA_SYS_FAIL_MASK) + +#define BLK_CTRL_S_AONMIX_ELE_IRQ_MASK_LC_BRICKED_MASK (0x40U) +#define BLK_CTRL_S_AONMIX_ELE_IRQ_MASK_LC_BRICKED_SHIFT (6U) +/*! LC_BRICKED - LMDA lifecycle is bricked state */ +#define BLK_CTRL_S_AONMIX_ELE_IRQ_MASK_LC_BRICKED(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_S_AONMIX_ELE_IRQ_MASK_LC_BRICKED_SHIFT)) & BLK_CTRL_S_AONMIX_ELE_IRQ_MASK_LC_BRICKED_MASK) + +#define BLK_CTRL_S_AONMIX_ELE_IRQ_MASK_WDG_RESET_MASK (0x100U) +#define BLK_CTRL_S_AONMIX_ELE_IRQ_MASK_WDG_RESET_SHIFT (8U) +/*! WDG_RESET - Watchdog reset request */ +#define BLK_CTRL_S_AONMIX_ELE_IRQ_MASK_WDG_RESET(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_S_AONMIX_ELE_IRQ_MASK_WDG_RESET_SHIFT)) & BLK_CTRL_S_AONMIX_ELE_IRQ_MASK_WDG_RESET_MASK) +/*! @} */ + +/*! @name ELE_RESET_REQ_MASK - Mask bits of ELE reset */ +/*! @{ */ + +#define BLK_CTRL_S_AONMIX_ELE_RESET_REQ_MASK_NOCLK_REF2_MASK (0x1U) +#define BLK_CTRL_S_AONMIX_ELE_RESET_REQ_MASK_NOCLK_REF2_SHIFT (0U) +/*! NOCLK_REF2 - No Clock Reference 2 + * 0b0..Mask interrupt + * 0b1..Unmask interrupt + */ +#define BLK_CTRL_S_AONMIX_ELE_RESET_REQ_MASK_NOCLK_REF2(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_S_AONMIX_ELE_RESET_REQ_MASK_NOCLK_REF2_SHIFT)) & BLK_CTRL_S_AONMIX_ELE_RESET_REQ_MASK_NOCLK_REF2_MASK) + +#define BLK_CTRL_S_AONMIX_ELE_RESET_REQ_MASK_NOCLK_REF1_MASK (0x2U) +#define BLK_CTRL_S_AONMIX_ELE_RESET_REQ_MASK_NOCLK_REF1_SHIFT (1U) +/*! NOCLK_REF1 - No Clock Reference 1 */ +#define BLK_CTRL_S_AONMIX_ELE_RESET_REQ_MASK_NOCLK_REF1(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_S_AONMIX_ELE_RESET_REQ_MASK_NOCLK_REF1_SHIFT)) & BLK_CTRL_S_AONMIX_ELE_RESET_REQ_MASK_NOCLK_REF1_MASK) + +#define BLK_CTRL_S_AONMIX_ELE_RESET_REQ_MASK_LMDA_32K_RESET_REQ_MASK (0x4U) +#define BLK_CTRL_S_AONMIX_ELE_RESET_REQ_MASK_LMDA_32K_RESET_REQ_SHIFT (2U) +/*! LMDA_32K_RESET_REQ - Request Edgelock reset from 32 KHz clock domain, active low, interrupt request + * 0b0..Mask interrupt + * 0b1..Unmask interrupt + */ +#define BLK_CTRL_S_AONMIX_ELE_RESET_REQ_MASK_LMDA_32K_RESET_REQ(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_S_AONMIX_ELE_RESET_REQ_MASK_LMDA_32K_RESET_REQ_SHIFT)) & BLK_CTRL_S_AONMIX_ELE_RESET_REQ_MASK_LMDA_32K_RESET_REQ_MASK) + +#define BLK_CTRL_S_AONMIX_ELE_RESET_REQ_MASK_LMDA_RESET_REQ_MASK (0x8U) +#define BLK_CTRL_S_AONMIX_ELE_RESET_REQ_MASK_LMDA_RESET_REQ_SHIFT (3U) +/*! LMDA_RESET_REQ - Request Edgelock reset, active low, interrupt request + * 0b0..Mask interrupt + * 0b1..Unmask interrupt + */ +#define BLK_CTRL_S_AONMIX_ELE_RESET_REQ_MASK_LMDA_RESET_REQ(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_S_AONMIX_ELE_RESET_REQ_MASK_LMDA_RESET_REQ_SHIFT)) & BLK_CTRL_S_AONMIX_ELE_RESET_REQ_MASK_LMDA_RESET_REQ_MASK) + +#define BLK_CTRL_S_AONMIX_ELE_RESET_REQ_MASK_NOCLK_32K_MASK (0x10U) +#define BLK_CTRL_S_AONMIX_ELE_RESET_REQ_MASK_NOCLK_32K_SHIFT (4U) +/*! NOCLK_32K - Edgelock FDET clock not detected interrupt mask */ +#define BLK_CTRL_S_AONMIX_ELE_RESET_REQ_MASK_NOCLK_32K(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_S_AONMIX_ELE_RESET_REQ_MASK_NOCLK_32K_SHIFT)) & BLK_CTRL_S_AONMIX_ELE_RESET_REQ_MASK_NOCLK_32K_MASK) + +#define BLK_CTRL_S_AONMIX_ELE_RESET_REQ_MASK_LMDA_SYS_FAIL_MASK (0x20U) +#define BLK_CTRL_S_AONMIX_ELE_RESET_REQ_MASK_LMDA_SYS_FAIL_SHIFT (5U) +/*! LMDA_SYS_FAIL - System failure, reset chip or Edgelock + * 0b0..Mask interrupt + * 0b1..Unmask interrupt + */ +#define BLK_CTRL_S_AONMIX_ELE_RESET_REQ_MASK_LMDA_SYS_FAIL(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_S_AONMIX_ELE_RESET_REQ_MASK_LMDA_SYS_FAIL_SHIFT)) & BLK_CTRL_S_AONMIX_ELE_RESET_REQ_MASK_LMDA_SYS_FAIL_MASK) + +#define BLK_CTRL_S_AONMIX_ELE_RESET_REQ_MASK_LC_BRICKED_MASK (0x40U) +#define BLK_CTRL_S_AONMIX_ELE_RESET_REQ_MASK_LC_BRICKED_SHIFT (6U) +/*! LC_BRICKED - LMDA lifecycle is bricked state */ +#define BLK_CTRL_S_AONMIX_ELE_RESET_REQ_MASK_LC_BRICKED(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_S_AONMIX_ELE_RESET_REQ_MASK_LC_BRICKED_SHIFT)) & BLK_CTRL_S_AONMIX_ELE_RESET_REQ_MASK_LC_BRICKED_MASK) + +#define BLK_CTRL_S_AONMIX_ELE_RESET_REQ_MASK_PUF_RESET_MASK (0x80U) +#define BLK_CTRL_S_AONMIX_ELE_RESET_REQ_MASK_PUF_RESET_SHIFT (7U) +/*! PUF_RESET - PUF reset request + * 0b0..Mask interrupt + * 0b1..Unmask interrupt + */ +#define BLK_CTRL_S_AONMIX_ELE_RESET_REQ_MASK_PUF_RESET(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_S_AONMIX_ELE_RESET_REQ_MASK_PUF_RESET_SHIFT)) & BLK_CTRL_S_AONMIX_ELE_RESET_REQ_MASK_PUF_RESET_MASK) + +#define BLK_CTRL_S_AONMIX_ELE_RESET_REQ_MASK_WDG_RESET_MASK (0x100U) +#define BLK_CTRL_S_AONMIX_ELE_RESET_REQ_MASK_WDG_RESET_SHIFT (8U) +/*! WDG_RESET - Watchdog reset request */ +#define BLK_CTRL_S_AONMIX_ELE_RESET_REQ_MASK_WDG_RESET(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_S_AONMIX_ELE_RESET_REQ_MASK_WDG_RESET_SHIFT)) & BLK_CTRL_S_AONMIX_ELE_RESET_REQ_MASK_WDG_RESET_MASK) +/*! @} */ + +/*! @name ELE_HALT_ST - ELE halt status */ +/*! @{ */ + +#define BLK_CTRL_S_AONMIX_ELE_HALT_ST_ELE_HALT_ACK_MASK (0x1U) +#define BLK_CTRL_S_AONMIX_ELE_HALT_ST_ELE_HALT_ACK_SHIFT (0U) +/*! ELE_HALT_ACK - EdgeLock halt and clock status + * 0b0..EdgeLock is not fully halted and its clocks must be enabled + * 0b0..Mask interrupt + * 0b1..EdgeLock is fully halted indicating clocks may be removed + * 0b1..Unmask interrupt + */ +#define BLK_CTRL_S_AONMIX_ELE_HALT_ST_ELE_HALT_ACK(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_S_AONMIX_ELE_HALT_ST_ELE_HALT_ACK_SHIFT)) & BLK_CTRL_S_AONMIX_ELE_HALT_ST_ELE_HALT_ACK_MASK) + +#define BLK_CTRL_S_AONMIX_ELE_HALT_ST_ELE_HALT_EXIT_IRQ_CLR_MASK (0x100U) +#define BLK_CTRL_S_AONMIX_ELE_HALT_ST_ELE_HALT_EXIT_IRQ_CLR_SHIFT (8U) +/*! ELE_HALT_EXIT_IRQ_CLR - EdgeLock halt exit interrupt clear + * 0b0..Remove the clear signal. This bit is not self-clearing and need SW to clear. + * 0b1..Clear EdgeLock halt exit interrupt + */ +#define BLK_CTRL_S_AONMIX_ELE_HALT_ST_ELE_HALT_EXIT_IRQ_CLR(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_S_AONMIX_ELE_HALT_ST_ELE_HALT_EXIT_IRQ_CLR_SHIFT)) & BLK_CTRL_S_AONMIX_ELE_HALT_ST_ELE_HALT_EXIT_IRQ_CLR_MASK) +/*! @} */ + +/*! @name CA55_MODE - Control the boot mode of two ca55 cores */ +/*! @{ */ + +#define BLK_CTRL_S_AONMIX_CA55_MODE_AA64NAA32_MASK (0x3U) +#define BLK_CTRL_S_AONMIX_CA55_MODE_AA64NAA32_SHIFT (0U) +/*! AA64NAA32 - Core0 initial mode control + * 0b00..State after reset is aarch32 + * 0b01..State after reset is aarch64 + */ +#define BLK_CTRL_S_AONMIX_CA55_MODE_AA64NAA32(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_S_AONMIX_CA55_MODE_AA64NAA32_SHIFT)) & BLK_CTRL_S_AONMIX_CA55_MODE_AA64NAA32_MASK) +/*! @} */ + +/*! @name WDOG_ANY_MASK - WDOG any mask */ +/*! @{ */ + +#define BLK_CTRL_S_AONMIX_WDOG_ANY_MASK_WDOG1_MASK (0x1U) +#define BLK_CTRL_S_AONMIX_WDOG_ANY_MASK_WDOG1_SHIFT (0U) +/*! WDOG1 - WDOG1 to WDOG_ANY mask + * 0b0..DISABLE + * 0b1..ENABLE + */ +#define BLK_CTRL_S_AONMIX_WDOG_ANY_MASK_WDOG1(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_S_AONMIX_WDOG_ANY_MASK_WDOG1_SHIFT)) & BLK_CTRL_S_AONMIX_WDOG_ANY_MASK_WDOG1_MASK) + +#define BLK_CTRL_S_AONMIX_WDOG_ANY_MASK_WDOG2_MASK (0x2U) +#define BLK_CTRL_S_AONMIX_WDOG_ANY_MASK_WDOG2_SHIFT (1U) +/*! WDOG2 - WDOG2 to WDOG_ANY mask + * 0b0..DISABLE + * 0b1..ENABLE + */ +#define BLK_CTRL_S_AONMIX_WDOG_ANY_MASK_WDOG2(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_S_AONMIX_WDOG_ANY_MASK_WDOG2_SHIFT)) & BLK_CTRL_S_AONMIX_WDOG_ANY_MASK_WDOG2_MASK) + +#define BLK_CTRL_S_AONMIX_WDOG_ANY_MASK_WDOG3_MASK (0x4U) +#define BLK_CTRL_S_AONMIX_WDOG_ANY_MASK_WDOG3_SHIFT (2U) +/*! WDOG3 - WDOG3 to WDOG_ANY mask + * 0b0..DISABLE + * 0b1..ENABLE + */ +#define BLK_CTRL_S_AONMIX_WDOG_ANY_MASK_WDOG3(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_S_AONMIX_WDOG_ANY_MASK_WDOG3_SHIFT)) & BLK_CTRL_S_AONMIX_WDOG_ANY_MASK_WDOG3_MASK) + +#define BLK_CTRL_S_AONMIX_WDOG_ANY_MASK_WDOG4_MASK (0x8U) +#define BLK_CTRL_S_AONMIX_WDOG_ANY_MASK_WDOG4_SHIFT (3U) +/*! WDOG4 - WDOG4 to WDOG_ANY mask + * 0b0..DISABLE + * 0b1..ENABLE + */ +#define BLK_CTRL_S_AONMIX_WDOG_ANY_MASK_WDOG4(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_S_AONMIX_WDOG_ANY_MASK_WDOG4_SHIFT)) & BLK_CTRL_S_AONMIX_WDOG_ANY_MASK_WDOG4_MASK) + +#define BLK_CTRL_S_AONMIX_WDOG_ANY_MASK_WDOG5_MASK (0x10U) +#define BLK_CTRL_S_AONMIX_WDOG_ANY_MASK_WDOG5_SHIFT (4U) +/*! WDOG5 - WDOG5 to WDOG_ANY mask + * 0b0..DISABLE + * 0b1..ENABLE + */ +#define BLK_CTRL_S_AONMIX_WDOG_ANY_MASK_WDOG5(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_S_AONMIX_WDOG_ANY_MASK_WDOG5_SHIFT)) & BLK_CTRL_S_AONMIX_WDOG_ANY_MASK_WDOG5_MASK) +/*! @} */ + +/*! @name ELEV1_IPI_NOCLK_REF1 - ELEV1_IPI_NOCLK_REF1 clear */ +/*! @{ */ + +#define BLK_CTRL_S_AONMIX_ELEV1_IPI_NOCLK_REF1_SLOW_CLEAR_MASK (0x1U) +#define BLK_CTRL_S_AONMIX_ELEV1_IPI_NOCLK_REF1_SLOW_CLEAR_SHIFT (0U) +/*! SLOW_CLEAR - Interrupt clear + * 0b0..Interrupt not cleared + * 0b1..Interrupt cleared + */ +#define BLK_CTRL_S_AONMIX_ELEV1_IPI_NOCLK_REF1_SLOW_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_S_AONMIX_ELEV1_IPI_NOCLK_REF1_SLOW_CLEAR_SHIFT)) & BLK_CTRL_S_AONMIX_ELEV1_IPI_NOCLK_REF1_SLOW_CLEAR_MASK) +/*! @} */ + +/*! @name L2_OCRAM_STICKY - L2 ocram enable bit */ +/*! @{ */ + +#define BLK_CTRL_S_AONMIX_L2_OCRAM_STICKY_OCRAM_EN_MASK (0x1U) +#define BLK_CTRL_S_AONMIX_L2_OCRAM_STICKY_OCRAM_EN_SHIFT (0U) +/*! OCRAM_EN - L2 cache as ocram enable bit + * 0b0..L2 cache used as OCRAM once written to 0, cannot be written to 1 again unless reset + * 0b1..L2 cache used as OCRAM + */ +#define BLK_CTRL_S_AONMIX_L2_OCRAM_STICKY_OCRAM_EN(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_S_AONMIX_L2_OCRAM_STICKY_OCRAM_EN_SHIFT)) & BLK_CTRL_S_AONMIX_L2_OCRAM_STICKY_OCRAM_EN_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group BLK_CTRL_S_AONMIX_Register_Masks */ + + +/* BLK_CTRL_S_AONMIX - Peripheral instance base addresses */ +/** Peripheral BLK_CTRL_S_AONMIX2 base address */ +#define BLK_CTRL_S_AONMIX2_BASE (0x444F0000u) +/** Peripheral BLK_CTRL_S_AONMIX2 base pointer */ +#define BLK_CTRL_S_AONMIX2 ((BLK_CTRL_S_AONMIX_Type *)BLK_CTRL_S_AONMIX2_BASE) +/** Array initializer of BLK_CTRL_S_AONMIX peripheral base addresses */ +#define BLK_CTRL_S_AONMIX_BASE_ADDRS { BLK_CTRL_S_AONMIX2_BASE } +/** Array initializer of BLK_CTRL_S_AONMIX peripheral base pointers */ +#define BLK_CTRL_S_AONMIX_BASE_PTRS { BLK_CTRL_S_AONMIX2 } + +/*! + * @} + */ /* end of group BLK_CTRL_S_AONMIX_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- BLK_CTRL_WAKEUPMIX Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup BLK_CTRL_WAKEUPMIX_Peripheral_Access_Layer BLK_CTRL_WAKEUPMIX Peripheral Access Layer + * @{ + */ + +/** BLK_CTRL_WAKEUPMIX - Register Layout Typedef */ +typedef struct { + uint8_t RESERVED_0[12]; + __IO uint32_t LP_HANDSHAKE; /**< CAN2 and ENET2 low power handshake bits, offset: 0xC */ + uint8_t RESERVED_1[16]; + __IO uint32_t MQS_SETTING; /**< MQS Settings for MQS2, offset: 0x20 */ + __IO uint32_t SAI_CLK_SEL; /**< SAI2 and SAI3 MCLK1~3 CLK root mux settings, offset: 0x24 */ + __IO uint32_t GPR; /**< ENET QOS control signals, offset: 0x28 */ + __IO uint32_t ENET_CLK_SEL; /**< ENET CLK direction selection, offset: 0x2C */ + uint8_t RESERVED_2[4]; + __I uint32_t VOLT_DETECT; /**< Voltage detectors output, offset: 0x34 */ + __IO uint32_t I3C2_WAKEUP; /**< I3C2 WAKEUPX CLR, offset: 0x38 */ + __IO uint32_t IPG_DEBUG_CA55C0; /**< IPG DEBUG mask bit for CA55 core0, offset: 0x3C */ + uint8_t RESERVED_3[4]; + __IO uint32_t AXI_ATTR_CFG; /**< AXI CACHE OVERRITE BIT, offset: 0x44 */ + __IO uint32_t I3C2_SDA_IRQ; /**< I3C SDA IRQ Control, offset: 0x48 */ + uint8_t RESERVED_4[4]; + __IO uint32_t SSI_MST_WKUP2AON; /**< Low power control for SSI_MST_WKUP2AON, offset: 0x50 */ + __IO uint32_t SSI_MST_WKUP2NIC; /**< Low power control for SSI_MST_WKUP2NIC, offset: 0x54 */ + __IO uint32_t SSI_SLV_AON2WKUP; /**< Low power control for SSI_SLV_AON2WKUP, offset: 0x58 */ + __IO uint32_t SSI_SLV_NIC2WKUP; /**< Low power control for SSI_SLV_NIC2WKUP, offset: 0x5C */ +} BLK_CTRL_WAKEUPMIX_Type; + +/* ---------------------------------------------------------------------------- + -- BLK_CTRL_WAKEUPMIX Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup BLK_CTRL_WAKEUPMIX_Register_Masks BLK_CTRL_WAKEUPMIX Register Masks + * @{ + */ + +/*! @name LP_HANDSHAKE - CAN2 and ENET2 low power handshake bits */ +/*! @{ */ + +#define BLK_CTRL_WAKEUPMIX_LP_HANDSHAKE_ENET2_STOP_ACK_MASK (0x1U) +#define BLK_CTRL_WAKEUPMIX_LP_HANDSHAKE_ENET2_STOP_ACK_SHIFT (0U) +/*! ENET2_STOP_ACK - ENET1_STOP_ACK */ +#define BLK_CTRL_WAKEUPMIX_LP_HANDSHAKE_ENET2_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_LP_HANDSHAKE_ENET2_STOP_ACK_SHIFT)) & BLK_CTRL_WAKEUPMIX_LP_HANDSHAKE_ENET2_STOP_ACK_MASK) + +#define BLK_CTRL_WAKEUPMIX_LP_HANDSHAKE_ENET2_STOP_MASK (0x2U) +#define BLK_CTRL_WAKEUPMIX_LP_HANDSHAKE_ENET2_STOP_SHIFT (1U) +/*! ENET2_STOP - ENET1_STOP */ +#define BLK_CTRL_WAKEUPMIX_LP_HANDSHAKE_ENET2_STOP(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_LP_HANDSHAKE_ENET2_STOP_SHIFT)) & BLK_CTRL_WAKEUPMIX_LP_HANDSHAKE_ENET2_STOP_MASK) + +#define BLK_CTRL_WAKEUPMIX_LP_HANDSHAKE_CAN2_STOP_MASK (0x4U) +#define BLK_CTRL_WAKEUPMIX_LP_HANDSHAKE_CAN2_STOP_SHIFT (2U) +/*! CAN2_STOP - CAN2_STOP */ +#define BLK_CTRL_WAKEUPMIX_LP_HANDSHAKE_CAN2_STOP(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_LP_HANDSHAKE_CAN2_STOP_SHIFT)) & BLK_CTRL_WAKEUPMIX_LP_HANDSHAKE_CAN2_STOP_MASK) + +#define BLK_CTRL_WAKEUPMIX_LP_HANDSHAKE_DUMMY_MASK (0x3F8U) +#define BLK_CTRL_WAKEUPMIX_LP_HANDSHAKE_DUMMY_SHIFT (3U) +/*! DUMMY - DUMMY + * 0b0000000..Module does not enter debug halted mode with CM33 + * 0b0000001..Module enters debug halted mode when CM33 is debug halted + */ +#define BLK_CTRL_WAKEUPMIX_LP_HANDSHAKE_DUMMY(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_LP_HANDSHAKE_DUMMY_SHIFT)) & BLK_CTRL_WAKEUPMIX_LP_HANDSHAKE_DUMMY_MASK) +/*! @} */ + +/*! @name MQS_SETTING - MQS Settings for MQS2 */ +/*! @{ */ + +#define BLK_CTRL_WAKEUPMIX_MQS_SETTING_SAI_SEL_MASK (0x1U) +#define BLK_CTRL_WAKEUPMIX_MQS_SETTING_SAI_SEL_SHIFT (0U) +/*! SAI_SEL - SAI select + * 0b0..SAI2 + * 0b1..SAI3 + */ +#define BLK_CTRL_WAKEUPMIX_MQS_SETTING_SAI_SEL(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_MQS_SETTING_SAI_SEL_SHIFT)) & BLK_CTRL_WAKEUPMIX_MQS_SETTING_SAI_SEL_MASK) + +#define BLK_CTRL_WAKEUPMIX_MQS_SETTING_MQS_EN_MASK (0x2U) +#define BLK_CTRL_WAKEUPMIX_MQS_SETTING_MQS_EN_SHIFT (1U) +/*! MQS_EN - MQS Enable + * 0b0..MQS2 is disabled + * 0b1..MQS2 is enabled + */ +#define BLK_CTRL_WAKEUPMIX_MQS_SETTING_MQS_EN(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_MQS_SETTING_MQS_EN_SHIFT)) & BLK_CTRL_WAKEUPMIX_MQS_SETTING_MQS_EN_MASK) + +#define BLK_CTRL_WAKEUPMIX_MQS_SETTING_SOFT_RESET_MASK (0x4U) +#define BLK_CTRL_WAKEUPMIX_MQS_SETTING_SOFT_RESET_SHIFT (2U) +/*! SOFT_RESET - Software Reset + * 0b0..Reset is enabled + * 0b1..Reset is disabled + */ +#define BLK_CTRL_WAKEUPMIX_MQS_SETTING_SOFT_RESET(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_MQS_SETTING_SOFT_RESET_SHIFT)) & BLK_CTRL_WAKEUPMIX_MQS_SETTING_SOFT_RESET_MASK) + +#define BLK_CTRL_WAKEUPMIX_MQS_SETTING_OVERSAMPLE_MASK (0x8U) +#define BLK_CTRL_WAKEUPMIX_MQS_SETTING_OVERSAMPLE_SHIFT (3U) +/*! OVERSAMPLE - Oversample enable + * 0b0..32 + * 0b1..64 + */ +#define BLK_CTRL_WAKEUPMIX_MQS_SETTING_OVERSAMPLE(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_MQS_SETTING_OVERSAMPLE_SHIFT)) & BLK_CTRL_WAKEUPMIX_MQS_SETTING_OVERSAMPLE_MASK) + +#define BLK_CTRL_WAKEUPMIX_MQS_SETTING_CLK_DIVIDE_MASK (0xFF00U) +#define BLK_CTRL_WAKEUPMIX_MQS_SETTING_CLK_DIVIDE_SHIFT (8U) +/*! CLK_DIVIDE - Clock divide factor configuration + * 0b00000000..hmclk frequency + * 0b00000001..hmclk frequency x 1/2 + * 0b00000010..hmclk frequency x 1/3 + * 0b00000011..hmclk frequency x 1/4 + * 0b00000100-0b11111111..mclk frequency = hmclk frequency x 1/(n+1) + */ +#define BLK_CTRL_WAKEUPMIX_MQS_SETTING_CLK_DIVIDE(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_MQS_SETTING_CLK_DIVIDE_SHIFT)) & BLK_CTRL_WAKEUPMIX_MQS_SETTING_CLK_DIVIDE_MASK) +/*! @} */ + +/*! @name SAI_CLK_SEL - SAI2 and SAI3 MCLK1~3 CLK root mux settings */ +/*! @{ */ + +#define BLK_CTRL_WAKEUPMIX_SAI_CLK_SEL_SAI2_MCLK1_MASK (0x1U) +#define BLK_CTRL_WAKEUPMIX_SAI_CLK_SEL_SAI2_MCLK1_SHIFT (0U) +/*! SAI2_MCLK1 - SAI2 MCLK1 clock source selection + * 0b0..SAI2 CLK_ROOT from CCM + * 0b1..SAI2 MCLK + */ +#define BLK_CTRL_WAKEUPMIX_SAI_CLK_SEL_SAI2_MCLK1(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_SAI_CLK_SEL_SAI2_MCLK1_SHIFT)) & BLK_CTRL_WAKEUPMIX_SAI_CLK_SEL_SAI2_MCLK1_MASK) + +#define BLK_CTRL_WAKEUPMIX_SAI_CLK_SEL_SAI2_MCLK2_MASK (0xEU) +#define BLK_CTRL_WAKEUPMIX_SAI_CLK_SEL_SAI2_MCLK2_SHIFT (1U) +/*! SAI2_MCLK2 - SAI2 MCLK2 clock source selection + * 0b000..SAI1 CLK ROOT from CCM + * 0b001..SAI2 CLK ROOT from CCM + * 0b010..SAI3 CLK ROOT from CCM + * 0b011..SAI1_MCLK from IOMUX + * 0b100..SAI2_MCLK from IOMUX + * 0b101..SAI3_MCLK from IOMUX + * 0b110..SPDIF CLK ROOT from CCM + * 0b111..SPDIF RX clock + */ +#define BLK_CTRL_WAKEUPMIX_SAI_CLK_SEL_SAI2_MCLK2(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_SAI_CLK_SEL_SAI2_MCLK2_SHIFT)) & BLK_CTRL_WAKEUPMIX_SAI_CLK_SEL_SAI2_MCLK2_MASK) + +#define BLK_CTRL_WAKEUPMIX_SAI_CLK_SEL_SAI2_MCLK3_MASK (0x70U) +#define BLK_CTRL_WAKEUPMIX_SAI_CLK_SEL_SAI2_MCLK3_SHIFT (4U) +/*! SAI2_MCLK3 - SAI2 MCLK3 clock source selection + * 0b000..SAI1 CLK ROOT from CCM + * 0b001..SAI2 CLK ROOT from CCM + * 0b010..SAI3 CLK ROOT from CCM + * 0b011..SAI1_MCLK from IOMUX + * 0b100..SAI2_MCLK from IOMUX + * 0b101..SAI3_MCLK from IOMUX + * 0b110..SPDIF CLK ROOT from CCM + * 0b111..SPDIF RX clock + */ +#define BLK_CTRL_WAKEUPMIX_SAI_CLK_SEL_SAI2_MCLK3(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_SAI_CLK_SEL_SAI2_MCLK3_SHIFT)) & BLK_CTRL_WAKEUPMIX_SAI_CLK_SEL_SAI2_MCLK3_MASK) + +#define BLK_CTRL_WAKEUPMIX_SAI_CLK_SEL_SAI3_MCLK1_MASK (0x10000U) +#define BLK_CTRL_WAKEUPMIX_SAI_CLK_SEL_SAI3_MCLK1_SHIFT (16U) +/*! SAI3_MCLK1 - SAI3 MCLK1 clock source selection + * 0b0..SAI3 CLK_ROOT from CCM + * 0b1..SAI3 MCLK + */ +#define BLK_CTRL_WAKEUPMIX_SAI_CLK_SEL_SAI3_MCLK1(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_SAI_CLK_SEL_SAI3_MCLK1_SHIFT)) & BLK_CTRL_WAKEUPMIX_SAI_CLK_SEL_SAI3_MCLK1_MASK) + +#define BLK_CTRL_WAKEUPMIX_SAI_CLK_SEL_SAI3_MCLK2_MASK (0xE0000U) +#define BLK_CTRL_WAKEUPMIX_SAI_CLK_SEL_SAI3_MCLK2_SHIFT (17U) +/*! SAI3_MCLK2 - SAI2 MCLK2 clock source selection + * 0b000..SAI1 CLK ROOT from CCM + * 0b001..SAI2 CLK ROOT from CCM + * 0b010..SAI3 CLK ROOT from CCM + * 0b011..SAI1_MCLK from IOMUX + * 0b100..SAI2_MCLK from IOMUX + * 0b101..SAI3_MCLK from IOMUX + * 0b110..SPDIF CLK ROOT from CCM + * 0b111..SPDIF RX clock + */ +#define BLK_CTRL_WAKEUPMIX_SAI_CLK_SEL_SAI3_MCLK2(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_SAI_CLK_SEL_SAI3_MCLK2_SHIFT)) & BLK_CTRL_WAKEUPMIX_SAI_CLK_SEL_SAI3_MCLK2_MASK) + +#define BLK_CTRL_WAKEUPMIX_SAI_CLK_SEL_SAI3_MCLK3_MASK (0x700000U) +#define BLK_CTRL_WAKEUPMIX_SAI_CLK_SEL_SAI3_MCLK3_SHIFT (20U) +/*! SAI3_MCLK3 - SAI3 MCLK3 clock source selection + * 0b000..SAI1 CLK ROOT from CCM + * 0b001..SAI2 CLK ROOT from CCM + * 0b010..SAI3 CLK ROOT from CCM + * 0b011..SAI1_MCLK from IOMUX + * 0b100..SAI2_MCLK from IOMUX + * 0b101..SAI3_MCLK from IOMUX + * 0b110..SPDIF CLK ROOT from CCM + * 0b111..SPDIF RX clock + */ +#define BLK_CTRL_WAKEUPMIX_SAI_CLK_SEL_SAI3_MCLK3(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_SAI_CLK_SEL_SAI3_MCLK3_SHIFT)) & BLK_CTRL_WAKEUPMIX_SAI_CLK_SEL_SAI3_MCLK3_MASK) +/*! @} */ + +/*! @name GPR - ENET QOS control signals */ +/*! @{ */ + +#define BLK_CTRL_WAKEUPMIX_GPR_ENABLE_MASK (0x1U) +#define BLK_CTRL_WAKEUPMIX_GPR_ENABLE_SHIFT (0U) +/*! ENABLE - ENET QOS enable + * 0b0..ENET QoS is disabled + * 0b1..ENET QoS is enabled + */ +#define BLK_CTRL_WAKEUPMIX_GPR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_GPR_ENABLE_SHIFT)) & BLK_CTRL_WAKEUPMIX_GPR_ENABLE_MASK) + +#define BLK_CTRL_WAKEUPMIX_GPR_MODE_MASK (0xEU) +#define BLK_CTRL_WAKEUPMIX_GPR_MODE_SHIFT (1U) +/*! MODE - ENET QOS mode selection + * 0b000..MII mode is selected + * 0b001..RGMII mode is selected + * 0b100..RMII mode is selected + */ +#define BLK_CTRL_WAKEUPMIX_GPR_MODE(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_GPR_MODE_SHIFT)) & BLK_CTRL_WAKEUPMIX_GPR_MODE_MASK) + +#define BLK_CTRL_WAKEUPMIX_GPR_DIS_CRC_CHK_MASK (0x10U) +#define BLK_CTRL_WAKEUPMIX_GPR_DIS_CRC_CHK_SHIFT (4U) +/*! DIS_CRC_CHK - Disable ENET QoS CRC check + * 0b0..CRC check is disabled + * 0b1..CRC check is enabled + */ +#define BLK_CTRL_WAKEUPMIX_GPR_DIS_CRC_CHK(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_GPR_DIS_CRC_CHK_SHIFT)) & BLK_CTRL_WAKEUPMIX_GPR_DIS_CRC_CHK_MASK) +/*! @} */ + +/*! @name ENET_CLK_SEL - ENET CLK direction selection */ +/*! @{ */ + +#define BLK_CTRL_WAKEUPMIX_ENET_CLK_SEL_enet1_clk_tx_clk_sel_MASK (0x1U) +#define BLK_CTRL_WAKEUPMIX_ENET_CLK_SEL_enet1_clk_tx_clk_sel_SHIFT (0U) +/*! enet1_clk_tx_clk_sel - Direction of TX_CLK of ENET QOS + * 0b0..ENET QOS TX CLK is Input + * 0b1..ENET QOS TX CLK is Output + */ +#define BLK_CTRL_WAKEUPMIX_ENET_CLK_SEL_enet1_clk_tx_clk_sel(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_ENET_CLK_SEL_enet1_clk_tx_clk_sel_SHIFT)) & BLK_CTRL_WAKEUPMIX_ENET_CLK_SEL_enet1_clk_tx_clk_sel_MASK) + +#define BLK_CTRL_WAKEUPMIX_ENET_CLK_SEL_enet2_regular_tx_clk_sel_MASK (0x2U) +#define BLK_CTRL_WAKEUPMIX_ENET_CLK_SEL_enet2_regular_tx_clk_sel_SHIFT (1U) +/*! enet2_regular_tx_clk_sel - Direction of TX_CLK of ENET + * 0b0..ENET TX CLK is Input + * 0b1..ENET TX CLK is Output + */ +#define BLK_CTRL_WAKEUPMIX_ENET_CLK_SEL_enet2_regular_tx_clk_sel(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_ENET_CLK_SEL_enet2_regular_tx_clk_sel_SHIFT)) & BLK_CTRL_WAKEUPMIX_ENET_CLK_SEL_enet2_regular_tx_clk_sel_MASK) +/*! @} */ + +/*! @name VOLT_DETECT - Voltage detectors output */ +/*! @{ */ + +#define BLK_CTRL_WAKEUPMIX_VOLT_DETECT_SUPPLY_DETECTOR_AON_MASK (0x1U) +#define BLK_CTRL_WAKEUPMIX_VOLT_DETECT_SUPPLY_DETECTOR_AON_SHIFT (0U) +/*! SUPPLY_DETECTOR_AON - Voltage detectors output of AON */ +#define BLK_CTRL_WAKEUPMIX_VOLT_DETECT_SUPPLY_DETECTOR_AON(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_VOLT_DETECT_SUPPLY_DETECTOR_AON_SHIFT)) & BLK_CTRL_WAKEUPMIX_VOLT_DETECT_SUPPLY_DETECTOR_AON_MASK) + +#define BLK_CTRL_WAKEUPMIX_VOLT_DETECT_SUPPLY_DETECTOR_GPIO_MASK (0x2U) +#define BLK_CTRL_WAKEUPMIX_VOLT_DETECT_SUPPLY_DETECTOR_GPIO_SHIFT (1U) +/*! SUPPLY_DETECTOR_GPIO - Voltage detectors output of GPIO */ +#define BLK_CTRL_WAKEUPMIX_VOLT_DETECT_SUPPLY_DETECTOR_GPIO(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_VOLT_DETECT_SUPPLY_DETECTOR_GPIO_SHIFT)) & BLK_CTRL_WAKEUPMIX_VOLT_DETECT_SUPPLY_DETECTOR_GPIO_MASK) + +#define BLK_CTRL_WAKEUPMIX_VOLT_DETECT_SUPPLY_DETECTOR_SD2_MASK (0x4U) +#define BLK_CTRL_WAKEUPMIX_VOLT_DETECT_SUPPLY_DETECTOR_SD2_SHIFT (2U) +/*! SUPPLY_DETECTOR_SD2 - Voltage detectors output of SD2 */ +#define BLK_CTRL_WAKEUPMIX_VOLT_DETECT_SUPPLY_DETECTOR_SD2(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_VOLT_DETECT_SUPPLY_DETECTOR_SD2_SHIFT)) & BLK_CTRL_WAKEUPMIX_VOLT_DETECT_SUPPLY_DETECTOR_SD2_MASK) + +#define BLK_CTRL_WAKEUPMIX_VOLT_DETECT_SUPPLY_DETECTOR_WAKEUP_MASK (0x8U) +#define BLK_CTRL_WAKEUPMIX_VOLT_DETECT_SUPPLY_DETECTOR_WAKEUP_SHIFT (3U) +/*! SUPPLY_DETECTOR_WAKEUP - Voltage detectors output of WAKEUP */ +#define BLK_CTRL_WAKEUPMIX_VOLT_DETECT_SUPPLY_DETECTOR_WAKEUP(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_VOLT_DETECT_SUPPLY_DETECTOR_WAKEUP_SHIFT)) & BLK_CTRL_WAKEUPMIX_VOLT_DETECT_SUPPLY_DETECTOR_WAKEUP_MASK) +/*! @} */ + +/*! @name I3C2_WAKEUP - I3C2 WAKEUPX CLR */ +/*! @{ */ + +#define BLK_CTRL_WAKEUPMIX_I3C2_WAKEUP_IRQ_CLR_MASK (0x1U) +#define BLK_CTRL_WAKEUPMIX_I3C2_WAKEUP_IRQ_CLR_SHIFT (0U) +#define BLK_CTRL_WAKEUPMIX_I3C2_WAKEUP_IRQ_CLR(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_I3C2_WAKEUP_IRQ_CLR_SHIFT)) & BLK_CTRL_WAKEUPMIX_I3C2_WAKEUP_IRQ_CLR_MASK) +/*! @} */ + +/*! @name IPG_DEBUG_CA55C0 - IPG DEBUG mask bit for CA55 core0 */ +/*! @{ */ + +#define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_CAN2_MASK (0x1U) +#define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_CAN2_SHIFT (0U) +/*! CAN2 + * 0b0..Module does not enter debug halted mode with A55 + * 0b1..Module enters debug halted mode when A55 is debug halted + */ +#define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_CAN2(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_CAN2_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_CAN2_MASK) + +#define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_EDMA2_MASK (0x2U) +#define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_EDMA2_SHIFT (1U) +/*! EDMA2 + * 0b0..Module does not enter debug halted mode with A55 + * 0b1..Module enters debug halted mode when A55 is debug halted + */ +#define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_EDMA2(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_EDMA2_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_EDMA2_MASK) + +#define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_LPI2C3_MASK (0x10U) +#define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_LPI2C3_SHIFT (4U) +/*! LPI2C3 + * 0b0..Module does not enter debug halted mode with A55 + * 0b1..Module enters debug halted mode when A55 is debug halted + */ +#define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_LPI2C3(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_LPI2C3_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_LPI2C3_MASK) + +#define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_LPI2C4_MASK (0x20U) +#define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_LPI2C4_SHIFT (5U) +/*! LPI2C4 + * 0b0..Module does not enter debug halted mode with A55 + * 0b1..Module enters debug halted mode when A55 is debug halted + */ +#define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_LPI2C4(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_LPI2C4_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_LPI2C4_MASK) + +#define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_LPI2C5_MASK (0x40U) +#define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_LPI2C5_SHIFT (6U) +/*! LPI2C5 + * 0b0..Module does not enter debug halted mode with A55 + * 0b1..Module enters debug halted mode when A55 is debug halted + */ +#define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_LPI2C5(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_LPI2C5_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_LPI2C5_MASK) + +#define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_LPI2C6_MASK (0x80U) +#define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_LPI2C6_SHIFT (7U) +/*! LPI2C6 + * 0b0..Module does not enter debug halted mode with A55 + * 0b1..Module enters debug halted mode when A55 is debug halted + */ +#define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_LPI2C6(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_LPI2C6_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_LPI2C6_MASK) + +#define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_LPI2C7_MASK (0x100U) +#define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_LPI2C7_SHIFT (8U) +/*! LPI2C7 + * 0b0..Module does not enter debug halted mode with A55 + * 0b1..Module enters debug halted mode when A55 is debug halted + */ +#define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_LPI2C7(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_LPI2C7_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_LPI2C7_MASK) + +#define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_LPI2C8_MASK (0x200U) +#define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_LPI2C8_SHIFT (9U) +/*! LPI2C8 + * 0b0..Module does not enter debug halted mode with A55 + * 0b1..Module enters debug halted mode when A55 is debug halted + */ +#define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_LPI2C8(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_LPI2C8_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_LPI2C8_MASK) + +#define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_LPIT2_MASK (0x400U) +#define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_LPIT2_SHIFT (10U) +/*! LPIT2 + * 0b0..Module does not enter debug halted mode with A55 + * 0b1..Module enters debug halted mode when A55 is debug halted + */ +#define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_LPIT2(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_LPIT2_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_LPIT2_MASK) + +#define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_LPSPI3_MASK (0x800U) +#define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_LPSPI3_SHIFT (11U) +/*! LPSPI3 + * 0b0..Module does not enter debug halted mode with A55 + * 0b1..Module enters debug halted mode when A55 is debug halted + */ +#define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_LPSPI3(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_LPSPI3_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_LPSPI3_MASK) + +#define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_LPSPI4_MASK (0x1000U) +#define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_LPSPI4_SHIFT (12U) +/*! LPSPI4 + * 0b0..Module does not enter debug halted mode with A55 + * 0b1..Module enters debug halted mode when A55 is debug halted + */ +#define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_LPSPI4(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_LPSPI4_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_LPSPI4_MASK) + +#define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_LPSPI5_MASK (0x2000U) +#define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_LPSPI5_SHIFT (13U) +#define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_LPSPI5(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_LPSPI5_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_LPSPI5_MASK) + +#define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_LPSPI6_MASK (0x4000U) +#define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_LPSPI6_SHIFT (14U) +/*! LPSPI6 + * 0b0..Module does not enter debug halted mode with A55 + * 0b1..Module enters debug halted mode when A55 is debug halted + */ +#define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_LPSPI6(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_LPSPI6_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_LPSPI6_MASK) + +#define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_LPSPI7_MASK (0x8000U) +#define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_LPSPI7_SHIFT (15U) +/*! LPSPI7 + * 0b0..Module does not enter debug halted mode with A55 + * 0b1..Module enters debug halted mode when A55 is debug halted + */ +#define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_LPSPI7(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_LPSPI7_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_LPSPI7_MASK) + +#define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_LPSPI8_MASK (0x10000U) +#define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_LPSPI8_SHIFT (16U) +/*! LPSPI8 + * 0b0..Module does not enter debug halted mode with A55 + * 0b1..Module enters debug halted mode when A55 is debug halted + */ +#define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_LPSPI8(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_LPSPI8_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_LPSPI8_MASK) + +#define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_LPTMR2_MASK (0x20000U) +#define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_LPTMR2_SHIFT (17U) +/*! LPTMR2 + * 0b0..Module does not enter debug halted mode with A55 + * 0b1..Module enters debug halted mode when A55 is debug halted + */ +#define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_LPTMR2(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_LPTMR2_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_LPTMR2_MASK) + +#define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_TPM3_MASK (0x40000U) +#define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_TPM3_SHIFT (18U) +/*! TPM3 + * 0b0..Module does not enter debug halted mode with A55 + * 0b1..Module enters debug halted mode when A55 is debug halted + */ +#define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_TPM3(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_TPM3_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_TPM3_MASK) + +#define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_TPM4_MASK (0x80000U) +#define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_TPM4_SHIFT (19U) +/*! TPM4 + * 0b0..Module does not enter debug halted mode with A55 + * 0b1..Module enters debug halted mode when A55 is debug halted + */ +#define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_TPM4(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_TPM4_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_TPM4_MASK) + +#define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_TPM5_MASK (0x100000U) +#define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_TPM5_SHIFT (20U) +/*! TPM5 + * 0b0..Module does not enter debug halted mode with A55 + * 0b1..Module enters debug halted mode when A55 is debug halted + */ +#define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_TPM5(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_TPM5_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_TPM5_MASK) + +#define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_TPM6_MASK (0x200000U) +#define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_TPM6_SHIFT (21U) +/*! TPM6 + * 0b0..Module does not enter debug halted mode with A55 + * 0b1..Module enters debug halted mode when A55 is debug halted + */ +#define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_TPM6(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_TPM6_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_TPM6_MASK) + +#define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_WDOG3_MASK (0x400000U) +#define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_WDOG3_SHIFT (22U) +/*! WDOG3 + * 0b0..Module does not enter debug halted mode with A55 + * 0b1..Module enters debug halted mode when A55 is debug halted + */ +#define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_WDOG3(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_WDOG3_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_WDOG3_MASK) + +#define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_WDOG4_MASK (0x800000U) +#define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_WDOG4_SHIFT (23U) +/*! WDOG4 + * 0b0..Module does not enter debug halted mode with A55 + * 0b1..Module enters debug halted mode when A55 is debug halted + */ +#define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_WDOG4(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_WDOG4_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_WDOG4_MASK) + +#define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_WDOG5_MASK (0x1000000U) +#define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_WDOG5_SHIFT (24U) +/*! WDOG5 + * 0b0..Module does not enter debug halted mode with A55 + * 0b1..Module enters debug halted mode when A55 is debug halted + */ +#define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_WDOG5(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_WDOG5_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_WDOG5_MASK) + +#define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_I3C2_MASK (0x2000000U) +#define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_I3C2_SHIFT (25U) +/*! I3C2 + * 0b0..Module does not enter debug halted mode with A55 + * 0b1..Module enters debug halted mode when A55 is debug halted + */ +#define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_I3C2(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_I3C2_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_I3C2_MASK) + +#define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_SAI2_MASK (0x4000000U) +#define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_SAI2_SHIFT (26U) +/*! SAI2 + * 0b0..Module does not enter debug halted mode with A55 + * 0b1..Module enters debug halted mode when A55 is debug halted + */ +#define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_SAI2(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_SAI2_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_SAI2_MASK) + +#define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_SAI3_MASK (0x8000000U) +#define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_SAI3_SHIFT (27U) +/*! SAI3 + * 0b0..Module does not enter debug halted mode with A55 + * 0b1..Module enters debug halted mode when A55 is debug halted + */ +#define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_SAI3(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_SAI3_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_SAI3_MASK) + +#define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_ENET2_REGULAR_MASK (0x10000000U) +#define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_ENET2_REGULAR_SHIFT (28U) +/*! ENET2_REGULAR + * 0b0..Module does not enter debug halted mode with A55 + * 0b1..Module enters debug halted mode when A55 is debug halted + */ +#define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_ENET2_REGULAR(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_ENET2_REGULAR_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_ENET2_REGULAR_MASK) +/*! @} */ + +/*! @name AXI_ATTR_CFG - AXI CACHE OVERRITE BIT */ +/*! @{ */ + +#define BLK_CTRL_WAKEUPMIX_AXI_ATTR_CFG_ARCACHE_USDHC1_MASK (0x1U) +#define BLK_CTRL_WAKEUPMIX_AXI_ATTR_CFG_ARCACHE_USDHC1_SHIFT (0U) +/*! ARCACHE_USDHC1 - Overwrite arcache of USDHC1 */ +#define BLK_CTRL_WAKEUPMIX_AXI_ATTR_CFG_ARCACHE_USDHC1(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_AXI_ATTR_CFG_ARCACHE_USDHC1_SHIFT)) & BLK_CTRL_WAKEUPMIX_AXI_ATTR_CFG_ARCACHE_USDHC1_MASK) + +#define BLK_CTRL_WAKEUPMIX_AXI_ATTR_CFG_AWCACHE_USDHC1_MASK (0x2U) +#define BLK_CTRL_WAKEUPMIX_AXI_ATTR_CFG_AWCACHE_USDHC1_SHIFT (1U) +/*! AWCACHE_USDHC1 - Overwrite awcache of USDHC1 */ +#define BLK_CTRL_WAKEUPMIX_AXI_ATTR_CFG_AWCACHE_USDHC1(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_AXI_ATTR_CFG_AWCACHE_USDHC1_SHIFT)) & BLK_CTRL_WAKEUPMIX_AXI_ATTR_CFG_AWCACHE_USDHC1_MASK) + +#define BLK_CTRL_WAKEUPMIX_AXI_ATTR_CFG_ARCACHE_USDHC2_MASK (0x4U) +#define BLK_CTRL_WAKEUPMIX_AXI_ATTR_CFG_ARCACHE_USDHC2_SHIFT (2U) +/*! ARCACHE_USDHC2 - Overwrite arcache of USDHC2 */ +#define BLK_CTRL_WAKEUPMIX_AXI_ATTR_CFG_ARCACHE_USDHC2(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_AXI_ATTR_CFG_ARCACHE_USDHC2_SHIFT)) & BLK_CTRL_WAKEUPMIX_AXI_ATTR_CFG_ARCACHE_USDHC2_MASK) + +#define BLK_CTRL_WAKEUPMIX_AXI_ATTR_CFG_AWCACHE_USDHC2_MASK (0x8U) +#define BLK_CTRL_WAKEUPMIX_AXI_ATTR_CFG_AWCACHE_USDHC2_SHIFT (3U) +/*! AWCACHE_USDHC2 - Overwrite awcache of USDHC2 */ +#define BLK_CTRL_WAKEUPMIX_AXI_ATTR_CFG_AWCACHE_USDHC2(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_AXI_ATTR_CFG_AWCACHE_USDHC2_SHIFT)) & BLK_CTRL_WAKEUPMIX_AXI_ATTR_CFG_AWCACHE_USDHC2_MASK) + +#define BLK_CTRL_WAKEUPMIX_AXI_ATTR_CFG_ARCACHE_USDHC3_MASK (0x10U) +#define BLK_CTRL_WAKEUPMIX_AXI_ATTR_CFG_ARCACHE_USDHC3_SHIFT (4U) +/*! ARCACHE_USDHC3 - Overwrite arcache of USDHC3 */ +#define BLK_CTRL_WAKEUPMIX_AXI_ATTR_CFG_ARCACHE_USDHC3(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_AXI_ATTR_CFG_ARCACHE_USDHC3_SHIFT)) & BLK_CTRL_WAKEUPMIX_AXI_ATTR_CFG_ARCACHE_USDHC3_MASK) + +#define BLK_CTRL_WAKEUPMIX_AXI_ATTR_CFG_AWCACHE_USDHC3_MASK (0x20U) +#define BLK_CTRL_WAKEUPMIX_AXI_ATTR_CFG_AWCACHE_USDHC3_SHIFT (5U) +/*! AWCACHE_USDHC3 - Overwrite awcache of USDHC3 */ +#define BLK_CTRL_WAKEUPMIX_AXI_ATTR_CFG_AWCACHE_USDHC3(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_AXI_ATTR_CFG_AWCACHE_USDHC3_SHIFT)) & BLK_CTRL_WAKEUPMIX_AXI_ATTR_CFG_AWCACHE_USDHC3_MASK) +/*! @} */ + +/*! @name I3C2_SDA_IRQ - I3C SDA IRQ Control */ +/*! @{ */ + +#define BLK_CTRL_WAKEUPMIX_I3C2_SDA_IRQ_enable_MASK (0x1U) +#define BLK_CTRL_WAKEUPMIX_I3C2_SDA_IRQ_enable_SHIFT (0U) +/*! enable - IRQ enable bit + * 0b0..I3C2 SDA IRQ disable + * 0b1..I3C2 SDA IRQ enable + */ +#define BLK_CTRL_WAKEUPMIX_I3C2_SDA_IRQ_enable(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_I3C2_SDA_IRQ_enable_SHIFT)) & BLK_CTRL_WAKEUPMIX_I3C2_SDA_IRQ_enable_MASK) +/*! @} */ + +/*! @name SSI_MST_WKUP2AON - Low power control for SSI_MST_WKUP2AON */ +/*! @{ */ + +#define BLK_CTRL_WAKEUPMIX_SSI_MST_WKUP2AON_idle_MASK (0x1U) +#define BLK_CTRL_WAKEUPMIX_SSI_MST_WKUP2AON_idle_SHIFT (0U) +#define BLK_CTRL_WAKEUPMIX_SSI_MST_WKUP2AON_idle(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_SSI_MST_WKUP2AON_idle_SHIFT)) & BLK_CTRL_WAKEUPMIX_SSI_MST_WKUP2AON_idle_MASK) + +#define BLK_CTRL_WAKEUPMIX_SSI_MST_WKUP2AON_pause_MASK (0x4U) +#define BLK_CTRL_WAKEUPMIX_SSI_MST_WKUP2AON_pause_SHIFT (2U) +#define BLK_CTRL_WAKEUPMIX_SSI_MST_WKUP2AON_pause(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_SSI_MST_WKUP2AON_pause_SHIFT)) & BLK_CTRL_WAKEUPMIX_SSI_MST_WKUP2AON_pause_MASK) + +#define BLK_CTRL_WAKEUPMIX_SSI_MST_WKUP2AON_black_hole_mode_b_MASK (0x8U) +#define BLK_CTRL_WAKEUPMIX_SSI_MST_WKUP2AON_black_hole_mode_b_SHIFT (3U) +#define BLK_CTRL_WAKEUPMIX_SSI_MST_WKUP2AON_black_hole_mode_b(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_SSI_MST_WKUP2AON_black_hole_mode_b_SHIFT)) & BLK_CTRL_WAKEUPMIX_SSI_MST_WKUP2AON_black_hole_mode_b_MASK) + +#define BLK_CTRL_WAKEUPMIX_SSI_MST_WKUP2AON_power_control_MASK (0x10U) +#define BLK_CTRL_WAKEUPMIX_SSI_MST_WKUP2AON_power_control_SHIFT (4U) +#define BLK_CTRL_WAKEUPMIX_SSI_MST_WKUP2AON_power_control(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_SSI_MST_WKUP2AON_power_control_SHIFT)) & BLK_CTRL_WAKEUPMIX_SSI_MST_WKUP2AON_power_control_MASK) + +#define BLK_CTRL_WAKEUPMIX_SSI_MST_WKUP2AON_iso_control_MASK (0x20U) +#define BLK_CTRL_WAKEUPMIX_SSI_MST_WKUP2AON_iso_control_SHIFT (5U) +#define BLK_CTRL_WAKEUPMIX_SSI_MST_WKUP2AON_iso_control(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_SSI_MST_WKUP2AON_iso_control_SHIFT)) & BLK_CTRL_WAKEUPMIX_SSI_MST_WKUP2AON_iso_control_MASK) +/*! @} */ + +/*! @name SSI_MST_WKUP2NIC - Low power control for SSI_MST_WKUP2NIC */ +/*! @{ */ + +#define BLK_CTRL_WAKEUPMIX_SSI_MST_WKUP2NIC_idle_MASK (0x1U) +#define BLK_CTRL_WAKEUPMIX_SSI_MST_WKUP2NIC_idle_SHIFT (0U) +#define BLK_CTRL_WAKEUPMIX_SSI_MST_WKUP2NIC_idle(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_SSI_MST_WKUP2NIC_idle_SHIFT)) & BLK_CTRL_WAKEUPMIX_SSI_MST_WKUP2NIC_idle_MASK) + +#define BLK_CTRL_WAKEUPMIX_SSI_MST_WKUP2NIC_pause_MASK (0x4U) +#define BLK_CTRL_WAKEUPMIX_SSI_MST_WKUP2NIC_pause_SHIFT (2U) +#define BLK_CTRL_WAKEUPMIX_SSI_MST_WKUP2NIC_pause(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_SSI_MST_WKUP2NIC_pause_SHIFT)) & BLK_CTRL_WAKEUPMIX_SSI_MST_WKUP2NIC_pause_MASK) + +#define BLK_CTRL_WAKEUPMIX_SSI_MST_WKUP2NIC_black_hole_mode_b_MASK (0x8U) +#define BLK_CTRL_WAKEUPMIX_SSI_MST_WKUP2NIC_black_hole_mode_b_SHIFT (3U) +#define BLK_CTRL_WAKEUPMIX_SSI_MST_WKUP2NIC_black_hole_mode_b(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_SSI_MST_WKUP2NIC_black_hole_mode_b_SHIFT)) & BLK_CTRL_WAKEUPMIX_SSI_MST_WKUP2NIC_black_hole_mode_b_MASK) + +#define BLK_CTRL_WAKEUPMIX_SSI_MST_WKUP2NIC_power_control_MASK (0x10U) +#define BLK_CTRL_WAKEUPMIX_SSI_MST_WKUP2NIC_power_control_SHIFT (4U) +#define BLK_CTRL_WAKEUPMIX_SSI_MST_WKUP2NIC_power_control(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_SSI_MST_WKUP2NIC_power_control_SHIFT)) & BLK_CTRL_WAKEUPMIX_SSI_MST_WKUP2NIC_power_control_MASK) + +#define BLK_CTRL_WAKEUPMIX_SSI_MST_WKUP2NIC_iso_control_MASK (0x20U) +#define BLK_CTRL_WAKEUPMIX_SSI_MST_WKUP2NIC_iso_control_SHIFT (5U) +#define BLK_CTRL_WAKEUPMIX_SSI_MST_WKUP2NIC_iso_control(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_SSI_MST_WKUP2NIC_iso_control_SHIFT)) & BLK_CTRL_WAKEUPMIX_SSI_MST_WKUP2NIC_iso_control_MASK) +/*! @} */ + +/*! @name SSI_SLV_AON2WKUP - Low power control for SSI_SLV_AON2WKUP */ +/*! @{ */ + +#define BLK_CTRL_WAKEUPMIX_SSI_SLV_AON2WKUP_idle_MASK (0x1U) +#define BLK_CTRL_WAKEUPMIX_SSI_SLV_AON2WKUP_idle_SHIFT (0U) +#define BLK_CTRL_WAKEUPMIX_SSI_SLV_AON2WKUP_idle(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_SSI_SLV_AON2WKUP_idle_SHIFT)) & BLK_CTRL_WAKEUPMIX_SSI_SLV_AON2WKUP_idle_MASK) + +#define BLK_CTRL_WAKEUPMIX_SSI_SLV_AON2WKUP_power_control_MASK (0x10U) +#define BLK_CTRL_WAKEUPMIX_SSI_SLV_AON2WKUP_power_control_SHIFT (4U) +#define BLK_CTRL_WAKEUPMIX_SSI_SLV_AON2WKUP_power_control(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_SSI_SLV_AON2WKUP_power_control_SHIFT)) & BLK_CTRL_WAKEUPMIX_SSI_SLV_AON2WKUP_power_control_MASK) + +#define BLK_CTRL_WAKEUPMIX_SSI_SLV_AON2WKUP_iso_control_MASK (0x20U) +#define BLK_CTRL_WAKEUPMIX_SSI_SLV_AON2WKUP_iso_control_SHIFT (5U) +#define BLK_CTRL_WAKEUPMIX_SSI_SLV_AON2WKUP_iso_control(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_SSI_SLV_AON2WKUP_iso_control_SHIFT)) & BLK_CTRL_WAKEUPMIX_SSI_SLV_AON2WKUP_iso_control_MASK) +/*! @} */ + +/*! @name SSI_SLV_NIC2WKUP - Low power control for SSI_SLV_NIC2WKUP */ +/*! @{ */ + +#define BLK_CTRL_WAKEUPMIX_SSI_SLV_NIC2WKUP_idle_MASK (0x1U) +#define BLK_CTRL_WAKEUPMIX_SSI_SLV_NIC2WKUP_idle_SHIFT (0U) +#define BLK_CTRL_WAKEUPMIX_SSI_SLV_NIC2WKUP_idle(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_SSI_SLV_NIC2WKUP_idle_SHIFT)) & BLK_CTRL_WAKEUPMIX_SSI_SLV_NIC2WKUP_idle_MASK) + +#define BLK_CTRL_WAKEUPMIX_SSI_SLV_NIC2WKUP_power_control_MASK (0x10U) +#define BLK_CTRL_WAKEUPMIX_SSI_SLV_NIC2WKUP_power_control_SHIFT (4U) +#define BLK_CTRL_WAKEUPMIX_SSI_SLV_NIC2WKUP_power_control(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_SSI_SLV_NIC2WKUP_power_control_SHIFT)) & BLK_CTRL_WAKEUPMIX_SSI_SLV_NIC2WKUP_power_control_MASK) + +#define BLK_CTRL_WAKEUPMIX_SSI_SLV_NIC2WKUP_iso_control_MASK (0x20U) +#define BLK_CTRL_WAKEUPMIX_SSI_SLV_NIC2WKUP_iso_control_SHIFT (5U) +#define BLK_CTRL_WAKEUPMIX_SSI_SLV_NIC2WKUP_iso_control(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_SSI_SLV_NIC2WKUP_iso_control_SHIFT)) & BLK_CTRL_WAKEUPMIX_SSI_SLV_NIC2WKUP_iso_control_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group BLK_CTRL_WAKEUPMIX_Register_Masks */ + + +/* BLK_CTRL_WAKEUPMIX - Peripheral instance base addresses */ +/** Peripheral BLK_CTRL_WAKEUPMIX1 base address */ +#define BLK_CTRL_WAKEUPMIX1_BASE (0x42420000u) +/** Peripheral BLK_CTRL_WAKEUPMIX1 base pointer */ +#define BLK_CTRL_WAKEUPMIX1 ((BLK_CTRL_WAKEUPMIX_Type *)BLK_CTRL_WAKEUPMIX1_BASE) +/** Array initializer of BLK_CTRL_WAKEUPMIX peripheral base addresses */ +#define BLK_CTRL_WAKEUPMIX_BASE_ADDRS { BLK_CTRL_WAKEUPMIX1_BASE } +/** Array initializer of BLK_CTRL_WAKEUPMIX peripheral base pointers */ +#define BLK_CTRL_WAKEUPMIX_BASE_PTRS { BLK_CTRL_WAKEUPMIX1 } + +/*! + * @} + */ /* end of group BLK_CTRL_WAKEUPMIX_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- CAN Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CAN_Peripheral_Access_Layer CAN Peripheral Access Layer + * @{ + */ + +/** CAN - Register Layout Typedef */ +typedef struct { + __IO uint32_t MCR; /**< Module Configuration, offset: 0x0 */ + __IO uint32_t CTRL1; /**< Control 1, offset: 0x4 */ + __IO uint32_t TIMER; /**< Free-Running Timer, offset: 0x8 */ + uint8_t RESERVED_0[4]; + __IO uint32_t RXMGMASK; /**< RX Message Buffers Global Mask, offset: 0x10 */ + __IO uint32_t RX14MASK; /**< Receive 14 Mask, offset: 0x14 */ + __IO uint32_t RX15MASK; /**< Receive 15 Mask, offset: 0x18 */ + __IO uint32_t ECR; /**< Error Counter, offset: 0x1C */ + __IO uint32_t ESR1; /**< Error and Status 1, offset: 0x20 */ + __IO uint32_t IMASK2; /**< Interrupt Masks 2, offset: 0x24 */ + __IO uint32_t IMASK1; /**< Interrupt Masks 1, offset: 0x28 */ + __IO uint32_t IFLAG2; /**< Interrupt Flags 2, offset: 0x2C */ + __IO uint32_t IFLAG1; /**< Interrupt Flags 1, offset: 0x30 */ + __IO uint32_t CTRL2; /**< Control 2, offset: 0x34 */ + __I uint32_t ESR2; /**< Error and Status 2, offset: 0x38 */ + uint8_t RESERVED_1[8]; + __I uint32_t CRCR; /**< Cyclic Redundancy Check, offset: 0x44 */ + __IO uint32_t RXFGMASK; /**< Legacy RX FIFO Global Mask, offset: 0x48 */ + __I uint32_t RXFIR; /**< Legacy RX FIFO Information, offset: 0x4C */ + __IO uint32_t CBT; /**< CAN Bit Timing, offset: 0x50 */ + uint8_t RESERVED_2[24]; + __IO uint32_t IMASK3; /**< Interrupt Masks 3, offset: 0x6C */ + uint8_t RESERVED_3[4]; + __IO uint32_t IFLAG3; /**< Interrupt Flags 3, offset: 0x74 */ + __I uint32_t ET; /**< External Timer, offset: 0x78, available only on: CAN_FD1/CAN1 (missing on CAN_FD2/CAN2) */ + __IO uint32_t FLTCONF_IE; /**< Fault Confinement Interrupt Enable, offset: 0x7C, available only on: CAN_FD1/CAN1 (missing on CAN_FD2/CAN2) */ + uint8_t RESERVED_4[2048]; + __IO uint32_t RXIMR[96]; /**< Receive Individual Mask, array offset: 0x880, array step: 0x4 */ + uint8_t RESERVED_5[224]; + __IO uint32_t MECR; /**< Memory Error Control, offset: 0xAE0 */ + __IO uint32_t ERRIAR; /**< Error Injection Address, offset: 0xAE4 */ + __IO uint32_t ERRIDPR; /**< Error Injection Data Pattern, offset: 0xAE8 */ + __IO uint32_t ERRIPPR; /**< Error Injection Parity Pattern, offset: 0xAEC */ + __I uint32_t RERRAR; /**< Error Report Address, offset: 0xAF0 */ + __I uint32_t RERRDR; /**< Error Report Data, offset: 0xAF4 */ + __I uint32_t RERRSYNR; /**< Error Report Syndrome, offset: 0xAF8 */ + __IO uint32_t ERRSR; /**< Error Status, offset: 0xAFC */ + uint8_t RESERVED_6[240]; + __IO uint32_t EPRS; /**< Enhanced CAN Bit Timing Prescalers, offset: 0xBF0 */ + __IO uint32_t ENCBT; /**< Enhanced Nominal CAN Bit Timing, offset: 0xBF4 */ + __IO uint32_t EDCBT; /**< Enhanced Data Phase CAN Bit Timing, offset: 0xBF8 */ + __IO uint32_t ETDC; /**< Enhanced Transceiver Delay Compensation, offset: 0xBFC */ + __IO uint32_t FDCTRL; /**< CAN FD Control, offset: 0xC00 */ + __IO uint32_t FDCBT; /**< CAN FD Bit Timing, offset: 0xC04 */ + __I uint32_t FDCRC; /**< CAN FD CRC, offset: 0xC08 */ + __IO uint32_t ERFCR; /**< Enhanced RX FIFO Control, offset: 0xC0C */ + __IO uint32_t ERFIER; /**< Enhanced RX FIFO Interrupt Enable, offset: 0xC10 */ + __IO uint32_t ERFSR; /**< Enhanced RX FIFO Status, offset: 0xC14 */ + uint8_t RESERVED_7[24]; + __IO uint32_t HR_TIME_STAMP[96]; /**< High-Resolution Timestamp, array offset: 0xC30, array step: 0x4 */ + uint8_t RESERVED_8[8784]; + __IO uint32_t ERFFEL[128]; /**< Enhanced RX FIFO Filter Element, array offset: 0x3000, array step: 0x4 */ +} CAN_Type; + +/* ---------------------------------------------------------------------------- + -- CAN Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CAN_Register_Masks CAN Register Masks + * @{ + */ + +/*! @name MCR - Module Configuration */ +/*! @{ */ + +#define CAN_MCR_MAXMB_MASK (0x7FU) +#define CAN_MCR_MAXMB_SHIFT (0U) +/*! MAXMB - Number of the Last Message Buffer */ +#define CAN_MCR_MAXMB(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_MAXMB_SHIFT)) & CAN_MCR_MAXMB_MASK) + +#define CAN_MCR_TPOE_MASK (0x80U) +#define CAN_MCR_TPOE_SHIFT (7U) +/*! TPOE - TX Pin Override Enable + * 0b0..TX pin forcing is disabled + * 0b1..TX pin forcing is enabled + */ +#define CAN_MCR_TPOE(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_TPOE_SHIFT)) & CAN_MCR_TPOE_MASK) + +#define CAN_MCR_IDAM_MASK (0x300U) +#define CAN_MCR_IDAM_SHIFT (8U) +/*! IDAM - ID Acceptance Mode + * 0b00..Format A: One full ID (standard and extended) per ID filter table element. + * 0b01..Format B: Two full standard IDs or two partial 14-bit (standard and extended) IDs per ID filter table element. + * 0b10..Format C: Four partial 8-bit standard IDs per ID filter table element. + * 0b11..Format D: All frames rejected. + */ +#define CAN_MCR_IDAM(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_IDAM_SHIFT)) & CAN_MCR_IDAM_MASK) + +#define CAN_MCR_TPOV_MASK (0x400U) +#define CAN_MCR_TPOV_SHIFT (10U) +/*! TPOV - TX Pin Override Value + * 0b0..TX pin is forced to be dominant + * 0b1..TX pin is forced to be recessive + */ +#define CAN_MCR_TPOV(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_TPOV_SHIFT)) & CAN_MCR_TPOV_MASK) + +#define CAN_MCR_FDEN_MASK (0x800U) +#define CAN_MCR_FDEN_SHIFT (11U) +/*! FDEN - CAN FD Operation Enable + * 0b0..Disable + * 0b1..Enable + */ +#define CAN_MCR_FDEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FDEN_SHIFT)) & CAN_MCR_FDEN_MASK) + +#define CAN_MCR_AEN_MASK (0x1000U) +#define CAN_MCR_AEN_SHIFT (12U) +/*! AEN - Abort Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define CAN_MCR_AEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_AEN_SHIFT)) & CAN_MCR_AEN_MASK) + +#define CAN_MCR_LPRIOEN_MASK (0x2000U) +#define CAN_MCR_LPRIOEN_SHIFT (13U) +/*! LPRIOEN - Local Priority Enable + * 0b0..Disable + * 0b1..Enable + */ +#define CAN_MCR_LPRIOEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_LPRIOEN_SHIFT)) & CAN_MCR_LPRIOEN_MASK) + +#define CAN_MCR_DMA_MASK (0x8000U) +#define CAN_MCR_DMA_SHIFT (15U) +/*! DMA - DMA Enable + * 0b0..Disable + * 0b1..Enable + */ +#define CAN_MCR_DMA(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_DMA_SHIFT)) & CAN_MCR_DMA_MASK) + +#define CAN_MCR_IRMQ_MASK (0x10000U) +#define CAN_MCR_IRMQ_SHIFT (16U) +/*! IRMQ - Individual RX Masking and Queue Enable + * 0b0..Disable + * 0b1..Enable + */ +#define CAN_MCR_IRMQ(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_IRMQ_SHIFT)) & CAN_MCR_IRMQ_MASK) + +#define CAN_MCR_SRXDIS_MASK (0x20000U) +#define CAN_MCR_SRXDIS_SHIFT (17U) +/*! SRXDIS - Self-Reception Disable + * 0b0..Enable + * 0b1..Disable + */ +#define CAN_MCR_SRXDIS(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SRXDIS_SHIFT)) & CAN_MCR_SRXDIS_MASK) + +#define CAN_MCR_DOZE_MASK (0x40000U) +#define CAN_MCR_DOZE_SHIFT (18U) +/*! DOZE - Doze Mode Enable + * 0b0..Disable + * 0b1..Enable + */ +#define CAN_MCR_DOZE(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_DOZE_SHIFT)) & CAN_MCR_DOZE_MASK) + +#define CAN_MCR_WAKSRC_MASK (0x80000U) +#define CAN_MCR_WAKSRC_SHIFT (19U) +/*! WAKSRC - Wake-Up Source + * 0b0..No filter applied + * 0b1..Filter applied + */ +#define CAN_MCR_WAKSRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WAKSRC_SHIFT)) & CAN_MCR_WAKSRC_MASK) + +#define CAN_MCR_LPMACK_MASK (0x100000U) +#define CAN_MCR_LPMACK_SHIFT (20U) +/*! LPMACK - Low-Power Mode Acknowledge + * 0b0..Not in a low-power mode + * 0b1..In a low-power mode + */ +#define CAN_MCR_LPMACK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_LPMACK_SHIFT)) & CAN_MCR_LPMACK_MASK) + +#define CAN_MCR_WRNEN_MASK (0x200000U) +#define CAN_MCR_WRNEN_SHIFT (21U) +/*! WRNEN - Warning Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define CAN_MCR_WRNEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WRNEN_SHIFT)) & CAN_MCR_WRNEN_MASK) + +#define CAN_MCR_SLFWAK_MASK (0x400000U) +#define CAN_MCR_SLFWAK_SHIFT (22U) +/*! SLFWAK - Self Wake-up + * 0b0..Disable + * 0b1..Enable + */ +#define CAN_MCR_SLFWAK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SLFWAK_SHIFT)) & CAN_MCR_SLFWAK_MASK) + +#define CAN_MCR_SUPV_MASK (0x800000U) +#define CAN_MCR_SUPV_SHIFT (23U) +/*! SUPV - Supervisor Mode + * 0b0..User mode + * 0b1..Supervisor mode + */ +#define CAN_MCR_SUPV(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SUPV_SHIFT)) & CAN_MCR_SUPV_MASK) + +#define CAN_MCR_FRZACK_MASK (0x1000000U) +#define CAN_MCR_FRZACK_SHIFT (24U) +/*! FRZACK - Freeze Mode Acknowledge + * 0b0..Not in Freeze mode, prescaler running. + * 0b1..In Freeze mode, prescaler stopped. + */ +#define CAN_MCR_FRZACK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FRZACK_SHIFT)) & CAN_MCR_FRZACK_MASK) + +#define CAN_MCR_SOFTRST_MASK (0x2000000U) +#define CAN_MCR_SOFTRST_SHIFT (25U) +/*! SOFTRST - Soft Reset + * 0b0..No reset + * 0b1..Soft reset affects reset registers + */ +#define CAN_MCR_SOFTRST(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SOFTRST_SHIFT)) & CAN_MCR_SOFTRST_MASK) + +#define CAN_MCR_WAKMSK_MASK (0x4000000U) +#define CAN_MCR_WAKMSK_SHIFT (26U) +/*! WAKMSK - Wake-up Interrupt Mask + * 0b0..Disabled + * 0b1..Enabled + */ +#define CAN_MCR_WAKMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WAKMSK_SHIFT)) & CAN_MCR_WAKMSK_MASK) + +#define CAN_MCR_NOTRDY_MASK (0x8000000U) +#define CAN_MCR_NOTRDY_SHIFT (27U) +/*! NOTRDY - FlexCAN Not Ready + * 0b0..FlexCAN is in Normal mode, Listen-Only mode, or Loopback mode. + * 0b1..FlexCAN is in Disable mode, Doze mode, Stop mode, or Freeze mode. + */ +#define CAN_MCR_NOTRDY(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_NOTRDY_SHIFT)) & CAN_MCR_NOTRDY_MASK) + +#define CAN_MCR_HALT_MASK (0x10000000U) +#define CAN_MCR_HALT_SHIFT (28U) +/*! HALT - Halt FlexCAN + * 0b0..No request + * 0b1..Enter Freeze mode, if MCR[FRZ] = 1. + */ +#define CAN_MCR_HALT(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_HALT_SHIFT)) & CAN_MCR_HALT_MASK) + +#define CAN_MCR_RFEN_MASK (0x20000000U) +#define CAN_MCR_RFEN_SHIFT (29U) +/*! RFEN - Legacy RX FIFO Enable + * 0b0..Disable + * 0b1..Enable + */ +#define CAN_MCR_RFEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_RFEN_SHIFT)) & CAN_MCR_RFEN_MASK) + +#define CAN_MCR_FRZ_MASK (0x40000000U) +#define CAN_MCR_FRZ_SHIFT (30U) +/*! FRZ - Freeze Enable + * 0b0..Disable + * 0b1..Enable + */ +#define CAN_MCR_FRZ(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FRZ_SHIFT)) & CAN_MCR_FRZ_MASK) + +#define CAN_MCR_MDIS_MASK (0x80000000U) +#define CAN_MCR_MDIS_SHIFT (31U) +/*! MDIS - Module Disable + * 0b0..Enable + * 0b1..Disable + */ +#define CAN_MCR_MDIS(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_MDIS_SHIFT)) & CAN_MCR_MDIS_MASK) +/*! @} */ + +/*! @name CTRL1 - Control 1 */ +/*! @{ */ + +#define CAN_CTRL1_PROPSEG_MASK (0x7U) +#define CAN_CTRL1_PROPSEG_SHIFT (0U) +/*! PROPSEG - Propagation Segment */ +#define CAN_CTRL1_PROPSEG(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PROPSEG_SHIFT)) & CAN_CTRL1_PROPSEG_MASK) + +#define CAN_CTRL1_LOM_MASK (0x8U) +#define CAN_CTRL1_LOM_SHIFT (3U) +/*! LOM - Listen-Only Mode + * 0b0..Listen-Only mode is deactivated. + * 0b1..FlexCAN module operates in Listen-Only mode. + */ +#define CAN_CTRL1_LOM(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LOM_SHIFT)) & CAN_CTRL1_LOM_MASK) + +#define CAN_CTRL1_LBUF_MASK (0x10U) +#define CAN_CTRL1_LBUF_SHIFT (4U) +/*! LBUF - Lowest Buffer Transmitted First + * 0b0..Buffer with highest priority is transmitted first. + * 0b1..Lowest number buffer is transmitted first. + */ +#define CAN_CTRL1_LBUF(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LBUF_SHIFT)) & CAN_CTRL1_LBUF_MASK) + +#define CAN_CTRL1_TSYN_MASK (0x20U) +#define CAN_CTRL1_TSYN_SHIFT (5U) +/*! TSYN - Timer Sync + * 0b0..Disable + * 0b1..Enable + */ +#define CAN_CTRL1_TSYN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_TSYN_SHIFT)) & CAN_CTRL1_TSYN_MASK) + +#define CAN_CTRL1_BOFFREC_MASK (0x40U) +#define CAN_CTRL1_BOFFREC_SHIFT (6U) +/*! BOFFREC - Bus Off Recovery + * 0b0..Enabled + * 0b1..Disabled + */ +#define CAN_CTRL1_BOFFREC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_BOFFREC_SHIFT)) & CAN_CTRL1_BOFFREC_MASK) + +#define CAN_CTRL1_SMP_MASK (0x80U) +#define CAN_CTRL1_SMP_SHIFT (7U) +/*! SMP - CAN Bit Sampling + * 0b0..One sample is used to determine the bit value. + * 0b1..Three samples are used to determine the value of the received bit: the regular one (sample point) and two + * preceding samples. A majority rule is used. + */ +#define CAN_CTRL1_SMP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_SMP_SHIFT)) & CAN_CTRL1_SMP_MASK) + +#define CAN_CTRL1_ROM_MASK (0x100U) +#define CAN_CTRL1_ROM_SHIFT (8U) +/*! ROM - Restricted Operation Mode + * 0b0..Restricted operation is disabled + * 0b1..Restricted operation is enabled + */ +#define CAN_CTRL1_ROM(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_ROM_SHIFT)) & CAN_CTRL1_ROM_MASK) + +#define CAN_CTRL1_RWRNMSK_MASK (0x400U) +#define CAN_CTRL1_RWRNMSK_SHIFT (10U) +/*! RWRNMSK - RX Warning Interrupt Mask + * 0b0..Disabled + * 0b1..Enabled + */ +#define CAN_CTRL1_RWRNMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_RWRNMSK_SHIFT)) & CAN_CTRL1_RWRNMSK_MASK) + +#define CAN_CTRL1_TWRNMSK_MASK (0x800U) +#define CAN_CTRL1_TWRNMSK_SHIFT (11U) +/*! TWRNMSK - TX Warning Interrupt Mask + * 0b0..Disabled + * 0b1..Enabled + */ +#define CAN_CTRL1_TWRNMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_TWRNMSK_SHIFT)) & CAN_CTRL1_TWRNMSK_MASK) + +#define CAN_CTRL1_LPB_MASK (0x1000U) +#define CAN_CTRL1_LPB_SHIFT (12U) +/*! LPB - Loopback Mode + * 0b0..Disabled + * 0b1..Enabled + */ +#define CAN_CTRL1_LPB(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LPB_SHIFT)) & CAN_CTRL1_LPB_MASK) + +#define CAN_CTRL1_CLKSRC_MASK (0x2000U) +#define CAN_CTRL1_CLKSRC_SHIFT (13U) +/*! CLKSRC - CAN Engine Clock Source + * 0b0..Peripheral clock + * 0b1..Bus clock + */ +#define CAN_CTRL1_CLKSRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_CLKSRC_SHIFT)) & CAN_CTRL1_CLKSRC_MASK) + +#define CAN_CTRL1_ERRMSK_MASK (0x4000U) +#define CAN_CTRL1_ERRMSK_SHIFT (14U) +/*! ERRMSK - Error Interrupt Mask + * 0b0..Interrupt disabled + * 0b1..Interrupt enabled + */ +#define CAN_CTRL1_ERRMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_ERRMSK_SHIFT)) & CAN_CTRL1_ERRMSK_MASK) + +#define CAN_CTRL1_BOFFMSK_MASK (0x8000U) +#define CAN_CTRL1_BOFFMSK_SHIFT (15U) +/*! BOFFMSK - Bus Off Interrupt Mask + * 0b0..Interrupt disabled + * 0b1..Interrupt enabled + */ +#define CAN_CTRL1_BOFFMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_BOFFMSK_SHIFT)) & CAN_CTRL1_BOFFMSK_MASK) + +#define CAN_CTRL1_PSEG2_MASK (0x70000U) +#define CAN_CTRL1_PSEG2_SHIFT (16U) +/*! PSEG2 - Phase Segment 2 */ +#define CAN_CTRL1_PSEG2(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PSEG2_SHIFT)) & CAN_CTRL1_PSEG2_MASK) + +#define CAN_CTRL1_PSEG1_MASK (0x380000U) +#define CAN_CTRL1_PSEG1_SHIFT (19U) +/*! PSEG1 - Phase Segment 1 */ +#define CAN_CTRL1_PSEG1(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PSEG1_SHIFT)) & CAN_CTRL1_PSEG1_MASK) + +#define CAN_CTRL1_RJW_MASK (0xC00000U) +#define CAN_CTRL1_RJW_SHIFT (22U) +/*! RJW - Resync Jump Width */ +#define CAN_CTRL1_RJW(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_RJW_SHIFT)) & CAN_CTRL1_RJW_MASK) + +#define CAN_CTRL1_PRESDIV_MASK (0xFF000000U) +#define CAN_CTRL1_PRESDIV_SHIFT (24U) +/*! PRESDIV - Prescaler Division Factor */ +#define CAN_CTRL1_PRESDIV(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PRESDIV_SHIFT)) & CAN_CTRL1_PRESDIV_MASK) +/*! @} */ + +/*! @name TIMER - Free-Running Timer */ +/*! @{ */ + +#define CAN_TIMER_TIMER_MASK (0xFFFFU) +#define CAN_TIMER_TIMER_SHIFT (0U) +/*! TIMER - Timer Value */ +#define CAN_TIMER_TIMER(x) (((uint32_t)(((uint32_t)(x)) << CAN_TIMER_TIMER_SHIFT)) & CAN_TIMER_TIMER_MASK) +/*! @} */ + +/*! @name RXMGMASK - RX Message Buffers Global Mask */ +/*! @{ */ + +#define CAN_RXMGMASK_MG_MASK (0xFFFFFFFFU) +#define CAN_RXMGMASK_MG_SHIFT (0U) +/*! MG - Global Mask for RX Message Buffers */ +#define CAN_RXMGMASK_MG(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXMGMASK_MG_SHIFT)) & CAN_RXMGMASK_MG_MASK) +/*! @} */ + +/*! @name RX14MASK - Receive 14 Mask */ +/*! @{ */ + +#define CAN_RX14MASK_RX14M_MASK (0xFFFFFFFFU) +#define CAN_RX14MASK_RX14M_SHIFT (0U) +/*! RX14M - RX Buffer 14 Mask Bits */ +#define CAN_RX14MASK_RX14M(x) (((uint32_t)(((uint32_t)(x)) << CAN_RX14MASK_RX14M_SHIFT)) & CAN_RX14MASK_RX14M_MASK) +/*! @} */ + +/*! @name RX15MASK - Receive 15 Mask */ +/*! @{ */ + +#define CAN_RX15MASK_RX15M_MASK (0xFFFFFFFFU) +#define CAN_RX15MASK_RX15M_SHIFT (0U) +/*! RX15M - RX Buffer 15 Mask Bits */ +#define CAN_RX15MASK_RX15M(x) (((uint32_t)(((uint32_t)(x)) << CAN_RX15MASK_RX15M_SHIFT)) & CAN_RX15MASK_RX15M_MASK) +/*! @} */ + +/*! @name ECR - Error Counter */ +/*! @{ */ + +#define CAN_ECR_TXERRCNT_MASK (0xFFU) +#define CAN_ECR_TXERRCNT_SHIFT (0U) +/*! TXERRCNT - Transmit Error Counter */ +#define CAN_ECR_TXERRCNT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_TXERRCNT_SHIFT)) & CAN_ECR_TXERRCNT_MASK) + +#define CAN_ECR_RXERRCNT_MASK (0xFF00U) +#define CAN_ECR_RXERRCNT_SHIFT (8U) +/*! RXERRCNT - Receive Error Counter */ +#define CAN_ECR_RXERRCNT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_RXERRCNT_SHIFT)) & CAN_ECR_RXERRCNT_MASK) + +#define CAN_ECR_TXERRCNT_FAST_MASK (0xFF0000U) +#define CAN_ECR_TXERRCNT_FAST_SHIFT (16U) +/*! TXERRCNT_FAST - Transmit Error Counter for Fast Bits */ +#define CAN_ECR_TXERRCNT_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_TXERRCNT_FAST_SHIFT)) & CAN_ECR_TXERRCNT_FAST_MASK) + +#define CAN_ECR_RXERRCNT_FAST_MASK (0xFF000000U) +#define CAN_ECR_RXERRCNT_FAST_SHIFT (24U) +/*! RXERRCNT_FAST - Receive Error Counter for Fast Bits */ +#define CAN_ECR_RXERRCNT_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_RXERRCNT_FAST_SHIFT)) & CAN_ECR_RXERRCNT_FAST_MASK) +/*! @} */ + +/*! @name ESR1 - Error and Status 1 */ +/*! @{ */ + +#define CAN_ESR1_WAKINT_MASK (0x1U) +#define CAN_ESR1_WAKINT_SHIFT (0U) +/*! WAKINT - Wake-up Interrupt Flag + * 0b0..No such occurrence. + * 0b1..Indicates that a recessive-to-dominant transition was received on the CAN bus. + */ +#define CAN_ESR1_WAKINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_WAKINT_SHIFT)) & CAN_ESR1_WAKINT_MASK) + +#define CAN_ESR1_ERRINT_MASK (0x2U) +#define CAN_ESR1_ERRINT_SHIFT (1U) +/*! ERRINT - Error Interrupt Flag + * 0b0..No such occurrence. + * 0b1..Indicates setting of any error flag in the Error and Status register. + */ +#define CAN_ESR1_ERRINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ERRINT_SHIFT)) & CAN_ESR1_ERRINT_MASK) + +#define CAN_ESR1_BOFFINT_MASK (0x4U) +#define CAN_ESR1_BOFFINT_SHIFT (2U) +/*! BOFFINT - Bus Off Interrupt Flag + * 0b0..No such occurrence. + * 0b1..FlexCAN module entered Bus Off state. + */ +#define CAN_ESR1_BOFFINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BOFFINT_SHIFT)) & CAN_ESR1_BOFFINT_MASK) + +#define CAN_ESR1_RX_MASK (0x8U) +#define CAN_ESR1_RX_SHIFT (3U) +/*! RX - FlexCAN in Reception Flag + * 0b0..Not receiving + * 0b1..Receiving + */ +#define CAN_ESR1_RX(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RX_SHIFT)) & CAN_ESR1_RX_MASK) + +#define CAN_ESR1_FLTCONF_MASK (0x30U) +#define CAN_ESR1_FLTCONF_SHIFT (4U) +/*! FLTCONF - Fault Confinement State + * 0b00..Error Active + * 0b01..Error Passive + * 0b1x..Bus Off + */ +#define CAN_ESR1_FLTCONF(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_FLTCONF_SHIFT)) & CAN_ESR1_FLTCONF_MASK) + +#define CAN_ESR1_TX_MASK (0x40U) +#define CAN_ESR1_TX_SHIFT (6U) +/*! TX - FlexCAN In Transmission + * 0b0..Not transmitting + * 0b1..Transmitting + */ +#define CAN_ESR1_TX(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TX_SHIFT)) & CAN_ESR1_TX_MASK) + +#define CAN_ESR1_IDLE_MASK (0x80U) +#define CAN_ESR1_IDLE_SHIFT (7U) +/*! IDLE - Idle + * 0b0..Not IDLE + * 0b1..IDLE + */ +#define CAN_ESR1_IDLE(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_IDLE_SHIFT)) & CAN_ESR1_IDLE_MASK) + +#define CAN_ESR1_RXWRN_MASK (0x100U) +#define CAN_ESR1_RXWRN_SHIFT (8U) +/*! RXWRN - RX Error Warning Flag + * 0b0..No such occurrence. + * 0b1..RXERRCNT is greater than or equal to 96. + */ +#define CAN_ESR1_RXWRN(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RXWRN_SHIFT)) & CAN_ESR1_RXWRN_MASK) + +#define CAN_ESR1_TXWRN_MASK (0x200U) +#define CAN_ESR1_TXWRN_SHIFT (9U) +/*! TXWRN - TX Error Warning Flag + * 0b0..No such occurrence. + * 0b1..TXERRCNT is 96 or greater. + */ +#define CAN_ESR1_TXWRN(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TXWRN_SHIFT)) & CAN_ESR1_TXWRN_MASK) + +#define CAN_ESR1_STFERR_MASK (0x400U) +#define CAN_ESR1_STFERR_SHIFT (10U) +/*! STFERR - Stuffing Error Flag + * 0b0..No error + * 0b1..Error occurred since last read of this register. + */ +#define CAN_ESR1_STFERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_STFERR_SHIFT)) & CAN_ESR1_STFERR_MASK) + +#define CAN_ESR1_FRMERR_MASK (0x800U) +#define CAN_ESR1_FRMERR_SHIFT (11U) +/*! FRMERR - Form Error Flag + * 0b0..No error + * 0b1..Error occurred since last read of this register. + */ +#define CAN_ESR1_FRMERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_FRMERR_SHIFT)) & CAN_ESR1_FRMERR_MASK) + +#define CAN_ESR1_CRCERR_MASK (0x1000U) +#define CAN_ESR1_CRCERR_SHIFT (12U) +/*! CRCERR - Cyclic Redundancy Check Error Flag + * 0b0..No error + * 0b1..Error occurred since last read of this register. + */ +#define CAN_ESR1_CRCERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_CRCERR_SHIFT)) & CAN_ESR1_CRCERR_MASK) + +#define CAN_ESR1_ACKERR_MASK (0x2000U) +#define CAN_ESR1_ACKERR_SHIFT (13U) +/*! ACKERR - Acknowledge Error Flag + * 0b0..No error + * 0b1..Error occurred since last read of this register. + */ +#define CAN_ESR1_ACKERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ACKERR_SHIFT)) & CAN_ESR1_ACKERR_MASK) + +#define CAN_ESR1_BIT0ERR_MASK (0x4000U) +#define CAN_ESR1_BIT0ERR_SHIFT (14U) +/*! BIT0ERR - Bit0 Error Flag + * 0b0..No such occurrence. + * 0b1..At least one bit sent as dominant is received as recessive. + */ +#define CAN_ESR1_BIT0ERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT0ERR_SHIFT)) & CAN_ESR1_BIT0ERR_MASK) + +#define CAN_ESR1_BIT1ERR_MASK (0x8000U) +#define CAN_ESR1_BIT1ERR_SHIFT (15U) +/*! BIT1ERR - Bit1 Error Flag + * 0b0..No such occurrence. + * 0b1..At least one bit sent as recessive is received as dominant. + */ +#define CAN_ESR1_BIT1ERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT1ERR_SHIFT)) & CAN_ESR1_BIT1ERR_MASK) + +#define CAN_ESR1_RWRNINT_MASK (0x10000U) +#define CAN_ESR1_RWRNINT_SHIFT (16U) +/*! RWRNINT - RX Warning Interrupt Flag + * 0b0..No such occurrence + * 0b1..RX error counter changed from less than 96 to greater than or equal to 96. + */ +#define CAN_ESR1_RWRNINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RWRNINT_SHIFT)) & CAN_ESR1_RWRNINT_MASK) + +#define CAN_ESR1_TWRNINT_MASK (0x20000U) +#define CAN_ESR1_TWRNINT_SHIFT (17U) +/*! TWRNINT - TX Warning Interrupt Flag + * 0b0..No such occurrence + * 0b1..TX error counter changed from less than 96 to greater than or equal to 96. + */ +#define CAN_ESR1_TWRNINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TWRNINT_SHIFT)) & CAN_ESR1_TWRNINT_MASK) + +#define CAN_ESR1_SYNCH_MASK (0x40000U) +#define CAN_ESR1_SYNCH_SHIFT (18U) +/*! SYNCH - CAN Synchronization Status Flag + * 0b0..Not synchronized + * 0b1..Synchronized + */ +#define CAN_ESR1_SYNCH(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_SYNCH_SHIFT)) & CAN_ESR1_SYNCH_MASK) + +#define CAN_ESR1_BOFFDONEINT_MASK (0x80000U) +#define CAN_ESR1_BOFFDONEINT_SHIFT (19U) +/*! BOFFDONEINT - Bus Off Done Interrupt Flag + * 0b0..No such occurrence + * 0b1..FlexCAN module has completed Bus Off process. + */ +#define CAN_ESR1_BOFFDONEINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BOFFDONEINT_SHIFT)) & CAN_ESR1_BOFFDONEINT_MASK) + +#define CAN_ESR1_ERRINT_FAST_MASK (0x100000U) +#define CAN_ESR1_ERRINT_FAST_SHIFT (20U) +/*! ERRINT_FAST - Fast Error Interrupt Flag + * 0b0..No such occurrence. + * 0b1..Error flag set in the data phase of CAN FD frames that have BRS = 1. + */ +#define CAN_ESR1_ERRINT_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ERRINT_FAST_SHIFT)) & CAN_ESR1_ERRINT_FAST_MASK) + +#define CAN_ESR1_ERROVR_MASK (0x200000U) +#define CAN_ESR1_ERROVR_SHIFT (21U) +/*! ERROVR - Error Overrun Flag + * 0b0..No overrun + * 0b1..Overrun + */ +#define CAN_ESR1_ERROVR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ERROVR_SHIFT)) & CAN_ESR1_ERROVR_MASK) + +#define CAN_ESR1_ATP_MASK (0x400000U) +#define CAN_ESR1_ATP_SHIFT (22U) +/*! ATP - Active to Passive State + * 0b0..Does not transition + * 0b1..Transitions + */ +#define CAN_ESR1_ATP(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ATP_SHIFT)) & CAN_ESR1_ATP_MASK) + +#define CAN_ESR1_PTA_MASK (0x800000U) +#define CAN_ESR1_PTA_SHIFT (23U) +/*! PTA - Passive to Active State + * 0b0..Does not transition + * 0b1..Transitions + */ +#define CAN_ESR1_PTA(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_PTA_SHIFT)) & CAN_ESR1_PTA_MASK) + +#define CAN_ESR1_STFERR_FAST_MASK (0x4000000U) +#define CAN_ESR1_STFERR_FAST_SHIFT (26U) +/*! STFERR_FAST - Fast Stuffing Error Flag + * 0b0..No such occurrence. + * 0b1..A stuffing error occurred since last read of this register. + */ +#define CAN_ESR1_STFERR_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_STFERR_FAST_SHIFT)) & CAN_ESR1_STFERR_FAST_MASK) + +#define CAN_ESR1_FRMERR_FAST_MASK (0x8000000U) +#define CAN_ESR1_FRMERR_FAST_SHIFT (27U) +/*! FRMERR_FAST - Fast Form Error Flag + * 0b0..No such occurrence. + * 0b1..A form error occurred since last read of this register. + */ +#define CAN_ESR1_FRMERR_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_FRMERR_FAST_SHIFT)) & CAN_ESR1_FRMERR_FAST_MASK) + +#define CAN_ESR1_CRCERR_FAST_MASK (0x10000000U) +#define CAN_ESR1_CRCERR_FAST_SHIFT (28U) +/*! CRCERR_FAST - Fast Cyclic Redundancy Check Error Flag + * 0b0..No such occurrence. + * 0b1..A CRC error occurred since last read of this register. + */ +#define CAN_ESR1_CRCERR_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_CRCERR_FAST_SHIFT)) & CAN_ESR1_CRCERR_FAST_MASK) + +#define CAN_ESR1_BIT0ERR_FAST_MASK (0x40000000U) +#define CAN_ESR1_BIT0ERR_FAST_SHIFT (30U) +/*! BIT0ERR_FAST - Fast Bit0 Error Flag + * 0b0..No such occurrence. + * 0b1..At least one bit transmitted as dominant is received as recessive. + */ +#define CAN_ESR1_BIT0ERR_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT0ERR_FAST_SHIFT)) & CAN_ESR1_BIT0ERR_FAST_MASK) + +#define CAN_ESR1_BIT1ERR_FAST_MASK (0x80000000U) +#define CAN_ESR1_BIT1ERR_FAST_SHIFT (31U) +/*! BIT1ERR_FAST - Fast Bit1 Error Flag + * 0b0..No such occurrence. + * 0b1..At least one bit transmitted as recessive is received as dominant. + */ +#define CAN_ESR1_BIT1ERR_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT1ERR_FAST_SHIFT)) & CAN_ESR1_BIT1ERR_FAST_MASK) +/*! @} */ + +/*! @name IMASK2 - Interrupt Masks 2 */ +/*! @{ */ + +#define CAN_IMASK2_BUF63TO32M_MASK (0xFFFFFFFFU) +#define CAN_IMASK2_BUF63TO32M_SHIFT (0U) +/*! BUF63TO32M - Buffer MBi Mask */ +#define CAN_IMASK2_BUF63TO32M(x) (((uint32_t)(((uint32_t)(x)) << CAN_IMASK2_BUF63TO32M_SHIFT)) & CAN_IMASK2_BUF63TO32M_MASK) +/*! @} */ + +/*! @name IMASK1 - Interrupt Masks 1 */ +/*! @{ */ + +#define CAN_IMASK1_BUF31TO0M_MASK (0xFFFFFFFFU) +#define CAN_IMASK1_BUF31TO0M_SHIFT (0U) +/*! BUF31TO0M - Buffer MBi Mask */ +#define CAN_IMASK1_BUF31TO0M(x) (((uint32_t)(((uint32_t)(x)) << CAN_IMASK1_BUF31TO0M_SHIFT)) & CAN_IMASK1_BUF31TO0M_MASK) +/*! @} */ + +/*! @name IFLAG2 - Interrupt Flags 2 */ +/*! @{ */ + +#define CAN_IFLAG2_BUF63TO32I_MASK (0xFFFFFFFFU) +#define CAN_IFLAG2_BUF63TO32I_SHIFT (0U) +/*! BUF63TO32I - Buffer MBi Interrupt */ +#define CAN_IFLAG2_BUF63TO32I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG2_BUF63TO32I_SHIFT)) & CAN_IFLAG2_BUF63TO32I_MASK) +/*! @} */ + +/*! @name IFLAG1 - Interrupt Flags 1 */ +/*! @{ */ + +#define CAN_IFLAG1_BUF0I_MASK (0x1U) +#define CAN_IFLAG1_BUF0I_SHIFT (0U) +/*! BUF0I - Buffer MB0 Interrupt or Clear Legacy FIFO bit + * 0b0..MB0 has no occurrence of successfully completed transmission or reception. + * 0b1..MB0 has successfully completed transmission or reception. + */ +#define CAN_IFLAG1_BUF0I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF0I_SHIFT)) & CAN_IFLAG1_BUF0I_MASK) + +#define CAN_IFLAG1_BUF4TO1I_MASK (0x1EU) +#define CAN_IFLAG1_BUF4TO1I_SHIFT (1U) +/*! BUF4TO1I - Buffer MBi Interrupt or Reserved */ +#define CAN_IFLAG1_BUF4TO1I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF4TO1I_SHIFT)) & CAN_IFLAG1_BUF4TO1I_MASK) + +#define CAN_IFLAG1_BUF5I_MASK (0x20U) +#define CAN_IFLAG1_BUF5I_SHIFT (5U) +/*! BUF5I - Buffer MB5 Interrupt or Frames available in Legacy RX FIFO + * 0b0..No occurrence of completed transmission or reception, or no frames available + * 0b1..MB5 completed transmission or reception, or frames available + */ +#define CAN_IFLAG1_BUF5I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF5I_SHIFT)) & CAN_IFLAG1_BUF5I_MASK) + +#define CAN_IFLAG1_BUF6I_MASK (0x40U) +#define CAN_IFLAG1_BUF6I_SHIFT (6U) +/*! BUF6I - Buffer MB6 Interrupt or Legacy RX FIFO Warning + * 0b0..No occurrence of MB6 completing transmission or reception, or FIFO not almost full. + * 0b1..MB6 completed transmission or reception, or FIFO almost full. + */ +#define CAN_IFLAG1_BUF6I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF6I_SHIFT)) & CAN_IFLAG1_BUF6I_MASK) + +#define CAN_IFLAG1_BUF7I_MASK (0x80U) +#define CAN_IFLAG1_BUF7I_SHIFT (7U) +/*! BUF7I - Buffer MB7 Interrupt or Legacy RX FIFO Overflow + * 0b0..No occurrence of MB7 completing transmission or reception, or no FIFO overflow. + * 0b1..MB7 completed transmission or reception, or FIFO overflow. + */ +#define CAN_IFLAG1_BUF7I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF7I_SHIFT)) & CAN_IFLAG1_BUF7I_MASK) + +#define CAN_IFLAG1_BUF31TO8I_MASK (0xFFFFFF00U) +#define CAN_IFLAG1_BUF31TO8I_SHIFT (8U) +/*! BUF31TO8I - Buffer MBi Interrupt */ +#define CAN_IFLAG1_BUF31TO8I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF31TO8I_SHIFT)) & CAN_IFLAG1_BUF31TO8I_MASK) +/*! @} */ + +/*! @name CTRL2 - Control 2 */ +/*! @{ */ + +#define CAN_CTRL2_RETRY_MASK (0x1CU) +#define CAN_CTRL2_RETRY_SHIFT (2U) +/*! RETRY - Number of Retransmission Requests + * 0b000..No retransmission + * 0b001..Count of re-transmission attempts + * 0b010..Count of re-transmission attempts + * 0b011..Count of re-transmission attempts + * 0b100..Count of re-transmission attempts + * 0b101..Count of re-transmission attempts + * 0b110..Count of re-transmission attempts + * 0b111..Unlimited number of retransmission + */ +#define CAN_CTRL2_RETRY(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_RETRY_SHIFT)) & CAN_CTRL2_RETRY_MASK) + +#define CAN_CTRL2_TSTAMPCAP_MASK (0xC0U) +#define CAN_CTRL2_TSTAMPCAP_SHIFT (6U) +/*! TSTAMPCAP - Timestamp Capture Point + * 0b00..Disabled + * 0b01..End of the CAN frame + * 0b10..Start of the CAN frame + * 0b11..Start of frame for classical CAN frames; res bit for CAN FD frames + */ +#define CAN_CTRL2_TSTAMPCAP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_TSTAMPCAP_SHIFT)) & CAN_CTRL2_TSTAMPCAP_MASK) + +#define CAN_CTRL2_MBTSBASE_MASK (0x300U) +#define CAN_CTRL2_MBTSBASE_SHIFT (8U) +/*! MBTSBASE - Message Buffer Timestamp Base + * 0b00..TIMER + * 0b01..Lower 16 bits of high-resolution timer + * 0b10..Upper 16 bits of high-resolution timer + * 0b11..Reserved + */ +#define CAN_CTRL2_MBTSBASE(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_MBTSBASE_SHIFT)) & CAN_CTRL2_MBTSBASE_MASK) + +#define CAN_CTRL2_FLT_RXN_MASK (0x400U) +#define CAN_CTRL2_FLT_RXN_SHIFT (10U) +/*! FLT_RXN - Fault reaction + * 0b0..Fault reaction is disabled + * 0b1..Fault reaction is enabled + */ +#define CAN_CTRL2_FLT_RXN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_FLT_RXN_SHIFT)) & CAN_CTRL2_FLT_RXN_MASK) + +#define CAN_CTRL2_EDFLTDIS_MASK (0x800U) +#define CAN_CTRL2_EDFLTDIS_SHIFT (11U) +/*! EDFLTDIS - Edge Filter Disable + * 0b0..Enabled + * 0b1..Disabled + */ +#define CAN_CTRL2_EDFLTDIS(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_EDFLTDIS_SHIFT)) & CAN_CTRL2_EDFLTDIS_MASK) + +#define CAN_CTRL2_ISOCANFDEN_MASK (0x1000U) +#define CAN_CTRL2_ISOCANFDEN_SHIFT (12U) +/*! ISOCANFDEN - ISO CAN FD Enable + * 0b0..Disable + * 0b1..Enable + */ +#define CAN_CTRL2_ISOCANFDEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_ISOCANFDEN_SHIFT)) & CAN_CTRL2_ISOCANFDEN_MASK) + +#define CAN_CTRL2_BTE_MASK (0x2000U) +#define CAN_CTRL2_BTE_SHIFT (13U) +/*! BTE - Bit Timing Expansion Enable + * 0b0..Disable + * 0b1..Enable + */ +#define CAN_CTRL2_BTE(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_BTE_SHIFT)) & CAN_CTRL2_BTE_MASK) + +#define CAN_CTRL2_PREXCEN_MASK (0x4000U) +#define CAN_CTRL2_PREXCEN_SHIFT (14U) +/*! PREXCEN - Protocol Exception Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define CAN_CTRL2_PREXCEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_PREXCEN_SHIFT)) & CAN_CTRL2_PREXCEN_MASK) + +#define CAN_CTRL2_TIMER_SRC_MASK (0x8000U) +#define CAN_CTRL2_TIMER_SRC_SHIFT (15U) +/*! TIMER_SRC - Timer Source + * 0b0..CAN bit clock + * 0b1..External time tick + */ +#define CAN_CTRL2_TIMER_SRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_TIMER_SRC_SHIFT)) & CAN_CTRL2_TIMER_SRC_MASK) + +#define CAN_CTRL2_EACEN_MASK (0x10000U) +#define CAN_CTRL2_EACEN_SHIFT (16U) +/*! EACEN - Entire Frame Arbitration Field Comparison Enable for RX Message Buffers + * 0b0..Disable + * 0b1..Enable + */ +#define CAN_CTRL2_EACEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_EACEN_SHIFT)) & CAN_CTRL2_EACEN_MASK) + +#define CAN_CTRL2_RRS_MASK (0x20000U) +#define CAN_CTRL2_RRS_SHIFT (17U) +/*! RRS - Remote Request Storing + * 0b0..Generated + * 0b1..Stored + */ +#define CAN_CTRL2_RRS(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_RRS_SHIFT)) & CAN_CTRL2_RRS_MASK) + +#define CAN_CTRL2_MRP_MASK (0x40000U) +#define CAN_CTRL2_MRP_SHIFT (18U) +/*! MRP - Message Buffers Reception Priority + * 0b0..Matching starts from Legacy RX FIFO or Enhanced RX FIFO and continues on message buffers. + * 0b1..Matching starts from message buffers and continues on Legacy RX FIFO or Enhanced RX FIFO. + */ +#define CAN_CTRL2_MRP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_MRP_SHIFT)) & CAN_CTRL2_MRP_MASK) + +#define CAN_CTRL2_TASD_MASK (0xF80000U) +#define CAN_CTRL2_TASD_SHIFT (19U) +/*! TASD - Transmission Arbitration Start Delay */ +#define CAN_CTRL2_TASD(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_TASD_SHIFT)) & CAN_CTRL2_TASD_MASK) + +#define CAN_CTRL2_RFFN_MASK (0xF000000U) +#define CAN_CTRL2_RFFN_SHIFT (24U) +/*! RFFN - Number of Legacy Receive FIFO Filters */ +#define CAN_CTRL2_RFFN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_RFFN_SHIFT)) & CAN_CTRL2_RFFN_MASK) + +#define CAN_CTRL2_WRMFRZ_MASK (0x10000000U) +#define CAN_CTRL2_WRMFRZ_SHIFT (28U) +/*! WRMFRZ - Write Access to Memory in Freeze Mode + * 0b0..Disable + * 0b1..Enable + */ +#define CAN_CTRL2_WRMFRZ(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_WRMFRZ_SHIFT)) & CAN_CTRL2_WRMFRZ_MASK) + +#define CAN_CTRL2_ECRWRE_MASK (0x20000000U) +#define CAN_CTRL2_ECRWRE_SHIFT (29U) +/*! ECRWRE - Error Correction Configuration Register Write Enable + * 0b0..Disable + * 0b1..Enable + */ +#define CAN_CTRL2_ECRWRE(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_ECRWRE_SHIFT)) & CAN_CTRL2_ECRWRE_MASK) + +#define CAN_CTRL2_BOFFDONEMSK_MASK (0x40000000U) +#define CAN_CTRL2_BOFFDONEMSK_SHIFT (30U) +/*! BOFFDONEMSK - Bus Off Done Interrupt Mask + * 0b0..Disable + * 0b1..Enable + */ +#define CAN_CTRL2_BOFFDONEMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_BOFFDONEMSK_SHIFT)) & CAN_CTRL2_BOFFDONEMSK_MASK) + +#define CAN_CTRL2_ERRMSK_FAST_MASK (0x80000000U) +#define CAN_CTRL2_ERRMSK_FAST_SHIFT (31U) +/*! ERRMSK_FAST - Error Interrupt Mask for Errors Detected in the Data Phase of Fast CAN FD Frames + * 0b0..Disable + * 0b1..Enable + */ +#define CAN_CTRL2_ERRMSK_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_ERRMSK_FAST_SHIFT)) & CAN_CTRL2_ERRMSK_FAST_MASK) +/*! @} */ + +/*! @name ESR2 - Error and Status 2 */ +/*! @{ */ + +#define CAN_ESR2_RX_PIN_ST_MASK (0x1000U) +#define CAN_ESR2_RX_PIN_ST_SHIFT (12U) +/*! RX_PIN_ST - RX Pin Status + * 0b0..RX pin is in the dominant state + * 0b1..RX pin is in a recessive state + */ +#define CAN_ESR2_RX_PIN_ST(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_RX_PIN_ST_SHIFT)) & CAN_ESR2_RX_PIN_ST_MASK) + +#define CAN_ESR2_IMB_MASK (0x2000U) +#define CAN_ESR2_IMB_SHIFT (13U) +/*! IMB - Inactive Message Buffer + * 0b0..Message buffer indicated by ESR2[LPTM] is not inactive. + * 0b1..At least one message buffer is inactive. + */ +#define CAN_ESR2_IMB(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_IMB_SHIFT)) & CAN_ESR2_IMB_MASK) + +#define CAN_ESR2_VPS_MASK (0x4000U) +#define CAN_ESR2_VPS_SHIFT (14U) +/*! VPS - Valid Priority Status + * 0b0..Invalid + * 0b1..Valid + */ +#define CAN_ESR2_VPS(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_VPS_SHIFT)) & CAN_ESR2_VPS_MASK) + +#define CAN_ESR2_LPTM_MASK (0x7F0000U) +#define CAN_ESR2_LPTM_SHIFT (16U) +/*! LPTM - Lowest Priority TX Message Buffer */ +#define CAN_ESR2_LPTM(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_LPTM_SHIFT)) & CAN_ESR2_LPTM_MASK) +/*! @} */ + +/*! @name CRCR - Cyclic Redundancy Check */ +/*! @{ */ + +#define CAN_CRCR_TXCRC_MASK (0x7FFFU) +#define CAN_CRCR_TXCRC_SHIFT (0U) +/*! TXCRC - Transmitted CRC value */ +#define CAN_CRCR_TXCRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CRCR_TXCRC_SHIFT)) & CAN_CRCR_TXCRC_MASK) + +#define CAN_CRCR_MBCRC_MASK (0x7F0000U) +#define CAN_CRCR_MBCRC_SHIFT (16U) +/*! MBCRC - CRC Message Buffer */ +#define CAN_CRCR_MBCRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CRCR_MBCRC_SHIFT)) & CAN_CRCR_MBCRC_MASK) +/*! @} */ + +/*! @name RXFGMASK - Legacy RX FIFO Global Mask */ +/*! @{ */ + +#define CAN_RXFGMASK_FGM_MASK (0xFFFFFFFFU) +#define CAN_RXFGMASK_FGM_SHIFT (0U) +/*! FGM - Legacy RX FIFO Global Mask Bits */ +#define CAN_RXFGMASK_FGM(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXFGMASK_FGM_SHIFT)) & CAN_RXFGMASK_FGM_MASK) +/*! @} */ + +/*! @name RXFIR - Legacy RX FIFO Information */ +/*! @{ */ + +#define CAN_RXFIR_IDHIT_MASK (0x1FFU) +#define CAN_RXFIR_IDHIT_SHIFT (0U) +/*! IDHIT - Identifier Acceptance Filter Hit Indicator */ +#define CAN_RXFIR_IDHIT(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXFIR_IDHIT_SHIFT)) & CAN_RXFIR_IDHIT_MASK) +/*! @} */ + +/*! @name CBT - CAN Bit Timing */ +/*! @{ */ + +#define CAN_CBT_EPSEG2_MASK (0x1FU) +#define CAN_CBT_EPSEG2_SHIFT (0U) +/*! EPSEG2 - Extended Phase Segment 2 */ +#define CAN_CBT_EPSEG2(x) (((uint32_t)(((uint32_t)(x)) << CAN_CBT_EPSEG2_SHIFT)) & CAN_CBT_EPSEG2_MASK) + +#define CAN_CBT_EPSEG1_MASK (0x3E0U) +#define CAN_CBT_EPSEG1_SHIFT (5U) +/*! EPSEG1 - Extended Phase Segment 1 */ +#define CAN_CBT_EPSEG1(x) (((uint32_t)(((uint32_t)(x)) << CAN_CBT_EPSEG1_SHIFT)) & CAN_CBT_EPSEG1_MASK) + +#define CAN_CBT_EPROPSEG_MASK (0xFC00U) +#define CAN_CBT_EPROPSEG_SHIFT (10U) +/*! EPROPSEG - Extended Propagation Segment */ +#define CAN_CBT_EPROPSEG(x) (((uint32_t)(((uint32_t)(x)) << CAN_CBT_EPROPSEG_SHIFT)) & CAN_CBT_EPROPSEG_MASK) + +#define CAN_CBT_ERJW_MASK (0x1F0000U) +#define CAN_CBT_ERJW_SHIFT (16U) +/*! ERJW - Extended Resync Jump Width */ +#define CAN_CBT_ERJW(x) (((uint32_t)(((uint32_t)(x)) << CAN_CBT_ERJW_SHIFT)) & CAN_CBT_ERJW_MASK) + +#define CAN_CBT_EPRESDIV_MASK (0x7FE00000U) +#define CAN_CBT_EPRESDIV_SHIFT (21U) +/*! EPRESDIV - Extended Prescaler Division Factor */ +#define CAN_CBT_EPRESDIV(x) (((uint32_t)(((uint32_t)(x)) << CAN_CBT_EPRESDIV_SHIFT)) & CAN_CBT_EPRESDIV_MASK) + +#define CAN_CBT_BTF_MASK (0x80000000U) +#define CAN_CBT_BTF_SHIFT (31U) +/*! BTF - Bit Timing Format Enable + * 0b0..Disable + * 0b1..Enable + */ +#define CAN_CBT_BTF(x) (((uint32_t)(((uint32_t)(x)) << CAN_CBT_BTF_SHIFT)) & CAN_CBT_BTF_MASK) +/*! @} */ + +/*! @name IMASK3 - Interrupt Masks 3 */ +/*! @{ */ + +#define CAN_IMASK3_BUF95TO64M_MASK (0xFFFFFFFFU) +#define CAN_IMASK3_BUF95TO64M_SHIFT (0U) +/*! BUF95TO64M - Buffer MBi Mask */ +#define CAN_IMASK3_BUF95TO64M(x) (((uint32_t)(((uint32_t)(x)) << CAN_IMASK3_BUF95TO64M_SHIFT)) & CAN_IMASK3_BUF95TO64M_MASK) +/*! @} */ + +/*! @name IFLAG3 - Interrupt Flags 3 */ +/*! @{ */ + +#define CAN_IFLAG3_BUF95TO64_MASK (0xFFFFFFFFU) +#define CAN_IFLAG3_BUF95TO64_SHIFT (0U) +/*! BUF95TO64 - Buffer MBi Interrupt */ +#define CAN_IFLAG3_BUF95TO64(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG3_BUF95TO64_SHIFT)) & CAN_IFLAG3_BUF95TO64_MASK) +/*! @} */ + +/*! @name ET - External Timer */ +/*! @{ */ + +#define CAN_ET_TIMER_MASK (0xFFFFFFFFU) +#define CAN_ET_TIMER_SHIFT (0U) +/*! TIMER - Timer */ +#define CAN_ET_TIMER(x) (((uint32_t)(((uint32_t)(x)) << CAN_ET_TIMER_SHIFT)) & CAN_ET_TIMER_MASK) +/*! @} */ + +/*! @name FLTCONF_IE - Fault Confinement Interrupt Enable */ +/*! @{ */ + +#define CAN_FLTCONF_IE_ATP_IE_MASK (0x1U) +#define CAN_FLTCONF_IE_ATP_IE_SHIFT (0U) +/*! ATP_IE - Active to Passive Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define CAN_FLTCONF_IE_ATP_IE(x) (((uint32_t)(((uint32_t)(x)) << CAN_FLTCONF_IE_ATP_IE_SHIFT)) & CAN_FLTCONF_IE_ATP_IE_MASK) + +#define CAN_FLTCONF_IE_PTA_IE_MASK (0x2U) +#define CAN_FLTCONF_IE_PTA_IE_SHIFT (1U) +/*! PTA_IE - Passive to Active Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define CAN_FLTCONF_IE_PTA_IE(x) (((uint32_t)(((uint32_t)(x)) << CAN_FLTCONF_IE_PTA_IE_SHIFT)) & CAN_FLTCONF_IE_PTA_IE_MASK) +/*! @} */ + +/*! @name RXIMR - Receive Individual Mask */ +/*! @{ */ + +#define CAN_RXIMR_MI_MASK (0xFFFFFFFFU) +#define CAN_RXIMR_MI_SHIFT (0U) +/*! MI - Individual Mask Bits */ +#define CAN_RXIMR_MI(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXIMR_MI_SHIFT)) & CAN_RXIMR_MI_MASK) +/*! @} */ + +/* The count of CAN_RXIMR */ +#define CAN_RXIMR_COUNT (96U) + +/*! @name MECR - Memory Error Control */ +/*! @{ */ + +#define CAN_MECR_NCEFAFRZ_MASK (0x80U) +#define CAN_MECR_NCEFAFRZ_SHIFT (7U) +/*! NCEFAFRZ - Noncorrectable Errors in FlexCAN Access Put Chip in Freeze Mode + * 0b0..Normal operation + * 0b1..Freeze mode + */ +#define CAN_MECR_NCEFAFRZ(x) (((uint32_t)(((uint32_t)(x)) << CAN_MECR_NCEFAFRZ_SHIFT)) & CAN_MECR_NCEFAFRZ_MASK) + +#define CAN_MECR_ECCDIS_MASK (0x100U) +#define CAN_MECR_ECCDIS_SHIFT (8U) +/*! ECCDIS - Error Correction Disable + * 0b0..Enable + * 0b1..Disable + */ +#define CAN_MECR_ECCDIS(x) (((uint32_t)(((uint32_t)(x)) << CAN_MECR_ECCDIS_SHIFT)) & CAN_MECR_ECCDIS_MASK) + +#define CAN_MECR_RERRDIS_MASK (0x200U) +#define CAN_MECR_RERRDIS_SHIFT (9U) +/*! RERRDIS - Error Report Disable + * 0b0..Enable + * 0b1..Disable + */ +#define CAN_MECR_RERRDIS(x) (((uint32_t)(((uint32_t)(x)) << CAN_MECR_RERRDIS_SHIFT)) & CAN_MECR_RERRDIS_MASK) + +#define CAN_MECR_EXTERRIE_MASK (0x2000U) +#define CAN_MECR_EXTERRIE_SHIFT (13U) +/*! EXTERRIE - Extended Error Injection Enable + * 0b0..Disable. Apply error injection only to the 32-bit word. + * 0b1..Enable. Apply error injection to the 64-bit word. + */ +#define CAN_MECR_EXTERRIE(x) (((uint32_t)(((uint32_t)(x)) << CAN_MECR_EXTERRIE_SHIFT)) & CAN_MECR_EXTERRIE_MASK) + +#define CAN_MECR_FAERRIE_MASK (0x4000U) +#define CAN_MECR_FAERRIE_SHIFT (14U) +/*! FAERRIE - FlexCAN Access Error Injection Enable + * 0b0..Disable + * 0b1..Enable + */ +#define CAN_MECR_FAERRIE(x) (((uint32_t)(((uint32_t)(x)) << CAN_MECR_FAERRIE_SHIFT)) & CAN_MECR_FAERRIE_MASK) + +#define CAN_MECR_HAERRIE_MASK (0x8000U) +#define CAN_MECR_HAERRIE_SHIFT (15U) +/*! HAERRIE - Host Access Error Injection Enable + * 0b0..Disable + * 0b1..Enable + */ +#define CAN_MECR_HAERRIE(x) (((uint32_t)(((uint32_t)(x)) << CAN_MECR_HAERRIE_SHIFT)) & CAN_MECR_HAERRIE_MASK) + +#define CAN_MECR_CEI_MSK_MASK (0x10000U) +#define CAN_MECR_CEI_MSK_SHIFT (16U) +/*! CEI_MSK - Correctable Errors Interrupt Mask + * 0b0..Disable + * 0b1..Enable + */ +#define CAN_MECR_CEI_MSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MECR_CEI_MSK_SHIFT)) & CAN_MECR_CEI_MSK_MASK) + +#define CAN_MECR_FANCEI_MSK_MASK (0x40000U) +#define CAN_MECR_FANCEI_MSK_SHIFT (18U) +/*! FANCEI_MSK - FlexCAN Access with Noncorrectable Errors Interrupt Mask + * 0b0..Disable + * 0b1..Enable + */ +#define CAN_MECR_FANCEI_MSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MECR_FANCEI_MSK_SHIFT)) & CAN_MECR_FANCEI_MSK_MASK) + +#define CAN_MECR_HANCEI_MSK_MASK (0x80000U) +#define CAN_MECR_HANCEI_MSK_SHIFT (19U) +/*! HANCEI_MSK - Host Access with Noncorrectable Errors Interrupt Mask + * 0b0..Disable + * 0b1..Enable + */ +#define CAN_MECR_HANCEI_MSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MECR_HANCEI_MSK_SHIFT)) & CAN_MECR_HANCEI_MSK_MASK) + +#define CAN_MECR_ECRWRDIS_MASK (0x80000000U) +#define CAN_MECR_ECRWRDIS_SHIFT (31U) +/*! ECRWRDIS - Error Configuration Register Write Disable + * 0b0..Enable + * 0b1..Disable + */ +#define CAN_MECR_ECRWRDIS(x) (((uint32_t)(((uint32_t)(x)) << CAN_MECR_ECRWRDIS_SHIFT)) & CAN_MECR_ECRWRDIS_MASK) +/*! @} */ + +/*! @name ERRIAR - Error Injection Address */ +/*! @{ */ + +#define CAN_ERRIAR_INJADDR_L_MASK (0x3U) +#define CAN_ERRIAR_INJADDR_L_SHIFT (0U) +/*! INJADDR_L - Error Injection Address Low */ +#define CAN_ERRIAR_INJADDR_L(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERRIAR_INJADDR_L_SHIFT)) & CAN_ERRIAR_INJADDR_L_MASK) + +#define CAN_ERRIAR_INJADDR_H_MASK (0x3FFCU) +#define CAN_ERRIAR_INJADDR_H_SHIFT (2U) +/*! INJADDR_H - Error Injection Address High */ +#define CAN_ERRIAR_INJADDR_H(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERRIAR_INJADDR_H_SHIFT)) & CAN_ERRIAR_INJADDR_H_MASK) +/*! @} */ + +/*! @name ERRIDPR - Error Injection Data Pattern */ +/*! @{ */ + +#define CAN_ERRIDPR_DFLIP_MASK (0xFFFFFFFFU) +#define CAN_ERRIDPR_DFLIP_SHIFT (0U) +/*! DFLIP - Data Flip Pattern */ +#define CAN_ERRIDPR_DFLIP(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERRIDPR_DFLIP_SHIFT)) & CAN_ERRIDPR_DFLIP_MASK) +/*! @} */ + +/*! @name ERRIPPR - Error Injection Parity Pattern */ +/*! @{ */ + +#define CAN_ERRIPPR_PFLIP0_MASK (0x1FU) +#define CAN_ERRIPPR_PFLIP0_SHIFT (0U) +/*! PFLIP0 - Parity Flip Pattern for Byte 0 (Least Significant) */ +#define CAN_ERRIPPR_PFLIP0(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERRIPPR_PFLIP0_SHIFT)) & CAN_ERRIPPR_PFLIP0_MASK) + +#define CAN_ERRIPPR_PFLIP1_MASK (0x1F00U) +#define CAN_ERRIPPR_PFLIP1_SHIFT (8U) +/*! PFLIP1 - Parity Flip Pattern for Byte 1 */ +#define CAN_ERRIPPR_PFLIP1(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERRIPPR_PFLIP1_SHIFT)) & CAN_ERRIPPR_PFLIP1_MASK) + +#define CAN_ERRIPPR_PFLIP2_MASK (0x1F0000U) +#define CAN_ERRIPPR_PFLIP2_SHIFT (16U) +/*! PFLIP2 - Parity Flip Pattern for Byte 2 */ +#define CAN_ERRIPPR_PFLIP2(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERRIPPR_PFLIP2_SHIFT)) & CAN_ERRIPPR_PFLIP2_MASK) + +#define CAN_ERRIPPR_PFLIP3_MASK (0x1F000000U) +#define CAN_ERRIPPR_PFLIP3_SHIFT (24U) +/*! PFLIP3 - Parity Flip Pattern for Byte 3 (Most Significant) */ +#define CAN_ERRIPPR_PFLIP3(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERRIPPR_PFLIP3_SHIFT)) & CAN_ERRIPPR_PFLIP3_MASK) +/*! @} */ + +/*! @name RERRAR - Error Report Address */ +/*! @{ */ + +#define CAN_RERRAR_ERRADDR_MASK (0x3FFFU) +#define CAN_RERRAR_ERRADDR_SHIFT (0U) +/*! ERRADDR - Address Where Error Detected */ +#define CAN_RERRAR_ERRADDR(x) (((uint32_t)(((uint32_t)(x)) << CAN_RERRAR_ERRADDR_SHIFT)) & CAN_RERRAR_ERRADDR_MASK) + +#define CAN_RERRAR_SAID_MASK (0x70000U) +#define CAN_RERRAR_SAID_SHIFT (16U) +/*! SAID - SAID */ +#define CAN_RERRAR_SAID(x) (((uint32_t)(((uint32_t)(x)) << CAN_RERRAR_SAID_SHIFT)) & CAN_RERRAR_SAID_MASK) + +#define CAN_RERRAR_NCE_MASK (0x1000000U) +#define CAN_RERRAR_NCE_SHIFT (24U) +/*! NCE - Noncorrectable Error + * 0b0..Reporting a correctable error + * 0b1..Reporting a noncorrectable error + */ +#define CAN_RERRAR_NCE(x) (((uint32_t)(((uint32_t)(x)) << CAN_RERRAR_NCE_SHIFT)) & CAN_RERRAR_NCE_MASK) +/*! @} */ + +/*! @name RERRDR - Error Report Data */ +/*! @{ */ + +#define CAN_RERRDR_RDATA_MASK (0xFFFFFFFFU) +#define CAN_RERRDR_RDATA_SHIFT (0U) +/*! RDATA - Raw Data Word Read from Memory with Error */ +#define CAN_RERRDR_RDATA(x) (((uint32_t)(((uint32_t)(x)) << CAN_RERRDR_RDATA_SHIFT)) & CAN_RERRDR_RDATA_MASK) +/*! @} */ + +/*! @name RERRSYNR - Error Report Syndrome */ +/*! @{ */ + +#define CAN_RERRSYNR_SYND0_MASK (0x1FU) +#define CAN_RERRSYNR_SYND0_SHIFT (0U) +/*! SYND0 - Error Syndrome for Byte 0 (Least Significant) */ +#define CAN_RERRSYNR_SYND0(x) (((uint32_t)(((uint32_t)(x)) << CAN_RERRSYNR_SYND0_SHIFT)) & CAN_RERRSYNR_SYND0_MASK) + +#define CAN_RERRSYNR_BE0_MASK (0x80U) +#define CAN_RERRSYNR_BE0_SHIFT (7U) +/*! BE0 - Byte Enabled for Byte 0 (Least Significant) + * 0b0..Byte was not read. + * 0b1..Byte was read. + */ +#define CAN_RERRSYNR_BE0(x) (((uint32_t)(((uint32_t)(x)) << CAN_RERRSYNR_BE0_SHIFT)) & CAN_RERRSYNR_BE0_MASK) + +#define CAN_RERRSYNR_SYND1_MASK (0x1F00U) +#define CAN_RERRSYNR_SYND1_SHIFT (8U) +/*! SYND1 - Error Syndrome for Byte 1 */ +#define CAN_RERRSYNR_SYND1(x) (((uint32_t)(((uint32_t)(x)) << CAN_RERRSYNR_SYND1_SHIFT)) & CAN_RERRSYNR_SYND1_MASK) + +#define CAN_RERRSYNR_BE1_MASK (0x8000U) +#define CAN_RERRSYNR_BE1_SHIFT (15U) +/*! BE1 - Byte Enabled for Byte 1 + * 0b0..Byte was not read. + * 0b1..Byte was read. + */ +#define CAN_RERRSYNR_BE1(x) (((uint32_t)(((uint32_t)(x)) << CAN_RERRSYNR_BE1_SHIFT)) & CAN_RERRSYNR_BE1_MASK) + +#define CAN_RERRSYNR_SYND2_MASK (0x1F0000U) +#define CAN_RERRSYNR_SYND2_SHIFT (16U) +/*! SYND2 - Error Syndrome for Byte 2 */ +#define CAN_RERRSYNR_SYND2(x) (((uint32_t)(((uint32_t)(x)) << CAN_RERRSYNR_SYND2_SHIFT)) & CAN_RERRSYNR_SYND2_MASK) + +#define CAN_RERRSYNR_BE2_MASK (0x800000U) +#define CAN_RERRSYNR_BE2_SHIFT (23U) +/*! BE2 - Byte Enabled for Byte 2 + * 0b0..Byte was not read. + * 0b1..Byte was read. + */ +#define CAN_RERRSYNR_BE2(x) (((uint32_t)(((uint32_t)(x)) << CAN_RERRSYNR_BE2_SHIFT)) & CAN_RERRSYNR_BE2_MASK) + +#define CAN_RERRSYNR_SYND3_MASK (0x1F000000U) +#define CAN_RERRSYNR_SYND3_SHIFT (24U) +/*! SYND3 - Error Syndrome for Byte 3 (Most Significant) */ +#define CAN_RERRSYNR_SYND3(x) (((uint32_t)(((uint32_t)(x)) << CAN_RERRSYNR_SYND3_SHIFT)) & CAN_RERRSYNR_SYND3_MASK) + +#define CAN_RERRSYNR_BE3_MASK (0x80000000U) +#define CAN_RERRSYNR_BE3_SHIFT (31U) +/*! BE3 - Byte Enabled for Byte 3 (Most Significant) + * 0b0..Byte was not read. + * 0b1..Byte was read. + */ +#define CAN_RERRSYNR_BE3(x) (((uint32_t)(((uint32_t)(x)) << CAN_RERRSYNR_BE3_SHIFT)) & CAN_RERRSYNR_BE3_MASK) +/*! @} */ + +/*! @name ERRSR - Error Status */ +/*! @{ */ + +#define CAN_ERRSR_CEIOF_MASK (0x1U) +#define CAN_ERRSR_CEIOF_SHIFT (0U) +/*! CEIOF - Correctable Error Interrupt Overrun Flag + * 0b0..No errors detected + * 0b1..Error detected + */ +#define CAN_ERRSR_CEIOF(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERRSR_CEIOF_SHIFT)) & CAN_ERRSR_CEIOF_MASK) + +#define CAN_ERRSR_FANCEIOF_MASK (0x4U) +#define CAN_ERRSR_FANCEIOF_SHIFT (2U) +/*! FANCEIOF - FlexCAN Access with Noncorrectable Error Interrupt Overrun Flag + * 0b0..No errors detected + * 0b1..Error detected + */ +#define CAN_ERRSR_FANCEIOF(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERRSR_FANCEIOF_SHIFT)) & CAN_ERRSR_FANCEIOF_MASK) + +#define CAN_ERRSR_HANCEIOF_MASK (0x8U) +#define CAN_ERRSR_HANCEIOF_SHIFT (3U) +/*! HANCEIOF - Host Access With Noncorrectable Error Interrupt Overrun Flag + * 0b0..No errors detected + * 0b1..Error detected + */ +#define CAN_ERRSR_HANCEIOF(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERRSR_HANCEIOF_SHIFT)) & CAN_ERRSR_HANCEIOF_MASK) + +#define CAN_ERRSR_CEIF_MASK (0x10000U) +#define CAN_ERRSR_CEIF_SHIFT (16U) +/*! CEIF - Correctable Error Interrupt Flag + * 0b0..No errors detected + * 0b1..Error detected + */ +#define CAN_ERRSR_CEIF(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERRSR_CEIF_SHIFT)) & CAN_ERRSR_CEIF_MASK) + +#define CAN_ERRSR_FANCEIF_MASK (0x40000U) +#define CAN_ERRSR_FANCEIF_SHIFT (18U) +/*! FANCEIF - FlexCAN Access with Noncorrectable Error Interrupt Flag + * 0b0..No errors detected + * 0b1..Error detected + */ +#define CAN_ERRSR_FANCEIF(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERRSR_FANCEIF_SHIFT)) & CAN_ERRSR_FANCEIF_MASK) + +#define CAN_ERRSR_HANCEIF_MASK (0x80000U) +#define CAN_ERRSR_HANCEIF_SHIFT (19U) +/*! HANCEIF - Host Access with Noncorrectable Error Interrupt Flag + * 0b0..No errors detected + * 0b1..Error detected + */ +#define CAN_ERRSR_HANCEIF(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERRSR_HANCEIF_SHIFT)) & CAN_ERRSR_HANCEIF_MASK) +/*! @} */ + +/*! @name EPRS - Enhanced CAN Bit Timing Prescalers */ +/*! @{ */ + +#define CAN_EPRS_ENPRESDIV_MASK (0x3FFU) +#define CAN_EPRS_ENPRESDIV_SHIFT (0U) +/*! ENPRESDIV - Extended Nominal Prescaler Division Factor */ +#define CAN_EPRS_ENPRESDIV(x) (((uint32_t)(((uint32_t)(x)) << CAN_EPRS_ENPRESDIV_SHIFT)) & CAN_EPRS_ENPRESDIV_MASK) + +#define CAN_EPRS_EDPRESDIV_MASK (0x3FF0000U) +#define CAN_EPRS_EDPRESDIV_SHIFT (16U) +/*! EDPRESDIV - Extended Data Phase Prescaler Division Factor */ +#define CAN_EPRS_EDPRESDIV(x) (((uint32_t)(((uint32_t)(x)) << CAN_EPRS_EDPRESDIV_SHIFT)) & CAN_EPRS_EDPRESDIV_MASK) +/*! @} */ + +/*! @name ENCBT - Enhanced Nominal CAN Bit Timing */ +/*! @{ */ + +#define CAN_ENCBT_NTSEG1_MASK (0xFFU) +#define CAN_ENCBT_NTSEG1_SHIFT (0U) +/*! NTSEG1 - Nominal Time Segment 1 */ +#define CAN_ENCBT_NTSEG1(x) (((uint32_t)(((uint32_t)(x)) << CAN_ENCBT_NTSEG1_SHIFT)) & CAN_ENCBT_NTSEG1_MASK) + +#define CAN_ENCBT_NTSEG2_MASK (0x7F000U) +#define CAN_ENCBT_NTSEG2_SHIFT (12U) +/*! NTSEG2 - Nominal Time Segment 2 */ +#define CAN_ENCBT_NTSEG2(x) (((uint32_t)(((uint32_t)(x)) << CAN_ENCBT_NTSEG2_SHIFT)) & CAN_ENCBT_NTSEG2_MASK) + +#define CAN_ENCBT_NRJW_MASK (0x1FC00000U) +#define CAN_ENCBT_NRJW_SHIFT (22U) +/*! NRJW - Nominal Resynchronization Jump Width */ +#define CAN_ENCBT_NRJW(x) (((uint32_t)(((uint32_t)(x)) << CAN_ENCBT_NRJW_SHIFT)) & CAN_ENCBT_NRJW_MASK) +/*! @} */ + +/*! @name EDCBT - Enhanced Data Phase CAN Bit Timing */ +/*! @{ */ + +#define CAN_EDCBT_DTSEG1_MASK (0x1FU) +#define CAN_EDCBT_DTSEG1_SHIFT (0U) +/*! DTSEG1 - Data Phase Segment 1 */ +#define CAN_EDCBT_DTSEG1(x) (((uint32_t)(((uint32_t)(x)) << CAN_EDCBT_DTSEG1_SHIFT)) & CAN_EDCBT_DTSEG1_MASK) + +#define CAN_EDCBT_DTSEG2_MASK (0xF000U) +#define CAN_EDCBT_DTSEG2_SHIFT (12U) +/*! DTSEG2 - Data Phase Time Segment 2 */ +#define CAN_EDCBT_DTSEG2(x) (((uint32_t)(((uint32_t)(x)) << CAN_EDCBT_DTSEG2_SHIFT)) & CAN_EDCBT_DTSEG2_MASK) + +#define CAN_EDCBT_DRJW_MASK (0x3C00000U) +#define CAN_EDCBT_DRJW_SHIFT (22U) +/*! DRJW - Data Phase Resynchronization Jump Width */ +#define CAN_EDCBT_DRJW(x) (((uint32_t)(((uint32_t)(x)) << CAN_EDCBT_DRJW_SHIFT)) & CAN_EDCBT_DRJW_MASK) +/*! @} */ + +/*! @name ETDC - Enhanced Transceiver Delay Compensation */ +/*! @{ */ + +#define CAN_ETDC_ETDCVAL_MASK (0xFFU) +#define CAN_ETDC_ETDCVAL_SHIFT (0U) +/*! ETDCVAL - Enhanced Transceiver Delay Compensation Value */ +#define CAN_ETDC_ETDCVAL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ETDC_ETDCVAL_SHIFT)) & CAN_ETDC_ETDCVAL_MASK) + +#define CAN_ETDC_ETDCFAIL_MASK (0x8000U) +#define CAN_ETDC_ETDCFAIL_SHIFT (15U) +/*! ETDCFAIL - Transceiver Delay Compensation Fail + * 0b0..In range + * 0b1..Out of range + */ +#define CAN_ETDC_ETDCFAIL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ETDC_ETDCFAIL_SHIFT)) & CAN_ETDC_ETDCFAIL_MASK) + +#define CAN_ETDC_ETDCOFF_MASK (0x7F0000U) +#define CAN_ETDC_ETDCOFF_SHIFT (16U) +/*! ETDCOFF - Enhanced Transceiver Delay Compensation Offset */ +#define CAN_ETDC_ETDCOFF(x) (((uint32_t)(((uint32_t)(x)) << CAN_ETDC_ETDCOFF_SHIFT)) & CAN_ETDC_ETDCOFF_MASK) + +#define CAN_ETDC_TDMDIS_MASK (0x40000000U) +#define CAN_ETDC_TDMDIS_SHIFT (30U) +/*! TDMDIS - Transceiver Delay Measurement Disable + * 0b0..Enable + * 0b1..Disable + */ +#define CAN_ETDC_TDMDIS(x) (((uint32_t)(((uint32_t)(x)) << CAN_ETDC_TDMDIS_SHIFT)) & CAN_ETDC_TDMDIS_MASK) + +#define CAN_ETDC_ETDCEN_MASK (0x80000000U) +#define CAN_ETDC_ETDCEN_SHIFT (31U) +/*! ETDCEN - Transceiver Delay Compensation Enable + * 0b0..Disable + * 0b1..Enable + */ +#define CAN_ETDC_ETDCEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_ETDC_ETDCEN_SHIFT)) & CAN_ETDC_ETDCEN_MASK) +/*! @} */ + +/*! @name FDCTRL - CAN FD Control */ +/*! @{ */ + +#define CAN_FDCTRL_TDCVAL_MASK (0x3FU) +#define CAN_FDCTRL_TDCVAL_SHIFT (0U) +/*! TDCVAL - Transceiver Delay Compensation Value */ +#define CAN_FDCTRL_TDCVAL(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_TDCVAL_SHIFT)) & CAN_FDCTRL_TDCVAL_MASK) + +#define CAN_FDCTRL_TDCOFF_MASK (0x1F00U) +#define CAN_FDCTRL_TDCOFF_SHIFT (8U) +/*! TDCOFF - Transceiver Delay Compensation Offset */ +#define CAN_FDCTRL_TDCOFF(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_TDCOFF_SHIFT)) & CAN_FDCTRL_TDCOFF_MASK) + +#define CAN_FDCTRL_TDCFAIL_MASK (0x4000U) +#define CAN_FDCTRL_TDCFAIL_SHIFT (14U) +/*! TDCFAIL - Transceiver Delay Compensation Fail + * 0b0..In range + * 0b1..Out of range + */ +#define CAN_FDCTRL_TDCFAIL(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_TDCFAIL_SHIFT)) & CAN_FDCTRL_TDCFAIL_MASK) + +#define CAN_FDCTRL_TDCEN_MASK (0x8000U) +#define CAN_FDCTRL_TDCEN_SHIFT (15U) +/*! TDCEN - Transceiver Delay Compensation Enable + * 0b0..Disable + * 0b1..Enable + */ +#define CAN_FDCTRL_TDCEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_TDCEN_SHIFT)) & CAN_FDCTRL_TDCEN_MASK) + +#define CAN_FDCTRL_MBDSR0_MASK (0x30000U) +#define CAN_FDCTRL_MBDSR0_SHIFT (16U) +/*! MBDSR0 - Message Buffer Data Size for Region 0 + * 0b00..8 bytes + * 0b01..16 bytes + * 0b10..32 bytes + * 0b11..64 bytes + */ +#define CAN_FDCTRL_MBDSR0(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_MBDSR0_SHIFT)) & CAN_FDCTRL_MBDSR0_MASK) + +#define CAN_FDCTRL_MBDSR1_MASK (0x180000U) +#define CAN_FDCTRL_MBDSR1_SHIFT (19U) +/*! MBDSR1 - Message Buffer Data Size for Region 1 + * 0b00..8 bytes + * 0b01..16 bytes + * 0b10..32 bytes + * 0b11..64 bytes + */ +#define CAN_FDCTRL_MBDSR1(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_MBDSR1_SHIFT)) & CAN_FDCTRL_MBDSR1_MASK) + +#define CAN_FDCTRL_MBDSR2_MASK (0xC00000U) +#define CAN_FDCTRL_MBDSR2_SHIFT (22U) +/*! MBDSR2 - Message Buffer Data Size for Region 2 + * 0b00..8 bytes + * 0b01..16 bytes + * 0b10..32 bytes + * 0b11..64 bytes + */ +#define CAN_FDCTRL_MBDSR2(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_MBDSR2_SHIFT)) & CAN_FDCTRL_MBDSR2_MASK) + +#define CAN_FDCTRL_FDRATE_MASK (0x80000000U) +#define CAN_FDCTRL_FDRATE_SHIFT (31U) +/*! FDRATE - Bit Rate Switch Enable + * 0b0..Disable + * 0b1..Enable + */ +#define CAN_FDCTRL_FDRATE(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_FDRATE_SHIFT)) & CAN_FDCTRL_FDRATE_MASK) +/*! @} */ + +/*! @name FDCBT - CAN FD Bit Timing */ +/*! @{ */ + +#define CAN_FDCBT_FPSEG2_MASK (0x7U) +#define CAN_FDCBT_FPSEG2_SHIFT (0U) +/*! FPSEG2 - Fast Phase Segment 2 */ +#define CAN_FDCBT_FPSEG2(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCBT_FPSEG2_SHIFT)) & CAN_FDCBT_FPSEG2_MASK) + +#define CAN_FDCBT_FPSEG1_MASK (0xE0U) +#define CAN_FDCBT_FPSEG1_SHIFT (5U) +/*! FPSEG1 - Fast Phase Segment 1 */ +#define CAN_FDCBT_FPSEG1(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCBT_FPSEG1_SHIFT)) & CAN_FDCBT_FPSEG1_MASK) + +#define CAN_FDCBT_FPROPSEG_MASK (0x7C00U) +#define CAN_FDCBT_FPROPSEG_SHIFT (10U) +/*! FPROPSEG - Fast Propagation Segment */ +#define CAN_FDCBT_FPROPSEG(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCBT_FPROPSEG_SHIFT)) & CAN_FDCBT_FPROPSEG_MASK) + +#define CAN_FDCBT_FRJW_MASK (0x70000U) +#define CAN_FDCBT_FRJW_SHIFT (16U) +/*! FRJW - Fast Resync Jump Width */ +#define CAN_FDCBT_FRJW(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCBT_FRJW_SHIFT)) & CAN_FDCBT_FRJW_MASK) + +#define CAN_FDCBT_FPRESDIV_MASK (0x3FF00000U) +#define CAN_FDCBT_FPRESDIV_SHIFT (20U) +/*! FPRESDIV - Fast Prescaler Division Factor */ +#define CAN_FDCBT_FPRESDIV(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCBT_FPRESDIV_SHIFT)) & CAN_FDCBT_FPRESDIV_MASK) +/*! @} */ + +/*! @name FDCRC - CAN FD CRC */ +/*! @{ */ + +#define CAN_FDCRC_FD_TXCRC_MASK (0x1FFFFFU) +#define CAN_FDCRC_FD_TXCRC_SHIFT (0U) +/*! FD_TXCRC - Extended Transmitted CRC value */ +#define CAN_FDCRC_FD_TXCRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCRC_FD_TXCRC_SHIFT)) & CAN_FDCRC_FD_TXCRC_MASK) + +#define CAN_FDCRC_FD_MBCRC_MASK (0x7F000000U) +#define CAN_FDCRC_FD_MBCRC_SHIFT (24U) +/*! FD_MBCRC - CRC Message Buffer Number for FD_TXCRC */ +#define CAN_FDCRC_FD_MBCRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCRC_FD_MBCRC_SHIFT)) & CAN_FDCRC_FD_MBCRC_MASK) +/*! @} */ + +/*! @name ERFCR - Enhanced RX FIFO Control */ +/*! @{ */ + +#define CAN_ERFCR_ERFWM_MASK (0x1FU) +#define CAN_ERFCR_ERFWM_SHIFT (0U) +/*! ERFWM - Enhanced RX FIFO Watermark */ +#define CAN_ERFCR_ERFWM(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFCR_ERFWM_SHIFT)) & CAN_ERFCR_ERFWM_MASK) + +#define CAN_ERFCR_NFE_MASK (0x3F00U) +#define CAN_ERFCR_NFE_SHIFT (8U) +/*! NFE - Number of Enhanced RX FIFO Filter Elements */ +#define CAN_ERFCR_NFE(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFCR_NFE_SHIFT)) & CAN_ERFCR_NFE_MASK) + +#define CAN_ERFCR_NEXIF_MASK (0x7F0000U) +#define CAN_ERFCR_NEXIF_SHIFT (16U) +/*! NEXIF - Number of Extended ID Filter Elements */ +#define CAN_ERFCR_NEXIF(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFCR_NEXIF_SHIFT)) & CAN_ERFCR_NEXIF_MASK) + +#define CAN_ERFCR_DMALW_MASK (0x7C000000U) +#define CAN_ERFCR_DMALW_SHIFT (26U) +/*! DMALW - DMA Last Word */ +#define CAN_ERFCR_DMALW(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFCR_DMALW_SHIFT)) & CAN_ERFCR_DMALW_MASK) + +#define CAN_ERFCR_ERFEN_MASK (0x80000000U) +#define CAN_ERFCR_ERFEN_SHIFT (31U) +/*! ERFEN - Enhanced RX FIFO enable + * 0b0..Disable + * 0b1..Enable + */ +#define CAN_ERFCR_ERFEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFCR_ERFEN_SHIFT)) & CAN_ERFCR_ERFEN_MASK) +/*! @} */ + +/*! @name ERFIER - Enhanced RX FIFO Interrupt Enable */ +/*! @{ */ + +#define CAN_ERFIER_ERFDAIE_MASK (0x10000000U) +#define CAN_ERFIER_ERFDAIE_SHIFT (28U) +/*! ERFDAIE - Enhanced RX FIFO Data Available Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define CAN_ERFIER_ERFDAIE(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFIER_ERFDAIE_SHIFT)) & CAN_ERFIER_ERFDAIE_MASK) + +#define CAN_ERFIER_ERFWMIIE_MASK (0x20000000U) +#define CAN_ERFIER_ERFWMIIE_SHIFT (29U) +/*! ERFWMIIE - Enhanced RX FIFO Watermark Indication Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define CAN_ERFIER_ERFWMIIE(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFIER_ERFWMIIE_SHIFT)) & CAN_ERFIER_ERFWMIIE_MASK) + +#define CAN_ERFIER_ERFOVFIE_MASK (0x40000000U) +#define CAN_ERFIER_ERFOVFIE_SHIFT (30U) +/*! ERFOVFIE - Enhanced RX FIFO Overflow Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define CAN_ERFIER_ERFOVFIE(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFIER_ERFOVFIE_SHIFT)) & CAN_ERFIER_ERFOVFIE_MASK) + +#define CAN_ERFIER_ERFUFWIE_MASK (0x80000000U) +#define CAN_ERFIER_ERFUFWIE_SHIFT (31U) +/*! ERFUFWIE - Enhanced RX FIFO Underflow Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define CAN_ERFIER_ERFUFWIE(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFIER_ERFUFWIE_SHIFT)) & CAN_ERFIER_ERFUFWIE_MASK) +/*! @} */ + +/*! @name ERFSR - Enhanced RX FIFO Status */ +/*! @{ */ + +#define CAN_ERFSR_ERFEL_MASK (0x3FU) +#define CAN_ERFSR_ERFEL_SHIFT (0U) +/*! ERFEL - Enhanced RX FIFO Elements */ +#define CAN_ERFSR_ERFEL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFSR_ERFEL_SHIFT)) & CAN_ERFSR_ERFEL_MASK) + +#define CAN_ERFSR_ERFF_MASK (0x10000U) +#define CAN_ERFSR_ERFF_SHIFT (16U) +/*! ERFF - Enhanced RX FIFO Full Flag + * 0b0..Not full + * 0b1..Full + */ +#define CAN_ERFSR_ERFF(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFSR_ERFF_SHIFT)) & CAN_ERFSR_ERFF_MASK) + +#define CAN_ERFSR_ERFE_MASK (0x20000U) +#define CAN_ERFSR_ERFE_SHIFT (17U) +/*! ERFE - Enhanced RX FIFO Empty Flag + * 0b0..Not empty + * 0b1..Empty + */ +#define CAN_ERFSR_ERFE(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFSR_ERFE_SHIFT)) & CAN_ERFSR_ERFE_MASK) + +#define CAN_ERFSR_ERFCLR_MASK (0x8000000U) +#define CAN_ERFSR_ERFCLR_SHIFT (27U) +/*! ERFCLR - Enhanced RX FIFO Clear + * 0b0..No effect + * 0b1..Clear enhanced RX FIFO content + */ +#define CAN_ERFSR_ERFCLR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFSR_ERFCLR_SHIFT)) & CAN_ERFSR_ERFCLR_MASK) + +#define CAN_ERFSR_ERFDA_MASK (0x10000000U) +#define CAN_ERFSR_ERFDA_SHIFT (28U) +/*! ERFDA - Enhanced RX FIFO Data Available Flag + * 0b0..No such occurrence + * 0b1..At least one message stored in Enhanced RX FIFO + */ +#define CAN_ERFSR_ERFDA(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFSR_ERFDA_SHIFT)) & CAN_ERFSR_ERFDA_MASK) + +#define CAN_ERFSR_ERFWMI_MASK (0x20000000U) +#define CAN_ERFSR_ERFWMI_SHIFT (29U) +/*! ERFWMI - Enhanced RX FIFO Watermark Indication Flag + * 0b0..No such occurrence + * 0b1..Number of messages in FIFO is greater than the watermark + */ +#define CAN_ERFSR_ERFWMI(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFSR_ERFWMI_SHIFT)) & CAN_ERFSR_ERFWMI_MASK) + +#define CAN_ERFSR_ERFOVF_MASK (0x40000000U) +#define CAN_ERFSR_ERFOVF_SHIFT (30U) +/*! ERFOVF - Enhanced RX FIFO Overflow Flag + * 0b0..No such occurrence + * 0b1..Overflow + */ +#define CAN_ERFSR_ERFOVF(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFSR_ERFOVF_SHIFT)) & CAN_ERFSR_ERFOVF_MASK) + +#define CAN_ERFSR_ERFUFW_MASK (0x80000000U) +#define CAN_ERFSR_ERFUFW_SHIFT (31U) +/*! ERFUFW - Enhanced RX FIFO Underflow Flag + * 0b0..No such occurrence + * 0b1..Underflow + */ +#define CAN_ERFSR_ERFUFW(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFSR_ERFUFW_SHIFT)) & CAN_ERFSR_ERFUFW_MASK) +/*! @} */ + +/*! @name HR_TIME_STAMP - High-Resolution Timestamp */ +/*! @{ */ + +#define CAN_HR_TIME_STAMP_TS_MASK (0xFFFFFFFFU) +#define CAN_HR_TIME_STAMP_TS_SHIFT (0U) +/*! TS - High-Resolution Timestamp */ +#define CAN_HR_TIME_STAMP_TS(x) (((uint32_t)(((uint32_t)(x)) << CAN_HR_TIME_STAMP_TS_SHIFT)) & CAN_HR_TIME_STAMP_TS_MASK) +/*! @} */ + +/* The count of CAN_HR_TIME_STAMP */ +#define CAN_HR_TIME_STAMP_COUNT (96U) + +/*! @name ERFFEL - Enhanced RX FIFO Filter Element */ +/*! @{ */ + +#define CAN_ERFFEL_FEL_MASK (0xFFFFFFFFU) +#define CAN_ERFFEL_FEL_SHIFT (0U) +/*! FEL - Filter Element Bits */ +#define CAN_ERFFEL_FEL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFFEL_FEL_SHIFT)) & CAN_ERFFEL_FEL_MASK) +/*! @} */ + +/* The count of CAN_ERFFEL */ +#define CAN_ERFFEL_COUNT (128U) + + +/*! + * @} + */ /* end of group CAN_Register_Masks */ + + +/* CAN - Peripheral instance base addresses */ +/** Peripheral CAN1 base address */ +#define CAN1_BASE (0x443A0000u) +/** Peripheral CAN1 base pointer */ +#define CAN1 ((CAN_Type *)CAN1_BASE) +/** Peripheral CAN2 base address */ +#define CAN2_BASE (0x425B0000u) +/** Peripheral CAN2 base pointer */ +#define CAN2 ((CAN_Type *)CAN2_BASE) +/** Array initializer of CAN peripheral base addresses */ +#define CAN_BASE_ADDRS { 0u, CAN1_BASE, CAN2_BASE } +/** Array initializer of CAN peripheral base pointers */ +#define CAN_BASE_PTRS { (CAN_Type *)0u, CAN1, CAN2 } +/** Interrupt vectors for the CAN peripheral type */ +#define CAN_Rx_Warning_IRQS { NotAvail_IRQn, CAN1_IRQn, CAN2_IRQn } +#define CAN_Tx_Warning_IRQS { NotAvail_IRQn, CAN1_IRQn, CAN2_IRQn } +#define CAN_Wake_Up_IRQS { NotAvail_IRQn, CAN1_IRQn, CAN2_IRQn } +#define CAN_Error_IRQS { NotAvail_IRQn, CAN1_IRQn, CAN2_IRQn } +#define CAN_Bus_Off_IRQS { NotAvail_IRQn, CAN1_IRQn, CAN2_IRQn } + +/*! + * @} + */ /* end of group CAN_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- CCM Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CCM_Peripheral_Access_Layer CCM Peripheral Access Layer + * @{ + */ + +/** CCM - Register Layout Typedef */ +typedef struct { + struct { /* offset: 0x0, array step: 0x80 */ + struct { /* offset: 0x0 */ + __IO uint32_t RW; /**< Clock Root Control Register, offset: 0x0 */ + __IO uint32_t SET; /**< Clock Root Control Register, offset: 0x4 */ + __IO uint32_t CLR; /**< Clock Root Control Register, offset: 0x8 */ + __IO uint32_t TOG; /**< Clock Root Control Register, offset: 0xC */ + } CLOCK_ROOT_CONTROL; + uint8_t RESERVED_0[16]; + __IO uint32_t STATUS0; /**< Clock root working status, array offset: 0x20, array step: 0x80 */ + uint8_t RESERVED_1[12]; + struct { /* offset: 0x30 */ + __IO uint32_t RW; /**< Clock root access control, offset: 0x30 */ + __IO uint32_t SET; /**< Clock root access control, offset: 0x34 */ + __IO uint32_t CLR; /**< Clock root access control, offset: 0x38 */ + __IO uint32_t TOG; /**< Clock root access control, offset: 0x3C */ + } CLOCK_ROOT_AUTHEN; + uint8_t RESERVED_2[64]; + } CLOCK_ROOT[95]; + uint8_t RESERVED_0[6272]; + struct { /* offset: 0x4800 */ + uint32_t RW; /**< General Purpose Register, offset: 0x4800 */ + uint32_t SET; /**< General Purpose Register, offset: 0x4804 */ + uint32_t CLR; /**< General Purpose Register, offset: 0x4808 */ + uint32_t TOG; /**< General Purpose Register, offset: 0x480C */ + } GPR_SHARED0; + struct { /* offset: 0x4810 */ + __IO uint32_t RW; /**< GPR access control, offset: 0x4810 */ + __IO uint32_t SET; /**< GPR access control, offset: 0x4814 */ + __IO uint32_t CLR; /**< GPR access control, offset: 0x4818 */ + __IO uint32_t TOG; /**< GPR access control, offset: 0x481C */ + } GPR_SHARED0_AUTHEN; + struct { /* offset: 0x4820 */ + __IO uint32_t RW; /**< General Purpose Register, offset: 0x4820 */ + __IO uint32_t SET; /**< General Purpose Register, offset: 0x4824 */ + __IO uint32_t CLR; /**< General Purpose Register, offset: 0x4828 */ + __IO uint32_t TOG; /**< General Purpose Register, offset: 0x482C */ + } GPR_SHARED1; + struct { /* offset: 0x4830 */ + __IO uint32_t RW; /**< GPR access control, offset: 0x4830 */ + __IO uint32_t SET; /**< GPR access control, offset: 0x4834 */ + __IO uint32_t CLR; /**< GPR access control, offset: 0x4838 */ + __IO uint32_t TOG; /**< GPR access control, offset: 0x483C */ + } GPR_SHARED1_AUTHEN; + struct { /* offset: 0x4840 */ + __IO uint32_t RW; /**< General Purpose Register, offset: 0x4840 */ + __IO uint32_t SET; /**< General Purpose Register, offset: 0x4844 */ + __IO uint32_t CLR; /**< General Purpose Register, offset: 0x4848 */ + __IO uint32_t TOG; /**< General Purpose Register, offset: 0x484C */ + } GPR_SHARED2; + struct { /* offset: 0x4850 */ + __IO uint32_t RW; /**< GPR access control, offset: 0x4850 */ + __IO uint32_t SET; /**< GPR access control, offset: 0x4854 */ + __IO uint32_t CLR; /**< GPR access control, offset: 0x4858 */ + __IO uint32_t TOG; /**< GPR access control, offset: 0x485C */ + } GPR_SHARED2_AUTHEN; + struct { /* offset: 0x4860, array step: 0x20 */ + struct { /* offset: 0x4860 */ + uint32_t RW; /**< General Purpose Register, offset: 0x4860 */ + uint32_t SET; /**< General Purpose Register, offset: 0x4864 */ + uint32_t CLR; /**< General Purpose Register, offset: 0x4868 */ + uint32_t TOG; /**< General Purpose Register, offset: 0x486C */ + } GPR_SHARED; + struct { /* offset: 0x4870 */ + __IO uint32_t RW; /**< GPR access control, offset: 0x4870 */ + __IO uint32_t SET; /**< GPR access control, offset: 0x4874 */ + __IO uint32_t CLR; /**< GPR access control, offset: 0x4878 */ + __IO uint32_t TOG; /**< GPR access control, offset: 0x487C */ + } GPR_SHARED_AUTHEN; + } GPR_SHARED[5]; + uint8_t RESERVED_1[768]; + struct { /* offset: 0x4C00, array step: 0x20 */ + struct { /* offset: 0x4C00 */ + __IO uint32_t RW; /**< General puspose register, offset: 0x4C00 */ + __IO uint32_t SET; /**< General puspose register, offset: 0x4C04 */ + __IO uint32_t CLR; /**< General puspose register, offset: 0x4C08 */ + __IO uint32_t TOG; /**< General puspose register, offset: 0x4C0C */ + } GPR_PRIVATE; + struct { /* offset: 0x4C10 */ + __IO uint32_t RW; /**< GPR access control, offset: 0x4C10 */ + __IO uint32_t SET; /**< GPR access control, offset: 0x4C14 */ + __IO uint32_t CLR; /**< GPR access control, offset: 0x4C18 */ + __IO uint32_t TOG; /**< GPR access control, offset: 0x4C1C */ + } GPR_PRIVATE_AUTHEN; + } GPR_PRIVATE[8]; + uint8_t RESERVED_2[768]; + struct { /* offset: 0x5000, array step: 0x40 */ + __IO uint32_t DIRECT; /**< Clock source direct control, array offset: 0x5000, array step: 0x40 */ + __I uint32_t LPM_STATUS0; /**< Low power mode information transfer status, array offset: 0x5004, array step: 0x40 */ + __I uint32_t LPM_STATUS1; /**< Low power mode information transfer status, array offset: 0x5008, array step: 0x40 */ + uint8_t RESERVED_0[4]; + __IO uint32_t LPM0; /**< Clock source low power mode setting, array offset: 0x5010, array step: 0x40 */ + __IO uint32_t LPM1; /**< clock source low power mode setting, array offset: 0x5014, array step: 0x40 */ + uint8_t RESERVED_1[4]; + __I uint32_t LPM_CUR; /**< LPM setting of current CPU domain, array offset: 0x501C, array step: 0x40 */ + __I uint32_t STATUS0; /**< Clock source working status, array offset: 0x5020, array step: 0x40 */ + __I uint32_t STATUS1; /**< Clock source domain status, array offset: 0x5024, array step: 0x40 */ + uint8_t RESERVED_2[8]; + __IO uint32_t AUTHEN; /**< Clock Source access control, array offset: 0x5030, array step: 0x40 */ + uint8_t RESERVED_3[12]; + } OSCPLL[20]; + uint8_t RESERVED_3[11008]; + struct { /* offset: 0x8000, array step: 0x40 */ + __IO uint32_t DIRECT; /**< LPCG direct control, array offset: 0x8000, array step: 0x40 */ + __I uint32_t LPM_STATUS0; /**< Low power mode information transfer status, array offset: 0x8004, array step: 0x40 */ + __I uint32_t LPM_STATUS1; /**< Low power mode information transfer status, array offset: 0x8008, array step: 0x40 */ + uint8_t RESERVED_0[4]; + __IO uint32_t LPM0; /**< LPCG low power mode setting, array offset: 0x8010, array step: 0x40 */ + __IO uint32_t LPM1; /**< LPCG low power mode setting, array offset: 0x8014, array step: 0x40 */ + uint8_t RESERVED_1[4]; + __IO uint32_t LPM_CUR; /**< LPM setting of current CPU domain, array offset: 0x801C, array step: 0x40 */ + __I uint32_t STATUS0; /**< LPCG working status, array offset: 0x8020, array step: 0x40 */ + __I uint32_t STATUS1; /**< LPCG domain status, array offset: 0x8024, array step: 0x40 */ + uint8_t RESERVED_2[8]; + __IO uint32_t AUTHEN; /**< LPCG access control, array offset: 0x8030, array step: 0x40 */ + uint8_t RESERVED_3[12]; + } LPCG[127]; +} CCM_Type; + +/* ---------------------------------------------------------------------------- + -- CCM Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CCM_Register_Masks CCM Register Masks + * @{ + */ + +/*! @name CLOCK_ROOT - Clock Root Control Register */ +/*! @{ */ + +#define CCM_CLOCK_ROOT_DIV_MASK (0xFFU) +#define CCM_CLOCK_ROOT_DIV_SHIFT (0U) +/*! DIV - Clock division fraction. */ +#define CCM_CLOCK_ROOT_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_DIV_SHIFT)) & CCM_CLOCK_ROOT_DIV_MASK) + +#define CCM_CLOCK_ROOT_MUX_MASK (0x300U) +#define CCM_CLOCK_ROOT_MUX_SHIFT (8U) +/*! MUX - Clock multiplexer. + * 0b00..Select clock source 0 + * 0b01..Select clock source 1 + * 0b10..Select clock source 2 + * 0b11..Select clock source 3 + */ +#define CCM_CLOCK_ROOT_MUX(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_MUX_SHIFT)) & CCM_CLOCK_ROOT_MUX_MASK) + +#define CCM_CLOCK_ROOT_OFF_MASK (0x1000000U) +#define CCM_CLOCK_ROOT_OFF_SHIFT (24U) +/*! OFF - Shutdown clock root. + * 0b0..Clock is running. + * 0b1..Turn off clock. + */ +#define CCM_CLOCK_ROOT_OFF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_OFF_SHIFT)) & CCM_CLOCK_ROOT_OFF_MASK) +/*! @} */ + +/*! @name CLOCK_ROOT_STATUS0 - Clock root working status */ +/*! @{ */ + +#define CCM_CLOCK_ROOT_STATUS0_DIV_MASK (0xFFU) +#define CCM_CLOCK_ROOT_STATUS0_DIV_SHIFT (0U) +/*! DIV - Current clock root DIV setting */ +#define CCM_CLOCK_ROOT_STATUS0_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_STATUS0_DIV_SHIFT)) & CCM_CLOCK_ROOT_STATUS0_DIV_MASK) + +#define CCM_CLOCK_ROOT_STATUS0_MUX_MASK (0x300U) +#define CCM_CLOCK_ROOT_STATUS0_MUX_SHIFT (8U) +/*! MUX - Current clock root MUX setting */ +#define CCM_CLOCK_ROOT_STATUS0_MUX(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_STATUS0_MUX_SHIFT)) & CCM_CLOCK_ROOT_STATUS0_MUX_MASK) + +#define CCM_CLOCK_ROOT_STATUS0_OFF_MASK (0x1000000U) +#define CCM_CLOCK_ROOT_STATUS0_OFF_SHIFT (24U) +/*! OFF - Current clock root OFF setting + * 0b0..Clock is running. + * 0b1..Turn off clock. + */ +#define CCM_CLOCK_ROOT_STATUS0_OFF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_STATUS0_OFF_SHIFT)) & CCM_CLOCK_ROOT_STATUS0_OFF_MASK) + +#define CCM_CLOCK_ROOT_STATUS0_SLICE_BUSY_MASK (0x10000000U) +#define CCM_CLOCK_ROOT_STATUS0_SLICE_BUSY_SHIFT (28U) +/*! SLICE_BUSY - Indication for clock generation logic is applying new setting. + * 0b0..Clock generation logic is not busy. + * 0b1..Clock generation logic is applying new setting. + */ +#define CCM_CLOCK_ROOT_STATUS0_SLICE_BUSY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_STATUS0_SLICE_BUSY_SHIFT)) & CCM_CLOCK_ROOT_STATUS0_SLICE_BUSY_MASK) + +#define CCM_CLOCK_ROOT_STATUS0_CHANGING_MASK (0x80000000U) +#define CCM_CLOCK_ROOT_STATUS0_CHANGING_SHIFT (31U) +/*! CHANGING - Internal updating in clock root + * 0b0..Clock Status is not updating currently + * 0b1..Clock generation logic is updating currently + */ +#define CCM_CLOCK_ROOT_STATUS0_CHANGING(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_STATUS0_CHANGING_SHIFT)) & CCM_CLOCK_ROOT_STATUS0_CHANGING_MASK) +/*! @} */ + +/* The count of CCM_CLOCK_ROOT_STATUS0 */ +#define CCM_CLOCK_ROOT_STATUS0_COUNT (95U) + +/*! @name CLOCK_ROOT - Clock root access control */ +/*! @{ */ + +#define CCM_CLOCK_ROOT_TZ_USER_MASK (0x100U) +#define CCM_CLOCK_ROOT_TZ_USER_SHIFT (8U) +/*! TZ_USER - User access permission + * 0b0..Clock Root settings cannot be changed in user mode. + * 0b1..Clock Root settings can be changed in user mode. + */ +#define CCM_CLOCK_ROOT_TZ_USER(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_TZ_USER_SHIFT)) & CCM_CLOCK_ROOT_TZ_USER_MASK) + +#define CCM_CLOCK_ROOT_TZ_NS_MASK (0x200U) +#define CCM_CLOCK_ROOT_TZ_NS_SHIFT (9U) +/*! TZ_NS - Non-secure access permission + * 0b0..Cannot be changed in Non-secure mode. + * 0b1..Can be changed in Non-secure mode. + */ +#define CCM_CLOCK_ROOT_TZ_NS(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_TZ_NS_SHIFT)) & CCM_CLOCK_ROOT_TZ_NS_MASK) + +#define CCM_CLOCK_ROOT_LOCK_TZ_MASK (0x800U) +#define CCM_CLOCK_ROOT_LOCK_TZ_SHIFT (11U) +/*! LOCK_TZ - Lock TrustZone settings + * 0b0..TrustZone setting is not locked. + * 0b1..TrustZone setting is locked. + */ +#define CCM_CLOCK_ROOT_LOCK_TZ(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_LOCK_TZ_SHIFT)) & CCM_CLOCK_ROOT_LOCK_TZ_MASK) + +#define CCM_CLOCK_ROOT_LOCK_LIST_MASK (0x8000U) +#define CCM_CLOCK_ROOT_LOCK_LIST_SHIFT (15U) +/*! LOCK_LIST - Lock white list + * 0b0..Whitelist is not locked. + * 0b1..Whitelist is locked. + */ +#define CCM_CLOCK_ROOT_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_LOCK_LIST_SHIFT)) & CCM_CLOCK_ROOT_LOCK_LIST_MASK) + +#define CCM_CLOCK_ROOT_WHITE_LIST_MASK (0xFFFF0000U) +#define CCM_CLOCK_ROOT_WHITE_LIST_SHIFT (16U) +/*! WHITE_LIST - Whitelist settings */ +#define CCM_CLOCK_ROOT_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_WHITE_LIST_SHIFT)) & CCM_CLOCK_ROOT_WHITE_LIST_MASK) +/*! @} */ + +/*! @name GPR_SHARED0_AUTHEN - GPR access control */ +/*! @{ */ + +#define CCM_GPR_SHARED0_AUTHEN_TZ_USER_MASK (0x100U) +#define CCM_GPR_SHARED0_AUTHEN_TZ_USER_SHIFT (8U) +/*! TZ_USER - User access permission + * 0b0..Registers of shared GPR slice cannot be changed in user mode. + * 0b1..Registers of shared GPR slice can be changed in user mode. + */ +#define CCM_GPR_SHARED0_AUTHEN_TZ_USER(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED0_AUTHEN_TZ_USER_SHIFT)) & CCM_GPR_SHARED0_AUTHEN_TZ_USER_MASK) + +#define CCM_GPR_SHARED0_AUTHEN_TZ_NS_MASK (0x200U) +#define CCM_GPR_SHARED0_AUTHEN_TZ_NS_SHIFT (9U) +/*! TZ_NS - Non-secure access permission + * 0b0..Cannot be changed in Non-secure mode. + * 0b1..Can be changed in Non-secure mode. + */ +#define CCM_GPR_SHARED0_AUTHEN_TZ_NS(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED0_AUTHEN_TZ_NS_SHIFT)) & CCM_GPR_SHARED0_AUTHEN_TZ_NS_MASK) + +#define CCM_GPR_SHARED0_AUTHEN_LOCK_TZ_MASK (0x800U) +#define CCM_GPR_SHARED0_AUTHEN_LOCK_TZ_SHIFT (11U) +/*! LOCK_TZ - Lock TrustZone settings + * 0b0..TrustZone settings is not locked. + * 0b1..TrustZone settings is locked. + */ +#define CCM_GPR_SHARED0_AUTHEN_LOCK_TZ(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED0_AUTHEN_LOCK_TZ_SHIFT)) & CCM_GPR_SHARED0_AUTHEN_LOCK_TZ_MASK) + +#define CCM_GPR_SHARED0_AUTHEN_LOCK_LIST_MASK (0x8000U) +#define CCM_GPR_SHARED0_AUTHEN_LOCK_LIST_SHIFT (15U) +/*! LOCK_LIST - Lock white list + * 0b0..Whitelist is not locked. + * 0b1..Whitelist is locked. + */ +#define CCM_GPR_SHARED0_AUTHEN_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED0_AUTHEN_LOCK_LIST_SHIFT)) & CCM_GPR_SHARED0_AUTHEN_LOCK_LIST_MASK) + +#define CCM_GPR_SHARED0_AUTHEN_WHITE_LIST_MASK (0xFFFF0000U) +#define CCM_GPR_SHARED0_AUTHEN_WHITE_LIST_SHIFT (16U) +/*! WHITE_LIST - Whitelist settings */ +#define CCM_GPR_SHARED0_AUTHEN_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED0_AUTHEN_WHITE_LIST_SHIFT)) & CCM_GPR_SHARED0_AUTHEN_WHITE_LIST_MASK) +/*! @} */ + +/*! @name GPR_SHARED1 - General Purpose Register */ +/*! @{ */ + +#define CCM_GPR_SHARED1_CA55_CLOCK_SELECT_MASK (0x1U) +#define CCM_GPR_SHARED1_CA55_CLOCK_SELECT_SHIFT (0U) +/*! CA55_CLOCK_SELECT - Clock select signal between ccm clock root and ARM PLL clock + * 0b0..Clkroot_arm_a55 is used. + * 0b1..The clock output of ARM PLL is selected. + */ +#define CCM_GPR_SHARED1_CA55_CLOCK_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED1_CA55_CLOCK_SELECT_SHIFT)) & CCM_GPR_SHARED1_CA55_CLOCK_SELECT_MASK) +/*! @} */ + +/*! @name GPR_SHARED1_AUTHEN - GPR access control */ +/*! @{ */ + +#define CCM_GPR_SHARED1_AUTHEN_TZ_USER_MASK (0x100U) +#define CCM_GPR_SHARED1_AUTHEN_TZ_USER_SHIFT (8U) +/*! TZ_USER - User access permission + * 0b0..Registers of shared GPR slice cannot be changed in user mode. + * 0b1..Registers of shared GPR slice can be changed in user mode. + */ +#define CCM_GPR_SHARED1_AUTHEN_TZ_USER(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED1_AUTHEN_TZ_USER_SHIFT)) & CCM_GPR_SHARED1_AUTHEN_TZ_USER_MASK) + +#define CCM_GPR_SHARED1_AUTHEN_TZ_NS_MASK (0x200U) +#define CCM_GPR_SHARED1_AUTHEN_TZ_NS_SHIFT (9U) +/*! TZ_NS - Non-secure access permission + * 0b0..Cannot be changed in Non-secure mode. + * 0b1..Can be changed in Non-secure mode. + */ +#define CCM_GPR_SHARED1_AUTHEN_TZ_NS(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED1_AUTHEN_TZ_NS_SHIFT)) & CCM_GPR_SHARED1_AUTHEN_TZ_NS_MASK) + +#define CCM_GPR_SHARED1_AUTHEN_LOCK_TZ_MASK (0x800U) +#define CCM_GPR_SHARED1_AUTHEN_LOCK_TZ_SHIFT (11U) +/*! LOCK_TZ - Lock TrustZone settings + * 0b0..TrustZone settings is not locked. + * 0b1..TrustZone settings is locked. + */ +#define CCM_GPR_SHARED1_AUTHEN_LOCK_TZ(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED1_AUTHEN_LOCK_TZ_SHIFT)) & CCM_GPR_SHARED1_AUTHEN_LOCK_TZ_MASK) + +#define CCM_GPR_SHARED1_AUTHEN_LOCK_LIST_MASK (0x8000U) +#define CCM_GPR_SHARED1_AUTHEN_LOCK_LIST_SHIFT (15U) +/*! LOCK_LIST - Lock white list + * 0b0..Whitelist is not locked. + * 0b1..Whitelist is locked. + */ +#define CCM_GPR_SHARED1_AUTHEN_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED1_AUTHEN_LOCK_LIST_SHIFT)) & CCM_GPR_SHARED1_AUTHEN_LOCK_LIST_MASK) + +#define CCM_GPR_SHARED1_AUTHEN_WHITE_LIST_MASK (0xFFFF0000U) +#define CCM_GPR_SHARED1_AUTHEN_WHITE_LIST_SHIFT (16U) +/*! WHITE_LIST - Whitelist settings */ +#define CCM_GPR_SHARED1_AUTHEN_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED1_AUTHEN_WHITE_LIST_SHIFT)) & CCM_GPR_SHARED1_AUTHEN_WHITE_LIST_MASK) +/*! @} */ + +/*! @name GPR_SHARED2 - General Purpose Register */ +/*! @{ */ + +#define CCM_GPR_SHARED2_DRAM_PLL_BYPASS_MASK (0x1U) +#define CCM_GPR_SHARED2_DRAM_PLL_BYPASS_SHIFT (0U) +/*! DRAM_PLL_BYPASS - Clock select signal between ccm clock root and DRAM PLL clock + * 0b0..The clock output of DRAM PLL is selected. + * 0b1..Dram_alt_clk_root is selected. + */ +#define CCM_GPR_SHARED2_DRAM_PLL_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED2_DRAM_PLL_BYPASS_SHIFT)) & CCM_GPR_SHARED2_DRAM_PLL_BYPASS_MASK) +/*! @} */ + +/*! @name GPR_SHARED2_AUTHEN - GPR access control */ +/*! @{ */ + +#define CCM_GPR_SHARED2_AUTHEN_TZ_USER_MASK (0x100U) +#define CCM_GPR_SHARED2_AUTHEN_TZ_USER_SHIFT (8U) +/*! TZ_USER - User access permission + * 0b0..Registers of shared GPR slice cannot be changed in user mode. + * 0b1..Registers of shared GPR slice can be changed in user mode. + */ +#define CCM_GPR_SHARED2_AUTHEN_TZ_USER(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED2_AUTHEN_TZ_USER_SHIFT)) & CCM_GPR_SHARED2_AUTHEN_TZ_USER_MASK) + +#define CCM_GPR_SHARED2_AUTHEN_TZ_NS_MASK (0x200U) +#define CCM_GPR_SHARED2_AUTHEN_TZ_NS_SHIFT (9U) +/*! TZ_NS - Non-secure access permission + * 0b0..Cannot be changed in Non-secure mode. + * 0b1..Can be changed in Non-secure mode. + */ +#define CCM_GPR_SHARED2_AUTHEN_TZ_NS(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED2_AUTHEN_TZ_NS_SHIFT)) & CCM_GPR_SHARED2_AUTHEN_TZ_NS_MASK) + +#define CCM_GPR_SHARED2_AUTHEN_LOCK_TZ_MASK (0x800U) +#define CCM_GPR_SHARED2_AUTHEN_LOCK_TZ_SHIFT (11U) +/*! LOCK_TZ - Lock TrustZone settings + * 0b0..TrustZone settings is not locked. + * 0b1..TrustZone settings is locked. + */ +#define CCM_GPR_SHARED2_AUTHEN_LOCK_TZ(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED2_AUTHEN_LOCK_TZ_SHIFT)) & CCM_GPR_SHARED2_AUTHEN_LOCK_TZ_MASK) + +#define CCM_GPR_SHARED2_AUTHEN_LOCK_LIST_MASK (0x8000U) +#define CCM_GPR_SHARED2_AUTHEN_LOCK_LIST_SHIFT (15U) +/*! LOCK_LIST - Lock white list + * 0b0..Whitelist is not locked. + * 0b1..Whitelist is locked. + */ +#define CCM_GPR_SHARED2_AUTHEN_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED2_AUTHEN_LOCK_LIST_SHIFT)) & CCM_GPR_SHARED2_AUTHEN_LOCK_LIST_MASK) + +#define CCM_GPR_SHARED2_AUTHEN_WHITE_LIST_MASK (0xFFFF0000U) +#define CCM_GPR_SHARED2_AUTHEN_WHITE_LIST_SHIFT (16U) +/*! WHITE_LIST - Whitelist settings */ +#define CCM_GPR_SHARED2_AUTHEN_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED2_AUTHEN_WHITE_LIST_SHIFT)) & CCM_GPR_SHARED2_AUTHEN_WHITE_LIST_MASK) +/*! @} */ + +/*! @name GPR_SHARED - GPR access control */ +/*! @{ */ + +#define CCM_GPR_SHARED_TZ_USER_MASK (0x100U) +#define CCM_GPR_SHARED_TZ_USER_SHIFT (8U) +/*! TZ_USER - User access permission + * 0b0..Registers of shared GPR slice cannot be changed in user mode. + * 0b1..Registers of shared GPR slice can be changed in user mode. + */ +#define CCM_GPR_SHARED_TZ_USER(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED_TZ_USER_SHIFT)) & CCM_GPR_SHARED_TZ_USER_MASK) + +#define CCM_GPR_SHARED_TZ_NS_MASK (0x200U) +#define CCM_GPR_SHARED_TZ_NS_SHIFT (9U) +/*! TZ_NS - Non-secure access permission + * 0b0..Cannot be changed in Non-secure mode. + * 0b1..Can be changed in Non-secure mode. + */ +#define CCM_GPR_SHARED_TZ_NS(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED_TZ_NS_SHIFT)) & CCM_GPR_SHARED_TZ_NS_MASK) + +#define CCM_GPR_SHARED_LOCK_TZ_MASK (0x800U) +#define CCM_GPR_SHARED_LOCK_TZ_SHIFT (11U) +/*! LOCK_TZ - Lock TrustZone settings + * 0b0..TrustZone settings is not locked. + * 0b1..TrustZone settings is locked. + */ +#define CCM_GPR_SHARED_LOCK_TZ(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED_LOCK_TZ_SHIFT)) & CCM_GPR_SHARED_LOCK_TZ_MASK) + +#define CCM_GPR_SHARED_LOCK_LIST_MASK (0x8000U) +#define CCM_GPR_SHARED_LOCK_LIST_SHIFT (15U) +/*! LOCK_LIST - Lock white list + * 0b0..Whitelist is not locked. + * 0b1..Whitelist is locked. + */ +#define CCM_GPR_SHARED_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED_LOCK_LIST_SHIFT)) & CCM_GPR_SHARED_LOCK_LIST_MASK) + +#define CCM_GPR_SHARED_WHITE_LIST_MASK (0xFFFF0000U) +#define CCM_GPR_SHARED_WHITE_LIST_SHIFT (16U) +/*! WHITE_LIST - Whitelist settings */ +#define CCM_GPR_SHARED_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED_WHITE_LIST_SHIFT)) & CCM_GPR_SHARED_WHITE_LIST_MASK) +/*! @} */ + +/*! @name GPR_PRIVATE - General puspose register */ +/*! @{ */ + +#define CCM_GPR_PRIVATE_GPR_MASK (0xFFFFFFFFU) +#define CCM_GPR_PRIVATE_GPR_SHIFT (0U) +/*! GPR - GP register */ +#define CCM_GPR_PRIVATE_GPR(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE_GPR_SHIFT)) & CCM_GPR_PRIVATE_GPR_MASK) +/*! @} */ + +/*! @name GPR_PRIVATE - GPR access control */ +/*! @{ */ + +#define CCM_GPR_PRIVATE_TZ_USER_MASK (0x100U) +#define CCM_GPR_PRIVATE_TZ_USER_SHIFT (8U) +/*! TZ_USER - User access permission + * 0b0..Registers of privat GPR cannot be changed in user mode. + * 0b1..Registers of private GPR can be changed in user mode. + */ +#define CCM_GPR_PRIVATE_TZ_USER(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE_TZ_USER_SHIFT)) & CCM_GPR_PRIVATE_TZ_USER_MASK) + +#define CCM_GPR_PRIVATE_TZ_NS_MASK (0x200U) +#define CCM_GPR_PRIVATE_TZ_NS_SHIFT (9U) +/*! TZ_NS - Non-secure access permission + * 0b0..Cannot be changed in Non-secure mode. + * 0b1..Can be changed in Non-secure mode. + */ +#define CCM_GPR_PRIVATE_TZ_NS(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE_TZ_NS_SHIFT)) & CCM_GPR_PRIVATE_TZ_NS_MASK) + +#define CCM_GPR_PRIVATE_LOCK_TZ_MASK (0x800U) +#define CCM_GPR_PRIVATE_LOCK_TZ_SHIFT (11U) +/*! LOCK_TZ - Lock TrustZone settings + * 0b0..TrustZone settings is not locked. + * 0b1..TrustZone settings is locked. + */ +#define CCM_GPR_PRIVATE_LOCK_TZ(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE_LOCK_TZ_SHIFT)) & CCM_GPR_PRIVATE_LOCK_TZ_MASK) + +#define CCM_GPR_PRIVATE_LOCK_LIST_MASK (0x8000U) +#define CCM_GPR_PRIVATE_LOCK_LIST_SHIFT (15U) +/*! LOCK_LIST - Lock white list + * 0b0..Whitelist is not locked. + * 0b1..Whitelist is locked. + */ +#define CCM_GPR_PRIVATE_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE_LOCK_LIST_SHIFT)) & CCM_GPR_PRIVATE_LOCK_LIST_MASK) + +#define CCM_GPR_PRIVATE_WHITE_LIST_MASK (0xFFFF0000U) +#define CCM_GPR_PRIVATE_WHITE_LIST_SHIFT (16U) +/*! WHITE_LIST - Whitelist settings */ +#define CCM_GPR_PRIVATE_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE_WHITE_LIST_SHIFT)) & CCM_GPR_PRIVATE_WHITE_LIST_MASK) +/*! @} */ + +/*! @name OSCPLL_DIRECT - Clock source direct control */ +/*! @{ */ + +#define CCM_OSCPLL_DIRECT_ON_MASK (0x1U) +#define CCM_OSCPLL_DIRECT_ON_SHIFT (0U) +/*! ON - Turn on clock source + * 0b0..Clock source is OFF. + * 0b1..Clock source is ON. + */ +#define CCM_OSCPLL_DIRECT_ON(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_DIRECT_ON_SHIFT)) & CCM_OSCPLL_DIRECT_ON_MASK) +/*! @} */ + +/* The count of CCM_OSCPLL_DIRECT */ +#define CCM_OSCPLL_DIRECT_COUNT (20U) + +/*! @name OSCPLL_LPM_STATUS0 - Low power mode information transfer status */ +/*! @{ */ + +#define CCM_OSCPLL_LPM_STATUS0_CPU_MODE_DOMAIN0_MASK (0x3U) +#define CCM_OSCPLL_LPM_STATUS0_CPU_MODE_DOMAIN0_SHIFT (0U) +/*! CPU_MODE_DOMAIN0 - Current mode of CPU domain 0 + * 0b00..CPU is in RUN mode + * 0b01..CPU is in WAIT mode + * 0b10..CPU is in STOP mode + * 0b11..CPU is in SUSPEND mode + */ +#define CCM_OSCPLL_LPM_STATUS0_CPU_MODE_DOMAIN0(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_LPM_STATUS0_CPU_MODE_DOMAIN0_SHIFT)) & CCM_OSCPLL_LPM_STATUS0_CPU_MODE_DOMAIN0_MASK) + +#define CCM_OSCPLL_LPM_STATUS0_TRANS_REQ_DOMAIN0_MASK (0x4U) +#define CCM_OSCPLL_LPM_STATUS0_TRANS_REQ_DOMAIN0_SHIFT (2U) +/*! TRANS_REQ_DOMAIN0 - GPC request CCM to enable or disable OSCPLL. This signal will turn to low once CCM complete response to GPC. */ +#define CCM_OSCPLL_LPM_STATUS0_TRANS_REQ_DOMAIN0(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_LPM_STATUS0_TRANS_REQ_DOMAIN0_SHIFT)) & CCM_OSCPLL_LPM_STATUS0_TRANS_REQ_DOMAIN0_MASK) + +#define CCM_OSCPLL_LPM_STATUS0_CPU_MODE_DOMAIN1_MASK (0x30U) +#define CCM_OSCPLL_LPM_STATUS0_CPU_MODE_DOMAIN1_SHIFT (4U) +/*! CPU_MODE_DOMAIN1 - Current mode of CPU domain 1 + * 0b00..CPU is in RUN mode + * 0b01..CPU is in WAIT mode + * 0b10..CPU is in STOP mode + * 0b11..CPU is in SUSPEND mode + */ +#define CCM_OSCPLL_LPM_STATUS0_CPU_MODE_DOMAIN1(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_LPM_STATUS0_CPU_MODE_DOMAIN1_SHIFT)) & CCM_OSCPLL_LPM_STATUS0_CPU_MODE_DOMAIN1_MASK) + +#define CCM_OSCPLL_LPM_STATUS0_TRANS_REQ_DOMAIN1_MASK (0x40U) +#define CCM_OSCPLL_LPM_STATUS0_TRANS_REQ_DOMAIN1_SHIFT (6U) +/*! TRANS_REQ_DOMAIN1 - GPC request CCM to enable or disable OSCPLL. This signal will turn to low once CCM complete response to GPC. */ +#define CCM_OSCPLL_LPM_STATUS0_TRANS_REQ_DOMAIN1(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_LPM_STATUS0_TRANS_REQ_DOMAIN1_SHIFT)) & CCM_OSCPLL_LPM_STATUS0_TRANS_REQ_DOMAIN1_MASK) + +#define CCM_OSCPLL_LPM_STATUS0_CPU_MODE_DOMAIN2_MASK (0x300U) +#define CCM_OSCPLL_LPM_STATUS0_CPU_MODE_DOMAIN2_SHIFT (8U) +/*! CPU_MODE_DOMAIN2 - Current mode of CPU domain 2 + * 0b00..CPU is in RUN mode + * 0b01..CPU is in WAIT mode + * 0b10..CPU is in STOP mode + * 0b11..CPU is in SUSPEND mode + */ +#define CCM_OSCPLL_LPM_STATUS0_CPU_MODE_DOMAIN2(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_LPM_STATUS0_CPU_MODE_DOMAIN2_SHIFT)) & CCM_OSCPLL_LPM_STATUS0_CPU_MODE_DOMAIN2_MASK) + +#define CCM_OSCPLL_LPM_STATUS0_TRANS_REQ_DOMAIN2_MASK (0x400U) +#define CCM_OSCPLL_LPM_STATUS0_TRANS_REQ_DOMAIN2_SHIFT (10U) +/*! TRANS_REQ_DOMAIN2 - GPC request CCM to enable or disable OSCPLL. This signal will turn to low once CCM complete response to GPC. */ +#define CCM_OSCPLL_LPM_STATUS0_TRANS_REQ_DOMAIN2(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_LPM_STATUS0_TRANS_REQ_DOMAIN2_SHIFT)) & CCM_OSCPLL_LPM_STATUS0_TRANS_REQ_DOMAIN2_MASK) + +#define CCM_OSCPLL_LPM_STATUS0_CPU_MODE_DOMAIN3_MASK (0x3000U) +#define CCM_OSCPLL_LPM_STATUS0_CPU_MODE_DOMAIN3_SHIFT (12U) +/*! CPU_MODE_DOMAIN3 - Current mode of CPU domain 3 + * 0b00..CPU is in RUN mode + * 0b01..CPU is in WAIT mode + * 0b10..CPU is in STOP mode + * 0b11..CPU is in SUSPEND mode + */ +#define CCM_OSCPLL_LPM_STATUS0_CPU_MODE_DOMAIN3(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_LPM_STATUS0_CPU_MODE_DOMAIN3_SHIFT)) & CCM_OSCPLL_LPM_STATUS0_CPU_MODE_DOMAIN3_MASK) + +#define CCM_OSCPLL_LPM_STATUS0_TRANS_REQ_DOMAIN3_MASK (0x4000U) +#define CCM_OSCPLL_LPM_STATUS0_TRANS_REQ_DOMAIN3_SHIFT (14U) +/*! TRANS_REQ_DOMAIN3 - GPC request CCM to enable or disable OSCPLL. This signal will turn to low once CCM complete response to GPC. */ +#define CCM_OSCPLL_LPM_STATUS0_TRANS_REQ_DOMAIN3(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_LPM_STATUS0_TRANS_REQ_DOMAIN3_SHIFT)) & CCM_OSCPLL_LPM_STATUS0_TRANS_REQ_DOMAIN3_MASK) + +#define CCM_OSCPLL_LPM_STATUS0_CPU_MODE_DOMAIN4_MASK (0x30000U) +#define CCM_OSCPLL_LPM_STATUS0_CPU_MODE_DOMAIN4_SHIFT (16U) +/*! CPU_MODE_DOMAIN4 - Current mode of CPU domain 4 + * 0b00..CPU is in RUN mode + * 0b01..CPU is in WAIT mode + * 0b10..CPU is in STOP mode + * 0b11..CPU is in SUSPEND mode + */ +#define CCM_OSCPLL_LPM_STATUS0_CPU_MODE_DOMAIN4(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_LPM_STATUS0_CPU_MODE_DOMAIN4_SHIFT)) & CCM_OSCPLL_LPM_STATUS0_CPU_MODE_DOMAIN4_MASK) + +#define CCM_OSCPLL_LPM_STATUS0_TRANS_REQ_DOMAIN4_MASK (0x40000U) +#define CCM_OSCPLL_LPM_STATUS0_TRANS_REQ_DOMAIN4_SHIFT (18U) +/*! TRANS_REQ_DOMAIN4 - GPC request CCM to enable or disable OSCPLL. This signal will turn to low once CCM complete response to GPC. */ +#define CCM_OSCPLL_LPM_STATUS0_TRANS_REQ_DOMAIN4(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_LPM_STATUS0_TRANS_REQ_DOMAIN4_SHIFT)) & CCM_OSCPLL_LPM_STATUS0_TRANS_REQ_DOMAIN4_MASK) + +#define CCM_OSCPLL_LPM_STATUS0_CPU_MODE_DOMAIN5_MASK (0x300000U) +#define CCM_OSCPLL_LPM_STATUS0_CPU_MODE_DOMAIN5_SHIFT (20U) +/*! CPU_MODE_DOMAIN5 - Current mode of CPU domain 5 + * 0b00..CPU is in RUN mode + * 0b01..CPU is in WAIT mode + * 0b10..CPU is in STOP mode + * 0b11..CPU is in SUSPEND mode + */ +#define CCM_OSCPLL_LPM_STATUS0_CPU_MODE_DOMAIN5(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_LPM_STATUS0_CPU_MODE_DOMAIN5_SHIFT)) & CCM_OSCPLL_LPM_STATUS0_CPU_MODE_DOMAIN5_MASK) + +#define CCM_OSCPLL_LPM_STATUS0_TRANS_REQ_DOMAIN5_MASK (0x400000U) +#define CCM_OSCPLL_LPM_STATUS0_TRANS_REQ_DOMAIN5_SHIFT (22U) +/*! TRANS_REQ_DOMAIN5 - GPC request CCM to enable or disable OSCPLL. This signal will turn to low once CCM complete response to GPC. */ +#define CCM_OSCPLL_LPM_STATUS0_TRANS_REQ_DOMAIN5(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_LPM_STATUS0_TRANS_REQ_DOMAIN5_SHIFT)) & CCM_OSCPLL_LPM_STATUS0_TRANS_REQ_DOMAIN5_MASK) + +#define CCM_OSCPLL_LPM_STATUS0_CPU_MODE_DOMAIN6_MASK (0x3000000U) +#define CCM_OSCPLL_LPM_STATUS0_CPU_MODE_DOMAIN6_SHIFT (24U) +/*! CPU_MODE_DOMAIN6 - Current mode of CPU domain 6 + * 0b00..CPU is in RUN mode + * 0b01..CPU is in WAIT mode + * 0b10..CPU is in STOP mode + * 0b11..CPU is in SUSPEND mode + */ +#define CCM_OSCPLL_LPM_STATUS0_CPU_MODE_DOMAIN6(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_LPM_STATUS0_CPU_MODE_DOMAIN6_SHIFT)) & CCM_OSCPLL_LPM_STATUS0_CPU_MODE_DOMAIN6_MASK) + +#define CCM_OSCPLL_LPM_STATUS0_TRANS_REQ_DOMAIN6_MASK (0x4000000U) +#define CCM_OSCPLL_LPM_STATUS0_TRANS_REQ_DOMAIN6_SHIFT (26U) +/*! TRANS_REQ_DOMAIN6 - GPC request CCM to enable or disable OSCPLL. This signal will turn to low once CCM complete response to GPC. */ +#define CCM_OSCPLL_LPM_STATUS0_TRANS_REQ_DOMAIN6(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_LPM_STATUS0_TRANS_REQ_DOMAIN6_SHIFT)) & CCM_OSCPLL_LPM_STATUS0_TRANS_REQ_DOMAIN6_MASK) + +#define CCM_OSCPLL_LPM_STATUS0_CPU_MODE_DOMAIN7_MASK (0x30000000U) +#define CCM_OSCPLL_LPM_STATUS0_CPU_MODE_DOMAIN7_SHIFT (28U) +/*! CPU_MODE_DOMAIN7 - Current mode of CPU domain 7 + * 0b00..CPU is in RUN mode + * 0b01..CPU is in WAIT mode + * 0b10..CPU is in STOP mode + * 0b11..CPU is in SUSPEND mode + */ +#define CCM_OSCPLL_LPM_STATUS0_CPU_MODE_DOMAIN7(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_LPM_STATUS0_CPU_MODE_DOMAIN7_SHIFT)) & CCM_OSCPLL_LPM_STATUS0_CPU_MODE_DOMAIN7_MASK) + +#define CCM_OSCPLL_LPM_STATUS0_TRANS_REQ_DOMAIN7_MASK (0x40000000U) +#define CCM_OSCPLL_LPM_STATUS0_TRANS_REQ_DOMAIN7_SHIFT (30U) +/*! TRANS_REQ_DOMAIN7 - GPC request CCM to enable or disable OSCPLL. This signal will turn to low once CCM complete response to GPC. */ +#define CCM_OSCPLL_LPM_STATUS0_TRANS_REQ_DOMAIN7(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_LPM_STATUS0_TRANS_REQ_DOMAIN7_SHIFT)) & CCM_OSCPLL_LPM_STATUS0_TRANS_REQ_DOMAIN7_MASK) +/*! @} */ + +/* The count of CCM_OSCPLL_LPM_STATUS0 */ +#define CCM_OSCPLL_LPM_STATUS0_COUNT (20U) + +/*! @name OSCPLL_LPM_STATUS1 - Low power mode information transfer status */ +/*! @{ */ + +#define CCM_OSCPLL_LPM_STATUS1_CPU_MODE_DOMAIN8_MASK (0x3U) +#define CCM_OSCPLL_LPM_STATUS1_CPU_MODE_DOMAIN8_SHIFT (0U) +/*! CPU_MODE_DOMAIN8 - Current mode of CPU domain 8 + * 0b00..CPU is in RUN mode + * 0b01..CPU is in WAIT mode + * 0b10..CPU is in STOP mode + * 0b11..CPU is in SUSPEND mode + */ +#define CCM_OSCPLL_LPM_STATUS1_CPU_MODE_DOMAIN8(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_LPM_STATUS1_CPU_MODE_DOMAIN8_SHIFT)) & CCM_OSCPLL_LPM_STATUS1_CPU_MODE_DOMAIN8_MASK) + +#define CCM_OSCPLL_LPM_STATUS1_TRANS_REQ_DOMAIN8_MASK (0x4U) +#define CCM_OSCPLL_LPM_STATUS1_TRANS_REQ_DOMAIN8_SHIFT (2U) +/*! TRANS_REQ_DOMAIN8 - GPC request CCM to enable or disable OSCPLL. This signal will turn to low once CCM complete response to GPC. */ +#define CCM_OSCPLL_LPM_STATUS1_TRANS_REQ_DOMAIN8(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_LPM_STATUS1_TRANS_REQ_DOMAIN8_SHIFT)) & CCM_OSCPLL_LPM_STATUS1_TRANS_REQ_DOMAIN8_MASK) + +#define CCM_OSCPLL_LPM_STATUS1_CPU_MODE_DOMAIN9_MASK (0x30U) +#define CCM_OSCPLL_LPM_STATUS1_CPU_MODE_DOMAIN9_SHIFT (4U) +/*! CPU_MODE_DOMAIN9 - Current mode of CPU domain 9 + * 0b00..CPU is in RUN mode + * 0b01..CPU is in WAIT mode + * 0b10..CPU is in STOP mode + * 0b11..CPU is in SUSPEND mode + */ +#define CCM_OSCPLL_LPM_STATUS1_CPU_MODE_DOMAIN9(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_LPM_STATUS1_CPU_MODE_DOMAIN9_SHIFT)) & CCM_OSCPLL_LPM_STATUS1_CPU_MODE_DOMAIN9_MASK) + +#define CCM_OSCPLL_LPM_STATUS1_TRANS_REQ_DOMAIN9_MASK (0x40U) +#define CCM_OSCPLL_LPM_STATUS1_TRANS_REQ_DOMAIN9_SHIFT (6U) +/*! TRANS_REQ_DOMAIN9 - GPC request CCM to enable or disable OSCPLL. This signal will turn to low once CCM complete response to GPC. */ +#define CCM_OSCPLL_LPM_STATUS1_TRANS_REQ_DOMAIN9(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_LPM_STATUS1_TRANS_REQ_DOMAIN9_SHIFT)) & CCM_OSCPLL_LPM_STATUS1_TRANS_REQ_DOMAIN9_MASK) + +#define CCM_OSCPLL_LPM_STATUS1_CPU_MODE_DOMAIN10_MASK (0x300U) +#define CCM_OSCPLL_LPM_STATUS1_CPU_MODE_DOMAIN10_SHIFT (8U) +/*! CPU_MODE_DOMAIN10 - Current mode of CPU domain 10 + * 0b00..CPU is in RUN mode + * 0b01..CPU is in WAIT mode + * 0b10..CPU is in STOP mode + * 0b11..CPU is in SUSPEND mode + */ +#define CCM_OSCPLL_LPM_STATUS1_CPU_MODE_DOMAIN10(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_LPM_STATUS1_CPU_MODE_DOMAIN10_SHIFT)) & CCM_OSCPLL_LPM_STATUS1_CPU_MODE_DOMAIN10_MASK) + +#define CCM_OSCPLL_LPM_STATUS1_TRANS_REQ_DOMAIN10_MASK (0x400U) +#define CCM_OSCPLL_LPM_STATUS1_TRANS_REQ_DOMAIN10_SHIFT (10U) +/*! TRANS_REQ_DOMAIN10 - GPC request CCM to enable or disable OSCPLL. This signal will turn to low once CCM complete response to GPC. */ +#define CCM_OSCPLL_LPM_STATUS1_TRANS_REQ_DOMAIN10(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_LPM_STATUS1_TRANS_REQ_DOMAIN10_SHIFT)) & CCM_OSCPLL_LPM_STATUS1_TRANS_REQ_DOMAIN10_MASK) + +#define CCM_OSCPLL_LPM_STATUS1_CPU_MODE_DOMAIN11_MASK (0x3000U) +#define CCM_OSCPLL_LPM_STATUS1_CPU_MODE_DOMAIN11_SHIFT (12U) +/*! CPU_MODE_DOMAIN11 - Current mode of CPU domain 11 + * 0b00..CPU is in RUN mode + * 0b01..CPU is in WAIT mode + * 0b10..CPU is in STOP mode + * 0b11..CPU is in SUSPEND mode + */ +#define CCM_OSCPLL_LPM_STATUS1_CPU_MODE_DOMAIN11(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_LPM_STATUS1_CPU_MODE_DOMAIN11_SHIFT)) & CCM_OSCPLL_LPM_STATUS1_CPU_MODE_DOMAIN11_MASK) + +#define CCM_OSCPLL_LPM_STATUS1_TRANS_REQ_DOMAIN11_MASK (0x4000U) +#define CCM_OSCPLL_LPM_STATUS1_TRANS_REQ_DOMAIN11_SHIFT (14U) +/*! TRANS_REQ_DOMAIN11 - GPC request CCM to enable or disable OSCPLL. This signal will turn to low once CCM complete response to GPC. */ +#define CCM_OSCPLL_LPM_STATUS1_TRANS_REQ_DOMAIN11(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_LPM_STATUS1_TRANS_REQ_DOMAIN11_SHIFT)) & CCM_OSCPLL_LPM_STATUS1_TRANS_REQ_DOMAIN11_MASK) + +#define CCM_OSCPLL_LPM_STATUS1_CPU_MODE_DOMAIN12_MASK (0x30000U) +#define CCM_OSCPLL_LPM_STATUS1_CPU_MODE_DOMAIN12_SHIFT (16U) +/*! CPU_MODE_DOMAIN12 - Current mode of CPU domain 12 + * 0b00..CPU is in RUN mode + * 0b01..CPU is in WAIT mode + * 0b10..CPU is in STOP mode + * 0b11..CPU is in SUSPEND mode + */ +#define CCM_OSCPLL_LPM_STATUS1_CPU_MODE_DOMAIN12(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_LPM_STATUS1_CPU_MODE_DOMAIN12_SHIFT)) & CCM_OSCPLL_LPM_STATUS1_CPU_MODE_DOMAIN12_MASK) + +#define CCM_OSCPLL_LPM_STATUS1_TRANS_REQ_DOMAIN12_MASK (0x40000U) +#define CCM_OSCPLL_LPM_STATUS1_TRANS_REQ_DOMAIN12_SHIFT (18U) +/*! TRANS_REQ_DOMAIN12 - GPC request CCM to enable or disable OSCPLL. This signal will turn to low once CCM complete response to GPC. */ +#define CCM_OSCPLL_LPM_STATUS1_TRANS_REQ_DOMAIN12(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_LPM_STATUS1_TRANS_REQ_DOMAIN12_SHIFT)) & CCM_OSCPLL_LPM_STATUS1_TRANS_REQ_DOMAIN12_MASK) + +#define CCM_OSCPLL_LPM_STATUS1_CPU_MODE_DOMAIN13_MASK (0x300000U) +#define CCM_OSCPLL_LPM_STATUS1_CPU_MODE_DOMAIN13_SHIFT (20U) +/*! CPU_MODE_DOMAIN13 - Current mode of CPU domain 13 + * 0b00..CPU is in RUN mode + * 0b01..CPU is in WAIT mode + * 0b10..CPU is in STOP mode + * 0b11..CPU is in SUSPEND mode + */ +#define CCM_OSCPLL_LPM_STATUS1_CPU_MODE_DOMAIN13(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_LPM_STATUS1_CPU_MODE_DOMAIN13_SHIFT)) & CCM_OSCPLL_LPM_STATUS1_CPU_MODE_DOMAIN13_MASK) + +#define CCM_OSCPLL_LPM_STATUS1_TRANS_REQ_DOMAIN13_MASK (0x400000U) +#define CCM_OSCPLL_LPM_STATUS1_TRANS_REQ_DOMAIN13_SHIFT (22U) +/*! TRANS_REQ_DOMAIN13 - GPC request CCM to enable or disable OSCPLL. This signal will turn to low once CCM complete response to GPC. */ +#define CCM_OSCPLL_LPM_STATUS1_TRANS_REQ_DOMAIN13(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_LPM_STATUS1_TRANS_REQ_DOMAIN13_SHIFT)) & CCM_OSCPLL_LPM_STATUS1_TRANS_REQ_DOMAIN13_MASK) + +#define CCM_OSCPLL_LPM_STATUS1_CPU_MODE_DOMAIN14_MASK (0x3000000U) +#define CCM_OSCPLL_LPM_STATUS1_CPU_MODE_DOMAIN14_SHIFT (24U) +/*! CPU_MODE_DOMAIN14 - Current mode of CPU domain 14 + * 0b00..CPU is in RUN mode + * 0b01..CPU is in WAIT mode + * 0b10..CPU is in STOP mode + * 0b11..CPU is in SUSPEND mode + */ +#define CCM_OSCPLL_LPM_STATUS1_CPU_MODE_DOMAIN14(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_LPM_STATUS1_CPU_MODE_DOMAIN14_SHIFT)) & CCM_OSCPLL_LPM_STATUS1_CPU_MODE_DOMAIN14_MASK) + +#define CCM_OSCPLL_LPM_STATUS1_TRANS_REQ_DOMAIN14_MASK (0x4000000U) +#define CCM_OSCPLL_LPM_STATUS1_TRANS_REQ_DOMAIN14_SHIFT (26U) +/*! TRANS_REQ_DOMAIN14 - GPC request CCM to enable or disable OSCPLL. This signal will turn to low once CCM complete response to GPC. */ +#define CCM_OSCPLL_LPM_STATUS1_TRANS_REQ_DOMAIN14(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_LPM_STATUS1_TRANS_REQ_DOMAIN14_SHIFT)) & CCM_OSCPLL_LPM_STATUS1_TRANS_REQ_DOMAIN14_MASK) + +#define CCM_OSCPLL_LPM_STATUS1_CPU_MODE_DOMAIN15_MASK (0x30000000U) +#define CCM_OSCPLL_LPM_STATUS1_CPU_MODE_DOMAIN15_SHIFT (28U) +/*! CPU_MODE_DOMAIN15 - Current mode of CPU domain 15 + * 0b00..CPU is in RUN mode + * 0b01..CPU is in WAIT mode + * 0b10..CPU is in STOP mode + * 0b11..CPU is in SUSPEND mode + */ +#define CCM_OSCPLL_LPM_STATUS1_CPU_MODE_DOMAIN15(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_LPM_STATUS1_CPU_MODE_DOMAIN15_SHIFT)) & CCM_OSCPLL_LPM_STATUS1_CPU_MODE_DOMAIN15_MASK) + +#define CCM_OSCPLL_LPM_STATUS1_TRANS_REQ_DOMAIN15_MASK (0x40000000U) +#define CCM_OSCPLL_LPM_STATUS1_TRANS_REQ_DOMAIN15_SHIFT (30U) +/*! TRANS_REQ_DOMAIN15 - GPC request CCM to enable or disable OSCPLL. This signal will turn to low once CCM complete response to GPC. */ +#define CCM_OSCPLL_LPM_STATUS1_TRANS_REQ_DOMAIN15(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_LPM_STATUS1_TRANS_REQ_DOMAIN15_SHIFT)) & CCM_OSCPLL_LPM_STATUS1_TRANS_REQ_DOMAIN15_MASK) +/*! @} */ + +/* The count of CCM_OSCPLL_LPM_STATUS1 */ +#define CCM_OSCPLL_LPM_STATUS1_COUNT (20U) + +/*! @name OSCPLL_LPM0 - Clock source low power mode setting */ +/*! @{ */ + +#define CCM_OSCPLL_LPM0_LPM_SETTING_D0_MASK (0x7U) +#define CCM_OSCPLL_LPM0_LPM_SETTING_D0_SHIFT (0U) +/*! LPM_SETTING_D0 - Clock Source LPM in DOMAIN0 + * 0b000..Clock Source will be OFF in any CPU mode. + * 0b001..Clock Source will be ON in RUN mode, OFF in WAIT/STOP/SUSPEND mode. + * 0b010..Clock Source will be ON in RUN/WAIT mode, OFF in STOP/SUSPEND mode. + * 0b011..Clock Source will be ON in RUN/WAIT/STOP mode, OFF in SUSPEND mode. + * 0b100..Clock Source will be ON in RUN/WAIT/STOP/SUSPEND Mode. + */ +#define CCM_OSCPLL_LPM0_LPM_SETTING_D0(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_LPM0_LPM_SETTING_D0_SHIFT)) & CCM_OSCPLL_LPM0_LPM_SETTING_D0_MASK) + +#define CCM_OSCPLL_LPM0_LPM_SETTING_D1_MASK (0x70U) +#define CCM_OSCPLL_LPM0_LPM_SETTING_D1_SHIFT (4U) +/*! LPM_SETTING_D1 - Clock Source LPM in DOMAIN1 + * 0b000..Clock Source will be OFF in any CPU mode. + * 0b001..Clock Source will be ON in RUN mode, OFF in WAIT/STOP/SUSPEND mode. + * 0b010..Clock Source will be ON in RUN/WAIT mode, OFF in STOP/SUSPEND mode. + * 0b011..Clock Source will be ON in RUN/WAIT/STOP mode, OFF in SUSPEND mode. + * 0b100..Clock Source will be ON in RUN/WAIT/STOP/SUSPEND mode. + */ +#define CCM_OSCPLL_LPM0_LPM_SETTING_D1(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_LPM0_LPM_SETTING_D1_SHIFT)) & CCM_OSCPLL_LPM0_LPM_SETTING_D1_MASK) + +#define CCM_OSCPLL_LPM0_LPM_SETTING_D2_MASK (0x700U) +#define CCM_OSCPLL_LPM0_LPM_SETTING_D2_SHIFT (8U) +/*! LPM_SETTING_D2 - Clock Source LPM in DOMAIN2 + * 0b000..Clock Source will be OFF in any CPU mode. + * 0b001..Clock Source will be ON in RUN mode, OFF in WAIT/STOP/SUSPEND mode. + * 0b010..Clock Source will be ON in RUN/WAIT mode, OFF in STOP/SUSPEND mode. + * 0b011..Clock Source will be ON in RUN/WAIT/STOP mode, OFF in SUSPEND mode. + * 0b100..Clock Source will be ON in RUN/WAIT/STOP/SUSPEND mode. + */ +#define CCM_OSCPLL_LPM0_LPM_SETTING_D2(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_LPM0_LPM_SETTING_D2_SHIFT)) & CCM_OSCPLL_LPM0_LPM_SETTING_D2_MASK) + +#define CCM_OSCPLL_LPM0_LPM_SETTING_D3_MASK (0x7000U) +#define CCM_OSCPLL_LPM0_LPM_SETTING_D3_SHIFT (12U) +/*! LPM_SETTING_D3 - Clock Source LPM in DOMAIN3 + * 0b000..Clock Source will be OFF in any CPU mode. + * 0b001..Clock Source will be ON in RUN mode, OFF in WAIT/STOP/SUSPEND mode. + * 0b010..Clock Source will be ON in RUN/WAIT mode, OFF in STOP/SUSPEND mode. + * 0b011..Clock Source will be ON in RUN/WAIT/STOP mode, OFF in SUSPEND mode. + * 0b100..Clock Source will be ON in RUN/WAIT/STOP/SUSPEND mode. + */ +#define CCM_OSCPLL_LPM0_LPM_SETTING_D3(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_LPM0_LPM_SETTING_D3_SHIFT)) & CCM_OSCPLL_LPM0_LPM_SETTING_D3_MASK) + +#define CCM_OSCPLL_LPM0_LPM_SETTING_D4_MASK (0x70000U) +#define CCM_OSCPLL_LPM0_LPM_SETTING_D4_SHIFT (16U) +/*! LPM_SETTING_D4 - Clock Source LPM in DOMAIN4 + * 0b000..Clock Source will be OFF in any CPU mode. + * 0b001..Clock Source will be ON in RUN mode, OFF in WAIT/STOP/SUSPEND mode. + * 0b010..Clock Source will be ON in RUN/WAIT mode, OFF in STOP/SUSPEND mode. + * 0b011..Clock Source will be ON in RUN/WAIT/STOP mode, OFF in SUSPEND mode. + * 0b100..Clock Source will be ON in RUN/WAIT/STOP/SUSPEND mode. + */ +#define CCM_OSCPLL_LPM0_LPM_SETTING_D4(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_LPM0_LPM_SETTING_D4_SHIFT)) & CCM_OSCPLL_LPM0_LPM_SETTING_D4_MASK) + +#define CCM_OSCPLL_LPM0_LPM_SETTING_D5_MASK (0x700000U) +#define CCM_OSCPLL_LPM0_LPM_SETTING_D5_SHIFT (20U) +/*! LPM_SETTING_D5 - Clock Source LPM in DOMAIN5 + * 0b000..Clock Source will be OFF in any CPU mode. + * 0b001..Clock Source will be ON in RUN mode, OFF in WAIT/STOP/SUSPEND mode. + * 0b010..Clock Source will be ON in RUN/WAIT mode, OFF in STOP/SUSPEND mode. + * 0b011..Clock Source will be ON in RUN/WAIT/STOP mode, OFF in SUSPEND mode. + * 0b100..Clock Source will be ON in RUN/WAIT/STOP/SUSPEND mode. + */ +#define CCM_OSCPLL_LPM0_LPM_SETTING_D5(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_LPM0_LPM_SETTING_D5_SHIFT)) & CCM_OSCPLL_LPM0_LPM_SETTING_D5_MASK) + +#define CCM_OSCPLL_LPM0_LPM_SETTING_D6_MASK (0x7000000U) +#define CCM_OSCPLL_LPM0_LPM_SETTING_D6_SHIFT (24U) +/*! LPM_SETTING_D6 - Clock Source LPM in DOMAIN6 + * 0b000..Clock Source will be OFF in any CPU mode. + * 0b001..Clock Source will be ON in RUN mode, OFF in WAIT/STOP/SUSPEND mode. + * 0b010..Clock Source will be ON in RUN/WAIT mode, OFF in STOP/SUSPEND mode. + * 0b011..Clock Source will be ON in RUN/WAIT/STOP mode, OFF in SUSPEND mode. + * 0b100..Clock Source will be ON in RUN/WAIT/STOP/SUSPEND mode. + */ +#define CCM_OSCPLL_LPM0_LPM_SETTING_D6(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_LPM0_LPM_SETTING_D6_SHIFT)) & CCM_OSCPLL_LPM0_LPM_SETTING_D6_MASK) + +#define CCM_OSCPLL_LPM0_LPM_SETTING_D7_MASK (0x70000000U) +#define CCM_OSCPLL_LPM0_LPM_SETTING_D7_SHIFT (28U) +/*! LPM_SETTING_D7 - Clock Source LPM in DOMAIN7 + * 0b000..Clock Source will be OFF in any CPU mode. + * 0b001..Clock Source will be ON in RUN mode, OFF in WAIT/STOP/SUSPEND mode. + * 0b010..Clock Source will be ON in RUN/WAIT mode, OFF in STOP/SUSPEND mode. + * 0b011..Clock Source will be ON in RUN/WAIT/STOP mode, OFF in SUSPEND mode. + * 0b100..Clock Source will be ON in RUN/WAIT/STOP/SUSPEND mode. + */ +#define CCM_OSCPLL_LPM0_LPM_SETTING_D7(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_LPM0_LPM_SETTING_D7_SHIFT)) & CCM_OSCPLL_LPM0_LPM_SETTING_D7_MASK) +/*! @} */ + +/* The count of CCM_OSCPLL_LPM0 */ +#define CCM_OSCPLL_LPM0_COUNT (20U) + +/*! @name OSCPLL_LPM1 - clock source low power mode setting */ +/*! @{ */ + +#define CCM_OSCPLL_LPM1_LPM_SETTING_D8_MASK (0x7U) +#define CCM_OSCPLL_LPM1_LPM_SETTING_D8_SHIFT (0U) +/*! LPM_SETTING_D8 - Clock Source LPM in DOMAIN8 + * 0b000..Clock Source will be OFF in any CPU mode. + * 0b001..Clock Source will be ON in RUN mode, OFF in WAIT/STOP/SUSPEND mode. + * 0b010..Clock Source will be ON in RUN/WAIT mode, OFF in STOP/SUSPEND mode. + * 0b011..Clock Source will be ON in RUN/WAIT/STOP mode, OFF in SUSPEND mode. + * 0b100..Clock Source will be ON in RUN/WAIT/STOP/SUSPEND mode. + */ +#define CCM_OSCPLL_LPM1_LPM_SETTING_D8(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_LPM1_LPM_SETTING_D8_SHIFT)) & CCM_OSCPLL_LPM1_LPM_SETTING_D8_MASK) + +#define CCM_OSCPLL_LPM1_LPM_SETTING_D9_MASK (0x70U) +#define CCM_OSCPLL_LPM1_LPM_SETTING_D9_SHIFT (4U) +/*! LPM_SETTING_D9 - Clock Source LPM in DOMAIN9 + * 0b000..Clock Source will be OFF in any CPU mode. + * 0b001..Clock Source will be ON in RUN mode, OFF in WAIT/STOP/SUSPEND mode. + * 0b010..Clock Source will be ON in RUN/WAIT mode, OFF in STOP/SUSPEND mode. + * 0b011..Clock Source will be ON in RUN/WAIT/STOP mode, OFF in SUSPEND mode. + * 0b100..Clock Source will be ON in RUN/WAIT/STOP/SUSPEND mode. + */ +#define CCM_OSCPLL_LPM1_LPM_SETTING_D9(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_LPM1_LPM_SETTING_D9_SHIFT)) & CCM_OSCPLL_LPM1_LPM_SETTING_D9_MASK) + +#define CCM_OSCPLL_LPM1_LPM_SETTING_D10_MASK (0x700U) +#define CCM_OSCPLL_LPM1_LPM_SETTING_D10_SHIFT (8U) +/*! LPM_SETTING_D10 - Clock Source LPM in DOMAIN10 + * 0b000..Clock Source will be OFF in any CPU mode. + * 0b001..Clock Source will be ON in RUN mode, OFF in WAIT/STOP/SUSPEND mode. + * 0b010..Clock Source will be ON in RUN/WAIT mode, OFF in STOP/SUSPEND mode. + * 0b011..Clock Source will be ON in RUN/WAIT/STOP mode, OFF in SUSPEND mode. + * 0b100..Clock Source will be ON in RUN/WAIT/STOP/SUSPEND mode. + */ +#define CCM_OSCPLL_LPM1_LPM_SETTING_D10(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_LPM1_LPM_SETTING_D10_SHIFT)) & CCM_OSCPLL_LPM1_LPM_SETTING_D10_MASK) + +#define CCM_OSCPLL_LPM1_LPM_SETTING_D11_MASK (0x7000U) +#define CCM_OSCPLL_LPM1_LPM_SETTING_D11_SHIFT (12U) +/*! LPM_SETTING_D11 - Clock Source LPM in DOMAIN11 + * 0b000..Clock Source will be OFF in any CPU mode. + * 0b001..Clock Source will be ON in RUN mode, OFF in WAIT/STOP/SUSPEND mode. + * 0b010..Clock Source will be ON in RUN/WAIT mode, OFF in STOP/SUSPEND mode. + * 0b011..Clock Source will be ON in RUN/WAIT/STOP mode, OFF in SUSPEND mode. + * 0b100..Clock Source will be ON in RUN/WAIT/STOP/SUSPEND mode. + */ +#define CCM_OSCPLL_LPM1_LPM_SETTING_D11(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_LPM1_LPM_SETTING_D11_SHIFT)) & CCM_OSCPLL_LPM1_LPM_SETTING_D11_MASK) + +#define CCM_OSCPLL_LPM1_LPM_SETTING_D12_MASK (0x70000U) +#define CCM_OSCPLL_LPM1_LPM_SETTING_D12_SHIFT (16U) +/*! LPM_SETTING_D12 - Clock Source LPM in DOMAIN12 + * 0b000..Clock Source will be OFF in any CPU mode. + * 0b001..Clock Source will be ON in RUN mode, OFF in WAIT/STOP/SUSPEND mode. + * 0b010..Clock Source will be ON in RUN/WAIT mode, OFF in STOP/SUSPEND mode. + * 0b011..Clock Source will be ON in RUN/WAIT/STOP mode, OFF in SUSPEND mode. + * 0b100..Clock Source will be ON in RUN/WAIT/STOP/SUSPEND mode. + */ +#define CCM_OSCPLL_LPM1_LPM_SETTING_D12(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_LPM1_LPM_SETTING_D12_SHIFT)) & CCM_OSCPLL_LPM1_LPM_SETTING_D12_MASK) + +#define CCM_OSCPLL_LPM1_LPM_SETTING_D13_MASK (0x700000U) +#define CCM_OSCPLL_LPM1_LPM_SETTING_D13_SHIFT (20U) +/*! LPM_SETTING_D13 - Clock Source LPM in DOMAIN13 + * 0b000..Clock Source will be OFF in any CPU mode. + * 0b001..Clock Source will be ON in RUN mode, OFF in WAIT/STOP/SUSPEND mode. + * 0b010..Clock Source will be ON in RUN/WAIT mode, OFF in STOP/SUSPEND mode. + * 0b011..Clock Source will be ON in RUN/WAIT/STOP mode, OFF in SUSPEND mode. + * 0b100..Clock Source will be ON in RUN/WAIT/STOP/SUSPEND mode. + */ +#define CCM_OSCPLL_LPM1_LPM_SETTING_D13(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_LPM1_LPM_SETTING_D13_SHIFT)) & CCM_OSCPLL_LPM1_LPM_SETTING_D13_MASK) + +#define CCM_OSCPLL_LPM1_LPM_SETTING_D14_MASK (0x7000000U) +#define CCM_OSCPLL_LPM1_LPM_SETTING_D14_SHIFT (24U) +/*! LPM_SETTING_D14 - Clock Source LPM in DOMAIN14 + * 0b000..Clock Source will be OFF in any CPU mode. + * 0b001..Clock Source will be ON in RUN mode, OFF in WAIT/STOP/SUSPEND mode. + * 0b010..Clock Source will be ON in RUN/WAIT mode, OFF in STOP/SUSPEND mode. + * 0b011..Clock Source will be ON in RUN/WAIT/STOP mode, OFF in SUSPEND mode. + * 0b100..Clock Source will be ON in RUN/WAIT/STOP/SUSPEND mode. + */ +#define CCM_OSCPLL_LPM1_LPM_SETTING_D14(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_LPM1_LPM_SETTING_D14_SHIFT)) & CCM_OSCPLL_LPM1_LPM_SETTING_D14_MASK) + +#define CCM_OSCPLL_LPM1_LPM_SETTING_D15_MASK (0x70000000U) +#define CCM_OSCPLL_LPM1_LPM_SETTING_D15_SHIFT (28U) +/*! LPM_SETTING_D15 - Clock Source LPM in DOMAIN15 + * 0b000..Clock Source will be OFF in any CPU mode. + * 0b001..Clock Source will be ON in RUN mode, OFF in WAIT/STOP/SUSPEND mode. + * 0b010..Clock Source will be ON in RUN/WAIT mode, OFF in STOP/SUSPEND mode. + * 0b011..Clock Source will be ON in RUN/WAIT/STOP mode, OFF in SUSPEND mode. + * 0b100..Clock Source will be ON in RUN/WAIT/STOP/SUSPEND mode. + */ +#define CCM_OSCPLL_LPM1_LPM_SETTING_D15(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_LPM1_LPM_SETTING_D15_SHIFT)) & CCM_OSCPLL_LPM1_LPM_SETTING_D15_MASK) +/*! @} */ + +/* The count of CCM_OSCPLL_LPM1 */ +#define CCM_OSCPLL_LPM1_COUNT (20U) + +/*! @name OSCPLL_LPM_CUR - LPM setting of current CPU domain */ +/*! @{ */ + +#define CCM_OSCPLL_LPM_CUR_LPM_SETTING_CUR_MASK (0x7U) +#define CCM_OSCPLL_LPM_CUR_LPM_SETTING_CUR_SHIFT (0U) +/*! LPM_SETTING_CUR - LPM SETTING of current CPU DOMAIN */ +#define CCM_OSCPLL_LPM_CUR_LPM_SETTING_CUR(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_LPM_CUR_LPM_SETTING_CUR_SHIFT)) & CCM_OSCPLL_LPM_CUR_LPM_SETTING_CUR_MASK) +/*! @} */ + +/* The count of CCM_OSCPLL_LPM_CUR */ +#define CCM_OSCPLL_LPM_CUR_COUNT (20U) + +/*! @name OSCPLL_STATUS0 - Clock source working status */ +/*! @{ */ + +#define CCM_OSCPLL_STATUS0_ON_MASK (0x1U) +#define CCM_OSCPLL_STATUS0_ON_SHIFT (0U) +/*! ON - Clock source current state + * 0b0..Clock source is OFF. + * 0b1..Clock source is ON. + */ +#define CCM_OSCPLL_STATUS0_ON(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_STATUS0_ON_SHIFT)) & CCM_OSCPLL_STATUS0_ON_MASK) + +#define CCM_OSCPLL_STATUS0_STATUS_EARLY_MASK (0x10U) +#define CCM_OSCPLL_STATUS0_STATUS_EARLY_SHIFT (4U) +#define CCM_OSCPLL_STATUS0_STATUS_EARLY(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_STATUS0_STATUS_EARLY_SHIFT)) & CCM_OSCPLL_STATUS0_STATUS_EARLY_MASK) + +#define CCM_OSCPLL_STATUS0_STATUS_LATE_MASK (0x20U) +#define CCM_OSCPLL_STATUS0_STATUS_LATE_SHIFT (5U) +#define CCM_OSCPLL_STATUS0_STATUS_LATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_STATUS0_STATUS_LATE_SHIFT)) & CCM_OSCPLL_STATUS0_STATUS_LATE_MASK) + +#define CCM_OSCPLL_STATUS0_IN_USE_MASK (0x1000U) +#define CCM_OSCPLL_STATUS0_IN_USE_SHIFT (12U) +/*! IN_USE - This Clock Source is being used or not. + * 0b0..Clock Source is not being used. + * 0b1..Clock Source is being used. + */ +#define CCM_OSCPLL_STATUS0_IN_USE(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_STATUS0_IN_USE_SHIFT)) & CCM_OSCPLL_STATUS0_IN_USE_MASK) +/*! @} */ + +/* The count of CCM_OSCPLL_STATUS0 */ +#define CCM_OSCPLL_STATUS0_COUNT (20U) + +/*! @name OSCPLL_STATUS1 - Clock source domain status */ +/*! @{ */ + +#define CCM_OSCPLL_STATUS1_DOMAIN_ACTIVE_MASK (0xFFFFU) +#define CCM_OSCPLL_STATUS1_DOMAIN_ACTIVE_SHIFT (0U) +/*! DOMAIN_ACTIVE - Domain active */ +#define CCM_OSCPLL_STATUS1_DOMAIN_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_STATUS1_DOMAIN_ACTIVE_SHIFT)) & CCM_OSCPLL_STATUS1_DOMAIN_ACTIVE_MASK) + +#define CCM_OSCPLL_STATUS1_DOMAIN_ENABLE_MASK (0xFFFF0000U) +#define CCM_OSCPLL_STATUS1_DOMAIN_ENABLE_SHIFT (16U) +/*! DOMAIN_ENABLE - Domain enable */ +#define CCM_OSCPLL_STATUS1_DOMAIN_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_STATUS1_DOMAIN_ENABLE_SHIFT)) & CCM_OSCPLL_STATUS1_DOMAIN_ENABLE_MASK) +/*! @} */ + +/* The count of CCM_OSCPLL_STATUS1 */ +#define CCM_OSCPLL_STATUS1_COUNT (20U) + +/*! @name OSCPLL_AUTHEN - Clock Source access control */ +/*! @{ */ + +#define CCM_OSCPLL_AUTHEN_CPULPM_MODE_MASK (0x4U) +#define CCM_OSCPLL_AUTHEN_CPULPM_MODE_SHIFT (2U) +/*! CPULPM_MODE - CPULPM mode enable + * 0b0..Disable CPULPM mode. + * 0b1..Enable CPULPM mode. + */ +#define CCM_OSCPLL_AUTHEN_CPULPM_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_AUTHEN_CPULPM_MODE_SHIFT)) & CCM_OSCPLL_AUTHEN_CPULPM_MODE_MASK) + +#define CCM_OSCPLL_AUTHEN_AUTO_CTRL_MASK (0x8U) +#define CCM_OSCPLL_AUTHEN_AUTO_CTRL_SHIFT (3U) +/*! AUTO_CTRL - Auto mode enable + * 0b0..Disable Auto mode + * 0b1..Enable Auto mode + */ +#define CCM_OSCPLL_AUTHEN_AUTO_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_AUTHEN_AUTO_CTRL_SHIFT)) & CCM_OSCPLL_AUTHEN_AUTO_CTRL_MASK) + +#define CCM_OSCPLL_AUTHEN_LOCK_MODE_MASK (0x80U) +#define CCM_OSCPLL_AUTHEN_LOCK_MODE_SHIFT (7U) +/*! LOCK_MODE + * 0b0..CPULPM_MODE and AUTO_CTRL is not locked. + * 0b1..CPULPM_MODE and AUTO_CTRL is locked. + */ +#define CCM_OSCPLL_AUTHEN_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_AUTHEN_LOCK_MODE_SHIFT)) & CCM_OSCPLL_AUTHEN_LOCK_MODE_MASK) + +#define CCM_OSCPLL_AUTHEN_TZ_USER_MASK (0x100U) +#define CCM_OSCPLL_AUTHEN_TZ_USER_SHIFT (8U) +/*! TZ_USER - User access permission + * 0b0..Clock Source settings cannot be changed in user mode. + * 0b1..Clock Source settings can be changed in user mode. + */ +#define CCM_OSCPLL_AUTHEN_TZ_USER(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_AUTHEN_TZ_USER_SHIFT)) & CCM_OSCPLL_AUTHEN_TZ_USER_MASK) + +#define CCM_OSCPLL_AUTHEN_TZ_NS_MASK (0x200U) +#define CCM_OSCPLL_AUTHEN_TZ_NS_SHIFT (9U) +/*! TZ_NS - Non-secure access permission + * 0b0..Cannot be changed in Non-secure mode. + * 0b1..Can be changed in Non-secure mode. + */ +#define CCM_OSCPLL_AUTHEN_TZ_NS(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_AUTHEN_TZ_NS_SHIFT)) & CCM_OSCPLL_AUTHEN_TZ_NS_MASK) + +#define CCM_OSCPLL_AUTHEN_LOCK_TZ_MASK (0x800U) +#define CCM_OSCPLL_AUTHEN_LOCK_TZ_SHIFT (11U) +/*! LOCK_TZ - Lock TrustZone settings + * 0b0..TrustZone settings is not locked. + * 0b1..TrustZone settings is locked. + */ +#define CCM_OSCPLL_AUTHEN_LOCK_TZ(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_AUTHEN_LOCK_TZ_SHIFT)) & CCM_OSCPLL_AUTHEN_LOCK_TZ_MASK) + +#define CCM_OSCPLL_AUTHEN_LOCK_LIST_MASK (0x8000U) +#define CCM_OSCPLL_AUTHEN_LOCK_LIST_SHIFT (15U) +/*! LOCK_LIST - Lock white list + * 0b0..Whitelist is not locked. + * 0b1..Whitelist is locked. + */ +#define CCM_OSCPLL_AUTHEN_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_AUTHEN_LOCK_LIST_SHIFT)) & CCM_OSCPLL_AUTHEN_LOCK_LIST_MASK) + +#define CCM_OSCPLL_AUTHEN_WHITE_LIST_MASK (0xFFFF0000U) +#define CCM_OSCPLL_AUTHEN_WHITE_LIST_SHIFT (16U) +/*! WHITE_LIST - Whitelist */ +#define CCM_OSCPLL_AUTHEN_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_AUTHEN_WHITE_LIST_SHIFT)) & CCM_OSCPLL_AUTHEN_WHITE_LIST_MASK) +/*! @} */ + +/* The count of CCM_OSCPLL_AUTHEN */ +#define CCM_OSCPLL_AUTHEN_COUNT (20U) + +/*! @name LPCG_DIRECT - LPCG direct control */ +/*! @{ */ + +#define CCM_LPCG_DIRECT_ON_MASK (0x1U) +#define CCM_LPCG_DIRECT_ON_SHIFT (0U) +/*! ON - Turn on LPCG + * 0b0..LPCG gate clock + * 0b1..LPCG ungate clock + */ +#define CCM_LPCG_DIRECT_ON(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_DIRECT_ON_SHIFT)) & CCM_LPCG_DIRECT_ON_MASK) + +#define CCM_LPCG_DIRECT_CLKOFF_ACK_TIMEOUT_EN_MASK (0x4U) +#define CCM_LPCG_DIRECT_CLKOFF_ACK_TIMEOUT_EN_SHIFT (2U) +/*! CLKOFF_ACK_TIMEOUT_EN - Clock off handshake timeout enable + * 0b0..disable + * 0b1..enable + */ +#define CCM_LPCG_DIRECT_CLKOFF_ACK_TIMEOUT_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_DIRECT_CLKOFF_ACK_TIMEOUT_EN_SHIFT)) & CCM_LPCG_DIRECT_CLKOFF_ACK_TIMEOUT_EN_MASK) +/*! @} */ + +/* The count of CCM_LPCG_DIRECT */ +#define CCM_LPCG_DIRECT_COUNT (127U) + +/*! @name LPCG_LPM_STATUS0 - Low power mode information transfer status */ +/*! @{ */ + +#define CCM_LPCG_LPM_STATUS0_CPU_MODE_DOMAIN0_MASK (0x3U) +#define CCM_LPCG_LPM_STATUS0_CPU_MODE_DOMAIN0_SHIFT (0U) +/*! CPU_MODE_DOMAIN0 - Current mode of CPU domain 0 + * 0b00..CPU is in RUN mode + * 0b01..CPU is in WAIT mode + * 0b10..CPU is in STOP mode + * 0b11..CPU is in SUSPEND mode + */ +#define CCM_LPCG_LPM_STATUS0_CPU_MODE_DOMAIN0(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_LPM_STATUS0_CPU_MODE_DOMAIN0_SHIFT)) & CCM_LPCG_LPM_STATUS0_CPU_MODE_DOMAIN0_MASK) + +#define CCM_LPCG_LPM_STATUS0_TRANS_REQ_DOMAIN0_MASK (0x4U) +#define CCM_LPCG_LPM_STATUS0_TRANS_REQ_DOMAIN0_SHIFT (2U) +/*! TRANS_REQ_DOMAIN0 - GPC request CCM to enable or disable LPCG. This signal will turn to low once CCM complete response to GPC. */ +#define CCM_LPCG_LPM_STATUS0_TRANS_REQ_DOMAIN0(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_LPM_STATUS0_TRANS_REQ_DOMAIN0_SHIFT)) & CCM_LPCG_LPM_STATUS0_TRANS_REQ_DOMAIN0_MASK) + +#define CCM_LPCG_LPM_STATUS0_CPU_MODE_DOMAIN1_MASK (0x30U) +#define CCM_LPCG_LPM_STATUS0_CPU_MODE_DOMAIN1_SHIFT (4U) +/*! CPU_MODE_DOMAIN1 - Current mode of CPU domain 1 + * 0b00..CPU is in RUN mode + * 0b01..CPU is in WAIT mode + * 0b10..CPU is in STOP mode + * 0b11..CPU is in SUSPEND mode + */ +#define CCM_LPCG_LPM_STATUS0_CPU_MODE_DOMAIN1(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_LPM_STATUS0_CPU_MODE_DOMAIN1_SHIFT)) & CCM_LPCG_LPM_STATUS0_CPU_MODE_DOMAIN1_MASK) + +#define CCM_LPCG_LPM_STATUS0_TRANS_REQ_DOMAIN1_MASK (0x40U) +#define CCM_LPCG_LPM_STATUS0_TRANS_REQ_DOMAIN1_SHIFT (6U) +#define CCM_LPCG_LPM_STATUS0_TRANS_REQ_DOMAIN1(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_LPM_STATUS0_TRANS_REQ_DOMAIN1_SHIFT)) & CCM_LPCG_LPM_STATUS0_TRANS_REQ_DOMAIN1_MASK) + +#define CCM_LPCG_LPM_STATUS0_CPU_MODE_DOMAIN2_MASK (0x300U) +#define CCM_LPCG_LPM_STATUS0_CPU_MODE_DOMAIN2_SHIFT (8U) +/*! CPU_MODE_DOMAIN2 - Current mode of CPU domain 2 + * 0b00..CPU is in RUN mode + * 0b01..CPU is in WAIT mode + * 0b10..CPU is in STOP mode + * 0b11..CPU is in SUSPEND mode + */ +#define CCM_LPCG_LPM_STATUS0_CPU_MODE_DOMAIN2(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_LPM_STATUS0_CPU_MODE_DOMAIN2_SHIFT)) & CCM_LPCG_LPM_STATUS0_CPU_MODE_DOMAIN2_MASK) + +#define CCM_LPCG_LPM_STATUS0_TRANS_REQ_DOMAIN2_MASK (0x400U) +#define CCM_LPCG_LPM_STATUS0_TRANS_REQ_DOMAIN2_SHIFT (10U) +/*! TRANS_REQ_DOMAIN2 - GPC request CCM to enable or disable LPCG. This signal will turn to low once CCM complete response to GPC. */ +#define CCM_LPCG_LPM_STATUS0_TRANS_REQ_DOMAIN2(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_LPM_STATUS0_TRANS_REQ_DOMAIN2_SHIFT)) & CCM_LPCG_LPM_STATUS0_TRANS_REQ_DOMAIN2_MASK) + +#define CCM_LPCG_LPM_STATUS0_CPU_MODE_DOMAIN3_MASK (0x3000U) +#define CCM_LPCG_LPM_STATUS0_CPU_MODE_DOMAIN3_SHIFT (12U) +/*! CPU_MODE_DOMAIN3 - Current mode of CPU domain 3 + * 0b00..CPU is in RUN mode + * 0b01..CPU is in WAIT mode + * 0b10..CPU is in STOP mode + * 0b11..CPU is in SUSPEND mode + */ +#define CCM_LPCG_LPM_STATUS0_CPU_MODE_DOMAIN3(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_LPM_STATUS0_CPU_MODE_DOMAIN3_SHIFT)) & CCM_LPCG_LPM_STATUS0_CPU_MODE_DOMAIN3_MASK) + +#define CCM_LPCG_LPM_STATUS0_TRANS_REQ_DOMAIN3_MASK (0x4000U) +#define CCM_LPCG_LPM_STATUS0_TRANS_REQ_DOMAIN3_SHIFT (14U) +#define CCM_LPCG_LPM_STATUS0_TRANS_REQ_DOMAIN3(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_LPM_STATUS0_TRANS_REQ_DOMAIN3_SHIFT)) & CCM_LPCG_LPM_STATUS0_TRANS_REQ_DOMAIN3_MASK) + +#define CCM_LPCG_LPM_STATUS0_CPU_MODE_DOMAIN4_MASK (0x30000U) +#define CCM_LPCG_LPM_STATUS0_CPU_MODE_DOMAIN4_SHIFT (16U) +/*! CPU_MODE_DOMAIN4 - Current mode of CPU domain 4 + * 0b00..CPU is in RUN mode + * 0b01..CPU is in WAIT mode + * 0b10..CPU is in STOP mode + * 0b11..CPU is in SUSPEND mode + */ +#define CCM_LPCG_LPM_STATUS0_CPU_MODE_DOMAIN4(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_LPM_STATUS0_CPU_MODE_DOMAIN4_SHIFT)) & CCM_LPCG_LPM_STATUS0_CPU_MODE_DOMAIN4_MASK) + +#define CCM_LPCG_LPM_STATUS0_TRANS_REQ_DOMAIN4_MASK (0x40000U) +#define CCM_LPCG_LPM_STATUS0_TRANS_REQ_DOMAIN4_SHIFT (18U) +/*! TRANS_REQ_DOMAIN4 - GPC request CCM to enable or disable LPCG. This signal will turn to low once CCM complete response to GPC. */ +#define CCM_LPCG_LPM_STATUS0_TRANS_REQ_DOMAIN4(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_LPM_STATUS0_TRANS_REQ_DOMAIN4_SHIFT)) & CCM_LPCG_LPM_STATUS0_TRANS_REQ_DOMAIN4_MASK) + +#define CCM_LPCG_LPM_STATUS0_CPU_MODE_DOMAIN5_MASK (0x300000U) +#define CCM_LPCG_LPM_STATUS0_CPU_MODE_DOMAIN5_SHIFT (20U) +/*! CPU_MODE_DOMAIN5 - Current mode of CPU domain 5 + * 0b00..CPU is in RUN mode + * 0b01..CPU is in WAIT mode + * 0b10..CPU is in STOP mode + * 0b11..CPU is in SUSPEND mode + */ +#define CCM_LPCG_LPM_STATUS0_CPU_MODE_DOMAIN5(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_LPM_STATUS0_CPU_MODE_DOMAIN5_SHIFT)) & CCM_LPCG_LPM_STATUS0_CPU_MODE_DOMAIN5_MASK) + +#define CCM_LPCG_LPM_STATUS0_TRANS_REQ_DOMAIN5_MASK (0x400000U) +#define CCM_LPCG_LPM_STATUS0_TRANS_REQ_DOMAIN5_SHIFT (22U) +/*! TRANS_REQ_DOMAIN5 - GPC request CCM to enable or disable LPCG. This signal will turn to low once CCM complete response to GPC. */ +#define CCM_LPCG_LPM_STATUS0_TRANS_REQ_DOMAIN5(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_LPM_STATUS0_TRANS_REQ_DOMAIN5_SHIFT)) & CCM_LPCG_LPM_STATUS0_TRANS_REQ_DOMAIN5_MASK) + +#define CCM_LPCG_LPM_STATUS0_CPU_MODE_DOMAIN6_MASK (0x3000000U) +#define CCM_LPCG_LPM_STATUS0_CPU_MODE_DOMAIN6_SHIFT (24U) +/*! CPU_MODE_DOMAIN6 - Current mode of CPU domain 6 + * 0b00..CPU is in RUN mode + * 0b01..CPU is in WAIT mode + * 0b10..CPU is in STOP mode + * 0b11..CPU is in SUSPEND mode + */ +#define CCM_LPCG_LPM_STATUS0_CPU_MODE_DOMAIN6(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_LPM_STATUS0_CPU_MODE_DOMAIN6_SHIFT)) & CCM_LPCG_LPM_STATUS0_CPU_MODE_DOMAIN6_MASK) + +#define CCM_LPCG_LPM_STATUS0_TRANS_REQ_DOMAIN6_MASK (0x4000000U) +#define CCM_LPCG_LPM_STATUS0_TRANS_REQ_DOMAIN6_SHIFT (26U) +/*! TRANS_REQ_DOMAIN6 - GPC request CCM to enable or disable LPCG. This signal will turn to low once CCM complete response to GPC. */ +#define CCM_LPCG_LPM_STATUS0_TRANS_REQ_DOMAIN6(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_LPM_STATUS0_TRANS_REQ_DOMAIN6_SHIFT)) & CCM_LPCG_LPM_STATUS0_TRANS_REQ_DOMAIN6_MASK) + +#define CCM_LPCG_LPM_STATUS0_CPU_MODE_DOMAIN7_MASK (0x30000000U) +#define CCM_LPCG_LPM_STATUS0_CPU_MODE_DOMAIN7_SHIFT (28U) +/*! CPU_MODE_DOMAIN7 - Current mode of CPU domain 7 + * 0b00..CPU is in RUN mode + * 0b01..CPU is in WAIT mode + * 0b10..CPU is in STOP mode + * 0b11..CPU is in SUSPEND mode + */ +#define CCM_LPCG_LPM_STATUS0_CPU_MODE_DOMAIN7(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_LPM_STATUS0_CPU_MODE_DOMAIN7_SHIFT)) & CCM_LPCG_LPM_STATUS0_CPU_MODE_DOMAIN7_MASK) + +#define CCM_LPCG_LPM_STATUS0_TRANS_REQ_DOMAIN7_MASK (0x40000000U) +#define CCM_LPCG_LPM_STATUS0_TRANS_REQ_DOMAIN7_SHIFT (30U) +/*! TRANS_REQ_DOMAIN7 - GPC request CCM to enable or disable LPCG. This signal will turn to low once CCM complete response to GPC. */ +#define CCM_LPCG_LPM_STATUS0_TRANS_REQ_DOMAIN7(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_LPM_STATUS0_TRANS_REQ_DOMAIN7_SHIFT)) & CCM_LPCG_LPM_STATUS0_TRANS_REQ_DOMAIN7_MASK) +/*! @} */ + +/* The count of CCM_LPCG_LPM_STATUS0 */ +#define CCM_LPCG_LPM_STATUS0_COUNT (127U) + +/*! @name LPCG_LPM_STATUS1 - Low power mode information transfer status */ +/*! @{ */ + +#define CCM_LPCG_LPM_STATUS1_CPU_MODE_DOMAIN8_MASK (0x3U) +#define CCM_LPCG_LPM_STATUS1_CPU_MODE_DOMAIN8_SHIFT (0U) +/*! CPU_MODE_DOMAIN8 - Current mode of CPU domain 8 + * 0b00..CPU is in RUN mode + * 0b01..CPU is in WAIT mode + * 0b10..CPU is in STOP mode + * 0b11..CPU is in SUSPEND mode + */ +#define CCM_LPCG_LPM_STATUS1_CPU_MODE_DOMAIN8(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_LPM_STATUS1_CPU_MODE_DOMAIN8_SHIFT)) & CCM_LPCG_LPM_STATUS1_CPU_MODE_DOMAIN8_MASK) + +#define CCM_LPCG_LPM_STATUS1_TRANS_REQ_DOMAIN8_MASK (0x4U) +#define CCM_LPCG_LPM_STATUS1_TRANS_REQ_DOMAIN8_SHIFT (2U) +/*! TRANS_REQ_DOMAIN8 - GPC request CCM to enable or disable LPCG. This signal will turn to low once CCM complete response to GPC. */ +#define CCM_LPCG_LPM_STATUS1_TRANS_REQ_DOMAIN8(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_LPM_STATUS1_TRANS_REQ_DOMAIN8_SHIFT)) & CCM_LPCG_LPM_STATUS1_TRANS_REQ_DOMAIN8_MASK) + +#define CCM_LPCG_LPM_STATUS1_CPU_MODE_DOMAIN9_MASK (0x30U) +#define CCM_LPCG_LPM_STATUS1_CPU_MODE_DOMAIN9_SHIFT (4U) +/*! CPU_MODE_DOMAIN9 - Current mode of CPU domain 9 + * 0b00..CPU is in RUN mode + * 0b01..CPU is in WAIT mode + * 0b10..CPU is in STOP mode + * 0b11..CPU is in SUSPEND mode + */ +#define CCM_LPCG_LPM_STATUS1_CPU_MODE_DOMAIN9(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_LPM_STATUS1_CPU_MODE_DOMAIN9_SHIFT)) & CCM_LPCG_LPM_STATUS1_CPU_MODE_DOMAIN9_MASK) + +#define CCM_LPCG_LPM_STATUS1_TRANS_REQ_DOMAIN9_MASK (0x40U) +#define CCM_LPCG_LPM_STATUS1_TRANS_REQ_DOMAIN9_SHIFT (6U) +/*! TRANS_REQ_DOMAIN9 - GPC request CCM to enable or disable LPCG. This signal will turn to low once CCM complete response to GPC. */ +#define CCM_LPCG_LPM_STATUS1_TRANS_REQ_DOMAIN9(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_LPM_STATUS1_TRANS_REQ_DOMAIN9_SHIFT)) & CCM_LPCG_LPM_STATUS1_TRANS_REQ_DOMAIN9_MASK) + +#define CCM_LPCG_LPM_STATUS1_CPU_MODE_DOMAIN10_MASK (0x300U) +#define CCM_LPCG_LPM_STATUS1_CPU_MODE_DOMAIN10_SHIFT (8U) +/*! CPU_MODE_DOMAIN10 - Current mode of CPU domain 10 + * 0b00..CPU is in RUN mode + * 0b01..CPU is in WAIT mode + * 0b10..CPU is in STOP mode + * 0b11..CPU is in SUSPEND mode + */ +#define CCM_LPCG_LPM_STATUS1_CPU_MODE_DOMAIN10(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_LPM_STATUS1_CPU_MODE_DOMAIN10_SHIFT)) & CCM_LPCG_LPM_STATUS1_CPU_MODE_DOMAIN10_MASK) + +#define CCM_LPCG_LPM_STATUS1_TRANS_REQ_DOMAIN10_MASK (0x400U) +#define CCM_LPCG_LPM_STATUS1_TRANS_REQ_DOMAIN10_SHIFT (10U) +/*! TRANS_REQ_DOMAIN10 - GPC request CCM to enable or disable LPCG. This signal will turn to low once CCM complete response to GPC. */ +#define CCM_LPCG_LPM_STATUS1_TRANS_REQ_DOMAIN10(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_LPM_STATUS1_TRANS_REQ_DOMAIN10_SHIFT)) & CCM_LPCG_LPM_STATUS1_TRANS_REQ_DOMAIN10_MASK) + +#define CCM_LPCG_LPM_STATUS1_CPU_MODE_DOMAIN11_MASK (0x3000U) +#define CCM_LPCG_LPM_STATUS1_CPU_MODE_DOMAIN11_SHIFT (12U) +/*! CPU_MODE_DOMAIN11 - Current mode of CPU domain 11 + * 0b00..CPU is in RUN mode + * 0b01..CPU is in WAIT mode + * 0b10..CPU is in STOP mode + * 0b11..CPU is in SUSPEND mode + */ +#define CCM_LPCG_LPM_STATUS1_CPU_MODE_DOMAIN11(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_LPM_STATUS1_CPU_MODE_DOMAIN11_SHIFT)) & CCM_LPCG_LPM_STATUS1_CPU_MODE_DOMAIN11_MASK) + +#define CCM_LPCG_LPM_STATUS1_TRANS_REQ_DOMAIN11_MASK (0x4000U) +#define CCM_LPCG_LPM_STATUS1_TRANS_REQ_DOMAIN11_SHIFT (14U) +/*! TRANS_REQ_DOMAIN11 - GPC request CCM to enable or disable LPCG. This signal will turn to low once CCM complete response to GPC. */ +#define CCM_LPCG_LPM_STATUS1_TRANS_REQ_DOMAIN11(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_LPM_STATUS1_TRANS_REQ_DOMAIN11_SHIFT)) & CCM_LPCG_LPM_STATUS1_TRANS_REQ_DOMAIN11_MASK) + +#define CCM_LPCG_LPM_STATUS1_CPU_MODE_DOMAIN12_MASK (0x30000U) +#define CCM_LPCG_LPM_STATUS1_CPU_MODE_DOMAIN12_SHIFT (16U) +/*! CPU_MODE_DOMAIN12 - Current mode of CPU domain 12 + * 0b00..CPU is in RUN mode + * 0b01..CPU is in WAIT mode + * 0b10..CPU is in STOP mode + * 0b11..CPU is in SUSPEND mode + */ +#define CCM_LPCG_LPM_STATUS1_CPU_MODE_DOMAIN12(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_LPM_STATUS1_CPU_MODE_DOMAIN12_SHIFT)) & CCM_LPCG_LPM_STATUS1_CPU_MODE_DOMAIN12_MASK) + +#define CCM_LPCG_LPM_STATUS1_TRANS_REQ_DOMAIN12_MASK (0x40000U) +#define CCM_LPCG_LPM_STATUS1_TRANS_REQ_DOMAIN12_SHIFT (18U) +/*! TRANS_REQ_DOMAIN12 - GPC request CCM to enable or disable LPCG. This signal will turn to low once CCM complete response to GPC. */ +#define CCM_LPCG_LPM_STATUS1_TRANS_REQ_DOMAIN12(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_LPM_STATUS1_TRANS_REQ_DOMAIN12_SHIFT)) & CCM_LPCG_LPM_STATUS1_TRANS_REQ_DOMAIN12_MASK) + +#define CCM_LPCG_LPM_STATUS1_CPU_MODE_DOMAIN13_MASK (0x300000U) +#define CCM_LPCG_LPM_STATUS1_CPU_MODE_DOMAIN13_SHIFT (20U) +/*! CPU_MODE_DOMAIN13 - Current mode of CPU domain 13 + * 0b00..CPU is in RUN mode + * 0b01..CPU is in WAIT mode + * 0b10..CPU is in STOP mode + * 0b11..CPU is in SUSPEND mode + */ +#define CCM_LPCG_LPM_STATUS1_CPU_MODE_DOMAIN13(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_LPM_STATUS1_CPU_MODE_DOMAIN13_SHIFT)) & CCM_LPCG_LPM_STATUS1_CPU_MODE_DOMAIN13_MASK) + +#define CCM_LPCG_LPM_STATUS1_TRANS_REQ_DOMAIN13_MASK (0x400000U) +#define CCM_LPCG_LPM_STATUS1_TRANS_REQ_DOMAIN13_SHIFT (22U) +/*! TRANS_REQ_DOMAIN13 - GPC request CCM to enable or disable LPCG. This signal will turn to low once CCM complete response to GPC. */ +#define CCM_LPCG_LPM_STATUS1_TRANS_REQ_DOMAIN13(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_LPM_STATUS1_TRANS_REQ_DOMAIN13_SHIFT)) & CCM_LPCG_LPM_STATUS1_TRANS_REQ_DOMAIN13_MASK) + +#define CCM_LPCG_LPM_STATUS1_CPU_MODE_DOMAIN14_MASK (0x3000000U) +#define CCM_LPCG_LPM_STATUS1_CPU_MODE_DOMAIN14_SHIFT (24U) +/*! CPU_MODE_DOMAIN14 - Current mode of CPU domain 14 + * 0b00..CPU is in RUN mode + * 0b01..CPU is in WAIT mode + * 0b10..CPU is in STOP mode + * 0b11..CPU is in SUSPEND mode + */ +#define CCM_LPCG_LPM_STATUS1_CPU_MODE_DOMAIN14(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_LPM_STATUS1_CPU_MODE_DOMAIN14_SHIFT)) & CCM_LPCG_LPM_STATUS1_CPU_MODE_DOMAIN14_MASK) + +#define CCM_LPCG_LPM_STATUS1_TRANS_REQ_DOMAIN14_MASK (0x4000000U) +#define CCM_LPCG_LPM_STATUS1_TRANS_REQ_DOMAIN14_SHIFT (26U) +#define CCM_LPCG_LPM_STATUS1_TRANS_REQ_DOMAIN14(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_LPM_STATUS1_TRANS_REQ_DOMAIN14_SHIFT)) & CCM_LPCG_LPM_STATUS1_TRANS_REQ_DOMAIN14_MASK) + +#define CCM_LPCG_LPM_STATUS1_CPU_MODE_DOMAIN15_MASK (0x30000000U) +#define CCM_LPCG_LPM_STATUS1_CPU_MODE_DOMAIN15_SHIFT (28U) +/*! CPU_MODE_DOMAIN15 - Current mode of CPU domain 15 + * 0b00..CPU is in RUN mode + * 0b01..CPU is in WAIT mode + * 0b10..CPU is in STOP mode + * 0b11..CPU is in SUSPEND mode + */ +#define CCM_LPCG_LPM_STATUS1_CPU_MODE_DOMAIN15(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_LPM_STATUS1_CPU_MODE_DOMAIN15_SHIFT)) & CCM_LPCG_LPM_STATUS1_CPU_MODE_DOMAIN15_MASK) + +#define CCM_LPCG_LPM_STATUS1_TRANS_REQ_DOMAIN15_MASK (0x40000000U) +#define CCM_LPCG_LPM_STATUS1_TRANS_REQ_DOMAIN15_SHIFT (30U) +/*! TRANS_REQ_DOMAIN15 - GPC request CCM to enable or disable LPCG. This signal will turn to low once CCM complete response to GPC. */ +#define CCM_LPCG_LPM_STATUS1_TRANS_REQ_DOMAIN15(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_LPM_STATUS1_TRANS_REQ_DOMAIN15_SHIFT)) & CCM_LPCG_LPM_STATUS1_TRANS_REQ_DOMAIN15_MASK) +/*! @} */ + +/* The count of CCM_LPCG_LPM_STATUS1 */ +#define CCM_LPCG_LPM_STATUS1_COUNT (127U) + +/*! @name LPCG_LPM0 - LPCG low power mode setting */ +/*! @{ */ + +#define CCM_LPCG_LPM0_LPM_SETTING_D0_MASK (0x7U) +#define CCM_LPCG_LPM0_LPM_SETTING_D0_SHIFT (0U) +/*! LPM_SETTING_D0 - LPCG LPM in DOMAIN0 + * 0b000..LPCG will be OFF in any CPU mode. + * 0b001..LPCG will be ON in RUN mode, OFF in WAIT/STOP/SUSPEND mode. + * 0b010..LPCG will be ON in RUN/WAIT mode, OFF in STOP/SUSPEND mode. + * 0b011..LPCG will be ON in RUN/WAIT/STOP mode, OFF in SUSPEND mode. + * 0b100..LPCG will be ON in RUN/WAIT/STOP/SUSPEND mode. + */ +#define CCM_LPCG_LPM0_LPM_SETTING_D0(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_LPM0_LPM_SETTING_D0_SHIFT)) & CCM_LPCG_LPM0_LPM_SETTING_D0_MASK) + +#define CCM_LPCG_LPM0_LPM_SETTING_D1_MASK (0x70U) +#define CCM_LPCG_LPM0_LPM_SETTING_D1_SHIFT (4U) +/*! LPM_SETTING_D1 - LPCG LPM in DOMAIN1 + * 0b000..LPCG will be OFF in any CPU mode. + * 0b001..LPCG will be ON in RUN mode, OFF in WAIT/STOP/SUSPEND mode. + * 0b010..LPCG will be ON in RUN/WAIT mode, OFF in STOP/SUSPEND mode. + * 0b011..LPCG will be ON in RUN/WAIT/STOP mode, OFF in SUSPEND mode. + * 0b100..LPCG will be ON in RUN/WAIT/STOP/SUSPEND mode. + */ +#define CCM_LPCG_LPM0_LPM_SETTING_D1(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_LPM0_LPM_SETTING_D1_SHIFT)) & CCM_LPCG_LPM0_LPM_SETTING_D1_MASK) + +#define CCM_LPCG_LPM0_LPM_SETTING_D2_MASK (0x700U) +#define CCM_LPCG_LPM0_LPM_SETTING_D2_SHIFT (8U) +/*! LPM_SETTING_D2 - LPCG LPM in DOMAIN2 + * 0b000..LPCG will be OFF in any CPU mode. + * 0b001..LPCG will be ON in RUN mode, OFF in WAIT/STOP/SUSPEND mode. + * 0b010..LPCG will be ON in RUN/WAIT mode, OFF in STOP/SUSPEND mode. + * 0b011..LPCG will be ON in RUN/WAIT/STOP mode, OFF in SUSPEND mode. + * 0b100..LPCG will be ON in RUN/WAIT/STOP/SUSPEND mode. + */ +#define CCM_LPCG_LPM0_LPM_SETTING_D2(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_LPM0_LPM_SETTING_D2_SHIFT)) & CCM_LPCG_LPM0_LPM_SETTING_D2_MASK) + +#define CCM_LPCG_LPM0_LPM_SETTING_D3_MASK (0x7000U) +#define CCM_LPCG_LPM0_LPM_SETTING_D3_SHIFT (12U) +/*! LPM_SETTING_D3 + * 0b000..LPCG will be OFF in any CPU mode. + * 0b001..LPCG will be ON in RUN mode, OFF in WAIT/STOP/SUSPEND mode. + * 0b010..LPCG will be ON in RUN/WAIT mode, OFF in STOP/SUSPEND mode. + * 0b011..LPCG will be ON in RUN/WAIT/STOP mode, OFF in SUSPEND mode. + * 0b100..LPCG will be ON in RUN/WAIT/STOP/SUSPEND mode. + */ +#define CCM_LPCG_LPM0_LPM_SETTING_D3(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_LPM0_LPM_SETTING_D3_SHIFT)) & CCM_LPCG_LPM0_LPM_SETTING_D3_MASK) + +#define CCM_LPCG_LPM0_LPM_SETTING_D4_MASK (0x70000U) +#define CCM_LPCG_LPM0_LPM_SETTING_D4_SHIFT (16U) +/*! LPM_SETTING_D4 + * 0b000..LPCG will be OFF in any CPU mode. + * 0b001..LPCG will be ON in RUN mode, OFF in WAIT/STOP/SUSPEND mode. + * 0b010..LPCG will be ON in RUN/WAIT mode, OFF in STOP/SUSPEND mode. + * 0b011..LPCG will be ON in RUN/WAIT/STOP mode, OFF in SUSPEND mode. + * 0b100..LPCG will be ON in RUN/WAIT/STOP/SUSPEND mode. + */ +#define CCM_LPCG_LPM0_LPM_SETTING_D4(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_LPM0_LPM_SETTING_D4_SHIFT)) & CCM_LPCG_LPM0_LPM_SETTING_D4_MASK) + +#define CCM_LPCG_LPM0_LPM_SETTING_D5_MASK (0x700000U) +#define CCM_LPCG_LPM0_LPM_SETTING_D5_SHIFT (20U) +/*! LPM_SETTING_D5 + * 0b000..LPCG will be OFF in any CPU mode. + * 0b001..LPCG will be ON in RUN mode, OFF in WAIT/STOP/SUSPEND mode. + * 0b010..LPCG will be ON in RUN/WAIT mode, OFF in STOP/SUSPEND mode. + * 0b011..LPCG will be ON in RUN/WAIT/STOP mode, OFF in SUSPEND mode. + * 0b100..LPCG will be ON in RUN/WAIT/STOP/SUSPEND mode. + */ +#define CCM_LPCG_LPM0_LPM_SETTING_D5(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_LPM0_LPM_SETTING_D5_SHIFT)) & CCM_LPCG_LPM0_LPM_SETTING_D5_MASK) + +#define CCM_LPCG_LPM0_LPM_SETTING_D6_MASK (0x7000000U) +#define CCM_LPCG_LPM0_LPM_SETTING_D6_SHIFT (24U) +/*! LPM_SETTING_D6 + * 0b000..LPCG will be OFF in any CPU mode. + * 0b001..LPCG will be ON in RUN mode, OFF in WAIT/STOP/SUSPEND mode. + * 0b010..LPCG will be ON in RUN/WAIT mode, OFF in STOP/SUSPEND mode. + * 0b011..LPCG will be ON in RUN/WAIT/STOP mode, OFF in SUSPEND mode. + * 0b100..LPCG will be ON in RUN/WAIT/STOP/SUSPEND mode. + */ +#define CCM_LPCG_LPM0_LPM_SETTING_D6(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_LPM0_LPM_SETTING_D6_SHIFT)) & CCM_LPCG_LPM0_LPM_SETTING_D6_MASK) + +#define CCM_LPCG_LPM0_LPM_SETTING_D7_MASK (0x70000000U) +#define CCM_LPCG_LPM0_LPM_SETTING_D7_SHIFT (28U) +/*! LPM_SETTING_D7 + * 0b000..LPCG will be OFF in any CPU mode. + * 0b001..LPCG will be ON in RUN mode, OFF in WAIT/STOP/SUSPEND mode. + * 0b010..LPCG will be ON in RUN/WAIT mode, OFF in STOP/SUSPEND mode. + * 0b011..LPCG will be ON in RUN/WAIT/STOP mode, OFF in SUSPEND mode. + * 0b100..LPCG will be ON in RUN/WAIT/STOP/SUSPEND mode. + */ +#define CCM_LPCG_LPM0_LPM_SETTING_D7(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_LPM0_LPM_SETTING_D7_SHIFT)) & CCM_LPCG_LPM0_LPM_SETTING_D7_MASK) +/*! @} */ + +/* The count of CCM_LPCG_LPM0 */ +#define CCM_LPCG_LPM0_COUNT (127U) + +/*! @name LPCG_LPM1 - LPCG low power mode setting */ +/*! @{ */ + +#define CCM_LPCG_LPM1_LPM_SETTING_D8_MASK (0x7U) +#define CCM_LPCG_LPM1_LPM_SETTING_D8_SHIFT (0U) +/*! LPM_SETTING_D8 + * 0b000..LPCG will be OFF in any CPU mode. + * 0b001..LPCG will be ON in RUN mode, OFF in WAIT/STOP/SUSPEND mode. + * 0b010..LPCG will be ON in RUN/WAIT mode, OFF in STOP/SUSPEND mode. + * 0b011..LPCG will be ON in RUN/WAIT/STOP mode, OFF in SUSPEND mode. + * 0b100..LPCG will be ON in RUN/WAIT/STOP/SUSPEND mode. + */ +#define CCM_LPCG_LPM1_LPM_SETTING_D8(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_LPM1_LPM_SETTING_D8_SHIFT)) & CCM_LPCG_LPM1_LPM_SETTING_D8_MASK) + +#define CCM_LPCG_LPM1_LPM_SETTING_D9_MASK (0x70U) +#define CCM_LPCG_LPM1_LPM_SETTING_D9_SHIFT (4U) +/*! LPM_SETTING_D9 + * 0b000..LPCG will be OFF in any CPU mode. + * 0b001..LPCG will be ON in RUN mode, OFF in WAIT/STOP/SUSPEND mode. + * 0b010..LPCG will be ON in RUN/WAIT mode, OFF in STOP/SUSPEND mode. + * 0b011..LPCG will be ON in RUN/WAIT/STOP mode, OFF in SUSPEND mode. + * 0b100..LPCG will be ON in RUN/WAIT/STOP/SUSPEND mode. + */ +#define CCM_LPCG_LPM1_LPM_SETTING_D9(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_LPM1_LPM_SETTING_D9_SHIFT)) & CCM_LPCG_LPM1_LPM_SETTING_D9_MASK) + +#define CCM_LPCG_LPM1_LPM_SETTING_D10_MASK (0x700U) +#define CCM_LPCG_LPM1_LPM_SETTING_D10_SHIFT (8U) +/*! LPM_SETTING_D10 + * 0b000..LPCG will be OFF in any CPU mode. + * 0b001..LPCG will be ON in RUN mode, OFF in WAIT/STOP/SUSPEND mode. + * 0b010..LPCG will be ON in RUN/WAIT mode, OFF in STOP/SUSPEND mode. + * 0b011..LPCG will be ON in RUN/WAIT/STOP mode, OFF in SUSPEND mode. + * 0b100..LPCG will be ON in RUN/WAIT/STOP/SUSPEND mode. + */ +#define CCM_LPCG_LPM1_LPM_SETTING_D10(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_LPM1_LPM_SETTING_D10_SHIFT)) & CCM_LPCG_LPM1_LPM_SETTING_D10_MASK) + +#define CCM_LPCG_LPM1_LPM_SETTING_D11_MASK (0x7000U) +#define CCM_LPCG_LPM1_LPM_SETTING_D11_SHIFT (12U) +/*! LPM_SETTING_D11 + * 0b000..LPCG will be OFF in any CPU mode. + * 0b001..LPCG will be ON in RUN mode, OFF in WAIT/STOP/SUSPEND mode. + * 0b010..LPCG will be ON in RUN/WAIT mode, OFF in STOP/SUSPEND mode. + * 0b011..LPCG will be ON in RUN/WAIT/STOP mode, OFF in SUSPEND mode. + * 0b100..LPCG will be ON in RUN/WAIT/STOP/SUSPEND mode. + */ +#define CCM_LPCG_LPM1_LPM_SETTING_D11(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_LPM1_LPM_SETTING_D11_SHIFT)) & CCM_LPCG_LPM1_LPM_SETTING_D11_MASK) + +#define CCM_LPCG_LPM1_LPM_SETTING_D12_MASK (0x70000U) +#define CCM_LPCG_LPM1_LPM_SETTING_D12_SHIFT (16U) +/*! LPM_SETTING_D12 + * 0b000..LPCG will be OFF in any CPU mode. + * 0b001..LPCG will be ON in RUN mode, OFF in WAIT/STOP/SUSPEND mode. + * 0b010..LPCG will be ON in RUN/WAIT mode, OFF in STOP/SUSPEND mode. + * 0b011..LPCG will be ON in RUN/WAIT/STOP mode, OFF in SUSPEND mode. + * 0b100..LPCG will be ON in RUN/WAIT/STOP/SUSPEND mode. + */ +#define CCM_LPCG_LPM1_LPM_SETTING_D12(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_LPM1_LPM_SETTING_D12_SHIFT)) & CCM_LPCG_LPM1_LPM_SETTING_D12_MASK) + +#define CCM_LPCG_LPM1_LPM_SETTING_D13_MASK (0x700000U) +#define CCM_LPCG_LPM1_LPM_SETTING_D13_SHIFT (20U) +/*! LPM_SETTING_D13 + * 0b000..LPCG will be OFF in any CPU mode. + * 0b001..LPCG will be ON in RUN mode, OFF in WAIT/STOP/SUSPEND mode. + * 0b010..LPCG will be ON in RUN/WAIT mode, OFF in STOP/SUSPEND mode. + * 0b011..LPCG will be ON in RUN/WAIT/STOP mode, OFF in SUSPEND mode. + * 0b100..LPCG will be ON in RUN/WAIT/STOP/SUSPEND mode. + */ +#define CCM_LPCG_LPM1_LPM_SETTING_D13(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_LPM1_LPM_SETTING_D13_SHIFT)) & CCM_LPCG_LPM1_LPM_SETTING_D13_MASK) + +#define CCM_LPCG_LPM1_LPM_SETTING_D14_MASK (0x7000000U) +#define CCM_LPCG_LPM1_LPM_SETTING_D14_SHIFT (24U) +/*! LPM_SETTING_D14 + * 0b000..LPCG will be OFF in any CPU mode. + * 0b001..LPCG will be ON in RUN mode, OFF in WAIT/STOP/SUSPEND mode. + * 0b010..LPCG will be ON in RUN/WAIT mode, OFF in STOP/SUSPEND mode. + * 0b011..LPCG will be ON in RUN/WAIT/STOP mode, OFF in SUSPEND mode. + * 0b100..LPCG will be ON in RUN/WAIT/STOP/SUSPEND mode. + */ +#define CCM_LPCG_LPM1_LPM_SETTING_D14(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_LPM1_LPM_SETTING_D14_SHIFT)) & CCM_LPCG_LPM1_LPM_SETTING_D14_MASK) + +#define CCM_LPCG_LPM1_LPM_SETTING_D15_MASK (0x70000000U) +#define CCM_LPCG_LPM1_LPM_SETTING_D15_SHIFT (28U) +/*! LPM_SETTING_D15 + * 0b000..LPCG will be OFF in any CPU mode. + * 0b001..LPCG will be ON in RUN mode, OFF in WAIT/STOP/SUSPEND mode. + * 0b010..LPCG will be ON in RUN/WAIT mode, OFF in STOP/SUSPEND mode. + * 0b011..LPCG will be ON in RUN/WAIT/STOP mode, OFF in SUSPEND mode. + * 0b100..LPCG will be ON in RUN/WAIT/STOP/SUSPEND mode. + */ +#define CCM_LPCG_LPM1_LPM_SETTING_D15(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_LPM1_LPM_SETTING_D15_SHIFT)) & CCM_LPCG_LPM1_LPM_SETTING_D15_MASK) +/*! @} */ + +/* The count of CCM_LPCG_LPM1 */ +#define CCM_LPCG_LPM1_COUNT (127U) + +/*! @name LPCG_LPM_CUR - LPM setting of current CPU domain */ +/*! @{ */ + +#define CCM_LPCG_LPM_CUR_LPM_SETTING_CUR_MASK (0x7U) +#define CCM_LPCG_LPM_CUR_LPM_SETTING_CUR_SHIFT (0U) +/*! LPM_SETTING_CUR - LPM SETTING of current CPU DOMAIN */ +#define CCM_LPCG_LPM_CUR_LPM_SETTING_CUR(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_LPM_CUR_LPM_SETTING_CUR_SHIFT)) & CCM_LPCG_LPM_CUR_LPM_SETTING_CUR_MASK) +/*! @} */ + +/* The count of CCM_LPCG_LPM_CUR */ +#define CCM_LPCG_LPM_CUR_COUNT (127U) + +/*! @name LPCG_STATUS0 - LPCG working status */ +/*! @{ */ + +#define CCM_LPCG_STATUS0_ON_MASK (0x1U) +#define CCM_LPCG_STATUS0_ON_SHIFT (0U) +/*! ON - LPCG work status + * 0b0..LPCG is OFF. + * 0b1..LPCG is ON. + */ +#define CCM_LPCG_STATUS0_ON(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_STATUS0_ON_SHIFT)) & CCM_LPCG_STATUS0_ON_MASK) +/*! @} */ + +/* The count of CCM_LPCG_STATUS0 */ +#define CCM_LPCG_STATUS0_COUNT (127U) + +/*! @name LPCG_STATUS1 - LPCG domain status */ +/*! @{ */ + +#define CCM_LPCG_STATUS1_DOMAIN_ACTIVE_MASK (0xFFFFU) +#define CCM_LPCG_STATUS1_DOMAIN_ACTIVE_SHIFT (0U) +/*! DOMAIN_ACTIVE - Domain active */ +#define CCM_LPCG_STATUS1_DOMAIN_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_STATUS1_DOMAIN_ACTIVE_SHIFT)) & CCM_LPCG_STATUS1_DOMAIN_ACTIVE_MASK) + +#define CCM_LPCG_STATUS1_DOMAIN_ENABLE_MASK (0xFFFF0000U) +#define CCM_LPCG_STATUS1_DOMAIN_ENABLE_SHIFT (16U) +/*! DOMAIN_ENABLE - Domain enable */ +#define CCM_LPCG_STATUS1_DOMAIN_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_STATUS1_DOMAIN_ENABLE_SHIFT)) & CCM_LPCG_STATUS1_DOMAIN_ENABLE_MASK) +/*! @} */ + +/* The count of CCM_LPCG_STATUS1 */ +#define CCM_LPCG_STATUS1_COUNT (127U) + +/*! @name LPCG_AUTHEN - LPCG access control */ +/*! @{ */ + +#define CCM_LPCG_AUTHEN_CPULPM_MODE_MASK (0x4U) +#define CCM_LPCG_AUTHEN_CPULPM_MODE_SHIFT (2U) +/*! CPULPM_MODE - CPULPM mode enable + * 0b0..Disable CPULPM mode, this LPCG is in Direct Control mode. + * 0b1..Enable CPULPM mode, this LPCG is in CPULPM mode. + */ +#define CCM_LPCG_AUTHEN_CPULPM_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_AUTHEN_CPULPM_MODE_SHIFT)) & CCM_LPCG_AUTHEN_CPULPM_MODE_MASK) + +#define CCM_LPCG_AUTHEN_LOCK_MODE_MASK (0x80U) +#define CCM_LPCG_AUTHEN_LOCK_MODE_SHIFT (7U) +/*! LOCK_MODE + * 0b0..CPULPM_MODE is not locked. + * 0b1..CPULPM_MODE is locked. + */ +#define CCM_LPCG_AUTHEN_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_AUTHEN_LOCK_MODE_SHIFT)) & CCM_LPCG_AUTHEN_LOCK_MODE_MASK) + +#define CCM_LPCG_AUTHEN_TZ_USER_MASK (0x100U) +#define CCM_LPCG_AUTHEN_TZ_USER_SHIFT (8U) +/*! TZ_USER - User access permission + * 0b0..LPCG settings cannot be changed in user mode. + * 0b1..LPCG settings can be changed in user mode. + */ +#define CCM_LPCG_AUTHEN_TZ_USER(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_AUTHEN_TZ_USER_SHIFT)) & CCM_LPCG_AUTHEN_TZ_USER_MASK) + +#define CCM_LPCG_AUTHEN_TZ_NS_MASK (0x200U) +#define CCM_LPCG_AUTHEN_TZ_NS_SHIFT (9U) +/*! TZ_NS - Non-secure access permission + * 0b0..Cannot be changed in Non-secure mode. + * 0b1..Can be changed in Non-secure mode. + */ +#define CCM_LPCG_AUTHEN_TZ_NS(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_AUTHEN_TZ_NS_SHIFT)) & CCM_LPCG_AUTHEN_TZ_NS_MASK) + +#define CCM_LPCG_AUTHEN_LOCK_TZ_MASK (0x800U) +#define CCM_LPCG_AUTHEN_LOCK_TZ_SHIFT (11U) +/*! LOCK_TZ - Lock TrustZone settings + * 0b0..TrustZone settings is not locked. + * 0b1..TrustZone settings is locked. + */ +#define CCM_LPCG_AUTHEN_LOCK_TZ(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_AUTHEN_LOCK_TZ_SHIFT)) & CCM_LPCG_AUTHEN_LOCK_TZ_MASK) + +#define CCM_LPCG_AUTHEN_LOCK_LIST_MASK (0x8000U) +#define CCM_LPCG_AUTHEN_LOCK_LIST_SHIFT (15U) +/*! LOCK_LIST - Lock white list + * 0b0..Whitelist is not locked. + * 0b1..Whitelist is locked. + */ +#define CCM_LPCG_AUTHEN_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_AUTHEN_LOCK_LIST_SHIFT)) & CCM_LPCG_AUTHEN_LOCK_LIST_MASK) + +#define CCM_LPCG_AUTHEN_WHITE_LIST_MASK (0xFFFF0000U) +#define CCM_LPCG_AUTHEN_WHITE_LIST_SHIFT (16U) +/*! WHITE_LIST - Whitelist */ +#define CCM_LPCG_AUTHEN_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_AUTHEN_WHITE_LIST_SHIFT)) & CCM_LPCG_AUTHEN_WHITE_LIST_MASK) +/*! @} */ + +/* The count of CCM_LPCG_AUTHEN */ +#define CCM_LPCG_AUTHEN_COUNT (127U) + + +/*! + * @} + */ /* end of group CCM_Register_Masks */ + + +/* CCM - Peripheral instance base addresses */ +/** Peripheral CCM_CTRL base address */ +#define CCM_CTRL_BASE (0x44450000u) +/** Peripheral CCM_CTRL base pointer */ +extern CCM_Type* CCM_CTRL; +/** Array initializer of CCM peripheral base addresses */ +#define CCM_BASE_ADDRS { CCM_CTRL_BASE } +/** Array initializer of CCM peripheral base pointers */ +#define CCM_BASE_PTRS { CCM_CTRL } + +/*! + * @} + */ /* end of group CCM_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- DDRC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup DDRC_Peripheral_Access_Layer DDRC Peripheral Access Layer + * @{ + */ + +/** DDRC - Register Layout Typedef */ +typedef struct { + struct { /* offset: 0x0, array step: 0x8 */ + __IO uint32_t CS_BNDS; /**< Rank 0 Memory Bounds..Rank 1 Memory Bounds, array offset: 0x0, array step: 0x8 */ + uint8_t RESERVED_0[4]; + } CS_BNDS[2]; + uint8_t RESERVED_0[16]; + __IO uint32_t REMAP_0A; /**< Remap Region 0A Configuration, offset: 0x20 */ + __IO uint32_t REMAP_0B; /**< Remap Region 0B Configuration, offset: 0x24 */ + __IO uint32_t REMAP_1A; /**< Remap Region 1A Configuration, offset: 0x28 */ + __IO uint32_t REMAP_1B; /**< Remap Region 1B Configuration, offset: 0x2C */ + __IO uint32_t REMAP_2A; /**< Remap Region 2A Configuration, offset: 0x30 */ + __IO uint32_t REMAP_2B; /**< Remap Region 2B Configuration, offset: 0x34 */ + __IO uint32_t REMAP_3A; /**< Remap Region 3A Configuration, offset: 0x38 */ + __IO uint32_t REMAP_3B; /**< Remap Region 3B Configuration, offset: 0x3C */ + __IO uint32_t DDR_ADDR_DEC_0; /**< DDRC Address Decode 0, offset: 0x40 */ + __IO uint32_t DDR_ADDR_DEC_1; /**< DDRC Address Decode 1, offset: 0x44 */ + __IO uint32_t DDR_ADDR_DEC_2; /**< DDRC Address Decode 2, offset: 0x48 */ + __IO uint32_t DDR_ADDR_DEC_3; /**< DDRC Address Decode 3, offset: 0x4C */ + __IO uint32_t DDR_ADDR_DEC_4; /**< DDRC Address Decode 4, offset: 0x50 */ + __IO uint32_t DDR_ADDR_DEC_5; /**< DDRC Address Decode 5, offset: 0x54 */ + __IO uint32_t DDR_ADDR_DEC_6; /**< DDRC Address Decode 6, offset: 0x58 */ + __IO uint32_t DDR_ADDR_DEC_7; /**< DDRC Address Decode 7, offset: 0x5C */ + __IO uint32_t DDR_ADDR_DEC_8; /**< DDRC Address Decode 8, offset: 0x60 */ + __IO uint32_t DDR_ADDR_DEC_9; /**< DDRC Address Decode 9, offset: 0x64 */ + uint8_t RESERVED_1[24]; + __IO uint32_t CS_CONFIG[2]; /**< Rank 0 Configuration..Rank 1 Configuration, array offset: 0x80, array step: 0x4 */ + uint8_t RESERVED_2[120]; + __IO uint32_t TIMING_CFG_3; /**< DDR SDRAM Timing Configuration 3, offset: 0x100 */ + __IO uint32_t TIMING_CFG_0; /**< DDR SDRAM Timing Configuration 0, offset: 0x104 */ + __IO uint32_t TIMING_CFG_1; /**< DDR SDRAM Timing Configuration 1, offset: 0x108 */ + __IO uint32_t TIMING_CFG_2; /**< DDR SDRAM Timing Configuration 2, offset: 0x10C */ + __IO uint32_t DDR_SDRAM_CFG; /**< DDR SDRAM Control Configuration, offset: 0x110 */ + __IO uint32_t DDR_SDRAM_CFG_2; /**< DDR SDRAM Control Configuration 2, offset: 0x114 */ + uint8_t RESERVED_3[8]; + __IO uint32_t DDR_SDRAM_MD_CNTL; /**< DDR SDRAM Mode Control, offset: 0x120 */ + __IO uint32_t DDR_SDRAM_INTERVAL; /**< DDR SDRAM Interval Configuration, offset: 0x124 */ + __IO uint32_t DDR_DATA_INIT; /**< DDR SDRAM Data Initialization, offset: 0x128 */ + uint8_t RESERVED_4[52]; + __IO uint32_t TIMING_CFG_4; /**< DDR SDRAM Timing Configuration 4, offset: 0x160 */ + uint8_t RESERVED_5[8]; + __IO uint32_t TIMING_CFG_7; /**< DDR SDRAM Timing Configuration 7, offset: 0x16C */ + __IO uint32_t DDR_ZQ_CNTL; /**< DDR SDRAM ZQ Calibration Control, offset: 0x170 */ + uint8_t RESERVED_6[8]; + __IO uint32_t DDR_SR_CNTR; /**< DDR SDRAM Self-Refresh Counter, offset: 0x17C */ + uint8_t RESERVED_7[208]; + __IO uint32_t TIMING_CFG_8; /**< DDR SDRAM Timing Configuration 8, offset: 0x250 */ + __IO uint32_t TIMING_CFG_9; /**< DDR SDRAM timing configuration 9, offset: 0x254 */ + __IO uint32_t TIMING_CFG_10; /**< DDR SDRAM Timing Configuration 10, offset: 0x258 */ + __IO uint32_t TIMING_CFG_11; /**< DDR SDRAM Timing Configuration 11, offset: 0x25C */ + __IO uint32_t DDR_SDRAM_CFG_3; /**< DDR SDRAM Control Configuration 3, offset: 0x260 */ + __IO uint32_t DDR_SDRAM_CFG_4; /**< DDR SDRAM Control Configuration 4, offset: 0x264 */ + uint8_t RESERVED_8[88]; + __I uint32_t DDR_SDRAM_REF_RATE; /**< DDR Refresh Rate, offset: 0x2C0 */ + uint8_t RESERVED_9[60]; + __IO uint32_t TIMING_CFG_12; /**< DDR SDRAM Timing Configuration 12, offset: 0x300 */ + __IO uint32_t TIMING_CFG_13; /**< DDR SDRAM Timing Configuration 13, offset: 0x304 */ + __IO uint32_t TIMING_CFG_14; /**< DDR SDRAM Timing Configuration 14, offset: 0x308 */ + uint8_t RESERVED_10[1268]; + __IO uint32_t TX_CFG_1; /**< Transaction Configuration Register 1, offset: 0x800 */ + uint8_t RESERVED_11[800]; + __IO uint32_t DDRDSR_2; /**< DDR SDRAM Debug Status 2, offset: 0xB24 */ + uint8_t RESERVED_12[208]; + __I uint32_t DDR_IP_REV1; /**< DDRC Revision 1, offset: 0xBF8 */ + uint8_t RESERVED_13[260]; + __IO uint32_t DDR_MTCR; /**< DDR SDRAM Memory Test Control, offset: 0xD00 */ + uint8_t RESERVED_14[28]; + __IO uint32_t DDR_MTP[10]; /**< DDR SDRAM Memory Test Pattern n, array offset: 0xD20, array step: 0x4 */ + uint8_t RESERVED_15[24]; + __IO uint32_t DDR_MT_ST_EXT_ADDR; /**< DDR SDRAM Memory Test Start Extended Address, offset: 0xD60 */ + __IO uint32_t DDR_MT_ST_ADDR; /**< DDR SDRAM Memory Test Start Address, offset: 0xD64 */ + __IO uint32_t DDR_MT_END_EXT_ADDR; /**< DDR SDRAM Memory Test End Extended Address, offset: 0xD68 */ + __IO uint32_t DDR_MT_END_ADDR; /**< DDR SDRAM Memory Test End Address, offset: 0xD6C */ + uint8_t RESERVED_16[144]; + __IO uint32_t PMGC0; /**< Performance Monitor Global Control, offset: 0xE00 */ + uint8_t RESERVED_17[12]; + __IO uint32_t PMLCA0; /**< Performance Monitor Local Control A0, offset: 0xE10 */ + __IO uint32_t PMLCB0; /**< Performance Monitor Local Control B0, offset: 0xE14 */ + __IO uint32_t PMC0A; /**< PMC 0a, offset: 0xE18 */ + __IO uint32_t PMC0B; /**< PMC 0b, offset: 0xE1C */ + __IO uint32_t PMLCA1; /**< Performance Monitor Local Control A, offset: 0xE20 */ + __IO uint32_t PMLCB1; /**< Performance Monitor Local Control B, offset: 0xE24 */ + __IO uint32_t PMC1; /**< Performance Monitor Counter, offset: 0xE28 */ + uint8_t RESERVED_18[4]; + __IO uint32_t PMLCA2; /**< Performance Monitor Local Control A, offset: 0xE30 */ + __IO uint32_t PMLCB2; /**< Performance Monitor Local Control B, offset: 0xE34 */ + __IO uint32_t PMC2; /**< Performance Monitor Counter, offset: 0xE38 */ + uint8_t RESERVED_19[4]; + __IO uint32_t PMLCA3; /**< Performance Monitor Local Control A, offset: 0xE40 */ + __IO uint32_t PMLCB3; /**< Performance Monitor Local Control B, offset: 0xE44 */ + __IO uint32_t PMC3; /**< Performance Monitor Counter, offset: 0xE48 */ + uint8_t RESERVED_20[4]; + __IO uint32_t PMLCA4; /**< Performance Monitor Local Control A, offset: 0xE50 */ + __IO uint32_t PMLCB4; /**< Performance Monitor Local Control B, offset: 0xE54 */ + __IO uint32_t PMC4; /**< Performance Monitor Counter, offset: 0xE58 */ + uint8_t RESERVED_21[4]; + __IO uint32_t PMLCA5; /**< Performance Monitor Local Control A, offset: 0xE60 */ + __IO uint32_t PMLCB5; /**< Performance Monitor Local Control B, offset: 0xE64 */ + __IO uint32_t PMC5; /**< Performance Monitor Counter, offset: 0xE68 */ + uint8_t RESERVED_22[4]; + __IO uint32_t PMLCA6; /**< Performance Monitor Local Control A, offset: 0xE70 */ + __IO uint32_t PMLCB6; /**< Performance Monitor Local Control B, offset: 0xE74 */ + __IO uint32_t PMC6; /**< Performance Monitor Counter, offset: 0xE78 */ + uint8_t RESERVED_23[4]; + __IO uint32_t PMLCA7; /**< Performance Monitor Local Control A, offset: 0xE80 */ + __IO uint32_t PMLCB7; /**< Performance Monitor Local Control B, offset: 0xE84 */ + __IO uint32_t PMC7; /**< Performance Monitor Counter, offset: 0xE88 */ + uint8_t RESERVED_24[4]; + __IO uint32_t PMLCA8; /**< Performance Monitor Local Control A, offset: 0xE90 */ + __IO uint32_t PMLCB8; /**< Performance Monitor Local Control B, offset: 0xE94 */ + __IO uint32_t PMC8; /**< Performance Monitor Counter, offset: 0xE98 */ + uint8_t RESERVED_25[4]; + __IO uint32_t PMLCA9; /**< Performance Monitor Local Control A, offset: 0xEA0 */ + __IO uint32_t PMLCB9; /**< Performance Monitor Local Control B, offset: 0xEA4 */ + __IO uint32_t PMC9; /**< Performance Monitor Counter, offset: 0xEA8 */ + uint8_t RESERVED_26[4]; + __IO uint32_t PMLCA10; /**< Performance Monitor Local Control A, offset: 0xEB0 */ + __IO uint32_t PMLCB10; /**< Performance Monitor Local Control B, offset: 0xEB4 */ + __IO uint32_t PMC10; /**< Performance Monitor Counter, offset: 0xEB8 */ + uint8_t RESERVED_27[324]; + __IO uint32_t ERR_EN; /**< Error Enable, offset: 0x1000 */ + uint8_t RESERVED_28[252]; + __IO uint32_t DATA_ERR_INJECT_HI; /**< Memory Data Path Error Injection Mask High, offset: 0x1100 */ + __IO uint32_t DATA_ERR_INJECT_LO; /**< Memory Data Path Error Injection Mask Low, offset: 0x1104 */ + __IO uint32_t ERR_INJECT; /**< Memory Data Path Error Injection Mask ECC, offset: 0x1108 */ + __IO uint32_t ADDR_ERR_INJ; /**< Address Error Inject, offset: 0x110C */ + uint8_t RESERVED_29[8]; + __IO uint32_t CAPTURE_EXT_DATA_HI; /**< Memory Extended Data Path Read Capture High, offset: 0x1118 */ + __IO uint32_t CAPTURE_EXT_DATA_LO; /**< Memory Extended Data Path Read Capture Low, offset: 0x111C */ + __IO uint32_t CAPTURE_DATA_HI; /**< Memory Data Path Read Capture High, offset: 0x1120 */ + __IO uint32_t CAPTURE_DATA_LO; /**< Memory Data Path Read Capture Low, offset: 0x1124 */ + __IO uint32_t CAPTURE_ECC; /**< Memory Data Path Read Capture ECC, offset: 0x1128 */ + uint8_t RESERVED_30[20]; + __IO uint32_t ERR_DETECT; /**< Memory Error Detect, offset: 0x1140 */ + __IO uint32_t ERR_DISABLE; /**< Memory Error Disable, offset: 0x1144 */ + __IO uint32_t ERR_INT_EN; /**< Memory Error Interrupt Enable, offset: 0x1148 */ + __IO uint32_t CAPTURE_ATTRIBUTES; /**< Memory Error Attributes Capture, offset: 0x114C */ + __IO uint32_t CAPTURE_ADDRESS; /**< Memory Error Address Capture, offset: 0x1150 */ + __IO uint32_t CAPTURE_EXT_ADDRESS; /**< Memory Error Extended Address Capture, offset: 0x1154 */ + __IO uint32_t ERR_SBE; /**< Single-Bit ECC Memory Error Management, offset: 0x1158 */ + uint8_t RESERVED_31[228]; + __IO uint32_t ECC_REG_0; /**< ECC Region 0 Configuration, offset: 0x1240 */ + __IO uint32_t ECC_REG_1; /**< ECC Region 1 Configuration, offset: 0x1244 */ + __IO uint32_t ECC_REG_2; /**< ECC Region 2 Configuration, offset: 0x1248 */ + __IO uint32_t ECC_REG_3; /**< ECC Region 3 Configuration, offset: 0x124C */ + __IO uint32_t ECC_REG_4; /**< ECC Region 4 Configuration, offset: 0x1250 */ + __IO uint32_t ECC_REG_5; /**< ECC Region 5 Configuration, offset: 0x1254 */ + __IO uint32_t ECC_REG_6; /**< ECC Region 6 Configuration, offset: 0x1258 */ + __IO uint32_t ECC_REG_7; /**< ECC Region 7 Configuration, offset: 0x125C */ +} DDRC_Type; + +/* ---------------------------------------------------------------------------- + -- DDRC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup DDRC_Register_Masks DDRC Register Masks + * @{ + */ + +/*! @name CS_BNDS - Rank 0 Memory Bounds..Rank 1 Memory Bounds */ +/*! @{ */ + +#define DDRC_CS_BNDS_EA_MASK (0xFFFFU) +#define DDRC_CS_BNDS_EA_SHIFT (0U) +/*! EA - Ending Address */ +#define DDRC_CS_BNDS_EA(x) (((uint32_t)(((uint32_t)(x)) << DDRC_CS_BNDS_EA_SHIFT)) & DDRC_CS_BNDS_EA_MASK) + +#define DDRC_CS_BNDS_SA_MASK (0xFFFF0000U) +#define DDRC_CS_BNDS_SA_SHIFT (16U) +/*! SA - Starting Address */ +#define DDRC_CS_BNDS_SA(x) (((uint32_t)(((uint32_t)(x)) << DDRC_CS_BNDS_SA_SHIFT)) & DDRC_CS_BNDS_SA_MASK) +/*! @} */ + +/* The count of DDRC_CS_BNDS */ +#define DDRC_CS_BNDS_COUNT (2U) + +/*! @name REMAP_0A - Remap Region 0A Configuration */ +/*! @{ */ + +#define DDRC_REMAP_0A_REG_0_REMAP_ADDR_MASK (0xFFFU) +#define DDRC_REMAP_0A_REG_0_REMAP_ADDR_SHIFT (0U) +/*! REG_0_REMAP_ADDR - Region 0 Remap Starting Address */ +#define DDRC_REMAP_0A_REG_0_REMAP_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REMAP_0A_REG_0_REMAP_ADDR_SHIFT)) & DDRC_REMAP_0A_REG_0_REMAP_ADDR_MASK) + +#define DDRC_REMAP_0A_REG_0_REMAP_EN_MASK (0x80000000U) +#define DDRC_REMAP_0A_REG_0_REMAP_EN_SHIFT (31U) +/*! REG_0_REMAP_EN - Region 0 Remap Enable + * 0b0..Disables + * 0b1..Enables + */ +#define DDRC_REMAP_0A_REG_0_REMAP_EN(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REMAP_0A_REG_0_REMAP_EN_SHIFT)) & DDRC_REMAP_0A_REG_0_REMAP_EN_MASK) +/*! @} */ + +/*! @name REMAP_0B - Remap Region 0B Configuration */ +/*! @{ */ + +#define DDRC_REMAP_0B_REG_0_EA_MASK (0xFFFU) +#define DDRC_REMAP_0B_REG_0_EA_SHIFT (0U) +/*! REG_0_EA - Region 0 Ending Address */ +#define DDRC_REMAP_0B_REG_0_EA(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REMAP_0B_REG_0_EA_SHIFT)) & DDRC_REMAP_0B_REG_0_EA_MASK) + +#define DDRC_REMAP_0B_REG_0_SA_MASK (0xFFF0000U) +#define DDRC_REMAP_0B_REG_0_SA_SHIFT (16U) +/*! REG_0_SA - Region 0 Starting Address */ +#define DDRC_REMAP_0B_REG_0_SA(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REMAP_0B_REG_0_SA_SHIFT)) & DDRC_REMAP_0B_REG_0_SA_MASK) +/*! @} */ + +/*! @name REMAP_1A - Remap Region 1A Configuration */ +/*! @{ */ + +#define DDRC_REMAP_1A_REG_1_REMAP_ADDR_MASK (0xFFFU) +#define DDRC_REMAP_1A_REG_1_REMAP_ADDR_SHIFT (0U) +/*! REG_1_REMAP_ADDR - Region 1 Remap Starting Address */ +#define DDRC_REMAP_1A_REG_1_REMAP_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REMAP_1A_REG_1_REMAP_ADDR_SHIFT)) & DDRC_REMAP_1A_REG_1_REMAP_ADDR_MASK) + +#define DDRC_REMAP_1A_REG_1_REMAP_EN_MASK (0x80000000U) +#define DDRC_REMAP_1A_REG_1_REMAP_EN_SHIFT (31U) +/*! REG_1_REMAP_EN - Region 1 Remap Enable + * 0b0..Disables + * 0b1..Enables + */ +#define DDRC_REMAP_1A_REG_1_REMAP_EN(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REMAP_1A_REG_1_REMAP_EN_SHIFT)) & DDRC_REMAP_1A_REG_1_REMAP_EN_MASK) +/*! @} */ + +/*! @name REMAP_1B - Remap Region 1B Configuration */ +/*! @{ */ + +#define DDRC_REMAP_1B_REG_1_EA_MASK (0xFFFU) +#define DDRC_REMAP_1B_REG_1_EA_SHIFT (0U) +/*! REG_1_EA - Region 1 Ending Address */ +#define DDRC_REMAP_1B_REG_1_EA(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REMAP_1B_REG_1_EA_SHIFT)) & DDRC_REMAP_1B_REG_1_EA_MASK) + +#define DDRC_REMAP_1B_REG_1_SA_MASK (0xFFF0000U) +#define DDRC_REMAP_1B_REG_1_SA_SHIFT (16U) +/*! REG_1_SA - Region 1 Starting Address */ +#define DDRC_REMAP_1B_REG_1_SA(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REMAP_1B_REG_1_SA_SHIFT)) & DDRC_REMAP_1B_REG_1_SA_MASK) +/*! @} */ + +/*! @name REMAP_2A - Remap Region 2A Configuration */ +/*! @{ */ + +#define DDRC_REMAP_2A_REG_2_REMAP_ADDR_MASK (0xFFFU) +#define DDRC_REMAP_2A_REG_2_REMAP_ADDR_SHIFT (0U) +/*! REG_2_REMAP_ADDR - Region 2 Remap Starting Address */ +#define DDRC_REMAP_2A_REG_2_REMAP_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REMAP_2A_REG_2_REMAP_ADDR_SHIFT)) & DDRC_REMAP_2A_REG_2_REMAP_ADDR_MASK) + +#define DDRC_REMAP_2A_REG_2_REMAP_EN_MASK (0x80000000U) +#define DDRC_REMAP_2A_REG_2_REMAP_EN_SHIFT (31U) +/*! REG_2_REMAP_EN - Region 2 Remap Enable + * 0b0..Disables + * 0b1..Enables + */ +#define DDRC_REMAP_2A_REG_2_REMAP_EN(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REMAP_2A_REG_2_REMAP_EN_SHIFT)) & DDRC_REMAP_2A_REG_2_REMAP_EN_MASK) +/*! @} */ + +/*! @name REMAP_2B - Remap Region 2B Configuration */ +/*! @{ */ + +#define DDRC_REMAP_2B_REG_2_EA_MASK (0xFFFU) +#define DDRC_REMAP_2B_REG_2_EA_SHIFT (0U) +/*! REG_2_EA - Region 2 Ending Address */ +#define DDRC_REMAP_2B_REG_2_EA(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REMAP_2B_REG_2_EA_SHIFT)) & DDRC_REMAP_2B_REG_2_EA_MASK) + +#define DDRC_REMAP_2B_REG_2_SA_MASK (0xFFF0000U) +#define DDRC_REMAP_2B_REG_2_SA_SHIFT (16U) +/*! REG_2_SA - Region 2 Starting Address */ +#define DDRC_REMAP_2B_REG_2_SA(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REMAP_2B_REG_2_SA_SHIFT)) & DDRC_REMAP_2B_REG_2_SA_MASK) +/*! @} */ + +/*! @name REMAP_3A - Remap Region 3A Configuration */ +/*! @{ */ + +#define DDRC_REMAP_3A_REG_3_REMAP_ADDR_MASK (0xFFFU) +#define DDRC_REMAP_3A_REG_3_REMAP_ADDR_SHIFT (0U) +/*! REG_3_REMAP_ADDR - Region 3 Remap Starting Address */ +#define DDRC_REMAP_3A_REG_3_REMAP_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REMAP_3A_REG_3_REMAP_ADDR_SHIFT)) & DDRC_REMAP_3A_REG_3_REMAP_ADDR_MASK) + +#define DDRC_REMAP_3A_REG_3_REMAP_EN_MASK (0x80000000U) +#define DDRC_REMAP_3A_REG_3_REMAP_EN_SHIFT (31U) +/*! REG_3_REMAP_EN - Region 3 Remap Enable + * 0b0..Disables + * 0b1..Enables + */ +#define DDRC_REMAP_3A_REG_3_REMAP_EN(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REMAP_3A_REG_3_REMAP_EN_SHIFT)) & DDRC_REMAP_3A_REG_3_REMAP_EN_MASK) +/*! @} */ + +/*! @name REMAP_3B - Remap Region 3B Configuration */ +/*! @{ */ + +#define DDRC_REMAP_3B_REG_3_EA_MASK (0xFFFU) +#define DDRC_REMAP_3B_REG_3_EA_SHIFT (0U) +/*! REG_3_EA - Region 3 Ending Address */ +#define DDRC_REMAP_3B_REG_3_EA(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REMAP_3B_REG_3_EA_SHIFT)) & DDRC_REMAP_3B_REG_3_EA_MASK) + +#define DDRC_REMAP_3B_REG_3_SA_MASK (0xFFF0000U) +#define DDRC_REMAP_3B_REG_3_SA_SHIFT (16U) +/*! REG_3_SA - Region 3 Starting Address */ +#define DDRC_REMAP_3B_REG_3_SA(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REMAP_3B_REG_3_SA_SHIFT)) & DDRC_REMAP_3B_REG_3_SA_MASK) +/*! @} */ + +/*! @name DDR_ADDR_DEC_0 - DDRC Address Decode 0 */ +/*! @{ */ + +#define DDRC_DDR_ADDR_DEC_0_ROW14_OVRD_MASK (0xFCU) +#define DDRC_DDR_ADDR_DEC_0_ROW14_OVRD_SHIFT (2U) +/*! ROW14_OVRD - Row 14 Override */ +#define DDRC_DDR_ADDR_DEC_0_ROW14_OVRD(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_ADDR_DEC_0_ROW14_OVRD_SHIFT)) & DDRC_DDR_ADDR_DEC_0_ROW14_OVRD_MASK) + +#define DDRC_DDR_ADDR_DEC_0_ROW15_OVRD_MASK (0xFC00U) +#define DDRC_DDR_ADDR_DEC_0_ROW15_OVRD_SHIFT (10U) +/*! ROW15_OVRD - Row 15 Override */ +#define DDRC_DDR_ADDR_DEC_0_ROW15_OVRD(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_ADDR_DEC_0_ROW15_OVRD_SHIFT)) & DDRC_DDR_ADDR_DEC_0_ROW15_OVRD_MASK) + +#define DDRC_DDR_ADDR_DEC_0_ROW16_OVRD_MASK (0xFC0000U) +#define DDRC_DDR_ADDR_DEC_0_ROW16_OVRD_SHIFT (18U) +/*! ROW16_OVRD - Row 16 Override */ +#define DDRC_DDR_ADDR_DEC_0_ROW16_OVRD(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_ADDR_DEC_0_ROW16_OVRD_SHIFT)) & DDRC_DDR_ADDR_DEC_0_ROW16_OVRD_MASK) + +#define DDRC_DDR_ADDR_DEC_0_ROW17_OVRD_MASK (0xFC000000U) +#define DDRC_DDR_ADDR_DEC_0_ROW17_OVRD_SHIFT (26U) +/*! ROW17_OVRD - Row 17 Override */ +#define DDRC_DDR_ADDR_DEC_0_ROW17_OVRD(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_ADDR_DEC_0_ROW17_OVRD_SHIFT)) & DDRC_DDR_ADDR_DEC_0_ROW17_OVRD_MASK) +/*! @} */ + +/*! @name DDR_ADDR_DEC_1 - DDRC Address Decode 1 */ +/*! @{ */ + +#define DDRC_DDR_ADDR_DEC_1_ROW10_OVRD_MASK (0xFCU) +#define DDRC_DDR_ADDR_DEC_1_ROW10_OVRD_SHIFT (2U) +/*! ROW10_OVRD - Row 10 Override */ +#define DDRC_DDR_ADDR_DEC_1_ROW10_OVRD(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_ADDR_DEC_1_ROW10_OVRD_SHIFT)) & DDRC_DDR_ADDR_DEC_1_ROW10_OVRD_MASK) + +#define DDRC_DDR_ADDR_DEC_1_ROW11_OVRD_MASK (0xFC00U) +#define DDRC_DDR_ADDR_DEC_1_ROW11_OVRD_SHIFT (10U) +/*! ROW11_OVRD - Row 11 Override */ +#define DDRC_DDR_ADDR_DEC_1_ROW11_OVRD(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_ADDR_DEC_1_ROW11_OVRD_SHIFT)) & DDRC_DDR_ADDR_DEC_1_ROW11_OVRD_MASK) + +#define DDRC_DDR_ADDR_DEC_1_ROW12_OVRD_MASK (0xFC0000U) +#define DDRC_DDR_ADDR_DEC_1_ROW12_OVRD_SHIFT (18U) +/*! ROW12_OVRD - Row 12 Override */ +#define DDRC_DDR_ADDR_DEC_1_ROW12_OVRD(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_ADDR_DEC_1_ROW12_OVRD_SHIFT)) & DDRC_DDR_ADDR_DEC_1_ROW12_OVRD_MASK) + +#define DDRC_DDR_ADDR_DEC_1_ROW13_OVRD_MASK (0xFC000000U) +#define DDRC_DDR_ADDR_DEC_1_ROW13_OVRD_SHIFT (26U) +/*! ROW13_OVRD - Row 13 Override */ +#define DDRC_DDR_ADDR_DEC_1_ROW13_OVRD(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_ADDR_DEC_1_ROW13_OVRD_SHIFT)) & DDRC_DDR_ADDR_DEC_1_ROW13_OVRD_MASK) +/*! @} */ + +/*! @name DDR_ADDR_DEC_2 - DDRC Address Decode 2 */ +/*! @{ */ + +#define DDRC_DDR_ADDR_DEC_2_ROW6_OVRD_MASK (0xFCU) +#define DDRC_DDR_ADDR_DEC_2_ROW6_OVRD_SHIFT (2U) +/*! ROW6_OVRD - Row 6 Override */ +#define DDRC_DDR_ADDR_DEC_2_ROW6_OVRD(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_ADDR_DEC_2_ROW6_OVRD_SHIFT)) & DDRC_DDR_ADDR_DEC_2_ROW6_OVRD_MASK) + +#define DDRC_DDR_ADDR_DEC_2_ROW7_OVRD_MASK (0xFC00U) +#define DDRC_DDR_ADDR_DEC_2_ROW7_OVRD_SHIFT (10U) +/*! ROW7_OVRD - Row 7 Override */ +#define DDRC_DDR_ADDR_DEC_2_ROW7_OVRD(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_ADDR_DEC_2_ROW7_OVRD_SHIFT)) & DDRC_DDR_ADDR_DEC_2_ROW7_OVRD_MASK) + +#define DDRC_DDR_ADDR_DEC_2_ROW8_OVRD_MASK (0xFC0000U) +#define DDRC_DDR_ADDR_DEC_2_ROW8_OVRD_SHIFT (18U) +/*! ROW8_OVRD - Row 8 Override */ +#define DDRC_DDR_ADDR_DEC_2_ROW8_OVRD(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_ADDR_DEC_2_ROW8_OVRD_SHIFT)) & DDRC_DDR_ADDR_DEC_2_ROW8_OVRD_MASK) + +#define DDRC_DDR_ADDR_DEC_2_ROW9_OVRD_MASK (0xFC000000U) +#define DDRC_DDR_ADDR_DEC_2_ROW9_OVRD_SHIFT (26U) +/*! ROW9_OVRD - Row 9 Override */ +#define DDRC_DDR_ADDR_DEC_2_ROW9_OVRD(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_ADDR_DEC_2_ROW9_OVRD_SHIFT)) & DDRC_DDR_ADDR_DEC_2_ROW9_OVRD_MASK) +/*! @} */ + +/*! @name DDR_ADDR_DEC_3 - DDRC Address Decode 3 */ +/*! @{ */ + +#define DDRC_DDR_ADDR_DEC_3_ROW2_OVRD_MASK (0xFCU) +#define DDRC_DDR_ADDR_DEC_3_ROW2_OVRD_SHIFT (2U) +/*! ROW2_OVRD - Row 2 Override */ +#define DDRC_DDR_ADDR_DEC_3_ROW2_OVRD(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_ADDR_DEC_3_ROW2_OVRD_SHIFT)) & DDRC_DDR_ADDR_DEC_3_ROW2_OVRD_MASK) + +#define DDRC_DDR_ADDR_DEC_3_ROW3_OVRD_MASK (0xFC00U) +#define DDRC_DDR_ADDR_DEC_3_ROW3_OVRD_SHIFT (10U) +/*! ROW3_OVRD - Row 3 Override */ +#define DDRC_DDR_ADDR_DEC_3_ROW3_OVRD(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_ADDR_DEC_3_ROW3_OVRD_SHIFT)) & DDRC_DDR_ADDR_DEC_3_ROW3_OVRD_MASK) + +#define DDRC_DDR_ADDR_DEC_3_ROW4_OVRD_MASK (0xFC0000U) +#define DDRC_DDR_ADDR_DEC_3_ROW4_OVRD_SHIFT (18U) +/*! ROW4_OVRD - Row 4 Override */ +#define DDRC_DDR_ADDR_DEC_3_ROW4_OVRD(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_ADDR_DEC_3_ROW4_OVRD_SHIFT)) & DDRC_DDR_ADDR_DEC_3_ROW4_OVRD_MASK) + +#define DDRC_DDR_ADDR_DEC_3_ROW5_OVRD_MASK (0xFC000000U) +#define DDRC_DDR_ADDR_DEC_3_ROW5_OVRD_SHIFT (26U) +/*! ROW5_OVRD - Row 5 Override */ +#define DDRC_DDR_ADDR_DEC_3_ROW5_OVRD(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_ADDR_DEC_3_ROW5_OVRD_SHIFT)) & DDRC_DDR_ADDR_DEC_3_ROW5_OVRD_MASK) +/*! @} */ + +/*! @name DDR_ADDR_DEC_4 - DDRC Address Decode 4 */ +/*! @{ */ + +#define DDRC_DDR_ADDR_DEC_4_COL9_OVRD_MASK (0xFCU) +#define DDRC_DDR_ADDR_DEC_4_COL9_OVRD_SHIFT (2U) +/*! COL9_OVRD - Col 9 Override */ +#define DDRC_DDR_ADDR_DEC_4_COL9_OVRD(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_ADDR_DEC_4_COL9_OVRD_SHIFT)) & DDRC_DDR_ADDR_DEC_4_COL9_OVRD_MASK) + +#define DDRC_DDR_ADDR_DEC_4_COL10_OVRD_MASK (0xFC00U) +#define DDRC_DDR_ADDR_DEC_4_COL10_OVRD_SHIFT (10U) +/*! COL10_OVRD - Col 10 Override */ +#define DDRC_DDR_ADDR_DEC_4_COL10_OVRD(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_ADDR_DEC_4_COL10_OVRD_SHIFT)) & DDRC_DDR_ADDR_DEC_4_COL10_OVRD_MASK) + +#define DDRC_DDR_ADDR_DEC_4_ROW0_OVRD_MASK (0xFC0000U) +#define DDRC_DDR_ADDR_DEC_4_ROW0_OVRD_SHIFT (18U) +/*! ROW0_OVRD - Row 0 Override */ +#define DDRC_DDR_ADDR_DEC_4_ROW0_OVRD(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_ADDR_DEC_4_ROW0_OVRD_SHIFT)) & DDRC_DDR_ADDR_DEC_4_ROW0_OVRD_MASK) + +#define DDRC_DDR_ADDR_DEC_4_ROW1_OVRD_MASK (0xFC000000U) +#define DDRC_DDR_ADDR_DEC_4_ROW1_OVRD_SHIFT (26U) +/*! ROW1_OVRD - Row 1 Override */ +#define DDRC_DDR_ADDR_DEC_4_ROW1_OVRD(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_ADDR_DEC_4_ROW1_OVRD_SHIFT)) & DDRC_DDR_ADDR_DEC_4_ROW1_OVRD_MASK) +/*! @} */ + +/*! @name DDR_ADDR_DEC_5 - DDRC Address Decode 5 */ +/*! @{ */ + +#define DDRC_DDR_ADDR_DEC_5_COL5_OVRD_MASK (0xFCU) +#define DDRC_DDR_ADDR_DEC_5_COL5_OVRD_SHIFT (2U) +/*! COL5_OVRD - Col 5 Override */ +#define DDRC_DDR_ADDR_DEC_5_COL5_OVRD(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_ADDR_DEC_5_COL5_OVRD_SHIFT)) & DDRC_DDR_ADDR_DEC_5_COL5_OVRD_MASK) + +#define DDRC_DDR_ADDR_DEC_5_COL6_OVRD_MASK (0xFC00U) +#define DDRC_DDR_ADDR_DEC_5_COL6_OVRD_SHIFT (10U) +/*! COL6_OVRD - Col 6 Override */ +#define DDRC_DDR_ADDR_DEC_5_COL6_OVRD(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_ADDR_DEC_5_COL6_OVRD_SHIFT)) & DDRC_DDR_ADDR_DEC_5_COL6_OVRD_MASK) + +#define DDRC_DDR_ADDR_DEC_5_COL7_OVRD_MASK (0xFC0000U) +#define DDRC_DDR_ADDR_DEC_5_COL7_OVRD_SHIFT (18U) +/*! COL7_OVRD - Col 7 Override */ +#define DDRC_DDR_ADDR_DEC_5_COL7_OVRD(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_ADDR_DEC_5_COL7_OVRD_SHIFT)) & DDRC_DDR_ADDR_DEC_5_COL7_OVRD_MASK) + +#define DDRC_DDR_ADDR_DEC_5_COL8_OVRD_MASK (0xFC000000U) +#define DDRC_DDR_ADDR_DEC_5_COL8_OVRD_SHIFT (26U) +/*! COL8_OVRD - Col 8 Override */ +#define DDRC_DDR_ADDR_DEC_5_COL8_OVRD(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_ADDR_DEC_5_COL8_OVRD_SHIFT)) & DDRC_DDR_ADDR_DEC_5_COL8_OVRD_MASK) +/*! @} */ + +/*! @name DDR_ADDR_DEC_6 - DDRC Address Decode 6 */ +/*! @{ */ + +#define DDRC_DDR_ADDR_DEC_6_COL1_OVRD_MASK (0xFCU) +#define DDRC_DDR_ADDR_DEC_6_COL1_OVRD_SHIFT (2U) +/*! COL1_OVRD - Col 1 Override */ +#define DDRC_DDR_ADDR_DEC_6_COL1_OVRD(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_ADDR_DEC_6_COL1_OVRD_SHIFT)) & DDRC_DDR_ADDR_DEC_6_COL1_OVRD_MASK) + +#define DDRC_DDR_ADDR_DEC_6_COL2_OVRD_MASK (0xFC00U) +#define DDRC_DDR_ADDR_DEC_6_COL2_OVRD_SHIFT (10U) +/*! COL2_OVRD - Col 2 Override */ +#define DDRC_DDR_ADDR_DEC_6_COL2_OVRD(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_ADDR_DEC_6_COL2_OVRD_SHIFT)) & DDRC_DDR_ADDR_DEC_6_COL2_OVRD_MASK) + +#define DDRC_DDR_ADDR_DEC_6_COL3_OVRD_MASK (0xFC0000U) +#define DDRC_DDR_ADDR_DEC_6_COL3_OVRD_SHIFT (18U) +/*! COL3_OVRD - Col 3 Override */ +#define DDRC_DDR_ADDR_DEC_6_COL3_OVRD(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_ADDR_DEC_6_COL3_OVRD_SHIFT)) & DDRC_DDR_ADDR_DEC_6_COL3_OVRD_MASK) + +#define DDRC_DDR_ADDR_DEC_6_COL4_OVRD_MASK (0xFC000000U) +#define DDRC_DDR_ADDR_DEC_6_COL4_OVRD_SHIFT (26U) +/*! COL4_OVRD - Col 4 Override */ +#define DDRC_DDR_ADDR_DEC_6_COL4_OVRD(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_ADDR_DEC_6_COL4_OVRD_SHIFT)) & DDRC_DDR_ADDR_DEC_6_COL4_OVRD_MASK) +/*! @} */ + +/*! @name DDR_ADDR_DEC_7 - DDRC Address Decode 7 */ +/*! @{ */ + +#define DDRC_DDR_ADDR_DEC_7_CID1_OVRD_MASK (0xFCU) +#define DDRC_DDR_ADDR_DEC_7_CID1_OVRD_SHIFT (2U) +/*! CID1_OVRD - CID 1 Override */ +#define DDRC_DDR_ADDR_DEC_7_CID1_OVRD(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_ADDR_DEC_7_CID1_OVRD_SHIFT)) & DDRC_DDR_ADDR_DEC_7_CID1_OVRD_MASK) + +#define DDRC_DDR_ADDR_DEC_7_BA0_OVRD_MASK (0xFC00U) +#define DDRC_DDR_ADDR_DEC_7_BA0_OVRD_SHIFT (10U) +/*! BA0_OVRD - Bank 0 Override */ +#define DDRC_DDR_ADDR_DEC_7_BA0_OVRD(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_ADDR_DEC_7_BA0_OVRD_SHIFT)) & DDRC_DDR_ADDR_DEC_7_BA0_OVRD_MASK) + +#define DDRC_DDR_ADDR_DEC_7_BA1_OVRD_MASK (0xFC0000U) +#define DDRC_DDR_ADDR_DEC_7_BA1_OVRD_SHIFT (18U) +/*! BA1_OVRD - Bank 1 Override */ +#define DDRC_DDR_ADDR_DEC_7_BA1_OVRD(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_ADDR_DEC_7_BA1_OVRD_SHIFT)) & DDRC_DDR_ADDR_DEC_7_BA1_OVRD_MASK) + +#define DDRC_DDR_ADDR_DEC_7_COL0_OVRD_MASK (0xFC000000U) +#define DDRC_DDR_ADDR_DEC_7_COL0_OVRD_SHIFT (26U) +/*! COL0_OVRD - Col 0 Override */ +#define DDRC_DDR_ADDR_DEC_7_COL0_OVRD(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_ADDR_DEC_7_COL0_OVRD_SHIFT)) & DDRC_DDR_ADDR_DEC_7_COL0_OVRD_MASK) +/*! @} */ + +/*! @name DDR_ADDR_DEC_8 - DDRC Address Decode 8 */ +/*! @{ */ + +#define DDRC_DDR_ADDR_DEC_8_BG1_OVRD_MASK (0xFCU) +#define DDRC_DDR_ADDR_DEC_8_BG1_OVRD_SHIFT (2U) +/*! BG1_OVRD - Bank Group 1 Override */ +#define DDRC_DDR_ADDR_DEC_8_BG1_OVRD(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_ADDR_DEC_8_BG1_OVRD_SHIFT)) & DDRC_DDR_ADDR_DEC_8_BG1_OVRD_MASK) + +#define DDRC_DDR_ADDR_DEC_8_CS0_OVRD_MASK (0xFC00U) +#define DDRC_DDR_ADDR_DEC_8_CS0_OVRD_SHIFT (10U) +/*! CS0_OVRD - Interleaved Rank 0 Override */ +#define DDRC_DDR_ADDR_DEC_8_CS0_OVRD(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_ADDR_DEC_8_CS0_OVRD_SHIFT)) & DDRC_DDR_ADDR_DEC_8_CS0_OVRD_MASK) + +#define DDRC_DDR_ADDR_DEC_8_CS1_OVRD_MASK (0xFC0000U) +#define DDRC_DDR_ADDR_DEC_8_CS1_OVRD_SHIFT (18U) +/*! CS1_OVRD - Interleaved Rank 1 Override */ +#define DDRC_DDR_ADDR_DEC_8_CS1_OVRD(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_ADDR_DEC_8_CS1_OVRD_SHIFT)) & DDRC_DDR_ADDR_DEC_8_CS1_OVRD_MASK) + +#define DDRC_DDR_ADDR_DEC_8_CID0_OVRD_MASK (0xFC000000U) +#define DDRC_DDR_ADDR_DEC_8_CID0_OVRD_SHIFT (26U) +/*! CID0_OVRD - CID 0 Override */ +#define DDRC_DDR_ADDR_DEC_8_CID0_OVRD(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_ADDR_DEC_8_CID0_OVRD_SHIFT)) & DDRC_DDR_ADDR_DEC_8_CID0_OVRD_MASK) +/*! @} */ + +/*! @name DDR_ADDR_DEC_9 - DDRC Address Decode 9 */ +/*! @{ */ + +#define DDRC_DDR_ADDR_DEC_9_ADDR_DEC_OVRD_MASK (0x1U) +#define DDRC_DDR_ADDR_DEC_9_ADDR_DEC_OVRD_SHIFT (0U) +/*! ADDR_DEC_OVRD - Address Decode Override */ +#define DDRC_DDR_ADDR_DEC_9_ADDR_DEC_OVRD(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_ADDR_DEC_9_ADDR_DEC_OVRD_SHIFT)) & DDRC_DDR_ADDR_DEC_9_ADDR_DEC_OVRD_MASK) + +#define DDRC_DDR_ADDR_DEC_9_BG0_OVRD_MASK (0xFC000000U) +#define DDRC_DDR_ADDR_DEC_9_BG0_OVRD_SHIFT (26U) +/*! BG0_OVRD - Bank Group 0 Override */ +#define DDRC_DDR_ADDR_DEC_9_BG0_OVRD(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_ADDR_DEC_9_BG0_OVRD_SHIFT)) & DDRC_DDR_ADDR_DEC_9_BG0_OVRD_MASK) +/*! @} */ + +/*! @name CS_CONFIG - Rank 0 Configuration..Rank 1 Configuration */ +/*! @{ */ + +#define DDRC_CS_CONFIG_COL_BITS_CS_MASK (0x7U) +#define DDRC_CS_CONFIG_COL_BITS_CS_SHIFT (0U) +/*! COL_BITS_CS - Column Bits + * 0b000..8 + * 0b001..9 + * 0b010..10 + * 0b011..11 + * 0b111..7 + */ +#define DDRC_CS_CONFIG_COL_BITS_CS(x) (((uint32_t)(((uint32_t)(x)) << DDRC_CS_CONFIG_COL_BITS_CS_SHIFT)) & DDRC_CS_CONFIG_COL_BITS_CS_MASK) + +#define DDRC_CS_CONFIG_BG_BITS_CS_MASK (0x30U) +#define DDRC_CS_CONFIG_BG_BITS_CS_SHIFT (4U) +/*! BG_BITS_CS - Bank Group Bits + * 0b00..0 + * 0b01..Must be set to 1 to enable the 3rd bank address bit for LPDDR4, memories. + * 0b10..Reserved for LPDDR4 + * 0b11..Reserved + */ +#define DDRC_CS_CONFIG_BG_BITS_CS(x) (((uint32_t)(((uint32_t)(x)) << DDRC_CS_CONFIG_BG_BITS_CS_SHIFT)) & DDRC_CS_CONFIG_BG_BITS_CS_MASK) + +#define DDRC_CS_CONFIG_ROW_BITS_CS_MASK (0x700U) +#define DDRC_CS_CONFIG_ROW_BITS_CS_SHIFT (8U) +/*! ROW_BITS_CS - Row Bits + * 0b000..12 + * 0b001..13 + * 0b010..14 + * 0b011..15 + * 0b100..16 + * 0b101..17 + */ +#define DDRC_CS_CONFIG_ROW_BITS_CS(x) (((uint32_t)(((uint32_t)(x)) << DDRC_CS_CONFIG_ROW_BITS_CS_SHIFT)) & DDRC_CS_CONFIG_ROW_BITS_CS_MASK) + +#define DDRC_CS_CONFIG_AP_EN_MASK (0x800000U) +#define DDRC_CS_CONFIG_AP_EN_SHIFT (23U) +/*! AP_EN - Auto-Precharge Enable + * 0b0..Disables + * 0b1..Enables + */ +#define DDRC_CS_CONFIG_AP_EN(x) (((uint32_t)(((uint32_t)(x)) << DDRC_CS_CONFIG_AP_EN_SHIFT)) & DDRC_CS_CONFIG_AP_EN_MASK) + +#define DDRC_CS_CONFIG_CS_EN_MASK (0x80000000U) +#define DDRC_CS_CONFIG_CS_EN_SHIFT (31U) +/*! CS_EN - Rank Enable + * 0b0..Disables + * 0b1..Enables + */ +#define DDRC_CS_CONFIG_CS_EN(x) (((uint32_t)(((uint32_t)(x)) << DDRC_CS_CONFIG_CS_EN_SHIFT)) & DDRC_CS_CONFIG_CS_EN_MASK) +/*! @} */ + +/* The count of DDRC_CS_CONFIG */ +#define DDRC_CS_CONFIG_COUNT (2U) + +/*! @name TIMING_CFG_3 - DDR SDRAM Timing Configuration 3 */ +/*! @{ */ + +#define DDRC_TIMING_CFG_3_EXT_WRTORD_MASK (0x1U) +#define DDRC_TIMING_CFG_3_EXT_WRTORD_SHIFT (0U) +/*! EXT_WRTORD - Extended Write-To-Read Time */ +#define DDRC_TIMING_CFG_3_EXT_WRTORD(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TIMING_CFG_3_EXT_WRTORD_SHIFT)) & DDRC_TIMING_CFG_3_EXT_WRTORD_MASK) + +#define DDRC_TIMING_CFG_3_EXT_ACTTOACT_MASK (0x2U) +#define DDRC_TIMING_CFG_3_EXT_ACTTOACT_SHIFT (1U) +/*! EXT_ACTTOACT - Extended Activate-To-Activate Time */ +#define DDRC_TIMING_CFG_3_EXT_ACTTOACT(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TIMING_CFG_3_EXT_ACTTOACT_SHIFT)) & DDRC_TIMING_CFG_3_EXT_ACTTOACT_MASK) + +#define DDRC_TIMING_CFG_3_EXT_FOUR_ACT_MASK (0x8U) +#define DDRC_TIMING_CFG_3_EXT_FOUR_ACT_SHIFT (3U) +/*! EXT_FOUR_ACT - Extended Four Activate */ +#define DDRC_TIMING_CFG_3_EXT_FOUR_ACT(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TIMING_CFG_3_EXT_FOUR_ACT_SHIFT)) & DDRC_TIMING_CFG_3_EXT_FOUR_ACT_MASK) + +#define DDRC_TIMING_CFG_3_EXT_CKE_PLS_MASK (0x30U) +#define DDRC_TIMING_CFG_3_EXT_CKE_PLS_SHIFT (4U) +/*! EXT_CKE_PLS - Extended MCKE Pulse */ +#define DDRC_TIMING_CFG_3_EXT_CKE_PLS(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TIMING_CFG_3_EXT_CKE_PLS_SHIFT)) & DDRC_TIMING_CFG_3_EXT_CKE_PLS_MASK) + +#define DDRC_TIMING_CFG_3_EXT_WRREC_MASK (0x300U) +#define DDRC_TIMING_CFG_3_EXT_WRREC_SHIFT (8U) +/*! EXT_WRREC - Extended Write Recovery + * 0b11.. + * *..Clock cycles as defined in the description + */ +#define DDRC_TIMING_CFG_3_EXT_WRREC(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TIMING_CFG_3_EXT_WRREC_SHIFT)) & DDRC_TIMING_CFG_3_EXT_WRREC_MASK) + +#define DDRC_TIMING_CFG_3_EXT_WR_LAT_2_MASK (0x800U) +#define DDRC_TIMING_CFG_3_EXT_WR_LAT_2_SHIFT (11U) +/*! EXT_WR_LAT_2 - Extended Write Latency 2 */ +#define DDRC_TIMING_CFG_3_EXT_WR_LAT_2(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TIMING_CFG_3_EXT_WR_LAT_2_SHIFT)) & DDRC_TIMING_CFG_3_EXT_WR_LAT_2_MASK) + +#define DDRC_TIMING_CFG_3_EXT_CASLAT_MASK (0x7000U) +#define DDRC_TIMING_CFG_3_EXT_CASLAT_SHIFT (12U) +/*! EXT_CASLAT - Extended CAS Latency */ +#define DDRC_TIMING_CFG_3_EXT_CASLAT(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TIMING_CFG_3_EXT_CASLAT_SHIFT)) & DDRC_TIMING_CFG_3_EXT_CASLAT_MASK) + +#define DDRC_TIMING_CFG_3_EXT_REFREC_MASK (0x3F0000U) +#define DDRC_TIMING_CFG_3_EXT_REFREC_SHIFT (16U) +/*! EXT_REFREC - Extended Refresh Recovery */ +#define DDRC_TIMING_CFG_3_EXT_REFREC(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TIMING_CFG_3_EXT_REFREC_SHIFT)) & DDRC_TIMING_CFG_3_EXT_REFREC_MASK) + +#define DDRC_TIMING_CFG_3_EXT_ACTTORW_MASK (0xC00000U) +#define DDRC_TIMING_CFG_3_EXT_ACTTORW_SHIFT (22U) +/*! EXT_ACTTORW - Extended Activate To Read Or Write Time */ +#define DDRC_TIMING_CFG_3_EXT_ACTTORW(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TIMING_CFG_3_EXT_ACTTORW_SHIFT)) & DDRC_TIMING_CFG_3_EXT_ACTTORW_MASK) + +#define DDRC_TIMING_CFG_3_EXT_ACTTOPRE_MASK (0x7000000U) +#define DDRC_TIMING_CFG_3_EXT_ACTTOPRE_SHIFT (24U) +/*! EXT_ACTTOPRE - Extended Activate-To-Precharge Time */ +#define DDRC_TIMING_CFG_3_EXT_ACTTOPRE(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TIMING_CFG_3_EXT_ACTTOPRE_SHIFT)) & DDRC_TIMING_CFG_3_EXT_ACTTOPRE_MASK) + +#define DDRC_TIMING_CFG_3_EXT_PRETOACT_MASK (0x30000000U) +#define DDRC_TIMING_CFG_3_EXT_PRETOACT_SHIFT (28U) +/*! EXT_PRETOACT - Extended Precharge-To-Activate Time */ +#define DDRC_TIMING_CFG_3_EXT_PRETOACT(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TIMING_CFG_3_EXT_PRETOACT_SHIFT)) & DDRC_TIMING_CFG_3_EXT_PRETOACT_MASK) +/*! @} */ + +/*! @name TIMING_CFG_0 - DDR SDRAM Timing Configuration 0 */ +/*! @{ */ + +#define DDRC_TIMING_CFG_0_MRS_CYC_MASK (0x3FU) +#define DDRC_TIMING_CFG_0_MRS_CYC_SHIFT (0U) +/*! MRS_CYC - MRW Cycle Time + * 0b000000.. + * *..Clock cycles as defined in the description + */ +#define DDRC_TIMING_CFG_0_MRS_CYC(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TIMING_CFG_0_MRS_CYC_SHIFT)) & DDRC_TIMING_CFG_0_MRS_CYC_MASK) + +#define DDRC_TIMING_CFG_0_EXT_ACT_PD_EXIT_MASK (0x1000U) +#define DDRC_TIMING_CFG_0_EXT_ACT_PD_EXIT_SHIFT (12U) +/*! EXT_ACT_PD_EXIT - Extended Active Power-Down Exit */ +#define DDRC_TIMING_CFG_0_EXT_ACT_PD_EXIT(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TIMING_CFG_0_EXT_ACT_PD_EXIT_SHIFT)) & DDRC_TIMING_CFG_0_EXT_ACT_PD_EXIT_MASK) + +#define DDRC_TIMING_CFG_0_EXT_PRE_PD_EXIT_MASK (0xC000U) +#define DDRC_TIMING_CFG_0_EXT_PRE_PD_EXIT_SHIFT (14U) +/*! EXT_PRE_PD_EXIT - Extended Precharge Power-Down Exit */ +#define DDRC_TIMING_CFG_0_EXT_PRE_PD_EXIT(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TIMING_CFG_0_EXT_PRE_PD_EXIT_SHIFT)) & DDRC_TIMING_CFG_0_EXT_PRE_PD_EXIT_MASK) + +#define DDRC_TIMING_CFG_0_PRE_PD_EXIT_MASK (0xF0000U) +#define DDRC_TIMING_CFG_0_PRE_PD_EXIT_SHIFT (16U) +/*! PRE_PD_EXIT - Precharge Power-Down Exit + * 0b0000.. + * *..Clock cycles as defined in the description + */ +#define DDRC_TIMING_CFG_0_PRE_PD_EXIT(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TIMING_CFG_0_PRE_PD_EXIT_SHIFT)) & DDRC_TIMING_CFG_0_PRE_PD_EXIT_MASK) + +#define DDRC_TIMING_CFG_0_ACT_PD_EXIT_MASK (0xF00000U) +#define DDRC_TIMING_CFG_0_ACT_PD_EXIT_SHIFT (20U) +/*! ACT_PD_EXIT - Active Powerdown Exit + * 0b0000.. + * *..Clock cycles as defined in the description + */ +#define DDRC_TIMING_CFG_0_ACT_PD_EXIT(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TIMING_CFG_0_ACT_PD_EXIT_SHIFT)) & DDRC_TIMING_CFG_0_ACT_PD_EXIT_MASK) + +#define DDRC_TIMING_CFG_0_WWT_MASK (0x3000000U) +#define DDRC_TIMING_CFG_0_WWT_SHIFT (24U) +/*! WWT - Write-To-Write Turnaround To Different Ranks */ +#define DDRC_TIMING_CFG_0_WWT(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TIMING_CFG_0_WWT_SHIFT)) & DDRC_TIMING_CFG_0_WWT_MASK) + +#define DDRC_TIMING_CFG_0_RRT_MASK (0xC000000U) +#define DDRC_TIMING_CFG_0_RRT_SHIFT (26U) +/*! RRT - Read-To-Read Turnaround To Different Ranks */ +#define DDRC_TIMING_CFG_0_RRT(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TIMING_CFG_0_RRT_SHIFT)) & DDRC_TIMING_CFG_0_RRT_MASK) + +#define DDRC_TIMING_CFG_0_WRT_MASK (0x30000000U) +#define DDRC_TIMING_CFG_0_WRT_SHIFT (28U) +/*! WRT - Write-To-Read Turnaround To Different Ranks */ +#define DDRC_TIMING_CFG_0_WRT(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TIMING_CFG_0_WRT_SHIFT)) & DDRC_TIMING_CFG_0_WRT_MASK) + +#define DDRC_TIMING_CFG_0_RWT_MASK (0xC0000000U) +#define DDRC_TIMING_CFG_0_RWT_SHIFT (30U) +/*! RWT - Read-To-Write Turnaround To Different Ranks */ +#define DDRC_TIMING_CFG_0_RWT(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TIMING_CFG_0_RWT_SHIFT)) & DDRC_TIMING_CFG_0_RWT_MASK) +/*! @} */ + +/*! @name TIMING_CFG_1 - DDR SDRAM Timing Configuration 1 */ +/*! @{ */ + +#define DDRC_TIMING_CFG_1_WRTORD_MASK (0xFU) +#define DDRC_TIMING_CFG_1_WRTORD_SHIFT (0U) +/*! WRTORD - Write-To-Read Interval + * 0b0000.. + * *..Clock cycles as defined in the description + */ +#define DDRC_TIMING_CFG_1_WRTORD(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TIMING_CFG_1_WRTORD_SHIFT)) & DDRC_TIMING_CFG_1_WRTORD_MASK) + +#define DDRC_TIMING_CFG_1_ACTTOACT_MASK (0xF0U) +#define DDRC_TIMING_CFG_1_ACTTOACT_SHIFT (4U) +/*! ACTTOACT - Activate-To-Activate Interval + * 0b0000.. + * *..Clock cycles as defined in the description + */ +#define DDRC_TIMING_CFG_1_ACTTOACT(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TIMING_CFG_1_ACTTOACT_SHIFT)) & DDRC_TIMING_CFG_1_ACTTOACT_MASK) + +#define DDRC_TIMING_CFG_1_WRREC_MASK (0xF00U) +#define DDRC_TIMING_CFG_1_WRREC_SHIFT (8U) +/*! WRREC - Write Recovery */ +#define DDRC_TIMING_CFG_1_WRREC(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TIMING_CFG_1_WRREC_SHIFT)) & DDRC_TIMING_CFG_1_WRREC_MASK) + +#define DDRC_TIMING_CFG_1_REFREC_MASK (0xF000U) +#define DDRC_TIMING_CFG_1_REFREC_SHIFT (12U) +/*! REFREC - Refresh Recovery */ +#define DDRC_TIMING_CFG_1_REFREC(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TIMING_CFG_1_REFREC_SHIFT)) & DDRC_TIMING_CFG_1_REFREC_MASK) + +#define DDRC_TIMING_CFG_1_CASLAT_MASK (0xE0000U) +#define DDRC_TIMING_CFG_1_CASLAT_SHIFT (17U) +/*! CASLAT - CAS Latency */ +#define DDRC_TIMING_CFG_1_CASLAT(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TIMING_CFG_1_CASLAT_SHIFT)) & DDRC_TIMING_CFG_1_CASLAT_MASK) + +#define DDRC_TIMING_CFG_1_ACTTORW_MASK (0xF00000U) +#define DDRC_TIMING_CFG_1_ACTTORW_SHIFT (20U) +/*! ACTTORW - Activate To Read Or Write + * 0b0000.. + * *..Clock cycles as defined in the description + */ +#define DDRC_TIMING_CFG_1_ACTTORW(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TIMING_CFG_1_ACTTORW_SHIFT)) & DDRC_TIMING_CFG_1_ACTTORW_MASK) + +#define DDRC_TIMING_CFG_1_ACTTOPRE_MASK (0xF000000U) +#define DDRC_TIMING_CFG_1_ACTTOPRE_SHIFT (24U) +/*! ACTTOPRE - Activate-To-Precharge Time */ +#define DDRC_TIMING_CFG_1_ACTTOPRE(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TIMING_CFG_1_ACTTOPRE_SHIFT)) & DDRC_TIMING_CFG_1_ACTTOPRE_MASK) + +#define DDRC_TIMING_CFG_1_PRETOACT_MASK (0xF0000000U) +#define DDRC_TIMING_CFG_1_PRETOACT_SHIFT (28U) +/*! PRETOACT - Precharge-To-Activate Time + * 0b0000.. + * *..Clock cycles as defined in the description + */ +#define DDRC_TIMING_CFG_1_PRETOACT(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TIMING_CFG_1_PRETOACT_SHIFT)) & DDRC_TIMING_CFG_1_PRETOACT_MASK) +/*! @} */ + +/*! @name TIMING_CFG_2 - DDR SDRAM Timing Configuration 2 */ +/*! @{ */ + +#define DDRC_TIMING_CFG_2_FOUR_ACT_MASK (0x3FU) +#define DDRC_TIMING_CFG_2_FOUR_ACT_SHIFT (0U) +/*! FOUR_ACT - Four Activate */ +#define DDRC_TIMING_CFG_2_FOUR_ACT(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TIMING_CFG_2_FOUR_ACT_SHIFT)) & DDRC_TIMING_CFG_2_FOUR_ACT_MASK) + +#define DDRC_TIMING_CFG_2_CKE_PLS_MASK (0x1C0U) +#define DDRC_TIMING_CFG_2_CKE_PLS_SHIFT (6U) +/*! CKE_PLS - MCKE Pulse */ +#define DDRC_TIMING_CFG_2_CKE_PLS(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TIMING_CFG_2_CKE_PLS_SHIFT)) & DDRC_TIMING_CFG_2_CKE_PLS_MASK) + +#define DDRC_TIMING_CFG_2_RD_TO_PRE_MASK (0x3E000U) +#define DDRC_TIMING_CFG_2_RD_TO_PRE_SHIFT (13U) +/*! RD_TO_PRE - Read-To-Precharge Time + * 0b00000.. + * *..Clock cycles as defined in the description + */ +#define DDRC_TIMING_CFG_2_RD_TO_PRE(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TIMING_CFG_2_RD_TO_PRE_SHIFT)) & DDRC_TIMING_CFG_2_RD_TO_PRE_MASK) + +#define DDRC_TIMING_CFG_2_EXT_WR_LAT_MASK (0x40000U) +#define DDRC_TIMING_CFG_2_EXT_WR_LAT_SHIFT (18U) +/*! EXT_WR_LAT - Extended Write Latency */ +#define DDRC_TIMING_CFG_2_EXT_WR_LAT(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TIMING_CFG_2_EXT_WR_LAT_SHIFT)) & DDRC_TIMING_CFG_2_EXT_WR_LAT_MASK) + +#define DDRC_TIMING_CFG_2_WR_LAT_MASK (0x780000U) +#define DDRC_TIMING_CFG_2_WR_LAT_SHIFT (19U) +/*! WR_LAT - Write Latency */ +#define DDRC_TIMING_CFG_2_WR_LAT(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TIMING_CFG_2_WR_LAT_SHIFT)) & DDRC_TIMING_CFG_2_WR_LAT_MASK) + +#define DDRC_TIMING_CFG_2_DERATE_VAL_MASK (0xF0000000U) +#define DDRC_TIMING_CFG_2_DERATE_VAL_SHIFT (28U) +/*! DERATE_VAL - Derate Value */ +#define DDRC_TIMING_CFG_2_DERATE_VAL(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TIMING_CFG_2_DERATE_VAL_SHIFT)) & DDRC_TIMING_CFG_2_DERATE_VAL_MASK) +/*! @} */ + +/*! @name DDR_SDRAM_CFG - DDR SDRAM Control Configuration */ +/*! @{ */ + +#define DDRC_DDR_SDRAM_CFG_BI_MASK (0x1U) +#define DDRC_DDR_SDRAM_CFG_BI_SHIFT (0U) +/*! BI - Bypass Initialization + * 0b0..Reserved; do not use + * 0b1..Initialization routine is bypassed + */ +#define DDRC_DDR_SDRAM_CFG_BI(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_SDRAM_CFG_BI_SHIFT)) & DDRC_DDR_SDRAM_CFG_BI_MASK) + +#define DDRC_DDR_SDRAM_CFG_MEM_HALT_MASK (0x2U) +#define DDRC_DDR_SDRAM_CFG_MEM_HALT_SHIFT (1U) +/*! MEM_HALT - DDRC Halt + * 0b0..Accepts new transactions + * 0b1..Completes any remaining transactions and remains halted until you write 0 to this field + */ +#define DDRC_DDR_SDRAM_CFG_MEM_HALT(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_SDRAM_CFG_MEM_HALT_SHIFT)) & DDRC_DDR_SDRAM_CFG_MEM_HALT_MASK) + +#define DDRC_DDR_SDRAM_CFG_BA_INTLV_CTL_MASK (0x7F00U) +#define DDRC_DDR_SDRAM_CFG_BA_INTLV_CTL_SHIFT (8U) +/*! BA_INTLV_CTL - Rank Interleaving Control + * 0b0000000..No external ranks are interleaved. + * 0b1000000..External ranks 0 and 1 are interleaved. + */ +#define DDRC_DDR_SDRAM_CFG_BA_INTLV_CTL(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_SDRAM_CFG_BA_INTLV_CTL_SHIFT)) & DDRC_DDR_SDRAM_CFG_BA_INTLV_CTL_MASK) + +#define DDRC_DDR_SDRAM_CFG_DBW_MASK (0x180000U) +#define DDRC_DDR_SDRAM_CFG_DBW_SHIFT (19U) +/*! DBW - DDR SDRAM Data Bus Width + * 0b10..16 bits + */ +#define DDRC_DDR_SDRAM_CFG_DBW(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_SDRAM_CFG_DBW_SHIFT)) & DDRC_DDR_SDRAM_CFG_DBW_MASK) + +#define DDRC_DDR_SDRAM_CFG_DYN_PWR_MASK (0x200000U) +#define DDRC_DDR_SDRAM_CFG_DYN_PWR_SHIFT (21U) +/*! DYN_PWR - Dynamic Power Management + * 0b0..No + * 0b1..Yes + */ +#define DDRC_DDR_SDRAM_CFG_DYN_PWR(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_SDRAM_CFG_DYN_PWR_SHIFT)) & DDRC_DDR_SDRAM_CFG_DYN_PWR_MASK) + +#define DDRC_DDR_SDRAM_CFG_SDRAM_TYPE_MASK (0x7000000U) +#define DDRC_DDR_SDRAM_CFG_SDRAM_TYPE_SHIFT (24U) +/*! SDRAM_TYPE - DDR SDRAM Type + * 0b100..LPDDR4, SDRAM + */ +#define DDRC_DDR_SDRAM_CFG_SDRAM_TYPE(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_SDRAM_CFG_SDRAM_TYPE_SHIFT)) & DDRC_DDR_SDRAM_CFG_SDRAM_TYPE_MASK) + +#define DDRC_DDR_SDRAM_CFG_SREN_MASK (0x40000000U) +#define DDRC_DDR_SDRAM_CFG_SREN_SHIFT (30U) +/*! SREN - Self-Refresh Enable + * 0b0..Disables + * 0b1..Enables + */ +#define DDRC_DDR_SDRAM_CFG_SREN(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_SDRAM_CFG_SREN_SHIFT)) & DDRC_DDR_SDRAM_CFG_SREN_MASK) + +#define DDRC_DDR_SDRAM_CFG_MEM_EN_MASK (0x80000000U) +#define DDRC_DDR_SDRAM_CFG_MEM_EN_SHIFT (31U) +/*! MEM_EN - DDRC Enable + * 0b0..Disables + * 0b1..Enables + */ +#define DDRC_DDR_SDRAM_CFG_MEM_EN(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_SDRAM_CFG_MEM_EN_SHIFT)) & DDRC_DDR_SDRAM_CFG_MEM_EN_MASK) +/*! @} */ + +/*! @name DDR_SDRAM_CFG_2 - DDR SDRAM Control Configuration 2 */ +/*! @{ */ + +#define DDRC_DDR_SDRAM_CFG_2_D_INIT_MASK (0x10U) +#define DDRC_DDR_SDRAM_CFG_2_D_INIT_SHIFT (4U) +/*! D_INIT - DDR SDRAM Data Initialization + * 0b0..No data initialization in progress, and none scheduled + * 0b1..DDRC to initialize the DDR SDRAM after DDRC is enabled + */ +#define DDRC_DDR_SDRAM_CFG_2_D_INIT(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_SDRAM_CFG_2_D_INIT_SHIFT)) & DDRC_DDR_SDRAM_CFG_2_D_INIT_MASK) + +#define DDRC_DDR_SDRAM_CFG_2_NUM_PR_MASK (0xF000U) +#define DDRC_DDR_SDRAM_CFG_2_NUM_PR_SHIFT (12U) +/*! NUM_PR - Number Of Posted Refreshes + * 0b0000, 0b0001..1 + * 0b0010..2 + * 0b0011..3 + * 0b0100..4 + * 0b0101..5 + * 0b0110..6 + * 0b0111..7 + * 0b1000..8 + */ +#define DDRC_DDR_SDRAM_CFG_2_NUM_PR(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_SDRAM_CFG_2_NUM_PR_SHIFT)) & DDRC_DDR_SDRAM_CFG_2_NUM_PR_MASK) + +#define DDRC_DDR_SDRAM_CFG_2_MCK_DIS_MASK (0xF000000U) +#define DDRC_DDR_SDRAM_CFG_2_MCK_DIS_SHIFT (24U) +/*! MCK_DIS - MCK Disable */ +#define DDRC_DDR_SDRAM_CFG_2_MCK_DIS(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_SDRAM_CFG_2_MCK_DIS_SHIFT)) & DDRC_DDR_SDRAM_CFG_2_MCK_DIS_MASK) + +#define DDRC_DDR_SDRAM_CFG_2_FRC_SR_MASK (0x80000000U) +#define DDRC_DDR_SDRAM_CFG_2_FRC_SR_SHIFT (31U) +/*! FRC_SR - Force Self-Refresh + * 0b0..Normal mode + * 0b1..Self-Refresh mode + */ +#define DDRC_DDR_SDRAM_CFG_2_FRC_SR(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_SDRAM_CFG_2_FRC_SR_SHIFT)) & DDRC_DDR_SDRAM_CFG_2_FRC_SR_MASK) +/*! @} */ + +/*! @name DDR_SDRAM_MD_CNTL - DDR SDRAM Mode Control */ +/*! @{ */ + +#define DDRC_DDR_SDRAM_MD_CNTL_MD_VALUE_MASK (0x3FFFFU) +#define DDRC_DDR_SDRAM_MD_CNTL_MD_VALUE_SHIFT (0U) +/*! MD_VALUE - Mode Register Value */ +#define DDRC_DDR_SDRAM_MD_CNTL_MD_VALUE(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_SDRAM_MD_CNTL_MD_VALUE_SHIFT)) & DDRC_DDR_SDRAM_MD_CNTL_MD_VALUE_MASK) + +#define DDRC_DDR_SDRAM_MD_CNTL_CKE_CNTL_MASK (0x300000U) +#define DDRC_DDR_SDRAM_MD_CNTL_CKE_CNTL_SHIFT (20U) +/*! CKE_CNTL - Clock Enable Control + * 0b00..Not forced + * 0b01..Forced to a lower value + * 0b10..Forced to a higher value + * 0b11.. + */ +#define DDRC_DDR_SDRAM_MD_CNTL_CKE_CNTL(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_SDRAM_MD_CNTL_CKE_CNTL_SHIFT)) & DDRC_DDR_SDRAM_MD_CNTL_CKE_CNTL_MASK) + +#define DDRC_DDR_SDRAM_MD_CNTL_SET_PRE_MASK (0x400000U) +#define DDRC_DDR_SDRAM_MD_CNTL_SET_PRE_SHIFT (22U) +/*! SET_PRE - Set Precharge + * 0b0..No + * 0b1..Yes + */ +#define DDRC_DDR_SDRAM_MD_CNTL_SET_PRE(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_SDRAM_MD_CNTL_SET_PRE_SHIFT)) & DDRC_DDR_SDRAM_MD_CNTL_SET_PRE_MASK) + +#define DDRC_DDR_SDRAM_MD_CNTL_SET_REF_MASK (0x800000U) +#define DDRC_DDR_SDRAM_MD_CNTL_SET_REF_SHIFT (23U) +/*! SET_REF - Set Refresh + * 0b0..No + * 0b1..Yes + */ +#define DDRC_DDR_SDRAM_MD_CNTL_SET_REF(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_SDRAM_MD_CNTL_SET_REF_SHIFT)) & DDRC_DDR_SDRAM_MD_CNTL_SET_REF_MASK) + +#define DDRC_DDR_SDRAM_MD_CNTL_MD_SEL_MASK (0xF000000U) +#define DDRC_DDR_SDRAM_MD_CNTL_MD_SEL_SHIFT (24U) +/*! MD_SEL - Mode Register Select + * 0b0000..MR + * 0b0001..EMR + * 0b0010..EMR2 + * 0b0011..EMR3 + */ +#define DDRC_DDR_SDRAM_MD_CNTL_MD_SEL(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_SDRAM_MD_CNTL_MD_SEL_SHIFT)) & DDRC_DDR_SDRAM_MD_CNTL_MD_SEL_MASK) + +#define DDRC_DDR_SDRAM_MD_CNTL_CS_SEL_MASK (0x70000000U) +#define DDRC_DDR_SDRAM_MD_CNTL_CS_SEL_SHIFT (28U) +/*! CS_SEL - Select Rank + * 0b000..0 + * 0b001..1 + * 0b100..0 and 1 + */ +#define DDRC_DDR_SDRAM_MD_CNTL_CS_SEL(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_SDRAM_MD_CNTL_CS_SEL_SHIFT)) & DDRC_DDR_SDRAM_MD_CNTL_CS_SEL_MASK) + +#define DDRC_DDR_SDRAM_MD_CNTL_MD_EN_MASK (0x80000000U) +#define DDRC_DDR_SDRAM_MD_CNTL_MD_EN_SHIFT (31U) +/*! MD_EN - Mode Enable + * 0b0..Does not need to be issued + * 0b1..Valid data contained in the register ready to be issued as an MRW command + */ +#define DDRC_DDR_SDRAM_MD_CNTL_MD_EN(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_SDRAM_MD_CNTL_MD_EN_SHIFT)) & DDRC_DDR_SDRAM_MD_CNTL_MD_EN_MASK) +/*! @} */ + +/*! @name DDR_SDRAM_INTERVAL - DDR SDRAM Interval Configuration */ +/*! @{ */ + +#define DDRC_DDR_SDRAM_INTERVAL_BSTOPRE_MASK (0x3FFFU) +#define DDRC_DDR_SDRAM_INTERVAL_BSTOPRE_SHIFT (0U) +/*! BSTOPRE - Precharge Interval */ +#define DDRC_DDR_SDRAM_INTERVAL_BSTOPRE(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_SDRAM_INTERVAL_BSTOPRE_SHIFT)) & DDRC_DDR_SDRAM_INTERVAL_BSTOPRE_MASK) + +#define DDRC_DDR_SDRAM_INTERVAL_REFINT_MASK (0xFFFF0000U) +#define DDRC_DDR_SDRAM_INTERVAL_REFINT_SHIFT (16U) +/*! REFINT - Refresh Interval */ +#define DDRC_DDR_SDRAM_INTERVAL_REFINT(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_SDRAM_INTERVAL_REFINT_SHIFT)) & DDRC_DDR_SDRAM_INTERVAL_REFINT_MASK) +/*! @} */ + +/*! @name DDR_DATA_INIT - DDR SDRAM Data Initialization */ +/*! @{ */ + +#define DDRC_DDR_DATA_INIT_INIT_VALUE_MASK (0xFFFFFFFFU) +#define DDRC_DDR_DATA_INIT_INIT_VALUE_SHIFT (0U) +/*! INIT_VALUE - Initialization Value */ +#define DDRC_DDR_DATA_INIT_INIT_VALUE(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_DATA_INIT_INIT_VALUE_SHIFT)) & DDRC_DDR_DATA_INIT_INIT_VALUE_MASK) +/*! @} */ + +/*! @name TIMING_CFG_4 - DDR SDRAM Timing Configuration 4 */ +/*! @{ */ + +#define DDRC_TIMING_CFG_4_DLL_LOCK_MASK (0x3U) +#define DDRC_TIMING_CFG_4_DLL_LOCK_SHIFT (0U) +/*! DLL_LOCK - DDR SDRAM DLL Lock Time + * 0b10..1024 clocks + * 0b11..2048 clocks + */ +#define DDRC_TIMING_CFG_4_DLL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TIMING_CFG_4_DLL_LOCK_SHIFT)) & DDRC_TIMING_CFG_4_DLL_LOCK_MASK) + +#define DDRC_TIMING_CFG_4_EXT_REFINT_MASK (0x10U) +#define DDRC_TIMING_CFG_4_EXT_REFINT_SHIFT (4U) +/*! EXT_REFINT - Extended Refresh Interval + * 0b0..0 + * 0b1..65,536 + */ +#define DDRC_TIMING_CFG_4_EXT_REFINT(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TIMING_CFG_4_EXT_REFINT_SHIFT)) & DDRC_TIMING_CFG_4_EXT_REFINT_MASK) + +#define DDRC_TIMING_CFG_4_EXT_WWT_MASK (0x300U) +#define DDRC_TIMING_CFG_4_EXT_WWT_SHIFT (8U) +/*! EXT_WWT - Extended Write-To-Write Turnaround */ +#define DDRC_TIMING_CFG_4_EXT_WWT(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TIMING_CFG_4_EXT_WWT_SHIFT)) & DDRC_TIMING_CFG_4_EXT_WWT_MASK) + +#define DDRC_TIMING_CFG_4_EXT_RRT_MASK (0xC00U) +#define DDRC_TIMING_CFG_4_EXT_RRT_SHIFT (10U) +/*! EXT_RRT - Extended Read-To-Read Turnaround */ +#define DDRC_TIMING_CFG_4_EXT_RRT(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TIMING_CFG_4_EXT_RRT_SHIFT)) & DDRC_TIMING_CFG_4_EXT_RRT_MASK) + +#define DDRC_TIMING_CFG_4_EXT_WRT_MASK (0x3000U) +#define DDRC_TIMING_CFG_4_EXT_WRT_SHIFT (12U) +/*! EXT_WRT - Extended Write-To-Read Turnaround */ +#define DDRC_TIMING_CFG_4_EXT_WRT(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TIMING_CFG_4_EXT_WRT_SHIFT)) & DDRC_TIMING_CFG_4_EXT_WRT_MASK) + +#define DDRC_TIMING_CFG_4_EXT_RWT_MASK (0xC000U) +#define DDRC_TIMING_CFG_4_EXT_RWT_SHIFT (14U) +/*! EXT_RWT - Extended Read-To-Write Turnaround */ +#define DDRC_TIMING_CFG_4_EXT_RWT(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TIMING_CFG_4_EXT_RWT_SHIFT)) & DDRC_TIMING_CFG_4_EXT_RWT_MASK) + +#define DDRC_TIMING_CFG_4_WWT_MASK (0xF0000U) +#define DDRC_TIMING_CFG_4_WWT_SHIFT (16U) +/*! WWT - Write-To-Write Turnaround For Same Rank */ +#define DDRC_TIMING_CFG_4_WWT(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TIMING_CFG_4_WWT_SHIFT)) & DDRC_TIMING_CFG_4_WWT_MASK) + +#define DDRC_TIMING_CFG_4_RRT_MASK (0xF00000U) +#define DDRC_TIMING_CFG_4_RRT_SHIFT (20U) +/*! RRT - Read-To-Read Turnaround For Same Rank */ +#define DDRC_TIMING_CFG_4_RRT(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TIMING_CFG_4_RRT_SHIFT)) & DDRC_TIMING_CFG_4_RRT_MASK) + +#define DDRC_TIMING_CFG_4_WRT_MASK (0xF000000U) +#define DDRC_TIMING_CFG_4_WRT_SHIFT (24U) +/*! WRT - Write-To-Read Turnaround For Same Rank */ +#define DDRC_TIMING_CFG_4_WRT(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TIMING_CFG_4_WRT_SHIFT)) & DDRC_TIMING_CFG_4_WRT_MASK) + +#define DDRC_TIMING_CFG_4_RWT_MASK (0xF0000000U) +#define DDRC_TIMING_CFG_4_RWT_SHIFT (28U) +/*! RWT - Read-To-Write Turnaround For Same Rank */ +#define DDRC_TIMING_CFG_4_RWT(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TIMING_CFG_4_RWT_SHIFT)) & DDRC_TIMING_CFG_4_RWT_MASK) +/*! @} */ + +/*! @name TIMING_CFG_7 - DDR SDRAM Timing Configuration 7 */ +/*! @{ */ + +#define DDRC_TIMING_CFG_7_CKSRX_MASK (0xF00000U) +#define DDRC_TIMING_CFG_7_CKSRX_SHIFT (20U) +/*! CKSRX - Clock After Self-Refresh Exit + * 0b0000, 0b1010..15 + * 0b0001..6 + * 0b0010..7 + * 0b0011..8 + * 0b0100..9 + * 0b0101..10 + * 0b0110..11 + * 0b0111..12 + * 0b1000..13 + * 0b1001..14 + * 0b1011..16 + * 0b1100..17 + * 0b1101..18 + * 0b1110..19 + * 0b1111..32 + */ +#define DDRC_TIMING_CFG_7_CKSRX(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TIMING_CFG_7_CKSRX_SHIFT)) & DDRC_TIMING_CFG_7_CKSRX_MASK) + +#define DDRC_TIMING_CFG_7_CKSRE_MASK (0xF000000U) +#define DDRC_TIMING_CFG_7_CKSRE_SHIFT (24U) +/*! CKSRE - Clock After Self-Refresh Entry + * 0b0000, 0b1010..15 + * 0b0001..6 + * 0b0010..7 + * 0b0011..8 + * 0b0100..9 + * 0b0101..10 + * 0b0110..11 + * 0b0111..12 + * 0b1000..13 + * 0b1001..14 + * 0b1011..16 + * 0b1100..17 + * 0b1101..18 + * 0b1110..19 + * 0b1111..32 + */ +#define DDRC_TIMING_CFG_7_CKSRE(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TIMING_CFG_7_CKSRE_SHIFT)) & DDRC_TIMING_CFG_7_CKSRE_MASK) + +#define DDRC_TIMING_CFG_7_CKE_RST_MASK (0x30000000U) +#define DDRC_TIMING_CFG_7_CKE_RST_SHIFT (28U) +/*! CKE_RST - MCKE Reset Time + * 0b00..200 + * 0b01..256 + * 0b10..512 + * 0b11..4096 + */ +#define DDRC_TIMING_CFG_7_CKE_RST(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TIMING_CFG_7_CKE_RST_SHIFT)) & DDRC_TIMING_CFG_7_CKE_RST_MASK) +/*! @} */ + +/*! @name DDR_ZQ_CNTL - DDR SDRAM ZQ Calibration Control */ +/*! @{ */ + +#define DDRC_DDR_ZQ_CNTL_ZQCS_INT_MASK (0xFU) +#define DDRC_DDR_ZQ_CNTL_ZQCS_INT_SHIFT (0U) +/*! ZQCS_INT - ZQCS Interval + * 0b0000..32 + * 0b0001..64 + * 0b0010..128 + * 0b0011..256 + * 0b0100..512 + * 0b0101..1024 + * 0b0110..2048 + * 0b0111..4096 + * 0b1000..8192 + * 0b1001..16384 + * 0b1010..32768 + * 0b1111..ZQCS calibration disabled + */ +#define DDRC_DDR_ZQ_CNTL_ZQCS_INT(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_ZQ_CNTL_ZQCS_INT_SHIFT)) & DDRC_DDR_ZQ_CNTL_ZQCS_INT_MASK) + +#define DDRC_DDR_ZQ_CNTL_ZQCS_MASK (0xF00U) +#define DDRC_DDR_ZQ_CNTL_ZQCS_SHIFT (8U) +/*! ZQCS - ZQ Calibration Short Time + * 0b0000..1 + * 0b0001..2 + * 0b0010..4 + * 0b0011..8 + * 0b0100..16 + * 0b0101..32 + * 0b0110..64 + * 0b0111..128 + * 0b1000..256 + * 0b1001..512 + */ +#define DDRC_DDR_ZQ_CNTL_ZQCS(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_ZQ_CNTL_ZQCS_SHIFT)) & DDRC_DDR_ZQ_CNTL_ZQCS_MASK) + +#define DDRC_DDR_ZQ_CNTL_ZQOPER_MASK (0xF0000U) +#define DDRC_DDR_ZQ_CNTL_ZQOPER_SHIFT (16U) +/*! ZQOPER - ZQ Calibration Operation Time + * 0b0111..128 + * 0b1000..256 + * 0b1001..512 + * 0b1010..1024 + * 0b1011..2048 + */ +#define DDRC_DDR_ZQ_CNTL_ZQOPER(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_ZQ_CNTL_ZQOPER_SHIFT)) & DDRC_DDR_ZQ_CNTL_ZQOPER_MASK) + +#define DDRC_DDR_ZQ_CNTL_ZQINIT_MASK (0xF000000U) +#define DDRC_DDR_ZQ_CNTL_ZQINIT_SHIFT (24U) +/*! ZQINIT - ZQ Calibration Initialization Time + * 0b0111..128 + * 0b1000..256 + * 0b1001..512 + * 0b1010..1024 + * 0b1011..2048 + */ +#define DDRC_DDR_ZQ_CNTL_ZQINIT(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_ZQ_CNTL_ZQINIT_SHIFT)) & DDRC_DDR_ZQ_CNTL_ZQINIT_MASK) + +#define DDRC_DDR_ZQ_CNTL_ZQ_EN_MASK (0x80000000U) +#define DDRC_DDR_ZQ_CNTL_ZQ_EN_SHIFT (31U) +/*! ZQ_EN - ZQ Calibration Enable + * 0b0..Not used + * 0b1..Used + */ +#define DDRC_DDR_ZQ_CNTL_ZQ_EN(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_ZQ_CNTL_ZQ_EN_SHIFT)) & DDRC_DDR_ZQ_CNTL_ZQ_EN_MASK) +/*! @} */ + +/*! @name DDR_SR_CNTR - DDR SDRAM Self-Refresh Counter */ +/*! @{ */ + +#define DDRC_DDR_SR_CNTR_SR_IT_MASK (0xF0000U) +#define DDRC_DDR_SR_CNTR_SR_IT_SHIFT (16U) +/*! SR_IT - Self-Refresh Idle Threshold */ +#define DDRC_DDR_SR_CNTR_SR_IT(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_SR_CNTR_SR_IT_SHIFT)) & DDRC_DDR_SR_CNTR_SR_IT_MASK) +/*! @} */ + +/*! @name TIMING_CFG_8 - DDR SDRAM Timing Configuration 8 */ +/*! @{ */ + +#define DDRC_TIMING_CFG_8_PRE_ALL_REC_MASK (0x3FU) +#define DDRC_TIMING_CFG_8_PRE_ALL_REC_SHIFT (0U) +/*! PRE_ALL_REC - Precharge All-To-Activate Interval */ +#define DDRC_TIMING_CFG_8_PRE_ALL_REC(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TIMING_CFG_8_PRE_ALL_REC_SHIFT)) & DDRC_TIMING_CFG_8_PRE_ALL_REC_MASK) +/*! @} */ + +/*! @name TIMING_CFG_9 - DDR SDRAM timing configuration 9 */ +/*! @{ */ + +#define DDRC_TIMING_CFG_9_REFTOREF_PB_MASK (0x3FFU) +#define DDRC_TIMING_CFG_9_REFTOREF_PB_SHIFT (0U) +/*! REFTOREF_PB - Refresh-to-refresh interval for per-bank refresh. + * 0b0000000000..disable PB refresh + * 0b0000000001..9 clocks + * 0b0000000010..10 clocks + * 0b1011111110..774 clocks + * 0b1011111111..775 clocks + */ +#define DDRC_TIMING_CFG_9_REFTOREF_PB(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TIMING_CFG_9_REFTOREF_PB_SHIFT)) & DDRC_TIMING_CFG_9_REFTOREF_PB_MASK) + +#define DDRC_TIMING_CFG_9_REFREC_PB_MASK (0x3FF0000U) +#define DDRC_TIMING_CFG_9_REFREC_PB_SHIFT (16U) +/*! REFREC_PB - Refresh Recovery Per-Bank Refresh + * 0b0000000000..8 clocks + * 0b0000000001..9 clocks + * 0b0000000010..10 clocks + * 0b1011111110..774 clocks + * 0b1011111111..775 clocks + */ +#define DDRC_TIMING_CFG_9_REFREC_PB(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TIMING_CFG_9_REFREC_PB_SHIFT)) & DDRC_TIMING_CFG_9_REFREC_PB_MASK) +/*! @} */ + +/*! @name TIMING_CFG_10 - DDR SDRAM Timing Configuration 10 */ +/*! @{ */ + +#define DDRC_TIMING_CFG_10_T_STAB_MASK (0x7FFFU) +#define DDRC_TIMING_CFG_10_T_STAB_SHIFT (0U) +/*! T_STAB - Stabilization Wait Time */ +#define DDRC_TIMING_CFG_10_T_STAB(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TIMING_CFG_10_T_STAB_SHIFT)) & DDRC_TIMING_CFG_10_T_STAB_MASK) +/*! @} */ + +/*! @name TIMING_CFG_11 - DDR SDRAM Timing Configuration 11 */ +/*! @{ */ + +#define DDRC_TIMING_CFG_11_MWWT_MASK (0xFU) +#define DDRC_TIMING_CFG_11_MWWT_SHIFT (0U) +/*! MWWT - Masked Write-To-Write Turnaround (tCCDMW) */ +#define DDRC_TIMING_CFG_11_MWWT(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TIMING_CFG_11_MWWT_SHIFT)) & DDRC_TIMING_CFG_11_MWWT_MASK) + +#define DDRC_TIMING_CFG_11_PRE_TO_PRE_MASK (0xF00U) +#define DDRC_TIMING_CFG_11_PRE_TO_PRE_SHIFT (8U) +/*! PRE_TO_PRE - Precharge-To-Precharge Time + * 0b0000, 0b0100..4 + * 0b0001..1 + * 0b0010..2 + * 0b0011..3 + * 0b0101..5 + * 0b0110..6 + * 0b0111..7 + * 0b1000..8 + * 0b1001..9 + * 0b1010..10 + * 0b1011..11 + * 0b1100..12 + * 0b1101..13 + * 0b1110..14 + * 0b1111..15 + */ +#define DDRC_TIMING_CFG_11_PRE_TO_PRE(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TIMING_CFG_11_PRE_TO_PRE_SHIFT)) & DDRC_TIMING_CFG_11_PRE_TO_PRE_MASK) +/*! @} */ + +/*! @name DDR_SDRAM_CFG_3 - DDR SDRAM Control Configuration 3 */ +/*! @{ */ + +#define DDRC_DDR_SDRAM_CFG_3_SR_FAST_WK_EN_MASK (0x2U) +#define DDRC_DDR_SDRAM_CFG_3_SR_FAST_WK_EN_SHIFT (1U) +/*! SR_FAST_WK_EN - Self Refresh Fast Wakeup Enable + * 0b0..Slow + * 0b1..Fast + */ +#define DDRC_DDR_SDRAM_CFG_3_SR_FAST_WK_EN(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_SDRAM_CFG_3_SR_FAST_WK_EN_SHIFT)) & DDRC_DDR_SDRAM_CFG_3_SR_FAST_WK_EN_MASK) + +#define DDRC_DDR_SDRAM_CFG_3_NON_PWR_2_MASK (0x8U) +#define DDRC_DDR_SDRAM_CFG_3_NON_PWR_2_SHIFT (3U) +/*! NON_PWR_2 - Non Power of 2 Enable + * 0b0..Disables + * 0b1..Enables + */ +#define DDRC_DDR_SDRAM_CFG_3_NON_PWR_2(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_SDRAM_CFG_3_NON_PWR_2_SHIFT)) & DDRC_DDR_SDRAM_CFG_3_NON_PWR_2_MASK) + +#define DDRC_DDR_SDRAM_CFG_3_DYN_REF_RATE_EN_MASK (0x80U) +#define DDRC_DDR_SDRAM_CFG_3_DYN_REF_RATE_EN_SHIFT (7U) +/*! DYN_REF_RATE_EN - Dynamic Refresh Rate Enable + * 0b0..Disables + * 0b1..Enables + */ +#define DDRC_DDR_SDRAM_CFG_3_DYN_REF_RATE_EN(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_SDRAM_CFG_3_DYN_REF_RATE_EN_SHIFT)) & DDRC_DDR_SDRAM_CFG_3_DYN_REF_RATE_EN_MASK) + +#define DDRC_DDR_SDRAM_CFG_3_DRAIN_FOR_SR_MASK (0x800U) +#define DDRC_DDR_SDRAM_CFG_3_DRAIN_FOR_SR_SHIFT (11U) +/*! DRAIN_FOR_SR - Drain Queues For Self-Refresh + * 0b0..Do not drain + * 0b1..Drain + */ +#define DDRC_DDR_SDRAM_CFG_3_DRAIN_FOR_SR(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_SDRAM_CFG_3_DRAIN_FOR_SR_SHIFT)) & DDRC_DDR_SDRAM_CFG_3_DRAIN_FOR_SR_MASK) + +#define DDRC_DDR_SDRAM_CFG_3_DM_CFG_MASK (0x7000U) +#define DDRC_DDR_SDRAM_CFG_3_DM_CFG_SHIFT (12U) +/*! DM_CFG - Data Mask Configuration + * 0b000..Normal data masks based on the settings defined in DDR_SDRAM_CFG[SDRAM_TYPE] + * 0b010..DBI + * 0b011..Neither data masks nor DBI + * 0b100..DBI with data masks + */ +#define DDRC_DDR_SDRAM_CFG_3_DM_CFG(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_SDRAM_CFG_3_DM_CFG_SHIFT)) & DDRC_DDR_SDRAM_CFG_3_DM_CFG_MASK) + +#define DDRC_DDR_SDRAM_CFG_3_DDRC_RST_MASK (0x80000000U) +#define DDRC_DDR_SDRAM_CFG_3_DDRC_RST_SHIFT (31U) +/*! DDRC_RST - DDRC Reset + * 0b0..Operating normally + * 0b1..Undergoing reset + */ +#define DDRC_DDR_SDRAM_CFG_3_DDRC_RST(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_SDRAM_CFG_3_DDRC_RST_SHIFT)) & DDRC_DDR_SDRAM_CFG_3_DDRC_RST_MASK) +/*! @} */ + +/*! @name DDR_SDRAM_CFG_4 - DDR SDRAM Control Configuration 4 */ +/*! @{ */ + +#define DDRC_DDR_SDRAM_CFG_4_FRQCH_RET_MASK (0x1F000U) +#define DDRC_DDR_SDRAM_CFG_4_FRQCH_RET_SHIFT (12U) +/*! FRQCH_RET - Frequency Change and Retention Setup */ +#define DDRC_DDR_SDRAM_CFG_4_FRQCH_RET(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_SDRAM_CFG_4_FRQCH_RET_SHIFT)) & DDRC_DDR_SDRAM_CFG_4_FRQCH_RET_MASK) +/*! @} */ + +/*! @name DDR_SDRAM_REF_RATE - DDR Refresh Rate */ +/*! @{ */ + +#define DDRC_DDR_SDRAM_REF_RATE_REF_RATE_CS1_MASK (0xFFU) +#define DDRC_DDR_SDRAM_REF_RATE_REF_RATE_CS1_SHIFT (0U) +/*! REF_RATE_CS1 - Refresh Rate Rank 1 */ +#define DDRC_DDR_SDRAM_REF_RATE_REF_RATE_CS1(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_SDRAM_REF_RATE_REF_RATE_CS1_SHIFT)) & DDRC_DDR_SDRAM_REF_RATE_REF_RATE_CS1_MASK) + +#define DDRC_DDR_SDRAM_REF_RATE_REF_RATE_CS0_MASK (0xFF00U) +#define DDRC_DDR_SDRAM_REF_RATE_REF_RATE_CS0_SHIFT (8U) +/*! REF_RATE_CS0 - Refresh Rate Rank 0 */ +#define DDRC_DDR_SDRAM_REF_RATE_REF_RATE_CS0(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_SDRAM_REF_RATE_REF_RATE_CS0_SHIFT)) & DDRC_DDR_SDRAM_REF_RATE_REF_RATE_CS0_MASK) +/*! @} */ + +/*! @name TIMING_CFG_12 - DDR SDRAM Timing Configuration 12 */ +/*! @{ */ + +#define DDRC_TIMING_CFG_12_CASLAT_HS_MASK (0x3FU) +#define DDRC_TIMING_CFG_12_CASLAT_HS_SHIFT (0U) +/*! CASLAT_HS - CAS Latency For Half Speed */ +#define DDRC_TIMING_CFG_12_CASLAT_HS(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TIMING_CFG_12_CASLAT_HS_SHIFT)) & DDRC_TIMING_CFG_12_CASLAT_HS_MASK) + +#define DDRC_TIMING_CFG_12_ACTTORW_HS_MASK (0x3F00U) +#define DDRC_TIMING_CFG_12_ACTTORW_HS_SHIFT (8U) +/*! ACTTORW_HS - Activate To Read Or Write For Half Speed + * 0b000000.. + * *..Clock cycles as defined in the description + */ +#define DDRC_TIMING_CFG_12_ACTTORW_HS(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TIMING_CFG_12_ACTTORW_HS_SHIFT)) & DDRC_TIMING_CFG_12_ACTTORW_HS_MASK) + +#define DDRC_TIMING_CFG_12_ACTTOPRE_HS_MASK (0x7F0000U) +#define DDRC_TIMING_CFG_12_ACTTOPRE_HS_SHIFT (16U) +/*! ACTTOPRE_HS - Activate-To-Precharge Time For Half Speed */ +#define DDRC_TIMING_CFG_12_ACTTOPRE_HS(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TIMING_CFG_12_ACTTOPRE_HS_SHIFT)) & DDRC_TIMING_CFG_12_ACTTOPRE_HS_MASK) + +#define DDRC_TIMING_CFG_12_PRETOACT_HS_MASK (0x3F000000U) +#define DDRC_TIMING_CFG_12_PRETOACT_HS_SHIFT (24U) +/*! PRETOACT_HS - Precharge-To-Activate Time For Half Speed + * 0b000000.. + * *..Clock cycles as defined in the description + */ +#define DDRC_TIMING_CFG_12_PRETOACT_HS(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TIMING_CFG_12_PRETOACT_HS_SHIFT)) & DDRC_TIMING_CFG_12_PRETOACT_HS_MASK) +/*! @} */ + +/*! @name TIMING_CFG_13 - DDR SDRAM Timing Configuration 13 */ +/*! @{ */ + +#define DDRC_TIMING_CFG_13_ACTTOACT_HS_MASK (0x1FU) +#define DDRC_TIMING_CFG_13_ACTTOACT_HS_SHIFT (0U) +/*! ACTTOACT_HS - Activate-To-Activate Interval For Half Speed + * 0b00000.. + * *..Clock cycles as defined in the description + */ +#define DDRC_TIMING_CFG_13_ACTTOACT_HS(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TIMING_CFG_13_ACTTOACT_HS_SHIFT)) & DDRC_TIMING_CFG_13_ACTTOACT_HS_MASK) + +#define DDRC_TIMING_CFG_13_WRREC_HS_MASK (0x3F00U) +#define DDRC_TIMING_CFG_13_WRREC_HS_SHIFT (8U) +/*! WRREC_HS - Write Recovery For Half Speed + * 0b000000.. + * *..Clock cycles as defined in the description + */ +#define DDRC_TIMING_CFG_13_WRREC_HS(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TIMING_CFG_13_WRREC_HS_SHIFT)) & DDRC_TIMING_CFG_13_WRREC_HS_MASK) + +#define DDRC_TIMING_CFG_13_REFREC_HS_MASK (0x3FF0000U) +#define DDRC_TIMING_CFG_13_REFREC_HS_SHIFT (16U) +/*! REFREC_HS - Refresh Recovery For Half Speed */ +#define DDRC_TIMING_CFG_13_REFREC_HS(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TIMING_CFG_13_REFREC_HS_SHIFT)) & DDRC_TIMING_CFG_13_REFREC_HS_MASK) +/*! @} */ + +/*! @name TIMING_CFG_14 - DDR SDRAM Timing Configuration 14 */ +/*! @{ */ + +#define DDRC_TIMING_CFG_14_REFINT_HS_MASK (0x1FFFFU) +#define DDRC_TIMING_CFG_14_REFINT_HS_SHIFT (0U) +/*! REFINT_HS - Refresh Interval For Half Speed */ +#define DDRC_TIMING_CFG_14_REFINT_HS(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TIMING_CFG_14_REFINT_HS_SHIFT)) & DDRC_TIMING_CFG_14_REFINT_HS_MASK) + +#define DDRC_TIMING_CFG_14_RD_TO_PRE_HS_MASK (0x7C0000U) +#define DDRC_TIMING_CFG_14_RD_TO_PRE_HS_SHIFT (18U) +/*! RD_TO_PRE_HS - Read-To-Precharge Time For Half Speed + * 0b00000.. + * *..Clock cycles as defined in the description + */ +#define DDRC_TIMING_CFG_14_RD_TO_PRE_HS(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TIMING_CFG_14_RD_TO_PRE_HS_SHIFT)) & DDRC_TIMING_CFG_14_RD_TO_PRE_HS_MASK) + +#define DDRC_TIMING_CFG_14_WRLAT_HS_MASK (0x3F000000U) +#define DDRC_TIMING_CFG_14_WRLAT_HS_SHIFT (24U) +/*! WRLAT_HS - Write Latency For Half Speed */ +#define DDRC_TIMING_CFG_14_WRLAT_HS(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TIMING_CFG_14_WRLAT_HS_SHIFT)) & DDRC_TIMING_CFG_14_WRLAT_HS_MASK) +/*! @} */ + +/*! @name TX_CFG_1 - Transaction Configuration Register 1 */ +/*! @{ */ + +#define DDRC_TX_CFG_1_WWATER_MASK (0xFU) +#define DDRC_TX_CFG_1_WWATER_SHIFT (0U) +/*! WWATER - Write Watermark. */ +#define DDRC_TX_CFG_1_WWATER(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TX_CFG_1_WWATER_SHIFT)) & DDRC_TX_CFG_1_WWATER_MASK) + +#define DDRC_TX_CFG_1_TS_DEPTH_MASK (0xF80U) +#define DDRC_TX_CFG_1_TS_DEPTH_SHIFT (7U) +/*! TS_DEPTH - Transaction Scheduler Depth */ +#define DDRC_TX_CFG_1_TS_DEPTH(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TX_CFG_1_TS_DEPTH_SHIFT)) & DDRC_TX_CFG_1_TS_DEPTH_MASK) +/*! @} */ + +/*! @name DDRDSR_2 - DDR SDRAM Debug Status 2 */ +/*! @{ */ + +#define DDRC_DDRDSR_2_RPD_END_MASK (0x1U) +#define DDRC_DDRDSR_2_RPD_END_SHIFT (0U) +/*! RPD_END - Rapid Clear Of Memory End + * 0b0..Not complete + * 0b1..Complete + */ +#define DDRC_DDRDSR_2_RPD_END(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDRDSR_2_RPD_END_SHIFT)) & DDRC_DDRDSR_2_RPD_END_MASK) + +#define DDRC_DDRDSR_2_RPD_ST_MASK (0x2U) +#define DDRC_DDRDSR_2_RPD_ST_SHIFT (1U) +/*! RPD_ST - Rapid Clear Of Memory Start + * 0b0..Not started + * 0b1..Started + */ +#define DDRC_DDRDSR_2_RPD_ST(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDRDSR_2_RPD_ST_SHIFT)) & DDRC_DDRDSR_2_RPD_ST_MASK) + +#define DDRC_DDRDSR_2_PHY_INIT_CMPLT_MASK (0x4U) +#define DDRC_DDRDSR_2_PHY_INIT_CMPLT_SHIFT (2U) +/*! PHY_INIT_CMPLT - DDR PHY Initialization Complete + * 0b0..Not complete + * 0b1..Complete + */ +#define DDRC_DDRDSR_2_PHY_INIT_CMPLT(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDRDSR_2_PHY_INIT_CMPLT_SHIFT)) & DDRC_DDRDSR_2_PHY_INIT_CMPLT_MASK) + +#define DDRC_DDRDSR_2_NML_MASK (0x40000000U) +#define DDRC_DDRDSR_2_NML_SHIFT (30U) +/*! NML - No Modified Lines + * 0b0..Exist + * 0b1..Do not exist + */ +#define DDRC_DDRDSR_2_NML(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDRDSR_2_NML_SHIFT)) & DDRC_DDRDSR_2_NML_MASK) + +#define DDRC_DDRDSR_2_IDLE_MASK (0x80000000U) +#define DDRC_DDRDSR_2_IDLE_SHIFT (31U) +/*! IDLE - Memory controller idle (read only). + * 0b0..Memory controller is busy. + * 0b1..Memory controller is idle. + */ +#define DDRC_DDRDSR_2_IDLE(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDRDSR_2_IDLE_SHIFT)) & DDRC_DDRDSR_2_IDLE_MASK) +/*! @} */ + +/*! @name DDR_IP_REV1 - DDRC Revision 1 */ +/*! @{ */ + +#define DDRC_DDR_IP_REV1_IP_MN_MASK (0xFFU) +#define DDRC_DDR_IP_REV1_IP_MN_SHIFT (0U) +/*! IP_MN - Minor Revision */ +#define DDRC_DDR_IP_REV1_IP_MN(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_IP_REV1_IP_MN_SHIFT)) & DDRC_DDR_IP_REV1_IP_MN_MASK) + +#define DDRC_DDR_IP_REV1_IP_MJ_MASK (0xFF00U) +#define DDRC_DDR_IP_REV1_IP_MJ_SHIFT (8U) +/*! IP_MJ - Major Revision */ +#define DDRC_DDR_IP_REV1_IP_MJ(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_IP_REV1_IP_MJ_SHIFT)) & DDRC_DDR_IP_REV1_IP_MJ_MASK) + +#define DDRC_DDR_IP_REV1_IP_ID_MASK (0xFFFF0000U) +#define DDRC_DDR_IP_REV1_IP_ID_SHIFT (16U) +/*! IP_ID - IP Block ID */ +#define DDRC_DDR_IP_REV1_IP_ID(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_IP_REV1_IP_ID_SHIFT)) & DDRC_DDR_IP_REV1_IP_ID_MASK) +/*! @} */ + +/*! @name DDR_MTCR - DDR SDRAM Memory Test Control */ +/*! @{ */ + +#define DDRC_DDR_MTCR_MT_STAT_MASK (0x1U) +#define DDRC_DDR_MTCR_MT_STAT_SHIFT (0U) +/*! MT_STAT - Memory Test Status + * 0b0..No fail detected + * 0b1..Data miscompare detected + */ +#define DDRC_DDR_MTCR_MT_STAT(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_MTCR_MT_STAT_SHIFT)) & DDRC_DDR_MTCR_MT_STAT_MASK) + +#define DDRC_DDR_MTCR_MT_ADDR_EN_MASK (0x200U) +#define DDRC_DDR_MTCR_MT_ADDR_EN_SHIFT (9U) +/*! MT_ADDR_EN - Memory Test Address Range Enable + * 0b0..Memory range that the CSn_BNDS registers define + * 0b1..Memory range that the DDR_MT_ST_EXT_ADDR, DDR_MT_ST_ADDR, DDR_MT_END_EXT_ADDR, and DDR_MT_END_ADDR registers define + */ +#define DDRC_DDR_MTCR_MT_ADDR_EN(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_MTCR_MT_ADDR_EN_SHIFT)) & DDRC_DDR_MTCR_MT_ADDR_EN_MASK) + +#define DDRC_DDR_MTCR_MT_TRNARND_MASK (0xF0000U) +#define DDRC_DDR_MTCR_MT_TRNARND_SHIFT (16U) +/*! MT_TRNARND - Memory Test Turnaround + * 0b0000..Entire memory is written to before read transactions are issued. + * 0b0001..Total write and read streams are one transaction each. + * 0b0010..Total write and read streams are two transactions each. + * 0b0011..Total write and read streams are four transactions each. + */ +#define DDRC_DDR_MTCR_MT_TRNARND(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_MTCR_MT_TRNARND_SHIFT)) & DDRC_DDR_MTCR_MT_TRNARND_MASK) + +#define DDRC_DDR_MTCR_MT_TYP_MASK (0x3000000U) +#define DDRC_DDR_MTCR_MT_TYP_SHIFT (24U) +/*! MT_TYP - Memory Test Type + * 0b00..Both writes and reads + * 0b01..Only writes + * 0b10..Only reads + * 0b11..Reserved + */ +#define DDRC_DDR_MTCR_MT_TYP(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_MTCR_MT_TYP_SHIFT)) & DDRC_DDR_MTCR_MT_TYP_MASK) + +#define DDRC_DDR_MTCR_MT_EN_MASK (0x80000000U) +#define DDRC_DDR_MTCR_MT_EN_SHIFT (31U) +/*! MT_EN - Memory Test Enable + * 0b0..Disables + * 0b1..Enables + */ +#define DDRC_DDR_MTCR_MT_EN(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_MTCR_MT_EN_SHIFT)) & DDRC_DDR_MTCR_MT_EN_MASK) +/*! @} */ + +/*! @name DDR_MTP - DDR SDRAM Memory Test Pattern n */ +/*! @{ */ + +#define DDRC_DDR_MTP_DDR_PATT_MASK (0xFFFFFFFFU) +#define DDRC_DDR_MTP_DDR_PATT_SHIFT (0U) +/*! DDR_PATT - DDR SDRAM Pattern */ +#define DDRC_DDR_MTP_DDR_PATT(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_MTP_DDR_PATT_SHIFT)) & DDRC_DDR_MTP_DDR_PATT_MASK) +/*! @} */ + +/* The count of DDRC_DDR_MTP */ +#define DDRC_DDR_MTP_COUNT (10U) + +/*! @name DDR_MT_ST_EXT_ADDR - DDR SDRAM Memory Test Start Extended Address */ +/*! @{ */ + +#define DDRC_DDR_MT_ST_EXT_ADDR_MT_ST_EXT_ADDR_MASK (0xFFU) +#define DDRC_DDR_MT_ST_EXT_ADDR_MT_ST_EXT_ADDR_SHIFT (0U) +/*! MT_ST_EXT_ADDR - Memory Test Start Extended Address */ +#define DDRC_DDR_MT_ST_EXT_ADDR_MT_ST_EXT_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_MT_ST_EXT_ADDR_MT_ST_EXT_ADDR_SHIFT)) & DDRC_DDR_MT_ST_EXT_ADDR_MT_ST_EXT_ADDR_MASK) +/*! @} */ + +/*! @name DDR_MT_ST_ADDR - DDR SDRAM Memory Test Start Address */ +/*! @{ */ + +#define DDRC_DDR_MT_ST_ADDR_MT_ST_ADDR_MASK (0xFFFFFFFFU) +#define DDRC_DDR_MT_ST_ADDR_MT_ST_ADDR_SHIFT (0U) +/*! MT_ST_ADDR - Memory Test Start Address */ +#define DDRC_DDR_MT_ST_ADDR_MT_ST_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_MT_ST_ADDR_MT_ST_ADDR_SHIFT)) & DDRC_DDR_MT_ST_ADDR_MT_ST_ADDR_MASK) +/*! @} */ + +/*! @name DDR_MT_END_EXT_ADDR - DDR SDRAM Memory Test End Extended Address */ +/*! @{ */ + +#define DDRC_DDR_MT_END_EXT_ADDR_MT_END_EXT_ADDR_MASK (0xFFU) +#define DDRC_DDR_MT_END_EXT_ADDR_MT_END_EXT_ADDR_SHIFT (0U) +/*! MT_END_EXT_ADDR - Memory Test End Extended Address */ +#define DDRC_DDR_MT_END_EXT_ADDR_MT_END_EXT_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_MT_END_EXT_ADDR_MT_END_EXT_ADDR_SHIFT)) & DDRC_DDR_MT_END_EXT_ADDR_MT_END_EXT_ADDR_MASK) +/*! @} */ + +/*! @name DDR_MT_END_ADDR - DDR SDRAM Memory Test End Address */ +/*! @{ */ + +#define DDRC_DDR_MT_END_ADDR_MT_END_ADDR_MASK (0xFFFFFFFFU) +#define DDRC_DDR_MT_END_ADDR_MT_END_ADDR_SHIFT (0U) +/*! MT_END_ADDR - Memory Test End Address */ +#define DDRC_DDR_MT_END_ADDR_MT_END_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_MT_END_ADDR_MT_END_ADDR_SHIFT)) & DDRC_DDR_MT_END_ADDR_MT_END_ADDR_MASK) +/*! @} */ + +/*! @name PMGC0 - Performance Monitor Global Control */ +/*! @{ */ + +#define DDRC_PMGC0_FCECE_MASK (0x20000000U) +#define DDRC_PMGC0_FCECE_SHIFT (29U) +/*! FCECE - Freeze Counters On Enabled Condition Or Event + * 0b0..Enabled if PMLCAn[CE] = 1, until an event or condition occurs. + * 0b1..Enabled if PMLCAn[CE] = 1, until an event or condition occurs. At this point, if PMGC0[FAC] = 1, you must write 0 to it. + */ +#define DDRC_PMGC0_FCECE(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMGC0_FCECE_SHIFT)) & DDRC_PMGC0_FCECE_MASK) + +#define DDRC_PMGC0_PMIE_MASK (0x40000000U) +#define DDRC_PMGC0_PMIE_SHIFT (30U) +/*! PMIE - Performance Monitor Interrupt Enable + * 0b0..Disables + * 0b1..Enables + */ +#define DDRC_PMGC0_PMIE(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMGC0_PMIE_SHIFT)) & DDRC_PMGC0_PMIE_MASK) + +#define DDRC_PMGC0_FAC_MASK (0x80000000U) +#define DDRC_PMGC0_FAC_SHIFT (31U) +/*! FAC - Freeze All Counters + * 0b0..Incremented + * 0b1..Not incremented + */ +#define DDRC_PMGC0_FAC(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMGC0_FAC_SHIFT)) & DDRC_PMGC0_FAC_MASK) +/*! @} */ + +/*! @name PMLCA0 - Performance Monitor Local Control A0 */ +/*! @{ */ + +#define DDRC_PMLCA0_CE_MASK (0x4000000U) +#define DDRC_PMLCA0_CE_SHIFT (26U) +/*! CE - Condition Enable + * 0b0..Counter overflow conditions for PMC0n cannot occur (PMC0n cannot cause interrupts or freeze counters) + * 0b1..Counter overflow conditions occur when the most-significant bit of PMC0n is 1 + */ +#define DDRC_PMLCA0_CE(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCA0_CE_SHIFT)) & DDRC_PMLCA0_CE_MASK) + +#define DDRC_PMLCA0_FC_MASK (0x80000000U) +#define DDRC_PMLCA0_FC_SHIFT (31U) +/*! FC - Freeze Counter + * 0b0..Enabled + * 0b1..Disabled + */ +#define DDRC_PMLCA0_FC(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCA0_FC_SHIFT)) & DDRC_PMLCA0_FC_MASK) +/*! @} */ + +/*! @name PMLCB0 - Performance Monitor Local Control B0 */ +/*! @{ */ + +#define DDRC_PMLCB0_TRIGOFFCNTL_MASK (0x30000U) +#define DDRC_PMLCB0_TRIGOFFCNTL_SHIFT (16U) +/*! TRIGOFFCNTL - Trigger-Off Control + * 0b00..Triggering off (no triggering to start) + * 0b01..Trigger on change + * 0b10..Trigger on overflow + * 0b11..Reserved + */ +#define DDRC_PMLCB0_TRIGOFFCNTL(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCB0_TRIGOFFCNTL_SHIFT)) & DDRC_PMLCB0_TRIGOFFCNTL_MASK) + +#define DDRC_PMLCB0_TRIGONCNTL_MASK (0xC0000U) +#define DDRC_PMLCB0_TRIGONCNTL_SHIFT (18U) +/*! TRIGONCNTL - Trigger-On Control + * 0b00..Triggering off (no triggering to start) + * 0b01..Trigger on change + * 0b10..Trigger on overflow + * 0b11..Reserved + */ +#define DDRC_PMLCB0_TRIGONCNTL(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCB0_TRIGONCNTL_SHIFT)) & DDRC_PMLCB0_TRIGONCNTL_MASK) + +#define DDRC_PMLCB0_TRIGOFFSEL_MASK (0xF00000U) +#define DDRC_PMLCB0_TRIGOFFSEL_SHIFT (20U) +/*! TRIGOFFSEL - Trigger-Off Select */ +#define DDRC_PMLCB0_TRIGOFFSEL(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCB0_TRIGOFFSEL_SHIFT)) & DDRC_PMLCB0_TRIGOFFSEL_MASK) + +#define DDRC_PMLCB0_TRIGONSEL_MASK (0x3C000000U) +#define DDRC_PMLCB0_TRIGONSEL_SHIFT (26U) +/*! TRIGONSEL - Trigger-On Select */ +#define DDRC_PMLCB0_TRIGONSEL(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCB0_TRIGONSEL_SHIFT)) & DDRC_PMLCB0_TRIGONSEL_MASK) +/*! @} */ + +/*! @name PMC0A - PMC 0a */ +/*! @{ */ + +#define DDRC_PMC0A_PMC0_MASK (0xFFFFFFFFU) +#define DDRC_PMC0A_PMC0_SHIFT (0U) +/*! PMC0 - Counter 0 */ +#define DDRC_PMC0A_PMC0(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMC0A_PMC0_SHIFT)) & DDRC_PMC0A_PMC0_MASK) +/*! @} */ + +/*! @name PMC0B - PMC 0b */ +/*! @{ */ + +#define DDRC_PMC0B_PMC0_MASK (0xFFFFFFFFU) +#define DDRC_PMC0B_PMC0_SHIFT (0U) +/*! PMC0 - Counter 0 */ +#define DDRC_PMC0B_PMC0(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMC0B_PMC0_SHIFT)) & DDRC_PMC0B_PMC0_MASK) +/*! @} */ + +/*! @name PMLCA1 - Performance Monitor Local Control A */ +/*! @{ */ + +#define DDRC_PMLCA1_BDIST_MASK (0x3FU) +#define DDRC_PMLCA1_BDIST_SHIFT (0U) +/*! BDIST - Burst Distance */ +#define DDRC_PMLCA1_BDIST(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCA1_BDIST_SHIFT)) & DDRC_PMLCA1_BDIST_MASK) + +#define DDRC_PMLCA1_BGRAN_MASK (0x7C0U) +#define DDRC_PMLCA1_BGRAN_SHIFT (6U) +/*! BGRAN - Burst Granularity */ +#define DDRC_PMLCA1_BGRAN(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCA1_BGRAN_SHIFT)) & DDRC_PMLCA1_BGRAN_MASK) + +#define DDRC_PMLCA1_BSIZE_MASK (0xF800U) +#define DDRC_PMLCA1_BSIZE_SHIFT (11U) +/*! BSIZE - Burst Size */ +#define DDRC_PMLCA1_BSIZE(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCA1_BSIZE_SHIFT)) & DDRC_PMLCA1_BSIZE_MASK) + +#define DDRC_PMLCA1_EVENT_MASK (0x7F0000U) +#define DDRC_PMLCA1_EVENT_SHIFT (16U) +/*! EVENT - Event Selector */ +#define DDRC_PMLCA1_EVENT(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCA1_EVENT_SHIFT)) & DDRC_PMLCA1_EVENT_MASK) + +#define DDRC_PMLCA1_CE_MASK (0x4000000U) +#define DDRC_PMLCA1_CE_SHIFT (26U) +/*! CE - Condition Enable + * 0b0..Counter overflow conditions cannot occur + * 0b1..Counter overflow conditions occur + */ +#define DDRC_PMLCA1_CE(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCA1_CE_SHIFT)) & DDRC_PMLCA1_CE_MASK) + +#define DDRC_PMLCA1_FC_MASK (0x80000000U) +#define DDRC_PMLCA1_FC_SHIFT (31U) +/*! FC - Freeze Counter + * 0b0..Enabled + * 0b1..Disabled + */ +#define DDRC_PMLCA1_FC(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCA1_FC_SHIFT)) & DDRC_PMLCA1_FC_MASK) +/*! @} */ + +/*! @name PMLCB1 - Performance Monitor Local Control B */ +/*! @{ */ + +#define DDRC_PMLCB1_THRESHOLD_MASK (0x3FU) +#define DDRC_PMLCB1_THRESHOLD_SHIFT (0U) +/*! THRESHOLD - Threshold */ +#define DDRC_PMLCB1_THRESHOLD(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCB1_THRESHOLD_SHIFT)) & DDRC_PMLCB1_THRESHOLD_MASK) + +#define DDRC_PMLCB1_TBMULT_MASK (0x700U) +#define DDRC_PMLCB1_TBMULT_SHIFT (8U) +/*! TBMULT - Threshold And Burstiness Multiplier + * 0b000..1 + * 0b001..2 + * 0b010..4 + * 0b011..8 + * 0b100..16 + * 0b101..32 + * 0b110..64 + * 0b111..128 + */ +#define DDRC_PMLCB1_TBMULT(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCB1_TBMULT_SHIFT)) & DDRC_PMLCB1_TBMULT_MASK) + +#define DDRC_PMLCB1_TRIGOFFCNTL_MASK (0x30000U) +#define DDRC_PMLCB1_TRIGOFFCNTL_SHIFT (16U) +/*! TRIGOFFCNTL - Trigger-Off Control + * 0b00..Trigger off (no triggering to start) + * 0b01..Trigger on change + * 0b10..Trigger on overflow + * 0b11..Reserved + */ +#define DDRC_PMLCB1_TRIGOFFCNTL(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCB1_TRIGOFFCNTL_SHIFT)) & DDRC_PMLCB1_TRIGOFFCNTL_MASK) + +#define DDRC_PMLCB1_TRIGONCNTL_MASK (0xC0000U) +#define DDRC_PMLCB1_TRIGONCNTL_SHIFT (18U) +/*! TRIGONCNTL - Trigger-On Control + * 0b00..Triggering off (no triggering to start) + * 0b01..Trigger on change + * 0b10..Trigger on overflow + * 0b11..Reserved + */ +#define DDRC_PMLCB1_TRIGONCNTL(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCB1_TRIGONCNTL_SHIFT)) & DDRC_PMLCB1_TRIGONCNTL_MASK) + +#define DDRC_PMLCB1_TRIGOFFSEL_MASK (0xF00000U) +#define DDRC_PMLCB1_TRIGOFFSEL_SHIFT (20U) +/*! TRIGOFFSEL - Trigger-Off Select */ +#define DDRC_PMLCB1_TRIGOFFSEL(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCB1_TRIGOFFSEL_SHIFT)) & DDRC_PMLCB1_TRIGOFFSEL_MASK) + +#define DDRC_PMLCB1_TRIGONSEL_MASK (0x3C000000U) +#define DDRC_PMLCB1_TRIGONSEL_SHIFT (26U) +/*! TRIGONSEL - Trigger-On Select */ +#define DDRC_PMLCB1_TRIGONSEL(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCB1_TRIGONSEL_SHIFT)) & DDRC_PMLCB1_TRIGONSEL_MASK) +/*! @} */ + +/*! @name PMC1 - Performance Monitor Counter */ +/*! @{ */ + +#define DDRC_PMC1_PMC1_MASK (0xFFFFFFFFU) +#define DDRC_PMC1_PMC1_SHIFT (0U) +/*! PMC1 - Event Count */ +#define DDRC_PMC1_PMC1(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMC1_PMC1_SHIFT)) & DDRC_PMC1_PMC1_MASK) +/*! @} */ + +/*! @name PMLCA2 - Performance Monitor Local Control A */ +/*! @{ */ + +#define DDRC_PMLCA2_BDIST_MASK (0x3FU) +#define DDRC_PMLCA2_BDIST_SHIFT (0U) +/*! BDIST - Burst Distance */ +#define DDRC_PMLCA2_BDIST(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCA2_BDIST_SHIFT)) & DDRC_PMLCA2_BDIST_MASK) + +#define DDRC_PMLCA2_BGRAN_MASK (0x7C0U) +#define DDRC_PMLCA2_BGRAN_SHIFT (6U) +/*! BGRAN - Burst Granularity */ +#define DDRC_PMLCA2_BGRAN(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCA2_BGRAN_SHIFT)) & DDRC_PMLCA2_BGRAN_MASK) + +#define DDRC_PMLCA2_BSIZE_MASK (0xF800U) +#define DDRC_PMLCA2_BSIZE_SHIFT (11U) +/*! BSIZE - Burst Size */ +#define DDRC_PMLCA2_BSIZE(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCA2_BSIZE_SHIFT)) & DDRC_PMLCA2_BSIZE_MASK) + +#define DDRC_PMLCA2_EVENT_MASK (0x7F0000U) +#define DDRC_PMLCA2_EVENT_SHIFT (16U) +/*! EVENT - Event Selector */ +#define DDRC_PMLCA2_EVENT(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCA2_EVENT_SHIFT)) & DDRC_PMLCA2_EVENT_MASK) + +#define DDRC_PMLCA2_CE_MASK (0x4000000U) +#define DDRC_PMLCA2_CE_SHIFT (26U) +/*! CE - Condition Enable + * 0b0..Counter overflow conditions cannot occur + * 0b1..Counter overflow conditions occur + */ +#define DDRC_PMLCA2_CE(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCA2_CE_SHIFT)) & DDRC_PMLCA2_CE_MASK) + +#define DDRC_PMLCA2_FC_MASK (0x80000000U) +#define DDRC_PMLCA2_FC_SHIFT (31U) +/*! FC - Freeze Counter + * 0b0..Enabled + * 0b1..Disabled + */ +#define DDRC_PMLCA2_FC(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCA2_FC_SHIFT)) & DDRC_PMLCA2_FC_MASK) +/*! @} */ + +/*! @name PMLCB2 - Performance Monitor Local Control B */ +/*! @{ */ + +#define DDRC_PMLCB2_THRESHOLD_MASK (0x3FU) +#define DDRC_PMLCB2_THRESHOLD_SHIFT (0U) +/*! THRESHOLD - Threshold */ +#define DDRC_PMLCB2_THRESHOLD(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCB2_THRESHOLD_SHIFT)) & DDRC_PMLCB2_THRESHOLD_MASK) + +#define DDRC_PMLCB2_TBMULT_MASK (0x700U) +#define DDRC_PMLCB2_TBMULT_SHIFT (8U) +/*! TBMULT - Threshold And Burstiness Multiplier + * 0b000..1 + * 0b001..2 + * 0b010..4 + * 0b011..8 + * 0b100..16 + * 0b101..32 + * 0b110..64 + * 0b111..128 + */ +#define DDRC_PMLCB2_TBMULT(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCB2_TBMULT_SHIFT)) & DDRC_PMLCB2_TBMULT_MASK) + +#define DDRC_PMLCB2_TRIGOFFCNTL_MASK (0x30000U) +#define DDRC_PMLCB2_TRIGOFFCNTL_SHIFT (16U) +/*! TRIGOFFCNTL - Trigger-Off Control + * 0b00..Trigger off (no triggering to start) + * 0b01..Trigger on change + * 0b10..Trigger on overflow + * 0b11..Reserved + */ +#define DDRC_PMLCB2_TRIGOFFCNTL(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCB2_TRIGOFFCNTL_SHIFT)) & DDRC_PMLCB2_TRIGOFFCNTL_MASK) + +#define DDRC_PMLCB2_TRIGONCNTL_MASK (0xC0000U) +#define DDRC_PMLCB2_TRIGONCNTL_SHIFT (18U) +/*! TRIGONCNTL - Trigger-On Control + * 0b00..Triggering off (no triggering to start) + * 0b01..Trigger on change + * 0b10..Trigger on overflow + * 0b11..Reserved + */ +#define DDRC_PMLCB2_TRIGONCNTL(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCB2_TRIGONCNTL_SHIFT)) & DDRC_PMLCB2_TRIGONCNTL_MASK) + +#define DDRC_PMLCB2_TRIGOFFSEL_MASK (0xF00000U) +#define DDRC_PMLCB2_TRIGOFFSEL_SHIFT (20U) +/*! TRIGOFFSEL - Trigger-Off Select */ +#define DDRC_PMLCB2_TRIGOFFSEL(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCB2_TRIGOFFSEL_SHIFT)) & DDRC_PMLCB2_TRIGOFFSEL_MASK) + +#define DDRC_PMLCB2_TRIGONSEL_MASK (0x3C000000U) +#define DDRC_PMLCB2_TRIGONSEL_SHIFT (26U) +/*! TRIGONSEL - Trigger-On Select */ +#define DDRC_PMLCB2_TRIGONSEL(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCB2_TRIGONSEL_SHIFT)) & DDRC_PMLCB2_TRIGONSEL_MASK) +/*! @} */ + +/*! @name PMC2 - Performance Monitor Counter */ +/*! @{ */ + +#define DDRC_PMC2_PMC2_MASK (0xFFFFFFFFU) +#define DDRC_PMC2_PMC2_SHIFT (0U) +/*! PMC2 - Event Count */ +#define DDRC_PMC2_PMC2(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMC2_PMC2_SHIFT)) & DDRC_PMC2_PMC2_MASK) +/*! @} */ + +/*! @name PMLCA3 - Performance Monitor Local Control A */ +/*! @{ */ + +#define DDRC_PMLCA3_BDIST_MASK (0x3FU) +#define DDRC_PMLCA3_BDIST_SHIFT (0U) +/*! BDIST - Burst Distance */ +#define DDRC_PMLCA3_BDIST(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCA3_BDIST_SHIFT)) & DDRC_PMLCA3_BDIST_MASK) + +#define DDRC_PMLCA3_BGRAN_MASK (0x7C0U) +#define DDRC_PMLCA3_BGRAN_SHIFT (6U) +/*! BGRAN - Burst Granularity */ +#define DDRC_PMLCA3_BGRAN(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCA3_BGRAN_SHIFT)) & DDRC_PMLCA3_BGRAN_MASK) + +#define DDRC_PMLCA3_BSIZE_MASK (0xF800U) +#define DDRC_PMLCA3_BSIZE_SHIFT (11U) +/*! BSIZE - Burst Size */ +#define DDRC_PMLCA3_BSIZE(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCA3_BSIZE_SHIFT)) & DDRC_PMLCA3_BSIZE_MASK) + +#define DDRC_PMLCA3_EVENT_MASK (0x7F0000U) +#define DDRC_PMLCA3_EVENT_SHIFT (16U) +/*! EVENT - Event Selector */ +#define DDRC_PMLCA3_EVENT(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCA3_EVENT_SHIFT)) & DDRC_PMLCA3_EVENT_MASK) + +#define DDRC_PMLCA3_CE_MASK (0x4000000U) +#define DDRC_PMLCA3_CE_SHIFT (26U) +/*! CE - Condition Enable + * 0b0..Counter overflow conditions cannot occur + * 0b1..Counter overflow conditions occur + */ +#define DDRC_PMLCA3_CE(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCA3_CE_SHIFT)) & DDRC_PMLCA3_CE_MASK) + +#define DDRC_PMLCA3_FC_MASK (0x80000000U) +#define DDRC_PMLCA3_FC_SHIFT (31U) +/*! FC - Freeze Counter + * 0b0..Enabled + * 0b1..Disabled + */ +#define DDRC_PMLCA3_FC(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCA3_FC_SHIFT)) & DDRC_PMLCA3_FC_MASK) +/*! @} */ + +/*! @name PMLCB3 - Performance Monitor Local Control B */ +/*! @{ */ + +#define DDRC_PMLCB3_THRESHOLD_MASK (0x3FU) +#define DDRC_PMLCB3_THRESHOLD_SHIFT (0U) +/*! THRESHOLD - Threshold */ +#define DDRC_PMLCB3_THRESHOLD(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCB3_THRESHOLD_SHIFT)) & DDRC_PMLCB3_THRESHOLD_MASK) + +#define DDRC_PMLCB3_TBMULT_MASK (0x700U) +#define DDRC_PMLCB3_TBMULT_SHIFT (8U) +/*! TBMULT - Threshold And Burstiness Multiplier + * 0b000..1 + * 0b001..2 + * 0b010..4 + * 0b011..8 + * 0b100..16 + * 0b101..32 + * 0b110..64 + * 0b111..128 + */ +#define DDRC_PMLCB3_TBMULT(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCB3_TBMULT_SHIFT)) & DDRC_PMLCB3_TBMULT_MASK) + +#define DDRC_PMLCB3_TRIGOFFCNTL_MASK (0x30000U) +#define DDRC_PMLCB3_TRIGOFFCNTL_SHIFT (16U) +/*! TRIGOFFCNTL - Trigger-Off Control + * 0b00..Trigger off (no triggering to start) + * 0b01..Trigger on change + * 0b10..Trigger on overflow + * 0b11..Reserved + */ +#define DDRC_PMLCB3_TRIGOFFCNTL(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCB3_TRIGOFFCNTL_SHIFT)) & DDRC_PMLCB3_TRIGOFFCNTL_MASK) + +#define DDRC_PMLCB3_TRIGONCNTL_MASK (0xC0000U) +#define DDRC_PMLCB3_TRIGONCNTL_SHIFT (18U) +/*! TRIGONCNTL - Trigger-On Control + * 0b00..Triggering off (no triggering to start) + * 0b01..Trigger on change + * 0b10..Trigger on overflow + * 0b11..Reserved + */ +#define DDRC_PMLCB3_TRIGONCNTL(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCB3_TRIGONCNTL_SHIFT)) & DDRC_PMLCB3_TRIGONCNTL_MASK) + +#define DDRC_PMLCB3_TRIGOFFSEL_MASK (0xF00000U) +#define DDRC_PMLCB3_TRIGOFFSEL_SHIFT (20U) +/*! TRIGOFFSEL - Trigger-Off Select */ +#define DDRC_PMLCB3_TRIGOFFSEL(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCB3_TRIGOFFSEL_SHIFT)) & DDRC_PMLCB3_TRIGOFFSEL_MASK) + +#define DDRC_PMLCB3_TRIGONSEL_MASK (0x3C000000U) +#define DDRC_PMLCB3_TRIGONSEL_SHIFT (26U) +/*! TRIGONSEL - Trigger-On Select */ +#define DDRC_PMLCB3_TRIGONSEL(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCB3_TRIGONSEL_SHIFT)) & DDRC_PMLCB3_TRIGONSEL_MASK) +/*! @} */ + +/*! @name PMC3 - Performance Monitor Counter */ +/*! @{ */ + +#define DDRC_PMC3_PMC3_MASK (0xFFFFFFFFU) +#define DDRC_PMC3_PMC3_SHIFT (0U) +/*! PMC3 - Event Count */ +#define DDRC_PMC3_PMC3(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMC3_PMC3_SHIFT)) & DDRC_PMC3_PMC3_MASK) +/*! @} */ + +/*! @name PMLCA4 - Performance Monitor Local Control A */ +/*! @{ */ + +#define DDRC_PMLCA4_BDIST_MASK (0x3FU) +#define DDRC_PMLCA4_BDIST_SHIFT (0U) +/*! BDIST - Burst Distance */ +#define DDRC_PMLCA4_BDIST(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCA4_BDIST_SHIFT)) & DDRC_PMLCA4_BDIST_MASK) + +#define DDRC_PMLCA4_BGRAN_MASK (0x7C0U) +#define DDRC_PMLCA4_BGRAN_SHIFT (6U) +/*! BGRAN - Burst Granularity */ +#define DDRC_PMLCA4_BGRAN(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCA4_BGRAN_SHIFT)) & DDRC_PMLCA4_BGRAN_MASK) + +#define DDRC_PMLCA4_BSIZE_MASK (0xF800U) +#define DDRC_PMLCA4_BSIZE_SHIFT (11U) +/*! BSIZE - Burst Size */ +#define DDRC_PMLCA4_BSIZE(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCA4_BSIZE_SHIFT)) & DDRC_PMLCA4_BSIZE_MASK) + +#define DDRC_PMLCA4_EVENT_MASK (0x7F0000U) +#define DDRC_PMLCA4_EVENT_SHIFT (16U) +/*! EVENT - Event Selector */ +#define DDRC_PMLCA4_EVENT(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCA4_EVENT_SHIFT)) & DDRC_PMLCA4_EVENT_MASK) + +#define DDRC_PMLCA4_CE_MASK (0x4000000U) +#define DDRC_PMLCA4_CE_SHIFT (26U) +/*! CE - Condition Enable + * 0b0..Counter overflow conditions cannot occur + * 0b1..Counter overflow conditions occur + */ +#define DDRC_PMLCA4_CE(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCA4_CE_SHIFT)) & DDRC_PMLCA4_CE_MASK) + +#define DDRC_PMLCA4_FC_MASK (0x80000000U) +#define DDRC_PMLCA4_FC_SHIFT (31U) +/*! FC - Freeze Counter + * 0b0..Enabled + * 0b1..Disabled + */ +#define DDRC_PMLCA4_FC(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCA4_FC_SHIFT)) & DDRC_PMLCA4_FC_MASK) +/*! @} */ + +/*! @name PMLCB4 - Performance Monitor Local Control B */ +/*! @{ */ + +#define DDRC_PMLCB4_THRESHOLD_MASK (0x3FU) +#define DDRC_PMLCB4_THRESHOLD_SHIFT (0U) +/*! THRESHOLD - Threshold */ +#define DDRC_PMLCB4_THRESHOLD(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCB4_THRESHOLD_SHIFT)) & DDRC_PMLCB4_THRESHOLD_MASK) + +#define DDRC_PMLCB4_TBMULT_MASK (0x700U) +#define DDRC_PMLCB4_TBMULT_SHIFT (8U) +/*! TBMULT - Threshold And Burstiness Multiplier + * 0b000..1 + * 0b001..2 + * 0b010..4 + * 0b011..8 + * 0b100..16 + * 0b101..32 + * 0b110..64 + * 0b111..128 + */ +#define DDRC_PMLCB4_TBMULT(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCB4_TBMULT_SHIFT)) & DDRC_PMLCB4_TBMULT_MASK) + +#define DDRC_PMLCB4_TRIGOFFCNTL_MASK (0x30000U) +#define DDRC_PMLCB4_TRIGOFFCNTL_SHIFT (16U) +/*! TRIGOFFCNTL - Trigger-Off Control + * 0b00..Trigger off (no triggering to start) + * 0b01..Trigger on change + * 0b10..Trigger on overflow + * 0b11..Reserved + */ +#define DDRC_PMLCB4_TRIGOFFCNTL(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCB4_TRIGOFFCNTL_SHIFT)) & DDRC_PMLCB4_TRIGOFFCNTL_MASK) + +#define DDRC_PMLCB4_TRIGONCNTL_MASK (0xC0000U) +#define DDRC_PMLCB4_TRIGONCNTL_SHIFT (18U) +/*! TRIGONCNTL - Trigger-On Control + * 0b00..Triggering off (no triggering to start) + * 0b01..Trigger on change + * 0b10..Trigger on overflow + * 0b11..Reserved + */ +#define DDRC_PMLCB4_TRIGONCNTL(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCB4_TRIGONCNTL_SHIFT)) & DDRC_PMLCB4_TRIGONCNTL_MASK) + +#define DDRC_PMLCB4_TRIGOFFSEL_MASK (0xF00000U) +#define DDRC_PMLCB4_TRIGOFFSEL_SHIFT (20U) +/*! TRIGOFFSEL - Trigger-Off Select */ +#define DDRC_PMLCB4_TRIGOFFSEL(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCB4_TRIGOFFSEL_SHIFT)) & DDRC_PMLCB4_TRIGOFFSEL_MASK) + +#define DDRC_PMLCB4_TRIGONSEL_MASK (0x3C000000U) +#define DDRC_PMLCB4_TRIGONSEL_SHIFT (26U) +/*! TRIGONSEL - Trigger-On Select */ +#define DDRC_PMLCB4_TRIGONSEL(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCB4_TRIGONSEL_SHIFT)) & DDRC_PMLCB4_TRIGONSEL_MASK) +/*! @} */ + +/*! @name PMC4 - Performance Monitor Counter */ +/*! @{ */ + +#define DDRC_PMC4_PMC4_MASK (0xFFFFFFFFU) +#define DDRC_PMC4_PMC4_SHIFT (0U) +/*! PMC4 - Event Count */ +#define DDRC_PMC4_PMC4(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMC4_PMC4_SHIFT)) & DDRC_PMC4_PMC4_MASK) +/*! @} */ + +/*! @name PMLCA5 - Performance Monitor Local Control A */ +/*! @{ */ + +#define DDRC_PMLCA5_BDIST_MASK (0x3FU) +#define DDRC_PMLCA5_BDIST_SHIFT (0U) +/*! BDIST - Burst Distance */ +#define DDRC_PMLCA5_BDIST(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCA5_BDIST_SHIFT)) & DDRC_PMLCA5_BDIST_MASK) + +#define DDRC_PMLCA5_BGRAN_MASK (0x7C0U) +#define DDRC_PMLCA5_BGRAN_SHIFT (6U) +/*! BGRAN - Burst Granularity */ +#define DDRC_PMLCA5_BGRAN(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCA5_BGRAN_SHIFT)) & DDRC_PMLCA5_BGRAN_MASK) + +#define DDRC_PMLCA5_BSIZE_MASK (0xF800U) +#define DDRC_PMLCA5_BSIZE_SHIFT (11U) +/*! BSIZE - Burst Size */ +#define DDRC_PMLCA5_BSIZE(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCA5_BSIZE_SHIFT)) & DDRC_PMLCA5_BSIZE_MASK) + +#define DDRC_PMLCA5_EVENT_MASK (0x7F0000U) +#define DDRC_PMLCA5_EVENT_SHIFT (16U) +/*! EVENT - Event Selector */ +#define DDRC_PMLCA5_EVENT(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCA5_EVENT_SHIFT)) & DDRC_PMLCA5_EVENT_MASK) + +#define DDRC_PMLCA5_CE_MASK (0x4000000U) +#define DDRC_PMLCA5_CE_SHIFT (26U) +/*! CE - Condition Enable + * 0b0..Counter overflow conditions cannot occur + * 0b1..Counter overflow conditions occur + */ +#define DDRC_PMLCA5_CE(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCA5_CE_SHIFT)) & DDRC_PMLCA5_CE_MASK) + +#define DDRC_PMLCA5_FC_MASK (0x80000000U) +#define DDRC_PMLCA5_FC_SHIFT (31U) +/*! FC - Freeze Counter + * 0b0..Enabled + * 0b1..Disabled + */ +#define DDRC_PMLCA5_FC(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCA5_FC_SHIFT)) & DDRC_PMLCA5_FC_MASK) +/*! @} */ + +/*! @name PMLCB5 - Performance Monitor Local Control B */ +/*! @{ */ + +#define DDRC_PMLCB5_THRESHOLD_MASK (0x3FU) +#define DDRC_PMLCB5_THRESHOLD_SHIFT (0U) +/*! THRESHOLD - Threshold */ +#define DDRC_PMLCB5_THRESHOLD(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCB5_THRESHOLD_SHIFT)) & DDRC_PMLCB5_THRESHOLD_MASK) + +#define DDRC_PMLCB5_TBMULT_MASK (0x700U) +#define DDRC_PMLCB5_TBMULT_SHIFT (8U) +/*! TBMULT - Threshold And Burstiness Multiplier + * 0b000..1 + * 0b001..2 + * 0b010..4 + * 0b011..8 + * 0b100..16 + * 0b101..32 + * 0b110..64 + * 0b111..128 + */ +#define DDRC_PMLCB5_TBMULT(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCB5_TBMULT_SHIFT)) & DDRC_PMLCB5_TBMULT_MASK) + +#define DDRC_PMLCB5_TRIGOFFCNTL_MASK (0x30000U) +#define DDRC_PMLCB5_TRIGOFFCNTL_SHIFT (16U) +/*! TRIGOFFCNTL - Trigger-Off Control + * 0b00..Trigger off (no triggering to start) + * 0b01..Trigger on change + * 0b10..Trigger on overflow + * 0b11..Reserved + */ +#define DDRC_PMLCB5_TRIGOFFCNTL(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCB5_TRIGOFFCNTL_SHIFT)) & DDRC_PMLCB5_TRIGOFFCNTL_MASK) + +#define DDRC_PMLCB5_TRIGONCNTL_MASK (0xC0000U) +#define DDRC_PMLCB5_TRIGONCNTL_SHIFT (18U) +/*! TRIGONCNTL - Trigger-On Control + * 0b00..Triggering off (no triggering to start) + * 0b01..Trigger on change + * 0b10..Trigger on overflow + * 0b11..Reserved + */ +#define DDRC_PMLCB5_TRIGONCNTL(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCB5_TRIGONCNTL_SHIFT)) & DDRC_PMLCB5_TRIGONCNTL_MASK) + +#define DDRC_PMLCB5_TRIGOFFSEL_MASK (0xF00000U) +#define DDRC_PMLCB5_TRIGOFFSEL_SHIFT (20U) +/*! TRIGOFFSEL - Trigger-Off Select */ +#define DDRC_PMLCB5_TRIGOFFSEL(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCB5_TRIGOFFSEL_SHIFT)) & DDRC_PMLCB5_TRIGOFFSEL_MASK) + +#define DDRC_PMLCB5_TRIGONSEL_MASK (0x3C000000U) +#define DDRC_PMLCB5_TRIGONSEL_SHIFT (26U) +/*! TRIGONSEL - Trigger-On Select */ +#define DDRC_PMLCB5_TRIGONSEL(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCB5_TRIGONSEL_SHIFT)) & DDRC_PMLCB5_TRIGONSEL_MASK) +/*! @} */ + +/*! @name PMC5 - Performance Monitor Counter */ +/*! @{ */ + +#define DDRC_PMC5_PMC5_MASK (0xFFFFFFFFU) +#define DDRC_PMC5_PMC5_SHIFT (0U) +/*! PMC5 - Event Count */ +#define DDRC_PMC5_PMC5(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMC5_PMC5_SHIFT)) & DDRC_PMC5_PMC5_MASK) +/*! @} */ + +/*! @name PMLCA6 - Performance Monitor Local Control A */ +/*! @{ */ + +#define DDRC_PMLCA6_BDIST_MASK (0x3FU) +#define DDRC_PMLCA6_BDIST_SHIFT (0U) +/*! BDIST - Burst Distance */ +#define DDRC_PMLCA6_BDIST(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCA6_BDIST_SHIFT)) & DDRC_PMLCA6_BDIST_MASK) + +#define DDRC_PMLCA6_BGRAN_MASK (0x7C0U) +#define DDRC_PMLCA6_BGRAN_SHIFT (6U) +/*! BGRAN - Burst Granularity */ +#define DDRC_PMLCA6_BGRAN(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCA6_BGRAN_SHIFT)) & DDRC_PMLCA6_BGRAN_MASK) + +#define DDRC_PMLCA6_BSIZE_MASK (0xF800U) +#define DDRC_PMLCA6_BSIZE_SHIFT (11U) +/*! BSIZE - Burst Size */ +#define DDRC_PMLCA6_BSIZE(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCA6_BSIZE_SHIFT)) & DDRC_PMLCA6_BSIZE_MASK) + +#define DDRC_PMLCA6_EVENT_MASK (0x7F0000U) +#define DDRC_PMLCA6_EVENT_SHIFT (16U) +/*! EVENT - Event Selector */ +#define DDRC_PMLCA6_EVENT(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCA6_EVENT_SHIFT)) & DDRC_PMLCA6_EVENT_MASK) + +#define DDRC_PMLCA6_CE_MASK (0x4000000U) +#define DDRC_PMLCA6_CE_SHIFT (26U) +/*! CE - Condition Enable + * 0b0..Counter overflow conditions cannot occur + * 0b1..Counter overflow conditions occur + */ +#define DDRC_PMLCA6_CE(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCA6_CE_SHIFT)) & DDRC_PMLCA6_CE_MASK) + +#define DDRC_PMLCA6_FC_MASK (0x80000000U) +#define DDRC_PMLCA6_FC_SHIFT (31U) +/*! FC - Freeze Counter + * 0b0..Enabled + * 0b1..Disabled + */ +#define DDRC_PMLCA6_FC(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCA6_FC_SHIFT)) & DDRC_PMLCA6_FC_MASK) +/*! @} */ + +/*! @name PMLCB6 - Performance Monitor Local Control B */ +/*! @{ */ + +#define DDRC_PMLCB6_THRESHOLD_MASK (0x3FU) +#define DDRC_PMLCB6_THRESHOLD_SHIFT (0U) +/*! THRESHOLD - Threshold */ +#define DDRC_PMLCB6_THRESHOLD(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCB6_THRESHOLD_SHIFT)) & DDRC_PMLCB6_THRESHOLD_MASK) + +#define DDRC_PMLCB6_TBMULT_MASK (0x700U) +#define DDRC_PMLCB6_TBMULT_SHIFT (8U) +/*! TBMULT - Threshold And Burstiness Multiplier + * 0b000..1 + * 0b001..2 + * 0b010..4 + * 0b011..8 + * 0b100..16 + * 0b101..32 + * 0b110..64 + * 0b111..128 + */ +#define DDRC_PMLCB6_TBMULT(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCB6_TBMULT_SHIFT)) & DDRC_PMLCB6_TBMULT_MASK) + +#define DDRC_PMLCB6_TRIGOFFCNTL_MASK (0x30000U) +#define DDRC_PMLCB6_TRIGOFFCNTL_SHIFT (16U) +/*! TRIGOFFCNTL - Trigger-Off Control + * 0b00..Trigger off (no triggering to start) + * 0b01..Trigger on change + * 0b10..Trigger on overflow + * 0b11..Reserved + */ +#define DDRC_PMLCB6_TRIGOFFCNTL(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCB6_TRIGOFFCNTL_SHIFT)) & DDRC_PMLCB6_TRIGOFFCNTL_MASK) + +#define DDRC_PMLCB6_TRIGONCNTL_MASK (0xC0000U) +#define DDRC_PMLCB6_TRIGONCNTL_SHIFT (18U) +/*! TRIGONCNTL - Trigger-On Control + * 0b00..Triggering off (no triggering to start) + * 0b01..Trigger on change + * 0b10..Trigger on overflow + * 0b11..Reserved + */ +#define DDRC_PMLCB6_TRIGONCNTL(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCB6_TRIGONCNTL_SHIFT)) & DDRC_PMLCB6_TRIGONCNTL_MASK) + +#define DDRC_PMLCB6_TRIGOFFSEL_MASK (0xF00000U) +#define DDRC_PMLCB6_TRIGOFFSEL_SHIFT (20U) +/*! TRIGOFFSEL - Trigger-Off Select */ +#define DDRC_PMLCB6_TRIGOFFSEL(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCB6_TRIGOFFSEL_SHIFT)) & DDRC_PMLCB6_TRIGOFFSEL_MASK) + +#define DDRC_PMLCB6_TRIGONSEL_MASK (0x3C000000U) +#define DDRC_PMLCB6_TRIGONSEL_SHIFT (26U) +/*! TRIGONSEL - Trigger-On Select */ +#define DDRC_PMLCB6_TRIGONSEL(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCB6_TRIGONSEL_SHIFT)) & DDRC_PMLCB6_TRIGONSEL_MASK) +/*! @} */ + +/*! @name PMC6 - Performance Monitor Counter */ +/*! @{ */ + +#define DDRC_PMC6_PMC6_MASK (0xFFFFFFFFU) +#define DDRC_PMC6_PMC6_SHIFT (0U) +/*! PMC6 - Event Count */ +#define DDRC_PMC6_PMC6(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMC6_PMC6_SHIFT)) & DDRC_PMC6_PMC6_MASK) +/*! @} */ + +/*! @name PMLCA7 - Performance Monitor Local Control A */ +/*! @{ */ + +#define DDRC_PMLCA7_BDIST_MASK (0x3FU) +#define DDRC_PMLCA7_BDIST_SHIFT (0U) +/*! BDIST - Burst Distance */ +#define DDRC_PMLCA7_BDIST(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCA7_BDIST_SHIFT)) & DDRC_PMLCA7_BDIST_MASK) + +#define DDRC_PMLCA7_BGRAN_MASK (0x7C0U) +#define DDRC_PMLCA7_BGRAN_SHIFT (6U) +/*! BGRAN - Burst Granularity */ +#define DDRC_PMLCA7_BGRAN(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCA7_BGRAN_SHIFT)) & DDRC_PMLCA7_BGRAN_MASK) + +#define DDRC_PMLCA7_BSIZE_MASK (0xF800U) +#define DDRC_PMLCA7_BSIZE_SHIFT (11U) +/*! BSIZE - Burst Size */ +#define DDRC_PMLCA7_BSIZE(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCA7_BSIZE_SHIFT)) & DDRC_PMLCA7_BSIZE_MASK) + +#define DDRC_PMLCA7_EVENT_MASK (0x7F0000U) +#define DDRC_PMLCA7_EVENT_SHIFT (16U) +/*! EVENT - Event Selector */ +#define DDRC_PMLCA7_EVENT(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCA7_EVENT_SHIFT)) & DDRC_PMLCA7_EVENT_MASK) + +#define DDRC_PMLCA7_CE_MASK (0x4000000U) +#define DDRC_PMLCA7_CE_SHIFT (26U) +/*! CE - Condition Enable + * 0b0..Counter overflow conditions cannot occur + * 0b1..Counter overflow conditions occur + */ +#define DDRC_PMLCA7_CE(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCA7_CE_SHIFT)) & DDRC_PMLCA7_CE_MASK) + +#define DDRC_PMLCA7_FC_MASK (0x80000000U) +#define DDRC_PMLCA7_FC_SHIFT (31U) +/*! FC - Freeze Counter + * 0b0..Enabled + * 0b1..Disabled + */ +#define DDRC_PMLCA7_FC(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCA7_FC_SHIFT)) & DDRC_PMLCA7_FC_MASK) +/*! @} */ + +/*! @name PMLCB7 - Performance Monitor Local Control B */ +/*! @{ */ + +#define DDRC_PMLCB7_THRESHOLD_MASK (0x3FU) +#define DDRC_PMLCB7_THRESHOLD_SHIFT (0U) +/*! THRESHOLD - Threshold */ +#define DDRC_PMLCB7_THRESHOLD(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCB7_THRESHOLD_SHIFT)) & DDRC_PMLCB7_THRESHOLD_MASK) + +#define DDRC_PMLCB7_TBMULT_MASK (0x700U) +#define DDRC_PMLCB7_TBMULT_SHIFT (8U) +/*! TBMULT - Threshold And Burstiness Multiplier + * 0b000..1 + * 0b001..2 + * 0b010..4 + * 0b011..8 + * 0b100..16 + * 0b101..32 + * 0b110..64 + * 0b111..128 + */ +#define DDRC_PMLCB7_TBMULT(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCB7_TBMULT_SHIFT)) & DDRC_PMLCB7_TBMULT_MASK) + +#define DDRC_PMLCB7_TRIGOFFCNTL_MASK (0x30000U) +#define DDRC_PMLCB7_TRIGOFFCNTL_SHIFT (16U) +/*! TRIGOFFCNTL - Trigger-Off Control + * 0b00..Trigger off (no triggering to start) + * 0b01..Trigger on change + * 0b10..Trigger on overflow + * 0b11..Reserved + */ +#define DDRC_PMLCB7_TRIGOFFCNTL(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCB7_TRIGOFFCNTL_SHIFT)) & DDRC_PMLCB7_TRIGOFFCNTL_MASK) + +#define DDRC_PMLCB7_TRIGONCNTL_MASK (0xC0000U) +#define DDRC_PMLCB7_TRIGONCNTL_SHIFT (18U) +/*! TRIGONCNTL - Trigger-On Control + * 0b00..Triggering off (no triggering to start) + * 0b01..Trigger on change + * 0b10..Trigger on overflow + * 0b11..Reserved + */ +#define DDRC_PMLCB7_TRIGONCNTL(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCB7_TRIGONCNTL_SHIFT)) & DDRC_PMLCB7_TRIGONCNTL_MASK) + +#define DDRC_PMLCB7_TRIGOFFSEL_MASK (0xF00000U) +#define DDRC_PMLCB7_TRIGOFFSEL_SHIFT (20U) +/*! TRIGOFFSEL - Trigger-Off Select */ +#define DDRC_PMLCB7_TRIGOFFSEL(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCB7_TRIGOFFSEL_SHIFT)) & DDRC_PMLCB7_TRIGOFFSEL_MASK) + +#define DDRC_PMLCB7_TRIGONSEL_MASK (0x3C000000U) +#define DDRC_PMLCB7_TRIGONSEL_SHIFT (26U) +/*! TRIGONSEL - Trigger-On Select */ +#define DDRC_PMLCB7_TRIGONSEL(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCB7_TRIGONSEL_SHIFT)) & DDRC_PMLCB7_TRIGONSEL_MASK) +/*! @} */ + +/*! @name PMC7 - Performance Monitor Counter */ +/*! @{ */ + +#define DDRC_PMC7_PMC7_MASK (0xFFFFFFFFU) +#define DDRC_PMC7_PMC7_SHIFT (0U) +/*! PMC7 - Event Count */ +#define DDRC_PMC7_PMC7(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMC7_PMC7_SHIFT)) & DDRC_PMC7_PMC7_MASK) +/*! @} */ + +/*! @name PMLCA8 - Performance Monitor Local Control A */ +/*! @{ */ + +#define DDRC_PMLCA8_BDIST_MASK (0x3FU) +#define DDRC_PMLCA8_BDIST_SHIFT (0U) +/*! BDIST - Burst Distance */ +#define DDRC_PMLCA8_BDIST(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCA8_BDIST_SHIFT)) & DDRC_PMLCA8_BDIST_MASK) + +#define DDRC_PMLCA8_BGRAN_MASK (0x7C0U) +#define DDRC_PMLCA8_BGRAN_SHIFT (6U) +/*! BGRAN - Burst Granularity */ +#define DDRC_PMLCA8_BGRAN(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCA8_BGRAN_SHIFT)) & DDRC_PMLCA8_BGRAN_MASK) + +#define DDRC_PMLCA8_BSIZE_MASK (0xF800U) +#define DDRC_PMLCA8_BSIZE_SHIFT (11U) +/*! BSIZE - Burst Size */ +#define DDRC_PMLCA8_BSIZE(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCA8_BSIZE_SHIFT)) & DDRC_PMLCA8_BSIZE_MASK) + +#define DDRC_PMLCA8_EVENT_MASK (0x7F0000U) +#define DDRC_PMLCA8_EVENT_SHIFT (16U) +/*! EVENT - Event Selector */ +#define DDRC_PMLCA8_EVENT(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCA8_EVENT_SHIFT)) & DDRC_PMLCA8_EVENT_MASK) + +#define DDRC_PMLCA8_CE_MASK (0x4000000U) +#define DDRC_PMLCA8_CE_SHIFT (26U) +/*! CE - Condition Enable + * 0b0..Counter overflow conditions cannot occur + * 0b1..Counter overflow conditions occur + */ +#define DDRC_PMLCA8_CE(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCA8_CE_SHIFT)) & DDRC_PMLCA8_CE_MASK) + +#define DDRC_PMLCA8_FC_MASK (0x80000000U) +#define DDRC_PMLCA8_FC_SHIFT (31U) +/*! FC - Freeze Counter + * 0b0..Enabled + * 0b1..Disabled + */ +#define DDRC_PMLCA8_FC(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCA8_FC_SHIFT)) & DDRC_PMLCA8_FC_MASK) +/*! @} */ + +/*! @name PMLCB8 - Performance Monitor Local Control B */ +/*! @{ */ + +#define DDRC_PMLCB8_THRESHOLD_MASK (0x3FU) +#define DDRC_PMLCB8_THRESHOLD_SHIFT (0U) +/*! THRESHOLD - Threshold */ +#define DDRC_PMLCB8_THRESHOLD(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCB8_THRESHOLD_SHIFT)) & DDRC_PMLCB8_THRESHOLD_MASK) + +#define DDRC_PMLCB8_TBMULT_MASK (0x700U) +#define DDRC_PMLCB8_TBMULT_SHIFT (8U) +/*! TBMULT - Threshold And Burstiness Multiplier + * 0b000..1 + * 0b001..2 + * 0b010..4 + * 0b011..8 + * 0b100..16 + * 0b101..32 + * 0b110..64 + * 0b111..128 + */ +#define DDRC_PMLCB8_TBMULT(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCB8_TBMULT_SHIFT)) & DDRC_PMLCB8_TBMULT_MASK) + +#define DDRC_PMLCB8_TRIGOFFCNTL_MASK (0x30000U) +#define DDRC_PMLCB8_TRIGOFFCNTL_SHIFT (16U) +/*! TRIGOFFCNTL - Trigger-Off Control + * 0b00..Trigger off (no triggering to start) + * 0b01..Trigger on change + * 0b10..Trigger on overflow + * 0b11..Reserved + */ +#define DDRC_PMLCB8_TRIGOFFCNTL(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCB8_TRIGOFFCNTL_SHIFT)) & DDRC_PMLCB8_TRIGOFFCNTL_MASK) + +#define DDRC_PMLCB8_TRIGONCNTL_MASK (0xC0000U) +#define DDRC_PMLCB8_TRIGONCNTL_SHIFT (18U) +/*! TRIGONCNTL - Trigger-On Control + * 0b00..Triggering off (no triggering to start) + * 0b01..Trigger on change + * 0b10..Trigger on overflow + * 0b11..Reserved + */ +#define DDRC_PMLCB8_TRIGONCNTL(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCB8_TRIGONCNTL_SHIFT)) & DDRC_PMLCB8_TRIGONCNTL_MASK) + +#define DDRC_PMLCB8_TRIGOFFSEL_MASK (0xF00000U) +#define DDRC_PMLCB8_TRIGOFFSEL_SHIFT (20U) +/*! TRIGOFFSEL - Trigger-Off Select */ +#define DDRC_PMLCB8_TRIGOFFSEL(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCB8_TRIGOFFSEL_SHIFT)) & DDRC_PMLCB8_TRIGOFFSEL_MASK) + +#define DDRC_PMLCB8_TRIGONSEL_MASK (0x3C000000U) +#define DDRC_PMLCB8_TRIGONSEL_SHIFT (26U) +/*! TRIGONSEL - Trigger-On Select */ +#define DDRC_PMLCB8_TRIGONSEL(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCB8_TRIGONSEL_SHIFT)) & DDRC_PMLCB8_TRIGONSEL_MASK) +/*! @} */ + +/*! @name PMC8 - Performance Monitor Counter */ +/*! @{ */ + +#define DDRC_PMC8_PMC8_MASK (0xFFFFFFFFU) +#define DDRC_PMC8_PMC8_SHIFT (0U) +/*! PMC8 - Event Count */ +#define DDRC_PMC8_PMC8(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMC8_PMC8_SHIFT)) & DDRC_PMC8_PMC8_MASK) +/*! @} */ + +/*! @name PMLCA9 - Performance Monitor Local Control A */ +/*! @{ */ + +#define DDRC_PMLCA9_BDIST_MASK (0x3FU) +#define DDRC_PMLCA9_BDIST_SHIFT (0U) +/*! BDIST - Burst Distance */ +#define DDRC_PMLCA9_BDIST(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCA9_BDIST_SHIFT)) & DDRC_PMLCA9_BDIST_MASK) + +#define DDRC_PMLCA9_BGRAN_MASK (0x7C0U) +#define DDRC_PMLCA9_BGRAN_SHIFT (6U) +/*! BGRAN - Burst Granularity */ +#define DDRC_PMLCA9_BGRAN(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCA9_BGRAN_SHIFT)) & DDRC_PMLCA9_BGRAN_MASK) + +#define DDRC_PMLCA9_BSIZE_MASK (0xF800U) +#define DDRC_PMLCA9_BSIZE_SHIFT (11U) +/*! BSIZE - Burst Size */ +#define DDRC_PMLCA9_BSIZE(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCA9_BSIZE_SHIFT)) & DDRC_PMLCA9_BSIZE_MASK) + +#define DDRC_PMLCA9_EVENT_MASK (0x7F0000U) +#define DDRC_PMLCA9_EVENT_SHIFT (16U) +/*! EVENT - Event Selector */ +#define DDRC_PMLCA9_EVENT(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCA9_EVENT_SHIFT)) & DDRC_PMLCA9_EVENT_MASK) + +#define DDRC_PMLCA9_CE_MASK (0x4000000U) +#define DDRC_PMLCA9_CE_SHIFT (26U) +/*! CE - Condition Enable + * 0b0..Counter overflow conditions cannot occur + * 0b1..Counter overflow conditions occur + */ +#define DDRC_PMLCA9_CE(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCA9_CE_SHIFT)) & DDRC_PMLCA9_CE_MASK) + +#define DDRC_PMLCA9_FC_MASK (0x80000000U) +#define DDRC_PMLCA9_FC_SHIFT (31U) +/*! FC - Freeze Counter + * 0b0..Enabled + * 0b1..Disabled + */ +#define DDRC_PMLCA9_FC(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCA9_FC_SHIFT)) & DDRC_PMLCA9_FC_MASK) +/*! @} */ + +/*! @name PMLCB9 - Performance Monitor Local Control B */ +/*! @{ */ + +#define DDRC_PMLCB9_THRESHOLD_MASK (0x3FU) +#define DDRC_PMLCB9_THRESHOLD_SHIFT (0U) +/*! THRESHOLD - Threshold */ +#define DDRC_PMLCB9_THRESHOLD(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCB9_THRESHOLD_SHIFT)) & DDRC_PMLCB9_THRESHOLD_MASK) + +#define DDRC_PMLCB9_TBMULT_MASK (0x700U) +#define DDRC_PMLCB9_TBMULT_SHIFT (8U) +/*! TBMULT - Threshold And Burstiness Multiplier + * 0b000..1 + * 0b001..2 + * 0b010..4 + * 0b011..8 + * 0b100..16 + * 0b101..32 + * 0b110..64 + * 0b111..128 + */ +#define DDRC_PMLCB9_TBMULT(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCB9_TBMULT_SHIFT)) & DDRC_PMLCB9_TBMULT_MASK) + +#define DDRC_PMLCB9_TRIGOFFCNTL_MASK (0x30000U) +#define DDRC_PMLCB9_TRIGOFFCNTL_SHIFT (16U) +/*! TRIGOFFCNTL - Trigger-Off Control + * 0b00..Trigger off (no triggering to start) + * 0b01..Trigger on change + * 0b10..Trigger on overflow + * 0b11..Reserved + */ +#define DDRC_PMLCB9_TRIGOFFCNTL(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCB9_TRIGOFFCNTL_SHIFT)) & DDRC_PMLCB9_TRIGOFFCNTL_MASK) + +#define DDRC_PMLCB9_TRIGONCNTL_MASK (0xC0000U) +#define DDRC_PMLCB9_TRIGONCNTL_SHIFT (18U) +/*! TRIGONCNTL - Trigger-On Control + * 0b00..Triggering off (no triggering to start) + * 0b01..Trigger on change + * 0b10..Trigger on overflow + * 0b11..Reserved + */ +#define DDRC_PMLCB9_TRIGONCNTL(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCB9_TRIGONCNTL_SHIFT)) & DDRC_PMLCB9_TRIGONCNTL_MASK) + +#define DDRC_PMLCB9_TRIGOFFSEL_MASK (0xF00000U) +#define DDRC_PMLCB9_TRIGOFFSEL_SHIFT (20U) +/*! TRIGOFFSEL - Trigger-Off Select */ +#define DDRC_PMLCB9_TRIGOFFSEL(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCB9_TRIGOFFSEL_SHIFT)) & DDRC_PMLCB9_TRIGOFFSEL_MASK) + +#define DDRC_PMLCB9_TRIGONSEL_MASK (0x3C000000U) +#define DDRC_PMLCB9_TRIGONSEL_SHIFT (26U) +/*! TRIGONSEL - Trigger-On Select */ +#define DDRC_PMLCB9_TRIGONSEL(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCB9_TRIGONSEL_SHIFT)) & DDRC_PMLCB9_TRIGONSEL_MASK) +/*! @} */ + +/*! @name PMC9 - Performance Monitor Counter */ +/*! @{ */ + +#define DDRC_PMC9_PMC9_MASK (0xFFFFFFFFU) +#define DDRC_PMC9_PMC9_SHIFT (0U) +/*! PMC9 - Event Count */ +#define DDRC_PMC9_PMC9(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMC9_PMC9_SHIFT)) & DDRC_PMC9_PMC9_MASK) +/*! @} */ + +/*! @name PMLCA10 - Performance Monitor Local Control A */ +/*! @{ */ + +#define DDRC_PMLCA10_BDIST_MASK (0x3FU) +#define DDRC_PMLCA10_BDIST_SHIFT (0U) +/*! BDIST - Burst Distance */ +#define DDRC_PMLCA10_BDIST(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCA10_BDIST_SHIFT)) & DDRC_PMLCA10_BDIST_MASK) + +#define DDRC_PMLCA10_BGRAN_MASK (0x7C0U) +#define DDRC_PMLCA10_BGRAN_SHIFT (6U) +/*! BGRAN - Burst Granularity */ +#define DDRC_PMLCA10_BGRAN(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCA10_BGRAN_SHIFT)) & DDRC_PMLCA10_BGRAN_MASK) + +#define DDRC_PMLCA10_BSIZE_MASK (0xF800U) +#define DDRC_PMLCA10_BSIZE_SHIFT (11U) +/*! BSIZE - Burst Size */ +#define DDRC_PMLCA10_BSIZE(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCA10_BSIZE_SHIFT)) & DDRC_PMLCA10_BSIZE_MASK) + +#define DDRC_PMLCA10_EVENT_MASK (0x7F0000U) +#define DDRC_PMLCA10_EVENT_SHIFT (16U) +/*! EVENT - Event Selector */ +#define DDRC_PMLCA10_EVENT(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCA10_EVENT_SHIFT)) & DDRC_PMLCA10_EVENT_MASK) + +#define DDRC_PMLCA10_CE_MASK (0x4000000U) +#define DDRC_PMLCA10_CE_SHIFT (26U) +/*! CE - Condition Enable + * 0b0..Counter overflow conditions cannot occur + * 0b1..Counter overflow conditions occur + */ +#define DDRC_PMLCA10_CE(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCA10_CE_SHIFT)) & DDRC_PMLCA10_CE_MASK) + +#define DDRC_PMLCA10_FC_MASK (0x80000000U) +#define DDRC_PMLCA10_FC_SHIFT (31U) +/*! FC - Freeze Counter + * 0b0..Enabled + * 0b1..Disabled + */ +#define DDRC_PMLCA10_FC(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCA10_FC_SHIFT)) & DDRC_PMLCA10_FC_MASK) +/*! @} */ + +/*! @name PMLCB10 - Performance Monitor Local Control B */ +/*! @{ */ + +#define DDRC_PMLCB10_THRESHOLD_MASK (0x3FU) +#define DDRC_PMLCB10_THRESHOLD_SHIFT (0U) +/*! THRESHOLD - Threshold */ +#define DDRC_PMLCB10_THRESHOLD(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCB10_THRESHOLD_SHIFT)) & DDRC_PMLCB10_THRESHOLD_MASK) + +#define DDRC_PMLCB10_TBMULT_MASK (0x700U) +#define DDRC_PMLCB10_TBMULT_SHIFT (8U) +/*! TBMULT - Threshold And Burstiness Multiplier + * 0b000..1 + * 0b001..2 + * 0b010..4 + * 0b011..8 + * 0b100..16 + * 0b101..32 + * 0b110..64 + * 0b111..128 + */ +#define DDRC_PMLCB10_TBMULT(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCB10_TBMULT_SHIFT)) & DDRC_PMLCB10_TBMULT_MASK) + +#define DDRC_PMLCB10_TRIGOFFCNTL_MASK (0x30000U) +#define DDRC_PMLCB10_TRIGOFFCNTL_SHIFT (16U) +/*! TRIGOFFCNTL - Trigger-Off Control + * 0b00..Trigger off (no triggering to start) + * 0b01..Trigger on change + * 0b10..Trigger on overflow + * 0b11..Reserved + */ +#define DDRC_PMLCB10_TRIGOFFCNTL(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCB10_TRIGOFFCNTL_SHIFT)) & DDRC_PMLCB10_TRIGOFFCNTL_MASK) + +#define DDRC_PMLCB10_TRIGONCNTL_MASK (0xC0000U) +#define DDRC_PMLCB10_TRIGONCNTL_SHIFT (18U) +/*! TRIGONCNTL - Trigger-On Control + * 0b00..Triggering off (no triggering to start) + * 0b01..Trigger on change + * 0b10..Trigger on overflow + * 0b11..Reserved + */ +#define DDRC_PMLCB10_TRIGONCNTL(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCB10_TRIGONCNTL_SHIFT)) & DDRC_PMLCB10_TRIGONCNTL_MASK) + +#define DDRC_PMLCB10_TRIGOFFSEL_MASK (0xF00000U) +#define DDRC_PMLCB10_TRIGOFFSEL_SHIFT (20U) +/*! TRIGOFFSEL - Trigger-Off Select */ +#define DDRC_PMLCB10_TRIGOFFSEL(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCB10_TRIGOFFSEL_SHIFT)) & DDRC_PMLCB10_TRIGOFFSEL_MASK) + +#define DDRC_PMLCB10_TRIGONSEL_MASK (0x3C000000U) +#define DDRC_PMLCB10_TRIGONSEL_SHIFT (26U) +/*! TRIGONSEL - Trigger-On Select */ +#define DDRC_PMLCB10_TRIGONSEL(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCB10_TRIGONSEL_SHIFT)) & DDRC_PMLCB10_TRIGONSEL_MASK) +/*! @} */ + +/*! @name PMC10 - Performance Monitor Counter */ +/*! @{ */ + +#define DDRC_PMC10_PMC10_MASK (0xFFFFFFFFU) +#define DDRC_PMC10_PMC10_SHIFT (0U) +/*! PMC10 - Event Count */ +#define DDRC_PMC10_PMC10(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMC10_PMC10_SHIFT)) & DDRC_PMC10_PMC10_MASK) +/*! @} */ + +/*! @name ERR_EN - Error Enable */ +/*! @{ */ + +#define DDRC_ERR_EN_ECC_EN_RAM_2_MASK (0x40U) +#define DDRC_ERR_EN_ECC_EN_RAM_2_SHIFT (6U) +/*! ECC_EN_RAM_2 - ECC Enable For On-Chip RAM 2 + * 0b0..Disables + * 0b1..Enables + */ +#define DDRC_ERR_EN_ECC_EN_RAM_2(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ERR_EN_ECC_EN_RAM_2_SHIFT)) & DDRC_ERR_EN_ECC_EN_RAM_2_MASK) + +#define DDRC_ERR_EN_ECC_EN_RAM_1_MASK (0x80U) +#define DDRC_ERR_EN_ECC_EN_RAM_1_SHIFT (7U) +/*! ECC_EN_RAM_1 - ECC Enable For On-Chip RAM 1 + * 0b0..Disables + * 0b1..Enables + */ +#define DDRC_ERR_EN_ECC_EN_RAM_1(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ERR_EN_ECC_EN_RAM_1_SHIFT)) & DDRC_ERR_EN_ECC_EN_RAM_1_MASK) + +#define DDRC_ERR_EN_INLINE_ECC_EN_MASK (0x40000000U) +#define DDRC_ERR_EN_INLINE_ECC_EN_SHIFT (30U) +/*! INLINE_ECC_EN - Inline ECC Enable + * 0b0..Disables + * 0b1..Enables + */ +#define DDRC_ERR_EN_INLINE_ECC_EN(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ERR_EN_INLINE_ECC_EN_SHIFT)) & DDRC_ERR_EN_INLINE_ECC_EN_MASK) + +#define DDRC_ERR_EN_ECC_EN_MASK (0x80000000U) +#define DDRC_ERR_EN_ECC_EN_SHIFT (31U) +/*! ECC_EN - ECC Enable + * 0b0..Disables + * 0b1..Enables + */ +#define DDRC_ERR_EN_ECC_EN(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ERR_EN_ECC_EN_SHIFT)) & DDRC_ERR_EN_ECC_EN_MASK) +/*! @} */ + +/*! @name DATA_ERR_INJECT_HI - Memory Data Path Error Injection Mask High */ +/*! @{ */ + +#define DDRC_DATA_ERR_INJECT_HI_EIMH_MASK (0xFFFFFFFFU) +#define DDRC_DATA_ERR_INJECT_HI_EIMH_SHIFT (0U) +/*! EIMH - Error Injection Mask High Data Path */ +#define DDRC_DATA_ERR_INJECT_HI_EIMH(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DATA_ERR_INJECT_HI_EIMH_SHIFT)) & DDRC_DATA_ERR_INJECT_HI_EIMH_MASK) +/*! @} */ + +/*! @name DATA_ERR_INJECT_LO - Memory Data Path Error Injection Mask Low */ +/*! @{ */ + +#define DDRC_DATA_ERR_INJECT_LO_EIML_MASK (0xFFFFFFFFU) +#define DDRC_DATA_ERR_INJECT_LO_EIML_SHIFT (0U) +/*! EIML - Error Injection Mask Low Data Bit */ +#define DDRC_DATA_ERR_INJECT_LO_EIML(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DATA_ERR_INJECT_LO_EIML_SHIFT)) & DDRC_DATA_ERR_INJECT_LO_EIML_MASK) +/*! @} */ + +/*! @name ERR_INJECT - Memory Data Path Error Injection Mask ECC */ +/*! @{ */ + +#define DDRC_ERR_INJECT_EEIM_MASK (0xFFU) +#define DDRC_ERR_INJECT_EEIM_SHIFT (0U) +/*! EEIM - ECC Error Injection Mask */ +#define DDRC_ERR_INJECT_EEIM(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ERR_INJECT_EEIM_SHIFT)) & DDRC_ERR_INJECT_EEIM_MASK) + +#define DDRC_ERR_INJECT_EIEN_MASK (0x100U) +#define DDRC_ERR_INJECT_EIEN_SHIFT (8U) +/*! EIEN - Error Injection Enable + * 0b0..Disables + * 0b1..Enables + */ +#define DDRC_ERR_INJECT_EIEN(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ERR_INJECT_EIEN_SHIFT)) & DDRC_ERR_INJECT_EIEN_MASK) + +#define DDRC_ERR_INJECT_NUM_ECC_INJ_MASK (0xF000U) +#define DDRC_ERR_INJECT_NUM_ECC_INJ_SHIFT (12U) +/*! NUM_ECC_INJ - Number Of ECC Errors Injected + * 0b0000..ECC errors are injected until the error injection is disabled + * 0b0001..4 + * 0b0010..8 + * 0b0011..16 + * 0b0100..20 + * 0b0101..24 + * 0b0110..28 + * 0b0111..32 + * 0b1000..36 + * 0b1001..40 + * 0b1010..44 + * 0b1011..48 + * 0b1100..52 + * 0b1101..56 + * 0b1110..60 + * 0b1111..64 + */ +#define DDRC_ERR_INJECT_NUM_ECC_INJ(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ERR_INJECT_NUM_ECC_INJ_SHIFT)) & DDRC_ERR_INJECT_NUM_ECC_INJ_MASK) + +#define DDRC_ERR_INJECT_ECC_INJ_SRC_MASK (0x600000U) +#define DDRC_ERR_INJECT_ECC_INJ_SRC_SHIFT (21U) +/*! ECC_INJ_SRC - ECC Injection Source + * 0b00..DDR SDRAM ECC using programmed data and ECC injection masks + * 0b01..On-chip RAM ECC 1 + * 0b10..On-chip RAM ECC 2 + * 0b11..DDR SDRAM ECC. This setting forces a 1 or 2-bit ECC syndrome error based on the value of FRC2B + */ +#define DDRC_ERR_INJECT_ECC_INJ_SRC(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ERR_INJECT_ECC_INJ_SRC_SHIFT)) & DDRC_ERR_INJECT_ECC_INJ_SRC_MASK) + +#define DDRC_ERR_INJECT_FRC2B_MASK (0x800000U) +#define DDRC_ERR_INJECT_FRC2B_SHIFT (23U) +/*! FRC2B - Force 2-Bit Error + * 0b0..SBE + * 0b1..2-bit error + */ +#define DDRC_ERR_INJECT_FRC2B(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ERR_INJECT_FRC2B_SHIFT)) & DDRC_ERR_INJECT_FRC2B_MASK) + +#define DDRC_ERR_INJECT_ADDR_TEN_MASK (0x80000000U) +#define DDRC_ERR_INJECT_ADDR_TEN_SHIFT (31U) +/*! ADDR_TEN - Address Trigger Enable + * 0b0..Disables + * 0b1..Enables + */ +#define DDRC_ERR_INJECT_ADDR_TEN(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ERR_INJECT_ADDR_TEN_SHIFT)) & DDRC_ERR_INJECT_ADDR_TEN_MASK) +/*! @} */ + +/*! @name ADDR_ERR_INJ - Address Error Inject */ +/*! @{ */ + +#define DDRC_ADDR_ERR_INJ_ADDR_MASK (0xFFFFFFFFU) +#define DDRC_ADDR_ERR_INJ_ADDR_SHIFT (0U) +/*! ADDR - Address */ +#define DDRC_ADDR_ERR_INJ_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ADDR_ERR_INJ_ADDR_SHIFT)) & DDRC_ADDR_ERR_INJ_ADDR_MASK) +/*! @} */ + +/*! @name CAPTURE_EXT_DATA_HI - Memory Extended Data Path Read Capture High */ +/*! @{ */ + +#define DDRC_CAPTURE_EXT_DATA_HI_ECEHD_MASK (0xFFFFFFFFU) +#define DDRC_CAPTURE_EXT_DATA_HI_ECEHD_SHIFT (0U) +/*! ECEHD - Error Capture Extended High Data Path */ +#define DDRC_CAPTURE_EXT_DATA_HI_ECEHD(x) (((uint32_t)(((uint32_t)(x)) << DDRC_CAPTURE_EXT_DATA_HI_ECEHD_SHIFT)) & DDRC_CAPTURE_EXT_DATA_HI_ECEHD_MASK) +/*! @} */ + +/*! @name CAPTURE_EXT_DATA_LO - Memory Extended Data Path Read Capture Low */ +/*! @{ */ + +#define DDRC_CAPTURE_EXT_DATA_LO_ECELD_MASK (0xFFFFFFFFU) +#define DDRC_CAPTURE_EXT_DATA_LO_ECELD_SHIFT (0U) +/*! ECELD - Error Capture Extended Low Data Path */ +#define DDRC_CAPTURE_EXT_DATA_LO_ECELD(x) (((uint32_t)(((uint32_t)(x)) << DDRC_CAPTURE_EXT_DATA_LO_ECELD_SHIFT)) & DDRC_CAPTURE_EXT_DATA_LO_ECELD_MASK) +/*! @} */ + +/*! @name CAPTURE_DATA_HI - Memory Data Path Read Capture High */ +/*! @{ */ + +#define DDRC_CAPTURE_DATA_HI_ECHD_MASK (0xFFFFFFFFU) +#define DDRC_CAPTURE_DATA_HI_ECHD_SHIFT (0U) +/*! ECHD - Error Capture High Data Path */ +#define DDRC_CAPTURE_DATA_HI_ECHD(x) (((uint32_t)(((uint32_t)(x)) << DDRC_CAPTURE_DATA_HI_ECHD_SHIFT)) & DDRC_CAPTURE_DATA_HI_ECHD_MASK) +/*! @} */ + +/*! @name CAPTURE_DATA_LO - Memory Data Path Read Capture Low */ +/*! @{ */ + +#define DDRC_CAPTURE_DATA_LO_ECLD_MASK (0xFFFFFFFFU) +#define DDRC_CAPTURE_DATA_LO_ECLD_SHIFT (0U) +/*! ECLD - Error Capture Low Data Path */ +#define DDRC_CAPTURE_DATA_LO_ECLD(x) (((uint32_t)(((uint32_t)(x)) << DDRC_CAPTURE_DATA_LO_ECLD_SHIFT)) & DDRC_CAPTURE_DATA_LO_ECLD_MASK) +/*! @} */ + +/*! @name CAPTURE_ECC - Memory Data Path Read Capture ECC */ +/*! @{ */ + +#define DDRC_CAPTURE_ECC_ECE_MASK (0xFFFFFFFFU) +#define DDRC_CAPTURE_ECC_ECE_SHIFT (0U) +/*! ECE - Error Capture ECC */ +#define DDRC_CAPTURE_ECC_ECE(x) (((uint32_t)(((uint32_t)(x)) << DDRC_CAPTURE_ECC_ECE_SHIFT)) & DDRC_CAPTURE_ECC_ECE_MASK) +/*! @} */ + +/*! @name ERR_DETECT - Memory Error Detect */ +/*! @{ */ + +#define DDRC_ERR_DETECT_MSE_MASK (0x1U) +#define DDRC_ERR_DETECT_MSE_SHIFT (0U) +/*! MSE - Memory-Select Error + * 0b0..Not detected + * 0b1..Detected + */ +#define DDRC_ERR_DETECT_MSE(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ERR_DETECT_MSE_SHIFT)) & DDRC_ERR_DETECT_MSE_MASK) + +#define DDRC_ERR_DETECT_SBE_MASK (0x4U) +#define DDRC_ERR_DETECT_SBE_SHIFT (2U) +/*! SBE - Single-Bit ECC Errors + * 0b0..Did not cross + * 0b1..Crossed + */ +#define DDRC_ERR_DETECT_SBE(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ERR_DETECT_SBE_SHIFT)) & DDRC_ERR_DETECT_SBE_MASK) + +#define DDRC_ERR_DETECT_MBE_MASK (0x8U) +#define DDRC_ERR_DETECT_MBE_SHIFT (3U) +/*! MBE - Multiple-Bit Error + * 0b0..Not detected + * 0b1..Detected + */ +#define DDRC_ERR_DETECT_MBE(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ERR_DETECT_MBE_SHIFT)) & DDRC_ERR_DETECT_MBE_MASK) + +#define DDRC_ERR_DETECT_REFRATEE_MASK (0x80U) +#define DDRC_ERR_DETECT_REFRATEE_SHIFT (7U) +/*! REFRATEE - Refresh rate error. + * 0b0..A refresh rate error has not been detected. + * 0b1..A refresh rate error has been detected. + */ +#define DDRC_ERR_DETECT_REFRATEE(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ERR_DETECT_REFRATEE_SHIFT)) & DDRC_ERR_DETECT_REFRATEE_MASK) + +#define DDRC_ERR_DETECT_PHYE_MASK (0x10000U) +#define DDRC_ERR_DETECT_PHYE_SHIFT (16U) +/*! PHYE - PHY error. + * 0b0..A DDR PHY error has not been detected. + * 0b1..An error has been detected by the DDR PHY. + */ +#define DDRC_ERR_DETECT_PHYE(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ERR_DETECT_PHYE_SHIFT)) & DDRC_ERR_DETECT_PHYE_MASK) + +#define DDRC_ERR_DETECT_UPDTMTE_MASK (0x100000U) +#define DDRC_ERR_DETECT_UPDTMTE_SHIFT (20U) +/*! UPDTMTE - Update Timeout Error + * 0b0..Not detected + * 0b1..Detected + */ +#define DDRC_ERR_DETECT_UPDTMTE(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ERR_DETECT_UPDTMTE_SHIFT)) & DDRC_ERR_DETECT_UPDTMTE_MASK) + +#define DDRC_ERR_DETECT_SMBE2_MASK (0x400000U) +#define DDRC_ERR_DETECT_SMBE2_SHIFT (22U) +/*! SMBE2 - SRAM Multi-Bit Error 2 + * 0b0..Did not occur + * 0b1..Occurred + */ +#define DDRC_ERR_DETECT_SMBE2(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ERR_DETECT_SMBE2_SHIFT)) & DDRC_ERR_DETECT_SMBE2_MASK) + +#define DDRC_ERR_DETECT_SMBE1_MASK (0x800000U) +#define DDRC_ERR_DETECT_SMBE1_SHIFT (23U) +/*! SMBE1 - SRAM Multi-Bit Error 1 + * 0b0..Did not occur + * 0b1..Occurred + */ +#define DDRC_ERR_DETECT_SMBE1(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ERR_DETECT_SMBE1_SHIFT)) & DDRC_ERR_DETECT_SMBE1_MASK) + +#define DDRC_ERR_DETECT_SSBE2_MASK (0x1000000U) +#define DDRC_ERR_DETECT_SSBE2_SHIFT (24U) +/*! SSBE2 - SRAM SBE 2 + * 0b0..Did not occur + * 0b1..Occurred + */ +#define DDRC_ERR_DETECT_SSBE2(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ERR_DETECT_SSBE2_SHIFT)) & DDRC_ERR_DETECT_SSBE2_MASK) + +#define DDRC_ERR_DETECT_SSBE1_MASK (0x2000000U) +#define DDRC_ERR_DETECT_SSBE1_SHIFT (25U) +/*! SSBE1 - SRAM SBE 1 + * 0b0..Did not occur + * 0b1..Occurred + */ +#define DDRC_ERR_DETECT_SSBE1(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ERR_DETECT_SSBE1_SHIFT)) & DDRC_ERR_DETECT_SSBE1_MASK) + +#define DDRC_ERR_DETECT_MME_MASK (0x80000000U) +#define DDRC_ERR_DETECT_MME_SHIFT (31U) +/*! MME - Multiple Memory Errors + * 0b0..Not detected + * 0b1..Detected + */ +#define DDRC_ERR_DETECT_MME(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ERR_DETECT_MME_SHIFT)) & DDRC_ERR_DETECT_MME_MASK) +/*! @} */ + +/*! @name ERR_DISABLE - Memory Error Disable */ +/*! @{ */ + +#define DDRC_ERR_DISABLE_MSED_MASK (0x1U) +#define DDRC_ERR_DISABLE_MSED_SHIFT (0U) +/*! MSED - Memory-Select Error Disable + * 0b0..Enables + * 0b1..Disables + */ +#define DDRC_ERR_DISABLE_MSED(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ERR_DISABLE_MSED_SHIFT)) & DDRC_ERR_DISABLE_MSED_MASK) + +#define DDRC_ERR_DISABLE_SBED_MASK (0x4U) +#define DDRC_ERR_DISABLE_SBED_SHIFT (2U) +/*! SBED - Single-Bit ECC Error Disable + * 0b0..Enables + * 0b1..Disables + */ +#define DDRC_ERR_DISABLE_SBED(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ERR_DISABLE_SBED_SHIFT)) & DDRC_ERR_DISABLE_SBED_MASK) + +#define DDRC_ERR_DISABLE_MBED_MASK (0x8U) +#define DDRC_ERR_DISABLE_MBED_SHIFT (3U) +/*! MBED - Multiple-Bit ECC Error Disable + * 0b0..Detected + * 0b1..Not detected or reported + */ +#define DDRC_ERR_DISABLE_MBED(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ERR_DISABLE_MBED_SHIFT)) & DDRC_ERR_DISABLE_MBED_MASK) + +#define DDRC_ERR_DISABLE_REFRATEED_MASK (0x80U) +#define DDRC_ERR_DISABLE_REFRATEED_SHIFT (7U) +/*! REFRATEED - Refresh Rate Error Disable + * 0b0..Enables + * 0b1..Disables + */ +#define DDRC_ERR_DISABLE_REFRATEED(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ERR_DISABLE_REFRATEED_SHIFT)) & DDRC_ERR_DISABLE_REFRATEED_MASK) + +#define DDRC_ERR_DISABLE_PHYED_MASK (0x10000U) +#define DDRC_ERR_DISABLE_PHYED_SHIFT (16U) +/*! PHYED - PHY Error Disable + * 0b0..Enables + * 0b1..Disables + */ +#define DDRC_ERR_DISABLE_PHYED(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ERR_DISABLE_PHYED_SHIFT)) & DDRC_ERR_DISABLE_PHYED_MASK) + +#define DDRC_ERR_DISABLE_UPDTMTED_MASK (0x100000U) +#define DDRC_ERR_DISABLE_UPDTMTED_SHIFT (20U) +/*! UPDTMTED - Update Timeout Error Disable + * 0b0..Enables + * 0b1..Disables + */ +#define DDRC_ERR_DISABLE_UPDTMTED(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ERR_DISABLE_UPDTMTED_SHIFT)) & DDRC_ERR_DISABLE_UPDTMTED_MASK) +/*! @} */ + +/*! @name ERR_INT_EN - Memory Error Interrupt Enable */ +/*! @{ */ + +#define DDRC_ERR_INT_EN_MSEE_MASK (0x1U) +#define DDRC_ERR_INT_EN_MSEE_SHIFT (0U) +/*! MSEE - Memory-Select Error Interrupt Enable + * 0b0..No + * 0b1..Yes + */ +#define DDRC_ERR_INT_EN_MSEE(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ERR_INT_EN_MSEE_SHIFT)) & DDRC_ERR_INT_EN_MSEE_MASK) + +#define DDRC_ERR_INT_EN_SBEE_MASK (0x4U) +#define DDRC_ERR_INT_EN_SBEE_SHIFT (2U) +/*! SBEE - Single-Bit ECC Error Interrupt Enable + * 0b0..No + * 0b1..Yes + */ +#define DDRC_ERR_INT_EN_SBEE(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ERR_INT_EN_SBEE_SHIFT)) & DDRC_ERR_INT_EN_SBEE_MASK) + +#define DDRC_ERR_INT_EN_MBEE_MASK (0x8U) +#define DDRC_ERR_INT_EN_MBEE_SHIFT (3U) +/*! MBEE - Multiple-Bit ECC Error Interrupt Enable + * 0b0..No + * 0b1..Yes + */ +#define DDRC_ERR_INT_EN_MBEE(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ERR_INT_EN_MBEE_SHIFT)) & DDRC_ERR_INT_EN_MBEE_MASK) + +#define DDRC_ERR_INT_EN_SSBE12E_MASK (0x10U) +#define DDRC_ERR_INT_EN_SSBE12E_SHIFT (4U) +/*! SSBE12E - SRAM Single-Bit Error Interrupt Enable + * 0b0..No + * 0b1..Yes + */ +#define DDRC_ERR_INT_EN_SSBE12E(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ERR_INT_EN_SSBE12E_SHIFT)) & DDRC_ERR_INT_EN_SSBE12E_MASK) + +#define DDRC_ERR_INT_EN_REFRATEEE_MASK (0x80U) +#define DDRC_ERR_INT_EN_REFRATEEE_SHIFT (7U) +/*! REFRATEEE - Refresh Rate Interrupt Enable + * 0b0..No + * 0b1..Yes + */ +#define DDRC_ERR_INT_EN_REFRATEEE(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ERR_INT_EN_REFRATEEE_SHIFT)) & DDRC_ERR_INT_EN_REFRATEEE_MASK) + +#define DDRC_ERR_INT_EN_PHYEE_MASK (0x10000U) +#define DDRC_ERR_INT_EN_PHYEE_SHIFT (16U) +/*! PHYEE - PHY error interrupt enable. + * 0b0..PHY errors cannot generate interrupts. + * 0b1..PHY errors generate interrupts. + */ +#define DDRC_ERR_INT_EN_PHYEE(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ERR_INT_EN_PHYEE_SHIFT)) & DDRC_ERR_INT_EN_PHYEE_MASK) + +#define DDRC_ERR_INT_EN_UPDTMTEE_MASK (0x100000U) +#define DDRC_ERR_INT_EN_UPDTMTEE_SHIFT (20U) +/*! UPDTMTEE - Update Timeout Interrupt Enable + * 0b0..No + * 0b1..Yes + */ +#define DDRC_ERR_INT_EN_UPDTMTEE(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ERR_INT_EN_UPDTMTEE_SHIFT)) & DDRC_ERR_INT_EN_UPDTMTEE_MASK) +/*! @} */ + +/*! @name CAPTURE_ATTRIBUTES - Memory Error Attributes Capture */ +/*! @{ */ + +#define DDRC_CAPTURE_ATTRIBUTES_VLD_MASK (0x1U) +#define DDRC_CAPTURE_ATTRIBUTES_VLD_SHIFT (0U) +/*! VLD - Valid */ +#define DDRC_CAPTURE_ATTRIBUTES_VLD(x) (((uint32_t)(((uint32_t)(x)) << DDRC_CAPTURE_ATTRIBUTES_VLD_SHIFT)) & DDRC_CAPTURE_ATTRIBUTES_VLD_MASK) + +#define DDRC_CAPTURE_ATTRIBUTES_TTYP_MASK (0x3000U) +#define DDRC_CAPTURE_ATTRIBUTES_TTYP_SHIFT (12U) +/*! TTYP - Error Transaction Type + * 0b00..Reserved + * 0b01..Write + * 0b10..Read + * 0b11..Read-modify-write + */ +#define DDRC_CAPTURE_ATTRIBUTES_TTYP(x) (((uint32_t)(((uint32_t)(x)) << DDRC_CAPTURE_ATTRIBUTES_TTYP_SHIFT)) & DDRC_CAPTURE_ATTRIBUTES_TTYP_MASK) + +#define DDRC_CAPTURE_ATTRIBUTES_TSIZ_MASK (0x7000000U) +#define DDRC_CAPTURE_ATTRIBUTES_TSIZ_SHIFT (24U) +/*! TSIZ - Error Transaction Size + * 0b000..8 + * 0b001..1 + * 0b010..2 + * 0b011..3 + * 0b100..4 + * 0b101..5 + * 0b110..6 + * 0b111..7 + */ +#define DDRC_CAPTURE_ATTRIBUTES_TSIZ(x) (((uint32_t)(((uint32_t)(x)) << DDRC_CAPTURE_ATTRIBUTES_TSIZ_SHIFT)) & DDRC_CAPTURE_ATTRIBUTES_TSIZ_MASK) + +#define DDRC_CAPTURE_ATTRIBUTES_BNUM_MASK (0x70000000U) +#define DDRC_CAPTURE_ATTRIBUTES_BNUM_SHIFT (28U) +/*! BNUM - Data Beat Number */ +#define DDRC_CAPTURE_ATTRIBUTES_BNUM(x) (((uint32_t)(((uint32_t)(x)) << DDRC_CAPTURE_ATTRIBUTES_BNUM_SHIFT)) & DDRC_CAPTURE_ATTRIBUTES_BNUM_MASK) +/*! @} */ + +/*! @name CAPTURE_ADDRESS - Memory Error Address Capture */ +/*! @{ */ + +#define DDRC_CAPTURE_ADDRESS_CADDR_MASK (0xFFFFFFFFU) +#define DDRC_CAPTURE_ADDRESS_CADDR_SHIFT (0U) +/*! CADDR - Captured Address */ +#define DDRC_CAPTURE_ADDRESS_CADDR(x) (((uint32_t)(((uint32_t)(x)) << DDRC_CAPTURE_ADDRESS_CADDR_SHIFT)) & DDRC_CAPTURE_ADDRESS_CADDR_MASK) +/*! @} */ + +/*! @name CAPTURE_EXT_ADDRESS - Memory Error Extended Address Capture */ +/*! @{ */ + +#define DDRC_CAPTURE_EXT_ADDRESS_CEADDR_MASK (0xFFU) +#define DDRC_CAPTURE_EXT_ADDRESS_CEADDR_SHIFT (0U) +/*! CEADDR - Captured Extended Address */ +#define DDRC_CAPTURE_EXT_ADDRESS_CEADDR(x) (((uint32_t)(((uint32_t)(x)) << DDRC_CAPTURE_EXT_ADDRESS_CEADDR_SHIFT)) & DDRC_CAPTURE_EXT_ADDRESS_CEADDR_MASK) +/*! @} */ + +/*! @name ERR_SBE - Single-Bit ECC Memory Error Management */ +/*! @{ */ + +#define DDRC_ERR_SBE_SBEC_MASK (0xFFU) +#define DDRC_ERR_SBE_SBEC_SHIFT (0U) +/*! SBEC - SBE Counter */ +#define DDRC_ERR_SBE_SBEC(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ERR_SBE_SBEC_SHIFT)) & DDRC_ERR_SBE_SBEC_MASK) + +#define DDRC_ERR_SBE_SBET_MASK (0xFF0000U) +#define DDRC_ERR_SBE_SBET_SHIFT (16U) +/*! SBET - SBE Threshold */ +#define DDRC_ERR_SBE_SBET(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ERR_SBE_SBET_SHIFT)) & DDRC_ERR_SBE_SBET_MASK) +/*! @} */ + +/*! @name ECC_REG_0 - ECC Region 0 Configuration */ +/*! @{ */ + +#define DDRC_ECC_REG_0_REG_0_EA_MASK (0xFFFU) +#define DDRC_ECC_REG_0_REG_0_EA_SHIFT (0U) +/*! REG_0_EA - Region 0 End Address */ +#define DDRC_ECC_REG_0_REG_0_EA(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ECC_REG_0_REG_0_EA_SHIFT)) & DDRC_ECC_REG_0_REG_0_EA_MASK) + +#define DDRC_ECC_REG_0_REG_0_SA_MASK (0xFFF0000U) +#define DDRC_ECC_REG_0_REG_0_SA_SHIFT (16U) +/*! REG_0_SA - Region 0 Start Address */ +#define DDRC_ECC_REG_0_REG_0_SA(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ECC_REG_0_REG_0_SA_SHIFT)) & DDRC_ECC_REG_0_REG_0_SA_MASK) + +#define DDRC_ECC_REG_0_REG_0_EN_MASK (0x80000000U) +#define DDRC_ECC_REG_0_REG_0_EN_SHIFT (31U) +/*! REG_0_EN - Region 0 Enable + * 0b0..Does not use region 0 for ECC enablement + * 0b1..Protects addresses from region 0 with ECC + */ +#define DDRC_ECC_REG_0_REG_0_EN(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ECC_REG_0_REG_0_EN_SHIFT)) & DDRC_ECC_REG_0_REG_0_EN_MASK) +/*! @} */ + +/*! @name ECC_REG_1 - ECC Region 1 Configuration */ +/*! @{ */ + +#define DDRC_ECC_REG_1_REG_1_EA_MASK (0xFFFU) +#define DDRC_ECC_REG_1_REG_1_EA_SHIFT (0U) +/*! REG_1_EA - Region 1 End Address */ +#define DDRC_ECC_REG_1_REG_1_EA(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ECC_REG_1_REG_1_EA_SHIFT)) & DDRC_ECC_REG_1_REG_1_EA_MASK) + +#define DDRC_ECC_REG_1_REG_1_SA_MASK (0xFFF0000U) +#define DDRC_ECC_REG_1_REG_1_SA_SHIFT (16U) +/*! REG_1_SA - Region 1 Start Address */ +#define DDRC_ECC_REG_1_REG_1_SA(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ECC_REG_1_REG_1_SA_SHIFT)) & DDRC_ECC_REG_1_REG_1_SA_MASK) + +#define DDRC_ECC_REG_1_REG_1_EN_MASK (0x80000000U) +#define DDRC_ECC_REG_1_REG_1_EN_SHIFT (31U) +/*! REG_1_EN - Region 1 Enable + * 0b0..Does not use region 1 for ECC enablement + * 0b1..Protects addresses from region 1 with ECC + */ +#define DDRC_ECC_REG_1_REG_1_EN(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ECC_REG_1_REG_1_EN_SHIFT)) & DDRC_ECC_REG_1_REG_1_EN_MASK) +/*! @} */ + +/*! @name ECC_REG_2 - ECC Region 2 Configuration */ +/*! @{ */ + +#define DDRC_ECC_REG_2_REG_2_EA_MASK (0xFFFU) +#define DDRC_ECC_REG_2_REG_2_EA_SHIFT (0U) +/*! REG_2_EA - Region 2 End Address */ +#define DDRC_ECC_REG_2_REG_2_EA(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ECC_REG_2_REG_2_EA_SHIFT)) & DDRC_ECC_REG_2_REG_2_EA_MASK) + +#define DDRC_ECC_REG_2_REG_2_SA_MASK (0xFFF0000U) +#define DDRC_ECC_REG_2_REG_2_SA_SHIFT (16U) +/*! REG_2_SA - Region 2 Start Address */ +#define DDRC_ECC_REG_2_REG_2_SA(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ECC_REG_2_REG_2_SA_SHIFT)) & DDRC_ECC_REG_2_REG_2_SA_MASK) + +#define DDRC_ECC_REG_2_REG_2_EN_MASK (0x80000000U) +#define DDRC_ECC_REG_2_REG_2_EN_SHIFT (31U) +/*! REG_2_EN - Region 2 Enable + * 0b0..Does not use region 2 for ECC enablement + * 0b1..Protects addresses from region 2 with ECC + */ +#define DDRC_ECC_REG_2_REG_2_EN(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ECC_REG_2_REG_2_EN_SHIFT)) & DDRC_ECC_REG_2_REG_2_EN_MASK) +/*! @} */ + +/*! @name ECC_REG_3 - ECC Region 3 Configuration */ +/*! @{ */ + +#define DDRC_ECC_REG_3_REG_3_EA_MASK (0xFFFU) +#define DDRC_ECC_REG_3_REG_3_EA_SHIFT (0U) +/*! REG_3_EA - Region 3 End Address */ +#define DDRC_ECC_REG_3_REG_3_EA(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ECC_REG_3_REG_3_EA_SHIFT)) & DDRC_ECC_REG_3_REG_3_EA_MASK) + +#define DDRC_ECC_REG_3_REG_3_SA_MASK (0xFFF0000U) +#define DDRC_ECC_REG_3_REG_3_SA_SHIFT (16U) +/*! REG_3_SA - Region 3 Start Address */ +#define DDRC_ECC_REG_3_REG_3_SA(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ECC_REG_3_REG_3_SA_SHIFT)) & DDRC_ECC_REG_3_REG_3_SA_MASK) + +#define DDRC_ECC_REG_3_REG_3_EN_MASK (0x80000000U) +#define DDRC_ECC_REG_3_REG_3_EN_SHIFT (31U) +/*! REG_3_EN - Region 3 Enable + * 0b0..Does not use region 3 for ECC enablement + * 0b1..Protects addresses from region 3 with ECC + */ +#define DDRC_ECC_REG_3_REG_3_EN(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ECC_REG_3_REG_3_EN_SHIFT)) & DDRC_ECC_REG_3_REG_3_EN_MASK) +/*! @} */ + +/*! @name ECC_REG_4 - ECC Region 4 Configuration */ +/*! @{ */ + +#define DDRC_ECC_REG_4_REG_4_EA_MASK (0xFFFU) +#define DDRC_ECC_REG_4_REG_4_EA_SHIFT (0U) +/*! REG_4_EA - Region 4 End Address */ +#define DDRC_ECC_REG_4_REG_4_EA(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ECC_REG_4_REG_4_EA_SHIFT)) & DDRC_ECC_REG_4_REG_4_EA_MASK) + +#define DDRC_ECC_REG_4_REG_4_SA_MASK (0xFFF0000U) +#define DDRC_ECC_REG_4_REG_4_SA_SHIFT (16U) +/*! REG_4_SA - Region 4 Start Address */ +#define DDRC_ECC_REG_4_REG_4_SA(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ECC_REG_4_REG_4_SA_SHIFT)) & DDRC_ECC_REG_4_REG_4_SA_MASK) + +#define DDRC_ECC_REG_4_REG_4_EN_MASK (0x80000000U) +#define DDRC_ECC_REG_4_REG_4_EN_SHIFT (31U) +/*! REG_4_EN - Region 4 Enable + * 0b0..Does not use region 4 for ECC enablement + * 0b1..Protects addresses from region 4 with ECC + */ +#define DDRC_ECC_REG_4_REG_4_EN(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ECC_REG_4_REG_4_EN_SHIFT)) & DDRC_ECC_REG_4_REG_4_EN_MASK) +/*! @} */ + +/*! @name ECC_REG_5 - ECC Region 5 Configuration */ +/*! @{ */ + +#define DDRC_ECC_REG_5_REG_5_EA_MASK (0xFFFU) +#define DDRC_ECC_REG_5_REG_5_EA_SHIFT (0U) +/*! REG_5_EA - Region 5 End Address */ +#define DDRC_ECC_REG_5_REG_5_EA(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ECC_REG_5_REG_5_EA_SHIFT)) & DDRC_ECC_REG_5_REG_5_EA_MASK) + +#define DDRC_ECC_REG_5_REG_5_SA_MASK (0xFFF0000U) +#define DDRC_ECC_REG_5_REG_5_SA_SHIFT (16U) +/*! REG_5_SA - Region 5 Start Address */ +#define DDRC_ECC_REG_5_REG_5_SA(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ECC_REG_5_REG_5_SA_SHIFT)) & DDRC_ECC_REG_5_REG_5_SA_MASK) + +#define DDRC_ECC_REG_5_REG_5_EN_MASK (0x80000000U) +#define DDRC_ECC_REG_5_REG_5_EN_SHIFT (31U) +/*! REG_5_EN - Region 5 Enable + * 0b0..Does not use region 5 for ECC enablement + * 0b1..Protects addresses from region 5 with ECC + */ +#define DDRC_ECC_REG_5_REG_5_EN(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ECC_REG_5_REG_5_EN_SHIFT)) & DDRC_ECC_REG_5_REG_5_EN_MASK) +/*! @} */ + +/*! @name ECC_REG_6 - ECC Region 6 Configuration */ +/*! @{ */ + +#define DDRC_ECC_REG_6_REG_6_EA_MASK (0xFFFU) +#define DDRC_ECC_REG_6_REG_6_EA_SHIFT (0U) +/*! REG_6_EA - Region 6 End Address */ +#define DDRC_ECC_REG_6_REG_6_EA(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ECC_REG_6_REG_6_EA_SHIFT)) & DDRC_ECC_REG_6_REG_6_EA_MASK) + +#define DDRC_ECC_REG_6_REG_6_SA_MASK (0xFFF0000U) +#define DDRC_ECC_REG_6_REG_6_SA_SHIFT (16U) +/*! REG_6_SA - Region 6 Start Address */ +#define DDRC_ECC_REG_6_REG_6_SA(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ECC_REG_6_REG_6_SA_SHIFT)) & DDRC_ECC_REG_6_REG_6_SA_MASK) + +#define DDRC_ECC_REG_6_REG_6_EN_MASK (0x80000000U) +#define DDRC_ECC_REG_6_REG_6_EN_SHIFT (31U) +/*! REG_6_EN - Region 6 Enable + * 0b0..Does not use region 6 for ECC enablement + * 0b1..Protects addresses from region 6 with ECC + */ +#define DDRC_ECC_REG_6_REG_6_EN(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ECC_REG_6_REG_6_EN_SHIFT)) & DDRC_ECC_REG_6_REG_6_EN_MASK) +/*! @} */ + +/*! @name ECC_REG_7 - ECC Region 7 Configuration */ +/*! @{ */ + +#define DDRC_ECC_REG_7_REG_7_EA_MASK (0xFFFU) +#define DDRC_ECC_REG_7_REG_7_EA_SHIFT (0U) +/*! REG_7_EA - Region 7 End Address */ +#define DDRC_ECC_REG_7_REG_7_EA(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ECC_REG_7_REG_7_EA_SHIFT)) & DDRC_ECC_REG_7_REG_7_EA_MASK) + +#define DDRC_ECC_REG_7_REG_7_SA_MASK (0xFFF0000U) +#define DDRC_ECC_REG_7_REG_7_SA_SHIFT (16U) +/*! REG_7_SA - Region 7 Start Address */ +#define DDRC_ECC_REG_7_REG_7_SA(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ECC_REG_7_REG_7_SA_SHIFT)) & DDRC_ECC_REG_7_REG_7_SA_MASK) + +#define DDRC_ECC_REG_7_REG_7_EN_MASK (0x80000000U) +#define DDRC_ECC_REG_7_REG_7_EN_SHIFT (31U) +/*! REG_7_EN - Region 7 Enable + * 0b0..Does not use region 7 for ECC enablement + * 0b1..Protects addresses from region 7 with ECC + */ +#define DDRC_ECC_REG_7_REG_7_EN(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ECC_REG_7_REG_7_EN_SHIFT)) & DDRC_ECC_REG_7_REG_7_EN_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group DDRC_Register_Masks */ + + +/* DDRC - Peripheral instance base addresses */ +/** Peripheral DDR_CTRL base address */ +#define DDR_CTRL_BASE (0x4E300000u) +/** Peripheral DDR_CTRL base pointer */ +#define DDR_CTRL ((DDRC_Type *)DDR_CTRL_BASE) +/** Array initializer of DDRC peripheral base addresses */ +#define DDRC_BASE_ADDRS { DDR_CTRL_BASE } +/** Array initializer of DDRC peripheral base pointers */ +#define DDRC_BASE_PTRS { DDR_CTRL } + +/*! + * @} + */ /* end of group DDRC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- DMA Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup DMA_Peripheral_Access_Layer DMA Peripheral Access Layer + * @{ + */ + +/** DMA - Register Layout Typedef */ +typedef struct { + __IO uint32_t MP_CSR; /**< Management Page Control, offset: 0x0 */ + __I uint32_t MP_ES; /**< Management Page Error Status, offset: 0x4 */ + __I uint32_t MP_INT; /**< Management Page Interrupt Request Status, offset: 0x8 */ + __I uint32_t MP_HRS; /**< Management Page Hardware Request Status, offset: 0xC */ + uint8_t RESERVED_0[240]; + __IO uint32_t CH_GRPRI[31]; /**< Channel Arbitration Group, array offset: 0x100, array step: 0x4 */ +} DMA_Type; + +/* ---------------------------------------------------------------------------- + -- DMA Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup DMA_Register_Masks DMA Register Masks + * @{ + */ + +/*! @name MP_CSR - Management Page Control */ +/*! @{ */ + +#define DMA_MP_CSR_EDBG_MASK (0x2U) +#define DMA_MP_CSR_EDBG_SHIFT (1U) +/*! EDBG - Enable Debug + * 0b0..Debug mode disabled + * 0b1..Debug mode is enabled. + */ +#define DMA_MP_CSR_EDBG(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_CSR_EDBG_SHIFT)) & DMA_MP_CSR_EDBG_MASK) + +#define DMA_MP_CSR_ERCA_MASK (0x4U) +#define DMA_MP_CSR_ERCA_SHIFT (2U) +/*! ERCA - Enable Round Robin Channel Arbitration + * 0b0..Round-robin channel arbitration disabled + * 0b1..Round-robin channel arbitration enabled + */ +#define DMA_MP_CSR_ERCA(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_CSR_ERCA_SHIFT)) & DMA_MP_CSR_ERCA_MASK) + +#define DMA_MP_CSR_HAE_MASK (0x10U) +#define DMA_MP_CSR_HAE_SHIFT (4U) +/*! HAE - Halt After Error + * 0b0..Normal operation + * 0b1..Any error causes the HALT field to be set to 1 + */ +#define DMA_MP_CSR_HAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_CSR_HAE_SHIFT)) & DMA_MP_CSR_HAE_MASK) + +#define DMA_MP_CSR_HALT_MASK (0x20U) +#define DMA_MP_CSR_HALT_SHIFT (5U) +/*! HALT - Halt DMA Operations + * 0b0..Normal operation + * 0b1..Stall the start of any new channels + */ +#define DMA_MP_CSR_HALT(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_CSR_HALT_SHIFT)) & DMA_MP_CSR_HALT_MASK) + +#define DMA_MP_CSR_GCLC_MASK (0x40U) +#define DMA_MP_CSR_GCLC_SHIFT (6U) +/*! GCLC - Global Channel Linking Control + * 0b0..Channel linking disabled for all channels + * 0b1..Channel linking available and controlled by each channel's link settings + */ +#define DMA_MP_CSR_GCLC(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_CSR_GCLC_SHIFT)) & DMA_MP_CSR_GCLC_MASK) + +#define DMA_MP_CSR_GMRC_MASK (0x80U) +#define DMA_MP_CSR_GMRC_SHIFT (7U) +/*! GMRC - Global Master ID Replication Control + * 0b0..Master ID replication disabled for all channels + * 0b1..Master ID replication available and controlled by each channel's CHn_SBR[EMI] setting + */ +#define DMA_MP_CSR_GMRC(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_CSR_GMRC_SHIFT)) & DMA_MP_CSR_GMRC_MASK) + +#define DMA_MP_CSR_ECX_MASK (0x100U) +#define DMA_MP_CSR_ECX_SHIFT (8U) +/*! ECX - Cancel Transfer With Error + * 0b0..Normal operation + * 0b1..Cancel the remaining data transfer + */ +#define DMA_MP_CSR_ECX(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_CSR_ECX_SHIFT)) & DMA_MP_CSR_ECX_MASK) + +#define DMA_MP_CSR_CX_MASK (0x200U) +#define DMA_MP_CSR_CX_SHIFT (9U) +/*! CX - Cancel Transfer + * 0b0..Normal operation + * 0b1..Cancel the remaining data transfer + */ +#define DMA_MP_CSR_CX(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_CSR_CX_SHIFT)) & DMA_MP_CSR_CX_MASK) + +#define DMA_MP_CSR_ACTIVE_ID_MASK (0x1F000000U) +#define DMA_MP_CSR_ACTIVE_ID_SHIFT (24U) +/*! ACTIVE_ID - Active Channel ID */ +#define DMA_MP_CSR_ACTIVE_ID(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_CSR_ACTIVE_ID_SHIFT)) & DMA_MP_CSR_ACTIVE_ID_MASK) + +#define DMA_MP_CSR_ACTIVE_MASK (0x80000000U) +#define DMA_MP_CSR_ACTIVE_SHIFT (31U) +/*! ACTIVE - DMA Active Status + * 0b0..eDMA is idle + * 0b1..eDMA is executing a channel + */ +#define DMA_MP_CSR_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_CSR_ACTIVE_SHIFT)) & DMA_MP_CSR_ACTIVE_MASK) +/*! @} */ + +/*! @name MP_ES - Management Page Error Status */ +/*! @{ */ + +#define DMA_MP_ES_DBE_MASK (0x1U) +#define DMA_MP_ES_DBE_SHIFT (0U) +/*! DBE - Destination Bus Error + * 0b0..No destination bus error + * 0b1..Last recorded error was a bus error on a destination write + */ +#define DMA_MP_ES_DBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_ES_DBE_SHIFT)) & DMA_MP_ES_DBE_MASK) + +#define DMA_MP_ES_SBE_MASK (0x2U) +#define DMA_MP_ES_SBE_SHIFT (1U) +/*! SBE - Source Bus Error + * 0b0..No source bus error + * 0b1..Last recorded error was a bus error on a source read + */ +#define DMA_MP_ES_SBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_ES_SBE_SHIFT)) & DMA_MP_ES_SBE_MASK) + +#define DMA_MP_ES_SGE_MASK (0x4U) +#define DMA_MP_ES_SGE_SHIFT (2U) +/*! SGE - Scatter/Gather Configuration Error + * 0b0..No scatter/gather configuration error + * 0b1..Last recorded error was a configuration error detected in the TCDn_DLAST_SGA field + */ +#define DMA_MP_ES_SGE(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_ES_SGE_SHIFT)) & DMA_MP_ES_SGE_MASK) + +#define DMA_MP_ES_NCE_MASK (0x8U) +#define DMA_MP_ES_NCE_SHIFT (3U) +/*! NCE - NBYTES/CITER Configuration Error + * 0b0..No NBYTES/CITER configuration error + * 0b1..The last recorded error was NBYTES equal to zero or a CITER not equal to BITER error + */ +#define DMA_MP_ES_NCE(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_ES_NCE_SHIFT)) & DMA_MP_ES_NCE_MASK) + +#define DMA_MP_ES_DOE_MASK (0x10U) +#define DMA_MP_ES_DOE_SHIFT (4U) +/*! DOE - Destination Offset Error + * 0b0..No destination offset configuration error + * 0b1..Last recorded error was a configuration error detected in the TCDn_DOFF field + */ +#define DMA_MP_ES_DOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_ES_DOE_SHIFT)) & DMA_MP_ES_DOE_MASK) + +#define DMA_MP_ES_DAE_MASK (0x20U) +#define DMA_MP_ES_DAE_SHIFT (5U) +/*! DAE - Destination Address Error + * 0b0..No destination address configuration error + * 0b1..Last recorded error was a configuration error detected in the TCDn_DADDR field + */ +#define DMA_MP_ES_DAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_ES_DAE_SHIFT)) & DMA_MP_ES_DAE_MASK) + +#define DMA_MP_ES_SOE_MASK (0x40U) +#define DMA_MP_ES_SOE_SHIFT (6U) +/*! SOE - Source Offset Error + * 0b0..No source offset configuration error + * 0b1..Last recorded error was a configuration error detected in the TCDn_SOFF field + */ +#define DMA_MP_ES_SOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_ES_SOE_SHIFT)) & DMA_MP_ES_SOE_MASK) + +#define DMA_MP_ES_SAE_MASK (0x80U) +#define DMA_MP_ES_SAE_SHIFT (7U) +/*! SAE - Source Address Error + * 0b0..No source address configuration error + * 0b1..Last recorded error was a configuration error detected in the TCDn_SADDR field + */ +#define DMA_MP_ES_SAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_ES_SAE_SHIFT)) & DMA_MP_ES_SAE_MASK) + +#define DMA_MP_ES_ECX_MASK (0x100U) +#define DMA_MP_ES_ECX_SHIFT (8U) +/*! ECX - Transfer Canceled + * 0b0..No canceled transfers + * 0b1..Last recorded entry was a canceled transfer by the error cancel transfer input + */ +#define DMA_MP_ES_ECX(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_ES_ECX_SHIFT)) & DMA_MP_ES_ECX_MASK) + +#define DMA_MP_ES_ERRCHN_MASK (0x1F000000U) +#define DMA_MP_ES_ERRCHN_SHIFT (24U) +/*! ERRCHN - Error Channel Number or Canceled Channel Number */ +#define DMA_MP_ES_ERRCHN(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_ES_ERRCHN_SHIFT)) & DMA_MP_ES_ERRCHN_MASK) + +#define DMA_MP_ES_VLD_MASK (0x80000000U) +#define DMA_MP_ES_VLD_SHIFT (31U) +/*! VLD - Valid + * 0b0..No CHn_ES[ERR] fields are set to 1 + * 0b1..At least one CHn_ES[ERR] field is set to 1, indicating a valid error exists that software has not cleared + */ +#define DMA_MP_ES_VLD(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_ES_VLD_SHIFT)) & DMA_MP_ES_VLD_MASK) +/*! @} */ + +/*! @name MP_INT - Management Page Interrupt Request Status */ +/*! @{ */ + +#define DMA_MP_INT_INT_MASK (0x7FFFFFFFU) +#define DMA_MP_INT_INT_SHIFT (0U) +/*! INT - Interrupt Request Status */ +#define DMA_MP_INT_INT(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_INT_INT_SHIFT)) & DMA_MP_INT_INT_MASK) +/*! @} */ + +/*! @name MP_HRS - Management Page Hardware Request Status */ +/*! @{ */ + +#define DMA_MP_HRS_HRS_MASK (0xFFFFFFFFU) +#define DMA_MP_HRS_HRS_SHIFT (0U) +/*! HRS - Hardware Request Status */ +#define DMA_MP_HRS_HRS(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_HRS_HRS_SHIFT)) & DMA_MP_HRS_HRS_MASK) +/*! @} */ + +/*! @name CH_GRPRI - Channel Arbitration Group */ +/*! @{ */ + +#define DMA_CH_GRPRI_GRPRI_MASK (0x1FU) +#define DMA_CH_GRPRI_GRPRI_SHIFT (0U) +/*! GRPRI - Arbitration Group For Channel n */ +#define DMA_CH_GRPRI_GRPRI(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_GRPRI_GRPRI_SHIFT)) & DMA_CH_GRPRI_GRPRI_MASK) +/*! @} */ + +/* The count of DMA_CH_GRPRI */ +#define DMA_CH_GRPRI_COUNT (31U) + + +/*! + * @} + */ /* end of group DMA_Register_Masks */ + + +/* DMA - Peripheral instance base addresses */ +/** Peripheral DMA3 base address */ +#define DMA3_BASE (0x44000000u) +/** Peripheral DMA3 base pointer */ +#define DMA3 ((DMA_Type *)DMA3_BASE) +/** Array initializer of DMA peripheral base addresses */ +#define DMA_BASE_ADDRS { DMA3_BASE } +/** Array initializer of DMA peripheral base pointers */ +#define DMA_BASE_PTRS { DMA3 } + +/*! + * @} + */ /* end of group DMA_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- DMA4 Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup DMA4_Peripheral_Access_Layer DMA4 Peripheral Access Layer + * @{ + */ + +/** DMA4 - Register Layout Typedef */ +typedef struct { + __IO uint32_t CSR; /**< Management Page Control Register, offset: 0x0 */ + __I uint32_t ES; /**< Management Page Error Status Register, offset: 0x4 */ + __I uint32_t INT_LOW; /**< Management Page Interrupt Request Status Register - Low, offset: 0x8 */ + __I uint32_t INT_HIGH; /**< Management Page Interrupt Request Status Register- High, offset: 0xC */ + __I uint32_t HRS_LOW; /**< Management Page Hardware Request Status Register - Low, offset: 0x10 */ + __I uint32_t HRS_HIGH; /**< Management Page Hardware Request Status Register - High, offset: 0x14 */ + uint8_t RESERVED_0[232]; + __IO uint32_t CH_GRPRI[64]; /**< Channel Arbitration Group Register, array offset: 0x100, array step: 0x4 */ +} DMA4_Type; + +/* ---------------------------------------------------------------------------- + -- DMA4 Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup DMA4_Register_Masks DMA4 Register Masks + * @{ + */ + +/*! @name CSR - Management Page Control Register */ +/*! @{ */ + +#define DMA4_CSR_EDBG_MASK (0x2U) +#define DMA4_CSR_EDBG_SHIFT (1U) +/*! EDBG - Enable Debug + * 0b0..Debug mode is disabled. + * 0b1..Debug mode is enabled. + */ +#define DMA4_CSR_EDBG(x) (((uint32_t)(((uint32_t)(x)) << DMA4_CSR_EDBG_SHIFT)) & DMA4_CSR_EDBG_MASK) + +#define DMA4_CSR_ERCA_MASK (0x4U) +#define DMA4_CSR_ERCA_SHIFT (2U) +/*! ERCA - Enable Round Robin Channel Arbitration + * 0b0..Round robin channel arbitration is disabled. + * 0b1..Round robin channel arbitration is enabled. + */ +#define DMA4_CSR_ERCA(x) (((uint32_t)(((uint32_t)(x)) << DMA4_CSR_ERCA_SHIFT)) & DMA4_CSR_ERCA_MASK) + +#define DMA4_CSR_HAE_MASK (0x10U) +#define DMA4_CSR_HAE_SHIFT (4U) +/*! HAE - Halt After Error + * 0b0..Normal operation + * 0b1..Any error causes the HALT bit to set. Subsequently, all service requests are ignored until the HALT bit is cleared. + */ +#define DMA4_CSR_HAE(x) (((uint32_t)(((uint32_t)(x)) << DMA4_CSR_HAE_SHIFT)) & DMA4_CSR_HAE_MASK) + +#define DMA4_CSR_HALT_MASK (0x20U) +#define DMA4_CSR_HALT_SHIFT (5U) +/*! HALT - Halt DMA Operations + * 0b0..Normal operation + * 0b1..Stall the start of any new channels. Executing channels are allowed to complete. Channel execution resumes when this bit is cleared. + */ +#define DMA4_CSR_HALT(x) (((uint32_t)(((uint32_t)(x)) << DMA4_CSR_HALT_SHIFT)) & DMA4_CSR_HALT_MASK) + +#define DMA4_CSR_GCLC_MASK (0x40U) +#define DMA4_CSR_GCLC_SHIFT (6U) +/*! GCLC - Global Channel Linking Control + * 0b0..Channel linking is disabled for all channels. + * 0b1..Channel linking is available and controlled by each channel's link settings. + */ +#define DMA4_CSR_GCLC(x) (((uint32_t)(((uint32_t)(x)) << DMA4_CSR_GCLC_SHIFT)) & DMA4_CSR_GCLC_MASK) + +#define DMA4_CSR_GMRC_MASK (0x80U) +#define DMA4_CSR_GMRC_SHIFT (7U) +/*! GMRC - Global Master ID Replication Control + * 0b0..Master ID replication is disabled for all channels. + * 0b1..Master ID replication is available and is controlled by each channel's CHn_SBR[EMI] setting. + */ +#define DMA4_CSR_GMRC(x) (((uint32_t)(((uint32_t)(x)) << DMA4_CSR_GMRC_SHIFT)) & DMA4_CSR_GMRC_MASK) + +#define DMA4_CSR_ECX_MASK (0x100U) +#define DMA4_CSR_ECX_SHIFT (8U) +/*! ECX - Cancel Transfer with Error + * 0b0..Normal operation + * 0b1..Cancel the remaining data transfer in the same fashion as the CX bit. Stop the executing channel and + * force the minor loop to finish. The cancel takes effect after the last write of the current read/write + * sequence. The ECX bit clears itself after the cancel is honored. In addition to cancelling the transfer, ECX + * treats the cancel as an error condition, thus updating the Error Status register (DMAx_ES) and generating an + * optional error interrupt. + */ +#define DMA4_CSR_ECX(x) (((uint32_t)(((uint32_t)(x)) << DMA4_CSR_ECX_SHIFT)) & DMA4_CSR_ECX_MASK) + +#define DMA4_CSR_CX_MASK (0x200U) +#define DMA4_CSR_CX_SHIFT (9U) +/*! CX - Cancel Transfer + * 0b0..Normal operation + * 0b1..Cancel the remaining data transfer. Stop the executing channel and force the minor loop to finish. The + * cancel takes effect after the last write of the current read/write sequence. The CX bit clears itself after + * the cancel has been honored. This cancel retires the channel normally as if the minor loop was completed. + */ +#define DMA4_CSR_CX(x) (((uint32_t)(((uint32_t)(x)) << DMA4_CSR_CX_SHIFT)) & DMA4_CSR_CX_MASK) + +#define DMA4_CSR_VER_MASK (0xFF0000U) +#define DMA4_CSR_VER_SHIFT (16U) +/*! VER - eDMA version */ +#define DMA4_CSR_VER(x) (((uint32_t)(((uint32_t)(x)) << DMA4_CSR_VER_SHIFT)) & DMA4_CSR_VER_MASK) + +#define DMA4_CSR_ACTIVE_ID_MASK (0x3F000000U) +#define DMA4_CSR_ACTIVE_ID_SHIFT (24U) +/*! ACTIVE_ID - Active channel ID */ +#define DMA4_CSR_ACTIVE_ID(x) (((uint32_t)(((uint32_t)(x)) << DMA4_CSR_ACTIVE_ID_SHIFT)) & DMA4_CSR_ACTIVE_ID_MASK) + +#define DMA4_CSR_ACTIVE_MASK (0x80000000U) +#define DMA4_CSR_ACTIVE_SHIFT (31U) +/*! ACTIVE - DMA Active Status + * 0b0..eDMA is idle. + * 0b1..eDMA is executing a channel. + */ +#define DMA4_CSR_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << DMA4_CSR_ACTIVE_SHIFT)) & DMA4_CSR_ACTIVE_MASK) +/*! @} */ + +/*! @name ES - Management Page Error Status Register */ +/*! @{ */ + +#define DMA4_ES_DBE_MASK (0x1U) +#define DMA4_ES_DBE_SHIFT (0U) +/*! DBE - Destination Bus Error + * 0b0..No destination bus error + * 0b1..The last recorded error was a bus error on a destination write + */ +#define DMA4_ES_DBE(x) (((uint32_t)(((uint32_t)(x)) << DMA4_ES_DBE_SHIFT)) & DMA4_ES_DBE_MASK) + +#define DMA4_ES_SBE_MASK (0x2U) +#define DMA4_ES_SBE_SHIFT (1U) +/*! SBE - Source Bus Error + * 0b0..No source bus error + * 0b1..The last recorded error was a bus error on a source read + */ +#define DMA4_ES_SBE(x) (((uint32_t)(((uint32_t)(x)) << DMA4_ES_SBE_SHIFT)) & DMA4_ES_SBE_MASK) + +#define DMA4_ES_SGE_MASK (0x4U) +#define DMA4_ES_SGE_SHIFT (2U) +/*! SGE - Scatter/Gather Configuration Error + * 0b0..No scatter/gather configuration error + * 0b1..The last recorded error was a configuration error detected in the TCDn_DLASTSGA field. This field is + * checked at the beginning of a scatter/gather operation after major loop completion if TCDn_CSR[ESG] is + * enabled. TCDn_DLASTSGA is not on a 32 byte boundary. + */ +#define DMA4_ES_SGE(x) (((uint32_t)(((uint32_t)(x)) << DMA4_ES_SGE_SHIFT)) & DMA4_ES_SGE_MASK) + +#define DMA4_ES_NCE_MASK (0x8U) +#define DMA4_ES_NCE_SHIFT (3U) +/*! NCE - NBYTES/CITER Configuration Error + * 0b0..No NBYTES/CITER configuration error + * 0b1..The last recorded error was NBYTES equal to zero or a CITER not equal to BITER error + */ +#define DMA4_ES_NCE(x) (((uint32_t)(((uint32_t)(x)) << DMA4_ES_NCE_SHIFT)) & DMA4_ES_NCE_MASK) + +#define DMA4_ES_DOE_MASK (0x10U) +#define DMA4_ES_DOE_SHIFT (4U) +/*! DOE - Destination Offset Error + * 0b0..No destination offset configuration error + * 0b1..The last recorded error was a configuration error detected in the TCDn_DOFF field. TCDn_DOFF is inconsistent with TCDn_ATTR[DSIZE]. + */ +#define DMA4_ES_DOE(x) (((uint32_t)(((uint32_t)(x)) << DMA4_ES_DOE_SHIFT)) & DMA4_ES_DOE_MASK) + +#define DMA4_ES_DAE_MASK (0x20U) +#define DMA4_ES_DAE_SHIFT (5U) +/*! DAE - Destination Address Error + * 0b0..No destination address configuration error + * 0b1..The last recorded error was a configuration error detected in the TCDn_DADDR field. TCDn_DADDR is inconsistent with TCDn_ATTR[DSIZE]. + */ +#define DMA4_ES_DAE(x) (((uint32_t)(((uint32_t)(x)) << DMA4_ES_DAE_SHIFT)) & DMA4_ES_DAE_MASK) + +#define DMA4_ES_SOE_MASK (0x40U) +#define DMA4_ES_SOE_SHIFT (6U) +/*! SOE - Source Offset Error + * 0b0..No source offset configuration error + * 0b1..The last recorded error was a configuration error detected in the TCDn_SOFF field. TCDn_SOFF is inconsistent with TCDn_ATTR[SSIZE]. + */ +#define DMA4_ES_SOE(x) (((uint32_t)(((uint32_t)(x)) << DMA4_ES_SOE_SHIFT)) & DMA4_ES_SOE_MASK) + +#define DMA4_ES_SAE_MASK (0x80U) +#define DMA4_ES_SAE_SHIFT (7U) +/*! SAE - Source Address Error + * 0b0..No source address configuration error. + * 0b1..The last recorded error was a configuration error detected in the TCDn_SADDR field. TCDn_SADDR is inconsistent with TCDn_ATTR[SSIZE]. + */ +#define DMA4_ES_SAE(x) (((uint32_t)(((uint32_t)(x)) << DMA4_ES_SAE_SHIFT)) & DMA4_ES_SAE_MASK) + +#define DMA4_ES_ECX_MASK (0x100U) +#define DMA4_ES_ECX_SHIFT (8U) +/*! ECX - Transfer Canceled + * 0b0..No canceled transfers + * 0b1..The last recorded entry was a canceled transfer by the error cancel transfer input. + */ +#define DMA4_ES_ECX(x) (((uint32_t)(((uint32_t)(x)) << DMA4_ES_ECX_SHIFT)) & DMA4_ES_ECX_MASK) + +#define DMA4_ES_ERRCHN_MASK (0x3F000000U) +#define DMA4_ES_ERRCHN_SHIFT (24U) +/*! ERRCHN - Error Channel Number or Canceled Channel Number */ +#define DMA4_ES_ERRCHN(x) (((uint32_t)(((uint32_t)(x)) << DMA4_ES_ERRCHN_SHIFT)) & DMA4_ES_ERRCHN_MASK) + +#define DMA4_ES_VLD_MASK (0x80000000U) +#define DMA4_ES_VLD_SHIFT (31U) +/*! VLD - Valid + * 0b0..No ERR bits are set. + * 0b1..At least one ERR bit is set indicating a valid error exists that has not been cleared. + */ +#define DMA4_ES_VLD(x) (((uint32_t)(((uint32_t)(x)) << DMA4_ES_VLD_SHIFT)) & DMA4_ES_VLD_MASK) +/*! @} */ + +/*! @name INT_LOW - Management Page Interrupt Request Status Register - Low */ +/*! @{ */ + +#define DMA4_INT_LOW_INT_MASK (0xFFFFFFFFU) +#define DMA4_INT_LOW_INT_SHIFT (0U) +/*! INT - Interrupt Request Status for channels 31 - 0 */ +#define DMA4_INT_LOW_INT(x) (((uint32_t)(((uint32_t)(x)) << DMA4_INT_LOW_INT_SHIFT)) & DMA4_INT_LOW_INT_MASK) +/*! @} */ + +/*! @name INT_HIGH - Management Page Interrupt Request Status Register- High */ +/*! @{ */ + +#define DMA4_INT_HIGH_INT_MASK (0xFFFFFFFFU) +#define DMA4_INT_HIGH_INT_SHIFT (0U) +/*! INT - Interrupt Request Status for channels 63-32 */ +#define DMA4_INT_HIGH_INT(x) (((uint32_t)(((uint32_t)(x)) << DMA4_INT_HIGH_INT_SHIFT)) & DMA4_INT_HIGH_INT_MASK) +/*! @} */ + +/*! @name HRS_LOW - Management Page Hardware Request Status Register - Low */ +/*! @{ */ + +#define DMA4_HRS_LOW_HRS_MASK (0xFFFFFFFFU) +#define DMA4_HRS_LOW_HRS_SHIFT (0U) +/*! HRS - Hardware Request Status for channels 31 - 0 + * 0b00000000000000000000000000000000..A hardware service request for the channel is not present + * 0b00000000000000000000000000000001..A hardware service request for channel 0 is present + */ +#define DMA4_HRS_LOW_HRS(x) (((uint32_t)(((uint32_t)(x)) << DMA4_HRS_LOW_HRS_SHIFT)) & DMA4_HRS_LOW_HRS_MASK) +/*! @} */ + +/*! @name HRS_HIGH - Management Page Hardware Request Status Register - High */ +/*! @{ */ + +#define DMA4_HRS_HIGH_HRS_MASK (0xFFFFFFFFU) +#define DMA4_HRS_HIGH_HRS_SHIFT (0U) +/*! HRS - Hardware Request Status for channels 63-32 + * 0b00000000000000000000000000000000..A hardware service request for the channel is not present + * 0b00000000000000000000000000000001..A hardware service request for channel 0 is present + */ +#define DMA4_HRS_HIGH_HRS(x) (((uint32_t)(((uint32_t)(x)) << DMA4_HRS_HIGH_HRS_SHIFT)) & DMA4_HRS_HIGH_HRS_MASK) +/*! @} */ + +/*! @name CH_GRPRI - Channel Arbitration Group Register */ +/*! @{ */ + +#define DMA4_CH_GRPRI_GRPRI_MASK (0x3FU) +#define DMA4_CH_GRPRI_GRPRI_SHIFT (0U) +/*! GRPRI - Arbitration group per channel. */ +#define DMA4_CH_GRPRI_GRPRI(x) (((uint32_t)(((uint32_t)(x)) << DMA4_CH_GRPRI_GRPRI_SHIFT)) & DMA4_CH_GRPRI_GRPRI_MASK) +/*! @} */ + +/* The count of DMA4_CH_GRPRI */ +#define DMA4_CH_GRPRI_COUNT (64U) + + +/*! + * @} + */ /* end of group DMA4_Register_Masks */ + + +/* DMA4 - Peripheral instance base addresses */ +/** Peripheral DMA4 base address */ +#define DMA4_BASE (0u) +/** Peripheral DMA4 base pointer */ +#define DMA4 ((DMA4_Type *)DMA4_BASE) +/** Array initializer of DMA4 peripheral base addresses */ +#define DMA4_BASE_ADDRS { DMA4_BASE } +/** Array initializer of DMA4 peripheral base pointers */ +#define DMA4_BASE_PTRS { DMA4 } + +/*! + * @} + */ /* end of group DMA4_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- DMA4_TCD Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup DMA4_TCD_Peripheral_Access_Layer DMA4_TCD Peripheral Access Layer + * @{ + */ + +/** DMA4_TCD - Register Layout Typedef */ +typedef struct { + struct { /* offset: 0x0, array step: 0x1000 */ + __IO uint32_t CH_CSR; /**< Channel Control and Status Register, array offset: 0x0, array step: 0x1000 */ + __IO uint32_t CH_ES; /**< Channel Error Status Register, array offset: 0x4, array step: 0x1000 */ + __IO uint32_t CH_INT; /**< Channel Interrupt Status Register, array offset: 0x8, array step: 0x1000 */ + __IO uint32_t CH_SBR; /**< Channel System Bus Register, array offset: 0xC, array step: 0x1000 */ + __IO uint32_t CH_PRI; /**< Channel Priority Register, array offset: 0x10, array step: 0x1000 */ + __IO uint32_t CH_MUX; /**< Channel Multiplexor Configuration, array offset: 0x14, array step: 0x1000 */ + __IO uint16_t CH_MATTR; /**< Memory Attributes Register, array offset: 0x18, array step: 0x1000 */ + uint8_t RESERVED_0[6]; + __IO uint32_t SADDR; /**< TCD Source Address Register, array offset: 0x20, array step: 0x1000 */ + __IO uint16_t SOFF; /**< TCD Signed Source Address Offset Register, array offset: 0x24, array step: 0x1000 */ + __IO uint16_t ATTR; /**< TCD Transfer Attributes Register, array offset: 0x26, array step: 0x1000 */ + union { /* offset: 0x28, array step: 0x1000 */ + __IO uint32_t NBYTES_MLOFFNO; /**< TCD Transfer Size without Minor Loop Offsets Register, array offset: 0x28, array step: 0x1000 */ + __IO uint32_t NBYTES_MLOFFYES; /**< TCD Transfer Size with Minor Loop Offsets Register, array offset: 0x28, array step: 0x1000 */ + }; + __IO uint32_t SLAST_SDA; /**< TCD Last Source Address Adjustment / Store DADDR Address Register, array offset: 0x2C, array step: 0x1000 */ + __IO uint32_t DADDR; /**< TCD Destination Address Register, array offset: 0x30, array step: 0x1000 */ + __IO uint16_t DOFF; /**< TCD Signed Destination Address Offset Register, array offset: 0x34, array step: 0x1000 */ + union { /* offset: 0x36, array step: 0x1000 */ + __IO uint16_t CITER_ELINKNO; /**< TCD Current Major Loop Count (Minor Loop Channel Linking Disabled) Register, array offset: 0x36, array step: 0x1000 */ + __IO uint16_t CITER_ELINKYES; /**< TCD Current Major Loop Count (Minor Loop Channel Linking Enabled) Register, array offset: 0x36, array step: 0x1000 */ + }; + __IO uint32_t DLAST_SGA; /**< TCD Last Destination Address Adjustment / Scatter Gather Address Register, array offset: 0x38, array step: 0x1000 */ + __IO uint16_t CSR; /**< TCD Control and Status Register, array offset: 0x3C, array step: 0x1000 */ + union { /* offset: 0x3E, array step: 0x1000 */ + __IO uint16_t BITER_ELINKNO; /**< TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled) Register, array offset: 0x3E, array step: 0x1000 */ + __IO uint16_t BITER_ELINKYES; /**< TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled) Register, array offset: 0x3E, array step: 0x1000 */ + }; + uint8_t RESERVED_1[4032]; + } TCD[64]; +} DMA4_TCD_Type; + +/* ---------------------------------------------------------------------------- + -- DMA4_TCD Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup DMA4_TCD_Register_Masks DMA4_TCD Register Masks + * @{ + */ + +/*! @name CH_CSR - Channel Control and Status Register */ +/*! @{ */ + +#define DMA4_TCD_CH_CSR_ERQ_MASK (0x1U) +#define DMA4_TCD_CH_CSR_ERQ_SHIFT (0U) +/*! ERQ - Enable DMA Request + * 0b0..The DMA hardware request signal for the corresponding channel is disabled. + * 0b1..The DMA hardware request signal for the corresponding channel is enabled. + */ +#define DMA4_TCD_CH_CSR_ERQ(x) (((uint32_t)(((uint32_t)(x)) << DMA4_TCD_CH_CSR_ERQ_SHIFT)) & DMA4_TCD_CH_CSR_ERQ_MASK) + +#define DMA4_TCD_CH_CSR_EARQ_MASK (0x2U) +#define DMA4_TCD_CH_CSR_EARQ_SHIFT (1U) +/*! EARQ - Enable Asynchronous DMA Request + * 0b0..Disable asynchronous DMA request for the channel. + * 0b1..Enable asynchronous DMA request for the channel. + */ +#define DMA4_TCD_CH_CSR_EARQ(x) (((uint32_t)(((uint32_t)(x)) << DMA4_TCD_CH_CSR_EARQ_SHIFT)) & DMA4_TCD_CH_CSR_EARQ_MASK) + +#define DMA4_TCD_CH_CSR_EEI_MASK (0x4U) +#define DMA4_TCD_CH_CSR_EEI_SHIFT (2U) +/*! EEI - Enable Error Interrupt + * 0b0..The error signal for corresponding channel does not generate an error interrupt + * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request + */ +#define DMA4_TCD_CH_CSR_EEI(x) (((uint32_t)(((uint32_t)(x)) << DMA4_TCD_CH_CSR_EEI_SHIFT)) & DMA4_TCD_CH_CSR_EEI_MASK) + +#define DMA4_TCD_CH_CSR_SWAP_MASK (0xF000U) +#define DMA4_TCD_CH_CSR_SWAP_SHIFT (12U) +/*! SWAP - Swap size + * 0b0000..disabled + * 0b0001..read with 8-bit swap + * 0b0010..read with 16-bit swap + * 0b0011..read with 32-bit swap + * 0b0100-0b1000..reserved + * 0b1001..write with 8-bit swap + * 0b1010..write with 16-bit swap + * 0b1011..write with 32-bit swap + * 0b1100-0b1111..reserved + */ +#define DMA4_TCD_CH_CSR_SWAP(x) (((uint32_t)(((uint32_t)(x)) << DMA4_TCD_CH_CSR_SWAP_SHIFT)) & DMA4_TCD_CH_CSR_SWAP_MASK) + +#define DMA4_TCD_CH_CSR_SIGNEXT_MASK (0x3F0000U) +#define DMA4_TCD_CH_CSR_SIGNEXT_SHIFT (16U) +/*! SIGNEXT - Sign Extension + * 0b000000..disabled + * 0b000001..A non-zero value specifying the sign extend bit position + */ +#define DMA4_TCD_CH_CSR_SIGNEXT(x) (((uint32_t)(((uint32_t)(x)) << DMA4_TCD_CH_CSR_SIGNEXT_SHIFT)) & DMA4_TCD_CH_CSR_SIGNEXT_MASK) + +#define DMA4_TCD_CH_CSR_DONE_MASK (0x40000000U) +#define DMA4_TCD_CH_CSR_DONE_SHIFT (30U) +/*! DONE - Channel Done */ +#define DMA4_TCD_CH_CSR_DONE(x) (((uint32_t)(((uint32_t)(x)) << DMA4_TCD_CH_CSR_DONE_SHIFT)) & DMA4_TCD_CH_CSR_DONE_MASK) + +#define DMA4_TCD_CH_CSR_ACTIVE_MASK (0x80000000U) +#define DMA4_TCD_CH_CSR_ACTIVE_SHIFT (31U) +/*! ACTIVE - Channel Active */ +#define DMA4_TCD_CH_CSR_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << DMA4_TCD_CH_CSR_ACTIVE_SHIFT)) & DMA4_TCD_CH_CSR_ACTIVE_MASK) +/*! @} */ + +/* The count of DMA4_TCD_CH_CSR */ +#define DMA4_TCD_CH_CSR_COUNT (64U) + +/*! @name CH_ES - Channel Error Status Register */ +/*! @{ */ + +#define DMA4_TCD_CH_ES_DBE_MASK (0x1U) +#define DMA4_TCD_CH_ES_DBE_SHIFT (0U) +/*! DBE - Destination Bus Error + * 0b0..No destination bus error + * 0b1..The last recorded error was a bus error on a destination write + */ +#define DMA4_TCD_CH_ES_DBE(x) (((uint32_t)(((uint32_t)(x)) << DMA4_TCD_CH_ES_DBE_SHIFT)) & DMA4_TCD_CH_ES_DBE_MASK) + +#define DMA4_TCD_CH_ES_SBE_MASK (0x2U) +#define DMA4_TCD_CH_ES_SBE_SHIFT (1U) +/*! SBE - Source Bus Error + * 0b0..No source bus error + * 0b1..The last recorded error was a bus error on a source read + */ +#define DMA4_TCD_CH_ES_SBE(x) (((uint32_t)(((uint32_t)(x)) << DMA4_TCD_CH_ES_SBE_SHIFT)) & DMA4_TCD_CH_ES_SBE_MASK) + +#define DMA4_TCD_CH_ES_SGE_MASK (0x4U) +#define DMA4_TCD_CH_ES_SGE_SHIFT (2U) +/*! SGE - Scatter/Gather Configuration Error + * 0b0..No scatter/gather configuration error + * 0b1..The last recorded error was a configuration error detected in the TCDn_DLASTSGA field. This field is + * checked at the beginning of a scatter/gather operation after major loop completion if TCDn_CSR[ESG] is + * enabled. TCDn_DLASTSGA is not on a 32 byte boundary. + */ +#define DMA4_TCD_CH_ES_SGE(x) (((uint32_t)(((uint32_t)(x)) << DMA4_TCD_CH_ES_SGE_SHIFT)) & DMA4_TCD_CH_ES_SGE_MASK) + +#define DMA4_TCD_CH_ES_NCE_MASK (0x8U) +#define DMA4_TCD_CH_ES_NCE_SHIFT (3U) +/*! NCE - NBYTES/CITER Configuration Error + * 0b0..No NBYTES/CITER configuration error + * 0b1..The last recorded error was a configuration error detected in the TCDn_NBYTES or TCDn_CITER fields. + * TCDn_NBYTES is not a multiple of TCDn_ATTR[SSIZE] and TCDn_ATTR[DSIZE], or TCDn_CITER[CITER] is equal to zero, + * or TCDn_CITER[ELINK] is not equal to TCDn_BITER[ELINK] + */ +#define DMA4_TCD_CH_ES_NCE(x) (((uint32_t)(((uint32_t)(x)) << DMA4_TCD_CH_ES_NCE_SHIFT)) & DMA4_TCD_CH_ES_NCE_MASK) + +#define DMA4_TCD_CH_ES_DOE_MASK (0x10U) +#define DMA4_TCD_CH_ES_DOE_SHIFT (4U) +/*! DOE - Destination Offset Error + * 0b0..No destination offset configuration error + * 0b1..The last recorded error was a configuration error detected in the TCDn_DOFF field. TCDn_DOFF is inconsistent with TCDn_ATTR[DSIZE]. + */ +#define DMA4_TCD_CH_ES_DOE(x) (((uint32_t)(((uint32_t)(x)) << DMA4_TCD_CH_ES_DOE_SHIFT)) & DMA4_TCD_CH_ES_DOE_MASK) + +#define DMA4_TCD_CH_ES_DAE_MASK (0x20U) +#define DMA4_TCD_CH_ES_DAE_SHIFT (5U) +/*! DAE - Destination Address Error + * 0b0..No destination address configuration error + * 0b1..The last recorded error was a configuration error detected in the TCDn_DADDR field. TCDn_DADDR is inconsistent with TCDn_ATTR[DSIZE]. + */ +#define DMA4_TCD_CH_ES_DAE(x) (((uint32_t)(((uint32_t)(x)) << DMA4_TCD_CH_ES_DAE_SHIFT)) & DMA4_TCD_CH_ES_DAE_MASK) + +#define DMA4_TCD_CH_ES_SOE_MASK (0x40U) +#define DMA4_TCD_CH_ES_SOE_SHIFT (6U) +/*! SOE - Source Offset Error + * 0b0..No source offset configuration error + * 0b1..The last recorded error was a configuration error detected in the TCDn_SOFF field. TCDn_SOFF is inconsistent with TCDn_ATTR[SSIZE]. + */ +#define DMA4_TCD_CH_ES_SOE(x) (((uint32_t)(((uint32_t)(x)) << DMA4_TCD_CH_ES_SOE_SHIFT)) & DMA4_TCD_CH_ES_SOE_MASK) + +#define DMA4_TCD_CH_ES_SAE_MASK (0x80U) +#define DMA4_TCD_CH_ES_SAE_SHIFT (7U) +/*! SAE - Source Address Error + * 0b0..No source address configuration error. + * 0b1..The last recorded error was a configuration error detected in the TCDn_SADDR field. TCDn_SADDR is inconsistent with TCDn_ATTR[SSIZE]. + */ +#define DMA4_TCD_CH_ES_SAE(x) (((uint32_t)(((uint32_t)(x)) << DMA4_TCD_CH_ES_SAE_SHIFT)) & DMA4_TCD_CH_ES_SAE_MASK) + +#define DMA4_TCD_CH_ES_ERR_MASK (0x80000000U) +#define DMA4_TCD_CH_ES_ERR_SHIFT (31U) +/*! ERR - Error In Channel + * 0b0..An error in this channel has not occurred + * 0b1..An error in this channel has occurred + */ +#define DMA4_TCD_CH_ES_ERR(x) (((uint32_t)(((uint32_t)(x)) << DMA4_TCD_CH_ES_ERR_SHIFT)) & DMA4_TCD_CH_ES_ERR_MASK) +/*! @} */ + +/* The count of DMA4_TCD_CH_ES */ +#define DMA4_TCD_CH_ES_COUNT (64U) + +/*! @name CH_INT - Channel Interrupt Status Register */ +/*! @{ */ + +#define DMA4_TCD_CH_INT_INT_MASK (0x1U) +#define DMA4_TCD_CH_INT_INT_SHIFT (0U) +/*! INT - Interrupt Request + * 0b0..The interrupt request for corresponding channel is cleared + * 0b1..The interrupt request for corresponding channel is active + */ +#define DMA4_TCD_CH_INT_INT(x) (((uint32_t)(((uint32_t)(x)) << DMA4_TCD_CH_INT_INT_SHIFT)) & DMA4_TCD_CH_INT_INT_MASK) +/*! @} */ + +/* The count of DMA4_TCD_CH_INT */ +#define DMA4_TCD_CH_INT_COUNT (64U) + +/*! @name CH_SBR - Channel System Bus Register */ +/*! @{ */ + +#define DMA4_TCD_CH_SBR_MID_MASK (0xFU) +#define DMA4_TCD_CH_SBR_MID_SHIFT (0U) +/*! MID - Master ID */ +#define DMA4_TCD_CH_SBR_MID(x) (((uint32_t)(((uint32_t)(x)) << DMA4_TCD_CH_SBR_MID_SHIFT)) & DMA4_TCD_CH_SBR_MID_MASK) + +#define DMA4_TCD_CH_SBR_INSTR_MASK (0x2000U) +#define DMA4_TCD_CH_SBR_INSTR_SHIFT (13U) +/*! INSTR - Instruction/Data Access + * 0b0..Data access for DMA transfers + * 0b1..Instruction access for DMA transfers + */ +#define DMA4_TCD_CH_SBR_INSTR(x) (((uint32_t)(((uint32_t)(x)) << DMA4_TCD_CH_SBR_INSTR_SHIFT)) & DMA4_TCD_CH_SBR_INSTR_MASK) + +#define DMA4_TCD_CH_SBR_SEC_MASK (0x4000U) +#define DMA4_TCD_CH_SBR_SEC_SHIFT (14U) +/*! SEC - Security Level + * 0b0..Nonsecure protection level for DMA transfers + * 0b1..Secure protection level for DMA transfers + */ +#define DMA4_TCD_CH_SBR_SEC(x) (((uint32_t)(((uint32_t)(x)) << DMA4_TCD_CH_SBR_SEC_SHIFT)) & DMA4_TCD_CH_SBR_SEC_MASK) + +#define DMA4_TCD_CH_SBR_PAL_MASK (0x8000U) +#define DMA4_TCD_CH_SBR_PAL_SHIFT (15U) +/*! PAL - Privileged Access Level + * 0b0..User protection level for DMA transfers + * 0b1..Privileged protection level for DMA transfers + */ +#define DMA4_TCD_CH_SBR_PAL(x) (((uint32_t)(((uint32_t)(x)) << DMA4_TCD_CH_SBR_PAL_SHIFT)) & DMA4_TCD_CH_SBR_PAL_MASK) + +#define DMA4_TCD_CH_SBR_EMI_MASK (0x10000U) +#define DMA4_TCD_CH_SBR_EMI_SHIFT (16U) +/*! EMI - Enable Master ID replication + * 0b0..Master ID replication is disabled + * 0b1..Master ID replication is enabled + */ +#define DMA4_TCD_CH_SBR_EMI(x) (((uint32_t)(((uint32_t)(x)) << DMA4_TCD_CH_SBR_EMI_SHIFT)) & DMA4_TCD_CH_SBR_EMI_MASK) + +#define DMA4_TCD_CH_SBR_ATTR_MASK (0x7E0000U) +#define DMA4_TCD_CH_SBR_ATTR_SHIFT (17U) +/*! ATTR - Attribute Output */ +#define DMA4_TCD_CH_SBR_ATTR(x) (((uint32_t)(((uint32_t)(x)) << DMA4_TCD_CH_SBR_ATTR_SHIFT)) & DMA4_TCD_CH_SBR_ATTR_MASK) +/*! @} */ + +/* The count of DMA4_TCD_CH_SBR */ +#define DMA4_TCD_CH_SBR_COUNT (64U) + +/*! @name CH_PRI - Channel Priority Register */ +/*! @{ */ + +#define DMA4_TCD_CH_PRI_APL_MASK (0x7U) +#define DMA4_TCD_CH_PRI_APL_SHIFT (0U) +/*! APL - Arbitration Priority Level */ +#define DMA4_TCD_CH_PRI_APL(x) (((uint32_t)(((uint32_t)(x)) << DMA4_TCD_CH_PRI_APL_SHIFT)) & DMA4_TCD_CH_PRI_APL_MASK) + +#define DMA4_TCD_CH_PRI_DPA_MASK (0x40000000U) +#define DMA4_TCD_CH_PRI_DPA_SHIFT (30U) +/*! DPA - Disable Preempt Ability. + * 0b0..The channel can suspend a lower priority channel. + * 0b1..The channel cannot suspend any other channel, regardless of channel priority. + */ +#define DMA4_TCD_CH_PRI_DPA(x) (((uint32_t)(((uint32_t)(x)) << DMA4_TCD_CH_PRI_DPA_SHIFT)) & DMA4_TCD_CH_PRI_DPA_MASK) + +#define DMA4_TCD_CH_PRI_ECP_MASK (0x80000000U) +#define DMA4_TCD_CH_PRI_ECP_SHIFT (31U) +/*! ECP - Enable Channel Preemption. + * 0b0..The channel cannot be suspended by a higher priority channel's service request. + * 0b1..The channel can be temporarily suspended by the service request of a higher priority channel. + */ +#define DMA4_TCD_CH_PRI_ECP(x) (((uint32_t)(((uint32_t)(x)) << DMA4_TCD_CH_PRI_ECP_SHIFT)) & DMA4_TCD_CH_PRI_ECP_MASK) +/*! @} */ + +/* The count of DMA4_TCD_CH_PRI */ +#define DMA4_TCD_CH_PRI_COUNT (64U) + +/*! @name CH_MUX - Channel Multiplexor Configuration */ +/*! @{ */ + +#define DMA4_TCD_CH_MUX_SRC_MASK (0x7FU) +#define DMA4_TCD_CH_MUX_SRC_SHIFT (0U) +/*! SRC - Service Request Source */ +#define DMA4_TCD_CH_MUX_SRC(x) (((uint32_t)(((uint32_t)(x)) << DMA4_TCD_CH_MUX_SRC_SHIFT)) & DMA4_TCD_CH_MUX_SRC_MASK) +/*! @} */ + +/* The count of DMA4_TCD_CH_MUX */ +#define DMA4_TCD_CH_MUX_COUNT (64U) + +/*! @name CH_MATTR - Memory Attributes Register */ +/*! @{ */ + +#define DMA4_TCD_CH_MATTR_RCACHE_MASK (0xFU) +#define DMA4_TCD_CH_MATTR_RCACHE_SHIFT (0U) +/*! RCACHE - Read Cache Attributes */ +#define DMA4_TCD_CH_MATTR_RCACHE(x) (((uint16_t)(((uint16_t)(x)) << DMA4_TCD_CH_MATTR_RCACHE_SHIFT)) & DMA4_TCD_CH_MATTR_RCACHE_MASK) + +#define DMA4_TCD_CH_MATTR_WCACHE_MASK (0xF0U) +#define DMA4_TCD_CH_MATTR_WCACHE_SHIFT (4U) +/*! WCACHE - Write Cache Attributes */ +#define DMA4_TCD_CH_MATTR_WCACHE(x) (((uint16_t)(((uint16_t)(x)) << DMA4_TCD_CH_MATTR_WCACHE_SHIFT)) & DMA4_TCD_CH_MATTR_WCACHE_MASK) +/*! @} */ + +/* The count of DMA4_TCD_CH_MATTR */ +#define DMA4_TCD_CH_MATTR_COUNT (64U) + +/*! @name SADDR - TCD Source Address Register */ +/*! @{ */ + +#define DMA4_TCD_SADDR_SADDR_MASK (0xFFFFFFFFU) +#define DMA4_TCD_SADDR_SADDR_SHIFT (0U) +/*! SADDR - Source Address */ +#define DMA4_TCD_SADDR_SADDR(x) (((uint32_t)(((uint32_t)(x)) << DMA4_TCD_SADDR_SADDR_SHIFT)) & DMA4_TCD_SADDR_SADDR_MASK) +/*! @} */ + +/* The count of DMA4_TCD_SADDR */ +#define DMA4_TCD_SADDR_COUNT (64U) + +/*! @name SOFF - TCD Signed Source Address Offset Register */ +/*! @{ */ + +#define DMA4_TCD_SOFF_SOFF_MASK (0xFFFFU) +#define DMA4_TCD_SOFF_SOFF_SHIFT (0U) +/*! SOFF - Source address signed offset */ +#define DMA4_TCD_SOFF_SOFF(x) (((uint16_t)(((uint16_t)(x)) << DMA4_TCD_SOFF_SOFF_SHIFT)) & DMA4_TCD_SOFF_SOFF_MASK) +/*! @} */ + +/* The count of DMA4_TCD_SOFF */ +#define DMA4_TCD_SOFF_COUNT (64U) + +/*! @name ATTR - TCD Transfer Attributes Register */ +/*! @{ */ + +#define DMA4_TCD_ATTR_DSIZE_MASK (0x7U) +#define DMA4_TCD_ATTR_DSIZE_SHIFT (0U) +/*! DSIZE - Destination data transfer size + * 0b000..8-bit + * 0b001..16-bit + * 0b010..32-bit + * 0b011..64-bit + * 0b100..16-byte + * 0b101..32-byte + * 0b110..64-byte + * 0b111..128-byte + */ +#define DMA4_TCD_ATTR_DSIZE(x) (((uint16_t)(((uint16_t)(x)) << DMA4_TCD_ATTR_DSIZE_SHIFT)) & DMA4_TCD_ATTR_DSIZE_MASK) + +#define DMA4_TCD_ATTR_DMOD_MASK (0xF8U) +#define DMA4_TCD_ATTR_DMOD_SHIFT (3U) +/*! DMOD - Destination address modulo */ +#define DMA4_TCD_ATTR_DMOD(x) (((uint16_t)(((uint16_t)(x)) << DMA4_TCD_ATTR_DMOD_SHIFT)) & DMA4_TCD_ATTR_DMOD_MASK) + +#define DMA4_TCD_ATTR_SSIZE_MASK (0x700U) +#define DMA4_TCD_ATTR_SSIZE_SHIFT (8U) +/*! SSIZE - Source data transfer size + * 0b000..8-bit + * 0b001..16-bit + * 0b010..32-bit + * 0b011..64-bit + * 0b100..16-byte + * 0b101..32-byte + * 0b110..64-byte + * 0b111..128-byte + */ +#define DMA4_TCD_ATTR_SSIZE(x) (((uint16_t)(((uint16_t)(x)) << DMA4_TCD_ATTR_SSIZE_SHIFT)) & DMA4_TCD_ATTR_SSIZE_MASK) + +#define DMA4_TCD_ATTR_SMOD_MASK (0xF800U) +#define DMA4_TCD_ATTR_SMOD_SHIFT (11U) +/*! SMOD - Source address modulo + * 0b00000..Source address modulo feature is disabled + * 0b00001..Source address modulo feature is enabled for any non-zero value [1-31] + */ +#define DMA4_TCD_ATTR_SMOD(x) (((uint16_t)(((uint16_t)(x)) << DMA4_TCD_ATTR_SMOD_SHIFT)) & DMA4_TCD_ATTR_SMOD_MASK) +/*! @} */ + +/* The count of DMA4_TCD_ATTR */ +#define DMA4_TCD_ATTR_COUNT (64U) + +/*! @name NBYTES_MLOFFNO - TCD Transfer Size without Minor Loop Offsets Register */ +/*! @{ */ + +#define DMA4_TCD_NBYTES_MLOFFNO_NBYTES_MASK (0x3FFFFFFFU) +#define DMA4_TCD_NBYTES_MLOFFNO_NBYTES_SHIFT (0U) +/*! NBYTES - Number of Bytes to transfer per service request */ +#define DMA4_TCD_NBYTES_MLOFFNO_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA4_TCD_NBYTES_MLOFFNO_NBYTES_SHIFT)) & DMA4_TCD_NBYTES_MLOFFNO_NBYTES_MASK) + +#define DMA4_TCD_NBYTES_MLOFFNO_DMLOE_MASK (0x40000000U) +#define DMA4_TCD_NBYTES_MLOFFNO_DMLOE_SHIFT (30U) +/*! DMLOE - Destination Minor Loop Offset Enable + * 0b0..The minor loop offset is not applied to the DADDR + * 0b1..The minor loop offset is applied to the DADDR + */ +#define DMA4_TCD_NBYTES_MLOFFNO_DMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA4_TCD_NBYTES_MLOFFNO_DMLOE_SHIFT)) & DMA4_TCD_NBYTES_MLOFFNO_DMLOE_MASK) + +#define DMA4_TCD_NBYTES_MLOFFNO_SMLOE_MASK (0x80000000U) +#define DMA4_TCD_NBYTES_MLOFFNO_SMLOE_SHIFT (31U) +/*! SMLOE - Source Minor Loop Offset Enable + * 0b0..The minor loop offset is not applied to the SADDR + * 0b1..The minor loop offset is applied to the SADDR + */ +#define DMA4_TCD_NBYTES_MLOFFNO_SMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA4_TCD_NBYTES_MLOFFNO_SMLOE_SHIFT)) & DMA4_TCD_NBYTES_MLOFFNO_SMLOE_MASK) +/*! @} */ + +/* The count of DMA4_TCD_NBYTES_MLOFFNO */ +#define DMA4_TCD_NBYTES_MLOFFNO_COUNT (64U) + +/*! @name NBYTES_MLOFFYES - TCD Transfer Size with Minor Loop Offsets Register */ +/*! @{ */ + +#define DMA4_TCD_NBYTES_MLOFFYES_NBYTES_MASK (0x3FFU) +#define DMA4_TCD_NBYTES_MLOFFYES_NBYTES_SHIFT (0U) +/*! NBYTES - Number of Bytes to transfer per service request */ +#define DMA4_TCD_NBYTES_MLOFFYES_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA4_TCD_NBYTES_MLOFFYES_NBYTES_SHIFT)) & DMA4_TCD_NBYTES_MLOFFYES_NBYTES_MASK) + +#define DMA4_TCD_NBYTES_MLOFFYES_MLOFF_MASK (0x3FFFFC00U) +#define DMA4_TCD_NBYTES_MLOFFYES_MLOFF_SHIFT (10U) +/*! MLOFF - Minor Loop Offset */ +#define DMA4_TCD_NBYTES_MLOFFYES_MLOFF(x) (((uint32_t)(((uint32_t)(x)) << DMA4_TCD_NBYTES_MLOFFYES_MLOFF_SHIFT)) & DMA4_TCD_NBYTES_MLOFFYES_MLOFF_MASK) + +#define DMA4_TCD_NBYTES_MLOFFYES_DMLOE_MASK (0x40000000U) +#define DMA4_TCD_NBYTES_MLOFFYES_DMLOE_SHIFT (30U) +/*! DMLOE - Destination Minor Loop Offset Enable + * 0b0..The minor loop offset is not applied to the DADDR + * 0b1..The minor loop offset is applied to the DADDR + */ +#define DMA4_TCD_NBYTES_MLOFFYES_DMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA4_TCD_NBYTES_MLOFFYES_DMLOE_SHIFT)) & DMA4_TCD_NBYTES_MLOFFYES_DMLOE_MASK) + +#define DMA4_TCD_NBYTES_MLOFFYES_SMLOE_MASK (0x80000000U) +#define DMA4_TCD_NBYTES_MLOFFYES_SMLOE_SHIFT (31U) +/*! SMLOE - Source Minor Loop Offset Enable + * 0b0..The minor loop offset is not applied to the SADDR + * 0b1..The minor loop offset is applied to the SADDR + */ +#define DMA4_TCD_NBYTES_MLOFFYES_SMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA4_TCD_NBYTES_MLOFFYES_SMLOE_SHIFT)) & DMA4_TCD_NBYTES_MLOFFYES_SMLOE_MASK) +/*! @} */ + +/* The count of DMA4_TCD_NBYTES_MLOFFYES */ +#define DMA4_TCD_NBYTES_MLOFFYES_COUNT (64U) + +/*! @name SLAST_SDA - TCD Last Source Address Adjustment / Store DADDR Address Register */ +/*! @{ */ + +#define DMA4_TCD_SLAST_SDA_SLAST_SDA_MASK (0xFFFFFFFFU) +#define DMA4_TCD_SLAST_SDA_SLAST_SDA_SHIFT (0U) +/*! SLAST_SDA - Last Source Address Adjustment / Store DADDR Address */ +#define DMA4_TCD_SLAST_SDA_SLAST_SDA(x) (((uint32_t)(((uint32_t)(x)) << DMA4_TCD_SLAST_SDA_SLAST_SDA_SHIFT)) & DMA4_TCD_SLAST_SDA_SLAST_SDA_MASK) +/*! @} */ + +/* The count of DMA4_TCD_SLAST_SDA */ +#define DMA4_TCD_SLAST_SDA_COUNT (64U) + +/*! @name DADDR - TCD Destination Address Register */ +/*! @{ */ + +#define DMA4_TCD_DADDR_DADDR_MASK (0xFFFFFFFFU) +#define DMA4_TCD_DADDR_DADDR_SHIFT (0U) +/*! DADDR - Destination Address */ +#define DMA4_TCD_DADDR_DADDR(x) (((uint32_t)(((uint32_t)(x)) << DMA4_TCD_DADDR_DADDR_SHIFT)) & DMA4_TCD_DADDR_DADDR_MASK) +/*! @} */ + +/* The count of DMA4_TCD_DADDR */ +#define DMA4_TCD_DADDR_COUNT (64U) + +/*! @name DOFF - TCD Signed Destination Address Offset Register */ +/*! @{ */ + +#define DMA4_TCD_DOFF_DOFF_MASK (0xFFFFU) +#define DMA4_TCD_DOFF_DOFF_SHIFT (0U) +/*! DOFF - Destination Address Signed Offset */ +#define DMA4_TCD_DOFF_DOFF(x) (((uint16_t)(((uint16_t)(x)) << DMA4_TCD_DOFF_DOFF_SHIFT)) & DMA4_TCD_DOFF_DOFF_MASK) +/*! @} */ + +/* The count of DMA4_TCD_DOFF */ +#define DMA4_TCD_DOFF_COUNT (64U) + +/*! @name CITER_ELINKNO - TCD Current Major Loop Count (Minor Loop Channel Linking Disabled) Register */ +/*! @{ */ + +#define DMA4_TCD_CITER_ELINKNO_CITER_MASK (0x7FFFU) +#define DMA4_TCD_CITER_ELINKNO_CITER_SHIFT (0U) +/*! CITER - Current Major Iteration Count */ +#define DMA4_TCD_CITER_ELINKNO_CITER(x) (((uint16_t)(((uint16_t)(x)) << DMA4_TCD_CITER_ELINKNO_CITER_SHIFT)) & DMA4_TCD_CITER_ELINKNO_CITER_MASK) + +#define DMA4_TCD_CITER_ELINKNO_ELINK_MASK (0x8000U) +#define DMA4_TCD_CITER_ELINKNO_ELINK_SHIFT (15U) +/*! ELINK - Enable channel-to-channel linking on minor-loop complete + * 0b0..The channel-to-channel linking is disabled + * 0b1..The channel-to-channel linking is enabled + */ +#define DMA4_TCD_CITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA4_TCD_CITER_ELINKNO_ELINK_SHIFT)) & DMA4_TCD_CITER_ELINKNO_ELINK_MASK) +/*! @} */ + +/* The count of DMA4_TCD_CITER_ELINKNO */ +#define DMA4_TCD_CITER_ELINKNO_COUNT (64U) + +/*! @name CITER_ELINKYES - TCD Current Major Loop Count (Minor Loop Channel Linking Enabled) Register */ +/*! @{ */ + +#define DMA4_TCD_CITER_ELINKYES_CITER_MASK (0x1FFU) +#define DMA4_TCD_CITER_ELINKYES_CITER_SHIFT (0U) +/*! CITER - Current Major Iteration Count */ +#define DMA4_TCD_CITER_ELINKYES_CITER(x) (((uint16_t)(((uint16_t)(x)) << DMA4_TCD_CITER_ELINKYES_CITER_SHIFT)) & DMA4_TCD_CITER_ELINKYES_CITER_MASK) + +#define DMA4_TCD_CITER_ELINKYES_LINKCH_MASK (0x7E00U) +#define DMA4_TCD_CITER_ELINKYES_LINKCH_SHIFT (9U) +/*! LINKCH - Minor Loop Link Channel Number */ +#define DMA4_TCD_CITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA4_TCD_CITER_ELINKYES_LINKCH_SHIFT)) & DMA4_TCD_CITER_ELINKYES_LINKCH_MASK) + +#define DMA4_TCD_CITER_ELINKYES_ELINK_MASK (0x8000U) +#define DMA4_TCD_CITER_ELINKYES_ELINK_SHIFT (15U) +/*! ELINK - Enable channel-to-channel linking on minor-loop complete + * 0b0..The channel-to-channel linking is disabled + * 0b1..The channel-to-channel linking is enabled + */ +#define DMA4_TCD_CITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA4_TCD_CITER_ELINKYES_ELINK_SHIFT)) & DMA4_TCD_CITER_ELINKYES_ELINK_MASK) +/*! @} */ + +/* The count of DMA4_TCD_CITER_ELINKYES */ +#define DMA4_TCD_CITER_ELINKYES_COUNT (64U) + +/*! @name DLAST_SGA - TCD Last Destination Address Adjustment / Scatter Gather Address Register */ +/*! @{ */ + +#define DMA4_TCD_DLAST_SGA_DLAST_SGA_MASK (0xFFFFFFFFU) +#define DMA4_TCD_DLAST_SGA_DLAST_SGA_SHIFT (0U) +/*! DLAST_SGA - Final Destination Address Adjustment / Scatter Gather Address */ +#define DMA4_TCD_DLAST_SGA_DLAST_SGA(x) (((uint32_t)(((uint32_t)(x)) << DMA4_TCD_DLAST_SGA_DLAST_SGA_SHIFT)) & DMA4_TCD_DLAST_SGA_DLAST_SGA_MASK) +/*! @} */ + +/* The count of DMA4_TCD_DLAST_SGA */ +#define DMA4_TCD_DLAST_SGA_COUNT (64U) + +/*! @name CSR - TCD Control and Status Register */ +/*! @{ */ + +#define DMA4_TCD_CSR_START_MASK (0x1U) +#define DMA4_TCD_CSR_START_SHIFT (0U) +/*! START - Channel Start + * 0b0..The channel is not explicitly started. + * 0b1..The channel is explicitly started via a software initiated service request. + */ +#define DMA4_TCD_CSR_START(x) (((uint16_t)(((uint16_t)(x)) << DMA4_TCD_CSR_START_SHIFT)) & DMA4_TCD_CSR_START_MASK) + +#define DMA4_TCD_CSR_INTMAJOR_MASK (0x2U) +#define DMA4_TCD_CSR_INTMAJOR_SHIFT (1U) +/*! INTMAJOR - Enable an interrupt when major iteration count completes. + * 0b0..The end-of-major loop interrupt is disabled. + * 0b1..The end-of-major loop interrupt is enabled. + */ +#define DMA4_TCD_CSR_INTMAJOR(x) (((uint16_t)(((uint16_t)(x)) << DMA4_TCD_CSR_INTMAJOR_SHIFT)) & DMA4_TCD_CSR_INTMAJOR_MASK) + +#define DMA4_TCD_CSR_INTHALF_MASK (0x4U) +#define DMA4_TCD_CSR_INTHALF_SHIFT (2U) +/*! INTHALF - Enable an interrupt when major counter is half complete. + * 0b0..The half-point interrupt is disabled. + * 0b1..The half-point interrupt is enabled. + */ +#define DMA4_TCD_CSR_INTHALF(x) (((uint16_t)(((uint16_t)(x)) << DMA4_TCD_CSR_INTHALF_SHIFT)) & DMA4_TCD_CSR_INTHALF_MASK) + +#define DMA4_TCD_CSR_DREQ_MASK (0x8U) +#define DMA4_TCD_CSR_DREQ_SHIFT (3U) +/*! DREQ - Disable request + * 0b0..No operation + * 0b1..Clear the ERQ bit upon major loop completion, thus disabling hardware service requests. + */ +#define DMA4_TCD_CSR_DREQ(x) (((uint16_t)(((uint16_t)(x)) << DMA4_TCD_CSR_DREQ_SHIFT)) & DMA4_TCD_CSR_DREQ_MASK) + +#define DMA4_TCD_CSR_ESG_MASK (0x10U) +#define DMA4_TCD_CSR_ESG_SHIFT (4U) +/*! ESG - Enable Scatter/Gather processing + * 0b0..The current channel's TCD is normal format. + * 0b1..The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer + * to the next TCD to be loaded into this channel after the major loop completes its execution. + */ +#define DMA4_TCD_CSR_ESG(x) (((uint16_t)(((uint16_t)(x)) << DMA4_TCD_CSR_ESG_SHIFT)) & DMA4_TCD_CSR_ESG_MASK) + +#define DMA4_TCD_CSR_MAJORELINK_MASK (0x20U) +#define DMA4_TCD_CSR_MAJORELINK_SHIFT (5U) +/*! MAJORELINK - Enable channel-to-channel linking on major loop complete + * 0b0..The channel-to-channel linking is disabled. + * 0b1..The channel-to-channel linking is enabled. + */ +#define DMA4_TCD_CSR_MAJORELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA4_TCD_CSR_MAJORELINK_SHIFT)) & DMA4_TCD_CSR_MAJORELINK_MASK) + +#define DMA4_TCD_CSR_EEOP_MASK (0x40U) +#define DMA4_TCD_CSR_EEOP_SHIFT (6U) +/*! EEOP - Enable end-of-packet processing + * 0b0..The end-of-packet operation is disabled. + * 0b1..The end-of-packet hardware input signal is enabled. + */ +#define DMA4_TCD_CSR_EEOP(x) (((uint16_t)(((uint16_t)(x)) << DMA4_TCD_CSR_EEOP_SHIFT)) & DMA4_TCD_CSR_EEOP_MASK) + +#define DMA4_TCD_CSR_ESDA_MASK (0x80U) +#define DMA4_TCD_CSR_ESDA_SHIFT (7U) +/*! ESDA - Enable store destination address + * 0b0..The store destination address to system memory operation is disabled. + * 0b1..The store destination address to system memory operation is enabled. + */ +#define DMA4_TCD_CSR_ESDA(x) (((uint16_t)(((uint16_t)(x)) << DMA4_TCD_CSR_ESDA_SHIFT)) & DMA4_TCD_CSR_ESDA_MASK) + +#define DMA4_TCD_CSR_MAJORLINKCH_MASK (0x3F00U) +#define DMA4_TCD_CSR_MAJORLINKCH_SHIFT (8U) +/*! MAJORLINKCH - Major loop link channel number */ +#define DMA4_TCD_CSR_MAJORLINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA4_TCD_CSR_MAJORLINKCH_SHIFT)) & DMA4_TCD_CSR_MAJORLINKCH_MASK) + +#define DMA4_TCD_CSR_TMC_MASK (0xC000U) +#define DMA4_TCD_CSR_TMC_SHIFT (14U) +/*! TMC - Transfer Mode Control + * 0b00..Read/Write + * 0b01..Read Only + * 0b10..Write Only + * 0b11..Reserved + */ +#define DMA4_TCD_CSR_TMC(x) (((uint16_t)(((uint16_t)(x)) << DMA4_TCD_CSR_TMC_SHIFT)) & DMA4_TCD_CSR_TMC_MASK) +/*! @} */ + +/* The count of DMA4_TCD_CSR */ +#define DMA4_TCD_CSR_COUNT (64U) + +/*! @name BITER_ELINKNO - TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled) Register */ +/*! @{ */ + +#define DMA4_TCD_BITER_ELINKNO_BITER_MASK (0x7FFFU) +#define DMA4_TCD_BITER_ELINKNO_BITER_SHIFT (0U) +/*! BITER - Starting Major Iteration Count */ +#define DMA4_TCD_BITER_ELINKNO_BITER(x) (((uint16_t)(((uint16_t)(x)) << DMA4_TCD_BITER_ELINKNO_BITER_SHIFT)) & DMA4_TCD_BITER_ELINKNO_BITER_MASK) + +#define DMA4_TCD_BITER_ELINKNO_ELINK_MASK (0x8000U) +#define DMA4_TCD_BITER_ELINKNO_ELINK_SHIFT (15U) +/*! ELINK - Enables channel-to-channel linking on minor loop complete + * 0b0..The channel-to-channel linking is disabled + * 0b1..The channel-to-channel linking is enabled + */ +#define DMA4_TCD_BITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA4_TCD_BITER_ELINKNO_ELINK_SHIFT)) & DMA4_TCD_BITER_ELINKNO_ELINK_MASK) +/*! @} */ + +/* The count of DMA4_TCD_BITER_ELINKNO */ +#define DMA4_TCD_BITER_ELINKNO_COUNT (64U) + +/*! @name BITER_ELINKYES - TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled) Register */ +/*! @{ */ + +#define DMA4_TCD_BITER_ELINKYES_BITER_MASK (0x1FFU) +#define DMA4_TCD_BITER_ELINKYES_BITER_SHIFT (0U) +/*! BITER - Starting major iteration count */ +#define DMA4_TCD_BITER_ELINKYES_BITER(x) (((uint16_t)(((uint16_t)(x)) << DMA4_TCD_BITER_ELINKYES_BITER_SHIFT)) & DMA4_TCD_BITER_ELINKYES_BITER_MASK) + +#define DMA4_TCD_BITER_ELINKYES_LINKCH_MASK (0x7E00U) +#define DMA4_TCD_BITER_ELINKYES_LINKCH_SHIFT (9U) +/*! LINKCH - Link Channel Number */ +#define DMA4_TCD_BITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA4_TCD_BITER_ELINKYES_LINKCH_SHIFT)) & DMA4_TCD_BITER_ELINKYES_LINKCH_MASK) + +#define DMA4_TCD_BITER_ELINKYES_ELINK_MASK (0x8000U) +#define DMA4_TCD_BITER_ELINKYES_ELINK_SHIFT (15U) +/*! ELINK - Enables channel-to-channel linking on minor loop complete + * 0b0..The channel-to-channel linking is disabled + * 0b1..The channel-to-channel linking is enabled + */ +#define DMA4_TCD_BITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA4_TCD_BITER_ELINKYES_ELINK_SHIFT)) & DMA4_TCD_BITER_ELINKYES_ELINK_MASK) +/*! @} */ + +/* The count of DMA4_TCD_BITER_ELINKYES */ +#define DMA4_TCD_BITER_ELINKYES_COUNT (64U) + + +/*! + * @} + */ /* end of group DMA4_TCD_Register_Masks */ + + +/* DMA4_TCD - Peripheral instance base addresses */ +/** Peripheral EDMA4_2__TCD base address */ +#define EDMA4_2__TCD_BASE (0u) +/** Peripheral EDMA4_2__TCD base pointer */ +#define EDMA4_2__TCD ((DMA4_TCD_Type *)EDMA4_2__TCD_BASE) +/** Array initializer of DMA4_TCD peripheral base addresses */ +#define DMA4_TCD_BASE_ADDRS { EDMA4_2__TCD_BASE } +/** Array initializer of DMA4_TCD peripheral base pointers */ +#define DMA4_TCD_BASE_PTRS { EDMA4_2__TCD } + +/*! + * @} + */ /* end of group DMA4_TCD_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- ENET Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ENET_Peripheral_Access_Layer ENET Peripheral Access Layer + * @{ + */ + +/** ENET - Register Layout Typedef */ +typedef struct { + uint8_t RESERVED_0[4]; + __IO uint32_t EIR; /**< Interrupt Event Register, offset: 0x4 */ + __IO uint32_t EIMR; /**< Interrupt Mask Register, offset: 0x8 */ + uint8_t RESERVED_1[4]; + __IO uint32_t RDAR; /**< Receive Descriptor Active Register - Ring 0, offset: 0x10 */ + __IO uint32_t TDAR; /**< Transmit Descriptor Active Register - Ring 0, offset: 0x14 */ + uint8_t RESERVED_2[12]; + __IO uint32_t ECR; /**< Ethernet Control Register, offset: 0x24 */ + uint8_t RESERVED_3[24]; + __IO uint32_t MMFR; /**< MII Management Frame Register, offset: 0x40 */ + __IO uint32_t MSCR; /**< MII Speed Control Register, offset: 0x44 */ + uint8_t RESERVED_4[28]; + __IO uint32_t MIBC; /**< MIB Control Register, offset: 0x64 */ + uint8_t RESERVED_5[28]; + __IO uint32_t RCR; /**< Receive Control Register, offset: 0x84 */ + uint8_t RESERVED_6[60]; + __IO uint32_t TCR; /**< Transmit Control Register, offset: 0xC4 */ + uint8_t RESERVED_7[28]; + __IO uint32_t PALR; /**< Physical Address Lower Register, offset: 0xE4 */ + __IO uint32_t PAUR; /**< Physical Address Upper Register, offset: 0xE8 */ + __IO uint32_t OPD; /**< Opcode/Pause Duration Register, offset: 0xEC */ + __IO uint32_t TXIC[3]; /**< Transmit Interrupt Coalescing Register, array offset: 0xF0, array step: 0x4 */ + uint8_t RESERVED_8[4]; + __IO uint32_t RXIC[3]; /**< Receive Interrupt Coalescing Register, array offset: 0x100, array step: 0x4 */ + uint8_t RESERVED_9[12]; + __IO uint32_t IAUR; /**< Descriptor Individual Upper Address Register, offset: 0x118 */ + __IO uint32_t IALR; /**< Descriptor Individual Lower Address Register, offset: 0x11C */ + __IO uint32_t GAUR; /**< Descriptor Group Upper Address Register, offset: 0x120 */ + __IO uint32_t GALR; /**< Descriptor Group Lower Address Register, offset: 0x124 */ + uint8_t RESERVED_10[28]; + __IO uint32_t TFWR; /**< Transmit FIFO Watermark Register, offset: 0x144 */ + uint8_t RESERVED_11[24]; + __IO uint32_t RDSR1; /**< Receive Descriptor Ring 1 Start Register, offset: 0x160 */ + __IO uint32_t TDSR1; /**< Transmit Buffer Descriptor Ring 1 Start Register, offset: 0x164 */ + __IO uint32_t MRBR1; /**< Maximum Receive Buffer Size Register - Ring 1, offset: 0x168 */ + __IO uint32_t RDSR2; /**< Receive Descriptor Ring 2 Start Register, offset: 0x16C */ + __IO uint32_t TDSR2; /**< Transmit Buffer Descriptor Ring 2 Start Register, offset: 0x170 */ + __IO uint32_t MRBR2; /**< Maximum Receive Buffer Size Register - Ring 2, offset: 0x174 */ + uint8_t RESERVED_12[8]; + __IO uint32_t RDSR; /**< Receive Descriptor Ring 0 Start Register, offset: 0x180 */ + __IO uint32_t TDSR; /**< Transmit Buffer Descriptor Ring 0 Start Register, offset: 0x184 */ + __IO uint32_t MRBR; /**< Maximum Receive Buffer Size Register - Ring 0, offset: 0x188 */ + uint8_t RESERVED_13[4]; + __IO uint32_t RSFL; /**< Receive FIFO Section Full Threshold, offset: 0x190 */ + __IO uint32_t RSEM; /**< Receive FIFO Section Empty Threshold, offset: 0x194 */ + __IO uint32_t RAEM; /**< Receive FIFO Almost Empty Threshold, offset: 0x198 */ + __IO uint32_t RAFL; /**< Receive FIFO Almost Full Threshold, offset: 0x19C */ + __IO uint32_t TSEM; /**< Transmit FIFO Section Empty Threshold, offset: 0x1A0 */ + __IO uint32_t TAEM; /**< Transmit FIFO Almost Empty Threshold, offset: 0x1A4 */ + __IO uint32_t TAFL; /**< Transmit FIFO Almost Full Threshold, offset: 0x1A8 */ + __IO uint32_t TIPG; /**< Transmit Inter-Packet Gap, offset: 0x1AC */ + __IO uint32_t FTRL; /**< Frame Truncation Length, offset: 0x1B0 */ + uint8_t RESERVED_14[12]; + __IO uint32_t TACC; /**< Transmit Accelerator Function Configuration, offset: 0x1C0 */ + __IO uint32_t RACC; /**< Receive Accelerator Function Configuration, offset: 0x1C4 */ + __IO uint32_t RCMR[2]; /**< Receive Classification Match Register for Class n, array offset: 0x1C8, array step: 0x4 */ + uint8_t RESERVED_15[8]; + __IO uint32_t DMACFG[2]; /**< DMA Class Based Configuration, array offset: 0x1D8, array step: 0x4 */ + __IO uint32_t RDAR1; /**< Receive Descriptor Active Register - Ring 1, offset: 0x1E0 */ + __IO uint32_t TDAR1; /**< Transmit Descriptor Active Register - Ring 1, offset: 0x1E4 */ + __IO uint32_t RDAR2; /**< Receive Descriptor Active Register - Ring 2, offset: 0x1E8 */ + __IO uint32_t TDAR2; /**< Transmit Descriptor Active Register - Ring 2, offset: 0x1EC */ + __IO uint32_t QOS; /**< QOS Scheme, offset: 0x1F0 */ + uint8_t RESERVED_16[16]; + __I uint32_t RMON_T_PACKETS; /**< Tx Packet Count Statistic Register, offset: 0x204 */ + __I uint32_t RMON_T_BC_PKT; /**< Tx Broadcast Packets Statistic Register, offset: 0x208 */ + __I uint32_t RMON_T_MC_PKT; /**< Tx Multicast Packets Statistic Register, offset: 0x20C */ + __I uint32_t RMON_T_CRC_ALIGN; /**< Tx Packets with CRC/Align Error Statistic Register, offset: 0x210 */ + __I uint32_t RMON_T_UNDERSIZE; /**< Tx Packets Less Than Bytes and Good CRC Statistic Register, offset: 0x214 */ + __I uint32_t RMON_T_OVERSIZE; /**< Tx Packets GT MAX_FL bytes and Good CRC Statistic Register, offset: 0x218 */ + __I uint32_t RMON_T_FRAG; /**< Tx Packets Less Than 64 Bytes and Bad CRC Statistic Register, offset: 0x21C */ + __I uint32_t RMON_T_JAB; /**< Tx Packets Greater Than MAX_FL bytes and Bad CRC Statistic Register, offset: 0x220 */ + __I uint32_t RMON_T_COL; /**< Tx Collision Count Statistic Register, offset: 0x224 */ + __I uint32_t RMON_T_P64; /**< Tx 64-Byte Packets Statistic Register, offset: 0x228 */ + __I uint32_t RMON_T_P65TO127; /**< Tx 65- to 127-byte Packets Statistic Register, offset: 0x22C */ + __I uint32_t RMON_T_P128TO255; /**< Tx 128- to 255-byte Packets Statistic Register, offset: 0x230 */ + __I uint32_t RMON_T_P256TO511; /**< Tx 256- to 511-byte Packets Statistic Register, offset: 0x234 */ + __I uint32_t RMON_T_P512TO1023; /**< Tx 512- to 1023-byte Packets Statistic Register, offset: 0x238 */ + __I uint32_t RMON_T_P1024TO2047; /**< Tx 1024- to 2047-byte Packets Statistic Register, offset: 0x23C */ + __I uint32_t RMON_T_P_GTE2048; /**< Tx Packets Greater Than 2048 Bytes Statistic Register, offset: 0x240 */ + __I uint32_t RMON_T_OCTETS; /**< Tx Octets Statistic Register, offset: 0x244 */ + uint8_t RESERVED_17[4]; + __I uint32_t IEEE_T_FRAME_OK; /**< Frames Transmitted OK Statistic Register, offset: 0x24C */ + __I uint32_t IEEE_T_1COL; /**< Frames Transmitted with Single Collision Statistic Register, offset: 0x250 */ + __I uint32_t IEEE_T_MCOL; /**< Frames Transmitted with Multiple Collisions Statistic Register, offset: 0x254 */ + __I uint32_t IEEE_T_DEF; /**< Frames Transmitted after Deferral Delay Statistic Register, offset: 0x258 */ + __I uint32_t IEEE_T_LCOL; /**< Frames Transmitted with Late Collision Statistic Register, offset: 0x25C */ + __I uint32_t IEEE_T_EXCOL; /**< Frames Transmitted with Excessive Collisions Statistic Register, offset: 0x260 */ + __I uint32_t IEEE_T_MACERR; /**< Frames Transmitted with Tx FIFO Underrun Statistic Register, offset: 0x264 */ + __I uint32_t IEEE_T_CSERR; /**< Frames Transmitted with Carrier Sense Error Statistic Register, offset: 0x268 */ + __I uint32_t IEEE_T_SQE; /**< Reserved Statistic Register, offset: 0x26C */ + __I uint32_t IEEE_T_FDXFC; /**< Flow Control Pause Frames Transmitted Statistic Register, offset: 0x270 */ + __I uint32_t IEEE_T_OCTETS_OK; /**< Octet Count for Frames Transmitted w/o Error Statistic Register, offset: 0x274 */ + uint8_t RESERVED_18[12]; + __I uint32_t RMON_R_PACKETS; /**< Rx Packet Count Statistic Register, offset: 0x284 */ + __I uint32_t RMON_R_BC_PKT; /**< Rx Broadcast Packets Statistic Register, offset: 0x288 */ + __I uint32_t RMON_R_MC_PKT; /**< Rx Multicast Packets Statistic Register, offset: 0x28C */ + __I uint32_t RMON_R_CRC_ALIGN; /**< Rx Packets with CRC/Align Error Statistic Register, offset: 0x290 */ + __I uint32_t RMON_R_UNDERSIZE; /**< Rx Packets with Less Than 64 Bytes and Good CRC Statistic Register, offset: 0x294 */ + __I uint32_t RMON_R_OVERSIZE; /**< Rx Packets Greater Than MAX_FL and Good CRC Statistic Register, offset: 0x298 */ + __I uint32_t RMON_R_FRAG; /**< Rx Packets Less Than 64 Bytes and Bad CRC Statistic Register, offset: 0x29C */ + __I uint32_t RMON_R_JAB; /**< Rx Packets Greater Than MAX_FL Bytes and Bad CRC Statistic Register, offset: 0x2A0 */ + uint8_t RESERVED_19[4]; + __I uint32_t RMON_R_P64; /**< Rx 64-Byte Packets Statistic Register, offset: 0x2A8 */ + __I uint32_t RMON_R_P65TO127; /**< Rx 65- to 127-Byte Packets Statistic Register, offset: 0x2AC */ + __I uint32_t RMON_R_P128TO255; /**< Rx 128- to 255-Byte Packets Statistic Register, offset: 0x2B0 */ + __I uint32_t RMON_R_P256TO511; /**< Rx 256- to 511-Byte Packets Statistic Register, offset: 0x2B4 */ + __I uint32_t RMON_R_P512TO1023; /**< Rx 512- to 1023-Byte Packets Statistic Register, offset: 0x2B8 */ + __I uint32_t RMON_R_P1024TO2047; /**< Rx 1024- to 2047-Byte Packets Statistic Register, offset: 0x2BC */ + __I uint32_t RMON_R_P_GTE2048; /**< Rx Packets Greater than 2048 Bytes Statistic Register, offset: 0x2C0 */ + __I uint32_t RMON_R_OCTETS; /**< Rx Octets Statistic Register, offset: 0x2C4 */ + __I uint32_t IEEE_R_DROP; /**< Frames not Counted Correctly Statistic Register, offset: 0x2C8 */ + __I uint32_t IEEE_R_FRAME_OK; /**< Frames Received OK Statistic Register, offset: 0x2CC */ + __I uint32_t IEEE_R_CRC; /**< Frames Received with CRC Error Statistic Register, offset: 0x2D0 */ + __I uint32_t IEEE_R_ALIGN; /**< Frames Received with Alignment Error Statistic Register, offset: 0x2D4 */ + __I uint32_t IEEE_R_MACERR; /**< Receive FIFO Overflow Count Statistic Register, offset: 0x2D8 */ + __I uint32_t IEEE_R_FDXFC; /**< Flow Control Pause Frames Received Statistic Register, offset: 0x2DC */ + __I uint32_t IEEE_R_OCTETS_OK; /**< Octet Count for Frames Received without Error Statistic Register, offset: 0x2E0 */ + uint8_t RESERVED_20[284]; + __IO uint32_t ATCR; /**< Adjustable Timer Control Register, offset: 0x400 */ + __IO uint32_t ATVR; /**< Timer Value Register, offset: 0x404 */ + __IO uint32_t ATOFF; /**< Timer Offset Register, offset: 0x408 */ + __IO uint32_t ATPER; /**< Timer Period Register, offset: 0x40C */ + __IO uint32_t ATCOR; /**< Timer Correction Register, offset: 0x410 */ + __IO uint32_t ATINC; /**< Time-Stamping Clock Period Register, offset: 0x414 */ + __I uint32_t ATSTMP; /**< Timestamp of Last Transmitted Frame, offset: 0x418 */ + uint8_t RESERVED_21[488]; + __IO uint32_t TGSR; /**< Timer Global Status Register, offset: 0x604 */ + struct { /* offset: 0x608, array step: 0x8 */ + __IO uint32_t TCSR; /**< Timer Control Status Register, array offset: 0x608, array step: 0x8 */ + __IO uint32_t TCCR; /**< Timer Compare Capture Register, array offset: 0x60C, array step: 0x8 */ + } CHANNEL[4]; +} ENET_Type; + +/* ---------------------------------------------------------------------------- + -- ENET Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ENET_Register_Masks ENET Register Masks + * @{ + */ + +/*! @name EIR - Interrupt Event Register */ +/*! @{ */ + +#define ENET_EIR_RXB1_MASK (0x1U) +#define ENET_EIR_RXB1_SHIFT (0U) +/*! RXB1 - Receive buffer interrupt, class 1 */ +#define ENET_EIR_RXB1(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXB1_SHIFT)) & ENET_EIR_RXB1_MASK) + +#define ENET_EIR_RXF1_MASK (0x2U) +#define ENET_EIR_RXF1_SHIFT (1U) +/*! RXF1 - Receive frame interrupt, class 1 */ +#define ENET_EIR_RXF1(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXF1_SHIFT)) & ENET_EIR_RXF1_MASK) + +#define ENET_EIR_TXB1_MASK (0x4U) +#define ENET_EIR_TXB1_SHIFT (2U) +/*! TXB1 - Transmit buffer interrupt, class 1 */ +#define ENET_EIR_TXB1(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TXB1_SHIFT)) & ENET_EIR_TXB1_MASK) + +#define ENET_EIR_TXF1_MASK (0x8U) +#define ENET_EIR_TXF1_SHIFT (3U) +/*! TXF1 - Transmit frame interrupt, class 1 */ +#define ENET_EIR_TXF1(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TXF1_SHIFT)) & ENET_EIR_TXF1_MASK) + +#define ENET_EIR_RXB2_MASK (0x10U) +#define ENET_EIR_RXB2_SHIFT (4U) +/*! RXB2 - Receive buffer interrupt, class 2 */ +#define ENET_EIR_RXB2(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXB2_SHIFT)) & ENET_EIR_RXB2_MASK) + +#define ENET_EIR_RXF2_MASK (0x20U) +#define ENET_EIR_RXF2_SHIFT (5U) +/*! RXF2 - Receive frame interrupt, class 2 */ +#define ENET_EIR_RXF2(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXF2_SHIFT)) & ENET_EIR_RXF2_MASK) + +#define ENET_EIR_TXB2_MASK (0x40U) +#define ENET_EIR_TXB2_SHIFT (6U) +/*! TXB2 - Transmit buffer interrupt, class 2 */ +#define ENET_EIR_TXB2(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TXB2_SHIFT)) & ENET_EIR_TXB2_MASK) + +#define ENET_EIR_TXF2_MASK (0x80U) +#define ENET_EIR_TXF2_SHIFT (7U) +/*! TXF2 - Transmit frame interrupt, class 2 */ +#define ENET_EIR_TXF2(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TXF2_SHIFT)) & ENET_EIR_TXF2_MASK) + +#define ENET_EIR_RXFLUSH_0_MASK (0x1000U) +#define ENET_EIR_RXFLUSH_0_SHIFT (12U) +#define ENET_EIR_RXFLUSH_0(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXFLUSH_0_SHIFT)) & ENET_EIR_RXFLUSH_0_MASK) + +#define ENET_EIR_RXFLUSH_1_MASK (0x2000U) +#define ENET_EIR_RXFLUSH_1_SHIFT (13U) +#define ENET_EIR_RXFLUSH_1(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXFLUSH_1_SHIFT)) & ENET_EIR_RXFLUSH_1_MASK) + +#define ENET_EIR_RXFLUSH_2_MASK (0x4000U) +#define ENET_EIR_RXFLUSH_2_SHIFT (14U) +#define ENET_EIR_RXFLUSH_2(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXFLUSH_2_SHIFT)) & ENET_EIR_RXFLUSH_2_MASK) + +#define ENET_EIR_TS_TIMER_MASK (0x8000U) +#define ENET_EIR_TS_TIMER_SHIFT (15U) +/*! TS_TIMER - Timestamp Timer */ +#define ENET_EIR_TS_TIMER(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TS_TIMER_SHIFT)) & ENET_EIR_TS_TIMER_MASK) + +#define ENET_EIR_TS_AVAIL_MASK (0x10000U) +#define ENET_EIR_TS_AVAIL_SHIFT (16U) +/*! TS_AVAIL - Transmit Timestamp Available */ +#define ENET_EIR_TS_AVAIL(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TS_AVAIL_SHIFT)) & ENET_EIR_TS_AVAIL_MASK) + +#define ENET_EIR_WAKEUP_MASK (0x20000U) +#define ENET_EIR_WAKEUP_SHIFT (17U) +/*! WAKEUP - Node Wakeup Request Indication */ +#define ENET_EIR_WAKEUP(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_WAKEUP_SHIFT)) & ENET_EIR_WAKEUP_MASK) + +#define ENET_EIR_PLR_MASK (0x40000U) +#define ENET_EIR_PLR_SHIFT (18U) +/*! PLR - Payload Receive Error */ +#define ENET_EIR_PLR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_PLR_SHIFT)) & ENET_EIR_PLR_MASK) + +#define ENET_EIR_UN_MASK (0x80000U) +#define ENET_EIR_UN_SHIFT (19U) +/*! UN - Transmit FIFO Underrun */ +#define ENET_EIR_UN(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_UN_SHIFT)) & ENET_EIR_UN_MASK) + +#define ENET_EIR_RL_MASK (0x100000U) +#define ENET_EIR_RL_SHIFT (20U) +/*! RL - Collision Retry Limit */ +#define ENET_EIR_RL(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RL_SHIFT)) & ENET_EIR_RL_MASK) + +#define ENET_EIR_LC_MASK (0x200000U) +#define ENET_EIR_LC_SHIFT (21U) +/*! LC - Late Collision */ +#define ENET_EIR_LC(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_LC_SHIFT)) & ENET_EIR_LC_MASK) + +#define ENET_EIR_EBERR_MASK (0x400000U) +#define ENET_EIR_EBERR_SHIFT (22U) +/*! EBERR - Ethernet Bus Error */ +#define ENET_EIR_EBERR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_EBERR_SHIFT)) & ENET_EIR_EBERR_MASK) + +#define ENET_EIR_MII_MASK (0x800000U) +#define ENET_EIR_MII_SHIFT (23U) +/*! MII - MII Interrupt. */ +#define ENET_EIR_MII(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_MII_SHIFT)) & ENET_EIR_MII_MASK) + +#define ENET_EIR_RXB_MASK (0x1000000U) +#define ENET_EIR_RXB_SHIFT (24U) +/*! RXB - Receive Buffer Interrupt */ +#define ENET_EIR_RXB(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXB_SHIFT)) & ENET_EIR_RXB_MASK) + +#define ENET_EIR_RXF_MASK (0x2000000U) +#define ENET_EIR_RXF_SHIFT (25U) +/*! RXF - Receive Frame Interrupt */ +#define ENET_EIR_RXF(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXF_SHIFT)) & ENET_EIR_RXF_MASK) + +#define ENET_EIR_TXB_MASK (0x4000000U) +#define ENET_EIR_TXB_SHIFT (26U) +/*! TXB - Transmit Buffer Interrupt */ +#define ENET_EIR_TXB(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TXB_SHIFT)) & ENET_EIR_TXB_MASK) + +#define ENET_EIR_TXF_MASK (0x8000000U) +#define ENET_EIR_TXF_SHIFT (27U) +/*! TXF - Transmit Frame Interrupt */ +#define ENET_EIR_TXF(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TXF_SHIFT)) & ENET_EIR_TXF_MASK) + +#define ENET_EIR_GRA_MASK (0x10000000U) +#define ENET_EIR_GRA_SHIFT (28U) +/*! GRA - Graceful Stop Complete */ +#define ENET_EIR_GRA(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_GRA_SHIFT)) & ENET_EIR_GRA_MASK) + +#define ENET_EIR_BABT_MASK (0x20000000U) +#define ENET_EIR_BABT_SHIFT (29U) +/*! BABT - Babbling Transmit Error */ +#define ENET_EIR_BABT(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_BABT_SHIFT)) & ENET_EIR_BABT_MASK) + +#define ENET_EIR_BABR_MASK (0x40000000U) +#define ENET_EIR_BABR_SHIFT (30U) +/*! BABR - Babbling Receive Error */ +#define ENET_EIR_BABR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_BABR_SHIFT)) & ENET_EIR_BABR_MASK) +/*! @} */ + +/*! @name EIMR - Interrupt Mask Register */ +/*! @{ */ + +#define ENET_EIMR_RXB1_MASK (0x1U) +#define ENET_EIMR_RXB1_SHIFT (0U) +/*! RXB1 - Receive buffer interrupt, class 1 + * 0b0..The corresponding interrupt source is masked. + * 0b1..The corresponding interrupt source is not masked. + */ +#define ENET_EIMR_RXB1(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXB1_SHIFT)) & ENET_EIMR_RXB1_MASK) + +#define ENET_EIMR_RXF1_MASK (0x2U) +#define ENET_EIMR_RXF1_SHIFT (1U) +/*! RXF1 - Receive frame interrupt, class 1 + * 0b0..The corresponding interrupt source is masked. + * 0b1..The corresponding interrupt source is not masked. + */ +#define ENET_EIMR_RXF1(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXF1_SHIFT)) & ENET_EIMR_RXF1_MASK) + +#define ENET_EIMR_TXB1_MASK (0x4U) +#define ENET_EIMR_TXB1_SHIFT (2U) +/*! TXB1 - Transmit buffer interrupt, class 1 + * 0b0..The corresponding interrupt source is masked. + * 0b1..The corresponding interrupt source is not masked. + */ +#define ENET_EIMR_TXB1(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXB1_SHIFT)) & ENET_EIMR_TXB1_MASK) + +#define ENET_EIMR_TXF1_MASK (0x8U) +#define ENET_EIMR_TXF1_SHIFT (3U) +/*! TXF1 - Transmit frame interrupt, class 1 + * 0b0..The corresponding interrupt source is masked. + * 0b1..The corresponding interrupt source is not masked. + */ +#define ENET_EIMR_TXF1(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXF1_SHIFT)) & ENET_EIMR_TXF1_MASK) + +#define ENET_EIMR_RXB2_MASK (0x10U) +#define ENET_EIMR_RXB2_SHIFT (4U) +/*! RXB2 - Receive buffer interrupt, class 2 + * 0b0..The corresponding interrupt source is masked. + * 0b1..The corresponding interrupt source is not masked. + */ +#define ENET_EIMR_RXB2(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXB2_SHIFT)) & ENET_EIMR_RXB2_MASK) + +#define ENET_EIMR_RXF2_MASK (0x20U) +#define ENET_EIMR_RXF2_SHIFT (5U) +/*! RXF2 - Receive frame interrupt, class 2 + * 0b0..The corresponding interrupt source is masked. + * 0b1..The corresponding interrupt source is not masked. + */ +#define ENET_EIMR_RXF2(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXF2_SHIFT)) & ENET_EIMR_RXF2_MASK) + +#define ENET_EIMR_TXB2_MASK (0x40U) +#define ENET_EIMR_TXB2_SHIFT (6U) +/*! TXB2 - Transmit buffer interrupt, class 2 + * 0b0..The corresponding interrupt source is masked. + * 0b1..The corresponding interrupt source is not masked. + */ +#define ENET_EIMR_TXB2(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXB2_SHIFT)) & ENET_EIMR_TXB2_MASK) + +#define ENET_EIMR_TXF2_MASK (0x80U) +#define ENET_EIMR_TXF2_SHIFT (7U) +/*! TXF2 - Transmit frame interrupt, class 2 + * 0b0..The corresponding interrupt source is masked. + * 0b1..The corresponding interrupt source is not masked. + */ +#define ENET_EIMR_TXF2(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXF2_SHIFT)) & ENET_EIMR_TXF2_MASK) + +#define ENET_EIMR_RXFLUSH_0_MASK (0x1000U) +#define ENET_EIMR_RXFLUSH_0_SHIFT (12U) +/*! RXFLUSH_0 + * 0b0..The corresponding interrupt source is masked. + * 0b1..The corresponding interrupt source is not masked. + */ +#define ENET_EIMR_RXFLUSH_0(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXFLUSH_0_SHIFT)) & ENET_EIMR_RXFLUSH_0_MASK) + +#define ENET_EIMR_RXFLUSH_1_MASK (0x2000U) +#define ENET_EIMR_RXFLUSH_1_SHIFT (13U) +/*! RXFLUSH_1 + * 0b0..The corresponding interrupt source is masked. + * 0b1..The corresponding interrupt source is not masked. + */ +#define ENET_EIMR_RXFLUSH_1(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXFLUSH_1_SHIFT)) & ENET_EIMR_RXFLUSH_1_MASK) + +#define ENET_EIMR_RXFLUSH_2_MASK (0x4000U) +#define ENET_EIMR_RXFLUSH_2_SHIFT (14U) +/*! RXFLUSH_2 + * 0b0..The corresponding interrupt source is masked. + * 0b1..The corresponding interrupt source is not masked. + */ +#define ENET_EIMR_RXFLUSH_2(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXFLUSH_2_SHIFT)) & ENET_EIMR_RXFLUSH_2_MASK) + +#define ENET_EIMR_TS_TIMER_MASK (0x8000U) +#define ENET_EIMR_TS_TIMER_SHIFT (15U) +/*! TS_TIMER - TS_TIMER Interrupt Mask + * 0b0..The corresponding interrupt source is masked. + * 0b1..The corresponding interrupt source is not masked. + */ +#define ENET_EIMR_TS_TIMER(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TS_TIMER_SHIFT)) & ENET_EIMR_TS_TIMER_MASK) + +#define ENET_EIMR_TS_AVAIL_MASK (0x10000U) +#define ENET_EIMR_TS_AVAIL_SHIFT (16U) +/*! TS_AVAIL - TS_AVAIL Interrupt Mask + * 0b0..The corresponding interrupt source is masked. + * 0b1..The corresponding interrupt source is not masked. + */ +#define ENET_EIMR_TS_AVAIL(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TS_AVAIL_SHIFT)) & ENET_EIMR_TS_AVAIL_MASK) + +#define ENET_EIMR_WAKEUP_MASK (0x20000U) +#define ENET_EIMR_WAKEUP_SHIFT (17U) +/*! WAKEUP - WAKEUP Interrupt Mask + * 0b0..The corresponding interrupt source is masked. + * 0b1..The corresponding interrupt source is not masked. + */ +#define ENET_EIMR_WAKEUP(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_WAKEUP_SHIFT)) & ENET_EIMR_WAKEUP_MASK) + +#define ENET_EIMR_PLR_MASK (0x40000U) +#define ENET_EIMR_PLR_SHIFT (18U) +/*! PLR - PLR Interrupt Mask + * 0b0..The corresponding interrupt source is masked. + * 0b1..The corresponding interrupt source is not masked. + */ +#define ENET_EIMR_PLR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_PLR_SHIFT)) & ENET_EIMR_PLR_MASK) + +#define ENET_EIMR_UN_MASK (0x80000U) +#define ENET_EIMR_UN_SHIFT (19U) +/*! UN - UN Interrupt Mask + * 0b0..The corresponding interrupt source is masked. + * 0b1..The corresponding interrupt source is not masked. + */ +#define ENET_EIMR_UN(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_UN_SHIFT)) & ENET_EIMR_UN_MASK) + +#define ENET_EIMR_RL_MASK (0x100000U) +#define ENET_EIMR_RL_SHIFT (20U) +/*! RL - RL Interrupt Mask + * 0b0..The corresponding interrupt source is masked. + * 0b1..The corresponding interrupt source is not masked. + */ +#define ENET_EIMR_RL(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RL_SHIFT)) & ENET_EIMR_RL_MASK) + +#define ENET_EIMR_LC_MASK (0x200000U) +#define ENET_EIMR_LC_SHIFT (21U) +/*! LC - LC Interrupt Mask + * 0b0..The corresponding interrupt source is masked. + * 0b1..The corresponding interrupt source is not masked. + */ +#define ENET_EIMR_LC(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_LC_SHIFT)) & ENET_EIMR_LC_MASK) + +#define ENET_EIMR_EBERR_MASK (0x400000U) +#define ENET_EIMR_EBERR_SHIFT (22U) +/*! EBERR - EBERR Interrupt Mask + * 0b0..The corresponding interrupt source is masked. + * 0b1..The corresponding interrupt source is not masked. + */ +#define ENET_EIMR_EBERR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_EBERR_SHIFT)) & ENET_EIMR_EBERR_MASK) + +#define ENET_EIMR_MII_MASK (0x800000U) +#define ENET_EIMR_MII_SHIFT (23U) +/*! MII - MII Interrupt Mask + * 0b0..The corresponding interrupt source is masked. + * 0b1..The corresponding interrupt source is not masked. + */ +#define ENET_EIMR_MII(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_MII_SHIFT)) & ENET_EIMR_MII_MASK) + +#define ENET_EIMR_RXB_MASK (0x1000000U) +#define ENET_EIMR_RXB_SHIFT (24U) +/*! RXB - RXB Interrupt Mask + * 0b0..The corresponding interrupt source is masked. + * 0b1..The corresponding interrupt source is not masked. + */ +#define ENET_EIMR_RXB(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXB_SHIFT)) & ENET_EIMR_RXB_MASK) + +#define ENET_EIMR_RXF_MASK (0x2000000U) +#define ENET_EIMR_RXF_SHIFT (25U) +/*! RXF - RXF Interrupt Mask + * 0b0..The corresponding interrupt source is masked. + * 0b1..The corresponding interrupt source is not masked. + */ +#define ENET_EIMR_RXF(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXF_SHIFT)) & ENET_EIMR_RXF_MASK) + +#define ENET_EIMR_TXB_MASK (0x4000000U) +#define ENET_EIMR_TXB_SHIFT (26U) +/*! TXB - TXB Interrupt Mask + * 0b0..The corresponding interrupt source is masked. + * 0b1..The corresponding interrupt source is not masked. + */ +#define ENET_EIMR_TXB(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXB_SHIFT)) & ENET_EIMR_TXB_MASK) + +#define ENET_EIMR_TXF_MASK (0x8000000U) +#define ENET_EIMR_TXF_SHIFT (27U) +/*! TXF - TXF Interrupt Mask + * 0b0..The corresponding interrupt source is masked. + * 0b1..The corresponding interrupt source is not masked. + */ +#define ENET_EIMR_TXF(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXF_SHIFT)) & ENET_EIMR_TXF_MASK) + +#define ENET_EIMR_GRA_MASK (0x10000000U) +#define ENET_EIMR_GRA_SHIFT (28U) +/*! GRA - GRA Interrupt Mask + * 0b0..The corresponding interrupt source is masked. + * 0b1..The corresponding interrupt source is not masked. + */ +#define ENET_EIMR_GRA(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_GRA_SHIFT)) & ENET_EIMR_GRA_MASK) + +#define ENET_EIMR_BABT_MASK (0x20000000U) +#define ENET_EIMR_BABT_SHIFT (29U) +/*! BABT - BABT Interrupt Mask + * 0b0..The corresponding interrupt source is masked. + * 0b1..The corresponding interrupt source is not masked. + */ +#define ENET_EIMR_BABT(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_BABT_SHIFT)) & ENET_EIMR_BABT_MASK) + +#define ENET_EIMR_BABR_MASK (0x40000000U) +#define ENET_EIMR_BABR_SHIFT (30U) +/*! BABR - BABR Interrupt Mask + * 0b0..The corresponding interrupt source is masked. + * 0b1..The corresponding interrupt source is not masked. + */ +#define ENET_EIMR_BABR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_BABR_SHIFT)) & ENET_EIMR_BABR_MASK) +/*! @} */ + +/*! @name RDAR - Receive Descriptor Active Register - Ring 0 */ +/*! @{ */ + +#define ENET_RDAR_RDAR_MASK (0x1000000U) +#define ENET_RDAR_RDAR_SHIFT (24U) +/*! RDAR - Receive Descriptor Active */ +#define ENET_RDAR_RDAR(x) (((uint32_t)(((uint32_t)(x)) << ENET_RDAR_RDAR_SHIFT)) & ENET_RDAR_RDAR_MASK) +/*! @} */ + +/*! @name TDAR - Transmit Descriptor Active Register - Ring 0 */ +/*! @{ */ + +#define ENET_TDAR_TDAR_MASK (0x1000000U) +#define ENET_TDAR_TDAR_SHIFT (24U) +/*! TDAR - Transmit Descriptor Active */ +#define ENET_TDAR_TDAR(x) (((uint32_t)(((uint32_t)(x)) << ENET_TDAR_TDAR_SHIFT)) & ENET_TDAR_TDAR_MASK) +/*! @} */ + +/*! @name ECR - Ethernet Control Register */ +/*! @{ */ + +#define ENET_ECR_RESET_MASK (0x1U) +#define ENET_ECR_RESET_SHIFT (0U) +/*! RESET - Ethernet MAC Reset */ +#define ENET_ECR_RESET(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_RESET_SHIFT)) & ENET_ECR_RESET_MASK) + +#define ENET_ECR_ETHEREN_MASK (0x2U) +#define ENET_ECR_ETHEREN_SHIFT (1U) +/*! ETHEREN - Ethernet Enable + * 0b0..Reception immediately stops and transmission stops after a bad CRC is appended to any currently transmitted frame. + * 0b1..MAC is enabled, and reception and transmission are possible. + */ +#define ENET_ECR_ETHEREN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_ETHEREN_SHIFT)) & ENET_ECR_ETHEREN_MASK) + +#define ENET_ECR_MAGICEN_MASK (0x4U) +#define ENET_ECR_MAGICEN_SHIFT (2U) +/*! MAGICEN - Magic Packet Detection Enable + * 0b0..Magic detection logic disabled. + * 0b1..The MAC core detects magic packets and asserts EIR[WAKEUP] when a frame is detected. + */ +#define ENET_ECR_MAGICEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_MAGICEN_SHIFT)) & ENET_ECR_MAGICEN_MASK) + +#define ENET_ECR_SLEEP_MASK (0x8U) +#define ENET_ECR_SLEEP_SHIFT (3U) +/*! SLEEP - Sleep Mode Enable + * 0b0..Normal operating mode. + * 0b1..Sleep mode. + */ +#define ENET_ECR_SLEEP(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_SLEEP_SHIFT)) & ENET_ECR_SLEEP_MASK) + +#define ENET_ECR_EN1588_MASK (0x10U) +#define ENET_ECR_EN1588_SHIFT (4U) +/*! EN1588 - EN1588 Enable + * 0b0..Legacy FEC buffer descriptors and functions enabled. + * 0b1..Enhanced frame time-stamping functions enabled. Has no effect within the MAC besides controlling the DMA control bit ena_1588. + */ +#define ENET_ECR_EN1588(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_EN1588_SHIFT)) & ENET_ECR_EN1588_MASK) + +#define ENET_ECR_SPEED_MASK (0x20U) +#define ENET_ECR_SPEED_SHIFT (5U) +/*! SPEED + * 0b0..10/100-Mbit/s mode + * 0b1..1000-Mbit/s mode + */ +#define ENET_ECR_SPEED(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_SPEED_SHIFT)) & ENET_ECR_SPEED_MASK) + +#define ENET_ECR_DBGEN_MASK (0x40U) +#define ENET_ECR_DBGEN_SHIFT (6U) +/*! DBGEN - Debug Enable + * 0b0..MAC continues operation in debug mode. + * 0b1..MAC enters hardware freeze mode when the processor is in debug mode. + */ +#define ENET_ECR_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_DBGEN_SHIFT)) & ENET_ECR_DBGEN_MASK) + +#define ENET_ECR_DBSWP_MASK (0x100U) +#define ENET_ECR_DBSWP_SHIFT (8U) +/*! DBSWP - Descriptor Byte Swapping Enable + * 0b0..The buffer descriptor bytes are not swapped to support big-endian devices. + * 0b1..The buffer descriptor bytes are swapped to support little-endian devices. + */ +#define ENET_ECR_DBSWP(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_DBSWP_SHIFT)) & ENET_ECR_DBSWP_MASK) + +#define ENET_ECR_SVLANEN_MASK (0x200U) +#define ENET_ECR_SVLANEN_SHIFT (9U) +/*! SVLANEN - S-VLAN enable + * 0b0..Only the EtherType 0x8100 will be considered for VLAN detection. + * 0b1..The EtherType 0x88a8 will be considered in addition to 0x8100 (C-VLAN) to identify a VLAN frame in + * receive. When a VLAN frame is identified, the two bytes following the VLAN type are extracted and used by the + * classification match comparators, RCMRn. + */ +#define ENET_ECR_SVLANEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_SVLANEN_SHIFT)) & ENET_ECR_SVLANEN_MASK) + +#define ENET_ECR_VLANUSE2ND_MASK (0x400U) +#define ENET_ECR_VLANUSE2ND_SHIFT (10U) +/*! VLANUSE2ND - VLAN use second tag + * 0b0..Always extract data from the first VLAN tag if it exists. + * 0b1..When a double-tagged frame is detected, the data of the second tag is extracted for further processing. A + * double-tagged frame is defined as: The first tag can be a C-VLAN or a S-VLAN (if SVLAN_ENA = 1) The + * second tag must be a C-VLAN + */ +#define ENET_ECR_VLANUSE2ND(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_VLANUSE2ND_SHIFT)) & ENET_ECR_VLANUSE2ND_MASK) + +#define ENET_ECR_SVLANDBL_MASK (0x800U) +#define ENET_ECR_SVLANDBL_SHIFT (11U) +/*! SVLANDBL - S-VLAN double tag + * 0b0..Disable S-VLAN double tag + * 0b1..Enable S-VLAN double tag + */ +#define ENET_ECR_SVLANDBL(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_SVLANDBL_SHIFT)) & ENET_ECR_SVLANDBL_MASK) + +#define ENET_ECR_TXC_DLY_MASK (0x10000U) +#define ENET_ECR_TXC_DLY_SHIFT (16U) +/*! TXC_DLY - Transmit clock delay + * 0b0..RGMII_TXC is not delayed. + * 0b1..Generate delayed version of RGMII_TXC. + */ +#define ENET_ECR_TXC_DLY(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_TXC_DLY_SHIFT)) & ENET_ECR_TXC_DLY_MASK) + +#define ENET_ECR_RXC_DLY_MASK (0x20000U) +#define ENET_ECR_RXC_DLY_SHIFT (17U) +/*! RXC_DLY - Receive clock delay + * 0b0..Use non-delayed version of RGMII_RXC. + * 0b1..Use delayed version of RGMII_RXC. + */ +#define ENET_ECR_RXC_DLY(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_RXC_DLY_SHIFT)) & ENET_ECR_RXC_DLY_MASK) +/*! @} */ + +/*! @name MMFR - MII Management Frame Register */ +/*! @{ */ + +#define ENET_MMFR_DATA_MASK (0xFFFFU) +#define ENET_MMFR_DATA_SHIFT (0U) +/*! DATA - Management Frame Data */ +#define ENET_MMFR_DATA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_DATA_SHIFT)) & ENET_MMFR_DATA_MASK) + +#define ENET_MMFR_TA_MASK (0x30000U) +#define ENET_MMFR_TA_SHIFT (16U) +/*! TA - Turn Around */ +#define ENET_MMFR_TA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_TA_SHIFT)) & ENET_MMFR_TA_MASK) + +#define ENET_MMFR_RA_MASK (0x7C0000U) +#define ENET_MMFR_RA_SHIFT (18U) +/*! RA - Register Address */ +#define ENET_MMFR_RA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_RA_SHIFT)) & ENET_MMFR_RA_MASK) + +#define ENET_MMFR_PA_MASK (0xF800000U) +#define ENET_MMFR_PA_SHIFT (23U) +/*! PA - PHY Address */ +#define ENET_MMFR_PA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_PA_SHIFT)) & ENET_MMFR_PA_MASK) + +#define ENET_MMFR_OP_MASK (0x30000000U) +#define ENET_MMFR_OP_SHIFT (28U) +/*! OP - Operation Code */ +#define ENET_MMFR_OP(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_OP_SHIFT)) & ENET_MMFR_OP_MASK) + +#define ENET_MMFR_ST_MASK (0xC0000000U) +#define ENET_MMFR_ST_SHIFT (30U) +/*! ST - Start Of Frame Delimiter */ +#define ENET_MMFR_ST(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_ST_SHIFT)) & ENET_MMFR_ST_MASK) +/*! @} */ + +/*! @name MSCR - MII Speed Control Register */ +/*! @{ */ + +#define ENET_MSCR_MII_SPEED_MASK (0x7EU) +#define ENET_MSCR_MII_SPEED_SHIFT (1U) +/*! MII_SPEED - MII Speed */ +#define ENET_MSCR_MII_SPEED(x) (((uint32_t)(((uint32_t)(x)) << ENET_MSCR_MII_SPEED_SHIFT)) & ENET_MSCR_MII_SPEED_MASK) + +#define ENET_MSCR_DIS_PRE_MASK (0x80U) +#define ENET_MSCR_DIS_PRE_SHIFT (7U) +/*! DIS_PRE - Disable Preamble + * 0b0..Preamble enabled. + * 0b1..Preamble (32 ones) is not prepended to the MII management frame. + */ +#define ENET_MSCR_DIS_PRE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MSCR_DIS_PRE_SHIFT)) & ENET_MSCR_DIS_PRE_MASK) + +#define ENET_MSCR_HOLDTIME_MASK (0x700U) +#define ENET_MSCR_HOLDTIME_SHIFT (8U) +/*! HOLDTIME - Hold time On MDIO Output + * 0b000..1 internal module clock cycle + * 0b001..2 internal module clock cycles + * 0b010..3 internal module clock cycles + * 0b111..8 internal module clock cycles + */ +#define ENET_MSCR_HOLDTIME(x) (((uint32_t)(((uint32_t)(x)) << ENET_MSCR_HOLDTIME_SHIFT)) & ENET_MSCR_HOLDTIME_MASK) +/*! @} */ + +/*! @name MIBC - MIB Control Register */ +/*! @{ */ + +#define ENET_MIBC_MIB_CLEAR_MASK (0x20000000U) +#define ENET_MIBC_MIB_CLEAR_SHIFT (29U) +/*! MIB_CLEAR - MIB Clear + * 0b0..See note above. + * 0b1..All statistics counters are reset to 0. + */ +#define ENET_MIBC_MIB_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_CLEAR_SHIFT)) & ENET_MIBC_MIB_CLEAR_MASK) + +#define ENET_MIBC_MIB_IDLE_MASK (0x40000000U) +#define ENET_MIBC_MIB_IDLE_SHIFT (30U) +/*! MIB_IDLE - MIB Idle + * 0b0..The MIB block is updating MIB counters. + * 0b1..The MIB block is not currently updating any MIB counters. + */ +#define ENET_MIBC_MIB_IDLE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_IDLE_SHIFT)) & ENET_MIBC_MIB_IDLE_MASK) + +#define ENET_MIBC_MIB_DIS_MASK (0x80000000U) +#define ENET_MIBC_MIB_DIS_SHIFT (31U) +/*! MIB_DIS - Disable MIB Logic + * 0b0..MIB logic is enabled. + * 0b1..MIB logic is disabled. The MIB logic halts and does not update any MIB counters. + */ +#define ENET_MIBC_MIB_DIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_DIS_SHIFT)) & ENET_MIBC_MIB_DIS_MASK) +/*! @} */ + +/*! @name RCR - Receive Control Register */ +/*! @{ */ + +#define ENET_RCR_LOOP_MASK (0x1U) +#define ENET_RCR_LOOP_SHIFT (0U) +/*! LOOP - Internal Loopback + * 0b0..Loopback disabled. + * 0b1..Transmitted frames are looped back internal to the device and transmit MII output signals are not asserted. DRT must be cleared. + */ +#define ENET_RCR_LOOP(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_LOOP_SHIFT)) & ENET_RCR_LOOP_MASK) + +#define ENET_RCR_DRT_MASK (0x2U) +#define ENET_RCR_DRT_SHIFT (1U) +/*! DRT - Disable Receive On Transmit + * 0b0..Receive path operates independently of transmit (i.e., full-duplex mode). Can also be used to monitor transmit activity in half-duplex mode. + * 0b1..Disable reception of frames while transmitting. (Normally used for half-duplex mode.) + */ +#define ENET_RCR_DRT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_DRT_SHIFT)) & ENET_RCR_DRT_MASK) + +#define ENET_RCR_MII_MODE_MASK (0x4U) +#define ENET_RCR_MII_MODE_SHIFT (2U) +/*! MII_MODE - Media Independent Interface Mode + * 0b0..Reserved. + * 0b1..MII or RMII mode, as indicated by the RMII_MODE field. + */ +#define ENET_RCR_MII_MODE(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_MII_MODE_SHIFT)) & ENET_RCR_MII_MODE_MASK) + +#define ENET_RCR_PROM_MASK (0x8U) +#define ENET_RCR_PROM_SHIFT (3U) +/*! PROM - Promiscuous Mode + * 0b0..Disabled. + * 0b1..Enabled. + */ +#define ENET_RCR_PROM(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_PROM_SHIFT)) & ENET_RCR_PROM_MASK) + +#define ENET_RCR_BC_REJ_MASK (0x10U) +#define ENET_RCR_BC_REJ_SHIFT (4U) +/*! BC_REJ - Broadcast Frame Reject + * 0b0..Will not reject frames as described above + * 0b1..Will reject frames as described above + */ +#define ENET_RCR_BC_REJ(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_BC_REJ_SHIFT)) & ENET_RCR_BC_REJ_MASK) + +#define ENET_RCR_FCE_MASK (0x20U) +#define ENET_RCR_FCE_SHIFT (5U) +/*! FCE - Flow Control Enable + * 0b0..Disable flow control + * 0b1..Enable flow control + */ +#define ENET_RCR_FCE(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_FCE_SHIFT)) & ENET_RCR_FCE_MASK) + +#define ENET_RCR_RGMII_EN_MASK (0x40U) +#define ENET_RCR_RGMII_EN_SHIFT (6U) +/*! RGMII_EN - RGMII Mode Enable + * 0b0..MAC configured for non-RGMII operation + * 0b1..MAC configured for RGMII operation. If ECR[SPEED] is set, the MAC is in RGMII 1000-Mbit/s mode. If + * ECR[SPEED] is cleared, the MAC is in RGMII 10/100-Mbit/s mode. + */ +#define ENET_RCR_RGMII_EN(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_RGMII_EN_SHIFT)) & ENET_RCR_RGMII_EN_MASK) + +#define ENET_RCR_RMII_MODE_MASK (0x100U) +#define ENET_RCR_RMII_MODE_SHIFT (8U) +/*! RMII_MODE - RMII Mode Enable + * 0b0..MAC configured for MII mode. + * 0b1..MAC configured for RMII operation. + */ +#define ENET_RCR_RMII_MODE(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_RMII_MODE_SHIFT)) & ENET_RCR_RMII_MODE_MASK) + +#define ENET_RCR_RMII_10T_MASK (0x200U) +#define ENET_RCR_RMII_10T_SHIFT (9U) +/*! RMII_10T + * 0b0..100-Mbit/s or 1-Gbit/s operation. + * 0b1..10-Mbit/s operation. + */ +#define ENET_RCR_RMII_10T(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_RMII_10T_SHIFT)) & ENET_RCR_RMII_10T_MASK) + +#define ENET_RCR_PADEN_MASK (0x1000U) +#define ENET_RCR_PADEN_SHIFT (12U) +/*! PADEN - Enable Frame Padding Remove On Receive + * 0b0..No padding is removed on receive by the MAC. + * 0b1..Padding is removed from received frames. + */ +#define ENET_RCR_PADEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_PADEN_SHIFT)) & ENET_RCR_PADEN_MASK) + +#define ENET_RCR_PAUFWD_MASK (0x2000U) +#define ENET_RCR_PAUFWD_SHIFT (13U) +/*! PAUFWD - Terminate/Forward Pause Frames + * 0b0..Pause frames are terminated and discarded in the MAC. + * 0b1..Pause frames are forwarded to the user application. + */ +#define ENET_RCR_PAUFWD(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_PAUFWD_SHIFT)) & ENET_RCR_PAUFWD_MASK) + +#define ENET_RCR_CRCFWD_MASK (0x4000U) +#define ENET_RCR_CRCFWD_SHIFT (14U) +/*! CRCFWD - Terminate/Forward Received CRC + * 0b0..The CRC field of received frames is transmitted to the user application. + * 0b1..The CRC field is stripped from the frame. + */ +#define ENET_RCR_CRCFWD(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_CRCFWD_SHIFT)) & ENET_RCR_CRCFWD_MASK) + +#define ENET_RCR_CFEN_MASK (0x8000U) +#define ENET_RCR_CFEN_SHIFT (15U) +/*! CFEN - MAC Control Frame Enable + * 0b0..MAC control frames with any opcode other than 0x0001 (pause frame) are accepted and forwarded to the client interface. + * 0b1..MAC control frames with any opcode other than 0x0001 (pause frame) are silently discarded. + */ +#define ENET_RCR_CFEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_CFEN_SHIFT)) & ENET_RCR_CFEN_MASK) + +#define ENET_RCR_MAX_FL_MASK (0x3FFF0000U) +#define ENET_RCR_MAX_FL_SHIFT (16U) +/*! MAX_FL - Maximum Frame Length */ +#define ENET_RCR_MAX_FL(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_MAX_FL_SHIFT)) & ENET_RCR_MAX_FL_MASK) + +#define ENET_RCR_NLC_MASK (0x40000000U) +#define ENET_RCR_NLC_SHIFT (30U) +/*! NLC - Payload Length Check Disable + * 0b0..The payload length check is disabled. + * 0b1..The core checks the frame's payload length with the frame length/type field. Errors are indicated in the EIR[PLR] field. + */ +#define ENET_RCR_NLC(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_NLC_SHIFT)) & ENET_RCR_NLC_MASK) + +#define ENET_RCR_GRS_MASK (0x80000000U) +#define ENET_RCR_GRS_SHIFT (31U) +/*! GRS - Graceful Receive Stopped + * 0b0..Receive not stopped + * 0b1..Receive stopped + */ +#define ENET_RCR_GRS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_GRS_SHIFT)) & ENET_RCR_GRS_MASK) +/*! @} */ + +/*! @name TCR - Transmit Control Register */ +/*! @{ */ + +#define ENET_TCR_GTS_MASK (0x1U) +#define ENET_TCR_GTS_SHIFT (0U) +/*! GTS - Graceful Transmit Stop + * 0b0..Disable graceful transmit stop + * 0b1..Enable graceful transmit stop + */ +#define ENET_TCR_GTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_GTS_SHIFT)) & ENET_TCR_GTS_MASK) + +#define ENET_TCR_FDEN_MASK (0x4U) +#define ENET_TCR_FDEN_SHIFT (2U) +/*! FDEN - Full-Duplex Enable + * 0b0..Disable full-duplex + * 0b1..Enable full-duplex + */ +#define ENET_TCR_FDEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_FDEN_SHIFT)) & ENET_TCR_FDEN_MASK) + +#define ENET_TCR_TFC_PAUSE_MASK (0x8U) +#define ENET_TCR_TFC_PAUSE_SHIFT (3U) +/*! TFC_PAUSE - Transmit Frame Control Pause + * 0b0..No PAUSE frame transmitted. + * 0b1..The MAC stops transmission of data frames after the current transmission is complete. + */ +#define ENET_TCR_TFC_PAUSE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_TFC_PAUSE_SHIFT)) & ENET_TCR_TFC_PAUSE_MASK) + +#define ENET_TCR_RFC_PAUSE_MASK (0x10U) +#define ENET_TCR_RFC_PAUSE_SHIFT (4U) +/*! RFC_PAUSE - Receive Frame Control Pause */ +#define ENET_TCR_RFC_PAUSE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_RFC_PAUSE_SHIFT)) & ENET_TCR_RFC_PAUSE_MASK) + +#define ENET_TCR_ADDSEL_MASK (0xE0U) +#define ENET_TCR_ADDSEL_SHIFT (5U) +/*! ADDSEL - Source MAC Address Select On Transmit + * 0b000..Node MAC address programmed on PADDR1/2 registers. + * 0b100..Reserved. + * 0b101..Reserved. + * 0b110..Reserved. + */ +#define ENET_TCR_ADDSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_ADDSEL_SHIFT)) & ENET_TCR_ADDSEL_MASK) + +#define ENET_TCR_ADDINS_MASK (0x100U) +#define ENET_TCR_ADDINS_SHIFT (8U) +/*! ADDINS - Set MAC Address On Transmit + * 0b0..The source MAC address is not modified by the MAC. + * 0b1..The MAC overwrites the source MAC address with the programmed MAC address according to ADDSEL. + */ +#define ENET_TCR_ADDINS(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_ADDINS_SHIFT)) & ENET_TCR_ADDINS_MASK) + +#define ENET_TCR_CRCFWD_MASK (0x200U) +#define ENET_TCR_CRCFWD_SHIFT (9U) +/*! CRCFWD - Forward Frame From Application With CRC + * 0b0..TxBD[TC] controls whether the frame has a CRC from the application. + * 0b1..The transmitter does not append any CRC to transmitted frames, as it is expecting a frame with CRC from the application. + */ +#define ENET_TCR_CRCFWD(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_CRCFWD_SHIFT)) & ENET_TCR_CRCFWD_MASK) +/*! @} */ + +/*! @name PALR - Physical Address Lower Register */ +/*! @{ */ + +#define ENET_PALR_PADDR1_MASK (0xFFFFFFFFU) +#define ENET_PALR_PADDR1_SHIFT (0U) +/*! PADDR1 - Pause Address */ +#define ENET_PALR_PADDR1(x) (((uint32_t)(((uint32_t)(x)) << ENET_PALR_PADDR1_SHIFT)) & ENET_PALR_PADDR1_MASK) +/*! @} */ + +/*! @name PAUR - Physical Address Upper Register */ +/*! @{ */ + +#define ENET_PAUR_TYPE_MASK (0xFFFFU) +#define ENET_PAUR_TYPE_SHIFT (0U) +/*! TYPE - Type Field In PAUSE Frames */ +#define ENET_PAUR_TYPE(x) (((uint32_t)(((uint32_t)(x)) << ENET_PAUR_TYPE_SHIFT)) & ENET_PAUR_TYPE_MASK) + +#define ENET_PAUR_PADDR2_MASK (0xFFFF0000U) +#define ENET_PAUR_PADDR2_SHIFT (16U) +#define ENET_PAUR_PADDR2(x) (((uint32_t)(((uint32_t)(x)) << ENET_PAUR_PADDR2_SHIFT)) & ENET_PAUR_PADDR2_MASK) +/*! @} */ + +/*! @name OPD - Opcode/Pause Duration Register */ +/*! @{ */ + +#define ENET_OPD_PAUSE_DUR_MASK (0xFFFFU) +#define ENET_OPD_PAUSE_DUR_SHIFT (0U) +/*! PAUSE_DUR - Pause Duration */ +#define ENET_OPD_PAUSE_DUR(x) (((uint32_t)(((uint32_t)(x)) << ENET_OPD_PAUSE_DUR_SHIFT)) & ENET_OPD_PAUSE_DUR_MASK) + +#define ENET_OPD_OPCODE_MASK (0xFFFF0000U) +#define ENET_OPD_OPCODE_SHIFT (16U) +/*! OPCODE - Opcode Field In PAUSE Frames */ +#define ENET_OPD_OPCODE(x) (((uint32_t)(((uint32_t)(x)) << ENET_OPD_OPCODE_SHIFT)) & ENET_OPD_OPCODE_MASK) +/*! @} */ + +/*! @name TXIC - Transmit Interrupt Coalescing Register */ +/*! @{ */ + +#define ENET_TXIC_ICTT_MASK (0xFFFFU) +#define ENET_TXIC_ICTT_SHIFT (0U) +/*! ICTT - Interrupt coalescing timer threshold */ +#define ENET_TXIC_ICTT(x) (((uint32_t)(((uint32_t)(x)) << ENET_TXIC_ICTT_SHIFT)) & ENET_TXIC_ICTT_MASK) + +#define ENET_TXIC_ICFT_MASK (0xFF00000U) +#define ENET_TXIC_ICFT_SHIFT (20U) +/*! ICFT - Interrupt coalescing frame count threshold */ +#define ENET_TXIC_ICFT(x) (((uint32_t)(((uint32_t)(x)) << ENET_TXIC_ICFT_SHIFT)) & ENET_TXIC_ICFT_MASK) + +#define ENET_TXIC_ICCS_MASK (0x40000000U) +#define ENET_TXIC_ICCS_SHIFT (30U) +/*! ICCS - Interrupt Coalescing Timer Clock Source Select + * 0b0..Use MII/GMII TX clocks. + * 0b1..Use ENET system clock. + */ +#define ENET_TXIC_ICCS(x) (((uint32_t)(((uint32_t)(x)) << ENET_TXIC_ICCS_SHIFT)) & ENET_TXIC_ICCS_MASK) + +#define ENET_TXIC_ICEN_MASK (0x80000000U) +#define ENET_TXIC_ICEN_SHIFT (31U) +/*! ICEN - Interrupt Coalescing Enable + * 0b0..Disable Interrupt coalescing. + * 0b1..Enable Interrupt coalescing. + */ +#define ENET_TXIC_ICEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_TXIC_ICEN_SHIFT)) & ENET_TXIC_ICEN_MASK) +/*! @} */ + +/* The count of ENET_TXIC */ +#define ENET_TXIC_COUNT (3U) + +/*! @name RXIC - Receive Interrupt Coalescing Register */ +/*! @{ */ + +#define ENET_RXIC_ICTT_MASK (0xFFFFU) +#define ENET_RXIC_ICTT_SHIFT (0U) +/*! ICTT - Interrupt coalescing timer threshold */ +#define ENET_RXIC_ICTT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RXIC_ICTT_SHIFT)) & ENET_RXIC_ICTT_MASK) + +#define ENET_RXIC_ICFT_MASK (0xFF00000U) +#define ENET_RXIC_ICFT_SHIFT (20U) +/*! ICFT - Interrupt coalescing frame count threshold */ +#define ENET_RXIC_ICFT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RXIC_ICFT_SHIFT)) & ENET_RXIC_ICFT_MASK) + +#define ENET_RXIC_ICCS_MASK (0x40000000U) +#define ENET_RXIC_ICCS_SHIFT (30U) +/*! ICCS - Interrupt Coalescing Timer Clock Source Select + * 0b0..Use MII/GMII TX clocks. + * 0b1..Use ENET system clock. + */ +#define ENET_RXIC_ICCS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RXIC_ICCS_SHIFT)) & ENET_RXIC_ICCS_MASK) + +#define ENET_RXIC_ICEN_MASK (0x80000000U) +#define ENET_RXIC_ICEN_SHIFT (31U) +/*! ICEN - Interrupt Coalescing Enable + * 0b0..Disable Interrupt coalescing. + * 0b1..Enable Interrupt coalescing. + */ +#define ENET_RXIC_ICEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_RXIC_ICEN_SHIFT)) & ENET_RXIC_ICEN_MASK) +/*! @} */ + +/* The count of ENET_RXIC */ +#define ENET_RXIC_COUNT (3U) + +/*! @name IAUR - Descriptor Individual Upper Address Register */ +/*! @{ */ + +#define ENET_IAUR_IADDR1_MASK (0xFFFFFFFFU) +#define ENET_IAUR_IADDR1_SHIFT (0U) +#define ENET_IAUR_IADDR1(x) (((uint32_t)(((uint32_t)(x)) << ENET_IAUR_IADDR1_SHIFT)) & ENET_IAUR_IADDR1_MASK) +/*! @} */ + +/*! @name IALR - Descriptor Individual Lower Address Register */ +/*! @{ */ + +#define ENET_IALR_IADDR2_MASK (0xFFFFFFFFU) +#define ENET_IALR_IADDR2_SHIFT (0U) +#define ENET_IALR_IADDR2(x) (((uint32_t)(((uint32_t)(x)) << ENET_IALR_IADDR2_SHIFT)) & ENET_IALR_IADDR2_MASK) +/*! @} */ + +/*! @name GAUR - Descriptor Group Upper Address Register */ +/*! @{ */ + +#define ENET_GAUR_GADDR1_MASK (0xFFFFFFFFU) +#define ENET_GAUR_GADDR1_SHIFT (0U) +#define ENET_GAUR_GADDR1(x) (((uint32_t)(((uint32_t)(x)) << ENET_GAUR_GADDR1_SHIFT)) & ENET_GAUR_GADDR1_MASK) +/*! @} */ + +/*! @name GALR - Descriptor Group Lower Address Register */ +/*! @{ */ + +#define ENET_GALR_GADDR2_MASK (0xFFFFFFFFU) +#define ENET_GALR_GADDR2_SHIFT (0U) +#define ENET_GALR_GADDR2(x) (((uint32_t)(((uint32_t)(x)) << ENET_GALR_GADDR2_SHIFT)) & ENET_GALR_GADDR2_MASK) +/*! @} */ + +/*! @name TFWR - Transmit FIFO Watermark Register */ +/*! @{ */ + +#define ENET_TFWR_TFWR_MASK (0x3FU) +#define ENET_TFWR_TFWR_SHIFT (0U) +/*! TFWR - Transmit FIFO Write + * 0b000000..64 bytes written. + * 0b000001..64 bytes written. + * 0b000010..128 bytes written. + * 0b000011..192 bytes written. + * 0b111111..4032 bytes written. + */ +#define ENET_TFWR_TFWR(x) (((uint32_t)(((uint32_t)(x)) << ENET_TFWR_TFWR_SHIFT)) & ENET_TFWR_TFWR_MASK) + +#define ENET_TFWR_STRFWD_MASK (0x100U) +#define ENET_TFWR_STRFWD_SHIFT (8U) +/*! STRFWD - Store And Forward Enable + * 0b0..Reset. The transmission start threshold is programmed in TFWR[TFWR]. + * 0b1..Enabled. + */ +#define ENET_TFWR_STRFWD(x) (((uint32_t)(((uint32_t)(x)) << ENET_TFWR_STRFWD_SHIFT)) & ENET_TFWR_STRFWD_MASK) +/*! @} */ + +/*! @name RDSR1 - Receive Descriptor Ring 1 Start Register */ +/*! @{ */ + +#define ENET_RDSR1_R_DES_START_MASK (0xFFFFFFF8U) +#define ENET_RDSR1_R_DES_START_SHIFT (3U) +#define ENET_RDSR1_R_DES_START(x) (((uint32_t)(((uint32_t)(x)) << ENET_RDSR1_R_DES_START_SHIFT)) & ENET_RDSR1_R_DES_START_MASK) +/*! @} */ + +/*! @name TDSR1 - Transmit Buffer Descriptor Ring 1 Start Register */ +/*! @{ */ + +#define ENET_TDSR1_X_DES_START_MASK (0xFFFFFFF8U) +#define ENET_TDSR1_X_DES_START_SHIFT (3U) +#define ENET_TDSR1_X_DES_START(x) (((uint32_t)(((uint32_t)(x)) << ENET_TDSR1_X_DES_START_SHIFT)) & ENET_TDSR1_X_DES_START_MASK) +/*! @} */ + +/*! @name MRBR1 - Maximum Receive Buffer Size Register - Ring 1 */ +/*! @{ */ + +#define ENET_MRBR1_R_BUF_SIZE_MASK (0x3FF0U) +#define ENET_MRBR1_R_BUF_SIZE_SHIFT (4U) +#define ENET_MRBR1_R_BUF_SIZE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MRBR1_R_BUF_SIZE_SHIFT)) & ENET_MRBR1_R_BUF_SIZE_MASK) +/*! @} */ + +/*! @name RDSR2 - Receive Descriptor Ring 2 Start Register */ +/*! @{ */ + +#define ENET_RDSR2_R_DES_START_MASK (0xFFFFFFF8U) +#define ENET_RDSR2_R_DES_START_SHIFT (3U) +#define ENET_RDSR2_R_DES_START(x) (((uint32_t)(((uint32_t)(x)) << ENET_RDSR2_R_DES_START_SHIFT)) & ENET_RDSR2_R_DES_START_MASK) +/*! @} */ + +/*! @name TDSR2 - Transmit Buffer Descriptor Ring 2 Start Register */ +/*! @{ */ + +#define ENET_TDSR2_X_DES_START_MASK (0xFFFFFFF8U) +#define ENET_TDSR2_X_DES_START_SHIFT (3U) +#define ENET_TDSR2_X_DES_START(x) (((uint32_t)(((uint32_t)(x)) << ENET_TDSR2_X_DES_START_SHIFT)) & ENET_TDSR2_X_DES_START_MASK) +/*! @} */ + +/*! @name MRBR2 - Maximum Receive Buffer Size Register - Ring 2 */ +/*! @{ */ + +#define ENET_MRBR2_R_BUF_SIZE_MASK (0x3FF0U) +#define ENET_MRBR2_R_BUF_SIZE_SHIFT (4U) +#define ENET_MRBR2_R_BUF_SIZE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MRBR2_R_BUF_SIZE_SHIFT)) & ENET_MRBR2_R_BUF_SIZE_MASK) +/*! @} */ + +/*! @name RDSR - Receive Descriptor Ring 0 Start Register */ +/*! @{ */ + +#define ENET_RDSR_R_DES_START_MASK (0xFFFFFFF8U) +#define ENET_RDSR_R_DES_START_SHIFT (3U) +#define ENET_RDSR_R_DES_START(x) (((uint32_t)(((uint32_t)(x)) << ENET_RDSR_R_DES_START_SHIFT)) & ENET_RDSR_R_DES_START_MASK) +/*! @} */ + +/*! @name TDSR - Transmit Buffer Descriptor Ring 0 Start Register */ +/*! @{ */ + +#define ENET_TDSR_X_DES_START_MASK (0xFFFFFFF8U) +#define ENET_TDSR_X_DES_START_SHIFT (3U) +#define ENET_TDSR_X_DES_START(x) (((uint32_t)(((uint32_t)(x)) << ENET_TDSR_X_DES_START_SHIFT)) & ENET_TDSR_X_DES_START_MASK) +/*! @} */ + +/*! @name MRBR - Maximum Receive Buffer Size Register - Ring 0 */ +/*! @{ */ + +#define ENET_MRBR_R_BUF_SIZE_MASK (0x3FF0U) +#define ENET_MRBR_R_BUF_SIZE_SHIFT (4U) +#define ENET_MRBR_R_BUF_SIZE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MRBR_R_BUF_SIZE_SHIFT)) & ENET_MRBR_R_BUF_SIZE_MASK) +/*! @} */ + +/*! @name RSFL - Receive FIFO Section Full Threshold */ +/*! @{ */ + +#define ENET_RSFL_RX_SECTION_FULL_MASK (0x3FFU) +#define ENET_RSFL_RX_SECTION_FULL_SHIFT (0U) +/*! RX_SECTION_FULL - Value Of Receive FIFO Section Full Threshold */ +#define ENET_RSFL_RX_SECTION_FULL(x) (((uint32_t)(((uint32_t)(x)) << ENET_RSFL_RX_SECTION_FULL_SHIFT)) & ENET_RSFL_RX_SECTION_FULL_MASK) +/*! @} */ + +/*! @name RSEM - Receive FIFO Section Empty Threshold */ +/*! @{ */ + +#define ENET_RSEM_RX_SECTION_EMPTY_MASK (0x3FFU) +#define ENET_RSEM_RX_SECTION_EMPTY_SHIFT (0U) +/*! RX_SECTION_EMPTY - Value Of The Receive FIFO Section Empty Threshold */ +#define ENET_RSEM_RX_SECTION_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << ENET_RSEM_RX_SECTION_EMPTY_SHIFT)) & ENET_RSEM_RX_SECTION_EMPTY_MASK) + +#define ENET_RSEM_STAT_SECTION_EMPTY_MASK (0x1F0000U) +#define ENET_RSEM_STAT_SECTION_EMPTY_SHIFT (16U) +/*! STAT_SECTION_EMPTY - RX Status FIFO Section Empty Threshold */ +#define ENET_RSEM_STAT_SECTION_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << ENET_RSEM_STAT_SECTION_EMPTY_SHIFT)) & ENET_RSEM_STAT_SECTION_EMPTY_MASK) +/*! @} */ + +/*! @name RAEM - Receive FIFO Almost Empty Threshold */ +/*! @{ */ + +#define ENET_RAEM_RX_ALMOST_EMPTY_MASK (0x3FFU) +#define ENET_RAEM_RX_ALMOST_EMPTY_SHIFT (0U) +/*! RX_ALMOST_EMPTY - Value Of The Receive FIFO Almost Empty Threshold */ +#define ENET_RAEM_RX_ALMOST_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << ENET_RAEM_RX_ALMOST_EMPTY_SHIFT)) & ENET_RAEM_RX_ALMOST_EMPTY_MASK) +/*! @} */ + +/*! @name RAFL - Receive FIFO Almost Full Threshold */ +/*! @{ */ + +#define ENET_RAFL_RX_ALMOST_FULL_MASK (0x3FFU) +#define ENET_RAFL_RX_ALMOST_FULL_SHIFT (0U) +/*! RX_ALMOST_FULL - Value Of The Receive FIFO Almost Full Threshold */ +#define ENET_RAFL_RX_ALMOST_FULL(x) (((uint32_t)(((uint32_t)(x)) << ENET_RAFL_RX_ALMOST_FULL_SHIFT)) & ENET_RAFL_RX_ALMOST_FULL_MASK) +/*! @} */ + +/*! @name TSEM - Transmit FIFO Section Empty Threshold */ +/*! @{ */ + +#define ENET_TSEM_TX_SECTION_EMPTY_MASK (0x3FFU) +#define ENET_TSEM_TX_SECTION_EMPTY_SHIFT (0U) +/*! TX_SECTION_EMPTY - Value Of The Transmit FIFO Section Empty Threshold */ +#define ENET_TSEM_TX_SECTION_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << ENET_TSEM_TX_SECTION_EMPTY_SHIFT)) & ENET_TSEM_TX_SECTION_EMPTY_MASK) +/*! @} */ + +/*! @name TAEM - Transmit FIFO Almost Empty Threshold */ +/*! @{ */ + +#define ENET_TAEM_TX_ALMOST_EMPTY_MASK (0x3FFU) +#define ENET_TAEM_TX_ALMOST_EMPTY_SHIFT (0U) +/*! TX_ALMOST_EMPTY - Value of Transmit FIFO Almost Empty Threshold */ +#define ENET_TAEM_TX_ALMOST_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << ENET_TAEM_TX_ALMOST_EMPTY_SHIFT)) & ENET_TAEM_TX_ALMOST_EMPTY_MASK) +/*! @} */ + +/*! @name TAFL - Transmit FIFO Almost Full Threshold */ +/*! @{ */ + +#define ENET_TAFL_TX_ALMOST_FULL_MASK (0x3FFU) +#define ENET_TAFL_TX_ALMOST_FULL_SHIFT (0U) +/*! TX_ALMOST_FULL - Value Of The Transmit FIFO Almost Full Threshold */ +#define ENET_TAFL_TX_ALMOST_FULL(x) (((uint32_t)(((uint32_t)(x)) << ENET_TAFL_TX_ALMOST_FULL_SHIFT)) & ENET_TAFL_TX_ALMOST_FULL_MASK) +/*! @} */ + +/*! @name TIPG - Transmit Inter-Packet Gap */ +/*! @{ */ + +#define ENET_TIPG_IPG_MASK (0x1FU) +#define ENET_TIPG_IPG_SHIFT (0U) +/*! IPG - Transmit Inter-Packet Gap */ +#define ENET_TIPG_IPG(x) (((uint32_t)(((uint32_t)(x)) << ENET_TIPG_IPG_SHIFT)) & ENET_TIPG_IPG_MASK) +/*! @} */ + +/*! @name FTRL - Frame Truncation Length */ +/*! @{ */ + +#define ENET_FTRL_TRUNC_FL_MASK (0x3FFFU) +#define ENET_FTRL_TRUNC_FL_SHIFT (0U) +/*! TRUNC_FL - Frame Truncation Length */ +#define ENET_FTRL_TRUNC_FL(x) (((uint32_t)(((uint32_t)(x)) << ENET_FTRL_TRUNC_FL_SHIFT)) & ENET_FTRL_TRUNC_FL_MASK) +/*! @} */ + +/*! @name TACC - Transmit Accelerator Function Configuration */ +/*! @{ */ + +#define ENET_TACC_SHIFT16_MASK (0x1U) +#define ENET_TACC_SHIFT16_SHIFT (0U) +/*! SHIFT16 - TX FIFO Shift-16 + * 0b0..Disabled. + * 0b1..Indicates to the transmit data FIFO that the written frames contain two additional octets before the + * frame data. This means the actual frame begins at bit 16 of the first word written into the FIFO. This + * function allows putting the frame payload on a 32-bit boundary in memory, as the 14-byte Ethernet header is + * extended to a 16-byte header. + */ +#define ENET_TACC_SHIFT16(x) (((uint32_t)(((uint32_t)(x)) << ENET_TACC_SHIFT16_SHIFT)) & ENET_TACC_SHIFT16_MASK) + +#define ENET_TACC_IPCHK_MASK (0x8U) +#define ENET_TACC_IPCHK_SHIFT (3U) +/*! IPCHK + * 0b0..Checksum is not inserted. + * 0b1..If an IP frame is transmitted, the checksum is inserted automatically. The IP header checksum field must + * be cleared. If a non-IP frame is transmitted the frame is not modified. + */ +#define ENET_TACC_IPCHK(x) (((uint32_t)(((uint32_t)(x)) << ENET_TACC_IPCHK_SHIFT)) & ENET_TACC_IPCHK_MASK) + +#define ENET_TACC_PROCHK_MASK (0x10U) +#define ENET_TACC_PROCHK_SHIFT (4U) +/*! PROCHK + * 0b0..Checksum not inserted. + * 0b1..If an IP frame with a known protocol is transmitted, the checksum is inserted automatically into the + * frame. The checksum field must be cleared. The other frames are not modified. + */ +#define ENET_TACC_PROCHK(x) (((uint32_t)(((uint32_t)(x)) << ENET_TACC_PROCHK_SHIFT)) & ENET_TACC_PROCHK_MASK) +/*! @} */ + +/*! @name RACC - Receive Accelerator Function Configuration */ +/*! @{ */ + +#define ENET_RACC_PADREM_MASK (0x1U) +#define ENET_RACC_PADREM_SHIFT (0U) +/*! PADREM - Enable Padding Removal For Short IP Frames + * 0b0..Padding not removed. + * 0b1..Any bytes following the IP payload section of the frame are removed from the frame. + */ +#define ENET_RACC_PADREM(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_PADREM_SHIFT)) & ENET_RACC_PADREM_MASK) + +#define ENET_RACC_IPDIS_MASK (0x2U) +#define ENET_RACC_IPDIS_SHIFT (1U) +/*! IPDIS - Enable Discard Of Frames With Wrong IPv4 Header Checksum + * 0b0..Frames with wrong IPv4 header checksum are not discarded. + * 0b1..If an IPv4 frame is received with a mismatching header checksum, the frame is discarded. IPv6 has no + * header checksum and is not affected by this setting. Discarding is only available when the RX FIFO operates in + * store and forward mode (RSFL cleared). + */ +#define ENET_RACC_IPDIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_IPDIS_SHIFT)) & ENET_RACC_IPDIS_MASK) + +#define ENET_RACC_PRODIS_MASK (0x4U) +#define ENET_RACC_PRODIS_SHIFT (2U) +/*! PRODIS - Enable Discard Of Frames With Wrong Protocol Checksum + * 0b0..Frames with wrong checksum are not discarded. + * 0b1..If a TCP/IP, UDP/IP, or ICMP/IP frame is received that has a wrong TCP, UDP, or ICMP checksum, the frame + * is discarded. Discarding is only available when the RX FIFO operates in store and forward mode (RSFL + * cleared). + */ +#define ENET_RACC_PRODIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_PRODIS_SHIFT)) & ENET_RACC_PRODIS_MASK) + +#define ENET_RACC_LINEDIS_MASK (0x40U) +#define ENET_RACC_LINEDIS_SHIFT (6U) +/*! LINEDIS - Enable Discard Of Frames With MAC Layer Errors + * 0b0..Frames with errors are not discarded. + * 0b1..Any frame received with a CRC, length, or PHY error is automatically discarded and not forwarded to the user application interface. + */ +#define ENET_RACC_LINEDIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_LINEDIS_SHIFT)) & ENET_RACC_LINEDIS_MASK) + +#define ENET_RACC_SHIFT16_MASK (0x80U) +#define ENET_RACC_SHIFT16_SHIFT (7U) +/*! SHIFT16 - RX FIFO Shift-16 + * 0b0..Disabled. + * 0b1..Instructs the MAC to write two additional bytes in front of each frame received into the RX FIFO. + */ +#define ENET_RACC_SHIFT16(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_SHIFT16_SHIFT)) & ENET_RACC_SHIFT16_MASK) +/*! @} */ + +/*! @name RCMR - Receive Classification Match Register for Class n */ +/*! @{ */ + +#define ENET_RCMR_CMP0_MASK (0x7U) +#define ENET_RCMR_CMP0_SHIFT (0U) +/*! CMP0 - Compare 0 */ +#define ENET_RCMR_CMP0(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCMR_CMP0_SHIFT)) & ENET_RCMR_CMP0_MASK) + +#define ENET_RCMR_CMP1_MASK (0x70U) +#define ENET_RCMR_CMP1_SHIFT (4U) +/*! CMP1 - Compare 1 */ +#define ENET_RCMR_CMP1(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCMR_CMP1_SHIFT)) & ENET_RCMR_CMP1_MASK) + +#define ENET_RCMR_CMP2_MASK (0x700U) +#define ENET_RCMR_CMP2_SHIFT (8U) +/*! CMP2 - Compare 2 */ +#define ENET_RCMR_CMP2(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCMR_CMP2_SHIFT)) & ENET_RCMR_CMP2_MASK) + +#define ENET_RCMR_CMP3_MASK (0x7000U) +#define ENET_RCMR_CMP3_SHIFT (12U) +/*! CMP3 - Compare 3 */ +#define ENET_RCMR_CMP3(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCMR_CMP3_SHIFT)) & ENET_RCMR_CMP3_MASK) + +#define ENET_RCMR_MATCHEN_MASK (0x10000U) +#define ENET_RCMR_MATCHEN_SHIFT (16U) +/*! MATCHEN - Match Enable + * 0b0..Disabled (default): no compares will occur and the classification indicator for this class will never assert. + * 0b1..The register contents are valid and a comparison with all compare values is done when a VLAN frame is received. + */ +#define ENET_RCMR_MATCHEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCMR_MATCHEN_SHIFT)) & ENET_RCMR_MATCHEN_MASK) +/*! @} */ + +/* The count of ENET_RCMR */ +#define ENET_RCMR_COUNT (2U) + +/*! @name DMACFG - DMA Class Based Configuration */ +/*! @{ */ + +#define ENET_DMACFG_IDLE_SLOPE_MASK (0xFFFFU) +#define ENET_DMACFG_IDLE_SLOPE_SHIFT (0U) +/*! IDLE_SLOPE - Idle slope */ +#define ENET_DMACFG_IDLE_SLOPE(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMACFG_IDLE_SLOPE_SHIFT)) & ENET_DMACFG_IDLE_SLOPE_MASK) + +#define ENET_DMACFG_DMA_CLASS_EN_MASK (0x10000U) +#define ENET_DMACFG_DMA_CLASS_EN_SHIFT (16U) +/*! DMA_CLASS_EN - DMA class enable + * 0b0..The DMA controller's channel for the class is not used. Disabling the DMA controller of a class also + * requires disabling the class match comparator for the class (see registers RCMRn). When class 1 and class 2 + * queues are disabled then their frames will be placed in queue 0. + * 0b1..Enable the DMA controller to support the corresponding descriptor ring for this class of traffic. + */ +#define ENET_DMACFG_DMA_CLASS_EN(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMACFG_DMA_CLASS_EN_SHIFT)) & ENET_DMACFG_DMA_CLASS_EN_MASK) + +#define ENET_DMACFG_CALC_NOIPG_MASK (0x20000U) +#define ENET_DMACFG_CALC_NOIPG_SHIFT (17U) +/*! CALC_NOIPG - Calculate no IPG + * 0b0..The traffic shaper function should consider 12 octets of IPG in addition to the frame data transferred + * for a frame when doing bandwidth calculations. This is the default. + * 0b1..Addition of 12 bytes for the IPG should be omitted when calculating the bandwidth (for traffic shaping, + * when writing a frame into the transmit FIFO, the shaper will usually consider 12 bytes of IPG for every + * frame as part of the bandwidth allocated by the frame. This addition can be suppressed, meaning short frames + * will become more bandwidth than large frames due to the relation of data to IPG overhead). + */ +#define ENET_DMACFG_CALC_NOIPG(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMACFG_CALC_NOIPG_SHIFT)) & ENET_DMACFG_CALC_NOIPG_MASK) +/*! @} */ + +/* The count of ENET_DMACFG */ +#define ENET_DMACFG_COUNT (2U) + +/*! @name RDAR1 - Receive Descriptor Active Register - Ring 1 */ +/*! @{ */ + +#define ENET_RDAR1_RDAR_MASK (0x1000000U) +#define ENET_RDAR1_RDAR_SHIFT (24U) +/*! RDAR - Receive Descriptor Active */ +#define ENET_RDAR1_RDAR(x) (((uint32_t)(((uint32_t)(x)) << ENET_RDAR1_RDAR_SHIFT)) & ENET_RDAR1_RDAR_MASK) +/*! @} */ + +/*! @name TDAR1 - Transmit Descriptor Active Register - Ring 1 */ +/*! @{ */ + +#define ENET_TDAR1_TDAR_MASK (0x1000000U) +#define ENET_TDAR1_TDAR_SHIFT (24U) +/*! TDAR - Transmit Descriptor Active */ +#define ENET_TDAR1_TDAR(x) (((uint32_t)(((uint32_t)(x)) << ENET_TDAR1_TDAR_SHIFT)) & ENET_TDAR1_TDAR_MASK) +/*! @} */ + +/*! @name RDAR2 - Receive Descriptor Active Register - Ring 2 */ +/*! @{ */ + +#define ENET_RDAR2_RDAR_MASK (0x1000000U) +#define ENET_RDAR2_RDAR_SHIFT (24U) +/*! RDAR - Receive Descriptor Active */ +#define ENET_RDAR2_RDAR(x) (((uint32_t)(((uint32_t)(x)) << ENET_RDAR2_RDAR_SHIFT)) & ENET_RDAR2_RDAR_MASK) +/*! @} */ + +/*! @name TDAR2 - Transmit Descriptor Active Register - Ring 2 */ +/*! @{ */ + +#define ENET_TDAR2_TDAR_MASK (0x1000000U) +#define ENET_TDAR2_TDAR_SHIFT (24U) +/*! TDAR - Transmit Descriptor Active */ +#define ENET_TDAR2_TDAR(x) (((uint32_t)(((uint32_t)(x)) << ENET_TDAR2_TDAR_SHIFT)) & ENET_TDAR2_TDAR_MASK) +/*! @} */ + +/*! @name QOS - QOS Scheme */ +/*! @{ */ + +#define ENET_QOS_TX_SCHEME_MASK (0x7U) +#define ENET_QOS_TX_SCHEME_SHIFT (0U) +/*! TX_SCHEME - TX scheme configuration + * 0b000..Credit-based scheme + * 0b001..Round-robin scheme + * 0b010-0b111..Reserved + */ +#define ENET_QOS_TX_SCHEME(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_TX_SCHEME_SHIFT)) & ENET_QOS_TX_SCHEME_MASK) + +#define ENET_QOS_RX_FLUSH0_MASK (0x8U) +#define ENET_QOS_RX_FLUSH0_SHIFT (3U) +/*! RX_FLUSH0 - RX Flush Ring 0 + * 0b0..Disable + * 0b1..Enable + */ +#define ENET_QOS_RX_FLUSH0(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_RX_FLUSH0_SHIFT)) & ENET_QOS_RX_FLUSH0_MASK) + +#define ENET_QOS_RX_FLUSH1_MASK (0x10U) +#define ENET_QOS_RX_FLUSH1_SHIFT (4U) +/*! RX_FLUSH1 - RX Flush Ring 1 + * 0b0..Disable + * 0b1..Enable + */ +#define ENET_QOS_RX_FLUSH1(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_RX_FLUSH1_SHIFT)) & ENET_QOS_RX_FLUSH1_MASK) + +#define ENET_QOS_RX_FLUSH2_MASK (0x20U) +#define ENET_QOS_RX_FLUSH2_SHIFT (5U) +/*! RX_FLUSH2 - RX Flush Ring 2 + * 0b0..Disable + * 0b1..Enable + */ +#define ENET_QOS_RX_FLUSH2(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_RX_FLUSH2_SHIFT)) & ENET_QOS_RX_FLUSH2_MASK) +/*! @} */ + +/*! @name RMON_T_PACKETS - Tx Packet Count Statistic Register */ +/*! @{ */ + +#define ENET_RMON_T_PACKETS_TXPKTS_MASK (0xFFFFU) +#define ENET_RMON_T_PACKETS_TXPKTS_SHIFT (0U) +/*! TXPKTS - Packet count */ +#define ENET_RMON_T_PACKETS_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_PACKETS_TXPKTS_SHIFT)) & ENET_RMON_T_PACKETS_TXPKTS_MASK) +/*! @} */ + +/*! @name RMON_T_BC_PKT - Tx Broadcast Packets Statistic Register */ +/*! @{ */ + +#define ENET_RMON_T_BC_PKT_TXPKTS_MASK (0xFFFFU) +#define ENET_RMON_T_BC_PKT_TXPKTS_SHIFT (0U) +/*! TXPKTS - Number of broadcast packets */ +#define ENET_RMON_T_BC_PKT_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_BC_PKT_TXPKTS_SHIFT)) & ENET_RMON_T_BC_PKT_TXPKTS_MASK) +/*! @} */ + +/*! @name RMON_T_MC_PKT - Tx Multicast Packets Statistic Register */ +/*! @{ */ + +#define ENET_RMON_T_MC_PKT_TXPKTS_MASK (0xFFFFU) +#define ENET_RMON_T_MC_PKT_TXPKTS_SHIFT (0U) +/*! TXPKTS - Number of multicast packets */ +#define ENET_RMON_T_MC_PKT_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_MC_PKT_TXPKTS_SHIFT)) & ENET_RMON_T_MC_PKT_TXPKTS_MASK) +/*! @} */ + +/*! @name RMON_T_CRC_ALIGN - Tx Packets with CRC/Align Error Statistic Register */ +/*! @{ */ + +#define ENET_RMON_T_CRC_ALIGN_TXPKTS_MASK (0xFFFFU) +#define ENET_RMON_T_CRC_ALIGN_TXPKTS_SHIFT (0U) +/*! TXPKTS - Number of packets with CRC/align error */ +#define ENET_RMON_T_CRC_ALIGN_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_CRC_ALIGN_TXPKTS_SHIFT)) & ENET_RMON_T_CRC_ALIGN_TXPKTS_MASK) +/*! @} */ + +/*! @name RMON_T_UNDERSIZE - Tx Packets Less Than Bytes and Good CRC Statistic Register */ +/*! @{ */ + +#define ENET_RMON_T_UNDERSIZE_TXPKTS_MASK (0xFFFFU) +#define ENET_RMON_T_UNDERSIZE_TXPKTS_SHIFT (0U) +/*! TXPKTS - Number of transmit packets less than 64 bytes with good CRC */ +#define ENET_RMON_T_UNDERSIZE_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_UNDERSIZE_TXPKTS_SHIFT)) & ENET_RMON_T_UNDERSIZE_TXPKTS_MASK) +/*! @} */ + +/*! @name RMON_T_OVERSIZE - Tx Packets GT MAX_FL bytes and Good CRC Statistic Register */ +/*! @{ */ + +#define ENET_RMON_T_OVERSIZE_TXPKTS_MASK (0xFFFFU) +#define ENET_RMON_T_OVERSIZE_TXPKTS_SHIFT (0U) +/*! TXPKTS - Number of transmit packets greater than MAX_FL bytes with good CRC */ +#define ENET_RMON_T_OVERSIZE_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_OVERSIZE_TXPKTS_SHIFT)) & ENET_RMON_T_OVERSIZE_TXPKTS_MASK) +/*! @} */ + +/*! @name RMON_T_FRAG - Tx Packets Less Than 64 Bytes and Bad CRC Statistic Register */ +/*! @{ */ + +#define ENET_RMON_T_FRAG_TXPKTS_MASK (0xFFFFU) +#define ENET_RMON_T_FRAG_TXPKTS_SHIFT (0U) +/*! TXPKTS - Number of packets less than 64 bytes with bad CRC */ +#define ENET_RMON_T_FRAG_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_FRAG_TXPKTS_SHIFT)) & ENET_RMON_T_FRAG_TXPKTS_MASK) +/*! @} */ + +/*! @name RMON_T_JAB - Tx Packets Greater Than MAX_FL bytes and Bad CRC Statistic Register */ +/*! @{ */ + +#define ENET_RMON_T_JAB_TXPKTS_MASK (0xFFFFU) +#define ENET_RMON_T_JAB_TXPKTS_SHIFT (0U) +/*! TXPKTS - Number of transmit packets greater than MAX_FL bytes and bad CRC */ +#define ENET_RMON_T_JAB_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_JAB_TXPKTS_SHIFT)) & ENET_RMON_T_JAB_TXPKTS_MASK) +/*! @} */ + +/*! @name RMON_T_COL - Tx Collision Count Statistic Register */ +/*! @{ */ + +#define ENET_RMON_T_COL_TXPKTS_MASK (0xFFFFU) +#define ENET_RMON_T_COL_TXPKTS_SHIFT (0U) +/*! TXPKTS - Number of transmit collisions */ +#define ENET_RMON_T_COL_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_COL_TXPKTS_SHIFT)) & ENET_RMON_T_COL_TXPKTS_MASK) +/*! @} */ + +/*! @name RMON_T_P64 - Tx 64-Byte Packets Statistic Register */ +/*! @{ */ + +#define ENET_RMON_T_P64_TXPKTS_MASK (0xFFFFU) +#define ENET_RMON_T_P64_TXPKTS_SHIFT (0U) +/*! TXPKTS - Number of 64-byte transmit packets */ +#define ENET_RMON_T_P64_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P64_TXPKTS_SHIFT)) & ENET_RMON_T_P64_TXPKTS_MASK) +/*! @} */ + +/*! @name RMON_T_P65TO127 - Tx 65- to 127-byte Packets Statistic Register */ +/*! @{ */ + +#define ENET_RMON_T_P65TO127_TXPKTS_MASK (0xFFFFU) +#define ENET_RMON_T_P65TO127_TXPKTS_SHIFT (0U) +/*! TXPKTS - Number of 65- to 127-byte transmit packets */ +#define ENET_RMON_T_P65TO127_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P65TO127_TXPKTS_SHIFT)) & ENET_RMON_T_P65TO127_TXPKTS_MASK) +/*! @} */ + +/*! @name RMON_T_P128TO255 - Tx 128- to 255-byte Packets Statistic Register */ +/*! @{ */ + +#define ENET_RMON_T_P128TO255_TXPKTS_MASK (0xFFFFU) +#define ENET_RMON_T_P128TO255_TXPKTS_SHIFT (0U) +/*! TXPKTS - Number of 128- to 255-byte transmit packets */ +#define ENET_RMON_T_P128TO255_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P128TO255_TXPKTS_SHIFT)) & ENET_RMON_T_P128TO255_TXPKTS_MASK) +/*! @} */ + +/*! @name RMON_T_P256TO511 - Tx 256- to 511-byte Packets Statistic Register */ +/*! @{ */ + +#define ENET_RMON_T_P256TO511_TXPKTS_MASK (0xFFFFU) +#define ENET_RMON_T_P256TO511_TXPKTS_SHIFT (0U) +/*! TXPKTS - Number of 256- to 511-byte transmit packets */ +#define ENET_RMON_T_P256TO511_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P256TO511_TXPKTS_SHIFT)) & ENET_RMON_T_P256TO511_TXPKTS_MASK) +/*! @} */ + +/*! @name RMON_T_P512TO1023 - Tx 512- to 1023-byte Packets Statistic Register */ +/*! @{ */ + +#define ENET_RMON_T_P512TO1023_TXPKTS_MASK (0xFFFFU) +#define ENET_RMON_T_P512TO1023_TXPKTS_SHIFT (0U) +/*! TXPKTS - Number of 512- to 1023-byte transmit packets */ +#define ENET_RMON_T_P512TO1023_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P512TO1023_TXPKTS_SHIFT)) & ENET_RMON_T_P512TO1023_TXPKTS_MASK) +/*! @} */ + +/*! @name RMON_T_P1024TO2047 - Tx 1024- to 2047-byte Packets Statistic Register */ +/*! @{ */ + +#define ENET_RMON_T_P1024TO2047_TXPKTS_MASK (0xFFFFU) +#define ENET_RMON_T_P1024TO2047_TXPKTS_SHIFT (0U) +/*! TXPKTS - Number of 1024- to 2047-byte transmit packets */ +#define ENET_RMON_T_P1024TO2047_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P1024TO2047_TXPKTS_SHIFT)) & ENET_RMON_T_P1024TO2047_TXPKTS_MASK) +/*! @} */ + +/*! @name RMON_T_P_GTE2048 - Tx Packets Greater Than 2048 Bytes Statistic Register */ +/*! @{ */ + +#define ENET_RMON_T_P_GTE2048_TXPKTS_MASK (0xFFFFU) +#define ENET_RMON_T_P_GTE2048_TXPKTS_SHIFT (0U) +/*! TXPKTS - Number of transmit packets greater than 2048 bytes */ +#define ENET_RMON_T_P_GTE2048_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P_GTE2048_TXPKTS_SHIFT)) & ENET_RMON_T_P_GTE2048_TXPKTS_MASK) +/*! @} */ + +/*! @name RMON_T_OCTETS - Tx Octets Statistic Register */ +/*! @{ */ + +#define ENET_RMON_T_OCTETS_TXOCTS_MASK (0xFFFFFFFFU) +#define ENET_RMON_T_OCTETS_TXOCTS_SHIFT (0U) +/*! TXOCTS - Number of transmit octets */ +#define ENET_RMON_T_OCTETS_TXOCTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_OCTETS_TXOCTS_SHIFT)) & ENET_RMON_T_OCTETS_TXOCTS_MASK) +/*! @} */ + +/*! @name IEEE_T_FRAME_OK - Frames Transmitted OK Statistic Register */ +/*! @{ */ + +#define ENET_IEEE_T_FRAME_OK_COUNT_MASK (0xFFFFU) +#define ENET_IEEE_T_FRAME_OK_COUNT_SHIFT (0U) +/*! COUNT - Number of frames transmitted OK */ +#define ENET_IEEE_T_FRAME_OK_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_FRAME_OK_COUNT_SHIFT)) & ENET_IEEE_T_FRAME_OK_COUNT_MASK) +/*! @} */ + +/*! @name IEEE_T_1COL - Frames Transmitted with Single Collision Statistic Register */ +/*! @{ */ + +#define ENET_IEEE_T_1COL_COUNT_MASK (0xFFFFU) +#define ENET_IEEE_T_1COL_COUNT_SHIFT (0U) +/*! COUNT - Number of frames transmitted with one collision */ +#define ENET_IEEE_T_1COL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_1COL_COUNT_SHIFT)) & ENET_IEEE_T_1COL_COUNT_MASK) +/*! @} */ + +/*! @name IEEE_T_MCOL - Frames Transmitted with Multiple Collisions Statistic Register */ +/*! @{ */ + +#define ENET_IEEE_T_MCOL_COUNT_MASK (0xFFFFU) +#define ENET_IEEE_T_MCOL_COUNT_SHIFT (0U) +/*! COUNT - Number of frames transmitted with multiple collisions */ +#define ENET_IEEE_T_MCOL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_MCOL_COUNT_SHIFT)) & ENET_IEEE_T_MCOL_COUNT_MASK) +/*! @} */ + +/*! @name IEEE_T_DEF - Frames Transmitted after Deferral Delay Statistic Register */ +/*! @{ */ + +#define ENET_IEEE_T_DEF_COUNT_MASK (0xFFFFU) +#define ENET_IEEE_T_DEF_COUNT_SHIFT (0U) +/*! COUNT - Number of frames transmitted with deferral delay */ +#define ENET_IEEE_T_DEF_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_DEF_COUNT_SHIFT)) & ENET_IEEE_T_DEF_COUNT_MASK) +/*! @} */ + +/*! @name IEEE_T_LCOL - Frames Transmitted with Late Collision Statistic Register */ +/*! @{ */ + +#define ENET_IEEE_T_LCOL_COUNT_MASK (0xFFFFU) +#define ENET_IEEE_T_LCOL_COUNT_SHIFT (0U) +/*! COUNT - Number of frames transmitted with late collision */ +#define ENET_IEEE_T_LCOL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_LCOL_COUNT_SHIFT)) & ENET_IEEE_T_LCOL_COUNT_MASK) +/*! @} */ + +/*! @name IEEE_T_EXCOL - Frames Transmitted with Excessive Collisions Statistic Register */ +/*! @{ */ + +#define ENET_IEEE_T_EXCOL_COUNT_MASK (0xFFFFU) +#define ENET_IEEE_T_EXCOL_COUNT_SHIFT (0U) +/*! COUNT - Number of frames transmitted with excessive collisions */ +#define ENET_IEEE_T_EXCOL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_EXCOL_COUNT_SHIFT)) & ENET_IEEE_T_EXCOL_COUNT_MASK) +/*! @} */ + +/*! @name IEEE_T_MACERR - Frames Transmitted with Tx FIFO Underrun Statistic Register */ +/*! @{ */ + +#define ENET_IEEE_T_MACERR_COUNT_MASK (0xFFFFU) +#define ENET_IEEE_T_MACERR_COUNT_SHIFT (0U) +/*! COUNT - Number of frames transmitted with transmit FIFO underrun */ +#define ENET_IEEE_T_MACERR_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_MACERR_COUNT_SHIFT)) & ENET_IEEE_T_MACERR_COUNT_MASK) +/*! @} */ + +/*! @name IEEE_T_CSERR - Frames Transmitted with Carrier Sense Error Statistic Register */ +/*! @{ */ + +#define ENET_IEEE_T_CSERR_COUNT_MASK (0xFFFFU) +#define ENET_IEEE_T_CSERR_COUNT_SHIFT (0U) +/*! COUNT - Number of frames transmitted with carrier sense error */ +#define ENET_IEEE_T_CSERR_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_CSERR_COUNT_SHIFT)) & ENET_IEEE_T_CSERR_COUNT_MASK) +/*! @} */ + +/*! @name IEEE_T_SQE - Reserved Statistic Register */ +/*! @{ */ + +#define ENET_IEEE_T_SQE_COUNT_MASK (0xFFFFU) +#define ENET_IEEE_T_SQE_COUNT_SHIFT (0U) +/*! COUNT - This read-only field is reserved and always has the value 0 */ +#define ENET_IEEE_T_SQE_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_SQE_COUNT_SHIFT)) & ENET_IEEE_T_SQE_COUNT_MASK) +/*! @} */ + +/*! @name IEEE_T_FDXFC - Flow Control Pause Frames Transmitted Statistic Register */ +/*! @{ */ + +#define ENET_IEEE_T_FDXFC_COUNT_MASK (0xFFFFU) +#define ENET_IEEE_T_FDXFC_COUNT_SHIFT (0U) +/*! COUNT - Number of flow-control pause frames transmitted */ +#define ENET_IEEE_T_FDXFC_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_FDXFC_COUNT_SHIFT)) & ENET_IEEE_T_FDXFC_COUNT_MASK) +/*! @} */ + +/*! @name IEEE_T_OCTETS_OK - Octet Count for Frames Transmitted w/o Error Statistic Register */ +/*! @{ */ + +#define ENET_IEEE_T_OCTETS_OK_COUNT_MASK (0xFFFFFFFFU) +#define ENET_IEEE_T_OCTETS_OK_COUNT_SHIFT (0U) +/*! COUNT - Octet count for frames transmitted without error Counts total octets (includes header and FCS fields). */ +#define ENET_IEEE_T_OCTETS_OK_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_OCTETS_OK_COUNT_SHIFT)) & ENET_IEEE_T_OCTETS_OK_COUNT_MASK) +/*! @} */ + +/*! @name RMON_R_PACKETS - Rx Packet Count Statistic Register */ +/*! @{ */ + +#define ENET_RMON_R_PACKETS_COUNT_MASK (0xFFFFU) +#define ENET_RMON_R_PACKETS_COUNT_SHIFT (0U) +/*! COUNT - Number of packets received */ +#define ENET_RMON_R_PACKETS_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_PACKETS_COUNT_SHIFT)) & ENET_RMON_R_PACKETS_COUNT_MASK) +/*! @} */ + +/*! @name RMON_R_BC_PKT - Rx Broadcast Packets Statistic Register */ +/*! @{ */ + +#define ENET_RMON_R_BC_PKT_COUNT_MASK (0xFFFFU) +#define ENET_RMON_R_BC_PKT_COUNT_SHIFT (0U) +/*! COUNT - Number of receive broadcast packets */ +#define ENET_RMON_R_BC_PKT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_BC_PKT_COUNT_SHIFT)) & ENET_RMON_R_BC_PKT_COUNT_MASK) +/*! @} */ + +/*! @name RMON_R_MC_PKT - Rx Multicast Packets Statistic Register */ +/*! @{ */ + +#define ENET_RMON_R_MC_PKT_COUNT_MASK (0xFFFFU) +#define ENET_RMON_R_MC_PKT_COUNT_SHIFT (0U) +/*! COUNT - Number of receive multicast packets */ +#define ENET_RMON_R_MC_PKT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_MC_PKT_COUNT_SHIFT)) & ENET_RMON_R_MC_PKT_COUNT_MASK) +/*! @} */ + +/*! @name RMON_R_CRC_ALIGN - Rx Packets with CRC/Align Error Statistic Register */ +/*! @{ */ + +#define ENET_RMON_R_CRC_ALIGN_COUNT_MASK (0xFFFFU) +#define ENET_RMON_R_CRC_ALIGN_COUNT_SHIFT (0U) +/*! COUNT - Number of receive packets with CRC or align error */ +#define ENET_RMON_R_CRC_ALIGN_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_CRC_ALIGN_COUNT_SHIFT)) & ENET_RMON_R_CRC_ALIGN_COUNT_MASK) +/*! @} */ + +/*! @name RMON_R_UNDERSIZE - Rx Packets with Less Than 64 Bytes and Good CRC Statistic Register */ +/*! @{ */ + +#define ENET_RMON_R_UNDERSIZE_COUNT_MASK (0xFFFFU) +#define ENET_RMON_R_UNDERSIZE_COUNT_SHIFT (0U) +/*! COUNT - Number of receive packets with less than 64 bytes and good CRC */ +#define ENET_RMON_R_UNDERSIZE_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_UNDERSIZE_COUNT_SHIFT)) & ENET_RMON_R_UNDERSIZE_COUNT_MASK) +/*! @} */ + +/*! @name RMON_R_OVERSIZE - Rx Packets Greater Than MAX_FL and Good CRC Statistic Register */ +/*! @{ */ + +#define ENET_RMON_R_OVERSIZE_COUNT_MASK (0xFFFFU) +#define ENET_RMON_R_OVERSIZE_COUNT_SHIFT (0U) +/*! COUNT - Number of receive packets greater than MAX_FL and good CRC */ +#define ENET_RMON_R_OVERSIZE_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_OVERSIZE_COUNT_SHIFT)) & ENET_RMON_R_OVERSIZE_COUNT_MASK) +/*! @} */ + +/*! @name RMON_R_FRAG - Rx Packets Less Than 64 Bytes and Bad CRC Statistic Register */ +/*! @{ */ + +#define ENET_RMON_R_FRAG_COUNT_MASK (0xFFFFU) +#define ENET_RMON_R_FRAG_COUNT_SHIFT (0U) +/*! COUNT - Number of receive packets with less than 64 bytes and bad CRC */ +#define ENET_RMON_R_FRAG_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_FRAG_COUNT_SHIFT)) & ENET_RMON_R_FRAG_COUNT_MASK) +/*! @} */ + +/*! @name RMON_R_JAB - Rx Packets Greater Than MAX_FL Bytes and Bad CRC Statistic Register */ +/*! @{ */ + +#define ENET_RMON_R_JAB_COUNT_MASK (0xFFFFU) +#define ENET_RMON_R_JAB_COUNT_SHIFT (0U) +/*! COUNT - Number of receive packets greater than MAX_FL and bad CRC */ +#define ENET_RMON_R_JAB_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_JAB_COUNT_SHIFT)) & ENET_RMON_R_JAB_COUNT_MASK) +/*! @} */ + +/*! @name RMON_R_P64 - Rx 64-Byte Packets Statistic Register */ +/*! @{ */ + +#define ENET_RMON_R_P64_COUNT_MASK (0xFFFFU) +#define ENET_RMON_R_P64_COUNT_SHIFT (0U) +/*! COUNT - Number of 64-byte receive packets */ +#define ENET_RMON_R_P64_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P64_COUNT_SHIFT)) & ENET_RMON_R_P64_COUNT_MASK) +/*! @} */ + +/*! @name RMON_R_P65TO127 - Rx 65- to 127-Byte Packets Statistic Register */ +/*! @{ */ + +#define ENET_RMON_R_P65TO127_COUNT_MASK (0xFFFFU) +#define ENET_RMON_R_P65TO127_COUNT_SHIFT (0U) +/*! COUNT - Number of 65- to 127-byte receive packets */ +#define ENET_RMON_R_P65TO127_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P65TO127_COUNT_SHIFT)) & ENET_RMON_R_P65TO127_COUNT_MASK) +/*! @} */ + +/*! @name RMON_R_P128TO255 - Rx 128- to 255-Byte Packets Statistic Register */ +/*! @{ */ + +#define ENET_RMON_R_P128TO255_COUNT_MASK (0xFFFFU) +#define ENET_RMON_R_P128TO255_COUNT_SHIFT (0U) +/*! COUNT - Number of 128- to 255-byte receive packets */ +#define ENET_RMON_R_P128TO255_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P128TO255_COUNT_SHIFT)) & ENET_RMON_R_P128TO255_COUNT_MASK) +/*! @} */ + +/*! @name RMON_R_P256TO511 - Rx 256- to 511-Byte Packets Statistic Register */ +/*! @{ */ + +#define ENET_RMON_R_P256TO511_COUNT_MASK (0xFFFFU) +#define ENET_RMON_R_P256TO511_COUNT_SHIFT (0U) +/*! COUNT - Number of 256- to 511-byte receive packets */ +#define ENET_RMON_R_P256TO511_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P256TO511_COUNT_SHIFT)) & ENET_RMON_R_P256TO511_COUNT_MASK) +/*! @} */ + +/*! @name RMON_R_P512TO1023 - Rx 512- to 1023-Byte Packets Statistic Register */ +/*! @{ */ + +#define ENET_RMON_R_P512TO1023_COUNT_MASK (0xFFFFU) +#define ENET_RMON_R_P512TO1023_COUNT_SHIFT (0U) +/*! COUNT - Number of 512- to 1023-byte receive packets */ +#define ENET_RMON_R_P512TO1023_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P512TO1023_COUNT_SHIFT)) & ENET_RMON_R_P512TO1023_COUNT_MASK) +/*! @} */ + +/*! @name RMON_R_P1024TO2047 - Rx 1024- to 2047-Byte Packets Statistic Register */ +/*! @{ */ + +#define ENET_RMON_R_P1024TO2047_COUNT_MASK (0xFFFFU) +#define ENET_RMON_R_P1024TO2047_COUNT_SHIFT (0U) +/*! COUNT - Number of 1024- to 2047-byte receive packets */ +#define ENET_RMON_R_P1024TO2047_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P1024TO2047_COUNT_SHIFT)) & ENET_RMON_R_P1024TO2047_COUNT_MASK) +/*! @} */ + +/*! @name RMON_R_P_GTE2048 - Rx Packets Greater than 2048 Bytes Statistic Register */ +/*! @{ */ + +#define ENET_RMON_R_P_GTE2048_COUNT_MASK (0xFFFFU) +#define ENET_RMON_R_P_GTE2048_COUNT_SHIFT (0U) +/*! COUNT - Number of greater-than-2048-byte receive packets */ +#define ENET_RMON_R_P_GTE2048_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P_GTE2048_COUNT_SHIFT)) & ENET_RMON_R_P_GTE2048_COUNT_MASK) +/*! @} */ + +/*! @name RMON_R_OCTETS - Rx Octets Statistic Register */ +/*! @{ */ + +#define ENET_RMON_R_OCTETS_COUNT_MASK (0xFFFFFFFFU) +#define ENET_RMON_R_OCTETS_COUNT_SHIFT (0U) +/*! COUNT - Number of receive octets */ +#define ENET_RMON_R_OCTETS_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_OCTETS_COUNT_SHIFT)) & ENET_RMON_R_OCTETS_COUNT_MASK) +/*! @} */ + +/*! @name IEEE_R_DROP - Frames not Counted Correctly Statistic Register */ +/*! @{ */ + +#define ENET_IEEE_R_DROP_COUNT_MASK (0xFFFFU) +#define ENET_IEEE_R_DROP_COUNT_SHIFT (0U) +/*! COUNT - Frame count */ +#define ENET_IEEE_R_DROP_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_DROP_COUNT_SHIFT)) & ENET_IEEE_R_DROP_COUNT_MASK) +/*! @} */ + +/*! @name IEEE_R_FRAME_OK - Frames Received OK Statistic Register */ +/*! @{ */ + +#define ENET_IEEE_R_FRAME_OK_COUNT_MASK (0xFFFFU) +#define ENET_IEEE_R_FRAME_OK_COUNT_SHIFT (0U) +/*! COUNT - Number of frames received OK */ +#define ENET_IEEE_R_FRAME_OK_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_FRAME_OK_COUNT_SHIFT)) & ENET_IEEE_R_FRAME_OK_COUNT_MASK) +/*! @} */ + +/*! @name IEEE_R_CRC - Frames Received with CRC Error Statistic Register */ +/*! @{ */ + +#define ENET_IEEE_R_CRC_COUNT_MASK (0xFFFFU) +#define ENET_IEEE_R_CRC_COUNT_SHIFT (0U) +/*! COUNT - Number of frames received with CRC error */ +#define ENET_IEEE_R_CRC_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_CRC_COUNT_SHIFT)) & ENET_IEEE_R_CRC_COUNT_MASK) +/*! @} */ + +/*! @name IEEE_R_ALIGN - Frames Received with Alignment Error Statistic Register */ +/*! @{ */ + +#define ENET_IEEE_R_ALIGN_COUNT_MASK (0xFFFFU) +#define ENET_IEEE_R_ALIGN_COUNT_SHIFT (0U) +/*! COUNT - Number of frames received with alignment error */ +#define ENET_IEEE_R_ALIGN_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_ALIGN_COUNT_SHIFT)) & ENET_IEEE_R_ALIGN_COUNT_MASK) +/*! @} */ + +/*! @name IEEE_R_MACERR - Receive FIFO Overflow Count Statistic Register */ +/*! @{ */ + +#define ENET_IEEE_R_MACERR_COUNT_MASK (0xFFFFU) +#define ENET_IEEE_R_MACERR_COUNT_SHIFT (0U) +/*! COUNT - Receive FIFO overflow count */ +#define ENET_IEEE_R_MACERR_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_MACERR_COUNT_SHIFT)) & ENET_IEEE_R_MACERR_COUNT_MASK) +/*! @} */ + +/*! @name IEEE_R_FDXFC - Flow Control Pause Frames Received Statistic Register */ +/*! @{ */ + +#define ENET_IEEE_R_FDXFC_COUNT_MASK (0xFFFFU) +#define ENET_IEEE_R_FDXFC_COUNT_SHIFT (0U) +/*! COUNT - Number of flow-control pause frames received */ +#define ENET_IEEE_R_FDXFC_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_FDXFC_COUNT_SHIFT)) & ENET_IEEE_R_FDXFC_COUNT_MASK) +/*! @} */ + +/*! @name IEEE_R_OCTETS_OK - Octet Count for Frames Received without Error Statistic Register */ +/*! @{ */ + +#define ENET_IEEE_R_OCTETS_OK_COUNT_MASK (0xFFFFFFFFU) +#define ENET_IEEE_R_OCTETS_OK_COUNT_SHIFT (0U) +/*! COUNT - Number of octets for frames received without error */ +#define ENET_IEEE_R_OCTETS_OK_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_OCTETS_OK_COUNT_SHIFT)) & ENET_IEEE_R_OCTETS_OK_COUNT_MASK) +/*! @} */ + +/*! @name ATCR - Adjustable Timer Control Register */ +/*! @{ */ + +#define ENET_ATCR_EN_MASK (0x1U) +#define ENET_ATCR_EN_SHIFT (0U) +/*! EN - Enable Timer + * 0b0..The timer stops at the current value. + * 0b1..The timer starts incrementing. + */ +#define ENET_ATCR_EN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_EN_SHIFT)) & ENET_ATCR_EN_MASK) + +#define ENET_ATCR_OFFEN_MASK (0x4U) +#define ENET_ATCR_OFFEN_SHIFT (2U) +/*! OFFEN - Enable One-Shot Offset Event + * 0b0..Disable. + * 0b1..The timer can be reset to zero when the given offset time is reached (offset event). The field is cleared + * when the offset event is reached, so no further event occurs until the field is set again. The timer + * offset value must be set before setting this field. + */ +#define ENET_ATCR_OFFEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_OFFEN_SHIFT)) & ENET_ATCR_OFFEN_MASK) + +#define ENET_ATCR_OFFRST_MASK (0x8U) +#define ENET_ATCR_OFFRST_SHIFT (3U) +/*! OFFRST - Reset Timer On Offset Event + * 0b0..The timer is not affected and no action occurs, besides clearing OFFEN, when the offset is reached. + * 0b1..If OFFEN is set, the timer resets to zero when the offset setting is reached. The offset event does not cause a timer interrupt. + */ +#define ENET_ATCR_OFFRST(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_OFFRST_SHIFT)) & ENET_ATCR_OFFRST_MASK) + +#define ENET_ATCR_PEREN_MASK (0x10U) +#define ENET_ATCR_PEREN_SHIFT (4U) +/*! PEREN - Enable Periodical Event + * 0b0..Disable. + * 0b1..A period event interrupt can be generated (EIR[TS_TIMER]) and the event signal output is asserted when + * the timer wraps around according to the periodic setting ATPER. The timer period value must be set before + * setting this bit. Not all devices contain the event signal output. See the chip configuration details. + */ +#define ENET_ATCR_PEREN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_PEREN_SHIFT)) & ENET_ATCR_PEREN_MASK) + +#define ENET_ATCR_PINPER_MASK (0x80U) +#define ENET_ATCR_PINPER_SHIFT (7U) +/*! PINPER - Enables event signal output external pin frc_evt_period assertion on period event + * 0b0..Disable. + * 0b1..Enable. + */ +#define ENET_ATCR_PINPER(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_PINPER_SHIFT)) & ENET_ATCR_PINPER_MASK) + +#define ENET_ATCR_RESTART_MASK (0x200U) +#define ENET_ATCR_RESTART_SHIFT (9U) +/*! RESTART - Reset Timer */ +#define ENET_ATCR_RESTART(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_RESTART_SHIFT)) & ENET_ATCR_RESTART_MASK) + +#define ENET_ATCR_CAPTURE_MASK (0x800U) +#define ENET_ATCR_CAPTURE_SHIFT (11U) +/*! CAPTURE - Capture Timer Value + * 0b0..No effect. + * 0b1..The current time is captured and can be read from the ATVR register. + */ +#define ENET_ATCR_CAPTURE(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_CAPTURE_SHIFT)) & ENET_ATCR_CAPTURE_MASK) + +#define ENET_ATCR_SLAVE_MASK (0x2000U) +#define ENET_ATCR_SLAVE_SHIFT (13U) +/*! SLAVE - Enable Timer Slave Mode + * 0b0..The timer is active and all configuration fields in this register are relevant. + * 0b1..The internal timer is disabled and the externally provided timer value is used. All other fields, except + * CAPTURE, in this register have no effect. CAPTURE can still be used to capture the current timer value. + */ +#define ENET_ATCR_SLAVE(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_SLAVE_SHIFT)) & ENET_ATCR_SLAVE_MASK) +/*! @} */ + +/*! @name ATVR - Timer Value Register */ +/*! @{ */ + +#define ENET_ATVR_ATIME_MASK (0xFFFFFFFFU) +#define ENET_ATVR_ATIME_SHIFT (0U) +#define ENET_ATVR_ATIME(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATVR_ATIME_SHIFT)) & ENET_ATVR_ATIME_MASK) +/*! @} */ + +/*! @name ATOFF - Timer Offset Register */ +/*! @{ */ + +#define ENET_ATOFF_OFFSET_MASK (0xFFFFFFFFU) +#define ENET_ATOFF_OFFSET_SHIFT (0U) +#define ENET_ATOFF_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATOFF_OFFSET_SHIFT)) & ENET_ATOFF_OFFSET_MASK) +/*! @} */ + +/*! @name ATPER - Timer Period Register */ +/*! @{ */ + +#define ENET_ATPER_PERIOD_MASK (0xFFFFFFFFU) +#define ENET_ATPER_PERIOD_SHIFT (0U) +/*! PERIOD - Value for generating periodic events */ +#define ENET_ATPER_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATPER_PERIOD_SHIFT)) & ENET_ATPER_PERIOD_MASK) +/*! @} */ + +/*! @name ATCOR - Timer Correction Register */ +/*! @{ */ + +#define ENET_ATCOR_COR_MASK (0x7FFFFFFFU) +#define ENET_ATCOR_COR_SHIFT (0U) +/*! COR - Correction Counter Wrap-Around Value */ +#define ENET_ATCOR_COR(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCOR_COR_SHIFT)) & ENET_ATCOR_COR_MASK) +/*! @} */ + +/*! @name ATINC - Time-Stamping Clock Period Register */ +/*! @{ */ + +#define ENET_ATINC_INC_MASK (0x7FU) +#define ENET_ATINC_INC_SHIFT (0U) +/*! INC - Clock Period Of The Timestamping Clock (ts_clk) In Nanoseconds */ +#define ENET_ATINC_INC(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATINC_INC_SHIFT)) & ENET_ATINC_INC_MASK) + +#define ENET_ATINC_INC_CORR_MASK (0x7F00U) +#define ENET_ATINC_INC_CORR_SHIFT (8U) +/*! INC_CORR - Correction Increment Value */ +#define ENET_ATINC_INC_CORR(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATINC_INC_CORR_SHIFT)) & ENET_ATINC_INC_CORR_MASK) +/*! @} */ + +/*! @name ATSTMP - Timestamp of Last Transmitted Frame */ +/*! @{ */ + +#define ENET_ATSTMP_TIMESTAMP_MASK (0xFFFFFFFFU) +#define ENET_ATSTMP_TIMESTAMP_SHIFT (0U) +/*! TIMESTAMP - Timestamp of the last frame transmitted by the core that had TxBD[TS] set the + * ff_tx_ts_frm signal asserted from the user application + */ +#define ENET_ATSTMP_TIMESTAMP(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATSTMP_TIMESTAMP_SHIFT)) & ENET_ATSTMP_TIMESTAMP_MASK) +/*! @} */ + +/*! @name TGSR - Timer Global Status Register */ +/*! @{ */ + +#define ENET_TGSR_TF0_MASK (0x1U) +#define ENET_TGSR_TF0_SHIFT (0U) +/*! TF0 - Copy Of Timer Flag For Channel 0 + * 0b0..Timer Flag for Channel 0 is clear + * 0b1..Timer Flag for Channel 0 is set + */ +#define ENET_TGSR_TF0(x) (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF0_SHIFT)) & ENET_TGSR_TF0_MASK) + +#define ENET_TGSR_TF1_MASK (0x2U) +#define ENET_TGSR_TF1_SHIFT (1U) +/*! TF1 - Copy Of Timer Flag For Channel 1 + * 0b0..Timer Flag for Channel 1 is clear + * 0b1..Timer Flag for Channel 1 is set + */ +#define ENET_TGSR_TF1(x) (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF1_SHIFT)) & ENET_TGSR_TF1_MASK) + +#define ENET_TGSR_TF2_MASK (0x4U) +#define ENET_TGSR_TF2_SHIFT (2U) +/*! TF2 - Copy Of Timer Flag For Channel 2 + * 0b0..Timer Flag for Channel 2 is clear + * 0b1..Timer Flag for Channel 2 is set + */ +#define ENET_TGSR_TF2(x) (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF2_SHIFT)) & ENET_TGSR_TF2_MASK) + +#define ENET_TGSR_TF3_MASK (0x8U) +#define ENET_TGSR_TF3_SHIFT (3U) +/*! TF3 - Copy Of Timer Flag For Channel 3 + * 0b0..Timer Flag for Channel 3 is clear + * 0b1..Timer Flag for Channel 3 is set + */ +#define ENET_TGSR_TF3(x) (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF3_SHIFT)) & ENET_TGSR_TF3_MASK) +/*! @} */ + +/*! @name TCSR - Timer Control Status Register */ +/*! @{ */ + +#define ENET_TCSR_TDRE_MASK (0x1U) +#define ENET_TCSR_TDRE_SHIFT (0U) +/*! TDRE - Timer DMA Request Enable + * 0b0..DMA request is disabled + * 0b1..DMA request is enabled + */ +#define ENET_TCSR_TDRE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TDRE_SHIFT)) & ENET_TCSR_TDRE_MASK) + +#define ENET_TCSR_TMODE_MASK (0x3CU) +#define ENET_TCSR_TMODE_SHIFT (2U) +/*! TMODE - Timer Mode + * 0b0000..Timer Channel is disabled. + * 0b0001..Timer Channel is configured for Input Capture on rising edge. + * 0b0010..Timer Channel is configured for Input Capture on falling edge. + * 0b0011..Timer Channel is configured for Input Capture on both edges. + * 0b0100..Timer Channel is configured for Output Compare - software only. + * 0b0101..Timer Channel is configured for Output Compare - toggle output on compare. + * 0b0110..Timer Channel is configured for Output Compare - clear output on compare. + * 0b0111..Timer Channel is configured for Output Compare - set output on compare. + * 0b1000..Reserved + * 0b1010..Timer Channel is configured for Output Compare - clear output on compare, set output on overflow. + * 0b10x1..Timer Channel is configured for Output Compare - set output on compare, clear output on overflow. + * 0b110x..Reserved + * 0b1110..Timer Channel is configured for Output Compare - pulse output low on compare for one 1588-clock cycle. + * 0b1111..Timer Channel is configured for Output Compare - pulse output high on compare for one 1588-clock cycle. + */ +#define ENET_TCSR_TMODE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TMODE_SHIFT)) & ENET_TCSR_TMODE_MASK) + +#define ENET_TCSR_TIE_MASK (0x40U) +#define ENET_TCSR_TIE_SHIFT (6U) +/*! TIE - Timer Interrupt Enable + * 0b0..Interrupt is disabled + * 0b1..Interrupt is enabled + */ +#define ENET_TCSR_TIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TIE_SHIFT)) & ENET_TCSR_TIE_MASK) + +#define ENET_TCSR_TF_MASK (0x80U) +#define ENET_TCSR_TF_SHIFT (7U) +/*! TF - Timer Flag + * 0b0..Input Capture or Output Compare has not occurred. + * 0b1..Input Capture or Output Compare has occurred. + */ +#define ENET_TCSR_TF(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TF_SHIFT)) & ENET_TCSR_TF_MASK) +/*! @} */ + +/* The count of ENET_TCSR */ +#define ENET_TCSR_COUNT (4U) + +/*! @name TCCR - Timer Compare Capture Register */ +/*! @{ */ + +#define ENET_TCCR_TCC_MASK (0xFFFFFFFFU) +#define ENET_TCCR_TCC_SHIFT (0U) +/*! TCC - Timer Capture Compare */ +#define ENET_TCCR_TCC(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCCR_TCC_SHIFT)) & ENET_TCCR_TCC_MASK) +/*! @} */ + +/* The count of ENET_TCCR */ +#define ENET_TCCR_COUNT (4U) + + +/*! + * @} + */ /* end of group ENET_Register_Masks */ + + +/* ENET - Peripheral instance base addresses */ +/** Peripheral ENET2 base address */ +#define ENET2_BASE (0x42890000u) +/** Peripheral ENET2 base pointer */ +#define ENET2 ((ENET_Type *)ENET2_BASE) +/** Array initializer of ENET peripheral base addresses */ +#define ENET_BASE_ADDRS { 0u, 0u, ENET2_BASE } +/** Array initializer of ENET peripheral base pointers */ +#define ENET_BASE_PTRS { (ENET_Type *)0u, (ENET_Type *)0u, ENET2 } +/* ENET Buffer Descriptor and Buffer Address Alignment. */ +#define ENET_BUFF_ALIGNMENT (64U) + + +/*! + * @} + */ /* end of group ENET_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- ENET_QOS Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ENET_QOS_Peripheral_Access_Layer ENET_QOS Peripheral Access Layer + * @{ + */ + +/** ENET_QOS - Register Layout Typedef */ +typedef struct { + __IO uint32_t MAC_CONFIGURATION; /**< MAC Configuration Register, offset: 0x0 */ + __IO uint32_t MAC_EXT_CONFIGURATION; /**< MAC Extended Configuration Register, offset: 0x4 */ + __IO uint32_t MAC_PACKET_FILTER; /**< MAC Packet Filter, offset: 0x8 */ + __IO uint32_t MAC_WATCHDOG_TIMEOUT; /**< Watchdog Timeout, offset: 0xC */ + __IO uint32_t MAC_HASH_TABLE_REG0; /**< MAC Hash Table Register 0, offset: 0x10 */ + __IO uint32_t MAC_HASH_TABLE_REG1; /**< MAC Hash Table Register 1, offset: 0x14 */ + uint8_t RESERVED_0[56]; + __IO uint32_t MAC_VLAN_TAG_CTRL; /**< MAC VLAN Tag Control, offset: 0x50 */ + __IO uint32_t MAC_VLAN_TAG_DATA; /**< MAC VLAN Tag Data, offset: 0x54 */ + __IO uint32_t MAC_VLAN_HASH_TABLE; /**< MAC VLAN Hash Table, offset: 0x58 */ + uint8_t RESERVED_1[4]; + __IO uint32_t MAC_VLAN_INCL; /**< VLAN Tag Inclusion or Replacement, offset: 0x60 */ + __IO uint32_t MAC_INNER_VLAN_INCL; /**< MAC Inner VLAN Tag Inclusion or Replacement, offset: 0x64 */ + uint8_t RESERVED_2[8]; + __IO uint32_t MAC_TX_FLOW_CTRL_Q[5]; /**< MAC Q0 Tx Flow Control..MAC Q4 Tx Flow Control, array offset: 0x70, array step: 0x4 */ + uint8_t RESERVED_3[12]; + __IO uint32_t MAC_RX_FLOW_CTRL; /**< MAC Rx Flow Control, offset: 0x90 */ + __IO uint32_t MAC_RXQ_CTRL4; /**< Receive Queue Control 4, offset: 0x94 */ + __IO uint32_t MAC_TXQ_PRTY_MAP0; /**< Transmit Queue Priority Mapping 0, offset: 0x98 */ + __IO uint32_t MAC_TXQ_PRTY_MAP1; /**< Transmit Queue Priority Mapping 1, offset: 0x9C */ + __IO uint32_t MAC_RXQ_CTRL[4]; /**< Receive Queue Control 0..Receive Queue Control 3, array offset: 0xA0, array step: 0x4 */ + __I uint32_t MAC_INTERRUPT_STATUS; /**< Interrupt Status, offset: 0xB0 */ + __IO uint32_t MAC_INTERRUPT_ENABLE; /**< Interrupt Enable, offset: 0xB4 */ + __I uint32_t MAC_RX_TX_STATUS; /**< Receive Transmit Status, offset: 0xB8 */ + uint8_t RESERVED_4[4]; + __IO uint32_t MAC_PMT_CONTROL_STATUS; /**< PMT Control and Status, offset: 0xC0 */ + __IO uint32_t MAC_RWK_PACKET_FILTER; /**< Remote Wakeup Filter, offset: 0xC4 */ + uint8_t RESERVED_5[8]; + __IO uint32_t MAC_LPI_CONTROL_STATUS; /**< LPI Control and Status, offset: 0xD0 */ + __IO uint32_t MAC_LPI_TIMERS_CONTROL; /**< LPI Timers Control, offset: 0xD4 */ + __IO uint32_t MAC_LPI_ENTRY_TIMER; /**< Tx LPI Entry Timer Control, offset: 0xD8 */ + __IO uint32_t MAC_ONEUS_TIC_COUNTER; /**< One-microsecond Reference Timer, offset: 0xDC */ + uint8_t RESERVED_6[24]; + __IO uint32_t MAC_PHYIF_CONTROL_STATUS; /**< PHY Interface Control and Status, offset: 0xF8 */ + uint8_t RESERVED_7[20]; + __I uint32_t MAC_VERSION; /**< MAC Version, offset: 0x110 */ + __I uint32_t MAC_DEBUG; /**< MAC Debug, offset: 0x114 */ + uint8_t RESERVED_8[4]; + __I uint32_t MAC_HW_FEAT[4]; /**< Optional Features or Functions 0..Optional Features or Functions 3, array offset: 0x11C, array step: 0x4 */ + uint8_t RESERVED_9[212]; + __IO uint32_t MAC_MDIO_ADDRESS; /**< MDIO Address, offset: 0x200 */ + __IO uint32_t MAC_MDIO_DATA; /**< MAC MDIO Data, offset: 0x204 */ + uint8_t RESERVED_10[40]; + __IO uint32_t MAC_CSR_SW_CTRL; /**< CSR Software Control, offset: 0x230 */ + __IO uint32_t MAC_FPE_CTRL_STS; /**< Frame Preemption Control, offset: 0x234 */ + uint8_t RESERVED_11[8]; + __I uint32_t MAC_PRESN_TIME_NS; /**< 32-bit Binary Rollover Equivalent Time, offset: 0x240 */ + __IO uint32_t MAC_PRESN_TIME_UPDT; /**< MAC 1722 Presentation Time, offset: 0x244 */ + uint8_t RESERVED_12[184]; + struct { /* offset: 0x300, array step: 0x8 */ + __IO uint32_t HIGH; /**< MAC Address0 High..MAC Address63 High, array offset: 0x300, array step: 0x8 */ + __IO uint32_t LOW; /**< MAC Address0 Low..MAC Address63 Low, array offset: 0x304, array step: 0x8 */ + } MAC_ADDRESS[64]; + uint8_t RESERVED_13[512]; + __IO uint32_t MAC_MMC_CONTROL; /**< MMC Control, offset: 0x700 */ + __I uint32_t MAC_MMC_RX_INTERRUPT; /**< MMC Rx Interrupt, offset: 0x704 */ + __I uint32_t MAC_MMC_TX_INTERRUPT; /**< MMC Tx Interrupt, offset: 0x708 */ + __IO uint32_t MAC_MMC_RX_INTERRUPT_MASK; /**< MMC Rx Interrupt Mask, offset: 0x70C */ + __IO uint32_t MAC_MMC_TX_INTERRUPT_MASK; /**< MMC Tx Interrupt Mask, offset: 0x710 */ + __I uint32_t MAC_TX_OCTET_COUNT_GOOD_BAD; /**< Tx Octet Count Good and Bad, offset: 0x714 */ + __I uint32_t MAC_TX_PACKET_COUNT_GOOD_BAD; /**< Tx Packet Count Good and Bad, offset: 0x718 */ + __I uint32_t MAC_TX_BROADCAST_PACKETS_GOOD; /**< Tx Broadcast Packets Good, offset: 0x71C */ + __I uint32_t MAC_TX_MULTICAST_PACKETS_GOOD; /**< Tx Multicast Packets Good, offset: 0x720 */ + __I uint32_t MAC_TX_64OCTETS_PACKETS_GOOD_BAD; /**< Tx Good and Bad 64-Byte Packets, offset: 0x724 */ + __I uint32_t MAC_TX_65TO127OCTETS_PACKETS_GOOD_BAD; /**< Tx Good and Bad 65 to 127-Byte Packets, offset: 0x728 */ + __I uint32_t MAC_TX_128TO255OCTETS_PACKETS_GOOD_BAD; /**< Tx Good and Bad 128 to 255-Byte Packets, offset: 0x72C */ + __I uint32_t MAC_TX_256TO511OCTETS_PACKETS_GOOD_BAD; /**< Tx Good and Bad 256 to 511-Byte Packets, offset: 0x730 */ + __I uint32_t MAC_TX_512TO1023OCTETS_PACKETS_GOOD_BAD; /**< Tx Good and Bad 512 to 1023-Byte Packets, offset: 0x734 */ + __I uint32_t MAC_TX_1024TOMAXOCTETS_PACKETS_GOOD_BAD; /**< Tx Good and Bad 1024 to Max-Byte Packets, offset: 0x738 */ + __I uint32_t MAC_TX_UNICAST_PACKETS_GOOD_BAD; /**< Good and Bad Unicast Packets Transmitted, offset: 0x73C */ + __I uint32_t MAC_TX_MULTICAST_PACKETS_GOOD_BAD; /**< Good and Bad Multicast Packets Transmitted, offset: 0x740 */ + __I uint32_t MAC_TX_BROADCAST_PACKETS_GOOD_BAD; /**< Good and Bad Broadcast Packets Transmitted, offset: 0x744 */ + __I uint32_t MAC_TX_UNDERFLOW_ERROR_PACKETS; /**< Tx Packets Aborted By Underflow Error, offset: 0x748 */ + __I uint32_t MAC_TX_SINGLE_COLLISION_GOOD_PACKETS; /**< Single Collision Good Packets Transmitted, offset: 0x74C */ + __I uint32_t MAC_TX_MULTIPLE_COLLISION_GOOD_PACKETS; /**< Multiple Collision Good Packets Transmitted, offset: 0x750 */ + __I uint32_t MAC_TX_DEFERRED_PACKETS; /**< Deferred Packets Transmitted, offset: 0x754 */ + __I uint32_t MAC_TX_LATE_COLLISION_PACKETS; /**< Late Collision Packets Transmitted, offset: 0x758 */ + __I uint32_t MAC_TX_EXCESSIVE_COLLISION_PACKETS; /**< Excessive Collision Packets Transmitted, offset: 0x75C */ + __I uint32_t MAC_TX_CARRIER_ERROR_PACKETS; /**< Carrier Error Packets Transmitted, offset: 0x760 */ + __I uint32_t MAC_TX_OCTET_COUNT_GOOD; /**< Bytes Transmitted in Good Packets, offset: 0x764 */ + __I uint32_t MAC_TX_PACKET_COUNT_GOOD; /**< Good Packets Transmitted, offset: 0x768 */ + __I uint32_t MAC_TX_EXCESSIVE_DEFERRAL_ERROR; /**< Packets Aborted By Excessive Deferral Error, offset: 0x76C */ + __I uint32_t MAC_TX_PAUSE_PACKETS; /**< Pause Packets Transmitted, offset: 0x770 */ + __I uint32_t MAC_TX_VLAN_PACKETS_GOOD; /**< Good VLAN Packets Transmitted, offset: 0x774 */ + __I uint32_t MAC_TX_OSIZE_PACKETS_GOOD; /**< Good Oversize Packets Transmitted, offset: 0x778 */ + uint8_t RESERVED_14[4]; + __I uint32_t MAC_RX_PACKETS_COUNT_GOOD_BAD; /**< Good and Bad Packets Received, offset: 0x780 */ + __I uint32_t MAC_RX_OCTET_COUNT_GOOD_BAD; /**< Bytes in Good and Bad Packets Received, offset: 0x784 */ + __I uint32_t MAC_RX_OCTET_COUNT_GOOD; /**< Bytes in Good Packets Received, offset: 0x788 */ + __I uint32_t MAC_RX_BROADCAST_PACKETS_GOOD; /**< Good Broadcast Packets Received, offset: 0x78C */ + __I uint32_t MAC_RX_MULTICAST_PACKETS_GOOD; /**< Good Multicast Packets Received, offset: 0x790 */ + __I uint32_t MAC_RX_CRC_ERROR_PACKETS; /**< CRC Error Packets Received, offset: 0x794 */ + __I uint32_t MAC_RX_ALIGNMENT_ERROR_PACKETS; /**< Alignment Error Packets Received, offset: 0x798 */ + __I uint32_t MAC_RX_RUNT_ERROR_PACKETS; /**< Runt Error Packets Received, offset: 0x79C */ + __I uint32_t MAC_RX_JABBER_ERROR_PACKETS; /**< Jabber Error Packets Received, offset: 0x7A0 */ + __I uint32_t MAC_RX_UNDERSIZE_PACKETS_GOOD; /**< Good Undersize Packets Received, offset: 0x7A4 */ + __I uint32_t MAC_RX_OVERSIZE_PACKETS_GOOD; /**< Good Oversize Packets Received, offset: 0x7A8 */ + __I uint32_t MAC_RX_64OCTETS_PACKETS_GOOD_BAD; /**< Good and Bad 64-Byte Packets Received, offset: 0x7AC */ + __I uint32_t MAC_RX_65TO127OCTETS_PACKETS_GOOD_BAD; /**< Good and Bad 64-to-127 Byte Packets Received, offset: 0x7B0 */ + __I uint32_t MAC_RX_128TO255OCTETS_PACKETS_GOOD_BAD; /**< Good and Bad 128-to-255 Byte Packets Received, offset: 0x7B4 */ + __I uint32_t MAC_RX_256TO511OCTETS_PACKETS_GOOD_BAD; /**< Good and Bad 256-to-511 Byte Packets Received, offset: 0x7B8 */ + __I uint32_t MAC_RX_512TO1023OCTETS_PACKETS_GOOD_BAD; /**< Good and Bad 512-to-1023 Byte Packets Received, offset: 0x7BC */ + __I uint32_t MAC_RX_1024TOMAXOCTETS_PACKETS_GOOD_BAD; /**< Good and Bad 1024-to-Max Byte Packets Received, offset: 0x7C0 */ + __I uint32_t MAC_RX_UNICAST_PACKETS_GOOD; /**< Good Unicast Packets Received, offset: 0x7C4 */ + __I uint32_t MAC_RX_LENGTH_ERROR_PACKETS; /**< Length Error Packets Received, offset: 0x7C8 */ + __I uint32_t MAC_RX_OUT_OF_RANGE_TYPE_PACKETS; /**< Out-of-range Type Packets Received, offset: 0x7CC */ + __I uint32_t MAC_RX_PAUSE_PACKETS; /**< Pause Packets Received, offset: 0x7D0 */ + __I uint32_t MAC_RX_FIFO_OVERFLOW_PACKETS; /**< Missed Packets Due to FIFO Overflow, offset: 0x7D4 */ + __I uint32_t MAC_RX_VLAN_PACKETS_GOOD_BAD; /**< Good and Bad VLAN Packets Received, offset: 0x7D8 */ + __I uint32_t MAC_RX_WATCHDOG_ERROR_PACKETS; /**< Watchdog Error Packets Received, offset: 0x7DC */ + __I uint32_t MAC_RX_RECEIVE_ERROR_PACKETS; /**< Receive Error Packets Received, offset: 0x7E0 */ + __I uint32_t MAC_RX_CONTROL_PACKETS_GOOD; /**< Good Control Packets Received, offset: 0x7E4 */ + uint8_t RESERVED_15[4]; + __I uint32_t MAC_TX_LPI_USEC_CNTR; /**< Microseconds Tx LPI Asserted, offset: 0x7EC */ + __I uint32_t MAC_TX_LPI_TRAN_CNTR; /**< Number of Times Tx LPI Asserted, offset: 0x7F0 */ + __I uint32_t MAC_RX_LPI_USEC_CNTR; /**< Microseconds Rx LPI Sampled, offset: 0x7F4 */ + __I uint32_t MAC_RX_LPI_TRAN_CNTR; /**< Number of Times Rx LPI Entered, offset: 0x7F8 */ + uint8_t RESERVED_16[4]; + __IO uint32_t MAC_MMC_IPC_RX_INTERRUPT_MASK; /**< MMC IPC Receive Interrupt Mask, offset: 0x800 */ + uint8_t RESERVED_17[4]; + __I uint32_t MAC_MMC_IPC_RX_INTERRUPT; /**< MMC IPC Receive Interrupt, offset: 0x808 */ + uint8_t RESERVED_18[4]; + __I uint32_t MAC_RXIPV4_GOOD_PACKETS; /**< Good IPv4 Datagrams Received, offset: 0x810 */ + __I uint32_t MAC_RXIPV4_HEADER_ERROR_PACKETS; /**< IPv4 Datagrams Received with Header Errors, offset: 0x814 */ + __I uint32_t MAC_RXIPV4_NO_PAYLOAD_PACKETS; /**< IPv4 Datagrams Received with No Payload, offset: 0x818 */ + __I uint32_t MAC_RXIPV4_FRAGMENTED_PACKETS; /**< IPv4 Datagrams Received with Fragmentation, offset: 0x81C */ + __I uint32_t MAC_RXIPV4_UDP_CHECKSUM_DISABLED_PACKETS; /**< IPv4 Datagrams Received with UDP Checksum Disabled, offset: 0x820 */ + __I uint32_t MAC_RXIPV6_GOOD_PACKETS; /**< Good IPv6 Datagrams Received, offset: 0x824 */ + __I uint32_t MAC_RXIPV6_HEADER_ERROR_PACKETS; /**< IPv6 Datagrams Received with Header Errors, offset: 0x828 */ + __I uint32_t MAC_RXIPV6_NO_PAYLOAD_PACKETS; /**< IPv6 Datagrams Received with No Payload, offset: 0x82C */ + __I uint32_t MAC_RXUDP_GOOD_PACKETS; /**< IPv6 Datagrams Received with Good UDP, offset: 0x830 */ + __I uint32_t MAC_RXUDP_ERROR_PACKETS; /**< IPv6 Datagrams Received with UDP Checksum Error, offset: 0x834 */ + __I uint32_t MAC_RXTCP_GOOD_PACKETS; /**< IPv6 Datagrams Received with Good TCP Payload, offset: 0x838 */ + __I uint32_t MAC_RXTCP_ERROR_PACKETS; /**< IPv6 Datagrams Received with TCP Checksum Error, offset: 0x83C */ + __I uint32_t MAC_RXICMP_GOOD_PACKETS; /**< IPv6 Datagrams Received with Good ICMP Payload, offset: 0x840 */ + __I uint32_t MAC_RXICMP_ERROR_PACKETS; /**< IPv6 Datagrams Received with ICMP Checksum Error, offset: 0x844 */ + uint8_t RESERVED_19[8]; + __I uint32_t MAC_RXIPV4_GOOD_OCTETS; /**< Good Bytes Received in IPv4 Datagrams, offset: 0x850 */ + __I uint32_t MAC_RXIPV4_HEADER_ERROR_OCTETS; /**< Bytes Received in IPv4 Datagrams with Header Errors, offset: 0x854 */ + __I uint32_t MAC_RXIPV4_NO_PAYLOAD_OCTETS; /**< Bytes Received in IPv4 Datagrams with No Payload, offset: 0x858 */ + __I uint32_t MAC_RXIPV4_FRAGMENTED_OCTETS; /**< Bytes Received in Fragmented IPv4 Datagrams, offset: 0x85C */ + __I uint32_t MAC_RXIPV4_UDP_CHECKSUM_DISABLE_OCTETS; /**< Bytes Received with UDP Checksum Disabled, offset: 0x860 */ + __I uint32_t MAC_RXIPV6_GOOD_OCTETS; /**< Bytes Received in Good IPv6 Datagrams, offset: 0x864 */ + __I uint32_t MAC_RXIPV6_HEADER_ERROR_OCTETS; /**< Bytes Received in IPv6 Datagrams with Data Errors, offset: 0x868 */ + __I uint32_t MAC_RXIPV6_NO_PAYLOAD_OCTETS; /**< Bytes Received in IPv6 Datagrams with No Payload, offset: 0x86C */ + __I uint32_t MAC_RXUDP_GOOD_OCTETS; /**< Bytes Received in Good UDP Segment, offset: 0x870 */ + __I uint32_t MAC_RXUDP_ERROR_OCTETS; /**< Bytes Received in UDP Segment with Checksum Errors, offset: 0x874 */ + __I uint32_t MAC_RXTCP_GOOD_OCTETS; /**< Bytes Received in Good TCP Segment, offset: 0x878 */ + __I uint32_t MAC_RXTCP_ERROR_OCTETS; /**< Bytes Received in TCP Segment with Checksum Errors, offset: 0x87C */ + __I uint32_t MAC_RXICMP_GOOD_OCTETS; /**< Bytes Received in Good ICMP Segment, offset: 0x880 */ + __I uint32_t MAC_RXICMP_ERROR_OCTETS; /**< Bytes Received in ICMP Segment with Checksum Errors, offset: 0x884 */ + uint8_t RESERVED_20[24]; + __I uint32_t MAC_MMC_FPE_TX_INTERRUPT; /**< MMC FPE Transmit Interrupt, offset: 0x8A0 */ + __IO uint32_t MAC_MMC_FPE_TX_INTERRUPT_MASK; /**< MMC FPE Transmit Mask Interrupt, offset: 0x8A4 */ + __I uint32_t MAC_MMC_TX_FPE_FRAGMENT_CNTR; /**< MMC FPE Transmitted Fragment Counter, offset: 0x8A8 */ + __I uint32_t MAC_MMC_TX_HOLD_REQ_CNTR; /**< MMC FPE Transmitted Hold Request Counter, offset: 0x8AC */ + uint8_t RESERVED_21[16]; + __I uint32_t MAC_MMC_FPE_RX_INTERRUPT; /**< MMC FPE Receive Interrupt, offset: 0x8C0 */ + __IO uint32_t MAC_MMC_FPE_RX_INTERRUPT_MASK; /**< MMC FPE Receive Interrupt Mask, offset: 0x8C4 */ + __I uint32_t MAC_MMC_RX_PACKET_ASSEMBLY_ERR_CNTR; /**< MMC Receive Packet Reassembly Error Counter, offset: 0x8C8 */ + __I uint32_t MAC_MMC_RX_PACKET_SMD_ERR_CNTR; /**< MMC Receive Packet SMD Error Counter, offset: 0x8CC */ + __I uint32_t MAC_MMC_RX_PACKET_ASSEMBLY_OK_CNTR; /**< MMC Receive Packet Successful Reassembly Counter, offset: 0x8D0 */ + __I uint32_t MAC_MMC_RX_FPE_FRAGMENT_CNTR; /**< MMC FPE Received Fragment Counter, offset: 0x8D4 */ + uint8_t RESERVED_22[40]; + __IO uint32_t MAC_L3_L4_CONTROL0; /**< Layer 3 and Layer 4 Control of Filter 0, offset: 0x900 */ + __IO uint32_t MAC_LAYER4_ADDRESS0; /**< Layer 4 Address 0, offset: 0x904 */ + uint8_t RESERVED_23[8]; + __IO uint32_t MAC_LAYER3_ADDR0_REG0; /**< Layer 3 Address 0 Register 0, offset: 0x910 */ + __IO uint32_t MAC_LAYER3_ADDR1_REG0; /**< Layer 3 Address 1 Register 0, offset: 0x914 */ + __IO uint32_t MAC_LAYER3_ADDR2_REG0; /**< Layer 3 Address 2 Register 0, offset: 0x918 */ + __IO uint32_t MAC_LAYER3_ADDR3_REG0; /**< Layer 3 Address 3 Register 0, offset: 0x91C */ + uint8_t RESERVED_24[16]; + __IO uint32_t MAC_L3_L4_CONTROL1; /**< Layer 3 and Layer 4 Control of Filter 1, offset: 0x930 */ + __IO uint32_t MAC_LAYER4_ADDRESS1; /**< Layer 4 Address 0, offset: 0x934 */ + uint8_t RESERVED_25[8]; + __IO uint32_t MAC_LAYER3_ADDR0_REG1; /**< Layer 3 Address 0 Register 1, offset: 0x940 */ + __IO uint32_t MAC_LAYER3_ADDR1_REG1; /**< Layer 3 Address 1 Register 1, offset: 0x944 */ + __IO uint32_t MAC_LAYER3_ADDR2_REG1; /**< Layer 3 Address 2 Register 1, offset: 0x948 */ + __IO uint32_t MAC_LAYER3_ADDR3_REG1; /**< Layer 3 Address 3 Register 1, offset: 0x94C */ + uint8_t RESERVED_26[16]; + __IO uint32_t MAC_L3_L4_CONTROL2; /**< Layer 3 and Layer 4 Control of Filter 2, offset: 0x960 */ + __IO uint32_t MAC_LAYER4_ADDRESS2; /**< Layer 4 Address 2, offset: 0x964 */ + uint8_t RESERVED_27[8]; + __IO uint32_t MAC_LAYER3_ADDR0_REG2; /**< Layer 3 Address 0 Register 2, offset: 0x970 */ + __IO uint32_t MAC_LAYER3_ADDR1_REG2; /**< Layer 3 Address 0 Register 2, offset: 0x974 */ + __IO uint32_t MAC_LAYER3_ADDR2_REG2; /**< Layer 3 Address 2 Register 2, offset: 0x978 */ + __IO uint32_t MAC_LAYER3_ADDR3_REG2; /**< Layer 3 Address 3 Register 2, offset: 0x97C */ + uint8_t RESERVED_28[16]; + __IO uint32_t MAC_L3_L4_CONTROL3; /**< Layer 3 and Layer 4 Control of Filter 3, offset: 0x990 */ + __IO uint32_t MAC_LAYER4_ADDRESS3; /**< Layer 4 Address 3, offset: 0x994 */ + uint8_t RESERVED_29[8]; + __IO uint32_t MAC_LAYER3_ADDR0_REG3; /**< Layer 3 Address 0 Register 3, offset: 0x9A0 */ + __IO uint32_t MAC_LAYER3_ADDR1_REG3; /**< Layer 3 Address 1 Register 3, offset: 0x9A4 */ + __IO uint32_t MAC_LAYER3_ADDR2_REG3; /**< Layer 3 Address 2 Register 3, offset: 0x9A8 */ + __IO uint32_t MAC_LAYER3_ADDR3_REG3; /**< Layer 3 Address 3 Register 3, offset: 0x9AC */ + uint8_t RESERVED_30[16]; + __IO uint32_t MAC_L3_L4_CONTROL4; /**< Layer 3 and Layer 4 Control of Filter 4, offset: 0x9C0 */ + __IO uint32_t MAC_LAYER4_ADDRESS4; /**< Layer 4 Address 4, offset: 0x9C4 */ + uint8_t RESERVED_31[8]; + __IO uint32_t MAC_LAYER3_ADDR0_REG4; /**< Layer 3 Address 0 Register 4, offset: 0x9D0 */ + __IO uint32_t MAC_LAYER3_ADDR1_REG4; /**< Layer 3 Address 1 Register 4, offset: 0x9D4 */ + __IO uint32_t MAC_LAYER3_ADDR2_REG4; /**< Layer 3 Address 2 Register 4, offset: 0x9D8 */ + __IO uint32_t MAC_LAYER3_ADDR3_REG4; /**< Layer 3 Address 3 Register 4, offset: 0x9DC */ + uint8_t RESERVED_32[16]; + __IO uint32_t MAC_L3_L4_CONTROL5; /**< Layer 3 and Layer 4 Control of Filter 5, offset: 0x9F0 */ + __IO uint32_t MAC_LAYER4_ADDRESS5; /**< Layer 4 Address 5, offset: 0x9F4 */ + uint8_t RESERVED_33[8]; + __IO uint32_t MAC_LAYER3_ADDR0_REG5; /**< Layer 3 Address 0 Register 5, offset: 0xA00 */ + __IO uint32_t MAC_LAYER3_ADDR1_REG5; /**< Layer 3 Address 1 Register 5, offset: 0xA04 */ + __IO uint32_t MAC_LAYER3_ADDR2_REG5; /**< Layer 3 Address 2 Register 5, offset: 0xA08 */ + __IO uint32_t MAC_LAYER3_ADDR3_REG5; /**< Layer 3 Address 3 Register 5, offset: 0xA0C */ + uint8_t RESERVED_34[16]; + __IO uint32_t MAC_L3_L4_CONTROL6; /**< Layer 3 and Layer 4 Control of Filter 6, offset: 0xA20 */ + __IO uint32_t MAC_LAYER4_ADDRESS6; /**< Layer 4 Address 6, offset: 0xA24 */ + uint8_t RESERVED_35[8]; + __IO uint32_t MAC_LAYER3_ADDR0_REG6; /**< Layer 3 Address 0 Register 6, offset: 0xA30 */ + __IO uint32_t MAC_LAYER3_ADDR1_REG6; /**< Layer 3 Address 1 Register 6, offset: 0xA34 */ + __IO uint32_t MAC_LAYER3_ADDR2_REG6; /**< Layer 3 Address 2 Register 6, offset: 0xA38 */ + __IO uint32_t MAC_LAYER3_ADDR3_REG6; /**< Layer 3 Address 3 Register 6, offset: 0xA3C */ + uint8_t RESERVED_36[16]; + __IO uint32_t MAC_L3_L4_CONTROL7; /**< Layer 3 and Layer 4 Control of Filter 0, offset: 0xA50 */ + __IO uint32_t MAC_LAYER4_ADDRESS7; /**< Layer 4 Address 7, offset: 0xA54 */ + uint8_t RESERVED_37[8]; + __IO uint32_t MAC_LAYER3_ADDR0_REG7; /**< Layer 3 Address 0 Register 7, offset: 0xA60 */ + __IO uint32_t MAC_LAYER3_ADDR1_REG7; /**< Layer 3 Address 1 Register 7, offset: 0xA64 */ + __IO uint32_t MAC_LAYER3_ADDR2_REG7; /**< Layer 3 Address 2 Register 7, offset: 0xA68 */ + __IO uint32_t MAC_LAYER3_ADDR3_REG7; /**< Layer 3 Address 3 Register 7, offset: 0xA6C */ + __IO uint32_t MAC_INDIR_ACCESS_CTRL; /**< MAC_INDIR_ACCESS_CTRL, offset: 0xA70 */ + __IO uint32_t MAC_INDIR_ACCESS_DATA; /**< MAC_INDIR_ACCESS_DATA, offset: 0xA74 */ + uint8_t RESERVED_38[136]; + __IO uint32_t MAC_TIMESTAMP_CONTROL; /**< Timestamp Control, offset: 0xB00 */ + __IO uint32_t MAC_SUB_SECOND_INCREMENT; /**< Subsecond Increment, offset: 0xB04 */ + __I uint32_t MAC_SYSTEM_TIME_SECONDS; /**< System Time Seconds, offset: 0xB08 */ + __I uint32_t MAC_SYSTEM_TIME_NANOSECONDS; /**< System Time Nanoseconds, offset: 0xB0C */ + __IO uint32_t MAC_SYSTEM_TIME_SECONDS_UPDATE; /**< System Time Seconds Update, offset: 0xB10 */ + __IO uint32_t MAC_SYSTEM_TIME_NANOSECONDS_UPDATE; /**< System Time Nanoseconds Update, offset: 0xB14 */ + __IO uint32_t MAC_TIMESTAMP_ADDEND; /**< Timestamp Addend, offset: 0xB18 */ + __IO uint32_t MAC_SYSTEM_TIME_HIGHER_WORD_SECONDS; /**< System Time - Higher Word Seconds, offset: 0xB1C */ + __I uint32_t MAC_TIMESTAMP_STATUS; /**< Timestamp Status, offset: 0xB20 */ + uint8_t RESERVED_39[12]; + __I uint32_t MAC_TX_TIMESTAMP_STATUS_NANOSECONDS; /**< Transmit Timestamp Status Nanoseconds, offset: 0xB30 */ + __I uint32_t MAC_TX_TIMESTAMP_STATUS_SECONDS; /**< Transmit Timestamp Status Seconds, offset: 0xB34 */ + uint8_t RESERVED_40[8]; + __IO uint32_t MAC_AUXILIARY_CONTROL; /**< Auxiliary Timestamp Control, offset: 0xB40 */ + uint8_t RESERVED_41[4]; + __I uint32_t MAC_AUXILIARY_TIMESTAMP_NANOSECONDS; /**< Auxiliary Timestamp Nanoseconds, offset: 0xB48 */ + __I uint32_t MAC_AUXILIARY_TIMESTAMP_SECONDS; /**< Auxiliary Timestamp Seconds, offset: 0xB4C */ + __IO uint32_t MAC_TIMESTAMP_INGRESS_ASYM_CORR; /**< Timestamp Ingress Asymmetry Correction, offset: 0xB50 */ + __IO uint32_t MAC_TIMESTAMP_EGRESS_ASYM_CORR; /**< Timestamp Egress Asymmetry Correction, offset: 0xB54 */ + __IO uint32_t MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND; /**< Timestamp Ingress Correction Nanosecond, offset: 0xB58 */ + __IO uint32_t MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND; /**< Timestamp Egress Correction Nanosecond, offset: 0xB5C */ + __IO uint32_t MAC_TIMESTAMP_INGRESS_CORR_SUBNANOSEC; /**< Timestamp Ingress Correction Subnanosecond, offset: 0xB60 */ + __IO uint32_t MAC_TIMESTAMP_EGRESS_CORR_SUBNANOSEC; /**< Timestamp Egress Correction Subnanosecond, offset: 0xB64 */ + __I uint32_t MAC_TIMESTAMP_INGRESS_LATENCY; /**< Timestamp Ingress Latency, offset: 0xB68 */ + __I uint32_t MAC_TIMESTAMP_EGRESS_LATENCY; /**< Timestamp Egress Latency, offset: 0xB6C */ + __IO uint32_t MAC_PPS_CONTROL; /**< PPS Control, offset: 0xB70 */ + uint8_t RESERVED_42[12]; + __IO uint32_t MAC_PPS0_TARGET_TIME_SECONDS; /**< PPS0 Target Time Seconds, offset: 0xB80 */ + __IO uint32_t MAC_PPS0_TARGET_TIME_NANOSECONDS; /**< PPS0 Target Time Nanoseconds, offset: 0xB84 */ + __IO uint32_t MAC_PPS0_INTERVAL; /**< PPS0 Interval, offset: 0xB88 */ + __IO uint32_t MAC_PPS0_WIDTH; /**< PPS0 Width, offset: 0xB8C */ + __IO uint32_t MAC_PPS1_TARGET_TIME_SECONDS; /**< PPS1 Target Time Seconds, offset: 0xB90 */ + __IO uint32_t MAC_PPS1_TARGET_TIME_NANOSECONDS; /**< PPS1 Target Time Nanoseconds, offset: 0xB94 */ + __IO uint32_t MAC_PPS1_INTERVAL; /**< PPS1 Interval, offset: 0xB98 */ + __IO uint32_t MAC_PPS1_WIDTH; /**< PPS1 Width, offset: 0xB9C */ + __IO uint32_t MAC_PPS2_TARGET_TIME_SECONDS; /**< PPS2 Target Time Seconds, offset: 0xBA0 */ + __IO uint32_t MAC_PPS2_TARGET_TIME_NANOSECONDS; /**< PPS2 Target Time Nanoseconds, offset: 0xBA4 */ + __IO uint32_t MAC_PPS2_INTERVAL; /**< PPS2 Interval, offset: 0xBA8 */ + __IO uint32_t MAC_PPS2_WIDTH; /**< PPS2 Width, offset: 0xBAC */ + __IO uint32_t MAC_PPS3_TARGET_TIME_SECONDS; /**< PPS3 Target Time Seconds, offset: 0xBB0 */ + __IO uint32_t MAC_PPS3_TARGET_TIME_NANOSECONDS; /**< PPS3 Target Time Nanoseconds, offset: 0xBB4 */ + __IO uint32_t MAC_PPS3_INTERVAL; /**< PPS3 Interval, offset: 0xBB8 */ + __IO uint32_t MAC_PPS3_WIDTH; /**< PPS3 Width, offset: 0xBBC */ + __IO uint32_t MAC_PTO_CONTROL; /**< PTP Offload Engine Control, offset: 0xBC0 */ + __IO uint32_t MAC_SOURCE_PORT_IDENTITY0; /**< Source Port Identity 0, offset: 0xBC4 */ + __IO uint32_t MAC_SOURCE_PORT_IDENTITY1; /**< Source Port Identity 1, offset: 0xBC8 */ + __IO uint32_t MAC_SOURCE_PORT_IDENTITY2; /**< Source Port Identity 2, offset: 0xBCC */ + __IO uint32_t MAC_LOG_MESSAGE_INTERVAL; /**< Log Message Interval, offset: 0xBD0 */ + uint8_t RESERVED_43[44]; + __IO uint32_t MTL_OPERATION_MODE; /**< MTL Operation Mode, offset: 0xC00 */ + uint8_t RESERVED_44[4]; + __IO uint32_t MTL_DBG_CTL; /**< FIFO Debug Access Control and Status, offset: 0xC08 */ + __IO uint32_t MTL_DBG_STS; /**< FIFO Debug Status, offset: 0xC0C */ + __IO uint32_t MTL_FIFO_DEBUG_DATA; /**< FIFO Debug Data, offset: 0xC10 */ + uint8_t RESERVED_45[12]; + __I uint32_t MTL_INTERRUPT_STATUS; /**< MTL Interrupt Status, offset: 0xC20 */ + uint8_t RESERVED_46[12]; + __IO uint32_t MTL_RXQ_DMA_MAP0; /**< Receive Queue and DMA Channel Mapping 0, offset: 0xC30 */ + __IO uint32_t MTL_RXQ_DMA_MAP1; /**< Receive Queue and DMA Channel Mapping 1, offset: 0xC34 */ + uint8_t RESERVED_47[8]; + __IO uint32_t MTL_TBS_CTRL; /**< Time Based Scheduling Control, offset: 0xC40 */ + uint8_t RESERVED_48[12]; + __IO uint32_t MTL_EST_CONTROL; /**< Enhancements to Scheduled Transmission Control, offset: 0xC50 */ + __IO uint32_t MTL_EST_EXT_CONTROL; /**< MTL_EST_EXT_CONTROL, offset: 0xC54 */ + __IO uint32_t MTL_EST_STATUS; /**< Enhancements to Scheduled Transmission Status, offset: 0xC58 */ + uint8_t RESERVED_49[4]; + __IO uint32_t MTL_EST_SCH_ERROR; /**< EST Scheduling Error, offset: 0xC60 */ + __IO uint32_t MTL_EST_FRM_SIZE_ERROR; /**< EST Frame Size Error, offset: 0xC64 */ + __I uint32_t MTL_EST_FRM_SIZE_CAPTURE; /**< EST Frame Size Capture, offset: 0xC68 */ + uint8_t RESERVED_50[4]; + __IO uint32_t MTL_EST_INTR_ENABLE; /**< EST Interrupt Enable, offset: 0xC70 */ + uint8_t RESERVED_51[12]; + __IO uint32_t MTL_EST_GCL_CONTROL; /**< EST GCL Control, offset: 0xC80 */ + __IO uint32_t MTL_EST_GCL_DATA; /**< EST GCL Data, offset: 0xC84 */ + uint8_t RESERVED_52[8]; + __IO uint32_t MTL_FPE_CTRL_STS; /**< Frame Preemption Control and Status, offset: 0xC90 */ + __IO uint32_t MTL_FPE_ADVANCE; /**< Frame Preemption Hold and Release Advance, offset: 0xC94 */ + uint8_t RESERVED_53[8]; + __IO uint32_t MTL_RXP_CONTROL_STATUS; /**< RXP Control Status, offset: 0xCA0 */ + __IO uint32_t MTL_RXP_INTERRUPT_CONTROL_STATUS; /**< RXP Interrupt Control Status, offset: 0xCA4 */ + __I uint32_t MTL_RXP_DROP_CNT; /**< RXP Drop Count, offset: 0xCA8 */ + __I uint32_t MTL_RXP_ERROR_CNT; /**< RXP Error Count, offset: 0xCAC */ + __IO uint32_t MTL_RXP_INDIRECT_ACC_CONTROL_STATUS; /**< RXP Indirect Access Control and Status, offset: 0xCB0 */ + __IO uint32_t MTL_RXP_INDIRECT_ACC_DATA; /**< RXP Indirect Access Data, offset: 0xCB4 */ + __I uint32_t MTL_RXP_BYPASS_CNT; /**< MTL_RXP_BYPASS_CNT, offset: 0xCB8 */ + uint8_t RESERVED_54[68]; + struct { /* offset: 0xD00, array step: 0x40 */ + __IO uint32_t MTL_TXQX_OP_MODE; /**< Queue 0 Transmit Operation Mode..Queue 4 Transmit Operation Mode, array offset: 0xD00, array step: 0x40 */ + __I uint32_t MTL_TXQX_UNDRFLW; /**< Queue 0 Underflow Counter..Queue 4 Underflow Counter, array offset: 0xD04, array step: 0x40 */ + __I uint32_t MTL_TXQX_DBG; /**< Queue 0 Transmit Debug..Queue 4 Transmit Debug, array offset: 0xD08, array step: 0x40 */ + uint8_t RESERVED_0[4]; + __IO uint32_t MTL_TXQX_ETS_CTRL; /**< Queue 1 ETS Control..Queue 4 ETS Control, array offset: 0xD10, array step: 0x40, valid indices: [1-4] */ + __I uint32_t MTL_TXQX_ETS_STAT; /**< Queue 0 ETS Status..Queue 4 ETS Status, array offset: 0xD14, array step: 0x40 */ + __IO uint32_t MTL_TXQX_QNTM_WGHT; /**< Queue 0 Quantum or Weights..Queue 4 idleSlopeCredit, Quantum or Weights, array offset: 0xD18, array step: 0x40 */ + __IO uint32_t MTL_TXQX_SNDSLP_CRDT; /**< Queue 1 sendSlopeCredit..Queue 4 sendSlopeCredit, array offset: 0xD1C, array step: 0x40, valid indices: [1-4] */ + __IO uint32_t MTL_TXQX_HI_CRDT; /**< Queue 1 hiCredit..Queue 4 hiCredit, array offset: 0xD20, array step: 0x40, valid indices: [1-4] */ + __IO uint32_t MTL_TXQX_LO_CRDT; /**< Queue 1 loCredit..Queue 4 loCredit, array offset: 0xD24, array step: 0x40, valid indices: [1-4] */ + uint8_t RESERVED_1[4]; + __IO uint32_t MTL_TXQX_INTCTRL_STAT; /**< Queue 0 Interrupt Control Status..Queue 4 Interrupt Control Status, array offset: 0xD2C, array step: 0x40 */ + __IO uint32_t MTL_RXQX_OP_MODE; /**< Queue 0 Receive Operation Mode..Queue 4 Receive Operation Mode, array offset: 0xD30, array step: 0x40 */ + __I uint32_t MTL_RXQX_MISSPKT_OVRFLW_CNT; /**< Queue 0 Missed Packet and Overflow Counter..Queue 4 Missed Packet and Overflow Counter, array offset: 0xD34, array step: 0x40 */ + __I uint32_t MTL_RXQX_DBG; /**< Queue 0 Receive Debug..Queue 4 Receive Debug, array offset: 0xD38, array step: 0x40 */ + __IO uint32_t MTL_RXQX_CTRL; /**< Queue 0 Receive Control..Queue 4 Receive Control, array offset: 0xD3C, array step: 0x40 */ + } MTL_QUEUE[5]; + uint8_t RESERVED_55[448]; + __IO uint32_t DMA_MODE; /**< DMA Bus Mode, offset: 0x1000 */ + __IO uint32_t DMA_SYSBUS_MODE; /**< DMA System Bus Mode, offset: 0x1004 */ + __I uint32_t DMA_INTERRUPT_STATUS; /**< DMA Interrupt Status, offset: 0x1008 */ + __I uint32_t DMA_DEBUG_STATUS0; /**< DMA Debug Status 0, offset: 0x100C */ + __I uint32_t DMA_DEBUG_STATUS1; /**< DMA Debug Status 1, offset: 0x1010 */ + uint8_t RESERVED_56[44]; + __IO uint32_t DMA_AXI_LPI_ENTRY_INTERVAL; /**< AXI LPI Entry Interval Control, offset: 0x1040 */ + uint8_t RESERVED_57[12]; + __IO uint32_t DMA_TBS_CTRL0; /**< DMA_TBS_CTRL0, offset: 0x1050 */ + __IO uint32_t DMA_TBS_CTRL1; /**< DMA_TBS_CTRL1, offset: 0x1054 */ + __IO uint32_t DMA_TBS_CTRL2; /**< DMA_TBS_CTRL2, offset: 0x1058 */ + __IO uint32_t DMA_TBS_CTRL3; /**< DMA_TBS_CTRL3, offset: 0x105C */ + uint8_t RESERVED_58[160]; + struct { /* offset: 0x1100, array step: 0x80 */ + __IO uint32_t DMA_CHX_CTRL; /**< DMA Channel 0 Control..Channel 4 Control, array offset: 0x1100, array step: 0x80 */ + __IO uint32_t DMA_CHX_TX_CTRL; /**< DMA Channel 0 Transmit Control..DMA Channel 4 Transmit Control, array offset: 0x1104, array step: 0x80 */ + __IO uint32_t DMA_CHX_RX_CTRL; /**< DMA Channel 0 Receive Control..DMA Channel 4 Receive Control, array offset: 0x1108, array step: 0x80 */ + uint8_t RESERVED_0[8]; + __IO uint32_t DMA_CHX_TXDESC_LIST_ADDR; /**< Channel 0 Tx Descriptor List Address register..Channel 4 Tx Descriptor List Address, array offset: 0x1114, array step: 0x80 */ + uint8_t RESERVED_1[4]; + __IO uint32_t DMA_CHX_RXDESC_LIST_ADDR; /**< Channel 0 Rx Descriptor List Address register..Channel 4 Rx Descriptor List Address, array offset: 0x111C, array step: 0x80 */ + __IO uint32_t DMA_CHX_TXDESC_TAIL_PTR; /**< Channel 0 Tx Descriptor Tail Pointer..Channel 4 Tx Descriptor Tail Pointer, array offset: 0x1120, array step: 0x80 */ + uint8_t RESERVED_2[4]; + __IO uint32_t DMA_CHX_RXDESC_TAIL_PTR; /**< Channel 0 Rx Descriptor Tail Pointer..Channel 4 Rx Descriptor Tail Pointer, array offset: 0x1128, array step: 0x80 */ + __IO uint32_t DMA_CHX_TXDESC_RING_LENGTH; /**< Channel 0 Tx Descriptor Ring Length..Channel 4 Tx Descriptor Ring Length, array offset: 0x112C, array step: 0x80 */ + __IO uint32_t DMA_CHX_RX_CONTROL2; /**< Channel 0 Receive Control 2 register..DMA Channel 4 Receive Control 2 register, array offset: 0x1130, array step: 0x80 */ + __IO uint32_t DMA_CHX_INT_EN; /**< Channel 0 Interrupt Enable..Channel 4 Interrupt Enable, array offset: 0x1134, array step: 0x80 */ + __IO uint32_t DMA_CHX_RX_INT_WDTIMER; /**< Channel 0 Receive Interrupt Watchdog Timer..Channel 4 Receive Interrupt Watchdog Timer, array offset: 0x1138, array step: 0x80 */ + __IO uint32_t DMA_CHX_SLOT_FUNC_CTRL_STAT; /**< Channel 0 Slot Function Control and Status..Channel 4 Slot Function Control and Status, array offset: 0x113C, array step: 0x80 */ + uint8_t RESERVED_3[4]; + __I uint32_t DMA_CHX_CUR_HST_TXDESC; /**< Channel 0 Current Application Transmit Descriptor..Channel 4 Current Application Transmit Descriptor, array offset: 0x1144, array step: 0x80 */ + uint8_t RESERVED_4[4]; + __I uint32_t DMA_CHX_CUR_HST_RXDESC; /**< Channel 0 Current Application Receive Descriptor..Channel 4 Current Application Receive Descriptor, array offset: 0x114C, array step: 0x80 */ + uint8_t RESERVED_5[4]; + __I uint32_t DMA_CHX_CUR_HST_TXBUF; /**< Channel 0 Current Application Transmit Buffer Address..Channel 4 Current Application Transmit Buffer Address, array offset: 0x1154, array step: 0x80 */ + uint8_t RESERVED_6[4]; + __I uint32_t DMA_CHX_CUR_HST_RXBUF; /**< Channel 0 Current Application Receive Buffer Address..Channel 4 Current Application Receive Buffer Address, array offset: 0x115C, array step: 0x80 */ + __IO uint32_t DMA_CHX_STAT; /**< DMA Channel 0 Status..DMA Channel 4 Status, array offset: 0x1160, array step: 0x80 */ + __I uint32_t DMA_CHX_MISS_FRAME_CNT; /**< Channel 0 Missed Frame Counter..Channel 4 Missed Frame Counter, array offset: 0x1164, array step: 0x80 */ + __I uint32_t DMA_CHX_RXP_ACCEPT_CNT; /**< Channel 0 RXP Frames Accepted Counter..Channel 4 RXP Frames Accepted Counter, array offset: 0x1168, array step: 0x80 */ + uint8_t RESERVED_7[20]; + } DMA_CH[5]; +} ENET_QOS_Type; + +/* ---------------------------------------------------------------------------- + -- ENET_QOS Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ENET_QOS_Register_Masks ENET_QOS Register Masks + * @{ + */ + +/*! @name MAC_CONFIGURATION - MAC Configuration Register */ +/*! @{ */ + +#define ENET_QOS_MAC_CONFIGURATION_RE_MASK (0x1U) +#define ENET_QOS_MAC_CONFIGURATION_RE_SHIFT (0U) +/*! RE - Receiver Enable + * 0b0..Receiver is disabled + * 0b1..Receiver is enabled + */ +#define ENET_QOS_MAC_CONFIGURATION_RE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_CONFIGURATION_RE_SHIFT)) & ENET_QOS_MAC_CONFIGURATION_RE_MASK) + +#define ENET_QOS_MAC_CONFIGURATION_TE_MASK (0x2U) +#define ENET_QOS_MAC_CONFIGURATION_TE_SHIFT (1U) +/*! TE - Transmitter Enable + * 0b0..Transmitter is disabled + * 0b1..Transmitter is enabled + */ +#define ENET_QOS_MAC_CONFIGURATION_TE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_CONFIGURATION_TE_SHIFT)) & ENET_QOS_MAC_CONFIGURATION_TE_MASK) + +#define ENET_QOS_MAC_CONFIGURATION_PRELEN_MASK (0xCU) +#define ENET_QOS_MAC_CONFIGURATION_PRELEN_SHIFT (2U) +/*! PRELEN - Preamble Length for Transmit packets + * 0b00..7 bytes of preamble + * 0b01..5 bytes of preamble + * 0b10..3 bytes of preamble + * 0b11..Reserved + */ +#define ENET_QOS_MAC_CONFIGURATION_PRELEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_CONFIGURATION_PRELEN_SHIFT)) & ENET_QOS_MAC_CONFIGURATION_PRELEN_MASK) + +#define ENET_QOS_MAC_CONFIGURATION_DC_MASK (0x10U) +#define ENET_QOS_MAC_CONFIGURATION_DC_SHIFT (4U) +/*! DC - Deferral Check + * 0b0..Deferral check function is disabled + * 0b1..Deferral check function is enabled + */ +#define ENET_QOS_MAC_CONFIGURATION_DC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_CONFIGURATION_DC_SHIFT)) & ENET_QOS_MAC_CONFIGURATION_DC_MASK) + +#define ENET_QOS_MAC_CONFIGURATION_BL_MASK (0x60U) +#define ENET_QOS_MAC_CONFIGURATION_BL_SHIFT (5U) +/*! BL - Back-Off Limit + * 0b00..k = min(n,10) + * 0b01..k = min(n,8) + * 0b10..k = min(n,4) + * 0b11..k = min(n,1) + */ +#define ENET_QOS_MAC_CONFIGURATION_BL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_CONFIGURATION_BL_SHIFT)) & ENET_QOS_MAC_CONFIGURATION_BL_MASK) + +#define ENET_QOS_MAC_CONFIGURATION_DR_MASK (0x100U) +#define ENET_QOS_MAC_CONFIGURATION_DR_SHIFT (8U) +/*! DR - Disable Retry + * 0b0..Enable Retry + * 0b1..Disable Retry + */ +#define ENET_QOS_MAC_CONFIGURATION_DR(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_CONFIGURATION_DR_SHIFT)) & ENET_QOS_MAC_CONFIGURATION_DR_MASK) + +#define ENET_QOS_MAC_CONFIGURATION_DCRS_MASK (0x200U) +#define ENET_QOS_MAC_CONFIGURATION_DCRS_SHIFT (9U) +/*! DCRS - Disable Carrier Sense During Transmission + * 0b0..Enable Carrier Sense During Transmission + * 0b1..Disable Carrier Sense During Transmission + */ +#define ENET_QOS_MAC_CONFIGURATION_DCRS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_CONFIGURATION_DCRS_SHIFT)) & ENET_QOS_MAC_CONFIGURATION_DCRS_MASK) + +#define ENET_QOS_MAC_CONFIGURATION_DO_MASK (0x400U) +#define ENET_QOS_MAC_CONFIGURATION_DO_SHIFT (10U) +/*! DO - Disable Receive Own + * 0b0..Enable Receive Own + * 0b1..Disable Receive Own + */ +#define ENET_QOS_MAC_CONFIGURATION_DO(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_CONFIGURATION_DO_SHIFT)) & ENET_QOS_MAC_CONFIGURATION_DO_MASK) + +#define ENET_QOS_MAC_CONFIGURATION_ECRSFD_MASK (0x800U) +#define ENET_QOS_MAC_CONFIGURATION_ECRSFD_SHIFT (11U) +/*! ECRSFD - Enable Carrier Sense Before Transmission in Full-Duplex Mode + * 0b0..ECRSFD is disabled + * 0b1..ECRSFD is enabled + */ +#define ENET_QOS_MAC_CONFIGURATION_ECRSFD(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_CONFIGURATION_ECRSFD_SHIFT)) & ENET_QOS_MAC_CONFIGURATION_ECRSFD_MASK) + +#define ENET_QOS_MAC_CONFIGURATION_LM_MASK (0x1000U) +#define ENET_QOS_MAC_CONFIGURATION_LM_SHIFT (12U) +/*! LM - Loopback Mode + * 0b0..Loopback is disabled + * 0b1..Loopback is enabled + */ +#define ENET_QOS_MAC_CONFIGURATION_LM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_CONFIGURATION_LM_SHIFT)) & ENET_QOS_MAC_CONFIGURATION_LM_MASK) + +#define ENET_QOS_MAC_CONFIGURATION_DM_MASK (0x2000U) +#define ENET_QOS_MAC_CONFIGURATION_DM_SHIFT (13U) +/*! DM - Duplex Mode + * 0b0..Half-duplex mode + * 0b1..Full-duplex mode + */ +#define ENET_QOS_MAC_CONFIGURATION_DM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_CONFIGURATION_DM_SHIFT)) & ENET_QOS_MAC_CONFIGURATION_DM_MASK) + +#define ENET_QOS_MAC_CONFIGURATION_FES_MASK (0x4000U) +#define ENET_QOS_MAC_CONFIGURATION_FES_SHIFT (14U) +/*! FES - Speed + * 0b0..10 Mbps when PS bit is 1 and 1 Gbps when PS bit is 0 + * 0b1..100 Mbps when PS bit is 1 and 2.5 Gbps when PS bit is 0 + */ +#define ENET_QOS_MAC_CONFIGURATION_FES(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_CONFIGURATION_FES_SHIFT)) & ENET_QOS_MAC_CONFIGURATION_FES_MASK) + +#define ENET_QOS_MAC_CONFIGURATION_PS_MASK (0x8000U) +#define ENET_QOS_MAC_CONFIGURATION_PS_SHIFT (15U) +/*! PS - Port Select + * 0b0..For 1000 or 2500 Mbps operations + * 0b1..For 10 or 100 Mbps operations + */ +#define ENET_QOS_MAC_CONFIGURATION_PS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_CONFIGURATION_PS_SHIFT)) & ENET_QOS_MAC_CONFIGURATION_PS_MASK) + +#define ENET_QOS_MAC_CONFIGURATION_JE_MASK (0x10000U) +#define ENET_QOS_MAC_CONFIGURATION_JE_SHIFT (16U) +/*! JE - Jumbo Packet Enable When this bit is set, the MAC allows jumbo packets of 9,018 bytes + * (9,022 bytes for VLAN tagged packets) without reporting a giant packet error in the Rx packet + * status. + * 0b0..Jumbo packet is disabled + * 0b1..Jumbo packet is enabled + */ +#define ENET_QOS_MAC_CONFIGURATION_JE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_CONFIGURATION_JE_SHIFT)) & ENET_QOS_MAC_CONFIGURATION_JE_MASK) + +#define ENET_QOS_MAC_CONFIGURATION_JD_MASK (0x20000U) +#define ENET_QOS_MAC_CONFIGURATION_JD_SHIFT (17U) +/*! JD - Jabber Disable + * 0b0..Jabber is enabled + * 0b1..Jabber is disabled + */ +#define ENET_QOS_MAC_CONFIGURATION_JD(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_CONFIGURATION_JD_SHIFT)) & ENET_QOS_MAC_CONFIGURATION_JD_MASK) + +#define ENET_QOS_MAC_CONFIGURATION_BE_MASK (0x40000U) +#define ENET_QOS_MAC_CONFIGURATION_BE_SHIFT (18U) +/*! BE - Packet Burst Enable When this bit is set, the MAC allows packet bursting during + * transmission in the GMII half-duplex mode. + * 0b0..Packet Burst is disabled + * 0b1..Packet Burst is enabled + */ +#define ENET_QOS_MAC_CONFIGURATION_BE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_CONFIGURATION_BE_SHIFT)) & ENET_QOS_MAC_CONFIGURATION_BE_MASK) + +#define ENET_QOS_MAC_CONFIGURATION_WD_MASK (0x80000U) +#define ENET_QOS_MAC_CONFIGURATION_WD_SHIFT (19U) +/*! WD - Watchdog Disable + * 0b0..Watchdog is enabled + * 0b1..Watchdog is disabled + */ +#define ENET_QOS_MAC_CONFIGURATION_WD(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_CONFIGURATION_WD_SHIFT)) & ENET_QOS_MAC_CONFIGURATION_WD_MASK) + +#define ENET_QOS_MAC_CONFIGURATION_ACS_MASK (0x100000U) +#define ENET_QOS_MAC_CONFIGURATION_ACS_SHIFT (20U) +/*! ACS - Automatic Pad or CRC Stripping When this bit is set, the MAC strips the Pad or FCS field + * on the incoming packets only if the value of the length field is less than 1,536 bytes. + * 0b0..Automatic Pad or CRC Stripping is disabled + * 0b1..Automatic Pad or CRC Stripping is enabled + */ +#define ENET_QOS_MAC_CONFIGURATION_ACS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_CONFIGURATION_ACS_SHIFT)) & ENET_QOS_MAC_CONFIGURATION_ACS_MASK) + +#define ENET_QOS_MAC_CONFIGURATION_CST_MASK (0x200000U) +#define ENET_QOS_MAC_CONFIGURATION_CST_SHIFT (21U) +/*! CST - CRC stripping for Type packets When this bit is set, the last four bytes (FCS) of all + * packets of Ether type (type field greater than 1,536) are stripped and dropped before forwarding + * the packet to the application. + * 0b0..CRC stripping for Type packets is disabled + * 0b1..CRC stripping for Type packets is enabled + */ +#define ENET_QOS_MAC_CONFIGURATION_CST(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_CONFIGURATION_CST_SHIFT)) & ENET_QOS_MAC_CONFIGURATION_CST_MASK) + +#define ENET_QOS_MAC_CONFIGURATION_S2KP_MASK (0x400000U) +#define ENET_QOS_MAC_CONFIGURATION_S2KP_SHIFT (22U) +/*! S2KP - IEEE 802. + * 0b0..Support upto 2K packet is disabled + * 0b1..Support upto 2K packet is Enabled + */ +#define ENET_QOS_MAC_CONFIGURATION_S2KP(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_CONFIGURATION_S2KP_SHIFT)) & ENET_QOS_MAC_CONFIGURATION_S2KP_MASK) + +#define ENET_QOS_MAC_CONFIGURATION_GPSLCE_MASK (0x800000U) +#define ENET_QOS_MAC_CONFIGURATION_GPSLCE_SHIFT (23U) +/*! GPSLCE - Giant Packet Size Limit Control Enable + * 0b0..Giant Packet Size Limit Control is disabled + * 0b1..Giant Packet Size Limit Control is enabled + */ +#define ENET_QOS_MAC_CONFIGURATION_GPSLCE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_CONFIGURATION_GPSLCE_SHIFT)) & ENET_QOS_MAC_CONFIGURATION_GPSLCE_MASK) + +#define ENET_QOS_MAC_CONFIGURATION_IPG_MASK (0x7000000U) +#define ENET_QOS_MAC_CONFIGURATION_IPG_SHIFT (24U) +/*! IPG - Inter-Packet Gap These bits control the minimum IPG between packets during transmission. + * 0b000..96 bit times IPG + * 0b001..88 bit times IPG + * 0b010..80 bit times IPG + * 0b011..72 bit times IPG + * 0b100..64 bit times IPG + * 0b101..56 bit times IPG + * 0b110..48 bit times IPG + * 0b111..40 bit times IPG + */ +#define ENET_QOS_MAC_CONFIGURATION_IPG(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_CONFIGURATION_IPG_SHIFT)) & ENET_QOS_MAC_CONFIGURATION_IPG_MASK) + +#define ENET_QOS_MAC_CONFIGURATION_IPC_MASK (0x8000000U) +#define ENET_QOS_MAC_CONFIGURATION_IPC_SHIFT (27U) +/*! IPC - Checksum Offload + * 0b0..IP header/payload checksum checking is disabled + * 0b1..IP header/payload checksum checking is enabled + */ +#define ENET_QOS_MAC_CONFIGURATION_IPC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_CONFIGURATION_IPC_SHIFT)) & ENET_QOS_MAC_CONFIGURATION_IPC_MASK) + +#define ENET_QOS_MAC_CONFIGURATION_SARC_MASK (0x70000000U) +#define ENET_QOS_MAC_CONFIGURATION_SARC_SHIFT (28U) +/*! SARC - Source Address Insertion or Replacement Control + * 0b000..mti_sa_ctrl_i and ati_sa_ctrl_i input signals control the SA field generation + * 0b010..Contents of MAC Addr-0 inserted in SA field + * 0b011..Contents of MAC Addr-0 replaces SA field + * 0b110..Contents of MAC Addr-1 inserted in SA field + * 0b111..Contents of MAC Addr-1 replaces SA field + */ +#define ENET_QOS_MAC_CONFIGURATION_SARC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_CONFIGURATION_SARC_SHIFT)) & ENET_QOS_MAC_CONFIGURATION_SARC_MASK) +/*! @} */ + +/*! @name MAC_EXT_CONFIGURATION - MAC Extended Configuration Register */ +/*! @{ */ + +#define ENET_QOS_MAC_EXT_CONFIGURATION_GPSL_MASK (0x3FFFU) +#define ENET_QOS_MAC_EXT_CONFIGURATION_GPSL_SHIFT (0U) +/*! GPSL - Giant Packet Size Limit */ +#define ENET_QOS_MAC_EXT_CONFIGURATION_GPSL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_EXT_CONFIGURATION_GPSL_SHIFT)) & ENET_QOS_MAC_EXT_CONFIGURATION_GPSL_MASK) + +#define ENET_QOS_MAC_EXT_CONFIGURATION_DCRCC_MASK (0x10000U) +#define ENET_QOS_MAC_EXT_CONFIGURATION_DCRCC_SHIFT (16U) +/*! DCRCC - Disable CRC Checking for Received Packets + * 0b0..CRC Checking is enabled + * 0b1..CRC Checking is disabled + */ +#define ENET_QOS_MAC_EXT_CONFIGURATION_DCRCC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_EXT_CONFIGURATION_DCRCC_SHIFT)) & ENET_QOS_MAC_EXT_CONFIGURATION_DCRCC_MASK) + +#define ENET_QOS_MAC_EXT_CONFIGURATION_SPEN_MASK (0x20000U) +#define ENET_QOS_MAC_EXT_CONFIGURATION_SPEN_SHIFT (17U) +/*! SPEN - Slow Protocol Detection Enable + * 0b0..Slow Protocol Detection is disabled + * 0b1..Slow Protocol Detection is enabled + */ +#define ENET_QOS_MAC_EXT_CONFIGURATION_SPEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_EXT_CONFIGURATION_SPEN_SHIFT)) & ENET_QOS_MAC_EXT_CONFIGURATION_SPEN_MASK) + +#define ENET_QOS_MAC_EXT_CONFIGURATION_USP_MASK (0x40000U) +#define ENET_QOS_MAC_EXT_CONFIGURATION_USP_SHIFT (18U) +/*! USP - Unicast Slow Protocol Packet Detect + * 0b0..Unicast Slow Protocol Packet Detection is disabled + * 0b1..Unicast Slow Protocol Packet Detection is enabled + */ +#define ENET_QOS_MAC_EXT_CONFIGURATION_USP(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_EXT_CONFIGURATION_USP_SHIFT)) & ENET_QOS_MAC_EXT_CONFIGURATION_USP_MASK) + +#define ENET_QOS_MAC_EXT_CONFIGURATION_PDC_MASK (0x80000U) +#define ENET_QOS_MAC_EXT_CONFIGURATION_PDC_SHIFT (19U) +/*! PDC - Packet Duplication Control + * 0b0..Packet Duplication Control is disabled + * 0b1..Packet Duplication Control is enabled + */ +#define ENET_QOS_MAC_EXT_CONFIGURATION_PDC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_EXT_CONFIGURATION_PDC_SHIFT)) & ENET_QOS_MAC_EXT_CONFIGURATION_PDC_MASK) + +#define ENET_QOS_MAC_EXT_CONFIGURATION_EIPGEN_MASK (0x1000000U) +#define ENET_QOS_MAC_EXT_CONFIGURATION_EIPGEN_SHIFT (24U) +/*! EIPGEN - Extended Inter-Packet Gap Enable + * 0b0..Extended Inter-Packet Gap is disabled + * 0b1..Extended Inter-Packet Gap is enabled + */ +#define ENET_QOS_MAC_EXT_CONFIGURATION_EIPGEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_EXT_CONFIGURATION_EIPGEN_SHIFT)) & ENET_QOS_MAC_EXT_CONFIGURATION_EIPGEN_MASK) + +#define ENET_QOS_MAC_EXT_CONFIGURATION_EIPG_MASK (0x3E000000U) +#define ENET_QOS_MAC_EXT_CONFIGURATION_EIPG_SHIFT (25U) +/*! EIPG - Extended Inter-Packet Gap */ +#define ENET_QOS_MAC_EXT_CONFIGURATION_EIPG(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_EXT_CONFIGURATION_EIPG_SHIFT)) & ENET_QOS_MAC_EXT_CONFIGURATION_EIPG_MASK) +/*! @} */ + +/*! @name MAC_PACKET_FILTER - MAC Packet Filter */ +/*! @{ */ + +#define ENET_QOS_MAC_PACKET_FILTER_PR_MASK (0x1U) +#define ENET_QOS_MAC_PACKET_FILTER_PR_SHIFT (0U) +/*! PR - Promiscuous Mode + * 0b0..Promiscuous Mode is disabled + * 0b1..Promiscuous Mode is enabled + */ +#define ENET_QOS_MAC_PACKET_FILTER_PR(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PACKET_FILTER_PR_SHIFT)) & ENET_QOS_MAC_PACKET_FILTER_PR_MASK) + +#define ENET_QOS_MAC_PACKET_FILTER_HUC_MASK (0x2U) +#define ENET_QOS_MAC_PACKET_FILTER_HUC_SHIFT (1U) +/*! HUC - Hash Unicast + * 0b0..Hash Unicast is disabled + * 0b1..Hash Unicast is enabled + */ +#define ENET_QOS_MAC_PACKET_FILTER_HUC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PACKET_FILTER_HUC_SHIFT)) & ENET_QOS_MAC_PACKET_FILTER_HUC_MASK) + +#define ENET_QOS_MAC_PACKET_FILTER_HMC_MASK (0x4U) +#define ENET_QOS_MAC_PACKET_FILTER_HMC_SHIFT (2U) +/*! HMC - Hash Multicast + * 0b0..Hash Multicast is disabled + * 0b1..Hash Multicast is enabled + */ +#define ENET_QOS_MAC_PACKET_FILTER_HMC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PACKET_FILTER_HMC_SHIFT)) & ENET_QOS_MAC_PACKET_FILTER_HMC_MASK) + +#define ENET_QOS_MAC_PACKET_FILTER_DAIF_MASK (0x8U) +#define ENET_QOS_MAC_PACKET_FILTER_DAIF_SHIFT (3U) +/*! DAIF - DA Inverse Filtering + * 0b0..DA Inverse Filtering is disabled + * 0b1..DA Inverse Filtering is enabled + */ +#define ENET_QOS_MAC_PACKET_FILTER_DAIF(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PACKET_FILTER_DAIF_SHIFT)) & ENET_QOS_MAC_PACKET_FILTER_DAIF_MASK) + +#define ENET_QOS_MAC_PACKET_FILTER_PM_MASK (0x10U) +#define ENET_QOS_MAC_PACKET_FILTER_PM_SHIFT (4U) +/*! PM - Pass All Multicast + * 0b0..Pass All Multicast is disabled + * 0b1..Pass All Multicast is enabled + */ +#define ENET_QOS_MAC_PACKET_FILTER_PM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PACKET_FILTER_PM_SHIFT)) & ENET_QOS_MAC_PACKET_FILTER_PM_MASK) + +#define ENET_QOS_MAC_PACKET_FILTER_DBF_MASK (0x20U) +#define ENET_QOS_MAC_PACKET_FILTER_DBF_SHIFT (5U) +/*! DBF - Disable Broadcast Packets + * 0b0..Enable Broadcast Packets + * 0b1..Disable Broadcast Packets + */ +#define ENET_QOS_MAC_PACKET_FILTER_DBF(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PACKET_FILTER_DBF_SHIFT)) & ENET_QOS_MAC_PACKET_FILTER_DBF_MASK) + +#define ENET_QOS_MAC_PACKET_FILTER_PCF_MASK (0xC0U) +#define ENET_QOS_MAC_PACKET_FILTER_PCF_SHIFT (6U) +/*! PCF - Pass Control Packets These bits control the forwarding of all control packets (including + * unicast and multicast Pause packets). + * 0b00..MAC filters all control packets from reaching the application + * 0b01..MAC forwards all control packets except Pause packets to the application even if they fail the Address filter + * 0b10..MAC forwards all control packets to the application even if they fail the Address filter + * 0b11..MAC forwards the control packets that pass the Address filter + */ +#define ENET_QOS_MAC_PACKET_FILTER_PCF(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PACKET_FILTER_PCF_SHIFT)) & ENET_QOS_MAC_PACKET_FILTER_PCF_MASK) + +#define ENET_QOS_MAC_PACKET_FILTER_SAIF_MASK (0x100U) +#define ENET_QOS_MAC_PACKET_FILTER_SAIF_SHIFT (8U) +/*! SAIF - SA Inverse Filtering + * 0b0..SA Inverse Filtering is disabled + * 0b1..SA Inverse Filtering is enabled + */ +#define ENET_QOS_MAC_PACKET_FILTER_SAIF(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PACKET_FILTER_SAIF_SHIFT)) & ENET_QOS_MAC_PACKET_FILTER_SAIF_MASK) + +#define ENET_QOS_MAC_PACKET_FILTER_SAF_MASK (0x200U) +#define ENET_QOS_MAC_PACKET_FILTER_SAF_SHIFT (9U) +/*! SAF - Source Address Filter Enable + * 0b0..SA Filtering is disabled + * 0b1..SA Filtering is enabled + */ +#define ENET_QOS_MAC_PACKET_FILTER_SAF(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PACKET_FILTER_SAF_SHIFT)) & ENET_QOS_MAC_PACKET_FILTER_SAF_MASK) + +#define ENET_QOS_MAC_PACKET_FILTER_HPF_MASK (0x400U) +#define ENET_QOS_MAC_PACKET_FILTER_HPF_SHIFT (10U) +/*! HPF - Hash or Perfect Filter + * 0b0..Hash or Perfect Filter is disabled + * 0b1..Hash or Perfect Filter is enabled + */ +#define ENET_QOS_MAC_PACKET_FILTER_HPF(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PACKET_FILTER_HPF_SHIFT)) & ENET_QOS_MAC_PACKET_FILTER_HPF_MASK) + +#define ENET_QOS_MAC_PACKET_FILTER_VTFE_MASK (0x10000U) +#define ENET_QOS_MAC_PACKET_FILTER_VTFE_SHIFT (16U) +/*! VTFE - VLAN Tag Filter Enable + * 0b0..VLAN Tag Filter is disabled + * 0b1..VLAN Tag Filter is enabled + */ +#define ENET_QOS_MAC_PACKET_FILTER_VTFE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PACKET_FILTER_VTFE_SHIFT)) & ENET_QOS_MAC_PACKET_FILTER_VTFE_MASK) + +#define ENET_QOS_MAC_PACKET_FILTER_IPFE_MASK (0x100000U) +#define ENET_QOS_MAC_PACKET_FILTER_IPFE_SHIFT (20U) +/*! IPFE - Layer 3 and Layer 4 Filter Enable + * 0b0..Layer 3 and Layer 4 Filters are disabled + * 0b1..Layer 3 and Layer 4 Filters are enabled + */ +#define ENET_QOS_MAC_PACKET_FILTER_IPFE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PACKET_FILTER_IPFE_SHIFT)) & ENET_QOS_MAC_PACKET_FILTER_IPFE_MASK) + +#define ENET_QOS_MAC_PACKET_FILTER_DNTU_MASK (0x200000U) +#define ENET_QOS_MAC_PACKET_FILTER_DNTU_SHIFT (21U) +/*! DNTU - Drop Non-TCP/UDP over IP Packets + * 0b0..Forward Non-TCP/UDP over IP Packets + * 0b1..Drop Non-TCP/UDP over IP Packets + */ +#define ENET_QOS_MAC_PACKET_FILTER_DNTU(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PACKET_FILTER_DNTU_SHIFT)) & ENET_QOS_MAC_PACKET_FILTER_DNTU_MASK) + +#define ENET_QOS_MAC_PACKET_FILTER_RA_MASK (0x80000000U) +#define ENET_QOS_MAC_PACKET_FILTER_RA_SHIFT (31U) +/*! RA - Receive All + * 0b0..Receive All is disabled + * 0b1..Receive All is enabled + */ +#define ENET_QOS_MAC_PACKET_FILTER_RA(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PACKET_FILTER_RA_SHIFT)) & ENET_QOS_MAC_PACKET_FILTER_RA_MASK) +/*! @} */ + +/*! @name MAC_WATCHDOG_TIMEOUT - Watchdog Timeout */ +/*! @{ */ + +#define ENET_QOS_MAC_WATCHDOG_TIMEOUT_WTO_MASK (0xFU) +#define ENET_QOS_MAC_WATCHDOG_TIMEOUT_WTO_SHIFT (0U) +/*! WTO - Watchdog Timeout + * 0b0000..2 KB + * 0b0001..3 KB + * 0b0010..4 KB + * 0b0011..5 KB + * 0b0100..6 KB + * 0b0101..7 KB + * 0b0110..8 KB + * 0b0111..9 KB + * 0b1000..10 KB + * 0b1001..11 KB + * 0b1010..12 KB + * 0b1011..13 KB + * 0b1100..14 KB + * 0b1101..15 KB + * 0b1110..16383 Bytes + * 0b1111..Reserved + */ +#define ENET_QOS_MAC_WATCHDOG_TIMEOUT_WTO(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_WATCHDOG_TIMEOUT_WTO_SHIFT)) & ENET_QOS_MAC_WATCHDOG_TIMEOUT_WTO_MASK) + +#define ENET_QOS_MAC_WATCHDOG_TIMEOUT_PWE_MASK (0x100U) +#define ENET_QOS_MAC_WATCHDOG_TIMEOUT_PWE_SHIFT (8U) +/*! PWE - Programmable Watchdog Enable + * 0b0..Programmable Watchdog is disabled + * 0b1..Programmable Watchdog is enabled + */ +#define ENET_QOS_MAC_WATCHDOG_TIMEOUT_PWE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_WATCHDOG_TIMEOUT_PWE_SHIFT)) & ENET_QOS_MAC_WATCHDOG_TIMEOUT_PWE_MASK) +/*! @} */ + +/*! @name MAC_HASH_TABLE_REG0 - MAC Hash Table Register 0 */ +/*! @{ */ + +#define ENET_QOS_MAC_HASH_TABLE_REG0_HT31T0_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_HASH_TABLE_REG0_HT31T0_SHIFT (0U) +/*! HT31T0 - MAC Hash Table First 32 Bits This field contains the first 32 Bits [31:0] of the Hash table. */ +#define ENET_QOS_MAC_HASH_TABLE_REG0_HT31T0(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HASH_TABLE_REG0_HT31T0_SHIFT)) & ENET_QOS_MAC_HASH_TABLE_REG0_HT31T0_MASK) +/*! @} */ + +/*! @name MAC_HASH_TABLE_REG1 - MAC Hash Table Register 1 */ +/*! @{ */ + +#define ENET_QOS_MAC_HASH_TABLE_REG1_HT63T32_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_HASH_TABLE_REG1_HT63T32_SHIFT (0U) +/*! HT63T32 - MAC Hash Table Second 32 Bits This field contains the second 32 Bits [63:32] of the Hash table. */ +#define ENET_QOS_MAC_HASH_TABLE_REG1_HT63T32(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HASH_TABLE_REG1_HT63T32_SHIFT)) & ENET_QOS_MAC_HASH_TABLE_REG1_HT63T32_MASK) +/*! @} */ + +/*! @name MAC_VLAN_TAG_CTRL - MAC VLAN Tag Control */ +/*! @{ */ + +#define ENET_QOS_MAC_VLAN_TAG_CTRL_OB_MASK (0x1U) +#define ENET_QOS_MAC_VLAN_TAG_CTRL_OB_SHIFT (0U) +/*! OB - Operation Busy + * 0b0..Operation Busy is disabled + * 0b1..Operation Busy is enabled + */ +#define ENET_QOS_MAC_VLAN_TAG_CTRL_OB(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_TAG_CTRL_OB_SHIFT)) & ENET_QOS_MAC_VLAN_TAG_CTRL_OB_MASK) + +#define ENET_QOS_MAC_VLAN_TAG_CTRL_CT_MASK (0x2U) +#define ENET_QOS_MAC_VLAN_TAG_CTRL_CT_SHIFT (1U) +/*! CT - Command Type + * 0b0..Write operation + * 0b1..Read operation + */ +#define ENET_QOS_MAC_VLAN_TAG_CTRL_CT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_TAG_CTRL_CT_SHIFT)) & ENET_QOS_MAC_VLAN_TAG_CTRL_CT_MASK) + +#define ENET_QOS_MAC_VLAN_TAG_CTRL_OFS_MASK (0x7CU) +#define ENET_QOS_MAC_VLAN_TAG_CTRL_OFS_SHIFT (2U) +/*! OFS - Offset */ +#define ENET_QOS_MAC_VLAN_TAG_CTRL_OFS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_TAG_CTRL_OFS_SHIFT)) & ENET_QOS_MAC_VLAN_TAG_CTRL_OFS_MASK) + +#define ENET_QOS_MAC_VLAN_TAG_CTRL_VTIM_MASK (0x20000U) +#define ENET_QOS_MAC_VLAN_TAG_CTRL_VTIM_SHIFT (17U) +/*! VTIM - VLAN Tag Inverse Match Enable + * 0b0..VLAN Tag Inverse Match is disabled + * 0b1..VLAN Tag Inverse Match is enabled + */ +#define ENET_QOS_MAC_VLAN_TAG_CTRL_VTIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_TAG_CTRL_VTIM_SHIFT)) & ENET_QOS_MAC_VLAN_TAG_CTRL_VTIM_MASK) + +#define ENET_QOS_MAC_VLAN_TAG_CTRL_ESVL_MASK (0x40000U) +#define ENET_QOS_MAC_VLAN_TAG_CTRL_ESVL_SHIFT (18U) +/*! ESVL - Enable S-VLAN When this bit is set, the MAC transmitter and receiver consider the S-VLAN + * packets (Type = 0x88A8) as valid VLAN tagged packets. + * 0b0..S-VLAN is disabled + * 0b1..S-VLAN is enabled + */ +#define ENET_QOS_MAC_VLAN_TAG_CTRL_ESVL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_TAG_CTRL_ESVL_SHIFT)) & ENET_QOS_MAC_VLAN_TAG_CTRL_ESVL_MASK) + +#define ENET_QOS_MAC_VLAN_TAG_CTRL_EVLS_MASK (0x600000U) +#define ENET_QOS_MAC_VLAN_TAG_CTRL_EVLS_SHIFT (21U) +/*! EVLS - Enable VLAN Tag Stripping on Receive This field indicates the stripping operation on the + * outer VLAN Tag in received packet. + * 0b00..Do not strip + * 0b01..Strip if VLAN filter passes + * 0b10..Strip if VLAN filter fails + * 0b11..Always strip + */ +#define ENET_QOS_MAC_VLAN_TAG_CTRL_EVLS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_TAG_CTRL_EVLS_SHIFT)) & ENET_QOS_MAC_VLAN_TAG_CTRL_EVLS_MASK) + +#define ENET_QOS_MAC_VLAN_TAG_CTRL_EVLRXS_MASK (0x1000000U) +#define ENET_QOS_MAC_VLAN_TAG_CTRL_EVLRXS_SHIFT (24U) +/*! EVLRXS - Enable VLAN Tag in Rx status + * 0b0..VLAN Tag in Rx status is disabled + * 0b1..VLAN Tag in Rx status is enabled + */ +#define ENET_QOS_MAC_VLAN_TAG_CTRL_EVLRXS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_TAG_CTRL_EVLRXS_SHIFT)) & ENET_QOS_MAC_VLAN_TAG_CTRL_EVLRXS_MASK) + +#define ENET_QOS_MAC_VLAN_TAG_CTRL_VTHM_MASK (0x2000000U) +#define ENET_QOS_MAC_VLAN_TAG_CTRL_VTHM_SHIFT (25U) +/*! VTHM - VLAN Tag Hash Table Match Enable + * 0b0..VLAN Tag Hash Table Match is disabled + * 0b1..VLAN Tag Hash Table Match is enabled + */ +#define ENET_QOS_MAC_VLAN_TAG_CTRL_VTHM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_TAG_CTRL_VTHM_SHIFT)) & ENET_QOS_MAC_VLAN_TAG_CTRL_VTHM_MASK) + +#define ENET_QOS_MAC_VLAN_TAG_CTRL_EDVLP_MASK (0x4000000U) +#define ENET_QOS_MAC_VLAN_TAG_CTRL_EDVLP_SHIFT (26U) +/*! EDVLP - Enable Double VLAN Processing + * 0b0..Double VLAN Processing is disabled + * 0b1..Double VLAN Processing is enabled + */ +#define ENET_QOS_MAC_VLAN_TAG_CTRL_EDVLP(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_TAG_CTRL_EDVLP_SHIFT)) & ENET_QOS_MAC_VLAN_TAG_CTRL_EDVLP_MASK) + +#define ENET_QOS_MAC_VLAN_TAG_CTRL_ERIVLT_MASK (0x8000000U) +#define ENET_QOS_MAC_VLAN_TAG_CTRL_ERIVLT_SHIFT (27U) +/*! ERIVLT - ERIVLT + * 0b0..Inner VLAN tag is disabled + * 0b1..Inner VLAN tag is enabled + */ +#define ENET_QOS_MAC_VLAN_TAG_CTRL_ERIVLT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_TAG_CTRL_ERIVLT_SHIFT)) & ENET_QOS_MAC_VLAN_TAG_CTRL_ERIVLT_MASK) + +#define ENET_QOS_MAC_VLAN_TAG_CTRL_EIVLS_MASK (0x30000000U) +#define ENET_QOS_MAC_VLAN_TAG_CTRL_EIVLS_SHIFT (28U) +/*! EIVLS - Enable Inner VLAN Tag Stripping on Receive This field indicates the stripping operation + * on inner VLAN Tag in received packet. + * 0b00..Do not strip + * 0b01..Strip if VLAN filter passes + * 0b10..Strip if VLAN filter fails + * 0b11..Always strip + */ +#define ENET_QOS_MAC_VLAN_TAG_CTRL_EIVLS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_TAG_CTRL_EIVLS_SHIFT)) & ENET_QOS_MAC_VLAN_TAG_CTRL_EIVLS_MASK) + +#define ENET_QOS_MAC_VLAN_TAG_CTRL_EIVLRXS_MASK (0x80000000U) +#define ENET_QOS_MAC_VLAN_TAG_CTRL_EIVLRXS_SHIFT (31U) +/*! EIVLRXS - Enable Inner VLAN Tag in Rx Status + * 0b0..Inner VLAN Tag in Rx status is disabled + * 0b1..Inner VLAN Tag in Rx status is enabled + */ +#define ENET_QOS_MAC_VLAN_TAG_CTRL_EIVLRXS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_TAG_CTRL_EIVLRXS_SHIFT)) & ENET_QOS_MAC_VLAN_TAG_CTRL_EIVLRXS_MASK) +/*! @} */ + +/*! @name MAC_VLAN_TAG_DATA - MAC VLAN Tag Data */ +/*! @{ */ + +#define ENET_QOS_MAC_VLAN_TAG_DATA_VID_MASK (0xFFFFU) +#define ENET_QOS_MAC_VLAN_TAG_DATA_VID_SHIFT (0U) +/*! VID - VLAN Tag ID */ +#define ENET_QOS_MAC_VLAN_TAG_DATA_VID(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_TAG_DATA_VID_SHIFT)) & ENET_QOS_MAC_VLAN_TAG_DATA_VID_MASK) + +#define ENET_QOS_MAC_VLAN_TAG_DATA_VEN_MASK (0x10000U) +#define ENET_QOS_MAC_VLAN_TAG_DATA_VEN_SHIFT (16U) +/*! VEN - VLAN Tag Enable + * 0b0..VLAN Tag is disabled + * 0b1..VLAN Tag is enabled + */ +#define ENET_QOS_MAC_VLAN_TAG_DATA_VEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_TAG_DATA_VEN_SHIFT)) & ENET_QOS_MAC_VLAN_TAG_DATA_VEN_MASK) + +#define ENET_QOS_MAC_VLAN_TAG_DATA_ETV_MASK (0x20000U) +#define ENET_QOS_MAC_VLAN_TAG_DATA_ETV_SHIFT (17U) +/*! ETV - 12bits or 16bits VLAN comparison + * 0b0..16 bit VLAN comparison + * 0b1..12 bit VLAN comparison + */ +#define ENET_QOS_MAC_VLAN_TAG_DATA_ETV(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_TAG_DATA_ETV_SHIFT)) & ENET_QOS_MAC_VLAN_TAG_DATA_ETV_MASK) + +#define ENET_QOS_MAC_VLAN_TAG_DATA_DOVLTC_MASK (0x40000U) +#define ENET_QOS_MAC_VLAN_TAG_DATA_DOVLTC_SHIFT (18U) +/*! DOVLTC - Disable VLAN Type Comparison + * 0b0..VLAN type comparison is enabled + * 0b1..VLAN type comparison is disabled + */ +#define ENET_QOS_MAC_VLAN_TAG_DATA_DOVLTC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_TAG_DATA_DOVLTC_SHIFT)) & ENET_QOS_MAC_VLAN_TAG_DATA_DOVLTC_MASK) + +#define ENET_QOS_MAC_VLAN_TAG_DATA_ERSVLM_MASK (0x80000U) +#define ENET_QOS_MAC_VLAN_TAG_DATA_ERSVLM_SHIFT (19U) +/*! ERSVLM - Enable S-VLAN Match for received Frames + * 0b0..Receive S-VLAN Match is disabled + * 0b1..Receive S-VLAN Match is enabled + */ +#define ENET_QOS_MAC_VLAN_TAG_DATA_ERSVLM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_TAG_DATA_ERSVLM_SHIFT)) & ENET_QOS_MAC_VLAN_TAG_DATA_ERSVLM_MASK) + +#define ENET_QOS_MAC_VLAN_TAG_DATA_ERIVLT_MASK (0x100000U) +#define ENET_QOS_MAC_VLAN_TAG_DATA_ERIVLT_SHIFT (20U) +/*! ERIVLT - Enable Inner VLAN Tag Comparison + * 0b0..Inner VLAN tag comparison is disabled + * 0b1..Inner VLAN tag comparison is enabled + */ +#define ENET_QOS_MAC_VLAN_TAG_DATA_ERIVLT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_TAG_DATA_ERIVLT_SHIFT)) & ENET_QOS_MAC_VLAN_TAG_DATA_ERIVLT_MASK) + +#define ENET_QOS_MAC_VLAN_TAG_DATA_DMACHEN_MASK (0x1000000U) +#define ENET_QOS_MAC_VLAN_TAG_DATA_DMACHEN_SHIFT (24U) +/*! DMACHEN - DMA Channel Number Enable + * 0b0..DMA Channel Number is disabled + * 0b1..DMA Channel Number is enabled + */ +#define ENET_QOS_MAC_VLAN_TAG_DATA_DMACHEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_TAG_DATA_DMACHEN_SHIFT)) & ENET_QOS_MAC_VLAN_TAG_DATA_DMACHEN_MASK) + +#define ENET_QOS_MAC_VLAN_TAG_DATA_DMACHN_MASK (0xE000000U) +#define ENET_QOS_MAC_VLAN_TAG_DATA_DMACHN_SHIFT (25U) +/*! DMACHN - DMA Channel Number */ +#define ENET_QOS_MAC_VLAN_TAG_DATA_DMACHN(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_TAG_DATA_DMACHN_SHIFT)) & ENET_QOS_MAC_VLAN_TAG_DATA_DMACHN_MASK) +/*! @} */ + +/*! @name MAC_VLAN_HASH_TABLE - MAC VLAN Hash Table */ +/*! @{ */ + +#define ENET_QOS_MAC_VLAN_HASH_TABLE_VLHT_MASK (0xFFFFU) +#define ENET_QOS_MAC_VLAN_HASH_TABLE_VLHT_SHIFT (0U) +/*! VLHT - VLAN Hash Table This field contains the 16-bit VLAN Hash Table. */ +#define ENET_QOS_MAC_VLAN_HASH_TABLE_VLHT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_HASH_TABLE_VLHT_SHIFT)) & ENET_QOS_MAC_VLAN_HASH_TABLE_VLHT_MASK) +/*! @} */ + +/*! @name MAC_VLAN_INCL - VLAN Tag Inclusion or Replacement */ +/*! @{ */ + +#define ENET_QOS_MAC_VLAN_INCL_VLT_MASK (0xFFFFU) +#define ENET_QOS_MAC_VLAN_INCL_VLT_SHIFT (0U) +/*! VLT - VLAN Tag for Transmit Packets */ +#define ENET_QOS_MAC_VLAN_INCL_VLT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_INCL_VLT_SHIFT)) & ENET_QOS_MAC_VLAN_INCL_VLT_MASK) + +#define ENET_QOS_MAC_VLAN_INCL_VLC_MASK (0x30000U) +#define ENET_QOS_MAC_VLAN_INCL_VLC_SHIFT (16U) +/*! VLC - VLAN Tag Control in Transmit Packets - 2'b00: No VLAN tag deletion, insertion, or + * replacement - 2'b01: VLAN tag deletion The MAC removes the VLAN type (bytes 13 and 14) and VLAN tag + * (bytes 15 and 16) of all transmitted packets with VLAN tags. + * 0b00..No VLAN tag deletion, insertion, or replacement + * 0b01..VLAN tag deletion + * 0b10..VLAN tag insertion + * 0b11..VLAN tag replacement + */ +#define ENET_QOS_MAC_VLAN_INCL_VLC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_INCL_VLC_SHIFT)) & ENET_QOS_MAC_VLAN_INCL_VLC_MASK) + +#define ENET_QOS_MAC_VLAN_INCL_VLP_MASK (0x40000U) +#define ENET_QOS_MAC_VLAN_INCL_VLP_SHIFT (18U) +/*! VLP - VLAN Priority Control + * 0b0..VLAN Priority Control is disabled + * 0b1..VLAN Priority Control is enabled + */ +#define ENET_QOS_MAC_VLAN_INCL_VLP(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_INCL_VLP_SHIFT)) & ENET_QOS_MAC_VLAN_INCL_VLP_MASK) + +#define ENET_QOS_MAC_VLAN_INCL_CSVL_MASK (0x80000U) +#define ENET_QOS_MAC_VLAN_INCL_CSVL_SHIFT (19U) +/*! CSVL - C-VLAN or S-VLAN + * 0b0..C-VLAN type (0x8100) is inserted or replaced + * 0b1..S-VLAN type (0x88A8) is inserted or replaced + */ +#define ENET_QOS_MAC_VLAN_INCL_CSVL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_INCL_CSVL_SHIFT)) & ENET_QOS_MAC_VLAN_INCL_CSVL_MASK) + +#define ENET_QOS_MAC_VLAN_INCL_VLTI_MASK (0x100000U) +#define ENET_QOS_MAC_VLAN_INCL_VLTI_SHIFT (20U) +/*! VLTI - VLAN Tag Input When this bit is set, it indicates that the VLAN tag to be inserted or + * replaced in Tx packet should be taken from: - The Tx descriptor + * 0b0..VLAN Tag Input is disabled + * 0b1..VLAN Tag Input is enabled + */ +#define ENET_QOS_MAC_VLAN_INCL_VLTI(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_INCL_VLTI_SHIFT)) & ENET_QOS_MAC_VLAN_INCL_VLTI_MASK) + +#define ENET_QOS_MAC_VLAN_INCL_CBTI_MASK (0x200000U) +#define ENET_QOS_MAC_VLAN_INCL_CBTI_SHIFT (21U) +/*! CBTI - Channel based tag insertion + * 0b0..Channel based tag insertion is disabled + * 0b1..Channel based tag insertion is enabled + */ +#define ENET_QOS_MAC_VLAN_INCL_CBTI(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_INCL_CBTI_SHIFT)) & ENET_QOS_MAC_VLAN_INCL_CBTI_MASK) + +#define ENET_QOS_MAC_VLAN_INCL_ADDR_MASK (0x7000000U) +#define ENET_QOS_MAC_VLAN_INCL_ADDR_SHIFT (24U) +/*! ADDR - Address */ +#define ENET_QOS_MAC_VLAN_INCL_ADDR(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_INCL_ADDR_SHIFT)) & ENET_QOS_MAC_VLAN_INCL_ADDR_MASK) + +#define ENET_QOS_MAC_VLAN_INCL_RDWR_MASK (0x40000000U) +#define ENET_QOS_MAC_VLAN_INCL_RDWR_SHIFT (30U) +/*! RDWR - Read write control + * 0b0..Read operation of indirect access + * 0b1..Write operation of indirect access + */ +#define ENET_QOS_MAC_VLAN_INCL_RDWR(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_INCL_RDWR_SHIFT)) & ENET_QOS_MAC_VLAN_INCL_RDWR_MASK) + +#define ENET_QOS_MAC_VLAN_INCL_BUSY_MASK (0x80000000U) +#define ENET_QOS_MAC_VLAN_INCL_BUSY_SHIFT (31U) +/*! BUSY - Busy + * 0b0..Busy status not detected + * 0b1..Busy status detected + */ +#define ENET_QOS_MAC_VLAN_INCL_BUSY(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_INCL_BUSY_SHIFT)) & ENET_QOS_MAC_VLAN_INCL_BUSY_MASK) +/*! @} */ + +/*! @name MAC_INNER_VLAN_INCL - MAC Inner VLAN Tag Inclusion or Replacement */ +/*! @{ */ + +#define ENET_QOS_MAC_INNER_VLAN_INCL_VLT_MASK (0xFFFFU) +#define ENET_QOS_MAC_INNER_VLAN_INCL_VLT_SHIFT (0U) +/*! VLT - VLAN Tag for Transmit Packets */ +#define ENET_QOS_MAC_INNER_VLAN_INCL_VLT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INNER_VLAN_INCL_VLT_SHIFT)) & ENET_QOS_MAC_INNER_VLAN_INCL_VLT_MASK) + +#define ENET_QOS_MAC_INNER_VLAN_INCL_VLC_MASK (0x30000U) +#define ENET_QOS_MAC_INNER_VLAN_INCL_VLC_SHIFT (16U) +/*! VLC - VLAN Tag Control in Transmit Packets + * 0b00..No VLAN tag deletion, insertion, or replacement + * 0b01..VLAN tag deletion + * 0b10..VLAN tag insertion + * 0b11..VLAN tag replacement + */ +#define ENET_QOS_MAC_INNER_VLAN_INCL_VLC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INNER_VLAN_INCL_VLC_SHIFT)) & ENET_QOS_MAC_INNER_VLAN_INCL_VLC_MASK) + +#define ENET_QOS_MAC_INNER_VLAN_INCL_VLP_MASK (0x40000U) +#define ENET_QOS_MAC_INNER_VLAN_INCL_VLP_SHIFT (18U) +/*! VLP - VLAN Priority Control + * 0b0..VLAN Priority Control is disabled + * 0b1..VLAN Priority Control is enabled + */ +#define ENET_QOS_MAC_INNER_VLAN_INCL_VLP(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INNER_VLAN_INCL_VLP_SHIFT)) & ENET_QOS_MAC_INNER_VLAN_INCL_VLP_MASK) + +#define ENET_QOS_MAC_INNER_VLAN_INCL_CSVL_MASK (0x80000U) +#define ENET_QOS_MAC_INNER_VLAN_INCL_CSVL_SHIFT (19U) +/*! CSVL - C-VLAN or S-VLAN + * 0b0..C-VLAN type (0x8100) is inserted + * 0b1..S-VLAN type (0x88A8) is inserted + */ +#define ENET_QOS_MAC_INNER_VLAN_INCL_CSVL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INNER_VLAN_INCL_CSVL_SHIFT)) & ENET_QOS_MAC_INNER_VLAN_INCL_CSVL_MASK) + +#define ENET_QOS_MAC_INNER_VLAN_INCL_VLTI_MASK (0x100000U) +#define ENET_QOS_MAC_INNER_VLAN_INCL_VLTI_SHIFT (20U) +/*! VLTI - VLAN Tag Input When this bit is set, it indicates that the VLAN tag to be inserted or + * replaced in Tx packet should be taken from: - The Tx descriptor + * 0b0..VLAN Tag Input is disabled + * 0b1..VLAN Tag Input is enabled + */ +#define ENET_QOS_MAC_INNER_VLAN_INCL_VLTI(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INNER_VLAN_INCL_VLTI_SHIFT)) & ENET_QOS_MAC_INNER_VLAN_INCL_VLTI_MASK) +/*! @} */ + +/*! @name MAC_TX_FLOW_CTRL_Q - MAC Q0 Tx Flow Control..MAC Q4 Tx Flow Control */ +/*! @{ */ + +#define ENET_QOS_MAC_TX_FLOW_CTRL_Q_FCB_BPA_MASK (0x1U) +#define ENET_QOS_MAC_TX_FLOW_CTRL_Q_FCB_BPA_SHIFT (0U) +/*! FCB_BPA - Flow Control Busy or Backpressure Activate + * 0b0..Flow Control Busy or Backpressure Activate is disabled + * 0b1..Flow Control Busy or Backpressure Activate is enabled + */ +#define ENET_QOS_MAC_TX_FLOW_CTRL_Q_FCB_BPA(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_FLOW_CTRL_Q_FCB_BPA_SHIFT)) & ENET_QOS_MAC_TX_FLOW_CTRL_Q_FCB_BPA_MASK) + +#define ENET_QOS_MAC_TX_FLOW_CTRL_Q_TFE_MASK (0x2U) +#define ENET_QOS_MAC_TX_FLOW_CTRL_Q_TFE_SHIFT (1U) +/*! TFE - Transmit Flow Control Enable + * 0b0..Transmit Flow Control is disabled + * 0b1..Transmit Flow Control is enabled + */ +#define ENET_QOS_MAC_TX_FLOW_CTRL_Q_TFE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_FLOW_CTRL_Q_TFE_SHIFT)) & ENET_QOS_MAC_TX_FLOW_CTRL_Q_TFE_MASK) + +#define ENET_QOS_MAC_TX_FLOW_CTRL_Q_PLT_MASK (0x70U) +#define ENET_QOS_MAC_TX_FLOW_CTRL_Q_PLT_SHIFT (4U) +/*! PLT - Pause Low Threshold + * 0b000..Pause Time minus 4 Slot Times (PT -4 slot times) + * 0b001..Pause Time minus 28 Slot Times (PT -28 slot times) + * 0b010..Pause Time minus 36 Slot Times (PT -36 slot times) + * 0b011..Pause Time minus 144 Slot Times (PT -144 slot times) + * 0b100..Pause Time minus 256 Slot Times (PT -256 slot times) + * 0b101..Pause Time minus 512 Slot Times (PT -512 slot times) + * 0b110..Reserved + */ +#define ENET_QOS_MAC_TX_FLOW_CTRL_Q_PLT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_FLOW_CTRL_Q_PLT_SHIFT)) & ENET_QOS_MAC_TX_FLOW_CTRL_Q_PLT_MASK) + +#define ENET_QOS_MAC_TX_FLOW_CTRL_Q_DZPQ_MASK (0x80U) +#define ENET_QOS_MAC_TX_FLOW_CTRL_Q_DZPQ_SHIFT (7U) +/*! DZPQ - Disable Zero-Quanta Pause + * 0b0..Zero-Quanta Pause packet generation is enabled + * 0b1..Zero-Quanta Pause packet generation is disabled + */ +#define ENET_QOS_MAC_TX_FLOW_CTRL_Q_DZPQ(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_FLOW_CTRL_Q_DZPQ_SHIFT)) & ENET_QOS_MAC_TX_FLOW_CTRL_Q_DZPQ_MASK) + +#define ENET_QOS_MAC_TX_FLOW_CTRL_Q_PT_MASK (0xFFFF0000U) +#define ENET_QOS_MAC_TX_FLOW_CTRL_Q_PT_SHIFT (16U) +/*! PT - Pause Time */ +#define ENET_QOS_MAC_TX_FLOW_CTRL_Q_PT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_FLOW_CTRL_Q_PT_SHIFT)) & ENET_QOS_MAC_TX_FLOW_CTRL_Q_PT_MASK) +/*! @} */ + +/* The count of ENET_QOS_MAC_TX_FLOW_CTRL_Q */ +#define ENET_QOS_MAC_TX_FLOW_CTRL_Q_COUNT (5U) + +/*! @name MAC_RX_FLOW_CTRL - MAC Rx Flow Control */ +/*! @{ */ + +#define ENET_QOS_MAC_RX_FLOW_CTRL_RFE_MASK (0x1U) +#define ENET_QOS_MAC_RX_FLOW_CTRL_RFE_SHIFT (0U) +/*! RFE - Receive Flow Control Enable + * 0b0..Receive Flow Control is disabled + * 0b1..Receive Flow Control is enabled + */ +#define ENET_QOS_MAC_RX_FLOW_CTRL_RFE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_FLOW_CTRL_RFE_SHIFT)) & ENET_QOS_MAC_RX_FLOW_CTRL_RFE_MASK) + +#define ENET_QOS_MAC_RX_FLOW_CTRL_UP_MASK (0x2U) +#define ENET_QOS_MAC_RX_FLOW_CTRL_UP_SHIFT (1U) +/*! UP - Unicast Pause Packet Detect + * 0b0..Unicast Pause Packet Detect disabled + * 0b1..Unicast Pause Packet Detect enabled + */ +#define ENET_QOS_MAC_RX_FLOW_CTRL_UP(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_FLOW_CTRL_UP_SHIFT)) & ENET_QOS_MAC_RX_FLOW_CTRL_UP_MASK) + +#define ENET_QOS_MAC_RX_FLOW_CTRL_PFCE_MASK (0x100U) +#define ENET_QOS_MAC_RX_FLOW_CTRL_PFCE_SHIFT (8U) +/*! PFCE - Priority Based Flow Control Enable + * 0b0..Priority Based Flow Control is disabled + * 0b1..Priority Based Flow Control is enabled + */ +#define ENET_QOS_MAC_RX_FLOW_CTRL_PFCE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_FLOW_CTRL_PFCE_SHIFT)) & ENET_QOS_MAC_RX_FLOW_CTRL_PFCE_MASK) +/*! @} */ + +/*! @name MAC_RXQ_CTRL4 - Receive Queue Control 4 */ +/*! @{ */ + +#define ENET_QOS_MAC_RXQ_CTRL4_UFFQE_MASK (0x1U) +#define ENET_QOS_MAC_RXQ_CTRL4_UFFQE_SHIFT (0U) +/*! UFFQE - Unicast Address Filter Fail Packets Queuing Enable. + * 0b0..Unicast Address Filter Fail Packets Queuing is disabled + * 0b1..Unicast Address Filter Fail Packets Queuing is enabled + */ +#define ENET_QOS_MAC_RXQ_CTRL4_UFFQE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXQ_CTRL4_UFFQE_SHIFT)) & ENET_QOS_MAC_RXQ_CTRL4_UFFQE_MASK) + +#define ENET_QOS_MAC_RXQ_CTRL4_UFFQ_MASK (0xEU) +#define ENET_QOS_MAC_RXQ_CTRL4_UFFQ_SHIFT (1U) +/*! UFFQ - Unicast Address Filter Fail Packets Queue. */ +#define ENET_QOS_MAC_RXQ_CTRL4_UFFQ(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXQ_CTRL4_UFFQ_SHIFT)) & ENET_QOS_MAC_RXQ_CTRL4_UFFQ_MASK) + +#define ENET_QOS_MAC_RXQ_CTRL4_MFFQE_MASK (0x100U) +#define ENET_QOS_MAC_RXQ_CTRL4_MFFQE_SHIFT (8U) +/*! MFFQE - Multicast Address Filter Fail Packets Queuing Enable. + * 0b0..Multicast Address Filter Fail Packets Queuing is disabled + * 0b1..Multicast Address Filter Fail Packets Queuing is enabled + */ +#define ENET_QOS_MAC_RXQ_CTRL4_MFFQE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXQ_CTRL4_MFFQE_SHIFT)) & ENET_QOS_MAC_RXQ_CTRL4_MFFQE_MASK) + +#define ENET_QOS_MAC_RXQ_CTRL4_MFFQ_MASK (0xE00U) +#define ENET_QOS_MAC_RXQ_CTRL4_MFFQ_SHIFT (9U) +/*! MFFQ - Multicast Address Filter Fail Packets Queue. */ +#define ENET_QOS_MAC_RXQ_CTRL4_MFFQ(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXQ_CTRL4_MFFQ_SHIFT)) & ENET_QOS_MAC_RXQ_CTRL4_MFFQ_MASK) + +#define ENET_QOS_MAC_RXQ_CTRL4_VFFQE_MASK (0x10000U) +#define ENET_QOS_MAC_RXQ_CTRL4_VFFQE_SHIFT (16U) +/*! VFFQE - VLAN Tag Filter Fail Packets Queuing Enable + * 0b0..VLAN tag Filter Fail Packets Queuing is disabled + * 0b1..VLAN tag Filter Fail Packets Queuing is enabled + */ +#define ENET_QOS_MAC_RXQ_CTRL4_VFFQE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXQ_CTRL4_VFFQE_SHIFT)) & ENET_QOS_MAC_RXQ_CTRL4_VFFQE_MASK) + +#define ENET_QOS_MAC_RXQ_CTRL4_VFFQ_MASK (0xE0000U) +#define ENET_QOS_MAC_RXQ_CTRL4_VFFQ_SHIFT (17U) +/*! VFFQ - VLAN Tag Filter Fail Packets Queue */ +#define ENET_QOS_MAC_RXQ_CTRL4_VFFQ(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXQ_CTRL4_VFFQ_SHIFT)) & ENET_QOS_MAC_RXQ_CTRL4_VFFQ_MASK) +/*! @} */ + +/*! @name MAC_TXQ_PRTY_MAP0 - Transmit Queue Priority Mapping 0 */ +/*! @{ */ + +#define ENET_QOS_MAC_TXQ_PRTY_MAP0_PSTQ0_MASK (0xFFU) +#define ENET_QOS_MAC_TXQ_PRTY_MAP0_PSTQ0_SHIFT (0U) +/*! PSTQ0 - Priorities Selected in Transmit Queue 0 */ +#define ENET_QOS_MAC_TXQ_PRTY_MAP0_PSTQ0(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TXQ_PRTY_MAP0_PSTQ0_SHIFT)) & ENET_QOS_MAC_TXQ_PRTY_MAP0_PSTQ0_MASK) + +#define ENET_QOS_MAC_TXQ_PRTY_MAP0_PSTQ1_MASK (0xFF00U) +#define ENET_QOS_MAC_TXQ_PRTY_MAP0_PSTQ1_SHIFT (8U) +/*! PSTQ1 - Priorities Selected in Transmit Queue 1 This bit is similar to the PSTQ0 bit. */ +#define ENET_QOS_MAC_TXQ_PRTY_MAP0_PSTQ1(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TXQ_PRTY_MAP0_PSTQ1_SHIFT)) & ENET_QOS_MAC_TXQ_PRTY_MAP0_PSTQ1_MASK) + +#define ENET_QOS_MAC_TXQ_PRTY_MAP0_PSTQ2_MASK (0xFF0000U) +#define ENET_QOS_MAC_TXQ_PRTY_MAP0_PSTQ2_SHIFT (16U) +/*! PSTQ2 - Priorities Selected in Transmit Queue 2 This bit is similar to the PSTQ0 bit. */ +#define ENET_QOS_MAC_TXQ_PRTY_MAP0_PSTQ2(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TXQ_PRTY_MAP0_PSTQ2_SHIFT)) & ENET_QOS_MAC_TXQ_PRTY_MAP0_PSTQ2_MASK) + +#define ENET_QOS_MAC_TXQ_PRTY_MAP0_PSTQ3_MASK (0xFF000000U) +#define ENET_QOS_MAC_TXQ_PRTY_MAP0_PSTQ3_SHIFT (24U) +/*! PSTQ3 - Priorities Selected in Transmit Queue 3 This bit is similar to the PSTQ0 bit. */ +#define ENET_QOS_MAC_TXQ_PRTY_MAP0_PSTQ3(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TXQ_PRTY_MAP0_PSTQ3_SHIFT)) & ENET_QOS_MAC_TXQ_PRTY_MAP0_PSTQ3_MASK) +/*! @} */ + +/*! @name MAC_TXQ_PRTY_MAP1 - Transmit Queue Priority Mapping 1 */ +/*! @{ */ + +#define ENET_QOS_MAC_TXQ_PRTY_MAP1_PSTQ4_MASK (0xFFU) +#define ENET_QOS_MAC_TXQ_PRTY_MAP1_PSTQ4_SHIFT (0U) +/*! PSTQ4 - Priorities Selected in Transmit Queue 4 */ +#define ENET_QOS_MAC_TXQ_PRTY_MAP1_PSTQ4(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TXQ_PRTY_MAP1_PSTQ4_SHIFT)) & ENET_QOS_MAC_TXQ_PRTY_MAP1_PSTQ4_MASK) +/*! @} */ + +/*! @name MAC_RXQ_CTRL - Receive Queue Control 0..Receive Queue Control 3 */ +/*! @{ */ + +#define ENET_QOS_MAC_RXQ_CTRL_AVCPQ_MASK (0x7U) +#define ENET_QOS_MAC_RXQ_CTRL_AVCPQ_SHIFT (0U) +/*! AVCPQ - AV Untagged Control Packets Queue + * 0b000..Receive Queue 0 + * 0b001..Receive Queue 1 + * 0b010..Receive Queue 2 + * 0b011..Receive Queue 3 + * 0b100..Receive Queue 4 + * 0b101..Reserved + * 0b110..Reserved + * 0b111..Reserved + */ +#define ENET_QOS_MAC_RXQ_CTRL_AVCPQ(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXQ_CTRL_AVCPQ_SHIFT)) & ENET_QOS_MAC_RXQ_CTRL_AVCPQ_MASK) + +#define ENET_QOS_MAC_RXQ_CTRL_PSRQ0_MASK (0xFFU) +#define ENET_QOS_MAC_RXQ_CTRL_PSRQ0_SHIFT (0U) +/*! PSRQ0 - Priorities Selected in the Receive Queue 0 */ +#define ENET_QOS_MAC_RXQ_CTRL_PSRQ0(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXQ_CTRL_PSRQ0_SHIFT)) & ENET_QOS_MAC_RXQ_CTRL_PSRQ0_MASK) + +#define ENET_QOS_MAC_RXQ_CTRL_PSRQ4_MASK (0xFFU) +#define ENET_QOS_MAC_RXQ_CTRL_PSRQ4_SHIFT (0U) +/*! PSRQ4 - Priorities Selected in the Receive Queue 4 */ +#define ENET_QOS_MAC_RXQ_CTRL_PSRQ4(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXQ_CTRL_PSRQ4_SHIFT)) & ENET_QOS_MAC_RXQ_CTRL_PSRQ4_MASK) + +#define ENET_QOS_MAC_RXQ_CTRL_RXQ0EN_MASK (0x3U) +#define ENET_QOS_MAC_RXQ_CTRL_RXQ0EN_SHIFT (0U) +/*! RXQ0EN - Receive Queue 0 Enable This field indicates whether Rx Queue 0 is enabled for AV or DCB. + * 0b00..Queue not enabled + * 0b01..Queue enabled for AV + * 0b10..Queue enabled for DCB/Generic + * 0b11..Reserved + */ +#define ENET_QOS_MAC_RXQ_CTRL_RXQ0EN(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXQ_CTRL_RXQ0EN_SHIFT)) & ENET_QOS_MAC_RXQ_CTRL_RXQ0EN_MASK) + +#define ENET_QOS_MAC_RXQ_CTRL_RXQ1EN_MASK (0xCU) +#define ENET_QOS_MAC_RXQ_CTRL_RXQ1EN_SHIFT (2U) +/*! RXQ1EN - Receive Queue 1 Enable This field is similar to the RXQ0EN field. + * 0b00..Queue not enabled + * 0b01..Queue enabled for AV + * 0b10..Queue enabled for DCB/Generic + * 0b11..Reserved + */ +#define ENET_QOS_MAC_RXQ_CTRL_RXQ1EN(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXQ_CTRL_RXQ1EN_SHIFT)) & ENET_QOS_MAC_RXQ_CTRL_RXQ1EN_MASK) + +#define ENET_QOS_MAC_RXQ_CTRL_PTPQ_MASK (0x70U) +#define ENET_QOS_MAC_RXQ_CTRL_PTPQ_SHIFT (4U) +/*! PTPQ - PTP Packets Queue + * 0b000..Receive Queue 0 + * 0b001..Receive Queue 1 + * 0b010..Receive Queue 2 + * 0b011..Receive Queue 3 + * 0b100..Receive Queue 4 + * 0b101..Reserved + * 0b110..Reserved + * 0b111..Reserved + */ +#define ENET_QOS_MAC_RXQ_CTRL_PTPQ(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXQ_CTRL_PTPQ_SHIFT)) & ENET_QOS_MAC_RXQ_CTRL_PTPQ_MASK) + +#define ENET_QOS_MAC_RXQ_CTRL_RXQ2EN_MASK (0x30U) +#define ENET_QOS_MAC_RXQ_CTRL_RXQ2EN_SHIFT (4U) +/*! RXQ2EN - Receive Queue 2 Enable This field is similar to the RXQ0EN field. + * 0b00..Queue not enabled + * 0b01..Queue enabled for AV + * 0b10..Queue enabled for DCB/Generic + * 0b11..Reserved + */ +#define ENET_QOS_MAC_RXQ_CTRL_RXQ2EN(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXQ_CTRL_RXQ2EN_SHIFT)) & ENET_QOS_MAC_RXQ_CTRL_RXQ2EN_MASK) + +#define ENET_QOS_MAC_RXQ_CTRL_RXQ3EN_MASK (0xC0U) +#define ENET_QOS_MAC_RXQ_CTRL_RXQ3EN_SHIFT (6U) +/*! RXQ3EN - Receive Queue 3 Enable This field is similar to the RXQ0EN field. + * 0b00..Queue not enabled + * 0b01..Queue enabled for AV + * 0b10..Queue enabled for DCB/Generic + * 0b11..Reserved + */ +#define ENET_QOS_MAC_RXQ_CTRL_RXQ3EN(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXQ_CTRL_RXQ3EN_SHIFT)) & ENET_QOS_MAC_RXQ_CTRL_RXQ3EN_MASK) + +#define ENET_QOS_MAC_RXQ_CTRL_DCBCPQ_MASK (0x700U) +#define ENET_QOS_MAC_RXQ_CTRL_DCBCPQ_SHIFT (8U) +/*! DCBCPQ - DCB Control Packets Queue + * 0b000..Receive Queue 0 + * 0b001..Receive Queue 1 + * 0b010..Receive Queue 2 + * 0b011..Receive Queue 3 + * 0b100..Receive Queue 4 + * 0b101..Reserved + * 0b110..Reserved + * 0b111..Reserved + */ +#define ENET_QOS_MAC_RXQ_CTRL_DCBCPQ(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXQ_CTRL_DCBCPQ_SHIFT)) & ENET_QOS_MAC_RXQ_CTRL_DCBCPQ_MASK) + +#define ENET_QOS_MAC_RXQ_CTRL_PSRQ1_MASK (0xFF00U) +#define ENET_QOS_MAC_RXQ_CTRL_PSRQ1_SHIFT (8U) +/*! PSRQ1 - Priorities Selected in the Receive Queue 1 */ +#define ENET_QOS_MAC_RXQ_CTRL_PSRQ1(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXQ_CTRL_PSRQ1_SHIFT)) & ENET_QOS_MAC_RXQ_CTRL_PSRQ1_MASK) + +#define ENET_QOS_MAC_RXQ_CTRL_RXQ4EN_MASK (0x300U) +#define ENET_QOS_MAC_RXQ_CTRL_RXQ4EN_SHIFT (8U) +/*! RXQ4EN - Receive Queue 4 Enable This field is similar to the RXQ0EN field. + * 0b00..Queue not enabled + * 0b01..Queue enabled for AV + * 0b10..Queue enabled for DCB/Generic + * 0b11..Reserved + */ +#define ENET_QOS_MAC_RXQ_CTRL_RXQ4EN(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXQ_CTRL_RXQ4EN_SHIFT)) & ENET_QOS_MAC_RXQ_CTRL_RXQ4EN_MASK) + +#define ENET_QOS_MAC_RXQ_CTRL_UPQ_MASK (0x7000U) +#define ENET_QOS_MAC_RXQ_CTRL_UPQ_SHIFT (12U) +/*! UPQ - Untagged Packet Queue + * 0b000..Receive Queue 0 + * 0b001..Receive Queue 1 + * 0b010..Receive Queue 2 + * 0b011..Receive Queue 3 + * 0b100..Receive Queue 4 + * 0b101..Reserved + * 0b110..Reserved + * 0b111..Reserved + */ +#define ENET_QOS_MAC_RXQ_CTRL_UPQ(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXQ_CTRL_UPQ_SHIFT)) & ENET_QOS_MAC_RXQ_CTRL_UPQ_MASK) + +#define ENET_QOS_MAC_RXQ_CTRL_MCBCQ_MASK (0x70000U) +#define ENET_QOS_MAC_RXQ_CTRL_MCBCQ_SHIFT (16U) +/*! MCBCQ - Multicast and Broadcast Queue + * 0b000..Receive Queue 0 + * 0b001..Receive Queue 1 + * 0b010..Receive Queue 2 + * 0b011..Receive Queue 3 + * 0b100..Receive Queue 4 + * 0b101..Reserved + * 0b110..Reserved + * 0b111..Reserved + */ +#define ENET_QOS_MAC_RXQ_CTRL_MCBCQ(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXQ_CTRL_MCBCQ_SHIFT)) & ENET_QOS_MAC_RXQ_CTRL_MCBCQ_MASK) + +#define ENET_QOS_MAC_RXQ_CTRL_PSRQ2_MASK (0xFF0000U) +#define ENET_QOS_MAC_RXQ_CTRL_PSRQ2_SHIFT (16U) +/*! PSRQ2 - Priorities Selected in the Receive Queue 2 */ +#define ENET_QOS_MAC_RXQ_CTRL_PSRQ2(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXQ_CTRL_PSRQ2_SHIFT)) & ENET_QOS_MAC_RXQ_CTRL_PSRQ2_MASK) + +#define ENET_QOS_MAC_RXQ_CTRL_MCBCQEN_MASK (0x100000U) +#define ENET_QOS_MAC_RXQ_CTRL_MCBCQEN_SHIFT (20U) +/*! MCBCQEN - Multicast and Broadcast Queue Enable This bit specifies that Multicast or Broadcast + * packets routing to the Rx Queue is enabled and the Multicast or Broadcast packets must be routed + * to Rx Queue specified in MCBCQ field. + * 0b0..Multicast and Broadcast Queue is disabled + * 0b1..Multicast and Broadcast Queue is enabled + */ +#define ENET_QOS_MAC_RXQ_CTRL_MCBCQEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXQ_CTRL_MCBCQEN_SHIFT)) & ENET_QOS_MAC_RXQ_CTRL_MCBCQEN_MASK) + +#define ENET_QOS_MAC_RXQ_CTRL_TACPQE_MASK (0x200000U) +#define ENET_QOS_MAC_RXQ_CTRL_TACPQE_SHIFT (21U) +/*! TACPQE - Tagged AV Control Packets Queuing Enable. + * 0b0..Tagged AV Control Packets Queuing is disabled + * 0b1..Tagged AV Control Packets Queuing is enabled + */ +#define ENET_QOS_MAC_RXQ_CTRL_TACPQE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXQ_CTRL_TACPQE_SHIFT)) & ENET_QOS_MAC_RXQ_CTRL_TACPQE_MASK) + +#define ENET_QOS_MAC_RXQ_CTRL_TPQC_MASK (0xC00000U) +#define ENET_QOS_MAC_RXQ_CTRL_TPQC_SHIFT (22U) +/*! TPQC - Tagged PTP over Ethernet Packets Queuing Control. */ +#define ENET_QOS_MAC_RXQ_CTRL_TPQC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXQ_CTRL_TPQC_SHIFT)) & ENET_QOS_MAC_RXQ_CTRL_TPQC_MASK) + +#define ENET_QOS_MAC_RXQ_CTRL_FPRQ_MASK (0x7000000U) +#define ENET_QOS_MAC_RXQ_CTRL_FPRQ_SHIFT (24U) +/*! FPRQ - Frame Preemption Residue Queue */ +#define ENET_QOS_MAC_RXQ_CTRL_FPRQ(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXQ_CTRL_FPRQ_SHIFT)) & ENET_QOS_MAC_RXQ_CTRL_FPRQ_MASK) + +#define ENET_QOS_MAC_RXQ_CTRL_PSRQ3_MASK (0xFF000000U) +#define ENET_QOS_MAC_RXQ_CTRL_PSRQ3_SHIFT (24U) +/*! PSRQ3 - Priorities Selected in the Receive Queue 3 */ +#define ENET_QOS_MAC_RXQ_CTRL_PSRQ3(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXQ_CTRL_PSRQ3_SHIFT)) & ENET_QOS_MAC_RXQ_CTRL_PSRQ3_MASK) +/*! @} */ + +/* The count of ENET_QOS_MAC_RXQ_CTRL */ +#define ENET_QOS_MAC_RXQ_CTRL_COUNT (4U) + +/*! @name MAC_INTERRUPT_STATUS - Interrupt Status */ +/*! @{ */ + +#define ENET_QOS_MAC_INTERRUPT_STATUS_RGSMIIIS_MASK (0x1U) +#define ENET_QOS_MAC_INTERRUPT_STATUS_RGSMIIIS_SHIFT (0U) +/*! RGSMIIIS - RGMII or SMII Interrupt Status + * 0b0..RGMII or SMII Interrupt Status is not active + * 0b1..RGMII or SMII Interrupt Status is active + */ +#define ENET_QOS_MAC_INTERRUPT_STATUS_RGSMIIIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INTERRUPT_STATUS_RGSMIIIS_SHIFT)) & ENET_QOS_MAC_INTERRUPT_STATUS_RGSMIIIS_MASK) + +#define ENET_QOS_MAC_INTERRUPT_STATUS_PHYIS_MASK (0x8U) +#define ENET_QOS_MAC_INTERRUPT_STATUS_PHYIS_SHIFT (3U) +/*! PHYIS - PHY Interrupt + * 0b0..PHY Interrupt not detected + * 0b1..PHY Interrupt detected + */ +#define ENET_QOS_MAC_INTERRUPT_STATUS_PHYIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INTERRUPT_STATUS_PHYIS_SHIFT)) & ENET_QOS_MAC_INTERRUPT_STATUS_PHYIS_MASK) + +#define ENET_QOS_MAC_INTERRUPT_STATUS_PMTIS_MASK (0x10U) +#define ENET_QOS_MAC_INTERRUPT_STATUS_PMTIS_SHIFT (4U) +/*! PMTIS - PMT Interrupt Status + * 0b0..PMT Interrupt status not active + * 0b1..PMT Interrupt status active + */ +#define ENET_QOS_MAC_INTERRUPT_STATUS_PMTIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INTERRUPT_STATUS_PMTIS_SHIFT)) & ENET_QOS_MAC_INTERRUPT_STATUS_PMTIS_MASK) + +#define ENET_QOS_MAC_INTERRUPT_STATUS_LPIIS_MASK (0x20U) +#define ENET_QOS_MAC_INTERRUPT_STATUS_LPIIS_SHIFT (5U) +/*! LPIIS - LPI Interrupt Status + * 0b0..LPI Interrupt status not active + * 0b1..LPI Interrupt status active + */ +#define ENET_QOS_MAC_INTERRUPT_STATUS_LPIIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INTERRUPT_STATUS_LPIIS_SHIFT)) & ENET_QOS_MAC_INTERRUPT_STATUS_LPIIS_MASK) + +#define ENET_QOS_MAC_INTERRUPT_STATUS_MMCIS_MASK (0x100U) +#define ENET_QOS_MAC_INTERRUPT_STATUS_MMCIS_SHIFT (8U) +/*! MMCIS - MMC Interrupt Status + * 0b0..MMC Interrupt status not active + * 0b1..MMC Interrupt status active + */ +#define ENET_QOS_MAC_INTERRUPT_STATUS_MMCIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INTERRUPT_STATUS_MMCIS_SHIFT)) & ENET_QOS_MAC_INTERRUPT_STATUS_MMCIS_MASK) + +#define ENET_QOS_MAC_INTERRUPT_STATUS_MMCRXIS_MASK (0x200U) +#define ENET_QOS_MAC_INTERRUPT_STATUS_MMCRXIS_SHIFT (9U) +/*! MMCRXIS - MMC Receive Interrupt Status + * 0b0..MMC Receive Interrupt status not active + * 0b1..MMC Receive Interrupt status active + */ +#define ENET_QOS_MAC_INTERRUPT_STATUS_MMCRXIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INTERRUPT_STATUS_MMCRXIS_SHIFT)) & ENET_QOS_MAC_INTERRUPT_STATUS_MMCRXIS_MASK) + +#define ENET_QOS_MAC_INTERRUPT_STATUS_MMCTXIS_MASK (0x400U) +#define ENET_QOS_MAC_INTERRUPT_STATUS_MMCTXIS_SHIFT (10U) +/*! MMCTXIS - MMC Transmit Interrupt Status + * 0b0..MMC Transmit Interrupt status not active + * 0b1..MMC Transmit Interrupt status active + */ +#define ENET_QOS_MAC_INTERRUPT_STATUS_MMCTXIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INTERRUPT_STATUS_MMCTXIS_SHIFT)) & ENET_QOS_MAC_INTERRUPT_STATUS_MMCTXIS_MASK) + +#define ENET_QOS_MAC_INTERRUPT_STATUS_MMCRXIPIS_MASK (0x800U) +#define ENET_QOS_MAC_INTERRUPT_STATUS_MMCRXIPIS_SHIFT (11U) +/*! MMCRXIPIS - MMC Receive Checksum Offload Interrupt Status + * 0b0..MMC Receive Checksum Offload Interrupt status not active + * 0b1..MMC Receive Checksum Offload Interrupt status active + */ +#define ENET_QOS_MAC_INTERRUPT_STATUS_MMCRXIPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INTERRUPT_STATUS_MMCRXIPIS_SHIFT)) & ENET_QOS_MAC_INTERRUPT_STATUS_MMCRXIPIS_MASK) + +#define ENET_QOS_MAC_INTERRUPT_STATUS_TSIS_MASK (0x1000U) +#define ENET_QOS_MAC_INTERRUPT_STATUS_TSIS_SHIFT (12U) +/*! TSIS - Timestamp Interrupt Status + * 0b0..Timestamp Interrupt status not active + * 0b1..Timestamp Interrupt status active + */ +#define ENET_QOS_MAC_INTERRUPT_STATUS_TSIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INTERRUPT_STATUS_TSIS_SHIFT)) & ENET_QOS_MAC_INTERRUPT_STATUS_TSIS_MASK) + +#define ENET_QOS_MAC_INTERRUPT_STATUS_TXSTSIS_MASK (0x2000U) +#define ENET_QOS_MAC_INTERRUPT_STATUS_TXSTSIS_SHIFT (13U) +/*! TXSTSIS - Transmit Status Interrupt + * 0b0..Transmit Interrupt status not active + * 0b1..Transmit Interrupt status active + */ +#define ENET_QOS_MAC_INTERRUPT_STATUS_TXSTSIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INTERRUPT_STATUS_TXSTSIS_SHIFT)) & ENET_QOS_MAC_INTERRUPT_STATUS_TXSTSIS_MASK) + +#define ENET_QOS_MAC_INTERRUPT_STATUS_RXSTSIS_MASK (0x4000U) +#define ENET_QOS_MAC_INTERRUPT_STATUS_RXSTSIS_SHIFT (14U) +/*! RXSTSIS - Receive Status Interrupt + * 0b0..Receive Interrupt status not active + * 0b1..Receive Interrupt status active + */ +#define ENET_QOS_MAC_INTERRUPT_STATUS_RXSTSIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INTERRUPT_STATUS_RXSTSIS_SHIFT)) & ENET_QOS_MAC_INTERRUPT_STATUS_RXSTSIS_MASK) + +#define ENET_QOS_MAC_INTERRUPT_STATUS_FPEIS_MASK (0x20000U) +#define ENET_QOS_MAC_INTERRUPT_STATUS_FPEIS_SHIFT (17U) +/*! FPEIS - Frame Preemption Interrupt Status + * 0b0..Frame Preemption Interrupt status not active + * 0b1..Frame Preemption Interrupt status active + */ +#define ENET_QOS_MAC_INTERRUPT_STATUS_FPEIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INTERRUPT_STATUS_FPEIS_SHIFT)) & ENET_QOS_MAC_INTERRUPT_STATUS_FPEIS_MASK) + +#define ENET_QOS_MAC_INTERRUPT_STATUS_MDIOIS_MASK (0x40000U) +#define ENET_QOS_MAC_INTERRUPT_STATUS_MDIOIS_SHIFT (18U) +/*! MDIOIS - MDIO Interrupt Status + * 0b0..MDIO Interrupt status not active + * 0b1..MDIO Interrupt status active + */ +#define ENET_QOS_MAC_INTERRUPT_STATUS_MDIOIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INTERRUPT_STATUS_MDIOIS_SHIFT)) & ENET_QOS_MAC_INTERRUPT_STATUS_MDIOIS_MASK) + +#define ENET_QOS_MAC_INTERRUPT_STATUS_MFTIS_MASK (0x80000U) +#define ENET_QOS_MAC_INTERRUPT_STATUS_MFTIS_SHIFT (19U) +/*! MFTIS - MMC FPE Transmit Interrupt Status + * 0b0..MMC FPE Transmit Interrupt status not active + * 0b1..MMC FPE Transmit Interrupt status active + */ +#define ENET_QOS_MAC_INTERRUPT_STATUS_MFTIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INTERRUPT_STATUS_MFTIS_SHIFT)) & ENET_QOS_MAC_INTERRUPT_STATUS_MFTIS_MASK) + +#define ENET_QOS_MAC_INTERRUPT_STATUS_MFRIS_MASK (0x100000U) +#define ENET_QOS_MAC_INTERRUPT_STATUS_MFRIS_SHIFT (20U) +/*! MFRIS - MMC FPE Receive Interrupt Status + * 0b0..MMC FPE Receive Interrupt status not active + * 0b1..MMC FPE Receive Interrupt status active + */ +#define ENET_QOS_MAC_INTERRUPT_STATUS_MFRIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INTERRUPT_STATUS_MFRIS_SHIFT)) & ENET_QOS_MAC_INTERRUPT_STATUS_MFRIS_MASK) +/*! @} */ + +/*! @name MAC_INTERRUPT_ENABLE - Interrupt Enable */ +/*! @{ */ + +#define ENET_QOS_MAC_INTERRUPT_ENABLE_RGSMIIIE_MASK (0x1U) +#define ENET_QOS_MAC_INTERRUPT_ENABLE_RGSMIIIE_SHIFT (0U) +/*! RGSMIIIE - RGMII or SMII Interrupt Enable When this bit is set, it enables the assertion of the + * interrupt signal because of the setting of RGSMIIIS bit in MAC_INTERRUPT_STATUS register. + * 0b0..RGMII or SMII Interrupt is disabled + * 0b1..RGMII or SMII Interrupt is enabled + */ +#define ENET_QOS_MAC_INTERRUPT_ENABLE_RGSMIIIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INTERRUPT_ENABLE_RGSMIIIE_SHIFT)) & ENET_QOS_MAC_INTERRUPT_ENABLE_RGSMIIIE_MASK) + +#define ENET_QOS_MAC_INTERRUPT_ENABLE_PHYIE_MASK (0x8U) +#define ENET_QOS_MAC_INTERRUPT_ENABLE_PHYIE_SHIFT (3U) +/*! PHYIE - PHY Interrupt Enable When this bit is set, it enables the assertion of the interrupt + * signal because of the setting of MAC_INTERRUPT_STATUS[PHYIS]. + * 0b0..PHY Interrupt is disabled + * 0b1..PHY Interrupt is enabled + */ +#define ENET_QOS_MAC_INTERRUPT_ENABLE_PHYIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INTERRUPT_ENABLE_PHYIE_SHIFT)) & ENET_QOS_MAC_INTERRUPT_ENABLE_PHYIE_MASK) + +#define ENET_QOS_MAC_INTERRUPT_ENABLE_PMTIE_MASK (0x10U) +#define ENET_QOS_MAC_INTERRUPT_ENABLE_PMTIE_SHIFT (4U) +/*! PMTIE - PMT Interrupt Enable When this bit is set, it enables the assertion of the interrupt + * signal because of the setting of MAC_INTERRUPT_STATUS[PMTIS]. + * 0b0..PMT Interrupt is disabled + * 0b1..PMT Interrupt is enabled + */ +#define ENET_QOS_MAC_INTERRUPT_ENABLE_PMTIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INTERRUPT_ENABLE_PMTIE_SHIFT)) & ENET_QOS_MAC_INTERRUPT_ENABLE_PMTIE_MASK) + +#define ENET_QOS_MAC_INTERRUPT_ENABLE_LPIIE_MASK (0x20U) +#define ENET_QOS_MAC_INTERRUPT_ENABLE_LPIIE_SHIFT (5U) +/*! LPIIE - LPI Interrupt Enable When this bit is set, it enables the assertion of the interrupt + * signal because of the setting of MAC_INTERRUPT_STATUS[LPIIS]. + * 0b0..LPI Interrupt is disabled + * 0b1..LPI Interrupt is enabled + */ +#define ENET_QOS_MAC_INTERRUPT_ENABLE_LPIIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INTERRUPT_ENABLE_LPIIE_SHIFT)) & ENET_QOS_MAC_INTERRUPT_ENABLE_LPIIE_MASK) + +#define ENET_QOS_MAC_INTERRUPT_ENABLE_TSIE_MASK (0x1000U) +#define ENET_QOS_MAC_INTERRUPT_ENABLE_TSIE_SHIFT (12U) +/*! TSIE - Timestamp Interrupt Enable When this bit is set, it enables the assertion of the + * interrupt signal because of the setting of MAC_INTERRUPT_STATUS[TSIS]. + * 0b0..Timestamp Interrupt is disabled + * 0b1..Timestamp Interrupt is enabled + */ +#define ENET_QOS_MAC_INTERRUPT_ENABLE_TSIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INTERRUPT_ENABLE_TSIE_SHIFT)) & ENET_QOS_MAC_INTERRUPT_ENABLE_TSIE_MASK) + +#define ENET_QOS_MAC_INTERRUPT_ENABLE_TXSTSIE_MASK (0x2000U) +#define ENET_QOS_MAC_INTERRUPT_ENABLE_TXSTSIE_SHIFT (13U) +/*! TXSTSIE - Transmit Status Interrupt Enable When this bit is set, it enables the assertion of the + * interrupt signal because of the setting of MAC_INTERRUPT_STATUS[TXSTSIS]. + * 0b0..Timestamp Status Interrupt is disabled + * 0b1..Timestamp Status Interrupt is enabled + */ +#define ENET_QOS_MAC_INTERRUPT_ENABLE_TXSTSIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INTERRUPT_ENABLE_TXSTSIE_SHIFT)) & ENET_QOS_MAC_INTERRUPT_ENABLE_TXSTSIE_MASK) + +#define ENET_QOS_MAC_INTERRUPT_ENABLE_RXSTSIE_MASK (0x4000U) +#define ENET_QOS_MAC_INTERRUPT_ENABLE_RXSTSIE_SHIFT (14U) +/*! RXSTSIE - Receive Status Interrupt Enable When this bit is set, it enables the assertion of the + * interrupt signal because of the setting of MAC_INTERRUPT_STATUS[RXSTSIS]. + * 0b0..Receive Status Interrupt is disabled + * 0b1..Receive Status Interrupt is enabled + */ +#define ENET_QOS_MAC_INTERRUPT_ENABLE_RXSTSIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INTERRUPT_ENABLE_RXSTSIE_SHIFT)) & ENET_QOS_MAC_INTERRUPT_ENABLE_RXSTSIE_MASK) + +#define ENET_QOS_MAC_INTERRUPT_ENABLE_FPEIE_MASK (0x20000U) +#define ENET_QOS_MAC_INTERRUPT_ENABLE_FPEIE_SHIFT (17U) +/*! FPEIE - Frame Preemption Interrupt Enable When this bit is set, it enables the assertion of the + * interrupt when FPEIS field is set in the MAC_INTERRUPT_STATUS. + * 0b0..Frame Preemption Interrupt is disabled + * 0b1..Frame Preemption Interrupt is enabled + */ +#define ENET_QOS_MAC_INTERRUPT_ENABLE_FPEIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INTERRUPT_ENABLE_FPEIE_SHIFT)) & ENET_QOS_MAC_INTERRUPT_ENABLE_FPEIE_MASK) + +#define ENET_QOS_MAC_INTERRUPT_ENABLE_MDIOIE_MASK (0x40000U) +#define ENET_QOS_MAC_INTERRUPT_ENABLE_MDIOIE_SHIFT (18U) +/*! MDIOIE - MDIO Interrupt Enable When this bit is set, it enables the assertion of the interrupt + * when MDIOIS field is set in the MAC_INTERRUPT_STATUS register. + * 0b0..MDIO Interrupt is disabled + * 0b1..MDIO Interrupt is enabled + */ +#define ENET_QOS_MAC_INTERRUPT_ENABLE_MDIOIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INTERRUPT_ENABLE_MDIOIE_SHIFT)) & ENET_QOS_MAC_INTERRUPT_ENABLE_MDIOIE_MASK) +/*! @} */ + +/*! @name MAC_RX_TX_STATUS - Receive Transmit Status */ +/*! @{ */ + +#define ENET_QOS_MAC_RX_TX_STATUS_TJT_MASK (0x1U) +#define ENET_QOS_MAC_RX_TX_STATUS_TJT_SHIFT (0U) +/*! TJT - Transmit Jabber Timeout This bit indicates that the Transmit Jabber Timer expired which + * happens when the packet size exceeds 2,048 bytes (10,240 bytes when the Jumbo packet is enabled) + * and JD bit is reset in the MAC_CONFIGURATION register. + * 0b0..No Transmit Jabber Timeout + * 0b1..Transmit Jabber Timeout occurred + */ +#define ENET_QOS_MAC_RX_TX_STATUS_TJT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_TX_STATUS_TJT_SHIFT)) & ENET_QOS_MAC_RX_TX_STATUS_TJT_MASK) + +#define ENET_QOS_MAC_RX_TX_STATUS_NCARR_MASK (0x2U) +#define ENET_QOS_MAC_RX_TX_STATUS_NCARR_SHIFT (1U) +/*! NCARR - No Carrier When the DTXSTS bit is set in the MAC_OPERATION_MODE register, this bit + * indicates that the carrier signal from the PHY is not present at the end of preamble transmission. + * 0b0..Carrier is present + * 0b1..No carrier + */ +#define ENET_QOS_MAC_RX_TX_STATUS_NCARR(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_TX_STATUS_NCARR_SHIFT)) & ENET_QOS_MAC_RX_TX_STATUS_NCARR_MASK) + +#define ENET_QOS_MAC_RX_TX_STATUS_LCARR_MASK (0x4U) +#define ENET_QOS_MAC_RX_TX_STATUS_LCARR_SHIFT (2U) +/*! LCARR - Loss of Carrier When the DTXSTS bit is set in the MAC_OPERATION_MODE register, this bit + * indicates that the loss of carrier occurred during packet transmission, that is, the phy_crs_i + * signal was inactive for one or more transmission clock periods during packet transmission. + * 0b0..Carrier is present + * 0b1..Loss of carrier + */ +#define ENET_QOS_MAC_RX_TX_STATUS_LCARR(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_TX_STATUS_LCARR_SHIFT)) & ENET_QOS_MAC_RX_TX_STATUS_LCARR_MASK) + +#define ENET_QOS_MAC_RX_TX_STATUS_EXDEF_MASK (0x8U) +#define ENET_QOS_MAC_RX_TX_STATUS_EXDEF_SHIFT (3U) +/*! EXDEF - Excessive Deferral When the DTXSTS bit is set in the MAC_OPERATION_MODE register and the + * DC bit is set in the MAC_CONFIGURATION register, this bit indicates that the transmission + * ended because of excessive deferral of over 24,288 bit times (155,680 in 1000/2500 Mbps mode or + * when Jumbo packet is enabled). + * 0b0..No Excessive deferral + * 0b1..Excessive deferral + */ +#define ENET_QOS_MAC_RX_TX_STATUS_EXDEF(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_TX_STATUS_EXDEF_SHIFT)) & ENET_QOS_MAC_RX_TX_STATUS_EXDEF_MASK) + +#define ENET_QOS_MAC_RX_TX_STATUS_LCOL_MASK (0x10U) +#define ENET_QOS_MAC_RX_TX_STATUS_LCOL_SHIFT (4U) +/*! LCOL - Late Collision When the DTXSTS bit is set in the MAC_OPERATION_MODE register, this bit + * indicates that the packet transmission aborted because a collision occurred after the collision + * window (512 bytes including Preamble and Carrier Extension in GMII mode). + * 0b0..No collision + * 0b1..Late collision is sensed + */ +#define ENET_QOS_MAC_RX_TX_STATUS_LCOL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_TX_STATUS_LCOL_SHIFT)) & ENET_QOS_MAC_RX_TX_STATUS_LCOL_MASK) + +#define ENET_QOS_MAC_RX_TX_STATUS_EXCOL_MASK (0x20U) +#define ENET_QOS_MAC_RX_TX_STATUS_EXCOL_SHIFT (5U) +/*! EXCOL - Excessive Collisions When the DTXSTS bit is set in the MAC_OPERATION_MODE register, this + * bit indicates that the transmission aborted after 16 successive collisions while attempting + * to transmit the current packet. + * 0b0..No collision + * 0b1..Excessive collision is sensed + */ +#define ENET_QOS_MAC_RX_TX_STATUS_EXCOL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_TX_STATUS_EXCOL_SHIFT)) & ENET_QOS_MAC_RX_TX_STATUS_EXCOL_MASK) + +#define ENET_QOS_MAC_RX_TX_STATUS_RWT_MASK (0x100U) +#define ENET_QOS_MAC_RX_TX_STATUS_RWT_SHIFT (8U) +/*! RWT - Receive Watchdog Timeout This bit is set when a packet with length greater than 2,048 + * bytes is received (10, 240 bytes when Jumbo Packet mode is enabled) and the WD bit is reset in the + * MAC_CONFIGURATION register. + * 0b0..No receive watchdog timeout + * 0b1..Receive watchdog timed out + */ +#define ENET_QOS_MAC_RX_TX_STATUS_RWT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_TX_STATUS_RWT_SHIFT)) & ENET_QOS_MAC_RX_TX_STATUS_RWT_MASK) +/*! @} */ + +/*! @name MAC_PMT_CONTROL_STATUS - PMT Control and Status */ +/*! @{ */ + +#define ENET_QOS_MAC_PMT_CONTROL_STATUS_PWRDWN_MASK (0x1U) +#define ENET_QOS_MAC_PMT_CONTROL_STATUS_PWRDWN_SHIFT (0U) +/*! PWRDWN - Power Down When this bit is set, the MAC receiver drops all received packets until it + * receives the expected magic packet or remote wake-up packet. + * 0b0..Power down is disabled + * 0b1..Power down is enabled + */ +#define ENET_QOS_MAC_PMT_CONTROL_STATUS_PWRDWN(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PMT_CONTROL_STATUS_PWRDWN_SHIFT)) & ENET_QOS_MAC_PMT_CONTROL_STATUS_PWRDWN_MASK) + +#define ENET_QOS_MAC_PMT_CONTROL_STATUS_MGKPKTEN_MASK (0x2U) +#define ENET_QOS_MAC_PMT_CONTROL_STATUS_MGKPKTEN_SHIFT (1U) +/*! MGKPKTEN - Magic Packet Enable When this bit is set, a power management event is generated when the MAC receives a magic packet. + * 0b0..Magic Packet is disabled + * 0b1..Magic Packet is enabled + */ +#define ENET_QOS_MAC_PMT_CONTROL_STATUS_MGKPKTEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PMT_CONTROL_STATUS_MGKPKTEN_SHIFT)) & ENET_QOS_MAC_PMT_CONTROL_STATUS_MGKPKTEN_MASK) + +#define ENET_QOS_MAC_PMT_CONTROL_STATUS_RWKPKTEN_MASK (0x4U) +#define ENET_QOS_MAC_PMT_CONTROL_STATUS_RWKPKTEN_SHIFT (2U) +/*! RWKPKTEN - Remote Wake-Up Packet Enable When this bit is set, a power management event is + * generated when the MAC receives a remote wake-up packet. + * 0b0..Remote wake-up packet is disabled + * 0b1..Remote wake-up packet is enabled + */ +#define ENET_QOS_MAC_PMT_CONTROL_STATUS_RWKPKTEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PMT_CONTROL_STATUS_RWKPKTEN_SHIFT)) & ENET_QOS_MAC_PMT_CONTROL_STATUS_RWKPKTEN_MASK) + +#define ENET_QOS_MAC_PMT_CONTROL_STATUS_MGKPRCVD_MASK (0x20U) +#define ENET_QOS_MAC_PMT_CONTROL_STATUS_MGKPRCVD_SHIFT (5U) +/*! MGKPRCVD - Magic Packet Received When this bit is set, it indicates that the power management + * event is generated because of the reception of a magic packet. + * 0b0..No Magic packet is received + * 0b1..Magic packet is received + */ +#define ENET_QOS_MAC_PMT_CONTROL_STATUS_MGKPRCVD(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PMT_CONTROL_STATUS_MGKPRCVD_SHIFT)) & ENET_QOS_MAC_PMT_CONTROL_STATUS_MGKPRCVD_MASK) + +#define ENET_QOS_MAC_PMT_CONTROL_STATUS_RWKPRCVD_MASK (0x40U) +#define ENET_QOS_MAC_PMT_CONTROL_STATUS_RWKPRCVD_SHIFT (6U) +/*! RWKPRCVD - Remote Wake-Up Packet Received When this bit is set, it indicates that the power + * management event is generated because of the reception of a remote wake-up packet. + * 0b0..Remote wake-up packet is received + * 0b1..Remote wake-up packet is received + */ +#define ENET_QOS_MAC_PMT_CONTROL_STATUS_RWKPRCVD(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PMT_CONTROL_STATUS_RWKPRCVD_SHIFT)) & ENET_QOS_MAC_PMT_CONTROL_STATUS_RWKPRCVD_MASK) + +#define ENET_QOS_MAC_PMT_CONTROL_STATUS_GLBLUCAST_MASK (0x200U) +#define ENET_QOS_MAC_PMT_CONTROL_STATUS_GLBLUCAST_SHIFT (9U) +/*! GLBLUCAST - Global Unicast When this bit set, any unicast packet filtered by the MAC (DAF) + * address recognition is detected as a remote wake-up packet. + * 0b0..Global unicast is disabled + * 0b1..Global unicast is enabled + */ +#define ENET_QOS_MAC_PMT_CONTROL_STATUS_GLBLUCAST(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PMT_CONTROL_STATUS_GLBLUCAST_SHIFT)) & ENET_QOS_MAC_PMT_CONTROL_STATUS_GLBLUCAST_MASK) + +#define ENET_QOS_MAC_PMT_CONTROL_STATUS_RWKPFE_MASK (0x400U) +#define ENET_QOS_MAC_PMT_CONTROL_STATUS_RWKPFE_SHIFT (10U) +/*! RWKPFE - Remote Wake-up Packet Forwarding Enable When this bit is set along with RWKPKTEN, the + * MAC receiver drops all received frames until it receives the expected Wake-up frame. + * 0b0..Remote Wake-up Packet Forwarding is disabled + * 0b1..Remote Wake-up Packet Forwarding is enabled + */ +#define ENET_QOS_MAC_PMT_CONTROL_STATUS_RWKPFE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PMT_CONTROL_STATUS_RWKPFE_SHIFT)) & ENET_QOS_MAC_PMT_CONTROL_STATUS_RWKPFE_MASK) + +#define ENET_QOS_MAC_PMT_CONTROL_STATUS_RWKPTR_MASK (0x1F000000U) +#define ENET_QOS_MAC_PMT_CONTROL_STATUS_RWKPTR_SHIFT (24U) +/*! RWKPTR - Remote Wake-up FIFO Pointer This field gives the current value (0 to 7, 15, or 31 when + * 4, 8, or 16 Remote Wake-up Packet Filters are selected) of the Remote Wake-up Packet Filter + * register pointer. + */ +#define ENET_QOS_MAC_PMT_CONTROL_STATUS_RWKPTR(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PMT_CONTROL_STATUS_RWKPTR_SHIFT)) & ENET_QOS_MAC_PMT_CONTROL_STATUS_RWKPTR_MASK) + +#define ENET_QOS_MAC_PMT_CONTROL_STATUS_RWKFILTRST_MASK (0x80000000U) +#define ENET_QOS_MAC_PMT_CONTROL_STATUS_RWKFILTRST_SHIFT (31U) +/*! RWKFILTRST - Remote Wake-Up Packet Filter Register Pointer Reset When this bit is set, the + * remote wake-up packet filter register pointer is reset to 3'b000. + * 0b0..Remote Wake-Up Packet Filter Register Pointer is not Reset + * 0b1..Remote Wake-Up Packet Filter Register Pointer is Reset + */ +#define ENET_QOS_MAC_PMT_CONTROL_STATUS_RWKFILTRST(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PMT_CONTROL_STATUS_RWKFILTRST_SHIFT)) & ENET_QOS_MAC_PMT_CONTROL_STATUS_RWKFILTRST_MASK) +/*! @} */ + +/*! @name MAC_RWK_PACKET_FILTER - Remote Wakeup Filter */ +/*! @{ */ + +#define ENET_QOS_MAC_RWK_PACKET_FILTER_WKUPFRMFTR_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_RWK_PACKET_FILTER_WKUPFRMFTR_SHIFT (0U) +/*! WKUPFRMFTR - RWK Packet Filter This field contains the various controls of RWK Packet filter. */ +#define ENET_QOS_MAC_RWK_PACKET_FILTER_WKUPFRMFTR(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RWK_PACKET_FILTER_WKUPFRMFTR_SHIFT)) & ENET_QOS_MAC_RWK_PACKET_FILTER_WKUPFRMFTR_MASK) +/*! @} */ + +/*! @name MAC_LPI_CONTROL_STATUS - LPI Control and Status */ +/*! @{ */ + +#define ENET_QOS_MAC_LPI_CONTROL_STATUS_TLPIEN_MASK (0x1U) +#define ENET_QOS_MAC_LPI_CONTROL_STATUS_TLPIEN_SHIFT (0U) +/*! TLPIEN - Transmit LPI Entry When this bit is set, it indicates that the MAC Transmitter has + * entered the LPI state because of the setting of the LPIEN bit. + * 0b0..Transmit LPI entry not detected + * 0b1..Transmit LPI entry detected + */ +#define ENET_QOS_MAC_LPI_CONTROL_STATUS_TLPIEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LPI_CONTROL_STATUS_TLPIEN_SHIFT)) & ENET_QOS_MAC_LPI_CONTROL_STATUS_TLPIEN_MASK) + +#define ENET_QOS_MAC_LPI_CONTROL_STATUS_TLPIEX_MASK (0x2U) +#define ENET_QOS_MAC_LPI_CONTROL_STATUS_TLPIEX_SHIFT (1U) +/*! TLPIEX - Transmit LPI Exit When this bit is set, it indicates that the MAC transmitter exited + * the LPI state after the application cleared the LPIEN bit and the LPI TW Timer has expired. + * 0b0..Transmit LPI exit not detected + * 0b1..Transmit LPI exit detected + */ +#define ENET_QOS_MAC_LPI_CONTROL_STATUS_TLPIEX(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LPI_CONTROL_STATUS_TLPIEX_SHIFT)) & ENET_QOS_MAC_LPI_CONTROL_STATUS_TLPIEX_MASK) + +#define ENET_QOS_MAC_LPI_CONTROL_STATUS_RLPIEN_MASK (0x4U) +#define ENET_QOS_MAC_LPI_CONTROL_STATUS_RLPIEN_SHIFT (2U) +/*! RLPIEN - Receive LPI Entry When this bit is set, it indicates that the MAC Receiver has received + * an LPI pattern and entered the LPI state. + * 0b0..Receive LPI entry not detected + * 0b1..Receive LPI entry detected + */ +#define ENET_QOS_MAC_LPI_CONTROL_STATUS_RLPIEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LPI_CONTROL_STATUS_RLPIEN_SHIFT)) & ENET_QOS_MAC_LPI_CONTROL_STATUS_RLPIEN_MASK) + +#define ENET_QOS_MAC_LPI_CONTROL_STATUS_RLPIEX_MASK (0x8U) +#define ENET_QOS_MAC_LPI_CONTROL_STATUS_RLPIEX_SHIFT (3U) +/*! RLPIEX - Receive LPI Exit When this bit is set, it indicates that the MAC Receiver has stopped + * receiving the LPI pattern on the GMII interface, exited the LPI state, and resumed the normal + * reception. + * 0b0..Receive LPI exit not detected + * 0b1..Receive LPI exit detected + */ +#define ENET_QOS_MAC_LPI_CONTROL_STATUS_RLPIEX(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LPI_CONTROL_STATUS_RLPIEX_SHIFT)) & ENET_QOS_MAC_LPI_CONTROL_STATUS_RLPIEX_MASK) + +#define ENET_QOS_MAC_LPI_CONTROL_STATUS_TLPIST_MASK (0x100U) +#define ENET_QOS_MAC_LPI_CONTROL_STATUS_TLPIST_SHIFT (8U) +/*! TLPIST - Transmit LPI State When this bit is set, it indicates that the MAC is transmitting the + * LPI pattern on the GMII interface. + * 0b0..Transmit LPI state not detected + * 0b1..Transmit LPI state detected + */ +#define ENET_QOS_MAC_LPI_CONTROL_STATUS_TLPIST(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LPI_CONTROL_STATUS_TLPIST_SHIFT)) & ENET_QOS_MAC_LPI_CONTROL_STATUS_TLPIST_MASK) + +#define ENET_QOS_MAC_LPI_CONTROL_STATUS_RLPIST_MASK (0x200U) +#define ENET_QOS_MAC_LPI_CONTROL_STATUS_RLPIST_SHIFT (9U) +/*! RLPIST - Receive LPI State When this bit is set, it indicates that the MAC is receiving the LPI pattern on the GMII interface. + * 0b0..Receive LPI state not detected + * 0b1..Receive LPI state detected + */ +#define ENET_QOS_MAC_LPI_CONTROL_STATUS_RLPIST(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LPI_CONTROL_STATUS_RLPIST_SHIFT)) & ENET_QOS_MAC_LPI_CONTROL_STATUS_RLPIST_MASK) + +#define ENET_QOS_MAC_LPI_CONTROL_STATUS_LPIEN_MASK (0x10000U) +#define ENET_QOS_MAC_LPI_CONTROL_STATUS_LPIEN_SHIFT (16U) +/*! LPIEN - LPI Enable When this bit is set, it instructs the MAC Transmitter to enter the LPI state. + * 0b0..LPI state is disabled + * 0b1..LPI state is enabled + */ +#define ENET_QOS_MAC_LPI_CONTROL_STATUS_LPIEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LPI_CONTROL_STATUS_LPIEN_SHIFT)) & ENET_QOS_MAC_LPI_CONTROL_STATUS_LPIEN_MASK) + +#define ENET_QOS_MAC_LPI_CONTROL_STATUS_PLS_MASK (0x20000U) +#define ENET_QOS_MAC_LPI_CONTROL_STATUS_PLS_SHIFT (17U) +/*! PLS - PHY Link Status This bit indicates the link status of the PHY. + * 0b0..link is down + * 0b1..link is okay (UP) + */ +#define ENET_QOS_MAC_LPI_CONTROL_STATUS_PLS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LPI_CONTROL_STATUS_PLS_SHIFT)) & ENET_QOS_MAC_LPI_CONTROL_STATUS_PLS_MASK) + +#define ENET_QOS_MAC_LPI_CONTROL_STATUS_PLSEN_MASK (0x40000U) +#define ENET_QOS_MAC_LPI_CONTROL_STATUS_PLSEN_SHIFT (18U) +/*! PLSEN - PHY Link Status Enable This bit enables the link status received on the RGMII, SGMII, or + * SMII Receive paths to be used for activating the LPI LS TIMER. + * 0b0..PHY Link Status is disabled + * 0b1..PHY Link Status is enabled + */ +#define ENET_QOS_MAC_LPI_CONTROL_STATUS_PLSEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LPI_CONTROL_STATUS_PLSEN_SHIFT)) & ENET_QOS_MAC_LPI_CONTROL_STATUS_PLSEN_MASK) + +#define ENET_QOS_MAC_LPI_CONTROL_STATUS_LPITXA_MASK (0x80000U) +#define ENET_QOS_MAC_LPI_CONTROL_STATUS_LPITXA_SHIFT (19U) +/*! LPITXA - LPI Tx Automate This bit controls the behavior of the MAC when it is entering or coming + * out of the LPI mode on the Transmit side. + * 0b0..LPI Tx Automate is disabled + * 0b1..LPI Tx Automate is enabled + */ +#define ENET_QOS_MAC_LPI_CONTROL_STATUS_LPITXA(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LPI_CONTROL_STATUS_LPITXA_SHIFT)) & ENET_QOS_MAC_LPI_CONTROL_STATUS_LPITXA_MASK) + +#define ENET_QOS_MAC_LPI_CONTROL_STATUS_LPIATE_MASK (0x100000U) +#define ENET_QOS_MAC_LPI_CONTROL_STATUS_LPIATE_SHIFT (20U) +/*! LPIATE - LPI Timer Enable This bit controls the automatic entry of the MAC Transmitter into and exit out of the LPI state. + * 0b0..LPI Timer is disabled + * 0b1..LPI Timer is enabled + */ +#define ENET_QOS_MAC_LPI_CONTROL_STATUS_LPIATE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LPI_CONTROL_STATUS_LPIATE_SHIFT)) & ENET_QOS_MAC_LPI_CONTROL_STATUS_LPIATE_MASK) + +#define ENET_QOS_MAC_LPI_CONTROL_STATUS_LPITCSE_MASK (0x200000U) +#define ENET_QOS_MAC_LPI_CONTROL_STATUS_LPITCSE_SHIFT (21U) +/*! LPITCSE - LPI Tx Clock Stop Enable When this bit is set, the MAC asserts + * sbd_tx_clk_gating_ctrl_o signal high after it enters Tx LPI mode to indicate that the Tx clock to MAC can be stopped. + * 0b0..LPI Tx Clock Stop is disabled + * 0b1..LPI Tx Clock Stop is enabled + */ +#define ENET_QOS_MAC_LPI_CONTROL_STATUS_LPITCSE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LPI_CONTROL_STATUS_LPITCSE_SHIFT)) & ENET_QOS_MAC_LPI_CONTROL_STATUS_LPITCSE_MASK) +/*! @} */ + +/*! @name MAC_LPI_TIMERS_CONTROL - LPI Timers Control */ +/*! @{ */ + +#define ENET_QOS_MAC_LPI_TIMERS_CONTROL_TWT_MASK (0xFFFFU) +#define ENET_QOS_MAC_LPI_TIMERS_CONTROL_TWT_SHIFT (0U) +/*! TWT - LPI TW Timer This field specifies the minimum time (in microseconds) for which the MAC + * waits after it stops transmitting the LPI pattern to the PHY and before it resumes the normal + * transmission. + */ +#define ENET_QOS_MAC_LPI_TIMERS_CONTROL_TWT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LPI_TIMERS_CONTROL_TWT_SHIFT)) & ENET_QOS_MAC_LPI_TIMERS_CONTROL_TWT_MASK) + +#define ENET_QOS_MAC_LPI_TIMERS_CONTROL_LST_MASK (0x3FF0000U) +#define ENET_QOS_MAC_LPI_TIMERS_CONTROL_LST_SHIFT (16U) +/*! LST - LPI LS Timer This field specifies the minimum time (in milliseconds) for which the link + * status from the PHY should be up (OKAY) before the LPI pattern can be transmitted to the PHY. + */ +#define ENET_QOS_MAC_LPI_TIMERS_CONTROL_LST(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LPI_TIMERS_CONTROL_LST_SHIFT)) & ENET_QOS_MAC_LPI_TIMERS_CONTROL_LST_MASK) +/*! @} */ + +/*! @name MAC_LPI_ENTRY_TIMER - Tx LPI Entry Timer Control */ +/*! @{ */ + +#define ENET_QOS_MAC_LPI_ENTRY_TIMER_LPIET_MASK (0xFFFF8U) +#define ENET_QOS_MAC_LPI_ENTRY_TIMER_LPIET_SHIFT (3U) +/*! LPIET - LPI Entry Timer This field specifies the time in microseconds the MAC waits to enter LPI + * mode, after it has transmitted all the frames. + */ +#define ENET_QOS_MAC_LPI_ENTRY_TIMER_LPIET(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LPI_ENTRY_TIMER_LPIET_SHIFT)) & ENET_QOS_MAC_LPI_ENTRY_TIMER_LPIET_MASK) +/*! @} */ + +/*! @name MAC_ONEUS_TIC_COUNTER - One-microsecond Reference Timer */ +/*! @{ */ + +#define ENET_QOS_MAC_ONEUS_TIC_COUNTER_TIC_1US_CNTR_MASK (0xFFFU) +#define ENET_QOS_MAC_ONEUS_TIC_COUNTER_TIC_1US_CNTR_SHIFT (0U) +/*! TIC_1US_CNTR - 1US TIC Counter The application must program this counter so that the number of clock cycles of CSR clock is 1us. */ +#define ENET_QOS_MAC_ONEUS_TIC_COUNTER_TIC_1US_CNTR(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_ONEUS_TIC_COUNTER_TIC_1US_CNTR_SHIFT)) & ENET_QOS_MAC_ONEUS_TIC_COUNTER_TIC_1US_CNTR_MASK) +/*! @} */ + +/*! @name MAC_PHYIF_CONTROL_STATUS - PHY Interface Control and Status */ +/*! @{ */ + +#define ENET_QOS_MAC_PHYIF_CONTROL_STATUS_TC_MASK (0x1U) +#define ENET_QOS_MAC_PHYIF_CONTROL_STATUS_TC_SHIFT (0U) +/*! TC - Transmit Configuration in RGMII, SGMII, or SMII When set, this bit enables the transmission + * of duplex mode, link speed, and link up or down information to the PHY in the RGMII, SMII, or + * SGMII port. + * 0b0..Disable Transmit Configuration in RGMII, SGMII, or SMII + * 0b1..Enable Transmit Configuration in RGMII, SGMII, or SMII + */ +#define ENET_QOS_MAC_PHYIF_CONTROL_STATUS_TC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PHYIF_CONTROL_STATUS_TC_SHIFT)) & ENET_QOS_MAC_PHYIF_CONTROL_STATUS_TC_MASK) + +#define ENET_QOS_MAC_PHYIF_CONTROL_STATUS_LUD_MASK (0x2U) +#define ENET_QOS_MAC_PHYIF_CONTROL_STATUS_LUD_SHIFT (1U) +/*! LUD - Link Up or Down This bit indicates whether the link is up or down during transmission of + * configuration in the RGMII, SGMII, or SMII interface. + * 0b0..Link down + * 0b1..Link up + */ +#define ENET_QOS_MAC_PHYIF_CONTROL_STATUS_LUD(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PHYIF_CONTROL_STATUS_LUD_SHIFT)) & ENET_QOS_MAC_PHYIF_CONTROL_STATUS_LUD_MASK) + +#define ENET_QOS_MAC_PHYIF_CONTROL_STATUS_LNKMOD_MASK (0x10000U) +#define ENET_QOS_MAC_PHYIF_CONTROL_STATUS_LNKMOD_SHIFT (16U) +/*! LNKMOD - Link Mode This bit indicates the current mode of operation of the link. + * 0b0..Half-duplex mode + * 0b1..Full-duplex mode + */ +#define ENET_QOS_MAC_PHYIF_CONTROL_STATUS_LNKMOD(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PHYIF_CONTROL_STATUS_LNKMOD_SHIFT)) & ENET_QOS_MAC_PHYIF_CONTROL_STATUS_LNKMOD_MASK) + +#define ENET_QOS_MAC_PHYIF_CONTROL_STATUS_LNKSPEED_MASK (0x60000U) +#define ENET_QOS_MAC_PHYIF_CONTROL_STATUS_LNKSPEED_SHIFT (17U) +/*! LNKSPEED - Link Speed This bit indicates the current speed of the link. + * 0b00..2.5 MHz + * 0b01..25 MHz + * 0b10..125 MHz + * 0b11..Reserved + */ +#define ENET_QOS_MAC_PHYIF_CONTROL_STATUS_LNKSPEED(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PHYIF_CONTROL_STATUS_LNKSPEED_SHIFT)) & ENET_QOS_MAC_PHYIF_CONTROL_STATUS_LNKSPEED_MASK) + +#define ENET_QOS_MAC_PHYIF_CONTROL_STATUS_LNKSTS_MASK (0x80000U) +#define ENET_QOS_MAC_PHYIF_CONTROL_STATUS_LNKSTS_SHIFT (19U) +/*! LNKSTS - Link Status This bit indicates whether the link is up (1'b1) or down (1'b0). + * 0b0..Link down + * 0b1..Link up + */ +#define ENET_QOS_MAC_PHYIF_CONTROL_STATUS_LNKSTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PHYIF_CONTROL_STATUS_LNKSTS_SHIFT)) & ENET_QOS_MAC_PHYIF_CONTROL_STATUS_LNKSTS_MASK) +/*! @} */ + +/*! @name MAC_VERSION - MAC Version */ +/*! @{ */ + +#define ENET_QOS_MAC_VERSION_SNPSVER_MASK (0xFFU) +#define ENET_QOS_MAC_VERSION_SNPSVER_SHIFT (0U) +/*! SNPSVER - Synopsys-defined Version */ +#define ENET_QOS_MAC_VERSION_SNPSVER(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VERSION_SNPSVER_SHIFT)) & ENET_QOS_MAC_VERSION_SNPSVER_MASK) + +#define ENET_QOS_MAC_VERSION_USERVER_MASK (0xFF00U) +#define ENET_QOS_MAC_VERSION_USERVER_SHIFT (8U) +/*! USERVER - User-defined Version (8'h10) */ +#define ENET_QOS_MAC_VERSION_USERVER(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VERSION_USERVER_SHIFT)) & ENET_QOS_MAC_VERSION_USERVER_MASK) +/*! @} */ + +/*! @name MAC_DEBUG - MAC Debug */ +/*! @{ */ + +#define ENET_QOS_MAC_DEBUG_RPESTS_MASK (0x1U) +#define ENET_QOS_MAC_DEBUG_RPESTS_SHIFT (0U) +/*! RPESTS - MAC GMII Receive Protocol Engine Status When this bit is set, it indicates that the MAC + * GMII receive protocol engine is actively receiving data, and it is not in the Idle state. + * 0b0..MAC GMII Receive Protocol Engine Status not detected + * 0b1..MAC GMII Receive Protocol Engine Status detected + */ +#define ENET_QOS_MAC_DEBUG_RPESTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_DEBUG_RPESTS_SHIFT)) & ENET_QOS_MAC_DEBUG_RPESTS_MASK) + +#define ENET_QOS_MAC_DEBUG_RFCFCSTS_MASK (0x6U) +#define ENET_QOS_MAC_DEBUG_RFCFCSTS_SHIFT (1U) +/*! RFCFCSTS - MAC Receive Packet Controller FIFO Status When this bit is set, this field indicates + * the active state of the small FIFO Read and Write controllers of the MAC Receive Packet + * Controller module. + */ +#define ENET_QOS_MAC_DEBUG_RFCFCSTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_DEBUG_RFCFCSTS_SHIFT)) & ENET_QOS_MAC_DEBUG_RFCFCSTS_MASK) + +#define ENET_QOS_MAC_DEBUG_TPESTS_MASK (0x10000U) +#define ENET_QOS_MAC_DEBUG_TPESTS_SHIFT (16U) +/*! TPESTS - MAC GMII or MII Transmit Protocol Engine Status When this bit is set, it indicates that + * the MAC GMII or MII transmit protocol engine is actively transmitting data, and it is not in + * the Idle state. + * 0b0..MAC GMII Transmit Protocol Engine Status not detected + * 0b1..MAC GMII Transmit Protocol Engine Status detected + */ +#define ENET_QOS_MAC_DEBUG_TPESTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_DEBUG_TPESTS_SHIFT)) & ENET_QOS_MAC_DEBUG_TPESTS_MASK) + +#define ENET_QOS_MAC_DEBUG_TFCSTS_MASK (0x60000U) +#define ENET_QOS_MAC_DEBUG_TFCSTS_SHIFT (17U) +/*! TFCSTS - MAC Transmit Packet Controller Status This field indicates the state of the MAC Transmit Packet Controller module. + * 0b00..Idle state + * 0b01..Waiting for one of the following: Status of the previous packet OR IPG or back off period to be over + * 0b10..Generating and transmitting a Pause control packet (in full-duplex mode) + * 0b11..Transferring input packet for transmission + */ +#define ENET_QOS_MAC_DEBUG_TFCSTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_DEBUG_TFCSTS_SHIFT)) & ENET_QOS_MAC_DEBUG_TFCSTS_MASK) +/*! @} */ + +/*! @name MAC_HW_FEAT - Optional Features or Functions 0..Optional Features or Functions 3 */ +/*! @{ */ + +#define ENET_QOS_MAC_HW_FEAT_MIISEL_MASK (0x1U) +#define ENET_QOS_MAC_HW_FEAT_MIISEL_SHIFT (0U) +/*! MIISEL - 10 or 100 Mbps Support This bit is set to 1 when 10/100 Mbps is selected as the Mode of Operation + * 0b0..No 10 or 100 Mbps support + * 0b1..10 or 100 Mbps support + */ +#define ENET_QOS_MAC_HW_FEAT_MIISEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_MIISEL_SHIFT)) & ENET_QOS_MAC_HW_FEAT_MIISEL_MASK) + +#define ENET_QOS_MAC_HW_FEAT_NRVF_MASK (0x7U) +#define ENET_QOS_MAC_HW_FEAT_NRVF_SHIFT (0U) +/*! NRVF - Number of Extended VLAN Tag Filters Enabled This field indicates the Number of Extended VLAN Tag Filters selected: + * 0b000..No Extended Rx VLAN Filters + * 0b001..4 Extended Rx VLAN Filters + * 0b010..8 Extended Rx VLAN Filters + * 0b011..16 Extended Rx VLAN Filters + * 0b100..24 Extended Rx VLAN Filters + * 0b101..32 Extended Rx VLAN Filters + * 0b110..Reserved + */ +#define ENET_QOS_MAC_HW_FEAT_NRVF(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_NRVF_SHIFT)) & ENET_QOS_MAC_HW_FEAT_NRVF_MASK) + +#define ENET_QOS_MAC_HW_FEAT_RXFIFOSIZE_MASK (0x1FU) +#define ENET_QOS_MAC_HW_FEAT_RXFIFOSIZE_SHIFT (0U) +/*! RXFIFOSIZE - MTL Receive FIFO Size This field contains the configured value of MTL Rx FIFO in + * bytes expressed as Log to base 2 minus 7, that is, Log2(RXFIFO_SIZE) -7: + * 0b00000..128 bytes + * 0b00001..256 bytes + * 0b00010..512 bytes + * 0b00011..1024 bytes + * 0b00100..2048 bytes + * 0b00101..4096 bytes + * 0b00110..8192 bytes + * 0b00111..16384 bytes + * 0b01000..32 KB + * 0b01001..64 KB + * 0b01010..128 KB + * 0b01011..256 KB + * 0b01100..Reserved + */ +#define ENET_QOS_MAC_HW_FEAT_RXFIFOSIZE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_RXFIFOSIZE_SHIFT)) & ENET_QOS_MAC_HW_FEAT_RXFIFOSIZE_MASK) + +#define ENET_QOS_MAC_HW_FEAT_RXQCNT_MASK (0xFU) +#define ENET_QOS_MAC_HW_FEAT_RXQCNT_SHIFT (0U) +/*! RXQCNT - Number of MTL Receive Queues This field indicates the number of MTL Receive queues: + * 0b0000..1 MTL Rx Queue + * 0b0001..2 MTL Rx Queues + * 0b0010..3 MTL Rx Queues + * 0b0011..4 MTL Rx Queues + * 0b0100..5 MTL Rx Queues + * 0b0101..Reserved + * 0b0110..Reserved + * 0b0111..Reserved + */ +#define ENET_QOS_MAC_HW_FEAT_RXQCNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_RXQCNT_SHIFT)) & ENET_QOS_MAC_HW_FEAT_RXQCNT_MASK) + +#define ENET_QOS_MAC_HW_FEAT_GMIISEL_MASK (0x2U) +#define ENET_QOS_MAC_HW_FEAT_GMIISEL_SHIFT (1U) +/*! GMIISEL - 1000 Mbps Support This bit is set to 1 when 1000 Mbps is selected as the Mode of Operation + * 0b0..No 1000 Mbps support + * 0b1..1000 Mbps support + */ +#define ENET_QOS_MAC_HW_FEAT_GMIISEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_GMIISEL_SHIFT)) & ENET_QOS_MAC_HW_FEAT_GMIISEL_MASK) + +#define ENET_QOS_MAC_HW_FEAT_HDSEL_MASK (0x4U) +#define ENET_QOS_MAC_HW_FEAT_HDSEL_SHIFT (2U) +/*! HDSEL - Half-duplex Support This bit is set to 1 when the half-duplex mode is selected + * 0b0..No Half-duplex support + * 0b1..Half-duplex support + */ +#define ENET_QOS_MAC_HW_FEAT_HDSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_HDSEL_SHIFT)) & ENET_QOS_MAC_HW_FEAT_HDSEL_MASK) + +#define ENET_QOS_MAC_HW_FEAT_PCSSEL_MASK (0x8U) +#define ENET_QOS_MAC_HW_FEAT_PCSSEL_SHIFT (3U) +/*! PCSSEL - PCS Registers (TBI, SGMII, or RTBI PHY interface) This bit is set to 1 when the TBI, + * SGMII, or RTBI PHY interface option is selected + * 0b0..No PCS Registers (TBI, SGMII, or RTBI PHY interface) + * 0b1..PCS Registers (TBI, SGMII, or RTBI PHY interface) + */ +#define ENET_QOS_MAC_HW_FEAT_PCSSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_PCSSEL_SHIFT)) & ENET_QOS_MAC_HW_FEAT_PCSSEL_MASK) + +#define ENET_QOS_MAC_HW_FEAT_CBTISEL_MASK (0x10U) +#define ENET_QOS_MAC_HW_FEAT_CBTISEL_SHIFT (4U) +/*! CBTISEL - Queue/Channel based VLAN tag insertion on Tx Enable This bit is set to 1 when the + * Enable Queue/Channel based VLAN tag insertion on Tx Feature is selected. + * 0b0..Enable Queue/Channel based VLAN tag insertion on Tx feature is not selected + * 0b1..Enable Queue/Channel based VLAN tag insertion on Tx feature is selected + */ +#define ENET_QOS_MAC_HW_FEAT_CBTISEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_CBTISEL_SHIFT)) & ENET_QOS_MAC_HW_FEAT_CBTISEL_MASK) + +#define ENET_QOS_MAC_HW_FEAT_VLHASH_MASK (0x10U) +#define ENET_QOS_MAC_HW_FEAT_VLHASH_SHIFT (4U) +/*! VLHASH - VLAN Hash Filter Selected This bit is set to 1 when the Enable VLAN Hash Table Based Filtering option is selected + * 0b0..VLAN Hash Filter not selected + * 0b1..VLAN Hash Filter selected + */ +#define ENET_QOS_MAC_HW_FEAT_VLHASH(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_VLHASH_SHIFT)) & ENET_QOS_MAC_HW_FEAT_VLHASH_MASK) + +#define ENET_QOS_MAC_HW_FEAT_DVLAN_MASK (0x20U) +#define ENET_QOS_MAC_HW_FEAT_DVLAN_SHIFT (5U) +/*! DVLAN - Double VLAN Tag Processing Selected This bit is set to 1 when the Enable Double VLAN Processing Feature is selected. + * 0b0..Double VLAN option is not selected + * 0b1..Double VLAN option is selected + */ +#define ENET_QOS_MAC_HW_FEAT_DVLAN(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_DVLAN_SHIFT)) & ENET_QOS_MAC_HW_FEAT_DVLAN_MASK) + +#define ENET_QOS_MAC_HW_FEAT_SMASEL_MASK (0x20U) +#define ENET_QOS_MAC_HW_FEAT_SMASEL_SHIFT (5U) +/*! SMASEL - SMA (MDIO) Interface This bit is set to 1 when the Enable Station Management (MDIO Interface) option is selected + * 0b0..SMA (MDIO) Interface not selected + * 0b1..SMA (MDIO) Interface selected + */ +#define ENET_QOS_MAC_HW_FEAT_SMASEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_SMASEL_SHIFT)) & ENET_QOS_MAC_HW_FEAT_SMASEL_MASK) + +#define ENET_QOS_MAC_HW_FEAT_SPRAM_MASK (0x20U) +#define ENET_QOS_MAC_HW_FEAT_SPRAM_SHIFT (5U) +/*! SPRAM - Single Port RAM Enable This bit is set to 1 when the Use single port RAM Feature is selected. + * 0b0..Single Port RAM feature is not selected + * 0b1..Single Port RAM feature is selected + */ +#define ENET_QOS_MAC_HW_FEAT_SPRAM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_SPRAM_SHIFT)) & ENET_QOS_MAC_HW_FEAT_SPRAM_MASK) + +#define ENET_QOS_MAC_HW_FEAT_RWKSEL_MASK (0x40U) +#define ENET_QOS_MAC_HW_FEAT_RWKSEL_SHIFT (6U) +/*! RWKSEL - PMT Remote Wake-up Packet Enable This bit is set to 1 when the Enable Remote Wake-Up Packet Detection option is selected + * 0b0..PMT Remote Wake-up Packet Enable option is not selected + * 0b1..PMT Remote Wake-up Packet Enable option is selected + */ +#define ENET_QOS_MAC_HW_FEAT_RWKSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_RWKSEL_SHIFT)) & ENET_QOS_MAC_HW_FEAT_RWKSEL_MASK) + +#define ENET_QOS_MAC_HW_FEAT_TXFIFOSIZE_MASK (0x7C0U) +#define ENET_QOS_MAC_HW_FEAT_TXFIFOSIZE_SHIFT (6U) +/*! TXFIFOSIZE - MTL Transmit FIFO Size This field contains the configured value of MTL Tx FIFO in + * bytes expressed as Log to base 2 minus 7, that is, Log2(TXFIFO_SIZE) -7: + * 0b00000..128 bytes + * 0b00001..256 bytes + * 0b00010..512 bytes + * 0b00011..1024 bytes + * 0b00100..2048 bytes + * 0b00101..4096 bytes + * 0b00110..8192 bytes + * 0b00111..16384 bytes + * 0b01000..32 KB + * 0b01001..64 KB + * 0b01010..128 KB + * 0b01011..Reserved + */ +#define ENET_QOS_MAC_HW_FEAT_TXFIFOSIZE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_TXFIFOSIZE_SHIFT)) & ENET_QOS_MAC_HW_FEAT_TXFIFOSIZE_MASK) + +#define ENET_QOS_MAC_HW_FEAT_TXQCNT_MASK (0x3C0U) +#define ENET_QOS_MAC_HW_FEAT_TXQCNT_SHIFT (6U) +/*! TXQCNT - Number of MTL Transmit Queues This field indicates the number of MTL Transmit queues: + * 0b0000..1 MTL Tx Queue + * 0b0001..2 MTL Tx Queues + * 0b0010..3 MTL Tx Queues + * 0b0011..4 MTL Tx Queues + * 0b0100..5 MTL Tx Queues + * 0b0101..Reserved + * 0b0110..Reserved + * 0b0111..Reserved + */ +#define ENET_QOS_MAC_HW_FEAT_TXQCNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_TXQCNT_SHIFT)) & ENET_QOS_MAC_HW_FEAT_TXQCNT_MASK) + +#define ENET_QOS_MAC_HW_FEAT_MGKSEL_MASK (0x80U) +#define ENET_QOS_MAC_HW_FEAT_MGKSEL_SHIFT (7U) +/*! MGKSEL - PMT Magic Packet Enable This bit is set to 1 when the Enable Magic Packet Detection option is selected + * 0b0..PMT Magic Packet Enable option is not selected + * 0b1..PMT Magic Packet Enable option is selected + */ +#define ENET_QOS_MAC_HW_FEAT_MGKSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_MGKSEL_SHIFT)) & ENET_QOS_MAC_HW_FEAT_MGKSEL_MASK) + +#define ENET_QOS_MAC_HW_FEAT_MMCSEL_MASK (0x100U) +#define ENET_QOS_MAC_HW_FEAT_MMCSEL_SHIFT (8U) +/*! MMCSEL - RMON Module Enable This bit is set to 1 when the Enable MAC Management Counters (MMC) option is selected + * 0b0..RMON Module Enable option is not selected + * 0b1..RMON Module Enable option is selected + */ +#define ENET_QOS_MAC_HW_FEAT_MMCSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_MMCSEL_SHIFT)) & ENET_QOS_MAC_HW_FEAT_MMCSEL_MASK) + +#define ENET_QOS_MAC_HW_FEAT_ARPOFFSEL_MASK (0x200U) +#define ENET_QOS_MAC_HW_FEAT_ARPOFFSEL_SHIFT (9U) +/*! ARPOFFSEL - ARP Offload Enabled This bit is set to 1 when the Enable IPv4 ARP Offload option is selected + * 0b0..ARP Offload Enable option is not selected + * 0b1..ARP Offload Enable option is selected + */ +#define ENET_QOS_MAC_HW_FEAT_ARPOFFSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_ARPOFFSEL_SHIFT)) & ENET_QOS_MAC_HW_FEAT_ARPOFFSEL_MASK) + +#define ENET_QOS_MAC_HW_FEAT_PDUPSEL_MASK (0x200U) +#define ENET_QOS_MAC_HW_FEAT_PDUPSEL_SHIFT (9U) +/*! PDUPSEL - Broadcast/Multicast Packet Duplication This bit is set to 1 when the + * Broadcast/Multicast Packet Duplication feature is selected. + * 0b0..Broadcast/Multicast Packet Duplication feature is not selected + * 0b1..Broadcast/Multicast Packet Duplication feature is selected + */ +#define ENET_QOS_MAC_HW_FEAT_PDUPSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_PDUPSEL_SHIFT)) & ENET_QOS_MAC_HW_FEAT_PDUPSEL_MASK) + +#define ENET_QOS_MAC_HW_FEAT_FRPSEL_MASK (0x400U) +#define ENET_QOS_MAC_HW_FEAT_FRPSEL_SHIFT (10U) +/*! FRPSEL - Flexible Receive Parser Selected This bit is set to 1 when the Enable Flexible + * Programmable Receive Parser option is selected. + * 0b0..Flexible Receive Parser feature is not selected + * 0b1..Flexible Receive Parser feature is selected + */ +#define ENET_QOS_MAC_HW_FEAT_FRPSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_FRPSEL_SHIFT)) & ENET_QOS_MAC_HW_FEAT_FRPSEL_MASK) + +#define ENET_QOS_MAC_HW_FEAT_FRPBS_MASK (0x1800U) +#define ENET_QOS_MAC_HW_FEAT_FRPBS_SHIFT (11U) +/*! FRPBS - Flexible Receive Parser Buffer size This field indicates the supported Max Number of + * bytes of the packet data to be Parsed by Flexible Receive Parser. + * 0b00..64 Bytes + * 0b01..128 Bytes + * 0b10..256 Bytes + * 0b11..Reserved + */ +#define ENET_QOS_MAC_HW_FEAT_FRPBS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_FRPBS_SHIFT)) & ENET_QOS_MAC_HW_FEAT_FRPBS_MASK) + +#define ENET_QOS_MAC_HW_FEAT_OSTEN_MASK (0x800U) +#define ENET_QOS_MAC_HW_FEAT_OSTEN_SHIFT (11U) +/*! OSTEN - One-Step Timestamping Enable This bit is set to 1 when the Enable One-Step Timestamp Feature is selected. + * 0b0..One-Step Timestamping feature is not selected + * 0b1..One-Step Timestamping feature is selected + */ +#define ENET_QOS_MAC_HW_FEAT_OSTEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_OSTEN_SHIFT)) & ENET_QOS_MAC_HW_FEAT_OSTEN_MASK) + +#define ENET_QOS_MAC_HW_FEAT_PTOEN_MASK (0x1000U) +#define ENET_QOS_MAC_HW_FEAT_PTOEN_SHIFT (12U) +/*! PTOEN - PTP Offload Enable This bit is set to 1 when the Enable PTP Timestamp Offload Feature is selected. + * 0b0..PTP Offload feature is not selected + * 0b1..PTP Offload feature is selected + */ +#define ENET_QOS_MAC_HW_FEAT_PTOEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_PTOEN_SHIFT)) & ENET_QOS_MAC_HW_FEAT_PTOEN_MASK) + +#define ENET_QOS_MAC_HW_FEAT_RXCHCNT_MASK (0xF000U) +#define ENET_QOS_MAC_HW_FEAT_RXCHCNT_SHIFT (12U) +/*! RXCHCNT - Number of DMA Receive Channels This field indicates the number of DMA Receive channels: + * 0b0000..1 MTL Rx Channel + * 0b0001..2 MTL Rx Channels + * 0b0010..3 MTL Rx Channels + * 0b0011..4 MTL Rx Channels + * 0b0100..5 MTL Rx Channels + * 0b0101..Reserved + * 0b0110..Reserved + * 0b0111..Reserved + */ +#define ENET_QOS_MAC_HW_FEAT_RXCHCNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_RXCHCNT_SHIFT)) & ENET_QOS_MAC_HW_FEAT_RXCHCNT_MASK) + +#define ENET_QOS_MAC_HW_FEAT_TSSEL_MASK (0x1000U) +#define ENET_QOS_MAC_HW_FEAT_TSSEL_SHIFT (12U) +/*! TSSEL - IEEE 1588-2008 Timestamp Enabled This bit is set to 1 when the Enable IEEE 1588 Timestamp Support option is selected + * 0b0..IEEE 1588-2008 Timestamp Enable option is not selected + * 0b1..IEEE 1588-2008 Timestamp Enable option is selected + */ +#define ENET_QOS_MAC_HW_FEAT_TSSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_TSSEL_SHIFT)) & ENET_QOS_MAC_HW_FEAT_TSSEL_MASK) + +#define ENET_QOS_MAC_HW_FEAT_ADVTHWORD_MASK (0x2000U) +#define ENET_QOS_MAC_HW_FEAT_ADVTHWORD_SHIFT (13U) +/*! ADVTHWORD - IEEE 1588 High Word Register Enable This bit is set to 1 when the Add IEEE 1588 Higher Word Register option is selected + * 0b0..IEEE 1588 High Word Register option is not selected + * 0b1..IEEE 1588 High Word Register option is selected + */ +#define ENET_QOS_MAC_HW_FEAT_ADVTHWORD(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_ADVTHWORD_SHIFT)) & ENET_QOS_MAC_HW_FEAT_ADVTHWORD_MASK) + +#define ENET_QOS_MAC_HW_FEAT_EEESEL_MASK (0x2000U) +#define ENET_QOS_MAC_HW_FEAT_EEESEL_SHIFT (13U) +/*! EEESEL - Energy Efficient Ethernet Enabled This bit is set to 1 when the Enable Energy Efficient + * Ethernet (EEE) option is selected + * 0b0..Energy Efficient Ethernet Enable option is not selected + * 0b1..Energy Efficient Ethernet Enable option is selected + */ +#define ENET_QOS_MAC_HW_FEAT_EEESEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_EEESEL_SHIFT)) & ENET_QOS_MAC_HW_FEAT_EEESEL_MASK) + +#define ENET_QOS_MAC_HW_FEAT_FRPES_MASK (0x6000U) +#define ENET_QOS_MAC_HW_FEAT_FRPES_SHIFT (13U) +/*! FRPES - Flexible Receive Parser Table Entries size This field indicates the Max Number of Parser + * Entries supported by Flexible Receive Parser. + * 0b00..64 Entries + * 0b01..128 Entries + * 0b10..256 Entries + * 0b11..Reserved + */ +#define ENET_QOS_MAC_HW_FEAT_FRPES(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_FRPES_SHIFT)) & ENET_QOS_MAC_HW_FEAT_FRPES_MASK) + +#define ENET_QOS_MAC_HW_FEAT_ADDR64_MASK (0xC000U) +#define ENET_QOS_MAC_HW_FEAT_ADDR64_SHIFT (14U) +/*! ADDR64 - Address Width. + * 0b00..32 + * 0b01..40 + * 0b10..48 + * 0b11..Reserved + */ +#define ENET_QOS_MAC_HW_FEAT_ADDR64(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_ADDR64_SHIFT)) & ENET_QOS_MAC_HW_FEAT_ADDR64_MASK) + +#define ENET_QOS_MAC_HW_FEAT_TXCOESEL_MASK (0x4000U) +#define ENET_QOS_MAC_HW_FEAT_TXCOESEL_SHIFT (14U) +/*! TXCOESEL - Transmit Checksum Offload Enabled This bit is set to 1 when the Enable Transmit + * TCP/IP Checksum Insertion option is selected + * 0b0..Transmit Checksum Offload Enable option is not selected + * 0b1..Transmit Checksum Offload Enable option is selected + */ +#define ENET_QOS_MAC_HW_FEAT_TXCOESEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_TXCOESEL_SHIFT)) & ENET_QOS_MAC_HW_FEAT_TXCOESEL_MASK) + +#define ENET_QOS_MAC_HW_FEAT_DCBEN_MASK (0x10000U) +#define ENET_QOS_MAC_HW_FEAT_DCBEN_SHIFT (16U) +/*! DCBEN - DCB Feature Enable This bit is set to 1 when the Enable Data Center Bridging option is selected + * 0b0..DCB Feature is not selected + * 0b1..DCB Feature is selected + */ +#define ENET_QOS_MAC_HW_FEAT_DCBEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_DCBEN_SHIFT)) & ENET_QOS_MAC_HW_FEAT_DCBEN_MASK) + +#define ENET_QOS_MAC_HW_FEAT_ESTSEL_MASK (0x10000U) +#define ENET_QOS_MAC_HW_FEAT_ESTSEL_SHIFT (16U) +/*! ESTSEL - Enhancements to Scheduling Traffic Enable This bit is set to 1 when the Enable + * Enhancements to Scheduling Traffic feature is selected. + * 0b0..Enable Enhancements to Scheduling Traffic feature is not selected + * 0b1..Enable Enhancements to Scheduling Traffic feature is selected + */ +#define ENET_QOS_MAC_HW_FEAT_ESTSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_ESTSEL_SHIFT)) & ENET_QOS_MAC_HW_FEAT_ESTSEL_MASK) + +#define ENET_QOS_MAC_HW_FEAT_RXCOESEL_MASK (0x10000U) +#define ENET_QOS_MAC_HW_FEAT_RXCOESEL_SHIFT (16U) +/*! RXCOESEL - Receive Checksum Offload Enabled This bit is set to 1 when the Enable Receive TCP/IP Checksum Check option is selected + * 0b0..Receive Checksum Offload Enable option is not selected + * 0b1..Receive Checksum Offload Enable option is selected + */ +#define ENET_QOS_MAC_HW_FEAT_RXCOESEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_RXCOESEL_SHIFT)) & ENET_QOS_MAC_HW_FEAT_RXCOESEL_MASK) + +#define ENET_QOS_MAC_HW_FEAT_ESTDEP_MASK (0xE0000U) +#define ENET_QOS_MAC_HW_FEAT_ESTDEP_SHIFT (17U) +/*! ESTDEP - Depth of the Gate Control List This field indicates the depth of Gate Control list expressed as Log2(DWC_EQOS_EST_DEP)-5 + * 0b000..No Depth configured + * 0b001..64 + * 0b010..128 + * 0b011..256 + * 0b100..512 + * 0b101..1024 + * 0b110..Reserved + */ +#define ENET_QOS_MAC_HW_FEAT_ESTDEP(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_ESTDEP_SHIFT)) & ENET_QOS_MAC_HW_FEAT_ESTDEP_MASK) + +#define ENET_QOS_MAC_HW_FEAT_SPHEN_MASK (0x20000U) +#define ENET_QOS_MAC_HW_FEAT_SPHEN_SHIFT (17U) +/*! SPHEN - Split Header Feature Enable This bit is set to 1 when the Enable Split Header Structure option is selected + * 0b0..Split Header Feature is not selected + * 0b1..Split Header Feature is selected + */ +#define ENET_QOS_MAC_HW_FEAT_SPHEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_SPHEN_SHIFT)) & ENET_QOS_MAC_HW_FEAT_SPHEN_MASK) + +#define ENET_QOS_MAC_HW_FEAT_ADDMACADRSEL_MASK (0x7C0000U) +#define ENET_QOS_MAC_HW_FEAT_ADDMACADRSEL_SHIFT (18U) +/*! ADDMACADRSEL - MAC Addresses 1-31 Selected This bit is set to 1 when the non-zero value is + * selected for Enable Additional 1-31 MAC Address Registers option + */ +#define ENET_QOS_MAC_HW_FEAT_ADDMACADRSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_ADDMACADRSEL_SHIFT)) & ENET_QOS_MAC_HW_FEAT_ADDMACADRSEL_MASK) + +#define ENET_QOS_MAC_HW_FEAT_TSOEN_MASK (0x40000U) +#define ENET_QOS_MAC_HW_FEAT_TSOEN_SHIFT (18U) +/*! TSOEN - TCP Segmentation Offload Enable This bit is set to 1 when the Enable TCP Segmentation + * Offloading for TCP/IP Packets option is selected + * 0b0..TCP Segmentation Offload Feature is not selected + * 0b1..TCP Segmentation Offload Feature is selected + */ +#define ENET_QOS_MAC_HW_FEAT_TSOEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_TSOEN_SHIFT)) & ENET_QOS_MAC_HW_FEAT_TSOEN_MASK) + +#define ENET_QOS_MAC_HW_FEAT_TXCHCNT_MASK (0x3C0000U) +#define ENET_QOS_MAC_HW_FEAT_TXCHCNT_SHIFT (18U) +/*! TXCHCNT - Number of DMA Transmit Channels This field indicates the number of DMA Transmit channels: + * 0b0000..1 MTL Tx Channel + * 0b0001..2 MTL Tx Channels + * 0b0010..3 MTL Tx Channels + * 0b0011..4 MTL Tx Channels + * 0b0100..5 MTL Tx Channels + * 0b0101..Reserved + * 0b0110..Reserved + * 0b0111..Reserved + */ +#define ENET_QOS_MAC_HW_FEAT_TXCHCNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_TXCHCNT_SHIFT)) & ENET_QOS_MAC_HW_FEAT_TXCHCNT_MASK) + +#define ENET_QOS_MAC_HW_FEAT_DBGMEMA_MASK (0x80000U) +#define ENET_QOS_MAC_HW_FEAT_DBGMEMA_SHIFT (19U) +/*! DBGMEMA - DMA Debug Registers Enable This bit is set to 1 when the Debug Mode Enable option is selected + * 0b0..DMA Debug Registers option is not selected + * 0b1..DMA Debug Registers option is selected + */ +#define ENET_QOS_MAC_HW_FEAT_DBGMEMA(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_DBGMEMA_SHIFT)) & ENET_QOS_MAC_HW_FEAT_DBGMEMA_MASK) + +#define ENET_QOS_MAC_HW_FEAT_AVSEL_MASK (0x100000U) +#define ENET_QOS_MAC_HW_FEAT_AVSEL_SHIFT (20U) +/*! AVSEL - AV Feature Enable This bit is set to 1 when the Enable Audio Video Bridging option is selected. + * 0b0..AV Feature is not selected + * 0b1..AV Feature is selected + */ +#define ENET_QOS_MAC_HW_FEAT_AVSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_AVSEL_SHIFT)) & ENET_QOS_MAC_HW_FEAT_AVSEL_MASK) + +#define ENET_QOS_MAC_HW_FEAT_ESTWID_MASK (0x300000U) +#define ENET_QOS_MAC_HW_FEAT_ESTWID_SHIFT (20U) +/*! ESTWID - Width of the Time Interval field in the Gate Control List This field indicates the + * width of the Configured Time Interval Field + * 0b00..Width not configured + * 0b01..16 + * 0b10..20 + * 0b11..24 + */ +#define ENET_QOS_MAC_HW_FEAT_ESTWID(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_ESTWID_SHIFT)) & ENET_QOS_MAC_HW_FEAT_ESTWID_MASK) + +#define ENET_QOS_MAC_HW_FEAT_RAVSEL_MASK (0x200000U) +#define ENET_QOS_MAC_HW_FEAT_RAVSEL_SHIFT (21U) +/*! RAVSEL - Rx Side Only AV Feature Enable This bit is set to 1 when the Enable Audio Video + * Bridging option on Rx Side Only is selected. + * 0b0..Rx Side Only AV Feature is not selected + * 0b1..Rx Side Only AV Feature is selected + */ +#define ENET_QOS_MAC_HW_FEAT_RAVSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_RAVSEL_SHIFT)) & ENET_QOS_MAC_HW_FEAT_RAVSEL_MASK) + +#define ENET_QOS_MAC_HW_FEAT_MACADR32SEL_MASK (0x800000U) +#define ENET_QOS_MAC_HW_FEAT_MACADR32SEL_SHIFT (23U) +/*! MACADR32SEL - MAC Addresses 32-63 Selected This bit is set to 1 when the Enable Additional 32 + * MAC Address Registers (32-63) option is selected + * 0b0..MAC Addresses 32-63 Select option is not selected + * 0b1..MAC Addresses 32-63 Select option is selected + */ +#define ENET_QOS_MAC_HW_FEAT_MACADR32SEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_MACADR32SEL_SHIFT)) & ENET_QOS_MAC_HW_FEAT_MACADR32SEL_MASK) + +#define ENET_QOS_MAC_HW_FEAT_POUOST_MASK (0x800000U) +#define ENET_QOS_MAC_HW_FEAT_POUOST_SHIFT (23U) +/*! POUOST - One Step for PTP over UDP/IP Feature Enable This bit is set to 1 when the Enable One + * step timestamp for PTP over UDP/IP feature is selected. + * 0b0..One Step for PTP over UDP/IP Feature is not selected + * 0b1..One Step for PTP over UDP/IP Feature is selected + */ +#define ENET_QOS_MAC_HW_FEAT_POUOST(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_POUOST_SHIFT)) & ENET_QOS_MAC_HW_FEAT_POUOST_MASK) + +#define ENET_QOS_MAC_HW_FEAT_HASHTBLSZ_MASK (0x3000000U) +#define ENET_QOS_MAC_HW_FEAT_HASHTBLSZ_SHIFT (24U) +/*! HASHTBLSZ - Hash Table Size This field indicates the size of the hash table: + * 0b00..No hash table + * 0b01..64 + * 0b10..128 + * 0b11..256 + */ +#define ENET_QOS_MAC_HW_FEAT_HASHTBLSZ(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_HASHTBLSZ_SHIFT)) & ENET_QOS_MAC_HW_FEAT_HASHTBLSZ_MASK) + +#define ENET_QOS_MAC_HW_FEAT_MACADR64SEL_MASK (0x1000000U) +#define ENET_QOS_MAC_HW_FEAT_MACADR64SEL_SHIFT (24U) +/*! MACADR64SEL - MAC Addresses 64-127 Selected This bit is set to 1 when the Enable Additional 64 + * MAC Address Registers (64-127) option is selected + * 0b0..MAC Addresses 64-127 Select option is not selected + * 0b1..MAC Addresses 64-127 Select option is selected + */ +#define ENET_QOS_MAC_HW_FEAT_MACADR64SEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_MACADR64SEL_SHIFT)) & ENET_QOS_MAC_HW_FEAT_MACADR64SEL_MASK) + +#define ENET_QOS_MAC_HW_FEAT_PPSOUTNUM_MASK (0x7000000U) +#define ENET_QOS_MAC_HW_FEAT_PPSOUTNUM_SHIFT (24U) +/*! PPSOUTNUM - Number of PPS Outputs This field indicates the number of PPS outputs: + * 0b000..No PPS output + * 0b001..1 PPS output + * 0b010..2 PPS output + * 0b011..3 PPS output + * 0b100..4 PPS output + * 0b101..Reserved + */ +#define ENET_QOS_MAC_HW_FEAT_PPSOUTNUM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_PPSOUTNUM_SHIFT)) & ENET_QOS_MAC_HW_FEAT_PPSOUTNUM_MASK) + +#define ENET_QOS_MAC_HW_FEAT_TSSTSSEL_MASK (0x6000000U) +#define ENET_QOS_MAC_HW_FEAT_TSSTSSEL_SHIFT (25U) +/*! TSSTSSEL - Timestamp System Time Source This bit indicates the source of the Timestamp system + * time: This bit is set to 1 when the Enable IEEE 1588 Timestamp Support option is selected + * 0b00..Reserved + * 0b01..Internal + * 0b10..External + * 0b11..Both + */ +#define ENET_QOS_MAC_HW_FEAT_TSSTSSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_TSSTSSEL_SHIFT)) & ENET_QOS_MAC_HW_FEAT_TSSTSSEL_MASK) + +#define ENET_QOS_MAC_HW_FEAT_FPESEL_MASK (0x4000000U) +#define ENET_QOS_MAC_HW_FEAT_FPESEL_SHIFT (26U) +/*! FPESEL - Frame Preemption Enable This bit is set to 1 when the Enable Frame preemption feature is selected. + * 0b0..Frame Preemption Enable feature is not selected + * 0b1..Frame Preemption Enable feature is selected + */ +#define ENET_QOS_MAC_HW_FEAT_FPESEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_FPESEL_SHIFT)) & ENET_QOS_MAC_HW_FEAT_FPESEL_MASK) + +#define ENET_QOS_MAC_HW_FEAT_L3L4FNUM_MASK (0x78000000U) +#define ENET_QOS_MAC_HW_FEAT_L3L4FNUM_SHIFT (27U) +/*! L3L4FNUM - Total number of L3 or L4 Filters This field indicates the total number of L3 or L4 filters: + * 0b0000..No L3 or L4 Filter + * 0b0001..1 L3 or L4 Filter + * 0b0010..2 L3 or L4 Filters + * 0b0011..3 L3 or L4 Filters + * 0b0100..4 L3 or L4 Filters + * 0b0101..5 L3 or L4 Filters + * 0b0110..6 L3 or L4 Filters + * 0b0111..7 L3 or L4 Filters + * 0b1000..8 L3 or L4 Filters + */ +#define ENET_QOS_MAC_HW_FEAT_L3L4FNUM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_L3L4FNUM_SHIFT)) & ENET_QOS_MAC_HW_FEAT_L3L4FNUM_MASK) + +#define ENET_QOS_MAC_HW_FEAT_SAVLANINS_MASK (0x8000000U) +#define ENET_QOS_MAC_HW_FEAT_SAVLANINS_SHIFT (27U) +/*! SAVLANINS - Source Address or VLAN Insertion Enable This bit is set to 1 when the Enable SA and + * VLAN Insertion on Tx option is selected + * 0b0..Source Address or VLAN Insertion Enable option is not selected + * 0b1..Source Address or VLAN Insertion Enable option is selected + */ +#define ENET_QOS_MAC_HW_FEAT_SAVLANINS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_SAVLANINS_SHIFT)) & ENET_QOS_MAC_HW_FEAT_SAVLANINS_MASK) + +#define ENET_QOS_MAC_HW_FEAT_TBSSEL_MASK (0x8000000U) +#define ENET_QOS_MAC_HW_FEAT_TBSSEL_SHIFT (27U) +/*! TBSSEL - Time Based Scheduling Enable This bit is set to 1 when the Time Based Scheduling feature is selected. + * 0b0..Time Based Scheduling Enable feature is not selected + * 0b1..Time Based Scheduling Enable feature is selected + */ +#define ENET_QOS_MAC_HW_FEAT_TBSSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_TBSSEL_SHIFT)) & ENET_QOS_MAC_HW_FEAT_TBSSEL_MASK) + +#define ENET_QOS_MAC_HW_FEAT_ACTPHYSEL_MASK (0x70000000U) +#define ENET_QOS_MAC_HW_FEAT_ACTPHYSEL_SHIFT (28U) +/*! ACTPHYSEL - Active PHY Selected When you have multiple PHY interfaces in your configuration, + * this field indicates the sampled value of phy_intf_sel_i during reset de-assertion. + * 0b000..GMII + * 0b001..RGMII + * 0b010..SGMII + * 0b011..TBI + * 0b100..RMII + * 0b101..RTBI + * 0b110..SMII + * 0b111..RevMII + */ +#define ENET_QOS_MAC_HW_FEAT_ACTPHYSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_ACTPHYSEL_SHIFT)) & ENET_QOS_MAC_HW_FEAT_ACTPHYSEL_MASK) + +#define ENET_QOS_MAC_HW_FEAT_ASP_MASK (0x30000000U) +#define ENET_QOS_MAC_HW_FEAT_ASP_SHIFT (28U) +/*! ASP - Automotive Safety Package Following are the encoding for the different Safety features + * 0b00..No Safety features selected + * 0b01..Only "ECC protection for external memory" feature is selected + * 0b10..All the Automotive Safety features are selected without the "Parity Port Enable for external interface" feature + * 0b11..All the Automotive Safety features are selected with the "Parity Port Enable for external interface" feature + */ +#define ENET_QOS_MAC_HW_FEAT_ASP(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_ASP_SHIFT)) & ENET_QOS_MAC_HW_FEAT_ASP_MASK) + +#define ENET_QOS_MAC_HW_FEAT_AUXSNAPNUM_MASK (0x70000000U) +#define ENET_QOS_MAC_HW_FEAT_AUXSNAPNUM_SHIFT (28U) +/*! AUXSNAPNUM - Number of Auxiliary Snapshot Inputs This field indicates the number of auxiliary snapshot inputs: + * 0b000..No auxiliary input + * 0b001..1 auxiliary input + * 0b010..2 auxiliary input + * 0b011..3 auxiliary input + * 0b100..4 auxiliary input + * 0b101..Reserved + */ +#define ENET_QOS_MAC_HW_FEAT_AUXSNAPNUM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_AUXSNAPNUM_SHIFT)) & ENET_QOS_MAC_HW_FEAT_AUXSNAPNUM_MASK) +/*! @} */ + +/* The count of ENET_QOS_MAC_HW_FEAT */ +#define ENET_QOS_MAC_HW_FEAT_COUNT (4U) + +/*! @name MAC_MDIO_ADDRESS - MDIO Address */ +/*! @{ */ + +#define ENET_QOS_MAC_MDIO_ADDRESS_GB_MASK (0x1U) +#define ENET_QOS_MAC_MDIO_ADDRESS_GB_SHIFT (0U) +/*! GB - GMII Busy The application sets this bit to instruct the SMA to initiate a Read or Write access to the MDIO slave. + * 0b0..GMII Busy is disabled + * 0b1..GMII Busy is enabled + */ +#define ENET_QOS_MAC_MDIO_ADDRESS_GB(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MDIO_ADDRESS_GB_SHIFT)) & ENET_QOS_MAC_MDIO_ADDRESS_GB_MASK) + +#define ENET_QOS_MAC_MDIO_ADDRESS_C45E_MASK (0x2U) +#define ENET_QOS_MAC_MDIO_ADDRESS_C45E_SHIFT (1U) +/*! C45E - Clause 45 PHY Enable When this bit is set, Clause 45 capable PHY is connected to MDIO. + * 0b0..Clause 45 PHY is disabled + * 0b1..Clause 45 PHY is enabled + */ +#define ENET_QOS_MAC_MDIO_ADDRESS_C45E(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MDIO_ADDRESS_C45E_SHIFT)) & ENET_QOS_MAC_MDIO_ADDRESS_C45E_MASK) + +#define ENET_QOS_MAC_MDIO_ADDRESS_GOC_0_MASK (0x4U) +#define ENET_QOS_MAC_MDIO_ADDRESS_GOC_0_SHIFT (2U) +/*! GOC_0 - GMII Operation Command 0 This is the lower bit of the operation command to the PHY or RevMII. + * 0b0..GMII Operation Command 0 is disabled + * 0b1..GMII Operation Command 0 is enabled + */ +#define ENET_QOS_MAC_MDIO_ADDRESS_GOC_0(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MDIO_ADDRESS_GOC_0_SHIFT)) & ENET_QOS_MAC_MDIO_ADDRESS_GOC_0_MASK) + +#define ENET_QOS_MAC_MDIO_ADDRESS_GOC_1_MASK (0x8U) +#define ENET_QOS_MAC_MDIO_ADDRESS_GOC_1_SHIFT (3U) +/*! GOC_1 - GMII Operation Command 1 This bit is higher bit of the operation command to the PHY or + * RevMII, GOC_1 and GOC_O is encoded as follows: - 00: Reserved - 01: Write - 10: Post Read + * Increment Address for Clause 45 PHY - 11: Read When Clause 22 PHY or RevMII is enabled, only Write + * and Read commands are valid. + * 0b0..GMII Operation Command 1 is disabled + * 0b1..GMII Operation Command 1 is enabled + */ +#define ENET_QOS_MAC_MDIO_ADDRESS_GOC_1(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MDIO_ADDRESS_GOC_1_SHIFT)) & ENET_QOS_MAC_MDIO_ADDRESS_GOC_1_MASK) + +#define ENET_QOS_MAC_MDIO_ADDRESS_SKAP_MASK (0x10U) +#define ENET_QOS_MAC_MDIO_ADDRESS_SKAP_SHIFT (4U) +/*! SKAP - Skip Address Packet When this bit is set, the SMA does not send the address packets + * before read, write, or post-read increment address packets. + * 0b0..Skip Address Packet is disabled + * 0b1..Skip Address Packet is enabled + */ +#define ENET_QOS_MAC_MDIO_ADDRESS_SKAP(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MDIO_ADDRESS_SKAP_SHIFT)) & ENET_QOS_MAC_MDIO_ADDRESS_SKAP_MASK) + +#define ENET_QOS_MAC_MDIO_ADDRESS_CR_MASK (0xF00U) +#define ENET_QOS_MAC_MDIO_ADDRESS_CR_SHIFT (8U) +/*! CR - CSR Clock Range The CSR Clock Range selection determines the frequency of the MDC clock + * according to the CSR clock frequency used in your design: - 0000: CSR clock = 60-100 MHz; MDC + * clock = CSR clock/42 - 0001: CSR clock = 100-150 MHz; MDC clock = CSR clock/62 - 0010: CSR clock + * = 20-35 MHz; MDC clock = CSR clock/16 - 0011: CSR clock = 35-60 MHz; MDC clock = CSR clock/26 + * - 0100: CSR clock = 150-250 MHz; MDC clock = CSR clock/102 - 0101: CSR clock = 250-300 MHz; + * MDC clock = CSR clock/124 - 0110: CSR clock = 300-500 MHz; MDC clock = CSR clock/204 - 0111: CSR + * clock = 500-800 MHz; MDC clock = CSR clock/324 The suggested range of CSR clock frequency + * applicable for each value (when Bit 11 = 0) ensures that the MDC clock is approximately between 1. + */ +#define ENET_QOS_MAC_MDIO_ADDRESS_CR(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MDIO_ADDRESS_CR_SHIFT)) & ENET_QOS_MAC_MDIO_ADDRESS_CR_MASK) + +#define ENET_QOS_MAC_MDIO_ADDRESS_NTC_MASK (0x7000U) +#define ENET_QOS_MAC_MDIO_ADDRESS_NTC_SHIFT (12U) +/*! NTC - Number of Trailing Clocks This field controls the number of trailing clock cycles + * generated on gmii_mdc_o (MDC) after the end of transmission of MDIO frame. + */ +#define ENET_QOS_MAC_MDIO_ADDRESS_NTC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MDIO_ADDRESS_NTC_SHIFT)) & ENET_QOS_MAC_MDIO_ADDRESS_NTC_MASK) + +#define ENET_QOS_MAC_MDIO_ADDRESS_RDA_MASK (0x1F0000U) +#define ENET_QOS_MAC_MDIO_ADDRESS_RDA_SHIFT (16U) +/*! RDA - Register/Device Address These bits select the PHY register in selected Clause 22 PHY device. */ +#define ENET_QOS_MAC_MDIO_ADDRESS_RDA(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MDIO_ADDRESS_RDA_SHIFT)) & ENET_QOS_MAC_MDIO_ADDRESS_RDA_MASK) + +#define ENET_QOS_MAC_MDIO_ADDRESS_PA_MASK (0x3E00000U) +#define ENET_QOS_MAC_MDIO_ADDRESS_PA_SHIFT (21U) +/*! PA - Physical Layer Address This field indicates which Clause 22 PHY devices (out of 32 devices) the MAC is accessing. */ +#define ENET_QOS_MAC_MDIO_ADDRESS_PA(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MDIO_ADDRESS_PA_SHIFT)) & ENET_QOS_MAC_MDIO_ADDRESS_PA_MASK) + +#define ENET_QOS_MAC_MDIO_ADDRESS_BTB_MASK (0x4000000U) +#define ENET_QOS_MAC_MDIO_ADDRESS_BTB_SHIFT (26U) +/*! BTB - Back to Back transactions When this bit is set and the NTC has value greater than 0, then + * the MAC informs the completion of a read or write command at the end of frame transfer (before + * the trailing clocks are transmitted). + * 0b0..Back to Back transactions disabled + * 0b1..Back to Back transactions enabled + */ +#define ENET_QOS_MAC_MDIO_ADDRESS_BTB(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MDIO_ADDRESS_BTB_SHIFT)) & ENET_QOS_MAC_MDIO_ADDRESS_BTB_MASK) + +#define ENET_QOS_MAC_MDIO_ADDRESS_PSE_MASK (0x8000000U) +#define ENET_QOS_MAC_MDIO_ADDRESS_PSE_SHIFT (27U) +/*! PSE - Preamble Suppression Enable When this bit is set, the SMA suppresses the 32-bit preamble + * and transmits MDIO frames with only 1 preamble bit. + * 0b0..Preamble Suppression disabled + * 0b1..Preamble Suppression enabled + */ +#define ENET_QOS_MAC_MDIO_ADDRESS_PSE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MDIO_ADDRESS_PSE_SHIFT)) & ENET_QOS_MAC_MDIO_ADDRESS_PSE_MASK) +/*! @} */ + +/*! @name MAC_MDIO_DATA - MAC MDIO Data */ +/*! @{ */ + +#define ENET_QOS_MAC_MDIO_DATA_GD_MASK (0xFFFFU) +#define ENET_QOS_MAC_MDIO_DATA_GD_SHIFT (0U) +/*! GD - GMII Data This field contains the 16-bit data value read from the PHY or RevMII after a + * Management Read operation or the 16-bit data value to be written to the PHY or RevMII before a + * Management Write operation. + */ +#define ENET_QOS_MAC_MDIO_DATA_GD(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MDIO_DATA_GD_SHIFT)) & ENET_QOS_MAC_MDIO_DATA_GD_MASK) + +#define ENET_QOS_MAC_MDIO_DATA_RA_MASK (0xFFFF0000U) +#define ENET_QOS_MAC_MDIO_DATA_RA_SHIFT (16U) +/*! RA - Register Address This field is valid only when C45E is set. */ +#define ENET_QOS_MAC_MDIO_DATA_RA(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MDIO_DATA_RA_SHIFT)) & ENET_QOS_MAC_MDIO_DATA_RA_MASK) +/*! @} */ + +/*! @name MAC_CSR_SW_CTRL - CSR Software Control */ +/*! @{ */ + +#define ENET_QOS_MAC_CSR_SW_CTRL_RCWE_MASK (0x1U) +#define ENET_QOS_MAC_CSR_SW_CTRL_RCWE_SHIFT (0U) +/*! RCWE - Register Clear on Write 1 Enable When this bit is set, the access mode of some register + * fields changes to Clear on Write 1, the application needs to set that respective bit to 1 to + * clear it. + * 0b0..Register Clear on Write 1 is disabled + * 0b1..Register Clear on Write 1 is enabled + */ +#define ENET_QOS_MAC_CSR_SW_CTRL_RCWE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_CSR_SW_CTRL_RCWE_SHIFT)) & ENET_QOS_MAC_CSR_SW_CTRL_RCWE_MASK) +/*! @} */ + +/*! @name MAC_FPE_CTRL_STS - Frame Preemption Control */ +/*! @{ */ + +#define ENET_QOS_MAC_FPE_CTRL_STS_EFPE_MASK (0x1U) +#define ENET_QOS_MAC_FPE_CTRL_STS_EFPE_SHIFT (0U) +/*! EFPE - Enable Tx Frame Preemption When set Frame Preemption Tx functionality is enabled. + * 0b0..Tx Frame Preemption is disabled + * 0b1..Tx Frame Preemption is enabled + */ +#define ENET_QOS_MAC_FPE_CTRL_STS_EFPE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_FPE_CTRL_STS_EFPE_SHIFT)) & ENET_QOS_MAC_FPE_CTRL_STS_EFPE_MASK) + +#define ENET_QOS_MAC_FPE_CTRL_STS_SVER_MASK (0x2U) +#define ENET_QOS_MAC_FPE_CTRL_STS_SVER_SHIFT (1U) +/*! SVER - Send Verify mPacket When set indicates hardware to send a verify mPacket. + * 0b0..Send Verify mPacket is disabled + * 0b1..Send Verify mPacket is enabled + */ +#define ENET_QOS_MAC_FPE_CTRL_STS_SVER(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_FPE_CTRL_STS_SVER_SHIFT)) & ENET_QOS_MAC_FPE_CTRL_STS_SVER_MASK) + +#define ENET_QOS_MAC_FPE_CTRL_STS_SRSP_MASK (0x4U) +#define ENET_QOS_MAC_FPE_CTRL_STS_SRSP_SHIFT (2U) +/*! SRSP - Send Respond mPacket When set indicates hardware to send a Respond mPacket. + * 0b0..Send Respond mPacket is disabled + * 0b1..Send Respond mPacket is enabled + */ +#define ENET_QOS_MAC_FPE_CTRL_STS_SRSP(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_FPE_CTRL_STS_SRSP_SHIFT)) & ENET_QOS_MAC_FPE_CTRL_STS_SRSP_MASK) + +#define ENET_QOS_MAC_FPE_CTRL_STS_S1_SET_0_MASK (0x8U) +#define ENET_QOS_MAC_FPE_CTRL_STS_S1_SET_0_SHIFT (3U) +/*! S1_SET_0 - Reserved, Must be set to "0". */ +#define ENET_QOS_MAC_FPE_CTRL_STS_S1_SET_0(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_FPE_CTRL_STS_S1_SET_0_SHIFT)) & ENET_QOS_MAC_FPE_CTRL_STS_S1_SET_0_MASK) + +#define ENET_QOS_MAC_FPE_CTRL_STS_RVER_MASK (0x10000U) +#define ENET_QOS_MAC_FPE_CTRL_STS_RVER_SHIFT (16U) +/*! RVER - Received Verify Frame Set when a Verify mPacket is received. + * 0b0..Not received Verify Frame + * 0b1..Received Verify Frame + */ +#define ENET_QOS_MAC_FPE_CTRL_STS_RVER(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_FPE_CTRL_STS_RVER_SHIFT)) & ENET_QOS_MAC_FPE_CTRL_STS_RVER_MASK) + +#define ENET_QOS_MAC_FPE_CTRL_STS_RRSP_MASK (0x20000U) +#define ENET_QOS_MAC_FPE_CTRL_STS_RRSP_SHIFT (17U) +/*! RRSP - Received Respond Frame Set when a Respond mPacket is received. + * 0b0..Not received Respond Frame + * 0b1..Received Respond Frame + */ +#define ENET_QOS_MAC_FPE_CTRL_STS_RRSP(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_FPE_CTRL_STS_RRSP_SHIFT)) & ENET_QOS_MAC_FPE_CTRL_STS_RRSP_MASK) + +#define ENET_QOS_MAC_FPE_CTRL_STS_TVER_MASK (0x40000U) +#define ENET_QOS_MAC_FPE_CTRL_STS_TVER_SHIFT (18U) +/*! TVER - Transmitted Verify Frame Set when a Verify mPacket is transmitted (triggered by setting SVER field). + * 0b0..Not transmitted Verify Frame + * 0b1..transmitted Verify Frame + */ +#define ENET_QOS_MAC_FPE_CTRL_STS_TVER(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_FPE_CTRL_STS_TVER_SHIFT)) & ENET_QOS_MAC_FPE_CTRL_STS_TVER_MASK) + +#define ENET_QOS_MAC_FPE_CTRL_STS_TRSP_MASK (0x80000U) +#define ENET_QOS_MAC_FPE_CTRL_STS_TRSP_SHIFT (19U) +/*! TRSP - Transmitted Respond Frame Set when a Respond mPacket is transmitted (triggered by setting SRSP field). + * 0b0..Not transmitted Respond Frame + * 0b1..transmitted Respond Frame + */ +#define ENET_QOS_MAC_FPE_CTRL_STS_TRSP(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_FPE_CTRL_STS_TRSP_SHIFT)) & ENET_QOS_MAC_FPE_CTRL_STS_TRSP_MASK) +/*! @} */ + +/*! @name MAC_PRESN_TIME_NS - 32-bit Binary Rollover Equivalent Time */ +/*! @{ */ + +#define ENET_QOS_MAC_PRESN_TIME_NS_MPTN_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_PRESN_TIME_NS_MPTN_SHIFT (0U) +/*! MPTN - MAC 1722 Presentation Time in ns These bits indicate the value of the 32-bit binary + * rollover equivalent time of the PTP System Time in ns + */ +#define ENET_QOS_MAC_PRESN_TIME_NS_MPTN(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PRESN_TIME_NS_MPTN_SHIFT)) & ENET_QOS_MAC_PRESN_TIME_NS_MPTN_MASK) +/*! @} */ + +/*! @name MAC_PRESN_TIME_UPDT - MAC 1722 Presentation Time */ +/*! @{ */ + +#define ENET_QOS_MAC_PRESN_TIME_UPDT_MPTU_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_PRESN_TIME_UPDT_MPTU_SHIFT (0U) +/*! MPTU - MAC 1722 Presentation Time Update This field holds the init value or the update value for the presentation time. */ +#define ENET_QOS_MAC_PRESN_TIME_UPDT_MPTU(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PRESN_TIME_UPDT_MPTU_SHIFT)) & ENET_QOS_MAC_PRESN_TIME_UPDT_MPTU_MASK) +/*! @} */ + +/*! @name HIGH - MAC Address0 High..MAC Address63 High */ +/*! @{ */ + +#define ENET_QOS_HIGH_ADDRHI_MASK (0xFFFFU) +#define ENET_QOS_HIGH_ADDRHI_SHIFT (0U) +/*! ADDRHI - MAC ADDRESS12 [47:32] This field contains the upper 16 bits[47:32] of the thirteenth 6-byte MAC address. */ +#define ENET_QOS_HIGH_ADDRHI(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_HIGH_ADDRHI_SHIFT)) & ENET_QOS_HIGH_ADDRHI_MASK) + +#define ENET_QOS_HIGH_DCS_MASK (0x1F0000U) /* Merged from fields with different position or width, of widths (3, 5), largest definition used */ +#define ENET_QOS_HIGH_DCS_SHIFT (16U) +/*! DCS - DMA Channel Select If the PDC bit of MAC_EXT_CONFIGURATION register is not set: This field + * contains the binary representation of the DMA Channel number to which an Rx packet whose DA + * matches the MAC Address(#i) content is routed. + */ +#define ENET_QOS_HIGH_DCS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_HIGH_DCS_SHIFT)) & ENET_QOS_HIGH_DCS_MASK) /* Merged from fields with different position or width, of widths (3, 5), largest definition used */ + +#define ENET_QOS_HIGH_MBC_MASK (0x3F000000U) +#define ENET_QOS_HIGH_MBC_SHIFT (24U) +/*! MBC - Mask Byte Control These bits are mask control bits for comparing each of the MAC Address bytes. */ +#define ENET_QOS_HIGH_MBC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_HIGH_MBC_SHIFT)) & ENET_QOS_HIGH_MBC_MASK) + +#define ENET_QOS_HIGH_SA_MASK (0x40000000U) +#define ENET_QOS_HIGH_SA_SHIFT (30U) +/*! SA - Source Address When this bit is set, the MAC ADDRESS31[47:0] is used to compare with the SA + * fields of the received packet. + * 0b0..Compare with Destination Address + * 0b1..Compare with Source Address + */ +#define ENET_QOS_HIGH_SA(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_HIGH_SA_SHIFT)) & ENET_QOS_HIGH_SA_MASK) + +#define ENET_QOS_HIGH_AE_MASK (0x80000000U) +#define ENET_QOS_HIGH_AE_SHIFT (31U) +/*! AE - Address Enable When this bit is set, the address filter module uses the thirteenth MAC address for perfect filtering. + * 0b0..INVALID : This bit must be always set to 1 + * 0b1..This bit is always set to 1 + */ +#define ENET_QOS_HIGH_AE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_HIGH_AE_SHIFT)) & ENET_QOS_HIGH_AE_MASK) +/*! @} */ + +/* The count of ENET_QOS_HIGH */ +#define ENET_QOS_HIGH_COUNT (64U) + +/*! @name LOW - MAC Address0 Low..MAC Address63 Low */ +/*! @{ */ + +#define ENET_QOS_LOW_ADDRLO_MASK (0xFFFFFFFFU) +#define ENET_QOS_LOW_ADDRLO_SHIFT (0U) +/*! ADDRLO - MAC ADDRESS12 [31:0] This field contains the lower 32 bits of thirteenth 6-byte MAC address. */ +#define ENET_QOS_LOW_ADDRLO(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_LOW_ADDRLO_SHIFT)) & ENET_QOS_LOW_ADDRLO_MASK) +/*! @} */ + +/* The count of ENET_QOS_LOW */ +#define ENET_QOS_LOW_COUNT (64U) + +/*! @name MAC_MMC_CONTROL - MMC Control */ +/*! @{ */ + +#define ENET_QOS_MAC_MMC_CONTROL_CNTRST_MASK (0x1U) +#define ENET_QOS_MAC_MMC_CONTROL_CNTRST_SHIFT (0U) +/*! CNTRST - Counters Reset When this bit is set, all counters are reset. + * 0b0..Counters are not reset + * 0b1..All counters are reset + */ +#define ENET_QOS_MAC_MMC_CONTROL_CNTRST(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_CONTROL_CNTRST_SHIFT)) & ENET_QOS_MAC_MMC_CONTROL_CNTRST_MASK) + +#define ENET_QOS_MAC_MMC_CONTROL_CNTSTOPRO_MASK (0x2U) +#define ENET_QOS_MAC_MMC_CONTROL_CNTSTOPRO_SHIFT (1U) +/*! CNTSTOPRO - Counter Stop Rollover When this bit is set, the counter does not roll over to zero after reaching the maximum value. + * 0b0..Counter Stop Rollover is disabled + * 0b1..Counter Stop Rollover is enabled + */ +#define ENET_QOS_MAC_MMC_CONTROL_CNTSTOPRO(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_CONTROL_CNTSTOPRO_SHIFT)) & ENET_QOS_MAC_MMC_CONTROL_CNTSTOPRO_MASK) + +#define ENET_QOS_MAC_MMC_CONTROL_RSTONRD_MASK (0x4U) +#define ENET_QOS_MAC_MMC_CONTROL_RSTONRD_SHIFT (2U) +/*! RSTONRD - Reset on Read When this bit is set, the MMC counters are reset to zero after Read (self-clearing after reset). + * 0b0..Reset on Read is disabled + * 0b1..Reset on Read is enabled + */ +#define ENET_QOS_MAC_MMC_CONTROL_RSTONRD(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_CONTROL_RSTONRD_SHIFT)) & ENET_QOS_MAC_MMC_CONTROL_RSTONRD_MASK) + +#define ENET_QOS_MAC_MMC_CONTROL_CNTFREEZ_MASK (0x8U) +#define ENET_QOS_MAC_MMC_CONTROL_CNTFREEZ_SHIFT (3U) +/*! CNTFREEZ - MMC Counter Freeze When this bit is set, it freezes all MMC counters to their current value. + * 0b0..MMC Counter Freeze is disabled + * 0b1..MMC Counter Freeze is enabled + */ +#define ENET_QOS_MAC_MMC_CONTROL_CNTFREEZ(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_CONTROL_CNTFREEZ_SHIFT)) & ENET_QOS_MAC_MMC_CONTROL_CNTFREEZ_MASK) + +#define ENET_QOS_MAC_MMC_CONTROL_CNTPRST_MASK (0x10U) +#define ENET_QOS_MAC_MMC_CONTROL_CNTPRST_SHIFT (4U) +/*! CNTPRST - Counters Preset When this bit is set, all counters are initialized or preset to almost + * full or almost half according to the CNTPRSTLVL bit. + * 0b0..Counters Preset is disabled + * 0b1..Counters Preset is enabled + */ +#define ENET_QOS_MAC_MMC_CONTROL_CNTPRST(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_CONTROL_CNTPRST_SHIFT)) & ENET_QOS_MAC_MMC_CONTROL_CNTPRST_MASK) + +#define ENET_QOS_MAC_MMC_CONTROL_CNTPRSTLVL_MASK (0x20U) +#define ENET_QOS_MAC_MMC_CONTROL_CNTPRSTLVL_SHIFT (5U) +/*! CNTPRSTLVL - Full-Half Preset When this bit is low and the CNTPRST bit is set, all MMC counters get preset to almost-half value. + * 0b0..Full-Half Preset is disabled + * 0b1..Full-Half Preset is enabled + */ +#define ENET_QOS_MAC_MMC_CONTROL_CNTPRSTLVL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_CONTROL_CNTPRSTLVL_SHIFT)) & ENET_QOS_MAC_MMC_CONTROL_CNTPRSTLVL_MASK) + +#define ENET_QOS_MAC_MMC_CONTROL_UCDBC_MASK (0x100U) +#define ENET_QOS_MAC_MMC_CONTROL_UCDBC_SHIFT (8U) +/*! UCDBC - Update MMC Counters for Dropped Broadcast Packets Note: The CNTRST bit has a higher priority than the CNTPRST bit. + * 0b0..Update MMC Counters for Dropped Broadcast Packets is disabled + * 0b1..Update MMC Counters for Dropped Broadcast Packets is enabled + */ +#define ENET_QOS_MAC_MMC_CONTROL_UCDBC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_CONTROL_UCDBC_SHIFT)) & ENET_QOS_MAC_MMC_CONTROL_UCDBC_MASK) +/*! @} */ + +/*! @name MAC_MMC_RX_INTERRUPT - MMC Rx Interrupt */ +/*! @{ */ + +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXGBPKTIS_MASK (0x1U) +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXGBPKTIS_SHIFT (0U) +/*! RXGBPKTIS - MMC Receive Good Bad Packet Counter Interrupt Status This bit is set when the + * rxpacketcount_gb counter reaches half of the maximum value or the maximum value. + * 0b0..MMC Receive Good Bad Packet Counter Interrupt Status not detected + * 0b1..MMC Receive Good Bad Packet Counter Interrupt Status detected + */ +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXGBPKTIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RXGBPKTIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RXGBPKTIS_MASK) + +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXGBOCTIS_MASK (0x2U) +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXGBOCTIS_SHIFT (1U) +/*! RXGBOCTIS - MMC Receive Good Bad Octet Counter Interrupt Status This bit is set when the + * rxoctetcount_gb counter reaches half of the maximum value or the maximum value. + * 0b0..MMC Receive Good Bad Octet Counter Interrupt Status not detected + * 0b1..MMC Receive Good Bad Octet Counter Interrupt Status detected + */ +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXGBOCTIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RXGBOCTIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RXGBOCTIS_MASK) + +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXGOCTIS_MASK (0x4U) +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXGOCTIS_SHIFT (2U) +/*! RXGOCTIS - MMC Receive Good Octet Counter Interrupt Status This bit is set when the + * rxoctetcount_g counter reaches half of the maximum value or the maximum value. + * 0b0..MMC Receive Good Octet Counter Interrupt Status not detected + * 0b1..MMC Receive Good Octet Counter Interrupt Status detected + */ +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXGOCTIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RXGOCTIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RXGOCTIS_MASK) + +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXBCGPIS_MASK (0x8U) +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXBCGPIS_SHIFT (3U) +/*! RXBCGPIS - MMC Receive Broadcast Good Packet Counter Interrupt Status This bit is set when the + * rxbroadcastpackets_g counter reaches half of the maximum value or the maximum value. + * 0b0..MMC Receive Broadcast Good Packet Counter Interrupt Status not detected + * 0b1..MMC Receive Broadcast Good Packet Counter Interrupt Status detected + */ +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXBCGPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RXBCGPIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RXBCGPIS_MASK) + +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXMCGPIS_MASK (0x10U) +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXMCGPIS_SHIFT (4U) +/*! RXMCGPIS - MMC Receive Multicast Good Packet Counter Interrupt Status This bit is set when the + * rxmulticastpackets_g counter reaches half of the maximum value or the maximum value. + * 0b0..MMC Receive Multicast Good Packet Counter Interrupt Status not detected + * 0b1..MMC Receive Multicast Good Packet Counter Interrupt Status detected + */ +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXMCGPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RXMCGPIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RXMCGPIS_MASK) + +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXCRCERPIS_MASK (0x20U) +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXCRCERPIS_SHIFT (5U) +/*! RXCRCERPIS - MMC Receive CRC Error Packet Counter Interrupt Status This bit is set when the + * rxcrcerror counter reaches half of the maximum value or the maximum value. + * 0b0..MMC Receive CRC Error Packet Counter Interrupt Status not detected + * 0b1..MMC Receive CRC Error Packet Counter Interrupt Status detected + */ +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXCRCERPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RXCRCERPIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RXCRCERPIS_MASK) + +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXALGNERPIS_MASK (0x40U) +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXALGNERPIS_SHIFT (6U) +/*! RXALGNERPIS - MMC Receive Alignment Error Packet Counter Interrupt Status This bit is set when + * the rxalignmenterror counter reaches half of the maximum value or the maximum value. + * 0b0..MMC Receive Alignment Error Packet Counter Interrupt Status not detected + * 0b1..MMC Receive Alignment Error Packet Counter Interrupt Status detected + */ +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXALGNERPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RXALGNERPIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RXALGNERPIS_MASK) + +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXRUNTPIS_MASK (0x80U) +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXRUNTPIS_SHIFT (7U) +/*! RXRUNTPIS - MMC Receive Runt Packet Counter Interrupt Status This bit is set when the + * rxrunterror counter reaches half of the maximum value or the maximum value. + * 0b0..MMC Receive Runt Packet Counter Interrupt Status not detected + * 0b1..MMC Receive Runt Packet Counter Interrupt Status detected + */ +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXRUNTPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RXRUNTPIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RXRUNTPIS_MASK) + +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXJABERPIS_MASK (0x100U) +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXJABERPIS_SHIFT (8U) +/*! RXJABERPIS - MMC Receive Jabber Error Packet Counter Interrupt Status This bit is set when the + * rxjabbererror counter reaches half of the maximum value or the maximum value. + * 0b0..MMC Receive Jabber Error Packet Counter Interrupt Status not detected + * 0b1..MMC Receive Jabber Error Packet Counter Interrupt Status detected + */ +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXJABERPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RXJABERPIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RXJABERPIS_MASK) + +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXUSIZEGPIS_MASK (0x200U) +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXUSIZEGPIS_SHIFT (9U) +/*! RXUSIZEGPIS - MMC Receive Undersize Good Packet Counter Interrupt Status This bit is set when + * the rxundersize_g counter reaches half of the maximum value or the maximum value. + * 0b0..MMC Receive Undersize Good Packet Counter Interrupt Status not detected + * 0b1..MMC Receive Undersize Good Packet Counter Interrupt Status detected + */ +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXUSIZEGPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RXUSIZEGPIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RXUSIZEGPIS_MASK) + +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXOSIZEGPIS_MASK (0x400U) +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXOSIZEGPIS_SHIFT (10U) +/*! RXOSIZEGPIS - MMC Receive Oversize Good Packet Counter Interrupt Status This bit is set when the + * rxoversize_g counter reaches half of the maximum value or the maximum value. + * 0b0..MMC Receive Oversize Good Packet Counter Interrupt Status not detected + * 0b1..MMC Receive Oversize Good Packet Counter Interrupt Status detected + */ +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXOSIZEGPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RXOSIZEGPIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RXOSIZEGPIS_MASK) + +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RX64OCTGBPIS_MASK (0x800U) +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RX64OCTGBPIS_SHIFT (11U) +/*! RX64OCTGBPIS - MMC Receive 64 Octet Good Bad Packet Counter Interrupt Status This bit is set + * when the rx64octets_gb counter reaches half of the maximum value or the maximum value. + * 0b0..MMC Receive 64 Octet Good Bad Packet Counter Interrupt Status not detected + * 0b1..MMC Receive 64 Octet Good Bad Packet Counter Interrupt Status detected + */ +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RX64OCTGBPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RX64OCTGBPIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RX64OCTGBPIS_MASK) + +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RX65T127OCTGBPIS_MASK (0x1000U) +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RX65T127OCTGBPIS_SHIFT (12U) +/*! RX65T127OCTGBPIS - MMC Receive 65 to 127 Octet Good Bad Packet Counter Interrupt Status This bit + * is set when the rx65to127octets_gb counter reaches half of the maximum value or the maximum + * value. + * 0b0..MMC Receive 65 to 127 Octet Good Bad Packet Counter Interrupt Status not detected + * 0b1..MMC Receive 65 to 127 Octet Good Bad Packet Counter Interrupt Status detected + */ +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RX65T127OCTGBPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RX65T127OCTGBPIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RX65T127OCTGBPIS_MASK) + +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RX128T255OCTGBPIS_MASK (0x2000U) +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RX128T255OCTGBPIS_SHIFT (13U) +/*! RX128T255OCTGBPIS - MMC Receive 128 to 255 Octet Good Bad Packet Counter Interrupt Status This + * bit is set when the rx128to255octets_gb counter reaches half of the maximum value or the + * maximum value. + * 0b0..MMC Receive 128 to 255 Octet Good Bad Packet Counter Interrupt Status not detected + * 0b1..MMC Receive 128 to 255 Octet Good Bad Packet Counter Interrupt Status detected + */ +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RX128T255OCTGBPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RX128T255OCTGBPIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RX128T255OCTGBPIS_MASK) + +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RX256T511OCTGBPIS_MASK (0x4000U) +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RX256T511OCTGBPIS_SHIFT (14U) +/*! RX256T511OCTGBPIS - MMC Receive 256 to 511 Octet Good Bad Packet Counter Interrupt Status This + * bit is set when the rx256to511octets_gb counter reaches half of the maximum value or the + * maximum value. + * 0b0..MMC Receive 256 to 511 Octet Good Bad Packet Counter Interrupt Status not detected + * 0b1..MMC Receive 256 to 511 Octet Good Bad Packet Counter Interrupt Status detected + */ +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RX256T511OCTGBPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RX256T511OCTGBPIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RX256T511OCTGBPIS_MASK) + +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RX512T1023OCTGBPIS_MASK (0x8000U) +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RX512T1023OCTGBPIS_SHIFT (15U) +/*! RX512T1023OCTGBPIS - MMC Receive 512 to 1023 Octet Good Bad Packet Counter Interrupt Status This + * bit is set when the rx512to1023octets_gb counter reaches half of the maximum value or the + * maximum value. + * 0b0..MMC Receive 512 to 1023 Octet Good Bad Packet Counter Interrupt Status not detected + * 0b1..MMC Receive 512 to 1023 Octet Good Bad Packet Counter Interrupt Status detected + */ +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RX512T1023OCTGBPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RX512T1023OCTGBPIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RX512T1023OCTGBPIS_MASK) + +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RX1024TMAXOCTGBPIS_MASK (0x10000U) +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RX1024TMAXOCTGBPIS_SHIFT (16U) +/*! RX1024TMAXOCTGBPIS - MMC Receive 1024 to Maximum Octet Good Bad Packet Counter Interrupt Status + * This bit is set when the rx1024tomaxoctets_gb counter reaches half of the maximum value or the + * maximum value. + * 0b0..MMC Receive 1024 to Maximum Octet Good Bad Packet Counter Interrupt Status not detected + * 0b1..MMC Receive 1024 to Maximum Octet Good Bad Packet Counter Interrupt Status detected + */ +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RX1024TMAXOCTGBPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RX1024TMAXOCTGBPIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RX1024TMAXOCTGBPIS_MASK) + +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXUCGPIS_MASK (0x20000U) +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXUCGPIS_SHIFT (17U) +/*! RXUCGPIS - MMC Receive Unicast Good Packet Counter Interrupt Status This bit is set when the + * rxunicastpackets_g counter reaches half of the maximum value or the maximum value. + * 0b0..MMC Receive Unicast Good Packet Counter Interrupt Status not detected + * 0b1..MMC Receive Unicast Good Packet Counter Interrupt Status detected + */ +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXUCGPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RXUCGPIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RXUCGPIS_MASK) + +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXLENERPIS_MASK (0x40000U) +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXLENERPIS_SHIFT (18U) +/*! RXLENERPIS - MMC Receive Length Error Packet Counter Interrupt Status This bit is set when the + * rxlengtherror counter reaches half of the maximum value or the maximum value. + * 0b0..MMC Receive Length Error Packet Counter Interrupt Status not detected + * 0b1..MMC Receive Length Error Packet Counter Interrupt Status detected + */ +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXLENERPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RXLENERPIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RXLENERPIS_MASK) + +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXORANGEPIS_MASK (0x80000U) +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXORANGEPIS_SHIFT (19U) +/*! RXORANGEPIS - MMC Receive Out Of Range Error Packet Counter Interrupt Status. + * 0b0..MMC Receive Out Of Range Error Packet Counter Interrupt Status not detected + * 0b1..MMC Receive Out Of Range Error Packet Counter Interrupt Status detected + */ +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXORANGEPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RXORANGEPIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RXORANGEPIS_MASK) + +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXPAUSPIS_MASK (0x100000U) +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXPAUSPIS_SHIFT (20U) +/*! RXPAUSPIS - MMC Receive Pause Packet Counter Interrupt Status This bit is set when the + * rxpausepackets counter reaches half of the maximum value or the maximum value. + * 0b0..MMC Receive Pause Packet Counter Interrupt Status not detected + * 0b1..MMC Receive Pause Packet Counter Interrupt Status detected + */ +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXPAUSPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RXPAUSPIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RXPAUSPIS_MASK) + +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXFOVPIS_MASK (0x200000U) +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXFOVPIS_SHIFT (21U) +/*! RXFOVPIS - MMC Receive FIFO Overflow Packet Counter Interrupt Status This bit is set when the + * rxfifooverflow counter reaches half of the maximum value or the maximum value. + * 0b0..MMC Receive FIFO Overflow Packet Counter Interrupt Status not detected + * 0b1..MMC Receive FIFO Overflow Packet Counter Interrupt Status detected + */ +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXFOVPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RXFOVPIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RXFOVPIS_MASK) + +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXVLANGBPIS_MASK (0x400000U) +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXVLANGBPIS_SHIFT (22U) +/*! RXVLANGBPIS - MMC Receive VLAN Good Bad Packet Counter Interrupt Status This bit is set when the + * rxvlanpackets_gb counter reaches half of the maximum value or the maximum value. + * 0b0..MMC Receive VLAN Good Bad Packet Counter Interrupt Status not detected + * 0b1..MMC Receive VLAN Good Bad Packet Counter Interrupt Status detected + */ +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXVLANGBPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RXVLANGBPIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RXVLANGBPIS_MASK) + +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXWDOGPIS_MASK (0x800000U) +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXWDOGPIS_SHIFT (23U) +/*! RXWDOGPIS - MMC Receive Watchdog Error Packet Counter Interrupt Status This bit is set when the + * rxwatchdog error counter reaches half of the maximum value or the maximum value. + * 0b0..MMC Receive Watchdog Error Packet Counter Interrupt Status not detected + * 0b1..MMC Receive Watchdog Error Packet Counter Interrupt Status detected + */ +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXWDOGPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RXWDOGPIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RXWDOGPIS_MASK) + +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXRCVERRPIS_MASK (0x1000000U) +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXRCVERRPIS_SHIFT (24U) +/*! RXRCVERRPIS - MMC Receive Error Packet Counter Interrupt Status This bit is set when the + * rxrcverror counter reaches half of the maximum value or the maximum value. + * 0b0..MMC Receive Error Packet Counter Interrupt Status not detected + * 0b1..MMC Receive Error Packet Counter Interrupt Status detected + */ +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXRCVERRPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RXRCVERRPIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RXRCVERRPIS_MASK) + +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXCTRLPIS_MASK (0x2000000U) +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXCTRLPIS_SHIFT (25U) +/*! RXCTRLPIS - MMC Receive Control Packet Counter Interrupt Status This bit is set when the + * rxctrlpackets_g counter reaches half of the maximum value or the maximum value. + * 0b0..MMC Receive Control Packet Counter Interrupt Status not detected + * 0b1..MMC Receive Control Packet Counter Interrupt Status detected + */ +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXCTRLPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RXCTRLPIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RXCTRLPIS_MASK) + +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXLPIUSCIS_MASK (0x4000000U) +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXLPIUSCIS_SHIFT (26U) +/*! RXLPIUSCIS - MMC Receive LPI microsecond counter interrupt status This bit is set when the + * Rx_LPI_USEC_Cntr counter reaches half of the maximum value or the maximum value. + * 0b0..MMC Receive LPI microsecond Counter Interrupt Status not detected + * 0b1..MMC Receive LPI microsecond Counter Interrupt Status detected + */ +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXLPIUSCIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RXLPIUSCIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RXLPIUSCIS_MASK) + +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXLPITRCIS_MASK (0x8000000U) +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXLPITRCIS_SHIFT (27U) +/*! RXLPITRCIS - MMC Receive LPI transition counter interrupt status This bit is set when the + * Rx_LPI_Tran_Cntr counter reaches half of the maximum value or the maximum value. + * 0b0..MMC Receive LPI transition Counter Interrupt Status not detected + * 0b1..MMC Receive LPI transition Counter Interrupt Status detected + */ +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXLPITRCIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RXLPITRCIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RXLPITRCIS_MASK) +/*! @} */ + +/*! @name MAC_MMC_TX_INTERRUPT - MMC Tx Interrupt */ +/*! @{ */ + +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXGBOCTIS_MASK (0x1U) +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXGBOCTIS_SHIFT (0U) +/*! TXGBOCTIS - MMC Transmit Good Bad Octet Counter Interrupt Status This bit is set when the + * txoctetcount_gb counter reaches half of the maximum value or the maximum value. + * 0b0..MMC Transmit Good Bad Octet Counter Interrupt Status not detected + * 0b1..MMC Transmit Good Bad Octet Counter Interrupt Status detected + */ +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXGBOCTIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TXGBOCTIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TXGBOCTIS_MASK) + +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXGBPKTIS_MASK (0x2U) +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXGBPKTIS_SHIFT (1U) +/*! TXGBPKTIS - MMC Transmit Good Bad Packet Counter Interrupt Status This bit is set when the + * txpacketcount_gb counter reaches half of the maximum value or the maximum value. + * 0b0..MMC Transmit Good Bad Packet Counter Interrupt Status not detected + * 0b1..MMC Transmit Good Bad Packet Counter Interrupt Status detected + */ +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXGBPKTIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TXGBPKTIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TXGBPKTIS_MASK) + +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXBCGPIS_MASK (0x4U) +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXBCGPIS_SHIFT (2U) +/*! TXBCGPIS - MMC Transmit Broadcast Good Packet Counter Interrupt Status This bit is set when the + * txbroadcastpackets_g counter reaches half of the maximum value or the maximum value. + * 0b0..MMC Transmit Broadcast Good Packet Counter Interrupt Status not detected + * 0b1..MMC Transmit Broadcast Good Packet Counter Interrupt Status detected + */ +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXBCGPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TXBCGPIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TXBCGPIS_MASK) + +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXMCGPIS_MASK (0x8U) +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXMCGPIS_SHIFT (3U) +/*! TXMCGPIS - MMC Transmit Multicast Good Packet Counter Interrupt Status This bit is set when the + * txmulticastpackets_g counter reaches half of the maximum value or the maximum value. + * 0b0..MMC Transmit Multicast Good Packet Counter Interrupt Status not detected + * 0b1..MMC Transmit Multicast Good Packet Counter Interrupt Status detected + */ +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXMCGPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TXMCGPIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TXMCGPIS_MASK) + +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TX64OCTGBPIS_MASK (0x10U) +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TX64OCTGBPIS_SHIFT (4U) +/*! TX64OCTGBPIS - MMC Transmit 64 Octet Good Bad Packet Counter Interrupt Status This bit is set + * when the tx64octets_gb counter reaches half of the maximum value or the maximum value. + * 0b0..MMC Transmit 64 Octet Good Bad Packet Counter Interrupt Status not detected + * 0b1..MMC Transmit 64 Octet Good Bad Packet Counter Interrupt Status detected + */ +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TX64OCTGBPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TX64OCTGBPIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TX64OCTGBPIS_MASK) + +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TX65T127OCTGBPIS_MASK (0x20U) +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TX65T127OCTGBPIS_SHIFT (5U) +/*! TX65T127OCTGBPIS - MMC Transmit 65 to 127 Octet Good Bad Packet Counter Interrupt Status This + * bit is set when the tx65to127octets_gb counter reaches half the maximum value, and also when it + * reaches the maximum value. + * 0b0..MMC Transmit 65 to 127 Octet Good Bad Packet Counter Interrupt Status not detected + * 0b1..MMC Transmit 65 to 127 Octet Good Bad Packet Counter Interrupt Status detected + */ +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TX65T127OCTGBPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TX65T127OCTGBPIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TX65T127OCTGBPIS_MASK) + +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TX128T255OCTGBPIS_MASK (0x40U) +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TX128T255OCTGBPIS_SHIFT (6U) +/*! TX128T255OCTGBPIS - MMC Transmit 128 to 255 Octet Good Bad Packet Counter Interrupt Status This + * bit is set when the tx128to255octets_gb counter reaches half of the maximum value or the + * maximum value. + * 0b0..MMC Transmit 128 to 255 Octet Good Bad Packet Counter Interrupt Status not detected + * 0b1..MMC Transmit 128 to 255 Octet Good Bad Packet Counter Interrupt Status detected + */ +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TX128T255OCTGBPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TX128T255OCTGBPIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TX128T255OCTGBPIS_MASK) + +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TX256T511OCTGBPIS_MASK (0x80U) +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TX256T511OCTGBPIS_SHIFT (7U) +/*! TX256T511OCTGBPIS - MMC Transmit 256 to 511 Octet Good Bad Packet Counter Interrupt Status This + * bit is set when the tx256to511octets_gb counter reaches half of the maximum value or the + * maximum value. + * 0b0..MMC Transmit 256 to 511 Octet Good Bad Packet Counter Interrupt Status not detected + * 0b1..MMC Transmit 256 to 511 Octet Good Bad Packet Counter Interrupt Status detected + */ +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TX256T511OCTGBPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TX256T511OCTGBPIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TX256T511OCTGBPIS_MASK) + +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TX512T1023OCTGBPIS_MASK (0x100U) +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TX512T1023OCTGBPIS_SHIFT (8U) +/*! TX512T1023OCTGBPIS - MMC Transmit 512 to 1023 Octet Good Bad Packet Counter Interrupt Status + * This bit is set when the tx512to1023octets_gb counter reaches half of the maximum value or the + * maximum value. + * 0b0..MMC Transmit 512 to 1023 Octet Good Bad Packet Counter Interrupt Status not detected + * 0b1..MMC Transmit 512 to 1023 Octet Good Bad Packet Counter Interrupt Status detected + */ +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TX512T1023OCTGBPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TX512T1023OCTGBPIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TX512T1023OCTGBPIS_MASK) + +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TX1024TMAXOCTGBPIS_MASK (0x200U) +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TX1024TMAXOCTGBPIS_SHIFT (9U) +/*! TX1024TMAXOCTGBPIS - MMC Transmit 1024 to Maximum Octet Good Bad Packet Counter Interrupt Status + * This bit is set when the tx1024tomaxoctets_gb counter reaches half of the maximum value or + * the maximum value. + * 0b0..MMC Transmit 1024 to Maximum Octet Good Bad Packet Counter Interrupt Status not detected + * 0b1..MMC Transmit 1024 to Maximum Octet Good Bad Packet Counter Interrupt Status detected + */ +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TX1024TMAXOCTGBPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TX1024TMAXOCTGBPIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TX1024TMAXOCTGBPIS_MASK) + +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXUCGBPIS_MASK (0x400U) +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXUCGBPIS_SHIFT (10U) +/*! TXUCGBPIS - MMC Transmit Unicast Good Bad Packet Counter Interrupt Status This bit is set when + * the txunicastpackets_gb counter reaches half of the maximum value or the maximum value. + * 0b0..MMC Transmit Unicast Good Bad Packet Counter Interrupt Status not detected + * 0b1..MMC Transmit Unicast Good Bad Packet Counter Interrupt Status detected + */ +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXUCGBPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TXUCGBPIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TXUCGBPIS_MASK) + +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXMCGBPIS_MASK (0x800U) +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXMCGBPIS_SHIFT (11U) +/*! TXMCGBPIS - MMC Transmit Multicast Good Bad Packet Counter Interrupt Status The bit is set when + * the txmulticastpackets_gb counter reaches half of the maximum value or the maximum value. + * 0b0..MMC Transmit Multicast Good Bad Packet Counter Interrupt Status not detected + * 0b1..MMC Transmit Multicast Good Bad Packet Counter Interrupt Status detected + */ +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXMCGBPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TXMCGBPIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TXMCGBPIS_MASK) + +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXBCGBPIS_MASK (0x1000U) +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXBCGBPIS_SHIFT (12U) +/*! TXBCGBPIS - MMC Transmit Broadcast Good Bad Packet Counter Interrupt Status This bit is set when + * the txbroadcastpackets_gb counter reaches half of the maximum value or the maximum value. + * 0b0..MMC Transmit Broadcast Good Bad Packet Counter Interrupt Status not detected + * 0b1..MMC Transmit Broadcast Good Bad Packet Counter Interrupt Status detected + */ +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXBCGBPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TXBCGBPIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TXBCGBPIS_MASK) + +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXUFLOWERPIS_MASK (0x2000U) +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXUFLOWERPIS_SHIFT (13U) +/*! TXUFLOWERPIS - MMC Transmit Underflow Error Packet Counter Interrupt Status This bit is set when + * the txunderflowerror counter reaches half of the maximum value or the maximum value. + * 0b0..MMC Transmit Underflow Error Packet Counter Interrupt Status not detected + * 0b1..MMC Transmit Underflow Error Packet Counter Interrupt Status detected + */ +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXUFLOWERPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TXUFLOWERPIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TXUFLOWERPIS_MASK) + +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXSCOLGPIS_MASK (0x4000U) +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXSCOLGPIS_SHIFT (14U) +/*! TXSCOLGPIS - MMC Transmit Single Collision Good Packet Counter Interrupt Status This bit is set + * when the txsinglecol_g counter reaches half of the maximum value or the maximum value. + * 0b0..MMC Transmit Single Collision Good Packet Counter Interrupt Status not detected + * 0b1..MMC Transmit Single Collision Good Packet Counter Interrupt Status detected + */ +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXSCOLGPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TXSCOLGPIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TXSCOLGPIS_MASK) + +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXMCOLGPIS_MASK (0x8000U) +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXMCOLGPIS_SHIFT (15U) +/*! TXMCOLGPIS - MMC Transmit Multiple Collision Good Packet Counter Interrupt Status This bit is + * set when the txmulticol_g counter reaches half of the maximum value or the maximum value. + * 0b0..MMC Transmit Multiple Collision Good Packet Counter Interrupt Status not detected + * 0b1..MMC Transmit Multiple Collision Good Packet Counter Interrupt Status detected + */ +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXMCOLGPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TXMCOLGPIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TXMCOLGPIS_MASK) + +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXDEFPIS_MASK (0x10000U) +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXDEFPIS_SHIFT (16U) +/*! TXDEFPIS - MMC Transmit Deferred Packet Counter Interrupt Status This bit is set when the + * txdeferred counter reaches half of the maximum value or the maximum value. + * 0b0..MMC Transmit Deferred Packet Counter Interrupt Status not detected + * 0b1..MMC Transmit Deferred Packet Counter Interrupt Status detected + */ +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXDEFPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TXDEFPIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TXDEFPIS_MASK) + +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXLATCOLPIS_MASK (0x20000U) +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXLATCOLPIS_SHIFT (17U) +/*! TXLATCOLPIS - MMC Transmit Late Collision Packet Counter Interrupt Status This bit is set when + * the txlatecol counter reaches half of the maximum value or the maximum value. + * 0b0..MMC Transmit Late Collision Packet Counter Interrupt Status not detected + * 0b1..MMC Transmit Late Collision Packet Counter Interrupt Status detected + */ +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXLATCOLPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TXLATCOLPIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TXLATCOLPIS_MASK) + +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXEXCOLPIS_MASK (0x40000U) +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXEXCOLPIS_SHIFT (18U) +/*! TXEXCOLPIS - MMC Transmit Excessive Collision Packet Counter Interrupt Status This bit is set + * when the txexesscol counter reaches half of the maximum value or the maximum value. + * 0b0..MMC Transmit Excessive Collision Packet Counter Interrupt Status not detected + * 0b1..MMC Transmit Excessive Collision Packet Counter Interrupt Status detected + */ +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXEXCOLPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TXEXCOLPIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TXEXCOLPIS_MASK) + +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXCARERPIS_MASK (0x80000U) +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXCARERPIS_SHIFT (19U) +/*! TXCARERPIS - MMC Transmit Carrier Error Packet Counter Interrupt Status This bit is set when the + * txcarriererror counter reaches half of the maximum value or the maximum value. + * 0b0..MMC Transmit Carrier Error Packet Counter Interrupt Status not detected + * 0b1..MMC Transmit Carrier Error Packet Counter Interrupt Status detected + */ +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXCARERPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TXCARERPIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TXCARERPIS_MASK) + +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXGOCTIS_MASK (0x100000U) +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXGOCTIS_SHIFT (20U) +/*! TXGOCTIS - MMC Transmit Good Octet Counter Interrupt Status This bit is set when the + * txoctetcount_g counter reaches half of the maximum value or the maximum value. + * 0b0..MMC Transmit Good Octet Counter Interrupt Status not detected + * 0b1..MMC Transmit Good Octet Counter Interrupt Status detected + */ +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXGOCTIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TXGOCTIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TXGOCTIS_MASK) + +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXGPKTIS_MASK (0x200000U) +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXGPKTIS_SHIFT (21U) +/*! TXGPKTIS - MMC Transmit Good Packet Counter Interrupt Status This bit is set when the + * txpacketcount_g counter reaches half of the maximum value or the maximum value. + * 0b0..MMC Transmit Good Packet Counter Interrupt Status not detected + * 0b1..MMC Transmit Good Packet Counter Interrupt Status detected + */ +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXGPKTIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TXGPKTIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TXGPKTIS_MASK) + +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXEXDEFPIS_MASK (0x400000U) +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXEXDEFPIS_SHIFT (22U) +/*! TXEXDEFPIS - MMC Transmit Excessive Deferral Packet Counter Interrupt Status This bit is set + * when the txexcessdef counter reaches half of the maximum value or the maximum value. + * 0b0..MMC Transmit Excessive Deferral Packet Counter Interrupt Status not detected + * 0b1..MMC Transmit Excessive Deferral Packet Counter Interrupt Status detected + */ +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXEXDEFPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TXEXDEFPIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TXEXDEFPIS_MASK) + +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXPAUSPIS_MASK (0x800000U) +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXPAUSPIS_SHIFT (23U) +/*! TXPAUSPIS - MMC Transmit Pause Packet Counter Interrupt Status This bit is set when the + * txpausepacketserror counter reaches half of the maximum value or the maximum value. + * 0b0..MMC Transmit Pause Packet Counter Interrupt Status not detected + * 0b1..MMC Transmit Pause Packet Counter Interrupt Status detected + */ +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXPAUSPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TXPAUSPIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TXPAUSPIS_MASK) + +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXVLANGPIS_MASK (0x1000000U) +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXVLANGPIS_SHIFT (24U) +/*! TXVLANGPIS - MMC Transmit VLAN Good Packet Counter Interrupt Status This bit is set when the + * txvlanpackets_g counter reaches half of the maximum value or the maximum value. + * 0b0..MMC Transmit VLAN Good Packet Counter Interrupt Status not detected + * 0b1..MMC Transmit VLAN Good Packet Counter Interrupt Status detected + */ +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXVLANGPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TXVLANGPIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TXVLANGPIS_MASK) + +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXOSIZEGPIS_MASK (0x2000000U) +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXOSIZEGPIS_SHIFT (25U) +/*! TXOSIZEGPIS - MMC Transmit Oversize Good Packet Counter Interrupt Status This bit is set when + * the txoversize_g counter reaches half of the maximum value or the maximum value. + * 0b0..MMC Transmit Oversize Good Packet Counter Interrupt Status not detected + * 0b1..MMC Transmit Oversize Good Packet Counter Interrupt Status detected + */ +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXOSIZEGPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TXOSIZEGPIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TXOSIZEGPIS_MASK) + +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXLPIUSCIS_MASK (0x4000000U) +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXLPIUSCIS_SHIFT (26U) +/*! TXLPIUSCIS - MMC Transmit LPI microsecond counter interrupt status This bit is set when the + * Tx_LPI_USEC_Cntr counter reaches half of the maximum value or the maximum value. + * 0b0..MMC Transmit LPI microsecond Counter Interrupt Status not detected + * 0b1..MMC Transmit LPI microsecond Counter Interrupt Status detected + */ +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXLPIUSCIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TXLPIUSCIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TXLPIUSCIS_MASK) + +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXLPITRCIS_MASK (0x8000000U) +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXLPITRCIS_SHIFT (27U) +/*! TXLPITRCIS - MMC Transmit LPI transition counter interrupt status This bit is set when the + * Tx_LPI_Tran_Cntr counter reaches half of the maximum value or the maximum value. + * 0b0..MMC Transmit LPI transition Counter Interrupt Status not detected + * 0b1..MMC Transmit LPI transition Counter Interrupt Status detected + */ +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXLPITRCIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TXLPITRCIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TXLPITRCIS_MASK) +/*! @} */ + +/*! @name MAC_MMC_RX_INTERRUPT_MASK - MMC Rx Interrupt Mask */ +/*! @{ */ + +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXGBPKTIM_MASK (0x1U) +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXGBPKTIM_SHIFT (0U) +/*! RXGBPKTIM - MMC Receive Good Bad Packet Counter Interrupt Mask Setting this bit masks the + * interrupt when the rxpacketcount_gb counter reaches half of the maximum value or the maximum value. + * 0b0..MMC Receive Good Bad Packet Counter Interrupt Mask is disabled + * 0b1..MMC Receive Good Bad Packet Counter Interrupt Mask is enabled + */ +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXGBPKTIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXGBPKTIM_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXGBPKTIM_MASK) + +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXGBOCTIM_MASK (0x2U) +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXGBOCTIM_SHIFT (1U) +/*! RXGBOCTIM - MMC Receive Good Bad Octet Counter Interrupt Mask Setting this bit masks the + * interrupt when the rxoctetcount_gb counter reaches half of the maximum value or the maximum value. + * 0b0..MMC Receive Good Bad Octet Counter Interrupt Mask is disabled + * 0b1..MMC Receive Good Bad Octet Counter Interrupt Mask is enabled + */ +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXGBOCTIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXGBOCTIM_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXGBOCTIM_MASK) + +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXGOCTIM_MASK (0x4U) +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXGOCTIM_SHIFT (2U) +/*! RXGOCTIM - MMC Receive Good Octet Counter Interrupt Mask Setting this bit masks the interrupt + * when the rxoctetcount_g counter reaches half of the maximum value or the maximum value. + * 0b0..MMC Receive Good Octet Counter Interrupt Mask is disabled + * 0b1..MMC Receive Good Octet Counter Interrupt Mask is enabled + */ +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXGOCTIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXGOCTIM_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXGOCTIM_MASK) + +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXBCGPIM_MASK (0x8U) +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXBCGPIM_SHIFT (3U) +/*! RXBCGPIM - MMC Receive Broadcast Good Packet Counter Interrupt Mask Setting this bit masks the + * interrupt when the rxbroadcastpackets_g counter reaches half of the maximum value or the + * maximum value. + * 0b0..MMC Receive Broadcast Good Packet Counter Interrupt Mask is disabled + * 0b1..MMC Receive Broadcast Good Packet Counter Interrupt Mask is enabled + */ +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXBCGPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXBCGPIM_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXBCGPIM_MASK) + +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXMCGPIM_MASK (0x10U) +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXMCGPIM_SHIFT (4U) +/*! RXMCGPIM - MMC Receive Multicast Good Packet Counter Interrupt Mask Setting this bit masks the + * interrupt when the rxmulticastpackets_g counter reaches half of the maximum value or the + * maximum value. + * 0b0..MMC Receive Multicast Good Packet Counter Interrupt Mask is disabled + * 0b1..MMC Receive Multicast Good Packet Counter Interrupt Mask is enabled + */ +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXMCGPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXMCGPIM_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXMCGPIM_MASK) + +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXCRCERPIM_MASK (0x20U) +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXCRCERPIM_SHIFT (5U) +/*! RXCRCERPIM - MMC Receive CRC Error Packet Counter Interrupt Mask Setting this bit masks the + * interrupt when the rxcrcerror counter reaches half of the maximum value or the maximum value. + * 0b0..MMC Receive CRC Error Packet Counter Interrupt Mask is disabled + * 0b1..MMC Receive CRC Error Packet Counter Interrupt Mask is enabled + */ +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXCRCERPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXCRCERPIM_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXCRCERPIM_MASK) + +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXALGNERPIM_MASK (0x40U) +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXALGNERPIM_SHIFT (6U) +/*! RXALGNERPIM - MMC Receive Alignment Error Packet Counter Interrupt Mask Setting this bit masks + * the interrupt when the rxalignmenterror counter reaches half of the maximum value or the + * maximum value. + * 0b0..MMC Receive Alignment Error Packet Counter Interrupt Mask is disabled + * 0b1..MMC Receive Alignment Error Packet Counter Interrupt Mask is enabled + */ +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXALGNERPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXALGNERPIM_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXALGNERPIM_MASK) + +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXRUNTPIM_MASK (0x80U) +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXRUNTPIM_SHIFT (7U) +/*! RXRUNTPIM - MMC Receive Runt Packet Counter Interrupt Mask Setting this bit masks the interrupt + * when the rxrunterror counter reaches half of the maximum value or the maximum value. + * 0b0..MMC Receive Runt Packet Counter Interrupt Mask is disabled + * 0b1..MMC Receive Runt Packet Counter Interrupt Mask is enabled + */ +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXRUNTPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXRUNTPIM_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXRUNTPIM_MASK) + +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXJABERPIM_MASK (0x100U) +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXJABERPIM_SHIFT (8U) +/*! RXJABERPIM - MMC Receive Jabber Error Packet Counter Interrupt Mask Setting this bit masks the + * interrupt when the rxjabbererror counter reaches half of the maximum value or the maximum value. + * 0b0..MMC Receive Jabber Error Packet Counter Interrupt Mask is disabled + * 0b1..MMC Receive Jabber Error Packet Counter Interrupt Mask is enabled + */ +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXJABERPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXJABERPIM_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXJABERPIM_MASK) + +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXUSIZEGPIM_MASK (0x200U) +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXUSIZEGPIM_SHIFT (9U) +/*! RXUSIZEGPIM - MMC Receive Undersize Good Packet Counter Interrupt Mask Setting this bit masks + * the interrupt when the rxundersize_g counter reaches half of the maximum value or the maximum + * value. + * 0b0..MMC Receive Undersize Good Packet Counter Interrupt Mask is disabled + * 0b1..MMC Receive Undersize Good Packet Counter Interrupt Mask is enabled + */ +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXUSIZEGPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXUSIZEGPIM_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXUSIZEGPIM_MASK) + +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXOSIZEGPIM_MASK (0x400U) +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXOSIZEGPIM_SHIFT (10U) +/*! RXOSIZEGPIM - MMC Receive Oversize Good Packet Counter Interrupt Mask Setting this bit masks the + * interrupt when the rxoversize_g counter reaches half of the maximum value or the maximum + * value. + * 0b0..MMC Receive Oversize Good Packet Counter Interrupt Mask is disabled + * 0b1..MMC Receive Oversize Good Packet Counter Interrupt Mask is enabled + */ +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXOSIZEGPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXOSIZEGPIM_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXOSIZEGPIM_MASK) + +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RX64OCTGBPIM_MASK (0x800U) +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RX64OCTGBPIM_SHIFT (11U) +/*! RX64OCTGBPIM - MMC Receive 64 Octet Good Bad Packet Counter Interrupt Mask Setting this bit + * masks the interrupt when the rx64octets_gb counter reaches half of the maximum value or the + * maximum value. + * 0b0..MMC Receive 64 Octet Good Bad Packet Counter Interrupt Mask is disabled + * 0b1..MMC Receive 64 Octet Good Bad Packet Counter Interrupt Mask is enabled + */ +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RX64OCTGBPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RX64OCTGBPIM_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RX64OCTGBPIM_MASK) + +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RX65T127OCTGBPIM_MASK (0x1000U) +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RX65T127OCTGBPIM_SHIFT (12U) +/*! RX65T127OCTGBPIM - MMC Receive 65 to 127 Octet Good Bad Packet Counter Interrupt Mask Setting + * this bit masks the interrupt when the rx65to127octets_gb counter reaches half of the maximum + * value or the maximum value. + * 0b0..MMC Receive 65 to 127 Octet Good Bad Packet Counter Interrupt Mask is disabled + * 0b1..MMC Receive 65 to 127 Octet Good Bad Packet Counter Interrupt Mask is enabled + */ +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RX65T127OCTGBPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RX65T127OCTGBPIM_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RX65T127OCTGBPIM_MASK) + +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RX128T255OCTGBPIM_MASK (0x2000U) +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RX128T255OCTGBPIM_SHIFT (13U) +/*! RX128T255OCTGBPIM - MMC Receive 128 to 255 Octet Good Bad Packet Counter Interrupt Mask Setting + * this bit masks the interrupt when the rx128to255octets_gb counter reaches half of the maximum + * value or the maximum value. + * 0b0..MMC Receive 128 to 255 Octet Good Bad Packet Counter Interrupt Mask is disabled + * 0b1..MMC Receive 128 to 255 Octet Good Bad Packet Counter Interrupt Mask is enabled + */ +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RX128T255OCTGBPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RX128T255OCTGBPIM_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RX128T255OCTGBPIM_MASK) + +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RX256T511OCTGBPIM_MASK (0x4000U) +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RX256T511OCTGBPIM_SHIFT (14U) +/*! RX256T511OCTGBPIM - MMC Receive 256 to 511 Octet Good Bad Packet Counter Interrupt Mask Setting + * this bit masks the interrupt when the rx256to511octets_gb counter reaches half of the maximum + * value or the maximum value. + * 0b0..MMC Receive 256 to 511 Octet Good Bad Packet Counter Interrupt Mask is disabled + * 0b1..MMC Receive 256 to 511 Octet Good Bad Packet Counter Interrupt Mask is enabled + */ +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RX256T511OCTGBPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RX256T511OCTGBPIM_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RX256T511OCTGBPIM_MASK) + +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RX512T1023OCTGBPIM_MASK (0x8000U) +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RX512T1023OCTGBPIM_SHIFT (15U) +/*! RX512T1023OCTGBPIM - MMC Receive 512 to 1023 Octet Good Bad Packet Counter Interrupt Mask + * Setting this bit masks the interrupt when the rx512to1023octets_gb counter reaches half of the + * maximum value or the maximum value. + * 0b0..MMC Receive 512 to 1023 Octet Good Bad Packet Counter Interrupt Mask is disabled + * 0b1..MMC Receive 512 to 1023 Octet Good Bad Packet Counter Interrupt Mask is enabled + */ +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RX512T1023OCTGBPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RX512T1023OCTGBPIM_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RX512T1023OCTGBPIM_MASK) + +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RX1024TMAXOCTGBPIM_MASK (0x10000U) +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RX1024TMAXOCTGBPIM_SHIFT (16U) +/*! RX1024TMAXOCTGBPIM - MMC Receive 1024 to Maximum Octet Good Bad Packet Counter Interrupt Mask. + * 0b0..MMC Receive 1024 to Maximum Octet Good Bad Packet Counter Interrupt Mask is disabled + * 0b1..MMC Receive 1024 to Maximum Octet Good Bad Packet Counter Interrupt Mask is enabled + */ +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RX1024TMAXOCTGBPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RX1024TMAXOCTGBPIM_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RX1024TMAXOCTGBPIM_MASK) + +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXUCGPIM_MASK (0x20000U) +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXUCGPIM_SHIFT (17U) +/*! RXUCGPIM - MMC Receive Unicast Good Packet Counter Interrupt Mask Setting this bit masks the + * interrupt when the rxunicastpackets_g counter reaches half of the maximum value or the maximum + * value. + * 0b0..MMC Receive Unicast Good Packet Counter Interrupt Mask is disabled + * 0b1..MMC Receive Unicast Good Packet Counter Interrupt Mask is enabled + */ +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXUCGPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXUCGPIM_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXUCGPIM_MASK) + +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXLENERPIM_MASK (0x40000U) +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXLENERPIM_SHIFT (18U) +/*! RXLENERPIM - MMC Receive Length Error Packet Counter Interrupt Mask Setting this bit masks the + * interrupt when the rxlengtherror counter reaches half of the maximum value or the maximum value. + * 0b0..MMC Receive Length Error Packet Counter Interrupt Mask is disabled + * 0b1..MMC Receive Length Error Packet Counter Interrupt Mask is enabled + */ +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXLENERPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXLENERPIM_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXLENERPIM_MASK) + +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXORANGEPIM_MASK (0x80000U) +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXORANGEPIM_SHIFT (19U) +/*! RXORANGEPIM - MMC Receive Out Of Range Error Packet Counter Interrupt Mask Setting this bit + * masks the interrupt when the rxoutofrangetype counter reaches half of the maximum value or the + * maximum value. + * 0b0..MMC Receive Out Of Range Error Packet Counter Interrupt Mask is disabled + * 0b1..MMC Receive Out Of Range Error Packet Counter Interrupt Mask is enabled + */ +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXORANGEPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXORANGEPIM_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXORANGEPIM_MASK) + +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXPAUSPIM_MASK (0x100000U) +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXPAUSPIM_SHIFT (20U) +/*! RXPAUSPIM - MMC Receive Pause Packet Counter Interrupt Mask Setting this bit masks the interrupt + * when the rxpausepackets counter reaches half of the maximum value or the maximum value. + * 0b0..MMC Receive Pause Packet Counter Interrupt Mask is disabled + * 0b1..MMC Receive Pause Packet Counter Interrupt Mask is enabled + */ +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXPAUSPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXPAUSPIM_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXPAUSPIM_MASK) + +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXFOVPIM_MASK (0x200000U) +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXFOVPIM_SHIFT (21U) +/*! RXFOVPIM - MMC Receive FIFO Overflow Packet Counter Interrupt Mask Setting this bit masks the + * interrupt when the rxfifooverflow counter reaches half of the maximum value or the maximum value. + * 0b0..MMC Receive FIFO Overflow Packet Counter Interrupt Mask is disabled + * 0b1..MMC Receive FIFO Overflow Packet Counter Interrupt Mask is enabled + */ +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXFOVPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXFOVPIM_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXFOVPIM_MASK) + +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXVLANGBPIM_MASK (0x400000U) +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXVLANGBPIM_SHIFT (22U) +/*! RXVLANGBPIM - MMC Receive VLAN Good Bad Packet Counter Interrupt Mask Setting this bit masks the + * interrupt when the rxvlanpackets_gb counter reaches half of the maximum value or the maximum + * value. + * 0b0..MMC Receive VLAN Good Bad Packet Counter Interrupt Mask is disabled + * 0b1..MMC Receive VLAN Good Bad Packet Counter Interrupt Mask is enabled + */ +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXVLANGBPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXVLANGBPIM_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXVLANGBPIM_MASK) + +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXWDOGPIM_MASK (0x800000U) +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXWDOGPIM_SHIFT (23U) +/*! RXWDOGPIM - MMC Receive Watchdog Error Packet Counter Interrupt Mask Setting this bit masks the + * interrupt when the rxwatchdog counter reaches half of the maximum value or the maximum value. + * 0b0..MMC Receive Watchdog Error Packet Counter Interrupt Mask is disabled + * 0b1..MMC Receive Watchdog Error Packet Counter Interrupt Mask is enabled + */ +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXWDOGPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXWDOGPIM_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXWDOGPIM_MASK) + +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXRCVERRPIM_MASK (0x1000000U) +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXRCVERRPIM_SHIFT (24U) +/*! RXRCVERRPIM - MMC Receive Error Packet Counter Interrupt Mask Setting this bit masks the + * interrupt when the rxrcverror counter reaches half of the maximum value or the maximum value. + * 0b0..MMC Receive Error Packet Counter Interrupt Mask is disabled + * 0b1..MMC Receive Error Packet Counter Interrupt Mask is enabled + */ +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXRCVERRPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXRCVERRPIM_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXRCVERRPIM_MASK) + +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXCTRLPIM_MASK (0x2000000U) +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXCTRLPIM_SHIFT (25U) +/*! RXCTRLPIM - MMC Receive Control Packet Counter Interrupt Mask Setting this bit masks the + * interrupt when the rxctrlpackets_g counter reaches half of the maximum value or the maximum value. + * 0b0..MMC Receive Control Packet Counter Interrupt Mask is disabled + * 0b1..MMC Receive Control Packet Counter Interrupt Mask is enabled + */ +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXCTRLPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXCTRLPIM_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXCTRLPIM_MASK) + +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXLPIUSCIM_MASK (0x4000000U) +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXLPIUSCIM_SHIFT (26U) +/*! RXLPIUSCIM - MMC Receive LPI microsecond counter interrupt Mask Setting this bit masks the + * interrupt when the Rx_LPI_USEC_Cntr counter reaches half of the maximum value or the maximum value. + * 0b0..MMC Receive LPI microsecond counter interrupt Mask is disabled + * 0b1..MMC Receive LPI microsecond counter interrupt Mask is enabled + */ +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXLPIUSCIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXLPIUSCIM_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXLPIUSCIM_MASK) + +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXLPITRCIM_MASK (0x8000000U) +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXLPITRCIM_SHIFT (27U) +/*! RXLPITRCIM - MMC Receive LPI transition counter interrupt Mask Setting this bit masks the + * interrupt when the Rx_LPI_Tran_Cntr counter reaches half of the maximum value or the maximum value. + * 0b0..MMC Receive LPI transition counter interrupt Mask is disabled + * 0b1..MMC Receive LPI transition counter interrupt Mask is enabled + */ +#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXLPITRCIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXLPITRCIM_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXLPITRCIM_MASK) +/*! @} */ + +/*! @name MAC_MMC_TX_INTERRUPT_MASK - MMC Tx Interrupt Mask */ +/*! @{ */ + +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXGBOCTIM_MASK (0x1U) +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXGBOCTIM_SHIFT (0U) +/*! TXGBOCTIM - MMC Transmit Good Bad Octet Counter Interrupt Mask Setting this bit masks the + * interrupt when the txoctetcount_gb counter reaches half of the maximum value or the maximum value. + * 0b0..MMC Transmit Good Bad Octet Counter Interrupt Mask is disabled + * 0b1..MMC Transmit Good Bad Octet Counter Interrupt Mask is enabled + */ +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXGBOCTIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXGBOCTIM_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXGBOCTIM_MASK) + +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXGBPKTIM_MASK (0x2U) +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXGBPKTIM_SHIFT (1U) +/*! TXGBPKTIM - MMC Transmit Good Bad Packet Counter Interrupt Mask Setting this bit masks the + * interrupt when the txpacketcount_gb counter reaches half of the maximum value or the maximum value. + * 0b0..MMC Transmit Good Bad Packet Counter Interrupt Mask is disabled + * 0b1..MMC Transmit Good Bad Packet Counter Interrupt Mask is enabled + */ +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXGBPKTIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXGBPKTIM_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXGBPKTIM_MASK) + +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXBCGPIM_MASK (0x4U) +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXBCGPIM_SHIFT (2U) +/*! TXBCGPIM - MMC Transmit Broadcast Good Packet Counter Interrupt Mask Setting this bit masks the + * interrupt when the txbroadcastpackets_g counter reaches half of the maximum value or the + * maximum value. + * 0b0..MMC Transmit Broadcast Good Packet Counter Interrupt Mask is disabled + * 0b1..MMC Transmit Broadcast Good Packet Counter Interrupt Mask is enabled + */ +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXBCGPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXBCGPIM_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXBCGPIM_MASK) + +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXMCGPIM_MASK (0x8U) +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXMCGPIM_SHIFT (3U) +/*! TXMCGPIM - MMC Transmit Multicast Good Packet Counter Interrupt Mask Setting this bit masks the + * interrupt when the txmulticastpackets_g counter reaches half of the maximum value or the + * maximum value. + * 0b0..MMC Transmit Multicast Good Packet Counter Interrupt Mask is disabled + * 0b1..MMC Transmit Multicast Good Packet Counter Interrupt Mask is enabled + */ +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXMCGPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXMCGPIM_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXMCGPIM_MASK) + +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TX64OCTGBPIM_MASK (0x10U) +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TX64OCTGBPIM_SHIFT (4U) +/*! TX64OCTGBPIM - MMC Transmit 64 Octet Good Bad Packet Counter Interrupt Mask Setting this bit + * masks the interrupt when the tx64octets_gb counter reaches half of the maximum value or the + * maximum value. + * 0b0..MMC Transmit 64 Octet Good Bad Packet Counter Interrupt Mask is disabled + * 0b1..MMC Transmit 64 Octet Good Bad Packet Counter Interrupt Mask is enabled + */ +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TX64OCTGBPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TX64OCTGBPIM_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TX64OCTGBPIM_MASK) + +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TX65T127OCTGBPIM_MASK (0x20U) +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TX65T127OCTGBPIM_SHIFT (5U) +/*! TX65T127OCTGBPIM - MMC Transmit 65 to 127 Octet Good Bad Packet Counter Interrupt Mask Setting + * this bit masks the interrupt when the tx65to127octets_gb counter reaches half of the maximum + * value or the maximum value. + * 0b0..MMC Transmit 65 to 127 Octet Good Bad Packet Counter Interrupt Mask is disabled + * 0b1..MMC Transmit 65 to 127 Octet Good Bad Packet Counter Interrupt Mask is enabled + */ +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TX65T127OCTGBPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TX65T127OCTGBPIM_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TX65T127OCTGBPIM_MASK) + +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TX128T255OCTGBPIM_MASK (0x40U) +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TX128T255OCTGBPIM_SHIFT (6U) +/*! TX128T255OCTGBPIM - MMC Transmit 128 to 255 Octet Good Bad Packet Counter Interrupt Mask Setting + * this bit masks the interrupt when the tx128to255octets_gb counter reaches half of the maximum + * value or the maximum value. + * 0b0..MMC Transmit 128 to 255 Octet Good Bad Packet Counter Interrupt Mask is disabled + * 0b1..MMC Transmit 128 to 255 Octet Good Bad Packet Counter Interrupt Mask is enabled + */ +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TX128T255OCTGBPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TX128T255OCTGBPIM_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TX128T255OCTGBPIM_MASK) + +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TX256T511OCTGBPIM_MASK (0x80U) +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TX256T511OCTGBPIM_SHIFT (7U) +/*! TX256T511OCTGBPIM - MMC Transmit 256 to 511 Octet Good Bad Packet Counter Interrupt Mask Setting + * this bit masks the interrupt when the tx256to511octets_gb counter reaches half of the maximum + * value or the maximum value. + * 0b0..MMC Transmit 256 to 511 Octet Good Bad Packet Counter Interrupt Mask is disabled + * 0b1..MMC Transmit 256 to 511 Octet Good Bad Packet Counter Interrupt Mask is enabled + */ +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TX256T511OCTGBPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TX256T511OCTGBPIM_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TX256T511OCTGBPIM_MASK) + +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TX512T1023OCTGBPIM_MASK (0x100U) +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TX512T1023OCTGBPIM_SHIFT (8U) +/*! TX512T1023OCTGBPIM - MMC Transmit 512 to 1023 Octet Good Bad Packet Counter Interrupt Mask + * Setting this bit masks the interrupt when the tx512to1023octets_gb counter reaches half of the + * maximum value or the maximum value. + * 0b0..MMC Transmit 512 to 1023 Octet Good Bad Packet Counter Interrupt Mask is disabled + * 0b1..MMC Transmit 512 to 1023 Octet Good Bad Packet Counter Interrupt Mask is enabled + */ +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TX512T1023OCTGBPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TX512T1023OCTGBPIM_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TX512T1023OCTGBPIM_MASK) + +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TX1024TMAXOCTGBPIM_MASK (0x200U) +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TX1024TMAXOCTGBPIM_SHIFT (9U) +/*! TX1024TMAXOCTGBPIM - MMC Transmit 1024 to Maximum Octet Good Bad Packet Counter Interrupt Mask + * Setting this bit masks the interrupt when the tx1024tomaxoctets_gb counter reaches half of the + * maximum value or the maximum value. + * 0b0..MMC Transmit 1024 to Maximum Octet Good Bad Packet Counter Interrupt Mask is disabled + * 0b1..MMC Transmit 1024 to Maximum Octet Good Bad Packet Counter Interrupt Mask is enabled + */ +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TX1024TMAXOCTGBPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TX1024TMAXOCTGBPIM_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TX1024TMAXOCTGBPIM_MASK) + +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXUCGBPIM_MASK (0x400U) +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXUCGBPIM_SHIFT (10U) +/*! TXUCGBPIM - MMC Transmit Unicast Good Bad Packet Counter Interrupt Mask Setting this bit masks + * the interrupt when the txunicastpackets_gb counter reaches half of the maximum value or the + * maximum value. + * 0b0..MMC Transmit Unicast Good Bad Packet Counter Interrupt Mask is disabled + * 0b1..MMC Transmit Unicast Good Bad Packet Counter Interrupt Mask is enabled + */ +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXUCGBPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXUCGBPIM_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXUCGBPIM_MASK) + +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXMCGBPIM_MASK (0x800U) +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXMCGBPIM_SHIFT (11U) +/*! TXMCGBPIM - MMC Transmit Multicast Good Bad Packet Counter Interrupt Mask Setting this bit masks + * the interrupt when the txmulticastpackets_gb counter reaches half of the maximum value or the + * maximum value. + * 0b0..MMC Transmit Multicast Good Bad Packet Counter Interrupt Mask is disabled + * 0b1..MMC Transmit Multicast Good Bad Packet Counter Interrupt Mask is enabled + */ +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXMCGBPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXMCGBPIM_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXMCGBPIM_MASK) + +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXBCGBPIM_MASK (0x1000U) +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXBCGBPIM_SHIFT (12U) +/*! TXBCGBPIM - MMC Transmit Broadcast Good Bad Packet Counter Interrupt Mask Setting this bit masks + * the interrupt when the txbroadcastpackets_gb counter reaches half of the maximum value or the + * maximum value. + * 0b0..MMC Transmit Broadcast Good Bad Packet Counter Interrupt Mask is disabled + * 0b1..MMC Transmit Broadcast Good Bad Packet Counter Interrupt Mask is enabled + */ +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXBCGBPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXBCGBPIM_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXBCGBPIM_MASK) + +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXUFLOWERPIM_MASK (0x2000U) +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXUFLOWERPIM_SHIFT (13U) +/*! TXUFLOWERPIM - MMC Transmit Underflow Error Packet Counter Interrupt Mask Setting this bit masks + * the interrupt when the txunderflowerror counter reaches half of the maximum value or the + * maximum value. + * 0b0..MMC Transmit Underflow Error Packet Counter Interrupt Mask is disabled + * 0b1..MMC Transmit Underflow Error Packet Counter Interrupt Mask is enabled + */ +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXUFLOWERPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXUFLOWERPIM_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXUFLOWERPIM_MASK) + +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXSCOLGPIM_MASK (0x4000U) +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXSCOLGPIM_SHIFT (14U) +/*! TXSCOLGPIM - MMC Transmit Single Collision Good Packet Counter Interrupt Mask Setting this bit + * masks the interrupt when the txsinglecol_g counter reaches half of the maximum value or the + * maximum value. + * 0b0..MMC Transmit Single Collision Good Packet Counter Interrupt Mask is disabled + * 0b1..MMC Transmit Single Collision Good Packet Counter Interrupt Mask is enabled + */ +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXSCOLGPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXSCOLGPIM_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXSCOLGPIM_MASK) + +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXMCOLGPIM_MASK (0x8000U) +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXMCOLGPIM_SHIFT (15U) +/*! TXMCOLGPIM - MMC Transmit Multiple Collision Good Packet Counter Interrupt Mask Setting this bit + * masks the interrupt when the txmulticol_g counter reaches half of the maximum value or the + * maximum value. + * 0b0..MMC Transmit Multiple Collision Good Packet Counter Interrupt Mask is disabled + * 0b1..MMC Transmit Multiple Collision Good Packet Counter Interrupt Mask is enabled + */ +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXMCOLGPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXMCOLGPIM_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXMCOLGPIM_MASK) + +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXDEFPIM_MASK (0x10000U) +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXDEFPIM_SHIFT (16U) +/*! TXDEFPIM - MMC Transmit Deferred Packet Counter Interrupt Mask Setting this bit masks the + * interrupt when the txdeferred counter reaches half of the maximum value or the maximum value. + * 0b0..MMC Transmit Deferred Packet Counter Interrupt Mask is disabled + * 0b1..MMC Transmit Deferred Packet Counter Interrupt Mask is enabled + */ +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXDEFPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXDEFPIM_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXDEFPIM_MASK) + +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXLATCOLPIM_MASK (0x20000U) +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXLATCOLPIM_SHIFT (17U) +/*! TXLATCOLPIM - MMC Transmit Late Collision Packet Counter Interrupt Mask Setting this bit masks + * the interrupt when the txlatecol counter reaches half of the maximum value or the maximum value. + * 0b0..MMC Transmit Late Collision Packet Counter Interrupt Mask is disabled + * 0b1..MMC Transmit Late Collision Packet Counter Interrupt Mask is enabled + */ +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXLATCOLPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXLATCOLPIM_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXLATCOLPIM_MASK) + +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXEXCOLPIM_MASK (0x40000U) +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXEXCOLPIM_SHIFT (18U) +/*! TXEXCOLPIM - MMC Transmit Excessive Collision Packet Counter Interrupt Mask Setting this bit + * masks the interrupt when the txexcesscol counter reaches half of the maximum value or the maximum + * value. + * 0b0..MMC Transmit Excessive Collision Packet Counter Interrupt Mask is disabled + * 0b1..MMC Transmit Excessive Collision Packet Counter Interrupt Mask is enabled + */ +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXEXCOLPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXEXCOLPIM_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXEXCOLPIM_MASK) + +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXCARERPIM_MASK (0x80000U) +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXCARERPIM_SHIFT (19U) +/*! TXCARERPIM - MMC Transmit Carrier Error Packet Counter Interrupt Mask Setting this bit masks the + * interrupt when the txcarriererror counter reaches half of the maximum value or the maximum + * value. + * 0b0..MMC Transmit Carrier Error Packet Counter Interrupt Mask is disabled + * 0b1..MMC Transmit Carrier Error Packet Counter Interrupt Mask is enabled + */ +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXCARERPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXCARERPIM_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXCARERPIM_MASK) + +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXGOCTIM_MASK (0x100000U) +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXGOCTIM_SHIFT (20U) +/*! TXGOCTIM - MMC Transmit Good Octet Counter Interrupt Mask Setting this bit masks the interrupt + * when the txoctetcount_g counter reaches half of the maximum value or the maximum value. + * 0b0..MMC Transmit Good Octet Counter Interrupt Mask is disabled + * 0b1..MMC Transmit Good Octet Counter Interrupt Mask is enabled + */ +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXGOCTIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXGOCTIM_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXGOCTIM_MASK) + +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXGPKTIM_MASK (0x200000U) +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXGPKTIM_SHIFT (21U) +/*! TXGPKTIM - MMC Transmit Good Packet Counter Interrupt Mask Setting this bit masks the interrupt + * when the txpacketcount_g counter reaches half of the maximum value or the maximum value. + * 0b0..MMC Transmit Good Packet Counter Interrupt Mask is disabled + * 0b1..MMC Transmit Good Packet Counter Interrupt Mask is enabled + */ +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXGPKTIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXGPKTIM_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXGPKTIM_MASK) + +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXEXDEFPIM_MASK (0x400000U) +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXEXDEFPIM_SHIFT (22U) +/*! TXEXDEFPIM - MMC Transmit Excessive Deferral Packet Counter Interrupt Mask Setting this bit + * masks the interrupt when the txexcessdef counter reaches half of the maximum value or the maximum + * value. + * 0b0..MMC Transmit Excessive Deferral Packet Counter Interrupt Mask is disabled + * 0b1..MMC Transmit Excessive Deferral Packet Counter Interrupt Mask is enabled + */ +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXEXDEFPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXEXDEFPIM_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXEXDEFPIM_MASK) + +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXPAUSPIM_MASK (0x800000U) +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXPAUSPIM_SHIFT (23U) +/*! TXPAUSPIM - MMC Transmit Pause Packet Counter Interrupt Mask Setting this bit masks the + * interrupt when the txpausepackets counter reaches half of the maximum value or the maximum value. + * 0b0..MMC Transmit Pause Packet Counter Interrupt Mask is disabled + * 0b1..MMC Transmit Pause Packet Counter Interrupt Mask is enabled + */ +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXPAUSPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXPAUSPIM_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXPAUSPIM_MASK) + +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXVLANGPIM_MASK (0x1000000U) +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXVLANGPIM_SHIFT (24U) +/*! TXVLANGPIM - MMC Transmit VLAN Good Packet Counter Interrupt Mask Setting this bit masks the + * interrupt when the txvlanpackets_g counter reaches half of the maximum value or the maximum value. + * 0b0..MMC Transmit VLAN Good Packet Counter Interrupt Mask is disabled + * 0b1..MMC Transmit VLAN Good Packet Counter Interrupt Mask is enabled + */ +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXVLANGPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXVLANGPIM_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXVLANGPIM_MASK) + +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXOSIZEGPIM_MASK (0x2000000U) +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXOSIZEGPIM_SHIFT (25U) +/*! TXOSIZEGPIM - MMC Transmit Oversize Good Packet Counter Interrupt Mask Setting this bit masks + * the interrupt when the txoversize_g counter reaches half of the maximum value or the maximum + * value. + * 0b0..MMC Transmit Oversize Good Packet Counter Interrupt Mask is disabled + * 0b1..MMC Transmit Oversize Good Packet Counter Interrupt Mask is enabled + */ +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXOSIZEGPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXOSIZEGPIM_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXOSIZEGPIM_MASK) + +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXLPIUSCIM_MASK (0x4000000U) +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXLPIUSCIM_SHIFT (26U) +/*! TXLPIUSCIM - MMC Transmit LPI microsecond counter interrupt Mask Setting this bit masks the + * interrupt when the Tx_LPI_USEC_Cntr counter reaches half of the maximum value or the maximum value. + * 0b0..MMC Transmit LPI microsecond counter interrupt Mask is disabled + * 0b1..MMC Transmit LPI microsecond counter interrupt Mask is enabled + */ +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXLPIUSCIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXLPIUSCIM_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXLPIUSCIM_MASK) + +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXLPITRCIM_MASK (0x8000000U) +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXLPITRCIM_SHIFT (27U) +/*! TXLPITRCIM - MMC Transmit LPI transition counter interrupt Mask Setting this bit masks the + * interrupt when the Tx_LPI_Tran_Cntr counter reaches half of the maximum value or the maximum value. + * 0b0..MMC Transmit LPI transition counter interrupt Mask is disabled + * 0b1..MMC Transmit LPI transition counter interrupt Mask is enabled + */ +#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXLPITRCIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXLPITRCIM_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXLPITRCIM_MASK) +/*! @} */ + +/*! @name MAC_TX_OCTET_COUNT_GOOD_BAD - Tx Octet Count Good and Bad */ +/*! @{ */ + +#define ENET_QOS_MAC_TX_OCTET_COUNT_GOOD_BAD_TXOCTGB_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_TX_OCTET_COUNT_GOOD_BAD_TXOCTGB_SHIFT (0U) +/*! TXOCTGB - Tx Octet Count Good Bad This field indicates the number of bytes transmitted, + * exclusive of preamble and retried bytes, in good and bad packets. + */ +#define ENET_QOS_MAC_TX_OCTET_COUNT_GOOD_BAD_TXOCTGB(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_OCTET_COUNT_GOOD_BAD_TXOCTGB_SHIFT)) & ENET_QOS_MAC_TX_OCTET_COUNT_GOOD_BAD_TXOCTGB_MASK) +/*! @} */ + +/*! @name MAC_TX_PACKET_COUNT_GOOD_BAD - Tx Packet Count Good and Bad */ +/*! @{ */ + +#define ENET_QOS_MAC_TX_PACKET_COUNT_GOOD_BAD_TXPKTGB_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_TX_PACKET_COUNT_GOOD_BAD_TXPKTGB_SHIFT (0U) +/*! TXPKTGB - Tx Packet Count Good Bad This field indicates the number of good and bad packets + * transmitted, exclusive of retried packets. + */ +#define ENET_QOS_MAC_TX_PACKET_COUNT_GOOD_BAD_TXPKTGB(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_PACKET_COUNT_GOOD_BAD_TXPKTGB_SHIFT)) & ENET_QOS_MAC_TX_PACKET_COUNT_GOOD_BAD_TXPKTGB_MASK) +/*! @} */ + +/*! @name MAC_TX_BROADCAST_PACKETS_GOOD - Tx Broadcast Packets Good */ +/*! @{ */ + +#define ENET_QOS_MAC_TX_BROADCAST_PACKETS_GOOD_TXBCASTG_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_TX_BROADCAST_PACKETS_GOOD_TXBCASTG_SHIFT (0U) +/*! TXBCASTG - Tx Broadcast Packets Good This field indicates the number of good broadcast packets transmitted. */ +#define ENET_QOS_MAC_TX_BROADCAST_PACKETS_GOOD_TXBCASTG(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_BROADCAST_PACKETS_GOOD_TXBCASTG_SHIFT)) & ENET_QOS_MAC_TX_BROADCAST_PACKETS_GOOD_TXBCASTG_MASK) +/*! @} */ + +/*! @name MAC_TX_MULTICAST_PACKETS_GOOD - Tx Multicast Packets Good */ +/*! @{ */ + +#define ENET_QOS_MAC_TX_MULTICAST_PACKETS_GOOD_TXMCASTG_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_TX_MULTICAST_PACKETS_GOOD_TXMCASTG_SHIFT (0U) +/*! TXMCASTG - Tx Multicast Packets Good This field indicates the number of good multicast packets transmitted. */ +#define ENET_QOS_MAC_TX_MULTICAST_PACKETS_GOOD_TXMCASTG(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_MULTICAST_PACKETS_GOOD_TXMCASTG_SHIFT)) & ENET_QOS_MAC_TX_MULTICAST_PACKETS_GOOD_TXMCASTG_MASK) +/*! @} */ + +/*! @name MAC_TX_64OCTETS_PACKETS_GOOD_BAD - Tx Good and Bad 64-Byte Packets */ +/*! @{ */ + +#define ENET_QOS_MAC_TX_64OCTETS_PACKETS_GOOD_BAD_TX64OCTGB_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_TX_64OCTETS_PACKETS_GOOD_BAD_TX64OCTGB_SHIFT (0U) +/*! TX64OCTGB - Tx 64Octets Packets Good_Bad This field indicates the number of good and bad packets + * transmitted with length 64 bytes, exclusive of preamble and retried packets. + */ +#define ENET_QOS_MAC_TX_64OCTETS_PACKETS_GOOD_BAD_TX64OCTGB(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_64OCTETS_PACKETS_GOOD_BAD_TX64OCTGB_SHIFT)) & ENET_QOS_MAC_TX_64OCTETS_PACKETS_GOOD_BAD_TX64OCTGB_MASK) +/*! @} */ + +/*! @name MAC_TX_65TO127OCTETS_PACKETS_GOOD_BAD - Tx Good and Bad 65 to 127-Byte Packets */ +/*! @{ */ + +#define ENET_QOS_MAC_TX_65TO127OCTETS_PACKETS_GOOD_BAD_TX65_127OCTGB_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_TX_65TO127OCTETS_PACKETS_GOOD_BAD_TX65_127OCTGB_SHIFT (0U) +/*! TX65_127OCTGB - Tx 65To127Octets Packets Good Bad This field indicates the number of good and + * bad packets transmitted with length between 65 and 127 (inclusive) bytes, exclusive of preamble + * and retried packets. + */ +#define ENET_QOS_MAC_TX_65TO127OCTETS_PACKETS_GOOD_BAD_TX65_127OCTGB(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_65TO127OCTETS_PACKETS_GOOD_BAD_TX65_127OCTGB_SHIFT)) & ENET_QOS_MAC_TX_65TO127OCTETS_PACKETS_GOOD_BAD_TX65_127OCTGB_MASK) +/*! @} */ + +/*! @name MAC_TX_128TO255OCTETS_PACKETS_GOOD_BAD - Tx Good and Bad 128 to 255-Byte Packets */ +/*! @{ */ + +#define ENET_QOS_MAC_TX_128TO255OCTETS_PACKETS_GOOD_BAD_TX128_255OCTGB_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_TX_128TO255OCTETS_PACKETS_GOOD_BAD_TX128_255OCTGB_SHIFT (0U) +/*! TX128_255OCTGB - Tx 128To255Octets Packets Good Bad This field indicates the number of good and + * bad packets transmitted with length between 128 and 255 (inclusive) bytes, exclusive of + * preamble and retried packets. + */ +#define ENET_QOS_MAC_TX_128TO255OCTETS_PACKETS_GOOD_BAD_TX128_255OCTGB(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_128TO255OCTETS_PACKETS_GOOD_BAD_TX128_255OCTGB_SHIFT)) & ENET_QOS_MAC_TX_128TO255OCTETS_PACKETS_GOOD_BAD_TX128_255OCTGB_MASK) +/*! @} */ + +/*! @name MAC_TX_256TO511OCTETS_PACKETS_GOOD_BAD - Tx Good and Bad 256 to 511-Byte Packets */ +/*! @{ */ + +#define ENET_QOS_MAC_TX_256TO511OCTETS_PACKETS_GOOD_BAD_TX256_511OCTGB_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_TX_256TO511OCTETS_PACKETS_GOOD_BAD_TX256_511OCTGB_SHIFT (0U) +/*! TX256_511OCTGB - Tx 256To511Octets Packets Good Bad This field indicates the number of good and + * bad packets transmitted with length between 256 and 511 (inclusive) bytes, exclusive of + * preamble and retried packets. + */ +#define ENET_QOS_MAC_TX_256TO511OCTETS_PACKETS_GOOD_BAD_TX256_511OCTGB(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_256TO511OCTETS_PACKETS_GOOD_BAD_TX256_511OCTGB_SHIFT)) & ENET_QOS_MAC_TX_256TO511OCTETS_PACKETS_GOOD_BAD_TX256_511OCTGB_MASK) +/*! @} */ + +/*! @name MAC_TX_512TO1023OCTETS_PACKETS_GOOD_BAD - Tx Good and Bad 512 to 1023-Byte Packets */ +/*! @{ */ + +#define ENET_QOS_MAC_TX_512TO1023OCTETS_PACKETS_GOOD_BAD_TX512_1023OCTGB_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_TX_512TO1023OCTETS_PACKETS_GOOD_BAD_TX512_1023OCTGB_SHIFT (0U) +/*! TX512_1023OCTGB - Tx 512To1023Octets Packets Good Bad This field indicates the number of good + * and bad packets transmitted with length between 512 and 1023 (inclusive) bytes, exclusive of + * preamble and retried packets. + */ +#define ENET_QOS_MAC_TX_512TO1023OCTETS_PACKETS_GOOD_BAD_TX512_1023OCTGB(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_512TO1023OCTETS_PACKETS_GOOD_BAD_TX512_1023OCTGB_SHIFT)) & ENET_QOS_MAC_TX_512TO1023OCTETS_PACKETS_GOOD_BAD_TX512_1023OCTGB_MASK) +/*! @} */ + +/*! @name MAC_TX_1024TOMAXOCTETS_PACKETS_GOOD_BAD - Tx Good and Bad 1024 to Max-Byte Packets */ +/*! @{ */ + +#define ENET_QOS_MAC_TX_1024TOMAXOCTETS_PACKETS_GOOD_BAD_TX1024_MAXOCTGB_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_TX_1024TOMAXOCTETS_PACKETS_GOOD_BAD_TX1024_MAXOCTGB_SHIFT (0U) +/*! TX1024_MAXOCTGB - Tx 1024ToMaxOctets Packets Good Bad This field indicates the number of good + * and bad packets transmitted with length between 1024 and maxsize (inclusive) bytes, exclusive of + * preamble and retried packets. + */ +#define ENET_QOS_MAC_TX_1024TOMAXOCTETS_PACKETS_GOOD_BAD_TX1024_MAXOCTGB(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_1024TOMAXOCTETS_PACKETS_GOOD_BAD_TX1024_MAXOCTGB_SHIFT)) & ENET_QOS_MAC_TX_1024TOMAXOCTETS_PACKETS_GOOD_BAD_TX1024_MAXOCTGB_MASK) +/*! @} */ + +/*! @name MAC_TX_UNICAST_PACKETS_GOOD_BAD - Good and Bad Unicast Packets Transmitted */ +/*! @{ */ + +#define ENET_QOS_MAC_TX_UNICAST_PACKETS_GOOD_BAD_TXUCASTGB_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_TX_UNICAST_PACKETS_GOOD_BAD_TXUCASTGB_SHIFT (0U) +/*! TXUCASTGB - Tx Unicast Packets Good Bad This field indicates the number of good and bad unicast packets transmitted. */ +#define ENET_QOS_MAC_TX_UNICAST_PACKETS_GOOD_BAD_TXUCASTGB(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_UNICAST_PACKETS_GOOD_BAD_TXUCASTGB_SHIFT)) & ENET_QOS_MAC_TX_UNICAST_PACKETS_GOOD_BAD_TXUCASTGB_MASK) +/*! @} */ + +/*! @name MAC_TX_MULTICAST_PACKETS_GOOD_BAD - Good and Bad Multicast Packets Transmitted */ +/*! @{ */ + +#define ENET_QOS_MAC_TX_MULTICAST_PACKETS_GOOD_BAD_TXMCASTGB_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_TX_MULTICAST_PACKETS_GOOD_BAD_TXMCASTGB_SHIFT (0U) +/*! TXMCASTGB - Tx Multicast Packets Good Bad This field indicates the number of good and bad multicast packets transmitted. */ +#define ENET_QOS_MAC_TX_MULTICAST_PACKETS_GOOD_BAD_TXMCASTGB(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_MULTICAST_PACKETS_GOOD_BAD_TXMCASTGB_SHIFT)) & ENET_QOS_MAC_TX_MULTICAST_PACKETS_GOOD_BAD_TXMCASTGB_MASK) +/*! @} */ + +/*! @name MAC_TX_BROADCAST_PACKETS_GOOD_BAD - Good and Bad Broadcast Packets Transmitted */ +/*! @{ */ + +#define ENET_QOS_MAC_TX_BROADCAST_PACKETS_GOOD_BAD_TXBCASTGB_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_TX_BROADCAST_PACKETS_GOOD_BAD_TXBCASTGB_SHIFT (0U) +/*! TXBCASTGB - Tx Broadcast Packets Good Bad This field indicates the number of good and bad broadcast packets transmitted. */ +#define ENET_QOS_MAC_TX_BROADCAST_PACKETS_GOOD_BAD_TXBCASTGB(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_BROADCAST_PACKETS_GOOD_BAD_TXBCASTGB_SHIFT)) & ENET_QOS_MAC_TX_BROADCAST_PACKETS_GOOD_BAD_TXBCASTGB_MASK) +/*! @} */ + +/*! @name MAC_TX_UNDERFLOW_ERROR_PACKETS - Tx Packets Aborted By Underflow Error */ +/*! @{ */ + +#define ENET_QOS_MAC_TX_UNDERFLOW_ERROR_PACKETS_TXUNDRFLW_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_TX_UNDERFLOW_ERROR_PACKETS_TXUNDRFLW_SHIFT (0U) +/*! TXUNDRFLW - Tx Underflow Error Packets This field indicates the number of packets aborted because of packets underflow error. */ +#define ENET_QOS_MAC_TX_UNDERFLOW_ERROR_PACKETS_TXUNDRFLW(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_UNDERFLOW_ERROR_PACKETS_TXUNDRFLW_SHIFT)) & ENET_QOS_MAC_TX_UNDERFLOW_ERROR_PACKETS_TXUNDRFLW_MASK) +/*! @} */ + +/*! @name MAC_TX_SINGLE_COLLISION_GOOD_PACKETS - Single Collision Good Packets Transmitted */ +/*! @{ */ + +#define ENET_QOS_MAC_TX_SINGLE_COLLISION_GOOD_PACKETS_TXSNGLCOLG_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_TX_SINGLE_COLLISION_GOOD_PACKETS_TXSNGLCOLG_SHIFT (0U) +/*! TXSNGLCOLG - Tx Single Collision Good Packets This field indicates the number of successfully + * transmitted packets after a single collision in the half-duplex mode. + */ +#define ENET_QOS_MAC_TX_SINGLE_COLLISION_GOOD_PACKETS_TXSNGLCOLG(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_SINGLE_COLLISION_GOOD_PACKETS_TXSNGLCOLG_SHIFT)) & ENET_QOS_MAC_TX_SINGLE_COLLISION_GOOD_PACKETS_TXSNGLCOLG_MASK) +/*! @} */ + +/*! @name MAC_TX_MULTIPLE_COLLISION_GOOD_PACKETS - Multiple Collision Good Packets Transmitted */ +/*! @{ */ + +#define ENET_QOS_MAC_TX_MULTIPLE_COLLISION_GOOD_PACKETS_TXMULTCOLG_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_TX_MULTIPLE_COLLISION_GOOD_PACKETS_TXMULTCOLG_SHIFT (0U) +/*! TXMULTCOLG - Tx Multiple Collision Good Packets This field indicates the number of successfully + * transmitted packets after multiple collisions in the half-duplex mode. + */ +#define ENET_QOS_MAC_TX_MULTIPLE_COLLISION_GOOD_PACKETS_TXMULTCOLG(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_MULTIPLE_COLLISION_GOOD_PACKETS_TXMULTCOLG_SHIFT)) & ENET_QOS_MAC_TX_MULTIPLE_COLLISION_GOOD_PACKETS_TXMULTCOLG_MASK) +/*! @} */ + +/*! @name MAC_TX_DEFERRED_PACKETS - Deferred Packets Transmitted */ +/*! @{ */ + +#define ENET_QOS_MAC_TX_DEFERRED_PACKETS_TXDEFRD_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_TX_DEFERRED_PACKETS_TXDEFRD_SHIFT (0U) +/*! TXDEFRD - Tx Deferred Packets This field indicates the number of successfully transmitted after + * a deferral in the half-duplex mode. + */ +#define ENET_QOS_MAC_TX_DEFERRED_PACKETS_TXDEFRD(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_DEFERRED_PACKETS_TXDEFRD_SHIFT)) & ENET_QOS_MAC_TX_DEFERRED_PACKETS_TXDEFRD_MASK) +/*! @} */ + +/*! @name MAC_TX_LATE_COLLISION_PACKETS - Late Collision Packets Transmitted */ +/*! @{ */ + +#define ENET_QOS_MAC_TX_LATE_COLLISION_PACKETS_TXLATECOL_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_TX_LATE_COLLISION_PACKETS_TXLATECOL_SHIFT (0U) +/*! TXLATECOL - Tx Late Collision Packets This field indicates the number of packets aborted because of late collision error. */ +#define ENET_QOS_MAC_TX_LATE_COLLISION_PACKETS_TXLATECOL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_LATE_COLLISION_PACKETS_TXLATECOL_SHIFT)) & ENET_QOS_MAC_TX_LATE_COLLISION_PACKETS_TXLATECOL_MASK) +/*! @} */ + +/*! @name MAC_TX_EXCESSIVE_COLLISION_PACKETS - Excessive Collision Packets Transmitted */ +/*! @{ */ + +#define ENET_QOS_MAC_TX_EXCESSIVE_COLLISION_PACKETS_TXEXSCOL_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_TX_EXCESSIVE_COLLISION_PACKETS_TXEXSCOL_SHIFT (0U) +/*! TXEXSCOL - Tx Excessive Collision Packets This field indicates the number of packets aborted + * because of excessive (16) collision errors. + */ +#define ENET_QOS_MAC_TX_EXCESSIVE_COLLISION_PACKETS_TXEXSCOL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_EXCESSIVE_COLLISION_PACKETS_TXEXSCOL_SHIFT)) & ENET_QOS_MAC_TX_EXCESSIVE_COLLISION_PACKETS_TXEXSCOL_MASK) +/*! @} */ + +/*! @name MAC_TX_CARRIER_ERROR_PACKETS - Carrier Error Packets Transmitted */ +/*! @{ */ + +#define ENET_QOS_MAC_TX_CARRIER_ERROR_PACKETS_TXCARR_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_TX_CARRIER_ERROR_PACKETS_TXCARR_SHIFT (0U) +/*! TXCARR - Tx Carrier Error Packets This field indicates the number of packets aborted because of + * carrier sense error (no carrier or loss of carrier). + */ +#define ENET_QOS_MAC_TX_CARRIER_ERROR_PACKETS_TXCARR(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_CARRIER_ERROR_PACKETS_TXCARR_SHIFT)) & ENET_QOS_MAC_TX_CARRIER_ERROR_PACKETS_TXCARR_MASK) +/*! @} */ + +/*! @name MAC_TX_OCTET_COUNT_GOOD - Bytes Transmitted in Good Packets */ +/*! @{ */ + +#define ENET_QOS_MAC_TX_OCTET_COUNT_GOOD_TXOCTG_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_TX_OCTET_COUNT_GOOD_TXOCTG_SHIFT (0U) +/*! TXOCTG - Tx Octet Count Good This field indicates the number of bytes transmitted, exclusive of preamble, only in good packets. */ +#define ENET_QOS_MAC_TX_OCTET_COUNT_GOOD_TXOCTG(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_OCTET_COUNT_GOOD_TXOCTG_SHIFT)) & ENET_QOS_MAC_TX_OCTET_COUNT_GOOD_TXOCTG_MASK) +/*! @} */ + +/*! @name MAC_TX_PACKET_COUNT_GOOD - Good Packets Transmitted */ +/*! @{ */ + +#define ENET_QOS_MAC_TX_PACKET_COUNT_GOOD_TXPKTG_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_TX_PACKET_COUNT_GOOD_TXPKTG_SHIFT (0U) +/*! TXPKTG - Tx Packet Count Good This field indicates the number of good packets transmitted. */ +#define ENET_QOS_MAC_TX_PACKET_COUNT_GOOD_TXPKTG(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_PACKET_COUNT_GOOD_TXPKTG_SHIFT)) & ENET_QOS_MAC_TX_PACKET_COUNT_GOOD_TXPKTG_MASK) +/*! @} */ + +/*! @name MAC_TX_EXCESSIVE_DEFERRAL_ERROR - Packets Aborted By Excessive Deferral Error */ +/*! @{ */ + +#define ENET_QOS_MAC_TX_EXCESSIVE_DEFERRAL_ERROR_TXEXSDEF_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_TX_EXCESSIVE_DEFERRAL_ERROR_TXEXSDEF_SHIFT (0U) +/*! TXEXSDEF - Tx Excessive Deferral Error This field indicates the number of packets aborted + * because of excessive deferral error (deferred for more than two max-sized packet times). + */ +#define ENET_QOS_MAC_TX_EXCESSIVE_DEFERRAL_ERROR_TXEXSDEF(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_EXCESSIVE_DEFERRAL_ERROR_TXEXSDEF_SHIFT)) & ENET_QOS_MAC_TX_EXCESSIVE_DEFERRAL_ERROR_TXEXSDEF_MASK) +/*! @} */ + +/*! @name MAC_TX_PAUSE_PACKETS - Pause Packets Transmitted */ +/*! @{ */ + +#define ENET_QOS_MAC_TX_PAUSE_PACKETS_TXPAUSE_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_TX_PAUSE_PACKETS_TXPAUSE_SHIFT (0U) +/*! TXPAUSE - Tx Pause Packets This field indicates the number of good Pause packets transmitted. */ +#define ENET_QOS_MAC_TX_PAUSE_PACKETS_TXPAUSE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_PAUSE_PACKETS_TXPAUSE_SHIFT)) & ENET_QOS_MAC_TX_PAUSE_PACKETS_TXPAUSE_MASK) +/*! @} */ + +/*! @name MAC_TX_VLAN_PACKETS_GOOD - Good VLAN Packets Transmitted */ +/*! @{ */ + +#define ENET_QOS_MAC_TX_VLAN_PACKETS_GOOD_TXVLANG_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_TX_VLAN_PACKETS_GOOD_TXVLANG_SHIFT (0U) +/*! TXVLANG - Tx VLAN Packets Good This field provides the number of good VLAN packets transmitted. */ +#define ENET_QOS_MAC_TX_VLAN_PACKETS_GOOD_TXVLANG(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_VLAN_PACKETS_GOOD_TXVLANG_SHIFT)) & ENET_QOS_MAC_TX_VLAN_PACKETS_GOOD_TXVLANG_MASK) +/*! @} */ + +/*! @name MAC_TX_OSIZE_PACKETS_GOOD - Good Oversize Packets Transmitted */ +/*! @{ */ + +#define ENET_QOS_MAC_TX_OSIZE_PACKETS_GOOD_TXOSIZG_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_TX_OSIZE_PACKETS_GOOD_TXOSIZG_SHIFT (0U) +/*! TXOSIZG - Tx OSize Packets Good This field indicates the number of packets transmitted without + * errors and with length greater than the maxsize (1,518 or 1,522 bytes for VLAN tagged packets; + * 2000 bytes if enabled in S2KP bit of the CONFIGURATION register). + */ +#define ENET_QOS_MAC_TX_OSIZE_PACKETS_GOOD_TXOSIZG(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_OSIZE_PACKETS_GOOD_TXOSIZG_SHIFT)) & ENET_QOS_MAC_TX_OSIZE_PACKETS_GOOD_TXOSIZG_MASK) +/*! @} */ + +/*! @name MAC_RX_PACKETS_COUNT_GOOD_BAD - Good and Bad Packets Received */ +/*! @{ */ + +#define ENET_QOS_MAC_RX_PACKETS_COUNT_GOOD_BAD_RXPKTGB_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_RX_PACKETS_COUNT_GOOD_BAD_RXPKTGB_SHIFT (0U) +/*! RXPKTGB - Rx Packets Count Good Bad This field indicates the number of good and bad packets received. */ +#define ENET_QOS_MAC_RX_PACKETS_COUNT_GOOD_BAD_RXPKTGB(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_PACKETS_COUNT_GOOD_BAD_RXPKTGB_SHIFT)) & ENET_QOS_MAC_RX_PACKETS_COUNT_GOOD_BAD_RXPKTGB_MASK) +/*! @} */ + +/*! @name MAC_RX_OCTET_COUNT_GOOD_BAD - Bytes in Good and Bad Packets Received */ +/*! @{ */ + +#define ENET_QOS_MAC_RX_OCTET_COUNT_GOOD_BAD_RXOCTGB_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_RX_OCTET_COUNT_GOOD_BAD_RXOCTGB_SHIFT (0U) +/*! RXOCTGB - Rx Octet Count Good Bad This field indicates the number of bytes received, exclusive + * of preamble, in good and bad packets. + */ +#define ENET_QOS_MAC_RX_OCTET_COUNT_GOOD_BAD_RXOCTGB(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_OCTET_COUNT_GOOD_BAD_RXOCTGB_SHIFT)) & ENET_QOS_MAC_RX_OCTET_COUNT_GOOD_BAD_RXOCTGB_MASK) +/*! @} */ + +/*! @name MAC_RX_OCTET_COUNT_GOOD - Bytes in Good Packets Received */ +/*! @{ */ + +#define ENET_QOS_MAC_RX_OCTET_COUNT_GOOD_RXOCTG_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_RX_OCTET_COUNT_GOOD_RXOCTG_SHIFT (0U) +/*! RXOCTG - Rx Octet Count Good This field indicates the number of bytes received, exclusive of preamble, only in good packets. */ +#define ENET_QOS_MAC_RX_OCTET_COUNT_GOOD_RXOCTG(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_OCTET_COUNT_GOOD_RXOCTG_SHIFT)) & ENET_QOS_MAC_RX_OCTET_COUNT_GOOD_RXOCTG_MASK) +/*! @} */ + +/*! @name MAC_RX_BROADCAST_PACKETS_GOOD - Good Broadcast Packets Received */ +/*! @{ */ + +#define ENET_QOS_MAC_RX_BROADCAST_PACKETS_GOOD_RXBCASTG_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_RX_BROADCAST_PACKETS_GOOD_RXBCASTG_SHIFT (0U) +/*! RXBCASTG - Rx Broadcast Packets Good This field indicates the number of good broadcast packets received. */ +#define ENET_QOS_MAC_RX_BROADCAST_PACKETS_GOOD_RXBCASTG(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_BROADCAST_PACKETS_GOOD_RXBCASTG_SHIFT)) & ENET_QOS_MAC_RX_BROADCAST_PACKETS_GOOD_RXBCASTG_MASK) +/*! @} */ + +/*! @name MAC_RX_MULTICAST_PACKETS_GOOD - Good Multicast Packets Received */ +/*! @{ */ + +#define ENET_QOS_MAC_RX_MULTICAST_PACKETS_GOOD_RXMCASTG_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_RX_MULTICAST_PACKETS_GOOD_RXMCASTG_SHIFT (0U) +/*! RXMCASTG - Rx Multicast Packets Good This field indicates the number of good multicast packets received. */ +#define ENET_QOS_MAC_RX_MULTICAST_PACKETS_GOOD_RXMCASTG(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_MULTICAST_PACKETS_GOOD_RXMCASTG_SHIFT)) & ENET_QOS_MAC_RX_MULTICAST_PACKETS_GOOD_RXMCASTG_MASK) +/*! @} */ + +/*! @name MAC_RX_CRC_ERROR_PACKETS - CRC Error Packets Received */ +/*! @{ */ + +#define ENET_QOS_MAC_RX_CRC_ERROR_PACKETS_RXCRCERR_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_RX_CRC_ERROR_PACKETS_RXCRCERR_SHIFT (0U) +/*! RXCRCERR - Rx CRC Error Packets This field indicates the number of packets received with CRC error. */ +#define ENET_QOS_MAC_RX_CRC_ERROR_PACKETS_RXCRCERR(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_CRC_ERROR_PACKETS_RXCRCERR_SHIFT)) & ENET_QOS_MAC_RX_CRC_ERROR_PACKETS_RXCRCERR_MASK) +/*! @} */ + +/*! @name MAC_RX_ALIGNMENT_ERROR_PACKETS - Alignment Error Packets Received */ +/*! @{ */ + +#define ENET_QOS_MAC_RX_ALIGNMENT_ERROR_PACKETS_RXALGNERR_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_RX_ALIGNMENT_ERROR_PACKETS_RXALGNERR_SHIFT (0U) +/*! RXALGNERR - Rx Alignment Error Packets This field indicates the number of packets received with alignment (dribble) error. */ +#define ENET_QOS_MAC_RX_ALIGNMENT_ERROR_PACKETS_RXALGNERR(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_ALIGNMENT_ERROR_PACKETS_RXALGNERR_SHIFT)) & ENET_QOS_MAC_RX_ALIGNMENT_ERROR_PACKETS_RXALGNERR_MASK) +/*! @} */ + +/*! @name MAC_RX_RUNT_ERROR_PACKETS - Runt Error Packets Received */ +/*! @{ */ + +#define ENET_QOS_MAC_RX_RUNT_ERROR_PACKETS_RXRUNTERR_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_RX_RUNT_ERROR_PACKETS_RXRUNTERR_SHIFT (0U) +/*! RXRUNTERR - Rx Runt Error Packets This field indicates the number of packets received with runt + * (length less than 64 bytes and CRC error) error. + */ +#define ENET_QOS_MAC_RX_RUNT_ERROR_PACKETS_RXRUNTERR(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_RUNT_ERROR_PACKETS_RXRUNTERR_SHIFT)) & ENET_QOS_MAC_RX_RUNT_ERROR_PACKETS_RXRUNTERR_MASK) +/*! @} */ + +/*! @name MAC_RX_JABBER_ERROR_PACKETS - Jabber Error Packets Received */ +/*! @{ */ + +#define ENET_QOS_MAC_RX_JABBER_ERROR_PACKETS_RXJABERR_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_RX_JABBER_ERROR_PACKETS_RXJABERR_SHIFT (0U) +/*! RXJABERR - Rx Jabber Error Packets This field indicates the number of giant packets received + * with length (including CRC) greater than 1,518 bytes (1,522 bytes for VLAN tagged) and with CRC + * error. + */ +#define ENET_QOS_MAC_RX_JABBER_ERROR_PACKETS_RXJABERR(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_JABBER_ERROR_PACKETS_RXJABERR_SHIFT)) & ENET_QOS_MAC_RX_JABBER_ERROR_PACKETS_RXJABERR_MASK) +/*! @} */ + +/*! @name MAC_RX_UNDERSIZE_PACKETS_GOOD - Good Undersize Packets Received */ +/*! @{ */ + +#define ENET_QOS_MAC_RX_UNDERSIZE_PACKETS_GOOD_RXUNDERSZG_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_RX_UNDERSIZE_PACKETS_GOOD_RXUNDERSZG_SHIFT (0U) +/*! RXUNDERSZG - Rx Undersize Packets Good This field indicates the number of packets received with + * length less than 64 bytes, without any errors. + */ +#define ENET_QOS_MAC_RX_UNDERSIZE_PACKETS_GOOD_RXUNDERSZG(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_UNDERSIZE_PACKETS_GOOD_RXUNDERSZG_SHIFT)) & ENET_QOS_MAC_RX_UNDERSIZE_PACKETS_GOOD_RXUNDERSZG_MASK) +/*! @} */ + +/*! @name MAC_RX_OVERSIZE_PACKETS_GOOD - Good Oversize Packets Received */ +/*! @{ */ + +#define ENET_QOS_MAC_RX_OVERSIZE_PACKETS_GOOD_RXOVERSZG_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_RX_OVERSIZE_PACKETS_GOOD_RXOVERSZG_SHIFT (0U) +/*! RXOVERSZG - Rx Oversize Packets Good This field indicates the number of packets received without + * errors, with length greater than the maxsize (1,518 bytes or 1,522 bytes for VLAN tagged + * packets; 2000 bytes if enabled in the S2KP bit of the MAC_CONFIGURATION register). + */ +#define ENET_QOS_MAC_RX_OVERSIZE_PACKETS_GOOD_RXOVERSZG(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_OVERSIZE_PACKETS_GOOD_RXOVERSZG_SHIFT)) & ENET_QOS_MAC_RX_OVERSIZE_PACKETS_GOOD_RXOVERSZG_MASK) +/*! @} */ + +/*! @name MAC_RX_64OCTETS_PACKETS_GOOD_BAD - Good and Bad 64-Byte Packets Received */ +/*! @{ */ + +#define ENET_QOS_MAC_RX_64OCTETS_PACKETS_GOOD_BAD_RX64OCTGB_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_RX_64OCTETS_PACKETS_GOOD_BAD_RX64OCTGB_SHIFT (0U) +/*! RX64OCTGB - Rx 64 Octets Packets Good Bad This field indicates the number of good and bad + * packets received with length 64 bytes, exclusive of the preamble. + */ +#define ENET_QOS_MAC_RX_64OCTETS_PACKETS_GOOD_BAD_RX64OCTGB(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_64OCTETS_PACKETS_GOOD_BAD_RX64OCTGB_SHIFT)) & ENET_QOS_MAC_RX_64OCTETS_PACKETS_GOOD_BAD_RX64OCTGB_MASK) +/*! @} */ + +/*! @name MAC_RX_65TO127OCTETS_PACKETS_GOOD_BAD - Good and Bad 64-to-127 Byte Packets Received */ +/*! @{ */ + +#define ENET_QOS_MAC_RX_65TO127OCTETS_PACKETS_GOOD_BAD_RX65_127OCTGB_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_RX_65TO127OCTETS_PACKETS_GOOD_BAD_RX65_127OCTGB_SHIFT (0U) +/*! RX65_127OCTGB - Rx 65-127 Octets Packets Good Bad This field indicates the number of good and + * bad packets received with length between 65 and 127 (inclusive) bytes, exclusive of the preamble. + */ +#define ENET_QOS_MAC_RX_65TO127OCTETS_PACKETS_GOOD_BAD_RX65_127OCTGB(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_65TO127OCTETS_PACKETS_GOOD_BAD_RX65_127OCTGB_SHIFT)) & ENET_QOS_MAC_RX_65TO127OCTETS_PACKETS_GOOD_BAD_RX65_127OCTGB_MASK) +/*! @} */ + +/*! @name MAC_RX_128TO255OCTETS_PACKETS_GOOD_BAD - Good and Bad 128-to-255 Byte Packets Received */ +/*! @{ */ + +#define ENET_QOS_MAC_RX_128TO255OCTETS_PACKETS_GOOD_BAD_RX128_255OCTGB_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_RX_128TO255OCTETS_PACKETS_GOOD_BAD_RX128_255OCTGB_SHIFT (0U) +/*! RX128_255OCTGB - Rx 128-255 Octets Packets Good Bad This field indicates the number of good and + * bad packets received with length between 128 and 255 (inclusive) bytes, exclusive of the + * preamble. + */ +#define ENET_QOS_MAC_RX_128TO255OCTETS_PACKETS_GOOD_BAD_RX128_255OCTGB(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_128TO255OCTETS_PACKETS_GOOD_BAD_RX128_255OCTGB_SHIFT)) & ENET_QOS_MAC_RX_128TO255OCTETS_PACKETS_GOOD_BAD_RX128_255OCTGB_MASK) +/*! @} */ + +/*! @name MAC_RX_256TO511OCTETS_PACKETS_GOOD_BAD - Good and Bad 256-to-511 Byte Packets Received */ +/*! @{ */ + +#define ENET_QOS_MAC_RX_256TO511OCTETS_PACKETS_GOOD_BAD_RX256_511OCTGB_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_RX_256TO511OCTETS_PACKETS_GOOD_BAD_RX256_511OCTGB_SHIFT (0U) +/*! RX256_511OCTGB - Rx 256-511 Octets Packets Good Bad This field indicates the number of good and + * bad packets received with length between 256 and 511 (inclusive) bytes, exclusive of the + * preamble. + */ +#define ENET_QOS_MAC_RX_256TO511OCTETS_PACKETS_GOOD_BAD_RX256_511OCTGB(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_256TO511OCTETS_PACKETS_GOOD_BAD_RX256_511OCTGB_SHIFT)) & ENET_QOS_MAC_RX_256TO511OCTETS_PACKETS_GOOD_BAD_RX256_511OCTGB_MASK) +/*! @} */ + +/*! @name MAC_RX_512TO1023OCTETS_PACKETS_GOOD_BAD - Good and Bad 512-to-1023 Byte Packets Received */ +/*! @{ */ + +#define ENET_QOS_MAC_RX_512TO1023OCTETS_PACKETS_GOOD_BAD_RX512_1023OCTGB_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_RX_512TO1023OCTETS_PACKETS_GOOD_BAD_RX512_1023OCTGB_SHIFT (0U) +/*! RX512_1023OCTGB - RX 512-1023 Octets Packets Good Bad This field indicates the number of good + * and bad packets received with length between 512 and 1023 (inclusive) bytes, exclusive of the + * preamble. + */ +#define ENET_QOS_MAC_RX_512TO1023OCTETS_PACKETS_GOOD_BAD_RX512_1023OCTGB(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_512TO1023OCTETS_PACKETS_GOOD_BAD_RX512_1023OCTGB_SHIFT)) & ENET_QOS_MAC_RX_512TO1023OCTETS_PACKETS_GOOD_BAD_RX512_1023OCTGB_MASK) +/*! @} */ + +/*! @name MAC_RX_1024TOMAXOCTETS_PACKETS_GOOD_BAD - Good and Bad 1024-to-Max Byte Packets Received */ +/*! @{ */ + +#define ENET_QOS_MAC_RX_1024TOMAXOCTETS_PACKETS_GOOD_BAD_RX1024_MAXOCTGB_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_RX_1024TOMAXOCTETS_PACKETS_GOOD_BAD_RX1024_MAXOCTGB_SHIFT (0U) +/*! RX1024_MAXOCTGB - Rx 1024-Max Octets Good Bad This field indicates the number of good and bad + * packets received with length between 1024 and maxsize (inclusive) bytes, exclusive of the + * preamble. + */ +#define ENET_QOS_MAC_RX_1024TOMAXOCTETS_PACKETS_GOOD_BAD_RX1024_MAXOCTGB(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_1024TOMAXOCTETS_PACKETS_GOOD_BAD_RX1024_MAXOCTGB_SHIFT)) & ENET_QOS_MAC_RX_1024TOMAXOCTETS_PACKETS_GOOD_BAD_RX1024_MAXOCTGB_MASK) +/*! @} */ + +/*! @name MAC_RX_UNICAST_PACKETS_GOOD - Good Unicast Packets Received */ +/*! @{ */ + +#define ENET_QOS_MAC_RX_UNICAST_PACKETS_GOOD_RXUCASTG_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_RX_UNICAST_PACKETS_GOOD_RXUCASTG_SHIFT (0U) +/*! RXUCASTG - Rx Unicast Packets Good This field indicates the number of good unicast packets received. */ +#define ENET_QOS_MAC_RX_UNICAST_PACKETS_GOOD_RXUCASTG(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_UNICAST_PACKETS_GOOD_RXUCASTG_SHIFT)) & ENET_QOS_MAC_RX_UNICAST_PACKETS_GOOD_RXUCASTG_MASK) +/*! @} */ + +/*! @name MAC_RX_LENGTH_ERROR_PACKETS - Length Error Packets Received */ +/*! @{ */ + +#define ENET_QOS_MAC_RX_LENGTH_ERROR_PACKETS_RXLENERR_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_RX_LENGTH_ERROR_PACKETS_RXLENERR_SHIFT (0U) +/*! RXLENERR - Rx Length Error Packets This field indicates the number of packets received with + * length error (Length Type field not equal to packet size), for all packets with valid length field. + */ +#define ENET_QOS_MAC_RX_LENGTH_ERROR_PACKETS_RXLENERR(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_LENGTH_ERROR_PACKETS_RXLENERR_SHIFT)) & ENET_QOS_MAC_RX_LENGTH_ERROR_PACKETS_RXLENERR_MASK) +/*! @} */ + +/*! @name MAC_RX_OUT_OF_RANGE_TYPE_PACKETS - Out-of-range Type Packets Received */ +/*! @{ */ + +#define ENET_QOS_MAC_RX_OUT_OF_RANGE_TYPE_PACKETS_RXOUTOFRNG_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_RX_OUT_OF_RANGE_TYPE_PACKETS_RXOUTOFRNG_SHIFT (0U) +/*! RXOUTOFRNG - Rx Out of Range Type Packet This field indicates the number of packets received + * with length field not equal to the valid packet size (greater than 1,500 but less than 1,536). + */ +#define ENET_QOS_MAC_RX_OUT_OF_RANGE_TYPE_PACKETS_RXOUTOFRNG(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_OUT_OF_RANGE_TYPE_PACKETS_RXOUTOFRNG_SHIFT)) & ENET_QOS_MAC_RX_OUT_OF_RANGE_TYPE_PACKETS_RXOUTOFRNG_MASK) +/*! @} */ + +/*! @name MAC_RX_PAUSE_PACKETS - Pause Packets Received */ +/*! @{ */ + +#define ENET_QOS_MAC_RX_PAUSE_PACKETS_RXPAUSEPKT_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_RX_PAUSE_PACKETS_RXPAUSEPKT_SHIFT (0U) +/*! RXPAUSEPKT - Rx Pause Packets This field indicates the number of good and valid Pause packets received. */ +#define ENET_QOS_MAC_RX_PAUSE_PACKETS_RXPAUSEPKT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_PAUSE_PACKETS_RXPAUSEPKT_SHIFT)) & ENET_QOS_MAC_RX_PAUSE_PACKETS_RXPAUSEPKT_MASK) +/*! @} */ + +/*! @name MAC_RX_FIFO_OVERFLOW_PACKETS - Missed Packets Due to FIFO Overflow */ +/*! @{ */ + +#define ENET_QOS_MAC_RX_FIFO_OVERFLOW_PACKETS_RXFIFOOVFL_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_RX_FIFO_OVERFLOW_PACKETS_RXFIFOOVFL_SHIFT (0U) +/*! RXFIFOOVFL - Rx FIFO Overflow Packets This field indicates the number of missed received packets because of FIFO overflow. */ +#define ENET_QOS_MAC_RX_FIFO_OVERFLOW_PACKETS_RXFIFOOVFL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_FIFO_OVERFLOW_PACKETS_RXFIFOOVFL_SHIFT)) & ENET_QOS_MAC_RX_FIFO_OVERFLOW_PACKETS_RXFIFOOVFL_MASK) +/*! @} */ + +/*! @name MAC_RX_VLAN_PACKETS_GOOD_BAD - Good and Bad VLAN Packets Received */ +/*! @{ */ + +#define ENET_QOS_MAC_RX_VLAN_PACKETS_GOOD_BAD_RXVLANPKTGB_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_RX_VLAN_PACKETS_GOOD_BAD_RXVLANPKTGB_SHIFT (0U) +/*! RXVLANPKTGB - Rx VLAN Packets Good Bad This field indicates the number of good and bad VLAN packets received. */ +#define ENET_QOS_MAC_RX_VLAN_PACKETS_GOOD_BAD_RXVLANPKTGB(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_VLAN_PACKETS_GOOD_BAD_RXVLANPKTGB_SHIFT)) & ENET_QOS_MAC_RX_VLAN_PACKETS_GOOD_BAD_RXVLANPKTGB_MASK) +/*! @} */ + +/*! @name MAC_RX_WATCHDOG_ERROR_PACKETS - Watchdog Error Packets Received */ +/*! @{ */ + +#define ENET_QOS_MAC_RX_WATCHDOG_ERROR_PACKETS_RXWDGERR_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_RX_WATCHDOG_ERROR_PACKETS_RXWDGERR_SHIFT (0U) +/*! RXWDGERR - Rx Watchdog Error Packets This field indicates the number of packets received with + * error because of watchdog timeout error (packets with a data load larger than 2,048 bytes (when + * JE and WD bits are reset in MAC_CONFIGURATION register), 10,240 bytes (when JE bit is set and + * WD bit is reset in MAC_CONFIGURATION register), 16,384 bytes (when WD bit is set in + * MAC_CONFIGURATION register) or the value programmed in the MAC_WATCHDOG_TIMEOUT register). + */ +#define ENET_QOS_MAC_RX_WATCHDOG_ERROR_PACKETS_RXWDGERR(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_WATCHDOG_ERROR_PACKETS_RXWDGERR_SHIFT)) & ENET_QOS_MAC_RX_WATCHDOG_ERROR_PACKETS_RXWDGERR_MASK) +/*! @} */ + +/*! @name MAC_RX_RECEIVE_ERROR_PACKETS - Receive Error Packets Received */ +/*! @{ */ + +#define ENET_QOS_MAC_RX_RECEIVE_ERROR_PACKETS_RXRCVERR_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_RX_RECEIVE_ERROR_PACKETS_RXRCVERR_SHIFT (0U) +/*! RXRCVERR - Rx Receive Error Packets This field indicates the number of packets received with + * Receive error or Packet Extension error on the GMII interface. + */ +#define ENET_QOS_MAC_RX_RECEIVE_ERROR_PACKETS_RXRCVERR(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_RECEIVE_ERROR_PACKETS_RXRCVERR_SHIFT)) & ENET_QOS_MAC_RX_RECEIVE_ERROR_PACKETS_RXRCVERR_MASK) +/*! @} */ + +/*! @name MAC_RX_CONTROL_PACKETS_GOOD - Good Control Packets Received */ +/*! @{ */ + +#define ENET_QOS_MAC_RX_CONTROL_PACKETS_GOOD_RXCTRLG_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_RX_CONTROL_PACKETS_GOOD_RXCTRLG_SHIFT (0U) +/*! RXCTRLG - Rx Control Packets Good This field indicates the number of good control packets received. */ +#define ENET_QOS_MAC_RX_CONTROL_PACKETS_GOOD_RXCTRLG(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_CONTROL_PACKETS_GOOD_RXCTRLG_SHIFT)) & ENET_QOS_MAC_RX_CONTROL_PACKETS_GOOD_RXCTRLG_MASK) +/*! @} */ + +/*! @name MAC_TX_LPI_USEC_CNTR - Microseconds Tx LPI Asserted */ +/*! @{ */ + +#define ENET_QOS_MAC_TX_LPI_USEC_CNTR_TXLPIUSC_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_TX_LPI_USEC_CNTR_TXLPIUSC_SHIFT (0U) +/*! TXLPIUSC - Tx LPI Microseconds Counter This field indicates the number of microseconds Tx LPI is asserted. */ +#define ENET_QOS_MAC_TX_LPI_USEC_CNTR_TXLPIUSC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_LPI_USEC_CNTR_TXLPIUSC_SHIFT)) & ENET_QOS_MAC_TX_LPI_USEC_CNTR_TXLPIUSC_MASK) +/*! @} */ + +/*! @name MAC_TX_LPI_TRAN_CNTR - Number of Times Tx LPI Asserted */ +/*! @{ */ + +#define ENET_QOS_MAC_TX_LPI_TRAN_CNTR_TXLPITRC_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_TX_LPI_TRAN_CNTR_TXLPITRC_SHIFT (0U) +/*! TXLPITRC - Tx LPI Transition counter This field indicates the number of times Tx LPI Entry has occurred. */ +#define ENET_QOS_MAC_TX_LPI_TRAN_CNTR_TXLPITRC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_LPI_TRAN_CNTR_TXLPITRC_SHIFT)) & ENET_QOS_MAC_TX_LPI_TRAN_CNTR_TXLPITRC_MASK) +/*! @} */ + +/*! @name MAC_RX_LPI_USEC_CNTR - Microseconds Rx LPI Sampled */ +/*! @{ */ + +#define ENET_QOS_MAC_RX_LPI_USEC_CNTR_RXLPIUSC_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_RX_LPI_USEC_CNTR_RXLPIUSC_SHIFT (0U) +/*! RXLPIUSC - Rx LPI Microseconds Counter This field indicates the number of microseconds Rx LPI is asserted. */ +#define ENET_QOS_MAC_RX_LPI_USEC_CNTR_RXLPIUSC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_LPI_USEC_CNTR_RXLPIUSC_SHIFT)) & ENET_QOS_MAC_RX_LPI_USEC_CNTR_RXLPIUSC_MASK) +/*! @} */ + +/*! @name MAC_RX_LPI_TRAN_CNTR - Number of Times Rx LPI Entered */ +/*! @{ */ + +#define ENET_QOS_MAC_RX_LPI_TRAN_CNTR_RXLPITRC_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_RX_LPI_TRAN_CNTR_RXLPITRC_SHIFT (0U) +/*! RXLPITRC - Rx LPI Transition counter This field indicates the number of times Rx LPI Entry has occurred. */ +#define ENET_QOS_MAC_RX_LPI_TRAN_CNTR_RXLPITRC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_LPI_TRAN_CNTR_RXLPITRC_SHIFT)) & ENET_QOS_MAC_RX_LPI_TRAN_CNTR_RXLPITRC_MASK) +/*! @} */ + +/*! @name MAC_MMC_IPC_RX_INTERRUPT_MASK - MMC IPC Receive Interrupt Mask */ +/*! @{ */ + +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4GPIM_MASK (0x1U) +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4GPIM_SHIFT (0U) +/*! RXIPV4GPIM - MMC Receive IPV4 Good Packet Counter Interrupt Mask Setting this bit masks the + * interrupt when the rxipv4_gd_pkts counter reaches half of the maximum value or the maximum value. + * 0b0..MMC Receive IPV4 Good Packet Counter Interrupt Mask is disabled + * 0b1..MMC Receive IPV4 Good Packet Counter Interrupt Mask is enabled + */ +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4GPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4GPIM_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4GPIM_MASK) + +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4HERPIM_MASK (0x2U) +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4HERPIM_SHIFT (1U) +/*! RXIPV4HERPIM - MMC Receive IPV4 Header Error Packet Counter Interrupt Mask Setting this bit + * masks the interrupt when the rxipv4_hdrerr_pkts counter reaches half of the maximum value or the + * maximum value. + * 0b0..MMC Receive IPV4 Header Error Packet Counter Interrupt Mask is disabled + * 0b1..MMC Receive IPV4 Header Error Packet Counter Interrupt Mask is enabled + */ +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4HERPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4HERPIM_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4HERPIM_MASK) + +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4NOPAYPIM_MASK (0x4U) +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4NOPAYPIM_SHIFT (2U) +/*! RXIPV4NOPAYPIM - MMC Receive IPV4 No Payload Packet Counter Interrupt Mask Setting this bit + * masks the interrupt when the rxipv4_nopay_pkts counter reaches half of the maximum value or the + * maximum value. + * 0b0..MMC Receive IPV4 No Payload Packet Counter Interrupt Mask is disabled + * 0b1..MMC Receive IPV4 No Payload Packet Counter Interrupt Mask is enabled + */ +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4NOPAYPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4NOPAYPIM_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4NOPAYPIM_MASK) + +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4FRAGPIM_MASK (0x8U) +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4FRAGPIM_SHIFT (3U) +/*! RXIPV4FRAGPIM - MMC Receive IPV4 Fragmented Packet Counter Interrupt Mask Setting this bit masks + * the interrupt when the rxipv4_frag_pkts counter reaches half of the maximum value or the + * maximum value. + * 0b0..MMC Receive IPV4 Fragmented Packet Counter Interrupt Mask is disabled + * 0b1..MMC Receive IPV4 Fragmented Packet Counter Interrupt Mask is enabled + */ +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4FRAGPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4FRAGPIM_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4FRAGPIM_MASK) + +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4UDSBLPIM_MASK (0x10U) +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4UDSBLPIM_SHIFT (4U) +/*! RXIPV4UDSBLPIM - MMC Receive IPV4 UDP Checksum Disabled Packet Counter Interrupt Mask Setting + * this bit masks the interrupt when the rxipv4_udsbl_pkts counter reaches half of the maximum + * value or the maximum value. + * 0b0..MMC Receive IPV4 UDP Checksum Disabled Packet Counter Interrupt Mask is disabled + * 0b1..MMC Receive IPV4 UDP Checksum Disabled Packet Counter Interrupt Mask is enabled + */ +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4UDSBLPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4UDSBLPIM_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4UDSBLPIM_MASK) + +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6GPIM_MASK (0x20U) +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6GPIM_SHIFT (5U) +/*! RXIPV6GPIM - MMC Receive IPV6 Good Packet Counter Interrupt Mask Setting this bit masks the + * interrupt when the rxipv6_gd_pkts counter reaches half of the maximum value or the maximum value. + * 0b0..MMC Receive IPV6 Good Packet Counter Interrupt Mask is disabled + * 0b1..MMC Receive IPV6 Good Packet Counter Interrupt Mask is enabled + */ +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6GPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6GPIM_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6GPIM_MASK) + +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6HERPIM_MASK (0x40U) +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6HERPIM_SHIFT (6U) +/*! RXIPV6HERPIM - MMC Receive IPV6 Header Error Packet Counter Interrupt Mask Setting this bit + * masks the interrupt when the rxipv6_hdrerr_pkts counter reaches half of the maximum value or the + * maximum value. + * 0b0..MMC Receive IPV6 Header Error Packet Counter Interrupt Mask is disabled + * 0b1..MMC Receive IPV6 Header Error Packet Counter Interrupt Mask is enabled + */ +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6HERPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6HERPIM_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6HERPIM_MASK) + +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6NOPAYPIM_MASK (0x80U) +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6NOPAYPIM_SHIFT (7U) +/*! RXIPV6NOPAYPIM - MMC Receive IPV6 No Payload Packet Counter Interrupt Mask Setting this bit + * masks the interrupt when the rxipv6_nopay_pkts counter reaches half of the maximum value or the + * maximum value. + * 0b0..MMC Receive IPV6 No Payload Packet Counter Interrupt Mask is disabled + * 0b1..MMC Receive IPV6 No Payload Packet Counter Interrupt Mask is enabled + */ +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6NOPAYPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6NOPAYPIM_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6NOPAYPIM_MASK) + +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXUDPGPIM_MASK (0x100U) +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXUDPGPIM_SHIFT (8U) +/*! RXUDPGPIM - MMC Receive UDP Good Packet Counter Interrupt Mask Setting this bit masks the + * interrupt when the rxudp_gd_pkts counter reaches half of the maximum value or the maximum value. + * 0b0..MMC Receive UDP Good Packet Counter Interrupt Mask is disabled + * 0b1..MMC Receive UDP Good Packet Counter Interrupt Mask is enabled + */ +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXUDPGPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXUDPGPIM_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXUDPGPIM_MASK) + +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXUDPERPIM_MASK (0x200U) +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXUDPERPIM_SHIFT (9U) +/*! RXUDPERPIM - MMC Receive UDP Error Packet Counter Interrupt Mask Setting this bit masks the + * interrupt when the rxudp_err_pkts counter reaches half of the maximum value or the maximum value. + * 0b0..MMC Receive UDP Error Packet Counter Interrupt Mask is disabled + * 0b1..MMC Receive UDP Error Packet Counter Interrupt Mask is enabled + */ +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXUDPERPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXUDPERPIM_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXUDPERPIM_MASK) + +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXTCPGPIM_MASK (0x400U) +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXTCPGPIM_SHIFT (10U) +/*! RXTCPGPIM - MMC Receive TCP Good Packet Counter Interrupt Mask Setting this bit masks the + * interrupt when the rxtcp_gd_pkts counter reaches half of the maximum value or the maximum value. + * 0b0..MMC Receive TCP Good Packet Counter Interrupt Mask is disabled + * 0b1..MMC Receive TCP Good Packet Counter Interrupt Mask is enabled + */ +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXTCPGPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXTCPGPIM_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXTCPGPIM_MASK) + +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXTCPERPIM_MASK (0x800U) +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXTCPERPIM_SHIFT (11U) +/*! RXTCPERPIM - MMC Receive TCP Error Packet Counter Interrupt Mask Setting this bit masks the + * interrupt when the rxtcp_err_pkts counter reaches half of the maximum value or the maximum value. + * 0b0..MMC Receive TCP Error Packet Counter Interrupt Mask is disabled + * 0b1..MMC Receive TCP Error Packet Counter Interrupt Mask is enabled + */ +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXTCPERPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXTCPERPIM_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXTCPERPIM_MASK) + +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXICMPGPIM_MASK (0x1000U) +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXICMPGPIM_SHIFT (12U) +/*! RXICMPGPIM - MMC Receive ICMP Good Packet Counter Interrupt Mask Setting this bit masks the + * interrupt when the rxicmp_gd_pkts counter reaches half of the maximum value or the maximum value. + * 0b0..MMC Receive ICMP Good Packet Counter Interrupt Mask is disabled + * 0b1..MMC Receive ICMP Good Packet Counter Interrupt Mask is enabled + */ +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXICMPGPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXICMPGPIM_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXICMPGPIM_MASK) + +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXICMPERPIM_MASK (0x2000U) +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXICMPERPIM_SHIFT (13U) +/*! RXICMPERPIM - MMC Receive ICMP Error Packet Counter Interrupt Mask Setting this bit masks the + * interrupt when the rxicmp_err_pkts counter reaches half of the maximum value or the maximum + * value. + * 0b0..MMC Receive ICMP Error Packet Counter Interrupt Mask is disabled + * 0b1..MMC Receive ICMP Error Packet Counter Interrupt Mask is enabled + */ +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXICMPERPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXICMPERPIM_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXICMPERPIM_MASK) + +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4GOIM_MASK (0x10000U) +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4GOIM_SHIFT (16U) +/*! RXIPV4GOIM - MMC Receive IPV4 Good Octet Counter Interrupt Mask Setting this bit masks the + * interrupt when the rxipv4_gd_octets counter reaches half of the maximum value or the maximum value. + * 0b0..MMC Receive IPV4 Good Octet Counter Interrupt Mask is disabled + * 0b1..MMC Receive IPV4 Good Octet Counter Interrupt Mask is enabled + */ +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4GOIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4GOIM_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4GOIM_MASK) + +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4HEROIM_MASK (0x20000U) +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4HEROIM_SHIFT (17U) +/*! RXIPV4HEROIM - MMC Receive IPV4 Header Error Octet Counter Interrupt Mask Setting this bit masks + * the interrupt when the rxipv4_hdrerr_octets counter reaches half of the maximum value or the + * maximum value. + * 0b0..MMC Receive IPV4 Header Error Octet Counter Interrupt Mask is disabled + * 0b1..MMC Receive IPV4 Header Error Octet Counter Interrupt Mask is enabled + */ +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4HEROIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4HEROIM_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4HEROIM_MASK) + +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4NOPAYOIM_MASK (0x40000U) +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4NOPAYOIM_SHIFT (18U) +/*! RXIPV4NOPAYOIM - MMC Receive IPV4 No Payload Octet Counter Interrupt Mask Setting this bit masks + * the interrupt when the rxipv4_nopay_octets counter reaches half of the maximum value or the + * maximum value. + * 0b0..MMC Receive IPV4 No Payload Octet Counter Interrupt Mask is disabled + * 0b1..MMC Receive IPV4 No Payload Octet Counter Interrupt Mask is enabled + */ +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4NOPAYOIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4NOPAYOIM_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4NOPAYOIM_MASK) + +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4FRAGOIM_MASK (0x80000U) +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4FRAGOIM_SHIFT (19U) +/*! RXIPV4FRAGOIM - MMC Receive IPV4 Fragmented Octet Counter Interrupt Mask Setting this bit masks + * the interrupt when the rxipv4_frag_octets counter reaches half of the maximum value or the + * maximum value. + * 0b0..MMC Receive IPV4 Fragmented Octet Counter Interrupt Mask is disabled + * 0b1..MMC Receive IPV4 Fragmented Octet Counter Interrupt Mask is enabled + */ +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4FRAGOIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4FRAGOIM_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4FRAGOIM_MASK) + +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4UDSBLOIM_MASK (0x100000U) +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4UDSBLOIM_SHIFT (20U) +/*! RXIPV4UDSBLOIM - MMC Receive IPV4 UDP Checksum Disabled Octet Counter Interrupt Mask Setting + * this bit masks the interrupt when the rxipv4_udsbl_octets counter reaches half of the maximum + * value or the maximum value. + * 0b0..MMC Receive IPV4 UDP Checksum Disabled Octet Counter Interrupt Mask is disabled + * 0b1..MMC Receive IPV4 UDP Checksum Disabled Octet Counter Interrupt Mask is enabled + */ +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4UDSBLOIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4UDSBLOIM_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4UDSBLOIM_MASK) + +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6GOIM_MASK (0x200000U) +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6GOIM_SHIFT (21U) +/*! RXIPV6GOIM - MMC Receive IPV6 Good Octet Counter Interrupt Mask Setting this bit masks the + * interrupt when the rxipv6_gd_octets counter reaches half of the maximum value or the maximum value. + * 0b0..MMC Receive IPV6 Good Octet Counter Interrupt Mask is disabled + * 0b1..MMC Receive IPV6 Good Octet Counter Interrupt Mask is enabled + */ +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6GOIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6GOIM_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6GOIM_MASK) + +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6HEROIM_MASK (0x400000U) +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6HEROIM_SHIFT (22U) +/*! RXIPV6HEROIM - MMC Receive IPV6 Good Octet Counter Interrupt Mask Setting this bit masks the + * interrupt when the rxipv6_hdrerr_octets counter reaches half of the maximum value or the maximum + * value. + * 0b0..MMC Receive IPV6 Good Octet Counter Interrupt Mask is disabled + * 0b1..MMC Receive IPV6 Good Octet Counter Interrupt Mask is enabled + */ +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6HEROIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6HEROIM_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6HEROIM_MASK) + +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6NOPAYOIM_MASK (0x800000U) +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6NOPAYOIM_SHIFT (23U) +/*! RXIPV6NOPAYOIM - MMC Receive IPV6 Header Error Octet Counter Interrupt Mask Setting this bit + * masks the interrupt when the rxipv6_nopay_octets counter reaches half of the maximum value or the + * maximum value. + * 0b0..MMC Receive IPV6 Header Error Octet Counter Interrupt Mask is disabled + * 0b1..MMC Receive IPV6 Header Error Octet Counter Interrupt Mask is enabled + */ +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6NOPAYOIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6NOPAYOIM_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6NOPAYOIM_MASK) + +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXUDPGOIM_MASK (0x1000000U) +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXUDPGOIM_SHIFT (24U) +/*! RXUDPGOIM - MMC Receive IPV6 No Payload Octet Counter Interrupt Mask Setting this bit masks the + * interrupt when the rxudp_gd_octets counter reaches half of the maximum value or the maximum + * value. + * 0b0..MMC Receive IPV6 No Payload Octet Counter Interrupt Mask is disabled + * 0b1..MMC Receive IPV6 No Payload Octet Counter Interrupt Mask is enabled + */ +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXUDPGOIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXUDPGOIM_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXUDPGOIM_MASK) + +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXUDPEROIM_MASK (0x2000000U) +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXUDPEROIM_SHIFT (25U) +/*! RXUDPEROIM - MMC Receive UDP Good Octet Counter Interrupt Mask Setting this bit masks the + * interrupt when the rxudp_err_octets counter reaches half of the maximum value or the maximum value. + * 0b0..MMC Receive UDP Good Octet Counter Interrupt Mask is disabled + * 0b1..MMC Receive UDP Good Octet Counter Interrupt Mask is enabled + */ +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXUDPEROIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXUDPEROIM_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXUDPEROIM_MASK) + +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXTCPGOIM_MASK (0x4000000U) +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXTCPGOIM_SHIFT (26U) +/*! RXTCPGOIM - MMC Receive TCP Good Octet Counter Interrupt Mask Setting this bit masks the + * interrupt when the rxtcp_gd_octets counter reaches half of the maximum value or the maximum value. + * 0b0..MMC Receive TCP Good Octet Counter Interrupt Mask is disabled + * 0b1..MMC Receive TCP Good Octet Counter Interrupt Mask is enabled + */ +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXTCPGOIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXTCPGOIM_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXTCPGOIM_MASK) + +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXTCPEROIM_MASK (0x8000000U) +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXTCPEROIM_SHIFT (27U) +/*! RXTCPEROIM - MMC Receive TCP Error Octet Counter Interrupt Mask Setting this bit masks the + * interrupt when the rxtcp_err_octets counter reaches half of the maximum value or the maximum value. + * 0b0..MMC Receive TCP Error Octet Counter Interrupt Mask is disabled + * 0b1..MMC Receive TCP Error Octet Counter Interrupt Mask is enabled + */ +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXTCPEROIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXTCPEROIM_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXTCPEROIM_MASK) + +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXICMPGOIM_MASK (0x10000000U) +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXICMPGOIM_SHIFT (28U) +/*! RXICMPGOIM - MMC Receive ICMP Good Octet Counter Interrupt Mask Setting this bit masks the + * interrupt when the rxicmp_gd_octets counter reaches half of the maximum value or the maximum value. + * 0b0..MMC Receive ICMP Good Octet Counter Interrupt Mask is disabled + * 0b1..MMC Receive ICMP Good Octet Counter Interrupt Mask is enabled + */ +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXICMPGOIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXICMPGOIM_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXICMPGOIM_MASK) + +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXICMPEROIM_MASK (0x20000000U) +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXICMPEROIM_SHIFT (29U) +/*! RXICMPEROIM - MMC Receive ICMP Error Octet Counter Interrupt Mask Setting this bit masks the + * interrupt when the rxicmp_err_octets counter reaches half of the maximum value or the maximum + * value. + * 0b0..MMC Receive ICMP Error Octet Counter Interrupt Mask is disabled + * 0b1..MMC Receive ICMP Error Octet Counter Interrupt Mask is enabled + */ +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXICMPEROIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXICMPEROIM_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXICMPEROIM_MASK) +/*! @} */ + +/*! @name MAC_MMC_IPC_RX_INTERRUPT - MMC IPC Receive Interrupt */ +/*! @{ */ + +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4GPIS_MASK (0x1U) +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4GPIS_SHIFT (0U) +/*! RXIPV4GPIS - MMC Receive IPV4 Good Packet Counter Interrupt Status This bit is set when the + * rxipv4_gd_pkts counter reaches half of the maximum value or the maximum value. + * 0b0..MMC Receive IPV4 Good Packet Counter Interrupt Status not detected + * 0b1..MMC Receive IPV4 Good Packet Counter Interrupt Status detected + */ +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4GPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4GPIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4GPIS_MASK) + +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4HERPIS_MASK (0x2U) +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4HERPIS_SHIFT (1U) +/*! RXIPV4HERPIS - MMC Receive IPV4 Header Error Packet Counter Interrupt Status This bit is set + * when the rxipv4_hdrerr_pkts counter reaches half of the maximum value or the maximum value. + * 0b0..MMC Receive IPV4 Header Error Packet Counter Interrupt Status not detected + * 0b1..MMC Receive IPV4 Header Error Packet Counter Interrupt Status detected + */ +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4HERPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4HERPIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4HERPIS_MASK) + +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4NOPAYPIS_MASK (0x4U) +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4NOPAYPIS_SHIFT (2U) +/*! RXIPV4NOPAYPIS - MMC Receive IPV4 No Payload Packet Counter Interrupt Status This bit is set + * when the rxipv4_nopay_pkts counter reaches half of the maximum value or the maximum value. + * 0b0..MMC Receive IPV4 No Payload Packet Counter Interrupt Status not detected + * 0b1..MMC Receive IPV4 No Payload Packet Counter Interrupt Status detected + */ +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4NOPAYPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4NOPAYPIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4NOPAYPIS_MASK) + +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4FRAGPIS_MASK (0x8U) +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4FRAGPIS_SHIFT (3U) +/*! RXIPV4FRAGPIS - MMC Receive IPV4 Fragmented Packet Counter Interrupt Status This bit is set when + * the rxipv4_frag_pkts counter reaches half of the maximum value or the maximum value. + * 0b0..MMC Receive IPV4 Fragmented Packet Counter Interrupt Status not detected + * 0b1..MMC Receive IPV4 Fragmented Packet Counter Interrupt Status detected + */ +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4FRAGPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4FRAGPIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4FRAGPIS_MASK) + +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4UDSBLPIS_MASK (0x10U) +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4UDSBLPIS_SHIFT (4U) +/*! RXIPV4UDSBLPIS - MMC Receive IPV4 UDP Checksum Disabled Packet Counter Interrupt Status This bit + * is set when the rxipv4_udsbl_pkts counter reaches half of the maximum value or the maximum + * value. + * 0b0..MMC Receive IPV4 UDP Checksum Disabled Packet Counter Interrupt Status not detected + * 0b1..MMC Receive IPV4 UDP Checksum Disabled Packet Counter Interrupt Status detected + */ +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4UDSBLPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4UDSBLPIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4UDSBLPIS_MASK) + +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6GPIS_MASK (0x20U) +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6GPIS_SHIFT (5U) +/*! RXIPV6GPIS - MMC Receive IPV6 Good Packet Counter Interrupt Status This bit is set when the + * rxipv6_gd_pkts counter reaches half of the maximum value or the maximum value. + * 0b0..MMC Receive IPV6 Good Packet Counter Interrupt Status not detected + * 0b1..MMC Receive IPV6 Good Packet Counter Interrupt Status detected + */ +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6GPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6GPIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6GPIS_MASK) + +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6HERPIS_MASK (0x40U) +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6HERPIS_SHIFT (6U) +/*! RXIPV6HERPIS - MMC Receive IPV6 Header Error Packet Counter Interrupt Status This bit is set + * when the rxipv6_hdrerr_pkts counter reaches half of the maximum value or the maximum value. + * 0b0..MMC Receive IPV6 Header Error Packet Counter Interrupt Status not detected + * 0b1..MMC Receive IPV6 Header Error Packet Counter Interrupt Status detected + */ +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6HERPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6HERPIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6HERPIS_MASK) + +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6NOPAYPIS_MASK (0x80U) +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6NOPAYPIS_SHIFT (7U) +/*! RXIPV6NOPAYPIS - MMC Receive IPV6 No Payload Packet Counter Interrupt Status This bit is set + * when the rxipv6_nopay_pkts counter reaches half of the maximum value or the maximum value. + * 0b0..MMC Receive IPV6 No Payload Packet Counter Interrupt Status not detected + * 0b1..MMC Receive IPV6 No Payload Packet Counter Interrupt Status detected + */ +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6NOPAYPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6NOPAYPIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6NOPAYPIS_MASK) + +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXUDPGPIS_MASK (0x100U) +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXUDPGPIS_SHIFT (8U) +/*! RXUDPGPIS - MC Receive UDP Good Packet Counter Interrupt Status This bit is set when the + * rxudp_gd_pkts counter reaches half of the maximum value or the maximum value. + * 0b0..MMC Receive UDP Good Packet Counter Interrupt Status not detected + * 0b1..MMC Receive UDP Good Packet Counter Interrupt Status detected + */ +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXUDPGPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXUDPGPIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXUDPGPIS_MASK) + +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXUDPERPIS_MASK (0x200U) +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXUDPERPIS_SHIFT (9U) +/*! RXUDPERPIS - MMC Receive UDP Error Packet Counter Interrupt Status This bit is set when the + * rxudp_err_pkts counter reaches half of the maximum value or the maximum value. + * 0b0..MMC Receive UDP Error Packet Counter Interrupt Status not detected + * 0b1..MMC Receive UDP Error Packet Counter Interrupt Status detected + */ +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXUDPERPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXUDPERPIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXUDPERPIS_MASK) + +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXTCPGPIS_MASK (0x400U) +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXTCPGPIS_SHIFT (10U) +/*! RXTCPGPIS - MMC Receive TCP Good Packet Counter Interrupt Status This bit is set when the + * rxtcp_gd_pkts counter reaches half of the maximum value or the maximum value. + * 0b0..MMC Receive TCP Good Packet Counter Interrupt Status not detected + * 0b1..MMC Receive TCP Good Packet Counter Interrupt Status detected + */ +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXTCPGPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXTCPGPIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXTCPGPIS_MASK) + +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXTCPERPIS_MASK (0x800U) +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXTCPERPIS_SHIFT (11U) +/*! RXTCPERPIS - MMC Receive TCP Error Packet Counter Interrupt Status This bit is set when the + * rxtcp_err_pkts counter reaches half of the maximum value or the maximum value. + * 0b0..MMC Receive TCP Error Packet Counter Interrupt Status not detected + * 0b1..MMC Receive TCP Error Packet Counter Interrupt Status detected + */ +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXTCPERPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXTCPERPIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXTCPERPIS_MASK) + +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXICMPGPIS_MASK (0x1000U) +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXICMPGPIS_SHIFT (12U) +/*! RXICMPGPIS - MMC Receive ICMP Good Packet Counter Interrupt Status This bit is set when the + * rxicmp_gd_pkts counter reaches half of the maximum value or the maximum value. + * 0b0..MMC Receive ICMP Good Packet Counter Interrupt Status not detected + * 0b1..MMC Receive ICMP Good Packet Counter Interrupt Status detected + */ +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXICMPGPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXICMPGPIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXICMPGPIS_MASK) + +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXICMPERPIS_MASK (0x2000U) +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXICMPERPIS_SHIFT (13U) +/*! RXICMPERPIS - MMC Receive ICMP Error Packet Counter Interrupt Status This bit is set when the + * rxicmp_err_pkts counter reaches half of the maximum value or the maximum value. + * 0b0..MMC Receive ICMP Error Packet Counter Interrupt Status not detected + * 0b1..MMC Receive ICMP Error Packet Counter Interrupt Status detected + */ +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXICMPERPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXICMPERPIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXICMPERPIS_MASK) + +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4GOIS_MASK (0x10000U) +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4GOIS_SHIFT (16U) +/*! RXIPV4GOIS - MMC Receive IPV4 Good Octet Counter Interrupt Status This bit is set when the + * rxipv4_gd_octets counter reaches half of the maximum value or the maximum value. + * 0b0..MMC Receive IPV4 Good Octet Counter Interrupt Status not detected + * 0b1..MMC Receive IPV4 Good Octet Counter Interrupt Status detected + */ +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4GOIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4GOIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4GOIS_MASK) + +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4HEROIS_MASK (0x20000U) +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4HEROIS_SHIFT (17U) +/*! RXIPV4HEROIS - MMC Receive IPV4 Header Error Octet Counter Interrupt Status This bit is set when + * the rxipv4_hdrerr_octets counter reaches half of the maximum value or the maximum value. + * 0b0..MMC Receive IPV4 Header Error Octet Counter Interrupt Status not detected + * 0b1..MMC Receive IPV4 Header Error Octet Counter Interrupt Status detected + */ +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4HEROIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4HEROIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4HEROIS_MASK) + +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4NOPAYOIS_MASK (0x40000U) +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4NOPAYOIS_SHIFT (18U) +/*! RXIPV4NOPAYOIS - MMC Receive IPV4 No Payload Octet Counter Interrupt Status This bit is set when + * the rxipv4_nopay_octets counter reaches half of the maximum value or the maximum value. + * 0b0..MMC Receive IPV4 No Payload Octet Counter Interrupt Status not detected + * 0b1..MMC Receive IPV4 No Payload Octet Counter Interrupt Status detected + */ +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4NOPAYOIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4NOPAYOIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4NOPAYOIS_MASK) + +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4FRAGOIS_MASK (0x80000U) +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4FRAGOIS_SHIFT (19U) +/*! RXIPV4FRAGOIS - MMC Receive IPV4 Fragmented Octet Counter Interrupt Status This bit is set when + * the rxipv4_frag_octets counter reaches half of the maximum value or the maximum value. + * 0b0..MMC Receive IPV4 Fragmented Octet Counter Interrupt Status not detected + * 0b1..MMC Receive IPV4 Fragmented Octet Counter Interrupt Status detected + */ +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4FRAGOIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4FRAGOIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4FRAGOIS_MASK) + +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4UDSBLOIS_MASK (0x100000U) +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4UDSBLOIS_SHIFT (20U) +/*! RXIPV4UDSBLOIS - MMC Receive IPV4 UDP Checksum Disabled Octet Counter Interrupt Status This bit + * is set when the rxipv4_udsbl_octets counter reaches half of the maximum value or the maximum + * value. + * 0b0..MMC Receive IPV4 UDP Checksum Disabled Octet Counter Interrupt Status not detected + * 0b1..MMC Receive IPV4 UDP Checksum Disabled Octet Counter Interrupt Status detected + */ +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4UDSBLOIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4UDSBLOIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4UDSBLOIS_MASK) + +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6GOIS_MASK (0x200000U) +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6GOIS_SHIFT (21U) +/*! RXIPV6GOIS - MMC Receive IPV6 Good Octet Counter Interrupt Status This bit is set when the + * rxipv6_gd_octets counter reaches half of the maximum value or the maximum value. + * 0b0..MMC Receive IPV6 Good Octet Counter Interrupt Status not detected + * 0b1..MMC Receive IPV6 Good Octet Counter Interrupt Status detected + */ +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6GOIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6GOIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6GOIS_MASK) + +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6HEROIS_MASK (0x400000U) +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6HEROIS_SHIFT (22U) +/*! RXIPV6HEROIS - MMC Receive IPV6 Header Error Octet Counter Interrupt Status This bit is set when + * the rxipv6_hdrerr_octets counter reaches half of the maximum value or the maximum value. + * 0b0..MMC Receive IPV6 Header Error Octet Counter Interrupt Status not detected + * 0b1..MMC Receive IPV6 Header Error Octet Counter Interrupt Status detected + */ +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6HEROIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6HEROIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6HEROIS_MASK) + +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6NOPAYOIS_MASK (0x800000U) +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6NOPAYOIS_SHIFT (23U) +/*! RXIPV6NOPAYOIS - MMC Receive IPV6 No Payload Octet Counter Interrupt Status This bit is set when + * the rxipv6_nopay_octets counter reaches half of the maximum value or the maximum value. + * 0b0..MMC Receive IPV6 No Payload Octet Counter Interrupt Status not detected + * 0b1..MMC Receive IPV6 No Payload Octet Counter Interrupt Status detected + */ +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6NOPAYOIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6NOPAYOIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6NOPAYOIS_MASK) + +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXUDPGOIS_MASK (0x1000000U) +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXUDPGOIS_SHIFT (24U) +/*! RXUDPGOIS - MMC Receive UDP Good Octet Counter Interrupt Status This bit is set when the + * rxudp_gd_octets counter reaches half of the maximum value or the maximum value. + * 0b0..MMC Receive UDP Good Octet Counter Interrupt Status not detected + * 0b1..MMC Receive UDP Good Octet Counter Interrupt Status detected + */ +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXUDPGOIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXUDPGOIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXUDPGOIS_MASK) + +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXUDPEROIS_MASK (0x2000000U) +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXUDPEROIS_SHIFT (25U) +/*! RXUDPEROIS - MMC Receive UDP Error Octet Counter Interrupt Status This bit is set when the + * rxudp_err_octets counter reaches half of the maximum value or the maximum value. + * 0b0..MMC Receive UDP Error Octet Counter Interrupt Status not detected + * 0b1..MMC Receive UDP Error Octet Counter Interrupt Status detected + */ +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXUDPEROIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXUDPEROIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXUDPEROIS_MASK) + +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXTCPGOIS_MASK (0x4000000U) +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXTCPGOIS_SHIFT (26U) +/*! RXTCPGOIS - MMC Receive TCP Good Octet Counter Interrupt Status This bit is set when the + * rxtcp_gd_octets counter reaches half of the maximum value or the maximum value. + * 0b0..MMC Receive TCP Good Octet Counter Interrupt Status not detected + * 0b1..MMC Receive TCP Good Octet Counter Interrupt Status detected + */ +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXTCPGOIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXTCPGOIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXTCPGOIS_MASK) + +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXTCPEROIS_MASK (0x8000000U) +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXTCPEROIS_SHIFT (27U) +/*! RXTCPEROIS - MMC Receive TCP Error Octet Counter Interrupt Status This bit is set when the + * rxtcp_err_octets counter reaches half of the maximum value or the maximum value. + * 0b0..MMC Receive TCP Error Octet Counter Interrupt Status not detected + * 0b1..MMC Receive TCP Error Octet Counter Interrupt Status detected + */ +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXTCPEROIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXTCPEROIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXTCPEROIS_MASK) + +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXICMPGOIS_MASK (0x10000000U) +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXICMPGOIS_SHIFT (28U) +/*! RXICMPGOIS - MMC Receive ICMP Good Octet Counter Interrupt Status This bit is set when the + * rxicmp_gd_octets counter reaches half of the maximum value or the maximum value. + * 0b0..MMC Receive ICMP Good Octet Counter Interrupt Status not detected + * 0b1..MMC Receive ICMP Good Octet Counter Interrupt Status detected + */ +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXICMPGOIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXICMPGOIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXICMPGOIS_MASK) + +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXICMPEROIS_MASK (0x20000000U) +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXICMPEROIS_SHIFT (29U) +/*! RXICMPEROIS - MMC Receive ICMP Error Octet Counter Interrupt Status This bit is set when the + * rxicmp_err_octets counter reaches half of the maximum value or the maximum value. + * 0b0..MMC Receive ICMP Error Octet Counter Interrupt Status not detected + * 0b1..MMC Receive ICMP Error Octet Counter Interrupt Status detected + */ +#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXICMPEROIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXICMPEROIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXICMPEROIS_MASK) +/*! @} */ + +/*! @name MAC_RXIPV4_GOOD_PACKETS - Good IPv4 Datagrams Received */ +/*! @{ */ + +#define ENET_QOS_MAC_RXIPV4_GOOD_PACKETS_RXIPV4GDPKT_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_RXIPV4_GOOD_PACKETS_RXIPV4GDPKT_SHIFT (0U) +/*! RXIPV4GDPKT - RxIPv4 Good Packets This field indicates the number of good IPv4 datagrams received with the TCP, UDP, or ICMP payload. */ +#define ENET_QOS_MAC_RXIPV4_GOOD_PACKETS_RXIPV4GDPKT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXIPV4_GOOD_PACKETS_RXIPV4GDPKT_SHIFT)) & ENET_QOS_MAC_RXIPV4_GOOD_PACKETS_RXIPV4GDPKT_MASK) +/*! @} */ + +/*! @name MAC_RXIPV4_HEADER_ERROR_PACKETS - IPv4 Datagrams Received with Header Errors */ +/*! @{ */ + +#define ENET_QOS_MAC_RXIPV4_HEADER_ERROR_PACKETS_RXIPV4HDRERRPKT_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_RXIPV4_HEADER_ERROR_PACKETS_RXIPV4HDRERRPKT_SHIFT (0U) +/*! RXIPV4HDRERRPKT - RxIPv4 Header Error Packets This field indicates the number of IPv4 datagrams + * received with header (checksum, length, or version mismatch) errors. + */ +#define ENET_QOS_MAC_RXIPV4_HEADER_ERROR_PACKETS_RXIPV4HDRERRPKT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXIPV4_HEADER_ERROR_PACKETS_RXIPV4HDRERRPKT_SHIFT)) & ENET_QOS_MAC_RXIPV4_HEADER_ERROR_PACKETS_RXIPV4HDRERRPKT_MASK) +/*! @} */ + +/*! @name MAC_RXIPV4_NO_PAYLOAD_PACKETS - IPv4 Datagrams Received with No Payload */ +/*! @{ */ + +#define ENET_QOS_MAC_RXIPV4_NO_PAYLOAD_PACKETS_RXIPV4NOPAYPKT_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_RXIPV4_NO_PAYLOAD_PACKETS_RXIPV4NOPAYPKT_SHIFT (0U) +/*! RXIPV4NOPAYPKT - RxIPv4 Payload Packets This field indicates the number of IPv4 datagram packets + * received that did not have a TCP, UDP, or ICMP payload. + */ +#define ENET_QOS_MAC_RXIPV4_NO_PAYLOAD_PACKETS_RXIPV4NOPAYPKT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXIPV4_NO_PAYLOAD_PACKETS_RXIPV4NOPAYPKT_SHIFT)) & ENET_QOS_MAC_RXIPV4_NO_PAYLOAD_PACKETS_RXIPV4NOPAYPKT_MASK) +/*! @} */ + +/*! @name MAC_RXIPV4_FRAGMENTED_PACKETS - IPv4 Datagrams Received with Fragmentation */ +/*! @{ */ + +#define ENET_QOS_MAC_RXIPV4_FRAGMENTED_PACKETS_RXIPV4FRAGPKT_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_RXIPV4_FRAGMENTED_PACKETS_RXIPV4FRAGPKT_SHIFT (0U) +/*! RXIPV4FRAGPKT - RxIPv4 Fragmented Packets This field indicates the number of good IPv4 datagrams received with fragmentation. */ +#define ENET_QOS_MAC_RXIPV4_FRAGMENTED_PACKETS_RXIPV4FRAGPKT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXIPV4_FRAGMENTED_PACKETS_RXIPV4FRAGPKT_SHIFT)) & ENET_QOS_MAC_RXIPV4_FRAGMENTED_PACKETS_RXIPV4FRAGPKT_MASK) +/*! @} */ + +/*! @name MAC_RXIPV4_UDP_CHECKSUM_DISABLED_PACKETS - IPv4 Datagrams Received with UDP Checksum Disabled */ +/*! @{ */ + +#define ENET_QOS_MAC_RXIPV4_UDP_CHECKSUM_DISABLED_PACKETS_RXIPV4UDSBLPKT_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_RXIPV4_UDP_CHECKSUM_DISABLED_PACKETS_RXIPV4UDSBLPKT_SHIFT (0U) +/*! RXIPV4UDSBLPKT - RxIPv4 UDP Checksum Disabled Packets This field indicates the number of good + * IPv4 datagrams received that had a UDP payload with checksum disabled. + */ +#define ENET_QOS_MAC_RXIPV4_UDP_CHECKSUM_DISABLED_PACKETS_RXIPV4UDSBLPKT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXIPV4_UDP_CHECKSUM_DISABLED_PACKETS_RXIPV4UDSBLPKT_SHIFT)) & ENET_QOS_MAC_RXIPV4_UDP_CHECKSUM_DISABLED_PACKETS_RXIPV4UDSBLPKT_MASK) +/*! @} */ + +/*! @name MAC_RXIPV6_GOOD_PACKETS - Good IPv6 Datagrams Received */ +/*! @{ */ + +#define ENET_QOS_MAC_RXIPV6_GOOD_PACKETS_RXIPV6GDPKT_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_RXIPV6_GOOD_PACKETS_RXIPV6GDPKT_SHIFT (0U) +/*! RXIPV6GDPKT - RxIPv6 Good Packets This field indicates the number of good IPv6 datagrams received with the TCP, UDP, or ICMP payload. */ +#define ENET_QOS_MAC_RXIPV6_GOOD_PACKETS_RXIPV6GDPKT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXIPV6_GOOD_PACKETS_RXIPV6GDPKT_SHIFT)) & ENET_QOS_MAC_RXIPV6_GOOD_PACKETS_RXIPV6GDPKT_MASK) +/*! @} */ + +/*! @name MAC_RXIPV6_HEADER_ERROR_PACKETS - IPv6 Datagrams Received with Header Errors */ +/*! @{ */ + +#define ENET_QOS_MAC_RXIPV6_HEADER_ERROR_PACKETS_RXIPV6HDRERRPKT_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_RXIPV6_HEADER_ERROR_PACKETS_RXIPV6HDRERRPKT_SHIFT (0U) +/*! RXIPV6HDRERRPKT - RxIPv6 Header Error Packets This field indicates the number of IPv6 datagrams + * received with header (length or version mismatch) errors. + */ +#define ENET_QOS_MAC_RXIPV6_HEADER_ERROR_PACKETS_RXIPV6HDRERRPKT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXIPV6_HEADER_ERROR_PACKETS_RXIPV6HDRERRPKT_SHIFT)) & ENET_QOS_MAC_RXIPV6_HEADER_ERROR_PACKETS_RXIPV6HDRERRPKT_MASK) +/*! @} */ + +/*! @name MAC_RXIPV6_NO_PAYLOAD_PACKETS - IPv6 Datagrams Received with No Payload */ +/*! @{ */ + +#define ENET_QOS_MAC_RXIPV6_NO_PAYLOAD_PACKETS_RXIPV6NOPAYPKT_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_RXIPV6_NO_PAYLOAD_PACKETS_RXIPV6NOPAYPKT_SHIFT (0U) +/*! RXIPV6NOPAYPKT - RxIPv6 Payload Packets This field indicates the number of IPv6 datagram packets + * received that did not have a TCP, UDP, or ICMP payload. + */ +#define ENET_QOS_MAC_RXIPV6_NO_PAYLOAD_PACKETS_RXIPV6NOPAYPKT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXIPV6_NO_PAYLOAD_PACKETS_RXIPV6NOPAYPKT_SHIFT)) & ENET_QOS_MAC_RXIPV6_NO_PAYLOAD_PACKETS_RXIPV6NOPAYPKT_MASK) +/*! @} */ + +/*! @name MAC_RXUDP_GOOD_PACKETS - IPv6 Datagrams Received with Good UDP */ +/*! @{ */ + +#define ENET_QOS_MAC_RXUDP_GOOD_PACKETS_RXUDPGDPKT_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_RXUDP_GOOD_PACKETS_RXUDPGDPKT_SHIFT (0U) +/*! RXUDPGDPKT - RxUDP Good Packets This field indicates the number of good IP datagrams received with a good UDP payload. */ +#define ENET_QOS_MAC_RXUDP_GOOD_PACKETS_RXUDPGDPKT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXUDP_GOOD_PACKETS_RXUDPGDPKT_SHIFT)) & ENET_QOS_MAC_RXUDP_GOOD_PACKETS_RXUDPGDPKT_MASK) +/*! @} */ + +/*! @name MAC_RXUDP_ERROR_PACKETS - IPv6 Datagrams Received with UDP Checksum Error */ +/*! @{ */ + +#define ENET_QOS_MAC_RXUDP_ERROR_PACKETS_RXUDPERRPKT_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_RXUDP_ERROR_PACKETS_RXUDPERRPKT_SHIFT (0U) +/*! RXUDPERRPKT - RxUDP Error Packets This field indicates the number of good IP datagrams received + * whose UDP payload has a checksum error. + */ +#define ENET_QOS_MAC_RXUDP_ERROR_PACKETS_RXUDPERRPKT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXUDP_ERROR_PACKETS_RXUDPERRPKT_SHIFT)) & ENET_QOS_MAC_RXUDP_ERROR_PACKETS_RXUDPERRPKT_MASK) +/*! @} */ + +/*! @name MAC_RXTCP_GOOD_PACKETS - IPv6 Datagrams Received with Good TCP Payload */ +/*! @{ */ + +#define ENET_QOS_MAC_RXTCP_GOOD_PACKETS_RXTCPGDPKT_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_RXTCP_GOOD_PACKETS_RXTCPGDPKT_SHIFT (0U) +/*! RXTCPGDPKT - RxTCP Good Packets This field indicates the number of good IP datagrams received with a good TCP payload. */ +#define ENET_QOS_MAC_RXTCP_GOOD_PACKETS_RXTCPGDPKT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXTCP_GOOD_PACKETS_RXTCPGDPKT_SHIFT)) & ENET_QOS_MAC_RXTCP_GOOD_PACKETS_RXTCPGDPKT_MASK) +/*! @} */ + +/*! @name MAC_RXTCP_ERROR_PACKETS - IPv6 Datagrams Received with TCP Checksum Error */ +/*! @{ */ + +#define ENET_QOS_MAC_RXTCP_ERROR_PACKETS_RXTCPERRPKT_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_RXTCP_ERROR_PACKETS_RXTCPERRPKT_SHIFT (0U) +/*! RXTCPERRPKT - RxTCP Error Packets This field indicates the number of good IP datagrams received + * whose TCP payload has a checksum error. + */ +#define ENET_QOS_MAC_RXTCP_ERROR_PACKETS_RXTCPERRPKT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXTCP_ERROR_PACKETS_RXTCPERRPKT_SHIFT)) & ENET_QOS_MAC_RXTCP_ERROR_PACKETS_RXTCPERRPKT_MASK) +/*! @} */ + +/*! @name MAC_RXICMP_GOOD_PACKETS - IPv6 Datagrams Received with Good ICMP Payload */ +/*! @{ */ + +#define ENET_QOS_MAC_RXICMP_GOOD_PACKETS_RXICMPGDPKT_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_RXICMP_GOOD_PACKETS_RXICMPGDPKT_SHIFT (0U) +/*! RXICMPGDPKT - RxICMP Good Packets This field indicates the number of good IP datagrams received with a good ICMP payload. */ +#define ENET_QOS_MAC_RXICMP_GOOD_PACKETS_RXICMPGDPKT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXICMP_GOOD_PACKETS_RXICMPGDPKT_SHIFT)) & ENET_QOS_MAC_RXICMP_GOOD_PACKETS_RXICMPGDPKT_MASK) +/*! @} */ + +/*! @name MAC_RXICMP_ERROR_PACKETS - IPv6 Datagrams Received with ICMP Checksum Error */ +/*! @{ */ + +#define ENET_QOS_MAC_RXICMP_ERROR_PACKETS_RXICMPERRPKT_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_RXICMP_ERROR_PACKETS_RXICMPERRPKT_SHIFT (0U) +/*! RXICMPERRPKT - RxICMP Error Packets This field indicates the number of good IP datagrams + * received whose ICMP payload has a checksum error. + */ +#define ENET_QOS_MAC_RXICMP_ERROR_PACKETS_RXICMPERRPKT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXICMP_ERROR_PACKETS_RXICMPERRPKT_SHIFT)) & ENET_QOS_MAC_RXICMP_ERROR_PACKETS_RXICMPERRPKT_MASK) +/*! @} */ + +/*! @name MAC_RXIPV4_GOOD_OCTETS - Good Bytes Received in IPv4 Datagrams */ +/*! @{ */ + +#define ENET_QOS_MAC_RXIPV4_GOOD_OCTETS_RXIPV4GDOCT_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_RXIPV4_GOOD_OCTETS_RXIPV4GDOCT_SHIFT (0U) +/*! RXIPV4GDOCT - RxIPv4 Good Octets This field indicates the number of bytes received in good IPv4 + * datagrams encapsulating TCP, UDP, or ICMP data. + */ +#define ENET_QOS_MAC_RXIPV4_GOOD_OCTETS_RXIPV4GDOCT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXIPV4_GOOD_OCTETS_RXIPV4GDOCT_SHIFT)) & ENET_QOS_MAC_RXIPV4_GOOD_OCTETS_RXIPV4GDOCT_MASK) +/*! @} */ + +/*! @name MAC_RXIPV4_HEADER_ERROR_OCTETS - Bytes Received in IPv4 Datagrams with Header Errors */ +/*! @{ */ + +#define ENET_QOS_MAC_RXIPV4_HEADER_ERROR_OCTETS_RXIPV4HDRERROCT_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_RXIPV4_HEADER_ERROR_OCTETS_RXIPV4HDRERROCT_SHIFT (0U) +/*! RXIPV4HDRERROCT - RxIPv4 Header Error Octets This field indicates the number of bytes received + * in IPv4 datagrams with header errors (checksum, length, version mismatch). + */ +#define ENET_QOS_MAC_RXIPV4_HEADER_ERROR_OCTETS_RXIPV4HDRERROCT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXIPV4_HEADER_ERROR_OCTETS_RXIPV4HDRERROCT_SHIFT)) & ENET_QOS_MAC_RXIPV4_HEADER_ERROR_OCTETS_RXIPV4HDRERROCT_MASK) +/*! @} */ + +/*! @name MAC_RXIPV4_NO_PAYLOAD_OCTETS - Bytes Received in IPv4 Datagrams with No Payload */ +/*! @{ */ + +#define ENET_QOS_MAC_RXIPV4_NO_PAYLOAD_OCTETS_RXIPV4NOPAYOCT_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_RXIPV4_NO_PAYLOAD_OCTETS_RXIPV4NOPAYOCT_SHIFT (0U) +/*! RXIPV4NOPAYOCT - RxIPv4 Payload Octets This field indicates the number of bytes received in IPv4 + * datagrams that did not have a TCP, UDP, or ICMP payload. + */ +#define ENET_QOS_MAC_RXIPV4_NO_PAYLOAD_OCTETS_RXIPV4NOPAYOCT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXIPV4_NO_PAYLOAD_OCTETS_RXIPV4NOPAYOCT_SHIFT)) & ENET_QOS_MAC_RXIPV4_NO_PAYLOAD_OCTETS_RXIPV4NOPAYOCT_MASK) +/*! @} */ + +/*! @name MAC_RXIPV4_FRAGMENTED_OCTETS - Bytes Received in Fragmented IPv4 Datagrams */ +/*! @{ */ + +#define ENET_QOS_MAC_RXIPV4_FRAGMENTED_OCTETS_RXIPV4FRAGOCT_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_RXIPV4_FRAGMENTED_OCTETS_RXIPV4FRAGOCT_SHIFT (0U) +/*! RXIPV4FRAGOCT - RxIPv4 Fragmented Octets This field indicates the number of bytes received in fragmented IPv4 datagrams. */ +#define ENET_QOS_MAC_RXIPV4_FRAGMENTED_OCTETS_RXIPV4FRAGOCT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXIPV4_FRAGMENTED_OCTETS_RXIPV4FRAGOCT_SHIFT)) & ENET_QOS_MAC_RXIPV4_FRAGMENTED_OCTETS_RXIPV4FRAGOCT_MASK) +/*! @} */ + +/*! @name MAC_RXIPV4_UDP_CHECKSUM_DISABLE_OCTETS - Bytes Received with UDP Checksum Disabled */ +/*! @{ */ + +#define ENET_QOS_MAC_RXIPV4_UDP_CHECKSUM_DISABLE_OCTETS_RXIPV4UDSBLOCT_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_RXIPV4_UDP_CHECKSUM_DISABLE_OCTETS_RXIPV4UDSBLOCT_SHIFT (0U) +/*! RXIPV4UDSBLOCT - RxIPv4 UDP Checksum Disable Octets This field indicates the number of bytes + * received in a UDP segment that had the UDP checksum disabled. + */ +#define ENET_QOS_MAC_RXIPV4_UDP_CHECKSUM_DISABLE_OCTETS_RXIPV4UDSBLOCT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXIPV4_UDP_CHECKSUM_DISABLE_OCTETS_RXIPV4UDSBLOCT_SHIFT)) & ENET_QOS_MAC_RXIPV4_UDP_CHECKSUM_DISABLE_OCTETS_RXIPV4UDSBLOCT_MASK) +/*! @} */ + +/*! @name MAC_RXIPV6_GOOD_OCTETS - Bytes Received in Good IPv6 Datagrams */ +/*! @{ */ + +#define ENET_QOS_MAC_RXIPV6_GOOD_OCTETS_RXIPV6GDOCT_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_RXIPV6_GOOD_OCTETS_RXIPV6GDOCT_SHIFT (0U) +/*! RXIPV6GDOCT - RxIPv6 Good Octets This field indicates the number of bytes received in good IPv6 + * datagrams encapsulating TCP, UDP, or ICMP data. + */ +#define ENET_QOS_MAC_RXIPV6_GOOD_OCTETS_RXIPV6GDOCT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXIPV6_GOOD_OCTETS_RXIPV6GDOCT_SHIFT)) & ENET_QOS_MAC_RXIPV6_GOOD_OCTETS_RXIPV6GDOCT_MASK) +/*! @} */ + +/*! @name MAC_RXIPV6_HEADER_ERROR_OCTETS - Bytes Received in IPv6 Datagrams with Data Errors */ +/*! @{ */ + +#define ENET_QOS_MAC_RXIPV6_HEADER_ERROR_OCTETS_RXIPV6HDRERROCT_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_RXIPV6_HEADER_ERROR_OCTETS_RXIPV6HDRERROCT_SHIFT (0U) +/*! RXIPV6HDRERROCT - RxIPv6 Header Error Octets This field indicates the number of bytes received + * in IPv6 datagrams with header errors (length, version mismatch). + */ +#define ENET_QOS_MAC_RXIPV6_HEADER_ERROR_OCTETS_RXIPV6HDRERROCT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXIPV6_HEADER_ERROR_OCTETS_RXIPV6HDRERROCT_SHIFT)) & ENET_QOS_MAC_RXIPV6_HEADER_ERROR_OCTETS_RXIPV6HDRERROCT_MASK) +/*! @} */ + +/*! @name MAC_RXIPV6_NO_PAYLOAD_OCTETS - Bytes Received in IPv6 Datagrams with No Payload */ +/*! @{ */ + +#define ENET_QOS_MAC_RXIPV6_NO_PAYLOAD_OCTETS_RXIPV6NOPAYOCT_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_RXIPV6_NO_PAYLOAD_OCTETS_RXIPV6NOPAYOCT_SHIFT (0U) +/*! RXIPV6NOPAYOCT - RxIPv6 Payload Octets This field indicates the number of bytes received in IPv6 + * datagrams that did not have a TCP, UDP, or ICMP payload. + */ +#define ENET_QOS_MAC_RXIPV6_NO_PAYLOAD_OCTETS_RXIPV6NOPAYOCT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXIPV6_NO_PAYLOAD_OCTETS_RXIPV6NOPAYOCT_SHIFT)) & ENET_QOS_MAC_RXIPV6_NO_PAYLOAD_OCTETS_RXIPV6NOPAYOCT_MASK) +/*! @} */ + +/*! @name MAC_RXUDP_GOOD_OCTETS - Bytes Received in Good UDP Segment */ +/*! @{ */ + +#define ENET_QOS_MAC_RXUDP_GOOD_OCTETS_RXUDPGDOCT_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_RXUDP_GOOD_OCTETS_RXUDPGDOCT_SHIFT (0U) +/*! RXUDPGDOCT - RxUDP Good Octets This field indicates the number of bytes received in a good UDP segment. */ +#define ENET_QOS_MAC_RXUDP_GOOD_OCTETS_RXUDPGDOCT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXUDP_GOOD_OCTETS_RXUDPGDOCT_SHIFT)) & ENET_QOS_MAC_RXUDP_GOOD_OCTETS_RXUDPGDOCT_MASK) +/*! @} */ + +/*! @name MAC_RXUDP_ERROR_OCTETS - Bytes Received in UDP Segment with Checksum Errors */ +/*! @{ */ + +#define ENET_QOS_MAC_RXUDP_ERROR_OCTETS_RXUDPERROCT_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_RXUDP_ERROR_OCTETS_RXUDPERROCT_SHIFT (0U) +/*! RXUDPERROCT - RxUDP Error Octets This field indicates the number of bytes received in a UDP segment that had checksum errors. */ +#define ENET_QOS_MAC_RXUDP_ERROR_OCTETS_RXUDPERROCT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXUDP_ERROR_OCTETS_RXUDPERROCT_SHIFT)) & ENET_QOS_MAC_RXUDP_ERROR_OCTETS_RXUDPERROCT_MASK) +/*! @} */ + +/*! @name MAC_RXTCP_GOOD_OCTETS - Bytes Received in Good TCP Segment */ +/*! @{ */ + +#define ENET_QOS_MAC_RXTCP_GOOD_OCTETS_RXTCPGDOCT_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_RXTCP_GOOD_OCTETS_RXTCPGDOCT_SHIFT (0U) +/*! RXTCPGDOCT - RxTCP Good Octets This field indicates the number of bytes received in a good TCP segment. */ +#define ENET_QOS_MAC_RXTCP_GOOD_OCTETS_RXTCPGDOCT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXTCP_GOOD_OCTETS_RXTCPGDOCT_SHIFT)) & ENET_QOS_MAC_RXTCP_GOOD_OCTETS_RXTCPGDOCT_MASK) +/*! @} */ + +/*! @name MAC_RXTCP_ERROR_OCTETS - Bytes Received in TCP Segment with Checksum Errors */ +/*! @{ */ + +#define ENET_QOS_MAC_RXTCP_ERROR_OCTETS_RXTCPERROCT_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_RXTCP_ERROR_OCTETS_RXTCPERROCT_SHIFT (0U) +/*! RXTCPERROCT - RxTCP Error Octets This field indicates the number of bytes received in a TCP segment that had checksum errors. */ +#define ENET_QOS_MAC_RXTCP_ERROR_OCTETS_RXTCPERROCT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXTCP_ERROR_OCTETS_RXTCPERROCT_SHIFT)) & ENET_QOS_MAC_RXTCP_ERROR_OCTETS_RXTCPERROCT_MASK) +/*! @} */ + +/*! @name MAC_RXICMP_GOOD_OCTETS - Bytes Received in Good ICMP Segment */ +/*! @{ */ + +#define ENET_QOS_MAC_RXICMP_GOOD_OCTETS_RXICMPGDOCT_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_RXICMP_GOOD_OCTETS_RXICMPGDOCT_SHIFT (0U) +/*! RXICMPGDOCT - RxICMP Good Octets This field indicates the number of bytes received in a good ICMP segment. */ +#define ENET_QOS_MAC_RXICMP_GOOD_OCTETS_RXICMPGDOCT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXICMP_GOOD_OCTETS_RXICMPGDOCT_SHIFT)) & ENET_QOS_MAC_RXICMP_GOOD_OCTETS_RXICMPGDOCT_MASK) +/*! @} */ + +/*! @name MAC_RXICMP_ERROR_OCTETS - Bytes Received in ICMP Segment with Checksum Errors */ +/*! @{ */ + +#define ENET_QOS_MAC_RXICMP_ERROR_OCTETS_RXICMPERROCT_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_RXICMP_ERROR_OCTETS_RXICMPERROCT_SHIFT (0U) +/*! RXICMPERROCT - RxICMP Error Octets This field indicates the number of bytes received in a ICMP segment that had checksum errors. */ +#define ENET_QOS_MAC_RXICMP_ERROR_OCTETS_RXICMPERROCT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXICMP_ERROR_OCTETS_RXICMPERROCT_SHIFT)) & ENET_QOS_MAC_RXICMP_ERROR_OCTETS_RXICMPERROCT_MASK) +/*! @} */ + +/*! @name MAC_MMC_FPE_TX_INTERRUPT - MMC FPE Transmit Interrupt */ +/*! @{ */ + +#define ENET_QOS_MAC_MMC_FPE_TX_INTERRUPT_FCIS_MASK (0x1U) +#define ENET_QOS_MAC_MMC_FPE_TX_INTERRUPT_FCIS_SHIFT (0U) +/*! FCIS - MMC Tx FPE Fragment Counter Interrupt status This bit is set when the + * Tx_FPE_Fragment_Cntr counter reaches half of the maximum value or the maximum value. + * 0b0..MMC Tx FPE Fragment Counter Interrupt status not detected + * 0b1..MMC Tx FPE Fragment Counter Interrupt status detected + */ +#define ENET_QOS_MAC_MMC_FPE_TX_INTERRUPT_FCIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_FPE_TX_INTERRUPT_FCIS_SHIFT)) & ENET_QOS_MAC_MMC_FPE_TX_INTERRUPT_FCIS_MASK) + +#define ENET_QOS_MAC_MMC_FPE_TX_INTERRUPT_HRCIS_MASK (0x2U) +#define ENET_QOS_MAC_MMC_FPE_TX_INTERRUPT_HRCIS_SHIFT (1U) +/*! HRCIS - MMC Tx Hold Request Counter Interrupt Status This bit is set when the Tx_Hold_Req_Cntr + * counter reaches half of the maximum value or the maximum value. + * 0b0..MMC Tx Hold Request Counter Interrupt Status not detected + * 0b1..MMC Tx Hold Request Counter Interrupt Status detected + */ +#define ENET_QOS_MAC_MMC_FPE_TX_INTERRUPT_HRCIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_FPE_TX_INTERRUPT_HRCIS_SHIFT)) & ENET_QOS_MAC_MMC_FPE_TX_INTERRUPT_HRCIS_MASK) +/*! @} */ + +/*! @name MAC_MMC_FPE_TX_INTERRUPT_MASK - MMC FPE Transmit Mask Interrupt */ +/*! @{ */ + +#define ENET_QOS_MAC_MMC_FPE_TX_INTERRUPT_MASK_FCIM_MASK (0x1U) +#define ENET_QOS_MAC_MMC_FPE_TX_INTERRUPT_MASK_FCIM_SHIFT (0U) +/*! FCIM - MMC Transmit Fragment Counter Interrupt Mask Setting this bit masks the interrupt when + * the Tx_FPE_Fragment_Cntr counter reaches half of the maximum value or the maximum value. + * 0b0..MMC Transmit Fragment Counter Interrupt Mask is disabled + * 0b1..MMC Transmit Fragment Counter Interrupt Mask is enabled + */ +#define ENET_QOS_MAC_MMC_FPE_TX_INTERRUPT_MASK_FCIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_FPE_TX_INTERRUPT_MASK_FCIM_SHIFT)) & ENET_QOS_MAC_MMC_FPE_TX_INTERRUPT_MASK_FCIM_MASK) + +#define ENET_QOS_MAC_MMC_FPE_TX_INTERRUPT_MASK_HRCIM_MASK (0x2U) +#define ENET_QOS_MAC_MMC_FPE_TX_INTERRUPT_MASK_HRCIM_SHIFT (1U) +/*! HRCIM - MMC Transmit Hold Request Counter Interrupt Mask Setting this bit masks the interrupt + * when the Tx_Hold_Req_Cntr counter reaches half of the maximum value or the maximum value. + * 0b0..MMC Transmit Hold Request Counter Interrupt Mask is disabled + * 0b1..MMC Transmit Hold Request Counter Interrupt Mask is enabled + */ +#define ENET_QOS_MAC_MMC_FPE_TX_INTERRUPT_MASK_HRCIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_FPE_TX_INTERRUPT_MASK_HRCIM_SHIFT)) & ENET_QOS_MAC_MMC_FPE_TX_INTERRUPT_MASK_HRCIM_MASK) +/*! @} */ + +/*! @name MAC_MMC_TX_FPE_FRAGMENT_CNTR - MMC FPE Transmitted Fragment Counter */ +/*! @{ */ + +#define ENET_QOS_MAC_MMC_TX_FPE_FRAGMENT_CNTR_TXFFC_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_MMC_TX_FPE_FRAGMENT_CNTR_TXFFC_SHIFT (0U) +/*! TXFFC - Tx FPE Fragment counter This field indicates the number of additional mPackets that has + * been transmitted due to preemption Exists when any one of the RX/TX MMC counters are enabled + * during FPE Enabled configuration. + */ +#define ENET_QOS_MAC_MMC_TX_FPE_FRAGMENT_CNTR_TXFFC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_FPE_FRAGMENT_CNTR_TXFFC_SHIFT)) & ENET_QOS_MAC_MMC_TX_FPE_FRAGMENT_CNTR_TXFFC_MASK) +/*! @} */ + +/*! @name MAC_MMC_TX_HOLD_REQ_CNTR - MMC FPE Transmitted Hold Request Counter */ +/*! @{ */ + +#define ENET_QOS_MAC_MMC_TX_HOLD_REQ_CNTR_TXHRC_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_MMC_TX_HOLD_REQ_CNTR_TXHRC_SHIFT (0U) +/*! TXHRC - Tx Hold Request Counter This field indicates count of number of a hold request is given to MAC. */ +#define ENET_QOS_MAC_MMC_TX_HOLD_REQ_CNTR_TXHRC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_HOLD_REQ_CNTR_TXHRC_SHIFT)) & ENET_QOS_MAC_MMC_TX_HOLD_REQ_CNTR_TXHRC_MASK) +/*! @} */ + +/*! @name MAC_MMC_FPE_RX_INTERRUPT - MMC FPE Receive Interrupt */ +/*! @{ */ + +#define ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_PAECIS_MASK (0x1U) +#define ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_PAECIS_SHIFT (0U) +/*! PAECIS - MMC Rx Packet Assembly Error Counter Interrupt Status This bit is set when the + * Rx_Packet_Assemble_Err_Cntr counter reaches half of the maximum value or the maximum value. + * 0b0..MMC Rx Packet Assembly Error Counter Interrupt Status not detected + * 0b1..MMC Rx Packet Assembly Error Counter Interrupt Status detected + */ +#define ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_PAECIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_PAECIS_SHIFT)) & ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_PAECIS_MASK) + +#define ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_PSECIS_MASK (0x2U) +#define ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_PSECIS_SHIFT (1U) +/*! PSECIS - MMC Rx Packet SMD Error Counter Interrupt Status This bit is set when the + * Rx_Packet_SMD_Err_Cntr counter reaches half of the maximum value or the maximum value. + * 0b0..MMC Rx Packet SMD Error Counter Interrupt Status not detected + * 0b1..MMC Rx Packet SMD Error Counter Interrupt Status detected + */ +#define ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_PSECIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_PSECIS_SHIFT)) & ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_PSECIS_MASK) + +#define ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_PAOCIS_MASK (0x4U) +#define ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_PAOCIS_SHIFT (2U) +/*! PAOCIS - MMC Rx Packet Assembly OK Counter Interrupt Status This bit is set when the + * Rx_Packet_Assemble_Ok_Cntr counter reaches half of the maximum value or the maximum value. + * 0b0..MMC Rx Packet Assembly OK Counter Interrupt Status not detected + * 0b1..MMC Rx Packet Assembly OK Counter Interrupt Status detected + */ +#define ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_PAOCIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_PAOCIS_SHIFT)) & ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_PAOCIS_MASK) + +#define ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_FCIS_MASK (0x8U) +#define ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_FCIS_SHIFT (3U) +/*! FCIS - MMC Rx FPE Fragment Counter Interrupt Status This bit is set when the + * Rx_FPE_Fragment_Cntr counter reaches half of the maximum value or the maximum value. + * 0b0..MMC Rx FPE Fragment Counter Interrupt Status not detected + * 0b1..MMC Rx FPE Fragment Counter Interrupt Status detected + */ +#define ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_FCIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_FCIS_SHIFT)) & ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_FCIS_MASK) +/*! @} */ + +/*! @name MAC_MMC_FPE_RX_INTERRUPT_MASK - MMC FPE Receive Interrupt Mask */ +/*! @{ */ + +#define ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_MASK_PAECIM_MASK (0x1U) +#define ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_MASK_PAECIM_SHIFT (0U) +/*! PAECIM - MMC Rx Packet Assembly Error Counter Interrupt Mask Setting this bit masks the + * interrupt when the R Rx_Packet_Assemble_Err_Cntr counter reaches half of the maximum value or the + * maximum value. + * 0b0..MMC Rx Packet Assembly Error Counter Interrupt Mask is disabled + * 0b1..MMC Rx Packet Assembly Error Counter Interrupt Mask is enabled + */ +#define ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_MASK_PAECIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_MASK_PAECIM_SHIFT)) & ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_MASK_PAECIM_MASK) + +#define ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_MASK_PSECIM_MASK (0x2U) +#define ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_MASK_PSECIM_SHIFT (1U) +/*! PSECIM - MMC Rx Packet SMD Error Counter Interrupt Mask Setting this bit masks the interrupt + * when the R Rx_Packet_SMD_Err_Cntr counter reaches half of the maximum value or the maximum value. + * 0b0..MMC Rx Packet SMD Error Counter Interrupt Mask is disabled + * 0b1..MMC Rx Packet SMD Error Counter Interrupt Mask is enabled + */ +#define ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_MASK_PSECIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_MASK_PSECIM_SHIFT)) & ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_MASK_PSECIM_MASK) + +#define ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_MASK_PAOCIM_MASK (0x4U) +#define ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_MASK_PAOCIM_SHIFT (2U) +/*! PAOCIM - MMC Rx Packet Assembly OK Counter Interrupt Mask Setting this bit masks the interrupt + * when the Rx_Packet_Assemble_Ok_Cntr counter reaches half of the maximum value or the maximum + * value. + * 0b0..MMC Rx Packet Assembly OK Counter Interrupt Mask is disabled + * 0b1..MMC Rx Packet Assembly OK Counter Interrupt Mask is enabled + */ +#define ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_MASK_PAOCIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_MASK_PAOCIM_SHIFT)) & ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_MASK_PAOCIM_MASK) + +#define ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_MASK_FCIM_MASK (0x8U) +#define ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_MASK_FCIM_SHIFT (3U) +/*! FCIM - MMC Rx FPE Fragment Counter Interrupt Mask Setting this bit masks the interrupt when the + * Tx_FPE_Fragment_Cntr counter reaches half of the maximum value or the maximum value. + * 0b0..MMC Rx FPE Fragment Counter Interrupt Mask is disabled + * 0b1..MMC Rx FPE Fragment Counter Interrupt Mask is enabled + */ +#define ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_MASK_FCIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_MASK_FCIM_SHIFT)) & ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_MASK_FCIM_MASK) +/*! @} */ + +/*! @name MAC_MMC_RX_PACKET_ASSEMBLY_ERR_CNTR - MMC Receive Packet Reassembly Error Counter */ +/*! @{ */ + +#define ENET_QOS_MAC_MMC_RX_PACKET_ASSEMBLY_ERR_CNTR_PAEC_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_MMC_RX_PACKET_ASSEMBLY_ERR_CNTR_PAEC_SHIFT (0U) +/*! PAEC - Rx Packet Assembly Error Counter This field indicates the number of MAC frames with + * reassembly errors on the Receiver, due to mismatch in the Fragment Count value. + */ +#define ENET_QOS_MAC_MMC_RX_PACKET_ASSEMBLY_ERR_CNTR_PAEC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_PACKET_ASSEMBLY_ERR_CNTR_PAEC_SHIFT)) & ENET_QOS_MAC_MMC_RX_PACKET_ASSEMBLY_ERR_CNTR_PAEC_MASK) +/*! @} */ + +/*! @name MAC_MMC_RX_PACKET_SMD_ERR_CNTR - MMC Receive Packet SMD Error Counter */ +/*! @{ */ + +#define ENET_QOS_MAC_MMC_RX_PACKET_SMD_ERR_CNTR_PSEC_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_MMC_RX_PACKET_SMD_ERR_CNTR_PSEC_SHIFT (0U) +/*! PSEC - Rx Packet SMD Error Counter This field indicates the number of MAC frames rejected due to + * unknown SMD value and MAC frame fragments rejected due to arriving with an SMD-C when there + * was no preceding preempted frame. + */ +#define ENET_QOS_MAC_MMC_RX_PACKET_SMD_ERR_CNTR_PSEC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_PACKET_SMD_ERR_CNTR_PSEC_SHIFT)) & ENET_QOS_MAC_MMC_RX_PACKET_SMD_ERR_CNTR_PSEC_MASK) +/*! @} */ + +/*! @name MAC_MMC_RX_PACKET_ASSEMBLY_OK_CNTR - MMC Receive Packet Successful Reassembly Counter */ +/*! @{ */ + +#define ENET_QOS_MAC_MMC_RX_PACKET_ASSEMBLY_OK_CNTR_PAOC_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_MMC_RX_PACKET_ASSEMBLY_OK_CNTR_PAOC_SHIFT (0U) +/*! PAOC - Rx Packet Assembly OK Counter This field indicates the number of MAC frames that were + * successfully reassembled and delivered to MAC. + */ +#define ENET_QOS_MAC_MMC_RX_PACKET_ASSEMBLY_OK_CNTR_PAOC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_PACKET_ASSEMBLY_OK_CNTR_PAOC_SHIFT)) & ENET_QOS_MAC_MMC_RX_PACKET_ASSEMBLY_OK_CNTR_PAOC_MASK) +/*! @} */ + +/*! @name MAC_MMC_RX_FPE_FRAGMENT_CNTR - MMC FPE Received Fragment Counter */ +/*! @{ */ + +#define ENET_QOS_MAC_MMC_RX_FPE_FRAGMENT_CNTR_FFC_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_MMC_RX_FPE_FRAGMENT_CNTR_FFC_SHIFT (0U) +/*! FFC - Rx FPE Fragment Counter This field indicates the number of additional mPackets received + * due to preemption Exists when at least one of the RX/TX MMC counters are enabled during FPE + * Enabled configuration. + */ +#define ENET_QOS_MAC_MMC_RX_FPE_FRAGMENT_CNTR_FFC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_FPE_FRAGMENT_CNTR_FFC_SHIFT)) & ENET_QOS_MAC_MMC_RX_FPE_FRAGMENT_CNTR_FFC_MASK) +/*! @} */ + +/*! @name MAC_L3_L4_CONTROL0 - Layer 3 and Layer 4 Control of Filter 0 */ +/*! @{ */ + +#define ENET_QOS_MAC_L3_L4_CONTROL0_L3PEN0_MASK (0x1U) +#define ENET_QOS_MAC_L3_L4_CONTROL0_L3PEN0_SHIFT (0U) +/*! L3PEN0 - Layer 3 Protocol Enable When this bit is set, the Layer 3 IP Source or Destination + * Address matching is enabled for IPv6 packets. + * 0b0..Layer 3 Protocol is disabled + * 0b1..Layer 3 Protocol is enabled + */ +#define ENET_QOS_MAC_L3_L4_CONTROL0_L3PEN0(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL0_L3PEN0_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL0_L3PEN0_MASK) + +#define ENET_QOS_MAC_L3_L4_CONTROL0_L3SAM0_MASK (0x4U) +#define ENET_QOS_MAC_L3_L4_CONTROL0_L3SAM0_SHIFT (2U) +/*! L3SAM0 - Layer 3 IP SA Match Enable When this bit is set, the Layer 3 IP Source Address field is enabled for matching. + * 0b0..Layer 3 IP SA Match is disabled + * 0b1..Layer 3 IP SA Match is enabled + */ +#define ENET_QOS_MAC_L3_L4_CONTROL0_L3SAM0(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL0_L3SAM0_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL0_L3SAM0_MASK) + +#define ENET_QOS_MAC_L3_L4_CONTROL0_L3SAIM0_MASK (0x8U) +#define ENET_QOS_MAC_L3_L4_CONTROL0_L3SAIM0_SHIFT (3U) +/*! L3SAIM0 - Layer 3 IP SA Inverse Match Enable When this bit is set, the Layer 3 IP Source Address + * field is enabled for inverse matching. + * 0b0..Layer 3 IP SA Inverse Match is disabled + * 0b1..Layer 3 IP SA Inverse Match is enabled + */ +#define ENET_QOS_MAC_L3_L4_CONTROL0_L3SAIM0(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL0_L3SAIM0_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL0_L3SAIM0_MASK) + +#define ENET_QOS_MAC_L3_L4_CONTROL0_L3DAM0_MASK (0x10U) +#define ENET_QOS_MAC_L3_L4_CONTROL0_L3DAM0_SHIFT (4U) +/*! L3DAM0 - Layer 3 IP DA Match Enable When this bit is set, the Layer 3 IP Destination Address field is enabled for matching. + * 0b0..Layer 3 IP DA Match is disabled + * 0b1..Layer 3 IP DA Match is enabled + */ +#define ENET_QOS_MAC_L3_L4_CONTROL0_L3DAM0(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL0_L3DAM0_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL0_L3DAM0_MASK) + +#define ENET_QOS_MAC_L3_L4_CONTROL0_L3DAIM0_MASK (0x20U) +#define ENET_QOS_MAC_L3_L4_CONTROL0_L3DAIM0_SHIFT (5U) +/*! L3DAIM0 - Layer 3 IP DA Inverse Match Enable When this bit is set, the Layer 3 IP Destination + * Address field is enabled for inverse matching. + * 0b0..Layer 3 IP DA Inverse Match is disabled + * 0b1..Layer 3 IP DA Inverse Match is enabled + */ +#define ENET_QOS_MAC_L3_L4_CONTROL0_L3DAIM0(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL0_L3DAIM0_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL0_L3DAIM0_MASK) + +#define ENET_QOS_MAC_L3_L4_CONTROL0_L3HSBM0_MASK (0x7C0U) +#define ENET_QOS_MAC_L3_L4_CONTROL0_L3HSBM0_SHIFT (6U) +/*! L3HSBM0 - Layer 3 IP SA Higher Bits Match IPv4 Packets: This field contains the number of lower + * bits of IP Source Address that are masked for matching in the IPv4 packets. + */ +#define ENET_QOS_MAC_L3_L4_CONTROL0_L3HSBM0(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL0_L3HSBM0_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL0_L3HSBM0_MASK) + +#define ENET_QOS_MAC_L3_L4_CONTROL0_L3HDBM0_MASK (0xF800U) +#define ENET_QOS_MAC_L3_L4_CONTROL0_L3HDBM0_SHIFT (11U) +/*! L3HDBM0 - Layer 3 IP DA Higher Bits Match IPv4 Packets: This field contains the number of higher + * bits of IP Destination Address that are matched in the IPv4 packets. + */ +#define ENET_QOS_MAC_L3_L4_CONTROL0_L3HDBM0(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL0_L3HDBM0_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL0_L3HDBM0_MASK) + +#define ENET_QOS_MAC_L3_L4_CONTROL0_L4PEN0_MASK (0x10000U) +#define ENET_QOS_MAC_L3_L4_CONTROL0_L4PEN0_SHIFT (16U) +/*! L4PEN0 - Layer 4 Protocol Enable When this bit is set, the Source and Destination Port number + * fields of UDP packets are used for matching. + * 0b0..Layer 4 Protocol is disabled + * 0b1..Layer 4 Protocol is enabled + */ +#define ENET_QOS_MAC_L3_L4_CONTROL0_L4PEN0(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL0_L4PEN0_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL0_L4PEN0_MASK) + +#define ENET_QOS_MAC_L3_L4_CONTROL0_L4SPM0_MASK (0x40000U) +#define ENET_QOS_MAC_L3_L4_CONTROL0_L4SPM0_SHIFT (18U) +/*! L4SPM0 - Layer 4 Source Port Match Enable When this bit is set, the Layer 4 Source Port number field is enabled for matching. + * 0b0..Layer 4 Source Port Match is disabled + * 0b1..Layer 4 Source Port Match is enabled + */ +#define ENET_QOS_MAC_L3_L4_CONTROL0_L4SPM0(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL0_L4SPM0_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL0_L4SPM0_MASK) + +#define ENET_QOS_MAC_L3_L4_CONTROL0_L4SPIM0_MASK (0x80000U) +#define ENET_QOS_MAC_L3_L4_CONTROL0_L4SPIM0_SHIFT (19U) +/*! L4SPIM0 - Layer 4 Source Port Inverse Match Enable When this bit is set, the Layer 4 Source Port + * number field is enabled for inverse matching. + * 0b0..Layer 4 Source Port Inverse Match is disabled + * 0b1..Layer 4 Source Port Inverse Match is enabled + */ +#define ENET_QOS_MAC_L3_L4_CONTROL0_L4SPIM0(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL0_L4SPIM0_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL0_L4SPIM0_MASK) + +#define ENET_QOS_MAC_L3_L4_CONTROL0_L4DPM0_MASK (0x100000U) +#define ENET_QOS_MAC_L3_L4_CONTROL0_L4DPM0_SHIFT (20U) +/*! L4DPM0 - Layer 4 Destination Port Match Enable When this bit is set, the Layer 4 Destination + * Port number field is enabled for matching. + * 0b0..Layer 4 Destination Port Match is disabled + * 0b1..Layer 4 Destination Port Match is enabled + */ +#define ENET_QOS_MAC_L3_L4_CONTROL0_L4DPM0(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL0_L4DPM0_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL0_L4DPM0_MASK) + +#define ENET_QOS_MAC_L3_L4_CONTROL0_L4DPIM0_MASK (0x200000U) +#define ENET_QOS_MAC_L3_L4_CONTROL0_L4DPIM0_SHIFT (21U) +/*! L4DPIM0 - Layer 4 Destination Port Inverse Match Enable When this bit is set, the Layer 4 + * Destination Port number field is enabled for inverse matching. + * 0b0..Layer 4 Destination Port Inverse Match is disabled + * 0b1..Layer 4 Destination Port Inverse Match is enabled + */ +#define ENET_QOS_MAC_L3_L4_CONTROL0_L4DPIM0(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL0_L4DPIM0_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL0_L4DPIM0_MASK) + +#define ENET_QOS_MAC_L3_L4_CONTROL0_DMCHN0_MASK (0x7000000U) +#define ENET_QOS_MAC_L3_L4_CONTROL0_DMCHN0_SHIFT (24U) +/*! DMCHN0 - DMA Channel Number When DMCHEN is set high, this field selects the DMA Channel number + * to which the packet passed by this filter is routed. + */ +#define ENET_QOS_MAC_L3_L4_CONTROL0_DMCHN0(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL0_DMCHN0_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL0_DMCHN0_MASK) + +#define ENET_QOS_MAC_L3_L4_CONTROL0_DMCHEN0_MASK (0x10000000U) +#define ENET_QOS_MAC_L3_L4_CONTROL0_DMCHEN0_SHIFT (28U) +/*! DMCHEN0 - DMA Channel Select Enable When set, this bit enables the selection of the DMA channel + * number for the packet that is passed by this L3_L4 filter. + * 0b0..DMA Channel Select is disabled + * 0b1..DMA Channel Select is enabled + */ +#define ENET_QOS_MAC_L3_L4_CONTROL0_DMCHEN0(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL0_DMCHEN0_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL0_DMCHEN0_MASK) +/*! @} */ + +/*! @name MAC_LAYER4_ADDRESS0 - Layer 4 Address 0 */ +/*! @{ */ + +#define ENET_QOS_MAC_LAYER4_ADDRESS0_L4SP0_MASK (0xFFFFU) +#define ENET_QOS_MAC_LAYER4_ADDRESS0_L4SP0_SHIFT (0U) +/*! L4SP0 - Layer 4 Source Port Number Field When the L4PEN0 bit is reset and the L4SPM0 bit is set + * in the MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with the TCP + * Source Port Number field in the IPv4 or IPv6 packets. + */ +#define ENET_QOS_MAC_LAYER4_ADDRESS0_L4SP0(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER4_ADDRESS0_L4SP0_SHIFT)) & ENET_QOS_MAC_LAYER4_ADDRESS0_L4SP0_MASK) + +#define ENET_QOS_MAC_LAYER4_ADDRESS0_L4DP0_MASK (0xFFFF0000U) +#define ENET_QOS_MAC_LAYER4_ADDRESS0_L4DP0_SHIFT (16U) +/*! L4DP0 - Layer 4 Destination Port Number Field When the L4PEN0 bit is reset and the L4DPM0 bit is + * set in the MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with the + * TCP Destination Port Number field in the IPv4 or IPv6 packets. + */ +#define ENET_QOS_MAC_LAYER4_ADDRESS0_L4DP0(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER4_ADDRESS0_L4DP0_SHIFT)) & ENET_QOS_MAC_LAYER4_ADDRESS0_L4DP0_MASK) +/*! @} */ + +/*! @name MAC_LAYER3_ADDR0_REG0 - Layer 3 Address 0 Register 0 */ +/*! @{ */ + +#define ENET_QOS_MAC_LAYER3_ADDR0_REG0_L3A00_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_LAYER3_ADDR0_REG0_L3A00_SHIFT (0U) +/*! L3A00 - Layer 3 Address 0 Field When the L3PEN0 and L3SAM0 bits are set in the + * MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[31:0] of the IP Source + * Address field in the IPv6 packets. + */ +#define ENET_QOS_MAC_LAYER3_ADDR0_REG0_L3A00(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER3_ADDR0_REG0_L3A00_SHIFT)) & ENET_QOS_MAC_LAYER3_ADDR0_REG0_L3A00_MASK) +/*! @} */ + +/*! @name MAC_LAYER3_ADDR1_REG0 - Layer 3 Address 1 Register 0 */ +/*! @{ */ + +#define ENET_QOS_MAC_LAYER3_ADDR1_REG0_L3A10_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_LAYER3_ADDR1_REG0_L3A10_SHIFT (0U) +/*! L3A10 - Layer 3 Address 1 Field When the L3PEN0 and L3SAM0 bits are set in the + * MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[63:32] of the IP Source + * Address field in the IPv6 packets. + */ +#define ENET_QOS_MAC_LAYER3_ADDR1_REG0_L3A10(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER3_ADDR1_REG0_L3A10_SHIFT)) & ENET_QOS_MAC_LAYER3_ADDR1_REG0_L3A10_MASK) +/*! @} */ + +/*! @name MAC_LAYER3_ADDR2_REG0 - Layer 3 Address 2 Register 0 */ +/*! @{ */ + +#define ENET_QOS_MAC_LAYER3_ADDR2_REG0_L3A20_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_LAYER3_ADDR2_REG0_L3A20_SHIFT (0U) +/*! L3A20 - Layer 3 Address 2 Field When the L3PEN0 and L3SAM0 bits are set in the + * MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[95:64] of the IP Source + * Address field in the IPv6 packets. + */ +#define ENET_QOS_MAC_LAYER3_ADDR2_REG0_L3A20(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER3_ADDR2_REG0_L3A20_SHIFT)) & ENET_QOS_MAC_LAYER3_ADDR2_REG0_L3A20_MASK) +/*! @} */ + +/*! @name MAC_LAYER3_ADDR3_REG0 - Layer 3 Address 3 Register 0 */ +/*! @{ */ + +#define ENET_QOS_MAC_LAYER3_ADDR3_REG0_L3A30_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_LAYER3_ADDR3_REG0_L3A30_SHIFT (0U) +/*! L3A30 - Layer 3 Address 3 Field When the L3PEN0 and L3SAM0 bits are set in the + * MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[127:96] of the IP Source + * Address field in the IPv6 packets. + */ +#define ENET_QOS_MAC_LAYER3_ADDR3_REG0_L3A30(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER3_ADDR3_REG0_L3A30_SHIFT)) & ENET_QOS_MAC_LAYER3_ADDR3_REG0_L3A30_MASK) +/*! @} */ + +/*! @name MAC_L3_L4_CONTROL1 - Layer 3 and Layer 4 Control of Filter 1 */ +/*! @{ */ + +#define ENET_QOS_MAC_L3_L4_CONTROL1_L3PEN1_MASK (0x1U) +#define ENET_QOS_MAC_L3_L4_CONTROL1_L3PEN1_SHIFT (0U) +/*! L3PEN1 - Layer 3 Protocol Enable When this bit is set, the Layer 3 IP Source or Destination + * Address matching is enabled for IPv6 packets. + * 0b0..Layer 3 Protocol is disabled + * 0b1..Layer 3 Protocol is enabled + */ +#define ENET_QOS_MAC_L3_L4_CONTROL1_L3PEN1(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL1_L3PEN1_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL1_L3PEN1_MASK) + +#define ENET_QOS_MAC_L3_L4_CONTROL1_L3SAM1_MASK (0x4U) +#define ENET_QOS_MAC_L3_L4_CONTROL1_L3SAM1_SHIFT (2U) +/*! L3SAM1 - Layer 3 IP SA Match Enable When this bit is set, the Layer 3 IP Source Address field is enabled for matching. + * 0b0..Layer 3 IP SA Match is disabled + * 0b1..Layer 3 IP SA Match is enabled + */ +#define ENET_QOS_MAC_L3_L4_CONTROL1_L3SAM1(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL1_L3SAM1_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL1_L3SAM1_MASK) + +#define ENET_QOS_MAC_L3_L4_CONTROL1_L3SAIM1_MASK (0x8U) +#define ENET_QOS_MAC_L3_L4_CONTROL1_L3SAIM1_SHIFT (3U) +/*! L3SAIM1 - Layer 3 IP SA Inverse Match Enable When this bit is set, the Layer 3 IP Source Address + * field is enabled for inverse matching. + * 0b0..Layer 3 IP SA Inverse Match is disabled + * 0b1..Layer 3 IP SA Inverse Match is enabled + */ +#define ENET_QOS_MAC_L3_L4_CONTROL1_L3SAIM1(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL1_L3SAIM1_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL1_L3SAIM1_MASK) + +#define ENET_QOS_MAC_L3_L4_CONTROL1_L3DAM1_MASK (0x10U) +#define ENET_QOS_MAC_L3_L4_CONTROL1_L3DAM1_SHIFT (4U) +/*! L3DAM1 - Layer 3 IP DA Match Enable When this bit is set, the Layer 3 IP Destination Address field is enabled for matching. + * 0b0..Layer 3 IP DA Match is disabled + * 0b1..Layer 3 IP DA Match is enabled + */ +#define ENET_QOS_MAC_L3_L4_CONTROL1_L3DAM1(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL1_L3DAM1_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL1_L3DAM1_MASK) + +#define ENET_QOS_MAC_L3_L4_CONTROL1_L3DAIM1_MASK (0x20U) +#define ENET_QOS_MAC_L3_L4_CONTROL1_L3DAIM1_SHIFT (5U) +/*! L3DAIM1 - Layer 3 IP DA Inverse Match Enable When this bit is set, the Layer 3 IP Destination + * Address field is enabled for inverse matching. + * 0b0..Layer 3 IP DA Inverse Match is disabled + * 0b1..Layer 3 IP DA Inverse Match is enabled + */ +#define ENET_QOS_MAC_L3_L4_CONTROL1_L3DAIM1(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL1_L3DAIM1_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL1_L3DAIM1_MASK) + +#define ENET_QOS_MAC_L3_L4_CONTROL1_L3HSBM1_MASK (0x7C0U) +#define ENET_QOS_MAC_L3_L4_CONTROL1_L3HSBM1_SHIFT (6U) +/*! L3HSBM1 - Layer 3 IP SA Higher Bits Match IPv4 Packets: This field contains the number of lower + * bits of IP Source Address that are masked for matching in the IPv4 packets. + */ +#define ENET_QOS_MAC_L3_L4_CONTROL1_L3HSBM1(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL1_L3HSBM1_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL1_L3HSBM1_MASK) + +#define ENET_QOS_MAC_L3_L4_CONTROL1_L3HDBM1_MASK (0xF800U) +#define ENET_QOS_MAC_L3_L4_CONTROL1_L3HDBM1_SHIFT (11U) +/*! L3HDBM1 - Layer 3 IP DA Higher Bits Match IPv4 Packets: This field contains the number of higher + * bits of IP Destination Address that are matched in the IPv4 packets. + */ +#define ENET_QOS_MAC_L3_L4_CONTROL1_L3HDBM1(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL1_L3HDBM1_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL1_L3HDBM1_MASK) + +#define ENET_QOS_MAC_L3_L4_CONTROL1_L4PEN1_MASK (0x10000U) +#define ENET_QOS_MAC_L3_L4_CONTROL1_L4PEN1_SHIFT (16U) +/*! L4PEN1 - Layer 4 Protocol Enable When this bit is set, the Source and Destination Port number + * fields of UDP packets are used for matching. + * 0b0..Layer 4 Protocol is disabled + * 0b1..Layer 4 Protocol is enabled + */ +#define ENET_QOS_MAC_L3_L4_CONTROL1_L4PEN1(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL1_L4PEN1_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL1_L4PEN1_MASK) + +#define ENET_QOS_MAC_L3_L4_CONTROL1_L4SPM1_MASK (0x40000U) +#define ENET_QOS_MAC_L3_L4_CONTROL1_L4SPM1_SHIFT (18U) +/*! L4SPM1 - Layer 4 Source Port Match Enable When this bit is set, the Layer 4 Source Port number field is enabled for matching. + * 0b0..Layer 4 Source Port Match is disabled + * 0b1..Layer 4 Source Port Match is enabled + */ +#define ENET_QOS_MAC_L3_L4_CONTROL1_L4SPM1(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL1_L4SPM1_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL1_L4SPM1_MASK) + +#define ENET_QOS_MAC_L3_L4_CONTROL1_L4SPIM1_MASK (0x80000U) +#define ENET_QOS_MAC_L3_L4_CONTROL1_L4SPIM1_SHIFT (19U) +/*! L4SPIM1 - Layer 4 Source Port Inverse Match Enable When this bit is set, the Layer 4 Source Port + * number field is enabled for inverse matching. + * 0b0..Layer 4 Source Port Inverse Match is disabled + * 0b1..Layer 4 Source Port Inverse Match is enabled + */ +#define ENET_QOS_MAC_L3_L4_CONTROL1_L4SPIM1(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL1_L4SPIM1_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL1_L4SPIM1_MASK) + +#define ENET_QOS_MAC_L3_L4_CONTROL1_L4DPM1_MASK (0x100000U) +#define ENET_QOS_MAC_L3_L4_CONTROL1_L4DPM1_SHIFT (20U) +/*! L4DPM1 - Layer 4 Destination Port Match Enable When this bit is set, the Layer 4 Destination + * Port number field is enabled for matching. + * 0b0..Layer 4 Destination Port Match is disabled + * 0b1..Layer 4 Destination Port Match is enabled + */ +#define ENET_QOS_MAC_L3_L4_CONTROL1_L4DPM1(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL1_L4DPM1_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL1_L4DPM1_MASK) + +#define ENET_QOS_MAC_L3_L4_CONTROL1_L4DPIM1_MASK (0x200000U) +#define ENET_QOS_MAC_L3_L4_CONTROL1_L4DPIM1_SHIFT (21U) +/*! L4DPIM1 - Layer 4 Destination Port Inverse Match Enable When this bit is set, the Layer 4 + * Destination Port number field is enabled for inverse matching. + * 0b0..Layer 4 Destination Port Inverse Match is disabled + * 0b1..Layer 4 Destination Port Inverse Match is enabled + */ +#define ENET_QOS_MAC_L3_L4_CONTROL1_L4DPIM1(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL1_L4DPIM1_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL1_L4DPIM1_MASK) + +#define ENET_QOS_MAC_L3_L4_CONTROL1_DMCHN1_MASK (0x7000000U) +#define ENET_QOS_MAC_L3_L4_CONTROL1_DMCHN1_SHIFT (24U) +/*! DMCHN1 - DMA Channel Number When DMCHEN is set high, this field selects the DMA Channel number + * to which the packet passed by this filter is routed. + */ +#define ENET_QOS_MAC_L3_L4_CONTROL1_DMCHN1(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL1_DMCHN1_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL1_DMCHN1_MASK) + +#define ENET_QOS_MAC_L3_L4_CONTROL1_DMCHEN1_MASK (0x10000000U) +#define ENET_QOS_MAC_L3_L4_CONTROL1_DMCHEN1_SHIFT (28U) +/*! DMCHEN1 - DMA Channel Select Enable When set, this bit enables the selection of the DMA channel + * number for the packet that is passed by this L3_L4 filter. + * 0b0..DMA Channel Select is disabled + * 0b1..DMA Channel Select is enabled + */ +#define ENET_QOS_MAC_L3_L4_CONTROL1_DMCHEN1(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL1_DMCHEN1_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL1_DMCHEN1_MASK) +/*! @} */ + +/*! @name MAC_LAYER4_ADDRESS1 - Layer 4 Address 0 */ +/*! @{ */ + +#define ENET_QOS_MAC_LAYER4_ADDRESS1_L4SP1_MASK (0xFFFFU) +#define ENET_QOS_MAC_LAYER4_ADDRESS1_L4SP1_SHIFT (0U) +/*! L4SP1 - Layer 4 Source Port Number Field When the L4PEN1 bit is reset and the L4SPM0 bit is set + * in the MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with the TCP + * Source Port Number field in the IPv4 or IPv6 packets. + */ +#define ENET_QOS_MAC_LAYER4_ADDRESS1_L4SP1(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER4_ADDRESS1_L4SP1_SHIFT)) & ENET_QOS_MAC_LAYER4_ADDRESS1_L4SP1_MASK) + +#define ENET_QOS_MAC_LAYER4_ADDRESS1_L4DP1_MASK (0xFFFF0000U) +#define ENET_QOS_MAC_LAYER4_ADDRESS1_L4DP1_SHIFT (16U) +/*! L4DP1 - Layer 4 Destination Port Number Field When the L4PEN0 bit is reset and the L4DPM1 bit is + * set in the MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with the + * TCP Destination Port Number field in the IPv4 or IPv6 packets. + */ +#define ENET_QOS_MAC_LAYER4_ADDRESS1_L4DP1(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER4_ADDRESS1_L4DP1_SHIFT)) & ENET_QOS_MAC_LAYER4_ADDRESS1_L4DP1_MASK) +/*! @} */ + +/*! @name MAC_LAYER3_ADDR0_REG1 - Layer 3 Address 0 Register 1 */ +/*! @{ */ + +#define ENET_QOS_MAC_LAYER3_ADDR0_REG1_L3A01_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_LAYER3_ADDR0_REG1_L3A01_SHIFT (0U) +/*! L3A01 - Layer 3 Address 0 Field When the L3PEN0 and L3SAM0 bits are set in the + * MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[31:0] of the IP Source + * Address field in the IPv6 packets. + */ +#define ENET_QOS_MAC_LAYER3_ADDR0_REG1_L3A01(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER3_ADDR0_REG1_L3A01_SHIFT)) & ENET_QOS_MAC_LAYER3_ADDR0_REG1_L3A01_MASK) +/*! @} */ + +/*! @name MAC_LAYER3_ADDR1_REG1 - Layer 3 Address 1 Register 1 */ +/*! @{ */ + +#define ENET_QOS_MAC_LAYER3_ADDR1_REG1_L3A11_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_LAYER3_ADDR1_REG1_L3A11_SHIFT (0U) +/*! L3A11 - Layer 3 Address 1 Field When the L3PEN0 and L3SAM0 bits are set in the + * MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[63:32] of the IP Source + * Address field in the IPv6 packets. + */ +#define ENET_QOS_MAC_LAYER3_ADDR1_REG1_L3A11(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER3_ADDR1_REG1_L3A11_SHIFT)) & ENET_QOS_MAC_LAYER3_ADDR1_REG1_L3A11_MASK) +/*! @} */ + +/*! @name MAC_LAYER3_ADDR2_REG1 - Layer 3 Address 2 Register 1 */ +/*! @{ */ + +#define ENET_QOS_MAC_LAYER3_ADDR2_REG1_L3A21_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_LAYER3_ADDR2_REG1_L3A21_SHIFT (0U) +/*! L3A21 - Layer 3 Address 2 Field When the L3PEN0 and L3SAM0 bits are set in the + * MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[95:64] of the IP Source + * Address field in the IPv6 packets. + */ +#define ENET_QOS_MAC_LAYER3_ADDR2_REG1_L3A21(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER3_ADDR2_REG1_L3A21_SHIFT)) & ENET_QOS_MAC_LAYER3_ADDR2_REG1_L3A21_MASK) +/*! @} */ + +/*! @name MAC_LAYER3_ADDR3_REG1 - Layer 3 Address 3 Register 1 */ +/*! @{ */ + +#define ENET_QOS_MAC_LAYER3_ADDR3_REG1_L3A31_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_LAYER3_ADDR3_REG1_L3A31_SHIFT (0U) +/*! L3A31 - Layer 3 Address 3 Field When the L3PEN0 and L3SAM0 bits are set in the + * MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[127:96] of the IP Source + * Address field in the IPv6 packets. + */ +#define ENET_QOS_MAC_LAYER3_ADDR3_REG1_L3A31(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER3_ADDR3_REG1_L3A31_SHIFT)) & ENET_QOS_MAC_LAYER3_ADDR3_REG1_L3A31_MASK) +/*! @} */ + +/*! @name MAC_L3_L4_CONTROL2 - Layer 3 and Layer 4 Control of Filter 2 */ +/*! @{ */ + +#define ENET_QOS_MAC_L3_L4_CONTROL2_L3PEN2_MASK (0x1U) +#define ENET_QOS_MAC_L3_L4_CONTROL2_L3PEN2_SHIFT (0U) +/*! L3PEN2 - Layer 3 Protocol Enable When this bit is set, the Layer 3 IP Source or Destination + * Address matching is enabled for IPv6 packets. + * 0b0..Layer 3 Protocol is disabled + * 0b1..Layer 3 Protocol is enabled + */ +#define ENET_QOS_MAC_L3_L4_CONTROL2_L3PEN2(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL2_L3PEN2_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL2_L3PEN2_MASK) + +#define ENET_QOS_MAC_L3_L4_CONTROL2_L3SAM2_MASK (0x4U) +#define ENET_QOS_MAC_L3_L4_CONTROL2_L3SAM2_SHIFT (2U) +/*! L3SAM2 - Layer 3 IP SA Match Enable When this bit is set, the Layer 3 IP Source Address field is enabled for matching. + * 0b0..Layer 3 IP SA Match is disabled + * 0b1..Layer 3 IP SA Match is enabled + */ +#define ENET_QOS_MAC_L3_L4_CONTROL2_L3SAM2(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL2_L3SAM2_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL2_L3SAM2_MASK) + +#define ENET_QOS_MAC_L3_L4_CONTROL2_L3SAIM2_MASK (0x8U) +#define ENET_QOS_MAC_L3_L4_CONTROL2_L3SAIM2_SHIFT (3U) +/*! L3SAIM2 - Layer 3 IP SA Inverse Match Enable When this bit is set, the Layer 3 IP Source Address + * field is enabled for inverse matching. + * 0b0..Layer 3 IP SA Inverse Match is disabled + * 0b1..Layer 3 IP SA Inverse Match is enabled + */ +#define ENET_QOS_MAC_L3_L4_CONTROL2_L3SAIM2(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL2_L3SAIM2_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL2_L3SAIM2_MASK) + +#define ENET_QOS_MAC_L3_L4_CONTROL2_L3DAM2_MASK (0x10U) +#define ENET_QOS_MAC_L3_L4_CONTROL2_L3DAM2_SHIFT (4U) +/*! L3DAM2 - Layer 3 IP DA Match Enable When this bit is set, the Layer 3 IP Destination Address field is enabled for matching. + * 0b0..Layer 3 IP DA Match is disabled + * 0b1..Layer 3 IP DA Match is enabled + */ +#define ENET_QOS_MAC_L3_L4_CONTROL2_L3DAM2(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL2_L3DAM2_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL2_L3DAM2_MASK) + +#define ENET_QOS_MAC_L3_L4_CONTROL2_L3DAIM2_MASK (0x20U) +#define ENET_QOS_MAC_L3_L4_CONTROL2_L3DAIM2_SHIFT (5U) +/*! L3DAIM2 - Layer 3 IP DA Inverse Match Enable When this bit is set, the Layer 3 IP Destination + * Address field is enabled for inverse matching. + * 0b0..Layer 3 IP DA Inverse Match is disabled + * 0b1..Layer 3 IP DA Inverse Match is enabled + */ +#define ENET_QOS_MAC_L3_L4_CONTROL2_L3DAIM2(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL2_L3DAIM2_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL2_L3DAIM2_MASK) + +#define ENET_QOS_MAC_L3_L4_CONTROL2_L3HSBM2_MASK (0x7C0U) +#define ENET_QOS_MAC_L3_L4_CONTROL2_L3HSBM2_SHIFT (6U) +/*! L3HSBM2 - Layer 3 IP SA Higher Bits Match IPv4 Packets: This field contains the number of lower + * bits of IP Source Address that are masked for matching in the IPv4 packets. + */ +#define ENET_QOS_MAC_L3_L4_CONTROL2_L3HSBM2(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL2_L3HSBM2_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL2_L3HSBM2_MASK) + +#define ENET_QOS_MAC_L3_L4_CONTROL2_L3HDBM2_MASK (0xF800U) +#define ENET_QOS_MAC_L3_L4_CONTROL2_L3HDBM2_SHIFT (11U) +/*! L3HDBM2 - Layer 3 IP DA Higher Bits Match IPv4 Packets: This field contains the number of higher + * bits of IP Destination Address that are matched in the IPv4 packets. + */ +#define ENET_QOS_MAC_L3_L4_CONTROL2_L3HDBM2(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL2_L3HDBM2_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL2_L3HDBM2_MASK) + +#define ENET_QOS_MAC_L3_L4_CONTROL2_L4PEN2_MASK (0x10000U) +#define ENET_QOS_MAC_L3_L4_CONTROL2_L4PEN2_SHIFT (16U) +/*! L4PEN2 - Layer 4 Protocol Enable When this bit is set, the Source and Destination Port number + * fields of UDP packets are used for matching. + * 0b0..Layer 4 Protocol is disabled + * 0b1..Layer 4 Protocol is enabled + */ +#define ENET_QOS_MAC_L3_L4_CONTROL2_L4PEN2(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL2_L4PEN2_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL2_L4PEN2_MASK) + +#define ENET_QOS_MAC_L3_L4_CONTROL2_L4SPM2_MASK (0x40000U) +#define ENET_QOS_MAC_L3_L4_CONTROL2_L4SPM2_SHIFT (18U) +/*! L4SPM2 - Layer 4 Source Port Match Enable When this bit is set, the Layer 4 Source Port number field is enabled for matching. + * 0b0..Layer 4 Source Port Match is disabled + * 0b1..Layer 4 Source Port Match is enabled + */ +#define ENET_QOS_MAC_L3_L4_CONTROL2_L4SPM2(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL2_L4SPM2_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL2_L4SPM2_MASK) + +#define ENET_QOS_MAC_L3_L4_CONTROL2_L4SPIM2_MASK (0x80000U) +#define ENET_QOS_MAC_L3_L4_CONTROL2_L4SPIM2_SHIFT (19U) +/*! L4SPIM2 - Layer 4 Source Port Inverse Match Enable When this bit is set, the Layer 4 Source Port + * number field is enabled for inverse matching. + * 0b0..Layer 4 Source Port Inverse Match is disabled + * 0b1..Layer 4 Source Port Inverse Match is enabled + */ +#define ENET_QOS_MAC_L3_L4_CONTROL2_L4SPIM2(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL2_L4SPIM2_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL2_L4SPIM2_MASK) + +#define ENET_QOS_MAC_L3_L4_CONTROL2_L4DPM2_MASK (0x100000U) +#define ENET_QOS_MAC_L3_L4_CONTROL2_L4DPM2_SHIFT (20U) +/*! L4DPM2 - Layer 4 Destination Port Match Enable When this bit is set, the Layer 4 Destination + * Port number field is enabled for matching. + * 0b0..Layer 4 Destination Port Match is disabled + * 0b1..Layer 4 Destination Port Match is enabled + */ +#define ENET_QOS_MAC_L3_L4_CONTROL2_L4DPM2(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL2_L4DPM2_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL2_L4DPM2_MASK) + +#define ENET_QOS_MAC_L3_L4_CONTROL2_L4DPIM2_MASK (0x200000U) +#define ENET_QOS_MAC_L3_L4_CONTROL2_L4DPIM2_SHIFT (21U) +/*! L4DPIM2 - Layer 4 Destination Port Inverse Match Enable When this bit is set, the Layer 4 + * Destination Port number field is enabled for inverse matching. + * 0b0..Layer 4 Destination Port Inverse Match is disabled + * 0b1..Layer 4 Destination Port Inverse Match is enabled + */ +#define ENET_QOS_MAC_L3_L4_CONTROL2_L4DPIM2(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL2_L4DPIM2_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL2_L4DPIM2_MASK) + +#define ENET_QOS_MAC_L3_L4_CONTROL2_DMCHN2_MASK (0x7000000U) +#define ENET_QOS_MAC_L3_L4_CONTROL2_DMCHN2_SHIFT (24U) +/*! DMCHN2 - DMA Channel Number When DMCHEN is set high, this field selects the DMA Channel number + * to which the packet passed by this filter is routed. + */ +#define ENET_QOS_MAC_L3_L4_CONTROL2_DMCHN2(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL2_DMCHN2_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL2_DMCHN2_MASK) + +#define ENET_QOS_MAC_L3_L4_CONTROL2_DMCHEN2_MASK (0x10000000U) +#define ENET_QOS_MAC_L3_L4_CONTROL2_DMCHEN2_SHIFT (28U) +/*! DMCHEN2 - DMA Channel Select Enable When set, this bit enables the selection of the DMA channel + * number for the packet that is passed by this L3_L4 filter. + * 0b0..DMA Channel Select is disabled + * 0b1..DMA Channel Select is enabled + */ +#define ENET_QOS_MAC_L3_L4_CONTROL2_DMCHEN2(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL2_DMCHEN2_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL2_DMCHEN2_MASK) +/*! @} */ + +/*! @name MAC_LAYER4_ADDRESS2 - Layer 4 Address 2 */ +/*! @{ */ + +#define ENET_QOS_MAC_LAYER4_ADDRESS2_L4SP2_MASK (0xFFFFU) +#define ENET_QOS_MAC_LAYER4_ADDRESS2_L4SP2_SHIFT (0U) +/*! L4SP2 - Layer 4 Source Port Number Field When the L4PEN2 bit is reset and the L4SPM0 bit is set + * in the MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with the TCP + * Source Port Number field in the IPv4 or IPv6 packets. + */ +#define ENET_QOS_MAC_LAYER4_ADDRESS2_L4SP2(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER4_ADDRESS2_L4SP2_SHIFT)) & ENET_QOS_MAC_LAYER4_ADDRESS2_L4SP2_MASK) + +#define ENET_QOS_MAC_LAYER4_ADDRESS2_L4DP2_MASK (0xFFFF0000U) +#define ENET_QOS_MAC_LAYER4_ADDRESS2_L4DP2_SHIFT (16U) +/*! L4DP2 - Layer 4 Destination Port Number Field When the L4PEN2 bit is reset and the L4DPM2 bit is + * set in the MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with the + * TCP Destination Port Number field in the IPv4 or IPv6 packets. + */ +#define ENET_QOS_MAC_LAYER4_ADDRESS2_L4DP2(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER4_ADDRESS2_L4DP2_SHIFT)) & ENET_QOS_MAC_LAYER4_ADDRESS2_L4DP2_MASK) +/*! @} */ + +/*! @name MAC_LAYER3_ADDR0_REG2 - Layer 3 Address 0 Register 2 */ +/*! @{ */ + +#define ENET_QOS_MAC_LAYER3_ADDR0_REG2_L3A02_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_LAYER3_ADDR0_REG2_L3A02_SHIFT (0U) +/*! L3A02 - Layer 3 Address 0 Field When the L3PEN0 and L3SAM0 bits are set in the + * MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[31:0] of the IP Source + * Address field in the IPv6 packets. + */ +#define ENET_QOS_MAC_LAYER3_ADDR0_REG2_L3A02(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER3_ADDR0_REG2_L3A02_SHIFT)) & ENET_QOS_MAC_LAYER3_ADDR0_REG2_L3A02_MASK) +/*! @} */ + +/*! @name MAC_LAYER3_ADDR1_REG2 - Layer 3 Address 0 Register 2 */ +/*! @{ */ + +#define ENET_QOS_MAC_LAYER3_ADDR1_REG2_L3A12_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_LAYER3_ADDR1_REG2_L3A12_SHIFT (0U) +/*! L3A12 - Layer 3 Address 1 Field When the L3PEN0 and L3SAM0 bits are set in the + * MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[63:32] of the IP Source + * Address field in the IPv6 packets. + */ +#define ENET_QOS_MAC_LAYER3_ADDR1_REG2_L3A12(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER3_ADDR1_REG2_L3A12_SHIFT)) & ENET_QOS_MAC_LAYER3_ADDR1_REG2_L3A12_MASK) +/*! @} */ + +/*! @name MAC_LAYER3_ADDR2_REG2 - Layer 3 Address 2 Register 2 */ +/*! @{ */ + +#define ENET_QOS_MAC_LAYER3_ADDR2_REG2_L3A22_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_LAYER3_ADDR2_REG2_L3A22_SHIFT (0U) +/*! L3A22 - Layer 3 Address 2 Field When the L3PEN0 and L3SAM0 bits are set in the + * MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[95:64] of the IP Source + * Address field in the IPv6 packets. + */ +#define ENET_QOS_MAC_LAYER3_ADDR2_REG2_L3A22(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER3_ADDR2_REG2_L3A22_SHIFT)) & ENET_QOS_MAC_LAYER3_ADDR2_REG2_L3A22_MASK) +/*! @} */ + +/*! @name MAC_LAYER3_ADDR3_REG2 - Layer 3 Address 3 Register 2 */ +/*! @{ */ + +#define ENET_QOS_MAC_LAYER3_ADDR3_REG2_L3A32_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_LAYER3_ADDR3_REG2_L3A32_SHIFT (0U) +/*! L3A32 - Layer 3 Address 3 Field When the L3PEN0 and L3SAM0 bits are set in the + * MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[127:96] of the IP Source + * Address field in the IPv6 packets. + */ +#define ENET_QOS_MAC_LAYER3_ADDR3_REG2_L3A32(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER3_ADDR3_REG2_L3A32_SHIFT)) & ENET_QOS_MAC_LAYER3_ADDR3_REG2_L3A32_MASK) +/*! @} */ + +/*! @name MAC_L3_L4_CONTROL3 - Layer 3 and Layer 4 Control of Filter 3 */ +/*! @{ */ + +#define ENET_QOS_MAC_L3_L4_CONTROL3_L3PEN3_MASK (0x1U) +#define ENET_QOS_MAC_L3_L4_CONTROL3_L3PEN3_SHIFT (0U) +/*! L3PEN3 - Layer 3 Protocol Enable When this bit is set, the Layer 3 IP Source or Destination + * Address matching is enabled for IPv6 packets. + * 0b0..Layer 3 Protocol is disabled + * 0b1..Layer 3 Protocol is enabled + */ +#define ENET_QOS_MAC_L3_L4_CONTROL3_L3PEN3(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL3_L3PEN3_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL3_L3PEN3_MASK) + +#define ENET_QOS_MAC_L3_L4_CONTROL3_L3SAM3_MASK (0x4U) +#define ENET_QOS_MAC_L3_L4_CONTROL3_L3SAM3_SHIFT (2U) +/*! L3SAM3 - Layer 3 IP SA Match Enable When this bit is set, the Layer 3 IP Source Address field is enabled for matching. + * 0b0..Layer 3 IP SA Match is disabled + * 0b1..Layer 3 IP SA Match is enabled + */ +#define ENET_QOS_MAC_L3_L4_CONTROL3_L3SAM3(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL3_L3SAM3_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL3_L3SAM3_MASK) + +#define ENET_QOS_MAC_L3_L4_CONTROL3_L3SAIM3_MASK (0x8U) +#define ENET_QOS_MAC_L3_L4_CONTROL3_L3SAIM3_SHIFT (3U) +/*! L3SAIM3 - Layer 3 IP SA Inverse Match Enable When this bit is set, the Layer 3 IP Source Address + * field is enabled for inverse matching. + * 0b0..Layer 3 IP SA Inverse Match is disabled + * 0b1..Layer 3 IP SA Inverse Match is enabled + */ +#define ENET_QOS_MAC_L3_L4_CONTROL3_L3SAIM3(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL3_L3SAIM3_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL3_L3SAIM3_MASK) + +#define ENET_QOS_MAC_L3_L4_CONTROL3_L3DAM3_MASK (0x10U) +#define ENET_QOS_MAC_L3_L4_CONTROL3_L3DAM3_SHIFT (4U) +/*! L3DAM3 - Layer 3 IP DA Match Enable When this bit is set, the Layer 3 IP Destination Address field is enabled for matching. + * 0b0..Layer 3 IP DA Match is disabled + * 0b1..Layer 3 IP DA Match is enabled + */ +#define ENET_QOS_MAC_L3_L4_CONTROL3_L3DAM3(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL3_L3DAM3_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL3_L3DAM3_MASK) + +#define ENET_QOS_MAC_L3_L4_CONTROL3_L3DAIM3_MASK (0x20U) +#define ENET_QOS_MAC_L3_L4_CONTROL3_L3DAIM3_SHIFT (5U) +/*! L3DAIM3 - Layer 3 IP DA Inverse Match Enable When this bit is set, the Layer 3 IP Destination + * Address field is enabled for inverse matching. + * 0b0..Layer 3 IP DA Inverse Match is disabled + * 0b1..Layer 3 IP DA Inverse Match is enabled + */ +#define ENET_QOS_MAC_L3_L4_CONTROL3_L3DAIM3(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL3_L3DAIM3_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL3_L3DAIM3_MASK) + +#define ENET_QOS_MAC_L3_L4_CONTROL3_L3HSBM3_MASK (0x7C0U) +#define ENET_QOS_MAC_L3_L4_CONTROL3_L3HSBM3_SHIFT (6U) +/*! L3HSBM3 - Layer 3 IP SA Higher Bits Match IPv4 Packets: This field contains the number of lower + * bits of IP Source Address that are masked for matching in the IPv4 packets. + */ +#define ENET_QOS_MAC_L3_L4_CONTROL3_L3HSBM3(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL3_L3HSBM3_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL3_L3HSBM3_MASK) + +#define ENET_QOS_MAC_L3_L4_CONTROL3_L3HDBM3_MASK (0xF800U) +#define ENET_QOS_MAC_L3_L4_CONTROL3_L3HDBM3_SHIFT (11U) +/*! L3HDBM3 - Layer 3 IP DA Higher Bits Match IPv4 Packets: This field contains the number of higher + * bits of IP Destination Address that are matched in the IPv4 packets. + */ +#define ENET_QOS_MAC_L3_L4_CONTROL3_L3HDBM3(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL3_L3HDBM3_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL3_L3HDBM3_MASK) + +#define ENET_QOS_MAC_L3_L4_CONTROL3_L4PEN3_MASK (0x10000U) +#define ENET_QOS_MAC_L3_L4_CONTROL3_L4PEN3_SHIFT (16U) +/*! L4PEN3 - Layer 4 Protocol Enable When this bit is set, the Source and Destination Port number + * fields of UDP packets are used for matching. + * 0b0..Layer 4 Protocol is disabled + * 0b1..Layer 4 Protocol is enabled + */ +#define ENET_QOS_MAC_L3_L4_CONTROL3_L4PEN3(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL3_L4PEN3_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL3_L4PEN3_MASK) + +#define ENET_QOS_MAC_L3_L4_CONTROL3_L4SPM3_MASK (0x40000U) +#define ENET_QOS_MAC_L3_L4_CONTROL3_L4SPM3_SHIFT (18U) +/*! L4SPM3 - Layer 4 Source Port Match Enable When this bit is set, the Layer 4 Source Port number field is enabled for matching. + * 0b0..Layer 4 Source Port Match is disabled + * 0b1..Layer 4 Source Port Match is enabled + */ +#define ENET_QOS_MAC_L3_L4_CONTROL3_L4SPM3(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL3_L4SPM3_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL3_L4SPM3_MASK) + +#define ENET_QOS_MAC_L3_L4_CONTROL3_L4SPIM3_MASK (0x80000U) +#define ENET_QOS_MAC_L3_L4_CONTROL3_L4SPIM3_SHIFT (19U) +/*! L4SPIM3 - Layer 4 Source Port Inverse Match Enable When this bit is set, the Layer 4 Source Port + * number field is enabled for inverse matching. + * 0b0..Layer 4 Source Port Inverse Match is disabled + * 0b1..Layer 4 Source Port Inverse Match is enabled + */ +#define ENET_QOS_MAC_L3_L4_CONTROL3_L4SPIM3(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL3_L4SPIM3_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL3_L4SPIM3_MASK) + +#define ENET_QOS_MAC_L3_L4_CONTROL3_L4DPM3_MASK (0x100000U) +#define ENET_QOS_MAC_L3_L4_CONTROL3_L4DPM3_SHIFT (20U) +/*! L4DPM3 - Layer 4 Destination Port Match Enable When this bit is set, the Layer 4 Destination + * Port number field is enabled for matching. + * 0b0..Layer 4 Destination Port Match is disabled + * 0b1..Layer 4 Destination Port Match is enabled + */ +#define ENET_QOS_MAC_L3_L4_CONTROL3_L4DPM3(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL3_L4DPM3_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL3_L4DPM3_MASK) + +#define ENET_QOS_MAC_L3_L4_CONTROL3_L4DPIM3_MASK (0x200000U) +#define ENET_QOS_MAC_L3_L4_CONTROL3_L4DPIM3_SHIFT (21U) +/*! L4DPIM3 - Layer 4 Destination Port Inverse Match Enable When this bit is set, the Layer 4 + * Destination Port number field is enabled for inverse matching. + * 0b0..Layer 4 Destination Port Inverse Match is disabled + * 0b1..Layer 4 Destination Port Inverse Match is enabled + */ +#define ENET_QOS_MAC_L3_L4_CONTROL3_L4DPIM3(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL3_L4DPIM3_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL3_L4DPIM3_MASK) + +#define ENET_QOS_MAC_L3_L4_CONTROL3_DMCHN3_MASK (0x7000000U) +#define ENET_QOS_MAC_L3_L4_CONTROL3_DMCHN3_SHIFT (24U) +/*! DMCHN3 - DMA Channel Number When DMCHEN is set high, this field selects the DMA Channel number + * to which the packet passed by this filter is routed. + */ +#define ENET_QOS_MAC_L3_L4_CONTROL3_DMCHN3(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL3_DMCHN3_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL3_DMCHN3_MASK) + +#define ENET_QOS_MAC_L3_L4_CONTROL3_DMCHEN3_MASK (0x10000000U) +#define ENET_QOS_MAC_L3_L4_CONTROL3_DMCHEN3_SHIFT (28U) +/*! DMCHEN3 - DMA Channel Select Enable When set, this bit enables the selection of the DMA channel + * number for the packet that is passed by this L3_L4 filter. + * 0b0..DMA Channel Select is disabled + * 0b1..DMA Channel Select is enabled + */ +#define ENET_QOS_MAC_L3_L4_CONTROL3_DMCHEN3(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL3_DMCHEN3_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL3_DMCHEN3_MASK) +/*! @} */ + +/*! @name MAC_LAYER4_ADDRESS3 - Layer 4 Address 3 */ +/*! @{ */ + +#define ENET_QOS_MAC_LAYER4_ADDRESS3_L4SP3_MASK (0xFFFFU) +#define ENET_QOS_MAC_LAYER4_ADDRESS3_L4SP3_SHIFT (0U) +/*! L4SP3 - Layer 4 Source Port Number Field When the L4PEN3 bit is reset and the L4SPM0 bit is set + * in the MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with the TCP + * Source Port Number field in the IPv4 or IPv6 packets. + */ +#define ENET_QOS_MAC_LAYER4_ADDRESS3_L4SP3(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER4_ADDRESS3_L4SP3_SHIFT)) & ENET_QOS_MAC_LAYER4_ADDRESS3_L4SP3_MASK) + +#define ENET_QOS_MAC_LAYER4_ADDRESS3_L4DP3_MASK (0xFFFF0000U) +#define ENET_QOS_MAC_LAYER4_ADDRESS3_L4DP3_SHIFT (16U) +/*! L4DP3 - Layer 4 Destination Port Number Field When the L4PEN3 bit is reset and the L4DPM3 bit is + * set in the MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with the + * TCP Destination Port Number field in the IPv4 or IPv6 packets. + */ +#define ENET_QOS_MAC_LAYER4_ADDRESS3_L4DP3(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER4_ADDRESS3_L4DP3_SHIFT)) & ENET_QOS_MAC_LAYER4_ADDRESS3_L4DP3_MASK) +/*! @} */ + +/*! @name MAC_LAYER3_ADDR0_REG3 - Layer 3 Address 0 Register 3 */ +/*! @{ */ + +#define ENET_QOS_MAC_LAYER3_ADDR0_REG3_L3A03_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_LAYER3_ADDR0_REG3_L3A03_SHIFT (0U) +/*! L3A03 - Layer 3 Address 0 Field When the L3PEN0 and L3SAM0 bits are set in the + * MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[31:0] of the IP Source + * Address field in the IPv6 packets. + */ +#define ENET_QOS_MAC_LAYER3_ADDR0_REG3_L3A03(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER3_ADDR0_REG3_L3A03_SHIFT)) & ENET_QOS_MAC_LAYER3_ADDR0_REG3_L3A03_MASK) +/*! @} */ + +/*! @name MAC_LAYER3_ADDR1_REG3 - Layer 3 Address 1 Register 3 */ +/*! @{ */ + +#define ENET_QOS_MAC_LAYER3_ADDR1_REG3_L3A13_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_LAYER3_ADDR1_REG3_L3A13_SHIFT (0U) +/*! L3A13 - Layer 3 Address 1 Field When the L3PEN0 and L3SAM0 bits are set in the + * MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[63:32] of the IP Source + * Address field in the IPv6 packets. + */ +#define ENET_QOS_MAC_LAYER3_ADDR1_REG3_L3A13(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER3_ADDR1_REG3_L3A13_SHIFT)) & ENET_QOS_MAC_LAYER3_ADDR1_REG3_L3A13_MASK) +/*! @} */ + +/*! @name MAC_LAYER3_ADDR2_REG3 - Layer 3 Address 2 Register 3 */ +/*! @{ */ + +#define ENET_QOS_MAC_LAYER3_ADDR2_REG3_L3A23_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_LAYER3_ADDR2_REG3_L3A23_SHIFT (0U) +/*! L3A23 - Layer 3 Address 2 Field When the L3PEN0 and L3SAM0 bits are set in the + * MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[95:64] of the IP Source + * Address field in the IPv6 packets. + */ +#define ENET_QOS_MAC_LAYER3_ADDR2_REG3_L3A23(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER3_ADDR2_REG3_L3A23_SHIFT)) & ENET_QOS_MAC_LAYER3_ADDR2_REG3_L3A23_MASK) +/*! @} */ + +/*! @name MAC_LAYER3_ADDR3_REG3 - Layer 3 Address 3 Register 3 */ +/*! @{ */ + +#define ENET_QOS_MAC_LAYER3_ADDR3_REG3_L3A33_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_LAYER3_ADDR3_REG3_L3A33_SHIFT (0U) +/*! L3A33 - Layer 3 Address 3 Field When the L3PEN0 and L3SAM0 bits are set in the + * MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[127:96] of the IP Source + * Address field in the IPv6 packets. + */ +#define ENET_QOS_MAC_LAYER3_ADDR3_REG3_L3A33(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER3_ADDR3_REG3_L3A33_SHIFT)) & ENET_QOS_MAC_LAYER3_ADDR3_REG3_L3A33_MASK) +/*! @} */ + +/*! @name MAC_L3_L4_CONTROL4 - Layer 3 and Layer 4 Control of Filter 4 */ +/*! @{ */ + +#define ENET_QOS_MAC_L3_L4_CONTROL4_L3PEN4_MASK (0x1U) +#define ENET_QOS_MAC_L3_L4_CONTROL4_L3PEN4_SHIFT (0U) +/*! L3PEN4 - Layer 3 Protocol Enable When this bit is set, the Layer 3 IP Source or Destination + * Address matching is enabled for IPv6 packets. + * 0b0..Layer 3 Protocol is disabled + * 0b1..Layer 3 Protocol is enabled + */ +#define ENET_QOS_MAC_L3_L4_CONTROL4_L3PEN4(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL4_L3PEN4_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL4_L3PEN4_MASK) + +#define ENET_QOS_MAC_L3_L4_CONTROL4_L3SAM4_MASK (0x4U) +#define ENET_QOS_MAC_L3_L4_CONTROL4_L3SAM4_SHIFT (2U) +/*! L3SAM4 - Layer 3 IP SA Match Enable When this bit is set, the Layer 3 IP Source Address field is enabled for matching. + * 0b0..Layer 3 IP SA Match is disabled + * 0b1..Layer 3 IP SA Match is enabled + */ +#define ENET_QOS_MAC_L3_L4_CONTROL4_L3SAM4(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL4_L3SAM4_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL4_L3SAM4_MASK) + +#define ENET_QOS_MAC_L3_L4_CONTROL4_L3SAIM4_MASK (0x8U) +#define ENET_QOS_MAC_L3_L4_CONTROL4_L3SAIM4_SHIFT (3U) +/*! L3SAIM4 - Layer 3 IP SA Inverse Match Enable When this bit is set, the Layer 3 IP Source Address + * field is enabled for inverse matching. + * 0b0..Layer 3 IP SA Inverse Match is disabled + * 0b1..Layer 3 IP SA Inverse Match is enabled + */ +#define ENET_QOS_MAC_L3_L4_CONTROL4_L3SAIM4(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL4_L3SAIM4_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL4_L3SAIM4_MASK) + +#define ENET_QOS_MAC_L3_L4_CONTROL4_L3DAM4_MASK (0x10U) +#define ENET_QOS_MAC_L3_L4_CONTROL4_L3DAM4_SHIFT (4U) +/*! L3DAM4 - Layer 3 IP DA Match Enable When this bit is set, the Layer 3 IP Destination Address field is enabled for matching. + * 0b0..Layer 3 IP DA Match is disabled + * 0b1..Layer 3 IP DA Match is enabled + */ +#define ENET_QOS_MAC_L3_L4_CONTROL4_L3DAM4(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL4_L3DAM4_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL4_L3DAM4_MASK) + +#define ENET_QOS_MAC_L3_L4_CONTROL4_L3DAIM4_MASK (0x20U) +#define ENET_QOS_MAC_L3_L4_CONTROL4_L3DAIM4_SHIFT (5U) +/*! L3DAIM4 - Layer 3 IP DA Inverse Match Enable When this bit is set, the Layer 3 IP Destination + * Address field is enabled for inverse matching. + * 0b0..Layer 3 IP DA Inverse Match is disabled + * 0b1..Layer 3 IP DA Inverse Match is enabled + */ +#define ENET_QOS_MAC_L3_L4_CONTROL4_L3DAIM4(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL4_L3DAIM4_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL4_L3DAIM4_MASK) + +#define ENET_QOS_MAC_L3_L4_CONTROL4_L3HSBM4_MASK (0x7C0U) +#define ENET_QOS_MAC_L3_L4_CONTROL4_L3HSBM4_SHIFT (6U) +/*! L3HSBM4 - Layer 3 IP SA Higher Bits Match IPv4 Packets: This field contains the number of lower + * bits of IP Source Address that are masked for matching in the IPv4 packets. + */ +#define ENET_QOS_MAC_L3_L4_CONTROL4_L3HSBM4(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL4_L3HSBM4_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL4_L3HSBM4_MASK) + +#define ENET_QOS_MAC_L3_L4_CONTROL4_L3HDBM4_MASK (0xF800U) +#define ENET_QOS_MAC_L3_L4_CONTROL4_L3HDBM4_SHIFT (11U) +/*! L3HDBM4 - Layer 3 IP DA Higher Bits Match IPv4 Packets: This field contains the number of higher + * bits of IP Destination Address that are matched in the IPv4 packets. + */ +#define ENET_QOS_MAC_L3_L4_CONTROL4_L3HDBM4(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL4_L3HDBM4_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL4_L3HDBM4_MASK) + +#define ENET_QOS_MAC_L3_L4_CONTROL4_L4PEN4_MASK (0x10000U) +#define ENET_QOS_MAC_L3_L4_CONTROL4_L4PEN4_SHIFT (16U) +/*! L4PEN4 - Layer 4 Protocol Enable When this bit is set, the Source and Destination Port number + * fields of UDP packets are used for matching. + * 0b0..Layer 4 Protocol is disabled + * 0b1..Layer 4 Protocol is enabled + */ +#define ENET_QOS_MAC_L3_L4_CONTROL4_L4PEN4(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL4_L4PEN4_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL4_L4PEN4_MASK) + +#define ENET_QOS_MAC_L3_L4_CONTROL4_L4SPM4_MASK (0x40000U) +#define ENET_QOS_MAC_L3_L4_CONTROL4_L4SPM4_SHIFT (18U) +/*! L4SPM4 - Layer 4 Source Port Match Enable When this bit is set, the Layer 4 Source Port number field is enabled for matching. + * 0b0..Layer 4 Source Port Match is disabled + * 0b1..Layer 4 Source Port Match is enabled + */ +#define ENET_QOS_MAC_L3_L4_CONTROL4_L4SPM4(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL4_L4SPM4_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL4_L4SPM4_MASK) + +#define ENET_QOS_MAC_L3_L4_CONTROL4_L4SPIM4_MASK (0x80000U) +#define ENET_QOS_MAC_L3_L4_CONTROL4_L4SPIM4_SHIFT (19U) +/*! L4SPIM4 - Layer 4 Source Port Inverse Match Enable When this bit is set, the Layer 4 Source Port + * number field is enabled for inverse matching. + * 0b0..Layer 4 Source Port Inverse Match is disabled + * 0b1..Layer 4 Source Port Inverse Match is enabled + */ +#define ENET_QOS_MAC_L3_L4_CONTROL4_L4SPIM4(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL4_L4SPIM4_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL4_L4SPIM4_MASK) + +#define ENET_QOS_MAC_L3_L4_CONTROL4_L4DPM4_MASK (0x100000U) +#define ENET_QOS_MAC_L3_L4_CONTROL4_L4DPM4_SHIFT (20U) +/*! L4DPM4 - Layer 4 Destination Port Match Enable When this bit is set, the Layer 4 Destination + * Port number field is enabled for matching. + * 0b0..Layer 4 Destination Port Match is disabled + * 0b1..Layer 4 Destination Port Match is enabled + */ +#define ENET_QOS_MAC_L3_L4_CONTROL4_L4DPM4(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL4_L4DPM4_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL4_L4DPM4_MASK) + +#define ENET_QOS_MAC_L3_L4_CONTROL4_L4DPIM4_MASK (0x200000U) +#define ENET_QOS_MAC_L3_L4_CONTROL4_L4DPIM4_SHIFT (21U) +/*! L4DPIM4 - Layer 4 Destination Port Inverse Match Enable When this bit is set, the Layer 4 + * Destination Port number field is enabled for inverse matching. + * 0b0..Layer 4 Destination Port Inverse Match is disabled + * 0b1..Layer 4 Destination Port Inverse Match is enabled + */ +#define ENET_QOS_MAC_L3_L4_CONTROL4_L4DPIM4(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL4_L4DPIM4_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL4_L4DPIM4_MASK) + +#define ENET_QOS_MAC_L3_L4_CONTROL4_DMCHN4_MASK (0x7000000U) +#define ENET_QOS_MAC_L3_L4_CONTROL4_DMCHN4_SHIFT (24U) +/*! DMCHN4 - DMA Channel Number When DMCHEN is set high, this field selects the DMA Channel number + * to which the packet passed by this filter is routed. + */ +#define ENET_QOS_MAC_L3_L4_CONTROL4_DMCHN4(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL4_DMCHN4_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL4_DMCHN4_MASK) + +#define ENET_QOS_MAC_L3_L4_CONTROL4_DMCHEN4_MASK (0x10000000U) +#define ENET_QOS_MAC_L3_L4_CONTROL4_DMCHEN4_SHIFT (28U) +/*! DMCHEN4 - DMA Channel Select Enable When set, this bit enables the selection of the DMA channel + * number for the packet that is passed by this L3_L4 filter. + * 0b0..DMA Channel Select is disabled + * 0b1..DMA Channel Select is enabled + */ +#define ENET_QOS_MAC_L3_L4_CONTROL4_DMCHEN4(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL4_DMCHEN4_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL4_DMCHEN4_MASK) +/*! @} */ + +/*! @name MAC_LAYER4_ADDRESS4 - Layer 4 Address 4 */ +/*! @{ */ + +#define ENET_QOS_MAC_LAYER4_ADDRESS4_L4SP4_MASK (0xFFFFU) +#define ENET_QOS_MAC_LAYER4_ADDRESS4_L4SP4_SHIFT (0U) +/*! L4SP4 - Layer 4 Source Port Number Field When the L4PEN4 bit is reset and the L4SPM0 bit is set + * in the MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with the TCP + * Source Port Number field in the IPv4 or IPv6 packets. + */ +#define ENET_QOS_MAC_LAYER4_ADDRESS4_L4SP4(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER4_ADDRESS4_L4SP4_SHIFT)) & ENET_QOS_MAC_LAYER4_ADDRESS4_L4SP4_MASK) + +#define ENET_QOS_MAC_LAYER4_ADDRESS4_L4DP4_MASK (0xFFFF0000U) +#define ENET_QOS_MAC_LAYER4_ADDRESS4_L4DP4_SHIFT (16U) +/*! L4DP4 - Layer 4 Destination Port Number Field When the L4PEN4 bit is reset and the L4DPM4 bit is + * set in the MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with the + * TCP Destination Port Number field in the IPv4 or IPv6 packets. + */ +#define ENET_QOS_MAC_LAYER4_ADDRESS4_L4DP4(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER4_ADDRESS4_L4DP4_SHIFT)) & ENET_QOS_MAC_LAYER4_ADDRESS4_L4DP4_MASK) +/*! @} */ + +/*! @name MAC_LAYER3_ADDR0_REG4 - Layer 3 Address 0 Register 4 */ +/*! @{ */ + +#define ENET_QOS_MAC_LAYER3_ADDR0_REG4_L3A04_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_LAYER3_ADDR0_REG4_L3A04_SHIFT (0U) +/*! L3A04 - Layer 3 Address 0 Field When the L3PEN0 and L3SAM0 bits are set in the + * MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[31:0] of the IP Source + * Address field in the IPv6 packets. + */ +#define ENET_QOS_MAC_LAYER3_ADDR0_REG4_L3A04(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER3_ADDR0_REG4_L3A04_SHIFT)) & ENET_QOS_MAC_LAYER3_ADDR0_REG4_L3A04_MASK) +/*! @} */ + +/*! @name MAC_LAYER3_ADDR1_REG4 - Layer 3 Address 1 Register 4 */ +/*! @{ */ + +#define ENET_QOS_MAC_LAYER3_ADDR1_REG4_L3A14_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_LAYER3_ADDR1_REG4_L3A14_SHIFT (0U) +/*! L3A14 - Layer 3 Address 1 Field When the L3PEN0 and L3SAM0 bits are set in the + * MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[63:32] of the IP Source + * Address field in the IPv6 packets. + */ +#define ENET_QOS_MAC_LAYER3_ADDR1_REG4_L3A14(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER3_ADDR1_REG4_L3A14_SHIFT)) & ENET_QOS_MAC_LAYER3_ADDR1_REG4_L3A14_MASK) +/*! @} */ + +/*! @name MAC_LAYER3_ADDR2_REG4 - Layer 3 Address 2 Register 4 */ +/*! @{ */ + +#define ENET_QOS_MAC_LAYER3_ADDR2_REG4_L3A24_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_LAYER3_ADDR2_REG4_L3A24_SHIFT (0U) +/*! L3A24 - Layer 3 Address 2 Field When the L3PEN0 and L3SAM0 bits are set in the + * MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[95:64] of the IP Source + * Address field in the IPv6 packets. + */ +#define ENET_QOS_MAC_LAYER3_ADDR2_REG4_L3A24(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER3_ADDR2_REG4_L3A24_SHIFT)) & ENET_QOS_MAC_LAYER3_ADDR2_REG4_L3A24_MASK) +/*! @} */ + +/*! @name MAC_LAYER3_ADDR3_REG4 - Layer 3 Address 3 Register 4 */ +/*! @{ */ + +#define ENET_QOS_MAC_LAYER3_ADDR3_REG4_L3A34_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_LAYER3_ADDR3_REG4_L3A34_SHIFT (0U) +/*! L3A34 - Layer 3 Address 3 Field When the L3PEN0 and L3SAM0 bits are set in the + * MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[127:96] of the IP Source + * Address field in the IPv6 packets. + */ +#define ENET_QOS_MAC_LAYER3_ADDR3_REG4_L3A34(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER3_ADDR3_REG4_L3A34_SHIFT)) & ENET_QOS_MAC_LAYER3_ADDR3_REG4_L3A34_MASK) +/*! @} */ + +/*! @name MAC_L3_L4_CONTROL5 - Layer 3 and Layer 4 Control of Filter 5 */ +/*! @{ */ + +#define ENET_QOS_MAC_L3_L4_CONTROL5_L3PEN5_MASK (0x1U) +#define ENET_QOS_MAC_L3_L4_CONTROL5_L3PEN5_SHIFT (0U) +/*! L3PEN5 - Layer 3 Protocol Enable When this bit is set, the Layer 3 IP Source or Destination + * Address matching is enabled for IPv6 packets. + * 0b0..Layer 3 Protocol is disabled + * 0b1..Layer 3 Protocol is enabled + */ +#define ENET_QOS_MAC_L3_L4_CONTROL5_L3PEN5(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL5_L3PEN5_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL5_L3PEN5_MASK) + +#define ENET_QOS_MAC_L3_L4_CONTROL5_L3SAM5_MASK (0x4U) +#define ENET_QOS_MAC_L3_L4_CONTROL5_L3SAM5_SHIFT (2U) +/*! L3SAM5 - Layer 3 IP SA Match Enable When this bit is set, the Layer 3 IP Source Address field is enabled for matching. + * 0b0..Layer 3 IP SA Match is disabled + * 0b1..Layer 3 IP SA Match is enabled + */ +#define ENET_QOS_MAC_L3_L4_CONTROL5_L3SAM5(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL5_L3SAM5_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL5_L3SAM5_MASK) + +#define ENET_QOS_MAC_L3_L4_CONTROL5_L3SAIM5_MASK (0x8U) +#define ENET_QOS_MAC_L3_L4_CONTROL5_L3SAIM5_SHIFT (3U) +/*! L3SAIM5 - Layer 3 IP SA Inverse Match Enable When this bit is set, the Layer 3 IP Source Address + * field is enabled for inverse matching. + * 0b0..Layer 3 IP SA Inverse Match is disabled + * 0b1..Layer 3 IP SA Inverse Match is enabled + */ +#define ENET_QOS_MAC_L3_L4_CONTROL5_L3SAIM5(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL5_L3SAIM5_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL5_L3SAIM5_MASK) + +#define ENET_QOS_MAC_L3_L4_CONTROL5_L3DAM5_MASK (0x10U) +#define ENET_QOS_MAC_L3_L4_CONTROL5_L3DAM5_SHIFT (4U) +/*! L3DAM5 - Layer 3 IP DA Match Enable When this bit is set, the Layer 3 IP Destination Address field is enabled for matching. + * 0b0..Layer 3 IP DA Match is disabled + * 0b1..Layer 3 IP DA Match is enabled + */ +#define ENET_QOS_MAC_L3_L4_CONTROL5_L3DAM5(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL5_L3DAM5_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL5_L3DAM5_MASK) + +#define ENET_QOS_MAC_L3_L4_CONTROL5_L3DAIM5_MASK (0x20U) +#define ENET_QOS_MAC_L3_L4_CONTROL5_L3DAIM5_SHIFT (5U) +/*! L3DAIM5 - Layer 3 IP DA Inverse Match Enable When this bit is set, the Layer 3 IP Destination + * Address field is enabled for inverse matching. + * 0b0..Layer 3 IP DA Inverse Match is disabled + * 0b1..Layer 3 IP DA Inverse Match is enabled + */ +#define ENET_QOS_MAC_L3_L4_CONTROL5_L3DAIM5(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL5_L3DAIM5_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL5_L3DAIM5_MASK) + +#define ENET_QOS_MAC_L3_L4_CONTROL5_L3HSBM5_MASK (0x7C0U) +#define ENET_QOS_MAC_L3_L4_CONTROL5_L3HSBM5_SHIFT (6U) +/*! L3HSBM5 - Layer 3 IP SA Higher Bits Match IPv4 Packets: This field contains the number of lower + * bits of IP Source Address that are masked for matching in the IPv4 packets. + */ +#define ENET_QOS_MAC_L3_L4_CONTROL5_L3HSBM5(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL5_L3HSBM5_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL5_L3HSBM5_MASK) + +#define ENET_QOS_MAC_L3_L4_CONTROL5_L3HDBM5_MASK (0xF800U) +#define ENET_QOS_MAC_L3_L4_CONTROL5_L3HDBM5_SHIFT (11U) +/*! L3HDBM5 - Layer 3 IP DA Higher Bits Match IPv4 Packets: This field contains the number of higher + * bits of IP Destination Address that are matched in the IPv4 packets. + */ +#define ENET_QOS_MAC_L3_L4_CONTROL5_L3HDBM5(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL5_L3HDBM5_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL5_L3HDBM5_MASK) + +#define ENET_QOS_MAC_L3_L4_CONTROL5_L4PEN5_MASK (0x10000U) +#define ENET_QOS_MAC_L3_L4_CONTROL5_L4PEN5_SHIFT (16U) +/*! L4PEN5 - Layer 4 Protocol Enable When this bit is set, the Source and Destination Port number + * fields of UDP packets are used for matching. + * 0b0..Layer 4 Protocol is disabled + * 0b1..Layer 4 Protocol is enabled + */ +#define ENET_QOS_MAC_L3_L4_CONTROL5_L4PEN5(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL5_L4PEN5_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL5_L4PEN5_MASK) + +#define ENET_QOS_MAC_L3_L4_CONTROL5_L4SPM5_MASK (0x40000U) +#define ENET_QOS_MAC_L3_L4_CONTROL5_L4SPM5_SHIFT (18U) +/*! L4SPM5 - Layer 4 Source Port Match Enable When this bit is set, the Layer 4 Source Port number field is enabled for matching. + * 0b0..Layer 4 Source Port Match is disabled + * 0b1..Layer 4 Source Port Match is enabled + */ +#define ENET_QOS_MAC_L3_L4_CONTROL5_L4SPM5(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL5_L4SPM5_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL5_L4SPM5_MASK) + +#define ENET_QOS_MAC_L3_L4_CONTROL5_L4SPIM5_MASK (0x80000U) +#define ENET_QOS_MAC_L3_L4_CONTROL5_L4SPIM5_SHIFT (19U) +/*! L4SPIM5 - Layer 4 Source Port Inverse Match Enable When this bit is set, the Layer 4 Source Port + * number field is enabled for inverse matching. + * 0b0..Layer 4 Source Port Inverse Match is disabled + * 0b1..Layer 4 Source Port Inverse Match is enabled + */ +#define ENET_QOS_MAC_L3_L4_CONTROL5_L4SPIM5(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL5_L4SPIM5_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL5_L4SPIM5_MASK) + +#define ENET_QOS_MAC_L3_L4_CONTROL5_L4DPM5_MASK (0x100000U) +#define ENET_QOS_MAC_L3_L4_CONTROL5_L4DPM5_SHIFT (20U) +/*! L4DPM5 - Layer 4 Destination Port Match Enable When this bit is set, the Layer 4 Destination + * Port number field is enabled for matching. + * 0b0..Layer 4 Destination Port Match is disabled + * 0b1..Layer 4 Destination Port Match is enabled + */ +#define ENET_QOS_MAC_L3_L4_CONTROL5_L4DPM5(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL5_L4DPM5_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL5_L4DPM5_MASK) + +#define ENET_QOS_MAC_L3_L4_CONTROL5_L4DPIM5_MASK (0x200000U) +#define ENET_QOS_MAC_L3_L4_CONTROL5_L4DPIM5_SHIFT (21U) +/*! L4DPIM5 - Layer 4 Destination Port Inverse Match Enable When this bit is set, the Layer 4 + * Destination Port number field is enabled for inverse matching. + * 0b0..Layer 4 Destination Port Inverse Match is disabled + * 0b1..Layer 4 Destination Port Inverse Match is enabled + */ +#define ENET_QOS_MAC_L3_L4_CONTROL5_L4DPIM5(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL5_L4DPIM5_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL5_L4DPIM5_MASK) + +#define ENET_QOS_MAC_L3_L4_CONTROL5_DMCHN5_MASK (0x7000000U) +#define ENET_QOS_MAC_L3_L4_CONTROL5_DMCHN5_SHIFT (24U) +/*! DMCHN5 - DMA Channel Number When DMCHEN is set high, this field selects the DMA Channel number + * to which the packet passed by this filter is routed. + */ +#define ENET_QOS_MAC_L3_L4_CONTROL5_DMCHN5(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL5_DMCHN5_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL5_DMCHN5_MASK) + +#define ENET_QOS_MAC_L3_L4_CONTROL5_DMCHEN5_MASK (0x10000000U) +#define ENET_QOS_MAC_L3_L4_CONTROL5_DMCHEN5_SHIFT (28U) +/*! DMCHEN5 - DMA Channel Select Enable When set, this bit enables the selection of the DMA channel + * number for the packet that is passed by this L3_L4 filter. + * 0b0..DMA Channel Select is disabled + * 0b1..DMA Channel Select is enabled + */ +#define ENET_QOS_MAC_L3_L4_CONTROL5_DMCHEN5(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL5_DMCHEN5_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL5_DMCHEN5_MASK) +/*! @} */ + +/*! @name MAC_LAYER4_ADDRESS5 - Layer 4 Address 5 */ +/*! @{ */ + +#define ENET_QOS_MAC_LAYER4_ADDRESS5_L4SP5_MASK (0xFFFFU) +#define ENET_QOS_MAC_LAYER4_ADDRESS5_L4SP5_SHIFT (0U) +/*! L4SP5 - Layer 4 Source Port Number Field When the L4PEN5 bit is reset and the L4SPM0 bit is set + * in the MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with the TCP + * Source Port Number field in the IPv4 or IPv6 packets. + */ +#define ENET_QOS_MAC_LAYER4_ADDRESS5_L4SP5(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER4_ADDRESS5_L4SP5_SHIFT)) & ENET_QOS_MAC_LAYER4_ADDRESS5_L4SP5_MASK) + +#define ENET_QOS_MAC_LAYER4_ADDRESS5_L4DP5_MASK (0xFFFF0000U) +#define ENET_QOS_MAC_LAYER4_ADDRESS5_L4DP5_SHIFT (16U) +/*! L4DP5 - Layer 4 Destination Port Number Field When the L4PEN5 bit is reset and the L4DPM5 bit is + * set in the MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with the + * TCP Destination Port Number field in the IPv4 or IPv6 packets. + */ +#define ENET_QOS_MAC_LAYER4_ADDRESS5_L4DP5(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER4_ADDRESS5_L4DP5_SHIFT)) & ENET_QOS_MAC_LAYER4_ADDRESS5_L4DP5_MASK) +/*! @} */ + +/*! @name MAC_LAYER3_ADDR0_REG5 - Layer 3 Address 0 Register 5 */ +/*! @{ */ + +#define ENET_QOS_MAC_LAYER3_ADDR0_REG5_L3A05_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_LAYER3_ADDR0_REG5_L3A05_SHIFT (0U) +/*! L3A05 - Layer 3 Address 0 Field When the L3PEN0 and L3SAM0 bits are set in the + * MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[31:0] of the IP Source + * Address field in the IPv6 packets. + */ +#define ENET_QOS_MAC_LAYER3_ADDR0_REG5_L3A05(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER3_ADDR0_REG5_L3A05_SHIFT)) & ENET_QOS_MAC_LAYER3_ADDR0_REG5_L3A05_MASK) +/*! @} */ + +/*! @name MAC_LAYER3_ADDR1_REG5 - Layer 3 Address 1 Register 5 */ +/*! @{ */ + +#define ENET_QOS_MAC_LAYER3_ADDR1_REG5_L3A15_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_LAYER3_ADDR1_REG5_L3A15_SHIFT (0U) +/*! L3A15 - Layer 3 Address 1 Field When the L3PEN0 and L3SAM0 bits are set in the + * MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[63:32] of the IP Source + * Address field in the IPv6 packets. + */ +#define ENET_QOS_MAC_LAYER3_ADDR1_REG5_L3A15(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER3_ADDR1_REG5_L3A15_SHIFT)) & ENET_QOS_MAC_LAYER3_ADDR1_REG5_L3A15_MASK) +/*! @} */ + +/*! @name MAC_LAYER3_ADDR2_REG5 - Layer 3 Address 2 Register 5 */ +/*! @{ */ + +#define ENET_QOS_MAC_LAYER3_ADDR2_REG5_L3A25_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_LAYER3_ADDR2_REG5_L3A25_SHIFT (0U) +/*! L3A25 - Layer 3 Address 2 Field When the L3PEN0 and L3SAM0 bits are set in the + * MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[95:64] of the IP Source + * Address field in the IPv6 packets. + */ +#define ENET_QOS_MAC_LAYER3_ADDR2_REG5_L3A25(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER3_ADDR2_REG5_L3A25_SHIFT)) & ENET_QOS_MAC_LAYER3_ADDR2_REG5_L3A25_MASK) +/*! @} */ + +/*! @name MAC_LAYER3_ADDR3_REG5 - Layer 3 Address 3 Register 5 */ +/*! @{ */ + +#define ENET_QOS_MAC_LAYER3_ADDR3_REG5_L3A35_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_LAYER3_ADDR3_REG5_L3A35_SHIFT (0U) +/*! L3A35 - Layer 3 Address 3 Field When the L3PEN0 and L3SAM0 bits are set in the + * MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[127:96] of the IP Source + * Address field in the IPv6 packets. + */ +#define ENET_QOS_MAC_LAYER3_ADDR3_REG5_L3A35(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER3_ADDR3_REG5_L3A35_SHIFT)) & ENET_QOS_MAC_LAYER3_ADDR3_REG5_L3A35_MASK) +/*! @} */ + +/*! @name MAC_L3_L4_CONTROL6 - Layer 3 and Layer 4 Control of Filter 6 */ +/*! @{ */ + +#define ENET_QOS_MAC_L3_L4_CONTROL6_L3PEN6_MASK (0x1U) +#define ENET_QOS_MAC_L3_L4_CONTROL6_L3PEN6_SHIFT (0U) +/*! L3PEN6 - Layer 3 Protocol Enable When this bit is set, the Layer 3 IP Source or Destination + * Address matching is enabled for IPv6 packets. + * 0b0..Layer 3 Protocol is disabled + * 0b1..Layer 3 Protocol is enabled + */ +#define ENET_QOS_MAC_L3_L4_CONTROL6_L3PEN6(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL6_L3PEN6_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL6_L3PEN6_MASK) + +#define ENET_QOS_MAC_L3_L4_CONTROL6_L3SAM6_MASK (0x4U) +#define ENET_QOS_MAC_L3_L4_CONTROL6_L3SAM6_SHIFT (2U) +/*! L3SAM6 - Layer 3 IP SA Match Enable When this bit is set, the Layer 3 IP Source Address field is enabled for matching. + * 0b0..Layer 3 IP SA Match is disabled + * 0b1..Layer 3 IP SA Match is enabled + */ +#define ENET_QOS_MAC_L3_L4_CONTROL6_L3SAM6(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL6_L3SAM6_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL6_L3SAM6_MASK) + +#define ENET_QOS_MAC_L3_L4_CONTROL6_L3SAIM6_MASK (0x8U) +#define ENET_QOS_MAC_L3_L4_CONTROL6_L3SAIM6_SHIFT (3U) +/*! L3SAIM6 - Layer 3 IP SA Inverse Match Enable When this bit is set, the Layer 3 IP Source Address + * field is enabled for inverse matching. + * 0b0..Layer 3 IP SA Inverse Match is disabled + * 0b1..Layer 3 IP SA Inverse Match is enabled + */ +#define ENET_QOS_MAC_L3_L4_CONTROL6_L3SAIM6(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL6_L3SAIM6_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL6_L3SAIM6_MASK) + +#define ENET_QOS_MAC_L3_L4_CONTROL6_L3DAM6_MASK (0x10U) +#define ENET_QOS_MAC_L3_L4_CONTROL6_L3DAM6_SHIFT (4U) +/*! L3DAM6 - Layer 3 IP DA Match Enable When this bit is set, the Layer 3 IP Destination Address field is enabled for matching. + * 0b0..Layer 3 IP DA Match is disabled + * 0b1..Layer 3 IP DA Match is enabled + */ +#define ENET_QOS_MAC_L3_L4_CONTROL6_L3DAM6(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL6_L3DAM6_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL6_L3DAM6_MASK) + +#define ENET_QOS_MAC_L3_L4_CONTROL6_L3DAIM6_MASK (0x20U) +#define ENET_QOS_MAC_L3_L4_CONTROL6_L3DAIM6_SHIFT (5U) +/*! L3DAIM6 - Layer 3 IP DA Inverse Match Enable When this bit is set, the Layer 3 IP Destination + * Address field is enabled for inverse matching. + * 0b0..Layer 3 IP DA Inverse Match is disabled + * 0b1..Layer 3 IP DA Inverse Match is enabled + */ +#define ENET_QOS_MAC_L3_L4_CONTROL6_L3DAIM6(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL6_L3DAIM6_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL6_L3DAIM6_MASK) + +#define ENET_QOS_MAC_L3_L4_CONTROL6_L3HSBM6_MASK (0x7C0U) +#define ENET_QOS_MAC_L3_L4_CONTROL6_L3HSBM6_SHIFT (6U) +/*! L3HSBM6 - Layer 3 IP SA Higher Bits Match IPv4 Packets: This field contains the number of lower + * bits of IP Source Address that are masked for matching in the IPv4 packets. + */ +#define ENET_QOS_MAC_L3_L4_CONTROL6_L3HSBM6(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL6_L3HSBM6_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL6_L3HSBM6_MASK) + +#define ENET_QOS_MAC_L3_L4_CONTROL6_L3HDBM6_MASK (0xF800U) +#define ENET_QOS_MAC_L3_L4_CONTROL6_L3HDBM6_SHIFT (11U) +/*! L3HDBM6 - Layer 3 IP DA Higher Bits Match IPv4 Packets: This field contains the number of higher + * bits of IP Destination Address that are matched in the IPv4 packets. + */ +#define ENET_QOS_MAC_L3_L4_CONTROL6_L3HDBM6(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL6_L3HDBM6_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL6_L3HDBM6_MASK) + +#define ENET_QOS_MAC_L3_L4_CONTROL6_L4PEN6_MASK (0x10000U) +#define ENET_QOS_MAC_L3_L4_CONTROL6_L4PEN6_SHIFT (16U) +/*! L4PEN6 - Layer 4 Protocol Enable When this bit is set, the Source and Destination Port number + * fields of UDP packets are used for matching. + * 0b0..Layer 4 Protocol is disabled + * 0b1..Layer 4 Protocol is enabled + */ +#define ENET_QOS_MAC_L3_L4_CONTROL6_L4PEN6(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL6_L4PEN6_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL6_L4PEN6_MASK) + +#define ENET_QOS_MAC_L3_L4_CONTROL6_L4SPM6_MASK (0x40000U) +#define ENET_QOS_MAC_L3_L4_CONTROL6_L4SPM6_SHIFT (18U) +/*! L4SPM6 - Layer 4 Source Port Match Enable When this bit is set, the Layer 4 Source Port number field is enabled for matching. + * 0b0..Layer 4 Source Port Match is disabled + * 0b1..Layer 4 Source Port Match is enabled + */ +#define ENET_QOS_MAC_L3_L4_CONTROL6_L4SPM6(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL6_L4SPM6_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL6_L4SPM6_MASK) + +#define ENET_QOS_MAC_L3_L4_CONTROL6_L4SPIM6_MASK (0x80000U) +#define ENET_QOS_MAC_L3_L4_CONTROL6_L4SPIM6_SHIFT (19U) +/*! L4SPIM6 - Layer 4 Source Port Inverse Match Enable When this bit is set, the Layer 4 Source Port + * number field is enabled for inverse matching. + * 0b0..Layer 4 Source Port Inverse Match is disabled + * 0b1..Layer 4 Source Port Inverse Match is enabled + */ +#define ENET_QOS_MAC_L3_L4_CONTROL6_L4SPIM6(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL6_L4SPIM6_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL6_L4SPIM6_MASK) + +#define ENET_QOS_MAC_L3_L4_CONTROL6_L4DPM6_MASK (0x100000U) +#define ENET_QOS_MAC_L3_L4_CONTROL6_L4DPM6_SHIFT (20U) +/*! L4DPM6 - Layer 4 Destination Port Match Enable When this bit is set, the Layer 4 Destination + * Port number field is enabled for matching. + * 0b0..Layer 4 Destination Port Match is disabled + * 0b1..Layer 4 Destination Port Match is enabled + */ +#define ENET_QOS_MAC_L3_L4_CONTROL6_L4DPM6(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL6_L4DPM6_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL6_L4DPM6_MASK) + +#define ENET_QOS_MAC_L3_L4_CONTROL6_L4DPIM6_MASK (0x200000U) +#define ENET_QOS_MAC_L3_L4_CONTROL6_L4DPIM6_SHIFT (21U) +/*! L4DPIM6 - Layer 4 Destination Port Inverse Match Enable When this bit is set, the Layer 4 + * Destination Port number field is enabled for inverse matching. + * 0b0..Layer 4 Destination Port Inverse Match is disabled + * 0b1..Layer 4 Destination Port Inverse Match is enabled + */ +#define ENET_QOS_MAC_L3_L4_CONTROL6_L4DPIM6(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL6_L4DPIM6_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL6_L4DPIM6_MASK) + +#define ENET_QOS_MAC_L3_L4_CONTROL6_DMCHN6_MASK (0x7000000U) +#define ENET_QOS_MAC_L3_L4_CONTROL6_DMCHN6_SHIFT (24U) +/*! DMCHN6 - DMA Channel Number When DMCHEN is set high, this field selects the DMA Channel number + * to which the packet passed by this filter is routed. + */ +#define ENET_QOS_MAC_L3_L4_CONTROL6_DMCHN6(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL6_DMCHN6_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL6_DMCHN6_MASK) + +#define ENET_QOS_MAC_L3_L4_CONTROL6_DMCHEN6_MASK (0x10000000U) +#define ENET_QOS_MAC_L3_L4_CONTROL6_DMCHEN6_SHIFT (28U) +/*! DMCHEN6 - DMA Channel Select Enable When set, this bit enables the selection of the DMA channel + * number for the packet that is passed by this L3_L4 filter. + * 0b0..DMA Channel Select is disabled + * 0b1..DMA Channel Select is enabled + */ +#define ENET_QOS_MAC_L3_L4_CONTROL6_DMCHEN6(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL6_DMCHEN6_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL6_DMCHEN6_MASK) +/*! @} */ + +/*! @name MAC_LAYER4_ADDRESS6 - Layer 4 Address 6 */ +/*! @{ */ + +#define ENET_QOS_MAC_LAYER4_ADDRESS6_L4SP6_MASK (0xFFFFU) +#define ENET_QOS_MAC_LAYER4_ADDRESS6_L4SP6_SHIFT (0U) +/*! L4SP6 - Layer 4 Source Port Number Field When the L4PEN6 bit is reset and the L4SPM0 bit is set + * in the MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with the TCP + * Source Port Number field in the IPv4 or IPv6 packets. + */ +#define ENET_QOS_MAC_LAYER4_ADDRESS6_L4SP6(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER4_ADDRESS6_L4SP6_SHIFT)) & ENET_QOS_MAC_LAYER4_ADDRESS6_L4SP6_MASK) + +#define ENET_QOS_MAC_LAYER4_ADDRESS6_L4DP6_MASK (0xFFFF0000U) +#define ENET_QOS_MAC_LAYER4_ADDRESS6_L4DP6_SHIFT (16U) +/*! L4DP6 - Layer 4 Destination Port Number Field When the L4PEN6 bit is reset and the L4DPM6 bit is + * set in the MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with the + * TCP Destination Port Number field in the IPv4 or IPv6 packets. + */ +#define ENET_QOS_MAC_LAYER4_ADDRESS6_L4DP6(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER4_ADDRESS6_L4DP6_SHIFT)) & ENET_QOS_MAC_LAYER4_ADDRESS6_L4DP6_MASK) +/*! @} */ + +/*! @name MAC_LAYER3_ADDR0_REG6 - Layer 3 Address 0 Register 6 */ +/*! @{ */ + +#define ENET_QOS_MAC_LAYER3_ADDR0_REG6_L3A06_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_LAYER3_ADDR0_REG6_L3A06_SHIFT (0U) +/*! L3A06 - Layer 3 Address 0 Field When the L3PEN0 and L3SAM0 bits are set in the + * MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[31:0] of the IP Source + * Address field in the IPv6 packets. + */ +#define ENET_QOS_MAC_LAYER3_ADDR0_REG6_L3A06(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER3_ADDR0_REG6_L3A06_SHIFT)) & ENET_QOS_MAC_LAYER3_ADDR0_REG6_L3A06_MASK) +/*! @} */ + +/*! @name MAC_LAYER3_ADDR1_REG6 - Layer 3 Address 1 Register 6 */ +/*! @{ */ + +#define ENET_QOS_MAC_LAYER3_ADDR1_REG6_L3A16_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_LAYER3_ADDR1_REG6_L3A16_SHIFT (0U) +/*! L3A16 - Layer 3 Address 1 Field When the L3PEN0 and L3SAM0 bits are set in the + * MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[63:32] of the IP Source + * Address field in the IPv6 packets. + */ +#define ENET_QOS_MAC_LAYER3_ADDR1_REG6_L3A16(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER3_ADDR1_REG6_L3A16_SHIFT)) & ENET_QOS_MAC_LAYER3_ADDR1_REG6_L3A16_MASK) +/*! @} */ + +/*! @name MAC_LAYER3_ADDR2_REG6 - Layer 3 Address 2 Register 6 */ +/*! @{ */ + +#define ENET_QOS_MAC_LAYER3_ADDR2_REG6_L3A26_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_LAYER3_ADDR2_REG6_L3A26_SHIFT (0U) +/*! L3A26 - Layer 3 Address 2 Field When the L3PEN0 and L3SAM0 bits are set in the + * MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[95:64] of the IP Source + * Address field in the IPv6 packets. + */ +#define ENET_QOS_MAC_LAYER3_ADDR2_REG6_L3A26(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER3_ADDR2_REG6_L3A26_SHIFT)) & ENET_QOS_MAC_LAYER3_ADDR2_REG6_L3A26_MASK) +/*! @} */ + +/*! @name MAC_LAYER3_ADDR3_REG6 - Layer 3 Address 3 Register 6 */ +/*! @{ */ + +#define ENET_QOS_MAC_LAYER3_ADDR3_REG6_L3A36_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_LAYER3_ADDR3_REG6_L3A36_SHIFT (0U) +/*! L3A36 - Layer 3 Address 3 Field When the L3PEN0 and L3SAM0 bits are set in the + * MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[127:96] of the IP Source + * Address field in the IPv6 packets. + */ +#define ENET_QOS_MAC_LAYER3_ADDR3_REG6_L3A36(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER3_ADDR3_REG6_L3A36_SHIFT)) & ENET_QOS_MAC_LAYER3_ADDR3_REG6_L3A36_MASK) +/*! @} */ + +/*! @name MAC_L3_L4_CONTROL7 - Layer 3 and Layer 4 Control of Filter 0 */ +/*! @{ */ + +#define ENET_QOS_MAC_L3_L4_CONTROL7_L3PEN7_MASK (0x1U) +#define ENET_QOS_MAC_L3_L4_CONTROL7_L3PEN7_SHIFT (0U) +/*! L3PEN7 - Layer 3 Protocol Enable When this bit is set, the Layer 3 IP Source or Destination + * Address matching is enabled for IPv6 packets. + * 0b0..Layer 3 Protocol is disabled + * 0b1..Layer 3 Protocol is enabled + */ +#define ENET_QOS_MAC_L3_L4_CONTROL7_L3PEN7(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL7_L3PEN7_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL7_L3PEN7_MASK) + +#define ENET_QOS_MAC_L3_L4_CONTROL7_L3SAM7_MASK (0x4U) +#define ENET_QOS_MAC_L3_L4_CONTROL7_L3SAM7_SHIFT (2U) +/*! L3SAM7 - Layer 3 IP SA Match Enable When this bit is set, the Layer 3 IP Source Address field is enabled for matching. + * 0b0..Layer 3 IP SA Match is disabled + * 0b1..Layer 3 IP SA Match is enabled + */ +#define ENET_QOS_MAC_L3_L4_CONTROL7_L3SAM7(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL7_L3SAM7_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL7_L3SAM7_MASK) + +#define ENET_QOS_MAC_L3_L4_CONTROL7_L3SAIM7_MASK (0x8U) +#define ENET_QOS_MAC_L3_L4_CONTROL7_L3SAIM7_SHIFT (3U) +/*! L3SAIM7 - Layer 3 IP SA Inverse Match Enable When this bit is set, the Layer 3 IP Source Address + * field is enabled for inverse matching. + * 0b0..Layer 3 IP SA Inverse Match is disabled + * 0b1..Layer 3 IP SA Inverse Match is enabled + */ +#define ENET_QOS_MAC_L3_L4_CONTROL7_L3SAIM7(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL7_L3SAIM7_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL7_L3SAIM7_MASK) + +#define ENET_QOS_MAC_L3_L4_CONTROL7_L3DAM7_MASK (0x10U) +#define ENET_QOS_MAC_L3_L4_CONTROL7_L3DAM7_SHIFT (4U) +/*! L3DAM7 - Layer 3 IP DA Match Enable When this bit is set, the Layer 3 IP Destination Address field is enabled for matching. + * 0b0..Layer 3 IP DA Match is disabled + * 0b1..Layer 3 IP DA Match is enabled + */ +#define ENET_QOS_MAC_L3_L4_CONTROL7_L3DAM7(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL7_L3DAM7_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL7_L3DAM7_MASK) + +#define ENET_QOS_MAC_L3_L4_CONTROL7_L3DAIM7_MASK (0x20U) +#define ENET_QOS_MAC_L3_L4_CONTROL7_L3DAIM7_SHIFT (5U) +/*! L3DAIM7 - Layer 3 IP DA Inverse Match Enable When this bit is set, the Layer 3 IP Destination + * Address field is enabled for inverse matching. + * 0b0..Layer 3 IP DA Inverse Match is disabled + * 0b1..Layer 3 IP DA Inverse Match is enabled + */ +#define ENET_QOS_MAC_L3_L4_CONTROL7_L3DAIM7(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL7_L3DAIM7_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL7_L3DAIM7_MASK) + +#define ENET_QOS_MAC_L3_L4_CONTROL7_L3HSBM7_MASK (0x7C0U) +#define ENET_QOS_MAC_L3_L4_CONTROL7_L3HSBM7_SHIFT (6U) +/*! L3HSBM7 - Layer 3 IP SA Higher Bits Match IPv4 Packets: This field contains the number of lower + * bits of IP Source Address that are masked for matching in the IPv4 packets. + */ +#define ENET_QOS_MAC_L3_L4_CONTROL7_L3HSBM7(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL7_L3HSBM7_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL7_L3HSBM7_MASK) + +#define ENET_QOS_MAC_L3_L4_CONTROL7_L3HDBM7_MASK (0xF800U) +#define ENET_QOS_MAC_L3_L4_CONTROL7_L3HDBM7_SHIFT (11U) +/*! L3HDBM7 - Layer 3 IP DA Higher Bits Match IPv4 Packets: This field contains the number of higher + * bits of IP Destination Address that are matched in the IPv4 packets. + */ +#define ENET_QOS_MAC_L3_L4_CONTROL7_L3HDBM7(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL7_L3HDBM7_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL7_L3HDBM7_MASK) + +#define ENET_QOS_MAC_L3_L4_CONTROL7_L4PEN7_MASK (0x10000U) +#define ENET_QOS_MAC_L3_L4_CONTROL7_L4PEN7_SHIFT (16U) +/*! L4PEN7 - Layer 4 Protocol Enable When this bit is set, the Source and Destination Port number + * fields of UDP packets are used for matching. + * 0b0..Layer 4 Protocol is disabled + * 0b1..Layer 4 Protocol is enabled + */ +#define ENET_QOS_MAC_L3_L4_CONTROL7_L4PEN7(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL7_L4PEN7_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL7_L4PEN7_MASK) + +#define ENET_QOS_MAC_L3_L4_CONTROL7_L4SPM7_MASK (0x40000U) +#define ENET_QOS_MAC_L3_L4_CONTROL7_L4SPM7_SHIFT (18U) +/*! L4SPM7 - Layer 4 Source Port Match Enable When this bit is set, the Layer 4 Source Port number field is enabled for matching. + * 0b0..Layer 4 Source Port Match is disabled + * 0b1..Layer 4 Source Port Match is enabled + */ +#define ENET_QOS_MAC_L3_L4_CONTROL7_L4SPM7(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL7_L4SPM7_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL7_L4SPM7_MASK) + +#define ENET_QOS_MAC_L3_L4_CONTROL7_L4SPIM7_MASK (0x80000U) +#define ENET_QOS_MAC_L3_L4_CONTROL7_L4SPIM7_SHIFT (19U) +/*! L4SPIM7 - Layer 4 Source Port Inverse Match Enable When this bit is set, the Layer 4 Source Port + * number field is enabled for inverse matching. + * 0b0..Layer 4 Source Port Inverse Match is disabled + * 0b1..Layer 4 Source Port Inverse Match is enabled + */ +#define ENET_QOS_MAC_L3_L4_CONTROL7_L4SPIM7(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL7_L4SPIM7_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL7_L4SPIM7_MASK) + +#define ENET_QOS_MAC_L3_L4_CONTROL7_L4DPM7_MASK (0x100000U) +#define ENET_QOS_MAC_L3_L4_CONTROL7_L4DPM7_SHIFT (20U) +/*! L4DPM7 - Layer 4 Destination Port Match Enable When this bit is set, the Layer 4 Destination + * Port number field is enabled for matching. + * 0b0..Layer 4 Destination Port Match is disabled + * 0b1..Layer 4 Destination Port Match is enabled + */ +#define ENET_QOS_MAC_L3_L4_CONTROL7_L4DPM7(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL7_L4DPM7_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL7_L4DPM7_MASK) + +#define ENET_QOS_MAC_L3_L4_CONTROL7_L4DPIM7_MASK (0x200000U) +#define ENET_QOS_MAC_L3_L4_CONTROL7_L4DPIM7_SHIFT (21U) +/*! L4DPIM7 - Layer 4 Destination Port Inverse Match Enable When this bit is set, the Layer 4 + * Destination Port number field is enabled for inverse matching. + * 0b0..Layer 4 Destination Port Inverse Match is disabled + * 0b1..Layer 4 Destination Port Inverse Match is enabled + */ +#define ENET_QOS_MAC_L3_L4_CONTROL7_L4DPIM7(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL7_L4DPIM7_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL7_L4DPIM7_MASK) + +#define ENET_QOS_MAC_L3_L4_CONTROL7_DMCHN7_MASK (0x7000000U) +#define ENET_QOS_MAC_L3_L4_CONTROL7_DMCHN7_SHIFT (24U) +/*! DMCHN7 - DMA Channel Number When DMCHEN is set high, this field selects the DMA Channel number + * to which the packet passed by this filter is routed. + */ +#define ENET_QOS_MAC_L3_L4_CONTROL7_DMCHN7(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL7_DMCHN7_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL7_DMCHN7_MASK) + +#define ENET_QOS_MAC_L3_L4_CONTROL7_DMCHEN7_MASK (0x10000000U) +#define ENET_QOS_MAC_L3_L4_CONTROL7_DMCHEN7_SHIFT (28U) +/*! DMCHEN7 - DMA Channel Select Enable When set, this bit enables the selection of the DMA channel + * number for the packet that is passed by this L3_L4 filter. + * 0b0..DMA Channel Select is disabled + * 0b1..DMA Channel Select is enabled + */ +#define ENET_QOS_MAC_L3_L4_CONTROL7_DMCHEN7(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL7_DMCHEN7_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL7_DMCHEN7_MASK) +/*! @} */ + +/*! @name MAC_LAYER4_ADDRESS7 - Layer 4 Address 7 */ +/*! @{ */ + +#define ENET_QOS_MAC_LAYER4_ADDRESS7_L4SP7_MASK (0xFFFFU) +#define ENET_QOS_MAC_LAYER4_ADDRESS7_L4SP7_SHIFT (0U) +/*! L4SP7 - Layer 4 Source Port Number Field When the L4PEN7 bit is reset and the L4SPM0 bit is set + * in the MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with the TCP + * Source Port Number field in the IPv4 or IPv6 packets. + */ +#define ENET_QOS_MAC_LAYER4_ADDRESS7_L4SP7(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER4_ADDRESS7_L4SP7_SHIFT)) & ENET_QOS_MAC_LAYER4_ADDRESS7_L4SP7_MASK) + +#define ENET_QOS_MAC_LAYER4_ADDRESS7_L4DP7_MASK (0xFFFF0000U) +#define ENET_QOS_MAC_LAYER4_ADDRESS7_L4DP7_SHIFT (16U) +/*! L4DP7 - Layer 4 Destination Port Number Field When the L4PEN7 bit is reset and the L4DPM7 bit is + * set in the MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with the + * TCP Destination Port Number field in the IPv4 or IPv6 packets. + */ +#define ENET_QOS_MAC_LAYER4_ADDRESS7_L4DP7(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER4_ADDRESS7_L4DP7_SHIFT)) & ENET_QOS_MAC_LAYER4_ADDRESS7_L4DP7_MASK) +/*! @} */ + +/*! @name MAC_LAYER3_ADDR0_REG7 - Layer 3 Address 0 Register 7 */ +/*! @{ */ + +#define ENET_QOS_MAC_LAYER3_ADDR0_REG7_L3A07_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_LAYER3_ADDR0_REG7_L3A07_SHIFT (0U) +/*! L3A07 - Layer 3 Address 0 Field When the L3PEN0 and L3SAM0 bits are set in the + * MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[31:0] of the IP Source + * Address field in the IPv6 packets. + */ +#define ENET_QOS_MAC_LAYER3_ADDR0_REG7_L3A07(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER3_ADDR0_REG7_L3A07_SHIFT)) & ENET_QOS_MAC_LAYER3_ADDR0_REG7_L3A07_MASK) +/*! @} */ + +/*! @name MAC_LAYER3_ADDR1_REG7 - Layer 3 Address 1 Register 7 */ +/*! @{ */ + +#define ENET_QOS_MAC_LAYER3_ADDR1_REG7_L3A17_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_LAYER3_ADDR1_REG7_L3A17_SHIFT (0U) +/*! L3A17 - Layer 3 Address 1 Field When the L3PEN0 and L3SAM0 bits are set in the + * MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[63:32] of the IP Source + * Address field in the IPv6 packets. + */ +#define ENET_QOS_MAC_LAYER3_ADDR1_REG7_L3A17(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER3_ADDR1_REG7_L3A17_SHIFT)) & ENET_QOS_MAC_LAYER3_ADDR1_REG7_L3A17_MASK) +/*! @} */ + +/*! @name MAC_LAYER3_ADDR2_REG7 - Layer 3 Address 2 Register 7 */ +/*! @{ */ + +#define ENET_QOS_MAC_LAYER3_ADDR2_REG7_L3A27_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_LAYER3_ADDR2_REG7_L3A27_SHIFT (0U) +/*! L3A27 - Layer 3 Address 2 Field When the L3PEN0 and L3SAM0 bits are set in the + * MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[95:64] of the IP Source + * Address field in the IPv6 packets. + */ +#define ENET_QOS_MAC_LAYER3_ADDR2_REG7_L3A27(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER3_ADDR2_REG7_L3A27_SHIFT)) & ENET_QOS_MAC_LAYER3_ADDR2_REG7_L3A27_MASK) +/*! @} */ + +/*! @name MAC_LAYER3_ADDR3_REG7 - Layer 3 Address 3 Register 7 */ +/*! @{ */ + +#define ENET_QOS_MAC_LAYER3_ADDR3_REG7_L3A37_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_LAYER3_ADDR3_REG7_L3A37_SHIFT (0U) +/*! L3A37 - Layer 3 Address 3 Field When the L3PEN0 and L3SAM0 bits are set in the + * MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[127:96] of the IP Source + * Address field in the IPv6 packets. + */ +#define ENET_QOS_MAC_LAYER3_ADDR3_REG7_L3A37(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER3_ADDR3_REG7_L3A37_SHIFT)) & ENET_QOS_MAC_LAYER3_ADDR3_REG7_L3A37_MASK) +/*! @} */ + +/*! @name MAC_INDIR_ACCESS_CTRL - MAC_INDIR_ACCESS_CTRL */ +/*! @{ */ + +#define ENET_QOS_MAC_INDIR_ACCESS_CTRL_OB_MASK (0x1U) +#define ENET_QOS_MAC_INDIR_ACCESS_CTRL_OB_SHIFT (0U) +/*! OB - Operation Busy */ +#define ENET_QOS_MAC_INDIR_ACCESS_CTRL_OB(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INDIR_ACCESS_CTRL_OB_SHIFT)) & ENET_QOS_MAC_INDIR_ACCESS_CTRL_OB_MASK) + +#define ENET_QOS_MAC_INDIR_ACCESS_CTRL_COM_MASK (0x2U) +#define ENET_QOS_MAC_INDIR_ACCESS_CTRL_COM_SHIFT (1U) +/*! COM - Command type. Indicates the register access type. + * 0b0..Indicates a write operation + * 0b1..Indicates a read operation + */ +#define ENET_QOS_MAC_INDIR_ACCESS_CTRL_COM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INDIR_ACCESS_CTRL_COM_SHIFT)) & ENET_QOS_MAC_INDIR_ACCESS_CTRL_COM_MASK) + +#define ENET_QOS_MAC_INDIR_ACCESS_CTRL_AUTO_MASK (0x20U) +#define ENET_QOS_MAC_INDIR_ACCESS_CTRL_AUTO_SHIFT (5U) +/*! AUTO - Auto increment enable + * 0b0..AOFF is not incremented automatically. Software should program the correct Address Offset for each access. + * 0b1..AOFF is incremented by 1. Software should ensure not to cause a wrap condition. Byte wise read/write is + * not supported when auto increment is enabled. + */ +#define ENET_QOS_MAC_INDIR_ACCESS_CTRL_AUTO(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INDIR_ACCESS_CTRL_AUTO_SHIFT)) & ENET_QOS_MAC_INDIR_ACCESS_CTRL_AUTO_MASK) + +#define ENET_QOS_MAC_INDIR_ACCESS_CTRL_AOFF_MASK (0xFF00U) +#define ENET_QOS_MAC_INDIR_ACCESS_CTRL_AOFF_SHIFT (8U) +/*! AOFF - Address Offset */ +#define ENET_QOS_MAC_INDIR_ACCESS_CTRL_AOFF(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INDIR_ACCESS_CTRL_AOFF_SHIFT)) & ENET_QOS_MAC_INDIR_ACCESS_CTRL_AOFF_MASK) + +#define ENET_QOS_MAC_INDIR_ACCESS_CTRL_MSEL_MASK (0xF0000U) +#define ENET_QOS_MAC_INDIR_ACCESS_CTRL_MSEL_SHIFT (16U) +/*! MSEL - Mode Select */ +#define ENET_QOS_MAC_INDIR_ACCESS_CTRL_MSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INDIR_ACCESS_CTRL_MSEL_SHIFT)) & ENET_QOS_MAC_INDIR_ACCESS_CTRL_MSEL_MASK) +/*! @} */ + +/*! @name MAC_INDIR_ACCESS_DATA - MAC_INDIR_ACCESS_DATA */ +/*! @{ */ + +#define ENET_QOS_MAC_INDIR_ACCESS_DATA_DATA_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_INDIR_ACCESS_DATA_DATA_SHIFT (0U) +/*! DATA - This field contains data to read/write for Indirect address access associated with MAC_INDIR_ACCESS_CTRL register. */ +#define ENET_QOS_MAC_INDIR_ACCESS_DATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INDIR_ACCESS_DATA_DATA_SHIFT)) & ENET_QOS_MAC_INDIR_ACCESS_DATA_DATA_MASK) +/*! @} */ + +/*! @name MAC_TIMESTAMP_CONTROL - Timestamp Control */ +/*! @{ */ + +#define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSENA_MASK (0x1U) +#define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSENA_SHIFT (0U) +/*! TSENA - Enable Timestamp When this bit is set, the timestamp is added for Transmit and Receive packets. + * 0b0..Timestamp is disabled + * 0b1..Timestamp is enabled + */ +#define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSENA(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_CONTROL_TSENA_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_CONTROL_TSENA_MASK) + +#define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSCFUPDT_MASK (0x2U) +#define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSCFUPDT_SHIFT (1U) +/*! TSCFUPDT - Fine or Coarse Timestamp Update When this bit is set, the Fine method is used to update system timestamp. + * 0b0..Coarse method is used to update system timestamp + * 0b1..Fine method is used to update system timestamp + */ +#define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSCFUPDT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_CONTROL_TSCFUPDT_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_CONTROL_TSCFUPDT_MASK) + +#define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSINIT_MASK (0x4U) +#define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSINIT_SHIFT (2U) +/*! TSINIT - Initialize Timestamp When this bit is set, the system time is initialized (overwritten) + * with the value specified in the MAC_System_Time_Seconds_Update and + * MAC_System_Time_Nanoseconds_Update registers. + * 0b0..Timestamp is not initialized + * 0b1..Timestamp is initialized + */ +#define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSINIT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_CONTROL_TSINIT_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_CONTROL_TSINIT_MASK) + +#define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSUPDT_MASK (0x8U) +#define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSUPDT_SHIFT (3U) +/*! TSUPDT - Update Timestamp When this bit is set, the system time is updated (added or subtracted) + * with the value specified in MAC_System_Time_Seconds_Update and + * MAC_System_Time_Nanoseconds_Update registers. + * 0b0..Timestamp is not updated + * 0b1..Timestamp is updated + */ +#define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSUPDT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_CONTROL_TSUPDT_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_CONTROL_TSUPDT_MASK) + +#define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSADDREG_MASK (0x20U) +#define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSADDREG_SHIFT (5U) +/*! TSADDREG - Update Addend Register When this bit is set, the content of the Timestamp Addend + * register is updated in the PTP block for fine correction. + * 0b0..Addend Register is not updated + * 0b1..Addend Register is updated + */ +#define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSADDREG(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_CONTROL_TSADDREG_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_CONTROL_TSADDREG_MASK) + +#define ENET_QOS_MAC_TIMESTAMP_CONTROL_PTGE_MASK (0x40U) +#define ENET_QOS_MAC_TIMESTAMP_CONTROL_PTGE_SHIFT (6U) +/*! PTGE - Presentation Time Generation Enable When this bit is set the Presentation Time generation will be enabled. + * 0b0..Presentation Time Generation is disabled + * 0b1..Presentation Time Generation is enabled + */ +#define ENET_QOS_MAC_TIMESTAMP_CONTROL_PTGE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_CONTROL_PTGE_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_CONTROL_PTGE_MASK) + +#define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSENALL_MASK (0x100U) +#define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSENALL_SHIFT (8U) +/*! TSENALL - Enable Timestamp for All Packets When this bit is set, the timestamp snapshot is + * enabled for all packets received by the MAC. + * 0b0..Timestamp for All Packets disabled + * 0b1..Timestamp for All Packets enabled + */ +#define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSENALL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_CONTROL_TSENALL_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_CONTROL_TSENALL_MASK) + +#define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSCTRLSSR_MASK (0x200U) +#define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSCTRLSSR_SHIFT (9U) +/*! TSCTRLSSR - Timestamp Digital or Binary Rollover Control When this bit is set, the Timestamp Low + * register rolls over after 0x3B9A_C9FF value (that is, 1 nanosecond accuracy) and increments + * the timestamp (High) seconds. + * 0b0..Timestamp Digital or Binary Rollover Control is disabled + * 0b1..Timestamp Digital or Binary Rollover Control is enabled + */ +#define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSCTRLSSR(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_CONTROL_TSCTRLSSR_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_CONTROL_TSCTRLSSR_MASK) + +#define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSVER2ENA_MASK (0x400U) +#define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSVER2ENA_SHIFT (10U) +/*! TSVER2ENA - Enable PTP Packet Processing for Version 2 Format When this bit is set, the IEEE + * 1588 version 2 format is used to process the PTP packets. + * 0b0..PTP Packet Processing for Version 2 Format is disabled + * 0b1..PTP Packet Processing for Version 2 Format is enabled + */ +#define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSVER2ENA(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_CONTROL_TSVER2ENA_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_CONTROL_TSVER2ENA_MASK) + +#define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSIPENA_MASK (0x800U) +#define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSIPENA_SHIFT (11U) +/*! TSIPENA - Enable Processing of PTP over Ethernet Packets When this bit is set, the MAC receiver + * processes the PTP packets encapsulated directly in the Ethernet packets. + * 0b0..Processing of PTP over Ethernet Packets is disabled + * 0b1..Processing of PTP over Ethernet Packets is enabled + */ +#define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSIPENA(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_CONTROL_TSIPENA_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_CONTROL_TSIPENA_MASK) + +#define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSIPV6ENA_MASK (0x1000U) +#define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSIPV6ENA_SHIFT (12U) +/*! TSIPV6ENA - Enable Processing of PTP Packets Sent over IPv6-UDP When this bit is set, the MAC + * receiver processes the PTP packets encapsulated in IPv6-UDP packets. + * 0b0..Processing of PTP Packets Sent over IPv6-UDP is disabled + * 0b1..Processing of PTP Packets Sent over IPv6-UDP is enabled + */ +#define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSIPV6ENA(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_CONTROL_TSIPV6ENA_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_CONTROL_TSIPV6ENA_MASK) + +#define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSIPV4ENA_MASK (0x2000U) +#define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSIPV4ENA_SHIFT (13U) +/*! TSIPV4ENA - Enable Processing of PTP Packets Sent over IPv4-UDP When this bit is set, the MAC + * receiver processes the PTP packets encapsulated in IPv4-UDP packets. + * 0b0..Processing of PTP Packets Sent over IPv4-UDP is disabled + * 0b1..Processing of PTP Packets Sent over IPv4-UDP is enabled + */ +#define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSIPV4ENA(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_CONTROL_TSIPV4ENA_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_CONTROL_TSIPV4ENA_MASK) + +#define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSEVNTENA_MASK (0x4000U) +#define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSEVNTENA_SHIFT (14U) +/*! TSEVNTENA - Enable Timestamp Snapshot for Event Messages When this bit is set, the timestamp + * snapshot is taken only for event messages (SYNC, Delay_Req, Pdelay_Req, or Pdelay_Resp). + * 0b0..Timestamp Snapshot for Event Messages is disabled + * 0b1..Timestamp Snapshot for Event Messages is enabled + */ +#define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSEVNTENA(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_CONTROL_TSEVNTENA_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_CONTROL_TSEVNTENA_MASK) + +#define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSMSTRENA_MASK (0x8000U) +#define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSMSTRENA_SHIFT (15U) +/*! TSMSTRENA - Enable Snapshot for Messages Relevant to Master When this bit is set, the snapshot + * is taken only for the messages that are relevant to the master node. + * 0b0..Snapshot for Messages Relevant to Master is disabled + * 0b1..Snapshot for Messages Relevant to Master is enabled + */ +#define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSMSTRENA(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_CONTROL_TSMSTRENA_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_CONTROL_TSMSTRENA_MASK) + +#define ENET_QOS_MAC_TIMESTAMP_CONTROL_SNAPTYPSEL_MASK (0x30000U) +#define ENET_QOS_MAC_TIMESTAMP_CONTROL_SNAPTYPSEL_SHIFT (16U) +/*! SNAPTYPSEL - Select PTP packets for Taking Snapshots These bits, along with Bits 15 and 14, + * decide the set of PTP packet types for which snapshot needs to be taken. + */ +#define ENET_QOS_MAC_TIMESTAMP_CONTROL_SNAPTYPSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_CONTROL_SNAPTYPSEL_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_CONTROL_SNAPTYPSEL_MASK) + +#define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSENMACADDR_MASK (0x40000U) +#define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSENMACADDR_SHIFT (18U) +/*! TSENMACADDR - Enable MAC Address for PTP Packet Filtering When this bit is set, the DA MAC + * address (that matches any MAC Address register) is used to filter the PTP packets when PTP is + * directly sent over Ethernet. + * 0b0..MAC Address for PTP Packet Filtering is disabled + * 0b1..MAC Address for PTP Packet Filtering is enabled + */ +#define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSENMACADDR(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_CONTROL_TSENMACADDR_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_CONTROL_TSENMACADDR_MASK) + +#define ENET_QOS_MAC_TIMESTAMP_CONTROL_CSC_MASK (0x80000U) +#define ENET_QOS_MAC_TIMESTAMP_CONTROL_CSC_SHIFT (19U) +/*! CSC - Enable checksum correction during OST for PTP over UDP/IPv4 packets When this bit is set, + * the last two bytes of PTP message sent over UDP/IPv4 is updated to keep the UDP checksum + * correct, for changes made to origin timestamp and/or correction field as part of one step timestamp + * operation. + * 0b0..checksum correction during OST for PTP over UDP/IPv4 packets is disabled + * 0b1..checksum correction during OST for PTP over UDP/IPv4 packets is enabled + */ +#define ENET_QOS_MAC_TIMESTAMP_CONTROL_CSC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_CONTROL_CSC_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_CONTROL_CSC_MASK) + +#define ENET_QOS_MAC_TIMESTAMP_CONTROL_ESTI_MASK (0x100000U) +#define ENET_QOS_MAC_TIMESTAMP_CONTROL_ESTI_SHIFT (20U) +/*! ESTI - External System Time Input When this bit is set, the MAC uses the external 64-bit + * reference System Time input for the following: - To take the timestamp provided as status - To insert + * the timestamp in transmit PTP packets when One-step Timestamp or Timestamp Offload feature is + * enabled. + * 0b0..External System Time Input is disabled + * 0b1..External System Time Input is enabled + */ +#define ENET_QOS_MAC_TIMESTAMP_CONTROL_ESTI(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_CONTROL_ESTI_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_CONTROL_ESTI_MASK) + +#define ENET_QOS_MAC_TIMESTAMP_CONTROL_TXTSSTSM_MASK (0x1000000U) +#define ENET_QOS_MAC_TIMESTAMP_CONTROL_TXTSSTSM_SHIFT (24U) +/*! TXTSSTSM - Transmit Timestamp Status Mode When this bit is set, the MAC overwrites the earlier + * transmit timestamp status even if it is not read by the software. + * 0b0..Transmit Timestamp Status Mode is disabled + * 0b1..Transmit Timestamp Status Mode is enabled + */ +#define ENET_QOS_MAC_TIMESTAMP_CONTROL_TXTSSTSM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_CONTROL_TXTSSTSM_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_CONTROL_TXTSSTSM_MASK) + +#define ENET_QOS_MAC_TIMESTAMP_CONTROL_AV8021ASMEN_MASK (0x10000000U) +#define ENET_QOS_MAC_TIMESTAMP_CONTROL_AV8021ASMEN_SHIFT (28U) +/*! AV8021ASMEN - AV 802. + * 0b0..AV 802.1AS Mode is disabled + * 0b1..AV 802.1AS Mode is enabled + */ +#define ENET_QOS_MAC_TIMESTAMP_CONTROL_AV8021ASMEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_CONTROL_AV8021ASMEN_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_CONTROL_AV8021ASMEN_MASK) +/*! @} */ + +/*! @name MAC_SUB_SECOND_INCREMENT - Subsecond Increment */ +/*! @{ */ + +#define ENET_QOS_MAC_SUB_SECOND_INCREMENT_SNSINC_MASK (0xFF00U) +#define ENET_QOS_MAC_SUB_SECOND_INCREMENT_SNSINC_SHIFT (8U) +/*! SNSINC - Sub-nanosecond Increment Value This field contains the sub-nanosecond increment value, + * represented in nanoseconds multiplied by 2^8. + */ +#define ENET_QOS_MAC_SUB_SECOND_INCREMENT_SNSINC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_SUB_SECOND_INCREMENT_SNSINC_SHIFT)) & ENET_QOS_MAC_SUB_SECOND_INCREMENT_SNSINC_MASK) + +#define ENET_QOS_MAC_SUB_SECOND_INCREMENT_SSINC_MASK (0xFF0000U) +#define ENET_QOS_MAC_SUB_SECOND_INCREMENT_SSINC_SHIFT (16U) +/*! SSINC - Sub-second Increment Value The value programmed in this field is accumulated every clock + * cycle (of clk_ptp_i) with the contents of the sub-second register. + */ +#define ENET_QOS_MAC_SUB_SECOND_INCREMENT_SSINC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_SUB_SECOND_INCREMENT_SSINC_SHIFT)) & ENET_QOS_MAC_SUB_SECOND_INCREMENT_SSINC_MASK) +/*! @} */ + +/*! @name MAC_SYSTEM_TIME_SECONDS - System Time Seconds */ +/*! @{ */ + +#define ENET_QOS_MAC_SYSTEM_TIME_SECONDS_TSS_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_SYSTEM_TIME_SECONDS_TSS_SHIFT (0U) +/*! TSS - Timestamp Second The value in this field indicates the current value in seconds of the + * System Time maintained by the MAC. + */ +#define ENET_QOS_MAC_SYSTEM_TIME_SECONDS_TSS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_SYSTEM_TIME_SECONDS_TSS_SHIFT)) & ENET_QOS_MAC_SYSTEM_TIME_SECONDS_TSS_MASK) +/*! @} */ + +/*! @name MAC_SYSTEM_TIME_NANOSECONDS - System Time Nanoseconds */ +/*! @{ */ + +#define ENET_QOS_MAC_SYSTEM_TIME_NANOSECONDS_TSSS_MASK (0x7FFFFFFFU) +#define ENET_QOS_MAC_SYSTEM_TIME_NANOSECONDS_TSSS_SHIFT (0U) +/*! TSSS - Timestamp Sub Seconds The value in this field has the sub-second representation of time, with an accuracy of 0. */ +#define ENET_QOS_MAC_SYSTEM_TIME_NANOSECONDS_TSSS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_SYSTEM_TIME_NANOSECONDS_TSSS_SHIFT)) & ENET_QOS_MAC_SYSTEM_TIME_NANOSECONDS_TSSS_MASK) +/*! @} */ + +/*! @name MAC_SYSTEM_TIME_SECONDS_UPDATE - System Time Seconds Update */ +/*! @{ */ + +#define ENET_QOS_MAC_SYSTEM_TIME_SECONDS_UPDATE_TSS_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_SYSTEM_TIME_SECONDS_UPDATE_TSS_SHIFT (0U) +/*! TSS - Timestamp Seconds The value in this field is the seconds part of the update. */ +#define ENET_QOS_MAC_SYSTEM_TIME_SECONDS_UPDATE_TSS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_SYSTEM_TIME_SECONDS_UPDATE_TSS_SHIFT)) & ENET_QOS_MAC_SYSTEM_TIME_SECONDS_UPDATE_TSS_MASK) +/*! @} */ + +/*! @name MAC_SYSTEM_TIME_NANOSECONDS_UPDATE - System Time Nanoseconds Update */ +/*! @{ */ + +#define ENET_QOS_MAC_SYSTEM_TIME_NANOSECONDS_UPDATE_TSSS_MASK (0x7FFFFFFFU) +#define ENET_QOS_MAC_SYSTEM_TIME_NANOSECONDS_UPDATE_TSSS_SHIFT (0U) +/*! TSSS - Timestamp Sub Seconds The value in this field is the sub-seconds part of the update. */ +#define ENET_QOS_MAC_SYSTEM_TIME_NANOSECONDS_UPDATE_TSSS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_SYSTEM_TIME_NANOSECONDS_UPDATE_TSSS_SHIFT)) & ENET_QOS_MAC_SYSTEM_TIME_NANOSECONDS_UPDATE_TSSS_MASK) + +#define ENET_QOS_MAC_SYSTEM_TIME_NANOSECONDS_UPDATE_ADDSUB_MASK (0x80000000U) +#define ENET_QOS_MAC_SYSTEM_TIME_NANOSECONDS_UPDATE_ADDSUB_SHIFT (31U) +/*! ADDSUB - Add or Subtract Time When this bit is set, the time value is subtracted with the contents of the update register. + * 0b0..Add time + * 0b1..Subtract time + */ +#define ENET_QOS_MAC_SYSTEM_TIME_NANOSECONDS_UPDATE_ADDSUB(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_SYSTEM_TIME_NANOSECONDS_UPDATE_ADDSUB_SHIFT)) & ENET_QOS_MAC_SYSTEM_TIME_NANOSECONDS_UPDATE_ADDSUB_MASK) +/*! @} */ + +/*! @name MAC_TIMESTAMP_ADDEND - Timestamp Addend */ +/*! @{ */ + +#define ENET_QOS_MAC_TIMESTAMP_ADDEND_TSAR_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_TIMESTAMP_ADDEND_TSAR_SHIFT (0U) +/*! TSAR - Timestamp Addend Register This field indicates the 32-bit time value to be added to the + * Accumulator register to achieve time synchronization. + */ +#define ENET_QOS_MAC_TIMESTAMP_ADDEND_TSAR(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_ADDEND_TSAR_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_ADDEND_TSAR_MASK) +/*! @} */ + +/*! @name MAC_SYSTEM_TIME_HIGHER_WORD_SECONDS - System Time - Higher Word Seconds */ +/*! @{ */ + +#define ENET_QOS_MAC_SYSTEM_TIME_HIGHER_WORD_SECONDS_TSHWR_MASK (0xFFFFU) +#define ENET_QOS_MAC_SYSTEM_TIME_HIGHER_WORD_SECONDS_TSHWR_SHIFT (0U) +/*! TSHWR - Timestamp Higher Word Register This field contains the most-significant 16-bits of timestamp seconds value. */ +#define ENET_QOS_MAC_SYSTEM_TIME_HIGHER_WORD_SECONDS_TSHWR(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_SYSTEM_TIME_HIGHER_WORD_SECONDS_TSHWR_SHIFT)) & ENET_QOS_MAC_SYSTEM_TIME_HIGHER_WORD_SECONDS_TSHWR_MASK) +/*! @} */ + +/*! @name MAC_TIMESTAMP_STATUS - Timestamp Status */ +/*! @{ */ + +#define ENET_QOS_MAC_TIMESTAMP_STATUS_TSSOVF_MASK (0x1U) +#define ENET_QOS_MAC_TIMESTAMP_STATUS_TSSOVF_SHIFT (0U) +/*! TSSOVF - Timestamp Seconds Overflow When this bit is set, it indicates that the seconds value of + * the timestamp (when supporting version 2 format) has overflowed beyond 32'hFFFF_FFFF. + * 0b0..Timestamp Seconds Overflow status not detected + * 0b1..Timestamp Seconds Overflow status detected + */ +#define ENET_QOS_MAC_TIMESTAMP_STATUS_TSSOVF(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_STATUS_TSSOVF_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_STATUS_TSSOVF_MASK) + +#define ENET_QOS_MAC_TIMESTAMP_STATUS_TSTARGT0_MASK (0x2U) +#define ENET_QOS_MAC_TIMESTAMP_STATUS_TSTARGT0_SHIFT (1U) +/*! TSTARGT0 - Timestamp Target Time Reached When set, this bit indicates that the value of system + * time is greater than or equal to the value specified in the MAC_PPS0_Target_Time_Seconds and + * MAC_PPS0_Target_Time_Nanoseconds registers. + * 0b0..Timestamp Target Time Reached status not detected + * 0b1..Timestamp Target Time Reached status detected + */ +#define ENET_QOS_MAC_TIMESTAMP_STATUS_TSTARGT0(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_STATUS_TSTARGT0_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_STATUS_TSTARGT0_MASK) + +#define ENET_QOS_MAC_TIMESTAMP_STATUS_AUXTSTRIG_MASK (0x4U) +#define ENET_QOS_MAC_TIMESTAMP_STATUS_AUXTSTRIG_SHIFT (2U) +/*! AUXTSTRIG - Auxiliary Timestamp Trigger Snapshot This bit is set high when the auxiliary snapshot is written to the FIFO. + * 0b0..Auxiliary Timestamp Trigger Snapshot status not detected + * 0b1..Auxiliary Timestamp Trigger Snapshot status detected + */ +#define ENET_QOS_MAC_TIMESTAMP_STATUS_AUXTSTRIG(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_STATUS_AUXTSTRIG_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_STATUS_AUXTSTRIG_MASK) + +#define ENET_QOS_MAC_TIMESTAMP_STATUS_TSTRGTERR0_MASK (0x8U) +#define ENET_QOS_MAC_TIMESTAMP_STATUS_TSTRGTERR0_SHIFT (3U) +/*! TSTRGTERR0 - Timestamp Target Time Error This bit is set when the latest target time programmed + * in the MAC_PPS0_Target_Time_Seconds and MAC_PPS0_Target_Time_Nanoseconds registers elapses. + * 0b0..Timestamp Target Time Error status not detected + * 0b1..Timestamp Target Time Error status detected + */ +#define ENET_QOS_MAC_TIMESTAMP_STATUS_TSTRGTERR0(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_STATUS_TSTRGTERR0_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_STATUS_TSTRGTERR0_MASK) + +#define ENET_QOS_MAC_TIMESTAMP_STATUS_TSTARGT1_MASK (0x10U) +#define ENET_QOS_MAC_TIMESTAMP_STATUS_TSTARGT1_SHIFT (4U) +/*! TSTARGT1 - Timestamp Target Time Reached for Target Time PPS1 When set, this bit indicates that + * the value of system time is greater than or equal to the value specified in the + * MAC_PPS1_TARGET_TIME_SECONDS and MAC_PPS1_TARGET_TIME_NANOSECONDS registers. + * 0b0..Timestamp Target Time Reached for Target Time PPS1 status not detected + * 0b1..Timestamp Target Time Reached for Target Time PPS1 status detected + */ +#define ENET_QOS_MAC_TIMESTAMP_STATUS_TSTARGT1(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_STATUS_TSTARGT1_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_STATUS_TSTARGT1_MASK) + +#define ENET_QOS_MAC_TIMESTAMP_STATUS_TSTRGTERR1_MASK (0x20U) +#define ENET_QOS_MAC_TIMESTAMP_STATUS_TSTRGTERR1_SHIFT (5U) +/*! TSTRGTERR1 - Timestamp Target Time Error This bit is set when the latest target time programmed + * in the MAC_PPS1_TARGET_TIME_SECONDS and MAC_PPS1_TARGET_TIME_NANOSECONDS registers elapses. + * 0b0..Timestamp Target Time Error status not detected + * 0b1..Timestamp Target Time Error status detected + */ +#define ENET_QOS_MAC_TIMESTAMP_STATUS_TSTRGTERR1(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_STATUS_TSTRGTERR1_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_STATUS_TSTRGTERR1_MASK) + +#define ENET_QOS_MAC_TIMESTAMP_STATUS_TSTARGT2_MASK (0x40U) +#define ENET_QOS_MAC_TIMESTAMP_STATUS_TSTARGT2_SHIFT (6U) +/*! TSTARGT2 - Timestamp Target Time Reached for Target Time PPS2 When set, this bit indicates that + * the value of system time is greater than or equal to the value specified in the + * MAC_PPS2_TARGET_TIME_SECONDS and MAC_PPS2_TARGET_TIME_NANOSECONDS registers. + * 0b0..Timestamp Target Time Reached for Target Time PPS2 status not detected + * 0b1..Timestamp Target Time Reached for Target Time PPS2 status detected + */ +#define ENET_QOS_MAC_TIMESTAMP_STATUS_TSTARGT2(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_STATUS_TSTARGT2_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_STATUS_TSTARGT2_MASK) + +#define ENET_QOS_MAC_TIMESTAMP_STATUS_TSTRGTERR2_MASK (0x80U) +#define ENET_QOS_MAC_TIMESTAMP_STATUS_TSTRGTERR2_SHIFT (7U) +/*! TSTRGTERR2 - Timestamp Target Time Error This bit is set when the latest target time programmed + * in the MAC_PPS2_TARGET_TIME_SECONDS and MAC_PPS2_TARGET_TIME_NANOSECONDS registers elapses. + * 0b0..Timestamp Target Time Error status not detected + * 0b1..Timestamp Target Time Error status detected + */ +#define ENET_QOS_MAC_TIMESTAMP_STATUS_TSTRGTERR2(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_STATUS_TSTRGTERR2_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_STATUS_TSTRGTERR2_MASK) + +#define ENET_QOS_MAC_TIMESTAMP_STATUS_TSTARGT3_MASK (0x100U) +#define ENET_QOS_MAC_TIMESTAMP_STATUS_TSTARGT3_SHIFT (8U) +/*! TSTARGT3 - Timestamp Target Time Reached for Target Time PPS3 When this bit is set, it indicates + * that the value of system time is greater than or equal to the value specified in the + * MAC_PPS3_TARGET_TIME_SECONDS and MAC_PPS3_TARGET_TIME_NANOSECONDS registers. + * 0b0..Timestamp Target Time Reached for Target Time PPS3 status not detected + * 0b1..Timestamp Target Time Reached for Target Time PPS3 status detected + */ +#define ENET_QOS_MAC_TIMESTAMP_STATUS_TSTARGT3(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_STATUS_TSTARGT3_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_STATUS_TSTARGT3_MASK) + +#define ENET_QOS_MAC_TIMESTAMP_STATUS_TSTRGTERR3_MASK (0x200U) +#define ENET_QOS_MAC_TIMESTAMP_STATUS_TSTRGTERR3_SHIFT (9U) +/*! TSTRGTERR3 - Timestamp Target Time Error This bit is set when the latest target time programmed + * in the MAC_PPS3_TARGET_TIME_SECONDS and MAC_PPS3_TARGET_TIME_NANOSECONDS registers elapses. + * 0b0..Timestamp Target Time Error status not detected + * 0b1..Timestamp Target Time Error status detected + */ +#define ENET_QOS_MAC_TIMESTAMP_STATUS_TSTRGTERR3(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_STATUS_TSTRGTERR3_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_STATUS_TSTRGTERR3_MASK) + +#define ENET_QOS_MAC_TIMESTAMP_STATUS_TXTSSIS_MASK (0x8000U) +#define ENET_QOS_MAC_TIMESTAMP_STATUS_TXTSSIS_SHIFT (15U) +/*! TXTSSIS - Tx Timestamp Status Interrupt Status In non-EQOS_CORE configurations when drop + * transmit status is enabled in MTL, this bit is set when the captured transmit timestamp is updated in + * the MAC_TX_TIMESTAMP_STATUS_NANOSECONDS and MAC_TX_TIMESTAMP_STATUS_SECONDS registers. + * 0b0..Tx Timestamp Status Interrupt status not detected + * 0b1..Tx Timestamp Status Interrupt status detected + */ +#define ENET_QOS_MAC_TIMESTAMP_STATUS_TXTSSIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_STATUS_TXTSSIS_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_STATUS_TXTSSIS_MASK) + +#define ENET_QOS_MAC_TIMESTAMP_STATUS_ATSSTN_MASK (0xF0000U) +#define ENET_QOS_MAC_TIMESTAMP_STATUS_ATSSTN_SHIFT (16U) +/*! ATSSTN - Auxiliary Timestamp Snapshot Trigger Identifier These bits identify the Auxiliary + * trigger inputs for which the timestamp available in the Auxiliary Snapshot Register is applicable. + */ +#define ENET_QOS_MAC_TIMESTAMP_STATUS_ATSSTN(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_STATUS_ATSSTN_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_STATUS_ATSSTN_MASK) + +#define ENET_QOS_MAC_TIMESTAMP_STATUS_ATSSTM_MASK (0x1000000U) +#define ENET_QOS_MAC_TIMESTAMP_STATUS_ATSSTM_SHIFT (24U) +/*! ATSSTM - Auxiliary Timestamp Snapshot Trigger Missed This bit is set when the Auxiliary + * timestamp snapshot FIFO is full and external trigger was set. + * 0b0..Auxiliary Timestamp Snapshot Trigger Missed status not detected + * 0b1..Auxiliary Timestamp Snapshot Trigger Missed status detected + */ +#define ENET_QOS_MAC_TIMESTAMP_STATUS_ATSSTM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_STATUS_ATSSTM_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_STATUS_ATSSTM_MASK) + +#define ENET_QOS_MAC_TIMESTAMP_STATUS_ATSNS_MASK (0x3E000000U) +#define ENET_QOS_MAC_TIMESTAMP_STATUS_ATSNS_SHIFT (25U) +/*! ATSNS - Number of Auxiliary Timestamp Snapshots This field indicates the number of Snapshots available in the FIFO. */ +#define ENET_QOS_MAC_TIMESTAMP_STATUS_ATSNS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_STATUS_ATSNS_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_STATUS_ATSNS_MASK) +/*! @} */ + +/*! @name MAC_TX_TIMESTAMP_STATUS_NANOSECONDS - Transmit Timestamp Status Nanoseconds */ +/*! @{ */ + +#define ENET_QOS_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSLO_MASK (0x7FFFFFFFU) +#define ENET_QOS_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSLO_SHIFT (0U) +/*! TXTSSLO - Transmit Timestamp Status Low This field contains the 31 bits of the Nanoseconds field + * of the Transmit packet's captured timestamp. + */ +#define ENET_QOS_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSLO(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSLO_SHIFT)) & ENET_QOS_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSLO_MASK) + +#define ENET_QOS_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSMIS_MASK (0x80000000U) +#define ENET_QOS_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSMIS_SHIFT (31U) +/*! TXTSSMIS - Transmit Timestamp Status Missed + * 0b0..Transmit Timestamp Status Missed status not detected + * 0b1..Transmit Timestamp Status Missed status detected + */ +#define ENET_QOS_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSMIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSMIS_SHIFT)) & ENET_QOS_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSMIS_MASK) +/*! @} */ + +/*! @name MAC_TX_TIMESTAMP_STATUS_SECONDS - Transmit Timestamp Status Seconds */ +/*! @{ */ + +#define ENET_QOS_MAC_TX_TIMESTAMP_STATUS_SECONDS_TXTSSHI_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_TX_TIMESTAMP_STATUS_SECONDS_TXTSSHI_SHIFT (0U) +/*! TXTSSHI - Transmit Timestamp Status High This field contains the lower 32 bits of the Seconds + * field of Transmit packet's captured timestamp. + */ +#define ENET_QOS_MAC_TX_TIMESTAMP_STATUS_SECONDS_TXTSSHI(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_TIMESTAMP_STATUS_SECONDS_TXTSSHI_SHIFT)) & ENET_QOS_MAC_TX_TIMESTAMP_STATUS_SECONDS_TXTSSHI_MASK) +/*! @} */ + +/*! @name MAC_AUXILIARY_CONTROL - Auxiliary Timestamp Control */ +/*! @{ */ + +#define ENET_QOS_MAC_AUXILIARY_CONTROL_ATSFC_MASK (0x1U) +#define ENET_QOS_MAC_AUXILIARY_CONTROL_ATSFC_SHIFT (0U) +/*! ATSFC - Auxiliary Snapshot FIFO Clear + * 0b0..Auxiliary Snapshot FIFO Clear is disabled + * 0b1..Auxiliary Snapshot FIFO Clear is enabled + */ +#define ENET_QOS_MAC_AUXILIARY_CONTROL_ATSFC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_AUXILIARY_CONTROL_ATSFC_SHIFT)) & ENET_QOS_MAC_AUXILIARY_CONTROL_ATSFC_MASK) + +#define ENET_QOS_MAC_AUXILIARY_CONTROL_ATSEN0_MASK (0x10U) +#define ENET_QOS_MAC_AUXILIARY_CONTROL_ATSEN0_SHIFT (4U) +/*! ATSEN0 - Auxiliary Snapshot 0 Enable + * 0b0..Auxiliary Snapshot $i is disabled + * 0b1..Auxiliary Snapshot $i is enabled + */ +#define ENET_QOS_MAC_AUXILIARY_CONTROL_ATSEN0(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_AUXILIARY_CONTROL_ATSEN0_SHIFT)) & ENET_QOS_MAC_AUXILIARY_CONTROL_ATSEN0_MASK) + +#define ENET_QOS_MAC_AUXILIARY_CONTROL_ATSEN1_MASK (0x20U) +#define ENET_QOS_MAC_AUXILIARY_CONTROL_ATSEN1_SHIFT (5U) +/*! ATSEN1 - Auxiliary Snapshot 1 Enable + * 0b0..Auxiliary Snapshot $i is disabled + * 0b1..Auxiliary Snapshot $i is enabled + */ +#define ENET_QOS_MAC_AUXILIARY_CONTROL_ATSEN1(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_AUXILIARY_CONTROL_ATSEN1_SHIFT)) & ENET_QOS_MAC_AUXILIARY_CONTROL_ATSEN1_MASK) + +#define ENET_QOS_MAC_AUXILIARY_CONTROL_ATSEN2_MASK (0x40U) +#define ENET_QOS_MAC_AUXILIARY_CONTROL_ATSEN2_SHIFT (6U) +/*! ATSEN2 - Auxiliary Snapshot 2 Enable + * 0b0..Auxiliary Snapshot $i is disabled + * 0b1..Auxiliary Snapshot $i is enabled + */ +#define ENET_QOS_MAC_AUXILIARY_CONTROL_ATSEN2(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_AUXILIARY_CONTROL_ATSEN2_SHIFT)) & ENET_QOS_MAC_AUXILIARY_CONTROL_ATSEN2_MASK) + +#define ENET_QOS_MAC_AUXILIARY_CONTROL_ATSEN3_MASK (0x80U) +#define ENET_QOS_MAC_AUXILIARY_CONTROL_ATSEN3_SHIFT (7U) +/*! ATSEN3 - Auxiliary Snapshot 3 Enable + * 0b0..Auxiliary Snapshot $i is disabled + * 0b1..Auxiliary Snapshot $i is enabled + */ +#define ENET_QOS_MAC_AUXILIARY_CONTROL_ATSEN3(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_AUXILIARY_CONTROL_ATSEN3_SHIFT)) & ENET_QOS_MAC_AUXILIARY_CONTROL_ATSEN3_MASK) +/*! @} */ + +/*! @name MAC_AUXILIARY_TIMESTAMP_NANOSECONDS - Auxiliary Timestamp Nanoseconds */ +/*! @{ */ + +#define ENET_QOS_MAC_AUXILIARY_TIMESTAMP_NANOSECONDS_AUXTSLO_MASK (0x7FFFFFFFU) +#define ENET_QOS_MAC_AUXILIARY_TIMESTAMP_NANOSECONDS_AUXTSLO_SHIFT (0U) +/*! AUXTSLO - Auxiliary Timestamp Contains the lower 31 bits (nanoseconds field) of the auxiliary timestamp. */ +#define ENET_QOS_MAC_AUXILIARY_TIMESTAMP_NANOSECONDS_AUXTSLO(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_AUXILIARY_TIMESTAMP_NANOSECONDS_AUXTSLO_SHIFT)) & ENET_QOS_MAC_AUXILIARY_TIMESTAMP_NANOSECONDS_AUXTSLO_MASK) +/*! @} */ + +/*! @name MAC_AUXILIARY_TIMESTAMP_SECONDS - Auxiliary Timestamp Seconds */ +/*! @{ */ + +#define ENET_QOS_MAC_AUXILIARY_TIMESTAMP_SECONDS_AUXTSHI_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_AUXILIARY_TIMESTAMP_SECONDS_AUXTSHI_SHIFT (0U) +/*! AUXTSHI - Auxiliary Timestamp Contains the lower 32 bits of the Seconds field of the auxiliary timestamp. */ +#define ENET_QOS_MAC_AUXILIARY_TIMESTAMP_SECONDS_AUXTSHI(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_AUXILIARY_TIMESTAMP_SECONDS_AUXTSHI_SHIFT)) & ENET_QOS_MAC_AUXILIARY_TIMESTAMP_SECONDS_AUXTSHI_MASK) +/*! @} */ + +/*! @name MAC_TIMESTAMP_INGRESS_ASYM_CORR - Timestamp Ingress Asymmetry Correction */ +/*! @{ */ + +#define ENET_QOS_MAC_TIMESTAMP_INGRESS_ASYM_CORR_OSTIAC_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_TIMESTAMP_INGRESS_ASYM_CORR_OSTIAC_SHIFT (0U) +/*! OSTIAC - One-Step Timestamp Ingress Asymmetry Correction */ +#define ENET_QOS_MAC_TIMESTAMP_INGRESS_ASYM_CORR_OSTIAC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_INGRESS_ASYM_CORR_OSTIAC_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_INGRESS_ASYM_CORR_OSTIAC_MASK) +/*! @} */ + +/*! @name MAC_TIMESTAMP_EGRESS_ASYM_CORR - Timestamp Egress Asymmetry Correction */ +/*! @{ */ + +#define ENET_QOS_MAC_TIMESTAMP_EGRESS_ASYM_CORR_OSTEAC_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_TIMESTAMP_EGRESS_ASYM_CORR_OSTEAC_SHIFT (0U) +/*! OSTEAC - One-Step Timestamp Egress Asymmetry Correction */ +#define ENET_QOS_MAC_TIMESTAMP_EGRESS_ASYM_CORR_OSTEAC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_EGRESS_ASYM_CORR_OSTEAC_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_EGRESS_ASYM_CORR_OSTEAC_MASK) +/*! @} */ + +/*! @name MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND - Timestamp Ingress Correction Nanosecond */ +/*! @{ */ + +#define ENET_QOS_MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND_TSIC_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND_TSIC_SHIFT (0U) +/*! TSIC - Timestamp Ingress Correction This field contains the ingress path correction value as + * defined by the Ingress Correction expression. + */ +#define ENET_QOS_MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND_TSIC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND_TSIC_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND_TSIC_MASK) +/*! @} */ + +/*! @name MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND - Timestamp Egress Correction Nanosecond */ +/*! @{ */ + +#define ENET_QOS_MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND_TSEC_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND_TSEC_SHIFT (0U) +/*! TSEC - Timestamp Egress Correction This field contains the nanoseconds part of the egress path + * correction value as defined by the Egress Correction expression. + */ +#define ENET_QOS_MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND_TSEC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND_TSEC_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND_TSEC_MASK) +/*! @} */ + +/*! @name MAC_TIMESTAMP_INGRESS_CORR_SUBNANOSEC - Timestamp Ingress Correction Subnanosecond */ +/*! @{ */ + +#define ENET_QOS_MAC_TIMESTAMP_INGRESS_CORR_SUBNANOSEC_TSICSNS_MASK (0xFF00U) +#define ENET_QOS_MAC_TIMESTAMP_INGRESS_CORR_SUBNANOSEC_TSICSNS_SHIFT (8U) +/*! TSICSNS - Timestamp Ingress Correction, sub-nanoseconds This field contains the sub-nanoseconds + * part of the ingress path correction value as defined by the "Ingress Correction" expression. + */ +#define ENET_QOS_MAC_TIMESTAMP_INGRESS_CORR_SUBNANOSEC_TSICSNS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_INGRESS_CORR_SUBNANOSEC_TSICSNS_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_INGRESS_CORR_SUBNANOSEC_TSICSNS_MASK) +/*! @} */ + +/*! @name MAC_TIMESTAMP_EGRESS_CORR_SUBNANOSEC - Timestamp Egress Correction Subnanosecond */ +/*! @{ */ + +#define ENET_QOS_MAC_TIMESTAMP_EGRESS_CORR_SUBNANOSEC_TSECSNS_MASK (0xFF00U) +#define ENET_QOS_MAC_TIMESTAMP_EGRESS_CORR_SUBNANOSEC_TSECSNS_SHIFT (8U) +/*! TSECSNS - Timestamp Egress Correction, sub-nanoseconds This field contains the sub-nanoseconds + * part of the egress path correction value as defined by the "Egress Correction" expression. + */ +#define ENET_QOS_MAC_TIMESTAMP_EGRESS_CORR_SUBNANOSEC_TSECSNS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_EGRESS_CORR_SUBNANOSEC_TSECSNS_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_EGRESS_CORR_SUBNANOSEC_TSECSNS_MASK) +/*! @} */ + +/*! @name MAC_TIMESTAMP_INGRESS_LATENCY - Timestamp Ingress Latency */ +/*! @{ */ + +#define ENET_QOS_MAC_TIMESTAMP_INGRESS_LATENCY_ITLSNS_MASK (0xFF00U) +#define ENET_QOS_MAC_TIMESTAMP_INGRESS_LATENCY_ITLSNS_SHIFT (8U) +/*! ITLSNS - Ingress Timestamp Latency, in nanoseconds */ +#define ENET_QOS_MAC_TIMESTAMP_INGRESS_LATENCY_ITLSNS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_INGRESS_LATENCY_ITLSNS_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_INGRESS_LATENCY_ITLSNS_MASK) + +#define ENET_QOS_MAC_TIMESTAMP_INGRESS_LATENCY_ITLNS_MASK (0xFFF0000U) +#define ENET_QOS_MAC_TIMESTAMP_INGRESS_LATENCY_ITLNS_SHIFT (16U) +/*! ITLNS - Ingress Timestamp Latency, in sub-nanoseconds */ +#define ENET_QOS_MAC_TIMESTAMP_INGRESS_LATENCY_ITLNS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_INGRESS_LATENCY_ITLNS_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_INGRESS_LATENCY_ITLNS_MASK) +/*! @} */ + +/*! @name MAC_TIMESTAMP_EGRESS_LATENCY - Timestamp Egress Latency */ +/*! @{ */ + +#define ENET_QOS_MAC_TIMESTAMP_EGRESS_LATENCY_ETLSNS_MASK (0xFF00U) +#define ENET_QOS_MAC_TIMESTAMP_EGRESS_LATENCY_ETLSNS_SHIFT (8U) +/*! ETLSNS - Egress Timestamp Latency, in sub-nanoseconds */ +#define ENET_QOS_MAC_TIMESTAMP_EGRESS_LATENCY_ETLSNS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_EGRESS_LATENCY_ETLSNS_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_EGRESS_LATENCY_ETLSNS_MASK) + +#define ENET_QOS_MAC_TIMESTAMP_EGRESS_LATENCY_ETLNS_MASK (0xFFF0000U) +#define ENET_QOS_MAC_TIMESTAMP_EGRESS_LATENCY_ETLNS_SHIFT (16U) +/*! ETLNS - Egress Timestamp Latency, in nanoseconds */ +#define ENET_QOS_MAC_TIMESTAMP_EGRESS_LATENCY_ETLNS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_EGRESS_LATENCY_ETLNS_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_EGRESS_LATENCY_ETLNS_MASK) +/*! @} */ + +/*! @name MAC_PPS_CONTROL - PPS Control */ +/*! @{ */ + +#define ENET_QOS_MAC_PPS_CONTROL_PPSCTRL_PPSCMD_MASK (0xFU) +#define ENET_QOS_MAC_PPS_CONTROL_PPSCTRL_PPSCMD_SHIFT (0U) +/*! PPSCTRL_PPSCMD - PPS Output Frequency Control This field controls the frequency of the PPS0 output (ptp_pps_o[0]) signal. */ +#define ENET_QOS_MAC_PPS_CONTROL_PPSCTRL_PPSCMD(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS_CONTROL_PPSCTRL_PPSCMD_SHIFT)) & ENET_QOS_MAC_PPS_CONTROL_PPSCTRL_PPSCMD_MASK) + +#define ENET_QOS_MAC_PPS_CONTROL_PPSEN0_MASK (0x10U) +#define ENET_QOS_MAC_PPS_CONTROL_PPSEN0_SHIFT (4U) +/*! PPSEN0 - Flexible PPS Output Mode Enable When this bit is set, Bits[3:0] function as PPSCMD. + * 0b0..Flexible PPS Output Mode is disabled + * 0b1..Flexible PPS Output Mode is enabled + */ +#define ENET_QOS_MAC_PPS_CONTROL_PPSEN0(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS_CONTROL_PPSEN0_SHIFT)) & ENET_QOS_MAC_PPS_CONTROL_PPSEN0_MASK) + +#define ENET_QOS_MAC_PPS_CONTROL_TRGTMODSEL0_MASK (0x60U) +#define ENET_QOS_MAC_PPS_CONTROL_TRGTMODSEL0_SHIFT (5U) +/*! TRGTMODSEL0 - Target Time Register Mode for PPS0 Output This field indicates the Target Time + * registers (MAC_PPS0_TARGET_TIME_SECONDS and MAC_PPS0_TARGET_TIME_NANOSECONDS) mode for PPS0 + * output signal: + * 0b00..Target Time registers are programmed only for generating the interrupt event. The Flexible PPS function + * must not be enabled in this mode, otherwise spurious transitions may be observed on the corresponding + * ptp_pps_o output port + * 0b01..Reserved + * 0b10..Target Time registers are programmed for generating the interrupt event and starting or stopping the PPS0 output signal generation + * 0b11..Target Time registers are programmed only for starting or stopping the PPS0 output signal generation. No interrupt is asserted + */ +#define ENET_QOS_MAC_PPS_CONTROL_TRGTMODSEL0(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS_CONTROL_TRGTMODSEL0_SHIFT)) & ENET_QOS_MAC_PPS_CONTROL_TRGTMODSEL0_MASK) + +#define ENET_QOS_MAC_PPS_CONTROL_MCGREN0_MASK (0x80U) +#define ENET_QOS_MAC_PPS_CONTROL_MCGREN0_SHIFT (7U) +/*! MCGREN0 - MCGR Mode Enable for PPS0 Output This field enables the 0th PPS instance to operate in PPS or MCGR mode. + * 0b0..0th PPS instance is enabled to operate in PPS mode + * 0b1..0th PPS instance is enabled to operate in MCGR mode + */ +#define ENET_QOS_MAC_PPS_CONTROL_MCGREN0(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS_CONTROL_MCGREN0_SHIFT)) & ENET_QOS_MAC_PPS_CONTROL_MCGREN0_MASK) + +#define ENET_QOS_MAC_PPS_CONTROL_PPSCMD1_MASK (0xF00U) +#define ENET_QOS_MAC_PPS_CONTROL_PPSCMD1_SHIFT (8U) +/*! PPSCMD1 - Flexible PPS1 Output Control This field controls the flexible PPS1 output (ptp_pps_o[1]) signal. */ +#define ENET_QOS_MAC_PPS_CONTROL_PPSCMD1(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS_CONTROL_PPSCMD1_SHIFT)) & ENET_QOS_MAC_PPS_CONTROL_PPSCMD1_MASK) + +#define ENET_QOS_MAC_PPS_CONTROL_TRGTMODSEL1_MASK (0x6000U) +#define ENET_QOS_MAC_PPS_CONTROL_TRGTMODSEL1_SHIFT (13U) +/*! TRGTMODSEL1 - Target Time Register Mode for PPS1 Output This field indicates the Target Time + * registers (MAC_PPS1_TARGET_TIME_SECONDS and MAC_PPS1_TARGET_TIME_NANOSECONDS) mode for PPS1 + * output signal. + * 0b00..Target Time registers are programmed only for generating the interrupt event. The Flexible PPS function + * must not be enabled in this mode, otherwise spurious transitions may be observed on the corresponding + * ptp_pps_o output port + * 0b01..Reserved + * 0b10..Target Time registers are programmed for generating the interrupt event and starting or stopping the PPS0 output signal generation + * 0b11..Target Time registers are programmed only for starting or stopping the PPS0 output signal generation. No interrupt is asserted + */ +#define ENET_QOS_MAC_PPS_CONTROL_TRGTMODSEL1(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS_CONTROL_TRGTMODSEL1_SHIFT)) & ENET_QOS_MAC_PPS_CONTROL_TRGTMODSEL1_MASK) + +#define ENET_QOS_MAC_PPS_CONTROL_MCGREN1_MASK (0x8000U) +#define ENET_QOS_MAC_PPS_CONTROL_MCGREN1_SHIFT (15U) +/*! MCGREN1 - MCGR Mode Enable for PPS1 Output This field enables the 1st PPS instance to operate in PPS or MCGR mode. + * 0b0..1st PPS instance is disabled to operate in PPS or MCGR mode + * 0b1..1st PPS instance is enabled to operate in PPS or MCGR mode + */ +#define ENET_QOS_MAC_PPS_CONTROL_MCGREN1(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS_CONTROL_MCGREN1_SHIFT)) & ENET_QOS_MAC_PPS_CONTROL_MCGREN1_MASK) + +#define ENET_QOS_MAC_PPS_CONTROL_PPSCMD2_MASK (0xF0000U) +#define ENET_QOS_MAC_PPS_CONTROL_PPSCMD2_SHIFT (16U) +/*! PPSCMD2 - Flexible PPS2 Output Control This field controls the flexible PPS2 output (ptp_pps_o[2]) signal. */ +#define ENET_QOS_MAC_PPS_CONTROL_PPSCMD2(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS_CONTROL_PPSCMD2_SHIFT)) & ENET_QOS_MAC_PPS_CONTROL_PPSCMD2_MASK) + +#define ENET_QOS_MAC_PPS_CONTROL_TRGTMODSEL2_MASK (0x600000U) +#define ENET_QOS_MAC_PPS_CONTROL_TRGTMODSEL2_SHIFT (21U) +/*! TRGTMODSEL2 - Target Time Register Mode for PPS2 Output This field indicates the Target Time + * registers (MAC_PPS2_TARGET_TIME_SECONDS and MAC_PPS2_TARGET_TIME_NANOSECONDS) mode for PPS2 + * output signal. + * 0b00..Target Time registers are programmed only for generating the interrupt event. The Flexible PPS function + * must not be enabled in this mode, otherwise spurious transitions may be observed on the corresponding + * ptp_pps_o output port + * 0b01..Reserved + * 0b10..Target Time registers are programmed for generating the interrupt event and starting or stopping the PPS0 output signal generation + * 0b11..Target Time registers are programmed only for starting or stopping the PPS0 output signal generation. No interrupt is asserted + */ +#define ENET_QOS_MAC_PPS_CONTROL_TRGTMODSEL2(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS_CONTROL_TRGTMODSEL2_SHIFT)) & ENET_QOS_MAC_PPS_CONTROL_TRGTMODSEL2_MASK) + +#define ENET_QOS_MAC_PPS_CONTROL_MCGREN2_MASK (0x800000U) +#define ENET_QOS_MAC_PPS_CONTROL_MCGREN2_SHIFT (23U) +/*! MCGREN2 - MCGR Mode Enable for PPS2 Output This field enables the 2nd PPS instance to operate in PPS or MCGR mode. + * 0b0..2nd PPS instance is disabled to operate in PPS or MCGR mode + * 0b1..2nd PPS instance is enabled to operate in PPS or MCGR mode + */ +#define ENET_QOS_MAC_PPS_CONTROL_MCGREN2(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS_CONTROL_MCGREN2_SHIFT)) & ENET_QOS_MAC_PPS_CONTROL_MCGREN2_MASK) + +#define ENET_QOS_MAC_PPS_CONTROL_PPSCMD3_MASK (0xF000000U) +#define ENET_QOS_MAC_PPS_CONTROL_PPSCMD3_SHIFT (24U) +/*! PPSCMD3 - Flexible PPS3 Output Control This field controls the flexible PPS3 output (ptp_pps_o[3]) signal. */ +#define ENET_QOS_MAC_PPS_CONTROL_PPSCMD3(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS_CONTROL_PPSCMD3_SHIFT)) & ENET_QOS_MAC_PPS_CONTROL_PPSCMD3_MASK) + +#define ENET_QOS_MAC_PPS_CONTROL_TRGTMODSEL3_MASK (0x60000000U) +#define ENET_QOS_MAC_PPS_CONTROL_TRGTMODSEL3_SHIFT (29U) +/*! TRGTMODSEL3 - Target Time Register Mode for PPS3 Output This field indicates the Target Time + * registers (MAC_PPS3_TARGET_TIME_SECONDS and MAC_PPS3_TARGET_TIME_NANOSECONDS) mode for PPS3 + * output signal. + * 0b00..Target Time registers are programmed only for generating the interrupt event. The Flexible PPS function + * must not be enabled in this mode, otherwise spurious transitions may be observed on the corresponding + * ptp_pps_o output port + * 0b01..Reserved + * 0b10..Target Time registers are programmed for generating the interrupt event and starting or stopping the PPS0 output signal generation + * 0b11..Target Time registers are programmed only for starting or stopping the PPS0 output signal generation. No interrupt is asserted + */ +#define ENET_QOS_MAC_PPS_CONTROL_TRGTMODSEL3(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS_CONTROL_TRGTMODSEL3_SHIFT)) & ENET_QOS_MAC_PPS_CONTROL_TRGTMODSEL3_MASK) + +#define ENET_QOS_MAC_PPS_CONTROL_MCGREN3_MASK (0x80000000U) +#define ENET_QOS_MAC_PPS_CONTROL_MCGREN3_SHIFT (31U) +/*! MCGREN3 - MCGR Mode Enable for PPS3 Output This field enables the 3rd PPS instance to operate in PPS or MCGR mode. */ +#define ENET_QOS_MAC_PPS_CONTROL_MCGREN3(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS_CONTROL_MCGREN3_SHIFT)) & ENET_QOS_MAC_PPS_CONTROL_MCGREN3_MASK) +/*! @} */ + +/*! @name MAC_PPS0_TARGET_TIME_SECONDS - PPS0 Target Time Seconds */ +/*! @{ */ + +#define ENET_QOS_MAC_PPS0_TARGET_TIME_SECONDS_TSTRH0_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_PPS0_TARGET_TIME_SECONDS_TSTRH0_SHIFT (0U) +/*! TSTRH0 - PPS Target Time Seconds Register This field stores the time in seconds. */ +#define ENET_QOS_MAC_PPS0_TARGET_TIME_SECONDS_TSTRH0(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS0_TARGET_TIME_SECONDS_TSTRH0_SHIFT)) & ENET_QOS_MAC_PPS0_TARGET_TIME_SECONDS_TSTRH0_MASK) +/*! @} */ + +/*! @name MAC_PPS0_TARGET_TIME_NANOSECONDS - PPS0 Target Time Nanoseconds */ +/*! @{ */ + +#define ENET_QOS_MAC_PPS0_TARGET_TIME_NANOSECONDS_TTSL0_MASK (0x7FFFFFFFU) +#define ENET_QOS_MAC_PPS0_TARGET_TIME_NANOSECONDS_TTSL0_SHIFT (0U) +/*! TTSL0 - Target Time Low for PPS Register This register stores the time in (signed) nanoseconds. */ +#define ENET_QOS_MAC_PPS0_TARGET_TIME_NANOSECONDS_TTSL0(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS0_TARGET_TIME_NANOSECONDS_TTSL0_SHIFT)) & ENET_QOS_MAC_PPS0_TARGET_TIME_NANOSECONDS_TTSL0_MASK) + +#define ENET_QOS_MAC_PPS0_TARGET_TIME_NANOSECONDS_TRGTBUSY0_MASK (0x80000000U) +#define ENET_QOS_MAC_PPS0_TARGET_TIME_NANOSECONDS_TRGTBUSY0_SHIFT (31U) +/*! TRGTBUSY0 - PPS Target Time Register Busy The MAC sets this bit when the PPSCMD0 field in the + * PPS_CONTROL register is programmed to 010 or 011. + * 0b0..PPS Target Time Register Busy status is not detected + * 0b1..PPS Target Time Register Busy is detected + */ +#define ENET_QOS_MAC_PPS0_TARGET_TIME_NANOSECONDS_TRGTBUSY0(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS0_TARGET_TIME_NANOSECONDS_TRGTBUSY0_SHIFT)) & ENET_QOS_MAC_PPS0_TARGET_TIME_NANOSECONDS_TRGTBUSY0_MASK) +/*! @} */ + +/*! @name MAC_PPS0_INTERVAL - PPS0 Interval */ +/*! @{ */ + +#define ENET_QOS_MAC_PPS0_INTERVAL_PPSINT0_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_PPS0_INTERVAL_PPSINT0_SHIFT (0U) +/*! PPSINT0 - PPS Output Signal Interval These bits store the interval between the rising edges of PPS0 signal output. */ +#define ENET_QOS_MAC_PPS0_INTERVAL_PPSINT0(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS0_INTERVAL_PPSINT0_SHIFT)) & ENET_QOS_MAC_PPS0_INTERVAL_PPSINT0_MASK) +/*! @} */ + +/*! @name MAC_PPS0_WIDTH - PPS0 Width */ +/*! @{ */ + +#define ENET_QOS_MAC_PPS0_WIDTH_PPSWIDTH0_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_PPS0_WIDTH_PPSWIDTH0_SHIFT (0U) +/*! PPSWIDTH0 - PPS Output Signal Width These bits store the width between the rising edge and + * corresponding falling edge of PPS0 signal output. + */ +#define ENET_QOS_MAC_PPS0_WIDTH_PPSWIDTH0(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS0_WIDTH_PPSWIDTH0_SHIFT)) & ENET_QOS_MAC_PPS0_WIDTH_PPSWIDTH0_MASK) +/*! @} */ + +/*! @name MAC_PPS1_TARGET_TIME_SECONDS - PPS1 Target Time Seconds */ +/*! @{ */ + +#define ENET_QOS_MAC_PPS1_TARGET_TIME_SECONDS_TSTRH1_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_PPS1_TARGET_TIME_SECONDS_TSTRH1_SHIFT (0U) +/*! TSTRH1 - PPS Target Time Seconds Register This field stores the time in seconds. */ +#define ENET_QOS_MAC_PPS1_TARGET_TIME_SECONDS_TSTRH1(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS1_TARGET_TIME_SECONDS_TSTRH1_SHIFT)) & ENET_QOS_MAC_PPS1_TARGET_TIME_SECONDS_TSTRH1_MASK) +/*! @} */ + +/*! @name MAC_PPS1_TARGET_TIME_NANOSECONDS - PPS1 Target Time Nanoseconds */ +/*! @{ */ + +#define ENET_QOS_MAC_PPS1_TARGET_TIME_NANOSECONDS_TTSL1_MASK (0x7FFFFFFFU) +#define ENET_QOS_MAC_PPS1_TARGET_TIME_NANOSECONDS_TTSL1_SHIFT (0U) +/*! TTSL1 - Target Time Low for PPS Register This register stores the time in (signed) nanoseconds. */ +#define ENET_QOS_MAC_PPS1_TARGET_TIME_NANOSECONDS_TTSL1(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS1_TARGET_TIME_NANOSECONDS_TTSL1_SHIFT)) & ENET_QOS_MAC_PPS1_TARGET_TIME_NANOSECONDS_TTSL1_MASK) + +#define ENET_QOS_MAC_PPS1_TARGET_TIME_NANOSECONDS_TRGTBUSY1_MASK (0x80000000U) +#define ENET_QOS_MAC_PPS1_TARGET_TIME_NANOSECONDS_TRGTBUSY1_SHIFT (31U) +/*! TRGTBUSY1 - PPS Target Time Register Busy The MAC sets this bit when the PPSCMD0 field in the + * PPS_CONTROL register is programmed to 010 or 011. + * 0b0..PPS Target Time Register Busy status is not detected + * 0b1..PPS Target Time Register Busy is detected + */ +#define ENET_QOS_MAC_PPS1_TARGET_TIME_NANOSECONDS_TRGTBUSY1(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS1_TARGET_TIME_NANOSECONDS_TRGTBUSY1_SHIFT)) & ENET_QOS_MAC_PPS1_TARGET_TIME_NANOSECONDS_TRGTBUSY1_MASK) +/*! @} */ + +/*! @name MAC_PPS1_INTERVAL - PPS1 Interval */ +/*! @{ */ + +#define ENET_QOS_MAC_PPS1_INTERVAL_PPSINT1_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_PPS1_INTERVAL_PPSINT1_SHIFT (0U) +/*! PPSINT1 - PPS Output Signal Interval These bits store the interval between the rising edges of PPS1 signal output. */ +#define ENET_QOS_MAC_PPS1_INTERVAL_PPSINT1(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS1_INTERVAL_PPSINT1_SHIFT)) & ENET_QOS_MAC_PPS1_INTERVAL_PPSINT1_MASK) +/*! @} */ + +/*! @name MAC_PPS1_WIDTH - PPS1 Width */ +/*! @{ */ + +#define ENET_QOS_MAC_PPS1_WIDTH_PPSWIDTH1_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_PPS1_WIDTH_PPSWIDTH1_SHIFT (0U) +/*! PPSWIDTH1 - PPS Output Signal Width These bits store the width between the rising edge and + * corresponding falling edge of PPS0 signal output. + */ +#define ENET_QOS_MAC_PPS1_WIDTH_PPSWIDTH1(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS1_WIDTH_PPSWIDTH1_SHIFT)) & ENET_QOS_MAC_PPS1_WIDTH_PPSWIDTH1_MASK) +/*! @} */ + +/*! @name MAC_PPS2_TARGET_TIME_SECONDS - PPS2 Target Time Seconds */ +/*! @{ */ + +#define ENET_QOS_MAC_PPS2_TARGET_TIME_SECONDS_TSTRH2_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_PPS2_TARGET_TIME_SECONDS_TSTRH2_SHIFT (0U) +/*! TSTRH2 - PPS Target Time Seconds Register This field stores the time in seconds. */ +#define ENET_QOS_MAC_PPS2_TARGET_TIME_SECONDS_TSTRH2(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS2_TARGET_TIME_SECONDS_TSTRH2_SHIFT)) & ENET_QOS_MAC_PPS2_TARGET_TIME_SECONDS_TSTRH2_MASK) +/*! @} */ + +/*! @name MAC_PPS2_TARGET_TIME_NANOSECONDS - PPS2 Target Time Nanoseconds */ +/*! @{ */ + +#define ENET_QOS_MAC_PPS2_TARGET_TIME_NANOSECONDS_TTSL2_MASK (0x7FFFFFFFU) +#define ENET_QOS_MAC_PPS2_TARGET_TIME_NANOSECONDS_TTSL2_SHIFT (0U) +/*! TTSL2 - Target Time Low for PPS Register This register stores the time in (signed) nanoseconds. */ +#define ENET_QOS_MAC_PPS2_TARGET_TIME_NANOSECONDS_TTSL2(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS2_TARGET_TIME_NANOSECONDS_TTSL2_SHIFT)) & ENET_QOS_MAC_PPS2_TARGET_TIME_NANOSECONDS_TTSL2_MASK) + +#define ENET_QOS_MAC_PPS2_TARGET_TIME_NANOSECONDS_TRGTBUSY2_MASK (0x80000000U) +#define ENET_QOS_MAC_PPS2_TARGET_TIME_NANOSECONDS_TRGTBUSY2_SHIFT (31U) +/*! TRGTBUSY2 - PPS Target Time Register Busy The MAC sets this bit when the PPSCMD0 field in the + * PPS_CONTROL register is programmed to 010 or 011. + * 0b0..PPS Target Time Register Busy status is not detected + * 0b1..PPS Target Time Register Busy is detected + */ +#define ENET_QOS_MAC_PPS2_TARGET_TIME_NANOSECONDS_TRGTBUSY2(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS2_TARGET_TIME_NANOSECONDS_TRGTBUSY2_SHIFT)) & ENET_QOS_MAC_PPS2_TARGET_TIME_NANOSECONDS_TRGTBUSY2_MASK) +/*! @} */ + +/*! @name MAC_PPS2_INTERVAL - PPS2 Interval */ +/*! @{ */ + +#define ENET_QOS_MAC_PPS2_INTERVAL_PPSINT2_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_PPS2_INTERVAL_PPSINT2_SHIFT (0U) +/*! PPSINT2 - PPS Output Signal Interval These bits store the interval between the rising edges of PPS2 signal output. */ +#define ENET_QOS_MAC_PPS2_INTERVAL_PPSINT2(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS2_INTERVAL_PPSINT2_SHIFT)) & ENET_QOS_MAC_PPS2_INTERVAL_PPSINT2_MASK) +/*! @} */ + +/*! @name MAC_PPS2_WIDTH - PPS2 Width */ +/*! @{ */ + +#define ENET_QOS_MAC_PPS2_WIDTH_PPSWIDTH2_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_PPS2_WIDTH_PPSWIDTH2_SHIFT (0U) +/*! PPSWIDTH2 - PPS Output Signal Width These bits store the width between the rising edge and + * corresponding falling edge of PPS0 signal output. + */ +#define ENET_QOS_MAC_PPS2_WIDTH_PPSWIDTH2(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS2_WIDTH_PPSWIDTH2_SHIFT)) & ENET_QOS_MAC_PPS2_WIDTH_PPSWIDTH2_MASK) +/*! @} */ + +/*! @name MAC_PPS3_TARGET_TIME_SECONDS - PPS3 Target Time Seconds */ +/*! @{ */ + +#define ENET_QOS_MAC_PPS3_TARGET_TIME_SECONDS_TSTRH3_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_PPS3_TARGET_TIME_SECONDS_TSTRH3_SHIFT (0U) +/*! TSTRH3 - PPS Target Time Seconds Register This field stores the time in seconds. */ +#define ENET_QOS_MAC_PPS3_TARGET_TIME_SECONDS_TSTRH3(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS3_TARGET_TIME_SECONDS_TSTRH3_SHIFT)) & ENET_QOS_MAC_PPS3_TARGET_TIME_SECONDS_TSTRH3_MASK) +/*! @} */ + +/*! @name MAC_PPS3_TARGET_TIME_NANOSECONDS - PPS3 Target Time Nanoseconds */ +/*! @{ */ + +#define ENET_QOS_MAC_PPS3_TARGET_TIME_NANOSECONDS_TTSL3_MASK (0x7FFFFFFFU) +#define ENET_QOS_MAC_PPS3_TARGET_TIME_NANOSECONDS_TTSL3_SHIFT (0U) +/*! TTSL3 - Target Time Low for PPS Register This register stores the time in (signed) nanoseconds. */ +#define ENET_QOS_MAC_PPS3_TARGET_TIME_NANOSECONDS_TTSL3(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS3_TARGET_TIME_NANOSECONDS_TTSL3_SHIFT)) & ENET_QOS_MAC_PPS3_TARGET_TIME_NANOSECONDS_TTSL3_MASK) + +#define ENET_QOS_MAC_PPS3_TARGET_TIME_NANOSECONDS_TRGTBUSY3_MASK (0x80000000U) +#define ENET_QOS_MAC_PPS3_TARGET_TIME_NANOSECONDS_TRGTBUSY3_SHIFT (31U) +/*! TRGTBUSY3 - PPS Target Time Register Busy The MAC sets this bit when the PPSCMD0 field in the + * PPS_CONTROL register is programmed to 010 or 011. + * 0b0..PPS Target Time Register Busy status is not detected + * 0b1..PPS Target Time Register Busy is detected + */ +#define ENET_QOS_MAC_PPS3_TARGET_TIME_NANOSECONDS_TRGTBUSY3(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS3_TARGET_TIME_NANOSECONDS_TRGTBUSY3_SHIFT)) & ENET_QOS_MAC_PPS3_TARGET_TIME_NANOSECONDS_TRGTBUSY3_MASK) +/*! @} */ + +/*! @name MAC_PPS3_INTERVAL - PPS3 Interval */ +/*! @{ */ + +#define ENET_QOS_MAC_PPS3_INTERVAL_PPSINT3_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_PPS3_INTERVAL_PPSINT3_SHIFT (0U) +/*! PPSINT3 - PPS Output Signal Interval These bits store the interval between the rising edges of PPS3 signal output. */ +#define ENET_QOS_MAC_PPS3_INTERVAL_PPSINT3(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS3_INTERVAL_PPSINT3_SHIFT)) & ENET_QOS_MAC_PPS3_INTERVAL_PPSINT3_MASK) +/*! @} */ + +/*! @name MAC_PPS3_WIDTH - PPS3 Width */ +/*! @{ */ + +#define ENET_QOS_MAC_PPS3_WIDTH_PPSWIDTH3_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_PPS3_WIDTH_PPSWIDTH3_SHIFT (0U) +/*! PPSWIDTH3 - PPS Output Signal Width These bits store the width between the rising edge and + * corresponding falling edge of PPS0 signal output. + */ +#define ENET_QOS_MAC_PPS3_WIDTH_PPSWIDTH3(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS3_WIDTH_PPSWIDTH3_SHIFT)) & ENET_QOS_MAC_PPS3_WIDTH_PPSWIDTH3_MASK) +/*! @} */ + +/*! @name MAC_PTO_CONTROL - PTP Offload Engine Control */ +/*! @{ */ + +#define ENET_QOS_MAC_PTO_CONTROL_PTOEN_MASK (0x1U) +#define ENET_QOS_MAC_PTO_CONTROL_PTOEN_SHIFT (0U) +/*! PTOEN - PTP Offload Enable When this bit is set, the PTP Offload feature is enabled. + * 0b0..PTP Offload feature is disabled + * 0b1..PTP Offload feature is enabled + */ +#define ENET_QOS_MAC_PTO_CONTROL_PTOEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PTO_CONTROL_PTOEN_SHIFT)) & ENET_QOS_MAC_PTO_CONTROL_PTOEN_MASK) + +#define ENET_QOS_MAC_PTO_CONTROL_ASYNCEN_MASK (0x2U) +#define ENET_QOS_MAC_PTO_CONTROL_ASYNCEN_SHIFT (1U) +/*! ASYNCEN - Automatic PTP SYNC message Enable When this bit is set, PTP SYNC message is generated + * periodically based on interval programmed or trigger from application, when the MAC is + * programmed to be in Clock Master mode. + * 0b0..Automatic PTP SYNC message is disabled + * 0b1..Automatic PTP SYNC message is enabled + */ +#define ENET_QOS_MAC_PTO_CONTROL_ASYNCEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PTO_CONTROL_ASYNCEN_SHIFT)) & ENET_QOS_MAC_PTO_CONTROL_ASYNCEN_MASK) + +#define ENET_QOS_MAC_PTO_CONTROL_APDREQEN_MASK (0x4U) +#define ENET_QOS_MAC_PTO_CONTROL_APDREQEN_SHIFT (2U) +/*! APDREQEN - Automatic PTP Pdelay_Req message Enable When this bit is set, PTP Pdelay_Req message + * is generated periodically based on interval programmed or trigger from application, when the + * MAC is programmed to be in Peer-to-Peer Transparent mode. + * 0b0..Automatic PTP Pdelay_Req message is disabled + * 0b1..Automatic PTP Pdelay_Req message is enabled + */ +#define ENET_QOS_MAC_PTO_CONTROL_APDREQEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PTO_CONTROL_APDREQEN_SHIFT)) & ENET_QOS_MAC_PTO_CONTROL_APDREQEN_MASK) + +#define ENET_QOS_MAC_PTO_CONTROL_ASYNCTRIG_MASK (0x10U) +#define ENET_QOS_MAC_PTO_CONTROL_ASYNCTRIG_SHIFT (4U) +/*! ASYNCTRIG - Automatic PTP SYNC message Trigger When this bit is set, one PTP SYNC message is transmitted. + * 0b0..Automatic PTP SYNC message Trigger is disabled + * 0b1..Automatic PTP SYNC message Trigger is enabled + */ +#define ENET_QOS_MAC_PTO_CONTROL_ASYNCTRIG(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PTO_CONTROL_ASYNCTRIG_SHIFT)) & ENET_QOS_MAC_PTO_CONTROL_ASYNCTRIG_MASK) + +#define ENET_QOS_MAC_PTO_CONTROL_APDREQTRIG_MASK (0x20U) +#define ENET_QOS_MAC_PTO_CONTROL_APDREQTRIG_SHIFT (5U) +/*! APDREQTRIG - Automatic PTP Pdelay_Req message Trigger When this bit is set, one PTP Pdelay_Req message is transmitted. + * 0b0..Automatic PTP Pdelay_Req message Trigger is disabled + * 0b1..Automatic PTP Pdelay_Req message Trigger is enabled + */ +#define ENET_QOS_MAC_PTO_CONTROL_APDREQTRIG(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PTO_CONTROL_APDREQTRIG_SHIFT)) & ENET_QOS_MAC_PTO_CONTROL_APDREQTRIG_MASK) + +#define ENET_QOS_MAC_PTO_CONTROL_DRRDIS_MASK (0x40U) +#define ENET_QOS_MAC_PTO_CONTROL_DRRDIS_SHIFT (6U) +/*! DRRDIS - Disable PTO Delay Request/Response response generation When this bit is set, the Delay + * Request and Delay response is not generated for received SYNC and Delay request packet + * respectively, as required by the programmed mode. + * 0b0..PTO Delay Request/Response response generation is enabled + * 0b1..PTO Delay Request/Response response generation is disabled + */ +#define ENET_QOS_MAC_PTO_CONTROL_DRRDIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PTO_CONTROL_DRRDIS_SHIFT)) & ENET_QOS_MAC_PTO_CONTROL_DRRDIS_MASK) + +#define ENET_QOS_MAC_PTO_CONTROL_PDRDIS_MASK (0x80U) +#define ENET_QOS_MAC_PTO_CONTROL_PDRDIS_SHIFT (7U) +/*! PDRDIS - Disable Peer Delay Response response generation When this bit is set, the Peer Delay + * Response (Pdelay_Resp) response is not be generated for received Peer Delay Request (Pdelay_Req) + * request packet, as required by the programmed mode. + * 0b0..Peer Delay Response response generation is enabled + * 0b1..Peer Delay Response response generation is disabled + */ +#define ENET_QOS_MAC_PTO_CONTROL_PDRDIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PTO_CONTROL_PDRDIS_SHIFT)) & ENET_QOS_MAC_PTO_CONTROL_PDRDIS_MASK) + +#define ENET_QOS_MAC_PTO_CONTROL_DN_MASK (0xFF00U) +#define ENET_QOS_MAC_PTO_CONTROL_DN_SHIFT (8U) +/*! DN - Domain Number This field indicates the domain Number in which the PTP node is operating. */ +#define ENET_QOS_MAC_PTO_CONTROL_DN(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PTO_CONTROL_DN_SHIFT)) & ENET_QOS_MAC_PTO_CONTROL_DN_MASK) +/*! @} */ + +/*! @name MAC_SOURCE_PORT_IDENTITY0 - Source Port Identity 0 */ +/*! @{ */ + +#define ENET_QOS_MAC_SOURCE_PORT_IDENTITY0_SPI0_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_SOURCE_PORT_IDENTITY0_SPI0_SHIFT (0U) +/*! SPI0 - Source Port Identity 0 This field indicates bits [31:0] of sourcePortIdentity of PTP node. */ +#define ENET_QOS_MAC_SOURCE_PORT_IDENTITY0_SPI0(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_SOURCE_PORT_IDENTITY0_SPI0_SHIFT)) & ENET_QOS_MAC_SOURCE_PORT_IDENTITY0_SPI0_MASK) +/*! @} */ + +/*! @name MAC_SOURCE_PORT_IDENTITY1 - Source Port Identity 1 */ +/*! @{ */ + +#define ENET_QOS_MAC_SOURCE_PORT_IDENTITY1_SPI1_MASK (0xFFFFFFFFU) +#define ENET_QOS_MAC_SOURCE_PORT_IDENTITY1_SPI1_SHIFT (0U) +/*! SPI1 - Source Port Identity 1 This field indicates bits [63:32] of sourcePortIdentity of PTP node. */ +#define ENET_QOS_MAC_SOURCE_PORT_IDENTITY1_SPI1(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_SOURCE_PORT_IDENTITY1_SPI1_SHIFT)) & ENET_QOS_MAC_SOURCE_PORT_IDENTITY1_SPI1_MASK) +/*! @} */ + +/*! @name MAC_SOURCE_PORT_IDENTITY2 - Source Port Identity 2 */ +/*! @{ */ + +#define ENET_QOS_MAC_SOURCE_PORT_IDENTITY2_SPI2_MASK (0xFFFFU) +#define ENET_QOS_MAC_SOURCE_PORT_IDENTITY2_SPI2_SHIFT (0U) +/*! SPI2 - Source Port Identity 2 This field indicates bits [79:64] of sourcePortIdentity of PTP node. */ +#define ENET_QOS_MAC_SOURCE_PORT_IDENTITY2_SPI2(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_SOURCE_PORT_IDENTITY2_SPI2_SHIFT)) & ENET_QOS_MAC_SOURCE_PORT_IDENTITY2_SPI2_MASK) +/*! @} */ + +/*! @name MAC_LOG_MESSAGE_INTERVAL - Log Message Interval */ +/*! @{ */ + +#define ENET_QOS_MAC_LOG_MESSAGE_INTERVAL_LSI_MASK (0xFFU) +#define ENET_QOS_MAC_LOG_MESSAGE_INTERVAL_LSI_SHIFT (0U) +/*! LSI - Log Sync Interval This field indicates the periodicity of the automatically generated SYNC + * message when the PTP node is Master. + */ +#define ENET_QOS_MAC_LOG_MESSAGE_INTERVAL_LSI(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LOG_MESSAGE_INTERVAL_LSI_SHIFT)) & ENET_QOS_MAC_LOG_MESSAGE_INTERVAL_LSI_MASK) + +#define ENET_QOS_MAC_LOG_MESSAGE_INTERVAL_DRSYNCR_MASK (0x700U) +#define ENET_QOS_MAC_LOG_MESSAGE_INTERVAL_DRSYNCR_SHIFT (8U) +/*! DRSYNCR - Delay_Req to SYNC Ratio In Slave mode, it is used for controlling frequency of Delay_Req messages transmitted. + * 0b000..DelayReq generated for every received SYNC + * 0b001..DelayReq generated every alternate reception of SYNC + * 0b010..for every 4 SYNC messages + * 0b011..for every 8 SYNC messages + * 0b100..for every 16 SYNC messages + * 0b101..for every 32 SYNC messages + * 0b110..Reserved + */ +#define ENET_QOS_MAC_LOG_MESSAGE_INTERVAL_DRSYNCR(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LOG_MESSAGE_INTERVAL_DRSYNCR_SHIFT)) & ENET_QOS_MAC_LOG_MESSAGE_INTERVAL_DRSYNCR_MASK) + +#define ENET_QOS_MAC_LOG_MESSAGE_INTERVAL_LMPDRI_MASK (0xFF000000U) +#define ENET_QOS_MAC_LOG_MESSAGE_INTERVAL_LMPDRI_SHIFT (24U) +/*! LMPDRI - Log Min Pdelay_Req Interval This field indicates logMinPdelayReqInterval of PTP node. */ +#define ENET_QOS_MAC_LOG_MESSAGE_INTERVAL_LMPDRI(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LOG_MESSAGE_INTERVAL_LMPDRI_SHIFT)) & ENET_QOS_MAC_LOG_MESSAGE_INTERVAL_LMPDRI_MASK) +/*! @} */ + +/*! @name MTL_OPERATION_MODE - MTL Operation Mode */ +/*! @{ */ + +#define ENET_QOS_MTL_OPERATION_MODE_DTXSTS_MASK (0x2U) +#define ENET_QOS_MTL_OPERATION_MODE_DTXSTS_SHIFT (1U) +/*! DTXSTS - Drop Transmit Status When this bit is set, the Tx packet status received from the MAC is dropped in the MTL. + * 0b0..Drop Transmit Status is disabled + * 0b1..Drop Transmit Status is enabled + */ +#define ENET_QOS_MTL_OPERATION_MODE_DTXSTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_OPERATION_MODE_DTXSTS_SHIFT)) & ENET_QOS_MTL_OPERATION_MODE_DTXSTS_MASK) + +#define ENET_QOS_MTL_OPERATION_MODE_RAA_MASK (0x4U) +#define ENET_QOS_MTL_OPERATION_MODE_RAA_SHIFT (2U) +/*! RAA - Receive Arbitration Algorithm This field is used to select the arbitration algorithm for the Rx side. + * 0b0..Strict priority (SP) + * 0b1..Weighted Strict Priority (WSP) + */ +#define ENET_QOS_MTL_OPERATION_MODE_RAA(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_OPERATION_MODE_RAA_SHIFT)) & ENET_QOS_MTL_OPERATION_MODE_RAA_MASK) + +#define ENET_QOS_MTL_OPERATION_MODE_SCHALG_MASK (0x60U) +#define ENET_QOS_MTL_OPERATION_MODE_SCHALG_SHIFT (5U) +/*! SCHALG - Tx Scheduling Algorithm This field indicates the algorithm for Tx scheduling: + * 0b00..WRR algorithm + * 0b01..WFQ algorithm when DCB feature is selected.Otherwise, Reserved + * 0b10..DWRR algorithm when DCB feature is selected.Otherwise, Reserved + * 0b11..Strict priority algorithm + */ +#define ENET_QOS_MTL_OPERATION_MODE_SCHALG(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_OPERATION_MODE_SCHALG_SHIFT)) & ENET_QOS_MTL_OPERATION_MODE_SCHALG_MASK) + +#define ENET_QOS_MTL_OPERATION_MODE_CNTPRST_MASK (0x100U) +#define ENET_QOS_MTL_OPERATION_MODE_CNTPRST_SHIFT (8U) +/*! CNTPRST - Counters Preset When this bit is set, - MTL_TxQ[0-7]_Underflow register is initialized/preset to 12'h7F0. + * 0b0..Counters Preset is disabled + * 0b1..Counters Preset is enabled + */ +#define ENET_QOS_MTL_OPERATION_MODE_CNTPRST(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_OPERATION_MODE_CNTPRST_SHIFT)) & ENET_QOS_MTL_OPERATION_MODE_CNTPRST_MASK) + +#define ENET_QOS_MTL_OPERATION_MODE_CNTCLR_MASK (0x200U) +#define ENET_QOS_MTL_OPERATION_MODE_CNTCLR_SHIFT (9U) +/*! CNTCLR - Counters Reset When this bit is set, all counters are reset. + * 0b0..Counters are not reset + * 0b1..All counters are reset + */ +#define ENET_QOS_MTL_OPERATION_MODE_CNTCLR(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_OPERATION_MODE_CNTCLR_SHIFT)) & ENET_QOS_MTL_OPERATION_MODE_CNTCLR_MASK) + +#define ENET_QOS_MTL_OPERATION_MODE_FRPE_MASK (0x8000U) +#define ENET_QOS_MTL_OPERATION_MODE_FRPE_SHIFT (15U) +/*! FRPE - Flexible Rx parser Enable When this bit is set to 1, the Programmable Rx Parser functionality is enabled. + * 0b0..Flexible Rx parser is disabled + * 0b1..Flexible Rx parser is enabled + */ +#define ENET_QOS_MTL_OPERATION_MODE_FRPE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_OPERATION_MODE_FRPE_SHIFT)) & ENET_QOS_MTL_OPERATION_MODE_FRPE_MASK) +/*! @} */ + +/*! @name MTL_DBG_CTL - FIFO Debug Access Control and Status */ +/*! @{ */ + +#define ENET_QOS_MTL_DBG_CTL_FDBGEN_MASK (0x1U) +#define ENET_QOS_MTL_DBG_CTL_FDBGEN_SHIFT (0U) +/*! FDBGEN - FIFO Debug Access Enable When this bit is set, it indicates that the debug mode access to the FIFO is enabled. + * 0b0..FIFO Debug Access is disabled + * 0b1..FIFO Debug Access is enabled + */ +#define ENET_QOS_MTL_DBG_CTL_FDBGEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_DBG_CTL_FDBGEN_SHIFT)) & ENET_QOS_MTL_DBG_CTL_FDBGEN_MASK) + +#define ENET_QOS_MTL_DBG_CTL_DBGMOD_MASK (0x2U) +#define ENET_QOS_MTL_DBG_CTL_DBGMOD_SHIFT (1U) +/*! DBGMOD - Debug Mode Access to FIFO When this bit is set, it indicates that the current access to + * the FIFO is read, write, and debug access. + * 0b0..Debug Mode Access to FIFO is disabled + * 0b1..Debug Mode Access to FIFO is enabled + */ +#define ENET_QOS_MTL_DBG_CTL_DBGMOD(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_DBG_CTL_DBGMOD_SHIFT)) & ENET_QOS_MTL_DBG_CTL_DBGMOD_MASK) + +#define ENET_QOS_MTL_DBG_CTL_BYTEEN_MASK (0xCU) +#define ENET_QOS_MTL_DBG_CTL_BYTEEN_SHIFT (2U) +/*! BYTEEN - Byte Enables This field indicates the number of data bytes valid in the data register during Write operation. + * 0b00..Byte 0 valid + * 0b01..Byte 0 and Byte 1 are valid + * 0b10..Byte 0, Byte 1, and Byte 2 are valid + * 0b11..All four bytes are valid + */ +#define ENET_QOS_MTL_DBG_CTL_BYTEEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_DBG_CTL_BYTEEN_SHIFT)) & ENET_QOS_MTL_DBG_CTL_BYTEEN_MASK) + +#define ENET_QOS_MTL_DBG_CTL_PKTSTATE_MASK (0x60U) +#define ENET_QOS_MTL_DBG_CTL_PKTSTATE_SHIFT (5U) +/*! PKTSTATE - Encoded Packet State This field is used to write the control information to the Tx FIFO or Rx FIFO. + * 0b00..Packet Data + * 0b01..Control Word/Normal Status + * 0b10..SOP Data/Last Status + * 0b11..EOP Data/EOP + */ +#define ENET_QOS_MTL_DBG_CTL_PKTSTATE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_DBG_CTL_PKTSTATE_SHIFT)) & ENET_QOS_MTL_DBG_CTL_PKTSTATE_MASK) + +#define ENET_QOS_MTL_DBG_CTL_RSTALL_MASK (0x100U) +#define ENET_QOS_MTL_DBG_CTL_RSTALL_SHIFT (8U) +/*! RSTALL - Reset All Pointers When this bit is set, the pointers of all FIFOs are reset when FIFO Debug Access is enabled. + * 0b0..Reset All Pointers is disabled + * 0b1..Reset All Pointers is enabled + */ +#define ENET_QOS_MTL_DBG_CTL_RSTALL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_DBG_CTL_RSTALL_SHIFT)) & ENET_QOS_MTL_DBG_CTL_RSTALL_MASK) + +#define ENET_QOS_MTL_DBG_CTL_RSTSEL_MASK (0x200U) +#define ENET_QOS_MTL_DBG_CTL_RSTSEL_SHIFT (9U) +/*! RSTSEL - Reset Pointers of Selected FIFO When this bit is set, the pointers of the + * currently-selected FIFO are reset when FIFO Debug Access is enabled. + * 0b0..Reset Pointers of Selected FIFO is disabled + * 0b1..Reset Pointers of Selected FIFO is enabled + */ +#define ENET_QOS_MTL_DBG_CTL_RSTSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_DBG_CTL_RSTSEL_SHIFT)) & ENET_QOS_MTL_DBG_CTL_RSTSEL_MASK) + +#define ENET_QOS_MTL_DBG_CTL_FIFORDEN_MASK (0x400U) +#define ENET_QOS_MTL_DBG_CTL_FIFORDEN_SHIFT (10U) +/*! FIFORDEN - FIFO Read Enable When this bit is set, it enables the Read operation on selected FIFO when FIFO Debug Access is enabled. + * 0b0..FIFO Read is disabled + * 0b1..FIFO Read is enabled + */ +#define ENET_QOS_MTL_DBG_CTL_FIFORDEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_DBG_CTL_FIFORDEN_SHIFT)) & ENET_QOS_MTL_DBG_CTL_FIFORDEN_MASK) + +#define ENET_QOS_MTL_DBG_CTL_FIFOWREN_MASK (0x800U) +#define ENET_QOS_MTL_DBG_CTL_FIFOWREN_SHIFT (11U) +/*! FIFOWREN - FIFO Write Enable When this bit is set, it enables the Write operation on selected + * FIFO when FIFO Debug Access is enabled. + * 0b0..FIFO Write is disabled + * 0b1..FIFO Write is enabled + */ +#define ENET_QOS_MTL_DBG_CTL_FIFOWREN(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_DBG_CTL_FIFOWREN_SHIFT)) & ENET_QOS_MTL_DBG_CTL_FIFOWREN_MASK) + +#define ENET_QOS_MTL_DBG_CTL_FIFOSEL_MASK (0x3000U) +#define ENET_QOS_MTL_DBG_CTL_FIFOSEL_SHIFT (12U) +/*! FIFOSEL - FIFO Selected for Access This field indicates the FIFO selected for debug access: + * 0b00..Tx FIFO + * 0b01..Tx Status FIFO (only read access when SLVMOD is set) + * 0b10..TSO FIFO (cannot be accessed when SLVMOD is set) + * 0b11..Rx FIFO + */ +#define ENET_QOS_MTL_DBG_CTL_FIFOSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_DBG_CTL_FIFOSEL_SHIFT)) & ENET_QOS_MTL_DBG_CTL_FIFOSEL_MASK) + +#define ENET_QOS_MTL_DBG_CTL_PKTIE_MASK (0x4000U) +#define ENET_QOS_MTL_DBG_CTL_PKTIE_SHIFT (14U) +/*! PKTIE - Receive Packet Available Interrupt Status Enable When this bit is set, an interrupt is + * generated when EOP of received packet is written to the Rx FIFO. + * 0b0..Receive Packet Available Interrupt Status is disabled + * 0b1..Receive Packet Available Interrupt Status is enabled + */ +#define ENET_QOS_MTL_DBG_CTL_PKTIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_DBG_CTL_PKTIE_SHIFT)) & ENET_QOS_MTL_DBG_CTL_PKTIE_MASK) + +#define ENET_QOS_MTL_DBG_CTL_STSIE_MASK (0x8000U) +#define ENET_QOS_MTL_DBG_CTL_STSIE_SHIFT (15U) +/*! STSIE - Transmit Status Available Interrupt Status Enable When this bit is set, an interrupt is + * generated when Transmit status is available in slave mode. + * 0b0..Transmit Packet Available Interrupt Status is disabled + * 0b1..Transmit Packet Available Interrupt Status is enabled + */ +#define ENET_QOS_MTL_DBG_CTL_STSIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_DBG_CTL_STSIE_SHIFT)) & ENET_QOS_MTL_DBG_CTL_STSIE_MASK) +/*! @} */ + +/*! @name MTL_DBG_STS - FIFO Debug Status */ +/*! @{ */ + +#define ENET_QOS_MTL_DBG_STS_FIFOBUSY_MASK (0x1U) +#define ENET_QOS_MTL_DBG_STS_FIFOBUSY_SHIFT (0U) +/*! FIFOBUSY - FIFO Busy When set, this bit indicates that a FIFO operation is in progress in the + * MAC and content of the following fields is not valid: - All other fields of this register - All + * fields of the MTL_FIFO_DEBUG_DATA register + * 0b0..FIFO Busy not detected + * 0b1..FIFO Busy detected + */ +#define ENET_QOS_MTL_DBG_STS_FIFOBUSY(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_DBG_STS_FIFOBUSY_SHIFT)) & ENET_QOS_MTL_DBG_STS_FIFOBUSY_MASK) + +#define ENET_QOS_MTL_DBG_STS_PKTSTATE_MASK (0x6U) +#define ENET_QOS_MTL_DBG_STS_PKTSTATE_SHIFT (1U) +/*! PKTSTATE - Encoded Packet State This field is used to get the control or status information of the selected FIFO. + * 0b00..Packet Data + * 0b01..Control Word/Normal Status + * 0b10..SOP Data/Last Status + * 0b11..EOP Data/EOP + */ +#define ENET_QOS_MTL_DBG_STS_PKTSTATE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_DBG_STS_PKTSTATE_SHIFT)) & ENET_QOS_MTL_DBG_STS_PKTSTATE_MASK) + +#define ENET_QOS_MTL_DBG_STS_BYTEEN_MASK (0x18U) +#define ENET_QOS_MTL_DBG_STS_BYTEEN_SHIFT (3U) +/*! BYTEEN - Byte Enables This field indicates the number of data bytes valid in the data register during Read operation. + * 0b00..Byte 0 valid + * 0b01..Byte 0 and Byte 1 are valid + * 0b10..Byte 0, Byte 1, and Byte 2 are valid + * 0b11..All four bytes are valid + */ +#define ENET_QOS_MTL_DBG_STS_BYTEEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_DBG_STS_BYTEEN_SHIFT)) & ENET_QOS_MTL_DBG_STS_BYTEEN_MASK) + +#define ENET_QOS_MTL_DBG_STS_PKTI_MASK (0x100U) +#define ENET_QOS_MTL_DBG_STS_PKTI_SHIFT (8U) +/*! PKTI - Receive Packet Available Interrupt Status When set, this bit indicates that MAC layer has + * written the EOP of received packet to the Rx FIFO. + * 0b0..Receive Packet Available Interrupt Status not detected + * 0b1..Receive Packet Available Interrupt Status detected + */ +#define ENET_QOS_MTL_DBG_STS_PKTI(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_DBG_STS_PKTI_SHIFT)) & ENET_QOS_MTL_DBG_STS_PKTI_MASK) + +#define ENET_QOS_MTL_DBG_STS_STSI_MASK (0x200U) +#define ENET_QOS_MTL_DBG_STS_STSI_SHIFT (9U) +/*! STSI - Transmit Status Available Interrupt Status When set, this bit indicates that the Slave + * mode Tx packet is transmitted, and the status is available in Tx Status FIFO. + * 0b0..Transmit Status Available Interrupt Status not detected + * 0b1..Transmit Status Available Interrupt Status detected + */ +#define ENET_QOS_MTL_DBG_STS_STSI(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_DBG_STS_STSI_SHIFT)) & ENET_QOS_MTL_DBG_STS_STSI_MASK) + +#define ENET_QOS_MTL_DBG_STS_LOCR_MASK (0xFFFF8000U) +#define ENET_QOS_MTL_DBG_STS_LOCR_SHIFT (15U) +/*! LOCR - Remaining Locations in the FIFO Slave Access Mode: This field indicates the space available in selected FIFO. */ +#define ENET_QOS_MTL_DBG_STS_LOCR(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_DBG_STS_LOCR_SHIFT)) & ENET_QOS_MTL_DBG_STS_LOCR_MASK) +/*! @} */ + +/*! @name MTL_FIFO_DEBUG_DATA - FIFO Debug Data */ +/*! @{ */ + +#define ENET_QOS_MTL_FIFO_DEBUG_DATA_FDBGDATA_MASK (0xFFFFFFFFU) +#define ENET_QOS_MTL_FIFO_DEBUG_DATA_FDBGDATA_SHIFT (0U) +/*! FDBGDATA - FIFO Debug Data During debug or slave access write operation, this field contains the + * data to be written to the Tx FIFO, Rx FIFO, or TSO FIFO. + */ +#define ENET_QOS_MTL_FIFO_DEBUG_DATA_FDBGDATA(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_FIFO_DEBUG_DATA_FDBGDATA_SHIFT)) & ENET_QOS_MTL_FIFO_DEBUG_DATA_FDBGDATA_MASK) +/*! @} */ + +/*! @name MTL_INTERRUPT_STATUS - MTL Interrupt Status */ +/*! @{ */ + +#define ENET_QOS_MTL_INTERRUPT_STATUS_Q0IS_MASK (0x1U) +#define ENET_QOS_MTL_INTERRUPT_STATUS_Q0IS_SHIFT (0U) +/*! Q0IS - Queue 0 Interrupt status This bit indicates that there is an interrupt from Queue 0. + * 0b0..Queue 0 Interrupt status not detected + * 0b1..Queue 0 Interrupt status detected + */ +#define ENET_QOS_MTL_INTERRUPT_STATUS_Q0IS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_INTERRUPT_STATUS_Q0IS_SHIFT)) & ENET_QOS_MTL_INTERRUPT_STATUS_Q0IS_MASK) + +#define ENET_QOS_MTL_INTERRUPT_STATUS_Q1IS_MASK (0x2U) +#define ENET_QOS_MTL_INTERRUPT_STATUS_Q1IS_SHIFT (1U) +/*! Q1IS - Queue 1 Interrupt status This bit indicates that there is an interrupt from Queue 1. + * 0b0..Queue 1 Interrupt status not detected + * 0b1..Queue 1 Interrupt status detected + */ +#define ENET_QOS_MTL_INTERRUPT_STATUS_Q1IS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_INTERRUPT_STATUS_Q1IS_SHIFT)) & ENET_QOS_MTL_INTERRUPT_STATUS_Q1IS_MASK) + +#define ENET_QOS_MTL_INTERRUPT_STATUS_Q2IS_MASK (0x4U) +#define ENET_QOS_MTL_INTERRUPT_STATUS_Q2IS_SHIFT (2U) +/*! Q2IS - Queue 2 Interrupt status This bit indicates that there is an interrupt from Queue 2. + * 0b0..Queue 2 Interrupt status not detected + * 0b1..Queue 2 Interrupt status detected + */ +#define ENET_QOS_MTL_INTERRUPT_STATUS_Q2IS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_INTERRUPT_STATUS_Q2IS_SHIFT)) & ENET_QOS_MTL_INTERRUPT_STATUS_Q2IS_MASK) + +#define ENET_QOS_MTL_INTERRUPT_STATUS_Q3IS_MASK (0x8U) +#define ENET_QOS_MTL_INTERRUPT_STATUS_Q3IS_SHIFT (3U) +/*! Q3IS - Queue 3 Interrupt status This bit indicates that there is an interrupt from Queue 3. + * 0b0..Queue 3 Interrupt status not detected + * 0b1..Queue 3 Interrupt status detected + */ +#define ENET_QOS_MTL_INTERRUPT_STATUS_Q3IS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_INTERRUPT_STATUS_Q3IS_SHIFT)) & ENET_QOS_MTL_INTERRUPT_STATUS_Q3IS_MASK) + +#define ENET_QOS_MTL_INTERRUPT_STATUS_Q4IS_MASK (0x10U) +#define ENET_QOS_MTL_INTERRUPT_STATUS_Q4IS_SHIFT (4U) +/*! Q4IS - Queue 4 Interrupt status This bit indicates that there is an interrupt from Queue 4. + * 0b0..Queue 4 Interrupt status not detected + * 0b1..Queue 4 Interrupt status detected + */ +#define ENET_QOS_MTL_INTERRUPT_STATUS_Q4IS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_INTERRUPT_STATUS_Q4IS_SHIFT)) & ENET_QOS_MTL_INTERRUPT_STATUS_Q4IS_MASK) + +#define ENET_QOS_MTL_INTERRUPT_STATUS_DBGIS_MASK (0x20000U) +#define ENET_QOS_MTL_INTERRUPT_STATUS_DBGIS_SHIFT (17U) +/*! DBGIS - Debug Interrupt status This bit indicates an interrupt event during the slave access. + * 0b0..Debug Interrupt status not detected + * 0b1..Debug Interrupt status detected + */ +#define ENET_QOS_MTL_INTERRUPT_STATUS_DBGIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_INTERRUPT_STATUS_DBGIS_SHIFT)) & ENET_QOS_MTL_INTERRUPT_STATUS_DBGIS_MASK) + +#define ENET_QOS_MTL_INTERRUPT_STATUS_ESTIS_MASK (0x40000U) +#define ENET_QOS_MTL_INTERRUPT_STATUS_ESTIS_SHIFT (18U) +/*! ESTIS - EST (TAS- 802. + * 0b0..EST (TAS- 802.1Qbv) Interrupt status not detected + * 0b1..EST (TAS- 802.1Qbv) Interrupt status detected + */ +#define ENET_QOS_MTL_INTERRUPT_STATUS_ESTIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_INTERRUPT_STATUS_ESTIS_SHIFT)) & ENET_QOS_MTL_INTERRUPT_STATUS_ESTIS_MASK) + +#define ENET_QOS_MTL_INTERRUPT_STATUS_MTLPIS_MASK (0x800000U) +#define ENET_QOS_MTL_INTERRUPT_STATUS_MTLPIS_SHIFT (23U) +/*! MTLPIS - MTL Rx Parser Interrupt Status This bit indicates that there is an interrupt from Rx Parser Block. + * 0b0..MTL Rx Parser Interrupt status not detected + * 0b1..MTL Rx Parser Interrupt status detected + */ +#define ENET_QOS_MTL_INTERRUPT_STATUS_MTLPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_INTERRUPT_STATUS_MTLPIS_SHIFT)) & ENET_QOS_MTL_INTERRUPT_STATUS_MTLPIS_MASK) +/*! @} */ + +/*! @name MTL_RXQ_DMA_MAP0 - Receive Queue and DMA Channel Mapping 0 */ +/*! @{ */ + +#define ENET_QOS_MTL_RXQ_DMA_MAP0_Q0MDMACH_MASK (0x7U) +#define ENET_QOS_MTL_RXQ_DMA_MAP0_Q0MDMACH_SHIFT (0U) +/*! Q0MDMACH - Queue 0 Mapped to DMA Channel This field controls the routing of the packet received + * in Queue 0 to the DMA channel: - 000: DMA Channel 0 - 001: DMA Channel 1 - 010: DMA Channel 2 + * - 011: DMA Channel 3 - 100: DMA Channel 4 - 101: Reserved - 110: Reserved - 111: Reserved This + * field is valid when the Q0DDMACH field is reset. + */ +#define ENET_QOS_MTL_RXQ_DMA_MAP0_Q0MDMACH(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXQ_DMA_MAP0_Q0MDMACH_SHIFT)) & ENET_QOS_MTL_RXQ_DMA_MAP0_Q0MDMACH_MASK) + +#define ENET_QOS_MTL_RXQ_DMA_MAP0_Q0DDMACH_MASK (0x10U) +#define ENET_QOS_MTL_RXQ_DMA_MAP0_Q0DDMACH_SHIFT (4U) +/*! Q0DDMACH - Queue 0 Enabled for DA-based DMA Channel Selection When set, this bit indicates that + * the packets received in Queue 0 are routed to a particular DMA channel as decided in the MAC + * Receiver based on the DMA channel number programmed in the L3-L4 filter registers, or the + * Ethernet DA address. + * 0b0..Queue 0 disabled for DA-based DMA Channel Selection + * 0b1..Queue 0 enabled for DA-based DMA Channel Selection + */ +#define ENET_QOS_MTL_RXQ_DMA_MAP0_Q0DDMACH(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXQ_DMA_MAP0_Q0DDMACH_SHIFT)) & ENET_QOS_MTL_RXQ_DMA_MAP0_Q0DDMACH_MASK) + +#define ENET_QOS_MTL_RXQ_DMA_MAP0_Q1MDMACH_MASK (0x700U) +#define ENET_QOS_MTL_RXQ_DMA_MAP0_Q1MDMACH_SHIFT (8U) +/*! Q1MDMACH - Queue 1 Mapped to DMA Channel This field controls the routing of the received packet + * in Queue 1 to the DMA channel: - 000: DMA Channel 0 - 001: DMA Channel 1 - 010: DMA Channel 2 + * - 011: DMA Channel 3 - 100: DMA Channel 4 - 101: Reserved - 110: Reserved - 111: Reserved This + * field is valid when the Q1DDMACH field is reset. + */ +#define ENET_QOS_MTL_RXQ_DMA_MAP0_Q1MDMACH(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXQ_DMA_MAP0_Q1MDMACH_SHIFT)) & ENET_QOS_MTL_RXQ_DMA_MAP0_Q1MDMACH_MASK) + +#define ENET_QOS_MTL_RXQ_DMA_MAP0_Q1DDMACH_MASK (0x1000U) +#define ENET_QOS_MTL_RXQ_DMA_MAP0_Q1DDMACH_SHIFT (12U) +/*! Q1DDMACH - Queue 1 Enabled for DA-based DMA Channel Selection When set, this bit indicates that + * the packets received in Queue 1 are routed to a particular DMA channel as decided in the MAC + * Receiver based on the DMA channel number programmed in the L3-L4 filter registers, or the + * Ethernet DA address. + * 0b0..Queue 1 disabled for DA-based DMA Channel Selection + * 0b1..Queue 1 enabled for DA-based DMA Channel Selection + */ +#define ENET_QOS_MTL_RXQ_DMA_MAP0_Q1DDMACH(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXQ_DMA_MAP0_Q1DDMACH_SHIFT)) & ENET_QOS_MTL_RXQ_DMA_MAP0_Q1DDMACH_MASK) + +#define ENET_QOS_MTL_RXQ_DMA_MAP0_Q2MDMACH_MASK (0x70000U) +#define ENET_QOS_MTL_RXQ_DMA_MAP0_Q2MDMACH_SHIFT (16U) +/*! Q2MDMACH - Queue 2 Mapped to DMA Channel This field controls the routing of the received packet + * in Queue 2 to the DMA channel: - 000: DMA Channel 0 - 001: DMA Channel 1 - 010: DMA Channel 2 + * - 011: DMA Channel 3 - 100: DMA Channel 4 - 101: Reserved - 110: Reserved - 111: Reserved This + * field is valid when the Q2DDMACH field is reset. + */ +#define ENET_QOS_MTL_RXQ_DMA_MAP0_Q2MDMACH(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXQ_DMA_MAP0_Q2MDMACH_SHIFT)) & ENET_QOS_MTL_RXQ_DMA_MAP0_Q2MDMACH_MASK) + +#define ENET_QOS_MTL_RXQ_DMA_MAP0_Q2DDMACH_MASK (0x100000U) +#define ENET_QOS_MTL_RXQ_DMA_MAP0_Q2DDMACH_SHIFT (20U) +/*! Q2DDMACH - Queue 2 Enabled for DA-based DMA Channel Selection When set, this bit indicates that + * the packets received in Queue 2 are routed to a particular DMA channel as decided in the MAC + * Receiver based on the DMA channel number programmed in the L3-L4 filter registers, or the + * Ethernet DA address. + * 0b0..Queue 2 disabled for DA-based DMA Channel Selection + * 0b1..Queue 2 enabled for DA-based DMA Channel Selection + */ +#define ENET_QOS_MTL_RXQ_DMA_MAP0_Q2DDMACH(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXQ_DMA_MAP0_Q2DDMACH_SHIFT)) & ENET_QOS_MTL_RXQ_DMA_MAP0_Q2DDMACH_MASK) + +#define ENET_QOS_MTL_RXQ_DMA_MAP0_Q3MDMACH_MASK (0x7000000U) +#define ENET_QOS_MTL_RXQ_DMA_MAP0_Q3MDMACH_SHIFT (24U) +/*! Q3MDMACH - Queue 3 Mapped to DMA Channel This field controls the routing of the received packet + * in Queue 3 to the DMA channel: - 000: DMA Channel 0 - 001: DMA Channel 1 - 010: DMA Channel 2 + * - 011: DMA Channel 3 - 100: DMA Channel 4 - 101: Reserved - 110: Reserved - 111: Reserved This + * field is valid when the Q3DDMACH field is reset. + */ +#define ENET_QOS_MTL_RXQ_DMA_MAP0_Q3MDMACH(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXQ_DMA_MAP0_Q3MDMACH_SHIFT)) & ENET_QOS_MTL_RXQ_DMA_MAP0_Q3MDMACH_MASK) + +#define ENET_QOS_MTL_RXQ_DMA_MAP0_Q3DDMACH_MASK (0x10000000U) +#define ENET_QOS_MTL_RXQ_DMA_MAP0_Q3DDMACH_SHIFT (28U) +/*! Q3DDMACH - Queue 3 Enabled for Dynamic (per packet) DMA Channel Selection When set, this bit + * indicates that the packets received in Queue 3 are routed to a particular DMA channel as decided + * in the MAC Receiver based on the DMA channel number programmed in the L3-L4 filter registers, + * or the Ethernet DA address. + * 0b0..Queue 3 disabled for DA-based DMA Channel Selection + * 0b1..Queue 3 enabled for DA-based DMA Channel Selection + */ +#define ENET_QOS_MTL_RXQ_DMA_MAP0_Q3DDMACH(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXQ_DMA_MAP0_Q3DDMACH_SHIFT)) & ENET_QOS_MTL_RXQ_DMA_MAP0_Q3DDMACH_MASK) +/*! @} */ + +/*! @name MTL_RXQ_DMA_MAP1 - Receive Queue and DMA Channel Mapping 1 */ +/*! @{ */ + +#define ENET_QOS_MTL_RXQ_DMA_MAP1_Q4MDMACH_MASK (0x7U) +#define ENET_QOS_MTL_RXQ_DMA_MAP1_Q4MDMACH_SHIFT (0U) +/*! Q4MDMACH - Queue 4 Mapped to DMA Channel This field controls the routing of the packet received + * in Queue 4 to the DMA channel: - 000: DMA Channel 0 - 001: DMA Channel 1 - 010: DMA Channel 2 + * - 011: DMA Channel 3 - 100: DMA Channel 4 - 101: Reserved - 110: Reserved - 111: Reserved This + * field is valid when the Q4DDMACH field is reset. + */ +#define ENET_QOS_MTL_RXQ_DMA_MAP1_Q4MDMACH(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXQ_DMA_MAP1_Q4MDMACH_SHIFT)) & ENET_QOS_MTL_RXQ_DMA_MAP1_Q4MDMACH_MASK) + +#define ENET_QOS_MTL_RXQ_DMA_MAP1_Q4DDMACH_MASK (0x10U) +#define ENET_QOS_MTL_RXQ_DMA_MAP1_Q4DDMACH_SHIFT (4U) +/*! Q4DDMACH - Queue 4 Enabled for DA-based DMA Channel Selection When set, this bit indicates that + * the packets received in Queue 4 are routed to a particular DMA channel as decided in the MAC + * Receiver based on the DMA channel number programmed in the L3-L4 filter registers, or the + * Ethernet DA address. + * 0b0..Queue 4 disabled for DA-based DMA Channel Selection + * 0b1..Queue 4 enabled for DA-based DMA Channel Selection + */ +#define ENET_QOS_MTL_RXQ_DMA_MAP1_Q4DDMACH(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXQ_DMA_MAP1_Q4DDMACH_SHIFT)) & ENET_QOS_MTL_RXQ_DMA_MAP1_Q4DDMACH_MASK) +/*! @} */ + +/*! @name MTL_TBS_CTRL - Time Based Scheduling Control */ +/*! @{ */ + +#define ENET_QOS_MTL_TBS_CTRL_ESTM_MASK (0x1U) +#define ENET_QOS_MTL_TBS_CTRL_ESTM_SHIFT (0U) +/*! ESTM - EST offset Mode When this bit is set, the Launch Time value used in Time Based Scheduling + * is interpreted as an EST offset value and is added to the Base Time Register (BTR) of the + * current list. + * 0b0..EST offset Mode is disabled + * 0b1..EST offset Mode is enabled + */ +#define ENET_QOS_MTL_TBS_CTRL_ESTM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TBS_CTRL_ESTM_SHIFT)) & ENET_QOS_MTL_TBS_CTRL_ESTM_MASK) + +#define ENET_QOS_MTL_TBS_CTRL_LEOV_MASK (0x2U) +#define ENET_QOS_MTL_TBS_CTRL_LEOV_SHIFT (1U) +/*! LEOV - Launch Expiry Offset Valid When set indicates the LEOS field is valid. + * 0b0..LEOS field is invalid + * 0b1..LEOS field is valid + */ +#define ENET_QOS_MTL_TBS_CTRL_LEOV(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TBS_CTRL_LEOV_SHIFT)) & ENET_QOS_MTL_TBS_CTRL_LEOV_MASK) + +#define ENET_QOS_MTL_TBS_CTRL_LEGOS_MASK (0x70U) +#define ENET_QOS_MTL_TBS_CTRL_LEGOS_SHIFT (4U) +/*! LEGOS - Launch Expiry GSN Offset The number GSN slots that has to be added to the Launch GSN to compute the Launch Expiry time. */ +#define ENET_QOS_MTL_TBS_CTRL_LEGOS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TBS_CTRL_LEGOS_SHIFT)) & ENET_QOS_MTL_TBS_CTRL_LEGOS_MASK) + +#define ENET_QOS_MTL_TBS_CTRL_LEOS_MASK (0xFFFFFF00U) +#define ENET_QOS_MTL_TBS_CTRL_LEOS_SHIFT (8U) +/*! LEOS - Launch Expiry Offset The value in units of 256 nanoseconds that has to be added to the + * Launch time to compute the Launch Expiry time. + */ +#define ENET_QOS_MTL_TBS_CTRL_LEOS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TBS_CTRL_LEOS_SHIFT)) & ENET_QOS_MTL_TBS_CTRL_LEOS_MASK) +/*! @} */ + +/*! @name MTL_EST_CONTROL - Enhancements to Scheduled Transmission Control */ +/*! @{ */ + +#define ENET_QOS_MTL_EST_CONTROL_EEST_MASK (0x1U) +#define ENET_QOS_MTL_EST_CONTROL_EEST_SHIFT (0U) +/*! EEST - Enable EST When reset, the gate control list processing is halted and all gates are assumed to be in Open state. + * 0b0..EST is disabled + * 0b1..EST is enabled + */ +#define ENET_QOS_MTL_EST_CONTROL_EEST(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_CONTROL_EEST_SHIFT)) & ENET_QOS_MTL_EST_CONTROL_EEST_MASK) + +#define ENET_QOS_MTL_EST_CONTROL_SSWL_MASK (0x2U) +#define ENET_QOS_MTL_EST_CONTROL_SSWL_SHIFT (1U) +/*! SSWL - Switch to S/W owned list When set indicates that the software has programmed that list + * that it currently owns (SWOL) and the hardware should switch to the new list based on the new + * BTR. + * 0b0..Switch to S/W owned list is disabled + * 0b1..Switch to S/W owned list is enabled + */ +#define ENET_QOS_MTL_EST_CONTROL_SSWL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_CONTROL_SSWL_SHIFT)) & ENET_QOS_MTL_EST_CONTROL_SSWL_MASK) + +#define ENET_QOS_MTL_EST_CONTROL_DDBF_MASK (0x10U) +#define ENET_QOS_MTL_EST_CONTROL_DDBF_SHIFT (4U) +/*! DDBF - Do not Drop frames during Frame Size Error When set, frames are not be dropped during + * Head-of-Line blocking due to Frame Size Error (HLBF field of MTL_EST_STATUS register). + * 0b0..Drop frames during Frame Size Error + * 0b1..Do not Drop frames during Frame Size Error + */ +#define ENET_QOS_MTL_EST_CONTROL_DDBF(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_CONTROL_DDBF_SHIFT)) & ENET_QOS_MTL_EST_CONTROL_DDBF_MASK) + +#define ENET_QOS_MTL_EST_CONTROL_DFBS_MASK (0x20U) +#define ENET_QOS_MTL_EST_CONTROL_DFBS_SHIFT (5U) +/*! DFBS - Drop Frames causing Scheduling Error When set frames reported to cause HOL Blocking due + * to not getting scheduled (HLBS field of EST_STATUS register) after 4,8,16,32 (based on LCSE + * field of this register) GCL iterations are dropped. + * 0b0..Do not Drop Frames causing Scheduling Error + * 0b1..Drop Frames causing Scheduling Error + */ +#define ENET_QOS_MTL_EST_CONTROL_DFBS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_CONTROL_DFBS_SHIFT)) & ENET_QOS_MTL_EST_CONTROL_DFBS_MASK) + +#define ENET_QOS_MTL_EST_CONTROL_LCSE_MASK (0xC0U) +#define ENET_QOS_MTL_EST_CONTROL_LCSE_SHIFT (6U) +/*! LCSE - Loop Count to report Scheduling Error Programmable number of GCL list iterations before + * reporting an HLBS error defined in EST_STATUS register. + * 0b00..4 iterations + * 0b01..8 iterations + * 0b10..16 iterations + * 0b11..32 iterations + */ +#define ENET_QOS_MTL_EST_CONTROL_LCSE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_CONTROL_LCSE_SHIFT)) & ENET_QOS_MTL_EST_CONTROL_LCSE_MASK) + +#define ENET_QOS_MTL_EST_CONTROL_TILS_MASK (0x700U) +#define ENET_QOS_MTL_EST_CONTROL_TILS_SHIFT (8U) +/*! TILS - Time Interval Left Shift Amount This field provides the left shift amount for the + * programmed Time Interval values used in the Gate Control Lists. + */ +#define ENET_QOS_MTL_EST_CONTROL_TILS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_CONTROL_TILS_SHIFT)) & ENET_QOS_MTL_EST_CONTROL_TILS_MASK) + +#define ENET_QOS_MTL_EST_CONTROL_CTOV_MASK (0xFFF000U) +#define ENET_QOS_MTL_EST_CONTROL_CTOV_SHIFT (12U) +/*! CTOV - Current Time Offset Value Provides a 12 bit time offset value in nano second that is + * added to the current time to compensate for all the implementation pipeline delays such as the CDC + * sync delay, buffering delays, data path delays etc. + */ +#define ENET_QOS_MTL_EST_CONTROL_CTOV(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_CONTROL_CTOV_SHIFT)) & ENET_QOS_MTL_EST_CONTROL_CTOV_MASK) + +#define ENET_QOS_MTL_EST_CONTROL_PTOV_MASK (0xFF000000U) +#define ENET_QOS_MTL_EST_CONTROL_PTOV_SHIFT (24U) +/*! PTOV - PTP Time Offset Value The value of PTP Clock period multiplied by 6 in nanoseconds. */ +#define ENET_QOS_MTL_EST_CONTROL_PTOV(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_CONTROL_PTOV_SHIFT)) & ENET_QOS_MTL_EST_CONTROL_PTOV_MASK) +/*! @} */ + +/*! @name MTL_EST_EXT_CONTROL - MTL_EST_EXT_CONTROL */ +/*! @{ */ + +#define ENET_QOS_MTL_EST_EXT_CONTROL_OVHD_MASK (0x3FU) +#define ENET_QOS_MTL_EST_EXT_CONTROL_OVHD_SHIFT (0U) +/*! OVHD - Overhead Bytes Value */ +#define ENET_QOS_MTL_EST_EXT_CONTROL_OVHD(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_EXT_CONTROL_OVHD_SHIFT)) & ENET_QOS_MTL_EST_EXT_CONTROL_OVHD_MASK) +/*! @} */ + +/*! @name MTL_EST_STATUS - Enhancements to Scheduled Transmission Status */ +/*! @{ */ + +#define ENET_QOS_MTL_EST_STATUS_SWLC_MASK (0x1U) +#define ENET_QOS_MTL_EST_STATUS_SWLC_SHIFT (0U) +/*! SWLC - Switch to S/W owned list Complete When "1" indicates the hardware has successfully + * switched to the SWOL, and the SWOL bit has been updated to that effect. + * 0b0..Switch to S/W owned list Complete not detected + * 0b1..Switch to S/W owned list Complete detected + */ +#define ENET_QOS_MTL_EST_STATUS_SWLC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_STATUS_SWLC_SHIFT)) & ENET_QOS_MTL_EST_STATUS_SWLC_MASK) + +#define ENET_QOS_MTL_EST_STATUS_BTRE_MASK (0x2U) +#define ENET_QOS_MTL_EST_STATUS_BTRE_SHIFT (1U) +/*! BTRE - BTR Error When "1" indicates a programming error in the BTR of SWOL where the programmed + * value is less than current time. + * 0b0..BTR Error not detected + * 0b1..BTR Error detected + */ +#define ENET_QOS_MTL_EST_STATUS_BTRE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_STATUS_BTRE_SHIFT)) & ENET_QOS_MTL_EST_STATUS_BTRE_MASK) + +#define ENET_QOS_MTL_EST_STATUS_HLBF_MASK (0x4U) +#define ENET_QOS_MTL_EST_STATUS_HLBF_SHIFT (2U) +/*! HLBF - Head-Of-Line Blocking due to Frame Size Set when HOL Blocking is noticed on one or more + * Queues as a result of none of the Time Intervals of gate open in the GCL being greater than or + * equal to the duration needed for frame size (or frame fragment size when preemption is + * enabled) transmission. + * 0b0..Head-Of-Line Blocking due to Frame Size not detected + * 0b1..Head-Of-Line Blocking due to Frame Size detected + */ +#define ENET_QOS_MTL_EST_STATUS_HLBF(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_STATUS_HLBF_SHIFT)) & ENET_QOS_MTL_EST_STATUS_HLBF_MASK) + +#define ENET_QOS_MTL_EST_STATUS_HLBS_MASK (0x8U) +#define ENET_QOS_MTL_EST_STATUS_HLBS_SHIFT (3U) +/*! HLBS - Head-Of-Line Blocking due to Scheduling Set when the frame is not able to win arbitration + * and get scheduled even after 4 iterations of the GCL. + * 0b0..Head-Of-Line Blocking due to Scheduling not detected + * 0b1..Head-Of-Line Blocking due to Scheduling detected + */ +#define ENET_QOS_MTL_EST_STATUS_HLBS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_STATUS_HLBS_SHIFT)) & ENET_QOS_MTL_EST_STATUS_HLBS_MASK) + +#define ENET_QOS_MTL_EST_STATUS_CGCE_MASK (0x10U) +#define ENET_QOS_MTL_EST_STATUS_CGCE_SHIFT (4U) +/*! CGCE - Constant Gate Control Error This error occurs when the list length (LLR) is 1 and the + * programmed Time Interval (TI) value after the optional Left Shifting is less than or equal to the + * Cycle Time (CTR). + * 0b0..Constant Gate Control Error not detected + * 0b1..Constant Gate Control Error detected + */ +#define ENET_QOS_MTL_EST_STATUS_CGCE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_STATUS_CGCE_SHIFT)) & ENET_QOS_MTL_EST_STATUS_CGCE_MASK) + +#define ENET_QOS_MTL_EST_STATUS_SWOL_MASK (0x80U) +#define ENET_QOS_MTL_EST_STATUS_SWOL_SHIFT (7U) +/*! SWOL - S/W owned list When '0' indicates Gate control list number "0" is owned by software and + * when "1" indicates the Gate Control list "1" is owned by the software. + * 0b0..Gate control list number "0" is owned by software + * 0b1..Gate control list number "1" is owned by software + */ +#define ENET_QOS_MTL_EST_STATUS_SWOL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_STATUS_SWOL_SHIFT)) & ENET_QOS_MTL_EST_STATUS_SWOL_MASK) + +#define ENET_QOS_MTL_EST_STATUS_BTRL_MASK (0xF00U) +#define ENET_QOS_MTL_EST_STATUS_BTRL_SHIFT (8U) +/*! BTRL - BTR Error Loop Count Provides the minimum count (N) for which the equation Current Time + * =< New BTR + (N * New Cycle Time) becomes true. + */ +#define ENET_QOS_MTL_EST_STATUS_BTRL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_STATUS_BTRL_SHIFT)) & ENET_QOS_MTL_EST_STATUS_BTRL_MASK) + +#define ENET_QOS_MTL_EST_STATUS_CGSN_MASK (0xF0000U) +#define ENET_QOS_MTL_EST_STATUS_CGSN_SHIFT (16U) +/*! CGSN - Current GCL Slot Number Indicates the slot number of the GCL list. */ +#define ENET_QOS_MTL_EST_STATUS_CGSN(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_STATUS_CGSN_SHIFT)) & ENET_QOS_MTL_EST_STATUS_CGSN_MASK) +/*! @} */ + +/*! @name MTL_EST_SCH_ERROR - EST Scheduling Error */ +/*! @{ */ + +#define ENET_QOS_MTL_EST_SCH_ERROR_SEQN_MASK (0x1FU) +#define ENET_QOS_MTL_EST_SCH_ERROR_SEQN_SHIFT (0U) +/*! SEQN - Schedule Error Queue Number The One Hot Encoded Queue Numbers that have experienced + * error/timeout described in HLBS field of status register. + */ +#define ENET_QOS_MTL_EST_SCH_ERROR_SEQN(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_SCH_ERROR_SEQN_SHIFT)) & ENET_QOS_MTL_EST_SCH_ERROR_SEQN_MASK) +/*! @} */ + +/*! @name MTL_EST_FRM_SIZE_ERROR - EST Frame Size Error */ +/*! @{ */ + +#define ENET_QOS_MTL_EST_FRM_SIZE_ERROR_FEQN_MASK (0x1FU) +#define ENET_QOS_MTL_EST_FRM_SIZE_ERROR_FEQN_SHIFT (0U) +/*! FEQN - Frame Size Error Queue Number The One Hot Encoded Queue Numbers that have experienced + * error described in HLBF field of status register. + */ +#define ENET_QOS_MTL_EST_FRM_SIZE_ERROR_FEQN(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_FRM_SIZE_ERROR_FEQN_SHIFT)) & ENET_QOS_MTL_EST_FRM_SIZE_ERROR_FEQN_MASK) +/*! @} */ + +/*! @name MTL_EST_FRM_SIZE_CAPTURE - EST Frame Size Capture */ +/*! @{ */ + +#define ENET_QOS_MTL_EST_FRM_SIZE_CAPTURE_HBFS_MASK (0x7FFFU) +#define ENET_QOS_MTL_EST_FRM_SIZE_CAPTURE_HBFS_SHIFT (0U) +/*! HBFS - Frame Size of HLBF Captures the Frame Size of the dropped frame related to queue number + * indicated in HBFQ field of this register. + */ +#define ENET_QOS_MTL_EST_FRM_SIZE_CAPTURE_HBFS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_FRM_SIZE_CAPTURE_HBFS_SHIFT)) & ENET_QOS_MTL_EST_FRM_SIZE_CAPTURE_HBFS_MASK) + +#define ENET_QOS_MTL_EST_FRM_SIZE_CAPTURE_HBFQ_MASK (0x70000U) +#define ENET_QOS_MTL_EST_FRM_SIZE_CAPTURE_HBFQ_SHIFT (16U) +/*! HBFQ - Queue Number of HLBF Captures the binary value of the of the first Queue (number) + * experiencing HLBF error (see HLBF field of status register). + */ +#define ENET_QOS_MTL_EST_FRM_SIZE_CAPTURE_HBFQ(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_FRM_SIZE_CAPTURE_HBFQ_SHIFT)) & ENET_QOS_MTL_EST_FRM_SIZE_CAPTURE_HBFQ_MASK) +/*! @} */ + +/*! @name MTL_EST_INTR_ENABLE - EST Interrupt Enable */ +/*! @{ */ + +#define ENET_QOS_MTL_EST_INTR_ENABLE_IECC_MASK (0x1U) +#define ENET_QOS_MTL_EST_INTR_ENABLE_IECC_SHIFT (0U) +/*! IECC - Interrupt Enable for Switch List When set, generates interrupt when the configuration + * change is successful and the hardware has switched to the new list. + * 0b0..Interrupt for Switch List is disabled + * 0b1..Interrupt for Switch List is enabled + */ +#define ENET_QOS_MTL_EST_INTR_ENABLE_IECC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_INTR_ENABLE_IECC_SHIFT)) & ENET_QOS_MTL_EST_INTR_ENABLE_IECC_MASK) + +#define ENET_QOS_MTL_EST_INTR_ENABLE_IEBE_MASK (0x2U) +#define ENET_QOS_MTL_EST_INTR_ENABLE_IEBE_SHIFT (1U) +/*! IEBE - Interrupt Enable for BTR Error When set, generates interrupt when the BTR Error occurs and is indicated in the status. + * 0b0..Interrupt for BTR Error is disabled + * 0b1..Interrupt for BTR Error is enabled + */ +#define ENET_QOS_MTL_EST_INTR_ENABLE_IEBE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_INTR_ENABLE_IEBE_SHIFT)) & ENET_QOS_MTL_EST_INTR_ENABLE_IEBE_MASK) + +#define ENET_QOS_MTL_EST_INTR_ENABLE_IEHF_MASK (0x4U) +#define ENET_QOS_MTL_EST_INTR_ENABLE_IEHF_SHIFT (2U) +/*! IEHF - Interrupt Enable for HLBF When set, generates interrupt when the Head-of-Line Blocking + * due to Frame Size error occurs and is indicated in the status. + * 0b0..Interrupt for HLBF is disabled + * 0b1..Interrupt for HLBF is enabled + */ +#define ENET_QOS_MTL_EST_INTR_ENABLE_IEHF(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_INTR_ENABLE_IEHF_SHIFT)) & ENET_QOS_MTL_EST_INTR_ENABLE_IEHF_MASK) + +#define ENET_QOS_MTL_EST_INTR_ENABLE_IEHS_MASK (0x8U) +#define ENET_QOS_MTL_EST_INTR_ENABLE_IEHS_SHIFT (3U) +/*! IEHS - Interrupt Enable for HLBS When set, generates interrupt when the Head-of-Line Blocking + * due to Scheduling issue and is indicated in the status. + * 0b0..Interrupt for HLBS is disabled + * 0b1..Interrupt for HLBS is enabled + */ +#define ENET_QOS_MTL_EST_INTR_ENABLE_IEHS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_INTR_ENABLE_IEHS_SHIFT)) & ENET_QOS_MTL_EST_INTR_ENABLE_IEHS_MASK) + +#define ENET_QOS_MTL_EST_INTR_ENABLE_CGCE_MASK (0x10U) +#define ENET_QOS_MTL_EST_INTR_ENABLE_CGCE_SHIFT (4U) +/*! CGCE - Interrupt Enable for CGCE When set, generates interrupt when the Constant Gate Control + * Error occurs and is indicated in the status. + * 0b0..Interrupt for CGCE is disabled + * 0b1..Interrupt for CGCE is enabled + */ +#define ENET_QOS_MTL_EST_INTR_ENABLE_CGCE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_INTR_ENABLE_CGCE_SHIFT)) & ENET_QOS_MTL_EST_INTR_ENABLE_CGCE_MASK) +/*! @} */ + +/*! @name MTL_EST_GCL_CONTROL - EST GCL Control */ +/*! @{ */ + +#define ENET_QOS_MTL_EST_GCL_CONTROL_SRWO_MASK (0x1U) +#define ENET_QOS_MTL_EST_GCL_CONTROL_SRWO_SHIFT (0U) +/*! SRWO - Start Read/Write Op When set indicates a Read/Write Op has started and is in progress. + * 0b0..Start Read/Write Op disabled + * 0b1..Start Read/Write Op enabled + */ +#define ENET_QOS_MTL_EST_GCL_CONTROL_SRWO(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_GCL_CONTROL_SRWO_SHIFT)) & ENET_QOS_MTL_EST_GCL_CONTROL_SRWO_MASK) + +#define ENET_QOS_MTL_EST_GCL_CONTROL_R1W0_MASK (0x2U) +#define ENET_QOS_MTL_EST_GCL_CONTROL_R1W0_SHIFT (1U) +/*! R1W0 - Read '1', Write '0': When set to '1': Read Operation When set to '0': Write Operation. + * 0b0..Write Operation + * 0b1..Read Operation + */ +#define ENET_QOS_MTL_EST_GCL_CONTROL_R1W0(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_GCL_CONTROL_R1W0_SHIFT)) & ENET_QOS_MTL_EST_GCL_CONTROL_R1W0_MASK) + +#define ENET_QOS_MTL_EST_GCL_CONTROL_GCRR_MASK (0x4U) +#define ENET_QOS_MTL_EST_GCL_CONTROL_GCRR_SHIFT (2U) +/*! GCRR - Gate Control Related Registers When set to "1" indicates the R/W access is for the GCL + * related registers (BTR, CTR, TER, LLR) whose address is provided by GCRA. + * 0b0..Gate Control Related Registers are disabled + * 0b1..Gate Control Related Registers are enabled + */ +#define ENET_QOS_MTL_EST_GCL_CONTROL_GCRR(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_GCL_CONTROL_GCRR_SHIFT)) & ENET_QOS_MTL_EST_GCL_CONTROL_GCRR_MASK) + +#define ENET_QOS_MTL_EST_GCL_CONTROL_DBGM_MASK (0x10U) +#define ENET_QOS_MTL_EST_GCL_CONTROL_DBGM_SHIFT (4U) +/*! DBGM - Debug Mode When set to "1" indicates R/W in debug mode where the memory bank (for GCL and + * Time related registers) is explicitly provided by DBGB value, when set to "0" SWOL bit is + * used to determine which bank to use. + * 0b0..Debug Mode is disabled + * 0b1..Debug Mode is enabled + */ +#define ENET_QOS_MTL_EST_GCL_CONTROL_DBGM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_GCL_CONTROL_DBGM_SHIFT)) & ENET_QOS_MTL_EST_GCL_CONTROL_DBGM_MASK) + +#define ENET_QOS_MTL_EST_GCL_CONTROL_DBGB_MASK (0x20U) +#define ENET_QOS_MTL_EST_GCL_CONTROL_DBGB_SHIFT (5U) +/*! DBGB - Debug Mode Bank Select When set to "0" indicates R/W in debug mode should be directed to + * Bank 0 (GCL0 and corresponding Time related registers). + * 0b0..R/W in debug mode should be directed to Bank 0 + * 0b1..R/W in debug mode should be directed to Bank 1 + */ +#define ENET_QOS_MTL_EST_GCL_CONTROL_DBGB(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_GCL_CONTROL_DBGB_SHIFT)) & ENET_QOS_MTL_EST_GCL_CONTROL_DBGB_MASK) + +#define ENET_QOS_MTL_EST_GCL_CONTROL_ADDR_MASK (0x1FF00U) +#define ENET_QOS_MTL_EST_GCL_CONTROL_ADDR_SHIFT (8U) +/*! ADDR - Gate Control List Address: (GCLA when GCRR is "0"). */ +#define ENET_QOS_MTL_EST_GCL_CONTROL_ADDR(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_GCL_CONTROL_ADDR_SHIFT)) & ENET_QOS_MTL_EST_GCL_CONTROL_ADDR_MASK) + +#define ENET_QOS_MTL_EST_GCL_CONTROL_ERR0_MASK (0x100000U) +#define ENET_QOS_MTL_EST_GCL_CONTROL_ERR0_SHIFT (20U) +/*! ERR0 - When set indicates the last write operation was aborted as software writes to GCL and GCL + * registers is prohibited when SSWL bit of MTL_EST_CONTROL Register is set. + * 0b0..ERR0 is disabled + * 0b1..ERR1 is enabled + */ +#define ENET_QOS_MTL_EST_GCL_CONTROL_ERR0(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_GCL_CONTROL_ERR0_SHIFT)) & ENET_QOS_MTL_EST_GCL_CONTROL_ERR0_MASK) + +#define ENET_QOS_MTL_EST_GCL_CONTROL_ESTEIEE_MASK (0x200000U) +#define ENET_QOS_MTL_EST_GCL_CONTROL_ESTEIEE_SHIFT (21U) +/*! ESTEIEE - EST ECC Inject Error Enable When set along with EEST bit of MTL_EST_CONTROL register, + * enables the ECC error injection feature. + * 0b0..EST ECC Inject Error is disabled + * 0b1..EST ECC Inject Error is enabled + */ +#define ENET_QOS_MTL_EST_GCL_CONTROL_ESTEIEE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_GCL_CONTROL_ESTEIEE_SHIFT)) & ENET_QOS_MTL_EST_GCL_CONTROL_ESTEIEE_MASK) + +#define ENET_QOS_MTL_EST_GCL_CONTROL_ESTEIEC_MASK (0xC00000U) +#define ENET_QOS_MTL_EST_GCL_CONTROL_ESTEIEC_SHIFT (22U) +/*! ESTEIEC - ECC Inject Error Control for EST Memory When EIEE bit of this register is set, + * following are the errors inserted based on the value encoded in this field. + * 0b00..Insert 1 bit error + * 0b01..Insert 2 bit errors + * 0b10..Insert 3 bit errors + * 0b11..Insert 1 bit error in address field + */ +#define ENET_QOS_MTL_EST_GCL_CONTROL_ESTEIEC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_GCL_CONTROL_ESTEIEC_SHIFT)) & ENET_QOS_MTL_EST_GCL_CONTROL_ESTEIEC_MASK) +/*! @} */ + +/*! @name MTL_EST_GCL_DATA - EST GCL Data */ +/*! @{ */ + +#define ENET_QOS_MTL_EST_GCL_DATA_GCD_MASK (0xFFFFFFFFU) +#define ENET_QOS_MTL_EST_GCL_DATA_GCD_SHIFT (0U) +/*! GCD - Gate Control Data The data corresponding to the address selected in the MTL_GCL_CONTROL register. */ +#define ENET_QOS_MTL_EST_GCL_DATA_GCD(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_GCL_DATA_GCD_SHIFT)) & ENET_QOS_MTL_EST_GCL_DATA_GCD_MASK) +/*! @} */ + +/*! @name MTL_FPE_CTRL_STS - Frame Preemption Control and Status */ +/*! @{ */ + +#define ENET_QOS_MTL_FPE_CTRL_STS_AFSZ_MASK (0x3U) +#define ENET_QOS_MTL_FPE_CTRL_STS_AFSZ_SHIFT (0U) +/*! AFSZ - Additional Fragment Size used to indicate, in units of 64 bytes, the minimum number of + * bytes over 64 bytes required in non-final fragments of preempted frames. + */ +#define ENET_QOS_MTL_FPE_CTRL_STS_AFSZ(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_FPE_CTRL_STS_AFSZ_SHIFT)) & ENET_QOS_MTL_FPE_CTRL_STS_AFSZ_MASK) + +#define ENET_QOS_MTL_FPE_CTRL_STS_PEC_MASK (0x1F00U) +#define ENET_QOS_MTL_FPE_CTRL_STS_PEC_SHIFT (8U) +/*! PEC - Preemption Classification When set indicates the corresponding Queue must be classified as + * preemptable, when '0' Queue is classified as express. + */ +#define ENET_QOS_MTL_FPE_CTRL_STS_PEC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_FPE_CTRL_STS_PEC_SHIFT)) & ENET_QOS_MTL_FPE_CTRL_STS_PEC_MASK) + +#define ENET_QOS_MTL_FPE_CTRL_STS_HRS_MASK (0x10000000U) +#define ENET_QOS_MTL_FPE_CTRL_STS_HRS_SHIFT (28U) +/*! HRS - Hold/Release Status - 1: Indicates a Set-and-Hold-MAC operation was last executed and the pMAC is in Hold State. + * 0b0..Indicates a Set-and-Release-MAC operation was last executed and the pMAC is in Release State + * 0b1..Indicates a Set-and-Hold-MAC operation was last executed and the pMAC is in Hold State + */ +#define ENET_QOS_MTL_FPE_CTRL_STS_HRS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_FPE_CTRL_STS_HRS_SHIFT)) & ENET_QOS_MTL_FPE_CTRL_STS_HRS_MASK) +/*! @} */ + +/*! @name MTL_FPE_ADVANCE - Frame Preemption Hold and Release Advance */ +/*! @{ */ + +#define ENET_QOS_MTL_FPE_ADVANCE_HADV_MASK (0xFFFFU) +#define ENET_QOS_MTL_FPE_ADVANCE_HADV_SHIFT (0U) +/*! HADV - Hold Advance The maximum time in nanoseconds that can elapse between issuing a HOLD to + * the MAC and the MAC ceasing to transmit any preemptable frame that is in the process of + * transmission or any preemptable frames that are queued for transmission. + */ +#define ENET_QOS_MTL_FPE_ADVANCE_HADV(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_FPE_ADVANCE_HADV_SHIFT)) & ENET_QOS_MTL_FPE_ADVANCE_HADV_MASK) + +#define ENET_QOS_MTL_FPE_ADVANCE_RADV_MASK (0xFFFF0000U) +#define ENET_QOS_MTL_FPE_ADVANCE_RADV_SHIFT (16U) +/*! RADV - Release Advance The maximum time in nanoseconds that can elapse between issuing a RELEASE + * to the MAC and the MAC being ready to resume transmission of preemptable frames, in the + * absence of there being any express frames available for transmission. + */ +#define ENET_QOS_MTL_FPE_ADVANCE_RADV(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_FPE_ADVANCE_RADV_SHIFT)) & ENET_QOS_MTL_FPE_ADVANCE_RADV_MASK) +/*! @} */ + +/*! @name MTL_RXP_CONTROL_STATUS - RXP Control Status */ +/*! @{ */ + +#define ENET_QOS_MTL_RXP_CONTROL_STATUS_NVE_MASK (0xFFU) +#define ENET_QOS_MTL_RXP_CONTROL_STATUS_NVE_SHIFT (0U) +/*! NVE - Number of valid entries in the Instruction table This control indicates the number of + * valid entries in the Instruction Memory. + */ +#define ENET_QOS_MTL_RXP_CONTROL_STATUS_NVE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXP_CONTROL_STATUS_NVE_SHIFT)) & ENET_QOS_MTL_RXP_CONTROL_STATUS_NVE_MASK) + +#define ENET_QOS_MTL_RXP_CONTROL_STATUS_NPE_MASK (0xFF0000U) +#define ENET_QOS_MTL_RXP_CONTROL_STATUS_NPE_SHIFT (16U) +/*! NPE - Number of parsable entries in the Instruction table This control indicates the number of + * parsable entries in the Instruction Memory. + */ +#define ENET_QOS_MTL_RXP_CONTROL_STATUS_NPE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXP_CONTROL_STATUS_NPE_SHIFT)) & ENET_QOS_MTL_RXP_CONTROL_STATUS_NPE_MASK) + +#define ENET_QOS_MTL_RXP_CONTROL_STATUS_RXPI_MASK (0x80000000U) +#define ENET_QOS_MTL_RXP_CONTROL_STATUS_RXPI_SHIFT (31U) +/*! RXPI - RX Parser in Idle state This status bit is set to 1 when the Rx parser is in Idle State + * and waiting for a new packet for processing. + * 0b0..RX Parser not in Idle state + * 0b1..RX Parser in Idle state + */ +#define ENET_QOS_MTL_RXP_CONTROL_STATUS_RXPI(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXP_CONTROL_STATUS_RXPI_SHIFT)) & ENET_QOS_MTL_RXP_CONTROL_STATUS_RXPI_MASK) +/*! @} */ + +/*! @name MTL_RXP_INTERRUPT_CONTROL_STATUS - RXP Interrupt Control Status */ +/*! @{ */ + +#define ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_NVEOVIS_MASK (0x1U) +#define ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_NVEOVIS_SHIFT (0U) +/*! NVEOVIS - Number of Valid Entries Overflow Interrupt Status While parsing if the Instruction + * address found to be more than NVE (Number of Valid Entries in MTL_RXP_CONTROL register), then + * this bit is set to 1. + * 0b0..Number of Valid Entries Overflow Interrupt Status not detected + * 0b1..Number of Valid Entries Overflow Interrupt Status detected + */ +#define ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_NVEOVIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_NVEOVIS_SHIFT)) & ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_NVEOVIS_MASK) + +#define ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_NPEOVIS_MASK (0x2U) +#define ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_NPEOVIS_SHIFT (1U) +/*! NPEOVIS - Number of Parsable Entries Overflow Interrupt Status While parsing a packet if the + * number of parsed entries found to be more than NPE[] (Number of Parseable Entries in + * MTL_RXP_CONTROL register),then this bit is set to 1. + * 0b0..Number of Parsable Entries Overflow Interrupt Status not detected + * 0b1..Number of Parsable Entries Overflow Interrupt Status detected + */ +#define ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_NPEOVIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_NPEOVIS_SHIFT)) & ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_NPEOVIS_MASK) + +#define ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_FOOVIS_MASK (0x4U) +#define ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_FOOVIS_SHIFT (2U) +/*! FOOVIS - Frame Offset Overflow Interrupt Status While parsing if the Instruction table entry's + * 'Frame Offset' found to be more than EOF offset, then then this bit is set. + * 0b0..Frame Offset Overflow Interrupt Status not detected + * 0b1..Frame Offset Overflow Interrupt Status detected + */ +#define ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_FOOVIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_FOOVIS_SHIFT)) & ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_FOOVIS_MASK) + +#define ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_PDRFIS_MASK (0x8U) +#define ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_PDRFIS_SHIFT (3U) +/*! PDRFIS - Packet Dropped due to RF Interrupt Status If the Rx Parser result says to drop the + * packet by setting RF=1 in the instruction memory, then this bit is set to 1. + * 0b0..Packet Dropped due to RF Interrupt Status not detected + * 0b1..Packet Dropped due to RF Interrupt Status detected + */ +#define ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_PDRFIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_PDRFIS_SHIFT)) & ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_PDRFIS_MASK) + +#define ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_NVEOVIE_MASK (0x10000U) +#define ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_NVEOVIE_SHIFT (16U) +/*! NVEOVIE - Number of Valid Entries Overflow Interrupt Enable When this bit is set, the NVEOVIS interrupt is enabled. + * 0b0..Number of Valid Entries Overflow Interrupt is disabled + * 0b1..Number of Valid Entries Overflow Interrupt is enabled + */ +#define ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_NVEOVIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_NVEOVIE_SHIFT)) & ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_NVEOVIE_MASK) + +#define ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_NPEOVIE_MASK (0x20000U) +#define ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_NPEOVIE_SHIFT (17U) +/*! NPEOVIE - Number of Parsable Entries Overflow Interrupt Enable When this bit is set, the NPEOVIS interrupt is enabled. + * 0b0..Number of Parsable Entries Overflow Interrupt is disabled + * 0b1..Number of Parsable Entries Overflow Interrupt is enabled + */ +#define ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_NPEOVIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_NPEOVIE_SHIFT)) & ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_NPEOVIE_MASK) + +#define ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_FOOVIE_MASK (0x40000U) +#define ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_FOOVIE_SHIFT (18U) +/*! FOOVIE - Frame Offset Overflow Interrupt Enable When this bit is set, the FOOVIS interrupt is enabled. + * 0b0..Frame Offset Overflow Interrupt is disabled + * 0b1..Frame Offset Overflow Interrupt is enabled + */ +#define ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_FOOVIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_FOOVIE_SHIFT)) & ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_FOOVIE_MASK) + +#define ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_PDRFIE_MASK (0x80000U) +#define ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_PDRFIE_SHIFT (19U) +/*! PDRFIE - Packet Drop due to RF Interrupt Enable When this bit is set, the PDRFIS interrupt is enabled. + * 0b0..Packet Drop due to RF Interrupt is disabled + * 0b1..Packet Drop due to RF Interrupt is enabled + */ +#define ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_PDRFIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_PDRFIE_SHIFT)) & ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_PDRFIE_MASK) +/*! @} */ + +/*! @name MTL_RXP_DROP_CNT - RXP Drop Count */ +/*! @{ */ + +#define ENET_QOS_MTL_RXP_DROP_CNT_RXPDC_MASK (0x7FFFFFFFU) +#define ENET_QOS_MTL_RXP_DROP_CNT_RXPDC_SHIFT (0U) +/*! RXPDC - Rx Parser Drop count This 31-bit counter is implemented whenever a Rx Parser Drops a packet due to RF =1. */ +#define ENET_QOS_MTL_RXP_DROP_CNT_RXPDC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXP_DROP_CNT_RXPDC_SHIFT)) & ENET_QOS_MTL_RXP_DROP_CNT_RXPDC_MASK) + +#define ENET_QOS_MTL_RXP_DROP_CNT_RXPDCOVF_MASK (0x80000000U) +#define ENET_QOS_MTL_RXP_DROP_CNT_RXPDCOVF_SHIFT (31U) +/*! RXPDCOVF - Rx Parser Drop Counter Overflow Bit When set, this bit indicates that the + * MTL_RXP_DROP_CNT (RXPDC) Counter field crossed the maximum limit. + * 0b0..Rx Parser Drop count overflow not occurred + * 0b1..Rx Parser Drop count overflow occurred + */ +#define ENET_QOS_MTL_RXP_DROP_CNT_RXPDCOVF(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXP_DROP_CNT_RXPDCOVF_SHIFT)) & ENET_QOS_MTL_RXP_DROP_CNT_RXPDCOVF_MASK) +/*! @} */ + +/*! @name MTL_RXP_ERROR_CNT - RXP Error Count */ +/*! @{ */ + +#define ENET_QOS_MTL_RXP_ERROR_CNT_RXPEC_MASK (0x7FFFFFFFU) +#define ENET_QOS_MTL_RXP_ERROR_CNT_RXPEC_SHIFT (0U) +/*! RXPEC - Rx Parser Error count This 31-bit counter is implemented whenever a Rx Parser encounters + * following Error scenarios - Entry address >= NVE[] - Number Parsed Entries >= NPE[] - Entry + * address > EOF data entry address The counter is cleared when the register is read. + */ +#define ENET_QOS_MTL_RXP_ERROR_CNT_RXPEC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXP_ERROR_CNT_RXPEC_SHIFT)) & ENET_QOS_MTL_RXP_ERROR_CNT_RXPEC_MASK) + +#define ENET_QOS_MTL_RXP_ERROR_CNT_RXPECOVF_MASK (0x80000000U) +#define ENET_QOS_MTL_RXP_ERROR_CNT_RXPECOVF_SHIFT (31U) +/*! RXPECOVF - Rx Parser Error Counter Overflow Bit When set, this bit indicates that the + * MTL_RXP_ERROR_CNT (RXPEC) Counter field crossed the maximum limit. + * 0b0..Rx Parser Error count overflow not occurred + * 0b1..Rx Parser Error count overflow occurred + */ +#define ENET_QOS_MTL_RXP_ERROR_CNT_RXPECOVF(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXP_ERROR_CNT_RXPECOVF_SHIFT)) & ENET_QOS_MTL_RXP_ERROR_CNT_RXPECOVF_MASK) +/*! @} */ + +/*! @name MTL_RXP_INDIRECT_ACC_CONTROL_STATUS - RXP Indirect Access Control and Status */ +/*! @{ */ + +#define ENET_QOS_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_ADDR_MASK (0x3FFU) +#define ENET_QOS_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_ADDR_SHIFT (0U) +/*! ADDR - FRP Instruction Table Offset Address This field indicates the ADDR of the 32-bit entry in Rx parser instruction table. */ +#define ENET_QOS_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_ADDR(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_ADDR_SHIFT)) & ENET_QOS_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_ADDR_MASK) + +#define ENET_QOS_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_WRRDN_MASK (0x10000U) +#define ENET_QOS_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_WRRDN_SHIFT (16U) +/*! WRRDN - Read Write Control When this bit is set to 1 indicates the write operation to the Rx Parser Memory. + * 0b0..Read operation to the Rx Parser Memory + * 0b1..Write operation to the Rx Parser Memory + */ +#define ENET_QOS_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_WRRDN(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_WRRDN_SHIFT)) & ENET_QOS_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_WRRDN_MASK) + +#define ENET_QOS_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_STARTBUSY_MASK (0x80000000U) +#define ENET_QOS_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_STARTBUSY_SHIFT (31U) +/*! STARTBUSY - FRP Instruction Table Access Busy When this bit is set to 1 by the software then it + * indicates to start the Read/Write operation from/to the Rx Parser Memory. + * 0b0..hardware not busy + * 0b1..hardware is busy (Read/Write operation from/to the Rx Parser Memory) + */ +#define ENET_QOS_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_STARTBUSY(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_STARTBUSY_SHIFT)) & ENET_QOS_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_STARTBUSY_MASK) +/*! @} */ + +/*! @name MTL_RXP_INDIRECT_ACC_DATA - RXP Indirect Access Data */ +/*! @{ */ + +#define ENET_QOS_MTL_RXP_INDIRECT_ACC_DATA_DATA_MASK (0xFFFFFFFFU) +#define ENET_QOS_MTL_RXP_INDIRECT_ACC_DATA_DATA_SHIFT (0U) +/*! DATA - FRP Instruction Table Write/Read Data Software should write this register before issuing any write command. */ +#define ENET_QOS_MTL_RXP_INDIRECT_ACC_DATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXP_INDIRECT_ACC_DATA_DATA_SHIFT)) & ENET_QOS_MTL_RXP_INDIRECT_ACC_DATA_DATA_MASK) +/*! @} */ + +/*! @name MTL_RXP_BYPASS_CNT - MTL_RXP_BYPASS_CNT */ +/*! @{ */ + +#define ENET_QOS_MTL_RXP_BYPASS_CNT_RXPBC_MASK (0x7FFFFFFFU) +#define ENET_QOS_MTL_RXP_BYPASS_CNT_RXPBC_SHIFT (0U) +/*! RXPBC - Rx Parser Bypass Count */ +#define ENET_QOS_MTL_RXP_BYPASS_CNT_RXPBC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXP_BYPASS_CNT_RXPBC_SHIFT)) & ENET_QOS_MTL_RXP_BYPASS_CNT_RXPBC_MASK) + +#define ENET_QOS_MTL_RXP_BYPASS_CNT_RXPBCOF_MASK (0x80000000U) +#define ENET_QOS_MTL_RXP_BYPASS_CNT_RXPBCOF_SHIFT (31U) +/*! RXPBCOF - Rx Parser bypass Counter Overflow Bit. Access restriction applies. Clears on read. Self-set to 1 on internal event. + * 0b0..Indicates that MTL_RXP_BYPASS_CNT[RXPBC] counter field has not crossed the maximum limit + * 0b1..Indicates that MTL_RXP_BYPASS_CNT[RXPBC] counter field has crossed the maximum limit + */ +#define ENET_QOS_MTL_RXP_BYPASS_CNT_RXPBCOF(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXP_BYPASS_CNT_RXPBCOF_SHIFT)) & ENET_QOS_MTL_RXP_BYPASS_CNT_RXPBCOF_MASK) +/*! @} */ + +/*! @name MTL_TXQX_OP_MODE - Queue 0 Transmit Operation Mode..Queue 4 Transmit Operation Mode */ +/*! @{ */ + +#define ENET_QOS_MTL_TXQX_OP_MODE_FTQ_MASK (0x1U) +#define ENET_QOS_MTL_TXQX_OP_MODE_FTQ_SHIFT (0U) +/*! FTQ - Flush Transmit Queue When this bit is set, the Tx queue controller logic is reset to its default values. + * 0b0..Flush Transmit Queue is disabled + * 0b1..Flush Transmit Queue is enabled + */ +#define ENET_QOS_MTL_TXQX_OP_MODE_FTQ(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TXQX_OP_MODE_FTQ_SHIFT)) & ENET_QOS_MTL_TXQX_OP_MODE_FTQ_MASK) + +#define ENET_QOS_MTL_TXQX_OP_MODE_TSF_MASK (0x2U) +#define ENET_QOS_MTL_TXQX_OP_MODE_TSF_SHIFT (1U) +/*! TSF - Transmit Store and Forward When this bit is set, the transmission starts when a full packet resides in the MTL Tx queue. + * 0b0..Transmit Store and Forward is disabled + * 0b1..Transmit Store and Forward is enabled + */ +#define ENET_QOS_MTL_TXQX_OP_MODE_TSF(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TXQX_OP_MODE_TSF_SHIFT)) & ENET_QOS_MTL_TXQX_OP_MODE_TSF_MASK) + +#define ENET_QOS_MTL_TXQX_OP_MODE_TXQEN_MASK (0xCU) +#define ENET_QOS_MTL_TXQX_OP_MODE_TXQEN_SHIFT (2U) +/*! TXQEN - Transmit Queue Enable This field is used to enable/disable the transmit queue 0. + * 0b00..Not enabled + * 0b01..Enable in AV mode (Reserved in non-AV) + * 0b10..Enabled + * 0b11..Reserved + */ +#define ENET_QOS_MTL_TXQX_OP_MODE_TXQEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TXQX_OP_MODE_TXQEN_SHIFT)) & ENET_QOS_MTL_TXQX_OP_MODE_TXQEN_MASK) + +#define ENET_QOS_MTL_TXQX_OP_MODE_TTC_MASK (0x70U) +#define ENET_QOS_MTL_TXQX_OP_MODE_TTC_SHIFT (4U) +/*! TTC - Transmit Threshold Control These bits control the threshold level of the MTL Tx Queue. + * 0b000..32 + * 0b001..64 + * 0b010..96 + * 0b011..128 + * 0b100..192 + * 0b101..256 + * 0b110..384 + * 0b111..512 + */ +#define ENET_QOS_MTL_TXQX_OP_MODE_TTC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TXQX_OP_MODE_TTC_SHIFT)) & ENET_QOS_MTL_TXQX_OP_MODE_TTC_MASK) + +#define ENET_QOS_MTL_TXQX_OP_MODE_TQS_MASK (0x1F0000U) +#define ENET_QOS_MTL_TXQX_OP_MODE_TQS_SHIFT (16U) +/*! TQS - Transmit Queue Size This field indicates the size of the allocated Transmit queues in blocks of 256 bytes. */ +#define ENET_QOS_MTL_TXQX_OP_MODE_TQS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TXQX_OP_MODE_TQS_SHIFT)) & ENET_QOS_MTL_TXQX_OP_MODE_TQS_MASK) +/*! @} */ + +/* The count of ENET_QOS_MTL_TXQX_OP_MODE */ +#define ENET_QOS_MTL_TXQX_OP_MODE_COUNT (5U) + +/*! @name MTL_TXQX_UNDRFLW - Queue 0 Underflow Counter..Queue 4 Underflow Counter */ +/*! @{ */ + +#define ENET_QOS_MTL_TXQX_UNDRFLW_UFFRMCNT_MASK (0x7FFU) +#define ENET_QOS_MTL_TXQX_UNDRFLW_UFFRMCNT_SHIFT (0U) +/*! UFFRMCNT - Underflow Packet Counter This field indicates the number of packets aborted by the + * controller because of Tx Queue Underflow. + */ +#define ENET_QOS_MTL_TXQX_UNDRFLW_UFFRMCNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TXQX_UNDRFLW_UFFRMCNT_SHIFT)) & ENET_QOS_MTL_TXQX_UNDRFLW_UFFRMCNT_MASK) + +#define ENET_QOS_MTL_TXQX_UNDRFLW_UFCNTOVF_MASK (0x800U) +#define ENET_QOS_MTL_TXQX_UNDRFLW_UFCNTOVF_SHIFT (11U) +/*! UFCNTOVF - Overflow Bit for Underflow Packet Counter This bit is set every time the Tx queue + * Underflow Packet Counter field overflows, that is, it has crossed the maximum count. + * 0b0..Overflow not detected for Underflow Packet Counter + * 0b1..Overflow detected for Underflow Packet Counter + */ +#define ENET_QOS_MTL_TXQX_UNDRFLW_UFCNTOVF(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TXQX_UNDRFLW_UFCNTOVF_SHIFT)) & ENET_QOS_MTL_TXQX_UNDRFLW_UFCNTOVF_MASK) +/*! @} */ + +/* The count of ENET_QOS_MTL_TXQX_UNDRFLW */ +#define ENET_QOS_MTL_TXQX_UNDRFLW_COUNT (5U) + +/*! @name MTL_TXQX_DBG - Queue 0 Transmit Debug..Queue 4 Transmit Debug */ +/*! @{ */ + +#define ENET_QOS_MTL_TXQX_DBG_TXQPAUSED_MASK (0x1U) +#define ENET_QOS_MTL_TXQX_DBG_TXQPAUSED_SHIFT (0U) +/*! TXQPAUSED - Transmit Queue in Pause When this bit is high and the Rx flow control is enabled, it + * indicates that the Tx Queue is in the Pause condition (in the full-duplex only mode) because + * of the following: - Reception of the PFC packet for the priorities assigned to the Tx Queue + * when PFC is enabled - Reception of 802. + * 0b0..Transmit Queue in Pause status is not detected + * 0b1..Transmit Queue in Pause status is detected + */ +#define ENET_QOS_MTL_TXQX_DBG_TXQPAUSED(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TXQX_DBG_TXQPAUSED_SHIFT)) & ENET_QOS_MTL_TXQX_DBG_TXQPAUSED_MASK) + +#define ENET_QOS_MTL_TXQX_DBG_TRCSTS_MASK (0x6U) +#define ENET_QOS_MTL_TXQX_DBG_TRCSTS_SHIFT (1U) +/*! TRCSTS - MTL Tx Queue Read Controller Status This field indicates the state of the Tx Queue Read Controller: + * 0b00..Idle state + * 0b01..Read state (transferring data to the MAC transmitter) + * 0b10..Waiting for pending Tx Status from the MAC transmitter + * 0b11..Flushing the Tx queue because of the Packet Abort request from the MAC + */ +#define ENET_QOS_MTL_TXQX_DBG_TRCSTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TXQX_DBG_TRCSTS_SHIFT)) & ENET_QOS_MTL_TXQX_DBG_TRCSTS_MASK) + +#define ENET_QOS_MTL_TXQX_DBG_TWCSTS_MASK (0x8U) +#define ENET_QOS_MTL_TXQX_DBG_TWCSTS_SHIFT (3U) +/*! TWCSTS - MTL Tx Queue Write Controller Status When high, this bit indicates that the MTL Tx + * Queue Write Controller is active, and it is transferring the data to the Tx Queue. + * 0b0..MTL Tx Queue Write Controller status is not detected + * 0b1..MTL Tx Queue Write Controller status is detected + */ +#define ENET_QOS_MTL_TXQX_DBG_TWCSTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TXQX_DBG_TWCSTS_SHIFT)) & ENET_QOS_MTL_TXQX_DBG_TWCSTS_MASK) + +#define ENET_QOS_MTL_TXQX_DBG_TXQSTS_MASK (0x10U) +#define ENET_QOS_MTL_TXQX_DBG_TXQSTS_SHIFT (4U) +/*! TXQSTS - MTL Tx Queue Not Empty Status When this bit is high, it indicates that the MTL Tx Queue + * is not empty and some data is left for transmission. + * 0b0..MTL Tx Queue Not Empty status is not detected + * 0b1..MTL Tx Queue Not Empty status is detected + */ +#define ENET_QOS_MTL_TXQX_DBG_TXQSTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TXQX_DBG_TXQSTS_SHIFT)) & ENET_QOS_MTL_TXQX_DBG_TXQSTS_MASK) + +#define ENET_QOS_MTL_TXQX_DBG_TXSTSFSTS_MASK (0x20U) +#define ENET_QOS_MTL_TXQX_DBG_TXSTSFSTS_SHIFT (5U) +/*! TXSTSFSTS - MTL Tx Status FIFO Full Status When high, this bit indicates that the MTL Tx Status FIFO is full. + * 0b0..MTL Tx Status FIFO Full status is not detected + * 0b1..MTL Tx Status FIFO Full status is detected + */ +#define ENET_QOS_MTL_TXQX_DBG_TXSTSFSTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TXQX_DBG_TXSTSFSTS_SHIFT)) & ENET_QOS_MTL_TXQX_DBG_TXSTSFSTS_MASK) + +#define ENET_QOS_MTL_TXQX_DBG_PTXQ_MASK (0x70000U) +#define ENET_QOS_MTL_TXQX_DBG_PTXQ_SHIFT (16U) +/*! PTXQ - Number of Packets in the Transmit Queue This field indicates the current number of packets in the Tx Queue. */ +#define ENET_QOS_MTL_TXQX_DBG_PTXQ(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TXQX_DBG_PTXQ_SHIFT)) & ENET_QOS_MTL_TXQX_DBG_PTXQ_MASK) + +#define ENET_QOS_MTL_TXQX_DBG_STXSTSF_MASK (0x700000U) +#define ENET_QOS_MTL_TXQX_DBG_STXSTSF_SHIFT (20U) +/*! STXSTSF - Number of Status Words in Tx Status FIFO of Queue This field indicates the current + * number of status in the Tx Status FIFO of this queue. + */ +#define ENET_QOS_MTL_TXQX_DBG_STXSTSF(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TXQX_DBG_STXSTSF_SHIFT)) & ENET_QOS_MTL_TXQX_DBG_STXSTSF_MASK) +/*! @} */ + +/* The count of ENET_QOS_MTL_TXQX_DBG */ +#define ENET_QOS_MTL_TXQX_DBG_COUNT (5U) + +/*! @name MTL_TXQX_ETS_CTRL - Queue 1 ETS Control..Queue 4 ETS Control */ +/*! @{ */ + +#define ENET_QOS_MTL_TXQX_ETS_CTRL_AVALG_MASK (0x4U) +#define ENET_QOS_MTL_TXQX_ETS_CTRL_AVALG_SHIFT (2U) +/*! AVALG - AV Algorithm When Queue 4 is programmed for AV, this field configures the scheduling + * algorithm for this queue: This bit when set, indicates credit based shaper algorithm (CBS) is + * selected for Queue 4 traffic. + * 0b0..CBS Algorithm is disabled + * 0b1..CBS Algorithm is enabled + */ +#define ENET_QOS_MTL_TXQX_ETS_CTRL_AVALG(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TXQX_ETS_CTRL_AVALG_SHIFT)) & ENET_QOS_MTL_TXQX_ETS_CTRL_AVALG_MASK) + +#define ENET_QOS_MTL_TXQX_ETS_CTRL_CC_MASK (0x8U) +#define ENET_QOS_MTL_TXQX_ETS_CTRL_CC_SHIFT (3U) +/*! CC - Credit Control When this bit is set, the accumulated credit parameter in the credit-based + * shaper algorithm logic is not reset to zero when there is positive credit and no packet to + * transmit in Channel 4. + * 0b0..Credit Control is disabled + * 0b1..Credit Control is enabled + */ +#define ENET_QOS_MTL_TXQX_ETS_CTRL_CC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TXQX_ETS_CTRL_CC_SHIFT)) & ENET_QOS_MTL_TXQX_ETS_CTRL_CC_MASK) + +#define ENET_QOS_MTL_TXQX_ETS_CTRL_SLC_MASK (0x70U) +#define ENET_QOS_MTL_TXQX_ETS_CTRL_SLC_SHIFT (4U) +/*! SLC - Slot Count + * 0b000..1 slot + * 0b001..2 slots + * 0b010..4 slots + * 0b011..8 slots + * 0b100..16 slots + * 0b101..Reserved + */ +#define ENET_QOS_MTL_TXQX_ETS_CTRL_SLC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TXQX_ETS_CTRL_SLC_SHIFT)) & ENET_QOS_MTL_TXQX_ETS_CTRL_SLC_MASK) +/*! @} */ + +/* The count of ENET_QOS_MTL_TXQX_ETS_CTRL */ +#define ENET_QOS_MTL_TXQX_ETS_CTRL_COUNT (5U) + +/*! @name MTL_TXQX_ETS_STAT - Queue 0 ETS Status..Queue 4 ETS Status */ +/*! @{ */ + +#define ENET_QOS_MTL_TXQX_ETS_STAT_ABS_MASK (0xFFFFFFU) +#define ENET_QOS_MTL_TXQX_ETS_STAT_ABS_SHIFT (0U) +/*! ABS - Average Bits per Slot This field contains the average transmitted bits per slot. */ +#define ENET_QOS_MTL_TXQX_ETS_STAT_ABS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TXQX_ETS_STAT_ABS_SHIFT)) & ENET_QOS_MTL_TXQX_ETS_STAT_ABS_MASK) +/*! @} */ + +/* The count of ENET_QOS_MTL_TXQX_ETS_STAT */ +#define ENET_QOS_MTL_TXQX_ETS_STAT_COUNT (5U) + +/*! @name MTL_TXQX_QNTM_WGHT - Queue 0 Quantum or Weights..Queue 4 idleSlopeCredit, Quantum or Weights */ +/*! @{ */ + +#define ENET_QOS_MTL_TXQX_QNTM_WGHT_ISCQW_MASK (0x1FFFFFU) +#define ENET_QOS_MTL_TXQX_QNTM_WGHT_ISCQW_SHIFT (0U) +/*! ISCQW - Quantum or Weights When the DCB operation is enabled with DWRR algorithm for Queue 0 + * traffic, this field contains the quantum value in bytes to be added to credit during every queue + * scanning cycle. + */ +#define ENET_QOS_MTL_TXQX_QNTM_WGHT_ISCQW(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TXQX_QNTM_WGHT_ISCQW_SHIFT)) & ENET_QOS_MTL_TXQX_QNTM_WGHT_ISCQW_MASK) +/*! @} */ + +/* The count of ENET_QOS_MTL_TXQX_QNTM_WGHT */ +#define ENET_QOS_MTL_TXQX_QNTM_WGHT_COUNT (5U) + +/*! @name MTL_TXQX_SNDSLP_CRDT - Queue 1 sendSlopeCredit..Queue 4 sendSlopeCredit */ +/*! @{ */ + +#define ENET_QOS_MTL_TXQX_SNDSLP_CRDT_SSC_MASK (0x3FFFU) +#define ENET_QOS_MTL_TXQX_SNDSLP_CRDT_SSC_SHIFT (0U) +/*! SSC - sendSlopeCredit Value When AV operation is enabled, this field contains the + * sendSlopeCredit value required for credit-based shaper algorithm for Queue 4. + */ +#define ENET_QOS_MTL_TXQX_SNDSLP_CRDT_SSC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TXQX_SNDSLP_CRDT_SSC_SHIFT)) & ENET_QOS_MTL_TXQX_SNDSLP_CRDT_SSC_MASK) +/*! @} */ + +/* The count of ENET_QOS_MTL_TXQX_SNDSLP_CRDT */ +#define ENET_QOS_MTL_TXQX_SNDSLP_CRDT_COUNT (5U) + +/*! @name MTL_TXQX_HI_CRDT - Queue 1 hiCredit..Queue 4 hiCredit */ +/*! @{ */ + +#define ENET_QOS_MTL_TXQX_HI_CRDT_HC_MASK (0x1FFFFFFFU) +#define ENET_QOS_MTL_TXQX_HI_CRDT_HC_SHIFT (0U) +/*! HC - hiCredit Value When the AV feature is enabled, this field contains the hiCredit value + * required for the credit-based shaper algorithm. + */ +#define ENET_QOS_MTL_TXQX_HI_CRDT_HC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TXQX_HI_CRDT_HC_SHIFT)) & ENET_QOS_MTL_TXQX_HI_CRDT_HC_MASK) +/*! @} */ + +/* The count of ENET_QOS_MTL_TXQX_HI_CRDT */ +#define ENET_QOS_MTL_TXQX_HI_CRDT_COUNT (5U) + +/*! @name MTL_TXQX_LO_CRDT - Queue 1 loCredit..Queue 4 loCredit */ +/*! @{ */ + +#define ENET_QOS_MTL_TXQX_LO_CRDT_LC_MASK (0x1FFFFFFFU) +#define ENET_QOS_MTL_TXQX_LO_CRDT_LC_SHIFT (0U) +/*! LC - loCredit Value When AV operation is enabled, this field contains the loCredit value + * required for the credit-based shaper algorithm. + */ +#define ENET_QOS_MTL_TXQX_LO_CRDT_LC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TXQX_LO_CRDT_LC_SHIFT)) & ENET_QOS_MTL_TXQX_LO_CRDT_LC_MASK) +/*! @} */ + +/* The count of ENET_QOS_MTL_TXQX_LO_CRDT */ +#define ENET_QOS_MTL_TXQX_LO_CRDT_COUNT (5U) + +/*! @name MTL_TXQX_INTCTRL_STAT - Queue 0 Interrupt Control Status..Queue 4 Interrupt Control Status */ +/*! @{ */ + +#define ENET_QOS_MTL_TXQX_INTCTRL_STAT_TXUNFIS_MASK (0x1U) +#define ENET_QOS_MTL_TXQX_INTCTRL_STAT_TXUNFIS_SHIFT (0U) +/*! TXUNFIS - Transmit Queue Underflow Interrupt Status This bit indicates that the Transmit Queue + * had an underflow while transmitting the packet. + * 0b0..Transmit Queue Underflow Interrupt Status not detected + * 0b1..Transmit Queue Underflow Interrupt Status detected + */ +#define ENET_QOS_MTL_TXQX_INTCTRL_STAT_TXUNFIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TXQX_INTCTRL_STAT_TXUNFIS_SHIFT)) & ENET_QOS_MTL_TXQX_INTCTRL_STAT_TXUNFIS_MASK) + +#define ENET_QOS_MTL_TXQX_INTCTRL_STAT_ABPSIS_MASK (0x2U) +#define ENET_QOS_MTL_TXQX_INTCTRL_STAT_ABPSIS_SHIFT (1U) +/*! ABPSIS - Average Bits Per Slot Interrupt Status When set, this bit indicates that the MAC has updated the ABS value. + * 0b0..Average Bits Per Slot Interrupt Status not detected + * 0b1..Average Bits Per Slot Interrupt Status detected + */ +#define ENET_QOS_MTL_TXQX_INTCTRL_STAT_ABPSIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TXQX_INTCTRL_STAT_ABPSIS_SHIFT)) & ENET_QOS_MTL_TXQX_INTCTRL_STAT_ABPSIS_MASK) + +#define ENET_QOS_MTL_TXQX_INTCTRL_STAT_TXUIE_MASK (0x100U) +#define ENET_QOS_MTL_TXQX_INTCTRL_STAT_TXUIE_SHIFT (8U) +/*! TXUIE - Transmit Queue Underflow Interrupt Enable When this bit is set, the Transmit Queue Underflow interrupt is enabled. + * 0b0..Transmit Queue Underflow Interrupt Status is disabled + * 0b1..Transmit Queue Underflow Interrupt Status is enabled + */ +#define ENET_QOS_MTL_TXQX_INTCTRL_STAT_TXUIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TXQX_INTCTRL_STAT_TXUIE_SHIFT)) & ENET_QOS_MTL_TXQX_INTCTRL_STAT_TXUIE_MASK) + +#define ENET_QOS_MTL_TXQX_INTCTRL_STAT_ABPSIE_MASK (0x200U) +#define ENET_QOS_MTL_TXQX_INTCTRL_STAT_ABPSIE_SHIFT (9U) +/*! ABPSIE - Average Bits Per Slot Interrupt Enable When this bit is set, the MAC asserts the + * sbd_intr_o or mci_intr_o interrupt when the average bits per slot status is updated. + * 0b0..Average Bits Per Slot Interrupt is disabled + * 0b1..Average Bits Per Slot Interrupt is enabled + */ +#define ENET_QOS_MTL_TXQX_INTCTRL_STAT_ABPSIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TXQX_INTCTRL_STAT_ABPSIE_SHIFT)) & ENET_QOS_MTL_TXQX_INTCTRL_STAT_ABPSIE_MASK) + +#define ENET_QOS_MTL_TXQX_INTCTRL_STAT_RXOVFIS_MASK (0x10000U) +#define ENET_QOS_MTL_TXQX_INTCTRL_STAT_RXOVFIS_SHIFT (16U) +/*! RXOVFIS - Receive Queue Overflow Interrupt Status This bit indicates that the Receive Queue had + * an overflow while receiving the packet. + * 0b0..Receive Queue Overflow Interrupt Status not detected + * 0b1..Receive Queue Overflow Interrupt Status detected + */ +#define ENET_QOS_MTL_TXQX_INTCTRL_STAT_RXOVFIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TXQX_INTCTRL_STAT_RXOVFIS_SHIFT)) & ENET_QOS_MTL_TXQX_INTCTRL_STAT_RXOVFIS_MASK) + +#define ENET_QOS_MTL_TXQX_INTCTRL_STAT_RXOIE_MASK (0x1000000U) +#define ENET_QOS_MTL_TXQX_INTCTRL_STAT_RXOIE_SHIFT (24U) +/*! RXOIE - Receive Queue Overflow Interrupt Enable When this bit is set, the Receive Queue Overflow interrupt is enabled. + * 0b0..Receive Queue Overflow Interrupt is disabled + * 0b1..Receive Queue Overflow Interrupt is enabled + */ +#define ENET_QOS_MTL_TXQX_INTCTRL_STAT_RXOIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TXQX_INTCTRL_STAT_RXOIE_SHIFT)) & ENET_QOS_MTL_TXQX_INTCTRL_STAT_RXOIE_MASK) +/*! @} */ + +/* The count of ENET_QOS_MTL_TXQX_INTCTRL_STAT */ +#define ENET_QOS_MTL_TXQX_INTCTRL_STAT_COUNT (5U) + +/*! @name MTL_RXQX_OP_MODE - Queue 0 Receive Operation Mode..Queue 4 Receive Operation Mode */ +/*! @{ */ + +#define ENET_QOS_MTL_RXQX_OP_MODE_RTC_MASK (0x3U) +#define ENET_QOS_MTL_RXQX_OP_MODE_RTC_SHIFT (0U) +/*! RTC - Receive Queue Threshold Control These bits control the threshold level of the MTL Rx queue + * (in bytes): The received packet is transferred to the application or DMA when the packet size + * within the MTL Rx queue is larger than the threshold. + * 0b00..64 + * 0b01..32 + * 0b10..96 + * 0b11..128 + */ +#define ENET_QOS_MTL_RXQX_OP_MODE_RTC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXQX_OP_MODE_RTC_SHIFT)) & ENET_QOS_MTL_RXQX_OP_MODE_RTC_MASK) + +#define ENET_QOS_MTL_RXQX_OP_MODE_FUP_MASK (0x8U) +#define ENET_QOS_MTL_RXQX_OP_MODE_FUP_SHIFT (3U) +/*! FUP - Forward Undersized Good Packets When this bit is set, the Rx queue forwards the undersized + * good packets (packets with no error and length less than 64 bytes), including pad-bytes and + * CRC. + * 0b0..Forward Undersized Good Packets is disabled + * 0b1..Forward Undersized Good Packets is enabled + */ +#define ENET_QOS_MTL_RXQX_OP_MODE_FUP(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXQX_OP_MODE_FUP_SHIFT)) & ENET_QOS_MTL_RXQX_OP_MODE_FUP_MASK) + +#define ENET_QOS_MTL_RXQX_OP_MODE_FEP_MASK (0x10U) +#define ENET_QOS_MTL_RXQX_OP_MODE_FEP_SHIFT (4U) +/*! FEP - Forward Error Packets When this bit is reset, the Rx queue drops packets with error status + * (CRC error, GMII_ER, watchdog timeout, or overflow). + * 0b0..Forward Error Packets is disabled + * 0b1..Forward Error Packets is enabled + */ +#define ENET_QOS_MTL_RXQX_OP_MODE_FEP(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXQX_OP_MODE_FEP_SHIFT)) & ENET_QOS_MTL_RXQX_OP_MODE_FEP_MASK) + +#define ENET_QOS_MTL_RXQX_OP_MODE_RSF_MASK (0x20U) +#define ENET_QOS_MTL_RXQX_OP_MODE_RSF_SHIFT (5U) +/*! RSF - Receive Queue Store and Forward When this bit is set, the DWC_ether_qos reads a packet + * from the Rx queue only after the complete packet has been written to it, ignoring the RTC field + * of this register. + * 0b0..Receive Queue Store and Forward is disabled + * 0b1..Receive Queue Store and Forward is enabled + */ +#define ENET_QOS_MTL_RXQX_OP_MODE_RSF(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXQX_OP_MODE_RSF_SHIFT)) & ENET_QOS_MTL_RXQX_OP_MODE_RSF_MASK) + +#define ENET_QOS_MTL_RXQX_OP_MODE_DIS_TCP_EF_MASK (0x40U) +#define ENET_QOS_MTL_RXQX_OP_MODE_DIS_TCP_EF_SHIFT (6U) +/*! DIS_TCP_EF - Disable Dropping of TCP/IP Checksum Error Packets When this bit is set, the MAC + * does not drop the packets which only have the errors detected by the Receive Checksum Offload + * engine. + * 0b0..Dropping of TCP/IP Checksum Error Packets is enabled + * 0b1..Dropping of TCP/IP Checksum Error Packets is disabled + */ +#define ENET_QOS_MTL_RXQX_OP_MODE_DIS_TCP_EF(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXQX_OP_MODE_DIS_TCP_EF_SHIFT)) & ENET_QOS_MTL_RXQX_OP_MODE_DIS_TCP_EF_MASK) + +#define ENET_QOS_MTL_RXQX_OP_MODE_EHFC_MASK (0x80U) +#define ENET_QOS_MTL_RXQX_OP_MODE_EHFC_SHIFT (7U) +/*! EHFC - Enable Hardware Flow Control When this bit is set, the flow control signal operation, + * based on the fill-level of Rx queue, is enabled. + * 0b0..Hardware Flow Control is disabled + * 0b1..Hardware Flow Control is enabled + */ +#define ENET_QOS_MTL_RXQX_OP_MODE_EHFC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXQX_OP_MODE_EHFC_SHIFT)) & ENET_QOS_MTL_RXQX_OP_MODE_EHFC_MASK) + +#define ENET_QOS_MTL_RXQX_OP_MODE_RFA_MASK (0xF00U) +#define ENET_QOS_MTL_RXQX_OP_MODE_RFA_SHIFT (8U) +/*! RFA - Threshold for Activating Flow Control (in half-duplex and full-duplex These bits control + * the threshold (fill-level of Rx queue) at which the flow control is activated: For more + * information on encoding for this field, see RFD. + */ +#define ENET_QOS_MTL_RXQX_OP_MODE_RFA(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXQX_OP_MODE_RFA_SHIFT)) & ENET_QOS_MTL_RXQX_OP_MODE_RFA_MASK) + +#define ENET_QOS_MTL_RXQX_OP_MODE_RFD_MASK (0x3C000U) +#define ENET_QOS_MTL_RXQX_OP_MODE_RFD_SHIFT (14U) +/*! RFD - Threshold for Deactivating Flow Control (in half-duplex and full-duplex modes) These bits + * control the threshold (fill-level of Rx queue) at which the flow control is de-asserted after + * activation: - 0: Full minus 1 KB, that is, FULL 1 KB - 1: Full minus 1. + */ +#define ENET_QOS_MTL_RXQX_OP_MODE_RFD(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXQX_OP_MODE_RFD_SHIFT)) & ENET_QOS_MTL_RXQX_OP_MODE_RFD_MASK) + +#define ENET_QOS_MTL_RXQX_OP_MODE_RQS_MASK (0x1F00000U) +#define ENET_QOS_MTL_RXQX_OP_MODE_RQS_SHIFT (20U) +/*! RQS - Receive Queue Size This field indicates the size of the allocated Receive queues in blocks of 256 bytes. */ +#define ENET_QOS_MTL_RXQX_OP_MODE_RQS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXQX_OP_MODE_RQS_SHIFT)) & ENET_QOS_MTL_RXQX_OP_MODE_RQS_MASK) +/*! @} */ + +/* The count of ENET_QOS_MTL_RXQX_OP_MODE */ +#define ENET_QOS_MTL_RXQX_OP_MODE_COUNT (5U) + +/*! @name MTL_RXQX_MISSPKT_OVRFLW_CNT - Queue 0 Missed Packet and Overflow Counter..Queue 4 Missed Packet and Overflow Counter */ +/*! @{ */ + +#define ENET_QOS_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFPKTCNT_MASK (0x7FFU) +#define ENET_QOS_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFPKTCNT_SHIFT (0U) +/*! OVFPKTCNT - Overflow Packet Counter This field indicates the number of packets discarded by the + * DWC_ether_qos because of Receive queue overflow. + */ +#define ENET_QOS_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFPKTCNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFPKTCNT_SHIFT)) & ENET_QOS_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFPKTCNT_MASK) + +#define ENET_QOS_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFCNTOVF_MASK (0x800U) +#define ENET_QOS_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFCNTOVF_SHIFT (11U) +/*! OVFCNTOVF - Overflow Counter Overflow Bit When set, this bit indicates that the Rx Queue + * Overflow Packet Counter field crossed the maximum limit. + * 0b0..Overflow Counter overflow not detected + * 0b1..Overflow Counter overflow detected + */ +#define ENET_QOS_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFCNTOVF(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFCNTOVF_SHIFT)) & ENET_QOS_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFCNTOVF_MASK) + +#define ENET_QOS_MTL_RXQX_MISSPKT_OVRFLW_CNT_MISPKTCNT_MASK (0x7FF0000U) +#define ENET_QOS_MTL_RXQX_MISSPKT_OVRFLW_CNT_MISPKTCNT_SHIFT (16U) +/*! MISPKTCNT - Missed Packet Counter This field indicates the number of packets missed by the + * DWC_ether_qos because the application asserted ari_pkt_flush_i[] for this queue. + */ +#define ENET_QOS_MTL_RXQX_MISSPKT_OVRFLW_CNT_MISPKTCNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXQX_MISSPKT_OVRFLW_CNT_MISPKTCNT_SHIFT)) & ENET_QOS_MTL_RXQX_MISSPKT_OVRFLW_CNT_MISPKTCNT_MASK) + +#define ENET_QOS_MTL_RXQX_MISSPKT_OVRFLW_CNT_MISCNTOVF_MASK (0x8000000U) +#define ENET_QOS_MTL_RXQX_MISSPKT_OVRFLW_CNT_MISCNTOVF_SHIFT (27U) +/*! MISCNTOVF - Missed Packet Counter Overflow Bit When set, this bit indicates that the Rx Queue + * Missed Packet Counter crossed the maximum limit. + * 0b0..Missed Packet Counter overflow not detected + * 0b1..Missed Packet Counter overflow detected + */ +#define ENET_QOS_MTL_RXQX_MISSPKT_OVRFLW_CNT_MISCNTOVF(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXQX_MISSPKT_OVRFLW_CNT_MISCNTOVF_SHIFT)) & ENET_QOS_MTL_RXQX_MISSPKT_OVRFLW_CNT_MISCNTOVF_MASK) +/*! @} */ + +/* The count of ENET_QOS_MTL_RXQX_MISSPKT_OVRFLW_CNT */ +#define ENET_QOS_MTL_RXQX_MISSPKT_OVRFLW_CNT_COUNT (5U) + +/*! @name MTL_RXQX_DBG - Queue 0 Receive Debug..Queue 4 Receive Debug */ +/*! @{ */ + +#define ENET_QOS_MTL_RXQX_DBG_RWCSTS_MASK (0x1U) +#define ENET_QOS_MTL_RXQX_DBG_RWCSTS_SHIFT (0U) +/*! RWCSTS - MTL Rx Queue Write Controller Active Status When high, this bit indicates that the MTL + * Rx queue Write controller is active, and it is transferring a received packet to the Rx Queue. + * 0b0..MTL Rx Queue Write Controller Active Status not detected + * 0b1..MTL Rx Queue Write Controller Active Status detected + */ +#define ENET_QOS_MTL_RXQX_DBG_RWCSTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXQX_DBG_RWCSTS_SHIFT)) & ENET_QOS_MTL_RXQX_DBG_RWCSTS_MASK) + +#define ENET_QOS_MTL_RXQX_DBG_RRCSTS_MASK (0x6U) +#define ENET_QOS_MTL_RXQX_DBG_RRCSTS_SHIFT (1U) +/*! RRCSTS - MTL Rx Queue Read Controller State This field gives the state of the Rx queue Read controller: + * 0b00..Idle state + * 0b01..Reading packet data + * 0b10..Reading packet status (or timestamp) + * 0b11..Flushing the packet data and status + */ +#define ENET_QOS_MTL_RXQX_DBG_RRCSTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXQX_DBG_RRCSTS_SHIFT)) & ENET_QOS_MTL_RXQX_DBG_RRCSTS_MASK) + +#define ENET_QOS_MTL_RXQX_DBG_RXQSTS_MASK (0x30U) +#define ENET_QOS_MTL_RXQX_DBG_RXQSTS_SHIFT (4U) +/*! RXQSTS - MTL Rx Queue Fill-Level Status This field gives the status of the fill-level of the Rx Queue: + * 0b00..Rx Queue empty + * 0b01..Rx Queue fill-level below flow-control deactivate threshold + * 0b10..Rx Queue fill-level above flow-control activate threshold + * 0b11..Rx Queue full + */ +#define ENET_QOS_MTL_RXQX_DBG_RXQSTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXQX_DBG_RXQSTS_SHIFT)) & ENET_QOS_MTL_RXQX_DBG_RXQSTS_MASK) + +#define ENET_QOS_MTL_RXQX_DBG_PRXQ_MASK (0x3FFF0000U) +#define ENET_QOS_MTL_RXQX_DBG_PRXQ_SHIFT (16U) +/*! PRXQ - Number of Packets in Receive Queue This field indicates the current number of packets in the Rx Queue. */ +#define ENET_QOS_MTL_RXQX_DBG_PRXQ(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXQX_DBG_PRXQ_SHIFT)) & ENET_QOS_MTL_RXQX_DBG_PRXQ_MASK) +/*! @} */ + +/* The count of ENET_QOS_MTL_RXQX_DBG */ +#define ENET_QOS_MTL_RXQX_DBG_COUNT (5U) + +/*! @name MTL_RXQX_CTRL - Queue 0 Receive Control..Queue 4 Receive Control */ +/*! @{ */ + +#define ENET_QOS_MTL_RXQX_CTRL_RXQ_WEGT_MASK (0x7U) +#define ENET_QOS_MTL_RXQX_CTRL_RXQ_WEGT_SHIFT (0U) +/*! RXQ_WEGT - Receive Queue Weight This field indicates the weight assigned to the Rx Queue 4. */ +#define ENET_QOS_MTL_RXQX_CTRL_RXQ_WEGT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXQX_CTRL_RXQ_WEGT_SHIFT)) & ENET_QOS_MTL_RXQX_CTRL_RXQ_WEGT_MASK) + +#define ENET_QOS_MTL_RXQX_CTRL_RXQ_FRM_ARBIT_MASK (0x8U) +#define ENET_QOS_MTL_RXQX_CTRL_RXQ_FRM_ARBIT_SHIFT (3U) +/*! RXQ_FRM_ARBIT - Receive Queue Packet Arbitration When this bit is set, the DWC_ether_qos drives + * the packet data to the ARI interface such that the entire packet data of currently-selected + * queue is transmitted before switching to other queue. + * 0b0..Receive Queue Packet Arbitration is disabled + * 0b1..Receive Queue Packet Arbitration is enabled + */ +#define ENET_QOS_MTL_RXQX_CTRL_RXQ_FRM_ARBIT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXQX_CTRL_RXQ_FRM_ARBIT_SHIFT)) & ENET_QOS_MTL_RXQX_CTRL_RXQ_FRM_ARBIT_MASK) +/*! @} */ + +/* The count of ENET_QOS_MTL_RXQX_CTRL */ +#define ENET_QOS_MTL_RXQX_CTRL_COUNT (5U) + +/*! @name DMA_MODE - DMA Bus Mode */ +/*! @{ */ + +#define ENET_QOS_DMA_MODE_SWR_MASK (0x1U) +#define ENET_QOS_DMA_MODE_SWR_SHIFT (0U) +/*! SWR - Software Reset When this bit is set, the MAC and the DMA controller reset the logic and + * all internal registers of the DMA, MTL, and MAC. + * 0b0..Software Reset is disabled + * 0b1..Software Reset is enabled + */ +#define ENET_QOS_DMA_MODE_SWR(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_MODE_SWR_SHIFT)) & ENET_QOS_DMA_MODE_SWR_MASK) + +#define ENET_QOS_DMA_MODE_DSPW_MASK (0x100U) +#define ENET_QOS_DMA_MODE_DSPW_SHIFT (8U) +/*! DSPW - Descriptor Posted Write When this bit is set to 0, the descriptor writes are always non-posted. + * 0b0..Descriptor Posted Write is disabled + * 0b1..Descriptor Posted Write is enabled + */ +#define ENET_QOS_DMA_MODE_DSPW(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_MODE_DSPW_SHIFT)) & ENET_QOS_DMA_MODE_DSPW_MASK) + +#define ENET_QOS_DMA_MODE_INTM_MASK (0x30000U) +#define ENET_QOS_DMA_MODE_INTM_SHIFT (16U) +/*! INTM - Interrupt Mode This field defines the interrupt mode of DWC_ether_qos. + * 0b00..See above description + * 0b01..See above description + * 0b10..See above description + * 0b11..Reserved + */ +#define ENET_QOS_DMA_MODE_INTM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_MODE_INTM_SHIFT)) & ENET_QOS_DMA_MODE_INTM_MASK) +/*! @} */ + +/*! @name DMA_SYSBUS_MODE - DMA System Bus Mode */ +/*! @{ */ + +#define ENET_QOS_DMA_SYSBUS_MODE_FB_MASK (0x1U) +#define ENET_QOS_DMA_SYSBUS_MODE_FB_SHIFT (0U) +/*! FB - Fixed Burst Length When this bit is set to 1, the EQOS-AXI master initiates burst transfers + * of specified lengths as given below. + * 0b0..Fixed Burst Length is disabled + * 0b1..Fixed Burst Length is enabled + */ +#define ENET_QOS_DMA_SYSBUS_MODE_FB(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_SYSBUS_MODE_FB_SHIFT)) & ENET_QOS_DMA_SYSBUS_MODE_FB_MASK) + +#define ENET_QOS_DMA_SYSBUS_MODE_BLEN4_MASK (0x2U) +#define ENET_QOS_DMA_SYSBUS_MODE_BLEN4_SHIFT (1U) +/*! BLEN4 - AXI Burst Length 4 When this bit is set to 1 or the FB bit is set to 0, the EQOS-AXI + * master can select a burst length of 4 on the AXI interface. + * 0b0..No effect + * 0b1..AXI Burst Length 4 + */ +#define ENET_QOS_DMA_SYSBUS_MODE_BLEN4(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_SYSBUS_MODE_BLEN4_SHIFT)) & ENET_QOS_DMA_SYSBUS_MODE_BLEN4_MASK) + +#define ENET_QOS_DMA_SYSBUS_MODE_BLEN8_MASK (0x4U) +#define ENET_QOS_DMA_SYSBUS_MODE_BLEN8_SHIFT (2U) +/*! BLEN8 - AXI Burst Length 8 When this bit is set to 1 or the FB bit is set to 0, the EQOS-AXI + * master can select a burst length of 8 on the AXI interface. + * 0b0..No effect + * 0b1..AXI Burst Length 8 + */ +#define ENET_QOS_DMA_SYSBUS_MODE_BLEN8(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_SYSBUS_MODE_BLEN8_SHIFT)) & ENET_QOS_DMA_SYSBUS_MODE_BLEN8_MASK) + +#define ENET_QOS_DMA_SYSBUS_MODE_BLEN16_MASK (0x8U) +#define ENET_QOS_DMA_SYSBUS_MODE_BLEN16_SHIFT (3U) +/*! BLEN16 - AXI Burst Length 16 When this bit is set to 1 or the FB bit is set to 0, the EQOS-AXI + * master can select a burst length of 16 on the AXI interface. + * 0b0..No effect + * 0b1..AXI Burst Length 16 + */ +#define ENET_QOS_DMA_SYSBUS_MODE_BLEN16(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_SYSBUS_MODE_BLEN16_SHIFT)) & ENET_QOS_DMA_SYSBUS_MODE_BLEN16_MASK) + +#define ENET_QOS_DMA_SYSBUS_MODE_AALE_MASK (0x400U) +#define ENET_QOS_DMA_SYSBUS_MODE_AALE_SHIFT (10U) +/*! AALE - Automatic AXI LPI enable When set to 1, enables the AXI master to enter into LPI state + * when there is no activity in the DWC_ether_qos for number of system clock cycles programmed in + * the LPIEI field of DMA_AXI_LPI_ENTRY_INTERVAL register. + * 0b0..Automatic AXI LPI is disabled + * 0b1..Automatic AXI LPI is enabled + */ +#define ENET_QOS_DMA_SYSBUS_MODE_AALE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_SYSBUS_MODE_AALE_SHIFT)) & ENET_QOS_DMA_SYSBUS_MODE_AALE_MASK) + +#define ENET_QOS_DMA_SYSBUS_MODE_AAL_MASK (0x1000U) +#define ENET_QOS_DMA_SYSBUS_MODE_AAL_SHIFT (12U) +/*! AAL - Address-Aligned Beats When this bit is set to 1, the EQOS-AXI or EQOS-AHB master performs + * address-aligned burst transfers on Read and Write channels. + * 0b0..Address-Aligned Beats is disabled + * 0b1..Address-Aligned Beats is enabled + */ +#define ENET_QOS_DMA_SYSBUS_MODE_AAL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_SYSBUS_MODE_AAL_SHIFT)) & ENET_QOS_DMA_SYSBUS_MODE_AAL_MASK) + +#define ENET_QOS_DMA_SYSBUS_MODE_ONEKBBE_MASK (0x2000U) +#define ENET_QOS_DMA_SYSBUS_MODE_ONEKBBE_SHIFT (13U) +/*! ONEKBBE - 1 KB Boundary Crossing Enable for the EQOS-AXI Master When set, the burst transfers + * performed by the EQOS-AXI master do not cross 1 KB boundary. + * 0b0..1 KB Boundary Crossing for the EQOS-AXI Master Beats is disabled + * 0b1..1 KB Boundary Crossing for the EQOS-AXI Master Beats is enabled + */ +#define ENET_QOS_DMA_SYSBUS_MODE_ONEKBBE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_SYSBUS_MODE_ONEKBBE_SHIFT)) & ENET_QOS_DMA_SYSBUS_MODE_ONEKBBE_MASK) + +#define ENET_QOS_DMA_SYSBUS_MODE_RD_OSR_LMT_MASK (0xF0000U) +#define ENET_QOS_DMA_SYSBUS_MODE_RD_OSR_LMT_SHIFT (16U) +/*! RD_OSR_LMT - AXI Maximum Read Outstanding Request Limit This value limits the maximum outstanding request on the AXI read interface. */ +#define ENET_QOS_DMA_SYSBUS_MODE_RD_OSR_LMT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_SYSBUS_MODE_RD_OSR_LMT_SHIFT)) & ENET_QOS_DMA_SYSBUS_MODE_RD_OSR_LMT_MASK) + +#define ENET_QOS_DMA_SYSBUS_MODE_WR_OSR_LMT_MASK (0xF000000U) +#define ENET_QOS_DMA_SYSBUS_MODE_WR_OSR_LMT_SHIFT (24U) +/*! WR_OSR_LMT - AXI Maximum Write Outstanding Request Limit This value limits the maximum + * outstanding request on the AXI write interface. + */ +#define ENET_QOS_DMA_SYSBUS_MODE_WR_OSR_LMT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_SYSBUS_MODE_WR_OSR_LMT_SHIFT)) & ENET_QOS_DMA_SYSBUS_MODE_WR_OSR_LMT_MASK) + +#define ENET_QOS_DMA_SYSBUS_MODE_LPI_XIT_PKT_MASK (0x40000000U) +#define ENET_QOS_DMA_SYSBUS_MODE_LPI_XIT_PKT_SHIFT (30U) +/*! LPI_XIT_PKT - Unlock on Magic Packet or Remote Wake-Up Packet When set to 1, this bit enables + * the AXI master to come out of the LPI mode only when the magic packet or remote wake-up packet + * is received. + * 0b0..Unlock on Magic Packet or Remote Wake-Up Packet is disabled + * 0b1..Unlock on Magic Packet or Remote Wake-Up Packet is enabled + */ +#define ENET_QOS_DMA_SYSBUS_MODE_LPI_XIT_PKT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_SYSBUS_MODE_LPI_XIT_PKT_SHIFT)) & ENET_QOS_DMA_SYSBUS_MODE_LPI_XIT_PKT_MASK) + +#define ENET_QOS_DMA_SYSBUS_MODE_EN_LPI_MASK (0x80000000U) +#define ENET_QOS_DMA_SYSBUS_MODE_EN_LPI_SHIFT (31U) +/*! EN_LPI - Enable Low Power Interface (LPI) When set to 1, this bit enables the LPI mode supported + * by the EQOS-AXI configuration and accepts the LPI request from the AXI System Clock + * controller. + * 0b0..Low Power Interface (LPI) is disabled + * 0b1..Low Power Interface (LPI) is enabled + */ +#define ENET_QOS_DMA_SYSBUS_MODE_EN_LPI(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_SYSBUS_MODE_EN_LPI_SHIFT)) & ENET_QOS_DMA_SYSBUS_MODE_EN_LPI_MASK) +/*! @} */ + +/*! @name DMA_INTERRUPT_STATUS - DMA Interrupt Status */ +/*! @{ */ + +#define ENET_QOS_DMA_INTERRUPT_STATUS_DC0IS_MASK (0x1U) +#define ENET_QOS_DMA_INTERRUPT_STATUS_DC0IS_SHIFT (0U) +/*! DC0IS - DMA Channel 0 Interrupt Status This bit indicates an interrupt event in DMA Channel 0. + * 0b0..DMA Channel 0 Interrupt Status not detected + * 0b1..DMA Channel 0 Interrupt Status detected + */ +#define ENET_QOS_DMA_INTERRUPT_STATUS_DC0IS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_INTERRUPT_STATUS_DC0IS_SHIFT)) & ENET_QOS_DMA_INTERRUPT_STATUS_DC0IS_MASK) + +#define ENET_QOS_DMA_INTERRUPT_STATUS_DC1IS_MASK (0x2U) +#define ENET_QOS_DMA_INTERRUPT_STATUS_DC1IS_SHIFT (1U) +/*! DC1IS - DMA Channel 1 Interrupt Status This bit indicates an interrupt event in DMA Channel 1. + * 0b0..DMA Channel 1 Interrupt Status not detected + * 0b1..DMA Channel 1 Interrupt Status detected + */ +#define ENET_QOS_DMA_INTERRUPT_STATUS_DC1IS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_INTERRUPT_STATUS_DC1IS_SHIFT)) & ENET_QOS_DMA_INTERRUPT_STATUS_DC1IS_MASK) + +#define ENET_QOS_DMA_INTERRUPT_STATUS_DC2IS_MASK (0x4U) +#define ENET_QOS_DMA_INTERRUPT_STATUS_DC2IS_SHIFT (2U) +/*! DC2IS - DMA Channel 2 Interrupt Status This bit indicates an interrupt event in DMA Channel 2. + * 0b0..DMA Channel 2 Interrupt Status not detected + * 0b1..DMA Channel 2 Interrupt Status detected + */ +#define ENET_QOS_DMA_INTERRUPT_STATUS_DC2IS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_INTERRUPT_STATUS_DC2IS_SHIFT)) & ENET_QOS_DMA_INTERRUPT_STATUS_DC2IS_MASK) + +#define ENET_QOS_DMA_INTERRUPT_STATUS_DC3IS_MASK (0x8U) +#define ENET_QOS_DMA_INTERRUPT_STATUS_DC3IS_SHIFT (3U) +/*! DC3IS - DMA Channel 3 Interrupt Status This bit indicates an interrupt event in DMA Channel 3. + * 0b0..DMA Channel 3 Interrupt Status not detected + * 0b1..DMA Channel 3 Interrupt Status detected + */ +#define ENET_QOS_DMA_INTERRUPT_STATUS_DC3IS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_INTERRUPT_STATUS_DC3IS_SHIFT)) & ENET_QOS_DMA_INTERRUPT_STATUS_DC3IS_MASK) + +#define ENET_QOS_DMA_INTERRUPT_STATUS_DC4IS_MASK (0x10U) +#define ENET_QOS_DMA_INTERRUPT_STATUS_DC4IS_SHIFT (4U) +/*! DC4IS - DMA Channel 4 Interrupt Status This bit indicates an interrupt event in DMA Channel 4. + * 0b0..DMA Channel 4 Interrupt Status not detected + * 0b1..DMA Channel 4 Interrupt Status detected + */ +#define ENET_QOS_DMA_INTERRUPT_STATUS_DC4IS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_INTERRUPT_STATUS_DC4IS_SHIFT)) & ENET_QOS_DMA_INTERRUPT_STATUS_DC4IS_MASK) + +#define ENET_QOS_DMA_INTERRUPT_STATUS_MTLIS_MASK (0x10000U) +#define ENET_QOS_DMA_INTERRUPT_STATUS_MTLIS_SHIFT (16U) +/*! MTLIS - MTL Interrupt Status This bit indicates an interrupt event in the MTL. + * 0b0..MTL Interrupt Status not detected + * 0b1..MTL Interrupt Status detected + */ +#define ENET_QOS_DMA_INTERRUPT_STATUS_MTLIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_INTERRUPT_STATUS_MTLIS_SHIFT)) & ENET_QOS_DMA_INTERRUPT_STATUS_MTLIS_MASK) + +#define ENET_QOS_DMA_INTERRUPT_STATUS_MACIS_MASK (0x20000U) +#define ENET_QOS_DMA_INTERRUPT_STATUS_MACIS_SHIFT (17U) +/*! MACIS - MAC Interrupt Status This bit indicates an interrupt event in the MAC. + * 0b0..MAC Interrupt Status not detected + * 0b1..MAC Interrupt Status detected + */ +#define ENET_QOS_DMA_INTERRUPT_STATUS_MACIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_INTERRUPT_STATUS_MACIS_SHIFT)) & ENET_QOS_DMA_INTERRUPT_STATUS_MACIS_MASK) +/*! @} */ + +/*! @name DMA_DEBUG_STATUS0 - DMA Debug Status 0 */ +/*! @{ */ + +#define ENET_QOS_DMA_DEBUG_STATUS0_AXWHSTS_MASK (0x1U) +#define ENET_QOS_DMA_DEBUG_STATUS0_AXWHSTS_SHIFT (0U) +/*! AXWHSTS - AXI Master Write Channel When high, this bit indicates that the write channel of the + * AXI master is active, and it is transferring data. + * 0b0..AXI Master Write Channel or AHB Master Status not detected + * 0b1..AXI Master Write Channel or AHB Master Status detected + */ +#define ENET_QOS_DMA_DEBUG_STATUS0_AXWHSTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_DEBUG_STATUS0_AXWHSTS_SHIFT)) & ENET_QOS_DMA_DEBUG_STATUS0_AXWHSTS_MASK) + +#define ENET_QOS_DMA_DEBUG_STATUS0_AXRHSTS_MASK (0x2U) +#define ENET_QOS_DMA_DEBUG_STATUS0_AXRHSTS_SHIFT (1U) +/*! AXRHSTS - AXI Master Read Channel Status When high, this bit indicates that the read channel of + * the AXI master is active, and it is transferring the data. + * 0b0..AXI Master Read Channel Status not detected + * 0b1..AXI Master Read Channel Status detected + */ +#define ENET_QOS_DMA_DEBUG_STATUS0_AXRHSTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_DEBUG_STATUS0_AXRHSTS_SHIFT)) & ENET_QOS_DMA_DEBUG_STATUS0_AXRHSTS_MASK) + +#define ENET_QOS_DMA_DEBUG_STATUS0_RPS0_MASK (0xF00U) +#define ENET_QOS_DMA_DEBUG_STATUS0_RPS0_SHIFT (8U) +/*! RPS0 - DMA Channel 0 Receive Process State This field indicates the Rx DMA FSM state for Channel 0. + * 0b0000..Stopped (Reset or Stop Receive Command issued) + * 0b0001..Running (Fetching Rx Transfer Descriptor) + * 0b0010..Reserved for future use + * 0b0011..Running (Waiting for Rx packet) + * 0b0100..Suspended (Rx Descriptor Unavailable) + * 0b0101..Running (Closing the Rx Descriptor) + * 0b0110..Timestamp write state + * 0b0111..Running (Transferring the received packet data from the Rx buffer to the system memory) + */ +#define ENET_QOS_DMA_DEBUG_STATUS0_RPS0(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_DEBUG_STATUS0_RPS0_SHIFT)) & ENET_QOS_DMA_DEBUG_STATUS0_RPS0_MASK) + +#define ENET_QOS_DMA_DEBUG_STATUS0_TPS0_MASK (0xF000U) +#define ENET_QOS_DMA_DEBUG_STATUS0_TPS0_SHIFT (12U) +/*! TPS0 - DMA Channel 0 Transmit Process State This field indicates the Tx DMA FSM state for Channel 0. + * 0b0000..Stopped (Reset or Stop Transmit Command issued) + * 0b0001..Running (Fetching Tx Transfer Descriptor) + * 0b0010..Running (Waiting for status) + * 0b0011..Running (Reading Data from system memory buffer and queuing it to the Tx buffer (Tx FIFO)) + * 0b0100..Timestamp write state + * 0b0101..Reserved for future use + * 0b0110..Suspended (Tx Descriptor Unavailable or Tx Buffer Underflow) + * 0b0111..Running (Closing Tx Descriptor) + */ +#define ENET_QOS_DMA_DEBUG_STATUS0_TPS0(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_DEBUG_STATUS0_TPS0_SHIFT)) & ENET_QOS_DMA_DEBUG_STATUS0_TPS0_MASK) + +#define ENET_QOS_DMA_DEBUG_STATUS0_RPS1_MASK (0xF0000U) +#define ENET_QOS_DMA_DEBUG_STATUS0_RPS1_SHIFT (16U) +/*! RPS1 - DMA Channel 1 Receive Process State This field indicates the Rx DMA FSM state for Channel 1. + * 0b0000..Stopped (Reset or Stop Receive Command issued) + * 0b0001..Running (Fetching Rx Transfer Descriptor) + * 0b0010..Reserved for future use + * 0b0011..Running (Waiting for Rx packet) + * 0b0100..Suspended (Rx Descriptor Unavailable) + * 0b0101..Running (Closing the Rx Descriptor) + * 0b0110..Timestamp write state + * 0b0111..Running (Transferring the received packet data from the Rx buffer to the system memory) + */ +#define ENET_QOS_DMA_DEBUG_STATUS0_RPS1(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_DEBUG_STATUS0_RPS1_SHIFT)) & ENET_QOS_DMA_DEBUG_STATUS0_RPS1_MASK) + +#define ENET_QOS_DMA_DEBUG_STATUS0_TPS1_MASK (0xF00000U) +#define ENET_QOS_DMA_DEBUG_STATUS0_TPS1_SHIFT (20U) +/*! TPS1 - DMA Channel 1 Transmit Process State This field indicates the Tx DMA FSM state for Channel 1. + * 0b0000..Stopped (Reset or Stop Transmit Command issued) + * 0b0001..Running (Fetching Tx Transfer Descriptor) + * 0b0010..Running (Waiting for status) + * 0b0011..Running (Reading Data from system memory buffer and queuing it to the Tx buffer (Tx FIFO)) + * 0b0100..Timestamp write state + * 0b0101..Reserved for future use + * 0b0110..Suspended (Tx Descriptor Unavailable or Tx Buffer Underflow) + * 0b0111..Running (Closing Tx Descriptor) + */ +#define ENET_QOS_DMA_DEBUG_STATUS0_TPS1(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_DEBUG_STATUS0_TPS1_SHIFT)) & ENET_QOS_DMA_DEBUG_STATUS0_TPS1_MASK) + +#define ENET_QOS_DMA_DEBUG_STATUS0_RPS2_MASK (0xF000000U) +#define ENET_QOS_DMA_DEBUG_STATUS0_RPS2_SHIFT (24U) +/*! RPS2 - DMA Channel 2 Receive Process State This field indicates the Rx DMA FSM state for Channel 2. + * 0b0000..Stopped (Reset or Stop Receive Command issued) + * 0b0001..Running (Fetching Rx Transfer Descriptor) + * 0b0010..Reserved for future use + * 0b0011..Running (Waiting for Rx packet) + * 0b0100..Suspended (Rx Descriptor Unavailable) + * 0b0101..Running (Closing the Rx Descriptor) + * 0b0110..Timestamp write state + * 0b0111..Running (Transferring the received packet data from the Rx buffer to the system memory) + */ +#define ENET_QOS_DMA_DEBUG_STATUS0_RPS2(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_DEBUG_STATUS0_RPS2_SHIFT)) & ENET_QOS_DMA_DEBUG_STATUS0_RPS2_MASK) + +#define ENET_QOS_DMA_DEBUG_STATUS0_TPS2_MASK (0xF0000000U) +#define ENET_QOS_DMA_DEBUG_STATUS0_TPS2_SHIFT (28U) +/*! TPS2 - DMA Channel 2 Transmit Process State This field indicates the Tx DMA FSM state for Channel 2. + * 0b0000..Stopped (Reset or Stop Transmit Command issued) + * 0b0001..Running (Fetching Tx Transfer Descriptor) + * 0b0010..Running (Waiting for status) + * 0b0011..Running (Reading Data from system memory buffer and queuing it to the Tx buffer (Tx FIFO)) + * 0b0100..Timestamp write state + * 0b0101..Reserved for future use + * 0b0110..Suspended (Tx Descriptor Unavailable or Tx Buffer Underflow) + * 0b0111..Running (Closing Tx Descriptor) + */ +#define ENET_QOS_DMA_DEBUG_STATUS0_TPS2(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_DEBUG_STATUS0_TPS2_SHIFT)) & ENET_QOS_DMA_DEBUG_STATUS0_TPS2_MASK) +/*! @} */ + +/*! @name DMA_DEBUG_STATUS1 - DMA Debug Status 1 */ +/*! @{ */ + +#define ENET_QOS_DMA_DEBUG_STATUS1_RPS3_MASK (0xFU) +#define ENET_QOS_DMA_DEBUG_STATUS1_RPS3_SHIFT (0U) +/*! RPS3 - DMA Channel 3 Receive Process State This field indicates the Rx DMA FSM state for Channel 3. + * 0b0000..Stopped (Reset or Stop Receive Command issued) + * 0b0001..Running (Fetching Rx Transfer Descriptor) + * 0b0010..Reserved for future use + * 0b0011..Running (Waiting for Rx packet) + * 0b0100..Suspended (Rx Descriptor Unavailable) + * 0b0101..Running (Closing the Rx Descriptor) + * 0b0110..Timestamp write state + * 0b0111..Running (Transferring the received packet data from the Rx buffer to the system memory) + */ +#define ENET_QOS_DMA_DEBUG_STATUS1_RPS3(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_DEBUG_STATUS1_RPS3_SHIFT)) & ENET_QOS_DMA_DEBUG_STATUS1_RPS3_MASK) + +#define ENET_QOS_DMA_DEBUG_STATUS1_TPS3_MASK (0xF0U) +#define ENET_QOS_DMA_DEBUG_STATUS1_TPS3_SHIFT (4U) +/*! TPS3 - DMA Channel 3 Transmit Process State This field indicates the Tx DMA FSM state for Channel 3. + * 0b0000..Stopped (Reset or Stop Transmit Command issued) + * 0b0001..Running (Fetching Tx Transfer Descriptor) + * 0b0010..Running (Waiting for status) + * 0b0011..Running (Reading Data from system memory buffer and queuing it to the Tx buffer (Tx FIFO)) + * 0b0100..Timestamp write state + * 0b0101..Reserved for future use + * 0b0110..Suspended (Tx Descriptor Unavailable or Tx Buffer Underflow) + * 0b0111..Running (Closing Tx Descriptor) + */ +#define ENET_QOS_DMA_DEBUG_STATUS1_TPS3(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_DEBUG_STATUS1_TPS3_SHIFT)) & ENET_QOS_DMA_DEBUG_STATUS1_TPS3_MASK) + +#define ENET_QOS_DMA_DEBUG_STATUS1_RPS4_MASK (0xF00U) +#define ENET_QOS_DMA_DEBUG_STATUS1_RPS4_SHIFT (8U) +/*! RPS4 - DMA Channel 4 Receive Process State This field indicates the Rx DMA FSM state for Channel 4. + * 0b0000..Stopped (Reset or Stop Receive Command issued) + * 0b0001..Running (Fetching Rx Transfer Descriptor) + * 0b0010..Reserved for future use + * 0b0011..Running (Waiting for Rx packet) + * 0b0100..Suspended (Rx Descriptor Unavailable) + * 0b0101..Running (Closing the Rx Descriptor) + * 0b0110..Timestamp write state + * 0b0111..Running (Transferring the received packet data from the Rx buffer to the system memory) + */ +#define ENET_QOS_DMA_DEBUG_STATUS1_RPS4(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_DEBUG_STATUS1_RPS4_SHIFT)) & ENET_QOS_DMA_DEBUG_STATUS1_RPS4_MASK) + +#define ENET_QOS_DMA_DEBUG_STATUS1_TPS4_MASK (0xF000U) +#define ENET_QOS_DMA_DEBUG_STATUS1_TPS4_SHIFT (12U) +/*! TPS4 - DMA Channel 4 Transmit Process State This field indicates the Tx DMA FSM state for Channel 4. + * 0b0000..Stopped (Reset or Stop Transmit Command issued) + * 0b0001..Running (Fetching Tx Transfer Descriptor) + * 0b0010..Running (Waiting for status) + * 0b0011..Running (Reading Data from system memory buffer and queuing it to the Tx buffer (Tx FIFO)) + * 0b0100..Timestamp write state + * 0b0101..Reserved for future use + * 0b0110..Suspended (Tx Descriptor Unavailable or Tx Buffer Underflow) + * 0b0111..Running (Closing Tx Descriptor) + */ +#define ENET_QOS_DMA_DEBUG_STATUS1_TPS4(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_DEBUG_STATUS1_TPS4_SHIFT)) & ENET_QOS_DMA_DEBUG_STATUS1_TPS4_MASK) +/*! @} */ + +/*! @name DMA_AXI_LPI_ENTRY_INTERVAL - AXI LPI Entry Interval Control */ +/*! @{ */ + +#define ENET_QOS_DMA_AXI_LPI_ENTRY_INTERVAL_LPIEI_MASK (0xFU) +#define ENET_QOS_DMA_AXI_LPI_ENTRY_INTERVAL_LPIEI_SHIFT (0U) +/*! LPIEI - LPI Entry Interval Contains the number of system clock cycles, multiplied by 64, to wait + * for an activity in the DWC_ether_qos to enter into the AXI low power state 0 indicates 64 + * clock cycles + */ +#define ENET_QOS_DMA_AXI_LPI_ENTRY_INTERVAL_LPIEI(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_AXI_LPI_ENTRY_INTERVAL_LPIEI_SHIFT)) & ENET_QOS_DMA_AXI_LPI_ENTRY_INTERVAL_LPIEI_MASK) +/*! @} */ + +/*! @name DMA_TBS_CTRL0 - DMA_TBS_CTRL0 */ +/*! @{ */ + +#define ENET_QOS_DMA_TBS_CTRL0_FTOV_MASK (0x1U) +#define ENET_QOS_DMA_TBS_CTRL0_FTOV_SHIFT (0U) +/*! FTOV - Fetch Time Offset Valid When set indicates the FTOS field is valid. When not set, + * indicates the Fetch Offset is not valid and the DMA engine can fetch the frames from host memory + * without any time restrictions. + * 0b0..Fetch Time Offset is invalid + * 0b1..Fetch Time Offset is valid + */ +#define ENET_QOS_DMA_TBS_CTRL0_FTOV(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_TBS_CTRL0_FTOV_SHIFT)) & ENET_QOS_DMA_TBS_CTRL0_FTOV_MASK) + +#define ENET_QOS_DMA_TBS_CTRL0_FGOS_MASK (0x70U) +#define ENET_QOS_DMA_TBS_CTRL0_FGOS_SHIFT (4U) +/*! FGOS - Fetch GSN Offset */ +#define ENET_QOS_DMA_TBS_CTRL0_FGOS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_TBS_CTRL0_FGOS_SHIFT)) & ENET_QOS_DMA_TBS_CTRL0_FGOS_MASK) + +#define ENET_QOS_DMA_TBS_CTRL0_FTOS_MASK (0xFFFFFF00U) +#define ENET_QOS_DMA_TBS_CTRL0_FTOS_SHIFT (8U) +/*! FTOS - Fetch Time Offset */ +#define ENET_QOS_DMA_TBS_CTRL0_FTOS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_TBS_CTRL0_FTOS_SHIFT)) & ENET_QOS_DMA_TBS_CTRL0_FTOS_MASK) +/*! @} */ + +/*! @name DMA_TBS_CTRL1 - DMA_TBS_CTRL1 */ +/*! @{ */ + +#define ENET_QOS_DMA_TBS_CTRL1_FTOV_MASK (0x1U) +#define ENET_QOS_DMA_TBS_CTRL1_FTOV_SHIFT (0U) +/*! FTOV - Fetch Time Offset Valid When set indicates the FTOS field is valid. When not set, + * indicates the Fetch Offset is not valid and the DMA engine can fetch the frames from host memory + * without any time restrictions. + * 0b0..Fetch Time Offset is invalid + * 0b1..Fetch Time Offset is valid + */ +#define ENET_QOS_DMA_TBS_CTRL1_FTOV(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_TBS_CTRL1_FTOV_SHIFT)) & ENET_QOS_DMA_TBS_CTRL1_FTOV_MASK) + +#define ENET_QOS_DMA_TBS_CTRL1_FGOS_MASK (0x70U) +#define ENET_QOS_DMA_TBS_CTRL1_FGOS_SHIFT (4U) +/*! FGOS - Fetch GSN Offset */ +#define ENET_QOS_DMA_TBS_CTRL1_FGOS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_TBS_CTRL1_FGOS_SHIFT)) & ENET_QOS_DMA_TBS_CTRL1_FGOS_MASK) + +#define ENET_QOS_DMA_TBS_CTRL1_FTOS_MASK (0xFFFFFF00U) +#define ENET_QOS_DMA_TBS_CTRL1_FTOS_SHIFT (8U) +/*! FTOS - Fetch Time Offset */ +#define ENET_QOS_DMA_TBS_CTRL1_FTOS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_TBS_CTRL1_FTOS_SHIFT)) & ENET_QOS_DMA_TBS_CTRL1_FTOS_MASK) +/*! @} */ + +/*! @name DMA_TBS_CTRL2 - DMA_TBS_CTRL2 */ +/*! @{ */ + +#define ENET_QOS_DMA_TBS_CTRL2_FTOV_MASK (0x1U) +#define ENET_QOS_DMA_TBS_CTRL2_FTOV_SHIFT (0U) +/*! FTOV - Fetch Time Offset Valid When set indicates the FTOS field is valid. When not set, + * indicates the Fetch Offset is not valid and the DMA engine can fetch the frames from host memory + * without any time restrictions. + * 0b0..Fetch Time Offset is invalid + * 0b1..Fetch Time Offset is valid + */ +#define ENET_QOS_DMA_TBS_CTRL2_FTOV(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_TBS_CTRL2_FTOV_SHIFT)) & ENET_QOS_DMA_TBS_CTRL2_FTOV_MASK) + +#define ENET_QOS_DMA_TBS_CTRL2_FGOS_MASK (0x70U) +#define ENET_QOS_DMA_TBS_CTRL2_FGOS_SHIFT (4U) +/*! FGOS - Fetch GSN Offset */ +#define ENET_QOS_DMA_TBS_CTRL2_FGOS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_TBS_CTRL2_FGOS_SHIFT)) & ENET_QOS_DMA_TBS_CTRL2_FGOS_MASK) + +#define ENET_QOS_DMA_TBS_CTRL2_FTOS_MASK (0xFFFFFF00U) +#define ENET_QOS_DMA_TBS_CTRL2_FTOS_SHIFT (8U) +/*! FTOS - Fetch Time Offset */ +#define ENET_QOS_DMA_TBS_CTRL2_FTOS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_TBS_CTRL2_FTOS_SHIFT)) & ENET_QOS_DMA_TBS_CTRL2_FTOS_MASK) +/*! @} */ + +/*! @name DMA_TBS_CTRL3 - DMA_TBS_CTRL3 */ +/*! @{ */ + +#define ENET_QOS_DMA_TBS_CTRL3_FTOV_MASK (0x1U) +#define ENET_QOS_DMA_TBS_CTRL3_FTOV_SHIFT (0U) +/*! FTOV - Fetch Time Offset Valid When set indicates the FTOS field is valid. When not set, + * indicates the Fetch Offset is not valid and the DMA engine can fetch the frames from host memory + * without any time restrictions. + * 0b0..Fetch Time Offset is invalid + * 0b1..Fetch Time Offset is valid + */ +#define ENET_QOS_DMA_TBS_CTRL3_FTOV(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_TBS_CTRL3_FTOV_SHIFT)) & ENET_QOS_DMA_TBS_CTRL3_FTOV_MASK) + +#define ENET_QOS_DMA_TBS_CTRL3_FGOS_MASK (0x70U) +#define ENET_QOS_DMA_TBS_CTRL3_FGOS_SHIFT (4U) +/*! FGOS - Fetch GSN Offset */ +#define ENET_QOS_DMA_TBS_CTRL3_FGOS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_TBS_CTRL3_FGOS_SHIFT)) & ENET_QOS_DMA_TBS_CTRL3_FGOS_MASK) + +#define ENET_QOS_DMA_TBS_CTRL3_FTOS_MASK (0xFFFFFF00U) +#define ENET_QOS_DMA_TBS_CTRL3_FTOS_SHIFT (8U) +/*! FTOS - Fetch Time Offset */ +#define ENET_QOS_DMA_TBS_CTRL3_FTOS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_TBS_CTRL3_FTOS_SHIFT)) & ENET_QOS_DMA_TBS_CTRL3_FTOS_MASK) +/*! @} */ + +/*! @name DMA_CHX_CTRL - DMA Channel 0 Control..Channel 4 Control */ +/*! @{ */ + +#define ENET_QOS_DMA_CHX_CTRL_PBLx8_MASK (0x10000U) +#define ENET_QOS_DMA_CHX_CTRL_PBLx8_SHIFT (16U) +/*! PBLx8 - 8xPBL mode When this bit is set, the PBL value programmed in Bits[21:16] in + * DMA_CH4_TX_CONTROL and Bits[21:16] in DMA_CH4_RX_CONTROL is multiplied by eight times. + * 0b0..8xPBL mode is disabled + * 0b1..8xPBL mode is enabled + */ +#define ENET_QOS_DMA_CHX_CTRL_PBLx8(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_CTRL_PBLx8_SHIFT)) & ENET_QOS_DMA_CHX_CTRL_PBLx8_MASK) + +#define ENET_QOS_DMA_CHX_CTRL_DSL_MASK (0x1C0000U) +#define ENET_QOS_DMA_CHX_CTRL_DSL_SHIFT (18U) +/*! DSL - Descriptor Skip Length This bit specifies the Word, Dword, or Lword number (depending on + * the 32-bit, 64-bit, or 128-bit bus) to skip between two unchained descriptors. + */ +#define ENET_QOS_DMA_CHX_CTRL_DSL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_CTRL_DSL_SHIFT)) & ENET_QOS_DMA_CHX_CTRL_DSL_MASK) +/*! @} */ + +/* The count of ENET_QOS_DMA_CHX_CTRL */ +#define ENET_QOS_DMA_CHX_CTRL_COUNT (5U) + +/*! @name DMA_CHX_TX_CTRL - DMA Channel 0 Transmit Control..DMA Channel 4 Transmit Control */ +/*! @{ */ + +#define ENET_QOS_DMA_CHX_TX_CTRL_ST_MASK (0x1U) +#define ENET_QOS_DMA_CHX_TX_CTRL_ST_SHIFT (0U) +/*! ST - Start or Stop Transmission Command When this bit is set, transmission is placed in the Running state. + * 0b0..Stop Transmission Command + * 0b1..Start Transmission Command + */ +#define ENET_QOS_DMA_CHX_TX_CTRL_ST(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_TX_CTRL_ST_SHIFT)) & ENET_QOS_DMA_CHX_TX_CTRL_ST_MASK) + +#define ENET_QOS_DMA_CHX_TX_CTRL_OSF_MASK (0x10U) +#define ENET_QOS_DMA_CHX_TX_CTRL_OSF_SHIFT (4U) +/*! OSF - Operate on Second Packet When this bit is set, it instructs the DMA to process the second + * packet of the Transmit data even before the status for the first packet is obtained. + * 0b0..Operate on Second Packet disabled + * 0b1..Operate on Second Packet enabled + */ +#define ENET_QOS_DMA_CHX_TX_CTRL_OSF(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_TX_CTRL_OSF_SHIFT)) & ENET_QOS_DMA_CHX_TX_CTRL_OSF_MASK) + +#define ENET_QOS_DMA_CHX_TX_CTRL_IPBL_MASK (0x8000U) +#define ENET_QOS_DMA_CHX_TX_CTRL_IPBL_SHIFT (15U) +/*! IPBL - Ignore PBL Requirement When this bit is set, the DMA does not check for PBL number of + * locations in the MTL before initiating a transfer. + * 0b0..Ignore PBL Requirement is disabled + * 0b1..Ignore PBL Requirement is enabled + */ +#define ENET_QOS_DMA_CHX_TX_CTRL_IPBL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_TX_CTRL_IPBL_SHIFT)) & ENET_QOS_DMA_CHX_TX_CTRL_IPBL_MASK) + +#define ENET_QOS_DMA_CHX_TX_CTRL_TxPBL_MASK (0x3F0000U) +#define ENET_QOS_DMA_CHX_TX_CTRL_TxPBL_SHIFT (16U) +/*! TxPBL - Transmit Programmable Burst Length These bits indicate the maximum number of beats to be + * transferred in one DMA block data transfer. + */ +#define ENET_QOS_DMA_CHX_TX_CTRL_TxPBL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_TX_CTRL_TxPBL_SHIFT)) & ENET_QOS_DMA_CHX_TX_CTRL_TxPBL_MASK) + +#define ENET_QOS_DMA_CHX_TX_CTRL_EDSE_MASK (0x10000000U) +#define ENET_QOS_DMA_CHX_TX_CTRL_EDSE_SHIFT (28U) +/*! EDSE - Enhanced Descriptor Enable When this bit is set, the corresponding channel uses Enhanced + * Descriptors that are 32 Bytes for both Normal and Context Descriptors. + * 0b0..Enhanced Descriptor is disabled + * 0b1..Enhanced Descriptor is enabled + */ +#define ENET_QOS_DMA_CHX_TX_CTRL_EDSE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_TX_CTRL_EDSE_SHIFT)) & ENET_QOS_DMA_CHX_TX_CTRL_EDSE_MASK) +/*! @} */ + +/* The count of ENET_QOS_DMA_CHX_TX_CTRL */ +#define ENET_QOS_DMA_CHX_TX_CTRL_COUNT (5U) + +/*! @name DMA_CHX_RX_CTRL - DMA Channel 0 Receive Control..DMA Channel 4 Receive Control */ +/*! @{ */ + +#define ENET_QOS_DMA_CHX_RX_CTRL_SR_MASK (0x1U) +#define ENET_QOS_DMA_CHX_RX_CTRL_SR_SHIFT (0U) +/*! SR - Start or Stop Receive When this bit is set, the DMA tries to acquire the descriptor from + * the Receive list and processes the incoming packets. + * 0b0..Stop Receive + * 0b1..Start Receive + */ +#define ENET_QOS_DMA_CHX_RX_CTRL_SR(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_RX_CTRL_SR_SHIFT)) & ENET_QOS_DMA_CHX_RX_CTRL_SR_MASK) + +#define ENET_QOS_DMA_CHX_RX_CTRL_RBSZ_x_0_MASK (0xEU) +#define ENET_QOS_DMA_CHX_RX_CTRL_RBSZ_x_0_SHIFT (1U) +/*! RBSZ_x_0 - Receive Buffer size Low RBSZ[13:0] is split into two fields RBSZ_13_y and RBSZ_x_0. */ +#define ENET_QOS_DMA_CHX_RX_CTRL_RBSZ_x_0(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_RX_CTRL_RBSZ_x_0_SHIFT)) & ENET_QOS_DMA_CHX_RX_CTRL_RBSZ_x_0_MASK) + +#define ENET_QOS_DMA_CHX_RX_CTRL_RBSZ_13_y_MASK (0x7FF0U) +#define ENET_QOS_DMA_CHX_RX_CTRL_RBSZ_13_y_SHIFT (4U) +/*! RBSZ_13_y - Receive Buffer size High RBSZ[13:0] is split into two fields higher RBSZ_13_y and lower RBSZ_x_0. */ +#define ENET_QOS_DMA_CHX_RX_CTRL_RBSZ_13_y(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_RX_CTRL_RBSZ_13_y_SHIFT)) & ENET_QOS_DMA_CHX_RX_CTRL_RBSZ_13_y_MASK) + +#define ENET_QOS_DMA_CHX_RX_CTRL_RxPBL_MASK (0x3F0000U) +#define ENET_QOS_DMA_CHX_RX_CTRL_RxPBL_SHIFT (16U) +/*! RxPBL - Receive Programmable Burst Length These bits indicate the maximum number of beats to be + * transferred in one DMA block data transfer. + */ +#define ENET_QOS_DMA_CHX_RX_CTRL_RxPBL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_RX_CTRL_RxPBL_SHIFT)) & ENET_QOS_DMA_CHX_RX_CTRL_RxPBL_MASK) + +#define ENET_QOS_DMA_CHX_RX_CTRL_RPF_MASK (0x80000000U) +#define ENET_QOS_DMA_CHX_RX_CTRL_RPF_SHIFT (31U) +/*! RPF - Rx Packet Flush. + * 0b0..Rx Packet Flush is disabled + * 0b1..Rx Packet Flush is enabled + */ +#define ENET_QOS_DMA_CHX_RX_CTRL_RPF(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_RX_CTRL_RPF_SHIFT)) & ENET_QOS_DMA_CHX_RX_CTRL_RPF_MASK) +/*! @} */ + +/* The count of ENET_QOS_DMA_CHX_RX_CTRL */ +#define ENET_QOS_DMA_CHX_RX_CTRL_COUNT (5U) + +/*! @name DMA_CHX_TXDESC_LIST_ADDR - Channel 0 Tx Descriptor List Address register..Channel 4 Tx Descriptor List Address */ +/*! @{ */ + +#define ENET_QOS_DMA_CHX_TXDESC_LIST_ADDR_TDESLA_MASK (0xFFFFFFF8U) +#define ENET_QOS_DMA_CHX_TXDESC_LIST_ADDR_TDESLA_SHIFT (3U) +/*! TDESLA - Start of Transmit List This field contains the base address of the first descriptor in the Transmit descriptor list. */ +#define ENET_QOS_DMA_CHX_TXDESC_LIST_ADDR_TDESLA(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_TXDESC_LIST_ADDR_TDESLA_SHIFT)) & ENET_QOS_DMA_CHX_TXDESC_LIST_ADDR_TDESLA_MASK) +/*! @} */ + +/* The count of ENET_QOS_DMA_CHX_TXDESC_LIST_ADDR */ +#define ENET_QOS_DMA_CHX_TXDESC_LIST_ADDR_COUNT (5U) + +/*! @name DMA_CHX_RXDESC_LIST_ADDR - Channel 0 Rx Descriptor List Address register..Channel 4 Rx Descriptor List Address */ +/*! @{ */ + +#define ENET_QOS_DMA_CHX_RXDESC_LIST_ADDR_RDESLA_MASK (0xFFFFFFF8U) +#define ENET_QOS_DMA_CHX_RXDESC_LIST_ADDR_RDESLA_SHIFT (3U) +/*! RDESLA - Start of Receive List This field contains the base address of the first descriptor in the Rx Descriptor list. */ +#define ENET_QOS_DMA_CHX_RXDESC_LIST_ADDR_RDESLA(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_RXDESC_LIST_ADDR_RDESLA_SHIFT)) & ENET_QOS_DMA_CHX_RXDESC_LIST_ADDR_RDESLA_MASK) +/*! @} */ + +/* The count of ENET_QOS_DMA_CHX_RXDESC_LIST_ADDR */ +#define ENET_QOS_DMA_CHX_RXDESC_LIST_ADDR_COUNT (5U) + +/*! @name DMA_CHX_TXDESC_TAIL_PTR - Channel 0 Tx Descriptor Tail Pointer..Channel 4 Tx Descriptor Tail Pointer */ +/*! @{ */ + +#define ENET_QOS_DMA_CHX_TXDESC_TAIL_PTR_TDTP_MASK (0xFFFFFFF8U) +#define ENET_QOS_DMA_CHX_TXDESC_TAIL_PTR_TDTP_SHIFT (3U) +/*! TDTP - Transmit Descriptor Tail Pointer This field contains the tail pointer for the Tx descriptor ring. */ +#define ENET_QOS_DMA_CHX_TXDESC_TAIL_PTR_TDTP(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_TXDESC_TAIL_PTR_TDTP_SHIFT)) & ENET_QOS_DMA_CHX_TXDESC_TAIL_PTR_TDTP_MASK) +/*! @} */ + +/* The count of ENET_QOS_DMA_CHX_TXDESC_TAIL_PTR */ +#define ENET_QOS_DMA_CHX_TXDESC_TAIL_PTR_COUNT (5U) + +/*! @name DMA_CHX_RXDESC_TAIL_PTR - Channel 0 Rx Descriptor Tail Pointer..Channel 4 Rx Descriptor Tail Pointer */ +/*! @{ */ + +#define ENET_QOS_DMA_CHX_RXDESC_TAIL_PTR_RDTP_MASK (0xFFFFFFF8U) +#define ENET_QOS_DMA_CHX_RXDESC_TAIL_PTR_RDTP_SHIFT (3U) +/*! RDTP - Receive Descriptor Tail Pointer This field contains the tail pointer for the Rx descriptor ring. */ +#define ENET_QOS_DMA_CHX_RXDESC_TAIL_PTR_RDTP(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_RXDESC_TAIL_PTR_RDTP_SHIFT)) & ENET_QOS_DMA_CHX_RXDESC_TAIL_PTR_RDTP_MASK) +/*! @} */ + +/* The count of ENET_QOS_DMA_CHX_RXDESC_TAIL_PTR */ +#define ENET_QOS_DMA_CHX_RXDESC_TAIL_PTR_COUNT (5U) + +/*! @name DMA_CHX_TXDESC_RING_LENGTH - Channel 0 Tx Descriptor Ring Length..Channel 4 Tx Descriptor Ring Length */ +/*! @{ */ + +#define ENET_QOS_DMA_CHX_TXDESC_RING_LENGTH_TDRL_MASK (0x3FFU) +#define ENET_QOS_DMA_CHX_TXDESC_RING_LENGTH_TDRL_SHIFT (0U) +/*! TDRL - Transmit Descriptor Ring Length This field sets the maximum number of Tx descriptors in the circular descriptor ring. */ +#define ENET_QOS_DMA_CHX_TXDESC_RING_LENGTH_TDRL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_TXDESC_RING_LENGTH_TDRL_SHIFT)) & ENET_QOS_DMA_CHX_TXDESC_RING_LENGTH_TDRL_MASK) +/*! @} */ + +/* The count of ENET_QOS_DMA_CHX_TXDESC_RING_LENGTH */ +#define ENET_QOS_DMA_CHX_TXDESC_RING_LENGTH_COUNT (5U) + +/*! @name DMA_CHX_RX_CONTROL2 - Channel 0 Receive Control 2 register..DMA Channel 4 Receive Control 2 register */ +/*! @{ */ + +#define ENET_QOS_DMA_CHX_RX_CONTROL2_RDRL_MASK (0x3FFU) +#define ENET_QOS_DMA_CHX_RX_CONTROL2_RDRL_SHIFT (0U) +/*! RDRL - Receive Descriptor Ring Length This register sets the maximum number of Rx descriptors in the circular descriptor ring. */ +#define ENET_QOS_DMA_CHX_RX_CONTROL2_RDRL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_RX_CONTROL2_RDRL_SHIFT)) & ENET_QOS_DMA_CHX_RX_CONTROL2_RDRL_MASK) + +#define ENET_QOS_DMA_CHX_RX_CONTROL2_ARBS_MASK (0xFE0000U) +#define ENET_QOS_DMA_CHX_RX_CONTROL2_ARBS_SHIFT (17U) +/*! ARBS - Alternate Receive Buffer Size */ +#define ENET_QOS_DMA_CHX_RX_CONTROL2_ARBS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_RX_CONTROL2_ARBS_SHIFT)) & ENET_QOS_DMA_CHX_RX_CONTROL2_ARBS_MASK) +/*! @} */ + +/* The count of ENET_QOS_DMA_CHX_RX_CONTROL2 */ +#define ENET_QOS_DMA_CHX_RX_CONTROL2_COUNT (5U) + +/*! @name DMA_CHX_INT_EN - Channel 0 Interrupt Enable..Channel 4 Interrupt Enable */ +/*! @{ */ + +#define ENET_QOS_DMA_CHX_INT_EN_TIE_MASK (0x1U) +#define ENET_QOS_DMA_CHX_INT_EN_TIE_SHIFT (0U) +/*! TIE - Transmit Interrupt Enable When this bit is set along with the NIE bit, the Transmit Interrupt is enabled. + * 0b0..Transmit Interrupt is disabled + * 0b1..Transmit Interrupt is enabled + */ +#define ENET_QOS_DMA_CHX_INT_EN_TIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_INT_EN_TIE_SHIFT)) & ENET_QOS_DMA_CHX_INT_EN_TIE_MASK) + +#define ENET_QOS_DMA_CHX_INT_EN_TXSE_MASK (0x2U) +#define ENET_QOS_DMA_CHX_INT_EN_TXSE_SHIFT (1U) +/*! TXSE - Transmit Stopped Enable When this bit is set along with the AIE bit, the Transmission Stopped interrupt is enabled. + * 0b0..Transmit Stopped is disabled + * 0b1..Transmit Stopped is enabled + */ +#define ENET_QOS_DMA_CHX_INT_EN_TXSE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_INT_EN_TXSE_SHIFT)) & ENET_QOS_DMA_CHX_INT_EN_TXSE_MASK) + +#define ENET_QOS_DMA_CHX_INT_EN_TBUE_MASK (0x4U) +#define ENET_QOS_DMA_CHX_INT_EN_TBUE_SHIFT (2U) +/*! TBUE - Transmit Buffer Unavailable Enable When this bit is set along with the NIE bit, the + * Transmit Buffer Unavailable interrupt is enabled. + * 0b0..Transmit Buffer Unavailable is disabled + * 0b1..Transmit Buffer Unavailable is enabled + */ +#define ENET_QOS_DMA_CHX_INT_EN_TBUE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_INT_EN_TBUE_SHIFT)) & ENET_QOS_DMA_CHX_INT_EN_TBUE_MASK) + +#define ENET_QOS_DMA_CHX_INT_EN_RIE_MASK (0x40U) +#define ENET_QOS_DMA_CHX_INT_EN_RIE_SHIFT (6U) +/*! RIE - Receive Interrupt Enable When this bit is set along with the NIE bit, the Receive Interrupt is enabled. + * 0b0..Receive Interrupt is disabled + * 0b1..Receive Interrupt is enabled + */ +#define ENET_QOS_DMA_CHX_INT_EN_RIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_INT_EN_RIE_SHIFT)) & ENET_QOS_DMA_CHX_INT_EN_RIE_MASK) + +#define ENET_QOS_DMA_CHX_INT_EN_RBUE_MASK (0x80U) +#define ENET_QOS_DMA_CHX_INT_EN_RBUE_SHIFT (7U) +/*! RBUE - Receive Buffer Unavailable Enable When this bit is set along with the AIE bit, the + * Receive Buffer Unavailable interrupt is enabled. + * 0b0..Receive Buffer Unavailable is disabled + * 0b1..Receive Buffer Unavailable is enabled + */ +#define ENET_QOS_DMA_CHX_INT_EN_RBUE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_INT_EN_RBUE_SHIFT)) & ENET_QOS_DMA_CHX_INT_EN_RBUE_MASK) + +#define ENET_QOS_DMA_CHX_INT_EN_RSE_MASK (0x100U) +#define ENET_QOS_DMA_CHX_INT_EN_RSE_SHIFT (8U) +/*! RSE - Receive Stopped Enable When this bit is set along with the AIE bit, the Receive Stopped Interrupt is enabled. + * 0b0..Receive Stopped is disabled + * 0b1..Receive Stopped is enabled + */ +#define ENET_QOS_DMA_CHX_INT_EN_RSE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_INT_EN_RSE_SHIFT)) & ENET_QOS_DMA_CHX_INT_EN_RSE_MASK) + +#define ENET_QOS_DMA_CHX_INT_EN_RWTE_MASK (0x200U) +#define ENET_QOS_DMA_CHX_INT_EN_RWTE_SHIFT (9U) +/*! RWTE - Receive Watchdog Timeout Enable When this bit is set along with the AIE bit, the Receive + * Watchdog Timeout interrupt is enabled. + * 0b0..Receive Watchdog Timeout is disabled + * 0b1..Receive Watchdog Timeout is enabled + */ +#define ENET_QOS_DMA_CHX_INT_EN_RWTE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_INT_EN_RWTE_SHIFT)) & ENET_QOS_DMA_CHX_INT_EN_RWTE_MASK) + +#define ENET_QOS_DMA_CHX_INT_EN_ETIE_MASK (0x400U) +#define ENET_QOS_DMA_CHX_INT_EN_ETIE_SHIFT (10U) +/*! ETIE - Early Transmit Interrupt Enable When this bit is set along with the AIE bit, the Early Transmit interrupt is enabled. + * 0b0..Early Transmit Interrupt is disabled + * 0b1..Early Transmit Interrupt is enabled + */ +#define ENET_QOS_DMA_CHX_INT_EN_ETIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_INT_EN_ETIE_SHIFT)) & ENET_QOS_DMA_CHX_INT_EN_ETIE_MASK) + +#define ENET_QOS_DMA_CHX_INT_EN_ERIE_MASK (0x800U) +#define ENET_QOS_DMA_CHX_INT_EN_ERIE_SHIFT (11U) +/*! ERIE - Early Receive Interrupt Enable When this bit is set along with the NIE bit, the Early Receive interrupt is enabled. + * 0b0..Early Receive Interrupt is disabled + * 0b1..Early Receive Interrupt is enabled + */ +#define ENET_QOS_DMA_CHX_INT_EN_ERIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_INT_EN_ERIE_SHIFT)) & ENET_QOS_DMA_CHX_INT_EN_ERIE_MASK) + +#define ENET_QOS_DMA_CHX_INT_EN_FBEE_MASK (0x1000U) +#define ENET_QOS_DMA_CHX_INT_EN_FBEE_SHIFT (12U) +/*! FBEE - Fatal Bus Error Enable When this bit is set along with the AIE bit, the Fatal Bus error interrupt is enabled. + * 0b0..Fatal Bus Error is disabled + * 0b1..Fatal Bus Error is enabled + */ +#define ENET_QOS_DMA_CHX_INT_EN_FBEE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_INT_EN_FBEE_SHIFT)) & ENET_QOS_DMA_CHX_INT_EN_FBEE_MASK) + +#define ENET_QOS_DMA_CHX_INT_EN_CDEE_MASK (0x2000U) +#define ENET_QOS_DMA_CHX_INT_EN_CDEE_SHIFT (13U) +/*! CDEE - Context Descriptor Error Enable When this bit is set along with the AIE bit, the Descriptor error interrupt is enabled. + * 0b0..Context Descriptor Error is disabled + * 0b1..Context Descriptor Error is enabled + */ +#define ENET_QOS_DMA_CHX_INT_EN_CDEE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_INT_EN_CDEE_SHIFT)) & ENET_QOS_DMA_CHX_INT_EN_CDEE_MASK) + +#define ENET_QOS_DMA_CHX_INT_EN_AIE_MASK (0x4000U) +#define ENET_QOS_DMA_CHX_INT_EN_AIE_SHIFT (14U) +/*! AIE - Abnormal Interrupt Summary Enable When this bit is set, the abnormal interrupt summary is enabled. + * 0b0..Abnormal Interrupt Summary is disabled + * 0b1..Abnormal Interrupt Summary is enabled + */ +#define ENET_QOS_DMA_CHX_INT_EN_AIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_INT_EN_AIE_SHIFT)) & ENET_QOS_DMA_CHX_INT_EN_AIE_MASK) + +#define ENET_QOS_DMA_CHX_INT_EN_NIE_MASK (0x8000U) +#define ENET_QOS_DMA_CHX_INT_EN_NIE_SHIFT (15U) +/*! NIE - Normal Interrupt Summary Enable When this bit is set, the normal interrupt summary is enabled. + * 0b0..Normal Interrupt Summary is disabled + * 0b1..Normal Interrupt Summary is enabled + */ +#define ENET_QOS_DMA_CHX_INT_EN_NIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_INT_EN_NIE_SHIFT)) & ENET_QOS_DMA_CHX_INT_EN_NIE_MASK) +/*! @} */ + +/* The count of ENET_QOS_DMA_CHX_INT_EN */ +#define ENET_QOS_DMA_CHX_INT_EN_COUNT (5U) + +/*! @name DMA_CHX_RX_INT_WDTIMER - Channel 0 Receive Interrupt Watchdog Timer..Channel 4 Receive Interrupt Watchdog Timer */ +/*! @{ */ + +#define ENET_QOS_DMA_CHX_RX_INT_WDTIMER_RWT_MASK (0xFFU) +#define ENET_QOS_DMA_CHX_RX_INT_WDTIMER_RWT_SHIFT (0U) +/*! RWT - Receive Interrupt Watchdog Timer Count This field indicates the number of system clock + * cycles, multiplied by factor indicated in RWTU field, for which the watchdog timer is set. + */ +#define ENET_QOS_DMA_CHX_RX_INT_WDTIMER_RWT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_RX_INT_WDTIMER_RWT_SHIFT)) & ENET_QOS_DMA_CHX_RX_INT_WDTIMER_RWT_MASK) + +#define ENET_QOS_DMA_CHX_RX_INT_WDTIMER_RWTU_MASK (0x30000U) +#define ENET_QOS_DMA_CHX_RX_INT_WDTIMER_RWTU_SHIFT (16U) +/*! RWTU - Receive Interrupt Watchdog Timer Count Units This fields indicates the number of system + * clock cycles corresponding to one unit in RWT field. + */ +#define ENET_QOS_DMA_CHX_RX_INT_WDTIMER_RWTU(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_RX_INT_WDTIMER_RWTU_SHIFT)) & ENET_QOS_DMA_CHX_RX_INT_WDTIMER_RWTU_MASK) +/*! @} */ + +/* The count of ENET_QOS_DMA_CHX_RX_INT_WDTIMER */ +#define ENET_QOS_DMA_CHX_RX_INT_WDTIMER_COUNT (5U) + +/*! @name DMA_CHX_SLOT_FUNC_CTRL_STAT - Channel 0 Slot Function Control and Status..Channel 4 Slot Function Control and Status */ +/*! @{ */ + +#define ENET_QOS_DMA_CHX_SLOT_FUNC_CTRL_STAT_ESC_MASK (0x1U) +#define ENET_QOS_DMA_CHX_SLOT_FUNC_CTRL_STAT_ESC_SHIFT (0U) +/*! ESC - Enable Slot Comparison When set, this bit enables the checking of the slot numbers + * programmed in the Tx descriptor with the current reference given in the RSN field. + * 0b0..Slot Comparison is disabled + * 0b1..Slot Comparison is enabled + */ +#define ENET_QOS_DMA_CHX_SLOT_FUNC_CTRL_STAT_ESC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_SLOT_FUNC_CTRL_STAT_ESC_SHIFT)) & ENET_QOS_DMA_CHX_SLOT_FUNC_CTRL_STAT_ESC_MASK) + +#define ENET_QOS_DMA_CHX_SLOT_FUNC_CTRL_STAT_ASC_MASK (0x2U) +#define ENET_QOS_DMA_CHX_SLOT_FUNC_CTRL_STAT_ASC_SHIFT (1U) +/*! ASC - Advance Slot Check When set, this bit enables the DMA to fetch the data from the buffer + * when the slot number (SLOTNUM) programmed in the Tx descriptor is - equal to the reference slot + * number given in the RSN field or - ahead of the reference slot number by up to two slots This + * bit is applicable only when the ESC bit is set. + * 0b0..Advance Slot Check is disabled + * 0b1..Advance Slot Check is enabled + */ +#define ENET_QOS_DMA_CHX_SLOT_FUNC_CTRL_STAT_ASC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_SLOT_FUNC_CTRL_STAT_ASC_SHIFT)) & ENET_QOS_DMA_CHX_SLOT_FUNC_CTRL_STAT_ASC_MASK) + +#define ENET_QOS_DMA_CHX_SLOT_FUNC_CTRL_STAT_SIV_MASK (0xFFF0U) +#define ENET_QOS_DMA_CHX_SLOT_FUNC_CTRL_STAT_SIV_SHIFT (4U) +/*! SIV - Slot Interval Value This field controls the period of the slot interval in which the TxDMA + * fetches the scheduled packets. + */ +#define ENET_QOS_DMA_CHX_SLOT_FUNC_CTRL_STAT_SIV(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_SLOT_FUNC_CTRL_STAT_SIV_SHIFT)) & ENET_QOS_DMA_CHX_SLOT_FUNC_CTRL_STAT_SIV_MASK) + +#define ENET_QOS_DMA_CHX_SLOT_FUNC_CTRL_STAT_RSN_MASK (0xF0000U) +#define ENET_QOS_DMA_CHX_SLOT_FUNC_CTRL_STAT_RSN_SHIFT (16U) +/*! RSN - Reference Slot Number This field gives the current value of the reference slot number in the DMA. */ +#define ENET_QOS_DMA_CHX_SLOT_FUNC_CTRL_STAT_RSN(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_SLOT_FUNC_CTRL_STAT_RSN_SHIFT)) & ENET_QOS_DMA_CHX_SLOT_FUNC_CTRL_STAT_RSN_MASK) +/*! @} */ + +/* The count of ENET_QOS_DMA_CHX_SLOT_FUNC_CTRL_STAT */ +#define ENET_QOS_DMA_CHX_SLOT_FUNC_CTRL_STAT_COUNT (5U) + +/*! @name DMA_CHX_CUR_HST_TXDESC - Channel 0 Current Application Transmit Descriptor..Channel 4 Current Application Transmit Descriptor */ +/*! @{ */ + +#define ENET_QOS_DMA_CHX_CUR_HST_TXDESC_CURTDESAPTR_MASK (0xFFFFFFFFU) +#define ENET_QOS_DMA_CHX_CUR_HST_TXDESC_CURTDESAPTR_SHIFT (0U) +/*! CURTDESAPTR - Application Transmit Descriptor Address Pointer The DMA updates this pointer during Tx operation. */ +#define ENET_QOS_DMA_CHX_CUR_HST_TXDESC_CURTDESAPTR(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_CUR_HST_TXDESC_CURTDESAPTR_SHIFT)) & ENET_QOS_DMA_CHX_CUR_HST_TXDESC_CURTDESAPTR_MASK) +/*! @} */ + +/* The count of ENET_QOS_DMA_CHX_CUR_HST_TXDESC */ +#define ENET_QOS_DMA_CHX_CUR_HST_TXDESC_COUNT (5U) + +/*! @name DMA_CHX_CUR_HST_RXDESC - Channel 0 Current Application Receive Descriptor..Channel 4 Current Application Receive Descriptor */ +/*! @{ */ + +#define ENET_QOS_DMA_CHX_CUR_HST_RXDESC_CURRDESAPTR_MASK (0xFFFFFFFFU) +#define ENET_QOS_DMA_CHX_CUR_HST_RXDESC_CURRDESAPTR_SHIFT (0U) +/*! CURRDESAPTR - Application Receive Descriptor Address Pointer The DMA updates this pointer during Rx operation. */ +#define ENET_QOS_DMA_CHX_CUR_HST_RXDESC_CURRDESAPTR(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_CUR_HST_RXDESC_CURRDESAPTR_SHIFT)) & ENET_QOS_DMA_CHX_CUR_HST_RXDESC_CURRDESAPTR_MASK) +/*! @} */ + +/* The count of ENET_QOS_DMA_CHX_CUR_HST_RXDESC */ +#define ENET_QOS_DMA_CHX_CUR_HST_RXDESC_COUNT (5U) + +/*! @name DMA_CHX_CUR_HST_TXBUF - Channel 0 Current Application Transmit Buffer Address..Channel 4 Current Application Transmit Buffer Address */ +/*! @{ */ + +#define ENET_QOS_DMA_CHX_CUR_HST_TXBUF_CURTBUFAPTR_MASK (0xFFFFFFFFU) +#define ENET_QOS_DMA_CHX_CUR_HST_TXBUF_CURTBUFAPTR_SHIFT (0U) +/*! CURTBUFAPTR - Application Transmit Buffer Address Pointer The DMA updates this pointer during Tx operation. */ +#define ENET_QOS_DMA_CHX_CUR_HST_TXBUF_CURTBUFAPTR(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_CUR_HST_TXBUF_CURTBUFAPTR_SHIFT)) & ENET_QOS_DMA_CHX_CUR_HST_TXBUF_CURTBUFAPTR_MASK) +/*! @} */ + +/* The count of ENET_QOS_DMA_CHX_CUR_HST_TXBUF */ +#define ENET_QOS_DMA_CHX_CUR_HST_TXBUF_COUNT (5U) + +/*! @name DMA_CHX_CUR_HST_RXBUF - Channel 0 Current Application Receive Buffer Address..Channel 4 Current Application Receive Buffer Address */ +/*! @{ */ + +#define ENET_QOS_DMA_CHX_CUR_HST_RXBUF_CURRBUFAPTR_MASK (0xFFFFFFFFU) +#define ENET_QOS_DMA_CHX_CUR_HST_RXBUF_CURRBUFAPTR_SHIFT (0U) +/*! CURRBUFAPTR - Application Receive Buffer Address Pointer The DMA updates this pointer during Rx operation. */ +#define ENET_QOS_DMA_CHX_CUR_HST_RXBUF_CURRBUFAPTR(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_CUR_HST_RXBUF_CURRBUFAPTR_SHIFT)) & ENET_QOS_DMA_CHX_CUR_HST_RXBUF_CURRBUFAPTR_MASK) +/*! @} */ + +/* The count of ENET_QOS_DMA_CHX_CUR_HST_RXBUF */ +#define ENET_QOS_DMA_CHX_CUR_HST_RXBUF_COUNT (5U) + +/*! @name DMA_CHX_STAT - DMA Channel 0 Status..DMA Channel 4 Status */ +/*! @{ */ + +#define ENET_QOS_DMA_CHX_STAT_TI_MASK (0x1U) +#define ENET_QOS_DMA_CHX_STAT_TI_SHIFT (0U) +/*! TI - Transmit Interrupt This bit indicates that the packet transmission is complete. + * 0b0..Transmit Interrupt status not detected + * 0b1..Transmit Interrupt status detected + */ +#define ENET_QOS_DMA_CHX_STAT_TI(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_STAT_TI_SHIFT)) & ENET_QOS_DMA_CHX_STAT_TI_MASK) + +#define ENET_QOS_DMA_CHX_STAT_TPS_MASK (0x2U) +#define ENET_QOS_DMA_CHX_STAT_TPS_SHIFT (1U) +/*! TPS - Transmit Process Stopped This bit is set when the transmission is stopped. + * 0b0..Transmit Process Stopped status not detected + * 0b1..Transmit Process Stopped status detected + */ +#define ENET_QOS_DMA_CHX_STAT_TPS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_STAT_TPS_SHIFT)) & ENET_QOS_DMA_CHX_STAT_TPS_MASK) + +#define ENET_QOS_DMA_CHX_STAT_TBU_MASK (0x4U) +#define ENET_QOS_DMA_CHX_STAT_TBU_SHIFT (2U) +/*! TBU - Transmit Buffer Unavailable This bit indicates that the application owns the next + * descriptor in the Transmit list, and the DMA cannot acquire it. + * 0b0..Transmit Buffer Unavailable status not detected + * 0b1..Transmit Buffer Unavailable status detected + */ +#define ENET_QOS_DMA_CHX_STAT_TBU(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_STAT_TBU_SHIFT)) & ENET_QOS_DMA_CHX_STAT_TBU_MASK) + +#define ENET_QOS_DMA_CHX_STAT_RI_MASK (0x40U) +#define ENET_QOS_DMA_CHX_STAT_RI_SHIFT (6U) +/*! RI - Receive Interrupt This bit indicates that the packet reception is complete. + * 0b0..Receive Interrupt status not detected + * 0b1..Receive Interrupt status detected + */ +#define ENET_QOS_DMA_CHX_STAT_RI(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_STAT_RI_SHIFT)) & ENET_QOS_DMA_CHX_STAT_RI_MASK) + +#define ENET_QOS_DMA_CHX_STAT_RBU_MASK (0x80U) +#define ENET_QOS_DMA_CHX_STAT_RBU_SHIFT (7U) +/*! RBU - Receive Buffer Unavailable This bit indicates that the application owns the next + * descriptor in the Receive list, and the DMA cannot acquire it. + * 0b0..Receive Buffer Unavailable status not detected + * 0b1..Receive Buffer Unavailable status detected + */ +#define ENET_QOS_DMA_CHX_STAT_RBU(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_STAT_RBU_SHIFT)) & ENET_QOS_DMA_CHX_STAT_RBU_MASK) + +#define ENET_QOS_DMA_CHX_STAT_RPS_MASK (0x100U) +#define ENET_QOS_DMA_CHX_STAT_RPS_SHIFT (8U) +/*! RPS - Receive Process Stopped This bit is asserted when the Rx process enters the Stopped state. + * 0b0..Receive Process Stopped status not detected + * 0b1..Receive Process Stopped status detected + */ +#define ENET_QOS_DMA_CHX_STAT_RPS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_STAT_RPS_SHIFT)) & ENET_QOS_DMA_CHX_STAT_RPS_MASK) + +#define ENET_QOS_DMA_CHX_STAT_RWT_MASK (0x200U) +#define ENET_QOS_DMA_CHX_STAT_RWT_SHIFT (9U) +/*! RWT - Receive Watchdog Timeout This bit is asserted when a packet with length greater than 2,048 + * bytes (10,240 bytes when Jumbo Packet mode is enabled) is received. + * 0b0..Receive Watchdog Timeout status not detected + * 0b1..Receive Watchdog Timeout status detected + */ +#define ENET_QOS_DMA_CHX_STAT_RWT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_STAT_RWT_SHIFT)) & ENET_QOS_DMA_CHX_STAT_RWT_MASK) + +#define ENET_QOS_DMA_CHX_STAT_ETI_MASK (0x400U) +#define ENET_QOS_DMA_CHX_STAT_ETI_SHIFT (10U) +/*! ETI - Early Transmit Interrupt This bit when set indicates that the TxDMA has completed the + * transfer of packet data to the MTL TXFIFO memory. + * 0b0..Early Transmit Interrupt status not detected + * 0b1..Early Transmit Interrupt status detected + */ +#define ENET_QOS_DMA_CHX_STAT_ETI(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_STAT_ETI_SHIFT)) & ENET_QOS_DMA_CHX_STAT_ETI_MASK) + +#define ENET_QOS_DMA_CHX_STAT_ERI_MASK (0x800U) +#define ENET_QOS_DMA_CHX_STAT_ERI_SHIFT (11U) +/*! ERI - Early Receive Interrupt This bit when set indicates that the RxDMA has completed the + * transfer of packet data to the memory. + * 0b0..Early Receive Interrupt status not detected + * 0b1..Early Receive Interrupt status detected + */ +#define ENET_QOS_DMA_CHX_STAT_ERI(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_STAT_ERI_SHIFT)) & ENET_QOS_DMA_CHX_STAT_ERI_MASK) + +#define ENET_QOS_DMA_CHX_STAT_FBE_MASK (0x1000U) +#define ENET_QOS_DMA_CHX_STAT_FBE_SHIFT (12U) +/*! FBE - Fatal Bus Error This bit indicates that a bus error occurred (as described in the EB field). + * 0b0..Fatal Bus Error status not detected + * 0b1..Fatal Bus Error status detected + */ +#define ENET_QOS_DMA_CHX_STAT_FBE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_STAT_FBE_SHIFT)) & ENET_QOS_DMA_CHX_STAT_FBE_MASK) + +#define ENET_QOS_DMA_CHX_STAT_CDE_MASK (0x2000U) +#define ENET_QOS_DMA_CHX_STAT_CDE_SHIFT (13U) +/*! CDE - Context Descriptor Error This bit indicates that the DMA Tx/Rx engine received a + * descriptor error, which indicates invalid context in the middle of packet flow ( intermediate + * descriptor) or all one's descriptor in Tx case and on Rx side it indicates DMA has read a descriptor + * with either of the buffer address as ones which is considered to be invalid. + * 0b0..Context Descriptor Error status not detected + * 0b1..Context Descriptor Error status detected + */ +#define ENET_QOS_DMA_CHX_STAT_CDE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_STAT_CDE_SHIFT)) & ENET_QOS_DMA_CHX_STAT_CDE_MASK) + +#define ENET_QOS_DMA_CHX_STAT_AIS_MASK (0x4000U) +#define ENET_QOS_DMA_CHX_STAT_AIS_SHIFT (14U) +/*! AIS - Abnormal Interrupt Summary Abnormal Interrupt Summary bit value is the logical OR of the + * following when the corresponding interrupt bits are enabled in the DMA_CH3_INTERRUPT_ENABLE + * register: - Bit 1: Transmit Process Stopped - Bit 7: Receive Buffer Unavailable - Bit 8: Receive + * Process Stopped - Bit 10: Early Transmit Interrupt - Bit 12: Fatal Bus Error - Bit 13: Context + * Descriptor Error Only unmasked bits affect the Abnormal Interrupt Summary bit. + * 0b0..Abnormal Interrupt Summary status not detected + * 0b1..Abnormal Interrupt Summary status detected + */ +#define ENET_QOS_DMA_CHX_STAT_AIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_STAT_AIS_SHIFT)) & ENET_QOS_DMA_CHX_STAT_AIS_MASK) + +#define ENET_QOS_DMA_CHX_STAT_NIS_MASK (0x8000U) +#define ENET_QOS_DMA_CHX_STAT_NIS_SHIFT (15U) +/*! NIS - Normal Interrupt Summary Normal Interrupt Summary bit value is the logical OR of the + * following bits when the corresponding interrupt bits are enabled in the DMA_CH3_INTERRUPT_ENABLE + * register: - Bit 0: Transmit Interrupt - Bit 2: Transmit Buffer Unavailable - Bit 6: Receive + * Interrupt - Bit 11: Early Receive Interrupt Only unmasked bits (interrupts for which interrupt + * enable is set in DMA_CH3_INTERRUPT_ENABLE register) affect the Normal Interrupt Summary bit. + * 0b0..Normal Interrupt Summary status not detected + * 0b1..Normal Interrupt Summary status detected + */ +#define ENET_QOS_DMA_CHX_STAT_NIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_STAT_NIS_SHIFT)) & ENET_QOS_DMA_CHX_STAT_NIS_MASK) + +#define ENET_QOS_DMA_CHX_STAT_TEB_MASK (0x70000U) +#define ENET_QOS_DMA_CHX_STAT_TEB_SHIFT (16U) +/*! TEB - Tx DMA Error Bits This field indicates the type of error that caused a Bus Error. */ +#define ENET_QOS_DMA_CHX_STAT_TEB(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_STAT_TEB_SHIFT)) & ENET_QOS_DMA_CHX_STAT_TEB_MASK) + +#define ENET_QOS_DMA_CHX_STAT_REB_MASK (0x380000U) +#define ENET_QOS_DMA_CHX_STAT_REB_SHIFT (19U) +/*! REB - Rx DMA Error Bits This field indicates the type of error that caused a Bus Error. */ +#define ENET_QOS_DMA_CHX_STAT_REB(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_STAT_REB_SHIFT)) & ENET_QOS_DMA_CHX_STAT_REB_MASK) +/*! @} */ + +/* The count of ENET_QOS_DMA_CHX_STAT */ +#define ENET_QOS_DMA_CHX_STAT_COUNT (5U) + +/*! @name DMA_CHX_MISS_FRAME_CNT - Channel 0 Missed Frame Counter..Channel 4 Missed Frame Counter */ +/*! @{ */ + +#define ENET_QOS_DMA_CHX_MISS_FRAME_CNT_MFC_MASK (0x7FFU) +#define ENET_QOS_DMA_CHX_MISS_FRAME_CNT_MFC_SHIFT (0U) +/*! MFC - Dropped Packet Counters This counter indicates the number of packet counters that are + * dropped by the DMA either because of bus error or because of programming RPF field in + * DMA_CH2_RX_CONTROL register. + */ +#define ENET_QOS_DMA_CHX_MISS_FRAME_CNT_MFC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_MISS_FRAME_CNT_MFC_SHIFT)) & ENET_QOS_DMA_CHX_MISS_FRAME_CNT_MFC_MASK) + +#define ENET_QOS_DMA_CHX_MISS_FRAME_CNT_MFCO_MASK (0x8000U) +#define ENET_QOS_DMA_CHX_MISS_FRAME_CNT_MFCO_SHIFT (15U) +/*! MFCO - Overflow status of the MFC Counter When this bit is set then the MFC counter does not get incremented further. + * 0b0..Miss Frame Counter overflow not occurred + * 0b1..Miss Frame Counter overflow occurred + */ +#define ENET_QOS_DMA_CHX_MISS_FRAME_CNT_MFCO(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_MISS_FRAME_CNT_MFCO_SHIFT)) & ENET_QOS_DMA_CHX_MISS_FRAME_CNT_MFCO_MASK) +/*! @} */ + +/* The count of ENET_QOS_DMA_CHX_MISS_FRAME_CNT */ +#define ENET_QOS_DMA_CHX_MISS_FRAME_CNT_COUNT (5U) + +/*! @name DMA_CHX_RXP_ACCEPT_CNT - Channel 0 RXP Frames Accepted Counter..Channel 4 RXP Frames Accepted Counter */ +/*! @{ */ + +#define ENET_QOS_DMA_CHX_RXP_ACCEPT_CNT_RXPAC_MASK (0x7FFFFFFFU) +#define ENET_QOS_DMA_CHX_RXP_ACCEPT_CNT_RXPAC_SHIFT (0U) +/*! RXPAC - Rx Parser Accept Counter This 31-bit counter is implemented whenever a Rx Parser Accept a packet due to AF =1. */ +#define ENET_QOS_DMA_CHX_RXP_ACCEPT_CNT_RXPAC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_RXP_ACCEPT_CNT_RXPAC_SHIFT)) & ENET_QOS_DMA_CHX_RXP_ACCEPT_CNT_RXPAC_MASK) + +#define ENET_QOS_DMA_CHX_RXP_ACCEPT_CNT_RXPACOF_MASK (0x80000000U) +#define ENET_QOS_DMA_CHX_RXP_ACCEPT_CNT_RXPACOF_SHIFT (31U) +/*! RXPACOF - Rx Parser Accept Counter Overflow Bit When set, this bit indicates that the RXPAC + * Counter field crossed the maximum limit. + * 0b0..Rx Parser Accept Counter overflow not occurred + * 0b1..Rx Parser Accept Counter overflow occurred + */ +#define ENET_QOS_DMA_CHX_RXP_ACCEPT_CNT_RXPACOF(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_RXP_ACCEPT_CNT_RXPACOF_SHIFT)) & ENET_QOS_DMA_CHX_RXP_ACCEPT_CNT_RXPACOF_MASK) +/*! @} */ + +/* The count of ENET_QOS_DMA_CHX_RXP_ACCEPT_CNT */ +#define ENET_QOS_DMA_CHX_RXP_ACCEPT_CNT_COUNT (5U) + + +/*! + * @} + */ /* end of group ENET_QOS_Register_Masks */ + + +/* ENET_QOS - Peripheral instance base addresses */ +/** Peripheral ENET_QOS base address */ +#define ENET_QOS_BASE (0x428A0000u) +/** Peripheral ENET_QOS base pointer */ +#define ENET_QOS ((ENET_QOS_Type *)ENET_QOS_BASE) +/** Array initializer of ENET_QOS peripheral base addresses */ +#define ENET_QOS_BASE_ADDRS { ENET_QOS_BASE } +/** Array initializer of ENET_QOS peripheral base pointers */ +#define ENET_QOS_BASE_PTRS { ENET_QOS } + +/*! + * @} + */ /* end of group ENET_QOS_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- FLEXIO Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup FLEXIO_Peripheral_Access_Layer FLEXIO Peripheral Access Layer + * @{ + */ + +/** FLEXIO - Register Layout Typedef */ +typedef struct { + __I uint32_t VERID; /**< Version ID, offset: 0x0 */ + __I uint32_t PARAM; /**< Parameter, offset: 0x4 */ + __IO uint32_t CTRL; /**< FLEXIO Control, offset: 0x8 */ + __I uint32_t PIN; /**< Pin State, offset: 0xC */ + __IO uint32_t SHIFTSTAT; /**< Shifter Status, offset: 0x10 */ + __IO uint32_t SHIFTERR; /**< Shifter Error, offset: 0x14 */ + __IO uint32_t TIMSTAT; /**< Timer Status Flag, offset: 0x18 */ + uint8_t RESERVED_0[4]; + __IO uint32_t SHIFTSIEN; /**< Shifter Status Interrupt Enable, offset: 0x20 */ + __IO uint32_t SHIFTEIEN; /**< Shifter Error Interrupt Enable, offset: 0x24 */ + __IO uint32_t TIMIEN; /**< Timer Interrupt Enable, offset: 0x28 */ + uint8_t RESERVED_1[4]; + __IO uint32_t SHIFTSDEN; /**< Shifter Status DMA Enable, offset: 0x30 */ + uint8_t RESERVED_2[4]; + __IO uint32_t TIMERSDEN; /**< Timer Status DMA Enable, offset: 0x38 */ + uint8_t RESERVED_3[4]; + __IO uint32_t SHIFTSTATE; /**< Shifter State, offset: 0x40 */ + uint8_t RESERVED_4[4]; + __IO uint32_t TRGSTAT; /**< Trigger Status, offset: 0x48 */ + __IO uint32_t TRIGIEN; /**< External Trigger Interrupt Enable, offset: 0x4C */ + __IO uint32_t PINSTAT; /**< Pin Status, offset: 0x50 */ + __IO uint32_t PINIEN; /**< Pin Interrupt Enable, offset: 0x54 */ + __IO uint32_t PINREN; /**< Pin Rising Edge Enable, offset: 0x58 */ + __IO uint32_t PINFEN; /**< Pin Falling Edge Enable, offset: 0x5C */ + __IO uint32_t PINOUTD; /**< Pin Output Data, offset: 0x60 */ + __IO uint32_t PINOUTE; /**< Pin Output Enable, offset: 0x64 */ + __IO uint32_t PINOUTDIS; /**< Pin Output Disable, offset: 0x68 */ + __IO uint32_t PINOUTCLR; /**< Pin Output Clear, offset: 0x6C */ + __IO uint32_t PINOUTSET; /**< Pin Output Set, offset: 0x70 */ + __IO uint32_t PINOUTTOG; /**< Pin Output Toggle, offset: 0x74 */ + uint8_t RESERVED_5[8]; + __IO uint32_t SHIFTCTL[8]; /**< Shifter Control, array offset: 0x80, array step: 0x4 */ + uint8_t RESERVED_6[96]; + __IO uint32_t SHIFTCFG[8]; /**< Shifter Configuration, array offset: 0x100, array step: 0x4 */ + uint8_t RESERVED_7[224]; + __IO uint32_t SHIFTBUF[8]; /**< Shifter Buffer, array offset: 0x200, array step: 0x4 */ + uint8_t RESERVED_8[96]; + __IO uint32_t SHIFTBUFBIS[8]; /**< Shifter Buffer Bit Swapped, array offset: 0x280, array step: 0x4 */ + uint8_t RESERVED_9[96]; + __IO uint32_t SHIFTBUFBYS[8]; /**< Shifter Buffer Byte Swapped, array offset: 0x300, array step: 0x4 */ + uint8_t RESERVED_10[96]; + __IO uint32_t SHIFTBUFBBS[8]; /**< Shifter Buffer Bit Byte Swapped, array offset: 0x380, array step: 0x4 */ + uint8_t RESERVED_11[96]; + __IO uint32_t TIMCTL[8]; /**< Timer Control, array offset: 0x400, array step: 0x4 */ + uint8_t RESERVED_12[96]; + __IO uint32_t TIMCFG[8]; /**< Timer Configuration, array offset: 0x480, array step: 0x4 */ + uint8_t RESERVED_13[96]; + __IO uint32_t TIMCMP[8]; /**< Timer Compare, array offset: 0x500, array step: 0x4 */ + uint8_t RESERVED_14[352]; + __IO uint32_t SHIFTBUFNBS[8]; /**< Shifter Buffer Nibble Byte Swapped, array offset: 0x680, array step: 0x4 */ + uint8_t RESERVED_15[96]; + __IO uint32_t SHIFTBUFHWS[8]; /**< Shifter Buffer Halfword Swapped, array offset: 0x700, array step: 0x4 */ + uint8_t RESERVED_16[96]; + __IO uint32_t SHIFTBUFNIS[8]; /**< Shifter Buffer Nibble Swapped, array offset: 0x780, array step: 0x4 */ + uint8_t RESERVED_17[96]; + __IO uint32_t SHIFTBUFOES[8]; /**< Shifter Buffer Odd Even Swapped, array offset: 0x800, array step: 0x4 */ + uint8_t RESERVED_18[96]; + __IO uint32_t SHIFTBUFEOS[8]; /**< Shifter Buffer Even Odd Swapped, array offset: 0x880, array step: 0x4 */ + uint8_t RESERVED_19[96]; + __IO uint32_t SHIFTBUFHBS[8]; /**< Shifter Buffer Halfword Byte Swapped, array offset: 0x900, array step: 0x4 */ +} FLEXIO_Type; + +/* ---------------------------------------------------------------------------- + -- FLEXIO Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup FLEXIO_Register_Masks FLEXIO Register Masks + * @{ + */ + +/*! @name VERID - Version ID */ +/*! @{ */ + +#define FLEXIO_VERID_FEATURE_MASK (0xFFFFU) +#define FLEXIO_VERID_FEATURE_SHIFT (0U) +/*! FEATURE - Feature Specification Number + * 0b0000000000000000..Standard features implemented + * 0b0000000000000001..State, logic, and parallel modes supported + * 0b0000000000000010..Pin control registers supported + * 0b0000000000000011..State, logic, and parallel modes, plus pin control registers supported + */ +#define FLEXIO_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_VERID_FEATURE_SHIFT)) & FLEXIO_VERID_FEATURE_MASK) + +#define FLEXIO_VERID_MINOR_MASK (0xFF0000U) +#define FLEXIO_VERID_MINOR_SHIFT (16U) +/*! MINOR - Minor Version Number */ +#define FLEXIO_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_VERID_MINOR_SHIFT)) & FLEXIO_VERID_MINOR_MASK) + +#define FLEXIO_VERID_MAJOR_MASK (0xFF000000U) +#define FLEXIO_VERID_MAJOR_SHIFT (24U) +/*! MAJOR - Major Version Number */ +#define FLEXIO_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_VERID_MAJOR_SHIFT)) & FLEXIO_VERID_MAJOR_MASK) +/*! @} */ + +/*! @name PARAM - Parameter */ +/*! @{ */ + +#define FLEXIO_PARAM_SHIFTER_MASK (0xFFU) +#define FLEXIO_PARAM_SHIFTER_SHIFT (0U) +/*! SHIFTER - Shifter Number */ +#define FLEXIO_PARAM_SHIFTER(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_SHIFTER_SHIFT)) & FLEXIO_PARAM_SHIFTER_MASK) + +#define FLEXIO_PARAM_TIMER_MASK (0xFF00U) +#define FLEXIO_PARAM_TIMER_SHIFT (8U) +/*! TIMER - Timer Number */ +#define FLEXIO_PARAM_TIMER(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_TIMER_SHIFT)) & FLEXIO_PARAM_TIMER_MASK) + +#define FLEXIO_PARAM_PIN_MASK (0xFF0000U) +#define FLEXIO_PARAM_PIN_SHIFT (16U) +/*! PIN - Pin Number */ +#define FLEXIO_PARAM_PIN(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_PIN_SHIFT)) & FLEXIO_PARAM_PIN_MASK) + +#define FLEXIO_PARAM_TRIGGER_MASK (0xFF000000U) +#define FLEXIO_PARAM_TRIGGER_SHIFT (24U) +/*! TRIGGER - Trigger Number */ +#define FLEXIO_PARAM_TRIGGER(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_TRIGGER_SHIFT)) & FLEXIO_PARAM_TRIGGER_MASK) +/*! @} */ + +/*! @name CTRL - FLEXIO Control */ +/*! @{ */ + +#define FLEXIO_CTRL_FLEXEN_MASK (0x1U) +#define FLEXIO_CTRL_FLEXEN_SHIFT (0U) +/*! FLEXEN - FLEXIO Enable + * 0b0..Disable + * 0b1..Enable + */ +#define FLEXIO_CTRL_FLEXEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_FLEXEN_SHIFT)) & FLEXIO_CTRL_FLEXEN_MASK) + +#define FLEXIO_CTRL_SWRST_MASK (0x2U) +#define FLEXIO_CTRL_SWRST_SHIFT (1U) +/*! SWRST - Software Reset + * 0b0..Disabled + * 0b1..Enabled + */ +#define FLEXIO_CTRL_SWRST(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_SWRST_SHIFT)) & FLEXIO_CTRL_SWRST_MASK) + +#define FLEXIO_CTRL_FASTACC_MASK (0x4U) +#define FLEXIO_CTRL_FASTACC_SHIFT (2U) +/*! FASTACC - Fast Access + * 0b0..Normal + * 0b1..Fast + */ +#define FLEXIO_CTRL_FASTACC(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_FASTACC_SHIFT)) & FLEXIO_CTRL_FASTACC_MASK) + +#define FLEXIO_CTRL_DBGE_MASK (0x40000000U) +#define FLEXIO_CTRL_DBGE_SHIFT (30U) +/*! DBGE - Debug Enable + * 0b0..Disable + * 0b1..Enable + */ +#define FLEXIO_CTRL_DBGE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_DBGE_SHIFT)) & FLEXIO_CTRL_DBGE_MASK) + +#define FLEXIO_CTRL_DOZEN_MASK (0x80000000U) +#define FLEXIO_CTRL_DOZEN_SHIFT (31U) +/*! DOZEN - Doze Enable + * 0b0..Enable + * 0b1..Disable + */ +#define FLEXIO_CTRL_DOZEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_DOZEN_SHIFT)) & FLEXIO_CTRL_DOZEN_MASK) +/*! @} */ + +/*! @name PIN - Pin State */ +/*! @{ */ + +#define FLEXIO_PIN_PDI_MASK (0xFFFFFFFFU) +#define FLEXIO_PIN_PDI_SHIFT (0U) +/*! PDI - Pin Data Input */ +#define FLEXIO_PIN_PDI(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PIN_PDI_SHIFT)) & FLEXIO_PIN_PDI_MASK) +/*! @} */ + +/*! @name SHIFTSTAT - Shifter Status */ +/*! @{ */ + +#define FLEXIO_SHIFTSTAT_SSF_MASK (0xFFU) +#define FLEXIO_SHIFTSTAT_SSF_SHIFT (0U) +/*! SSF - Shifter Status Flag + * 0b00000000..Clear + * 0b00000000..No effect + * 0b00000001..Set + * 0b00000001..Clear the flag + */ +#define FLEXIO_SHIFTSTAT_SSF(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSTAT_SSF_SHIFT)) & FLEXIO_SHIFTSTAT_SSF_MASK) +/*! @} */ + +/*! @name SHIFTERR - Shifter Error */ +/*! @{ */ + +#define FLEXIO_SHIFTERR_SEF_MASK (0xFFU) +#define FLEXIO_SHIFTERR_SEF_SHIFT (0U) +/*! SEF - Shifter Error Flag + * 0b00000000..Clear + * 0b00000000..No effect + * 0b00000001..Set + * 0b00000001..Clear the flag + */ +#define FLEXIO_SHIFTERR_SEF(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTERR_SEF_SHIFT)) & FLEXIO_SHIFTERR_SEF_MASK) +/*! @} */ + +/*! @name TIMSTAT - Timer Status Flag */ +/*! @{ */ + +#define FLEXIO_TIMSTAT_TSF_MASK (0xFFU) +#define FLEXIO_TIMSTAT_TSF_SHIFT (0U) +/*! TSF - Timer Status Flag + * 0b00000000..Clear + * 0b00000000..No effect + * 0b00000001..Set + * 0b00000001..Clear the flag + */ +#define FLEXIO_TIMSTAT_TSF(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMSTAT_TSF_SHIFT)) & FLEXIO_TIMSTAT_TSF_MASK) +/*! @} */ + +/*! @name SHIFTSIEN - Shifter Status Interrupt Enable */ +/*! @{ */ + +#define FLEXIO_SHIFTSIEN_SSIE_MASK (0xFFU) +#define FLEXIO_SHIFTSIEN_SSIE_SHIFT (0U) +/*! SSIE - Shifter Status Interrupt Enable */ +#define FLEXIO_SHIFTSIEN_SSIE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSIEN_SSIE_SHIFT)) & FLEXIO_SHIFTSIEN_SSIE_MASK) +/*! @} */ + +/*! @name SHIFTEIEN - Shifter Error Interrupt Enable */ +/*! @{ */ + +#define FLEXIO_SHIFTEIEN_SEIE_MASK (0xFFU) +#define FLEXIO_SHIFTEIEN_SEIE_SHIFT (0U) +/*! SEIE - Shifter Error Interrupt Enable */ +#define FLEXIO_SHIFTEIEN_SEIE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTEIEN_SEIE_SHIFT)) & FLEXIO_SHIFTEIEN_SEIE_MASK) +/*! @} */ + +/*! @name TIMIEN - Timer Interrupt Enable */ +/*! @{ */ + +#define FLEXIO_TIMIEN_TEIE_MASK (0xFFU) +#define FLEXIO_TIMIEN_TEIE_SHIFT (0U) +/*! TEIE - Timer Status Interrupt Enable */ +#define FLEXIO_TIMIEN_TEIE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMIEN_TEIE_SHIFT)) & FLEXIO_TIMIEN_TEIE_MASK) +/*! @} */ + +/*! @name SHIFTSDEN - Shifter Status DMA Enable */ +/*! @{ */ + +#define FLEXIO_SHIFTSDEN_SSDE_MASK (0xFFU) +#define FLEXIO_SHIFTSDEN_SSDE_SHIFT (0U) +/*! SSDE - Shifter Status DMA Enable */ +#define FLEXIO_SHIFTSDEN_SSDE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSDEN_SSDE_SHIFT)) & FLEXIO_SHIFTSDEN_SSDE_MASK) +/*! @} */ + +/*! @name TIMERSDEN - Timer Status DMA Enable */ +/*! @{ */ + +#define FLEXIO_TIMERSDEN_TSDE_MASK (0xFFU) +#define FLEXIO_TIMERSDEN_TSDE_SHIFT (0U) +/*! TSDE - Timer Status DMA Enable */ +#define FLEXIO_TIMERSDEN_TSDE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMERSDEN_TSDE_SHIFT)) & FLEXIO_TIMERSDEN_TSDE_MASK) +/*! @} */ + +/*! @name SHIFTSTATE - Shifter State */ +/*! @{ */ + +#define FLEXIO_SHIFTSTATE_STATE_MASK (0x7U) +#define FLEXIO_SHIFTSTATE_STATE_SHIFT (0U) +/*! STATE - Current State Pointer */ +#define FLEXIO_SHIFTSTATE_STATE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSTATE_STATE_SHIFT)) & FLEXIO_SHIFTSTATE_STATE_MASK) +/*! @} */ + +/*! @name TRGSTAT - Trigger Status */ +/*! @{ */ + +#define FLEXIO_TRGSTAT_ETSF_MASK (0xFU) +#define FLEXIO_TRGSTAT_ETSF_SHIFT (0U) +/*! ETSF - External Trigger Status Flag + * 0b0000..Clear + * 0b0000..No effect + * 0b0001..Set + * 0b0001..Clear the flag + */ +#define FLEXIO_TRGSTAT_ETSF(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TRGSTAT_ETSF_SHIFT)) & FLEXIO_TRGSTAT_ETSF_MASK) +/*! @} */ + +/*! @name TRIGIEN - External Trigger Interrupt Enable */ +/*! @{ */ + +#define FLEXIO_TRIGIEN_TRIE_MASK (0xFU) +#define FLEXIO_TRIGIEN_TRIE_SHIFT (0U) +/*! TRIE - External Trigger Interrupt Enable */ +#define FLEXIO_TRIGIEN_TRIE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TRIGIEN_TRIE_SHIFT)) & FLEXIO_TRIGIEN_TRIE_MASK) +/*! @} */ + +/*! @name PINSTAT - Pin Status */ +/*! @{ */ + +#define FLEXIO_PINSTAT_PSF_MASK (0xFFFFFFFFU) +#define FLEXIO_PINSTAT_PSF_SHIFT (0U) +/*! PSF - Pin Status Flag + * 0b00000000000000000000000000000000..Clear + * 0b00000000000000000000000000000000..No effect + * 0b00000000000000000000000000000001..Set + * 0b00000000000000000000000000000001..Clear the flag + */ +#define FLEXIO_PINSTAT_PSF(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PINSTAT_PSF_SHIFT)) & FLEXIO_PINSTAT_PSF_MASK) +/*! @} */ + +/*! @name PINIEN - Pin Interrupt Enable */ +/*! @{ */ + +#define FLEXIO_PINIEN_PSIE_MASK (0xFFFFFFFFU) +#define FLEXIO_PINIEN_PSIE_SHIFT (0U) +/*! PSIE - Pin Status Interrupt Enable */ +#define FLEXIO_PINIEN_PSIE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PINIEN_PSIE_SHIFT)) & FLEXIO_PINIEN_PSIE_MASK) +/*! @} */ + +/*! @name PINREN - Pin Rising Edge Enable */ +/*! @{ */ + +#define FLEXIO_PINREN_PRE_MASK (0xFFFFFFFFU) +#define FLEXIO_PINREN_PRE_SHIFT (0U) +/*! PRE - Pin Rising Edge */ +#define FLEXIO_PINREN_PRE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PINREN_PRE_SHIFT)) & FLEXIO_PINREN_PRE_MASK) +/*! @} */ + +/*! @name PINFEN - Pin Falling Edge Enable */ +/*! @{ */ + +#define FLEXIO_PINFEN_PFE_MASK (0xFFFFFFFFU) +#define FLEXIO_PINFEN_PFE_SHIFT (0U) +/*! PFE - Pin Falling Edge */ +#define FLEXIO_PINFEN_PFE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PINFEN_PFE_SHIFT)) & FLEXIO_PINFEN_PFE_MASK) +/*! @} */ + +/*! @name PINOUTD - Pin Output Data */ +/*! @{ */ + +#define FLEXIO_PINOUTD_OUTD_MASK (0xFFFFFFFFU) +#define FLEXIO_PINOUTD_OUTD_SHIFT (0U) +/*! OUTD - Output Data */ +#define FLEXIO_PINOUTD_OUTD(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PINOUTD_OUTD_SHIFT)) & FLEXIO_PINOUTD_OUTD_MASK) +/*! @} */ + +/*! @name PINOUTE - Pin Output Enable */ +/*! @{ */ + +#define FLEXIO_PINOUTE_OUTE_MASK (0xFFFFFFFFU) +#define FLEXIO_PINOUTE_OUTE_SHIFT (0U) +/*! OUTE - Output Enable */ +#define FLEXIO_PINOUTE_OUTE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PINOUTE_OUTE_SHIFT)) & FLEXIO_PINOUTE_OUTE_MASK) +/*! @} */ + +/*! @name PINOUTDIS - Pin Output Disable */ +/*! @{ */ + +#define FLEXIO_PINOUTDIS_OUTDIS_MASK (0xFFFFFFFFU) +#define FLEXIO_PINOUTDIS_OUTDIS_SHIFT (0U) +/*! OUTDIS - Output Disable */ +#define FLEXIO_PINOUTDIS_OUTDIS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PINOUTDIS_OUTDIS_SHIFT)) & FLEXIO_PINOUTDIS_OUTDIS_MASK) +/*! @} */ + +/*! @name PINOUTCLR - Pin Output Clear */ +/*! @{ */ + +#define FLEXIO_PINOUTCLR_OUTCLR_MASK (0xFFFFFFFFU) +#define FLEXIO_PINOUTCLR_OUTCLR_SHIFT (0U) +/*! OUTCLR - Output Clear */ +#define FLEXIO_PINOUTCLR_OUTCLR(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PINOUTCLR_OUTCLR_SHIFT)) & FLEXIO_PINOUTCLR_OUTCLR_MASK) +/*! @} */ + +/*! @name PINOUTSET - Pin Output Set */ +/*! @{ */ + +#define FLEXIO_PINOUTSET_OUTSET_MASK (0xFFFFFFFFU) +#define FLEXIO_PINOUTSET_OUTSET_SHIFT (0U) +/*! OUTSET - Output Set */ +#define FLEXIO_PINOUTSET_OUTSET(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PINOUTSET_OUTSET_SHIFT)) & FLEXIO_PINOUTSET_OUTSET_MASK) +/*! @} */ + +/*! @name PINOUTTOG - Pin Output Toggle */ +/*! @{ */ + +#define FLEXIO_PINOUTTOG_OUTTOG_MASK (0xFFFFFFFFU) +#define FLEXIO_PINOUTTOG_OUTTOG_SHIFT (0U) +/*! OUTTOG - Output Toggle */ +#define FLEXIO_PINOUTTOG_OUTTOG(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PINOUTTOG_OUTTOG_SHIFT)) & FLEXIO_PINOUTTOG_OUTTOG_MASK) +/*! @} */ + +/*! @name SHIFTCTL - Shifter Control */ +/*! @{ */ + +#define FLEXIO_SHIFTCTL_SMOD_MASK (0x7U) +#define FLEXIO_SHIFTCTL_SMOD_SHIFT (0U) +/*! SMOD - Shifter Mode + * 0b000..Disable + * 0b001..Receive mode; capture the current shifter content into SHIFTBUF on expiration of the timer + * 0b010..Transmit mode; load SHIFTBUF contents into the shifter on expiration of the timer + * 0b011..Reserved + * 0b100..Match Store mode; shifter data is compared to SHIFTBUF content on expiration of the timer + * 0b101..Match Continuous mode; shifter data is continuously compared to SHIFTBUF contents + * 0b110..State mode; SHIFTBUF contents store programmable state attributes + * 0b111..Logic mode; SHIFTBUF contents implement programmable logic lookup table + */ +#define FLEXIO_SHIFTCTL_SMOD(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_SMOD_SHIFT)) & FLEXIO_SHIFTCTL_SMOD_MASK) + +#define FLEXIO_SHIFTCTL_PINPOL_MASK (0x80U) +#define FLEXIO_SHIFTCTL_PINPOL_SHIFT (7U) +/*! PINPOL - Shifter Pin Polarity + * 0b0..Active high + * 0b1..Active low + */ +#define FLEXIO_SHIFTCTL_PINPOL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_PINPOL_SHIFT)) & FLEXIO_SHIFTCTL_PINPOL_MASK) + +#define FLEXIO_SHIFTCTL_PINSEL_MASK (0x1F00U) +#define FLEXIO_SHIFTCTL_PINSEL_SHIFT (8U) +/*! PINSEL - Shifter Pin Select */ +#define FLEXIO_SHIFTCTL_PINSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_PINSEL_SHIFT)) & FLEXIO_SHIFTCTL_PINSEL_MASK) + +#define FLEXIO_SHIFTCTL_PINCFG_MASK (0x30000U) +#define FLEXIO_SHIFTCTL_PINCFG_SHIFT (16U) +/*! PINCFG - Shifter Pin Configuration + * 0b00..Shifter pin output disabled + * 0b01..Shifter pin open-drain or bidirectional output enable + * 0b10..Shifter pin bidirectional output data + * 0b11..Shifter pin output + */ +#define FLEXIO_SHIFTCTL_PINCFG(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_PINCFG_SHIFT)) & FLEXIO_SHIFTCTL_PINCFG_MASK) + +#define FLEXIO_SHIFTCTL_TIMPOL_MASK (0x800000U) +#define FLEXIO_SHIFTCTL_TIMPOL_SHIFT (23U) +/*! TIMPOL - Timer Polarity + * 0b0..Positive edge + * 0b1..Negative edge + */ +#define FLEXIO_SHIFTCTL_TIMPOL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_TIMPOL_SHIFT)) & FLEXIO_SHIFTCTL_TIMPOL_MASK) + +#define FLEXIO_SHIFTCTL_TIMSEL_MASK (0x7000000U) +#define FLEXIO_SHIFTCTL_TIMSEL_SHIFT (24U) +/*! TIMSEL - Timer Select */ +#define FLEXIO_SHIFTCTL_TIMSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_TIMSEL_SHIFT)) & FLEXIO_SHIFTCTL_TIMSEL_MASK) +/*! @} */ + +/* The count of FLEXIO_SHIFTCTL */ +#define FLEXIO_SHIFTCTL_COUNT (8U) + +/*! @name SHIFTCFG - Shifter Configuration */ +/*! @{ */ + +#define FLEXIO_SHIFTCFG_SSTART_MASK (0x3U) +#define FLEXIO_SHIFTCFG_SSTART_SHIFT (0U) +/*! SSTART - Shifter Start + * 0b00..Start bit disabled for Transmitter, Receiver, and Match Store modes; Transmitter mode loads data on enable + * 0b01..Start bit disabled for Transmitter, Receiver, and Match Store modes; Transmitter mode loads data on first shift + * 0b10..Transmitter mode outputs start bit value 0 before loading data on first shift; if start bit is not 0, + * Receiver and Match Store modes set error flag + * 0b11..Transmitter mode outputs start bit value 1 before loading data on first shift; if start bit is not 1, + * Receiver and Match Store modes set error flag + */ +#define FLEXIO_SHIFTCFG_SSTART(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_SSTART_SHIFT)) & FLEXIO_SHIFTCFG_SSTART_MASK) + +#define FLEXIO_SHIFTCFG_SSTOP_MASK (0x30U) +#define FLEXIO_SHIFTCFG_SSTOP_SHIFT (4U) +/*! SSTOP - Shifter Stop + * 0b00..Stop bit disabled for Transmitter, Receiver, and Match Store modes + * 0b01..Stop bit disabled for Transmitter, Receiver, and Match Store modes; when timer is in stop condition, + * Receiver and Match Store modes store receive data on the configured shift edge + * 0b10..Transmitter mode outputs stop bit value 0 in Match Store mode; if stop bit is not 0, Receiver and Match + * Store modes set error flag (when timer is in stop condition, these modes also store receive data on the + * configured shift edge) + * 0b11..Transmitter mode outputs stop bit value 1 in Match Store mode; if stop bit is not 1, Receiver and Match + * Store modes set error flag (when timer is in stop condition, these modes also store receive data on the + * configured shift edge) + */ +#define FLEXIO_SHIFTCFG_SSTOP(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_SSTOP_SHIFT)) & FLEXIO_SHIFTCFG_SSTOP_MASK) + +#define FLEXIO_SHIFTCFG_INSRC_MASK (0x100U) +#define FLEXIO_SHIFTCFG_INSRC_SHIFT (8U) +/*! INSRC - Input Source + * 0b0..Pin + * 0b1..Shifter n+1 output + */ +#define FLEXIO_SHIFTCFG_INSRC(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_INSRC_SHIFT)) & FLEXIO_SHIFTCFG_INSRC_MASK) + +#define FLEXIO_SHIFTCFG_LATST_MASK (0x200U) +#define FLEXIO_SHIFTCFG_LATST_SHIFT (9U) +/*! LATST - Late Store + * 0b0..Store the pre-shift register state + * 0b1..Store the post-shift register state + */ +#define FLEXIO_SHIFTCFG_LATST(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_LATST_SHIFT)) & FLEXIO_SHIFTCFG_LATST_MASK) + +#define FLEXIO_SHIFTCFG_SSIZE_MASK (0x1000U) +#define FLEXIO_SHIFTCFG_SSIZE_SHIFT (12U) +/*! SSIZE - Shifter Size + * 0b0..32-bit + * 0b1..24-bit + */ +#define FLEXIO_SHIFTCFG_SSIZE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_SSIZE_SHIFT)) & FLEXIO_SHIFTCFG_SSIZE_MASK) + +#define FLEXIO_SHIFTCFG_PWIDTH_MASK (0x1F0000U) +#define FLEXIO_SHIFTCFG_PWIDTH_SHIFT (16U) +/*! PWIDTH - Parallel Width */ +#define FLEXIO_SHIFTCFG_PWIDTH(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_PWIDTH_SHIFT)) & FLEXIO_SHIFTCFG_PWIDTH_MASK) +/*! @} */ + +/* The count of FLEXIO_SHIFTCFG */ +#define FLEXIO_SHIFTCFG_COUNT (8U) + +/*! @name SHIFTBUF - Shifter Buffer */ +/*! @{ */ + +#define FLEXIO_SHIFTBUF_SHIFTBUF_MASK (0xFFFFFFFFU) +#define FLEXIO_SHIFTBUF_SHIFTBUF_SHIFT (0U) +/*! SHIFTBUF - Shift Buffer */ +#define FLEXIO_SHIFTBUF_SHIFTBUF(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUF_SHIFTBUF_SHIFT)) & FLEXIO_SHIFTBUF_SHIFTBUF_MASK) +/*! @} */ + +/* The count of FLEXIO_SHIFTBUF */ +#define FLEXIO_SHIFTBUF_COUNT (8U) + +/*! @name SHIFTBUFBIS - Shifter Buffer Bit Swapped */ +/*! @{ */ + +#define FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_MASK (0xFFFFFFFFU) +#define FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_SHIFT (0U) +/*! SHIFTBUFBIS - Shift Buffer */ +#define FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_SHIFT)) & FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_MASK) +/*! @} */ + +/* The count of FLEXIO_SHIFTBUFBIS */ +#define FLEXIO_SHIFTBUFBIS_COUNT (8U) + +/*! @name SHIFTBUFBYS - Shifter Buffer Byte Swapped */ +/*! @{ */ + +#define FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_MASK (0xFFFFFFFFU) +#define FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_SHIFT (0U) +/*! SHIFTBUFBYS - Shift Buffer */ +#define FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_SHIFT)) & FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_MASK) +/*! @} */ + +/* The count of FLEXIO_SHIFTBUFBYS */ +#define FLEXIO_SHIFTBUFBYS_COUNT (8U) + +/*! @name SHIFTBUFBBS - Shifter Buffer Bit Byte Swapped */ +/*! @{ */ + +#define FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_MASK (0xFFFFFFFFU) +#define FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_SHIFT (0U) +/*! SHIFTBUFBBS - Shift Buffer */ +#define FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_SHIFT)) & FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_MASK) +/*! @} */ + +/* The count of FLEXIO_SHIFTBUFBBS */ +#define FLEXIO_SHIFTBUFBBS_COUNT (8U) + +/*! @name TIMCTL - Timer Control */ +/*! @{ */ + +#define FLEXIO_TIMCTL_TIMOD_MASK (0x7U) +#define FLEXIO_TIMCTL_TIMOD_SHIFT (0U) +/*! TIMOD - Timer Mode + * 0b000..Timer disabled + * 0b001..Dual 8-bit counters baud mode + * 0b010..Dual 8-bit counters PWM high mode + * 0b011..Single 16-bit counter mode + * 0b100..Single 16-bit counter disable mode + * 0b101..Dual 8-bit counters word mode + * 0b110..Dual 8-bit counters PWM low mode + * 0b111..Single 16-bit input capture mode + */ +#define FLEXIO_TIMCTL_TIMOD(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TIMOD_SHIFT)) & FLEXIO_TIMCTL_TIMOD_MASK) + +#define FLEXIO_TIMCTL_ONETIM_MASK (0x20U) +#define FLEXIO_TIMCTL_ONETIM_SHIFT (5U) +/*! ONETIM - Timer One Time Operation + * 0b0..Generate the timer enable event as normal + * 0b1..Block the timer enable event unless the timer status flag is clear + */ +#define FLEXIO_TIMCTL_ONETIM(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_ONETIM_SHIFT)) & FLEXIO_TIMCTL_ONETIM_MASK) + +#define FLEXIO_TIMCTL_PININS_MASK (0x40U) +#define FLEXIO_TIMCTL_PININS_SHIFT (6U) +/*! PININS - Timer Pin Input Select + * 0b0..PINSEL selects timer pin input and output + * 0b1..PINSEL + 1 selects the timer pin input; timer pin output remains selected by PINSEL + */ +#define FLEXIO_TIMCTL_PININS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_PININS_SHIFT)) & FLEXIO_TIMCTL_PININS_MASK) + +#define FLEXIO_TIMCTL_PINPOL_MASK (0x80U) +#define FLEXIO_TIMCTL_PINPOL_SHIFT (7U) +/*! PINPOL - Timer Pin Polarity + * 0b0..Active high + * 0b1..Active low + */ +#define FLEXIO_TIMCTL_PINPOL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_PINPOL_SHIFT)) & FLEXIO_TIMCTL_PINPOL_MASK) + +#define FLEXIO_TIMCTL_PINSEL_MASK (0x1F00U) +#define FLEXIO_TIMCTL_PINSEL_SHIFT (8U) +/*! PINSEL - Timer Pin Select */ +#define FLEXIO_TIMCTL_PINSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_PINSEL_SHIFT)) & FLEXIO_TIMCTL_PINSEL_MASK) + +#define FLEXIO_TIMCTL_PINCFG_MASK (0x30000U) +#define FLEXIO_TIMCTL_PINCFG_SHIFT (16U) +/*! PINCFG - Timer Pin Configuration + * 0b00..Timer pin output disabled + * 0b01..Timer pin open-drain or bidirectional output enable + * 0b10..Timer pin bidirectional output data + * 0b11..Timer pin output + */ +#define FLEXIO_TIMCTL_PINCFG(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_PINCFG_SHIFT)) & FLEXIO_TIMCTL_PINCFG_MASK) + +#define FLEXIO_TIMCTL_TRGSRC_MASK (0x400000U) +#define FLEXIO_TIMCTL_TRGSRC_SHIFT (22U) +/*! TRGSRC - Trigger Source + * 0b0..External + * 0b1..Internal + */ +#define FLEXIO_TIMCTL_TRGSRC(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TRGSRC_SHIFT)) & FLEXIO_TIMCTL_TRGSRC_MASK) + +#define FLEXIO_TIMCTL_TRGPOL_MASK (0x800000U) +#define FLEXIO_TIMCTL_TRGPOL_SHIFT (23U) +/*! TRGPOL - Trigger Polarity + * 0b0..Active high + * 0b1..Active low + */ +#define FLEXIO_TIMCTL_TRGPOL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TRGPOL_SHIFT)) & FLEXIO_TIMCTL_TRGPOL_MASK) + +#define FLEXIO_TIMCTL_TRGSEL_MASK (0x3F000000U) +#define FLEXIO_TIMCTL_TRGSEL_SHIFT (24U) +/*! TRGSEL - Trigger Select */ +#define FLEXIO_TIMCTL_TRGSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TRGSEL_SHIFT)) & FLEXIO_TIMCTL_TRGSEL_MASK) +/*! @} */ + +/* The count of FLEXIO_TIMCTL */ +#define FLEXIO_TIMCTL_COUNT (8U) + +/*! @name TIMCFG - Timer Configuration */ +/*! @{ */ + +#define FLEXIO_TIMCFG_TSTART_MASK (0x2U) +#define FLEXIO_TIMCFG_TSTART_SHIFT (1U) +/*! TSTART - Timer Start + * 0b0..Disabled + * 0b1..Enabled + */ +#define FLEXIO_TIMCFG_TSTART(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TSTART_SHIFT)) & FLEXIO_TIMCFG_TSTART_MASK) + +#define FLEXIO_TIMCFG_TSTOP_MASK (0x30U) +#define FLEXIO_TIMCFG_TSTOP_SHIFT (4U) +/*! TSTOP - Timer Stop + * 0b00..Disabled + * 0b01..Enabled on timer compare + * 0b10..Enabled on timer disable + * 0b11..Enabled on timer compare and timer disable + */ +#define FLEXIO_TIMCFG_TSTOP(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TSTOP_SHIFT)) & FLEXIO_TIMCFG_TSTOP_MASK) + +#define FLEXIO_TIMCFG_TIMENA_MASK (0x700U) +#define FLEXIO_TIMCFG_TIMENA_SHIFT (8U) +/*! TIMENA - Timer Enable + * 0b000..Timer always enabled + * 0b001..Timer enabled on timer n-1 enable + * 0b010..Timer enabled on trigger high + * 0b011..Timer enabled on trigger high and pin high + * 0b100..Timer enabled on pin rising edge + * 0b101..Timer enabled on pin rising edge and trigger high + * 0b110..Timer enabled on trigger rising edge + * 0b111..Timer enabled on trigger rising or falling edge + */ +#define FLEXIO_TIMCFG_TIMENA(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMENA_SHIFT)) & FLEXIO_TIMCFG_TIMENA_MASK) + +#define FLEXIO_TIMCFG_TIMDIS_MASK (0x7000U) +#define FLEXIO_TIMCFG_TIMDIS_SHIFT (12U) +/*! TIMDIS - Timer Disable + * 0b000..Timer never disabled + * 0b001..Timer disabled on timer n-1 disable + * 0b010..Timer disabled on timer compare (upper 8 bits match and decrement) + * 0b011..Timer disabled on timer compare (upper 8 bits match and decrement) and trigger low + * 0b100..Timer disabled on pin rising or falling edge + * 0b101..Timer disabled on pin rising or falling edge provided trigger is high + * 0b110..Timer disabled on trigger falling edge + * 0b111..Reserved + */ +#define FLEXIO_TIMCFG_TIMDIS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMDIS_SHIFT)) & FLEXIO_TIMCFG_TIMDIS_MASK) + +#define FLEXIO_TIMCFG_TIMRST_MASK (0x70000U) +#define FLEXIO_TIMCFG_TIMRST_SHIFT (16U) +/*! TIMRST - Timer Reset + * 0b000..Never reset timer + * 0b001..Timer reset on timer output high. + * 0b010..Timer reset on timer pin equal to timer output + * 0b011..Timer reset on timer trigger equal to timer output + * 0b100..Timer reset on timer pin rising edge + * 0b101..Reserved + * 0b110..Timer reset on trigger rising edge + * 0b111..Timer reset on trigger rising or falling edge + */ +#define FLEXIO_TIMCFG_TIMRST(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMRST_SHIFT)) & FLEXIO_TIMCFG_TIMRST_MASK) + +#define FLEXIO_TIMCFG_TIMDEC_MASK (0x700000U) +#define FLEXIO_TIMCFG_TIMDEC_SHIFT (20U) +/*! TIMDEC - Timer Decrement + * 0b000..Decrement counter on FLEXIO clock; shift clock equals timer output + * 0b001..Decrement counter on trigger input (both edges); shift clock equals timer output + * 0b010..Decrement counter on pin input (both edges); shift clock equals pin input + * 0b011..Decrement counter on trigger input (both edges); shift clock equals trigger input + * 0b100..Decrement counter on FLEXIO clock divided by 16; shift clock equals timer output + * 0b101..Decrement counter on FLEXIO clock divided by 256; shift clock equals timer output + * 0b110..Decrement counter on pin input (rising edge); shift clock equals pin input + * 0b111..Decrement counter on trigger input (rising edge); shift clock equals trigger input + */ +#define FLEXIO_TIMCFG_TIMDEC(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMDEC_SHIFT)) & FLEXIO_TIMCFG_TIMDEC_MASK) + +#define FLEXIO_TIMCFG_TIMOUT_MASK (0x3000000U) +#define FLEXIO_TIMCFG_TIMOUT_SHIFT (24U) +/*! TIMOUT - Timer Output + * 0b00..Logic one when enabled; not affected by timer reset + * 0b01..Logic zero when enabled; not affected by timer reset + * 0b10..Logic one when enabled and on timer reset + * 0b11..Logic zero when enabled and on timer reset + */ +#define FLEXIO_TIMCFG_TIMOUT(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMOUT_SHIFT)) & FLEXIO_TIMCFG_TIMOUT_MASK) +/*! @} */ + +/* The count of FLEXIO_TIMCFG */ +#define FLEXIO_TIMCFG_COUNT (8U) + +/*! @name TIMCMP - Timer Compare */ +/*! @{ */ + +#define FLEXIO_TIMCMP_CMP_MASK (0xFFFFU) +#define FLEXIO_TIMCMP_CMP_SHIFT (0U) +/*! CMP - Timer Compare Value */ +#define FLEXIO_TIMCMP_CMP(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCMP_CMP_SHIFT)) & FLEXIO_TIMCMP_CMP_MASK) +/*! @} */ + +/* The count of FLEXIO_TIMCMP */ +#define FLEXIO_TIMCMP_COUNT (8U) + +/*! @name SHIFTBUFNBS - Shifter Buffer Nibble Byte Swapped */ +/*! @{ */ + +#define FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_MASK (0xFFFFFFFFU) +#define FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_SHIFT (0U) +/*! SHIFTBUFNBS - Shift Buffer */ +#define FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_SHIFT)) & FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_MASK) +/*! @} */ + +/* The count of FLEXIO_SHIFTBUFNBS */ +#define FLEXIO_SHIFTBUFNBS_COUNT (8U) + +/*! @name SHIFTBUFHWS - Shifter Buffer Halfword Swapped */ +/*! @{ */ + +#define FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_MASK (0xFFFFFFFFU) +#define FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_SHIFT (0U) +/*! SHIFTBUFHWS - Shift Buffer */ +#define FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_SHIFT)) & FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_MASK) +/*! @} */ + +/* The count of FLEXIO_SHIFTBUFHWS */ +#define FLEXIO_SHIFTBUFHWS_COUNT (8U) + +/*! @name SHIFTBUFNIS - Shifter Buffer Nibble Swapped */ +/*! @{ */ + +#define FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_MASK (0xFFFFFFFFU) +#define FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_SHIFT (0U) +/*! SHIFTBUFNIS - Shift Buffer */ +#define FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_SHIFT)) & FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_MASK) +/*! @} */ + +/* The count of FLEXIO_SHIFTBUFNIS */ +#define FLEXIO_SHIFTBUFNIS_COUNT (8U) + +/*! @name SHIFTBUFOES - Shifter Buffer Odd Even Swapped */ +/*! @{ */ + +#define FLEXIO_SHIFTBUFOES_SHIFTBUFOES_MASK (0xFFFFFFFFU) +#define FLEXIO_SHIFTBUFOES_SHIFTBUFOES_SHIFT (0U) +/*! SHIFTBUFOES - Shift Buffer */ +#define FLEXIO_SHIFTBUFOES_SHIFTBUFOES(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFOES_SHIFTBUFOES_SHIFT)) & FLEXIO_SHIFTBUFOES_SHIFTBUFOES_MASK) +/*! @} */ + +/* The count of FLEXIO_SHIFTBUFOES */ +#define FLEXIO_SHIFTBUFOES_COUNT (8U) + +/*! @name SHIFTBUFEOS - Shifter Buffer Even Odd Swapped */ +/*! @{ */ + +#define FLEXIO_SHIFTBUFEOS_SHIFTBUFEOS_MASK (0xFFFFFFFFU) +#define FLEXIO_SHIFTBUFEOS_SHIFTBUFEOS_SHIFT (0U) +/*! SHIFTBUFEOS - Shift Buffer */ +#define FLEXIO_SHIFTBUFEOS_SHIFTBUFEOS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFEOS_SHIFTBUFEOS_SHIFT)) & FLEXIO_SHIFTBUFEOS_SHIFTBUFEOS_MASK) +/*! @} */ + +/* The count of FLEXIO_SHIFTBUFEOS */ +#define FLEXIO_SHIFTBUFEOS_COUNT (8U) + +/*! @name SHIFTBUFHBS - Shifter Buffer Halfword Byte Swapped */ +/*! @{ */ + +#define FLEXIO_SHIFTBUFHBS_SHIFTBUFHBS_MASK (0xFFFFFFFFU) +#define FLEXIO_SHIFTBUFHBS_SHIFTBUFHBS_SHIFT (0U) +/*! SHIFTBUFHBS - Shift Buffer */ +#define FLEXIO_SHIFTBUFHBS_SHIFTBUFHBS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFHBS_SHIFTBUFHBS_SHIFT)) & FLEXIO_SHIFTBUFHBS_SHIFTBUFHBS_MASK) +/*! @} */ + +/* The count of FLEXIO_SHIFTBUFHBS */ +#define FLEXIO_SHIFTBUFHBS_COUNT (8U) + + +/*! + * @} + */ /* end of group FLEXIO_Register_Masks */ + + +/* FLEXIO - Peripheral instance base addresses */ +/** Peripheral FLEXIO1 base address */ +#define FLEXIO1_BASE (0x425C0000u) +/** Peripheral FLEXIO1 base pointer */ +#define FLEXIO1 ((FLEXIO_Type *)FLEXIO1_BASE) +/** Peripheral FLEXIO2 base address */ +#define FLEXIO2_BASE (0x425D0000u) +/** Peripheral FLEXIO2 base pointer */ +#define FLEXIO2 ((FLEXIO_Type *)FLEXIO2_BASE) +/** Array initializer of FLEXIO peripheral base addresses */ +#define FLEXIO_BASE_ADDRS { FLEXIO1_BASE, FLEXIO2_BASE } +/** Array initializer of FLEXIO peripheral base pointers */ +#define FLEXIO_BASE_PTRS { FLEXIO1, FLEXIO2 } + +/*! + * @} + */ /* end of group FLEXIO_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- FLEXSPI Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup FLEXSPI_Peripheral_Access_Layer FLEXSPI Peripheral Access Layer + * @{ + */ + +/** FLEXSPI - Register Layout Typedef */ +typedef struct { + __IO uint32_t MCR0; /**< Module Control 0, offset: 0x0 */ + __IO uint32_t MCR1; /**< Module Control 1, offset: 0x4 */ + __IO uint32_t MCR2; /**< Module Control 2, offset: 0x8 */ + __IO uint32_t AHBCR; /**< AHB Bus Control, offset: 0xC */ + __IO uint32_t INTEN; /**< Interrupt Enable, offset: 0x10 */ + __IO uint32_t INTR; /**< Interrupt, offset: 0x14 */ + __IO uint32_t LUTKEY; /**< LUT Key, offset: 0x18 */ + __IO uint32_t LUTCR; /**< LUT Control, offset: 0x1C */ + __IO uint32_t AHBRXBUFCR0[8]; /**< AHB Receive Buffer 0 Control 0..AHB Receive Buffer 7 Control 0, array offset: 0x20, array step: 0x4 */ + uint8_t RESERVED_0[32]; + __IO uint32_t FLSHCR0[4]; /**< Flash Control 0, array offset: 0x60, array step: 0x4 */ + __IO uint32_t FLSHCR1[4]; /**< Flash Control 1, array offset: 0x70, array step: 0x4 */ + __IO uint32_t FLSHCR2[4]; /**< Flash Control 2, array offset: 0x80, array step: 0x4 */ + uint8_t RESERVED_1[4]; + __IO uint32_t FLSHCR4; /**< Flash Control 4, offset: 0x94 */ + uint8_t RESERVED_2[8]; + __IO uint32_t IPCR0; /**< IP Control 0, offset: 0xA0 */ + __IO uint32_t IPCR1; /**< IP Control 1, offset: 0xA4 */ + __IO uint32_t IPCR2; /**< IP Control 2, offset: 0xA8 */ + uint8_t RESERVED_3[4]; + __IO uint32_t IPCMD; /**< IP Command, offset: 0xB0 */ + __IO uint32_t DLPR; /**< Data Learning Pattern, offset: 0xB4 */ + __IO uint32_t IPRXFCR; /**< IP Receive FIFO Control, offset: 0xB8 */ + __IO uint32_t IPTXFCR; /**< IP Transmit FIFO Control, offset: 0xBC */ + __IO uint32_t DLLCR[2]; /**< DLL Control 0, array offset: 0xC0, array step: 0x4 */ + uint8_t RESERVED_4[24]; + __I uint32_t STS0; /**< Status 0, offset: 0xE0 */ + __I uint32_t STS1; /**< Status 1, offset: 0xE4 */ + __I uint32_t STS2; /**< Status 2, offset: 0xE8 */ + __I uint32_t AHBSPNDSTS; /**< AHB Suspend Status, offset: 0xEC */ + __I uint32_t IPRXFSTS; /**< IP Receive FIFO Status, offset: 0xF0 */ + __I uint32_t IPTXFSTS; /**< IP Transmit FIFO Status, offset: 0xF4 */ + uint8_t RESERVED_5[8]; + __I uint32_t RFDR[32]; /**< IP Receive FIFO Data 0..IP Receive FIFO Data 31, array offset: 0x100, array step: 0x4 */ + __O uint32_t TFDR[32]; /**< IP TX FIFO Data 0..IP TX FIFO Data 31, array offset: 0x180, array step: 0x4 */ + __IO uint32_t LUT[128]; /**< Lookup Table 0..Lookup Table 127, array offset: 0x200, array step: 0x4 */ + uint8_t RESERVED_6[64]; + __IO uint32_t AHBBUFREGIONSTART0; /**< Receive Buffer Start Address of Region 0, offset: 0x440 */ + __IO uint32_t AHBBUFREGIONEND0; /**< Receive Buffer Region 0 End Address, offset: 0x444 */ + __IO uint32_t AHBBUFREGIONSTART1; /**< Receive Buffer Start Address of Region 1, offset: 0x448 */ + __IO uint32_t AHBBUFREGIONEND1; /**< Receive Buffer Region 1 End Address, offset: 0x44C */ + __IO uint32_t AHBBUFREGIONSTART2; /**< Receive Buffer Start Address of Region 2, offset: 0x450 */ + __IO uint32_t AHBBUFREGIONEND2; /**< Receive Buffer Region 2 End Address, offset: 0x454 */ + __IO uint32_t AHBBUFREGIONSTART3; /**< Receive Buffer Start Address of Region 3, offset: 0x458 */ + __IO uint32_t AHBBUFREGIONEND3; /**< Receive Buffer Region 3 End Address, offset: 0x45C */ +} FLEXSPI_Type; + +/* ---------------------------------------------------------------------------- + -- FLEXSPI Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup FLEXSPI_Register_Masks FLEXSPI Register Masks + * @{ + */ + +/*! @name MCR0 - Module Control 0 */ +/*! @{ */ + +#define FLEXSPI_MCR0_SWRESET_MASK (0x1U) +#define FLEXSPI_MCR0_SWRESET_SHIFT (0U) +/*! SWRESET - Software Reset + * 0b0..No impact + * 0b1..Software reset + */ +#define FLEXSPI_MCR0_SWRESET(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_SWRESET_SHIFT)) & FLEXSPI_MCR0_SWRESET_MASK) + +#define FLEXSPI_MCR0_MDIS_MASK (0x2U) +#define FLEXSPI_MCR0_MDIS_SHIFT (1U) +/*! MDIS - Module Disable + * 0b0..No impact + * 0b1..Module disable + */ +#define FLEXSPI_MCR0_MDIS(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_MDIS_SHIFT)) & FLEXSPI_MCR0_MDIS_MASK) + +#define FLEXSPI_MCR0_RXCLKSRC_MASK (0x30U) +#define FLEXSPI_MCR0_RXCLKSRC_SHIFT (4U) +/*! RXCLKSRC - Sample Clock Source for Flash Reading + * 0b00..Dummy Read strobe that FlexSPI generates, looped back internally + * 0b01..Dummy Read strobe that FlexSPI generates, looped back from DQS pad + * 0b10..SCLK output clock and looped back from SCLK pad + * 0b11..Flash-memory-provided read strobe and input from DQS pad + */ +#define FLEXSPI_MCR0_RXCLKSRC(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_RXCLKSRC_SHIFT)) & FLEXSPI_MCR0_RXCLKSRC_MASK) + +#define FLEXSPI_MCR0_ARDFEN_MASK (0x40U) +#define FLEXSPI_MCR0_ARDFEN_SHIFT (6U) +/*! ARDFEN - AHB Read Access to IP Receive FIFO Enable + * 0b0..AHB read access disabled. IP bus reads IP receive FIFO. AHB Bus read access to IP receive FIFO memory space produces bus error. + * 0b1..AHB read access enabled. AHB bus reads IP receive FIFO. IP Bus read access to IP receive FIFO memory + * space returns data zero and causes no bus error. + */ +#define FLEXSPI_MCR0_ARDFEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_ARDFEN_SHIFT)) & FLEXSPI_MCR0_ARDFEN_MASK) + +#define FLEXSPI_MCR0_ATDFEN_MASK (0x80U) +#define FLEXSPI_MCR0_ATDFEN_SHIFT (7U) +/*! ATDFEN - AHB Write Access to IP Transmit FIFO Enable + * 0b0..AHB write access disabled. IP bus writes to IP transmit FIFO. AHB bus write access to IP transmit FIFO memory space produces bus error. + * 0b1..AHB write access enabled. AHB bus writes to IP transmit FIFO. IP Bus write access to IP transmit FIFO + * memory space is ignored and causes no bus error. + */ +#define FLEXSPI_MCR0_ATDFEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_ATDFEN_SHIFT)) & FLEXSPI_MCR0_ATDFEN_MASK) + +#define FLEXSPI_MCR0_SERCLKDIV_MASK (0x700U) +#define FLEXSPI_MCR0_SERCLKDIV_SHIFT (8U) +/*! SERCLKDIV - Serial Root Clock Divider + * 0b000..Divided by 1 + * 0b001..Divided by 2 + * 0b010..Divided by 3 + * 0b011..Divided by 4 + * 0b100..Divided by 5 + * 0b101..Divided by 6 + * 0b110..Divided by 7 + * 0b111..Divided by 8 + */ +#define FLEXSPI_MCR0_SERCLKDIV(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_SERCLKDIV_SHIFT)) & FLEXSPI_MCR0_SERCLKDIV_MASK) + +#define FLEXSPI_MCR0_HSEN_MASK (0x800U) +#define FLEXSPI_MCR0_HSEN_SHIFT (11U) +/*! HSEN - Half Speed Serial Flash Memory Access Enable + * 0b0..Disable + * 0b1..Enable + */ +#define FLEXSPI_MCR0_HSEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_HSEN_SHIFT)) & FLEXSPI_MCR0_HSEN_MASK) + +#define FLEXSPI_MCR0_DOZEEN_MASK (0x1000U) +#define FLEXSPI_MCR0_DOZEEN_SHIFT (12U) +/*! DOZEEN - Doze Mode Enable + * 0b0..Disable + * 0b1..Enable + */ +#define FLEXSPI_MCR0_DOZEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_DOZEEN_SHIFT)) & FLEXSPI_MCR0_DOZEEN_MASK) + +#define FLEXSPI_MCR0_SCKFREERUNEN_MASK (0x4000U) +#define FLEXSPI_MCR0_SCKFREERUNEN_SHIFT (14U) +/*! SCKFREERUNEN - SCLK Free-running Enable + * 0b0..Disable + * 0b1..Enable + */ +#define FLEXSPI_MCR0_SCKFREERUNEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_SCKFREERUNEN_SHIFT)) & FLEXSPI_MCR0_SCKFREERUNEN_MASK) + +#define FLEXSPI_MCR0_LEARNEN_MASK (0x8000U) +#define FLEXSPI_MCR0_LEARNEN_SHIFT (15U) +/*! LEARNEN - Data Learning Enable + * 0b0..Disable + * 0b1..Enable + */ +#define FLEXSPI_MCR0_LEARNEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_LEARNEN_SHIFT)) & FLEXSPI_MCR0_LEARNEN_MASK) + +#define FLEXSPI_MCR0_IPGRANTWAIT_MASK (0xFF0000U) +#define FLEXSPI_MCR0_IPGRANTWAIT_SHIFT (16U) +/*! IPGRANTWAIT - Timeout Wait Cycle for IP Command Grant */ +#define FLEXSPI_MCR0_IPGRANTWAIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_IPGRANTWAIT_SHIFT)) & FLEXSPI_MCR0_IPGRANTWAIT_MASK) + +#define FLEXSPI_MCR0_AHBGRANTWAIT_MASK (0xFF000000U) +#define FLEXSPI_MCR0_AHBGRANTWAIT_SHIFT (24U) +/*! AHBGRANTWAIT - Timeouts Wait Cycle for AHB command Grant */ +#define FLEXSPI_MCR0_AHBGRANTWAIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_AHBGRANTWAIT_SHIFT)) & FLEXSPI_MCR0_AHBGRANTWAIT_MASK) +/*! @} */ + +/*! @name MCR1 - Module Control 1 */ +/*! @{ */ + +#define FLEXSPI_MCR1_AHBBUSWAIT_MASK (0xFFFFU) +#define FLEXSPI_MCR1_AHBBUSWAIT_SHIFT (0U) +/*! AHBBUSWAIT - AHB Bus Wait */ +#define FLEXSPI_MCR1_AHBBUSWAIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR1_AHBBUSWAIT_SHIFT)) & FLEXSPI_MCR1_AHBBUSWAIT_MASK) + +#define FLEXSPI_MCR1_SEQWAIT_MASK (0xFFFF0000U) +#define FLEXSPI_MCR1_SEQWAIT_SHIFT (16U) +/*! SEQWAIT - Command Sequence Wait */ +#define FLEXSPI_MCR1_SEQWAIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR1_SEQWAIT_SHIFT)) & FLEXSPI_MCR1_SEQWAIT_MASK) +/*! @} */ + +/*! @name MCR2 - Module Control 2 */ +/*! @{ */ + +#define FLEXSPI_MCR2_CLRAHBBUFOPT_MASK (0x800U) +#define FLEXSPI_MCR2_CLRAHBBUFOPT_SHIFT (11U) +/*! CLRAHBBUFOPT - Clear AHB Buffer + * 0b0..Not cleared automatically + * 0b1..Cleared automatically + */ +#define FLEXSPI_MCR2_CLRAHBBUFOPT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_CLRAHBBUFOPT_SHIFT)) & FLEXSPI_MCR2_CLRAHBBUFOPT_MASK) + +#define FLEXSPI_MCR2_CLRLEARNPHASE_MASK (0x4000U) +#define FLEXSPI_MCR2_CLRLEARNPHASE_SHIFT (14U) +/*! CLRLEARNPHASE - Clear Learn Phase Selection + * 0b0..No impact + * 0b1..Reset sample clock phase selection to 0 + */ +#define FLEXSPI_MCR2_CLRLEARNPHASE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_CLRLEARNPHASE_SHIFT)) & FLEXSPI_MCR2_CLRLEARNPHASE_MASK) + +#define FLEXSPI_MCR2_SAMEDEVICEEN_MASK (0x8000U) +#define FLEXSPI_MCR2_SAMEDEVICEEN_SHIFT (15U) +/*! SAMEDEVICEEN - Same Device Enable + * 0b0..In Individual mode, FLSHA1CRx and FLSHA2CRx, FLSHB1CRx and FLSHB2CRx settings are applied to Flash A1, A2, B1, B2 separately. + * 0b1..FLSHA1CR0, FLSHA1CR1, and FLSHA1CR2 register settings are applied to Flash A1, A2, B1, B2. FLSHA2CRx, + * FLSHB1CRx, and FLSHB2CRx settings are ignored. + */ +#define FLEXSPI_MCR2_SAMEDEVICEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_SAMEDEVICEEN_SHIFT)) & FLEXSPI_MCR2_SAMEDEVICEEN_MASK) + +#define FLEXSPI_MCR2_RESUMEWAIT_MASK (0xFF000000U) +#define FLEXSPI_MCR2_RESUMEWAIT_SHIFT (24U) +/*! RESUMEWAIT - Resume Wait Duration */ +#define FLEXSPI_MCR2_RESUMEWAIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_RESUMEWAIT_SHIFT)) & FLEXSPI_MCR2_RESUMEWAIT_MASK) +/*! @} */ + +/*! @name AHBCR - AHB Bus Control */ +/*! @{ */ + +#define FLEXSPI_AHBCR_CLRAHBTXBUF_MASK (0x4U) +#define FLEXSPI_AHBCR_CLRAHBTXBUF_SHIFT (2U) +/*! CLRAHBTXBUF - Clear AHB Transmit Buffer + * 0b0..No impact. + * 0b1..Enable clear operation. + */ +#define FLEXSPI_AHBCR_CLRAHBTXBUF(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_CLRAHBTXBUF_SHIFT)) & FLEXSPI_AHBCR_CLRAHBTXBUF_MASK) + +#define FLEXSPI_AHBCR_CACHABLEEN_MASK (0x8U) +#define FLEXSPI_AHBCR_CACHABLEEN_SHIFT (3U) +/*! CACHABLEEN - Cacheable Read Access Enable + * 0b0..Disabled. When an AHB bus cacheable read access occurs, FlexSPI does not check whether it hit the AHB transmit buffer. + * 0b1..Enabled. When an AHB bus cacheable read access occurs, FlexSPI first checks whether the access hit the AHB transmit buffer. + */ +#define FLEXSPI_AHBCR_CACHABLEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_CACHABLEEN_SHIFT)) & FLEXSPI_AHBCR_CACHABLEEN_MASK) + +#define FLEXSPI_AHBCR_BUFFERABLEEN_MASK (0x10U) +#define FLEXSPI_AHBCR_BUFFERABLEEN_SHIFT (4U) +/*! BUFFERABLEEN - Bufferable Write Access Enable + * 0b0..Disabled. For all AHB write accesses (bufferable or nonbufferable), FlexSPI returns AHB Bus Ready after + * transmitting all data and finishing command. + * 0b1..Enabled. For AHB bufferable write access, FlexSPI returns AHB Bus Ready when the arbitrator grants the + * AHB command. FlexSPI does not wait for the AHB command to finish. + */ +#define FLEXSPI_AHBCR_BUFFERABLEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_BUFFERABLEEN_SHIFT)) & FLEXSPI_AHBCR_BUFFERABLEEN_MASK) + +#define FLEXSPI_AHBCR_PREFETCHEN_MASK (0x20U) +#define FLEXSPI_AHBCR_PREFETCHEN_SHIFT (5U) +/*! PREFETCHEN - AHB Read Prefetch Enable + * 0b0..Disable + * 0b1..Enable + */ +#define FLEXSPI_AHBCR_PREFETCHEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_PREFETCHEN_SHIFT)) & FLEXSPI_AHBCR_PREFETCHEN_MASK) + +#define FLEXSPI_AHBCR_READADDROPT_MASK (0x40U) +#define FLEXSPI_AHBCR_READADDROPT_SHIFT (6U) +/*! READADDROPT - AHB Read Address Option + * 0b0..AHB read burst start address alignment is limited when flash memory is accessed in flash is word-addressable. + * 0b1..AHB read burst start address alignment is not limited. FlexSPI fetches more data than the AHB burst requires for address alignment. + */ +#define FLEXSPI_AHBCR_READADDROPT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_READADDROPT_SHIFT)) & FLEXSPI_AHBCR_READADDROPT_MASK) + +#define FLEXSPI_AHBCR_RESUMEDISABLE_MASK (0x80U) +#define FLEXSPI_AHBCR_RESUMEDISABLE_SHIFT (7U) +/*! RESUMEDISABLE - AHB Read Resume Disable + * 0b0..Suspended AHB read prefetch resumes when AHB is IDLE. + * 0b1..Suspended AHB read prefetch does not resume once aborted. + */ +#define FLEXSPI_AHBCR_RESUMEDISABLE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_RESUMEDISABLE_SHIFT)) & FLEXSPI_AHBCR_RESUMEDISABLE_MASK) + +#define FLEXSPI_AHBCR_READSZALIGN_MASK (0x400U) +#define FLEXSPI_AHBCR_READSZALIGN_SHIFT (10U) +/*! READSZALIGN - AHB Read Size Alignment + * 0b0..Register settings such as PREFETCH_EN and OTFAD_EN determine AHB read size. + * 0b1..AHB read size to up size to 8 bytes aligned, no prefetching + */ +#define FLEXSPI_AHBCR_READSZALIGN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_READSZALIGN_SHIFT)) & FLEXSPI_AHBCR_READSZALIGN_MASK) + +#define FLEXSPI_AHBCR_ALIGNMENT_MASK (0x300000U) +#define FLEXSPI_AHBCR_ALIGNMENT_SHIFT (20U) +/*! ALIGNMENT - AHB Boundary Alignment + * 0b00..No limit + * 0b01..1 KB + * 0b10..512 bytes + * 0b11..256 bytes + */ +#define FLEXSPI_AHBCR_ALIGNMENT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_ALIGNMENT_SHIFT)) & FLEXSPI_AHBCR_ALIGNMENT_MASK) + +#define FLEXSPI_AHBCR_AFLASHBASE_MASK (0xF8000000U) +#define FLEXSPI_AHBCR_AFLASHBASE_SHIFT (27U) +/*! AFLASHBASE - AHB Memory-Mapped Flash Base Address */ +#define FLEXSPI_AHBCR_AFLASHBASE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_AFLASHBASE_SHIFT)) & FLEXSPI_AHBCR_AFLASHBASE_MASK) +/*! @} */ + +/*! @name INTEN - Interrupt Enable */ +/*! @{ */ + +#define FLEXSPI_INTEN_IPCMDDONEEN_MASK (0x1U) +#define FLEXSPI_INTEN_IPCMDDONEEN_SHIFT (0U) +/*! IPCMDDONEEN - IP-Triggered Command Sequences Execution Finished Interrupt Enable + * 0b0..Disable interrupt or no impact + * 0b1..Enable interrupt + */ +#define FLEXSPI_INTEN_IPCMDDONEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPCMDDONEEN_SHIFT)) & FLEXSPI_INTEN_IPCMDDONEEN_MASK) + +#define FLEXSPI_INTEN_IPCMDGEEN_MASK (0x2U) +#define FLEXSPI_INTEN_IPCMDGEEN_SHIFT (1U) +/*! IPCMDGEEN - IP-Triggered Command Sequences Grant Timeout Interrupt Enable + * 0b0..Disable interrupt or no impact + * 0b1..Enable interrupt + */ +#define FLEXSPI_INTEN_IPCMDGEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPCMDGEEN_SHIFT)) & FLEXSPI_INTEN_IPCMDGEEN_MASK) + +#define FLEXSPI_INTEN_AHBCMDGEEN_MASK (0x4U) +#define FLEXSPI_INTEN_AHBCMDGEEN_SHIFT (2U) +/*! AHBCMDGEEN - AHB-Triggered Command Sequences Grant Timeout Interrupt Enable. + * 0b0..Disable interrupt or no impact + * 0b1..Enable interrupt + */ +#define FLEXSPI_INTEN_AHBCMDGEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_AHBCMDGEEN_SHIFT)) & FLEXSPI_INTEN_AHBCMDGEEN_MASK) + +#define FLEXSPI_INTEN_IPCMDERREN_MASK (0x8U) +#define FLEXSPI_INTEN_IPCMDERREN_SHIFT (3U) +/*! IPCMDERREN - IP-Triggered Command Sequences Error Detected Interrupt Enable + * 0b0..Disable interrupt or no impact + * 0b1..Enable interrupt + */ +#define FLEXSPI_INTEN_IPCMDERREN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPCMDERREN_SHIFT)) & FLEXSPI_INTEN_IPCMDERREN_MASK) + +#define FLEXSPI_INTEN_AHBCMDERREN_MASK (0x10U) +#define FLEXSPI_INTEN_AHBCMDERREN_SHIFT (4U) +/*! AHBCMDERREN - AHB-Triggered Command Sequences Error Detected Interrupt Enable + * 0b0..Disable interrupt or no impact + * 0b1..Enable interrupt + */ +#define FLEXSPI_INTEN_AHBCMDERREN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_AHBCMDERREN_SHIFT)) & FLEXSPI_INTEN_AHBCMDERREN_MASK) + +#define FLEXSPI_INTEN_IPRXWAEN_MASK (0x20U) +#define FLEXSPI_INTEN_IPRXWAEN_SHIFT (5U) +/*! IPRXWAEN - IP Receive FIFO Watermark Available Interrupt Enable + * 0b0..Disable interrupt or no impact + * 0b1..Enable interrupt + */ +#define FLEXSPI_INTEN_IPRXWAEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPRXWAEN_SHIFT)) & FLEXSPI_INTEN_IPRXWAEN_MASK) + +#define FLEXSPI_INTEN_IPTXWEEN_MASK (0x40U) +#define FLEXSPI_INTEN_IPTXWEEN_SHIFT (6U) +/*! IPTXWEEN - IP Transmit FIFO Watermark Empty Interrupt Enable + * 0b0..Disable interrupt or no impact + * 0b1..Enable interrupt + */ +#define FLEXSPI_INTEN_IPTXWEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPTXWEEN_SHIFT)) & FLEXSPI_INTEN_IPTXWEEN_MASK) + +#define FLEXSPI_INTEN_DATALEARNFAILEN_MASK (0x80U) +#define FLEXSPI_INTEN_DATALEARNFAILEN_SHIFT (7U) +/*! DATALEARNFAILEN - Data Learning Failed Interrupt Enable + * 0b0..Disable interrupt or no impact + * 0b1..Enable interrupt + */ +#define FLEXSPI_INTEN_DATALEARNFAILEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_DATALEARNFAILEN_SHIFT)) & FLEXSPI_INTEN_DATALEARNFAILEN_MASK) + +#define FLEXSPI_INTEN_SCKSTOPBYRDEN_MASK (0x100U) +#define FLEXSPI_INTEN_SCKSTOPBYRDEN_SHIFT (8U) +/*! SCKSTOPBYRDEN - SCLK Stopped By Read Interrupt Enable + * 0b0..Disable interrupt or no impact + * 0b1..Enable interrupt + */ +#define FLEXSPI_INTEN_SCKSTOPBYRDEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_SCKSTOPBYRDEN_SHIFT)) & FLEXSPI_INTEN_SCKSTOPBYRDEN_MASK) + +#define FLEXSPI_INTEN_SCKSTOPBYWREN_MASK (0x200U) +#define FLEXSPI_INTEN_SCKSTOPBYWREN_SHIFT (9U) +/*! SCKSTOPBYWREN - SCLK Stopped By Write Interrupt Enable + * 0b0..Disable interrupt or no impact + * 0b1..Enable interrupt + */ +#define FLEXSPI_INTEN_SCKSTOPBYWREN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_SCKSTOPBYWREN_SHIFT)) & FLEXSPI_INTEN_SCKSTOPBYWREN_MASK) + +#define FLEXSPI_INTEN_AHBBUSERROREN_MASK (0x400U) +#define FLEXSPI_INTEN_AHBBUSERROREN_SHIFT (10U) +/*! AHBBUSERROREN - AHB Bus Error Interrupt Enable + * 0b0..Disable interrupt or no impact + * 0b1..Enable interrupt + */ +#define FLEXSPI_INTEN_AHBBUSERROREN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_AHBBUSERROREN_SHIFT)) & FLEXSPI_INTEN_AHBBUSERROREN_MASK) + +#define FLEXSPI_INTEN_SEQTIMEOUTEN_MASK (0x800U) +#define FLEXSPI_INTEN_SEQTIMEOUTEN_SHIFT (11U) +/*! SEQTIMEOUTEN - Sequence execution Timeout Interrupt Enable + * 0b0..Disable interrupt or no impact + * 0b1..Enable interrupt + */ +#define FLEXSPI_INTEN_SEQTIMEOUTEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_SEQTIMEOUTEN_SHIFT)) & FLEXSPI_INTEN_SEQTIMEOUTEN_MASK) + +#define FLEXSPI_INTEN_KEYDONEEN_MASK (0x1000U) +#define FLEXSPI_INTEN_KEYDONEEN_SHIFT (12U) +/*! KEYDONEEN - OTFAD Key Blob Processing Done Interrupt Enable + * 0b0..Disable interrupt or no impact + * 0b1..Enable interrupt + */ +#define FLEXSPI_INTEN_KEYDONEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_KEYDONEEN_SHIFT)) & FLEXSPI_INTEN_KEYDONEEN_MASK) + +#define FLEXSPI_INTEN_KEYERROREN_MASK (0x2000U) +#define FLEXSPI_INTEN_KEYERROREN_SHIFT (13U) +/*! KEYERROREN - OTFAD Key Blob Processing Error Interrupt Enable + * 0b0..Disable interrupt or no impact + * 0b1..Enable interrupt + */ +#define FLEXSPI_INTEN_KEYERROREN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_KEYERROREN_SHIFT)) & FLEXSPI_INTEN_KEYERROREN_MASK) +/*! @} */ + +/*! @name INTR - Interrupt */ +/*! @{ */ + +#define FLEXSPI_INTR_IPCMDDONE_MASK (0x1U) +#define FLEXSPI_INTR_IPCMDDONE_SHIFT (0U) +/*! IPCMDDONE - IP-Triggered Command Sequences Execution Finished + * 0b0..Interrupt condition has not occurred + * 0b0..No effect + * 0b1..Interrupt condition has occurred + * 0b1..Clear the flag + */ +#define FLEXSPI_INTR_IPCMDDONE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPCMDDONE_SHIFT)) & FLEXSPI_INTR_IPCMDDONE_MASK) + +#define FLEXSPI_INTR_IPCMDGE_MASK (0x2U) +#define FLEXSPI_INTR_IPCMDGE_SHIFT (1U) +/*! IPCMDGE - IP-Triggered Command Sequences Grant Timeout + * 0b0..Interrupt condition has not occurred + * 0b0..No effect + * 0b1..Interrupt condition has occurred + * 0b1..Clear the flag + */ +#define FLEXSPI_INTR_IPCMDGE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPCMDGE_SHIFT)) & FLEXSPI_INTR_IPCMDGE_MASK) + +#define FLEXSPI_INTR_AHBCMDGE_MASK (0x4U) +#define FLEXSPI_INTR_AHBCMDGE_SHIFT (2U) +/*! AHBCMDGE - AHB-Triggered Command Sequences Grant Timeout + * 0b0..Interrupt condition has not occurred + * 0b0..No effect + * 0b1..Interrupt condition has occurred + * 0b1..Clear the flag + */ +#define FLEXSPI_INTR_AHBCMDGE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_AHBCMDGE_SHIFT)) & FLEXSPI_INTR_AHBCMDGE_MASK) + +#define FLEXSPI_INTR_IPCMDERR_MASK (0x8U) +#define FLEXSPI_INTR_IPCMDERR_SHIFT (3U) +/*! IPCMDERR - IP-Triggered Command Sequences Error + * 0b0..Interrupt condition has not occurred + * 0b0..No effect + * 0b1..Interrupt condition has occurred + * 0b1..Clear the flag + */ +#define FLEXSPI_INTR_IPCMDERR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPCMDERR_SHIFT)) & FLEXSPI_INTR_IPCMDERR_MASK) + +#define FLEXSPI_INTR_AHBCMDERR_MASK (0x10U) +#define FLEXSPI_INTR_AHBCMDERR_SHIFT (4U) +/*! AHBCMDERR - AHB-Triggered Command Sequences Error + * 0b0..Interrupt condition has not occurred + * 0b0..No effect + * 0b1..Interrupt condition has occurred + * 0b1..Clear the flag + */ +#define FLEXSPI_INTR_AHBCMDERR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_AHBCMDERR_SHIFT)) & FLEXSPI_INTR_AHBCMDERR_MASK) + +#define FLEXSPI_INTR_IPRXWA_MASK (0x20U) +#define FLEXSPI_INTR_IPRXWA_SHIFT (5U) +/*! IPRXWA - IP Receive FIFO Watermark Available + * 0b0..Interrupt condition has not occurred + * 0b0..No effect + * 0b1..Interrupt condition has occurred + * 0b1..Clear the flag + */ +#define FLEXSPI_INTR_IPRXWA(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPRXWA_SHIFT)) & FLEXSPI_INTR_IPRXWA_MASK) + +#define FLEXSPI_INTR_IPTXWE_MASK (0x40U) +#define FLEXSPI_INTR_IPTXWE_SHIFT (6U) +/*! IPTXWE - IP Transmit FIFO Watermark Empty + * 0b0..Interrupt condition has not occurred + * 0b0..No effect + * 0b1..Interrupt condition has occurred + * 0b1..Clear the flag + */ +#define FLEXSPI_INTR_IPTXWE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPTXWE_SHIFT)) & FLEXSPI_INTR_IPTXWE_MASK) + +#define FLEXSPI_INTR_DATALEARNFAIL_MASK (0x80U) +#define FLEXSPI_INTR_DATALEARNFAIL_SHIFT (7U) +/*! DATALEARNFAIL - Data Learning Failed + * 0b0..Interrupt condition has not occurred + * 0b0..No effect + * 0b1..Interrupt condition has occurred + * 0b1..Clear the flag + */ +#define FLEXSPI_INTR_DATALEARNFAIL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_DATALEARNFAIL_SHIFT)) & FLEXSPI_INTR_DATALEARNFAIL_MASK) + +#define FLEXSPI_INTR_SCKSTOPBYRD_MASK (0x100U) +#define FLEXSPI_INTR_SCKSTOPBYRD_SHIFT (8U) +/*! SCKSTOPBYRD - SCLK Stopped Due To Full Receive FIFO + * 0b0..Interrupt condition has not occurred + * 0b0..No effect + * 0b1..Interrupt condition has occurred + * 0b1..Clear the flag + */ +#define FLEXSPI_INTR_SCKSTOPBYRD(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_SCKSTOPBYRD_SHIFT)) & FLEXSPI_INTR_SCKSTOPBYRD_MASK) + +#define FLEXSPI_INTR_SCKSTOPBYWR_MASK (0x200U) +#define FLEXSPI_INTR_SCKSTOPBYWR_SHIFT (9U) +/*! SCKSTOPBYWR - SCLK Stopped Due To Empty Transmit FIFO + * 0b0..Interrupt condition has not occurred + * 0b0..No effect + * 0b1..Interrupt condition has occurred + * 0b1..Clear the flag + */ +#define FLEXSPI_INTR_SCKSTOPBYWR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_SCKSTOPBYWR_SHIFT)) & FLEXSPI_INTR_SCKSTOPBYWR_MASK) + +#define FLEXSPI_INTR_AHBBUSERROR_MASK (0x400U) +#define FLEXSPI_INTR_AHBBUSERROR_SHIFT (10U) +/*! AHBBUSERROR - AHB Bus Error + * 0b0..Interrupt condition has not occurred + * 0b0..No effect + * 0b1..Interrupt condition has occurred + * 0b1..Clear the flag + */ +#define FLEXSPI_INTR_AHBBUSERROR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_AHBBUSERROR_SHIFT)) & FLEXSPI_INTR_AHBBUSERROR_MASK) + +#define FLEXSPI_INTR_SEQTIMEOUT_MASK (0x800U) +#define FLEXSPI_INTR_SEQTIMEOUT_SHIFT (11U) +/*! SEQTIMEOUT - Sequence Execution Timeout + * 0b0..Interrupt condition has not occurred + * 0b0..No effect + * 0b1..Interrupt condition has occurred + * 0b1..Clear the flag + */ +#define FLEXSPI_INTR_SEQTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_SEQTIMEOUT_SHIFT)) & FLEXSPI_INTR_SEQTIMEOUT_MASK) + +#define FLEXSPI_INTR_KEYDONE_MASK (0x1000U) +#define FLEXSPI_INTR_KEYDONE_SHIFT (12U) +/*! KEYDONE - OTFAD key blob processing done interrupt. */ +#define FLEXSPI_INTR_KEYDONE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_KEYDONE_SHIFT)) & FLEXSPI_INTR_KEYDONE_MASK) + +#define FLEXSPI_INTR_KEYERROR_MASK (0x2000U) +#define FLEXSPI_INTR_KEYERROR_SHIFT (13U) +/*! KEYERROR - OTFAD Key Blob Processing Error + * 0b0..Interrupt condition has not occurred + * 0b0..No effect + * 0b1..Interrupt condition has occurred + * 0b1..Clear the flag + */ +#define FLEXSPI_INTR_KEYERROR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_KEYERROR_SHIFT)) & FLEXSPI_INTR_KEYERROR_MASK) +/*! @} */ + +/*! @name LUTKEY - LUT Key */ +/*! @{ */ + +#define FLEXSPI_LUTKEY_KEY_MASK (0xFFFFFFFFU) +#define FLEXSPI_LUTKEY_KEY_SHIFT (0U) +/*! KEY - LUT Key */ +#define FLEXSPI_LUTKEY_KEY(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUTKEY_KEY_SHIFT)) & FLEXSPI_LUTKEY_KEY_MASK) +/*! @} */ + +/*! @name LUTCR - LUT Control */ +/*! @{ */ + +#define FLEXSPI_LUTCR_LOCK_MASK (0x1U) +#define FLEXSPI_LUTCR_LOCK_SHIFT (0U) +/*! LOCK - Lock LUT + * 0b0..LUT is unlocked (LUTCR[UNLOCK] must be 1) + * 0b1..LUT is locked and cannot be written + */ +#define FLEXSPI_LUTCR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUTCR_LOCK_SHIFT)) & FLEXSPI_LUTCR_LOCK_MASK) + +#define FLEXSPI_LUTCR_UNLOCK_MASK (0x2U) +#define FLEXSPI_LUTCR_UNLOCK_SHIFT (1U) +/*! UNLOCK - Unlock LUT + * 0b0..LUT is locked (LUTCR[LOCK] must be 1) + * 0b1..LUT is unlocked and can be written + */ +#define FLEXSPI_LUTCR_UNLOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUTCR_UNLOCK_SHIFT)) & FLEXSPI_LUTCR_UNLOCK_MASK) +/*! @} */ + +/*! @name AHBRXBUFCR0 - AHB Receive Buffer 0 Control 0..AHB Receive Buffer 7 Control 0 */ +/*! @{ */ + +#define FLEXSPI_AHBRXBUFCR0_BUFSZ_MASK (0x1FFU) +#define FLEXSPI_AHBRXBUFCR0_BUFSZ_SHIFT (0U) +/*! BUFSZ - AHB Receive Buffer Size */ +#define FLEXSPI_AHBRXBUFCR0_BUFSZ(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBRXBUFCR0_BUFSZ_SHIFT)) & FLEXSPI_AHBRXBUFCR0_BUFSZ_MASK) + +#define FLEXSPI_AHBRXBUFCR0_MSTRID_MASK (0xF0000U) +#define FLEXSPI_AHBRXBUFCR0_MSTRID_SHIFT (16U) +/*! MSTRID - AHB Controller ID */ +#define FLEXSPI_AHBRXBUFCR0_MSTRID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBRXBUFCR0_MSTRID_SHIFT)) & FLEXSPI_AHBRXBUFCR0_MSTRID_MASK) + +#define FLEXSPI_AHBRXBUFCR0_PRIORITY_MASK (0x7000000U) +#define FLEXSPI_AHBRXBUFCR0_PRIORITY_SHIFT (24U) +/*! PRIORITY - AHB Controller Read Priority */ +#define FLEXSPI_AHBRXBUFCR0_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBRXBUFCR0_PRIORITY_SHIFT)) & FLEXSPI_AHBRXBUFCR0_PRIORITY_MASK) + +#define FLEXSPI_AHBRXBUFCR0_REGIONEN_MASK (0x40000000U) +#define FLEXSPI_AHBRXBUFCR0_REGIONEN_SHIFT (30U) +/*! REGIONEN - AHB Receive Buffer Address Region Enable + * 0b0..Disabled. The buffer hit is based on the value of MSTRID only. + * 0b1..Enabled. The buffer hit is based on the value of MSTRID and the address within AHBBUFREGIONSTARTn and AHBREGIONENDn. + */ +#define FLEXSPI_AHBRXBUFCR0_REGIONEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBRXBUFCR0_REGIONEN_SHIFT)) & FLEXSPI_AHBRXBUFCR0_REGIONEN_MASK) + +#define FLEXSPI_AHBRXBUFCR0_PREFETCHEN_MASK (0x80000000U) +#define FLEXSPI_AHBRXBUFCR0_PREFETCHEN_SHIFT (31U) +/*! PREFETCHEN - AHB Read Prefetch Enable + * 0b0..Disabled + * 0b1..Enabled when is enabled. + */ +#define FLEXSPI_AHBRXBUFCR0_PREFETCHEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBRXBUFCR0_PREFETCHEN_SHIFT)) & FLEXSPI_AHBRXBUFCR0_PREFETCHEN_MASK) +/*! @} */ + +/* The count of FLEXSPI_AHBRXBUFCR0 */ +#define FLEXSPI_AHBRXBUFCR0_COUNT (8U) + +/*! @name FLSHCR0 - Flash Control 0 */ +/*! @{ */ + +#define FLEXSPI_FLSHCR0_FLSHSZ_MASK (0x7FFFFFU) +#define FLEXSPI_FLSHCR0_FLSHSZ_SHIFT (0U) +/*! FLSHSZ - Flash Size in KB */ +#define FLEXSPI_FLSHCR0_FLSHSZ(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR0_FLSHSZ_SHIFT)) & FLEXSPI_FLSHCR0_FLSHSZ_MASK) + +#define FLEXSPI_FLSHCR0_ADDRSHIFT_MASK (0x20000000U) +#define FLEXSPI_FLSHCR0_ADDRSHIFT_SHIFT (29U) +/*! ADDRSHIFT - AHB Address Shift Function control + * 0b0..Disabled + * 0b1..Enabled + */ +#define FLEXSPI_FLSHCR0_ADDRSHIFT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR0_ADDRSHIFT_SHIFT)) & FLEXSPI_FLSHCR0_ADDRSHIFT_MASK) +/*! @} */ + +/* The count of FLEXSPI_FLSHCR0 */ +#define FLEXSPI_FLSHCR0_COUNT (4U) + +/*! @name FLSHCR1 - Flash Control 1 */ +/*! @{ */ + +#define FLEXSPI_FLSHCR1_TCSS_MASK (0x1FU) +#define FLEXSPI_FLSHCR1_TCSS_SHIFT (0U) +/*! TCSS - Serial Flash CS Setup Time */ +#define FLEXSPI_FLSHCR1_TCSS(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_TCSS_SHIFT)) & FLEXSPI_FLSHCR1_TCSS_MASK) + +#define FLEXSPI_FLSHCR1_TCSH_MASK (0x3E0U) +#define FLEXSPI_FLSHCR1_TCSH_SHIFT (5U) +/*! TCSH - Serial Flash CS Hold Time */ +#define FLEXSPI_FLSHCR1_TCSH(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_TCSH_SHIFT)) & FLEXSPI_FLSHCR1_TCSH_MASK) + +#define FLEXSPI_FLSHCR1_WA_MASK (0x400U) +#define FLEXSPI_FLSHCR1_WA_SHIFT (10U) +/*! WA - Word-Addressable + * 0b0..Byte-addressable + * 0b1..Word-addressable + */ +#define FLEXSPI_FLSHCR1_WA(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_WA_SHIFT)) & FLEXSPI_FLSHCR1_WA_MASK) + +#define FLEXSPI_FLSHCR1_CAS_MASK (0x7800U) +#define FLEXSPI_FLSHCR1_CAS_SHIFT (11U) +/*! CAS - Column Address Size */ +#define FLEXSPI_FLSHCR1_CAS(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_CAS_SHIFT)) & FLEXSPI_FLSHCR1_CAS_MASK) + +#define FLEXSPI_FLSHCR1_CSINTERVALUNIT_MASK (0x8000U) +#define FLEXSPI_FLSHCR1_CSINTERVALUNIT_SHIFT (15U) +/*! CSINTERVALUNIT - Chip Select Interval Unit + * 0b0..1 serial clock cycle + * 0b1..256 serial clock cycles + */ +#define FLEXSPI_FLSHCR1_CSINTERVALUNIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_CSINTERVALUNIT_SHIFT)) & FLEXSPI_FLSHCR1_CSINTERVALUNIT_MASK) + +#define FLEXSPI_FLSHCR1_CSINTERVAL_MASK (0xFFFF0000U) +#define FLEXSPI_FLSHCR1_CSINTERVAL_SHIFT (16U) +/*! CSINTERVAL - Chip Select Interval */ +#define FLEXSPI_FLSHCR1_CSINTERVAL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_CSINTERVAL_SHIFT)) & FLEXSPI_FLSHCR1_CSINTERVAL_MASK) +/*! @} */ + +/* The count of FLEXSPI_FLSHCR1 */ +#define FLEXSPI_FLSHCR1_COUNT (4U) + +/*! @name FLSHCR2 - Flash Control 2 */ +/*! @{ */ + +#define FLEXSPI_FLSHCR2_ARDSEQID_MASK (0x1FU) +#define FLEXSPI_FLSHCR2_ARDSEQID_SHIFT (0U) +/*! ARDSEQID - Sequence Index for AHB Read-Triggered Command in LUT */ +#define FLEXSPI_FLSHCR2_ARDSEQID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_ARDSEQID_SHIFT)) & FLEXSPI_FLSHCR2_ARDSEQID_MASK) + +#define FLEXSPI_FLSHCR2_ARDSEQNUM_MASK (0xE0U) +#define FLEXSPI_FLSHCR2_ARDSEQNUM_SHIFT (5U) +/*! ARDSEQNUM - Sequence Number for AHB Read-Triggered Command */ +#define FLEXSPI_FLSHCR2_ARDSEQNUM(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_ARDSEQNUM_SHIFT)) & FLEXSPI_FLSHCR2_ARDSEQNUM_MASK) + +#define FLEXSPI_FLSHCR2_AWRSEQID_MASK (0x1F00U) +#define FLEXSPI_FLSHCR2_AWRSEQID_SHIFT (8U) +/*! AWRSEQID - Sequence Index for AHB Write-Triggered Command */ +#define FLEXSPI_FLSHCR2_AWRSEQID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_AWRSEQID_SHIFT)) & FLEXSPI_FLSHCR2_AWRSEQID_MASK) + +#define FLEXSPI_FLSHCR2_AWRSEQNUM_MASK (0xE000U) +#define FLEXSPI_FLSHCR2_AWRSEQNUM_SHIFT (13U) +/*! AWRSEQNUM - Sequence Number for AHB Write-Triggered Command */ +#define FLEXSPI_FLSHCR2_AWRSEQNUM(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_AWRSEQNUM_SHIFT)) & FLEXSPI_FLSHCR2_AWRSEQNUM_MASK) + +#define FLEXSPI_FLSHCR2_AWRWAIT_MASK (0xFFF0000U) +#define FLEXSPI_FLSHCR2_AWRWAIT_SHIFT (16U) +/*! AWRWAIT - AHB Write Wait */ +#define FLEXSPI_FLSHCR2_AWRWAIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_AWRWAIT_SHIFT)) & FLEXSPI_FLSHCR2_AWRWAIT_MASK) + +#define FLEXSPI_FLSHCR2_AWRWAITUNIT_MASK (0x70000000U) +#define FLEXSPI_FLSHCR2_AWRWAITUNIT_SHIFT (28U) +/*! AWRWAITUNIT - AWRWAIT Unit + * 0b000..2 + * 0b001..8 + * 0b010..32 + * 0b011..128 + * 0b100..512 + * 0b101..2048 + * 0b110..8192 + * 0b111..32768 + */ +#define FLEXSPI_FLSHCR2_AWRWAITUNIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_AWRWAITUNIT_SHIFT)) & FLEXSPI_FLSHCR2_AWRWAITUNIT_MASK) + +#define FLEXSPI_FLSHCR2_CLRINSTRPTR_MASK (0x80000000U) +#define FLEXSPI_FLSHCR2_CLRINSTRPTR_SHIFT (31U) +/*! CLRINSTRPTR - Clear Instruction Pointer */ +#define FLEXSPI_FLSHCR2_CLRINSTRPTR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_CLRINSTRPTR_SHIFT)) & FLEXSPI_FLSHCR2_CLRINSTRPTR_MASK) +/*! @} */ + +/* The count of FLEXSPI_FLSHCR2 */ +#define FLEXSPI_FLSHCR2_COUNT (4U) + +/*! @name FLSHCR4 - Flash Control 4 */ +/*! @{ */ + +#define FLEXSPI_FLSHCR4_WMOPT1_MASK (0x1U) +#define FLEXSPI_FLSHCR4_WMOPT1_SHIFT (0U) +/*! WMOPT1 - Write Mask Option 1 + * 0b0..When writing to an external device, DQS pin is used as write mask. When flash memory is accessed in + * individual mode, AHB or IP write burst start address alignment is not limited. + * 0b1..When writing to an external device, DQS pin is not used as write mask. When flash memory is accessed in + * individual mode, AHB or IP write burst start address alignment is limited. + */ +#define FLEXSPI_FLSHCR4_WMOPT1(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR4_WMOPT1_SHIFT)) & FLEXSPI_FLSHCR4_WMOPT1_MASK) + +#define FLEXSPI_FLSHCR4_WMOPT2_MASK (0x2U) +#define FLEXSPI_FLSHCR4_WMOPT2_SHIFT (1U) +/*! WMOPT2 - Write Mask Option 2 + * 0b0..When writing to an external device, DQS pin is used as write mask. When flash memory is accessed in + * individual mode, AHB or IP write burst length is not limited. + * 0b1..When writing to an external device, DQS pin is not used as write mask. When flash memory is accessed in + * individual mode, AHB or IP write burst length is limited. The minimum write burst length should be 4. + */ +#define FLEXSPI_FLSHCR4_WMOPT2(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR4_WMOPT2_SHIFT)) & FLEXSPI_FLSHCR4_WMOPT2_MASK) + +#define FLEXSPI_FLSHCR4_WMENA_MASK (0x4U) +#define FLEXSPI_FLSHCR4_WMENA_SHIFT (2U) +/*! WMENA - Write Mask Enable for Port A + * 0b0..Disabled. When writing to external device, DQS(RWDS) pin is not driven. + * 0b1..Enabled. When writing to external device, FlexSPI drives DQS(RWDS) pin as write mask output. + */ +#define FLEXSPI_FLSHCR4_WMENA(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR4_WMENA_SHIFT)) & FLEXSPI_FLSHCR4_WMENA_MASK) +/*! @} */ + +/*! @name IPCR0 - IP Control 0 */ +/*! @{ */ + +#define FLEXSPI_IPCR0_SFAR_MASK (0xFFFFFFFFU) +#define FLEXSPI_IPCR0_SFAR_SHIFT (0U) +/*! SFAR - Serial Flash Address */ +#define FLEXSPI_IPCR0_SFAR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR0_SFAR_SHIFT)) & FLEXSPI_IPCR0_SFAR_MASK) +/*! @} */ + +/*! @name IPCR1 - IP Control 1 */ +/*! @{ */ + +#define FLEXSPI_IPCR1_IDATSZ_MASK (0xFFFFU) +#define FLEXSPI_IPCR1_IDATSZ_SHIFT (0U) +/*! IDATSZ - Flash Read/Program Data Size (in bytes) for IP command. */ +#define FLEXSPI_IPCR1_IDATSZ(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR1_IDATSZ_SHIFT)) & FLEXSPI_IPCR1_IDATSZ_MASK) + +#define FLEXSPI_IPCR1_ISEQID_MASK (0x1F0000U) +#define FLEXSPI_IPCR1_ISEQID_SHIFT (16U) +/*! ISEQID - Sequence Index in LUT for IP command. */ +#define FLEXSPI_IPCR1_ISEQID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR1_ISEQID_SHIFT)) & FLEXSPI_IPCR1_ISEQID_MASK) + +#define FLEXSPI_IPCR1_ISEQNUM_MASK (0x7000000U) +#define FLEXSPI_IPCR1_ISEQNUM_SHIFT (24U) +/*! ISEQNUM - Sequence Number for IP command: ISEQNUM+1. */ +#define FLEXSPI_IPCR1_ISEQNUM(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR1_ISEQNUM_SHIFT)) & FLEXSPI_IPCR1_ISEQNUM_MASK) +/*! @} */ + +/*! @name IPCR2 - IP Control 2 */ +/*! @{ */ + +#define FLEXSPI_IPCR2_IPBLKAHBREQ_MASK (0x1U) +#define FLEXSPI_IPCR2_IPBLKAHBREQ_SHIFT (0U) +/*! IPBLKAHBREQ - IP Command Blocking AHB Command Request Enable + * 0b0..IP commands do not block AHB command requests. + * 0b1..IP commands block AHB command requests. + */ +#define FLEXSPI_IPCR2_IPBLKAHBREQ(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR2_IPBLKAHBREQ_SHIFT)) & FLEXSPI_IPCR2_IPBLKAHBREQ_MASK) + +#define FLEXSPI_IPCR2_IPBLKAHBACK_MASK (0x2U) +#define FLEXSPI_IPCR2_IPBLKAHBACK_SHIFT (1U) +/*! IPBLKAHBACK - IP Command Blocking AHB Command Acknowledgment Enable + * 0b0..IP commands do not block AHB command acknowledgment. + * 0b1..IP commands block AHB command acknowledgment. + */ +#define FLEXSPI_IPCR2_IPBLKAHBACK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR2_IPBLKAHBACK_SHIFT)) & FLEXSPI_IPCR2_IPBLKAHBACK_MASK) + +#define FLEXSPI_IPCR2_IPBLKALLAHB_MASK (0x4U) +#define FLEXSPI_IPCR2_IPBLKALLAHB_SHIFT (2U) +/*! IPBLKALLAHB - IP Command Blocking All AHB Command Enable + * 0b0.. + * 0b1..IP commands block all AHB commands. + */ +#define FLEXSPI_IPCR2_IPBLKALLAHB(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR2_IPBLKALLAHB_SHIFT)) & FLEXSPI_IPCR2_IPBLKALLAHB_MASK) +/*! @} */ + +/*! @name IPCMD - IP Command */ +/*! @{ */ + +#define FLEXSPI_IPCMD_TRG_MASK (0x1U) +#define FLEXSPI_IPCMD_TRG_SHIFT (0U) +/*! TRG - Command Trigger + * 0b0..No action + * 0b1..Start the IP command that the IPCR0 and IPCR1 registers define. + */ +#define FLEXSPI_IPCMD_TRG(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCMD_TRG_SHIFT)) & FLEXSPI_IPCMD_TRG_MASK) +/*! @} */ + +/*! @name DLPR - Data Learning Pattern */ +/*! @{ */ + +#define FLEXSPI_DLPR_DLP_MASK (0xFFFFFFFFU) +#define FLEXSPI_DLPR_DLP_SHIFT (0U) +/*! DLP - Data Learning Pattern */ +#define FLEXSPI_DLPR_DLP(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLPR_DLP_SHIFT)) & FLEXSPI_DLPR_DLP_MASK) +/*! @} */ + +/*! @name IPRXFCR - IP Receive FIFO Control */ +/*! @{ */ + +#define FLEXSPI_IPRXFCR_CLRIPRXF_MASK (0x1U) +#define FLEXSPI_IPRXFCR_CLRIPRXF_SHIFT (0U) +/*! CLRIPRXF - Clear IP Receive FIFO + * 0b0..No function + * 0b1..A clock cycle pulse clears all valid data entries in IP receive FIFO. + */ +#define FLEXSPI_IPRXFCR_CLRIPRXF(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFCR_CLRIPRXF_SHIFT)) & FLEXSPI_IPRXFCR_CLRIPRXF_MASK) + +#define FLEXSPI_IPRXFCR_RXDMAEN_MASK (0x2U) +#define FLEXSPI_IPRXFCR_RXDMAEN_SHIFT (1U) +/*! RXDMAEN - IP Receive FIFO Reading by DMA Enable + * 0b0..Disabled. The processor reads the FIFO. + * 0b1..Enabled. DMA reads the FIFO. + */ +#define FLEXSPI_IPRXFCR_RXDMAEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFCR_RXDMAEN_SHIFT)) & FLEXSPI_IPRXFCR_RXDMAEN_MASK) + +#define FLEXSPI_IPRXFCR_RXWMRK_MASK (0xFCU) +#define FLEXSPI_IPRXFCR_RXWMRK_SHIFT (2U) +/*! RXWMRK - IP Receive FIFO Watermark Level */ +#define FLEXSPI_IPRXFCR_RXWMRK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFCR_RXWMRK_SHIFT)) & FLEXSPI_IPRXFCR_RXWMRK_MASK) +/*! @} */ + +/*! @name IPTXFCR - IP Transmit FIFO Control */ +/*! @{ */ + +#define FLEXSPI_IPTXFCR_CLRIPTXF_MASK (0x1U) +#define FLEXSPI_IPTXFCR_CLRIPTXF_SHIFT (0U) +/*! CLRIPTXF - Clear IP Transmit FIFO + * 0b0..No function + * 0b1..A clock cycle pulse clears all valid data entries in the IP transmit FIFO. + */ +#define FLEXSPI_IPTXFCR_CLRIPTXF(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFCR_CLRIPTXF_SHIFT)) & FLEXSPI_IPTXFCR_CLRIPTXF_MASK) + +#define FLEXSPI_IPTXFCR_TXDMAEN_MASK (0x2U) +#define FLEXSPI_IPTXFCR_TXDMAEN_SHIFT (1U) +/*! TXDMAEN - Transmit FIFO DMA Enable + * 0b0..Processor + * 0b1..DMA + */ +#define FLEXSPI_IPTXFCR_TXDMAEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFCR_TXDMAEN_SHIFT)) & FLEXSPI_IPTXFCR_TXDMAEN_MASK) + +#define FLEXSPI_IPTXFCR_TXWMRK_MASK (0x1FCU) +#define FLEXSPI_IPTXFCR_TXWMRK_SHIFT (2U) +/*! TXWMRK - Transmit Watermark Level */ +#define FLEXSPI_IPTXFCR_TXWMRK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFCR_TXWMRK_SHIFT)) & FLEXSPI_IPTXFCR_TXWMRK_MASK) +/*! @} */ + +/*! @name DLLCR - DLL Control 0 */ +/*! @{ */ + +#define FLEXSPI_DLLCR_DLLEN_MASK (0x1U) +#define FLEXSPI_DLLCR_DLLEN_SHIFT (0U) +/*! DLLEN - DLL Calibration Enable + * 0b0..Disable + * 0b1..Enable + */ +#define FLEXSPI_DLLCR_DLLEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_DLLEN_SHIFT)) & FLEXSPI_DLLCR_DLLEN_MASK) + +#define FLEXSPI_DLLCR_DLLRESET_MASK (0x2U) +#define FLEXSPI_DLLCR_DLLRESET_SHIFT (1U) +/*! DLLRESET - DLL reset + * 0b0..No function + * 0b1..Force DLL reset. + */ +#define FLEXSPI_DLLCR_DLLRESET(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_DLLRESET_SHIFT)) & FLEXSPI_DLLCR_DLLRESET_MASK) + +#define FLEXSPI_DLLCR_SLVDLYTARGET_MASK (0x78U) +#define FLEXSPI_DLLCR_SLVDLYTARGET_SHIFT (3U) +/*! SLVDLYTARGET - Target Delay Line */ +#define FLEXSPI_DLLCR_SLVDLYTARGET(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_SLVDLYTARGET_SHIFT)) & FLEXSPI_DLLCR_SLVDLYTARGET_MASK) + +#define FLEXSPI_DLLCR_OVRDEN_MASK (0x100U) +#define FLEXSPI_DLLCR_OVRDEN_SHIFT (8U) +/*! OVRDEN - Target Clock Delay Line Override Value Enable + * 0b0..Disable + * 0b1..Enable + */ +#define FLEXSPI_DLLCR_OVRDEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_OVRDEN_SHIFT)) & FLEXSPI_DLLCR_OVRDEN_MASK) + +#define FLEXSPI_DLLCR_OVRDVAL_MASK (0x7E00U) +#define FLEXSPI_DLLCR_OVRDVAL_SHIFT (9U) +/*! OVRDVAL - Target Clock Delay Line Override Value */ +#define FLEXSPI_DLLCR_OVRDVAL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_OVRDVAL_SHIFT)) & FLEXSPI_DLLCR_OVRDVAL_MASK) + +#define FLEXSPI_DLLCR_REFPHASEGAP_MASK (0x18000U) +#define FLEXSPI_DLLCR_REFPHASEGAP_SHIFT (15U) +/*! REFPHASEGAP - Reference Clock Delay Line Phase Adjust Gap. REFPHASEGAP setting of 2h is recommended if DLLEN is set. */ +#define FLEXSPI_DLLCR_REFPHASEGAP(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_REFPHASEGAP_SHIFT)) & FLEXSPI_DLLCR_REFPHASEGAP_MASK) + +#define FLEXSPI_DLLCR_REFPHASESTART_MASK (0xE0000U) +#define FLEXSPI_DLLCR_REFPHASESTART_SHIFT (17U) +/*! REFPHASESTART - Reference Clock Delay Line Start Phase */ +#define FLEXSPI_DLLCR_REFPHASESTART(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_REFPHASESTART_SHIFT)) & FLEXSPI_DLLCR_REFPHASESTART_MASK) +/*! @} */ + +/* The count of FLEXSPI_DLLCR */ +#define FLEXSPI_DLLCR_COUNT (2U) + +/*! @name STS0 - Status 0 */ +/*! @{ */ + +#define FLEXSPI_STS0_SEQIDLE_MASK (0x1U) +#define FLEXSPI_STS0_SEQIDLE_SHIFT (0U) +/*! SEQIDLE - SEQ_CTL State Machine Idle + * 0b0..Not idle + * 0b1..Idle + */ +#define FLEXSPI_STS0_SEQIDLE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS0_SEQIDLE_SHIFT)) & FLEXSPI_STS0_SEQIDLE_MASK) + +#define FLEXSPI_STS0_ARBIDLE_MASK (0x2U) +#define FLEXSPI_STS0_ARBIDLE_SHIFT (1U) +/*! ARBIDLE - ARB_CTL State Machine Idle + * 0b0..Not idle + * 0b1..Idle + */ +#define FLEXSPI_STS0_ARBIDLE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS0_ARBIDLE_SHIFT)) & FLEXSPI_STS0_ARBIDLE_MASK) + +#define FLEXSPI_STS0_ARBCMDSRC_MASK (0xCU) +#define FLEXSPI_STS0_ARBCMDSRC_SHIFT (2U) +/*! ARBCMDSRC - ARB Command Source + * 0b00..Trigger source is AHB read command. + * 0b01..Trigger source is AHB write command. + * 0b10..Trigger source is IP command (by writing 1 to IPCMD[TRG]). + * 0b11..Trigger source is a suspended command that has resumed. + */ +#define FLEXSPI_STS0_ARBCMDSRC(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS0_ARBCMDSRC_SHIFT)) & FLEXSPI_STS0_ARBCMDSRC_MASK) + +#define FLEXSPI_STS0_DATALEARNPHASEA_MASK (0xF0U) +#define FLEXSPI_STS0_DATALEARNPHASEA_SHIFT (4U) +/*! DATALEARNPHASEA - Data Learning Phase Selection on Port A */ +#define FLEXSPI_STS0_DATALEARNPHASEA(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS0_DATALEARNPHASEA_SHIFT)) & FLEXSPI_STS0_DATALEARNPHASEA_MASK) +/*! @} */ + +/*! @name STS1 - Status 1 */ +/*! @{ */ + +#define FLEXSPI_STS1_AHBCMDERRID_MASK (0x1FU) +#define FLEXSPI_STS1_AHBCMDERRID_SHIFT (0U) +/*! AHBCMDERRID - AHB Command Error ID */ +#define FLEXSPI_STS1_AHBCMDERRID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS1_AHBCMDERRID_SHIFT)) & FLEXSPI_STS1_AHBCMDERRID_MASK) + +#define FLEXSPI_STS1_AHBCMDERRCODE_MASK (0xF00U) +#define FLEXSPI_STS1_AHBCMDERRCODE_SHIFT (8U) +/*! AHBCMDERRCODE - AHB Command Error Code + * 0b0000..No error + * 0b0010..AHB Write command with JMP_ON_CS instruction used in the sequence + * 0b0011..Unknown instruction opcode in the sequence + * 0b0100..DUMMY_SDR or DUMMY_RWDS_SDR instruction used in DDR sequence + * 0b0101..DUMMY_DDR or DUMMY_RWDS_DDR instruction used in SDR sequence + * 0b1110..Sequence execution timeout + */ +#define FLEXSPI_STS1_AHBCMDERRCODE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS1_AHBCMDERRCODE_SHIFT)) & FLEXSPI_STS1_AHBCMDERRCODE_MASK) + +#define FLEXSPI_STS1_IPCMDERRID_MASK (0x1F0000U) +#define FLEXSPI_STS1_IPCMDERRID_SHIFT (16U) +/*! IPCMDERRID - IP Command Error ID */ +#define FLEXSPI_STS1_IPCMDERRID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS1_IPCMDERRID_SHIFT)) & FLEXSPI_STS1_IPCMDERRID_MASK) + +#define FLEXSPI_STS1_IPCMDERRCODE_MASK (0xF000000U) +#define FLEXSPI_STS1_IPCMDERRCODE_SHIFT (24U) +/*! IPCMDERRCODE - IP Command Error Code + * 0b0000..No error + * 0b0010..IP command with JMP_ON_CS instruction used in the sequence + * 0b0011..Unknown instruction opcode in the sequence + * 0b0100..DUMMY_SDR or DUMMY_RWDS_SDR instruction used in DDR sequence + * 0b0101..DUMMY_DDR or DUMMY_RWDS_DDR instruction used in SDR sequence + * 0b0110..Flash memory access start address exceeds entire flash address range (A1, A2, B1, and B2) + * 0b1110..Sequence execution timeout + * 0b1111..Flash boundary crossed + */ +#define FLEXSPI_STS1_IPCMDERRCODE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS1_IPCMDERRCODE_SHIFT)) & FLEXSPI_STS1_IPCMDERRCODE_MASK) +/*! @} */ + +/*! @name STS2 - Status 2 */ +/*! @{ */ + +#define FLEXSPI_STS2_ASLVLOCK_MASK (0x1U) +#define FLEXSPI_STS2_ASLVLOCK_SHIFT (0U) +/*! ASLVLOCK - Flash A Sample Target Delay Line Locked + * 0b0..Not locked + * 0b1..Locked + */ +#define FLEXSPI_STS2_ASLVLOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_ASLVLOCK_SHIFT)) & FLEXSPI_STS2_ASLVLOCK_MASK) + +#define FLEXSPI_STS2_AREFLOCK_MASK (0x2U) +#define FLEXSPI_STS2_AREFLOCK_SHIFT (1U) +/*! AREFLOCK - Flash A Sample Clock Reference Delay Line Locked + * 0b0..Not locked + * 0b1..Locked + */ +#define FLEXSPI_STS2_AREFLOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_AREFLOCK_SHIFT)) & FLEXSPI_STS2_AREFLOCK_MASK) + +#define FLEXSPI_STS2_ASLVSEL_MASK (0xFCU) +#define FLEXSPI_STS2_ASLVSEL_SHIFT (2U) +/*! ASLVSEL - Flash A Sample Clock Target Delay Line Delay Cell Number */ +#define FLEXSPI_STS2_ASLVSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_ASLVSEL_SHIFT)) & FLEXSPI_STS2_ASLVSEL_MASK) + +#define FLEXSPI_STS2_AREFSEL_MASK (0x3F00U) +#define FLEXSPI_STS2_AREFSEL_SHIFT (8U) +/*! AREFSEL - Flash A Sample Clock Reference Delay Line Delay Cell Number */ +#define FLEXSPI_STS2_AREFSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_AREFSEL_SHIFT)) & FLEXSPI_STS2_AREFSEL_MASK) + +#define FLEXSPI_STS2_BSLVLOCK_MASK (0x10000U) +#define FLEXSPI_STS2_BSLVLOCK_SHIFT (16U) +/*! BSLVLOCK - Flash B Sample Target Reference Delay Line Locked + * 0b0..Not locked + * 0b1..Locked + */ +#define FLEXSPI_STS2_BSLVLOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_BSLVLOCK_SHIFT)) & FLEXSPI_STS2_BSLVLOCK_MASK) + +#define FLEXSPI_STS2_BREFLOCK_MASK (0x20000U) +#define FLEXSPI_STS2_BREFLOCK_SHIFT (17U) +/*! BREFLOCK - Flash B Sample Clock Reference Delay Line Locked + * 0b0..Not locked + * 0b1..Locked + */ +#define FLEXSPI_STS2_BREFLOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_BREFLOCK_SHIFT)) & FLEXSPI_STS2_BREFLOCK_MASK) + +#define FLEXSPI_STS2_BSLVSEL_MASK (0xFC0000U) +#define FLEXSPI_STS2_BSLVSEL_SHIFT (18U) +/*! BSLVSEL - Flash B Sample Clock Target Delay Line Delay Cell Number */ +#define FLEXSPI_STS2_BSLVSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_BSLVSEL_SHIFT)) & FLEXSPI_STS2_BSLVSEL_MASK) + +#define FLEXSPI_STS2_BREFSEL_MASK (0x3F000000U) +#define FLEXSPI_STS2_BREFSEL_SHIFT (24U) +/*! BREFSEL - Flash B Sample Clock Reference Delay Line Delay Cell Number */ +#define FLEXSPI_STS2_BREFSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_BREFSEL_SHIFT)) & FLEXSPI_STS2_BREFSEL_MASK) +/*! @} */ + +/*! @name AHBSPNDSTS - AHB Suspend Status */ +/*! @{ */ + +#define FLEXSPI_AHBSPNDSTS_ACTIVE_MASK (0x1U) +#define FLEXSPI_AHBSPNDSTS_ACTIVE_SHIFT (0U) +/*! ACTIVE - Active AHB Read Prefetch Suspended + * 0b0..No suspended AHB read prefetch command. + * 0b1..An AHB read prefetch command sequence has been suspended. + */ +#define FLEXSPI_AHBSPNDSTS_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBSPNDSTS_ACTIVE_SHIFT)) & FLEXSPI_AHBSPNDSTS_ACTIVE_MASK) + +#define FLEXSPI_AHBSPNDSTS_BUFID_MASK (0xEU) +#define FLEXSPI_AHBSPNDSTS_BUFID_SHIFT (1U) +/*! BUFID - AHB Receive Buffer ID for Suspended Command Sequence */ +#define FLEXSPI_AHBSPNDSTS_BUFID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBSPNDSTS_BUFID_SHIFT)) & FLEXSPI_AHBSPNDSTS_BUFID_MASK) + +#define FLEXSPI_AHBSPNDSTS_DATLFT_MASK (0xFFFF0000U) +#define FLEXSPI_AHBSPNDSTS_DATLFT_SHIFT (16U) +/*! DATLFT - Data Left */ +#define FLEXSPI_AHBSPNDSTS_DATLFT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBSPNDSTS_DATLFT_SHIFT)) & FLEXSPI_AHBSPNDSTS_DATLFT_MASK) +/*! @} */ + +/*! @name IPRXFSTS - IP Receive FIFO Status */ +/*! @{ */ + +#define FLEXSPI_IPRXFSTS_FILL_MASK (0xFFU) +#define FLEXSPI_IPRXFSTS_FILL_SHIFT (0U) +/*! FILL - Fill Level of IP Receive FIFO */ +#define FLEXSPI_IPRXFSTS_FILL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFSTS_FILL_SHIFT)) & FLEXSPI_IPRXFSTS_FILL_MASK) + +#define FLEXSPI_IPRXFSTS_RDCNTR_MASK (0xFFFF0000U) +#define FLEXSPI_IPRXFSTS_RDCNTR_SHIFT (16U) +/*! RDCNTR - Read Data Counter */ +#define FLEXSPI_IPRXFSTS_RDCNTR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFSTS_RDCNTR_SHIFT)) & FLEXSPI_IPRXFSTS_RDCNTR_MASK) +/*! @} */ + +/*! @name IPTXFSTS - IP Transmit FIFO Status */ +/*! @{ */ + +#define FLEXSPI_IPTXFSTS_FILL_MASK (0xFFU) +#define FLEXSPI_IPTXFSTS_FILL_SHIFT (0U) +/*! FILL - Fill Level of IP Transmit FIFO */ +#define FLEXSPI_IPTXFSTS_FILL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFSTS_FILL_SHIFT)) & FLEXSPI_IPTXFSTS_FILL_MASK) + +#define FLEXSPI_IPTXFSTS_WRCNTR_MASK (0xFFFF0000U) +#define FLEXSPI_IPTXFSTS_WRCNTR_SHIFT (16U) +/*! WRCNTR - Write Data Counter */ +#define FLEXSPI_IPTXFSTS_WRCNTR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFSTS_WRCNTR_SHIFT)) & FLEXSPI_IPTXFSTS_WRCNTR_MASK) +/*! @} */ + +/*! @name RFDR - IP Receive FIFO Data 0..IP Receive FIFO Data 31 */ +/*! @{ */ + +#define FLEXSPI_RFDR_RXDATA_MASK (0xFFFFFFFFU) +#define FLEXSPI_RFDR_RXDATA_SHIFT (0U) +/*! RXDATA - Receive Data */ +#define FLEXSPI_RFDR_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_RFDR_RXDATA_SHIFT)) & FLEXSPI_RFDR_RXDATA_MASK) +/*! @} */ + +/* The count of FLEXSPI_RFDR */ +#define FLEXSPI_RFDR_COUNT (32U) + +/*! @name TFDR - IP TX FIFO Data 0..IP TX FIFO Data 31 */ +/*! @{ */ + +#define FLEXSPI_TFDR_TXDATA_MASK (0xFFFFFFFFU) +#define FLEXSPI_TFDR_TXDATA_SHIFT (0U) +/*! TXDATA - Transmit Data */ +#define FLEXSPI_TFDR_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_TFDR_TXDATA_SHIFT)) & FLEXSPI_TFDR_TXDATA_MASK) +/*! @} */ + +/* The count of FLEXSPI_TFDR */ +#define FLEXSPI_TFDR_COUNT (32U) + +/*! @name LUT - Lookup Table 0..Lookup Table 127 */ +/*! @{ */ + +#define FLEXSPI_LUT_OPERAND0_MASK (0xFFU) +#define FLEXSPI_LUT_OPERAND0_SHIFT (0U) +/*! OPERAND0 - OPERAND0 */ +#define FLEXSPI_LUT_OPERAND0(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_OPERAND0_SHIFT)) & FLEXSPI_LUT_OPERAND0_MASK) + +#define FLEXSPI_LUT_NUM_PADS0_MASK (0x300U) +#define FLEXSPI_LUT_NUM_PADS0_SHIFT (8U) +/*! NUM_PADS0 - NUM_PADS0 */ +#define FLEXSPI_LUT_NUM_PADS0(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_NUM_PADS0_SHIFT)) & FLEXSPI_LUT_NUM_PADS0_MASK) + +#define FLEXSPI_LUT_OPCODE0_MASK (0xFC00U) +#define FLEXSPI_LUT_OPCODE0_SHIFT (10U) +/*! OPCODE0 - OPCODE */ +#define FLEXSPI_LUT_OPCODE0(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_OPCODE0_SHIFT)) & FLEXSPI_LUT_OPCODE0_MASK) + +#define FLEXSPI_LUT_OPERAND1_MASK (0xFF0000U) +#define FLEXSPI_LUT_OPERAND1_SHIFT (16U) +/*! OPERAND1 - OPERAND1 */ +#define FLEXSPI_LUT_OPERAND1(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_OPERAND1_SHIFT)) & FLEXSPI_LUT_OPERAND1_MASK) + +#define FLEXSPI_LUT_NUM_PADS1_MASK (0x3000000U) +#define FLEXSPI_LUT_NUM_PADS1_SHIFT (24U) +/*! NUM_PADS1 - NUM_PADS1 */ +#define FLEXSPI_LUT_NUM_PADS1(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_NUM_PADS1_SHIFT)) & FLEXSPI_LUT_NUM_PADS1_MASK) + +#define FLEXSPI_LUT_OPCODE1_MASK (0xFC000000U) +#define FLEXSPI_LUT_OPCODE1_SHIFT (26U) +/*! OPCODE1 - OPCODE1 */ +#define FLEXSPI_LUT_OPCODE1(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_OPCODE1_SHIFT)) & FLEXSPI_LUT_OPCODE1_MASK) +/*! @} */ + +/* The count of FLEXSPI_LUT */ +#define FLEXSPI_LUT_COUNT (128U) + +/*! @name AHBBUFREGIONSTART0 - Receive Buffer Start Address of Region 0 */ +/*! @{ */ + +#define FLEXSPI_AHBBUFREGIONSTART0_START_ADDRESS_MASK (0xFFFFF000U) +#define FLEXSPI_AHBBUFREGIONSTART0_START_ADDRESS_SHIFT (12U) +/*! START_ADDRESS - Start Address of Prefetch Sub-Buffer Region */ +#define FLEXSPI_AHBBUFREGIONSTART0_START_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBBUFREGIONSTART0_START_ADDRESS_SHIFT)) & FLEXSPI_AHBBUFREGIONSTART0_START_ADDRESS_MASK) +/*! @} */ + +/*! @name AHBBUFREGIONEND0 - Receive Buffer Region 0 End Address */ +/*! @{ */ + +#define FLEXSPI_AHBBUFREGIONEND0_END_ADDRESS_MASK (0xFFFFF000U) +#define FLEXSPI_AHBBUFREGIONEND0_END_ADDRESS_SHIFT (12U) +/*! END_ADDRESS - End Address of Prefetch Sub-Buffer Region */ +#define FLEXSPI_AHBBUFREGIONEND0_END_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBBUFREGIONEND0_END_ADDRESS_SHIFT)) & FLEXSPI_AHBBUFREGIONEND0_END_ADDRESS_MASK) +/*! @} */ + +/*! @name AHBBUFREGIONSTART1 - Receive Buffer Start Address of Region 1 */ +/*! @{ */ + +#define FLEXSPI_AHBBUFREGIONSTART1_START_ADDRESS_MASK (0xFFFFF000U) +#define FLEXSPI_AHBBUFREGIONSTART1_START_ADDRESS_SHIFT (12U) +/*! START_ADDRESS - Start Address of Prefetch Sub-Buffer Region */ +#define FLEXSPI_AHBBUFREGIONSTART1_START_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBBUFREGIONSTART1_START_ADDRESS_SHIFT)) & FLEXSPI_AHBBUFREGIONSTART1_START_ADDRESS_MASK) +/*! @} */ + +/*! @name AHBBUFREGIONEND1 - Receive Buffer Region 1 End Address */ +/*! @{ */ + +#define FLEXSPI_AHBBUFREGIONEND1_END_ADDRESS_MASK (0xFFFFF000U) +#define FLEXSPI_AHBBUFREGIONEND1_END_ADDRESS_SHIFT (12U) +/*! END_ADDRESS - End Address of Prefetch Sub-Buffer Region */ +#define FLEXSPI_AHBBUFREGIONEND1_END_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBBUFREGIONEND1_END_ADDRESS_SHIFT)) & FLEXSPI_AHBBUFREGIONEND1_END_ADDRESS_MASK) +/*! @} */ + +/*! @name AHBBUFREGIONSTART2 - Receive Buffer Start Address of Region 2 */ +/*! @{ */ + +#define FLEXSPI_AHBBUFREGIONSTART2_START_ADDRESS_MASK (0xFFFFF000U) +#define FLEXSPI_AHBBUFREGIONSTART2_START_ADDRESS_SHIFT (12U) +/*! START_ADDRESS - Start Address of Prefetch Sub-Buffer Region */ +#define FLEXSPI_AHBBUFREGIONSTART2_START_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBBUFREGIONSTART2_START_ADDRESS_SHIFT)) & FLEXSPI_AHBBUFREGIONSTART2_START_ADDRESS_MASK) +/*! @} */ + +/*! @name AHBBUFREGIONEND2 - Receive Buffer Region 2 End Address */ +/*! @{ */ + +#define FLEXSPI_AHBBUFREGIONEND2_END_ADDRESS_MASK (0xFFFFF000U) +#define FLEXSPI_AHBBUFREGIONEND2_END_ADDRESS_SHIFT (12U) +/*! END_ADDRESS - End Address of Prefetch Sub-Buffer Region */ +#define FLEXSPI_AHBBUFREGIONEND2_END_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBBUFREGIONEND2_END_ADDRESS_SHIFT)) & FLEXSPI_AHBBUFREGIONEND2_END_ADDRESS_MASK) +/*! @} */ + +/*! @name AHBBUFREGIONSTART3 - Receive Buffer Start Address of Region 3 */ +/*! @{ */ + +#define FLEXSPI_AHBBUFREGIONSTART3_START_ADDRESS_MASK (0xFFFFF000U) +#define FLEXSPI_AHBBUFREGIONSTART3_START_ADDRESS_SHIFT (12U) +/*! START_ADDRESS - Start Address of Prefetch Sub-Buffer Region */ +#define FLEXSPI_AHBBUFREGIONSTART3_START_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBBUFREGIONSTART3_START_ADDRESS_SHIFT)) & FLEXSPI_AHBBUFREGIONSTART3_START_ADDRESS_MASK) +/*! @} */ + +/*! @name AHBBUFREGIONEND3 - Receive Buffer Region 3 End Address */ +/*! @{ */ + +#define FLEXSPI_AHBBUFREGIONEND3_END_ADDRESS_MASK (0xFFFFF000U) +#define FLEXSPI_AHBBUFREGIONEND3_END_ADDRESS_SHIFT (12U) +/*! END_ADDRESS - End Address of Prefetch Sub-Buffer Region */ +#define FLEXSPI_AHBBUFREGIONEND3_END_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBBUFREGIONEND3_END_ADDRESS_SHIFT)) & FLEXSPI_AHBBUFREGIONEND3_END_ADDRESS_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group FLEXSPI_Register_Masks */ + + +/* FLEXSPI - Peripheral instance base addresses */ +/** Peripheral FLEXSPI1 base address */ +#define FLEXSPI1_BASE (0x425E0000u) +/** Peripheral FLEXSPI1 base pointer */ +#define FLEXSPI1 ((FLEXSPI_Type *)FLEXSPI1_BASE) +/** Array initializer of FLEXSPI peripheral base addresses */ +#define FLEXSPI_BASE_ADDRS { 0u, FLEXSPI1_BASE } +/** Array initializer of FLEXSPI peripheral base pointers */ +#define FLEXSPI_BASE_PTRS { (FLEXSPI_Type *)0u, FLEXSPI1 } +/** FlexSPI AMBA memory base alias count */ +#define FLEXSPI_AMBA_BASE_ALIAS_COUNT (1) +/* FlexSPI1 AMBA address. */ +#define FlexSPI1_AMBA_BASE (0x38000000u) +/* FlexSPI1 ASFM address. */ +#define FlexSPI1_ASFM_BASE (0x38000000u) +/* Base Address of AHB address space mapped to IP RX FIFO. */ +#define FlexSPI1_ARDF_BASE (0x57420000u) +/* Base Address of AHB address space mapped to IP TX FIFO. */ +#define FlexSPI1_ATDF_BASE (0x57430000u) + + +/*! + * @} + */ /* end of group FLEXSPI_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- FSB Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup FSB_Peripheral_Access_Layer FSB Peripheral Access Layer + * @{ + */ + +/** FSB - Register Layout Typedef */ +typedef struct { + __I uint32_t VERID; /**< FSB Version ID Register, offset: 0x0 */ + uint8_t RESERVED_0[24]; + __I uint32_t FSB_STATUS; /**< FSB Status Register, offset: 0x1C */ + uint8_t RESERVED_1[68]; + __IO uint32_t ACCESS_COUNT; /**< Access Count Register, offset: 0x64 */ + uint8_t RESERVED_2[3992]; + __IO uint32_t FUSE_STAT; /**< Fuse Status Register, offset: 0x1000 */ + __IO uint32_t FUSE_EVNT; /**< Fuse Event Register, offset: 0x1004 */ + __IO uint32_t FUSE_INT_EN; /**< Fuse Interrupt Enable Register, offset: 0x1008 */ + __I uint32_t FUSE_INT; /**< Fuse Interrupt Register, offset: 0x100C */ + uint8_t RESERVED_3[28656]; + __I uint32_t FUSE[512]; /**< Fuse Value Registers, array offset: 0x8000, array step: 0x4 */ +} FSB_Type; + +/* ---------------------------------------------------------------------------- + -- FSB Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup FSB_Register_Masks FSB Register Masks + * @{ + */ + +/*! @name VERID - FSB Version ID Register */ +/*! @{ */ + +#define FSB_VERID_MISC_MASK (0xFFU) +#define FSB_VERID_MISC_SHIFT (0U) +/*! MISC - Feature Specification + * 0bxxxxxx1x..MU IRQ steering is enabled. + * 0bxxxxxxx1..Support for aborted transfers to OCOTP fuse space on the FSB slave APB is enabled. + */ +#define FSB_VERID_MISC(x) (((uint32_t)(((uint32_t)(x)) << FSB_VERID_MISC_SHIFT)) & FSB_VERID_MISC_MASK) + +#define FSB_VERID_ECO_MASK (0xFF00U) +#define FSB_VERID_ECO_SHIFT (8U) +/*! ECO - ECO Version Number */ +#define FSB_VERID_ECO(x) (((uint32_t)(((uint32_t)(x)) << FSB_VERID_ECO_SHIFT)) & FSB_VERID_ECO_MASK) + +#define FSB_VERID_MINOR_MASK (0xFF0000U) +#define FSB_VERID_MINOR_SHIFT (16U) +/*! MINOR - Minor Version Number */ +#define FSB_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << FSB_VERID_MINOR_SHIFT)) & FSB_VERID_MINOR_MASK) + +#define FSB_VERID_MAJOR_MASK (0xFF000000U) +#define FSB_VERID_MAJOR_SHIFT (24U) +/*! MAJOR - Major Version Number */ +#define FSB_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << FSB_VERID_MAJOR_SHIFT)) & FSB_VERID_MAJOR_MASK) +/*! @} */ + +/*! @name FSB_STATUS - FSB Status Register */ +/*! @{ */ + +#define FSB_FSB_STATUS_VMTR_MASK (0x1U) +#define FSB_FSB_STATUS_VMTR_SHIFT (0U) +/*! VMTR - MTR Trim fuses valid. */ +#define FSB_FSB_STATUS_VMTR(x) (((uint32_t)(((uint32_t)(x)) << FSB_FSB_STATUS_VMTR_SHIFT)) & FSB_FSB_STATUS_VMTR_MASK) + +#define FSB_FSB_STATUS_VERL_MASK (0x2U) +#define FSB_FSB_STATUS_VERL_SHIFT (1U) +/*! VERL - Early fuses valid. */ +#define FSB_FSB_STATUS_VERL(x) (((uint32_t)(((uint32_t)(x)) << FSB_FSB_STATUS_VERL_SHIFT)) & FSB_FSB_STATUS_VERL_MASK) + +#define FSB_FSB_STATUS_VMED_MASK (0x4U) +#define FSB_FSB_STATUS_VMED_SHIFT (2U) +/*! VMED - Medium fuses valid. */ +#define FSB_FSB_STATUS_VMED(x) (((uint32_t)(((uint32_t)(x)) << FSB_FSB_STATUS_VMED_SHIFT)) & FSB_FSB_STATUS_VMED_MASK) + +#define FSB_FSB_STATUS_VALL_MASK (0x8U) +#define FSB_FSB_STATUS_VALL_SHIFT (3U) +/*! VALL - All fuses valid. */ +#define FSB_FSB_STATUS_VALL(x) (((uint32_t)(((uint32_t)(x)) << FSB_FSB_STATUS_VALL_SHIFT)) & FSB_FSB_STATUS_VALL_MASK) + +#define FSB_FSB_STATUS_LMTR_MASK (0x10U) +#define FSB_FSB_STATUS_LMTR_SHIFT (4U) +/*! LMTR - MTR Trim fuses loaded. */ +#define FSB_FSB_STATUS_LMTR(x) (((uint32_t)(((uint32_t)(x)) << FSB_FSB_STATUS_LMTR_SHIFT)) & FSB_FSB_STATUS_LMTR_MASK) + +#define FSB_FSB_STATUS_LERL_MASK (0x20U) +#define FSB_FSB_STATUS_LERL_SHIFT (5U) +/*! LERL - Early fuses loaded. */ +#define FSB_FSB_STATUS_LERL(x) (((uint32_t)(((uint32_t)(x)) << FSB_FSB_STATUS_LERL_SHIFT)) & FSB_FSB_STATUS_LERL_MASK) + +#define FSB_FSB_STATUS_LMED_MASK (0x40U) +#define FSB_FSB_STATUS_LMED_SHIFT (6U) +/*! LMED - Medium fuses loaded. */ +#define FSB_FSB_STATUS_LMED(x) (((uint32_t)(((uint32_t)(x)) << FSB_FSB_STATUS_LMED_SHIFT)) & FSB_FSB_STATUS_LMED_MASK) + +#define FSB_FSB_STATUS_LALL_MASK (0x80U) +#define FSB_FSB_STATUS_LALL_SHIFT (7U) +/*! LALL - All fuses loaded. */ +#define FSB_FSB_STATUS_LALL(x) (((uint32_t)(((uint32_t)(x)) << FSB_FSB_STATUS_LALL_SHIFT)) & FSB_FSB_STATUS_LALL_MASK) +/*! @} */ + +/*! @name ACCESS_COUNT - Access Count Register */ +/*! @{ */ + +#define FSB_ACCESS_COUNT_COUNT_MASK (0xFFFFFFFFU) +#define FSB_ACCESS_COUNT_COUNT_SHIFT (0U) +/*! COUNT - Access Count Register. */ +#define FSB_ACCESS_COUNT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << FSB_ACCESS_COUNT_COUNT_SHIFT)) & FSB_ACCESS_COUNT_COUNT_MASK) +/*! @} */ + +/*! @name FUSE_STAT - Fuse Status Register */ +/*! @{ */ + +#define FSB_FUSE_STAT_FUSE_ADDR_MASK (0xFFFFU) +#define FSB_FUSE_STAT_FUSE_ADDR_SHIFT (0U) +/*! FUSE_ADDR - Fuse address */ +#define FSB_FUSE_STAT_FUSE_ADDR(x) (((uint32_t)(((uint32_t)(x)) << FSB_FUSE_STAT_FUSE_ADDR_SHIFT)) & FSB_FUSE_STAT_FUSE_ADDR_MASK) + +#define FSB_FUSE_STAT_SHDW_ZERO_MASK (0x1000000U) +#define FSB_FUSE_STAT_SHDW_ZERO_SHIFT (24U) +/*! SHDW_ZERO - Shadow zeroized */ +#define FSB_FUSE_STAT_SHDW_ZERO(x) (((uint32_t)(((uint32_t)(x)) << FSB_FUSE_STAT_SHDW_ZERO_SHIFT)) & FSB_FUSE_STAT_SHDW_ZERO_MASK) + +#define FSB_FUSE_STAT_SHDW_UNPROG_MASK (0x2000000U) +#define FSB_FUSE_STAT_SHDW_UNPROG_SHIFT (25U) +/*! SHDW_UNPROG - Shadow unprogrammed */ +#define FSB_FUSE_STAT_SHDW_UNPROG(x) (((uint32_t)(((uint32_t)(x)) << FSB_FUSE_STAT_SHDW_UNPROG_SHIFT)) & FSB_FUSE_STAT_SHDW_UNPROG_MASK) + +#define FSB_FUSE_STAT_FUSE_ERR_MASK (0x4000000U) +#define FSB_FUSE_STAT_FUSE_ERR_SHIFT (26U) +/*! FUSE_ERR - Fuse error */ +#define FSB_FUSE_STAT_FUSE_ERR(x) (((uint32_t)(((uint32_t)(x)) << FSB_FUSE_STAT_FUSE_ERR_SHIFT)) & FSB_FUSE_STAT_FUSE_ERR_MASK) + +#define FSB_FUSE_STAT_LOADING_MASK (0x8000000U) +#define FSB_FUSE_STAT_LOADING_SHIFT (27U) +/*! LOADING - Shadow loading */ +#define FSB_FUSE_STAT_LOADING(x) (((uint32_t)(((uint32_t)(x)) << FSB_FUSE_STAT_LOADING_SHIFT)) & FSB_FUSE_STAT_LOADING_MASK) + +#define FSB_FUSE_STAT_RLD_ERR_MASK (0x10000000U) +#define FSB_FUSE_STAT_RLD_ERR_SHIFT (28U) +/*! RLD_ERR - Reload error */ +#define FSB_FUSE_STAT_RLD_ERR(x) (((uint32_t)(((uint32_t)(x)) << FSB_FUSE_STAT_RLD_ERR_SHIFT)) & FSB_FUSE_STAT_RLD_ERR_MASK) + +#define FSB_FUSE_STAT_RD_ERR_MASK (0x20000000U) +#define FSB_FUSE_STAT_RD_ERR_SHIFT (29U) +/*! RD_ERR - Read error */ +#define FSB_FUSE_STAT_RD_ERR(x) (((uint32_t)(((uint32_t)(x)) << FSB_FUSE_STAT_RD_ERR_SHIFT)) & FSB_FUSE_STAT_RD_ERR_MASK) + +#define FSB_FUSE_STAT_ADDR_ERR_MASK (0x80000000U) +#define FSB_FUSE_STAT_ADDR_ERR_SHIFT (31U) +/*! ADDR_ERR - Address error */ +#define FSB_FUSE_STAT_ADDR_ERR(x) (((uint32_t)(((uint32_t)(x)) << FSB_FUSE_STAT_ADDR_ERR_SHIFT)) & FSB_FUSE_STAT_ADDR_ERR_MASK) +/*! @} */ + +/*! @name FUSE_EVNT - Fuse Event Register */ +/*! @{ */ + +#define FSB_FUSE_EVNT_SHDW_ZERO_MASK (0x1000000U) +#define FSB_FUSE_EVNT_SHDW_ZERO_SHIFT (24U) +/*! SHDW_ZERO - Shadow zeroized */ +#define FSB_FUSE_EVNT_SHDW_ZERO(x) (((uint32_t)(((uint32_t)(x)) << FSB_FUSE_EVNT_SHDW_ZERO_SHIFT)) & FSB_FUSE_EVNT_SHDW_ZERO_MASK) + +#define FSB_FUSE_EVNT_SHDW_UNPROG_MASK (0x2000000U) +#define FSB_FUSE_EVNT_SHDW_UNPROG_SHIFT (25U) +/*! SHDW_UNPROG - Shadow unprogrammed */ +#define FSB_FUSE_EVNT_SHDW_UNPROG(x) (((uint32_t)(((uint32_t)(x)) << FSB_FUSE_EVNT_SHDW_UNPROG_SHIFT)) & FSB_FUSE_EVNT_SHDW_UNPROG_MASK) + +#define FSB_FUSE_EVNT_FUSE_ERR_MASK (0x4000000U) +#define FSB_FUSE_EVNT_FUSE_ERR_SHIFT (26U) +/*! FUSE_ERR - Fuse error */ +#define FSB_FUSE_EVNT_FUSE_ERR(x) (((uint32_t)(((uint32_t)(x)) << FSB_FUSE_EVNT_FUSE_ERR_SHIFT)) & FSB_FUSE_EVNT_FUSE_ERR_MASK) + +#define FSB_FUSE_EVNT_LOADING_MASK (0x8000000U) +#define FSB_FUSE_EVNT_LOADING_SHIFT (27U) +/*! LOADING - Shadow loading */ +#define FSB_FUSE_EVNT_LOADING(x) (((uint32_t)(((uint32_t)(x)) << FSB_FUSE_EVNT_LOADING_SHIFT)) & FSB_FUSE_EVNT_LOADING_MASK) + +#define FSB_FUSE_EVNT_RLD_ERR_MASK (0x10000000U) +#define FSB_FUSE_EVNT_RLD_ERR_SHIFT (28U) +/*! RLD_ERR - Reload error */ +#define FSB_FUSE_EVNT_RLD_ERR(x) (((uint32_t)(((uint32_t)(x)) << FSB_FUSE_EVNT_RLD_ERR_SHIFT)) & FSB_FUSE_EVNT_RLD_ERR_MASK) + +#define FSB_FUSE_EVNT_RD_ERR_MASK (0x20000000U) +#define FSB_FUSE_EVNT_RD_ERR_SHIFT (29U) +/*! RD_ERR - Read error */ +#define FSB_FUSE_EVNT_RD_ERR(x) (((uint32_t)(((uint32_t)(x)) << FSB_FUSE_EVNT_RD_ERR_SHIFT)) & FSB_FUSE_EVNT_RD_ERR_MASK) + +#define FSB_FUSE_EVNT_ADDR_ERR_MASK (0x80000000U) +#define FSB_FUSE_EVNT_ADDR_ERR_SHIFT (31U) +/*! ADDR_ERR - Address error */ +#define FSB_FUSE_EVNT_ADDR_ERR(x) (((uint32_t)(((uint32_t)(x)) << FSB_FUSE_EVNT_ADDR_ERR_SHIFT)) & FSB_FUSE_EVNT_ADDR_ERR_MASK) +/*! @} */ + +/*! @name FUSE_INT_EN - Fuse Interrupt Enable Register */ +/*! @{ */ + +#define FSB_FUSE_INT_EN_INT_EN_MASK (0xFF000000U) +#define FSB_FUSE_INT_EN_INT_EN_SHIFT (24U) +/*! INT_EN - Interrupt Enables */ +#define FSB_FUSE_INT_EN_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << FSB_FUSE_INT_EN_INT_EN_SHIFT)) & FSB_FUSE_INT_EN_INT_EN_MASK) +/*! @} */ + +/*! @name FUSE_INT - Fuse Interrupt Register */ +/*! @{ */ + +#define FSB_FUSE_INT_INT_MASK (0xFF000000U) +#define FSB_FUSE_INT_INT_SHIFT (24U) +/*! INT - Interrupts */ +#define FSB_FUSE_INT_INT(x) (((uint32_t)(((uint32_t)(x)) << FSB_FUSE_INT_INT_SHIFT)) & FSB_FUSE_INT_INT_MASK) +/*! @} */ + +/*! @name FUSE - Fuse Value Registers */ +/*! @{ */ + +#define FSB_FUSE_FUSE_MASK (0xFFFFFFFFU) +#define FSB_FUSE_FUSE_SHIFT (0U) +/*! FUSE - Fuse Values */ +#define FSB_FUSE_FUSE(x) (((uint32_t)(((uint32_t)(x)) << FSB_FUSE_FUSE_SHIFT)) & FSB_FUSE_FUSE_MASK) +/*! @} */ + +/* The count of FSB_FUSE */ +#define FSB_FUSE_COUNT (512U) + + +/*! + * @} + */ /* end of group FSB_Register_Masks */ + + +/* FSB - Peripheral instance base addresses */ +/** Peripheral FSB1 base address */ +#define FSB1_BASE (0x47510000u) +/** Peripheral FSB1 base pointer */ +#define FSB1 ((FSB_Type *)FSB1_BASE) +/** Array initializer of FSB peripheral base addresses */ +#define FSB_BASE_ADDRS { FSB1_BASE } +/** Array initializer of FSB peripheral base pointers */ +#define FSB_BASE_PTRS { FSB1 } + +/*! + * @} + */ /* end of group FSB_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- GPC_CPU_CTRL Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup GPC_CPU_CTRL_Peripheral_Access_Layer GPC_CPU_CTRL Peripheral Access Layer + * @{ + */ + +/** GPC_CPU_CTRL - Register Layout Typedef */ +typedef struct { + uint8_t RESERVED_0[4]; + __IO uint32_t CM_AUTHEN_CTRL; /**< CM Authentication Control, offset: 0x4 */ + uint8_t RESERVED_1[4]; + __IO uint32_t CM_MISC; /**< Miscellaneous, offset: 0xC */ + __IO uint32_t CM_MODE_CTRL; /**< CPU mode control, offset: 0x10 */ + __I uint32_t CM_MODE_STAT; /**< CM CPU mode Status, offset: 0x14 */ + __I uint32_t CM_PIN_STAT; /**< CM pin Status, offset: 0x18 */ + uint8_t RESERVED_2[228]; + __IO uint32_t CM_IRQ_WAKEUP_MASK_0; /**< CM IRQ0~31 wakeup mask, offset: 0x100 */ + __IO uint32_t CM_IRQ_WAKEUP_MASK_1; /**< CM IRQ32~63 wakeup mask, offset: 0x104 */ + __IO uint32_t CM_IRQ_WAKEUP_MASK_2; /**< CM IRQ64~95 wakeup mask, offset: 0x108 */ + __IO uint32_t CM_IRQ_WAKEUP_MASK_3; /**< CM IRQ96~127 wakeup mask, offset: 0x10C */ + __IO uint32_t CM_IRQ_WAKEUP_MASK_4; /**< CM IRQ128~159 wakeup mask, offset: 0x110 */ + __IO uint32_t CM_IRQ_WAKEUP_MASK_5; /**< CM IRQ160~191 wakeup mask, offset: 0x114 */ + __IO uint32_t CM_IRQ_WAKEUP_MASK_6; /**< CM IRQ192~223 wakeup mask, offset: 0x118 */ + __IO uint32_t CM_IRQ_WAKEUP_MASK_7; /**< CM IRQ224~255 wakeup mask, offset: 0x11C */ + uint8_t RESERVED_3[32]; + __IO uint32_t CM_NON_IRQ_WAKEUP_MASK; /**< CM non-IRQ wakeup mask, offset: 0x140 */ + uint8_t RESERVED_4[12]; + __I uint32_t CM_IRQ_WAKEUP_STAT_0; /**< CM IRQ0~31 wakeup status, offset: 0x150 */ + __I uint32_t CM_IRQ_WAKEUP_STAT_1; /**< CM IRQ32~63 wakeup status, offset: 0x154 */ + __I uint32_t CM_IRQ_WAKEUP_STAT_2; /**< CM IRQ64~95 wakeup status, offset: 0x158 */ + __I uint32_t CM_IRQ_WAKEUP_STAT_3; /**< CM IRQ96~127 wakeup status, offset: 0x15C */ + __I uint32_t CM_IRQ_WAKEUP_STAT_4; /**< CM IRQ128~159 wakeup status, offset: 0x160 */ + __I uint32_t CM_IRQ_WAKEUP_STAT_5; /**< CM IRQ160~191 wakeup status, offset: 0x164 */ + __I uint32_t CM_IRQ_WAKEUP_STAT_6; /**< CM IRQ192~223 wakeup status, offset: 0x168 */ + __I uint32_t CM_IRQ_WAKEUP_STAT_7; /**< CM IRQ224~255 wakeup status, offset: 0x16C */ + uint8_t RESERVED_5[32]; + __I uint32_t CM_NON_IRQ_WAKEUP_STAT; /**< CM non-IRQ wakeup status, offset: 0x190 */ + uint8_t RESERVED_6[108]; + __IO uint32_t CM_SLEEP_A55_HDSK_CTRL; /**< CM sleep A55_HDSK control, offset: 0x200 */ + uint8_t RESERVED_7[4]; + __IO uint32_t CM_SLEEP_SSAR_CTRL; /**< CM sleep SSAR control, offset: 0x208 */ + uint8_t RESERVED_8[4]; + __IO uint32_t CM_SLEEP_LPCG_CTRL; /**< CM sleep LPCG control, offset: 0x210 */ + uint8_t RESERVED_9[4]; + __IO uint32_t CM_SLEEP_PLL_CTRL; /**< CM sleep PLL control, offset: 0x218 */ + uint8_t RESERVED_10[4]; + __IO uint32_t CM_SLEEP_ISO_CTRL; /**< CM sleep isolation control, offset: 0x220 */ + uint8_t RESERVED_11[4]; + __IO uint32_t CM_SLEEP_MEM_CTRL; /**< CM sleep memory control, offset: 0x228 */ + uint8_t RESERVED_12[4]; + __IO uint32_t CM_SLEEP_RESET_CTRL; /**< CM sleep reset control, offset: 0x230 */ + uint8_t RESERVED_13[4]; + __IO uint32_t CM_SLEEP_POWER_CTRL; /**< CM sleep power control, offset: 0x238 */ + uint8_t RESERVED_14[4]; + __IO uint32_t CM_SLEEP_RSV2_CTRL; /**< CM sleep rsv2 control, offset: 0x240 */ + uint8_t RESERVED_15[68]; + __IO uint32_t CM_WAKEUP_RSV2_CTRL; /**< CM wakeup rsv2 control, offset: 0x288 */ + uint8_t RESERVED_16[4]; + __IO uint32_t CM_WAKEUP_POWER_CTRL; /**< CM wakeup power control, offset: 0x290 */ + uint8_t RESERVED_17[4]; + __IO uint32_t CM_WAKEUP_MEM_CTRL; /**< CM wakeup memory control, offset: 0x298 */ + uint8_t RESERVED_18[4]; + __IO uint32_t CM_WAKEUP_RESET_CTRL; /**< CM wakeup reset control, offset: 0x2A0 */ + uint8_t RESERVED_19[4]; + __IO uint32_t CM_WAKEUP_ISO_CTRL; /**< CM wakeup isolation control, offset: 0x2A8 */ + uint8_t RESERVED_20[4]; + __IO uint32_t CM_WAKEUP_PLL_CTRL; /**< CM wakeup PLL control, offset: 0x2B0 */ + uint8_t RESERVED_21[4]; + __IO uint32_t CM_WAKEUP_LPCG_CTRL; /**< CM wakeup LPCG control, offset: 0x2B8 */ + uint8_t RESERVED_22[4]; + __IO uint32_t CM_WAKEUP_MTR_CTRL; /**< CM wakeup MTR control, offset: 0x2C0 */ + uint8_t RESERVED_23[4]; + __IO uint32_t CM_WAKEUP_SSAR_CTRL; /**< CM wakeup SSAR control, offset: 0x2C8 */ + uint8_t RESERVED_24[4]; + __IO uint32_t CM_WAKEUP_A55_HDSK_CTRL; /**< CM wakeup A55_HDSK control, offset: 0x2D0 */ + uint8_t RESERVED_25[172]; + __IO uint32_t CM_SYS_SLEEP_CTRL; /**< CM system sleep control, offset: 0x380 */ + uint8_t RESERVED_26[12]; + __IO uint32_t CM_DEBUG; /**< CM debug, offset: 0x390 */ +} GPC_CPU_CTRL_Type; + +/* ---------------------------------------------------------------------------- + -- GPC_CPU_CTRL Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup GPC_CPU_CTRL_Register_Masks GPC_CPU_CTRL Register Masks + * @{ + */ + +/*! @name CM_AUTHEN_CTRL - CM Authentication Control */ +/*! @{ */ + +#define GPC_CPU_CTRL_CM_AUTHEN_CTRL_LOCK_CFG_MASK (0x80U) +#define GPC_CPU_CTRL_CM_AUTHEN_CTRL_LOCK_CFG_SHIFT (7U) +/*! LOCK_CFG - Configuration lock + * 0b0..The value of low power configuration fields are not locked. + * 0b1..The value of low power configuration fields are locked. It locks the CPUx_CM registers which are marked + * as "Locked by LOCK_CFG field" in the function field. + */ +#define GPC_CPU_CTRL_CM_AUTHEN_CTRL_LOCK_CFG(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_AUTHEN_CTRL_LOCK_CFG_SHIFT)) & GPC_CPU_CTRL_CM_AUTHEN_CTRL_LOCK_CFG_MASK) + +#define GPC_CPU_CTRL_CM_AUTHEN_CTRL_USER_MASK (0x100U) +#define GPC_CPU_CTRL_CM_AUTHEN_CTRL_USER_SHIFT (8U) +/*! USER - Allow user mode access + * 0b0..Allow only privilege mode to access CPU mode control registers + * 0b1..Allow both privilege and user mode to access CPU mode control registers + */ +#define GPC_CPU_CTRL_CM_AUTHEN_CTRL_USER(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_AUTHEN_CTRL_USER_SHIFT)) & GPC_CPU_CTRL_CM_AUTHEN_CTRL_USER_MASK) + +#define GPC_CPU_CTRL_CM_AUTHEN_CTRL_NONSECURE_MASK (0x200U) +#define GPC_CPU_CTRL_CM_AUTHEN_CTRL_NONSECURE_SHIFT (9U) +/*! NONSECURE - Allow non-secure mode access + * 0b0..Allow only secure mode to access CPU mode control + * 0b1..Allow both secure and non-secure mode to access CPU mode control registers + */ +#define GPC_CPU_CTRL_CM_AUTHEN_CTRL_NONSECURE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_AUTHEN_CTRL_NONSECURE_SHIFT)) & GPC_CPU_CTRL_CM_AUTHEN_CTRL_NONSECURE_MASK) + +#define GPC_CPU_CTRL_CM_AUTHEN_CTRL_LOCK_SETTING_MASK (0x800U) +#define GPC_CPU_CTRL_CM_AUTHEN_CTRL_LOCK_SETTING_SHIFT (11U) +/*! LOCK_SETTING - Lock NONSECURE and USER + * 0b0..NONSECURE and USER fields are not locked + * 0b1..NONSECURE and USER fields are locked + */ +#define GPC_CPU_CTRL_CM_AUTHEN_CTRL_LOCK_SETTING(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_AUTHEN_CTRL_LOCK_SETTING_SHIFT)) & GPC_CPU_CTRL_CM_AUTHEN_CTRL_LOCK_SETTING_MASK) + +#define GPC_CPU_CTRL_CM_AUTHEN_CTRL_LOCK_LIST_MASK (0x8000U) +#define GPC_CPU_CTRL_CM_AUTHEN_CTRL_LOCK_LIST_SHIFT (15U) +/*! LOCK_LIST - White list lock + * 0b0..WHITE_LIST is not locked + * 0b1..WHITE_LIST is locked + */ +#define GPC_CPU_CTRL_CM_AUTHEN_CTRL_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_AUTHEN_CTRL_LOCK_LIST_SHIFT)) & GPC_CPU_CTRL_CM_AUTHEN_CTRL_LOCK_LIST_MASK) + +#define GPC_CPU_CTRL_CM_AUTHEN_CTRL_WHITE_LIST_MASK (0xFFFF0000U) +#define GPC_CPU_CTRL_CM_AUTHEN_CTRL_WHITE_LIST_SHIFT (16U) +/*! WHITE_LIST - Domain ID white list */ +#define GPC_CPU_CTRL_CM_AUTHEN_CTRL_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_AUTHEN_CTRL_WHITE_LIST_SHIFT)) & GPC_CPU_CTRL_CM_AUTHEN_CTRL_WHITE_LIST_MASK) +/*! @} */ + +/*! @name CM_MISC - Miscellaneous */ +/*! @{ */ + +#define GPC_CPU_CTRL_CM_MISC_NMI_STAT_MASK (0x1U) +#define GPC_CPU_CTRL_CM_MISC_NMI_STAT_SHIFT (0U) +/*! NMI_STAT - Non-masked interrupt status + * 0b0..NMI is not asserted + * 0b1..NMI is asserted + */ +#define GPC_CPU_CTRL_CM_MISC_NMI_STAT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_MISC_NMI_STAT_SHIFT)) & GPC_CPU_CTRL_CM_MISC_NMI_STAT_MASK) + +#define GPC_CPU_CTRL_CM_MISC_SLEEP_HOLD_EN_MASK (0x2U) +#define GPC_CPU_CTRL_CM_MISC_SLEEP_HOLD_EN_SHIFT (1U) +/*! SLEEP_HOLD_EN - Allow cpu_sleep_hold_req assert during CPU low power status + * 0b0..Disable cpu_sleep_hold_req + * 0b1..Allow cpu_sleep_hold_req to assert during CPU low power status + */ +#define GPC_CPU_CTRL_CM_MISC_SLEEP_HOLD_EN(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_MISC_SLEEP_HOLD_EN_SHIFT)) & GPC_CPU_CTRL_CM_MISC_SLEEP_HOLD_EN_MASK) + +#define GPC_CPU_CTRL_CM_MISC_SLEEP_HOLD_STAT_MASK (0x4U) +#define GPC_CPU_CTRL_CM_MISC_SLEEP_HOLD_STAT_SHIFT (2U) +/*! SLEEP_HOLD_STAT - Status of cpu_sleep_hold_ack_b + * 0b0..CPU sleep hold is acknowledged + * 0b1..CPU is not in sleep hold + */ +#define GPC_CPU_CTRL_CM_MISC_SLEEP_HOLD_STAT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_MISC_SLEEP_HOLD_STAT_SHIFT)) & GPC_CPU_CTRL_CM_MISC_SLEEP_HOLD_STAT_MASK) + +#define GPC_CPU_CTRL_CM_MISC_GIC_WAKEUP_STAT_MASK (0x10U) +#define GPC_CPU_CTRL_CM_MISC_GIC_WAKEUP_STAT_SHIFT (4U) +/*! GIC_WAKEUP_STAT - GIC wakeup request status */ +#define GPC_CPU_CTRL_CM_MISC_GIC_WAKEUP_STAT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_MISC_GIC_WAKEUP_STAT_SHIFT)) & GPC_CPU_CTRL_CM_MISC_GIC_WAKEUP_STAT_MASK) + +#define GPC_CPU_CTRL_CM_MISC_IRQ_MUX_MASK (0x20U) +#define GPC_CPU_CTRL_CM_MISC_IRQ_MUX_SHIFT (5U) +/*! IRQ_MUX - IRQ select + * 0b0..From raw IRQ + * 0b1..From GIC + */ +#define GPC_CPU_CTRL_CM_MISC_IRQ_MUX(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_MISC_IRQ_MUX_SHIFT)) & GPC_CPU_CTRL_CM_MISC_IRQ_MUX_MASK) + +#define GPC_CPU_CTRL_CM_MISC_SW_WAKEUP_MASK (0x40U) +#define GPC_CPU_CTRL_CM_MISC_SW_WAKEUP_SHIFT (6U) +/*! SW_WAKEUP - software wakeup. Used for CPU hotplug. */ +#define GPC_CPU_CTRL_CM_MISC_SW_WAKEUP(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_MISC_SW_WAKEUP_SHIFT)) & GPC_CPU_CTRL_CM_MISC_SW_WAKEUP_MASK) +/*! @} */ + +/*! @name CM_MODE_CTRL - CPU mode control */ +/*! @{ */ + +#define GPC_CPU_CTRL_CM_MODE_CTRL_CPU_MODE_TARGET_MASK (0x3U) +#define GPC_CPU_CTRL_CM_MODE_CTRL_CPU_MODE_TARGET_SHIFT (0U) +/*! CPU_MODE_TARGET - The CPU mode the CPU platform should transit to on next sleep event + * 0b00..Stay in RUN mode + * 0b01..Transit to WAIT mode + * 0b10..Transit to STOP mode + * 0b11..Transit to SUSPEND mode + */ +#define GPC_CPU_CTRL_CM_MODE_CTRL_CPU_MODE_TARGET(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_MODE_CTRL_CPU_MODE_TARGET_SHIFT)) & GPC_CPU_CTRL_CM_MODE_CTRL_CPU_MODE_TARGET_MASK) +/*! @} */ + +/*! @name CM_MODE_STAT - CM CPU mode Status */ +/*! @{ */ + +#define GPC_CPU_CTRL_CM_MODE_STAT_CPU_MODE_CURRENT_MASK (0x3U) +#define GPC_CPU_CTRL_CM_MODE_STAT_CPU_MODE_CURRENT_SHIFT (0U) +/*! CPU_MODE_CURRENT - Current CPU mode + * 0b00..CPU is currently in RUN mode + * 0b01..CPU is currently in WAIT mode + * 0b10..CPU is currently in STOP mode + * 0b11..CPU is currently in SUSPEND mode + */ +#define GPC_CPU_CTRL_CM_MODE_STAT_CPU_MODE_CURRENT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_MODE_STAT_CPU_MODE_CURRENT_SHIFT)) & GPC_CPU_CTRL_CM_MODE_STAT_CPU_MODE_CURRENT_MASK) + +#define GPC_CPU_CTRL_CM_MODE_STAT_CPU_MODE_PREVIOUS_MASK (0xCU) +#define GPC_CPU_CTRL_CM_MODE_STAT_CPU_MODE_PREVIOUS_SHIFT (2U) +/*! CPU_MODE_PREVIOUS - Previous CPU mode + * 0b00..CPU was previously in RUN mode + * 0b01..CPU was previously in WAIT mode + * 0b10..CPU was previously in STOP mode + * 0b11..CPU was previously in SUSPEND mode + */ +#define GPC_CPU_CTRL_CM_MODE_STAT_CPU_MODE_PREVIOUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_MODE_STAT_CPU_MODE_PREVIOUS_SHIFT)) & GPC_CPU_CTRL_CM_MODE_STAT_CPU_MODE_PREVIOUS_MASK) + +#define GPC_CPU_CTRL_CM_MODE_STAT_SLEEP_TRANS_BUSY_MASK (0x100U) +#define GPC_CPU_CTRL_CM_MODE_STAT_SLEEP_TRANS_BUSY_SHIFT (8U) +/*! SLEEP_TRANS_BUSY - Busy on CPU mode transition of sleep, not include set point trans busy. */ +#define GPC_CPU_CTRL_CM_MODE_STAT_SLEEP_TRANS_BUSY(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_MODE_STAT_SLEEP_TRANS_BUSY_SHIFT)) & GPC_CPU_CTRL_CM_MODE_STAT_SLEEP_TRANS_BUSY_MASK) + +#define GPC_CPU_CTRL_CM_MODE_STAT_WAKEUP_TRANS_BUSY_MASK (0x200U) +#define GPC_CPU_CTRL_CM_MODE_STAT_WAKEUP_TRANS_BUSY_SHIFT (9U) +/*! WAKEUP_TRANS_BUSY - Busy on CPU mode transition of wakeup, not include set point trans busy. */ +#define GPC_CPU_CTRL_CM_MODE_STAT_WAKEUP_TRANS_BUSY(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_MODE_STAT_WAKEUP_TRANS_BUSY_SHIFT)) & GPC_CPU_CTRL_CM_MODE_STAT_WAKEUP_TRANS_BUSY_MASK) + +#define GPC_CPU_CTRL_CM_MODE_STAT_SLEEPING_IDLE_MASK (0x400U) +#define GPC_CPU_CTRL_CM_MODE_STAT_SLEEPING_IDLE_SHIFT (10U) +/*! SLEEPING_IDLE - Completed CPU mode and set point transition of sleep sequence, in a sleeping_idle state. */ +#define GPC_CPU_CTRL_CM_MODE_STAT_SLEEPING_IDLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_MODE_STAT_SLEEPING_IDLE_SHIFT)) & GPC_CPU_CTRL_CM_MODE_STAT_SLEEPING_IDLE_MASK) + +#define GPC_CPU_CTRL_CM_MODE_STAT_SLEEP_REQUEST_MASK (0x10000U) +#define GPC_CPU_CTRL_CM_MODE_STAT_SLEEP_REQUEST_SHIFT (16U) +/*! SLEEP_REQUEST - Status of sleep_request input port */ +#define GPC_CPU_CTRL_CM_MODE_STAT_SLEEP_REQUEST(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_MODE_STAT_SLEEP_REQUEST_SHIFT)) & GPC_CPU_CTRL_CM_MODE_STAT_SLEEP_REQUEST_MASK) + +#define GPC_CPU_CTRL_CM_MODE_STAT_WAKEUP_REQUEST_MASK (0x40000U) +#define GPC_CPU_CTRL_CM_MODE_STAT_WAKEUP_REQUEST_SHIFT (18U) +/*! WAKEUP_REQUEST - "ORed" of all unmasked IRQ in. */ +#define GPC_CPU_CTRL_CM_MODE_STAT_WAKEUP_REQUEST(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_MODE_STAT_WAKEUP_REQUEST_SHIFT)) & GPC_CPU_CTRL_CM_MODE_STAT_WAKEUP_REQUEST_MASK) + +#define GPC_CPU_CTRL_CM_MODE_STAT_FSM_STATE_MASK (0x1F000000U) +#define GPC_CPU_CTRL_CM_MODE_STAT_FSM_STATE_SHIFT (24U) +/*! FSM_STATE - CPU mode trans FSM state. */ +#define GPC_CPU_CTRL_CM_MODE_STAT_FSM_STATE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_MODE_STAT_FSM_STATE_SHIFT)) & GPC_CPU_CTRL_CM_MODE_STAT_FSM_STATE_MASK) +/*! @} */ + +/*! @name CM_PIN_STAT - CM pin Status */ +/*! @{ */ + +#define GPC_CPU_CTRL_CM_PIN_STAT_A55_HDSK_REQUEST_STAT_MASK (0x1U) +#define GPC_CPU_CTRL_CM_PIN_STAT_A55_HDSK_REQUEST_STAT_SHIFT (0U) +/*! A55_HDSK_REQUEST_STAT - cpu_mode_trans_a55_hdsk_request pin status */ +#define GPC_CPU_CTRL_CM_PIN_STAT_A55_HDSK_REQUEST_STAT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_PIN_STAT_A55_HDSK_REQUEST_STAT_SHIFT)) & GPC_CPU_CTRL_CM_PIN_STAT_A55_HDSK_REQUEST_STAT_MASK) + +#define GPC_CPU_CTRL_CM_PIN_STAT_SSAR_REQUEST_STAT_MASK (0x2U) +#define GPC_CPU_CTRL_CM_PIN_STAT_SSAR_REQUEST_STAT_SHIFT (1U) +/*! SSAR_REQUEST_STAT - cpu_mode_trans_ssar_request pin status */ +#define GPC_CPU_CTRL_CM_PIN_STAT_SSAR_REQUEST_STAT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_PIN_STAT_SSAR_REQUEST_STAT_SHIFT)) & GPC_CPU_CTRL_CM_PIN_STAT_SSAR_REQUEST_STAT_MASK) + +#define GPC_CPU_CTRL_CM_PIN_STAT_LPCG_REQUEST_STAT_MASK (0x4U) +#define GPC_CPU_CTRL_CM_PIN_STAT_LPCG_REQUEST_STAT_SHIFT (2U) +/*! LPCG_REQUEST_STAT - cpu_mode_trans_lpcg_request pin status */ +#define GPC_CPU_CTRL_CM_PIN_STAT_LPCG_REQUEST_STAT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_PIN_STAT_LPCG_REQUEST_STAT_SHIFT)) & GPC_CPU_CTRL_CM_PIN_STAT_LPCG_REQUEST_STAT_MASK) + +#define GPC_CPU_CTRL_CM_PIN_STAT_PLL_REQUEST_STAT_MASK (0x8U) +#define GPC_CPU_CTRL_CM_PIN_STAT_PLL_REQUEST_STAT_SHIFT (3U) +/*! PLL_REQUEST_STAT - cpu_mode_trans_pll_request pin status */ +#define GPC_CPU_CTRL_CM_PIN_STAT_PLL_REQUEST_STAT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_PIN_STAT_PLL_REQUEST_STAT_SHIFT)) & GPC_CPU_CTRL_CM_PIN_STAT_PLL_REQUEST_STAT_MASK) + +#define GPC_CPU_CTRL_CM_PIN_STAT_ISO_REQUEST_STAT_MASK (0x10U) +#define GPC_CPU_CTRL_CM_PIN_STAT_ISO_REQUEST_STAT_SHIFT (4U) +/*! ISO_REQUEST_STAT - cpu_mode_trans_iso_request pin status */ +#define GPC_CPU_CTRL_CM_PIN_STAT_ISO_REQUEST_STAT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_PIN_STAT_ISO_REQUEST_STAT_SHIFT)) & GPC_CPU_CTRL_CM_PIN_STAT_ISO_REQUEST_STAT_MASK) + +#define GPC_CPU_CTRL_CM_PIN_STAT_MEM_REQUEST_STAT_MASK (0x20U) +#define GPC_CPU_CTRL_CM_PIN_STAT_MEM_REQUEST_STAT_SHIFT (5U) +/*! MEM_REQUEST_STAT - cpu_mode_trans_mem_request pin status */ +#define GPC_CPU_CTRL_CM_PIN_STAT_MEM_REQUEST_STAT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_PIN_STAT_MEM_REQUEST_STAT_SHIFT)) & GPC_CPU_CTRL_CM_PIN_STAT_MEM_REQUEST_STAT_MASK) + +#define GPC_CPU_CTRL_CM_PIN_STAT_RESET_REQUEST_STAT_MASK (0x40U) +#define GPC_CPU_CTRL_CM_PIN_STAT_RESET_REQUEST_STAT_SHIFT (6U) +/*! RESET_REQUEST_STAT - cpu_mode_trans_reset_request pin status */ +#define GPC_CPU_CTRL_CM_PIN_STAT_RESET_REQUEST_STAT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_PIN_STAT_RESET_REQUEST_STAT_SHIFT)) & GPC_CPU_CTRL_CM_PIN_STAT_RESET_REQUEST_STAT_MASK) + +#define GPC_CPU_CTRL_CM_PIN_STAT_POWER_REQUEST_STAT_MASK (0x80U) +#define GPC_CPU_CTRL_CM_PIN_STAT_POWER_REQUEST_STAT_SHIFT (7U) +/*! POWER_REQUEST_STAT - cpu_mode_trans_power_request pin status */ +#define GPC_CPU_CTRL_CM_PIN_STAT_POWER_REQUEST_STAT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_PIN_STAT_POWER_REQUEST_STAT_SHIFT)) & GPC_CPU_CTRL_CM_PIN_STAT_POWER_REQUEST_STAT_MASK) + +#define GPC_CPU_CTRL_CM_PIN_STAT_MTR_REQUEST_STAT_MASK (0x100U) +#define GPC_CPU_CTRL_CM_PIN_STAT_MTR_REQUEST_STAT_SHIFT (8U) +/*! MTR_REQUEST_STAT - cpu_mode_trans_mtr_request pin status */ +#define GPC_CPU_CTRL_CM_PIN_STAT_MTR_REQUEST_STAT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_PIN_STAT_MTR_REQUEST_STAT_SHIFT)) & GPC_CPU_CTRL_CM_PIN_STAT_MTR_REQUEST_STAT_MASK) + +#define GPC_CPU_CTRL_CM_PIN_STAT_A55_HDSK_DONE_STAT_MASK (0x10000U) +#define GPC_CPU_CTRL_CM_PIN_STAT_A55_HDSK_DONE_STAT_SHIFT (16U) +/*! A55_HDSK_DONE_STAT - cpu_mode_trans_a55_hdsk_done pin status */ +#define GPC_CPU_CTRL_CM_PIN_STAT_A55_HDSK_DONE_STAT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_PIN_STAT_A55_HDSK_DONE_STAT_SHIFT)) & GPC_CPU_CTRL_CM_PIN_STAT_A55_HDSK_DONE_STAT_MASK) + +#define GPC_CPU_CTRL_CM_PIN_STAT_SSAR_DONE_STAT_MASK (0x20000U) +#define GPC_CPU_CTRL_CM_PIN_STAT_SSAR_DONE_STAT_SHIFT (17U) +/*! SSAR_DONE_STAT - cpu_mode_trans_ssar_done pin status */ +#define GPC_CPU_CTRL_CM_PIN_STAT_SSAR_DONE_STAT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_PIN_STAT_SSAR_DONE_STAT_SHIFT)) & GPC_CPU_CTRL_CM_PIN_STAT_SSAR_DONE_STAT_MASK) + +#define GPC_CPU_CTRL_CM_PIN_STAT_LPCG_DONE_STAT_MASK (0x40000U) +#define GPC_CPU_CTRL_CM_PIN_STAT_LPCG_DONE_STAT_SHIFT (18U) +/*! LPCG_DONE_STAT - cpu_mode_trans_lpcg_done pin status */ +#define GPC_CPU_CTRL_CM_PIN_STAT_LPCG_DONE_STAT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_PIN_STAT_LPCG_DONE_STAT_SHIFT)) & GPC_CPU_CTRL_CM_PIN_STAT_LPCG_DONE_STAT_MASK) + +#define GPC_CPU_CTRL_CM_PIN_STAT_PLL_DONE_STAT_MASK (0x80000U) +#define GPC_CPU_CTRL_CM_PIN_STAT_PLL_DONE_STAT_SHIFT (19U) +/*! PLL_DONE_STAT - cpu_mode_trans_pll_done pin status */ +#define GPC_CPU_CTRL_CM_PIN_STAT_PLL_DONE_STAT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_PIN_STAT_PLL_DONE_STAT_SHIFT)) & GPC_CPU_CTRL_CM_PIN_STAT_PLL_DONE_STAT_MASK) + +#define GPC_CPU_CTRL_CM_PIN_STAT_ISO_DONE_STAT_MASK (0x100000U) +#define GPC_CPU_CTRL_CM_PIN_STAT_ISO_DONE_STAT_SHIFT (20U) +/*! ISO_DONE_STAT - cpu_mode_trans_iso_done pin status */ +#define GPC_CPU_CTRL_CM_PIN_STAT_ISO_DONE_STAT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_PIN_STAT_ISO_DONE_STAT_SHIFT)) & GPC_CPU_CTRL_CM_PIN_STAT_ISO_DONE_STAT_MASK) + +#define GPC_CPU_CTRL_CM_PIN_STAT_MEM_DONE_STAT_MASK (0x200000U) +#define GPC_CPU_CTRL_CM_PIN_STAT_MEM_DONE_STAT_SHIFT (21U) +/*! MEM_DONE_STAT - cpu_mode_trans_mem_done pin status */ +#define GPC_CPU_CTRL_CM_PIN_STAT_MEM_DONE_STAT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_PIN_STAT_MEM_DONE_STAT_SHIFT)) & GPC_CPU_CTRL_CM_PIN_STAT_MEM_DONE_STAT_MASK) + +#define GPC_CPU_CTRL_CM_PIN_STAT_RESET_DONE_STAT_MASK (0x400000U) +#define GPC_CPU_CTRL_CM_PIN_STAT_RESET_DONE_STAT_SHIFT (22U) +/*! RESET_DONE_STAT - cpu_mode_trans_reset_done pin status */ +#define GPC_CPU_CTRL_CM_PIN_STAT_RESET_DONE_STAT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_PIN_STAT_RESET_DONE_STAT_SHIFT)) & GPC_CPU_CTRL_CM_PIN_STAT_RESET_DONE_STAT_MASK) + +#define GPC_CPU_CTRL_CM_PIN_STAT_POWER_DONE_STAT_MASK (0x800000U) +#define GPC_CPU_CTRL_CM_PIN_STAT_POWER_DONE_STAT_SHIFT (23U) +/*! POWER_DONE_STAT - cpu_mode_trans_power_done pin status */ +#define GPC_CPU_CTRL_CM_PIN_STAT_POWER_DONE_STAT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_PIN_STAT_POWER_DONE_STAT_SHIFT)) & GPC_CPU_CTRL_CM_PIN_STAT_POWER_DONE_STAT_MASK) + +#define GPC_CPU_CTRL_CM_PIN_STAT_MTR_DONE_STAT_MASK (0x1000000U) +#define GPC_CPU_CTRL_CM_PIN_STAT_MTR_DONE_STAT_SHIFT (24U) +/*! MTR_DONE_STAT - cpu_mode_trans_mtr_done pin status */ +#define GPC_CPU_CTRL_CM_PIN_STAT_MTR_DONE_STAT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_PIN_STAT_MTR_DONE_STAT_SHIFT)) & GPC_CPU_CTRL_CM_PIN_STAT_MTR_DONE_STAT_MASK) + +#define GPC_CPU_CTRL_CM_PIN_STAT_CPU_MODE_STAT_MASK (0x60000000U) +#define GPC_CPU_CTRL_CM_PIN_STAT_CPU_MODE_STAT_SHIFT (29U) +/*! CPU_MODE_STAT - cpu_power_mode pin status */ +#define GPC_CPU_CTRL_CM_PIN_STAT_CPU_MODE_STAT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_PIN_STAT_CPU_MODE_STAT_SHIFT)) & GPC_CPU_CTRL_CM_PIN_STAT_CPU_MODE_STAT_MASK) + +#define GPC_CPU_CTRL_CM_PIN_STAT_DEBUG_WAKEUP_ACK_STAT_MASK (0x80000000U) +#define GPC_CPU_CTRL_CM_PIN_STAT_DEBUG_WAKEUP_ACK_STAT_SHIFT (31U) +/*! DEBUG_WAKEUP_ACK_STAT - debug wakeup acknowledge pin status */ +#define GPC_CPU_CTRL_CM_PIN_STAT_DEBUG_WAKEUP_ACK_STAT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_PIN_STAT_DEBUG_WAKEUP_ACK_STAT_SHIFT)) & GPC_CPU_CTRL_CM_PIN_STAT_DEBUG_WAKEUP_ACK_STAT_MASK) +/*! @} */ + +/*! @name CM_IRQ_WAKEUP_MASK_0 - CM IRQ0~31 wakeup mask */ +/*! @{ */ + +#define GPC_CPU_CTRL_CM_IRQ_WAKEUP_MASK_0_IRQ_WAKEUP_MASK_0_31_MASK (0xFFFFFFFFU) +#define GPC_CPU_CTRL_CM_IRQ_WAKEUP_MASK_0_IRQ_WAKEUP_MASK_0_31_SHIFT (0U) +/*! IRQ_WAKEUP_MASK_0_31 - "1" means the IRQ cannot wakeup CPU platform */ +#define GPC_CPU_CTRL_CM_IRQ_WAKEUP_MASK_0_IRQ_WAKEUP_MASK_0_31(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_IRQ_WAKEUP_MASK_0_IRQ_WAKEUP_MASK_0_31_SHIFT)) & GPC_CPU_CTRL_CM_IRQ_WAKEUP_MASK_0_IRQ_WAKEUP_MASK_0_31_MASK) +/*! @} */ + +/*! @name CM_IRQ_WAKEUP_MASK_1 - CM IRQ32~63 wakeup mask */ +/*! @{ */ + +#define GPC_CPU_CTRL_CM_IRQ_WAKEUP_MASK_1_IRQ_WAKEUP_MASK_32_63_MASK (0xFFFFFFFFU) +#define GPC_CPU_CTRL_CM_IRQ_WAKEUP_MASK_1_IRQ_WAKEUP_MASK_32_63_SHIFT (0U) +/*! IRQ_WAKEUP_MASK_32_63 - "1" means the IRQ cannot wakeup CPU platform */ +#define GPC_CPU_CTRL_CM_IRQ_WAKEUP_MASK_1_IRQ_WAKEUP_MASK_32_63(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_IRQ_WAKEUP_MASK_1_IRQ_WAKEUP_MASK_32_63_SHIFT)) & GPC_CPU_CTRL_CM_IRQ_WAKEUP_MASK_1_IRQ_WAKEUP_MASK_32_63_MASK) +/*! @} */ + +/*! @name CM_IRQ_WAKEUP_MASK_2 - CM IRQ64~95 wakeup mask */ +/*! @{ */ + +#define GPC_CPU_CTRL_CM_IRQ_WAKEUP_MASK_2_IRQ_WAKEUP_MASK_64_95_MASK (0xFFFFFFFFU) +#define GPC_CPU_CTRL_CM_IRQ_WAKEUP_MASK_2_IRQ_WAKEUP_MASK_64_95_SHIFT (0U) +/*! IRQ_WAKEUP_MASK_64_95 - "1" means the IRQ cannot wakeup CPU platform */ +#define GPC_CPU_CTRL_CM_IRQ_WAKEUP_MASK_2_IRQ_WAKEUP_MASK_64_95(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_IRQ_WAKEUP_MASK_2_IRQ_WAKEUP_MASK_64_95_SHIFT)) & GPC_CPU_CTRL_CM_IRQ_WAKEUP_MASK_2_IRQ_WAKEUP_MASK_64_95_MASK) +/*! @} */ + +/*! @name CM_IRQ_WAKEUP_MASK_3 - CM IRQ96~127 wakeup mask */ +/*! @{ */ + +#define GPC_CPU_CTRL_CM_IRQ_WAKEUP_MASK_3_IRQ_WAKEUP_MASK_96_127_MASK (0xFFFFFFFFU) +#define GPC_CPU_CTRL_CM_IRQ_WAKEUP_MASK_3_IRQ_WAKEUP_MASK_96_127_SHIFT (0U) +/*! IRQ_WAKEUP_MASK_96_127 - "1" means the IRQ cannot wakeup CPU platform */ +#define GPC_CPU_CTRL_CM_IRQ_WAKEUP_MASK_3_IRQ_WAKEUP_MASK_96_127(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_IRQ_WAKEUP_MASK_3_IRQ_WAKEUP_MASK_96_127_SHIFT)) & GPC_CPU_CTRL_CM_IRQ_WAKEUP_MASK_3_IRQ_WAKEUP_MASK_96_127_MASK) +/*! @} */ + +/*! @name CM_IRQ_WAKEUP_MASK_4 - CM IRQ128~159 wakeup mask */ +/*! @{ */ + +#define GPC_CPU_CTRL_CM_IRQ_WAKEUP_MASK_4_IRQ_WAKEUP_MASK_128_159_MASK (0xFFFFFFFFU) +#define GPC_CPU_CTRL_CM_IRQ_WAKEUP_MASK_4_IRQ_WAKEUP_MASK_128_159_SHIFT (0U) +/*! IRQ_WAKEUP_MASK_128_159 - "1" means the IRQ cannot wakeup CPU platform */ +#define GPC_CPU_CTRL_CM_IRQ_WAKEUP_MASK_4_IRQ_WAKEUP_MASK_128_159(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_IRQ_WAKEUP_MASK_4_IRQ_WAKEUP_MASK_128_159_SHIFT)) & GPC_CPU_CTRL_CM_IRQ_WAKEUP_MASK_4_IRQ_WAKEUP_MASK_128_159_MASK) +/*! @} */ + +/*! @name CM_IRQ_WAKEUP_MASK_5 - CM IRQ160~191 wakeup mask */ +/*! @{ */ + +#define GPC_CPU_CTRL_CM_IRQ_WAKEUP_MASK_5_IRQ_WAKEUP_MASK_160_191_MASK (0xFFFFFFFFU) +#define GPC_CPU_CTRL_CM_IRQ_WAKEUP_MASK_5_IRQ_WAKEUP_MASK_160_191_SHIFT (0U) +/*! IRQ_WAKEUP_MASK_160_191 - "1" means the IRQ cannot wakeup CPU platform */ +#define GPC_CPU_CTRL_CM_IRQ_WAKEUP_MASK_5_IRQ_WAKEUP_MASK_160_191(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_IRQ_WAKEUP_MASK_5_IRQ_WAKEUP_MASK_160_191_SHIFT)) & GPC_CPU_CTRL_CM_IRQ_WAKEUP_MASK_5_IRQ_WAKEUP_MASK_160_191_MASK) +/*! @} */ + +/*! @name CM_IRQ_WAKEUP_MASK_6 - CM IRQ192~223 wakeup mask */ +/*! @{ */ + +#define GPC_CPU_CTRL_CM_IRQ_WAKEUP_MASK_6_IRQ_WAKEUP_MASK_192_223_MASK (0xFFFFFFFFU) +#define GPC_CPU_CTRL_CM_IRQ_WAKEUP_MASK_6_IRQ_WAKEUP_MASK_192_223_SHIFT (0U) +/*! IRQ_WAKEUP_MASK_192_223 - "1" means the IRQ cannot wakeup CPU platform */ +#define GPC_CPU_CTRL_CM_IRQ_WAKEUP_MASK_6_IRQ_WAKEUP_MASK_192_223(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_IRQ_WAKEUP_MASK_6_IRQ_WAKEUP_MASK_192_223_SHIFT)) & GPC_CPU_CTRL_CM_IRQ_WAKEUP_MASK_6_IRQ_WAKEUP_MASK_192_223_MASK) +/*! @} */ + +/*! @name CM_IRQ_WAKEUP_MASK_7 - CM IRQ224~255 wakeup mask */ +/*! @{ */ + +#define GPC_CPU_CTRL_CM_IRQ_WAKEUP_MASK_7_IRQ_WAKEUP_MASK_224_255_MASK (0xFFFFFFFFU) +#define GPC_CPU_CTRL_CM_IRQ_WAKEUP_MASK_7_IRQ_WAKEUP_MASK_224_255_SHIFT (0U) +/*! IRQ_WAKEUP_MASK_224_255 - "1" means the IRQ cannot wakeup CPU platform */ +#define GPC_CPU_CTRL_CM_IRQ_WAKEUP_MASK_7_IRQ_WAKEUP_MASK_224_255(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_IRQ_WAKEUP_MASK_7_IRQ_WAKEUP_MASK_224_255_SHIFT)) & GPC_CPU_CTRL_CM_IRQ_WAKEUP_MASK_7_IRQ_WAKEUP_MASK_224_255_MASK) +/*! @} */ + +/*! @name CM_NON_IRQ_WAKEUP_MASK - CM non-IRQ wakeup mask */ +/*! @{ */ + +#define GPC_CPU_CTRL_CM_NON_IRQ_WAKEUP_MASK_EVENT_WAKEUP_MASK_MASK (0x1U) +#define GPC_CPU_CTRL_CM_NON_IRQ_WAKEUP_MASK_EVENT_WAKEUP_MASK_SHIFT (0U) +/*! EVENT_WAKEUP_MASK - "1" means the event cannot wakeup CPU platform */ +#define GPC_CPU_CTRL_CM_NON_IRQ_WAKEUP_MASK_EVENT_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_NON_IRQ_WAKEUP_MASK_EVENT_WAKEUP_MASK_SHIFT)) & GPC_CPU_CTRL_CM_NON_IRQ_WAKEUP_MASK_EVENT_WAKEUP_MASK_MASK) + +#define GPC_CPU_CTRL_CM_NON_IRQ_WAKEUP_MASK_DEBUG_WAKEUP_MASK_MASK (0x2U) +#define GPC_CPU_CTRL_CM_NON_IRQ_WAKEUP_MASK_DEBUG_WAKEUP_MASK_SHIFT (1U) +/*! DEBUG_WAKEUP_MASK - "1" means the debug_wakeup_request cannot wakeup CPU platform */ +#define GPC_CPU_CTRL_CM_NON_IRQ_WAKEUP_MASK_DEBUG_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_NON_IRQ_WAKEUP_MASK_DEBUG_WAKEUP_MASK_SHIFT)) & GPC_CPU_CTRL_CM_NON_IRQ_WAKEUP_MASK_DEBUG_WAKEUP_MASK_MASK) +/*! @} */ + +/*! @name CM_IRQ_WAKEUP_STAT_0 - CM IRQ0~31 wakeup status */ +/*! @{ */ + +#define GPC_CPU_CTRL_CM_IRQ_WAKEUP_STAT_0_IRQ_WAKEUP_STAT_0_31_MASK (0xFFFFFFFFU) +#define GPC_CPU_CTRL_CM_IRQ_WAKEUP_STAT_0_IRQ_WAKEUP_STAT_0_31_SHIFT (0U) +/*! IRQ_WAKEUP_STAT_0_31 - IRQ status */ +#define GPC_CPU_CTRL_CM_IRQ_WAKEUP_STAT_0_IRQ_WAKEUP_STAT_0_31(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_IRQ_WAKEUP_STAT_0_IRQ_WAKEUP_STAT_0_31_SHIFT)) & GPC_CPU_CTRL_CM_IRQ_WAKEUP_STAT_0_IRQ_WAKEUP_STAT_0_31_MASK) +/*! @} */ + +/*! @name CM_IRQ_WAKEUP_STAT_1 - CM IRQ32~63 wakeup status */ +/*! @{ */ + +#define GPC_CPU_CTRL_CM_IRQ_WAKEUP_STAT_1_IRQ_WAKEUP_STAT_32_63_MASK (0xFFFFFFFFU) +#define GPC_CPU_CTRL_CM_IRQ_WAKEUP_STAT_1_IRQ_WAKEUP_STAT_32_63_SHIFT (0U) +/*! IRQ_WAKEUP_STAT_32_63 - IRQ status */ +#define GPC_CPU_CTRL_CM_IRQ_WAKEUP_STAT_1_IRQ_WAKEUP_STAT_32_63(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_IRQ_WAKEUP_STAT_1_IRQ_WAKEUP_STAT_32_63_SHIFT)) & GPC_CPU_CTRL_CM_IRQ_WAKEUP_STAT_1_IRQ_WAKEUP_STAT_32_63_MASK) +/*! @} */ + +/*! @name CM_IRQ_WAKEUP_STAT_2 - CM IRQ64~95 wakeup status */ +/*! @{ */ + +#define GPC_CPU_CTRL_CM_IRQ_WAKEUP_STAT_2_IRQ_WAKEUP_STAT_64_95_MASK (0xFFFFFFFFU) +#define GPC_CPU_CTRL_CM_IRQ_WAKEUP_STAT_2_IRQ_WAKEUP_STAT_64_95_SHIFT (0U) +/*! IRQ_WAKEUP_STAT_64_95 - IRQ status */ +#define GPC_CPU_CTRL_CM_IRQ_WAKEUP_STAT_2_IRQ_WAKEUP_STAT_64_95(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_IRQ_WAKEUP_STAT_2_IRQ_WAKEUP_STAT_64_95_SHIFT)) & GPC_CPU_CTRL_CM_IRQ_WAKEUP_STAT_2_IRQ_WAKEUP_STAT_64_95_MASK) +/*! @} */ + +/*! @name CM_IRQ_WAKEUP_STAT_3 - CM IRQ96~127 wakeup status */ +/*! @{ */ + +#define GPC_CPU_CTRL_CM_IRQ_WAKEUP_STAT_3_IRQ_WAKEUP_STAT_96_127_MASK (0xFFFFFFFFU) +#define GPC_CPU_CTRL_CM_IRQ_WAKEUP_STAT_3_IRQ_WAKEUP_STAT_96_127_SHIFT (0U) +/*! IRQ_WAKEUP_STAT_96_127 - IRQ status */ +#define GPC_CPU_CTRL_CM_IRQ_WAKEUP_STAT_3_IRQ_WAKEUP_STAT_96_127(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_IRQ_WAKEUP_STAT_3_IRQ_WAKEUP_STAT_96_127_SHIFT)) & GPC_CPU_CTRL_CM_IRQ_WAKEUP_STAT_3_IRQ_WAKEUP_STAT_96_127_MASK) +/*! @} */ + +/*! @name CM_IRQ_WAKEUP_STAT_4 - CM IRQ128~159 wakeup status */ +/*! @{ */ + +#define GPC_CPU_CTRL_CM_IRQ_WAKEUP_STAT_4_IRQ_WAKEUP_STAT_128_159_MASK (0xFFFFFFFFU) +#define GPC_CPU_CTRL_CM_IRQ_WAKEUP_STAT_4_IRQ_WAKEUP_STAT_128_159_SHIFT (0U) +/*! IRQ_WAKEUP_STAT_128_159 - IRQ status */ +#define GPC_CPU_CTRL_CM_IRQ_WAKEUP_STAT_4_IRQ_WAKEUP_STAT_128_159(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_IRQ_WAKEUP_STAT_4_IRQ_WAKEUP_STAT_128_159_SHIFT)) & GPC_CPU_CTRL_CM_IRQ_WAKEUP_STAT_4_IRQ_WAKEUP_STAT_128_159_MASK) +/*! @} */ + +/*! @name CM_IRQ_WAKEUP_STAT_5 - CM IRQ160~191 wakeup status */ +/*! @{ */ + +#define GPC_CPU_CTRL_CM_IRQ_WAKEUP_STAT_5_IRQ_WAKEUP_STAT_160_191_MASK (0xFFFFFFFFU) +#define GPC_CPU_CTRL_CM_IRQ_WAKEUP_STAT_5_IRQ_WAKEUP_STAT_160_191_SHIFT (0U) +/*! IRQ_WAKEUP_STAT_160_191 - IRQ status */ +#define GPC_CPU_CTRL_CM_IRQ_WAKEUP_STAT_5_IRQ_WAKEUP_STAT_160_191(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_IRQ_WAKEUP_STAT_5_IRQ_WAKEUP_STAT_160_191_SHIFT)) & GPC_CPU_CTRL_CM_IRQ_WAKEUP_STAT_5_IRQ_WAKEUP_STAT_160_191_MASK) +/*! @} */ + +/*! @name CM_IRQ_WAKEUP_STAT_6 - CM IRQ192~223 wakeup status */ +/*! @{ */ + +#define GPC_CPU_CTRL_CM_IRQ_WAKEUP_STAT_6_IRQ_WAKEUP_STAT_192_223_MASK (0xFFFFFFFFU) +#define GPC_CPU_CTRL_CM_IRQ_WAKEUP_STAT_6_IRQ_WAKEUP_STAT_192_223_SHIFT (0U) +/*! IRQ_WAKEUP_STAT_192_223 - IRQ status */ +#define GPC_CPU_CTRL_CM_IRQ_WAKEUP_STAT_6_IRQ_WAKEUP_STAT_192_223(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_IRQ_WAKEUP_STAT_6_IRQ_WAKEUP_STAT_192_223_SHIFT)) & GPC_CPU_CTRL_CM_IRQ_WAKEUP_STAT_6_IRQ_WAKEUP_STAT_192_223_MASK) +/*! @} */ + +/*! @name CM_IRQ_WAKEUP_STAT_7 - CM IRQ224~255 wakeup status */ +/*! @{ */ + +#define GPC_CPU_CTRL_CM_IRQ_WAKEUP_STAT_7_IRQ_WAKEUP_MASK_224_255_MASK (0xFFFFFFFFU) +#define GPC_CPU_CTRL_CM_IRQ_WAKEUP_STAT_7_IRQ_WAKEUP_MASK_224_255_SHIFT (0U) +/*! IRQ_WAKEUP_MASK_224_255 - IRQ status */ +#define GPC_CPU_CTRL_CM_IRQ_WAKEUP_STAT_7_IRQ_WAKEUP_MASK_224_255(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_IRQ_WAKEUP_STAT_7_IRQ_WAKEUP_MASK_224_255_SHIFT)) & GPC_CPU_CTRL_CM_IRQ_WAKEUP_STAT_7_IRQ_WAKEUP_MASK_224_255_MASK) +/*! @} */ + +/*! @name CM_NON_IRQ_WAKEUP_STAT - CM non-IRQ wakeup status */ +/*! @{ */ + +#define GPC_CPU_CTRL_CM_NON_IRQ_WAKEUP_STAT_EVENT_WAKEUP_STAT_MASK (0x1U) +#define GPC_CPU_CTRL_CM_NON_IRQ_WAKEUP_STAT_EVENT_WAKEUP_STAT_SHIFT (0U) +/*! EVENT_WAKEUP_STAT - Event wakeup status + * 0b0..No event wakeup is requested + * 0b1..Event wakeup is requested + */ +#define GPC_CPU_CTRL_CM_NON_IRQ_WAKEUP_STAT_EVENT_WAKEUP_STAT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_NON_IRQ_WAKEUP_STAT_EVENT_WAKEUP_STAT_SHIFT)) & GPC_CPU_CTRL_CM_NON_IRQ_WAKEUP_STAT_EVENT_WAKEUP_STAT_MASK) + +#define GPC_CPU_CTRL_CM_NON_IRQ_WAKEUP_STAT_DEBUG_WAKEUP_STAT_MASK (0x2U) +#define GPC_CPU_CTRL_CM_NON_IRQ_WAKEUP_STAT_DEBUG_WAKEUP_STAT_SHIFT (1U) +/*! DEBUG_WAKEUP_STAT - Debug wakeup status + * 0b0..No debug wakeup is requested + * 0b1..Debug wakeup is requested + */ +#define GPC_CPU_CTRL_CM_NON_IRQ_WAKEUP_STAT_DEBUG_WAKEUP_STAT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_NON_IRQ_WAKEUP_STAT_DEBUG_WAKEUP_STAT_SHIFT)) & GPC_CPU_CTRL_CM_NON_IRQ_WAKEUP_STAT_DEBUG_WAKEUP_STAT_MASK) +/*! @} */ + +/*! @name CM_SLEEP_A55_HDSK_CTRL - CM sleep A55_HDSK control */ +/*! @{ */ + +#define GPC_CPU_CTRL_CM_SLEEP_A55_HDSK_CTRL_STEP_CNT_MASK (0xFFFFFFU) +#define GPC_CPU_CTRL_CM_SLEEP_A55_HDSK_CTRL_STEP_CNT_SHIFT (0U) +/*! STEP_CNT - Step count, usage depends on CNT_MODE. */ +#define GPC_CPU_CTRL_CM_SLEEP_A55_HDSK_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_SLEEP_A55_HDSK_CTRL_STEP_CNT_SHIFT)) & GPC_CPU_CTRL_CM_SLEEP_A55_HDSK_CTRL_STEP_CNT_MASK) + +#define GPC_CPU_CTRL_CM_SLEEP_A55_HDSK_CTRL_CNT_MODE_MASK (0x30000000U) +#define GPC_CPU_CTRL_CM_SLEEP_A55_HDSK_CTRL_CNT_MODE_SHIFT (28U) +/*! CNT_MODE - Count mode + * 0b00..Counter disable mode: not use step counter, step completes once receiving step_done + * 0b01..Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT + * 0b10..Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes + * 0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value + */ +#define GPC_CPU_CTRL_CM_SLEEP_A55_HDSK_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_SLEEP_A55_HDSK_CTRL_CNT_MODE_SHIFT)) & GPC_CPU_CTRL_CM_SLEEP_A55_HDSK_CTRL_CNT_MODE_MASK) + +#define GPC_CPU_CTRL_CM_SLEEP_A55_HDSK_CTRL_DISABLE_MASK (0x80000000U) +#define GPC_CPU_CTRL_CM_SLEEP_A55_HDSK_CTRL_DISABLE_SHIFT (31U) +/*! DISABLE - Disable this step + * 0b0..This step is enabled. + * 0b1..This step is disabled. GPC will skip this step and not send any request. + */ +#define GPC_CPU_CTRL_CM_SLEEP_A55_HDSK_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_SLEEP_A55_HDSK_CTRL_DISABLE_SHIFT)) & GPC_CPU_CTRL_CM_SLEEP_A55_HDSK_CTRL_DISABLE_MASK) +/*! @} */ + +/*! @name CM_SLEEP_SSAR_CTRL - CM sleep SSAR control */ +/*! @{ */ + +#define GPC_CPU_CTRL_CM_SLEEP_SSAR_CTRL_STEP_CNT_MASK (0xFFFFFFU) +#define GPC_CPU_CTRL_CM_SLEEP_SSAR_CTRL_STEP_CNT_SHIFT (0U) +/*! STEP_CNT - Step count, usage depends on CNT_MODE. */ +#define GPC_CPU_CTRL_CM_SLEEP_SSAR_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_SLEEP_SSAR_CTRL_STEP_CNT_SHIFT)) & GPC_CPU_CTRL_CM_SLEEP_SSAR_CTRL_STEP_CNT_MASK) + +#define GPC_CPU_CTRL_CM_SLEEP_SSAR_CTRL_CNT_MODE_MASK (0x30000000U) +#define GPC_CPU_CTRL_CM_SLEEP_SSAR_CTRL_CNT_MODE_SHIFT (28U) +/*! CNT_MODE - Count mode + * 0b00..Counter disable mode: not use step counter, step completes once receiving step_done + * 0b01..Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT + * 0b10..Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes + * 0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value + */ +#define GPC_CPU_CTRL_CM_SLEEP_SSAR_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_SLEEP_SSAR_CTRL_CNT_MODE_SHIFT)) & GPC_CPU_CTRL_CM_SLEEP_SSAR_CTRL_CNT_MODE_MASK) + +#define GPC_CPU_CTRL_CM_SLEEP_SSAR_CTRL_DISABLE_MASK (0x80000000U) +#define GPC_CPU_CTRL_CM_SLEEP_SSAR_CTRL_DISABLE_SHIFT (31U) +/*! DISABLE - Disable this step + * 0b0..This step is enabled. + * 0b1..This step is disabled. GPC will skip this step and not send any request. + */ +#define GPC_CPU_CTRL_CM_SLEEP_SSAR_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_SLEEP_SSAR_CTRL_DISABLE_SHIFT)) & GPC_CPU_CTRL_CM_SLEEP_SSAR_CTRL_DISABLE_MASK) +/*! @} */ + +/*! @name CM_SLEEP_LPCG_CTRL - CM sleep LPCG control */ +/*! @{ */ + +#define GPC_CPU_CTRL_CM_SLEEP_LPCG_CTRL_STEP_CNT_MASK (0xFFFFFFU) +#define GPC_CPU_CTRL_CM_SLEEP_LPCG_CTRL_STEP_CNT_SHIFT (0U) +/*! STEP_CNT - Step count, usage depends on CNT_MODE */ +#define GPC_CPU_CTRL_CM_SLEEP_LPCG_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_SLEEP_LPCG_CTRL_STEP_CNT_SHIFT)) & GPC_CPU_CTRL_CM_SLEEP_LPCG_CTRL_STEP_CNT_MASK) + +#define GPC_CPU_CTRL_CM_SLEEP_LPCG_CTRL_CNT_MODE_MASK (0x30000000U) +#define GPC_CPU_CTRL_CM_SLEEP_LPCG_CTRL_CNT_MODE_SHIFT (28U) +/*! CNT_MODE - Count mode + * 0b00..Counter disable mode: not use step counter, step completes once receiving step_done + * 0b01..Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT + * 0b10..Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes + * 0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value + */ +#define GPC_CPU_CTRL_CM_SLEEP_LPCG_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_SLEEP_LPCG_CTRL_CNT_MODE_SHIFT)) & GPC_CPU_CTRL_CM_SLEEP_LPCG_CTRL_CNT_MODE_MASK) + +#define GPC_CPU_CTRL_CM_SLEEP_LPCG_CTRL_DISABLE_MASK (0x80000000U) +#define GPC_CPU_CTRL_CM_SLEEP_LPCG_CTRL_DISABLE_SHIFT (31U) +/*! DISABLE - Disable this step + * 0b0..This step is enabled. + * 0b1..This step is disabled. GPC will skip this step and not send any request. + */ +#define GPC_CPU_CTRL_CM_SLEEP_LPCG_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_SLEEP_LPCG_CTRL_DISABLE_SHIFT)) & GPC_CPU_CTRL_CM_SLEEP_LPCG_CTRL_DISABLE_MASK) +/*! @} */ + +/*! @name CM_SLEEP_PLL_CTRL - CM sleep PLL control */ +/*! @{ */ + +#define GPC_CPU_CTRL_CM_SLEEP_PLL_CTRL_STEP_CNT_MASK (0xFFFFFFU) +#define GPC_CPU_CTRL_CM_SLEEP_PLL_CTRL_STEP_CNT_SHIFT (0U) +/*! STEP_CNT - Step count, usage depends on CNT_MODE */ +#define GPC_CPU_CTRL_CM_SLEEP_PLL_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_SLEEP_PLL_CTRL_STEP_CNT_SHIFT)) & GPC_CPU_CTRL_CM_SLEEP_PLL_CTRL_STEP_CNT_MASK) + +#define GPC_CPU_CTRL_CM_SLEEP_PLL_CTRL_CNT_MODE_MASK (0x30000000U) +#define GPC_CPU_CTRL_CM_SLEEP_PLL_CTRL_CNT_MODE_SHIFT (28U) +/*! CNT_MODE - Count mode + * 0b00..Counter disable mode: not use step counter, step completes once receiving step_done + * 0b01..Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT + * 0b10..Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes + * 0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value + */ +#define GPC_CPU_CTRL_CM_SLEEP_PLL_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_SLEEP_PLL_CTRL_CNT_MODE_SHIFT)) & GPC_CPU_CTRL_CM_SLEEP_PLL_CTRL_CNT_MODE_MASK) + +#define GPC_CPU_CTRL_CM_SLEEP_PLL_CTRL_DISABLE_MASK (0x80000000U) +#define GPC_CPU_CTRL_CM_SLEEP_PLL_CTRL_DISABLE_SHIFT (31U) +/*! DISABLE - Disable this step + * 0b0..This step is enabled. + * 0b1..This step is disabled. GPC will skip this step and not send any request. + */ +#define GPC_CPU_CTRL_CM_SLEEP_PLL_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_SLEEP_PLL_CTRL_DISABLE_SHIFT)) & GPC_CPU_CTRL_CM_SLEEP_PLL_CTRL_DISABLE_MASK) +/*! @} */ + +/*! @name CM_SLEEP_ISO_CTRL - CM sleep isolation control */ +/*! @{ */ + +#define GPC_CPU_CTRL_CM_SLEEP_ISO_CTRL_STEP_CNT_MASK (0xFFFFFFU) +#define GPC_CPU_CTRL_CM_SLEEP_ISO_CTRL_STEP_CNT_SHIFT (0U) +/*! STEP_CNT - Step count, usage depends on CNT_MODE */ +#define GPC_CPU_CTRL_CM_SLEEP_ISO_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_SLEEP_ISO_CTRL_STEP_CNT_SHIFT)) & GPC_CPU_CTRL_CM_SLEEP_ISO_CTRL_STEP_CNT_MASK) + +#define GPC_CPU_CTRL_CM_SLEEP_ISO_CTRL_CNT_MODE_MASK (0x30000000U) +#define GPC_CPU_CTRL_CM_SLEEP_ISO_CTRL_CNT_MODE_SHIFT (28U) +/*! CNT_MODE - Count mode + * 0b00..Counter disable mode: not use step counter, step completes once receiving step_done + * 0b01..Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT + * 0b10..Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes + * 0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value + */ +#define GPC_CPU_CTRL_CM_SLEEP_ISO_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_SLEEP_ISO_CTRL_CNT_MODE_SHIFT)) & GPC_CPU_CTRL_CM_SLEEP_ISO_CTRL_CNT_MODE_MASK) + +#define GPC_CPU_CTRL_CM_SLEEP_ISO_CTRL_DISABLE_MASK (0x80000000U) +#define GPC_CPU_CTRL_CM_SLEEP_ISO_CTRL_DISABLE_SHIFT (31U) +/*! DISABLE - Disable this step + * 0b0..This step is enabled. + * 0b1..This step is disabled. GPC will skip this step and not send any request. + */ +#define GPC_CPU_CTRL_CM_SLEEP_ISO_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_SLEEP_ISO_CTRL_DISABLE_SHIFT)) & GPC_CPU_CTRL_CM_SLEEP_ISO_CTRL_DISABLE_MASK) +/*! @} */ + +/*! @name CM_SLEEP_MEM_CTRL - CM sleep memory control */ +/*! @{ */ + +#define GPC_CPU_CTRL_CM_SLEEP_MEM_CTRL_STEP_CNT_MASK (0xFFFFFFU) +#define GPC_CPU_CTRL_CM_SLEEP_MEM_CTRL_STEP_CNT_SHIFT (0U) +/*! STEP_CNT - Step count, usage depends on CNT_MODE */ +#define GPC_CPU_CTRL_CM_SLEEP_MEM_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_SLEEP_MEM_CTRL_STEP_CNT_SHIFT)) & GPC_CPU_CTRL_CM_SLEEP_MEM_CTRL_STEP_CNT_MASK) + +#define GPC_CPU_CTRL_CM_SLEEP_MEM_CTRL_CNT_MODE_MASK (0x30000000U) +#define GPC_CPU_CTRL_CM_SLEEP_MEM_CTRL_CNT_MODE_SHIFT (28U) +/*! CNT_MODE - Count mode + * 0b00..Counter disable mode: not use step counter, step completes once receiving step_done + * 0b01..Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT + * 0b10..Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes + * 0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value + */ +#define GPC_CPU_CTRL_CM_SLEEP_MEM_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_SLEEP_MEM_CTRL_CNT_MODE_SHIFT)) & GPC_CPU_CTRL_CM_SLEEP_MEM_CTRL_CNT_MODE_MASK) + +#define GPC_CPU_CTRL_CM_SLEEP_MEM_CTRL_DISABLE_MASK (0x80000000U) +#define GPC_CPU_CTRL_CM_SLEEP_MEM_CTRL_DISABLE_SHIFT (31U) +/*! DISABLE - Disable this step + * 0b0..This step is enabled. + * 0b1..This step is disabled. GPC will skip this step and not send any request. + */ +#define GPC_CPU_CTRL_CM_SLEEP_MEM_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_SLEEP_MEM_CTRL_DISABLE_SHIFT)) & GPC_CPU_CTRL_CM_SLEEP_MEM_CTRL_DISABLE_MASK) +/*! @} */ + +/*! @name CM_SLEEP_RESET_CTRL - CM sleep reset control */ +/*! @{ */ + +#define GPC_CPU_CTRL_CM_SLEEP_RESET_CTRL_STEP_CNT_MASK (0xFFFFFFU) +#define GPC_CPU_CTRL_CM_SLEEP_RESET_CTRL_STEP_CNT_SHIFT (0U) +/*! STEP_CNT - Step count, usage depends on CNT_MODE */ +#define GPC_CPU_CTRL_CM_SLEEP_RESET_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_SLEEP_RESET_CTRL_STEP_CNT_SHIFT)) & GPC_CPU_CTRL_CM_SLEEP_RESET_CTRL_STEP_CNT_MASK) + +#define GPC_CPU_CTRL_CM_SLEEP_RESET_CTRL_CNT_MODE_MASK (0x30000000U) +#define GPC_CPU_CTRL_CM_SLEEP_RESET_CTRL_CNT_MODE_SHIFT (28U) +/*! CNT_MODE - Count mode + * 0b00..Counter disable mode: not use step counter, step completes once receiving step_done + * 0b01..Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT + * 0b10..Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes + * 0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value + */ +#define GPC_CPU_CTRL_CM_SLEEP_RESET_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_SLEEP_RESET_CTRL_CNT_MODE_SHIFT)) & GPC_CPU_CTRL_CM_SLEEP_RESET_CTRL_CNT_MODE_MASK) + +#define GPC_CPU_CTRL_CM_SLEEP_RESET_CTRL_DISABLE_MASK (0x80000000U) +#define GPC_CPU_CTRL_CM_SLEEP_RESET_CTRL_DISABLE_SHIFT (31U) +/*! DISABLE - Disable this step + * 0b0..This step is enabled. + * 0b1..This step is disabled. GPC will skip this step and not send any request. + */ +#define GPC_CPU_CTRL_CM_SLEEP_RESET_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_SLEEP_RESET_CTRL_DISABLE_SHIFT)) & GPC_CPU_CTRL_CM_SLEEP_RESET_CTRL_DISABLE_MASK) +/*! @} */ + +/*! @name CM_SLEEP_POWER_CTRL - CM sleep power control */ +/*! @{ */ + +#define GPC_CPU_CTRL_CM_SLEEP_POWER_CTRL_STEP_CNT_MASK (0xFFFFFFU) +#define GPC_CPU_CTRL_CM_SLEEP_POWER_CTRL_STEP_CNT_SHIFT (0U) +/*! STEP_CNT - Step count, usage depends on CNT_MODE */ +#define GPC_CPU_CTRL_CM_SLEEP_POWER_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_SLEEP_POWER_CTRL_STEP_CNT_SHIFT)) & GPC_CPU_CTRL_CM_SLEEP_POWER_CTRL_STEP_CNT_MASK) + +#define GPC_CPU_CTRL_CM_SLEEP_POWER_CTRL_CNT_MODE_MASK (0x30000000U) +#define GPC_CPU_CTRL_CM_SLEEP_POWER_CTRL_CNT_MODE_SHIFT (28U) +/*! CNT_MODE - Count mode + * 0b00..Counter disable mode: not use step counter, step completes once receiving step_done + * 0b01..Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT + * 0b10..Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes + * 0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value + */ +#define GPC_CPU_CTRL_CM_SLEEP_POWER_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_SLEEP_POWER_CTRL_CNT_MODE_SHIFT)) & GPC_CPU_CTRL_CM_SLEEP_POWER_CTRL_CNT_MODE_MASK) + +#define GPC_CPU_CTRL_CM_SLEEP_POWER_CTRL_DISABLE_MASK (0x80000000U) +#define GPC_CPU_CTRL_CM_SLEEP_POWER_CTRL_DISABLE_SHIFT (31U) +/*! DISABLE - Disable this step + * 0b0..This step is enabled. + * 0b1..This step is disabled. GPC will skip this step and not send any request. + */ +#define GPC_CPU_CTRL_CM_SLEEP_POWER_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_SLEEP_POWER_CTRL_DISABLE_SHIFT)) & GPC_CPU_CTRL_CM_SLEEP_POWER_CTRL_DISABLE_MASK) +/*! @} */ + +/*! @name CM_SLEEP_RSV2_CTRL - CM sleep rsv2 control */ +/*! @{ */ + +#define GPC_CPU_CTRL_CM_SLEEP_RSV2_CTRL_STEP_CNT_MASK (0xFFFFFFU) +#define GPC_CPU_CTRL_CM_SLEEP_RSV2_CTRL_STEP_CNT_SHIFT (0U) +/*! STEP_CNT - Step count, usage depends on CNT_MODE */ +#define GPC_CPU_CTRL_CM_SLEEP_RSV2_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_SLEEP_RSV2_CTRL_STEP_CNT_SHIFT)) & GPC_CPU_CTRL_CM_SLEEP_RSV2_CTRL_STEP_CNT_MASK) + +#define GPC_CPU_CTRL_CM_SLEEP_RSV2_CTRL_CNT_MODE_MASK (0x30000000U) +#define GPC_CPU_CTRL_CM_SLEEP_RSV2_CTRL_CNT_MODE_SHIFT (28U) +/*! CNT_MODE - Count mode + * 0b00..Counter disable mode: not use step counter, step completes once receiving step_done + * 0b01..Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT + * 0b10..Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes + * 0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value + */ +#define GPC_CPU_CTRL_CM_SLEEP_RSV2_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_SLEEP_RSV2_CTRL_CNT_MODE_SHIFT)) & GPC_CPU_CTRL_CM_SLEEP_RSV2_CTRL_CNT_MODE_MASK) + +#define GPC_CPU_CTRL_CM_SLEEP_RSV2_CTRL_DISABLE_MASK (0x80000000U) +#define GPC_CPU_CTRL_CM_SLEEP_RSV2_CTRL_DISABLE_SHIFT (31U) +/*! DISABLE - Disable this step + * 0b0..This step is enabled. + * 0b1..This step is disabled. GPC will skip this step and not send any request. + */ +#define GPC_CPU_CTRL_CM_SLEEP_RSV2_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_SLEEP_RSV2_CTRL_DISABLE_SHIFT)) & GPC_CPU_CTRL_CM_SLEEP_RSV2_CTRL_DISABLE_MASK) +/*! @} */ + +/*! @name CM_WAKEUP_RSV2_CTRL - CM wakeup rsv2 control */ +/*! @{ */ + +#define GPC_CPU_CTRL_CM_WAKEUP_RSV2_CTRL_STEP_CNT_MASK (0xFFFFFFU) +#define GPC_CPU_CTRL_CM_WAKEUP_RSV2_CTRL_STEP_CNT_SHIFT (0U) +/*! STEP_CNT - Step count, usage depends on CNT_MODE */ +#define GPC_CPU_CTRL_CM_WAKEUP_RSV2_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_WAKEUP_RSV2_CTRL_STEP_CNT_SHIFT)) & GPC_CPU_CTRL_CM_WAKEUP_RSV2_CTRL_STEP_CNT_MASK) + +#define GPC_CPU_CTRL_CM_WAKEUP_RSV2_CTRL_CNT_MODE_MASK (0x30000000U) +#define GPC_CPU_CTRL_CM_WAKEUP_RSV2_CTRL_CNT_MODE_SHIFT (28U) +/*! CNT_MODE - Count mode + * 0b00..Counter disable mode: not use step counter, step completes once receiving step_done + * 0b01..Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT + * 0b10..Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes + * 0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value + */ +#define GPC_CPU_CTRL_CM_WAKEUP_RSV2_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_WAKEUP_RSV2_CTRL_CNT_MODE_SHIFT)) & GPC_CPU_CTRL_CM_WAKEUP_RSV2_CTRL_CNT_MODE_MASK) + +#define GPC_CPU_CTRL_CM_WAKEUP_RSV2_CTRL_DISABLE_MASK (0x80000000U) +#define GPC_CPU_CTRL_CM_WAKEUP_RSV2_CTRL_DISABLE_SHIFT (31U) +/*! DISABLE - Disable this step + * 0b0..This step is enabled. + * 0b1..This step is disabled. GPC will skip this step and not send any request. + */ +#define GPC_CPU_CTRL_CM_WAKEUP_RSV2_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_WAKEUP_RSV2_CTRL_DISABLE_SHIFT)) & GPC_CPU_CTRL_CM_WAKEUP_RSV2_CTRL_DISABLE_MASK) +/*! @} */ + +/*! @name CM_WAKEUP_POWER_CTRL - CM wakeup power control */ +/*! @{ */ + +#define GPC_CPU_CTRL_CM_WAKEUP_POWER_CTRL_STEP_CNT_MASK (0xFFFFFFU) +#define GPC_CPU_CTRL_CM_WAKEUP_POWER_CTRL_STEP_CNT_SHIFT (0U) +/*! STEP_CNT - Step count, usage depends on CNT_MODE */ +#define GPC_CPU_CTRL_CM_WAKEUP_POWER_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_WAKEUP_POWER_CTRL_STEP_CNT_SHIFT)) & GPC_CPU_CTRL_CM_WAKEUP_POWER_CTRL_STEP_CNT_MASK) + +#define GPC_CPU_CTRL_CM_WAKEUP_POWER_CTRL_CNT_MODE_MASK (0x30000000U) +#define GPC_CPU_CTRL_CM_WAKEUP_POWER_CTRL_CNT_MODE_SHIFT (28U) +/*! CNT_MODE - Count mode + * 0b00..Counter disable mode: not use step counter, step completes once receiving step_done + * 0b01..Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT + * 0b10..Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes + * 0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value + */ +#define GPC_CPU_CTRL_CM_WAKEUP_POWER_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_WAKEUP_POWER_CTRL_CNT_MODE_SHIFT)) & GPC_CPU_CTRL_CM_WAKEUP_POWER_CTRL_CNT_MODE_MASK) + +#define GPC_CPU_CTRL_CM_WAKEUP_POWER_CTRL_DISABLE_MASK (0x80000000U) +#define GPC_CPU_CTRL_CM_WAKEUP_POWER_CTRL_DISABLE_SHIFT (31U) +/*! DISABLE - Disable this step + * 0b0..This step is enabled. + * 0b1..This step is disabled. GPC will skip this step and not send any request. + */ +#define GPC_CPU_CTRL_CM_WAKEUP_POWER_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_WAKEUP_POWER_CTRL_DISABLE_SHIFT)) & GPC_CPU_CTRL_CM_WAKEUP_POWER_CTRL_DISABLE_MASK) +/*! @} */ + +/*! @name CM_WAKEUP_MEM_CTRL - CM wakeup memory control */ +/*! @{ */ + +#define GPC_CPU_CTRL_CM_WAKEUP_MEM_CTRL_STEP_CNT_MASK (0xFFFFFFU) +#define GPC_CPU_CTRL_CM_WAKEUP_MEM_CTRL_STEP_CNT_SHIFT (0U) +/*! STEP_CNT - Step count, usage depends on CNT_MODE */ +#define GPC_CPU_CTRL_CM_WAKEUP_MEM_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_WAKEUP_MEM_CTRL_STEP_CNT_SHIFT)) & GPC_CPU_CTRL_CM_WAKEUP_MEM_CTRL_STEP_CNT_MASK) + +#define GPC_CPU_CTRL_CM_WAKEUP_MEM_CTRL_CNT_MODE_MASK (0x30000000U) +#define GPC_CPU_CTRL_CM_WAKEUP_MEM_CTRL_CNT_MODE_SHIFT (28U) +/*! CNT_MODE - Count mode + * 0b00..Counter disable mode: not use step counter, step completes once receiving step_done + * 0b01..Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT + * 0b10..Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes + * 0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value + */ +#define GPC_CPU_CTRL_CM_WAKEUP_MEM_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_WAKEUP_MEM_CTRL_CNT_MODE_SHIFT)) & GPC_CPU_CTRL_CM_WAKEUP_MEM_CTRL_CNT_MODE_MASK) + +#define GPC_CPU_CTRL_CM_WAKEUP_MEM_CTRL_DISABLE_MASK (0x80000000U) +#define GPC_CPU_CTRL_CM_WAKEUP_MEM_CTRL_DISABLE_SHIFT (31U) +/*! DISABLE - Disable this step + * 0b0..This step is enabled. + * 0b1..This step is disabled. GPC will skip this step and not send any request. + */ +#define GPC_CPU_CTRL_CM_WAKEUP_MEM_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_WAKEUP_MEM_CTRL_DISABLE_SHIFT)) & GPC_CPU_CTRL_CM_WAKEUP_MEM_CTRL_DISABLE_MASK) +/*! @} */ + +/*! @name CM_WAKEUP_RESET_CTRL - CM wakeup reset control */ +/*! @{ */ + +#define GPC_CPU_CTRL_CM_WAKEUP_RESET_CTRL_STEP_CNT_MASK (0xFFFFFFU) +#define GPC_CPU_CTRL_CM_WAKEUP_RESET_CTRL_STEP_CNT_SHIFT (0U) +/*! STEP_CNT - Step count, usage depends on CNT_MODE */ +#define GPC_CPU_CTRL_CM_WAKEUP_RESET_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_WAKEUP_RESET_CTRL_STEP_CNT_SHIFT)) & GPC_CPU_CTRL_CM_WAKEUP_RESET_CTRL_STEP_CNT_MASK) + +#define GPC_CPU_CTRL_CM_WAKEUP_RESET_CTRL_CNT_MODE_MASK (0x30000000U) +#define GPC_CPU_CTRL_CM_WAKEUP_RESET_CTRL_CNT_MODE_SHIFT (28U) +/*! CNT_MODE - Count mode + * 0b00..Counter disable mode: not use step counter, step completes once receiving step_done + * 0b01..Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT + * 0b10..Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes + * 0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value + */ +#define GPC_CPU_CTRL_CM_WAKEUP_RESET_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_WAKEUP_RESET_CTRL_CNT_MODE_SHIFT)) & GPC_CPU_CTRL_CM_WAKEUP_RESET_CTRL_CNT_MODE_MASK) + +#define GPC_CPU_CTRL_CM_WAKEUP_RESET_CTRL_DISABLE_MASK (0x80000000U) +#define GPC_CPU_CTRL_CM_WAKEUP_RESET_CTRL_DISABLE_SHIFT (31U) +/*! DISABLE - Disable this step + * 0b0..This step is enabled. + * 0b1..This step is disabled. GPC will skip this step and not send any request. + */ +#define GPC_CPU_CTRL_CM_WAKEUP_RESET_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_WAKEUP_RESET_CTRL_DISABLE_SHIFT)) & GPC_CPU_CTRL_CM_WAKEUP_RESET_CTRL_DISABLE_MASK) +/*! @} */ + +/*! @name CM_WAKEUP_ISO_CTRL - CM wakeup isolation control */ +/*! @{ */ + +#define GPC_CPU_CTRL_CM_WAKEUP_ISO_CTRL_STEP_CNT_MASK (0xFFFFFFU) +#define GPC_CPU_CTRL_CM_WAKEUP_ISO_CTRL_STEP_CNT_SHIFT (0U) +/*! STEP_CNT - Step count, usage depends on CNT_MODE */ +#define GPC_CPU_CTRL_CM_WAKEUP_ISO_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_WAKEUP_ISO_CTRL_STEP_CNT_SHIFT)) & GPC_CPU_CTRL_CM_WAKEUP_ISO_CTRL_STEP_CNT_MASK) + +#define GPC_CPU_CTRL_CM_WAKEUP_ISO_CTRL_CNT_MODE_MASK (0x30000000U) +#define GPC_CPU_CTRL_CM_WAKEUP_ISO_CTRL_CNT_MODE_SHIFT (28U) +/*! CNT_MODE - Count mode + * 0b00..Counter disable mode: not use step counter, step completes once receiving step_done + * 0b01..Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT + * 0b10..Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes + * 0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value + */ +#define GPC_CPU_CTRL_CM_WAKEUP_ISO_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_WAKEUP_ISO_CTRL_CNT_MODE_SHIFT)) & GPC_CPU_CTRL_CM_WAKEUP_ISO_CTRL_CNT_MODE_MASK) + +#define GPC_CPU_CTRL_CM_WAKEUP_ISO_CTRL_DISABLE_MASK (0x80000000U) +#define GPC_CPU_CTRL_CM_WAKEUP_ISO_CTRL_DISABLE_SHIFT (31U) +/*! DISABLE - Disable this step + * 0b0..This step is enabled. + * 0b1..This step is disabled. GPC will skip this step and not send any request. + */ +#define GPC_CPU_CTRL_CM_WAKEUP_ISO_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_WAKEUP_ISO_CTRL_DISABLE_SHIFT)) & GPC_CPU_CTRL_CM_WAKEUP_ISO_CTRL_DISABLE_MASK) +/*! @} */ + +/*! @name CM_WAKEUP_PLL_CTRL - CM wakeup PLL control */ +/*! @{ */ + +#define GPC_CPU_CTRL_CM_WAKEUP_PLL_CTRL_STEP_CNT_MASK (0xFFFFFFU) +#define GPC_CPU_CTRL_CM_WAKEUP_PLL_CTRL_STEP_CNT_SHIFT (0U) +/*! STEP_CNT - Step count, usage depends on CNT_MODE */ +#define GPC_CPU_CTRL_CM_WAKEUP_PLL_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_WAKEUP_PLL_CTRL_STEP_CNT_SHIFT)) & GPC_CPU_CTRL_CM_WAKEUP_PLL_CTRL_STEP_CNT_MASK) + +#define GPC_CPU_CTRL_CM_WAKEUP_PLL_CTRL_CNT_MODE_MASK (0x30000000U) +#define GPC_CPU_CTRL_CM_WAKEUP_PLL_CTRL_CNT_MODE_SHIFT (28U) +/*! CNT_MODE - Count mode + * 0b00..Counter disable mode: not use step counter, step completes once receiving step_done + * 0b01..Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT + * 0b10..Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes + * 0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value + */ +#define GPC_CPU_CTRL_CM_WAKEUP_PLL_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_WAKEUP_PLL_CTRL_CNT_MODE_SHIFT)) & GPC_CPU_CTRL_CM_WAKEUP_PLL_CTRL_CNT_MODE_MASK) + +#define GPC_CPU_CTRL_CM_WAKEUP_PLL_CTRL_DISABLE_MASK (0x80000000U) +#define GPC_CPU_CTRL_CM_WAKEUP_PLL_CTRL_DISABLE_SHIFT (31U) +/*! DISABLE - Disable this step + * 0b0..This step is enabled. + * 0b1..This step is disabled. GPC will skip this step and not send any request. + */ +#define GPC_CPU_CTRL_CM_WAKEUP_PLL_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_WAKEUP_PLL_CTRL_DISABLE_SHIFT)) & GPC_CPU_CTRL_CM_WAKEUP_PLL_CTRL_DISABLE_MASK) +/*! @} */ + +/*! @name CM_WAKEUP_LPCG_CTRL - CM wakeup LPCG control */ +/*! @{ */ + +#define GPC_CPU_CTRL_CM_WAKEUP_LPCG_CTRL_STEP_CNT_MASK (0xFFFFFFU) +#define GPC_CPU_CTRL_CM_WAKEUP_LPCG_CTRL_STEP_CNT_SHIFT (0U) +/*! STEP_CNT - Step count, usage depends on CNT_MODE */ +#define GPC_CPU_CTRL_CM_WAKEUP_LPCG_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_WAKEUP_LPCG_CTRL_STEP_CNT_SHIFT)) & GPC_CPU_CTRL_CM_WAKEUP_LPCG_CTRL_STEP_CNT_MASK) + +#define GPC_CPU_CTRL_CM_WAKEUP_LPCG_CTRL_CNT_MODE_MASK (0x30000000U) +#define GPC_CPU_CTRL_CM_WAKEUP_LPCG_CTRL_CNT_MODE_SHIFT (28U) +/*! CNT_MODE - Count mode + * 0b00..Counter disable mode: not use step counter, step completes once receiving step_done + * 0b01..Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT + * 0b10..Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes + * 0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value + */ +#define GPC_CPU_CTRL_CM_WAKEUP_LPCG_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_WAKEUP_LPCG_CTRL_CNT_MODE_SHIFT)) & GPC_CPU_CTRL_CM_WAKEUP_LPCG_CTRL_CNT_MODE_MASK) + +#define GPC_CPU_CTRL_CM_WAKEUP_LPCG_CTRL_DISABLE_MASK (0x80000000U) +#define GPC_CPU_CTRL_CM_WAKEUP_LPCG_CTRL_DISABLE_SHIFT (31U) +/*! DISABLE - Disable this step + * 0b0..This step is enabled. + * 0b1..This step is disabled. GPC will skip this step and not send any request. + */ +#define GPC_CPU_CTRL_CM_WAKEUP_LPCG_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_WAKEUP_LPCG_CTRL_DISABLE_SHIFT)) & GPC_CPU_CTRL_CM_WAKEUP_LPCG_CTRL_DISABLE_MASK) +/*! @} */ + +/*! @name CM_WAKEUP_MTR_CTRL - CM wakeup MTR control */ +/*! @{ */ + +#define GPC_CPU_CTRL_CM_WAKEUP_MTR_CTRL_STEP_CNT_MASK (0xFFFFFFU) +#define GPC_CPU_CTRL_CM_WAKEUP_MTR_CTRL_STEP_CNT_SHIFT (0U) +/*! STEP_CNT - Step count, usage depends on CNT_MODE */ +#define GPC_CPU_CTRL_CM_WAKEUP_MTR_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_WAKEUP_MTR_CTRL_STEP_CNT_SHIFT)) & GPC_CPU_CTRL_CM_WAKEUP_MTR_CTRL_STEP_CNT_MASK) + +#define GPC_CPU_CTRL_CM_WAKEUP_MTR_CTRL_CNT_MODE_MASK (0x30000000U) +#define GPC_CPU_CTRL_CM_WAKEUP_MTR_CTRL_CNT_MODE_SHIFT (28U) +/*! CNT_MODE - Count mode + * 0b00..Counter disable mode: not use step counter, step completes once receiving step_done + * 0b01..Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT + * 0b10..Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes + * 0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value + */ +#define GPC_CPU_CTRL_CM_WAKEUP_MTR_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_WAKEUP_MTR_CTRL_CNT_MODE_SHIFT)) & GPC_CPU_CTRL_CM_WAKEUP_MTR_CTRL_CNT_MODE_MASK) + +#define GPC_CPU_CTRL_CM_WAKEUP_MTR_CTRL_DISABLE_MASK (0x80000000U) +#define GPC_CPU_CTRL_CM_WAKEUP_MTR_CTRL_DISABLE_SHIFT (31U) +/*! DISABLE - Disable this step + * 0b0..This step is enabled. + * 0b1..This step is disabled. GPC will skip this step and not send any request. + */ +#define GPC_CPU_CTRL_CM_WAKEUP_MTR_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_WAKEUP_MTR_CTRL_DISABLE_SHIFT)) & GPC_CPU_CTRL_CM_WAKEUP_MTR_CTRL_DISABLE_MASK) +/*! @} */ + +/*! @name CM_WAKEUP_SSAR_CTRL - CM wakeup SSAR control */ +/*! @{ */ + +#define GPC_CPU_CTRL_CM_WAKEUP_SSAR_CTRL_STEP_CNT_MASK (0xFFFFFFU) +#define GPC_CPU_CTRL_CM_WAKEUP_SSAR_CTRL_STEP_CNT_SHIFT (0U) +/*! STEP_CNT - Step count, usage depends on CNT_MODE */ +#define GPC_CPU_CTRL_CM_WAKEUP_SSAR_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_WAKEUP_SSAR_CTRL_STEP_CNT_SHIFT)) & GPC_CPU_CTRL_CM_WAKEUP_SSAR_CTRL_STEP_CNT_MASK) + +#define GPC_CPU_CTRL_CM_WAKEUP_SSAR_CTRL_CNT_MODE_MASK (0x30000000U) +#define GPC_CPU_CTRL_CM_WAKEUP_SSAR_CTRL_CNT_MODE_SHIFT (28U) +/*! CNT_MODE - Count mode + * 0b00..Counter disable mode: not use step counter, step completes once receiving step_done + * 0b01..Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT + * 0b10..Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes + * 0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value + */ +#define GPC_CPU_CTRL_CM_WAKEUP_SSAR_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_WAKEUP_SSAR_CTRL_CNT_MODE_SHIFT)) & GPC_CPU_CTRL_CM_WAKEUP_SSAR_CTRL_CNT_MODE_MASK) + +#define GPC_CPU_CTRL_CM_WAKEUP_SSAR_CTRL_DISABLE_MASK (0x80000000U) +#define GPC_CPU_CTRL_CM_WAKEUP_SSAR_CTRL_DISABLE_SHIFT (31U) +/*! DISABLE - Disable this step + * 0b0..This step is enabled. + * 0b1..This step is disabled. GPC will skip this step and not send any request. + */ +#define GPC_CPU_CTRL_CM_WAKEUP_SSAR_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_WAKEUP_SSAR_CTRL_DISABLE_SHIFT)) & GPC_CPU_CTRL_CM_WAKEUP_SSAR_CTRL_DISABLE_MASK) +/*! @} */ + +/*! @name CM_WAKEUP_A55_HDSK_CTRL - CM wakeup A55_HDSK control */ +/*! @{ */ + +#define GPC_CPU_CTRL_CM_WAKEUP_A55_HDSK_CTRL_STEP_CNT_MASK (0xFFFFFFU) +#define GPC_CPU_CTRL_CM_WAKEUP_A55_HDSK_CTRL_STEP_CNT_SHIFT (0U) +/*! STEP_CNT - Step count, usage depends on CNT_MODE */ +#define GPC_CPU_CTRL_CM_WAKEUP_A55_HDSK_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_WAKEUP_A55_HDSK_CTRL_STEP_CNT_SHIFT)) & GPC_CPU_CTRL_CM_WAKEUP_A55_HDSK_CTRL_STEP_CNT_MASK) + +#define GPC_CPU_CTRL_CM_WAKEUP_A55_HDSK_CTRL_CNT_MODE_MASK (0x30000000U) +#define GPC_CPU_CTRL_CM_WAKEUP_A55_HDSK_CTRL_CNT_MODE_SHIFT (28U) +/*! CNT_MODE - Count mode + * 0b00..Counter disable mode: not use step counter, step completes once receiving step_done + * 0b01..Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT + * 0b10..Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes + * 0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value + */ +#define GPC_CPU_CTRL_CM_WAKEUP_A55_HDSK_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_WAKEUP_A55_HDSK_CTRL_CNT_MODE_SHIFT)) & GPC_CPU_CTRL_CM_WAKEUP_A55_HDSK_CTRL_CNT_MODE_MASK) + +#define GPC_CPU_CTRL_CM_WAKEUP_A55_HDSK_CTRL_DISABLE_MASK (0x80000000U) +#define GPC_CPU_CTRL_CM_WAKEUP_A55_HDSK_CTRL_DISABLE_SHIFT (31U) +/*! DISABLE - Disable this step + * 0b0..This step is enabled. + * 0b1..This step is disabled. GPC will skip this step and not send any request. + */ +#define GPC_CPU_CTRL_CM_WAKEUP_A55_HDSK_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_WAKEUP_A55_HDSK_CTRL_DISABLE_SHIFT)) & GPC_CPU_CTRL_CM_WAKEUP_A55_HDSK_CTRL_DISABLE_MASK) +/*! @} */ + +/*! @name CM_SYS_SLEEP_CTRL - CM system sleep control */ +/*! @{ */ + +#define GPC_CPU_CTRL_CM_SYS_SLEEP_CTRL_SS_WAIT_MASK (0x1U) +#define GPC_CPU_CTRL_CM_SYS_SLEEP_CTRL_SS_WAIT_SHIFT (0U) +/*! SS_WAIT - Request system sleep when CPU is in WAIT mode + * 0b0..Do not request system sleep when CPU is in WAIT mode + * 0b1..Request system sleep when CPU is in WAIT mode + */ +#define GPC_CPU_CTRL_CM_SYS_SLEEP_CTRL_SS_WAIT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_SYS_SLEEP_CTRL_SS_WAIT_SHIFT)) & GPC_CPU_CTRL_CM_SYS_SLEEP_CTRL_SS_WAIT_MASK) + +#define GPC_CPU_CTRL_CM_SYS_SLEEP_CTRL_SS_STOP_MASK (0x2U) +#define GPC_CPU_CTRL_CM_SYS_SLEEP_CTRL_SS_STOP_SHIFT (1U) +/*! SS_STOP - Request system sleep when CPU is in STOP mode + * 0b0..Do not request system sleep when CPU is in STOP mode + * 0b1..Request system sleep when CPU is in STOP mode + */ +#define GPC_CPU_CTRL_CM_SYS_SLEEP_CTRL_SS_STOP(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_SYS_SLEEP_CTRL_SS_STOP_SHIFT)) & GPC_CPU_CTRL_CM_SYS_SLEEP_CTRL_SS_STOP_MASK) + +#define GPC_CPU_CTRL_CM_SYS_SLEEP_CTRL_SS_SUSPEND_MASK (0x4U) +#define GPC_CPU_CTRL_CM_SYS_SLEEP_CTRL_SS_SUSPEND_SHIFT (2U) +/*! SS_SUSPEND - Request system sleep when CPU is in SUSPEND mode + * 0b0..Do not request system sleep when CPU is in SUSPEND mode + * 0b1..Request system sleep when CPU is in SUSPEND mode + */ +#define GPC_CPU_CTRL_CM_SYS_SLEEP_CTRL_SS_SUSPEND(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_SYS_SLEEP_CTRL_SS_SUSPEND_SHIFT)) & GPC_CPU_CTRL_CM_SYS_SLEEP_CTRL_SS_SUSPEND_MASK) + +#define GPC_CPU_CTRL_CM_SYS_SLEEP_CTRL_SYS_SLEEP_BUSY_MASK (0x10000U) +#define GPC_CPU_CTRL_CM_SYS_SLEEP_CTRL_SYS_SLEEP_BUSY_SHIFT (16U) +/*! SYS_SLEEP_BUSY - Indicates the CPU is busy entering system sleep mode. */ +#define GPC_CPU_CTRL_CM_SYS_SLEEP_CTRL_SYS_SLEEP_BUSY(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_SYS_SLEEP_CTRL_SYS_SLEEP_BUSY_SHIFT)) & GPC_CPU_CTRL_CM_SYS_SLEEP_CTRL_SYS_SLEEP_BUSY_MASK) + +#define GPC_CPU_CTRL_CM_SYS_SLEEP_CTRL_SYS_WAKEUP_BUSY_MASK (0x20000U) +#define GPC_CPU_CTRL_CM_SYS_SLEEP_CTRL_SYS_WAKEUP_BUSY_SHIFT (17U) +/*! SYS_WAKEUP_BUSY - Indicates the CPU is busy exiting system sleep mode. */ +#define GPC_CPU_CTRL_CM_SYS_SLEEP_CTRL_SYS_WAKEUP_BUSY(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_SYS_SLEEP_CTRL_SYS_WAKEUP_BUSY_SHIFT)) & GPC_CPU_CTRL_CM_SYS_SLEEP_CTRL_SYS_WAKEUP_BUSY_MASK) +/*! @} */ + +/*! @name CM_DEBUG - CM debug */ +/*! @{ */ + +#define GPC_CPU_CTRL_CM_DEBUG_PRETEND_SLEEP_MASK (0x1U) +#define GPC_CPU_CTRL_CM_DEBUG_PRETEND_SLEEP_SHIFT (0U) +/*! PRETEND_SLEEP - Write 1 to force CMC into sleep. Used to debug GPC status. Locked by LOCK_CFG field. */ +#define GPC_CPU_CTRL_CM_DEBUG_PRETEND_SLEEP(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_CTRL_CM_DEBUG_PRETEND_SLEEP_SHIFT)) & GPC_CPU_CTRL_CM_DEBUG_PRETEND_SLEEP_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group GPC_CPU_CTRL_Register_Masks */ + + +/* GPC_CPU_CTRL - Peripheral instance base addresses */ +/** Peripheral GPC__GPC_CTRL_CA55_0 base address */ +#define GPC__GPC_CTRL_CA55_0_BASE (0x44470800u) +/** Peripheral GPC__GPC_CTRL_CA55_0 base pointer */ +#define GPC__GPC_CTRL_CA55_0 ((GPC_CPU_CTRL_Type *)GPC__GPC_CTRL_CA55_0_BASE) +/** Peripheral GPC__GPC_CTRL_CA55_CLUSTER base address */ +#define GPC__GPC_CTRL_CA55_CLUSTER_BASE (0x44471800u) +/** Peripheral GPC__GPC_CTRL_CA55_CLUSTER base pointer */ +#define GPC__GPC_CTRL_CA55_CLUSTER ((GPC_CPU_CTRL_Type *)GPC__GPC_CTRL_CA55_CLUSTER_BASE) +/** Array initializer of GPC_CPU_CTRL peripheral base addresses */ +#define GPC_CPU_CTRL_BASE_ADDRS { GPC__GPC_CTRL_CA55_0_BASE, GPC__GPC_CTRL_CA55_CLUSTER_BASE } +/** Array initializer of GPC_CPU_CTRL peripheral base pointers */ +#define GPC_CPU_CTRL_BASE_PTRS { GPC__GPC_CTRL_CA55_0, GPC__GPC_CTRL_CA55_CLUSTER } + +/*! + * @} + */ /* end of group GPC_CPU_CTRL_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- GPC_GLOBAL Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup GPC_GLOBAL_Peripheral_Access_Layer GPC_GLOBAL Peripheral Access Layer + * @{ + */ + +/** GPC_GLOBAL - Register Layout Typedef */ +typedef struct { + uint8_t RESERVED_0[4]; + __IO uint32_t AUTHEN_CTRL; /**< GPC Global Authentication Control, offset: 0x4 */ + uint8_t RESERVED_1[8]; + __IO uint32_t GPC_DOMAIN; /**< GPC domain assignment, offset: 0x10 */ + uint8_t RESERVED_2[8]; + __IO uint32_t GPC_MASTER; /**< GPC master CPU configuration, offset: 0x1C */ + uint8_t RESERVED_3[32]; + __IO uint32_t GPC_SYS_SLEEP; /**< GPC system sleep control, offset: 0x40 */ + uint8_t RESERVED_4[188]; + __IO uint32_t PMIC_CTRL; /**< PMIC standby control, offset: 0x100 */ + __IO uint32_t PMIC_PRE_DLY_CTRL; /**< PMIC standby pre delay control, offset: 0x104 */ + __IO uint32_t PMIC_STBY_ACK_CTRL; /**< PMIC standby acknowledge control, offset: 0x108 */ + uint8_t RESERVED_5[244]; + __IO uint32_t GPC_ROSC_CTRL; /**< RCOSC control, offset: 0x200 */ + __IO uint32_t GPC_AON_MEM_CTRL; /**< AON Memory control, offset: 0x204 */ + __IO uint32_t GPC_EFUSE_CTRL; /**< eFUSE control, offset: 0x208 */ +} GPC_GLOBAL_Type; + +/* ---------------------------------------------------------------------------- + -- GPC_GLOBAL Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup GPC_GLOBAL_Register_Masks GPC_GLOBAL Register Masks + * @{ + */ + +/*! @name AUTHEN_CTRL - GPC Global Authentication Control */ +/*! @{ */ + +#define GPC_GLOBAL_AUTHEN_CTRL_LOCK_CFG_MASK (0x80U) +#define GPC_GLOBAL_AUTHEN_CTRL_LOCK_CFG_SHIFT (7U) +/*! LOCK_CFG - Configuration lock + * 0b0..The value of low power configuration fields are not locked. + * 0b1..The value of low power configuration fields are locked. Refer to the function field of each gpc_global registers. + */ +#define GPC_GLOBAL_AUTHEN_CTRL_LOCK_CFG(x) (((uint32_t)(((uint32_t)(x)) << GPC_GLOBAL_AUTHEN_CTRL_LOCK_CFG_SHIFT)) & GPC_GLOBAL_AUTHEN_CTRL_LOCK_CFG_MASK) + +#define GPC_GLOBAL_AUTHEN_CTRL_USER_MASK (0x100U) +#define GPC_GLOBAL_AUTHEN_CTRL_USER_SHIFT (8U) +/*! USER - Allow user mode access + * 0b0..Allow only privilege mode to access CPU mode control registers + * 0b1..Allow both privilege and user mode to access CPU mode control registers + */ +#define GPC_GLOBAL_AUTHEN_CTRL_USER(x) (((uint32_t)(((uint32_t)(x)) << GPC_GLOBAL_AUTHEN_CTRL_USER_SHIFT)) & GPC_GLOBAL_AUTHEN_CTRL_USER_MASK) + +#define GPC_GLOBAL_AUTHEN_CTRL_NONSECURE_MASK (0x200U) +#define GPC_GLOBAL_AUTHEN_CTRL_NONSECURE_SHIFT (9U) +/*! NONSECURE - Allow non-secure mode access + * 0b0..Allow only secure mode to access CPU mode registers + * 0b1..Allow both secure and non-secure mode to access CPU mode control registers. + */ +#define GPC_GLOBAL_AUTHEN_CTRL_NONSECURE(x) (((uint32_t)(((uint32_t)(x)) << GPC_GLOBAL_AUTHEN_CTRL_NONSECURE_SHIFT)) & GPC_GLOBAL_AUTHEN_CTRL_NONSECURE_MASK) + +#define GPC_GLOBAL_AUTHEN_CTRL_LOCK_SETTING_MASK (0x800U) +#define GPC_GLOBAL_AUTHEN_CTRL_LOCK_SETTING_SHIFT (11U) +/*! LOCK_SETTING - Lock NONSECURE and USER + * 0b0..NONSECURE and USER fields are not locked + * 0b1..NONSECURE and USER fields are locked + */ +#define GPC_GLOBAL_AUTHEN_CTRL_LOCK_SETTING(x) (((uint32_t)(((uint32_t)(x)) << GPC_GLOBAL_AUTHEN_CTRL_LOCK_SETTING_SHIFT)) & GPC_GLOBAL_AUTHEN_CTRL_LOCK_SETTING_MASK) + +#define GPC_GLOBAL_AUTHEN_CTRL_LOCK_LIST_MASK (0x8000U) +#define GPC_GLOBAL_AUTHEN_CTRL_LOCK_LIST_SHIFT (15U) +/*! LOCK_LIST - White list lock + * 0b0..WHITE_LIST is not locked + * 0b1..WHITE_LIST is locked + */ +#define GPC_GLOBAL_AUTHEN_CTRL_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << GPC_GLOBAL_AUTHEN_CTRL_LOCK_LIST_SHIFT)) & GPC_GLOBAL_AUTHEN_CTRL_LOCK_LIST_MASK) + +#define GPC_GLOBAL_AUTHEN_CTRL_WHITE_LIST_MASK (0xFFFF0000U) +#define GPC_GLOBAL_AUTHEN_CTRL_WHITE_LIST_SHIFT (16U) +/*! WHITE_LIST - Domain ID white list */ +#define GPC_GLOBAL_AUTHEN_CTRL_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << GPC_GLOBAL_AUTHEN_CTRL_WHITE_LIST_SHIFT)) & GPC_GLOBAL_AUTHEN_CTRL_WHITE_LIST_MASK) +/*! @} */ + +/*! @name GPC_DOMAIN - GPC domain assignment */ +/*! @{ */ + +#define GPC_GLOBAL_GPC_DOMAIN_CPU0_DOMAIN_MASK (0xFU) +#define GPC_GLOBAL_GPC_DOMAIN_CPU0_DOMAIN_SHIFT (0U) +/*! CPU0_DOMAIN - CPU0 domain assignment */ +#define GPC_GLOBAL_GPC_DOMAIN_CPU0_DOMAIN(x) (((uint32_t)(((uint32_t)(x)) << GPC_GLOBAL_GPC_DOMAIN_CPU0_DOMAIN_SHIFT)) & GPC_GLOBAL_GPC_DOMAIN_CPU0_DOMAIN_MASK) + +#define GPC_GLOBAL_GPC_DOMAIN_CPU1_DOMAIN_MASK (0xF0U) +#define GPC_GLOBAL_GPC_DOMAIN_CPU1_DOMAIN_SHIFT (4U) +/*! CPU1_DOMAIN - CPU1 domain assignment */ +#define GPC_GLOBAL_GPC_DOMAIN_CPU1_DOMAIN(x) (((uint32_t)(((uint32_t)(x)) << GPC_GLOBAL_GPC_DOMAIN_CPU1_DOMAIN_SHIFT)) & GPC_GLOBAL_GPC_DOMAIN_CPU1_DOMAIN_MASK) + +#define GPC_GLOBAL_GPC_DOMAIN_CPU2_DOMAIN_MASK (0xF00U) +#define GPC_GLOBAL_GPC_DOMAIN_CPU2_DOMAIN_SHIFT (8U) +/*! CPU2_DOMAIN - CPU2 domain assignment */ +#define GPC_GLOBAL_GPC_DOMAIN_CPU2_DOMAIN(x) (((uint32_t)(((uint32_t)(x)) << GPC_GLOBAL_GPC_DOMAIN_CPU2_DOMAIN_SHIFT)) & GPC_GLOBAL_GPC_DOMAIN_CPU2_DOMAIN_MASK) + +#define GPC_GLOBAL_GPC_DOMAIN_CPU3_DOMAIN_MASK (0xF000U) +#define GPC_GLOBAL_GPC_DOMAIN_CPU3_DOMAIN_SHIFT (12U) +/*! CPU3_DOMAIN - CPU3 domain assignment */ +#define GPC_GLOBAL_GPC_DOMAIN_CPU3_DOMAIN(x) (((uint32_t)(((uint32_t)(x)) << GPC_GLOBAL_GPC_DOMAIN_CPU3_DOMAIN_SHIFT)) & GPC_GLOBAL_GPC_DOMAIN_CPU3_DOMAIN_MASK) +/*! @} */ + +/*! @name GPC_MASTER - GPC master CPU configuration */ +/*! @{ */ + +#define GPC_GLOBAL_GPC_MASTER_CPU0_MASTER_MASK (0x1U) +#define GPC_GLOBAL_GPC_MASTER_CPU0_MASTER_SHIFT (0U) +/*! CPU0_MASTER - Setting to 1 means CPU0 is the master CPU of its domain + * 0b0..CPU0 is not the master CPU of its domain + * 0b1..CPU0 is the master CPU of its domain + */ +#define GPC_GLOBAL_GPC_MASTER_CPU0_MASTER(x) (((uint32_t)(((uint32_t)(x)) << GPC_GLOBAL_GPC_MASTER_CPU0_MASTER_SHIFT)) & GPC_GLOBAL_GPC_MASTER_CPU0_MASTER_MASK) + +#define GPC_GLOBAL_GPC_MASTER_CPU1_MASTER_MASK (0x2U) +#define GPC_GLOBAL_GPC_MASTER_CPU1_MASTER_SHIFT (1U) +/*! CPU1_MASTER - Setting to 1 means CPU1 is the master CPU of its domain + * 0b0..CPU1 is not the master CPU of its domain + * 0b1..CPU1 is the master CPU of its domain + */ +#define GPC_GLOBAL_GPC_MASTER_CPU1_MASTER(x) (((uint32_t)(((uint32_t)(x)) << GPC_GLOBAL_GPC_MASTER_CPU1_MASTER_SHIFT)) & GPC_GLOBAL_GPC_MASTER_CPU1_MASTER_MASK) + +#define GPC_GLOBAL_GPC_MASTER_CPU2_MASTER_MASK (0x4U) +#define GPC_GLOBAL_GPC_MASTER_CPU2_MASTER_SHIFT (2U) +/*! CPU2_MASTER - Setting to 1 means CPU2 is the master CPU of its domain + * 0b0..CPU2 is not the master CPU of its domain + * 0b1..CPU2 is the master CPU of its domain + */ +#define GPC_GLOBAL_GPC_MASTER_CPU2_MASTER(x) (((uint32_t)(((uint32_t)(x)) << GPC_GLOBAL_GPC_MASTER_CPU2_MASTER_SHIFT)) & GPC_GLOBAL_GPC_MASTER_CPU2_MASTER_MASK) + +#define GPC_GLOBAL_GPC_MASTER_CPU3_MASTER_MASK (0x8U) +#define GPC_GLOBAL_GPC_MASTER_CPU3_MASTER_SHIFT (3U) +/*! CPU3_MASTER - Setting to 1 means CPU3 is the master CPU of its domain + * 0b0..CPU3 is not the master CPU of its domain + * 0b1..CPU3 is the master CPU of its domain + */ +#define GPC_GLOBAL_GPC_MASTER_CPU3_MASTER(x) (((uint32_t)(((uint32_t)(x)) << GPC_GLOBAL_GPC_MASTER_CPU3_MASTER_SHIFT)) & GPC_GLOBAL_GPC_MASTER_CPU3_MASTER_MASK) +/*! @} */ + +/*! @name GPC_SYS_SLEEP - GPC system sleep control */ +/*! @{ */ + +#define GPC_GLOBAL_GPC_SYS_SLEEP_FORCE_CPU0_DISABLE_MASK (0x10000U) +#define GPC_GLOBAL_GPC_SYS_SLEEP_FORCE_CPU0_DISABLE_SHIFT (16U) +/*! FORCE_CPU0_DISABLE - Force CPU0 into a system sleep status */ +#define GPC_GLOBAL_GPC_SYS_SLEEP_FORCE_CPU0_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_GLOBAL_GPC_SYS_SLEEP_FORCE_CPU0_DISABLE_SHIFT)) & GPC_GLOBAL_GPC_SYS_SLEEP_FORCE_CPU0_DISABLE_MASK) + +#define GPC_GLOBAL_GPC_SYS_SLEEP_FORCE_CPU1_DISABLE_MASK (0x20000U) +#define GPC_GLOBAL_GPC_SYS_SLEEP_FORCE_CPU1_DISABLE_SHIFT (17U) +/*! FORCE_CPU1_DISABLE - Force CPU1 into a system sleep status */ +#define GPC_GLOBAL_GPC_SYS_SLEEP_FORCE_CPU1_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_GLOBAL_GPC_SYS_SLEEP_FORCE_CPU1_DISABLE_SHIFT)) & GPC_GLOBAL_GPC_SYS_SLEEP_FORCE_CPU1_DISABLE_MASK) + +#define GPC_GLOBAL_GPC_SYS_SLEEP_FORCE_CPU2_DISABLE_MASK (0x40000U) +#define GPC_GLOBAL_GPC_SYS_SLEEP_FORCE_CPU2_DISABLE_SHIFT (18U) +/*! FORCE_CPU2_DISABLE - Force CPU2 into a system sleep status */ +#define GPC_GLOBAL_GPC_SYS_SLEEP_FORCE_CPU2_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_GLOBAL_GPC_SYS_SLEEP_FORCE_CPU2_DISABLE_SHIFT)) & GPC_GLOBAL_GPC_SYS_SLEEP_FORCE_CPU2_DISABLE_MASK) + +#define GPC_GLOBAL_GPC_SYS_SLEEP_FORCE_CPU3_DISABLE_MASK (0x80000U) +#define GPC_GLOBAL_GPC_SYS_SLEEP_FORCE_CPU3_DISABLE_SHIFT (19U) +/*! FORCE_CPU3_DISABLE - Force CPU3 into a system sleep status */ +#define GPC_GLOBAL_GPC_SYS_SLEEP_FORCE_CPU3_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_GLOBAL_GPC_SYS_SLEEP_FORCE_CPU3_DISABLE_SHIFT)) & GPC_GLOBAL_GPC_SYS_SLEEP_FORCE_CPU3_DISABLE_MASK) +/*! @} */ + +/*! @name PMIC_CTRL - PMIC standby control */ +/*! @{ */ + +#define GPC_GLOBAL_PMIC_CTRL_PMIC_STBY_EN_MASK (0x1U) +#define GPC_GLOBAL_PMIC_CTRL_PMIC_STBY_EN_SHIFT (0U) +/*! PMIC_STBY_EN - Assert the PMIC_STBY_REQ when system sleep */ +#define GPC_GLOBAL_PMIC_CTRL_PMIC_STBY_EN(x) (((uint32_t)(((uint32_t)(x)) << GPC_GLOBAL_PMIC_CTRL_PMIC_STBY_EN_SHIFT)) & GPC_GLOBAL_PMIC_CTRL_PMIC_STBY_EN_MASK) +/*! @} */ + +/*! @name PMIC_PRE_DLY_CTRL - PMIC standby pre delay control */ +/*! @{ */ + +#define GPC_GLOBAL_PMIC_PRE_DLY_CTRL_DLY_PRE_STBY_ON_MASK (0xFFFFU) +#define GPC_GLOBAL_PMIC_PRE_DLY_CTRL_DLY_PRE_STBY_ON_SHIFT (0U) +/*! DLY_PRE_STBY_ON - Delay before pmic_standby on. Locked by LOCK_CFG field. */ +#define GPC_GLOBAL_PMIC_PRE_DLY_CTRL_DLY_PRE_STBY_ON(x) (((uint32_t)(((uint32_t)(x)) << GPC_GLOBAL_PMIC_PRE_DLY_CTRL_DLY_PRE_STBY_ON_SHIFT)) & GPC_GLOBAL_PMIC_PRE_DLY_CTRL_DLY_PRE_STBY_ON_MASK) + +#define GPC_GLOBAL_PMIC_PRE_DLY_CTRL_DLY_PRE_STBY_OFF_MASK (0xFFFF0000U) +#define GPC_GLOBAL_PMIC_PRE_DLY_CTRL_DLY_PRE_STBY_OFF_SHIFT (16U) +/*! DLY_PRE_STBY_OFF - Delay before pmic_standby off. Locked by LOCK_CFG field. */ +#define GPC_GLOBAL_PMIC_PRE_DLY_CTRL_DLY_PRE_STBY_OFF(x) (((uint32_t)(((uint32_t)(x)) << GPC_GLOBAL_PMIC_PRE_DLY_CTRL_DLY_PRE_STBY_OFF_SHIFT)) & GPC_GLOBAL_PMIC_PRE_DLY_CTRL_DLY_PRE_STBY_OFF_MASK) +/*! @} */ + +/*! @name PMIC_STBY_ACK_CTRL - PMIC standby acknowledge control */ +/*! @{ */ + +#define GPC_GLOBAL_PMIC_STBY_ACK_CTRL_STBY_ON_CNT_CFG_MASK (0xFFFU) +#define GPC_GLOBAL_PMIC_STBY_ACK_CTRL_STBY_ON_CNT_CFG_SHIFT (0U) +/*! STBY_ON_CNT_CFG - PMIC standby on acknowledge count configure. Usage depends on STBY_ON_CNT_MODE. Locked by LOCK_CFG field. */ +#define GPC_GLOBAL_PMIC_STBY_ACK_CTRL_STBY_ON_CNT_CFG(x) (((uint32_t)(((uint32_t)(x)) << GPC_GLOBAL_PMIC_STBY_ACK_CTRL_STBY_ON_CNT_CFG_SHIFT)) & GPC_GLOBAL_PMIC_STBY_ACK_CTRL_STBY_ON_CNT_CFG_MASK) + +#define GPC_GLOBAL_PMIC_STBY_ACK_CTRL_STBY_ON_CNT_MODE_MASK (0xC000U) +#define GPC_GLOBAL_PMIC_STBY_ACK_CTRL_STBY_ON_CNT_MODE_SHIFT (14U) +/*! STBY_ON_CNT_MODE - PMIC standby on acknowledge count mode. Locked by LOCK_CFG field. + * 0b00..Finish the process once pmic_standby signal changes + * 0b01..Finish the process once getting acknowledge from PMIC + * 0b10..Ignore PMIC acknowledge, the delay counter starts to count once pmic_standby changes + * 0b11..Time out mode, the counter starts to count once pmic_standby changes, then finishes the process when + * either acknowledge received or counting to CNT_CFG value + */ +#define GPC_GLOBAL_PMIC_STBY_ACK_CTRL_STBY_ON_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_GLOBAL_PMIC_STBY_ACK_CTRL_STBY_ON_CNT_MODE_SHIFT)) & GPC_GLOBAL_PMIC_STBY_ACK_CTRL_STBY_ON_CNT_MODE_MASK) + +#define GPC_GLOBAL_PMIC_STBY_ACK_CTRL_STBY_OFF_CNT_CFG_MASK (0xFFF0000U) +#define GPC_GLOBAL_PMIC_STBY_ACK_CTRL_STBY_OFF_CNT_CFG_SHIFT (16U) +/*! STBY_OFF_CNT_CFG - PMIC standby off acknowledge count configure. Usage depends on STBY_OFF_CNT_MODE. Locked by LOCK_CFG field. */ +#define GPC_GLOBAL_PMIC_STBY_ACK_CTRL_STBY_OFF_CNT_CFG(x) (((uint32_t)(((uint32_t)(x)) << GPC_GLOBAL_PMIC_STBY_ACK_CTRL_STBY_OFF_CNT_CFG_SHIFT)) & GPC_GLOBAL_PMIC_STBY_ACK_CTRL_STBY_OFF_CNT_CFG_MASK) + +#define GPC_GLOBAL_PMIC_STBY_ACK_CTRL_STBY_OFF_CNT_MODE_MASK (0xC0000000U) +#define GPC_GLOBAL_PMIC_STBY_ACK_CTRL_STBY_OFF_CNT_MODE_SHIFT (30U) +/*! STBY_OFF_CNT_MODE - PMIC standby off acknowledge count mode. Locked by LOCK_CFG field. + * 0b00..Finish the process once pmic_standby signal changes + * 0b01..Finish the process once getting acknowledge from PMIC + * 0b10..Ignore PMIC acknowledge, the delay counter starts to count once pmic_standby changes + * 0b11..Time out mode, the counter starts to count once pmic_standby changes, then finishes the process when + * either acknowledge received or counting to CNT_CFG value + */ +#define GPC_GLOBAL_PMIC_STBY_ACK_CTRL_STBY_OFF_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_GLOBAL_PMIC_STBY_ACK_CTRL_STBY_OFF_CNT_MODE_SHIFT)) & GPC_GLOBAL_PMIC_STBY_ACK_CTRL_STBY_OFF_CNT_MODE_MASK) +/*! @} */ + +/*! @name GPC_ROSC_CTRL - RCOSC control */ +/*! @{ */ + +#define GPC_GLOBAL_GPC_ROSC_CTRL_ROSC_OFF_EN_MASK (0x1U) +#define GPC_GLOBAL_GPC_ROSC_CTRL_ROSC_OFF_EN_SHIFT (0U) +/*! ROSC_OFF_EN - Shut off the 24 MHz RCOSC clock when system sleep */ +#define GPC_GLOBAL_GPC_ROSC_CTRL_ROSC_OFF_EN(x) (((uint32_t)(((uint32_t)(x)) << GPC_GLOBAL_GPC_ROSC_CTRL_ROSC_OFF_EN_SHIFT)) & GPC_GLOBAL_GPC_ROSC_CTRL_ROSC_OFF_EN_MASK) +/*! @} */ + +/*! @name GPC_AON_MEM_CTRL - AON Memory control */ +/*! @{ */ + +#define GPC_GLOBAL_GPC_AON_MEM_CTRL_AON_MEM_LP_EN_MASK (0x1U) +#define GPC_GLOBAL_GPC_AON_MEM_CTRL_AON_MEM_LP_EN_SHIFT (0U) +/*! AON_MEM_LP_EN - AON memory enter LP enable */ +#define GPC_GLOBAL_GPC_AON_MEM_CTRL_AON_MEM_LP_EN(x) (((uint32_t)(((uint32_t)(x)) << GPC_GLOBAL_GPC_AON_MEM_CTRL_AON_MEM_LP_EN_SHIFT)) & GPC_GLOBAL_GPC_AON_MEM_CTRL_AON_MEM_LP_EN_MASK) +/*! @} */ + +/*! @name GPC_EFUSE_CTRL - eFUSE control */ +/*! @{ */ + +#define GPC_GLOBAL_GPC_EFUSE_CTRL_EFUSE_PD_EN_MASK (0x1U) +#define GPC_GLOBAL_GPC_EFUSE_CTRL_EFUSE_PD_EN_SHIFT (0U) +/*! EFUSE_PD_EN - eFUSE power down enable */ +#define GPC_GLOBAL_GPC_EFUSE_CTRL_EFUSE_PD_EN(x) (((uint32_t)(((uint32_t)(x)) << GPC_GLOBAL_GPC_EFUSE_CTRL_EFUSE_PD_EN_SHIFT)) & GPC_GLOBAL_GPC_EFUSE_CTRL_EFUSE_PD_EN_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group GPC_GLOBAL_Register_Masks */ + + +/* GPC_GLOBAL - Peripheral instance base addresses */ +/** Peripheral GPC__GPC_GLOBAL base address */ +#define GPC__GPC_GLOBAL_BASE (0x44474000u) +/** Peripheral GPC__GPC_GLOBAL base pointer */ +#define GPC__GPC_GLOBAL ((GPC_GLOBAL_Type *)GPC__GPC_GLOBAL_BASE) +/** Array initializer of GPC_GLOBAL peripheral base addresses */ +#define GPC_GLOBAL_BASE_ADDRS { GPC__GPC_GLOBAL_BASE } +/** Array initializer of GPC_GLOBAL peripheral base pointers */ +#define GPC_GLOBAL_BASE_PTRS { GPC__GPC_GLOBAL } + +/*! + * @} + */ /* end of group GPC_GLOBAL_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- I2S Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup I2S_Peripheral_Access_Layer I2S Peripheral Access Layer + * @{ + */ + +/** I2S - Register Layout Typedef */ +typedef struct { + __I uint32_t VERID; /**< Version ID, offset: 0x0 */ + __I uint32_t PARAM; /**< Parameter, offset: 0x4 */ + __IO uint32_t TCSR; /**< Transmit Control, offset: 0x8 */ + __IO uint32_t TCR1; /**< Transmit Configuration 1, offset: 0xC */ + __IO uint32_t TCR2; /**< Transmit Configuration 2, offset: 0x10 */ + __IO uint32_t TCR3; /**< Transmit Configuration 3, offset: 0x14 */ + __IO uint32_t TCR4; /**< Transmit Configuration 4, offset: 0x18 */ + __IO uint32_t TCR5; /**< Transmit Configuration 5, offset: 0x1C */ + __IO uint32_t TDR[2]; /**< Transmit Data, array offset: 0x20, array step: 0x4, irregular array, not all indices are valid */ + uint8_t RESERVED_0[24]; + __I uint32_t TFR[2]; /**< Transmit FIFO, array offset: 0x40, array step: 0x4, irregular array, not all indices are valid */ + uint8_t RESERVED_1[24]; + __IO uint32_t TMR; /**< Transmit Mask, offset: 0x60 */ + uint8_t RESERVED_2[12]; + __IO uint32_t TTCR; /**< Transmit Timestamp Control, offset: 0x70 */ + __I uint32_t TTSR; /**< Transmit Timestamp, offset: 0x74 */ + __I uint32_t TBCR; /**< Transmit Bit Count, offset: 0x78 */ + __I uint32_t TBCTR; /**< Transmit Bit Count Timestamp, offset: 0x7C */ + uint8_t RESERVED_3[8]; + __IO uint32_t RCSR; /**< Receive Control, offset: 0x88 */ + __IO uint32_t RCR1; /**< Receive Configuration 1, offset: 0x8C */ + __IO uint32_t RCR2; /**< Receive Configuration 2, offset: 0x90 */ + __IO uint32_t RCR3; /**< Receive Configuration 3, offset: 0x94 */ + __IO uint32_t RCR4; /**< Receive Configuration 4, offset: 0x98 */ + __IO uint32_t RCR5; /**< Receive Configuration 5, offset: 0x9C */ + __I uint32_t RDR[2]; /**< Receive Data, array offset: 0xA0, array step: 0x4, irregular array, not all indices are valid */ + uint8_t RESERVED_4[24]; + __I uint32_t RFR[2]; /**< Receive FIFO, array offset: 0xC0, array step: 0x4, irregular array, not all indices are valid */ + uint8_t RESERVED_5[24]; + __IO uint32_t RMR; /**< Receive Mask, offset: 0xE0 */ + uint8_t RESERVED_6[12]; + __IO uint32_t RTCR; /**< Receive Timestamp Control, offset: 0xF0 */ + __I uint32_t RTSR; /**< Receive Timestamp, offset: 0xF4 */ + __I uint32_t RBCR; /**< Receive Bit Count, offset: 0xF8 */ + __I uint32_t RBCTR; /**< Receive Bit Count Timestamp, offset: 0xFC */ + __IO uint32_t MCR; /**< MCLK Control, offset: 0x100 */ +} I2S_Type; + +/* ---------------------------------------------------------------------------- + -- I2S Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup I2S_Register_Masks I2S Register Masks + * @{ + */ + +/*! @name VERID - Version ID */ +/*! @{ */ + +#define I2S_VERID_FEATURE_MASK (0xFFFFU) +#define I2S_VERID_FEATURE_SHIFT (0U) +/*! FEATURE - Feature Specification Number + * 0b0000000000000000..Standard feature set + * 0b0000000000000010..Standard feature set with timestamp registers + */ +#define I2S_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << I2S_VERID_FEATURE_SHIFT)) & I2S_VERID_FEATURE_MASK) + +#define I2S_VERID_MINOR_MASK (0xFF0000U) +#define I2S_VERID_MINOR_SHIFT (16U) +/*! MINOR - Minor Version Number */ +#define I2S_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << I2S_VERID_MINOR_SHIFT)) & I2S_VERID_MINOR_MASK) + +#define I2S_VERID_MAJOR_MASK (0xFF000000U) +#define I2S_VERID_MAJOR_SHIFT (24U) +/*! MAJOR - Major Version Number */ +#define I2S_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << I2S_VERID_MAJOR_SHIFT)) & I2S_VERID_MAJOR_MASK) +/*! @} */ + +/*! @name PARAM - Parameter */ +/*! @{ */ + +#define I2S_PARAM_DATALINE_MASK (0xFU) +#define I2S_PARAM_DATALINE_SHIFT (0U) +/*! DATALINE - Number of Data Lines */ +#define I2S_PARAM_DATALINE(x) (((uint32_t)(((uint32_t)(x)) << I2S_PARAM_DATALINE_SHIFT)) & I2S_PARAM_DATALINE_MASK) + +#define I2S_PARAM_FIFO_MASK (0xF00U) +#define I2S_PARAM_FIFO_SHIFT (8U) +/*! FIFO - FIFO Size */ +#define I2S_PARAM_FIFO(x) (((uint32_t)(((uint32_t)(x)) << I2S_PARAM_FIFO_SHIFT)) & I2S_PARAM_FIFO_MASK) + +#define I2S_PARAM_FRAME_MASK (0xF0000U) +#define I2S_PARAM_FRAME_SHIFT (16U) +/*! FRAME - Frame Size */ +#define I2S_PARAM_FRAME(x) (((uint32_t)(((uint32_t)(x)) << I2S_PARAM_FRAME_SHIFT)) & I2S_PARAM_FRAME_MASK) +/*! @} */ + +/*! @name TCSR - Transmit Control */ +/*! @{ */ + +#define I2S_TCSR_FRDE_MASK (0x1U) +#define I2S_TCSR_FRDE_SHIFT (0U) +/*! FRDE - FIFO Request DMA Enable + * 0b0..Disable + * 0b1..Enable + */ +#define I2S_TCSR_FRDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRDE_SHIFT)) & I2S_TCSR_FRDE_MASK) + +#define I2S_TCSR_FWDE_MASK (0x2U) +#define I2S_TCSR_FWDE_SHIFT (1U) +/*! FWDE - FIFO Warning DMA Enable + * 0b0..Disable + * 0b1..Enable + */ +#define I2S_TCSR_FWDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWDE_SHIFT)) & I2S_TCSR_FWDE_MASK) + +#define I2S_TCSR_FRIE_MASK (0x100U) +#define I2S_TCSR_FRIE_SHIFT (8U) +/*! FRIE - FIFO Request Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define I2S_TCSR_FRIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRIE_SHIFT)) & I2S_TCSR_FRIE_MASK) + +#define I2S_TCSR_FWIE_MASK (0x200U) +#define I2S_TCSR_FWIE_SHIFT (9U) +/*! FWIE - FIFO Warning Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define I2S_TCSR_FWIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWIE_SHIFT)) & I2S_TCSR_FWIE_MASK) + +#define I2S_TCSR_FEIE_MASK (0x400U) +#define I2S_TCSR_FEIE_SHIFT (10U) +/*! FEIE - FIFO Error Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define I2S_TCSR_FEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FEIE_SHIFT)) & I2S_TCSR_FEIE_MASK) + +#define I2S_TCSR_SEIE_MASK (0x800U) +#define I2S_TCSR_SEIE_SHIFT (11U) +/*! SEIE - Sync Error Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define I2S_TCSR_SEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SEIE_SHIFT)) & I2S_TCSR_SEIE_MASK) + +#define I2S_TCSR_WSIE_MASK (0x1000U) +#define I2S_TCSR_WSIE_SHIFT (12U) +/*! WSIE - Word Start Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define I2S_TCSR_WSIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_WSIE_SHIFT)) & I2S_TCSR_WSIE_MASK) + +#define I2S_TCSR_FRF_MASK (0x10000U) +#define I2S_TCSR_FRF_SHIFT (16U) +/*! FRF - FIFO Request Flag + * 0b0..Watermark not reached + * 0b1..Watermark reached + */ +#define I2S_TCSR_FRF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRF_SHIFT)) & I2S_TCSR_FRF_MASK) + +#define I2S_TCSR_FWF_MASK (0x20000U) +#define I2S_TCSR_FWF_SHIFT (17U) +/*! FWF - FIFO Warning Flag + * 0b0..Not empty + * 0b1..Empty + */ +#define I2S_TCSR_FWF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWF_SHIFT)) & I2S_TCSR_FWF_MASK) + +#define I2S_TCSR_FEF_MASK (0x40000U) +#define I2S_TCSR_FEF_SHIFT (18U) +/*! FEF - FIFO Error Flag + * 0b0..Not detected + * 0b0..No effect + * 0b1..Detected + * 0b1..Clear the flag + */ +#define I2S_TCSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FEF_SHIFT)) & I2S_TCSR_FEF_MASK) + +#define I2S_TCSR_SEF_MASK (0x80000U) +#define I2S_TCSR_SEF_SHIFT (19U) +/*! SEF - Sync Error Flag + * 0b0..Not detected + * 0b0..No effect + * 0b1..Detected + * 0b1..Clear the flag + */ +#define I2S_TCSR_SEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SEF_SHIFT)) & I2S_TCSR_SEF_MASK) + +#define I2S_TCSR_WSF_MASK (0x100000U) +#define I2S_TCSR_WSF_SHIFT (20U) +/*! WSF - Word Start Flag + * 0b0..Not detected + * 0b0..No effect + * 0b1..Detected + * 0b1..Clear the flag + */ +#define I2S_TCSR_WSF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_WSF_SHIFT)) & I2S_TCSR_WSF_MASK) + +#define I2S_TCSR_SR_MASK (0x1000000U) +#define I2S_TCSR_SR_SHIFT (24U) +/*! SR - Software Reset + * 0b0..No effect + * 0b1..Software reset + */ +#define I2S_TCSR_SR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SR_SHIFT)) & I2S_TCSR_SR_MASK) + +#define I2S_TCSR_FR_MASK (0x2000000U) +#define I2S_TCSR_FR_SHIFT (25U) +/*! FR - FIFO Reset + * 0b0..No effect + * 0b1..FIFO reset + */ +#define I2S_TCSR_FR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FR_SHIFT)) & I2S_TCSR_FR_MASK) + +#define I2S_TCSR_BCE_MASK (0x10000000U) +#define I2S_TCSR_BCE_SHIFT (28U) +/*! BCE - Bit Clock Enable + * 0b0..Disable + * 0b1..Enable + */ +#define I2S_TCSR_BCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_BCE_SHIFT)) & I2S_TCSR_BCE_MASK) + +#define I2S_TCSR_DBGE_MASK (0x20000000U) +#define I2S_TCSR_DBGE_SHIFT (29U) +/*! DBGE - Debug Enable + * 0b0..Disable + * 0b1..Enable + */ +#define I2S_TCSR_DBGE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_DBGE_SHIFT)) & I2S_TCSR_DBGE_MASK) + +#define I2S_TCSR_STOPE_MASK (0x40000000U) +#define I2S_TCSR_STOPE_SHIFT (30U) +/*! STOPE - Stop Enable + * 0b0..Disable + * 0b1..Enable + */ +#define I2S_TCSR_STOPE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_STOPE_SHIFT)) & I2S_TCSR_STOPE_MASK) + +#define I2S_TCSR_TE_MASK (0x80000000U) +#define I2S_TCSR_TE_SHIFT (31U) +/*! TE - Transmitter Enable + * 0b0..Disable + * 0b1..Enable (or transmitter has been disabled and has not yet reached the end of the frame) + */ +#define I2S_TCSR_TE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_TE_SHIFT)) & I2S_TCSR_TE_MASK) +/*! @} */ + +/*! @name TCR1 - Transmit Configuration 1 */ +/*! @{ */ + +#define I2S_TCR1_TFW_MASK (0x7FU) /* Merged from fields with different position or width, of widths (6, 7), largest definition used */ +#define I2S_TCR1_TFW_SHIFT (0U) +/*! TFW - Transmit FIFO Watermark + * 0b0000000..1 + * 0b0000001..2 + * 0b0000010-0b1111110..(TFW +1) + * 0b1111111..128 + */ +#define I2S_TCR1_TFW(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR1_TFW_SHIFT)) & I2S_TCR1_TFW_MASK) /* Merged from fields with different position or width, of widths (6, 7), largest definition used */ +/*! @} */ + +/*! @name TCR2 - Transmit Configuration 2 */ +/*! @{ */ + +#define I2S_TCR2_DIV_MASK (0xFFU) +#define I2S_TCR2_DIV_SHIFT (0U) +/*! DIV - Bit Clock Divide */ +#define I2S_TCR2_DIV(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_DIV_SHIFT)) & I2S_TCR2_DIV_MASK) + +#define I2S_TCR2_BYP_MASK (0x800000U) +#define I2S_TCR2_BYP_SHIFT (23U) +/*! BYP - Bit Clock Bypass + * 0b0..Disable + * 0b1..Enable + */ +#define I2S_TCR2_BYP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BYP_SHIFT)) & I2S_TCR2_BYP_MASK) + +#define I2S_TCR2_BCD_MASK (0x1000000U) +#define I2S_TCR2_BCD_SHIFT (24U) +/*! BCD - Bit Clock Direction + * 0b0..Generate externally in Target mode + * 0b1..Generate internally in Controller mode + */ +#define I2S_TCR2_BCD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCD_SHIFT)) & I2S_TCR2_BCD_MASK) + +#define I2S_TCR2_BCP_MASK (0x2000000U) +#define I2S_TCR2_BCP_SHIFT (25U) +/*! BCP - Bit Clock Polarity + * 0b0..Active high + * 0b1..Active low + */ +#define I2S_TCR2_BCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCP_SHIFT)) & I2S_TCR2_BCP_MASK) + +#define I2S_TCR2_MSEL_MASK (0xC000000U) +#define I2S_TCR2_MSEL_SHIFT (26U) +/*! MSEL - MCLK Select + * 0b00..Bus clock + * 0b01..Controller clock (MCLK) option 1 + * 0b10..Controller clock (MCLK) option 2 + * 0b11..Controller clock (MCLK) option 3 + */ +#define I2S_TCR2_MSEL(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_MSEL_SHIFT)) & I2S_TCR2_MSEL_MASK) + +#define I2S_TCR2_BCI_MASK (0x10000000U) +#define I2S_TCR2_BCI_SHIFT (28U) +/*! BCI - Bit Clock Input + * 0b0..Disable + * 0b1..Enable + */ +#define I2S_TCR2_BCI(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCI_SHIFT)) & I2S_TCR2_BCI_MASK) + +#define I2S_TCR2_BCS_MASK (0x20000000U) +#define I2S_TCR2_BCS_SHIFT (29U) +/*! BCS - Bit Clock Swap + * 0b0..Use the normal bit clock source + * 0b1..Swap the bit clock source + */ +#define I2S_TCR2_BCS(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCS_SHIFT)) & I2S_TCR2_BCS_MASK) + +#define I2S_TCR2_SYNC_MASK (0x40000000U) +#define I2S_TCR2_SYNC_SHIFT (30U) +/*! SYNC - Synchronous Mode + * 0b0..Asynchronous mode + * 0b1..Synchronous with receiver + */ +#define I2S_TCR2_SYNC(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_SYNC_SHIFT)) & I2S_TCR2_SYNC_MASK) +/*! @} */ + +/*! @name TCR3 - Transmit Configuration 3 */ +/*! @{ */ + +#define I2S_TCR3_WDFL_MASK (0x1FU) +#define I2S_TCR3_WDFL_SHIFT (0U) +/*! WDFL - Word Flag Configuration */ +#define I2S_TCR3_WDFL(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_WDFL_SHIFT)) & I2S_TCR3_WDFL_MASK) + +#define I2S_TCR3_TCE_MASK (0x30000U) /* Merged from fields with different position or width, of widths (1, 2), largest definition used */ +#define I2S_TCR3_TCE_SHIFT (16U) +/*! TCE - Transmit Channel Enable */ +#define I2S_TCR3_TCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_TCE_SHIFT)) & I2S_TCR3_TCE_MASK) /* Merged from fields with different position or width, of widths (1, 2), largest definition used */ + +#define I2S_TCR3_CFR_MASK (0x3000000U) +#define I2S_TCR3_CFR_SHIFT (24U) +/*! CFR - Channel FIFO Reset */ +#define I2S_TCR3_CFR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_CFR_SHIFT)) & I2S_TCR3_CFR_MASK) +/*! @} */ + +/*! @name TCR4 - Transmit Configuration 4 */ +/*! @{ */ + +#define I2S_TCR4_FSD_MASK (0x1U) +#define I2S_TCR4_FSD_SHIFT (0U) +/*! FSD - Frame Sync Direction + * 0b0..Generated externally in Target mode + * 0b1..Generated internally in Controller mode + */ +#define I2S_TCR4_FSD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSD_SHIFT)) & I2S_TCR4_FSD_MASK) + +#define I2S_TCR4_FSP_MASK (0x2U) +#define I2S_TCR4_FSP_SHIFT (1U) +/*! FSP - Frame Sync Polarity + * 0b0..Active high + * 0b1..Active low + */ +#define I2S_TCR4_FSP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSP_SHIFT)) & I2S_TCR4_FSP_MASK) + +#define I2S_TCR4_ONDEM_MASK (0x4U) +#define I2S_TCR4_ONDEM_SHIFT (2U) +/*! ONDEM - On-Demand Mode + * 0b0..Generated continuously + * 0b1..Generated after the FIFO warning flag is cleared + */ +#define I2S_TCR4_ONDEM(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_ONDEM_SHIFT)) & I2S_TCR4_ONDEM_MASK) + +#define I2S_TCR4_FSE_MASK (0x8U) +#define I2S_TCR4_FSE_SHIFT (3U) +/*! FSE - Frame Sync Early + * 0b0..First bit of the frame + * 0b1..One bit before the first bit of the frame + */ +#define I2S_TCR4_FSE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSE_SHIFT)) & I2S_TCR4_FSE_MASK) + +#define I2S_TCR4_MF_MASK (0x10U) +#define I2S_TCR4_MF_SHIFT (4U) +/*! MF - MSB First + * 0b0..LSB + * 0b1..MSB + */ +#define I2S_TCR4_MF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_MF_SHIFT)) & I2S_TCR4_MF_MASK) + +#define I2S_TCR4_CHMOD_MASK (0x20U) +#define I2S_TCR4_CHMOD_SHIFT (5U) +/*! CHMOD - Channel Mode + * 0b0..TDM mode + * 0b1..Output mode + */ +#define I2S_TCR4_CHMOD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_CHMOD_SHIFT)) & I2S_TCR4_CHMOD_MASK) + +#define I2S_TCR4_SYWD_MASK (0x1F00U) +#define I2S_TCR4_SYWD_SHIFT (8U) +/*! SYWD - Sync Width */ +#define I2S_TCR4_SYWD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_SYWD_SHIFT)) & I2S_TCR4_SYWD_MASK) + +#define I2S_TCR4_FRSZ_MASK (0x1F0000U) +#define I2S_TCR4_FRSZ_SHIFT (16U) +/*! FRSZ - Frame Size */ +#define I2S_TCR4_FRSZ(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FRSZ_SHIFT)) & I2S_TCR4_FRSZ_MASK) + +#define I2S_TCR4_FPACK_MASK (0x3000000U) +#define I2S_TCR4_FPACK_SHIFT (24U) +/*! FPACK - FIFO Packing Mode + * 0b00..Disable FIFO packing + * 0b01..Reserved + * 0b10..Enable 8-bit FIFO packing + * 0b11..Enable 16-bit FIFO packing + */ +#define I2S_TCR4_FPACK(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FPACK_SHIFT)) & I2S_TCR4_FPACK_MASK) + +#define I2S_TCR4_FCOMB_MASK (0xC000000U) +#define I2S_TCR4_FCOMB_SHIFT (26U) +/*! FCOMB - FIFO Combine Mode + * 0b00..Disable + * 0b01..Enable on FIFO reads (from transmit shift registers) + * 0b10..Enable on FIFO writes (by software) + * 0b11..Enable on FIFO reads (from transmit shift registers) and writes (by software) + */ +#define I2S_TCR4_FCOMB(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FCOMB_SHIFT)) & I2S_TCR4_FCOMB_MASK) + +#define I2S_TCR4_FCONT_MASK (0x10000000U) +#define I2S_TCR4_FCONT_SHIFT (28U) +/*! FCONT - FIFO Continue on Error + * 0b0..Continue from the start of the next frame + * 0b1..Continue from the same word that caused the FIFO error + */ +#define I2S_TCR4_FCONT(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FCONT_SHIFT)) & I2S_TCR4_FCONT_MASK) +/*! @} */ + +/*! @name TCR5 - Transmit Configuration 5 */ +/*! @{ */ + +#define I2S_TCR5_FBT_MASK (0x1F00U) +#define I2S_TCR5_FBT_SHIFT (8U) +/*! FBT - First Bit Shifted + * 0b00000..0 + * 0b00001-0b11110..FBT + * 0b11111..31 + */ +#define I2S_TCR5_FBT(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_FBT_SHIFT)) & I2S_TCR5_FBT_MASK) + +#define I2S_TCR5_W0W_MASK (0x1F0000U) +#define I2S_TCR5_W0W_SHIFT (16U) +/*! W0W - Word 0 Width + * 0b00111..8 + * 0b01000..9 + * 0b01001-0b11110..(W0W value + 1) + * 0b11111..32 + */ +#define I2S_TCR5_W0W(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_W0W_SHIFT)) & I2S_TCR5_W0W_MASK) + +#define I2S_TCR5_WNW_MASK (0x1F000000U) +#define I2S_TCR5_WNW_SHIFT (24U) +/*! WNW - Word N Width + * 0b00111..8 + * 0b01000..9 + * 0b01001-0b11110..(WNW value + 1) + * 0b11111..32 + */ +#define I2S_TCR5_WNW(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_WNW_SHIFT)) & I2S_TCR5_WNW_MASK) +/*! @} */ + +/*! @name TDR - Transmit Data */ +/*! @{ */ + +#define I2S_TDR_TDR_MASK (0xFFFFFFFFU) +#define I2S_TDR_TDR_SHIFT (0U) +/*! TDR - Transmit Data */ +#define I2S_TDR_TDR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TDR_TDR_SHIFT)) & I2S_TDR_TDR_MASK) +/*! @} */ + +/* The count of I2S_TDR */ +#define I2S_TDR_COUNT (2U) + +/*! @name TFR - Transmit FIFO */ +/*! @{ */ + +#define I2S_TFR_RFP_MASK (0xFFU) /* Merged from fields with different position or width, of widths (7, 8), largest definition used */ +#define I2S_TFR_RFP_SHIFT (0U) +/*! RFP - Read FIFO Pointer */ +#define I2S_TFR_RFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TFR_RFP_SHIFT)) & I2S_TFR_RFP_MASK) /* Merged from fields with different position or width, of widths (7, 8), largest definition used */ + +#define I2S_TFR_WFP_MASK (0xFF0000U) /* Merged from fields with different position or width, of widths (7, 8), largest definition used */ +#define I2S_TFR_WFP_SHIFT (16U) +/*! WFP - Write FIFO Pointer */ +#define I2S_TFR_WFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TFR_WFP_SHIFT)) & I2S_TFR_WFP_MASK) /* Merged from fields with different position or width, of widths (7, 8), largest definition used */ + +#define I2S_TFR_WCP_MASK (0x80000000U) +#define I2S_TFR_WCP_SHIFT (31U) +/*! WCP - Write Channel Pointer + * 0b0..No effect + * 0b1..Next FIFO to be written + */ +#define I2S_TFR_WCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TFR_WCP_SHIFT)) & I2S_TFR_WCP_MASK) +/*! @} */ + +/* The count of I2S_TFR */ +#define I2S_TFR_COUNT (2U) + +/*! @name TMR - Transmit Mask */ +/*! @{ */ + +#define I2S_TMR_TWM_MASK (0xFFFFFFFFU) +#define I2S_TMR_TWM_SHIFT (0U) +/*! TWM - Transmit Word Mask + * 0b00000000000000000000000000000000..Enable + * 0b00000000000000000000000000000001..Mask + */ +#define I2S_TMR_TWM(x) (((uint32_t)(((uint32_t)(x)) << I2S_TMR_TWM_SHIFT)) & I2S_TMR_TWM_MASK) +/*! @} */ + +/*! @name TTCR - Transmit Timestamp Control */ +/*! @{ */ + +#define I2S_TTCR_TSEN_MASK (0x1U) +#define I2S_TTCR_TSEN_SHIFT (0U) +/*! TSEN - Timestamp Enable + * 0b0..Disable + * 0b1..Enable + */ +#define I2S_TTCR_TSEN(x) (((uint32_t)(((uint32_t)(x)) << I2S_TTCR_TSEN_SHIFT)) & I2S_TTCR_TSEN_MASK) + +#define I2S_TTCR_TSINC_MASK (0x2U) +#define I2S_TTCR_TSINC_SHIFT (1U) +/*! TSINC - Timestamp Increment + * 0b0..When enabled and after the bit counter has incremented + * 0b1..When enabled + */ +#define I2S_TTCR_TSINC(x) (((uint32_t)(((uint32_t)(x)) << I2S_TTCR_TSINC_SHIFT)) & I2S_TTCR_TSINC_MASK) + +#define I2S_TTCR_TSSEL_MASK (0xCU) +#define I2S_TTCR_TSSEL_SHIFT (2U) +/*! TSSEL - Timestamp Select + * 0b00..Increment when enabled + * 0b01..Increment when the receive timestamp counter is enabled + * 0b10..Increment when the transmit timestamp counter on another instance is enabled + * 0b11..Increment when the receive timestamp counter on another instance is enabled + */ +#define I2S_TTCR_TSSEL(x) (((uint32_t)(((uint32_t)(x)) << I2S_TTCR_TSSEL_SHIFT)) & I2S_TTCR_TSSEL_MASK) + +#define I2S_TTCR_RTSC_MASK (0x100U) +#define I2S_TTCR_RTSC_SHIFT (8U) +/*! RTSC - Reset Timestamp Counter + * 0b0..No effect + * 0b1..Reset + */ +#define I2S_TTCR_RTSC(x) (((uint32_t)(((uint32_t)(x)) << I2S_TTCR_RTSC_SHIFT)) & I2S_TTCR_RTSC_MASK) + +#define I2S_TTCR_RBC_MASK (0x200U) +#define I2S_TTCR_RBC_SHIFT (9U) +/*! RBC - Reset Bit Counter + * 0b0..No effect + * 0b1..Reset + */ +#define I2S_TTCR_RBC(x) (((uint32_t)(((uint32_t)(x)) << I2S_TTCR_RBC_SHIFT)) & I2S_TTCR_RBC_MASK) +/*! @} */ + +/*! @name TTSR - Transmit Timestamp */ +/*! @{ */ + +#define I2S_TTSR_TSC_MASK (0xFFFFFFFFU) +#define I2S_TTSR_TSC_SHIFT (0U) +/*! TSC - Timestamp Counter */ +#define I2S_TTSR_TSC(x) (((uint32_t)(((uint32_t)(x)) << I2S_TTSR_TSC_SHIFT)) & I2S_TTSR_TSC_MASK) +/*! @} */ + +/*! @name TBCR - Transmit Bit Count */ +/*! @{ */ + +#define I2S_TBCR_BCNT_MASK (0xFFFFFFFFU) +#define I2S_TBCR_BCNT_SHIFT (0U) +/*! BCNT - Bit Counter */ +#define I2S_TBCR_BCNT(x) (((uint32_t)(((uint32_t)(x)) << I2S_TBCR_BCNT_SHIFT)) & I2S_TBCR_BCNT_MASK) +/*! @} */ + +/*! @name TBCTR - Transmit Bit Count Timestamp */ +/*! @{ */ + +#define I2S_TBCTR_BCTS_MASK (0xFFFFFFFFU) +#define I2S_TBCTR_BCTS_SHIFT (0U) +/*! BCTS - Bit Timestamp */ +#define I2S_TBCTR_BCTS(x) (((uint32_t)(((uint32_t)(x)) << I2S_TBCTR_BCTS_SHIFT)) & I2S_TBCTR_BCTS_MASK) +/*! @} */ + +/*! @name RCSR - Receive Control */ +/*! @{ */ + +#define I2S_RCSR_FRDE_MASK (0x1U) +#define I2S_RCSR_FRDE_SHIFT (0U) +/*! FRDE - FIFO Request DMA Enable + * 0b0..Disable + * 0b1..Enable + */ +#define I2S_RCSR_FRDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRDE_SHIFT)) & I2S_RCSR_FRDE_MASK) + +#define I2S_RCSR_FWDE_MASK (0x2U) +#define I2S_RCSR_FWDE_SHIFT (1U) +/*! FWDE - FIFO Warning DMA Enable + * 0b0..Disable + * 0b1..Enable + */ +#define I2S_RCSR_FWDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWDE_SHIFT)) & I2S_RCSR_FWDE_MASK) + +#define I2S_RCSR_FRIE_MASK (0x100U) +#define I2S_RCSR_FRIE_SHIFT (8U) +/*! FRIE - FIFO Request Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define I2S_RCSR_FRIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRIE_SHIFT)) & I2S_RCSR_FRIE_MASK) + +#define I2S_RCSR_FWIE_MASK (0x200U) +#define I2S_RCSR_FWIE_SHIFT (9U) +/*! FWIE - FIFO Warning Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define I2S_RCSR_FWIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWIE_SHIFT)) & I2S_RCSR_FWIE_MASK) + +#define I2S_RCSR_FEIE_MASK (0x400U) +#define I2S_RCSR_FEIE_SHIFT (10U) +/*! FEIE - FIFO Error Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define I2S_RCSR_FEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FEIE_SHIFT)) & I2S_RCSR_FEIE_MASK) + +#define I2S_RCSR_SEIE_MASK (0x800U) +#define I2S_RCSR_SEIE_SHIFT (11U) +/*! SEIE - Sync Error Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define I2S_RCSR_SEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SEIE_SHIFT)) & I2S_RCSR_SEIE_MASK) + +#define I2S_RCSR_WSIE_MASK (0x1000U) +#define I2S_RCSR_WSIE_SHIFT (12U) +/*! WSIE - Word Start Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define I2S_RCSR_WSIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_WSIE_SHIFT)) & I2S_RCSR_WSIE_MASK) + +#define I2S_RCSR_FRF_MASK (0x10000U) +#define I2S_RCSR_FRF_SHIFT (16U) +/*! FRF - FIFO Request Flag + * 0b0..Watermark not reached + * 0b1..Watermark reached + */ +#define I2S_RCSR_FRF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRF_SHIFT)) & I2S_RCSR_FRF_MASK) + +#define I2S_RCSR_FWF_MASK (0x20000U) +#define I2S_RCSR_FWF_SHIFT (17U) +/*! FWF - FIFO Warning Flag + * 0b0..Not full + * 0b1..Full + */ +#define I2S_RCSR_FWF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWF_SHIFT)) & I2S_RCSR_FWF_MASK) + +#define I2S_RCSR_FEF_MASK (0x40000U) +#define I2S_RCSR_FEF_SHIFT (18U) +/*! FEF - FIFO Error Flag + * 0b0..No error + * 0b0..No effect + * 0b1..Receive overflow detected + * 0b1..Clear the flag + */ +#define I2S_RCSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FEF_SHIFT)) & I2S_RCSR_FEF_MASK) + +#define I2S_RCSR_SEF_MASK (0x80000U) +#define I2S_RCSR_SEF_SHIFT (19U) +/*! SEF - Sync Error Flag + * 0b0..Not detected + * 0b0..No effect + * 0b1..Detected + * 0b1..Clear the flag + */ +#define I2S_RCSR_SEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SEF_SHIFT)) & I2S_RCSR_SEF_MASK) + +#define I2S_RCSR_WSF_MASK (0x100000U) +#define I2S_RCSR_WSF_SHIFT (20U) +/*! WSF - Word Start Flag + * 0b0..Not detected + * 0b0..No effect + * 0b1..Detected + * 0b1..Clear the flag + */ +#define I2S_RCSR_WSF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_WSF_SHIFT)) & I2S_RCSR_WSF_MASK) + +#define I2S_RCSR_SR_MASK (0x1000000U) +#define I2S_RCSR_SR_SHIFT (24U) +/*! SR - Software Reset + * 0b0..No effect + * 0b1..Software reset + */ +#define I2S_RCSR_SR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SR_SHIFT)) & I2S_RCSR_SR_MASK) + +#define I2S_RCSR_FR_MASK (0x2000000U) +#define I2S_RCSR_FR_SHIFT (25U) +/*! FR - FIFO Reset + * 0b0..No effect + * 0b1..Reset + */ +#define I2S_RCSR_FR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FR_SHIFT)) & I2S_RCSR_FR_MASK) + +#define I2S_RCSR_BCE_MASK (0x10000000U) +#define I2S_RCSR_BCE_SHIFT (28U) +/*! BCE - Bit Clock Enable + * 0b0..Disable + * 0b1..Enable + */ +#define I2S_RCSR_BCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_BCE_SHIFT)) & I2S_RCSR_BCE_MASK) + +#define I2S_RCSR_DBGE_MASK (0x20000000U) +#define I2S_RCSR_DBGE_SHIFT (29U) +/*! DBGE - Debug Enable + * 0b0..Disable after completing the current frame + * 0b1..Enable + */ +#define I2S_RCSR_DBGE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_DBGE_SHIFT)) & I2S_RCSR_DBGE_MASK) + +#define I2S_RCSR_STOPE_MASK (0x40000000U) +#define I2S_RCSR_STOPE_SHIFT (30U) +/*! STOPE - Stop Enable + * 0b0..Disable + * 0b1..Enable + */ +#define I2S_RCSR_STOPE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_STOPE_SHIFT)) & I2S_RCSR_STOPE_MASK) + +#define I2S_RCSR_RE_MASK (0x80000000U) +#define I2S_RCSR_RE_SHIFT (31U) +/*! RE - Receiver Enable + * 0b0..Disable + * 0b1..Enable (or receiver disabled and not yet reached end of frame) + */ +#define I2S_RCSR_RE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_RE_SHIFT)) & I2S_RCSR_RE_MASK) +/*! @} */ + +/*! @name RCR1 - Receive Configuration 1 */ +/*! @{ */ + +#define I2S_RCR1_RFW_MASK (0x7FU) /* Merged from fields with different position or width, of widths (6, 7), largest definition used */ +#define I2S_RCR1_RFW_SHIFT (0U) +/*! RFW - Receive FIFO Watermark + * 0b0000000..1 + * 0b0000001..2 + * 0b0000010-0b1111110..(RFW value + 1) + * 0b1111111..128 + */ +#define I2S_RCR1_RFW(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR1_RFW_SHIFT)) & I2S_RCR1_RFW_MASK) /* Merged from fields with different position or width, of widths (6, 7), largest definition used */ +/*! @} */ + +/*! @name RCR2 - Receive Configuration 2 */ +/*! @{ */ + +#define I2S_RCR2_DIV_MASK (0xFFU) +#define I2S_RCR2_DIV_SHIFT (0U) +/*! DIV - Bit Clock Divide */ +#define I2S_RCR2_DIV(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_DIV_SHIFT)) & I2S_RCR2_DIV_MASK) + +#define I2S_RCR2_BYP_MASK (0x800000U) +#define I2S_RCR2_BYP_SHIFT (23U) +/*! BYP - Bit Clock Bypass + * 0b0..Disable + * 0b1..Enable + */ +#define I2S_RCR2_BYP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BYP_SHIFT)) & I2S_RCR2_BYP_MASK) + +#define I2S_RCR2_BCD_MASK (0x1000000U) +#define I2S_RCR2_BCD_SHIFT (24U) +/*! BCD - Bit Clock Direction + * 0b0..Generated externally in Target mode + * 0b1..Generated internally in Controller mode + */ +#define I2S_RCR2_BCD(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCD_SHIFT)) & I2S_RCR2_BCD_MASK) + +#define I2S_RCR2_BCP_MASK (0x2000000U) +#define I2S_RCR2_BCP_SHIFT (25U) +/*! BCP - Bit Clock Polarity + * 0b0..Active high + * 0b1..Active low + */ +#define I2S_RCR2_BCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCP_SHIFT)) & I2S_RCR2_BCP_MASK) + +#define I2S_RCR2_MSEL_MASK (0xC000000U) +#define I2S_RCR2_MSEL_SHIFT (26U) +/*! MSEL - MCLK Select + * 0b00..Bus clock + * 0b01..Controller clock (MCLK) option 1 + * 0b10..Controller clock (MCLK) option 2 + * 0b11..Controller clock (MCLK) option 3 + */ +#define I2S_RCR2_MSEL(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_MSEL_SHIFT)) & I2S_RCR2_MSEL_MASK) + +#define I2S_RCR2_BCI_MASK (0x10000000U) +#define I2S_RCR2_BCI_SHIFT (28U) +/*! BCI - Bit Clock Input + * 0b0..Disable + * 0b1..Enable + */ +#define I2S_RCR2_BCI(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCI_SHIFT)) & I2S_RCR2_BCI_MASK) + +#define I2S_RCR2_BCS_MASK (0x20000000U) +#define I2S_RCR2_BCS_SHIFT (29U) +/*! BCS - Bit Clock Swap + * 0b0..Use the normal bit clock source + * 0b1..Swap the bit clock source + */ +#define I2S_RCR2_BCS(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCS_SHIFT)) & I2S_RCR2_BCS_MASK) + +#define I2S_RCR2_SYNC_MASK (0x40000000U) +#define I2S_RCR2_SYNC_SHIFT (30U) +/*! SYNC - Synchronous Mode + * 0b0..Asynchronous mode + * 0b1..Synchronous with transmitter + */ +#define I2S_RCR2_SYNC(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_SYNC_SHIFT)) & I2S_RCR2_SYNC_MASK) +/*! @} */ + +/*! @name RCR3 - Receive Configuration 3 */ +/*! @{ */ + +#define I2S_RCR3_WDFL_MASK (0x1FU) +#define I2S_RCR3_WDFL_SHIFT (0U) +/*! WDFL - Word Flag Configuration + * 0b00000..Word 1 + * 0b00001..Word 2 + * 0b00010-0b11110..Word (WDFL value + 1) + * 0b11111..Word 32 + */ +#define I2S_RCR3_WDFL(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_WDFL_SHIFT)) & I2S_RCR3_WDFL_MASK) + +#define I2S_RCR3_RCE_MASK (0x30000U) /* Merged from fields with different position or width, of widths (1, 2), largest definition used */ +#define I2S_RCR3_RCE_SHIFT (16U) +/*! RCE - Receive Channel Enable */ +#define I2S_RCR3_RCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_RCE_SHIFT)) & I2S_RCR3_RCE_MASK) /* Merged from fields with different position or width, of widths (1, 2), largest definition used */ + +#define I2S_RCR3_CFR_MASK (0x3000000U) +#define I2S_RCR3_CFR_SHIFT (24U) +/*! CFR - Channel FIFO Reset */ +#define I2S_RCR3_CFR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_CFR_SHIFT)) & I2S_RCR3_CFR_MASK) +/*! @} */ + +/*! @name RCR4 - Receive Configuration 4 */ +/*! @{ */ + +#define I2S_RCR4_FSD_MASK (0x1U) +#define I2S_RCR4_FSD_SHIFT (0U) +/*! FSD - Frame Sync Direction + * 0b0..Generated externally in Target mode + * 0b1..Generated internally in Controller mode + */ +#define I2S_RCR4_FSD(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSD_SHIFT)) & I2S_RCR4_FSD_MASK) + +#define I2S_RCR4_FSP_MASK (0x2U) +#define I2S_RCR4_FSP_SHIFT (1U) +/*! FSP - Frame Sync Polarity + * 0b0..Active high + * 0b1..Active low + */ +#define I2S_RCR4_FSP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSP_SHIFT)) & I2S_RCR4_FSP_MASK) + +#define I2S_RCR4_ONDEM_MASK (0x4U) +#define I2S_RCR4_ONDEM_SHIFT (2U) +/*! ONDEM - On-Demand Mode + * 0b0..Generated continuously + * 0b1..Generated when the FIFO warning flag is 0 + */ +#define I2S_RCR4_ONDEM(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_ONDEM_SHIFT)) & I2S_RCR4_ONDEM_MASK) + +#define I2S_RCR4_FSE_MASK (0x8U) +#define I2S_RCR4_FSE_SHIFT (3U) +/*! FSE - Frame Sync Early + * 0b0..First bit of the frame + * 0b1..One bit before the first bit of the frame + */ +#define I2S_RCR4_FSE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSE_SHIFT)) & I2S_RCR4_FSE_MASK) + +#define I2S_RCR4_MF_MASK (0x10U) +#define I2S_RCR4_MF_SHIFT (4U) +/*! MF - MSB First + * 0b0..LSB + * 0b1..MSB + */ +#define I2S_RCR4_MF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_MF_SHIFT)) & I2S_RCR4_MF_MASK) + +#define I2S_RCR4_SYWD_MASK (0x1F00U) +#define I2S_RCR4_SYWD_SHIFT (8U) +/*! SYWD - Sync Width + * 0b00000..1 + * 0b00001..2 + * 0b00010-0b11110..(SYWD value + 1) + * 0b11111..32 + */ +#define I2S_RCR4_SYWD(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_SYWD_SHIFT)) & I2S_RCR4_SYWD_MASK) + +#define I2S_RCR4_FRSZ_MASK (0x1F0000U) +#define I2S_RCR4_FRSZ_SHIFT (16U) +/*! FRSZ - Frame Size + * 0b00000..1 + * 0b00001..2 + * 0b00010-0b11110..(FRSZ value + 1) + * 0b11111..32 + */ +#define I2S_RCR4_FRSZ(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FRSZ_SHIFT)) & I2S_RCR4_FRSZ_MASK) + +#define I2S_RCR4_FPACK_MASK (0x3000000U) +#define I2S_RCR4_FPACK_SHIFT (24U) +/*! FPACK - FIFO Packing Mode + * 0b00..Disable + * 0b01..Reserved + * 0b10..Enable 8-bit FIFO packing + * 0b11..Enable 16-bit FIFO packing + */ +#define I2S_RCR4_FPACK(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FPACK_SHIFT)) & I2S_RCR4_FPACK_MASK) + +#define I2S_RCR4_FCOMB_MASK (0xC000000U) +#define I2S_RCR4_FCOMB_SHIFT (26U) +/*! FCOMB - FIFO Combine Mode + * 0b00..Disable + * 0b01..Enable on FIFO writes (from receive shift registers) + * 0b10..Enable on FIFO reads (by software) + * 0b11..Enable on FIFO writes (from receive shift registers) and reads (by software) + */ +#define I2S_RCR4_FCOMB(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FCOMB_SHIFT)) & I2S_RCR4_FCOMB_MASK) + +#define I2S_RCR4_FCONT_MASK (0x10000000U) +#define I2S_RCR4_FCONT_SHIFT (28U) +/*! FCONT - FIFO Continue on Error + * 0b0..From the start of the next frame after the FIFO error flag is cleared + * 0b1..From the same word that caused the FIFO error to become 1 after the FIFO warning flag is cleared + */ +#define I2S_RCR4_FCONT(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FCONT_SHIFT)) & I2S_RCR4_FCONT_MASK) +/*! @} */ + +/*! @name RCR5 - Receive Configuration 5 */ +/*! @{ */ + +#define I2S_RCR5_FBT_MASK (0x1F00U) +#define I2S_RCR5_FBT_SHIFT (8U) +/*! FBT - First Bit Shifted + * 0b00000..0 + * 0b00001-0b11110..FBT value + * 0b11111..31 + */ +#define I2S_RCR5_FBT(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_FBT_SHIFT)) & I2S_RCR5_FBT_MASK) + +#define I2S_RCR5_W0W_MASK (0x1F0000U) +#define I2S_RCR5_W0W_SHIFT (16U) +/*! W0W - Word 0 Width + * 0b00000..1 + * 0b00001..2 + * 0b00010-0b11110..(W0W value + 1) + * 0b11111..32 + */ +#define I2S_RCR5_W0W(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_W0W_SHIFT)) & I2S_RCR5_W0W_MASK) + +#define I2S_RCR5_WNW_MASK (0x1F000000U) +#define I2S_RCR5_WNW_SHIFT (24U) +/*! WNW - Word N Width + * 0b00111..8 + * 0b01000..9 + * 0b01001-0b11110..(WNW value + 1) + * 0b11111..32 + */ +#define I2S_RCR5_WNW(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_WNW_SHIFT)) & I2S_RCR5_WNW_MASK) +/*! @} */ + +/*! @name RDR - Receive Data */ +/*! @{ */ + +#define I2S_RDR_RDR_MASK (0xFFFFFFFFU) +#define I2S_RDR_RDR_SHIFT (0U) +/*! RDR - Receive Data */ +#define I2S_RDR_RDR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RDR_RDR_SHIFT)) & I2S_RDR_RDR_MASK) +/*! @} */ + +/* The count of I2S_RDR */ +#define I2S_RDR_COUNT (2U) + +/*! @name RFR - Receive FIFO */ +/*! @{ */ + +#define I2S_RFR_RFP_MASK (0xFFU) /* Merged from fields with different position or width, of widths (7, 8), largest definition used */ +#define I2S_RFR_RFP_SHIFT (0U) +/*! RFP - Read FIFO Pointer */ +#define I2S_RFR_RFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RFR_RFP_SHIFT)) & I2S_RFR_RFP_MASK) /* Merged from fields with different position or width, of widths (7, 8), largest definition used */ + +#define I2S_RFR_RCP_MASK (0x8000U) +#define I2S_RFR_RCP_SHIFT (15U) +/*! RCP - Read Channel Pointer + * 0b0..No effect + * 0b1..Next FIFO to be read + */ +#define I2S_RFR_RCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RFR_RCP_SHIFT)) & I2S_RFR_RCP_MASK) + +#define I2S_RFR_WFP_MASK (0xFF0000U) /* Merged from fields with different position or width, of widths (7, 8), largest definition used */ +#define I2S_RFR_WFP_SHIFT (16U) +/*! WFP - Write FIFO Pointer */ +#define I2S_RFR_WFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RFR_WFP_SHIFT)) & I2S_RFR_WFP_MASK) /* Merged from fields with different position or width, of widths (7, 8), largest definition used */ +/*! @} */ + +/* The count of I2S_RFR */ +#define I2S_RFR_COUNT (2U) + +/*! @name RMR - Receive Mask */ +/*! @{ */ + +#define I2S_RMR_RWM_MASK (0xFFFFFFFFU) +#define I2S_RMR_RWM_SHIFT (0U) +/*! RWM - Receive Word Mask + * 0b00000000000000000000000000000000..Enable + * 0b00000000000000000000000000000001..Mask + */ +#define I2S_RMR_RWM(x) (((uint32_t)(((uint32_t)(x)) << I2S_RMR_RWM_SHIFT)) & I2S_RMR_RWM_MASK) +/*! @} */ + +/*! @name RTCR - Receive Timestamp Control */ +/*! @{ */ + +#define I2S_RTCR_TSEN_MASK (0x1U) +#define I2S_RTCR_TSEN_SHIFT (0U) +/*! TSEN - Timestamp Enable + * 0b0..Disable + * 0b1..Enable + */ +#define I2S_RTCR_TSEN(x) (((uint32_t)(((uint32_t)(x)) << I2S_RTCR_TSEN_SHIFT)) & I2S_RTCR_TSEN_MASK) + +#define I2S_RTCR_TSINC_MASK (0x2U) +#define I2S_RTCR_TSINC_SHIFT (1U) +/*! TSINC - Timestamp Increment + * 0b0..When enabled and after the bit counter has incremented + * 0b1..When enabled + */ +#define I2S_RTCR_TSINC(x) (((uint32_t)(((uint32_t)(x)) << I2S_RTCR_TSINC_SHIFT)) & I2S_RTCR_TSINC_MASK) + +#define I2S_RTCR_TSSEL_MASK (0xCU) +#define I2S_RTCR_TSSEL_SHIFT (2U) +/*! TSSEL - Timestamp Select + * 0b00..Increment when enabled + * 0b01..Increment when the transmit timestamp counter is enabled + * 0b10..Increment when the receive timestamp counter on another instance is enabled + * 0b11..Increment when the transmit timestamp counter on another instance is enabled + */ +#define I2S_RTCR_TSSEL(x) (((uint32_t)(((uint32_t)(x)) << I2S_RTCR_TSSEL_SHIFT)) & I2S_RTCR_TSSEL_MASK) + +#define I2S_RTCR_RTSC_MASK (0x100U) +#define I2S_RTCR_RTSC_SHIFT (8U) +/*! RTSC - Reset Timestamp Counter + * 0b0..No effect + * 0b1..Reset + */ +#define I2S_RTCR_RTSC(x) (((uint32_t)(((uint32_t)(x)) << I2S_RTCR_RTSC_SHIFT)) & I2S_RTCR_RTSC_MASK) + +#define I2S_RTCR_RBC_MASK (0x200U) +#define I2S_RTCR_RBC_SHIFT (9U) +/*! RBC - Reset Bit Counter + * 0b0..No effect + * 0b1..Reset + */ +#define I2S_RTCR_RBC(x) (((uint32_t)(((uint32_t)(x)) << I2S_RTCR_RBC_SHIFT)) & I2S_RTCR_RBC_MASK) +/*! @} */ + +/*! @name RTSR - Receive Timestamp */ +/*! @{ */ + +#define I2S_RTSR_TSC_MASK (0xFFFFFFFFU) +#define I2S_RTSR_TSC_SHIFT (0U) +/*! TSC - Timestamp Counter */ +#define I2S_RTSR_TSC(x) (((uint32_t)(((uint32_t)(x)) << I2S_RTSR_TSC_SHIFT)) & I2S_RTSR_TSC_MASK) +/*! @} */ + +/*! @name RBCR - Receive Bit Count */ +/*! @{ */ + +#define I2S_RBCR_BCNT_MASK (0xFFFFFFFFU) +#define I2S_RBCR_BCNT_SHIFT (0U) +/*! BCNT - Bit Counter */ +#define I2S_RBCR_BCNT(x) (((uint32_t)(((uint32_t)(x)) << I2S_RBCR_BCNT_SHIFT)) & I2S_RBCR_BCNT_MASK) +/*! @} */ + +/*! @name RBCTR - Receive Bit Count Timestamp */ +/*! @{ */ + +#define I2S_RBCTR_BCTS_MASK (0xFFFFFFFFU) +#define I2S_RBCTR_BCTS_SHIFT (0U) +/*! BCTS - Bit Timestamp */ +#define I2S_RBCTR_BCTS(x) (((uint32_t)(((uint32_t)(x)) << I2S_RBCTR_BCTS_SHIFT)) & I2S_RBCTR_BCTS_MASK) +/*! @} */ + +/*! @name MCR - MCLK Control */ +/*! @{ */ + +#define I2S_MCR_DIV_MASK (0xFFU) +#define I2S_MCR_DIV_SHIFT (0U) +/*! DIV - MCLK Post Divide */ +#define I2S_MCR_DIV(x) (((uint32_t)(((uint32_t)(x)) << I2S_MCR_DIV_SHIFT)) & I2S_MCR_DIV_MASK) + +#define I2S_MCR_DIVEN_MASK (0x800000U) +#define I2S_MCR_DIVEN_SHIFT (23U) +/*! DIVEN - MCLK Post Divide Enable + * 0b0..Disable + * 0b1..Enable + */ +#define I2S_MCR_DIVEN(x) (((uint32_t)(((uint32_t)(x)) << I2S_MCR_DIVEN_SHIFT)) & I2S_MCR_DIVEN_MASK) + +#define I2S_MCR_MSEL_MASK (0x3000000U) +#define I2S_MCR_MSEL_SHIFT (24U) +/*! MSEL - MCLK Select + * 0b00..Controller clock (MCLK) option 1 + * 0b01..Reserved + * 0b10..Controller clock (MCLK) option 2 + * 0b11..Controller clock (MCLK) option 3 + */ +#define I2S_MCR_MSEL(x) (((uint32_t)(((uint32_t)(x)) << I2S_MCR_MSEL_SHIFT)) & I2S_MCR_MSEL_MASK) + +#define I2S_MCR_MOE_MASK (0x40000000U) +#define I2S_MCR_MOE_SHIFT (30U) +/*! MOE - MCLK Output Enable + * 0b0..Input + * 0b1..Output + */ +#define I2S_MCR_MOE(x) (((uint32_t)(((uint32_t)(x)) << I2S_MCR_MOE_SHIFT)) & I2S_MCR_MOE_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group I2S_Register_Masks */ + + +/* I2S - Peripheral instance base addresses */ +/** Peripheral SAI1 base address */ +#define SAI1_BASE (0x443B0000u) +/** Peripheral SAI1 base pointer */ +#define SAI1 ((I2S_Type *)SAI1_BASE) +/** Peripheral SAI2 base address */ +#define SAI2_BASE (0x42650000u) +/** Peripheral SAI2 base pointer */ +#define SAI2 ((I2S_Type *)SAI2_BASE) +/** Peripheral SAI3 base address */ +#define SAI3_BASE (0x42660000u) +/** Peripheral SAI3 base pointer */ +#define SAI3 ((I2S_Type *)SAI3_BASE) +/** Array initializer of I2S peripheral base addresses */ +#define I2S_BASE_ADDRS { 0u, SAI1_BASE, SAI2_BASE, SAI3_BASE } +/** Array initializer of I2S peripheral base pointers */ +#define I2S_BASE_PTRS { (I2S_Type *)0u, SAI1, SAI2, SAI3 } +/** Interrupt vectors for the I2S peripheral type */ +#define I2S_RX_IRQS { NotAvail_IRQn, SAI1_IRQn, SAI2_IRQn, SAI3_IRQn } +#define I2S_TX_IRQS { NotAvail_IRQn, SAI1_IRQn, SAI2_IRQn, SAI3_IRQn } + +/*! + * @} + */ /* end of group I2S_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- I3C Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup I3C_Peripheral_Access_Layer I3C Peripheral Access Layer + * @{ + */ + +/** I3C - Register Layout Typedef */ +typedef struct { + __IO uint32_t MCONFIG; /**< Controller Configuration, offset: 0x0 */ + __IO uint32_t SCONFIG; /**< Target Configuration, offset: 0x4 */ + __IO uint32_t SSTATUS; /**< Target Status, offset: 0x8 */ + __IO uint32_t SCTRL; /**< Target Control, offset: 0xC */ + __IO uint32_t SINTSET; /**< Target Interrupt Set, offset: 0x10 */ + __IO uint32_t SINTCLR; /**< Target Interrupt Clear, offset: 0x14 */ + __I uint32_t SINTMASKED; /**< Target Interrupt Mask, offset: 0x18 */ + __IO uint32_t SERRWARN; /**< Target Errors and Warnings, offset: 0x1C */ + __IO uint32_t SDMACTRL; /**< Target DMA Control, offset: 0x20 */ + uint8_t RESERVED_0[8]; + __IO uint32_t SDATACTRL; /**< Target Data Control, offset: 0x2C */ + __O uint32_t SWDATAB; /**< Target Write Data Byte, offset: 0x30 */ + __O uint32_t SWDATABE; /**< Target Write Data Byte End, offset: 0x34 */ + __O uint32_t SWDATAH; /**< Target Write Data Halfword, offset: 0x38 */ + __O uint32_t SWDATAHE; /**< Target Write Data Halfword End, offset: 0x3C */ + __I uint32_t SRDATAB; /**< Target Read Data Byte, offset: 0x40 */ + uint8_t RESERVED_1[4]; + __I uint32_t SRDATAH; /**< Target Read Data Halfword, offset: 0x48 */ + uint8_t RESERVED_2[8]; + union { /* offset: 0x54 */ + __O uint32_t SWDATAB1; /**< Target Write Data Byte, offset: 0x54 */ + __O uint32_t SWDATAH1; /**< Target Write Data Halfword, offset: 0x54 */ + }; + uint8_t RESERVED_3[4]; + __I uint32_t SCAPABILITIES2; /**< Target Capabilities 2, offset: 0x5C */ + __I uint32_t SCAPABILITIES; /**< Target Capabilities, offset: 0x60 */ + uint8_t RESERVED_4[4]; + __IO uint32_t SMAXLIMITS; /**< Target Maximum Limits, offset: 0x68 */ + __IO uint32_t SIDPARTNO; /**< Target ID Part Number, offset: 0x6C */ + __IO uint32_t SIDEXT; /**< Target ID Extension, offset: 0x70 */ + __IO uint32_t SVENDORID; /**< Target Vendor ID, offset: 0x74 */ + __IO uint32_t STCCLOCK; /**< Target Time Control Clock, offset: 0x78 */ + __I uint32_t SMSGMAPADDR; /**< Target Message Map Address, offset: 0x7C */ + __IO uint32_t MCONFIG_EXT; /**< Controller Extended Configuration, offset: 0x80 */ + __IO uint32_t MCTRL; /**< Controller Control, offset: 0x84 */ + __IO uint32_t MSTATUS; /**< Controller Status, offset: 0x88 */ + __IO uint32_t MIBIRULES; /**< Controller In-band Interrupt Registry and Rules, offset: 0x8C */ + __IO uint32_t MINTSET; /**< Controller Interrupt Set, offset: 0x90 */ + __IO uint32_t MINTCLR; /**< Controller Interrupt Clear, offset: 0x94 */ + __I uint32_t MINTMASKED; /**< Controller Interrupt Mask, offset: 0x98 */ + __IO uint32_t MERRWARN; /**< Controller Errors and Warnings, offset: 0x9C */ + __IO uint32_t MDMACTRL; /**< Controller DMA Control, offset: 0xA0 */ + uint8_t RESERVED_5[8]; + __IO uint32_t MDATACTRL; /**< Controller Data Control, offset: 0xAC */ + __O uint32_t MWDATAB; /**< Controller Write Data Byte, offset: 0xB0 */ + __O uint32_t MWDATABE; /**< Controller Write Data Byte End, offset: 0xB4 */ + __O uint32_t MWDATAH; /**< Controller Write Data Halfword, offset: 0xB8 */ + __O uint32_t MWDATAHE; /**< Controller Write Data Halfword End, offset: 0xBC */ + __I uint32_t MRDATAB; /**< Controller Read Data Byte, offset: 0xC0 */ + uint8_t RESERVED_6[4]; + __I uint32_t MRDATAH; /**< Controller Read Data Halfword, offset: 0xC8 */ + union { /* offset: 0xCC */ + __O uint32_t MWDATAB1; /**< Controller Write Byte Data 1 (to Bus), offset: 0xCC */ + __O uint32_t MWDATAH1; /**< Controller Write Halfword Data (to Bus), offset: 0xCC */ + }; + union { /* offset: 0xD0 */ + __O uint32_t MWMSG_SDR_CONTROL; /**< Controller Write Message Control in SDR mode, offset: 0xD0 */ + __O uint32_t MWMSG_SDR_DATA; /**< Controller Write Message Data in SDR mode, offset: 0xD0 */ + }; + __I uint32_t MRMSG_SDR; /**< Controller Read Message in SDR mode, offset: 0xD4 */ + union { /* offset: 0xD8 */ + __O uint32_t MWMSG_DDR_CONTROL; /**< Controller Write Message in DDR mode: First Control Word, offset: 0xD8 */ + __O uint32_t MWMSG_DDR_CONTROL2; /**< Controller Write Message in DDR Mode Control 2, offset: 0xD8 */ + __O uint32_t MWMSG_DDR_DATA; /**< Controller Write Message Data in DDR mode, offset: 0xD8 */ + }; + __I uint32_t MRMSG_DDR; /**< Controller Read Message in DDR mode, offset: 0xDC */ + uint8_t RESERVED_7[4]; + __IO uint32_t MDYNADDR; /**< Controller Dynamic Address, offset: 0xE4 */ + uint8_t RESERVED_8[24]; + __IO uint32_t SRSTACTTIME; /**< Timing Rules for Target Reset Recovery, offset: 0x100 */ + uint8_t RESERVED_9[8]; + __IO uint32_t SCCCMASK; /**< CCC Mask for Unhandled CCCs, offset: 0x10C */ + __IO uint32_t SERRWARNMASK; /**< Target Errors and Warnings Mask, offset: 0x110 */ + uint8_t RESERVED_10[8]; + __I uint32_t SMAPCTRL0; /**< Map Feature Control 0, offset: 0x11C */ + __IO uint32_t SMAPCTRL1; /**< Map Feature Control 1, offset: 0x120 */ + uint8_t RESERVED_11[28]; + __IO uint32_t IBIEXT1; /**< Extended IBI Data 1, offset: 0x140 */ + __IO uint32_t IBIEXT2; /**< Extended IBI Data 2, offset: 0x144 */ + uint8_t RESERVED_12[3752]; + __IO uint32_t SELFRESET; /**< Self Reset, offset: 0xFF0 */ +} I3C_Type; + +/* ---------------------------------------------------------------------------- + -- I3C Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup I3C_Register_Masks I3C Register Masks + * @{ + */ + +/*! @name MCONFIG - Controller Configuration */ +/*! @{ */ + +#define I3C_MCONFIG_MSTENA_MASK (0x3U) +#define I3C_MCONFIG_MSTENA_SHIFT (0U) +/*! MSTENA - Controller Enable + * 0b00..CONTROLLER_OFF + * 0b01..CONTROLLER_ON + * 0b10..CONTROLLER_CAPABLE + * 0b11..I2C_CONTROLLER_MODE + */ +#define I3C_MCONFIG_MSTENA(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_MSTENA_SHIFT)) & I3C_MCONFIG_MSTENA_MASK) + +#define I3C_MCONFIG_DISTO_MASK (0x8U) +#define I3C_MCONFIG_DISTO_SHIFT (3U) +/*! DISTO - Disable Timeout + * 0b0..Enabled + * 0b1..Disabled, if configured + */ +#define I3C_MCONFIG_DISTO(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_DISTO_SHIFT)) & I3C_MCONFIG_DISTO_MASK) + +#define I3C_MCONFIG_HKEEP_MASK (0x30U) +#define I3C_MCONFIG_HKEEP_SHIFT (4U) +/*! HKEEP - High-Keeper + * 0b00..None + * 0b01..WIRED_IN + * 0b10..PASSIVE_SDA + * 0b11..PASSIVE_ON_SDA_SCL + */ +#define I3C_MCONFIG_HKEEP(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_HKEEP_SHIFT)) & I3C_MCONFIG_HKEEP_MASK) + +#define I3C_MCONFIG_ODSTOP_MASK (0x40U) +#define I3C_MCONFIG_ODSTOP_SHIFT (6U) +/*! ODSTOP - Open Drain Stop + * 0b0..Disable + * 0b1..Enable + */ +#define I3C_MCONFIG_ODSTOP(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_ODSTOP_SHIFT)) & I3C_MCONFIG_ODSTOP_MASK) + +#define I3C_MCONFIG_PPBAUD_MASK (0xF00U) +#define I3C_MCONFIG_PPBAUD_SHIFT (8U) +/*! PPBAUD - Push-Pull Baud Rate */ +#define I3C_MCONFIG_PPBAUD(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_PPBAUD_SHIFT)) & I3C_MCONFIG_PPBAUD_MASK) + +#define I3C_MCONFIG_PPLOW_MASK (0xF000U) +#define I3C_MCONFIG_PPLOW_SHIFT (12U) +/*! PPLOW - Push-Pull Low */ +#define I3C_MCONFIG_PPLOW(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_PPLOW_SHIFT)) & I3C_MCONFIG_PPLOW_MASK) + +#define I3C_MCONFIG_ODBAUD_MASK (0xFF0000U) +#define I3C_MCONFIG_ODBAUD_SHIFT (16U) +/*! ODBAUD - Open Drain Baud Rate */ +#define I3C_MCONFIG_ODBAUD(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_ODBAUD_SHIFT)) & I3C_MCONFIG_ODBAUD_MASK) + +#define I3C_MCONFIG_ODHPP_MASK (0x1000000U) +#define I3C_MCONFIG_ODHPP_SHIFT (24U) +/*! ODHPP - Open Drain High Push-Pull + * 0b0..Disable + * 0b1..Enable + */ +#define I3C_MCONFIG_ODHPP(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_ODHPP_SHIFT)) & I3C_MCONFIG_ODHPP_MASK) + +#define I3C_MCONFIG_SKEW_MASK (0xE000000U) +#define I3C_MCONFIG_SKEW_SHIFT (25U) +/*! SKEW - Skew */ +#define I3C_MCONFIG_SKEW(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_SKEW_SHIFT)) & I3C_MCONFIG_SKEW_MASK) + +#define I3C_MCONFIG_I2CBAUD_MASK (0xF0000000U) +#define I3C_MCONFIG_I2CBAUD_SHIFT (28U) +/*! I2CBAUD - I2C Baud Rate */ +#define I3C_MCONFIG_I2CBAUD(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_I2CBAUD_SHIFT)) & I3C_MCONFIG_I2CBAUD_MASK) +/*! @} */ + +/*! @name SCONFIG - Target Configuration */ +/*! @{ */ + +#define I3C_SCONFIG_SLVENA_MASK (0x1U) +#define I3C_SCONFIG_SLVENA_SHIFT (0U) +/*! SLVENA - Target Enable + * 0b0..Disable + * 0b1..Enable + */ +#define I3C_SCONFIG_SLVENA(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCONFIG_SLVENA_SHIFT)) & I3C_SCONFIG_SLVENA_MASK) + +#define I3C_SCONFIG_NACK_MASK (0x2U) +#define I3C_SCONFIG_NACK_SHIFT (1U) +/*! NACK - Not Acknowledge + * 0b0..Always disable NACK mode + * 0b1..Always enable NACK mode (works normally) + */ +#define I3C_SCONFIG_NACK(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCONFIG_NACK_SHIFT)) & I3C_SCONFIG_NACK_MASK) + +#define I3C_SCONFIG_MATCHSS_MASK (0x4U) +#define I3C_SCONFIG_MATCHSS_SHIFT (2U) +/*! MATCHSS - Match Start or Stop + * 0b0..Disable + * 0b1..Enable + */ +#define I3C_SCONFIG_MATCHSS(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCONFIG_MATCHSS_SHIFT)) & I3C_SCONFIG_MATCHSS_MASK) + +#define I3C_SCONFIG_S0IGNORE_MASK (0x8U) +#define I3C_SCONFIG_S0IGNORE_SHIFT (3U) +/*! S0IGNORE - Ignore TE0 or TE1 Errors + * 0b0..Do not ignore TE0 or TE1 errors + * 0b1..Ignore TE0 or TE1 errors + */ +#define I3C_SCONFIG_S0IGNORE(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCONFIG_S0IGNORE_SHIFT)) & I3C_SCONFIG_S0IGNORE_MASK) + +#define I3C_SCONFIG_HDROK_MASK (0x10U) +#define I3C_SCONFIG_HDROK_SHIFT (4U) +/*! HDROK - HDR OK + * 0b0..Disable HDR OK + * 0b1..Enable HDR OK + */ +#define I3C_SCONFIG_HDROK(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCONFIG_HDROK_SHIFT)) & I3C_SCONFIG_HDROK_MASK) + +#define I3C_SCONFIG_OFFLINE_MASK (0x200U) +#define I3C_SCONFIG_OFFLINE_SHIFT (9U) +/*! OFFLINE - Offline + * 0b0..Disable + * 0b1..Enable + */ +#define I3C_SCONFIG_OFFLINE(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCONFIG_OFFLINE_SHIFT)) & I3C_SCONFIG_OFFLINE_MASK) + +#define I3C_SCONFIG_BAMATCH_MASK (0x3F0000U) +#define I3C_SCONFIG_BAMATCH_SHIFT (16U) +/*! BAMATCH - Bus Available Match */ +#define I3C_SCONFIG_BAMATCH(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCONFIG_BAMATCH_SHIFT)) & I3C_SCONFIG_BAMATCH_MASK) + +#define I3C_SCONFIG_SADDR_MASK (0xFE000000U) +#define I3C_SCONFIG_SADDR_SHIFT (25U) +/*! SADDR - Static Address */ +#define I3C_SCONFIG_SADDR(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCONFIG_SADDR_SHIFT)) & I3C_SCONFIG_SADDR_MASK) +/*! @} */ + +/*! @name SSTATUS - Target Status */ +/*! @{ */ + +#define I3C_SSTATUS_STNOTSTOP_MASK (0x1U) +#define I3C_SSTATUS_STNOTSTOP_SHIFT (0U) +/*! STNOTSTOP - Status not Stop + * 0b0..In STOP condition + * 0b1..Busy + */ +#define I3C_SSTATUS_STNOTSTOP(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_STNOTSTOP_SHIFT)) & I3C_SSTATUS_STNOTSTOP_MASK) + +#define I3C_SSTATUS_STMSG_MASK (0x2U) +#define I3C_SSTATUS_STMSG_SHIFT (1U) +/*! STMSG - Status Message + * 0b0..Idle + * 0b1..Busy + */ +#define I3C_SSTATUS_STMSG(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_STMSG_SHIFT)) & I3C_SSTATUS_STMSG_MASK) + +#define I3C_SSTATUS_STCCCH_MASK (0x4U) +#define I3C_SSTATUS_STCCCH_SHIFT (2U) +/*! STCCCH - Status Common Command Code Handler + * 0b0..No CCC message handled + * 0b1..Handled automatically + */ +#define I3C_SSTATUS_STCCCH(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_STCCCH_SHIFT)) & I3C_SSTATUS_STCCCH_MASK) + +#define I3C_SSTATUS_STREQRD_MASK (0x8U) +#define I3C_SSTATUS_STREQRD_SHIFT (3U) +/*! STREQRD - Status Request Read + * 0b0..Not an SDR read + * 0b1..SDR read from this target or an IBI is being pushed out + */ +#define I3C_SSTATUS_STREQRD(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_STREQRD_SHIFT)) & I3C_SSTATUS_STREQRD_MASK) + +#define I3C_SSTATUS_STREQWR_MASK (0x10U) +#define I3C_SSTATUS_STREQWR_SHIFT (4U) +/*! STREQWR - Status Request Write + * 0b0..Not an SDR write + * 0b1..SDR write data from the controller, but not in ENTDAA mode + */ +#define I3C_SSTATUS_STREQWR(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_STREQWR_SHIFT)) & I3C_SSTATUS_STREQWR_MASK) + +#define I3C_SSTATUS_STDAA_MASK (0x20U) +#define I3C_SSTATUS_STDAA_SHIFT (5U) +/*! STDAA - Status Dynamic Address Assignment + * 0b0..Not in ENTDAA mode + * 0b1..In ENTDAA mode + */ +#define I3C_SSTATUS_STDAA(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_STDAA_SHIFT)) & I3C_SSTATUS_STDAA_MASK) + +#define I3C_SSTATUS_STHDR_MASK (0x40U) +#define I3C_SSTATUS_STHDR_SHIFT (6U) +/*! STHDR - Status High Data Rate + * 0b0..I3C bus not in HDR-DDR mode + * 0b1..I3C bus in HDR-DDR mode + */ +#define I3C_SSTATUS_STHDR(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_STHDR_SHIFT)) & I3C_SSTATUS_STHDR_MASK) + +#define I3C_SSTATUS_START_MASK (0x100U) +#define I3C_SSTATUS_START_SHIFT (8U) +/*! START - Start Flag + * 0b0..Not detected + * 0b0..No effect + * 0b1..Detected + * 0b1..Clear the flag + */ +#define I3C_SSTATUS_START(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_START_SHIFT)) & I3C_SSTATUS_START_MASK) + +#define I3C_SSTATUS_MATCHED_MASK (0x200U) +#define I3C_SSTATUS_MATCHED_SHIFT (9U) +/*! MATCHED - Matched Flag + * 0b0..Header not matched + * 0b0..No effect + * 0b1..Header matched + * 0b1..Clear the flag + */ +#define I3C_SSTATUS_MATCHED(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_MATCHED_SHIFT)) & I3C_SSTATUS_MATCHED_MASK) + +#define I3C_SSTATUS_STOP_MASK (0x400U) +#define I3C_SSTATUS_STOP_SHIFT (10U) +/*! STOP - Stop Flag + * 0b0..No Stopped state detected + * 0b0..No effect + * 0b1..Stopped state detected + * 0b1..Clear the flag + */ +#define I3C_SSTATUS_STOP(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_STOP_SHIFT)) & I3C_SSTATUS_STOP_MASK) + +#define I3C_SSTATUS_RX_PEND_MASK (0x800U) +#define I3C_SSTATUS_RX_PEND_SHIFT (11U) +/*! RX_PEND - Received Message Pending + * 0b0..No received message pending + * 0b1..Received message pending + */ +#define I3C_SSTATUS_RX_PEND(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_RX_PEND_SHIFT)) & I3C_SSTATUS_RX_PEND_MASK) + +#define I3C_SSTATUS_TXNOTFULL_MASK (0x1000U) +#define I3C_SSTATUS_TXNOTFULL_SHIFT (12U) +/*! TXNOTFULL - Transmit Buffer Not Full + * 0b0..Transmit buffer full + * 0b1..Transmit buffer not full + */ +#define I3C_SSTATUS_TXNOTFULL(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_TXNOTFULL_SHIFT)) & I3C_SSTATUS_TXNOTFULL_MASK) + +#define I3C_SSTATUS_DACHG_MASK (0x2000U) +#define I3C_SSTATUS_DACHG_SHIFT (13U) +/*! DACHG - Dynamic Address Change Flag + * 0b0..No DA change detected + * 0b0..No effect + * 0b1..DA change detected + * 0b1..Clear the flag + */ +#define I3C_SSTATUS_DACHG(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_DACHG_SHIFT)) & I3C_SSTATUS_DACHG_MASK) + +#define I3C_SSTATUS_CCC_MASK (0x4000U) +#define I3C_SSTATUS_CCC_SHIFT (14U) +/*! CCC - Common Command Code Flag + * 0b0..CCC not received + * 0b0..No effect + * 0b1..CCC received + * 0b1..Clear the flag + */ +#define I3C_SSTATUS_CCC(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_CCC_SHIFT)) & I3C_SSTATUS_CCC_MASK) + +#define I3C_SSTATUS_ERRWARN_MASK (0x8000U) +#define I3C_SSTATUS_ERRWARN_SHIFT (15U) +/*! ERRWARN - Error Warning */ +#define I3C_SSTATUS_ERRWARN(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_ERRWARN_SHIFT)) & I3C_SSTATUS_ERRWARN_MASK) + +#define I3C_SSTATUS_HDRMATCH_MASK (0x10000U) +#define I3C_SSTATUS_HDRMATCH_SHIFT (16U) +/*! HDRMATCH - High Data Rate Command Match Flag + * 0b0..Did not match + * 0b0..No effect + * 0b1..Matched the I3C dynamic address + * 0b1..Clear the flag + */ +#define I3C_SSTATUS_HDRMATCH(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_HDRMATCH_SHIFT)) & I3C_SSTATUS_HDRMATCH_MASK) + +#define I3C_SSTATUS_CHANDLED_MASK (0x20000U) +#define I3C_SSTATUS_CHANDLED_SHIFT (17U) +/*! CHANDLED - Common Command Code Handled Flag + * 0b0..CCC handling not in progress + * 0b0..No effect + * 0b1..CCC handling in progress + * 0b1..Clear the flag + */ +#define I3C_SSTATUS_CHANDLED(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_CHANDLED_SHIFT)) & I3C_SSTATUS_CHANDLED_MASK) + +#define I3C_SSTATUS_EVENT_MASK (0x40000U) +#define I3C_SSTATUS_EVENT_SHIFT (18U) +/*! EVENT - Event Flag + * 0b0..No event occurred + * 0b0..No effect + * 0b1..IBI, CR, or HJ occurred + * 0b1..Clear the flag + */ +#define I3C_SSTATUS_EVENT(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_EVENT_SHIFT)) & I3C_SSTATUS_EVENT_MASK) + +#define I3C_SSTATUS_SLVRST_MASK (0x80000U) +#define I3C_SSTATUS_SLVRST_SHIFT (19U) +/*! SLVRST - Target Reset Flag */ +#define I3C_SSTATUS_SLVRST(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_SLVRST_SHIFT)) & I3C_SSTATUS_SLVRST_MASK) + +#define I3C_SSTATUS_EVDET_MASK (0x300000U) +#define I3C_SSTATUS_EVDET_SHIFT (20U) +/*! EVDET - Event Details + * 0b00..NONE (no event or no pending event) + * 0b01..NO_REQUEST (request is not sent yet; either there is no START condition yet, or is waiting for Bus-Available or Bus-Idle (HJ)) + * 0b10..NACKed (not acknowledged, request sent and rejected); I3C tries again + * 0b11..ACKed (acknowledged; request sent and accepted), so done (unless the time control data is still being sent) + */ +#define I3C_SSTATUS_EVDET(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_EVDET_SHIFT)) & I3C_SSTATUS_EVDET_MASK) + +#define I3C_SSTATUS_IBIDIS_MASK (0x1000000U) +#define I3C_SSTATUS_IBIDIS_SHIFT (24U) +/*! IBIDIS - In-Band Interrupts Disable + * 0b0..Enabled + * 0b1..Disabled + */ +#define I3C_SSTATUS_IBIDIS(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_IBIDIS_SHIFT)) & I3C_SSTATUS_IBIDIS_MASK) + +#define I3C_SSTATUS_MRDIS_MASK (0x2000000U) +#define I3C_SSTATUS_MRDIS_SHIFT (25U) +/*! MRDIS - Controller Requests Disable + * 0b0..Enabled + * 0b1..Disabled + */ +#define I3C_SSTATUS_MRDIS(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_MRDIS_SHIFT)) & I3C_SSTATUS_MRDIS_MASK) + +#define I3C_SSTATUS_HJDIS_MASK (0x8000000U) +#define I3C_SSTATUS_HJDIS_SHIFT (27U) +/*! HJDIS - Hot-Join Disabled + * 0b0..Enabled + * 0b1..Disabled + */ +#define I3C_SSTATUS_HJDIS(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_HJDIS_SHIFT)) & I3C_SSTATUS_HJDIS_MASK) + +#define I3C_SSTATUS_ACTSTATE_MASK (0x30000000U) +#define I3C_SSTATUS_ACTSTATE_SHIFT (28U) +/*! ACTSTATE - Activity State from Common Command Codes (CCC) + * 0b00..NO_LATENCY (normal bus operations) + * 0b01..LATENCY_1MS (1 ms of latency) + * 0b10..LATENCY_100MS (100 ms of latency) + * 0b11..LATENCY_10S (10 seconds of latency) + */ +#define I3C_SSTATUS_ACTSTATE(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_ACTSTATE_SHIFT)) & I3C_SSTATUS_ACTSTATE_MASK) + +#define I3C_SSTATUS_TIMECTRL_MASK (0xC0000000U) +#define I3C_SSTATUS_TIMECTRL_SHIFT (30U) +/*! TIMECTRL - Time Control + * 0b00..NO_TIME_CONTROL (no time control is enabled) + * 0b01..SYNC_MODE (Synchronous mode is enabled) + * 0b10..ASYNC_MODE (Asynchronous standard mode (0 or 1) is enabled) + * 0b11..BOTHSYNCASYNC (both Synchronous and Asynchronous modes are enabled) + */ +#define I3C_SSTATUS_TIMECTRL(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_TIMECTRL_SHIFT)) & I3C_SSTATUS_TIMECTRL_MASK) +/*! @} */ + +/*! @name SCTRL - Target Control */ +/*! @{ */ + +#define I3C_SCTRL_EVENT_MASK (0x3U) +#define I3C_SCTRL_EVENT_SHIFT (0U) +/*! EVENT - Event + * 0b00..NORMAL_MODE + * 0b01..IBI + * 0b10..CONTROLLER_REQUEST + * 0b11..HOT_JOIN_REQUEST + */ +#define I3C_SCTRL_EVENT(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCTRL_EVENT_SHIFT)) & I3C_SCTRL_EVENT_MASK) + +#define I3C_SCTRL_EXTDATA_MASK (0x8U) +#define I3C_SCTRL_EXTDATA_SHIFT (3U) +/*! EXTDATA - Extended Data + * 0b0..Disable + * 0b1..Enable + */ +#define I3C_SCTRL_EXTDATA(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCTRL_EXTDATA_SHIFT)) & I3C_SCTRL_EXTDATA_MASK) + +#define I3C_SCTRL_MAPIDX_MASK (0x10U) +#define I3C_SCTRL_MAPIDX_SHIFT (4U) +/*! MAPIDX - Map Index */ +#define I3C_SCTRL_MAPIDX(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCTRL_MAPIDX_SHIFT)) & I3C_SCTRL_MAPIDX_MASK) + +#define I3C_SCTRL_IBIDATA_MASK (0xFF00U) +#define I3C_SCTRL_IBIDATA_SHIFT (8U) +/*! IBIDATA - In-Band Interrupt Data */ +#define I3C_SCTRL_IBIDATA(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCTRL_IBIDATA_SHIFT)) & I3C_SCTRL_IBIDATA_MASK) + +#define I3C_SCTRL_PENDINT_MASK (0xF0000U) +#define I3C_SCTRL_PENDINT_SHIFT (16U) +/*! PENDINT - Pending Interrupt */ +#define I3C_SCTRL_PENDINT(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCTRL_PENDINT_SHIFT)) & I3C_SCTRL_PENDINT_MASK) + +#define I3C_SCTRL_ACTSTATE_MASK (0x300000U) +#define I3C_SCTRL_ACTSTATE_SHIFT (20U) +/*! ACTSTATE - Activity State of Target */ +#define I3C_SCTRL_ACTSTATE(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCTRL_ACTSTATE_SHIFT)) & I3C_SCTRL_ACTSTATE_MASK) + +#define I3C_SCTRL_VENDINFO_MASK (0xFF000000U) +#define I3C_SCTRL_VENDINFO_SHIFT (24U) +/*! VENDINFO - Vendor Information */ +#define I3C_SCTRL_VENDINFO(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCTRL_VENDINFO_SHIFT)) & I3C_SCTRL_VENDINFO_MASK) +/*! @} */ + +/*! @name SINTSET - Target Interrupt Set */ +/*! @{ */ + +#define I3C_SINTSET_START_MASK (0x100U) +#define I3C_SINTSET_START_SHIFT (8U) +/*! START - Start Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define I3C_SINTSET_START(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_START_SHIFT)) & I3C_SINTSET_START_MASK) + +#define I3C_SINTSET_MATCHED_MASK (0x200U) +#define I3C_SINTSET_MATCHED_SHIFT (9U) +/*! MATCHED - Match Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define I3C_SINTSET_MATCHED(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_MATCHED_SHIFT)) & I3C_SINTSET_MATCHED_MASK) + +#define I3C_SINTSET_STOP_MASK (0x400U) +#define I3C_SINTSET_STOP_SHIFT (10U) +/*! STOP - Stop Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define I3C_SINTSET_STOP(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_STOP_SHIFT)) & I3C_SINTSET_STOP_MASK) + +#define I3C_SINTSET_RXPEND_MASK (0x800U) +#define I3C_SINTSET_RXPEND_SHIFT (11U) +/*! RXPEND - Receive Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define I3C_SINTSET_RXPEND(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_RXPEND_SHIFT)) & I3C_SINTSET_RXPEND_MASK) + +#define I3C_SINTSET_TXSEND_MASK (0x1000U) +#define I3C_SINTSET_TXSEND_SHIFT (12U) +/*! TXSEND - Transmit Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define I3C_SINTSET_TXSEND(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_TXSEND_SHIFT)) & I3C_SINTSET_TXSEND_MASK) + +#define I3C_SINTSET_DACHG_MASK (0x2000U) +#define I3C_SINTSET_DACHG_SHIFT (13U) +/*! DACHG - Dynamic Address Change Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define I3C_SINTSET_DACHG(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_DACHG_SHIFT)) & I3C_SINTSET_DACHG_MASK) + +#define I3C_SINTSET_CCC_MASK (0x4000U) +#define I3C_SINTSET_CCC_SHIFT (14U) +/*! CCC - Common Command Code (CCC) Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define I3C_SINTSET_CCC(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_CCC_SHIFT)) & I3C_SINTSET_CCC_MASK) + +#define I3C_SINTSET_ERRWARN_MASK (0x8000U) +#define I3C_SINTSET_ERRWARN_SHIFT (15U) +/*! ERRWARN - Error or Warning Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define I3C_SINTSET_ERRWARN(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_ERRWARN_SHIFT)) & I3C_SINTSET_ERRWARN_MASK) + +#define I3C_SINTSET_DDRMATCHED_MASK (0x10000U) +#define I3C_SINTSET_DDRMATCHED_SHIFT (16U) +/*! DDRMATCHED - Double Data Rate Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define I3C_SINTSET_DDRMATCHED(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_DDRMATCHED_SHIFT)) & I3C_SINTSET_DDRMATCHED_MASK) + +#define I3C_SINTSET_CHANDLED_MASK (0x20000U) +#define I3C_SINTSET_CHANDLED_SHIFT (17U) +/*! CHANDLED - Common Command Code (CCC) Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define I3C_SINTSET_CHANDLED(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_CHANDLED_SHIFT)) & I3C_SINTSET_CHANDLED_MASK) + +#define I3C_SINTSET_EVENT_MASK (0x40000U) +#define I3C_SINTSET_EVENT_SHIFT (18U) +/*! EVENT - Event Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define I3C_SINTSET_EVENT(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_EVENT_SHIFT)) & I3C_SINTSET_EVENT_MASK) + +#define I3C_SINTSET_SLVRST_MASK (0x80000U) +#define I3C_SINTSET_SLVRST_SHIFT (19U) +/*! SLVRST - Target Reset + * 0b0..Disable + * 0b1..Enable + */ +#define I3C_SINTSET_SLVRST(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_SLVRST_SHIFT)) & I3C_SINTSET_SLVRST_MASK) +/*! @} */ + +/*! @name SINTCLR - Target Interrupt Clear */ +/*! @{ */ + +#define I3C_SINTCLR_START_MASK (0x100U) +#define I3C_SINTCLR_START_SHIFT (8U) +/*! START - START Interrupt Enable Clear Flag */ +#define I3C_SINTCLR_START(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTCLR_START_SHIFT)) & I3C_SINTCLR_START_MASK) + +#define I3C_SINTCLR_MATCHED_MASK (0x200U) +#define I3C_SINTCLR_MATCHED_SHIFT (9U) +/*! MATCHED - Matched Interrupt Enable Clear Flag */ +#define I3C_SINTCLR_MATCHED(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTCLR_MATCHED_SHIFT)) & I3C_SINTCLR_MATCHED_MASK) + +#define I3C_SINTCLR_STOP_MASK (0x400U) +#define I3C_SINTCLR_STOP_SHIFT (10U) +/*! STOP - STOP Interrupt Enable Clear Flag */ +#define I3C_SINTCLR_STOP(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTCLR_STOP_SHIFT)) & I3C_SINTCLR_STOP_MASK) + +#define I3C_SINTCLR_RXPEND_MASK (0x800U) +#define I3C_SINTCLR_RXPEND_SHIFT (11U) +/*! RXPEND - RXPEND Interrupt Enable Clear Flag */ +#define I3C_SINTCLR_RXPEND(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTCLR_RXPEND_SHIFT)) & I3C_SINTCLR_RXPEND_MASK) + +#define I3C_SINTCLR_TXSEND_MASK (0x1000U) +#define I3C_SINTCLR_TXSEND_SHIFT (12U) +/*! TXSEND - TXSEND Interrupt Enable Clear Flag */ +#define I3C_SINTCLR_TXSEND(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTCLR_TXSEND_SHIFT)) & I3C_SINTCLR_TXSEND_MASK) + +#define I3C_SINTCLR_DACHG_MASK (0x2000U) +#define I3C_SINTCLR_DACHG_SHIFT (13U) +/*! DACHG - DACHG Interrupt Enable Clear Flag */ +#define I3C_SINTCLR_DACHG(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTCLR_DACHG_SHIFT)) & I3C_SINTCLR_DACHG_MASK) + +#define I3C_SINTCLR_CCC_MASK (0x4000U) +#define I3C_SINTCLR_CCC_SHIFT (14U) +/*! CCC - CCC Interrupt Enable Clear Flag */ +#define I3C_SINTCLR_CCC(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTCLR_CCC_SHIFT)) & I3C_SINTCLR_CCC_MASK) + +#define I3C_SINTCLR_ERRWARN_MASK (0x8000U) +#define I3C_SINTCLR_ERRWARN_SHIFT (15U) +/*! ERRWARN - ERRWARN Interrupt Enable Clear Flag */ +#define I3C_SINTCLR_ERRWARN(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTCLR_ERRWARN_SHIFT)) & I3C_SINTCLR_ERRWARN_MASK) + +#define I3C_SINTCLR_DDRMATCHED_MASK (0x10000U) +#define I3C_SINTCLR_DDRMATCHED_SHIFT (16U) +/*! DDRMATCHED - DDRMATCHED Interrupt Enable Clear Flag */ +#define I3C_SINTCLR_DDRMATCHED(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTCLR_DDRMATCHED_SHIFT)) & I3C_SINTCLR_DDRMATCHED_MASK) + +#define I3C_SINTCLR_CHANDLED_MASK (0x20000U) +#define I3C_SINTCLR_CHANDLED_SHIFT (17U) +/*! CHANDLED - CHANDLED Interrupt Enable Clear Flag */ +#define I3C_SINTCLR_CHANDLED(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTCLR_CHANDLED_SHIFT)) & I3C_SINTCLR_CHANDLED_MASK) + +#define I3C_SINTCLR_EVENT_MASK (0x40000U) +#define I3C_SINTCLR_EVENT_SHIFT (18U) +/*! EVENT - EVENT Interrupt Enable Clear Flag */ +#define I3C_SINTCLR_EVENT(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTCLR_EVENT_SHIFT)) & I3C_SINTCLR_EVENT_MASK) + +#define I3C_SINTCLR_SLVRST_MASK (0x80000U) +#define I3C_SINTCLR_SLVRST_SHIFT (19U) +/*! SLVRST - Target Reset Flag (SLVRST Interrupt Enable Clear) */ +#define I3C_SINTCLR_SLVRST(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTCLR_SLVRST_SHIFT)) & I3C_SINTCLR_SLVRST_MASK) +/*! @} */ + +/*! @name SINTMASKED - Target Interrupt Mask */ +/*! @{ */ + +#define I3C_SINTMASKED_START_MASK (0x100U) +#define I3C_SINTMASKED_START_SHIFT (8U) +/*! START - START Interrupt Mask */ +#define I3C_SINTMASKED_START(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTMASKED_START_SHIFT)) & I3C_SINTMASKED_START_MASK) + +#define I3C_SINTMASKED_MATCHED_MASK (0x200U) +#define I3C_SINTMASKED_MATCHED_SHIFT (9U) +/*! MATCHED - MATCHED Interrupt Mask */ +#define I3C_SINTMASKED_MATCHED(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTMASKED_MATCHED_SHIFT)) & I3C_SINTMASKED_MATCHED_MASK) + +#define I3C_SINTMASKED_STOP_MASK (0x400U) +#define I3C_SINTMASKED_STOP_SHIFT (10U) +/*! STOP - STOP Interrupt Mask */ +#define I3C_SINTMASKED_STOP(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTMASKED_STOP_SHIFT)) & I3C_SINTMASKED_STOP_MASK) + +#define I3C_SINTMASKED_RXPEND_MASK (0x800U) +#define I3C_SINTMASKED_RXPEND_SHIFT (11U) +/*! RXPEND - RXPEND Interrupt Mask */ +#define I3C_SINTMASKED_RXPEND(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTMASKED_RXPEND_SHIFT)) & I3C_SINTMASKED_RXPEND_MASK) + +#define I3C_SINTMASKED_TXSEND_MASK (0x1000U) +#define I3C_SINTMASKED_TXSEND_SHIFT (12U) +/*! TXSEND - TXSEND Interrupt Mask */ +#define I3C_SINTMASKED_TXSEND(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTMASKED_TXSEND_SHIFT)) & I3C_SINTMASKED_TXSEND_MASK) + +#define I3C_SINTMASKED_DACHG_MASK (0x2000U) +#define I3C_SINTMASKED_DACHG_SHIFT (13U) +/*! DACHG - DACHG Interrupt Mask */ +#define I3C_SINTMASKED_DACHG(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTMASKED_DACHG_SHIFT)) & I3C_SINTMASKED_DACHG_MASK) + +#define I3C_SINTMASKED_CCC_MASK (0x4000U) +#define I3C_SINTMASKED_CCC_SHIFT (14U) +/*! CCC - CCC Interrupt Mask */ +#define I3C_SINTMASKED_CCC(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTMASKED_CCC_SHIFT)) & I3C_SINTMASKED_CCC_MASK) + +#define I3C_SINTMASKED_ERRWARN_MASK (0x8000U) +#define I3C_SINTMASKED_ERRWARN_SHIFT (15U) +/*! ERRWARN - ERRWARN Interrupt Mask */ +#define I3C_SINTMASKED_ERRWARN(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTMASKED_ERRWARN_SHIFT)) & I3C_SINTMASKED_ERRWARN_MASK) + +#define I3C_SINTMASKED_DDRMATCHED_MASK (0x10000U) +#define I3C_SINTMASKED_DDRMATCHED_SHIFT (16U) +/*! DDRMATCHED - DDRMATCHED Interrupt Mask */ +#define I3C_SINTMASKED_DDRMATCHED(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTMASKED_DDRMATCHED_SHIFT)) & I3C_SINTMASKED_DDRMATCHED_MASK) + +#define I3C_SINTMASKED_CHANDLED_MASK (0x20000U) +#define I3C_SINTMASKED_CHANDLED_SHIFT (17U) +/*! CHANDLED - CHANDLED Interrupt Mask */ +#define I3C_SINTMASKED_CHANDLED(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTMASKED_CHANDLED_SHIFT)) & I3C_SINTMASKED_CHANDLED_MASK) + +#define I3C_SINTMASKED_EVENT_MASK (0x40000U) +#define I3C_SINTMASKED_EVENT_SHIFT (18U) +/*! EVENT - EVENT Interrupt Mask */ +#define I3C_SINTMASKED_EVENT(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTMASKED_EVENT_SHIFT)) & I3C_SINTMASKED_EVENT_MASK) + +#define I3C_SINTMASKED_SLVRST_MASK (0x80000U) +#define I3C_SINTMASKED_SLVRST_SHIFT (19U) +/*! SLVRST - Target Reset Interrupt Mask */ +#define I3C_SINTMASKED_SLVRST(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTMASKED_SLVRST_SHIFT)) & I3C_SINTMASKED_SLVRST_MASK) +/*! @} */ + +/*! @name SERRWARN - Target Errors and Warnings */ +/*! @{ */ + +#define I3C_SERRWARN_ORUN_MASK (0x1U) +#define I3C_SERRWARN_ORUN_SHIFT (0U) +/*! ORUN - Overrun Error Flag + * 0b0..No overrun error + * 0b0..No effect + * 0b1..Overrun error + * 0b1..Clear the flag + */ +#define I3C_SERRWARN_ORUN(x) (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_ORUN_SHIFT)) & I3C_SERRWARN_ORUN_MASK) + +#define I3C_SERRWARN_URUN_MASK (0x2U) +#define I3C_SERRWARN_URUN_SHIFT (1U) +/*! URUN - Underrun Error Flag + * 0b0..No underrun error + * 0b0..No effect + * 0b1..Underrun error + * 0b1..Clear the flag + */ +#define I3C_SERRWARN_URUN(x) (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_URUN_SHIFT)) & I3C_SERRWARN_URUN_MASK) + +#define I3C_SERRWARN_URUNNACK_MASK (0x4U) +#define I3C_SERRWARN_URUNNACK_SHIFT (2U) +/*! URUNNACK - Underrun and Not Acknowledged (NACKed) Error Flag + * 0b0..No underrun; not acknowledged error + * 0b0..No effect + * 0b1..Underrun; not acknowledged error + * 0b1..Clear the flag + */ +#define I3C_SERRWARN_URUNNACK(x) (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_URUNNACK_SHIFT)) & I3C_SERRWARN_URUNNACK_MASK) + +#define I3C_SERRWARN_TERM_MASK (0x8U) +#define I3C_SERRWARN_TERM_SHIFT (3U) +/*! TERM - Terminated Error Flag + * 0b0..No terminated error + * 0b0..No effect + * 0b1..Terminated error + * 0b1..Clear the flag + */ +#define I3C_SERRWARN_TERM(x) (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_TERM_SHIFT)) & I3C_SERRWARN_TERM_MASK) + +#define I3C_SERRWARN_INVSTART_MASK (0x10U) +#define I3C_SERRWARN_INVSTART_SHIFT (4U) +/*! INVSTART - Invalid Start Error Flag + * 0b0..No invalid start error + * 0b0..No effect + * 0b1..Invalid start error + * 0b1..Clear the flag + */ +#define I3C_SERRWARN_INVSTART(x) (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_INVSTART_SHIFT)) & I3C_SERRWARN_INVSTART_MASK) + +#define I3C_SERRWARN_SPAR_MASK (0x100U) +#define I3C_SERRWARN_SPAR_SHIFT (8U) +/*! SPAR - SDR Parity Error Flag + * 0b0..No SDR parity error + * 0b0..No effect + * 0b1..SDR parity error + * 0b1..Clear the flag + */ +#define I3C_SERRWARN_SPAR(x) (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_SPAR_SHIFT)) & I3C_SERRWARN_SPAR_MASK) + +#define I3C_SERRWARN_HPAR_MASK (0x200U) +#define I3C_SERRWARN_HPAR_SHIFT (9U) +/*! HPAR - HDR Parity Error Flag + * 0b0..No HDR parity error + * 0b0..No effect + * 0b1..HDR parity error + * 0b1..Clear the flag + */ +#define I3C_SERRWARN_HPAR(x) (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_HPAR_SHIFT)) & I3C_SERRWARN_HPAR_MASK) + +#define I3C_SERRWARN_HCRC_MASK (0x400U) +#define I3C_SERRWARN_HCRC_SHIFT (10U) +/*! HCRC - HDR-DDR CRC Error Flag + * 0b0..No HDR-DDR CRC error occurred + * 0b0..No effect + * 0b1..HDR-DDR CRC error occurred + * 0b1..Clear the flag + */ +#define I3C_SERRWARN_HCRC(x) (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_HCRC_SHIFT)) & I3C_SERRWARN_HCRC_MASK) + +#define I3C_SERRWARN_S0S1_MASK (0x800U) +#define I3C_SERRWARN_S0S1_SHIFT (11U) +/*! S0S1 - TE0 or TE1 Error Flag + * 0b0..No TE0 or TE1 error occurred + * 0b0..No effect + * 0b1..TE0 or TE1 error occurred + * 0b1..Clear the flag + */ +#define I3C_SERRWARN_S0S1(x) (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_S0S1_SHIFT)) & I3C_SERRWARN_S0S1_MASK) + +#define I3C_SERRWARN_OREAD_MASK (0x10000U) +#define I3C_SERRWARN_OREAD_SHIFT (16U) +/*! OREAD - Over-Read Error Flag + * 0b0..No over-read error + * 0b0..No effect + * 0b1..Over-read error + * 0b1..Clear the flag + */ +#define I3C_SERRWARN_OREAD(x) (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_OREAD_SHIFT)) & I3C_SERRWARN_OREAD_MASK) + +#define I3C_SERRWARN_OWRITE_MASK (0x20000U) +#define I3C_SERRWARN_OWRITE_SHIFT (17U) +/*! OWRITE - Over-Write Error Flag + * 0b0..No overwrite error + * 0b0..No effect + * 0b1..Overwrite error + * 0b1..Clear the flag + */ +#define I3C_SERRWARN_OWRITE(x) (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_OWRITE_SHIFT)) & I3C_SERRWARN_OWRITE_MASK) +/*! @} */ + +/*! @name SDMACTRL - Target DMA Control */ +/*! @{ */ + +#define I3C_SDMACTRL_DMAFB_MASK (0x3U) +#define I3C_SDMACTRL_DMAFB_SHIFT (0U) +/*! DMAFB - DMA Read (From-Bus) Trigger + * 0b00..DMA not used + * 0b01..DMA enabled for one frame + * 0b10..DMA enabled until turned off + * 0b11.. + */ +#define I3C_SDMACTRL_DMAFB(x) (((uint32_t)(((uint32_t)(x)) << I3C_SDMACTRL_DMAFB_SHIFT)) & I3C_SDMACTRL_DMAFB_MASK) + +#define I3C_SDMACTRL_DMATB_MASK (0xCU) +#define I3C_SDMACTRL_DMATB_SHIFT (2U) +/*! DMATB - DMA Write (To-Bus) Trigger + * 0b00..DMA not used + * 0b01..DMA enabled for one frame + * 0b10..DMA enabled until turned off + * 0b11.. + */ +#define I3C_SDMACTRL_DMATB(x) (((uint32_t)(((uint32_t)(x)) << I3C_SDMACTRL_DMATB_SHIFT)) & I3C_SDMACTRL_DMATB_MASK) + +#define I3C_SDMACTRL_DMAWIDTH_MASK (0x30U) +#define I3C_SDMACTRL_DMAWIDTH_SHIFT (4U) +/*! DMAWIDTH - Width of DMA Operations + * 0b00, 0b01..Byte + * 0b10..Halfword (16 bits) (this value ensures that two bytes are available in the FIFO) + * 0b11.. + */ +#define I3C_SDMACTRL_DMAWIDTH(x) (((uint32_t)(((uint32_t)(x)) << I3C_SDMACTRL_DMAWIDTH_SHIFT)) & I3C_SDMACTRL_DMAWIDTH_MASK) + +#define I3C_SDMACTRL_BULKFB_MASK (0x40U) +#define I3C_SDMACTRL_BULKFB_SHIFT (6U) +/*! BULKFB - Bulk Transfer from Bus + * 0b0..Disable + * 0b1..Enable + */ +#define I3C_SDMACTRL_BULKFB(x) (((uint32_t)(((uint32_t)(x)) << I3C_SDMACTRL_BULKFB_SHIFT)) & I3C_SDMACTRL_BULKFB_MASK) + +#define I3C_SDMACTRL_BULKTB_MASK (0x80U) +#define I3C_SDMACTRL_BULKTB_SHIFT (7U) +/*! BULKTB - Bulk Transfer to Bus + * 0b0..Disable + * 0b1..Enable + */ +#define I3C_SDMACTRL_BULKTB(x) (((uint32_t)(((uint32_t)(x)) << I3C_SDMACTRL_BULKTB_SHIFT)) & I3C_SDMACTRL_BULKTB_MASK) +/*! @} */ + +/*! @name SDATACTRL - Target Data Control */ +/*! @{ */ + +#define I3C_SDATACTRL_FLUSHTB_MASK (0x1U) +#define I3C_SDATACTRL_FLUSHTB_SHIFT (0U) +/*! FLUSHTB - Flush To-Bus Buffer or FIFO + * 0b0..No action + * 0b1..Flush the buffer + */ +#define I3C_SDATACTRL_FLUSHTB(x) (((uint32_t)(((uint32_t)(x)) << I3C_SDATACTRL_FLUSHTB_SHIFT)) & I3C_SDATACTRL_FLUSHTB_MASK) + +#define I3C_SDATACTRL_FLUSHFB_MASK (0x2U) +#define I3C_SDATACTRL_FLUSHFB_SHIFT (1U) +/*! FLUSHFB - Flush From-Bus Buffer or FIFO + * 0b0..No action + * 0b1..Flush the buffer + */ +#define I3C_SDATACTRL_FLUSHFB(x) (((uint32_t)(((uint32_t)(x)) << I3C_SDATACTRL_FLUSHFB_SHIFT)) & I3C_SDATACTRL_FLUSHFB_MASK) + +#define I3C_SDATACTRL_UNLOCK_MASK (0x8U) +#define I3C_SDATACTRL_UNLOCK_SHIFT (3U) +/*! UNLOCK - Unlock + * 0b0..Cannot be changed + * 0b1..Can be changed + */ +#define I3C_SDATACTRL_UNLOCK(x) (((uint32_t)(((uint32_t)(x)) << I3C_SDATACTRL_UNLOCK_SHIFT)) & I3C_SDATACTRL_UNLOCK_MASK) + +#define I3C_SDATACTRL_TXTRIG_MASK (0x30U) +#define I3C_SDATACTRL_TXTRIG_SHIFT (4U) +/*! TXTRIG - Transmit Trigger Level + * 0b00..Trigger when empty + * 0b01..Trigger when 1/4 full or less + * 0b10..Trigger when 1/2 full or less + * 0b11..Default (trigger when 1 less than full or less) + */ +#define I3C_SDATACTRL_TXTRIG(x) (((uint32_t)(((uint32_t)(x)) << I3C_SDATACTRL_TXTRIG_SHIFT)) & I3C_SDATACTRL_TXTRIG_MASK) + +#define I3C_SDATACTRL_RXTRIG_MASK (0xC0U) +#define I3C_SDATACTRL_RXTRIG_SHIFT (6U) +/*! RXTRIG - Receive Trigger Level + * 0b00..Trigger when not empty (default) + * 0b01..Trigger when 1/4 or more full + * 0b10..Trigger when 1/2 or more full + * 0b11..Trigger when 3/4 or more full + */ +#define I3C_SDATACTRL_RXTRIG(x) (((uint32_t)(((uint32_t)(x)) << I3C_SDATACTRL_RXTRIG_SHIFT)) & I3C_SDATACTRL_RXTRIG_MASK) + +#define I3C_SDATACTRL_TXCOUNT_MASK (0x1F0000U) +#define I3C_SDATACTRL_TXCOUNT_SHIFT (16U) +/*! TXCOUNT - Count of Bytes in Transmit */ +#define I3C_SDATACTRL_TXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << I3C_SDATACTRL_TXCOUNT_SHIFT)) & I3C_SDATACTRL_TXCOUNT_MASK) + +#define I3C_SDATACTRL_RXCOUNT_MASK (0x1F000000U) +#define I3C_SDATACTRL_RXCOUNT_SHIFT (24U) +/*! RXCOUNT - Count of Bytes in Receive */ +#define I3C_SDATACTRL_RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << I3C_SDATACTRL_RXCOUNT_SHIFT)) & I3C_SDATACTRL_RXCOUNT_MASK) + +#define I3C_SDATACTRL_TXFULL_MASK (0x40000000U) +#define I3C_SDATACTRL_TXFULL_SHIFT (30U) +/*! TXFULL - Transmit is Full + * 0b0..Not full + * 0b1..Full + */ +#define I3C_SDATACTRL_TXFULL(x) (((uint32_t)(((uint32_t)(x)) << I3C_SDATACTRL_TXFULL_SHIFT)) & I3C_SDATACTRL_TXFULL_MASK) + +#define I3C_SDATACTRL_RXEMPTY_MASK (0x80000000U) +#define I3C_SDATACTRL_RXEMPTY_SHIFT (31U) +/*! RXEMPTY - Receive is Empty + * 0b0..Not empty + * 0b1..Empty + */ +#define I3C_SDATACTRL_RXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << I3C_SDATACTRL_RXEMPTY_SHIFT)) & I3C_SDATACTRL_RXEMPTY_MASK) +/*! @} */ + +/*! @name SWDATAB - Target Write Data Byte */ +/*! @{ */ + +#define I3C_SWDATAB_DATA_MASK (0xFFU) +#define I3C_SWDATAB_DATA_SHIFT (0U) +/*! DATA - Data */ +#define I3C_SWDATAB_DATA(x) (((uint32_t)(((uint32_t)(x)) << I3C_SWDATAB_DATA_SHIFT)) & I3C_SWDATAB_DATA_MASK) + +#define I3C_SWDATAB_END_MASK (0x100U) +#define I3C_SWDATAB_END_SHIFT (8U) +/*! END - End + * 0b0..Not the end + * 0b1..End + */ +#define I3C_SWDATAB_END(x) (((uint32_t)(((uint32_t)(x)) << I3C_SWDATAB_END_SHIFT)) & I3C_SWDATAB_END_MASK) + +#define I3C_SWDATAB_END_ALSO_MASK (0x10000U) +#define I3C_SWDATAB_END_ALSO_SHIFT (16U) +/*! END_ALSO - End Also + * 0b0..Not the end + * 0b1..End + */ +#define I3C_SWDATAB_END_ALSO(x) (((uint32_t)(((uint32_t)(x)) << I3C_SWDATAB_END_ALSO_SHIFT)) & I3C_SWDATAB_END_ALSO_MASK) +/*! @} */ + +/*! @name SWDATABE - Target Write Data Byte End */ +/*! @{ */ + +#define I3C_SWDATABE_DATA_MASK (0xFFU) +#define I3C_SWDATABE_DATA_SHIFT (0U) +/*! DATA - Data */ +#define I3C_SWDATABE_DATA(x) (((uint32_t)(((uint32_t)(x)) << I3C_SWDATABE_DATA_SHIFT)) & I3C_SWDATABE_DATA_MASK) +/*! @} */ + +/*! @name SWDATAH - Target Write Data Halfword */ +/*! @{ */ + +#define I3C_SWDATAH_DATA0_MASK (0xFFU) +#define I3C_SWDATAH_DATA0_SHIFT (0U) +/*! DATA0 - Data 0 */ +#define I3C_SWDATAH_DATA0(x) (((uint32_t)(((uint32_t)(x)) << I3C_SWDATAH_DATA0_SHIFT)) & I3C_SWDATAH_DATA0_MASK) + +#define I3C_SWDATAH_DATA1_MASK (0xFF00U) +#define I3C_SWDATAH_DATA1_SHIFT (8U) +/*! DATA1 - Data 1 */ +#define I3C_SWDATAH_DATA1(x) (((uint32_t)(((uint32_t)(x)) << I3C_SWDATAH_DATA1_SHIFT)) & I3C_SWDATAH_DATA1_MASK) + +#define I3C_SWDATAH_END_MASK (0x10000U) +#define I3C_SWDATAH_END_SHIFT (16U) +/*! END - End of Message + * 0b0..Not the end + * 0b1..End + */ +#define I3C_SWDATAH_END(x) (((uint32_t)(((uint32_t)(x)) << I3C_SWDATAH_END_SHIFT)) & I3C_SWDATAH_END_MASK) +/*! @} */ + +/*! @name SWDATAHE - Target Write Data Halfword End */ +/*! @{ */ + +#define I3C_SWDATAHE_DATA0_MASK (0xFFU) +#define I3C_SWDATAHE_DATA0_SHIFT (0U) +/*! DATA0 - Data 0 */ +#define I3C_SWDATAHE_DATA0(x) (((uint32_t)(((uint32_t)(x)) << I3C_SWDATAHE_DATA0_SHIFT)) & I3C_SWDATAHE_DATA0_MASK) + +#define I3C_SWDATAHE_DATA1_MASK (0xFF00U) +#define I3C_SWDATAHE_DATA1_SHIFT (8U) +/*! DATA1 - Data 1 */ +#define I3C_SWDATAHE_DATA1(x) (((uint32_t)(((uint32_t)(x)) << I3C_SWDATAHE_DATA1_SHIFT)) & I3C_SWDATAHE_DATA1_MASK) +/*! @} */ + +/*! @name SRDATAB - Target Read Data Byte */ +/*! @{ */ + +#define I3C_SRDATAB_DATA0_MASK (0xFFU) +#define I3C_SRDATAB_DATA0_SHIFT (0U) +/*! DATA0 - Data 0 */ +#define I3C_SRDATAB_DATA0(x) (((uint32_t)(((uint32_t)(x)) << I3C_SRDATAB_DATA0_SHIFT)) & I3C_SRDATAB_DATA0_MASK) +/*! @} */ + +/*! @name SRDATAH - Target Read Data Halfword */ +/*! @{ */ + +#define I3C_SRDATAH_LSB_MASK (0xFFU) +#define I3C_SRDATAH_LSB_SHIFT (0U) +/*! LSB - Low Byte */ +#define I3C_SRDATAH_LSB(x) (((uint32_t)(((uint32_t)(x)) << I3C_SRDATAH_LSB_SHIFT)) & I3C_SRDATAH_LSB_MASK) + +#define I3C_SRDATAH_MSB_MASK (0xFF00U) +#define I3C_SRDATAH_MSB_SHIFT (8U) +/*! MSB - High Byte */ +#define I3C_SRDATAH_MSB(x) (((uint32_t)(((uint32_t)(x)) << I3C_SRDATAH_MSB_SHIFT)) & I3C_SRDATAH_MSB_MASK) +/*! @} */ + +/*! @name SWDATAB1 - Target Write Data Byte */ +/*! @{ */ + +#define I3C_SWDATAB1_DATA_MASK (0xFFU) +#define I3C_SWDATAB1_DATA_SHIFT (0U) +/*! DATA - Data */ +#define I3C_SWDATAB1_DATA(x) (((uint32_t)(((uint32_t)(x)) << I3C_SWDATAB1_DATA_SHIFT)) & I3C_SWDATAB1_DATA_MASK) +/*! @} */ + +/*! @name SWDATAH1 - Target Write Data Halfword */ +/*! @{ */ + +#define I3C_SWDATAH1_DATA_MASK (0xFFFFU) +#define I3C_SWDATAH1_DATA_SHIFT (0U) +/*! DATA - Data */ +#define I3C_SWDATAH1_DATA(x) (((uint32_t)(((uint32_t)(x)) << I3C_SWDATAH1_DATA_SHIFT)) & I3C_SWDATAH1_DATA_MASK) +/*! @} */ + +/*! @name SCAPABILITIES2 - Target Capabilities 2 */ +/*! @{ */ + +#define I3C_SCAPABILITIES2_MAPCNT_MASK (0xFU) +#define I3C_SCAPABILITIES2_MAPCNT_SHIFT (0U) +/*! MAPCNT - Map Count */ +#define I3C_SCAPABILITIES2_MAPCNT(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES2_MAPCNT_SHIFT)) & I3C_SCAPABILITIES2_MAPCNT_MASK) + +#define I3C_SCAPABILITIES2_I2C10B_MASK (0x10U) +#define I3C_SCAPABILITIES2_I2C10B_SHIFT (4U) +/*! I2C10B - I2C 10-bit Address + * 0b0..Not supported + * 0b1..Supported + */ +#define I3C_SCAPABILITIES2_I2C10B(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES2_I2C10B_SHIFT)) & I3C_SCAPABILITIES2_I2C10B_MASK) + +#define I3C_SCAPABILITIES2_I2CDEVID_MASK (0x40U) +#define I3C_SCAPABILITIES2_I2CDEVID_SHIFT (6U) +/*! I2CDEVID - I2C Device ID + * 0b0..Not supported + * 0b1..Supported + */ +#define I3C_SCAPABILITIES2_I2CDEVID(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES2_I2CDEVID_SHIFT)) & I3C_SCAPABILITIES2_I2CDEVID_MASK) + +#define I3C_SCAPABILITIES2_IBIEXT_MASK (0x100U) +#define I3C_SCAPABILITIES2_IBIEXT_SHIFT (8U) +/*! IBIEXT - In-Band Interrupt EXTDATA + * 0b0..Not supported + * 0b1..Supported + */ +#define I3C_SCAPABILITIES2_IBIEXT(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES2_IBIEXT_SHIFT)) & I3C_SCAPABILITIES2_IBIEXT_MASK) + +#define I3C_SCAPABILITIES2_IBIXREG_MASK (0x200U) +#define I3C_SCAPABILITIES2_IBIXREG_SHIFT (9U) +/*! IBIXREG - In-Band Interrupt Extended Register + * 0b0..Not supported + * 0b1..Supported + */ +#define I3C_SCAPABILITIES2_IBIXREG(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES2_IBIXREG_SHIFT)) & I3C_SCAPABILITIES2_IBIXREG_MASK) + +#define I3C_SCAPABILITIES2_V1_1_MASK (0x10000U) +#define I3C_SCAPABILITIES2_V1_1_SHIFT (16U) +/*! V1_1 - Version 1.1 + * 0b0..Not supported + * 0b1..Supported + */ +#define I3C_SCAPABILITIES2_V1_1(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES2_V1_1_SHIFT)) & I3C_SCAPABILITIES2_V1_1_MASK) + +#define I3C_SCAPABILITIES2_SLVRST_MASK (0x20000U) +#define I3C_SCAPABILITIES2_SLVRST_SHIFT (17U) +/*! SLVRST - Target Reset + * 0b0..Not supported + * 0b1..Supported + */ +#define I3C_SCAPABILITIES2_SLVRST(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES2_SLVRST_SHIFT)) & I3C_SCAPABILITIES2_SLVRST_MASK) + +#define I3C_SCAPABILITIES2_GROUP_MASK (0xC0000U) +#define I3C_SCAPABILITIES2_GROUP_SHIFT (18U) +/*! GROUP - Group + * 0b00..v1.1 group addressing not supported + * 0b01..One group supported + * 0b10..Two groups supported + * 0b11..Three groups supported + */ +#define I3C_SCAPABILITIES2_GROUP(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES2_GROUP_SHIFT)) & I3C_SCAPABILITIES2_GROUP_MASK) + +#define I3C_SCAPABILITIES2_AASA_MASK (0x200000U) +#define I3C_SCAPABILITIES2_AASA_SHIFT (21U) +/*! AASA - SETAASA + * 0b0..SETAASA not supported + * 0b1..SETAASA supported + */ +#define I3C_SCAPABILITIES2_AASA(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES2_AASA_SHIFT)) & I3C_SCAPABILITIES2_AASA_MASK) + +#define I3C_SCAPABILITIES2_SSTSUB_MASK (0x400000U) +#define I3C_SCAPABILITIES2_SSTSUB_SHIFT (22U) +/*! SSTSUB - Target-Target(s)-Tunnel Subscriber Capable + * 0b0..Not subscriber capable + * 0b1..Subscriber capable + */ +#define I3C_SCAPABILITIES2_SSTSUB(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES2_SSTSUB_SHIFT)) & I3C_SCAPABILITIES2_SSTSUB_MASK) + +#define I3C_SCAPABILITIES2_SSTWR_MASK (0x800000U) +#define I3C_SCAPABILITIES2_SSTWR_SHIFT (23U) +/*! SSTWR - Target-Target(s)-Tunnel Write Capable + * 0b0..Not write capable + * 0b1..Write capable + */ +#define I3C_SCAPABILITIES2_SSTWR(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES2_SSTWR_SHIFT)) & I3C_SCAPABILITIES2_SSTWR_MASK) +/*! @} */ + +/*! @name SCAPABILITIES - Target Capabilities */ +/*! @{ */ + +#define I3C_SCAPABILITIES_IDENA_MASK (0x3U) +#define I3C_SCAPABILITIES_IDENA_SHIFT (0U) +/*! IDENA - ID 48b Handler + * 0b00..Application + * 0b01..Hardware + * 0b10..Hardware, but the I3C module instance handles ID 48b + * 0b11..A part number register (PARTNO) + */ +#define I3C_SCAPABILITIES_IDENA(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_IDENA_SHIFT)) & I3C_SCAPABILITIES_IDENA_MASK) + +#define I3C_SCAPABILITIES_IDREG_MASK (0x3CU) +#define I3C_SCAPABILITIES_IDREG_SHIFT (2U) +/*! IDREG - ID Register + * 0b0000..All ID register features disabled + * 0b1xxx..A Bus Characteristics Register (BCR) is available + * 0bx1xx..A Device Characteristic Register (DCR) is available + * 0bxx1x..An ID Random field is available + * 0bxxx1..ID Instance is a register; used if there is no PARTNO register + */ +#define I3C_SCAPABILITIES_IDREG(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_IDREG_SHIFT)) & I3C_SCAPABILITIES_IDREG_MASK) + +#define I3C_SCAPABILITIES_HDRSUPP_MASK (0xC0U) +#define I3C_SCAPABILITIES_HDRSUPP_SHIFT (6U) +/*! HDRSUPP - High Data Rate Support + * 0b00..No HDR modes supported + * 0b01..DDR mode supported + */ +#define I3C_SCAPABILITIES_HDRSUPP(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_HDRSUPP_SHIFT)) & I3C_SCAPABILITIES_HDRSUPP_MASK) + +#define I3C_SCAPABILITIES_MASTER_MASK (0x200U) +#define I3C_SCAPABILITIES_MASTER_SHIFT (9U) +/*! MASTER - Controller + * 0b0..Not supported + * 0b1..Supported + */ +#define I3C_SCAPABILITIES_MASTER(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_MASTER_SHIFT)) & I3C_SCAPABILITIES_MASTER_MASK) + +#define I3C_SCAPABILITIES_SADDR_MASK (0xC00U) +#define I3C_SCAPABILITIES_SADDR_SHIFT (10U) +/*! SADDR - Static Address + * 0b00..No static address + * 0b01..Static address is fixed in hardware + * 0b10..Hardware controls the static address dynamically (for example, from the pin strap) + * 0b11..SCONFIG register supplies the static address + */ +#define I3C_SCAPABILITIES_SADDR(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_SADDR_SHIFT)) & I3C_SCAPABILITIES_SADDR_MASK) + +#define I3C_SCAPABILITIES_CCCHANDLE_MASK (0xF000U) +#define I3C_SCAPABILITIES_CCCHANDLE_SHIFT (12U) +/*! CCCHANDLE - Common Command Codes Handling + * 0b0000..All handling features disabled + * 0b1xxx..GETSTATUS CCC returns the value of SCTRL[VENDINFO] + * 0bx1xx..GETSTATUS CCC returns the values of SCTRL[PENDINT] and SCTRL[ACTSTATE] + * 0bxx1x..The I3C module manages maximum read and write lengths, and max data speed + * 0bxxx1..The I3C module manages events, activities, status, HDR, and if enabled for it, ID and static-address-related items + */ +#define I3C_SCAPABILITIES_CCCHANDLE(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_CCCHANDLE_SHIFT)) & I3C_SCAPABILITIES_CCCHANDLE_MASK) + +#define I3C_SCAPABILITIES_IBI_MR_HJ_MASK (0x1F0000U) +#define I3C_SCAPABILITIES_IBI_MR_HJ_SHIFT (16U) +/*! IBI_MR_HJ - In-Band Interrupts, Controller Requests, Hot-Join Events + * 0b00000..Application cannot generate IBI, CR, or HJ + * 0b1xxxx..Application can use SCONFIG[BAMATCH] for bus-available timing + * 0bx1xxx..Application can generate a Hot-Join event + * 0bxx1xx..Application can generate a controller request for a secondary controller + * 0bxxx1x..When bit 0 = 1, the IBI has data from the SCTRL register + * 0bxxxx1..Application can generate an IBI + */ +#define I3C_SCAPABILITIES_IBI_MR_HJ(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_IBI_MR_HJ_SHIFT)) & I3C_SCAPABILITIES_IBI_MR_HJ_MASK) + +#define I3C_SCAPABILITIES_TIMECTRL_MASK (0x200000U) +#define I3C_SCAPABILITIES_TIMECTRL_SHIFT (21U) +/*! TIMECTRL - Time Control + * 0b0..No time control supported + * 0b1..At least one time-control type supported + */ +#define I3C_SCAPABILITIES_TIMECTRL(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_TIMECTRL_SHIFT)) & I3C_SCAPABILITIES_TIMECTRL_MASK) + +#define I3C_SCAPABILITIES_EXTFIFO_MASK (0x3800000U) +#define I3C_SCAPABILITIES_EXTFIFO_SHIFT (23U) +/*! EXTFIFO - External FIFO + * 0b000..No external FIFO available + * 0b001..Standard available or free external FIFO + * 0b010..Request track external FIFO + */ +#define I3C_SCAPABILITIES_EXTFIFO(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_EXTFIFO_SHIFT)) & I3C_SCAPABILITIES_EXTFIFO_MASK) + +#define I3C_SCAPABILITIES_FIFOTX_MASK (0xC000000U) +#define I3C_SCAPABILITIES_FIFOTX_SHIFT (26U) +/*! FIFOTX - FIFO Transmit + * 0b00..Two + * 0b01..Four + * 0b10..Eight + * 0b11..16 or larger + */ +#define I3C_SCAPABILITIES_FIFOTX(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_FIFOTX_SHIFT)) & I3C_SCAPABILITIES_FIFOTX_MASK) + +#define I3C_SCAPABILITIES_FIFORX_MASK (0x30000000U) +#define I3C_SCAPABILITIES_FIFORX_SHIFT (28U) +/*! FIFORX - FIFO Receive + * 0b00..Two or three + * 0b01..Four + * 0b10..Eight + * 0b11..16 or larger + */ +#define I3C_SCAPABILITIES_FIFORX(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_FIFORX_SHIFT)) & I3C_SCAPABILITIES_FIFORX_MASK) + +#define I3C_SCAPABILITIES_INT_MASK (0x40000000U) +#define I3C_SCAPABILITIES_INT_SHIFT (30U) +/*! INT - Interrupts + * 0b0..Not supported + * 0b1..Supported + */ +#define I3C_SCAPABILITIES_INT(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_INT_SHIFT)) & I3C_SCAPABILITIES_INT_MASK) + +#define I3C_SCAPABILITIES_DMA_MASK (0x80000000U) +#define I3C_SCAPABILITIES_DMA_SHIFT (31U) +/*! DMA - Direct Memory Access + * 0b0..Not supported + * 0b1..Supported + */ +#define I3C_SCAPABILITIES_DMA(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_DMA_SHIFT)) & I3C_SCAPABILITIES_DMA_MASK) +/*! @} */ + +/*! @name SMAXLIMITS - Target Maximum Limits */ +/*! @{ */ + +#define I3C_SMAXLIMITS_MAXRD_MASK (0xFFFU) +#define I3C_SMAXLIMITS_MAXRD_SHIFT (0U) +/*! MAXRD - Maximum Read Length */ +#define I3C_SMAXLIMITS_MAXRD(x) (((uint32_t)(((uint32_t)(x)) << I3C_SMAXLIMITS_MAXRD_SHIFT)) & I3C_SMAXLIMITS_MAXRD_MASK) + +#define I3C_SMAXLIMITS_MAXWR_MASK (0xFFF0000U) +#define I3C_SMAXLIMITS_MAXWR_SHIFT (16U) +/*! MAXWR - Maximum Write Length */ +#define I3C_SMAXLIMITS_MAXWR(x) (((uint32_t)(((uint32_t)(x)) << I3C_SMAXLIMITS_MAXWR_SHIFT)) & I3C_SMAXLIMITS_MAXWR_MASK) +/*! @} */ + +/*! @name SIDPARTNO - Target ID Part Number */ +/*! @{ */ + +#define I3C_SIDPARTNO_PARTNO_MASK (0xFFFFFFFFU) +#define I3C_SIDPARTNO_PARTNO_SHIFT (0U) +/*! PARTNO - Part Number */ +#define I3C_SIDPARTNO_PARTNO(x) (((uint32_t)(((uint32_t)(x)) << I3C_SIDPARTNO_PARTNO_SHIFT)) & I3C_SIDPARTNO_PARTNO_MASK) +/*! @} */ + +/*! @name SIDEXT - Target ID Extension */ +/*! @{ */ + +#define I3C_SIDEXT_DCR_MASK (0xFF00U) +#define I3C_SIDEXT_DCR_SHIFT (8U) +/*! DCR - Device Characteristic Register */ +#define I3C_SIDEXT_DCR(x) (((uint32_t)(((uint32_t)(x)) << I3C_SIDEXT_DCR_SHIFT)) & I3C_SIDEXT_DCR_MASK) + +#define I3C_SIDEXT_BCR_MASK (0xFF0000U) +#define I3C_SIDEXT_BCR_SHIFT (16U) +/*! BCR - Bus Characteristics Register */ +#define I3C_SIDEXT_BCR(x) (((uint32_t)(((uint32_t)(x)) << I3C_SIDEXT_BCR_SHIFT)) & I3C_SIDEXT_BCR_MASK) +/*! @} */ + +/*! @name SVENDORID - Target Vendor ID */ +/*! @{ */ + +#define I3C_SVENDORID_VID_MASK (0x7FFFU) +#define I3C_SVENDORID_VID_SHIFT (0U) +/*! VID - Vendor ID */ +#define I3C_SVENDORID_VID(x) (((uint32_t)(((uint32_t)(x)) << I3C_SVENDORID_VID_SHIFT)) & I3C_SVENDORID_VID_MASK) +/*! @} */ + +/*! @name STCCLOCK - Target Time Control Clock */ +/*! @{ */ + +#define I3C_STCCLOCK_ACCURACY_MASK (0xFFU) +#define I3C_STCCLOCK_ACCURACY_SHIFT (0U) +/*! ACCURACY - Clock Accuracy */ +#define I3C_STCCLOCK_ACCURACY(x) (((uint32_t)(((uint32_t)(x)) << I3C_STCCLOCK_ACCURACY_SHIFT)) & I3C_STCCLOCK_ACCURACY_MASK) + +#define I3C_STCCLOCK_FREQ_MASK (0xFF00U) +#define I3C_STCCLOCK_FREQ_SHIFT (8U) +/*! FREQ - Clock Frequency */ +#define I3C_STCCLOCK_FREQ(x) (((uint32_t)(((uint32_t)(x)) << I3C_STCCLOCK_FREQ_SHIFT)) & I3C_STCCLOCK_FREQ_MASK) +/*! @} */ + +/*! @name SMSGMAPADDR - Target Message Map Address */ +/*! @{ */ + +#define I3C_SMSGMAPADDR_MAPLAST_MASK (0xFU) +#define I3C_SMSGMAPADDR_MAPLAST_SHIFT (0U) +/*! MAPLAST - Matched Address Index */ +#define I3C_SMSGMAPADDR_MAPLAST(x) (((uint32_t)(((uint32_t)(x)) << I3C_SMSGMAPADDR_MAPLAST_SHIFT)) & I3C_SMSGMAPADDR_MAPLAST_MASK) + +#define I3C_SMSGMAPADDR_LASTSTATIC_MASK (0x10U) +#define I3C_SMSGMAPADDR_LASTSTATIC_SHIFT (4U) +/*! LASTSTATIC - Last Static Address Matched + * 0b0..I3C dynamic address + * 0b1..I2C static address + */ +#define I3C_SMSGMAPADDR_LASTSTATIC(x) (((uint32_t)(((uint32_t)(x)) << I3C_SMSGMAPADDR_LASTSTATIC_SHIFT)) & I3C_SMSGMAPADDR_LASTSTATIC_MASK) + +#define I3C_SMSGMAPADDR_MAPLASTM1_MASK (0xF00U) +#define I3C_SMSGMAPADDR_MAPLASTM1_SHIFT (8U) +/*! MAPLASTM1 - Matched Previous Address Index 1 */ +#define I3C_SMSGMAPADDR_MAPLASTM1(x) (((uint32_t)(((uint32_t)(x)) << I3C_SMSGMAPADDR_MAPLASTM1_SHIFT)) & I3C_SMSGMAPADDR_MAPLASTM1_MASK) + +#define I3C_SMSGMAPADDR_MAPLASTM2_MASK (0xF0000U) +#define I3C_SMSGMAPADDR_MAPLASTM2_SHIFT (16U) +/*! MAPLASTM2 - Matched Previous Index 2 */ +#define I3C_SMSGMAPADDR_MAPLASTM2(x) (((uint32_t)(((uint32_t)(x)) << I3C_SMSGMAPADDR_MAPLASTM2_SHIFT)) & I3C_SMSGMAPADDR_MAPLASTM2_MASK) +/*! @} */ + +/*! @name MCONFIG_EXT - Controller Extended Configuration */ +/*! @{ */ + +#define I3C_MCONFIG_EXT_I2CBLOW_MASK (0xFU) +#define I3C_MCONFIG_EXT_I2CBLOW_SHIFT (0U) +/*! I2CBLOW - I2C Baud Low */ +#define I3C_MCONFIG_EXT_I2CBLOW(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_EXT_I2CBLOW_SHIFT)) & I3C_MCONFIG_EXT_I2CBLOW_MASK) + +#define I3C_MCONFIG_EXT_I2CHS_MASK (0x10U) +#define I3C_MCONFIG_EXT_I2CHS_SHIFT (4U) +/*! I2CHS - I2C HS */ +#define I3C_MCONFIG_EXT_I2CHS(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_EXT_I2CHS_SHIFT)) & I3C_MCONFIG_EXT_I2CHS_MASK) + +#define I3C_MCONFIG_EXT_I2C_A10B_MASK (0x100U) +#define I3C_MCONFIG_EXT_I2C_A10B_SHIFT (8U) +/*! I2C_A10B - I2C_A10B + * 0b0..Disable + * 0b1..Enable + */ +#define I3C_MCONFIG_EXT_I2C_A10B(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_EXT_I2C_A10B_SHIFT)) & I3C_MCONFIG_EXT_I2C_A10B_MASK) + +#define I3C_MCONFIG_EXT_I2C_A10BEXT_MASK (0xE00U) +#define I3C_MCONFIG_EXT_I2C_A10BEXT_SHIFT (9U) +/*! I2C_A10BEXT - I2C_A10BEXT */ +#define I3C_MCONFIG_EXT_I2C_A10BEXT(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_EXT_I2C_A10BEXT_SHIFT)) & I3C_MCONFIG_EXT_I2C_A10BEXT_MASK) + +#define I3C_MCONFIG_EXT_I3C_CAS_DEL_MASK (0x30000U) +#define I3C_MCONFIG_EXT_I3C_CAS_DEL_SHIFT (16U) +/*! I3C_CAS_DEL - I3C CAS Delay After START + * 0b00..No delay + * 0b01..Increases SCL clock period by 1/2 + * 0b10..Increases SCL clock period by 1 + * 0b11..Increases SCL clock period by 3/2 + */ +#define I3C_MCONFIG_EXT_I3C_CAS_DEL(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_EXT_I3C_CAS_DEL_SHIFT)) & I3C_MCONFIG_EXT_I3C_CAS_DEL_MASK) + +#define I3C_MCONFIG_EXT_I3C_CASR_DEL_MASK (0xC0000U) +#define I3C_MCONFIG_EXT_I3C_CASR_DEL_SHIFT (18U) +/*! I3C_CASR_DEL - I3C CAS Delay After Repeated START + * 0b00..No delay + * 0b01..Increases SCL clock period by 1/2 + * 0b10..Increases SCL clock period by 1 + * 0b11..Increases SCL clock period by 1 1/2 + */ +#define I3C_MCONFIG_EXT_I3C_CASR_DEL(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_EXT_I3C_CASR_DEL_SHIFT)) & I3C_MCONFIG_EXT_I3C_CASR_DEL_MASK) +/*! @} */ + +/*! @name MCTRL - Controller Control */ +/*! @{ */ + +#define I3C_MCTRL_REQUEST_MASK (0x7U) +#define I3C_MCTRL_REQUEST_SHIFT (0U) +/*! REQUEST - Request + * 0b000..NONE + * 0b001..EMITSTARTADDR + * 0b010..EMITSTOP + * 0b011..IBIACKNACK + * 0b100..PROCESSDAA + * 0b101.. + * 0b110..Force Exit and Target Reset + * 0b111..AUTOIBI + */ +#define I3C_MCTRL_REQUEST(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCTRL_REQUEST_SHIFT)) & I3C_MCTRL_REQUEST_MASK) + +#define I3C_MCTRL_TYPE_MASK (0x30U) +#define I3C_MCTRL_TYPE_SHIFT (4U) +/*! TYPE - Bus Type with EmitStartAddr + * 0b00..I3C + * 0b01..I2C + * 0b10..DDR + * 0b11.. + */ +#define I3C_MCTRL_TYPE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCTRL_TYPE_SHIFT)) & I3C_MCTRL_TYPE_MASK) + +#define I3C_MCTRL_IBIRESP_MASK (0xC0U) +#define I3C_MCTRL_IBIRESP_SHIFT (6U) +/*! IBIRESP - In-Band Interrupt Response + * 0b00..ACK (acknowledge) + * 0b01..NACK (reject) + * 0b10..Acknowledge with mandatory byte + * 0b11..Manual + */ +#define I3C_MCTRL_IBIRESP(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCTRL_IBIRESP_SHIFT)) & I3C_MCTRL_IBIRESP_MASK) + +#define I3C_MCTRL_DIR_MASK (0x100U) +#define I3C_MCTRL_DIR_SHIFT (8U) +/*! DIR - Direction + * 0b0..Write + * 0b1..Read + */ +#define I3C_MCTRL_DIR(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCTRL_DIR_SHIFT)) & I3C_MCTRL_DIR_MASK) + +#define I3C_MCTRL_ADDR_MASK (0xFE00U) +#define I3C_MCTRL_ADDR_SHIFT (9U) +/*! ADDR - Address */ +#define I3C_MCTRL_ADDR(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCTRL_ADDR_SHIFT)) & I3C_MCTRL_ADDR_MASK) + +#define I3C_MCTRL_RDTERM_MASK (0xFF0000U) +#define I3C_MCTRL_RDTERM_SHIFT (16U) +/*! RDTERM - Read Terminate Counter */ +#define I3C_MCTRL_RDTERM(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCTRL_RDTERM_SHIFT)) & I3C_MCTRL_RDTERM_MASK) +/*! @} */ + +/*! @name MSTATUS - Controller Status */ +/*! @{ */ + +#define I3C_MSTATUS_STATE_MASK (0x7U) +#define I3C_MSTATUS_STATE_SHIFT (0U) +/*! STATE - State of the Controller + * 0b000..IDLE (bus has stopped) + * 0b001..SLVREQ (target request) + * 0b010..MSGSDR + * 0b011..NORMACT + * 0b100..MSGDDR + * 0b101..DAA + * 0b110..IBIACK + * 0b111..IBIRCV + */ +#define I3C_MSTATUS_STATE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_STATE_SHIFT)) & I3C_MSTATUS_STATE_MASK) + +#define I3C_MSTATUS_BETWEEN_MASK (0x10U) +#define I3C_MSTATUS_BETWEEN_SHIFT (4U) +/*! BETWEEN - Between + * 0b0..Inactive (for other cases) + * 0b1..Active + */ +#define I3C_MSTATUS_BETWEEN(x) (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_BETWEEN_SHIFT)) & I3C_MSTATUS_BETWEEN_MASK) + +#define I3C_MSTATUS_NACKED_MASK (0x20U) +#define I3C_MSTATUS_NACKED_SHIFT (5U) +/*! NACKED - Not Acknowledged + * 0b0..Not NACKed + * 0b1..NACKed (not acknowledged) + */ +#define I3C_MSTATUS_NACKED(x) (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_NACKED_SHIFT)) & I3C_MSTATUS_NACKED_MASK) + +#define I3C_MSTATUS_IBITYPE_MASK (0xC0U) +#define I3C_MSTATUS_IBITYPE_SHIFT (6U) +/*! IBITYPE - In-Band Interrupt (IBI) Type + * 0b00..NONE (no IBI: this status occurs when MSTATUS[IBIWON] becomes 0) + * 0b01..IBI + * 0b10..CR + * 0b11..HJ + */ +#define I3C_MSTATUS_IBITYPE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_IBITYPE_SHIFT)) & I3C_MSTATUS_IBITYPE_MASK) + +#define I3C_MSTATUS_SLVSTART_MASK (0x100U) +#define I3C_MSTATUS_SLVSTART_SHIFT (8U) +/*! SLVSTART - Target Start Flag + * 0b0..Target not requesting START + * 0b0..No effect + * 0b1..Target requesting START + * 0b1..Clear the flag + */ +#define I3C_MSTATUS_SLVSTART(x) (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_SLVSTART_SHIFT)) & I3C_MSTATUS_SLVSTART_MASK) + +#define I3C_MSTATUS_MCTRLDONE_MASK (0x200U) +#define I3C_MSTATUS_MCTRLDONE_SHIFT (9U) +/*! MCTRLDONE - Controller Control Done Flag + * 0b0..Not done + * 0b0..No effect + * 0b1..Done + * 0b1..Clear the flag + */ +#define I3C_MSTATUS_MCTRLDONE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_MCTRLDONE_SHIFT)) & I3C_MSTATUS_MCTRLDONE_MASK) + +#define I3C_MSTATUS_COMPLETE_MASK (0x400U) +#define I3C_MSTATUS_COMPLETE_SHIFT (10U) +/*! COMPLETE - Complete Flag + * 0b0..Not complete + * 0b0..No effect + * 0b1..Complete + * 0b1..Clear the flag + */ +#define I3C_MSTATUS_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_COMPLETE_SHIFT)) & I3C_MSTATUS_COMPLETE_MASK) + +#define I3C_MSTATUS_RXPEND_MASK (0x800U) +#define I3C_MSTATUS_RXPEND_SHIFT (11U) +/*! RXPEND - RXPEND + * 0b0..No receive message pending + * 0b1..Receive message pending + */ +#define I3C_MSTATUS_RXPEND(x) (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_RXPEND_SHIFT)) & I3C_MSTATUS_RXPEND_MASK) + +#define I3C_MSTATUS_TXNOTFULL_MASK (0x1000U) +#define I3C_MSTATUS_TXNOTFULL_SHIFT (12U) +/*! TXNOTFULL - TX Buffer or FIFO Not Full + * 0b0..Receive buffer or FIFO full + * 0b1..Receive buffer or FIFO not full + */ +#define I3C_MSTATUS_TXNOTFULL(x) (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_TXNOTFULL_SHIFT)) & I3C_MSTATUS_TXNOTFULL_MASK) + +#define I3C_MSTATUS_IBIWON_MASK (0x2000U) +#define I3C_MSTATUS_IBIWON_SHIFT (13U) +/*! IBIWON - In-Band Interrupt (IBI) Won Flag + * 0b0..No IBI arbitration won + * 0b0..No effect + * 0b1..IBI arbitration won + * 0b1..Clear the flag + */ +#define I3C_MSTATUS_IBIWON(x) (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_IBIWON_SHIFT)) & I3C_MSTATUS_IBIWON_MASK) + +#define I3C_MSTATUS_ERRWARN_MASK (0x8000U) +#define I3C_MSTATUS_ERRWARN_SHIFT (15U) +/*! ERRWARN - Error or Warning + * 0b0..No error or warning + * 0b1..Error or warning + */ +#define I3C_MSTATUS_ERRWARN(x) (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_ERRWARN_SHIFT)) & I3C_MSTATUS_ERRWARN_MASK) + +#define I3C_MSTATUS_NOWMASTER_MASK (0x80000U) +#define I3C_MSTATUS_NOWMASTER_SHIFT (19U) +/*! NOWMASTER - Module is now Controller Flag + * 0b0..Not a controller + * 0b0..No effect + * 0b1..Controller + * 0b1..Clear the flag + */ +#define I3C_MSTATUS_NOWMASTER(x) (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_NOWMASTER_SHIFT)) & I3C_MSTATUS_NOWMASTER_MASK) + +#define I3C_MSTATUS_IBIADDR_MASK (0x7F000000U) +#define I3C_MSTATUS_IBIADDR_SHIFT (24U) +/*! IBIADDR - IBI Address */ +#define I3C_MSTATUS_IBIADDR(x) (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_IBIADDR_SHIFT)) & I3C_MSTATUS_IBIADDR_MASK) +/*! @} */ + +/*! @name MIBIRULES - Controller In-band Interrupt Registry and Rules */ +/*! @{ */ + +#define I3C_MIBIRULES_ADDR0_MASK (0x3FU) +#define I3C_MIBIRULES_ADDR0_SHIFT (0U) +/*! ADDR0 - ADDR0 */ +#define I3C_MIBIRULES_ADDR0(x) (((uint32_t)(((uint32_t)(x)) << I3C_MIBIRULES_ADDR0_SHIFT)) & I3C_MIBIRULES_ADDR0_MASK) + +#define I3C_MIBIRULES_ADDR1_MASK (0xFC0U) +#define I3C_MIBIRULES_ADDR1_SHIFT (6U) +/*! ADDR1 - ADDR1 */ +#define I3C_MIBIRULES_ADDR1(x) (((uint32_t)(((uint32_t)(x)) << I3C_MIBIRULES_ADDR1_SHIFT)) & I3C_MIBIRULES_ADDR1_MASK) + +#define I3C_MIBIRULES_ADDR2_MASK (0x3F000U) +#define I3C_MIBIRULES_ADDR2_SHIFT (12U) +/*! ADDR2 - ADDR2 */ +#define I3C_MIBIRULES_ADDR2(x) (((uint32_t)(((uint32_t)(x)) << I3C_MIBIRULES_ADDR2_SHIFT)) & I3C_MIBIRULES_ADDR2_MASK) + +#define I3C_MIBIRULES_ADDR3_MASK (0xFC0000U) +#define I3C_MIBIRULES_ADDR3_SHIFT (18U) +/*! ADDR3 - ADDR3 */ +#define I3C_MIBIRULES_ADDR3(x) (((uint32_t)(((uint32_t)(x)) << I3C_MIBIRULES_ADDR3_SHIFT)) & I3C_MIBIRULES_ADDR3_MASK) + +#define I3C_MIBIRULES_ADDR4_MASK (0x3F000000U) +#define I3C_MIBIRULES_ADDR4_SHIFT (24U) +/*! ADDR4 - ADDR4 */ +#define I3C_MIBIRULES_ADDR4(x) (((uint32_t)(((uint32_t)(x)) << I3C_MIBIRULES_ADDR4_SHIFT)) & I3C_MIBIRULES_ADDR4_MASK) + +#define I3C_MIBIRULES_MSB0_MASK (0x40000000U) +#define I3C_MIBIRULES_MSB0_SHIFT (30U) +/*! MSB0 - Most Significant Address Bit is 0 + * 0b0..MSB is not 0 + * 0b1..MSB is 0 + */ +#define I3C_MIBIRULES_MSB0(x) (((uint32_t)(((uint32_t)(x)) << I3C_MIBIRULES_MSB0_SHIFT)) & I3C_MIBIRULES_MSB0_MASK) + +#define I3C_MIBIRULES_NOBYTE_MASK (0x80000000U) +#define I3C_MIBIRULES_NOBYTE_SHIFT (31U) +/*! NOBYTE - No IBI byte + * 0b0..With mandatory IBI byte + * 0b1..Without mandatory IBI byte + */ +#define I3C_MIBIRULES_NOBYTE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MIBIRULES_NOBYTE_SHIFT)) & I3C_MIBIRULES_NOBYTE_MASK) +/*! @} */ + +/*! @name MINTSET - Controller Interrupt Set */ +/*! @{ */ + +#define I3C_MINTSET_SLVSTART_MASK (0x100U) +#define I3C_MINTSET_SLVSTART_SHIFT (8U) +/*! SLVSTART - Target Start Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define I3C_MINTSET_SLVSTART(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTSET_SLVSTART_SHIFT)) & I3C_MINTSET_SLVSTART_MASK) + +#define I3C_MINTSET_MCTRLDONE_MASK (0x200U) +#define I3C_MINTSET_MCTRLDONE_SHIFT (9U) +/*! MCTRLDONE - Controller Control Done Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define I3C_MINTSET_MCTRLDONE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTSET_MCTRLDONE_SHIFT)) & I3C_MINTSET_MCTRLDONE_MASK) + +#define I3C_MINTSET_COMPLETE_MASK (0x400U) +#define I3C_MINTSET_COMPLETE_SHIFT (10U) +/*! COMPLETE - Completed Message Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define I3C_MINTSET_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTSET_COMPLETE_SHIFT)) & I3C_MINTSET_COMPLETE_MASK) + +#define I3C_MINTSET_RXPEND_MASK (0x800U) +#define I3C_MINTSET_RXPEND_SHIFT (11U) +/*! RXPEND - Receive Pending Interrupt Enable */ +#define I3C_MINTSET_RXPEND(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTSET_RXPEND_SHIFT)) & I3C_MINTSET_RXPEND_MASK) + +#define I3C_MINTSET_TXNOTFULL_MASK (0x1000U) +#define I3C_MINTSET_TXNOTFULL_SHIFT (12U) +/*! TXNOTFULL - Transmit Buffer/FIFO Not Full Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define I3C_MINTSET_TXNOTFULL(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTSET_TXNOTFULL_SHIFT)) & I3C_MINTSET_TXNOTFULL_MASK) + +#define I3C_MINTSET_IBIWON_MASK (0x2000U) +#define I3C_MINTSET_IBIWON_SHIFT (13U) +/*! IBIWON - IBI Won Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define I3C_MINTSET_IBIWON(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTSET_IBIWON_SHIFT)) & I3C_MINTSET_IBIWON_MASK) + +#define I3C_MINTSET_ERRWARN_MASK (0x8000U) +#define I3C_MINTSET_ERRWARN_SHIFT (15U) +/*! ERRWARN - Error or Warning (ERRWARN) Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define I3C_MINTSET_ERRWARN(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTSET_ERRWARN_SHIFT)) & I3C_MINTSET_ERRWARN_MASK) + +#define I3C_MINTSET_NOWMASTER_MASK (0x80000U) +#define I3C_MINTSET_NOWMASTER_SHIFT (19U) +/*! NOWMASTER - Now Controller Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define I3C_MINTSET_NOWMASTER(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTSET_NOWMASTER_SHIFT)) & I3C_MINTSET_NOWMASTER_MASK) +/*! @} */ + +/*! @name MINTCLR - Controller Interrupt Clear */ +/*! @{ */ + +#define I3C_MINTCLR_SLVSTART_MASK (0x100U) +#define I3C_MINTCLR_SLVSTART_SHIFT (8U) +/*! SLVSTART - SLVSTART Interrupt Enable Clear Flag + * 0b0..No effect + * 0b0..No effect + * 0b1..Interrupt enable cleared + * 0b1..Clear the flag + */ +#define I3C_MINTCLR_SLVSTART(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTCLR_SLVSTART_SHIFT)) & I3C_MINTCLR_SLVSTART_MASK) + +#define I3C_MINTCLR_MCTRLDONE_MASK (0x200U) +#define I3C_MINTCLR_MCTRLDONE_SHIFT (9U) +/*! MCTRLDONE - MCTRLDONE Interrupt Enable Clear Flag + * 0b0..No effect + * 0b0..No effect + * 0b1..Interrupt enable cleared + * 0b1..Clear the flag + */ +#define I3C_MINTCLR_MCTRLDONE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTCLR_MCTRLDONE_SHIFT)) & I3C_MINTCLR_MCTRLDONE_MASK) + +#define I3C_MINTCLR_COMPLETE_MASK (0x400U) +#define I3C_MINTCLR_COMPLETE_SHIFT (10U) +/*! COMPLETE - COMPLETE Interrupt Enable Clear Flag + * 0b0..No effect + * 0b0..No effect + * 0b1..Interrupt enable cleared + * 0b1..Clear the flag + */ +#define I3C_MINTCLR_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTCLR_COMPLETE_SHIFT)) & I3C_MINTCLR_COMPLETE_MASK) + +#define I3C_MINTCLR_RXPEND_MASK (0x800U) +#define I3C_MINTCLR_RXPEND_SHIFT (11U) +/*! RXPEND - RXPEND Interrupt Enable Clear Flag + * 0b0..No effect + * 0b0..No effect + * 0b1..Interrupt enable cleared + * 0b1..Clear the flag + */ +#define I3C_MINTCLR_RXPEND(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTCLR_RXPEND_SHIFT)) & I3C_MINTCLR_RXPEND_MASK) + +#define I3C_MINTCLR_TXNOTFULL_MASK (0x1000U) +#define I3C_MINTCLR_TXNOTFULL_SHIFT (12U) +/*! TXNOTFULL - TXNOTFULL Interrupt Enable Clear Flag + * 0b0..No effect + * 0b0..No effect + * 0b1..Interrupt enable cleared + * 0b1..Clear the flag + */ +#define I3C_MINTCLR_TXNOTFULL(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTCLR_TXNOTFULL_SHIFT)) & I3C_MINTCLR_TXNOTFULL_MASK) + +#define I3C_MINTCLR_IBIWON_MASK (0x2000U) +#define I3C_MINTCLR_IBIWON_SHIFT (13U) +/*! IBIWON - IBIWON Interrupt Enable Clear Flag + * 0b0..No effect + * 0b0..No effect + * 0b1..Interrupt enable cleared + * 0b1..Clear the flag + */ +#define I3C_MINTCLR_IBIWON(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTCLR_IBIWON_SHIFT)) & I3C_MINTCLR_IBIWON_MASK) + +#define I3C_MINTCLR_ERRWARN_MASK (0x8000U) +#define I3C_MINTCLR_ERRWARN_SHIFT (15U) +/*! ERRWARN - ERRWARN Interrupt Enable Clear Flag + * 0b0..No effect + * 0b0..No effect + * 0b1..Interrupt enable cleared + * 0b1..Clear the flag + */ +#define I3C_MINTCLR_ERRWARN(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTCLR_ERRWARN_SHIFT)) & I3C_MINTCLR_ERRWARN_MASK) + +#define I3C_MINTCLR_NOWMASTER_MASK (0x80000U) +#define I3C_MINTCLR_NOWMASTER_SHIFT (19U) +/*! NOWMASTER - NOWCONTROLLER Interrupt Enable Clear Flag + * 0b0..No effect + * 0b0..No effect + * 0b1..Interrupt enable cleared + * 0b1..Clear the flag + */ +#define I3C_MINTCLR_NOWMASTER(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTCLR_NOWMASTER_SHIFT)) & I3C_MINTCLR_NOWMASTER_MASK) +/*! @} */ + +/*! @name MINTMASKED - Controller Interrupt Mask */ +/*! @{ */ + +#define I3C_MINTMASKED_SLVSTART_MASK (0x100U) +#define I3C_MINTMASKED_SLVSTART_SHIFT (8U) +/*! SLVSTART - SLVSTART Interrupt Mask + * 0b0..Disabled + * 0b1..Enabled + */ +#define I3C_MINTMASKED_SLVSTART(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTMASKED_SLVSTART_SHIFT)) & I3C_MINTMASKED_SLVSTART_MASK) + +#define I3C_MINTMASKED_MCTRLDONE_MASK (0x200U) +#define I3C_MINTMASKED_MCTRLDONE_SHIFT (9U) +/*! MCTRLDONE - MCTRLDONE Interrupt Mask + * 0b0..Disabled + * 0b1..Enabled + */ +#define I3C_MINTMASKED_MCTRLDONE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTMASKED_MCTRLDONE_SHIFT)) & I3C_MINTMASKED_MCTRLDONE_MASK) + +#define I3C_MINTMASKED_COMPLETE_MASK (0x400U) +#define I3C_MINTMASKED_COMPLETE_SHIFT (10U) +/*! COMPLETE - COMPLETE Interrupt Mask + * 0b0..Disabled + * 0b1..Enabled + */ +#define I3C_MINTMASKED_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTMASKED_COMPLETE_SHIFT)) & I3C_MINTMASKED_COMPLETE_MASK) + +#define I3C_MINTMASKED_RXPEND_MASK (0x800U) +#define I3C_MINTMASKED_RXPEND_SHIFT (11U) +/*! RXPEND - RXPEND Interrupt Mask */ +#define I3C_MINTMASKED_RXPEND(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTMASKED_RXPEND_SHIFT)) & I3C_MINTMASKED_RXPEND_MASK) + +#define I3C_MINTMASKED_TXNOTFULL_MASK (0x1000U) +#define I3C_MINTMASKED_TXNOTFULL_SHIFT (12U) +/*! TXNOTFULL - TXNOTFULL Interrupt Mask + * 0b0..Disabled + * 0b1..Enabled + */ +#define I3C_MINTMASKED_TXNOTFULL(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTMASKED_TXNOTFULL_SHIFT)) & I3C_MINTMASKED_TXNOTFULL_MASK) + +#define I3C_MINTMASKED_IBIWON_MASK (0x2000U) +#define I3C_MINTMASKED_IBIWON_SHIFT (13U) +/*! IBIWON - IBIWON Interrupt Mask + * 0b0..Disabled + * 0b1..Enabled + */ +#define I3C_MINTMASKED_IBIWON(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTMASKED_IBIWON_SHIFT)) & I3C_MINTMASKED_IBIWON_MASK) + +#define I3C_MINTMASKED_ERRWARN_MASK (0x8000U) +#define I3C_MINTMASKED_ERRWARN_SHIFT (15U) +/*! ERRWARN - ERRWARN Interrupt Mask + * 0b0..Disabled + * 0b1..Enabled + */ +#define I3C_MINTMASKED_ERRWARN(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTMASKED_ERRWARN_SHIFT)) & I3C_MINTMASKED_ERRWARN_MASK) + +#define I3C_MINTMASKED_NOWMASTER_MASK (0x80000U) +#define I3C_MINTMASKED_NOWMASTER_SHIFT (19U) +/*! NOWMASTER - NOWCONTROLLER Interrupt Mask + * 0b0..Disabled + * 0b1..Enabled + */ +#define I3C_MINTMASKED_NOWMASTER(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTMASKED_NOWMASTER_SHIFT)) & I3C_MINTMASKED_NOWMASTER_MASK) +/*! @} */ + +/*! @name MERRWARN - Controller Errors and Warnings */ +/*! @{ */ + +#define I3C_MERRWARN_URUN_MASK (0x2U) +#define I3C_MERRWARN_URUN_SHIFT (1U) +/*! URUN - Underrun Error Flag + * 0b0..No error + * 0b0..No effect + * 0b1..Error + * 0b1..Clear the flag + */ +#define I3C_MERRWARN_URUN(x) (((uint32_t)(((uint32_t)(x)) << I3C_MERRWARN_URUN_SHIFT)) & I3C_MERRWARN_URUN_MASK) + +#define I3C_MERRWARN_NACK_MASK (0x4U) +#define I3C_MERRWARN_NACK_SHIFT (2U) +/*! NACK - Not Acknowledge Error Flag + * 0b0..No error + * 0b0..No effect + * 0b1..Error + * 0b1..Clear the flag + */ +#define I3C_MERRWARN_NACK(x) (((uint32_t)(((uint32_t)(x)) << I3C_MERRWARN_NACK_SHIFT)) & I3C_MERRWARN_NACK_MASK) + +#define I3C_MERRWARN_WRABT_MASK (0x8U) +#define I3C_MERRWARN_WRABT_SHIFT (3U) +/*! WRABT - Write Abort Error Flag + * 0b0..No error + * 0b0..No effect + * 0b1..Error + * 0b1..Clear the flag + */ +#define I3C_MERRWARN_WRABT(x) (((uint32_t)(((uint32_t)(x)) << I3C_MERRWARN_WRABT_SHIFT)) & I3C_MERRWARN_WRABT_MASK) + +#define I3C_MERRWARN_TERM_MASK (0x10U) +#define I3C_MERRWARN_TERM_SHIFT (4U) +/*! TERM - Terminate Error Flag + * 0b0..No error + * 0b0..No effect + * 0b1..Error + * 0b1..Clear the flag + */ +#define I3C_MERRWARN_TERM(x) (((uint32_t)(((uint32_t)(x)) << I3C_MERRWARN_TERM_SHIFT)) & I3C_MERRWARN_TERM_MASK) + +#define I3C_MERRWARN_HPAR_MASK (0x200U) +#define I3C_MERRWARN_HPAR_SHIFT (9U) +/*! HPAR - High Data Rate Parity Flag + * 0b0..No error + * 0b0..No effect + * 0b1..Error + * 0b1..Clear the flag + */ +#define I3C_MERRWARN_HPAR(x) (((uint32_t)(((uint32_t)(x)) << I3C_MERRWARN_HPAR_SHIFT)) & I3C_MERRWARN_HPAR_MASK) + +#define I3C_MERRWARN_HCRC_MASK (0x400U) +#define I3C_MERRWARN_HCRC_SHIFT (10U) +/*! HCRC - High Data Rate CRC Error Flag + * 0b0..No error + * 0b0..No effect + * 0b1..Error + * 0b1..Clear the flag + */ +#define I3C_MERRWARN_HCRC(x) (((uint32_t)(((uint32_t)(x)) << I3C_MERRWARN_HCRC_SHIFT)) & I3C_MERRWARN_HCRC_MASK) + +#define I3C_MERRWARN_OREAD_MASK (0x10000U) +#define I3C_MERRWARN_OREAD_SHIFT (16U) +/*! OREAD - Overread Error Flag + * 0b0..No error + * 0b0..No effect + * 0b1..Error + * 0b1..Clear the flag + */ +#define I3C_MERRWARN_OREAD(x) (((uint32_t)(((uint32_t)(x)) << I3C_MERRWARN_OREAD_SHIFT)) & I3C_MERRWARN_OREAD_MASK) + +#define I3C_MERRWARN_OWRITE_MASK (0x20000U) +#define I3C_MERRWARN_OWRITE_SHIFT (17U) +/*! OWRITE - Overwrite Error Flag + * 0b0..No error + * 0b0..No effect + * 0b1..Error + * 0b1..Clear the flag + */ +#define I3C_MERRWARN_OWRITE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MERRWARN_OWRITE_SHIFT)) & I3C_MERRWARN_OWRITE_MASK) + +#define I3C_MERRWARN_MSGERR_MASK (0x40000U) +#define I3C_MERRWARN_MSGERR_SHIFT (18U) +/*! MSGERR - Message Error Flag + * 0b0..No error + * 0b0..No effect + * 0b1..Error + * 0b1..Clear the flag + */ +#define I3C_MERRWARN_MSGERR(x) (((uint32_t)(((uint32_t)(x)) << I3C_MERRWARN_MSGERR_SHIFT)) & I3C_MERRWARN_MSGERR_MASK) + +#define I3C_MERRWARN_INVREQ_MASK (0x80000U) +#define I3C_MERRWARN_INVREQ_SHIFT (19U) +/*! INVREQ - Invalid Request Error Flag + * 0b0..No error + * 0b0..No effect + * 0b1..Error + * 0b1..Clear the flag + */ +#define I3C_MERRWARN_INVREQ(x) (((uint32_t)(((uint32_t)(x)) << I3C_MERRWARN_INVREQ_SHIFT)) & I3C_MERRWARN_INVREQ_MASK) + +#define I3C_MERRWARN_TIMEOUT_MASK (0x100000U) +#define I3C_MERRWARN_TIMEOUT_SHIFT (20U) +/*! TIMEOUT - Timeout Error Flag + * 0b0..No error + * 0b0..No effect + * 0b1..Error + * 0b1..Clear the flag + */ +#define I3C_MERRWARN_TIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << I3C_MERRWARN_TIMEOUT_SHIFT)) & I3C_MERRWARN_TIMEOUT_MASK) +/*! @} */ + +/*! @name MDMACTRL - Controller DMA Control */ +/*! @{ */ + +#define I3C_MDMACTRL_DMAFB_MASK (0x3U) +#define I3C_MDMACTRL_DMAFB_SHIFT (0U) +/*! DMAFB - DMA from Bus + * 0b00..DMA not used + * 0b01..Enable DMA for one frame + * 0b10..Enable DMA until DMA is turned off + * 0b11.. + */ +#define I3C_MDMACTRL_DMAFB(x) (((uint32_t)(((uint32_t)(x)) << I3C_MDMACTRL_DMAFB_SHIFT)) & I3C_MDMACTRL_DMAFB_MASK) + +#define I3C_MDMACTRL_DMATB_MASK (0xCU) +#define I3C_MDMACTRL_DMATB_SHIFT (2U) +/*! DMATB - DMA to Bus + * 0b00..DMA not used + * 0b01..Enable DMA for one frame (ended by DMA or terminated) + * 0b10..Enable DMA until DMA is turned off + * 0b11.. + */ +#define I3C_MDMACTRL_DMATB(x) (((uint32_t)(((uint32_t)(x)) << I3C_MDMACTRL_DMATB_SHIFT)) & I3C_MDMACTRL_DMATB_MASK) + +#define I3C_MDMACTRL_DMAWIDTH_MASK (0x30U) +#define I3C_MDMACTRL_DMAWIDTH_SHIFT (4U) +/*! DMAWIDTH - DMA Width + * 0b00, 0b01..Byte + * 0b10..Halfword (16 bits) + * 0b11.. + */ +#define I3C_MDMACTRL_DMAWIDTH(x) (((uint32_t)(((uint32_t)(x)) << I3C_MDMACTRL_DMAWIDTH_SHIFT)) & I3C_MDMACTRL_DMAWIDTH_MASK) + +#define I3C_MDMACTRL_BULKFB_MASK (0x40U) +#define I3C_MDMACTRL_BULKFB_SHIFT (6U) +/*! BULKFB - Bulk Transfer from Bus + * 0b0..Disable + * 0b1..Enable + */ +#define I3C_MDMACTRL_BULKFB(x) (((uint32_t)(((uint32_t)(x)) << I3C_MDMACTRL_BULKFB_SHIFT)) & I3C_MDMACTRL_BULKFB_MASK) + +#define I3C_MDMACTRL_BULKTB_MASK (0x80U) +#define I3C_MDMACTRL_BULKTB_SHIFT (7U) +/*! BULKTB - Bulk Transfer to Bus + * 0b0..Disable + * 0b1..Enable + */ +#define I3C_MDMACTRL_BULKTB(x) (((uint32_t)(((uint32_t)(x)) << I3C_MDMACTRL_BULKTB_SHIFT)) & I3C_MDMACTRL_BULKTB_MASK) +/*! @} */ + +/*! @name MDATACTRL - Controller Data Control */ +/*! @{ */ + +#define I3C_MDATACTRL_FLUSHTB_MASK (0x1U) +#define I3C_MDATACTRL_FLUSHTB_SHIFT (0U) +/*! FLUSHTB - Flush To-Bus Buffer or FIFO + * 0b0..No action + * 0b1..Flush the buffer + */ +#define I3C_MDATACTRL_FLUSHTB(x) (((uint32_t)(((uint32_t)(x)) << I3C_MDATACTRL_FLUSHTB_SHIFT)) & I3C_MDATACTRL_FLUSHTB_MASK) + +#define I3C_MDATACTRL_FLUSHFB_MASK (0x2U) +#define I3C_MDATACTRL_FLUSHFB_SHIFT (1U) +/*! FLUSHFB - Flush From-Bus Buffer or FIFO + * 0b0..No action + * 0b1..Flush the buffer + */ +#define I3C_MDATACTRL_FLUSHFB(x) (((uint32_t)(((uint32_t)(x)) << I3C_MDATACTRL_FLUSHFB_SHIFT)) & I3C_MDATACTRL_FLUSHFB_MASK) + +#define I3C_MDATACTRL_UNLOCK_MASK (0x8U) +#define I3C_MDATACTRL_UNLOCK_SHIFT (3U) +/*! UNLOCK - Unlock + * 0b0..Locked + * 0b1..Unlocked + */ +#define I3C_MDATACTRL_UNLOCK(x) (((uint32_t)(((uint32_t)(x)) << I3C_MDATACTRL_UNLOCK_SHIFT)) & I3C_MDATACTRL_UNLOCK_MASK) + +#define I3C_MDATACTRL_TXTRIG_MASK (0x30U) +#define I3C_MDATACTRL_TXTRIG_SHIFT (4U) +/*! TXTRIG - Transmit Trigger Level + * 0b00..Trigger when empty + * 0b01..Trigger when 1/4 full or less + * 0b10..Trigger when 1/2 full or less + * 0b11..Trigger when 1 less than full or less (default) + */ +#define I3C_MDATACTRL_TXTRIG(x) (((uint32_t)(((uint32_t)(x)) << I3C_MDATACTRL_TXTRIG_SHIFT)) & I3C_MDATACTRL_TXTRIG_MASK) + +#define I3C_MDATACTRL_RXTRIG_MASK (0xC0U) +#define I3C_MDATACTRL_RXTRIG_SHIFT (6U) +/*! RXTRIG - Receive Trigger Level + * 0b00..Trigger when not empty (default) + * 0b01..Trigger when 1/4 full or more + * 0b10..Trigger when 1/2 full or more + * 0b11..Trigger when 3/4 full or more + */ +#define I3C_MDATACTRL_RXTRIG(x) (((uint32_t)(((uint32_t)(x)) << I3C_MDATACTRL_RXTRIG_SHIFT)) & I3C_MDATACTRL_RXTRIG_MASK) + +#define I3C_MDATACTRL_TXCOUNT_MASK (0x1F0000U) +#define I3C_MDATACTRL_TXCOUNT_SHIFT (16U) +/*! TXCOUNT - Transmit Byte Count */ +#define I3C_MDATACTRL_TXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << I3C_MDATACTRL_TXCOUNT_SHIFT)) & I3C_MDATACTRL_TXCOUNT_MASK) + +#define I3C_MDATACTRL_RXCOUNT_MASK (0x1F000000U) +#define I3C_MDATACTRL_RXCOUNT_SHIFT (24U) +/*! RXCOUNT - Receive Byte Count */ +#define I3C_MDATACTRL_RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << I3C_MDATACTRL_RXCOUNT_SHIFT)) & I3C_MDATACTRL_RXCOUNT_MASK) + +#define I3C_MDATACTRL_TXFULL_MASK (0x40000000U) +#define I3C_MDATACTRL_TXFULL_SHIFT (30U) +/*! TXFULL - Transmit is Full + * 0b0..Not full + * 0b1..Full + */ +#define I3C_MDATACTRL_TXFULL(x) (((uint32_t)(((uint32_t)(x)) << I3C_MDATACTRL_TXFULL_SHIFT)) & I3C_MDATACTRL_TXFULL_MASK) + +#define I3C_MDATACTRL_RXEMPTY_MASK (0x80000000U) +#define I3C_MDATACTRL_RXEMPTY_SHIFT (31U) +/*! RXEMPTY - Receive is Empty + * 0b0..Not empty + * 0b1..Empty + */ +#define I3C_MDATACTRL_RXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << I3C_MDATACTRL_RXEMPTY_SHIFT)) & I3C_MDATACTRL_RXEMPTY_MASK) +/*! @} */ + +/*! @name MWDATAB - Controller Write Data Byte */ +/*! @{ */ + +#define I3C_MWDATAB_VALUE_MASK (0xFFU) +#define I3C_MWDATAB_VALUE_SHIFT (0U) +/*! VALUE - Data Byte */ +#define I3C_MWDATAB_VALUE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWDATAB_VALUE_SHIFT)) & I3C_MWDATAB_VALUE_MASK) + +#define I3C_MWDATAB_END_MASK (0x100U) +#define I3C_MWDATAB_END_SHIFT (8U) +/*! END - End of Message + * 0b0..Not the end + * 0b1..End + */ +#define I3C_MWDATAB_END(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWDATAB_END_SHIFT)) & I3C_MWDATAB_END_MASK) + +#define I3C_MWDATAB_END_ALSO_MASK (0x10000U) +#define I3C_MWDATAB_END_ALSO_SHIFT (16U) +/*! END_ALSO - End of Message ALSO + * 0b0..Not the end + * 0b1..End + */ +#define I3C_MWDATAB_END_ALSO(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWDATAB_END_ALSO_SHIFT)) & I3C_MWDATAB_END_ALSO_MASK) +/*! @} */ + +/*! @name MWDATABE - Controller Write Data Byte End */ +/*! @{ */ + +#define I3C_MWDATABE_VALUE_MASK (0xFFU) +#define I3C_MWDATABE_VALUE_SHIFT (0U) +/*! VALUE - Data */ +#define I3C_MWDATABE_VALUE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWDATABE_VALUE_SHIFT)) & I3C_MWDATABE_VALUE_MASK) +/*! @} */ + +/*! @name MWDATAH - Controller Write Data Halfword */ +/*! @{ */ + +#define I3C_MWDATAH_DATA0_MASK (0xFFU) +#define I3C_MWDATAH_DATA0_SHIFT (0U) +/*! DATA0 - Data Byte 0 */ +#define I3C_MWDATAH_DATA0(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWDATAH_DATA0_SHIFT)) & I3C_MWDATAH_DATA0_MASK) + +#define I3C_MWDATAH_DATA1_MASK (0xFF00U) +#define I3C_MWDATAH_DATA1_SHIFT (8U) +/*! DATA1 - Data Byte 1 */ +#define I3C_MWDATAH_DATA1(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWDATAH_DATA1_SHIFT)) & I3C_MWDATAH_DATA1_MASK) + +#define I3C_MWDATAH_END_MASK (0x10000U) +#define I3C_MWDATAH_END_SHIFT (16U) +/*! END - End of Message + * 0b0..Not the end + * 0b1..End + */ +#define I3C_MWDATAH_END(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWDATAH_END_SHIFT)) & I3C_MWDATAH_END_MASK) +/*! @} */ + +/*! @name MWDATAHE - Controller Write Data Halfword End */ +/*! @{ */ + +#define I3C_MWDATAHE_DATA0_MASK (0xFFU) +#define I3C_MWDATAHE_DATA0_SHIFT (0U) +/*! DATA0 - Data Byte 0 */ +#define I3C_MWDATAHE_DATA0(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWDATAHE_DATA0_SHIFT)) & I3C_MWDATAHE_DATA0_MASK) + +#define I3C_MWDATAHE_DATA1_MASK (0xFF00U) +#define I3C_MWDATAHE_DATA1_SHIFT (8U) +/*! DATA1 - Data Byte 1 */ +#define I3C_MWDATAHE_DATA1(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWDATAHE_DATA1_SHIFT)) & I3C_MWDATAHE_DATA1_MASK) +/*! @} */ + +/*! @name MRDATAB - Controller Read Data Byte */ +/*! @{ */ + +#define I3C_MRDATAB_VALUE_MASK (0xFFU) +#define I3C_MRDATAB_VALUE_SHIFT (0U) +/*! VALUE - Value */ +#define I3C_MRDATAB_VALUE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MRDATAB_VALUE_SHIFT)) & I3C_MRDATAB_VALUE_MASK) +/*! @} */ + +/*! @name MRDATAH - Controller Read Data Halfword */ +/*! @{ */ + +#define I3C_MRDATAH_LSB_MASK (0xFFU) +#define I3C_MRDATAH_LSB_SHIFT (0U) +/*! LSB - Low Byte */ +#define I3C_MRDATAH_LSB(x) (((uint32_t)(((uint32_t)(x)) << I3C_MRDATAH_LSB_SHIFT)) & I3C_MRDATAH_LSB_MASK) + +#define I3C_MRDATAH_MSB_MASK (0xFF00U) +#define I3C_MRDATAH_MSB_SHIFT (8U) +/*! MSB - High Byte */ +#define I3C_MRDATAH_MSB(x) (((uint32_t)(((uint32_t)(x)) << I3C_MRDATAH_MSB_SHIFT)) & I3C_MRDATAH_MSB_MASK) +/*! @} */ + +/*! @name MWDATAB1 - Controller Write Byte Data 1 (to Bus) */ +/*! @{ */ + +#define I3C_MWDATAB1_VALUE_MASK (0xFFU) +#define I3C_MWDATAB1_VALUE_SHIFT (0U) +/*! VALUE - Value */ +#define I3C_MWDATAB1_VALUE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWDATAB1_VALUE_SHIFT)) & I3C_MWDATAB1_VALUE_MASK) +/*! @} */ + +/*! @name MWDATAH1 - Controller Write Halfword Data (to Bus) */ +/*! @{ */ + +#define I3C_MWDATAH1_VALUE_MASK (0xFFFFU) +#define I3C_MWDATAH1_VALUE_SHIFT (0U) +/*! VALUE - Value */ +#define I3C_MWDATAH1_VALUE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWDATAH1_VALUE_SHIFT)) & I3C_MWDATAH1_VALUE_MASK) +/*! @} */ + +/*! @name MWMSG_SDR_CONTROL - Controller Write Message Control in SDR mode */ +/*! @{ */ + +#define I3C_MWMSG_SDR_CONTROL_DIR_MASK (0x1U) +#define I3C_MWMSG_SDR_CONTROL_DIR_SHIFT (0U) +/*! DIR - Direction + * 0b0..Write + * 0b1..Read + */ +#define I3C_MWMSG_SDR_CONTROL_DIR(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWMSG_SDR_CONTROL_DIR_SHIFT)) & I3C_MWMSG_SDR_CONTROL_DIR_MASK) + +#define I3C_MWMSG_SDR_CONTROL_ADDR_MASK (0xFEU) +#define I3C_MWMSG_SDR_CONTROL_ADDR_SHIFT (1U) +/*! ADDR - Address */ +#define I3C_MWMSG_SDR_CONTROL_ADDR(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWMSG_SDR_CONTROL_ADDR_SHIFT)) & I3C_MWMSG_SDR_CONTROL_ADDR_MASK) + +#define I3C_MWMSG_SDR_CONTROL_END_MASK (0x100U) +#define I3C_MWMSG_SDR_CONTROL_END_SHIFT (8U) +/*! END - End of SDR Message + * 0b0..Not the end + * 0b1..End + */ +#define I3C_MWMSG_SDR_CONTROL_END(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWMSG_SDR_CONTROL_END_SHIFT)) & I3C_MWMSG_SDR_CONTROL_END_MASK) + +#define I3C_MWMSG_SDR_CONTROL_I2C_MASK (0x400U) +#define I3C_MWMSG_SDR_CONTROL_I2C_SHIFT (10U) +/*! I2C - I2C + * 0b0..I3C message + * 0b1..I2C message + */ +#define I3C_MWMSG_SDR_CONTROL_I2C(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWMSG_SDR_CONTROL_I2C_SHIFT)) & I3C_MWMSG_SDR_CONTROL_I2C_MASK) + +#define I3C_MWMSG_SDR_CONTROL_LEN_MASK (0xF800U) +#define I3C_MWMSG_SDR_CONTROL_LEN_SHIFT (11U) +/*! LEN - Length */ +#define I3C_MWMSG_SDR_CONTROL_LEN(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWMSG_SDR_CONTROL_LEN_SHIFT)) & I3C_MWMSG_SDR_CONTROL_LEN_MASK) +/*! @} */ + +/*! @name MWMSG_SDR_DATA - Controller Write Message Data in SDR mode */ +/*! @{ */ + +#define I3C_MWMSG_SDR_DATA_DATA16B_MASK (0xFFFFU) +#define I3C_MWMSG_SDR_DATA_DATA16B_SHIFT (0U) +/*! DATA16B - Data */ +#define I3C_MWMSG_SDR_DATA_DATA16B(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWMSG_SDR_DATA_DATA16B_SHIFT)) & I3C_MWMSG_SDR_DATA_DATA16B_MASK) +/*! @} */ + +/*! @name MRMSG_SDR - Controller Read Message in SDR mode */ +/*! @{ */ + +#define I3C_MRMSG_SDR_DATA_MASK (0xFFFFU) +#define I3C_MRMSG_SDR_DATA_SHIFT (0U) +/*! DATA - Data */ +#define I3C_MRMSG_SDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << I3C_MRMSG_SDR_DATA_SHIFT)) & I3C_MRMSG_SDR_DATA_MASK) +/*! @} */ + +/*! @name MWMSG_DDR_CONTROL - Controller Write Message in DDR mode: First Control Word */ +/*! @{ */ + +#define I3C_MWMSG_DDR_CONTROL_ADDRCMD_MASK (0xFFFFU) +#define I3C_MWMSG_DDR_CONTROL_ADDRCMD_SHIFT (0U) +/*! ADDRCMD - Address Command */ +#define I3C_MWMSG_DDR_CONTROL_ADDRCMD(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWMSG_DDR_CONTROL_ADDRCMD_SHIFT)) & I3C_MWMSG_DDR_CONTROL_ADDRCMD_MASK) +/*! @} */ + +/*! @name MWMSG_DDR_CONTROL2 - Controller Write Message in DDR Mode Control 2 */ +/*! @{ */ + +#define I3C_MWMSG_DDR_CONTROL2_LEN_MASK (0x3FFU) +#define I3C_MWMSG_DDR_CONTROL2_LEN_SHIFT (0U) +/*! LEN - Length of Message */ +#define I3C_MWMSG_DDR_CONTROL2_LEN(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWMSG_DDR_CONTROL2_LEN_SHIFT)) & I3C_MWMSG_DDR_CONTROL2_LEN_MASK) + +#define I3C_MWMSG_DDR_CONTROL2_END_MASK (0x4000U) +#define I3C_MWMSG_DDR_CONTROL2_END_SHIFT (14U) +/*! END - End of Message + * 0b0..Not the end + * 0b1..End + */ +#define I3C_MWMSG_DDR_CONTROL2_END(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWMSG_DDR_CONTROL2_END_SHIFT)) & I3C_MWMSG_DDR_CONTROL2_END_MASK) +/*! @} */ + +/*! @name MWMSG_DDR_DATA - Controller Write Message Data in DDR mode */ +/*! @{ */ + +#define I3C_MWMSG_DDR_DATA_DATA16B_MASK (0xFFFFU) +#define I3C_MWMSG_DDR_DATA_DATA16B_SHIFT (0U) +/*! DATA16B - Data */ +#define I3C_MWMSG_DDR_DATA_DATA16B(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWMSG_DDR_DATA_DATA16B_SHIFT)) & I3C_MWMSG_DDR_DATA_DATA16B_MASK) +/*! @} */ + +/*! @name MRMSG_DDR - Controller Read Message in DDR mode */ +/*! @{ */ + +#define I3C_MRMSG_DDR_DATA_MASK (0xFFFFU) +#define I3C_MRMSG_DDR_DATA_SHIFT (0U) +/*! DATA - Data */ +#define I3C_MRMSG_DDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << I3C_MRMSG_DDR_DATA_SHIFT)) & I3C_MRMSG_DDR_DATA_MASK) +/*! @} */ + +/*! @name MDYNADDR - Controller Dynamic Address */ +/*! @{ */ + +#define I3C_MDYNADDR_DAVALID_MASK (0x1U) +#define I3C_MDYNADDR_DAVALID_SHIFT (0U) +/*! DAVALID - Dynamic Address Valid + * 0b0..No valid DA assigned + * 0b1..Valid DA assigned + */ +#define I3C_MDYNADDR_DAVALID(x) (((uint32_t)(((uint32_t)(x)) << I3C_MDYNADDR_DAVALID_SHIFT)) & I3C_MDYNADDR_DAVALID_MASK) + +#define I3C_MDYNADDR_DADDR_MASK (0xFEU) +#define I3C_MDYNADDR_DADDR_SHIFT (1U) +/*! DADDR - Dynamic Address */ +#define I3C_MDYNADDR_DADDR(x) (((uint32_t)(((uint32_t)(x)) << I3C_MDYNADDR_DADDR_SHIFT)) & I3C_MDYNADDR_DADDR_MASK) +/*! @} */ + +/*! @name SRSTACTTIME - Timing Rules for Target Reset Recovery */ +/*! @{ */ + +#define I3C_SRSTACTTIME_PERRSTTIM_MASK (0xFFU) +#define I3C_SRSTACTTIME_PERRSTTIM_SHIFT (0U) +/*! PERRSTTIM - Time to Recover from the I3C Peripheral */ +#define I3C_SRSTACTTIME_PERRSTTIM(x) (((uint32_t)(((uint32_t)(x)) << I3C_SRSTACTTIME_PERRSTTIM_SHIFT)) & I3C_SRSTACTTIME_PERRSTTIM_MASK) + +#define I3C_SRSTACTTIME_SYSRSTTIM_MASK (0xFF00U) +#define I3C_SRSTACTTIME_SYSRSTTIM_SHIFT (8U) +/*! SYSRSTTIM - Time to Recover from Chip Reset */ +#define I3C_SRSTACTTIME_SYSRSTTIM(x) (((uint32_t)(((uint32_t)(x)) << I3C_SRSTACTTIME_SYSRSTTIM_SHIFT)) & I3C_SRSTACTTIME_SYSRSTTIM_MASK) +/*! @} */ + +/*! @name SCCCMASK - CCC Mask for Unhandled CCCs */ +/*! @{ */ + +#define I3C_SCCCMASK_BASE_MASK (0x1U) +#define I3C_SCCCMASK_BASE_SHIFT (0U) +/*! BASE - Base + * 0b0..Suppressed + * 0b1..Passed to application + */ +#define I3C_SCCCMASK_BASE(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCCCMASK_BASE_SHIFT)) & I3C_SCCCMASK_BASE_MASK) + +#define I3C_SCCCMASK_BASEBX_MASK (0x2U) +#define I3C_SCCCMASK_BASEBX_SHIFT (1U) +/*! BASEBX - BASEBX + * 0b0..Suppressed + * 0b1..Passed to application + */ +#define I3C_SCCCMASK_BASEBX(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCCCMASK_BASEBX_SHIFT)) & I3C_SCCCMASK_BASEBX_MASK) + +#define I3C_SCCCMASK_BASEDX_MASK (0x4U) +#define I3C_SCCCMASK_BASEDX_SHIFT (2U) +/*! BASEDX - BASEDX + * 0b0..Suppressed + * 0b1..Passed to application + */ +#define I3C_SCCCMASK_BASEDX(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCCCMASK_BASEDX_SHIFT)) & I3C_SCCCMASK_BASEDX_MASK) + +#define I3C_SCCCMASK_MEXTB_MASK (0x8U) +#define I3C_SCCCMASK_MEXTB_SHIFT (3U) +/*! MEXTB - MEXTB + * 0b0..Suppressed + * 0b1..Passed to application + */ +#define I3C_SCCCMASK_MEXTB(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCCCMASK_MEXTB_SHIFT)) & I3C_SCCCMASK_MEXTB_MASK) + +#define I3C_SCCCMASK_MEXTD_MASK (0x10U) +#define I3C_SCCCMASK_MEXTD_SHIFT (4U) +/*! MEXTD - MEXTD + * 0b0..Suppressed + * 0b1..Passed to application + */ +#define I3C_SCCCMASK_MEXTD(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCCCMASK_MEXTD_SHIFT)) & I3C_SCCCMASK_MEXTD_MASK) + +#define I3C_SCCCMASK_VENDB_MASK (0x20U) +#define I3C_SCCCMASK_VENDB_SHIFT (5U) +/*! VENDB - VENDB + * 0b0..Suppressed + * 0b1..Passed to application + */ +#define I3C_SCCCMASK_VENDB(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCCCMASK_VENDB_SHIFT)) & I3C_SCCCMASK_VENDB_MASK) + +#define I3C_SCCCMASK_VENDD_MASK (0x40U) +#define I3C_SCCCMASK_VENDD_SHIFT (6U) +/*! VENDD - VENDD + * 0b0..Suppressed + * 0b1..Passed to application + */ +#define I3C_SCCCMASK_VENDD(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCCCMASK_VENDD_SHIFT)) & I3C_SCCCMASK_VENDD_MASK) +/*! @} */ + +/*! @name SERRWARNMASK - Target Errors and Warnings Mask */ +/*! @{ */ + +#define I3C_SERRWARNMASK_ORUN_MASK (0x1U) +#define I3C_SERRWARNMASK_ORUN_SHIFT (0U) +/*! ORUN - ORUN Mask + * 0b0..Deny + * 0b1..Allow + */ +#define I3C_SERRWARNMASK_ORUN(x) (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARNMASK_ORUN_SHIFT)) & I3C_SERRWARNMASK_ORUN_MASK) + +#define I3C_SERRWARNMASK_URUN_MASK (0x2U) +#define I3C_SERRWARNMASK_URUN_SHIFT (1U) +/*! URUN - URUN Mask + * 0b0..Deny + * 0b1..Allow + */ +#define I3C_SERRWARNMASK_URUN(x) (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARNMASK_URUN_SHIFT)) & I3C_SERRWARNMASK_URUN_MASK) + +#define I3C_SERRWARNMASK_URUNNACK_MASK (0x4U) +#define I3C_SERRWARNMASK_URUNNACK_SHIFT (2U) +/*! URUNNACK - URUNNACK Mask + * 0b0..Deny + * 0b1..Allow + */ +#define I3C_SERRWARNMASK_URUNNACK(x) (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARNMASK_URUNNACK_SHIFT)) & I3C_SERRWARNMASK_URUNNACK_MASK) + +#define I3C_SERRWARNMASK_TERM_MASK (0x8U) +#define I3C_SERRWARNMASK_TERM_SHIFT (3U) +/*! TERM - TERM Mask + * 0b0..Deny + * 0b1..Allow + */ +#define I3C_SERRWARNMASK_TERM(x) (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARNMASK_TERM_SHIFT)) & I3C_SERRWARNMASK_TERM_MASK) + +#define I3C_SERRWARNMASK_INVSTART_MASK (0x10U) +#define I3C_SERRWARNMASK_INVSTART_SHIFT (4U) +/*! INVSTART - INVSTART Mask + * 0b0..Deny + * 0b1..Allow + */ +#define I3C_SERRWARNMASK_INVSTART(x) (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARNMASK_INVSTART_SHIFT)) & I3C_SERRWARNMASK_INVSTART_MASK) + +#define I3C_SERRWARNMASK_SPAR_MASK (0x100U) +#define I3C_SERRWARNMASK_SPAR_SHIFT (8U) +/*! SPAR - SPAR Mask + * 0b0..Deny + * 0b1..Allow + */ +#define I3C_SERRWARNMASK_SPAR(x) (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARNMASK_SPAR_SHIFT)) & I3C_SERRWARNMASK_SPAR_MASK) + +#define I3C_SERRWARNMASK_HPAR_MASK (0x200U) +#define I3C_SERRWARNMASK_HPAR_SHIFT (9U) +/*! HPAR - HPAR Mask + * 0b0..Deny + * 0b1..Allow + */ +#define I3C_SERRWARNMASK_HPAR(x) (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARNMASK_HPAR_SHIFT)) & I3C_SERRWARNMASK_HPAR_MASK) + +#define I3C_SERRWARNMASK_HCRC_MASK (0x400U) +#define I3C_SERRWARNMASK_HCRC_SHIFT (10U) +/*! HCRC - HCRC Mask + * 0b0..Deny + * 0b1..Allow + */ +#define I3C_SERRWARNMASK_HCRC(x) (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARNMASK_HCRC_SHIFT)) & I3C_SERRWARNMASK_HCRC_MASK) + +#define I3C_SERRWARNMASK_S0S1_MASK (0x800U) +#define I3C_SERRWARNMASK_S0S1_SHIFT (11U) +/*! S0S1 - S0S1 Mask + * 0b0..Deny + * 0b1..Allow + */ +#define I3C_SERRWARNMASK_S0S1(x) (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARNMASK_S0S1_SHIFT)) & I3C_SERRWARNMASK_S0S1_MASK) +/*! @} */ + +/*! @name SMAPCTRL0 - Map Feature Control 0 */ +/*! @{ */ + +#define I3C_SMAPCTRL0_ENA_MASK (0x1U) +#define I3C_SMAPCTRL0_ENA_SHIFT (0U) +/*! ENA - Enable Primary Dynamic Address + * 0b0..Disabled + * 0b1..Enabled + */ +#define I3C_SMAPCTRL0_ENA(x) (((uint32_t)(((uint32_t)(x)) << I3C_SMAPCTRL0_ENA_SHIFT)) & I3C_SMAPCTRL0_ENA_MASK) + +#define I3C_SMAPCTRL0_DA_MASK (0xFEU) +#define I3C_SMAPCTRL0_DA_SHIFT (1U) +/*! DA - Dynamic Address */ +#define I3C_SMAPCTRL0_DA(x) (((uint32_t)(((uint32_t)(x)) << I3C_SMAPCTRL0_DA_SHIFT)) & I3C_SMAPCTRL0_DA_MASK) + +#define I3C_SMAPCTRL0_CAUSE_MASK (0x700U) +#define I3C_SMAPCTRL0_CAUSE_SHIFT (8U) +/*! CAUSE - Cause + * 0b000..No information (this value occurs when not configured to write DA) + * 0b001..Set using ENTDAA + * 0b010..Set using SETDASA, SETAASA, or SETNEWDA + * 0b011..Cleared using RSTDAA + * 0b100..Auto MAP change happened last + */ +#define I3C_SMAPCTRL0_CAUSE(x) (((uint32_t)(((uint32_t)(x)) << I3C_SMAPCTRL0_CAUSE_SHIFT)) & I3C_SMAPCTRL0_CAUSE_MASK) +/*! @} */ + +/*! @name SMAPCTRL1 - Map Feature Control 1 */ +/*! @{ */ + +#define I3C_SMAPCTRL1_ENA_MASK (0x1U) +#define I3C_SMAPCTRL1_ENA_SHIFT (0U) +/*! ENA - Enable + * 0b0..Disable + * 0b1..Enable + */ +#define I3C_SMAPCTRL1_ENA(x) (((uint32_t)(((uint32_t)(x)) << I3C_SMAPCTRL1_ENA_SHIFT)) & I3C_SMAPCTRL1_ENA_MASK) + +#define I3C_SMAPCTRL1_ADDR_MASK (0xFEU) +#define I3C_SMAPCTRL1_ADDR_SHIFT (1U) +/*! ADDR - Address */ +#define I3C_SMAPCTRL1_ADDR(x) (((uint32_t)(((uint32_t)(x)) << I3C_SMAPCTRL1_ADDR_SHIFT)) & I3C_SMAPCTRL1_ADDR_MASK) + +#define I3C_SMAPCTRL1_MAPSA_MASK (0x100U) +#define I3C_SMAPCTRL1_MAPSA_SHIFT (8U) +/*! MAPSA - MAP Static Address + * 0b0..I3C dynamic address + * 0b1..Static address (I2C style) + */ +#define I3C_SMAPCTRL1_MAPSA(x) (((uint32_t)(((uint32_t)(x)) << I3C_SMAPCTRL1_MAPSA_SHIFT)) & I3C_SMAPCTRL1_MAPSA_MASK) + +#define I3C_SMAPCTRL1_SA10B_MASK (0xE00U) +#define I3C_SMAPCTRL1_SA10B_SHIFT (9U) +/*! SA10B - Static Address 10-Bit Extension */ +#define I3C_SMAPCTRL1_SA10B(x) (((uint32_t)(((uint32_t)(x)) << I3C_SMAPCTRL1_SA10B_SHIFT)) & I3C_SMAPCTRL1_SA10B_MASK) + +#define I3C_SMAPCTRL1_NACK_MASK (0x1000U) +#define I3C_SMAPCTRL1_NACK_SHIFT (12U) +/*! NACK - Not Acknowledged + * 0b0..Do not always NACK messages + * 0b1..Always NACK messages + */ +#define I3C_SMAPCTRL1_NACK(x) (((uint32_t)(((uint32_t)(x)) << I3C_SMAPCTRL1_NACK_SHIFT)) & I3C_SMAPCTRL1_NACK_MASK) + +#define I3C_SMAPCTRL1_AUTO_MASK (0x2000U) +#define I3C_SMAPCTRL1_AUTO_SHIFT (13U) +/*! AUTO - Auto DAA + * 0b0..Disabled + * 0b1..Enabled + */ +#define I3C_SMAPCTRL1_AUTO(x) (((uint32_t)(((uint32_t)(x)) << I3C_SMAPCTRL1_AUTO_SHIFT)) & I3C_SMAPCTRL1_AUTO_MASK) + +#define I3C_SMAPCTRL1_DCR_MASK (0xFF000000U) +#define I3C_SMAPCTRL1_DCR_SHIFT (24U) +/*! DCR - DCR */ +#define I3C_SMAPCTRL1_DCR(x) (((uint32_t)(((uint32_t)(x)) << I3C_SMAPCTRL1_DCR_SHIFT)) & I3C_SMAPCTRL1_DCR_MASK) +/*! @} */ + +/*! @name IBIEXT1 - Extended IBI Data 1 */ +/*! @{ */ + +#define I3C_IBIEXT1_CNT_MASK (0x7U) +#define I3C_IBIEXT1_CNT_SHIFT (0U) +/*! CNT - Count */ +#define I3C_IBIEXT1_CNT(x) (((uint32_t)(((uint32_t)(x)) << I3C_IBIEXT1_CNT_SHIFT)) & I3C_IBIEXT1_CNT_MASK) + +#define I3C_IBIEXT1_MAX_MASK (0x70U) +#define I3C_IBIEXT1_MAX_SHIFT (4U) +/*! MAX - Maximum */ +#define I3C_IBIEXT1_MAX(x) (((uint32_t)(((uint32_t)(x)) << I3C_IBIEXT1_MAX_SHIFT)) & I3C_IBIEXT1_MAX_MASK) + +#define I3C_IBIEXT1_EXT1_MASK (0xFF00U) +#define I3C_IBIEXT1_EXT1_SHIFT (8U) +/*! EXT1 - Extra Byte 1 */ +#define I3C_IBIEXT1_EXT1(x) (((uint32_t)(((uint32_t)(x)) << I3C_IBIEXT1_EXT1_SHIFT)) & I3C_IBIEXT1_EXT1_MASK) + +#define I3C_IBIEXT1_EXT2_MASK (0xFF0000U) +#define I3C_IBIEXT1_EXT2_SHIFT (16U) +/*! EXT2 - Extra Byte 2 */ +#define I3C_IBIEXT1_EXT2(x) (((uint32_t)(((uint32_t)(x)) << I3C_IBIEXT1_EXT2_SHIFT)) & I3C_IBIEXT1_EXT2_MASK) + +#define I3C_IBIEXT1_EXT3_MASK (0xFF000000U) +#define I3C_IBIEXT1_EXT3_SHIFT (24U) +/*! EXT3 - Extra Byte 3 */ +#define I3C_IBIEXT1_EXT3(x) (((uint32_t)(((uint32_t)(x)) << I3C_IBIEXT1_EXT3_SHIFT)) & I3C_IBIEXT1_EXT3_MASK) +/*! @} */ + +/*! @name IBIEXT2 - Extended IBI Data 2 */ +/*! @{ */ + +#define I3C_IBIEXT2_EXT4_MASK (0xFFU) +#define I3C_IBIEXT2_EXT4_SHIFT (0U) +/*! EXT4 - Extra Byte 4 */ +#define I3C_IBIEXT2_EXT4(x) (((uint32_t)(((uint32_t)(x)) << I3C_IBIEXT2_EXT4_SHIFT)) & I3C_IBIEXT2_EXT4_MASK) + +#define I3C_IBIEXT2_EXT5_MASK (0xFF00U) +#define I3C_IBIEXT2_EXT5_SHIFT (8U) +/*! EXT5 - Extra Byte 5 */ +#define I3C_IBIEXT2_EXT5(x) (((uint32_t)(((uint32_t)(x)) << I3C_IBIEXT2_EXT5_SHIFT)) & I3C_IBIEXT2_EXT5_MASK) + +#define I3C_IBIEXT2_EXT6_MASK (0xFF0000U) +#define I3C_IBIEXT2_EXT6_SHIFT (16U) +/*! EXT6 - Extra Byte 6 */ +#define I3C_IBIEXT2_EXT6(x) (((uint32_t)(((uint32_t)(x)) << I3C_IBIEXT2_EXT6_SHIFT)) & I3C_IBIEXT2_EXT6_MASK) + +#define I3C_IBIEXT2_EXT7_MASK (0xFF000000U) +#define I3C_IBIEXT2_EXT7_SHIFT (24U) +/*! EXT7 - Extra Byte 7 */ +#define I3C_IBIEXT2_EXT7(x) (((uint32_t)(((uint32_t)(x)) << I3C_IBIEXT2_EXT7_SHIFT)) & I3C_IBIEXT2_EXT7_MASK) +/*! @} */ + +/*! @name SELFRESET - Self Reset */ +/*! @{ */ + +#define I3C_SELFRESET_RST_MASK (0x1U) +#define I3C_SELFRESET_RST_SHIFT (0U) +/*! RST - Reset + * 0b0..No reset + * 0b1..Reset + */ +#define I3C_SELFRESET_RST(x) (((uint32_t)(((uint32_t)(x)) << I3C_SELFRESET_RST_SHIFT)) & I3C_SELFRESET_RST_MASK) + +#define I3C_SELFRESET_KEY_MASK (0xFFFFFF00U) +#define I3C_SELFRESET_KEY_SHIFT (8U) +/*! KEY - Key */ +#define I3C_SELFRESET_KEY(x) (((uint32_t)(((uint32_t)(x)) << I3C_SELFRESET_KEY_SHIFT)) & I3C_SELFRESET_KEY_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group I3C_Register_Masks */ + + +/* I3C - Peripheral instance base addresses */ +/** Peripheral I3C1 base address */ +#define I3C1_BASE (0x44330000u) +/** Peripheral I3C1 base pointer */ +#define I3C1 ((I3C_Type *)I3C1_BASE) +/** Peripheral I3C2 base address */ +#define I3C2_BASE (0x42520000u) +/** Peripheral I3C2 base pointer */ +#define I3C2 ((I3C_Type *)I3C2_BASE) +/** Array initializer of I3C peripheral base addresses */ +#define I3C_BASE_ADDRS { 0u, I3C1_BASE, I3C2_BASE } +/** Array initializer of I3C peripheral base pointers */ +#define I3C_BASE_PTRS { (I3C_Type *)0u, I3C1, I3C2 } +/** Interrupt vectors for the I3C peripheral type */ +#define I3C_IRQS { NotAvail_IRQn, I3C1_IRQn, I3C2_IRQn } + +/*! + * @} + */ /* end of group I3C_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- IOMUXC1 Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup IOMUXC1_Peripheral_Access_Layer IOMUXC1 Peripheral Access Layer + * @{ + */ + +/** IOMUXC1 - Register Layout Typedef */ +typedef struct { + __IO uint32_t SW_MUX_CTL_PAD[108]; /**< SW_MUX_CTL_PAD_DAP_TDI SW MUX Control Register..SW_MUX_CTL_PAD_WDOG_ANY SW MUX Control Register, array offset: 0x0, array step: 0x4 */ + __IO uint32_t SW_PAD_CTL_PAD[108]; /**< SW_PAD_CTL_PAD_DAP_TDI SW PAD Control Register..SW_PAD_CTL_PAD_WDOG_ANY SW PAD Control Register, array offset: 0x1B0, array step: 0x4 */ + __IO uint32_t SELECT_INPUT[104]; /**< CAN1_IPP_IND_CANRX_SELECT_INPUT DAISY Register..USDHC3_IPP_DAT3_IN_SELECT_INPUT DAISY Register, array offset: 0x360, array step: 0x4 */ +} IOMUXC1_Type; + +/* ---------------------------------------------------------------------------- + -- IOMUXC1 Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup IOMUXC1_Register_Masks IOMUXC1 Register Masks + * @{ + */ + +/*! @name SW_MUX_CTL_PAD - SW_MUX_CTL_PAD_DAP_TDI SW MUX Control Register..SW_MUX_CTL_PAD_WDOG_ANY SW MUX Control Register */ +/*! @{ */ + +#define IOMUXC1_SW_MUX_CTL_PAD_MUX_MODE_MASK (0x7U) +#define IOMUXC1_SW_MUX_CTL_PAD_MUX_MODE_SHIFT (0U) +/*! MUX_MODE - MUX Mode Select Field. + * 0b000..Select mux mode: ALT0 mux port: GPIO2_IO14 of instance: gpio2 + * 0b001..Select mux mode: ALT1 mux port: LPUART3_TX of instance: lpuart3 + * 0b010..Select mux mode: ALT2 mux port: MEDIAMIX_CAM_DATA06 of instance: mediamix + * 0b011..Select mux mode: ALT3 mux port: MEDIAMIX_DISP_DATA10 of instance: mediamix + * 0b100..Select mux mode: ALT4 mux port: LPSPI8_SOUT of instance: lpspi8 + * 0b101..Select mux mode: ALT5 mux port: LPUART8_CTS_B of instance: lpuart8 + * 0b110..Select mux mode: ALT6 mux port: LPUART4_TX of instance: lpuart4 + * 0b111..Select mux mode: ALT7 mux port: FLEXIO1_FLEXIO14 of instance: flexio1 + */ +#define IOMUXC1_SW_MUX_CTL_PAD_MUX_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC1_SW_MUX_CTL_PAD_MUX_MODE_SHIFT)) & IOMUXC1_SW_MUX_CTL_PAD_MUX_MODE_MASK) + +#define IOMUXC1_SW_MUX_CTL_PAD_SION_MASK (0x10U) +#define IOMUXC1_SW_MUX_CTL_PAD_SION_SHIFT (4U) +/*! SION - Software Input On Field. + * 0b0..Input Path is determined by functionality + * 0b1..Force input path of pad DAP_TDO_TRACESWO + */ +#define IOMUXC1_SW_MUX_CTL_PAD_SION(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC1_SW_MUX_CTL_PAD_SION_SHIFT)) & IOMUXC1_SW_MUX_CTL_PAD_SION_MASK) +/*! @} */ + +/* The count of IOMUXC1_SW_MUX_CTL_PAD */ +#define IOMUXC1_SW_MUX_CTL_PAD_COUNT (108U) + +/*! @name SW_PAD_CTL_PAD - SW_PAD_CTL_PAD_DAP_TDI SW PAD Control Register..SW_PAD_CTL_PAD_WDOG_ANY SW PAD Control Register */ +/*! @{ */ + +#define IOMUXC1_SW_PAD_CTL_PAD_DSE_MASK (0x7EU) +#define IOMUXC1_SW_PAD_CTL_PAD_DSE_SHIFT (1U) +/*! DSE - Drive Strength Field + * 0b000000.. + * 0b000001.. + * 0b000010.. + * 0b000011.. + * 0b000100.. + * 0b000101.. + * 0b000110.. + * 0b000111.. + * 0b001000.. + * 0b001001.. + * 0b001010.. + * 0b001011.. + * 0b001100.. + * 0b001101.. + * 0b001110.. + * 0b001111.. + * 0b010000.. + * 0b010001.. + * 0b010010.. + * 0b010011.. + * 0b010100.. + * 0b010101.. + * 0b010110.. + * 0b010111.. + * 0b011000.. + * 0b011001.. + * 0b011010.. + * 0b011011.. + * 0b011100.. + * 0b011101.. + * 0b011110.. + * 0b011111.. + * 0b100000.. + * 0b100001.. + * 0b100010.. + * 0b100011.. + * 0b100100.. + * 0b100101.. + * 0b100110.. + * 0b100111.. + * 0b101000.. + * 0b101001.. + * 0b101010.. + * 0b101011.. + * 0b101100.. + * 0b101101.. + * 0b101110.. + * 0b101111.. + * 0b110000.. + * 0b110001.. + * 0b110010.. + * 0b110011.. + * 0b110100.. + * 0b110101.. + * 0b110110.. + * 0b110111.. + * 0b111000.. + * 0b111001.. + * 0b111010.. + * 0b111011.. + * 0b111100.. + * 0b111101.. + * 0b111110.. + * 0b111111..X6 + */ +#define IOMUXC1_SW_PAD_CTL_PAD_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC1_SW_PAD_CTL_PAD_DSE_SHIFT)) & IOMUXC1_SW_PAD_CTL_PAD_DSE_MASK) + +#define IOMUXC1_SW_PAD_CTL_PAD_FSEL1_MASK (0x180U) +#define IOMUXC1_SW_PAD_CTL_PAD_FSEL1_SHIFT (7U) +/*! FSEL1 - Slew Rate Field + * 0b00.. + * 0b01.. + * 0b10..Slight Fast Slew Rate + * 0b11..Fast Slew Rate + */ +#define IOMUXC1_SW_PAD_CTL_PAD_FSEL1(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC1_SW_PAD_CTL_PAD_FSEL1_SHIFT)) & IOMUXC1_SW_PAD_CTL_PAD_FSEL1_MASK) + +#define IOMUXC1_SW_PAD_CTL_PAD_PU_MASK (0x200U) +#define IOMUXC1_SW_PAD_CTL_PAD_PU_SHIFT (9U) +/*! PU - Pull Up Field + * 0b0..No pull up + * 0b1..Pull up + */ +#define IOMUXC1_SW_PAD_CTL_PAD_PU(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC1_SW_PAD_CTL_PAD_PU_SHIFT)) & IOMUXC1_SW_PAD_CTL_PAD_PU_MASK) + +#define IOMUXC1_SW_PAD_CTL_PAD_PD_MASK (0x400U) +#define IOMUXC1_SW_PAD_CTL_PAD_PD_SHIFT (10U) +/*! PD - Pull Down Field + * 0b0..Not pull down + * 0b1..Pull down + */ +#define IOMUXC1_SW_PAD_CTL_PAD_PD(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC1_SW_PAD_CTL_PAD_PD_SHIFT)) & IOMUXC1_SW_PAD_CTL_PAD_PD_MASK) + +#define IOMUXC1_SW_PAD_CTL_PAD_OD_MASK (0x800U) +#define IOMUXC1_SW_PAD_CTL_PAD_OD_SHIFT (11U) +/*! OD - Open Drain Field + * 0b0..Open Drain Disable + * 0b1..Open Drain Enable + */ +#define IOMUXC1_SW_PAD_CTL_PAD_OD(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC1_SW_PAD_CTL_PAD_OD_SHIFT)) & IOMUXC1_SW_PAD_CTL_PAD_OD_MASK) + +#define IOMUXC1_SW_PAD_CTL_PAD_HYS_MASK (0x1000U) +#define IOMUXC1_SW_PAD_CTL_PAD_HYS_SHIFT (12U) +/*! HYS - Schmitt trigger Field + * 0b0..No Schmitt input + * 0b1..Schmitt input + */ +#define IOMUXC1_SW_PAD_CTL_PAD_HYS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC1_SW_PAD_CTL_PAD_HYS_SHIFT)) & IOMUXC1_SW_PAD_CTL_PAD_HYS_MASK) + +#define IOMUXC1_SW_PAD_CTL_PAD_APC_MASK (0xFF000000U) +#define IOMUXC1_SW_PAD_CTL_PAD_APC_SHIFT (24U) +/*! APC - Domain Access Field + * 0b00000000.. + * 0b00000001.. + * 0b00000010.. + * 0b00000011.. + * 0b00000100.. + * 0b00000101.. + * 0b00000110.. + * 0b00000111.. + * 0b00001000.. + * 0b00001001.. + * 0b00001010.. + * 0b00001011.. + * 0b00001100.. + * 0b00001101.. + * 0b00001110.. + * 0b00001111.. + * 0b00010000.. + * 0b00010001.. + * 0b00010010.. + * 0b00010011.. + * 0b00010100.. + * 0b00010101.. + * 0b00010110.. + * 0b00010111.. + * 0b00011000.. + * 0b00011001.. + * 0b00011010.. + * 0b00011011.. + * 0b00011100.. + * 0b00011101.. + * 0b00011110.. + * 0b00011111.. + * 0b00100000.. + * 0b00100001.. + * 0b00100010.. + * 0b00100011.. + * 0b00100100.. + * 0b00100101.. + * 0b00100110.. + * 0b00100111.. + * 0b00101000.. + * 0b00101001.. + * 0b00101010.. + * 0b00101011.. + * 0b00101100.. + * 0b00101101.. + * 0b00101110.. + * 0b00101111.. + * 0b00110000.. + * 0b00110001.. + * 0b00110010.. + * 0b00110011.. + * 0b00110100.. + * 0b00110101.. + * 0b00110110.. + * 0b00110111.. + * 0b00111000.. + * 0b00111001.. + * 0b00111010.. + * 0b00111011.. + * 0b00111100.. + * 0b00111101.. + * 0b00111110.. + * 0b00111111.. + * 0b01000000.. + * 0b01000001.. + * 0b01000010.. + * 0b01000011.. + * 0b01000100.. + * 0b01000101.. + * 0b01000110.. + * 0b01000111.. + * 0b01001000.. + * 0b01001001.. + * 0b01001010.. + * 0b01001011.. + * 0b01001100.. + * 0b01001101.. + * 0b01001110.. + * 0b01001111.. + * 0b01010000.. + * 0b01010001.. + * 0b01010010.. + * 0b01010011.. + * 0b01010100.. + * 0b01010101.. + * 0b01010110.. + * 0b01010111.. + * 0b01011000.. + * 0b01011001.. + * 0b01011010.. + * 0b01011011.. + * 0b01011100.. + * 0b01011101.. + * 0b01011110.. + * 0b01011111.. + * 0b01100000.. + * 0b01100001.. + * 0b01100010.. + * 0b01100011.. + * 0b01100100.. + * 0b01100101.. + * 0b01100110.. + * 0b01100111.. + * 0b01101000.. + * 0b01101001.. + * 0b01101010.. + * 0b01101011.. + * 0b01101100.. + * 0b01101101.. + * 0b01101110.. + * 0b01101111.. + * 0b01110000.. + * 0b01110001.. + * 0b01110010.. + * 0b01110011.. + * 0b01110100.. + * 0b01110101.. + * 0b01110110.. + * 0b01110111.. + * 0b01111000.. + * 0b01111001.. + * 0b01111010.. + * 0b01111011.. + * 0b01111100.. + * 0b01111101.. + * 0b01111110.. + * 0b01111111.. + * 0b10000000.. + * 0b10000001.. + * 0b10000010.. + * 0b10000011.. + * 0b10000100.. + * 0b10000101.. + * 0b10000110.. + * 0b10000111.. + * 0b10001000.. + * 0b10001001.. + * 0b10001010.. + * 0b10001011.. + * 0b10001100.. + * 0b10001101.. + * 0b10001110.. + * 0b10001111.. + * 0b10010000.. + * 0b10010001.. + * 0b10010010.. + * 0b10010011.. + * 0b10010100.. + * 0b10010101.. + * 0b10010110.. + * 0b10010111.. + * 0b10011000.. + * 0b10011001.. + * 0b10011010.. + * 0b10011011.. + * 0b10011100.. + * 0b10011101.. + * 0b10011110.. + * 0b10011111.. + * 0b10100000.. + * 0b10100001.. + * 0b10100010.. + * 0b10100011.. + * 0b10100100.. + * 0b10100101.. + * 0b10100110.. + * 0b10100111.. + * 0b10101000.. + * 0b10101001.. + * 0b10101010.. + * 0b10101011.. + * 0b10101100.. + * 0b10101101.. + * 0b10101110.. + * 0b10101111.. + * 0b10110000.. + * 0b10110001.. + * 0b10110010.. + * 0b10110011.. + * 0b10110100.. + * 0b10110101.. + * 0b10110110.. + * 0b10110111.. + * 0b10111000.. + * 0b10111001.. + * 0b10111010.. + * 0b10111011.. + * 0b10111100.. + * 0b10111101.. + * 0b10111110.. + * 0b10111111.. + * 0b11000000.. + * 0b11000001.. + * 0b11000010.. + * 0b11000011.. + * 0b11000100.. + * 0b11000101.. + * 0b11000110.. + * 0b11000111.. + * 0b11001000.. + * 0b11001001.. + * 0b11001010.. + * 0b11001011.. + * 0b11001100.. + * 0b11001101.. + * 0b11001110.. + * 0b11001111.. + * 0b11010000.. + * 0b11010001.. + * 0b11010010.. + * 0b11010011.. + * 0b11010100.. + * 0b11010101.. + * 0b11010110.. + * 0b11010111.. + * 0b11011000.. + * 0b11011001.. + * 0b11011010.. + * 0b11011011.. + * 0b11011100.. + * 0b11011101.. + * 0b11011110.. + * 0b11011111.. + * 0b11100000.. + * 0b11100001.. + * 0b11100010.. + * 0b11100011.. + * 0b11100100.. + * 0b11100101.. + * 0b11100110.. + * 0b11100111.. + * 0b11101000.. + * 0b11101001.. + * 0b11101010.. + * 0b11101011.. + * 0b11101100.. + * 0b11101101.. + * 0b11101110.. + * 0b11101111.. + * 0b11110000.. + * 0b11110001.. + * 0b11110010.. + * 0b11110011.. + * 0b11110100.. + * 0b11110101.. + * 0b11110110.. + * 0b11110111.. + * 0b11111000.. + * 0b11111001.. + * 0b11111010.. + * 0b11111011.. + * 0b11111100.. + * 0b11111101.. + * 0b11111110.. + * 0b11111111.. + */ +#define IOMUXC1_SW_PAD_CTL_PAD_APC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC1_SW_PAD_CTL_PAD_APC_SHIFT)) & IOMUXC1_SW_PAD_CTL_PAD_APC_MASK) +/*! @} */ + +/* The count of IOMUXC1_SW_PAD_CTL_PAD */ +#define IOMUXC1_SW_PAD_CTL_PAD_COUNT (108U) + +/*! @name SELECT_INPUT - CAN1_IPP_IND_CANRX_SELECT_INPUT DAISY Register..USDHC3_IPP_DAT3_IN_SELECT_INPUT DAISY Register */ +/*! @{ */ + +#define IOMUXC1_SELECT_INPUT_DAISY_MASK (0x3U) /* Merged from fields with different position or width, of widths (1, 2), largest definition used */ +#define IOMUXC1_SELECT_INPUT_DAISY_SHIFT (0U) +/*! DAISY - Selecting Pads Involved in Daisy Chain. + * 0b00..Selecting Pad: DAP_TDO_TRACESWO for Mode: ALT3 + * 0b01..Selecting Pad: GPIO_IO27 for Mode: ALT2 + * 0b10..Selecting Pad: ENET1_TD2 for Mode: ALT2 + * 0b11..Selecting Pad: SD2_DATA1 for Mode: ALT2 + */ +#define IOMUXC1_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC1_SELECT_INPUT_DAISY_SHIFT)) & IOMUXC1_SELECT_INPUT_DAISY_MASK) /* Merged from fields with different position or width, of widths (1, 2), largest definition used */ +/*! @} */ + +/* The count of IOMUXC1_SELECT_INPUT */ +#define IOMUXC1_SELECT_INPUT_COUNT (104U) + + +/*! + * @} + */ /* end of group IOMUXC1_Register_Masks */ + + +/* IOMUXC1 - Peripheral instance base addresses */ +/** Peripheral IOMUXC1 base address */ +#define IOMUXC1_BASE (0x443C0000u) +/** Peripheral IOMUXC1 base pointer */ +#define IOMUXC1 ((IOMUXC1_Type *)IOMUXC1_BASE) +/** Array initializer of IOMUXC1 peripheral base addresses */ +#define IOMUXC1_BASE_ADDRS { IOMUXC1_BASE } +/** Array initializer of IOMUXC1 peripheral base pointers */ +#define IOMUXC1_BASE_PTRS { IOMUXC1 } + +/*! + * @} + */ /* end of group IOMUXC1_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- IOMUXC_GPR Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup IOMUXC_GPR_Peripheral_Access_Layer IOMUXC_GPR Peripheral Access Layer + * @{ + */ + +/** IOMUXC_GPR - Register Layout Typedef */ +typedef struct { + __IO uint32_t CONFIG; /**< IOMUXC GPR Configuration, offset: 0x0 */ +} IOMUXC_GPR_Type; + +/* ---------------------------------------------------------------------------- + -- IOMUXC_GPR Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup IOMUXC_GPR_Register_Masks IOMUXC_GPR Register Masks + * @{ + */ + +/*! @name CONFIG - IOMUXC GPR Configuration */ +/*! @{ */ + +#define IOMUXC_GPR_CONFIG_MASTERID0_DATA_MASK (0xFU) +#define IOMUXC_GPR_CONFIG_MASTERID0_DATA_SHIFT (0U) +/*! MASTERID0_DATA - Data bits */ +#define IOMUXC_GPR_CONFIG_MASTERID0_DATA(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_CONFIG_MASTERID0_DATA_SHIFT)) & IOMUXC_GPR_CONFIG_MASTERID0_DATA_MASK) + +#define IOMUXC_GPR_CONFIG_MASTERID1_DATA_MASK (0xF0U) +#define IOMUXC_GPR_CONFIG_MASTERID1_DATA_SHIFT (4U) +/*! MASTERID1_DATA - Data bits */ +#define IOMUXC_GPR_CONFIG_MASTERID1_DATA(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_CONFIG_MASTERID1_DATA_SHIFT)) & IOMUXC_GPR_CONFIG_MASTERID1_DATA_MASK) + +#define IOMUXC_GPR_CONFIG_MASTERID2_DATA_MASK (0xF00U) +#define IOMUXC_GPR_CONFIG_MASTERID2_DATA_SHIFT (8U) +/*! MASTERID2_DATA - Data bits */ +#define IOMUXC_GPR_CONFIG_MASTERID2_DATA(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_CONFIG_MASTERID2_DATA_SHIFT)) & IOMUXC_GPR_CONFIG_MASTERID2_DATA_MASK) + +#define IOMUXC_GPR_CONFIG_MASTERID0_LOCK_MASK (0xF0000U) +#define IOMUXC_GPR_CONFIG_MASTERID0_LOCK_SHIFT (16U) +/*! MASTERID0_LOCK - Lock bits */ +#define IOMUXC_GPR_CONFIG_MASTERID0_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_CONFIG_MASTERID0_LOCK_SHIFT)) & IOMUXC_GPR_CONFIG_MASTERID0_LOCK_MASK) + +#define IOMUXC_GPR_CONFIG_MASTERID1_LOCK_MASK (0xF00000U) +#define IOMUXC_GPR_CONFIG_MASTERID1_LOCK_SHIFT (20U) +/*! MASTERID1_LOCK - Lock bits */ +#define IOMUXC_GPR_CONFIG_MASTERID1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_CONFIG_MASTERID1_LOCK_SHIFT)) & IOMUXC_GPR_CONFIG_MASTERID1_LOCK_MASK) + +#define IOMUXC_GPR_CONFIG_MASTERID2_LOCK_MASK (0xF000000U) +#define IOMUXC_GPR_CONFIG_MASTERID2_LOCK_SHIFT (24U) +/*! MASTERID2_LOCK - Lock bits */ +#define IOMUXC_GPR_CONFIG_MASTERID2_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_CONFIG_MASTERID2_LOCK_SHIFT)) & IOMUXC_GPR_CONFIG_MASTERID2_LOCK_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group IOMUXC_GPR_Register_Masks */ + + +/* IOMUXC_GPR - Peripheral instance base addresses */ +/** Peripheral IOMUXC_GPR base address */ +#define IOMUXC_GPR_BASE (0x443D0000u) +/** Peripheral IOMUXC_GPR base pointer */ +#define IOMUXC_GPR ((IOMUXC_GPR_Type *)IOMUXC_GPR_BASE) +/** Array initializer of IOMUXC_GPR peripheral base addresses */ +#define IOMUXC_GPR_BASE_ADDRS { IOMUXC_GPR_BASE } +/** Array initializer of IOMUXC_GPR peripheral base pointers */ +#define IOMUXC_GPR_BASE_PTRS { IOMUXC_GPR } + +/*! + * @} + */ /* end of group IOMUXC_GPR_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- ISI Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ISI_Peripheral_Access_Layer ISI Peripheral Access Layer + * @{ + */ + +/** ISI - Register Layout Typedef */ +typedef struct { + __IO uint32_t CHNL_CTRL; /**< Channel Control, offset: 0x0 */ + __IO uint32_t CHNL_IMG_CTRL; /**< Channel Image Control, offset: 0x4 */ + __IO uint32_t CHNL_OUT_BUF_CTRL; /**< Channel Output Buffer Control, offset: 0x8 */ + __IO uint32_t CHNL_IMG_CFG; /**< Channel Image Configuration, offset: 0xC */ + __IO uint32_t CHNL_IER; /**< Channel Interrupt Enable, offset: 0x10 */ + __IO uint32_t CHNL_STS; /**< Channel Status, offset: 0x14 */ + __IO uint32_t CHNL_SCALE_FACTOR; /**< Channel Scale Factor, offset: 0x18 */ + __IO uint32_t CHNL_SCALE_OFFSET; /**< Channel Scale Offset, offset: 0x1C */ + __IO uint32_t CHNL_CROP_ULC; /**< Channel Crop Upper Left Corner Coordinate, offset: 0x20 */ + __IO uint32_t CHNL_CROP_LRC; /**< Channel Crop Lower Right Corner Coordinate, offset: 0x24 */ + __IO uint32_t CHNL_CSC_COEFF0; /**< Channel Color Space Conversion Coefficient 0, offset: 0x28 */ + __IO uint32_t CHNL_CSC_COEFF1; /**< Channel Color Space Conversion Coefficient 1, offset: 0x2C */ + __IO uint32_t CHNL_CSC_COEFF2; /**< Channel Color Space Conversion Coefficient 2, offset: 0x30 */ + __IO uint32_t CHNL_CSC_COEFF3; /**< Channel Color Space Conversion Coefficient 3, offset: 0x34 */ + __IO uint32_t CHNL_CSC_COEFF4; /**< Channel Color Space Conversion Coefficient 4, offset: 0x38 */ + __IO uint32_t CHNL_CSC_COEFF5; /**< Channel Color Space Conversion Coefficient 5, offset: 0x3C */ + __IO uint32_t CHNL_ROI_0_ALPHA; /**< Channel Alpha Value for ROI 0, offset: 0x40 */ + __IO uint32_t CHNL_ROI_0_ULC; /**< Channel Upper Left Coordinate for ROI 0, offset: 0x44 */ + __IO uint32_t CHNL_ROI_0_LRC; /**< Channel Lower Right Coordinate for ROI 0, offset: 0x48 */ + __IO uint32_t CHNL_ROI_1_ALPHA; /**< Channel Alpha Value for ROI 1, offset: 0x4C */ + __IO uint32_t CHNL_ROI_1_ULC; /**< Channel Upper Left Coordinate for ROI 1, offset: 0x50 */ + __IO uint32_t CHNL_ROI_1_LRC; /**< Channel Lower Right Coordinate for ROI 1, offset: 0x54 */ + __IO uint32_t CHNL_ROI_2_ALPHA; /**< Channel Alpha Value for ROI 2, offset: 0x58 */ + __IO uint32_t CHNL_ROI_2_ULC; /**< Channel Upper Left Coordinate for ROI 2, offset: 0x5C */ + __IO uint32_t CHNL_ROI_2_LRC; /**< Channel Lower Right Coordinate for ROI 2, offset: 0x60 */ + __IO uint32_t CHNL_ROI_3_ALPHA; /**< Channel Alpha Value for ROI 3, offset: 0x64 */ + __IO uint32_t CHNL_ROI_3_ULC; /**< Channel Upper Left Coordinate for ROI 3, offset: 0x68 */ + __IO uint32_t CHNL_ROI_3_LRC; /**< Channel Lower Right Coordinate for ROI 3, offset: 0x6C */ + __IO uint32_t CHNL_OUT_BUF1_ADDR_Y; /**< Channel RGB or Luma (Y) Output Buffer 1 Address, offset: 0x70 */ + __IO uint32_t CHNL_OUT_BUF1_ADDR_U; /**< Channel Chroma (U/Cb/UV/CbCr) Output Buffer 1 Address, offset: 0x74 */ + __IO uint32_t CHNL_OUT_BUF1_ADDR_V; /**< Channel Chroma (V/Cr) Output Buffer 1 Address, offset: 0x78 */ + __IO uint32_t CHNL_OUT_BUF_PITCH; /**< Channel Output Buffer Pitch, offset: 0x7C */ + uint8_t RESERVED_0[4]; + __IO uint32_t CHNL_IN_BUF_PITCH; /**< Channel Input Buffer Pitch, offset: 0x84 */ + __IO uint32_t CHNL_MEM_RD_CTRL; /**< Channel Memory Read Control, offset: 0x88 */ + __IO uint32_t CHNL_OUT_BUF2_ADDR_Y; /**< Channel RGB or Luma (Y) Output Buffer 2 Address, offset: 0x8C */ + __IO uint32_t CHNL_OUT_BUF2_ADDR_U; /**< Channel Chroma (U/Cb/UV/CbCr) Output Buffer 2 Address, offset: 0x90 */ + __IO uint32_t CHNL_OUT_BUF2_ADDR_V; /**< Channel Chroma (V/Cr) Output Buffer 2 Address, offset: 0x94 */ + __IO uint32_t CHNL_SCL_IMG_CFG; /**< Channel Scaled Image Configuration, offset: 0x98 */ + __IO uint32_t CHNL_FLOW_CTRL; /**< Channel Flow Control, offset: 0x9C */ +} ISI_Type; + +/* ---------------------------------------------------------------------------- + -- ISI Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ISI_Register_Masks ISI Register Masks + * @{ + */ + +/*! @name CHNL_CTRL - Channel Control */ +/*! @{ */ + +#define ISI_CHNL_CTRL_SRC_MASK (0x1U) +#define ISI_CHNL_CTRL_SRC_SHIFT (0U) +/*! SRC - Input Image Source Port Selection + * 0b0..Port 0 + * 0b1..Port 1 + */ +#define ISI_CHNL_CTRL_SRC(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CTRL_SRC_SHIFT)) & ISI_CHNL_CTRL_SRC_MASK) + +#define ISI_CHNL_CTRL_SRC_TYPE_MASK (0x10U) +#define ISI_CHNL_CTRL_SRC_TYPE_SHIFT (4U) +/*! SRC_TYPE - Type of Selected Input Image Source + * 0b0..Pixel link + * 0b1..Memory + */ +#define ISI_CHNL_CTRL_SRC_TYPE(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CTRL_SRC_TYPE_SHIFT)) & ISI_CHNL_CTRL_SRC_TYPE_MASK) + +#define ISI_CHNL_CTRL_VER_ID_MASK (0x3C0000U) +#define ISI_CHNL_CTRL_VER_ID_SHIFT (18U) +/*! VER_ID - Version ID */ +#define ISI_CHNL_CTRL_VER_ID(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CTRL_VER_ID_SHIFT)) & ISI_CHNL_CTRL_VER_ID_MASK) + +#define ISI_CHNL_CTRL_RAW_MSB_ALIGN_MASK (0x400000U) +#define ISI_CHNL_CTRL_RAW_MSB_ALIGN_SHIFT (22U) +/*! RAW_MSB_ALIGN - RAW to MSB Align + * 0b0..LSB aligned selection + * 0b1..MSB aligned selection + */ +#define ISI_CHNL_CTRL_RAW_MSB_ALIGN(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CTRL_RAW_MSB_ALIGN_SHIFT)) & ISI_CHNL_CTRL_RAW_MSB_ALIGN_MASK) + +#define ISI_CHNL_CTRL_SW_RST_MASK (0x1000000U) +#define ISI_CHNL_CTRL_SW_RST_SHIFT (24U) +/*! SW_RST - Software Reset + * 0b0..No reset + * 0b1..Software reset + */ +#define ISI_CHNL_CTRL_SW_RST(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CTRL_SW_RST_SHIFT)) & ISI_CHNL_CTRL_SW_RST_MASK) + +#define ISI_CHNL_CTRL_CHNL_BYPASS_MASK (0x20000000U) +#define ISI_CHNL_CTRL_CHNL_BYPASS_SHIFT (29U) +/*! CHNL_BYPASS - Channel Bypass Enable + * 0b0..Disable + * 0b1..Enable + */ +#define ISI_CHNL_CTRL_CHNL_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CTRL_CHNL_BYPASS_SHIFT)) & ISI_CHNL_CTRL_CHNL_BYPASS_MASK) + +#define ISI_CHNL_CTRL_CLK_EN_MASK (0x40000000U) +#define ISI_CHNL_CTRL_CLK_EN_SHIFT (30U) +/*! CLK_EN - Channel Clock Enable + * 0b0..Disable + * 0b1..Enable + */ +#define ISI_CHNL_CTRL_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CTRL_CLK_EN_SHIFT)) & ISI_CHNL_CTRL_CLK_EN_MASK) + +#define ISI_CHNL_CTRL_CHNL_EN_MASK (0x80000000U) +#define ISI_CHNL_CTRL_CHNL_EN_SHIFT (31U) +/*! CHNL_EN - Enable Channel Processing + * 0b0..Disable + * 0b1..Enable + */ +#define ISI_CHNL_CTRL_CHNL_EN(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CTRL_CHNL_EN_SHIFT)) & ISI_CHNL_CTRL_CHNL_EN_MASK) +/*! @} */ + +/*! @name CHNL_IMG_CTRL - Channel Image Control */ +/*! @{ */ + +#define ISI_CHNL_IMG_CTRL_CSC_BYP_MASK (0x1U) +#define ISI_CHNL_IMG_CTRL_CSC_BYP_SHIFT (0U) +/*! CSC_BYP - Color Space Conversion Bypass Control + * 0b0..CSC operational + * 0b1..CSC bypassed + */ +#define ISI_CHNL_IMG_CTRL_CSC_BYP(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IMG_CTRL_CSC_BYP_SHIFT)) & ISI_CHNL_IMG_CTRL_CSC_BYP_MASK) + +#define ISI_CHNL_IMG_CTRL_CSC_MODE_MASK (0x6U) +#define ISI_CHNL_IMG_CTRL_CSC_MODE_SHIFT (1U) +/*! CSC_MODE - Color Space Conversion Operating Mode + * 0b00..Convert from YUV to RGB + * 0b01..Convert from YCbCr to RGB + * 0b10..Convert from RGB to YUV + * 0b11..Convert from RGB to YCbCr + */ +#define ISI_CHNL_IMG_CTRL_CSC_MODE(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IMG_CTRL_CSC_MODE_SHIFT)) & ISI_CHNL_IMG_CTRL_CSC_MODE_MASK) + +#define ISI_CHNL_IMG_CTRL_YCBCR_MODE_MASK (0x8U) +#define ISI_CHNL_IMG_CTRL_YCBCR_MODE_SHIFT (3U) +/*! YCBCR_MODE - YCbCr Mode + * 0b0..Disable + * 0b1..Enable + */ +#define ISI_CHNL_IMG_CTRL_YCBCR_MODE(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IMG_CTRL_YCBCR_MODE_SHIFT)) & ISI_CHNL_IMG_CTRL_YCBCR_MODE_MASK) + +#define ISI_CHNL_IMG_CTRL_HFLIP_EN_MASK (0x20U) +#define ISI_CHNL_IMG_CTRL_HFLIP_EN_SHIFT (5U) +/*! HFLIP_EN - Horizontal Flip Control + * 0b0..Disable + * 0b1..Enable + */ +#define ISI_CHNL_IMG_CTRL_HFLIP_EN(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IMG_CTRL_HFLIP_EN_SHIFT)) & ISI_CHNL_IMG_CTRL_HFLIP_EN_MASK) + +#define ISI_CHNL_IMG_CTRL_VFLIP_EN_MASK (0x40U) +#define ISI_CHNL_IMG_CTRL_VFLIP_EN_SHIFT (6U) +/*! VFLIP_EN - Vertical Flip Control + * 0b0..Disable + * 0b1..Enable + */ +#define ISI_CHNL_IMG_CTRL_VFLIP_EN(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IMG_CTRL_VFLIP_EN_SHIFT)) & ISI_CHNL_IMG_CTRL_VFLIP_EN_MASK) + +#define ISI_CHNL_IMG_CTRL_CROP_EN_MASK (0x80U) +#define ISI_CHNL_IMG_CTRL_CROP_EN_SHIFT (7U) +/*! CROP_EN - Output Image Cropping Enable + * 0b0..Disable + * 0b1..Enable + */ +#define ISI_CHNL_IMG_CTRL_CROP_EN(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IMG_CTRL_CROP_EN_SHIFT)) & ISI_CHNL_IMG_CTRL_CROP_EN_MASK) + +#define ISI_CHNL_IMG_CTRL_DEC_Y_MASK (0x300U) +#define ISI_CHNL_IMG_CTRL_DEC_Y_SHIFT (8U) +/*! DEC_Y - Vertical Pre-Decimation Control + * 0b00..Disabled + * 0b01..Decimate by 2 + * 0b10..Decimate by 4 + * 0b11..Decimate by 8 + */ +#define ISI_CHNL_IMG_CTRL_DEC_Y(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IMG_CTRL_DEC_Y_SHIFT)) & ISI_CHNL_IMG_CTRL_DEC_Y_MASK) + +#define ISI_CHNL_IMG_CTRL_DEC_X_MASK (0xC00U) +#define ISI_CHNL_IMG_CTRL_DEC_X_SHIFT (10U) +/*! DEC_X - Horizontal Pre-Decimation Control + * 0b00..Disabled + * 0b01..Decimate by 2 + * 0b10..Decimate by 4 + * 0b11..Decimate by 8 + */ +#define ISI_CHNL_IMG_CTRL_DEC_X(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IMG_CTRL_DEC_X_SHIFT)) & ISI_CHNL_IMG_CTRL_DEC_X_MASK) + +#define ISI_CHNL_IMG_CTRL_DEINT_MASK (0x7000U) +#define ISI_CHNL_IMG_CTRL_DEINT_SHIFT (12U) +/*! DEINT - Deinterlace Control + * 0b000, 0b001..No deinterlacing + * 0b010..Weave deinterlacing (odd, even) + * 0b011..Weave deinterlacing (even, odd) + */ +#define ISI_CHNL_IMG_CTRL_DEINT(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IMG_CTRL_DEINT_SHIFT)) & ISI_CHNL_IMG_CTRL_DEINT_MASK) + +#define ISI_CHNL_IMG_CTRL_GBL_ALPHA_EN_MASK (0x8000U) +#define ISI_CHNL_IMG_CTRL_GBL_ALPHA_EN_SHIFT (15U) +/*! GBL_ALPHA_EN - Global Alpha Value Insertion Enable + * 0b0..Disable + * 0b1..Enable + */ +#define ISI_CHNL_IMG_CTRL_GBL_ALPHA_EN(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IMG_CTRL_GBL_ALPHA_EN_SHIFT)) & ISI_CHNL_IMG_CTRL_GBL_ALPHA_EN_MASK) + +#define ISI_CHNL_IMG_CTRL_GBL_ALPHA_VAL_MASK (0xFF0000U) +#define ISI_CHNL_IMG_CTRL_GBL_ALPHA_VAL_SHIFT (16U) +/*! GBL_ALPHA_VAL - Global Alpha Value + * 0b00000000-0b11111111..Alpha value to be inserted with all RGB pixels + */ +#define ISI_CHNL_IMG_CTRL_GBL_ALPHA_VAL(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IMG_CTRL_GBL_ALPHA_VAL_SHIFT)) & ISI_CHNL_IMG_CTRL_GBL_ALPHA_VAL_MASK) + +#define ISI_CHNL_IMG_CTRL_FORMAT_MASK (0x7F000000U) +#define ISI_CHNL_IMG_CTRL_FORMAT_SHIFT (24U) +/*! FORMAT - Output Image Format + * 0b0000000-0b1000001..See . + */ +#define ISI_CHNL_IMG_CTRL_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IMG_CTRL_FORMAT_SHIFT)) & ISI_CHNL_IMG_CTRL_FORMAT_MASK) +/*! @} */ + +/*! @name CHNL_OUT_BUF_CTRL - Channel Output Buffer Control */ +/*! @{ */ + +#define ISI_CHNL_OUT_BUF_CTRL_PANIC_SET_THD_Y_MASK (0xFU) +#define ISI_CHNL_OUT_BUF_CTRL_PANIC_SET_THD_Y_SHIFT (0U) +/*! PANIC_SET_THD_Y - Overflow Panic Set Threshold Value for Y or RGB Output Buffer + * 0b0000..No panic alert + * 0b0001-0b1111..Panic asserts + */ +#define ISI_CHNL_OUT_BUF_CTRL_PANIC_SET_THD_Y(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_OUT_BUF_CTRL_PANIC_SET_THD_Y_SHIFT)) & ISI_CHNL_OUT_BUF_CTRL_PANIC_SET_THD_Y_MASK) + +#define ISI_CHNL_OUT_BUF_CTRL_PANIC_SET_THD_U_MASK (0xF00U) +#define ISI_CHNL_OUT_BUF_CTRL_PANIC_SET_THD_U_SHIFT (8U) +/*! PANIC_SET_THD_U - Overflow Panic Set Threshold Value for U Output Buffer + * 0b0000..No panic alert + * 0b0001-0b1111..Panic asserts + */ +#define ISI_CHNL_OUT_BUF_CTRL_PANIC_SET_THD_U(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_OUT_BUF_CTRL_PANIC_SET_THD_U_SHIFT)) & ISI_CHNL_OUT_BUF_CTRL_PANIC_SET_THD_U_MASK) + +#define ISI_CHNL_OUT_BUF_CTRL_LOAD_BUF1_ADDR_MASK (0x4000U) +#define ISI_CHNL_OUT_BUF_CTRL_LOAD_BUF1_ADDR_SHIFT (14U) +/*! LOAD_BUF1_ADDR - Load Buffer 1 Address */ +#define ISI_CHNL_OUT_BUF_CTRL_LOAD_BUF1_ADDR(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_OUT_BUF_CTRL_LOAD_BUF1_ADDR_SHIFT)) & ISI_CHNL_OUT_BUF_CTRL_LOAD_BUF1_ADDR_MASK) + +#define ISI_CHNL_OUT_BUF_CTRL_LOAD_BUF2_ADDR_MASK (0x8000U) +#define ISI_CHNL_OUT_BUF_CTRL_LOAD_BUF2_ADDR_SHIFT (15U) +/*! LOAD_BUF2_ADDR - Load Buffer 2 Address */ +#define ISI_CHNL_OUT_BUF_CTRL_LOAD_BUF2_ADDR(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_OUT_BUF_CTRL_LOAD_BUF2_ADDR_SHIFT)) & ISI_CHNL_OUT_BUF_CTRL_LOAD_BUF2_ADDR_MASK) + +#define ISI_CHNL_OUT_BUF_CTRL_PANIC_SET_THD_V_MASK (0xF0000U) +#define ISI_CHNL_OUT_BUF_CTRL_PANIC_SET_THD_V_SHIFT (16U) +/*! PANIC_SET_THD_V - Overflow Panic Set Threshold Value for V Output Buffer + * 0b0000..No panic alert + * 0b0001-0b1111..Panic asserts + */ +#define ISI_CHNL_OUT_BUF_CTRL_PANIC_SET_THD_V(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_OUT_BUF_CTRL_PANIC_SET_THD_V_SHIFT)) & ISI_CHNL_OUT_BUF_CTRL_PANIC_SET_THD_V_MASK) + +#define ISI_CHNL_OUT_BUF_CTRL_MAX_WR_BEATS_UV_MASK (0x40000000U) +#define ISI_CHNL_OUT_BUF_CTRL_MAX_WR_BEATS_UV_SHIFT (30U) +/*! MAX_WR_BEATS_UV - Maximum AXI Write Beats for U- and V-Buffers + * 0b0..8 beats per write (128 bytes) + * 0b1..16 beats per write (256 bytes) + */ +#define ISI_CHNL_OUT_BUF_CTRL_MAX_WR_BEATS_UV(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_OUT_BUF_CTRL_MAX_WR_BEATS_UV_SHIFT)) & ISI_CHNL_OUT_BUF_CTRL_MAX_WR_BEATS_UV_MASK) + +#define ISI_CHNL_OUT_BUF_CTRL_MAX_WR_BEATS_Y_MASK (0x80000000U) +#define ISI_CHNL_OUT_BUF_CTRL_MAX_WR_BEATS_Y_SHIFT (31U) +/*! MAX_WR_BEATS_Y - Maximum AXI Write Beats for Y-Buffer + * 0b0..8 beats per write (128 bytes) + * 0b1..16 beats per write (256 bytes) + */ +#define ISI_CHNL_OUT_BUF_CTRL_MAX_WR_BEATS_Y(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_OUT_BUF_CTRL_MAX_WR_BEATS_Y_SHIFT)) & ISI_CHNL_OUT_BUF_CTRL_MAX_WR_BEATS_Y_MASK) +/*! @} */ + +/*! @name CHNL_IMG_CFG - Channel Image Configuration */ +/*! @{ */ + +#define ISI_CHNL_IMG_CFG_WIDTH_MASK (0x1FFFU) +#define ISI_CHNL_IMG_CFG_WIDTH_SHIFT (0U) +/*! WIDTH - Input Image Width */ +#define ISI_CHNL_IMG_CFG_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IMG_CFG_WIDTH_SHIFT)) & ISI_CHNL_IMG_CFG_WIDTH_MASK) + +#define ISI_CHNL_IMG_CFG_HEIGHT_MASK (0x1FFF0000U) +#define ISI_CHNL_IMG_CFG_HEIGHT_SHIFT (16U) +/*! HEIGHT - Input Image Height */ +#define ISI_CHNL_IMG_CFG_HEIGHT(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IMG_CFG_HEIGHT_SHIFT)) & ISI_CHNL_IMG_CFG_HEIGHT_MASK) +/*! @} */ + +/*! @name CHNL_IER - Channel Interrupt Enable */ +/*! @{ */ + +#define ISI_CHNL_IER_LATE_VSYNC_ERR_EN_MASK (0x10000U) +#define ISI_CHNL_IER_LATE_VSYNC_ERR_EN_SHIFT (16U) +/*! LATE_VSYNC_ERR_EN - VSYNC Timing (Late) Error Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define ISI_CHNL_IER_LATE_VSYNC_ERR_EN(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IER_LATE_VSYNC_ERR_EN_SHIFT)) & ISI_CHNL_IER_LATE_VSYNC_ERR_EN_MASK) + +#define ISI_CHNL_IER_EARLY_VSYNC_ERR_EN_MASK (0x20000U) +#define ISI_CHNL_IER_EARLY_VSYNC_ERR_EN_SHIFT (17U) +/*! EARLY_VSYNC_ERR_EN - VSYNC Timing (Early) Error Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define ISI_CHNL_IER_EARLY_VSYNC_ERR_EN(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IER_EARLY_VSYNC_ERR_EN_SHIFT)) & ISI_CHNL_IER_EARLY_VSYNC_ERR_EN_MASK) + +#define ISI_CHNL_IER_OFLW_Y_BUF_EN_MASK (0x40000U) +#define ISI_CHNL_IER_OFLW_Y_BUF_EN_SHIFT (18U) +/*! OFLW_Y_BUF_EN - Y Output Buffer Overflow Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define ISI_CHNL_IER_OFLW_Y_BUF_EN(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IER_OFLW_Y_BUF_EN_SHIFT)) & ISI_CHNL_IER_OFLW_Y_BUF_EN_MASK) + +#define ISI_CHNL_IER_PANIC_Y_BUF_EN_MASK (0x80000U) +#define ISI_CHNL_IER_PANIC_Y_BUF_EN_SHIFT (19U) +/*! PANIC_Y_BUF_EN - Y Output Buffer Potential Overflow Panic Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define ISI_CHNL_IER_PANIC_Y_BUF_EN(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IER_PANIC_Y_BUF_EN_SHIFT)) & ISI_CHNL_IER_PANIC_Y_BUF_EN_MASK) + +#define ISI_CHNL_IER_OFLW_U_BUF_EN_MASK (0x100000U) +#define ISI_CHNL_IER_OFLW_U_BUF_EN_SHIFT (20U) +/*! OFLW_U_BUF_EN - U Output Buffer Overflow Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define ISI_CHNL_IER_OFLW_U_BUF_EN(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IER_OFLW_U_BUF_EN_SHIFT)) & ISI_CHNL_IER_OFLW_U_BUF_EN_MASK) + +#define ISI_CHNL_IER_PANIC_U_BUF_EN_MASK (0x200000U) +#define ISI_CHNL_IER_PANIC_U_BUF_EN_SHIFT (21U) +/*! PANIC_U_BUF_EN - U Output Buffer Potential Overflow Panic Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define ISI_CHNL_IER_PANIC_U_BUF_EN(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IER_PANIC_U_BUF_EN_SHIFT)) & ISI_CHNL_IER_PANIC_U_BUF_EN_MASK) + +#define ISI_CHNL_IER_OFLW_V_BUF_EN_MASK (0x400000U) +#define ISI_CHNL_IER_OFLW_V_BUF_EN_SHIFT (22U) +/*! OFLW_V_BUF_EN - V Output Buffer Overflow Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define ISI_CHNL_IER_OFLW_V_BUF_EN(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IER_OFLW_V_BUF_EN_SHIFT)) & ISI_CHNL_IER_OFLW_V_BUF_EN_MASK) + +#define ISI_CHNL_IER_PANIC_V_BUF_EN_MASK (0x800000U) +#define ISI_CHNL_IER_PANIC_V_BUF_EN_SHIFT (23U) +/*! PANIC_V_BUF_EN - V Output Buffer Potential Overflow Panic Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define ISI_CHNL_IER_PANIC_V_BUF_EN(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IER_PANIC_V_BUF_EN_SHIFT)) & ISI_CHNL_IER_PANIC_V_BUF_EN_MASK) + +#define ISI_CHNL_IER_AXI_RD_ERR_EN_MASK (0x2000000U) +#define ISI_CHNL_IER_AXI_RD_ERR_EN_SHIFT (25U) +/*! AXI_RD_ERR_EN - AXI Bus Read Error Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define ISI_CHNL_IER_AXI_RD_ERR_EN(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IER_AXI_RD_ERR_EN_SHIFT)) & ISI_CHNL_IER_AXI_RD_ERR_EN_MASK) + +#define ISI_CHNL_IER_AXI_WR_ERR_Y_EN_MASK (0x4000000U) +#define ISI_CHNL_IER_AXI_WR_ERR_Y_EN_SHIFT (26U) +/*! AXI_WR_ERR_Y_EN - AXI Bus Read Error Interrupt Enable for Y and RGB Data Buffer + * 0b0..Disable + * 0b1..Enable + */ +#define ISI_CHNL_IER_AXI_WR_ERR_Y_EN(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IER_AXI_WR_ERR_Y_EN_SHIFT)) & ISI_CHNL_IER_AXI_WR_ERR_Y_EN_MASK) + +#define ISI_CHNL_IER_AXI_WR_ERR_U_EN_MASK (0x8000000U) +#define ISI_CHNL_IER_AXI_WR_ERR_U_EN_SHIFT (27U) +/*! AXI_WR_ERR_U_EN - AXI Bus Read Error Interrupt Enable for U Data Buffer + * 0b0..Disable + * 0b1..Enable + */ +#define ISI_CHNL_IER_AXI_WR_ERR_U_EN(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IER_AXI_WR_ERR_U_EN_SHIFT)) & ISI_CHNL_IER_AXI_WR_ERR_U_EN_MASK) + +#define ISI_CHNL_IER_AXI_WR_ERR_V_EN_MASK (0x10000000U) +#define ISI_CHNL_IER_AXI_WR_ERR_V_EN_SHIFT (28U) +/*! AXI_WR_ERR_V_EN - AXI Bus Read Error Interrupt Enable for V Data Buffer + * 0b0..Disable + * 0b1..Enable + */ +#define ISI_CHNL_IER_AXI_WR_ERR_V_EN(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IER_AXI_WR_ERR_V_EN_SHIFT)) & ISI_CHNL_IER_AXI_WR_ERR_V_EN_MASK) + +#define ISI_CHNL_IER_FRM_RCVD_EN_MASK (0x20000000U) +#define ISI_CHNL_IER_FRM_RCVD_EN_SHIFT (29U) +/*! FRM_RCVD_EN - Frame Received Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define ISI_CHNL_IER_FRM_RCVD_EN(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IER_FRM_RCVD_EN_SHIFT)) & ISI_CHNL_IER_FRM_RCVD_EN_MASK) + +#define ISI_CHNL_IER_LINE_RCVD_EN_MASK (0x40000000U) +#define ISI_CHNL_IER_LINE_RCVD_EN_SHIFT (30U) +/*! LINE_RCVD_EN - Line Received Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define ISI_CHNL_IER_LINE_RCVD_EN(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IER_LINE_RCVD_EN_SHIFT)) & ISI_CHNL_IER_LINE_RCVD_EN_MASK) + +#define ISI_CHNL_IER_MEM_RD_DONE_EN_MASK (0x80000000U) +#define ISI_CHNL_IER_MEM_RD_DONE_EN_SHIFT (31U) +/*! MEM_RD_DONE_EN - Memory Read Complete Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define ISI_CHNL_IER_MEM_RD_DONE_EN(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IER_MEM_RD_DONE_EN_SHIFT)) & ISI_CHNL_IER_MEM_RD_DONE_EN_MASK) +/*! @} */ + +/*! @name CHNL_STS - Channel Status */ +/*! @{ */ + +#define ISI_CHNL_STS_BUF1_ACTIVE_MASK (0x100U) +#define ISI_CHNL_STS_BUF1_ACTIVE_SHIFT (8U) +/*! BUF1_ACTIVE - Current Frame Stored in Buffer 1 Address + * 0b0..Buffer 1 address inactive + * 0b1..Buffer 1 address in use + */ +#define ISI_CHNL_STS_BUF1_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_STS_BUF1_ACTIVE_SHIFT)) & ISI_CHNL_STS_BUF1_ACTIVE_MASK) + +#define ISI_CHNL_STS_BUF2_ACTIVE_MASK (0x200U) +#define ISI_CHNL_STS_BUF2_ACTIVE_SHIFT (9U) +/*! BUF2_ACTIVE - Current Frame Stored in Buffer 2 Address + * 0b0..Buffer 2 address inactive + * 0b1..Buffer 2 address in use + */ +#define ISI_CHNL_STS_BUF2_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_STS_BUF2_ACTIVE_SHIFT)) & ISI_CHNL_STS_BUF2_ACTIVE_MASK) + +#define ISI_CHNL_STS_MEM_RD_OFLOW_MASK (0x400U) +#define ISI_CHNL_STS_MEM_RD_OFLOW_SHIFT (10U) +/*! MEM_RD_OFLOW - Memory Read FIFO Overflow Error Status + * 0b0..No overflow + * 0b1..FIFO overflow + */ +#define ISI_CHNL_STS_MEM_RD_OFLOW(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_STS_MEM_RD_OFLOW_SHIFT)) & ISI_CHNL_STS_MEM_RD_OFLOW_MASK) + +#define ISI_CHNL_STS_LATE_VSYNC_ERR_MASK (0x10000U) +#define ISI_CHNL_STS_LATE_VSYNC_ERR_SHIFT (16U) +/*! LATE_VSYNC_ERR - VSYNC Timing (Late) Error Interrupt flag + * 0b0..No error + * 0b1..VSYNC detected later + */ +#define ISI_CHNL_STS_LATE_VSYNC_ERR(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_STS_LATE_VSYNC_ERR_SHIFT)) & ISI_CHNL_STS_LATE_VSYNC_ERR_MASK) + +#define ISI_CHNL_STS_EARLY_VSYNC_ERR_MASK (0x20000U) +#define ISI_CHNL_STS_EARLY_VSYNC_ERR_SHIFT (17U) +/*! EARLY_VSYNC_ERR - VSYNC Timing (Early) Error Interrupt flag + * 0b0..No error + * 0b1..VSYNC detected earlier + */ +#define ISI_CHNL_STS_EARLY_VSYNC_ERR(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_STS_EARLY_VSYNC_ERR_SHIFT)) & ISI_CHNL_STS_EARLY_VSYNC_ERR_MASK) + +#define ISI_CHNL_STS_OFLW_Y_BUF_MASK (0x40000U) +#define ISI_CHNL_STS_OFLW_Y_BUF_SHIFT (18U) +/*! OFLW_Y_BUF - Overflow in Y or RGB Output Buffer Interrupt Flag + * 0b0..No overflow + * 0b1..Overflow + */ +#define ISI_CHNL_STS_OFLW_Y_BUF(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_STS_OFLW_Y_BUF_SHIFT)) & ISI_CHNL_STS_OFLW_Y_BUF_MASK) + +#define ISI_CHNL_STS_PANIC_Y_BUF_MASK (0x80000U) +#define ISI_CHNL_STS_PANIC_Y_BUF_SHIFT (19U) +/*! PANIC_Y_BUF - Y or RGB Output Buffer Potential Overflow Panic Alert Interrupt Flag + * 0b0..Threshold limit not crossed + * 0b1..Threshold limit crossed + */ +#define ISI_CHNL_STS_PANIC_Y_BUF(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_STS_PANIC_Y_BUF_SHIFT)) & ISI_CHNL_STS_PANIC_Y_BUF_MASK) + +#define ISI_CHNL_STS_OFLW_U_BUF_MASK (0x100000U) +#define ISI_CHNL_STS_OFLW_U_BUF_SHIFT (20U) +/*! OFLW_U_BUF - Overflow in U Output Buffer Interrupt Flag + * 0b0..No overflow + * 0b1..Overflow + */ +#define ISI_CHNL_STS_OFLW_U_BUF(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_STS_OFLW_U_BUF_SHIFT)) & ISI_CHNL_STS_OFLW_U_BUF_MASK) + +#define ISI_CHNL_STS_PANIC_U_BUF_MASK (0x200000U) +#define ISI_CHNL_STS_PANIC_U_BUF_SHIFT (21U) +/*! PANIC_U_BUF - U Output Buffer Potential Overflow Panic Alert Interrupt Flag + * 0b0..Threshold limit not crossed + * 0b1..Threshold limit crossed + */ +#define ISI_CHNL_STS_PANIC_U_BUF(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_STS_PANIC_U_BUF_SHIFT)) & ISI_CHNL_STS_PANIC_U_BUF_MASK) + +#define ISI_CHNL_STS_OFLW_V_BUF_MASK (0x400000U) +#define ISI_CHNL_STS_OFLW_V_BUF_SHIFT (22U) +/*! OFLW_V_BUF - Overflow in V Output Buffer Interrupt Flag + * 0b0..No overflow + * 0b1..Overflow + */ +#define ISI_CHNL_STS_OFLW_V_BUF(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_STS_OFLW_V_BUF_SHIFT)) & ISI_CHNL_STS_OFLW_V_BUF_MASK) + +#define ISI_CHNL_STS_PANIC_V_BUF_MASK (0x800000U) +#define ISI_CHNL_STS_PANIC_V_BUF_SHIFT (23U) +/*! PANIC_V_BUF - V Output Buffer Potential Overflow Panic Alert Interrupt Flag + * 0b0..Threshold limit not crossed + * 0b1..Threshold limit crossed + */ +#define ISI_CHNL_STS_PANIC_V_BUF(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_STS_PANIC_V_BUF_SHIFT)) & ISI_CHNL_STS_PANIC_V_BUF_MASK) + +#define ISI_CHNL_STS_AXI_RD_ERR_MASK (0x2000000U) +#define ISI_CHNL_STS_AXI_RD_ERR_SHIFT (25U) +/*! AXI_RD_ERR - AXI Bus Read Error Interrupt Flag + * 0b0..No error + * 0b1..Error occurred + */ +#define ISI_CHNL_STS_AXI_RD_ERR(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_STS_AXI_RD_ERR_SHIFT)) & ISI_CHNL_STS_AXI_RD_ERR_MASK) + +#define ISI_CHNL_STS_AXI_WR_ERR_Y_MASK (0x4000000U) +#define ISI_CHNL_STS_AXI_WR_ERR_Y_SHIFT (26U) +/*! AXI_WR_ERR_Y - AXI Bus Write Error Interrupt Flag for Y/RGB Data Buffer + * 0b0..No error + * 0b1..Error occurred + */ +#define ISI_CHNL_STS_AXI_WR_ERR_Y(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_STS_AXI_WR_ERR_Y_SHIFT)) & ISI_CHNL_STS_AXI_WR_ERR_Y_MASK) + +#define ISI_CHNL_STS_AXI_WR_ERR_U_MASK (0x8000000U) +#define ISI_CHNL_STS_AXI_WR_ERR_U_SHIFT (27U) +/*! AXI_WR_ERR_U - AXI Bus Write Error Interrupt Flag for U Data Buffer + * 0b0..No error + * 0b1..Error occurred + */ +#define ISI_CHNL_STS_AXI_WR_ERR_U(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_STS_AXI_WR_ERR_U_SHIFT)) & ISI_CHNL_STS_AXI_WR_ERR_U_MASK) + +#define ISI_CHNL_STS_AXI_WR_ERR_V_MASK (0x10000000U) +#define ISI_CHNL_STS_AXI_WR_ERR_V_SHIFT (28U) +/*! AXI_WR_ERR_V - AXI Bus Write Error Interrupt Flag for V Data Buffer + * 0b0..No error + * 0b1..Error occurred + */ +#define ISI_CHNL_STS_AXI_WR_ERR_V(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_STS_AXI_WR_ERR_V_SHIFT)) & ISI_CHNL_STS_AXI_WR_ERR_V_MASK) + +#define ISI_CHNL_STS_FRM_STRD_MASK (0x20000000U) +#define ISI_CHNL_STS_FRM_STRD_SHIFT (29U) +/*! FRM_STRD - Frame Stored Successfully Interrupt Flag + * 0b0..Not received or in progress + * 0b1..Received and stored + */ +#define ISI_CHNL_STS_FRM_STRD(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_STS_FRM_STRD_SHIFT)) & ISI_CHNL_STS_FRM_STRD_MASK) + +#define ISI_CHNL_STS_LINE_STRD_MASK (0x40000000U) +#define ISI_CHNL_STS_LINE_STRD_SHIFT (30U) +/*! LINE_STRD - Line Received and Stored Interrupt Flag + * 0b0..Not received + * 0b1..Received and stored + */ +#define ISI_CHNL_STS_LINE_STRD(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_STS_LINE_STRD_SHIFT)) & ISI_CHNL_STS_LINE_STRD_MASK) + +#define ISI_CHNL_STS_MEM_RD_DONE_MASK (0x80000000U) +#define ISI_CHNL_STS_MEM_RD_DONE_SHIFT (31U) +/*! MEM_RD_DONE - Memory Read Complete Interrupt Flag + * 0b0..Not complete or not started + * 0b1..Completed + */ +#define ISI_CHNL_STS_MEM_RD_DONE(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_STS_MEM_RD_DONE_SHIFT)) & ISI_CHNL_STS_MEM_RD_DONE_MASK) +/*! @} */ + +/*! @name CHNL_SCALE_FACTOR - Channel Scale Factor */ +/*! @{ */ + +#define ISI_CHNL_SCALE_FACTOR_X_SCALE_MASK (0x3FFFU) +#define ISI_CHNL_SCALE_FACTOR_X_SCALE_SHIFT (0U) +/*! X_SCALE - Horizontal Scaling Factor */ +#define ISI_CHNL_SCALE_FACTOR_X_SCALE(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_SCALE_FACTOR_X_SCALE_SHIFT)) & ISI_CHNL_SCALE_FACTOR_X_SCALE_MASK) + +#define ISI_CHNL_SCALE_FACTOR_Y_SCALE_MASK (0x3FFF0000U) +#define ISI_CHNL_SCALE_FACTOR_Y_SCALE_SHIFT (16U) +/*! Y_SCALE - Vertical Scaling Factor */ +#define ISI_CHNL_SCALE_FACTOR_Y_SCALE(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_SCALE_FACTOR_Y_SCALE_SHIFT)) & ISI_CHNL_SCALE_FACTOR_Y_SCALE_MASK) +/*! @} */ + +/*! @name CHNL_SCALE_OFFSET - Channel Scale Offset */ +/*! @{ */ + +#define ISI_CHNL_SCALE_OFFSET_X_OFFSET_MASK (0xFFFU) +#define ISI_CHNL_SCALE_OFFSET_X_OFFSET_SHIFT (0U) +/*! X_OFFSET - Horizontal Scaling Offset */ +#define ISI_CHNL_SCALE_OFFSET_X_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_SCALE_OFFSET_X_OFFSET_SHIFT)) & ISI_CHNL_SCALE_OFFSET_X_OFFSET_MASK) + +#define ISI_CHNL_SCALE_OFFSET_Y_OFFSET_MASK (0xFFF0000U) +#define ISI_CHNL_SCALE_OFFSET_Y_OFFSET_SHIFT (16U) +/*! Y_OFFSET - Vertical Scaling Offset */ +#define ISI_CHNL_SCALE_OFFSET_Y_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_SCALE_OFFSET_Y_OFFSET_SHIFT)) & ISI_CHNL_SCALE_OFFSET_Y_OFFSET_MASK) +/*! @} */ + +/*! @name CHNL_CROP_ULC - Channel Crop Upper Left Corner Coordinate */ +/*! @{ */ + +#define ISI_CHNL_CROP_ULC_Y_MASK (0xFFFU) +#define ISI_CHNL_CROP_ULC_Y_SHIFT (0U) +/*! Y - Upper Left Y-Coordinate */ +#define ISI_CHNL_CROP_ULC_Y(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CROP_ULC_Y_SHIFT)) & ISI_CHNL_CROP_ULC_Y_MASK) + +#define ISI_CHNL_CROP_ULC_X_MASK (0xFFF0000U) +#define ISI_CHNL_CROP_ULC_X_SHIFT (16U) +/*! X - Upper Left X-Coordinate */ +#define ISI_CHNL_CROP_ULC_X(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CROP_ULC_X_SHIFT)) & ISI_CHNL_CROP_ULC_X_MASK) +/*! @} */ + +/*! @name CHNL_CROP_LRC - Channel Crop Lower Right Corner Coordinate */ +/*! @{ */ + +#define ISI_CHNL_CROP_LRC_Y_MASK (0xFFFU) +#define ISI_CHNL_CROP_LRC_Y_SHIFT (0U) +/*! Y - Lower Right Y-Coordinate */ +#define ISI_CHNL_CROP_LRC_Y(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CROP_LRC_Y_SHIFT)) & ISI_CHNL_CROP_LRC_Y_MASK) + +#define ISI_CHNL_CROP_LRC_X_MASK (0xFFF0000U) +#define ISI_CHNL_CROP_LRC_X_SHIFT (16U) +/*! X - Lower Right X-Coordinate */ +#define ISI_CHNL_CROP_LRC_X(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CROP_LRC_X_SHIFT)) & ISI_CHNL_CROP_LRC_X_MASK) +/*! @} */ + +/*! @name CHNL_CSC_COEFF0 - Channel Color Space Conversion Coefficient 0 */ +/*! @{ */ + +#define ISI_CHNL_CSC_COEFF0_A1_MASK (0x7FFU) +#define ISI_CHNL_CSC_COEFF0_A1_SHIFT (0U) +/*! A1 - CSC Coefficient A1 Value */ +#define ISI_CHNL_CSC_COEFF0_A1(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CSC_COEFF0_A1_SHIFT)) & ISI_CHNL_CSC_COEFF0_A1_MASK) + +#define ISI_CHNL_CSC_COEFF0_A2_MASK (0x7FF0000U) +#define ISI_CHNL_CSC_COEFF0_A2_SHIFT (16U) +/*! A2 - CSC Coefficient A2 Value */ +#define ISI_CHNL_CSC_COEFF0_A2(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CSC_COEFF0_A2_SHIFT)) & ISI_CHNL_CSC_COEFF0_A2_MASK) +/*! @} */ + +/*! @name CHNL_CSC_COEFF1 - Channel Color Space Conversion Coefficient 1 */ +/*! @{ */ + +#define ISI_CHNL_CSC_COEFF1_A3_MASK (0x7FFU) +#define ISI_CHNL_CSC_COEFF1_A3_SHIFT (0U) +/*! A3 - CSC Coefficient A3 Value */ +#define ISI_CHNL_CSC_COEFF1_A3(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CSC_COEFF1_A3_SHIFT)) & ISI_CHNL_CSC_COEFF1_A3_MASK) + +#define ISI_CHNL_CSC_COEFF1_B1_MASK (0x7FF0000U) +#define ISI_CHNL_CSC_COEFF1_B1_SHIFT (16U) +/*! B1 - CSC Coefficient B1 Value */ +#define ISI_CHNL_CSC_COEFF1_B1(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CSC_COEFF1_B1_SHIFT)) & ISI_CHNL_CSC_COEFF1_B1_MASK) +/*! @} */ + +/*! @name CHNL_CSC_COEFF2 - Channel Color Space Conversion Coefficient 2 */ +/*! @{ */ + +#define ISI_CHNL_CSC_COEFF2_B2_MASK (0x7FFU) +#define ISI_CHNL_CSC_COEFF2_B2_SHIFT (0U) +/*! B2 - CSC Coefficient B2 Value */ +#define ISI_CHNL_CSC_COEFF2_B2(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CSC_COEFF2_B2_SHIFT)) & ISI_CHNL_CSC_COEFF2_B2_MASK) + +#define ISI_CHNL_CSC_COEFF2_B3_MASK (0x7FF0000U) +#define ISI_CHNL_CSC_COEFF2_B3_SHIFT (16U) +/*! B3 - CSC Coefficient B3 Value */ +#define ISI_CHNL_CSC_COEFF2_B3(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CSC_COEFF2_B3_SHIFT)) & ISI_CHNL_CSC_COEFF2_B3_MASK) +/*! @} */ + +/*! @name CHNL_CSC_COEFF3 - Channel Color Space Conversion Coefficient 3 */ +/*! @{ */ + +#define ISI_CHNL_CSC_COEFF3_C1_MASK (0x7FFU) +#define ISI_CHNL_CSC_COEFF3_C1_SHIFT (0U) +/*! C1 - CSC Coefficient C1 Value */ +#define ISI_CHNL_CSC_COEFF3_C1(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CSC_COEFF3_C1_SHIFT)) & ISI_CHNL_CSC_COEFF3_C1_MASK) + +#define ISI_CHNL_CSC_COEFF3_C2_MASK (0x7FF0000U) +#define ISI_CHNL_CSC_COEFF3_C2_SHIFT (16U) +/*! C2 - CSC Coefficient C2 Value */ +#define ISI_CHNL_CSC_COEFF3_C2(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CSC_COEFF3_C2_SHIFT)) & ISI_CHNL_CSC_COEFF3_C2_MASK) +/*! @} */ + +/*! @name CHNL_CSC_COEFF4 - Channel Color Space Conversion Coefficient 4 */ +/*! @{ */ + +#define ISI_CHNL_CSC_COEFF4_C3_MASK (0x7FFU) +#define ISI_CHNL_CSC_COEFF4_C3_SHIFT (0U) +/*! C3 - CSC Coefficient C3 Value */ +#define ISI_CHNL_CSC_COEFF4_C3(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CSC_COEFF4_C3_SHIFT)) & ISI_CHNL_CSC_COEFF4_C3_MASK) + +#define ISI_CHNL_CSC_COEFF4_D1_MASK (0x1FF0000U) +#define ISI_CHNL_CSC_COEFF4_D1_SHIFT (16U) +/*! D1 - CSC Coefficient D1 Value */ +#define ISI_CHNL_CSC_COEFF4_D1(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CSC_COEFF4_D1_SHIFT)) & ISI_CHNL_CSC_COEFF4_D1_MASK) +/*! @} */ + +/*! @name CHNL_CSC_COEFF5 - Channel Color Space Conversion Coefficient 5 */ +/*! @{ */ + +#define ISI_CHNL_CSC_COEFF5_D2_MASK (0x1FFU) +#define ISI_CHNL_CSC_COEFF5_D2_SHIFT (0U) +/*! D2 - CSC Coefficient D2 Value */ +#define ISI_CHNL_CSC_COEFF5_D2(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CSC_COEFF5_D2_SHIFT)) & ISI_CHNL_CSC_COEFF5_D2_MASK) + +#define ISI_CHNL_CSC_COEFF5_D3_MASK (0x1FF0000U) +#define ISI_CHNL_CSC_COEFF5_D3_SHIFT (16U) +/*! D3 - CSC Coefficient D3 Value */ +#define ISI_CHNL_CSC_COEFF5_D3(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CSC_COEFF5_D3_SHIFT)) & ISI_CHNL_CSC_COEFF5_D3_MASK) +/*! @} */ + +/*! @name CHNL_ROI_0_ALPHA - Channel Alpha Value for ROI 0 */ +/*! @{ */ + +#define ISI_CHNL_ROI_0_ALPHA_ALPHA_EN_MASK (0x10000U) +#define ISI_CHNL_ROI_0_ALPHA_ALPHA_EN_SHIFT (16U) +/*! ALPHA_EN - Alpha Value Insertion Enable + * 0b0..Disable + * 0b1..Enable + */ +#define ISI_CHNL_ROI_0_ALPHA_ALPHA_EN(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_0_ALPHA_ALPHA_EN_SHIFT)) & ISI_CHNL_ROI_0_ALPHA_ALPHA_EN_MASK) + +#define ISI_CHNL_ROI_0_ALPHA_ALPHA_MASK (0xFF000000U) +#define ISI_CHNL_ROI_0_ALPHA_ALPHA_SHIFT (24U) +/*! ALPHA - Alpha Value */ +#define ISI_CHNL_ROI_0_ALPHA_ALPHA(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_0_ALPHA_ALPHA_SHIFT)) & ISI_CHNL_ROI_0_ALPHA_ALPHA_MASK) +/*! @} */ + +/*! @name CHNL_ROI_0_ULC - Channel Upper Left Coordinate for ROI 0 */ +/*! @{ */ + +#define ISI_CHNL_ROI_0_ULC_Y_MASK (0xFFFU) +#define ISI_CHNL_ROI_0_ULC_Y_SHIFT (0U) +/*! Y - Upper Left Y-Coordinate */ +#define ISI_CHNL_ROI_0_ULC_Y(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_0_ULC_Y_SHIFT)) & ISI_CHNL_ROI_0_ULC_Y_MASK) + +#define ISI_CHNL_ROI_0_ULC_X_MASK (0xFFF0000U) +#define ISI_CHNL_ROI_0_ULC_X_SHIFT (16U) +/*! X - Upper Left X-Coordinate */ +#define ISI_CHNL_ROI_0_ULC_X(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_0_ULC_X_SHIFT)) & ISI_CHNL_ROI_0_ULC_X_MASK) +/*! @} */ + +/*! @name CHNL_ROI_0_LRC - Channel Lower Right Coordinate for ROI 0 */ +/*! @{ */ + +#define ISI_CHNL_ROI_0_LRC_Y_MASK (0xFFFU) +#define ISI_CHNL_ROI_0_LRC_Y_SHIFT (0U) +/*! Y - Lower Right Y-Coordinate */ +#define ISI_CHNL_ROI_0_LRC_Y(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_0_LRC_Y_SHIFT)) & ISI_CHNL_ROI_0_LRC_Y_MASK) + +#define ISI_CHNL_ROI_0_LRC_X_MASK (0xFFF0000U) +#define ISI_CHNL_ROI_0_LRC_X_SHIFT (16U) +/*! X - Lower Right X-Coordinate */ +#define ISI_CHNL_ROI_0_LRC_X(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_0_LRC_X_SHIFT)) & ISI_CHNL_ROI_0_LRC_X_MASK) +/*! @} */ + +/*! @name CHNL_ROI_1_ALPHA - Channel Alpha Value for ROI 1 */ +/*! @{ */ + +#define ISI_CHNL_ROI_1_ALPHA_ALPHA_EN_MASK (0x10000U) +#define ISI_CHNL_ROI_1_ALPHA_ALPHA_EN_SHIFT (16U) +/*! ALPHA_EN - Alpha Value Insertion Enable + * 0b0..Disable + * 0b1..Enable + */ +#define ISI_CHNL_ROI_1_ALPHA_ALPHA_EN(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_1_ALPHA_ALPHA_EN_SHIFT)) & ISI_CHNL_ROI_1_ALPHA_ALPHA_EN_MASK) + +#define ISI_CHNL_ROI_1_ALPHA_ALPHA_MASK (0xFF000000U) +#define ISI_CHNL_ROI_1_ALPHA_ALPHA_SHIFT (24U) +/*! ALPHA - Alpha Value */ +#define ISI_CHNL_ROI_1_ALPHA_ALPHA(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_1_ALPHA_ALPHA_SHIFT)) & ISI_CHNL_ROI_1_ALPHA_ALPHA_MASK) +/*! @} */ + +/*! @name CHNL_ROI_1_ULC - Channel Upper Left Coordinate for ROI 1 */ +/*! @{ */ + +#define ISI_CHNL_ROI_1_ULC_Y_MASK (0xFFFU) +#define ISI_CHNL_ROI_1_ULC_Y_SHIFT (0U) +/*! Y - Upper Left Y-Coordinate */ +#define ISI_CHNL_ROI_1_ULC_Y(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_1_ULC_Y_SHIFT)) & ISI_CHNL_ROI_1_ULC_Y_MASK) + +#define ISI_CHNL_ROI_1_ULC_X_MASK (0xFFF0000U) +#define ISI_CHNL_ROI_1_ULC_X_SHIFT (16U) +/*! X - Upper Left X-Coordinate */ +#define ISI_CHNL_ROI_1_ULC_X(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_1_ULC_X_SHIFT)) & ISI_CHNL_ROI_1_ULC_X_MASK) +/*! @} */ + +/*! @name CHNL_ROI_1_LRC - Channel Lower Right Coordinate for ROI 1 */ +/*! @{ */ + +#define ISI_CHNL_ROI_1_LRC_Y_MASK (0xFFFU) +#define ISI_CHNL_ROI_1_LRC_Y_SHIFT (0U) +/*! Y - Lower Right Y-Coordinate */ +#define ISI_CHNL_ROI_1_LRC_Y(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_1_LRC_Y_SHIFT)) & ISI_CHNL_ROI_1_LRC_Y_MASK) + +#define ISI_CHNL_ROI_1_LRC_X_MASK (0xFFF0000U) +#define ISI_CHNL_ROI_1_LRC_X_SHIFT (16U) +/*! X - Lower Right X-Coordinate */ +#define ISI_CHNL_ROI_1_LRC_X(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_1_LRC_X_SHIFT)) & ISI_CHNL_ROI_1_LRC_X_MASK) +/*! @} */ + +/*! @name CHNL_ROI_2_ALPHA - Channel Alpha Value for ROI 2 */ +/*! @{ */ + +#define ISI_CHNL_ROI_2_ALPHA_ALPHA_EN_MASK (0x10000U) +#define ISI_CHNL_ROI_2_ALPHA_ALPHA_EN_SHIFT (16U) +/*! ALPHA_EN - Alpha Value Insertion Enable + * 0b0..Disable + * 0b1..Enable + */ +#define ISI_CHNL_ROI_2_ALPHA_ALPHA_EN(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_2_ALPHA_ALPHA_EN_SHIFT)) & ISI_CHNL_ROI_2_ALPHA_ALPHA_EN_MASK) + +#define ISI_CHNL_ROI_2_ALPHA_ALPHA_MASK (0xFF000000U) +#define ISI_CHNL_ROI_2_ALPHA_ALPHA_SHIFT (24U) +/*! ALPHA - Alpha Value */ +#define ISI_CHNL_ROI_2_ALPHA_ALPHA(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_2_ALPHA_ALPHA_SHIFT)) & ISI_CHNL_ROI_2_ALPHA_ALPHA_MASK) +/*! @} */ + +/*! @name CHNL_ROI_2_ULC - Channel Upper Left Coordinate for ROI 2 */ +/*! @{ */ + +#define ISI_CHNL_ROI_2_ULC_Y_MASK (0xFFFU) +#define ISI_CHNL_ROI_2_ULC_Y_SHIFT (0U) +/*! Y - Upper Left Y-Coordinate */ +#define ISI_CHNL_ROI_2_ULC_Y(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_2_ULC_Y_SHIFT)) & ISI_CHNL_ROI_2_ULC_Y_MASK) + +#define ISI_CHNL_ROI_2_ULC_X_MASK (0xFFF0000U) +#define ISI_CHNL_ROI_2_ULC_X_SHIFT (16U) +/*! X - Upper Left X-Coordinate */ +#define ISI_CHNL_ROI_2_ULC_X(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_2_ULC_X_SHIFT)) & ISI_CHNL_ROI_2_ULC_X_MASK) +/*! @} */ + +/*! @name CHNL_ROI_2_LRC - Channel Lower Right Coordinate for ROI 2 */ +/*! @{ */ + +#define ISI_CHNL_ROI_2_LRC_Y_MASK (0xFFFU) +#define ISI_CHNL_ROI_2_LRC_Y_SHIFT (0U) +/*! Y - Lower Right Y-Coordinate */ +#define ISI_CHNL_ROI_2_LRC_Y(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_2_LRC_Y_SHIFT)) & ISI_CHNL_ROI_2_LRC_Y_MASK) + +#define ISI_CHNL_ROI_2_LRC_X_MASK (0xFFF0000U) +#define ISI_CHNL_ROI_2_LRC_X_SHIFT (16U) +/*! X - Lower Right X-Coordinate */ +#define ISI_CHNL_ROI_2_LRC_X(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_2_LRC_X_SHIFT)) & ISI_CHNL_ROI_2_LRC_X_MASK) +/*! @} */ + +/*! @name CHNL_ROI_3_ALPHA - Channel Alpha Value for ROI 3 */ +/*! @{ */ + +#define ISI_CHNL_ROI_3_ALPHA_ALPHA_EN_MASK (0x10000U) +#define ISI_CHNL_ROI_3_ALPHA_ALPHA_EN_SHIFT (16U) +/*! ALPHA_EN - Alpha Value Insertion Enable + * 0b0..Disable + * 0b1..Enable + */ +#define ISI_CHNL_ROI_3_ALPHA_ALPHA_EN(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_3_ALPHA_ALPHA_EN_SHIFT)) & ISI_CHNL_ROI_3_ALPHA_ALPHA_EN_MASK) + +#define ISI_CHNL_ROI_3_ALPHA_ALPHA_MASK (0xFF000000U) +#define ISI_CHNL_ROI_3_ALPHA_ALPHA_SHIFT (24U) +/*! ALPHA - Alpha Value */ +#define ISI_CHNL_ROI_3_ALPHA_ALPHA(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_3_ALPHA_ALPHA_SHIFT)) & ISI_CHNL_ROI_3_ALPHA_ALPHA_MASK) +/*! @} */ + +/*! @name CHNL_ROI_3_ULC - Channel Upper Left Coordinate for ROI 3 */ +/*! @{ */ + +#define ISI_CHNL_ROI_3_ULC_Y_MASK (0xFFFU) +#define ISI_CHNL_ROI_3_ULC_Y_SHIFT (0U) +/*! Y - Upper Left Y-Coordinate */ +#define ISI_CHNL_ROI_3_ULC_Y(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_3_ULC_Y_SHIFT)) & ISI_CHNL_ROI_3_ULC_Y_MASK) + +#define ISI_CHNL_ROI_3_ULC_X_MASK (0xFFF0000U) +#define ISI_CHNL_ROI_3_ULC_X_SHIFT (16U) +/*! X - Upper Left X-Coordinate */ +#define ISI_CHNL_ROI_3_ULC_X(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_3_ULC_X_SHIFT)) & ISI_CHNL_ROI_3_ULC_X_MASK) +/*! @} */ + +/*! @name CHNL_ROI_3_LRC - Channel Lower Right Coordinate for ROI 3 */ +/*! @{ */ + +#define ISI_CHNL_ROI_3_LRC_Y_MASK (0xFFFU) +#define ISI_CHNL_ROI_3_LRC_Y_SHIFT (0U) +/*! Y - Lower Right Y-Coordinate */ +#define ISI_CHNL_ROI_3_LRC_Y(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_3_LRC_Y_SHIFT)) & ISI_CHNL_ROI_3_LRC_Y_MASK) + +#define ISI_CHNL_ROI_3_LRC_X_MASK (0xFFF0000U) +#define ISI_CHNL_ROI_3_LRC_X_SHIFT (16U) +/*! X - Lower Right X-Coordinate */ +#define ISI_CHNL_ROI_3_LRC_X(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_3_LRC_X_SHIFT)) & ISI_CHNL_ROI_3_LRC_X_MASK) +/*! @} */ + +/*! @name CHNL_OUT_BUF1_ADDR_Y - Channel RGB or Luma (Y) Output Buffer 1 Address */ +/*! @{ */ + +#define ISI_CHNL_OUT_BUF1_ADDR_Y_ADDR_MASK (0xFFFFFFFFU) +#define ISI_CHNL_OUT_BUF1_ADDR_Y_ADDR_SHIFT (0U) +/*! ADDR - Address for RGB or Y (Luma) */ +#define ISI_CHNL_OUT_BUF1_ADDR_Y_ADDR(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_OUT_BUF1_ADDR_Y_ADDR_SHIFT)) & ISI_CHNL_OUT_BUF1_ADDR_Y_ADDR_MASK) +/*! @} */ + +/*! @name CHNL_OUT_BUF1_ADDR_U - Channel Chroma (U/Cb/UV/CbCr) Output Buffer 1 Address */ +/*! @{ */ + +#define ISI_CHNL_OUT_BUF1_ADDR_U_ADDR_MASK (0xFFFFFFFFU) +#define ISI_CHNL_OUT_BUF1_ADDR_U_ADDR_SHIFT (0U) +/*! ADDR - Address for U/Cb/UV/CbCr */ +#define ISI_CHNL_OUT_BUF1_ADDR_U_ADDR(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_OUT_BUF1_ADDR_U_ADDR_SHIFT)) & ISI_CHNL_OUT_BUF1_ADDR_U_ADDR_MASK) +/*! @} */ + +/*! @name CHNL_OUT_BUF1_ADDR_V - Channel Chroma (V/Cr) Output Buffer 1 Address */ +/*! @{ */ + +#define ISI_CHNL_OUT_BUF1_ADDR_V_ADDR_MASK (0xFFFFFFFFU) +#define ISI_CHNL_OUT_BUF1_ADDR_V_ADDR_SHIFT (0U) +/*! ADDR - Address for V or Cr */ +#define ISI_CHNL_OUT_BUF1_ADDR_V_ADDR(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_OUT_BUF1_ADDR_V_ADDR_SHIFT)) & ISI_CHNL_OUT_BUF1_ADDR_V_ADDR_MASK) +/*! @} */ + +/*! @name CHNL_OUT_BUF_PITCH - Channel Output Buffer Pitch */ +/*! @{ */ + +#define ISI_CHNL_OUT_BUF_PITCH_LINE_PITCH_MASK (0xFFFFU) +#define ISI_CHNL_OUT_BUF_PITCH_LINE_PITCH_SHIFT (0U) +/*! LINE_PITCH - Output Buffer Line Pitch */ +#define ISI_CHNL_OUT_BUF_PITCH_LINE_PITCH(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_OUT_BUF_PITCH_LINE_PITCH_SHIFT)) & ISI_CHNL_OUT_BUF_PITCH_LINE_PITCH_MASK) +/*! @} */ + +/*! @name CHNL_IN_BUF_PITCH - Channel Input Buffer Pitch */ +/*! @{ */ + +#define ISI_CHNL_IN_BUF_PITCH_LINE_PITCH_MASK (0xFFFFU) +#define ISI_CHNL_IN_BUF_PITCH_LINE_PITCH_SHIFT (0U) +/*! LINE_PITCH - Line Pitch */ +#define ISI_CHNL_IN_BUF_PITCH_LINE_PITCH(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IN_BUF_PITCH_LINE_PITCH_SHIFT)) & ISI_CHNL_IN_BUF_PITCH_LINE_PITCH_MASK) + +#define ISI_CHNL_IN_BUF_PITCH_FRM_PITCH_MASK (0xFFFF0000U) +#define ISI_CHNL_IN_BUF_PITCH_FRM_PITCH_SHIFT (16U) +/*! FRM_PITCH - Frame Pitch */ +#define ISI_CHNL_IN_BUF_PITCH_FRM_PITCH(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IN_BUF_PITCH_FRM_PITCH_SHIFT)) & ISI_CHNL_IN_BUF_PITCH_FRM_PITCH_MASK) +/*! @} */ + +/*! @name CHNL_MEM_RD_CTRL - Channel Memory Read Control */ +/*! @{ */ + +#define ISI_CHNL_MEM_RD_CTRL_READ_MEM_MASK (0x1U) +#define ISI_CHNL_MEM_RD_CTRL_READ_MEM_SHIFT (0U) +/*! READ_MEM - Initiate Read from Memory + * 0b0..No reads + * 0b1..Reads initiated + */ +#define ISI_CHNL_MEM_RD_CTRL_READ_MEM(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_MEM_RD_CTRL_READ_MEM_SHIFT)) & ISI_CHNL_MEM_RD_CTRL_READ_MEM_MASK) + +#define ISI_CHNL_MEM_RD_CTRL_IMG_TYPE_MASK (0xF0000000U) +#define ISI_CHNL_MEM_RD_CTRL_IMG_TYPE_SHIFT (28U) +/*! IMG_TYPE - Input Image Format */ +#define ISI_CHNL_MEM_RD_CTRL_IMG_TYPE(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_MEM_RD_CTRL_IMG_TYPE_SHIFT)) & ISI_CHNL_MEM_RD_CTRL_IMG_TYPE_MASK) +/*! @} */ + +/*! @name CHNL_OUT_BUF2_ADDR_Y - Channel RGB or Luma (Y) Output Buffer 2 Address */ +/*! @{ */ + +#define ISI_CHNL_OUT_BUF2_ADDR_Y_ADDR_MASK (0xFFFFFFFFU) +#define ISI_CHNL_OUT_BUF2_ADDR_Y_ADDR_SHIFT (0U) +/*! ADDR - Starting Address for RGB or Y */ +#define ISI_CHNL_OUT_BUF2_ADDR_Y_ADDR(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_OUT_BUF2_ADDR_Y_ADDR_SHIFT)) & ISI_CHNL_OUT_BUF2_ADDR_Y_ADDR_MASK) +/*! @} */ + +/*! @name CHNL_OUT_BUF2_ADDR_U - Channel Chroma (U/Cb/UV/CbCr) Output Buffer 2 Address */ +/*! @{ */ + +#define ISI_CHNL_OUT_BUF2_ADDR_U_ADDR_MASK (0xFFFFFFFFU) +#define ISI_CHNL_OUT_BUF2_ADDR_U_ADDR_SHIFT (0U) +/*! ADDR - Starting Address for U/Cb or 2-plane UV/CbCr */ +#define ISI_CHNL_OUT_BUF2_ADDR_U_ADDR(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_OUT_BUF2_ADDR_U_ADDR_SHIFT)) & ISI_CHNL_OUT_BUF2_ADDR_U_ADDR_MASK) +/*! @} */ + +/*! @name CHNL_OUT_BUF2_ADDR_V - Channel Chroma (V/Cr) Output Buffer 2 Address */ +/*! @{ */ + +#define ISI_CHNL_OUT_BUF2_ADDR_V_ADDR_MASK (0xFFFFFFFFU) +#define ISI_CHNL_OUT_BUF2_ADDR_V_ADDR_SHIFT (0U) +/*! ADDR - Starting Address for V or Cr */ +#define ISI_CHNL_OUT_BUF2_ADDR_V_ADDR(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_OUT_BUF2_ADDR_V_ADDR_SHIFT)) & ISI_CHNL_OUT_BUF2_ADDR_V_ADDR_MASK) +/*! @} */ + +/*! @name CHNL_SCL_IMG_CFG - Channel Scaled Image Configuration */ +/*! @{ */ + +#define ISI_CHNL_SCL_IMG_CFG_WIDTH_MASK (0x1FFFU) +#define ISI_CHNL_SCL_IMG_CFG_WIDTH_SHIFT (0U) +/*! WIDTH - Scaled Image Width (Pixels) */ +#define ISI_CHNL_SCL_IMG_CFG_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_SCL_IMG_CFG_WIDTH_SHIFT)) & ISI_CHNL_SCL_IMG_CFG_WIDTH_MASK) + +#define ISI_CHNL_SCL_IMG_CFG_HEIGHT_MASK (0x1FFF0000U) +#define ISI_CHNL_SCL_IMG_CFG_HEIGHT_SHIFT (16U) +/*! HEIGHT - Scaled Image Height (Lines) */ +#define ISI_CHNL_SCL_IMG_CFG_HEIGHT(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_SCL_IMG_CFG_HEIGHT_SHIFT)) & ISI_CHNL_SCL_IMG_CFG_HEIGHT_MASK) +/*! @} */ + +/*! @name CHNL_FLOW_CTRL - Channel Flow Control */ +/*! @{ */ + +#define ISI_CHNL_FLOW_CTRL_FC_DENOM_MASK (0xFFU) +#define ISI_CHNL_FLOW_CTRL_FC_DENOM_SHIFT (0U) +/*! FC_DENOM - Denominator Value of Fraction of Usable Bandwidth + * 0b00000000..Invalid value (flow control disabled) + */ +#define ISI_CHNL_FLOW_CTRL_FC_DENOM(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_FLOW_CTRL_FC_DENOM_SHIFT)) & ISI_CHNL_FLOW_CTRL_FC_DENOM_MASK) + +#define ISI_CHNL_FLOW_CTRL_FC_NUMER_MASK (0xFF0000U) +#define ISI_CHNL_FLOW_CTRL_FC_NUMER_SHIFT (16U) +/*! FC_NUMER - Numerator Value of Fraction of Usable Bandwidth + * 0b00000000..Invalid value (flow control disabled) + */ +#define ISI_CHNL_FLOW_CTRL_FC_NUMER(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_FLOW_CTRL_FC_NUMER_SHIFT)) & ISI_CHNL_FLOW_CTRL_FC_NUMER_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group ISI_Register_Masks */ + + +/* ISI - Peripheral instance base addresses */ +/** Peripheral ISI base address */ +#define ISI_BASE (0x4AE40000u) +/** Peripheral ISI base pointer */ +#define ISI ((ISI_Type *)ISI_BASE) +/** Array initializer of ISI peripheral base addresses */ +#define ISI_BASE_ADDRS { ISI_BASE } +/** Array initializer of ISI peripheral base pointers */ +#define ISI_BASE_PTRS { ISI } + +/*! + * @} + */ /* end of group ISI_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- LCDIF Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup LCDIF_Peripheral_Access_Layer LCDIF Peripheral Access Layer + * @{ + */ + +/** LCDIF - Register Layout Typedef */ +typedef struct { + struct { /* offset: 0x0 */ + __IO uint32_t RW; /**< LCDIF display control Register, offset: 0x0 */ + __IO uint32_t SET; /**< LCDIF display control Register, offset: 0x4 */ + __IO uint32_t CLR; /**< LCDIF display control Register, offset: 0x8 */ + __IO uint32_t TOG; /**< LCDIF display control Register, offset: 0xC */ + } CTRL; + __IO uint32_t DISP_PARA; /**< Display Parameter Register, offset: 0x10 */ + __IO uint32_t DISP_SIZE; /**< Display Size Register, offset: 0x14 */ + __IO uint32_t HSYN_PARA; /**< Horizontal Sync Parameter Register, offset: 0x18 */ + __IO uint32_t VSYN_PARA; /**< Vertical Sync Parameter Register, offset: 0x1C */ + __IO uint32_t VSYN_HSYN_WIDTH; /**< Vertical and Horizontal Pulse Width Parameter Register, offset: 0x20 */ + __IO uint32_t INT_STATUS_D0; /**< Interrupt Status Register for domain 0, offset: 0x24 */ + __IO uint32_t INT_ENABLE_D0; /**< Interrupt Enable Register for domain 0, offset: 0x28 */ + uint8_t RESERVED_0[4]; + __IO uint32_t INT_STATUS_D1; /**< Interrupt Status Register for domain 0, offset: 0x30 */ + __IO uint32_t INT_ENABLE_D1; /**< Interrupt Enable Register for domain 0, offset: 0x34 */ + uint8_t RESERVED_1[456]; + __IO uint32_t CTRLDESCL_1[1]; /**< Control Descriptor Layer Register 1, array offset: 0x200, array step: 0x4 */ + uint8_t RESERVED_2[4]; + __IO uint32_t CTRLDESCL_3[1]; /**< Control Descriptor Layer Register 3, array offset: 0x208, array step: 0x4 */ + __IO uint32_t CTRLDESCL_LOW_4[1]; /**< Control Descriptor Layer Register 4, array offset: 0x20C, array step: 0x4 */ + __IO uint32_t CTRLDESCL_HIGH_4[1]; /**< Control Descriptor Layer Register 4, array offset: 0x210, array step: 0x4 */ + __IO uint32_t CTRLDESCL_5[1]; /**< Control Descriptor Layer Register 5, array offset: 0x214, array step: 0x4 */ + uint8_t RESERVED_3[4]; + __IO uint32_t CSC_CTRL[1]; /**< Color Space Conversion Ctrl Register, array offset: 0x21C, array step: 0x4 */ + __IO uint32_t CSC_COEF0[1]; /**< Color Space Conversion Coefficient Register 0, array offset: 0x220, array step: 0x4 */ + __IO uint32_t CSC_COEF1[1]; /**< Color Space Conversion Coefficient Register 1, array offset: 0x224, array step: 0x4 */ + __IO uint32_t CSC_COEF2[1]; /**< Color Space Conversion Coefficient Register 2, array offset: 0x228, array step: 0x4 */ + __IO uint32_t CSC_COEF3[1]; /**< Color Space Conversion Coefficient Register 3, array offset: 0x22C, array step: 0x4 */ + __IO uint32_t CSC_COEF4[1]; /**< Color Space Conversion Coefficient Register 4, array offset: 0x230, array step: 0x4 */ + __IO uint32_t CSC_COEF5[1]; /**< Color Space Conversion Coefficient Register 0, array offset: 0x234, array step: 0x4 */ + __IO uint32_t PANIC_THRES[1]; /**< Memory request priority threshold register, array offset: 0x238, array step: 0x4 */ +} LCDIF_Type; + +/* ---------------------------------------------------------------------------- + -- LCDIF Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup LCDIF_Register_Masks LCDIF Register Masks + * @{ + */ + +/*! @name CTRL - LCDIF display control Register */ +/*! @{ */ + +#define LCDIF_CTRL_INV_HS_MASK (0x1U) +#define LCDIF_CTRL_INV_HS_SHIFT (0U) +/*! INV_HS - Invert Horizontal synchronization signal. + * 0b0..HSYNC signal not inverted (active HIGH). + * 0b1..Invert HSYNC signal (active LOW). + */ +#define LCDIF_CTRL_INV_HS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_INV_HS_SHIFT)) & LCDIF_CTRL_INV_HS_MASK) + +#define LCDIF_CTRL_INV_VS_MASK (0x2U) +#define LCDIF_CTRL_INV_VS_SHIFT (1U) +/*! INV_VS - Invert Vertical synchronization signal. + * 0b0..VSYNC signal not inverted (active HIGH). + * 0b1..Invert VSYNC signal (active LOW). + */ +#define LCDIF_CTRL_INV_VS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_INV_VS_SHIFT)) & LCDIF_CTRL_INV_VS_MASK) + +#define LCDIF_CTRL_INV_DE_MASK (0x4U) +#define LCDIF_CTRL_INV_DE_SHIFT (2U) +/*! INV_DE - Invert Data Enable polarity + * 0b0..Data enable is active high + * 0b1..Data enable is active low + */ +#define LCDIF_CTRL_INV_DE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_INV_DE_SHIFT)) & LCDIF_CTRL_INV_DE_MASK) + +#define LCDIF_CTRL_INV_PXCK_MASK (0x8U) +#define LCDIF_CTRL_INV_PXCK_SHIFT (3U) +/*! INV_PXCK - Polarity change of Pixel Clock. + * 0b0..Display samples data on the falling edge + * 0b1..Display samples data on the rising edge + */ +#define LCDIF_CTRL_INV_PXCK(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_INV_PXCK_SHIFT)) & LCDIF_CTRL_INV_PXCK_MASK) + +#define LCDIF_CTRL_NEG_MASK (0x10U) +#define LCDIF_CTRL_NEG_SHIFT (4U) +/*! NEG - Indicates if value at the output (pixel data output) needs to be negated. + * 0b0..Output is to remain same + * 0b1..Output to be negated + */ +#define LCDIF_CTRL_NEG(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_NEG_SHIFT)) & LCDIF_CTRL_NEG_MASK) + +#define LCDIF_CTRL_fetch_start_option_MASK (0x300U) +#define LCDIF_CTRL_fetch_start_option_SHIFT (8U) +/*! fetch_start_option - Indicates when to start fetching for new frame. This signals also decide the shadow load, fifo clear time + * 0b00..fetch start as soon as FPV begins(as the end of the data_enable) + * 0b01..fetch start as soon as PWV begins + * 0b10..fetch start as soon as BPV begins + * 0b11..fetch start as soon as RESV begins(still have hsync blanking for margin) + */ +#define LCDIF_CTRL_fetch_start_option(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_fetch_start_option_SHIFT)) & LCDIF_CTRL_fetch_start_option_MASK) + +#define LCDIF_CTRL_SW_RESET_MASK (0x80000000U) +#define LCDIF_CTRL_SW_RESET_SHIFT (31U) +/*! SW_RESET - SW_RESET + * 0b0..No action + * 0b1..All LCDIF internal registers are forced into their reset state. User registers are not affected. + */ +#define LCDIF_CTRL_SW_RESET(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SW_RESET_SHIFT)) & LCDIF_CTRL_SW_RESET_MASK) +/*! @} */ + +/*! @name DISP_PARA - Display Parameter Register */ +/*! @{ */ + +#define LCDIF_DISP_PARA_BGND_B_MASK (0xFFU) +#define LCDIF_DISP_PARA_BGND_B_SHIFT (0U) +/*! BGND_B - Background Blue component value in display Mode 1. */ +#define LCDIF_DISP_PARA_BGND_B(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DISP_PARA_BGND_B_SHIFT)) & LCDIF_DISP_PARA_BGND_B_MASK) + +#define LCDIF_DISP_PARA_BGND_G_MASK (0xFF00U) +#define LCDIF_DISP_PARA_BGND_G_SHIFT (8U) +/*! BGND_G - Background Green component value in display Mode 1. */ +#define LCDIF_DISP_PARA_BGND_G(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DISP_PARA_BGND_G_SHIFT)) & LCDIF_DISP_PARA_BGND_G_MASK) + +#define LCDIF_DISP_PARA_BGND_R_MASK (0xFF0000U) +#define LCDIF_DISP_PARA_BGND_R_SHIFT (16U) +/*! BGND_R - Background Red component value in display Mode 1. */ +#define LCDIF_DISP_PARA_BGND_R(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DISP_PARA_BGND_R_SHIFT)) & LCDIF_DISP_PARA_BGND_R_MASK) + +#define LCDIF_DISP_PARA_DISP_MODE_MASK (0x3000000U) +#define LCDIF_DISP_PARA_DISP_MODE_SHIFT (24U) +/*! DISP_MODE - LCDIF operating mode. + * 0b00..Normal mode. Panel content controlled by layer configuration. + * 0b01..display Mode1.(BGND Color Display) + * 0b10..display Mode2.(Column Color Bar) + * 0b11..display Mode3.(Row Color Bar) + */ +#define LCDIF_DISP_PARA_DISP_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DISP_PARA_DISP_MODE_SHIFT)) & LCDIF_DISP_PARA_DISP_MODE_MASK) + +#define LCDIF_DISP_PARA_LINE_PATTERN_MASK (0x3C000000U) +#define LCDIF_DISP_PARA_LINE_PATTERN_SHIFT (26U) +/*! LINE_PATTERN - LCDIF line output order. + * 0b0000..RGB/YUV. + * 0b0001..RBG. + * 0b0010..GBR. + * 0b0011..GRB/UYV. + * 0b0100..BRG. + * 0b0101..BGR. + * 0b0110..RGB555. + * 0b0111..RGB565. + * 0b1000..YUYV at [15:0]. For line pattern with "1000 - YUYV at [15:0]，Y is [15:8], U is [7:0], and next 16th bit is Y and V. + * 0b1001..UYVY at [15:0]. + * 0b1010..YVYU at [15:0]. + * 0b1011..YUYV at [15:0]. + * 0b1100..YUYV at [23:8]. + * 0b1101..UYVY at [23:8]. + * 0b1110..YVYU at [23:8]. + * 0b1111..YUYV at [23:8]. + */ +#define LCDIF_DISP_PARA_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DISP_PARA_LINE_PATTERN_SHIFT)) & LCDIF_DISP_PARA_LINE_PATTERN_MASK) + +#define LCDIF_DISP_PARA_SWAP_EN_MASK (0x40000000U) +#define LCDIF_DISP_PARA_SWAP_EN_SHIFT (30U) +/*! SWAP_EN - output data swap enable. + * 0b0..swap disable + * 0b1..swap enbale, output data will swap the high 16bits with the low 16bits. + */ +#define LCDIF_DISP_PARA_SWAP_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DISP_PARA_SWAP_EN_SHIFT)) & LCDIF_DISP_PARA_SWAP_EN_MASK) + +#define LCDIF_DISP_PARA_DISP_ON_MASK (0x80000000U) +#define LCDIF_DISP_PARA_DISP_ON_SHIFT (31U) +/*! DISP_ON - Display panel On/Off mode. + * 0b0..Display Off. + * 0b1..Display On. + */ +#define LCDIF_DISP_PARA_DISP_ON(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DISP_PARA_DISP_ON_SHIFT)) & LCDIF_DISP_PARA_DISP_ON_MASK) +/*! @} */ + +/*! @name DISP_SIZE - Display Size Register */ +/*! @{ */ + +#define LCDIF_DISP_SIZE_DELTA_X_MASK (0xFFFFU) +#define LCDIF_DISP_SIZE_DELTA_X_SHIFT (0U) +/*! DELTA_X - Sets the display size horizontal resolution in pixels. */ +#define LCDIF_DISP_SIZE_DELTA_X(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DISP_SIZE_DELTA_X_SHIFT)) & LCDIF_DISP_SIZE_DELTA_X_MASK) + +#define LCDIF_DISP_SIZE_DELTA_Y_MASK (0xFFFF0000U) +#define LCDIF_DISP_SIZE_DELTA_Y_SHIFT (16U) +/*! DELTA_Y - Sets the display size vertical resolution in pixels. */ +#define LCDIF_DISP_SIZE_DELTA_Y(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DISP_SIZE_DELTA_Y_SHIFT)) & LCDIF_DISP_SIZE_DELTA_Y_MASK) +/*! @} */ + +/*! @name HSYN_PARA - Horizontal Sync Parameter Register */ +/*! @{ */ + +#define LCDIF_HSYN_PARA_FP_H_MASK (0xFFFFU) +#define LCDIF_HSYN_PARA_FP_H_SHIFT (0U) +/*! FP_H - HSYNC front-porch pulse width (in pixel clock cycles). Pulse width has a minimum value of 1. */ +#define LCDIF_HSYN_PARA_FP_H(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_HSYN_PARA_FP_H_SHIFT)) & LCDIF_HSYN_PARA_FP_H_MASK) + +#define LCDIF_HSYN_PARA_BP_H_MASK (0xFFFF0000U) +#define LCDIF_HSYN_PARA_BP_H_SHIFT (16U) +/*! BP_H - HSYNC back-porch pulse width (in pixel clock cycles). Pulse width has a minimum value of 1. */ +#define LCDIF_HSYN_PARA_BP_H(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_HSYN_PARA_BP_H_SHIFT)) & LCDIF_HSYN_PARA_BP_H_MASK) +/*! @} */ + +/*! @name VSYN_PARA - Vertical Sync Parameter Register */ +/*! @{ */ + +#define LCDIF_VSYN_PARA_FP_V_MASK (0xFFFFU) +#define LCDIF_VSYN_PARA_FP_V_SHIFT (0U) +/*! FP_V - VSYNC front-porch pulse width (in horizontal line cycles). Pulse width has a minimum value of 1. */ +#define LCDIF_VSYN_PARA_FP_V(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VSYN_PARA_FP_V_SHIFT)) & LCDIF_VSYN_PARA_FP_V_MASK) + +#define LCDIF_VSYN_PARA_BP_V_MASK (0xFFFF0000U) +#define LCDIF_VSYN_PARA_BP_V_SHIFT (16U) +/*! BP_V - VSYNC back-porch pulse width (in horizontal line cycles). Pulse width has a minimum value of 1. */ +#define LCDIF_VSYN_PARA_BP_V(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VSYN_PARA_BP_V_SHIFT)) & LCDIF_VSYN_PARA_BP_V_MASK) +/*! @} */ + +/*! @name VSYN_HSYN_WIDTH - Vertical and Horizontal Pulse Width Parameter Register */ +/*! @{ */ + +#define LCDIF_VSYN_HSYN_WIDTH_PW_H_MASK (0xFFFFU) +#define LCDIF_VSYN_HSYN_WIDTH_PW_H_SHIFT (0U) +/*! PW_H - HSYNC active pulse width (in pixel clock cycles). Pulse width has a minimum value of 1. */ +#define LCDIF_VSYN_HSYN_WIDTH_PW_H(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VSYN_HSYN_WIDTH_PW_H_SHIFT)) & LCDIF_VSYN_HSYN_WIDTH_PW_H_MASK) + +#define LCDIF_VSYN_HSYN_WIDTH_PW_V_MASK (0xFFFF0000U) +#define LCDIF_VSYN_HSYN_WIDTH_PW_V_SHIFT (16U) +/*! PW_V - VSYNC active pulse width (in horizontal line cycles). Pulse width has a minimum value of 1. */ +#define LCDIF_VSYN_HSYN_WIDTH_PW_V(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VSYN_HSYN_WIDTH_PW_V_SHIFT)) & LCDIF_VSYN_HSYN_WIDTH_PW_V_MASK) +/*! @} */ + +/*! @name INT_STATUS_D0 - Interrupt Status Register for domain 0 */ +/*! @{ */ + +#define LCDIF_INT_STATUS_D0_VSYNC_MASK (0x1U) +#define LCDIF_INT_STATUS_D0_VSYNC_SHIFT (0U) +/*! VSYNC - Interrupt flag to indicate that the vertical synchronization phase(The beginning of a + * frame). Write a logic 1 to this field to clear this flag. + */ +#define LCDIF_INT_STATUS_D0_VSYNC(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_INT_STATUS_D0_VSYNC_SHIFT)) & LCDIF_INT_STATUS_D0_VSYNC_MASK) + +#define LCDIF_INT_STATUS_D0_UNDERRUN_MASK (0x2U) +#define LCDIF_INT_STATUS_D0_UNDERRUN_SHIFT (1U) +/*! UNDERRUN - Interrupt flag to indicate the output buffer underrun condition. Write a logic 1 to this field to clear this flag. */ +#define LCDIF_INT_STATUS_D0_UNDERRUN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_INT_STATUS_D0_UNDERRUN_SHIFT)) & LCDIF_INT_STATUS_D0_UNDERRUN_MASK) + +#define LCDIF_INT_STATUS_D0_VS_BLANK_MASK (0x4U) +#define LCDIF_INT_STATUS_D0_VS_BLANK_SHIFT (2U) +/*! VS_BLANK - Interrupt flag to indicate vertical blanking period. Write a logic 1 to this field to clear this flag. */ +#define LCDIF_INT_STATUS_D0_VS_BLANK(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_INT_STATUS_D0_VS_BLANK_SHIFT)) & LCDIF_INT_STATUS_D0_VS_BLANK_MASK) + +#define LCDIF_INT_STATUS_D0_DMA_ERR_MASK (0x100U) +#define LCDIF_INT_STATUS_D0_DMA_ERR_SHIFT (8U) +/*! DMA_ERR - Interrupt flag to indicate that which PLANE has Read Error on the AXI interface. Write + * a logic 1 to this field to clear this flag. + */ +#define LCDIF_INT_STATUS_D0_DMA_ERR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_INT_STATUS_D0_DMA_ERR_SHIFT)) & LCDIF_INT_STATUS_D0_DMA_ERR_MASK) + +#define LCDIF_INT_STATUS_D0_DMA_DONE_MASK (0x10000U) +#define LCDIF_INT_STATUS_D0_DMA_DONE_SHIFT (16U) +/*! DMA_DONE - Interrupt flag to indicate that which PLANE has fetched the last pixel from memory. + * Write a logic 1 to this field to clear this flag. + */ +#define LCDIF_INT_STATUS_D0_DMA_DONE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_INT_STATUS_D0_DMA_DONE_SHIFT)) & LCDIF_INT_STATUS_D0_DMA_DONE_MASK) + +#define LCDIF_INT_STATUS_D0_FIFO_EMPTY_MASK (0x1000000U) +#define LCDIF_INT_STATUS_D0_FIFO_EMPTY_SHIFT (24U) +/*! FIFO_EMPTY - Interrupt flag to indicate that which FIFO in the pixel blending underflowed. Write + * a logic 1 to this field to clear this flag. + */ +#define LCDIF_INT_STATUS_D0_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_INT_STATUS_D0_FIFO_EMPTY_SHIFT)) & LCDIF_INT_STATUS_D0_FIFO_EMPTY_MASK) +/*! @} */ + +/*! @name INT_ENABLE_D0 - Interrupt Enable Register for domain 0 */ +/*! @{ */ + +#define LCDIF_INT_ENABLE_D0_VSYNC_EN_MASK (0x1U) +#define LCDIF_INT_ENABLE_D0_VSYNC_EN_SHIFT (0U) +/*! VSYNC_EN - Enable Interrupt flag to indicate that the vertical synchronization phase(The beginning of a frame). */ +#define LCDIF_INT_ENABLE_D0_VSYNC_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_INT_ENABLE_D0_VSYNC_EN_SHIFT)) & LCDIF_INT_ENABLE_D0_VSYNC_EN_MASK) + +#define LCDIF_INT_ENABLE_D0_UNDERRUN_EN_MASK (0x2U) +#define LCDIF_INT_ENABLE_D0_UNDERRUN_EN_SHIFT (1U) +/*! UNDERRUN_EN - Enable Interrupt flag to indicate the output buffer underrun condition. */ +#define LCDIF_INT_ENABLE_D0_UNDERRUN_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_INT_ENABLE_D0_UNDERRUN_EN_SHIFT)) & LCDIF_INT_ENABLE_D0_UNDERRUN_EN_MASK) + +#define LCDIF_INT_ENABLE_D0_VS_BLANK_EN_MASK (0x4U) +#define LCDIF_INT_ENABLE_D0_VS_BLANK_EN_SHIFT (2U) +/*! VS_BLANK_EN - Enable Interrupt flag to indicate vertical blanking period. */ +#define LCDIF_INT_ENABLE_D0_VS_BLANK_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_INT_ENABLE_D0_VS_BLANK_EN_SHIFT)) & LCDIF_INT_ENABLE_D0_VS_BLANK_EN_MASK) + +#define LCDIF_INT_ENABLE_D0_DMA_ERR_EN_MASK (0x100U) +#define LCDIF_INT_ENABLE_D0_DMA_ERR_EN_SHIFT (8U) +/*! DMA_ERR_EN - Enable Interrupt flag to indicate that which PLANE has Read Error on the AXI interface. */ +#define LCDIF_INT_ENABLE_D0_DMA_ERR_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_INT_ENABLE_D0_DMA_ERR_EN_SHIFT)) & LCDIF_INT_ENABLE_D0_DMA_ERR_EN_MASK) + +#define LCDIF_INT_ENABLE_D0_DMA_DONE_EN_MASK (0x10000U) +#define LCDIF_INT_ENABLE_D0_DMA_DONE_EN_SHIFT (16U) +/*! DMA_DONE_EN - Enable Interrupt flag to indicate that which PLANE has fetched the last pixel from memory. */ +#define LCDIF_INT_ENABLE_D0_DMA_DONE_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_INT_ENABLE_D0_DMA_DONE_EN_SHIFT)) & LCDIF_INT_ENABLE_D0_DMA_DONE_EN_MASK) + +#define LCDIF_INT_ENABLE_D0_FIFO_EMPTY_EN_MASK (0x1000000U) +#define LCDIF_INT_ENABLE_D0_FIFO_EMPTY_EN_SHIFT (24U) +/*! FIFO_EMPTY_EN - Enable Interrupt flag to indicate that which FIFO in the pixel blending underflowed. */ +#define LCDIF_INT_ENABLE_D0_FIFO_EMPTY_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_INT_ENABLE_D0_FIFO_EMPTY_EN_SHIFT)) & LCDIF_INT_ENABLE_D0_FIFO_EMPTY_EN_MASK) +/*! @} */ + +/*! @name INT_STATUS_D1 - Interrupt Status Register for domain 0 */ +/*! @{ */ + +#define LCDIF_INT_STATUS_D1_PLANE_PANIC_MASK (0x1U) +#define LCDIF_INT_STATUS_D1_PLANE_PANIC_SHIFT (0U) +/*! PLANE_PANIC - Plane panic to indicate that which FIFO reaches the panic threshold. Write a logic 1 to this field to clear this flag. */ +#define LCDIF_INT_STATUS_D1_PLANE_PANIC(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_INT_STATUS_D1_PLANE_PANIC_SHIFT)) & LCDIF_INT_STATUS_D1_PLANE_PANIC_MASK) +/*! @} */ + +/*! @name INT_ENABLE_D1 - Interrupt Enable Register for domain 0 */ +/*! @{ */ + +#define LCDIF_INT_ENABLE_D1_PLANE_PANIC_EN_MASK (0x1U) +#define LCDIF_INT_ENABLE_D1_PLANE_PANIC_EN_SHIFT (0U) +/*! PLANE_PANIC_EN - Enable Interrupt flag to indicate that which FIFO in the pixel blending underflowed. */ +#define LCDIF_INT_ENABLE_D1_PLANE_PANIC_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_INT_ENABLE_D1_PLANE_PANIC_EN_SHIFT)) & LCDIF_INT_ENABLE_D1_PLANE_PANIC_EN_MASK) +/*! @} */ + +/*! @name CTRLDESCL_1 - Control Descriptor Layer Register 1 */ +/*! @{ */ + +#define LCDIF_CTRLDESCL_1_WIDTH_MASK (0xFFFFU) +#define LCDIF_CTRLDESCL_1_WIDTH_SHIFT (0U) +/*! WIDTH - Width of the layer in pixels. */ +#define LCDIF_CTRLDESCL_1_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRLDESCL_1_WIDTH_SHIFT)) & LCDIF_CTRLDESCL_1_WIDTH_MASK) + +#define LCDIF_CTRLDESCL_1_HEIGHT_MASK (0xFFFF0000U) +#define LCDIF_CTRLDESCL_1_HEIGHT_SHIFT (16U) +/*! HEIGHT - Height of the layer in pixels. */ +#define LCDIF_CTRLDESCL_1_HEIGHT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRLDESCL_1_HEIGHT_SHIFT)) & LCDIF_CTRLDESCL_1_HEIGHT_MASK) +/*! @} */ + +/* The count of LCDIF_CTRLDESCL_1 */ +#define LCDIF_CTRLDESCL_1_COUNT (1U) + +/*! @name CTRLDESCL_3 - Control Descriptor Layer Register 3 */ +/*! @{ */ + +#define LCDIF_CTRLDESCL_3_PITCH_MASK (0xFFFFU) +#define LCDIF_CTRLDESCL_3_PITCH_SHIFT (0U) +/*! PITCH - Number of bytes between 2 vertically adjacent pixels in system memory. Byte granularity + * is supported, but SW should align to 64B boundary. + */ +#define LCDIF_CTRLDESCL_3_PITCH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRLDESCL_3_PITCH_SHIFT)) & LCDIF_CTRLDESCL_3_PITCH_MASK) + +#define LCDIF_CTRLDESCL_3_T_SIZE_MASK (0x30000U) +#define LCDIF_CTRLDESCL_3_T_SIZE_SHIFT (16U) +/*! T_SIZE - Transaction Size */ +#define LCDIF_CTRLDESCL_3_T_SIZE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRLDESCL_3_T_SIZE_SHIFT)) & LCDIF_CTRLDESCL_3_T_SIZE_MASK) + +#define LCDIF_CTRLDESCL_3_P_SIZE_MASK (0x700000U) +#define LCDIF_CTRLDESCL_3_P_SIZE_SHIFT (20U) +/*! P_SIZE - Payload size. */ +#define LCDIF_CTRLDESCL_3_P_SIZE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRLDESCL_3_P_SIZE_SHIFT)) & LCDIF_CTRLDESCL_3_P_SIZE_MASK) +/*! @} */ + +/* The count of LCDIF_CTRLDESCL_3 */ +#define LCDIF_CTRLDESCL_3_COUNT (1U) + +/*! @name CTRLDESCL_LOW_4 - Control Descriptor Layer Register 4 */ +/*! @{ */ + +#define LCDIF_CTRLDESCL_LOW_4_ADDR_LOW_MASK (0xFFFFFFFFU) +#define LCDIF_CTRLDESCL_LOW_4_ADDR_LOW_SHIFT (0U) +/*! ADDR_LOW - Address of layer data in the memory. The address programmed should be 128-bit aligned. */ +#define LCDIF_CTRLDESCL_LOW_4_ADDR_LOW(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRLDESCL_LOW_4_ADDR_LOW_SHIFT)) & LCDIF_CTRLDESCL_LOW_4_ADDR_LOW_MASK) +/*! @} */ + +/* The count of LCDIF_CTRLDESCL_LOW_4 */ +#define LCDIF_CTRLDESCL_LOW_4_COUNT (1U) + +/*! @name CTRLDESCL_HIGH_4 - Control Descriptor Layer Register 4 */ +/*! @{ */ + +#define LCDIF_CTRLDESCL_HIGH_4_ADDR_HIGH_MASK (0xFU) +#define LCDIF_CTRLDESCL_HIGH_4_ADDR_HIGH_SHIFT (0U) +/*! ADDR_HIGH - Address of layer data in the memory. */ +#define LCDIF_CTRLDESCL_HIGH_4_ADDR_HIGH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRLDESCL_HIGH_4_ADDR_HIGH_SHIFT)) & LCDIF_CTRLDESCL_HIGH_4_ADDR_HIGH_MASK) +/*! @} */ + +/* The count of LCDIF_CTRLDESCL_HIGH_4 */ +#define LCDIF_CTRLDESCL_HIGH_4_COUNT (1U) + +/*! @name CTRLDESCL_5 - Control Descriptor Layer Register 5 */ +/*! @{ */ + +#define LCDIF_CTRLDESCL_5_YUV_FORMAT_MASK (0xC000U) +#define LCDIF_CTRLDESCL_5_YUV_FORMAT_SHIFT (14U) +/*! YUV_FORMAT - The YUV422 input format selection. + * 0b00..The YUV422 32bit memory is {Y2,V1,Y1,U1} + * 0b01..The YUV422 32bit memory is {Y2,U1,Y1,V1} + * 0b10..The YUV422 32bit memory is {V1,Y2,U1,Y1} + * 0b11..The YUV422 32bit memory is {U1,Y2,V1,Y1} + */ +#define LCDIF_CTRLDESCL_5_YUV_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRLDESCL_5_YUV_FORMAT_SHIFT)) & LCDIF_CTRLDESCL_5_YUV_FORMAT_MASK) + +#define LCDIF_CTRLDESCL_5_BPP_MASK (0xF000000U) +#define LCDIF_CTRLDESCL_5_BPP_SHIFT (24U) +/*! BPP - Layer encoding format (bit per pixel) + * 0b0100..16 bpp (RGB565) + * 0b0101..16 bpp (ARGB1555) + * 0b0110..16 bpp (ARGB4444) + * 0b0111..YCbCr422 + * 0b1000..24 bpp (RGB888) + * 0b1001..32 bpp (ARGB8888) + * 0b1010..32 bpp (ABGR8888) + */ +#define LCDIF_CTRLDESCL_5_BPP(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRLDESCL_5_BPP_SHIFT)) & LCDIF_CTRLDESCL_5_BPP_MASK) + +#define LCDIF_CTRLDESCL_5_SHADOW_LOAD_EN_MASK (0x40000000U) +#define LCDIF_CTRLDESCL_5_SHADOW_LOAD_EN_SHIFT (30U) +/*! SHADOW_LOAD_EN - Shadow Load Enable */ +#define LCDIF_CTRLDESCL_5_SHADOW_LOAD_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRLDESCL_5_SHADOW_LOAD_EN_SHIFT)) & LCDIF_CTRLDESCL_5_SHADOW_LOAD_EN_MASK) + +#define LCDIF_CTRLDESCL_5_EN_MASK (0x80000000U) +#define LCDIF_CTRLDESCL_5_EN_SHIFT (31U) +/*! EN - Enable the layer for DMA. + * 0b0..OFF + * 0b1..ON + */ +#define LCDIF_CTRLDESCL_5_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRLDESCL_5_EN_SHIFT)) & LCDIF_CTRLDESCL_5_EN_MASK) +/*! @} */ + +/* The count of LCDIF_CTRLDESCL_5 */ +#define LCDIF_CTRLDESCL_5_COUNT (1U) + +/*! @name CSC_CTRL - Color Space Conversion Ctrl Register */ +/*! @{ */ + +#define LCDIF_CSC_CTRL_BYPASS_MASK (0x1U) +#define LCDIF_CSC_CTRL_BYPASS_SHIFT (0U) +/*! BYPASS - This bit controls whether the pixels entering the CSC2 unit get converted or not. */ +#define LCDIF_CSC_CTRL_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_CTRL_BYPASS_SHIFT)) & LCDIF_CSC_CTRL_BYPASS_MASK) + +#define LCDIF_CSC_CTRL_CSC_MODE_MASK (0x6U) +#define LCDIF_CSC_CTRL_CSC_MODE_SHIFT (1U) +/*! CSC_MODE - This field controls how the CSC unit operates on pixels when the CSC is not bypassed. + * 0b00..Convert from YUV to RGB. + * 0b01..Convert from YCbCr to RGB. + * 0b10..Reserved + * 0b11..Convert from RGB to YCbCr. + */ +#define LCDIF_CSC_CTRL_CSC_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_CTRL_CSC_MODE_SHIFT)) & LCDIF_CSC_CTRL_CSC_MODE_MASK) +/*! @} */ + +/* The count of LCDIF_CSC_CTRL */ +#define LCDIF_CSC_CTRL_COUNT (1U) + +/*! @name CSC_COEF0 - Color Space Conversion Coefficient Register 0 */ +/*! @{ */ + +#define LCDIF_CSC_COEF0_A1_MASK (0x7FFU) +#define LCDIF_CSC_COEF0_A1_SHIFT (0U) +/*! A1 - Two's complement coefficient offset. This coefficient has a sign bit, 2 bits integer, and 8 + * bits of fraction as ###.####_####. + */ +#define LCDIF_CSC_COEF0_A1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_COEF0_A1_SHIFT)) & LCDIF_CSC_COEF0_A1_MASK) + +#define LCDIF_CSC_COEF0_A2_MASK (0x7FF0000U) +#define LCDIF_CSC_COEF0_A2_SHIFT (16U) +/*! A2 - Two's complement coefficient offset. This coefficient has a sign bit, 2 bits integer, and 8 + * bits of fraction as ###.####_####. + */ +#define LCDIF_CSC_COEF0_A2(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_COEF0_A2_SHIFT)) & LCDIF_CSC_COEF0_A2_MASK) +/*! @} */ + +/* The count of LCDIF_CSC_COEF0 */ +#define LCDIF_CSC_COEF0_COUNT (1U) + +/*! @name CSC_COEF1 - Color Space Conversion Coefficient Register 1 */ +/*! @{ */ + +#define LCDIF_CSC_COEF1_A3_MASK (0x7FFU) +#define LCDIF_CSC_COEF1_A3_SHIFT (0U) +/*! A3 - Two's complement coefficient offset. This coefficient has a sign bit, 2 bits integer, and 8 + * bits of fraction as ###.####_####. + */ +#define LCDIF_CSC_COEF1_A3(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_COEF1_A3_SHIFT)) & LCDIF_CSC_COEF1_A3_MASK) + +#define LCDIF_CSC_COEF1_B1_MASK (0x7FF0000U) +#define LCDIF_CSC_COEF1_B1_SHIFT (16U) +/*! B1 - Two's complement coefficient offset. This coefficient has a sign bit, 2 bits integer, and 8 + * bits of fraction as ###.####_####. + */ +#define LCDIF_CSC_COEF1_B1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_COEF1_B1_SHIFT)) & LCDIF_CSC_COEF1_B1_MASK) +/*! @} */ + +/* The count of LCDIF_CSC_COEF1 */ +#define LCDIF_CSC_COEF1_COUNT (1U) + +/*! @name CSC_COEF2 - Color Space Conversion Coefficient Register 2 */ +/*! @{ */ + +#define LCDIF_CSC_COEF2_B2_MASK (0x7FFU) +#define LCDIF_CSC_COEF2_B2_SHIFT (0U) +/*! B2 - Two's complement coefficient offset. This coefficient has a sign bit, 2 bits integer, and 8 + * bits of fraction as ###.####_####. + */ +#define LCDIF_CSC_COEF2_B2(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_COEF2_B2_SHIFT)) & LCDIF_CSC_COEF2_B2_MASK) + +#define LCDIF_CSC_COEF2_B3_MASK (0x7FF0000U) +#define LCDIF_CSC_COEF2_B3_SHIFT (16U) +/*! B3 - Two's complement coefficient offset. This coefficient has a sign bit, 2 bits integer, and 8 + * bits of fraction as ###.####_####. + */ +#define LCDIF_CSC_COEF2_B3(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_COEF2_B3_SHIFT)) & LCDIF_CSC_COEF2_B3_MASK) +/*! @} */ + +/* The count of LCDIF_CSC_COEF2 */ +#define LCDIF_CSC_COEF2_COUNT (1U) + +/*! @name CSC_COEF3 - Color Space Conversion Coefficient Register 3 */ +/*! @{ */ + +#define LCDIF_CSC_COEF3_C1_MASK (0x7FFU) +#define LCDIF_CSC_COEF3_C1_SHIFT (0U) +/*! C1 - Two's complement coefficient offset. This coefficient has a sign bit, 2 bits integer, and 8 + * bits of fraction as ###.####_####. + */ +#define LCDIF_CSC_COEF3_C1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_COEF3_C1_SHIFT)) & LCDIF_CSC_COEF3_C1_MASK) + +#define LCDIF_CSC_COEF3_C2_MASK (0x7FF0000U) +#define LCDIF_CSC_COEF3_C2_SHIFT (16U) +/*! C2 - Two's complement coefficient offset. This coefficient has a sign bit, 2 bits integer, and 8 + * bits of fraction as ###.####_####. + */ +#define LCDIF_CSC_COEF3_C2(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_COEF3_C2_SHIFT)) & LCDIF_CSC_COEF3_C2_MASK) +/*! @} */ + +/* The count of LCDIF_CSC_COEF3 */ +#define LCDIF_CSC_COEF3_COUNT (1U) + +/*! @name CSC_COEF4 - Color Space Conversion Coefficient Register 4 */ +/*! @{ */ + +#define LCDIF_CSC_COEF4_C3_MASK (0x7FFU) +#define LCDIF_CSC_COEF4_C3_SHIFT (0U) +/*! C3 - Two's complement coefficient offset. This coefficient has a sign bit, 2 bits integer, and 8 + * bits of fraction as ###.####_####. + */ +#define LCDIF_CSC_COEF4_C3(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_COEF4_C3_SHIFT)) & LCDIF_CSC_COEF4_C3_MASK) + +#define LCDIF_CSC_COEF4_D1_MASK (0x1FF0000U) +#define LCDIF_CSC_COEF4_D1_SHIFT (16U) +/*! D1 - Two's complement D1 coefficient integer offset to be added. */ +#define LCDIF_CSC_COEF4_D1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_COEF4_D1_SHIFT)) & LCDIF_CSC_COEF4_D1_MASK) +/*! @} */ + +/* The count of LCDIF_CSC_COEF4 */ +#define LCDIF_CSC_COEF4_COUNT (1U) + +/*! @name CSC_COEF5 - Color Space Conversion Coefficient Register 0 */ +/*! @{ */ + +#define LCDIF_CSC_COEF5_D2_MASK (0x1FFU) +#define LCDIF_CSC_COEF5_D2_SHIFT (0U) +/*! D2 - Two's complement D2 coefficient integer offset to be added. */ +#define LCDIF_CSC_COEF5_D2(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_COEF5_D2_SHIFT)) & LCDIF_CSC_COEF5_D2_MASK) + +#define LCDIF_CSC_COEF5_D3_MASK (0x1FF0000U) +#define LCDIF_CSC_COEF5_D3_SHIFT (16U) +/*! D3 - Two's complement D3 coefficient integer offset to be added. */ +#define LCDIF_CSC_COEF5_D3(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_COEF5_D3_SHIFT)) & LCDIF_CSC_COEF5_D3_MASK) +/*! @} */ + +/* The count of LCDIF_CSC_COEF5 */ +#define LCDIF_CSC_COEF5_COUNT (1U) + +/*! @name PANIC_THRES - Memory request priority threshold register */ +/*! @{ */ + +#define LCDIF_PANIC_THRES_PANIC_THRES_HIGH_MASK (0x1FFU) +#define LCDIF_PANIC_THRES_PANIC_THRES_HIGH_SHIFT (0U) +/*! PANIC_THRES_HIGH - Panic Threshold High Value */ +#define LCDIF_PANIC_THRES_PANIC_THRES_HIGH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PANIC_THRES_PANIC_THRES_HIGH_SHIFT)) & LCDIF_PANIC_THRES_PANIC_THRES_HIGH_MASK) + +#define LCDIF_PANIC_THRES_PANIC_THRES_LOW_MASK (0x1FF0000U) +#define LCDIF_PANIC_THRES_PANIC_THRES_LOW_SHIFT (16U) +/*! PANIC_THRES_LOW - Panic Threshold Low Value */ +#define LCDIF_PANIC_THRES_PANIC_THRES_LOW(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PANIC_THRES_PANIC_THRES_LOW_SHIFT)) & LCDIF_PANIC_THRES_PANIC_THRES_LOW_MASK) +/*! @} */ + +/* The count of LCDIF_PANIC_THRES */ +#define LCDIF_PANIC_THRES_COUNT (1U) + + +/*! + * @} + */ /* end of group LCDIF_Register_Masks */ + + +/* LCDIF - Peripheral instance base addresses */ +/** Peripheral LCDIF base address */ +#define LCDIF_BASE (0x4AE30000u) +/** Peripheral LCDIF base pointer */ +#define LCDIF ((LCDIF_Type *)LCDIF_BASE) +/** Array initializer of LCDIF peripheral base addresses */ +#define LCDIF_BASE_ADDRS { LCDIF_BASE } +/** Array initializer of LCDIF peripheral base pointers */ +#define LCDIF_BASE_PTRS { LCDIF } + +/*! + * @} + */ /* end of group LCDIF_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- LPI2C Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup LPI2C_Peripheral_Access_Layer LPI2C Peripheral Access Layer + * @{ + */ + +/** LPI2C - Register Layout Typedef */ +typedef struct { + __I uint32_t VERID; /**< Version ID, offset: 0x0 */ + __I uint32_t PARAM; /**< Parameter, offset: 0x4 */ + uint8_t RESERVED_0[8]; + __IO uint32_t MCR; /**< Controller Control, offset: 0x10 */ + __IO uint32_t MSR; /**< Controller Status, offset: 0x14 */ + __IO uint32_t MIER; /**< Controller Interrupt Enable, offset: 0x18 */ + __IO uint32_t MDER; /**< Controller DMA Enable, offset: 0x1C */ + __IO uint32_t MCFGR0; /**< Controller Configuration 0, offset: 0x20 */ + __IO uint32_t MCFGR1; /**< Controller Configuration 1, offset: 0x24 */ + __IO uint32_t MCFGR2; /**< Controller Configuration 2, offset: 0x28 */ + __IO uint32_t MCFGR3; /**< Controller Configuration 3, offset: 0x2C */ + uint8_t RESERVED_1[16]; + __IO uint32_t MDMR; /**< Controller Data Match, offset: 0x40 */ + uint8_t RESERVED_2[4]; + __IO uint32_t MCCR0; /**< Controller Clock Configuration 0, offset: 0x48 */ + uint8_t RESERVED_3[4]; + __IO uint32_t MCCR1; /**< Controller Clock Configuration 1, offset: 0x50 */ + uint8_t RESERVED_4[4]; + __IO uint32_t MFCR; /**< Controller FIFO Control, offset: 0x58 */ + __I uint32_t MFSR; /**< Controller FIFO Status, offset: 0x5C */ + __O uint32_t MTDR; /**< Controller Transmit Data, offset: 0x60 */ + uint8_t RESERVED_5[12]; + __I uint32_t MRDR; /**< Controller Receive Data, offset: 0x70 */ + uint8_t RESERVED_6[4]; + __I uint32_t MRDROR; /**< Controller Receive Data Read Only, offset: 0x78 */ + uint8_t RESERVED_7[148]; + __IO uint32_t SCR; /**< Target Control, offset: 0x110 */ + __IO uint32_t SSR; /**< Target Status, offset: 0x114 */ + __IO uint32_t SIER; /**< Target Interrupt Enable, offset: 0x118 */ + __IO uint32_t SDER; /**< Target DMA Enable, offset: 0x11C */ + __IO uint32_t SCFGR0; /**< Target Configuration 0, offset: 0x120 */ + __IO uint32_t SCFGR1; /**< Target Configuration 1, offset: 0x124 */ + __IO uint32_t SCFGR2; /**< Target Configuration 2, offset: 0x128 */ + uint8_t RESERVED_8[20]; + __IO uint32_t SAMR; /**< Target Address Match, offset: 0x140 */ + uint8_t RESERVED_9[12]; + __I uint32_t SASR; /**< Target Address Status, offset: 0x150 */ + __IO uint32_t STAR; /**< Target Transmit ACK, offset: 0x154 */ + uint8_t RESERVED_10[8]; + __O uint32_t STDR; /**< Target Transmit Data, offset: 0x160 */ + uint8_t RESERVED_11[12]; + __I uint32_t SRDR; /**< Target Receive Data, offset: 0x170 */ + uint8_t RESERVED_12[4]; + __I uint32_t SRDROR; /**< Target Receive Data Read Only, offset: 0x178 */ + uint8_t RESERVED_13[132]; + __O uint32_t MTCBR[128]; /**< Controller Transmit Command Burst, array offset: 0x200, array step: 0x4 */ + __O uint32_t MTDBR[256]; /**< Transmit Data Burst, array offset: 0x400, array step: 0x4 */ +} LPI2C_Type; + +/* ---------------------------------------------------------------------------- + -- LPI2C Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup LPI2C_Register_Masks LPI2C Register Masks + * @{ + */ + +/*! @name VERID - Version ID */ +/*! @{ */ + +#define LPI2C_VERID_FEATURE_MASK (0xFFFFU) +#define LPI2C_VERID_FEATURE_SHIFT (0U) +/*! FEATURE - Feature Specification Number + * 0b0000000000000010..Controller only, with standard feature set + * 0b0000000000000011..Controller and target, with standard feature set + */ +#define LPI2C_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_FEATURE_SHIFT)) & LPI2C_VERID_FEATURE_MASK) + +#define LPI2C_VERID_MINOR_MASK (0xFF0000U) +#define LPI2C_VERID_MINOR_SHIFT (16U) +/*! MINOR - Minor Version Number */ +#define LPI2C_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_MINOR_SHIFT)) & LPI2C_VERID_MINOR_MASK) + +#define LPI2C_VERID_MAJOR_MASK (0xFF000000U) +#define LPI2C_VERID_MAJOR_SHIFT (24U) +/*! MAJOR - Major Version Number */ +#define LPI2C_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_MAJOR_SHIFT)) & LPI2C_VERID_MAJOR_MASK) +/*! @} */ + +/*! @name PARAM - Parameter */ +/*! @{ */ + +#define LPI2C_PARAM_MTXFIFO_MASK (0xFU) +#define LPI2C_PARAM_MTXFIFO_SHIFT (0U) +/*! MTXFIFO - Controller Transmit FIFO Size */ +#define LPI2C_PARAM_MTXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_PARAM_MTXFIFO_SHIFT)) & LPI2C_PARAM_MTXFIFO_MASK) + +#define LPI2C_PARAM_MRXFIFO_MASK (0xF00U) +#define LPI2C_PARAM_MRXFIFO_SHIFT (8U) +/*! MRXFIFO - Controller Receive FIFO Size */ +#define LPI2C_PARAM_MRXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_PARAM_MRXFIFO_SHIFT)) & LPI2C_PARAM_MRXFIFO_MASK) +/*! @} */ + +/*! @name MCR - Controller Control */ +/*! @{ */ + +#define LPI2C_MCR_MEN_MASK (0x1U) +#define LPI2C_MCR_MEN_SHIFT (0U) +/*! MEN - Controller Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_MCR_MEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_MEN_SHIFT)) & LPI2C_MCR_MEN_MASK) + +#define LPI2C_MCR_RST_MASK (0x2U) +#define LPI2C_MCR_RST_SHIFT (1U) +/*! RST - Software Reset + * 0b0..No effect + * 0b1..Reset + */ +#define LPI2C_MCR_RST(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_RST_SHIFT)) & LPI2C_MCR_RST_MASK) + +#define LPI2C_MCR_DOZEN_MASK (0x4U) +#define LPI2C_MCR_DOZEN_SHIFT (2U) +/*! DOZEN - Doze Mode Enable + * 0b0..Enable + * 0b1..Disable + */ +#define LPI2C_MCR_DOZEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_DOZEN_SHIFT)) & LPI2C_MCR_DOZEN_MASK) + +#define LPI2C_MCR_DBGEN_MASK (0x8U) +#define LPI2C_MCR_DBGEN_SHIFT (3U) +/*! DBGEN - Debug Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_MCR_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_DBGEN_SHIFT)) & LPI2C_MCR_DBGEN_MASK) + +#define LPI2C_MCR_RTF_MASK (0x100U) +#define LPI2C_MCR_RTF_SHIFT (8U) +/*! RTF - Reset Transmit FIFO + * 0b0..No effect + * 0b1..Reset transmit FIFO + */ +#define LPI2C_MCR_RTF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_RTF_SHIFT)) & LPI2C_MCR_RTF_MASK) + +#define LPI2C_MCR_RRF_MASK (0x200U) +#define LPI2C_MCR_RRF_SHIFT (9U) +/*! RRF - Reset Receive FIFO + * 0b0..No effect + * 0b1..Reset receive FIFO + */ +#define LPI2C_MCR_RRF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_RRF_SHIFT)) & LPI2C_MCR_RRF_MASK) +/*! @} */ + +/*! @name MSR - Controller Status */ +/*! @{ */ + +#define LPI2C_MSR_TDF_MASK (0x1U) +#define LPI2C_MSR_TDF_SHIFT (0U) +/*! TDF - Transmit Data Flag + * 0b0..Transmit data not requested + * 0b1..Transmit data requested + */ +#define LPI2C_MSR_TDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_TDF_SHIFT)) & LPI2C_MSR_TDF_MASK) + +#define LPI2C_MSR_RDF_MASK (0x2U) +#define LPI2C_MSR_RDF_SHIFT (1U) +/*! RDF - Receive Data Flag + * 0b0..Receive data not ready + * 0b1..Receive data ready + */ +#define LPI2C_MSR_RDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_RDF_SHIFT)) & LPI2C_MSR_RDF_MASK) + +#define LPI2C_MSR_EPF_MASK (0x100U) +#define LPI2C_MSR_EPF_SHIFT (8U) +/*! EPF - End Packet Flag + * 0b0..No Stop or repeated Start generated + * 0b0..No effect + * 0b1..Stop or repeated Start generated + * 0b1..Clear the flag + */ +#define LPI2C_MSR_EPF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_EPF_SHIFT)) & LPI2C_MSR_EPF_MASK) + +#define LPI2C_MSR_SDF_MASK (0x200U) +#define LPI2C_MSR_SDF_SHIFT (9U) +/*! SDF - Stop Detect Flag + * 0b0..No Stop condition generated + * 0b0..No effect + * 0b1..Stop condition generated + * 0b1..Clear the flag + */ +#define LPI2C_MSR_SDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_SDF_SHIFT)) & LPI2C_MSR_SDF_MASK) + +#define LPI2C_MSR_NDF_MASK (0x400U) +#define LPI2C_MSR_NDF_SHIFT (10U) +/*! NDF - NACK Detect Flag + * 0b0..No unexpected NACK detected + * 0b0..No effect + * 0b1..Unexpected NACK detected + * 0b1..Clear the flag + */ +#define LPI2C_MSR_NDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_NDF_SHIFT)) & LPI2C_MSR_NDF_MASK) + +#define LPI2C_MSR_ALF_MASK (0x800U) +#define LPI2C_MSR_ALF_SHIFT (11U) +/*! ALF - Arbitration Lost Flag + * 0b0..Controller did not lose arbitration + * 0b0..No effect + * 0b1..Controller lost arbitration + * 0b1..Clear the flag + */ +#define LPI2C_MSR_ALF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_ALF_SHIFT)) & LPI2C_MSR_ALF_MASK) + +#define LPI2C_MSR_FEF_MASK (0x1000U) +#define LPI2C_MSR_FEF_SHIFT (12U) +/*! FEF - FIFO Error Flag + * 0b0..No FIFO error + * 0b0..No effect + * 0b1..FIFO error + * 0b1..Clear the flag + */ +#define LPI2C_MSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_FEF_SHIFT)) & LPI2C_MSR_FEF_MASK) + +#define LPI2C_MSR_PLTF_MASK (0x2000U) +#define LPI2C_MSR_PLTF_SHIFT (13U) +/*! PLTF - Pin Low Timeout Flag + * 0b0..Pin low timeout did not occur + * 0b0..No effect + * 0b1..Pin low timeout occurred + * 0b1..Clear the flag + */ +#define LPI2C_MSR_PLTF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_PLTF_SHIFT)) & LPI2C_MSR_PLTF_MASK) + +#define LPI2C_MSR_DMF_MASK (0x4000U) +#define LPI2C_MSR_DMF_SHIFT (14U) +/*! DMF - Data Match Flag + * 0b0..Matching data not received + * 0b0..No effect + * 0b1..Matching data received + * 0b1..Clear the flag + */ +#define LPI2C_MSR_DMF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_DMF_SHIFT)) & LPI2C_MSR_DMF_MASK) + +#define LPI2C_MSR_STF_MASK (0x8000U) +#define LPI2C_MSR_STF_SHIFT (15U) +/*! STF - Start Flag + * 0b0..Start condition not detected + * 0b0..No effect + * 0b1..Start condition detected + * 0b1..Clear the flag + */ +#define LPI2C_MSR_STF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_STF_SHIFT)) & LPI2C_MSR_STF_MASK) + +#define LPI2C_MSR_MBF_MASK (0x1000000U) +#define LPI2C_MSR_MBF_SHIFT (24U) +/*! MBF - Controller Busy Flag + * 0b0..Idle + * 0b1..Busy + */ +#define LPI2C_MSR_MBF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_MBF_SHIFT)) & LPI2C_MSR_MBF_MASK) + +#define LPI2C_MSR_BBF_MASK (0x2000000U) +#define LPI2C_MSR_BBF_SHIFT (25U) +/*! BBF - Bus Busy Flag + * 0b0..Idle + * 0b1..Busy + */ +#define LPI2C_MSR_BBF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_BBF_SHIFT)) & LPI2C_MSR_BBF_MASK) +/*! @} */ + +/*! @name MIER - Controller Interrupt Enable */ +/*! @{ */ + +#define LPI2C_MIER_TDIE_MASK (0x1U) +#define LPI2C_MIER_TDIE_SHIFT (0U) +/*! TDIE - Transmit Data Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_MIER_TDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_TDIE_SHIFT)) & LPI2C_MIER_TDIE_MASK) + +#define LPI2C_MIER_RDIE_MASK (0x2U) +#define LPI2C_MIER_RDIE_SHIFT (1U) +/*! RDIE - Receive Data Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_MIER_RDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_RDIE_SHIFT)) & LPI2C_MIER_RDIE_MASK) + +#define LPI2C_MIER_EPIE_MASK (0x100U) +#define LPI2C_MIER_EPIE_SHIFT (8U) +/*! EPIE - End Packet Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_MIER_EPIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_EPIE_SHIFT)) & LPI2C_MIER_EPIE_MASK) + +#define LPI2C_MIER_SDIE_MASK (0x200U) +#define LPI2C_MIER_SDIE_SHIFT (9U) +/*! SDIE - Stop Detect Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_MIER_SDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_SDIE_SHIFT)) & LPI2C_MIER_SDIE_MASK) + +#define LPI2C_MIER_NDIE_MASK (0x400U) +#define LPI2C_MIER_NDIE_SHIFT (10U) +/*! NDIE - NACK Detect Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_MIER_NDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_NDIE_SHIFT)) & LPI2C_MIER_NDIE_MASK) + +#define LPI2C_MIER_ALIE_MASK (0x800U) +#define LPI2C_MIER_ALIE_SHIFT (11U) +/*! ALIE - Arbitration Lost Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_MIER_ALIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_ALIE_SHIFT)) & LPI2C_MIER_ALIE_MASK) + +#define LPI2C_MIER_FEIE_MASK (0x1000U) +#define LPI2C_MIER_FEIE_SHIFT (12U) +/*! FEIE - FIFO Error Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_MIER_FEIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_FEIE_SHIFT)) & LPI2C_MIER_FEIE_MASK) + +#define LPI2C_MIER_PLTIE_MASK (0x2000U) +#define LPI2C_MIER_PLTIE_SHIFT (13U) +/*! PLTIE - Pin Low Timeout Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_MIER_PLTIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_PLTIE_SHIFT)) & LPI2C_MIER_PLTIE_MASK) + +#define LPI2C_MIER_DMIE_MASK (0x4000U) +#define LPI2C_MIER_DMIE_SHIFT (14U) +/*! DMIE - Data Match Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_MIER_DMIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_DMIE_SHIFT)) & LPI2C_MIER_DMIE_MASK) + +#define LPI2C_MIER_STIE_MASK (0x8000U) +#define LPI2C_MIER_STIE_SHIFT (15U) +/*! STIE - Start Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_MIER_STIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_STIE_SHIFT)) & LPI2C_MIER_STIE_MASK) +/*! @} */ + +/*! @name MDER - Controller DMA Enable */ +/*! @{ */ + +#define LPI2C_MDER_TDDE_MASK (0x1U) +#define LPI2C_MDER_TDDE_SHIFT (0U) +/*! TDDE - Transmit Data DMA Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_MDER_TDDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MDER_TDDE_SHIFT)) & LPI2C_MDER_TDDE_MASK) + +#define LPI2C_MDER_RDDE_MASK (0x2U) +#define LPI2C_MDER_RDDE_SHIFT (1U) +/*! RDDE - Receive Data DMA Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_MDER_RDDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MDER_RDDE_SHIFT)) & LPI2C_MDER_RDDE_MASK) +/*! @} */ + +/*! @name MCFGR0 - Controller Configuration 0 */ +/*! @{ */ + +#define LPI2C_MCFGR0_HREN_MASK (0x1U) +#define LPI2C_MCFGR0_HREN_SHIFT (0U) +/*! HREN - Host Request Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_MCFGR0_HREN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_HREN_SHIFT)) & LPI2C_MCFGR0_HREN_MASK) + +#define LPI2C_MCFGR0_HRPOL_MASK (0x2U) +#define LPI2C_MCFGR0_HRPOL_SHIFT (1U) +/*! HRPOL - Host Request Polarity + * 0b0..Active low + * 0b1..Active high + */ +#define LPI2C_MCFGR0_HRPOL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_HRPOL_SHIFT)) & LPI2C_MCFGR0_HRPOL_MASK) + +#define LPI2C_MCFGR0_HRSEL_MASK (0x4U) +#define LPI2C_MCFGR0_HRSEL_SHIFT (2U) +/*! HRSEL - Host Request Select + * 0b0.. + * 0b1..Host request input is input trigger + */ +#define LPI2C_MCFGR0_HRSEL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_HRSEL_SHIFT)) & LPI2C_MCFGR0_HRSEL_MASK) + +#define LPI2C_MCFGR0_CIRFIFO_MASK (0x100U) +#define LPI2C_MCFGR0_CIRFIFO_SHIFT (8U) +/*! CIRFIFO - Circular FIFO Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_MCFGR0_CIRFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_CIRFIFO_SHIFT)) & LPI2C_MCFGR0_CIRFIFO_MASK) + +#define LPI2C_MCFGR0_RDMO_MASK (0x200U) +#define LPI2C_MCFGR0_RDMO_SHIFT (9U) +/*! RDMO - Receive Data Match Only + * 0b0..Received data is stored in the receive FIFO + * 0b1..Received data is discarded unless MSR[DMF] is set + */ +#define LPI2C_MCFGR0_RDMO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_RDMO_SHIFT)) & LPI2C_MCFGR0_RDMO_MASK) + +#define LPI2C_MCFGR0_RELAX_MASK (0x10000U) +#define LPI2C_MCFGR0_RELAX_SHIFT (16U) +/*! RELAX - Relaxed Mode + * 0b0..Normal transfer + * 0b1..Relaxed transfer + */ +#define LPI2C_MCFGR0_RELAX(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_RELAX_SHIFT)) & LPI2C_MCFGR0_RELAX_MASK) + +#define LPI2C_MCFGR0_ABORT_MASK (0x20000U) +#define LPI2C_MCFGR0_ABORT_SHIFT (17U) +/*! ABORT - Abort Transfer + * 0b0..Normal transfer + * 0b1..Abort existing transfer and do not start a new one + */ +#define LPI2C_MCFGR0_ABORT(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_ABORT_SHIFT)) & LPI2C_MCFGR0_ABORT_MASK) +/*! @} */ + +/*! @name MCFGR1 - Controller Configuration 1 */ +/*! @{ */ + +#define LPI2C_MCFGR1_PRESCALE_MASK (0x7U) +#define LPI2C_MCFGR1_PRESCALE_SHIFT (0U) +/*! PRESCALE - Prescaler + * 0b000..Divide by 1 + * 0b001..Divide by 2 + * 0b010..Divide by 4 + * 0b011..Divide by 8 + * 0b100..Divide by 16 + * 0b101..Divide by 32 + * 0b110..Divide by 64 + * 0b111..Divide by 128 + */ +#define LPI2C_MCFGR1_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_PRESCALE_SHIFT)) & LPI2C_MCFGR1_PRESCALE_MASK) + +#define LPI2C_MCFGR1_AUTOSTOP_MASK (0x100U) +#define LPI2C_MCFGR1_AUTOSTOP_SHIFT (8U) +/*! AUTOSTOP - Automatic Stop Generation + * 0b0..No effect + * 0b1..Stop automatically generated + */ +#define LPI2C_MCFGR1_AUTOSTOP(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_AUTOSTOP_SHIFT)) & LPI2C_MCFGR1_AUTOSTOP_MASK) + +#define LPI2C_MCFGR1_IGNACK_MASK (0x200U) +#define LPI2C_MCFGR1_IGNACK_SHIFT (9U) +/*! IGNACK - Ignore NACK + * 0b0..No effect + * 0b1..Treat a received NACK as an ACK + */ +#define LPI2C_MCFGR1_IGNACK(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_IGNACK_SHIFT)) & LPI2C_MCFGR1_IGNACK_MASK) + +#define LPI2C_MCFGR1_TIMECFG_MASK (0x400U) +#define LPI2C_MCFGR1_TIMECFG_SHIFT (10U) +/*! TIMECFG - Timeout Configuration + * 0b0..SCL + * 0b1..SCL or SDA + */ +#define LPI2C_MCFGR1_TIMECFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_TIMECFG_SHIFT)) & LPI2C_MCFGR1_TIMECFG_MASK) + +#define LPI2C_MCFGR1_STOPCFG_MASK (0x800U) +#define LPI2C_MCFGR1_STOPCFG_SHIFT (11U) +/*! STOPCFG - Stop Configuration + * 0b0..Any Stop condition + * 0b1..Last Stop condition + */ +#define LPI2C_MCFGR1_STOPCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_STOPCFG_SHIFT)) & LPI2C_MCFGR1_STOPCFG_MASK) + +#define LPI2C_MCFGR1_STARTCFG_MASK (0x1000U) +#define LPI2C_MCFGR1_STARTCFG_SHIFT (12U) +/*! STARTCFG - Start Configuration + * 0b0..Sets when both I2C bus and LPI2C controller are idle + * 0b1..Sets when I2C bus is idle + */ +#define LPI2C_MCFGR1_STARTCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_STARTCFG_SHIFT)) & LPI2C_MCFGR1_STARTCFG_MASK) + +#define LPI2C_MCFGR1_MATCFG_MASK (0x70000U) +#define LPI2C_MCFGR1_MATCFG_SHIFT (16U) +/*! MATCFG - Match Configuration + * 0b000..Match is disabled + * 0b001..Reserved + * 0b010..Match is enabled: first data word equals MDMR[MATCH0] OR MDMR[MATCH1] + * 0b011..Match is enabled: any data word equals MDMR[MATCH0] OR MDMR[MATCH1] + * 0b100..Match is enabled: (first data word equals MDMR[MATCH0]) AND (second data word equals MDMR[MATCH1) + * 0b101..Match is enabled: (any data word equals MDMR[MATCH0]) AND (next data word equals MDMR[MATCH1) + * 0b110..Match is enabled: (first data word AND MDMR[MATCH1]) equals (MDMR[MATCH0] AND MDMR[MATCH1]) + * 0b111..Match is enabled: (any data word AND MDMR[MATCH1]) equals (MDMR[MATCH0] AND MDMR[MATCH1]) + */ +#define LPI2C_MCFGR1_MATCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_MATCFG_SHIFT)) & LPI2C_MCFGR1_MATCFG_MASK) + +#define LPI2C_MCFGR1_PINCFG_MASK (0x7000000U) +#define LPI2C_MCFGR1_PINCFG_SHIFT (24U) +/*! PINCFG - Pin Configuration + * 0b000..Two-pin open drain mode + * 0b001..Two-pin output only mode (Ultra-Fast mode) + * 0b010..Two-pin push-pull mode + * 0b011..Four-pin push-pull mode + * 0b100..Two-pin open-drain mode with separate LPI2C target + * 0b101..Two-pin output only mode (Ultra-Fast mode) with separate LPI2C target + * 0b110..Two-pin push-pull mode with separate LPI2C target + * 0b111..Four-pin push-pull mode (inverted outputs) + */ +#define LPI2C_MCFGR1_PINCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_PINCFG_SHIFT)) & LPI2C_MCFGR1_PINCFG_MASK) +/*! @} */ + +/*! @name MCFGR2 - Controller Configuration 2 */ +/*! @{ */ + +#define LPI2C_MCFGR2_BUSIDLE_MASK (0xFFFU) +#define LPI2C_MCFGR2_BUSIDLE_SHIFT (0U) +/*! BUSIDLE - Bus Idle Timeout */ +#define LPI2C_MCFGR2_BUSIDLE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR2_BUSIDLE_SHIFT)) & LPI2C_MCFGR2_BUSIDLE_MASK) + +#define LPI2C_MCFGR2_FILTSCL_MASK (0xF0000U) +#define LPI2C_MCFGR2_FILTSCL_SHIFT (16U) +/*! FILTSCL - Glitch Filter SCL */ +#define LPI2C_MCFGR2_FILTSCL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR2_FILTSCL_SHIFT)) & LPI2C_MCFGR2_FILTSCL_MASK) + +#define LPI2C_MCFGR2_FILTSDA_MASK (0xF000000U) +#define LPI2C_MCFGR2_FILTSDA_SHIFT (24U) +/*! FILTSDA - Glitch Filter SDA */ +#define LPI2C_MCFGR2_FILTSDA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR2_FILTSDA_SHIFT)) & LPI2C_MCFGR2_FILTSDA_MASK) +/*! @} */ + +/*! @name MCFGR3 - Controller Configuration 3 */ +/*! @{ */ + +#define LPI2C_MCFGR3_PINLOW_MASK (0xFFF00U) +#define LPI2C_MCFGR3_PINLOW_SHIFT (8U) +/*! PINLOW - Pin Low Timeout */ +#define LPI2C_MCFGR3_PINLOW(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR3_PINLOW_SHIFT)) & LPI2C_MCFGR3_PINLOW_MASK) +/*! @} */ + +/*! @name MDMR - Controller Data Match */ +/*! @{ */ + +#define LPI2C_MDMR_MATCH0_MASK (0xFFU) +#define LPI2C_MDMR_MATCH0_SHIFT (0U) +/*! MATCH0 - Match 0 Value */ +#define LPI2C_MDMR_MATCH0(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MDMR_MATCH0_SHIFT)) & LPI2C_MDMR_MATCH0_MASK) + +#define LPI2C_MDMR_MATCH1_MASK (0xFF0000U) +#define LPI2C_MDMR_MATCH1_SHIFT (16U) +/*! MATCH1 - Match 1 Value */ +#define LPI2C_MDMR_MATCH1(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MDMR_MATCH1_SHIFT)) & LPI2C_MDMR_MATCH1_MASK) +/*! @} */ + +/*! @name MCCR0 - Controller Clock Configuration 0 */ +/*! @{ */ + +#define LPI2C_MCCR0_CLKLO_MASK (0x3FU) +#define LPI2C_MCCR0_CLKLO_SHIFT (0U) +/*! CLKLO - Clock Low Period */ +#define LPI2C_MCCR0_CLKLO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_CLKLO_SHIFT)) & LPI2C_MCCR0_CLKLO_MASK) + +#define LPI2C_MCCR0_CLKHI_MASK (0x3F00U) +#define LPI2C_MCCR0_CLKHI_SHIFT (8U) +/*! CLKHI - Clock High Period */ +#define LPI2C_MCCR0_CLKHI(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_CLKHI_SHIFT)) & LPI2C_MCCR0_CLKHI_MASK) + +#define LPI2C_MCCR0_SETHOLD_MASK (0x3F0000U) +#define LPI2C_MCCR0_SETHOLD_SHIFT (16U) +/*! SETHOLD - Setup Hold Delay */ +#define LPI2C_MCCR0_SETHOLD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_SETHOLD_SHIFT)) & LPI2C_MCCR0_SETHOLD_MASK) + +#define LPI2C_MCCR0_DATAVD_MASK (0x3F000000U) +#define LPI2C_MCCR0_DATAVD_SHIFT (24U) +/*! DATAVD - Data Valid Delay */ +#define LPI2C_MCCR0_DATAVD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_DATAVD_SHIFT)) & LPI2C_MCCR0_DATAVD_MASK) +/*! @} */ + +/*! @name MCCR1 - Controller Clock Configuration 1 */ +/*! @{ */ + +#define LPI2C_MCCR1_CLKLO_MASK (0x3FU) +#define LPI2C_MCCR1_CLKLO_SHIFT (0U) +/*! CLKLO - Clock Low Period */ +#define LPI2C_MCCR1_CLKLO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_CLKLO_SHIFT)) & LPI2C_MCCR1_CLKLO_MASK) + +#define LPI2C_MCCR1_CLKHI_MASK (0x3F00U) +#define LPI2C_MCCR1_CLKHI_SHIFT (8U) +/*! CLKHI - Clock High Period */ +#define LPI2C_MCCR1_CLKHI(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_CLKHI_SHIFT)) & LPI2C_MCCR1_CLKHI_MASK) + +#define LPI2C_MCCR1_SETHOLD_MASK (0x3F0000U) +#define LPI2C_MCCR1_SETHOLD_SHIFT (16U) +/*! SETHOLD - Setup Hold Delay */ +#define LPI2C_MCCR1_SETHOLD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_SETHOLD_SHIFT)) & LPI2C_MCCR1_SETHOLD_MASK) + +#define LPI2C_MCCR1_DATAVD_MASK (0x3F000000U) +#define LPI2C_MCCR1_DATAVD_SHIFT (24U) +/*! DATAVD - Data Valid Delay */ +#define LPI2C_MCCR1_DATAVD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_DATAVD_SHIFT)) & LPI2C_MCCR1_DATAVD_MASK) +/*! @} */ + +/*! @name MFCR - Controller FIFO Control */ +/*! @{ */ + +#define LPI2C_MFCR_TXWATER_MASK (0x7U) +#define LPI2C_MFCR_TXWATER_SHIFT (0U) +/*! TXWATER - Transmit FIFO Watermark */ +#define LPI2C_MFCR_TXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MFCR_TXWATER_SHIFT)) & LPI2C_MFCR_TXWATER_MASK) + +#define LPI2C_MFCR_RXWATER_MASK (0x70000U) +#define LPI2C_MFCR_RXWATER_SHIFT (16U) +/*! RXWATER - Receive FIFO Watermark */ +#define LPI2C_MFCR_RXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MFCR_RXWATER_SHIFT)) & LPI2C_MFCR_RXWATER_MASK) +/*! @} */ + +/*! @name MFSR - Controller FIFO Status */ +/*! @{ */ + +#define LPI2C_MFSR_TXCOUNT_MASK (0xFU) +#define LPI2C_MFSR_TXCOUNT_SHIFT (0U) +/*! TXCOUNT - Transmit FIFO Count */ +#define LPI2C_MFSR_TXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MFSR_TXCOUNT_SHIFT)) & LPI2C_MFSR_TXCOUNT_MASK) + +#define LPI2C_MFSR_RXCOUNT_MASK (0xF0000U) +#define LPI2C_MFSR_RXCOUNT_SHIFT (16U) +/*! RXCOUNT - Receive FIFO Count */ +#define LPI2C_MFSR_RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MFSR_RXCOUNT_SHIFT)) & LPI2C_MFSR_RXCOUNT_MASK) +/*! @} */ + +/*! @name MTDR - Controller Transmit Data */ +/*! @{ */ + +#define LPI2C_MTDR_DATA_MASK (0xFFU) +#define LPI2C_MTDR_DATA_SHIFT (0U) +/*! DATA - Transmit Data */ +#define LPI2C_MTDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MTDR_DATA_SHIFT)) & LPI2C_MTDR_DATA_MASK) + +#define LPI2C_MTDR_CMD_MASK (0x700U) +#define LPI2C_MTDR_CMD_SHIFT (8U) +/*! CMD - Command Data + * 0b000..Transmit the value in DATA[7:0] + * 0b001..Receive (DATA[7:0] + 1) bytes + * 0b010..Generate Stop condition on I2C bus + * 0b011..Receive and discard (DATA[7:0] + 1) bytes + * 0b100..Generate (repeated) Start on the I2C bus and transmit the address in DATA[7:0] + * 0b101..Generate (repeated) Start on the I2C bus and transmit the address in DATA[7:0] (this transfer expects a NACK to be returned) + * 0b110..Generate (repeated) Start on the I2C bus and transmit the address in DATA[7:0] using HS mode + * 0b111..Generate (repeated) Start on the I2C bus and transmit the address in DATA[7:0] using HS mode (this transfer expects a NACK to be returned) + */ +#define LPI2C_MTDR_CMD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MTDR_CMD_SHIFT)) & LPI2C_MTDR_CMD_MASK) +/*! @} */ + +/*! @name MRDR - Controller Receive Data */ +/*! @{ */ + +#define LPI2C_MRDR_DATA_MASK (0xFFU) +#define LPI2C_MRDR_DATA_SHIFT (0U) +/*! DATA - Receive Data */ +#define LPI2C_MRDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MRDR_DATA_SHIFT)) & LPI2C_MRDR_DATA_MASK) + +#define LPI2C_MRDR_RXEMPTY_MASK (0x4000U) +#define LPI2C_MRDR_RXEMPTY_SHIFT (14U) +/*! RXEMPTY - Receive Empty + * 0b0..Not empty + * 0b1..Empty + */ +#define LPI2C_MRDR_RXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MRDR_RXEMPTY_SHIFT)) & LPI2C_MRDR_RXEMPTY_MASK) +/*! @} */ + +/*! @name MRDROR - Controller Receive Data Read Only */ +/*! @{ */ + +#define LPI2C_MRDROR_DATA_MASK (0xFFU) +#define LPI2C_MRDROR_DATA_SHIFT (0U) +/*! DATA - Receive Data */ +#define LPI2C_MRDROR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MRDROR_DATA_SHIFT)) & LPI2C_MRDROR_DATA_MASK) + +#define LPI2C_MRDROR_RXEMPTY_MASK (0x4000U) +#define LPI2C_MRDROR_RXEMPTY_SHIFT (14U) +/*! RXEMPTY - RX Empty + * 0b0..Not empty + * 0b1..Empty + */ +#define LPI2C_MRDROR_RXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MRDROR_RXEMPTY_SHIFT)) & LPI2C_MRDROR_RXEMPTY_MASK) +/*! @} */ + +/*! @name SCR - Target Control */ +/*! @{ */ + +#define LPI2C_SCR_SEN_MASK (0x1U) +#define LPI2C_SCR_SEN_SHIFT (0U) +/*! SEN - Target Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_SCR_SEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_SEN_SHIFT)) & LPI2C_SCR_SEN_MASK) + +#define LPI2C_SCR_RST_MASK (0x2U) +#define LPI2C_SCR_RST_SHIFT (1U) +/*! RST - Software Reset + * 0b0..Not reset + * 0b1..Reset + */ +#define LPI2C_SCR_RST(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_RST_SHIFT)) & LPI2C_SCR_RST_MASK) + +#define LPI2C_SCR_FILTEN_MASK (0x10U) +#define LPI2C_SCR_FILTEN_SHIFT (4U) +/*! FILTEN - Filter Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_SCR_FILTEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_FILTEN_SHIFT)) & LPI2C_SCR_FILTEN_MASK) + +#define LPI2C_SCR_FILTDZ_MASK (0x20U) +#define LPI2C_SCR_FILTDZ_SHIFT (5U) +/*! FILTDZ - Filter Doze Enable + * 0b0..Enable + * 0b1..Disable + */ +#define LPI2C_SCR_FILTDZ(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_FILTDZ_SHIFT)) & LPI2C_SCR_FILTDZ_MASK) + +#define LPI2C_SCR_RTF_MASK (0x100U) +#define LPI2C_SCR_RTF_SHIFT (8U) +/*! RTF - Reset Transmit FIFO + * 0b0..No effect + * 0b1..STDR is now empty + */ +#define LPI2C_SCR_RTF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_RTF_SHIFT)) & LPI2C_SCR_RTF_MASK) + +#define LPI2C_SCR_RRF_MASK (0x200U) +#define LPI2C_SCR_RRF_SHIFT (9U) +/*! RRF - Reset Receive FIFO + * 0b0..No effect + * 0b1..SRDR is now empty + */ +#define LPI2C_SCR_RRF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_RRF_SHIFT)) & LPI2C_SCR_RRF_MASK) +/*! @} */ + +/*! @name SSR - Target Status */ +/*! @{ */ + +#define LPI2C_SSR_TDF_MASK (0x1U) +#define LPI2C_SSR_TDF_SHIFT (0U) +/*! TDF - Transmit Data Flag + * 0b0..Transmit data not requested + * 0b1..Transmit data is requested + */ +#define LPI2C_SSR_TDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_TDF_SHIFT)) & LPI2C_SSR_TDF_MASK) + +#define LPI2C_SSR_RDF_MASK (0x2U) +#define LPI2C_SSR_RDF_SHIFT (1U) +/*! RDF - Receive Data Flag + * 0b0..Not ready + * 0b1..Ready + */ +#define LPI2C_SSR_RDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_RDF_SHIFT)) & LPI2C_SSR_RDF_MASK) + +#define LPI2C_SSR_AVF_MASK (0x4U) +#define LPI2C_SSR_AVF_SHIFT (2U) +/*! AVF - Address Valid Flag + * 0b0..Not valid + * 0b1..Valid + */ +#define LPI2C_SSR_AVF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_AVF_SHIFT)) & LPI2C_SSR_AVF_MASK) + +#define LPI2C_SSR_TAF_MASK (0x8U) +#define LPI2C_SSR_TAF_SHIFT (3U) +/*! TAF - Transmit ACK Flag + * 0b0..Not required + * 0b1..Required + */ +#define LPI2C_SSR_TAF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_TAF_SHIFT)) & LPI2C_SSR_TAF_MASK) + +#define LPI2C_SSR_RSF_MASK (0x100U) +#define LPI2C_SSR_RSF_SHIFT (8U) +/*! RSF - Repeated Start Flag + * 0b0..No repeated Start detected + * 0b0..No effect + * 0b1..Repeated Start detected + * 0b1..Clear the flag + */ +#define LPI2C_SSR_RSF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_RSF_SHIFT)) & LPI2C_SSR_RSF_MASK) + +#define LPI2C_SSR_SDF_MASK (0x200U) +#define LPI2C_SSR_SDF_SHIFT (9U) +/*! SDF - Stop Detect Flag + * 0b0..No Stop detected + * 0b0..No effect + * 0b1..Stop detected + * 0b1..Clear the flag + */ +#define LPI2C_SSR_SDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_SDF_SHIFT)) & LPI2C_SSR_SDF_MASK) + +#define LPI2C_SSR_BEF_MASK (0x400U) +#define LPI2C_SSR_BEF_SHIFT (10U) +/*! BEF - Bit Error Flag + * 0b0..No bit error occurred + * 0b0..No effect + * 0b1..Bit error occurred + * 0b1..Clear the flag + */ +#define LPI2C_SSR_BEF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_BEF_SHIFT)) & LPI2C_SSR_BEF_MASK) + +#define LPI2C_SSR_FEF_MASK (0x800U) +#define LPI2C_SSR_FEF_SHIFT (11U) +/*! FEF - FIFO Error Flag + * 0b0..No FIFO error + * 0b0..No effect + * 0b1..FIFO error + * 0b1..Clear the flag + */ +#define LPI2C_SSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_FEF_SHIFT)) & LPI2C_SSR_FEF_MASK) + +#define LPI2C_SSR_AM0F_MASK (0x1000U) +#define LPI2C_SSR_AM0F_SHIFT (12U) +/*! AM0F - Address Match 0 Flag + * 0b0..ADDR0 matching address not received + * 0b1..ADDR0 matching address received + */ +#define LPI2C_SSR_AM0F(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_AM0F_SHIFT)) & LPI2C_SSR_AM0F_MASK) + +#define LPI2C_SSR_AM1F_MASK (0x2000U) +#define LPI2C_SSR_AM1F_SHIFT (13U) +/*! AM1F - Address Match 1 Flag + * 0b0..Matching address not received + * 0b1..Matching address received + */ +#define LPI2C_SSR_AM1F(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_AM1F_SHIFT)) & LPI2C_SSR_AM1F_MASK) + +#define LPI2C_SSR_GCF_MASK (0x4000U) +#define LPI2C_SSR_GCF_SHIFT (14U) +/*! GCF - General Call Flag + * 0b0..General call address disabled or not detected + * 0b1..General call address detected + */ +#define LPI2C_SSR_GCF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_GCF_SHIFT)) & LPI2C_SSR_GCF_MASK) + +#define LPI2C_SSR_SARF_MASK (0x8000U) +#define LPI2C_SSR_SARF_SHIFT (15U) +/*! SARF - SMBus Alert Response Flag + * 0b0..Disabled or not detected + * 0b1..Enabled and detected + */ +#define LPI2C_SSR_SARF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_SARF_SHIFT)) & LPI2C_SSR_SARF_MASK) + +#define LPI2C_SSR_SBF_MASK (0x1000000U) +#define LPI2C_SSR_SBF_SHIFT (24U) +/*! SBF - Target Busy Flag + * 0b0..Idle + * 0b1..Busy + */ +#define LPI2C_SSR_SBF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_SBF_SHIFT)) & LPI2C_SSR_SBF_MASK) + +#define LPI2C_SSR_BBF_MASK (0x2000000U) +#define LPI2C_SSR_BBF_SHIFT (25U) +/*! BBF - Bus Busy Flag + * 0b0..Idle + * 0b1..Busy + */ +#define LPI2C_SSR_BBF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_BBF_SHIFT)) & LPI2C_SSR_BBF_MASK) +/*! @} */ + +/*! @name SIER - Target Interrupt Enable */ +/*! @{ */ + +#define LPI2C_SIER_TDIE_MASK (0x1U) +#define LPI2C_SIER_TDIE_SHIFT (0U) +/*! TDIE - Transmit Data Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_SIER_TDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_TDIE_SHIFT)) & LPI2C_SIER_TDIE_MASK) + +#define LPI2C_SIER_RDIE_MASK (0x2U) +#define LPI2C_SIER_RDIE_SHIFT (1U) +/*! RDIE - Receive Data Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_SIER_RDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_RDIE_SHIFT)) & LPI2C_SIER_RDIE_MASK) + +#define LPI2C_SIER_AVIE_MASK (0x4U) +#define LPI2C_SIER_AVIE_SHIFT (2U) +/*! AVIE - Address Valid Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_SIER_AVIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_AVIE_SHIFT)) & LPI2C_SIER_AVIE_MASK) + +#define LPI2C_SIER_TAIE_MASK (0x8U) +#define LPI2C_SIER_TAIE_SHIFT (3U) +/*! TAIE - Transmit ACK Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_SIER_TAIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_TAIE_SHIFT)) & LPI2C_SIER_TAIE_MASK) + +#define LPI2C_SIER_RSIE_MASK (0x100U) +#define LPI2C_SIER_RSIE_SHIFT (8U) +/*! RSIE - Repeated Start Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_SIER_RSIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_RSIE_SHIFT)) & LPI2C_SIER_RSIE_MASK) + +#define LPI2C_SIER_SDIE_MASK (0x200U) +#define LPI2C_SIER_SDIE_SHIFT (9U) +/*! SDIE - Stop Detect Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_SIER_SDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_SDIE_SHIFT)) & LPI2C_SIER_SDIE_MASK) + +#define LPI2C_SIER_BEIE_MASK (0x400U) +#define LPI2C_SIER_BEIE_SHIFT (10U) +/*! BEIE - Bit Error Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_SIER_BEIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_BEIE_SHIFT)) & LPI2C_SIER_BEIE_MASK) + +#define LPI2C_SIER_FEIE_MASK (0x800U) +#define LPI2C_SIER_FEIE_SHIFT (11U) +/*! FEIE - FIFO Error Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_SIER_FEIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_FEIE_SHIFT)) & LPI2C_SIER_FEIE_MASK) + +#define LPI2C_SIER_AM0IE_MASK (0x1000U) +#define LPI2C_SIER_AM0IE_SHIFT (12U) +/*! AM0IE - Address Match 0 Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_SIER_AM0IE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_AM0IE_SHIFT)) & LPI2C_SIER_AM0IE_MASK) + +#define LPI2C_SIER_AM1IE_MASK (0x2000U) +#define LPI2C_SIER_AM1IE_SHIFT (13U) +/*! AM1IE - Address Match 1 Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_SIER_AM1IE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_AM1IE_SHIFT)) & LPI2C_SIER_AM1IE_MASK) + +#define LPI2C_SIER_GCIE_MASK (0x4000U) +#define LPI2C_SIER_GCIE_SHIFT (14U) +/*! GCIE - General Call Interrupt Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define LPI2C_SIER_GCIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_GCIE_SHIFT)) & LPI2C_SIER_GCIE_MASK) + +#define LPI2C_SIER_SARIE_MASK (0x8000U) +#define LPI2C_SIER_SARIE_SHIFT (15U) +/*! SARIE - SMBus Alert Response Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_SIER_SARIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_SARIE_SHIFT)) & LPI2C_SIER_SARIE_MASK) +/*! @} */ + +/*! @name SDER - Target DMA Enable */ +/*! @{ */ + +#define LPI2C_SDER_TDDE_MASK (0x1U) +#define LPI2C_SDER_TDDE_SHIFT (0U) +/*! TDDE - Transmit Data DMA Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_SDER_TDDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_TDDE_SHIFT)) & LPI2C_SDER_TDDE_MASK) + +#define LPI2C_SDER_RDDE_MASK (0x2U) +#define LPI2C_SDER_RDDE_SHIFT (1U) +/*! RDDE - Receive Data DMA Enable + * 0b0..Disable DMA request + * 0b1..Enable DMA request + */ +#define LPI2C_SDER_RDDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_RDDE_SHIFT)) & LPI2C_SDER_RDDE_MASK) + +#define LPI2C_SDER_AVDE_MASK (0x4U) +#define LPI2C_SDER_AVDE_SHIFT (2U) +/*! AVDE - Address Valid DMA Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_SDER_AVDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_AVDE_SHIFT)) & LPI2C_SDER_AVDE_MASK) + +#define LPI2C_SDER_RSDE_MASK (0x100U) +#define LPI2C_SDER_RSDE_SHIFT (8U) +/*! RSDE - Repeated Start DMA Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_SDER_RSDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_RSDE_SHIFT)) & LPI2C_SDER_RSDE_MASK) + +#define LPI2C_SDER_SDDE_MASK (0x200U) +#define LPI2C_SDER_SDDE_SHIFT (9U) +/*! SDDE - Stop Detect DMA Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_SDER_SDDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_SDDE_SHIFT)) & LPI2C_SDER_SDDE_MASK) +/*! @} */ + +/*! @name SCFGR0 - Target Configuration 0 */ +/*! @{ */ + +#define LPI2C_SCFGR0_RDREQ_MASK (0x1U) +#define LPI2C_SCFGR0_RDREQ_SHIFT (0U) +/*! RDREQ - Read Request + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_SCFGR0_RDREQ(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR0_RDREQ_SHIFT)) & LPI2C_SCFGR0_RDREQ_MASK) + +#define LPI2C_SCFGR0_RDACK_MASK (0x2U) +#define LPI2C_SCFGR0_RDACK_SHIFT (1U) +/*! RDACK - Read Acknowledge Flag + * 0b0..Read Request not acknowledged + * 0b1..Read Request acknowledged + */ +#define LPI2C_SCFGR0_RDACK(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR0_RDACK_SHIFT)) & LPI2C_SCFGR0_RDACK_MASK) +/*! @} */ + +/*! @name SCFGR1 - Target Configuration 1 */ +/*! @{ */ + +#define LPI2C_SCFGR1_ADRSTALL_MASK (0x1U) +#define LPI2C_SCFGR1_ADRSTALL_SHIFT (0U) +/*! ADRSTALL - Address SCL Stall + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_SCFGR1_ADRSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_ADRSTALL_SHIFT)) & LPI2C_SCFGR1_ADRSTALL_MASK) + +#define LPI2C_SCFGR1_RXSTALL_MASK (0x2U) +#define LPI2C_SCFGR1_RXSTALL_SHIFT (1U) +/*! RXSTALL - RX SCL Stall + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_SCFGR1_RXSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_RXSTALL_SHIFT)) & LPI2C_SCFGR1_RXSTALL_MASK) + +#define LPI2C_SCFGR1_TXDSTALL_MASK (0x4U) +#define LPI2C_SCFGR1_TXDSTALL_SHIFT (2U) +/*! TXDSTALL - Transmit Data SCL Stall + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_SCFGR1_TXDSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_TXDSTALL_SHIFT)) & LPI2C_SCFGR1_TXDSTALL_MASK) + +#define LPI2C_SCFGR1_ACKSTALL_MASK (0x8U) +#define LPI2C_SCFGR1_ACKSTALL_SHIFT (3U) +/*! ACKSTALL - ACK SCL Stall + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_SCFGR1_ACKSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_ACKSTALL_SHIFT)) & LPI2C_SCFGR1_ACKSTALL_MASK) + +#define LPI2C_SCFGR1_RXNACK_MASK (0x10U) +#define LPI2C_SCFGR1_RXNACK_SHIFT (4U) +/*! RXNACK - Receive NACK + * 0b0..ACK or NACK always determined by STAR[TXNACK] + * 0b1..NACK always generated on address overrun or receive data overrun, otherwise ACK or NACK is determined by STAR[TXNACK] + */ +#define LPI2C_SCFGR1_RXNACK(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_RXNACK_SHIFT)) & LPI2C_SCFGR1_RXNACK_MASK) + +#define LPI2C_SCFGR1_GCEN_MASK (0x100U) +#define LPI2C_SCFGR1_GCEN_SHIFT (8U) +/*! GCEN - General Call Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_SCFGR1_GCEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_GCEN_SHIFT)) & LPI2C_SCFGR1_GCEN_MASK) + +#define LPI2C_SCFGR1_SAEN_MASK (0x200U) +#define LPI2C_SCFGR1_SAEN_SHIFT (9U) +/*! SAEN - SMBus Alert Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_SCFGR1_SAEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_SAEN_SHIFT)) & LPI2C_SCFGR1_SAEN_MASK) + +#define LPI2C_SCFGR1_TXCFG_MASK (0x400U) +#define LPI2C_SCFGR1_TXCFG_SHIFT (10U) +/*! TXCFG - Transmit Flag Configuration + * 0b0..MSR[TDF] is set only during a target-transmit transfer when STDR is empty + * 0b1..MSR[TDF] is set whenever STDR is empty + */ +#define LPI2C_SCFGR1_TXCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_TXCFG_SHIFT)) & LPI2C_SCFGR1_TXCFG_MASK) + +#define LPI2C_SCFGR1_RXCFG_MASK (0x800U) +#define LPI2C_SCFGR1_RXCFG_SHIFT (11U) +/*! RXCFG - Receive Data Configuration + * 0b0..Return received data, clear MSR[RDF] + * 0b1..Return SASR and clear SSR[AVF] when SSR[AVF] is set, return received data and clear MSR[RDF] when SSR[AFV] is not set + */ +#define LPI2C_SCFGR1_RXCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_RXCFG_SHIFT)) & LPI2C_SCFGR1_RXCFG_MASK) + +#define LPI2C_SCFGR1_IGNACK_MASK (0x1000U) +#define LPI2C_SCFGR1_IGNACK_SHIFT (12U) +/*! IGNACK - Ignore NACK + * 0b0..End transfer on NACK + * 0b1..Do not end transfer on NACK + */ +#define LPI2C_SCFGR1_IGNACK(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_IGNACK_SHIFT)) & LPI2C_SCFGR1_IGNACK_MASK) + +#define LPI2C_SCFGR1_HSMEN_MASK (0x2000U) +#define LPI2C_SCFGR1_HSMEN_SHIFT (13U) +/*! HSMEN - HS Mode Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_SCFGR1_HSMEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_HSMEN_SHIFT)) & LPI2C_SCFGR1_HSMEN_MASK) + +#define LPI2C_SCFGR1_ADDRCFG_MASK (0x70000U) +#define LPI2C_SCFGR1_ADDRCFG_SHIFT (16U) +/*! ADDRCFG - Address Configuration + * 0b000..Address match 0 (7-bit) + * 0b001..Address match 0 (10-bit) + * 0b010..Address match 0 (7-bit) or address match 1 (7-bit) + * 0b011..Address match 0 (10-bit) or address match 1 (10-bit) + * 0b100..Address match 0 (7-bit) or address match 1 (10-bit) + * 0b101..Address match 0 (10-bit) or address match 1 (7-bit) + * 0b110..From address match 0 (7-bit) to address match 1 (7-bit) + * 0b111..From address match 0 (10-bit) to address match 1 (10-bit) + */ +#define LPI2C_SCFGR1_ADDRCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_ADDRCFG_SHIFT)) & LPI2C_SCFGR1_ADDRCFG_MASK) + +#define LPI2C_SCFGR1_RXALL_MASK (0x1000000U) +#define LPI2C_SCFGR1_RXALL_SHIFT (24U) +/*! RXALL - Receive All + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_SCFGR1_RXALL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_RXALL_SHIFT)) & LPI2C_SCFGR1_RXALL_MASK) + +#define LPI2C_SCFGR1_RSCFG_MASK (0x2000000U) +#define LPI2C_SCFGR1_RSCFG_SHIFT (25U) +/*! RSCFG - Repeated Start Configuration + * 0b0..Any repeated Start condition following an address match + * 0b1..Any repeated Start condition + */ +#define LPI2C_SCFGR1_RSCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_RSCFG_SHIFT)) & LPI2C_SCFGR1_RSCFG_MASK) + +#define LPI2C_SCFGR1_SDCFG_MASK (0x4000000U) +#define LPI2C_SCFGR1_SDCFG_SHIFT (26U) +/*! SDCFG - Stop Detect Configuration + * 0b0..Any Stop condition following an address match + * 0b1..Any Stop condition + */ +#define LPI2C_SCFGR1_SDCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_SDCFG_SHIFT)) & LPI2C_SCFGR1_SDCFG_MASK) +/*! @} */ + +/*! @name SCFGR2 - Target Configuration 2 */ +/*! @{ */ + +#define LPI2C_SCFGR2_CLKHOLD_MASK (0xFU) +#define LPI2C_SCFGR2_CLKHOLD_SHIFT (0U) +/*! CLKHOLD - Clock Hold Time */ +#define LPI2C_SCFGR2_CLKHOLD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_CLKHOLD_SHIFT)) & LPI2C_SCFGR2_CLKHOLD_MASK) + +#define LPI2C_SCFGR2_DATAVD_MASK (0x3F00U) +#define LPI2C_SCFGR2_DATAVD_SHIFT (8U) +/*! DATAVD - Data Valid Delay */ +#define LPI2C_SCFGR2_DATAVD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_DATAVD_SHIFT)) & LPI2C_SCFGR2_DATAVD_MASK) + +#define LPI2C_SCFGR2_FILTSCL_MASK (0xF0000U) +#define LPI2C_SCFGR2_FILTSCL_SHIFT (16U) +/*! FILTSCL - Glitch Filter SCL */ +#define LPI2C_SCFGR2_FILTSCL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_FILTSCL_SHIFT)) & LPI2C_SCFGR2_FILTSCL_MASK) + +#define LPI2C_SCFGR2_FILTSDA_MASK (0xF000000U) +#define LPI2C_SCFGR2_FILTSDA_SHIFT (24U) +/*! FILTSDA - Glitch Filter SDA */ +#define LPI2C_SCFGR2_FILTSDA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_FILTSDA_SHIFT)) & LPI2C_SCFGR2_FILTSDA_MASK) +/*! @} */ + +/*! @name SAMR - Target Address Match */ +/*! @{ */ + +#define LPI2C_SAMR_ADDR0_MASK (0x7FEU) +#define LPI2C_SAMR_ADDR0_SHIFT (1U) +/*! ADDR0 - Address 0 Value */ +#define LPI2C_SAMR_ADDR0(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SAMR_ADDR0_SHIFT)) & LPI2C_SAMR_ADDR0_MASK) + +#define LPI2C_SAMR_ADDR1_MASK (0x7FE0000U) +#define LPI2C_SAMR_ADDR1_SHIFT (17U) +/*! ADDR1 - Address 1 Value */ +#define LPI2C_SAMR_ADDR1(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SAMR_ADDR1_SHIFT)) & LPI2C_SAMR_ADDR1_MASK) +/*! @} */ + +/*! @name SASR - Target Address Status */ +/*! @{ */ + +#define LPI2C_SASR_RADDR_MASK (0x7FFU) +#define LPI2C_SASR_RADDR_SHIFT (0U) +/*! RADDR - Received Address */ +#define LPI2C_SASR_RADDR(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SASR_RADDR_SHIFT)) & LPI2C_SASR_RADDR_MASK) + +#define LPI2C_SASR_ANV_MASK (0x4000U) +#define LPI2C_SASR_ANV_SHIFT (14U) +/*! ANV - Address Not Valid + * 0b0..Valid + * 0b1..Not valid + */ +#define LPI2C_SASR_ANV(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SASR_ANV_SHIFT)) & LPI2C_SASR_ANV_MASK) +/*! @} */ + +/*! @name STAR - Target Transmit ACK */ +/*! @{ */ + +#define LPI2C_STAR_TXNACK_MASK (0x1U) +#define LPI2C_STAR_TXNACK_SHIFT (0U) +/*! TXNACK - Transmit NACK + * 0b0..Transmit ACK + * 0b1..Transmit NACK + */ +#define LPI2C_STAR_TXNACK(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_STAR_TXNACK_SHIFT)) & LPI2C_STAR_TXNACK_MASK) +/*! @} */ + +/*! @name STDR - Target Transmit Data */ +/*! @{ */ + +#define LPI2C_STDR_DATA_MASK (0xFFU) +#define LPI2C_STDR_DATA_SHIFT (0U) +/*! DATA - Transmit Data */ +#define LPI2C_STDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_STDR_DATA_SHIFT)) & LPI2C_STDR_DATA_MASK) +/*! @} */ + +/*! @name SRDR - Target Receive Data */ +/*! @{ */ + +#define LPI2C_SRDR_DATA_MASK (0xFFU) +#define LPI2C_SRDR_DATA_SHIFT (0U) +/*! DATA - Received Data */ +#define LPI2C_SRDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDR_DATA_SHIFT)) & LPI2C_SRDR_DATA_MASK) + +#define LPI2C_SRDR_RADDR_MASK (0x700U) +#define LPI2C_SRDR_RADDR_SHIFT (8U) +/*! RADDR - Received Address */ +#define LPI2C_SRDR_RADDR(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDR_RADDR_SHIFT)) & LPI2C_SRDR_RADDR_MASK) + +#define LPI2C_SRDR_RXEMPTY_MASK (0x4000U) +#define LPI2C_SRDR_RXEMPTY_SHIFT (14U) +/*! RXEMPTY - Receive Empty + * 0b0..Not empty + * 0b1..Empty + */ +#define LPI2C_SRDR_RXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDR_RXEMPTY_SHIFT)) & LPI2C_SRDR_RXEMPTY_MASK) + +#define LPI2C_SRDR_SOF_MASK (0x8000U) +#define LPI2C_SRDR_SOF_SHIFT (15U) +/*! SOF - Start of Frame + * 0b0..Not first + * 0b1..First + */ +#define LPI2C_SRDR_SOF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDR_SOF_SHIFT)) & LPI2C_SRDR_SOF_MASK) +/*! @} */ + +/*! @name SRDROR - Target Receive Data Read Only */ +/*! @{ */ + +#define LPI2C_SRDROR_DATA_MASK (0xFFU) +#define LPI2C_SRDROR_DATA_SHIFT (0U) +/*! DATA - Receive Data */ +#define LPI2C_SRDROR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDROR_DATA_SHIFT)) & LPI2C_SRDROR_DATA_MASK) + +#define LPI2C_SRDROR_RADDR_MASK (0x700U) +#define LPI2C_SRDROR_RADDR_SHIFT (8U) +/*! RADDR - Received Address */ +#define LPI2C_SRDROR_RADDR(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDROR_RADDR_SHIFT)) & LPI2C_SRDROR_RADDR_MASK) + +#define LPI2C_SRDROR_RXEMPTY_MASK (0x4000U) +#define LPI2C_SRDROR_RXEMPTY_SHIFT (14U) +/*! RXEMPTY - Receive Empty + * 0b0..Not empty + * 0b1..Empty + */ +#define LPI2C_SRDROR_RXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDROR_RXEMPTY_SHIFT)) & LPI2C_SRDROR_RXEMPTY_MASK) + +#define LPI2C_SRDROR_SOF_MASK (0x8000U) +#define LPI2C_SRDROR_SOF_SHIFT (15U) +/*! SOF - Start of Frame + * 0b0..Not the first + * 0b1..First + */ +#define LPI2C_SRDROR_SOF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDROR_SOF_SHIFT)) & LPI2C_SRDROR_SOF_MASK) +/*! @} */ + +/*! @name MTCBR - Controller Transmit Command Burst */ +/*! @{ */ + +#define LPI2C_MTCBR_DATA_MASK (0xFFU) +#define LPI2C_MTCBR_DATA_SHIFT (0U) +/*! DATA - Data */ +#define LPI2C_MTCBR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MTCBR_DATA_SHIFT)) & LPI2C_MTCBR_DATA_MASK) + +#define LPI2C_MTCBR_CMD_MASK (0x700U) +#define LPI2C_MTCBR_CMD_SHIFT (8U) +/*! CMD - Command */ +#define LPI2C_MTCBR_CMD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MTCBR_CMD_SHIFT)) & LPI2C_MTCBR_CMD_MASK) +/*! @} */ + +/* The count of LPI2C_MTCBR */ +#define LPI2C_MTCBR_COUNT (128U) + +/*! @name MTDBR - Transmit Data Burst */ +/*! @{ */ + +#define LPI2C_MTDBR_DATA0_MASK (0xFFU) +#define LPI2C_MTDBR_DATA0_SHIFT (0U) +/*! DATA0 - Data */ +#define LPI2C_MTDBR_DATA0(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MTDBR_DATA0_SHIFT)) & LPI2C_MTDBR_DATA0_MASK) + +#define LPI2C_MTDBR_DATA1_MASK (0xFF00U) +#define LPI2C_MTDBR_DATA1_SHIFT (8U) +/*! DATA1 - Data */ +#define LPI2C_MTDBR_DATA1(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MTDBR_DATA1_SHIFT)) & LPI2C_MTDBR_DATA1_MASK) + +#define LPI2C_MTDBR_DATA2_MASK (0xFF0000U) +#define LPI2C_MTDBR_DATA2_SHIFT (16U) +/*! DATA2 - Data */ +#define LPI2C_MTDBR_DATA2(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MTDBR_DATA2_SHIFT)) & LPI2C_MTDBR_DATA2_MASK) + +#define LPI2C_MTDBR_DATA3_MASK (0xFF000000U) +#define LPI2C_MTDBR_DATA3_SHIFT (24U) +/*! DATA3 - Data */ +#define LPI2C_MTDBR_DATA3(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MTDBR_DATA3_SHIFT)) & LPI2C_MTDBR_DATA3_MASK) +/*! @} */ + +/* The count of LPI2C_MTDBR */ +#define LPI2C_MTDBR_COUNT (256U) + + +/*! + * @} + */ /* end of group LPI2C_Register_Masks */ + + +/* LPI2C - Peripheral instance base addresses */ +/** Peripheral LPI2C1 base address */ +#define LPI2C1_BASE (0x44340000u) +/** Peripheral LPI2C1 base pointer */ +#define LPI2C1 ((LPI2C_Type *)LPI2C1_BASE) +/** Peripheral LPI2C2 base address */ +#define LPI2C2_BASE (0x44350000u) +/** Peripheral LPI2C2 base pointer */ +#define LPI2C2 ((LPI2C_Type *)LPI2C2_BASE) +/** Peripheral LPI2C3 base address */ +#define LPI2C3_BASE (0x42530000u) +/** Peripheral LPI2C3 base pointer */ +#define LPI2C3 ((LPI2C_Type *)LPI2C3_BASE) +/** Peripheral LPI2C4 base address */ +#define LPI2C4_BASE (0x42540000u) +/** Peripheral LPI2C4 base pointer */ +#define LPI2C4 ((LPI2C_Type *)LPI2C4_BASE) +/** Peripheral LPI2C5 base address */ +#define LPI2C5_BASE (0x426B0000u) +/** Peripheral LPI2C5 base pointer */ +#define LPI2C5 ((LPI2C_Type *)LPI2C5_BASE) +/** Peripheral LPI2C6 base address */ +#define LPI2C6_BASE (0x426C0000u) +/** Peripheral LPI2C6 base pointer */ +#define LPI2C6 ((LPI2C_Type *)LPI2C6_BASE) +/** Peripheral LPI2C7 base address */ +#define LPI2C7_BASE (0x426D0000u) +/** Peripheral LPI2C7 base pointer */ +#define LPI2C7 ((LPI2C_Type *)LPI2C7_BASE) +/** Peripheral LPI2C8 base address */ +#define LPI2C8_BASE (0x426E0000u) +/** Peripheral LPI2C8 base pointer */ +#define LPI2C8 ((LPI2C_Type *)LPI2C8_BASE) +/** Array initializer of LPI2C peripheral base addresses */ +#define LPI2C_BASE_ADDRS { 0u, LPI2C1_BASE, LPI2C2_BASE, LPI2C3_BASE, LPI2C4_BASE, LPI2C5_BASE, LPI2C6_BASE, LPI2C7_BASE, LPI2C8_BASE } +/** Array initializer of LPI2C peripheral base pointers */ +#define LPI2C_BASE_PTRS { (LPI2C_Type *)0u, LPI2C1, LPI2C2, LPI2C3, LPI2C4, LPI2C5, LPI2C6, LPI2C7, LPI2C8 } +/** Interrupt vectors for the LPI2C peripheral type */ +#define LPI2C_IRQS { NotAvail_IRQn, LPI2C1_IRQn, LPI2C2_IRQn, LPI2C3_IRQn, LPI2C4_IRQn, LPI2C5_IRQn, LPI2C6_IRQn, LPI2C7_IRQn, LPI2C8_IRQn } + +/*! + * @} + */ /* end of group LPI2C_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- LPIT Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup LPIT_Peripheral_Access_Layer LPIT Peripheral Access Layer + * @{ + */ + +/** LPIT - Register Layout Typedef */ +typedef struct { + __I uint32_t VERID; /**< Version ID, offset: 0x0 */ + __I uint32_t PARAM; /**< Parameter, offset: 0x4 */ + __IO uint32_t MCR; /**< Module Control, offset: 0x8 */ + __IO uint32_t MSR; /**< Module Status, offset: 0xC */ + __IO uint32_t MIER; /**< Module Interrupt Enable, offset: 0x10 */ + __IO uint32_t SETTEN; /**< Set Timer Enable, offset: 0x14 */ + __IO uint32_t CLRTEN; /**< Clear Timer Enable, offset: 0x18 */ + uint8_t RESERVED_0[4]; + struct { /* offset: 0x20, array step: 0x10 */ + __IO uint32_t TVAL; /**< Timer Value, array offset: 0x20, array step: 0x10 */ + __I uint32_t CVAL; /**< Current Timer Value, array offset: 0x24, array step: 0x10 */ + __IO uint32_t TCTRL; /**< Timer Control, array offset: 0x28, array step: 0x10 */ + uint8_t RESERVED_0[4]; + } CHANNEL[4]; +} LPIT_Type; + +/* ---------------------------------------------------------------------------- + -- LPIT Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup LPIT_Register_Masks LPIT Register Masks + * @{ + */ + +/*! @name VERID - Version ID */ +/*! @{ */ + +#define LPIT_VERID_FEATURE_MASK (0xFFFFU) +#define LPIT_VERID_FEATURE_SHIFT (0U) +/*! FEATURE - Feature Number */ +#define LPIT_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << LPIT_VERID_FEATURE_SHIFT)) & LPIT_VERID_FEATURE_MASK) + +#define LPIT_VERID_MINOR_MASK (0xFF0000U) +#define LPIT_VERID_MINOR_SHIFT (16U) +/*! MINOR - Minor Version Number */ +#define LPIT_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << LPIT_VERID_MINOR_SHIFT)) & LPIT_VERID_MINOR_MASK) + +#define LPIT_VERID_MAJOR_MASK (0xFF000000U) +#define LPIT_VERID_MAJOR_SHIFT (24U) +/*! MAJOR - Major Version Number */ +#define LPIT_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << LPIT_VERID_MAJOR_SHIFT)) & LPIT_VERID_MAJOR_MASK) +/*! @} */ + +/*! @name PARAM - Parameter */ +/*! @{ */ + +#define LPIT_PARAM_CHANNEL_MASK (0xFFU) +#define LPIT_PARAM_CHANNEL_SHIFT (0U) +/*! CHANNEL - Number of Timer Channels */ +#define LPIT_PARAM_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << LPIT_PARAM_CHANNEL_SHIFT)) & LPIT_PARAM_CHANNEL_MASK) + +#define LPIT_PARAM_EXT_TRIG_MASK (0xFF00U) +#define LPIT_PARAM_EXT_TRIG_SHIFT (8U) +/*! EXT_TRIG - Number of External Trigger Inputs */ +#define LPIT_PARAM_EXT_TRIG(x) (((uint32_t)(((uint32_t)(x)) << LPIT_PARAM_EXT_TRIG_SHIFT)) & LPIT_PARAM_EXT_TRIG_MASK) +/*! @} */ + +/*! @name MCR - Module Control */ +/*! @{ */ + +#define LPIT_MCR_M_CEN_MASK (0x1U) +#define LPIT_MCR_M_CEN_SHIFT (0U) +/*! M_CEN - Module Clock Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPIT_MCR_M_CEN(x) (((uint32_t)(((uint32_t)(x)) << LPIT_MCR_M_CEN_SHIFT)) & LPIT_MCR_M_CEN_MASK) + +#define LPIT_MCR_SW_RST_MASK (0x2U) +#define LPIT_MCR_SW_RST_SHIFT (1U) +/*! SW_RST - Software Reset + * 0b0..Does not reset + * 0b1..Resets + */ +#define LPIT_MCR_SW_RST(x) (((uint32_t)(((uint32_t)(x)) << LPIT_MCR_SW_RST_SHIFT)) & LPIT_MCR_SW_RST_MASK) + +#define LPIT_MCR_DOZE_EN_MASK (0x4U) +#define LPIT_MCR_DOZE_EN_SHIFT (2U) +/*! DOZE_EN - DOZE Mode Enable + * 0b0..Stops timer channels + * 0b1..Allows timer channels to continue running + */ +#define LPIT_MCR_DOZE_EN(x) (((uint32_t)(((uint32_t)(x)) << LPIT_MCR_DOZE_EN_SHIFT)) & LPIT_MCR_DOZE_EN_MASK) + +#define LPIT_MCR_DBG_EN_MASK (0x8U) +#define LPIT_MCR_DBG_EN_SHIFT (3U) +/*! DBG_EN - Debug Mode Enable + * 0b0..Stops timer channels + * 0b1..Allows timer channels to continue running + */ +#define LPIT_MCR_DBG_EN(x) (((uint32_t)(((uint32_t)(x)) << LPIT_MCR_DBG_EN_SHIFT)) & LPIT_MCR_DBG_EN_MASK) +/*! @} */ + +/*! @name MSR - Module Status */ +/*! @{ */ + +#define LPIT_MSR_TIF0_MASK (0x1U) +#define LPIT_MSR_TIF0_SHIFT (0U) +/*! TIF0 - Channel 0 Timer Interrupt Flag + * 0b0..Not timed out + * 0b0..No effect + * 0b1..Timed out + * 0b1..Clear the flag + */ +#define LPIT_MSR_TIF0(x) (((uint32_t)(((uint32_t)(x)) << LPIT_MSR_TIF0_SHIFT)) & LPIT_MSR_TIF0_MASK) + +#define LPIT_MSR_TIF1_MASK (0x2U) +#define LPIT_MSR_TIF1_SHIFT (1U) +/*! TIF1 - Channel 1 Timer Interrupt Flag + * 0b0..Not timed out + * 0b0..No effect + * 0b1..Timed out + * 0b1..Clear the flag + */ +#define LPIT_MSR_TIF1(x) (((uint32_t)(((uint32_t)(x)) << LPIT_MSR_TIF1_SHIFT)) & LPIT_MSR_TIF1_MASK) + +#define LPIT_MSR_TIF2_MASK (0x4U) +#define LPIT_MSR_TIF2_SHIFT (2U) +/*! TIF2 - Channel 2 Timer Interrupt Flag + * 0b0..Not timed out + * 0b0..No effect + * 0b1..Timed out + * 0b1..Clear the flag + */ +#define LPIT_MSR_TIF2(x) (((uint32_t)(((uint32_t)(x)) << LPIT_MSR_TIF2_SHIFT)) & LPIT_MSR_TIF2_MASK) + +#define LPIT_MSR_TIF3_MASK (0x8U) +#define LPIT_MSR_TIF3_SHIFT (3U) +/*! TIF3 - Channel 3 Timer Interrupt Flag + * 0b0..Not timed out + * 0b0..No effect + * 0b1..Timed out + * 0b1..Clear the flag + */ +#define LPIT_MSR_TIF3(x) (((uint32_t)(((uint32_t)(x)) << LPIT_MSR_TIF3_SHIFT)) & LPIT_MSR_TIF3_MASK) +/*! @} */ + +/*! @name MIER - Module Interrupt Enable */ +/*! @{ */ + +#define LPIT_MIER_TIE0_MASK (0x1U) +#define LPIT_MIER_TIE0_SHIFT (0U) +/*! TIE0 - Channel 0 Timer Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPIT_MIER_TIE0(x) (((uint32_t)(((uint32_t)(x)) << LPIT_MIER_TIE0_SHIFT)) & LPIT_MIER_TIE0_MASK) + +#define LPIT_MIER_TIE1_MASK (0x2U) +#define LPIT_MIER_TIE1_SHIFT (1U) +/*! TIE1 - Channel 1 Timer Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPIT_MIER_TIE1(x) (((uint32_t)(((uint32_t)(x)) << LPIT_MIER_TIE1_SHIFT)) & LPIT_MIER_TIE1_MASK) + +#define LPIT_MIER_TIE2_MASK (0x4U) +#define LPIT_MIER_TIE2_SHIFT (2U) +/*! TIE2 - Channel 2 Timer Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPIT_MIER_TIE2(x) (((uint32_t)(((uint32_t)(x)) << LPIT_MIER_TIE2_SHIFT)) & LPIT_MIER_TIE2_MASK) + +#define LPIT_MIER_TIE3_MASK (0x8U) +#define LPIT_MIER_TIE3_SHIFT (3U) +/*! TIE3 - Channel 3 Timer Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPIT_MIER_TIE3(x) (((uint32_t)(((uint32_t)(x)) << LPIT_MIER_TIE3_SHIFT)) & LPIT_MIER_TIE3_MASK) +/*! @} */ + +/*! @name SETTEN - Set Timer Enable */ +/*! @{ */ + +#define LPIT_SETTEN_SET_T_EN_0_MASK (0x1U) +#define LPIT_SETTEN_SET_T_EN_0_SHIFT (0U) +/*! SET_T_EN_0 - Set Timer 0 Enable + * 0b0..No effect + * 0b1..Enables timer channel 0 + */ +#define LPIT_SETTEN_SET_T_EN_0(x) (((uint32_t)(((uint32_t)(x)) << LPIT_SETTEN_SET_T_EN_0_SHIFT)) & LPIT_SETTEN_SET_T_EN_0_MASK) + +#define LPIT_SETTEN_SET_T_EN_1_MASK (0x2U) +#define LPIT_SETTEN_SET_T_EN_1_SHIFT (1U) +/*! SET_T_EN_1 - Set Timer 1 Enable + * 0b0..No Effect + * 0b1..Enables timer channel 1 + */ +#define LPIT_SETTEN_SET_T_EN_1(x) (((uint32_t)(((uint32_t)(x)) << LPIT_SETTEN_SET_T_EN_1_SHIFT)) & LPIT_SETTEN_SET_T_EN_1_MASK) + +#define LPIT_SETTEN_SET_T_EN_2_MASK (0x4U) +#define LPIT_SETTEN_SET_T_EN_2_SHIFT (2U) +/*! SET_T_EN_2 - Set Timer 2 Enable + * 0b0..No Effect + * 0b1..Enables timer channel 2 + */ +#define LPIT_SETTEN_SET_T_EN_2(x) (((uint32_t)(((uint32_t)(x)) << LPIT_SETTEN_SET_T_EN_2_SHIFT)) & LPIT_SETTEN_SET_T_EN_2_MASK) + +#define LPIT_SETTEN_SET_T_EN_3_MASK (0x8U) +#define LPIT_SETTEN_SET_T_EN_3_SHIFT (3U) +/*! SET_T_EN_3 - Set Timer 3 Enable + * 0b0..No effect + * 0b1..Enables timer channel 3 + */ +#define LPIT_SETTEN_SET_T_EN_3(x) (((uint32_t)(((uint32_t)(x)) << LPIT_SETTEN_SET_T_EN_3_SHIFT)) & LPIT_SETTEN_SET_T_EN_3_MASK) +/*! @} */ + +/*! @name CLRTEN - Clear Timer Enable */ +/*! @{ */ + +#define LPIT_CLRTEN_CLR_T_EN_0_MASK (0x1U) +#define LPIT_CLRTEN_CLR_T_EN_0_SHIFT (0U) +/*! CLR_T_EN_0 - Clear Timer 0 Enable + * 0b0..No action + * 0b1..Turns TCTRL0[T_EN] = 0 for timer channel 0 + */ +#define LPIT_CLRTEN_CLR_T_EN_0(x) (((uint32_t)(((uint32_t)(x)) << LPIT_CLRTEN_CLR_T_EN_0_SHIFT)) & LPIT_CLRTEN_CLR_T_EN_0_MASK) + +#define LPIT_CLRTEN_CLR_T_EN_1_MASK (0x2U) +#define LPIT_CLRTEN_CLR_T_EN_1_SHIFT (1U) +/*! CLR_T_EN_1 - Clear Timer 1 Enable + * 0b0..No action + * 0b1..Turns TCTRL1[T_EN] = 0 for timer channel 1 + */ +#define LPIT_CLRTEN_CLR_T_EN_1(x) (((uint32_t)(((uint32_t)(x)) << LPIT_CLRTEN_CLR_T_EN_1_SHIFT)) & LPIT_CLRTEN_CLR_T_EN_1_MASK) + +#define LPIT_CLRTEN_CLR_T_EN_2_MASK (0x4U) +#define LPIT_CLRTEN_CLR_T_EN_2_SHIFT (2U) +/*! CLR_T_EN_2 - Clear Timer 2 Enable + * 0b0..No action + * 0b1..Turns TCTRL2[T_EN] = 0 for timer channel 2 + */ +#define LPIT_CLRTEN_CLR_T_EN_2(x) (((uint32_t)(((uint32_t)(x)) << LPIT_CLRTEN_CLR_T_EN_2_SHIFT)) & LPIT_CLRTEN_CLR_T_EN_2_MASK) + +#define LPIT_CLRTEN_CLR_T_EN_3_MASK (0x8U) +#define LPIT_CLRTEN_CLR_T_EN_3_SHIFT (3U) +/*! CLR_T_EN_3 - Clear Timer 3 Enable + * 0b0..No action + * 0b1..Turns TCTRL3[T_EN] = 0 for timer channel 3 + */ +#define LPIT_CLRTEN_CLR_T_EN_3(x) (((uint32_t)(((uint32_t)(x)) << LPIT_CLRTEN_CLR_T_EN_3_SHIFT)) & LPIT_CLRTEN_CLR_T_EN_3_MASK) +/*! @} */ + +/*! @name TVAL - Timer Value */ +/*! @{ */ + +#define LPIT_TVAL_TMR_VAL_MASK (0xFFFFFFFFU) +#define LPIT_TVAL_TMR_VAL_SHIFT (0U) +/*! TMR_VAL - Timer Value + * 0b00000000000000000000000000000000, 0b00000000000000000000000000000001..Invalid load value in Compare mode + * 0b00000000000000000000000000000010-0b11111111111111111111111111111111..In Compare mode: the value to be loaded; in Capture mode, the value of the timer + */ +#define LPIT_TVAL_TMR_VAL(x) (((uint32_t)(((uint32_t)(x)) << LPIT_TVAL_TMR_VAL_SHIFT)) & LPIT_TVAL_TMR_VAL_MASK) +/*! @} */ + +/* The count of LPIT_TVAL */ +#define LPIT_TVAL_COUNT (4U) + +/*! @name CVAL - Current Timer Value */ +/*! @{ */ + +#define LPIT_CVAL_TMR_CUR_VAL_MASK (0xFFFFFFFFU) +#define LPIT_CVAL_TMR_CUR_VAL_SHIFT (0U) +/*! TMR_CUR_VAL - Current Timer Value */ +#define LPIT_CVAL_TMR_CUR_VAL(x) (((uint32_t)(((uint32_t)(x)) << LPIT_CVAL_TMR_CUR_VAL_SHIFT)) & LPIT_CVAL_TMR_CUR_VAL_MASK) +/*! @} */ + +/* The count of LPIT_CVAL */ +#define LPIT_CVAL_COUNT (4U) + +/*! @name TCTRL - Timer Control */ +/*! @{ */ + +#define LPIT_TCTRL_T_EN_MASK (0x1U) +#define LPIT_TCTRL_T_EN_SHIFT (0U) +/*! T_EN - Timer Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPIT_TCTRL_T_EN(x) (((uint32_t)(((uint32_t)(x)) << LPIT_TCTRL_T_EN_SHIFT)) & LPIT_TCTRL_T_EN_MASK) + +#define LPIT_TCTRL_CHAIN_MASK (0x2U) +#define LPIT_TCTRL_CHAIN_SHIFT (1U) +/*! CHAIN - Chain Channel + * 0b0..Disabled + * 0b1..Enabled + */ +#define LPIT_TCTRL_CHAIN(x) (((uint32_t)(((uint32_t)(x)) << LPIT_TCTRL_CHAIN_SHIFT)) & LPIT_TCTRL_CHAIN_MASK) + +#define LPIT_TCTRL_MODE_MASK (0xCU) +#define LPIT_TCTRL_MODE_SHIFT (2U) +/*! MODE - Timer Operation Mode + * 0b00..32-bit periodic counter + * 0b01..Dual 16-bit periodic counter + * 0b10..32-bit trigger accumulator + * 0b11..32-bit trigger input capture + */ +#define LPIT_TCTRL_MODE(x) (((uint32_t)(((uint32_t)(x)) << LPIT_TCTRL_MODE_SHIFT)) & LPIT_TCTRL_MODE_MASK) + +#define LPIT_TCTRL_TSOT_MASK (0x10000U) +#define LPIT_TCTRL_TSOT_SHIFT (16U) +/*! TSOT - Timer Start on Trigger + * 0b0..Immediately + * 0b1..When a rising edge is detected + */ +#define LPIT_TCTRL_TSOT(x) (((uint32_t)(((uint32_t)(x)) << LPIT_TCTRL_TSOT_SHIFT)) & LPIT_TCTRL_TSOT_MASK) + +#define LPIT_TCTRL_TSOI_MASK (0x20000U) +#define LPIT_TCTRL_TSOI_SHIFT (17U) +/*! TSOI - Timer Stop on Interrupt + * 0b0..Does not stop + * 0b1..Stops + */ +#define LPIT_TCTRL_TSOI(x) (((uint32_t)(((uint32_t)(x)) << LPIT_TCTRL_TSOI_SHIFT)) & LPIT_TCTRL_TSOI_MASK) + +#define LPIT_TCTRL_TROT_MASK (0x40000U) +#define LPIT_TCTRL_TROT_SHIFT (18U) +/*! TROT - Timer Reload on Trigger + * 0b0..Does not reload + * 0b1..Reloads + */ +#define LPIT_TCTRL_TROT(x) (((uint32_t)(((uint32_t)(x)) << LPIT_TCTRL_TROT_SHIFT)) & LPIT_TCTRL_TROT_MASK) + +#define LPIT_TCTRL_TRG_SRC_MASK (0x800000U) +#define LPIT_TCTRL_TRG_SRC_SHIFT (23U) +/*! TRG_SRC - Trigger Source + * 0b0..External + * 0b1..Internal + */ +#define LPIT_TCTRL_TRG_SRC(x) (((uint32_t)(((uint32_t)(x)) << LPIT_TCTRL_TRG_SRC_SHIFT)) & LPIT_TCTRL_TRG_SRC_MASK) + +#define LPIT_TCTRL_TRG_SEL_MASK (0xF000000U) +#define LPIT_TCTRL_TRG_SEL_SHIFT (24U) +/*! TRG_SEL - Trigger Select + * 0b0000-0b0011..Timer channel 0-3 trigger source + * 0b0100-0b1111..Reserved + */ +#define LPIT_TCTRL_TRG_SEL(x) (((uint32_t)(((uint32_t)(x)) << LPIT_TCTRL_TRG_SEL_SHIFT)) & LPIT_TCTRL_TRG_SEL_MASK) +/*! @} */ + +/* The count of LPIT_TCTRL */ +#define LPIT_TCTRL_COUNT (4U) + + +/*! + * @} + */ /* end of group LPIT_Register_Masks */ + + +/* LPIT - Peripheral instance base addresses */ +/** Peripheral LPIT1 base address */ +#define LPIT1_BASE (0x442F0000u) +/** Peripheral LPIT1 base pointer */ +#define LPIT1 ((LPIT_Type *)LPIT1_BASE) +/** Peripheral LPIT2 base address */ +#define LPIT2_BASE (0x424C0000u) +/** Peripheral LPIT2 base pointer */ +#define LPIT2 ((LPIT_Type *)LPIT2_BASE) +/** Array initializer of LPIT peripheral base addresses */ +#define LPIT_BASE_ADDRS { 0u, LPIT1_BASE, LPIT2_BASE } +/** Array initializer of LPIT peripheral base pointers */ +#define LPIT_BASE_PTRS { (LPIT_Type *)0u, LPIT1, LPIT2 } + +/*! + * @} + */ /* end of group LPIT_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- LPSPI Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup LPSPI_Peripheral_Access_Layer LPSPI Peripheral Access Layer + * @{ + */ + +/** LPSPI - Register Layout Typedef */ +typedef struct { + __I uint32_t VERID; /**< Version ID, offset: 0x0 */ + __I uint32_t PARAM; /**< Parameter, offset: 0x4 */ + uint8_t RESERVED_0[8]; + __IO uint32_t CR; /**< Control, offset: 0x10 */ + __IO uint32_t SR; /**< Status, offset: 0x14 */ + __IO uint32_t IER; /**< Interrupt Enable, offset: 0x18 */ + __IO uint32_t DER; /**< DMA Enable, offset: 0x1C */ + __IO uint32_t CFGR0; /**< Configuration 0, offset: 0x20 */ + __IO uint32_t CFGR1; /**< Configuration 1, offset: 0x24 */ + uint8_t RESERVED_1[8]; + __IO uint32_t DMR0; /**< Data Match 0, offset: 0x30 */ + __IO uint32_t DMR1; /**< Data Match 1, offset: 0x34 */ + uint8_t RESERVED_2[8]; + __IO uint32_t CCR; /**< Clock Configuration, offset: 0x40 */ + __IO uint32_t CCR1; /**< Clock Configuration 1, offset: 0x44 */ + uint8_t RESERVED_3[16]; + __IO uint32_t FCR; /**< FIFO Control, offset: 0x58 */ + __I uint32_t FSR; /**< FIFO Status, offset: 0x5C */ + __IO uint32_t TCR; /**< Transmit Command, offset: 0x60 */ + __O uint32_t TDR; /**< Transmit Data, offset: 0x64 */ + uint8_t RESERVED_4[8]; + __I uint32_t RSR; /**< Receive Status, offset: 0x70 */ + __I uint32_t RDR; /**< Receive Data, offset: 0x74 */ + __I uint32_t RDROR; /**< Receive Data Read Only, offset: 0x78 */ + uint8_t RESERVED_5[896]; + __O uint32_t TCBR; /**< Transmit Command Burst, offset: 0x3FC */ + __O uint32_t TDBR[128]; /**< Transmit Data Burst, array offset: 0x400, array step: 0x4 */ + __I uint32_t RDBR[128]; /**< Receive Data Burst, array offset: 0x600, array step: 0x4 */ +} LPSPI_Type; + +/* ---------------------------------------------------------------------------- + -- LPSPI Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup LPSPI_Register_Masks LPSPI Register Masks + * @{ + */ + +/*! @name VERID - Version ID */ +/*! @{ */ + +#define LPSPI_VERID_FEATURE_MASK (0xFFFFU) +#define LPSPI_VERID_FEATURE_SHIFT (0U) +/*! FEATURE - Module Identification Number + * 0b0000000000000100..Standard feature set supporting a 32-bit shift register. + */ +#define LPSPI_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_VERID_FEATURE_SHIFT)) & LPSPI_VERID_FEATURE_MASK) + +#define LPSPI_VERID_MINOR_MASK (0xFF0000U) +#define LPSPI_VERID_MINOR_SHIFT (16U) +/*! MINOR - Minor Version Number */ +#define LPSPI_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_VERID_MINOR_SHIFT)) & LPSPI_VERID_MINOR_MASK) + +#define LPSPI_VERID_MAJOR_MASK (0xFF000000U) +#define LPSPI_VERID_MAJOR_SHIFT (24U) +/*! MAJOR - Major Version Number */ +#define LPSPI_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_VERID_MAJOR_SHIFT)) & LPSPI_VERID_MAJOR_MASK) +/*! @} */ + +/*! @name PARAM - Parameter */ +/*! @{ */ + +#define LPSPI_PARAM_TXFIFO_MASK (0xFFU) +#define LPSPI_PARAM_TXFIFO_SHIFT (0U) +/*! TXFIFO - Transmit FIFO Size */ +#define LPSPI_PARAM_TXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_PARAM_TXFIFO_SHIFT)) & LPSPI_PARAM_TXFIFO_MASK) + +#define LPSPI_PARAM_RXFIFO_MASK (0xFF00U) +#define LPSPI_PARAM_RXFIFO_SHIFT (8U) +/*! RXFIFO - Receive FIFO Size */ +#define LPSPI_PARAM_RXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_PARAM_RXFIFO_SHIFT)) & LPSPI_PARAM_RXFIFO_MASK) + +#define LPSPI_PARAM_PCSNUM_MASK (0xFF0000U) +#define LPSPI_PARAM_PCSNUM_SHIFT (16U) +/*! PCSNUM - PCS Number */ +#define LPSPI_PARAM_PCSNUM(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_PARAM_PCSNUM_SHIFT)) & LPSPI_PARAM_PCSNUM_MASK) +/*! @} */ + +/*! @name CR - Control */ +/*! @{ */ + +#define LPSPI_CR_MEN_MASK (0x1U) +#define LPSPI_CR_MEN_SHIFT (0U) +/*! MEN - Module Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPSPI_CR_MEN(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_MEN_SHIFT)) & LPSPI_CR_MEN_MASK) + +#define LPSPI_CR_RST_MASK (0x2U) +#define LPSPI_CR_RST_SHIFT (1U) +/*! RST - Software Reset + * 0b0..Not reset + * 0b1..Reset + */ +#define LPSPI_CR_RST(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_RST_SHIFT)) & LPSPI_CR_RST_MASK) + +#define LPSPI_CR_DOZEN_MASK (0x4U) +#define LPSPI_CR_DOZEN_SHIFT (2U) +/*! DOZEN - Doze Mode Enable + * 0b0..Enable + * 0b1..Disable + */ +#define LPSPI_CR_DOZEN(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_DOZEN_SHIFT)) & LPSPI_CR_DOZEN_MASK) + +#define LPSPI_CR_DBGEN_MASK (0x8U) +#define LPSPI_CR_DBGEN_SHIFT (3U) +/*! DBGEN - Debug Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPSPI_CR_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_DBGEN_SHIFT)) & LPSPI_CR_DBGEN_MASK) + +#define LPSPI_CR_RTF_MASK (0x100U) +#define LPSPI_CR_RTF_SHIFT (8U) +/*! RTF - Reset Transmit FIFO + * 0b0..No effect + * 0b1..Reset + */ +#define LPSPI_CR_RTF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_RTF_SHIFT)) & LPSPI_CR_RTF_MASK) + +#define LPSPI_CR_RRF_MASK (0x200U) +#define LPSPI_CR_RRF_SHIFT (9U) +/*! RRF - Reset Receive FIFO + * 0b0..No effect + * 0b1..Reset + */ +#define LPSPI_CR_RRF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_RRF_SHIFT)) & LPSPI_CR_RRF_MASK) +/*! @} */ + +/*! @name SR - Status */ +/*! @{ */ + +#define LPSPI_SR_TDF_MASK (0x1U) +#define LPSPI_SR_TDF_SHIFT (0U) +/*! TDF - Transmit Data Flag + * 0b0..Transmit data not requested + * 0b1..Transmit data requested + */ +#define LPSPI_SR_TDF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_TDF_SHIFT)) & LPSPI_SR_TDF_MASK) + +#define LPSPI_SR_RDF_MASK (0x2U) +#define LPSPI_SR_RDF_SHIFT (1U) +/*! RDF - Receive Data Flag + * 0b0..Receive data not ready + * 0b1..Receive data ready + */ +#define LPSPI_SR_RDF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_RDF_SHIFT)) & LPSPI_SR_RDF_MASK) + +#define LPSPI_SR_WCF_MASK (0x100U) +#define LPSPI_SR_WCF_SHIFT (8U) +/*! WCF - Word Complete Flag + * 0b0..Not complete + * 0b0..No effect + * 0b1..Complete + * 0b1..Clear the flag + */ +#define LPSPI_SR_WCF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_WCF_SHIFT)) & LPSPI_SR_WCF_MASK) + +#define LPSPI_SR_FCF_MASK (0x200U) +#define LPSPI_SR_FCF_SHIFT (9U) +/*! FCF - Frame Complete Flag + * 0b0..Not complete + * 0b0..No effect + * 0b1..Complete + * 0b1..Clear the flag + */ +#define LPSPI_SR_FCF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_FCF_SHIFT)) & LPSPI_SR_FCF_MASK) + +#define LPSPI_SR_TCF_MASK (0x400U) +#define LPSPI_SR_TCF_SHIFT (10U) +/*! TCF - Transfer Complete Flag + * 0b0..Not complete + * 0b0..No effect + * 0b1..Complete + * 0b1..Clear the flag + */ +#define LPSPI_SR_TCF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_TCF_SHIFT)) & LPSPI_SR_TCF_MASK) + +#define LPSPI_SR_TEF_MASK (0x800U) +#define LPSPI_SR_TEF_SHIFT (11U) +/*! TEF - Transmit Error Flag + * 0b0..No underrun + * 0b0..No effect + * 0b1..Underrun + * 0b1..Clear the flag + */ +#define LPSPI_SR_TEF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_TEF_SHIFT)) & LPSPI_SR_TEF_MASK) + +#define LPSPI_SR_REF_MASK (0x1000U) +#define LPSPI_SR_REF_SHIFT (12U) +/*! REF - Receive Error Flag + * 0b0..No overflow + * 0b0..No effect + * 0b1..Overflow + * 0b1..Clear the flag + */ +#define LPSPI_SR_REF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_REF_SHIFT)) & LPSPI_SR_REF_MASK) + +#define LPSPI_SR_DMF_MASK (0x2000U) +#define LPSPI_SR_DMF_SHIFT (13U) +/*! DMF - Data Match Flag + * 0b0..No match + * 0b0..No effect + * 0b1..Match + * 0b1..Clear the flag + */ +#define LPSPI_SR_DMF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_DMF_SHIFT)) & LPSPI_SR_DMF_MASK) + +#define LPSPI_SR_MBF_MASK (0x1000000U) +#define LPSPI_SR_MBF_SHIFT (24U) +/*! MBF - Module Busy Flag + * 0b0..LPSPI is idle + * 0b1..LPSPI is busy + */ +#define LPSPI_SR_MBF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_MBF_SHIFT)) & LPSPI_SR_MBF_MASK) +/*! @} */ + +/*! @name IER - Interrupt Enable */ +/*! @{ */ + +#define LPSPI_IER_TDIE_MASK (0x1U) +#define LPSPI_IER_TDIE_SHIFT (0U) +/*! TDIE - Transmit Data Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPSPI_IER_TDIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_TDIE_SHIFT)) & LPSPI_IER_TDIE_MASK) + +#define LPSPI_IER_RDIE_MASK (0x2U) +#define LPSPI_IER_RDIE_SHIFT (1U) +/*! RDIE - Receive Data Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPSPI_IER_RDIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_RDIE_SHIFT)) & LPSPI_IER_RDIE_MASK) + +#define LPSPI_IER_WCIE_MASK (0x100U) +#define LPSPI_IER_WCIE_SHIFT (8U) +/*! WCIE - Word Complete Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPSPI_IER_WCIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_WCIE_SHIFT)) & LPSPI_IER_WCIE_MASK) + +#define LPSPI_IER_FCIE_MASK (0x200U) +#define LPSPI_IER_FCIE_SHIFT (9U) +/*! FCIE - Frame Complete Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPSPI_IER_FCIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_FCIE_SHIFT)) & LPSPI_IER_FCIE_MASK) + +#define LPSPI_IER_TCIE_MASK (0x400U) +#define LPSPI_IER_TCIE_SHIFT (10U) +/*! TCIE - Transfer Complete Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPSPI_IER_TCIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_TCIE_SHIFT)) & LPSPI_IER_TCIE_MASK) + +#define LPSPI_IER_TEIE_MASK (0x800U) +#define LPSPI_IER_TEIE_SHIFT (11U) +/*! TEIE - Transmit Error Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPSPI_IER_TEIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_TEIE_SHIFT)) & LPSPI_IER_TEIE_MASK) + +#define LPSPI_IER_REIE_MASK (0x1000U) +#define LPSPI_IER_REIE_SHIFT (12U) +/*! REIE - Receive Error Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPSPI_IER_REIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_REIE_SHIFT)) & LPSPI_IER_REIE_MASK) + +#define LPSPI_IER_DMIE_MASK (0x2000U) +#define LPSPI_IER_DMIE_SHIFT (13U) +/*! DMIE - Data Match Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPSPI_IER_DMIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_DMIE_SHIFT)) & LPSPI_IER_DMIE_MASK) +/*! @} */ + +/*! @name DER - DMA Enable */ +/*! @{ */ + +#define LPSPI_DER_TDDE_MASK (0x1U) +#define LPSPI_DER_TDDE_SHIFT (0U) +/*! TDDE - Transmit Data DMA Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPSPI_DER_TDDE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_DER_TDDE_SHIFT)) & LPSPI_DER_TDDE_MASK) + +#define LPSPI_DER_RDDE_MASK (0x2U) +#define LPSPI_DER_RDDE_SHIFT (1U) +/*! RDDE - Receive Data DMA Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPSPI_DER_RDDE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_DER_RDDE_SHIFT)) & LPSPI_DER_RDDE_MASK) + +#define LPSPI_DER_FCDE_MASK (0x200U) +#define LPSPI_DER_FCDE_SHIFT (9U) +/*! FCDE - Frame Complete DMA Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPSPI_DER_FCDE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_DER_FCDE_SHIFT)) & LPSPI_DER_FCDE_MASK) +/*! @} */ + +/*! @name CFGR0 - Configuration 0 */ +/*! @{ */ + +#define LPSPI_CFGR0_CIRFIFO_MASK (0x100U) +#define LPSPI_CFGR0_CIRFIFO_SHIFT (8U) +/*! CIRFIFO - Circular FIFO Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPSPI_CFGR0_CIRFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_CIRFIFO_SHIFT)) & LPSPI_CFGR0_CIRFIFO_MASK) + +#define LPSPI_CFGR0_RDMO_MASK (0x200U) +#define LPSPI_CFGR0_RDMO_SHIFT (9U) +/*! RDMO - Receive Data Match Only + * 0b0..Disable + * 0b1..Enable + */ +#define LPSPI_CFGR0_RDMO(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_RDMO_SHIFT)) & LPSPI_CFGR0_RDMO_MASK) +/*! @} */ + +/*! @name CFGR1 - Configuration 1 */ +/*! @{ */ + +#define LPSPI_CFGR1_MASTER_MASK (0x1U) +#define LPSPI_CFGR1_MASTER_SHIFT (0U) +/*! MASTER - Controller Mode + * 0b0..Peripheral mode + * 0b1..Controller mode + */ +#define LPSPI_CFGR1_MASTER(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_MASTER_SHIFT)) & LPSPI_CFGR1_MASTER_MASK) + +#define LPSPI_CFGR1_SAMPLE_MASK (0x2U) +#define LPSPI_CFGR1_SAMPLE_SHIFT (1U) +/*! SAMPLE - Sample Point + * 0b0..SCK edge + * 0b1..Delayed SCK edge + */ +#define LPSPI_CFGR1_SAMPLE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_SAMPLE_SHIFT)) & LPSPI_CFGR1_SAMPLE_MASK) + +#define LPSPI_CFGR1_AUTOPCS_MASK (0x4U) +#define LPSPI_CFGR1_AUTOPCS_SHIFT (2U) +/*! AUTOPCS - Automatic PCS + * 0b0..Disable + * 0b1..Enable + */ +#define LPSPI_CFGR1_AUTOPCS(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_AUTOPCS_SHIFT)) & LPSPI_CFGR1_AUTOPCS_MASK) + +#define LPSPI_CFGR1_NOSTALL_MASK (0x8U) +#define LPSPI_CFGR1_NOSTALL_SHIFT (3U) +/*! NOSTALL - No Stall + * 0b0..Disable + * 0b1..Enable + */ +#define LPSPI_CFGR1_NOSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_NOSTALL_SHIFT)) & LPSPI_CFGR1_NOSTALL_MASK) + +#define LPSPI_CFGR1_PARTIAL_MASK (0x10U) +#define LPSPI_CFGR1_PARTIAL_SHIFT (4U) +/*! PARTIAL - Partial Enable + * 0b0..Discard + * 0b1..Store + */ +#define LPSPI_CFGR1_PARTIAL(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_PARTIAL_SHIFT)) & LPSPI_CFGR1_PARTIAL_MASK) + +#define LPSPI_CFGR1_PCSPOL_MASK (0x700U) /* Merged from fields with different position or width, of widths (2, 3), largest definition used */ +#define LPSPI_CFGR1_PCSPOL_SHIFT (8U) +/*! PCSPOL - Peripheral Chip Select Polarity + * 0b000..Active low + * 0b001..Active high + */ +#define LPSPI_CFGR1_PCSPOL(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_PCSPOL_SHIFT)) & LPSPI_CFGR1_PCSPOL_MASK) /* Merged from fields with different position or width, of widths (2, 3), largest definition used */ + +#define LPSPI_CFGR1_MATCFG_MASK (0x70000U) +#define LPSPI_CFGR1_MATCFG_SHIFT (16U) +/*! MATCFG - Match Configuration + * 0b000..Match is disabled + * 0b001.. + * 0b010..Match first data word with compare word + * 0b011..Match any data word with compare word + * 0b100..Sequential match, first data word + * 0b101..Sequential match, any data word + * 0b110..Match first data word (masked) with compare word (masked) + * 0b111..Match any data word (masked) with compare word (masked) + */ +#define LPSPI_CFGR1_MATCFG(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_MATCFG_SHIFT)) & LPSPI_CFGR1_MATCFG_MASK) + +#define LPSPI_CFGR1_PINCFG_MASK (0x3000000U) +#define LPSPI_CFGR1_PINCFG_SHIFT (24U) +/*! PINCFG - Pin Configuration + * 0b00..SIN is used for input data; SOUT is used for output data + * 0b01..SIN is used for both input and output data; only half-duplex serial transfers are supported + * 0b10..SOUT is used for both input and output data; only half-duplex serial transfers are supported + * 0b11..SOUT is used for input data; SIN is used for output data + */ +#define LPSPI_CFGR1_PINCFG(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_PINCFG_SHIFT)) & LPSPI_CFGR1_PINCFG_MASK) + +#define LPSPI_CFGR1_OUTCFG_MASK (0x4000000U) +#define LPSPI_CFGR1_OUTCFG_SHIFT (26U) +/*! OUTCFG - Output Configuration + * 0b0..Retain last value + * 0b1..3-stated + */ +#define LPSPI_CFGR1_OUTCFG(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_OUTCFG_SHIFT)) & LPSPI_CFGR1_OUTCFG_MASK) +/*! @} */ + +/*! @name DMR0 - Data Match 0 */ +/*! @{ */ + +#define LPSPI_DMR0_MATCH0_MASK (0xFFFFFFFFU) +#define LPSPI_DMR0_MATCH0_SHIFT (0U) +/*! MATCH0 - Match 0 Value */ +#define LPSPI_DMR0_MATCH0(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_DMR0_MATCH0_SHIFT)) & LPSPI_DMR0_MATCH0_MASK) +/*! @} */ + +/*! @name DMR1 - Data Match 1 */ +/*! @{ */ + +#define LPSPI_DMR1_MATCH1_MASK (0xFFFFFFFFU) +#define LPSPI_DMR1_MATCH1_SHIFT (0U) +/*! MATCH1 - Match 1 Value */ +#define LPSPI_DMR1_MATCH1(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_DMR1_MATCH1_SHIFT)) & LPSPI_DMR1_MATCH1_MASK) +/*! @} */ + +/*! @name CCR - Clock Configuration */ +/*! @{ */ + +#define LPSPI_CCR_SCKDIV_MASK (0xFFU) +#define LPSPI_CCR_SCKDIV_SHIFT (0U) +/*! SCKDIV - SCK Divider */ +#define LPSPI_CCR_SCKDIV(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR_SCKDIV_SHIFT)) & LPSPI_CCR_SCKDIV_MASK) + +#define LPSPI_CCR_DBT_MASK (0xFF00U) +#define LPSPI_CCR_DBT_SHIFT (8U) +/*! DBT - Delay Between Transfers */ +#define LPSPI_CCR_DBT(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR_DBT_SHIFT)) & LPSPI_CCR_DBT_MASK) + +#define LPSPI_CCR_PCSSCK_MASK (0xFF0000U) +#define LPSPI_CCR_PCSSCK_SHIFT (16U) +/*! PCSSCK - PCS-to-SCK Delay */ +#define LPSPI_CCR_PCSSCK(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR_PCSSCK_SHIFT)) & LPSPI_CCR_PCSSCK_MASK) + +#define LPSPI_CCR_SCKPCS_MASK (0xFF000000U) +#define LPSPI_CCR_SCKPCS_SHIFT (24U) +/*! SCKPCS - SCK-to-PCS Delay */ +#define LPSPI_CCR_SCKPCS(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR_SCKPCS_SHIFT)) & LPSPI_CCR_SCKPCS_MASK) +/*! @} */ + +/*! @name CCR1 - Clock Configuration 1 */ +/*! @{ */ + +#define LPSPI_CCR1_SCKSET_MASK (0xFFU) +#define LPSPI_CCR1_SCKSET_SHIFT (0U) +/*! SCKSET - SCK Setup */ +#define LPSPI_CCR1_SCKSET(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR1_SCKSET_SHIFT)) & LPSPI_CCR1_SCKSET_MASK) + +#define LPSPI_CCR1_SCKHLD_MASK (0xFF00U) +#define LPSPI_CCR1_SCKHLD_SHIFT (8U) +/*! SCKHLD - SCK Hold */ +#define LPSPI_CCR1_SCKHLD(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR1_SCKHLD_SHIFT)) & LPSPI_CCR1_SCKHLD_MASK) + +#define LPSPI_CCR1_PCSPCS_MASK (0xFF0000U) +#define LPSPI_CCR1_PCSPCS_SHIFT (16U) +/*! PCSPCS - PCS to PCS Delay */ +#define LPSPI_CCR1_PCSPCS(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR1_PCSPCS_SHIFT)) & LPSPI_CCR1_PCSPCS_MASK) + +#define LPSPI_CCR1_SCKSCK_MASK (0xFF000000U) +#define LPSPI_CCR1_SCKSCK_SHIFT (24U) +/*! SCKSCK - SCK Inter-Frame Delay */ +#define LPSPI_CCR1_SCKSCK(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR1_SCKSCK_SHIFT)) & LPSPI_CCR1_SCKSCK_MASK) +/*! @} */ + +/*! @name FCR - FIFO Control */ +/*! @{ */ + +#define LPSPI_FCR_TXWATER_MASK (0x7U) +#define LPSPI_FCR_TXWATER_SHIFT (0U) +/*! TXWATER - Transmit FIFO Watermark */ +#define LPSPI_FCR_TXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_FCR_TXWATER_SHIFT)) & LPSPI_FCR_TXWATER_MASK) + +#define LPSPI_FCR_RXWATER_MASK (0x70000U) +#define LPSPI_FCR_RXWATER_SHIFT (16U) +/*! RXWATER - Receive FIFO Watermark */ +#define LPSPI_FCR_RXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_FCR_RXWATER_SHIFT)) & LPSPI_FCR_RXWATER_MASK) +/*! @} */ + +/*! @name FSR - FIFO Status */ +/*! @{ */ + +#define LPSPI_FSR_TXCOUNT_MASK (0xFU) +#define LPSPI_FSR_TXCOUNT_SHIFT (0U) +/*! TXCOUNT - Transmit FIFO Count */ +#define LPSPI_FSR_TXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_FSR_TXCOUNT_SHIFT)) & LPSPI_FSR_TXCOUNT_MASK) + +#define LPSPI_FSR_RXCOUNT_MASK (0xF0000U) +#define LPSPI_FSR_RXCOUNT_SHIFT (16U) +/*! RXCOUNT - Receive FIFO Count */ +#define LPSPI_FSR_RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_FSR_RXCOUNT_SHIFT)) & LPSPI_FSR_RXCOUNT_MASK) +/*! @} */ + +/*! @name TCR - Transmit Command */ +/*! @{ */ + +#define LPSPI_TCR_FRAMESZ_MASK (0xFFFU) +#define LPSPI_TCR_FRAMESZ_SHIFT (0U) +/*! FRAMESZ - Frame Size */ +#define LPSPI_TCR_FRAMESZ(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_FRAMESZ_SHIFT)) & LPSPI_TCR_FRAMESZ_MASK) + +#define LPSPI_TCR_TXMSK_MASK (0x40000U) +#define LPSPI_TCR_TXMSK_SHIFT (18U) +/*! TXMSK - Transmit Data Mask + * 0b0..Normal transfer + * 0b1..Mask transmit data + */ +#define LPSPI_TCR_TXMSK(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_TXMSK_SHIFT)) & LPSPI_TCR_TXMSK_MASK) + +#define LPSPI_TCR_RXMSK_MASK (0x80000U) +#define LPSPI_TCR_RXMSK_SHIFT (19U) +/*! RXMSK - Receive Data Mask + * 0b0..Normal transfer + * 0b1..Mask receive data + */ +#define LPSPI_TCR_RXMSK(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_RXMSK_SHIFT)) & LPSPI_TCR_RXMSK_MASK) + +#define LPSPI_TCR_CONTC_MASK (0x100000U) +#define LPSPI_TCR_CONTC_SHIFT (20U) +/*! CONTC - Continuing Command + * 0b0..Command word for start of new transfer + * 0b1..Command word for continuing transfer + */ +#define LPSPI_TCR_CONTC(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_CONTC_SHIFT)) & LPSPI_TCR_CONTC_MASK) + +#define LPSPI_TCR_CONT_MASK (0x200000U) +#define LPSPI_TCR_CONT_SHIFT (21U) +/*! CONT - Continuous Transfer + * 0b0..Disable + * 0b1..Enable + */ +#define LPSPI_TCR_CONT(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_CONT_SHIFT)) & LPSPI_TCR_CONT_MASK) + +#define LPSPI_TCR_BYSW_MASK (0x400000U) +#define LPSPI_TCR_BYSW_SHIFT (22U) +/*! BYSW - Byte Swap + * 0b0..Disable byte swap + * 0b1..Enable byte swap + */ +#define LPSPI_TCR_BYSW(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_BYSW_SHIFT)) & LPSPI_TCR_BYSW_MASK) + +#define LPSPI_TCR_LSBF_MASK (0x800000U) +#define LPSPI_TCR_LSBF_SHIFT (23U) +/*! LSBF - LSB First + * 0b0..MSB first + * 0b1..LSB first + */ +#define LPSPI_TCR_LSBF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_LSBF_SHIFT)) & LPSPI_TCR_LSBF_MASK) + +#define LPSPI_TCR_PCS_MASK (0x3000000U) /* Merged from fields with different position or width, of widths (1, 2), largest definition used */ +#define LPSPI_TCR_PCS_SHIFT (24U) +/*! PCS - Peripheral Chip Select + * 0b00..Transfer using PCS[0] + * 0b01..Transfer using PCS[1] + * 0b10..Transfer using PCS[2] + */ +#define LPSPI_TCR_PCS(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_PCS_SHIFT)) & LPSPI_TCR_PCS_MASK) /* Merged from fields with different position or width, of widths (1, 2), largest definition used */ + +#define LPSPI_TCR_PRESCALE_MASK (0x38000000U) +#define LPSPI_TCR_PRESCALE_SHIFT (27U) +/*! PRESCALE - Prescaler Value + * 0b000..Divide by 1 + * 0b001..Divide by 2 + * 0b010..Divide by 4 + * 0b011..Divide by 8 + * 0b100..Divide by 16 + * 0b101..Divide by 32 + * 0b110..Divide by 64 + * 0b111..Divide by 128 + */ +#define LPSPI_TCR_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_PRESCALE_SHIFT)) & LPSPI_TCR_PRESCALE_MASK) + +#define LPSPI_TCR_CPHA_MASK (0x40000000U) +#define LPSPI_TCR_CPHA_SHIFT (30U) +/*! CPHA - Clock Phase + * 0b0..Captured + * 0b1..Changed + */ +#define LPSPI_TCR_CPHA(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_CPHA_SHIFT)) & LPSPI_TCR_CPHA_MASK) + +#define LPSPI_TCR_CPOL_MASK (0x80000000U) +#define LPSPI_TCR_CPOL_SHIFT (31U) +/*! CPOL - Clock Polarity + * 0b0..Inactive low + * 0b1..Inactive high + */ +#define LPSPI_TCR_CPOL(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_CPOL_SHIFT)) & LPSPI_TCR_CPOL_MASK) +/*! @} */ + +/*! @name TDR - Transmit Data */ +/*! @{ */ + +#define LPSPI_TDR_DATA_MASK (0xFFFFFFFFU) +#define LPSPI_TDR_DATA_SHIFT (0U) +/*! DATA - Transmit Data */ +#define LPSPI_TDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TDR_DATA_SHIFT)) & LPSPI_TDR_DATA_MASK) +/*! @} */ + +/*! @name RSR - Receive Status */ +/*! @{ */ + +#define LPSPI_RSR_SOF_MASK (0x1U) +#define LPSPI_RSR_SOF_SHIFT (0U) +/*! SOF - Start of Frame + * 0b0..Subsequent data word or RX FIFO is empty (RXEMPTY=1). + * 0b1..First data word + */ +#define LPSPI_RSR_SOF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_RSR_SOF_SHIFT)) & LPSPI_RSR_SOF_MASK) + +#define LPSPI_RSR_RXEMPTY_MASK (0x2U) +#define LPSPI_RSR_RXEMPTY_SHIFT (1U) +/*! RXEMPTY - RX FIFO Empty + * 0b0..Not empty + * 0b1..Empty + */ +#define LPSPI_RSR_RXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_RSR_RXEMPTY_SHIFT)) & LPSPI_RSR_RXEMPTY_MASK) +/*! @} */ + +/*! @name RDR - Receive Data */ +/*! @{ */ + +#define LPSPI_RDR_DATA_MASK (0xFFFFFFFFU) +#define LPSPI_RDR_DATA_SHIFT (0U) +/*! DATA - Receive Data */ +#define LPSPI_RDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_RDR_DATA_SHIFT)) & LPSPI_RDR_DATA_MASK) +/*! @} */ + +/*! @name RDROR - Receive Data Read Only */ +/*! @{ */ + +#define LPSPI_RDROR_DATA_MASK (0xFFFFFFFFU) +#define LPSPI_RDROR_DATA_SHIFT (0U) +/*! DATA - Receive Data */ +#define LPSPI_RDROR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_RDROR_DATA_SHIFT)) & LPSPI_RDROR_DATA_MASK) +/*! @} */ + +/*! @name TCBR - Transmit Command Burst */ +/*! @{ */ + +#define LPSPI_TCBR_DATA_MASK (0xFFFFFFFFU) +#define LPSPI_TCBR_DATA_SHIFT (0U) +/*! DATA - Command Data */ +#define LPSPI_TCBR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCBR_DATA_SHIFT)) & LPSPI_TCBR_DATA_MASK) +/*! @} */ + +/*! @name TDBR - Transmit Data Burst */ +/*! @{ */ + +#define LPSPI_TDBR_DATA_MASK (0xFFFFFFFFU) +#define LPSPI_TDBR_DATA_SHIFT (0U) +/*! DATA - Data */ +#define LPSPI_TDBR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TDBR_DATA_SHIFT)) & LPSPI_TDBR_DATA_MASK) +/*! @} */ + +/* The count of LPSPI_TDBR */ +#define LPSPI_TDBR_COUNT (128U) + +/*! @name RDBR - Receive Data Burst */ +/*! @{ */ + +#define LPSPI_RDBR_DATA_MASK (0xFFFFFFFFU) +#define LPSPI_RDBR_DATA_SHIFT (0U) +/*! DATA - Data */ +#define LPSPI_RDBR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_RDBR_DATA_SHIFT)) & LPSPI_RDBR_DATA_MASK) +/*! @} */ + +/* The count of LPSPI_RDBR */ +#define LPSPI_RDBR_COUNT (128U) + + +/*! + * @} + */ /* end of group LPSPI_Register_Masks */ + + +/* LPSPI - Peripheral instance base addresses */ +/** Peripheral LPSPI1 base address */ +#define LPSPI1_BASE (0x44360000u) +/** Peripheral LPSPI1 base pointer */ +#define LPSPI1 ((LPSPI_Type *)LPSPI1_BASE) +/** Peripheral LPSPI2 base address */ +#define LPSPI2_BASE (0x44370000u) +/** Peripheral LPSPI2 base pointer */ +#define LPSPI2 ((LPSPI_Type *)LPSPI2_BASE) +/** Peripheral LPSPI3 base address */ +#define LPSPI3_BASE (0x42550000u) +/** Peripheral LPSPI3 base pointer */ +#define LPSPI3 ((LPSPI_Type *)LPSPI3_BASE) +/** Peripheral LPSPI4 base address */ +#define LPSPI4_BASE (0x42560000u) +/** Peripheral LPSPI4 base pointer */ +#define LPSPI4 ((LPSPI_Type *)LPSPI4_BASE) +/** Peripheral LPSPI5 base address */ +#define LPSPI5_BASE (0x426F0000u) +/** Peripheral LPSPI5 base pointer */ +#define LPSPI5 ((LPSPI_Type *)LPSPI5_BASE) +/** Peripheral LPSPI6 base address */ +#define LPSPI6_BASE (0x42700000u) +/** Peripheral LPSPI6 base pointer */ +#define LPSPI6 ((LPSPI_Type *)LPSPI6_BASE) +/** Peripheral LPSPI7 base address */ +#define LPSPI7_BASE (0x42710000u) +/** Peripheral LPSPI7 base pointer */ +#define LPSPI7 ((LPSPI_Type *)LPSPI7_BASE) +/** Peripheral LPSPI8 base address */ +#define LPSPI8_BASE (0x42720000u) +/** Peripheral LPSPI8 base pointer */ +#define LPSPI8 ((LPSPI_Type *)LPSPI8_BASE) +/** Array initializer of LPSPI peripheral base addresses */ +#define LPSPI_BASE_ADDRS { 0u, LPSPI1_BASE, LPSPI2_BASE, LPSPI3_BASE, LPSPI4_BASE, LPSPI5_BASE, LPSPI6_BASE, LPSPI7_BASE, LPSPI8_BASE } +/** Array initializer of LPSPI peripheral base pointers */ +#define LPSPI_BASE_PTRS { (LPSPI_Type *)0u, LPSPI1, LPSPI2, LPSPI3, LPSPI4, LPSPI5, LPSPI6, LPSPI7, LPSPI8 } +/** Interrupt vectors for the LPSPI peripheral type */ +#define LPSPI_IRQS { NotAvail_IRQn, LPSPI1_IRQn, LPSPI2_IRQn, LPSPI3_IRQn, LPSPI4_IRQn, LPSPI5_IRQn, LPSPI6_IRQn, LPSPI7_IRQn, LPSPI8_IRQn } + +/*! + * @} + */ /* end of group LPSPI_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- LPTMR Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup LPTMR_Peripheral_Access_Layer LPTMR Peripheral Access Layer + * @{ + */ + +/** LPTMR - Register Layout Typedef */ +typedef struct { + __IO uint32_t CSR; /**< Control Status, offset: 0x0 */ + __IO uint32_t PSR; /**< Prescaler and Glitch Filter, offset: 0x4 */ + __IO uint32_t CMR; /**< Compare, offset: 0x8 */ + __IO uint32_t CNR; /**< Counter, offset: 0xC */ +} LPTMR_Type; + +/* ---------------------------------------------------------------------------- + -- LPTMR Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup LPTMR_Register_Masks LPTMR Register Masks + * @{ + */ + +/*! @name CSR - Control Status */ +/*! @{ */ + +#define LPTMR_CSR_TEN_MASK (0x1U) +#define LPTMR_CSR_TEN_SHIFT (0U) +/*! TEN - Timer Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPTMR_CSR_TEN(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TEN_SHIFT)) & LPTMR_CSR_TEN_MASK) + +#define LPTMR_CSR_TMS_MASK (0x2U) +#define LPTMR_CSR_TMS_SHIFT (1U) +/*! TMS - Timer Mode Select + * 0b0..Time Counter + * 0b1..Pulse Counter + */ +#define LPTMR_CSR_TMS(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TMS_SHIFT)) & LPTMR_CSR_TMS_MASK) + +#define LPTMR_CSR_TFC_MASK (0x4U) +#define LPTMR_CSR_TFC_SHIFT (2U) +/*! TFC - Timer Free-Running Counter + * 0b0..Reset when TCF asserts + * 0b1..Reset on overflow + */ +#define LPTMR_CSR_TFC(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TFC_SHIFT)) & LPTMR_CSR_TFC_MASK) + +#define LPTMR_CSR_TPP_MASK (0x8U) +#define LPTMR_CSR_TPP_SHIFT (3U) +/*! TPP - Timer Pin Polarity + * 0b0..Active-high + * 0b1..Active-low + */ +#define LPTMR_CSR_TPP(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TPP_SHIFT)) & LPTMR_CSR_TPP_MASK) + +#define LPTMR_CSR_TPS_MASK (0x30U) +#define LPTMR_CSR_TPS_SHIFT (4U) +/*! TPS - Timer Pin Select + * 0b00..Input 0 + * 0b01..Input 1 + * 0b10..Input 2 + * 0b11..Input 3 + */ +#define LPTMR_CSR_TPS(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TPS_SHIFT)) & LPTMR_CSR_TPS_MASK) + +#define LPTMR_CSR_TIE_MASK (0x40U) +#define LPTMR_CSR_TIE_SHIFT (6U) +/*! TIE - Timer Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPTMR_CSR_TIE(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TIE_SHIFT)) & LPTMR_CSR_TIE_MASK) + +#define LPTMR_CSR_TCF_MASK (0x80U) +#define LPTMR_CSR_TCF_SHIFT (7U) +/*! TCF - Timer Compare Flag + * 0b0..CNR != (CMR + 1) + * 0b0..No effect + * 0b1..CNR = (CMR + 1) + * 0b1..Clear the flag + */ +#define LPTMR_CSR_TCF(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TCF_SHIFT)) & LPTMR_CSR_TCF_MASK) + +#define LPTMR_CSR_TDRE_MASK (0x100U) +#define LPTMR_CSR_TDRE_SHIFT (8U) +/*! TDRE - Timer DMA Request Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPTMR_CSR_TDRE(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TDRE_SHIFT)) & LPTMR_CSR_TDRE_MASK) +/*! @} */ + +/*! @name PSR - Prescaler and Glitch Filter */ +/*! @{ */ + +#define LPTMR_PSR_PCS_MASK (0x3U) +#define LPTMR_PSR_PCS_SHIFT (0U) +/*! PCS - Prescaler and Glitch Filter Clock Select + * 0b00..Clock 0 + * 0b01..Clock 1 + * 0b10..Clock 2 + * 0b11..Clock 3 + */ +#define LPTMR_PSR_PCS(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PCS_SHIFT)) & LPTMR_PSR_PCS_MASK) + +#define LPTMR_PSR_PBYP_MASK (0x4U) +#define LPTMR_PSR_PBYP_SHIFT (2U) +/*! PBYP - Prescaler and Glitch Filter Bypass + * 0b0..Prescaler and glitch filter enable + * 0b1..Prescaler and glitch filter bypass + */ +#define LPTMR_PSR_PBYP(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PBYP_SHIFT)) & LPTMR_PSR_PBYP_MASK) + +#define LPTMR_PSR_PRESCALE_MASK (0x78U) +#define LPTMR_PSR_PRESCALE_SHIFT (3U) +/*! PRESCALE - Prescaler and Glitch Filter Value + * 0b0000..Prescaler divides the prescaler clock by 2; glitch filter does not support this configuration + * 0b0001..Prescaler divides the prescaler clock by 4; glitch filter recognizes change on input pin after two rising clock edges + * 0b0010..Prescaler divides the prescaler clock by 8; glitch filter recognizes change on input pin after four rising clock edges + * 0b0011..Prescaler divides the prescaler clock by 16; glitch filter recognizes change on input pin after eight rising clock edges + * 0b0100..Prescaler divides the prescaler clock by 32; glitch filter recognizes change on input pin after 16 rising clock edges + * 0b0101..Prescaler divides the prescaler clock by 64; glitch filter recognizes change on input pin after 32 rising clock edges + * 0b0110..Prescaler divides the prescaler clock by 128; glitch filter recognizes change on input pin after 64 rising clock edges + * 0b0111..Prescaler divides the prescaler clock by 256; glitch filter recognizes change on input pin after 128 rising clock edges + * 0b1000..Prescaler divides the prescaler clock by 512; glitch filter recognizes change on input pin after 256 rising clock edges + * 0b1001..Prescaler divides the prescaler clock by 1024; glitch filter recognizes change on input pin after 512 rising clock edges + * 0b1010..Prescaler divides the prescaler clock by 2048; glitch filter recognizes change on input pin after 1024 rising clock edges + * 0b1011..Prescaler divides the prescaler clock by 4096; glitch filter recognizes change on input pin after 2048 rising clock edges + * 0b1100..Prescaler divides the prescaler clock by 8192; glitch filter recognizes change on input pin after 4096 rising clock edges + * 0b1101..Prescaler divides the prescaler clock by 16,384; glitch filter recognizes change on input pin after 8192 rising clock edges + * 0b1110..Prescaler divides the prescaler clock by 32,768; glitch filter recognizes change on input pin after 16,384 rising clock edges + * 0b1111..Prescaler divides the prescaler clock by 65,536; glitch filter recognizes change on input pin after 32,768 rising clock edges + */ +#define LPTMR_PSR_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PRESCALE_SHIFT)) & LPTMR_PSR_PRESCALE_MASK) +/*! @} */ + +/*! @name CMR - Compare */ +/*! @{ */ + +#define LPTMR_CMR_COMPARE_MASK (0xFFFFFFFFU) +#define LPTMR_CMR_COMPARE_SHIFT (0U) +/*! COMPARE - Compare Value */ +#define LPTMR_CMR_COMPARE(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CMR_COMPARE_SHIFT)) & LPTMR_CMR_COMPARE_MASK) +/*! @} */ + +/*! @name CNR - Counter */ +/*! @{ */ + +#define LPTMR_CNR_COUNTER_MASK (0xFFFFFFFFU) +#define LPTMR_CNR_COUNTER_SHIFT (0U) +/*! COUNTER - Counter Value */ +#define LPTMR_CNR_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CNR_COUNTER_SHIFT)) & LPTMR_CNR_COUNTER_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group LPTMR_Register_Masks */ + + +/* LPTMR - Peripheral instance base addresses */ +/** Peripheral LPTMR1 base address */ +#define LPTMR1_BASE (0x44300000u) +/** Peripheral LPTMR1 base pointer */ +#define LPTMR1 ((LPTMR_Type *)LPTMR1_BASE) +/** Peripheral LPTMR2 base address */ +#define LPTMR2_BASE (0x424D0000u) +/** Peripheral LPTMR2 base pointer */ +#define LPTMR2 ((LPTMR_Type *)LPTMR2_BASE) +/** Array initializer of LPTMR peripheral base addresses */ +#define LPTMR_BASE_ADDRS { 0u, LPTMR1_BASE, LPTMR2_BASE } +/** Array initializer of LPTMR peripheral base pointers */ +#define LPTMR_BASE_PTRS { (LPTMR_Type *)0u, LPTMR1, LPTMR2 } +/** Interrupt vectors for the LPTMR peripheral type */ +#define LPTMR_IRQS { NotAvail_IRQn, LPTMR1_IRQn, LPTMR2_IRQn } + +/*! + * @} + */ /* end of group LPTMR_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- LPUART Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup LPUART_Peripheral_Access_Layer LPUART Peripheral Access Layer + * @{ + */ + +/** LPUART - Register Layout Typedef */ +typedef struct { + __I uint32_t VERID; /**< Version ID, offset: 0x0 */ + __I uint32_t PARAM; /**< Parameter, offset: 0x4 */ + __IO uint32_t GLOBAL; /**< Global, offset: 0x8 */ + __IO uint32_t PINCFG; /**< Pin Configuration, offset: 0xC */ + __IO uint32_t BAUD; /**< Baud Rate, offset: 0x10 */ + __IO uint32_t STAT; /**< Status, offset: 0x14 */ + __IO uint32_t CTRL; /**< Control, offset: 0x18 */ + __IO uint32_t DATA; /**< Data, offset: 0x1C */ + __IO uint32_t MATCH; /**< Match Address, offset: 0x20 */ + __IO uint32_t MODIR; /**< MODEM IrDA, offset: 0x24 */ + __IO uint32_t FIFO; /**< FIFO, offset: 0x28 */ + __IO uint32_t WATER; /**< Watermark, offset: 0x2C */ + __I uint32_t DATARO; /**< Data Read-Only, offset: 0x30 */ + uint8_t RESERVED_0[12]; + __IO uint32_t MCR; /**< MODEM Control, offset: 0x40 */ + __IO uint32_t MSR; /**< MODEM Status, offset: 0x44 */ + __IO uint32_t REIR; /**< Receiver Extended Idle, offset: 0x48 */ + __IO uint32_t TEIR; /**< Transmitter Extended Idle, offset: 0x4C */ + __IO uint32_t HDCR; /**< Half Duplex Control, offset: 0x50 */ + uint8_t RESERVED_1[4]; + __IO uint32_t TOCR; /**< Timeout Control, offset: 0x58 */ + __IO uint32_t TOSR; /**< Timeout Status, offset: 0x5C */ + __IO uint32_t TIMEOUT[4]; /**< Timeout N, array offset: 0x60, array step: 0x4 */ + uint8_t RESERVED_2[400]; + __O uint32_t TCBR[128]; /**< Transmit Command Burst, array offset: 0x200, array step: 0x4 */ + __O uint32_t TDBR[256]; /**< Transmit Data Burst, array offset: 0x400, array step: 0x4 */ +} LPUART_Type; + +/* ---------------------------------------------------------------------------- + -- LPUART Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup LPUART_Register_Masks LPUART Register Masks + * @{ + */ + +/*! @name VERID - Version ID */ +/*! @{ */ + +#define LPUART_VERID_FEATURE_MASK (0xFFFFU) +#define LPUART_VERID_FEATURE_SHIFT (0U) +/*! FEATURE - Feature Identification Number + * 0b0000000000000001..Standard feature set + * 0b0000000000000011..Standard feature set with MODEM and IrDA support + * 0b0000000000000111..Enhanced feature set with full MODEM, IrDA, and enhanced idle detection + */ +#define LPUART_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_VERID_FEATURE_SHIFT)) & LPUART_VERID_FEATURE_MASK) + +#define LPUART_VERID_MINOR_MASK (0xFF0000U) +#define LPUART_VERID_MINOR_SHIFT (16U) +/*! MINOR - Minor Version Number */ +#define LPUART_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_VERID_MINOR_SHIFT)) & LPUART_VERID_MINOR_MASK) + +#define LPUART_VERID_MAJOR_MASK (0xFF000000U) +#define LPUART_VERID_MAJOR_SHIFT (24U) +/*! MAJOR - Major Version Number */ +#define LPUART_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_VERID_MAJOR_SHIFT)) & LPUART_VERID_MAJOR_MASK) +/*! @} */ + +/*! @name PARAM - Parameter */ +/*! @{ */ + +#define LPUART_PARAM_TXFIFO_MASK (0xFFU) +#define LPUART_PARAM_TXFIFO_SHIFT (0U) +/*! TXFIFO - Transmit FIFO Size */ +#define LPUART_PARAM_TXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPUART_PARAM_TXFIFO_SHIFT)) & LPUART_PARAM_TXFIFO_MASK) + +#define LPUART_PARAM_RXFIFO_MASK (0xFF00U) +#define LPUART_PARAM_RXFIFO_SHIFT (8U) +/*! RXFIFO - Receive FIFO Size */ +#define LPUART_PARAM_RXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPUART_PARAM_RXFIFO_SHIFT)) & LPUART_PARAM_RXFIFO_MASK) +/*! @} */ + +/*! @name GLOBAL - Global */ +/*! @{ */ + +#define LPUART_GLOBAL_RST_MASK (0x2U) +#define LPUART_GLOBAL_RST_SHIFT (1U) +/*! RST - Software Reset + * 0b0..Not reset + * 0b1..Reset + */ +#define LPUART_GLOBAL_RST(x) (((uint32_t)(((uint32_t)(x)) << LPUART_GLOBAL_RST_SHIFT)) & LPUART_GLOBAL_RST_MASK) +/*! @} */ + +/*! @name PINCFG - Pin Configuration */ +/*! @{ */ + +#define LPUART_PINCFG_TRGSEL_MASK (0x3U) +#define LPUART_PINCFG_TRGSEL_SHIFT (0U) +/*! TRGSEL - Trigger Select + * 0b00..Input trigger disabled + * 0b01..Input trigger used instead of the RXD pin input + * 0b10..Input trigger used instead of the CTS_B pin input + * 0b11..Input trigger used to modulate the TXD pin output, which (after TXINV configuration) is internally ANDed with the input trigger + */ +#define LPUART_PINCFG_TRGSEL(x) (((uint32_t)(((uint32_t)(x)) << LPUART_PINCFG_TRGSEL_SHIFT)) & LPUART_PINCFG_TRGSEL_MASK) +/*! @} */ + +/*! @name BAUD - Baud Rate */ +/*! @{ */ + +#define LPUART_BAUD_SBR_MASK (0x1FFFU) +#define LPUART_BAUD_SBR_SHIFT (0U) +/*! SBR - Baud Rate Modulo Divisor */ +#define LPUART_BAUD_SBR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_SBR_SHIFT)) & LPUART_BAUD_SBR_MASK) + +#define LPUART_BAUD_SBNS_MASK (0x2000U) +#define LPUART_BAUD_SBNS_SHIFT (13U) +/*! SBNS - Stop Bit Number Select + * 0b0..One stop bit + * 0b1..Two stop bits + */ +#define LPUART_BAUD_SBNS(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_SBNS_SHIFT)) & LPUART_BAUD_SBNS_MASK) + +#define LPUART_BAUD_RXEDGIE_MASK (0x4000U) +#define LPUART_BAUD_RXEDGIE_SHIFT (14U) +/*! RXEDGIE - RX Input Active Edge Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPUART_BAUD_RXEDGIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RXEDGIE_SHIFT)) & LPUART_BAUD_RXEDGIE_MASK) + +#define LPUART_BAUD_LBKDIE_MASK (0x8000U) +#define LPUART_BAUD_LBKDIE_SHIFT (15U) +/*! LBKDIE - LIN Break Detect Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPUART_BAUD_LBKDIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_LBKDIE_SHIFT)) & LPUART_BAUD_LBKDIE_MASK) + +#define LPUART_BAUD_RESYNCDIS_MASK (0x10000U) +#define LPUART_BAUD_RESYNCDIS_SHIFT (16U) +/*! RESYNCDIS - Resynchronization Disable + * 0b0..Enable + * 0b1..Disable + */ +#define LPUART_BAUD_RESYNCDIS(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RESYNCDIS_SHIFT)) & LPUART_BAUD_RESYNCDIS_MASK) + +#define LPUART_BAUD_BOTHEDGE_MASK (0x20000U) +#define LPUART_BAUD_BOTHEDGE_SHIFT (17U) +/*! BOTHEDGE - Both Edge Sampling + * 0b0..Rising edge + * 0b1..Both rising and falling edges + */ +#define LPUART_BAUD_BOTHEDGE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_BOTHEDGE_SHIFT)) & LPUART_BAUD_BOTHEDGE_MASK) + +#define LPUART_BAUD_MATCFG_MASK (0xC0000U) +#define LPUART_BAUD_MATCFG_SHIFT (18U) +/*! MATCFG - Match Configuration + * 0b00..Address match wake-up + * 0b01..Idle match wake-up + * 0b10..Match on and match off + * 0b11..Enables RWU on data match and match on or off for the transmitter CTS input + */ +#define LPUART_BAUD_MATCFG(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MATCFG_SHIFT)) & LPUART_BAUD_MATCFG_MASK) + +#define LPUART_BAUD_RIDMAE_MASK (0x100000U) +#define LPUART_BAUD_RIDMAE_SHIFT (20U) +/*! RIDMAE - Receiver Idle DMA Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPUART_BAUD_RIDMAE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RIDMAE_SHIFT)) & LPUART_BAUD_RIDMAE_MASK) + +#define LPUART_BAUD_RDMAE_MASK (0x200000U) +#define LPUART_BAUD_RDMAE_SHIFT (21U) +/*! RDMAE - Receiver Full DMA Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPUART_BAUD_RDMAE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RDMAE_SHIFT)) & LPUART_BAUD_RDMAE_MASK) + +#define LPUART_BAUD_TDMAE_MASK (0x800000U) +#define LPUART_BAUD_TDMAE_SHIFT (23U) +/*! TDMAE - Transmitter DMA Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPUART_BAUD_TDMAE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_TDMAE_SHIFT)) & LPUART_BAUD_TDMAE_MASK) + +#define LPUART_BAUD_OSR_MASK (0x1F000000U) +#define LPUART_BAUD_OSR_SHIFT (24U) +/*! OSR - Oversampling Ratio + * 0b00000..Results in an OSR of 16 + * 0b00001..Reserved + * 0b00010..Reserved + * 0b00011..Results in an OSR of 4 (requires BAUD[BOTHEDGE] to be 1) + * 0b00100..Results in an OSR of 5 (requires BAUD[BOTHEDGE] to be 1) + * 0b00101..Results in an OSR of 6 (requires BAUD[BOTHEDGE] to be 1) + * 0b00110..Results in an OSR of 7 (requires BAUD[BOTHEDGE] to be 1) + * 0b00111..Results in an OSR of 8 + * 0b01000..Results in an OSR of 9 + * 0b01001..Results in an OSR of 10 + * 0b01010..Results in an OSR of 11 + * 0b01011..Results in an OSR of 12 + * 0b01100..Results in an OSR of 13 + * 0b01101..Results in an OSR of 14 + * 0b01110..Results in an OSR of 15 + * 0b01111..Results in an OSR of 16 + * 0b10000..Results in an OSR of 17 + * 0b10001..Results in an OSR of 18 + * 0b10010..Results in an OSR of 19 + * 0b10011..Results in an OSR of 20 + * 0b10100..Results in an OSR of 21 + * 0b10101..Results in an OSR of 22 + * 0b10110..Results in an OSR of 23 + * 0b10111..Results in an OSR of 24 + * 0b11000..Results in an OSR of 25 + * 0b11001..Results in an OSR of 26 + * 0b11010..Results in an OSR of 27 + * 0b11011..Results in an OSR of 28 + * 0b11100..Results in an OSR of 29 + * 0b11101..Results in an OSR of 30 + * 0b11110..Results in an OSR of 31 + * 0b11111..Results in an OSR of 32 + */ +#define LPUART_BAUD_OSR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_OSR_SHIFT)) & LPUART_BAUD_OSR_MASK) + +#define LPUART_BAUD_M10_MASK (0x20000000U) +#define LPUART_BAUD_M10_SHIFT (29U) +/*! M10 - 10-Bit Mode Select + * 0b0..Receiver and transmitter use 7-bit to 9-bit data characters + * 0b1..Receiver and transmitter use 10-bit data characters + */ +#define LPUART_BAUD_M10(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_M10_SHIFT)) & LPUART_BAUD_M10_MASK) + +#define LPUART_BAUD_MAEN2_MASK (0x40000000U) +#define LPUART_BAUD_MAEN2_SHIFT (30U) +/*! MAEN2 - Match Address Mode Enable 2 + * 0b0..Disable + * 0b1..Enable + */ +#define LPUART_BAUD_MAEN2(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MAEN2_SHIFT)) & LPUART_BAUD_MAEN2_MASK) + +#define LPUART_BAUD_MAEN1_MASK (0x80000000U) +#define LPUART_BAUD_MAEN1_SHIFT (31U) +/*! MAEN1 - Match Address Mode Enable 1 + * 0b0..Disable + * 0b1..Enable + */ +#define LPUART_BAUD_MAEN1(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MAEN1_SHIFT)) & LPUART_BAUD_MAEN1_MASK) +/*! @} */ + +/*! @name STAT - Status */ +/*! @{ */ + +#define LPUART_STAT_LBKFE_MASK (0x1U) +#define LPUART_STAT_LBKFE_SHIFT (0U) +/*! LBKFE - LIN Break Flag Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPUART_STAT_LBKFE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_LBKFE_SHIFT)) & LPUART_STAT_LBKFE_MASK) + +#define LPUART_STAT_AME_MASK (0x2U) +#define LPUART_STAT_AME_SHIFT (1U) +/*! AME - Address Mark Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPUART_STAT_AME(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_AME_SHIFT)) & LPUART_STAT_AME_MASK) + +#define LPUART_STAT_MSF_MASK (0x100U) +#define LPUART_STAT_MSF_SHIFT (8U) +/*! MSF - MODEM Status Flag + * 0b0..Field is 0 + * 0b1..Field is 1 + */ +#define LPUART_STAT_MSF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MSF_SHIFT)) & LPUART_STAT_MSF_MASK) + +#define LPUART_STAT_TSF_MASK (0x200U) +#define LPUART_STAT_TSF_SHIFT (9U) +/*! TSF - Timeout Status Flag + * 0b0..Field is 0 + * 0b1..Field is 1 + */ +#define LPUART_STAT_TSF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_TSF_SHIFT)) & LPUART_STAT_TSF_MASK) + +#define LPUART_STAT_MA2F_MASK (0x4000U) +#define LPUART_STAT_MA2F_SHIFT (14U) +/*! MA2F - Match 2 Flag + * 0b0..Not equal to MA2 + * 0b0..No effect + * 0b1..Equal to MA2 + * 0b1..Clear the flag + */ +#define LPUART_STAT_MA2F(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MA2F_SHIFT)) & LPUART_STAT_MA2F_MASK) + +#define LPUART_STAT_MA1F_MASK (0x8000U) +#define LPUART_STAT_MA1F_SHIFT (15U) +/*! MA1F - Match 1 Flag + * 0b0..Not equal to MA1 + * 0b0..No effect + * 0b1..Equal to MA1 + * 0b1..Clear the flag + */ +#define LPUART_STAT_MA1F(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MA1F_SHIFT)) & LPUART_STAT_MA1F_MASK) + +#define LPUART_STAT_PF_MASK (0x10000U) +#define LPUART_STAT_PF_SHIFT (16U) +/*! PF - Parity Error Flag + * 0b0..No parity error detected + * 0b0..No effect + * 0b1..Parity error detected + * 0b1..Clear the flag + */ +#define LPUART_STAT_PF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_PF_SHIFT)) & LPUART_STAT_PF_MASK) + +#define LPUART_STAT_FE_MASK (0x20000U) +#define LPUART_STAT_FE_SHIFT (17U) +/*! FE - Framing Error Flag + * 0b0..No framing error detected (this does not guarantee that the framing is correct) + * 0b0..No effect + * 0b1..Framing error detected + * 0b1..Clear the flag + */ +#define LPUART_STAT_FE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_FE_SHIFT)) & LPUART_STAT_FE_MASK) + +#define LPUART_STAT_NF_MASK (0x40000U) +#define LPUART_STAT_NF_SHIFT (18U) +/*! NF - Noise Flag + * 0b0..No noise detected + * 0b0..No effect + * 0b1..Noise detected + * 0b1..Clear the flag + */ +#define LPUART_STAT_NF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_NF_SHIFT)) & LPUART_STAT_NF_MASK) + +#define LPUART_STAT_OR_MASK (0x80000U) +#define LPUART_STAT_OR_SHIFT (19U) +/*! OR - Receiver Overrun Flag + * 0b0..No overrun + * 0b0..No effect + * 0b1..Receive overrun (new LPUART data is lost) + * 0b1..Clear the flag + */ +#define LPUART_STAT_OR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_OR_SHIFT)) & LPUART_STAT_OR_MASK) + +#define LPUART_STAT_IDLE_MASK (0x100000U) +#define LPUART_STAT_IDLE_SHIFT (20U) +/*! IDLE - Idle Line Flag + * 0b0..Idle line detected + * 0b0..No effect + * 0b1..Idle line not detected + * 0b1..Clear the flag + */ +#define LPUART_STAT_IDLE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_IDLE_SHIFT)) & LPUART_STAT_IDLE_MASK) + +#define LPUART_STAT_RDRF_MASK (0x200000U) +#define LPUART_STAT_RDRF_SHIFT (21U) +/*! RDRF - Receive Data Register Full Flag + * 0b0..Equal to or less than watermark + * 0b1..Greater than watermark + */ +#define LPUART_STAT_RDRF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RDRF_SHIFT)) & LPUART_STAT_RDRF_MASK) + +#define LPUART_STAT_TC_MASK (0x400000U) +#define LPUART_STAT_TC_SHIFT (22U) +/*! TC - Transmission Complete Flag + * 0b0..Transmitter active + * 0b1..Transmitter idle + */ +#define LPUART_STAT_TC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_TC_SHIFT)) & LPUART_STAT_TC_MASK) + +#define LPUART_STAT_TDRE_MASK (0x800000U) +#define LPUART_STAT_TDRE_SHIFT (23U) +/*! TDRE - Transmit Data Register Empty Flag + * 0b0..Greater than watermark + * 0b1..Equal to or less than watermark + */ +#define LPUART_STAT_TDRE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_TDRE_SHIFT)) & LPUART_STAT_TDRE_MASK) + +#define LPUART_STAT_RAF_MASK (0x1000000U) +#define LPUART_STAT_RAF_SHIFT (24U) +/*! RAF - Receiver Active Flag + * 0b0..Idle, waiting for a start bit + * 0b1..Receiver active (RXD pin input not idle) + */ +#define LPUART_STAT_RAF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RAF_SHIFT)) & LPUART_STAT_RAF_MASK) + +#define LPUART_STAT_LBKDE_MASK (0x2000000U) +#define LPUART_STAT_LBKDE_SHIFT (25U) +/*! LBKDE - LIN Break Detection Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPUART_STAT_LBKDE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_LBKDE_SHIFT)) & LPUART_STAT_LBKDE_MASK) + +#define LPUART_STAT_BRK13_MASK (0x4000000U) +#define LPUART_STAT_BRK13_SHIFT (26U) +/*! BRK13 - Break Character Generation Length + * 0b0..9 to 13 bit times + * 0b1..12 to 15 bit times + */ +#define LPUART_STAT_BRK13(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_BRK13_SHIFT)) & LPUART_STAT_BRK13_MASK) + +#define LPUART_STAT_RWUID_MASK (0x8000000U) +#define LPUART_STAT_RWUID_SHIFT (27U) +/*! RWUID - Receive Wake Up Idle Detect + * 0b0..STAT[IDLE] does not become 1 + * 0b1..STAT[IDLE] becomes 1 + */ +#define LPUART_STAT_RWUID(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RWUID_SHIFT)) & LPUART_STAT_RWUID_MASK) + +#define LPUART_STAT_RXINV_MASK (0x10000000U) +#define LPUART_STAT_RXINV_SHIFT (28U) +/*! RXINV - Receive Data Inversion + * 0b0..Inverted + * 0b1..Not inverted + */ +#define LPUART_STAT_RXINV(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RXINV_SHIFT)) & LPUART_STAT_RXINV_MASK) + +#define LPUART_STAT_MSBF_MASK (0x20000000U) +#define LPUART_STAT_MSBF_SHIFT (29U) +/*! MSBF - MSB First + * 0b0..LSB + * 0b1..MSB + */ +#define LPUART_STAT_MSBF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MSBF_SHIFT)) & LPUART_STAT_MSBF_MASK) + +#define LPUART_STAT_RXEDGIF_MASK (0x40000000U) +#define LPUART_STAT_RXEDGIF_SHIFT (30U) +/*! RXEDGIF - RXD Pin Active Edge Interrupt Flag + * 0b0..Not occurred + * 0b0..No effect + * 0b1..Occurred + * 0b1..Clear the flag + */ +#define LPUART_STAT_RXEDGIF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RXEDGIF_SHIFT)) & LPUART_STAT_RXEDGIF_MASK) + +#define LPUART_STAT_LBKDIF_MASK (0x80000000U) +#define LPUART_STAT_LBKDIF_SHIFT (31U) +/*! LBKDIF - LIN Break Detect Interrupt Flag + * 0b0..Not detected + * 0b0..No effect + * 0b1..Detected + * 0b1..Clear the flag + */ +#define LPUART_STAT_LBKDIF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_LBKDIF_SHIFT)) & LPUART_STAT_LBKDIF_MASK) +/*! @} */ + +/*! @name CTRL - Control */ +/*! @{ */ + +#define LPUART_CTRL_PT_MASK (0x1U) +#define LPUART_CTRL_PT_SHIFT (0U) +/*! PT - Parity Type + * 0b0..Even parity + * 0b1..Odd parity + */ +#define LPUART_CTRL_PT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PT_SHIFT)) & LPUART_CTRL_PT_MASK) + +#define LPUART_CTRL_PE_MASK (0x2U) +#define LPUART_CTRL_PE_SHIFT (1U) +/*! PE - Parity Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPUART_CTRL_PE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PE_SHIFT)) & LPUART_CTRL_PE_MASK) + +#define LPUART_CTRL_ILT_MASK (0x4U) +#define LPUART_CTRL_ILT_SHIFT (2U) +/*! ILT - Idle Line Type Select + * 0b0..After the start bit + * 0b1..After the stop bit + */ +#define LPUART_CTRL_ILT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ILT_SHIFT)) & LPUART_CTRL_ILT_MASK) + +#define LPUART_CTRL_WAKE_MASK (0x8U) +#define LPUART_CTRL_WAKE_SHIFT (3U) +/*! WAKE - Receiver Wake-Up Method Select + * 0b0..Idle + * 0b1..Mark + */ +#define LPUART_CTRL_WAKE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_WAKE_SHIFT)) & LPUART_CTRL_WAKE_MASK) + +#define LPUART_CTRL_M_MASK (0x10U) +#define LPUART_CTRL_M_SHIFT (4U) +/*! M - 9-Bit Or 8-Bit Mode Select + * 0b0..8-bit + * 0b1..9-bit + */ +#define LPUART_CTRL_M(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_M_SHIFT)) & LPUART_CTRL_M_MASK) + +#define LPUART_CTRL_RSRC_MASK (0x20U) +#define LPUART_CTRL_RSRC_SHIFT (5U) +/*! RSRC - Receiver Source Select + * 0b0..Internal Loopback mode + * 0b1..Single-wire mode + */ +#define LPUART_CTRL_RSRC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RSRC_SHIFT)) & LPUART_CTRL_RSRC_MASK) + +#define LPUART_CTRL_DOZEEN_MASK (0x40U) +#define LPUART_CTRL_DOZEEN_SHIFT (6U) +/*! DOZEEN - Doze Mode + * 0b0..Enable + * 0b1..Disable + */ +#define LPUART_CTRL_DOZEEN(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_DOZEEN_SHIFT)) & LPUART_CTRL_DOZEEN_MASK) + +#define LPUART_CTRL_LOOPS_MASK (0x80U) +#define LPUART_CTRL_LOOPS_SHIFT (7U) +/*! LOOPS - Loop Mode Select + * 0b0..Normal operation: RXD and TXD use separate pins + * 0b1..Loop mode or Single-Wire mode + */ +#define LPUART_CTRL_LOOPS(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_LOOPS_SHIFT)) & LPUART_CTRL_LOOPS_MASK) + +#define LPUART_CTRL_IDLECFG_MASK (0x700U) +#define LPUART_CTRL_IDLECFG_SHIFT (8U) +/*! IDLECFG - Idle Configuration + * 0b000..1 + * 0b001..2 + * 0b010..4 + * 0b011..8 + * 0b100..16 + * 0b101..32 + * 0b110..64 + * 0b111..128 + */ +#define LPUART_CTRL_IDLECFG(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_IDLECFG_SHIFT)) & LPUART_CTRL_IDLECFG_MASK) + +#define LPUART_CTRL_M7_MASK (0x800U) +#define LPUART_CTRL_M7_SHIFT (11U) +/*! M7 - 7-Bit Mode Select + * 0b0..8-bit to 10-bit + * 0b1..7-bit + */ +#define LPUART_CTRL_M7(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_M7_SHIFT)) & LPUART_CTRL_M7_MASK) + +#define LPUART_CTRL_MA2IE_MASK (0x4000U) +#define LPUART_CTRL_MA2IE_SHIFT (14U) +/*! MA2IE - Match 2 (MA2F) Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPUART_CTRL_MA2IE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_MA2IE_SHIFT)) & LPUART_CTRL_MA2IE_MASK) + +#define LPUART_CTRL_MA1IE_MASK (0x8000U) +#define LPUART_CTRL_MA1IE_SHIFT (15U) +/*! MA1IE - Match 1 (MA1F) Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPUART_CTRL_MA1IE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_MA1IE_SHIFT)) & LPUART_CTRL_MA1IE_MASK) + +#define LPUART_CTRL_SBK_MASK (0x10000U) +#define LPUART_CTRL_SBK_SHIFT (16U) +/*! SBK - Send Break + * 0b0..Normal transmitter operation + * 0b1..Queue break character(s) to be sent + */ +#define LPUART_CTRL_SBK(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_SBK_SHIFT)) & LPUART_CTRL_SBK_MASK) + +#define LPUART_CTRL_RWU_MASK (0x20000U) +#define LPUART_CTRL_RWU_SHIFT (17U) +/*! RWU - Receiver Wake-Up Control + * 0b0..Normal receiver operation + * 0b1..LPUART receiver in standby, waiting for a wake-up condition + */ +#define LPUART_CTRL_RWU(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RWU_SHIFT)) & LPUART_CTRL_RWU_MASK) + +#define LPUART_CTRL_RE_MASK (0x40000U) +#define LPUART_CTRL_RE_SHIFT (18U) +/*! RE - Receiver Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPUART_CTRL_RE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RE_SHIFT)) & LPUART_CTRL_RE_MASK) + +#define LPUART_CTRL_TE_MASK (0x80000U) +#define LPUART_CTRL_TE_SHIFT (19U) +/*! TE - Transmitter Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPUART_CTRL_TE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TE_SHIFT)) & LPUART_CTRL_TE_MASK) + +#define LPUART_CTRL_ILIE_MASK (0x100000U) +#define LPUART_CTRL_ILIE_SHIFT (20U) +/*! ILIE - Idle Line Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPUART_CTRL_ILIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ILIE_SHIFT)) & LPUART_CTRL_ILIE_MASK) + +#define LPUART_CTRL_RIE_MASK (0x200000U) +#define LPUART_CTRL_RIE_SHIFT (21U) +/*! RIE - Receiver Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPUART_CTRL_RIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RIE_SHIFT)) & LPUART_CTRL_RIE_MASK) + +#define LPUART_CTRL_TCIE_MASK (0x400000U) +#define LPUART_CTRL_TCIE_SHIFT (22U) +/*! TCIE - Transmission Complete Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPUART_CTRL_TCIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TCIE_SHIFT)) & LPUART_CTRL_TCIE_MASK) + +#define LPUART_CTRL_TIE_MASK (0x800000U) +#define LPUART_CTRL_TIE_SHIFT (23U) +/*! TIE - Transmit Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPUART_CTRL_TIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TIE_SHIFT)) & LPUART_CTRL_TIE_MASK) + +#define LPUART_CTRL_PEIE_MASK (0x1000000U) +#define LPUART_CTRL_PEIE_SHIFT (24U) +/*! PEIE - Parity Error Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPUART_CTRL_PEIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PEIE_SHIFT)) & LPUART_CTRL_PEIE_MASK) + +#define LPUART_CTRL_FEIE_MASK (0x2000000U) +#define LPUART_CTRL_FEIE_SHIFT (25U) +/*! FEIE - Framing Error Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPUART_CTRL_FEIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_FEIE_SHIFT)) & LPUART_CTRL_FEIE_MASK) + +#define LPUART_CTRL_NEIE_MASK (0x4000000U) +#define LPUART_CTRL_NEIE_SHIFT (26U) +/*! NEIE - Noise Error Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPUART_CTRL_NEIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_NEIE_SHIFT)) & LPUART_CTRL_NEIE_MASK) + +#define LPUART_CTRL_ORIE_MASK (0x8000000U) +#define LPUART_CTRL_ORIE_SHIFT (27U) +/*! ORIE - Overrun Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPUART_CTRL_ORIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ORIE_SHIFT)) & LPUART_CTRL_ORIE_MASK) + +#define LPUART_CTRL_TXINV_MASK (0x10000000U) +#define LPUART_CTRL_TXINV_SHIFT (28U) +/*! TXINV - Transmit Data Inversion + * 0b0..Not inverted + * 0b1..Inverted + */ +#define LPUART_CTRL_TXINV(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TXINV_SHIFT)) & LPUART_CTRL_TXINV_MASK) + +#define LPUART_CTRL_TXDIR_MASK (0x20000000U) +#define LPUART_CTRL_TXDIR_SHIFT (29U) +/*! TXDIR - TXD Pin Direction in Single-Wire Mode + * 0b0..Input + * 0b1..Output + */ +#define LPUART_CTRL_TXDIR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TXDIR_SHIFT)) & LPUART_CTRL_TXDIR_MASK) + +#define LPUART_CTRL_R9T8_MASK (0x40000000U) +#define LPUART_CTRL_R9T8_SHIFT (30U) +/*! R9T8 - Receive Bit 9 Transmit Bit 8 */ +#define LPUART_CTRL_R9T8(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_R9T8_SHIFT)) & LPUART_CTRL_R9T8_MASK) + +#define LPUART_CTRL_R8T9_MASK (0x80000000U) +#define LPUART_CTRL_R8T9_SHIFT (31U) +/*! R8T9 - Receive Bit 8 Transmit Bit 9 */ +#define LPUART_CTRL_R8T9(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_R8T9_SHIFT)) & LPUART_CTRL_R8T9_MASK) +/*! @} */ + +/*! @name DATA - Data */ +/*! @{ */ + +#define LPUART_DATA_R0T0_MASK (0x1U) +#define LPUART_DATA_R0T0_SHIFT (0U) +/*! R0T0 - Read receive FIFO bit 0 or write transmit FIFO bit 0 */ +#define LPUART_DATA_R0T0(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R0T0_SHIFT)) & LPUART_DATA_R0T0_MASK) + +#define LPUART_DATA_R1T1_MASK (0x2U) +#define LPUART_DATA_R1T1_SHIFT (1U) +/*! R1T1 - Read receive FIFO bit 1 or write transmit FIFO bit 1 */ +#define LPUART_DATA_R1T1(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R1T1_SHIFT)) & LPUART_DATA_R1T1_MASK) + +#define LPUART_DATA_R2T2_MASK (0x4U) +#define LPUART_DATA_R2T2_SHIFT (2U) +/*! R2T2 - Read receive FIFO bit 2 or write transmit FIFO bit 2 */ +#define LPUART_DATA_R2T2(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R2T2_SHIFT)) & LPUART_DATA_R2T2_MASK) + +#define LPUART_DATA_R3T3_MASK (0x8U) +#define LPUART_DATA_R3T3_SHIFT (3U) +/*! R3T3 - Read receive FIFO bit 3 or write transmit FIFO bit 3 */ +#define LPUART_DATA_R3T3(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R3T3_SHIFT)) & LPUART_DATA_R3T3_MASK) + +#define LPUART_DATA_R4T4_MASK (0x10U) +#define LPUART_DATA_R4T4_SHIFT (4U) +/*! R4T4 - Read receive FIFO bit 4 or write transmit FIFO bit 4 */ +#define LPUART_DATA_R4T4(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R4T4_SHIFT)) & LPUART_DATA_R4T4_MASK) + +#define LPUART_DATA_R5T5_MASK (0x20U) +#define LPUART_DATA_R5T5_SHIFT (5U) +/*! R5T5 - Read receive FIFO bit 5 or write transmit FIFO bit 5 */ +#define LPUART_DATA_R5T5(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R5T5_SHIFT)) & LPUART_DATA_R5T5_MASK) + +#define LPUART_DATA_R6T6_MASK (0x40U) +#define LPUART_DATA_R6T6_SHIFT (6U) +/*! R6T6 - Read receive FIFO bit 6 or write transmit FIFO bit 6 */ +#define LPUART_DATA_R6T6(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R6T6_SHIFT)) & LPUART_DATA_R6T6_MASK) + +#define LPUART_DATA_R7T7_MASK (0x80U) +#define LPUART_DATA_R7T7_SHIFT (7U) +/*! R7T7 - Read receive FIFO bit 7 or write transmit FIFO bit 7 */ +#define LPUART_DATA_R7T7(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R7T7_SHIFT)) & LPUART_DATA_R7T7_MASK) + +#define LPUART_DATA_R8T8_MASK (0x100U) +#define LPUART_DATA_R8T8_SHIFT (8U) +/*! R8T8 - Read receive FIFO bit 8 or write transmit FIFO bit 8 */ +#define LPUART_DATA_R8T8(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R8T8_SHIFT)) & LPUART_DATA_R8T8_MASK) + +#define LPUART_DATA_R9T9_MASK (0x200U) +#define LPUART_DATA_R9T9_SHIFT (9U) +/*! R9T9 - Read receive FIFO bit 9 or write transmit FIFO bit 9 */ +#define LPUART_DATA_R9T9(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R9T9_SHIFT)) & LPUART_DATA_R9T9_MASK) + +#define LPUART_DATA_LINBRK_MASK (0x400U) +#define LPUART_DATA_LINBRK_SHIFT (10U) +/*! LINBRK - LIN Break + * 0b0..Not detected + * 0b1..Detected + */ +#define LPUART_DATA_LINBRK(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_LINBRK_SHIFT)) & LPUART_DATA_LINBRK_MASK) + +#define LPUART_DATA_IDLINE_MASK (0x800U) +#define LPUART_DATA_IDLINE_SHIFT (11U) +/*! IDLINE - Idle Line + * 0b0..Not idle + * 0b1..Idle + */ +#define LPUART_DATA_IDLINE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_IDLINE_SHIFT)) & LPUART_DATA_IDLINE_MASK) + +#define LPUART_DATA_RXEMPT_MASK (0x1000U) +#define LPUART_DATA_RXEMPT_SHIFT (12U) +/*! RXEMPT - Receive Buffer Empty + * 0b0..Valid data + * 0b1..Invalid data and empty + */ +#define LPUART_DATA_RXEMPT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_RXEMPT_SHIFT)) & LPUART_DATA_RXEMPT_MASK) + +#define LPUART_DATA_FRETSC_MASK (0x2000U) +#define LPUART_DATA_FRETSC_SHIFT (13U) +/*! FRETSC - Frame Error Transmit Special Character + * 0b0..Received without a frame error on reads or transmits a normal character on writes + * 0b1..Received with a frame error on reads or transmits an idle or break character on writes + */ +#define LPUART_DATA_FRETSC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_FRETSC_SHIFT)) & LPUART_DATA_FRETSC_MASK) + +#define LPUART_DATA_PARITYE_MASK (0x4000U) +#define LPUART_DATA_PARITYE_SHIFT (14U) +/*! PARITYE - Parity Error + * 0b0..Received without a parity error + * 0b1..Received with a parity error + */ +#define LPUART_DATA_PARITYE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_PARITYE_SHIFT)) & LPUART_DATA_PARITYE_MASK) + +#define LPUART_DATA_NOISY_MASK (0x8000U) +#define LPUART_DATA_NOISY_SHIFT (15U) +/*! NOISY - Noisy Data Received + * 0b0..Received without noise + * 0b1..Received with noise + */ +#define LPUART_DATA_NOISY(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_NOISY_SHIFT)) & LPUART_DATA_NOISY_MASK) +/*! @} */ + +/*! @name MATCH - Match Address */ +/*! @{ */ + +#define LPUART_MATCH_MA1_MASK (0x3FFU) +#define LPUART_MATCH_MA1_SHIFT (0U) +/*! MA1 - Match Address 1 */ +#define LPUART_MATCH_MA1(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MATCH_MA1_SHIFT)) & LPUART_MATCH_MA1_MASK) + +#define LPUART_MATCH_MA2_MASK (0x3FF0000U) +#define LPUART_MATCH_MA2_SHIFT (16U) +/*! MA2 - Match Address 2 */ +#define LPUART_MATCH_MA2(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MATCH_MA2_SHIFT)) & LPUART_MATCH_MA2_MASK) +/*! @} */ + +/*! @name MODIR - MODEM IrDA */ +/*! @{ */ + +#define LPUART_MODIR_TXCTSE_MASK (0x1U) +#define LPUART_MODIR_TXCTSE_SHIFT (0U) +/*! TXCTSE - Transmitter CTS Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPUART_MODIR_TXCTSE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSE_SHIFT)) & LPUART_MODIR_TXCTSE_MASK) + +#define LPUART_MODIR_TXRTSE_MASK (0x2U) +#define LPUART_MODIR_TXRTSE_SHIFT (1U) +/*! TXRTSE - Transmitter RTS Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPUART_MODIR_TXRTSE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXRTSE_SHIFT)) & LPUART_MODIR_TXRTSE_MASK) + +#define LPUART_MODIR_TXRTSPOL_MASK (0x4U) +#define LPUART_MODIR_TXRTSPOL_SHIFT (2U) +/*! TXRTSPOL - Transmitter RTS Polarity + * 0b0..Active low + * 0b1..Active high + */ +#define LPUART_MODIR_TXRTSPOL(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXRTSPOL_SHIFT)) & LPUART_MODIR_TXRTSPOL_MASK) + +#define LPUART_MODIR_RXRTSE_MASK (0x8U) +#define LPUART_MODIR_RXRTSE_SHIFT (3U) +/*! RXRTSE - Receiver RTS Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPUART_MODIR_RXRTSE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_RXRTSE_SHIFT)) & LPUART_MODIR_RXRTSE_MASK) + +#define LPUART_MODIR_TXCTSC_MASK (0x10U) +#define LPUART_MODIR_TXCTSC_SHIFT (4U) +/*! TXCTSC - Transmit CTS Configuration + * 0b0..Sampled at the start of each character + * 0b1..Sampled when the transmitter is idle + */ +#define LPUART_MODIR_TXCTSC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSC_SHIFT)) & LPUART_MODIR_TXCTSC_MASK) + +#define LPUART_MODIR_TXCTSSRC_MASK (0x20U) +#define LPUART_MODIR_TXCTSSRC_SHIFT (5U) +/*! TXCTSSRC - Transmit CTS Source + * 0b0..The CTS_B pin + * 0b1..An internal connection to the receiver address match result + */ +#define LPUART_MODIR_TXCTSSRC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSSRC_SHIFT)) & LPUART_MODIR_TXCTSSRC_MASK) + +#define LPUART_MODIR_RTSWATER_MASK (0xF00U) +#define LPUART_MODIR_RTSWATER_SHIFT (8U) +/*! RTSWATER - Receive RTS Configuration */ +#define LPUART_MODIR_RTSWATER(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_RTSWATER_SHIFT)) & LPUART_MODIR_RTSWATER_MASK) + +#define LPUART_MODIR_TNP_MASK (0x30000U) +#define LPUART_MODIR_TNP_SHIFT (16U) +/*! TNP - Transmitter Narrow Pulse + * 0b00..1 / OSR + * 0b01..2 / OSR + * 0b10..3 / OSR + * 0b11..4 / OSR + */ +#define LPUART_MODIR_TNP(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TNP_SHIFT)) & LPUART_MODIR_TNP_MASK) + +#define LPUART_MODIR_IREN_MASK (0x40000U) +#define LPUART_MODIR_IREN_SHIFT (18U) +/*! IREN - IR Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPUART_MODIR_IREN(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_IREN_SHIFT)) & LPUART_MODIR_IREN_MASK) +/*! @} */ + +/*! @name FIFO - FIFO */ +/*! @{ */ + +#define LPUART_FIFO_RXFIFOSIZE_MASK (0x7U) +#define LPUART_FIFO_RXFIFOSIZE_SHIFT (0U) +/*! RXFIFOSIZE - Receive FIFO Buffer Depth + * 0b000..1 + * 0b001..4 + * 0b010..8 + * 0b011..16 + * 0b100..32 + * 0b101..64 + * 0b110..128 + * 0b111..256 + */ +#define LPUART_FIFO_RXFIFOSIZE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXFIFOSIZE_SHIFT)) & LPUART_FIFO_RXFIFOSIZE_MASK) + +#define LPUART_FIFO_RXFE_MASK (0x8U) +#define LPUART_FIFO_RXFE_SHIFT (3U) +/*! RXFE - Receive FIFO Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPUART_FIFO_RXFE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXFE_SHIFT)) & LPUART_FIFO_RXFE_MASK) + +#define LPUART_FIFO_TXFIFOSIZE_MASK (0x70U) +#define LPUART_FIFO_TXFIFOSIZE_SHIFT (4U) +/*! TXFIFOSIZE - Transmit FIFO Buffer Depth + * 0b000..1 + * 0b001..4 + * 0b010..8 + * 0b011..16 + * 0b100..32 + * 0b101..64 + * 0b110..128 + * 0b111..256 + */ +#define LPUART_FIFO_TXFIFOSIZE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXFIFOSIZE_SHIFT)) & LPUART_FIFO_TXFIFOSIZE_MASK) + +#define LPUART_FIFO_TXFE_MASK (0x80U) +#define LPUART_FIFO_TXFE_SHIFT (7U) +/*! TXFE - Transmit FIFO Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPUART_FIFO_TXFE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXFE_SHIFT)) & LPUART_FIFO_TXFE_MASK) + +#define LPUART_FIFO_RXUFE_MASK (0x100U) +#define LPUART_FIFO_RXUFE_SHIFT (8U) +/*! RXUFE - Receive FIFO Underflow Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPUART_FIFO_RXUFE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXUFE_SHIFT)) & LPUART_FIFO_RXUFE_MASK) + +#define LPUART_FIFO_TXOFE_MASK (0x200U) +#define LPUART_FIFO_TXOFE_SHIFT (9U) +/*! TXOFE - Transmit FIFO Overflow Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPUART_FIFO_TXOFE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXOFE_SHIFT)) & LPUART_FIFO_TXOFE_MASK) + +#define LPUART_FIFO_RXIDEN_MASK (0x1C00U) +#define LPUART_FIFO_RXIDEN_SHIFT (10U) +/*! RXIDEN - Receiver Idle Empty Enable + * 0b000..Disable STAT[RDRF] to become 1 because of partially filled FIFO when the receiver is idle + * 0b001..Enable STAT[RDRF] to become 1 because of partially filled FIFO when the receiver is idle for one character + * 0b010..Enable STAT[RDRF] to become 1 because of partially filled FIFO when the receiver is idle for two characters + * 0b011..Enable STAT[RDRF] to become 1 because of partially filled FIFO when the receiver is idle for four characters + * 0b100..Enable STAT[RDRF] to become 1 because of partially filled FIFO when the receiver is idle for eight characters + * 0b101..Enable STAT[RDRF] to become 1 because of partially filled FIFO when the receiver is idle for 16 characters + * 0b110..Enable STAT[RDRF] to become 1 because of partially filled FIFO when the receiver is idle for 32 characters + * 0b111..Enable STAT[RDRF] to become 1 because of partially filled FIFO when the receiver is idle for 64 characters + */ +#define LPUART_FIFO_RXIDEN(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXIDEN_SHIFT)) & LPUART_FIFO_RXIDEN_MASK) + +#define LPUART_FIFO_RXFLUSH_MASK (0x4000U) +#define LPUART_FIFO_RXFLUSH_SHIFT (14U) +/*! RXFLUSH - Receive FIFO Flush + * 0b0..No effect + * 0b1..All data flushed out + */ +#define LPUART_FIFO_RXFLUSH(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXFLUSH_SHIFT)) & LPUART_FIFO_RXFLUSH_MASK) + +#define LPUART_FIFO_TXFLUSH_MASK (0x8000U) +#define LPUART_FIFO_TXFLUSH_SHIFT (15U) +/*! TXFLUSH - Transmit FIFO Flush + * 0b0..No effect + * 0b1..All data flushed out + */ +#define LPUART_FIFO_TXFLUSH(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXFLUSH_SHIFT)) & LPUART_FIFO_TXFLUSH_MASK) + +#define LPUART_FIFO_RXUF_MASK (0x10000U) +#define LPUART_FIFO_RXUF_SHIFT (16U) +/*! RXUF - Receiver FIFO Underflow Flag + * 0b0..No underflow + * 0b0..No effect + * 0b1..Underflow + * 0b1..Clear the flag + */ +#define LPUART_FIFO_RXUF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXUF_SHIFT)) & LPUART_FIFO_RXUF_MASK) + +#define LPUART_FIFO_TXOF_MASK (0x20000U) +#define LPUART_FIFO_TXOF_SHIFT (17U) +/*! TXOF - Transmitter FIFO Overflow Flag + * 0b0..No overflow + * 0b0..No effect + * 0b1..Overflow + * 0b1..Clear the flag + */ +#define LPUART_FIFO_TXOF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXOF_SHIFT)) & LPUART_FIFO_TXOF_MASK) + +#define LPUART_FIFO_RXEMPT_MASK (0x400000U) +#define LPUART_FIFO_RXEMPT_SHIFT (22U) +/*! RXEMPT - Receive FIFO Or Buffer Empty + * 0b0..Not empty + * 0b1..Empty + */ +#define LPUART_FIFO_RXEMPT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXEMPT_SHIFT)) & LPUART_FIFO_RXEMPT_MASK) + +#define LPUART_FIFO_TXEMPT_MASK (0x800000U) +#define LPUART_FIFO_TXEMPT_SHIFT (23U) +/*! TXEMPT - Transmit FIFO Or Buffer Empty + * 0b0..Not empty + * 0b1..Empty + */ +#define LPUART_FIFO_TXEMPT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXEMPT_SHIFT)) & LPUART_FIFO_TXEMPT_MASK) +/*! @} */ + +/*! @name WATER - Watermark */ +/*! @{ */ + +#define LPUART_WATER_TXWATER_MASK (0xFU) +#define LPUART_WATER_TXWATER_SHIFT (0U) +/*! TXWATER - Transmit Watermark */ +#define LPUART_WATER_TXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_TXWATER_SHIFT)) & LPUART_WATER_TXWATER_MASK) + +#define LPUART_WATER_TXCOUNT_MASK (0x1F00U) +#define LPUART_WATER_TXCOUNT_SHIFT (8U) +/*! TXCOUNT - Transmit Counter */ +#define LPUART_WATER_TXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_TXCOUNT_SHIFT)) & LPUART_WATER_TXCOUNT_MASK) + +#define LPUART_WATER_RXWATER_MASK (0xF0000U) +#define LPUART_WATER_RXWATER_SHIFT (16U) +/*! RXWATER - Receive Watermark */ +#define LPUART_WATER_RXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_RXWATER_SHIFT)) & LPUART_WATER_RXWATER_MASK) + +#define LPUART_WATER_RXCOUNT_MASK (0x1F000000U) +#define LPUART_WATER_RXCOUNT_SHIFT (24U) +/*! RXCOUNT - Receive Counter */ +#define LPUART_WATER_RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_RXCOUNT_SHIFT)) & LPUART_WATER_RXCOUNT_MASK) +/*! @} */ + +/*! @name DATARO - Data Read-Only */ +/*! @{ */ + +#define LPUART_DATARO_DATA_MASK (0xFFFFU) +#define LPUART_DATARO_DATA_SHIFT (0U) +/*! DATA - Receive Data */ +#define LPUART_DATARO_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATARO_DATA_SHIFT)) & LPUART_DATARO_DATA_MASK) +/*! @} */ + +/*! @name MCR - MODEM Control */ +/*! @{ */ + +#define LPUART_MCR_CTS_MASK (0x1U) +#define LPUART_MCR_CTS_SHIFT (0U) +/*! CTS - Clear To Send + * 0b0..Disable interrupt + * 0b1..Enable interrupt + */ +#define LPUART_MCR_CTS(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MCR_CTS_SHIFT)) & LPUART_MCR_CTS_MASK) + +#define LPUART_MCR_DSR_MASK (0x2U) +#define LPUART_MCR_DSR_SHIFT (1U) +/*! DSR - Data Set Ready + * 0b0..Disable interrupt + * 0b1..Enable interrupt + */ +#define LPUART_MCR_DSR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MCR_DSR_SHIFT)) & LPUART_MCR_DSR_MASK) + +#define LPUART_MCR_RIN_MASK (0x4U) +#define LPUART_MCR_RIN_SHIFT (2U) +/*! RIN - Ring Indicator + * 0b0..Disable interrupt + * 0b1..Enable interrupt + */ +#define LPUART_MCR_RIN(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MCR_RIN_SHIFT)) & LPUART_MCR_RIN_MASK) + +#define LPUART_MCR_DCD_MASK (0x8U) +#define LPUART_MCR_DCD_SHIFT (3U) +/*! DCD - Data Carrier Detect + * 0b0..Disable interrupt + * 0b1..Enable interrupt + */ +#define LPUART_MCR_DCD(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MCR_DCD_SHIFT)) & LPUART_MCR_DCD_MASK) + +#define LPUART_MCR_DTR_MASK (0x100U) +#define LPUART_MCR_DTR_SHIFT (8U) +/*! DTR - Data Terminal Ready + * 0b0..Logic one + * 0b1..Logic zero + */ +#define LPUART_MCR_DTR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MCR_DTR_SHIFT)) & LPUART_MCR_DTR_MASK) + +#define LPUART_MCR_RTS_MASK (0x200U) +#define LPUART_MCR_RTS_SHIFT (9U) +/*! RTS - Request To Send + * 0b0..Logic one + * 0b1..Logic zero + */ +#define LPUART_MCR_RTS(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MCR_RTS_SHIFT)) & LPUART_MCR_RTS_MASK) +/*! @} */ + +/*! @name MSR - MODEM Status */ +/*! @{ */ + +#define LPUART_MSR_DCTS_MASK (0x1U) +#define LPUART_MSR_DCTS_SHIFT (0U) +/*! DCTS - Delta Clear To Send + * 0b0..Did not change state + * 0b0..No effect + * 0b1..Changed state + * 0b1..Clear the flag + */ +#define LPUART_MSR_DCTS(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MSR_DCTS_SHIFT)) & LPUART_MSR_DCTS_MASK) + +#define LPUART_MSR_DDSR_MASK (0x2U) +#define LPUART_MSR_DDSR_SHIFT (1U) +/*! DDSR - Delta Data Set Ready + * 0b0..Did not change state + * 0b0..No effect + * 0b1..Changed state + * 0b1..Clear the flag + */ +#define LPUART_MSR_DDSR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MSR_DDSR_SHIFT)) & LPUART_MSR_DDSR_MASK) + +#define LPUART_MSR_DRI_MASK (0x4U) +#define LPUART_MSR_DRI_SHIFT (2U) +/*! DRI - Delta Ring Indicator + * 0b0..Did not change state + * 0b0..No effect + * 0b1..Changed state + * 0b1..Clear the flag + */ +#define LPUART_MSR_DRI(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MSR_DRI_SHIFT)) & LPUART_MSR_DRI_MASK) + +#define LPUART_MSR_DDCD_MASK (0x8U) +#define LPUART_MSR_DDCD_SHIFT (3U) +/*! DDCD - Delta Data Carrier Detect + * 0b0..Did not change state + * 0b0..No effect + * 0b1..Changed state + * 0b1..Clear the flag + */ +#define LPUART_MSR_DDCD(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MSR_DDCD_SHIFT)) & LPUART_MSR_DDCD_MASK) + +#define LPUART_MSR_CTS_MASK (0x10U) +#define LPUART_MSR_CTS_SHIFT (4U) +/*! CTS - Clear To Send + * 0b0..Logic one + * 0b1..Logic zero + */ +#define LPUART_MSR_CTS(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MSR_CTS_SHIFT)) & LPUART_MSR_CTS_MASK) + +#define LPUART_MSR_DSR_MASK (0x20U) +#define LPUART_MSR_DSR_SHIFT (5U) +/*! DSR - Data Set Ready + * 0b0..Logic one + * 0b1..Logic zero + */ +#define LPUART_MSR_DSR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MSR_DSR_SHIFT)) & LPUART_MSR_DSR_MASK) + +#define LPUART_MSR_RIN_MASK (0x40U) +#define LPUART_MSR_RIN_SHIFT (6U) +/*! RIN - Ring Indicator + * 0b0..Logic one + * 0b1..Logic zero + */ +#define LPUART_MSR_RIN(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MSR_RIN_SHIFT)) & LPUART_MSR_RIN_MASK) + +#define LPUART_MSR_DCD_MASK (0x80U) +#define LPUART_MSR_DCD_SHIFT (7U) +/*! DCD - Data Carrier Detect + * 0b0..Logic one + * 0b1..Logic zero + */ +#define LPUART_MSR_DCD(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MSR_DCD_SHIFT)) & LPUART_MSR_DCD_MASK) +/*! @} */ + +/*! @name REIR - Receiver Extended Idle */ +/*! @{ */ + +#define LPUART_REIR_IDTIME_MASK (0x3FFFU) +#define LPUART_REIR_IDTIME_SHIFT (0U) +/*! IDTIME - Idle Time */ +#define LPUART_REIR_IDTIME(x) (((uint32_t)(((uint32_t)(x)) << LPUART_REIR_IDTIME_SHIFT)) & LPUART_REIR_IDTIME_MASK) +/*! @} */ + +/*! @name TEIR - Transmitter Extended Idle */ +/*! @{ */ + +#define LPUART_TEIR_IDTIME_MASK (0x3FFFU) +#define LPUART_TEIR_IDTIME_SHIFT (0U) +/*! IDTIME - Idle Time */ +#define LPUART_TEIR_IDTIME(x) (((uint32_t)(((uint32_t)(x)) << LPUART_TEIR_IDTIME_SHIFT)) & LPUART_TEIR_IDTIME_MASK) +/*! @} */ + +/*! @name HDCR - Half Duplex Control */ +/*! @{ */ + +#define LPUART_HDCR_TXSTALL_MASK (0x1U) +#define LPUART_HDCR_TXSTALL_SHIFT (0U) +/*! TXSTALL - Transmit Stall + * 0b0..No effect + * 0b1..Does not become busy + */ +#define LPUART_HDCR_TXSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPUART_HDCR_TXSTALL_SHIFT)) & LPUART_HDCR_TXSTALL_MASK) + +#define LPUART_HDCR_RXSEL_MASK (0x2U) +#define LPUART_HDCR_RXSEL_SHIFT (1U) +/*! RXSEL - Receive Select + * 0b0..RXD + * 0b1..TXD + */ +#define LPUART_HDCR_RXSEL(x) (((uint32_t)(((uint32_t)(x)) << LPUART_HDCR_RXSEL_SHIFT)) & LPUART_HDCR_RXSEL_MASK) + +#define LPUART_HDCR_RXWRMSK_MASK (0x4U) +#define LPUART_HDCR_RXWRMSK_SHIFT (2U) +/*! RXWRMSK - Receive FIFO Write Mask + * 0b0..Do not mask + * 0b1..Mask + */ +#define LPUART_HDCR_RXWRMSK(x) (((uint32_t)(((uint32_t)(x)) << LPUART_HDCR_RXWRMSK_SHIFT)) & LPUART_HDCR_RXWRMSK_MASK) + +#define LPUART_HDCR_RXMSK_MASK (0x8U) +#define LPUART_HDCR_RXMSK_SHIFT (3U) +/*! RXMSK - Receive Mask + * 0b0..Do not mask + * 0b1..Mask + */ +#define LPUART_HDCR_RXMSK(x) (((uint32_t)(((uint32_t)(x)) << LPUART_HDCR_RXMSK_SHIFT)) & LPUART_HDCR_RXMSK_MASK) + +#define LPUART_HDCR_RTSEXT_MASK (0xFF00U) +#define LPUART_HDCR_RTSEXT_SHIFT (8U) +/*! RTSEXT - RTS Extended */ +#define LPUART_HDCR_RTSEXT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_HDCR_RTSEXT_SHIFT)) & LPUART_HDCR_RTSEXT_MASK) +/*! @} */ + +/*! @name TOCR - Timeout Control */ +/*! @{ */ + +#define LPUART_TOCR_TOEN_MASK (0xFU) +#define LPUART_TOCR_TOEN_SHIFT (0U) +/*! TOEN - Timeout Enable */ +#define LPUART_TOCR_TOEN(x) (((uint32_t)(((uint32_t)(x)) << LPUART_TOCR_TOEN_SHIFT)) & LPUART_TOCR_TOEN_MASK) + +#define LPUART_TOCR_TOIE_MASK (0xF00U) +#define LPUART_TOCR_TOIE_SHIFT (8U) +/*! TOIE - Timeout Interrupt Enable */ +#define LPUART_TOCR_TOIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_TOCR_TOIE_SHIFT)) & LPUART_TOCR_TOIE_MASK) +/*! @} */ + +/*! @name TOSR - Timeout Status */ +/*! @{ */ + +#define LPUART_TOSR_TOZ_MASK (0xFU) +#define LPUART_TOSR_TOZ_SHIFT (0U) +/*! TOZ - Timeout Zero */ +#define LPUART_TOSR_TOZ(x) (((uint32_t)(((uint32_t)(x)) << LPUART_TOSR_TOZ_SHIFT)) & LPUART_TOSR_TOZ_MASK) + +#define LPUART_TOSR_TOF_MASK (0xF00U) +#define LPUART_TOSR_TOF_SHIFT (8U) +/*! TOF - Timeout Flag + * 0b0000..Not occurred + * 0b0000..No effect + * 0b0001..Occurred + * 0b0001..Clear the flag + */ +#define LPUART_TOSR_TOF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_TOSR_TOF_SHIFT)) & LPUART_TOSR_TOF_MASK) +/*! @} */ + +/*! @name TIMEOUT - Timeout N */ +/*! @{ */ + +#define LPUART_TIMEOUT_TIMEOUT_MASK (0x3FFFU) +#define LPUART_TIMEOUT_TIMEOUT_SHIFT (0U) +/*! TIMEOUT - Timeout Value */ +#define LPUART_TIMEOUT_TIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_TIMEOUT_TIMEOUT_SHIFT)) & LPUART_TIMEOUT_TIMEOUT_MASK) + +#define LPUART_TIMEOUT_CFG_MASK (0xC0000000U) +#define LPUART_TIMEOUT_CFG_SHIFT (30U) +/*! CFG - Idle Configuration + * 0b00..Becomes 1 after timeout characters are received + * 0b01..Becomes 1 when idle for timeout bit clocks + * 0b10..Becomes 1 when idle for timeout bit clocks following the next character + * 0b11..Becomes 1 when idle for at least timeout bit clocks, but a new character is detected before the extended idle timeout is reached + */ +#define LPUART_TIMEOUT_CFG(x) (((uint32_t)(((uint32_t)(x)) << LPUART_TIMEOUT_CFG_SHIFT)) & LPUART_TIMEOUT_CFG_MASK) +/*! @} */ + +/* The count of LPUART_TIMEOUT */ +#define LPUART_TIMEOUT_COUNT (4U) + +/*! @name TCBR - Transmit Command Burst */ +/*! @{ */ + +#define LPUART_TCBR_DATA_MASK (0xFFFFU) +#define LPUART_TCBR_DATA_SHIFT (0U) +/*! DATA - Data */ +#define LPUART_TCBR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPUART_TCBR_DATA_SHIFT)) & LPUART_TCBR_DATA_MASK) +/*! @} */ + +/* The count of LPUART_TCBR */ +#define LPUART_TCBR_COUNT (128U) + +/*! @name TDBR - Transmit Data Burst */ +/*! @{ */ + +#define LPUART_TDBR_DATA0_MASK (0xFFU) +#define LPUART_TDBR_DATA0_SHIFT (0U) +/*! DATA0 - Data0 */ +#define LPUART_TDBR_DATA0(x) (((uint32_t)(((uint32_t)(x)) << LPUART_TDBR_DATA0_SHIFT)) & LPUART_TDBR_DATA0_MASK) + +#define LPUART_TDBR_DATA1_MASK (0xFF00U) +#define LPUART_TDBR_DATA1_SHIFT (8U) +/*! DATA1 - Data1 */ +#define LPUART_TDBR_DATA1(x) (((uint32_t)(((uint32_t)(x)) << LPUART_TDBR_DATA1_SHIFT)) & LPUART_TDBR_DATA1_MASK) + +#define LPUART_TDBR_DATA2_MASK (0xFF0000U) +#define LPUART_TDBR_DATA2_SHIFT (16U) +/*! DATA2 - Data2 */ +#define LPUART_TDBR_DATA2(x) (((uint32_t)(((uint32_t)(x)) << LPUART_TDBR_DATA2_SHIFT)) & LPUART_TDBR_DATA2_MASK) + +#define LPUART_TDBR_DATA3_MASK (0xFF000000U) +#define LPUART_TDBR_DATA3_SHIFT (24U) +/*! DATA3 - Data3 */ +#define LPUART_TDBR_DATA3(x) (((uint32_t)(((uint32_t)(x)) << LPUART_TDBR_DATA3_SHIFT)) & LPUART_TDBR_DATA3_MASK) +/*! @} */ + +/* The count of LPUART_TDBR */ +#define LPUART_TDBR_COUNT (256U) + + +/*! + * @} + */ /* end of group LPUART_Register_Masks */ + + +/* LPUART - Peripheral instance base addresses */ +/** Peripheral LPUART1 base address */ +#define LPUART1_BASE (0x44380000u) +/** Peripheral LPUART1 base pointer */ +extern LPUART_Type* LPUART1; +/** Peripheral LPUART2 base address */ +#define LPUART2_BASE (0x44390000u) +/** Peripheral LPUART2 base pointer */ +extern LPUART_Type* LPUART2; +/** Peripheral LPUART3 base address */ +#define LPUART3_BASE (0x42570000u) +/** Peripheral LPUART3 base pointer */ +extern LPUART_Type* LPUART3; +/** Peripheral LPUART4 base address */ +#define LPUART4_BASE (0x42580000u) +/** Peripheral LPUART4 base pointer */ +extern LPUART_Type* LPUART4; +/** Peripheral LPUART5 base address */ +#define LPUART5_BASE (0x42590000u) +/** Peripheral LPUART5 base pointer */ +extern LPUART_Type* LPUART5; +/** Peripheral LPUART6 base address */ +#define LPUART6_BASE (0x425A0000u) +/** Peripheral LPUART6 base pointer */ +extern LPUART_Type* LPUART6; +/** Peripheral LPUART7 base address */ +#define LPUART7_BASE (0x42690000u) +/** Peripheral LPUART7 base pointer */ +extern LPUART_Type* LPUART7; +/** Peripheral LPUART8 base address */ +#define LPUART8_BASE (0x426A0000u) +/** Peripheral LPUART8 base pointer */ +extern LPUART_Type* LPUART8; +/** Array initializer of LPUART peripheral base addresses */ +#define LPUART_BASE_ADDRS { 0u, LPUART1_BASE, LPUART2_BASE, LPUART3_BASE, LPUART4_BASE, LPUART5_BASE, LPUART6_BASE, LPUART7_BASE, LPUART8_BASE } +/** Array initializer of LPUART peripheral base pointers */ +#define LPUART_BASE_PTRS { (LPUART_Type **)0u, &LPUART1, &LPUART2, &LPUART3, &LPUART4, &LPUART5, &LPUART6, &LPUART7, &LPUART8 } +/** Interrupt vectors for the LPUART peripheral type */ +#define LPUART_RX_TX_IRQS { NotAvail_IRQn, LPUART1_IRQn, LPUART2_IRQn, LPUART3_IRQn, LPUART4_IRQn, LPUART5_IRQn, LPUART6_IRQn, LPUART7_IRQn, LPUART8_IRQn } + +/*! + * @} + */ /* end of group LPUART_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- MU Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup MU_Peripheral_Access_Layer MU Peripheral Access Layer + * @{ + */ + +/** MU - Register Layout Typedef */ +typedef struct { + __I uint32_t VER; /**< Version ID, offset: 0x0 */ + __I uint32_t PAR; /**< Parameter, offset: 0x4 */ + __IO uint32_t CR; /**< Control, offset: 0x8 */ + __IO uint32_t SR; /**< Status, offset: 0xC */ + __IO uint32_t CCR0; /**< Core Control 0, offset: 0x10 */ + uint32_t CIER0; /**< Core Interrupt Enable 0, offset: 0x14 */ + __IO uint32_t CSSR0; /**< Core Sticky Status 0, offset: 0x18 */ + uint8_t RESERVED_0[228]; + __IO uint32_t FCR; /**< Flag Control, offset: 0x100 */ + __I uint32_t FSR; /**< Flag Status, offset: 0x104 */ + uint8_t RESERVED_1[8]; + __IO uint32_t GIER; /**< General-Purpose Interrupt Enable, offset: 0x110 */ + __IO uint32_t GCR; /**< General-Purpose Control, offset: 0x114 */ + __IO uint32_t GSR; /**< General-purpose Status, offset: 0x118 */ + uint8_t RESERVED_2[4]; + __IO uint32_t TCR; /**< Transmit Control, offset: 0x120 */ + __I uint32_t TSR; /**< Transmit Status, offset: 0x124 */ + __IO uint32_t RCR; /**< Receive Control, offset: 0x128 */ + __I uint32_t RSR; /**< Receive Status, offset: 0x12C */ + uint8_t RESERVED_3[208]; + __IO uint32_t TR[4]; /**< Transmit, array offset: 0x200, array step: 0x4 */ + uint8_t RESERVED_4[112]; + __I uint32_t RR[4]; /**< Receive, array offset: 0x280, array step: 0x4 */ +} MU_Type; + +/* ---------------------------------------------------------------------------- + -- MU Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup MU_Register_Masks MU Register Masks + * @{ + */ + +/*! @name VER - Version ID */ +/*! @{ */ + +#define MU_VER_FEATURE_MASK (0xFFFFU) +#define MU_VER_FEATURE_SHIFT (0U) +/*! FEATURE - Feature Set Number */ +#define MU_VER_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << MU_VER_FEATURE_SHIFT)) & MU_VER_FEATURE_MASK) + +#define MU_VER_MINOR_MASK (0xFF0000U) +#define MU_VER_MINOR_SHIFT (16U) +/*! MINOR - Minor Version Number */ +#define MU_VER_MINOR(x) (((uint32_t)(((uint32_t)(x)) << MU_VER_MINOR_SHIFT)) & MU_VER_MINOR_MASK) + +#define MU_VER_MAJOR_MASK (0xFF000000U) +#define MU_VER_MAJOR_SHIFT (24U) +/*! MAJOR - Major Version Number */ +#define MU_VER_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << MU_VER_MAJOR_SHIFT)) & MU_VER_MAJOR_MASK) +/*! @} */ + +/*! @name PAR - Parameter */ +/*! @{ */ + +#define MU_PAR_TR_NUM_MASK (0xFFU) +#define MU_PAR_TR_NUM_SHIFT (0U) +/*! TR_NUM - Transmit Register Number */ +#define MU_PAR_TR_NUM(x) (((uint32_t)(((uint32_t)(x)) << MU_PAR_TR_NUM_SHIFT)) & MU_PAR_TR_NUM_MASK) + +#define MU_PAR_RR_NUM_MASK (0xFF00U) +#define MU_PAR_RR_NUM_SHIFT (8U) +/*! RR_NUM - Receive Register Number */ +#define MU_PAR_RR_NUM(x) (((uint32_t)(((uint32_t)(x)) << MU_PAR_RR_NUM_SHIFT)) & MU_PAR_RR_NUM_MASK) + +#define MU_PAR_GIR_NUM_MASK (0xFF0000U) +#define MU_PAR_GIR_NUM_SHIFT (16U) +/*! GIR_NUM - General-Purpose Interrupt Request Number */ +#define MU_PAR_GIR_NUM(x) (((uint32_t)(((uint32_t)(x)) << MU_PAR_GIR_NUM_SHIFT)) & MU_PAR_GIR_NUM_MASK) + +#define MU_PAR_FLAG_WIDTH_MASK (0xFF000000U) +#define MU_PAR_FLAG_WIDTH_SHIFT (24U) +/*! FLAG_WIDTH - Flag Width */ +#define MU_PAR_FLAG_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << MU_PAR_FLAG_WIDTH_SHIFT)) & MU_PAR_FLAG_WIDTH_MASK) +/*! @} */ + +/*! @name CR - Control */ +/*! @{ */ + +#define MU_CR_MUR_MASK (0x1U) +#define MU_CR_MUR_SHIFT (0U) +/*! MUR - MU Reset + * 0b0..Idle + * 0b1..Reset + */ +#define MU_CR_MUR(x) (((uint32_t)(((uint32_t)(x)) << MU_CR_MUR_SHIFT)) & MU_CR_MUR_MASK) + +#define MU_CR_MURIE_MASK (0x2U) +#define MU_CR_MURIE_SHIFT (1U) +/*! MURIE - MUB Reset Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define MU_CR_MURIE(x) (((uint32_t)(((uint32_t)(x)) << MU_CR_MURIE_SHIFT)) & MU_CR_MURIE_MASK) +/*! @} */ + +/*! @name SR - Status */ +/*! @{ */ + +#define MU_SR_MURS_MASK (0x1U) +#define MU_SR_MURS_SHIFT (0U) +/*! MURS - MUA and MUB Reset State + * 0b0..Out of reset + * 0b1..In reset + */ +#define MU_SR_MURS(x) (((uint32_t)(((uint32_t)(x)) << MU_SR_MURS_SHIFT)) & MU_SR_MURS_MASK) + +#define MU_SR_MURIP_MASK (0x2U) +#define MU_SR_MURIP_SHIFT (1U) +/*! MURIP - MU Reset Interrupt Pending Flag + * 0b0..Reset not issued + * 0b0..No effect + * 0b1..Reset issued + * 0b1..Clear the flag + */ +#define MU_SR_MURIP(x) (((uint32_t)(((uint32_t)(x)) << MU_SR_MURIP_SHIFT)) & MU_SR_MURIP_MASK) + +#define MU_SR_EP_MASK (0x4U) +#define MU_SR_EP_SHIFT (2U) +/*! EP - MUB Side Event Pending + * 0b0..Not pending + * 0b1..Pending + */ +#define MU_SR_EP(x) (((uint32_t)(((uint32_t)(x)) << MU_SR_EP_SHIFT)) & MU_SR_EP_MASK) + +#define MU_SR_FUP_MASK (0x8U) +#define MU_SR_FUP_SHIFT (3U) +/*! FUP - MUB Flag Update Pending + * 0b0..No pending update flags (initiated by MUA) + * 0b1..Pending update flags (initiated by MUA) + */ +#define MU_SR_FUP(x) (((uint32_t)(((uint32_t)(x)) << MU_SR_FUP_SHIFT)) & MU_SR_FUP_MASK) + +#define MU_SR_GIRP_MASK (0x10U) +#define MU_SR_GIRP_SHIFT (4U) +/*! GIRP - MUB General-Purpose Interrupt Pending + * 0b0..No request sent + * 0b1..Request sent + */ +#define MU_SR_GIRP(x) (((uint32_t)(((uint32_t)(x)) << MU_SR_GIRP_SHIFT)) & MU_SR_GIRP_MASK) + +#define MU_SR_TEP_MASK (0x20U) +#define MU_SR_TEP_SHIFT (5U) +/*! TEP - MUB Transmit Empty Pending + * 0b0..Not pending; MUA is reading no Receive (RRn) register + * 0b1..Pending; MUA is reading a Receive (RRn) register + */ +#define MU_SR_TEP(x) (((uint32_t)(((uint32_t)(x)) << MU_SR_TEP_SHIFT)) & MU_SR_TEP_MASK) + +#define MU_SR_RFP_MASK (0x40U) +#define MU_SR_RFP_SHIFT (6U) +/*! RFP - MUB Receive Full Pending + * 0b0..Not pending; MUA is not writing to a Transmit register + * 0b1..Pending; MUA is writing to a Transmit register + */ +#define MU_SR_RFP(x) (((uint32_t)(((uint32_t)(x)) << MU_SR_RFP_SHIFT)) & MU_SR_RFP_MASK) +/*! @} */ + +/*! @name CCR0 - Core Control 0 */ +/*! @{ */ + +#define MU_CCR0_NMI_MASK (0x1U) +#define MU_CCR0_NMI_SHIFT (0U) +/*! NMI - MUB Nonmaskable Interrupt Request + * 0b0..Nonmaskable interrupt not issued + * 0b1..Nonmaskable interrupt issued + */ +#define MU_CCR0_NMI(x) (((uint32_t)(((uint32_t)(x)) << MU_CCR0_NMI_SHIFT)) & MU_CCR0_NMI_MASK) +/*! @} */ + +/*! @name CSSR0 - Core Sticky Status 0 */ +/*! @{ */ + +#define MU_CSSR0_NMIC_MASK (0x1U) +#define MU_CSSR0_NMIC_SHIFT (0U) +/*! NMIC - Processor B Nonmaskable Interrupt Clear + * 0b0..Default + * 0b1..Clear MUA_CCR0[NMI] + */ +#define MU_CSSR0_NMIC(x) (((uint32_t)(((uint32_t)(x)) << MU_CSSR0_NMIC_SHIFT)) & MU_CSSR0_NMIC_MASK) +/*! @} */ + +/*! @name FCR - Flag Control */ +/*! @{ */ + +#define MU_FCR_F0_MASK (0x1U) +#define MU_FCR_F0_SHIFT (0U) +/*! F0 - MUB to MUA Flag + * 0b0..Clear MUA_FSR[Fn] + * 0b1..Set MUA_FSR[Fn] + */ +#define MU_FCR_F0(x) (((uint32_t)(((uint32_t)(x)) << MU_FCR_F0_SHIFT)) & MU_FCR_F0_MASK) + +#define MU_FCR_F1_MASK (0x2U) +#define MU_FCR_F1_SHIFT (1U) +/*! F1 - MUB to MUA Flag + * 0b0..Clear MUA_FSR[Fn] + * 0b1..Set MUA_FSR[Fn] + */ +#define MU_FCR_F1(x) (((uint32_t)(((uint32_t)(x)) << MU_FCR_F1_SHIFT)) & MU_FCR_F1_MASK) + +#define MU_FCR_F2_MASK (0x4U) +#define MU_FCR_F2_SHIFT (2U) +/*! F2 - MUB to MUA Flag + * 0b0..Clear MUA_FSR[Fn] + * 0b1..Set MUA_FSR[Fn] + */ +#define MU_FCR_F2(x) (((uint32_t)(((uint32_t)(x)) << MU_FCR_F2_SHIFT)) & MU_FCR_F2_MASK) +/*! @} */ + +/*! @name FSR - Flag Status */ +/*! @{ */ + +#define MU_FSR_F0_MASK (0x1U) +#define MU_FSR_F0_SHIFT (0U) +/*! F0 - MUB to MUA-Side Flag + * 0b0..MUA_FCR[Fn] = 0 + * 0b1..MUA_FCR[Fn] = 1 + */ +#define MU_FSR_F0(x) (((uint32_t)(((uint32_t)(x)) << MU_FSR_F0_SHIFT)) & MU_FSR_F0_MASK) + +#define MU_FSR_F1_MASK (0x2U) +#define MU_FSR_F1_SHIFT (1U) +/*! F1 - MUB to MUA-Side Flag + * 0b0..MUA_FCR[Fn] = 0 + * 0b1..MUA_FCR[Fn] = 1 + */ +#define MU_FSR_F1(x) (((uint32_t)(((uint32_t)(x)) << MU_FSR_F1_SHIFT)) & MU_FSR_F1_MASK) + +#define MU_FSR_F2_MASK (0x4U) +#define MU_FSR_F2_SHIFT (2U) +/*! F2 - MUB to MUA-Side Flag + * 0b0..MUA_FCR[Fn] = 0 + * 0b1..MUA_FCR[Fn] = 1 + */ +#define MU_FSR_F2(x) (((uint32_t)(((uint32_t)(x)) << MU_FSR_F2_SHIFT)) & MU_FSR_F2_MASK) +/*! @} */ + +/*! @name GIER - General-Purpose Interrupt Enable */ +/*! @{ */ + +#define MU_GIER_GIE0_MASK (0x1U) +#define MU_GIER_GIE0_SHIFT (0U) +/*! GIE0 - MUB General-purpose Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define MU_GIER_GIE0(x) (((uint32_t)(((uint32_t)(x)) << MU_GIER_GIE0_SHIFT)) & MU_GIER_GIE0_MASK) + +#define MU_GIER_GIE1_MASK (0x2U) +#define MU_GIER_GIE1_SHIFT (1U) +/*! GIE1 - MUB General-purpose Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define MU_GIER_GIE1(x) (((uint32_t)(((uint32_t)(x)) << MU_GIER_GIE1_SHIFT)) & MU_GIER_GIE1_MASK) + +#define MU_GIER_GIE2_MASK (0x4U) +#define MU_GIER_GIE2_SHIFT (2U) +/*! GIE2 - MUB General-purpose Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define MU_GIER_GIE2(x) (((uint32_t)(((uint32_t)(x)) << MU_GIER_GIE2_SHIFT)) & MU_GIER_GIE2_MASK) + +#define MU_GIER_GIE3_MASK (0x8U) +#define MU_GIER_GIE3_SHIFT (3U) +/*! GIE3 - MUB General-purpose Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define MU_GIER_GIE3(x) (((uint32_t)(((uint32_t)(x)) << MU_GIER_GIE3_SHIFT)) & MU_GIER_GIE3_MASK) +/*! @} */ + +/*! @name GCR - General-Purpose Control */ +/*! @{ */ + +#define MU_GCR_GIR0_MASK (0x1U) +#define MU_GCR_GIR0_SHIFT (0U) +/*! GIR0 - MUB General-Purpose Interrupt Request + * 0b0..Not requested + * 0b1..Requested + */ +#define MU_GCR_GIR0(x) (((uint32_t)(((uint32_t)(x)) << MU_GCR_GIR0_SHIFT)) & MU_GCR_GIR0_MASK) + +#define MU_GCR_GIR1_MASK (0x2U) +#define MU_GCR_GIR1_SHIFT (1U) +/*! GIR1 - MUB General-Purpose Interrupt Request + * 0b0..Not requested + * 0b1..Requested + */ +#define MU_GCR_GIR1(x) (((uint32_t)(((uint32_t)(x)) << MU_GCR_GIR1_SHIFT)) & MU_GCR_GIR1_MASK) + +#define MU_GCR_GIR2_MASK (0x4U) +#define MU_GCR_GIR2_SHIFT (2U) +/*! GIR2 - MUB General-Purpose Interrupt Request + * 0b0..Not requested + * 0b1..Requested + */ +#define MU_GCR_GIR2(x) (((uint32_t)(((uint32_t)(x)) << MU_GCR_GIR2_SHIFT)) & MU_GCR_GIR2_MASK) + +#define MU_GCR_GIR3_MASK (0x8U) +#define MU_GCR_GIR3_SHIFT (3U) +/*! GIR3 - MUB General-Purpose Interrupt Request + * 0b0..Not requested + * 0b1..Requested + */ +#define MU_GCR_GIR3(x) (((uint32_t)(((uint32_t)(x)) << MU_GCR_GIR3_SHIFT)) & MU_GCR_GIR3_MASK) +/*! @} */ + +/*! @name GSR - General-purpose Status */ +/*! @{ */ + +#define MU_GSR_GIP0_MASK (0x1U) +#define MU_GSR_GIP0_SHIFT (0U) +/*! GIP0 - MUB General-Purpose Interrupt Request Pending + * 0b0..Not pending + * 0b0..No effect + * 0b1..Pending + * 0b1..Clear the flag + */ +#define MU_GSR_GIP0(x) (((uint32_t)(((uint32_t)(x)) << MU_GSR_GIP0_SHIFT)) & MU_GSR_GIP0_MASK) + +#define MU_GSR_GIP1_MASK (0x2U) +#define MU_GSR_GIP1_SHIFT (1U) +/*! GIP1 - MUB General-Purpose Interrupt Request Pending + * 0b0..Not pending + * 0b0..No effect + * 0b1..Pending + * 0b1..Clear the flag + */ +#define MU_GSR_GIP1(x) (((uint32_t)(((uint32_t)(x)) << MU_GSR_GIP1_SHIFT)) & MU_GSR_GIP1_MASK) + +#define MU_GSR_GIP2_MASK (0x4U) +#define MU_GSR_GIP2_SHIFT (2U) +/*! GIP2 - MUB General-Purpose Interrupt Request Pending + * 0b0..Not pending + * 0b0..No effect + * 0b1..Pending + * 0b1..Clear the flag + */ +#define MU_GSR_GIP2(x) (((uint32_t)(((uint32_t)(x)) << MU_GSR_GIP2_SHIFT)) & MU_GSR_GIP2_MASK) + +#define MU_GSR_GIP3_MASK (0x8U) +#define MU_GSR_GIP3_SHIFT (3U) +/*! GIP3 - MUB General-Purpose Interrupt Request Pending + * 0b0..Not pending + * 0b0..No effect + * 0b1..Pending + * 0b1..Clear the flag + */ +#define MU_GSR_GIP3(x) (((uint32_t)(((uint32_t)(x)) << MU_GSR_GIP3_SHIFT)) & MU_GSR_GIP3_MASK) +/*! @} */ + +/*! @name TCR - Transmit Control */ +/*! @{ */ + +#define MU_TCR_TIE0_MASK (0x1U) +#define MU_TCR_TIE0_SHIFT (0U) +/*! TIE0 - MUB Transmit Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define MU_TCR_TIE0(x) (((uint32_t)(((uint32_t)(x)) << MU_TCR_TIE0_SHIFT)) & MU_TCR_TIE0_MASK) + +#define MU_TCR_TIE1_MASK (0x2U) +#define MU_TCR_TIE1_SHIFT (1U) +/*! TIE1 - MUB Transmit Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define MU_TCR_TIE1(x) (((uint32_t)(((uint32_t)(x)) << MU_TCR_TIE1_SHIFT)) & MU_TCR_TIE1_MASK) + +#define MU_TCR_TIE2_MASK (0x4U) +#define MU_TCR_TIE2_SHIFT (2U) +/*! TIE2 - MUB Transmit Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define MU_TCR_TIE2(x) (((uint32_t)(((uint32_t)(x)) << MU_TCR_TIE2_SHIFT)) & MU_TCR_TIE2_MASK) + +#define MU_TCR_TIE3_MASK (0x8U) +#define MU_TCR_TIE3_SHIFT (3U) +/*! TIE3 - MUB Transmit Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define MU_TCR_TIE3(x) (((uint32_t)(((uint32_t)(x)) << MU_TCR_TIE3_SHIFT)) & MU_TCR_TIE3_MASK) +/*! @} */ + +/*! @name TSR - Transmit Status */ +/*! @{ */ + +#define MU_TSR_TE0_MASK (0x1U) +#define MU_TSR_TE0_SHIFT (0U) +/*! TE0 - MUB Transmit Empty + * 0b0..Not empty + * 0b1..Empty + */ +#define MU_TSR_TE0(x) (((uint32_t)(((uint32_t)(x)) << MU_TSR_TE0_SHIFT)) & MU_TSR_TE0_MASK) + +#define MU_TSR_TE1_MASK (0x2U) +#define MU_TSR_TE1_SHIFT (1U) +/*! TE1 - MUB Transmit Empty + * 0b0..Not empty + * 0b1..Empty + */ +#define MU_TSR_TE1(x) (((uint32_t)(((uint32_t)(x)) << MU_TSR_TE1_SHIFT)) & MU_TSR_TE1_MASK) + +#define MU_TSR_TE2_MASK (0x4U) +#define MU_TSR_TE2_SHIFT (2U) +/*! TE2 - MUB Transmit Empty + * 0b0..Not empty + * 0b1..Empty + */ +#define MU_TSR_TE2(x) (((uint32_t)(((uint32_t)(x)) << MU_TSR_TE2_SHIFT)) & MU_TSR_TE2_MASK) + +#define MU_TSR_TE3_MASK (0x8U) +#define MU_TSR_TE3_SHIFT (3U) +/*! TE3 - MUB Transmit Empty + * 0b0..Not empty + * 0b1..Empty + */ +#define MU_TSR_TE3(x) (((uint32_t)(((uint32_t)(x)) << MU_TSR_TE3_SHIFT)) & MU_TSR_TE3_MASK) +/*! @} */ + +/*! @name RCR - Receive Control */ +/*! @{ */ + +#define MU_RCR_RIE0_MASK (0x1U) +#define MU_RCR_RIE0_SHIFT (0U) +/*! RIE0 - MUB Receive Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define MU_RCR_RIE0(x) (((uint32_t)(((uint32_t)(x)) << MU_RCR_RIE0_SHIFT)) & MU_RCR_RIE0_MASK) + +#define MU_RCR_RIE1_MASK (0x2U) +#define MU_RCR_RIE1_SHIFT (1U) +/*! RIE1 - MUB Receive Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define MU_RCR_RIE1(x) (((uint32_t)(((uint32_t)(x)) << MU_RCR_RIE1_SHIFT)) & MU_RCR_RIE1_MASK) + +#define MU_RCR_RIE2_MASK (0x4U) +#define MU_RCR_RIE2_SHIFT (2U) +/*! RIE2 - MUB Receive Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define MU_RCR_RIE2(x) (((uint32_t)(((uint32_t)(x)) << MU_RCR_RIE2_SHIFT)) & MU_RCR_RIE2_MASK) + +#define MU_RCR_RIE3_MASK (0x8U) +#define MU_RCR_RIE3_SHIFT (3U) +/*! RIE3 - MUB Receive Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define MU_RCR_RIE3(x) (((uint32_t)(((uint32_t)(x)) << MU_RCR_RIE3_SHIFT)) & MU_RCR_RIE3_MASK) +/*! @} */ + +/*! @name RSR - Receive Status */ +/*! @{ */ + +#define MU_RSR_RF0_MASK (0x1U) +#define MU_RSR_RF0_SHIFT (0U) +/*! RF0 - MUB Receive Register Full + * 0b0..Not full + * 0b1..Full + */ +#define MU_RSR_RF0(x) (((uint32_t)(((uint32_t)(x)) << MU_RSR_RF0_SHIFT)) & MU_RSR_RF0_MASK) + +#define MU_RSR_RF1_MASK (0x2U) +#define MU_RSR_RF1_SHIFT (1U) +/*! RF1 - MUB Receive Register Full + * 0b0..Not full + * 0b1..Full + */ +#define MU_RSR_RF1(x) (((uint32_t)(((uint32_t)(x)) << MU_RSR_RF1_SHIFT)) & MU_RSR_RF1_MASK) + +#define MU_RSR_RF2_MASK (0x4U) +#define MU_RSR_RF2_SHIFT (2U) +/*! RF2 - MUB Receive Register Full + * 0b0..Not full + * 0b1..Full + */ +#define MU_RSR_RF2(x) (((uint32_t)(((uint32_t)(x)) << MU_RSR_RF2_SHIFT)) & MU_RSR_RF2_MASK) + +#define MU_RSR_RF3_MASK (0x8U) +#define MU_RSR_RF3_SHIFT (3U) +/*! RF3 - MUB Receive Register Full + * 0b0..Not full + * 0b1..Full + */ +#define MU_RSR_RF3(x) (((uint32_t)(((uint32_t)(x)) << MU_RSR_RF3_SHIFT)) & MU_RSR_RF3_MASK) +/*! @} */ + +/*! @name TR - Transmit */ +/*! @{ */ + +#define MU_TR_TR_DATA_MASK (0xFFFFFFFFU) +#define MU_TR_TR_DATA_SHIFT (0U) +/*! TR_DATA - MUB Transmit Data */ +#define MU_TR_TR_DATA(x) (((uint32_t)(((uint32_t)(x)) << MU_TR_TR_DATA_SHIFT)) & MU_TR_TR_DATA_MASK) +/*! @} */ + +/* The count of MU_TR */ +#define MU_TR_COUNT (4U) + +/*! @name RR - Receive */ +/*! @{ */ + +#define MU_RR_RR_DATA_MASK (0xFFFFFFFFU) +#define MU_RR_RR_DATA_SHIFT (0U) +/*! RR_DATA - MUB Receive Data */ +#define MU_RR_RR_DATA(x) (((uint32_t)(((uint32_t)(x)) << MU_RR_RR_DATA_SHIFT)) & MU_RR_RR_DATA_MASK) +/*! @} */ + +/* The count of MU_RR */ +#define MU_RR_COUNT (4U) + + +/*! + * @} + */ /* end of group MU_Register_Masks */ + + +/* MU - Peripheral instance base addresses */ +/** Peripheral MU1__MUA base address */ +#define MU1__MUA_BASE (0x44220000u) +/** Peripheral MU1__MUA base pointer */ +#define MU1__MUA ((MU_Type *)MU1__MUA_BASE) +/** Peripheral MU1__MUB base address */ +#define MU1__MUB_BASE (0x44230000u) +/** Peripheral MU1__MUB base pointer */ +#define MU1__MUB ((MU_Type *)MU1__MUB_BASE) +/** Peripheral MU2__MUA base address */ +#define MU2__MUA_BASE (0x42430000u) +/** Peripheral MU2__MUA base pointer */ +#define MU2__MUA ((MU_Type *)MU2__MUA_BASE) +/** Peripheral MU2__MUB base address */ +#define MU2__MUB_BASE (0x42440000u) +/** Peripheral MU2__MUB base pointer */ +#define MU2__MUB ((MU_Type *)MU2__MUB_BASE) +/** Array initializer of MU peripheral base addresses */ +#define MU_BASE_ADDRS { MU1__MUA_BASE, MU1__MUB_BASE, MU2__MUA_BASE, MU2__MUB_BASE } +/** Array initializer of MU peripheral base pointers */ +#define MU_BASE_PTRS { MU1__MUA, MU1__MUB, MU2__MUA, MU2__MUB } + +/*! + * @} + */ /* end of group MU_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- OCRAM_CTRL Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup OCRAM_CTRL_Peripheral_Access_Layer OCRAM_CTRL Peripheral Access Layer + * @{ + */ + +/** OCRAM_CTRL - Register Layout Typedef */ +typedef struct { + __IO uint32_t RAMCR; /**< RAM Control, offset: 0x0 */ + __IO uint32_t RAMIAS; /**< RAM Initialization Address Start, offset: 0x4 */ + __IO uint32_t RAMIAE; /**< RAM Initialization Address End, offset: 0x8 */ + __IO uint32_t RAMSR; /**< RAM Status, offset: 0xC */ + __I uint32_t RAMMEMA; /**< RAM ECC Address, offset: 0x10 */ + uint8_t RESERVED_0[4]; + __I uint32_t RAMSYSA; /**< RAM System Address, offset: 0x18 */ + __IO uint32_t RAMECCNT; /**< RAM Correctable Error Count, offset: 0x1C */ + __IO uint32_t RAMEID0; /**< RAM Error Injection Data 0, offset: 0x20 */ + __IO uint32_t RAMEID1; /**< RAM Error Injection Data 1, offset: 0x24 */ + __IO uint32_t RAMEIDC; /**< RAM Error Injection Data Control, offset: 0x28 */ + uint8_t RESERVED_1[4]; + __IO uint32_t RAMEIA; /**< RAM Error Injection Base Address, offset: 0x30 */ + __IO uint32_t RAMEIAM; /**< RAM Error Injection Address Mask, offset: 0x34 */ + uint8_t RESERVED_2[8]; + __IO uint32_t RAMMAXA; /**< RAM Maximum-Value Address, offset: 0x40 */ + uint8_t RESERVED_3[60]; + __IO uint32_t RAMCR2; /**< RAM Control 2, offset: 0x80 */ +} OCRAM_CTRL_Type; + +/* ---------------------------------------------------------------------------- + -- OCRAM_CTRL Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup OCRAM_CTRL_Register_Masks OCRAM_CTRL Register Masks + * @{ + */ + +/*! @name RAMCR - RAM Control */ +/*! @{ */ + +#define OCRAM_CTRL_RAMCR_INIT_MASK (0x1U) +#define OCRAM_CTRL_RAMCR_INIT_SHIFT (0U) +/*! INIT - Initialization Request + * 0b0..Not requested + * 0b1..Requested + */ +#define OCRAM_CTRL_RAMCR_INIT(x) (((uint32_t)(((uint32_t)(x)) << OCRAM_CTRL_RAMCR_INIT_SHIFT)) & OCRAM_CTRL_RAMCR_INIT_MASK) + +#define OCRAM_CTRL_RAMCR_IWS_MASK (0x6U) +#define OCRAM_CTRL_RAMCR_IWS_SHIFT (1U) +/*! IWS - Initialization Wait States + * 0b00..Zero + * 0b01..One + * 0b10..Two + * 0b11..Three + */ +#define OCRAM_CTRL_RAMCR_IWS(x) (((uint32_t)(((uint32_t)(x)) << OCRAM_CTRL_RAMCR_IWS_SHIFT)) & OCRAM_CTRL_RAMCR_IWS_MASK) + +#define OCRAM_CTRL_RAMCR_INIT_SYSA_MASK (0x100U) +#define OCRAM_CTRL_RAMCR_INIT_SYSA_SHIFT (8U) +/*! INIT_SYSA - Initialize With System Address + * 0b0..Local + * 0b1..System + */ +#define OCRAM_CTRL_RAMCR_INIT_SYSA(x) (((uint32_t)(((uint32_t)(x)) << OCRAM_CTRL_RAMCR_INIT_SYSA_SHIFT)) & OCRAM_CTRL_RAMCR_INIT_SYSA_MASK) +/*! @} */ + +/*! @name RAMIAS - RAM Initialization Address Start */ +/*! @{ */ + +#define OCRAM_CTRL_RAMIAS_IAS_MASK (0xFFFFFFFFU) +#define OCRAM_CTRL_RAMIAS_IAS_SHIFT (0U) +/*! IAS - Initialization Address Start */ +#define OCRAM_CTRL_RAMIAS_IAS(x) (((uint32_t)(((uint32_t)(x)) << OCRAM_CTRL_RAMIAS_IAS_SHIFT)) & OCRAM_CTRL_RAMIAS_IAS_MASK) +/*! @} */ + +/*! @name RAMIAE - RAM Initialization Address End */ +/*! @{ */ + +#define OCRAM_CTRL_RAMIAE_IAE_MASK (0xFFFFFFFFU) +#define OCRAM_CTRL_RAMIAE_IAE_SHIFT (0U) +/*! IAE - Initialization Address End */ +#define OCRAM_CTRL_RAMIAE_IAE(x) (((uint32_t)(((uint32_t)(x)) << OCRAM_CTRL_RAMIAE_IAE_SHIFT)) & OCRAM_CTRL_RAMIAE_IAE_MASK) +/*! @} */ + +/*! @name RAMSR - RAM Status */ +/*! @{ */ + +#define OCRAM_CTRL_RAMSR_IDONE_MASK (0x1U) +#define OCRAM_CTRL_RAMSR_IDONE_SHIFT (0U) +/*! IDONE - Initialization Done + * 0b0..An initialization was not requested, is in progress, or did not complete + * 0b1..An initialization completed successfully + */ +#define OCRAM_CTRL_RAMSR_IDONE(x) (((uint32_t)(((uint32_t)(x)) << OCRAM_CTRL_RAMSR_IDONE_SHIFT)) & OCRAM_CTRL_RAMSR_IDONE_MASK) + +#define OCRAM_CTRL_RAMSR_BUSERR_MASK (0x2U) +#define OCRAM_CTRL_RAMSR_BUSERR_SHIFT (1U) +/*! BUSERR - Bus Error + * 0b0..No error occurred since the last time this field was cleared + * 0b1..An error occurred + */ +#define OCRAM_CTRL_RAMSR_BUSERR(x) (((uint32_t)(((uint32_t)(x)) << OCRAM_CTRL_RAMSR_BUSERR_SHIFT)) & OCRAM_CTRL_RAMSR_BUSERR_MASK) + +#define OCRAM_CTRL_RAMSR_IPEND_MASK (0x4U) +#define OCRAM_CTRL_RAMSR_IPEND_SHIFT (2U) +/*! IPEND - Initialization Pending + * 0b0..Not in progress + * 0b1..In progress + */ +#define OCRAM_CTRL_RAMSR_IPEND(x) (((uint32_t)(((uint32_t)(x)) << OCRAM_CTRL_RAMSR_IPEND_SHIFT)) & OCRAM_CTRL_RAMSR_IPEND_MASK) + +#define OCRAM_CTRL_RAMSR_AVALID_MASK (0x8U) +#define OCRAM_CTRL_RAMSR_AVALID_SHIFT (3U) +/*! AVALID - Addresses Valid + * 0b0..Addresses do not correspond to an event + * 0b1..Addresses correspond to an event + */ +#define OCRAM_CTRL_RAMSR_AVALID(x) (((uint32_t)(((uint32_t)(x)) << OCRAM_CTRL_RAMSR_AVALID_SHIFT)) & OCRAM_CTRL_RAMSR_AVALID_MASK) + +#define OCRAM_CTRL_RAMSR_AERR_MASK (0x20U) +#define OCRAM_CTRL_RAMSR_AERR_SHIFT (5U) +/*! AERR - ECC Address Error + * 0b0..No error occurred + * 0b1..An error occurred + */ +#define OCRAM_CTRL_RAMSR_AERR(x) (((uint32_t)(((uint32_t)(x)) << OCRAM_CTRL_RAMSR_AERR_SHIFT)) & OCRAM_CTRL_RAMSR_AERR_MASK) + +#define OCRAM_CTRL_RAMSR_MLTERR_MASK (0x40U) +#define OCRAM_CTRL_RAMSR_MLTERR_SHIFT (6U) +/*! MLTERR - ECC Multi-Bit Error + * 0b0..No error occurred + * 0b1..An error occurred + */ +#define OCRAM_CTRL_RAMSR_MLTERR(x) (((uint32_t)(((uint32_t)(x)) << OCRAM_CTRL_RAMSR_MLTERR_SHIFT)) & OCRAM_CTRL_RAMSR_MLTERR_MASK) + +#define OCRAM_CTRL_RAMSR_SGLERR_MASK (0x80U) +#define OCRAM_CTRL_RAMSR_SGLERR_SHIFT (7U) +/*! SGLERR - ECC Single-Bit Error + * 0b0..No error occurred + * 0b1..An error occurred + */ +#define OCRAM_CTRL_RAMSR_SGLERR(x) (((uint32_t)(((uint32_t)(x)) << OCRAM_CTRL_RAMSR_SGLERR_SHIFT)) & OCRAM_CTRL_RAMSR_SGLERR_MASK) + +#define OCRAM_CTRL_RAMSR_SYND_MASK (0xFF00U) +#define OCRAM_CTRL_RAMSR_SYND_SHIFT (8U) +/*! SYND - ECC Syndrome Value */ +#define OCRAM_CTRL_RAMSR_SYND(x) (((uint32_t)(((uint32_t)(x)) << OCRAM_CTRL_RAMSR_SYND_SHIFT)) & OCRAM_CTRL_RAMSR_SYND_MASK) + +#define OCRAM_CTRL_RAMSR_EINFO_MASK (0xFF0000U) +#define OCRAM_CTRL_RAMSR_EINFO_SHIFT (16U) +/*! EINFO - Event Information */ +#define OCRAM_CTRL_RAMSR_EINFO(x) (((uint32_t)(((uint32_t)(x)) << OCRAM_CTRL_RAMSR_EINFO_SHIFT)) & OCRAM_CTRL_RAMSR_EINFO_MASK) +/*! @} */ + +/*! @name RAMMEMA - RAM ECC Address */ +/*! @{ */ + +#define OCRAM_CTRL_RAMMEMA_MEMA_MASK (0x1FFFFU) +#define OCRAM_CTRL_RAMMEMA_MEMA_SHIFT (0U) +/*! MEMA - RAM Bank Address */ +#define OCRAM_CTRL_RAMMEMA_MEMA(x) (((uint32_t)(((uint32_t)(x)) << OCRAM_CTRL_RAMMEMA_MEMA_SHIFT)) & OCRAM_CTRL_RAMMEMA_MEMA_MASK) + +#define OCRAM_CTRL_RAMMEMA_BANK_MASK (0x1F00000U) +#define OCRAM_CTRL_RAMMEMA_BANK_SHIFT (20U) +/*! BANK - RAM Bank ID */ +#define OCRAM_CTRL_RAMMEMA_BANK(x) (((uint32_t)(((uint32_t)(x)) << OCRAM_CTRL_RAMMEMA_BANK_SHIFT)) & OCRAM_CTRL_RAMMEMA_BANK_MASK) +/*! @} */ + +/*! @name RAMSYSA - RAM System Address */ +/*! @{ */ + +#define OCRAM_CTRL_RAMSYSA_SYSA_MASK (0xFFFFFFFFU) +#define OCRAM_CTRL_RAMSYSA_SYSA_SHIFT (0U) +/*! SYSA - System Address */ +#define OCRAM_CTRL_RAMSYSA_SYSA(x) (((uint32_t)(((uint32_t)(x)) << OCRAM_CTRL_RAMSYSA_SYSA_SHIFT)) & OCRAM_CTRL_RAMSYSA_SYSA_MASK) +/*! @} */ + +/*! @name RAMECCNT - RAM Correctable Error Count */ +/*! @{ */ + +#define OCRAM_CTRL_RAMECCNT_ECCNT_MASK (0xFFU) +#define OCRAM_CTRL_RAMECCNT_ECCNT_SHIFT (0U) +/*! ECCNT - ECC Correctable Error Count */ +#define OCRAM_CTRL_RAMECCNT_ECCNT(x) (((uint32_t)(((uint32_t)(x)) << OCRAM_CTRL_RAMECCNT_ECCNT_SHIFT)) & OCRAM_CTRL_RAMECCNT_ECCNT_MASK) +/*! @} */ + +/*! @name RAMEID0 - RAM Error Injection Data 0 */ +/*! @{ */ + +#define OCRAM_CTRL_RAMEID0_EID_W0_MASK (0xFFFFFFFFU) +#define OCRAM_CTRL_RAMEID0_EID_W0_SHIFT (0U) +/*! EID_W0 - Error Injection Data Word 0 */ +#define OCRAM_CTRL_RAMEID0_EID_W0(x) (((uint32_t)(((uint32_t)(x)) << OCRAM_CTRL_RAMEID0_EID_W0_SHIFT)) & OCRAM_CTRL_RAMEID0_EID_W0_MASK) +/*! @} */ + +/*! @name RAMEID1 - RAM Error Injection Data 1 */ +/*! @{ */ + +#define OCRAM_CTRL_RAMEID1_EID_W1_MASK (0xFFFFFFFFU) +#define OCRAM_CTRL_RAMEID1_EID_W1_SHIFT (0U) +/*! EID_W1 - Error Injection Data Word 1 */ +#define OCRAM_CTRL_RAMEID1_EID_W1(x) (((uint32_t)(((uint32_t)(x)) << OCRAM_CTRL_RAMEID1_EID_W1_SHIFT)) & OCRAM_CTRL_RAMEID1_EID_W1_MASK) +/*! @} */ + +/*! @name RAMEIDC - RAM Error Injection Data Control */ +/*! @{ */ + +#define OCRAM_CTRL_RAMEIDC_EID_CKB_MASK (0xFFU) +#define OCRAM_CTRL_RAMEIDC_EID_CKB_SHIFT (0U) +/*! EID_CKB - Error Injection Data Checkbits */ +#define OCRAM_CTRL_RAMEIDC_EID_CKB(x) (((uint32_t)(((uint32_t)(x)) << OCRAM_CTRL_RAMEIDC_EID_CKB_SHIFT)) & OCRAM_CTRL_RAMEIDC_EID_CKB_MASK) + +#define OCRAM_CTRL_RAMEIDC_EIP_EN_MASK (0x1000000U) +#define OCRAM_CTRL_RAMEIDC_EIP_EN_SHIFT (24U) +/*! EIP_EN - Error Injection Into Pipeline Enable + * 0b0..No error injected + * 0b1..Error injected + */ +#define OCRAM_CTRL_RAMEIDC_EIP_EN(x) (((uint32_t)(((uint32_t)(x)) << OCRAM_CTRL_RAMEIDC_EIP_EN_SHIFT)) & OCRAM_CTRL_RAMEIDC_EIP_EN_MASK) + +#define OCRAM_CTRL_RAMEIDC_EIA_EN_MASK (0x40000000U) +#define OCRAM_CTRL_RAMEIDC_EIA_EN_SHIFT (30U) +/*! EIA_EN - Error Injection Address Enable + * 0b0..Ignore RAMEIA and RAMEIAM + * 0b1..Enable RAMEIA and RAMEIAM + */ +#define OCRAM_CTRL_RAMEIDC_EIA_EN(x) (((uint32_t)(((uint32_t)(x)) << OCRAM_CTRL_RAMEIDC_EIA_EN_SHIFT)) & OCRAM_CTRL_RAMEIDC_EIA_EN_MASK) + +#define OCRAM_CTRL_RAMEIDC_EID_EN_MASK (0x80000000U) +#define OCRAM_CTRL_RAMEIDC_EID_EN_SHIFT (31U) +/*! EID_EN - Error Injection Data Enable + * 0b0..No injection + * 0b1..Local injection + */ +#define OCRAM_CTRL_RAMEIDC_EID_EN(x) (((uint32_t)(((uint32_t)(x)) << OCRAM_CTRL_RAMEIDC_EID_EN_SHIFT)) & OCRAM_CTRL_RAMEIDC_EID_EN_MASK) +/*! @} */ + +/*! @name RAMEIA - RAM Error Injection Base Address */ +/*! @{ */ + +#define OCRAM_CTRL_RAMEIA_EIA_MASK (0xFFFFFFFFU) +#define OCRAM_CTRL_RAMEIA_EIA_SHIFT (0U) +/*! EIA - Error Injection Base Address */ +#define OCRAM_CTRL_RAMEIA_EIA(x) (((uint32_t)(((uint32_t)(x)) << OCRAM_CTRL_RAMEIA_EIA_SHIFT)) & OCRAM_CTRL_RAMEIA_EIA_MASK) +/*! @} */ + +/*! @name RAMEIAM - RAM Error Injection Address Mask */ +/*! @{ */ + +#define OCRAM_CTRL_RAMEIAM_EIAM_MASK (0xFFFFFFFFU) +#define OCRAM_CTRL_RAMEIAM_EIAM_SHIFT (0U) +/*! EIAM - Error Injection Address Mask */ +#define OCRAM_CTRL_RAMEIAM_EIAM(x) (((uint32_t)(((uint32_t)(x)) << OCRAM_CTRL_RAMEIAM_EIAM_SHIFT)) & OCRAM_CTRL_RAMEIAM_EIAM_MASK) +/*! @} */ + +/*! @name RAMMAXA - RAM Maximum-Value Address */ +/*! @{ */ + +#define OCRAM_CTRL_RAMMAXA_MAXA_MASK (0xFFFFFFFFU) +#define OCRAM_CTRL_RAMMAXA_MAXA_SHIFT (0U) +/*! MAXA - Maximum Address */ +#define OCRAM_CTRL_RAMMAXA_MAXA(x) (((uint32_t)(((uint32_t)(x)) << OCRAM_CTRL_RAMMAXA_MAXA_SHIFT)) & OCRAM_CTRL_RAMMAXA_MAXA_MASK) +/*! @} */ + +/*! @name RAMCR2 - RAM Control 2 */ +/*! @{ */ + +#define OCRAM_CTRL_RAMCR2_DEM_MASK (0x8U) +#define OCRAM_CTRL_RAMCR2_DEM_SHIFT (3U) +/*! DEM - Disable Exclusive Monitor + * 0b0..Enabled + * 0b1..Disabled + */ +#define OCRAM_CTRL_RAMCR2_DEM(x) (((uint32_t)(((uint32_t)(x)) << OCRAM_CTRL_RAMCR2_DEM_SHIFT)) & OCRAM_CTRL_RAMCR2_DEM_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group OCRAM_CTRL_Register_Masks */ + + +/* OCRAM_CTRL - Peripheral instance base addresses */ +/** Peripheral OCRAM_CTRL1 base address */ +#define OCRAM_CTRL1_BASE (0x490A0000u) +/** Peripheral OCRAM_CTRL1 base pointer */ +#define OCRAM_CTRL1 ((OCRAM_CTRL_Type *)OCRAM_CTRL1_BASE) +/** Array initializer of OCRAM_CTRL peripheral base addresses */ +#define OCRAM_CTRL_BASE_ADDRS { OCRAM_CTRL1_BASE } +/** Array initializer of OCRAM_CTRL peripheral base pointers */ +#define OCRAM_CTRL_BASE_PTRS { OCRAM_CTRL1 } + +/*! + * @} + */ /* end of group OCRAM_CTRL_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- PDM Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PDM_Peripheral_Access_Layer PDM Peripheral Access Layer + * @{ + */ + +/** PDM - Register Layout Typedef */ +typedef struct { + __IO uint32_t CTRL_1; /**< MICFIL Control 1, offset: 0x0 */ + __IO uint32_t CTRL_2; /**< MICFIL Control 2, offset: 0x4 */ + __IO uint32_t STAT; /**< MICFIL Status, offset: 0x8 */ + uint8_t RESERVED_0[4]; + __IO uint32_t FIFO_CTRL; /**< MICFIL FIFO Control, offset: 0x10 */ + __IO uint32_t FIFO_STAT; /**< MICFIL FIFO Status, offset: 0x14 */ + uint8_t RESERVED_1[12]; + __I uint32_t DATACH[8]; /**< MICFIL Output Result, array offset: 0x24, array step: 0x4 */ + uint8_t RESERVED_2[32]; + __IO uint32_t DC_CTRL; /**< MICFIL DC Remover Control, offset: 0x64 */ + __IO uint32_t DC_OUT_CTRL; /**< MICFIL Output DC Remover Control, offset: 0x68 */ + uint8_t RESERVED_3[8]; + __IO uint32_t RANGE_CTRL; /**< MICFIL Range Control, offset: 0x74 */ + uint8_t RESERVED_4[4]; + __IO uint32_t RANGE_STAT; /**< MICFIL Range Status, offset: 0x7C */ + __IO uint32_t FSYNC_CTRL; /**< Frame Synchronization Control, offset: 0x80 */ + __I uint32_t VERID; /**< Version ID, offset: 0x84 */ + __I uint32_t PARAM; /**< Parameter, offset: 0x88 */ + uint8_t RESERVED_5[4]; + __IO uint32_t VAD0_CTRL_1; /**< Voice Activity Detector 0 Control, offset: 0x90 */ + __IO uint32_t VAD0_CTRL_2; /**< Voice Activity Detector 0 Control, offset: 0x94 */ + __IO uint32_t VAD0_STAT; /**< Voice Activity Detector 0 Status, offset: 0x98 */ + __IO uint32_t VAD0_SCONFIG; /**< Voice Activity Detector 0 Signal Configuration, offset: 0x9C */ + __IO uint32_t VAD0_NCONFIG; /**< Voice Activity Detector 0 Noise Configuration, offset: 0xA0 */ + __I uint32_t VAD0_NDATA; /**< Voice Activity Detector 0 Noise Data, offset: 0xA4 */ + __IO uint32_t VAD0_ZCD; /**< Voice Activity Detector 0 Zero-Crossing Detector, offset: 0xA8 */ +} PDM_Type; + +/* ---------------------------------------------------------------------------- + -- PDM Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PDM_Register_Masks PDM Register Masks + * @{ + */ + +/*! @name CTRL_1 - MICFIL Control 1 */ +/*! @{ */ + +#define PDM_CTRL_1_CH0EN_MASK (0x1U) +#define PDM_CTRL_1_CH0EN_SHIFT (0U) +/*! CH0EN - Channel 0 Enable */ +#define PDM_CTRL_1_CH0EN(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_CH0EN_SHIFT)) & PDM_CTRL_1_CH0EN_MASK) + +#define PDM_CTRL_1_CH1EN_MASK (0x2U) +#define PDM_CTRL_1_CH1EN_SHIFT (1U) +/*! CH1EN - Channel 1 Enable */ +#define PDM_CTRL_1_CH1EN(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_CH1EN_SHIFT)) & PDM_CTRL_1_CH1EN_MASK) + +#define PDM_CTRL_1_CH2EN_MASK (0x4U) +#define PDM_CTRL_1_CH2EN_SHIFT (2U) +/*! CH2EN - Channel 2 Enable */ +#define PDM_CTRL_1_CH2EN(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_CH2EN_SHIFT)) & PDM_CTRL_1_CH2EN_MASK) + +#define PDM_CTRL_1_CH3EN_MASK (0x8U) +#define PDM_CTRL_1_CH3EN_SHIFT (3U) +/*! CH3EN - Channel 3 Enable */ +#define PDM_CTRL_1_CH3EN(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_CH3EN_SHIFT)) & PDM_CTRL_1_CH3EN_MASK) + +#define PDM_CTRL_1_CH4EN_MASK (0x10U) +#define PDM_CTRL_1_CH4EN_SHIFT (4U) +/*! CH4EN - Channel 4 Enable */ +#define PDM_CTRL_1_CH4EN(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_CH4EN_SHIFT)) & PDM_CTRL_1_CH4EN_MASK) + +#define PDM_CTRL_1_CH5EN_MASK (0x20U) +#define PDM_CTRL_1_CH5EN_SHIFT (5U) +/*! CH5EN - Channel 5 Enable */ +#define PDM_CTRL_1_CH5EN(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_CH5EN_SHIFT)) & PDM_CTRL_1_CH5EN_MASK) + +#define PDM_CTRL_1_CH6EN_MASK (0x40U) +#define PDM_CTRL_1_CH6EN_SHIFT (6U) +/*! CH6EN - Channel 6 Enable */ +#define PDM_CTRL_1_CH6EN(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_CH6EN_SHIFT)) & PDM_CTRL_1_CH6EN_MASK) + +#define PDM_CTRL_1_CH7EN_MASK (0x80U) +#define PDM_CTRL_1_CH7EN_SHIFT (7U) +/*! CH7EN - Channel 7 Enable */ +#define PDM_CTRL_1_CH7EN(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_CH7EN_SHIFT)) & PDM_CTRL_1_CH7EN_MASK) + +#define PDM_CTRL_1_FSYNCEN_MASK (0x10000U) +#define PDM_CTRL_1_FSYNCEN_SHIFT (16U) +/*! FSYNCEN - Frame Synchronization Enable + * 0b0..Disables + * 0b1..Enables + */ +#define PDM_CTRL_1_FSYNCEN(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_FSYNCEN_SHIFT)) & PDM_CTRL_1_FSYNCEN_MASK) + +#define PDM_CTRL_1_DECFILS_MASK (0x100000U) +#define PDM_CTRL_1_DECFILS_SHIFT (20U) +/*! DECFILS - Decimation Filter Enable in Stop + * 0b0..Stops decimation filter + * 0b1..Keeps decimation filter running + */ +#define PDM_CTRL_1_DECFILS(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_DECFILS_SHIFT)) & PDM_CTRL_1_DECFILS_MASK) + +#define PDM_CTRL_1_ERREN_MASK (0x800000U) +#define PDM_CTRL_1_ERREN_SHIFT (23U) +/*! ERREN - Error Interruption Enable + * 0b0..Disables + * 0b1..Enables + */ +#define PDM_CTRL_1_ERREN(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_ERREN_SHIFT)) & PDM_CTRL_1_ERREN_MASK) + +#define PDM_CTRL_1_DISEL_MASK (0x3000000U) +#define PDM_CTRL_1_DISEL_SHIFT (24U) +/*! DISEL - DMA Interrupt Selection + * 0b00..Disables DMA and interrupt requests + * 0b01..Enables DMA requests + * 0b10..Enables interrupt requests + * 0b11..Reserved + */ +#define PDM_CTRL_1_DISEL(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_DISEL_SHIFT)) & PDM_CTRL_1_DISEL_MASK) + +#define PDM_CTRL_1_DBGE_MASK (0x4000000U) +#define PDM_CTRL_1_DBGE_SHIFT (26U) +/*! DBGE - Module Enable in Debug + * 0b0..Disables after completing the current frame + * 0b1..Enables operation + */ +#define PDM_CTRL_1_DBGE(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_DBGE_SHIFT)) & PDM_CTRL_1_DBGE_MASK) + +#define PDM_CTRL_1_SRES_MASK (0x8000000U) +#define PDM_CTRL_1_SRES_SHIFT (27U) +/*! SRES - Software Reset + * 0b0..No action + * 0b1..Software reset + */ +#define PDM_CTRL_1_SRES(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_SRES_SHIFT)) & PDM_CTRL_1_SRES_MASK) + +#define PDM_CTRL_1_DBG_MASK (0x10000000U) +#define PDM_CTRL_1_DBG_SHIFT (28U) +/*! DBG - Debug Mode + * 0b0..Normal + * 0b1..Debug + */ +#define PDM_CTRL_1_DBG(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_DBG_SHIFT)) & PDM_CTRL_1_DBG_MASK) + +#define PDM_CTRL_1_PDMIEN_MASK (0x20000000U) +#define PDM_CTRL_1_PDMIEN_SHIFT (29U) +/*! PDMIEN - MICFIL Enable + * 0b0..Stops MICFIL operation + * 0b1..Starts MICFIL operation + */ +#define PDM_CTRL_1_PDMIEN(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_PDMIEN_SHIFT)) & PDM_CTRL_1_PDMIEN_MASK) + +#define PDM_CTRL_1_DOZEN_MASK (0x40000000U) +#define PDM_CTRL_1_DOZEN_SHIFT (30U) +/*! DOZEN - Stop Enable + * 0b0..Disables + * 0b1..Enables + */ +#define PDM_CTRL_1_DOZEN(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_DOZEN_SHIFT)) & PDM_CTRL_1_DOZEN_MASK) + +#define PDM_CTRL_1_MDIS_MASK (0x80000000U) +#define PDM_CTRL_1_MDIS_SHIFT (31U) +/*! MDIS - Module Disable + * 0b0..Normal mode + * 0b1..DLL mode + */ +#define PDM_CTRL_1_MDIS(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_MDIS_SHIFT)) & PDM_CTRL_1_MDIS_MASK) +/*! @} */ + +/*! @name CTRL_2 - MICFIL Control 2 */ +/*! @{ */ + +#define PDM_CTRL_2_CLKDIV_MASK (0xFFU) +#define PDM_CTRL_2_CLKDIV_SHIFT (0U) +/*! CLKDIV - Clock Divider + * 0b00000000..Internal clock divider value = 0 + * 0b00000001..Internal clock divider value = 1 + * 0b00000010-0b11111110..... + * 0b11111111..Internal clock divider value = 255 + */ +#define PDM_CTRL_2_CLKDIV(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_2_CLKDIV_SHIFT)) & PDM_CTRL_2_CLKDIV_MASK) + +#define PDM_CTRL_2_CICOSR_MASK (0xF0000U) +#define PDM_CTRL_2_CICOSR_SHIFT (16U) +/*! CICOSR - CIC Decimation Rate + * 0b0000..CIC oversampling rate = 0 + * 0b0001..CIC oversampling rate = 1 + * 0b0010-0b1110..... + * 0b1111..CIC oversampling rate = 15 + */ +#define PDM_CTRL_2_CICOSR(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_2_CICOSR_SHIFT)) & PDM_CTRL_2_CICOSR_MASK) + +#define PDM_CTRL_2_QSEL_MASK (0xE000000U) +#define PDM_CTRL_2_QSEL_SHIFT (25U) +/*! QSEL - Quality Mode + * 0b000..Medium-Quality mode + * 0b001..High-Quality mode + * 0b100..Very-Low-Quality 2 mode + * 0b101..Very-Low-Quality 1 mode + * 0b110..Very-Low-Quality 0 mode + * 0b111..Low-Quality mode + */ +#define PDM_CTRL_2_QSEL(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_2_QSEL_SHIFT)) & PDM_CTRL_2_QSEL_MASK) +/*! @} */ + +/*! @name STAT - MICFIL Status */ +/*! @{ */ + +#define PDM_STAT_CH0F_MASK (0x1U) +#define PDM_STAT_CH0F_SHIFT (0U) +/*! CH0F - Channel 0 Output Data Flag + * 0b0..Not surpassed + * 0b1..Surpassed + */ +#define PDM_STAT_CH0F(x) (((uint32_t)(((uint32_t)(x)) << PDM_STAT_CH0F_SHIFT)) & PDM_STAT_CH0F_MASK) + +#define PDM_STAT_CH1F_MASK (0x2U) +#define PDM_STAT_CH1F_SHIFT (1U) +/*! CH1F - Channel 1 Output Data Flag + * 0b0..Not surpassed + * 0b1..Surpassed + */ +#define PDM_STAT_CH1F(x) (((uint32_t)(((uint32_t)(x)) << PDM_STAT_CH1F_SHIFT)) & PDM_STAT_CH1F_MASK) + +#define PDM_STAT_CH2F_MASK (0x4U) +#define PDM_STAT_CH2F_SHIFT (2U) +/*! CH2F - Channel 2 Output Data Flag + * 0b0..Not surpassed + * 0b1..Surpassed + */ +#define PDM_STAT_CH2F(x) (((uint32_t)(((uint32_t)(x)) << PDM_STAT_CH2F_SHIFT)) & PDM_STAT_CH2F_MASK) + +#define PDM_STAT_CH3F_MASK (0x8U) +#define PDM_STAT_CH3F_SHIFT (3U) +/*! CH3F - Channel 3 Output Data Flag + * 0b0..Not surpassed + * 0b1..Surpassed + */ +#define PDM_STAT_CH3F(x) (((uint32_t)(((uint32_t)(x)) << PDM_STAT_CH3F_SHIFT)) & PDM_STAT_CH3F_MASK) + +#define PDM_STAT_CH4F_MASK (0x10U) +#define PDM_STAT_CH4F_SHIFT (4U) +/*! CH4F - Channel 4 Output Data Flag + * 0b0..Not surpassed + * 0b1..Surpassed + */ +#define PDM_STAT_CH4F(x) (((uint32_t)(((uint32_t)(x)) << PDM_STAT_CH4F_SHIFT)) & PDM_STAT_CH4F_MASK) + +#define PDM_STAT_CH5F_MASK (0x20U) +#define PDM_STAT_CH5F_SHIFT (5U) +/*! CH5F - Channel 5 Output Data Flag + * 0b0..Not surpassed + * 0b1..Surpassed + */ +#define PDM_STAT_CH5F(x) (((uint32_t)(((uint32_t)(x)) << PDM_STAT_CH5F_SHIFT)) & PDM_STAT_CH5F_MASK) + +#define PDM_STAT_CH6F_MASK (0x40U) +#define PDM_STAT_CH6F_SHIFT (6U) +/*! CH6F - Channel 6 Output Data Flag + * 0b0..Not surpassed + * 0b1..Surpassed + */ +#define PDM_STAT_CH6F(x) (((uint32_t)(((uint32_t)(x)) << PDM_STAT_CH6F_SHIFT)) & PDM_STAT_CH6F_MASK) + +#define PDM_STAT_CH7F_MASK (0x80U) +#define PDM_STAT_CH7F_SHIFT (7U) +/*! CH7F - Channel 7 Output Data Flag + * 0b0..Not surpassed + * 0b1..Surpassed + */ +#define PDM_STAT_CH7F(x) (((uint32_t)(((uint32_t)(x)) << PDM_STAT_CH7F_SHIFT)) & PDM_STAT_CH7F_MASK) + +#define PDM_STAT_LOWFREQF_MASK (0x20000000U) +#define PDM_STAT_LOWFREQF_SHIFT (29U) +/*! LOWFREQF - Low Frequency Flag + * 0b0..CLKDIV value is OK + * 0b1..CLKDIV value is too low + */ +#define PDM_STAT_LOWFREQF(x) (((uint32_t)(((uint32_t)(x)) << PDM_STAT_LOWFREQF_SHIFT)) & PDM_STAT_LOWFREQF_MASK) + +#define PDM_STAT_FIR_RDY_MASK (0x40000000U) +#define PDM_STAT_FIR_RDY_SHIFT (30U) +/*! FIR_RDY - Filter Data Ready + * 0b0..Not reliable + * 0b1..Reliable + */ +#define PDM_STAT_FIR_RDY(x) (((uint32_t)(((uint32_t)(x)) << PDM_STAT_FIR_RDY_SHIFT)) & PDM_STAT_FIR_RDY_MASK) + +#define PDM_STAT_BSY_FIL_MASK (0x80000000U) +#define PDM_STAT_BSY_FIL_SHIFT (31U) +/*! BSY_FIL - Busy Flag + * 0b0..MICFIL is stopped + * 0b1..MICFIL is running + */ +#define PDM_STAT_BSY_FIL(x) (((uint32_t)(((uint32_t)(x)) << PDM_STAT_BSY_FIL_SHIFT)) & PDM_STAT_BSY_FIL_MASK) +/*! @} */ + +/*! @name FIFO_CTRL - MICFIL FIFO Control */ +/*! @{ */ + +#define PDM_FIFO_CTRL_FIFOWMK_MASK (0x1FU) +#define PDM_FIFO_CTRL_FIFOWMK_SHIFT (0U) +/*! FIFOWMK - FIFO Watermark Control */ +#define PDM_FIFO_CTRL_FIFOWMK(x) (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_CTRL_FIFOWMK_SHIFT)) & PDM_FIFO_CTRL_FIFOWMK_MASK) +/*! @} */ + +/*! @name FIFO_STAT - MICFIL FIFO Status */ +/*! @{ */ + +#define PDM_FIFO_STAT_FIFOOVF0_MASK (0x1U) +#define PDM_FIFO_STAT_FIFOOVF0_SHIFT (0U) +/*! FIFOOVF0 - FIFO Overflow Exception Flag for Channel 0 + * 0b0..No exception by FIFO overflow + * 0b1..Exception by FIFO overflow + */ +#define PDM_FIFO_STAT_FIFOOVF0(x) (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOOVF0_SHIFT)) & PDM_FIFO_STAT_FIFOOVF0_MASK) + +#define PDM_FIFO_STAT_FIFOOVF1_MASK (0x2U) +#define PDM_FIFO_STAT_FIFOOVF1_SHIFT (1U) +/*! FIFOOVF1 - FIFO Overflow Exception Flag for Channel 1 + * 0b0..No exception by FIFO overflow + * 0b1..Exception by FIFO overflow + */ +#define PDM_FIFO_STAT_FIFOOVF1(x) (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOOVF1_SHIFT)) & PDM_FIFO_STAT_FIFOOVF1_MASK) + +#define PDM_FIFO_STAT_FIFOOVF2_MASK (0x4U) +#define PDM_FIFO_STAT_FIFOOVF2_SHIFT (2U) +/*! FIFOOVF2 - FIFO Overflow Exception Flag for Channel 2 + * 0b0..No exception by FIFO overflow + * 0b1..Exception by FIFO overflow + */ +#define PDM_FIFO_STAT_FIFOOVF2(x) (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOOVF2_SHIFT)) & PDM_FIFO_STAT_FIFOOVF2_MASK) + +#define PDM_FIFO_STAT_FIFOOVF3_MASK (0x8U) +#define PDM_FIFO_STAT_FIFOOVF3_SHIFT (3U) +/*! FIFOOVF3 - FIFO Overflow Exception Flag for Channel 3 + * 0b0..No exception by FIFO overflow + * 0b1..Exception by FIFO overflow + */ +#define PDM_FIFO_STAT_FIFOOVF3(x) (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOOVF3_SHIFT)) & PDM_FIFO_STAT_FIFOOVF3_MASK) + +#define PDM_FIFO_STAT_FIFOOVF4_MASK (0x10U) +#define PDM_FIFO_STAT_FIFOOVF4_SHIFT (4U) +/*! FIFOOVF4 - FIFO Overflow Exception Flag for Channel 4 + * 0b0..No exception by FIFO overflow + * 0b1..Exception by FIFO overflow + */ +#define PDM_FIFO_STAT_FIFOOVF4(x) (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOOVF4_SHIFT)) & PDM_FIFO_STAT_FIFOOVF4_MASK) + +#define PDM_FIFO_STAT_FIFOOVF5_MASK (0x20U) +#define PDM_FIFO_STAT_FIFOOVF5_SHIFT (5U) +/*! FIFOOVF5 - FIFO Overflow Exception Flag for Channel 5 + * 0b0..No exception by FIFO overflow + * 0b1..Exception by FIFO overflow + */ +#define PDM_FIFO_STAT_FIFOOVF5(x) (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOOVF5_SHIFT)) & PDM_FIFO_STAT_FIFOOVF5_MASK) + +#define PDM_FIFO_STAT_FIFOOVF6_MASK (0x40U) +#define PDM_FIFO_STAT_FIFOOVF6_SHIFT (6U) +/*! FIFOOVF6 - FIFO Overflow Exception Flag for Channel 6 + * 0b0..No exception by FIFO overflow + * 0b1..Exception by FIFO overflow + */ +#define PDM_FIFO_STAT_FIFOOVF6(x) (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOOVF6_SHIFT)) & PDM_FIFO_STAT_FIFOOVF6_MASK) + +#define PDM_FIFO_STAT_FIFOOVF7_MASK (0x80U) +#define PDM_FIFO_STAT_FIFOOVF7_SHIFT (7U) +/*! FIFOOVF7 - FIFO Overflow Exception Flag for Channel 7 + * 0b0..No exception by FIFO overflow + * 0b1..Exception by FIFO overflow + */ +#define PDM_FIFO_STAT_FIFOOVF7(x) (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOOVF7_SHIFT)) & PDM_FIFO_STAT_FIFOOVF7_MASK) + +#define PDM_FIFO_STAT_FIFOUND0_MASK (0x100U) +#define PDM_FIFO_STAT_FIFOUND0_SHIFT (8U) +/*! FIFOUND0 - FIFO Underflow Exception Flag for Channel 0 + * 0b0..No exception by FIFO underflow + * 0b1..Exception by FIFO underflow + */ +#define PDM_FIFO_STAT_FIFOUND0(x) (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOUND0_SHIFT)) & PDM_FIFO_STAT_FIFOUND0_MASK) + +#define PDM_FIFO_STAT_FIFOUND1_MASK (0x200U) +#define PDM_FIFO_STAT_FIFOUND1_SHIFT (9U) +/*! FIFOUND1 - FIFO Underflow Exception Flag for Channel 1 + * 0b0..No exception by FIFO underflow + * 0b1..Exception by FIFO underflow + */ +#define PDM_FIFO_STAT_FIFOUND1(x) (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOUND1_SHIFT)) & PDM_FIFO_STAT_FIFOUND1_MASK) + +#define PDM_FIFO_STAT_FIFOUND2_MASK (0x400U) +#define PDM_FIFO_STAT_FIFOUND2_SHIFT (10U) +/*! FIFOUND2 - FIFO Underflow Exception Flag for Channel 2 + * 0b0..No exception by FIFO underflow + * 0b1..Exception by FIFO underflow + */ +#define PDM_FIFO_STAT_FIFOUND2(x) (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOUND2_SHIFT)) & PDM_FIFO_STAT_FIFOUND2_MASK) + +#define PDM_FIFO_STAT_FIFOUND3_MASK (0x800U) +#define PDM_FIFO_STAT_FIFOUND3_SHIFT (11U) +/*! FIFOUND3 - FIFO Underflow Exception Flag for Channel 3 + * 0b0..No exception by FIFO underflow + * 0b1..Exception by FIFO underflow + */ +#define PDM_FIFO_STAT_FIFOUND3(x) (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOUND3_SHIFT)) & PDM_FIFO_STAT_FIFOUND3_MASK) + +#define PDM_FIFO_STAT_FIFOUND4_MASK (0x1000U) +#define PDM_FIFO_STAT_FIFOUND4_SHIFT (12U) +/*! FIFOUND4 - FIFO Underflow Exception Flag for Channel 4 + * 0b0..No exception by FIFO underflow + * 0b1..Exception by FIFO underflow + */ +#define PDM_FIFO_STAT_FIFOUND4(x) (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOUND4_SHIFT)) & PDM_FIFO_STAT_FIFOUND4_MASK) + +#define PDM_FIFO_STAT_FIFOUND5_MASK (0x2000U) +#define PDM_FIFO_STAT_FIFOUND5_SHIFT (13U) +/*! FIFOUND5 - FIFO Underflow Exception Flag for Channel 5 + * 0b0..No exception by FIFO underflow + * 0b1..Exception by FIFO underflow + */ +#define PDM_FIFO_STAT_FIFOUND5(x) (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOUND5_SHIFT)) & PDM_FIFO_STAT_FIFOUND5_MASK) + +#define PDM_FIFO_STAT_FIFOUND6_MASK (0x4000U) +#define PDM_FIFO_STAT_FIFOUND6_SHIFT (14U) +/*! FIFOUND6 - FIFO Underflow Exception Flag for Channel 6 + * 0b0..No exception by FIFO underflow + * 0b1..Exception by FIFO underflow + */ +#define PDM_FIFO_STAT_FIFOUND6(x) (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOUND6_SHIFT)) & PDM_FIFO_STAT_FIFOUND6_MASK) + +#define PDM_FIFO_STAT_FIFOUND7_MASK (0x8000U) +#define PDM_FIFO_STAT_FIFOUND7_SHIFT (15U) +/*! FIFOUND7 - FIFO Underflow Exception Flag for Channel 7 + * 0b0..No exception by FIFO underflow + * 0b1..Exception by FIFO underflow + */ +#define PDM_FIFO_STAT_FIFOUND7(x) (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOUND7_SHIFT)) & PDM_FIFO_STAT_FIFOUND7_MASK) +/*! @} */ + +/*! @name DATACH - MICFIL Output Result */ +/*! @{ */ + +#define PDM_DATACH_DATA_MASK (0xFFFFFFFFU) +#define PDM_DATACH_DATA_SHIFT (0U) +/*! DATA - Channel n Data */ +#define PDM_DATACH_DATA(x) (((uint32_t)(((uint32_t)(x)) << PDM_DATACH_DATA_SHIFT)) & PDM_DATACH_DATA_MASK) +/*! @} */ + +/* The count of PDM_DATACH */ +#define PDM_DATACH_COUNT (8U) + +/*! @name DC_CTRL - MICFIL DC Remover Control */ +/*! @{ */ + +#define PDM_DC_CTRL_DCCONFIG0_MASK (0x3U) +#define PDM_DC_CTRL_DCCONFIG0_SHIFT (0U) +/*! DCCONFIG0 - Channel 0 DC Remover Configuration + * 0b00..20 Hz (PDM_CLK = 3.072 MHz) + * 0b01..13.3 Hz (PDM_CLK = 3.072 MHz) + * 0b10..40 Hz (PDM_CLK = 3.072 MHz) + * 0b11..DC remover is bypassed + */ +#define PDM_DC_CTRL_DCCONFIG0(x) (((uint32_t)(((uint32_t)(x)) << PDM_DC_CTRL_DCCONFIG0_SHIFT)) & PDM_DC_CTRL_DCCONFIG0_MASK) + +#define PDM_DC_CTRL_DCCONFIG1_MASK (0xCU) +#define PDM_DC_CTRL_DCCONFIG1_SHIFT (2U) +/*! DCCONFIG1 - Channel 1 DC Remover Configuration + * 0b00..20 Hz (PDM_CLK = 3.072 MHz) + * 0b01..13.3 Hz (PDM_CLK = 3.072 MHz) + * 0b10..40 Hz (PDM_CLK = 3.072 MHz) + * 0b11..DC remover is bypassed + */ +#define PDM_DC_CTRL_DCCONFIG1(x) (((uint32_t)(((uint32_t)(x)) << PDM_DC_CTRL_DCCONFIG1_SHIFT)) & PDM_DC_CTRL_DCCONFIG1_MASK) + +#define PDM_DC_CTRL_DCCONFIG2_MASK (0x30U) +#define PDM_DC_CTRL_DCCONFIG2_SHIFT (4U) +/*! DCCONFIG2 - Channel 2 DC Remover Configuration + * 0b00..20 Hz (PDM_CLK = 3.072 MHz) + * 0b01..13.3 Hz (PDM_CLK = 3.072 MHz) + * 0b10..40 Hz (PDM_CLK = 3.072 MHz) + * 0b11..DC remover is bypassed + */ +#define PDM_DC_CTRL_DCCONFIG2(x) (((uint32_t)(((uint32_t)(x)) << PDM_DC_CTRL_DCCONFIG2_SHIFT)) & PDM_DC_CTRL_DCCONFIG2_MASK) + +#define PDM_DC_CTRL_DCCONFIG3_MASK (0xC0U) +#define PDM_DC_CTRL_DCCONFIG3_SHIFT (6U) +/*! DCCONFIG3 - Channel 3 DC Remover Configuration + * 0b00..20 Hz (PDM_CLK = 3.072 MHz) + * 0b01..13.3 Hz (PDM_CLK = 3.072 MHz) + * 0b10..40 Hz (PDM_CLK = 3.072 MHz) + * 0b11..DC remover is bypassed + */ +#define PDM_DC_CTRL_DCCONFIG3(x) (((uint32_t)(((uint32_t)(x)) << PDM_DC_CTRL_DCCONFIG3_SHIFT)) & PDM_DC_CTRL_DCCONFIG3_MASK) + +#define PDM_DC_CTRL_DCCONFIG4_MASK (0x300U) +#define PDM_DC_CTRL_DCCONFIG4_SHIFT (8U) +/*! DCCONFIG4 - Channel 4 DC Remover Configuration + * 0b00..20 Hz (PDM_CLK = 3.072 MHz) + * 0b01..13.3 Hz (PDM_CLK = 3.072 MHz) + * 0b10..40 Hz (PDM_CLK = 3.072 MHz) + * 0b11..DC remover is bypassed + */ +#define PDM_DC_CTRL_DCCONFIG4(x) (((uint32_t)(((uint32_t)(x)) << PDM_DC_CTRL_DCCONFIG4_SHIFT)) & PDM_DC_CTRL_DCCONFIG4_MASK) + +#define PDM_DC_CTRL_DCCONFIG5_MASK (0xC00U) +#define PDM_DC_CTRL_DCCONFIG5_SHIFT (10U) +/*! DCCONFIG5 - Channel 5 DC Remover Configuration + * 0b00..20 Hz (PDM_CLK = 3.072 MHz) + * 0b01..13.3 Hz (PDM_CLK = 3.072 MHz) + * 0b10..40 Hz (PDM_CLK = 3.072 MHz) + * 0b11..DC remover is bypassed + */ +#define PDM_DC_CTRL_DCCONFIG5(x) (((uint32_t)(((uint32_t)(x)) << PDM_DC_CTRL_DCCONFIG5_SHIFT)) & PDM_DC_CTRL_DCCONFIG5_MASK) + +#define PDM_DC_CTRL_DCCONFIG6_MASK (0x3000U) +#define PDM_DC_CTRL_DCCONFIG6_SHIFT (12U) +/*! DCCONFIG6 - Channel 6 DC Remover Configuration + * 0b00..20 Hz (PDM_CLK = 3.072 MHz) + * 0b01..13.3 Hz (PDM_CLK = 3.072 MHz) + * 0b10..40 Hz (PDM_CLK = 3.072 MHz) + * 0b11..DC remover is bypassed + */ +#define PDM_DC_CTRL_DCCONFIG6(x) (((uint32_t)(((uint32_t)(x)) << PDM_DC_CTRL_DCCONFIG6_SHIFT)) & PDM_DC_CTRL_DCCONFIG6_MASK) + +#define PDM_DC_CTRL_DCCONFIG7_MASK (0xC000U) +#define PDM_DC_CTRL_DCCONFIG7_SHIFT (14U) +/*! DCCONFIG7 - Channel 7 DC Remover Configuration + * 0b00..20 Hz (PDM_CLK = 3.072 MHz) + * 0b01..13.3 Hz (PDM_CLK = 3.072 MHz) + * 0b10..40 Hz (PDM_CLK = 3.072 MHz) + * 0b11..DC remover is bypassed + */ +#define PDM_DC_CTRL_DCCONFIG7(x) (((uint32_t)(((uint32_t)(x)) << PDM_DC_CTRL_DCCONFIG7_SHIFT)) & PDM_DC_CTRL_DCCONFIG7_MASK) +/*! @} */ + +/*! @name DC_OUT_CTRL - MICFIL Output DC Remover Control */ +/*! @{ */ + +#define PDM_DC_OUT_CTRL_DCCONFIG0_MASK (0x3U) +#define PDM_DC_OUT_CTRL_DCCONFIG0_SHIFT (0U) +/*! DCCONFIG0 - Channel 0 DC Remover Configuration + * 0b00..20 Hz (FS = 48 kHz) + * 0b01..13.3 Hz (FS = 48 kHz) + * 0b10..40 Hz (FS = 48 kHz) + * 0b11..DC remover is bypassed + */ +#define PDM_DC_OUT_CTRL_DCCONFIG0(x) (((uint32_t)(((uint32_t)(x)) << PDM_DC_OUT_CTRL_DCCONFIG0_SHIFT)) & PDM_DC_OUT_CTRL_DCCONFIG0_MASK) + +#define PDM_DC_OUT_CTRL_DCCONFIG1_MASK (0xCU) +#define PDM_DC_OUT_CTRL_DCCONFIG1_SHIFT (2U) +/*! DCCONFIG1 - Channel 1 DC Remover Configuration + * 0b00..20 Hz (FS = 48 kHz) + * 0b01..13.3 Hz (FS = 48 kHz) + * 0b10..40 Hz (FS = 48 kHz) + * 0b11..DC remover is bypassed + */ +#define PDM_DC_OUT_CTRL_DCCONFIG1(x) (((uint32_t)(((uint32_t)(x)) << PDM_DC_OUT_CTRL_DCCONFIG1_SHIFT)) & PDM_DC_OUT_CTRL_DCCONFIG1_MASK) + +#define PDM_DC_OUT_CTRL_DCCONFIG2_MASK (0x30U) +#define PDM_DC_OUT_CTRL_DCCONFIG2_SHIFT (4U) +/*! DCCONFIG2 - Channel 2 DC Remover Configuration + * 0b00..20 Hz (FS = 48 kHz) + * 0b01..13.3 Hz (FS = 48 kHz) + * 0b10..40 Hz (FS = 48 kHz) + * 0b11..DC remover is bypassed + */ +#define PDM_DC_OUT_CTRL_DCCONFIG2(x) (((uint32_t)(((uint32_t)(x)) << PDM_DC_OUT_CTRL_DCCONFIG2_SHIFT)) & PDM_DC_OUT_CTRL_DCCONFIG2_MASK) + +#define PDM_DC_OUT_CTRL_DCCONFIG3_MASK (0xC0U) +#define PDM_DC_OUT_CTRL_DCCONFIG3_SHIFT (6U) +/*! DCCONFIG3 - Channel 3 DC Remover Configuration + * 0b00..20 Hz (FS = 48 kHz) + * 0b01..13.3 Hz (FS = 48 kHz) + * 0b10..40 Hz (FS = 48 kHz) + * 0b11..DC remover is bypassed + */ +#define PDM_DC_OUT_CTRL_DCCONFIG3(x) (((uint32_t)(((uint32_t)(x)) << PDM_DC_OUT_CTRL_DCCONFIG3_SHIFT)) & PDM_DC_OUT_CTRL_DCCONFIG3_MASK) + +#define PDM_DC_OUT_CTRL_DCCONFIG4_MASK (0x300U) +#define PDM_DC_OUT_CTRL_DCCONFIG4_SHIFT (8U) +/*! DCCONFIG4 - Channel 4 DC Remover Configuration + * 0b00..20 Hz (FS = 48 kHz) + * 0b01..13.3 Hz (FS = 48 kHz) + * 0b10..40 Hz (FS = 48 kHz) + * 0b11..DC remover is bypassed + */ +#define PDM_DC_OUT_CTRL_DCCONFIG4(x) (((uint32_t)(((uint32_t)(x)) << PDM_DC_OUT_CTRL_DCCONFIG4_SHIFT)) & PDM_DC_OUT_CTRL_DCCONFIG4_MASK) + +#define PDM_DC_OUT_CTRL_DCCONFIG5_MASK (0xC00U) +#define PDM_DC_OUT_CTRL_DCCONFIG5_SHIFT (10U) +/*! DCCONFIG5 - Channel 5 DC Remover Configuration + * 0b00..20 Hz (FS = 48 kHz) + * 0b01..13.3 Hz (FS = 48 kHz) + * 0b10..40 Hz (FS = 48 kHz) + * 0b11..DC remover is bypassed + */ +#define PDM_DC_OUT_CTRL_DCCONFIG5(x) (((uint32_t)(((uint32_t)(x)) << PDM_DC_OUT_CTRL_DCCONFIG5_SHIFT)) & PDM_DC_OUT_CTRL_DCCONFIG5_MASK) + +#define PDM_DC_OUT_CTRL_DCCONFIG6_MASK (0x3000U) +#define PDM_DC_OUT_CTRL_DCCONFIG6_SHIFT (12U) +/*! DCCONFIG6 - Channel 6 DC Remover Configuration + * 0b00..20 Hz (FS = 48 kHz) + * 0b01..13.3 Hz (FS = 48 kHz) + * 0b10..40 Hz (FS = 48 kHz) + * 0b11..DC remover is bypassed + */ +#define PDM_DC_OUT_CTRL_DCCONFIG6(x) (((uint32_t)(((uint32_t)(x)) << PDM_DC_OUT_CTRL_DCCONFIG6_SHIFT)) & PDM_DC_OUT_CTRL_DCCONFIG6_MASK) + +#define PDM_DC_OUT_CTRL_DCCONFIG7_MASK (0xC000U) +#define PDM_DC_OUT_CTRL_DCCONFIG7_SHIFT (14U) +/*! DCCONFIG7 - Channel 7 DC Remover Configuration + * 0b00..20 Hz (FS = 48 kHz) + * 0b01..13.3 Hz (FS = 48 kHz) + * 0b10..40 Hz (FS = 48 kHz) + * 0b11..DC remover is bypassed + */ +#define PDM_DC_OUT_CTRL_DCCONFIG7(x) (((uint32_t)(((uint32_t)(x)) << PDM_DC_OUT_CTRL_DCCONFIG7_SHIFT)) & PDM_DC_OUT_CTRL_DCCONFIG7_MASK) +/*! @} */ + +/*! @name RANGE_CTRL - MICFIL Range Control */ +/*! @{ */ + +#define PDM_RANGE_CTRL_RANGEADJ0_MASK (0xFU) +#define PDM_RANGE_CTRL_RANGEADJ0_SHIFT (0U) +/*! RANGEADJ0 - Channel 0 Range Adjustment */ +#define PDM_RANGE_CTRL_RANGEADJ0(x) (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_CTRL_RANGEADJ0_SHIFT)) & PDM_RANGE_CTRL_RANGEADJ0_MASK) + +#define PDM_RANGE_CTRL_RANGEADJ1_MASK (0xF0U) +#define PDM_RANGE_CTRL_RANGEADJ1_SHIFT (4U) +/*! RANGEADJ1 - Channel 1 Range Adjustment */ +#define PDM_RANGE_CTRL_RANGEADJ1(x) (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_CTRL_RANGEADJ1_SHIFT)) & PDM_RANGE_CTRL_RANGEADJ1_MASK) + +#define PDM_RANGE_CTRL_RANGEADJ2_MASK (0xF00U) +#define PDM_RANGE_CTRL_RANGEADJ2_SHIFT (8U) +/*! RANGEADJ2 - Channel 2 Range Adjustment */ +#define PDM_RANGE_CTRL_RANGEADJ2(x) (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_CTRL_RANGEADJ2_SHIFT)) & PDM_RANGE_CTRL_RANGEADJ2_MASK) + +#define PDM_RANGE_CTRL_RANGEADJ3_MASK (0xF000U) +#define PDM_RANGE_CTRL_RANGEADJ3_SHIFT (12U) +/*! RANGEADJ3 - Channel 3 Range Adjustment */ +#define PDM_RANGE_CTRL_RANGEADJ3(x) (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_CTRL_RANGEADJ3_SHIFT)) & PDM_RANGE_CTRL_RANGEADJ3_MASK) + +#define PDM_RANGE_CTRL_RANGEADJ4_MASK (0xF0000U) +#define PDM_RANGE_CTRL_RANGEADJ4_SHIFT (16U) +/*! RANGEADJ4 - Channel 4 Range Adjustment */ +#define PDM_RANGE_CTRL_RANGEADJ4(x) (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_CTRL_RANGEADJ4_SHIFT)) & PDM_RANGE_CTRL_RANGEADJ4_MASK) + +#define PDM_RANGE_CTRL_RANGEADJ5_MASK (0xF00000U) +#define PDM_RANGE_CTRL_RANGEADJ5_SHIFT (20U) +/*! RANGEADJ5 - Channel 5 Range Adjustment */ +#define PDM_RANGE_CTRL_RANGEADJ5(x) (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_CTRL_RANGEADJ5_SHIFT)) & PDM_RANGE_CTRL_RANGEADJ5_MASK) + +#define PDM_RANGE_CTRL_RANGEADJ6_MASK (0xF000000U) +#define PDM_RANGE_CTRL_RANGEADJ6_SHIFT (24U) +/*! RANGEADJ6 - Channel 6 Range Adjustment */ +#define PDM_RANGE_CTRL_RANGEADJ6(x) (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_CTRL_RANGEADJ6_SHIFT)) & PDM_RANGE_CTRL_RANGEADJ6_MASK) + +#define PDM_RANGE_CTRL_RANGEADJ7_MASK (0xF0000000U) +#define PDM_RANGE_CTRL_RANGEADJ7_SHIFT (28U) +/*! RANGEADJ7 - Channel 7 Range Adjustment */ +#define PDM_RANGE_CTRL_RANGEADJ7(x) (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_CTRL_RANGEADJ7_SHIFT)) & PDM_RANGE_CTRL_RANGEADJ7_MASK) +/*! @} */ + +/*! @name RANGE_STAT - MICFIL Range Status */ +/*! @{ */ + +#define PDM_RANGE_STAT_RANGEOVF0_MASK (0x1U) +#define PDM_RANGE_STAT_RANGEOVF0_SHIFT (0U) +/*! RANGEOVF0 - Channel 0 Range Overflow Error Flag + * 0b0..No exception by range overflow + * 0b1..Exception by range overflow + */ +#define PDM_RANGE_STAT_RANGEOVF0(x) (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEOVF0_SHIFT)) & PDM_RANGE_STAT_RANGEOVF0_MASK) + +#define PDM_RANGE_STAT_RANGEOVF1_MASK (0x2U) +#define PDM_RANGE_STAT_RANGEOVF1_SHIFT (1U) +/*! RANGEOVF1 - Channel 1 Range Overflow Error Flag + * 0b0..No exception by range overflow + * 0b1..Exception by range overflow + */ +#define PDM_RANGE_STAT_RANGEOVF1(x) (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEOVF1_SHIFT)) & PDM_RANGE_STAT_RANGEOVF1_MASK) + +#define PDM_RANGE_STAT_RANGEOVF2_MASK (0x4U) +#define PDM_RANGE_STAT_RANGEOVF2_SHIFT (2U) +/*! RANGEOVF2 - Channel 2 Range Overflow Error Flag + * 0b0..No exception by range overflow + * 0b1..Exception by range overflow + */ +#define PDM_RANGE_STAT_RANGEOVF2(x) (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEOVF2_SHIFT)) & PDM_RANGE_STAT_RANGEOVF2_MASK) + +#define PDM_RANGE_STAT_RANGEOVF3_MASK (0x8U) +#define PDM_RANGE_STAT_RANGEOVF3_SHIFT (3U) +/*! RANGEOVF3 - Channel 3 Range Overflow Error Flag + * 0b0..No exception by range overflow + * 0b1..Exception by range overflow + */ +#define PDM_RANGE_STAT_RANGEOVF3(x) (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEOVF3_SHIFT)) & PDM_RANGE_STAT_RANGEOVF3_MASK) + +#define PDM_RANGE_STAT_RANGEOVF4_MASK (0x10U) +#define PDM_RANGE_STAT_RANGEOVF4_SHIFT (4U) +/*! RANGEOVF4 - Channel 4 Range Overflow Error Flag + * 0b0..No exception by range overflow + * 0b1..Exception by range overflow + */ +#define PDM_RANGE_STAT_RANGEOVF4(x) (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEOVF4_SHIFT)) & PDM_RANGE_STAT_RANGEOVF4_MASK) + +#define PDM_RANGE_STAT_RANGEOVF5_MASK (0x20U) +#define PDM_RANGE_STAT_RANGEOVF5_SHIFT (5U) +/*! RANGEOVF5 - Channel 5 Range Overflow Error Flag + * 0b0..No exception by range overflow + * 0b1..Exception by range overflow + */ +#define PDM_RANGE_STAT_RANGEOVF5(x) (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEOVF5_SHIFT)) & PDM_RANGE_STAT_RANGEOVF5_MASK) + +#define PDM_RANGE_STAT_RANGEOVF6_MASK (0x40U) +#define PDM_RANGE_STAT_RANGEOVF6_SHIFT (6U) +/*! RANGEOVF6 - Channel 6 Range Overflow Error Flag + * 0b0..No exception by range overflow + * 0b1..Exception by range overflow + */ +#define PDM_RANGE_STAT_RANGEOVF6(x) (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEOVF6_SHIFT)) & PDM_RANGE_STAT_RANGEOVF6_MASK) + +#define PDM_RANGE_STAT_RANGEOVF7_MASK (0x80U) +#define PDM_RANGE_STAT_RANGEOVF7_SHIFT (7U) +/*! RANGEOVF7 - Channel 7 Range Overflow Error Flag + * 0b0..No exception by range overflow + * 0b1..Exception by range overflow + */ +#define PDM_RANGE_STAT_RANGEOVF7(x) (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEOVF7_SHIFT)) & PDM_RANGE_STAT_RANGEOVF7_MASK) + +#define PDM_RANGE_STAT_RANGEUNF0_MASK (0x10000U) +#define PDM_RANGE_STAT_RANGEUNF0_SHIFT (16U) +/*! RANGEUNF0 - Channel 0 Range Underflow Error Flag + * 0b0..No exception by range underflow + * 0b1..Exception by range underflow + */ +#define PDM_RANGE_STAT_RANGEUNF0(x) (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEUNF0_SHIFT)) & PDM_RANGE_STAT_RANGEUNF0_MASK) + +#define PDM_RANGE_STAT_RANGEUNF1_MASK (0x20000U) +#define PDM_RANGE_STAT_RANGEUNF1_SHIFT (17U) +/*! RANGEUNF1 - Channel 1 Range Underflow Error Flag + * 0b0..No exception by range underflow + * 0b1..Exception by range underflow + */ +#define PDM_RANGE_STAT_RANGEUNF1(x) (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEUNF1_SHIFT)) & PDM_RANGE_STAT_RANGEUNF1_MASK) + +#define PDM_RANGE_STAT_RANGEUNF2_MASK (0x40000U) +#define PDM_RANGE_STAT_RANGEUNF2_SHIFT (18U) +/*! RANGEUNF2 - Channel 2 Range Underflow Error Flag + * 0b0..No exception by range underflow + * 0b1..Exception by range underflow + */ +#define PDM_RANGE_STAT_RANGEUNF2(x) (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEUNF2_SHIFT)) & PDM_RANGE_STAT_RANGEUNF2_MASK) + +#define PDM_RANGE_STAT_RANGEUNF3_MASK (0x80000U) +#define PDM_RANGE_STAT_RANGEUNF3_SHIFT (19U) +/*! RANGEUNF3 - Channel 3 Range Underflow Error Flag + * 0b0..No exception by range underflow + * 0b1..Exception by range underflow + */ +#define PDM_RANGE_STAT_RANGEUNF3(x) (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEUNF3_SHIFT)) & PDM_RANGE_STAT_RANGEUNF3_MASK) + +#define PDM_RANGE_STAT_RANGEUNF4_MASK (0x100000U) +#define PDM_RANGE_STAT_RANGEUNF4_SHIFT (20U) +/*! RANGEUNF4 - Channel 4 Range Underflow Error Flag + * 0b0..No exception by range underflow + * 0b1..Exception by range underflow + */ +#define PDM_RANGE_STAT_RANGEUNF4(x) (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEUNF4_SHIFT)) & PDM_RANGE_STAT_RANGEUNF4_MASK) + +#define PDM_RANGE_STAT_RANGEUNF5_MASK (0x200000U) +#define PDM_RANGE_STAT_RANGEUNF5_SHIFT (21U) +/*! RANGEUNF5 - Channel 5 Range Underflow Error Flag + * 0b0..No exception by range underflow + * 0b1..Exception by range underflow + */ +#define PDM_RANGE_STAT_RANGEUNF5(x) (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEUNF5_SHIFT)) & PDM_RANGE_STAT_RANGEUNF5_MASK) + +#define PDM_RANGE_STAT_RANGEUNF6_MASK (0x400000U) +#define PDM_RANGE_STAT_RANGEUNF6_SHIFT (22U) +/*! RANGEUNF6 - Channel 6 Range Underflow Error Flag + * 0b0..No exception by range underflow + * 0b1..Exception by range underflow + */ +#define PDM_RANGE_STAT_RANGEUNF6(x) (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEUNF6_SHIFT)) & PDM_RANGE_STAT_RANGEUNF6_MASK) + +#define PDM_RANGE_STAT_RANGEUNF7_MASK (0x800000U) +#define PDM_RANGE_STAT_RANGEUNF7_SHIFT (23U) +/*! RANGEUNF7 - Channel 7 Range Underflow Error Flag + * 0b0..No exception by range underflow + * 0b1..Exception by range underflow + */ +#define PDM_RANGE_STAT_RANGEUNF7(x) (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEUNF7_SHIFT)) & PDM_RANGE_STAT_RANGEUNF7_MASK) +/*! @} */ + +/*! @name FSYNC_CTRL - Frame Synchronization Control */ +/*! @{ */ + +#define PDM_FSYNC_CTRL_FSYNCLEN_MASK (0xFFFFFFFFU) +#define PDM_FSYNC_CTRL_FSYNCLEN_SHIFT (0U) +/*! FSYNCLEN - Frame Synchronization Window Length */ +#define PDM_FSYNC_CTRL_FSYNCLEN(x) (((uint32_t)(((uint32_t)(x)) << PDM_FSYNC_CTRL_FSYNCLEN_SHIFT)) & PDM_FSYNC_CTRL_FSYNCLEN_MASK) +/*! @} */ + +/*! @name VERID - Version ID */ +/*! @{ */ + +#define PDM_VERID_FEATURE_MASK (0xFFFFU) +#define PDM_VERID_FEATURE_SHIFT (0U) +/*! FEATURE - Feature Specification Number */ +#define PDM_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << PDM_VERID_FEATURE_SHIFT)) & PDM_VERID_FEATURE_MASK) + +#define PDM_VERID_MINOR_MASK (0xFF0000U) +#define PDM_VERID_MINOR_SHIFT (16U) +/*! MINOR - Minor Version Number */ +#define PDM_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << PDM_VERID_MINOR_SHIFT)) & PDM_VERID_MINOR_MASK) + +#define PDM_VERID_MAJOR_MASK (0xFF000000U) +#define PDM_VERID_MAJOR_SHIFT (24U) +/*! MAJOR - Major Version Number */ +#define PDM_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << PDM_VERID_MAJOR_SHIFT)) & PDM_VERID_MAJOR_MASK) +/*! @} */ + +/*! @name PARAM - Parameter */ +/*! @{ */ + +#define PDM_PARAM_NPAIR_MASK (0xFU) +#define PDM_PARAM_NPAIR_SHIFT (0U) +/*! NPAIR - Number of Microphone Pairs + * 0b0000..None + * 0b0001..1 pair + * 0b0010..2 pairs + * 0b0011-0b1110..... + * 0b1111..15 pairs + */ +#define PDM_PARAM_NPAIR(x) (((uint32_t)(((uint32_t)(x)) << PDM_PARAM_NPAIR_SHIFT)) & PDM_PARAM_NPAIR_MASK) + +#define PDM_PARAM_FIFO_PTRWID_MASK (0xF0U) +#define PDM_PARAM_FIFO_PTRWID_SHIFT (4U) +/*! FIFO_PTRWID - FIFO Pointer Width + * 0b0000..0 bits + * 0b0001..1 bit + * 0b0010..2 bits + * 0b0011-0b1110..... + * 0b1111..15 bits + */ +#define PDM_PARAM_FIFO_PTRWID(x) (((uint32_t)(((uint32_t)(x)) << PDM_PARAM_FIFO_PTRWID_SHIFT)) & PDM_PARAM_FIFO_PTRWID_MASK) + +#define PDM_PARAM_FIL_OUT_WIDTH_24B_MASK (0x100U) +#define PDM_PARAM_FIL_OUT_WIDTH_24B_SHIFT (8U) +/*! FIL_OUT_WIDTH_24B - Filter Output Width + * 0b0..16 bits + * 0b1..24 bits + */ +#define PDM_PARAM_FIL_OUT_WIDTH_24B(x) (((uint32_t)(((uint32_t)(x)) << PDM_PARAM_FIL_OUT_WIDTH_24B_SHIFT)) & PDM_PARAM_FIL_OUT_WIDTH_24B_MASK) + +#define PDM_PARAM_LOW_POWER_MASK (0x200U) +#define PDM_PARAM_LOW_POWER_SHIFT (9U) +/*! LOW_POWER - Low-Power Decimation Filter + * 0b0..Disables + * 0b1..Enables + */ +#define PDM_PARAM_LOW_POWER(x) (((uint32_t)(((uint32_t)(x)) << PDM_PARAM_LOW_POWER_SHIFT)) & PDM_PARAM_LOW_POWER_MASK) + +#define PDM_PARAM_DC_BYPASS_MASK (0x400U) +#define PDM_PARAM_DC_BYPASS_SHIFT (10U) +/*! DC_BYPASS - Input DC Remover Bypass + * 0b0..Active + * 0b1..Disabled + */ +#define PDM_PARAM_DC_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << PDM_PARAM_DC_BYPASS_SHIFT)) & PDM_PARAM_DC_BYPASS_MASK) + +#define PDM_PARAM_DC_OUT_BYPASS_MASK (0x800U) +#define PDM_PARAM_DC_OUT_BYPASS_SHIFT (11U) +/*! DC_OUT_BYPASS - Output DC Remover Bypass + * 0b0..Active + * 0b1..Disabled + */ +#define PDM_PARAM_DC_OUT_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << PDM_PARAM_DC_OUT_BYPASS_SHIFT)) & PDM_PARAM_DC_OUT_BYPASS_MASK) + +#define PDM_PARAM_HWVAD_MASK (0x10000U) +#define PDM_PARAM_HWVAD_SHIFT (16U) +/*! HWVAD - HWVAD Active + * 0b0..Disabled + * 0b1..Active + */ +#define PDM_PARAM_HWVAD(x) (((uint32_t)(((uint32_t)(x)) << PDM_PARAM_HWVAD_SHIFT)) & PDM_PARAM_HWVAD_MASK) + +#define PDM_PARAM_HWVAD_ENERGY_MODE_MASK (0x20000U) +#define PDM_PARAM_HWVAD_ENERGY_MODE_SHIFT (17U) +/*! HWVAD_ENERGY_MODE - HWVAD Energy Mode Active + * 0b0..Disabled + * 0b1..Active + */ +#define PDM_PARAM_HWVAD_ENERGY_MODE(x) (((uint32_t)(((uint32_t)(x)) << PDM_PARAM_HWVAD_ENERGY_MODE_SHIFT)) & PDM_PARAM_HWVAD_ENERGY_MODE_MASK) + +#define PDM_PARAM_HWVAD_ZCD_MASK (0x80000U) +#define PDM_PARAM_HWVAD_ZCD_SHIFT (19U) +/*! HWVAD_ZCD - HWVAD ZCD Active + * 0b0..Disabled + * 0b1..Active + */ +#define PDM_PARAM_HWVAD_ZCD(x) (((uint32_t)(((uint32_t)(x)) << PDM_PARAM_HWVAD_ZCD_SHIFT)) & PDM_PARAM_HWVAD_ZCD_MASK) + +#define PDM_PARAM_NUM_HWVAD_MASK (0xF000000U) +#define PDM_PARAM_NUM_HWVAD_SHIFT (24U) +/*! NUM_HWVAD - Number of HWVADs */ +#define PDM_PARAM_NUM_HWVAD(x) (((uint32_t)(((uint32_t)(x)) << PDM_PARAM_NUM_HWVAD_SHIFT)) & PDM_PARAM_NUM_HWVAD_MASK) +/*! @} */ + +/*! @name VAD0_CTRL_1 - Voice Activity Detector 0 Control */ +/*! @{ */ + +#define PDM_VAD0_CTRL_1_VADEN_MASK (0x1U) +#define PDM_VAD0_CTRL_1_VADEN_SHIFT (0U) +/*! VADEN - HWVAD Enable + * 0b0..Disables + * 0b1..Enables + */ +#define PDM_VAD0_CTRL_1_VADEN(x) (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_1_VADEN_SHIFT)) & PDM_VAD0_CTRL_1_VADEN_MASK) + +#define PDM_VAD0_CTRL_1_VADRST_MASK (0x2U) +#define PDM_VAD0_CTRL_1_VADRST_SHIFT (1U) +/*! VADRST - HWVAD Reset */ +#define PDM_VAD0_CTRL_1_VADRST(x) (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_1_VADRST_SHIFT)) & PDM_VAD0_CTRL_1_VADRST_MASK) + +#define PDM_VAD0_CTRL_1_VADIE_MASK (0x4U) +#define PDM_VAD0_CTRL_1_VADIE_SHIFT (2U) +/*! VADIE - Interruption Enable + * 0b0..Disables + * 0b1..Enables + */ +#define PDM_VAD0_CTRL_1_VADIE(x) (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_1_VADIE_SHIFT)) & PDM_VAD0_CTRL_1_VADIE_MASK) + +#define PDM_VAD0_CTRL_1_VADERIE_MASK (0x8U) +#define PDM_VAD0_CTRL_1_VADERIE_SHIFT (3U) +/*! VADERIE - Error Interruption Enable + * 0b0..Disables + * 0b1..Enables + */ +#define PDM_VAD0_CTRL_1_VADERIE(x) (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_1_VADERIE_SHIFT)) & PDM_VAD0_CTRL_1_VADERIE_MASK) + +#define PDM_VAD0_CTRL_1_VADST10_MASK (0x10U) +#define PDM_VAD0_CTRL_1_VADST10_SHIFT (4U) +/*! VADST10 - Internal Filters Initialization + * 0b0..Normal operation + * 0b1..Filters initialized + */ +#define PDM_VAD0_CTRL_1_VADST10(x) (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_1_VADST10_SHIFT)) & PDM_VAD0_CTRL_1_VADST10_MASK) + +#define PDM_VAD0_CTRL_1_VADINITT_MASK (0x1F00U) +#define PDM_VAD0_CTRL_1_VADINITT_SHIFT (8U) +/*! VADINITT - Initialization Time + * 0b00000..0 + * 0b00001..1 + * 0b00010-0b11110..... + * 0b11111..31 + */ +#define PDM_VAD0_CTRL_1_VADINITT(x) (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_1_VADINITT_SHIFT)) & PDM_VAD0_CTRL_1_VADINITT_MASK) + +#define PDM_VAD0_CTRL_1_VADCICOSR_MASK (0xF0000U) +#define PDM_VAD0_CTRL_1_VADCICOSR_SHIFT (16U) +/*! VADCICOSR - CIC Oversampling Rate */ +#define PDM_VAD0_CTRL_1_VADCICOSR(x) (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_1_VADCICOSR_SHIFT)) & PDM_VAD0_CTRL_1_VADCICOSR_MASK) + +#define PDM_VAD0_CTRL_1_VADCHSEL_MASK (0x7000000U) +#define PDM_VAD0_CTRL_1_VADCHSEL_SHIFT (24U) +/*! VADCHSEL - Channel Selector + * 0b000..PDM Microphone 0 Left + * 0b001..PDM Microphone 0 Right + * 0b010..PDM Microphone 1 Left + * 0b011-0b101..... + * 0b110..PDM Microphone 3 Left + * 0b111..PDM Microphone 3 Right + */ +#define PDM_VAD0_CTRL_1_VADCHSEL(x) (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_1_VADCHSEL_SHIFT)) & PDM_VAD0_CTRL_1_VADCHSEL_MASK) +/*! @} */ + +/*! @name VAD0_CTRL_2 - Voice Activity Detector 0 Control */ +/*! @{ */ + +#define PDM_VAD0_CTRL_2_VADHPF_MASK (0x3U) +#define PDM_VAD0_CTRL_2_VADHPF_SHIFT (0U) +/*! VADHPF - High-Pass Filter + * 0b00..Filter bypassed + * 0b01..Cut-off frequency at 1750 Hz + * 0b10..Cut-off frequency at 215 Hz + * 0b11..Cut-off frequency at 102 Hz + */ +#define PDM_VAD0_CTRL_2_VADHPF(x) (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_2_VADHPF_SHIFT)) & PDM_VAD0_CTRL_2_VADHPF_MASK) + +#define PDM_VAD0_CTRL_2_VADINPGAIN_MASK (0xF00U) +#define PDM_VAD0_CTRL_2_VADINPGAIN_SHIFT (8U) +/*! VADINPGAIN - Input Gain + * 0b0000..No shift + * 0b0001..Shift 1 bit to the left + * 0b0010..Shift 2 bits to the left + * 0b0011-0b0110..... + * 0b0111..Shift 7 bits to the left + * 0b1000..Shift 8 bits to the right + * 0b1001..Shift 7 bits to the right + * 0b1010-0b1110..... + * 0b1111..Shift 1 bits to the right + */ +#define PDM_VAD0_CTRL_2_VADINPGAIN(x) (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_2_VADINPGAIN_SHIFT)) & PDM_VAD0_CTRL_2_VADINPGAIN_MASK) + +#define PDM_VAD0_CTRL_2_VADFRAMET_MASK (0x3F0000U) +#define PDM_VAD0_CTRL_2_VADFRAMET_SHIFT (16U) +/*! VADFRAMET - Frame Time + * 0b000000..1 + * 0b000001..2 + * 0b000010-0b111110..... + * 0b111111..63 + */ +#define PDM_VAD0_CTRL_2_VADFRAMET(x) (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_2_VADFRAMET_SHIFT)) & PDM_VAD0_CTRL_2_VADFRAMET_MASK) + +#define PDM_VAD0_CTRL_2_VADFOUTDIS_MASK (0x10000000U) +#define PDM_VAD0_CTRL_2_VADFOUTDIS_SHIFT (28U) +/*! VADFOUTDIS - Force Output Disable + * 0b0..Enables + * 0b1..Disables + */ +#define PDM_VAD0_CTRL_2_VADFOUTDIS(x) (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_2_VADFOUTDIS_SHIFT)) & PDM_VAD0_CTRL_2_VADFOUTDIS_MASK) + +#define PDM_VAD0_CTRL_2_VADPREFEN_MASK (0x40000000U) +#define PDM_VAD0_CTRL_2_VADPREFEN_SHIFT (30U) +/*! VADPREFEN - Pre Filter Enable + * 0b0..Pre-filter bypassed + * 0b1..Pre-filter enabled + */ +#define PDM_VAD0_CTRL_2_VADPREFEN(x) (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_2_VADPREFEN_SHIFT)) & PDM_VAD0_CTRL_2_VADPREFEN_MASK) + +#define PDM_VAD0_CTRL_2_VADFRENDIS_MASK (0x80000000U) +#define PDM_VAD0_CTRL_2_VADFRENDIS_SHIFT (31U) +/*! VADFRENDIS - Frame Energy Disable + * 0b0..Enables + * 0b1..Disables + */ +#define PDM_VAD0_CTRL_2_VADFRENDIS(x) (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_2_VADFRENDIS_SHIFT)) & PDM_VAD0_CTRL_2_VADFRENDIS_MASK) +/*! @} */ + +/*! @name VAD0_STAT - Voice Activity Detector 0 Status */ +/*! @{ */ + +#define PDM_VAD0_STAT_VADIF_MASK (0x1U) +#define PDM_VAD0_STAT_VADIF_SHIFT (0U) +/*! VADIF - Interrupt Flag + * 0b0..Not detected + * 0b1..Detected + */ +#define PDM_VAD0_STAT_VADIF(x) (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_STAT_VADIF_SHIFT)) & PDM_VAD0_STAT_VADIF_MASK) + +#define PDM_VAD0_STAT_VADINSATF_MASK (0x10000U) +#define PDM_VAD0_STAT_VADINSATF_SHIFT (16U) +/*! VADINSATF - Input Saturation Flag + * 0b0..No exception + * 0b1..Exception + */ +#define PDM_VAD0_STAT_VADINSATF(x) (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_STAT_VADINSATF_SHIFT)) & PDM_VAD0_STAT_VADINSATF_MASK) + +#define PDM_VAD0_STAT_VADINITF_MASK (0x80000000U) +#define PDM_VAD0_STAT_VADINITF_SHIFT (31U) +/*! VADINITF - Initialization Flag + * 0b0..Not being initialized + * 0b1..Being initialized + */ +#define PDM_VAD0_STAT_VADINITF(x) (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_STAT_VADINITF_SHIFT)) & PDM_VAD0_STAT_VADINITF_MASK) +/*! @} */ + +/*! @name VAD0_SCONFIG - Voice Activity Detector 0 Signal Configuration */ +/*! @{ */ + +#define PDM_VAD0_SCONFIG_VADSGAIN_MASK (0xFU) +#define PDM_VAD0_SCONFIG_VADSGAIN_SHIFT (0U) +/*! VADSGAIN - Signal Gain + * 0b0000, 0b0001..Multiplier = 1 + * 0b0010..Multiplier = 2 + * 0b0011-0b1110..... + * 0b1111..Multiplier = 15 + */ +#define PDM_VAD0_SCONFIG_VADSGAIN(x) (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_SCONFIG_VADSGAIN_SHIFT)) & PDM_VAD0_SCONFIG_VADSGAIN_MASK) + +#define PDM_VAD0_SCONFIG_VADSMAXEN_MASK (0x40000000U) +#define PDM_VAD0_SCONFIG_VADSMAXEN_SHIFT (30U) +/*! VADSMAXEN - Signal Maximum Enable + * 0b0..Maximum block bypassed + * 0b1..Maximum block enabled + */ +#define PDM_VAD0_SCONFIG_VADSMAXEN(x) (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_SCONFIG_VADSMAXEN_SHIFT)) & PDM_VAD0_SCONFIG_VADSMAXEN_MASK) + +#define PDM_VAD0_SCONFIG_VADSFILEN_MASK (0x80000000U) +#define PDM_VAD0_SCONFIG_VADSFILEN_SHIFT (31U) +/*! VADSFILEN - Signal Filter Enable + * 0b0..Disables + * 0b1..Enables + */ +#define PDM_VAD0_SCONFIG_VADSFILEN(x) (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_SCONFIG_VADSFILEN_SHIFT)) & PDM_VAD0_SCONFIG_VADSFILEN_MASK) +/*! @} */ + +/*! @name VAD0_NCONFIG - Voice Activity Detector 0 Noise Configuration */ +/*! @{ */ + +#define PDM_VAD0_NCONFIG_VADNGAIN_MASK (0xFU) +#define PDM_VAD0_NCONFIG_VADNGAIN_SHIFT (0U) +/*! VADNGAIN - Noise Gain + * 0b0000, 0b0001..Multiplier = 1 + * 0b0010..Multiplier = 2 + * 0b0011-0b1110..... + * 0b1111..Multiplier = 15 + */ +#define PDM_VAD0_NCONFIG_VADNGAIN(x) (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_NCONFIG_VADNGAIN_SHIFT)) & PDM_VAD0_NCONFIG_VADNGAIN_MASK) + +#define PDM_VAD0_NCONFIG_VADNFILADJ_MASK (0x1F00U) +#define PDM_VAD0_NCONFIG_VADNFILADJ_SHIFT (8U) +/*! VADNFILADJ - Noise Filter Adjustment + * 0b00000..0 + * 0b00001..1 + * 0b00010-0b11110..... + * 0b11111..31 + */ +#define PDM_VAD0_NCONFIG_VADNFILADJ(x) (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_NCONFIG_VADNFILADJ_SHIFT)) & PDM_VAD0_NCONFIG_VADNFILADJ_MASK) + +#define PDM_VAD0_NCONFIG_VADNOREN_MASK (0x10000000U) +#define PDM_VAD0_NCONFIG_VADNOREN_SHIFT (28U) +/*! VADNOREN - Noise OR Enable + * 0b0..Not decimated + * 0b1..Decimated + */ +#define PDM_VAD0_NCONFIG_VADNOREN(x) (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_NCONFIG_VADNOREN_SHIFT)) & PDM_VAD0_NCONFIG_VADNOREN_MASK) + +#define PDM_VAD0_NCONFIG_VADNDECEN_MASK (0x20000000U) +#define PDM_VAD0_NCONFIG_VADNDECEN_SHIFT (29U) +/*! VADNDECEN - Noise Decimation Enable + * 0b0..Not decimated + * 0b1..Decimated + */ +#define PDM_VAD0_NCONFIG_VADNDECEN(x) (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_NCONFIG_VADNDECEN_SHIFT)) & PDM_VAD0_NCONFIG_VADNDECEN_MASK) + +#define PDM_VAD0_NCONFIG_VADNMINEN_MASK (0x40000000U) +#define PDM_VAD0_NCONFIG_VADNMINEN_SHIFT (30U) +/*! VADNMINEN - Noise Minimum Enable + * 0b0..Minimum block bypassed + * 0b1..Minimum block enabled + */ +#define PDM_VAD0_NCONFIG_VADNMINEN(x) (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_NCONFIG_VADNMINEN_SHIFT)) & PDM_VAD0_NCONFIG_VADNMINEN_MASK) + +#define PDM_VAD0_NCONFIG_VADNFILAUTO_MASK (0x80000000U) +#define PDM_VAD0_NCONFIG_VADNFILAUTO_SHIFT (31U) +/*! VADNFILAUTO - Noise Filter Auto + * 0b0..Always enabled + * 0b1..Enabled or disabled based on voice activity information + */ +#define PDM_VAD0_NCONFIG_VADNFILAUTO(x) (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_NCONFIG_VADNFILAUTO_SHIFT)) & PDM_VAD0_NCONFIG_VADNFILAUTO_MASK) +/*! @} */ + +/*! @name VAD0_NDATA - Voice Activity Detector 0 Noise Data */ +/*! @{ */ + +#define PDM_VAD0_NDATA_VADNDATA_MASK (0xFFFFU) +#define PDM_VAD0_NDATA_VADNDATA_SHIFT (0U) +/*! VADNDATA - Noise Data */ +#define PDM_VAD0_NDATA_VADNDATA(x) (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_NDATA_VADNDATA_SHIFT)) & PDM_VAD0_NDATA_VADNDATA_MASK) +/*! @} */ + +/*! @name VAD0_ZCD - Voice Activity Detector 0 Zero-Crossing Detector */ +/*! @{ */ + +#define PDM_VAD0_ZCD_VADZCDEN_MASK (0x1U) +#define PDM_VAD0_ZCD_VADZCDEN_SHIFT (0U) +/*! VADZCDEN - ZCD Enable + * 0b0..Disables + * 0b1..Enables + */ +#define PDM_VAD0_ZCD_VADZCDEN(x) (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_ZCD_VADZCDEN_SHIFT)) & PDM_VAD0_ZCD_VADZCDEN_MASK) + +#define PDM_VAD0_ZCD_VADZCDAUTO_MASK (0x4U) +#define PDM_VAD0_ZCD_VADZCDAUTO_SHIFT (2U) +/*! VADZCDAUTO - ZCD Automatic Threshold + * 0b0..Disables + * 0b1..Enables + */ +#define PDM_VAD0_ZCD_VADZCDAUTO(x) (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_ZCD_VADZCDAUTO_SHIFT)) & PDM_VAD0_ZCD_VADZCDAUTO_MASK) + +#define PDM_VAD0_ZCD_VADZCDAND_MASK (0x10U) +#define PDM_VAD0_ZCD_VADZCDAND_SHIFT (4U) +/*! VADZCDAND - ZCD AND Behavior + * 0b0..OR + * 0b1..AND + */ +#define PDM_VAD0_ZCD_VADZCDAND(x) (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_ZCD_VADZCDAND_SHIFT)) & PDM_VAD0_ZCD_VADZCDAND_MASK) + +#define PDM_VAD0_ZCD_VADZCDADJ_MASK (0xF00U) +#define PDM_VAD0_ZCD_VADZCDADJ_SHIFT (8U) +/*! VADZCDADJ - ZCD Adjustment + * 0b0000..0 + * 0b0001..1 + * 0b0010-0b1110..... + * 0b1111..15 + */ +#define PDM_VAD0_ZCD_VADZCDADJ(x) (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_ZCD_VADZCDADJ_SHIFT)) & PDM_VAD0_ZCD_VADZCDADJ_MASK) + +#define PDM_VAD0_ZCD_VADZCDTH_MASK (0x3FF0000U) +#define PDM_VAD0_ZCD_VADZCDTH_SHIFT (16U) +/*! VADZCDTH - ZCD Threshold */ +#define PDM_VAD0_ZCD_VADZCDTH(x) (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_ZCD_VADZCDTH_SHIFT)) & PDM_VAD0_ZCD_VADZCDTH_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group PDM_Register_Masks */ + + +/* PDM - Peripheral instance base addresses */ +/** Peripheral PDM base address */ +#define PDM_BASE (0x44520000u) +/** Peripheral PDM base pointer */ +#define PDM ((PDM_Type *)PDM_BASE) +/** Array initializer of PDM peripheral base addresses */ +#define PDM_BASE_ADDRS { PDM_BASE } +/** Array initializer of PDM peripheral base pointers */ +#define PDM_BASE_PTRS { PDM } + +/*! + * @} + */ /* end of group PDM_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- PLL Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PLL_Peripheral_Access_Layer PLL Peripheral Access Layer + * @{ + */ + +/** PLL - Register Layout Typedef */ +typedef struct { + struct { /* offset: 0x0 */ + __IO uint32_t RW; /**< PLL Control, offset: 0x0 */ + __IO uint32_t SET; /**< PLL Control, offset: 0x4 */ + __IO uint32_t CLR; /**< PLL Control, offset: 0x8 */ + __IO uint32_t TOG; /**< PLL Control, offset: 0xC */ + } CTRL; + uint8_t RESERVED_0[32]; + struct { /* offset: 0x30 */ + __IO uint32_t RW; /**< Spread Spectrum, offset: 0x30, available only on: AUDIOPLL, DRAMPLL, SYSPLL, VIDEOPLL (missing on ARMPLL) */ + __IO uint32_t SET; /**< Spread Spectrum, offset: 0x34, available only on: AUDIOPLL, DRAMPLL, SYSPLL, VIDEOPLL (missing on ARMPLL) */ + __IO uint32_t CLR; /**< Spread Spectrum, offset: 0x38, available only on: AUDIOPLL, DRAMPLL, SYSPLL, VIDEOPLL (missing on ARMPLL) */ + __IO uint32_t TOG; /**< Spread Spectrum, offset: 0x3C, available only on: AUDIOPLL, DRAMPLL, SYSPLL, VIDEOPLL (missing on ARMPLL) */ + } SPREAD_SPECTRUM; + struct { /* offset: 0x40 */ + __IO uint32_t RW; /**< Numerator, offset: 0x40, available only on: AUDIOPLL, DRAMPLL, SYSPLL, VIDEOPLL (missing on ARMPLL) */ + __IO uint32_t SET; /**< Numerator, offset: 0x44, available only on: AUDIOPLL, DRAMPLL, SYSPLL, VIDEOPLL (missing on ARMPLL) */ + __IO uint32_t CLR; /**< Numerator, offset: 0x48, available only on: AUDIOPLL, DRAMPLL, SYSPLL, VIDEOPLL (missing on ARMPLL) */ + __IO uint32_t TOG; /**< Numerator, offset: 0x4C, available only on: AUDIOPLL, DRAMPLL, SYSPLL, VIDEOPLL (missing on ARMPLL) */ + } NUMERATOR; + struct { /* offset: 0x50 */ + __IO uint32_t RW; /**< Denominator, offset: 0x50, available only on: AUDIOPLL, DRAMPLL, SYSPLL, VIDEOPLL (missing on ARMPLL) */ + __IO uint32_t SET; /**< Denominator, offset: 0x54, available only on: AUDIOPLL, DRAMPLL, SYSPLL, VIDEOPLL (missing on ARMPLL) */ + __IO uint32_t CLR; /**< Denominator, offset: 0x58, available only on: AUDIOPLL, DRAMPLL, SYSPLL, VIDEOPLL (missing on ARMPLL) */ + __IO uint32_t TOG; /**< Denominator, offset: 0x5C, available only on: AUDIOPLL, DRAMPLL, SYSPLL, VIDEOPLL (missing on ARMPLL) */ + } DENOMINATOR; + struct { /* offset: 0x60 */ + __IO uint32_t RW; /**< PLL Dividers, offset: 0x60 */ + __IO uint32_t SET; /**< PLL Dividers, offset: 0x64 */ + __IO uint32_t CLR; /**< PLL Dividers, offset: 0x68 */ + __IO uint32_t TOG; /**< PLL Dividers, offset: 0x6C */ + } DIV; + struct { /* offset: 0x70, array step: 0x20 */ + struct { /* offset: 0x70 */ + __IO uint32_t RW; /**< DFS Control, offset: 0x70, available only on: SYSPLL (missing on ARMPLL, AUDIOPLL, DRAMPLL, VIDEOPLL) */ + __IO uint32_t SET; /**< DFS Control, offset: 0x74, available only on: SYSPLL (missing on ARMPLL, AUDIOPLL, DRAMPLL, VIDEOPLL) */ + __IO uint32_t CLR; /**< DFS Control, offset: 0x78, available only on: SYSPLL (missing on ARMPLL, AUDIOPLL, DRAMPLL, VIDEOPLL) */ + __IO uint32_t TOG; /**< DFS Control, offset: 0x7C, available only on: SYSPLL (missing on ARMPLL, AUDIOPLL, DRAMPLL, VIDEOPLL) */ + } DFS_CTRL; + struct { /* offset: 0x80 */ + __IO uint32_t RW; /**< DFS Division_N, offset: 0x80, available only on: SYSPLL (missing on ARMPLL, AUDIOPLL, DRAMPLL, VIDEOPLL) */ + __IO uint32_t SET; /**< DFS Division_N, offset: 0x84, available only on: SYSPLL (missing on ARMPLL, AUDIOPLL, DRAMPLL, VIDEOPLL) */ + __IO uint32_t CLR; /**< DFS Division_N, offset: 0x88, available only on: SYSPLL (missing on ARMPLL, AUDIOPLL, DRAMPLL, VIDEOPLL) */ + __IO uint32_t TOG; /**< DFS Division_N, offset: 0x8C, available only on: SYSPLL (missing on ARMPLL, AUDIOPLL, DRAMPLL, VIDEOPLL) */ + } DFS_DIV; + } DFS[3]; + uint8_t RESERVED_1[32]; + __I uint32_t PLL_STATUS; /**< PLL Status, offset: 0xF0 */ + __I uint32_t DFS_STATUS; /**< DFS Status, offset: 0xF4, available only on: SYSPLL (missing on ARMPLL, AUDIOPLL, DRAMPLL, VIDEOPLL) */ +} PLL_Type; + +/* ---------------------------------------------------------------------------- + -- PLL Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PLL_Register_Masks PLL Register Masks + * @{ + */ + +/*! @name CTRL - PLL Control */ +/*! @{ */ + +#define PLL_CTRL_POWERUP_MASK (0x1U) +#define PLL_CTRL_POWERUP_SHIFT (0U) +/*! POWERUP - Power Up + * 0b0..Disable + * 0b1..Enable + */ +#define PLL_CTRL_POWERUP(x) (((uint32_t)(((uint32_t)(x)) << PLL_CTRL_POWERUP_SHIFT)) & PLL_CTRL_POWERUP_MASK) + +#define PLL_CTRL_CLKMUX_EN_MASK (0x2U) +#define PLL_CTRL_CLKMUX_EN_SHIFT (1U) +/*! CLKMUX_EN - CLKMUX Enable + * 0b0..Disable + * 0b1..Enable + */ +#define PLL_CTRL_CLKMUX_EN(x) (((uint32_t)(((uint32_t)(x)) << PLL_CTRL_CLKMUX_EN_SHIFT)) & PLL_CTRL_CLKMUX_EN_MASK) + +#define PLL_CTRL_CLKMUX_BYPASS_MASK (0x4U) +#define PLL_CTRL_CLKMUX_BYPASS_SHIFT (2U) +/*! CLKMUX_BYPASS - CLKMUX_Bypass + * 0b0..Normal mode + * 0b1..PLL Bypass mode + */ +#define PLL_CTRL_CLKMUX_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << PLL_CTRL_CLKMUX_BYPASS_SHIFT)) & PLL_CTRL_CLKMUX_BYPASS_MASK) + +#define PLL_CTRL_SPREADCTL_MASK (0x100U) +#define PLL_CTRL_SPREADCTL_SHIFT (8U) +/*! SPREADCTL - Modulation Type Select + * 0b0..Centered around nominal frequency + * 0b1..Spread below nominal frequency + */ +#define PLL_CTRL_SPREADCTL(x) (((uint32_t)(((uint32_t)(x)) << PLL_CTRL_SPREADCTL_SHIFT)) & PLL_CTRL_SPREADCTL_MASK) + +#define PLL_CTRL_HW_CTRL_SEL_MASK (0x10000U) +#define PLL_CTRL_HW_CTRL_SEL_SHIFT (16U) +/*! HW_CTRL_SEL - Hardware Control Select + * 0b0..Disable + * 0b1..Enable + */ +#define PLL_CTRL_HW_CTRL_SEL(x) (((uint32_t)(((uint32_t)(x)) << PLL_CTRL_HW_CTRL_SEL_SHIFT)) & PLL_CTRL_HW_CTRL_SEL_MASK) + +#define PLL_CTRL_LOCK_BYPASS_MASK (0x80000000U) +#define PLL_CTRL_LOCK_BYPASS_SHIFT (31U) +/*! LOCK_BYPASS - Lock Bypass + * 0b0..Disable + * 0b1..Enable + */ +#define PLL_CTRL_LOCK_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << PLL_CTRL_LOCK_BYPASS_SHIFT)) & PLL_CTRL_LOCK_BYPASS_MASK) +/*! @} */ + +/*! @name SPREAD_SPECTRUM - Spread Spectrum */ +/*! @{ */ + +#define PLL_SPREAD_SPECTRUM_STEP_MASK (0x7FFFU) +#define PLL_SPREAD_SPECTRUM_STEP_SHIFT (0U) +/*! STEP - Step */ +#define PLL_SPREAD_SPECTRUM_STEP(x) (((uint32_t)(((uint32_t)(x)) << PLL_SPREAD_SPECTRUM_STEP_SHIFT)) & PLL_SPREAD_SPECTRUM_STEP_MASK) + +#define PLL_SPREAD_SPECTRUM_ENABLE_MASK (0x8000U) +#define PLL_SPREAD_SPECTRUM_ENABLE_SHIFT (15U) +/*! ENABLE - Enable + * 0b0..Disable + * 0b1..Enable + */ +#define PLL_SPREAD_SPECTRUM_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PLL_SPREAD_SPECTRUM_ENABLE_SHIFT)) & PLL_SPREAD_SPECTRUM_ENABLE_MASK) + +#define PLL_SPREAD_SPECTRUM_STOP_MASK (0xFFFF0000U) +#define PLL_SPREAD_SPECTRUM_STOP_SHIFT (16U) +/*! STOP - Stop */ +#define PLL_SPREAD_SPECTRUM_STOP(x) (((uint32_t)(((uint32_t)(x)) << PLL_SPREAD_SPECTRUM_STOP_SHIFT)) & PLL_SPREAD_SPECTRUM_STOP_MASK) +/*! @} */ + +/*! @name NUMERATOR - Numerator */ +/*! @{ */ + +#define PLL_NUMERATOR_MFN_MASK (0xFFFFFFFCU) +#define PLL_NUMERATOR_MFN_SHIFT (2U) +/*! MFN - Numerator */ +#define PLL_NUMERATOR_MFN(x) (((uint32_t)(((uint32_t)(x)) << PLL_NUMERATOR_MFN_SHIFT)) & PLL_NUMERATOR_MFN_MASK) +/*! @} */ + +/*! @name DENOMINATOR - Denominator */ +/*! @{ */ + +#define PLL_DENOMINATOR_MFD_MASK (0x3FFFFFFFU) +#define PLL_DENOMINATOR_MFD_SHIFT (0U) +/*! MFD - Denominator */ +#define PLL_DENOMINATOR_MFD(x) (((uint32_t)(((uint32_t)(x)) << PLL_DENOMINATOR_MFD_SHIFT)) & PLL_DENOMINATOR_MFD_MASK) +/*! @} */ + +/*! @name DIV - PLL Dividers */ +/*! @{ */ + +#define PLL_DIV_ODIV_MASK (0xFFU) +#define PLL_DIV_ODIV_SHIFT (0U) +/*! ODIV - Output Frequency Divider for Clock Output + * 0b00000000..Divide by 2 + * 0b00000001..Divide by 3 + * 0b00000010..Divide by 2 + * 0b00000011..Divide by 3 + * 0b00000100..Divide by 4 + * 0b00000101..Divide by 5 + * 0b00000110..Divide by 6 + * 0b00001010..Divide by 10 + * 0b10000010..Divide by 130 + * 0b11111111..Divide by 255 + */ +#define PLL_DIV_ODIV(x) (((uint32_t)(((uint32_t)(x)) << PLL_DIV_ODIV_SHIFT)) & PLL_DIV_ODIV_MASK) + +#define PLL_DIV_RDIV_MASK (0xE000U) +#define PLL_DIV_RDIV_SHIFT (13U) +/*! RDIV - Input Clock Predivider + * 0b000..Divide by 1 + * 0b001..Divide by 1 + * 0b010..Divide by 2 + * 0b011..Divide by 3 + * 0b100..Divide by 4 + * 0b101..Divide by 5 + * 0b110..Divide by 6 + * 0b111..Divide by 7 + */ +#define PLL_DIV_RDIV(x) (((uint32_t)(((uint32_t)(x)) << PLL_DIV_RDIV_SHIFT)) & PLL_DIV_RDIV_MASK) + +#define PLL_DIV_MFI_MASK (0x1FF0000U) +#define PLL_DIV_MFI_SHIFT (16U) +/*! MFI - Integer Portion of Loop Divider */ +#define PLL_DIV_MFI(x) (((uint32_t)(((uint32_t)(x)) << PLL_DIV_MFI_SHIFT)) & PLL_DIV_MFI_MASK) +/*! @} */ + +/*! @name DFS - DFS Control */ +/*! @{ */ + +#define PLL_DFS_HW_CTRL_SEL_MASK (0x10000U) +#define PLL_DFS_HW_CTRL_SEL_SHIFT (16U) +/*! HW_CTRL_SEL - Hardware Control Select + * 0b0..Controlled by register + * 0b1..Controlled by hardware inputs + */ +#define PLL_DFS_HW_CTRL_SEL(x) (((uint32_t)(((uint32_t)(x)) << PLL_DFS_HW_CTRL_SEL_SHIFT)) & PLL_DFS_HW_CTRL_SEL_MASK) + +#define PLL_DFS_BYPASS_EN_MASK (0x800000U) +#define PLL_DFS_BYPASS_EN_SHIFT (23U) +/*! BYPASS_EN - Bypass Enable + * 0b0..Disable + * 0b1..Enable + */ +#define PLL_DFS_BYPASS_EN(x) (((uint32_t)(((uint32_t)(x)) << PLL_DFS_BYPASS_EN_SHIFT)) & PLL_DFS_BYPASS_EN_MASK) + +#define PLL_DFS_CLKOUT_DIVBY2_EN_MASK (0x20000000U) +#define PLL_DFS_CLKOUT_DIVBY2_EN_SHIFT (29U) +/*! CLKOUT_DIVBY2_EN - DFS Clock Output Divide by 2 Enable + * 0b0..Disable + * 0b1..Enable + */ +#define PLL_DFS_CLKOUT_DIVBY2_EN(x) (((uint32_t)(((uint32_t)(x)) << PLL_DFS_CLKOUT_DIVBY2_EN_SHIFT)) & PLL_DFS_CLKOUT_DIVBY2_EN_MASK) + +#define PLL_DFS_CLKOUT_EN_MASK (0x40000000U) +#define PLL_DFS_CLKOUT_EN_SHIFT (30U) +/*! CLKOUT_EN - DFS Clock Output Enable + * 0b0..Disable + * 0b1..Enable + */ +#define PLL_DFS_CLKOUT_EN(x) (((uint32_t)(((uint32_t)(x)) << PLL_DFS_CLKOUT_EN_SHIFT)) & PLL_DFS_CLKOUT_EN_MASK) + +#define PLL_DFS_ENABLE_MASK (0x80000000U) +#define PLL_DFS_ENABLE_SHIFT (31U) +/*! ENABLE - DFS Block Enable + * 0b0..Disable + * 0b1..Enable + */ +#define PLL_DFS_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PLL_DFS_ENABLE_SHIFT)) & PLL_DFS_ENABLE_MASK) +/*! @} */ + +/*! @name DFS - DFS Division_N */ +/*! @{ */ + +#define PLL_DFS_MFN_MASK (0x7U) +#define PLL_DFS_MFN_SHIFT (0U) +/*! MFN - MFN */ +#define PLL_DFS_MFN(x) (((uint32_t)(((uint32_t)(x)) << PLL_DFS_MFN_SHIFT)) & PLL_DFS_MFN_MASK) + +#define PLL_DFS_MFI_MASK (0xFF00U) +#define PLL_DFS_MFI_SHIFT (8U) +/*! MFI - MFI */ +#define PLL_DFS_MFI(x) (((uint32_t)(((uint32_t)(x)) << PLL_DFS_MFI_SHIFT)) & PLL_DFS_MFI_MASK) +/*! @} */ + +/*! @name PLL_STATUS - PLL Status */ +/*! @{ */ + +#define PLL_PLL_STATUS_PLL_LOCK_MASK (0x1U) +#define PLL_PLL_STATUS_PLL_LOCK_SHIFT (0U) +/*! PLL_LOCK - PLL_LOCK */ +#define PLL_PLL_STATUS_PLL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << PLL_PLL_STATUS_PLL_LOCK_SHIFT)) & PLL_PLL_STATUS_PLL_LOCK_MASK) + +#define PLL_PLL_STATUS_PLL_LOL_MASK (0x2U) +#define PLL_PLL_STATUS_PLL_LOL_SHIFT (1U) +/*! PLL_LOL - PLL_LOL */ +#define PLL_PLL_STATUS_PLL_LOL(x) (((uint32_t)(((uint32_t)(x)) << PLL_PLL_STATUS_PLL_LOL_SHIFT)) & PLL_PLL_STATUS_PLL_LOL_MASK) + +#define PLL_PLL_STATUS_ANA_MFN_MASK (0xFFFFFFFCU) +#define PLL_PLL_STATUS_ANA_MFN_SHIFT (2U) +/*! ANA_MFN - ANA_MFN */ +#define PLL_PLL_STATUS_ANA_MFN(x) (((uint32_t)(((uint32_t)(x)) << PLL_PLL_STATUS_ANA_MFN_SHIFT)) & PLL_PLL_STATUS_ANA_MFN_MASK) +/*! @} */ + +/*! @name DFS_STATUS - DFS Status */ +/*! @{ */ + +#define PLL_DFS_STATUS_DFS_OK_MASK (0x7U) +#define PLL_DFS_STATUS_DFS_OK_SHIFT (0U) +/*! DFS_OK - DFS OK + * 0b000..Invalid + * 0b001..Valid + */ +#define PLL_DFS_STATUS_DFS_OK(x) (((uint32_t)(((uint32_t)(x)) << PLL_DFS_STATUS_DFS_OK_SHIFT)) & PLL_DFS_STATUS_DFS_OK_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group PLL_Register_Masks */ + + +/* PLL - Peripheral instance base addresses */ +/** Peripheral ARMPLL base address */ +#define ARMPLL_BASE (0x44481000u) +/** Peripheral ARMPLL base pointer */ +#define ARMPLL ((PLL_Type *)ARMPLL_BASE) +/** Peripheral AUDIOPLL base address */ +#define AUDIOPLL_BASE (0x44481200u) +/** Peripheral AUDIOPLL base pointer */ +#define AUDIOPLL ((PLL_Type *)AUDIOPLL_BASE) +/** Peripheral DRAMPLL base address */ +#define DRAMPLL_BASE (0x44481300u) +/** Peripheral DRAMPLL base pointer */ +#define DRAMPLL ((PLL_Type *)DRAMPLL_BASE) +/** Peripheral SYSPLL base address */ +#define SYSPLL_BASE (0x44481100u) +/** Peripheral SYSPLL base pointer */ +#define SYSPLL ((PLL_Type *)SYSPLL_BASE) +/** Peripheral VIDEOPLL base address */ +#define VIDEOPLL_BASE (0x44481400u) +/** Peripheral VIDEOPLL base pointer */ +#define VIDEOPLL ((PLL_Type *)VIDEOPLL_BASE) +/** Array initializer of PLL peripheral base addresses */ +#define PLL_BASE_ADDRS { ARMPLL_BASE, AUDIOPLL_BASE, DRAMPLL_BASE, SYSPLL_BASE, VIDEOPLL_BASE } +/** Array initializer of PLL peripheral base pointers */ +#define PLL_BASE_PTRS { ARMPLL, AUDIOPLL, DRAMPLL, SYSPLL, VIDEOPLL } + +/*! + * @} + */ /* end of group PLL_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- RGPIO Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup RGPIO_Peripheral_Access_Layer RGPIO Peripheral Access Layer + * @{ + */ + +/** RGPIO - Register Layout Typedef */ +typedef struct { + __I uint32_t VERID; /**< Version ID, offset: 0x0 */ + __I uint32_t PARAM; /**< Parameter, offset: 0x4 */ + uint8_t RESERVED_0[4]; + __IO uint32_t LOCK; /**< Lock, offset: 0xC */ + __IO uint32_t PCNS; /**< Pin Control Nonsecure, offset: 0x10 */ + __IO uint32_t ICNS; /**< Interrupt Control Nonsecure, offset: 0x14 */ + __IO uint32_t PCNP; /**< Pin Control Nonprivilege, offset: 0x18 */ + __IO uint32_t ICNP; /**< Interrupt Control Nonprivilege, offset: 0x1C */ + uint8_t RESERVED_1[32]; + __IO uint32_t PDOR; /**< Port Data Output, offset: 0x40 */ + __IO uint32_t PSOR; /**< Port Set Output, offset: 0x44 */ + __IO uint32_t PCOR; /**< Port Clear Output, offset: 0x48 */ + __IO uint32_t PTOR; /**< Port Toggle Output, offset: 0x4C */ + __I uint32_t PDIR; /**< Port Data Input, offset: 0x50 */ + __IO uint32_t PDDR; /**< Port Data Direction, offset: 0x54 */ + __IO uint32_t PIDR; /**< Port Input Disable, offset: 0x58 */ + uint8_t RESERVED_2[4]; + __IO uint8_t PDR[32]; /**< Pin Data, array offset: 0x60, array step: 0x1 */ + __IO uint32_t ICR[32]; /**< Interrupt Control 0..Interrupt Control 31, array offset: 0x80, array step: 0x4 */ + __IO uint32_t GICLR; /**< Global Interrupt Control Low, offset: 0x100 */ + __IO uint32_t GICHR; /**< Global Interrupt Control High, offset: 0x104 */ + uint8_t RESERVED_3[24]; + __IO uint32_t ISFR[2]; /**< Interrupt Status Flag, array offset: 0x120, array step: 0x4 */ +} RGPIO_Type; + +/* ---------------------------------------------------------------------------- + -- RGPIO Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup RGPIO_Register_Masks RGPIO Register Masks + * @{ + */ + +/*! @name VERID - Version ID */ +/*! @{ */ + +#define RGPIO_VERID_FEATURE_MASK (0xFFFFU) +#define RGPIO_VERID_FEATURE_SHIFT (0U) +/*! FEATURE - Feature Specification Number + * 0b0000000000000000..Basic implementation + * 0b0000000000000001..Protection registers implemented + */ +#define RGPIO_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_VERID_FEATURE_SHIFT)) & RGPIO_VERID_FEATURE_MASK) + +#define RGPIO_VERID_MINOR_MASK (0xFF0000U) +#define RGPIO_VERID_MINOR_SHIFT (16U) +/*! MINOR - Minor Version Number */ +#define RGPIO_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_VERID_MINOR_SHIFT)) & RGPIO_VERID_MINOR_MASK) + +#define RGPIO_VERID_MAJOR_MASK (0xFF000000U) +#define RGPIO_VERID_MAJOR_SHIFT (24U) +/*! MAJOR - Major Version Number */ +#define RGPIO_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_VERID_MAJOR_SHIFT)) & RGPIO_VERID_MAJOR_MASK) +/*! @} */ + +/*! @name PARAM - Parameter */ +/*! @{ */ + +#define RGPIO_PARAM_IRQNUM_MASK (0xFU) +#define RGPIO_PARAM_IRQNUM_SHIFT (0U) +/*! IRQNUM - Interrupt Number */ +#define RGPIO_PARAM_IRQNUM(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PARAM_IRQNUM_SHIFT)) & RGPIO_PARAM_IRQNUM_MASK) +/*! @} */ + +/*! @name LOCK - Lock */ +/*! @{ */ + +#define RGPIO_LOCK_PCNS_MASK (0x1U) +#define RGPIO_LOCK_PCNS_SHIFT (0U) +/*! PCNS - Lock PCNS + * 0b0..Writable in Secure-Privilege state + * 0b1..Not writable until the next reset + */ +#define RGPIO_LOCK_PCNS(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_LOCK_PCNS_SHIFT)) & RGPIO_LOCK_PCNS_MASK) + +#define RGPIO_LOCK_ICNS_MASK (0x2U) +#define RGPIO_LOCK_ICNS_SHIFT (1U) +/*! ICNS - Lock ICNS + * 0b0..Writable in Secure-Privilege state + * 0b1..Not writable until the next reset + */ +#define RGPIO_LOCK_ICNS(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_LOCK_ICNS_SHIFT)) & RGPIO_LOCK_ICNS_MASK) + +#define RGPIO_LOCK_PCNP_MASK (0x4U) +#define RGPIO_LOCK_PCNP_SHIFT (2U) +/*! PCNP - Lock PCNP + * 0b0..Writable in Secure-Privilege state + * 0b1..Not writable until the next reset + */ +#define RGPIO_LOCK_PCNP(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_LOCK_PCNP_SHIFT)) & RGPIO_LOCK_PCNP_MASK) + +#define RGPIO_LOCK_ICNP_MASK (0x8U) +#define RGPIO_LOCK_ICNP_SHIFT (3U) +/*! ICNP - Lock ICNP + * 0b0..Writable in Secure-Privilege state + * 0b1..Not writable until the next reset + */ +#define RGPIO_LOCK_ICNP(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_LOCK_ICNP_SHIFT)) & RGPIO_LOCK_ICNP_MASK) +/*! @} */ + +/*! @name PCNS - Pin Control Nonsecure */ +/*! @{ */ + +#define RGPIO_PCNS_NSE0_MASK (0x1U) +#define RGPIO_PCNS_NSE0_SHIFT (0U) +/*! NSE0 - Nonsecure Enable + * 0b0..Secure access + * 0b1..Nonsecure access + */ +#define RGPIO_PCNS_NSE0(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNS_NSE0_SHIFT)) & RGPIO_PCNS_NSE0_MASK) + +#define RGPIO_PCNS_NSE1_MASK (0x2U) +#define RGPIO_PCNS_NSE1_SHIFT (1U) +/*! NSE1 - Nonsecure Enable + * 0b0..Secure access + * 0b1..Nonsecure access + */ +#define RGPIO_PCNS_NSE1(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNS_NSE1_SHIFT)) & RGPIO_PCNS_NSE1_MASK) + +#define RGPIO_PCNS_NSE2_MASK (0x4U) +#define RGPIO_PCNS_NSE2_SHIFT (2U) +/*! NSE2 - Nonsecure Enable + * 0b0..Secure access + * 0b1..Nonsecure access + */ +#define RGPIO_PCNS_NSE2(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNS_NSE2_SHIFT)) & RGPIO_PCNS_NSE2_MASK) + +#define RGPIO_PCNS_NSE3_MASK (0x8U) +#define RGPIO_PCNS_NSE3_SHIFT (3U) +/*! NSE3 - Nonsecure Enable + * 0b0..Secure access + * 0b1..Nonsecure access + */ +#define RGPIO_PCNS_NSE3(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNS_NSE3_SHIFT)) & RGPIO_PCNS_NSE3_MASK) + +#define RGPIO_PCNS_NSE4_MASK (0x10U) +#define RGPIO_PCNS_NSE4_SHIFT (4U) +/*! NSE4 - Nonsecure Enable + * 0b0..Secure access + * 0b1..Nonsecure access + */ +#define RGPIO_PCNS_NSE4(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNS_NSE4_SHIFT)) & RGPIO_PCNS_NSE4_MASK) + +#define RGPIO_PCNS_NSE5_MASK (0x20U) +#define RGPIO_PCNS_NSE5_SHIFT (5U) +/*! NSE5 - Nonsecure Enable + * 0b0..Secure access + * 0b1..Nonsecure access + */ +#define RGPIO_PCNS_NSE5(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNS_NSE5_SHIFT)) & RGPIO_PCNS_NSE5_MASK) + +#define RGPIO_PCNS_NSE6_MASK (0x40U) +#define RGPIO_PCNS_NSE6_SHIFT (6U) +/*! NSE6 - Nonsecure Enable + * 0b0..Secure access + * 0b1..Nonsecure access + */ +#define RGPIO_PCNS_NSE6(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNS_NSE6_SHIFT)) & RGPIO_PCNS_NSE6_MASK) + +#define RGPIO_PCNS_NSE7_MASK (0x80U) +#define RGPIO_PCNS_NSE7_SHIFT (7U) +/*! NSE7 - Nonsecure Enable + * 0b0..Secure access + * 0b1..Nonsecure access + */ +#define RGPIO_PCNS_NSE7(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNS_NSE7_SHIFT)) & RGPIO_PCNS_NSE7_MASK) + +#define RGPIO_PCNS_NSE8_MASK (0x100U) +#define RGPIO_PCNS_NSE8_SHIFT (8U) +/*! NSE8 - Nonsecure Enable + * 0b0..Secure access + * 0b1..Nonsecure access + */ +#define RGPIO_PCNS_NSE8(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNS_NSE8_SHIFT)) & RGPIO_PCNS_NSE8_MASK) + +#define RGPIO_PCNS_NSE9_MASK (0x200U) +#define RGPIO_PCNS_NSE9_SHIFT (9U) +/*! NSE9 - Nonsecure Enable + * 0b0..Secure access + * 0b1..Nonsecure access + */ +#define RGPIO_PCNS_NSE9(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNS_NSE9_SHIFT)) & RGPIO_PCNS_NSE9_MASK) + +#define RGPIO_PCNS_NSE10_MASK (0x400U) +#define RGPIO_PCNS_NSE10_SHIFT (10U) +/*! NSE10 - Nonsecure Enable + * 0b0..Secure access + * 0b1..Nonsecure access + */ +#define RGPIO_PCNS_NSE10(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNS_NSE10_SHIFT)) & RGPIO_PCNS_NSE10_MASK) + +#define RGPIO_PCNS_NSE11_MASK (0x800U) +#define RGPIO_PCNS_NSE11_SHIFT (11U) +/*! NSE11 - Nonsecure Enable + * 0b0..Secure access + * 0b1..Nonsecure access + */ +#define RGPIO_PCNS_NSE11(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNS_NSE11_SHIFT)) & RGPIO_PCNS_NSE11_MASK) + +#define RGPIO_PCNS_NSE12_MASK (0x1000U) +#define RGPIO_PCNS_NSE12_SHIFT (12U) +/*! NSE12 - Nonsecure Enable + * 0b0..Secure access + * 0b1..Nonsecure access + */ +#define RGPIO_PCNS_NSE12(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNS_NSE12_SHIFT)) & RGPIO_PCNS_NSE12_MASK) + +#define RGPIO_PCNS_NSE13_MASK (0x2000U) +#define RGPIO_PCNS_NSE13_SHIFT (13U) +/*! NSE13 - Nonsecure Enable + * 0b0..Secure access + * 0b1..Nonsecure access + */ +#define RGPIO_PCNS_NSE13(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNS_NSE13_SHIFT)) & RGPIO_PCNS_NSE13_MASK) + +#define RGPIO_PCNS_NSE14_MASK (0x4000U) +#define RGPIO_PCNS_NSE14_SHIFT (14U) +/*! NSE14 - Nonsecure Enable + * 0b0..Secure access + * 0b1..Nonsecure access + */ +#define RGPIO_PCNS_NSE14(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNS_NSE14_SHIFT)) & RGPIO_PCNS_NSE14_MASK) + +#define RGPIO_PCNS_NSE15_MASK (0x8000U) +#define RGPIO_PCNS_NSE15_SHIFT (15U) +/*! NSE15 - Nonsecure Enable + * 0b0..Secure access + * 0b1..Nonsecure access + */ +#define RGPIO_PCNS_NSE15(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNS_NSE15_SHIFT)) & RGPIO_PCNS_NSE15_MASK) + +#define RGPIO_PCNS_NSE16_MASK (0x10000U) +#define RGPIO_PCNS_NSE16_SHIFT (16U) +/*! NSE16 - Nonsecure Enable + * 0b0..Secure access + * 0b1..Nonsecure access + */ +#define RGPIO_PCNS_NSE16(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNS_NSE16_SHIFT)) & RGPIO_PCNS_NSE16_MASK) + +#define RGPIO_PCNS_NSE17_MASK (0x20000U) +#define RGPIO_PCNS_NSE17_SHIFT (17U) +/*! NSE17 - Nonsecure Enable + * 0b0..Secure access + * 0b1..Nonsecure access + */ +#define RGPIO_PCNS_NSE17(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNS_NSE17_SHIFT)) & RGPIO_PCNS_NSE17_MASK) + +#define RGPIO_PCNS_NSE18_MASK (0x40000U) +#define RGPIO_PCNS_NSE18_SHIFT (18U) +/*! NSE18 - Nonsecure Enable + * 0b0..Secure access + * 0b1..Nonsecure access + */ +#define RGPIO_PCNS_NSE18(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNS_NSE18_SHIFT)) & RGPIO_PCNS_NSE18_MASK) + +#define RGPIO_PCNS_NSE19_MASK (0x80000U) +#define RGPIO_PCNS_NSE19_SHIFT (19U) +/*! NSE19 - Nonsecure Enable + * 0b0..Secure access + * 0b1..Nonsecure access + */ +#define RGPIO_PCNS_NSE19(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNS_NSE19_SHIFT)) & RGPIO_PCNS_NSE19_MASK) + +#define RGPIO_PCNS_NSE20_MASK (0x100000U) +#define RGPIO_PCNS_NSE20_SHIFT (20U) +/*! NSE20 - Nonsecure Enable + * 0b0..Secure access + * 0b1..Nonsecure access + */ +#define RGPIO_PCNS_NSE20(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNS_NSE20_SHIFT)) & RGPIO_PCNS_NSE20_MASK) + +#define RGPIO_PCNS_NSE21_MASK (0x200000U) +#define RGPIO_PCNS_NSE21_SHIFT (21U) +/*! NSE21 - Nonsecure Enable + * 0b0..Secure access + * 0b1..Nonsecure access + */ +#define RGPIO_PCNS_NSE21(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNS_NSE21_SHIFT)) & RGPIO_PCNS_NSE21_MASK) + +#define RGPIO_PCNS_NSE22_MASK (0x400000U) +#define RGPIO_PCNS_NSE22_SHIFT (22U) +/*! NSE22 - Nonsecure Enable + * 0b0..Secure access + * 0b1..Nonsecure access + */ +#define RGPIO_PCNS_NSE22(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNS_NSE22_SHIFT)) & RGPIO_PCNS_NSE22_MASK) + +#define RGPIO_PCNS_NSE23_MASK (0x800000U) +#define RGPIO_PCNS_NSE23_SHIFT (23U) +/*! NSE23 - Nonsecure Enable + * 0b0..Secure access + * 0b1..Nonsecure access + */ +#define RGPIO_PCNS_NSE23(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNS_NSE23_SHIFT)) & RGPIO_PCNS_NSE23_MASK) + +#define RGPIO_PCNS_NSE24_MASK (0x1000000U) +#define RGPIO_PCNS_NSE24_SHIFT (24U) +/*! NSE24 - Nonsecure Enable + * 0b0..Secure access + * 0b1..Nonsecure access + */ +#define RGPIO_PCNS_NSE24(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNS_NSE24_SHIFT)) & RGPIO_PCNS_NSE24_MASK) + +#define RGPIO_PCNS_NSE25_MASK (0x2000000U) +#define RGPIO_PCNS_NSE25_SHIFT (25U) +/*! NSE25 - Nonsecure Enable + * 0b0..Secure access + * 0b1..Nonsecure access + */ +#define RGPIO_PCNS_NSE25(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNS_NSE25_SHIFT)) & RGPIO_PCNS_NSE25_MASK) + +#define RGPIO_PCNS_NSE26_MASK (0x4000000U) +#define RGPIO_PCNS_NSE26_SHIFT (26U) +/*! NSE26 - Nonsecure Enable + * 0b0..Secure access + * 0b1..Nonsecure access + */ +#define RGPIO_PCNS_NSE26(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNS_NSE26_SHIFT)) & RGPIO_PCNS_NSE26_MASK) + +#define RGPIO_PCNS_NSE27_MASK (0x8000000U) +#define RGPIO_PCNS_NSE27_SHIFT (27U) +/*! NSE27 - Nonsecure Enable + * 0b0..Secure access + * 0b1..Nonsecure access + */ +#define RGPIO_PCNS_NSE27(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNS_NSE27_SHIFT)) & RGPIO_PCNS_NSE27_MASK) + +#define RGPIO_PCNS_NSE28_MASK (0x10000000U) +#define RGPIO_PCNS_NSE28_SHIFT (28U) +/*! NSE28 - Nonsecure Enable + * 0b0..Secure access + * 0b1..Nonsecure access + */ +#define RGPIO_PCNS_NSE28(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNS_NSE28_SHIFT)) & RGPIO_PCNS_NSE28_MASK) + +#define RGPIO_PCNS_NSE29_MASK (0x20000000U) +#define RGPIO_PCNS_NSE29_SHIFT (29U) +/*! NSE29 - Nonsecure Enable + * 0b0..Secure access + * 0b1..Nonsecure access + */ +#define RGPIO_PCNS_NSE29(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNS_NSE29_SHIFT)) & RGPIO_PCNS_NSE29_MASK) + +#define RGPIO_PCNS_NSE30_MASK (0x40000000U) +#define RGPIO_PCNS_NSE30_SHIFT (30U) +/*! NSE30 - Nonsecure Enable + * 0b0..Secure access + * 0b1..Nonsecure access + */ +#define RGPIO_PCNS_NSE30(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNS_NSE30_SHIFT)) & RGPIO_PCNS_NSE30_MASK) + +#define RGPIO_PCNS_NSE31_MASK (0x80000000U) +#define RGPIO_PCNS_NSE31_SHIFT (31U) +/*! NSE31 - Nonsecure Enable + * 0b0..Secure access + * 0b1..Nonsecure access + */ +#define RGPIO_PCNS_NSE31(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNS_NSE31_SHIFT)) & RGPIO_PCNS_NSE31_MASK) +/*! @} */ + +/*! @name ICNS - Interrupt Control Nonsecure */ +/*! @{ */ + +#define RGPIO_ICNS_NSE0_MASK (0x1U) +#define RGPIO_ICNS_NSE0_SHIFT (0U) +/*! NSE0 - Nonsecure Enable + * 0b0..Secure access + * 0b1..Nonsecure access + */ +#define RGPIO_ICNS_NSE0(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_ICNS_NSE0_SHIFT)) & RGPIO_ICNS_NSE0_MASK) + +#define RGPIO_ICNS_NSE1_MASK (0x2U) +#define RGPIO_ICNS_NSE1_SHIFT (1U) +/*! NSE1 - Nonsecure Enable + * 0b0..Secure access + * 0b1..Nonsecure access + */ +#define RGPIO_ICNS_NSE1(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_ICNS_NSE1_SHIFT)) & RGPIO_ICNS_NSE1_MASK) +/*! @} */ + +/*! @name PCNP - Pin Control Nonprivilege */ +/*! @{ */ + +#define RGPIO_PCNP_NPE0_MASK (0x1U) +#define RGPIO_PCNP_NPE0_SHIFT (0U) +/*! NPE0 - Nonprivilege Enable + * 0b0..Privilege access + * 0b1..Nonprivilege access + */ +#define RGPIO_PCNP_NPE0(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNP_NPE0_SHIFT)) & RGPIO_PCNP_NPE0_MASK) + +#define RGPIO_PCNP_NPE1_MASK (0x2U) +#define RGPIO_PCNP_NPE1_SHIFT (1U) +/*! NPE1 - Nonprivilege Enable + * 0b0..Privilege access + * 0b1..Nonprivilege access + */ +#define RGPIO_PCNP_NPE1(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNP_NPE1_SHIFT)) & RGPIO_PCNP_NPE1_MASK) + +#define RGPIO_PCNP_NPE2_MASK (0x4U) +#define RGPIO_PCNP_NPE2_SHIFT (2U) +/*! NPE2 - Nonprivilege Enable + * 0b0..Privilege access + * 0b1..Nonprivilege access + */ +#define RGPIO_PCNP_NPE2(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNP_NPE2_SHIFT)) & RGPIO_PCNP_NPE2_MASK) + +#define RGPIO_PCNP_NPE3_MASK (0x8U) +#define RGPIO_PCNP_NPE3_SHIFT (3U) +/*! NPE3 - Nonprivilege Enable + * 0b0..Privilege access + * 0b1..Nonprivilege access + */ +#define RGPIO_PCNP_NPE3(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNP_NPE3_SHIFT)) & RGPIO_PCNP_NPE3_MASK) + +#define RGPIO_PCNP_NPE4_MASK (0x10U) +#define RGPIO_PCNP_NPE4_SHIFT (4U) +/*! NPE4 - Nonprivilege Enable + * 0b0..Privilege access + * 0b1..Nonprivilege access + */ +#define RGPIO_PCNP_NPE4(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNP_NPE4_SHIFT)) & RGPIO_PCNP_NPE4_MASK) + +#define RGPIO_PCNP_NPE5_MASK (0x20U) +#define RGPIO_PCNP_NPE5_SHIFT (5U) +/*! NPE5 - Nonprivilege Enable + * 0b0..Privilege access + * 0b1..Nonprivilege access + */ +#define RGPIO_PCNP_NPE5(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNP_NPE5_SHIFT)) & RGPIO_PCNP_NPE5_MASK) + +#define RGPIO_PCNP_NPE6_MASK (0x40U) +#define RGPIO_PCNP_NPE6_SHIFT (6U) +/*! NPE6 - Nonprivilege Enable + * 0b0..Privilege access + * 0b1..Nonprivilege access + */ +#define RGPIO_PCNP_NPE6(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNP_NPE6_SHIFT)) & RGPIO_PCNP_NPE6_MASK) + +#define RGPIO_PCNP_NPE7_MASK (0x80U) +#define RGPIO_PCNP_NPE7_SHIFT (7U) +/*! NPE7 - Nonprivilege Enable + * 0b0..Privilege access + * 0b1..Nonprivilege access + */ +#define RGPIO_PCNP_NPE7(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNP_NPE7_SHIFT)) & RGPIO_PCNP_NPE7_MASK) + +#define RGPIO_PCNP_NPE8_MASK (0x100U) +#define RGPIO_PCNP_NPE8_SHIFT (8U) +/*! NPE8 - Nonprivilege Enable + * 0b0..Privilege access + * 0b1..Nonprivilege access + */ +#define RGPIO_PCNP_NPE8(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNP_NPE8_SHIFT)) & RGPIO_PCNP_NPE8_MASK) + +#define RGPIO_PCNP_NPE9_MASK (0x200U) +#define RGPIO_PCNP_NPE9_SHIFT (9U) +/*! NPE9 - Nonprivilege Enable + * 0b0..Privilege access + * 0b1..Nonprivilege access + */ +#define RGPIO_PCNP_NPE9(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNP_NPE9_SHIFT)) & RGPIO_PCNP_NPE9_MASK) + +#define RGPIO_PCNP_NPE10_MASK (0x400U) +#define RGPIO_PCNP_NPE10_SHIFT (10U) +/*! NPE10 - Nonprivilege Enable + * 0b0..Privilege access + * 0b1..Nonprivilege access + */ +#define RGPIO_PCNP_NPE10(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNP_NPE10_SHIFT)) & RGPIO_PCNP_NPE10_MASK) + +#define RGPIO_PCNP_NPE11_MASK (0x800U) +#define RGPIO_PCNP_NPE11_SHIFT (11U) +/*! NPE11 - Nonprivilege Enable + * 0b0..Privilege access + * 0b1..Nonprivilege access + */ +#define RGPIO_PCNP_NPE11(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNP_NPE11_SHIFT)) & RGPIO_PCNP_NPE11_MASK) + +#define RGPIO_PCNP_NPE12_MASK (0x1000U) +#define RGPIO_PCNP_NPE12_SHIFT (12U) +/*! NPE12 - Nonprivilege Enable + * 0b0..Privilege access + * 0b1..Nonprivilege access + */ +#define RGPIO_PCNP_NPE12(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNP_NPE12_SHIFT)) & RGPIO_PCNP_NPE12_MASK) + +#define RGPIO_PCNP_NPE13_MASK (0x2000U) +#define RGPIO_PCNP_NPE13_SHIFT (13U) +/*! NPE13 - Nonprivilege Enable + * 0b0..Privilege access + * 0b1..Nonprivilege access + */ +#define RGPIO_PCNP_NPE13(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNP_NPE13_SHIFT)) & RGPIO_PCNP_NPE13_MASK) + +#define RGPIO_PCNP_NPE14_MASK (0x4000U) +#define RGPIO_PCNP_NPE14_SHIFT (14U) +/*! NPE14 - Nonprivilege Enable + * 0b0..Privilege access + * 0b1..Nonprivilege access + */ +#define RGPIO_PCNP_NPE14(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNP_NPE14_SHIFT)) & RGPIO_PCNP_NPE14_MASK) + +#define RGPIO_PCNP_NPE15_MASK (0x8000U) +#define RGPIO_PCNP_NPE15_SHIFT (15U) +/*! NPE15 - Nonprivilege Enable + * 0b0..Privilege access + * 0b1..Nonprivilege access + */ +#define RGPIO_PCNP_NPE15(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNP_NPE15_SHIFT)) & RGPIO_PCNP_NPE15_MASK) + +#define RGPIO_PCNP_NPE16_MASK (0x10000U) +#define RGPIO_PCNP_NPE16_SHIFT (16U) +/*! NPE16 - Nonprivilege Enable + * 0b0..Privilege access + * 0b1..Nonprivilege access + */ +#define RGPIO_PCNP_NPE16(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNP_NPE16_SHIFT)) & RGPIO_PCNP_NPE16_MASK) + +#define RGPIO_PCNP_NPE17_MASK (0x20000U) +#define RGPIO_PCNP_NPE17_SHIFT (17U) +/*! NPE17 - Nonprivilege Enable + * 0b0..Privilege access + * 0b1..Nonprivilege access + */ +#define RGPIO_PCNP_NPE17(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNP_NPE17_SHIFT)) & RGPIO_PCNP_NPE17_MASK) + +#define RGPIO_PCNP_NPE18_MASK (0x40000U) +#define RGPIO_PCNP_NPE18_SHIFT (18U) +/*! NPE18 - Nonprivilege Enable + * 0b0..Privilege access + * 0b1..Nonprivilege access + */ +#define RGPIO_PCNP_NPE18(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNP_NPE18_SHIFT)) & RGPIO_PCNP_NPE18_MASK) + +#define RGPIO_PCNP_NPE19_MASK (0x80000U) +#define RGPIO_PCNP_NPE19_SHIFT (19U) +/*! NPE19 - Nonprivilege Enable + * 0b0..Privilege access + * 0b1..Nonprivilege access + */ +#define RGPIO_PCNP_NPE19(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNP_NPE19_SHIFT)) & RGPIO_PCNP_NPE19_MASK) + +#define RGPIO_PCNP_NPE20_MASK (0x100000U) +#define RGPIO_PCNP_NPE20_SHIFT (20U) +/*! NPE20 - Nonprivilege Enable + * 0b0..Privilege access + * 0b1..Nonprivilege access + */ +#define RGPIO_PCNP_NPE20(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNP_NPE20_SHIFT)) & RGPIO_PCNP_NPE20_MASK) + +#define RGPIO_PCNP_NPE21_MASK (0x200000U) +#define RGPIO_PCNP_NPE21_SHIFT (21U) +/*! NPE21 - Nonprivilege Enable + * 0b0..Privilege access + * 0b1..Nonprivilege access + */ +#define RGPIO_PCNP_NPE21(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNP_NPE21_SHIFT)) & RGPIO_PCNP_NPE21_MASK) + +#define RGPIO_PCNP_NPE22_MASK (0x400000U) +#define RGPIO_PCNP_NPE22_SHIFT (22U) +/*! NPE22 - Nonprivilege Enable + * 0b0..Privilege access + * 0b1..Nonprivilege access + */ +#define RGPIO_PCNP_NPE22(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNP_NPE22_SHIFT)) & RGPIO_PCNP_NPE22_MASK) + +#define RGPIO_PCNP_NPE23_MASK (0x800000U) +#define RGPIO_PCNP_NPE23_SHIFT (23U) +/*! NPE23 - Nonprivilege Enable + * 0b0..Privilege access + * 0b1..Nonprivilege access + */ +#define RGPIO_PCNP_NPE23(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNP_NPE23_SHIFT)) & RGPIO_PCNP_NPE23_MASK) + +#define RGPIO_PCNP_NPE24_MASK (0x1000000U) +#define RGPIO_PCNP_NPE24_SHIFT (24U) +/*! NPE24 - Nonprivilege Enable + * 0b0..Privilege access + * 0b1..Nonprivilege access + */ +#define RGPIO_PCNP_NPE24(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNP_NPE24_SHIFT)) & RGPIO_PCNP_NPE24_MASK) + +#define RGPIO_PCNP_NPE25_MASK (0x2000000U) +#define RGPIO_PCNP_NPE25_SHIFT (25U) +/*! NPE25 - Nonprivilege Enable + * 0b0..Privilege access + * 0b1..Nonprivilege access + */ +#define RGPIO_PCNP_NPE25(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNP_NPE25_SHIFT)) & RGPIO_PCNP_NPE25_MASK) + +#define RGPIO_PCNP_NPE26_MASK (0x4000000U) +#define RGPIO_PCNP_NPE26_SHIFT (26U) +/*! NPE26 - Nonprivilege Enable + * 0b0..Privilege access + * 0b1..Nonprivilege access + */ +#define RGPIO_PCNP_NPE26(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNP_NPE26_SHIFT)) & RGPIO_PCNP_NPE26_MASK) + +#define RGPIO_PCNP_NPE27_MASK (0x8000000U) +#define RGPIO_PCNP_NPE27_SHIFT (27U) +/*! NPE27 - Nonprivilege Enable + * 0b0..Privilege access + * 0b1..Nonprivilege access + */ +#define RGPIO_PCNP_NPE27(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNP_NPE27_SHIFT)) & RGPIO_PCNP_NPE27_MASK) + +#define RGPIO_PCNP_NPE28_MASK (0x10000000U) +#define RGPIO_PCNP_NPE28_SHIFT (28U) +/*! NPE28 - Nonprivilege Enable + * 0b0..Privilege access + * 0b1..Nonprivilege access + */ +#define RGPIO_PCNP_NPE28(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNP_NPE28_SHIFT)) & RGPIO_PCNP_NPE28_MASK) + +#define RGPIO_PCNP_NPE29_MASK (0x20000000U) +#define RGPIO_PCNP_NPE29_SHIFT (29U) +/*! NPE29 - Nonprivilege Enable + * 0b0..Privilege access + * 0b1..Nonprivilege access + */ +#define RGPIO_PCNP_NPE29(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNP_NPE29_SHIFT)) & RGPIO_PCNP_NPE29_MASK) + +#define RGPIO_PCNP_NPE30_MASK (0x40000000U) +#define RGPIO_PCNP_NPE30_SHIFT (30U) +/*! NPE30 - Nonprivilege Enable + * 0b0..Privilege access + * 0b1..Nonprivilege access + */ +#define RGPIO_PCNP_NPE30(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNP_NPE30_SHIFT)) & RGPIO_PCNP_NPE30_MASK) + +#define RGPIO_PCNP_NPE31_MASK (0x80000000U) +#define RGPIO_PCNP_NPE31_SHIFT (31U) +/*! NPE31 - Nonprivilege Enable + * 0b0..Privilege access + * 0b1..Nonprivilege access + */ +#define RGPIO_PCNP_NPE31(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNP_NPE31_SHIFT)) & RGPIO_PCNP_NPE31_MASK) +/*! @} */ + +/*! @name ICNP - Interrupt Control Nonprivilege */ +/*! @{ */ + +#define RGPIO_ICNP_NPE0_MASK (0x1U) +#define RGPIO_ICNP_NPE0_SHIFT (0U) +/*! NPE0 - Nonprivilege Enable + * 0b0..Privilege access + * 0b1..Nonprivilege access + */ +#define RGPIO_ICNP_NPE0(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_ICNP_NPE0_SHIFT)) & RGPIO_ICNP_NPE0_MASK) + +#define RGPIO_ICNP_NPE1_MASK (0x2U) +#define RGPIO_ICNP_NPE1_SHIFT (1U) +/*! NPE1 - Nonprivilege Enable + * 0b0..Privilege access + * 0b1..Nonprivilege access + */ +#define RGPIO_ICNP_NPE1(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_ICNP_NPE1_SHIFT)) & RGPIO_ICNP_NPE1_MASK) +/*! @} */ + +/*! @name PDOR - Port Data Output */ +/*! @{ */ + +#define RGPIO_PDOR_PDO0_MASK (0x1U) +#define RGPIO_PDOR_PDO0_SHIFT (0U) +/*! PDO0 - Port Data Output + * 0b0..Logic level 0 + * 0b1..Logic level 1 + */ +#define RGPIO_PDOR_PDO0(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDOR_PDO0_SHIFT)) & RGPIO_PDOR_PDO0_MASK) + +#define RGPIO_PDOR_PDO1_MASK (0x2U) +#define RGPIO_PDOR_PDO1_SHIFT (1U) +/*! PDO1 - Port Data Output + * 0b0..Logic level 0 + * 0b1..Logic level 1 + */ +#define RGPIO_PDOR_PDO1(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDOR_PDO1_SHIFT)) & RGPIO_PDOR_PDO1_MASK) + +#define RGPIO_PDOR_PDO2_MASK (0x4U) +#define RGPIO_PDOR_PDO2_SHIFT (2U) +/*! PDO2 - Port Data Output + * 0b0..Logic level 0 + * 0b1..Logic level 1 + */ +#define RGPIO_PDOR_PDO2(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDOR_PDO2_SHIFT)) & RGPIO_PDOR_PDO2_MASK) + +#define RGPIO_PDOR_PDO3_MASK (0x8U) +#define RGPIO_PDOR_PDO3_SHIFT (3U) +/*! PDO3 - Port Data Output + * 0b0..Logic level 0 + * 0b1..Logic level 1 + */ +#define RGPIO_PDOR_PDO3(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDOR_PDO3_SHIFT)) & RGPIO_PDOR_PDO3_MASK) + +#define RGPIO_PDOR_PDO4_MASK (0x10U) +#define RGPIO_PDOR_PDO4_SHIFT (4U) +/*! PDO4 - Port Data Output + * 0b0..Logic level 0 + * 0b1..Logic level 1 + */ +#define RGPIO_PDOR_PDO4(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDOR_PDO4_SHIFT)) & RGPIO_PDOR_PDO4_MASK) + +#define RGPIO_PDOR_PDO5_MASK (0x20U) +#define RGPIO_PDOR_PDO5_SHIFT (5U) +/*! PDO5 - Port Data Output + * 0b0..Logic level 0 + * 0b1..Logic level 1 + */ +#define RGPIO_PDOR_PDO5(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDOR_PDO5_SHIFT)) & RGPIO_PDOR_PDO5_MASK) + +#define RGPIO_PDOR_PDO6_MASK (0x40U) +#define RGPIO_PDOR_PDO6_SHIFT (6U) +/*! PDO6 - Port Data Output + * 0b0..Logic level 0 + * 0b1..Logic level 1 + */ +#define RGPIO_PDOR_PDO6(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDOR_PDO6_SHIFT)) & RGPIO_PDOR_PDO6_MASK) + +#define RGPIO_PDOR_PDO7_MASK (0x80U) +#define RGPIO_PDOR_PDO7_SHIFT (7U) +/*! PDO7 - Port Data Output + * 0b0..Logic level 0 + * 0b1..Logic level 1 + */ +#define RGPIO_PDOR_PDO7(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDOR_PDO7_SHIFT)) & RGPIO_PDOR_PDO7_MASK) + +#define RGPIO_PDOR_PDO8_MASK (0x100U) +#define RGPIO_PDOR_PDO8_SHIFT (8U) +/*! PDO8 - Port Data Output + * 0b0..Logic level 0 + * 0b1..Logic level 1 + */ +#define RGPIO_PDOR_PDO8(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDOR_PDO8_SHIFT)) & RGPIO_PDOR_PDO8_MASK) + +#define RGPIO_PDOR_PDO9_MASK (0x200U) +#define RGPIO_PDOR_PDO9_SHIFT (9U) +/*! PDO9 - Port Data Output + * 0b0..Logic level 0 + * 0b1..Logic level 1 + */ +#define RGPIO_PDOR_PDO9(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDOR_PDO9_SHIFT)) & RGPIO_PDOR_PDO9_MASK) + +#define RGPIO_PDOR_PDO10_MASK (0x400U) +#define RGPIO_PDOR_PDO10_SHIFT (10U) +/*! PDO10 - Port Data Output + * 0b0..Logic level 0 + * 0b1..Logic level 1 + */ +#define RGPIO_PDOR_PDO10(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDOR_PDO10_SHIFT)) & RGPIO_PDOR_PDO10_MASK) + +#define RGPIO_PDOR_PDO11_MASK (0x800U) +#define RGPIO_PDOR_PDO11_SHIFT (11U) +/*! PDO11 - Port Data Output + * 0b0..Logic level 0 + * 0b1..Logic level 1 + */ +#define RGPIO_PDOR_PDO11(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDOR_PDO11_SHIFT)) & RGPIO_PDOR_PDO11_MASK) + +#define RGPIO_PDOR_PDO12_MASK (0x1000U) +#define RGPIO_PDOR_PDO12_SHIFT (12U) +/*! PDO12 - Port Data Output + * 0b0..Logic level 0 + * 0b1..Logic level 1 + */ +#define RGPIO_PDOR_PDO12(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDOR_PDO12_SHIFT)) & RGPIO_PDOR_PDO12_MASK) + +#define RGPIO_PDOR_PDO13_MASK (0x2000U) +#define RGPIO_PDOR_PDO13_SHIFT (13U) +/*! PDO13 - Port Data Output + * 0b0..Logic level 0 + * 0b1..Logic level 1 + */ +#define RGPIO_PDOR_PDO13(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDOR_PDO13_SHIFT)) & RGPIO_PDOR_PDO13_MASK) + +#define RGPIO_PDOR_PDO14_MASK (0x4000U) +#define RGPIO_PDOR_PDO14_SHIFT (14U) +/*! PDO14 - Port Data Output + * 0b0..Logic level 0 + * 0b1..Logic level 1 + */ +#define RGPIO_PDOR_PDO14(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDOR_PDO14_SHIFT)) & RGPIO_PDOR_PDO14_MASK) + +#define RGPIO_PDOR_PDO15_MASK (0x8000U) +#define RGPIO_PDOR_PDO15_SHIFT (15U) +/*! PDO15 - Port Data Output + * 0b0..Logic level 0 + * 0b1..Logic level 1 + */ +#define RGPIO_PDOR_PDO15(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDOR_PDO15_SHIFT)) & RGPIO_PDOR_PDO15_MASK) + +#define RGPIO_PDOR_PDO16_MASK (0x10000U) +#define RGPIO_PDOR_PDO16_SHIFT (16U) +/*! PDO16 - Port Data Output + * 0b0..Logic level 0 + * 0b1..Logic level 1 + */ +#define RGPIO_PDOR_PDO16(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDOR_PDO16_SHIFT)) & RGPIO_PDOR_PDO16_MASK) + +#define RGPIO_PDOR_PDO17_MASK (0x20000U) +#define RGPIO_PDOR_PDO17_SHIFT (17U) +/*! PDO17 - Port Data Output + * 0b0..Logic level 0 + * 0b1..Logic level 1 + */ +#define RGPIO_PDOR_PDO17(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDOR_PDO17_SHIFT)) & RGPIO_PDOR_PDO17_MASK) + +#define RGPIO_PDOR_PDO18_MASK (0x40000U) +#define RGPIO_PDOR_PDO18_SHIFT (18U) +/*! PDO18 - Port Data Output + * 0b0..Logic level 0 + * 0b1..Logic level 1 + */ +#define RGPIO_PDOR_PDO18(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDOR_PDO18_SHIFT)) & RGPIO_PDOR_PDO18_MASK) + +#define RGPIO_PDOR_PDO19_MASK (0x80000U) +#define RGPIO_PDOR_PDO19_SHIFT (19U) +/*! PDO19 - Port Data Output + * 0b0..Logic level 0 + * 0b1..Logic level 1 + */ +#define RGPIO_PDOR_PDO19(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDOR_PDO19_SHIFT)) & RGPIO_PDOR_PDO19_MASK) + +#define RGPIO_PDOR_PDO20_MASK (0x100000U) +#define RGPIO_PDOR_PDO20_SHIFT (20U) +/*! PDO20 - Port Data Output + * 0b0..Logic level 0 + * 0b1..Logic level 1 + */ +#define RGPIO_PDOR_PDO20(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDOR_PDO20_SHIFT)) & RGPIO_PDOR_PDO20_MASK) + +#define RGPIO_PDOR_PDO21_MASK (0x200000U) +#define RGPIO_PDOR_PDO21_SHIFT (21U) +/*! PDO21 - Port Data Output + * 0b0..Logic level 0 + * 0b1..Logic level 1 + */ +#define RGPIO_PDOR_PDO21(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDOR_PDO21_SHIFT)) & RGPIO_PDOR_PDO21_MASK) + +#define RGPIO_PDOR_PDO22_MASK (0x400000U) +#define RGPIO_PDOR_PDO22_SHIFT (22U) +/*! PDO22 - Port Data Output + * 0b0..Logic level 0 + * 0b1..Logic level 1 + */ +#define RGPIO_PDOR_PDO22(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDOR_PDO22_SHIFT)) & RGPIO_PDOR_PDO22_MASK) + +#define RGPIO_PDOR_PDO23_MASK (0x800000U) +#define RGPIO_PDOR_PDO23_SHIFT (23U) +/*! PDO23 - Port Data Output + * 0b0..Logic level 0 + * 0b1..Logic level 1 + */ +#define RGPIO_PDOR_PDO23(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDOR_PDO23_SHIFT)) & RGPIO_PDOR_PDO23_MASK) + +#define RGPIO_PDOR_PDO24_MASK (0x1000000U) +#define RGPIO_PDOR_PDO24_SHIFT (24U) +/*! PDO24 - Port Data Output + * 0b0..Logic level 0 + * 0b1..Logic level 1 + */ +#define RGPIO_PDOR_PDO24(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDOR_PDO24_SHIFT)) & RGPIO_PDOR_PDO24_MASK) + +#define RGPIO_PDOR_PDO25_MASK (0x2000000U) +#define RGPIO_PDOR_PDO25_SHIFT (25U) +/*! PDO25 - Port Data Output + * 0b0..Logic level 0 + * 0b1..Logic level 1 + */ +#define RGPIO_PDOR_PDO25(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDOR_PDO25_SHIFT)) & RGPIO_PDOR_PDO25_MASK) + +#define RGPIO_PDOR_PDO26_MASK (0x4000000U) +#define RGPIO_PDOR_PDO26_SHIFT (26U) +/*! PDO26 - Port Data Output + * 0b0..Logic level 0 + * 0b1..Logic level 1 + */ +#define RGPIO_PDOR_PDO26(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDOR_PDO26_SHIFT)) & RGPIO_PDOR_PDO26_MASK) + +#define RGPIO_PDOR_PDO27_MASK (0x8000000U) +#define RGPIO_PDOR_PDO27_SHIFT (27U) +/*! PDO27 - Port Data Output + * 0b0..Logic level 0 + * 0b1..Logic level 1 + */ +#define RGPIO_PDOR_PDO27(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDOR_PDO27_SHIFT)) & RGPIO_PDOR_PDO27_MASK) + +#define RGPIO_PDOR_PDO28_MASK (0x10000000U) +#define RGPIO_PDOR_PDO28_SHIFT (28U) +/*! PDO28 - Port Data Output + * 0b0..Logic level 0 + * 0b1..Logic level 1 + */ +#define RGPIO_PDOR_PDO28(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDOR_PDO28_SHIFT)) & RGPIO_PDOR_PDO28_MASK) + +#define RGPIO_PDOR_PDO29_MASK (0x20000000U) +#define RGPIO_PDOR_PDO29_SHIFT (29U) +/*! PDO29 - Port Data Output + * 0b0..Logic level 0 + * 0b1..Logic level 1 + */ +#define RGPIO_PDOR_PDO29(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDOR_PDO29_SHIFT)) & RGPIO_PDOR_PDO29_MASK) + +#define RGPIO_PDOR_PDO30_MASK (0x40000000U) +#define RGPIO_PDOR_PDO30_SHIFT (30U) +/*! PDO30 - Port Data Output + * 0b0..Logic level 0 + * 0b1..Logic level 1 + */ +#define RGPIO_PDOR_PDO30(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDOR_PDO30_SHIFT)) & RGPIO_PDOR_PDO30_MASK) + +#define RGPIO_PDOR_PDO31_MASK (0x80000000U) +#define RGPIO_PDOR_PDO31_SHIFT (31U) +/*! PDO31 - Port Data Output + * 0b0..Logic level 0 + * 0b1..Logic level 1 + */ +#define RGPIO_PDOR_PDO31(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDOR_PDO31_SHIFT)) & RGPIO_PDOR_PDO31_MASK) +/*! @} */ + +/*! @name PSOR - Port Set Output */ +/*! @{ */ + +#define RGPIO_PSOR_PTSO0_MASK (0x1U) +#define RGPIO_PSOR_PTSO0_SHIFT (0U) +/*! PTSO0 - Port Set Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 + */ +#define RGPIO_PSOR_PTSO0(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PSOR_PTSO0_SHIFT)) & RGPIO_PSOR_PTSO0_MASK) + +#define RGPIO_PSOR_PTSO1_MASK (0x2U) +#define RGPIO_PSOR_PTSO1_SHIFT (1U) +/*! PTSO1 - Port Set Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 + */ +#define RGPIO_PSOR_PTSO1(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PSOR_PTSO1_SHIFT)) & RGPIO_PSOR_PTSO1_MASK) + +#define RGPIO_PSOR_PTSO2_MASK (0x4U) +#define RGPIO_PSOR_PTSO2_SHIFT (2U) +/*! PTSO2 - Port Set Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 + */ +#define RGPIO_PSOR_PTSO2(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PSOR_PTSO2_SHIFT)) & RGPIO_PSOR_PTSO2_MASK) + +#define RGPIO_PSOR_PTSO3_MASK (0x8U) +#define RGPIO_PSOR_PTSO3_SHIFT (3U) +/*! PTSO3 - Port Set Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 + */ +#define RGPIO_PSOR_PTSO3(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PSOR_PTSO3_SHIFT)) & RGPIO_PSOR_PTSO3_MASK) + +#define RGPIO_PSOR_PTSO4_MASK (0x10U) +#define RGPIO_PSOR_PTSO4_SHIFT (4U) +/*! PTSO4 - Port Set Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 + */ +#define RGPIO_PSOR_PTSO4(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PSOR_PTSO4_SHIFT)) & RGPIO_PSOR_PTSO4_MASK) + +#define RGPIO_PSOR_PTSO5_MASK (0x20U) +#define RGPIO_PSOR_PTSO5_SHIFT (5U) +/*! PTSO5 - Port Set Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 + */ +#define RGPIO_PSOR_PTSO5(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PSOR_PTSO5_SHIFT)) & RGPIO_PSOR_PTSO5_MASK) + +#define RGPIO_PSOR_PTSO6_MASK (0x40U) +#define RGPIO_PSOR_PTSO6_SHIFT (6U) +/*! PTSO6 - Port Set Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 + */ +#define RGPIO_PSOR_PTSO6(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PSOR_PTSO6_SHIFT)) & RGPIO_PSOR_PTSO6_MASK) + +#define RGPIO_PSOR_PTSO7_MASK (0x80U) +#define RGPIO_PSOR_PTSO7_SHIFT (7U) +/*! PTSO7 - Port Set Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 + */ +#define RGPIO_PSOR_PTSO7(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PSOR_PTSO7_SHIFT)) & RGPIO_PSOR_PTSO7_MASK) + +#define RGPIO_PSOR_PTSO8_MASK (0x100U) +#define RGPIO_PSOR_PTSO8_SHIFT (8U) +/*! PTSO8 - Port Set Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 + */ +#define RGPIO_PSOR_PTSO8(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PSOR_PTSO8_SHIFT)) & RGPIO_PSOR_PTSO8_MASK) + +#define RGPIO_PSOR_PTSO9_MASK (0x200U) +#define RGPIO_PSOR_PTSO9_SHIFT (9U) +/*! PTSO9 - Port Set Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 + */ +#define RGPIO_PSOR_PTSO9(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PSOR_PTSO9_SHIFT)) & RGPIO_PSOR_PTSO9_MASK) + +#define RGPIO_PSOR_PTSO10_MASK (0x400U) +#define RGPIO_PSOR_PTSO10_SHIFT (10U) +/*! PTSO10 - Port Set Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 + */ +#define RGPIO_PSOR_PTSO10(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PSOR_PTSO10_SHIFT)) & RGPIO_PSOR_PTSO10_MASK) + +#define RGPIO_PSOR_PTSO11_MASK (0x800U) +#define RGPIO_PSOR_PTSO11_SHIFT (11U) +/*! PTSO11 - Port Set Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 + */ +#define RGPIO_PSOR_PTSO11(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PSOR_PTSO11_SHIFT)) & RGPIO_PSOR_PTSO11_MASK) + +#define RGPIO_PSOR_PTSO12_MASK (0x1000U) +#define RGPIO_PSOR_PTSO12_SHIFT (12U) +/*! PTSO12 - Port Set Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 + */ +#define RGPIO_PSOR_PTSO12(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PSOR_PTSO12_SHIFT)) & RGPIO_PSOR_PTSO12_MASK) + +#define RGPIO_PSOR_PTSO13_MASK (0x2000U) +#define RGPIO_PSOR_PTSO13_SHIFT (13U) +/*! PTSO13 - Port Set Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 + */ +#define RGPIO_PSOR_PTSO13(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PSOR_PTSO13_SHIFT)) & RGPIO_PSOR_PTSO13_MASK) + +#define RGPIO_PSOR_PTSO14_MASK (0x4000U) +#define RGPIO_PSOR_PTSO14_SHIFT (14U) +/*! PTSO14 - Port Set Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 + */ +#define RGPIO_PSOR_PTSO14(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PSOR_PTSO14_SHIFT)) & RGPIO_PSOR_PTSO14_MASK) + +#define RGPIO_PSOR_PTSO15_MASK (0x8000U) +#define RGPIO_PSOR_PTSO15_SHIFT (15U) +/*! PTSO15 - Port Set Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 + */ +#define RGPIO_PSOR_PTSO15(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PSOR_PTSO15_SHIFT)) & RGPIO_PSOR_PTSO15_MASK) + +#define RGPIO_PSOR_PTSO16_MASK (0x10000U) +#define RGPIO_PSOR_PTSO16_SHIFT (16U) +/*! PTSO16 - Port Set Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 + */ +#define RGPIO_PSOR_PTSO16(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PSOR_PTSO16_SHIFT)) & RGPIO_PSOR_PTSO16_MASK) + +#define RGPIO_PSOR_PTSO17_MASK (0x20000U) +#define RGPIO_PSOR_PTSO17_SHIFT (17U) +/*! PTSO17 - Port Set Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 + */ +#define RGPIO_PSOR_PTSO17(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PSOR_PTSO17_SHIFT)) & RGPIO_PSOR_PTSO17_MASK) + +#define RGPIO_PSOR_PTSO18_MASK (0x40000U) +#define RGPIO_PSOR_PTSO18_SHIFT (18U) +/*! PTSO18 - Port Set Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 + */ +#define RGPIO_PSOR_PTSO18(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PSOR_PTSO18_SHIFT)) & RGPIO_PSOR_PTSO18_MASK) + +#define RGPIO_PSOR_PTSO19_MASK (0x80000U) +#define RGPIO_PSOR_PTSO19_SHIFT (19U) +/*! PTSO19 - Port Set Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 + */ +#define RGPIO_PSOR_PTSO19(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PSOR_PTSO19_SHIFT)) & RGPIO_PSOR_PTSO19_MASK) + +#define RGPIO_PSOR_PTSO20_MASK (0x100000U) +#define RGPIO_PSOR_PTSO20_SHIFT (20U) +/*! PTSO20 - Port Set Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 + */ +#define RGPIO_PSOR_PTSO20(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PSOR_PTSO20_SHIFT)) & RGPIO_PSOR_PTSO20_MASK) + +#define RGPIO_PSOR_PTSO21_MASK (0x200000U) +#define RGPIO_PSOR_PTSO21_SHIFT (21U) +/*! PTSO21 - Port Set Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 + */ +#define RGPIO_PSOR_PTSO21(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PSOR_PTSO21_SHIFT)) & RGPIO_PSOR_PTSO21_MASK) + +#define RGPIO_PSOR_PTSO22_MASK (0x400000U) +#define RGPIO_PSOR_PTSO22_SHIFT (22U) +/*! PTSO22 - Port Set Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 + */ +#define RGPIO_PSOR_PTSO22(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PSOR_PTSO22_SHIFT)) & RGPIO_PSOR_PTSO22_MASK) + +#define RGPIO_PSOR_PTSO23_MASK (0x800000U) +#define RGPIO_PSOR_PTSO23_SHIFT (23U) +/*! PTSO23 - Port Set Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 + */ +#define RGPIO_PSOR_PTSO23(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PSOR_PTSO23_SHIFT)) & RGPIO_PSOR_PTSO23_MASK) + +#define RGPIO_PSOR_PTSO24_MASK (0x1000000U) +#define RGPIO_PSOR_PTSO24_SHIFT (24U) +/*! PTSO24 - Port Set Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 + */ +#define RGPIO_PSOR_PTSO24(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PSOR_PTSO24_SHIFT)) & RGPIO_PSOR_PTSO24_MASK) + +#define RGPIO_PSOR_PTSO25_MASK (0x2000000U) +#define RGPIO_PSOR_PTSO25_SHIFT (25U) +/*! PTSO25 - Port Set Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 + */ +#define RGPIO_PSOR_PTSO25(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PSOR_PTSO25_SHIFT)) & RGPIO_PSOR_PTSO25_MASK) + +#define RGPIO_PSOR_PTSO26_MASK (0x4000000U) +#define RGPIO_PSOR_PTSO26_SHIFT (26U) +/*! PTSO26 - Port Set Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 + */ +#define RGPIO_PSOR_PTSO26(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PSOR_PTSO26_SHIFT)) & RGPIO_PSOR_PTSO26_MASK) + +#define RGPIO_PSOR_PTSO27_MASK (0x8000000U) +#define RGPIO_PSOR_PTSO27_SHIFT (27U) +/*! PTSO27 - Port Set Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 + */ +#define RGPIO_PSOR_PTSO27(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PSOR_PTSO27_SHIFT)) & RGPIO_PSOR_PTSO27_MASK) + +#define RGPIO_PSOR_PTSO28_MASK (0x10000000U) +#define RGPIO_PSOR_PTSO28_SHIFT (28U) +/*! PTSO28 - Port Set Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 + */ +#define RGPIO_PSOR_PTSO28(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PSOR_PTSO28_SHIFT)) & RGPIO_PSOR_PTSO28_MASK) + +#define RGPIO_PSOR_PTSO29_MASK (0x20000000U) +#define RGPIO_PSOR_PTSO29_SHIFT (29U) +/*! PTSO29 - Port Set Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 + */ +#define RGPIO_PSOR_PTSO29(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PSOR_PTSO29_SHIFT)) & RGPIO_PSOR_PTSO29_MASK) + +#define RGPIO_PSOR_PTSO30_MASK (0x40000000U) +#define RGPIO_PSOR_PTSO30_SHIFT (30U) +/*! PTSO30 - Port Set Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 + */ +#define RGPIO_PSOR_PTSO30(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PSOR_PTSO30_SHIFT)) & RGPIO_PSOR_PTSO30_MASK) + +#define RGPIO_PSOR_PTSO31_MASK (0x80000000U) +#define RGPIO_PSOR_PTSO31_SHIFT (31U) +/*! PTSO31 - Port Set Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 + */ +#define RGPIO_PSOR_PTSO31(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PSOR_PTSO31_SHIFT)) & RGPIO_PSOR_PTSO31_MASK) +/*! @} */ + +/*! @name PCOR - Port Clear Output */ +/*! @{ */ + +#define RGPIO_PCOR_PTCO0_MASK (0x1U) +#define RGPIO_PCOR_PTCO0_SHIFT (0U) +/*! PTCO0 - Port Clear Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 + */ +#define RGPIO_PCOR_PTCO0(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCOR_PTCO0_SHIFT)) & RGPIO_PCOR_PTCO0_MASK) + +#define RGPIO_PCOR_PTCO1_MASK (0x2U) +#define RGPIO_PCOR_PTCO1_SHIFT (1U) +/*! PTCO1 - Port Clear Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 + */ +#define RGPIO_PCOR_PTCO1(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCOR_PTCO1_SHIFT)) & RGPIO_PCOR_PTCO1_MASK) + +#define RGPIO_PCOR_PTCO2_MASK (0x4U) +#define RGPIO_PCOR_PTCO2_SHIFT (2U) +/*! PTCO2 - Port Clear Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 + */ +#define RGPIO_PCOR_PTCO2(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCOR_PTCO2_SHIFT)) & RGPIO_PCOR_PTCO2_MASK) + +#define RGPIO_PCOR_PTCO3_MASK (0x8U) +#define RGPIO_PCOR_PTCO3_SHIFT (3U) +/*! PTCO3 - Port Clear Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 + */ +#define RGPIO_PCOR_PTCO3(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCOR_PTCO3_SHIFT)) & RGPIO_PCOR_PTCO3_MASK) + +#define RGPIO_PCOR_PTCO4_MASK (0x10U) +#define RGPIO_PCOR_PTCO4_SHIFT (4U) +/*! PTCO4 - Port Clear Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 + */ +#define RGPIO_PCOR_PTCO4(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCOR_PTCO4_SHIFT)) & RGPIO_PCOR_PTCO4_MASK) + +#define RGPIO_PCOR_PTCO5_MASK (0x20U) +#define RGPIO_PCOR_PTCO5_SHIFT (5U) +/*! PTCO5 - Port Clear Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 + */ +#define RGPIO_PCOR_PTCO5(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCOR_PTCO5_SHIFT)) & RGPIO_PCOR_PTCO5_MASK) + +#define RGPIO_PCOR_PTCO6_MASK (0x40U) +#define RGPIO_PCOR_PTCO6_SHIFT (6U) +/*! PTCO6 - Port Clear Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 + */ +#define RGPIO_PCOR_PTCO6(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCOR_PTCO6_SHIFT)) & RGPIO_PCOR_PTCO6_MASK) + +#define RGPIO_PCOR_PTCO7_MASK (0x80U) +#define RGPIO_PCOR_PTCO7_SHIFT (7U) +/*! PTCO7 - Port Clear Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 + */ +#define RGPIO_PCOR_PTCO7(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCOR_PTCO7_SHIFT)) & RGPIO_PCOR_PTCO7_MASK) + +#define RGPIO_PCOR_PTCO8_MASK (0x100U) +#define RGPIO_PCOR_PTCO8_SHIFT (8U) +/*! PTCO8 - Port Clear Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 + */ +#define RGPIO_PCOR_PTCO8(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCOR_PTCO8_SHIFT)) & RGPIO_PCOR_PTCO8_MASK) + +#define RGPIO_PCOR_PTCO9_MASK (0x200U) +#define RGPIO_PCOR_PTCO9_SHIFT (9U) +/*! PTCO9 - Port Clear Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 + */ +#define RGPIO_PCOR_PTCO9(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCOR_PTCO9_SHIFT)) & RGPIO_PCOR_PTCO9_MASK) + +#define RGPIO_PCOR_PTCO10_MASK (0x400U) +#define RGPIO_PCOR_PTCO10_SHIFT (10U) +/*! PTCO10 - Port Clear Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 + */ +#define RGPIO_PCOR_PTCO10(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCOR_PTCO10_SHIFT)) & RGPIO_PCOR_PTCO10_MASK) + +#define RGPIO_PCOR_PTCO11_MASK (0x800U) +#define RGPIO_PCOR_PTCO11_SHIFT (11U) +/*! PTCO11 - Port Clear Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 + */ +#define RGPIO_PCOR_PTCO11(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCOR_PTCO11_SHIFT)) & RGPIO_PCOR_PTCO11_MASK) + +#define RGPIO_PCOR_PTCO12_MASK (0x1000U) +#define RGPIO_PCOR_PTCO12_SHIFT (12U) +/*! PTCO12 - Port Clear Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 + */ +#define RGPIO_PCOR_PTCO12(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCOR_PTCO12_SHIFT)) & RGPIO_PCOR_PTCO12_MASK) + +#define RGPIO_PCOR_PTCO13_MASK (0x2000U) +#define RGPIO_PCOR_PTCO13_SHIFT (13U) +/*! PTCO13 - Port Clear Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 + */ +#define RGPIO_PCOR_PTCO13(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCOR_PTCO13_SHIFT)) & RGPIO_PCOR_PTCO13_MASK) + +#define RGPIO_PCOR_PTCO14_MASK (0x4000U) +#define RGPIO_PCOR_PTCO14_SHIFT (14U) +/*! PTCO14 - Port Clear Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 + */ +#define RGPIO_PCOR_PTCO14(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCOR_PTCO14_SHIFT)) & RGPIO_PCOR_PTCO14_MASK) + +#define RGPIO_PCOR_PTCO15_MASK (0x8000U) +#define RGPIO_PCOR_PTCO15_SHIFT (15U) +/*! PTCO15 - Port Clear Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 + */ +#define RGPIO_PCOR_PTCO15(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCOR_PTCO15_SHIFT)) & RGPIO_PCOR_PTCO15_MASK) + +#define RGPIO_PCOR_PTCO16_MASK (0x10000U) +#define RGPIO_PCOR_PTCO16_SHIFT (16U) +/*! PTCO16 - Port Clear Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 + */ +#define RGPIO_PCOR_PTCO16(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCOR_PTCO16_SHIFT)) & RGPIO_PCOR_PTCO16_MASK) + +#define RGPIO_PCOR_PTCO17_MASK (0x20000U) +#define RGPIO_PCOR_PTCO17_SHIFT (17U) +/*! PTCO17 - Port Clear Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 + */ +#define RGPIO_PCOR_PTCO17(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCOR_PTCO17_SHIFT)) & RGPIO_PCOR_PTCO17_MASK) + +#define RGPIO_PCOR_PTCO18_MASK (0x40000U) +#define RGPIO_PCOR_PTCO18_SHIFT (18U) +/*! PTCO18 - Port Clear Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 + */ +#define RGPIO_PCOR_PTCO18(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCOR_PTCO18_SHIFT)) & RGPIO_PCOR_PTCO18_MASK) + +#define RGPIO_PCOR_PTCO19_MASK (0x80000U) +#define RGPIO_PCOR_PTCO19_SHIFT (19U) +/*! PTCO19 - Port Clear Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 + */ +#define RGPIO_PCOR_PTCO19(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCOR_PTCO19_SHIFT)) & RGPIO_PCOR_PTCO19_MASK) + +#define RGPIO_PCOR_PTCO20_MASK (0x100000U) +#define RGPIO_PCOR_PTCO20_SHIFT (20U) +/*! PTCO20 - Port Clear Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 + */ +#define RGPIO_PCOR_PTCO20(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCOR_PTCO20_SHIFT)) & RGPIO_PCOR_PTCO20_MASK) + +#define RGPIO_PCOR_PTCO21_MASK (0x200000U) +#define RGPIO_PCOR_PTCO21_SHIFT (21U) +/*! PTCO21 - Port Clear Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 + */ +#define RGPIO_PCOR_PTCO21(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCOR_PTCO21_SHIFT)) & RGPIO_PCOR_PTCO21_MASK) + +#define RGPIO_PCOR_PTCO22_MASK (0x400000U) +#define RGPIO_PCOR_PTCO22_SHIFT (22U) +/*! PTCO22 - Port Clear Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 + */ +#define RGPIO_PCOR_PTCO22(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCOR_PTCO22_SHIFT)) & RGPIO_PCOR_PTCO22_MASK) + +#define RGPIO_PCOR_PTCO23_MASK (0x800000U) +#define RGPIO_PCOR_PTCO23_SHIFT (23U) +/*! PTCO23 - Port Clear Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 + */ +#define RGPIO_PCOR_PTCO23(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCOR_PTCO23_SHIFT)) & RGPIO_PCOR_PTCO23_MASK) + +#define RGPIO_PCOR_PTCO24_MASK (0x1000000U) +#define RGPIO_PCOR_PTCO24_SHIFT (24U) +/*! PTCO24 - Port Clear Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 + */ +#define RGPIO_PCOR_PTCO24(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCOR_PTCO24_SHIFT)) & RGPIO_PCOR_PTCO24_MASK) + +#define RGPIO_PCOR_PTCO25_MASK (0x2000000U) +#define RGPIO_PCOR_PTCO25_SHIFT (25U) +/*! PTCO25 - Port Clear Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 + */ +#define RGPIO_PCOR_PTCO25(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCOR_PTCO25_SHIFT)) & RGPIO_PCOR_PTCO25_MASK) + +#define RGPIO_PCOR_PTCO26_MASK (0x4000000U) +#define RGPIO_PCOR_PTCO26_SHIFT (26U) +/*! PTCO26 - Port Clear Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 + */ +#define RGPIO_PCOR_PTCO26(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCOR_PTCO26_SHIFT)) & RGPIO_PCOR_PTCO26_MASK) + +#define RGPIO_PCOR_PTCO27_MASK (0x8000000U) +#define RGPIO_PCOR_PTCO27_SHIFT (27U) +/*! PTCO27 - Port Clear Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 + */ +#define RGPIO_PCOR_PTCO27(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCOR_PTCO27_SHIFT)) & RGPIO_PCOR_PTCO27_MASK) + +#define RGPIO_PCOR_PTCO28_MASK (0x10000000U) +#define RGPIO_PCOR_PTCO28_SHIFT (28U) +/*! PTCO28 - Port Clear Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 + */ +#define RGPIO_PCOR_PTCO28(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCOR_PTCO28_SHIFT)) & RGPIO_PCOR_PTCO28_MASK) + +#define RGPIO_PCOR_PTCO29_MASK (0x20000000U) +#define RGPIO_PCOR_PTCO29_SHIFT (29U) +/*! PTCO29 - Port Clear Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 + */ +#define RGPIO_PCOR_PTCO29(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCOR_PTCO29_SHIFT)) & RGPIO_PCOR_PTCO29_MASK) + +#define RGPIO_PCOR_PTCO30_MASK (0x40000000U) +#define RGPIO_PCOR_PTCO30_SHIFT (30U) +/*! PTCO30 - Port Clear Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 + */ +#define RGPIO_PCOR_PTCO30(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCOR_PTCO30_SHIFT)) & RGPIO_PCOR_PTCO30_MASK) + +#define RGPIO_PCOR_PTCO31_MASK (0x80000000U) +#define RGPIO_PCOR_PTCO31_SHIFT (31U) +/*! PTCO31 - Port Clear Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 + */ +#define RGPIO_PCOR_PTCO31(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCOR_PTCO31_SHIFT)) & RGPIO_PCOR_PTCO31_MASK) +/*! @} */ + +/*! @name PTOR - Port Toggle Output */ +/*! @{ */ + +#define RGPIO_PTOR_PTTO0_MASK (0x1U) +#define RGPIO_PTOR_PTTO0_SHIFT (0U) +/*! PTTO0 - Port Toggle Output + * 0b0..No change + * 0b1..Set to the inverse of its current logic state + */ +#define RGPIO_PTOR_PTTO0(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PTOR_PTTO0_SHIFT)) & RGPIO_PTOR_PTTO0_MASK) + +#define RGPIO_PTOR_PTTO1_MASK (0x2U) +#define RGPIO_PTOR_PTTO1_SHIFT (1U) +/*! PTTO1 - Port Toggle Output + * 0b0..No change + * 0b1..Set to the inverse of its current logic state + */ +#define RGPIO_PTOR_PTTO1(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PTOR_PTTO1_SHIFT)) & RGPIO_PTOR_PTTO1_MASK) + +#define RGPIO_PTOR_PTTO2_MASK (0x4U) +#define RGPIO_PTOR_PTTO2_SHIFT (2U) +/*! PTTO2 - Port Toggle Output + * 0b0..No change + * 0b1..Set to the inverse of its current logic state + */ +#define RGPIO_PTOR_PTTO2(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PTOR_PTTO2_SHIFT)) & RGPIO_PTOR_PTTO2_MASK) + +#define RGPIO_PTOR_PTTO3_MASK (0x8U) +#define RGPIO_PTOR_PTTO3_SHIFT (3U) +/*! PTTO3 - Port Toggle Output + * 0b0..No change + * 0b1..Set to the inverse of its current logic state + */ +#define RGPIO_PTOR_PTTO3(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PTOR_PTTO3_SHIFT)) & RGPIO_PTOR_PTTO3_MASK) + +#define RGPIO_PTOR_PTTO4_MASK (0x10U) +#define RGPIO_PTOR_PTTO4_SHIFT (4U) +/*! PTTO4 - Port Toggle Output + * 0b0..No change + * 0b1..Set to the inverse of its current logic state + */ +#define RGPIO_PTOR_PTTO4(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PTOR_PTTO4_SHIFT)) & RGPIO_PTOR_PTTO4_MASK) + +#define RGPIO_PTOR_PTTO5_MASK (0x20U) +#define RGPIO_PTOR_PTTO5_SHIFT (5U) +/*! PTTO5 - Port Toggle Output + * 0b0..No change + * 0b1..Set to the inverse of its current logic state + */ +#define RGPIO_PTOR_PTTO5(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PTOR_PTTO5_SHIFT)) & RGPIO_PTOR_PTTO5_MASK) + +#define RGPIO_PTOR_PTTO6_MASK (0x40U) +#define RGPIO_PTOR_PTTO6_SHIFT (6U) +/*! PTTO6 - Port Toggle Output + * 0b0..No change + * 0b1..Set to the inverse of its current logic state + */ +#define RGPIO_PTOR_PTTO6(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PTOR_PTTO6_SHIFT)) & RGPIO_PTOR_PTTO6_MASK) + +#define RGPIO_PTOR_PTTO7_MASK (0x80U) +#define RGPIO_PTOR_PTTO7_SHIFT (7U) +/*! PTTO7 - Port Toggle Output + * 0b0..No change + * 0b1..Set to the inverse of its current logic state + */ +#define RGPIO_PTOR_PTTO7(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PTOR_PTTO7_SHIFT)) & RGPIO_PTOR_PTTO7_MASK) + +#define RGPIO_PTOR_PTTO8_MASK (0x100U) +#define RGPIO_PTOR_PTTO8_SHIFT (8U) +/*! PTTO8 - Port Toggle Output + * 0b0..No change + * 0b1..Set to the inverse of its current logic state + */ +#define RGPIO_PTOR_PTTO8(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PTOR_PTTO8_SHIFT)) & RGPIO_PTOR_PTTO8_MASK) + +#define RGPIO_PTOR_PTTO9_MASK (0x200U) +#define RGPIO_PTOR_PTTO9_SHIFT (9U) +/*! PTTO9 - Port Toggle Output + * 0b0..No change + * 0b1..Set to the inverse of its current logic state + */ +#define RGPIO_PTOR_PTTO9(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PTOR_PTTO9_SHIFT)) & RGPIO_PTOR_PTTO9_MASK) + +#define RGPIO_PTOR_PTTO10_MASK (0x400U) +#define RGPIO_PTOR_PTTO10_SHIFT (10U) +/*! PTTO10 - Port Toggle Output + * 0b0..No change + * 0b1..Set to the inverse of its current logic state + */ +#define RGPIO_PTOR_PTTO10(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PTOR_PTTO10_SHIFT)) & RGPIO_PTOR_PTTO10_MASK) + +#define RGPIO_PTOR_PTTO11_MASK (0x800U) +#define RGPIO_PTOR_PTTO11_SHIFT (11U) +/*! PTTO11 - Port Toggle Output + * 0b0..No change + * 0b1..Set to the inverse of its current logic state + */ +#define RGPIO_PTOR_PTTO11(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PTOR_PTTO11_SHIFT)) & RGPIO_PTOR_PTTO11_MASK) + +#define RGPIO_PTOR_PTTO12_MASK (0x1000U) +#define RGPIO_PTOR_PTTO12_SHIFT (12U) +/*! PTTO12 - Port Toggle Output + * 0b0..No change + * 0b1..Set to the inverse of its current logic state + */ +#define RGPIO_PTOR_PTTO12(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PTOR_PTTO12_SHIFT)) & RGPIO_PTOR_PTTO12_MASK) + +#define RGPIO_PTOR_PTTO13_MASK (0x2000U) +#define RGPIO_PTOR_PTTO13_SHIFT (13U) +/*! PTTO13 - Port Toggle Output + * 0b0..No change + * 0b1..Set to the inverse of its current logic state + */ +#define RGPIO_PTOR_PTTO13(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PTOR_PTTO13_SHIFT)) & RGPIO_PTOR_PTTO13_MASK) + +#define RGPIO_PTOR_PTTO14_MASK (0x4000U) +#define RGPIO_PTOR_PTTO14_SHIFT (14U) +/*! PTTO14 - Port Toggle Output + * 0b0..No change + * 0b1..Set to the inverse of its current logic state + */ +#define RGPIO_PTOR_PTTO14(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PTOR_PTTO14_SHIFT)) & RGPIO_PTOR_PTTO14_MASK) + +#define RGPIO_PTOR_PTTO15_MASK (0x8000U) +#define RGPIO_PTOR_PTTO15_SHIFT (15U) +/*! PTTO15 - Port Toggle Output + * 0b0..No change + * 0b1..Set to the inverse of its current logic state + */ +#define RGPIO_PTOR_PTTO15(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PTOR_PTTO15_SHIFT)) & RGPIO_PTOR_PTTO15_MASK) + +#define RGPIO_PTOR_PTTO16_MASK (0x10000U) +#define RGPIO_PTOR_PTTO16_SHIFT (16U) +/*! PTTO16 - Port Toggle Output + * 0b0..No change + * 0b1..Set to the inverse of its current logic state + */ +#define RGPIO_PTOR_PTTO16(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PTOR_PTTO16_SHIFT)) & RGPIO_PTOR_PTTO16_MASK) + +#define RGPIO_PTOR_PTTO17_MASK (0x20000U) +#define RGPIO_PTOR_PTTO17_SHIFT (17U) +/*! PTTO17 - Port Toggle Output + * 0b0..No change + * 0b1..Set to the inverse of its current logic state + */ +#define RGPIO_PTOR_PTTO17(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PTOR_PTTO17_SHIFT)) & RGPIO_PTOR_PTTO17_MASK) + +#define RGPIO_PTOR_PTTO18_MASK (0x40000U) +#define RGPIO_PTOR_PTTO18_SHIFT (18U) +/*! PTTO18 - Port Toggle Output + * 0b0..No change + * 0b1..Set to the inverse of its current logic state + */ +#define RGPIO_PTOR_PTTO18(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PTOR_PTTO18_SHIFT)) & RGPIO_PTOR_PTTO18_MASK) + +#define RGPIO_PTOR_PTTO19_MASK (0x80000U) +#define RGPIO_PTOR_PTTO19_SHIFT (19U) +/*! PTTO19 - Port Toggle Output + * 0b0..No change + * 0b1..Set to the inverse of its current logic state + */ +#define RGPIO_PTOR_PTTO19(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PTOR_PTTO19_SHIFT)) & RGPIO_PTOR_PTTO19_MASK) + +#define RGPIO_PTOR_PTTO20_MASK (0x100000U) +#define RGPIO_PTOR_PTTO20_SHIFT (20U) +/*! PTTO20 - Port Toggle Output + * 0b0..No change + * 0b1..Set to the inverse of its current logic state + */ +#define RGPIO_PTOR_PTTO20(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PTOR_PTTO20_SHIFT)) & RGPIO_PTOR_PTTO20_MASK) + +#define RGPIO_PTOR_PTTO21_MASK (0x200000U) +#define RGPIO_PTOR_PTTO21_SHIFT (21U) +/*! PTTO21 - Port Toggle Output + * 0b0..No change + * 0b1..Set to the inverse of its current logic state + */ +#define RGPIO_PTOR_PTTO21(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PTOR_PTTO21_SHIFT)) & RGPIO_PTOR_PTTO21_MASK) + +#define RGPIO_PTOR_PTTO22_MASK (0x400000U) +#define RGPIO_PTOR_PTTO22_SHIFT (22U) +/*! PTTO22 - Port Toggle Output + * 0b0..No change + * 0b1..Set to the inverse of its current logic state + */ +#define RGPIO_PTOR_PTTO22(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PTOR_PTTO22_SHIFT)) & RGPIO_PTOR_PTTO22_MASK) + +#define RGPIO_PTOR_PTTO23_MASK (0x800000U) +#define RGPIO_PTOR_PTTO23_SHIFT (23U) +/*! PTTO23 - Port Toggle Output + * 0b0..No change + * 0b1..Set to the inverse of its current logic state + */ +#define RGPIO_PTOR_PTTO23(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PTOR_PTTO23_SHIFT)) & RGPIO_PTOR_PTTO23_MASK) + +#define RGPIO_PTOR_PTTO24_MASK (0x1000000U) +#define RGPIO_PTOR_PTTO24_SHIFT (24U) +/*! PTTO24 - Port Toggle Output + * 0b0..No change + * 0b1..Set to the inverse of its current logic state + */ +#define RGPIO_PTOR_PTTO24(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PTOR_PTTO24_SHIFT)) & RGPIO_PTOR_PTTO24_MASK) + +#define RGPIO_PTOR_PTTO25_MASK (0x2000000U) +#define RGPIO_PTOR_PTTO25_SHIFT (25U) +/*! PTTO25 - Port Toggle Output + * 0b0..No change + * 0b1..Set to the inverse of its current logic state + */ +#define RGPIO_PTOR_PTTO25(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PTOR_PTTO25_SHIFT)) & RGPIO_PTOR_PTTO25_MASK) + +#define RGPIO_PTOR_PTTO26_MASK (0x4000000U) +#define RGPIO_PTOR_PTTO26_SHIFT (26U) +/*! PTTO26 - Port Toggle Output + * 0b0..No change + * 0b1..Set to the inverse of its current logic state + */ +#define RGPIO_PTOR_PTTO26(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PTOR_PTTO26_SHIFT)) & RGPIO_PTOR_PTTO26_MASK) + +#define RGPIO_PTOR_PTTO27_MASK (0x8000000U) +#define RGPIO_PTOR_PTTO27_SHIFT (27U) +/*! PTTO27 - Port Toggle Output + * 0b0..No change + * 0b1..Set to the inverse of its current logic state + */ +#define RGPIO_PTOR_PTTO27(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PTOR_PTTO27_SHIFT)) & RGPIO_PTOR_PTTO27_MASK) + +#define RGPIO_PTOR_PTTO28_MASK (0x10000000U) +#define RGPIO_PTOR_PTTO28_SHIFT (28U) +/*! PTTO28 - Port Toggle Output + * 0b0..No change + * 0b1..Set to the inverse of its current logic state + */ +#define RGPIO_PTOR_PTTO28(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PTOR_PTTO28_SHIFT)) & RGPIO_PTOR_PTTO28_MASK) + +#define RGPIO_PTOR_PTTO29_MASK (0x20000000U) +#define RGPIO_PTOR_PTTO29_SHIFT (29U) +/*! PTTO29 - Port Toggle Output + * 0b0..No change + * 0b1..Set to the inverse of its current logic state + */ +#define RGPIO_PTOR_PTTO29(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PTOR_PTTO29_SHIFT)) & RGPIO_PTOR_PTTO29_MASK) + +#define RGPIO_PTOR_PTTO30_MASK (0x40000000U) +#define RGPIO_PTOR_PTTO30_SHIFT (30U) +/*! PTTO30 - Port Toggle Output + * 0b0..No change + * 0b1..Set to the inverse of its current logic state + */ +#define RGPIO_PTOR_PTTO30(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PTOR_PTTO30_SHIFT)) & RGPIO_PTOR_PTTO30_MASK) + +#define RGPIO_PTOR_PTTO31_MASK (0x80000000U) +#define RGPIO_PTOR_PTTO31_SHIFT (31U) +/*! PTTO31 - Port Toggle Output + * 0b0..No change + * 0b1..Set to the inverse of its current logic state + */ +#define RGPIO_PTOR_PTTO31(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PTOR_PTTO31_SHIFT)) & RGPIO_PTOR_PTTO31_MASK) +/*! @} */ + +/*! @name PDIR - Port Data Input */ +/*! @{ */ + +#define RGPIO_PDIR_PDI0_MASK (0x1U) +#define RGPIO_PDIR_PDI0_SHIFT (0U) +/*! PDI0 - Port Data Input + * 0b0..Logic 0 + * 0b1..Logic 1 + */ +#define RGPIO_PDIR_PDI0(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDIR_PDI0_SHIFT)) & RGPIO_PDIR_PDI0_MASK) + +#define RGPIO_PDIR_PDI1_MASK (0x2U) +#define RGPIO_PDIR_PDI1_SHIFT (1U) +/*! PDI1 - Port Data Input + * 0b0..Logic 0 + * 0b1..Logic 1 + */ +#define RGPIO_PDIR_PDI1(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDIR_PDI1_SHIFT)) & RGPIO_PDIR_PDI1_MASK) + +#define RGPIO_PDIR_PDI2_MASK (0x4U) +#define RGPIO_PDIR_PDI2_SHIFT (2U) +/*! PDI2 - Port Data Input + * 0b0..Logic 0 + * 0b1..Logic 1 + */ +#define RGPIO_PDIR_PDI2(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDIR_PDI2_SHIFT)) & RGPIO_PDIR_PDI2_MASK) + +#define RGPIO_PDIR_PDI3_MASK (0x8U) +#define RGPIO_PDIR_PDI3_SHIFT (3U) +/*! PDI3 - Port Data Input + * 0b0..Logic 0 + * 0b1..Logic 1 + */ +#define RGPIO_PDIR_PDI3(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDIR_PDI3_SHIFT)) & RGPIO_PDIR_PDI3_MASK) + +#define RGPIO_PDIR_PDI4_MASK (0x10U) +#define RGPIO_PDIR_PDI4_SHIFT (4U) +/*! PDI4 - Port Data Input + * 0b0..Logic 0 + * 0b1..Logic 1 + */ +#define RGPIO_PDIR_PDI4(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDIR_PDI4_SHIFT)) & RGPIO_PDIR_PDI4_MASK) + +#define RGPIO_PDIR_PDI5_MASK (0x20U) +#define RGPIO_PDIR_PDI5_SHIFT (5U) +/*! PDI5 - Port Data Input + * 0b0..Logic 0 + * 0b1..Logic 1 + */ +#define RGPIO_PDIR_PDI5(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDIR_PDI5_SHIFT)) & RGPIO_PDIR_PDI5_MASK) + +#define RGPIO_PDIR_PDI6_MASK (0x40U) +#define RGPIO_PDIR_PDI6_SHIFT (6U) +/*! PDI6 - Port Data Input + * 0b0..Logic 0 + * 0b1..Logic 1 + */ +#define RGPIO_PDIR_PDI6(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDIR_PDI6_SHIFT)) & RGPIO_PDIR_PDI6_MASK) + +#define RGPIO_PDIR_PDI7_MASK (0x80U) +#define RGPIO_PDIR_PDI7_SHIFT (7U) +/*! PDI7 - Port Data Input + * 0b0..Logic 0 + * 0b1..Logic 1 + */ +#define RGPIO_PDIR_PDI7(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDIR_PDI7_SHIFT)) & RGPIO_PDIR_PDI7_MASK) + +#define RGPIO_PDIR_PDI8_MASK (0x100U) +#define RGPIO_PDIR_PDI8_SHIFT (8U) +/*! PDI8 - Port Data Input + * 0b0..Logic 0 + * 0b1..Logic 1 + */ +#define RGPIO_PDIR_PDI8(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDIR_PDI8_SHIFT)) & RGPIO_PDIR_PDI8_MASK) + +#define RGPIO_PDIR_PDI9_MASK (0x200U) +#define RGPIO_PDIR_PDI9_SHIFT (9U) +/*! PDI9 - Port Data Input + * 0b0..Logic 0 + * 0b1..Logic 1 + */ +#define RGPIO_PDIR_PDI9(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDIR_PDI9_SHIFT)) & RGPIO_PDIR_PDI9_MASK) + +#define RGPIO_PDIR_PDI10_MASK (0x400U) +#define RGPIO_PDIR_PDI10_SHIFT (10U) +/*! PDI10 - Port Data Input + * 0b0..Logic 0 + * 0b1..Logic 1 + */ +#define RGPIO_PDIR_PDI10(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDIR_PDI10_SHIFT)) & RGPIO_PDIR_PDI10_MASK) + +#define RGPIO_PDIR_PDI11_MASK (0x800U) +#define RGPIO_PDIR_PDI11_SHIFT (11U) +/*! PDI11 - Port Data Input + * 0b0..Logic 0 + * 0b1..Logic 1 + */ +#define RGPIO_PDIR_PDI11(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDIR_PDI11_SHIFT)) & RGPIO_PDIR_PDI11_MASK) + +#define RGPIO_PDIR_PDI12_MASK (0x1000U) +#define RGPIO_PDIR_PDI12_SHIFT (12U) +/*! PDI12 - Port Data Input + * 0b0..Logic 0 + * 0b1..Logic 1 + */ +#define RGPIO_PDIR_PDI12(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDIR_PDI12_SHIFT)) & RGPIO_PDIR_PDI12_MASK) + +#define RGPIO_PDIR_PDI13_MASK (0x2000U) +#define RGPIO_PDIR_PDI13_SHIFT (13U) +/*! PDI13 - Port Data Input + * 0b0..Logic 0 + * 0b1..Logic 1 + */ +#define RGPIO_PDIR_PDI13(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDIR_PDI13_SHIFT)) & RGPIO_PDIR_PDI13_MASK) + +#define RGPIO_PDIR_PDI14_MASK (0x4000U) +#define RGPIO_PDIR_PDI14_SHIFT (14U) +/*! PDI14 - Port Data Input + * 0b0..Logic 0 + * 0b1..Logic 1 + */ +#define RGPIO_PDIR_PDI14(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDIR_PDI14_SHIFT)) & RGPIO_PDIR_PDI14_MASK) + +#define RGPIO_PDIR_PDI15_MASK (0x8000U) +#define RGPIO_PDIR_PDI15_SHIFT (15U) +/*! PDI15 - Port Data Input + * 0b0..Logic 0 + * 0b1..Logic 1 + */ +#define RGPIO_PDIR_PDI15(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDIR_PDI15_SHIFT)) & RGPIO_PDIR_PDI15_MASK) + +#define RGPIO_PDIR_PDI16_MASK (0x10000U) +#define RGPIO_PDIR_PDI16_SHIFT (16U) +/*! PDI16 - Port Data Input + * 0b0..Logic 0 + * 0b1..Logic 1 + */ +#define RGPIO_PDIR_PDI16(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDIR_PDI16_SHIFT)) & RGPIO_PDIR_PDI16_MASK) + +#define RGPIO_PDIR_PDI17_MASK (0x20000U) +#define RGPIO_PDIR_PDI17_SHIFT (17U) +/*! PDI17 - Port Data Input + * 0b0..Logic 0 + * 0b1..Logic 1 + */ +#define RGPIO_PDIR_PDI17(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDIR_PDI17_SHIFT)) & RGPIO_PDIR_PDI17_MASK) + +#define RGPIO_PDIR_PDI18_MASK (0x40000U) +#define RGPIO_PDIR_PDI18_SHIFT (18U) +/*! PDI18 - Port Data Input + * 0b0..Logic 0 + * 0b1..Logic 1 + */ +#define RGPIO_PDIR_PDI18(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDIR_PDI18_SHIFT)) & RGPIO_PDIR_PDI18_MASK) + +#define RGPIO_PDIR_PDI19_MASK (0x80000U) +#define RGPIO_PDIR_PDI19_SHIFT (19U) +/*! PDI19 - Port Data Input + * 0b0..Logic 0 + * 0b1..Logic 1 + */ +#define RGPIO_PDIR_PDI19(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDIR_PDI19_SHIFT)) & RGPIO_PDIR_PDI19_MASK) + +#define RGPIO_PDIR_PDI20_MASK (0x100000U) +#define RGPIO_PDIR_PDI20_SHIFT (20U) +/*! PDI20 - Port Data Input + * 0b0..Logic 0 + * 0b1..Logic 1 + */ +#define RGPIO_PDIR_PDI20(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDIR_PDI20_SHIFT)) & RGPIO_PDIR_PDI20_MASK) + +#define RGPIO_PDIR_PDI21_MASK (0x200000U) +#define RGPIO_PDIR_PDI21_SHIFT (21U) +/*! PDI21 - Port Data Input + * 0b0..Logic 0 + * 0b1..Logic 1 + */ +#define RGPIO_PDIR_PDI21(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDIR_PDI21_SHIFT)) & RGPIO_PDIR_PDI21_MASK) + +#define RGPIO_PDIR_PDI22_MASK (0x400000U) +#define RGPIO_PDIR_PDI22_SHIFT (22U) +/*! PDI22 - Port Data Input + * 0b0..Logic 0 + * 0b1..Logic 1 + */ +#define RGPIO_PDIR_PDI22(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDIR_PDI22_SHIFT)) & RGPIO_PDIR_PDI22_MASK) + +#define RGPIO_PDIR_PDI23_MASK (0x800000U) +#define RGPIO_PDIR_PDI23_SHIFT (23U) +/*! PDI23 - Port Data Input + * 0b0..Logic 0 + * 0b1..Logic 1 + */ +#define RGPIO_PDIR_PDI23(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDIR_PDI23_SHIFT)) & RGPIO_PDIR_PDI23_MASK) + +#define RGPIO_PDIR_PDI24_MASK (0x1000000U) +#define RGPIO_PDIR_PDI24_SHIFT (24U) +/*! PDI24 - Port Data Input + * 0b0..Logic 0 + * 0b1..Logic 1 + */ +#define RGPIO_PDIR_PDI24(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDIR_PDI24_SHIFT)) & RGPIO_PDIR_PDI24_MASK) + +#define RGPIO_PDIR_PDI25_MASK (0x2000000U) +#define RGPIO_PDIR_PDI25_SHIFT (25U) +/*! PDI25 - Port Data Input + * 0b0..Logic 0 + * 0b1..Logic 1 + */ +#define RGPIO_PDIR_PDI25(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDIR_PDI25_SHIFT)) & RGPIO_PDIR_PDI25_MASK) + +#define RGPIO_PDIR_PDI26_MASK (0x4000000U) +#define RGPIO_PDIR_PDI26_SHIFT (26U) +/*! PDI26 - Port Data Input + * 0b0..Logic 0 + * 0b1..Logic 1 + */ +#define RGPIO_PDIR_PDI26(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDIR_PDI26_SHIFT)) & RGPIO_PDIR_PDI26_MASK) + +#define RGPIO_PDIR_PDI27_MASK (0x8000000U) +#define RGPIO_PDIR_PDI27_SHIFT (27U) +/*! PDI27 - Port Data Input + * 0b0..Logic 0 + * 0b1..Logic 1 + */ +#define RGPIO_PDIR_PDI27(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDIR_PDI27_SHIFT)) & RGPIO_PDIR_PDI27_MASK) + +#define RGPIO_PDIR_PDI28_MASK (0x10000000U) +#define RGPIO_PDIR_PDI28_SHIFT (28U) +/*! PDI28 - Port Data Input + * 0b0..Logic 0 + * 0b1..Logic 1 + */ +#define RGPIO_PDIR_PDI28(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDIR_PDI28_SHIFT)) & RGPIO_PDIR_PDI28_MASK) + +#define RGPIO_PDIR_PDI29_MASK (0x20000000U) +#define RGPIO_PDIR_PDI29_SHIFT (29U) +/*! PDI29 - Port Data Input + * 0b0..Logic 0 + * 0b1..Logic 1 + */ +#define RGPIO_PDIR_PDI29(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDIR_PDI29_SHIFT)) & RGPIO_PDIR_PDI29_MASK) + +#define RGPIO_PDIR_PDI30_MASK (0x40000000U) +#define RGPIO_PDIR_PDI30_SHIFT (30U) +/*! PDI30 - Port Data Input + * 0b0..Logic 0 + * 0b1..Logic 1 + */ +#define RGPIO_PDIR_PDI30(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDIR_PDI30_SHIFT)) & RGPIO_PDIR_PDI30_MASK) + +#define RGPIO_PDIR_PDI31_MASK (0x80000000U) +#define RGPIO_PDIR_PDI31_SHIFT (31U) +/*! PDI31 - Port Data Input + * 0b0..Logic 0 + * 0b1..Logic 1 + */ +#define RGPIO_PDIR_PDI31(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDIR_PDI31_SHIFT)) & RGPIO_PDIR_PDI31_MASK) +/*! @} */ + +/*! @name PDDR - Port Data Direction */ +/*! @{ */ + +#define RGPIO_PDDR_PDD0_MASK (0x1U) +#define RGPIO_PDDR_PDD0_SHIFT (0U) +/*! PDD0 - Port Data Direction + * 0b0..Input + * 0b1..Output + */ +#define RGPIO_PDDR_PDD0(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDDR_PDD0_SHIFT)) & RGPIO_PDDR_PDD0_MASK) + +#define RGPIO_PDDR_PDD1_MASK (0x2U) +#define RGPIO_PDDR_PDD1_SHIFT (1U) +/*! PDD1 - Port Data Direction + * 0b0..Input + * 0b1..Output + */ +#define RGPIO_PDDR_PDD1(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDDR_PDD1_SHIFT)) & RGPIO_PDDR_PDD1_MASK) + +#define RGPIO_PDDR_PDD2_MASK (0x4U) +#define RGPIO_PDDR_PDD2_SHIFT (2U) +/*! PDD2 - Port Data Direction + * 0b0..Input + * 0b1..Output + */ +#define RGPIO_PDDR_PDD2(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDDR_PDD2_SHIFT)) & RGPIO_PDDR_PDD2_MASK) + +#define RGPIO_PDDR_PDD3_MASK (0x8U) +#define RGPIO_PDDR_PDD3_SHIFT (3U) +/*! PDD3 - Port Data Direction + * 0b0..Input + * 0b1..Output + */ +#define RGPIO_PDDR_PDD3(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDDR_PDD3_SHIFT)) & RGPIO_PDDR_PDD3_MASK) + +#define RGPIO_PDDR_PDD4_MASK (0x10U) +#define RGPIO_PDDR_PDD4_SHIFT (4U) +/*! PDD4 - Port Data Direction + * 0b0..Input + * 0b1..Output + */ +#define RGPIO_PDDR_PDD4(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDDR_PDD4_SHIFT)) & RGPIO_PDDR_PDD4_MASK) + +#define RGPIO_PDDR_PDD5_MASK (0x20U) +#define RGPIO_PDDR_PDD5_SHIFT (5U) +/*! PDD5 - Port Data Direction + * 0b0..Input + * 0b1..Output + */ +#define RGPIO_PDDR_PDD5(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDDR_PDD5_SHIFT)) & RGPIO_PDDR_PDD5_MASK) + +#define RGPIO_PDDR_PDD6_MASK (0x40U) +#define RGPIO_PDDR_PDD6_SHIFT (6U) +/*! PDD6 - Port Data Direction + * 0b0..Input + * 0b1..Output + */ +#define RGPIO_PDDR_PDD6(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDDR_PDD6_SHIFT)) & RGPIO_PDDR_PDD6_MASK) + +#define RGPIO_PDDR_PDD7_MASK (0x80U) +#define RGPIO_PDDR_PDD7_SHIFT (7U) +/*! PDD7 - Port Data Direction + * 0b0..Input + * 0b1..Output + */ +#define RGPIO_PDDR_PDD7(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDDR_PDD7_SHIFT)) & RGPIO_PDDR_PDD7_MASK) + +#define RGPIO_PDDR_PDD8_MASK (0x100U) +#define RGPIO_PDDR_PDD8_SHIFT (8U) +/*! PDD8 - Port Data Direction + * 0b0..Input + * 0b1..Output + */ +#define RGPIO_PDDR_PDD8(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDDR_PDD8_SHIFT)) & RGPIO_PDDR_PDD8_MASK) + +#define RGPIO_PDDR_PDD9_MASK (0x200U) +#define RGPIO_PDDR_PDD9_SHIFT (9U) +/*! PDD9 - Port Data Direction + * 0b0..Input + * 0b1..Output + */ +#define RGPIO_PDDR_PDD9(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDDR_PDD9_SHIFT)) & RGPIO_PDDR_PDD9_MASK) + +#define RGPIO_PDDR_PDD10_MASK (0x400U) +#define RGPIO_PDDR_PDD10_SHIFT (10U) +/*! PDD10 - Port Data Direction + * 0b0..Input + * 0b1..Output + */ +#define RGPIO_PDDR_PDD10(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDDR_PDD10_SHIFT)) & RGPIO_PDDR_PDD10_MASK) + +#define RGPIO_PDDR_PDD11_MASK (0x800U) +#define RGPIO_PDDR_PDD11_SHIFT (11U) +/*! PDD11 - Port Data Direction + * 0b0..Input + * 0b1..Output + */ +#define RGPIO_PDDR_PDD11(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDDR_PDD11_SHIFT)) & RGPIO_PDDR_PDD11_MASK) + +#define RGPIO_PDDR_PDD12_MASK (0x1000U) +#define RGPIO_PDDR_PDD12_SHIFT (12U) +/*! PDD12 - Port Data Direction + * 0b0..Input + * 0b1..Output + */ +#define RGPIO_PDDR_PDD12(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDDR_PDD12_SHIFT)) & RGPIO_PDDR_PDD12_MASK) + +#define RGPIO_PDDR_PDD13_MASK (0x2000U) +#define RGPIO_PDDR_PDD13_SHIFT (13U) +/*! PDD13 - Port Data Direction + * 0b0..Input + * 0b1..Output + */ +#define RGPIO_PDDR_PDD13(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDDR_PDD13_SHIFT)) & RGPIO_PDDR_PDD13_MASK) + +#define RGPIO_PDDR_PDD14_MASK (0x4000U) +#define RGPIO_PDDR_PDD14_SHIFT (14U) +/*! PDD14 - Port Data Direction + * 0b0..Input + * 0b1..Output + */ +#define RGPIO_PDDR_PDD14(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDDR_PDD14_SHIFT)) & RGPIO_PDDR_PDD14_MASK) + +#define RGPIO_PDDR_PDD15_MASK (0x8000U) +#define RGPIO_PDDR_PDD15_SHIFT (15U) +/*! PDD15 - Port Data Direction + * 0b0..Input + * 0b1..Output + */ +#define RGPIO_PDDR_PDD15(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDDR_PDD15_SHIFT)) & RGPIO_PDDR_PDD15_MASK) + +#define RGPIO_PDDR_PDD16_MASK (0x10000U) +#define RGPIO_PDDR_PDD16_SHIFT (16U) +/*! PDD16 - Port Data Direction + * 0b0..Input + * 0b1..Output + */ +#define RGPIO_PDDR_PDD16(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDDR_PDD16_SHIFT)) & RGPIO_PDDR_PDD16_MASK) + +#define RGPIO_PDDR_PDD17_MASK (0x20000U) +#define RGPIO_PDDR_PDD17_SHIFT (17U) +/*! PDD17 - Port Data Direction + * 0b0..Input + * 0b1..Output + */ +#define RGPIO_PDDR_PDD17(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDDR_PDD17_SHIFT)) & RGPIO_PDDR_PDD17_MASK) + +#define RGPIO_PDDR_PDD18_MASK (0x40000U) +#define RGPIO_PDDR_PDD18_SHIFT (18U) +/*! PDD18 - Port Data Direction + * 0b0..Input + * 0b1..Output + */ +#define RGPIO_PDDR_PDD18(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDDR_PDD18_SHIFT)) & RGPIO_PDDR_PDD18_MASK) + +#define RGPIO_PDDR_PDD19_MASK (0x80000U) +#define RGPIO_PDDR_PDD19_SHIFT (19U) +/*! PDD19 - Port Data Direction + * 0b0..Input + * 0b1..Output + */ +#define RGPIO_PDDR_PDD19(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDDR_PDD19_SHIFT)) & RGPIO_PDDR_PDD19_MASK) + +#define RGPIO_PDDR_PDD20_MASK (0x100000U) +#define RGPIO_PDDR_PDD20_SHIFT (20U) +/*! PDD20 - Port Data Direction + * 0b0..Input + * 0b1..Output + */ +#define RGPIO_PDDR_PDD20(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDDR_PDD20_SHIFT)) & RGPIO_PDDR_PDD20_MASK) + +#define RGPIO_PDDR_PDD21_MASK (0x200000U) +#define RGPIO_PDDR_PDD21_SHIFT (21U) +/*! PDD21 - Port Data Direction + * 0b0..Input + * 0b1..Output + */ +#define RGPIO_PDDR_PDD21(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDDR_PDD21_SHIFT)) & RGPIO_PDDR_PDD21_MASK) + +#define RGPIO_PDDR_PDD22_MASK (0x400000U) +#define RGPIO_PDDR_PDD22_SHIFT (22U) +/*! PDD22 - Port Data Direction + * 0b0..Input + * 0b1..Output + */ +#define RGPIO_PDDR_PDD22(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDDR_PDD22_SHIFT)) & RGPIO_PDDR_PDD22_MASK) + +#define RGPIO_PDDR_PDD23_MASK (0x800000U) +#define RGPIO_PDDR_PDD23_SHIFT (23U) +/*! PDD23 - Port Data Direction + * 0b0..Input + * 0b1..Output + */ +#define RGPIO_PDDR_PDD23(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDDR_PDD23_SHIFT)) & RGPIO_PDDR_PDD23_MASK) + +#define RGPIO_PDDR_PDD24_MASK (0x1000000U) +#define RGPIO_PDDR_PDD24_SHIFT (24U) +/*! PDD24 - Port Data Direction + * 0b0..Input + * 0b1..Output + */ +#define RGPIO_PDDR_PDD24(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDDR_PDD24_SHIFT)) & RGPIO_PDDR_PDD24_MASK) + +#define RGPIO_PDDR_PDD25_MASK (0x2000000U) +#define RGPIO_PDDR_PDD25_SHIFT (25U) +/*! PDD25 - Port Data Direction + * 0b0..Input + * 0b1..Output + */ +#define RGPIO_PDDR_PDD25(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDDR_PDD25_SHIFT)) & RGPIO_PDDR_PDD25_MASK) + +#define RGPIO_PDDR_PDD26_MASK (0x4000000U) +#define RGPIO_PDDR_PDD26_SHIFT (26U) +/*! PDD26 - Port Data Direction + * 0b0..Input + * 0b1..Output + */ +#define RGPIO_PDDR_PDD26(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDDR_PDD26_SHIFT)) & RGPIO_PDDR_PDD26_MASK) + +#define RGPIO_PDDR_PDD27_MASK (0x8000000U) +#define RGPIO_PDDR_PDD27_SHIFT (27U) +/*! PDD27 - Port Data Direction + * 0b0..Input + * 0b1..Output + */ +#define RGPIO_PDDR_PDD27(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDDR_PDD27_SHIFT)) & RGPIO_PDDR_PDD27_MASK) + +#define RGPIO_PDDR_PDD28_MASK (0x10000000U) +#define RGPIO_PDDR_PDD28_SHIFT (28U) +/*! PDD28 - Port Data Direction + * 0b0..Input + * 0b1..Output + */ +#define RGPIO_PDDR_PDD28(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDDR_PDD28_SHIFT)) & RGPIO_PDDR_PDD28_MASK) + +#define RGPIO_PDDR_PDD29_MASK (0x20000000U) +#define RGPIO_PDDR_PDD29_SHIFT (29U) +/*! PDD29 - Port Data Direction + * 0b0..Input + * 0b1..Output + */ +#define RGPIO_PDDR_PDD29(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDDR_PDD29_SHIFT)) & RGPIO_PDDR_PDD29_MASK) + +#define RGPIO_PDDR_PDD30_MASK (0x40000000U) +#define RGPIO_PDDR_PDD30_SHIFT (30U) +/*! PDD30 - Port Data Direction + * 0b0..Input + * 0b1..Output + */ +#define RGPIO_PDDR_PDD30(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDDR_PDD30_SHIFT)) & RGPIO_PDDR_PDD30_MASK) + +#define RGPIO_PDDR_PDD31_MASK (0x80000000U) +#define RGPIO_PDDR_PDD31_SHIFT (31U) +/*! PDD31 - Port Data Direction + * 0b0..Input + * 0b1..Output + */ +#define RGPIO_PDDR_PDD31(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDDR_PDD31_SHIFT)) & RGPIO_PDDR_PDD31_MASK) +/*! @} */ + +/*! @name PIDR - Port Input Disable */ +/*! @{ */ + +#define RGPIO_PIDR_PID0_MASK (0x1U) +#define RGPIO_PIDR_PID0_SHIFT (0U) +/*! PID0 - Port Input Disable + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input + */ +#define RGPIO_PIDR_PID0(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PIDR_PID0_SHIFT)) & RGPIO_PIDR_PID0_MASK) + +#define RGPIO_PIDR_PID1_MASK (0x2U) +#define RGPIO_PIDR_PID1_SHIFT (1U) +/*! PID1 - Port Input Disable + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input + */ +#define RGPIO_PIDR_PID1(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PIDR_PID1_SHIFT)) & RGPIO_PIDR_PID1_MASK) + +#define RGPIO_PIDR_PID2_MASK (0x4U) +#define RGPIO_PIDR_PID2_SHIFT (2U) +/*! PID2 - Port Input Disable + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input + */ +#define RGPIO_PIDR_PID2(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PIDR_PID2_SHIFT)) & RGPIO_PIDR_PID2_MASK) + +#define RGPIO_PIDR_PID3_MASK (0x8U) +#define RGPIO_PIDR_PID3_SHIFT (3U) +/*! PID3 - Port Input Disable + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input + */ +#define RGPIO_PIDR_PID3(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PIDR_PID3_SHIFT)) & RGPIO_PIDR_PID3_MASK) + +#define RGPIO_PIDR_PID4_MASK (0x10U) +#define RGPIO_PIDR_PID4_SHIFT (4U) +/*! PID4 - Port Input Disable + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input + */ +#define RGPIO_PIDR_PID4(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PIDR_PID4_SHIFT)) & RGPIO_PIDR_PID4_MASK) + +#define RGPIO_PIDR_PID5_MASK (0x20U) +#define RGPIO_PIDR_PID5_SHIFT (5U) +/*! PID5 - Port Input Disable + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input + */ +#define RGPIO_PIDR_PID5(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PIDR_PID5_SHIFT)) & RGPIO_PIDR_PID5_MASK) + +#define RGPIO_PIDR_PID6_MASK (0x40U) +#define RGPIO_PIDR_PID6_SHIFT (6U) +/*! PID6 - Port Input Disable + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input + */ +#define RGPIO_PIDR_PID6(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PIDR_PID6_SHIFT)) & RGPIO_PIDR_PID6_MASK) + +#define RGPIO_PIDR_PID7_MASK (0x80U) +#define RGPIO_PIDR_PID7_SHIFT (7U) +/*! PID7 - Port Input Disable + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input + */ +#define RGPIO_PIDR_PID7(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PIDR_PID7_SHIFT)) & RGPIO_PIDR_PID7_MASK) + +#define RGPIO_PIDR_PID8_MASK (0x100U) +#define RGPIO_PIDR_PID8_SHIFT (8U) +/*! PID8 - Port Input Disable + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input + */ +#define RGPIO_PIDR_PID8(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PIDR_PID8_SHIFT)) & RGPIO_PIDR_PID8_MASK) + +#define RGPIO_PIDR_PID9_MASK (0x200U) +#define RGPIO_PIDR_PID9_SHIFT (9U) +/*! PID9 - Port Input Disable + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input + */ +#define RGPIO_PIDR_PID9(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PIDR_PID9_SHIFT)) & RGPIO_PIDR_PID9_MASK) + +#define RGPIO_PIDR_PID10_MASK (0x400U) +#define RGPIO_PIDR_PID10_SHIFT (10U) +/*! PID10 - Port Input Disable + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input + */ +#define RGPIO_PIDR_PID10(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PIDR_PID10_SHIFT)) & RGPIO_PIDR_PID10_MASK) + +#define RGPIO_PIDR_PID11_MASK (0x800U) +#define RGPIO_PIDR_PID11_SHIFT (11U) +/*! PID11 - Port Input Disable + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input + */ +#define RGPIO_PIDR_PID11(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PIDR_PID11_SHIFT)) & RGPIO_PIDR_PID11_MASK) + +#define RGPIO_PIDR_PID12_MASK (0x1000U) +#define RGPIO_PIDR_PID12_SHIFT (12U) +/*! PID12 - Port Input Disable + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input + */ +#define RGPIO_PIDR_PID12(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PIDR_PID12_SHIFT)) & RGPIO_PIDR_PID12_MASK) + +#define RGPIO_PIDR_PID13_MASK (0x2000U) +#define RGPIO_PIDR_PID13_SHIFT (13U) +/*! PID13 - Port Input Disable + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input + */ +#define RGPIO_PIDR_PID13(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PIDR_PID13_SHIFT)) & RGPIO_PIDR_PID13_MASK) + +#define RGPIO_PIDR_PID14_MASK (0x4000U) +#define RGPIO_PIDR_PID14_SHIFT (14U) +/*! PID14 - Port Input Disable + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input + */ +#define RGPIO_PIDR_PID14(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PIDR_PID14_SHIFT)) & RGPIO_PIDR_PID14_MASK) + +#define RGPIO_PIDR_PID15_MASK (0x8000U) +#define RGPIO_PIDR_PID15_SHIFT (15U) +/*! PID15 - Port Input Disable + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input + */ +#define RGPIO_PIDR_PID15(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PIDR_PID15_SHIFT)) & RGPIO_PIDR_PID15_MASK) + +#define RGPIO_PIDR_PID16_MASK (0x10000U) +#define RGPIO_PIDR_PID16_SHIFT (16U) +/*! PID16 - Port Input Disable + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input + */ +#define RGPIO_PIDR_PID16(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PIDR_PID16_SHIFT)) & RGPIO_PIDR_PID16_MASK) + +#define RGPIO_PIDR_PID17_MASK (0x20000U) +#define RGPIO_PIDR_PID17_SHIFT (17U) +/*! PID17 - Port Input Disable + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input + */ +#define RGPIO_PIDR_PID17(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PIDR_PID17_SHIFT)) & RGPIO_PIDR_PID17_MASK) + +#define RGPIO_PIDR_PID18_MASK (0x40000U) +#define RGPIO_PIDR_PID18_SHIFT (18U) +/*! PID18 - Port Input Disable + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input + */ +#define RGPIO_PIDR_PID18(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PIDR_PID18_SHIFT)) & RGPIO_PIDR_PID18_MASK) + +#define RGPIO_PIDR_PID19_MASK (0x80000U) +#define RGPIO_PIDR_PID19_SHIFT (19U) +/*! PID19 - Port Input Disable + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input + */ +#define RGPIO_PIDR_PID19(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PIDR_PID19_SHIFT)) & RGPIO_PIDR_PID19_MASK) + +#define RGPIO_PIDR_PID20_MASK (0x100000U) +#define RGPIO_PIDR_PID20_SHIFT (20U) +/*! PID20 - Port Input Disable + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input + */ +#define RGPIO_PIDR_PID20(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PIDR_PID20_SHIFT)) & RGPIO_PIDR_PID20_MASK) + +#define RGPIO_PIDR_PID21_MASK (0x200000U) +#define RGPIO_PIDR_PID21_SHIFT (21U) +/*! PID21 - Port Input Disable + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input + */ +#define RGPIO_PIDR_PID21(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PIDR_PID21_SHIFT)) & RGPIO_PIDR_PID21_MASK) + +#define RGPIO_PIDR_PID22_MASK (0x400000U) +#define RGPIO_PIDR_PID22_SHIFT (22U) +/*! PID22 - Port Input Disable + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input + */ +#define RGPIO_PIDR_PID22(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PIDR_PID22_SHIFT)) & RGPIO_PIDR_PID22_MASK) + +#define RGPIO_PIDR_PID23_MASK (0x800000U) +#define RGPIO_PIDR_PID23_SHIFT (23U) +/*! PID23 - Port Input Disable + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input + */ +#define RGPIO_PIDR_PID23(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PIDR_PID23_SHIFT)) & RGPIO_PIDR_PID23_MASK) + +#define RGPIO_PIDR_PID24_MASK (0x1000000U) +#define RGPIO_PIDR_PID24_SHIFT (24U) +/*! PID24 - Port Input Disable + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input + */ +#define RGPIO_PIDR_PID24(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PIDR_PID24_SHIFT)) & RGPIO_PIDR_PID24_MASK) + +#define RGPIO_PIDR_PID25_MASK (0x2000000U) +#define RGPIO_PIDR_PID25_SHIFT (25U) +/*! PID25 - Port Input Disable + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input + */ +#define RGPIO_PIDR_PID25(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PIDR_PID25_SHIFT)) & RGPIO_PIDR_PID25_MASK) + +#define RGPIO_PIDR_PID26_MASK (0x4000000U) +#define RGPIO_PIDR_PID26_SHIFT (26U) +/*! PID26 - Port Input Disable + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input + */ +#define RGPIO_PIDR_PID26(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PIDR_PID26_SHIFT)) & RGPIO_PIDR_PID26_MASK) + +#define RGPIO_PIDR_PID27_MASK (0x8000000U) +#define RGPIO_PIDR_PID27_SHIFT (27U) +/*! PID27 - Port Input Disable + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input + */ +#define RGPIO_PIDR_PID27(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PIDR_PID27_SHIFT)) & RGPIO_PIDR_PID27_MASK) + +#define RGPIO_PIDR_PID28_MASK (0x10000000U) +#define RGPIO_PIDR_PID28_SHIFT (28U) +/*! PID28 - Port Input Disable + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input + */ +#define RGPIO_PIDR_PID28(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PIDR_PID28_SHIFT)) & RGPIO_PIDR_PID28_MASK) + +#define RGPIO_PIDR_PID29_MASK (0x20000000U) +#define RGPIO_PIDR_PID29_SHIFT (29U) +/*! PID29 - Port Input Disable + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input + */ +#define RGPIO_PIDR_PID29(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PIDR_PID29_SHIFT)) & RGPIO_PIDR_PID29_MASK) + +#define RGPIO_PIDR_PID30_MASK (0x40000000U) +#define RGPIO_PIDR_PID30_SHIFT (30U) +/*! PID30 - Port Input Disable + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input + */ +#define RGPIO_PIDR_PID30(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PIDR_PID30_SHIFT)) & RGPIO_PIDR_PID30_MASK) + +#define RGPIO_PIDR_PID31_MASK (0x80000000U) +#define RGPIO_PIDR_PID31_SHIFT (31U) +/*! PID31 - Port Input Disable + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input + */ +#define RGPIO_PIDR_PID31(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PIDR_PID31_SHIFT)) & RGPIO_PIDR_PID31_MASK) +/*! @} */ + +/*! @name PDR - Pin Data */ +/*! @{ */ + +#define RGPIO_PDR_PD_MASK (0x1U) +#define RGPIO_PDR_PD_SHIFT (0U) +/*! PD - Pin Data (I/O) + * 0b0..Logic zero + * 0b1..Logic one + */ +#define RGPIO_PDR_PD(x) (((uint8_t)(((uint8_t)(x)) << RGPIO_PDR_PD_SHIFT)) & RGPIO_PDR_PD_MASK) +/*! @} */ + +/* The count of RGPIO_PDR */ +#define RGPIO_PDR_COUNT (32U) + +/*! @name ICR - Interrupt Control 0..Interrupt Control 31 */ +/*! @{ */ + +#define RGPIO_ICR_IRQC_MASK (0xF0000U) +#define RGPIO_ICR_IRQC_SHIFT (16U) +/*! IRQC - Interrupt Configuration + * 0b0000..ISF is disabled + * 0b0001..ISF and DMA request on rising edge + * 0b0010..ISF and DMA request on falling edge + * 0b0011..ISF and DMA request on either edge + * 0b0100..Reserved + * 0b0101..ISF sets on rising edge + * 0b0110..ISF sets on falling edge + * 0b0111..ISF sets on either edge + * 0b1000..ISF and interrupt when logic 0 + * 0b1001..ISF and interrupt on rising edge + * 0b1010..ISF and interrupt on falling edge + * 0b1011..ISF and Interrupt on either edge + * 0b1100..ISF and interrupt when logic 1 + * 0b1101..Reserved + * 0b1110..Reserved + * 0b1111..Reserved + */ +#define RGPIO_ICR_IRQC(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_ICR_IRQC_SHIFT)) & RGPIO_ICR_IRQC_MASK) + +#define RGPIO_ICR_IRQS_MASK (0x100000U) +#define RGPIO_ICR_IRQS_SHIFT (20U) +/*! IRQS - Interrupt Select + * 0b0..Interrupt, or DMA request 0 + * 0b1..Interrupt, or DMA request 1 + */ +#define RGPIO_ICR_IRQS(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_ICR_IRQS_SHIFT)) & RGPIO_ICR_IRQS_MASK) + +#define RGPIO_ICR_LK_MASK (0x800000U) +#define RGPIO_ICR_LK_SHIFT (23U) +/*! LK - Lock + * 0b0..Not locked + * 0b1..Locked + */ +#define RGPIO_ICR_LK(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_ICR_LK_SHIFT)) & RGPIO_ICR_LK_MASK) + +#define RGPIO_ICR_ISF_MASK (0x1000000U) +#define RGPIO_ICR_ISF_SHIFT (24U) +/*! ISF - Interrupt Status Flag + * 0b0..Not detected + * 0b0..No effect + * 0b1..Detected + * 0b1..Clear the flag + */ +#define RGPIO_ICR_ISF(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_ICR_ISF_SHIFT)) & RGPIO_ICR_ISF_MASK) +/*! @} */ + +/* The count of RGPIO_ICR */ +#define RGPIO_ICR_COUNT (32U) + +/*! @name GICLR - Global Interrupt Control Low */ +/*! @{ */ + +#define RGPIO_GICLR_GIWE0_MASK (0x1U) +#define RGPIO_GICLR_GIWE0_SHIFT (0U) +/*! GIWE0 - Global Interrupt Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define RGPIO_GICLR_GIWE0(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_GICLR_GIWE0_SHIFT)) & RGPIO_GICLR_GIWE0_MASK) + +#define RGPIO_GICLR_GIWE1_MASK (0x2U) +#define RGPIO_GICLR_GIWE1_SHIFT (1U) +/*! GIWE1 - Global Interrupt Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define RGPIO_GICLR_GIWE1(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_GICLR_GIWE1_SHIFT)) & RGPIO_GICLR_GIWE1_MASK) + +#define RGPIO_GICLR_GIWE2_MASK (0x4U) +#define RGPIO_GICLR_GIWE2_SHIFT (2U) +/*! GIWE2 - Global Interrupt Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define RGPIO_GICLR_GIWE2(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_GICLR_GIWE2_SHIFT)) & RGPIO_GICLR_GIWE2_MASK) + +#define RGPIO_GICLR_GIWE3_MASK (0x8U) +#define RGPIO_GICLR_GIWE3_SHIFT (3U) +/*! GIWE3 - Global Interrupt Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define RGPIO_GICLR_GIWE3(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_GICLR_GIWE3_SHIFT)) & RGPIO_GICLR_GIWE3_MASK) + +#define RGPIO_GICLR_GIWE4_MASK (0x10U) +#define RGPIO_GICLR_GIWE4_SHIFT (4U) +/*! GIWE4 - Global Interrupt Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define RGPIO_GICLR_GIWE4(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_GICLR_GIWE4_SHIFT)) & RGPIO_GICLR_GIWE4_MASK) + +#define RGPIO_GICLR_GIWE5_MASK (0x20U) +#define RGPIO_GICLR_GIWE5_SHIFT (5U) +/*! GIWE5 - Global Interrupt Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define RGPIO_GICLR_GIWE5(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_GICLR_GIWE5_SHIFT)) & RGPIO_GICLR_GIWE5_MASK) + +#define RGPIO_GICLR_GIWE6_MASK (0x40U) +#define RGPIO_GICLR_GIWE6_SHIFT (6U) +/*! GIWE6 - Global Interrupt Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define RGPIO_GICLR_GIWE6(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_GICLR_GIWE6_SHIFT)) & RGPIO_GICLR_GIWE6_MASK) + +#define RGPIO_GICLR_GIWE7_MASK (0x80U) +#define RGPIO_GICLR_GIWE7_SHIFT (7U) +/*! GIWE7 - Global Interrupt Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define RGPIO_GICLR_GIWE7(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_GICLR_GIWE7_SHIFT)) & RGPIO_GICLR_GIWE7_MASK) + +#define RGPIO_GICLR_GIWE8_MASK (0x100U) +#define RGPIO_GICLR_GIWE8_SHIFT (8U) +/*! GIWE8 - Global Interrupt Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define RGPIO_GICLR_GIWE8(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_GICLR_GIWE8_SHIFT)) & RGPIO_GICLR_GIWE8_MASK) + +#define RGPIO_GICLR_GIWE9_MASK (0x200U) +#define RGPIO_GICLR_GIWE9_SHIFT (9U) +/*! GIWE9 - Global Interrupt Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define RGPIO_GICLR_GIWE9(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_GICLR_GIWE9_SHIFT)) & RGPIO_GICLR_GIWE9_MASK) + +#define RGPIO_GICLR_GIWE10_MASK (0x400U) +#define RGPIO_GICLR_GIWE10_SHIFT (10U) +/*! GIWE10 - Global Interrupt Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define RGPIO_GICLR_GIWE10(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_GICLR_GIWE10_SHIFT)) & RGPIO_GICLR_GIWE10_MASK) + +#define RGPIO_GICLR_GIWE11_MASK (0x800U) +#define RGPIO_GICLR_GIWE11_SHIFT (11U) +/*! GIWE11 - Global Interrupt Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define RGPIO_GICLR_GIWE11(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_GICLR_GIWE11_SHIFT)) & RGPIO_GICLR_GIWE11_MASK) + +#define RGPIO_GICLR_GIWE12_MASK (0x1000U) +#define RGPIO_GICLR_GIWE12_SHIFT (12U) +/*! GIWE12 - Global Interrupt Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define RGPIO_GICLR_GIWE12(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_GICLR_GIWE12_SHIFT)) & RGPIO_GICLR_GIWE12_MASK) + +#define RGPIO_GICLR_GIWE13_MASK (0x2000U) +#define RGPIO_GICLR_GIWE13_SHIFT (13U) +/*! GIWE13 - Global Interrupt Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define RGPIO_GICLR_GIWE13(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_GICLR_GIWE13_SHIFT)) & RGPIO_GICLR_GIWE13_MASK) + +#define RGPIO_GICLR_GIWE14_MASK (0x4000U) +#define RGPIO_GICLR_GIWE14_SHIFT (14U) +/*! GIWE14 - Global Interrupt Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define RGPIO_GICLR_GIWE14(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_GICLR_GIWE14_SHIFT)) & RGPIO_GICLR_GIWE14_MASK) + +#define RGPIO_GICLR_GIWE15_MASK (0x8000U) +#define RGPIO_GICLR_GIWE15_SHIFT (15U) +/*! GIWE15 - Global Interrupt Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define RGPIO_GICLR_GIWE15(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_GICLR_GIWE15_SHIFT)) & RGPIO_GICLR_GIWE15_MASK) + +#define RGPIO_GICLR_GIWD_MASK (0xFFFF0000U) +#define RGPIO_GICLR_GIWD_SHIFT (16U) +/*! GIWD - Global Interrupt Write Data */ +#define RGPIO_GICLR_GIWD(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_GICLR_GIWD_SHIFT)) & RGPIO_GICLR_GIWD_MASK) +/*! @} */ + +/*! @name GICHR - Global Interrupt Control High */ +/*! @{ */ + +#define RGPIO_GICHR_GIWE16_MASK (0x1U) +#define RGPIO_GICHR_GIWE16_SHIFT (0U) +/*! GIWE16 - Global Interrupt Write Enable + * 0b0..Not updated. + * 0b1..Updated + */ +#define RGPIO_GICHR_GIWE16(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_GICHR_GIWE16_SHIFT)) & RGPIO_GICHR_GIWE16_MASK) + +#define RGPIO_GICHR_GIWE17_MASK (0x2U) +#define RGPIO_GICHR_GIWE17_SHIFT (1U) +/*! GIWE17 - Global Interrupt Write Enable + * 0b0..Not updated. + * 0b1..Updated + */ +#define RGPIO_GICHR_GIWE17(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_GICHR_GIWE17_SHIFT)) & RGPIO_GICHR_GIWE17_MASK) + +#define RGPIO_GICHR_GIWE18_MASK (0x4U) +#define RGPIO_GICHR_GIWE18_SHIFT (2U) +/*! GIWE18 - Global Interrupt Write Enable + * 0b0..Not updated. + * 0b1..Updated + */ +#define RGPIO_GICHR_GIWE18(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_GICHR_GIWE18_SHIFT)) & RGPIO_GICHR_GIWE18_MASK) + +#define RGPIO_GICHR_GIWE19_MASK (0x8U) +#define RGPIO_GICHR_GIWE19_SHIFT (3U) +/*! GIWE19 - Global Interrupt Write Enable + * 0b0..Not updated. + * 0b1..Updated + */ +#define RGPIO_GICHR_GIWE19(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_GICHR_GIWE19_SHIFT)) & RGPIO_GICHR_GIWE19_MASK) + +#define RGPIO_GICHR_GIWE20_MASK (0x10U) +#define RGPIO_GICHR_GIWE20_SHIFT (4U) +/*! GIWE20 - Global Interrupt Write Enable + * 0b0..Not updated. + * 0b1..Updated + */ +#define RGPIO_GICHR_GIWE20(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_GICHR_GIWE20_SHIFT)) & RGPIO_GICHR_GIWE20_MASK) + +#define RGPIO_GICHR_GIWE21_MASK (0x20U) +#define RGPIO_GICHR_GIWE21_SHIFT (5U) +/*! GIWE21 - Global Interrupt Write Enable + * 0b0..Not updated. + * 0b1..Updated + */ +#define RGPIO_GICHR_GIWE21(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_GICHR_GIWE21_SHIFT)) & RGPIO_GICHR_GIWE21_MASK) + +#define RGPIO_GICHR_GIWE22_MASK (0x40U) +#define RGPIO_GICHR_GIWE22_SHIFT (6U) +/*! GIWE22 - Global Interrupt Write Enable + * 0b0..Not updated. + * 0b1..Updated + */ +#define RGPIO_GICHR_GIWE22(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_GICHR_GIWE22_SHIFT)) & RGPIO_GICHR_GIWE22_MASK) + +#define RGPIO_GICHR_GIWE23_MASK (0x80U) +#define RGPIO_GICHR_GIWE23_SHIFT (7U) +/*! GIWE23 - Global Interrupt Write Enable + * 0b0..Not updated. + * 0b1..Updated + */ +#define RGPIO_GICHR_GIWE23(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_GICHR_GIWE23_SHIFT)) & RGPIO_GICHR_GIWE23_MASK) + +#define RGPIO_GICHR_GIWE24_MASK (0x100U) +#define RGPIO_GICHR_GIWE24_SHIFT (8U) +/*! GIWE24 - Global Interrupt Write Enable + * 0b0..Not updated. + * 0b1..Updated + */ +#define RGPIO_GICHR_GIWE24(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_GICHR_GIWE24_SHIFT)) & RGPIO_GICHR_GIWE24_MASK) + +#define RGPIO_GICHR_GIWE25_MASK (0x200U) +#define RGPIO_GICHR_GIWE25_SHIFT (9U) +/*! GIWE25 - Global Interrupt Write Enable + * 0b0..Not updated. + * 0b1..Updated + */ +#define RGPIO_GICHR_GIWE25(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_GICHR_GIWE25_SHIFT)) & RGPIO_GICHR_GIWE25_MASK) + +#define RGPIO_GICHR_GIWE26_MASK (0x400U) +#define RGPIO_GICHR_GIWE26_SHIFT (10U) +/*! GIWE26 - Global Interrupt Write Enable + * 0b0..Not updated. + * 0b1..Updated + */ +#define RGPIO_GICHR_GIWE26(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_GICHR_GIWE26_SHIFT)) & RGPIO_GICHR_GIWE26_MASK) + +#define RGPIO_GICHR_GIWE27_MASK (0x800U) +#define RGPIO_GICHR_GIWE27_SHIFT (11U) +/*! GIWE27 - Global Interrupt Write Enable + * 0b0..Not updated. + * 0b1..Updated + */ +#define RGPIO_GICHR_GIWE27(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_GICHR_GIWE27_SHIFT)) & RGPIO_GICHR_GIWE27_MASK) + +#define RGPIO_GICHR_GIWE28_MASK (0x1000U) +#define RGPIO_GICHR_GIWE28_SHIFT (12U) +/*! GIWE28 - Global Interrupt Write Enable + * 0b0..Not updated. + * 0b1..Updated + */ +#define RGPIO_GICHR_GIWE28(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_GICHR_GIWE28_SHIFT)) & RGPIO_GICHR_GIWE28_MASK) + +#define RGPIO_GICHR_GIWE29_MASK (0x2000U) +#define RGPIO_GICHR_GIWE29_SHIFT (13U) +/*! GIWE29 - Global Interrupt Write Enable + * 0b0..Not updated. + * 0b1..Updated + */ +#define RGPIO_GICHR_GIWE29(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_GICHR_GIWE29_SHIFT)) & RGPIO_GICHR_GIWE29_MASK) + +#define RGPIO_GICHR_GIWE30_MASK (0x4000U) +#define RGPIO_GICHR_GIWE30_SHIFT (14U) +/*! GIWE30 - Global Interrupt Write Enable + * 0b0..Not updated. + * 0b1..Updated + */ +#define RGPIO_GICHR_GIWE30(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_GICHR_GIWE30_SHIFT)) & RGPIO_GICHR_GIWE30_MASK) + +#define RGPIO_GICHR_GIWE31_MASK (0x8000U) +#define RGPIO_GICHR_GIWE31_SHIFT (15U) +/*! GIWE31 - Global Interrupt Write Enable + * 0b0..Not updated. + * 0b1..Updated + */ +#define RGPIO_GICHR_GIWE31(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_GICHR_GIWE31_SHIFT)) & RGPIO_GICHR_GIWE31_MASK) + +#define RGPIO_GICHR_GIWD_MASK (0xFFFF0000U) +#define RGPIO_GICHR_GIWD_SHIFT (16U) +/*! GIWD - Global Interrupt Write Data */ +#define RGPIO_GICHR_GIWD(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_GICHR_GIWD_SHIFT)) & RGPIO_GICHR_GIWD_MASK) +/*! @} */ + +/*! @name ISFR - Interrupt Status Flag */ +/*! @{ */ + +#define RGPIO_ISFR_ISF0_MASK (0x1U) +#define RGPIO_ISFR_ISF0_SHIFT (0U) +/*! ISF0 - Interrupt Status Flag + * 0b0..Not detected + * 0b0..No effect + * 0b1..Detected + * 0b1..Clear the flag + */ +#define RGPIO_ISFR_ISF0(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_ISFR_ISF0_SHIFT)) & RGPIO_ISFR_ISF0_MASK) + +#define RGPIO_ISFR_ISF1_MASK (0x2U) +#define RGPIO_ISFR_ISF1_SHIFT (1U) +/*! ISF1 - Interrupt Status Flag + * 0b0..Not detected + * 0b0..No effect + * 0b1..Detected + * 0b1..Clear the flag + */ +#define RGPIO_ISFR_ISF1(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_ISFR_ISF1_SHIFT)) & RGPIO_ISFR_ISF1_MASK) + +#define RGPIO_ISFR_ISF2_MASK (0x4U) +#define RGPIO_ISFR_ISF2_SHIFT (2U) +/*! ISF2 - Interrupt Status Flag + * 0b0..Not detected + * 0b0..No effect + * 0b1..Detected + * 0b1..Clear the flag + */ +#define RGPIO_ISFR_ISF2(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_ISFR_ISF2_SHIFT)) & RGPIO_ISFR_ISF2_MASK) + +#define RGPIO_ISFR_ISF3_MASK (0x8U) +#define RGPIO_ISFR_ISF3_SHIFT (3U) +/*! ISF3 - Interrupt Status Flag + * 0b0..Not detected + * 0b0..No effect + * 0b1..Detected + * 0b1..Clear the flag + */ +#define RGPIO_ISFR_ISF3(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_ISFR_ISF3_SHIFT)) & RGPIO_ISFR_ISF3_MASK) + +#define RGPIO_ISFR_ISF4_MASK (0x10U) +#define RGPIO_ISFR_ISF4_SHIFT (4U) +/*! ISF4 - Interrupt Status Flag + * 0b0..Not detected + * 0b0..No effect + * 0b1..Detected + * 0b1..Clear the flag + */ +#define RGPIO_ISFR_ISF4(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_ISFR_ISF4_SHIFT)) & RGPIO_ISFR_ISF4_MASK) + +#define RGPIO_ISFR_ISF5_MASK (0x20U) +#define RGPIO_ISFR_ISF5_SHIFT (5U) +/*! ISF5 - Interrupt Status Flag + * 0b0..Not detected + * 0b0..No effect + * 0b1..Detected + * 0b1..Clear the flag + */ +#define RGPIO_ISFR_ISF5(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_ISFR_ISF5_SHIFT)) & RGPIO_ISFR_ISF5_MASK) + +#define RGPIO_ISFR_ISF6_MASK (0x40U) +#define RGPIO_ISFR_ISF6_SHIFT (6U) +/*! ISF6 - Interrupt Status Flag + * 0b0..Not detected + * 0b0..No effect + * 0b1..Detected + * 0b1..Clear the flag + */ +#define RGPIO_ISFR_ISF6(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_ISFR_ISF6_SHIFT)) & RGPIO_ISFR_ISF6_MASK) + +#define RGPIO_ISFR_ISF7_MASK (0x80U) +#define RGPIO_ISFR_ISF7_SHIFT (7U) +/*! ISF7 - Interrupt Status Flag + * 0b0..Not detected + * 0b0..No effect + * 0b1..Detected + * 0b1..Clear the flag + */ +#define RGPIO_ISFR_ISF7(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_ISFR_ISF7_SHIFT)) & RGPIO_ISFR_ISF7_MASK) + +#define RGPIO_ISFR_ISF8_MASK (0x100U) +#define RGPIO_ISFR_ISF8_SHIFT (8U) +/*! ISF8 - Interrupt Status Flag + * 0b0..Not detected + * 0b0..No effect + * 0b1..Detected + * 0b1..Clear the flag + */ +#define RGPIO_ISFR_ISF8(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_ISFR_ISF8_SHIFT)) & RGPIO_ISFR_ISF8_MASK) + +#define RGPIO_ISFR_ISF9_MASK (0x200U) +#define RGPIO_ISFR_ISF9_SHIFT (9U) +/*! ISF9 - Interrupt Status Flag + * 0b0..Not detected + * 0b0..No effect + * 0b1..Detected + * 0b1..Clear the flag + */ +#define RGPIO_ISFR_ISF9(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_ISFR_ISF9_SHIFT)) & RGPIO_ISFR_ISF9_MASK) + +#define RGPIO_ISFR_ISF10_MASK (0x400U) +#define RGPIO_ISFR_ISF10_SHIFT (10U) +/*! ISF10 - Interrupt Status Flag + * 0b0..Not detected + * 0b0..No effect + * 0b1..Detected + * 0b1..Clear the flag + */ +#define RGPIO_ISFR_ISF10(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_ISFR_ISF10_SHIFT)) & RGPIO_ISFR_ISF10_MASK) + +#define RGPIO_ISFR_ISF11_MASK (0x800U) +#define RGPIO_ISFR_ISF11_SHIFT (11U) +/*! ISF11 - Interrupt Status Flag + * 0b0..Not detected + * 0b0..No effect + * 0b1..Detected + * 0b1..Clear the flag + */ +#define RGPIO_ISFR_ISF11(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_ISFR_ISF11_SHIFT)) & RGPIO_ISFR_ISF11_MASK) + +#define RGPIO_ISFR_ISF12_MASK (0x1000U) +#define RGPIO_ISFR_ISF12_SHIFT (12U) +/*! ISF12 - Interrupt Status Flag + * 0b0..Not detected + * 0b0..No effect + * 0b1..Detected + * 0b1..Clear the flag + */ +#define RGPIO_ISFR_ISF12(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_ISFR_ISF12_SHIFT)) & RGPIO_ISFR_ISF12_MASK) + +#define RGPIO_ISFR_ISF13_MASK (0x2000U) +#define RGPIO_ISFR_ISF13_SHIFT (13U) +/*! ISF13 - Interrupt Status Flag + * 0b0..Not detected + * 0b0..No effect + * 0b1..Detected + * 0b1..Clear the flag + */ +#define RGPIO_ISFR_ISF13(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_ISFR_ISF13_SHIFT)) & RGPIO_ISFR_ISF13_MASK) + +#define RGPIO_ISFR_ISF14_MASK (0x4000U) +#define RGPIO_ISFR_ISF14_SHIFT (14U) +/*! ISF14 - Interrupt Status Flag + * 0b0..Not detected + * 0b0..No effect + * 0b1..Detected + * 0b1..Clear the flag + */ +#define RGPIO_ISFR_ISF14(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_ISFR_ISF14_SHIFT)) & RGPIO_ISFR_ISF14_MASK) + +#define RGPIO_ISFR_ISF15_MASK (0x8000U) +#define RGPIO_ISFR_ISF15_SHIFT (15U) +/*! ISF15 - Interrupt Status Flag + * 0b0..Not detected + * 0b0..No effect + * 0b1..Detected + * 0b1..Clear the flag + */ +#define RGPIO_ISFR_ISF15(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_ISFR_ISF15_SHIFT)) & RGPIO_ISFR_ISF15_MASK) + +#define RGPIO_ISFR_ISF16_MASK (0x10000U) +#define RGPIO_ISFR_ISF16_SHIFT (16U) +/*! ISF16 - Interrupt Status Flag + * 0b0..Not detected + * 0b0..No effect + * 0b1..Detected + * 0b1..Clear the flag + */ +#define RGPIO_ISFR_ISF16(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_ISFR_ISF16_SHIFT)) & RGPIO_ISFR_ISF16_MASK) + +#define RGPIO_ISFR_ISF17_MASK (0x20000U) +#define RGPIO_ISFR_ISF17_SHIFT (17U) +/*! ISF17 - Interrupt Status Flag + * 0b0..Not detected + * 0b0..No effect + * 0b1..Detected + * 0b1..Clear the flag + */ +#define RGPIO_ISFR_ISF17(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_ISFR_ISF17_SHIFT)) & RGPIO_ISFR_ISF17_MASK) + +#define RGPIO_ISFR_ISF18_MASK (0x40000U) +#define RGPIO_ISFR_ISF18_SHIFT (18U) +/*! ISF18 - Interrupt Status Flag + * 0b0..Not detected + * 0b0..No effect + * 0b1..Detected + * 0b1..Clear the flag + */ +#define RGPIO_ISFR_ISF18(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_ISFR_ISF18_SHIFT)) & RGPIO_ISFR_ISF18_MASK) + +#define RGPIO_ISFR_ISF19_MASK (0x80000U) +#define RGPIO_ISFR_ISF19_SHIFT (19U) +/*! ISF19 - Interrupt Status Flag + * 0b0..Not detected + * 0b0..No effect + * 0b1..Detected + * 0b1..Clear the flag + */ +#define RGPIO_ISFR_ISF19(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_ISFR_ISF19_SHIFT)) & RGPIO_ISFR_ISF19_MASK) + +#define RGPIO_ISFR_ISF20_MASK (0x100000U) +#define RGPIO_ISFR_ISF20_SHIFT (20U) +/*! ISF20 - Interrupt Status Flag + * 0b0..Not detected + * 0b0..No effect + * 0b1..Detected + * 0b1..Clear the flag + */ +#define RGPIO_ISFR_ISF20(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_ISFR_ISF20_SHIFT)) & RGPIO_ISFR_ISF20_MASK) + +#define RGPIO_ISFR_ISF21_MASK (0x200000U) +#define RGPIO_ISFR_ISF21_SHIFT (21U) +/*! ISF21 - Interrupt Status Flag + * 0b0..Not detected + * 0b0..No effect + * 0b1..Detected + * 0b1..Clear the flag + */ +#define RGPIO_ISFR_ISF21(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_ISFR_ISF21_SHIFT)) & RGPIO_ISFR_ISF21_MASK) + +#define RGPIO_ISFR_ISF22_MASK (0x400000U) +#define RGPIO_ISFR_ISF22_SHIFT (22U) +/*! ISF22 - Interrupt Status Flag + * 0b0..Not detected + * 0b0..No effect + * 0b1..Detected + * 0b1..Clear the flag + */ +#define RGPIO_ISFR_ISF22(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_ISFR_ISF22_SHIFT)) & RGPIO_ISFR_ISF22_MASK) + +#define RGPIO_ISFR_ISF23_MASK (0x800000U) +#define RGPIO_ISFR_ISF23_SHIFT (23U) +/*! ISF23 - Interrupt Status Flag + * 0b0..Not detected + * 0b0..No effect + * 0b1..Detected + * 0b1..Clear the flag + */ +#define RGPIO_ISFR_ISF23(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_ISFR_ISF23_SHIFT)) & RGPIO_ISFR_ISF23_MASK) + +#define RGPIO_ISFR_ISF24_MASK (0x1000000U) +#define RGPIO_ISFR_ISF24_SHIFT (24U) +/*! ISF24 - Interrupt Status Flag + * 0b0..Not detected + * 0b0..No effect + * 0b1..Detected + * 0b1..Clear the flag + */ +#define RGPIO_ISFR_ISF24(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_ISFR_ISF24_SHIFT)) & RGPIO_ISFR_ISF24_MASK) + +#define RGPIO_ISFR_ISF25_MASK (0x2000000U) +#define RGPIO_ISFR_ISF25_SHIFT (25U) +/*! ISF25 - Interrupt Status Flag + * 0b0..Not detected + * 0b0..No effect + * 0b1..Detected + * 0b1..Clear the flag + */ +#define RGPIO_ISFR_ISF25(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_ISFR_ISF25_SHIFT)) & RGPIO_ISFR_ISF25_MASK) + +#define RGPIO_ISFR_ISF26_MASK (0x4000000U) +#define RGPIO_ISFR_ISF26_SHIFT (26U) +/*! ISF26 - Interrupt Status Flag + * 0b0..Not detected + * 0b0..No effect + * 0b1..Detected + * 0b1..Clear the flag + */ +#define RGPIO_ISFR_ISF26(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_ISFR_ISF26_SHIFT)) & RGPIO_ISFR_ISF26_MASK) + +#define RGPIO_ISFR_ISF27_MASK (0x8000000U) +#define RGPIO_ISFR_ISF27_SHIFT (27U) +/*! ISF27 - Interrupt Status Flag + * 0b0..Not detected + * 0b0..No effect + * 0b1..Detected + * 0b1..Clear the flag + */ +#define RGPIO_ISFR_ISF27(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_ISFR_ISF27_SHIFT)) & RGPIO_ISFR_ISF27_MASK) + +#define RGPIO_ISFR_ISF28_MASK (0x10000000U) +#define RGPIO_ISFR_ISF28_SHIFT (28U) +/*! ISF28 - Interrupt Status Flag + * 0b0..Not detected + * 0b0..No effect + * 0b1..Detected + * 0b1..Clear the flag + */ +#define RGPIO_ISFR_ISF28(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_ISFR_ISF28_SHIFT)) & RGPIO_ISFR_ISF28_MASK) + +#define RGPIO_ISFR_ISF29_MASK (0x20000000U) +#define RGPIO_ISFR_ISF29_SHIFT (29U) +/*! ISF29 - Interrupt Status Flag + * 0b0..Not detected + * 0b0..No effect + * 0b1..Detected + * 0b1..Clear the flag + */ +#define RGPIO_ISFR_ISF29(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_ISFR_ISF29_SHIFT)) & RGPIO_ISFR_ISF29_MASK) + +#define RGPIO_ISFR_ISF30_MASK (0x40000000U) +#define RGPIO_ISFR_ISF30_SHIFT (30U) +/*! ISF30 - Interrupt Status Flag + * 0b0..Not detected + * 0b0..No effect + * 0b1..Detected + * 0b1..Clear the flag + */ +#define RGPIO_ISFR_ISF30(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_ISFR_ISF30_SHIFT)) & RGPIO_ISFR_ISF30_MASK) + +#define RGPIO_ISFR_ISF31_MASK (0x80000000U) +#define RGPIO_ISFR_ISF31_SHIFT (31U) +/*! ISF31 - Interrupt Status Flag + * 0b0..Not detected + * 0b0..No effect + * 0b1..Detected + * 0b1..Clear the flag + */ +#define RGPIO_ISFR_ISF31(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_ISFR_ISF31_SHIFT)) & RGPIO_ISFR_ISF31_MASK) +/*! @} */ + +/* The count of RGPIO_ISFR */ +#define RGPIO_ISFR_COUNT (2U) + + +/*! + * @} + */ /* end of group RGPIO_Register_Masks */ + + +/* RGPIO - Peripheral instance base addresses */ +/** Peripheral GPIO1 base address */ +#define GPIO1_BASE (0x47400000u) +/** Peripheral GPIO1 base pointer */ +#define GPIO1 ((RGPIO_Type *)GPIO1_BASE) +/** Peripheral GPIO2 base address */ +#define GPIO2_BASE (0x43810000u) +/** Peripheral GPIO2 base pointer */ +#define GPIO2 ((RGPIO_Type *)GPIO2_BASE) +/** Peripheral GPIO3 base address */ +#define GPIO3_BASE (0x43820000u) +/** Peripheral GPIO3 base pointer */ +#define GPIO3 ((RGPIO_Type *)GPIO3_BASE) +/** Peripheral GPIO4 base address */ +#define GPIO4_BASE (0x43830000u) +/** Peripheral GPIO4 base pointer */ +#define GPIO4 ((RGPIO_Type *)GPIO4_BASE) +/** Array initializer of RGPIO peripheral base addresses */ +#define RGPIO_BASE_ADDRS { GPIO1_BASE, GPIO2_BASE, GPIO3_BASE, GPIO4_BASE } +/** Array initializer of RGPIO peripheral base pointers */ +#define RGPIO_BASE_PTRS { GPIO1, GPIO2, GPIO3, GPIO4 } +/** Interrupt vectors for the RGPIO peripheral type */ +#define RGPIO_IRQS { GPIO1_0_IRQn, GPIO2_0_IRQn, GPIO3_0_IRQn, GPIO4_0_IRQn } + +/*! + * @} + */ /* end of group RGPIO_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- SEMA42 Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SEMA42_Peripheral_Access_Layer SEMA42 Peripheral Access Layer + * @{ + */ + +/** SEMA42 - Register Layout Typedef */ +typedef struct { + __IO uint8_t GATE3; /**< Gate, offset: 0x0 */ + __IO uint8_t GATE2; /**< Gate, offset: 0x1 */ + __IO uint8_t GATE1; /**< Gate, offset: 0x2 */ + __IO uint8_t GATE0; /**< Gate, offset: 0x3 */ + __IO uint8_t GATE7; /**< Gate, offset: 0x4 */ + __IO uint8_t GATE6; /**< Gate, offset: 0x5 */ + __IO uint8_t GATE5; /**< Gate, offset: 0x6 */ + __IO uint8_t GATE4; /**< Gate, offset: 0x7 */ + __IO uint8_t GATE11; /**< Gate, offset: 0x8 */ + __IO uint8_t GATE10; /**< Gate, offset: 0x9 */ + __IO uint8_t GATE9; /**< Gate, offset: 0xA */ + __IO uint8_t GATE8; /**< Gate, offset: 0xB */ + __IO uint8_t GATE15; /**< Gate, offset: 0xC */ + __IO uint8_t GATE14; /**< Gate, offset: 0xD */ + __IO uint8_t GATE13; /**< Gate, offset: 0xE */ + __IO uint8_t GATE12; /**< Gate, offset: 0xF */ + __IO uint8_t GATE19; /**< Gate, offset: 0x10 */ + __IO uint8_t GATE18; /**< Gate, offset: 0x11 */ + __IO uint8_t GATE17; /**< Gate, offset: 0x12 */ + __IO uint8_t GATE16; /**< Gate, offset: 0x13 */ + __IO uint8_t GATE23; /**< Gate, offset: 0x14 */ + __IO uint8_t GATE22; /**< Gate, offset: 0x15 */ + __IO uint8_t GATE21; /**< Gate, offset: 0x16 */ + __IO uint8_t GATE20; /**< Gate, offset: 0x17 */ + __IO uint8_t GATE27; /**< Gate, offset: 0x18 */ + __IO uint8_t GATE26; /**< Gate, offset: 0x19 */ + __IO uint8_t GATE25; /**< Gate, offset: 0x1A */ + __IO uint8_t GATE24; /**< Gate, offset: 0x1B */ + __IO uint8_t GATE31; /**< Gate, offset: 0x1C */ + __IO uint8_t GATE30; /**< Gate, offset: 0x1D */ + __IO uint8_t GATE29; /**< Gate, offset: 0x1E */ + __IO uint8_t GATE28; /**< Gate, offset: 0x1F */ + __IO uint8_t GATE35; /**< Gate, offset: 0x20 */ + __IO uint8_t GATE34; /**< Gate, offset: 0x21 */ + __IO uint8_t GATE33; /**< Gate, offset: 0x22 */ + __IO uint8_t GATE32; /**< Gate, offset: 0x23 */ + __IO uint8_t GATE39; /**< Gate, offset: 0x24 */ + __IO uint8_t GATE38; /**< Gate, offset: 0x25 */ + __IO uint8_t GATE37; /**< Gate, offset: 0x26 */ + __IO uint8_t GATE36; /**< Gate, offset: 0x27 */ + __IO uint8_t GATE43; /**< Gate, offset: 0x28 */ + __IO uint8_t GATE42; /**< Gate, offset: 0x29 */ + __IO uint8_t GATE41; /**< Gate, offset: 0x2A */ + __IO uint8_t GATE40; /**< Gate, offset: 0x2B */ + __IO uint8_t GATE47; /**< Gate, offset: 0x2C */ + __IO uint8_t GATE46; /**< Gate, offset: 0x2D */ + __IO uint8_t GATE45; /**< Gate, offset: 0x2E */ + __IO uint8_t GATE44; /**< Gate, offset: 0x2F */ + __IO uint8_t GATE51; /**< Gate, offset: 0x30 */ + __IO uint8_t GATE50; /**< Gate, offset: 0x31 */ + __IO uint8_t GATE49; /**< Gate, offset: 0x32 */ + __IO uint8_t GATE48; /**< Gate, offset: 0x33 */ + __IO uint8_t GATE55; /**< Gate, offset: 0x34 */ + __IO uint8_t GATE54; /**< Gate, offset: 0x35 */ + __IO uint8_t GATE53; /**< Gate, offset: 0x36 */ + __IO uint8_t GATE52; /**< Gate, offset: 0x37 */ + __IO uint8_t GATE59; /**< Gate, offset: 0x38 */ + __IO uint8_t GATE58; /**< Gate, offset: 0x39 */ + __IO uint8_t GATE57; /**< Gate, offset: 0x3A */ + __IO uint8_t GATE56; /**< Gate, offset: 0x3B */ + __IO uint8_t GATE63; /**< Gate, offset: 0x3C */ + __IO uint8_t GATE62; /**< Gate, offset: 0x3D */ + __IO uint8_t GATE61; /**< Gate, offset: 0x3E */ + __IO uint8_t GATE60; /**< Gate, offset: 0x3F */ + uint8_t RESERVED_0[2]; + union { /* offset: 0x42 */ + __I uint16_t RSTGT_R; /**< Reset Gate Read, offset: 0x42 */ + __O uint16_t RSTGT_W; /**< Reset Gate Write, offset: 0x42 */ + }; +} SEMA42_Type; + +/* ---------------------------------------------------------------------------- + -- SEMA42 Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SEMA42_Register_Masks SEMA42 Register Masks + * @{ + */ + +/*! @name GATE3 - Gate */ +/*! @{ */ + +#define SEMA42_GATE3_GTFSM_MASK (0xFU) +#define SEMA42_GATE3_GTFSM_SHIFT (0U) +/*! GTFSM - Gate Finite State Machine + * 0b0000..The gate is unlocked (free). + * 0b0001..Domain 0 locked the gate. + * 0b0010..Domain 1 locked the gate. + * 0b0011..Domain 2 locked the gate. + * 0b0100..Domain 3 locked the gate. + * 0b0101..Domain 4 locked the gate. + * 0b0110..Domain 5 locked the gate. + * 0b0111..Domain 6 locked the gate. + * 0b1000..Domain 7 locked the gate. + * 0b1001..Domain 8 locked the gate. + * 0b1010..Domain 9 locked the gate. + * 0b1011..Domain 10 locked the gate. + * 0b1100..Domain 11 locked the gate. + * 0b1101..Domain 12 locked the gate. + * 0b1110..Domain 13 locked the gate. + * 0b1111..Domain 14 locked the gate. + */ +#define SEMA42_GATE3_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE3_GTFSM_SHIFT)) & SEMA42_GATE3_GTFSM_MASK) +/*! @} */ + +/*! @name GATE2 - Gate */ +/*! @{ */ + +#define SEMA42_GATE2_GTFSM_MASK (0xFU) +#define SEMA42_GATE2_GTFSM_SHIFT (0U) +/*! GTFSM - Gate Finite State Machine + * 0b0000..The gate is unlocked (free). + * 0b0001..Domain 0 locked the gate. + * 0b0010..Domain 1 locked the gate. + * 0b0011..Domain 2 locked the gate. + * 0b0100..Domain 3 locked the gate. + * 0b0101..Domain 4 locked the gate. + * 0b0110..Domain 5 locked the gate. + * 0b0111..Domain 6 locked the gate. + * 0b1000..Domain 7 locked the gate. + * 0b1001..Domain 8 locked the gate. + * 0b1010..Domain 9 locked the gate. + * 0b1011..Domain 10 locked the gate. + * 0b1100..Domain 11 locked the gate. + * 0b1101..Domain 12 locked the gate. + * 0b1110..Domain 13 locked the gate. + * 0b1111..Domain 14 locked the gate. + */ +#define SEMA42_GATE2_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE2_GTFSM_SHIFT)) & SEMA42_GATE2_GTFSM_MASK) +/*! @} */ + +/*! @name GATE1 - Gate */ +/*! @{ */ + +#define SEMA42_GATE1_GTFSM_MASK (0xFU) +#define SEMA42_GATE1_GTFSM_SHIFT (0U) +/*! GTFSM - Gate Finite State Machine + * 0b0000..The gate is unlocked (free). + * 0b0001..Domain 0 locked the gate. + * 0b0010..Domain 1 locked the gate. + * 0b0011..Domain 2 locked the gate. + * 0b0100..Domain 3 locked the gate. + * 0b0101..Domain 4 locked the gate. + * 0b0110..Domain 5 locked the gate. + * 0b0111..Domain 6 locked the gate. + * 0b1000..Domain 7 locked the gate. + * 0b1001..Domain 8 locked the gate. + * 0b1010..Domain 9 locked the gate. + * 0b1011..Domain 10 locked the gate. + * 0b1100..Domain 11 locked the gate. + * 0b1101..Domain 12 locked the gate. + * 0b1110..Domain 13 locked the gate. + * 0b1111..Domain 14 locked the gate. + */ +#define SEMA42_GATE1_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE1_GTFSM_SHIFT)) & SEMA42_GATE1_GTFSM_MASK) +/*! @} */ + +/*! @name GATE0 - Gate */ +/*! @{ */ + +#define SEMA42_GATE0_GTFSM_MASK (0xFU) +#define SEMA42_GATE0_GTFSM_SHIFT (0U) +/*! GTFSM - Gate Finite State Machine + * 0b0000..The gate is unlocked (free). + * 0b0001..Domain 0 locked the gate. + * 0b0010..Domain 1 locked the gate. + * 0b0011..Domain 2 locked the gate. + * 0b0100..Domain 3 locked the gate. + * 0b0101..Domain 4 locked the gate. + * 0b0110..Domain 5 locked the gate. + * 0b0111..Domain 6 locked the gate. + * 0b1000..Domain 7 locked the gate. + * 0b1001..Domain 8 locked the gate. + * 0b1010..Domain 9 locked the gate. + * 0b1011..Domain 10 locked the gate. + * 0b1100..Domain 11 locked the gate. + * 0b1101..Domain 12 locked the gate. + * 0b1110..Domain 13 locked the gate. + * 0b1111..Domain 14 locked the gate. + */ +#define SEMA42_GATE0_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE0_GTFSM_SHIFT)) & SEMA42_GATE0_GTFSM_MASK) +/*! @} */ + +/*! @name GATE7 - Gate */ +/*! @{ */ + +#define SEMA42_GATE7_GTFSM_MASK (0xFU) +#define SEMA42_GATE7_GTFSM_SHIFT (0U) +/*! GTFSM - Gate Finite State Machine + * 0b0000..The gate is unlocked (free). + * 0b0001..Domain 0 locked the gate. + * 0b0010..Domain 1 locked the gate. + * 0b0011..Domain 2 locked the gate. + * 0b0100..Domain 3 locked the gate. + * 0b0101..Domain 4 locked the gate. + * 0b0110..Domain 5 locked the gate. + * 0b0111..Domain 6 locked the gate. + * 0b1000..Domain 7 locked the gate. + * 0b1001..Domain 8 locked the gate. + * 0b1010..Domain 9 locked the gate. + * 0b1011..Domain 10 locked the gate. + * 0b1100..Domain 11 locked the gate. + * 0b1101..Domain 12 locked the gate. + * 0b1110..Domain 13 locked the gate. + * 0b1111..Domain 14 locked the gate. + */ +#define SEMA42_GATE7_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE7_GTFSM_SHIFT)) & SEMA42_GATE7_GTFSM_MASK) +/*! @} */ + +/*! @name GATE6 - Gate */ +/*! @{ */ + +#define SEMA42_GATE6_GTFSM_MASK (0xFU) +#define SEMA42_GATE6_GTFSM_SHIFT (0U) +/*! GTFSM - Gate Finite State Machine + * 0b0000..The gate is unlocked (free). + * 0b0001..Domain 0 locked the gate. + * 0b0010..Domain 1 locked the gate. + * 0b0011..Domain 2 locked the gate. + * 0b0100..Domain 3 locked the gate. + * 0b0101..Domain 4 locked the gate. + * 0b0110..Domain 5 locked the gate. + * 0b0111..Domain 6 locked the gate. + * 0b1000..Domain 7 locked the gate. + * 0b1001..Domain 8 locked the gate. + * 0b1010..Domain 9 locked the gate. + * 0b1011..Domain 10 locked the gate. + * 0b1100..Domain 11 locked the gate. + * 0b1101..Domain 12 locked the gate. + * 0b1110..Domain 13 locked the gate. + * 0b1111..Domain 14 locked the gate. + */ +#define SEMA42_GATE6_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE6_GTFSM_SHIFT)) & SEMA42_GATE6_GTFSM_MASK) +/*! @} */ + +/*! @name GATE5 - Gate */ +/*! @{ */ + +#define SEMA42_GATE5_GTFSM_MASK (0xFU) +#define SEMA42_GATE5_GTFSM_SHIFT (0U) +/*! GTFSM - Gate Finite State Machine + * 0b0000..The gate is unlocked (free). + * 0b0001..Domain 0 locked the gate. + * 0b0010..Domain 1 locked the gate. + * 0b0011..Domain 2 locked the gate. + * 0b0100..Domain 3 locked the gate. + * 0b0101..Domain 4 locked the gate. + * 0b0110..Domain 5 locked the gate. + * 0b0111..Domain 6 locked the gate. + * 0b1000..Domain 7 locked the gate. + * 0b1001..Domain 8 locked the gate. + * 0b1010..Domain 9 locked the gate. + * 0b1011..Domain 10 locked the gate. + * 0b1100..Domain 11 locked the gate. + * 0b1101..Domain 12 locked the gate. + * 0b1110..Domain 13 locked the gate. + * 0b1111..Domain 14 locked the gate. + */ +#define SEMA42_GATE5_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE5_GTFSM_SHIFT)) & SEMA42_GATE5_GTFSM_MASK) +/*! @} */ + +/*! @name GATE4 - Gate */ +/*! @{ */ + +#define SEMA42_GATE4_GTFSM_MASK (0xFU) +#define SEMA42_GATE4_GTFSM_SHIFT (0U) +/*! GTFSM - Gate Finite State Machine + * 0b0000..The gate is unlocked (free). + * 0b0001..Domain 0 locked the gate. + * 0b0010..Domain 1 locked the gate. + * 0b0011..Domain 2 locked the gate. + * 0b0100..Domain 3 locked the gate. + * 0b0101..Domain 4 locked the gate. + * 0b0110..Domain 5 locked the gate. + * 0b0111..Domain 6 locked the gate. + * 0b1000..Domain 7 locked the gate. + * 0b1001..Domain 8 locked the gate. + * 0b1010..Domain 9 locked the gate. + * 0b1011..Domain 10 locked the gate. + * 0b1100..Domain 11 locked the gate. + * 0b1101..Domain 12 locked the gate. + * 0b1110..Domain 13 locked the gate. + * 0b1111..Domain 14 locked the gate. + */ +#define SEMA42_GATE4_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE4_GTFSM_SHIFT)) & SEMA42_GATE4_GTFSM_MASK) +/*! @} */ + +/*! @name GATE11 - Gate */ +/*! @{ */ + +#define SEMA42_GATE11_GTFSM_MASK (0xFU) +#define SEMA42_GATE11_GTFSM_SHIFT (0U) +/*! GTFSM - Gate Finite State Machine + * 0b0000..The gate is unlocked (free). + * 0b0001..Domain 0 locked the gate. + * 0b0010..Domain 1 locked the gate. + * 0b0011..Domain 2 locked the gate. + * 0b0100..Domain 3 locked the gate. + * 0b0101..Domain 4 locked the gate. + * 0b0110..Domain 5 locked the gate. + * 0b0111..Domain 6 locked the gate. + * 0b1000..Domain 7 locked the gate. + * 0b1001..Domain 8 locked the gate. + * 0b1010..Domain 9 locked the gate. + * 0b1011..Domain 10 locked the gate. + * 0b1100..Domain 11 locked the gate. + * 0b1101..Domain 12 locked the gate. + * 0b1110..Domain 13 locked the gate. + * 0b1111..Domain 14 locked the gate. + */ +#define SEMA42_GATE11_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE11_GTFSM_SHIFT)) & SEMA42_GATE11_GTFSM_MASK) +/*! @} */ + +/*! @name GATE10 - Gate */ +/*! @{ */ + +#define SEMA42_GATE10_GTFSM_MASK (0xFU) +#define SEMA42_GATE10_GTFSM_SHIFT (0U) +/*! GTFSM - Gate Finite State Machine + * 0b0000..The gate is unlocked (free). + * 0b0001..Domain 0 locked the gate. + * 0b0010..Domain 1 locked the gate. + * 0b0011..Domain 2 locked the gate. + * 0b0100..Domain 3 locked the gate. + * 0b0101..Domain 4 locked the gate. + * 0b0110..Domain 5 locked the gate. + * 0b0111..Domain 6 locked the gate. + * 0b1000..Domain 7 locked the gate. + * 0b1001..Domain 8 locked the gate. + * 0b1010..Domain 9 locked the gate. + * 0b1011..Domain 10 locked the gate. + * 0b1100..Domain 11 locked the gate. + * 0b1101..Domain 12 locked the gate. + * 0b1110..Domain 13 locked the gate. + * 0b1111..Domain 14 locked the gate. + */ +#define SEMA42_GATE10_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE10_GTFSM_SHIFT)) & SEMA42_GATE10_GTFSM_MASK) +/*! @} */ + +/*! @name GATE9 - Gate */ +/*! @{ */ + +#define SEMA42_GATE9_GTFSM_MASK (0xFU) +#define SEMA42_GATE9_GTFSM_SHIFT (0U) +/*! GTFSM - Gate Finite State Machine + * 0b0000..The gate is unlocked (free). + * 0b0001..Domain 0 locked the gate. + * 0b0010..Domain 1 locked the gate. + * 0b0011..Domain 2 locked the gate. + * 0b0100..Domain 3 locked the gate. + * 0b0101..Domain 4 locked the gate. + * 0b0110..Domain 5 locked the gate. + * 0b0111..Domain 6 locked the gate. + * 0b1000..Domain 7 locked the gate. + * 0b1001..Domain 8 locked the gate. + * 0b1010..Domain 9 locked the gate. + * 0b1011..Domain 10 locked the gate. + * 0b1100..Domain 11 locked the gate. + * 0b1101..Domain 12 locked the gate. + * 0b1110..Domain 13 locked the gate. + * 0b1111..Domain 14 locked the gate. + */ +#define SEMA42_GATE9_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE9_GTFSM_SHIFT)) & SEMA42_GATE9_GTFSM_MASK) +/*! @} */ + +/*! @name GATE8 - Gate */ +/*! @{ */ + +#define SEMA42_GATE8_GTFSM_MASK (0xFU) +#define SEMA42_GATE8_GTFSM_SHIFT (0U) +/*! GTFSM - Gate Finite State Machine + * 0b0000..The gate is unlocked (free). + * 0b0001..Domain 0 locked the gate. + * 0b0010..Domain 1 locked the gate. + * 0b0011..Domain 2 locked the gate. + * 0b0100..Domain 3 locked the gate. + * 0b0101..Domain 4 locked the gate. + * 0b0110..Domain 5 locked the gate. + * 0b0111..Domain 6 locked the gate. + * 0b1000..Domain 7 locked the gate. + * 0b1001..Domain 8 locked the gate. + * 0b1010..Domain 9 locked the gate. + * 0b1011..Domain 10 locked the gate. + * 0b1100..Domain 11 locked the gate. + * 0b1101..Domain 12 locked the gate. + * 0b1110..Domain 13 locked the gate. + * 0b1111..Domain 14 locked the gate. + */ +#define SEMA42_GATE8_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE8_GTFSM_SHIFT)) & SEMA42_GATE8_GTFSM_MASK) +/*! @} */ + +/*! @name GATE15 - Gate */ +/*! @{ */ + +#define SEMA42_GATE15_GTFSM_MASK (0xFU) +#define SEMA42_GATE15_GTFSM_SHIFT (0U) +/*! GTFSM - Gate Finite State Machine + * 0b0000..The gate is unlocked (free). + * 0b0001..Domain 0 locked the gate. + * 0b0010..Domain 1 locked the gate. + * 0b0011..Domain 2 locked the gate. + * 0b0100..Domain 3 locked the gate. + * 0b0101..Domain 4 locked the gate. + * 0b0110..Domain 5 locked the gate. + * 0b0111..Domain 6 locked the gate. + * 0b1000..Domain 7 locked the gate. + * 0b1001..Domain 8 locked the gate. + * 0b1010..Domain 9 locked the gate. + * 0b1011..Domain 10 locked the gate. + * 0b1100..Domain 11 locked the gate. + * 0b1101..Domain 12 locked the gate. + * 0b1110..Domain 13 locked the gate. + * 0b1111..Domain 14 locked the gate. + */ +#define SEMA42_GATE15_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE15_GTFSM_SHIFT)) & SEMA42_GATE15_GTFSM_MASK) +/*! @} */ + +/*! @name GATE14 - Gate */ +/*! @{ */ + +#define SEMA42_GATE14_GTFSM_MASK (0xFU) +#define SEMA42_GATE14_GTFSM_SHIFT (0U) +/*! GTFSM - Gate Finite State Machine + * 0b0000..The gate is unlocked (free). + * 0b0001..Domain 0 locked the gate. + * 0b0010..Domain 1 locked the gate. + * 0b0011..Domain 2 locked the gate. + * 0b0100..Domain 3 locked the gate. + * 0b0101..Domain 4 locked the gate. + * 0b0110..Domain 5 locked the gate. + * 0b0111..Domain 6 locked the gate. + * 0b1000..Domain 7 locked the gate. + * 0b1001..Domain 8 locked the gate. + * 0b1010..Domain 9 locked the gate. + * 0b1011..Domain 10 locked the gate. + * 0b1100..Domain 11 locked the gate. + * 0b1101..Domain 12 locked the gate. + * 0b1110..Domain 13 locked the gate. + * 0b1111..Domain 14 locked the gate. + */ +#define SEMA42_GATE14_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE14_GTFSM_SHIFT)) & SEMA42_GATE14_GTFSM_MASK) +/*! @} */ + +/*! @name GATE13 - Gate */ +/*! @{ */ + +#define SEMA42_GATE13_GTFSM_MASK (0xFU) +#define SEMA42_GATE13_GTFSM_SHIFT (0U) +/*! GTFSM - Gate Finite State Machine + * 0b0000..The gate is unlocked (free). + * 0b0001..Domain 0 locked the gate. + * 0b0010..Domain 1 locked the gate. + * 0b0011..Domain 2 locked the gate. + * 0b0100..Domain 3 locked the gate. + * 0b0101..Domain 4 locked the gate. + * 0b0110..Domain 5 locked the gate. + * 0b0111..Domain 6 locked the gate. + * 0b1000..Domain 7 locked the gate. + * 0b1001..Domain 8 locked the gate. + * 0b1010..Domain 9 locked the gate. + * 0b1011..Domain 10 locked the gate. + * 0b1100..Domain 11 locked the gate. + * 0b1101..Domain 12 locked the gate. + * 0b1110..Domain 13 locked the gate. + * 0b1111..Domain 14 locked the gate. + */ +#define SEMA42_GATE13_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE13_GTFSM_SHIFT)) & SEMA42_GATE13_GTFSM_MASK) +/*! @} */ + +/*! @name GATE12 - Gate */ +/*! @{ */ + +#define SEMA42_GATE12_GTFSM_MASK (0xFU) +#define SEMA42_GATE12_GTFSM_SHIFT (0U) +/*! GTFSM - Gate Finite State Machine + * 0b0000..The gate is unlocked (free). + * 0b0001..Domain 0 locked the gate. + * 0b0010..Domain 1 locked the gate. + * 0b0011..Domain 2 locked the gate. + * 0b0100..Domain 3 locked the gate. + * 0b0101..Domain 4 locked the gate. + * 0b0110..Domain 5 locked the gate. + * 0b0111..Domain 6 locked the gate. + * 0b1000..Domain 7 locked the gate. + * 0b1001..Domain 8 locked the gate. + * 0b1010..Domain 9 locked the gate. + * 0b1011..Domain 10 locked the gate. + * 0b1100..Domain 11 locked the gate. + * 0b1101..Domain 12 locked the gate. + * 0b1110..Domain 13 locked the gate. + * 0b1111..Domain 14 locked the gate. + */ +#define SEMA42_GATE12_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE12_GTFSM_SHIFT)) & SEMA42_GATE12_GTFSM_MASK) +/*! @} */ + +/*! @name GATE19 - Gate */ +/*! @{ */ + +#define SEMA42_GATE19_GTFSM_MASK (0xFU) +#define SEMA42_GATE19_GTFSM_SHIFT (0U) +/*! GTFSM - Gate Finite State Machine + * 0b0000..The gate is unlocked (free). + * 0b0001..Domain 0 locked the gate. + * 0b0010..Domain 1 locked the gate. + * 0b0011..Domain 2 locked the gate. + * 0b0100..Domain 3 locked the gate. + * 0b0101..Domain 4 locked the gate. + * 0b0110..Domain 5 locked the gate. + * 0b0111..Domain 6 locked the gate. + * 0b1000..Domain 7 locked the gate. + * 0b1001..Domain 8 locked the gate. + * 0b1010..Domain 9 locked the gate. + * 0b1011..Domain 10 locked the gate. + * 0b1100..Domain 11 locked the gate. + * 0b1101..Domain 12 locked the gate. + * 0b1110..Domain 13 locked the gate. + * 0b1111..Domain 14 locked the gate. + */ +#define SEMA42_GATE19_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE19_GTFSM_SHIFT)) & SEMA42_GATE19_GTFSM_MASK) +/*! @} */ + +/*! @name GATE18 - Gate */ +/*! @{ */ + +#define SEMA42_GATE18_GTFSM_MASK (0xFU) +#define SEMA42_GATE18_GTFSM_SHIFT (0U) +/*! GTFSM - Gate Finite State Machine + * 0b0000..The gate is unlocked (free). + * 0b0001..Domain 0 locked the gate. + * 0b0010..Domain 1 locked the gate. + * 0b0011..Domain 2 locked the gate. + * 0b0100..Domain 3 locked the gate. + * 0b0101..Domain 4 locked the gate. + * 0b0110..Domain 5 locked the gate. + * 0b0111..Domain 6 locked the gate. + * 0b1000..Domain 7 locked the gate. + * 0b1001..Domain 8 locked the gate. + * 0b1010..Domain 9 locked the gate. + * 0b1011..Domain 10 locked the gate. + * 0b1100..Domain 11 locked the gate. + * 0b1101..Domain 12 locked the gate. + * 0b1110..Domain 13 locked the gate. + * 0b1111..Domain 14 locked the gate. + */ +#define SEMA42_GATE18_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE18_GTFSM_SHIFT)) & SEMA42_GATE18_GTFSM_MASK) +/*! @} */ + +/*! @name GATE17 - Gate */ +/*! @{ */ + +#define SEMA42_GATE17_GTFSM_MASK (0xFU) +#define SEMA42_GATE17_GTFSM_SHIFT (0U) +/*! GTFSM - Gate Finite State Machine + * 0b0000..The gate is unlocked (free). + * 0b0001..Domain 0 locked the gate. + * 0b0010..Domain 1 locked the gate. + * 0b0011..Domain 2 locked the gate. + * 0b0100..Domain 3 locked the gate. + * 0b0101..Domain 4 locked the gate. + * 0b0110..Domain 5 locked the gate. + * 0b0111..Domain 6 locked the gate. + * 0b1000..Domain 7 locked the gate. + * 0b1001..Domain 8 locked the gate. + * 0b1010..Domain 9 locked the gate. + * 0b1011..Domain 10 locked the gate. + * 0b1100..Domain 11 locked the gate. + * 0b1101..Domain 12 locked the gate. + * 0b1110..Domain 13 locked the gate. + * 0b1111..Domain 14 locked the gate. + */ +#define SEMA42_GATE17_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE17_GTFSM_SHIFT)) & SEMA42_GATE17_GTFSM_MASK) +/*! @} */ + +/*! @name GATE16 - Gate */ +/*! @{ */ + +#define SEMA42_GATE16_GTFSM_MASK (0xFU) +#define SEMA42_GATE16_GTFSM_SHIFT (0U) +/*! GTFSM - Gate Finite State Machine + * 0b0000..The gate is unlocked (free). + * 0b0001..Domain 0 locked the gate. + * 0b0010..Domain 1 locked the gate. + * 0b0011..Domain 2 locked the gate. + * 0b0100..Domain 3 locked the gate. + * 0b0101..Domain 4 locked the gate. + * 0b0110..Domain 5 locked the gate. + * 0b0111..Domain 6 locked the gate. + * 0b1000..Domain 7 locked the gate. + * 0b1001..Domain 8 locked the gate. + * 0b1010..Domain 9 locked the gate. + * 0b1011..Domain 10 locked the gate. + * 0b1100..Domain 11 locked the gate. + * 0b1101..Domain 12 locked the gate. + * 0b1110..Domain 13 locked the gate. + * 0b1111..Domain 14 locked the gate. + */ +#define SEMA42_GATE16_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE16_GTFSM_SHIFT)) & SEMA42_GATE16_GTFSM_MASK) +/*! @} */ + +/*! @name GATE23 - Gate */ +/*! @{ */ + +#define SEMA42_GATE23_GTFSM_MASK (0xFU) +#define SEMA42_GATE23_GTFSM_SHIFT (0U) +/*! GTFSM - Gate Finite State Machine + * 0b0000..The gate is unlocked (free). + * 0b0001..Domain 0 locked the gate. + * 0b0010..Domain 1 locked the gate. + * 0b0011..Domain 2 locked the gate. + * 0b0100..Domain 3 locked the gate. + * 0b0101..Domain 4 locked the gate. + * 0b0110..Domain 5 locked the gate. + * 0b0111..Domain 6 locked the gate. + * 0b1000..Domain 7 locked the gate. + * 0b1001..Domain 8 locked the gate. + * 0b1010..Domain 9 locked the gate. + * 0b1011..Domain 10 locked the gate. + * 0b1100..Domain 11 locked the gate. + * 0b1101..Domain 12 locked the gate. + * 0b1110..Domain 13 locked the gate. + * 0b1111..Domain 14 locked the gate. + */ +#define SEMA42_GATE23_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE23_GTFSM_SHIFT)) & SEMA42_GATE23_GTFSM_MASK) +/*! @} */ + +/*! @name GATE22 - Gate */ +/*! @{ */ + +#define SEMA42_GATE22_GTFSM_MASK (0xFU) +#define SEMA42_GATE22_GTFSM_SHIFT (0U) +/*! GTFSM - Gate Finite State Machine + * 0b0000..The gate is unlocked (free). + * 0b0001..Domain 0 locked the gate. + * 0b0010..Domain 1 locked the gate. + * 0b0011..Domain 2 locked the gate. + * 0b0100..Domain 3 locked the gate. + * 0b0101..Domain 4 locked the gate. + * 0b0110..Domain 5 locked the gate. + * 0b0111..Domain 6 locked the gate. + * 0b1000..Domain 7 locked the gate. + * 0b1001..Domain 8 locked the gate. + * 0b1010..Domain 9 locked the gate. + * 0b1011..Domain 10 locked the gate. + * 0b1100..Domain 11 locked the gate. + * 0b1101..Domain 12 locked the gate. + * 0b1110..Domain 13 locked the gate. + * 0b1111..Domain 14 locked the gate. + */ +#define SEMA42_GATE22_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE22_GTFSM_SHIFT)) & SEMA42_GATE22_GTFSM_MASK) +/*! @} */ + +/*! @name GATE21 - Gate */ +/*! @{ */ + +#define SEMA42_GATE21_GTFSM_MASK (0xFU) +#define SEMA42_GATE21_GTFSM_SHIFT (0U) +/*! GTFSM - Gate Finite State Machine + * 0b0000..The gate is unlocked (free). + * 0b0001..Domain 0 locked the gate. + * 0b0010..Domain 1 locked the gate. + * 0b0011..Domain 2 locked the gate. + * 0b0100..Domain 3 locked the gate. + * 0b0101..Domain 4 locked the gate. + * 0b0110..Domain 5 locked the gate. + * 0b0111..Domain 6 locked the gate. + * 0b1000..Domain 7 locked the gate. + * 0b1001..Domain 8 locked the gate. + * 0b1010..Domain 9 locked the gate. + * 0b1011..Domain 10 locked the gate. + * 0b1100..Domain 11 locked the gate. + * 0b1101..Domain 12 locked the gate. + * 0b1110..Domain 13 locked the gate. + * 0b1111..Domain 14 locked the gate. + */ +#define SEMA42_GATE21_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE21_GTFSM_SHIFT)) & SEMA42_GATE21_GTFSM_MASK) +/*! @} */ + +/*! @name GATE20 - Gate */ +/*! @{ */ + +#define SEMA42_GATE20_GTFSM_MASK (0xFU) +#define SEMA42_GATE20_GTFSM_SHIFT (0U) +/*! GTFSM - Gate Finite State Machine + * 0b0000..The gate is unlocked (free). + * 0b0001..Domain 0 locked the gate. + * 0b0010..Domain 1 locked the gate. + * 0b0011..Domain 2 locked the gate. + * 0b0100..Domain 3 locked the gate. + * 0b0101..Domain 4 locked the gate. + * 0b0110..Domain 5 locked the gate. + * 0b0111..Domain 6 locked the gate. + * 0b1000..Domain 7 locked the gate. + * 0b1001..Domain 8 locked the gate. + * 0b1010..Domain 9 locked the gate. + * 0b1011..Domain 10 locked the gate. + * 0b1100..Domain 11 locked the gate. + * 0b1101..Domain 12 locked the gate. + * 0b1110..Domain 13 locked the gate. + * 0b1111..Domain 14 locked the gate. + */ +#define SEMA42_GATE20_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE20_GTFSM_SHIFT)) & SEMA42_GATE20_GTFSM_MASK) +/*! @} */ + +/*! @name GATE27 - Gate */ +/*! @{ */ + +#define SEMA42_GATE27_GTFSM_MASK (0xFU) +#define SEMA42_GATE27_GTFSM_SHIFT (0U) +/*! GTFSM - Gate Finite State Machine + * 0b0000..The gate is unlocked (free). + * 0b0001..Domain 0 locked the gate. + * 0b0010..Domain 1 locked the gate. + * 0b0011..Domain 2 locked the gate. + * 0b0100..Domain 3 locked the gate. + * 0b0101..Domain 4 locked the gate. + * 0b0110..Domain 5 locked the gate. + * 0b0111..Domain 6 locked the gate. + * 0b1000..Domain 7 locked the gate. + * 0b1001..Domain 8 locked the gate. + * 0b1010..Domain 9 locked the gate. + * 0b1011..Domain 10 locked the gate. + * 0b1100..Domain 11 locked the gate. + * 0b1101..Domain 12 locked the gate. + * 0b1110..Domain 13 locked the gate. + * 0b1111..Domain 14 locked the gate. + */ +#define SEMA42_GATE27_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE27_GTFSM_SHIFT)) & SEMA42_GATE27_GTFSM_MASK) +/*! @} */ + +/*! @name GATE26 - Gate */ +/*! @{ */ + +#define SEMA42_GATE26_GTFSM_MASK (0xFU) +#define SEMA42_GATE26_GTFSM_SHIFT (0U) +/*! GTFSM - Gate Finite State Machine + * 0b0000..The gate is unlocked (free). + * 0b0001..Domain 0 locked the gate. + * 0b0010..Domain 1 locked the gate. + * 0b0011..Domain 2 locked the gate. + * 0b0100..Domain 3 locked the gate. + * 0b0101..Domain 4 locked the gate. + * 0b0110..Domain 5 locked the gate. + * 0b0111..Domain 6 locked the gate. + * 0b1000..Domain 7 locked the gate. + * 0b1001..Domain 8 locked the gate. + * 0b1010..Domain 9 locked the gate. + * 0b1011..Domain 10 locked the gate. + * 0b1100..Domain 11 locked the gate. + * 0b1101..Domain 12 locked the gate. + * 0b1110..Domain 13 locked the gate. + * 0b1111..Domain 14 locked the gate. + */ +#define SEMA42_GATE26_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE26_GTFSM_SHIFT)) & SEMA42_GATE26_GTFSM_MASK) +/*! @} */ + +/*! @name GATE25 - Gate */ +/*! @{ */ + +#define SEMA42_GATE25_GTFSM_MASK (0xFU) +#define SEMA42_GATE25_GTFSM_SHIFT (0U) +/*! GTFSM - Gate Finite State Machine + * 0b0000..The gate is unlocked (free). + * 0b0001..Domain 0 locked the gate. + * 0b0010..Domain 1 locked the gate. + * 0b0011..Domain 2 locked the gate. + * 0b0100..Domain 3 locked the gate. + * 0b0101..Domain 4 locked the gate. + * 0b0110..Domain 5 locked the gate. + * 0b0111..Domain 6 locked the gate. + * 0b1000..Domain 7 locked the gate. + * 0b1001..Domain 8 locked the gate. + * 0b1010..Domain 9 locked the gate. + * 0b1011..Domain 10 locked the gate. + * 0b1100..Domain 11 locked the gate. + * 0b1101..Domain 12 locked the gate. + * 0b1110..Domain 13 locked the gate. + * 0b1111..Domain 14 locked the gate. + */ +#define SEMA42_GATE25_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE25_GTFSM_SHIFT)) & SEMA42_GATE25_GTFSM_MASK) +/*! @} */ + +/*! @name GATE24 - Gate */ +/*! @{ */ + +#define SEMA42_GATE24_GTFSM_MASK (0xFU) +#define SEMA42_GATE24_GTFSM_SHIFT (0U) +/*! GTFSM - Gate Finite State Machine + * 0b0000..The gate is unlocked (free). + * 0b0001..Domain 0 locked the gate. + * 0b0010..Domain 1 locked the gate. + * 0b0011..Domain 2 locked the gate. + * 0b0100..Domain 3 locked the gate. + * 0b0101..Domain 4 locked the gate. + * 0b0110..Domain 5 locked the gate. + * 0b0111..Domain 6 locked the gate. + * 0b1000..Domain 7 locked the gate. + * 0b1001..Domain 8 locked the gate. + * 0b1010..Domain 9 locked the gate. + * 0b1011..Domain 10 locked the gate. + * 0b1100..Domain 11 locked the gate. + * 0b1101..Domain 12 locked the gate. + * 0b1110..Domain 13 locked the gate. + * 0b1111..Domain 14 locked the gate. + */ +#define SEMA42_GATE24_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE24_GTFSM_SHIFT)) & SEMA42_GATE24_GTFSM_MASK) +/*! @} */ + +/*! @name GATE31 - Gate */ +/*! @{ */ + +#define SEMA42_GATE31_GTFSM_MASK (0xFU) +#define SEMA42_GATE31_GTFSM_SHIFT (0U) +/*! GTFSM - Gate Finite State Machine + * 0b0000..The gate is unlocked (free). + * 0b0001..Domain 0 locked the gate. + * 0b0010..Domain 1 locked the gate. + * 0b0011..Domain 2 locked the gate. + * 0b0100..Domain 3 locked the gate. + * 0b0101..Domain 4 locked the gate. + * 0b0110..Domain 5 locked the gate. + * 0b0111..Domain 6 locked the gate. + * 0b1000..Domain 7 locked the gate. + * 0b1001..Domain 8 locked the gate. + * 0b1010..Domain 9 locked the gate. + * 0b1011..Domain 10 locked the gate. + * 0b1100..Domain 11 locked the gate. + * 0b1101..Domain 12 locked the gate. + * 0b1110..Domain 13 locked the gate. + * 0b1111..Domain 14 locked the gate. + */ +#define SEMA42_GATE31_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE31_GTFSM_SHIFT)) & SEMA42_GATE31_GTFSM_MASK) +/*! @} */ + +/*! @name GATE30 - Gate */ +/*! @{ */ + +#define SEMA42_GATE30_GTFSM_MASK (0xFU) +#define SEMA42_GATE30_GTFSM_SHIFT (0U) +/*! GTFSM - Gate Finite State Machine + * 0b0000..The gate is unlocked (free). + * 0b0001..Domain 0 locked the gate. + * 0b0010..Domain 1 locked the gate. + * 0b0011..Domain 2 locked the gate. + * 0b0100..Domain 3 locked the gate. + * 0b0101..Domain 4 locked the gate. + * 0b0110..Domain 5 locked the gate. + * 0b0111..Domain 6 locked the gate. + * 0b1000..Domain 7 locked the gate. + * 0b1001..Domain 8 locked the gate. + * 0b1010..Domain 9 locked the gate. + * 0b1011..Domain 10 locked the gate. + * 0b1100..Domain 11 locked the gate. + * 0b1101..Domain 12 locked the gate. + * 0b1110..Domain 13 locked the gate. + * 0b1111..Domain 14 locked the gate. + */ +#define SEMA42_GATE30_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE30_GTFSM_SHIFT)) & SEMA42_GATE30_GTFSM_MASK) +/*! @} */ + +/*! @name GATE29 - Gate */ +/*! @{ */ + +#define SEMA42_GATE29_GTFSM_MASK (0xFU) +#define SEMA42_GATE29_GTFSM_SHIFT (0U) +/*! GTFSM - Gate Finite State Machine + * 0b0000..The gate is unlocked (free). + * 0b0001..Domain 0 locked the gate. + * 0b0010..Domain 1 locked the gate. + * 0b0011..Domain 2 locked the gate. + * 0b0100..Domain 3 locked the gate. + * 0b0101..Domain 4 locked the gate. + * 0b0110..Domain 5 locked the gate. + * 0b0111..Domain 6 locked the gate. + * 0b1000..Domain 7 locked the gate. + * 0b1001..Domain 8 locked the gate. + * 0b1010..Domain 9 locked the gate. + * 0b1011..Domain 10 locked the gate. + * 0b1100..Domain 11 locked the gate. + * 0b1101..Domain 12 locked the gate. + * 0b1110..Domain 13 locked the gate. + * 0b1111..Domain 14 locked the gate. + */ +#define SEMA42_GATE29_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE29_GTFSM_SHIFT)) & SEMA42_GATE29_GTFSM_MASK) +/*! @} */ + +/*! @name GATE28 - Gate */ +/*! @{ */ + +#define SEMA42_GATE28_GTFSM_MASK (0xFU) +#define SEMA42_GATE28_GTFSM_SHIFT (0U) +/*! GTFSM - Gate Finite State Machine + * 0b0000..The gate is unlocked (free). + * 0b0001..Domain 0 locked the gate. + * 0b0010..Domain 1 locked the gate. + * 0b0011..Domain 2 locked the gate. + * 0b0100..Domain 3 locked the gate. + * 0b0101..Domain 4 locked the gate. + * 0b0110..Domain 5 locked the gate. + * 0b0111..Domain 6 locked the gate. + * 0b1000..Domain 7 locked the gate. + * 0b1001..Domain 8 locked the gate. + * 0b1010..Domain 9 locked the gate. + * 0b1011..Domain 10 locked the gate. + * 0b1100..Domain 11 locked the gate. + * 0b1101..Domain 12 locked the gate. + * 0b1110..Domain 13 locked the gate. + * 0b1111..Domain 14 locked the gate. + */ +#define SEMA42_GATE28_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE28_GTFSM_SHIFT)) & SEMA42_GATE28_GTFSM_MASK) +/*! @} */ + +/*! @name GATE35 - Gate */ +/*! @{ */ + +#define SEMA42_GATE35_GTFSM_MASK (0xFU) +#define SEMA42_GATE35_GTFSM_SHIFT (0U) +/*! GTFSM - Gate Finite State Machine + * 0b0000..The gate is unlocked (free). + * 0b0001..Domain 0 locked the gate. + * 0b0010..Domain 1 locked the gate. + * 0b0011..Domain 2 locked the gate. + * 0b0100..Domain 3 locked the gate. + * 0b0101..Domain 4 locked the gate. + * 0b0110..Domain 5 locked the gate. + * 0b0111..Domain 6 locked the gate. + * 0b1000..Domain 7 locked the gate. + * 0b1001..Domain 8 locked the gate. + * 0b1010..Domain 9 locked the gate. + * 0b1011..Domain 10 locked the gate. + * 0b1100..Domain 11 locked the gate. + * 0b1101..Domain 12 locked the gate. + * 0b1110..Domain 13 locked the gate. + * 0b1111..Domain 14 locked the gate. + */ +#define SEMA42_GATE35_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE35_GTFSM_SHIFT)) & SEMA42_GATE35_GTFSM_MASK) +/*! @} */ + +/*! @name GATE34 - Gate */ +/*! @{ */ + +#define SEMA42_GATE34_GTFSM_MASK (0xFU) +#define SEMA42_GATE34_GTFSM_SHIFT (0U) +/*! GTFSM - Gate Finite State Machine + * 0b0000..The gate is unlocked (free). + * 0b0001..Domain 0 locked the gate. + * 0b0010..Domain 1 locked the gate. + * 0b0011..Domain 2 locked the gate. + * 0b0100..Domain 3 locked the gate. + * 0b0101..Domain 4 locked the gate. + * 0b0110..Domain 5 locked the gate. + * 0b0111..Domain 6 locked the gate. + * 0b1000..Domain 7 locked the gate. + * 0b1001..Domain 8 locked the gate. + * 0b1010..Domain 9 locked the gate. + * 0b1011..Domain 10 locked the gate. + * 0b1100..Domain 11 locked the gate. + * 0b1101..Domain 12 locked the gate. + * 0b1110..Domain 13 locked the gate. + * 0b1111..Domain 14 locked the gate. + */ +#define SEMA42_GATE34_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE34_GTFSM_SHIFT)) & SEMA42_GATE34_GTFSM_MASK) +/*! @} */ + +/*! @name GATE33 - Gate */ +/*! @{ */ + +#define SEMA42_GATE33_GTFSM_MASK (0xFU) +#define SEMA42_GATE33_GTFSM_SHIFT (0U) +/*! GTFSM - Gate Finite State Machine + * 0b0000..The gate is unlocked (free). + * 0b0001..Domain 0 locked the gate. + * 0b0010..Domain 1 locked the gate. + * 0b0011..Domain 2 locked the gate. + * 0b0100..Domain 3 locked the gate. + * 0b0101..Domain 4 locked the gate. + * 0b0110..Domain 5 locked the gate. + * 0b0111..Domain 6 locked the gate. + * 0b1000..Domain 7 locked the gate. + * 0b1001..Domain 8 locked the gate. + * 0b1010..Domain 9 locked the gate. + * 0b1011..Domain 10 locked the gate. + * 0b1100..Domain 11 locked the gate. + * 0b1101..Domain 12 locked the gate. + * 0b1110..Domain 13 locked the gate. + * 0b1111..Domain 14 locked the gate. + */ +#define SEMA42_GATE33_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE33_GTFSM_SHIFT)) & SEMA42_GATE33_GTFSM_MASK) +/*! @} */ + +/*! @name GATE32 - Gate */ +/*! @{ */ + +#define SEMA42_GATE32_GTFSM_MASK (0xFU) +#define SEMA42_GATE32_GTFSM_SHIFT (0U) +/*! GTFSM - Gate Finite State Machine + * 0b0000..The gate is unlocked (free). + * 0b0001..Domain 0 locked the gate. + * 0b0010..Domain 1 locked the gate. + * 0b0011..Domain 2 locked the gate. + * 0b0100..Domain 3 locked the gate. + * 0b0101..Domain 4 locked the gate. + * 0b0110..Domain 5 locked the gate. + * 0b0111..Domain 6 locked the gate. + * 0b1000..Domain 7 locked the gate. + * 0b1001..Domain 8 locked the gate. + * 0b1010..Domain 9 locked the gate. + * 0b1011..Domain 10 locked the gate. + * 0b1100..Domain 11 locked the gate. + * 0b1101..Domain 12 locked the gate. + * 0b1110..Domain 13 locked the gate. + * 0b1111..Domain 14 locked the gate. + */ +#define SEMA42_GATE32_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE32_GTFSM_SHIFT)) & SEMA42_GATE32_GTFSM_MASK) +/*! @} */ + +/*! @name GATE39 - Gate */ +/*! @{ */ + +#define SEMA42_GATE39_GTFSM_MASK (0xFU) +#define SEMA42_GATE39_GTFSM_SHIFT (0U) +/*! GTFSM - Gate Finite State Machine + * 0b0000..The gate is unlocked (free). + * 0b0001..Domain 0 locked the gate. + * 0b0010..Domain 1 locked the gate. + * 0b0011..Domain 2 locked the gate. + * 0b0100..Domain 3 locked the gate. + * 0b0101..Domain 4 locked the gate. + * 0b0110..Domain 5 locked the gate. + * 0b0111..Domain 6 locked the gate. + * 0b1000..Domain 7 locked the gate. + * 0b1001..Domain 8 locked the gate. + * 0b1010..Domain 9 locked the gate. + * 0b1011..Domain 10 locked the gate. + * 0b1100..Domain 11 locked the gate. + * 0b1101..Domain 12 locked the gate. + * 0b1110..Domain 13 locked the gate. + * 0b1111..Domain 14 locked the gate. + */ +#define SEMA42_GATE39_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE39_GTFSM_SHIFT)) & SEMA42_GATE39_GTFSM_MASK) +/*! @} */ + +/*! @name GATE38 - Gate */ +/*! @{ */ + +#define SEMA42_GATE38_GTFSM_MASK (0xFU) +#define SEMA42_GATE38_GTFSM_SHIFT (0U) +/*! GTFSM - Gate Finite State Machine + * 0b0000..The gate is unlocked (free). + * 0b0001..Domain 0 locked the gate. + * 0b0010..Domain 1 locked the gate. + * 0b0011..Domain 2 locked the gate. + * 0b0100..Domain 3 locked the gate. + * 0b0101..Domain 4 locked the gate. + * 0b0110..Domain 5 locked the gate. + * 0b0111..Domain 6 locked the gate. + * 0b1000..Domain 7 locked the gate. + * 0b1001..Domain 8 locked the gate. + * 0b1010..Domain 9 locked the gate. + * 0b1011..Domain 10 locked the gate. + * 0b1100..Domain 11 locked the gate. + * 0b1101..Domain 12 locked the gate. + * 0b1110..Domain 13 locked the gate. + * 0b1111..Domain 14 locked the gate. + */ +#define SEMA42_GATE38_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE38_GTFSM_SHIFT)) & SEMA42_GATE38_GTFSM_MASK) +/*! @} */ + +/*! @name GATE37 - Gate */ +/*! @{ */ + +#define SEMA42_GATE37_GTFSM_MASK (0xFU) +#define SEMA42_GATE37_GTFSM_SHIFT (0U) +/*! GTFSM - Gate Finite State Machine + * 0b0000..The gate is unlocked (free). + * 0b0001..Domain 0 locked the gate. + * 0b0010..Domain 1 locked the gate. + * 0b0011..Domain 2 locked the gate. + * 0b0100..Domain 3 locked the gate. + * 0b0101..Domain 4 locked the gate. + * 0b0110..Domain 5 locked the gate. + * 0b0111..Domain 6 locked the gate. + * 0b1000..Domain 7 locked the gate. + * 0b1001..Domain 8 locked the gate. + * 0b1010..Domain 9 locked the gate. + * 0b1011..Domain 10 locked the gate. + * 0b1100..Domain 11 locked the gate. + * 0b1101..Domain 12 locked the gate. + * 0b1110..Domain 13 locked the gate. + * 0b1111..Domain 14 locked the gate. + */ +#define SEMA42_GATE37_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE37_GTFSM_SHIFT)) & SEMA42_GATE37_GTFSM_MASK) +/*! @} */ + +/*! @name GATE36 - Gate */ +/*! @{ */ + +#define SEMA42_GATE36_GTFSM_MASK (0xFU) +#define SEMA42_GATE36_GTFSM_SHIFT (0U) +/*! GTFSM - Gate Finite State Machine + * 0b0000..The gate is unlocked (free). + * 0b0001..Domain 0 locked the gate. + * 0b0010..Domain 1 locked the gate. + * 0b0011..Domain 2 locked the gate. + * 0b0100..Domain 3 locked the gate. + * 0b0101..Domain 4 locked the gate. + * 0b0110..Domain 5 locked the gate. + * 0b0111..Domain 6 locked the gate. + * 0b1000..Domain 7 locked the gate. + * 0b1001..Domain 8 locked the gate. + * 0b1010..Domain 9 locked the gate. + * 0b1011..Domain 10 locked the gate. + * 0b1100..Domain 11 locked the gate. + * 0b1101..Domain 12 locked the gate. + * 0b1110..Domain 13 locked the gate. + * 0b1111..Domain 14 locked the gate. + */ +#define SEMA42_GATE36_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE36_GTFSM_SHIFT)) & SEMA42_GATE36_GTFSM_MASK) +/*! @} */ + +/*! @name GATE43 - Gate */ +/*! @{ */ + +#define SEMA42_GATE43_GTFSM_MASK (0xFU) +#define SEMA42_GATE43_GTFSM_SHIFT (0U) +/*! GTFSM - Gate Finite State Machine + * 0b0000..The gate is unlocked (free). + * 0b0001..Domain 0 locked the gate. + * 0b0010..Domain 1 locked the gate. + * 0b0011..Domain 2 locked the gate. + * 0b0100..Domain 3 locked the gate. + * 0b0101..Domain 4 locked the gate. + * 0b0110..Domain 5 locked the gate. + * 0b0111..Domain 6 locked the gate. + * 0b1000..Domain 7 locked the gate. + * 0b1001..Domain 8 locked the gate. + * 0b1010..Domain 9 locked the gate. + * 0b1011..Domain 10 locked the gate. + * 0b1100..Domain 11 locked the gate. + * 0b1101..Domain 12 locked the gate. + * 0b1110..Domain 13 locked the gate. + * 0b1111..Domain 14 locked the gate. + */ +#define SEMA42_GATE43_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE43_GTFSM_SHIFT)) & SEMA42_GATE43_GTFSM_MASK) +/*! @} */ + +/*! @name GATE42 - Gate */ +/*! @{ */ + +#define SEMA42_GATE42_GTFSM_MASK (0xFU) +#define SEMA42_GATE42_GTFSM_SHIFT (0U) +/*! GTFSM - Gate Finite State Machine + * 0b0000..The gate is unlocked (free). + * 0b0001..Domain 0 locked the gate. + * 0b0010..Domain 1 locked the gate. + * 0b0011..Domain 2 locked the gate. + * 0b0100..Domain 3 locked the gate. + * 0b0101..Domain 4 locked the gate. + * 0b0110..Domain 5 locked the gate. + * 0b0111..Domain 6 locked the gate. + * 0b1000..Domain 7 locked the gate. + * 0b1001..Domain 8 locked the gate. + * 0b1010..Domain 9 locked the gate. + * 0b1011..Domain 10 locked the gate. + * 0b1100..Domain 11 locked the gate. + * 0b1101..Domain 12 locked the gate. + * 0b1110..Domain 13 locked the gate. + * 0b1111..Domain 14 locked the gate. + */ +#define SEMA42_GATE42_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE42_GTFSM_SHIFT)) & SEMA42_GATE42_GTFSM_MASK) +/*! @} */ + +/*! @name GATE41 - Gate */ +/*! @{ */ + +#define SEMA42_GATE41_GTFSM_MASK (0xFU) +#define SEMA42_GATE41_GTFSM_SHIFT (0U) +/*! GTFSM - Gate Finite State Machine + * 0b0000..The gate is unlocked (free). + * 0b0001..Domain 0 locked the gate. + * 0b0010..Domain 1 locked the gate. + * 0b0011..Domain 2 locked the gate. + * 0b0100..Domain 3 locked the gate. + * 0b0101..Domain 4 locked the gate. + * 0b0110..Domain 5 locked the gate. + * 0b0111..Domain 6 locked the gate. + * 0b1000..Domain 7 locked the gate. + * 0b1001..Domain 8 locked the gate. + * 0b1010..Domain 9 locked the gate. + * 0b1011..Domain 10 locked the gate. + * 0b1100..Domain 11 locked the gate. + * 0b1101..Domain 12 locked the gate. + * 0b1110..Domain 13 locked the gate. + * 0b1111..Domain 14 locked the gate. + */ +#define SEMA42_GATE41_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE41_GTFSM_SHIFT)) & SEMA42_GATE41_GTFSM_MASK) +/*! @} */ + +/*! @name GATE40 - Gate */ +/*! @{ */ + +#define SEMA42_GATE40_GTFSM_MASK (0xFU) +#define SEMA42_GATE40_GTFSM_SHIFT (0U) +/*! GTFSM - Gate Finite State Machine + * 0b0000..The gate is unlocked (free). + * 0b0001..Domain 0 locked the gate. + * 0b0010..Domain 1 locked the gate. + * 0b0011..Domain 2 locked the gate. + * 0b0100..Domain 3 locked the gate. + * 0b0101..Domain 4 locked the gate. + * 0b0110..Domain 5 locked the gate. + * 0b0111..Domain 6 locked the gate. + * 0b1000..Domain 7 locked the gate. + * 0b1001..Domain 8 locked the gate. + * 0b1010..Domain 9 locked the gate. + * 0b1011..Domain 10 locked the gate. + * 0b1100..Domain 11 locked the gate. + * 0b1101..Domain 12 locked the gate. + * 0b1110..Domain 13 locked the gate. + * 0b1111..Domain 14 locked the gate. + */ +#define SEMA42_GATE40_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE40_GTFSM_SHIFT)) & SEMA42_GATE40_GTFSM_MASK) +/*! @} */ + +/*! @name GATE47 - Gate */ +/*! @{ */ + +#define SEMA42_GATE47_GTFSM_MASK (0xFU) +#define SEMA42_GATE47_GTFSM_SHIFT (0U) +/*! GTFSM - Gate Finite State Machine + * 0b0000..The gate is unlocked (free). + * 0b0001..Domain 0 locked the gate. + * 0b0010..Domain 1 locked the gate. + * 0b0011..Domain 2 locked the gate. + * 0b0100..Domain 3 locked the gate. + * 0b0101..Domain 4 locked the gate. + * 0b0110..Domain 5 locked the gate. + * 0b0111..Domain 6 locked the gate. + * 0b1000..Domain 7 locked the gate. + * 0b1001..Domain 8 locked the gate. + * 0b1010..Domain 9 locked the gate. + * 0b1011..Domain 10 locked the gate. + * 0b1100..Domain 11 locked the gate. + * 0b1101..Domain 12 locked the gate. + * 0b1110..Domain 13 locked the gate. + * 0b1111..Domain 14 locked the gate. + */ +#define SEMA42_GATE47_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE47_GTFSM_SHIFT)) & SEMA42_GATE47_GTFSM_MASK) +/*! @} */ + +/*! @name GATE46 - Gate */ +/*! @{ */ + +#define SEMA42_GATE46_GTFSM_MASK (0xFU) +#define SEMA42_GATE46_GTFSM_SHIFT (0U) +/*! GTFSM - Gate Finite State Machine + * 0b0000..The gate is unlocked (free). + * 0b0001..Domain 0 locked the gate. + * 0b0010..Domain 1 locked the gate. + * 0b0011..Domain 2 locked the gate. + * 0b0100..Domain 3 locked the gate. + * 0b0101..Domain 4 locked the gate. + * 0b0110..Domain 5 locked the gate. + * 0b0111..Domain 6 locked the gate. + * 0b1000..Domain 7 locked the gate. + * 0b1001..Domain 8 locked the gate. + * 0b1010..Domain 9 locked the gate. + * 0b1011..Domain 10 locked the gate. + * 0b1100..Domain 11 locked the gate. + * 0b1101..Domain 12 locked the gate. + * 0b1110..Domain 13 locked the gate. + * 0b1111..Domain 14 locked the gate. + */ +#define SEMA42_GATE46_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE46_GTFSM_SHIFT)) & SEMA42_GATE46_GTFSM_MASK) +/*! @} */ + +/*! @name GATE45 - Gate */ +/*! @{ */ + +#define SEMA42_GATE45_GTFSM_MASK (0xFU) +#define SEMA42_GATE45_GTFSM_SHIFT (0U) +/*! GTFSM - Gate Finite State Machine + * 0b0000..The gate is unlocked (free). + * 0b0001..Domain 0 locked the gate. + * 0b0010..Domain 1 locked the gate. + * 0b0011..Domain 2 locked the gate. + * 0b0100..Domain 3 locked the gate. + * 0b0101..Domain 4 locked the gate. + * 0b0110..Domain 5 locked the gate. + * 0b0111..Domain 6 locked the gate. + * 0b1000..Domain 7 locked the gate. + * 0b1001..Domain 8 locked the gate. + * 0b1010..Domain 9 locked the gate. + * 0b1011..Domain 10 locked the gate. + * 0b1100..Domain 11 locked the gate. + * 0b1101..Domain 12 locked the gate. + * 0b1110..Domain 13 locked the gate. + * 0b1111..Domain 14 locked the gate. + */ +#define SEMA42_GATE45_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE45_GTFSM_SHIFT)) & SEMA42_GATE45_GTFSM_MASK) +/*! @} */ + +/*! @name GATE44 - Gate */ +/*! @{ */ + +#define SEMA42_GATE44_GTFSM_MASK (0xFU) +#define SEMA42_GATE44_GTFSM_SHIFT (0U) +/*! GTFSM - Gate Finite State Machine + * 0b0000..The gate is unlocked (free). + * 0b0001..Domain 0 locked the gate. + * 0b0010..Domain 1 locked the gate. + * 0b0011..Domain 2 locked the gate. + * 0b0100..Domain 3 locked the gate. + * 0b0101..Domain 4 locked the gate. + * 0b0110..Domain 5 locked the gate. + * 0b0111..Domain 6 locked the gate. + * 0b1000..Domain 7 locked the gate. + * 0b1001..Domain 8 locked the gate. + * 0b1010..Domain 9 locked the gate. + * 0b1011..Domain 10 locked the gate. + * 0b1100..Domain 11 locked the gate. + * 0b1101..Domain 12 locked the gate. + * 0b1110..Domain 13 locked the gate. + * 0b1111..Domain 14 locked the gate. + */ +#define SEMA42_GATE44_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE44_GTFSM_SHIFT)) & SEMA42_GATE44_GTFSM_MASK) +/*! @} */ + +/*! @name GATE51 - Gate */ +/*! @{ */ + +#define SEMA42_GATE51_GTFSM_MASK (0xFU) +#define SEMA42_GATE51_GTFSM_SHIFT (0U) +/*! GTFSM - Gate Finite State Machine + * 0b0000..The gate is unlocked (free). + * 0b0001..Domain 0 locked the gate. + * 0b0010..Domain 1 locked the gate. + * 0b0011..Domain 2 locked the gate. + * 0b0100..Domain 3 locked the gate. + * 0b0101..Domain 4 locked the gate. + * 0b0110..Domain 5 locked the gate. + * 0b0111..Domain 6 locked the gate. + * 0b1000..Domain 7 locked the gate. + * 0b1001..Domain 8 locked the gate. + * 0b1010..Domain 9 locked the gate. + * 0b1011..Domain 10 locked the gate. + * 0b1100..Domain 11 locked the gate. + * 0b1101..Domain 12 locked the gate. + * 0b1110..Domain 13 locked the gate. + * 0b1111..Domain 14 locked the gate. + */ +#define SEMA42_GATE51_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE51_GTFSM_SHIFT)) & SEMA42_GATE51_GTFSM_MASK) +/*! @} */ + +/*! @name GATE50 - Gate */ +/*! @{ */ + +#define SEMA42_GATE50_GTFSM_MASK (0xFU) +#define SEMA42_GATE50_GTFSM_SHIFT (0U) +/*! GTFSM - Gate Finite State Machine + * 0b0000..The gate is unlocked (free). + * 0b0001..Domain 0 locked the gate. + * 0b0010..Domain 1 locked the gate. + * 0b0011..Domain 2 locked the gate. + * 0b0100..Domain 3 locked the gate. + * 0b0101..Domain 4 locked the gate. + * 0b0110..Domain 5 locked the gate. + * 0b0111..Domain 6 locked the gate. + * 0b1000..Domain 7 locked the gate. + * 0b1001..Domain 8 locked the gate. + * 0b1010..Domain 9 locked the gate. + * 0b1011..Domain 10 locked the gate. + * 0b1100..Domain 11 locked the gate. + * 0b1101..Domain 12 locked the gate. + * 0b1110..Domain 13 locked the gate. + * 0b1111..Domain 14 locked the gate. + */ +#define SEMA42_GATE50_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE50_GTFSM_SHIFT)) & SEMA42_GATE50_GTFSM_MASK) +/*! @} */ + +/*! @name GATE49 - Gate */ +/*! @{ */ + +#define SEMA42_GATE49_GTFSM_MASK (0xFU) +#define SEMA42_GATE49_GTFSM_SHIFT (0U) +/*! GTFSM - Gate Finite State Machine + * 0b0000..The gate is unlocked (free). + * 0b0001..Domain 0 locked the gate. + * 0b0010..Domain 1 locked the gate. + * 0b0011..Domain 2 locked the gate. + * 0b0100..Domain 3 locked the gate. + * 0b0101..Domain 4 locked the gate. + * 0b0110..Domain 5 locked the gate. + * 0b0111..Domain 6 locked the gate. + * 0b1000..Domain 7 locked the gate. + * 0b1001..Domain 8 locked the gate. + * 0b1010..Domain 9 locked the gate. + * 0b1011..Domain 10 locked the gate. + * 0b1100..Domain 11 locked the gate. + * 0b1101..Domain 12 locked the gate. + * 0b1110..Domain 13 locked the gate. + * 0b1111..Domain 14 locked the gate. + */ +#define SEMA42_GATE49_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE49_GTFSM_SHIFT)) & SEMA42_GATE49_GTFSM_MASK) +/*! @} */ + +/*! @name GATE48 - Gate */ +/*! @{ */ + +#define SEMA42_GATE48_GTFSM_MASK (0xFU) +#define SEMA42_GATE48_GTFSM_SHIFT (0U) +/*! GTFSM - Gate Finite State Machine + * 0b0000..The gate is unlocked (free). + * 0b0001..Domain 0 locked the gate. + * 0b0010..Domain 1 locked the gate. + * 0b0011..Domain 2 locked the gate. + * 0b0100..Domain 3 locked the gate. + * 0b0101..Domain 4 locked the gate. + * 0b0110..Domain 5 locked the gate. + * 0b0111..Domain 6 locked the gate. + * 0b1000..Domain 7 locked the gate. + * 0b1001..Domain 8 locked the gate. + * 0b1010..Domain 9 locked the gate. + * 0b1011..Domain 10 locked the gate. + * 0b1100..Domain 11 locked the gate. + * 0b1101..Domain 12 locked the gate. + * 0b1110..Domain 13 locked the gate. + * 0b1111..Domain 14 locked the gate. + */ +#define SEMA42_GATE48_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE48_GTFSM_SHIFT)) & SEMA42_GATE48_GTFSM_MASK) +/*! @} */ + +/*! @name GATE55 - Gate */ +/*! @{ */ + +#define SEMA42_GATE55_GTFSM_MASK (0xFU) +#define SEMA42_GATE55_GTFSM_SHIFT (0U) +/*! GTFSM - Gate Finite State Machine + * 0b0000..The gate is unlocked (free). + * 0b0001..Domain 0 locked the gate. + * 0b0010..Domain 1 locked the gate. + * 0b0011..Domain 2 locked the gate. + * 0b0100..Domain 3 locked the gate. + * 0b0101..Domain 4 locked the gate. + * 0b0110..Domain 5 locked the gate. + * 0b0111..Domain 6 locked the gate. + * 0b1000..Domain 7 locked the gate. + * 0b1001..Domain 8 locked the gate. + * 0b1010..Domain 9 locked the gate. + * 0b1011..Domain 10 locked the gate. + * 0b1100..Domain 11 locked the gate. + * 0b1101..Domain 12 locked the gate. + * 0b1110..Domain 13 locked the gate. + * 0b1111..Domain 14 locked the gate. + */ +#define SEMA42_GATE55_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE55_GTFSM_SHIFT)) & SEMA42_GATE55_GTFSM_MASK) +/*! @} */ + +/*! @name GATE54 - Gate */ +/*! @{ */ + +#define SEMA42_GATE54_GTFSM_MASK (0xFU) +#define SEMA42_GATE54_GTFSM_SHIFT (0U) +/*! GTFSM - Gate Finite State Machine + * 0b0000..The gate is unlocked (free). + * 0b0001..Domain 0 locked the gate. + * 0b0010..Domain 1 locked the gate. + * 0b0011..Domain 2 locked the gate. + * 0b0100..Domain 3 locked the gate. + * 0b0101..Domain 4 locked the gate. + * 0b0110..Domain 5 locked the gate. + * 0b0111..Domain 6 locked the gate. + * 0b1000..Domain 7 locked the gate. + * 0b1001..Domain 8 locked the gate. + * 0b1010..Domain 9 locked the gate. + * 0b1011..Domain 10 locked the gate. + * 0b1100..Domain 11 locked the gate. + * 0b1101..Domain 12 locked the gate. + * 0b1110..Domain 13 locked the gate. + * 0b1111..Domain 14 locked the gate. + */ +#define SEMA42_GATE54_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE54_GTFSM_SHIFT)) & SEMA42_GATE54_GTFSM_MASK) +/*! @} */ + +/*! @name GATE53 - Gate */ +/*! @{ */ + +#define SEMA42_GATE53_GTFSM_MASK (0xFU) +#define SEMA42_GATE53_GTFSM_SHIFT (0U) +/*! GTFSM - Gate Finite State Machine + * 0b0000..The gate is unlocked (free). + * 0b0001..Domain 0 locked the gate. + * 0b0010..Domain 1 locked the gate. + * 0b0011..Domain 2 locked the gate. + * 0b0100..Domain 3 locked the gate. + * 0b0101..Domain 4 locked the gate. + * 0b0110..Domain 5 locked the gate. + * 0b0111..Domain 6 locked the gate. + * 0b1000..Domain 7 locked the gate. + * 0b1001..Domain 8 locked the gate. + * 0b1010..Domain 9 locked the gate. + * 0b1011..Domain 10 locked the gate. + * 0b1100..Domain 11 locked the gate. + * 0b1101..Domain 12 locked the gate. + * 0b1110..Domain 13 locked the gate. + * 0b1111..Domain 14 locked the gate. + */ +#define SEMA42_GATE53_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE53_GTFSM_SHIFT)) & SEMA42_GATE53_GTFSM_MASK) +/*! @} */ + +/*! @name GATE52 - Gate */ +/*! @{ */ + +#define SEMA42_GATE52_GTFSM_MASK (0xFU) +#define SEMA42_GATE52_GTFSM_SHIFT (0U) +/*! GTFSM - Gate Finite State Machine + * 0b0000..The gate is unlocked (free). + * 0b0001..Domain 0 locked the gate. + * 0b0010..Domain 1 locked the gate. + * 0b0011..Domain 2 locked the gate. + * 0b0100..Domain 3 locked the gate. + * 0b0101..Domain 4 locked the gate. + * 0b0110..Domain 5 locked the gate. + * 0b0111..Domain 6 locked the gate. + * 0b1000..Domain 7 locked the gate. + * 0b1001..Domain 8 locked the gate. + * 0b1010..Domain 9 locked the gate. + * 0b1011..Domain 10 locked the gate. + * 0b1100..Domain 11 locked the gate. + * 0b1101..Domain 12 locked the gate. + * 0b1110..Domain 13 locked the gate. + * 0b1111..Domain 14 locked the gate. + */ +#define SEMA42_GATE52_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE52_GTFSM_SHIFT)) & SEMA42_GATE52_GTFSM_MASK) +/*! @} */ + +/*! @name GATE59 - Gate */ +/*! @{ */ + +#define SEMA42_GATE59_GTFSM_MASK (0xFU) +#define SEMA42_GATE59_GTFSM_SHIFT (0U) +/*! GTFSM - Gate Finite State Machine + * 0b0000..The gate is unlocked (free). + * 0b0001..Domain 0 locked the gate. + * 0b0010..Domain 1 locked the gate. + * 0b0011..Domain 2 locked the gate. + * 0b0100..Domain 3 locked the gate. + * 0b0101..Domain 4 locked the gate. + * 0b0110..Domain 5 locked the gate. + * 0b0111..Domain 6 locked the gate. + * 0b1000..Domain 7 locked the gate. + * 0b1001..Domain 8 locked the gate. + * 0b1010..Domain 9 locked the gate. + * 0b1011..Domain 10 locked the gate. + * 0b1100..Domain 11 locked the gate. + * 0b1101..Domain 12 locked the gate. + * 0b1110..Domain 13 locked the gate. + * 0b1111..Domain 14 locked the gate. + */ +#define SEMA42_GATE59_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE59_GTFSM_SHIFT)) & SEMA42_GATE59_GTFSM_MASK) +/*! @} */ + +/*! @name GATE58 - Gate */ +/*! @{ */ + +#define SEMA42_GATE58_GTFSM_MASK (0xFU) +#define SEMA42_GATE58_GTFSM_SHIFT (0U) +/*! GTFSM - Gate Finite State Machine + * 0b0000..The gate is unlocked (free). + * 0b0001..Domain 0 locked the gate. + * 0b0010..Domain 1 locked the gate. + * 0b0011..Domain 2 locked the gate. + * 0b0100..Domain 3 locked the gate. + * 0b0101..Domain 4 locked the gate. + * 0b0110..Domain 5 locked the gate. + * 0b0111..Domain 6 locked the gate. + * 0b1000..Domain 7 locked the gate. + * 0b1001..Domain 8 locked the gate. + * 0b1010..Domain 9 locked the gate. + * 0b1011..Domain 10 locked the gate. + * 0b1100..Domain 11 locked the gate. + * 0b1101..Domain 12 locked the gate. + * 0b1110..Domain 13 locked the gate. + * 0b1111..Domain 14 locked the gate. + */ +#define SEMA42_GATE58_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE58_GTFSM_SHIFT)) & SEMA42_GATE58_GTFSM_MASK) +/*! @} */ + +/*! @name GATE57 - Gate */ +/*! @{ */ + +#define SEMA42_GATE57_GTFSM_MASK (0xFU) +#define SEMA42_GATE57_GTFSM_SHIFT (0U) +/*! GTFSM - Gate Finite State Machine + * 0b0000..The gate is unlocked (free). + * 0b0001..Domain 0 locked the gate. + * 0b0010..Domain 1 locked the gate. + * 0b0011..Domain 2 locked the gate. + * 0b0100..Domain 3 locked the gate. + * 0b0101..Domain 4 locked the gate. + * 0b0110..Domain 5 locked the gate. + * 0b0111..Domain 6 locked the gate. + * 0b1000..Domain 7 locked the gate. + * 0b1001..Domain 8 locked the gate. + * 0b1010..Domain 9 locked the gate. + * 0b1011..Domain 10 locked the gate. + * 0b1100..Domain 11 locked the gate. + * 0b1101..Domain 12 locked the gate. + * 0b1110..Domain 13 locked the gate. + * 0b1111..Domain 14 locked the gate. + */ +#define SEMA42_GATE57_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE57_GTFSM_SHIFT)) & SEMA42_GATE57_GTFSM_MASK) +/*! @} */ + +/*! @name GATE56 - Gate */ +/*! @{ */ + +#define SEMA42_GATE56_GTFSM_MASK (0xFU) +#define SEMA42_GATE56_GTFSM_SHIFT (0U) +/*! GTFSM - Gate Finite State Machine + * 0b0000..The gate is unlocked (free). + * 0b0001..Domain 0 locked the gate. + * 0b0010..Domain 1 locked the gate. + * 0b0011..Domain 2 locked the gate. + * 0b0100..Domain 3 locked the gate. + * 0b0101..Domain 4 locked the gate. + * 0b0110..Domain 5 locked the gate. + * 0b0111..Domain 6 locked the gate. + * 0b1000..Domain 7 locked the gate. + * 0b1001..Domain 8 locked the gate. + * 0b1010..Domain 9 locked the gate. + * 0b1011..Domain 10 locked the gate. + * 0b1100..Domain 11 locked the gate. + * 0b1101..Domain 12 locked the gate. + * 0b1110..Domain 13 locked the gate. + * 0b1111..Domain 14 locked the gate. + */ +#define SEMA42_GATE56_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE56_GTFSM_SHIFT)) & SEMA42_GATE56_GTFSM_MASK) +/*! @} */ + +/*! @name GATE63 - Gate */ +/*! @{ */ + +#define SEMA42_GATE63_GTFSM_MASK (0xFU) +#define SEMA42_GATE63_GTFSM_SHIFT (0U) +/*! GTFSM - Gate Finite State Machine + * 0b0000..The gate is unlocked (free). + * 0b0001..Domain 0 locked the gate. + * 0b0010..Domain 1 locked the gate. + * 0b0011..Domain 2 locked the gate. + * 0b0100..Domain 3 locked the gate. + * 0b0101..Domain 4 locked the gate. + * 0b0110..Domain 5 locked the gate. + * 0b0111..Domain 6 locked the gate. + * 0b1000..Domain 7 locked the gate. + * 0b1001..Domain 8 locked the gate. + * 0b1010..Domain 9 locked the gate. + * 0b1011..Domain 10 locked the gate. + * 0b1100..Domain 11 locked the gate. + * 0b1101..Domain 12 locked the gate. + * 0b1110..Domain 13 locked the gate. + * 0b1111..Domain 14 locked the gate. + */ +#define SEMA42_GATE63_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE63_GTFSM_SHIFT)) & SEMA42_GATE63_GTFSM_MASK) +/*! @} */ + +/*! @name GATE62 - Gate */ +/*! @{ */ + +#define SEMA42_GATE62_GTFSM_MASK (0xFU) +#define SEMA42_GATE62_GTFSM_SHIFT (0U) +/*! GTFSM - Gate Finite State Machine + * 0b0000..The gate is unlocked (free). + * 0b0001..Domain 0 locked the gate. + * 0b0010..Domain 1 locked the gate. + * 0b0011..Domain 2 locked the gate. + * 0b0100..Domain 3 locked the gate. + * 0b0101..Domain 4 locked the gate. + * 0b0110..Domain 5 locked the gate. + * 0b0111..Domain 6 locked the gate. + * 0b1000..Domain 7 locked the gate. + * 0b1001..Domain 8 locked the gate. + * 0b1010..Domain 9 locked the gate. + * 0b1011..Domain 10 locked the gate. + * 0b1100..Domain 11 locked the gate. + * 0b1101..Domain 12 locked the gate. + * 0b1110..Domain 13 locked the gate. + * 0b1111..Domain 14 locked the gate. + */ +#define SEMA42_GATE62_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE62_GTFSM_SHIFT)) & SEMA42_GATE62_GTFSM_MASK) +/*! @} */ + +/*! @name GATE61 - Gate */ +/*! @{ */ + +#define SEMA42_GATE61_GTFSM_MASK (0xFU) +#define SEMA42_GATE61_GTFSM_SHIFT (0U) +/*! GTFSM - Gate Finite State Machine + * 0b0000..The gate is unlocked (free). + * 0b0001..Domain 0 locked the gate. + * 0b0010..Domain 1 locked the gate. + * 0b0011..Domain 2 locked the gate. + * 0b0100..Domain 3 locked the gate. + * 0b0101..Domain 4 locked the gate. + * 0b0110..Domain 5 locked the gate. + * 0b0111..Domain 6 locked the gate. + * 0b1000..Domain 7 locked the gate. + * 0b1001..Domain 8 locked the gate. + * 0b1010..Domain 9 locked the gate. + * 0b1011..Domain 10 locked the gate. + * 0b1100..Domain 11 locked the gate. + * 0b1101..Domain 12 locked the gate. + * 0b1110..Domain 13 locked the gate. + * 0b1111..Domain 14 locked the gate. + */ +#define SEMA42_GATE61_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE61_GTFSM_SHIFT)) & SEMA42_GATE61_GTFSM_MASK) +/*! @} */ + +/*! @name GATE60 - Gate */ +/*! @{ */ + +#define SEMA42_GATE60_GTFSM_MASK (0xFU) +#define SEMA42_GATE60_GTFSM_SHIFT (0U) +/*! GTFSM - Gate Finite State Machine + * 0b0000..The gate is unlocked (free). + * 0b0001..Domain 0 locked the gate. + * 0b0010..Domain 1 locked the gate. + * 0b0011..Domain 2 locked the gate. + * 0b0100..Domain 3 locked the gate. + * 0b0101..Domain 4 locked the gate. + * 0b0110..Domain 5 locked the gate. + * 0b0111..Domain 6 locked the gate. + * 0b1000..Domain 7 locked the gate. + * 0b1001..Domain 8 locked the gate. + * 0b1010..Domain 9 locked the gate. + * 0b1011..Domain 10 locked the gate. + * 0b1100..Domain 11 locked the gate. + * 0b1101..Domain 12 locked the gate. + * 0b1110..Domain 13 locked the gate. + * 0b1111..Domain 14 locked the gate. + */ +#define SEMA42_GATE60_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE60_GTFSM_SHIFT)) & SEMA42_GATE60_GTFSM_MASK) +/*! @} */ + +/*! @name RSTGT_R - Reset Gate Read */ +/*! @{ */ + +#define SEMA42_RSTGT_R_RSTGTN_MASK (0xFFU) +#define SEMA42_RSTGT_R_RSTGTN_SHIFT (0U) +/*! RSTGTN - Reset Gate Number */ +#define SEMA42_RSTGT_R_RSTGTN(x) (((uint16_t)(((uint16_t)(x)) << SEMA42_RSTGT_R_RSTGTN_SHIFT)) & SEMA42_RSTGT_R_RSTGTN_MASK) + +#define SEMA42_RSTGT_R_RSTGMS_MASK (0xF00U) +#define SEMA42_RSTGT_R_RSTGMS_SHIFT (8U) +/*! RSTGMS - Reset Gate Domain */ +#define SEMA42_RSTGT_R_RSTGMS(x) (((uint16_t)(((uint16_t)(x)) << SEMA42_RSTGT_R_RSTGMS_SHIFT)) & SEMA42_RSTGT_R_RSTGMS_MASK) + +#define SEMA42_RSTGT_R_RSTGSM_MASK (0x3000U) +#define SEMA42_RSTGT_R_RSTGSM_SHIFT (12U) +/*! RSTGSM - Reset Gate Finite State Machine + * 0b00..Idle, waiting for the first data pattern write. + * 0b01..Waiting for the second data pattern write + * 0b10..The 2-write sequence has completed. Generate the specified gate reset(s). After the reset is performed, + * this machine returns to the idle (waiting for first data pattern write) state. + * 0b11..This state encoding is never used and therefore reserved. + */ +#define SEMA42_RSTGT_R_RSTGSM(x) (((uint16_t)(((uint16_t)(x)) << SEMA42_RSTGT_R_RSTGSM_SHIFT)) & SEMA42_RSTGT_R_RSTGSM_MASK) +/*! @} */ + +/*! @name RSTGT_W - Reset Gate Write */ +/*! @{ */ + +#define SEMA42_RSTGT_W_RSTGTN_MASK (0xFFU) +#define SEMA42_RSTGT_W_RSTGTN_SHIFT (0U) +/*! RSTGTN - Reset Gate Number */ +#define SEMA42_RSTGT_W_RSTGTN(x) (((uint16_t)(((uint16_t)(x)) << SEMA42_RSTGT_W_RSTGTN_SHIFT)) & SEMA42_RSTGT_W_RSTGTN_MASK) + +#define SEMA42_RSTGT_W_RSTGDP_MASK (0xFF00U) +#define SEMA42_RSTGT_W_RSTGDP_SHIFT (8U) +/*! RSTGDP - Reset Gate Data Pattern */ +#define SEMA42_RSTGT_W_RSTGDP(x) (((uint16_t)(((uint16_t)(x)) << SEMA42_RSTGT_W_RSTGDP_SHIFT)) & SEMA42_RSTGT_W_RSTGDP_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group SEMA42_Register_Masks */ + + +/* SEMA42 - Peripheral instance base addresses */ +/** Peripheral SEMA42_1 base address */ +#define SEMA42_1_BASE (0x44260000u) +/** Peripheral SEMA42_1 base pointer */ +#define SEMA42_1 ((SEMA42_Type *)SEMA42_1_BASE) +/** Peripheral SEMA42_2 base address */ +#define SEMA42_2_BASE (0x42450000u) +/** Peripheral SEMA42_2 base pointer */ +#define SEMA42_2 ((SEMA42_Type *)SEMA42_2_BASE) +/** Array initializer of SEMA42 peripheral base addresses */ +#define SEMA42_BASE_ADDRS { 0u, SEMA42_1_BASE, SEMA42_2_BASE } +/** Array initializer of SEMA42 peripheral base pointers */ +#define SEMA42_BASE_PTRS { (SEMA42_Type *)0u, SEMA42_1, SEMA42_2 } + +/*! + * @} + */ /* end of group SEMA42_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- SPDIF Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SPDIF_Peripheral_Access_Layer SPDIF Peripheral Access Layer + * @{ + */ + +/** SPDIF - Register Layout Typedef */ +typedef struct { + __IO uint32_t VERSION; /**< Version control register, offset: 0x0 */ + uint8_t RESERVED_0[12]; + struct { /* offset: 0x10 */ + __IO uint32_t RW; /**< External control register, offset: 0x10 */ + __IO uint32_t SET; /**< External control register, offset: 0x14 */ + __IO uint32_t CLR; /**< External control register, offset: 0x18 */ + __IO uint32_t TOG; /**< External control register, offset: 0x1C */ + } EXT_CTRL; + struct { /* offset: 0x20 */ + __IO uint32_t RW; /**< External Status register, offset: 0x20 */ + __IO uint32_t SET; /**< External Status register, offset: 0x24 */ + __IO uint32_t CLR; /**< External Status register, offset: 0x28 */ + __IO uint32_t TOG; /**< External Status register, offset: 0x2C */ + } EXT_STATUS; + struct { /* offset: 0x30 */ + __IO uint32_t RW; /**< Interrupt enables for interrupt 0, offset: 0x30 */ + __IO uint32_t SET; /**< Interrupt enables for interrupt 0, offset: 0x34 */ + __IO uint32_t CLR; /**< Interrupt enables for interrupt 0, offset: 0x38 */ + __IO uint32_t TOG; /**< Interrupt enables for interrupt 0, offset: 0x3C */ + } EXT_IER0; + struct { /* offset: 0x40 */ + __IO uint32_t RW; /**< Interrupt enables for interrupt 1, offset: 0x40 */ + __IO uint32_t SET; /**< Interrupt enables for interrupt 1, offset: 0x44 */ + __IO uint32_t CLR; /**< Interrupt enables for interrupt 1, offset: 0x48 */ + __IO uint32_t TOG; /**< Interrupt enables for interrupt 1, offset: 0x4C */ + } EXT_IER1; + struct { /* offset: 0x50 */ + __IO uint32_t RW; /**< External Interrupt Status register, offset: 0x50 */ + __IO uint32_t SET; /**< External Interrupt Status register, offset: 0x54 */ + __IO uint32_t CLR; /**< External Interrupt Status register, offset: 0x58 */ + __IO uint32_t TOG; /**< External Interrupt Status register, offset: 0x5C */ + } EXT_ISR; + uint8_t RESERVED_1[72]; + __I uint32_t DPATH_STATUS; /**< Audio XCVR datapath status, offset: 0xA8 */ + uint8_t RESERVED_2[4]; + __IO uint32_t CLK_CTRL; /**< Clock control register, offset: 0xB0 */ + uint8_t RESERVED_3[204]; + struct { /* offset: 0x180 */ + __IO uint32_t RW; /**< Data path control register, offset: 0x180 */ + __IO uint32_t SET; /**< Data path control register, offset: 0x184 */ + __IO uint32_t CLR; /**< Data path control register, offset: 0x188 */ + __IO uint32_t TOG; /**< Data path control register, offset: 0x18C */ + } RX_DATAPATH_CTRL; + __I uint32_t RX_CS_DATA_BITS[6]; /**< Channel staus bits, array offset: 0x190, array step: 0x4 */ + __I uint32_t RX_USER_DATA_BITS[6]; /**< User data bits, array offset: 0x1A8, array step: 0x4 */ + struct { /* offset: 0x1C0 */ + __IO uint32_t RW; /**< Receive Datapath counter control register, offset: 0x1C0 */ + __IO uint32_t SET; /**< Receive Datapath counter control register, offset: 0x1C4 */ + __IO uint32_t CLR; /**< Receive Datapath counter control register, offset: 0x1C8 */ + __IO uint32_t TOG; /**< Receive Datapath counter control register, offset: 0x1CC */ + } RX_DPATH_CNTR_CTRL; + __I uint32_t RX_DPATH_TSCR; /**< Receive Datapath Timestamp Counter Register, offset: 0x1D0 */ + __I uint32_t RX_DPATH_BCR; /**< Receive Datapath Bit counter register, offset: 0x1D4 */ + __I uint32_t RX_DPATH_BCTR; /**< Receive datapath Bit count timestamp register., offset: 0x1D8 */ + __I uint32_t RX_DPATH_BCRR; /**< Receive datapath Bit read timestamp register., offset: 0x1DC */ + struct { /* offset: 0x1E0 */ + __IO uint32_t RW; /**< Preamble match value register, offset: 0x1E0 */ + __IO uint32_t SET; /**< Preamble match value register, offset: 0x1E4 */ + __IO uint32_t CLR; /**< Preamble match value register, offset: 0x1E8 */ + __IO uint32_t TOG; /**< Preamble match value register, offset: 0x1EC */ + } PRE_MATCH_VAL; + struct { /* offset: 0x1F0 */ + __IO uint32_t RW; /**< Preamble match value register, offset: 0x1F0 */ + __IO uint32_t SET; /**< Preamble match value register, offset: 0x1F4 */ + __IO uint32_t CLR; /**< Preamble match value register, offset: 0x1F8 */ + __IO uint32_t TOG; /**< Preamble match value register, offset: 0x1FC */ + } DTS_PRE_MATCH_VAL; + __IO uint32_t RX_DPATH_PRE_ERR; /**< Error count for IEC60958-1 Block Synchronization., offset: 0x200 */ + __IO uint32_t RX_DPATH_PARITY_ERR; /**< Parity Error count for IEC60958-1 Blocks., offset: 0x204 */ + uint8_t RESERVED_4[8]; + __I uint32_t RX_DPATH_PKT_CNT; /**< Receive Data packet count., offset: 0x210 */ + uint8_t RESERVED_5[4]; + __I uint32_t PRE_MATCH_OFFSET; /**< Preamble match offset value register, offset: 0x218 */ + uint8_t RESERVED_6[4]; + struct { /* offset: 0x220 */ + __IO uint32_t RW; /**< Transmit Data path control register, offset: 0x220 */ + __IO uint32_t SET; /**< Transmit Data path control register, offset: 0x224 */ + __IO uint32_t CLR; /**< Transmit Data path control register, offset: 0x228 */ + __IO uint32_t TOG; /**< Transmit Data path control register, offset: 0x22C */ + } TX_DATAPATH_CTRL; + __IO uint32_t TX_CS_DATA_BITS[6]; /**< Channel staus bits, array offset: 0x230, array step: 0x4 */ + __IO uint32_t TX_USER_DATA_BITS[6]; /**< User data bits, array offset: 0x248, array step: 0x4 */ + struct { /* offset: 0x260 */ + __IO uint32_t RW; /**< Transmit datapath counter control register, offset: 0x260 */ + __IO uint32_t SET; /**< Transmit datapath counter control register, offset: 0x264 */ + __IO uint32_t CLR; /**< Transmit datapath counter control register, offset: 0x268 */ + __IO uint32_t TOG; /**< Transmit datapath counter control register, offset: 0x26C */ + } TX_DPATH_CNTR_CTRL; + __I uint32_t TX_DPATH_TSCR; /**< Transmit Datapath Timestamp Counter Register, offset: 0x270 */ + __I uint32_t TX_DPATH_BCR; /**< Transmit Datapath Bit counter register, offset: 0x274 */ + __I uint32_t TX_DPATH_BCTR; /**< Transmit datapath Bit count timestamp register., offset: 0x278 */ + __I uint32_t TX_DPATH_BCRR; /**< Transmmit datapath Bit read timestamp register., offset: 0x27C */ +} SPDIF_Type; + +/* ---------------------------------------------------------------------------- + -- SPDIF Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SPDIF_Register_Masks SPDIF Register Masks + * @{ + */ + +/*! @name VERSION - Version control register */ +/*! @{ */ + +#define SPDIF_VERSION_VERID_MASK (0xFFFFFFFFU) +#define SPDIF_VERSION_VERID_SHIFT (0U) +/*! VERID - Version ID */ +#define SPDIF_VERSION_VERID(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_VERSION_VERID_SHIFT)) & SPDIF_VERSION_VERID_MASK) +/*! @} */ + +/*! @name EXT_CTRL - External control register */ +/*! @{ */ + +#define SPDIF_EXT_CTRL_TX_FIFO_WMARK_MASK (0x7FU) +#define SPDIF_EXT_CTRL_TX_FIFO_WMARK_SHIFT (0U) +/*! TX_FIFO_WMARK - Audio Transmit FIFO Watermark Level */ +#define SPDIF_EXT_CTRL_TX_FIFO_WMARK(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_EXT_CTRL_TX_FIFO_WMARK_SHIFT)) & SPDIF_EXT_CTRL_TX_FIFO_WMARK_MASK) + +#define SPDIF_EXT_CTRL_RX_FIFO_WMARK_MASK (0x7F00U) +#define SPDIF_EXT_CTRL_RX_FIFO_WMARK_SHIFT (8U) +/*! RX_FIFO_WMARK - Audio Receive FIFO Watermark Level */ +#define SPDIF_EXT_CTRL_RX_FIFO_WMARK(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_EXT_CTRL_RX_FIFO_WMARK_SHIFT)) & SPDIF_EXT_CTRL_RX_FIFO_WMARK_MASK) + +#define SPDIF_EXT_CTRL_EN_SPDIF_WAKEUP_MASK (0x100000U) +#define SPDIF_EXT_CTRL_EN_SPDIF_WAKEUP_SHIFT (20U) +/*! EN_SPDIF_WAKEUP - Enable SPDIF wakeup interrupt */ +#define SPDIF_EXT_CTRL_EN_SPDIF_WAKEUP(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_EXT_CTRL_EN_SPDIF_WAKEUP_SHIFT)) & SPDIF_EXT_CTRL_EN_SPDIF_WAKEUP_MASK) + +#define SPDIF_EXT_CTRL_SDMA_WR_REQ_DIS_MASK (0x1000000U) +#define SPDIF_EXT_CTRL_SDMA_WR_REQ_DIS_SHIFT (24U) +/*! SDMA_WR_REQ_DIS - SDMA WR REQ disable */ +#define SPDIF_EXT_CTRL_SDMA_WR_REQ_DIS(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_EXT_CTRL_SDMA_WR_REQ_DIS_SHIFT)) & SPDIF_EXT_CTRL_SDMA_WR_REQ_DIS_MASK) + +#define SPDIF_EXT_CTRL_SDMA_RD_REQ_DIS_MASK (0x2000000U) +#define SPDIF_EXT_CTRL_SDMA_RD_REQ_DIS_SHIFT (25U) +/*! SDMA_RD_REQ_DIS - SDMA RD REQ disable */ +#define SPDIF_EXT_CTRL_SDMA_RD_REQ_DIS(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_EXT_CTRL_SDMA_RD_REQ_DIS_SHIFT)) & SPDIF_EXT_CTRL_SDMA_RD_REQ_DIS_MASK) + +#define SPDIF_EXT_CTRL_TX_DPATH_RESET_MASK (0x8000000U) +#define SPDIF_EXT_CTRL_TX_DPATH_RESET_SHIFT (27U) +/*! TX_DPATH_RESET - Soft reset to SPDIF Transmit datapath */ +#define SPDIF_EXT_CTRL_TX_DPATH_RESET(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_EXT_CTRL_TX_DPATH_RESET_SHIFT)) & SPDIF_EXT_CTRL_TX_DPATH_RESET_MASK) + +#define SPDIF_EXT_CTRL_RX_DPATH_RESET_MASK (0x10000000U) +#define SPDIF_EXT_CTRL_RX_DPATH_RESET_SHIFT (28U) +/*! RX_DPATH_RESET - Soft reset to SPDIF Receive datapath */ +#define SPDIF_EXT_CTRL_RX_DPATH_RESET(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_EXT_CTRL_RX_DPATH_RESET_SHIFT)) & SPDIF_EXT_CTRL_RX_DPATH_RESET_MASK) +/*! @} */ + +/*! @name EXT_STATUS - External Status register */ +/*! @{ */ + +#define SPDIF_EXT_STATUS_NO_TX_FIFO_ENTRIES_MASK (0xFFU) +#define SPDIF_EXT_STATUS_NO_TX_FIFO_ENTRIES_SHIFT (0U) +/*! NO_TX_FIFO_ENTRIES - TX FIFO entries */ +#define SPDIF_EXT_STATUS_NO_TX_FIFO_ENTRIES(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_EXT_STATUS_NO_TX_FIFO_ENTRIES_SHIFT)) & SPDIF_EXT_STATUS_NO_TX_FIFO_ENTRIES_MASK) + +#define SPDIF_EXT_STATUS_NO_RX_FIFO_ENTRIES_MASK (0xFF00U) +#define SPDIF_EXT_STATUS_NO_RX_FIFO_ENTRIES_SHIFT (8U) +/*! NO_RX_FIFO_ENTRIES - RX FIFO entries */ +#define SPDIF_EXT_STATUS_NO_RX_FIFO_ENTRIES(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_EXT_STATUS_NO_RX_FIFO_ENTRIES_SHIFT)) & SPDIF_EXT_STATUS_NO_RX_FIFO_ENTRIES_MASK) + +#define SPDIF_EXT_STATUS_TX_PIPE_EMPTY_MASK (0x200000U) +#define SPDIF_EXT_STATUS_TX_PIPE_EMPTY_SHIFT (21U) +/*! TX_PIPE_EMPTY - Indicates TX pipe status. */ +#define SPDIF_EXT_STATUS_TX_PIPE_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_EXT_STATUS_TX_PIPE_EMPTY_SHIFT)) & SPDIF_EXT_STATUS_TX_PIPE_EMPTY_MASK) + +#define SPDIF_EXT_STATUS_PREV_UD_0_MASK (0x400000U) +#define SPDIF_EXT_STATUS_PREV_UD_0_SHIFT (22U) +/*! PREV_UD_0 - Last User data received was all 0 */ +#define SPDIF_EXT_STATUS_PREV_UD_0(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_EXT_STATUS_PREV_UD_0_SHIFT)) & SPDIF_EXT_STATUS_PREV_UD_0_MASK) +/*! @} */ + +/*! @name EXT_IER0 - Interrupt enables for interrupt 0 */ +/*! @{ */ + +#define SPDIF_EXT_IER0_NEW_CS_IE_0_MASK (0x1U) +#define SPDIF_EXT_IER0_NEW_CS_IE_0_SHIFT (0U) +/*! NEW_CS_IE_0 - Enable for New channel status block received interrupt */ +#define SPDIF_EXT_IER0_NEW_CS_IE_0(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_EXT_IER0_NEW_CS_IE_0_SHIFT)) & SPDIF_EXT_IER0_NEW_CS_IE_0_MASK) + +#define SPDIF_EXT_IER0_UD_IE_0_MASK (0x2U) +#define SPDIF_EXT_IER0_UD_IE_0_SHIFT (1U) +/*! UD_IE_0 - Enable for user data received interrupt */ +#define SPDIF_EXT_IER0_UD_IE_0(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_EXT_IER0_UD_IE_0_SHIFT)) & SPDIF_EXT_IER0_UD_IE_0_MASK) + +#define SPDIF_EXT_IER0_MUTE_IE_0_MASK (0x4U) +#define SPDIF_EXT_IER0_MUTE_IE_0_SHIFT (2U) +/*! MUTE_IE_0 - Enable for Mute detected interrupt */ +#define SPDIF_EXT_IER0_MUTE_IE_0(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_EXT_IER0_MUTE_IE_0_SHIFT)) & SPDIF_EXT_IER0_MUTE_IE_0_MASK) + +#define SPDIF_EXT_IER0_PREAMBLE_MISMATCH_IE_0_MASK (0x20U) +#define SPDIF_EXT_IER0_PREAMBLE_MISMATCH_IE_0_SHIFT (5U) +/*! PREAMBLE_MISMATCH_IE_0 - Preamble mismatch interrupt enable. */ +#define SPDIF_EXT_IER0_PREAMBLE_MISMATCH_IE_0(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_EXT_IER0_PREAMBLE_MISMATCH_IE_0_SHIFT)) & SPDIF_EXT_IER0_PREAMBLE_MISMATCH_IE_0_MASK) + +#define SPDIF_EXT_IER0_FIFO_OFLOW_UFLOW_ERR_IE_0_MASK (0x40U) +#define SPDIF_EXT_IER0_FIFO_OFLOW_UFLOW_ERR_IE_0_SHIFT (6U) +/*! FIFO_OFLOW_UFLOW_ERR_IE_0 - Receive FIFO overflow error interrupt enable. */ +#define SPDIF_EXT_IER0_FIFO_OFLOW_UFLOW_ERR_IE_0(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_EXT_IER0_FIFO_OFLOW_UFLOW_ERR_IE_0_SHIFT)) & SPDIF_EXT_IER0_FIFO_OFLOW_UFLOW_ERR_IE_0_MASK) + +#define SPDIF_EXT_IER0_RX_NO_DATA_REC_IE_0_MASK (0x200U) +#define SPDIF_EXT_IER0_RX_NO_DATA_REC_IE_0_SHIFT (9U) +/*! RX_NO_DATA_REC_IE_0 - Indicates no data is received. */ +#define SPDIF_EXT_IER0_RX_NO_DATA_REC_IE_0(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_EXT_IER0_RX_NO_DATA_REC_IE_0_SHIFT)) & SPDIF_EXT_IER0_RX_NO_DATA_REC_IE_0_MASK) + +#define SPDIF_EXT_IER0_DMA_RD_REQ_IE_0_MASK (0x4000U) +#define SPDIF_EXT_IER0_DMA_RD_REQ_IE_0_SHIFT (14U) +/*! DMA_RD_REQ_IE_0 - Request to read data from FIFO. */ +#define SPDIF_EXT_IER0_DMA_RD_REQ_IE_0(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_EXT_IER0_DMA_RD_REQ_IE_0_SHIFT)) & SPDIF_EXT_IER0_DMA_RD_REQ_IE_0_MASK) + +#define SPDIF_EXT_IER0_DMA_WR_REQ_IE_0_MASK (0x8000U) +#define SPDIF_EXT_IER0_DMA_WR_REQ_IE_0_SHIFT (15U) +/*! DMA_WR_REQ_IE_0 - Request to write data to FIFO. */ +#define SPDIF_EXT_IER0_DMA_WR_REQ_IE_0(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_EXT_IER0_DMA_WR_REQ_IE_0_SHIFT)) & SPDIF_EXT_IER0_DMA_WR_REQ_IE_0_MASK) + +#define SPDIF_EXT_IER0_RX_DATA_BME_ERR_IE_0_MASK (0x10000U) +#define SPDIF_EXT_IER0_RX_DATA_BME_ERR_IE_0_SHIFT (16U) +/*! RX_DATA_BME_ERR_IE_0 - Bi-phase mark encoding error */ +#define SPDIF_EXT_IER0_RX_DATA_BME_ERR_IE_0(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_EXT_IER0_RX_DATA_BME_ERR_IE_0_SHIFT)) & SPDIF_EXT_IER0_RX_DATA_BME_ERR_IE_0_MASK) + +#define SPDIF_EXT_IER0_PREAMBLE_MATCH_IE_0_MASK (0x20000U) +#define SPDIF_EXT_IER0_PREAMBLE_MATCH_IE_0_SHIFT (17U) +/*! PREAMBLE_MATCH_IE_0 - Interrupt enable for preamble match received. */ +#define SPDIF_EXT_IER0_PREAMBLE_MATCH_IE_0(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_EXT_IER0_PREAMBLE_MATCH_IE_0_SHIFT)) & SPDIF_EXT_IER0_PREAMBLE_MATCH_IE_0_MASK) + +#define SPDIF_EXT_IER0_M_W_PRE_MISMATCH_IE_0_MASK (0x40000U) +#define SPDIF_EXT_IER0_M_W_PRE_MISMATCH_IE_0_SHIFT (18U) +/*! M_W_PRE_MISMATCH_IE_0 - Interrupt enable for sub-frame M/W preamble mismatch received. */ +#define SPDIF_EXT_IER0_M_W_PRE_MISMATCH_IE_0(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_EXT_IER0_M_W_PRE_MISMATCH_IE_0_SHIFT)) & SPDIF_EXT_IER0_M_W_PRE_MISMATCH_IE_0_MASK) + +#define SPDIF_EXT_IER0_B_PRE_MISMATCH_IE_0_MASK (0x80000U) +#define SPDIF_EXT_IER0_B_PRE_MISMATCH_IE_0_SHIFT (19U) +/*! B_PRE_MISMATCH_IE_0 - Interrupt enable for sub-frame B preamble mismatch received. */ +#define SPDIF_EXT_IER0_B_PRE_MISMATCH_IE_0(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_EXT_IER0_B_PRE_MISMATCH_IE_0_SHIFT)) & SPDIF_EXT_IER0_B_PRE_MISMATCH_IE_0_MASK) + +#define SPDIF_EXT_IER0_UNEXP_PRE_REC_IE_0_MASK (0x100000U) +#define SPDIF_EXT_IER0_UNEXP_PRE_REC_IE_0_SHIFT (20U) +/*! UNEXP_PRE_REC_IE_0 - Interrupt enable for Unexpected preamble received. */ +#define SPDIF_EXT_IER0_UNEXP_PRE_REC_IE_0(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_EXT_IER0_UNEXP_PRE_REC_IE_0_SHIFT)) & SPDIF_EXT_IER0_UNEXP_PRE_REC_IE_0_MASK) + +#define SPDIF_EXT_IER0_CS_UD_OFLOW_IE_0_MASK (0x400000U) +#define SPDIF_EXT_IER0_CS_UD_OFLOW_IE_0_SHIFT (22U) +/*! CS_UD_OFLOW_IE_0 - Channel status or used data could not be stored. */ +#define SPDIF_EXT_IER0_CS_UD_OFLOW_IE_0(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_EXT_IER0_CS_UD_OFLOW_IE_0_SHIFT)) & SPDIF_EXT_IER0_CS_UD_OFLOW_IE_0_MASK) + +#define SPDIF_EXT_IER0_NEW_BLK_RCVD_IE_0_MASK (0x800000U) +#define SPDIF_EXT_IER0_NEW_BLK_RCVD_IE_0_SHIFT (23U) +/*! NEW_BLK_RCVD_IE_0 - New block of data was received. */ +#define SPDIF_EXT_IER0_NEW_BLK_RCVD_IE_0(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_EXT_IER0_NEW_BLK_RCVD_IE_0_SHIFT)) & SPDIF_EXT_IER0_NEW_BLK_RCVD_IE_0_MASK) + +#define SPDIF_EXT_IER0_SPDIF_WAKEUP_IE_0_MASK (0x1000000U) +#define SPDIF_EXT_IER0_SPDIF_WAKEUP_IE_0_SHIFT (24U) +/*! SPDIF_WAKEUP_IE_0 - SPDIF Wakeup interrupt enable. */ +#define SPDIF_EXT_IER0_SPDIF_WAKEUP_IE_0(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_EXT_IER0_SPDIF_WAKEUP_IE_0_SHIFT)) & SPDIF_EXT_IER0_SPDIF_WAKEUP_IE_0_MASK) +/*! @} */ + +/*! @name EXT_IER1 - Interrupt enables for interrupt 1 */ +/*! @{ */ + +#define SPDIF_EXT_IER1_NEW_CS_IE_1_MASK (0x1U) +#define SPDIF_EXT_IER1_NEW_CS_IE_1_SHIFT (0U) +/*! NEW_CS_IE_1 - Enable for New channel status block received interrupt */ +#define SPDIF_EXT_IER1_NEW_CS_IE_1(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_EXT_IER1_NEW_CS_IE_1_SHIFT)) & SPDIF_EXT_IER1_NEW_CS_IE_1_MASK) + +#define SPDIF_EXT_IER1_UD_IE_1_MASK (0x2U) +#define SPDIF_EXT_IER1_UD_IE_1_SHIFT (1U) +/*! UD_IE_1 - Enable for user data received interrupt */ +#define SPDIF_EXT_IER1_UD_IE_1(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_EXT_IER1_UD_IE_1_SHIFT)) & SPDIF_EXT_IER1_UD_IE_1_MASK) + +#define SPDIF_EXT_IER1_MUTE_IE_1_MASK (0x4U) +#define SPDIF_EXT_IER1_MUTE_IE_1_SHIFT (2U) +/*! MUTE_IE_1 - Enable for Mute detected interrupt */ +#define SPDIF_EXT_IER1_MUTE_IE_1(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_EXT_IER1_MUTE_IE_1_SHIFT)) & SPDIF_EXT_IER1_MUTE_IE_1_MASK) + +#define SPDIF_EXT_IER1_PREAMBLE_MISMATCH_IE_1_MASK (0x20U) +#define SPDIF_EXT_IER1_PREAMBLE_MISMATCH_IE_1_SHIFT (5U) +/*! PREAMBLE_MISMATCH_IE_1 - Preamble mismatch interrupt enable. */ +#define SPDIF_EXT_IER1_PREAMBLE_MISMATCH_IE_1(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_EXT_IER1_PREAMBLE_MISMATCH_IE_1_SHIFT)) & SPDIF_EXT_IER1_PREAMBLE_MISMATCH_IE_1_MASK) + +#define SPDIF_EXT_IER1_FIFO_OFLOW_UFLOW_ERR_IE_1_MASK (0x40U) +#define SPDIF_EXT_IER1_FIFO_OFLOW_UFLOW_ERR_IE_1_SHIFT (6U) +/*! FIFO_OFLOW_UFLOW_ERR_IE_1 - Receive FIFO overflow error interrupt enable. */ +#define SPDIF_EXT_IER1_FIFO_OFLOW_UFLOW_ERR_IE_1(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_EXT_IER1_FIFO_OFLOW_UFLOW_ERR_IE_1_SHIFT)) & SPDIF_EXT_IER1_FIFO_OFLOW_UFLOW_ERR_IE_1_MASK) + +#define SPDIF_EXT_IER1_RX_NO_DATA_REC_IE_1_MASK (0x200U) +#define SPDIF_EXT_IER1_RX_NO_DATA_REC_IE_1_SHIFT (9U) +/*! RX_NO_DATA_REC_IE_1 - Indicates no data is received. */ +#define SPDIF_EXT_IER1_RX_NO_DATA_REC_IE_1(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_EXT_IER1_RX_NO_DATA_REC_IE_1_SHIFT)) & SPDIF_EXT_IER1_RX_NO_DATA_REC_IE_1_MASK) + +#define SPDIF_EXT_IER1_DMA_RD_REQ_IE_1_MASK (0x4000U) +#define SPDIF_EXT_IER1_DMA_RD_REQ_IE_1_SHIFT (14U) +/*! DMA_RD_REQ_IE_1 - Request to read data from FIFO. */ +#define SPDIF_EXT_IER1_DMA_RD_REQ_IE_1(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_EXT_IER1_DMA_RD_REQ_IE_1_SHIFT)) & SPDIF_EXT_IER1_DMA_RD_REQ_IE_1_MASK) + +#define SPDIF_EXT_IER1_DMA_WR_REQ_IE_1_MASK (0x8000U) +#define SPDIF_EXT_IER1_DMA_WR_REQ_IE_1_SHIFT (15U) +/*! DMA_WR_REQ_IE_1 - Request to write data to FIFO. */ +#define SPDIF_EXT_IER1_DMA_WR_REQ_IE_1(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_EXT_IER1_DMA_WR_REQ_IE_1_SHIFT)) & SPDIF_EXT_IER1_DMA_WR_REQ_IE_1_MASK) + +#define SPDIF_EXT_IER1_RX_DATA_BME_ERR_IE_1_MASK (0x10000U) +#define SPDIF_EXT_IER1_RX_DATA_BME_ERR_IE_1_SHIFT (16U) +/*! RX_DATA_BME_ERR_IE_1 - Bi-phase mark encoding error */ +#define SPDIF_EXT_IER1_RX_DATA_BME_ERR_IE_1(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_EXT_IER1_RX_DATA_BME_ERR_IE_1_SHIFT)) & SPDIF_EXT_IER1_RX_DATA_BME_ERR_IE_1_MASK) + +#define SPDIF_EXT_IER1_PREAMBLE_MATCH_IE_1_MASK (0x20000U) +#define SPDIF_EXT_IER1_PREAMBLE_MATCH_IE_1_SHIFT (17U) +/*! PREAMBLE_MATCH_IE_1 - Interrupt enable for preamble match received. */ +#define SPDIF_EXT_IER1_PREAMBLE_MATCH_IE_1(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_EXT_IER1_PREAMBLE_MATCH_IE_1_SHIFT)) & SPDIF_EXT_IER1_PREAMBLE_MATCH_IE_1_MASK) + +#define SPDIF_EXT_IER1_M_W_PRE_MISMATCH_IE_1_MASK (0x40000U) +#define SPDIF_EXT_IER1_M_W_PRE_MISMATCH_IE_1_SHIFT (18U) +/*! M_W_PRE_MISMATCH_IE_1 - Interrupt enable for sub-frame M/W preamble mismatch received. */ +#define SPDIF_EXT_IER1_M_W_PRE_MISMATCH_IE_1(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_EXT_IER1_M_W_PRE_MISMATCH_IE_1_SHIFT)) & SPDIF_EXT_IER1_M_W_PRE_MISMATCH_IE_1_MASK) + +#define SPDIF_EXT_IER1_B_PRE_MISMATCH_IE_1_MASK (0x80000U) +#define SPDIF_EXT_IER1_B_PRE_MISMATCH_IE_1_SHIFT (19U) +/*! B_PRE_MISMATCH_IE_1 - Interrupt enable for sub-frame B preamble mismatch received. */ +#define SPDIF_EXT_IER1_B_PRE_MISMATCH_IE_1(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_EXT_IER1_B_PRE_MISMATCH_IE_1_SHIFT)) & SPDIF_EXT_IER1_B_PRE_MISMATCH_IE_1_MASK) + +#define SPDIF_EXT_IER1_UNEXP_PRE_REC_IE_1_MASK (0x100000U) +#define SPDIF_EXT_IER1_UNEXP_PRE_REC_IE_1_SHIFT (20U) +/*! UNEXP_PRE_REC_IE_1 - Interrupt enable for Unexpected preamble received. */ +#define SPDIF_EXT_IER1_UNEXP_PRE_REC_IE_1(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_EXT_IER1_UNEXP_PRE_REC_IE_1_SHIFT)) & SPDIF_EXT_IER1_UNEXP_PRE_REC_IE_1_MASK) + +#define SPDIF_EXT_IER1_CS_UD_OFLOW_IE_1_MASK (0x400000U) +#define SPDIF_EXT_IER1_CS_UD_OFLOW_IE_1_SHIFT (22U) +/*! CS_UD_OFLOW_IE_1 - Channel status or used data could not be stored. */ +#define SPDIF_EXT_IER1_CS_UD_OFLOW_IE_1(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_EXT_IER1_CS_UD_OFLOW_IE_1_SHIFT)) & SPDIF_EXT_IER1_CS_UD_OFLOW_IE_1_MASK) + +#define SPDIF_EXT_IER1_NEW_BLK_RCVD_IE_1_MASK (0x800000U) +#define SPDIF_EXT_IER1_NEW_BLK_RCVD_IE_1_SHIFT (23U) +/*! NEW_BLK_RCVD_IE_1 - New block of data was received. */ +#define SPDIF_EXT_IER1_NEW_BLK_RCVD_IE_1(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_EXT_IER1_NEW_BLK_RCVD_IE_1_SHIFT)) & SPDIF_EXT_IER1_NEW_BLK_RCVD_IE_1_MASK) + +#define SPDIF_EXT_IER1_SPDIF_WAKEUP_IE_1_MASK (0x1000000U) +#define SPDIF_EXT_IER1_SPDIF_WAKEUP_IE_1_SHIFT (24U) +/*! SPDIF_WAKEUP_IE_1 - SPDIF Wakeup interrupt enable. */ +#define SPDIF_EXT_IER1_SPDIF_WAKEUP_IE_1(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_EXT_IER1_SPDIF_WAKEUP_IE_1_SHIFT)) & SPDIF_EXT_IER1_SPDIF_WAKEUP_IE_1_MASK) +/*! @} */ + +/*! @name EXT_ISR - External Interrupt Status register */ +/*! @{ */ + +#define SPDIF_EXT_ISR_RX_NEW_CH_STAT_MASK (0x1U) +#define SPDIF_EXT_ISR_RX_NEW_CH_STAT_SHIFT (0U) +/*! RX_NEW_CH_STAT - Received new channel status block */ +#define SPDIF_EXT_ISR_RX_NEW_CH_STAT(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_EXT_ISR_RX_NEW_CH_STAT_SHIFT)) & SPDIF_EXT_ISR_RX_NEW_CH_STAT_MASK) + +#define SPDIF_EXT_ISR_RX_USR_DATA_MASK (0x2U) +#define SPDIF_EXT_ISR_RX_USR_DATA_SHIFT (1U) +/*! RX_USR_DATA - Received User data Information */ +#define SPDIF_EXT_ISR_RX_USR_DATA(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_EXT_ISR_RX_USR_DATA_SHIFT)) & SPDIF_EXT_ISR_RX_USR_DATA_MASK) + +#define SPDIF_EXT_ISR_MUTE_DET_MASK (0x4U) +#define SPDIF_EXT_ISR_MUTE_DET_SHIFT (2U) +/*! MUTE_DET - Interrupt to indicate HW mute bit was detected. */ +#define SPDIF_EXT_ISR_MUTE_DET(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_EXT_ISR_MUTE_DET_SHIFT)) & SPDIF_EXT_ISR_MUTE_DET_MASK) + +#define SPDIF_EXT_ISR_PREAMBLE_MISMATCH_MASK (0x20U) +#define SPDIF_EXT_ISR_PREAMBLE_MISMATCH_SHIFT (5U) +/*! PREAMBLE_MISMATCH - Preamble mismatch interrupt */ +#define SPDIF_EXT_ISR_PREAMBLE_MISMATCH(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_EXT_ISR_PREAMBLE_MISMATCH_SHIFT)) & SPDIF_EXT_ISR_PREAMBLE_MISMATCH_MASK) + +#define SPDIF_EXT_ISR_FIFO_OFLOW_UFLOW_ERR_MASK (0x40U) +#define SPDIF_EXT_ISR_FIFO_OFLOW_UFLOW_ERR_SHIFT (6U) +/*! FIFO_OFLOW_UFLOW_ERR - Receive FIFO overflow error interrupt */ +#define SPDIF_EXT_ISR_FIFO_OFLOW_UFLOW_ERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_EXT_ISR_FIFO_OFLOW_UFLOW_ERR_SHIFT)) & SPDIF_EXT_ISR_FIFO_OFLOW_UFLOW_ERR_MASK) + +#define SPDIF_EXT_ISR_RX_NO_DATA_REC_MASK (0x200U) +#define SPDIF_EXT_ISR_RX_NO_DATA_REC_SHIFT (9U) +/*! RX_NO_DATA_REC - No data is received for 1us. */ +#define SPDIF_EXT_ISR_RX_NO_DATA_REC(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_EXT_ISR_RX_NO_DATA_REC_SHIFT)) & SPDIF_EXT_ISR_RX_NO_DATA_REC_MASK) + +#define SPDIF_EXT_ISR_DMA_RD_REQ_MASK (0x4000U) +#define SPDIF_EXT_ISR_DMA_RD_REQ_SHIFT (14U) +/*! DMA_RD_REQ - Set when DMA read request is asserted. */ +#define SPDIF_EXT_ISR_DMA_RD_REQ(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_EXT_ISR_DMA_RD_REQ_SHIFT)) & SPDIF_EXT_ISR_DMA_RD_REQ_MASK) + +#define SPDIF_EXT_ISR_DMA_WR_REQ_MASK (0x8000U) +#define SPDIF_EXT_ISR_DMA_WR_REQ_SHIFT (15U) +/*! DMA_WR_REQ - Set when DMA write request is asserted. */ +#define SPDIF_EXT_ISR_DMA_WR_REQ(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_EXT_ISR_DMA_WR_REQ_SHIFT)) & SPDIF_EXT_ISR_DMA_WR_REQ_MASK) + +#define SPDIF_EXT_ISR_RX_BME_BIT_ERR_MASK (0x10000U) +#define SPDIF_EXT_ISR_RX_BME_BIT_ERR_SHIFT (16U) +/*! RX_BME_BIT_ERR - Set when RX BME data has an error. */ +#define SPDIF_EXT_ISR_RX_BME_BIT_ERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_EXT_ISR_RX_BME_BIT_ERR_SHIFT)) & SPDIF_EXT_ISR_RX_BME_BIT_ERR_MASK) + +#define SPDIF_EXT_ISR_PREAMBLE_MATCH_INT_MASK (0x20000U) +#define SPDIF_EXT_ISR_PREAMBLE_MATCH_INT_SHIFT (17U) +/*! PREAMBLE_MATCH_INT - Interrupt to indicate PA PB / DTC CD preamble match was detected. */ +#define SPDIF_EXT_ISR_PREAMBLE_MATCH_INT(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_EXT_ISR_PREAMBLE_MATCH_INT_SHIFT)) & SPDIF_EXT_ISR_PREAMBLE_MATCH_INT_MASK) + +#define SPDIF_EXT_ISR_M_W_PRE_MISMATCH_MASK (0x40000U) +#define SPDIF_EXT_ISR_M_W_PRE_MISMATCH_SHIFT (18U) +/*! M_W_PRE_MISMATCH - Set when SPDIF preamble of M/W has an error. */ +#define SPDIF_EXT_ISR_M_W_PRE_MISMATCH(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_EXT_ISR_M_W_PRE_MISMATCH_SHIFT)) & SPDIF_EXT_ISR_M_W_PRE_MISMATCH_MASK) + +#define SPDIF_EXT_ISR_B_PRE_MISMATCH_MASK (0x80000U) +#define SPDIF_EXT_ISR_B_PRE_MISMATCH_SHIFT (19U) +/*! B_PRE_MISMATCH - Set when SPDIF B preamble has an error. */ +#define SPDIF_EXT_ISR_B_PRE_MISMATCH(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_EXT_ISR_B_PRE_MISMATCH_SHIFT)) & SPDIF_EXT_ISR_B_PRE_MISMATCH_MASK) + +#define SPDIF_EXT_ISR_UNEXP_PRE_REC_MASK (0x100000U) +#define SPDIF_EXT_ISR_UNEXP_PRE_REC_SHIFT (20U) +/*! UNEXP_PRE_REC - Set when SPDIF preamble was received after unexpected number of input bits. */ +#define SPDIF_EXT_ISR_UNEXP_PRE_REC(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_EXT_ISR_UNEXP_PRE_REC_SHIFT)) & SPDIF_EXT_ISR_UNEXP_PRE_REC_MASK) + +#define SPDIF_EXT_ISR_CS_OR_UD_OFLOW_MASK (0x400000U) +#define SPDIF_EXT_ISR_CS_OR_UD_OFLOW_SHIFT (22U) +/*! CS_OR_UD_OFLOW - Channel status or used data could not be stored. */ +#define SPDIF_EXT_ISR_CS_OR_UD_OFLOW(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_EXT_ISR_CS_OR_UD_OFLOW_SHIFT)) & SPDIF_EXT_ISR_CS_OR_UD_OFLOW_MASK) + +#define SPDIF_EXT_ISR_NEW_BLK_RCVD_MASK (0x800000U) +#define SPDIF_EXT_ISR_NEW_BLK_RCVD_SHIFT (23U) +/*! NEW_BLK_RCVD - New block of data was received. */ +#define SPDIF_EXT_ISR_NEW_BLK_RCVD(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_EXT_ISR_NEW_BLK_RCVD_SHIFT)) & SPDIF_EXT_ISR_NEW_BLK_RCVD_MASK) + +#define SPDIF_EXT_ISR_SPDIF_WAKEUP_REC_MASK (0x1000000U) +#define SPDIF_EXT_ISR_SPDIF_WAKEUP_REC_SHIFT (24U) +/*! SPDIF_WAKEUP_REC - SPDIF Wakeup received. */ +#define SPDIF_EXT_ISR_SPDIF_WAKEUP_REC(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_EXT_ISR_SPDIF_WAKEUP_REC_SHIFT)) & SPDIF_EXT_ISR_SPDIF_WAKEUP_REC_MASK) +/*! @} */ + +/*! @name DPATH_STATUS - Audio XCVR datapath status */ +/*! @{ */ + +#define SPDIF_DPATH_STATUS_RX_FRM_CNT_MASK (0xFFU) +#define SPDIF_DPATH_STATUS_RX_FRM_CNT_SHIFT (0U) +/*! RX_FRM_CNT - Count of received frames in a block */ +#define SPDIF_DPATH_STATUS_RX_FRM_CNT(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_DPATH_STATUS_RX_FRM_CNT_SHIFT)) & SPDIF_DPATH_STATUS_RX_FRM_CNT_MASK) + +#define SPDIF_DPATH_STATUS_TX_FRM_CNT_MASK (0xFF00U) +#define SPDIF_DPATH_STATUS_TX_FRM_CNT_SHIFT (8U) +/*! TX_FRM_CNT - Count of transmitted frames in a block */ +#define SPDIF_DPATH_STATUS_TX_FRM_CNT(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_DPATH_STATUS_TX_FRM_CNT_SHIFT)) & SPDIF_DPATH_STATUS_TX_FRM_CNT_MASK) +/*! @} */ + +/*! @name CLK_CTRL - Clock control register */ +/*! @{ */ + +#define SPDIF_CLK_CTRL_CLKDIV_MASK (0x3FFU) +#define SPDIF_CLK_CTRL_CLKDIV_SHIFT (0U) +/*! CLKDIV - Clock divider value */ +#define SPDIF_CLK_CTRL_CLKDIV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_CLK_CTRL_CLKDIV_SHIFT)) & SPDIF_CLK_CTRL_CLKDIV_MASK) +/*! @} */ + +/*! @name RX_DATAPATH_CTRL - Data path control register */ +/*! @{ */ + +#define SPDIF_RX_DATAPATH_CTRL_PAPB_FIFO_STATUS_MASK (0x1U) +#define SPDIF_RX_DATAPATH_CTRL_PAPB_FIFO_STATUS_SHIFT (0U) +#define SPDIF_RX_DATAPATH_CTRL_PAPB_FIFO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_RX_DATAPATH_CTRL_PAPB_FIFO_STATUS_SHIFT)) & SPDIF_RX_DATAPATH_CTRL_PAPB_FIFO_STATUS_MASK) + +#define SPDIF_RX_DATAPATH_CTRL_RST_PKT_CNT_FIFO_MASK (0x20U) +#define SPDIF_RX_DATAPATH_CTRL_RST_PKT_CNT_FIFO_SHIFT (5U) +/*! RST_PKT_CNT_FIFO - Resets the packet count fifo. */ +#define SPDIF_RX_DATAPATH_CTRL_RST_PKT_CNT_FIFO(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_RX_DATAPATH_CTRL_RST_PKT_CNT_FIFO_SHIFT)) & SPDIF_RX_DATAPATH_CTRL_RST_PKT_CNT_FIFO_MASK) + +#define SPDIF_RX_DATAPATH_CTRL_STORE_FMT_MASK (0x40U) +#define SPDIF_RX_DATAPATH_CTRL_STORE_FMT_SHIFT (6U) +/*! STORE_FMT - Receive Data store format. */ +#define SPDIF_RX_DATAPATH_CTRL_STORE_FMT(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_RX_DATAPATH_CTRL_STORE_FMT_SHIFT)) & SPDIF_RX_DATAPATH_CTRL_STORE_FMT_MASK) + +#define SPDIF_RX_DATAPATH_CTRL_EN_PARITY_CALC_MASK (0x80U) +#define SPDIF_RX_DATAPATH_CTRL_EN_PARITY_CALC_SHIFT (7U) +/*! EN_PARITY_CALC - Enable Parity calculation. */ +#define SPDIF_RX_DATAPATH_CTRL_EN_PARITY_CALC(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_RX_DATAPATH_CTRL_EN_PARITY_CALC_SHIFT)) & SPDIF_RX_DATAPATH_CTRL_EN_PARITY_CALC_MASK) + +#define SPDIF_RX_DATAPATH_CTRL_UDR_MASK (0x100U) +#define SPDIF_RX_DATAPATH_CTRL_UDR_SHIFT (8U) +/*! UDR - User data reset */ +#define SPDIF_RX_DATAPATH_CTRL_UDR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_RX_DATAPATH_CTRL_UDR_SHIFT)) & SPDIF_RX_DATAPATH_CTRL_UDR_MASK) + +#define SPDIF_RX_DATAPATH_CTRL_CSR_MASK (0x200U) +#define SPDIF_RX_DATAPATH_CTRL_CSR_SHIFT (9U) +/*! CSR - Channel Status reset */ +#define SPDIF_RX_DATAPATH_CTRL_CSR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_RX_DATAPATH_CTRL_CSR_SHIFT)) & SPDIF_RX_DATAPATH_CTRL_CSR_MASK) + +#define SPDIF_RX_DATAPATH_CTRL_UDA_MASK (0x400U) +#define SPDIF_RX_DATAPATH_CTRL_UDA_SHIFT (10U) +/*! UDA - User Data Acknowledge */ +#define SPDIF_RX_DATAPATH_CTRL_UDA(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_RX_DATAPATH_CTRL_UDA_SHIFT)) & SPDIF_RX_DATAPATH_CTRL_UDA_MASK) + +#define SPDIF_RX_DATAPATH_CTRL_CSA_MASK (0x800U) +#define SPDIF_RX_DATAPATH_CTRL_CSA_SHIFT (11U) +/*! CSA - Channel Status Acknowledge */ +#define SPDIF_RX_DATAPATH_CTRL_CSA(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_RX_DATAPATH_CTRL_CSA_SHIFT)) & SPDIF_RX_DATAPATH_CTRL_CSA_MASK) + +#define SPDIF_RX_DATAPATH_CTRL_CLR_RX_FIFO_MASK (0x1000U) +#define SPDIF_RX_DATAPATH_CTRL_CLR_RX_FIFO_SHIFT (12U) +/*! CLR_RX_FIFO - Clear Receive FIFO */ +#define SPDIF_RX_DATAPATH_CTRL_CLR_RX_FIFO(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_RX_DATAPATH_CTRL_CLR_RX_FIFO_SHIFT)) & SPDIF_RX_DATAPATH_CTRL_CLR_RX_FIFO_MASK) + +#define SPDIF_RX_DATAPATH_CTRL_RX_DATA_FMT_MASK (0xC000U) +#define SPDIF_RX_DATAPATH_CTRL_RX_DATA_FMT_SHIFT (14U) +/*! RX_DATA_FMT - Indicates format of data stored in memory. */ +#define SPDIF_RX_DATAPATH_CTRL_RX_DATA_FMT(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_RX_DATAPATH_CTRL_RX_DATA_FMT_SHIFT)) & SPDIF_RX_DATAPATH_CTRL_RX_DATA_FMT_MASK) + +#define SPDIF_RX_DATAPATH_CTRL_SPDIF_TGL_CNT_MASK (0x70000U) +#define SPDIF_RX_DATAPATH_CTRL_SPDIF_TGL_CNT_SHIFT (16U) +/*! SPDIF_TGL_CNT - SPDIF wakeup source toggle count. */ +#define SPDIF_RX_DATAPATH_CTRL_SPDIF_TGL_CNT(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_RX_DATAPATH_CTRL_SPDIF_TGL_CNT_SHIFT)) & SPDIF_RX_DATAPATH_CTRL_SPDIF_TGL_CNT_MASK) + +#define SPDIF_RX_DATAPATH_CTRL_PABS_MASK (0x80000U) +#define SPDIF_RX_DATAPATH_CTRL_PABS_SHIFT (19U) +/*! PABS - Enable preamble search */ +#define SPDIF_RX_DATAPATH_CTRL_PABS(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_RX_DATAPATH_CTRL_PABS_SHIFT)) & SPDIF_RX_DATAPATH_CTRL_PABS_MASK) + +#define SPDIF_RX_DATAPATH_CTRL_DTS_CDS_MASK (0x100000U) +#define SPDIF_RX_DATAPATH_CTRL_DTS_CDS_SHIFT (20U) +/*! DTS_CDS - Enable DTS CD 14 preamble search */ +#define SPDIF_RX_DATAPATH_CTRL_DTS_CDS(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_RX_DATAPATH_CTRL_DTS_CDS_SHIFT)) & SPDIF_RX_DATAPATH_CTRL_DTS_CDS_MASK) + +#define SPDIF_RX_DATAPATH_CTRL_MUTE_CTRL_MASK (0x400000U) +#define SPDIF_RX_DATAPATH_CTRL_MUTE_CTRL_SHIFT (22U) +/*! MUTE_CTRL - M0+ mute request */ +#define SPDIF_RX_DATAPATH_CTRL_MUTE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_RX_DATAPATH_CTRL_MUTE_CTRL_SHIFT)) & SPDIF_RX_DATAPATH_CTRL_MUTE_CTRL_MASK) + +#define SPDIF_RX_DATAPATH_CTRL_MUTE_MODE_MASK (0x800000U) +#define SPDIF_RX_DATAPATH_CTRL_MUTE_MODE_SHIFT (23U) +/*! MUTE_MODE - Mute mode control */ +#define SPDIF_RX_DATAPATH_CTRL_MUTE_MODE(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_RX_DATAPATH_CTRL_MUTE_MODE_SHIFT)) & SPDIF_RX_DATAPATH_CTRL_MUTE_MODE_MASK) + +#define SPDIF_RX_DATAPATH_CTRL_FSM_MASK (0xC0000000U) +#define SPDIF_RX_DATAPATH_CTRL_FSM_SHIFT (30U) +/*! FSM - IEC60958-1 Frame Synchronization Mode */ +#define SPDIF_RX_DATAPATH_CTRL_FSM(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_RX_DATAPATH_CTRL_FSM_SHIFT)) & SPDIF_RX_DATAPATH_CTRL_FSM_MASK) +/*! @} */ + +/*! @name RX_CS_DATA_BITS - Channel staus bits */ +/*! @{ */ + +#define SPDIF_RX_CS_DATA_BITS_CS_DATA_MASK (0xFFFFFFFFU) +#define SPDIF_RX_CS_DATA_BITS_CS_DATA_SHIFT (0U) +/*! CS_DATA - Channel Status bits */ +#define SPDIF_RX_CS_DATA_BITS_CS_DATA(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_RX_CS_DATA_BITS_CS_DATA_SHIFT)) & SPDIF_RX_CS_DATA_BITS_CS_DATA_MASK) +/*! @} */ + +/* The count of SPDIF_RX_CS_DATA_BITS */ +#define SPDIF_RX_CS_DATA_BITS_COUNT (6U) + +/*! @name RX_USER_DATA_BITS - User data bits */ +/*! @{ */ + +#define SPDIF_RX_USER_DATA_BITS_U_DATA_MASK (0xFFFFFFFFU) +#define SPDIF_RX_USER_DATA_BITS_U_DATA_SHIFT (0U) +/*! U_DATA - User data bits */ +#define SPDIF_RX_USER_DATA_BITS_U_DATA(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_RX_USER_DATA_BITS_U_DATA_SHIFT)) & SPDIF_RX_USER_DATA_BITS_U_DATA_MASK) +/*! @} */ + +/* The count of SPDIF_RX_USER_DATA_BITS */ +#define SPDIF_RX_USER_DATA_BITS_COUNT (6U) + +/*! @name RX_DPATH_CNTR_CTRL - Receive Datapath counter control register */ +/*! @{ */ + +#define SPDIF_RX_DPATH_CNTR_CTRL_TS_EN_MASK (0x1U) +#define SPDIF_RX_DPATH_CNTR_CTRL_TS_EN_SHIFT (0U) +/*! TS_EN - Timestamp counter enable */ +#define SPDIF_RX_DPATH_CNTR_CTRL_TS_EN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_RX_DPATH_CNTR_CTRL_TS_EN_SHIFT)) & SPDIF_RX_DPATH_CNTR_CTRL_TS_EN_MASK) + +#define SPDIF_RX_DPATH_CNTR_CTRL_TS_INC_MASK (0x2U) +#define SPDIF_RX_DPATH_CNTR_CTRL_TS_INC_SHIFT (1U) +/*! TS_INC - Timestamp Increment */ +#define SPDIF_RX_DPATH_CNTR_CTRL_TS_INC(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_RX_DPATH_CNTR_CTRL_TS_INC_SHIFT)) & SPDIF_RX_DPATH_CNTR_CTRL_TS_INC_MASK) + +#define SPDIF_RX_DPATH_CNTR_CTRL_RST_BIT_CNTR_MASK (0x100U) +#define SPDIF_RX_DPATH_CNTR_CTRL_RST_BIT_CNTR_SHIFT (8U) +/*! RST_BIT_CNTR - Reset bit counter. */ +#define SPDIF_RX_DPATH_CNTR_CTRL_RST_BIT_CNTR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_RX_DPATH_CNTR_CTRL_RST_BIT_CNTR_SHIFT)) & SPDIF_RX_DPATH_CNTR_CTRL_RST_BIT_CNTR_MASK) + +#define SPDIF_RX_DPATH_CNTR_CTRL_RST_TS_CNTR_MASK (0x200U) +#define SPDIF_RX_DPATH_CNTR_CTRL_RST_TS_CNTR_SHIFT (9U) +/*! RST_TS_CNTR - Reset timestamp counter. */ +#define SPDIF_RX_DPATH_CNTR_CTRL_RST_TS_CNTR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_RX_DPATH_CNTR_CTRL_RST_TS_CNTR_SHIFT)) & SPDIF_RX_DPATH_CNTR_CTRL_RST_TS_CNTR_MASK) +/*! @} */ + +/*! @name RX_DPATH_TSCR - Receive Datapath Timestamp Counter Register */ +/*! @{ */ + +#define SPDIF_RX_DPATH_TSCR_CVAL_MASK (0xFFFFFFFFU) +#define SPDIF_RX_DPATH_TSCR_CVAL_SHIFT (0U) +/*! CVAL - Timestamp counter value */ +#define SPDIF_RX_DPATH_TSCR_CVAL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_RX_DPATH_TSCR_CVAL_SHIFT)) & SPDIF_RX_DPATH_TSCR_CVAL_MASK) +/*! @} */ + +/*! @name RX_DPATH_BCR - Receive Datapath Bit counter register */ +/*! @{ */ + +#define SPDIF_RX_DPATH_BCR_CVAL_MASK (0xFFFFFFFFU) +#define SPDIF_RX_DPATH_BCR_CVAL_SHIFT (0U) +/*! CVAL - Bit count value */ +#define SPDIF_RX_DPATH_BCR_CVAL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_RX_DPATH_BCR_CVAL_SHIFT)) & SPDIF_RX_DPATH_BCR_CVAL_MASK) +/*! @} */ + +/*! @name RX_DPATH_BCTR - Receive datapath Bit count timestamp register. */ +/*! @{ */ + +#define SPDIF_RX_DPATH_BCTR_BCT_VAL_MASK (0xFFFFFFFFU) +#define SPDIF_RX_DPATH_BCTR_BCT_VAL_SHIFT (0U) +/*! BCT_VAL - Bit count timestamp value */ +#define SPDIF_RX_DPATH_BCTR_BCT_VAL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_RX_DPATH_BCTR_BCT_VAL_SHIFT)) & SPDIF_RX_DPATH_BCTR_BCT_VAL_MASK) +/*! @} */ + +/*! @name RX_DPATH_BCRR - Receive datapath Bit read timestamp register. */ +/*! @{ */ + +#define SPDIF_RX_DPATH_BCRR_BCT_VAL_MASK (0xFFFFFFFFU) +#define SPDIF_RX_DPATH_BCRR_BCT_VAL_SHIFT (0U) +/*! BCT_VAL - Bit count timestamp value */ +#define SPDIF_RX_DPATH_BCRR_BCT_VAL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_RX_DPATH_BCRR_BCT_VAL_SHIFT)) & SPDIF_RX_DPATH_BCRR_BCT_VAL_MASK) +/*! @} */ + +/*! @name PRE_MATCH_VAL - Preamble match value register */ +/*! @{ */ + +#define SPDIF_PRE_MATCH_VAL_PB_VAL_MASK (0xFFFFU) +#define SPDIF_PRE_MATCH_VAL_PB_VAL_SHIFT (0U) +/*! PB_VAL - Preamble PB value */ +#define SPDIF_PRE_MATCH_VAL_PB_VAL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_PRE_MATCH_VAL_PB_VAL_SHIFT)) & SPDIF_PRE_MATCH_VAL_PB_VAL_MASK) + +#define SPDIF_PRE_MATCH_VAL_PA_VAL_MASK (0xFFFF0000U) +#define SPDIF_PRE_MATCH_VAL_PA_VAL_SHIFT (16U) +/*! PA_VAL - Preamble PA value */ +#define SPDIF_PRE_MATCH_VAL_PA_VAL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_PRE_MATCH_VAL_PA_VAL_SHIFT)) & SPDIF_PRE_MATCH_VAL_PA_VAL_MASK) +/*! @} */ + +/*! @name DTS_PRE_MATCH_VAL - Preamble match value register */ +/*! @{ */ + +#define SPDIF_DTS_PRE_MATCH_VAL_DTS_PB_VAL_MASK (0xFFFFU) +#define SPDIF_DTS_PRE_MATCH_VAL_DTS_PB_VAL_SHIFT (0U) +/*! DTS_PB_VAL - Preamble value */ +#define SPDIF_DTS_PRE_MATCH_VAL_DTS_PB_VAL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_DTS_PRE_MATCH_VAL_DTS_PB_VAL_SHIFT)) & SPDIF_DTS_PRE_MATCH_VAL_DTS_PB_VAL_MASK) + +#define SPDIF_DTS_PRE_MATCH_VAL_DTS_PA_VAL_MASK (0xFFFF0000U) +#define SPDIF_DTS_PRE_MATCH_VAL_DTS_PA_VAL_SHIFT (16U) +/*! DTS_PA_VAL - Preamble value */ +#define SPDIF_DTS_PRE_MATCH_VAL_DTS_PA_VAL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_DTS_PRE_MATCH_VAL_DTS_PA_VAL_SHIFT)) & SPDIF_DTS_PRE_MATCH_VAL_DTS_PA_VAL_MASK) +/*! @} */ + +/*! @name RX_DPATH_PRE_ERR - Error count for IEC60958-1 Block Synchronization. */ +/*! @{ */ + +#define SPDIF_RX_DPATH_PRE_ERR_PRE_ERRS_MASK (0xFFFFU) +#define SPDIF_RX_DPATH_PRE_ERR_PRE_ERRS_SHIFT (0U) +/*! PRE_ERRS - Preamble Error counter */ +#define SPDIF_RX_DPATH_PRE_ERR_PRE_ERRS(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_RX_DPATH_PRE_ERR_PRE_ERRS_SHIFT)) & SPDIF_RX_DPATH_PRE_ERR_PRE_ERRS_MASK) + +#define SPDIF_RX_DPATH_PRE_ERR_CLEAR_MASK (0x80000000U) +#define SPDIF_RX_DPATH_PRE_ERR_CLEAR_SHIFT (31U) +/*! CLEAR - Clear bit for error counter. */ +#define SPDIF_RX_DPATH_PRE_ERR_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_RX_DPATH_PRE_ERR_CLEAR_SHIFT)) & SPDIF_RX_DPATH_PRE_ERR_CLEAR_MASK) +/*! @} */ + +/*! @name RX_DPATH_PARITY_ERR - Parity Error count for IEC60958-1 Blocks. */ +/*! @{ */ + +#define SPDIF_RX_DPATH_PARITY_ERR_PRE_ERRS_MASK (0xFFFFU) +#define SPDIF_RX_DPATH_PARITY_ERR_PRE_ERRS_SHIFT (0U) +/*! PRE_ERRS - Parity Error counter */ +#define SPDIF_RX_DPATH_PARITY_ERR_PRE_ERRS(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_RX_DPATH_PARITY_ERR_PRE_ERRS_SHIFT)) & SPDIF_RX_DPATH_PARITY_ERR_PRE_ERRS_MASK) + +#define SPDIF_RX_DPATH_PARITY_ERR_CLEAR_MASK (0x80000000U) +#define SPDIF_RX_DPATH_PARITY_ERR_CLEAR_SHIFT (31U) +/*! CLEAR - Clear bit for error counter. */ +#define SPDIF_RX_DPATH_PARITY_ERR_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_RX_DPATH_PARITY_ERR_CLEAR_SHIFT)) & SPDIF_RX_DPATH_PARITY_ERR_CLEAR_MASK) +/*! @} */ + +/*! @name RX_DPATH_PKT_CNT - Receive Data packet count. */ +/*! @{ */ + +#define SPDIF_RX_DPATH_PKT_CNT_VAL_MASK (0x7FFFFFFFU) +#define SPDIF_RX_DPATH_PKT_CNT_VAL_SHIFT (0U) +/*! VAL - Data packet counter */ +#define SPDIF_RX_DPATH_PKT_CNT_VAL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_RX_DPATH_PKT_CNT_VAL_SHIFT)) & SPDIF_RX_DPATH_PKT_CNT_VAL_MASK) +/*! @} */ + +/*! @name PRE_MATCH_OFFSET - Preamble match offset value register */ +/*! @{ */ + +#define SPDIF_PRE_MATCH_OFFSET_PA_OFFSET_MASK (0xFFFFFFFFU) +#define SPDIF_PRE_MATCH_OFFSET_PA_OFFSET_SHIFT (0U) +/*! PA_OFFSET - Sample count value for PA offset match */ +#define SPDIF_PRE_MATCH_OFFSET_PA_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_PRE_MATCH_OFFSET_PA_OFFSET_SHIFT)) & SPDIF_PRE_MATCH_OFFSET_PA_OFFSET_MASK) +/*! @} */ + +/*! @name TX_DATAPATH_CTRL - Transmit Data path control register */ +/*! @{ */ + +#define SPDIF_TX_DATAPATH_CTRL_CS_ACK_MASK (0x1U) +#define SPDIF_TX_DATAPATH_CTRL_CS_ACK_SHIFT (0U) +/*! CS_ACK - Channel Status ACK */ +#define SPDIF_TX_DATAPATH_CTRL_CS_ACK(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_TX_DATAPATH_CTRL_CS_ACK_SHIFT)) & SPDIF_TX_DATAPATH_CTRL_CS_ACK_MASK) + +#define SPDIF_TX_DATAPATH_CTRL_UD_ACK_MASK (0x2U) +#define SPDIF_TX_DATAPATH_CTRL_UD_ACK_SHIFT (1U) +/*! UD_ACK - User Data ACK */ +#define SPDIF_TX_DATAPATH_CTRL_UD_ACK(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_TX_DATAPATH_CTRL_UD_ACK_SHIFT)) & SPDIF_TX_DATAPATH_CTRL_UD_ACK_MASK) + +#define SPDIF_TX_DATAPATH_CTRL_CS_MOD_MASK (0x4U) +#define SPDIF_TX_DATAPATH_CTRL_CS_MOD_SHIFT (2U) +/*! CS_MOD - Enable Channel Status insertion */ +#define SPDIF_TX_DATAPATH_CTRL_CS_MOD(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_TX_DATAPATH_CTRL_CS_MOD_SHIFT)) & SPDIF_TX_DATAPATH_CTRL_CS_MOD_MASK) + +#define SPDIF_TX_DATAPATH_CTRL_UD_MOD_MASK (0x8U) +#define SPDIF_TX_DATAPATH_CTRL_UD_MOD_SHIFT (3U) +/*! UD_MOD - Enable User Data insertion */ +#define SPDIF_TX_DATAPATH_CTRL_UD_MOD(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_TX_DATAPATH_CTRL_UD_MOD_SHIFT)) & SPDIF_TX_DATAPATH_CTRL_UD_MOD_MASK) + +#define SPDIF_TX_DATAPATH_CTRL_VLD_MOD_MASK (0x10U) +#define SPDIF_TX_DATAPATH_CTRL_VLD_MOD_SHIFT (4U) +/*! VLD_MOD - Enable Valid bit insertion */ +#define SPDIF_TX_DATAPATH_CTRL_VLD_MOD(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_TX_DATAPATH_CTRL_VLD_MOD_SHIFT)) & SPDIF_TX_DATAPATH_CTRL_VLD_MOD_MASK) + +#define SPDIF_TX_DATAPATH_CTRL_FRM_VLD_MASK (0x20U) +#define SPDIF_TX_DATAPATH_CTRL_FRM_VLD_SHIFT (5U) +/*! FRM_VLD - Valid bit value */ +#define SPDIF_TX_DATAPATH_CTRL_FRM_VLD(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_TX_DATAPATH_CTRL_FRM_VLD_SHIFT)) & SPDIF_TX_DATAPATH_CTRL_FRM_VLD_MASK) + +#define SPDIF_TX_DATAPATH_CTRL_EN_PARITY_MASK (0x40U) +#define SPDIF_TX_DATAPATH_CTRL_EN_PARITY_SHIFT (6U) +/*! EN_PARITY - Enable parity insertion */ +#define SPDIF_TX_DATAPATH_CTRL_EN_PARITY(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_TX_DATAPATH_CTRL_EN_PARITY_SHIFT)) & SPDIF_TX_DATAPATH_CTRL_EN_PARITY_MASK) + +#define SPDIF_TX_DATAPATH_CTRL_EN_PREAMBLE_MASK (0x80U) +#define SPDIF_TX_DATAPATH_CTRL_EN_PREAMBLE_SHIFT (7U) +/*! EN_PREAMBLE - Enable preamble insertion */ +#define SPDIF_TX_DATAPATH_CTRL_EN_PREAMBLE(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_TX_DATAPATH_CTRL_EN_PREAMBLE_SHIFT)) & SPDIF_TX_DATAPATH_CTRL_EN_PREAMBLE_MASK) + +#define SPDIF_TX_DATAPATH_CTRL_FRM_FMT_MASK (0x800U) +#define SPDIF_TX_DATAPATH_CTRL_FRM_FMT_SHIFT (11U) +/*! FRM_FMT - Frame format of input data */ +#define SPDIF_TX_DATAPATH_CTRL_FRM_FMT(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_TX_DATAPATH_CTRL_FRM_FMT_SHIFT)) & SPDIF_TX_DATAPATH_CTRL_FRM_FMT_MASK) + +#define SPDIF_TX_DATAPATH_CTRL_TX_FORMAT_MASK (0x3000U) +#define SPDIF_TX_DATAPATH_CTRL_TX_FORMAT_SHIFT (12U) +/*! TX_FORMAT - Transmit data format */ +#define SPDIF_TX_DATAPATH_CTRL_TX_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_TX_DATAPATH_CTRL_TX_FORMAT_SHIFT)) & SPDIF_TX_DATAPATH_CTRL_TX_FORMAT_MASK) + +#define SPDIF_TX_DATAPATH_CTRL_STRT_DATA_TX_MASK (0x4000U) +#define SPDIF_TX_DATAPATH_CTRL_STRT_DATA_TX_SHIFT (14U) +/*! STRT_DATA_TX - Start transmit of data. */ +#define SPDIF_TX_DATAPATH_CTRL_STRT_DATA_TX(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_TX_DATAPATH_CTRL_STRT_DATA_TX_SHIFT)) & SPDIF_TX_DATAPATH_CTRL_STRT_DATA_TX_MASK) +/*! @} */ + +/*! @name TX_CS_DATA_BITS - Channel staus bits */ +/*! @{ */ + +#define SPDIF_TX_CS_DATA_BITS_CS_DATA_MASK (0xFFFFFFFFU) +#define SPDIF_TX_CS_DATA_BITS_CS_DATA_SHIFT (0U) +/*! CS_DATA - Channel Status bits / block */ +#define SPDIF_TX_CS_DATA_BITS_CS_DATA(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_TX_CS_DATA_BITS_CS_DATA_SHIFT)) & SPDIF_TX_CS_DATA_BITS_CS_DATA_MASK) +/*! @} */ + +/* The count of SPDIF_TX_CS_DATA_BITS */ +#define SPDIF_TX_CS_DATA_BITS_COUNT (6U) + +/*! @name TX_USER_DATA_BITS - User data bits */ +/*! @{ */ + +#define SPDIF_TX_USER_DATA_BITS_U_DATA_MASK (0xFFFFFFFFU) +#define SPDIF_TX_USER_DATA_BITS_U_DATA_SHIFT (0U) +/*! U_DATA - User data bits/block */ +#define SPDIF_TX_USER_DATA_BITS_U_DATA(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_TX_USER_DATA_BITS_U_DATA_SHIFT)) & SPDIF_TX_USER_DATA_BITS_U_DATA_MASK) +/*! @} */ + +/* The count of SPDIF_TX_USER_DATA_BITS */ +#define SPDIF_TX_USER_DATA_BITS_COUNT (6U) + +/*! @name TX_DPATH_CNTR_CTRL - Transmit datapath counter control register */ +/*! @{ */ + +#define SPDIF_TX_DPATH_CNTR_CTRL_TS_EN_MASK (0x1U) +#define SPDIF_TX_DPATH_CNTR_CTRL_TS_EN_SHIFT (0U) +/*! TS_EN - Timestamp counter enable */ +#define SPDIF_TX_DPATH_CNTR_CTRL_TS_EN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_TX_DPATH_CNTR_CTRL_TS_EN_SHIFT)) & SPDIF_TX_DPATH_CNTR_CTRL_TS_EN_MASK) + +#define SPDIF_TX_DPATH_CNTR_CTRL_TS_INC_MASK (0x2U) +#define SPDIF_TX_DPATH_CNTR_CTRL_TS_INC_SHIFT (1U) +/*! TS_INC - Timestamp Increment */ +#define SPDIF_TX_DPATH_CNTR_CTRL_TS_INC(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_TX_DPATH_CNTR_CTRL_TS_INC_SHIFT)) & SPDIF_TX_DPATH_CNTR_CTRL_TS_INC_MASK) + +#define SPDIF_TX_DPATH_CNTR_CTRL_RST_BIT_CNTR_MASK (0x100U) +#define SPDIF_TX_DPATH_CNTR_CTRL_RST_BIT_CNTR_SHIFT (8U) +/*! RST_BIT_CNTR - Reset bit counter. */ +#define SPDIF_TX_DPATH_CNTR_CTRL_RST_BIT_CNTR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_TX_DPATH_CNTR_CTRL_RST_BIT_CNTR_SHIFT)) & SPDIF_TX_DPATH_CNTR_CTRL_RST_BIT_CNTR_MASK) + +#define SPDIF_TX_DPATH_CNTR_CTRL_RST_TS_CNTR_MASK (0x200U) +#define SPDIF_TX_DPATH_CNTR_CTRL_RST_TS_CNTR_SHIFT (9U) +/*! RST_TS_CNTR - Reset timestamp counter. */ +#define SPDIF_TX_DPATH_CNTR_CTRL_RST_TS_CNTR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_TX_DPATH_CNTR_CTRL_RST_TS_CNTR_SHIFT)) & SPDIF_TX_DPATH_CNTR_CTRL_RST_TS_CNTR_MASK) +/*! @} */ + +/*! @name TX_DPATH_TSCR - Transmit Datapath Timestamp Counter Register */ +/*! @{ */ + +#define SPDIF_TX_DPATH_TSCR_CVAL_MASK (0xFFFFFFFFU) +#define SPDIF_TX_DPATH_TSCR_CVAL_SHIFT (0U) +/*! CVAL - Timestamp counter value */ +#define SPDIF_TX_DPATH_TSCR_CVAL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_TX_DPATH_TSCR_CVAL_SHIFT)) & SPDIF_TX_DPATH_TSCR_CVAL_MASK) +/*! @} */ + +/*! @name TX_DPATH_BCR - Transmit Datapath Bit counter register */ +/*! @{ */ + +#define SPDIF_TX_DPATH_BCR_CVAL_MASK (0xFFFFFFFFU) +#define SPDIF_TX_DPATH_BCR_CVAL_SHIFT (0U) +/*! CVAL - Bit count value */ +#define SPDIF_TX_DPATH_BCR_CVAL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_TX_DPATH_BCR_CVAL_SHIFT)) & SPDIF_TX_DPATH_BCR_CVAL_MASK) +/*! @} */ + +/*! @name TX_DPATH_BCTR - Transmit datapath Bit count timestamp register. */ +/*! @{ */ + +#define SPDIF_TX_DPATH_BCTR_BCT_VAL_MASK (0xFFFFFFFFU) +#define SPDIF_TX_DPATH_BCTR_BCT_VAL_SHIFT (0U) +/*! BCT_VAL - Bit count timestamp value */ +#define SPDIF_TX_DPATH_BCTR_BCT_VAL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_TX_DPATH_BCTR_BCT_VAL_SHIFT)) & SPDIF_TX_DPATH_BCTR_BCT_VAL_MASK) +/*! @} */ + +/*! @name TX_DPATH_BCRR - Transmmit datapath Bit read timestamp register. */ +/*! @{ */ + +#define SPDIF_TX_DPATH_BCRR_BCT_VAL_MASK (0xFFFFFFFFU) +#define SPDIF_TX_DPATH_BCRR_BCT_VAL_SHIFT (0U) +/*! BCT_VAL - Bit count timestamp value */ +#define SPDIF_TX_DPATH_BCRR_BCT_VAL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_TX_DPATH_BCRR_BCT_VAL_SHIFT)) & SPDIF_TX_DPATH_BCRR_BCT_VAL_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group SPDIF_Register_Masks */ + + +/* SPDIF - Peripheral instance base addresses */ +/** Peripheral SPDIF base address */ +#define SPDIF_BASE (0x42680000u) +/** Peripheral SPDIF base pointer */ +#define SPDIF ((SPDIF_Type *)SPDIF_BASE) +/** Array initializer of SPDIF peripheral base addresses */ +#define SPDIF_BASE_ADDRS { SPDIF_BASE } +/** Array initializer of SPDIF peripheral base pointers */ +#define SPDIF_BASE_PTRS { SPDIF } + +/*! + * @} + */ /* end of group SPDIF_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- SRC_GENERAL_REG Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SRC_GENERAL_REG_Peripheral_Access_Layer SRC_GENERAL_REG Peripheral Access Layer + * @{ + */ + +/** SRC_GENERAL_REG - Register Layout Typedef */ +typedef struct { + uint8_t RESERVED_0[4]; + __IO uint32_t AUTHEN_CTRL; /**< Authentication Control, offset: 0x4 */ + uint8_t RESERVED_1[12]; + __IO uint32_t SRTMR; /**< SRC RESET TRIGGER MODE REGISTER, offset: 0x14 */ + __IO uint32_t SRMASK; /**< SRC RESET TRIGGER MODE REGISTER, offset: 0x18 */ + uint8_t RESERVED_2[4]; + __IO uint32_t SRMR1; /**< SRC RESET MODE REGISTER 1, offset: 0x20 */ + __IO uint32_t SRMR2; /**< SRC RESET MODE REGISTER 2, offset: 0x24 */ + __IO uint32_t SRMR3; /**< SRC RESET MODE REGISTER 3, offset: 0x28 */ + __IO uint32_t SRMR4; /**< SRC RESET MODE REGISTER 4, offset: 0x2C */ + uint8_t RESERVED_3[16]; + __I uint32_t SBMR1; /**< SRC Boot Mode Register 1, offset: 0x40 */ + __I uint32_t SBMR2; /**< SRC Boot Mode Register 2, offset: 0x44 */ + uint8_t RESERVED_4[8]; + __IO uint32_t SRSR; /**< SRC Reset Status Register, offset: 0x50 */ + __IO uint32_t GPR1; /**< SRC General Purpose Register 1, offset: 0x54 */ + __IO uint32_t GPR2; /**< SRC General Purpose Register 2, offset: 0x58 */ + __IO uint32_t GPR3; /**< SRC General Purpose Register 3, offset: 0x5C */ + __IO uint32_t GPR4; /**< SRC General Purpose Register 4, offset: 0x60 */ + __IO uint32_t GPR5; /**< SRC General Purpose Register 5, offset: 0x64 */ + __IO uint32_t GPR6; /**< SRC General Purpose Register 6, offset: 0x68 */ + __IO uint32_t GPR7; /**< SRC General Purpose Register 7, offset: 0x6C */ + __IO uint32_t GPR8; /**< SRC General Purpose Register 8, offset: 0x70 */ + __IO uint32_t GPR9; /**< SRC General Purpose Register 9, offset: 0x74 */ + __IO uint32_t GPR10; /**< SRC General Purpose Register 10, offset: 0x78 */ + __IO uint32_t GPR11; /**< SRC General Purpose Register 11, offset: 0x7C */ + __IO uint32_t GPR12; /**< SRC General Purpose Register 12, offset: 0x80 */ + __IO uint32_t GPR13; /**< SRC General Purpose Register 13, offset: 0x84 */ + __IO uint32_t GPR14; /**< SRC General Purpose Register 14, offset: 0x88 */ + __IO uint32_t GPR15; /**< SRC General Purpose Register 15, offset: 0x8C */ + __IO uint32_t GPR16; /**< SRC General Purpose Register 16, offset: 0x90 */ + __IO uint32_t GPR17; /**< SRC General Purpose Register 17, offset: 0x94 */ + __IO uint32_t GPR18; /**< SRC General Purpose Register 18, offset: 0x98 */ + __IO uint32_t GPR19; /**< SRC General Purpose Register 19, offset: 0x9C */ + uint8_t RESERVED_5[96]; + __IO uint32_t GPR20; /**< SRC General Purpose Register 20, offset: 0x100 */ + uint8_t RESERVED_6[4]; + __IO uint32_t COLD_RESET_SSAR_ACK_CTRL; /**< Cold reset SSAR acknowledge control, offset: 0x108 */ + __IO uint32_t SP_ISO_CTRL; /**< SRC special ISO Control, offset: 0x10C */ + __IO uint32_t ROM_LP_CTRL; /**< ROM Low Power Control, offset: 0x110 */ + __I uint32_t A55_DENY_STAT; /**< A55 Q_Channel Deny Status, offset: 0x114 */ +} SRC_GENERAL_REG_Type; + +/* ---------------------------------------------------------------------------- + -- SRC_GENERAL_REG Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SRC_GENERAL_REG_Register_Masks SRC_GENERAL_REG Register Masks + * @{ + */ + +/*! @name AUTHEN_CTRL - Authentication Control */ +/*! @{ */ + +#define SRC_GENERAL_REG_AUTHEN_CTRL_LOCK_CFG_MASK (0x80U) +#define SRC_GENERAL_REG_AUTHEN_CTRL_LOCK_CFG_SHIFT (7U) +/*! LOCK_CFG - Configuration lock + * 0b0..General registers are not locked. + * 0b1..LOCK_CFG and registers in the list are locked. + */ +#define SRC_GENERAL_REG_AUTHEN_CTRL_LOCK_CFG(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_AUTHEN_CTRL_LOCK_CFG_SHIFT)) & SRC_GENERAL_REG_AUTHEN_CTRL_LOCK_CFG_MASK) + +#define SRC_GENERAL_REG_AUTHEN_CTRL_TZ_USER_MASK (0x100U) +#define SRC_GENERAL_REG_AUTHEN_CTRL_TZ_USER_SHIFT (8U) +/*! TZ_USER - Allow user mode access + * 0b0..General registers can only be written in privilege mode. + * 0b1..General registers can be written either in privilege mode or user mode. + */ +#define SRC_GENERAL_REG_AUTHEN_CTRL_TZ_USER(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_AUTHEN_CTRL_TZ_USER_SHIFT)) & SRC_GENERAL_REG_AUTHEN_CTRL_TZ_USER_MASK) + +#define SRC_GENERAL_REG_AUTHEN_CTRL_TZ_NS_MASK (0x200U) +#define SRC_GENERAL_REG_AUTHEN_CTRL_TZ_NS_SHIFT (9U) +/*! TZ_NS - Allow non-secure mode access + * 0b0..General registers can only be written in secure mode. + * 0b1..General registers can be written either in secure mode or non-secure mode. + */ +#define SRC_GENERAL_REG_AUTHEN_CTRL_TZ_NS(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_AUTHEN_CTRL_TZ_NS_SHIFT)) & SRC_GENERAL_REG_AUTHEN_CTRL_TZ_NS_MASK) + +#define SRC_GENERAL_REG_AUTHEN_CTRL_LOCK_TZ_MASK (0x800U) +#define SRC_GENERAL_REG_AUTHEN_CTRL_LOCK_TZ_SHIFT (11U) +/*! LOCK_TZ - Lock TZ_NS and TZ_USER bits + * 0b0..TZ_NS and TZ_USER value can be changed. + * 0b1..LOCK_TZ, TZ_NS and TZ_USER value cannot be changed. + */ +#define SRC_GENERAL_REG_AUTHEN_CTRL_LOCK_TZ(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_AUTHEN_CTRL_LOCK_TZ_SHIFT)) & SRC_GENERAL_REG_AUTHEN_CTRL_LOCK_TZ_MASK) + +#define SRC_GENERAL_REG_AUTHEN_CTRL_LOCK_LIST_MASK (0x8000U) +#define SRC_GENERAL_REG_AUTHEN_CTRL_LOCK_LIST_SHIFT (15U) +/*! LOCK_LIST - White list lock + * 0b0..WHITE_LIST value can be changed. + * 0b1..LOCK_LIST and WHITE_LIST value cannot be changed. + */ +#define SRC_GENERAL_REG_AUTHEN_CTRL_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_AUTHEN_CTRL_LOCK_LIST_SHIFT)) & SRC_GENERAL_REG_AUTHEN_CTRL_LOCK_LIST_MASK) + +#define SRC_GENERAL_REG_AUTHEN_CTRL_WHITE_LIST_MASK (0xFFFF0000U) +#define SRC_GENERAL_REG_AUTHEN_CTRL_WHITE_LIST_SHIFT (16U) +/*! WHITE_LIST - Domain ID white list + * 0b0000000000000001..Core with domain ID=0 can write General registers. + * 0b0000000000000010..Core with domain ID=1 can write General registers. + * 0b0000000000000100..Core with domain ID=2 can write General registers. + * 0b0000000000001000..Core with domain ID=3 can write General registers. + * 0b0000000000010000..Core with domain ID=4 can write General registers. + * 0b0000000000100000..Core with domain ID=5 can write General registers. + * 0b0000000001000000..Core with domain ID=6 can write General registers. + * 0b0000000010000000..Core with domain ID=7 can write General registers. + * 0b0000000100000000..Core with domain ID=8 can write General registers. + * 0b0000001000000000..Core with domain ID=9 can write General registers. + * 0b0000010000000000..Core with domain ID=10 can write General registers. + * 0b0000100000000000..Core with domain ID=11 can write General registers. + * 0b0001000000000000..Core with domain ID=12 can write General registers. + * 0b0010000000000000..Core with domain ID=13 can write General registers. + * 0b0100000000000000..Core with domain ID=14 can write General registers. + * 0b1000000000000000..Core with domain ID=15 can write General registers. + */ +#define SRC_GENERAL_REG_AUTHEN_CTRL_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_AUTHEN_CTRL_WHITE_LIST_SHIFT)) & SRC_GENERAL_REG_AUTHEN_CTRL_WHITE_LIST_MASK) +/*! @} */ + +/*! @name SRTMR - SRC RESET TRIGGER MODE REGISTER */ +/*! @{ */ + +#define SRC_GENERAL_REG_SRTMR_WDOG1_TRIG_MODE_MASK (0x1U) +#define SRC_GENERAL_REG_SRTMR_WDOG1_TRIG_MODE_SHIFT (0U) +/*! WDOG1_TRIG_MODE - WDOG1 reset trigger mode configuration,locked by LOCK_CFG field + * 0b0..Level-sensitive: System stays in reset until the reset source deasserts. + * 0b1..Edge-sensitive: System resets once, even if the reset source remains asserted. + */ +#define SRC_GENERAL_REG_SRTMR_WDOG1_TRIG_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_SRTMR_WDOG1_TRIG_MODE_SHIFT)) & SRC_GENERAL_REG_SRTMR_WDOG1_TRIG_MODE_MASK) + +#define SRC_GENERAL_REG_SRTMR_WDOG2_TRIG_MODE_MASK (0x2U) +#define SRC_GENERAL_REG_SRTMR_WDOG2_TRIG_MODE_SHIFT (1U) +/*! WDOG2_TRIG_MODE - WDOG2 reset trigger mode configuration,locked by LOCK_CFG field + * 0b0..Level-sensitive: System stays in reset until the reset source deasserts. + * 0b1..Edge-sensitive: System resets once, even if the reset source remains asserted. + */ +#define SRC_GENERAL_REG_SRTMR_WDOG2_TRIG_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_SRTMR_WDOG2_TRIG_MODE_SHIFT)) & SRC_GENERAL_REG_SRTMR_WDOG2_TRIG_MODE_MASK) + +#define SRC_GENERAL_REG_SRTMR_WDOG3_TRIG_MODE_MASK (0x4U) +#define SRC_GENERAL_REG_SRTMR_WDOG3_TRIG_MODE_SHIFT (2U) +/*! WDOG3_TRIG_MODE - WDOG3 reset trigger mode configuration,locked by LOCK_CFG field + * 0b0..Level-sensitive: System stays in reset until the reset source deasserts. + * 0b1..Edge-sensitive: System resets once, even if the reset source remains asserted. + */ +#define SRC_GENERAL_REG_SRTMR_WDOG3_TRIG_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_SRTMR_WDOG3_TRIG_MODE_SHIFT)) & SRC_GENERAL_REG_SRTMR_WDOG3_TRIG_MODE_MASK) + +#define SRC_GENERAL_REG_SRTMR_WDOG4_TRIG_MODE_MASK (0x8U) +#define SRC_GENERAL_REG_SRTMR_WDOG4_TRIG_MODE_SHIFT (3U) +/*! WDOG4_TRIG_MODE - WDOG4 reset trigger mode configuration,locked by LOCK_CFG field + * 0b0..Level-sensitive: System stays in reset until the reset source deasserts. + * 0b1..Edge-sensitive: System resets once, even if the reset source remains asserted. + */ +#define SRC_GENERAL_REG_SRTMR_WDOG4_TRIG_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_SRTMR_WDOG4_TRIG_MODE_SHIFT)) & SRC_GENERAL_REG_SRTMR_WDOG4_TRIG_MODE_MASK) + +#define SRC_GENERAL_REG_SRTMR_WDOG5_TRIG_MODE_MASK (0x10U) +#define SRC_GENERAL_REG_SRTMR_WDOG5_TRIG_MODE_SHIFT (4U) +/*! WDOG5_TRIG_MODE - WDOG5 reset trigger mode configuration,locked by LOCK_CFG field + * 0b0..Level-sensitive: System stays in reset until the reset source deasserts. + * 0b1..Edge-sensitive: System resets once, even if the reset source remains asserted. + */ +#define SRC_GENERAL_REG_SRTMR_WDOG5_TRIG_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_SRTMR_WDOG5_TRIG_MODE_SHIFT)) & SRC_GENERAL_REG_SRTMR_WDOG5_TRIG_MODE_MASK) + +#define SRC_GENERAL_REG_SRTMR_TEMPSENSE_TRIG_MODE_MASK (0x20U) +#define SRC_GENERAL_REG_SRTMR_TEMPSENSE_TRIG_MODE_SHIFT (5U) +/*! TEMPSENSE_TRIG_MODE - Tempsense reset trigger mode configuration,locked by LOCK_CFG field + * 0b0..Level-sensitive: System stays in reset until the reset source deasserts. + * 0b1..Edge-sensitive: System resets once, even if the reset source remains asserted. + */ +#define SRC_GENERAL_REG_SRTMR_TEMPSENSE_TRIG_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_SRTMR_TEMPSENSE_TRIG_MODE_SHIFT)) & SRC_GENERAL_REG_SRTMR_TEMPSENSE_TRIG_MODE_MASK) + +#define SRC_GENERAL_REG_SRTMR_CSU_TRIG_MODE_MASK (0x40U) +#define SRC_GENERAL_REG_SRTMR_CSU_TRIG_MODE_SHIFT (6U) +/*! CSU_TRIG_MODE - CSU reset trigger mode configuration,locked by LOCK_CFG field + * 0b0..Level-sensitive: System stays in reset until the reset source deasserts. + * 0b1..Edge-sensitive: System resets once, even if the reset source remains asserted. + */ +#define SRC_GENERAL_REG_SRTMR_CSU_TRIG_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_SRTMR_CSU_TRIG_MODE_SHIFT)) & SRC_GENERAL_REG_SRTMR_CSU_TRIG_MODE_MASK) + +#define SRC_GENERAL_REG_SRTMR_JTAGSW_TRIG_MODE_MASK (0x80U) +#define SRC_GENERAL_REG_SRTMR_JTAGSW_TRIG_MODE_SHIFT (7U) +/*! JTAGSW_TRIG_MODE - JTAGSW reset trigger mode configuration,locked by LOCK_CFG field + * 0b0..Level-sensitive: System stays in reset until the reset source deasserts. + * 0b1..Edge-sensitive: System resets once, even if the reset source remains asserted. + */ +#define SRC_GENERAL_REG_SRTMR_JTAGSW_TRIG_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_SRTMR_JTAGSW_TRIG_MODE_SHIFT)) & SRC_GENERAL_REG_SRTMR_JTAGSW_TRIG_MODE_MASK) + +#define SRC_GENERAL_REG_SRTMR_JTAG_RST_B_MASK (0x200U) +#define SRC_GENERAL_REG_SRTMR_JTAG_RST_B_SHIFT (9U) +/*! JTAG_RST_B - JTAG_RST_B trigger mode configuration, locked by LOCK_CFG field + * 0b0..Level-sensitive: System stays in reset until the reset source deasserts. + * 0b1..Edge-sensitive: System resets once, even if the reset source remains asserted. + */ +#define SRC_GENERAL_REG_SRTMR_JTAG_RST_B(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_SRTMR_JTAG_RST_B_SHIFT)) & SRC_GENERAL_REG_SRTMR_JTAG_RST_B_MASK) +/*! @} */ + +/*! @name SRMASK - SRC RESET TRIGGER MODE REGISTER */ +/*! @{ */ + +#define SRC_GENERAL_REG_SRMASK_WDOG1_MASK_MASK (0x1U) +#define SRC_GENERAL_REG_SRMASK_WDOG1_MASK_SHIFT (0U) +/*! WDOG1_MASK - WDOG1 reset mask, locked by LOCK_CFG field. + * 0b0..The cold reset source can work. + * 0b1..The cold reset source is masked and cannot work. + */ +#define SRC_GENERAL_REG_SRMASK_WDOG1_MASK(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_SRMASK_WDOG1_MASK_SHIFT)) & SRC_GENERAL_REG_SRMASK_WDOG1_MASK_MASK) + +#define SRC_GENERAL_REG_SRMASK_WDOG2_MASK_MASK (0x2U) +#define SRC_GENERAL_REG_SRMASK_WDOG2_MASK_SHIFT (1U) +/*! WDOG2_MASK - WDOG2 reset mask, locked by LOCK_CFG field. + * 0b0..The cold reset source can work. + * 0b1..The cold reset source is masked and cannot work. + */ +#define SRC_GENERAL_REG_SRMASK_WDOG2_MASK(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_SRMASK_WDOG2_MASK_SHIFT)) & SRC_GENERAL_REG_SRMASK_WDOG2_MASK_MASK) + +#define SRC_GENERAL_REG_SRMASK_WDOG3_MASK_MASK (0x4U) +#define SRC_GENERAL_REG_SRMASK_WDOG3_MASK_SHIFT (2U) +/*! WDOG3_MASK - WDOG3 reset mask, locked by LOCK_CFG field. + * 0b0..The cold reset source can work. + * 0b1..The cold reset source is masked and cannot work. + */ +#define SRC_GENERAL_REG_SRMASK_WDOG3_MASK(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_SRMASK_WDOG3_MASK_SHIFT)) & SRC_GENERAL_REG_SRMASK_WDOG3_MASK_MASK) + +#define SRC_GENERAL_REG_SRMASK_WDOG4_MASK_MASK (0x8U) +#define SRC_GENERAL_REG_SRMASK_WDOG4_MASK_SHIFT (3U) +/*! WDOG4_MASK - WDOG4 reset mask, locked by LOCK_CFG field. + * 0b0..The cold reset source can work. + * 0b1..The cold reset source is masked and cannot work. + */ +#define SRC_GENERAL_REG_SRMASK_WDOG4_MASK(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_SRMASK_WDOG4_MASK_SHIFT)) & SRC_GENERAL_REG_SRMASK_WDOG4_MASK_MASK) + +#define SRC_GENERAL_REG_SRMASK_WDOG5_MASK_MASK (0x10U) +#define SRC_GENERAL_REG_SRMASK_WDOG5_MASK_SHIFT (4U) +/*! WDOG5_MASK - WDOG5 reset mask, locked by LOCK_CFG field. + * 0b0..The cold reset source can work. + * 0b1..The cold reset source is masked and cannot work. + */ +#define SRC_GENERAL_REG_SRMASK_WDOG5_MASK(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_SRMASK_WDOG5_MASK_SHIFT)) & SRC_GENERAL_REG_SRMASK_WDOG5_MASK_MASK) + +#define SRC_GENERAL_REG_SRMASK_TEMPSENSE_MASK_MASK (0x20U) +#define SRC_GENERAL_REG_SRMASK_TEMPSENSE_MASK_SHIFT (5U) +/*! TEMPSENSE_MASK - Tempsense reset mask, locked by LOCK_CFG field. + * 0b0..The cold reset source can work. + * 0b1..The cold reset source is masked and cannot work. + */ +#define SRC_GENERAL_REG_SRMASK_TEMPSENSE_MASK(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_SRMASK_TEMPSENSE_MASK_SHIFT)) & SRC_GENERAL_REG_SRMASK_TEMPSENSE_MASK_MASK) + +#define SRC_GENERAL_REG_SRMASK_CSU_MASK_MASK (0x40U) +#define SRC_GENERAL_REG_SRMASK_CSU_MASK_SHIFT (6U) +/*! CSU_MASK - CSU reset mask, locked by LOCK_CFG field. + * 0b0..The cold reset source can work. + * 0b1..The cold reset source is masked and cannot work. + */ +#define SRC_GENERAL_REG_SRMASK_CSU_MASK(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_SRMASK_CSU_MASK_SHIFT)) & SRC_GENERAL_REG_SRMASK_CSU_MASK_MASK) + +#define SRC_GENERAL_REG_SRMASK_JTAGSW_MASK_MASK (0x80U) +#define SRC_GENERAL_REG_SRMASK_JTAGSW_MASK_SHIFT (7U) +/*! JTAGSW_MASK - JTAG SW reset mask, locked by LOCK_CFG field. + * 0b0..The cold reset source can work. + * 0b1..The cold reset source is masked and cannot work. + */ +#define SRC_GENERAL_REG_SRMASK_JTAGSW_MASK(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_SRMASK_JTAGSW_MASK_SHIFT)) & SRC_GENERAL_REG_SRMASK_JTAGSW_MASK_MASK) + +#define SRC_GENERAL_REG_SRMASK_JTAG_RST_B_MASK_MASK (0x200U) +#define SRC_GENERAL_REG_SRMASK_JTAG_RST_B_MASK_SHIFT (9U) +/*! JTAG_RST_B_MASK - JTAG_RST_B mask, locked by LOCK_CFG field. + * 0b0..The cold reset source can work. + * 0b1..The cold reset source is masked and cannot work. + */ +#define SRC_GENERAL_REG_SRMASK_JTAG_RST_B_MASK(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_SRMASK_JTAG_RST_B_MASK_SHIFT)) & SRC_GENERAL_REG_SRMASK_JTAG_RST_B_MASK_MASK) +/*! @} */ + +/*! @name SRMR1 - SRC RESET MODE REGISTER 1 */ +/*! @{ */ + +#define SRC_GENERAL_REG_SRMR1_WDOG1_RESET_MODE_MASK (0xFFFFU) +#define SRC_GENERAL_REG_SRMR1_WDOG1_RESET_MODE_SHIFT (0U) +/*! WDOG1_RESET_MODE - WDOG1 reset mode configuration, locked by LOCK_CFG field. + * 0b0000000000000000..system + * 0b0000000000000001..bit0: AONMIX + * 0b0000000000000010..bit1: WAKEUPMIX + * 0b0000000000000100..bit2: DDRMIX + * 0b0000000000001000..bit3: DRAM PHY + * 0b0000000000010000..Reserved + * 0b0000000000100000..bit5: NICMIX + * 0b0000000001000000..bit6: HSIOMIX + * 0b0000000010000000..bit7: MEDIAMIX + * 0b0000000100000000..bit8: Reserved + * 0b0000001000000000..bit9: CA55_CPU0 + * 0b0000010000000000..bit10: Reserved + * 0b0000100000000000..bit11: CA55_Platform + */ +#define SRC_GENERAL_REG_SRMR1_WDOG1_RESET_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_SRMR1_WDOG1_RESET_MODE_SHIFT)) & SRC_GENERAL_REG_SRMR1_WDOG1_RESET_MODE_MASK) + +#define SRC_GENERAL_REG_SRMR1_WDOG2_RESET_MODE_MASK (0xFFFF0000U) +#define SRC_GENERAL_REG_SRMR1_WDOG2_RESET_MODE_SHIFT (16U) +/*! WDOG2_RESET_MODE - WDOG2 reset mode configuration, locked by LOCK_CFG field. + * 0b0000000000000000..system + * 0b0000000000000001..bit0: AONMIX + * 0b0000000000000010..bit1: WAKEUPMIX + * 0b0000000000000100..bit2: DDRMIX + * 0b0000000000001000..bit3: DRAM PHY + * 0b0000000000010000..Reserved + * 0b0000000000100000..bit5: NICMIX + * 0b0000000001000000..bit6: HSIOMIX + * 0b0000000010000000..bit7: MEDIAMIX + * 0b0000000100000000..bit8: Reserved + * 0b0000001000000000..bit9: CA55_CPU0 + * 0b0000010000000000..bit10: Reserved + * 0b0000100000000000..bit11: CA55_Platform + */ +#define SRC_GENERAL_REG_SRMR1_WDOG2_RESET_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_SRMR1_WDOG2_RESET_MODE_SHIFT)) & SRC_GENERAL_REG_SRMR1_WDOG2_RESET_MODE_MASK) +/*! @} */ + +/*! @name SRMR2 - SRC RESET MODE REGISTER 2 */ +/*! @{ */ + +#define SRC_GENERAL_REG_SRMR2_WDOG3_RESET_MODE_MASK (0xFFFFU) +#define SRC_GENERAL_REG_SRMR2_WDOG3_RESET_MODE_SHIFT (0U) +/*! WDOG3_RESET_MODE - WDOG3 reset mode configuration, locked by LOCK_CFG field. + * 0b0000000000000000..system + * 0b0000000000000001..bit0: AONMIX + * 0b0000000000000010..bit1: WAKEUPMIX + * 0b0000000000000100..bit2: DDRMIX + * 0b0000000000001000..bit3: DRAM PHY + * 0b0000000000010000..Reserved + * 0b0000000000100000..bit5: NICMIX + * 0b0000000001000000..bit6: HSIOMIX + * 0b0000000010000000..bit7: MEDIAMIX + * 0b0000000100000000..bit8: Reserved + * 0b0000001000000000..bit9: CA55_CPU0 + * 0b0000010000000000..bit10: Reserved + * 0b0000100000000000..bit11: CA55_Platform + */ +#define SRC_GENERAL_REG_SRMR2_WDOG3_RESET_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_SRMR2_WDOG3_RESET_MODE_SHIFT)) & SRC_GENERAL_REG_SRMR2_WDOG3_RESET_MODE_MASK) + +#define SRC_GENERAL_REG_SRMR2_WDOG4_RESET_MODE_MASK (0xFFFF0000U) +#define SRC_GENERAL_REG_SRMR2_WDOG4_RESET_MODE_SHIFT (16U) +/*! WDOG4_RESET_MODE - WDOG4 reset mode configuration, locked by LOCK_CFG field. + * 0b0000000000000000..system + * 0b0000000000000001..bit0: AONMIX + * 0b0000000000000010..bit1: WAKEUPMIX + * 0b0000000000000100..bit2: DDRMIX + * 0b0000000000001000..bit3: DRAM PHY + * 0b0000000000010000..Reserved + * 0b0000000000100000..bit5: NICMIX + * 0b0000000001000000..bit6: HSIOMIX + * 0b0000000010000000..bit7: MEDIAMIX + * 0b0000000100000000..bit8: Reserved + * 0b0000001000000000..bit9: CA55_CPU0 + * 0b0000010000000000..bit10: Reserved + * 0b0000100000000000..bit11: CA55_Platform + */ +#define SRC_GENERAL_REG_SRMR2_WDOG4_RESET_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_SRMR2_WDOG4_RESET_MODE_SHIFT)) & SRC_GENERAL_REG_SRMR2_WDOG4_RESET_MODE_MASK) +/*! @} */ + +/*! @name SRMR3 - SRC RESET MODE REGISTER 3 */ +/*! @{ */ + +#define SRC_GENERAL_REG_SRMR3_WDOG5_RESET_MODE_MASK (0xFFFFU) +#define SRC_GENERAL_REG_SRMR3_WDOG5_RESET_MODE_SHIFT (0U) +/*! WDOG5_RESET_MODE - WDOG5 reset mode configuration, locked by LOCK_CFG field. + * 0b0000000000000000..system + * 0b0000000000000001..bit0: AONMIX + * 0b0000000000000010..bit1: WAKEUPMIX + * 0b0000000000000100..bit2: DDRMIX + * 0b0000000000001000..bit3: DRAM PHY + * 0b0000000000010000..Reserved + * 0b0000000000100000..bit5: NICMIX + * 0b0000000001000000..bit6: HSIOMIX + * 0b0000000010000000..bit7: MEDIAMIX + * 0b0000000100000000..bit8: Reserved + * 0b0000001000000000..bit9: CA55_CPU0 + * 0b0000010000000000..bit10: Reserved + * 0b0000100000000000..bit11: CA55_Platform + */ +#define SRC_GENERAL_REG_SRMR3_WDOG5_RESET_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_SRMR3_WDOG5_RESET_MODE_SHIFT)) & SRC_GENERAL_REG_SRMR3_WDOG5_RESET_MODE_MASK) + +#define SRC_GENERAL_REG_SRMR3_TEMPSENSE_RESET_MODE_MASK (0xFFFF0000U) +#define SRC_GENERAL_REG_SRMR3_TEMPSENSE_RESET_MODE_SHIFT (16U) +/*! TEMPSENSE_RESET_MODE - Tempsense reset mode configuration, locked by LOCK_CFG field. + * 0b0000000000000000..system + * 0b0000000000000001..bit0: AONMIX + * 0b0000000000000010..bit1: WAKEUPMIX + * 0b0000000000000100..bit2: DDRMIX + * 0b0000000000001000..bit3: DRAM PHY + * 0b0000000000010000..Reserved + * 0b0000000000100000..bit5: NICMIX + * 0b0000000001000000..bit6: HSIOMIX + * 0b0000000010000000..bit7: MEDIAMIX + * 0b0000000100000000..bit8: Reserved + * 0b0000001000000000..bit9: CA55_CPU0 + * 0b0000010000000000..bit10: Reserved + * 0b0000100000000000..bit11: CA55_Platform + */ +#define SRC_GENERAL_REG_SRMR3_TEMPSENSE_RESET_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_SRMR3_TEMPSENSE_RESET_MODE_SHIFT)) & SRC_GENERAL_REG_SRMR3_TEMPSENSE_RESET_MODE_MASK) +/*! @} */ + +/*! @name SRMR4 - SRC RESET MODE REGISTER 4 */ +/*! @{ */ + +#define SRC_GENERAL_REG_SRMR4_CSU_RESET_MODE_MASK (0xFFFFU) +#define SRC_GENERAL_REG_SRMR4_CSU_RESET_MODE_SHIFT (0U) +/*! CSU_RESET_MODE - CSU reset mode configuration, locked by LOCK_CFG field. + * 0b0000000000000000..system + * 0b0000000000000001..bit0: AONMIX + * 0b0000000000000010..bit1: WAKEUPMIX + * 0b0000000000000100..bit2: DDRMIX + * 0b0000000000001000..bit3: DRAM PHY + * 0b0000000000010000..Reserved + * 0b0000000000100000..bit5: NICMIX + * 0b0000000001000000..bit6: HSIOMIX + * 0b0000000010000000..bit7: MEDIAMIX + * 0b0000000100000000..bit8: Reserved + * 0b0000001000000000..bit9: CA55_CPU0 + * 0b0000010000000000..bit10: Reserved + * 0b0000100000000000..bit11: CA55_Platform + */ +#define SRC_GENERAL_REG_SRMR4_CSU_RESET_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_SRMR4_CSU_RESET_MODE_SHIFT)) & SRC_GENERAL_REG_SRMR4_CSU_RESET_MODE_MASK) + +#define SRC_GENERAL_REG_SRMR4_JTAGSW_RESET_MODE_MASK (0xFFFF0000U) +#define SRC_GENERAL_REG_SRMR4_JTAGSW_RESET_MODE_SHIFT (16U) +/*! JTAGSW_RESET_MODE - JTAG SW reset mode configuration, locked by LOCK_CFG field. + * 0b0000000000000000..system + * 0b0000000000000001..bit0: AONMIX + * 0b0000000000000010..bit1: WAKEUPMIX + * 0b0000000000000100..bit2: DDRMIX + * 0b0000000000001000..bit3: DRAM PHY + * 0b0000000000010000..Reserved + * 0b0000000000100000..bit5: NICMIX + * 0b0000000001000000..bit6: HSIOMIX + * 0b0000000010000000..bit7: MEDIAMIX + * 0b0000000100000000..bit8: Reserved + * 0b0000001000000000..bit9: CA55_CPU0 + * 0b0000010000000000..bit10: Reserved + * 0b0000100000000000..bit11: CA55_Platform + */ +#define SRC_GENERAL_REG_SRMR4_JTAGSW_RESET_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_SRMR4_JTAGSW_RESET_MODE_SHIFT)) & SRC_GENERAL_REG_SRMR4_JTAGSW_RESET_MODE_MASK) +/*! @} */ + +/*! @name SBMR1 - SRC Boot Mode Register 1 */ +/*! @{ */ + +#define SRC_GENERAL_REG_SBMR1_BOOT_CFG0_MASK (0xFFFFFFFFU) +#define SRC_GENERAL_REG_SBMR1_BOOT_CFG0_SHIFT (0U) +/*! BOOT_CFG0 - This bit field stores the BOOT_CFG8 fuse values. Please refer to the Fusemap for the fuse details. */ +#define SRC_GENERAL_REG_SBMR1_BOOT_CFG0(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_SBMR1_BOOT_CFG0_SHIFT)) & SRC_GENERAL_REG_SBMR1_BOOT_CFG0_MASK) +/*! @} */ + +/*! @name SBMR2 - SRC Boot Mode Register 2 */ +/*! @{ */ + +#define SRC_GENERAL_REG_SBMR2_BOOT_CFG1_MASK (0xFFFFU) +#define SRC_GENERAL_REG_SBMR2_BOOT_CFG1_SHIFT (0U) +/*! BOOT_CFG1 - This bit field stores the BOOT_CFG0[15:0] fuse values. Please refer to the Fusemap for the fuse details. */ +#define SRC_GENERAL_REG_SBMR2_BOOT_CFG1(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_SBMR2_BOOT_CFG1_SHIFT)) & SRC_GENERAL_REG_SBMR2_BOOT_CFG1_MASK) + +#define SRC_GENERAL_REG_SBMR2_SDP_DIS_MASK (0x10000U) +#define SRC_GENERAL_REG_SBMR2_SDP_DIS_SHIFT (16U) +/*! SDP_DIS - Please see the fusemap for fuse details. */ +#define SRC_GENERAL_REG_SBMR2_SDP_DIS(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_SBMR2_SDP_DIS_SHIFT)) & SRC_GENERAL_REG_SBMR2_SDP_DIS_MASK) + +#define SRC_GENERAL_REG_SBMR2_IPP_BOOT_MODE_MASK (0x3F000000U) +#define SRC_GENERAL_REG_SBMR2_IPP_BOOT_MODE_SHIFT (24U) +/*! IPP_BOOT_MODE - Boot mode from pins */ +#define SRC_GENERAL_REG_SBMR2_IPP_BOOT_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_SBMR2_IPP_BOOT_MODE_SHIFT)) & SRC_GENERAL_REG_SBMR2_IPP_BOOT_MODE_MASK) + +#define SRC_GENERAL_REG_SBMR2_DIT_BT_DIS_MASK (0x80000000U) +#define SRC_GENERAL_REG_SBMR2_DIT_BT_DIS_SHIFT (31U) +/*! DIT_BT_DIS - Please see the fusemap for fuse details. */ +#define SRC_GENERAL_REG_SBMR2_DIT_BT_DIS(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_SBMR2_DIT_BT_DIS_SHIFT)) & SRC_GENERAL_REG_SBMR2_DIT_BT_DIS_MASK) +/*! @} */ + +/*! @name SRSR - SRC Reset Status Register */ +/*! @{ */ + +#define SRC_GENERAL_REG_SRSR_SRC_POR_B_MASK (0x1U) +#define SRC_GENERAL_REG_SRSR_SRC_POR_B_SHIFT (0U) +/*! SRC_POR_B - Indicates whether the reset was the result of the system_por_b or jtag_rst_b. + * 0b0..Reset is not caused by system_por_b or jtag_rst_b event. + * 0b1..Reset is caused by system_por_b or jtag_rst_b event. + */ +#define SRC_GENERAL_REG_SRSR_SRC_POR_B(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_SRSR_SRC_POR_B_SHIFT)) & SRC_GENERAL_REG_SRSR_SRC_POR_B_MASK) + +#define SRC_GENERAL_REG_SRSR_IPP_USER_RESET_B_MASK (0x4U) +#define SRC_GENERAL_REG_SRSR_IPP_USER_RESET_B_SHIFT (2U) +/*! IPP_USER_RESET_B - Indicates whether the reset was the result of ipp_user_reset_b. + * 0b0..Reset is not caused by IPP_USER_RESET_B. + * 0b1..Reset is caused by IPP_USER_RESET_B. + */ +#define SRC_GENERAL_REG_SRSR_IPP_USER_RESET_B(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_SRSR_IPP_USER_RESET_B_SHIFT)) & SRC_GENERAL_REG_SRSR_IPP_USER_RESET_B_MASK) + +#define SRC_GENERAL_REG_SRSR_WDOG1_RST_B_MASK (0x8U) +#define SRC_GENERAL_REG_SRSR_WDOG1_RST_B_SHIFT (3U) +/*! WDOG1_RST_B - Time-out reset. Indicates whether the reset was the result of the watchdog1 time-out event. + * 0b0..Reset is not caused by the watchdog1 time-out event. + * 0b1..Reset is caused by the watchdog1 time-out event. + */ +#define SRC_GENERAL_REG_SRSR_WDOG1_RST_B(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_SRSR_WDOG1_RST_B_SHIFT)) & SRC_GENERAL_REG_SRSR_WDOG1_RST_B_MASK) + +#define SRC_GENERAL_REG_SRSR_WDOG2_RST_B_MASK (0x10U) +#define SRC_GENERAL_REG_SRSR_WDOG2_RST_B_SHIFT (4U) +/*! WDOG2_RST_B - Time-out reset. Indicates whether the reset was the result of the watchdog2 time-out event. + * 0b0..Reset is not caused by the watchdog2 time-out event. + * 0b1..Reset is caused by the watchdog2 time-out event. + */ +#define SRC_GENERAL_REG_SRSR_WDOG2_RST_B(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_SRSR_WDOG2_RST_B_SHIFT)) & SRC_GENERAL_REG_SRSR_WDOG2_RST_B_MASK) + +#define SRC_GENERAL_REG_SRSR_WDOG3_RST_B_MASK (0x20U) +#define SRC_GENERAL_REG_SRSR_WDOG3_RST_B_SHIFT (5U) +/*! WDOG3_RST_B - Time-out reset. Indicates whether the reset was the result of the watchdog3 time-out + * 0b0..Reset is not caused by the watchdog3 time-out event. + * 0b1..Reset is caused by the watchdog3 time-out event. + */ +#define SRC_GENERAL_REG_SRSR_WDOG3_RST_B(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_SRSR_WDOG3_RST_B_SHIFT)) & SRC_GENERAL_REG_SRSR_WDOG3_RST_B_MASK) + +#define SRC_GENERAL_REG_SRSR_WDOG4_RST_B_MASK (0x40U) +#define SRC_GENERAL_REG_SRSR_WDOG4_RST_B_SHIFT (6U) +/*! WDOG4_RST_B - Time-out reset. Indicates whether the reset was the result of the watchdog4 time-out + * 0b0..Reset is not caused by the watchdog4 time-out event. + * 0b1..Reset is caused by the watchdog4 time-out event. + */ +#define SRC_GENERAL_REG_SRSR_WDOG4_RST_B(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_SRSR_WDOG4_RST_B_SHIFT)) & SRC_GENERAL_REG_SRSR_WDOG4_RST_B_MASK) + +#define SRC_GENERAL_REG_SRSR_WDOG5_RST_B_MASK (0x80U) +#define SRC_GENERAL_REG_SRSR_WDOG5_RST_B_SHIFT (7U) +/*! WDOG5_RST_B - Time-out reset. Indicates whether the reset was the result of the watchdog5 time-out + * 0b0..Reset is not caused by the watchdog5 time-out event. + * 0b1..Reset is caused by the watchdog5 time-out event. + */ +#define SRC_GENERAL_REG_SRSR_WDOG5_RST_B(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_SRSR_WDOG5_RST_B_SHIFT)) & SRC_GENERAL_REG_SRSR_WDOG5_RST_B_MASK) + +#define SRC_GENERAL_REG_SRSR_TEMPSENSE_RST_B_MASK (0x100U) +#define SRC_GENERAL_REG_SRSR_TEMPSENSE_RST_B_SHIFT (8U) +/*! TEMPSENSE_RST_B - Temper Sensor software reset. Indicates whether the reset was the result of Temperature Sensor. + * 0b0..Reset is not caused by Temperature Sensor. + * 0b1..Reset is caused by Temperature Sensor. + */ +#define SRC_GENERAL_REG_SRSR_TEMPSENSE_RST_B(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_SRSR_TEMPSENSE_RST_B_SHIFT)) & SRC_GENERAL_REG_SRSR_TEMPSENSE_RST_B_MASK) + +#define SRC_GENERAL_REG_SRSR_CSU_RESET_B_MASK (0x200U) +#define SRC_GENERAL_REG_SRSR_CSU_RESET_B_SHIFT (9U) +/*! CSU_RESET_B - Indicates whether the reset was the result of the csu_reset_b input. + * 0b0..Reset is not caused by the csu_reset_b event. + * 0b1..Reset is caused by the csu_reset_b event. + */ +#define SRC_GENERAL_REG_SRSR_CSU_RESET_B(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_SRSR_CSU_RESET_B_SHIFT)) & SRC_GENERAL_REG_SRSR_CSU_RESET_B_MASK) + +#define SRC_GENERAL_REG_SRSR_JTAG_SW_RST_MASK (0x400U) +#define SRC_GENERAL_REG_SRSR_JTAG_SW_RST_SHIFT (10U) +/*! JTAG_SW_RST - JTAG software reset. Indicates whether the reset was the result of JTAG_SW_RST. + * 0b0..Reset is not caused by JTAG_SW_RST. + * 0b1..Reset is caused by JTAG_SW_RST. + */ +#define SRC_GENERAL_REG_SRSR_JTAG_SW_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_SRSR_JTAG_SW_RST_SHIFT)) & SRC_GENERAL_REG_SRSR_JTAG_SW_RST_MASK) + +#define SRC_GENERAL_REG_SRSR_JTAG_RST_B_MASK (0x1000U) +#define SRC_GENERAL_REG_SRSR_JTAG_RST_B_SHIFT (12U) +/*! JTAG_RST_B - Indicates a reset has been caused by JTAG_RST_B + * 0b0..Reset is not caused by JTAG_RST_B. + * 0b1..Reset is caused by JTAG_RST_B. + */ +#define SRC_GENERAL_REG_SRSR_JTAG_RST_B(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_SRSR_JTAG_RST_B_SHIFT)) & SRC_GENERAL_REG_SRSR_JTAG_RST_B_MASK) + +#define SRC_GENERAL_REG_SRSR_AONMIX_RST_MASK (0x10000U) +#define SRC_GENERAL_REG_SRSR_AONMIX_RST_SHIFT (16U) +/*! AONMIX_RST - Indicates whether a AONMIX slice reset happens + * 0b0..Power on reset or system cold reset happens. + * 0b1..AONMIX slice reset happens. + */ +#define SRC_GENERAL_REG_SRSR_AONMIX_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_SRSR_AONMIX_RST_SHIFT)) & SRC_GENERAL_REG_SRSR_AONMIX_RST_MASK) + +#define SRC_GENERAL_REG_SRSR_WAKEUPMIX_RST_MASK (0x20000U) +#define SRC_GENERAL_REG_SRSR_WAKEUPMIX_RST_SHIFT (17U) +/*! WAKEUPMIX_RST - Indicates whether a WAKEUPMIX slice reset happens + * 0b0..Power on reset or system cold reset happens. + * 0b1..WAKEUPMIX slice reset happens. + */ +#define SRC_GENERAL_REG_SRSR_WAKEUPMIX_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_SRSR_WAKEUPMIX_RST_SHIFT)) & SRC_GENERAL_REG_SRSR_WAKEUPMIX_RST_MASK) + +#define SRC_GENERAL_REG_SRSR_DDRMIX_RST_MASK (0x40000U) +#define SRC_GENERAL_REG_SRSR_DDRMIX_RST_SHIFT (18U) +/*! DDRMIX_RST - Indicates whether a DDRMIX slice reset happens + * 0b0..Power on reset or system cold reset happens. + * 0b1..DDRMIX slice reset happens. + */ +#define SRC_GENERAL_REG_SRSR_DDRMIX_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_SRSR_DDRMIX_RST_SHIFT)) & SRC_GENERAL_REG_SRSR_DDRMIX_RST_MASK) + +#define SRC_GENERAL_REG_SRSR_DDRPHY_RST_MASK (0x80000U) +#define SRC_GENERAL_REG_SRSR_DDRPHY_RST_SHIFT (19U) +/*! DDRPHY_RST - Indicates whether a DDRPHY slice reset happens + * 0b0..Power on reset or system cold reset happens. + * 0b1..DDRPHY slice reset happens. + */ +#define SRC_GENERAL_REG_SRSR_DDRPHY_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_SRSR_DDRPHY_RST_SHIFT)) & SRC_GENERAL_REG_SRSR_DDRPHY_RST_MASK) + +#define SRC_GENERAL_REG_SRSR_NICMIX_RST_MASK (0x200000U) +#define SRC_GENERAL_REG_SRSR_NICMIX_RST_SHIFT (21U) +/*! NICMIX_RST - Indicates whether a NICMIX slice reset happens + * 0b0..Power on reset or system cold reset happens. + * 0b1..NICMIX slice reset happens. + */ +#define SRC_GENERAL_REG_SRSR_NICMIX_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_SRSR_NICMIX_RST_SHIFT)) & SRC_GENERAL_REG_SRSR_NICMIX_RST_MASK) + +#define SRC_GENERAL_REG_SRSR_HSIOMIX_RST_MASK (0x400000U) +#define SRC_GENERAL_REG_SRSR_HSIOMIX_RST_SHIFT (22U) +/*! HSIOMIX_RST - Indicates whether a HSIOMIX slice reset happens + * 0b0..Power on reset or system cold reset happens. + * 0b1..HSIOMIX slice reset happens. + */ +#define SRC_GENERAL_REG_SRSR_HSIOMIX_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_SRSR_HSIOMIX_RST_SHIFT)) & SRC_GENERAL_REG_SRSR_HSIOMIX_RST_MASK) + +#define SRC_GENERAL_REG_SRSR_MEDIAMIX_RST_MASK (0x800000U) +#define SRC_GENERAL_REG_SRSR_MEDIAMIX_RST_SHIFT (23U) +/*! MEDIAMIX_RST - Indicates whether a MEDIAMIX slice reset happens + * 0b0..Power on reset or system cold reset happens. + * 0b1..MEDIAMIX slice reset happens. + */ +#define SRC_GENERAL_REG_SRSR_MEDIAMIX_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_SRSR_MEDIAMIX_RST_SHIFT)) & SRC_GENERAL_REG_SRSR_MEDIAMIX_RST_MASK) + +#define SRC_GENERAL_REG_SRSR_A55C0MIX_RST_MASK (0x2000000U) +#define SRC_GENERAL_REG_SRSR_A55C0MIX_RST_SHIFT (25U) +/*! A55C0MIX_RST - Indicates whether a A55C0MIX slice reset happens + * 0b0..Power on reset or system cold reset happens. + * 0b1..A55C0MIX slice reset happens. + */ +#define SRC_GENERAL_REG_SRSR_A55C0MIX_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_SRSR_A55C0MIX_RST_SHIFT)) & SRC_GENERAL_REG_SRSR_A55C0MIX_RST_MASK) + +#define SRC_GENERAL_REG_SRSR_A55PMIX_RST_MASK (0x8000000U) +#define SRC_GENERAL_REG_SRSR_A55PMIX_RST_SHIFT (27U) +/*! A55PMIX_RST - Indicates whether a A55PMIX slice reset happens + * 0b0..Power on reset or system cold reset happens. + * 0b1..A55PMIX slice reset happens. + */ +#define SRC_GENERAL_REG_SRSR_A55PMIX_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_SRSR_A55PMIX_RST_SHIFT)) & SRC_GENERAL_REG_SRSR_A55PMIX_RST_MASK) +/*! @} */ + +/*! @name GPR1 - SRC General Purpose Register 1 */ +/*! @{ */ + +#define SRC_GENERAL_REG_GPR1_GPR_MASK (0xFFFFFFFFU) +#define SRC_GENERAL_REG_GPR1_GPR_SHIFT (0U) +/*! GPR - General Purpose */ +#define SRC_GENERAL_REG_GPR1_GPR(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_GPR1_GPR_SHIFT)) & SRC_GENERAL_REG_GPR1_GPR_MASK) +/*! @} */ + +/*! @name GPR2 - SRC General Purpose Register 2 */ +/*! @{ */ + +#define SRC_GENERAL_REG_GPR2_GPR_MASK (0xFFFFFFFFU) +#define SRC_GENERAL_REG_GPR2_GPR_SHIFT (0U) +/*! GPR - General Purpose */ +#define SRC_GENERAL_REG_GPR2_GPR(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_GPR2_GPR_SHIFT)) & SRC_GENERAL_REG_GPR2_GPR_MASK) +/*! @} */ + +/*! @name GPR3 - SRC General Purpose Register 3 */ +/*! @{ */ + +#define SRC_GENERAL_REG_GPR3_GPR_MASK (0xFFFFFFFFU) +#define SRC_GENERAL_REG_GPR3_GPR_SHIFT (0U) +/*! GPR - General Purpose */ +#define SRC_GENERAL_REG_GPR3_GPR(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_GPR3_GPR_SHIFT)) & SRC_GENERAL_REG_GPR3_GPR_MASK) +/*! @} */ + +/*! @name GPR4 - SRC General Purpose Register 4 */ +/*! @{ */ + +#define SRC_GENERAL_REG_GPR4_GPR_MASK (0xFFFFFFFFU) +#define SRC_GENERAL_REG_GPR4_GPR_SHIFT (0U) +/*! GPR - General Purpose */ +#define SRC_GENERAL_REG_GPR4_GPR(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_GPR4_GPR_SHIFT)) & SRC_GENERAL_REG_GPR4_GPR_MASK) +/*! @} */ + +/*! @name GPR5 - SRC General Purpose Register 5 */ +/*! @{ */ + +#define SRC_GENERAL_REG_GPR5_GPR_MASK (0xFFFFFFFFU) +#define SRC_GENERAL_REG_GPR5_GPR_SHIFT (0U) +/*! GPR - General Purpose */ +#define SRC_GENERAL_REG_GPR5_GPR(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_GPR5_GPR_SHIFT)) & SRC_GENERAL_REG_GPR5_GPR_MASK) +/*! @} */ + +/*! @name GPR6 - SRC General Purpose Register 6 */ +/*! @{ */ + +#define SRC_GENERAL_REG_GPR6_GPR_MASK (0xFFFFFFFFU) +#define SRC_GENERAL_REG_GPR6_GPR_SHIFT (0U) +/*! GPR - General Purpose */ +#define SRC_GENERAL_REG_GPR6_GPR(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_GPR6_GPR_SHIFT)) & SRC_GENERAL_REG_GPR6_GPR_MASK) +/*! @} */ + +/*! @name GPR7 - SRC General Purpose Register 7 */ +/*! @{ */ + +#define SRC_GENERAL_REG_GPR7_GPR_MASK (0xFFFFFFFFU) +#define SRC_GENERAL_REG_GPR7_GPR_SHIFT (0U) +/*! GPR - General Purpose */ +#define SRC_GENERAL_REG_GPR7_GPR(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_GPR7_GPR_SHIFT)) & SRC_GENERAL_REG_GPR7_GPR_MASK) +/*! @} */ + +/*! @name GPR8 - SRC General Purpose Register 8 */ +/*! @{ */ + +#define SRC_GENERAL_REG_GPR8_GPR_MASK (0xFFFFFFFFU) +#define SRC_GENERAL_REG_GPR8_GPR_SHIFT (0U) +/*! GPR - General Purpose */ +#define SRC_GENERAL_REG_GPR8_GPR(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_GPR8_GPR_SHIFT)) & SRC_GENERAL_REG_GPR8_GPR_MASK) +/*! @} */ + +/*! @name GPR9 - SRC General Purpose Register 9 */ +/*! @{ */ + +#define SRC_GENERAL_REG_GPR9_GPR_MASK (0xFFFFFFFFU) +#define SRC_GENERAL_REG_GPR9_GPR_SHIFT (0U) +/*! GPR - General Purpose */ +#define SRC_GENERAL_REG_GPR9_GPR(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_GPR9_GPR_SHIFT)) & SRC_GENERAL_REG_GPR9_GPR_MASK) +/*! @} */ + +/*! @name GPR10 - SRC General Purpose Register 10 */ +/*! @{ */ + +#define SRC_GENERAL_REG_GPR10_GPR_MASK (0xFFFFFFFFU) +#define SRC_GENERAL_REG_GPR10_GPR_SHIFT (0U) +/*! GPR - General Purpose */ +#define SRC_GENERAL_REG_GPR10_GPR(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_GPR10_GPR_SHIFT)) & SRC_GENERAL_REG_GPR10_GPR_MASK) +/*! @} */ + +/*! @name GPR11 - SRC General Purpose Register 11 */ +/*! @{ */ + +#define SRC_GENERAL_REG_GPR11_GPR_MASK (0xFFFFFFFFU) +#define SRC_GENERAL_REG_GPR11_GPR_SHIFT (0U) +/*! GPR - General Purpose */ +#define SRC_GENERAL_REG_GPR11_GPR(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_GPR11_GPR_SHIFT)) & SRC_GENERAL_REG_GPR11_GPR_MASK) +/*! @} */ + +/*! @name GPR12 - SRC General Purpose Register 12 */ +/*! @{ */ + +#define SRC_GENERAL_REG_GPR12_GPR_MASK (0xFFFFFFFFU) +#define SRC_GENERAL_REG_GPR12_GPR_SHIFT (0U) +/*! GPR - General Purpose */ +#define SRC_GENERAL_REG_GPR12_GPR(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_GPR12_GPR_SHIFT)) & SRC_GENERAL_REG_GPR12_GPR_MASK) +/*! @} */ + +/*! @name GPR13 - SRC General Purpose Register 13 */ +/*! @{ */ + +#define SRC_GENERAL_REG_GPR13_GPR_MASK (0xFFFFFFFFU) +#define SRC_GENERAL_REG_GPR13_GPR_SHIFT (0U) +/*! GPR - General Purpose */ +#define SRC_GENERAL_REG_GPR13_GPR(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_GPR13_GPR_SHIFT)) & SRC_GENERAL_REG_GPR13_GPR_MASK) +/*! @} */ + +/*! @name GPR14 - SRC General Purpose Register 14 */ +/*! @{ */ + +#define SRC_GENERAL_REG_GPR14_GPR_MASK (0xFFFFFFFFU) +#define SRC_GENERAL_REG_GPR14_GPR_SHIFT (0U) +/*! GPR - General Purpose */ +#define SRC_GENERAL_REG_GPR14_GPR(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_GPR14_GPR_SHIFT)) & SRC_GENERAL_REG_GPR14_GPR_MASK) +/*! @} */ + +/*! @name GPR15 - SRC General Purpose Register 15 */ +/*! @{ */ + +#define SRC_GENERAL_REG_GPR15_GPR_MASK (0xFFFFFFFFU) +#define SRC_GENERAL_REG_GPR15_GPR_SHIFT (0U) +/*! GPR - General Purpose */ +#define SRC_GENERAL_REG_GPR15_GPR(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_GPR15_GPR_SHIFT)) & SRC_GENERAL_REG_GPR15_GPR_MASK) +/*! @} */ + +/*! @name GPR16 - SRC General Purpose Register 16 */ +/*! @{ */ + +#define SRC_GENERAL_REG_GPR16_GPR_MASK (0xFFFFFFFFU) +#define SRC_GENERAL_REG_GPR16_GPR_SHIFT (0U) +/*! GPR - General Purpose */ +#define SRC_GENERAL_REG_GPR16_GPR(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_GPR16_GPR_SHIFT)) & SRC_GENERAL_REG_GPR16_GPR_MASK) +/*! @} */ + +/*! @name GPR17 - SRC General Purpose Register 17 */ +/*! @{ */ + +#define SRC_GENERAL_REG_GPR17_GPR_MASK (0xFFFFFFFFU) +#define SRC_GENERAL_REG_GPR17_GPR_SHIFT (0U) +/*! GPR - General Purpose */ +#define SRC_GENERAL_REG_GPR17_GPR(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_GPR17_GPR_SHIFT)) & SRC_GENERAL_REG_GPR17_GPR_MASK) +/*! @} */ + +/*! @name GPR18 - SRC General Purpose Register 18 */ +/*! @{ */ + +#define SRC_GENERAL_REG_GPR18_GPR_MASK (0xFFFFFFFFU) +#define SRC_GENERAL_REG_GPR18_GPR_SHIFT (0U) +/*! GPR - General Purpose */ +#define SRC_GENERAL_REG_GPR18_GPR(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_GPR18_GPR_SHIFT)) & SRC_GENERAL_REG_GPR18_GPR_MASK) +/*! @} */ + +/*! @name GPR19 - SRC General Purpose Register 19 */ +/*! @{ */ + +#define SRC_GENERAL_REG_GPR19_GPR_MASK (0xFFFFFFFFU) +#define SRC_GENERAL_REG_GPR19_GPR_SHIFT (0U) +/*! GPR - General Purpose */ +#define SRC_GENERAL_REG_GPR19_GPR(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_GPR19_GPR_SHIFT)) & SRC_GENERAL_REG_GPR19_GPR_MASK) +/*! @} */ + +/*! @name GPR20 - SRC General Purpose Register 20 */ +/*! @{ */ + +#define SRC_GENERAL_REG_GPR20_ANAMIX_ATX_SENSE_BUS_ENABLE_LV_MASK (0x1U) +#define SRC_GENERAL_REG_GPR20_ANAMIX_ATX_SENSE_BUS_ENABLE_LV_SHIFT (0U) +/*! ANAMIX_ATX_SENSE_BUS_ENABLE_LV - ANAMIX ATX sense bus enable */ +#define SRC_GENERAL_REG_GPR20_ANAMIX_ATX_SENSE_BUS_ENABLE_LV(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_GPR20_ANAMIX_ATX_SENSE_BUS_ENABLE_LV_SHIFT)) & SRC_GENERAL_REG_GPR20_ANAMIX_ATX_SENSE_BUS_ENABLE_LV_MASK) + +#define SRC_GENERAL_REG_GPR20_ANAMIX_PLL_CLK_MUX_MASK (0x1EU) +#define SRC_GENERAL_REG_GPR20_ANAMIX_PLL_CLK_MUX_SHIFT (1U) +/*! ANAMIX_PLL_CLK_MUX - ANAMIX PLL clock mux */ +#define SRC_GENERAL_REG_GPR20_ANAMIX_PLL_CLK_MUX(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_GPR20_ANAMIX_PLL_CLK_MUX_SHIFT)) & SRC_GENERAL_REG_GPR20_ANAMIX_PLL_CLK_MUX_MASK) + +#define SRC_GENERAL_REG_GPR20_ANAMIX_REF_SEL_MASK (0x60U) +#define SRC_GENERAL_REG_GPR20_ANAMIX_REF_SEL_SHIFT (5U) +/*! ANAMIX_REF_SEL - ANAMIX reference clock select + * 0b00..OSC24M + * 0b01..CLKIN1 + * 0b10..CLKIN2 + * 0b11..Reserved + */ +#define SRC_GENERAL_REG_GPR20_ANAMIX_REF_SEL(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_GPR20_ANAMIX_REF_SEL_SHIFT)) & SRC_GENERAL_REG_GPR20_ANAMIX_REF_SEL_MASK) + +#define SRC_GENERAL_REG_GPR20_CCM_24MCLK_SEL_MASK (0x180U) +#define SRC_GENERAL_REG_GPR20_CCM_24MCLK_SEL_SHIFT (7U) +/*! CCM_24MCLK_SEL - ANAMIX reference clock select + * 0b00..OSC24M + * 0b01..CLKIN1 + * 0b10..CLKIN2 + * 0b11..CLKIN1 or CLKIN2 + */ +#define SRC_GENERAL_REG_GPR20_CCM_24MCLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_GPR20_CCM_24MCLK_SEL_SHIFT)) & SRC_GENERAL_REG_GPR20_CCM_24MCLK_SEL_MASK) + +#define SRC_GENERAL_REG_GPR20_CLKIN1_ENABLE_MASK (0x200U) +#define SRC_GENERAL_REG_GPR20_CLKIN1_ENABLE_SHIFT (9U) +/*! CLKIN1_ENABLE - CLKIN1 input buffer enable + * 0b0..Input buffer disable + * 0b1..Input buffer enabled. Needed to enable CLKIN1 as an input. + */ +#define SRC_GENERAL_REG_GPR20_CLKIN1_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_GPR20_CLKIN1_ENABLE_SHIFT)) & SRC_GENERAL_REG_GPR20_CLKIN1_ENABLE_MASK) + +#define SRC_GENERAL_REG_GPR20_CLKIN2_ENABLE_MASK (0x400U) +#define SRC_GENERAL_REG_GPR20_CLKIN2_ENABLE_SHIFT (10U) +/*! CLKIN2_ENABLE - CLKIN2 input buffer enable + * 0b0..Input buffer disable + * 0b1..Input buffer enabled. Needed to enable CLKIN2 as an input. + */ +#define SRC_GENERAL_REG_GPR20_CLKIN2_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_GPR20_CLKIN2_ENABLE_SHIFT)) & SRC_GENERAL_REG_GPR20_CLKIN2_ENABLE_MASK) +/*! @} */ + +/*! @name COLD_RESET_SSAR_ACK_CTRL - Cold reset SSAR acknowledge control */ +/*! @{ */ + +#define SRC_GENERAL_REG_COLD_RESET_SSAR_ACK_CTRL_SSAR_CNT_CFG_MASK (0x3FFFU) +#define SRC_GENERAL_REG_COLD_RESET_SSAR_ACK_CTRL_SSAR_CNT_CFG_SHIFT (0U) +/*! SSAR_CNT_CFG - ssar count configure. Usage depends on CNT_MODE, locked by LOCK_CFG field */ +#define SRC_GENERAL_REG_COLD_RESET_SSAR_ACK_CTRL_SSAR_CNT_CFG(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_COLD_RESET_SSAR_ACK_CTRL_SSAR_CNT_CFG_SHIFT)) & SRC_GENERAL_REG_COLD_RESET_SSAR_ACK_CTRL_SSAR_CNT_CFG_MASK) + +#define SRC_GENERAL_REG_COLD_RESET_SSAR_ACK_CTRL_CNT_MODE_MASK (0xC0000000U) +#define SRC_GENERAL_REG_COLD_RESET_SSAR_ACK_CTRL_CNT_MODE_SHIFT (30U) +/*! CNT_MODE - Configure the acknowledge counter working mode. Locked by LOCK_CFG field + * 0b00..Not use counter, raise done to cold_reset_controller once get EdgeLock Enclave ack + * 0b01..Delay after receiving EdgeLock Enclave ack, delay cycle number is CNT_CFG + * 0b10..Ignore EdgeLock Enclave ack, raise done to cold_reset_controller when counting to CNT_CFG value + * 0b11..Time out mode, raise done to cold_reset_controller when either EdgeLock Enclave ack received or counting to CNT_CFG value + */ +#define SRC_GENERAL_REG_COLD_RESET_SSAR_ACK_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_COLD_RESET_SSAR_ACK_CTRL_CNT_MODE_SHIFT)) & SRC_GENERAL_REG_COLD_RESET_SSAR_ACK_CTRL_CNT_MODE_MASK) +/*! @} */ + +/*! @name SP_ISO_CTRL - SRC special ISO Control */ +/*! @{ */ + +#define SRC_GENERAL_REG_SP_ISO_CTRL_USB_PHY1_ISO_MASK (0x1U) +#define SRC_GENERAL_REG_SP_ISO_CTRL_USB_PHY1_ISO_SHIFT (0U) +/*! USB_PHY1_ISO - Software control USB PHY1 isolation enable + * 0b0..Isolation disable + * 0b1..Isolation enable + */ +#define SRC_GENERAL_REG_SP_ISO_CTRL_USB_PHY1_ISO(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_SP_ISO_CTRL_USB_PHY1_ISO_SHIFT)) & SRC_GENERAL_REG_SP_ISO_CTRL_USB_PHY1_ISO_MASK) + +#define SRC_GENERAL_REG_SP_ISO_CTRL_USB_PHY2_ISO_MASK (0x2U) +#define SRC_GENERAL_REG_SP_ISO_CTRL_USB_PHY2_ISO_SHIFT (1U) +/*! USB_PHY2_ISO - Software control USB PHY2 isolation enable + * 0b0..Isolation disable + * 0b1..Isolation enable + */ +#define SRC_GENERAL_REG_SP_ISO_CTRL_USB_PHY2_ISO(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_SP_ISO_CTRL_USB_PHY2_ISO_SHIFT)) & SRC_GENERAL_REG_SP_ISO_CTRL_USB_PHY2_ISO_MASK) +/*! @} */ + +/*! @name ROM_LP_CTRL - ROM Low Power Control */ +/*! @{ */ + +#define SRC_GENERAL_REG_ROM_LP_CTRL_AONMIX_ROM_LP_EN_MASK (0x1U) +#define SRC_GENERAL_REG_ROM_LP_CTRL_AONMIX_ROM_LP_EN_SHIFT (0U) +/*! AONMIX_ROM_LP_EN - ROM in AONMIX low power control enable */ +#define SRC_GENERAL_REG_ROM_LP_CTRL_AONMIX_ROM_LP_EN(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_ROM_LP_CTRL_AONMIX_ROM_LP_EN_SHIFT)) & SRC_GENERAL_REG_ROM_LP_CTRL_AONMIX_ROM_LP_EN_MASK) +/*! @} */ + +/*! @name A55_DENY_STAT - A55 Q_Channel Deny Status */ +/*! @{ */ + +#define SRC_GENERAL_REG_A55_DENY_STAT_A55_CORE0_PWRDN_DENY_STAT_MASK (0x1U) +#define SRC_GENERAL_REG_A55_DENY_STAT_A55_CORE0_PWRDN_DENY_STAT_SHIFT (0U) +/*! A55_CORE0_PWRDN_DENY_STAT - A55 CORE 0 Q_Channel pwrdn deny status */ +#define SRC_GENERAL_REG_A55_DENY_STAT_A55_CORE0_PWRDN_DENY_STAT(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_A55_DENY_STAT_A55_CORE0_PWRDN_DENY_STAT_SHIFT)) & SRC_GENERAL_REG_A55_DENY_STAT_A55_CORE0_PWRDN_DENY_STAT_MASK) + +#define SRC_GENERAL_REG_A55_DENY_STAT_A55_CLUSTER_PWRDN_DENY_STAT_MASK (0x4U) +#define SRC_GENERAL_REG_A55_DENY_STAT_A55_CLUSTER_PWRDN_DENY_STAT_SHIFT (2U) +/*! A55_CLUSTER_PWRDN_DENY_STAT - A55 Cluster Q_Channel pwrdn deny status */ +#define SRC_GENERAL_REG_A55_DENY_STAT_A55_CLUSTER_PWRDN_DENY_STAT(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_A55_DENY_STAT_A55_CLUSTER_PWRDN_DENY_STAT_SHIFT)) & SRC_GENERAL_REG_A55_DENY_STAT_A55_CLUSTER_PWRDN_DENY_STAT_MASK) + +#define SRC_GENERAL_REG_A55_DENY_STAT_A55_CLUSTER_CLKOFF_DENY_STAT_MASK (0x8U) +#define SRC_GENERAL_REG_A55_DENY_STAT_A55_CLUSTER_CLKOFF_DENY_STAT_SHIFT (3U) +/*! A55_CLUSTER_CLKOFF_DENY_STAT - A55 Cluster Q_Channel clockoff deny status */ +#define SRC_GENERAL_REG_A55_DENY_STAT_A55_CLUSTER_CLKOFF_DENY_STAT(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_A55_DENY_STAT_A55_CLUSTER_CLKOFF_DENY_STAT_SHIFT)) & SRC_GENERAL_REG_A55_DENY_STAT_A55_CLUSTER_CLKOFF_DENY_STAT_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group SRC_GENERAL_REG_Register_Masks */ + + +/* SRC_GENERAL_REG - Peripheral instance base addresses */ +/** Peripheral SRC__SRC_GENERAL_REG base address */ +#define SRC__SRC_GENERAL_REG_BASE (0x44460000u) +/** Peripheral SRC__SRC_GENERAL_REG base pointer */ +#define SRC__SRC_GENERAL_REG ((SRC_GENERAL_REG_Type *)SRC__SRC_GENERAL_REG_BASE) +/** Array initializer of SRC_GENERAL_REG peripheral base addresses */ +#define SRC_GENERAL_REG_BASE_ADDRS { SRC__SRC_GENERAL_REG_BASE } +/** Array initializer of SRC_GENERAL_REG peripheral base pointers */ +#define SRC_GENERAL_REG_BASE_PTRS { SRC__SRC_GENERAL_REG } + +/*! + * @} + */ /* end of group SRC_GENERAL_REG_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- SRC_MEM_SLICE Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SRC_MEM_SLICE_Peripheral_Access_Layer SRC_MEM_SLICE Peripheral Access Layer + * @{ + */ + +/** SRC_MEM_SLICE - Register Layout Typedef */ +typedef struct { + uint8_t RESERVED_0[4]; + __IO uint32_t MEM_CTRL; /**< MEM Low Power Control, offset: 0x4 */ + __IO uint32_t MEMLP_CTRL_0; /**< MEM Low Power Control_0, offset: 0x8 */ + uint8_t RESERVED_1[4]; + __IO uint32_t MEMLP_CTRL_1; /**< MEM Low Power Control_1, offset: 0x10 */ + __IO uint32_t MEMLP_CTRL_2; /**< MEM Low Power Control_2, offset: 0x14 */ + __I uint32_t MEM_STAT; /**< MEM Status, offset: 0x18 */ +} SRC_MEM_SLICE_Type; + +/* ---------------------------------------------------------------------------- + -- SRC_MEM_SLICE Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SRC_MEM_SLICE_Register_Masks SRC_MEM_SLICE Register Masks + * @{ + */ + +/*! @name MEM_CTRL - MEM Low Power Control */ +/*! @{ */ + +#define SRC_MEM_SLICE_MEM_CTRL_SW_MEM_CTRL_MASK (0x1U) +#define SRC_MEM_SLICE_MEM_CTRL_SW_MEM_CTRL_SHIFT (0U) +/*! SW_MEM_CTRL - Software control MEM low power + * 0b0..software control MEM to exit low power + * 0b1..software control MEM to enter low power + */ +#define SRC_MEM_SLICE_MEM_CTRL_SW_MEM_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SRC_MEM_SLICE_MEM_CTRL_SW_MEM_CTRL_SHIFT)) & SRC_MEM_SLICE_MEM_CTRL_SW_MEM_CTRL_MASK) + +#define SRC_MEM_SLICE_MEM_CTRL_MEM_LP_MODE_MASK (0x2U) +#define SRC_MEM_SLICE_MEM_CTRL_MEM_LP_MODE_SHIFT (1U) +/*! MEM_LP_MODE - MEM low power mode. Locked by LOCK_CFG field. + * 0b0..Power down mode + * 0b1..Retention mode + */ +#define SRC_MEM_SLICE_MEM_CTRL_MEM_LP_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_MEM_SLICE_MEM_CTRL_MEM_LP_MODE_SHIFT)) & SRC_MEM_SLICE_MEM_CTRL_MEM_LP_MODE_MASK) + +#define SRC_MEM_SLICE_MEM_CTRL_MEM_LP_EN_MASK (0x4U) +#define SRC_MEM_SLICE_MEM_CTRL_MEM_LP_EN_SHIFT (2U) +/*! MEM_LP_EN - Enable MEM low power control. Locked by LOCK_CFG field */ +#define SRC_MEM_SLICE_MEM_CTRL_MEM_LP_EN(x) (((uint32_t)(((uint32_t)(x)) << SRC_MEM_SLICE_MEM_CTRL_MEM_LP_EN_SHIFT)) & SRC_MEM_SLICE_MEM_CTRL_MEM_LP_EN_MASK) + +#define SRC_MEM_SLICE_MEM_CTRL_MEM_LF_CNT_CFG_MASK (0xFF00U) +#define SRC_MEM_SLICE_MEM_CTRL_MEM_LF_CNT_CFG_SHIFT (8U) +/*! MEM_LF_CNT_CFG - MEM power up counter */ +#define SRC_MEM_SLICE_MEM_CTRL_MEM_LF_CNT_CFG(x) (((uint32_t)(((uint32_t)(x)) << SRC_MEM_SLICE_MEM_CTRL_MEM_LF_CNT_CFG_SHIFT)) & SRC_MEM_SLICE_MEM_CTRL_MEM_LF_CNT_CFG_MASK) + +#define SRC_MEM_SLICE_MEM_CTRL_MEM_HF_CNT_CFG_MASK (0xFF0000U) +#define SRC_MEM_SLICE_MEM_CTRL_MEM_HF_CNT_CFG_SHIFT (16U) +/*! MEM_HF_CNT_CFG - MEM power up counter */ +#define SRC_MEM_SLICE_MEM_CTRL_MEM_HF_CNT_CFG(x) (((uint32_t)(((uint32_t)(x)) << SRC_MEM_SLICE_MEM_CTRL_MEM_HF_CNT_CFG_SHIFT)) & SRC_MEM_SLICE_MEM_CTRL_MEM_HF_CNT_CFG_MASK) + +#define SRC_MEM_SLICE_MEM_CTRL_LOCK_CFG_MASK (0x1000000U) +#define SRC_MEM_SLICE_MEM_CTRL_LOCK_CFG_SHIFT (24U) +/*! LOCK_CFG - Configuration lock + * 0b0..Not locked. + * 0b1..Locked. + */ +#define SRC_MEM_SLICE_MEM_CTRL_LOCK_CFG(x) (((uint32_t)(((uint32_t)(x)) << SRC_MEM_SLICE_MEM_CTRL_LOCK_CFG_SHIFT)) & SRC_MEM_SLICE_MEM_CTRL_LOCK_CFG_MASK) +/*! @} */ + +/*! @name MEMLP_CTRL_0 - MEM Low Power Control_0 */ +/*! @{ */ + +#define SRC_MEM_SLICE_MEMLP_CTRL_0_MEMLP_ENT_CNT_MASK (0xFFFFFFFFU) +#define SRC_MEM_SLICE_MEMLP_CTRL_0_MEMLP_ENT_CNT_SHIFT (0U) +/*! MEMLP_ENT_CNT - Delay counter to start entering to memory low power mode. Locked by LOCK_CFG field */ +#define SRC_MEM_SLICE_MEMLP_CTRL_0_MEMLP_ENT_CNT(x) (((uint32_t)(((uint32_t)(x)) << SRC_MEM_SLICE_MEMLP_CTRL_0_MEMLP_ENT_CNT_SHIFT)) & SRC_MEM_SLICE_MEMLP_CTRL_0_MEMLP_ENT_CNT_MASK) +/*! @} */ + +/*! @name MEMLP_CTRL_1 - MEM Low Power Control_1 */ +/*! @{ */ + +#define SRC_MEM_SLICE_MEMLP_CTRL_1_MEMLP_RET_PGEN_CNT_MASK (0xFFFFFFFFU) +#define SRC_MEM_SLICE_MEMLP_CTRL_1_MEMLP_RET_PGEN_CNT_SHIFT (0U) +/*! MEMLP_RET_PGEN_CNT - Delay counter to interval for retn to pgen. Locked by LOCK_CFG field */ +#define SRC_MEM_SLICE_MEMLP_CTRL_1_MEMLP_RET_PGEN_CNT(x) (((uint32_t)(((uint32_t)(x)) << SRC_MEM_SLICE_MEMLP_CTRL_1_MEMLP_RET_PGEN_CNT_SHIFT)) & SRC_MEM_SLICE_MEMLP_CTRL_1_MEMLP_RET_PGEN_CNT_MASK) +/*! @} */ + +/*! @name MEMLP_CTRL_2 - MEM Low Power Control_2 */ +/*! @{ */ + +#define SRC_MEM_SLICE_MEMLP_CTRL_2_MEMLP_EXT_CNT_MASK (0xFFFFFFFFU) +#define SRC_MEM_SLICE_MEMLP_CTRL_2_MEMLP_EXT_CNT_SHIFT (0U) +/*! MEMLP_EXT_CNT - Delay counter to start exiting from memory low power mode. Locked by LOCK_CFG field */ +#define SRC_MEM_SLICE_MEMLP_CTRL_2_MEMLP_EXT_CNT(x) (((uint32_t)(((uint32_t)(x)) << SRC_MEM_SLICE_MEMLP_CTRL_2_MEMLP_EXT_CNT_SHIFT)) & SRC_MEM_SLICE_MEMLP_CTRL_2_MEMLP_EXT_CNT_MASK) +/*! @} */ + +/*! @name MEM_STAT - MEM Status */ +/*! @{ */ + +#define SRC_MEM_SLICE_MEM_STAT_MEM_FSM_STAT_MASK (0xFU) +#define SRC_MEM_SLICE_MEM_STAT_MEM_FSM_STAT_SHIFT (0U) +/*! MEM_FSM_STAT - MEM FSM status */ +#define SRC_MEM_SLICE_MEM_STAT_MEM_FSM_STAT(x) (((uint32_t)(((uint32_t)(x)) << SRC_MEM_SLICE_MEM_STAT_MEM_FSM_STAT_SHIFT)) & SRC_MEM_SLICE_MEM_STAT_MEM_FSM_STAT_MASK) + +#define SRC_MEM_SLICE_MEM_STAT_RET2N_STAT_MASK (0x10U) +#define SRC_MEM_SLICE_MEM_STAT_RET2N_STAT_SHIFT (4U) +/*! RET2N_STAT - RET2N status */ +#define SRC_MEM_SLICE_MEM_STAT_RET2N_STAT(x) (((uint32_t)(((uint32_t)(x)) << SRC_MEM_SLICE_MEM_STAT_RET2N_STAT_SHIFT)) & SRC_MEM_SLICE_MEM_STAT_RET2N_STAT_MASK) + +#define SRC_MEM_SLICE_MEM_STAT_RET1N_STAT_MASK (0x20U) +#define SRC_MEM_SLICE_MEM_STAT_RET1N_STAT_SHIFT (5U) +/*! RET1N_STAT - RET1N status */ +#define SRC_MEM_SLICE_MEM_STAT_RET1N_STAT(x) (((uint32_t)(((uint32_t)(x)) << SRC_MEM_SLICE_MEM_STAT_RET1N_STAT_SHIFT)) & SRC_MEM_SLICE_MEM_STAT_RET1N_STAT_MASK) + +#define SRC_MEM_SLICE_MEM_STAT_PGEN_STAT_MASK (0x40U) +#define SRC_MEM_SLICE_MEM_STAT_PGEN_STAT_SHIFT (6U) +/*! PGEN_STAT - PGEN status */ +#define SRC_MEM_SLICE_MEM_STAT_PGEN_STAT(x) (((uint32_t)(((uint32_t)(x)) << SRC_MEM_SLICE_MEM_STAT_PGEN_STAT_SHIFT)) & SRC_MEM_SLICE_MEM_STAT_PGEN_STAT_MASK) + +#define SRC_MEM_SLICE_MEM_STAT_MEM_STAT_MASK (0x100U) +#define SRC_MEM_SLICE_MEM_STAT_MEM_STAT_SHIFT (8U) +/*! MEM_STAT - MEM status + * 0b0..MEM exit low power + * 0b1..MEM enter low power - rentention1 mode or power down mode + */ +#define SRC_MEM_SLICE_MEM_STAT_MEM_STAT(x) (((uint32_t)(((uint32_t)(x)) << SRC_MEM_SLICE_MEM_STAT_MEM_STAT_SHIFT)) & SRC_MEM_SLICE_MEM_STAT_MEM_STAT_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group SRC_MEM_SLICE_Register_Masks */ + + +/* SRC_MEM_SLICE - Peripheral instance base addresses */ +/** Peripheral SRC__SRC_A55C0_MEM base address */ +#define SRC__SRC_A55C0_MEM_BASE (0x44465C00u) +/** Peripheral SRC__SRC_A55C0_MEM base pointer */ +#define SRC__SRC_A55C0_MEM ((SRC_MEM_SLICE_Type *)SRC__SRC_A55C0_MEM_BASE) +/** Peripheral SRC__SRC_A55_SCU_MEM base address */ +#define SRC__SRC_A55_SCU_MEM_BASE (0x44466400u) +/** Peripheral SRC__SRC_A55_SCU_MEM base pointer */ +#define SRC__SRC_A55_SCU_MEM ((SRC_MEM_SLICE_Type *)SRC__SRC_A55_SCU_MEM_BASE) +/** Peripheral SRC__SRC_AON_MEM base address */ +#define SRC__SRC_AON_MEM_BASE (0x44463800u) +/** Peripheral SRC__SRC_AON_MEM base pointer */ +#define SRC__SRC_AON_MEM ((SRC_MEM_SLICE_Type *)SRC__SRC_AON_MEM_BASE) +/** Peripheral SRC__SRC_DDR_MEM base address */ +#define SRC__SRC_DDR_MEM_BASE (0x44464000u) +/** Peripheral SRC__SRC_DDR_MEM base pointer */ +#define SRC__SRC_DDR_MEM ((SRC_MEM_SLICE_Type *)SRC__SRC_DDR_MEM_BASE) +/** Peripheral SRC__SRC_DPHY_MEM base address */ +#define SRC__SRC_DPHY_MEM_BASE (0x44464400u) +/** Peripheral SRC__SRC_DPHY_MEM base pointer */ +#define SRC__SRC_DPHY_MEM ((SRC_MEM_SLICE_Type *)SRC__SRC_DPHY_MEM_BASE) +/** Peripheral SRC__SRC_HSIO_MEM base address */ +#define SRC__SRC_HSIO_MEM_BASE (0x44465400u) +/** Peripheral SRC__SRC_HSIO_MEM base pointer */ +#define SRC__SRC_HSIO_MEM ((SRC_MEM_SLICE_Type *)SRC__SRC_HSIO_MEM_BASE) +/** Peripheral SRC__SRC_MEDIA_MEM base address */ +#define SRC__SRC_MEDIA_MEM_BASE (0x44465800u) +/** Peripheral SRC__SRC_MEDIA_MEM base pointer */ +#define SRC__SRC_MEDIA_MEM ((SRC_MEM_SLICE_Type *)SRC__SRC_MEDIA_MEM_BASE) +/** Peripheral SRC__SRC_NIC_MEM base address */ +#define SRC__SRC_NIC_MEM_BASE (0x44464C00u) +/** Peripheral SRC__SRC_NIC_MEM base pointer */ +#define SRC__SRC_NIC_MEM ((SRC_MEM_SLICE_Type *)SRC__SRC_NIC_MEM_BASE) +/** Peripheral SRC__SRC_NIC_OCRAM base address */ +#define SRC__SRC_NIC_OCRAM_BASE (0x44465000u) +/** Peripheral SRC__SRC_NIC_OCRAM base pointer */ +#define SRC__SRC_NIC_OCRAM ((SRC_MEM_SLICE_Type *)SRC__SRC_NIC_OCRAM_BASE) +/** Peripheral SRC__SRC_WKUP_MEM base address */ +#define SRC__SRC_WKUP_MEM_BASE (0x44463C00u) +/** Peripheral SRC__SRC_WKUP_MEM base pointer */ +#define SRC__SRC_WKUP_MEM ((SRC_MEM_SLICE_Type *)SRC__SRC_WKUP_MEM_BASE) +/** Array initializer of SRC_MEM_SLICE peripheral base addresses */ +#define SRC_MEM_SLICE_BASE_ADDRS { SRC__SRC_A55C0_MEM_BASE, SRC__SRC_A55_SCU_MEM_BASE, SRC__SRC_AON_MEM_BASE, SRC__SRC_DDR_MEM_BASE, SRC__SRC_DPHY_MEM_BASE, SRC__SRC_HSIO_MEM_BASE, SRC__SRC_MEDIA_MEM_BASE, SRC__SRC_NIC_MEM_BASE, SRC__SRC_NIC_OCRAM_BASE, SRC__SRC_WKUP_MEM_BASE } +/** Array initializer of SRC_MEM_SLICE peripheral base pointers */ +#define SRC_MEM_SLICE_BASE_PTRS { SRC__SRC_A55C0_MEM, SRC__SRC_A55_SCU_MEM, SRC__SRC_AON_MEM, SRC__SRC_DDR_MEM, SRC__SRC_DPHY_MEM, SRC__SRC_HSIO_MEM, SRC__SRC_MEDIA_MEM, SRC__SRC_NIC_MEM, SRC__SRC_NIC_OCRAM, SRC__SRC_WKUP_MEM } + +/*! + * @} + */ /* end of group SRC_MEM_SLICE_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- SRC_MIX_SLICE Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SRC_MIX_SLICE_Peripheral_Access_Layer SRC_MIX_SLICE Peripheral Access Layer + * @{ + */ + +/** SRC_MIX_SLICE - Register Layout Typedef */ +typedef struct { + uint8_t RESERVED_0[4]; + __IO uint32_t AUTHEN_CTRL; /**< Authentication Control, offset: 0x4 */ + uint8_t RESERVED_1[8]; + __IO uint32_t LPM_SETTING_0; /**< Low power mode setting, offset: 0x10 */ + __IO uint32_t LPM_SETTING_1; /**< Low power mode setting, offset: 0x14 */ + __IO uint32_t LPM_SETTING_2; /**< Low power mode setting, offset: 0x18 */ + uint8_t RESERVED_2[4]; + __IO uint32_t SLICE_SW_CTRL; /**< Slice software control, offset: 0x20 */ + __IO uint32_t SINGLE_RESET_SW_CTRL; /**< Single reset by software control, offset: 0x24 */ + uint8_t RESERVED_3[24]; + __IO uint32_t A55_HDSK_ACK_CTRL; /**< A55 handshake acknowledge control, offset: 0x40 */ + __I uint32_t A55_HDSK_ACK_STAT; /**< A55 handshake acknowledge status, offset: 0x44 */ + uint8_t RESERVED_4[8]; + __IO uint32_t SSAR_ACK_CTRL; /**< SSAR acknowledge control, offset: 0x50 */ + __I uint32_t SSAR_ACK_STAT; /**< SSAR acknowledge status, offset: 0x54 */ + uint8_t RESERVED_5[4]; + __IO uint32_t ISO_OFF_DLY_POR; /**< iso off delay control when por, offset: 0x5C */ + __IO uint32_t ISO_ON_DLY; /**< iso on delay control, offset: 0x60 */ + __IO uint32_t ISO_OFF_DLY; /**< iso off delay control, offset: 0x64 */ + __IO uint32_t PSW_OFF_LF_DLY; /**< psw off lf delay control, offset: 0x68 */ + uint8_t RESERVED_6[4]; + __IO uint32_t PSW_OFF_HF_DLY; /**< psw off hf delay control, offset: 0x70 */ + __IO uint32_t PSW_ON_LF_DLY; /**< psw on lf delay control, offset: 0x74 */ + __IO uint32_t PSW_ON_HF_DLY; /**< psw on hf delay control, offset: 0x78 */ + uint8_t RESERVED_7[4]; + __IO uint32_t PSW_ACK_CTRL_0; /**< Power switch acknowledge control, offset: 0x80 */ + __IO uint32_t PSW_ACK_CTRL_1; /**< Power switch acknowledge control, offset: 0x84 */ + __I uint32_t PSW_ACK_STAT; /**< PSW acknowledge status, offset: 0x88 */ + uint8_t RESERVED_8[4]; + __IO uint32_t MTR_ACK_CTRL; /**< MTR acknowledge control, offset: 0x90 */ + __I uint32_t MTR_ACK_STAT; /**< MTR acknowledge status, offset: 0x94 */ + uint8_t RESERVED_9[8]; + __I uint32_t UPI_STAT_0; /**< UPI status 0, offset: 0xA0 */ + __I uint32_t UPI_STAT_1; /**< UPI status 1, offset: 0xA4 */ + __I uint32_t UPI_STAT_2; /**< UPI status 2, offset: 0xA8 */ + __I uint32_t UPI_STAT_3; /**< UPI status 3, offset: 0xAC */ + __I uint32_t FSM_STAT; /**< FSM status, offset: 0xB0 */ + __I uint32_t FUNC_STAT; /**< function status, offset: 0xB4 */ +} SRC_MIX_SLICE_Type; + +/* ---------------------------------------------------------------------------- + -- SRC_MIX_SLICE Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SRC_MIX_SLICE_Register_Masks SRC_MIX_SLICE Register Masks + * @{ + */ + +/*! @name AUTHEN_CTRL - Authentication Control */ +/*! @{ */ + +#define SRC_MIX_SLICE_AUTHEN_CTRL_LPM_MODE_MASK (0x4U) +#define SRC_MIX_SLICE_AUTHEN_CTRL_LPM_MODE_SHIFT (2U) +/*! LPM_MODE - Low power control mode + * 0b0..Low power mode controlled by software + * 0b1..Low power mode controlled by GPC hardware + */ +#define SRC_MIX_SLICE_AUTHEN_CTRL_LPM_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIX_SLICE_AUTHEN_CTRL_LPM_MODE_SHIFT)) & SRC_MIX_SLICE_AUTHEN_CTRL_LPM_MODE_MASK) + +#define SRC_MIX_SLICE_AUTHEN_CTRL_LOCK_CFG_MASK (0x80U) +#define SRC_MIX_SLICE_AUTHEN_CTRL_LOCK_CFG_SHIFT (7U) +/*! LOCK_CFG - Configuration lock + * 0b0..Low power configuration fields are not locked. + * 0b1..Low power configuration fields are locked. + */ +#define SRC_MIX_SLICE_AUTHEN_CTRL_LOCK_CFG(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIX_SLICE_AUTHEN_CTRL_LOCK_CFG_SHIFT)) & SRC_MIX_SLICE_AUTHEN_CTRL_LOCK_CFG_MASK) + +#define SRC_MIX_SLICE_AUTHEN_CTRL_TZ_USER_MASK (0x100U) +#define SRC_MIX_SLICE_AUTHEN_CTRL_TZ_USER_SHIFT (8U) +/*! TZ_USER - Allow user mode access + * 0b0..This MIX SLICE registers can only be written in privilege mode. + * 0b1..This MIX SLICE registers can be written either in privilege mode or user mode. + */ +#define SRC_MIX_SLICE_AUTHEN_CTRL_TZ_USER(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIX_SLICE_AUTHEN_CTRL_TZ_USER_SHIFT)) & SRC_MIX_SLICE_AUTHEN_CTRL_TZ_USER_MASK) + +#define SRC_MIX_SLICE_AUTHEN_CTRL_TZ_NS_MASK (0x200U) +#define SRC_MIX_SLICE_AUTHEN_CTRL_TZ_NS_SHIFT (9U) +/*! TZ_NS - Allow non-secure mode access + * 0b0..This MIX SLICE registers can only be written in secure mode. + * 0b1..This MIX SLICE registers can be written either in secure mode or non-secure mode. + */ +#define SRC_MIX_SLICE_AUTHEN_CTRL_TZ_NS(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIX_SLICE_AUTHEN_CTRL_TZ_NS_SHIFT)) & SRC_MIX_SLICE_AUTHEN_CTRL_TZ_NS_MASK) + +#define SRC_MIX_SLICE_AUTHEN_CTRL_LOCK_TZ_MASK (0x800U) +#define SRC_MIX_SLICE_AUTHEN_CTRL_LOCK_TZ_SHIFT (11U) +/*! LOCK_TZ - Lock NONSECURE and USER + * 0b0..TZ_NS and TZ_USER value can be changed. + * 0b1..TZ_NS and TZ_USER value cannot be changed. + */ +#define SRC_MIX_SLICE_AUTHEN_CTRL_LOCK_TZ(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIX_SLICE_AUTHEN_CTRL_LOCK_TZ_SHIFT)) & SRC_MIX_SLICE_AUTHEN_CTRL_LOCK_TZ_MASK) + +#define SRC_MIX_SLICE_AUTHEN_CTRL_LOCK_LIST_MASK (0x8000U) +#define SRC_MIX_SLICE_AUTHEN_CTRL_LOCK_LIST_SHIFT (15U) +/*! LOCK_LIST - White list lock + * 0b0..WHITE_LIST value can be changed. + * 0b1..WHITE_LIST value cannot be changed. + */ +#define SRC_MIX_SLICE_AUTHEN_CTRL_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIX_SLICE_AUTHEN_CTRL_LOCK_LIST_SHIFT)) & SRC_MIX_SLICE_AUTHEN_CTRL_LOCK_LIST_MASK) + +#define SRC_MIX_SLICE_AUTHEN_CTRL_WHITE_LIST_MASK (0xFFFF0000U) +#define SRC_MIX_SLICE_AUTHEN_CTRL_WHITE_LIST_SHIFT (16U) +/*! WHITE_LIST - Domain ID white list + * 0b0000000000000001..Core with domain ID=0 can write SRC MIX SLICE registers. + * 0b0000000000000010..Core with domain ID=1 can write SRC MIX SLICE registers. + * 0b0000000000000100..Core with domain ID=2 can write SRC MIX SLICE registers. + * 0b0000000000001000..Core with domain ID=3 can write SRC MIX SLICE registers. + * 0b0000000000010000..Core with domain ID=4 can write SRC MIX SLICE registers. + * 0b0000000000100000..Core with domain ID=5 can write SRC MIX SLICE registers. + * 0b0000000001000000..Core with domain ID=6 can write SRC MIX SLICE registers. + * 0b0000000010000000..Core with domain ID=7 can write SRC MIX SLICE registers. + * 0b0000000100000000..Core with domain ID=8 can write SRC MIX SLICE registers. + * 0b0000001000000000..Core with domain ID=9 can write SRC MIX SLICE registers. + * 0b0000010000000000..Core with domain ID=10 can write SRC MIX SLICE registers. + * 0b0000100000000000..Core with domain ID=11 can write SRC MIX SLICE registers. + * 0b0001000000000000..Core with domain ID=12 can write SRC MIX SLICE registers. + * 0b0010000000000000..Core with domain ID=13 can write SRC MIX SLICE registers. + * 0b0100000000000000..Core with domain ID=14 can write SRC MIX SLICE registers. + * 0b1000000000000000..Core with domain ID=15 can write SRC MIX SLICE registers. + */ +#define SRC_MIX_SLICE_AUTHEN_CTRL_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIX_SLICE_AUTHEN_CTRL_WHITE_LIST_SHIFT)) & SRC_MIX_SLICE_AUTHEN_CTRL_WHITE_LIST_MASK) +/*! @} */ + +/*! @name LPM_SETTING_0 - Low power mode setting */ +/*! @{ */ + +#define SRC_MIX_SLICE_LPM_SETTING_0_LPM_SETTING_CD_MASK (0x7U) +#define SRC_MIX_SLICE_LPM_SETTING_0_LPM_SETTING_CD_SHIFT (0U) +/*! LPM_SETTING_CD - LPM setting of current domain + * 0b000..Power always off + * 0b001..Power on when domain n is in RUN, off in WAIT/STOP/SUSPEND + * 0b010..Power on when domain n is in RUN/WAIT, off in STOP/SUSPEND + * 0b011..Power on when domain n is in RUN/WAIT/STOP, off in SUSPEND + * 0b100-0b111..Power always on + */ +#define SRC_MIX_SLICE_LPM_SETTING_0_LPM_SETTING_CD(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIX_SLICE_LPM_SETTING_0_LPM_SETTING_CD_SHIFT)) & SRC_MIX_SLICE_LPM_SETTING_0_LPM_SETTING_CD_MASK) +/*! @} */ + +/*! @name LPM_SETTING_1 - Low power mode setting */ +/*! @{ */ + +#define SRC_MIX_SLICE_LPM_SETTING_1_LPM_SETTING_D0_MASK (0x7U) +#define SRC_MIX_SLICE_LPM_SETTING_1_LPM_SETTING_D0_SHIFT (0U) +/*! LPM_SETTING_D0 - LPM setting of domain 0 + * 0b000..Not used. Do not write this value. + * 0b001..power on when domain n is in RUN, off in WAIT/STOP/SUSPEND + * 0b010..power on when domain n is in RUN/WAIT, off in STOP/SUSPEND + * 0b011..power on when domain n is in RUN/WAIT/STOP, off in SUSPEND + * 0b100-0b111..power always on + */ +#define SRC_MIX_SLICE_LPM_SETTING_1_LPM_SETTING_D0(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIX_SLICE_LPM_SETTING_1_LPM_SETTING_D0_SHIFT)) & SRC_MIX_SLICE_LPM_SETTING_1_LPM_SETTING_D0_MASK) + +#define SRC_MIX_SLICE_LPM_SETTING_1_LPM_SETTING_D1_MASK (0x70U) +#define SRC_MIX_SLICE_LPM_SETTING_1_LPM_SETTING_D1_SHIFT (4U) +/*! LPM_SETTING_D1 - LPM setting of domain 1 + * 0b000..Not used. Do not write this value. + * 0b001..power on when domain n is in RUN, off in WAIT/STOP/SUSPEND + * 0b010..power on when domain n is in RUN/WAIT, off in STOP/SUSPEND + * 0b011..power on when domain n is in RUN/WAIT/STOP, off in SUSPEND + * 0b100-0b111..power always on + */ +#define SRC_MIX_SLICE_LPM_SETTING_1_LPM_SETTING_D1(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIX_SLICE_LPM_SETTING_1_LPM_SETTING_D1_SHIFT)) & SRC_MIX_SLICE_LPM_SETTING_1_LPM_SETTING_D1_MASK) + +#define SRC_MIX_SLICE_LPM_SETTING_1_LPM_SETTING_D2_MASK (0x700U) +#define SRC_MIX_SLICE_LPM_SETTING_1_LPM_SETTING_D2_SHIFT (8U) +/*! LPM_SETTING_D2 - LPM setting of domain 2 + * 0b000..Not used. Do not write this value. + * 0b001..power on when domain n is in RUN, off in WAIT/STOP/SUSPEND + * 0b010..power on when domain n is in RUN/WAIT, off in STOP/SUSPEND + * 0b011..power on when domain n is in RUN/WAIT/STOP, off in SUSPEND + * 0b100-0b111..power always on + */ +#define SRC_MIX_SLICE_LPM_SETTING_1_LPM_SETTING_D2(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIX_SLICE_LPM_SETTING_1_LPM_SETTING_D2_SHIFT)) & SRC_MIX_SLICE_LPM_SETTING_1_LPM_SETTING_D2_MASK) + +#define SRC_MIX_SLICE_LPM_SETTING_1_LPM_SETTING_D3_MASK (0x7000U) +#define SRC_MIX_SLICE_LPM_SETTING_1_LPM_SETTING_D3_SHIFT (12U) +/*! LPM_SETTING_D3 - LPM setting of domain 3 + * 0b000..Not used. Do not write this value. + * 0b001..power on when domain n is in RUN, off in WAIT/STOP/SUSPEND + * 0b010..power on when domain n is in RUN/WAIT, off in STOP/SUSPEND + * 0b011..power on when domain n is in RUN/WAIT/STOP, off in SUSPEND + * 0b100-0b111..power always on + */ +#define SRC_MIX_SLICE_LPM_SETTING_1_LPM_SETTING_D3(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIX_SLICE_LPM_SETTING_1_LPM_SETTING_D3_SHIFT)) & SRC_MIX_SLICE_LPM_SETTING_1_LPM_SETTING_D3_MASK) + +#define SRC_MIX_SLICE_LPM_SETTING_1_LPM_SETTING_D4_MASK (0x70000U) +#define SRC_MIX_SLICE_LPM_SETTING_1_LPM_SETTING_D4_SHIFT (16U) +/*! LPM_SETTING_D4 - LPM setting of domain 4 + * 0b000..Not used. Do not write this value. + * 0b001..power on when domain n is in RUN, off in WAIT/STOP/SUSPEND + * 0b010..power on when domain n is in RUN/WAIT, off in STOP/SUSPEND + * 0b011..power on when domain n is in RUN/WAIT/STOP, off in SUSPEND + * 0b100-0b111..power always on + */ +#define SRC_MIX_SLICE_LPM_SETTING_1_LPM_SETTING_D4(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIX_SLICE_LPM_SETTING_1_LPM_SETTING_D4_SHIFT)) & SRC_MIX_SLICE_LPM_SETTING_1_LPM_SETTING_D4_MASK) + +#define SRC_MIX_SLICE_LPM_SETTING_1_LPM_SETTING_D5_MASK (0x700000U) +#define SRC_MIX_SLICE_LPM_SETTING_1_LPM_SETTING_D5_SHIFT (20U) +/*! LPM_SETTING_D5 - LPM setting of domain 5 + * 0b000..Not used. Do not write this value. + * 0b001..power on when domain n is in RUN, off in WAIT/STOP/SUSPEND + * 0b010..power on when domain n is in RUN/WAIT, off in STOP/SUSPEND + * 0b011..power on when domain n is in RUN/WAIT/STOP, off in SUSPEND + * 0b100-0b111..power always on + */ +#define SRC_MIX_SLICE_LPM_SETTING_1_LPM_SETTING_D5(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIX_SLICE_LPM_SETTING_1_LPM_SETTING_D5_SHIFT)) & SRC_MIX_SLICE_LPM_SETTING_1_LPM_SETTING_D5_MASK) + +#define SRC_MIX_SLICE_LPM_SETTING_1_LPM_SETTING_D6_MASK (0x7000000U) +#define SRC_MIX_SLICE_LPM_SETTING_1_LPM_SETTING_D6_SHIFT (24U) +/*! LPM_SETTING_D6 - LPM setting of domain 6 + * 0b000..Not used. Do not write this value. + * 0b001..power on when domain n is in RUN, off in WAIT/STOP/SUSPEND + * 0b010..power on when domain n is in RUN/WAIT, off in STOP/SUSPEND + * 0b011..power on when domain n is in RUN/WAIT/STOP, off in SUSPEND + * 0b100-0b111..power always on + */ +#define SRC_MIX_SLICE_LPM_SETTING_1_LPM_SETTING_D6(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIX_SLICE_LPM_SETTING_1_LPM_SETTING_D6_SHIFT)) & SRC_MIX_SLICE_LPM_SETTING_1_LPM_SETTING_D6_MASK) + +#define SRC_MIX_SLICE_LPM_SETTING_1_LPM_SETTING_D7_MASK (0x70000000U) +#define SRC_MIX_SLICE_LPM_SETTING_1_LPM_SETTING_D7_SHIFT (28U) +/*! LPM_SETTING_D7 - LPM setting of domain 7 + * 0b000..Not used. Do not write this value. + * 0b001..power on when domain n is in RUN, off in WAIT/STOP/SUSPEND + * 0b010..power on when domain n is in RUN/WAIT, off in STOP/SUSPEND + * 0b011..power on when domain n is in RUN/WAIT/STOP, off in SUSPEND + * 0b100-0b111..power always on + */ +#define SRC_MIX_SLICE_LPM_SETTING_1_LPM_SETTING_D7(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIX_SLICE_LPM_SETTING_1_LPM_SETTING_D7_SHIFT)) & SRC_MIX_SLICE_LPM_SETTING_1_LPM_SETTING_D7_MASK) +/*! @} */ + +/*! @name LPM_SETTING_2 - Low power mode setting */ +/*! @{ */ + +#define SRC_MIX_SLICE_LPM_SETTING_2_LPM_SETTING_D8_MASK (0x7U) +#define SRC_MIX_SLICE_LPM_SETTING_2_LPM_SETTING_D8_SHIFT (0U) +/*! LPM_SETTING_D8 - LPM setting of domain 8 + * 0b000..Not used. Do not write this value. + * 0b001..power on when domain n is in RUN, off in WAIT/STOP/SUSPEND + * 0b010..power on when domain n is in RUN/WAIT, off in STOP/SUSPEND + * 0b011..power on when domain n is in RUN/WAIT/STOP, off in SUSPEND + * 0b100-0b111..power always on + */ +#define SRC_MIX_SLICE_LPM_SETTING_2_LPM_SETTING_D8(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIX_SLICE_LPM_SETTING_2_LPM_SETTING_D8_SHIFT)) & SRC_MIX_SLICE_LPM_SETTING_2_LPM_SETTING_D8_MASK) + +#define SRC_MIX_SLICE_LPM_SETTING_2_LPM_SETTING_D9_MASK (0x70U) +#define SRC_MIX_SLICE_LPM_SETTING_2_LPM_SETTING_D9_SHIFT (4U) +/*! LPM_SETTING_D9 - LPM setting of domain 9 + * 0b000..Not used. Do not write this value. + * 0b001..power on when domain n is in RUN, off in WAIT/STOP/SUSPEND + * 0b010..power on when domain n is in RUN/WAIT, off in STOP/SUSPEND + * 0b011..power on when domain n is in RUN/WAIT/STOP, off in SUSPEND + * 0b100-0b111..power always on + */ +#define SRC_MIX_SLICE_LPM_SETTING_2_LPM_SETTING_D9(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIX_SLICE_LPM_SETTING_2_LPM_SETTING_D9_SHIFT)) & SRC_MIX_SLICE_LPM_SETTING_2_LPM_SETTING_D9_MASK) + +#define SRC_MIX_SLICE_LPM_SETTING_2_LPM_SETTING_D10_MASK (0x700U) +#define SRC_MIX_SLICE_LPM_SETTING_2_LPM_SETTING_D10_SHIFT (8U) +/*! LPM_SETTING_D10 - LPM setting of domain 10 + * 0b000..Not used. Do not write this value. + * 0b001..power on when domain n is in RUN, off in WAIT/STOP/SUSPEND + * 0b010..power on when domain n is in RUN/WAIT, off in STOP/SUSPEND + * 0b011..power on when domain n is in RUN/WAIT/STOP, off in SUSPEND + * 0b100-0b111..power always on + */ +#define SRC_MIX_SLICE_LPM_SETTING_2_LPM_SETTING_D10(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIX_SLICE_LPM_SETTING_2_LPM_SETTING_D10_SHIFT)) & SRC_MIX_SLICE_LPM_SETTING_2_LPM_SETTING_D10_MASK) + +#define SRC_MIX_SLICE_LPM_SETTING_2_LPM_SETTING_D11_MASK (0x7000U) +#define SRC_MIX_SLICE_LPM_SETTING_2_LPM_SETTING_D11_SHIFT (12U) +/*! LPM_SETTING_D11 - LPM setting of domain 11 + * 0b000..Not used. Do not write this value. + * 0b001..power on when domain n is in RUN, off in WAIT/STOP/SUSPEND + * 0b010..power on when domain n is in RUN/WAIT, off in STOP/SUSPEND + * 0b011..power on when domain n is in RUN/WAIT/STOP, off in SUSPEND + * 0b100-0b111..power always on + */ +#define SRC_MIX_SLICE_LPM_SETTING_2_LPM_SETTING_D11(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIX_SLICE_LPM_SETTING_2_LPM_SETTING_D11_SHIFT)) & SRC_MIX_SLICE_LPM_SETTING_2_LPM_SETTING_D11_MASK) + +#define SRC_MIX_SLICE_LPM_SETTING_2_LPM_SETTING_D12_MASK (0x70000U) +#define SRC_MIX_SLICE_LPM_SETTING_2_LPM_SETTING_D12_SHIFT (16U) +/*! LPM_SETTING_D12 - LPM setting of domain 12 + * 0b000..Not used. Do not write this value. + * 0b001..power on when domain n is in RUN, off in WAIT/STOP/SUSPEND + * 0b010..power on when domain n is in RUN/WAIT, off in STOP/SUSPEND + * 0b011..power on when domain n is in RUN/WAIT/STOP, off in SUSPEND + * 0b100-0b111..power always on + */ +#define SRC_MIX_SLICE_LPM_SETTING_2_LPM_SETTING_D12(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIX_SLICE_LPM_SETTING_2_LPM_SETTING_D12_SHIFT)) & SRC_MIX_SLICE_LPM_SETTING_2_LPM_SETTING_D12_MASK) + +#define SRC_MIX_SLICE_LPM_SETTING_2_LPM_SETTING_D13_MASK (0x700000U) +#define SRC_MIX_SLICE_LPM_SETTING_2_LPM_SETTING_D13_SHIFT (20U) +/*! LPM_SETTING_D13 - LPM setting of domain 13 + * 0b000..Not used. Do not write this value. + * 0b001..power on when domain n is in RUN, off in WAIT/STOP/SUSPEND + * 0b010..power on when domain n is in RUN/WAIT, off in STOP/SUSPEND + * 0b011..power on when domain n is in RUN/WAIT/STOP, off in SUSPEND + * 0b100-0b111..power always on + */ +#define SRC_MIX_SLICE_LPM_SETTING_2_LPM_SETTING_D13(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIX_SLICE_LPM_SETTING_2_LPM_SETTING_D13_SHIFT)) & SRC_MIX_SLICE_LPM_SETTING_2_LPM_SETTING_D13_MASK) + +#define SRC_MIX_SLICE_LPM_SETTING_2_LPM_SETTING_D14_MASK (0x7000000U) +#define SRC_MIX_SLICE_LPM_SETTING_2_LPM_SETTING_D14_SHIFT (24U) +/*! LPM_SETTING_D14 - LPM setting of domain 14 + * 0b000..Not used. Do not write this value. + * 0b001..power on when domain n is in RUN, off in WAIT/STOP/SUSPEND + * 0b010..power on when domain n is in RUN/WAIT, off in STOP/SUSPEND + * 0b011..power on when domain n is in RUN/WAIT/STOP, off in SUSPEND + * 0b100-0b111..power always on + */ +#define SRC_MIX_SLICE_LPM_SETTING_2_LPM_SETTING_D14(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIX_SLICE_LPM_SETTING_2_LPM_SETTING_D14_SHIFT)) & SRC_MIX_SLICE_LPM_SETTING_2_LPM_SETTING_D14_MASK) + +#define SRC_MIX_SLICE_LPM_SETTING_2_LPM_SETTING_D15_MASK (0x70000000U) +#define SRC_MIX_SLICE_LPM_SETTING_2_LPM_SETTING_D15_SHIFT (28U) +/*! LPM_SETTING_D15 - LPM setting of domain 15 + * 0b000..Not used. Do not write this value. + * 0b001..power on when domain n is in RUN, off in WAIT/STOP/SUSPEND + * 0b010..power on when domain n is in RUN/WAIT, off in STOP/SUSPEND + * 0b011..power on when domain n is in RUN/WAIT/STOP, off in SUSPEND + * 0b100-0b111..power always on + */ +#define SRC_MIX_SLICE_LPM_SETTING_2_LPM_SETTING_D15(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIX_SLICE_LPM_SETTING_2_LPM_SETTING_D15_SHIFT)) & SRC_MIX_SLICE_LPM_SETTING_2_LPM_SETTING_D15_MASK) +/*! @} */ + +/*! @name SLICE_SW_CTRL - Slice software control */ +/*! @{ */ + +#define SRC_MIX_SLICE_SLICE_SW_CTRL_RST_CTRL_SOFT_MASK (0x1U) +#define SRC_MIX_SLICE_SLICE_SW_CTRL_RST_CTRL_SOFT_SHIFT (0U) +/*! RST_CTRL_SOFT - Software reset control. Locked by LPM_MODE field. + * 0b0..No effect or software reset deassert + * 0b1..Software reset assert + */ +#define SRC_MIX_SLICE_SLICE_SW_CTRL_RST_CTRL_SOFT(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIX_SLICE_SLICE_SW_CTRL_RST_CTRL_SOFT_SHIFT)) & SRC_MIX_SLICE_SLICE_SW_CTRL_RST_CTRL_SOFT_MASK) + +#define SRC_MIX_SLICE_SLICE_SW_CTRL_ISO_CTRL_SOFT_MASK (0x4U) +#define SRC_MIX_SLICE_SLICE_SW_CTRL_ISO_CTRL_SOFT_SHIFT (2U) +/*! ISO_CTRL_SOFT - Software isolation control. Locked by LPM_MODE field. + * 0b0..No effect or software iso off + * 0b1..Software iso on + */ +#define SRC_MIX_SLICE_SLICE_SW_CTRL_ISO_CTRL_SOFT(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIX_SLICE_SLICE_SW_CTRL_ISO_CTRL_SOFT_SHIFT)) & SRC_MIX_SLICE_SLICE_SW_CTRL_ISO_CTRL_SOFT_MASK) + +#define SRC_MIX_SLICE_SLICE_SW_CTRL_PSW_CTRL_SOFT_MASK (0x10U) +#define SRC_MIX_SLICE_SLICE_SW_CTRL_PSW_CTRL_SOFT_SHIFT (4U) +/*! PSW_CTRL_SOFT - Software power switch control. Locked by LPM_MODE field. + * 0b0..No effect or software power switch on + * 0b1..Software power switch off + */ +#define SRC_MIX_SLICE_SLICE_SW_CTRL_PSW_CTRL_SOFT(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIX_SLICE_SLICE_SW_CTRL_PSW_CTRL_SOFT_SHIFT)) & SRC_MIX_SLICE_SLICE_SW_CTRL_PSW_CTRL_SOFT_MASK) + +#define SRC_MIX_SLICE_SLICE_SW_CTRL_MTR_LOAD_SOFT_MASK (0x40U) +#define SRC_MIX_SLICE_SLICE_SW_CTRL_MTR_LOAD_SOFT_SHIFT (6U) +/*! MTR_LOAD_SOFT - Software control MTR repair load. Locked by LPM_MODE field. + * 0b0..No effect + * 0b1..Software load MTR repair + */ +#define SRC_MIX_SLICE_SLICE_SW_CTRL_MTR_LOAD_SOFT(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIX_SLICE_SLICE_SW_CTRL_MTR_LOAD_SOFT_SHIFT)) & SRC_MIX_SLICE_SLICE_SW_CTRL_MTR_LOAD_SOFT_MASK) + +#define SRC_MIX_SLICE_SLICE_SW_CTRL_SSAR_CTRL_SOFT_MASK (0x100U) +#define SRC_MIX_SLICE_SLICE_SW_CTRL_SSAR_CTRL_SOFT_SHIFT (8U) +/*! SSAR_CTRL_SOFT - Software SSAR control. Locked by LPM_MODE field. + * 0b0..No effect or software SSAR restore + * 0b1..Software SSAR save + */ +#define SRC_MIX_SLICE_SLICE_SW_CTRL_SSAR_CTRL_SOFT(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIX_SLICE_SLICE_SW_CTRL_SSAR_CTRL_SOFT_SHIFT)) & SRC_MIX_SLICE_SLICE_SW_CTRL_SSAR_CTRL_SOFT_MASK) + +#define SRC_MIX_SLICE_SLICE_SW_CTRL_A55_HDSK_CTRL_SOFT_MASK (0x400U) +#define SRC_MIX_SLICE_SLICE_SW_CTRL_A55_HDSK_CTRL_SOFT_SHIFT (10U) +/*! A55_HDSK_CTRL_SOFT - Software A55 handshake control. Locked by LPM_MODE field. + * 0b0..No effect or software notify A55 power up info + * 0b1..Software notify A55 power down info + */ +#define SRC_MIX_SLICE_SLICE_SW_CTRL_A55_HDSK_CTRL_SOFT(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIX_SLICE_SLICE_SW_CTRL_A55_HDSK_CTRL_SOFT_SHIFT)) & SRC_MIX_SLICE_SLICE_SW_CTRL_A55_HDSK_CTRL_SOFT_MASK) + +#define SRC_MIX_SLICE_SLICE_SW_CTRL_PDN_SOFT_MASK (0x80000000U) +#define SRC_MIX_SLICE_SLICE_SW_CTRL_PDN_SOFT_SHIFT (31U) +/*! PDN_SOFT - Software power trans control, including reset, iso, and power switch. Locked by LPM_MODE field. + * 0b0..No effect or software power up + * 0b1..Software power down + */ +#define SRC_MIX_SLICE_SLICE_SW_CTRL_PDN_SOFT(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIX_SLICE_SLICE_SW_CTRL_PDN_SOFT_SHIFT)) & SRC_MIX_SLICE_SLICE_SW_CTRL_PDN_SOFT_MASK) +/*! @} */ + +/*! @name SINGLE_RESET_SW_CTRL - Single reset by software control */ +/*! @{ */ + +#define SRC_MIX_SLICE_SINGLE_RESET_SW_CTRL_RST_CTRL_SOFT_0_MASK (0x1U) +#define SRC_MIX_SLICE_SINGLE_RESET_SW_CTRL_RST_CTRL_SOFT_0_SHIFT (0U) +/*! RST_CTRL_SOFT_0 - Locked by LPM_MODE field. */ +#define SRC_MIX_SLICE_SINGLE_RESET_SW_CTRL_RST_CTRL_SOFT_0(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIX_SLICE_SINGLE_RESET_SW_CTRL_RST_CTRL_SOFT_0_SHIFT)) & SRC_MIX_SLICE_SINGLE_RESET_SW_CTRL_RST_CTRL_SOFT_0_MASK) + +#define SRC_MIX_SLICE_SINGLE_RESET_SW_CTRL_RST_CTRL_SOFT_1_MASK (0x4U) +#define SRC_MIX_SLICE_SINGLE_RESET_SW_CTRL_RST_CTRL_SOFT_1_SHIFT (2U) +/*! RST_CTRL_SOFT_1 - Locked by LPM_MODE field. */ +#define SRC_MIX_SLICE_SINGLE_RESET_SW_CTRL_RST_CTRL_SOFT_1(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIX_SLICE_SINGLE_RESET_SW_CTRL_RST_CTRL_SOFT_1_SHIFT)) & SRC_MIX_SLICE_SINGLE_RESET_SW_CTRL_RST_CTRL_SOFT_1_MASK) + +#define SRC_MIX_SLICE_SINGLE_RESET_SW_CTRL_RST_CTRL_SOFT_2_MASK (0x10U) +#define SRC_MIX_SLICE_SINGLE_RESET_SW_CTRL_RST_CTRL_SOFT_2_SHIFT (4U) +/*! RST_CTRL_SOFT_2 - Locked by LPM_MODE field. + * 0b0..Software reset assert + * 0b1..No effect or software reset deassert + */ +#define SRC_MIX_SLICE_SINGLE_RESET_SW_CTRL_RST_CTRL_SOFT_2(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIX_SLICE_SINGLE_RESET_SW_CTRL_RST_CTRL_SOFT_2_SHIFT)) & SRC_MIX_SLICE_SINGLE_RESET_SW_CTRL_RST_CTRL_SOFT_2_MASK) + +#define SRC_MIX_SLICE_SINGLE_RESET_SW_CTRL_RST_CTRL_SOFT_3_MASK (0x40U) +#define SRC_MIX_SLICE_SINGLE_RESET_SW_CTRL_RST_CTRL_SOFT_3_SHIFT (6U) +/*! RST_CTRL_SOFT_3 - Locked by LPM_MODE field. + * 0b0..Software reset assert + * 0b1..No effect or software reset deassert + */ +#define SRC_MIX_SLICE_SINGLE_RESET_SW_CTRL_RST_CTRL_SOFT_3(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIX_SLICE_SINGLE_RESET_SW_CTRL_RST_CTRL_SOFT_3_SHIFT)) & SRC_MIX_SLICE_SINGLE_RESET_SW_CTRL_RST_CTRL_SOFT_3_MASK) + +#define SRC_MIX_SLICE_SINGLE_RESET_SW_CTRL_RST_CTRL_SOFT_4_MASK (0x100U) +#define SRC_MIX_SLICE_SINGLE_RESET_SW_CTRL_RST_CTRL_SOFT_4_SHIFT (8U) +/*! RST_CTRL_SOFT_4 - Locked by LPM_MODE field. + * 0b0..Software reset assert + * 0b1..No effect or software reset deassert + */ +#define SRC_MIX_SLICE_SINGLE_RESET_SW_CTRL_RST_CTRL_SOFT_4(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIX_SLICE_SINGLE_RESET_SW_CTRL_RST_CTRL_SOFT_4_SHIFT)) & SRC_MIX_SLICE_SINGLE_RESET_SW_CTRL_RST_CTRL_SOFT_4_MASK) + +#define SRC_MIX_SLICE_SINGLE_RESET_SW_CTRL_RST_CTRL_SOFT_5_MASK (0x400U) +#define SRC_MIX_SLICE_SINGLE_RESET_SW_CTRL_RST_CTRL_SOFT_5_SHIFT (10U) +/*! RST_CTRL_SOFT_5 - Locked by LPM_MODE field. + * 0b0..software reset assert + * 0b1..No effect or software reset deassert + */ +#define SRC_MIX_SLICE_SINGLE_RESET_SW_CTRL_RST_CTRL_SOFT_5(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIX_SLICE_SINGLE_RESET_SW_CTRL_RST_CTRL_SOFT_5_SHIFT)) & SRC_MIX_SLICE_SINGLE_RESET_SW_CTRL_RST_CTRL_SOFT_5_MASK) +/*! @} */ + +/*! @name A55_HDSK_ACK_CTRL - A55 handshake acknowledge control */ +/*! @{ */ + +#define SRC_MIX_SLICE_A55_HDSK_ACK_CTRL_A55_HDSK_CNT_CFG_MASK (0xFFU) +#define SRC_MIX_SLICE_A55_HDSK_ACK_CTRL_A55_HDSK_CNT_CFG_SHIFT (0U) +/*! A55_HDSK_CNT_CFG - A55 handshake count configure. Usage depends on CNT_MODE. Locked by LOCK_CFG field. */ +#define SRC_MIX_SLICE_A55_HDSK_ACK_CTRL_A55_HDSK_CNT_CFG(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIX_SLICE_A55_HDSK_ACK_CTRL_A55_HDSK_CNT_CFG_SHIFT)) & SRC_MIX_SLICE_A55_HDSK_ACK_CTRL_A55_HDSK_CNT_CFG_MASK) + +#define SRC_MIX_SLICE_A55_HDSK_ACK_CTRL_CNT_MODE_MASK (0xC0000000U) +#define SRC_MIX_SLICE_A55_HDSK_ACK_CTRL_CNT_MODE_SHIFT (30U) +/*! CNT_MODE - Configure the acknowledge counter working mode. Locked by LOCK_CFG field. + * 0b00..Not use counter, raise a55_hdsk done to GPC once get A55 ack + * 0b01..Delay after receiving a55 ack, delay cycle number is CNT_CFG + * 0b10..Ignore A55 ack, raise a55_hdsk done to GPC when counting to CNT_CFG value + * 0b11..Time out mode, raise a55_hdsk done to GPC when either A55 ack received or counting to CNT_CFG value + */ +#define SRC_MIX_SLICE_A55_HDSK_ACK_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIX_SLICE_A55_HDSK_ACK_CTRL_CNT_MODE_SHIFT)) & SRC_MIX_SLICE_A55_HDSK_ACK_CTRL_CNT_MODE_MASK) +/*! @} */ + +/*! @name A55_HDSK_ACK_STAT - A55 handshake acknowledge status */ +/*! @{ */ + +#define SRC_MIX_SLICE_A55_HDSK_ACK_STAT_PDN_ACK_CNT_MASK (0xFFU) +#define SRC_MIX_SLICE_A55_HDSK_ACK_STAT_PDN_ACK_CNT_SHIFT (0U) +/*! PDN_ACK_CNT - A55 handshake power down acknowledge count. */ +#define SRC_MIX_SLICE_A55_HDSK_ACK_STAT_PDN_ACK_CNT(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIX_SLICE_A55_HDSK_ACK_STAT_PDN_ACK_CNT_SHIFT)) & SRC_MIX_SLICE_A55_HDSK_ACK_STAT_PDN_ACK_CNT_MASK) + +#define SRC_MIX_SLICE_A55_HDSK_ACK_STAT_PUP_ACK_CNT_MASK (0xFF0000U) +#define SRC_MIX_SLICE_A55_HDSK_ACK_STAT_PUP_ACK_CNT_SHIFT (16U) +/*! PUP_ACK_CNT - A55 handshake power up acknowledge count */ +#define SRC_MIX_SLICE_A55_HDSK_ACK_STAT_PUP_ACK_CNT(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIX_SLICE_A55_HDSK_ACK_STAT_PUP_ACK_CNT_SHIFT)) & SRC_MIX_SLICE_A55_HDSK_ACK_STAT_PUP_ACK_CNT_MASK) + +#define SRC_MIX_SLICE_A55_HDSK_ACK_STAT_BUSY_A55_PDN_HDSK_MASK (0x40000000U) +#define SRC_MIX_SLICE_A55_HDSK_ACK_STAT_BUSY_A55_PDN_HDSK_SHIFT (30U) +/*! BUSY_A55_PDN_HDSK - Busy requesting A55 power down handshake */ +#define SRC_MIX_SLICE_A55_HDSK_ACK_STAT_BUSY_A55_PDN_HDSK(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIX_SLICE_A55_HDSK_ACK_STAT_BUSY_A55_PDN_HDSK_SHIFT)) & SRC_MIX_SLICE_A55_HDSK_ACK_STAT_BUSY_A55_PDN_HDSK_MASK) + +#define SRC_MIX_SLICE_A55_HDSK_ACK_STAT_BUSY_A55_PUP_HDSK_MASK (0x80000000U) +#define SRC_MIX_SLICE_A55_HDSK_ACK_STAT_BUSY_A55_PUP_HDSK_SHIFT (31U) +/*! BUSY_A55_PUP_HDSK - Busy requesting A55 power up handshake */ +#define SRC_MIX_SLICE_A55_HDSK_ACK_STAT_BUSY_A55_PUP_HDSK(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIX_SLICE_A55_HDSK_ACK_STAT_BUSY_A55_PUP_HDSK_SHIFT)) & SRC_MIX_SLICE_A55_HDSK_ACK_STAT_BUSY_A55_PUP_HDSK_MASK) +/*! @} */ + +/*! @name SSAR_ACK_CTRL - SSAR acknowledge control */ +/*! @{ */ + +#define SRC_MIX_SLICE_SSAR_ACK_CTRL_SSAR_CNT_CFG_MASK (0x3FFFU) +#define SRC_MIX_SLICE_SSAR_ACK_CTRL_SSAR_CNT_CFG_SHIFT (0U) +/*! SSAR_CNT_CFG - ssar count configure. Usage depends on CNT_MODE. Locked by LOCK_CFG field. */ +#define SRC_MIX_SLICE_SSAR_ACK_CTRL_SSAR_CNT_CFG(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIX_SLICE_SSAR_ACK_CTRL_SSAR_CNT_CFG_SHIFT)) & SRC_MIX_SLICE_SSAR_ACK_CTRL_SSAR_CNT_CFG_MASK) + +#define SRC_MIX_SLICE_SSAR_ACK_CTRL_CNT_MODE_MASK (0xC0000000U) +#define SRC_MIX_SLICE_SSAR_ACK_CTRL_CNT_MODE_SHIFT (30U) +/*! CNT_MODE - Configure the acknowledge counter working mode. Locked by LOCK_CFG field. + * 0b00..Not use counter, raise ssar_save/restore done to GPC once get Edgelock Enclave ack + * 0b01..Delay after receiving Edgelock Enclave ack, delay cycle number is CNT_CFG + * 0b10..Ignore Edgelock Enclave ack, raise ssar_save/restore done to GPC when counting to CNT_CFG value + * 0b11..Time out mode, raise ssar_save/restore done to GPC when either Edgelock Enclave ack received or counting to CNT_CFG value + */ +#define SRC_MIX_SLICE_SSAR_ACK_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIX_SLICE_SSAR_ACK_CTRL_CNT_MODE_SHIFT)) & SRC_MIX_SLICE_SSAR_ACK_CTRL_CNT_MODE_MASK) +/*! @} */ + +/*! @name SSAR_ACK_STAT - SSAR acknowledge status */ +/*! @{ */ + +#define SRC_MIX_SLICE_SSAR_ACK_STAT_SAVE_ACK_CNT_MASK (0x3FFFU) +#define SRC_MIX_SLICE_SSAR_ACK_STAT_SAVE_ACK_CNT_SHIFT (0U) +/*! SAVE_ACK_CNT - SAVE acknowledge count, record the delay from stat change to acknowledge received */ +#define SRC_MIX_SLICE_SSAR_ACK_STAT_SAVE_ACK_CNT(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIX_SLICE_SSAR_ACK_STAT_SAVE_ACK_CNT_SHIFT)) & SRC_MIX_SLICE_SSAR_ACK_STAT_SAVE_ACK_CNT_MASK) + +#define SRC_MIX_SLICE_SSAR_ACK_STAT_RESTORE_ACK_CNT_MASK (0xFFFC000U) +#define SRC_MIX_SLICE_SSAR_ACK_STAT_RESTORE_ACK_CNT_SHIFT (14U) +/*! RESTORE_ACK_CNT - RESTORE acknowledge count, record the delay from stat change to acknowledge received */ +#define SRC_MIX_SLICE_SSAR_ACK_STAT_RESTORE_ACK_CNT(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIX_SLICE_SSAR_ACK_STAT_RESTORE_ACK_CNT_SHIFT)) & SRC_MIX_SLICE_SSAR_ACK_STAT_RESTORE_ACK_CNT_MASK) + +#define SRC_MIX_SLICE_SSAR_ACK_STAT_SAVED_MASK (0x20000000U) +#define SRC_MIX_SLICE_SSAR_ACK_STAT_SAVED_SHIFT (29U) +/*! SAVED - Indicate this mix power down info have accepted Edgelock Enclave ack */ +#define SRC_MIX_SLICE_SSAR_ACK_STAT_SAVED(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIX_SLICE_SSAR_ACK_STAT_SAVED_SHIFT)) & SRC_MIX_SLICE_SSAR_ACK_STAT_SAVED_MASK) + +#define SRC_MIX_SLICE_SSAR_ACK_STAT_BUSY_SAVED_MASK (0x40000000U) +#define SRC_MIX_SLICE_SSAR_ACK_STAT_BUSY_SAVED_SHIFT (30U) +/*! BUSY_SAVED - Busy requesting SSAR save */ +#define SRC_MIX_SLICE_SSAR_ACK_STAT_BUSY_SAVED(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIX_SLICE_SSAR_ACK_STAT_BUSY_SAVED_SHIFT)) & SRC_MIX_SLICE_SSAR_ACK_STAT_BUSY_SAVED_MASK) + +#define SRC_MIX_SLICE_SSAR_ACK_STAT_BUSY_RESTORE_MASK (0x80000000U) +#define SRC_MIX_SLICE_SSAR_ACK_STAT_BUSY_RESTORE_SHIFT (31U) +/*! BUSY_RESTORE - Busy requesting SSAR restore */ +#define SRC_MIX_SLICE_SSAR_ACK_STAT_BUSY_RESTORE(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIX_SLICE_SSAR_ACK_STAT_BUSY_RESTORE_SHIFT)) & SRC_MIX_SLICE_SSAR_ACK_STAT_BUSY_RESTORE_MASK) +/*! @} */ + +/*! @name ISO_OFF_DLY_POR - iso off delay control when por */ +/*! @{ */ + +#define SRC_MIX_SLICE_ISO_OFF_DLY_POR_DLY_PRE_ISO_OFF_POR_MASK (0xFFFFFFFFU) +#define SRC_MIX_SLICE_ISO_OFF_DLY_POR_DLY_PRE_ISO_OFF_POR_SHIFT (0U) +/*! DLY_PRE_ISO_OFF_POR - Delay from receiving iso off request to isolation disable. Locked by LOCK_CFG field. */ +#define SRC_MIX_SLICE_ISO_OFF_DLY_POR_DLY_PRE_ISO_OFF_POR(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIX_SLICE_ISO_OFF_DLY_POR_DLY_PRE_ISO_OFF_POR_SHIFT)) & SRC_MIX_SLICE_ISO_OFF_DLY_POR_DLY_PRE_ISO_OFF_POR_MASK) +/*! @} */ + +/*! @name ISO_ON_DLY - iso on delay control */ +/*! @{ */ + +#define SRC_MIX_SLICE_ISO_ON_DLY_DLY_PRE_ISO_ON_MASK (0xFFFFFFFFU) +#define SRC_MIX_SLICE_ISO_ON_DLY_DLY_PRE_ISO_ON_SHIFT (0U) +/*! DLY_PRE_ISO_ON - Delay from receiving iso_on request to isolation enable. Locked by LOCK_CFG field. */ +#define SRC_MIX_SLICE_ISO_ON_DLY_DLY_PRE_ISO_ON(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIX_SLICE_ISO_ON_DLY_DLY_PRE_ISO_ON_SHIFT)) & SRC_MIX_SLICE_ISO_ON_DLY_DLY_PRE_ISO_ON_MASK) +/*! @} */ + +/*! @name ISO_OFF_DLY - iso off delay control */ +/*! @{ */ + +#define SRC_MIX_SLICE_ISO_OFF_DLY_DLY_PRE_ISO_OFF_MASK (0xFFFFFFFFU) +#define SRC_MIX_SLICE_ISO_OFF_DLY_DLY_PRE_ISO_OFF_SHIFT (0U) +/*! DLY_PRE_ISO_OFF - Delay from receiving iso off request to isolation disable. Locked by LOCK_CFG field. */ +#define SRC_MIX_SLICE_ISO_OFF_DLY_DLY_PRE_ISO_OFF(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIX_SLICE_ISO_OFF_DLY_DLY_PRE_ISO_OFF_SHIFT)) & SRC_MIX_SLICE_ISO_OFF_DLY_DLY_PRE_ISO_OFF_MASK) +/*! @} */ + +/*! @name PSW_OFF_LF_DLY - psw off lf delay control */ +/*! @{ */ + +#define SRC_MIX_SLICE_PSW_OFF_LF_DLY_DLY_PRE_PSW_OFF_LF_MASK (0xFFFFFFFFU) +#define SRC_MIX_SLICE_PSW_OFF_LF_DLY_DLY_PRE_PSW_OFF_LF_SHIFT (0U) +/*! DLY_PRE_PSW_OFF_LF - Delay from receiving power off lf request to power switch shut off. Locked by LOCK_CFG field. */ +#define SRC_MIX_SLICE_PSW_OFF_LF_DLY_DLY_PRE_PSW_OFF_LF(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIX_SLICE_PSW_OFF_LF_DLY_DLY_PRE_PSW_OFF_LF_SHIFT)) & SRC_MIX_SLICE_PSW_OFF_LF_DLY_DLY_PRE_PSW_OFF_LF_MASK) +/*! @} */ + +/*! @name PSW_OFF_HF_DLY - psw off hf delay control */ +/*! @{ */ + +#define SRC_MIX_SLICE_PSW_OFF_HF_DLY_DLY_PRE_PSW_OFF_HF_MASK (0xFFFFFFFFU) +#define SRC_MIX_SLICE_PSW_OFF_HF_DLY_DLY_PRE_PSW_OFF_HF_SHIFT (0U) +/*! DLY_PRE_PSW_OFF_HF - Delay from receiving power off hf request to power switch shut off. Locked by LOCK_CFG field. */ +#define SRC_MIX_SLICE_PSW_OFF_HF_DLY_DLY_PRE_PSW_OFF_HF(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIX_SLICE_PSW_OFF_HF_DLY_DLY_PRE_PSW_OFF_HF_SHIFT)) & SRC_MIX_SLICE_PSW_OFF_HF_DLY_DLY_PRE_PSW_OFF_HF_MASK) +/*! @} */ + +/*! @name PSW_ON_LF_DLY - psw on lf delay control */ +/*! @{ */ + +#define SRC_MIX_SLICE_PSW_ON_LF_DLY_DLY_PRE_PSW_ON_LF_MASK (0xFFFFFFFFU) +#define SRC_MIX_SLICE_PSW_ON_LF_DLY_DLY_PRE_PSW_ON_LF_SHIFT (0U) +/*! DLY_PRE_PSW_ON_LF - Delay from receiving power on lf request to power switch turns on. Locked by LOCK_CFG field. */ +#define SRC_MIX_SLICE_PSW_ON_LF_DLY_DLY_PRE_PSW_ON_LF(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIX_SLICE_PSW_ON_LF_DLY_DLY_PRE_PSW_ON_LF_SHIFT)) & SRC_MIX_SLICE_PSW_ON_LF_DLY_DLY_PRE_PSW_ON_LF_MASK) +/*! @} */ + +/*! @name PSW_ON_HF_DLY - psw on hf delay control */ +/*! @{ */ + +#define SRC_MIX_SLICE_PSW_ON_HF_DLY_DLY_PRE_PSW_ON_HF_MASK (0xFFFFFFFFU) +#define SRC_MIX_SLICE_PSW_ON_HF_DLY_DLY_PRE_PSW_ON_HF_SHIFT (0U) +/*! DLY_PRE_PSW_ON_HF - Delay from receiving power on lf request to power switch turns on. Locked by LOCK_CFG field. */ +#define SRC_MIX_SLICE_PSW_ON_HF_DLY_DLY_PRE_PSW_ON_HF(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIX_SLICE_PSW_ON_HF_DLY_DLY_PRE_PSW_ON_HF_SHIFT)) & SRC_MIX_SLICE_PSW_ON_HF_DLY_DLY_PRE_PSW_ON_HF_MASK) +/*! @} */ + +/*! @name PSW_ACK_CTRL_0 - Power switch acknowledge control */ +/*! @{ */ + +#define SRC_MIX_SLICE_PSW_ACK_CTRL_0_PUP_LF_CNT_CFG_MASK (0x3FFU) +#define SRC_MIX_SLICE_PSW_ACK_CTRL_0_PUP_LF_CNT_CFG_SHIFT (0U) +/*! PUP_LF_CNT_CFG - PUP LF Count configure. Usage depends on CNT_MODE. Locked by LOCK_CFG field. */ +#define SRC_MIX_SLICE_PSW_ACK_CTRL_0_PUP_LF_CNT_CFG(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIX_SLICE_PSW_ACK_CTRL_0_PUP_LF_CNT_CFG_SHIFT)) & SRC_MIX_SLICE_PSW_ACK_CTRL_0_PUP_LF_CNT_CFG_MASK) + +#define SRC_MIX_SLICE_PSW_ACK_CTRL_0_PUP_HF_CNT_CFG_MASK (0x3FF0000U) +#define SRC_MIX_SLICE_PSW_ACK_CTRL_0_PUP_HF_CNT_CFG_SHIFT (16U) +/*! PUP_HF_CNT_CFG - PUP HF Count configure. Usage depends on CNT_MODE. Locked by LOCK_CFG field. */ +#define SRC_MIX_SLICE_PSW_ACK_CTRL_0_PUP_HF_CNT_CFG(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIX_SLICE_PSW_ACK_CTRL_0_PUP_HF_CNT_CFG_SHIFT)) & SRC_MIX_SLICE_PSW_ACK_CTRL_0_PUP_HF_CNT_CFG_MASK) + +#define SRC_MIX_SLICE_PSW_ACK_CTRL_0_CNT_MODE_MASK (0x30000000U) +#define SRC_MIX_SLICE_PSW_ACK_CTRL_0_CNT_MODE_SHIFT (28U) +/*! CNT_MODE - Configure the acknowledge counter working mode. Locked by LOCK_CFG field. + * 0b00..Not use counter, raise power_on/off done to GPC once get psw ack + * 0b01..Delay after receiving psw ack, delay cycle number is CNT_CFG + * 0b10..Ignore psw ack, raise power_on/off done to GPC when counting to CNT_CFG value + * 0b11..Time out mode, raise power_on/off done to GPC when either psw ack received or counting to CNT_CFG value + */ +#define SRC_MIX_SLICE_PSW_ACK_CTRL_0_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIX_SLICE_PSW_ACK_CTRL_0_CNT_MODE_SHIFT)) & SRC_MIX_SLICE_PSW_ACK_CTRL_0_CNT_MODE_MASK) + +#define SRC_MIX_SLICE_PSW_ACK_CTRL_0_LF_ACK_INVERT_MASK (0x40000000U) +#define SRC_MIX_SLICE_PSW_ACK_CTRL_0_LF_ACK_INVERT_SHIFT (30U) +/*! LF_ACK_INVERT - LF Acknowledge value is inverted from power switch control. Locked by LOCK_CFG field. */ +#define SRC_MIX_SLICE_PSW_ACK_CTRL_0_LF_ACK_INVERT(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIX_SLICE_PSW_ACK_CTRL_0_LF_ACK_INVERT_SHIFT)) & SRC_MIX_SLICE_PSW_ACK_CTRL_0_LF_ACK_INVERT_MASK) + +#define SRC_MIX_SLICE_PSW_ACK_CTRL_0_HF_ACK_INVERT_MASK (0x80000000U) +#define SRC_MIX_SLICE_PSW_ACK_CTRL_0_HF_ACK_INVERT_SHIFT (31U) +/*! HF_ACK_INVERT - HF Acknowledge value is inverted from power switch control. Locked by LOCK_CFG field. */ +#define SRC_MIX_SLICE_PSW_ACK_CTRL_0_HF_ACK_INVERT(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIX_SLICE_PSW_ACK_CTRL_0_HF_ACK_INVERT_SHIFT)) & SRC_MIX_SLICE_PSW_ACK_CTRL_0_HF_ACK_INVERT_MASK) +/*! @} */ + +/*! @name PSW_ACK_CTRL_1 - Power switch acknowledge control */ +/*! @{ */ + +#define SRC_MIX_SLICE_PSW_ACK_CTRL_1_PDN_LF_CNT_CFG_MASK (0x3FFU) +#define SRC_MIX_SLICE_PSW_ACK_CTRL_1_PDN_LF_CNT_CFG_SHIFT (0U) +/*! PDN_LF_CNT_CFG - PDN LF Count configure. Usage depends on CNT_MODE. Locked by LOCK_CFG field. */ +#define SRC_MIX_SLICE_PSW_ACK_CTRL_1_PDN_LF_CNT_CFG(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIX_SLICE_PSW_ACK_CTRL_1_PDN_LF_CNT_CFG_SHIFT)) & SRC_MIX_SLICE_PSW_ACK_CTRL_1_PDN_LF_CNT_CFG_MASK) + +#define SRC_MIX_SLICE_PSW_ACK_CTRL_1_PDN_HF_CNT_CFG_MASK (0x3FF0000U) +#define SRC_MIX_SLICE_PSW_ACK_CTRL_1_PDN_HF_CNT_CFG_SHIFT (16U) +/*! PDN_HF_CNT_CFG - PDN HF Count configure. Usage depends on CNT_MODE. Locked by LOCK_CFG field. */ +#define SRC_MIX_SLICE_PSW_ACK_CTRL_1_PDN_HF_CNT_CFG(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIX_SLICE_PSW_ACK_CTRL_1_PDN_HF_CNT_CFG_SHIFT)) & SRC_MIX_SLICE_PSW_ACK_CTRL_1_PDN_HF_CNT_CFG_MASK) +/*! @} */ + +/*! @name PSW_ACK_STAT - PSW acknowledge status */ +/*! @{ */ + +#define SRC_MIX_SLICE_PSW_ACK_STAT_LF_ACK_CNT_MASK (0x3FFU) +#define SRC_MIX_SLICE_PSW_ACK_STAT_LF_ACK_CNT_SHIFT (0U) +/*! LF_ACK_CNT - LF PSW acknowledge count */ +#define SRC_MIX_SLICE_PSW_ACK_STAT_LF_ACK_CNT(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIX_SLICE_PSW_ACK_STAT_LF_ACK_CNT_SHIFT)) & SRC_MIX_SLICE_PSW_ACK_STAT_LF_ACK_CNT_MASK) + +#define SRC_MIX_SLICE_PSW_ACK_STAT_HF_ACK_CNT_MASK (0x3FF0000U) +#define SRC_MIX_SLICE_PSW_ACK_STAT_HF_ACK_CNT_SHIFT (16U) +/*! HF_ACK_CNT - HF PSW acknowledge count */ +#define SRC_MIX_SLICE_PSW_ACK_STAT_HF_ACK_CNT(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIX_SLICE_PSW_ACK_STAT_HF_ACK_CNT_SHIFT)) & SRC_MIX_SLICE_PSW_ACK_STAT_HF_ACK_CNT_MASK) + +#define SRC_MIX_SLICE_PSW_ACK_STAT_LF_ACK_STAT_MASK (0x40000000U) +#define SRC_MIX_SLICE_PSW_ACK_STAT_LF_ACK_STAT_SHIFT (30U) +/*! LF_ACK_STAT - LF PSW acknowledge status */ +#define SRC_MIX_SLICE_PSW_ACK_STAT_LF_ACK_STAT(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIX_SLICE_PSW_ACK_STAT_LF_ACK_STAT_SHIFT)) & SRC_MIX_SLICE_PSW_ACK_STAT_LF_ACK_STAT_MASK) + +#define SRC_MIX_SLICE_PSW_ACK_STAT_HF_ACK_STAT_MASK (0x80000000U) +#define SRC_MIX_SLICE_PSW_ACK_STAT_HF_ACK_STAT_SHIFT (31U) +/*! HF_ACK_STAT - HF PSW acknowledge status */ +#define SRC_MIX_SLICE_PSW_ACK_STAT_HF_ACK_STAT(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIX_SLICE_PSW_ACK_STAT_HF_ACK_STAT_SHIFT)) & SRC_MIX_SLICE_PSW_ACK_STAT_HF_ACK_STAT_MASK) +/*! @} */ + +/*! @name MTR_ACK_CTRL - MTR acknowledge control */ +/*! @{ */ + +#define SRC_MIX_SLICE_MTR_ACK_CTRL_MTR_CNT_CFG_MASK (0xFFU) +#define SRC_MIX_SLICE_MTR_ACK_CTRL_MTR_CNT_CFG_SHIFT (0U) +/*! MTR_CNT_CFG - MTR count configure. Usage depends on CNT_MODE. Locked by LOCK_CFG field. */ +#define SRC_MIX_SLICE_MTR_ACK_CTRL_MTR_CNT_CFG(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIX_SLICE_MTR_ACK_CTRL_MTR_CNT_CFG_SHIFT)) & SRC_MIX_SLICE_MTR_ACK_CTRL_MTR_CNT_CFG_MASK) + +#define SRC_MIX_SLICE_MTR_ACK_CTRL_CNT_MODE_MASK (0xC0000000U) +#define SRC_MIX_SLICE_MTR_ACK_CTRL_CNT_MODE_SHIFT (30U) +/*! CNT_MODE - Configure the acknowledge counter working mode. Locked by LOCK_CFG field. + * 0b00..Not use counter, raise mtr done to GPC once get MTR ack + * 0b01..Delay after receiving MTR ack, delay cycle number is CNT_CFG + * 0b10..Ignore MTR ack, raise mtr done to GPC when counting to CNT_CFG value + * 0b11..Time out mode, raise mtr done to GPC when either MTR ack received or counting to CNT_CFG value + */ +#define SRC_MIX_SLICE_MTR_ACK_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIX_SLICE_MTR_ACK_CTRL_CNT_MODE_SHIFT)) & SRC_MIX_SLICE_MTR_ACK_CTRL_CNT_MODE_MASK) +/*! @} */ + +/*! @name MTR_ACK_STAT - MTR acknowledge status */ +/*! @{ */ + +#define SRC_MIX_SLICE_MTR_ACK_STAT_MTR_ACK_CNT_MASK (0xFFU) +#define SRC_MIX_SLICE_MTR_ACK_STAT_MTR_ACK_CNT_SHIFT (0U) +/*! MTR_ACK_CNT - MTR acknowledge count, record the delay from stat change to acknowledge received */ +#define SRC_MIX_SLICE_MTR_ACK_STAT_MTR_ACK_CNT(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIX_SLICE_MTR_ACK_STAT_MTR_ACK_CNT_SHIFT)) & SRC_MIX_SLICE_MTR_ACK_STAT_MTR_ACK_CNT_MASK) + +#define SRC_MIX_SLICE_MTR_ACK_STAT_MTR_DONE_MASK (0x40000000U) +#define SRC_MIX_SLICE_MTR_ACK_STAT_MTR_DONE_SHIFT (30U) +/*! MTR_DONE - Indicate MTR load repair finished */ +#define SRC_MIX_SLICE_MTR_ACK_STAT_MTR_DONE(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIX_SLICE_MTR_ACK_STAT_MTR_DONE_SHIFT)) & SRC_MIX_SLICE_MTR_ACK_STAT_MTR_DONE_MASK) + +#define SRC_MIX_SLICE_MTR_ACK_STAT_BUSY_MTR_MASK (0x80000000U) +#define SRC_MIX_SLICE_MTR_ACK_STAT_BUSY_MTR_SHIFT (31U) +/*! BUSY_MTR - Busy requesting MTR */ +#define SRC_MIX_SLICE_MTR_ACK_STAT_BUSY_MTR(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIX_SLICE_MTR_ACK_STAT_BUSY_MTR_SHIFT)) & SRC_MIX_SLICE_MTR_ACK_STAT_BUSY_MTR_MASK) +/*! @} */ + +/*! @name UPI_STAT_0 - UPI status 0 */ +/*! @{ */ + +#define SRC_MIX_SLICE_UPI_STAT_0_UPI_ISO_REQUEST_MASK (0xFFFFU) +#define SRC_MIX_SLICE_UPI_STAT_0_UPI_ISO_REQUEST_SHIFT (0U) +/*! UPI_ISO_REQUEST - CPU mode trans iso request of 16 domains */ +#define SRC_MIX_SLICE_UPI_STAT_0_UPI_ISO_REQUEST(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIX_SLICE_UPI_STAT_0_UPI_ISO_REQUEST_SHIFT)) & SRC_MIX_SLICE_UPI_STAT_0_UPI_ISO_REQUEST_MASK) + +#define SRC_MIX_SLICE_UPI_STAT_0_UPI_POWER_REQUEST_MASK (0xFFFF0000U) +#define SRC_MIX_SLICE_UPI_STAT_0_UPI_POWER_REQUEST_SHIFT (16U) +/*! UPI_POWER_REQUEST - CPU mode trans power request of 16 domains */ +#define SRC_MIX_SLICE_UPI_STAT_0_UPI_POWER_REQUEST(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIX_SLICE_UPI_STAT_0_UPI_POWER_REQUEST_SHIFT)) & SRC_MIX_SLICE_UPI_STAT_0_UPI_POWER_REQUEST_MASK) +/*! @} */ + +/*! @name UPI_STAT_1 - UPI status 1 */ +/*! @{ */ + +#define SRC_MIX_SLICE_UPI_STAT_1_UPI_RESET_REQUEST_MASK (0xFFFFU) +#define SRC_MIX_SLICE_UPI_STAT_1_UPI_RESET_REQUEST_SHIFT (0U) +/*! UPI_RESET_REQUEST - CPU mode trans reset request of 16 domains */ +#define SRC_MIX_SLICE_UPI_STAT_1_UPI_RESET_REQUEST(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIX_SLICE_UPI_STAT_1_UPI_RESET_REQUEST_SHIFT)) & SRC_MIX_SLICE_UPI_STAT_1_UPI_RESET_REQUEST_MASK) + +#define SRC_MIX_SLICE_UPI_STAT_1_UPI_SSAR_REQUEST_MASK (0xFFFF0000U) +#define SRC_MIX_SLICE_UPI_STAT_1_UPI_SSAR_REQUEST_SHIFT (16U) +/*! UPI_SSAR_REQUEST - CPU mode trans ssar request of 16 domains */ +#define SRC_MIX_SLICE_UPI_STAT_1_UPI_SSAR_REQUEST(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIX_SLICE_UPI_STAT_1_UPI_SSAR_REQUEST_SHIFT)) & SRC_MIX_SLICE_UPI_STAT_1_UPI_SSAR_REQUEST_MASK) +/*! @} */ + +/*! @name UPI_STAT_2 - UPI status 2 */ +/*! @{ */ + +#define SRC_MIX_SLICE_UPI_STAT_2_UPI_MTR_REQUEST_MASK (0xFFFFU) +#define SRC_MIX_SLICE_UPI_STAT_2_UPI_MTR_REQUEST_SHIFT (0U) +/*! UPI_MTR_REQUEST - CPU mode trans mtr request of 16 domains */ +#define SRC_MIX_SLICE_UPI_STAT_2_UPI_MTR_REQUEST(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIX_SLICE_UPI_STAT_2_UPI_MTR_REQUEST_SHIFT)) & SRC_MIX_SLICE_UPI_STAT_2_UPI_MTR_REQUEST_MASK) + +#define SRC_MIX_SLICE_UPI_STAT_2_UPI_A55_HDSK_REQUEST_MASK (0xFFFF0000U) +#define SRC_MIX_SLICE_UPI_STAT_2_UPI_A55_HDSK_REQUEST_SHIFT (16U) +/*! UPI_A55_HDSK_REQUEST - CPU mode trans A55 handshake request of 16 domains */ +#define SRC_MIX_SLICE_UPI_STAT_2_UPI_A55_HDSK_REQUEST(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIX_SLICE_UPI_STAT_2_UPI_A55_HDSK_REQUEST_SHIFT)) & SRC_MIX_SLICE_UPI_STAT_2_UPI_A55_HDSK_REQUEST_MASK) +/*! @} */ + +/*! @name UPI_STAT_3 - UPI status 3 */ +/*! @{ */ + +#define SRC_MIX_SLICE_UPI_STAT_3_UPI_MEM_REQUEST_MASK (0xFFFFU) +#define SRC_MIX_SLICE_UPI_STAT_3_UPI_MEM_REQUEST_SHIFT (0U) +/*! UPI_MEM_REQUEST - CPU mode trans mem request of 16 domains */ +#define SRC_MIX_SLICE_UPI_STAT_3_UPI_MEM_REQUEST(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIX_SLICE_UPI_STAT_3_UPI_MEM_REQUEST_SHIFT)) & SRC_MIX_SLICE_UPI_STAT_3_UPI_MEM_REQUEST_MASK) +/*! @} */ + +/*! @name FSM_STAT - FSM status */ +/*! @{ */ + +#define SRC_MIX_SLICE_FSM_STAT_PSW_STAT_MASK (0xFU) +#define SRC_MIX_SLICE_FSM_STAT_PSW_STAT_SHIFT (0U) +/*! PSW_STAT - Power switch FSM status */ +#define SRC_MIX_SLICE_FSM_STAT_PSW_STAT(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIX_SLICE_FSM_STAT_PSW_STAT_SHIFT)) & SRC_MIX_SLICE_FSM_STAT_PSW_STAT_MASK) + +#define SRC_MIX_SLICE_FSM_STAT_RST_STAT_MASK (0xF0U) +#define SRC_MIX_SLICE_FSM_STAT_RST_STAT_SHIFT (4U) +/*! RST_STAT - Reset FSM status */ +#define SRC_MIX_SLICE_FSM_STAT_RST_STAT(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIX_SLICE_FSM_STAT_RST_STAT_SHIFT)) & SRC_MIX_SLICE_FSM_STAT_RST_STAT_MASK) + +#define SRC_MIX_SLICE_FSM_STAT_ISO_STAT_MASK (0xF00U) +#define SRC_MIX_SLICE_FSM_STAT_ISO_STAT_SHIFT (8U) +/*! ISO_STAT - Isolation FSM status */ +#define SRC_MIX_SLICE_FSM_STAT_ISO_STAT(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIX_SLICE_FSM_STAT_ISO_STAT_SHIFT)) & SRC_MIX_SLICE_FSM_STAT_ISO_STAT_MASK) + +#define SRC_MIX_SLICE_FSM_STAT_MTR_STAT_MASK (0x7000U) +#define SRC_MIX_SLICE_FSM_STAT_MTR_STAT_SHIFT (12U) +/*! MTR_STAT - MTR FSM status */ +#define SRC_MIX_SLICE_FSM_STAT_MTR_STAT(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIX_SLICE_FSM_STAT_MTR_STAT_SHIFT)) & SRC_MIX_SLICE_FSM_STAT_MTR_STAT_MASK) + +#define SRC_MIX_SLICE_FSM_STAT_SSAR_STAT_MASK (0x70000U) +#define SRC_MIX_SLICE_FSM_STAT_SSAR_STAT_SHIFT (16U) +/*! SSAR_STAT - SSAR FSM status */ +#define SRC_MIX_SLICE_FSM_STAT_SSAR_STAT(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIX_SLICE_FSM_STAT_SSAR_STAT_SHIFT)) & SRC_MIX_SLICE_FSM_STAT_SSAR_STAT_MASK) + +#define SRC_MIX_SLICE_FSM_STAT_A55_HDSK_STAT_MASK (0xF00000U) +#define SRC_MIX_SLICE_FSM_STAT_A55_HDSK_STAT_SHIFT (20U) +/*! A55_HDSK_STAT - A55 handshake FSM status */ +#define SRC_MIX_SLICE_FSM_STAT_A55_HDSK_STAT(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIX_SLICE_FSM_STAT_A55_HDSK_STAT_SHIFT)) & SRC_MIX_SLICE_FSM_STAT_A55_HDSK_STAT_MASK) + +#define SRC_MIX_SLICE_FSM_STAT_MEM_STAT_MASK (0x7000000U) +#define SRC_MIX_SLICE_FSM_STAT_MEM_STAT_SHIFT (24U) +/*! MEM_STAT - Memory FSM status */ +#define SRC_MIX_SLICE_FSM_STAT_MEM_STAT(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIX_SLICE_FSM_STAT_MEM_STAT_SHIFT)) & SRC_MIX_SLICE_FSM_STAT_MEM_STAT_MASK) +/*! @} */ + +/*! @name FUNC_STAT - function status */ +/*! @{ */ + +#define SRC_MIX_SLICE_FUNC_STAT_PSW_STAT_MASK (0x1U) +#define SRC_MIX_SLICE_FUNC_STAT_PSW_STAT_SHIFT (0U) +/*! PSW_STAT - Power switch status + * 0b0..Power switch on + * 0b1..Power switch off + */ +#define SRC_MIX_SLICE_FUNC_STAT_PSW_STAT(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIX_SLICE_FUNC_STAT_PSW_STAT_SHIFT)) & SRC_MIX_SLICE_FUNC_STAT_PSW_STAT_MASK) + +#define SRC_MIX_SLICE_FUNC_STAT_RST_STAT_MASK (0x4U) +#define SRC_MIX_SLICE_FUNC_STAT_RST_STAT_SHIFT (2U) +/*! RST_STAT - Reset status + * 0b0..Reset assert + * 0b1..Reset release + */ +#define SRC_MIX_SLICE_FUNC_STAT_RST_STAT(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIX_SLICE_FUNC_STAT_RST_STAT_SHIFT)) & SRC_MIX_SLICE_FUNC_STAT_RST_STAT_MASK) + +#define SRC_MIX_SLICE_FUNC_STAT_ISO_STAT_MASK (0x10U) +#define SRC_MIX_SLICE_FUNC_STAT_ISO_STAT_SHIFT (4U) +/*! ISO_STAT - Isolation status + * 0b0..Isolation off + * 0b1..Isolation on + */ +#define SRC_MIX_SLICE_FUNC_STAT_ISO_STAT(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIX_SLICE_FUNC_STAT_ISO_STAT_SHIFT)) & SRC_MIX_SLICE_FUNC_STAT_ISO_STAT_MASK) + +#define SRC_MIX_SLICE_FUNC_STAT_MTR_STAT_MASK (0x40U) +#define SRC_MIX_SLICE_FUNC_STAT_MTR_STAT_SHIFT (6U) +/*! MTR_STAT - MTR status + * 0b0..No effect + * 0b1..Memory repair/trim done + */ +#define SRC_MIX_SLICE_FUNC_STAT_MTR_STAT(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIX_SLICE_FUNC_STAT_MTR_STAT_SHIFT)) & SRC_MIX_SLICE_FUNC_STAT_MTR_STAT_MASK) + +#define SRC_MIX_SLICE_FUNC_STAT_SSAR_STAT_MASK (0x100U) +#define SRC_MIX_SLICE_FUNC_STAT_SSAR_STAT_SHIFT (8U) +/*! SSAR_STAT - ssar status + * 0b0..No effect or power up handshake with Edgelock Enclave done + * 0b1..Power down handshake with Edgelock Enclave done + */ +#define SRC_MIX_SLICE_FUNC_STAT_SSAR_STAT(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIX_SLICE_FUNC_STAT_SSAR_STAT_SHIFT)) & SRC_MIX_SLICE_FUNC_STAT_SSAR_STAT_MASK) + +#define SRC_MIX_SLICE_FUNC_STAT_A55_HDSK_STAT_MASK (0x400U) +#define SRC_MIX_SLICE_FUNC_STAT_A55_HDSK_STAT_SHIFT (10U) +/*! A55_HDSK_STAT - A55 handshake status + * 0b0..No effect or power up handshake with A55 done(just for A55 SLICE) + * 0b1..Power down handshake with A55 done(just for A55 SLICE) + */ +#define SRC_MIX_SLICE_FUNC_STAT_A55_HDSK_STAT(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIX_SLICE_FUNC_STAT_A55_HDSK_STAT_SHIFT)) & SRC_MIX_SLICE_FUNC_STAT_A55_HDSK_STAT_MASK) + +#define SRC_MIX_SLICE_FUNC_STAT_MEM_STAT_MASK (0x1000U) +#define SRC_MIX_SLICE_FUNC_STAT_MEM_STAT_SHIFT (12U) +/*! MEM_STAT - Memory w/ status + * 0b0..No effect or memory w/ exit LP done + * 0b1..Memory w/ enter LP done + */ +#define SRC_MIX_SLICE_FUNC_STAT_MEM_STAT(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIX_SLICE_FUNC_STAT_MEM_STAT_SHIFT)) & SRC_MIX_SLICE_FUNC_STAT_MEM_STAT_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group SRC_MIX_SLICE_Register_Masks */ + + +/* SRC_MIX_SLICE - Peripheral instance base addresses */ +/** Peripheral SRC__SRC_A55C0_SLICE base address */ +#define SRC__SRC_A55C0_SLICE_BASE (0x44462C00u) +/** Peripheral SRC__SRC_A55C0_SLICE base pointer */ +#define SRC__SRC_A55C0_SLICE ((SRC_MIX_SLICE_Type *)SRC__SRC_A55C0_SLICE_BASE) +/** Peripheral SRC__SRC_A55P_SLICE base address */ +#define SRC__SRC_A55P_SLICE_BASE (0x44463400u) +/** Peripheral SRC__SRC_A55P_SLICE base pointer */ +#define SRC__SRC_A55P_SLICE ((SRC_MIX_SLICE_Type *)SRC__SRC_A55P_SLICE_BASE) +/** Peripheral SRC__SRC_AON_SLICE base address */ +#define SRC__SRC_AON_SLICE_BASE (0x44460800u) +/** Peripheral SRC__SRC_AON_SLICE base pointer */ +#define SRC__SRC_AON_SLICE ((SRC_MIX_SLICE_Type *)SRC__SRC_AON_SLICE_BASE) +/** Peripheral SRC__SRC_DDR_SLICE base address */ +#define SRC__SRC_DDR_SLICE_BASE (0x44461000u) +/** Peripheral SRC__SRC_DDR_SLICE base pointer */ +#define SRC__SRC_DDR_SLICE ((SRC_MIX_SLICE_Type *)SRC__SRC_DDR_SLICE_BASE) +/** Peripheral SRC__SRC_DPHY_SLICE base address */ +#define SRC__SRC_DPHY_SLICE_BASE (0x44461400u) +/** Peripheral SRC__SRC_DPHY_SLICE base pointer */ +#define SRC__SRC_DPHY_SLICE ((SRC_MIX_SLICE_Type *)SRC__SRC_DPHY_SLICE_BASE) +/** Peripheral SRC__SRC_EDGELOCK_SLICE base address */ +#define SRC__SRC_EDGELOCK_SLICE_BASE (0x44460400u) +/** Peripheral SRC__SRC_EDGELOCK_SLICE base pointer */ +#define SRC__SRC_EDGELOCK_SLICE ((SRC_MIX_SLICE_Type *)SRC__SRC_EDGELOCK_SLICE_BASE) +/** Peripheral SRC__SRC_HSIO_SLICE base address */ +#define SRC__SRC_HSIO_SLICE_BASE (0x44462000u) +/** Peripheral SRC__SRC_HSIO_SLICE base pointer */ +#define SRC__SRC_HSIO_SLICE ((SRC_MIX_SLICE_Type *)SRC__SRC_HSIO_SLICE_BASE) +/** Peripheral SRC__SRC_MEDIA_SLICE base address */ +#define SRC__SRC_MEDIA_SLICE_BASE (0x44462400u) +/** Peripheral SRC__SRC_MEDIA_SLICE base pointer */ +#define SRC__SRC_MEDIA_SLICE ((SRC_MIX_SLICE_Type *)SRC__SRC_MEDIA_SLICE_BASE) +/** Peripheral SRC__SRC_NIC_SLICE base address */ +#define SRC__SRC_NIC_SLICE_BASE (0x44461C00u) +/** Peripheral SRC__SRC_NIC_SLICE base pointer */ +#define SRC__SRC_NIC_SLICE ((SRC_MIX_SLICE_Type *)SRC__SRC_NIC_SLICE_BASE) +/** Peripheral SRC__SRC_WKUP_SLICE base address */ +#define SRC__SRC_WKUP_SLICE_BASE (0x44460C00u) +/** Peripheral SRC__SRC_WKUP_SLICE base pointer */ +#define SRC__SRC_WKUP_SLICE ((SRC_MIX_SLICE_Type *)SRC__SRC_WKUP_SLICE_BASE) +/** Array initializer of SRC_MIX_SLICE peripheral base addresses */ +#define SRC_MIX_SLICE_BASE_ADDRS { SRC__SRC_A55C0_SLICE_BASE, SRC__SRC_A55P_SLICE_BASE, SRC__SRC_AON_SLICE_BASE, SRC__SRC_DDR_SLICE_BASE, SRC__SRC_DPHY_SLICE_BASE, SRC__SRC_EDGELOCK_SLICE_BASE, SRC__SRC_HSIO_SLICE_BASE, SRC__SRC_MEDIA_SLICE_BASE, SRC__SRC_NIC_SLICE_BASE, SRC__SRC_WKUP_SLICE_BASE } +/** Array initializer of SRC_MIX_SLICE peripheral base pointers */ +#define SRC_MIX_SLICE_BASE_PTRS { SRC__SRC_A55C0_SLICE, SRC__SRC_A55P_SLICE, SRC__SRC_AON_SLICE, SRC__SRC_DDR_SLICE, SRC__SRC_DPHY_SLICE, SRC__SRC_EDGELOCK_SLICE, SRC__SRC_HSIO_SLICE, SRC__SRC_MEDIA_SLICE, SRC__SRC_NIC_SLICE, SRC__SRC_WKUP_SLICE } + +/*! + * @} + */ /* end of group SRC_MIX_SLICE_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- SYS_CTR_COMPARE Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SYS_CTR_COMPARE_Peripheral_Access_Layer SYS_CTR_COMPARE Peripheral Access Layer + * @{ + */ + +/** SYS_CTR_COMPARE - Register Layout Typedef */ +typedef struct { + uint8_t RESERVED_0[32]; + __IO uint32_t CMPCVL0; /**< Compare Count Value Low, offset: 0x20 */ + __IO uint32_t CMPCVH0; /**< Compare Count Value High, offset: 0x24 */ + uint8_t RESERVED_1[4]; + __IO uint32_t CMPCR0; /**< Compare Control, offset: 0x2C */ + uint8_t RESERVED_2[240]; + __IO uint32_t CMPCVL1; /**< Compare Count Value Low, offset: 0x120 */ + __IO uint32_t CMPCVH1; /**< Compare Count Value High, offset: 0x124 */ + uint8_t RESERVED_3[4]; + __IO uint32_t CMPCR1; /**< Compare Control, offset: 0x12C */ + uint8_t RESERVED_4[3744]; + __I uint32_t CNTID0; /**< Counter ID, offset: 0xFD0 */ +} SYS_CTR_COMPARE_Type; + +/* ---------------------------------------------------------------------------- + -- SYS_CTR_COMPARE Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SYS_CTR_COMPARE_Register_Masks SYS_CTR_COMPARE Register Masks + * @{ + */ + +/*! @name CMPCVL0 - Compare Count Value Low */ +/*! @{ */ + +#define SYS_CTR_COMPARE_CMPCVL0_CMPCV0_MASK (0xFFFFFFFFU) +#define SYS_CTR_COMPARE_CMPCVL0_CMPCV0_SHIFT (0U) +/*! CMPCV0 - Compare Count Value Bits [31:0] */ +#define SYS_CTR_COMPARE_CMPCVL0_CMPCV0(x) (((uint32_t)(((uint32_t)(x)) << SYS_CTR_COMPARE_CMPCVL0_CMPCV0_SHIFT)) & SYS_CTR_COMPARE_CMPCVL0_CMPCV0_MASK) +/*! @} */ + +/*! @name CMPCVH0 - Compare Count Value High */ +/*! @{ */ + +#define SYS_CTR_COMPARE_CMPCVH0_CMPCV1_MASK (0xFFFFFFU) +#define SYS_CTR_COMPARE_CMPCVH0_CMPCV1_SHIFT (0U) +/*! CMPCV1 - Compare Count Value Bits [55:32] */ +#define SYS_CTR_COMPARE_CMPCVH0_CMPCV1(x) (((uint32_t)(((uint32_t)(x)) << SYS_CTR_COMPARE_CMPCVH0_CMPCV1_SHIFT)) & SYS_CTR_COMPARE_CMPCVH0_CMPCV1_MASK) +/*! @} */ + +/*! @name CMPCR0 - Compare Control */ +/*! @{ */ + +#define SYS_CTR_COMPARE_CMPCR0_EN_MASK (0x1U) +#define SYS_CTR_COMPARE_CMPCR0_EN_SHIFT (0U) +/*! EN - Compare Enable + * 0b0..Disable + * 0b1..Enable + */ +#define SYS_CTR_COMPARE_CMPCR0_EN(x) (((uint32_t)(((uint32_t)(x)) << SYS_CTR_COMPARE_CMPCR0_EN_SHIFT)) & SYS_CTR_COMPARE_CMPCR0_EN_MASK) + +#define SYS_CTR_COMPARE_CMPCR0_IMASK_MASK (0x2U) +#define SYS_CTR_COMPARE_CMPCR0_IMASK_SHIFT (1U) +/*! IMASK - Interrupt Request Mask + * 0b0..Not masked + * 0b1..Masked + */ +#define SYS_CTR_COMPARE_CMPCR0_IMASK(x) (((uint32_t)(((uint32_t)(x)) << SYS_CTR_COMPARE_CMPCR0_IMASK_SHIFT)) & SYS_CTR_COMPARE_CMPCR0_IMASK_MASK) + +#define SYS_CTR_COMPARE_CMPCR0_ISTAT_MASK (0x4U) +#define SYS_CTR_COMPARE_CMPCR0_ISTAT_SHIFT (2U) +/*! ISTAT - Compare Interrupt Status + * 0b0..Either less than the compare value or compare is disabled + * 0b1..Greater than or equal to the compare value and compare is enabled + */ +#define SYS_CTR_COMPARE_CMPCR0_ISTAT(x) (((uint32_t)(((uint32_t)(x)) << SYS_CTR_COMPARE_CMPCR0_ISTAT_SHIFT)) & SYS_CTR_COMPARE_CMPCR0_ISTAT_MASK) +/*! @} */ + +/*! @name CMPCVL1 - Compare Count Value Low */ +/*! @{ */ + +#define SYS_CTR_COMPARE_CMPCVL1_CMPCV0_MASK (0xFFFFFFFFU) +#define SYS_CTR_COMPARE_CMPCVL1_CMPCV0_SHIFT (0U) +/*! CMPCV0 - Compare Count Value Bits [31:0] */ +#define SYS_CTR_COMPARE_CMPCVL1_CMPCV0(x) (((uint32_t)(((uint32_t)(x)) << SYS_CTR_COMPARE_CMPCVL1_CMPCV0_SHIFT)) & SYS_CTR_COMPARE_CMPCVL1_CMPCV0_MASK) +/*! @} */ + +/*! @name CMPCVH1 - Compare Count Value High */ +/*! @{ */ + +#define SYS_CTR_COMPARE_CMPCVH1_CMPCV1_MASK (0xFFFFFFU) +#define SYS_CTR_COMPARE_CMPCVH1_CMPCV1_SHIFT (0U) +/*! CMPCV1 - Compare Count Value Bits [55:32] */ +#define SYS_CTR_COMPARE_CMPCVH1_CMPCV1(x) (((uint32_t)(((uint32_t)(x)) << SYS_CTR_COMPARE_CMPCVH1_CMPCV1_SHIFT)) & SYS_CTR_COMPARE_CMPCVH1_CMPCV1_MASK) +/*! @} */ + +/*! @name CMPCR1 - Compare Control */ +/*! @{ */ + +#define SYS_CTR_COMPARE_CMPCR1_EN_MASK (0x1U) +#define SYS_CTR_COMPARE_CMPCR1_EN_SHIFT (0U) +/*! EN - Compare Enable + * 0b0..Disable + * 0b1..Enable + */ +#define SYS_CTR_COMPARE_CMPCR1_EN(x) (((uint32_t)(((uint32_t)(x)) << SYS_CTR_COMPARE_CMPCR1_EN_SHIFT)) & SYS_CTR_COMPARE_CMPCR1_EN_MASK) + +#define SYS_CTR_COMPARE_CMPCR1_IMASK_MASK (0x2U) +#define SYS_CTR_COMPARE_CMPCR1_IMASK_SHIFT (1U) +/*! IMASK - Interrupt Request Mask + * 0b0..Not masked + * 0b1..Masked + */ +#define SYS_CTR_COMPARE_CMPCR1_IMASK(x) (((uint32_t)(((uint32_t)(x)) << SYS_CTR_COMPARE_CMPCR1_IMASK_SHIFT)) & SYS_CTR_COMPARE_CMPCR1_IMASK_MASK) + +#define SYS_CTR_COMPARE_CMPCR1_ISTAT_MASK (0x4U) +#define SYS_CTR_COMPARE_CMPCR1_ISTAT_SHIFT (2U) +/*! ISTAT - Compare Interrupt Status + * 0b0..Either less than the compare value or compare is disabled + * 0b1..Greater than or equal to the compare value and compare is enabled + */ +#define SYS_CTR_COMPARE_CMPCR1_ISTAT(x) (((uint32_t)(((uint32_t)(x)) << SYS_CTR_COMPARE_CMPCR1_ISTAT_SHIFT)) & SYS_CTR_COMPARE_CMPCR1_ISTAT_MASK) +/*! @} */ + +/*! @name CNTID0 - Counter ID */ +/*! @{ */ + +#define SYS_CTR_COMPARE_CNTID0_CNTID_MASK (0xFFFFFFFFU) +#define SYS_CTR_COMPARE_CNTID0_CNTID_SHIFT (0U) +/*! CNTID - Counter Identification */ +#define SYS_CTR_COMPARE_CNTID0_CNTID(x) (((uint32_t)(((uint32_t)(x)) << SYS_CTR_COMPARE_CNTID0_CNTID_SHIFT)) & SYS_CTR_COMPARE_CNTID0_CNTID_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group SYS_CTR_COMPARE_Register_Masks */ + + +/* SYS_CTR_COMPARE - Peripheral instance base addresses */ +/** Peripheral SYS_CTR_CTLBASE1__SYS_CTR_COMPARE base address */ +#define SYS_CTR_CTLBASE1__SYS_CTR_COMPARE_BASE (0x442A0000u) +/** Peripheral SYS_CTR_CTLBASE1__SYS_CTR_COMPARE base pointer */ +#define SYS_CTR_CTLBASE1__SYS_CTR_COMPARE ((SYS_CTR_COMPARE_Type *)SYS_CTR_CTLBASE1__SYS_CTR_COMPARE_BASE) +/** Array initializer of SYS_CTR_COMPARE peripheral base addresses */ +#define SYS_CTR_COMPARE_BASE_ADDRS { SYS_CTR_CTLBASE1__SYS_CTR_COMPARE_BASE } +/** Array initializer of SYS_CTR_COMPARE peripheral base pointers */ +#define SYS_CTR_COMPARE_BASE_PTRS { SYS_CTR_CTLBASE1__SYS_CTR_COMPARE } + +/*! + * @} + */ /* end of group SYS_CTR_COMPARE_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- SYS_CTR_CONTROL Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SYS_CTR_CONTROL_Peripheral_Access_Layer SYS_CTR_CONTROL Peripheral Access Layer + * @{ + */ + +/** SYS_CTR_CONTROL - Register Layout Typedef */ +typedef struct { + __IO uint32_t CNTCR; /**< Counter Control, offset: 0x0 */ + __I uint32_t CNTSR; /**< Counter Status, offset: 0x4 */ + __IO uint32_t CNTCV0; /**< Counter Count Value Low, offset: 0x8 */ + __IO uint32_t CNTCV1; /**< Counter Count Value High, offset: 0xC */ + uint8_t RESERVED_0[16]; + __I uint32_t CNTFID0; /**< Frequency-Modes Table 0, offset: 0x20 */ + __I uint32_t CNTFID1; /**< Frequency-Modes Table 1, offset: 0x24 */ + __I uint32_t CNTFID2; /**< Frequency-Modes Table 2, offset: 0x28 */ + uint8_t RESERVED_1[148]; + __IO uint32_t CNTCR2; /**< Counter Control 2, offset: 0xC0 */ + uint8_t RESERVED_2[3852]; + __I uint32_t CNTID0; /**< Counter ID, offset: 0xFD0 */ +} SYS_CTR_CONTROL_Type; + +/* ---------------------------------------------------------------------------- + -- SYS_CTR_CONTROL Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SYS_CTR_CONTROL_Register_Masks SYS_CTR_CONTROL Register Masks + * @{ + */ + +/*! @name CNTCR - Counter Control */ +/*! @{ */ + +#define SYS_CTR_CONTROL_CNTCR_EN_MASK (0x1U) +#define SYS_CTR_CONTROL_CNTCR_EN_SHIFT (0U) +/*! EN - Enable Counting + * 0b0..Disable + * 0b1..Enable + */ +#define SYS_CTR_CONTROL_CNTCR_EN(x) (((uint32_t)(((uint32_t)(x)) << SYS_CTR_CONTROL_CNTCR_EN_SHIFT)) & SYS_CTR_CONTROL_CNTCR_EN_MASK) + +#define SYS_CTR_CONTROL_CNTCR_HDBG_MASK (0x2U) +#define SYS_CTR_CONTROL_CNTCR_HDBG_SHIFT (1U) +/*! HDBG - Enable Debug Halt + * 0b0..Ignored + * 0b1..Causes SYS_CTR to halt + */ +#define SYS_CTR_CONTROL_CNTCR_HDBG(x) (((uint32_t)(((uint32_t)(x)) << SYS_CTR_CONTROL_CNTCR_HDBG_SHIFT)) & SYS_CTR_CONTROL_CNTCR_HDBG_MASK) + +#define SYS_CTR_CONTROL_CNTCR_FCR0_MASK (0x100U) +#define SYS_CTR_CONTROL_CNTCR_FCR0_SHIFT (8U) +/*! FCR0 - Frequency Change Request, ID 0 + * 0b0..No change + * 0b1..Base frequency + */ +#define SYS_CTR_CONTROL_CNTCR_FCR0(x) (((uint32_t)(((uint32_t)(x)) << SYS_CTR_CONTROL_CNTCR_FCR0_SHIFT)) & SYS_CTR_CONTROL_CNTCR_FCR0_MASK) + +#define SYS_CTR_CONTROL_CNTCR_FCR1_MASK (0x200U) +#define SYS_CTR_CONTROL_CNTCR_FCR1_SHIFT (9U) +/*! FCR1 - Frequency Change Request, ID 1 + * 0b0..No change + * 0b1..Alternate frequency + */ +#define SYS_CTR_CONTROL_CNTCR_FCR1(x) (((uint32_t)(((uint32_t)(x)) << SYS_CTR_CONTROL_CNTCR_FCR1_SHIFT)) & SYS_CTR_CONTROL_CNTCR_FCR1_MASK) +/*! @} */ + +/*! @name CNTSR - Counter Status */ +/*! @{ */ + +#define SYS_CTR_CONTROL_CNTSR_DBGH_MASK (0x1U) +#define SYS_CTR_CONTROL_CNTSR_DBGH_SHIFT (0U) +/*! DBGH - Debug Halt + * 0b0..Did not halt + * 0b1..Halted + */ +#define SYS_CTR_CONTROL_CNTSR_DBGH(x) (((uint32_t)(((uint32_t)(x)) << SYS_CTR_CONTROL_CNTSR_DBGH_SHIFT)) & SYS_CTR_CONTROL_CNTSR_DBGH_MASK) + +#define SYS_CTR_CONTROL_CNTSR_FCA0_MASK (0x100U) +#define SYS_CTR_CONTROL_CNTSR_FCA0_SHIFT (8U) +/*! FCA0 - Frequency Change Acknowledge, ID 0 + * 0b0..Not selected + * 0b1..Selected + */ +#define SYS_CTR_CONTROL_CNTSR_FCA0(x) (((uint32_t)(((uint32_t)(x)) << SYS_CTR_CONTROL_CNTSR_FCA0_SHIFT)) & SYS_CTR_CONTROL_CNTSR_FCA0_MASK) + +#define SYS_CTR_CONTROL_CNTSR_FCA1_MASK (0x200U) +#define SYS_CTR_CONTROL_CNTSR_FCA1_SHIFT (9U) +/*! FCA1 - Frequency Change Acknowledge, ID 1 + * 0b0..Not selected + * 0b1..Selected + */ +#define SYS_CTR_CONTROL_CNTSR_FCA1(x) (((uint32_t)(((uint32_t)(x)) << SYS_CTR_CONTROL_CNTSR_FCA1_SHIFT)) & SYS_CTR_CONTROL_CNTSR_FCA1_MASK) +/*! @} */ + +/*! @name CNTCV0 - Counter Count Value Low */ +/*! @{ */ + +#define SYS_CTR_CONTROL_CNTCV0_CNTCV0_MASK (0xFFFFFFFFU) +#define SYS_CTR_CONTROL_CNTCV0_CNTCV0_SHIFT (0U) +/*! CNTCV0 - Counter Count Value Bits [31:0] */ +#define SYS_CTR_CONTROL_CNTCV0_CNTCV0(x) (((uint32_t)(((uint32_t)(x)) << SYS_CTR_CONTROL_CNTCV0_CNTCV0_SHIFT)) & SYS_CTR_CONTROL_CNTCV0_CNTCV0_MASK) +/*! @} */ + +/*! @name CNTCV1 - Counter Count Value High */ +/*! @{ */ + +#define SYS_CTR_CONTROL_CNTCV1_CNTCV1_MASK (0xFFFFFFU) +#define SYS_CTR_CONTROL_CNTCV1_CNTCV1_SHIFT (0U) +/*! CNTCV1 - Counter Count Value Bits [55:32] */ +#define SYS_CTR_CONTROL_CNTCV1_CNTCV1(x) (((uint32_t)(((uint32_t)(x)) << SYS_CTR_CONTROL_CNTCV1_CNTCV1_SHIFT)) & SYS_CTR_CONTROL_CNTCV1_CNTCV1_MASK) +/*! @} */ + +/*! @name CNTFID0 - Frequency-Modes Table 0 */ +/*! @{ */ + +#define SYS_CTR_CONTROL_CNTFID0_CNTFID0_MASK (0xFFFFFFFFU) +#define SYS_CTR_CONTROL_CNTFID0_CNTFID0_SHIFT (0U) +/*! CNTFID0 - Counter Frequency ID 0 */ +#define SYS_CTR_CONTROL_CNTFID0_CNTFID0(x) (((uint32_t)(((uint32_t)(x)) << SYS_CTR_CONTROL_CNTFID0_CNTFID0_SHIFT)) & SYS_CTR_CONTROL_CNTFID0_CNTFID0_MASK) +/*! @} */ + +/*! @name CNTFID1 - Frequency-Modes Table 1 */ +/*! @{ */ + +#define SYS_CTR_CONTROL_CNTFID1_CNTFID1_MASK (0xFFFFFFFFU) +#define SYS_CTR_CONTROL_CNTFID1_CNTFID1_SHIFT (0U) +/*! CNTFID1 - Counter Frequency ID 1 */ +#define SYS_CTR_CONTROL_CNTFID1_CNTFID1(x) (((uint32_t)(((uint32_t)(x)) << SYS_CTR_CONTROL_CNTFID1_CNTFID1_SHIFT)) & SYS_CTR_CONTROL_CNTFID1_CNTFID1_MASK) +/*! @} */ + +/*! @name CNTFID2 - Frequency-Modes Table 2 */ +/*! @{ */ + +#define SYS_CTR_CONTROL_CNTFID2_CNTFID2_MASK (0xFFFFFFFFU) +#define SYS_CTR_CONTROL_CNTFID2_CNTFID2_SHIFT (0U) +/*! CNTFID2 - Counter Frequency ID 2 */ +#define SYS_CTR_CONTROL_CNTFID2_CNTFID2(x) (((uint32_t)(((uint32_t)(x)) << SYS_CTR_CONTROL_CNTFID2_CNTFID2_SHIFT)) & SYS_CTR_CONTROL_CNTFID2_CNTFID2_MASK) +/*! @} */ + +/*! @name CNTCR2 - Counter Control 2 */ +/*! @{ */ + +#define SYS_CTR_CONTROL_CNTCR2_HWFC_EN_MASK (0x1U) +#define SYS_CTR_CONTROL_CNTCR2_HWFC_EN_SHIFT (0U) +/*! HWFC_EN - Hardware Frequency Change Enable + * 0b0..No effect + * 0b1..Same as performed via software + */ +#define SYS_CTR_CONTROL_CNTCR2_HWFC_EN(x) (((uint32_t)(((uint32_t)(x)) << SYS_CTR_CONTROL_CNTCR2_HWFC_EN_SHIFT)) & SYS_CTR_CONTROL_CNTCR2_HWFC_EN_MASK) +/*! @} */ + +/*! @name CNTID0 - Counter ID */ +/*! @{ */ + +#define SYS_CTR_CONTROL_CNTID0_CNTID_MASK (0xFFFFFFFFU) +#define SYS_CTR_CONTROL_CNTID0_CNTID_SHIFT (0U) +/*! CNTID - Counter Identification */ +#define SYS_CTR_CONTROL_CNTID0_CNTID(x) (((uint32_t)(((uint32_t)(x)) << SYS_CTR_CONTROL_CNTID0_CNTID_SHIFT)) & SYS_CTR_CONTROL_CNTID0_CNTID_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group SYS_CTR_CONTROL_Register_Masks */ + + +/* SYS_CTR_CONTROL - Peripheral instance base addresses */ +/** Peripheral SYS_CTR_CTLBASE1__SYS_CTR_CONTROL base address */ +#define SYS_CTR_CTLBASE1__SYS_CTR_CONTROL_BASE (0x44290000u) +/** Peripheral SYS_CTR_CTLBASE1__SYS_CTR_CONTROL base pointer */ +#define SYS_CTR_CTLBASE1__SYS_CTR_CONTROL ((SYS_CTR_CONTROL_Type *)SYS_CTR_CTLBASE1__SYS_CTR_CONTROL_BASE) +/** Array initializer of SYS_CTR_CONTROL peripheral base addresses */ +#define SYS_CTR_CONTROL_BASE_ADDRS { SYS_CTR_CTLBASE1__SYS_CTR_CONTROL_BASE } +/** Array initializer of SYS_CTR_CONTROL peripheral base pointers */ +#define SYS_CTR_CONTROL_BASE_PTRS { SYS_CTR_CTLBASE1__SYS_CTR_CONTROL } + +/*! + * @} + */ /* end of group SYS_CTR_CONTROL_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- SYS_CTR_READ Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SYS_CTR_READ_Peripheral_Access_Layer SYS_CTR_READ Peripheral Access Layer + * @{ + */ + +/** SYS_CTR_READ - Register Layout Typedef */ +typedef struct { + uint8_t RESERVED_0[8]; + __I uint32_t CNTCV0; /**< Counter Count Value Low, offset: 0x8 */ + __I uint32_t CNTCV1; /**< Counter Count Value High, offset: 0xC */ + uint8_t RESERVED_1[4032]; + __I uint32_t CNTID0; /**< Counter ID, offset: 0xFD0 */ +} SYS_CTR_READ_Type; + +/* ---------------------------------------------------------------------------- + -- SYS_CTR_READ Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SYS_CTR_READ_Register_Masks SYS_CTR_READ Register Masks + * @{ + */ + +/*! @name CNTCV0 - Counter Count Value Low */ +/*! @{ */ + +#define SYS_CTR_READ_CNTCV0_CNTCV0_MASK (0xFFFFFFFFU) +#define SYS_CTR_READ_CNTCV0_CNTCV0_SHIFT (0U) +/*! CNTCV0 - Counter Count Value Bits [31:0] */ +#define SYS_CTR_READ_CNTCV0_CNTCV0(x) (((uint32_t)(((uint32_t)(x)) << SYS_CTR_READ_CNTCV0_CNTCV0_SHIFT)) & SYS_CTR_READ_CNTCV0_CNTCV0_MASK) +/*! @} */ + +/*! @name CNTCV1 - Counter Count Value High */ +/*! @{ */ + +#define SYS_CTR_READ_CNTCV1_CNTCV1_MASK (0xFFFFFFU) +#define SYS_CTR_READ_CNTCV1_CNTCV1_SHIFT (0U) +/*! CNTCV1 - Counter Count Value Bits [55:32] */ +#define SYS_CTR_READ_CNTCV1_CNTCV1(x) (((uint32_t)(((uint32_t)(x)) << SYS_CTR_READ_CNTCV1_CNTCV1_SHIFT)) & SYS_CTR_READ_CNTCV1_CNTCV1_MASK) +/*! @} */ + +/*! @name CNTID0 - Counter ID */ +/*! @{ */ + +#define SYS_CTR_READ_CNTID0_CNTID_MASK (0xFFFFFFFFU) +#define SYS_CTR_READ_CNTID0_CNTID_SHIFT (0U) +/*! CNTID - Counter Identification */ +#define SYS_CTR_READ_CNTID0_CNTID(x) (((uint32_t)(((uint32_t)(x)) << SYS_CTR_READ_CNTID0_CNTID_SHIFT)) & SYS_CTR_READ_CNTID0_CNTID_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group SYS_CTR_READ_Register_Masks */ + + +/* SYS_CTR_READ - Peripheral instance base addresses */ +/** Peripheral SYS_CTR_CTLBASE1__SYS_CTR_READ base address */ +#define SYS_CTR_CTLBASE1__SYS_CTR_READ_BASE (0x442B0000u) +/** Peripheral SYS_CTR_CTLBASE1__SYS_CTR_READ base pointer */ +#define SYS_CTR_CTLBASE1__SYS_CTR_READ ((SYS_CTR_READ_Type *)SYS_CTR_CTLBASE1__SYS_CTR_READ_BASE) +/** Array initializer of SYS_CTR_READ peripheral base addresses */ +#define SYS_CTR_READ_BASE_ADDRS { SYS_CTR_CTLBASE1__SYS_CTR_READ_BASE } +/** Array initializer of SYS_CTR_READ peripheral base pointers */ +#define SYS_CTR_READ_BASE_PTRS { SYS_CTR_CTLBASE1__SYS_CTR_READ } + +/*! + * @} + */ /* end of group SYS_CTR_READ_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- TCD Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup TCD_Peripheral_Access_Layer TCD Peripheral Access Layer + * @{ + */ + +/** TCD - Register Layout Typedef */ +typedef struct { + struct { /* offset: 0x0, array step: 0x10000 */ + __IO uint32_t CH_CSR; /**< Channel Control and Status, array offset: 0x0, array step: 0x10000 */ + __IO uint32_t CH_ES; /**< Channel Error Status, array offset: 0x4, array step: 0x10000 */ + __IO uint32_t CH_INT; /**< Channel Interrupt Status, array offset: 0x8, array step: 0x10000 */ + __IO uint32_t CH_SBR; /**< Channel System Bus, array offset: 0xC, array step: 0x10000 */ + __IO uint32_t CH_PRI; /**< Channel Priority, array offset: 0x10, array step: 0x10000 */ + uint8_t RESERVED_0[12]; + __IO uint32_t TCD_SADDR; /**< TCD Source Address, array offset: 0x20, array step: 0x10000 */ + __IO uint16_t TCD_SOFF; /**< TCD Signed Source Address Offset, array offset: 0x24, array step: 0x10000 */ + __IO uint16_t TCD_ATTR; /**< TCD Transfer Attributes, array offset: 0x26, array step: 0x10000 */ + union { /* offset: 0x28, array step: 0x10000 */ + __IO uint32_t TCD_NBYTES_MLOFFNO; /**< TCD Transfer Size Without Minor Loop Offsets, array offset: 0x28, array step: 0x10000 */ + __IO uint32_t TCD_NBYTES_MLOFFYES; /**< TCD Transfer Size with Minor Loop Offsets, array offset: 0x28, array step: 0x10000 */ + }; + __IO uint32_t TCD_SLAST_SDA; /**< TCD Last Source Address Adjustment / Store DADDR Address, array offset: 0x2C, array step: 0x10000 */ + __IO uint32_t TCD_DADDR; /**< TCD Destination Address, array offset: 0x30, array step: 0x10000 */ + __IO uint16_t TCD_DOFF; /**< TCD Signed Destination Address Offset, array offset: 0x34, array step: 0x10000 */ + union { /* offset: 0x36, array step: 0x10000 */ + __IO uint16_t TCD_CITER_ELINKNO; /**< TCD Current Major Loop Count (Minor Loop Channel Linking Disabled), array offset: 0x36, array step: 0x10000 */ + __IO uint16_t TCD_CITER_ELINKYES; /**< TCD Current Major Loop Count (Minor Loop Channel Linking Enabled), array offset: 0x36, array step: 0x10000 */ + }; + __IO uint32_t TCD_DLAST_SGA; /**< TCD Last Destination Address Adjustment / Scatter Gather Address, array offset: 0x38, array step: 0x10000 */ + __IO uint16_t TCD_CSR; /**< TCD Control and Status, array offset: 0x3C, array step: 0x10000 */ + union { /* offset: 0x3E, array step: 0x10000 */ + __IO uint16_t TCD_BITER_ELINKNO; /**< TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled), array offset: 0x3E, array step: 0x10000 */ + __IO uint16_t TCD_BITER_ELINKYES; /**< TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled), array offset: 0x3E, array step: 0x10000 */ + }; + uint8_t RESERVED_1[65472]; + } CH[31]; +} TCD_Type; + +/* ---------------------------------------------------------------------------- + -- TCD Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup TCD_Register_Masks TCD Register Masks + * @{ + */ + +/*! @name CH_CSR - Channel Control and Status */ +/*! @{ */ + +#define TCD_CH_CSR_ERQ_MASK (0x1U) +#define TCD_CH_CSR_ERQ_SHIFT (0U) +/*! ERQ - Enable DMA Request + * 0b0..DMA hardware request signal for corresponding channel disabled + * 0b1..DMA hardware request signal for corresponding channel enabled + */ +#define TCD_CH_CSR_ERQ(x) (((uint32_t)(((uint32_t)(x)) << TCD_CH_CSR_ERQ_SHIFT)) & TCD_CH_CSR_ERQ_MASK) + +#define TCD_CH_CSR_EARQ_MASK (0x2U) +#define TCD_CH_CSR_EARQ_SHIFT (1U) +/*! EARQ - Enable Asynchronous DMA Request + * 0b0..Disable asynchronous DMA request for the channel + * 0b1..Enable asynchronous DMA request for the channel + */ +#define TCD_CH_CSR_EARQ(x) (((uint32_t)(((uint32_t)(x)) << TCD_CH_CSR_EARQ_SHIFT)) & TCD_CH_CSR_EARQ_MASK) + +#define TCD_CH_CSR_EEI_MASK (0x4U) +#define TCD_CH_CSR_EEI_SHIFT (2U) +/*! EEI - Enable Error Interrupt + * 0b0..Error signal for corresponding channel does not generate error interrupt + * 0b1..Assertion of error signal for corresponding channel generates error interrupt request + */ +#define TCD_CH_CSR_EEI(x) (((uint32_t)(((uint32_t)(x)) << TCD_CH_CSR_EEI_SHIFT)) & TCD_CH_CSR_EEI_MASK) + +#define TCD_CH_CSR_EBW_MASK (0x8U) +#define TCD_CH_CSR_EBW_SHIFT (3U) +/*! EBW - Enable Buffered Writes + * 0b0..Buffered writes on system bus disabled + * 0b1..Buffered writes on system bus enabled + */ +#define TCD_CH_CSR_EBW(x) (((uint32_t)(((uint32_t)(x)) << TCD_CH_CSR_EBW_SHIFT)) & TCD_CH_CSR_EBW_MASK) + +#define TCD_CH_CSR_DONE_MASK (0x40000000U) +#define TCD_CH_CSR_DONE_SHIFT (30U) +/*! DONE - Channel Done */ +#define TCD_CH_CSR_DONE(x) (((uint32_t)(((uint32_t)(x)) << TCD_CH_CSR_DONE_SHIFT)) & TCD_CH_CSR_DONE_MASK) + +#define TCD_CH_CSR_ACTIVE_MASK (0x80000000U) +#define TCD_CH_CSR_ACTIVE_SHIFT (31U) +/*! ACTIVE - Channel Active */ +#define TCD_CH_CSR_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << TCD_CH_CSR_ACTIVE_SHIFT)) & TCD_CH_CSR_ACTIVE_MASK) +/*! @} */ + +/* The count of TCD_CH_CSR */ +#define TCD_CH_CSR_COUNT (31U) + +/*! @name CH_ES - Channel Error Status */ +/*! @{ */ + +#define TCD_CH_ES_DBE_MASK (0x1U) +#define TCD_CH_ES_DBE_SHIFT (0U) +/*! DBE - Destination Bus Error + * 0b0..No destination bus error + * 0b1..Last recorded error was bus error on destination write + */ +#define TCD_CH_ES_DBE(x) (((uint32_t)(((uint32_t)(x)) << TCD_CH_ES_DBE_SHIFT)) & TCD_CH_ES_DBE_MASK) + +#define TCD_CH_ES_SBE_MASK (0x2U) +#define TCD_CH_ES_SBE_SHIFT (1U) +/*! SBE - Source Bus Error + * 0b0..No source bus error + * 0b1..Last recorded error was bus error on source read + */ +#define TCD_CH_ES_SBE(x) (((uint32_t)(((uint32_t)(x)) << TCD_CH_ES_SBE_SHIFT)) & TCD_CH_ES_SBE_MASK) + +#define TCD_CH_ES_SGE_MASK (0x4U) +#define TCD_CH_ES_SGE_SHIFT (2U) +/*! SGE - Scatter/Gather Configuration Error + * 0b0..No scatter/gather configuration error + * 0b1..Last recorded error was a configuration error detected in the TCDn_DLAST_SGA field + */ +#define TCD_CH_ES_SGE(x) (((uint32_t)(((uint32_t)(x)) << TCD_CH_ES_SGE_SHIFT)) & TCD_CH_ES_SGE_MASK) + +#define TCD_CH_ES_NCE_MASK (0x8U) +#define TCD_CH_ES_NCE_SHIFT (3U) +/*! NCE - NBYTES/CITER Configuration Error + * 0b0..No NBYTES/CITER configuration error + * 0b1..Last recorded error was a configuration error detected in the TCDn_NBYTES or TCDn_CITER fields + */ +#define TCD_CH_ES_NCE(x) (((uint32_t)(((uint32_t)(x)) << TCD_CH_ES_NCE_SHIFT)) & TCD_CH_ES_NCE_MASK) + +#define TCD_CH_ES_DOE_MASK (0x10U) +#define TCD_CH_ES_DOE_SHIFT (4U) +/*! DOE - Destination Offset Error + * 0b0..No destination offset configuration error + * 0b1..Last recorded error was a configuration error detected in the TCDn_DOFF field + */ +#define TCD_CH_ES_DOE(x) (((uint32_t)(((uint32_t)(x)) << TCD_CH_ES_DOE_SHIFT)) & TCD_CH_ES_DOE_MASK) + +#define TCD_CH_ES_DAE_MASK (0x20U) +#define TCD_CH_ES_DAE_SHIFT (5U) +/*! DAE - Destination Address Error + * 0b0..No destination address configuration error + * 0b1..Last recorded error was a configuration error detected in the TCDn_DADDR field + */ +#define TCD_CH_ES_DAE(x) (((uint32_t)(((uint32_t)(x)) << TCD_CH_ES_DAE_SHIFT)) & TCD_CH_ES_DAE_MASK) + +#define TCD_CH_ES_SOE_MASK (0x40U) +#define TCD_CH_ES_SOE_SHIFT (6U) +/*! SOE - Source Offset Error + * 0b0..No source offset configuration error + * 0b1..Last recorded error was a configuration error detected in the TCDn_SOFF field + */ +#define TCD_CH_ES_SOE(x) (((uint32_t)(((uint32_t)(x)) << TCD_CH_ES_SOE_SHIFT)) & TCD_CH_ES_SOE_MASK) + +#define TCD_CH_ES_SAE_MASK (0x80U) +#define TCD_CH_ES_SAE_SHIFT (7U) +/*! SAE - Source Address Error + * 0b0..No source address configuration error + * 0b1..Last recorded error was a configuration error detected in the TCDn_SADDR field + */ +#define TCD_CH_ES_SAE(x) (((uint32_t)(((uint32_t)(x)) << TCD_CH_ES_SAE_SHIFT)) & TCD_CH_ES_SAE_MASK) + +#define TCD_CH_ES_ERR_MASK (0x80000000U) +#define TCD_CH_ES_ERR_SHIFT (31U) +/*! ERR - Error In Channel + * 0b0..An error in this channel has not occurred + * 0b1..An error in this channel has occurred + */ +#define TCD_CH_ES_ERR(x) (((uint32_t)(((uint32_t)(x)) << TCD_CH_ES_ERR_SHIFT)) & TCD_CH_ES_ERR_MASK) +/*! @} */ + +/* The count of TCD_CH_ES */ +#define TCD_CH_ES_COUNT (31U) + +/*! @name CH_INT - Channel Interrupt Status */ +/*! @{ */ + +#define TCD_CH_INT_INT_MASK (0x1U) +#define TCD_CH_INT_INT_SHIFT (0U) +/*! INT - Interrupt Request + * 0b0..Interrupt request for corresponding channel cleared + * 0b1..Interrupt request for corresponding channel active + */ +#define TCD_CH_INT_INT(x) (((uint32_t)(((uint32_t)(x)) << TCD_CH_INT_INT_SHIFT)) & TCD_CH_INT_INT_MASK) +/*! @} */ + +/* The count of TCD_CH_INT */ +#define TCD_CH_INT_COUNT (31U) + +/*! @name CH_SBR - Channel System Bus */ +/*! @{ */ + +#define TCD_CH_SBR_MID_MASK (0xFU) +#define TCD_CH_SBR_MID_SHIFT (0U) +/*! MID - Master ID */ +#define TCD_CH_SBR_MID(x) (((uint32_t)(((uint32_t)(x)) << TCD_CH_SBR_MID_SHIFT)) & TCD_CH_SBR_MID_MASK) + +#define TCD_CH_SBR_SEC_MASK (0x4000U) +#define TCD_CH_SBR_SEC_SHIFT (14U) +/*! SEC - Security Level + * 0b0..Nonsecure protection level for DMA transfers + * 0b1..Secure protection level for DMA transfers + */ +#define TCD_CH_SBR_SEC(x) (((uint32_t)(((uint32_t)(x)) << TCD_CH_SBR_SEC_SHIFT)) & TCD_CH_SBR_SEC_MASK) + +#define TCD_CH_SBR_PAL_MASK (0x8000U) +#define TCD_CH_SBR_PAL_SHIFT (15U) +/*! PAL - Privileged Access Level + * 0b0..User protection level for DMA transfers + * 0b1..Privileged protection level for DMA transfers + */ +#define TCD_CH_SBR_PAL(x) (((uint32_t)(((uint32_t)(x)) << TCD_CH_SBR_PAL_SHIFT)) & TCD_CH_SBR_PAL_MASK) + +#define TCD_CH_SBR_EMI_MASK (0x10000U) +#define TCD_CH_SBR_EMI_SHIFT (16U) +/*! EMI - Enable Master ID Replication + * 0b0..Master ID replication is disabled + * 0b1..Master ID replication is enabled + */ +#define TCD_CH_SBR_EMI(x) (((uint32_t)(((uint32_t)(x)) << TCD_CH_SBR_EMI_SHIFT)) & TCD_CH_SBR_EMI_MASK) + +#define TCD_CH_SBR_ATTR_MASK (0x7E0000U) +#define TCD_CH_SBR_ATTR_SHIFT (17U) +/*! ATTR - Attribute Output */ +#define TCD_CH_SBR_ATTR(x) (((uint32_t)(((uint32_t)(x)) << TCD_CH_SBR_ATTR_SHIFT)) & TCD_CH_SBR_ATTR_MASK) +/*! @} */ + +/* The count of TCD_CH_SBR */ +#define TCD_CH_SBR_COUNT (31U) + +/*! @name CH_PRI - Channel Priority */ +/*! @{ */ + +#define TCD_CH_PRI_APL_MASK (0x7U) +#define TCD_CH_PRI_APL_SHIFT (0U) +/*! APL - Arbitration Priority Level */ +#define TCD_CH_PRI_APL(x) (((uint32_t)(((uint32_t)(x)) << TCD_CH_PRI_APL_SHIFT)) & TCD_CH_PRI_APL_MASK) + +#define TCD_CH_PRI_DPA_MASK (0x40000000U) +#define TCD_CH_PRI_DPA_SHIFT (30U) +/*! DPA - Disable Preempt Ability + * 0b0..Channel can suspend a lower-priority channel + * 0b1..Channel cannot suspend any other channel, regardless of channel priority + */ +#define TCD_CH_PRI_DPA(x) (((uint32_t)(((uint32_t)(x)) << TCD_CH_PRI_DPA_SHIFT)) & TCD_CH_PRI_DPA_MASK) + +#define TCD_CH_PRI_ECP_MASK (0x80000000U) +#define TCD_CH_PRI_ECP_SHIFT (31U) +/*! ECP - Enable Channel Preemption + * 0b0..Channel cannot be suspended by a higher-priority channel's service request + * 0b1..Channel can be temporarily suspended by a higher-priority channel's service request + */ +#define TCD_CH_PRI_ECP(x) (((uint32_t)(((uint32_t)(x)) << TCD_CH_PRI_ECP_SHIFT)) & TCD_CH_PRI_ECP_MASK) +/*! @} */ + +/* The count of TCD_CH_PRI */ +#define TCD_CH_PRI_COUNT (31U) + +/*! @name TCD_SADDR - TCD Source Address */ +/*! @{ */ + +#define TCD_TCD_SADDR_SADDR_MASK (0xFFFFFFFFU) +#define TCD_TCD_SADDR_SADDR_SHIFT (0U) +/*! SADDR - Source Address */ +#define TCD_TCD_SADDR_SADDR(x) (((uint32_t)(((uint32_t)(x)) << TCD_TCD_SADDR_SADDR_SHIFT)) & TCD_TCD_SADDR_SADDR_MASK) +/*! @} */ + +/* The count of TCD_TCD_SADDR */ +#define TCD_TCD_SADDR_COUNT (31U) + +/*! @name TCD_SOFF - TCD Signed Source Address Offset */ +/*! @{ */ + +#define TCD_TCD_SOFF_SOFF_MASK (0xFFFFU) +#define TCD_TCD_SOFF_SOFF_SHIFT (0U) +/*! SOFF - Source Address Signed Offset */ +#define TCD_TCD_SOFF_SOFF(x) (((uint16_t)(((uint16_t)(x)) << TCD_TCD_SOFF_SOFF_SHIFT)) & TCD_TCD_SOFF_SOFF_MASK) +/*! @} */ + +/* The count of TCD_TCD_SOFF */ +#define TCD_TCD_SOFF_COUNT (31U) + +/*! @name TCD_ATTR - TCD Transfer Attributes */ +/*! @{ */ + +#define TCD_TCD_ATTR_DSIZE_MASK (0x7U) +#define TCD_TCD_ATTR_DSIZE_SHIFT (0U) +/*! DSIZE - Destination Data Transfer Size */ +#define TCD_TCD_ATTR_DSIZE(x) (((uint16_t)(((uint16_t)(x)) << TCD_TCD_ATTR_DSIZE_SHIFT)) & TCD_TCD_ATTR_DSIZE_MASK) + +#define TCD_TCD_ATTR_DMOD_MASK (0xF8U) +#define TCD_TCD_ATTR_DMOD_SHIFT (3U) +/*! DMOD - Destination Address Modulo */ +#define TCD_TCD_ATTR_DMOD(x) (((uint16_t)(((uint16_t)(x)) << TCD_TCD_ATTR_DMOD_SHIFT)) & TCD_TCD_ATTR_DMOD_MASK) + +#define TCD_TCD_ATTR_SSIZE_MASK (0x700U) +#define TCD_TCD_ATTR_SSIZE_SHIFT (8U) +/*! SSIZE - Source Data Transfer Size + * 0b000..8-bit + * 0b001..16-bit + * 0b010..32-bit + * 0b011..64-bit + * 0b100..16-byte + * 0b101..32-byte + * 0b110..64-byte + * 0b111.. + */ +#define TCD_TCD_ATTR_SSIZE(x) (((uint16_t)(((uint16_t)(x)) << TCD_TCD_ATTR_SSIZE_SHIFT)) & TCD_TCD_ATTR_SSIZE_MASK) + +#define TCD_TCD_ATTR_SMOD_MASK (0xF800U) +#define TCD_TCD_ATTR_SMOD_SHIFT (11U) +/*! SMOD - Source Address Modulo + * 0b00000..Source address modulo feature disabled + * 0b00001..Source address modulo feature enabled for any non-zero value [1-31] + */ +#define TCD_TCD_ATTR_SMOD(x) (((uint16_t)(((uint16_t)(x)) << TCD_TCD_ATTR_SMOD_SHIFT)) & TCD_TCD_ATTR_SMOD_MASK) +/*! @} */ + +/* The count of TCD_TCD_ATTR */ +#define TCD_TCD_ATTR_COUNT (31U) + +/*! @name TCD_NBYTES_MLOFFNO - TCD Transfer Size Without Minor Loop Offsets */ +/*! @{ */ + +#define TCD_TCD_NBYTES_MLOFFNO_NBYTES_MASK (0x3FFFFFFFU) +#define TCD_TCD_NBYTES_MLOFFNO_NBYTES_SHIFT (0U) +/*! NBYTES - Number of Bytes To Transfer Per Service Request */ +#define TCD_TCD_NBYTES_MLOFFNO_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << TCD_TCD_NBYTES_MLOFFNO_NBYTES_SHIFT)) & TCD_TCD_NBYTES_MLOFFNO_NBYTES_MASK) + +#define TCD_TCD_NBYTES_MLOFFNO_DMLOE_MASK (0x40000000U) +#define TCD_TCD_NBYTES_MLOFFNO_DMLOE_SHIFT (30U) +/*! DMLOE - Destination Minor Loop Offset Enable + * 0b0..Minor loop offset not applied to DADDR + * 0b1..Minor loop offset applied to DADDR + */ +#define TCD_TCD_NBYTES_MLOFFNO_DMLOE(x) (((uint32_t)(((uint32_t)(x)) << TCD_TCD_NBYTES_MLOFFNO_DMLOE_SHIFT)) & TCD_TCD_NBYTES_MLOFFNO_DMLOE_MASK) + +#define TCD_TCD_NBYTES_MLOFFNO_SMLOE_MASK (0x80000000U) +#define TCD_TCD_NBYTES_MLOFFNO_SMLOE_SHIFT (31U) +/*! SMLOE - Source Minor Loop Offset Enable + * 0b0..Minor loop offset not applied to SADDR + * 0b1..Minor loop offset applied to SADDR + */ +#define TCD_TCD_NBYTES_MLOFFNO_SMLOE(x) (((uint32_t)(((uint32_t)(x)) << TCD_TCD_NBYTES_MLOFFNO_SMLOE_SHIFT)) & TCD_TCD_NBYTES_MLOFFNO_SMLOE_MASK) +/*! @} */ + +/* The count of TCD_TCD_NBYTES_MLOFFNO */ +#define TCD_TCD_NBYTES_MLOFFNO_COUNT (31U) + +/*! @name TCD_NBYTES_MLOFFYES - TCD Transfer Size with Minor Loop Offsets */ +/*! @{ */ + +#define TCD_TCD_NBYTES_MLOFFYES_NBYTES_MASK (0x3FFU) +#define TCD_TCD_NBYTES_MLOFFYES_NBYTES_SHIFT (0U) +/*! NBYTES - Number of Bytes To Transfer Per Service Request */ +#define TCD_TCD_NBYTES_MLOFFYES_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << TCD_TCD_NBYTES_MLOFFYES_NBYTES_SHIFT)) & TCD_TCD_NBYTES_MLOFFYES_NBYTES_MASK) + +#define TCD_TCD_NBYTES_MLOFFYES_MLOFF_MASK (0x3FFFFC00U) +#define TCD_TCD_NBYTES_MLOFFYES_MLOFF_SHIFT (10U) +/*! MLOFF - Minor Loop Offset */ +#define TCD_TCD_NBYTES_MLOFFYES_MLOFF(x) (((uint32_t)(((uint32_t)(x)) << TCD_TCD_NBYTES_MLOFFYES_MLOFF_SHIFT)) & TCD_TCD_NBYTES_MLOFFYES_MLOFF_MASK) + +#define TCD_TCD_NBYTES_MLOFFYES_DMLOE_MASK (0x40000000U) +#define TCD_TCD_NBYTES_MLOFFYES_DMLOE_SHIFT (30U) +/*! DMLOE - Destination Minor Loop Offset Enable + * 0b0..Minor loop offset not applied to DADDR + * 0b1..Minor loop offset applied to DADDR + */ +#define TCD_TCD_NBYTES_MLOFFYES_DMLOE(x) (((uint32_t)(((uint32_t)(x)) << TCD_TCD_NBYTES_MLOFFYES_DMLOE_SHIFT)) & TCD_TCD_NBYTES_MLOFFYES_DMLOE_MASK) + +#define TCD_TCD_NBYTES_MLOFFYES_SMLOE_MASK (0x80000000U) +#define TCD_TCD_NBYTES_MLOFFYES_SMLOE_SHIFT (31U) +/*! SMLOE - Source Minor Loop Offset Enable + * 0b0..Minor loop offset not applied to SADDR + * 0b1..Minor loop offset applied to SADDR + */ +#define TCD_TCD_NBYTES_MLOFFYES_SMLOE(x) (((uint32_t)(((uint32_t)(x)) << TCD_TCD_NBYTES_MLOFFYES_SMLOE_SHIFT)) & TCD_TCD_NBYTES_MLOFFYES_SMLOE_MASK) +/*! @} */ + +/* The count of TCD_TCD_NBYTES_MLOFFYES */ +#define TCD_TCD_NBYTES_MLOFFYES_COUNT (31U) + +/*! @name TCD_SLAST_SDA - TCD Last Source Address Adjustment / Store DADDR Address */ +/*! @{ */ + +#define TCD_TCD_SLAST_SDA_SLAST_SDA_MASK (0xFFFFFFFFU) +#define TCD_TCD_SLAST_SDA_SLAST_SDA_SHIFT (0U) +/*! SLAST_SDA - Last Source Address Adjustment / Store DADDR Address */ +#define TCD_TCD_SLAST_SDA_SLAST_SDA(x) (((uint32_t)(((uint32_t)(x)) << TCD_TCD_SLAST_SDA_SLAST_SDA_SHIFT)) & TCD_TCD_SLAST_SDA_SLAST_SDA_MASK) +/*! @} */ + +/* The count of TCD_TCD_SLAST_SDA */ +#define TCD_TCD_SLAST_SDA_COUNT (31U) + +/*! @name TCD_DADDR - TCD Destination Address */ +/*! @{ */ + +#define TCD_TCD_DADDR_DADDR_MASK (0xFFFFFFFFU) +#define TCD_TCD_DADDR_DADDR_SHIFT (0U) +/*! DADDR - Destination Address */ +#define TCD_TCD_DADDR_DADDR(x) (((uint32_t)(((uint32_t)(x)) << TCD_TCD_DADDR_DADDR_SHIFT)) & TCD_TCD_DADDR_DADDR_MASK) +/*! @} */ + +/* The count of TCD_TCD_DADDR */ +#define TCD_TCD_DADDR_COUNT (31U) + +/*! @name TCD_DOFF - TCD Signed Destination Address Offset */ +/*! @{ */ + +#define TCD_TCD_DOFF_DOFF_MASK (0xFFFFU) +#define TCD_TCD_DOFF_DOFF_SHIFT (0U) +/*! DOFF - Destination Address Signed Offset */ +#define TCD_TCD_DOFF_DOFF(x) (((uint16_t)(((uint16_t)(x)) << TCD_TCD_DOFF_DOFF_SHIFT)) & TCD_TCD_DOFF_DOFF_MASK) +/*! @} */ + +/* The count of TCD_TCD_DOFF */ +#define TCD_TCD_DOFF_COUNT (31U) + +/*! @name TCD_CITER_ELINKNO - TCD Current Major Loop Count (Minor Loop Channel Linking Disabled) */ +/*! @{ */ + +#define TCD_TCD_CITER_ELINKNO_CITER_MASK (0x7FFFU) +#define TCD_TCD_CITER_ELINKNO_CITER_SHIFT (0U) +/*! CITER - Current Major Iteration Count */ +#define TCD_TCD_CITER_ELINKNO_CITER(x) (((uint16_t)(((uint16_t)(x)) << TCD_TCD_CITER_ELINKNO_CITER_SHIFT)) & TCD_TCD_CITER_ELINKNO_CITER_MASK) + +#define TCD_TCD_CITER_ELINKNO_ELINK_MASK (0x8000U) +#define TCD_TCD_CITER_ELINKNO_ELINK_SHIFT (15U) +/*! ELINK - Enable Link + * 0b0..Channel-to-channel linking disabled + * 0b1..Channel-to-channel linking enabled + */ +#define TCD_TCD_CITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x)) << TCD_TCD_CITER_ELINKNO_ELINK_SHIFT)) & TCD_TCD_CITER_ELINKNO_ELINK_MASK) +/*! @} */ + +/* The count of TCD_TCD_CITER_ELINKNO */ +#define TCD_TCD_CITER_ELINKNO_COUNT (31U) + +/*! @name TCD_CITER_ELINKYES - TCD Current Major Loop Count (Minor Loop Channel Linking Enabled) */ +/*! @{ */ + +#define TCD_TCD_CITER_ELINKYES_CITER_MASK (0x1FFU) +#define TCD_TCD_CITER_ELINKYES_CITER_SHIFT (0U) +/*! CITER - Current Major Iteration Count */ +#define TCD_TCD_CITER_ELINKYES_CITER(x) (((uint16_t)(((uint16_t)(x)) << TCD_TCD_CITER_ELINKYES_CITER_SHIFT)) & TCD_TCD_CITER_ELINKYES_CITER_MASK) + +#define TCD_TCD_CITER_ELINKYES_LINKCH_MASK (0x3E00U) +#define TCD_TCD_CITER_ELINKYES_LINKCH_SHIFT (9U) +/*! LINKCH - Minor Loop Link Channel Number */ +#define TCD_TCD_CITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << TCD_TCD_CITER_ELINKYES_LINKCH_SHIFT)) & TCD_TCD_CITER_ELINKYES_LINKCH_MASK) + +#define TCD_TCD_CITER_ELINKYES_ELINK_MASK (0x8000U) +#define TCD_TCD_CITER_ELINKYES_ELINK_SHIFT (15U) +/*! ELINK - Enable Link + * 0b0..Channel-to-channel linking disabled + * 0b1..Channel-to-channel linking enabled + */ +#define TCD_TCD_CITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x)) << TCD_TCD_CITER_ELINKYES_ELINK_SHIFT)) & TCD_TCD_CITER_ELINKYES_ELINK_MASK) +/*! @} */ + +/* The count of TCD_TCD_CITER_ELINKYES */ +#define TCD_TCD_CITER_ELINKYES_COUNT (31U) + +/*! @name TCD_DLAST_SGA - TCD Last Destination Address Adjustment / Scatter Gather Address */ +/*! @{ */ + +#define TCD_TCD_DLAST_SGA_DLAST_SGA_MASK (0xFFFFFFFFU) +#define TCD_TCD_DLAST_SGA_DLAST_SGA_SHIFT (0U) +/*! DLAST_SGA - Last Destination Address Adjustment / Scatter Gather Address */ +#define TCD_TCD_DLAST_SGA_DLAST_SGA(x) (((uint32_t)(((uint32_t)(x)) << TCD_TCD_DLAST_SGA_DLAST_SGA_SHIFT)) & TCD_TCD_DLAST_SGA_DLAST_SGA_MASK) +/*! @} */ + +/* The count of TCD_TCD_DLAST_SGA */ +#define TCD_TCD_DLAST_SGA_COUNT (31U) + +/*! @name TCD_CSR - TCD Control and Status */ +/*! @{ */ + +#define TCD_TCD_CSR_START_MASK (0x1U) +#define TCD_TCD_CSR_START_SHIFT (0U) +/*! START - Channel Start + * 0b0..Channel not explicitly started + * 0b1..Channel explicitly started via a software-initiated service request + */ +#define TCD_TCD_CSR_START(x) (((uint16_t)(((uint16_t)(x)) << TCD_TCD_CSR_START_SHIFT)) & TCD_TCD_CSR_START_MASK) + +#define TCD_TCD_CSR_INTMAJOR_MASK (0x2U) +#define TCD_TCD_CSR_INTMAJOR_SHIFT (1U) +/*! INTMAJOR - Enable Interrupt If Major count complete + * 0b0..End-of-major loop interrupt disabled + * 0b1..End-of-major loop interrupt enabled + */ +#define TCD_TCD_CSR_INTMAJOR(x) (((uint16_t)(((uint16_t)(x)) << TCD_TCD_CSR_INTMAJOR_SHIFT)) & TCD_TCD_CSR_INTMAJOR_MASK) + +#define TCD_TCD_CSR_INTHALF_MASK (0x4U) +#define TCD_TCD_CSR_INTHALF_SHIFT (2U) +/*! INTHALF - Enable Interrupt If Major Counter Half-complete + * 0b0..Halfway point interrupt disabled + * 0b1..Halfway point interrupt enabled + */ +#define TCD_TCD_CSR_INTHALF(x) (((uint16_t)(((uint16_t)(x)) << TCD_TCD_CSR_INTHALF_SHIFT)) & TCD_TCD_CSR_INTHALF_MASK) + +#define TCD_TCD_CSR_DREQ_MASK (0x8U) +#define TCD_TCD_CSR_DREQ_SHIFT (3U) +/*! DREQ - Disable Request + * 0b0..No operation + * 0b1..Clear the ERQ field to 0 upon major loop completion, thus disabling hardware service requests + */ +#define TCD_TCD_CSR_DREQ(x) (((uint16_t)(((uint16_t)(x)) << TCD_TCD_CSR_DREQ_SHIFT)) & TCD_TCD_CSR_DREQ_MASK) + +#define TCD_TCD_CSR_ESG_MASK (0x10U) +#define TCD_TCD_CSR_ESG_SHIFT (4U) +/*! ESG - Enable Scatter/Gather Processing + * 0b0..Current channel's TCD is normal format + * 0b1..Current channel's TCD specifies scatter/gather format. + */ +#define TCD_TCD_CSR_ESG(x) (((uint16_t)(((uint16_t)(x)) << TCD_TCD_CSR_ESG_SHIFT)) & TCD_TCD_CSR_ESG_MASK) + +#define TCD_TCD_CSR_MAJORELINK_MASK (0x20U) +#define TCD_TCD_CSR_MAJORELINK_SHIFT (5U) +/*! MAJORELINK - Enable Link When Major Loop Complete + * 0b0..Channel-to-channel linking disabled + * 0b1..Channel-to-channel linking enabled + */ +#define TCD_TCD_CSR_MAJORELINK(x) (((uint16_t)(((uint16_t)(x)) << TCD_TCD_CSR_MAJORELINK_SHIFT)) & TCD_TCD_CSR_MAJORELINK_MASK) + +#define TCD_TCD_CSR_EEOP_MASK (0x40U) +#define TCD_TCD_CSR_EEOP_SHIFT (6U) +/*! EEOP - Enable End-Of-Packet Processing + * 0b0..End-of-packet operation disabled + * 0b1..End-of-packet hardware input signal enabled + */ +#define TCD_TCD_CSR_EEOP(x) (((uint16_t)(((uint16_t)(x)) << TCD_TCD_CSR_EEOP_SHIFT)) & TCD_TCD_CSR_EEOP_MASK) + +#define TCD_TCD_CSR_ESDA_MASK (0x80U) +#define TCD_TCD_CSR_ESDA_SHIFT (7U) +/*! ESDA - Enable Store Destination Address + * 0b0..Ability to store destination address to system memory disabled + * 0b1..Ability to store destination address to system memory enabled + */ +#define TCD_TCD_CSR_ESDA(x) (((uint16_t)(((uint16_t)(x)) << TCD_TCD_CSR_ESDA_SHIFT)) & TCD_TCD_CSR_ESDA_MASK) + +#define TCD_TCD_CSR_MAJORLINKCH_MASK (0x1F00U) +#define TCD_TCD_CSR_MAJORLINKCH_SHIFT (8U) +/*! MAJORLINKCH - Major Loop Link Channel Number */ +#define TCD_TCD_CSR_MAJORLINKCH(x) (((uint16_t)(((uint16_t)(x)) << TCD_TCD_CSR_MAJORLINKCH_SHIFT)) & TCD_TCD_CSR_MAJORLINKCH_MASK) + +#define TCD_TCD_CSR_BWC_MASK (0xC000U) +#define TCD_TCD_CSR_BWC_SHIFT (14U) +/*! BWC - Bandwidth Control + * 0b00..No eDMA engine stalls + * 0b01.. + * 0b10..eDMA engine stalls for 4 cycles after each R/W + * 0b11..eDMA engine stalls for 8 cycles after each R/W + */ +#define TCD_TCD_CSR_BWC(x) (((uint16_t)(((uint16_t)(x)) << TCD_TCD_CSR_BWC_SHIFT)) & TCD_TCD_CSR_BWC_MASK) +/*! @} */ + +/* The count of TCD_TCD_CSR */ +#define TCD_TCD_CSR_COUNT (31U) + +/*! @name TCD_BITER_ELINKNO - TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled) */ +/*! @{ */ + +#define TCD_TCD_BITER_ELINKNO_BITER_MASK (0x7FFFU) +#define TCD_TCD_BITER_ELINKNO_BITER_SHIFT (0U) +/*! BITER - Starting Major Iteration Count */ +#define TCD_TCD_BITER_ELINKNO_BITER(x) (((uint16_t)(((uint16_t)(x)) << TCD_TCD_BITER_ELINKNO_BITER_SHIFT)) & TCD_TCD_BITER_ELINKNO_BITER_MASK) + +#define TCD_TCD_BITER_ELINKNO_ELINK_MASK (0x8000U) +#define TCD_TCD_BITER_ELINKNO_ELINK_SHIFT (15U) +/*! ELINK - Enables Link + * 0b0..Channel-to-channel linking disabled + * 0b1..Channel-to-channel linking enabled + */ +#define TCD_TCD_BITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x)) << TCD_TCD_BITER_ELINKNO_ELINK_SHIFT)) & TCD_TCD_BITER_ELINKNO_ELINK_MASK) +/*! @} */ + +/* The count of TCD_TCD_BITER_ELINKNO */ +#define TCD_TCD_BITER_ELINKNO_COUNT (31U) + +/*! @name TCD_BITER_ELINKYES - TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled) */ +/*! @{ */ + +#define TCD_TCD_BITER_ELINKYES_BITER_MASK (0x1FFU) +#define TCD_TCD_BITER_ELINKYES_BITER_SHIFT (0U) +/*! BITER - Starting Major Iteration Count */ +#define TCD_TCD_BITER_ELINKYES_BITER(x) (((uint16_t)(((uint16_t)(x)) << TCD_TCD_BITER_ELINKYES_BITER_SHIFT)) & TCD_TCD_BITER_ELINKYES_BITER_MASK) + +#define TCD_TCD_BITER_ELINKYES_LINKCH_MASK (0x3E00U) +#define TCD_TCD_BITER_ELINKYES_LINKCH_SHIFT (9U) +/*! LINKCH - Link Channel Number */ +#define TCD_TCD_BITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << TCD_TCD_BITER_ELINKYES_LINKCH_SHIFT)) & TCD_TCD_BITER_ELINKYES_LINKCH_MASK) + +#define TCD_TCD_BITER_ELINKYES_ELINK_MASK (0x8000U) +#define TCD_TCD_BITER_ELINKYES_ELINK_SHIFT (15U) +/*! ELINK - Enable Link + * 0b0..Channel-to-channel linking disabled + * 0b1..Channel-to-channel linking enabled + */ +#define TCD_TCD_BITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x)) << TCD_TCD_BITER_ELINKYES_ELINK_SHIFT)) & TCD_TCD_BITER_ELINKYES_ELINK_MASK) +/*! @} */ + +/* The count of TCD_TCD_BITER_ELINKYES */ +#define TCD_TCD_BITER_ELINKYES_COUNT (31U) + + +/*! + * @} + */ /* end of group TCD_Register_Masks */ + + +/* TCD - Peripheral instance base addresses */ +/** Peripheral EDMA3_1__TCD base address */ +#define EDMA3_1__TCD_BASE (0x44010000u) +/** Peripheral EDMA3_1__TCD base pointer */ +#define EDMA3_1__TCD ((TCD_Type *)EDMA3_1__TCD_BASE) +/** Array initializer of TCD peripheral base addresses */ +#define TCD_BASE_ADDRS { EDMA3_1__TCD_BASE } +/** Array initializer of TCD peripheral base pointers */ +#define TCD_BASE_PTRS { EDMA3_1__TCD } + +/*! + * @} + */ /* end of group TCD_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- TEMPSENSE Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup TEMPSENSE_Peripheral_Access_Layer TEMPSENSE Peripheral Access Layer + * @{ + */ + +/** TEMPSENSE - Register Layout Typedef */ +typedef struct { + struct { /* offset: 0x0 */ + __IO uint32_t RW; /**< Control 0, offset: 0x0 */ + __IO uint32_t SET; /**< Control 0, offset: 0x4 */ + __IO uint32_t CLR; /**< Control 0, offset: 0x8 */ + __IO uint32_t TOG; /**< Control 0, offset: 0xC */ + } CTRL0; + struct { /* offset: 0x10 */ + __IO uint32_t RW; /**< Status 0, offset: 0x10 */ + __IO uint32_t SET; /**< Status 0, offset: 0x14 */ + __IO uint32_t CLR; /**< Status 0, offset: 0x18 */ + __IO uint32_t TOG; /**< Status 0, offset: 0x1C */ + } STAT0; + struct { /* offset: 0x20 */ + __IO uint32_t RW; /**< Data 0, offset: 0x20 */ + __IO uint32_t SET; /**< Data 0, offset: 0x24 */ + __IO uint32_t CLR; /**< Data 0, offset: 0x28 */ + __IO uint32_t TOG; /**< Data 0, offset: 0x2C */ + } DATA0; + struct { /* offset: 0x30 */ + __IO uint32_t RW; /**< Threshold Control 01, offset: 0x30 */ + __IO uint32_t SET; /**< Threshold Control 01, offset: 0x34 */ + __IO uint32_t CLR; /**< Threshold Control 01, offset: 0x38 */ + __IO uint32_t TOG; /**< Threshold Control 01, offset: 0x3C */ + } THR_CTRL01; + struct { /* offset: 0x40 */ + __IO uint32_t RW; /**< Threshold Control 23, offset: 0x40 */ + __IO uint32_t SET; /**< Threshold Control 23, offset: 0x44 */ + __IO uint32_t CLR; /**< Threshold Control 23, offset: 0x48 */ + __IO uint32_t TOG; /**< Threshold Control 23, offset: 0x4C */ + } THR_CTRL23; + uint8_t RESERVED_0[432]; + struct { /* offset: 0x200 */ + __IO uint32_t RW; /**< Control 1, offset: 0x200 */ + __IO uint32_t SET; /**< Control 1, offset: 0x204 */ + __IO uint32_t CLR; /**< Control 1, offset: 0x208 */ + __IO uint32_t TOG; /**< Control 1, offset: 0x20C */ + } CTRL1; + struct { /* offset: 0x210 */ + __IO uint32_t RW; /**< Status 1, offset: 0x210 */ + __IO uint32_t SET; /**< Status 1, offset: 0x214 */ + __IO uint32_t CLR; /**< Status 1, offset: 0x218 */ + __IO uint32_t TOG; /**< Status 1, offset: 0x21C */ + } STAT1; + struct { /* offset: 0x220 */ + __IO uint32_t RW; /**< Data 1, offset: 0x220 */ + __IO uint32_t SET; /**< Data 1, offset: 0x224 */ + __IO uint32_t CLR; /**< Data 1, offset: 0x228 */ + __IO uint32_t TOG; /**< Data 1, offset: 0x22C */ + } DATA1; + uint8_t RESERVED_1[32]; + struct { /* offset: 0x250 */ + __IO uint32_t RW; /**< Threshold Control 45, offset: 0x250 */ + __IO uint32_t SET; /**< Threshold Control 45, offset: 0x254 */ + __IO uint32_t CLR; /**< Threshold Control 45, offset: 0x258 */ + __IO uint32_t TOG; /**< Threshold Control 45, offset: 0x25C */ + } THR_CTRL45; + uint8_t RESERVED_2[16]; + struct { /* offset: 0x270 */ + __IO uint32_t RW; /**< Measurement Period Control, offset: 0x270 */ + __IO uint32_t SET; /**< Measurement Period Control, offset: 0x274 */ + __IO uint32_t CLR; /**< Measurement Period Control, offset: 0x278 */ + __IO uint32_t TOG; /**< Measurement Period Control, offset: 0x27C */ + } PERIOD_CTRL; + __IO uint32_t REF_DIV; /**< Reference Clock Divider Control, offset: 0x280 */ + uint8_t RESERVED_3[44]; + struct { /* offset: 0x2B0 */ + __IO uint32_t RW; /**< Power-Up Delay Control, offset: 0x2B0 */ + __IO uint32_t SET; /**< Power-Up Delay Control, offset: 0x2B4 */ + __IO uint32_t CLR; /**< Power-Up Delay Control, offset: 0x2B8 */ + __IO uint32_t TOG; /**< Power-Up Delay Control, offset: 0x2BC */ + } PUD_ST_CTRL; + uint8_t RESERVED_4[32]; + struct { /* offset: 0x2E0 */ + __IO uint32_t RW; /**< Trim Control 1, offset: 0x2E0 */ + __IO uint32_t SET; /**< Trim Control 1, offset: 0x2E4 */ + __IO uint32_t CLR; /**< Trim Control 1, offset: 0x2E8 */ + __IO uint32_t TOG; /**< Trim Control 1, offset: 0x2EC */ + } TRIM1; + struct { /* offset: 0x2F0 */ + __IO uint32_t RW; /**< Trim Control 2, offset: 0x2F0 */ + __IO uint32_t SET; /**< Trim Control 2, offset: 0x2F4 */ + __IO uint32_t CLR; /**< Trim Control 2, offset: 0x2F8 */ + __IO uint32_t TOG; /**< Trim Control 2, offset: 0x2FC */ + } TRIM2; +} TEMPSENSE_Type; + +/* ---------------------------------------------------------------------------- + -- TEMPSENSE Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup TEMPSENSE_Register_Masks TEMPSENSE Register Masks + * @{ + */ + +/*! @name CTRL0 - Control 0 */ +/*! @{ */ + +#define TEMPSENSE_CTRL0_THR0_MODE_MASK (0x3U) +#define TEMPSENSE_CTRL0_THR0_MODE_SHIFT (0U) +/*! THR0_MODE - Threshold0 Comparator Mode + * 0b00..Less than or equal to threshold + * 0b01..Greater than threshold + * 0b10..High to low temperature data transition at threshold + * 0b11..Low to high temperature data transition at threshold + */ +#define TEMPSENSE_CTRL0_THR0_MODE(x) (((uint32_t)(((uint32_t)(x)) << TEMPSENSE_CTRL0_THR0_MODE_SHIFT)) & TEMPSENSE_CTRL0_THR0_MODE_MASK) + +#define TEMPSENSE_CTRL0_THR1_MODE_MASK (0xCU) +#define TEMPSENSE_CTRL0_THR1_MODE_SHIFT (2U) +/*! THR1_MODE - Threshold1 Comparator Mode + * 0b00..Less than or equal to threshold + * 0b01..Greater than threshold + * 0b10..High to low temperature data transition at threshold + * 0b11..Low to high temperature data transition at threshold + */ +#define TEMPSENSE_CTRL0_THR1_MODE(x) (((uint32_t)(((uint32_t)(x)) << TEMPSENSE_CTRL0_THR1_MODE_SHIFT)) & TEMPSENSE_CTRL0_THR1_MODE_MASK) + +#define TEMPSENSE_CTRL0_THR2_MODE_MASK (0x30U) +#define TEMPSENSE_CTRL0_THR2_MODE_SHIFT (4U) +/*! THR2_MODE - Threshold2 Comparator Mode + * 0b00..Less than or equal to threshold + * 0b01..Greater than threshold + * 0b10..High to low temperature data transition at threshold + * 0b11..Low to high temperature data transition at threshold + */ +#define TEMPSENSE_CTRL0_THR2_MODE(x) (((uint32_t)(((uint32_t)(x)) << TEMPSENSE_CTRL0_THR2_MODE_SHIFT)) & TEMPSENSE_CTRL0_THR2_MODE_MASK) + +#define TEMPSENSE_CTRL0_THR0_IE_MASK (0x100U) +#define TEMPSENSE_CTRL0_THR0_IE_SHIFT (8U) +/*! THR0_IE - Threshold0 Comparator Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define TEMPSENSE_CTRL0_THR0_IE(x) (((uint32_t)(((uint32_t)(x)) << TEMPSENSE_CTRL0_THR0_IE_SHIFT)) & TEMPSENSE_CTRL0_THR0_IE_MASK) + +#define TEMPSENSE_CTRL0_THR1_IE_MASK (0x200U) +#define TEMPSENSE_CTRL0_THR1_IE_SHIFT (9U) +/*! THR1_IE - Threshold1 Comparator Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define TEMPSENSE_CTRL0_THR1_IE(x) (((uint32_t)(((uint32_t)(x)) << TEMPSENSE_CTRL0_THR1_IE_SHIFT)) & TEMPSENSE_CTRL0_THR1_IE_MASK) + +#define TEMPSENSE_CTRL0_THR2_IE_MASK (0x400U) +#define TEMPSENSE_CTRL0_THR2_IE_SHIFT (10U) +/*! THR2_IE - Threshold2 Comparator Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define TEMPSENSE_CTRL0_THR2_IE(x) (((uint32_t)(((uint32_t)(x)) << TEMPSENSE_CTRL0_THR2_IE_SHIFT)) & TEMPSENSE_CTRL0_THR2_IE_MASK) + +#define TEMPSENSE_CTRL0_N_FILT_0_MASK (0xF000U) +#define TEMPSENSE_CTRL0_N_FILT_0_SHIFT (12U) +/*! N_FILT_0 - Filter Length for Threshold Flag */ +#define TEMPSENSE_CTRL0_N_FILT_0(x) (((uint32_t)(((uint32_t)(x)) << TEMPSENSE_CTRL0_N_FILT_0_SHIFT)) & TEMPSENSE_CTRL0_N_FILT_0_MASK) + +#define TEMPSENSE_CTRL0_DRDY0_IE_MASK (0x10000U) +#define TEMPSENSE_CTRL0_DRDY0_IE_SHIFT (16U) +/*! DRDY0_IE - Data-Ready Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define TEMPSENSE_CTRL0_DRDY0_IE(x) (((uint32_t)(((uint32_t)(x)) << TEMPSENSE_CTRL0_DRDY0_IE_SHIFT)) & TEMPSENSE_CTRL0_DRDY0_IE_MASK) + +#define TEMPSENSE_CTRL0_FILT0_CNT_CLR_MASK (0x100000U) +#define TEMPSENSE_CTRL0_FILT0_CNT_CLR_SHIFT (20U) +/*! FILT0_CNT_CLR - Filter 0 Counter Clear + * 0b0..Settle to 0 after clearing the counter + * 0b1..Clear the internal counter + */ +#define TEMPSENSE_CTRL0_FILT0_CNT_CLR(x) (((uint32_t)(((uint32_t)(x)) << TEMPSENSE_CTRL0_FILT0_CNT_CLR_SHIFT)) & TEMPSENSE_CTRL0_FILT0_CNT_CLR_MASK) + +#define TEMPSENSE_CTRL0_FILT1_CNT_CLR_MASK (0x200000U) +#define TEMPSENSE_CTRL0_FILT1_CNT_CLR_SHIFT (21U) +/*! FILT1_CNT_CLR - Filter 1 Counter Clear + * 0b0..Settle to 0 after clearing the counter + * 0b1..Clear the internal counter + */ +#define TEMPSENSE_CTRL0_FILT1_CNT_CLR(x) (((uint32_t)(((uint32_t)(x)) << TEMPSENSE_CTRL0_FILT1_CNT_CLR_SHIFT)) & TEMPSENSE_CTRL0_FILT1_CNT_CLR_MASK) + +#define TEMPSENSE_CTRL0_FILT2_CNT_CLR_MASK (0x400000U) +#define TEMPSENSE_CTRL0_FILT2_CNT_CLR_SHIFT (22U) +/*! FILT2_CNT_CLR - Filter 2 Counter Clear + * 0b0..Settle to 0 after clearing the counter + * 0b1..Clear the internal counter + */ +#define TEMPSENSE_CTRL0_FILT2_CNT_CLR(x) (((uint32_t)(((uint32_t)(x)) << TEMPSENSE_CTRL0_FILT2_CNT_CLR_SHIFT)) & TEMPSENSE_CTRL0_FILT2_CNT_CLR_MASK) +/*! @} */ + +/*! @name STAT0 - Status 0 */ +/*! @{ */ + +#define TEMPSENSE_STAT0_THR0_IF_MASK (0x100U) +#define TEMPSENSE_STAT0_THR0_IF_SHIFT (8U) +/*! THR0_IF - Threshold0 Status Flag + * 0b0..Event did not occur + * 0b0..No effect + * 0b1..Event occurred + * 0b1..Clear the flag + */ +#define TEMPSENSE_STAT0_THR0_IF(x) (((uint32_t)(((uint32_t)(x)) << TEMPSENSE_STAT0_THR0_IF_SHIFT)) & TEMPSENSE_STAT0_THR0_IF_MASK) + +#define TEMPSENSE_STAT0_THR1_IF_MASK (0x200U) +#define TEMPSENSE_STAT0_THR1_IF_SHIFT (9U) +/*! THR1_IF - Threshold1 Status Flag + * 0b0..Event did not occur + * 0b0..No effect + * 0b1..Event occurred + * 0b1..Clear the flag + */ +#define TEMPSENSE_STAT0_THR1_IF(x) (((uint32_t)(((uint32_t)(x)) << TEMPSENSE_STAT0_THR1_IF_SHIFT)) & TEMPSENSE_STAT0_THR1_IF_MASK) + +#define TEMPSENSE_STAT0_THR2_IF_MASK (0x400U) +#define TEMPSENSE_STAT0_THR2_IF_SHIFT (10U) +/*! THR2_IF - Threshold2 Status Flag + * 0b0..Event did not occur + * 0b0..No effect + * 0b1..Event occurred + * 0b1..Clear the flag + */ +#define TEMPSENSE_STAT0_THR2_IF(x) (((uint32_t)(((uint32_t)(x)) << TEMPSENSE_STAT0_THR2_IF_SHIFT)) & TEMPSENSE_STAT0_THR2_IF_MASK) + +#define TEMPSENSE_STAT0_THR0_STAT_MASK (0x1000U) +#define TEMPSENSE_STAT0_THR0_STAT_SHIFT (12U) +/*! THR0_STAT - Threshold0 State */ +#define TEMPSENSE_STAT0_THR0_STAT(x) (((uint32_t)(((uint32_t)(x)) << TEMPSENSE_STAT0_THR0_STAT_SHIFT)) & TEMPSENSE_STAT0_THR0_STAT_MASK) + +#define TEMPSENSE_STAT0_THR1_STAT_MASK (0x2000U) +#define TEMPSENSE_STAT0_THR1_STAT_SHIFT (13U) +/*! THR1_STAT - Threshold1 State */ +#define TEMPSENSE_STAT0_THR1_STAT(x) (((uint32_t)(((uint32_t)(x)) << TEMPSENSE_STAT0_THR1_STAT_SHIFT)) & TEMPSENSE_STAT0_THR1_STAT_MASK) + +#define TEMPSENSE_STAT0_THR2_STAT_MASK (0x4000U) +#define TEMPSENSE_STAT0_THR2_STAT_SHIFT (14U) +/*! THR2_STAT - Threshold2 State */ +#define TEMPSENSE_STAT0_THR2_STAT(x) (((uint32_t)(((uint32_t)(x)) << TEMPSENSE_STAT0_THR2_STAT_SHIFT)) & TEMPSENSE_STAT0_THR2_STAT_MASK) + +#define TEMPSENSE_STAT0_DRDY0_IF_MASK (0x10000U) +#define TEMPSENSE_STAT0_DRDY0_IF_SHIFT (16U) +/*! DRDY0_IF - Data Ready Flag + * 0b0..No new data available + * 0b1..New data available + */ +#define TEMPSENSE_STAT0_DRDY0_IF(x) (((uint32_t)(((uint32_t)(x)) << TEMPSENSE_STAT0_DRDY0_IF_SHIFT)) & TEMPSENSE_STAT0_DRDY0_IF_MASK) + +#define TEMPSENSE_STAT0_IDLE_MASK (0x80000000U) +#define TEMPSENSE_STAT0_IDLE_SHIFT (31U) +/*! IDLE - Idle State + * 0b0..Conversion + * 0b1..Idle + */ +#define TEMPSENSE_STAT0_IDLE(x) (((uint32_t)(((uint32_t)(x)) << TEMPSENSE_STAT0_IDLE_SHIFT)) & TEMPSENSE_STAT0_IDLE_MASK) +/*! @} */ + +/*! @name DATA0 - Data 0 */ +/*! @{ */ + +#define TEMPSENSE_DATA0_DATA_VAL_MASK (0xFFFFU) +#define TEMPSENSE_DATA0_DATA_VAL_SHIFT (0U) +/*! DATA_VAL - Temperature Data Value */ +#define TEMPSENSE_DATA0_DATA_VAL(x) (((uint32_t)(((uint32_t)(x)) << TEMPSENSE_DATA0_DATA_VAL_SHIFT)) & TEMPSENSE_DATA0_DATA_VAL_MASK) +/*! @} */ + +/*! @name THR_CTRL01 - Threshold Control 01 */ +/*! @{ */ + +#define TEMPSENSE_THR_CTRL01_TEMPERATURE_THRESHOLD0_MASK (0xFFFFU) +#define TEMPSENSE_THR_CTRL01_TEMPERATURE_THRESHOLD0_SHIFT (0U) +/*! TEMPERATURE_THRESHOLD0 - Temperature Threshold0 */ +#define TEMPSENSE_THR_CTRL01_TEMPERATURE_THRESHOLD0(x) (((uint32_t)(((uint32_t)(x)) << TEMPSENSE_THR_CTRL01_TEMPERATURE_THRESHOLD0_SHIFT)) & TEMPSENSE_THR_CTRL01_TEMPERATURE_THRESHOLD0_MASK) + +#define TEMPSENSE_THR_CTRL01_TEMPERATURE_THRESHOLD1_MASK (0xFFFF0000U) +#define TEMPSENSE_THR_CTRL01_TEMPERATURE_THRESHOLD1_SHIFT (16U) +/*! TEMPERATURE_THRESHOLD1 - Temperature Threshold1 */ +#define TEMPSENSE_THR_CTRL01_TEMPERATURE_THRESHOLD1(x) (((uint32_t)(((uint32_t)(x)) << TEMPSENSE_THR_CTRL01_TEMPERATURE_THRESHOLD1_SHIFT)) & TEMPSENSE_THR_CTRL01_TEMPERATURE_THRESHOLD1_MASK) +/*! @} */ + +/*! @name THR_CTRL23 - Threshold Control 23 */ +/*! @{ */ + +#define TEMPSENSE_THR_CTRL23_TEMPERATURE_THRESHOLD2_MASK (0xFFFFU) +#define TEMPSENSE_THR_CTRL23_TEMPERATURE_THRESHOLD2_SHIFT (0U) +/*! TEMPERATURE_THRESHOLD2 - Temperature Threshold2 */ +#define TEMPSENSE_THR_CTRL23_TEMPERATURE_THRESHOLD2(x) (((uint32_t)(((uint32_t)(x)) << TEMPSENSE_THR_CTRL23_TEMPERATURE_THRESHOLD2_SHIFT)) & TEMPSENSE_THR_CTRL23_TEMPERATURE_THRESHOLD2_MASK) +/*! @} */ + +/*! @name CTRL1 - Control 1 */ +/*! @{ */ + +#define TEMPSENSE_CTRL1_THR4_MODE_MASK (0x3U) +#define TEMPSENSE_CTRL1_THR4_MODE_SHIFT (0U) +/*! THR4_MODE - Threshold4 Comparator Mode + * 0b00..Less than or equal to threshold + * 0b01..Greater than threshold + * 0b10..High to low temperature data transition at threshold + * 0b11..Low to high temperature data transition at threshold + */ +#define TEMPSENSE_CTRL1_THR4_MODE(x) (((uint32_t)(((uint32_t)(x)) << TEMPSENSE_CTRL1_THR4_MODE_SHIFT)) & TEMPSENSE_CTRL1_THR4_MODE_MASK) + +#define TEMPSENSE_CTRL1_THR5_MODE_MASK (0xCU) +#define TEMPSENSE_CTRL1_THR5_MODE_SHIFT (2U) +/*! THR5_MODE - Threshold5 Comparator Mode + * 0b00..Less than or equal to threshold + * 0b01..Greater than threshold + * 0b10..High to low temperature data transition at threshold + * 0b11..Low to high temperature data transition at threshold + */ +#define TEMPSENSE_CTRL1_THR5_MODE(x) (((uint32_t)(((uint32_t)(x)) << TEMPSENSE_CTRL1_THR5_MODE_SHIFT)) & TEMPSENSE_CTRL1_THR5_MODE_MASK) + +#define TEMPSENSE_CTRL1_THR4_IE_MASK (0x100U) +#define TEMPSENSE_CTRL1_THR4_IE_SHIFT (8U) +/*! THR4_IE - Threshold Comparator4 Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define TEMPSENSE_CTRL1_THR4_IE(x) (((uint32_t)(((uint32_t)(x)) << TEMPSENSE_CTRL1_THR4_IE_SHIFT)) & TEMPSENSE_CTRL1_THR4_IE_MASK) + +#define TEMPSENSE_CTRL1_THR5_IE_MASK (0x200U) +#define TEMPSENSE_CTRL1_THR5_IE_SHIFT (9U) +/*! THR5_IE - Threshold Comparator5 Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define TEMPSENSE_CTRL1_THR5_IE(x) (((uint32_t)(((uint32_t)(x)) << TEMPSENSE_CTRL1_THR5_IE_SHIFT)) & TEMPSENSE_CTRL1_THR5_IE_MASK) + +#define TEMPSENSE_CTRL1_N_FILT_1_MASK (0xF000U) +#define TEMPSENSE_CTRL1_N_FILT_1_SHIFT (12U) +/*! N_FILT_1 - Filter Length for Threshold Flag */ +#define TEMPSENSE_CTRL1_N_FILT_1(x) (((uint32_t)(((uint32_t)(x)) << TEMPSENSE_CTRL1_N_FILT_1_SHIFT)) & TEMPSENSE_CTRL1_N_FILT_1_MASK) + +#define TEMPSENSE_CTRL1_DRDY1_IE_MASK (0x10000U) +#define TEMPSENSE_CTRL1_DRDY1_IE_SHIFT (16U) +/*! DRDY1_IE - Data-Ready Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define TEMPSENSE_CTRL1_DRDY1_IE(x) (((uint32_t)(((uint32_t)(x)) << TEMPSENSE_CTRL1_DRDY1_IE_SHIFT)) & TEMPSENSE_CTRL1_DRDY1_IE_MASK) + +#define TEMPSENSE_CTRL1_RESOLUTION_MASK (0xC0000U) +#define TEMPSENSE_CTRL1_RESOLUTION_SHIFT (18U) +/*! RESOLUTION - Resolution Mode + * 0b00..0.59325 ms + * 0b01..1.10525 ms + * 0b10..2.12925 ms + * 0b11..4.17725 ms + */ +#define TEMPSENSE_CTRL1_RESOLUTION(x) (((uint32_t)(((uint32_t)(x)) << TEMPSENSE_CTRL1_RESOLUTION_SHIFT)) & TEMPSENSE_CTRL1_RESOLUTION_MASK) + +#define TEMPSENSE_CTRL1_FILT4_CNT_CLR_MASK (0x100000U) +#define TEMPSENSE_CTRL1_FILT4_CNT_CLR_SHIFT (20U) +/*! FILT4_CNT_CLR - Filter 4 Counter Clear + * 0b0..Settle to 0 after clearing the counter + * 0b1..Clear the internal counter + */ +#define TEMPSENSE_CTRL1_FILT4_CNT_CLR(x) (((uint32_t)(((uint32_t)(x)) << TEMPSENSE_CTRL1_FILT4_CNT_CLR_SHIFT)) & TEMPSENSE_CTRL1_FILT4_CNT_CLR_MASK) + +#define TEMPSENSE_CTRL1_FILT5_CNT_CLR_MASK (0x200000U) +#define TEMPSENSE_CTRL1_FILT5_CNT_CLR_SHIFT (21U) +/*! FILT5_CNT_CLR - Filter 5 Counter Clear + * 0b0..Settle to 0 after clearing the counter + * 0b1..Clear the internal counter + */ +#define TEMPSENSE_CTRL1_FILT5_CNT_CLR(x) (((uint32_t)(((uint32_t)(x)) << TEMPSENSE_CTRL1_FILT5_CNT_CLR_SHIFT)) & TEMPSENSE_CTRL1_FILT5_CNT_CLR_MASK) + +#define TEMPSENSE_CTRL1_MEAS_MODE_MASK (0x3000000U) +#define TEMPSENSE_CTRL1_MEAS_MODE_SHIFT (24U) +/*! MEAS_MODE - Measurement Mode + * 0b00..Single One-Shot Measurement + * 0b01..Continuous Measurement + * 0b10..Periodic One-Shot Measurement + * 0b11..Reserved + */ +#define TEMPSENSE_CTRL1_MEAS_MODE(x) (((uint32_t)(((uint32_t)(x)) << TEMPSENSE_CTRL1_MEAS_MODE_SHIFT)) & TEMPSENSE_CTRL1_MEAS_MODE_MASK) + +#define TEMPSENSE_CTRL1_STOP_MASK (0x20000000U) +#define TEMPSENSE_CTRL1_STOP_SHIFT (29U) +/*! STOP - Stop Measurement + * 0b0..Clear after conversion is over + * 0b1..Stop the conversion + */ +#define TEMPSENSE_CTRL1_STOP(x) (((uint32_t)(((uint32_t)(x)) << TEMPSENSE_CTRL1_STOP_SHIFT)) & TEMPSENSE_CTRL1_STOP_MASK) + +#define TEMPSENSE_CTRL1_START_MASK (0x40000000U) +#define TEMPSENSE_CTRL1_START_SHIFT (30U) +/*! START - Start Measurement + * 0b0..No effect + * 0b1..Start the measurement + */ +#define TEMPSENSE_CTRL1_START(x) (((uint32_t)(((uint32_t)(x)) << TEMPSENSE_CTRL1_START_SHIFT)) & TEMPSENSE_CTRL1_START_MASK) + +#define TEMPSENSE_CTRL1_ENABLE_MASK (0x80000000U) +#define TEMPSENSE_CTRL1_ENABLE_SHIFT (31U) +/*! ENABLE - TEMPSENSE Enable + * 0b0..Disable + * 0b1..Enable + */ +#define TEMPSENSE_CTRL1_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << TEMPSENSE_CTRL1_ENABLE_SHIFT)) & TEMPSENSE_CTRL1_ENABLE_MASK) +/*! @} */ + +/*! @name STAT1 - Status 1 */ +/*! @{ */ + +#define TEMPSENSE_STAT1_THR4_IF_MASK (0x100U) +#define TEMPSENSE_STAT1_THR4_IF_SHIFT (8U) +/*! THR4_IF - Threshold4 Status Flag + * 0b0..Event did not occur + * 0b0..No effect + * 0b1..Event occurred + * 0b1..Clear the flag + */ +#define TEMPSENSE_STAT1_THR4_IF(x) (((uint32_t)(((uint32_t)(x)) << TEMPSENSE_STAT1_THR4_IF_SHIFT)) & TEMPSENSE_STAT1_THR4_IF_MASK) + +#define TEMPSENSE_STAT1_THR5_IF_MASK (0x200U) +#define TEMPSENSE_STAT1_THR5_IF_SHIFT (9U) +/*! THR5_IF - Threshold5 Status Flag + * 0b0..Event did not occur + * 0b0..No effect + * 0b1..Event occurred + * 0b1..Clear the flag + */ +#define TEMPSENSE_STAT1_THR5_IF(x) (((uint32_t)(((uint32_t)(x)) << TEMPSENSE_STAT1_THR5_IF_SHIFT)) & TEMPSENSE_STAT1_THR5_IF_MASK) + +#define TEMPSENSE_STAT1_THR4_STAT_MASK (0x1000U) +#define TEMPSENSE_STAT1_THR4_STAT_SHIFT (12U) +/*! THR4_STAT - Threshold4 State */ +#define TEMPSENSE_STAT1_THR4_STAT(x) (((uint32_t)(((uint32_t)(x)) << TEMPSENSE_STAT1_THR4_STAT_SHIFT)) & TEMPSENSE_STAT1_THR4_STAT_MASK) + +#define TEMPSENSE_STAT1_THR5_STAT_MASK (0x2000U) +#define TEMPSENSE_STAT1_THR5_STAT_SHIFT (13U) +/*! THR5_STAT - Threshold5 State */ +#define TEMPSENSE_STAT1_THR5_STAT(x) (((uint32_t)(((uint32_t)(x)) << TEMPSENSE_STAT1_THR5_STAT_SHIFT)) & TEMPSENSE_STAT1_THR5_STAT_MASK) + +#define TEMPSENSE_STAT1_DRDY1_IF_MASK (0x10000U) +#define TEMPSENSE_STAT1_DRDY1_IF_SHIFT (16U) +/*! DRDY1_IF - Data Ready Flag + * 0b0..No new data + * 0b1..New data + */ +#define TEMPSENSE_STAT1_DRDY1_IF(x) (((uint32_t)(((uint32_t)(x)) << TEMPSENSE_STAT1_DRDY1_IF_SHIFT)) & TEMPSENSE_STAT1_DRDY1_IF_MASK) + +#define TEMPSENSE_STAT1_IDLE_MASK (0x80000000U) +#define TEMPSENSE_STAT1_IDLE_SHIFT (31U) +/*! IDLE - Idle State + * 0b0..Conversion + * 0b1..Idle + */ +#define TEMPSENSE_STAT1_IDLE(x) (((uint32_t)(((uint32_t)(x)) << TEMPSENSE_STAT1_IDLE_SHIFT)) & TEMPSENSE_STAT1_IDLE_MASK) +/*! @} */ + +/*! @name DATA1 - Data 1 */ +/*! @{ */ + +#define TEMPSENSE_DATA1_DATA_VAL_MASK (0xFFFFU) +#define TEMPSENSE_DATA1_DATA_VAL_SHIFT (0U) +/*! DATA_VAL - Temperature Data Value */ +#define TEMPSENSE_DATA1_DATA_VAL(x) (((uint32_t)(((uint32_t)(x)) << TEMPSENSE_DATA1_DATA_VAL_SHIFT)) & TEMPSENSE_DATA1_DATA_VAL_MASK) +/*! @} */ + +/*! @name THR_CTRL45 - Threshold Control 45 */ +/*! @{ */ + +#define TEMPSENSE_THR_CTRL45_TEMPERATURE_THRESHOLD4_MASK (0xFFFFU) +#define TEMPSENSE_THR_CTRL45_TEMPERATURE_THRESHOLD4_SHIFT (0U) +/*! TEMPERATURE_THRESHOLD4 - Temperature Threshold4 */ +#define TEMPSENSE_THR_CTRL45_TEMPERATURE_THRESHOLD4(x) (((uint32_t)(((uint32_t)(x)) << TEMPSENSE_THR_CTRL45_TEMPERATURE_THRESHOLD4_SHIFT)) & TEMPSENSE_THR_CTRL45_TEMPERATURE_THRESHOLD4_MASK) + +#define TEMPSENSE_THR_CTRL45_TEMPERATURE_THRESHOLD5_MASK (0xFFFF0000U) +#define TEMPSENSE_THR_CTRL45_TEMPERATURE_THRESHOLD5_SHIFT (16U) +/*! TEMPERATURE_THRESHOLD5 - Temperature Threshold5 */ +#define TEMPSENSE_THR_CTRL45_TEMPERATURE_THRESHOLD5(x) (((uint32_t)(((uint32_t)(x)) << TEMPSENSE_THR_CTRL45_TEMPERATURE_THRESHOLD5_SHIFT)) & TEMPSENSE_THR_CTRL45_TEMPERATURE_THRESHOLD5_MASK) +/*! @} */ + +/*! @name PERIOD_CTRL - Measurement Period Control */ +/*! @{ */ + +#define TEMPSENSE_PERIOD_CTRL_MEAS_FREQ_MASK (0xFFFFFFU) +#define TEMPSENSE_PERIOD_CTRL_MEAS_FREQ_SHIFT (0U) +/*! MEAS_FREQ - TEMPSENSE Periodic Measurement Frequency */ +#define TEMPSENSE_PERIOD_CTRL_MEAS_FREQ(x) (((uint32_t)(((uint32_t)(x)) << TEMPSENSE_PERIOD_CTRL_MEAS_FREQ_SHIFT)) & TEMPSENSE_PERIOD_CTRL_MEAS_FREQ_MASK) +/*! @} */ + +/*! @name REF_DIV - Reference Clock Divider Control */ +/*! @{ */ + +#define TEMPSENSE_REF_DIV_DIV_MASK (0xFF0000U) +#define TEMPSENSE_REF_DIV_DIV_SHIFT (16U) +/*! DIV - Divider Value + * 0b00000000..Output clock frequency = input clock frequency + * 0b00000001..Output clock frequency = input clock frequency / 2 + * 0b00000010..Output clock frequency = input clock frequency / 3 + * 0b00000011..... + * 0b11111111..Output clock frequency = input clock frequency / 256 + */ +#define TEMPSENSE_REF_DIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << TEMPSENSE_REF_DIV_DIV_SHIFT)) & TEMPSENSE_REF_DIV_DIV_MASK) + +#define TEMPSENSE_REF_DIV_DE_MASK (0x80000000U) +#define TEMPSENSE_REF_DIV_DE_SHIFT (31U) +/*! DE - Divider Enable + * 0b0..Disable + * 0b1..Enable + */ +#define TEMPSENSE_REF_DIV_DE(x) (((uint32_t)(((uint32_t)(x)) << TEMPSENSE_REF_DIV_DE_SHIFT)) & TEMPSENSE_REF_DIV_DE_MASK) +/*! @} */ + +/*! @name PUD_ST_CTRL - Power-Up Delay Control */ +/*! @{ */ + +#define TEMPSENSE_PUD_ST_CTRL_PUD_MASK (0xFF0000U) +#define TEMPSENSE_PUD_ST_CTRL_PUD_SHIFT (16U) +/*! PUD - Power-Up Delay */ +#define TEMPSENSE_PUD_ST_CTRL_PUD(x) (((uint32_t)(((uint32_t)(x)) << TEMPSENSE_PUD_ST_CTRL_PUD_SHIFT)) & TEMPSENSE_PUD_ST_CTRL_PUD_MASK) +/*! @} */ + +/*! @name TRIM1 - Trim Control 1 */ +/*! @{ */ + +#define TEMPSENSE_TRIM1_VAL_A_MASK (0xFFFFU) +#define TEMPSENSE_TRIM1_VAL_A_SHIFT (0U) +/*! VAL_A - VAL_A */ +#define TEMPSENSE_TRIM1_VAL_A(x) (((uint32_t)(((uint32_t)(x)) << TEMPSENSE_TRIM1_VAL_A_SHIFT)) & TEMPSENSE_TRIM1_VAL_A_MASK) + +#define TEMPSENSE_TRIM1_VAL_B_MASK (0xFFFF0000U) +#define TEMPSENSE_TRIM1_VAL_B_SHIFT (16U) +/*! VAL_B - VAL_B */ +#define TEMPSENSE_TRIM1_VAL_B(x) (((uint32_t)(((uint32_t)(x)) << TEMPSENSE_TRIM1_VAL_B_SHIFT)) & TEMPSENSE_TRIM1_VAL_B_MASK) +/*! @} */ + +/*! @name TRIM2 - Trim Control 2 */ +/*! @{ */ + +#define TEMPSENSE_TRIM2_VAL_ALPHA_MASK (0xFFFFU) +#define TEMPSENSE_TRIM2_VAL_ALPHA_SHIFT (0U) +/*! VAL_ALPHA - VAL_ALPHA */ +#define TEMPSENSE_TRIM2_VAL_ALPHA(x) (((uint32_t)(((uint32_t)(x)) << TEMPSENSE_TRIM2_VAL_ALPHA_SHIFT)) & TEMPSENSE_TRIM2_VAL_ALPHA_MASK) + +#define TEMPSENSE_TRIM2_VAL_OFFSET_MASK (0xFFFF0000U) +#define TEMPSENSE_TRIM2_VAL_OFFSET_SHIFT (16U) +/*! VAL_OFFSET - VAL_OFFSET */ +#define TEMPSENSE_TRIM2_VAL_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << TEMPSENSE_TRIM2_VAL_OFFSET_SHIFT)) & TEMPSENSE_TRIM2_VAL_OFFSET_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group TEMPSENSE_Register_Masks */ + + +/* TEMPSENSE - Peripheral instance base addresses */ +/** Peripheral U_TEMP_ANAMIX base address */ +#define U_TEMP_ANAMIX_BASE (0x44482000u) +/** Peripheral U_TEMP_ANAMIX base pointer */ +#define U_TEMP_ANAMIX ((TEMPSENSE_Type *)U_TEMP_ANAMIX_BASE) +/** Array initializer of TEMPSENSE peripheral base addresses */ +#define TEMPSENSE_BASE_ADDRS { U_TEMP_ANAMIX_BASE } +/** Array initializer of TEMPSENSE peripheral base pointers */ +#define TEMPSENSE_BASE_PTRS { U_TEMP_ANAMIX } + +/*! + * @} + */ /* end of group TEMPSENSE_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- TPM Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup TPM_Peripheral_Access_Layer TPM Peripheral Access Layer + * @{ + */ + +/** TPM - Register Layout Typedef */ +typedef struct { + __I uint32_t VERID; /**< Version ID, offset: 0x0 */ + __I uint32_t PARAM; /**< Parameter, offset: 0x4 */ + __IO uint32_t GLOBAL; /**< TPM Global, offset: 0x8 */ + uint8_t RESERVED_0[4]; + __IO uint32_t SC; /**< Status and Control, offset: 0x10 */ + __IO uint32_t CNT; /**< Counter, offset: 0x14 */ + __IO uint32_t MOD; /**< Modulo, offset: 0x18 */ + __IO uint32_t STATUS; /**< Capture and Compare Status, offset: 0x1C */ + struct { /* offset: 0x20, array step: 0x8 */ + __IO uint32_t CnSC; /**< Channel n Status and Control, array offset: 0x20, array step: 0x8 */ + __IO uint32_t CnV; /**< Channel n Value, array offset: 0x24, array step: 0x8 */ + } CONTROLS[4]; + uint8_t RESERVED_1[36]; + __IO uint32_t COMBINE; /**< Combine Channel, offset: 0x64 */ + uint8_t RESERVED_2[4]; + __IO uint32_t TRIG; /**< Channel Trigger, offset: 0x6C */ + __IO uint32_t POL; /**< Channel Polarity, offset: 0x70 */ + uint8_t RESERVED_3[4]; + __IO uint32_t FILTER; /**< Filter Control, offset: 0x78 */ + uint8_t RESERVED_4[4]; + __IO uint32_t QDCTRL; /**< Quadrature Decoder Control and Status, offset: 0x80 */ + __IO uint32_t CONF; /**< Configuration, offset: 0x84 */ +} TPM_Type; + +/* ---------------------------------------------------------------------------- + -- TPM Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup TPM_Register_Masks TPM Register Masks + * @{ + */ + +/*! @name VERID - Version ID */ +/*! @{ */ + +#define TPM_VERID_FEATURE_MASK (0xFFFFU) +#define TPM_VERID_FEATURE_SHIFT (0U) +/*! FEATURE - Feature Identification Number + * 0b0000000000000001..Standard feature set + * 0b0000000000000011..Standard feature set with the filter and combine registers implemented + * 0b0000000000000101..Standard feature set with the quadrature register implemented + * 0b0000000000000111..Standard feature set with the filter, combine, and quadrature registers implemented + */ +#define TPM_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << TPM_VERID_FEATURE_SHIFT)) & TPM_VERID_FEATURE_MASK) + +#define TPM_VERID_MINOR_MASK (0xFF0000U) +#define TPM_VERID_MINOR_SHIFT (16U) +/*! MINOR - Minor Version Number */ +#define TPM_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << TPM_VERID_MINOR_SHIFT)) & TPM_VERID_MINOR_MASK) + +#define TPM_VERID_MAJOR_MASK (0xFF000000U) +#define TPM_VERID_MAJOR_SHIFT (24U) +/*! MAJOR - Major Version Number */ +#define TPM_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << TPM_VERID_MAJOR_SHIFT)) & TPM_VERID_MAJOR_MASK) +/*! @} */ + +/*! @name PARAM - Parameter */ +/*! @{ */ + +#define TPM_PARAM_CHAN_MASK (0xFFU) +#define TPM_PARAM_CHAN_SHIFT (0U) +/*! CHAN - Channel Count */ +#define TPM_PARAM_CHAN(x) (((uint32_t)(((uint32_t)(x)) << TPM_PARAM_CHAN_SHIFT)) & TPM_PARAM_CHAN_MASK) + +#define TPM_PARAM_TRIG_MASK (0xFF00U) +#define TPM_PARAM_TRIG_SHIFT (8U) +/*! TRIG - Trigger Count */ +#define TPM_PARAM_TRIG(x) (((uint32_t)(((uint32_t)(x)) << TPM_PARAM_TRIG_SHIFT)) & TPM_PARAM_TRIG_MASK) + +#define TPM_PARAM_WIDTH_MASK (0xFF0000U) +#define TPM_PARAM_WIDTH_SHIFT (16U) +/*! WIDTH - Counter Width */ +#define TPM_PARAM_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << TPM_PARAM_WIDTH_SHIFT)) & TPM_PARAM_WIDTH_MASK) +/*! @} */ + +/*! @name GLOBAL - TPM Global */ +/*! @{ */ + +#define TPM_GLOBAL_NOUPDATE_MASK (0x1U) +#define TPM_GLOBAL_NOUPDATE_SHIFT (0U) +/*! NOUPDATE - No Update + * 0b0..Internal double-buffered registers update as normal + * 0b1..Internal double-buffered registers do not update + */ +#define TPM_GLOBAL_NOUPDATE(x) (((uint32_t)(((uint32_t)(x)) << TPM_GLOBAL_NOUPDATE_SHIFT)) & TPM_GLOBAL_NOUPDATE_MASK) + +#define TPM_GLOBAL_RST_MASK (0x2U) +#define TPM_GLOBAL_RST_SHIFT (1U) +/*! RST - Software Reset + * 0b0..Module is not reset + * 0b1..Module is reset + */ +#define TPM_GLOBAL_RST(x) (((uint32_t)(((uint32_t)(x)) << TPM_GLOBAL_RST_SHIFT)) & TPM_GLOBAL_RST_MASK) +/*! @} */ + +/*! @name SC - Status and Control */ +/*! @{ */ + +#define TPM_SC_PS_MASK (0x7U) +#define TPM_SC_PS_SHIFT (0U) +/*! PS - Prescale Factor Selection + * 0b000..Divide by 1 + * 0b001..Divide by 2 + * 0b010..Divide by 4 + * 0b011..Divide by 8 + * 0b100..Divide by 16 + * 0b101..Divide by 32 + * 0b110..Divide by 64 + * 0b111..Divide by 128 + */ +#define TPM_SC_PS(x) (((uint32_t)(((uint32_t)(x)) << TPM_SC_PS_SHIFT)) & TPM_SC_PS_MASK) + +#define TPM_SC_CMOD_MASK (0x18U) +#define TPM_SC_CMOD_SHIFT (3U) +/*! CMOD - Clock Mode Selection + * 0b00..TPM counter is disabled + * 0b01..TPM counter increments on every TPM counter clock + * 0b10..TPM counter increments on the rising edge of EXTCLK synchronized to the TPM counter clock + * 0b11..TPM counter increments on the rising edge of the selected external input trigger + */ +#define TPM_SC_CMOD(x) (((uint32_t)(((uint32_t)(x)) << TPM_SC_CMOD_SHIFT)) & TPM_SC_CMOD_MASK) + +#define TPM_SC_CPWMS_MASK (0x20U) +#define TPM_SC_CPWMS_SHIFT (5U) +/*! CPWMS - Center-Aligned PWM Select + * 0b0..Up counting mode + * 0b1..Up-down counting mode + */ +#define TPM_SC_CPWMS(x) (((uint32_t)(((uint32_t)(x)) << TPM_SC_CPWMS_SHIFT)) & TPM_SC_CPWMS_MASK) + +#define TPM_SC_TOIE_MASK (0x40U) +#define TPM_SC_TOIE_SHIFT (6U) +/*! TOIE - Timer Overflow Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define TPM_SC_TOIE(x) (((uint32_t)(((uint32_t)(x)) << TPM_SC_TOIE_SHIFT)) & TPM_SC_TOIE_MASK) + +#define TPM_SC_TOF_MASK (0x80U) +#define TPM_SC_TOF_SHIFT (7U) +/*! TOF - Timer Overflow Flag + * 0b0..No overflow + * 0b1..Overflow + */ +#define TPM_SC_TOF(x) (((uint32_t)(((uint32_t)(x)) << TPM_SC_TOF_SHIFT)) & TPM_SC_TOF_MASK) + +#define TPM_SC_DMA_MASK (0x100U) +#define TPM_SC_DMA_SHIFT (8U) +/*! DMA - DMA Enable + * 0b0..Disable + * 0b1..Enable + */ +#define TPM_SC_DMA(x) (((uint32_t)(((uint32_t)(x)) << TPM_SC_DMA_SHIFT)) & TPM_SC_DMA_MASK) +/*! @} */ + +/*! @name CNT - Counter */ +/*! @{ */ + +#define TPM_CNT_COUNT_MASK (0xFFFFFFFFU) +#define TPM_CNT_COUNT_SHIFT (0U) +/*! COUNT - Counter Value */ +#define TPM_CNT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << TPM_CNT_COUNT_SHIFT)) & TPM_CNT_COUNT_MASK) +/*! @} */ + +/*! @name MOD - Modulo */ +/*! @{ */ + +#define TPM_MOD_MOD_MASK (0xFFFFFFFFU) +#define TPM_MOD_MOD_SHIFT (0U) +/*! MOD - Modulo Value */ +#define TPM_MOD_MOD(x) (((uint32_t)(((uint32_t)(x)) << TPM_MOD_MOD_SHIFT)) & TPM_MOD_MOD_MASK) +/*! @} */ + +/*! @name STATUS - Capture and Compare Status */ +/*! @{ */ + +#define TPM_STATUS_CH0F_MASK (0x1U) +#define TPM_STATUS_CH0F_SHIFT (0U) +/*! CH0F - Channel 0 Flag + * 0b0..Event not occurred + * 0b1..Event occurred + */ +#define TPM_STATUS_CH0F(x) (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_CH0F_SHIFT)) & TPM_STATUS_CH0F_MASK) + +#define TPM_STATUS_CH1F_MASK (0x2U) +#define TPM_STATUS_CH1F_SHIFT (1U) +/*! CH1F - Channel 1 Flag + * 0b0..Event not occurred + * 0b1..Event occurred + */ +#define TPM_STATUS_CH1F(x) (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_CH1F_SHIFT)) & TPM_STATUS_CH1F_MASK) + +#define TPM_STATUS_CH2F_MASK (0x4U) +#define TPM_STATUS_CH2F_SHIFT (2U) +/*! CH2F - Channel 2 Flag + * 0b0..Event not occurred + * 0b1..Event occurred + */ +#define TPM_STATUS_CH2F(x) (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_CH2F_SHIFT)) & TPM_STATUS_CH2F_MASK) + +#define TPM_STATUS_CH3F_MASK (0x8U) +#define TPM_STATUS_CH3F_SHIFT (3U) +/*! CH3F - Channel 3 Flag + * 0b0..Event not occurred + * 0b1..Event occurred + */ +#define TPM_STATUS_CH3F(x) (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_CH3F_SHIFT)) & TPM_STATUS_CH3F_MASK) + +#define TPM_STATUS_TOF_MASK (0x100U) +#define TPM_STATUS_TOF_SHIFT (8U) +/*! TOF - Timer Overflow Flag + * 0b0..No overflow + * 0b1..Overflow + */ +#define TPM_STATUS_TOF(x) (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_TOF_SHIFT)) & TPM_STATUS_TOF_MASK) +/*! @} */ + +/*! @name CnSC - Channel n Status and Control */ +/*! @{ */ + +#define TPM_CnSC_DMA_MASK (0x1U) +#define TPM_CnSC_DMA_SHIFT (0U) +/*! DMA - DMA Enable + * 0b0..Disable + * 0b1..Enable + */ +#define TPM_CnSC_DMA(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_DMA_SHIFT)) & TPM_CnSC_DMA_MASK) + +#define TPM_CnSC_ELSA_MASK (0x4U) +#define TPM_CnSC_ELSA_SHIFT (2U) +/*! ELSA - Edge or Level Select A */ +#define TPM_CnSC_ELSA(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_ELSA_SHIFT)) & TPM_CnSC_ELSA_MASK) + +#define TPM_CnSC_ELSB_MASK (0x8U) +#define TPM_CnSC_ELSB_SHIFT (3U) +/*! ELSB - Edge or Level Select B */ +#define TPM_CnSC_ELSB(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_ELSB_SHIFT)) & TPM_CnSC_ELSB_MASK) + +#define TPM_CnSC_MSA_MASK (0x10U) +#define TPM_CnSC_MSA_SHIFT (4U) +/*! MSA - Channel Mode Select A */ +#define TPM_CnSC_MSA(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_MSA_SHIFT)) & TPM_CnSC_MSA_MASK) + +#define TPM_CnSC_MSB_MASK (0x20U) +#define TPM_CnSC_MSB_SHIFT (5U) +/*! MSB - Channel Mode Select B */ +#define TPM_CnSC_MSB(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_MSB_SHIFT)) & TPM_CnSC_MSB_MASK) + +#define TPM_CnSC_CHIE_MASK (0x40U) +#define TPM_CnSC_CHIE_SHIFT (6U) +/*! CHIE - Channel Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define TPM_CnSC_CHIE(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_CHIE_SHIFT)) & TPM_CnSC_CHIE_MASK) + +#define TPM_CnSC_CHF_MASK (0x80U) +#define TPM_CnSC_CHF_SHIFT (7U) +/*! CHF - Channel Flag + * 0b0..Event not occurred + * 0b1..Event occurred + */ +#define TPM_CnSC_CHF(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_CHF_SHIFT)) & TPM_CnSC_CHF_MASK) +/*! @} */ + +/* The count of TPM_CnSC */ +#define TPM_CnSC_COUNT (4U) + +/*! @name CnV - Channel n Value */ +/*! @{ */ + +#define TPM_CnV_VAL_MASK (0xFFFFFFFFU) +#define TPM_CnV_VAL_SHIFT (0U) +/*! VAL - Channel Value */ +#define TPM_CnV_VAL(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnV_VAL_SHIFT)) & TPM_CnV_VAL_MASK) +/*! @} */ + +/* The count of TPM_CnV */ +#define TPM_CnV_COUNT (4U) + +/*! @name COMBINE - Combine Channel */ +/*! @{ */ + +#define TPM_COMBINE_COMBINE0_MASK (0x1U) +#define TPM_COMBINE_COMBINE0_SHIFT (0U) +/*! COMBINE0 - Combine Channels 0 and 1 + * 0b0..Independent + * 0b1..Combined + */ +#define TPM_COMBINE_COMBINE0(x) (((uint32_t)(((uint32_t)(x)) << TPM_COMBINE_COMBINE0_SHIFT)) & TPM_COMBINE_COMBINE0_MASK) + +#define TPM_COMBINE_COMSWAP0_MASK (0x2U) +#define TPM_COMBINE_COMSWAP0_SHIFT (1U) +/*! COMSWAP0 - Combine Channel 0 and 1 Swap + * 0b0..Even channel + * 0b1..Odd channel + */ +#define TPM_COMBINE_COMSWAP0(x) (((uint32_t)(((uint32_t)(x)) << TPM_COMBINE_COMSWAP0_SHIFT)) & TPM_COMBINE_COMSWAP0_MASK) + +#define TPM_COMBINE_COMBINE1_MASK (0x100U) +#define TPM_COMBINE_COMBINE1_SHIFT (8U) +/*! COMBINE1 - Combine Channels 2 and 3 + * 0b0..Independent + * 0b1..Combined + */ +#define TPM_COMBINE_COMBINE1(x) (((uint32_t)(((uint32_t)(x)) << TPM_COMBINE_COMBINE1_SHIFT)) & TPM_COMBINE_COMBINE1_MASK) + +#define TPM_COMBINE_COMSWAP1_MASK (0x200U) +#define TPM_COMBINE_COMSWAP1_SHIFT (9U) +/*! COMSWAP1 - Combine Channels 2 and 3 Swap + * 0b0..Even channel + * 0b1..Odd channel + */ +#define TPM_COMBINE_COMSWAP1(x) (((uint32_t)(((uint32_t)(x)) << TPM_COMBINE_COMSWAP1_SHIFT)) & TPM_COMBINE_COMSWAP1_MASK) +/*! @} */ + +/*! @name TRIG - Channel Trigger */ +/*! @{ */ + +#define TPM_TRIG_TRIG0_MASK (0x1U) +#define TPM_TRIG_TRIG0_SHIFT (0U) +/*! TRIG0 - Channel 0 Trigger + * 0b0..No effect + * 0b1..Configures trigger input 0 to be used by channel 0 + */ +#define TPM_TRIG_TRIG0(x) (((uint32_t)(((uint32_t)(x)) << TPM_TRIG_TRIG0_SHIFT)) & TPM_TRIG_TRIG0_MASK) + +#define TPM_TRIG_TRIG1_MASK (0x2U) +#define TPM_TRIG_TRIG1_SHIFT (1U) +/*! TRIG1 - Channel 1 Trigger + * 0b0..No effect + * 0b1..Configures trigger input 1 to be used by channel 1 + */ +#define TPM_TRIG_TRIG1(x) (((uint32_t)(((uint32_t)(x)) << TPM_TRIG_TRIG1_SHIFT)) & TPM_TRIG_TRIG1_MASK) + +#define TPM_TRIG_TRIG2_MASK (0x4U) +#define TPM_TRIG_TRIG2_SHIFT (2U) +/*! TRIG2 - Channel 2 Trigger + * 0b0..No effect + * 0b1..Configures trigger input 0 to be used by channel 2 + */ +#define TPM_TRIG_TRIG2(x) (((uint32_t)(((uint32_t)(x)) << TPM_TRIG_TRIG2_SHIFT)) & TPM_TRIG_TRIG2_MASK) + +#define TPM_TRIG_TRIG3_MASK (0x8U) +#define TPM_TRIG_TRIG3_SHIFT (3U) +/*! TRIG3 - Channel 3 Trigger + * 0b0..No effect + * 0b1..Configures trigger input 1 to be used by channel 3 + */ +#define TPM_TRIG_TRIG3(x) (((uint32_t)(((uint32_t)(x)) << TPM_TRIG_TRIG3_SHIFT)) & TPM_TRIG_TRIG3_MASK) +/*! @} */ + +/*! @name POL - Channel Polarity */ +/*! @{ */ + +#define TPM_POL_POL0_MASK (0x1U) +#define TPM_POL_POL0_SHIFT (0U) +/*! POL0 - Channel 0 Polarity + * 0b0..Active high + * 0b1..Active low + */ +#define TPM_POL_POL0(x) (((uint32_t)(((uint32_t)(x)) << TPM_POL_POL0_SHIFT)) & TPM_POL_POL0_MASK) + +#define TPM_POL_POL1_MASK (0x2U) +#define TPM_POL_POL1_SHIFT (1U) +/*! POL1 - Channel 1 Polarity + * 0b0..Active high + * 0b1..Active low + */ +#define TPM_POL_POL1(x) (((uint32_t)(((uint32_t)(x)) << TPM_POL_POL1_SHIFT)) & TPM_POL_POL1_MASK) + +#define TPM_POL_POL2_MASK (0x4U) +#define TPM_POL_POL2_SHIFT (2U) +/*! POL2 - Channel 2 Polarity + * 0b0..Active high + * 0b1..Active low + */ +#define TPM_POL_POL2(x) (((uint32_t)(((uint32_t)(x)) << TPM_POL_POL2_SHIFT)) & TPM_POL_POL2_MASK) + +#define TPM_POL_POL3_MASK (0x8U) +#define TPM_POL_POL3_SHIFT (3U) +/*! POL3 - Channel 3 Polarity + * 0b0..Active high + * 0b1..Active low + */ +#define TPM_POL_POL3(x) (((uint32_t)(((uint32_t)(x)) << TPM_POL_POL3_SHIFT)) & TPM_POL_POL3_MASK) +/*! @} */ + +/*! @name FILTER - Filter Control */ +/*! @{ */ + +#define TPM_FILTER_CH0FVAL_MASK (0xFU) +#define TPM_FILTER_CH0FVAL_SHIFT (0U) +/*! CH0FVAL - Channel 0 Filter Value */ +#define TPM_FILTER_CH0FVAL(x) (((uint32_t)(((uint32_t)(x)) << TPM_FILTER_CH0FVAL_SHIFT)) & TPM_FILTER_CH0FVAL_MASK) + +#define TPM_FILTER_CH1FVAL_MASK (0xF0U) +#define TPM_FILTER_CH1FVAL_SHIFT (4U) +/*! CH1FVAL - Channel 1 Filter Value */ +#define TPM_FILTER_CH1FVAL(x) (((uint32_t)(((uint32_t)(x)) << TPM_FILTER_CH1FVAL_SHIFT)) & TPM_FILTER_CH1FVAL_MASK) + +#define TPM_FILTER_CH2FVAL_MASK (0xF00U) +#define TPM_FILTER_CH2FVAL_SHIFT (8U) +/*! CH2FVAL - Channel 2 Filter Value */ +#define TPM_FILTER_CH2FVAL(x) (((uint32_t)(((uint32_t)(x)) << TPM_FILTER_CH2FVAL_SHIFT)) & TPM_FILTER_CH2FVAL_MASK) + +#define TPM_FILTER_CH3FVAL_MASK (0xF000U) +#define TPM_FILTER_CH3FVAL_SHIFT (12U) +/*! CH3FVAL - Channel 3 Filter Value */ +#define TPM_FILTER_CH3FVAL(x) (((uint32_t)(((uint32_t)(x)) << TPM_FILTER_CH3FVAL_SHIFT)) & TPM_FILTER_CH3FVAL_MASK) +/*! @} */ + +/*! @name QDCTRL - Quadrature Decoder Control and Status */ +/*! @{ */ + +#define TPM_QDCTRL_QUADEN_MASK (0x1U) +#define TPM_QDCTRL_QUADEN_SHIFT (0U) +/*! QUADEN - Quadrature Decoder Enable + * 0b0..Disable + * 0b1..Enable + */ +#define TPM_QDCTRL_QUADEN(x) (((uint32_t)(((uint32_t)(x)) << TPM_QDCTRL_QUADEN_SHIFT)) & TPM_QDCTRL_QUADEN_MASK) + +#define TPM_QDCTRL_TOFDIR_MASK (0x2U) +#define TPM_QDCTRL_TOFDIR_SHIFT (1U) +/*! TOFDIR - Timer Overflow Direction + * 0b0..Bottom of counting + * 0b1..Top of counting + */ +#define TPM_QDCTRL_TOFDIR(x) (((uint32_t)(((uint32_t)(x)) << TPM_QDCTRL_TOFDIR_SHIFT)) & TPM_QDCTRL_TOFDIR_MASK) + +#define TPM_QDCTRL_QUADIR_MASK (0x4U) +#define TPM_QDCTRL_QUADIR_SHIFT (2U) +/*! QUADIR - Counter Direction in Quadrature Decode Mode + * 0b0..Decreasing (counter decrement) + * 0b1..Increasing (counter increment) + */ +#define TPM_QDCTRL_QUADIR(x) (((uint32_t)(((uint32_t)(x)) << TPM_QDCTRL_QUADIR_SHIFT)) & TPM_QDCTRL_QUADIR_MASK) + +#define TPM_QDCTRL_QUADMODE_MASK (0x8U) +#define TPM_QDCTRL_QUADMODE_SHIFT (3U) +/*! QUADMODE - Quadrature Decoder Mode + * 0b0..Phase encoding mode + * 0b1..Count and direction encoding mode + */ +#define TPM_QDCTRL_QUADMODE(x) (((uint32_t)(((uint32_t)(x)) << TPM_QDCTRL_QUADMODE_SHIFT)) & TPM_QDCTRL_QUADMODE_MASK) +/*! @} */ + +/*! @name CONF - Configuration */ +/*! @{ */ + +#define TPM_CONF_DOZEEN_MASK (0x20U) +#define TPM_CONF_DOZEEN_SHIFT (5U) +/*! DOZEEN - Doze Enable + * 0b0..TPM counter continues + * 0b1..TPM counter pauses + */ +#define TPM_CONF_DOZEEN(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_DOZEEN_SHIFT)) & TPM_CONF_DOZEEN_MASK) + +#define TPM_CONF_DBGMODE_MASK (0xC0U) +#define TPM_CONF_DBGMODE_SHIFT (6U) +/*! DBGMODE - Debug Mode + * 0b00..TPM counter pauses + * 0b11..TPM counter continues + */ +#define TPM_CONF_DBGMODE(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_DBGMODE_SHIFT)) & TPM_CONF_DBGMODE_MASK) + +#define TPM_CONF_GTBSYNC_MASK (0x100U) +#define TPM_CONF_GTBSYNC_SHIFT (8U) +/*! GTBSYNC - GTB Synchronization + * 0b0..Disable + * 0b1..Enable + */ +#define TPM_CONF_GTBSYNC(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_GTBSYNC_SHIFT)) & TPM_CONF_GTBSYNC_MASK) + +#define TPM_CONF_GTBEEN_MASK (0x200U) +#define TPM_CONF_GTBEEN_SHIFT (9U) +/*! GTBEEN - GTB Enable + * 0b0..Internally generated TPM counter + * 0b1..Externally generated GTB counter + */ +#define TPM_CONF_GTBEEN(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_GTBEEN_SHIFT)) & TPM_CONF_GTBEEN_MASK) + +#define TPM_CONF_CSOT_MASK (0x10000U) +#define TPM_CONF_CSOT_SHIFT (16U) +/*! CSOT - Counter Start on Trigger + * 0b0..Counter starts immediately + * 0b1..Counter starts after detection of a rising edge on the selected input trigger + */ +#define TPM_CONF_CSOT(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_CSOT_SHIFT)) & TPM_CONF_CSOT_MASK) + +#define TPM_CONF_CSOO_MASK (0x20000U) +#define TPM_CONF_CSOO_SHIFT (17U) +/*! CSOO - Counter Stop on Overflow + * 0b0..TPM counter continues + * 0b1..TPM counter stops + */ +#define TPM_CONF_CSOO(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_CSOO_SHIFT)) & TPM_CONF_CSOO_MASK) + +#define TPM_CONF_CROT_MASK (0x40000U) +#define TPM_CONF_CROT_SHIFT (18U) +/*! CROT - Counter Reload on Trigger + * 0b0..No reload + * 0b1..Reload + */ +#define TPM_CONF_CROT(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_CROT_SHIFT)) & TPM_CONF_CROT_MASK) + +#define TPM_CONF_CPOT_MASK (0x80000U) +#define TPM_CONF_CPOT_SHIFT (19U) +/*! CPOT - Counter Pause on Trigger + * 0b0..TPM counter continues + * 0b1..TPM counter pauses + */ +#define TPM_CONF_CPOT(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_CPOT_SHIFT)) & TPM_CONF_CPOT_MASK) + +#define TPM_CONF_TRGPOL_MASK (0x400000U) +#define TPM_CONF_TRGPOL_SHIFT (22U) +/*! TRGPOL - Trigger Polarity + * 0b0..Active high + * 0b1..Active low + */ +#define TPM_CONF_TRGPOL(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_TRGPOL_SHIFT)) & TPM_CONF_TRGPOL_MASK) + +#define TPM_CONF_TRGSRC_MASK (0x800000U) +#define TPM_CONF_TRGSRC_SHIFT (23U) +/*! TRGSRC - Trigger Source + * 0b0..External + * 0b1..Internal (channel pin input capture) + */ +#define TPM_CONF_TRGSRC(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_TRGSRC_SHIFT)) & TPM_CONF_TRGSRC_MASK) + +#define TPM_CONF_TRGSEL_MASK (0x3000000U) +#define TPM_CONF_TRGSEL_SHIFT (24U) +/*! TRGSEL - Trigger Select + * 0b01..Channel 0 pin input capture + * 0b10..Channel 1 pin input capture + * 0b11..Channel 0 or channel 1 pin input capture + */ +#define TPM_CONF_TRGSEL(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_TRGSEL_SHIFT)) & TPM_CONF_TRGSEL_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group TPM_Register_Masks */ + + +/* TPM - Peripheral instance base addresses */ +/** Peripheral TPM1 base address */ +#define TPM1_BASE (0x44310000u) +/** Peripheral TPM1 base pointer */ +#define TPM1 ((TPM_Type *)TPM1_BASE) +/** Peripheral TPM2 base address */ +#define TPM2_BASE (0x44320000u) +/** Peripheral TPM2 base pointer */ +#define TPM2 ((TPM_Type *)TPM2_BASE) +/** Peripheral TPM3 base address */ +#define TPM3_BASE (0x424E0000u) +/** Peripheral TPM3 base pointer */ +#define TPM3 ((TPM_Type *)TPM3_BASE) +/** Peripheral TPM4 base address */ +#define TPM4_BASE (0x424F0000u) +/** Peripheral TPM4 base pointer */ +#define TPM4 ((TPM_Type *)TPM4_BASE) +/** Peripheral TPM5 base address */ +#define TPM5_BASE (0x42500000u) +/** Peripheral TPM5 base pointer */ +#define TPM5 ((TPM_Type *)TPM5_BASE) +/** Peripheral TPM6 base address */ +#define TPM6_BASE (0x42510000u) +/** Peripheral TPM6 base pointer */ +#define TPM6 ((TPM_Type *)TPM6_BASE) +/** Array initializer of TPM peripheral base addresses */ +#define TPM_BASE_ADDRS { TPM1_BASE, TPM2_BASE, TPM3_BASE, TPM4_BASE, TPM5_BASE, TPM6_BASE } +/** Array initializer of TPM peripheral base pointers */ +#define TPM_BASE_PTRS { TPM1, TPM2, TPM3, TPM4, TPM5, TPM6 } +/** Interrupt vectors for the TPM peripheral type */ +#define TPM_IRQS { TPM1_IRQn, TPM2_IRQn, TPM3_IRQn, TPM4_IRQn, TPM5_IRQn, TPM6_IRQn } + +/*! + * @} + */ /* end of group TPM_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- TRDC_MBC0 Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup TRDC_MBC0_Peripheral_Access_Layer TRDC_MBC0 Peripheral Access Layer + * @{ + */ + +/** TRDC_MBC0 - Register Layout Typedef */ +typedef struct { + __IO uint32_t TRDC_CR; /**< TRDC Register, offset: 0x0 */ + uint8_t RESERVED_0[236]; + __I uint32_t TRDC_HWCFG0; /**< TRDC Hardware Configuration Register 0, offset: 0xF0 */ + __I uint32_t TRDC_HWCFG1; /**< TRDC Hardware Configuration Register 1, offset: 0xF4 */ + uint8_t RESERVED_1[8]; + __I uint8_t DACFG[7]; /**< Domain Assignment Configuration Register, array offset: 0x100, array step: 0x1, irregular array, not all indices are valid */ + uint8_t RESERVED_2[185]; + __IO uint32_t TRDC_IDAU_CR; /**< TRDC IDAU Control Register, offset: 0x1C0 */ + uint8_t RESERVED_3[28]; + __IO uint32_t TRDC_FLW_CTL; /**< TRDC FLW Control, offset: 0x1E0 */ + __I uint32_t TRDC_FLW_PBASE; /**< TRDC FLW Physical Base, offset: 0x1E4 */ + __IO uint32_t TRDC_FLW_ABASE; /**< TRDC FLW Array Base, offset: 0x1E8 */ + __IO uint32_t TRDC_FLW_BCNT; /**< TRDC FLW Block Count, offset: 0x1EC */ + uint8_t RESERVED_4[12]; + __IO uint32_t TRDC_FDID; /**< TRDC Fault Domain ID, offset: 0x1FC */ + __I uint32_t TRDC_DERRLOC[16]; /**< TRDC Domain Error Location Register, array offset: 0x200, array step: 0x4 */ + uint8_t RESERVED_5[1472]; + struct { /* offset: 0x800, array step: 0x20 */ + struct { /* offset: 0x800, array step: index*0x20, index2*0x4 */ + __IO uint32_t MDA_W_DFMT1; /**< DAC Master Domain Assignment Register, array offset: 0x800, array step: index*0x20, index2*0x4, irregular array, not all indices are valid */ + } MDA_Wx_DFMT1[1]; + uint8_t RESERVED_0[28]; + } MDA_Wx_y_DFMT[7]; +} TRDC_MBC0_Type; + +/* ---------------------------------------------------------------------------- + -- TRDC_MBC0 Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup TRDC_MBC0_Register_Masks TRDC_MBC0 Register Masks + * @{ + */ + +/*! @name TRDC_CR - TRDC Register */ +/*! @{ */ + +#define TRDC_MBC0_TRDC_CR_GVLDM_MASK (0x1U) +#define TRDC_MBC0_TRDC_CR_GVLDM_SHIFT (0U) +/*! GVLDM - Global Valid for Domain Assignment Controllers + * 0b0..TRDC DACs are disabled. + * 0b1..TRDC DACs are enabled. + */ +#define TRDC_MBC0_TRDC_CR_GVLDM(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC0_TRDC_CR_GVLDM_SHIFT)) & TRDC_MBC0_TRDC_CR_GVLDM_MASK) + +#define TRDC_MBC0_TRDC_CR_HRL_MASK (0x1EU) +#define TRDC_MBC0_TRDC_CR_HRL_SHIFT (1U) +/*! HRL - Hardware Revision Level */ +#define TRDC_MBC0_TRDC_CR_HRL(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC0_TRDC_CR_HRL_SHIFT)) & TRDC_MBC0_TRDC_CR_HRL_MASK) + +#define TRDC_MBC0_TRDC_CR_GVLDB_MASK (0x4000U) +#define TRDC_MBC0_TRDC_CR_GVLDB_SHIFT (14U) +/*! GVLDB - Global Valid for Memory Block Checkers + * 0b0..TRDC MBCs are disabled. + * 0b1..TRDC MBCs are enabled. + */ +#define TRDC_MBC0_TRDC_CR_GVLDB(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC0_TRDC_CR_GVLDB_SHIFT)) & TRDC_MBC0_TRDC_CR_GVLDB_MASK) + +#define TRDC_MBC0_TRDC_CR_GVLDR_MASK (0x8000U) +#define TRDC_MBC0_TRDC_CR_GVLDR_SHIFT (15U) +/*! GVLDR - Global Valid for Memory Region Checkers + * 0b0..TRDC MRCs are disabled. + * 0b1..TRDC MRCs are enabled. + */ +#define TRDC_MBC0_TRDC_CR_GVLDR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC0_TRDC_CR_GVLDR_SHIFT)) & TRDC_MBC0_TRDC_CR_GVLDR_MASK) + +#define TRDC_MBC0_TRDC_CR_LK1_MASK (0x40000000U) +#define TRDC_MBC0_TRDC_CR_LK1_SHIFT (30U) +/*! LK1 - Lock Status + * 0b0..The CR can be written by any secure privileged write. + * 0b1..The CR is locked (read-only) until the next reset. + */ +#define TRDC_MBC0_TRDC_CR_LK1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC0_TRDC_CR_LK1_SHIFT)) & TRDC_MBC0_TRDC_CR_LK1_MASK) +/*! @} */ + +/*! @name TRDC_HWCFG0 - TRDC Hardware Configuration Register 0 */ +/*! @{ */ + +#define TRDC_MBC0_TRDC_HWCFG0_NDID_MASK (0x1FU) +#define TRDC_MBC0_TRDC_HWCFG0_NDID_SHIFT (0U) +/*! NDID - Number of domains */ +#define TRDC_MBC0_TRDC_HWCFG0_NDID(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC0_TRDC_HWCFG0_NDID_SHIFT)) & TRDC_MBC0_TRDC_HWCFG0_NDID_MASK) + +#define TRDC_MBC0_TRDC_HWCFG0_NMSTR_MASK (0xFF00U) +#define TRDC_MBC0_TRDC_HWCFG0_NMSTR_SHIFT (8U) +/*! NMSTR - Number of bus masters */ +#define TRDC_MBC0_TRDC_HWCFG0_NMSTR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC0_TRDC_HWCFG0_NMSTR_SHIFT)) & TRDC_MBC0_TRDC_HWCFG0_NMSTR_MASK) + +#define TRDC_MBC0_TRDC_HWCFG0_NMBC_MASK (0xF0000U) +#define TRDC_MBC0_TRDC_HWCFG0_NMBC_SHIFT (16U) +/*! NMBC - Number of MBCs */ +#define TRDC_MBC0_TRDC_HWCFG0_NMBC(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC0_TRDC_HWCFG0_NMBC_SHIFT)) & TRDC_MBC0_TRDC_HWCFG0_NMBC_MASK) + +#define TRDC_MBC0_TRDC_HWCFG0_NMRC_MASK (0x1F000000U) +#define TRDC_MBC0_TRDC_HWCFG0_NMRC_SHIFT (24U) +/*! NMRC - Number of MRCs */ +#define TRDC_MBC0_TRDC_HWCFG0_NMRC(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC0_TRDC_HWCFG0_NMRC_SHIFT)) & TRDC_MBC0_TRDC_HWCFG0_NMRC_MASK) + +#define TRDC_MBC0_TRDC_HWCFG0_MID_MASK (0xE0000000U) +#define TRDC_MBC0_TRDC_HWCFG0_MID_SHIFT (29U) +/*! MID - Module ID */ +#define TRDC_MBC0_TRDC_HWCFG0_MID(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC0_TRDC_HWCFG0_MID_SHIFT)) & TRDC_MBC0_TRDC_HWCFG0_MID_MASK) +/*! @} */ + +/*! @name TRDC_HWCFG1 - TRDC Hardware Configuration Register 1 */ +/*! @{ */ + +#define TRDC_MBC0_TRDC_HWCFG1_DID_MASK (0xFU) +#define TRDC_MBC0_TRDC_HWCFG1_DID_SHIFT (0U) +/*! DID - Domain identifier number */ +#define TRDC_MBC0_TRDC_HWCFG1_DID(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC0_TRDC_HWCFG1_DID_SHIFT)) & TRDC_MBC0_TRDC_HWCFG1_DID_MASK) +/*! @} */ + +/*! @name DACFG - Domain Assignment Configuration Register */ +/*! @{ */ + +#define TRDC_MBC0_DACFG_NMDAR_MASK (0xFU) +#define TRDC_MBC0_DACFG_NMDAR_SHIFT (0U) +/*! NMDAR - Number of master domain assignment registers for bus master m */ +#define TRDC_MBC0_DACFG_NMDAR(x) (((uint8_t)(((uint8_t)(x)) << TRDC_MBC0_DACFG_NMDAR_SHIFT)) & TRDC_MBC0_DACFG_NMDAR_MASK) + +#define TRDC_MBC0_DACFG_NCM_MASK (0x80U) +#define TRDC_MBC0_DACFG_NCM_SHIFT (7U) +/*! NCM - Non-CPU Master + * 0b0..Bus master is a processor. + * 0b1..Bus master is a non-processor. + */ +#define TRDC_MBC0_DACFG_NCM(x) (((uint8_t)(((uint8_t)(x)) << TRDC_MBC0_DACFG_NCM_SHIFT)) & TRDC_MBC0_DACFG_NCM_MASK) +/*! @} */ + +/* The count of TRDC_MBC0_DACFG */ +#define TRDC_MBC0_DACFG_COUNT (7U) + +/*! @name TRDC_IDAU_CR - TRDC IDAU Control Register */ +/*! @{ */ + +#define TRDC_MBC0_TRDC_IDAU_CR_VLD_MASK (0x1U) +#define TRDC_MBC0_TRDC_IDAU_CR_VLD_SHIFT (0U) +/*! VLD - Valid */ +#define TRDC_MBC0_TRDC_IDAU_CR_VLD(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC0_TRDC_IDAU_CR_VLD_SHIFT)) & TRDC_MBC0_TRDC_IDAU_CR_VLD_MASK) + +#define TRDC_MBC0_TRDC_IDAU_CR_CFGSECEXT_MASK (0x8U) +#define TRDC_MBC0_TRDC_IDAU_CR_CFGSECEXT_SHIFT (3U) +/*! CFGSECEXT - Configure Security Extension + * 0b0..Armv8M Security Extension is disabled + * 0b1..Armv8-M Security Extension is enabled + */ +#define TRDC_MBC0_TRDC_IDAU_CR_CFGSECEXT(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC0_TRDC_IDAU_CR_CFGSECEXT_SHIFT)) & TRDC_MBC0_TRDC_IDAU_CR_CFGSECEXT_MASK) + +#define TRDC_MBC0_TRDC_IDAU_CR_MPUSDIS_MASK (0x10U) +#define TRDC_MBC0_TRDC_IDAU_CR_MPUSDIS_SHIFT (4U) +/*! MPUSDIS - Secure Memory Protection Unit Disabled + * 0b0..Secure MPU is enabled + * 0b1..Secure MPU is disabled + */ +#define TRDC_MBC0_TRDC_IDAU_CR_MPUSDIS(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC0_TRDC_IDAU_CR_MPUSDIS_SHIFT)) & TRDC_MBC0_TRDC_IDAU_CR_MPUSDIS_MASK) + +#define TRDC_MBC0_TRDC_IDAU_CR_MPUNSDIS_MASK (0x20U) +#define TRDC_MBC0_TRDC_IDAU_CR_MPUNSDIS_SHIFT (5U) +/*! MPUNSDIS - NonSecure Memory Protection Unit Disabled + * 0b0..Nonsecure MPU is enabled + * 0b1..Nonsecure MPU is disabled + */ +#define TRDC_MBC0_TRDC_IDAU_CR_MPUNSDIS(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC0_TRDC_IDAU_CR_MPUNSDIS_SHIFT)) & TRDC_MBC0_TRDC_IDAU_CR_MPUNSDIS_MASK) + +#define TRDC_MBC0_TRDC_IDAU_CR_SAUDIS_MASK (0x40U) +#define TRDC_MBC0_TRDC_IDAU_CR_SAUDIS_SHIFT (6U) +/*! SAUDIS - Security Attribution Unit Disable + * 0b0..SAU is enabled + * 0b1..SAU is disabled + */ +#define TRDC_MBC0_TRDC_IDAU_CR_SAUDIS(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC0_TRDC_IDAU_CR_SAUDIS_SHIFT)) & TRDC_MBC0_TRDC_IDAU_CR_SAUDIS_MASK) + +#define TRDC_MBC0_TRDC_IDAU_CR_LKSVTAIRCR_MASK (0x100U) +#define TRDC_MBC0_TRDC_IDAU_CR_LKSVTAIRCR_SHIFT (8U) +/*! LKSVTAIRCR - Lock Secure VTOR, Application interrupt and Reset Control Registers + * 0b0..Unlock these registers + * 0b1..Disable writes to the VTOR_S, AIRCR[PRIS], and AIRCR[BFHFNMINS] registers + */ +#define TRDC_MBC0_TRDC_IDAU_CR_LKSVTAIRCR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC0_TRDC_IDAU_CR_LKSVTAIRCR_SHIFT)) & TRDC_MBC0_TRDC_IDAU_CR_LKSVTAIRCR_MASK) + +#define TRDC_MBC0_TRDC_IDAU_CR_LKNSVTOR_MASK (0x200U) +#define TRDC_MBC0_TRDC_IDAU_CR_LKNSVTOR_SHIFT (9U) +/*! LKNSVTOR - Lock Nonsecure Vector Table Offset Register + * 0b0..Unlock this register + * 0b1..Disable writes to the VTOR_NS register + */ +#define TRDC_MBC0_TRDC_IDAU_CR_LKNSVTOR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC0_TRDC_IDAU_CR_LKNSVTOR_SHIFT)) & TRDC_MBC0_TRDC_IDAU_CR_LKNSVTOR_MASK) + +#define TRDC_MBC0_TRDC_IDAU_CR_LKSMPU_MASK (0x400U) +#define TRDC_MBC0_TRDC_IDAU_CR_LKSMPU_SHIFT (10U) +/*! LKSMPU - Lock Secure MPU + * 0b0..Unlock these registers + * 0b1..Disable writes to the MPU_CTRL, MPU_RNR, MPU_RBAR, MPU_RLAR, MPU_RBAR_An and MPU_RLAR_An from software or + * from a debug agent connected to the processor in Secure state + */ +#define TRDC_MBC0_TRDC_IDAU_CR_LKSMPU(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC0_TRDC_IDAU_CR_LKSMPU_SHIFT)) & TRDC_MBC0_TRDC_IDAU_CR_LKSMPU_MASK) + +#define TRDC_MBC0_TRDC_IDAU_CR_LKNSMPU_MASK (0x800U) +#define TRDC_MBC0_TRDC_IDAU_CR_LKNSMPU_SHIFT (11U) +/*! LKNSMPU - Lock Nonsecure MPU + * 0b0..Unlock these registers + * 0b1..Disable writes to the MPU_CTRL_NS, MPU_RNR_NS, MPU_RBAR_NS, MPU_RLAR_NS, MPU_RBAR_A_NSn and + * MPU_RLAR_A_NSn from software or from a debug agent connected to the processor + */ +#define TRDC_MBC0_TRDC_IDAU_CR_LKNSMPU(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC0_TRDC_IDAU_CR_LKNSMPU_SHIFT)) & TRDC_MBC0_TRDC_IDAU_CR_LKNSMPU_MASK) + +#define TRDC_MBC0_TRDC_IDAU_CR_LKSAU_MASK (0x1000U) +#define TRDC_MBC0_TRDC_IDAU_CR_LKSAU_SHIFT (12U) +/*! LKSAU - Lock SAU + * 0b0..Unlock these registers + * 0b1..Disable writes to the SAU_CTRL, SAU_RNR, SAU_RBAR and SAU_RLAR registers from software or from a debug agent connected to the processor + */ +#define TRDC_MBC0_TRDC_IDAU_CR_LKSAU(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC0_TRDC_IDAU_CR_LKSAU_SHIFT)) & TRDC_MBC0_TRDC_IDAU_CR_LKSAU_MASK) + +#define TRDC_MBC0_TRDC_IDAU_CR_PCURRNS_MASK (0x80000000U) +#define TRDC_MBC0_TRDC_IDAU_CR_PCURRNS_SHIFT (31U) +/*! PCURRNS - Processor current security + * 0b0..Processor is in Secure state + * 0b1..Processor is in Nonsecure state + */ +#define TRDC_MBC0_TRDC_IDAU_CR_PCURRNS(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC0_TRDC_IDAU_CR_PCURRNS_SHIFT)) & TRDC_MBC0_TRDC_IDAU_CR_PCURRNS_MASK) +/*! @} */ + +/*! @name TRDC_FLW_CTL - TRDC FLW Control */ +/*! @{ */ + +#define TRDC_MBC0_TRDC_FLW_CTL_LK_MASK (0x40000000U) +#define TRDC_MBC0_TRDC_FLW_CTL_LK_SHIFT (30U) +/*! LK - Lock bit + * 0b0..FLW registers may be modified. + * 0b1..FLW registers are locked until the next reset. + */ +#define TRDC_MBC0_TRDC_FLW_CTL_LK(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC0_TRDC_FLW_CTL_LK_SHIFT)) & TRDC_MBC0_TRDC_FLW_CTL_LK_MASK) + +#define TRDC_MBC0_TRDC_FLW_CTL_V_MASK (0x80000000U) +#define TRDC_MBC0_TRDC_FLW_CTL_V_SHIFT (31U) +/*! V - Valid bit + * 0b0..FLW function is disabled. + * 0b1..FLW function is enabled. + */ +#define TRDC_MBC0_TRDC_FLW_CTL_V(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC0_TRDC_FLW_CTL_V_SHIFT)) & TRDC_MBC0_TRDC_FLW_CTL_V_MASK) +/*! @} */ + +/*! @name TRDC_FLW_PBASE - TRDC FLW Physical Base */ +/*! @{ */ + +#define TRDC_MBC0_TRDC_FLW_PBASE_PBASE_MASK (0xFFFFFFFFU) +#define TRDC_MBC0_TRDC_FLW_PBASE_PBASE_SHIFT (0U) +/*! PBASE - Physical base address */ +#define TRDC_MBC0_TRDC_FLW_PBASE_PBASE(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC0_TRDC_FLW_PBASE_PBASE_SHIFT)) & TRDC_MBC0_TRDC_FLW_PBASE_PBASE_MASK) +/*! @} */ + +/*! @name TRDC_FLW_ABASE - TRDC FLW Array Base */ +/*! @{ */ + +#define TRDC_MBC0_TRDC_FLW_ABASE_ABASE_L_MASK (0x3F8000U) +#define TRDC_MBC0_TRDC_FLW_ABASE_ABASE_L_SHIFT (15U) +/*! ABASE_L - Array base address low */ +#define TRDC_MBC0_TRDC_FLW_ABASE_ABASE_L(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC0_TRDC_FLW_ABASE_ABASE_L_SHIFT)) & TRDC_MBC0_TRDC_FLW_ABASE_ABASE_L_MASK) + +#define TRDC_MBC0_TRDC_FLW_ABASE_ABASE_H_MASK (0xFFC00000U) +#define TRDC_MBC0_TRDC_FLW_ABASE_ABASE_H_SHIFT (22U) +/*! ABASE_H - Array base address high */ +#define TRDC_MBC0_TRDC_FLW_ABASE_ABASE_H(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC0_TRDC_FLW_ABASE_ABASE_H_SHIFT)) & TRDC_MBC0_TRDC_FLW_ABASE_ABASE_H_MASK) +/*! @} */ + +/*! @name TRDC_FLW_BCNT - TRDC FLW Block Count */ +/*! @{ */ + +#define TRDC_MBC0_TRDC_FLW_BCNT_BCNT_MASK (0x7FFFU) +#define TRDC_MBC0_TRDC_FLW_BCNT_BCNT_SHIFT (0U) +/*! BCNT - Block Count */ +#define TRDC_MBC0_TRDC_FLW_BCNT_BCNT(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC0_TRDC_FLW_BCNT_BCNT_SHIFT)) & TRDC_MBC0_TRDC_FLW_BCNT_BCNT_MASK) +/*! @} */ + +/*! @name TRDC_FDID - TRDC Fault Domain ID */ +/*! @{ */ + +#define TRDC_MBC0_TRDC_FDID_FDID_MASK (0xFU) +#define TRDC_MBC0_TRDC_FDID_FDID_SHIFT (0U) +/*! FDID - Domain ID of Faulted Access */ +#define TRDC_MBC0_TRDC_FDID_FDID(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC0_TRDC_FDID_FDID_SHIFT)) & TRDC_MBC0_TRDC_FDID_FDID_MASK) +/*! @} */ + +/*! @name TRDC_DERRLOC - TRDC Domain Error Location Register */ +/*! @{ */ + +#define TRDC_MBC0_TRDC_DERRLOC_MBCINST_MASK (0xFFU) +#define TRDC_MBC0_TRDC_DERRLOC_MBCINST_SHIFT (0U) +/*! MBCINST - MBC instance */ +#define TRDC_MBC0_TRDC_DERRLOC_MBCINST(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC0_TRDC_DERRLOC_MBCINST_SHIFT)) & TRDC_MBC0_TRDC_DERRLOC_MBCINST_MASK) + +#define TRDC_MBC0_TRDC_DERRLOC_MRCINST_MASK (0xFFFF0000U) +#define TRDC_MBC0_TRDC_DERRLOC_MRCINST_SHIFT (16U) +/*! MRCINST - MRC instance */ +#define TRDC_MBC0_TRDC_DERRLOC_MRCINST(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC0_TRDC_DERRLOC_MRCINST_SHIFT)) & TRDC_MBC0_TRDC_DERRLOC_MRCINST_MASK) +/*! @} */ + +/* The count of TRDC_MBC0_TRDC_DERRLOC */ +#define TRDC_MBC0_TRDC_DERRLOC_COUNT (16U) + +/*! @name MDA_W_DFMT1 - DAC Master Domain Assignment Register */ +/*! @{ */ + +#define TRDC_MBC0_MDA_W_DFMT1_DID_MASK (0xFU) +#define TRDC_MBC0_MDA_W_DFMT1_DID_SHIFT (0U) +/*! DID - Domain identifier */ +#define TRDC_MBC0_MDA_W_DFMT1_DID(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC0_MDA_W_DFMT1_DID_SHIFT)) & TRDC_MBC0_MDA_W_DFMT1_DID_MASK) + +#define TRDC_MBC0_MDA_W_DFMT1_PA_MASK (0x30U) +#define TRDC_MBC0_MDA_W_DFMT1_PA_SHIFT (4U) +/*! PA - Privileged attribute + * 0b00..Force the bus attribute for this master to user. + * 0b01..Force the bus attribute for this master to privileged. + * 0b10..Use the bus master's privileged/user attribute directly. + * 0b11..Use the bus master's privileged/user attribute directly. + */ +#define TRDC_MBC0_MDA_W_DFMT1_PA(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC0_MDA_W_DFMT1_PA_SHIFT)) & TRDC_MBC0_MDA_W_DFMT1_PA_MASK) + +#define TRDC_MBC0_MDA_W_DFMT1_SA_MASK (0xC0U) +#define TRDC_MBC0_MDA_W_DFMT1_SA_SHIFT (6U) +/*! SA - Secure attribute + * 0b00..Force the bus attribute for this master to secure. + * 0b01..Force the bus attribute for this master to nonsecure. + * 0b10..Use the bus master's secure/nonsecure attribute directly. + * 0b11..Use the bus master's secure/nonsecure attribute directly. + */ +#define TRDC_MBC0_MDA_W_DFMT1_SA(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC0_MDA_W_DFMT1_SA_SHIFT)) & TRDC_MBC0_MDA_W_DFMT1_SA_MASK) + +#define TRDC_MBC0_MDA_W_DFMT1_DIDB_MASK (0x100U) +#define TRDC_MBC0_MDA_W_DFMT1_DIDB_SHIFT (8U) +/*! DIDB - DID Bypass + * 0b0..Use MDAn[3:0] as the domain identifier. + * 0b1..Use the DID input as the domain identifier. + */ +#define TRDC_MBC0_MDA_W_DFMT1_DIDB(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC0_MDA_W_DFMT1_DIDB_SHIFT)) & TRDC_MBC0_MDA_W_DFMT1_DIDB_MASK) + +#define TRDC_MBC0_MDA_W_DFMT1_DFMT_MASK (0x20000000U) +#define TRDC_MBC0_MDA_W_DFMT1_DFMT_SHIFT (29U) +/*! DFMT - Domain format + * 0b0..Processor-core domain assignment + * 0b1..Non-processor domain assignment + */ +#define TRDC_MBC0_MDA_W_DFMT1_DFMT(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC0_MDA_W_DFMT1_DFMT_SHIFT)) & TRDC_MBC0_MDA_W_DFMT1_DFMT_MASK) + +#define TRDC_MBC0_MDA_W_DFMT1_LK1_MASK (0x40000000U) +#define TRDC_MBC0_MDA_W_DFMT1_LK1_SHIFT (30U) +/*! LK1 - 1-bit Lock + * 0b0..Register can be written by any secure privileged write. + * 0b1..Register is locked (read-only) until the next reset. + */ +#define TRDC_MBC0_MDA_W_DFMT1_LK1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC0_MDA_W_DFMT1_LK1_SHIFT)) & TRDC_MBC0_MDA_W_DFMT1_LK1_MASK) + +#define TRDC_MBC0_MDA_W_DFMT1_VLD_MASK (0x80000000U) +#define TRDC_MBC0_MDA_W_DFMT1_VLD_SHIFT (31U) +/*! VLD - Valid + * 0b0..The Wr domain assignment is invalid. + * 0b1..The Wr domain assignment is valid. + */ +#define TRDC_MBC0_MDA_W_DFMT1_VLD(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC0_MDA_W_DFMT1_VLD_SHIFT)) & TRDC_MBC0_MDA_W_DFMT1_VLD_MASK) +/*! @} */ + +/* The count of TRDC_MBC0_MDA_W_DFMT1 */ +#define TRDC_MBC0_MDA_W_DFMT1_COUNT (7U) + +/* The count of TRDC_MBC0_MDA_W_DFMT1 */ +#define TRDC_MBC0_MDA_W_DFMT1_COUNT2 (1U) + + +/*! + * @} + */ /* end of group TRDC_MBC0_Register_Masks */ + + +/* TRDC_MBC0 - Peripheral instance base addresses */ +/** Peripheral TRDC3 base address */ +#define TRDC3_BASE (0x42810000u) +/** Peripheral TRDC3 base pointer */ +#define TRDC3 ((TRDC_MBC0_Type *)TRDC3_BASE) +/** Peripheral TRDC5 base address */ +#define TRDC5_BASE (0x4AC30000u) +/** Peripheral TRDC5 base pointer */ +#define TRDC5 ((TRDC_MBC0_Type *)TRDC5_BASE) +/** Peripheral TRDC6 base address */ +#define TRDC6_BASE (0x4C030000u) +/** Peripheral TRDC6 base pointer */ +#define TRDC6 ((TRDC_MBC0_Type *)TRDC6_BASE) +/** Array initializer of TRDC_MBC0 peripheral base addresses */ +#define TRDC_MBC0_BASE_ADDRS { 0u, 0u, 0u, TRDC3_BASE, 0u, TRDC5_BASE, TRDC6_BASE } +/** Array initializer of TRDC_MBC0 peripheral base pointers */ +#define TRDC_MBC0_BASE_PTRS { (TRDC_MBC0_Type *)0u, (TRDC_MBC0_Type *)0u, (TRDC_MBC0_Type *)0u, TRDC3, (TRDC_MBC0_Type *)0u, TRDC5, TRDC6 } + +/*! + * @} + */ /* end of group TRDC_MBC0_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- TRDC_MBC2 Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup TRDC_MBC2_Peripheral_Access_Layer TRDC_MBC2 Peripheral Access Layer + * @{ + */ + +/** TRDC_MBC2 - Register Layout Typedef */ +typedef struct { + __IO uint32_t TRDC_CR; /**< TRDC Register, offset: 0x0 */ + uint8_t RESERVED_0[236]; + __I uint32_t TRDC_HWCFG0; /**< TRDC Hardware Configuration Register 0, offset: 0xF0 */ + __I uint32_t TRDC_HWCFG1; /**< TRDC Hardware Configuration Register 1, offset: 0xF4 */ + uint8_t RESERVED_1[8]; + __I uint8_t DACFG[5]; /**< Domain Assignment Configuration Register, array offset: 0x100, array step: 0x1, valid indices: [2-4] */ + uint8_t RESERVED_2[187]; + __IO uint32_t TRDC_IDAU_CR; /**< TRDC IDAU Control Register, offset: 0x1C0 */ + uint8_t RESERVED_3[28]; + __IO uint32_t TRDC_FLW_CTL; /**< TRDC FLW Control, offset: 0x1E0 */ + __I uint32_t TRDC_FLW_PBASE; /**< TRDC FLW Physical Base, offset: 0x1E4 */ + __IO uint32_t TRDC_FLW_ABASE; /**< TRDC FLW Array Base, offset: 0x1E8 */ + __IO uint32_t TRDC_FLW_BCNT; /**< TRDC FLW Block Count, offset: 0x1EC */ + uint8_t RESERVED_4[12]; + __IO uint32_t TRDC_FDID; /**< TRDC Fault Domain ID, offset: 0x1FC */ + __I uint32_t TRDC_DERRLOC[16]; /**< TRDC Domain Error Location Register, array offset: 0x200, array step: 0x4 */ + uint8_t RESERVED_5[448]; + struct { /* offset: 0x400, array step: 0x10 */ + __I uint32_t W0; /**< MBC Domain Error Word0 Register, array offset: 0x400, array step: 0x10, irregular array, not all indices are valid */ + __I uint32_t W1; /**< MBC Domain Error Word1 Register, array offset: 0x404, array step: 0x10, irregular array, not all indices are valid */ + uint8_t RESERVED_0[4]; + __IO uint32_t W3; /**< MBC Domain Error Word3 Register, array offset: 0x40C, array step: 0x10, irregular array, not all indices are valid */ + } MBC_DERR[2]; + uint8_t RESERVED_6[96]; + struct { /* offset: 0x480, array step: 0x10 */ + __I uint32_t W0; /**< MRC Domain Error Word0 Register, array offset: 0x480, array step: 0x10, available only on: TRDC_WAKEUPMIX/TRDC2 (missing on TRDC_AONMIX/TRDC1) */ + __I uint32_t W1; /**< MRC Domain Error Word1 Register, array offset: 0x484, array step: 0x10, available only on: TRDC_WAKEUPMIX/TRDC2 (missing on TRDC_AONMIX/TRDC1) */ + uint8_t RESERVED_0[4]; + __IO uint32_t W3; /**< MRC Domain Error Word3 Register, array offset: 0x48C, array step: 0x10, available only on: TRDC_WAKEUPMIX/TRDC2 (missing on TRDC_AONMIX/TRDC1) */ + } MRC_DERR[2]; + uint8_t RESERVED_7[864]; + struct { /* offset: 0x800, array step: 0x20 */ + struct { /* offset: 0x800, array step: index*0x20, index2*0x4 */ + __IO uint32_t MDA_W_DFMT1; /**< DAC Master Domain Assignment Register, array offset: 0x800, array step: index*0x20, index2*0x4, valid indices: [2-4][0] */ + } MDA_Wx_DFMT1[1]; + uint8_t RESERVED_0[28]; + } MDA_Wx_y_DFMT[5]; + uint8_t RESERVED_8[63328]; + struct { /* offset: 0x10000, array step: 0x2000 */ + __I uint32_t MBC_MEM_GLBCFG[4]; /**< MBC Global Configuration Register, array offset: 0x10000, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */ + __IO uint32_t MBC_NSE_BLK_INDEX; /**< MBC NonSecure Enable Block Index, array offset: 0x10010, array step: 0x2000, irregular array, not all indices are valid */ + __IO uint32_t MBC_NSE_BLK_SET; /**< MBC NonSecure Enable Block Set, array offset: 0x10014, array step: 0x2000, irregular array, not all indices are valid */ + __IO uint32_t MBC_NSE_BLK_CLR; /**< MBC NonSecure Enable Block Clear, array offset: 0x10018, array step: 0x2000, irregular array, not all indices are valid */ + __IO uint32_t MBC_NSE_BLK_CLR_ALL; /**< MBC NonSecure Enable Block Clear All, array offset: 0x1001C, array step: 0x2000, irregular array, not all indices are valid */ + __IO uint32_t MBC_MEMN_GLBAC[8]; /**< MBC Global Access Control, array offset: 0x10020, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */ + __IO uint32_t MBC_DOM0_MEM0_BLK_CFG_W[16]; /**< MBC Memory Block Configuration Word, array offset: 0x10040, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */ + uint8_t RESERVED_0[192]; + __IO uint32_t MBC_DOM0_MEM0_BLK_NSE_W[4]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x10140, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */ + uint8_t RESERVED_1[48]; + __IO uint32_t MBC_DOM0_MEM1_BLK_CFG_W[1]; /**< MBC Memory Block Configuration Word, array offset: 0x10180, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */ + uint8_t RESERVED_2[28]; + __IO uint32_t MBC_DOM0_MEM1_BLK_NSE_W[1]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x101A0, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */ + uint8_t RESERVED_3[4]; + __IO uint32_t MBC_DOM0_MEM2_BLK_CFG_W[1]; /**< MBC Memory Block Configuration Word, array offset: 0x101A8, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */ + uint8_t RESERVED_4[28]; + __IO uint32_t MBC_DOM0_MEM2_BLK_NSE_W[1]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x101C8, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */ + uint8_t RESERVED_5[4]; + __IO uint32_t MBC_DOM0_MEM3_BLK_CFG_W[3]; /**< MBC Memory Block Configuration Word, array offset: 0x101D0, array step: index*0x2000, index2*0x4, available only on: TRDC_WAKEUPMIX/TRDC2 (missing on TRDC_AONMIX/TRDC1), valid indices: [0][0-2], [1][0] */ + uint8_t RESERVED_6[20]; + __IO uint32_t MBC_DOM0_MEM3_BLK_NSE_W[1]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x101F0, array step: index*0x2000, index2*0x4, available only on: TRDC_WAKEUPMIX/TRDC2 (missing on TRDC_AONMIX/TRDC1) */ + uint8_t RESERVED_7[76]; + __IO uint32_t MBC_DOM1_MEM0_BLK_CFG_W[16]; /**< MBC Memory Block Configuration Word, array offset: 0x10240, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */ + uint8_t RESERVED_8[192]; + __IO uint32_t MBC_DOM1_MEM0_BLK_NSE_W[4]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x10340, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */ + uint8_t RESERVED_9[48]; + __IO uint32_t MBC_DOM1_MEM1_BLK_CFG_W[1]; /**< MBC Memory Block Configuration Word, array offset: 0x10380, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */ + uint8_t RESERVED_10[28]; + __IO uint32_t MBC_DOM1_MEM1_BLK_NSE_W[1]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x103A0, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */ + uint8_t RESERVED_11[4]; + __IO uint32_t MBC_DOM1_MEM2_BLK_CFG_W[1]; /**< MBC Memory Block Configuration Word, array offset: 0x103A8, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */ + uint8_t RESERVED_12[28]; + __IO uint32_t MBC_DOM1_MEM2_BLK_NSE_W[1]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x103C8, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */ + uint8_t RESERVED_13[4]; + __IO uint32_t MBC_DOM1_MEM3_BLK_CFG_W[3]; /**< MBC Memory Block Configuration Word, array offset: 0x103D0, array step: index*0x2000, index2*0x4, available only on: TRDC_WAKEUPMIX/TRDC2 (missing on TRDC_AONMIX/TRDC1), valid indices: [0][0-2], [1][0] */ + uint8_t RESERVED_14[20]; + __IO uint32_t MBC_DOM1_MEM3_BLK_NSE_W[1]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x103F0, array step: index*0x2000, index2*0x4, available only on: TRDC_WAKEUPMIX/TRDC2 (missing on TRDC_AONMIX/TRDC1) */ + uint8_t RESERVED_15[76]; + __IO uint32_t MBC_DOM2_MEM0_BLK_CFG_W[16]; /**< MBC Memory Block Configuration Word, array offset: 0x10440, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */ + uint8_t RESERVED_16[192]; + __IO uint32_t MBC_DOM2_MEM0_BLK_NSE_W[4]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x10540, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */ + uint8_t RESERVED_17[48]; + __IO uint32_t MBC_DOM2_MEM1_BLK_CFG_W[1]; /**< MBC Memory Block Configuration Word, array offset: 0x10580, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */ + uint8_t RESERVED_18[28]; + __IO uint32_t MBC_DOM2_MEM1_BLK_NSE_W[1]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x105A0, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */ + uint8_t RESERVED_19[4]; + __IO uint32_t MBC_DOM2_MEM2_BLK_CFG_W[1]; /**< MBC Memory Block Configuration Word, array offset: 0x105A8, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */ + uint8_t RESERVED_20[28]; + __IO uint32_t MBC_DOM2_MEM2_BLK_NSE_W[1]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x105C8, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */ + uint8_t RESERVED_21[4]; + __IO uint32_t MBC_DOM2_MEM3_BLK_CFG_W[3]; /**< MBC Memory Block Configuration Word, array offset: 0x105D0, array step: index*0x2000, index2*0x4, available only on: TRDC_WAKEUPMIX/TRDC2 (missing on TRDC_AONMIX/TRDC1), valid indices: [0][0-2], [1][0] */ + uint8_t RESERVED_22[20]; + __IO uint32_t MBC_DOM2_MEM3_BLK_NSE_W[1]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x105F0, array step: index*0x2000, index2*0x4, available only on: TRDC_WAKEUPMIX/TRDC2 (missing on TRDC_AONMIX/TRDC1) */ + uint8_t RESERVED_23[76]; + __IO uint32_t MBC_DOM3_MEM0_BLK_CFG_W[16]; /**< MBC Memory Block Configuration Word, array offset: 0x10640, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */ + uint8_t RESERVED_24[192]; + __IO uint32_t MBC_DOM3_MEM0_BLK_NSE_W[4]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x10740, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */ + uint8_t RESERVED_25[48]; + __IO uint32_t MBC_DOM3_MEM1_BLK_CFG_W[1]; /**< MBC Memory Block Configuration Word, array offset: 0x10780, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */ + uint8_t RESERVED_26[28]; + __IO uint32_t MBC_DOM3_MEM1_BLK_NSE_W[1]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x107A0, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */ + uint8_t RESERVED_27[4]; + __IO uint32_t MBC_DOM3_MEM2_BLK_CFG_W[1]; /**< MBC Memory Block Configuration Word, array offset: 0x107A8, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */ + uint8_t RESERVED_28[28]; + __IO uint32_t MBC_DOM3_MEM2_BLK_NSE_W[1]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x107C8, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */ + uint8_t RESERVED_29[4]; + __IO uint32_t MBC_DOM3_MEM3_BLK_CFG_W[3]; /**< MBC Memory Block Configuration Word, array offset: 0x107D0, array step: index*0x2000, index2*0x4, available only on: TRDC_WAKEUPMIX/TRDC2 (missing on TRDC_AONMIX/TRDC1), valid indices: [0][0-2], [1][0] */ + uint8_t RESERVED_30[20]; + __IO uint32_t MBC_DOM3_MEM3_BLK_NSE_W[1]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x107F0, array step: index*0x2000, index2*0x4, available only on: TRDC_WAKEUPMIX/TRDC2 (missing on TRDC_AONMIX/TRDC1) */ + uint8_t RESERVED_31[76]; + __IO uint32_t MBC_DOM4_MEM0_BLK_CFG_W[16]; /**< MBC Memory Block Configuration Word, array offset: 0x10840, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */ + uint8_t RESERVED_32[192]; + __IO uint32_t MBC_DOM4_MEM0_BLK_NSE_W[4]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x10940, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */ + uint8_t RESERVED_33[48]; + __IO uint32_t MBC_DOM4_MEM1_BLK_CFG_W[1]; /**< MBC Memory Block Configuration Word, array offset: 0x10980, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */ + uint8_t RESERVED_34[28]; + __IO uint32_t MBC_DOM4_MEM1_BLK_NSE_W[1]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x109A0, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */ + uint8_t RESERVED_35[4]; + __IO uint32_t MBC_DOM4_MEM2_BLK_CFG_W[1]; /**< MBC Memory Block Configuration Word, array offset: 0x109A8, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */ + uint8_t RESERVED_36[28]; + __IO uint32_t MBC_DOM4_MEM2_BLK_NSE_W[1]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x109C8, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */ + uint8_t RESERVED_37[4]; + __IO uint32_t MBC_DOM4_MEM3_BLK_CFG_W[3]; /**< MBC Memory Block Configuration Word, array offset: 0x109D0, array step: index*0x2000, index2*0x4, available only on: TRDC_WAKEUPMIX/TRDC2 (missing on TRDC_AONMIX/TRDC1), valid indices: [0][0-2], [1][0] */ + uint8_t RESERVED_38[20]; + __IO uint32_t MBC_DOM4_MEM3_BLK_NSE_W[1]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x109F0, array step: index*0x2000, index2*0x4, available only on: TRDC_WAKEUPMIX/TRDC2 (missing on TRDC_AONMIX/TRDC1) */ + uint8_t RESERVED_39[76]; + __IO uint32_t MBC_DOM5_MEM0_BLK_CFG_W[16]; /**< MBC Memory Block Configuration Word, array offset: 0x10A40, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */ + uint8_t RESERVED_40[192]; + __IO uint32_t MBC_DOM5_MEM0_BLK_NSE_W[4]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x10B40, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */ + uint8_t RESERVED_41[48]; + __IO uint32_t MBC_DOM5_MEM1_BLK_CFG_W[1]; /**< MBC Memory Block Configuration Word, array offset: 0x10B80, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */ + uint8_t RESERVED_42[28]; + __IO uint32_t MBC_DOM5_MEM1_BLK_NSE_W[1]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x10BA0, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */ + uint8_t RESERVED_43[4]; + __IO uint32_t MBC_DOM5_MEM2_BLK_CFG_W[1]; /**< MBC Memory Block Configuration Word, array offset: 0x10BA8, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */ + uint8_t RESERVED_44[28]; + __IO uint32_t MBC_DOM5_MEM2_BLK_NSE_W[1]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x10BC8, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */ + uint8_t RESERVED_45[4]; + __IO uint32_t MBC_DOM5_MEM3_BLK_CFG_W[3]; /**< MBC Memory Block Configuration Word, array offset: 0x10BD0, array step: index*0x2000, index2*0x4, available only on: TRDC_WAKEUPMIX/TRDC2 (missing on TRDC_AONMIX/TRDC1), valid indices: [0][0-2], [1][0] */ + uint8_t RESERVED_46[20]; + __IO uint32_t MBC_DOM5_MEM3_BLK_NSE_W[1]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x10BF0, array step: index*0x2000, index2*0x4, available only on: TRDC_WAKEUPMIX/TRDC2 (missing on TRDC_AONMIX/TRDC1) */ + uint8_t RESERVED_47[76]; + __IO uint32_t MBC_DOM6_MEM0_BLK_CFG_W[16]; /**< MBC Memory Block Configuration Word, array offset: 0x10C40, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */ + uint8_t RESERVED_48[192]; + __IO uint32_t MBC_DOM6_MEM0_BLK_NSE_W[4]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x10D40, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */ + uint8_t RESERVED_49[48]; + __IO uint32_t MBC_DOM6_MEM1_BLK_CFG_W[1]; /**< MBC Memory Block Configuration Word, array offset: 0x10D80, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */ + uint8_t RESERVED_50[28]; + __IO uint32_t MBC_DOM6_MEM1_BLK_NSE_W[1]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x10DA0, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */ + uint8_t RESERVED_51[4]; + __IO uint32_t MBC_DOM6_MEM2_BLK_CFG_W[1]; /**< MBC Memory Block Configuration Word, array offset: 0x10DA8, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */ + uint8_t RESERVED_52[28]; + __IO uint32_t MBC_DOM6_MEM2_BLK_NSE_W[1]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x10DC8, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */ + uint8_t RESERVED_53[4]; + __IO uint32_t MBC_DOM6_MEM3_BLK_CFG_W[3]; /**< MBC Memory Block Configuration Word, array offset: 0x10DD0, array step: index*0x2000, index2*0x4, available only on: TRDC_WAKEUPMIX/TRDC2 (missing on TRDC_AONMIX/TRDC1), valid indices: [0][0-2], [1][0] */ + uint8_t RESERVED_54[20]; + __IO uint32_t MBC_DOM6_MEM3_BLK_NSE_W[1]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x10DF0, array step: index*0x2000, index2*0x4, available only on: TRDC_WAKEUPMIX/TRDC2 (missing on TRDC_AONMIX/TRDC1) */ + uint8_t RESERVED_55[76]; + __IO uint32_t MBC_DOM7_MEM0_BLK_CFG_W[16]; /**< MBC Memory Block Configuration Word, array offset: 0x10E40, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */ + uint8_t RESERVED_56[192]; + __IO uint32_t MBC_DOM7_MEM0_BLK_NSE_W[4]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x10F40, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */ + uint8_t RESERVED_57[48]; + __IO uint32_t MBC_DOM7_MEM1_BLK_CFG_W[1]; /**< MBC Memory Block Configuration Word, array offset: 0x10F80, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */ + uint8_t RESERVED_58[28]; + __IO uint32_t MBC_DOM7_MEM1_BLK_NSE_W[1]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x10FA0, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */ + uint8_t RESERVED_59[4]; + __IO uint32_t MBC_DOM7_MEM2_BLK_CFG_W[1]; /**< MBC Memory Block Configuration Word, array offset: 0x10FA8, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */ + uint8_t RESERVED_60[28]; + __IO uint32_t MBC_DOM7_MEM2_BLK_NSE_W[1]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x10FC8, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */ + uint8_t RESERVED_61[4]; + __IO uint32_t MBC_DOM7_MEM3_BLK_CFG_W[3]; /**< MBC Memory Block Configuration Word, array offset: 0x10FD0, array step: index*0x2000, index2*0x4, available only on: TRDC_WAKEUPMIX/TRDC2 (missing on TRDC_AONMIX/TRDC1), valid indices: [0][0-2], [1][0] */ + uint8_t RESERVED_62[20]; + __IO uint32_t MBC_DOM7_MEM3_BLK_NSE_W[1]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x10FF0, array step: index*0x2000, index2*0x4, available only on: TRDC_WAKEUPMIX/TRDC2 (missing on TRDC_AONMIX/TRDC1) */ + uint8_t RESERVED_63[76]; + __IO uint32_t MBC_DOM8_MEM0_BLK_CFG_W[16]; /**< MBC Memory Block Configuration Word, array offset: 0x11040, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */ + uint8_t RESERVED_64[192]; + __IO uint32_t MBC_DOM8_MEM0_BLK_NSE_W[4]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x11140, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */ + uint8_t RESERVED_65[48]; + __IO uint32_t MBC_DOM8_MEM1_BLK_CFG_W[1]; /**< MBC Memory Block Configuration Word, array offset: 0x11180, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */ + uint8_t RESERVED_66[28]; + __IO uint32_t MBC_DOM8_MEM1_BLK_NSE_W[1]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x111A0, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */ + uint8_t RESERVED_67[4]; + __IO uint32_t MBC_DOM8_MEM2_BLK_CFG_W[1]; /**< MBC Memory Block Configuration Word, array offset: 0x111A8, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */ + uint8_t RESERVED_68[28]; + __IO uint32_t MBC_DOM8_MEM2_BLK_NSE_W[1]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x111C8, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */ + uint8_t RESERVED_69[4]; + __IO uint32_t MBC_DOM8_MEM3_BLK_CFG_W[3]; /**< MBC Memory Block Configuration Word, array offset: 0x111D0, array step: index*0x2000, index2*0x4, available only on: TRDC_WAKEUPMIX/TRDC2 (missing on TRDC_AONMIX/TRDC1), valid indices: [0][0-2], [1][0] */ + uint8_t RESERVED_70[20]; + __IO uint32_t MBC_DOM8_MEM3_BLK_NSE_W[1]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x111F0, array step: index*0x2000, index2*0x4, available only on: TRDC_WAKEUPMIX/TRDC2 (missing on TRDC_AONMIX/TRDC1) */ + uint8_t RESERVED_71[76]; + __IO uint32_t MBC_DOM9_MEM0_BLK_CFG_W[16]; /**< MBC Memory Block Configuration Word, array offset: 0x11240, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */ + uint8_t RESERVED_72[192]; + __IO uint32_t MBC_DOM9_MEM0_BLK_NSE_W[4]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x11340, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */ + uint8_t RESERVED_73[48]; + __IO uint32_t MBC_DOM9_MEM1_BLK_CFG_W[1]; /**< MBC Memory Block Configuration Word, array offset: 0x11380, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */ + uint8_t RESERVED_74[28]; + __IO uint32_t MBC_DOM9_MEM1_BLK_NSE_W[1]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x113A0, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */ + uint8_t RESERVED_75[4]; + __IO uint32_t MBC_DOM9_MEM2_BLK_CFG_W[1]; /**< MBC Memory Block Configuration Word, array offset: 0x113A8, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */ + uint8_t RESERVED_76[28]; + __IO uint32_t MBC_DOM9_MEM2_BLK_NSE_W[1]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x113C8, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */ + uint8_t RESERVED_77[4]; + __IO uint32_t MBC_DOM9_MEM3_BLK_CFG_W[3]; /**< MBC Memory Block Configuration Word, array offset: 0x113D0, array step: index*0x2000, index2*0x4, available only on: TRDC_WAKEUPMIX/TRDC2 (missing on TRDC_AONMIX/TRDC1), valid indices: [0][0-2], [1][0] */ + uint8_t RESERVED_78[20]; + __IO uint32_t MBC_DOM9_MEM3_BLK_NSE_W[1]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x113F0, array step: index*0x2000, index2*0x4, available only on: TRDC_WAKEUPMIX/TRDC2 (missing on TRDC_AONMIX/TRDC1) */ + uint8_t RESERVED_79[76]; + __IO uint32_t MBC_DOM10_MEM0_BLK_CFG_W[16]; /**< MBC Memory Block Configuration Word, array offset: 0x11440, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */ + uint8_t RESERVED_80[192]; + __IO uint32_t MBC_DOM10_MEM0_BLK_NSE_W[4]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x11540, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */ + uint8_t RESERVED_81[48]; + __IO uint32_t MBC_DOM10_MEM1_BLK_CFG_W[1]; /**< MBC Memory Block Configuration Word, array offset: 0x11580, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */ + uint8_t RESERVED_82[28]; + __IO uint32_t MBC_DOM10_MEM1_BLK_NSE_W[1]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x115A0, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */ + uint8_t RESERVED_83[4]; + __IO uint32_t MBC_DOM10_MEM2_BLK_CFG_W[1]; /**< MBC Memory Block Configuration Word, array offset: 0x115A8, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */ + uint8_t RESERVED_84[28]; + __IO uint32_t MBC_DOM10_MEM2_BLK_NSE_W[1]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x115C8, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */ + uint8_t RESERVED_85[4]; + __IO uint32_t MBC_DOM10_MEM3_BLK_CFG_W[3]; /**< MBC Memory Block Configuration Word, array offset: 0x115D0, array step: index*0x2000, index2*0x4, available only on: TRDC_WAKEUPMIX/TRDC2 (missing on TRDC_AONMIX/TRDC1), valid indices: [0][0-2], [1][0] */ + uint8_t RESERVED_86[20]; + __IO uint32_t MBC_DOM10_MEM3_BLK_NSE_W[1]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x115F0, array step: index*0x2000, index2*0x4, available only on: TRDC_WAKEUPMIX/TRDC2 (missing on TRDC_AONMIX/TRDC1) */ + uint8_t RESERVED_87[76]; + __IO uint32_t MBC_DOM11_MEM0_BLK_CFG_W[16]; /**< MBC Memory Block Configuration Word, array offset: 0x11640, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */ + uint8_t RESERVED_88[192]; + __IO uint32_t MBC_DOM11_MEM0_BLK_NSE_W[4]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x11740, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */ + uint8_t RESERVED_89[48]; + __IO uint32_t MBC_DOM11_MEM1_BLK_CFG_W[1]; /**< MBC Memory Block Configuration Word, array offset: 0x11780, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */ + uint8_t RESERVED_90[28]; + __IO uint32_t MBC_DOM11_MEM1_BLK_NSE_W[1]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x117A0, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */ + uint8_t RESERVED_91[4]; + __IO uint32_t MBC_DOM11_MEM2_BLK_CFG_W[1]; /**< MBC Memory Block Configuration Word, array offset: 0x117A8, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */ + uint8_t RESERVED_92[28]; + __IO uint32_t MBC_DOM11_MEM2_BLK_NSE_W[1]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x117C8, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */ + uint8_t RESERVED_93[4]; + __IO uint32_t MBC_DOM11_MEM3_BLK_CFG_W[3]; /**< MBC Memory Block Configuration Word, array offset: 0x117D0, array step: index*0x2000, index2*0x4, available only on: TRDC_WAKEUPMIX/TRDC2 (missing on TRDC_AONMIX/TRDC1), valid indices: [0][0-2], [1][0] */ + uint8_t RESERVED_94[20]; + __IO uint32_t MBC_DOM11_MEM3_BLK_NSE_W[1]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x117F0, array step: index*0x2000, index2*0x4, available only on: TRDC_WAKEUPMIX/TRDC2 (missing on TRDC_AONMIX/TRDC1) */ + uint8_t RESERVED_95[76]; + __IO uint32_t MBC_DOM12_MEM0_BLK_CFG_W[16]; /**< MBC Memory Block Configuration Word, array offset: 0x11840, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */ + uint8_t RESERVED_96[192]; + __IO uint32_t MBC_DOM12_MEM0_BLK_NSE_W[4]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x11940, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */ + uint8_t RESERVED_97[48]; + __IO uint32_t MBC_DOM12_MEM1_BLK_CFG_W[1]; /**< MBC Memory Block Configuration Word, array offset: 0x11980, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */ + uint8_t RESERVED_98[28]; + __IO uint32_t MBC_DOM12_MEM1_BLK_NSE_W[1]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x119A0, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */ + uint8_t RESERVED_99[4]; + __IO uint32_t MBC_DOM12_MEM2_BLK_CFG_W[1]; /**< MBC Memory Block Configuration Word, array offset: 0x119A8, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */ + uint8_t RESERVED_100[28]; + __IO uint32_t MBC_DOM12_MEM2_BLK_NSE_W[1]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x119C8, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */ + uint8_t RESERVED_101[4]; + __IO uint32_t MBC_DOM12_MEM3_BLK_CFG_W[3]; /**< MBC Memory Block Configuration Word, array offset: 0x119D0, array step: index*0x2000, index2*0x4, available only on: TRDC_WAKEUPMIX/TRDC2 (missing on TRDC_AONMIX/TRDC1), valid indices: [0][0-2], [1][0] */ + uint8_t RESERVED_102[20]; + __IO uint32_t MBC_DOM12_MEM3_BLK_NSE_W[1]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x119F0, array step: index*0x2000, index2*0x4, available only on: TRDC_WAKEUPMIX/TRDC2 (missing on TRDC_AONMIX/TRDC1) */ + uint8_t RESERVED_103[76]; + __IO uint32_t MBC_DOM13_MEM0_BLK_CFG_W[16]; /**< MBC Memory Block Configuration Word, array offset: 0x11A40, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */ + uint8_t RESERVED_104[192]; + __IO uint32_t MBC_DOM13_MEM0_BLK_NSE_W[4]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x11B40, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */ + uint8_t RESERVED_105[48]; + __IO uint32_t MBC_DOM13_MEM1_BLK_CFG_W[1]; /**< MBC Memory Block Configuration Word, array offset: 0x11B80, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */ + uint8_t RESERVED_106[28]; + __IO uint32_t MBC_DOM13_MEM1_BLK_NSE_W[1]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x11BA0, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */ + uint8_t RESERVED_107[4]; + __IO uint32_t MBC_DOM13_MEM2_BLK_CFG_W[1]; /**< MBC Memory Block Configuration Word, array offset: 0x11BA8, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */ + uint8_t RESERVED_108[28]; + __IO uint32_t MBC_DOM13_MEM2_BLK_NSE_W[1]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x11BC8, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */ + uint8_t RESERVED_109[4]; + __IO uint32_t MBC_DOM13_MEM3_BLK_CFG_W[3]; /**< MBC Memory Block Configuration Word, array offset: 0x11BD0, array step: index*0x2000, index2*0x4, available only on: TRDC_WAKEUPMIX/TRDC2 (missing on TRDC_AONMIX/TRDC1), valid indices: [0][0-2], [1][0] */ + uint8_t RESERVED_110[20]; + __IO uint32_t MBC_DOM13_MEM3_BLK_NSE_W[1]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x11BF0, array step: index*0x2000, index2*0x4, available only on: TRDC_WAKEUPMIX/TRDC2 (missing on TRDC_AONMIX/TRDC1) */ + uint8_t RESERVED_111[76]; + __IO uint32_t MBC_DOM14_MEM0_BLK_CFG_W[16]; /**< MBC Memory Block Configuration Word, array offset: 0x11C40, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */ + uint8_t RESERVED_112[192]; + __IO uint32_t MBC_DOM14_MEM0_BLK_NSE_W[4]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x11D40, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */ + uint8_t RESERVED_113[48]; + __IO uint32_t MBC_DOM14_MEM1_BLK_CFG_W[1]; /**< MBC Memory Block Configuration Word, array offset: 0x11D80, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */ + uint8_t RESERVED_114[28]; + __IO uint32_t MBC_DOM14_MEM1_BLK_NSE_W[1]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x11DA0, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */ + uint8_t RESERVED_115[4]; + __IO uint32_t MBC_DOM14_MEM2_BLK_CFG_W[1]; /**< MBC Memory Block Configuration Word, array offset: 0x11DA8, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */ + uint8_t RESERVED_116[28]; + __IO uint32_t MBC_DOM14_MEM2_BLK_NSE_W[1]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x11DC8, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */ + uint8_t RESERVED_117[4]; + __IO uint32_t MBC_DOM14_MEM3_BLK_CFG_W[3]; /**< MBC Memory Block Configuration Word, array offset: 0x11DD0, array step: index*0x2000, index2*0x4, available only on: TRDC_WAKEUPMIX/TRDC2 (missing on TRDC_AONMIX/TRDC1), valid indices: [0][0-2], [1][0] */ + uint8_t RESERVED_118[20]; + __IO uint32_t MBC_DOM14_MEM3_BLK_NSE_W[1]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x11DF0, array step: index*0x2000, index2*0x4, available only on: TRDC_WAKEUPMIX/TRDC2 (missing on TRDC_AONMIX/TRDC1) */ + uint8_t RESERVED_119[76]; + __IO uint32_t MBC_DOM15_MEM0_BLK_CFG_W[16]; /**< MBC Memory Block Configuration Word, array offset: 0x11E40, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */ + uint8_t RESERVED_120[192]; + __IO uint32_t MBC_DOM15_MEM0_BLK_NSE_W[4]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x11F40, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */ + uint8_t RESERVED_121[48]; + __IO uint32_t MBC_DOM15_MEM1_BLK_CFG_W[1]; /**< MBC Memory Block Configuration Word, array offset: 0x11F80, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */ + uint8_t RESERVED_122[28]; + __IO uint32_t MBC_DOM15_MEM1_BLK_NSE_W[1]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x11FA0, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */ + uint8_t RESERVED_123[4]; + __IO uint32_t MBC_DOM15_MEM2_BLK_CFG_W[1]; /**< MBC Memory Block Configuration Word, array offset: 0x11FA8, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */ + uint8_t RESERVED_124[28]; + __IO uint32_t MBC_DOM15_MEM2_BLK_NSE_W[1]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x11FC8, array step: index*0x2000, index2*0x4, irregular array, not all indices are valid */ + uint8_t RESERVED_125[4]; + __IO uint32_t MBC_DOM15_MEM3_BLK_CFG_W[3]; /**< MBC Memory Block Configuration Word, array offset: 0x11FD0, array step: index*0x2000, index2*0x4, available only on: TRDC_WAKEUPMIX/TRDC2 (missing on TRDC_AONMIX/TRDC1), valid indices: [0][0-2], [1][0] */ + uint8_t RESERVED_126[20]; + __IO uint32_t MBC_DOM15_MEM3_BLK_NSE_W[1]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x11FF0, array step: index*0x2000, index2*0x4, available only on: TRDC_WAKEUPMIX/TRDC2 (missing on TRDC_AONMIX/TRDC1) */ + uint8_t RESERVED_127[12]; + } MBC_INDEX[2]; + struct { /* offset: 0x14000, array step: 0x1000 */ + __I uint32_t MRC_GLBCFG; /**< MRC Global Configuration Register, array offset: 0x14000, array step: 0x1000, available only on: TRDC_WAKEUPMIX/TRDC2 (missing on TRDC_AONMIX/TRDC1) */ + uint8_t RESERVED_0[12]; + __IO uint32_t MRC_NSE_RGN_INDIRECT; /**< MRC NonSecure Enable Region Indirect, array offset: 0x14010, array step: 0x1000, available only on: TRDC_WAKEUPMIX/TRDC2 (missing on TRDC_AONMIX/TRDC1) */ + __IO uint32_t MRC_NSE_RGN_SET; /**< MRC NonSecure Enable Region Set, array offset: 0x14014, array step: 0x1000, available only on: TRDC_WAKEUPMIX/TRDC2 (missing on TRDC_AONMIX/TRDC1) */ + __IO uint32_t MRC_NSE_RGN_CLR; /**< MRC NonSecure Enable Region Clear, array offset: 0x14018, array step: 0x1000, available only on: TRDC_WAKEUPMIX/TRDC2 (missing on TRDC_AONMIX/TRDC1) */ + __IO uint32_t MRC_NSE_RGN_CLR_ALL; /**< MRC NonSecure Enable Region Clear All, array offset: 0x1401C, array step: 0x1000, available only on: TRDC_WAKEUPMIX/TRDC2 (missing on TRDC_AONMIX/TRDC1) */ + __IO uint32_t MRC_GLBAC[8]; /**< MRC Global Access Control, array offset: 0x14020, array step: index*0x1000, index2*0x4, available only on: TRDC_WAKEUPMIX/TRDC2 (missing on TRDC_AONMIX/TRDC1) */ + __IO uint32_t MRC_DOM0_RGD_W[8][2]; /**< MRC Region Descriptor Word 0..MRC Region Descriptor Word 1, array offset: 0x14040, array step: index*0x1000, index2*0x8, index3*0x4, available only on: TRDC_WAKEUPMIX/TRDC2 (missing on TRDC_AONMIX/TRDC1) */ + uint8_t RESERVED_1[64]; + __IO uint32_t MRC_DOM0_RGD_NSE; /**< MRC Region Descriptor NonSecure Enable, array offset: 0x140C0, array step: 0x1000, available only on: TRDC_WAKEUPMIX/TRDC2 (missing on TRDC_AONMIX/TRDC1) */ + uint8_t RESERVED_2[124]; + __IO uint32_t MRC_DOM1_RGD_W[8][2]; /**< MRC Region Descriptor Word 0..MRC Region Descriptor Word 1, array offset: 0x14140, array step: index*0x1000, index2*0x8, index3*0x4, available only on: TRDC_WAKEUPMIX/TRDC2 (missing on TRDC_AONMIX/TRDC1) */ + uint8_t RESERVED_3[64]; + __IO uint32_t MRC_DOM1_RGD_NSE; /**< MRC Region Descriptor NonSecure Enable, array offset: 0x141C0, array step: 0x1000, available only on: TRDC_WAKEUPMIX/TRDC2 (missing on TRDC_AONMIX/TRDC1) */ + uint8_t RESERVED_4[124]; + __IO uint32_t MRC_DOM2_RGD_W[8][2]; /**< MRC Region Descriptor Word 0..MRC Region Descriptor Word 1, array offset: 0x14240, array step: index*0x1000, index2*0x8, index3*0x4, available only on: TRDC_WAKEUPMIX/TRDC2 (missing on TRDC_AONMIX/TRDC1) */ + uint8_t RESERVED_5[64]; + __IO uint32_t MRC_DOM2_RGD_NSE; /**< MRC Region Descriptor NonSecure Enable, array offset: 0x142C0, array step: 0x1000, available only on: TRDC_WAKEUPMIX/TRDC2 (missing on TRDC_AONMIX/TRDC1) */ + uint8_t RESERVED_6[124]; + __IO uint32_t MRC_DOM3_RGD_W[8][2]; /**< MRC Region Descriptor Word 0..MRC Region Descriptor Word 1, array offset: 0x14340, array step: index*0x1000, index2*0x8, index3*0x4, available only on: TRDC_WAKEUPMIX/TRDC2 (missing on TRDC_AONMIX/TRDC1) */ + uint8_t RESERVED_7[64]; + __IO uint32_t MRC_DOM3_RGD_NSE; /**< MRC Region Descriptor NonSecure Enable, array offset: 0x143C0, array step: 0x1000, available only on: TRDC_WAKEUPMIX/TRDC2 (missing on TRDC_AONMIX/TRDC1) */ + uint8_t RESERVED_8[124]; + __IO uint32_t MRC_DOM4_RGD_W[8][2]; /**< MRC Region Descriptor Word 0..MRC Region Descriptor Word 1, array offset: 0x14440, array step: index*0x1000, index2*0x8, index3*0x4, available only on: TRDC_WAKEUPMIX/TRDC2 (missing on TRDC_AONMIX/TRDC1) */ + uint8_t RESERVED_9[64]; + __IO uint32_t MRC_DOM4_RGD_NSE; /**< MRC Region Descriptor NonSecure Enable, array offset: 0x144C0, array step: 0x1000, available only on: TRDC_WAKEUPMIX/TRDC2 (missing on TRDC_AONMIX/TRDC1) */ + uint8_t RESERVED_10[124]; + __IO uint32_t MRC_DOM5_RGD_W[8][2]; /**< MRC Region Descriptor Word 0..MRC Region Descriptor Word 1, array offset: 0x14540, array step: index*0x1000, index2*0x8, index3*0x4, available only on: TRDC_WAKEUPMIX/TRDC2 (missing on TRDC_AONMIX/TRDC1) */ + uint8_t RESERVED_11[64]; + __IO uint32_t MRC_DOM5_RGD_NSE; /**< MRC Region Descriptor NonSecure Enable, array offset: 0x145C0, array step: 0x1000, available only on: TRDC_WAKEUPMIX/TRDC2 (missing on TRDC_AONMIX/TRDC1) */ + uint8_t RESERVED_12[124]; + __IO uint32_t MRC_DOM6_RGD_W[8][2]; /**< MRC Region Descriptor Word 0..MRC Region Descriptor Word 1, array offset: 0x14640, array step: index*0x1000, index2*0x8, index3*0x4, available only on: TRDC_WAKEUPMIX/TRDC2 (missing on TRDC_AONMIX/TRDC1) */ + uint8_t RESERVED_13[64]; + __IO uint32_t MRC_DOM6_RGD_NSE; /**< MRC Region Descriptor NonSecure Enable, array offset: 0x146C0, array step: 0x1000, available only on: TRDC_WAKEUPMIX/TRDC2 (missing on TRDC_AONMIX/TRDC1) */ + uint8_t RESERVED_14[124]; + __IO uint32_t MRC_DOM7_RGD_W[8][2]; /**< MRC Region Descriptor Word 0..MRC Region Descriptor Word 1, array offset: 0x14740, array step: index*0x1000, index2*0x8, index3*0x4, available only on: TRDC_WAKEUPMIX/TRDC2 (missing on TRDC_AONMIX/TRDC1) */ + uint8_t RESERVED_15[64]; + __IO uint32_t MRC_DOM7_RGD_NSE; /**< MRC Region Descriptor NonSecure Enable, array offset: 0x147C0, array step: 0x1000, available only on: TRDC_WAKEUPMIX/TRDC2 (missing on TRDC_AONMIX/TRDC1) */ + uint8_t RESERVED_16[124]; + __IO uint32_t MRC_DOM8_RGD_W[8][2]; /**< MRC Region Descriptor Word 0..MRC Region Descriptor Word 1, array offset: 0x14840, array step: index*0x1000, index2*0x8, index3*0x4, available only on: TRDC_WAKEUPMIX/TRDC2 (missing on TRDC_AONMIX/TRDC1) */ + uint8_t RESERVED_17[64]; + __IO uint32_t MRC_DOM8_RGD_NSE; /**< MRC Region Descriptor NonSecure Enable, array offset: 0x148C0, array step: 0x1000, available only on: TRDC_WAKEUPMIX/TRDC2 (missing on TRDC_AONMIX/TRDC1) */ + uint8_t RESERVED_18[124]; + __IO uint32_t MRC_DOM9_RGD_W[8][2]; /**< MRC Region Descriptor Word 0..MRC Region Descriptor Word 1, array offset: 0x14940, array step: index*0x1000, index2*0x8, index3*0x4, available only on: TRDC_WAKEUPMIX/TRDC2 (missing on TRDC_AONMIX/TRDC1) */ + uint8_t RESERVED_19[64]; + __IO uint32_t MRC_DOM9_RGD_NSE; /**< MRC Region Descriptor NonSecure Enable, array offset: 0x149C0, array step: 0x1000, available only on: TRDC_WAKEUPMIX/TRDC2 (missing on TRDC_AONMIX/TRDC1) */ + uint8_t RESERVED_20[124]; + __IO uint32_t MRC_DOM10_RGD_W[8][2]; /**< MRC Region Descriptor Word 0..MRC Region Descriptor Word 1, array offset: 0x14A40, array step: index*0x1000, index2*0x8, index3*0x4, available only on: TRDC_WAKEUPMIX/TRDC2 (missing on TRDC_AONMIX/TRDC1) */ + uint8_t RESERVED_21[64]; + __IO uint32_t MRC_DOM10_RGD_NSE; /**< MRC Region Descriptor NonSecure Enable, array offset: 0x14AC0, array step: 0x1000, available only on: TRDC_WAKEUPMIX/TRDC2 (missing on TRDC_AONMIX/TRDC1) */ + uint8_t RESERVED_22[124]; + __IO uint32_t MRC_DOM11_RGD_W[8][2]; /**< MRC Region Descriptor Word 0..MRC Region Descriptor Word 1, array offset: 0x14B40, array step: index*0x1000, index2*0x8, index3*0x4, available only on: TRDC_WAKEUPMIX/TRDC2 (missing on TRDC_AONMIX/TRDC1) */ + uint8_t RESERVED_23[64]; + __IO uint32_t MRC_DOM11_RGD_NSE; /**< MRC Region Descriptor NonSecure Enable, array offset: 0x14BC0, array step: 0x1000, available only on: TRDC_WAKEUPMIX/TRDC2 (missing on TRDC_AONMIX/TRDC1) */ + uint8_t RESERVED_24[124]; + __IO uint32_t MRC_DOM12_RGD_W[8][2]; /**< MRC Region Descriptor Word 0..MRC Region Descriptor Word 1, array offset: 0x14C40, array step: index*0x1000, index2*0x8, index3*0x4, available only on: TRDC_WAKEUPMIX/TRDC2 (missing on TRDC_AONMIX/TRDC1) */ + uint8_t RESERVED_25[64]; + __IO uint32_t MRC_DOM12_RGD_NSE; /**< MRC Region Descriptor NonSecure Enable, array offset: 0x14CC0, array step: 0x1000, available only on: TRDC_WAKEUPMIX/TRDC2 (missing on TRDC_AONMIX/TRDC1) */ + uint8_t RESERVED_26[124]; + __IO uint32_t MRC_DOM13_RGD_W[8][2]; /**< MRC Region Descriptor Word 0..MRC Region Descriptor Word 1, array offset: 0x14D40, array step: index*0x1000, index2*0x8, index3*0x4, available only on: TRDC_WAKEUPMIX/TRDC2 (missing on TRDC_AONMIX/TRDC1) */ + uint8_t RESERVED_27[64]; + __IO uint32_t MRC_DOM13_RGD_NSE; /**< MRC Region Descriptor NonSecure Enable, array offset: 0x14DC0, array step: 0x1000, available only on: TRDC_WAKEUPMIX/TRDC2 (missing on TRDC_AONMIX/TRDC1) */ + uint8_t RESERVED_28[124]; + __IO uint32_t MRC_DOM14_RGD_W[8][2]; /**< MRC Region Descriptor Word 0..MRC Region Descriptor Word 1, array offset: 0x14E40, array step: index*0x1000, index2*0x8, index3*0x4, available only on: TRDC_WAKEUPMIX/TRDC2 (missing on TRDC_AONMIX/TRDC1) */ + uint8_t RESERVED_29[64]; + __IO uint32_t MRC_DOM14_RGD_NSE; /**< MRC Region Descriptor NonSecure Enable, array offset: 0x14EC0, array step: 0x1000, available only on: TRDC_WAKEUPMIX/TRDC2 (missing on TRDC_AONMIX/TRDC1) */ + uint8_t RESERVED_30[124]; + __IO uint32_t MRC_DOM15_RGD_W[8][2]; /**< MRC Region Descriptor Word 0..MRC Region Descriptor Word 1, array offset: 0x14F40, array step: index*0x1000, index2*0x8, index3*0x4, available only on: TRDC_WAKEUPMIX/TRDC2 (missing on TRDC_AONMIX/TRDC1) */ + uint8_t RESERVED_31[64]; + __IO uint32_t MRC_DOM15_RGD_NSE; /**< MRC Region Descriptor NonSecure Enable, array offset: 0x14FC0, array step: 0x1000, available only on: TRDC_WAKEUPMIX/TRDC2 (missing on TRDC_AONMIX/TRDC1) */ + uint8_t RESERVED_32[60]; + } MRC_INDEX[2]; +} TRDC_MBC2_Type; + +/* ---------------------------------------------------------------------------- + -- TRDC_MBC2 Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup TRDC_MBC2_Register_Masks TRDC_MBC2 Register Masks + * @{ + */ + +/*! @name TRDC_CR - TRDC Register */ +/*! @{ */ + +#define TRDC_MBC2_TRDC_CR_GVLDM_MASK (0x1U) +#define TRDC_MBC2_TRDC_CR_GVLDM_SHIFT (0U) +/*! GVLDM - Global Valid for Domain Assignment Controllers + * 0b0..TRDC DACs are disabled. + * 0b1..TRDC DACs are enabled. + */ +#define TRDC_MBC2_TRDC_CR_GVLDM(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_TRDC_CR_GVLDM_SHIFT)) & TRDC_MBC2_TRDC_CR_GVLDM_MASK) + +#define TRDC_MBC2_TRDC_CR_HRL_MASK (0x1EU) +#define TRDC_MBC2_TRDC_CR_HRL_SHIFT (1U) +/*! HRL - Hardware Revision Level */ +#define TRDC_MBC2_TRDC_CR_HRL(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_TRDC_CR_HRL_SHIFT)) & TRDC_MBC2_TRDC_CR_HRL_MASK) + +#define TRDC_MBC2_TRDC_CR_GVLDB_MASK (0x4000U) +#define TRDC_MBC2_TRDC_CR_GVLDB_SHIFT (14U) +/*! GVLDB - Global Valid for Memory Block Checkers + * 0b0..TRDC MBCs are disabled. + * 0b1..TRDC MBCs are enabled. + */ +#define TRDC_MBC2_TRDC_CR_GVLDB(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_TRDC_CR_GVLDB_SHIFT)) & TRDC_MBC2_TRDC_CR_GVLDB_MASK) + +#define TRDC_MBC2_TRDC_CR_GVLDR_MASK (0x8000U) +#define TRDC_MBC2_TRDC_CR_GVLDR_SHIFT (15U) +/*! GVLDR - Global Valid for Memory Region Checkers + * 0b0..TRDC MRCs are disabled. + * 0b1..TRDC MRCs are enabled. + */ +#define TRDC_MBC2_TRDC_CR_GVLDR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_TRDC_CR_GVLDR_SHIFT)) & TRDC_MBC2_TRDC_CR_GVLDR_MASK) + +#define TRDC_MBC2_TRDC_CR_LK1_MASK (0x40000000U) +#define TRDC_MBC2_TRDC_CR_LK1_SHIFT (30U) +/*! LK1 - Lock Status + * 0b0..The CR can be written by any secure privileged write. + * 0b1..The CR is locked (read-only) until the next reset. + */ +#define TRDC_MBC2_TRDC_CR_LK1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_TRDC_CR_LK1_SHIFT)) & TRDC_MBC2_TRDC_CR_LK1_MASK) +/*! @} */ + +/*! @name TRDC_HWCFG0 - TRDC Hardware Configuration Register 0 */ +/*! @{ */ + +#define TRDC_MBC2_TRDC_HWCFG0_NDID_MASK (0x1FU) +#define TRDC_MBC2_TRDC_HWCFG0_NDID_SHIFT (0U) +/*! NDID - Number of domains */ +#define TRDC_MBC2_TRDC_HWCFG0_NDID(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_TRDC_HWCFG0_NDID_SHIFT)) & TRDC_MBC2_TRDC_HWCFG0_NDID_MASK) + +#define TRDC_MBC2_TRDC_HWCFG0_NMSTR_MASK (0xFF00U) +#define TRDC_MBC2_TRDC_HWCFG0_NMSTR_SHIFT (8U) +/*! NMSTR - Number of bus masters */ +#define TRDC_MBC2_TRDC_HWCFG0_NMSTR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_TRDC_HWCFG0_NMSTR_SHIFT)) & TRDC_MBC2_TRDC_HWCFG0_NMSTR_MASK) + +#define TRDC_MBC2_TRDC_HWCFG0_NMBC_MASK (0xF0000U) +#define TRDC_MBC2_TRDC_HWCFG0_NMBC_SHIFT (16U) +/*! NMBC - Number of MBCs */ +#define TRDC_MBC2_TRDC_HWCFG0_NMBC(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_TRDC_HWCFG0_NMBC_SHIFT)) & TRDC_MBC2_TRDC_HWCFG0_NMBC_MASK) + +#define TRDC_MBC2_TRDC_HWCFG0_NMRC_MASK (0x1F000000U) +#define TRDC_MBC2_TRDC_HWCFG0_NMRC_SHIFT (24U) +/*! NMRC - Number of MRCs */ +#define TRDC_MBC2_TRDC_HWCFG0_NMRC(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_TRDC_HWCFG0_NMRC_SHIFT)) & TRDC_MBC2_TRDC_HWCFG0_NMRC_MASK) + +#define TRDC_MBC2_TRDC_HWCFG0_MID_MASK (0xE0000000U) +#define TRDC_MBC2_TRDC_HWCFG0_MID_SHIFT (29U) +/*! MID - Module ID */ +#define TRDC_MBC2_TRDC_HWCFG0_MID(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_TRDC_HWCFG0_MID_SHIFT)) & TRDC_MBC2_TRDC_HWCFG0_MID_MASK) +/*! @} */ + +/*! @name TRDC_HWCFG1 - TRDC Hardware Configuration Register 1 */ +/*! @{ */ + +#define TRDC_MBC2_TRDC_HWCFG1_DID_MASK (0xFU) +#define TRDC_MBC2_TRDC_HWCFG1_DID_SHIFT (0U) +/*! DID - Domain identifier number */ +#define TRDC_MBC2_TRDC_HWCFG1_DID(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_TRDC_HWCFG1_DID_SHIFT)) & TRDC_MBC2_TRDC_HWCFG1_DID_MASK) +/*! @} */ + +/*! @name DACFG - Domain Assignment Configuration Register */ +/*! @{ */ + +#define TRDC_MBC2_DACFG_NMDAR_MASK (0xFU) +#define TRDC_MBC2_DACFG_NMDAR_SHIFT (0U) +/*! NMDAR - Number of master domain assignment registers for bus master m */ +#define TRDC_MBC2_DACFG_NMDAR(x) (((uint8_t)(((uint8_t)(x)) << TRDC_MBC2_DACFG_NMDAR_SHIFT)) & TRDC_MBC2_DACFG_NMDAR_MASK) + +#define TRDC_MBC2_DACFG_NCM_MASK (0x80U) +#define TRDC_MBC2_DACFG_NCM_SHIFT (7U) +/*! NCM - Non-CPU Master + * 0b0..Bus master is a processor. + * 0b1..Bus master is a non-processor. + */ +#define TRDC_MBC2_DACFG_NCM(x) (((uint8_t)(((uint8_t)(x)) << TRDC_MBC2_DACFG_NCM_SHIFT)) & TRDC_MBC2_DACFG_NCM_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_DACFG */ +#define TRDC_MBC2_DACFG_COUNT (5U) + +/*! @name TRDC_IDAU_CR - TRDC IDAU Control Register */ +/*! @{ */ + +#define TRDC_MBC2_TRDC_IDAU_CR_VLD_MASK (0x1U) +#define TRDC_MBC2_TRDC_IDAU_CR_VLD_SHIFT (0U) +/*! VLD - Valid */ +#define TRDC_MBC2_TRDC_IDAU_CR_VLD(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_TRDC_IDAU_CR_VLD_SHIFT)) & TRDC_MBC2_TRDC_IDAU_CR_VLD_MASK) + +#define TRDC_MBC2_TRDC_IDAU_CR_CFGSECEXT_MASK (0x8U) +#define TRDC_MBC2_TRDC_IDAU_CR_CFGSECEXT_SHIFT (3U) +/*! CFGSECEXT - Configure Security Extension + * 0b0..Armv8M Security Extension is disabled + * 0b1..Armv8-M Security Extension is enabled + */ +#define TRDC_MBC2_TRDC_IDAU_CR_CFGSECEXT(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_TRDC_IDAU_CR_CFGSECEXT_SHIFT)) & TRDC_MBC2_TRDC_IDAU_CR_CFGSECEXT_MASK) + +#define TRDC_MBC2_TRDC_IDAU_CR_MPUSDIS_MASK (0x10U) +#define TRDC_MBC2_TRDC_IDAU_CR_MPUSDIS_SHIFT (4U) +/*! MPUSDIS - Secure Memory Protection Unit Disabled + * 0b0..Secure MPU is enabled + * 0b1..Secure MPU is disabled + */ +#define TRDC_MBC2_TRDC_IDAU_CR_MPUSDIS(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_TRDC_IDAU_CR_MPUSDIS_SHIFT)) & TRDC_MBC2_TRDC_IDAU_CR_MPUSDIS_MASK) + +#define TRDC_MBC2_TRDC_IDAU_CR_MPUNSDIS_MASK (0x20U) +#define TRDC_MBC2_TRDC_IDAU_CR_MPUNSDIS_SHIFT (5U) +/*! MPUNSDIS - NonSecure Memory Protection Unit Disabled + * 0b0..Nonsecure MPU is enabled + * 0b1..Nonsecure MPU is disabled + */ +#define TRDC_MBC2_TRDC_IDAU_CR_MPUNSDIS(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_TRDC_IDAU_CR_MPUNSDIS_SHIFT)) & TRDC_MBC2_TRDC_IDAU_CR_MPUNSDIS_MASK) + +#define TRDC_MBC2_TRDC_IDAU_CR_SAUDIS_MASK (0x40U) +#define TRDC_MBC2_TRDC_IDAU_CR_SAUDIS_SHIFT (6U) +/*! SAUDIS - Security Attribution Unit Disable + * 0b0..SAU is enabled + * 0b1..SAU is disabled + */ +#define TRDC_MBC2_TRDC_IDAU_CR_SAUDIS(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_TRDC_IDAU_CR_SAUDIS_SHIFT)) & TRDC_MBC2_TRDC_IDAU_CR_SAUDIS_MASK) + +#define TRDC_MBC2_TRDC_IDAU_CR_LKSVTAIRCR_MASK (0x100U) +#define TRDC_MBC2_TRDC_IDAU_CR_LKSVTAIRCR_SHIFT (8U) +/*! LKSVTAIRCR - Lock Secure VTOR, Application interrupt and Reset Control Registers + * 0b0..Unlock these registers + * 0b1..Disable writes to the VTOR_S, AIRCR[PRIS], and AIRCR[BFHFNMINS] registers + */ +#define TRDC_MBC2_TRDC_IDAU_CR_LKSVTAIRCR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_TRDC_IDAU_CR_LKSVTAIRCR_SHIFT)) & TRDC_MBC2_TRDC_IDAU_CR_LKSVTAIRCR_MASK) + +#define TRDC_MBC2_TRDC_IDAU_CR_LKNSVTOR_MASK (0x200U) +#define TRDC_MBC2_TRDC_IDAU_CR_LKNSVTOR_SHIFT (9U) +/*! LKNSVTOR - Lock Nonsecure Vector Table Offset Register + * 0b0..Unlock this register + * 0b1..Disable writes to the VTOR_NS register + */ +#define TRDC_MBC2_TRDC_IDAU_CR_LKNSVTOR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_TRDC_IDAU_CR_LKNSVTOR_SHIFT)) & TRDC_MBC2_TRDC_IDAU_CR_LKNSVTOR_MASK) + +#define TRDC_MBC2_TRDC_IDAU_CR_LKSMPU_MASK (0x400U) +#define TRDC_MBC2_TRDC_IDAU_CR_LKSMPU_SHIFT (10U) +/*! LKSMPU - Lock Secure MPU + * 0b0..Unlock these registers + * 0b1..Disable writes to the MPU_CTRL, MPU_RNR, MPU_RBAR, MPU_RLAR, MPU_RBAR_An and MPU_RLAR_An from software or + * from a debug agent connected to the processor in Secure state + */ +#define TRDC_MBC2_TRDC_IDAU_CR_LKSMPU(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_TRDC_IDAU_CR_LKSMPU_SHIFT)) & TRDC_MBC2_TRDC_IDAU_CR_LKSMPU_MASK) + +#define TRDC_MBC2_TRDC_IDAU_CR_LKNSMPU_MASK (0x800U) +#define TRDC_MBC2_TRDC_IDAU_CR_LKNSMPU_SHIFT (11U) +/*! LKNSMPU - Lock Nonsecure MPU + * 0b0..Unlock these registers + * 0b1..Disable writes to the MPU_CTRL_NS, MPU_RNR_NS, MPU_RBAR_NS, MPU_RLAR_NS, MPU_RBAR_A_NSn and + * MPU_RLAR_A_NSn from software or from a debug agent connected to the processor + */ +#define TRDC_MBC2_TRDC_IDAU_CR_LKNSMPU(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_TRDC_IDAU_CR_LKNSMPU_SHIFT)) & TRDC_MBC2_TRDC_IDAU_CR_LKNSMPU_MASK) + +#define TRDC_MBC2_TRDC_IDAU_CR_LKSAU_MASK (0x1000U) +#define TRDC_MBC2_TRDC_IDAU_CR_LKSAU_SHIFT (12U) +/*! LKSAU - Lock SAU + * 0b0..Unlock these registers + * 0b1..Disable writes to the SAU_CTRL, SAU_RNR, SAU_RBAR and SAU_RLAR registers from software or from a debug agent connected to the processor + */ +#define TRDC_MBC2_TRDC_IDAU_CR_LKSAU(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_TRDC_IDAU_CR_LKSAU_SHIFT)) & TRDC_MBC2_TRDC_IDAU_CR_LKSAU_MASK) + +#define TRDC_MBC2_TRDC_IDAU_CR_PCURRNS_MASK (0x80000000U) +#define TRDC_MBC2_TRDC_IDAU_CR_PCURRNS_SHIFT (31U) +/*! PCURRNS - Processor current security + * 0b0..Processor is in Secure state + * 0b1..Processor is in Nonsecure state + */ +#define TRDC_MBC2_TRDC_IDAU_CR_PCURRNS(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_TRDC_IDAU_CR_PCURRNS_SHIFT)) & TRDC_MBC2_TRDC_IDAU_CR_PCURRNS_MASK) +/*! @} */ + +/*! @name TRDC_FLW_CTL - TRDC FLW Control */ +/*! @{ */ + +#define TRDC_MBC2_TRDC_FLW_CTL_LK_MASK (0x40000000U) +#define TRDC_MBC2_TRDC_FLW_CTL_LK_SHIFT (30U) +/*! LK - Lock bit + * 0b0..FLW registers may be modified. + * 0b1..FLW registers are locked until the next reset. + */ +#define TRDC_MBC2_TRDC_FLW_CTL_LK(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_TRDC_FLW_CTL_LK_SHIFT)) & TRDC_MBC2_TRDC_FLW_CTL_LK_MASK) + +#define TRDC_MBC2_TRDC_FLW_CTL_V_MASK (0x80000000U) +#define TRDC_MBC2_TRDC_FLW_CTL_V_SHIFT (31U) +/*! V - Valid bit + * 0b0..FLW function is disabled. + * 0b1..FLW function is enabled. + */ +#define TRDC_MBC2_TRDC_FLW_CTL_V(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_TRDC_FLW_CTL_V_SHIFT)) & TRDC_MBC2_TRDC_FLW_CTL_V_MASK) +/*! @} */ + +/*! @name TRDC_FLW_PBASE - TRDC FLW Physical Base */ +/*! @{ */ + +#define TRDC_MBC2_TRDC_FLW_PBASE_PBASE_MASK (0xFFFFFFFFU) +#define TRDC_MBC2_TRDC_FLW_PBASE_PBASE_SHIFT (0U) +/*! PBASE - Physical base address */ +#define TRDC_MBC2_TRDC_FLW_PBASE_PBASE(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_TRDC_FLW_PBASE_PBASE_SHIFT)) & TRDC_MBC2_TRDC_FLW_PBASE_PBASE_MASK) +/*! @} */ + +/*! @name TRDC_FLW_ABASE - TRDC FLW Array Base */ +/*! @{ */ + +#define TRDC_MBC2_TRDC_FLW_ABASE_ABASE_L_MASK (0x3F8000U) +#define TRDC_MBC2_TRDC_FLW_ABASE_ABASE_L_SHIFT (15U) +/*! ABASE_L - Array base address low */ +#define TRDC_MBC2_TRDC_FLW_ABASE_ABASE_L(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_TRDC_FLW_ABASE_ABASE_L_SHIFT)) & TRDC_MBC2_TRDC_FLW_ABASE_ABASE_L_MASK) + +#define TRDC_MBC2_TRDC_FLW_ABASE_ABASE_H_MASK (0xFFC00000U) +#define TRDC_MBC2_TRDC_FLW_ABASE_ABASE_H_SHIFT (22U) +/*! ABASE_H - Array base address high */ +#define TRDC_MBC2_TRDC_FLW_ABASE_ABASE_H(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_TRDC_FLW_ABASE_ABASE_H_SHIFT)) & TRDC_MBC2_TRDC_FLW_ABASE_ABASE_H_MASK) +/*! @} */ + +/*! @name TRDC_FLW_BCNT - TRDC FLW Block Count */ +/*! @{ */ + +#define TRDC_MBC2_TRDC_FLW_BCNT_BCNT_MASK (0x7FFFU) +#define TRDC_MBC2_TRDC_FLW_BCNT_BCNT_SHIFT (0U) +/*! BCNT - Block Count */ +#define TRDC_MBC2_TRDC_FLW_BCNT_BCNT(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_TRDC_FLW_BCNT_BCNT_SHIFT)) & TRDC_MBC2_TRDC_FLW_BCNT_BCNT_MASK) +/*! @} */ + +/*! @name TRDC_FDID - TRDC Fault Domain ID */ +/*! @{ */ + +#define TRDC_MBC2_TRDC_FDID_FDID_MASK (0xFU) +#define TRDC_MBC2_TRDC_FDID_FDID_SHIFT (0U) +/*! FDID - Domain ID of Faulted Access */ +#define TRDC_MBC2_TRDC_FDID_FDID(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_TRDC_FDID_FDID_SHIFT)) & TRDC_MBC2_TRDC_FDID_FDID_MASK) +/*! @} */ + +/*! @name TRDC_DERRLOC - TRDC Domain Error Location Register */ +/*! @{ */ + +#define TRDC_MBC2_TRDC_DERRLOC_MBCINST_MASK (0xFFU) +#define TRDC_MBC2_TRDC_DERRLOC_MBCINST_SHIFT (0U) +/*! MBCINST - MBC instance */ +#define TRDC_MBC2_TRDC_DERRLOC_MBCINST(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_TRDC_DERRLOC_MBCINST_SHIFT)) & TRDC_MBC2_TRDC_DERRLOC_MBCINST_MASK) + +#define TRDC_MBC2_TRDC_DERRLOC_MRCINST_MASK (0xFFFF0000U) +#define TRDC_MBC2_TRDC_DERRLOC_MRCINST_SHIFT (16U) +/*! MRCINST - MRC instance */ +#define TRDC_MBC2_TRDC_DERRLOC_MRCINST(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_TRDC_DERRLOC_MRCINST_SHIFT)) & TRDC_MBC2_TRDC_DERRLOC_MRCINST_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_TRDC_DERRLOC */ +#define TRDC_MBC2_TRDC_DERRLOC_COUNT (16U) + +/*! @name W0 - MBC Domain Error Word0 Register */ +/*! @{ */ + +#define TRDC_MBC2_W0_EADDR_MASK (0xFFFFFFFFU) +#define TRDC_MBC2_W0_EADDR_SHIFT (0U) +/*! EADDR - Error address */ +#define TRDC_MBC2_W0_EADDR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_W0_EADDR_SHIFT)) & TRDC_MBC2_W0_EADDR_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_W0 */ +#define TRDC_MBC2_W0_COUNT (2U) + +/*! @name W1 - MBC Domain Error Word1 Register */ +/*! @{ */ + +#define TRDC_MBC2_W1_EDID_MASK (0xFU) +#define TRDC_MBC2_W1_EDID_SHIFT (0U) +/*! EDID - Error domain identifier */ +#define TRDC_MBC2_W1_EDID(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_W1_EDID_SHIFT)) & TRDC_MBC2_W1_EDID_MASK) + +#define TRDC_MBC2_W1_EATR_MASK (0x700U) +#define TRDC_MBC2_W1_EATR_SHIFT (8U) +/*! EATR - Error attributes + * 0b000..Secure user mode, instruction fetch access. + * 0b001..Secure user mode, data access. + * 0b010..Secure privileged mode, instruction fetch access. + * 0b011..Secure privileged mode, data access. + * 0b100..Nonsecure user mode, instruction fetch access. + * 0b101..Nonsecure user mode, data access. + * 0b110..Nonsecure privileged mode, instruction fetch access. + * 0b111..Nonsecure privileged mode, data access. + */ +#define TRDC_MBC2_W1_EATR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_W1_EATR_SHIFT)) & TRDC_MBC2_W1_EATR_MASK) + +#define TRDC_MBC2_W1_ERW_MASK (0x800U) +#define TRDC_MBC2_W1_ERW_SHIFT (11U) +/*! ERW - Error read/write + * 0b0..Read access + * 0b1..Write access + */ +#define TRDC_MBC2_W1_ERW(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_W1_ERW_SHIFT)) & TRDC_MBC2_W1_ERW_MASK) + +#define TRDC_MBC2_W1_EPORT_MASK (0x7000000U) +#define TRDC_MBC2_W1_EPORT_SHIFT (24U) +/*! EPORT - Error port + * 0b000..mbcxslv0 + * 0b001..mbcxslv1 + * 0b010..mbcxslv2 + * 0b011..mbcxslv3 + */ +#define TRDC_MBC2_W1_EPORT(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_W1_EPORT_SHIFT)) & TRDC_MBC2_W1_EPORT_MASK) + +#define TRDC_MBC2_W1_EST_MASK (0xC0000000U) +#define TRDC_MBC2_W1_EST_SHIFT (30U) +/*! EST - Error state + * 0b00..No access violation has been detected. + * 0b01..No access violation has been detected. + * 0b10..A single access violation has been detected. + * 0b11..Multiple access violations for this domain have been detected by this submodule instance. Only the + * address and attribute information for the first error have been captured in DERR_W0_i and DERR_W1_i. + */ +#define TRDC_MBC2_W1_EST(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_W1_EST_SHIFT)) & TRDC_MBC2_W1_EST_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_W1 */ +#define TRDC_MBC2_W1_COUNT (2U) + +/*! @name W3 - MBC Domain Error Word3 Register */ +/*! @{ */ + +#define TRDC_MBC2_W3_RECR_MASK (0xC0000000U) +#define TRDC_MBC2_W3_RECR_SHIFT (30U) +/*! RECR - Rearm Error Capture Registers */ +#define TRDC_MBC2_W3_RECR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_W3_RECR_SHIFT)) & TRDC_MBC2_W3_RECR_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_W3 */ +#define TRDC_MBC2_W3_COUNT (2U) + +/*! @name W0 - MRC Domain Error Word0 Register */ +/*! @{ */ + +#define TRDC_MBC2_W0_EADDR_MASK (0xFFFFFFFFU) +#define TRDC_MBC2_W0_EADDR_SHIFT (0U) +/*! EADDR - Error address */ +#define TRDC_MBC2_W0_EADDR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_W0_EADDR_SHIFT)) & TRDC_MBC2_W0_EADDR_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_W0 */ +#define TRDC_MBC2_MRC_DERR_W0_COUNT (2U) + +/*! @name W1 - MRC Domain Error Word1 Register */ +/*! @{ */ + +#define TRDC_MBC2_W1_EDID_MASK (0xFU) +#define TRDC_MBC2_W1_EDID_SHIFT (0U) +/*! EDID - Error domain identifier */ +#define TRDC_MBC2_W1_EDID(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_W1_EDID_SHIFT)) & TRDC_MBC2_W1_EDID_MASK) + +#define TRDC_MBC2_W1_EATR_MASK (0x700U) +#define TRDC_MBC2_W1_EATR_SHIFT (8U) +/*! EATR - Error attributes + * 0b000..Secure user mode, instruction fetch access. + * 0b001..Secure user mode, data access. + * 0b010..Secure privileged mode, instruction fetch access. + * 0b011..Secure privileged mode, data access. + * 0b100..Nonsecure user mode, instruction fetch access. + * 0b101..Nonsecure user mode, data access. + * 0b110..Nonsecure privileged mode, instruction fetch access. + * 0b111..Nonsecure privileged mode, data access. + */ +#define TRDC_MBC2_W1_EATR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_W1_EATR_SHIFT)) & TRDC_MBC2_W1_EATR_MASK) + +#define TRDC_MBC2_W1_ERW_MASK (0x800U) +#define TRDC_MBC2_W1_ERW_SHIFT (11U) +/*! ERW - Error read/write + * 0b0..Read access + * 0b1..Write access + */ +#define TRDC_MBC2_W1_ERW(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_W1_ERW_SHIFT)) & TRDC_MBC2_W1_ERW_MASK) + +#define TRDC_MBC2_W1_EPORT_MASK (0x7000000U) +#define TRDC_MBC2_W1_EPORT_SHIFT (24U) +/*! EPORT - Error port */ +#define TRDC_MBC2_W1_EPORT(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_W1_EPORT_SHIFT)) & TRDC_MBC2_W1_EPORT_MASK) + +#define TRDC_MBC2_W1_EST_MASK (0xC0000000U) +#define TRDC_MBC2_W1_EST_SHIFT (30U) +/*! EST - Error state + * 0b00..No access violation has been detected. + * 0b01..No access violation has been detected. + * 0b10..A single access violation has been detected. + * 0b11..Multiple access violations for this domain have been detected by this submodule instance. Only the + * address and attribute information for the first error have been captured in DERR_W0_i and DERR_W1_i. + */ +#define TRDC_MBC2_W1_EST(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_W1_EST_SHIFT)) & TRDC_MBC2_W1_EST_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_W1 */ +#define TRDC_MBC2_MRC_DERR_W1_COUNT (2U) + +/*! @name W3 - MRC Domain Error Word3 Register */ +/*! @{ */ + +#define TRDC_MBC2_W3_RECR_MASK (0xC0000000U) +#define TRDC_MBC2_W3_RECR_SHIFT (30U) +/*! RECR - Rearm Error Capture Registers */ +#define TRDC_MBC2_W3_RECR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_W3_RECR_SHIFT)) & TRDC_MBC2_W3_RECR_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_W3 */ +#define TRDC_MBC2_MRC_DERR_W3_COUNT (2U) + +/*! @name MDA_W_DFMT1 - DAC Master Domain Assignment Register */ +/*! @{ */ + +#define TRDC_MBC2_MDA_W_DFMT1_DID_MASK (0xFU) +#define TRDC_MBC2_MDA_W_DFMT1_DID_SHIFT (0U) +/*! DID - Domain identifier */ +#define TRDC_MBC2_MDA_W_DFMT1_DID(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MDA_W_DFMT1_DID_SHIFT)) & TRDC_MBC2_MDA_W_DFMT1_DID_MASK) + +#define TRDC_MBC2_MDA_W_DFMT1_PA_MASK (0x30U) +#define TRDC_MBC2_MDA_W_DFMT1_PA_SHIFT (4U) +/*! PA - Privileged attribute + * 0b00..Force the bus attribute for this master to user. + * 0b01..Force the bus attribute for this master to privileged. + * 0b10..Use the bus master's privileged/user attribute directly. + * 0b11..Use the bus master's privileged/user attribute directly. + */ +#define TRDC_MBC2_MDA_W_DFMT1_PA(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MDA_W_DFMT1_PA_SHIFT)) & TRDC_MBC2_MDA_W_DFMT1_PA_MASK) + +#define TRDC_MBC2_MDA_W_DFMT1_SA_MASK (0xC0U) +#define TRDC_MBC2_MDA_W_DFMT1_SA_SHIFT (6U) +/*! SA - Secure attribute + * 0b00..Force the bus attribute for this master to secure. + * 0b01..Force the bus attribute for this master to nonsecure. + * 0b10..Use the bus master's secure/nonsecure attribute directly. + * 0b11..Use the bus master's secure/nonsecure attribute directly. + */ +#define TRDC_MBC2_MDA_W_DFMT1_SA(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MDA_W_DFMT1_SA_SHIFT)) & TRDC_MBC2_MDA_W_DFMT1_SA_MASK) + +#define TRDC_MBC2_MDA_W_DFMT1_DIDB_MASK (0x100U) +#define TRDC_MBC2_MDA_W_DFMT1_DIDB_SHIFT (8U) +/*! DIDB - DID Bypass + * 0b0..Use MDAn[3:0] as the domain identifier. + * 0b1..Use the DID input as the domain identifier. + */ +#define TRDC_MBC2_MDA_W_DFMT1_DIDB(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MDA_W_DFMT1_DIDB_SHIFT)) & TRDC_MBC2_MDA_W_DFMT1_DIDB_MASK) + +#define TRDC_MBC2_MDA_W_DFMT1_DFMT_MASK (0x20000000U) +#define TRDC_MBC2_MDA_W_DFMT1_DFMT_SHIFT (29U) +/*! DFMT - Domain format + * 0b0..Processor-core domain assignment + * 0b1..Non-processor domain assignment + */ +#define TRDC_MBC2_MDA_W_DFMT1_DFMT(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MDA_W_DFMT1_DFMT_SHIFT)) & TRDC_MBC2_MDA_W_DFMT1_DFMT_MASK) + +#define TRDC_MBC2_MDA_W_DFMT1_LK1_MASK (0x40000000U) +#define TRDC_MBC2_MDA_W_DFMT1_LK1_SHIFT (30U) +/*! LK1 - 1-bit Lock + * 0b0..Register can be written by any secure privileged write. + * 0b1..Register is locked (read-only) until the next reset. + */ +#define TRDC_MBC2_MDA_W_DFMT1_LK1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MDA_W_DFMT1_LK1_SHIFT)) & TRDC_MBC2_MDA_W_DFMT1_LK1_MASK) + +#define TRDC_MBC2_MDA_W_DFMT1_VLD_MASK (0x80000000U) +#define TRDC_MBC2_MDA_W_DFMT1_VLD_SHIFT (31U) +/*! VLD - Valid + * 0b0..The Wr domain assignment is invalid. + * 0b1..The Wr domain assignment is valid. + */ +#define TRDC_MBC2_MDA_W_DFMT1_VLD(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MDA_W_DFMT1_VLD_SHIFT)) & TRDC_MBC2_MDA_W_DFMT1_VLD_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MDA_W_DFMT1 */ +#define TRDC_MBC2_MDA_W_DFMT1_COUNT (5U) + +/* The count of TRDC_MBC2_MDA_W_DFMT1 */ +#define TRDC_MBC2_MDA_W_DFMT1_COUNT2 (1U) + +/*! @name MBC_MEM_GLBCFG - MBC Global Configuration Register */ +/*! @{ */ + +#define TRDC_MBC2_MBC_MEM_GLBCFG_NBLKS_MASK (0x3FFU) +#define TRDC_MBC2_MBC_MEM_GLBCFG_NBLKS_SHIFT (0U) +/*! NBLKS - Number of blocks in this memory */ +#define TRDC_MBC2_MBC_MEM_GLBCFG_NBLKS(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_MEM_GLBCFG_NBLKS_SHIFT)) & TRDC_MBC2_MBC_MEM_GLBCFG_NBLKS_MASK) + +#define TRDC_MBC2_MBC_MEM_GLBCFG_SIZE_LOG2_MASK (0x1F0000U) +#define TRDC_MBC2_MBC_MEM_GLBCFG_SIZE_LOG2_SHIFT (16U) +/*! SIZE_LOG2 - Log2 size per block */ +#define TRDC_MBC2_MBC_MEM_GLBCFG_SIZE_LOG2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_MEM_GLBCFG_SIZE_LOG2_SHIFT)) & TRDC_MBC2_MBC_MEM_GLBCFG_SIZE_LOG2_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MBC_MEM_GLBCFG */ +#define TRDC_MBC2_MBC_MEM_GLBCFG_COUNT (2U) + +/* The count of TRDC_MBC2_MBC_MEM_GLBCFG */ +#define TRDC_MBC2_MBC_MEM_GLBCFG_COUNT2 (4U) + +/*! @name MBC_NSE_BLK_INDEX - MBC NonSecure Enable Block Index */ +/*! @{ */ + +#define TRDC_MBC2_MBC_NSE_BLK_INDEX_AI_MASK (0x1U) +#define TRDC_MBC2_MBC_NSE_BLK_INDEX_AI_SHIFT (0U) +/*! AI - Auto Increment + * 0b0..No effect. + * 0b1..Add 1 to the WNDX field after the register write. + */ +#define TRDC_MBC2_MBC_NSE_BLK_INDEX_AI(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_NSE_BLK_INDEX_AI_SHIFT)) & TRDC_MBC2_MBC_NSE_BLK_INDEX_AI_MASK) + +#define TRDC_MBC2_MBC_NSE_BLK_INDEX_WNDX_MASK (0x3CU) +#define TRDC_MBC2_MBC_NSE_BLK_INDEX_WNDX_SHIFT (2U) +/*! WNDX - Word index into the block NSE bitmap. It selects the BLK_NSE_Wn register, where WNDX determines the value of n. */ +#define TRDC_MBC2_MBC_NSE_BLK_INDEX_WNDX(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_NSE_BLK_INDEX_WNDX_SHIFT)) & TRDC_MBC2_MBC_NSE_BLK_INDEX_WNDX_MASK) + +#define TRDC_MBC2_MBC_NSE_BLK_INDEX_MEM_SEL_MASK (0xF00U) +#define TRDC_MBC2_MBC_NSE_BLK_INDEX_MEM_SEL_SHIFT (8U) +/*! MEM_SEL - Memory Select */ +#define TRDC_MBC2_MBC_NSE_BLK_INDEX_MEM_SEL(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_NSE_BLK_INDEX_MEM_SEL_SHIFT)) & TRDC_MBC2_MBC_NSE_BLK_INDEX_MEM_SEL_MASK) + +#define TRDC_MBC2_MBC_NSE_BLK_INDEX_DID_SEL0_MASK (0x10000U) +#define TRDC_MBC2_MBC_NSE_BLK_INDEX_DID_SEL0_SHIFT (16U) +/*! DID_SEL0 - DID Select + * 0b0..No effect. + * 0b1..Selects NSE bits for this domain. + */ +#define TRDC_MBC2_MBC_NSE_BLK_INDEX_DID_SEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_NSE_BLK_INDEX_DID_SEL0_SHIFT)) & TRDC_MBC2_MBC_NSE_BLK_INDEX_DID_SEL0_MASK) + +#define TRDC_MBC2_MBC_NSE_BLK_INDEX_DID_SEL1_MASK (0x20000U) +#define TRDC_MBC2_MBC_NSE_BLK_INDEX_DID_SEL1_SHIFT (17U) +/*! DID_SEL1 - DID Select + * 0b0..No effect. + * 0b1..Selects NSE bits for this domain. + */ +#define TRDC_MBC2_MBC_NSE_BLK_INDEX_DID_SEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_NSE_BLK_INDEX_DID_SEL1_SHIFT)) & TRDC_MBC2_MBC_NSE_BLK_INDEX_DID_SEL1_MASK) + +#define TRDC_MBC2_MBC_NSE_BLK_INDEX_DID_SEL2_MASK (0x40000U) +#define TRDC_MBC2_MBC_NSE_BLK_INDEX_DID_SEL2_SHIFT (18U) +/*! DID_SEL2 - DID Select + * 0b0..No effect. + * 0b1..Selects NSE bits for this domain. + */ +#define TRDC_MBC2_MBC_NSE_BLK_INDEX_DID_SEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_NSE_BLK_INDEX_DID_SEL2_SHIFT)) & TRDC_MBC2_MBC_NSE_BLK_INDEX_DID_SEL2_MASK) + +#define TRDC_MBC2_MBC_NSE_BLK_INDEX_DID_SEL3_MASK (0x80000U) +#define TRDC_MBC2_MBC_NSE_BLK_INDEX_DID_SEL3_SHIFT (19U) +/*! DID_SEL3 - DID Select + * 0b0..No effect. + * 0b1..Selects NSE bits for this domain. + */ +#define TRDC_MBC2_MBC_NSE_BLK_INDEX_DID_SEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_NSE_BLK_INDEX_DID_SEL3_SHIFT)) & TRDC_MBC2_MBC_NSE_BLK_INDEX_DID_SEL3_MASK) + +#define TRDC_MBC2_MBC_NSE_BLK_INDEX_DID_SEL4_MASK (0x100000U) +#define TRDC_MBC2_MBC_NSE_BLK_INDEX_DID_SEL4_SHIFT (20U) +/*! DID_SEL4 - DID Select + * 0b0..No effect. + * 0b1..Selects NSE bits for this domain. + */ +#define TRDC_MBC2_MBC_NSE_BLK_INDEX_DID_SEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_NSE_BLK_INDEX_DID_SEL4_SHIFT)) & TRDC_MBC2_MBC_NSE_BLK_INDEX_DID_SEL4_MASK) + +#define TRDC_MBC2_MBC_NSE_BLK_INDEX_DID_SEL5_MASK (0x200000U) +#define TRDC_MBC2_MBC_NSE_BLK_INDEX_DID_SEL5_SHIFT (21U) +/*! DID_SEL5 - DID Select + * 0b0..No effect. + * 0b1..Selects NSE bits for this domain. + */ +#define TRDC_MBC2_MBC_NSE_BLK_INDEX_DID_SEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_NSE_BLK_INDEX_DID_SEL5_SHIFT)) & TRDC_MBC2_MBC_NSE_BLK_INDEX_DID_SEL5_MASK) + +#define TRDC_MBC2_MBC_NSE_BLK_INDEX_DID_SEL6_MASK (0x400000U) +#define TRDC_MBC2_MBC_NSE_BLK_INDEX_DID_SEL6_SHIFT (22U) +/*! DID_SEL6 - DID Select + * 0b0..No effect. + * 0b1..Selects NSE bits for this domain. + */ +#define TRDC_MBC2_MBC_NSE_BLK_INDEX_DID_SEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_NSE_BLK_INDEX_DID_SEL6_SHIFT)) & TRDC_MBC2_MBC_NSE_BLK_INDEX_DID_SEL6_MASK) + +#define TRDC_MBC2_MBC_NSE_BLK_INDEX_DID_SEL7_MASK (0x800000U) +#define TRDC_MBC2_MBC_NSE_BLK_INDEX_DID_SEL7_SHIFT (23U) +/*! DID_SEL7 - DID Select + * 0b0..No effect. + * 0b1..Selects NSE bits for this domain. + */ +#define TRDC_MBC2_MBC_NSE_BLK_INDEX_DID_SEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_NSE_BLK_INDEX_DID_SEL7_SHIFT)) & TRDC_MBC2_MBC_NSE_BLK_INDEX_DID_SEL7_MASK) + +#define TRDC_MBC2_MBC_NSE_BLK_INDEX_DID_SEL8_MASK (0x1000000U) +#define TRDC_MBC2_MBC_NSE_BLK_INDEX_DID_SEL8_SHIFT (24U) +/*! DID_SEL8 - DID Select + * 0b0..No effect. + * 0b1..Selects NSE bits for this domain. + */ +#define TRDC_MBC2_MBC_NSE_BLK_INDEX_DID_SEL8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_NSE_BLK_INDEX_DID_SEL8_SHIFT)) & TRDC_MBC2_MBC_NSE_BLK_INDEX_DID_SEL8_MASK) + +#define TRDC_MBC2_MBC_NSE_BLK_INDEX_DID_SEL9_MASK (0x2000000U) +#define TRDC_MBC2_MBC_NSE_BLK_INDEX_DID_SEL9_SHIFT (25U) +/*! DID_SEL9 - DID Select + * 0b0..No effect. + * 0b1..Selects NSE bits for this domain. + */ +#define TRDC_MBC2_MBC_NSE_BLK_INDEX_DID_SEL9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_NSE_BLK_INDEX_DID_SEL9_SHIFT)) & TRDC_MBC2_MBC_NSE_BLK_INDEX_DID_SEL9_MASK) + +#define TRDC_MBC2_MBC_NSE_BLK_INDEX_DID_SEL10_MASK (0x4000000U) +#define TRDC_MBC2_MBC_NSE_BLK_INDEX_DID_SEL10_SHIFT (26U) +/*! DID_SEL10 - DID Select + * 0b0..No effect. + * 0b1..Selects NSE bits for this domain. + */ +#define TRDC_MBC2_MBC_NSE_BLK_INDEX_DID_SEL10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_NSE_BLK_INDEX_DID_SEL10_SHIFT)) & TRDC_MBC2_MBC_NSE_BLK_INDEX_DID_SEL10_MASK) + +#define TRDC_MBC2_MBC_NSE_BLK_INDEX_DID_SEL11_MASK (0x8000000U) +#define TRDC_MBC2_MBC_NSE_BLK_INDEX_DID_SEL11_SHIFT (27U) +/*! DID_SEL11 - DID Select + * 0b0..No effect. + * 0b1..Selects NSE bits for this domain. + */ +#define TRDC_MBC2_MBC_NSE_BLK_INDEX_DID_SEL11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_NSE_BLK_INDEX_DID_SEL11_SHIFT)) & TRDC_MBC2_MBC_NSE_BLK_INDEX_DID_SEL11_MASK) + +#define TRDC_MBC2_MBC_NSE_BLK_INDEX_DID_SEL12_MASK (0x10000000U) +#define TRDC_MBC2_MBC_NSE_BLK_INDEX_DID_SEL12_SHIFT (28U) +/*! DID_SEL12 - DID Select + * 0b0..No effect. + * 0b1..Selects NSE bits for this domain. + */ +#define TRDC_MBC2_MBC_NSE_BLK_INDEX_DID_SEL12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_NSE_BLK_INDEX_DID_SEL12_SHIFT)) & TRDC_MBC2_MBC_NSE_BLK_INDEX_DID_SEL12_MASK) + +#define TRDC_MBC2_MBC_NSE_BLK_INDEX_DID_SEL13_MASK (0x20000000U) +#define TRDC_MBC2_MBC_NSE_BLK_INDEX_DID_SEL13_SHIFT (29U) +/*! DID_SEL13 - DID Select + * 0b0..No effect. + * 0b1..Selects NSE bits for this domain. + */ +#define TRDC_MBC2_MBC_NSE_BLK_INDEX_DID_SEL13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_NSE_BLK_INDEX_DID_SEL13_SHIFT)) & TRDC_MBC2_MBC_NSE_BLK_INDEX_DID_SEL13_MASK) + +#define TRDC_MBC2_MBC_NSE_BLK_INDEX_DID_SEL14_MASK (0x40000000U) +#define TRDC_MBC2_MBC_NSE_BLK_INDEX_DID_SEL14_SHIFT (30U) +/*! DID_SEL14 - DID Select + * 0b0..No effect. + * 0b1..Selects NSE bits for this domain. + */ +#define TRDC_MBC2_MBC_NSE_BLK_INDEX_DID_SEL14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_NSE_BLK_INDEX_DID_SEL14_SHIFT)) & TRDC_MBC2_MBC_NSE_BLK_INDEX_DID_SEL14_MASK) + +#define TRDC_MBC2_MBC_NSE_BLK_INDEX_DID_SEL15_MASK (0x80000000U) +#define TRDC_MBC2_MBC_NSE_BLK_INDEX_DID_SEL15_SHIFT (31U) +/*! DID_SEL15 - DID Select + * 0b0..No effect. + * 0b1..Selects NSE bits for this domain. + */ +#define TRDC_MBC2_MBC_NSE_BLK_INDEX_DID_SEL15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_NSE_BLK_INDEX_DID_SEL15_SHIFT)) & TRDC_MBC2_MBC_NSE_BLK_INDEX_DID_SEL15_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MBC_NSE_BLK_INDEX */ +#define TRDC_MBC2_MBC_NSE_BLK_INDEX_COUNT (2U) + +/*! @name MBC_NSE_BLK_SET - MBC NonSecure Enable Block Set */ +/*! @{ */ + +#define TRDC_MBC2_MBC_NSE_BLK_SET_W1SET_MASK (0xFFFFFFFFU) +#define TRDC_MBC2_MBC_NSE_BLK_SET_W1SET_SHIFT (0U) +/*! W1SET - Write-1 Set */ +#define TRDC_MBC2_MBC_NSE_BLK_SET_W1SET(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_NSE_BLK_SET_W1SET_SHIFT)) & TRDC_MBC2_MBC_NSE_BLK_SET_W1SET_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MBC_NSE_BLK_SET */ +#define TRDC_MBC2_MBC_NSE_BLK_SET_COUNT (2U) + +/*! @name MBC_NSE_BLK_CLR - MBC NonSecure Enable Block Clear */ +/*! @{ */ + +#define TRDC_MBC2_MBC_NSE_BLK_CLR_W1CLR_MASK (0xFFFFFFFFU) +#define TRDC_MBC2_MBC_NSE_BLK_CLR_W1CLR_SHIFT (0U) +/*! W1CLR - Write-1 Clear */ +#define TRDC_MBC2_MBC_NSE_BLK_CLR_W1CLR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_NSE_BLK_CLR_W1CLR_SHIFT)) & TRDC_MBC2_MBC_NSE_BLK_CLR_W1CLR_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MBC_NSE_BLK_CLR */ +#define TRDC_MBC2_MBC_NSE_BLK_CLR_COUNT (2U) + +/*! @name MBC_NSE_BLK_CLR_ALL - MBC NonSecure Enable Block Clear All */ +/*! @{ */ + +#define TRDC_MBC2_MBC_NSE_BLK_CLR_ALL_MEMSEL_MASK (0xF00U) +#define TRDC_MBC2_MBC_NSE_BLK_CLR_ALL_MEMSEL_SHIFT (8U) +/*! MEMSEL - Memory Select */ +#define TRDC_MBC2_MBC_NSE_BLK_CLR_ALL_MEMSEL(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_NSE_BLK_CLR_ALL_MEMSEL_SHIFT)) & TRDC_MBC2_MBC_NSE_BLK_CLR_ALL_MEMSEL_MASK) + +#define TRDC_MBC2_MBC_NSE_BLK_CLR_ALL_DID_SEL0_MASK (0x10000U) +#define TRDC_MBC2_MBC_NSE_BLK_CLR_ALL_DID_SEL0_SHIFT (16U) +/*! DID_SEL0 - DID Select + * 0b0..No effect. + * 0b1..Clear all NSE bits for this domain. + */ +#define TRDC_MBC2_MBC_NSE_BLK_CLR_ALL_DID_SEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_NSE_BLK_CLR_ALL_DID_SEL0_SHIFT)) & TRDC_MBC2_MBC_NSE_BLK_CLR_ALL_DID_SEL0_MASK) + +#define TRDC_MBC2_MBC_NSE_BLK_CLR_ALL_DID_SEL1_MASK (0x20000U) +#define TRDC_MBC2_MBC_NSE_BLK_CLR_ALL_DID_SEL1_SHIFT (17U) +/*! DID_SEL1 - DID Select + * 0b0..No effect. + * 0b1..Clear all NSE bits for this domain. + */ +#define TRDC_MBC2_MBC_NSE_BLK_CLR_ALL_DID_SEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_NSE_BLK_CLR_ALL_DID_SEL1_SHIFT)) & TRDC_MBC2_MBC_NSE_BLK_CLR_ALL_DID_SEL1_MASK) + +#define TRDC_MBC2_MBC_NSE_BLK_CLR_ALL_DID_SEL2_MASK (0x40000U) +#define TRDC_MBC2_MBC_NSE_BLK_CLR_ALL_DID_SEL2_SHIFT (18U) +/*! DID_SEL2 - DID Select + * 0b0..No effect. + * 0b1..Clear all NSE bits for this domain. + */ +#define TRDC_MBC2_MBC_NSE_BLK_CLR_ALL_DID_SEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_NSE_BLK_CLR_ALL_DID_SEL2_SHIFT)) & TRDC_MBC2_MBC_NSE_BLK_CLR_ALL_DID_SEL2_MASK) + +#define TRDC_MBC2_MBC_NSE_BLK_CLR_ALL_DID_SEL3_MASK (0x80000U) +#define TRDC_MBC2_MBC_NSE_BLK_CLR_ALL_DID_SEL3_SHIFT (19U) +/*! DID_SEL3 - DID Select + * 0b0..No effect. + * 0b1..Clear all NSE bits for this domain. + */ +#define TRDC_MBC2_MBC_NSE_BLK_CLR_ALL_DID_SEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_NSE_BLK_CLR_ALL_DID_SEL3_SHIFT)) & TRDC_MBC2_MBC_NSE_BLK_CLR_ALL_DID_SEL3_MASK) + +#define TRDC_MBC2_MBC_NSE_BLK_CLR_ALL_DID_SEL4_MASK (0x100000U) +#define TRDC_MBC2_MBC_NSE_BLK_CLR_ALL_DID_SEL4_SHIFT (20U) +/*! DID_SEL4 - DID Select + * 0b0..No effect. + * 0b1..Clear all NSE bits for this domain. + */ +#define TRDC_MBC2_MBC_NSE_BLK_CLR_ALL_DID_SEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_NSE_BLK_CLR_ALL_DID_SEL4_SHIFT)) & TRDC_MBC2_MBC_NSE_BLK_CLR_ALL_DID_SEL4_MASK) + +#define TRDC_MBC2_MBC_NSE_BLK_CLR_ALL_DID_SEL5_MASK (0x200000U) +#define TRDC_MBC2_MBC_NSE_BLK_CLR_ALL_DID_SEL5_SHIFT (21U) +/*! DID_SEL5 - DID Select + * 0b0..No effect. + * 0b1..Clear all NSE bits for this domain. + */ +#define TRDC_MBC2_MBC_NSE_BLK_CLR_ALL_DID_SEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_NSE_BLK_CLR_ALL_DID_SEL5_SHIFT)) & TRDC_MBC2_MBC_NSE_BLK_CLR_ALL_DID_SEL5_MASK) + +#define TRDC_MBC2_MBC_NSE_BLK_CLR_ALL_DID_SEL6_MASK (0x400000U) +#define TRDC_MBC2_MBC_NSE_BLK_CLR_ALL_DID_SEL6_SHIFT (22U) +/*! DID_SEL6 - DID Select + * 0b0..No effect. + * 0b1..Clear all NSE bits for this domain. + */ +#define TRDC_MBC2_MBC_NSE_BLK_CLR_ALL_DID_SEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_NSE_BLK_CLR_ALL_DID_SEL6_SHIFT)) & TRDC_MBC2_MBC_NSE_BLK_CLR_ALL_DID_SEL6_MASK) + +#define TRDC_MBC2_MBC_NSE_BLK_CLR_ALL_DID_SEL7_MASK (0x800000U) +#define TRDC_MBC2_MBC_NSE_BLK_CLR_ALL_DID_SEL7_SHIFT (23U) +/*! DID_SEL7 - DID Select + * 0b0..No effect. + * 0b1..Clear all NSE bits for this domain. + */ +#define TRDC_MBC2_MBC_NSE_BLK_CLR_ALL_DID_SEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_NSE_BLK_CLR_ALL_DID_SEL7_SHIFT)) & TRDC_MBC2_MBC_NSE_BLK_CLR_ALL_DID_SEL7_MASK) + +#define TRDC_MBC2_MBC_NSE_BLK_CLR_ALL_DID_SEL8_MASK (0x1000000U) +#define TRDC_MBC2_MBC_NSE_BLK_CLR_ALL_DID_SEL8_SHIFT (24U) +/*! DID_SEL8 - DID Select + * 0b0..No effect. + * 0b1..Clear all NSE bits for this domain. + */ +#define TRDC_MBC2_MBC_NSE_BLK_CLR_ALL_DID_SEL8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_NSE_BLK_CLR_ALL_DID_SEL8_SHIFT)) & TRDC_MBC2_MBC_NSE_BLK_CLR_ALL_DID_SEL8_MASK) + +#define TRDC_MBC2_MBC_NSE_BLK_CLR_ALL_DID_SEL9_MASK (0x2000000U) +#define TRDC_MBC2_MBC_NSE_BLK_CLR_ALL_DID_SEL9_SHIFT (25U) +/*! DID_SEL9 - DID Select + * 0b0..No effect. + * 0b1..Clear all NSE bits for this domain. + */ +#define TRDC_MBC2_MBC_NSE_BLK_CLR_ALL_DID_SEL9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_NSE_BLK_CLR_ALL_DID_SEL9_SHIFT)) & TRDC_MBC2_MBC_NSE_BLK_CLR_ALL_DID_SEL9_MASK) + +#define TRDC_MBC2_MBC_NSE_BLK_CLR_ALL_DID_SEL10_MASK (0x4000000U) +#define TRDC_MBC2_MBC_NSE_BLK_CLR_ALL_DID_SEL10_SHIFT (26U) +/*! DID_SEL10 - DID Select + * 0b0..No effect. + * 0b1..Clear all NSE bits for this domain. + */ +#define TRDC_MBC2_MBC_NSE_BLK_CLR_ALL_DID_SEL10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_NSE_BLK_CLR_ALL_DID_SEL10_SHIFT)) & TRDC_MBC2_MBC_NSE_BLK_CLR_ALL_DID_SEL10_MASK) + +#define TRDC_MBC2_MBC_NSE_BLK_CLR_ALL_DID_SEL11_MASK (0x8000000U) +#define TRDC_MBC2_MBC_NSE_BLK_CLR_ALL_DID_SEL11_SHIFT (27U) +/*! DID_SEL11 - DID Select + * 0b0..No effect. + * 0b1..Clear all NSE bits for this domain. + */ +#define TRDC_MBC2_MBC_NSE_BLK_CLR_ALL_DID_SEL11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_NSE_BLK_CLR_ALL_DID_SEL11_SHIFT)) & TRDC_MBC2_MBC_NSE_BLK_CLR_ALL_DID_SEL11_MASK) + +#define TRDC_MBC2_MBC_NSE_BLK_CLR_ALL_DID_SEL12_MASK (0x10000000U) +#define TRDC_MBC2_MBC_NSE_BLK_CLR_ALL_DID_SEL12_SHIFT (28U) +/*! DID_SEL12 - DID Select + * 0b0..No effect. + * 0b1..Clear all NSE bits for this domain. + */ +#define TRDC_MBC2_MBC_NSE_BLK_CLR_ALL_DID_SEL12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_NSE_BLK_CLR_ALL_DID_SEL12_SHIFT)) & TRDC_MBC2_MBC_NSE_BLK_CLR_ALL_DID_SEL12_MASK) + +#define TRDC_MBC2_MBC_NSE_BLK_CLR_ALL_DID_SEL13_MASK (0x20000000U) +#define TRDC_MBC2_MBC_NSE_BLK_CLR_ALL_DID_SEL13_SHIFT (29U) +/*! DID_SEL13 - DID Select + * 0b0..No effect. + * 0b1..Clear all NSE bits for this domain. + */ +#define TRDC_MBC2_MBC_NSE_BLK_CLR_ALL_DID_SEL13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_NSE_BLK_CLR_ALL_DID_SEL13_SHIFT)) & TRDC_MBC2_MBC_NSE_BLK_CLR_ALL_DID_SEL13_MASK) + +#define TRDC_MBC2_MBC_NSE_BLK_CLR_ALL_DID_SEL14_MASK (0x40000000U) +#define TRDC_MBC2_MBC_NSE_BLK_CLR_ALL_DID_SEL14_SHIFT (30U) +/*! DID_SEL14 - DID Select + * 0b0..No effect. + * 0b1..Clear all NSE bits for this domain. + */ +#define TRDC_MBC2_MBC_NSE_BLK_CLR_ALL_DID_SEL14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_NSE_BLK_CLR_ALL_DID_SEL14_SHIFT)) & TRDC_MBC2_MBC_NSE_BLK_CLR_ALL_DID_SEL14_MASK) + +#define TRDC_MBC2_MBC_NSE_BLK_CLR_ALL_DID_SEL15_MASK (0x80000000U) +#define TRDC_MBC2_MBC_NSE_BLK_CLR_ALL_DID_SEL15_SHIFT (31U) +/*! DID_SEL15 - DID Select + * 0b0..No effect. + * 0b1..Clear all NSE bits for this domain. + */ +#define TRDC_MBC2_MBC_NSE_BLK_CLR_ALL_DID_SEL15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_NSE_BLK_CLR_ALL_DID_SEL15_SHIFT)) & TRDC_MBC2_MBC_NSE_BLK_CLR_ALL_DID_SEL15_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MBC_NSE_BLK_CLR_ALL */ +#define TRDC_MBC2_MBC_NSE_BLK_CLR_ALL_COUNT (2U) + +/*! @name MBC_MEMN_GLBAC - MBC Global Access Control */ +/*! @{ */ + +#define TRDC_MBC2_MBC_MEMN_GLBAC_NUX_MASK (0x1U) +#define TRDC_MBC2_MBC_MEMN_GLBAC_NUX_SHIFT (0U) +/*! NUX - NonsecureUser Execute + * 0b0..Execute access is not allowed in Nonsecure User mode. + * 0b1..Execute access is allowed in Nonsecure User mode. + */ +#define TRDC_MBC2_MBC_MEMN_GLBAC_NUX(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_MEMN_GLBAC_NUX_SHIFT)) & TRDC_MBC2_MBC_MEMN_GLBAC_NUX_MASK) + +#define TRDC_MBC2_MBC_MEMN_GLBAC_NUW_MASK (0x2U) +#define TRDC_MBC2_MBC_MEMN_GLBAC_NUW_SHIFT (1U) +/*! NUW - NonsecureUser Write + * 0b0..Write access is not allowed in Nonsecure User mode. + * 0b1..Write access is allowed in Nonsecure User mode. + */ +#define TRDC_MBC2_MBC_MEMN_GLBAC_NUW(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_MEMN_GLBAC_NUW_SHIFT)) & TRDC_MBC2_MBC_MEMN_GLBAC_NUW_MASK) + +#define TRDC_MBC2_MBC_MEMN_GLBAC_NUR_MASK (0x4U) +#define TRDC_MBC2_MBC_MEMN_GLBAC_NUR_SHIFT (2U) +/*! NUR - NonsecureUser Read + * 0b0..Read access is not allowed in Nonsecure User mode. + * 0b1..Read access is allowed in Nonsecure User mode. + */ +#define TRDC_MBC2_MBC_MEMN_GLBAC_NUR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_MEMN_GLBAC_NUR_SHIFT)) & TRDC_MBC2_MBC_MEMN_GLBAC_NUR_MASK) + +#define TRDC_MBC2_MBC_MEMN_GLBAC_NPX_MASK (0x10U) +#define TRDC_MBC2_MBC_MEMN_GLBAC_NPX_SHIFT (4U) +/*! NPX - NonsecurePriv Execute + * 0b0..Execute access is not allowed in Nonsecure Privilege mode. + * 0b1..Execute access is allowed in Nonsecure Privilege mode. + */ +#define TRDC_MBC2_MBC_MEMN_GLBAC_NPX(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_MEMN_GLBAC_NPX_SHIFT)) & TRDC_MBC2_MBC_MEMN_GLBAC_NPX_MASK) + +#define TRDC_MBC2_MBC_MEMN_GLBAC_NPW_MASK (0x20U) +#define TRDC_MBC2_MBC_MEMN_GLBAC_NPW_SHIFT (5U) +/*! NPW - NonsecurePriv Write + * 0b0..Write access is not allowed in Nonsecure Privilege mode. + * 0b1..Write access is allowed in Nonsecure Privilege mode. + */ +#define TRDC_MBC2_MBC_MEMN_GLBAC_NPW(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_MEMN_GLBAC_NPW_SHIFT)) & TRDC_MBC2_MBC_MEMN_GLBAC_NPW_MASK) + +#define TRDC_MBC2_MBC_MEMN_GLBAC_NPR_MASK (0x40U) +#define TRDC_MBC2_MBC_MEMN_GLBAC_NPR_SHIFT (6U) +/*! NPR - NonsecurePriv Read + * 0b0..Read access is not allowed in Nonsecure Privilege mode. + * 0b1..Read access is allowed in Nonsecure Privilege mode. + */ +#define TRDC_MBC2_MBC_MEMN_GLBAC_NPR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_MEMN_GLBAC_NPR_SHIFT)) & TRDC_MBC2_MBC_MEMN_GLBAC_NPR_MASK) + +#define TRDC_MBC2_MBC_MEMN_GLBAC_SUX_MASK (0x100U) +#define TRDC_MBC2_MBC_MEMN_GLBAC_SUX_SHIFT (8U) +/*! SUX - SecureUser Execute + * 0b0..Execute access is not allowed in Secure User mode. + * 0b1..Execute access is allowed in Secure User mode. + */ +#define TRDC_MBC2_MBC_MEMN_GLBAC_SUX(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_MEMN_GLBAC_SUX_SHIFT)) & TRDC_MBC2_MBC_MEMN_GLBAC_SUX_MASK) + +#define TRDC_MBC2_MBC_MEMN_GLBAC_SUW_MASK (0x200U) +#define TRDC_MBC2_MBC_MEMN_GLBAC_SUW_SHIFT (9U) +/*! SUW - SecureUser Write + * 0b0..Write access is not allowed in Secure User mode. + * 0b1..Write access is allowed in Secure User mode. + */ +#define TRDC_MBC2_MBC_MEMN_GLBAC_SUW(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_MEMN_GLBAC_SUW_SHIFT)) & TRDC_MBC2_MBC_MEMN_GLBAC_SUW_MASK) + +#define TRDC_MBC2_MBC_MEMN_GLBAC_SUR_MASK (0x400U) +#define TRDC_MBC2_MBC_MEMN_GLBAC_SUR_SHIFT (10U) +/*! SUR - SecureUser Read + * 0b0..Read access is not allowed in Secure User mode. + * 0b1..Read access is allowed in Secure User mode. + */ +#define TRDC_MBC2_MBC_MEMN_GLBAC_SUR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_MEMN_GLBAC_SUR_SHIFT)) & TRDC_MBC2_MBC_MEMN_GLBAC_SUR_MASK) + +#define TRDC_MBC2_MBC_MEMN_GLBAC_SPX_MASK (0x1000U) +#define TRDC_MBC2_MBC_MEMN_GLBAC_SPX_SHIFT (12U) +/*! SPX - SecurePriv Execute + * 0b0..Execute access is not allowed in Secure Privilege mode. + * 0b1..Execute access is allowed in Secure Privilege mode. + */ +#define TRDC_MBC2_MBC_MEMN_GLBAC_SPX(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_MEMN_GLBAC_SPX_SHIFT)) & TRDC_MBC2_MBC_MEMN_GLBAC_SPX_MASK) + +#define TRDC_MBC2_MBC_MEMN_GLBAC_SPW_MASK (0x2000U) +#define TRDC_MBC2_MBC_MEMN_GLBAC_SPW_SHIFT (13U) +/*! SPW - SecurePriv Write + * 0b0..Write access is not allowed in Secure Privilege mode. + * 0b1..Write access is allowed in Secure Privilege mode. + */ +#define TRDC_MBC2_MBC_MEMN_GLBAC_SPW(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_MEMN_GLBAC_SPW_SHIFT)) & TRDC_MBC2_MBC_MEMN_GLBAC_SPW_MASK) + +#define TRDC_MBC2_MBC_MEMN_GLBAC_SPR_MASK (0x4000U) +#define TRDC_MBC2_MBC_MEMN_GLBAC_SPR_SHIFT (14U) +/*! SPR - SecurePriv Read + * 0b0..Read access is not allowed in Secure Privilege mode. + * 0b1..Read access is allowed in Secure Privilege mode. + */ +#define TRDC_MBC2_MBC_MEMN_GLBAC_SPR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_MEMN_GLBAC_SPR_SHIFT)) & TRDC_MBC2_MBC_MEMN_GLBAC_SPR_MASK) + +#define TRDC_MBC2_MBC_MEMN_GLBAC_LK_MASK (0x80000000U) +#define TRDC_MBC2_MBC_MEMN_GLBAC_LK_SHIFT (31U) +/*! LK - LOCK + * 0b0..This register is not locked and can be altered. + * 0b1..This register is locked and cannot be altered. + */ +#define TRDC_MBC2_MBC_MEMN_GLBAC_LK(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_MEMN_GLBAC_LK_SHIFT)) & TRDC_MBC2_MBC_MEMN_GLBAC_LK_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MBC_MEMN_GLBAC */ +#define TRDC_MBC2_MBC_MEMN_GLBAC_COUNT (2U) + +/* The count of TRDC_MBC2_MBC_MEMN_GLBAC */ +#define TRDC_MBC2_MBC_MEMN_GLBAC_COUNT2 (8U) + +/*! @name MBC_DOM0_MEM0_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM0_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM0_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM0_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM0_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM0_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM0_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM0_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM0_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM0_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM0_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM0_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM0_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM0_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM0_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM0_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM0_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MBC_DOM0_MEM0_BLK_CFG_W */ +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_CFG_W_COUNT (2U) + +/* The count of TRDC_MBC2_MBC_DOM0_MEM0_BLK_CFG_W */ +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_CFG_W_COUNT2 (16U) + +/*! @name MBC_DOM0_MEM0_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ +/*! @{ */ + +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT0_MASK (0x1U) +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT0_SHIFT (0U) +/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT0_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT1_MASK (0x2U) +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT1_SHIFT (1U) +/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT1_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT2_MASK (0x4U) +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT2_SHIFT (2U) +/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT2_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT3_MASK (0x8U) +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT3_SHIFT (3U) +/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT3_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT4_MASK (0x10U) +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT4_SHIFT (4U) +/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT4_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT5_MASK (0x20U) +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT5_SHIFT (5U) +/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT5_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT6_MASK (0x40U) +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT6_SHIFT (6U) +/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT6_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT7_MASK (0x80U) +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT7_SHIFT (7U) +/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT7_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT8_MASK (0x100U) +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT8_SHIFT (8U) +/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT8_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT9_MASK (0x200U) +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT9_SHIFT (9U) +/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT9_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT10_MASK (0x400U) +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT10_SHIFT (10U) +/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT10_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT11_MASK (0x800U) +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT11_SHIFT (11U) +/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT11_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT12_MASK (0x1000U) +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT12_SHIFT (12U) +/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT12_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT13_MASK (0x2000U) +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT13_SHIFT (13U) +/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT13_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT14_MASK (0x4000U) +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT14_SHIFT (14U) +/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT14_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT15_MASK (0x8000U) +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT15_SHIFT (15U) +/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT15_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT16_MASK (0x10000U) +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT16_SHIFT (16U) +/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT16_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT17_MASK (0x20000U) +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT17_SHIFT (17U) +/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT17_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT18_MASK (0x40000U) +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT18_SHIFT (18U) +/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT18_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT19_MASK (0x80000U) +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT19_SHIFT (19U) +/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT19_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT20_MASK (0x100000U) +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT20_SHIFT (20U) +/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT20_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT21_MASK (0x200000U) +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT21_SHIFT (21U) +/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT21_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT22_MASK (0x400000U) +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT22_SHIFT (22U) +/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT22_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT23_MASK (0x800000U) +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT23_SHIFT (23U) +/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT23_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT24_MASK (0x1000000U) +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT24_SHIFT (24U) +/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT24_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT25_MASK (0x2000000U) +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT25_SHIFT (25U) +/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT25_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT26_MASK (0x4000000U) +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT26_SHIFT (26U) +/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT26_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT27_MASK (0x8000000U) +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT27_SHIFT (27U) +/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT27_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT28_MASK (0x10000000U) +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT28_SHIFT (28U) +/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT28_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT29_MASK (0x20000000U) +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT29_SHIFT (29U) +/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT29_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT30_MASK (0x40000000U) +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT30_SHIFT (30U) +/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT30_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT31_MASK (0x80000000U) +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT31_SHIFT (31U) +/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_BIT31_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W */ +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_COUNT (2U) + +/* The count of TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W */ +#define TRDC_MBC2_MBC_DOM0_MEM0_BLK_NSE_W_COUNT2 (4U) + +/*! @name MBC_DOM0_MEM1_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM1_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM1_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM1_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM1_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM1_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM1_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM1_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM1_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM1_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM1_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM1_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM1_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM1_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM1_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM1_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM1_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MBC_DOM0_MEM1_BLK_CFG_W */ +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_CFG_W_COUNT (2U) + +/* The count of TRDC_MBC2_MBC_DOM0_MEM1_BLK_CFG_W */ +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_CFG_W_COUNT2 (1U) + +/*! @name MBC_DOM0_MEM1_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ +/*! @{ */ + +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT0_MASK (0x1U) +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT0_SHIFT (0U) +/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT0_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT1_MASK (0x2U) +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT1_SHIFT (1U) +/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT1_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT2_MASK (0x4U) +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT2_SHIFT (2U) +/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT2_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT3_MASK (0x8U) +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT3_SHIFT (3U) +/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT3_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT4_MASK (0x10U) +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT4_SHIFT (4U) +/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT4_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT5_MASK (0x20U) +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT5_SHIFT (5U) +/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT5_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT6_MASK (0x40U) +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT6_SHIFT (6U) +/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT6_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT7_MASK (0x80U) +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT7_SHIFT (7U) +/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT7_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT8_MASK (0x100U) +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT8_SHIFT (8U) +/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT8_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT9_MASK (0x200U) +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT9_SHIFT (9U) +/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT9_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT10_MASK (0x400U) +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT10_SHIFT (10U) +/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT10_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT11_MASK (0x800U) +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT11_SHIFT (11U) +/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT11_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT12_MASK (0x1000U) +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT12_SHIFT (12U) +/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT12_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT13_MASK (0x2000U) +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT13_SHIFT (13U) +/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT13_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT14_MASK (0x4000U) +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT14_SHIFT (14U) +/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT14_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT15_MASK (0x8000U) +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT15_SHIFT (15U) +/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT15_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT16_MASK (0x10000U) +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT16_SHIFT (16U) +/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT16_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT17_MASK (0x20000U) +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT17_SHIFT (17U) +/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT17_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT18_MASK (0x40000U) +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT18_SHIFT (18U) +/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT18_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT19_MASK (0x80000U) +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT19_SHIFT (19U) +/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT19_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT20_MASK (0x100000U) +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT20_SHIFT (20U) +/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT20_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT21_MASK (0x200000U) +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT21_SHIFT (21U) +/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT21_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT22_MASK (0x400000U) +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT22_SHIFT (22U) +/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT22_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT23_MASK (0x800000U) +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT23_SHIFT (23U) +/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT23_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT24_MASK (0x1000000U) +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT24_SHIFT (24U) +/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT24_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT25_MASK (0x2000000U) +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT25_SHIFT (25U) +/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT25_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT26_MASK (0x4000000U) +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT26_SHIFT (26U) +/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT26_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT27_MASK (0x8000000U) +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT27_SHIFT (27U) +/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT27_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT28_MASK (0x10000000U) +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT28_SHIFT (28U) +/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT28_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT29_MASK (0x20000000U) +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT29_SHIFT (29U) +/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT29_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT30_MASK (0x40000000U) +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT30_SHIFT (30U) +/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT30_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT31_MASK (0x80000000U) +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT31_SHIFT (31U) +/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_BIT31_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W */ +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_COUNT (2U) + +/* The count of TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W */ +#define TRDC_MBC2_MBC_DOM0_MEM1_BLK_NSE_W_COUNT2 (1U) + +/*! @name MBC_DOM0_MEM2_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM2_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM2_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM2_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM2_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM2_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM2_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM2_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM2_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM2_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM2_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM2_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM2_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM2_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM2_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM2_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM2_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MBC_DOM0_MEM2_BLK_CFG_W */ +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_CFG_W_COUNT (2U) + +/* The count of TRDC_MBC2_MBC_DOM0_MEM2_BLK_CFG_W */ +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_CFG_W_COUNT2 (1U) + +/*! @name MBC_DOM0_MEM2_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ +/*! @{ */ + +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT0_MASK (0x1U) +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT0_SHIFT (0U) +/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT0_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT1_MASK (0x2U) +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT1_SHIFT (1U) +/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT1_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT2_MASK (0x4U) +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT2_SHIFT (2U) +/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT2_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT3_MASK (0x8U) +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT3_SHIFT (3U) +/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT3_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT4_MASK (0x10U) +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT4_SHIFT (4U) +/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT4_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT5_MASK (0x20U) +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT5_SHIFT (5U) +/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT5_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT6_MASK (0x40U) +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT6_SHIFT (6U) +/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT6_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT7_MASK (0x80U) +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT7_SHIFT (7U) +/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT7_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT8_MASK (0x100U) +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT8_SHIFT (8U) +/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT8_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT9_MASK (0x200U) +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT9_SHIFT (9U) +/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT9_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT10_MASK (0x400U) +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT10_SHIFT (10U) +/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT10_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT11_MASK (0x800U) +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT11_SHIFT (11U) +/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT11_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT12_MASK (0x1000U) +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT12_SHIFT (12U) +/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT12_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT13_MASK (0x2000U) +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT13_SHIFT (13U) +/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT13_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT14_MASK (0x4000U) +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT14_SHIFT (14U) +/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT14_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT15_MASK (0x8000U) +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT15_SHIFT (15U) +/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT15_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT16_MASK (0x10000U) +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT16_SHIFT (16U) +/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT16_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT17_MASK (0x20000U) +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT17_SHIFT (17U) +/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT17_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT18_MASK (0x40000U) +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT18_SHIFT (18U) +/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT18_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT19_MASK (0x80000U) +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT19_SHIFT (19U) +/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT19_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT20_MASK (0x100000U) +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT20_SHIFT (20U) +/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT20_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT21_MASK (0x200000U) +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT21_SHIFT (21U) +/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT21_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT22_MASK (0x400000U) +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT22_SHIFT (22U) +/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT22_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT23_MASK (0x800000U) +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT23_SHIFT (23U) +/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT23_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT24_MASK (0x1000000U) +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT24_SHIFT (24U) +/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT24_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT25_MASK (0x2000000U) +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT25_SHIFT (25U) +/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT25_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT26_MASK (0x4000000U) +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT26_SHIFT (26U) +/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT26_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT27_MASK (0x8000000U) +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT27_SHIFT (27U) +/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT27_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT28_MASK (0x10000000U) +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT28_SHIFT (28U) +/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT28_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT29_MASK (0x20000000U) +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT29_SHIFT (29U) +/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT29_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT30_MASK (0x40000000U) +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT30_SHIFT (30U) +/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT30_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT31_MASK (0x80000000U) +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT31_SHIFT (31U) +/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_BIT31_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W */ +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_COUNT (2U) + +/* The count of TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W */ +#define TRDC_MBC2_MBC_DOM0_MEM2_BLK_NSE_W_COUNT2 (1U) + +/*! @name MBC_DOM0_MEM3_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM3_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM3_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM3_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM3_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM3_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM3_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM3_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM3_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM3_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM3_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM3_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM3_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM3_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM3_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM3_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM3_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MBC_DOM0_MEM3_BLK_CFG_W */ +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_CFG_W_COUNT (2U) + +/* The count of TRDC_MBC2_MBC_DOM0_MEM3_BLK_CFG_W */ +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_CFG_W_COUNT2 (3U) + +/*! @name MBC_DOM0_MEM3_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ +/*! @{ */ + +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT0_MASK (0x1U) +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT0_SHIFT (0U) +/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT0_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT1_MASK (0x2U) +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT1_SHIFT (1U) +/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT1_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT2_MASK (0x4U) +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT2_SHIFT (2U) +/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT2_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT3_MASK (0x8U) +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT3_SHIFT (3U) +/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT3_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT4_MASK (0x10U) +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT4_SHIFT (4U) +/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT4_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT5_MASK (0x20U) +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT5_SHIFT (5U) +/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT5_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT6_MASK (0x40U) +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT6_SHIFT (6U) +/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT6_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT7_MASK (0x80U) +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT7_SHIFT (7U) +/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT7_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT8_MASK (0x100U) +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT8_SHIFT (8U) +/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT8_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT9_MASK (0x200U) +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT9_SHIFT (9U) +/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT9_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT10_MASK (0x400U) +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT10_SHIFT (10U) +/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT10_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT11_MASK (0x800U) +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT11_SHIFT (11U) +/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT11_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT12_MASK (0x1000U) +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT12_SHIFT (12U) +/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT12_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT13_MASK (0x2000U) +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT13_SHIFT (13U) +/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT13_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT14_MASK (0x4000U) +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT14_SHIFT (14U) +/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT14_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT15_MASK (0x8000U) +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT15_SHIFT (15U) +/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT15_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT16_MASK (0x10000U) +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT16_SHIFT (16U) +/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT16_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT17_MASK (0x20000U) +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT17_SHIFT (17U) +/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT17_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT18_MASK (0x40000U) +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT18_SHIFT (18U) +/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT18_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT19_MASK (0x80000U) +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT19_SHIFT (19U) +/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT19_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT20_MASK (0x100000U) +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT20_SHIFT (20U) +/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT20_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT21_MASK (0x200000U) +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT21_SHIFT (21U) +/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT21_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT22_MASK (0x400000U) +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT22_SHIFT (22U) +/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT22_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT23_MASK (0x800000U) +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT23_SHIFT (23U) +/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT23_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT24_MASK (0x1000000U) +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT24_SHIFT (24U) +/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT24_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT25_MASK (0x2000000U) +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT25_SHIFT (25U) +/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT25_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT26_MASK (0x4000000U) +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT26_SHIFT (26U) +/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT26_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT27_MASK (0x8000000U) +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT27_SHIFT (27U) +/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT27_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT28_MASK (0x10000000U) +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT28_SHIFT (28U) +/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT28_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT29_MASK (0x20000000U) +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT29_SHIFT (29U) +/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT29_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT30_MASK (0x40000000U) +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT30_SHIFT (30U) +/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT30_MASK) + +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT31_MASK (0x80000000U) +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT31_SHIFT (31U) +/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_BIT31_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W */ +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_COUNT (2U) + +/* The count of TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W */ +#define TRDC_MBC2_MBC_DOM0_MEM3_BLK_NSE_W_COUNT2 (1U) + +/*! @name MBC_DOM1_MEM0_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM0_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM0_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM0_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM0_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM0_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM0_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM0_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM0_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM0_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM0_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM0_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM0_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM0_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM0_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM0_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM0_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MBC_DOM1_MEM0_BLK_CFG_W */ +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_CFG_W_COUNT (2U) + +/* The count of TRDC_MBC2_MBC_DOM1_MEM0_BLK_CFG_W */ +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_CFG_W_COUNT2 (16U) + +/*! @name MBC_DOM1_MEM0_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ +/*! @{ */ + +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT0_MASK (0x1U) +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT0_SHIFT (0U) +/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT0_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT1_MASK (0x2U) +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT1_SHIFT (1U) +/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT1_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT2_MASK (0x4U) +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT2_SHIFT (2U) +/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT2_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT3_MASK (0x8U) +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT3_SHIFT (3U) +/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT3_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT4_MASK (0x10U) +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT4_SHIFT (4U) +/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT4_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT5_MASK (0x20U) +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT5_SHIFT (5U) +/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT5_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT6_MASK (0x40U) +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT6_SHIFT (6U) +/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT6_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT7_MASK (0x80U) +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT7_SHIFT (7U) +/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT7_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT8_MASK (0x100U) +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT8_SHIFT (8U) +/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT8_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT9_MASK (0x200U) +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT9_SHIFT (9U) +/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT9_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT10_MASK (0x400U) +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT10_SHIFT (10U) +/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT10_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT11_MASK (0x800U) +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT11_SHIFT (11U) +/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT11_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT12_MASK (0x1000U) +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT12_SHIFT (12U) +/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT12_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT13_MASK (0x2000U) +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT13_SHIFT (13U) +/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT13_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT14_MASK (0x4000U) +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT14_SHIFT (14U) +/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT14_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT15_MASK (0x8000U) +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT15_SHIFT (15U) +/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT15_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT16_MASK (0x10000U) +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT16_SHIFT (16U) +/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT16_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT17_MASK (0x20000U) +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT17_SHIFT (17U) +/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT17_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT18_MASK (0x40000U) +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT18_SHIFT (18U) +/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT18_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT19_MASK (0x80000U) +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT19_SHIFT (19U) +/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT19_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT20_MASK (0x100000U) +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT20_SHIFT (20U) +/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT20_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT21_MASK (0x200000U) +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT21_SHIFT (21U) +/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT21_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT22_MASK (0x400000U) +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT22_SHIFT (22U) +/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT22_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT23_MASK (0x800000U) +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT23_SHIFT (23U) +/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT23_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT24_MASK (0x1000000U) +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT24_SHIFT (24U) +/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT24_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT25_MASK (0x2000000U) +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT25_SHIFT (25U) +/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT25_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT26_MASK (0x4000000U) +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT26_SHIFT (26U) +/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT26_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT27_MASK (0x8000000U) +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT27_SHIFT (27U) +/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT27_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT28_MASK (0x10000000U) +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT28_SHIFT (28U) +/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT28_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT29_MASK (0x20000000U) +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT29_SHIFT (29U) +/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT29_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT30_MASK (0x40000000U) +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT30_SHIFT (30U) +/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT30_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT31_MASK (0x80000000U) +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT31_SHIFT (31U) +/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_BIT31_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W */ +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_COUNT (2U) + +/* The count of TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W */ +#define TRDC_MBC2_MBC_DOM1_MEM0_BLK_NSE_W_COUNT2 (4U) + +/*! @name MBC_DOM1_MEM1_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM1_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM1_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM1_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM1_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM1_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM1_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM1_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM1_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM1_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM1_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM1_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM1_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM1_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM1_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM1_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM1_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MBC_DOM1_MEM1_BLK_CFG_W */ +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_CFG_W_COUNT (2U) + +/* The count of TRDC_MBC2_MBC_DOM1_MEM1_BLK_CFG_W */ +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_CFG_W_COUNT2 (1U) + +/*! @name MBC_DOM1_MEM1_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ +/*! @{ */ + +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT0_MASK (0x1U) +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT0_SHIFT (0U) +/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT0_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT1_MASK (0x2U) +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT1_SHIFT (1U) +/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT1_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT2_MASK (0x4U) +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT2_SHIFT (2U) +/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT2_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT3_MASK (0x8U) +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT3_SHIFT (3U) +/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT3_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT4_MASK (0x10U) +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT4_SHIFT (4U) +/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT4_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT5_MASK (0x20U) +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT5_SHIFT (5U) +/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT5_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT6_MASK (0x40U) +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT6_SHIFT (6U) +/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT6_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT7_MASK (0x80U) +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT7_SHIFT (7U) +/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT7_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT8_MASK (0x100U) +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT8_SHIFT (8U) +/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT8_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT9_MASK (0x200U) +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT9_SHIFT (9U) +/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT9_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT10_MASK (0x400U) +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT10_SHIFT (10U) +/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT10_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT11_MASK (0x800U) +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT11_SHIFT (11U) +/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT11_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT12_MASK (0x1000U) +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT12_SHIFT (12U) +/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT12_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT13_MASK (0x2000U) +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT13_SHIFT (13U) +/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT13_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT14_MASK (0x4000U) +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT14_SHIFT (14U) +/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT14_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT15_MASK (0x8000U) +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT15_SHIFT (15U) +/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT15_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT16_MASK (0x10000U) +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT16_SHIFT (16U) +/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT16_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT17_MASK (0x20000U) +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT17_SHIFT (17U) +/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT17_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT18_MASK (0x40000U) +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT18_SHIFT (18U) +/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT18_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT19_MASK (0x80000U) +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT19_SHIFT (19U) +/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT19_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT20_MASK (0x100000U) +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT20_SHIFT (20U) +/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT20_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT21_MASK (0x200000U) +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT21_SHIFT (21U) +/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT21_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT22_MASK (0x400000U) +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT22_SHIFT (22U) +/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT22_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT23_MASK (0x800000U) +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT23_SHIFT (23U) +/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT23_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT24_MASK (0x1000000U) +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT24_SHIFT (24U) +/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT24_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT25_MASK (0x2000000U) +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT25_SHIFT (25U) +/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT25_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT26_MASK (0x4000000U) +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT26_SHIFT (26U) +/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT26_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT27_MASK (0x8000000U) +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT27_SHIFT (27U) +/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT27_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT28_MASK (0x10000000U) +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT28_SHIFT (28U) +/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT28_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT29_MASK (0x20000000U) +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT29_SHIFT (29U) +/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT29_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT30_MASK (0x40000000U) +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT30_SHIFT (30U) +/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT30_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT31_MASK (0x80000000U) +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT31_SHIFT (31U) +/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_BIT31_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W */ +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_COUNT (2U) + +/* The count of TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W */ +#define TRDC_MBC2_MBC_DOM1_MEM1_BLK_NSE_W_COUNT2 (1U) + +/*! @name MBC_DOM1_MEM2_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM2_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM2_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM2_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM2_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM2_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM2_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM2_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM2_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM2_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM2_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM2_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM2_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM2_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM2_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM2_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM2_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MBC_DOM1_MEM2_BLK_CFG_W */ +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_CFG_W_COUNT (2U) + +/* The count of TRDC_MBC2_MBC_DOM1_MEM2_BLK_CFG_W */ +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_CFG_W_COUNT2 (1U) + +/*! @name MBC_DOM1_MEM2_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ +/*! @{ */ + +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT0_MASK (0x1U) +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT0_SHIFT (0U) +/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT0_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT1_MASK (0x2U) +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT1_SHIFT (1U) +/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT1_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT2_MASK (0x4U) +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT2_SHIFT (2U) +/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT2_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT3_MASK (0x8U) +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT3_SHIFT (3U) +/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT3_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT4_MASK (0x10U) +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT4_SHIFT (4U) +/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT4_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT5_MASK (0x20U) +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT5_SHIFT (5U) +/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT5_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT6_MASK (0x40U) +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT6_SHIFT (6U) +/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT6_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT7_MASK (0x80U) +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT7_SHIFT (7U) +/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT7_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT8_MASK (0x100U) +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT8_SHIFT (8U) +/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT8_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT9_MASK (0x200U) +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT9_SHIFT (9U) +/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT9_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT10_MASK (0x400U) +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT10_SHIFT (10U) +/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT10_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT11_MASK (0x800U) +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT11_SHIFT (11U) +/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT11_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT12_MASK (0x1000U) +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT12_SHIFT (12U) +/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT12_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT13_MASK (0x2000U) +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT13_SHIFT (13U) +/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT13_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT14_MASK (0x4000U) +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT14_SHIFT (14U) +/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT14_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT15_MASK (0x8000U) +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT15_SHIFT (15U) +/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT15_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT16_MASK (0x10000U) +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT16_SHIFT (16U) +/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT16_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT17_MASK (0x20000U) +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT17_SHIFT (17U) +/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT17_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT18_MASK (0x40000U) +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT18_SHIFT (18U) +/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT18_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT19_MASK (0x80000U) +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT19_SHIFT (19U) +/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT19_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT20_MASK (0x100000U) +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT20_SHIFT (20U) +/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT20_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT21_MASK (0x200000U) +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT21_SHIFT (21U) +/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT21_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT22_MASK (0x400000U) +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT22_SHIFT (22U) +/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT22_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT23_MASK (0x800000U) +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT23_SHIFT (23U) +/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT23_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT24_MASK (0x1000000U) +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT24_SHIFT (24U) +/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT24_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT25_MASK (0x2000000U) +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT25_SHIFT (25U) +/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT25_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT26_MASK (0x4000000U) +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT26_SHIFT (26U) +/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT26_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT27_MASK (0x8000000U) +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT27_SHIFT (27U) +/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT27_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT28_MASK (0x10000000U) +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT28_SHIFT (28U) +/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT28_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT29_MASK (0x20000000U) +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT29_SHIFT (29U) +/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT29_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT30_MASK (0x40000000U) +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT30_SHIFT (30U) +/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT30_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT31_MASK (0x80000000U) +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT31_SHIFT (31U) +/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_BIT31_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W */ +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_COUNT (2U) + +/* The count of TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W */ +#define TRDC_MBC2_MBC_DOM1_MEM2_BLK_NSE_W_COUNT2 (1U) + +/*! @name MBC_DOM1_MEM3_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM3_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM3_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM3_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM3_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM3_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM3_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM3_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM3_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM3_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM3_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM3_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM3_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM3_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM3_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM3_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM3_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MBC_DOM1_MEM3_BLK_CFG_W */ +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_CFG_W_COUNT (2U) + +/* The count of TRDC_MBC2_MBC_DOM1_MEM3_BLK_CFG_W */ +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_CFG_W_COUNT2 (3U) + +/*! @name MBC_DOM1_MEM3_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ +/*! @{ */ + +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT0_MASK (0x1U) +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT0_SHIFT (0U) +/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT0_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT1_MASK (0x2U) +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT1_SHIFT (1U) +/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT1_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT2_MASK (0x4U) +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT2_SHIFT (2U) +/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT2_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT3_MASK (0x8U) +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT3_SHIFT (3U) +/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT3_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT4_MASK (0x10U) +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT4_SHIFT (4U) +/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT4_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT5_MASK (0x20U) +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT5_SHIFT (5U) +/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT5_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT6_MASK (0x40U) +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT6_SHIFT (6U) +/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT6_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT7_MASK (0x80U) +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT7_SHIFT (7U) +/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT7_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT8_MASK (0x100U) +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT8_SHIFT (8U) +/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT8_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT9_MASK (0x200U) +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT9_SHIFT (9U) +/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT9_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT10_MASK (0x400U) +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT10_SHIFT (10U) +/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT10_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT11_MASK (0x800U) +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT11_SHIFT (11U) +/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT11_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT12_MASK (0x1000U) +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT12_SHIFT (12U) +/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT12_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT13_MASK (0x2000U) +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT13_SHIFT (13U) +/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT13_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT14_MASK (0x4000U) +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT14_SHIFT (14U) +/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT14_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT15_MASK (0x8000U) +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT15_SHIFT (15U) +/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT15_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT16_MASK (0x10000U) +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT16_SHIFT (16U) +/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT16_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT17_MASK (0x20000U) +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT17_SHIFT (17U) +/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT17_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT18_MASK (0x40000U) +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT18_SHIFT (18U) +/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT18_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT19_MASK (0x80000U) +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT19_SHIFT (19U) +/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT19_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT20_MASK (0x100000U) +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT20_SHIFT (20U) +/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT20_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT21_MASK (0x200000U) +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT21_SHIFT (21U) +/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT21_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT22_MASK (0x400000U) +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT22_SHIFT (22U) +/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT22_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT23_MASK (0x800000U) +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT23_SHIFT (23U) +/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT23_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT24_MASK (0x1000000U) +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT24_SHIFT (24U) +/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT24_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT25_MASK (0x2000000U) +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT25_SHIFT (25U) +/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT25_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT26_MASK (0x4000000U) +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT26_SHIFT (26U) +/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT26_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT27_MASK (0x8000000U) +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT27_SHIFT (27U) +/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT27_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT28_MASK (0x10000000U) +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT28_SHIFT (28U) +/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT28_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT29_MASK (0x20000000U) +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT29_SHIFT (29U) +/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT29_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT30_MASK (0x40000000U) +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT30_SHIFT (30U) +/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT30_MASK) + +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT31_MASK (0x80000000U) +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT31_SHIFT (31U) +/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_BIT31_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W */ +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_COUNT (2U) + +/* The count of TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W */ +#define TRDC_MBC2_MBC_DOM1_MEM3_BLK_NSE_W_COUNT2 (1U) + +/*! @name MBC_DOM2_MEM0_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM0_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM0_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM0_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM0_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM0_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM0_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM0_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM0_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM0_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM0_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM0_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM0_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM0_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM0_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM0_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM0_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MBC_DOM2_MEM0_BLK_CFG_W */ +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_CFG_W_COUNT (2U) + +/* The count of TRDC_MBC2_MBC_DOM2_MEM0_BLK_CFG_W */ +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_CFG_W_COUNT2 (16U) + +/*! @name MBC_DOM2_MEM0_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ +/*! @{ */ + +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT0_MASK (0x1U) +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT0_SHIFT (0U) +/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT0_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT1_MASK (0x2U) +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT1_SHIFT (1U) +/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT1_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT2_MASK (0x4U) +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT2_SHIFT (2U) +/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT2_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT3_MASK (0x8U) +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT3_SHIFT (3U) +/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT3_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT4_MASK (0x10U) +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT4_SHIFT (4U) +/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT4_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT5_MASK (0x20U) +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT5_SHIFT (5U) +/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT5_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT6_MASK (0x40U) +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT6_SHIFT (6U) +/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT6_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT7_MASK (0x80U) +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT7_SHIFT (7U) +/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT7_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT8_MASK (0x100U) +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT8_SHIFT (8U) +/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT8_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT9_MASK (0x200U) +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT9_SHIFT (9U) +/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT9_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT10_MASK (0x400U) +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT10_SHIFT (10U) +/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT10_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT11_MASK (0x800U) +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT11_SHIFT (11U) +/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT11_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT12_MASK (0x1000U) +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT12_SHIFT (12U) +/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT12_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT13_MASK (0x2000U) +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT13_SHIFT (13U) +/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT13_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT14_MASK (0x4000U) +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT14_SHIFT (14U) +/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT14_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT15_MASK (0x8000U) +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT15_SHIFT (15U) +/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT15_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT16_MASK (0x10000U) +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT16_SHIFT (16U) +/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT16_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT17_MASK (0x20000U) +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT17_SHIFT (17U) +/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT17_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT18_MASK (0x40000U) +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT18_SHIFT (18U) +/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT18_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT19_MASK (0x80000U) +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT19_SHIFT (19U) +/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT19_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT20_MASK (0x100000U) +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT20_SHIFT (20U) +/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT20_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT21_MASK (0x200000U) +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT21_SHIFT (21U) +/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT21_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT22_MASK (0x400000U) +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT22_SHIFT (22U) +/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT22_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT23_MASK (0x800000U) +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT23_SHIFT (23U) +/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT23_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT24_MASK (0x1000000U) +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT24_SHIFT (24U) +/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT24_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT25_MASK (0x2000000U) +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT25_SHIFT (25U) +/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT25_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT26_MASK (0x4000000U) +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT26_SHIFT (26U) +/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT26_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT27_MASK (0x8000000U) +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT27_SHIFT (27U) +/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT27_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT28_MASK (0x10000000U) +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT28_SHIFT (28U) +/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT28_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT29_MASK (0x20000000U) +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT29_SHIFT (29U) +/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT29_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT30_MASK (0x40000000U) +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT30_SHIFT (30U) +/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT30_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT31_MASK (0x80000000U) +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT31_SHIFT (31U) +/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_BIT31_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W */ +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_COUNT (2U) + +/* The count of TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W */ +#define TRDC_MBC2_MBC_DOM2_MEM0_BLK_NSE_W_COUNT2 (4U) + +/*! @name MBC_DOM2_MEM1_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM1_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM1_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM1_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM1_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM1_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM1_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM1_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM1_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM1_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM1_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM1_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM1_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM1_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM1_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM1_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM1_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MBC_DOM2_MEM1_BLK_CFG_W */ +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_CFG_W_COUNT (2U) + +/* The count of TRDC_MBC2_MBC_DOM2_MEM1_BLK_CFG_W */ +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_CFG_W_COUNT2 (1U) + +/*! @name MBC_DOM2_MEM1_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ +/*! @{ */ + +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT0_MASK (0x1U) +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT0_SHIFT (0U) +/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT0_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT1_MASK (0x2U) +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT1_SHIFT (1U) +/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT1_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT2_MASK (0x4U) +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT2_SHIFT (2U) +/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT2_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT3_MASK (0x8U) +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT3_SHIFT (3U) +/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT3_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT4_MASK (0x10U) +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT4_SHIFT (4U) +/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT4_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT5_MASK (0x20U) +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT5_SHIFT (5U) +/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT5_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT6_MASK (0x40U) +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT6_SHIFT (6U) +/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT6_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT7_MASK (0x80U) +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT7_SHIFT (7U) +/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT7_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT8_MASK (0x100U) +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT8_SHIFT (8U) +/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT8_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT9_MASK (0x200U) +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT9_SHIFT (9U) +/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT9_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT10_MASK (0x400U) +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT10_SHIFT (10U) +/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT10_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT11_MASK (0x800U) +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT11_SHIFT (11U) +/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT11_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT12_MASK (0x1000U) +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT12_SHIFT (12U) +/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT12_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT13_MASK (0x2000U) +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT13_SHIFT (13U) +/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT13_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT14_MASK (0x4000U) +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT14_SHIFT (14U) +/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT14_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT15_MASK (0x8000U) +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT15_SHIFT (15U) +/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT15_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT16_MASK (0x10000U) +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT16_SHIFT (16U) +/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT16_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT17_MASK (0x20000U) +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT17_SHIFT (17U) +/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT17_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT18_MASK (0x40000U) +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT18_SHIFT (18U) +/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT18_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT19_MASK (0x80000U) +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT19_SHIFT (19U) +/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT19_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT20_MASK (0x100000U) +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT20_SHIFT (20U) +/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT20_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT21_MASK (0x200000U) +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT21_SHIFT (21U) +/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT21_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT22_MASK (0x400000U) +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT22_SHIFT (22U) +/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT22_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT23_MASK (0x800000U) +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT23_SHIFT (23U) +/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT23_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT24_MASK (0x1000000U) +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT24_SHIFT (24U) +/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT24_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT25_MASK (0x2000000U) +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT25_SHIFT (25U) +/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT25_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT26_MASK (0x4000000U) +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT26_SHIFT (26U) +/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT26_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT27_MASK (0x8000000U) +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT27_SHIFT (27U) +/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT27_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT28_MASK (0x10000000U) +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT28_SHIFT (28U) +/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT28_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT29_MASK (0x20000000U) +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT29_SHIFT (29U) +/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT29_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT30_MASK (0x40000000U) +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT30_SHIFT (30U) +/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT30_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT31_MASK (0x80000000U) +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT31_SHIFT (31U) +/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_BIT31_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W */ +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_COUNT (2U) + +/* The count of TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W */ +#define TRDC_MBC2_MBC_DOM2_MEM1_BLK_NSE_W_COUNT2 (1U) + +/*! @name MBC_DOM2_MEM2_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM2_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM2_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM2_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM2_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM2_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM2_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM2_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM2_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM2_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM2_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM2_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM2_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM2_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM2_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM2_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM2_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MBC_DOM2_MEM2_BLK_CFG_W */ +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_CFG_W_COUNT (2U) + +/* The count of TRDC_MBC2_MBC_DOM2_MEM2_BLK_CFG_W */ +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_CFG_W_COUNT2 (1U) + +/*! @name MBC_DOM2_MEM2_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ +/*! @{ */ + +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT0_MASK (0x1U) +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT0_SHIFT (0U) +/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT0_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT1_MASK (0x2U) +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT1_SHIFT (1U) +/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT1_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT2_MASK (0x4U) +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT2_SHIFT (2U) +/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT2_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT3_MASK (0x8U) +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT3_SHIFT (3U) +/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT3_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT4_MASK (0x10U) +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT4_SHIFT (4U) +/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT4_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT5_MASK (0x20U) +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT5_SHIFT (5U) +/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT5_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT6_MASK (0x40U) +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT6_SHIFT (6U) +/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT6_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT7_MASK (0x80U) +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT7_SHIFT (7U) +/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT7_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT8_MASK (0x100U) +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT8_SHIFT (8U) +/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT8_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT9_MASK (0x200U) +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT9_SHIFT (9U) +/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT9_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT10_MASK (0x400U) +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT10_SHIFT (10U) +/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT10_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT11_MASK (0x800U) +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT11_SHIFT (11U) +/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT11_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT12_MASK (0x1000U) +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT12_SHIFT (12U) +/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT12_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT13_MASK (0x2000U) +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT13_SHIFT (13U) +/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT13_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT14_MASK (0x4000U) +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT14_SHIFT (14U) +/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT14_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT15_MASK (0x8000U) +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT15_SHIFT (15U) +/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT15_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT16_MASK (0x10000U) +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT16_SHIFT (16U) +/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT16_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT17_MASK (0x20000U) +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT17_SHIFT (17U) +/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT17_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT18_MASK (0x40000U) +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT18_SHIFT (18U) +/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT18_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT19_MASK (0x80000U) +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT19_SHIFT (19U) +/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT19_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT20_MASK (0x100000U) +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT20_SHIFT (20U) +/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT20_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT21_MASK (0x200000U) +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT21_SHIFT (21U) +/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT21_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT22_MASK (0x400000U) +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT22_SHIFT (22U) +/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT22_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT23_MASK (0x800000U) +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT23_SHIFT (23U) +/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT23_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT24_MASK (0x1000000U) +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT24_SHIFT (24U) +/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT24_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT25_MASK (0x2000000U) +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT25_SHIFT (25U) +/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT25_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT26_MASK (0x4000000U) +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT26_SHIFT (26U) +/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT26_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT27_MASK (0x8000000U) +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT27_SHIFT (27U) +/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT27_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT28_MASK (0x10000000U) +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT28_SHIFT (28U) +/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT28_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT29_MASK (0x20000000U) +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT29_SHIFT (29U) +/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT29_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT30_MASK (0x40000000U) +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT30_SHIFT (30U) +/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT30_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT31_MASK (0x80000000U) +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT31_SHIFT (31U) +/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_BIT31_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W */ +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_COUNT (2U) + +/* The count of TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W */ +#define TRDC_MBC2_MBC_DOM2_MEM2_BLK_NSE_W_COUNT2 (1U) + +/*! @name MBC_DOM2_MEM3_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM3_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM3_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM3_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM3_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM3_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM3_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM3_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM3_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM3_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM3_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM3_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM3_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM3_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM3_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM3_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM3_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MBC_DOM2_MEM3_BLK_CFG_W */ +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_CFG_W_COUNT (2U) + +/* The count of TRDC_MBC2_MBC_DOM2_MEM3_BLK_CFG_W */ +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_CFG_W_COUNT2 (3U) + +/*! @name MBC_DOM2_MEM3_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ +/*! @{ */ + +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT0_MASK (0x1U) +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT0_SHIFT (0U) +/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT0_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT1_MASK (0x2U) +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT1_SHIFT (1U) +/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT1_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT2_MASK (0x4U) +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT2_SHIFT (2U) +/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT2_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT3_MASK (0x8U) +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT3_SHIFT (3U) +/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT3_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT4_MASK (0x10U) +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT4_SHIFT (4U) +/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT4_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT5_MASK (0x20U) +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT5_SHIFT (5U) +/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT5_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT6_MASK (0x40U) +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT6_SHIFT (6U) +/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT6_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT7_MASK (0x80U) +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT7_SHIFT (7U) +/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT7_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT8_MASK (0x100U) +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT8_SHIFT (8U) +/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT8_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT9_MASK (0x200U) +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT9_SHIFT (9U) +/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT9_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT10_MASK (0x400U) +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT10_SHIFT (10U) +/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT10_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT11_MASK (0x800U) +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT11_SHIFT (11U) +/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT11_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT12_MASK (0x1000U) +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT12_SHIFT (12U) +/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT12_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT13_MASK (0x2000U) +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT13_SHIFT (13U) +/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT13_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT14_MASK (0x4000U) +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT14_SHIFT (14U) +/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT14_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT15_MASK (0x8000U) +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT15_SHIFT (15U) +/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT15_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT16_MASK (0x10000U) +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT16_SHIFT (16U) +/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT16_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT17_MASK (0x20000U) +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT17_SHIFT (17U) +/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT17_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT18_MASK (0x40000U) +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT18_SHIFT (18U) +/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT18_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT19_MASK (0x80000U) +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT19_SHIFT (19U) +/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT19_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT20_MASK (0x100000U) +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT20_SHIFT (20U) +/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT20_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT21_MASK (0x200000U) +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT21_SHIFT (21U) +/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT21_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT22_MASK (0x400000U) +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT22_SHIFT (22U) +/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT22_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT23_MASK (0x800000U) +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT23_SHIFT (23U) +/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT23_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT24_MASK (0x1000000U) +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT24_SHIFT (24U) +/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT24_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT25_MASK (0x2000000U) +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT25_SHIFT (25U) +/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT25_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT26_MASK (0x4000000U) +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT26_SHIFT (26U) +/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT26_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT27_MASK (0x8000000U) +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT27_SHIFT (27U) +/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT27_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT28_MASK (0x10000000U) +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT28_SHIFT (28U) +/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT28_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT29_MASK (0x20000000U) +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT29_SHIFT (29U) +/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT29_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT30_MASK (0x40000000U) +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT30_SHIFT (30U) +/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT30_MASK) + +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT31_MASK (0x80000000U) +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT31_SHIFT (31U) +/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_BIT31_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W */ +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_COUNT (2U) + +/* The count of TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W */ +#define TRDC_MBC2_MBC_DOM2_MEM3_BLK_NSE_W_COUNT2 (1U) + +/*! @name MBC_DOM3_MEM0_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM0_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM0_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM0_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM0_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM0_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM0_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM0_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM0_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM0_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM0_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM0_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM0_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM0_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM0_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM0_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM0_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM0_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM0_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM0_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM0_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM0_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM0_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM0_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM0_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM0_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM0_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM0_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM0_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM0_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM0_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM0_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM0_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MBC_DOM3_MEM0_BLK_CFG_W */ +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_CFG_W_COUNT (2U) + +/* The count of TRDC_MBC2_MBC_DOM3_MEM0_BLK_CFG_W */ +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_CFG_W_COUNT2 (16U) + +/*! @name MBC_DOM3_MEM0_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ +/*! @{ */ + +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT0_MASK (0x1U) +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT0_SHIFT (0U) +/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT0_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT1_MASK (0x2U) +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT1_SHIFT (1U) +/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT1_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT2_MASK (0x4U) +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT2_SHIFT (2U) +/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT2_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT3_MASK (0x8U) +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT3_SHIFT (3U) +/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT3_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT4_MASK (0x10U) +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT4_SHIFT (4U) +/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT4_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT5_MASK (0x20U) +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT5_SHIFT (5U) +/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT5_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT6_MASK (0x40U) +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT6_SHIFT (6U) +/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT6_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT7_MASK (0x80U) +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT7_SHIFT (7U) +/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT7_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT8_MASK (0x100U) +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT8_SHIFT (8U) +/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT8_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT9_MASK (0x200U) +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT9_SHIFT (9U) +/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT9_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT10_MASK (0x400U) +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT10_SHIFT (10U) +/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT10_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT11_MASK (0x800U) +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT11_SHIFT (11U) +/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT11_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT12_MASK (0x1000U) +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT12_SHIFT (12U) +/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT12_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT13_MASK (0x2000U) +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT13_SHIFT (13U) +/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT13_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT14_MASK (0x4000U) +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT14_SHIFT (14U) +/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT14_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT15_MASK (0x8000U) +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT15_SHIFT (15U) +/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT15_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT16_MASK (0x10000U) +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT16_SHIFT (16U) +/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT16_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT17_MASK (0x20000U) +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT17_SHIFT (17U) +/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT17_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT18_MASK (0x40000U) +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT18_SHIFT (18U) +/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT18_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT19_MASK (0x80000U) +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT19_SHIFT (19U) +/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT19_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT20_MASK (0x100000U) +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT20_SHIFT (20U) +/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT20_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT21_MASK (0x200000U) +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT21_SHIFT (21U) +/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT21_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT22_MASK (0x400000U) +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT22_SHIFT (22U) +/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT22_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT23_MASK (0x800000U) +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT23_SHIFT (23U) +/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT23_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT24_MASK (0x1000000U) +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT24_SHIFT (24U) +/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT24_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT25_MASK (0x2000000U) +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT25_SHIFT (25U) +/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT25_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT26_MASK (0x4000000U) +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT26_SHIFT (26U) +/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT26_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT27_MASK (0x8000000U) +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT27_SHIFT (27U) +/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT27_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT28_MASK (0x10000000U) +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT28_SHIFT (28U) +/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT28_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT29_MASK (0x20000000U) +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT29_SHIFT (29U) +/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT29_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT30_MASK (0x40000000U) +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT30_SHIFT (30U) +/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT30_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT31_MASK (0x80000000U) +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT31_SHIFT (31U) +/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_BIT31_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W */ +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_COUNT (2U) + +/* The count of TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W */ +#define TRDC_MBC2_MBC_DOM3_MEM0_BLK_NSE_W_COUNT2 (4U) + +/*! @name MBC_DOM3_MEM1_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM1_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM1_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM1_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM1_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM1_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM1_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM1_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM1_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM1_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM1_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM1_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM1_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM1_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM1_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM1_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM1_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM1_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM1_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM1_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM1_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM1_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM1_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM1_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM1_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM1_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM1_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM1_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM1_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM1_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM1_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM1_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM1_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MBC_DOM3_MEM1_BLK_CFG_W */ +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_CFG_W_COUNT (2U) + +/* The count of TRDC_MBC2_MBC_DOM3_MEM1_BLK_CFG_W */ +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_CFG_W_COUNT2 (1U) + +/*! @name MBC_DOM3_MEM1_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ +/*! @{ */ + +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT0_MASK (0x1U) +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT0_SHIFT (0U) +/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT0_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT1_MASK (0x2U) +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT1_SHIFT (1U) +/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT1_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT2_MASK (0x4U) +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT2_SHIFT (2U) +/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT2_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT3_MASK (0x8U) +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT3_SHIFT (3U) +/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT3_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT4_MASK (0x10U) +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT4_SHIFT (4U) +/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT4_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT5_MASK (0x20U) +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT5_SHIFT (5U) +/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT5_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT6_MASK (0x40U) +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT6_SHIFT (6U) +/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT6_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT7_MASK (0x80U) +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT7_SHIFT (7U) +/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT7_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT8_MASK (0x100U) +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT8_SHIFT (8U) +/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT8_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT9_MASK (0x200U) +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT9_SHIFT (9U) +/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT9_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT10_MASK (0x400U) +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT10_SHIFT (10U) +/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT10_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT11_MASK (0x800U) +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT11_SHIFT (11U) +/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT11_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT12_MASK (0x1000U) +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT12_SHIFT (12U) +/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT12_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT13_MASK (0x2000U) +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT13_SHIFT (13U) +/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT13_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT14_MASK (0x4000U) +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT14_SHIFT (14U) +/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT14_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT15_MASK (0x8000U) +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT15_SHIFT (15U) +/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT15_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT16_MASK (0x10000U) +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT16_SHIFT (16U) +/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT16_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT17_MASK (0x20000U) +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT17_SHIFT (17U) +/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT17_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT18_MASK (0x40000U) +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT18_SHIFT (18U) +/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT18_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT19_MASK (0x80000U) +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT19_SHIFT (19U) +/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT19_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT20_MASK (0x100000U) +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT20_SHIFT (20U) +/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT20_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT21_MASK (0x200000U) +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT21_SHIFT (21U) +/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT21_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT22_MASK (0x400000U) +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT22_SHIFT (22U) +/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT22_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT23_MASK (0x800000U) +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT23_SHIFT (23U) +/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT23_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT24_MASK (0x1000000U) +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT24_SHIFT (24U) +/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT24_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT25_MASK (0x2000000U) +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT25_SHIFT (25U) +/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT25_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT26_MASK (0x4000000U) +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT26_SHIFT (26U) +/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT26_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT27_MASK (0x8000000U) +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT27_SHIFT (27U) +/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT27_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT28_MASK (0x10000000U) +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT28_SHIFT (28U) +/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT28_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT29_MASK (0x20000000U) +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT29_SHIFT (29U) +/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT29_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT30_MASK (0x40000000U) +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT30_SHIFT (30U) +/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT30_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT31_MASK (0x80000000U) +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT31_SHIFT (31U) +/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_BIT31_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W */ +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_COUNT (2U) + +/* The count of TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W */ +#define TRDC_MBC2_MBC_DOM3_MEM1_BLK_NSE_W_COUNT2 (1U) + +/*! @name MBC_DOM3_MEM2_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM2_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM2_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM2_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM2_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM2_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM2_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM2_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM2_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM2_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM2_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM2_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM2_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM2_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM2_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM2_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM2_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM2_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM2_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM2_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM2_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM2_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM2_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM2_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM2_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM2_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM2_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM2_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM2_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM2_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM2_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM2_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM2_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MBC_DOM3_MEM2_BLK_CFG_W */ +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_CFG_W_COUNT (2U) + +/* The count of TRDC_MBC2_MBC_DOM3_MEM2_BLK_CFG_W */ +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_CFG_W_COUNT2 (1U) + +/*! @name MBC_DOM3_MEM2_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ +/*! @{ */ + +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT0_MASK (0x1U) +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT0_SHIFT (0U) +/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT0_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT1_MASK (0x2U) +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT1_SHIFT (1U) +/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT1_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT2_MASK (0x4U) +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT2_SHIFT (2U) +/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT2_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT3_MASK (0x8U) +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT3_SHIFT (3U) +/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT3_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT4_MASK (0x10U) +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT4_SHIFT (4U) +/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT4_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT5_MASK (0x20U) +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT5_SHIFT (5U) +/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT5_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT6_MASK (0x40U) +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT6_SHIFT (6U) +/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT6_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT7_MASK (0x80U) +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT7_SHIFT (7U) +/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT7_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT8_MASK (0x100U) +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT8_SHIFT (8U) +/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT8_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT9_MASK (0x200U) +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT9_SHIFT (9U) +/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT9_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT10_MASK (0x400U) +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT10_SHIFT (10U) +/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT10_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT11_MASK (0x800U) +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT11_SHIFT (11U) +/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT11_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT12_MASK (0x1000U) +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT12_SHIFT (12U) +/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT12_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT13_MASK (0x2000U) +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT13_SHIFT (13U) +/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT13_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT14_MASK (0x4000U) +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT14_SHIFT (14U) +/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT14_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT15_MASK (0x8000U) +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT15_SHIFT (15U) +/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT15_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT16_MASK (0x10000U) +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT16_SHIFT (16U) +/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT16_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT17_MASK (0x20000U) +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT17_SHIFT (17U) +/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT17_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT18_MASK (0x40000U) +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT18_SHIFT (18U) +/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT18_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT19_MASK (0x80000U) +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT19_SHIFT (19U) +/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT19_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT20_MASK (0x100000U) +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT20_SHIFT (20U) +/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT20_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT21_MASK (0x200000U) +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT21_SHIFT (21U) +/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT21_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT22_MASK (0x400000U) +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT22_SHIFT (22U) +/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT22_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT23_MASK (0x800000U) +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT23_SHIFT (23U) +/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT23_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT24_MASK (0x1000000U) +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT24_SHIFT (24U) +/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT24_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT25_MASK (0x2000000U) +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT25_SHIFT (25U) +/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT25_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT26_MASK (0x4000000U) +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT26_SHIFT (26U) +/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT26_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT27_MASK (0x8000000U) +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT27_SHIFT (27U) +/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT27_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT28_MASK (0x10000000U) +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT28_SHIFT (28U) +/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT28_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT29_MASK (0x20000000U) +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT29_SHIFT (29U) +/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT29_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT30_MASK (0x40000000U) +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT30_SHIFT (30U) +/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT30_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT31_MASK (0x80000000U) +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT31_SHIFT (31U) +/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_BIT31_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W */ +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_COUNT (2U) + +/* The count of TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W */ +#define TRDC_MBC2_MBC_DOM3_MEM2_BLK_NSE_W_COUNT2 (1U) + +/*! @name MBC_DOM3_MEM3_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM3_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM3_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM3_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM3_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM3_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM3_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM3_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM3_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM3_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM3_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM3_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM3_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM3_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM3_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM3_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM3_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM3_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM3_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM3_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM3_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM3_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM3_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM3_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM3_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM3_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM3_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM3_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM3_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM3_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM3_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM3_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM3_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MBC_DOM3_MEM3_BLK_CFG_W */ +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_CFG_W_COUNT (2U) + +/* The count of TRDC_MBC2_MBC_DOM3_MEM3_BLK_CFG_W */ +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_CFG_W_COUNT2 (3U) + +/*! @name MBC_DOM3_MEM3_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ +/*! @{ */ + +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT0_MASK (0x1U) +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT0_SHIFT (0U) +/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT0_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT1_MASK (0x2U) +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT1_SHIFT (1U) +/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT1_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT2_MASK (0x4U) +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT2_SHIFT (2U) +/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT2_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT3_MASK (0x8U) +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT3_SHIFT (3U) +/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT3_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT4_MASK (0x10U) +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT4_SHIFT (4U) +/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT4_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT5_MASK (0x20U) +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT5_SHIFT (5U) +/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT5_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT6_MASK (0x40U) +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT6_SHIFT (6U) +/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT6_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT7_MASK (0x80U) +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT7_SHIFT (7U) +/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT7_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT8_MASK (0x100U) +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT8_SHIFT (8U) +/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT8_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT9_MASK (0x200U) +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT9_SHIFT (9U) +/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT9_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT10_MASK (0x400U) +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT10_SHIFT (10U) +/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT10_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT11_MASK (0x800U) +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT11_SHIFT (11U) +/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT11_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT12_MASK (0x1000U) +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT12_SHIFT (12U) +/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT12_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT13_MASK (0x2000U) +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT13_SHIFT (13U) +/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT13_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT14_MASK (0x4000U) +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT14_SHIFT (14U) +/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT14_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT15_MASK (0x8000U) +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT15_SHIFT (15U) +/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT15_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT16_MASK (0x10000U) +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT16_SHIFT (16U) +/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT16_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT17_MASK (0x20000U) +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT17_SHIFT (17U) +/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT17_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT18_MASK (0x40000U) +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT18_SHIFT (18U) +/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT18_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT19_MASK (0x80000U) +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT19_SHIFT (19U) +/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT19_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT20_MASK (0x100000U) +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT20_SHIFT (20U) +/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT20_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT21_MASK (0x200000U) +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT21_SHIFT (21U) +/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT21_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT22_MASK (0x400000U) +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT22_SHIFT (22U) +/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT22_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT23_MASK (0x800000U) +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT23_SHIFT (23U) +/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT23_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT24_MASK (0x1000000U) +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT24_SHIFT (24U) +/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT24_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT25_MASK (0x2000000U) +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT25_SHIFT (25U) +/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT25_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT26_MASK (0x4000000U) +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT26_SHIFT (26U) +/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT26_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT27_MASK (0x8000000U) +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT27_SHIFT (27U) +/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT27_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT28_MASK (0x10000000U) +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT28_SHIFT (28U) +/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT28_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT29_MASK (0x20000000U) +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT29_SHIFT (29U) +/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT29_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT30_MASK (0x40000000U) +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT30_SHIFT (30U) +/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT30_MASK) + +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT31_MASK (0x80000000U) +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT31_SHIFT (31U) +/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_BIT31_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W */ +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_COUNT (2U) + +/* The count of TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W */ +#define TRDC_MBC2_MBC_DOM3_MEM3_BLK_NSE_W_COUNT2 (1U) + +/*! @name MBC_DOM4_MEM0_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM0_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM0_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM0_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM0_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM0_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM0_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM0_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM0_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM0_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM0_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM0_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM0_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM0_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM0_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM0_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM0_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM0_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM0_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM0_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM0_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM0_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM0_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM0_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM0_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM0_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM0_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM0_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM0_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM0_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM0_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM0_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM0_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MBC_DOM4_MEM0_BLK_CFG_W */ +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_CFG_W_COUNT (2U) + +/* The count of TRDC_MBC2_MBC_DOM4_MEM0_BLK_CFG_W */ +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_CFG_W_COUNT2 (16U) + +/*! @name MBC_DOM4_MEM0_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ +/*! @{ */ + +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT0_MASK (0x1U) +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT0_SHIFT (0U) +/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT0_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT1_MASK (0x2U) +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT1_SHIFT (1U) +/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT1_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT2_MASK (0x4U) +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT2_SHIFT (2U) +/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT2_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT3_MASK (0x8U) +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT3_SHIFT (3U) +/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT3_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT4_MASK (0x10U) +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT4_SHIFT (4U) +/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT4_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT5_MASK (0x20U) +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT5_SHIFT (5U) +/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT5_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT6_MASK (0x40U) +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT6_SHIFT (6U) +/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT6_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT7_MASK (0x80U) +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT7_SHIFT (7U) +/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT7_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT8_MASK (0x100U) +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT8_SHIFT (8U) +/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT8_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT9_MASK (0x200U) +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT9_SHIFT (9U) +/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT9_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT10_MASK (0x400U) +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT10_SHIFT (10U) +/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT10_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT11_MASK (0x800U) +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT11_SHIFT (11U) +/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT11_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT12_MASK (0x1000U) +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT12_SHIFT (12U) +/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT12_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT13_MASK (0x2000U) +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT13_SHIFT (13U) +/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT13_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT14_MASK (0x4000U) +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT14_SHIFT (14U) +/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT14_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT15_MASK (0x8000U) +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT15_SHIFT (15U) +/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT15_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT16_MASK (0x10000U) +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT16_SHIFT (16U) +/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT16_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT17_MASK (0x20000U) +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT17_SHIFT (17U) +/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT17_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT18_MASK (0x40000U) +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT18_SHIFT (18U) +/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT18_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT19_MASK (0x80000U) +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT19_SHIFT (19U) +/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT19_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT20_MASK (0x100000U) +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT20_SHIFT (20U) +/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT20_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT21_MASK (0x200000U) +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT21_SHIFT (21U) +/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT21_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT22_MASK (0x400000U) +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT22_SHIFT (22U) +/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT22_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT23_MASK (0x800000U) +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT23_SHIFT (23U) +/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT23_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT24_MASK (0x1000000U) +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT24_SHIFT (24U) +/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT24_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT25_MASK (0x2000000U) +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT25_SHIFT (25U) +/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT25_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT26_MASK (0x4000000U) +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT26_SHIFT (26U) +/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT26_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT27_MASK (0x8000000U) +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT27_SHIFT (27U) +/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT27_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT28_MASK (0x10000000U) +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT28_SHIFT (28U) +/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT28_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT29_MASK (0x20000000U) +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT29_SHIFT (29U) +/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT29_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT30_MASK (0x40000000U) +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT30_SHIFT (30U) +/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT30_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT31_MASK (0x80000000U) +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT31_SHIFT (31U) +/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_BIT31_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W */ +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_COUNT (2U) + +/* The count of TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W */ +#define TRDC_MBC2_MBC_DOM4_MEM0_BLK_NSE_W_COUNT2 (4U) + +/*! @name MBC_DOM4_MEM1_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM1_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM1_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM1_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM1_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM1_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM1_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM1_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM1_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM1_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM1_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM1_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM1_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM1_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM1_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM1_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM1_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM1_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM1_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM1_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM1_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM1_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM1_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM1_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM1_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM1_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM1_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM1_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM1_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM1_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM1_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM1_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM1_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MBC_DOM4_MEM1_BLK_CFG_W */ +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_CFG_W_COUNT (2U) + +/* The count of TRDC_MBC2_MBC_DOM4_MEM1_BLK_CFG_W */ +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_CFG_W_COUNT2 (1U) + +/*! @name MBC_DOM4_MEM1_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ +/*! @{ */ + +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT0_MASK (0x1U) +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT0_SHIFT (0U) +/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT0_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT1_MASK (0x2U) +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT1_SHIFT (1U) +/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT1_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT2_MASK (0x4U) +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT2_SHIFT (2U) +/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT2_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT3_MASK (0x8U) +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT3_SHIFT (3U) +/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT3_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT4_MASK (0x10U) +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT4_SHIFT (4U) +/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT4_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT5_MASK (0x20U) +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT5_SHIFT (5U) +/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT5_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT6_MASK (0x40U) +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT6_SHIFT (6U) +/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT6_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT7_MASK (0x80U) +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT7_SHIFT (7U) +/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT7_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT8_MASK (0x100U) +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT8_SHIFT (8U) +/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT8_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT9_MASK (0x200U) +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT9_SHIFT (9U) +/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT9_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT10_MASK (0x400U) +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT10_SHIFT (10U) +/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT10_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT11_MASK (0x800U) +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT11_SHIFT (11U) +/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT11_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT12_MASK (0x1000U) +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT12_SHIFT (12U) +/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT12_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT13_MASK (0x2000U) +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT13_SHIFT (13U) +/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT13_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT14_MASK (0x4000U) +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT14_SHIFT (14U) +/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT14_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT15_MASK (0x8000U) +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT15_SHIFT (15U) +/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT15_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT16_MASK (0x10000U) +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT16_SHIFT (16U) +/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT16_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT17_MASK (0x20000U) +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT17_SHIFT (17U) +/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT17_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT18_MASK (0x40000U) +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT18_SHIFT (18U) +/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT18_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT19_MASK (0x80000U) +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT19_SHIFT (19U) +/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT19_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT20_MASK (0x100000U) +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT20_SHIFT (20U) +/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT20_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT21_MASK (0x200000U) +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT21_SHIFT (21U) +/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT21_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT22_MASK (0x400000U) +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT22_SHIFT (22U) +/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT22_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT23_MASK (0x800000U) +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT23_SHIFT (23U) +/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT23_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT24_MASK (0x1000000U) +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT24_SHIFT (24U) +/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT24_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT25_MASK (0x2000000U) +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT25_SHIFT (25U) +/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT25_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT26_MASK (0x4000000U) +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT26_SHIFT (26U) +/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT26_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT27_MASK (0x8000000U) +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT27_SHIFT (27U) +/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT27_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT28_MASK (0x10000000U) +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT28_SHIFT (28U) +/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT28_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT29_MASK (0x20000000U) +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT29_SHIFT (29U) +/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT29_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT30_MASK (0x40000000U) +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT30_SHIFT (30U) +/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT30_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT31_MASK (0x80000000U) +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT31_SHIFT (31U) +/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_BIT31_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W */ +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_COUNT (2U) + +/* The count of TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W */ +#define TRDC_MBC2_MBC_DOM4_MEM1_BLK_NSE_W_COUNT2 (1U) + +/*! @name MBC_DOM4_MEM2_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM2_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM2_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM2_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM2_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM2_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM2_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM2_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM2_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM2_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM2_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM2_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM2_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM2_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM2_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM2_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM2_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM2_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM2_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM2_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM2_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM2_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM2_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM2_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM2_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM2_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM2_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM2_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM2_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM2_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM2_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM2_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM2_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MBC_DOM4_MEM2_BLK_CFG_W */ +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_CFG_W_COUNT (2U) + +/* The count of TRDC_MBC2_MBC_DOM4_MEM2_BLK_CFG_W */ +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_CFG_W_COUNT2 (1U) + +/*! @name MBC_DOM4_MEM2_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ +/*! @{ */ + +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT0_MASK (0x1U) +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT0_SHIFT (0U) +/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT0_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT1_MASK (0x2U) +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT1_SHIFT (1U) +/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT1_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT2_MASK (0x4U) +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT2_SHIFT (2U) +/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT2_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT3_MASK (0x8U) +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT3_SHIFT (3U) +/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT3_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT4_MASK (0x10U) +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT4_SHIFT (4U) +/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT4_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT5_MASK (0x20U) +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT5_SHIFT (5U) +/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT5_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT6_MASK (0x40U) +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT6_SHIFT (6U) +/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT6_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT7_MASK (0x80U) +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT7_SHIFT (7U) +/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT7_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT8_MASK (0x100U) +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT8_SHIFT (8U) +/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT8_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT9_MASK (0x200U) +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT9_SHIFT (9U) +/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT9_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT10_MASK (0x400U) +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT10_SHIFT (10U) +/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT10_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT11_MASK (0x800U) +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT11_SHIFT (11U) +/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT11_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT12_MASK (0x1000U) +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT12_SHIFT (12U) +/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT12_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT13_MASK (0x2000U) +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT13_SHIFT (13U) +/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT13_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT14_MASK (0x4000U) +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT14_SHIFT (14U) +/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT14_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT15_MASK (0x8000U) +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT15_SHIFT (15U) +/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT15_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT16_MASK (0x10000U) +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT16_SHIFT (16U) +/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT16_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT17_MASK (0x20000U) +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT17_SHIFT (17U) +/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT17_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT18_MASK (0x40000U) +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT18_SHIFT (18U) +/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT18_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT19_MASK (0x80000U) +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT19_SHIFT (19U) +/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT19_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT20_MASK (0x100000U) +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT20_SHIFT (20U) +/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT20_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT21_MASK (0x200000U) +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT21_SHIFT (21U) +/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT21_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT22_MASK (0x400000U) +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT22_SHIFT (22U) +/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT22_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT23_MASK (0x800000U) +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT23_SHIFT (23U) +/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT23_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT24_MASK (0x1000000U) +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT24_SHIFT (24U) +/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT24_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT25_MASK (0x2000000U) +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT25_SHIFT (25U) +/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT25_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT26_MASK (0x4000000U) +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT26_SHIFT (26U) +/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT26_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT27_MASK (0x8000000U) +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT27_SHIFT (27U) +/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT27_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT28_MASK (0x10000000U) +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT28_SHIFT (28U) +/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT28_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT29_MASK (0x20000000U) +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT29_SHIFT (29U) +/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT29_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT30_MASK (0x40000000U) +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT30_SHIFT (30U) +/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT30_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT31_MASK (0x80000000U) +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT31_SHIFT (31U) +/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_BIT31_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W */ +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_COUNT (2U) + +/* The count of TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W */ +#define TRDC_MBC2_MBC_DOM4_MEM2_BLK_NSE_W_COUNT2 (1U) + +/*! @name MBC_DOM4_MEM3_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM3_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM3_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM3_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM3_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM3_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM3_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM3_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM3_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM3_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM3_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM3_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM3_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM3_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM3_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM3_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM3_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM3_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM3_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM3_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM3_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM3_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM3_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM3_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM3_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM3_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM3_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM3_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM3_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM3_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM3_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM3_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM3_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MBC_DOM4_MEM3_BLK_CFG_W */ +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_CFG_W_COUNT (2U) + +/* The count of TRDC_MBC2_MBC_DOM4_MEM3_BLK_CFG_W */ +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_CFG_W_COUNT2 (3U) + +/*! @name MBC_DOM4_MEM3_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ +/*! @{ */ + +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT0_MASK (0x1U) +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT0_SHIFT (0U) +/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT0_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT1_MASK (0x2U) +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT1_SHIFT (1U) +/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT1_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT2_MASK (0x4U) +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT2_SHIFT (2U) +/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT2_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT3_MASK (0x8U) +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT3_SHIFT (3U) +/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT3_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT4_MASK (0x10U) +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT4_SHIFT (4U) +/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT4_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT5_MASK (0x20U) +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT5_SHIFT (5U) +/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT5_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT6_MASK (0x40U) +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT6_SHIFT (6U) +/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT6_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT7_MASK (0x80U) +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT7_SHIFT (7U) +/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT7_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT8_MASK (0x100U) +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT8_SHIFT (8U) +/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT8_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT9_MASK (0x200U) +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT9_SHIFT (9U) +/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT9_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT10_MASK (0x400U) +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT10_SHIFT (10U) +/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT10_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT11_MASK (0x800U) +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT11_SHIFT (11U) +/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT11_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT12_MASK (0x1000U) +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT12_SHIFT (12U) +/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT12_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT13_MASK (0x2000U) +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT13_SHIFT (13U) +/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT13_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT14_MASK (0x4000U) +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT14_SHIFT (14U) +/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT14_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT15_MASK (0x8000U) +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT15_SHIFT (15U) +/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT15_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT16_MASK (0x10000U) +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT16_SHIFT (16U) +/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT16_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT17_MASK (0x20000U) +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT17_SHIFT (17U) +/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT17_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT18_MASK (0x40000U) +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT18_SHIFT (18U) +/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT18_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT19_MASK (0x80000U) +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT19_SHIFT (19U) +/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT19_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT20_MASK (0x100000U) +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT20_SHIFT (20U) +/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT20_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT21_MASK (0x200000U) +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT21_SHIFT (21U) +/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT21_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT22_MASK (0x400000U) +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT22_SHIFT (22U) +/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT22_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT23_MASK (0x800000U) +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT23_SHIFT (23U) +/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT23_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT24_MASK (0x1000000U) +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT24_SHIFT (24U) +/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT24_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT25_MASK (0x2000000U) +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT25_SHIFT (25U) +/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT25_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT26_MASK (0x4000000U) +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT26_SHIFT (26U) +/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT26_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT27_MASK (0x8000000U) +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT27_SHIFT (27U) +/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT27_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT28_MASK (0x10000000U) +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT28_SHIFT (28U) +/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT28_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT29_MASK (0x20000000U) +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT29_SHIFT (29U) +/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT29_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT30_MASK (0x40000000U) +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT30_SHIFT (30U) +/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT30_MASK) + +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT31_MASK (0x80000000U) +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT31_SHIFT (31U) +/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_BIT31_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W */ +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_COUNT (2U) + +/* The count of TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W */ +#define TRDC_MBC2_MBC_DOM4_MEM3_BLK_NSE_W_COUNT2 (1U) + +/*! @name MBC_DOM5_MEM0_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM0_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM0_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM0_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM0_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM0_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM0_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM0_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM0_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM0_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM0_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM0_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM0_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM0_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM0_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM0_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM0_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM0_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM0_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM0_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM0_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM0_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM0_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM0_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM0_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM0_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM0_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM0_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM0_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM0_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM0_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM0_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM0_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MBC_DOM5_MEM0_BLK_CFG_W */ +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_CFG_W_COUNT (2U) + +/* The count of TRDC_MBC2_MBC_DOM5_MEM0_BLK_CFG_W */ +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_CFG_W_COUNT2 (16U) + +/*! @name MBC_DOM5_MEM0_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ +/*! @{ */ + +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT0_MASK (0x1U) +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT0_SHIFT (0U) +/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT0_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT1_MASK (0x2U) +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT1_SHIFT (1U) +/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT1_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT2_MASK (0x4U) +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT2_SHIFT (2U) +/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT2_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT3_MASK (0x8U) +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT3_SHIFT (3U) +/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT3_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT4_MASK (0x10U) +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT4_SHIFT (4U) +/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT4_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT5_MASK (0x20U) +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT5_SHIFT (5U) +/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT5_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT6_MASK (0x40U) +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT6_SHIFT (6U) +/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT6_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT7_MASK (0x80U) +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT7_SHIFT (7U) +/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT7_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT8_MASK (0x100U) +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT8_SHIFT (8U) +/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT8_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT9_MASK (0x200U) +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT9_SHIFT (9U) +/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT9_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT10_MASK (0x400U) +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT10_SHIFT (10U) +/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT10_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT11_MASK (0x800U) +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT11_SHIFT (11U) +/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT11_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT12_MASK (0x1000U) +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT12_SHIFT (12U) +/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT12_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT13_MASK (0x2000U) +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT13_SHIFT (13U) +/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT13_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT14_MASK (0x4000U) +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT14_SHIFT (14U) +/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT14_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT15_MASK (0x8000U) +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT15_SHIFT (15U) +/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT15_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT16_MASK (0x10000U) +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT16_SHIFT (16U) +/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT16_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT17_MASK (0x20000U) +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT17_SHIFT (17U) +/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT17_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT18_MASK (0x40000U) +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT18_SHIFT (18U) +/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT18_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT19_MASK (0x80000U) +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT19_SHIFT (19U) +/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT19_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT20_MASK (0x100000U) +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT20_SHIFT (20U) +/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT20_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT21_MASK (0x200000U) +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT21_SHIFT (21U) +/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT21_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT22_MASK (0x400000U) +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT22_SHIFT (22U) +/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT22_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT23_MASK (0x800000U) +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT23_SHIFT (23U) +/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT23_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT24_MASK (0x1000000U) +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT24_SHIFT (24U) +/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT24_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT25_MASK (0x2000000U) +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT25_SHIFT (25U) +/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT25_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT26_MASK (0x4000000U) +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT26_SHIFT (26U) +/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT26_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT27_MASK (0x8000000U) +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT27_SHIFT (27U) +/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT27_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT28_MASK (0x10000000U) +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT28_SHIFT (28U) +/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT28_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT29_MASK (0x20000000U) +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT29_SHIFT (29U) +/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT29_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT30_MASK (0x40000000U) +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT30_SHIFT (30U) +/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT30_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT31_MASK (0x80000000U) +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT31_SHIFT (31U) +/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_BIT31_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W */ +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_COUNT (2U) + +/* The count of TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W */ +#define TRDC_MBC2_MBC_DOM5_MEM0_BLK_NSE_W_COUNT2 (4U) + +/*! @name MBC_DOM5_MEM1_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM1_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM1_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM1_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM1_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM1_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM1_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM1_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM1_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM1_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM1_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM1_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM1_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM1_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM1_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM1_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM1_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM1_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM1_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM1_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM1_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM1_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM1_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM1_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM1_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM1_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM1_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM1_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM1_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM1_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM1_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM1_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM1_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MBC_DOM5_MEM1_BLK_CFG_W */ +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_CFG_W_COUNT (2U) + +/* The count of TRDC_MBC2_MBC_DOM5_MEM1_BLK_CFG_W */ +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_CFG_W_COUNT2 (1U) + +/*! @name MBC_DOM5_MEM1_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ +/*! @{ */ + +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT0_MASK (0x1U) +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT0_SHIFT (0U) +/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT0_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT1_MASK (0x2U) +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT1_SHIFT (1U) +/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT1_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT2_MASK (0x4U) +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT2_SHIFT (2U) +/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT2_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT3_MASK (0x8U) +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT3_SHIFT (3U) +/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT3_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT4_MASK (0x10U) +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT4_SHIFT (4U) +/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT4_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT5_MASK (0x20U) +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT5_SHIFT (5U) +/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT5_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT6_MASK (0x40U) +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT6_SHIFT (6U) +/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT6_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT7_MASK (0x80U) +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT7_SHIFT (7U) +/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT7_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT8_MASK (0x100U) +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT8_SHIFT (8U) +/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT8_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT9_MASK (0x200U) +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT9_SHIFT (9U) +/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT9_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT10_MASK (0x400U) +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT10_SHIFT (10U) +/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT10_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT11_MASK (0x800U) +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT11_SHIFT (11U) +/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT11_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT12_MASK (0x1000U) +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT12_SHIFT (12U) +/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT12_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT13_MASK (0x2000U) +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT13_SHIFT (13U) +/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT13_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT14_MASK (0x4000U) +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT14_SHIFT (14U) +/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT14_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT15_MASK (0x8000U) +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT15_SHIFT (15U) +/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT15_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT16_MASK (0x10000U) +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT16_SHIFT (16U) +/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT16_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT17_MASK (0x20000U) +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT17_SHIFT (17U) +/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT17_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT18_MASK (0x40000U) +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT18_SHIFT (18U) +/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT18_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT19_MASK (0x80000U) +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT19_SHIFT (19U) +/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT19_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT20_MASK (0x100000U) +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT20_SHIFT (20U) +/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT20_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT21_MASK (0x200000U) +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT21_SHIFT (21U) +/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT21_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT22_MASK (0x400000U) +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT22_SHIFT (22U) +/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT22_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT23_MASK (0x800000U) +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT23_SHIFT (23U) +/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT23_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT24_MASK (0x1000000U) +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT24_SHIFT (24U) +/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT24_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT25_MASK (0x2000000U) +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT25_SHIFT (25U) +/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT25_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT26_MASK (0x4000000U) +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT26_SHIFT (26U) +/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT26_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT27_MASK (0x8000000U) +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT27_SHIFT (27U) +/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT27_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT28_MASK (0x10000000U) +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT28_SHIFT (28U) +/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT28_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT29_MASK (0x20000000U) +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT29_SHIFT (29U) +/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT29_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT30_MASK (0x40000000U) +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT30_SHIFT (30U) +/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT30_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT31_MASK (0x80000000U) +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT31_SHIFT (31U) +/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_BIT31_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W */ +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_COUNT (2U) + +/* The count of TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W */ +#define TRDC_MBC2_MBC_DOM5_MEM1_BLK_NSE_W_COUNT2 (1U) + +/*! @name MBC_DOM5_MEM2_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM2_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM2_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM2_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM2_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM2_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM2_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM2_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM2_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM2_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM2_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM2_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM2_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM2_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM2_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM2_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM2_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM2_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM2_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM2_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM2_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM2_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM2_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM2_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM2_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM2_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM2_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM2_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM2_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM2_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM2_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM2_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM2_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MBC_DOM5_MEM2_BLK_CFG_W */ +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_CFG_W_COUNT (2U) + +/* The count of TRDC_MBC2_MBC_DOM5_MEM2_BLK_CFG_W */ +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_CFG_W_COUNT2 (1U) + +/*! @name MBC_DOM5_MEM2_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ +/*! @{ */ + +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT0_MASK (0x1U) +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT0_SHIFT (0U) +/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT0_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT1_MASK (0x2U) +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT1_SHIFT (1U) +/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT1_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT2_MASK (0x4U) +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT2_SHIFT (2U) +/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT2_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT3_MASK (0x8U) +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT3_SHIFT (3U) +/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT3_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT4_MASK (0x10U) +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT4_SHIFT (4U) +/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT4_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT5_MASK (0x20U) +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT5_SHIFT (5U) +/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT5_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT6_MASK (0x40U) +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT6_SHIFT (6U) +/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT6_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT7_MASK (0x80U) +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT7_SHIFT (7U) +/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT7_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT8_MASK (0x100U) +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT8_SHIFT (8U) +/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT8_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT9_MASK (0x200U) +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT9_SHIFT (9U) +/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT9_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT10_MASK (0x400U) +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT10_SHIFT (10U) +/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT10_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT11_MASK (0x800U) +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT11_SHIFT (11U) +/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT11_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT12_MASK (0x1000U) +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT12_SHIFT (12U) +/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT12_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT13_MASK (0x2000U) +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT13_SHIFT (13U) +/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT13_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT14_MASK (0x4000U) +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT14_SHIFT (14U) +/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT14_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT15_MASK (0x8000U) +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT15_SHIFT (15U) +/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT15_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT16_MASK (0x10000U) +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT16_SHIFT (16U) +/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT16_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT17_MASK (0x20000U) +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT17_SHIFT (17U) +/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT17_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT18_MASK (0x40000U) +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT18_SHIFT (18U) +/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT18_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT19_MASK (0x80000U) +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT19_SHIFT (19U) +/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT19_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT20_MASK (0x100000U) +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT20_SHIFT (20U) +/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT20_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT21_MASK (0x200000U) +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT21_SHIFT (21U) +/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT21_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT22_MASK (0x400000U) +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT22_SHIFT (22U) +/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT22_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT23_MASK (0x800000U) +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT23_SHIFT (23U) +/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT23_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT24_MASK (0x1000000U) +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT24_SHIFT (24U) +/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT24_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT25_MASK (0x2000000U) +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT25_SHIFT (25U) +/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT25_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT26_MASK (0x4000000U) +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT26_SHIFT (26U) +/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT26_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT27_MASK (0x8000000U) +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT27_SHIFT (27U) +/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT27_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT28_MASK (0x10000000U) +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT28_SHIFT (28U) +/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT28_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT29_MASK (0x20000000U) +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT29_SHIFT (29U) +/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT29_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT30_MASK (0x40000000U) +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT30_SHIFT (30U) +/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT30_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT31_MASK (0x80000000U) +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT31_SHIFT (31U) +/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_BIT31_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W */ +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_COUNT (2U) + +/* The count of TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W */ +#define TRDC_MBC2_MBC_DOM5_MEM2_BLK_NSE_W_COUNT2 (1U) + +/*! @name MBC_DOM5_MEM3_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM3_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM3_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM3_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM3_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM3_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM3_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM3_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM3_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM3_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM3_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM3_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM3_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM3_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM3_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM3_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM3_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM3_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM3_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM3_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM3_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM3_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM3_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM3_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM3_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM3_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM3_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM3_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM3_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM3_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM3_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM3_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM3_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MBC_DOM5_MEM3_BLK_CFG_W */ +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_CFG_W_COUNT (2U) + +/* The count of TRDC_MBC2_MBC_DOM5_MEM3_BLK_CFG_W */ +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_CFG_W_COUNT2 (3U) + +/*! @name MBC_DOM5_MEM3_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ +/*! @{ */ + +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT0_MASK (0x1U) +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT0_SHIFT (0U) +/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT0_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT1_MASK (0x2U) +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT1_SHIFT (1U) +/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT1_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT2_MASK (0x4U) +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT2_SHIFT (2U) +/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT2_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT3_MASK (0x8U) +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT3_SHIFT (3U) +/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT3_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT4_MASK (0x10U) +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT4_SHIFT (4U) +/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT4_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT5_MASK (0x20U) +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT5_SHIFT (5U) +/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT5_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT6_MASK (0x40U) +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT6_SHIFT (6U) +/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT6_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT7_MASK (0x80U) +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT7_SHIFT (7U) +/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT7_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT8_MASK (0x100U) +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT8_SHIFT (8U) +/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT8_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT9_MASK (0x200U) +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT9_SHIFT (9U) +/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT9_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT10_MASK (0x400U) +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT10_SHIFT (10U) +/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT10_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT11_MASK (0x800U) +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT11_SHIFT (11U) +/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT11_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT12_MASK (0x1000U) +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT12_SHIFT (12U) +/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT12_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT13_MASK (0x2000U) +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT13_SHIFT (13U) +/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT13_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT14_MASK (0x4000U) +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT14_SHIFT (14U) +/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT14_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT15_MASK (0x8000U) +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT15_SHIFT (15U) +/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT15_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT16_MASK (0x10000U) +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT16_SHIFT (16U) +/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT16_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT17_MASK (0x20000U) +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT17_SHIFT (17U) +/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT17_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT18_MASK (0x40000U) +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT18_SHIFT (18U) +/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT18_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT19_MASK (0x80000U) +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT19_SHIFT (19U) +/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT19_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT20_MASK (0x100000U) +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT20_SHIFT (20U) +/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT20_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT21_MASK (0x200000U) +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT21_SHIFT (21U) +/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT21_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT22_MASK (0x400000U) +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT22_SHIFT (22U) +/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT22_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT23_MASK (0x800000U) +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT23_SHIFT (23U) +/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT23_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT24_MASK (0x1000000U) +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT24_SHIFT (24U) +/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT24_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT25_MASK (0x2000000U) +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT25_SHIFT (25U) +/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT25_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT26_MASK (0x4000000U) +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT26_SHIFT (26U) +/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT26_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT27_MASK (0x8000000U) +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT27_SHIFT (27U) +/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT27_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT28_MASK (0x10000000U) +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT28_SHIFT (28U) +/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT28_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT29_MASK (0x20000000U) +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT29_SHIFT (29U) +/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT29_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT30_MASK (0x40000000U) +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT30_SHIFT (30U) +/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT30_MASK) + +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT31_MASK (0x80000000U) +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT31_SHIFT (31U) +/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_BIT31_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W */ +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_COUNT (2U) + +/* The count of TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W */ +#define TRDC_MBC2_MBC_DOM5_MEM3_BLK_NSE_W_COUNT2 (1U) + +/*! @name MBC_DOM6_MEM0_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM0_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM0_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM0_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM0_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM0_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM0_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM0_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM0_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM0_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM0_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM0_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM0_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM0_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM0_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM0_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM0_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM0_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM0_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM0_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM0_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM0_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM0_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM0_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM0_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM0_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM0_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM0_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM0_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM0_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM0_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM0_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM0_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MBC_DOM6_MEM0_BLK_CFG_W */ +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_CFG_W_COUNT (2U) + +/* The count of TRDC_MBC2_MBC_DOM6_MEM0_BLK_CFG_W */ +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_CFG_W_COUNT2 (16U) + +/*! @name MBC_DOM6_MEM0_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ +/*! @{ */ + +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT0_MASK (0x1U) +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT0_SHIFT (0U) +/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT0_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT1_MASK (0x2U) +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT1_SHIFT (1U) +/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT1_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT2_MASK (0x4U) +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT2_SHIFT (2U) +/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT2_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT3_MASK (0x8U) +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT3_SHIFT (3U) +/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT3_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT4_MASK (0x10U) +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT4_SHIFT (4U) +/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT4_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT5_MASK (0x20U) +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT5_SHIFT (5U) +/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT5_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT6_MASK (0x40U) +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT6_SHIFT (6U) +/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT6_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT7_MASK (0x80U) +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT7_SHIFT (7U) +/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT7_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT8_MASK (0x100U) +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT8_SHIFT (8U) +/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT8_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT9_MASK (0x200U) +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT9_SHIFT (9U) +/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT9_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT10_MASK (0x400U) +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT10_SHIFT (10U) +/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT10_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT11_MASK (0x800U) +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT11_SHIFT (11U) +/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT11_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT12_MASK (0x1000U) +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT12_SHIFT (12U) +/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT12_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT13_MASK (0x2000U) +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT13_SHIFT (13U) +/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT13_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT14_MASK (0x4000U) +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT14_SHIFT (14U) +/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT14_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT15_MASK (0x8000U) +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT15_SHIFT (15U) +/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT15_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT16_MASK (0x10000U) +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT16_SHIFT (16U) +/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT16_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT17_MASK (0x20000U) +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT17_SHIFT (17U) +/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT17_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT18_MASK (0x40000U) +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT18_SHIFT (18U) +/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT18_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT19_MASK (0x80000U) +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT19_SHIFT (19U) +/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT19_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT20_MASK (0x100000U) +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT20_SHIFT (20U) +/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT20_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT21_MASK (0x200000U) +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT21_SHIFT (21U) +/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT21_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT22_MASK (0x400000U) +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT22_SHIFT (22U) +/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT22_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT23_MASK (0x800000U) +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT23_SHIFT (23U) +/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT23_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT24_MASK (0x1000000U) +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT24_SHIFT (24U) +/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT24_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT25_MASK (0x2000000U) +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT25_SHIFT (25U) +/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT25_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT26_MASK (0x4000000U) +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT26_SHIFT (26U) +/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT26_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT27_MASK (0x8000000U) +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT27_SHIFT (27U) +/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT27_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT28_MASK (0x10000000U) +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT28_SHIFT (28U) +/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT28_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT29_MASK (0x20000000U) +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT29_SHIFT (29U) +/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT29_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT30_MASK (0x40000000U) +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT30_SHIFT (30U) +/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT30_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT31_MASK (0x80000000U) +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT31_SHIFT (31U) +/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_BIT31_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W */ +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_COUNT (2U) + +/* The count of TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W */ +#define TRDC_MBC2_MBC_DOM6_MEM0_BLK_NSE_W_COUNT2 (4U) + +/*! @name MBC_DOM6_MEM1_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM1_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM1_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM1_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM1_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM1_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM1_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM1_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM1_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM1_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM1_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM1_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM1_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM1_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM1_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM1_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM1_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM1_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM1_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM1_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM1_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM1_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM1_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM1_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM1_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM1_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM1_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM1_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM1_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM1_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM1_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM1_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM1_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MBC_DOM6_MEM1_BLK_CFG_W */ +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_CFG_W_COUNT (2U) + +/* The count of TRDC_MBC2_MBC_DOM6_MEM1_BLK_CFG_W */ +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_CFG_W_COUNT2 (1U) + +/*! @name MBC_DOM6_MEM1_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ +/*! @{ */ + +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT0_MASK (0x1U) +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT0_SHIFT (0U) +/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT0_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT1_MASK (0x2U) +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT1_SHIFT (1U) +/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT1_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT2_MASK (0x4U) +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT2_SHIFT (2U) +/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT2_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT3_MASK (0x8U) +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT3_SHIFT (3U) +/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT3_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT4_MASK (0x10U) +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT4_SHIFT (4U) +/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT4_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT5_MASK (0x20U) +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT5_SHIFT (5U) +/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT5_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT6_MASK (0x40U) +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT6_SHIFT (6U) +/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT6_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT7_MASK (0x80U) +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT7_SHIFT (7U) +/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT7_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT8_MASK (0x100U) +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT8_SHIFT (8U) +/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT8_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT9_MASK (0x200U) +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT9_SHIFT (9U) +/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT9_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT10_MASK (0x400U) +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT10_SHIFT (10U) +/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT10_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT11_MASK (0x800U) +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT11_SHIFT (11U) +/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT11_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT12_MASK (0x1000U) +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT12_SHIFT (12U) +/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT12_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT13_MASK (0x2000U) +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT13_SHIFT (13U) +/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT13_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT14_MASK (0x4000U) +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT14_SHIFT (14U) +/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT14_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT15_MASK (0x8000U) +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT15_SHIFT (15U) +/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT15_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT16_MASK (0x10000U) +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT16_SHIFT (16U) +/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT16_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT17_MASK (0x20000U) +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT17_SHIFT (17U) +/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT17_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT18_MASK (0x40000U) +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT18_SHIFT (18U) +/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT18_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT19_MASK (0x80000U) +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT19_SHIFT (19U) +/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT19_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT20_MASK (0x100000U) +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT20_SHIFT (20U) +/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT20_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT21_MASK (0x200000U) +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT21_SHIFT (21U) +/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT21_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT22_MASK (0x400000U) +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT22_SHIFT (22U) +/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT22_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT23_MASK (0x800000U) +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT23_SHIFT (23U) +/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT23_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT24_MASK (0x1000000U) +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT24_SHIFT (24U) +/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT24_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT25_MASK (0x2000000U) +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT25_SHIFT (25U) +/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT25_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT26_MASK (0x4000000U) +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT26_SHIFT (26U) +/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT26_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT27_MASK (0x8000000U) +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT27_SHIFT (27U) +/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT27_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT28_MASK (0x10000000U) +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT28_SHIFT (28U) +/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT28_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT29_MASK (0x20000000U) +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT29_SHIFT (29U) +/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT29_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT30_MASK (0x40000000U) +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT30_SHIFT (30U) +/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT30_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT31_MASK (0x80000000U) +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT31_SHIFT (31U) +/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_BIT31_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W */ +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_COUNT (2U) + +/* The count of TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W */ +#define TRDC_MBC2_MBC_DOM6_MEM1_BLK_NSE_W_COUNT2 (1U) + +/*! @name MBC_DOM6_MEM2_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM2_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM2_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM2_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM2_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM2_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM2_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM2_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM2_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM2_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM2_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM2_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM2_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM2_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM2_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM2_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM2_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM2_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM2_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM2_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM2_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM2_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM2_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM2_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM2_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM2_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM2_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM2_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM2_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM2_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM2_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM2_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM2_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MBC_DOM6_MEM2_BLK_CFG_W */ +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_CFG_W_COUNT (2U) + +/* The count of TRDC_MBC2_MBC_DOM6_MEM2_BLK_CFG_W */ +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_CFG_W_COUNT2 (1U) + +/*! @name MBC_DOM6_MEM2_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ +/*! @{ */ + +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT0_MASK (0x1U) +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT0_SHIFT (0U) +/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT0_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT1_MASK (0x2U) +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT1_SHIFT (1U) +/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT1_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT2_MASK (0x4U) +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT2_SHIFT (2U) +/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT2_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT3_MASK (0x8U) +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT3_SHIFT (3U) +/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT3_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT4_MASK (0x10U) +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT4_SHIFT (4U) +/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT4_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT5_MASK (0x20U) +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT5_SHIFT (5U) +/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT5_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT6_MASK (0x40U) +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT6_SHIFT (6U) +/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT6_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT7_MASK (0x80U) +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT7_SHIFT (7U) +/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT7_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT8_MASK (0x100U) +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT8_SHIFT (8U) +/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT8_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT9_MASK (0x200U) +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT9_SHIFT (9U) +/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT9_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT10_MASK (0x400U) +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT10_SHIFT (10U) +/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT10_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT11_MASK (0x800U) +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT11_SHIFT (11U) +/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT11_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT12_MASK (0x1000U) +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT12_SHIFT (12U) +/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT12_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT13_MASK (0x2000U) +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT13_SHIFT (13U) +/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT13_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT14_MASK (0x4000U) +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT14_SHIFT (14U) +/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT14_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT15_MASK (0x8000U) +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT15_SHIFT (15U) +/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT15_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT16_MASK (0x10000U) +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT16_SHIFT (16U) +/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT16_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT17_MASK (0x20000U) +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT17_SHIFT (17U) +/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT17_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT18_MASK (0x40000U) +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT18_SHIFT (18U) +/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT18_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT19_MASK (0x80000U) +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT19_SHIFT (19U) +/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT19_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT20_MASK (0x100000U) +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT20_SHIFT (20U) +/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT20_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT21_MASK (0x200000U) +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT21_SHIFT (21U) +/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT21_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT22_MASK (0x400000U) +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT22_SHIFT (22U) +/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT22_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT23_MASK (0x800000U) +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT23_SHIFT (23U) +/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT23_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT24_MASK (0x1000000U) +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT24_SHIFT (24U) +/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT24_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT25_MASK (0x2000000U) +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT25_SHIFT (25U) +/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT25_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT26_MASK (0x4000000U) +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT26_SHIFT (26U) +/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT26_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT27_MASK (0x8000000U) +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT27_SHIFT (27U) +/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT27_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT28_MASK (0x10000000U) +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT28_SHIFT (28U) +/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT28_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT29_MASK (0x20000000U) +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT29_SHIFT (29U) +/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT29_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT30_MASK (0x40000000U) +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT30_SHIFT (30U) +/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT30_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT31_MASK (0x80000000U) +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT31_SHIFT (31U) +/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_BIT31_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W */ +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_COUNT (2U) + +/* The count of TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W */ +#define TRDC_MBC2_MBC_DOM6_MEM2_BLK_NSE_W_COUNT2 (1U) + +/*! @name MBC_DOM6_MEM3_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM3_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM3_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM3_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM3_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM3_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM3_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM3_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM3_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM3_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM3_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM3_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM3_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM3_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM3_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM3_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM3_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM3_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM3_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM3_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM3_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM3_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM3_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM3_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM3_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM3_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM3_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM3_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM3_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM3_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM3_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM3_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM3_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MBC_DOM6_MEM3_BLK_CFG_W */ +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_CFG_W_COUNT (2U) + +/* The count of TRDC_MBC2_MBC_DOM6_MEM3_BLK_CFG_W */ +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_CFG_W_COUNT2 (3U) + +/*! @name MBC_DOM6_MEM3_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ +/*! @{ */ + +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT0_MASK (0x1U) +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT0_SHIFT (0U) +/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT0_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT1_MASK (0x2U) +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT1_SHIFT (1U) +/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT1_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT2_MASK (0x4U) +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT2_SHIFT (2U) +/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT2_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT3_MASK (0x8U) +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT3_SHIFT (3U) +/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT3_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT4_MASK (0x10U) +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT4_SHIFT (4U) +/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT4_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT5_MASK (0x20U) +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT5_SHIFT (5U) +/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT5_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT6_MASK (0x40U) +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT6_SHIFT (6U) +/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT6_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT7_MASK (0x80U) +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT7_SHIFT (7U) +/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT7_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT8_MASK (0x100U) +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT8_SHIFT (8U) +/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT8_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT9_MASK (0x200U) +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT9_SHIFT (9U) +/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT9_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT10_MASK (0x400U) +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT10_SHIFT (10U) +/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT10_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT11_MASK (0x800U) +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT11_SHIFT (11U) +/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT11_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT12_MASK (0x1000U) +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT12_SHIFT (12U) +/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT12_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT13_MASK (0x2000U) +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT13_SHIFT (13U) +/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT13_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT14_MASK (0x4000U) +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT14_SHIFT (14U) +/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT14_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT15_MASK (0x8000U) +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT15_SHIFT (15U) +/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT15_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT16_MASK (0x10000U) +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT16_SHIFT (16U) +/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT16_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT17_MASK (0x20000U) +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT17_SHIFT (17U) +/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT17_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT18_MASK (0x40000U) +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT18_SHIFT (18U) +/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT18_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT19_MASK (0x80000U) +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT19_SHIFT (19U) +/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT19_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT20_MASK (0x100000U) +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT20_SHIFT (20U) +/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT20_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT21_MASK (0x200000U) +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT21_SHIFT (21U) +/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT21_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT22_MASK (0x400000U) +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT22_SHIFT (22U) +/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT22_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT23_MASK (0x800000U) +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT23_SHIFT (23U) +/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT23_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT24_MASK (0x1000000U) +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT24_SHIFT (24U) +/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT24_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT25_MASK (0x2000000U) +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT25_SHIFT (25U) +/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT25_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT26_MASK (0x4000000U) +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT26_SHIFT (26U) +/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT26_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT27_MASK (0x8000000U) +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT27_SHIFT (27U) +/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT27_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT28_MASK (0x10000000U) +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT28_SHIFT (28U) +/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT28_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT29_MASK (0x20000000U) +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT29_SHIFT (29U) +/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT29_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT30_MASK (0x40000000U) +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT30_SHIFT (30U) +/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT30_MASK) + +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT31_MASK (0x80000000U) +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT31_SHIFT (31U) +/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_BIT31_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W */ +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_COUNT (2U) + +/* The count of TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W */ +#define TRDC_MBC2_MBC_DOM6_MEM3_BLK_NSE_W_COUNT2 (1U) + +/*! @name MBC_DOM7_MEM0_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM0_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM0_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM0_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM0_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM0_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM0_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM0_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM0_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM0_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM0_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM0_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM0_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM0_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM0_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM0_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM0_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM0_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM0_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM0_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM0_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM0_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM0_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM0_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM0_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM0_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM0_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM0_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM0_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM0_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM0_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM0_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM0_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MBC_DOM7_MEM0_BLK_CFG_W */ +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_CFG_W_COUNT (2U) + +/* The count of TRDC_MBC2_MBC_DOM7_MEM0_BLK_CFG_W */ +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_CFG_W_COUNT2 (16U) + +/*! @name MBC_DOM7_MEM0_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ +/*! @{ */ + +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT0_MASK (0x1U) +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT0_SHIFT (0U) +/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT0_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT1_MASK (0x2U) +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT1_SHIFT (1U) +/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT1_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT2_MASK (0x4U) +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT2_SHIFT (2U) +/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT2_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT3_MASK (0x8U) +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT3_SHIFT (3U) +/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT3_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT4_MASK (0x10U) +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT4_SHIFT (4U) +/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT4_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT5_MASK (0x20U) +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT5_SHIFT (5U) +/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT5_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT6_MASK (0x40U) +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT6_SHIFT (6U) +/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT6_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT7_MASK (0x80U) +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT7_SHIFT (7U) +/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT7_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT8_MASK (0x100U) +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT8_SHIFT (8U) +/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT8_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT9_MASK (0x200U) +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT9_SHIFT (9U) +/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT9_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT10_MASK (0x400U) +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT10_SHIFT (10U) +/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT10_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT11_MASK (0x800U) +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT11_SHIFT (11U) +/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT11_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT12_MASK (0x1000U) +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT12_SHIFT (12U) +/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT12_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT13_MASK (0x2000U) +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT13_SHIFT (13U) +/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT13_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT14_MASK (0x4000U) +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT14_SHIFT (14U) +/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT14_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT15_MASK (0x8000U) +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT15_SHIFT (15U) +/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT15_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT16_MASK (0x10000U) +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT16_SHIFT (16U) +/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT16_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT17_MASK (0x20000U) +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT17_SHIFT (17U) +/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT17_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT18_MASK (0x40000U) +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT18_SHIFT (18U) +/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT18_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT19_MASK (0x80000U) +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT19_SHIFT (19U) +/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT19_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT20_MASK (0x100000U) +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT20_SHIFT (20U) +/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT20_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT21_MASK (0x200000U) +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT21_SHIFT (21U) +/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT21_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT22_MASK (0x400000U) +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT22_SHIFT (22U) +/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT22_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT23_MASK (0x800000U) +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT23_SHIFT (23U) +/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT23_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT24_MASK (0x1000000U) +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT24_SHIFT (24U) +/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT24_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT25_MASK (0x2000000U) +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT25_SHIFT (25U) +/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT25_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT26_MASK (0x4000000U) +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT26_SHIFT (26U) +/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT26_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT27_MASK (0x8000000U) +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT27_SHIFT (27U) +/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT27_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT28_MASK (0x10000000U) +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT28_SHIFT (28U) +/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT28_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT29_MASK (0x20000000U) +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT29_SHIFT (29U) +/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT29_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT30_MASK (0x40000000U) +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT30_SHIFT (30U) +/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT30_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT31_MASK (0x80000000U) +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT31_SHIFT (31U) +/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_BIT31_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W */ +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_COUNT (2U) + +/* The count of TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W */ +#define TRDC_MBC2_MBC_DOM7_MEM0_BLK_NSE_W_COUNT2 (4U) + +/*! @name MBC_DOM7_MEM1_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM1_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM1_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM1_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM1_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM1_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM1_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM1_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM1_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM1_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM1_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM1_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM1_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM1_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM1_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM1_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM1_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM1_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM1_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM1_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM1_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM1_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM1_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM1_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM1_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM1_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM1_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM1_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM1_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM1_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM1_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM1_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM1_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MBC_DOM7_MEM1_BLK_CFG_W */ +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_CFG_W_COUNT (2U) + +/* The count of TRDC_MBC2_MBC_DOM7_MEM1_BLK_CFG_W */ +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_CFG_W_COUNT2 (1U) + +/*! @name MBC_DOM7_MEM1_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ +/*! @{ */ + +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT0_MASK (0x1U) +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT0_SHIFT (0U) +/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT0_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT1_MASK (0x2U) +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT1_SHIFT (1U) +/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT1_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT2_MASK (0x4U) +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT2_SHIFT (2U) +/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT2_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT3_MASK (0x8U) +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT3_SHIFT (3U) +/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT3_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT4_MASK (0x10U) +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT4_SHIFT (4U) +/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT4_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT5_MASK (0x20U) +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT5_SHIFT (5U) +/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT5_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT6_MASK (0x40U) +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT6_SHIFT (6U) +/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT6_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT7_MASK (0x80U) +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT7_SHIFT (7U) +/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT7_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT8_MASK (0x100U) +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT8_SHIFT (8U) +/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT8_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT9_MASK (0x200U) +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT9_SHIFT (9U) +/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT9_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT10_MASK (0x400U) +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT10_SHIFT (10U) +/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT10_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT11_MASK (0x800U) +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT11_SHIFT (11U) +/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT11_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT12_MASK (0x1000U) +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT12_SHIFT (12U) +/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT12_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT13_MASK (0x2000U) +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT13_SHIFT (13U) +/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT13_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT14_MASK (0x4000U) +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT14_SHIFT (14U) +/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT14_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT15_MASK (0x8000U) +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT15_SHIFT (15U) +/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT15_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT16_MASK (0x10000U) +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT16_SHIFT (16U) +/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT16_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT17_MASK (0x20000U) +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT17_SHIFT (17U) +/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT17_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT18_MASK (0x40000U) +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT18_SHIFT (18U) +/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT18_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT19_MASK (0x80000U) +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT19_SHIFT (19U) +/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT19_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT20_MASK (0x100000U) +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT20_SHIFT (20U) +/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT20_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT21_MASK (0x200000U) +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT21_SHIFT (21U) +/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT21_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT22_MASK (0x400000U) +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT22_SHIFT (22U) +/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT22_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT23_MASK (0x800000U) +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT23_SHIFT (23U) +/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT23_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT24_MASK (0x1000000U) +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT24_SHIFT (24U) +/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT24_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT25_MASK (0x2000000U) +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT25_SHIFT (25U) +/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT25_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT26_MASK (0x4000000U) +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT26_SHIFT (26U) +/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT26_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT27_MASK (0x8000000U) +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT27_SHIFT (27U) +/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT27_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT28_MASK (0x10000000U) +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT28_SHIFT (28U) +/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT28_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT29_MASK (0x20000000U) +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT29_SHIFT (29U) +/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT29_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT30_MASK (0x40000000U) +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT30_SHIFT (30U) +/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT30_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT31_MASK (0x80000000U) +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT31_SHIFT (31U) +/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_BIT31_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W */ +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_COUNT (2U) + +/* The count of TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W */ +#define TRDC_MBC2_MBC_DOM7_MEM1_BLK_NSE_W_COUNT2 (1U) + +/*! @name MBC_DOM7_MEM2_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM2_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM2_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM2_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM2_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM2_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM2_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM2_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM2_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM2_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM2_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM2_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM2_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM2_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM2_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM2_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM2_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM2_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM2_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM2_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM2_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM2_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM2_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM2_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM2_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM2_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM2_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM2_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM2_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM2_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM2_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM2_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM2_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MBC_DOM7_MEM2_BLK_CFG_W */ +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_CFG_W_COUNT (2U) + +/* The count of TRDC_MBC2_MBC_DOM7_MEM2_BLK_CFG_W */ +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_CFG_W_COUNT2 (1U) + +/*! @name MBC_DOM7_MEM2_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ +/*! @{ */ + +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT0_MASK (0x1U) +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT0_SHIFT (0U) +/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT0_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT1_MASK (0x2U) +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT1_SHIFT (1U) +/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT1_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT2_MASK (0x4U) +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT2_SHIFT (2U) +/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT2_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT3_MASK (0x8U) +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT3_SHIFT (3U) +/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT3_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT4_MASK (0x10U) +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT4_SHIFT (4U) +/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT4_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT5_MASK (0x20U) +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT5_SHIFT (5U) +/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT5_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT6_MASK (0x40U) +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT6_SHIFT (6U) +/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT6_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT7_MASK (0x80U) +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT7_SHIFT (7U) +/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT7_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT8_MASK (0x100U) +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT8_SHIFT (8U) +/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT8_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT9_MASK (0x200U) +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT9_SHIFT (9U) +/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT9_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT10_MASK (0x400U) +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT10_SHIFT (10U) +/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT10_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT11_MASK (0x800U) +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT11_SHIFT (11U) +/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT11_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT12_MASK (0x1000U) +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT12_SHIFT (12U) +/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT12_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT13_MASK (0x2000U) +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT13_SHIFT (13U) +/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT13_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT14_MASK (0x4000U) +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT14_SHIFT (14U) +/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT14_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT15_MASK (0x8000U) +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT15_SHIFT (15U) +/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT15_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT16_MASK (0x10000U) +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT16_SHIFT (16U) +/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT16_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT17_MASK (0x20000U) +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT17_SHIFT (17U) +/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT17_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT18_MASK (0x40000U) +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT18_SHIFT (18U) +/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT18_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT19_MASK (0x80000U) +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT19_SHIFT (19U) +/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT19_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT20_MASK (0x100000U) +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT20_SHIFT (20U) +/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT20_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT21_MASK (0x200000U) +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT21_SHIFT (21U) +/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT21_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT22_MASK (0x400000U) +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT22_SHIFT (22U) +/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT22_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT23_MASK (0x800000U) +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT23_SHIFT (23U) +/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT23_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT24_MASK (0x1000000U) +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT24_SHIFT (24U) +/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT24_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT25_MASK (0x2000000U) +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT25_SHIFT (25U) +/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT25_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT26_MASK (0x4000000U) +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT26_SHIFT (26U) +/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT26_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT27_MASK (0x8000000U) +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT27_SHIFT (27U) +/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT27_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT28_MASK (0x10000000U) +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT28_SHIFT (28U) +/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT28_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT29_MASK (0x20000000U) +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT29_SHIFT (29U) +/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT29_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT30_MASK (0x40000000U) +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT30_SHIFT (30U) +/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT30_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT31_MASK (0x80000000U) +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT31_SHIFT (31U) +/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_BIT31_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W */ +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_COUNT (2U) + +/* The count of TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W */ +#define TRDC_MBC2_MBC_DOM7_MEM2_BLK_NSE_W_COUNT2 (1U) + +/*! @name MBC_DOM7_MEM3_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM3_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM3_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM3_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM3_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM3_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM3_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM3_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM3_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM3_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM3_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM3_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM3_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM3_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM3_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM3_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM3_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM3_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM3_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM3_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM3_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM3_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM3_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM3_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM3_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM3_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM3_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM3_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM3_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM3_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM3_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM3_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM3_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MBC_DOM7_MEM3_BLK_CFG_W */ +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_CFG_W_COUNT (2U) + +/* The count of TRDC_MBC2_MBC_DOM7_MEM3_BLK_CFG_W */ +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_CFG_W_COUNT2 (3U) + +/*! @name MBC_DOM7_MEM3_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ +/*! @{ */ + +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT0_MASK (0x1U) +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT0_SHIFT (0U) +/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT0_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT1_MASK (0x2U) +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT1_SHIFT (1U) +/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT1_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT2_MASK (0x4U) +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT2_SHIFT (2U) +/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT2_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT3_MASK (0x8U) +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT3_SHIFT (3U) +/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT3_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT4_MASK (0x10U) +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT4_SHIFT (4U) +/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT4_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT5_MASK (0x20U) +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT5_SHIFT (5U) +/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT5_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT6_MASK (0x40U) +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT6_SHIFT (6U) +/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT6_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT7_MASK (0x80U) +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT7_SHIFT (7U) +/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT7_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT8_MASK (0x100U) +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT8_SHIFT (8U) +/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT8_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT9_MASK (0x200U) +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT9_SHIFT (9U) +/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT9_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT10_MASK (0x400U) +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT10_SHIFT (10U) +/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT10_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT11_MASK (0x800U) +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT11_SHIFT (11U) +/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT11_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT12_MASK (0x1000U) +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT12_SHIFT (12U) +/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT12_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT13_MASK (0x2000U) +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT13_SHIFT (13U) +/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT13_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT14_MASK (0x4000U) +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT14_SHIFT (14U) +/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT14_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT15_MASK (0x8000U) +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT15_SHIFT (15U) +/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT15_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT16_MASK (0x10000U) +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT16_SHIFT (16U) +/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT16_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT17_MASK (0x20000U) +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT17_SHIFT (17U) +/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT17_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT18_MASK (0x40000U) +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT18_SHIFT (18U) +/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT18_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT19_MASK (0x80000U) +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT19_SHIFT (19U) +/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT19_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT20_MASK (0x100000U) +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT20_SHIFT (20U) +/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT20_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT21_MASK (0x200000U) +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT21_SHIFT (21U) +/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT21_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT22_MASK (0x400000U) +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT22_SHIFT (22U) +/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT22_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT23_MASK (0x800000U) +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT23_SHIFT (23U) +/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT23_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT24_MASK (0x1000000U) +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT24_SHIFT (24U) +/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT24_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT25_MASK (0x2000000U) +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT25_SHIFT (25U) +/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT25_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT26_MASK (0x4000000U) +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT26_SHIFT (26U) +/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT26_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT27_MASK (0x8000000U) +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT27_SHIFT (27U) +/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT27_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT28_MASK (0x10000000U) +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT28_SHIFT (28U) +/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT28_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT29_MASK (0x20000000U) +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT29_SHIFT (29U) +/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT29_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT30_MASK (0x40000000U) +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT30_SHIFT (30U) +/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT30_MASK) + +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT31_MASK (0x80000000U) +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT31_SHIFT (31U) +/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_BIT31_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W */ +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_COUNT (2U) + +/* The count of TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W */ +#define TRDC_MBC2_MBC_DOM7_MEM3_BLK_NSE_W_COUNT2 (1U) + +/*! @name MBC_DOM8_MEM0_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM0_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM0_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM0_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM0_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM0_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM0_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM0_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM0_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM0_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM0_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM0_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM0_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM0_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM0_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM0_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM0_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM0_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM0_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM0_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM0_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM0_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM0_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM0_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM0_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM0_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM0_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM0_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM0_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM0_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM0_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM0_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM0_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MBC_DOM8_MEM0_BLK_CFG_W */ +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_CFG_W_COUNT (2U) + +/* The count of TRDC_MBC2_MBC_DOM8_MEM0_BLK_CFG_W */ +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_CFG_W_COUNT2 (16U) + +/*! @name MBC_DOM8_MEM0_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ +/*! @{ */ + +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT0_MASK (0x1U) +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT0_SHIFT (0U) +/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT0_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT1_MASK (0x2U) +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT1_SHIFT (1U) +/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT1_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT2_MASK (0x4U) +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT2_SHIFT (2U) +/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT2_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT3_MASK (0x8U) +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT3_SHIFT (3U) +/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT3_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT4_MASK (0x10U) +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT4_SHIFT (4U) +/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT4_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT5_MASK (0x20U) +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT5_SHIFT (5U) +/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT5_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT6_MASK (0x40U) +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT6_SHIFT (6U) +/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT6_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT7_MASK (0x80U) +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT7_SHIFT (7U) +/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT7_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT8_MASK (0x100U) +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT8_SHIFT (8U) +/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT8_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT9_MASK (0x200U) +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT9_SHIFT (9U) +/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT9_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT10_MASK (0x400U) +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT10_SHIFT (10U) +/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT10_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT11_MASK (0x800U) +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT11_SHIFT (11U) +/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT11_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT12_MASK (0x1000U) +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT12_SHIFT (12U) +/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT12_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT13_MASK (0x2000U) +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT13_SHIFT (13U) +/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT13_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT14_MASK (0x4000U) +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT14_SHIFT (14U) +/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT14_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT15_MASK (0x8000U) +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT15_SHIFT (15U) +/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT15_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT16_MASK (0x10000U) +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT16_SHIFT (16U) +/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT16_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT17_MASK (0x20000U) +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT17_SHIFT (17U) +/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT17_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT18_MASK (0x40000U) +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT18_SHIFT (18U) +/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT18_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT19_MASK (0x80000U) +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT19_SHIFT (19U) +/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT19_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT20_MASK (0x100000U) +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT20_SHIFT (20U) +/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT20_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT21_MASK (0x200000U) +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT21_SHIFT (21U) +/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT21_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT22_MASK (0x400000U) +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT22_SHIFT (22U) +/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT22_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT23_MASK (0x800000U) +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT23_SHIFT (23U) +/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT23_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT24_MASK (0x1000000U) +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT24_SHIFT (24U) +/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT24_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT25_MASK (0x2000000U) +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT25_SHIFT (25U) +/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT25_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT26_MASK (0x4000000U) +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT26_SHIFT (26U) +/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT26_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT27_MASK (0x8000000U) +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT27_SHIFT (27U) +/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT27_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT28_MASK (0x10000000U) +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT28_SHIFT (28U) +/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT28_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT29_MASK (0x20000000U) +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT29_SHIFT (29U) +/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT29_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT30_MASK (0x40000000U) +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT30_SHIFT (30U) +/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT30_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT31_MASK (0x80000000U) +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT31_SHIFT (31U) +/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_BIT31_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W */ +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_COUNT (2U) + +/* The count of TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W */ +#define TRDC_MBC2_MBC_DOM8_MEM0_BLK_NSE_W_COUNT2 (4U) + +/*! @name MBC_DOM8_MEM1_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM1_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM1_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM1_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM1_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM1_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM1_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM1_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM1_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM1_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM1_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM1_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM1_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM1_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM1_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM1_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM1_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM1_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM1_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM1_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM1_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM1_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM1_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM1_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM1_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM1_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM1_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM1_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM1_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM1_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM1_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM1_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM1_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MBC_DOM8_MEM1_BLK_CFG_W */ +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_CFG_W_COUNT (2U) + +/* The count of TRDC_MBC2_MBC_DOM8_MEM1_BLK_CFG_W */ +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_CFG_W_COUNT2 (1U) + +/*! @name MBC_DOM8_MEM1_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ +/*! @{ */ + +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT0_MASK (0x1U) +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT0_SHIFT (0U) +/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT0_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT1_MASK (0x2U) +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT1_SHIFT (1U) +/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT1_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT2_MASK (0x4U) +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT2_SHIFT (2U) +/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT2_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT3_MASK (0x8U) +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT3_SHIFT (3U) +/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT3_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT4_MASK (0x10U) +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT4_SHIFT (4U) +/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT4_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT5_MASK (0x20U) +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT5_SHIFT (5U) +/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT5_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT6_MASK (0x40U) +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT6_SHIFT (6U) +/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT6_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT7_MASK (0x80U) +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT7_SHIFT (7U) +/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT7_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT8_MASK (0x100U) +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT8_SHIFT (8U) +/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT8_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT9_MASK (0x200U) +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT9_SHIFT (9U) +/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT9_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT10_MASK (0x400U) +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT10_SHIFT (10U) +/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT10_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT11_MASK (0x800U) +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT11_SHIFT (11U) +/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT11_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT12_MASK (0x1000U) +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT12_SHIFT (12U) +/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT12_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT13_MASK (0x2000U) +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT13_SHIFT (13U) +/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT13_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT14_MASK (0x4000U) +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT14_SHIFT (14U) +/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT14_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT15_MASK (0x8000U) +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT15_SHIFT (15U) +/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT15_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT16_MASK (0x10000U) +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT16_SHIFT (16U) +/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT16_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT17_MASK (0x20000U) +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT17_SHIFT (17U) +/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT17_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT18_MASK (0x40000U) +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT18_SHIFT (18U) +/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT18_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT19_MASK (0x80000U) +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT19_SHIFT (19U) +/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT19_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT20_MASK (0x100000U) +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT20_SHIFT (20U) +/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT20_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT21_MASK (0x200000U) +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT21_SHIFT (21U) +/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT21_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT22_MASK (0x400000U) +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT22_SHIFT (22U) +/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT22_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT23_MASK (0x800000U) +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT23_SHIFT (23U) +/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT23_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT24_MASK (0x1000000U) +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT24_SHIFT (24U) +/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT24_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT25_MASK (0x2000000U) +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT25_SHIFT (25U) +/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT25_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT26_MASK (0x4000000U) +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT26_SHIFT (26U) +/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT26_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT27_MASK (0x8000000U) +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT27_SHIFT (27U) +/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT27_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT28_MASK (0x10000000U) +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT28_SHIFT (28U) +/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT28_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT29_MASK (0x20000000U) +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT29_SHIFT (29U) +/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT29_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT30_MASK (0x40000000U) +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT30_SHIFT (30U) +/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT30_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT31_MASK (0x80000000U) +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT31_SHIFT (31U) +/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_BIT31_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W */ +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_COUNT (2U) + +/* The count of TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W */ +#define TRDC_MBC2_MBC_DOM8_MEM1_BLK_NSE_W_COUNT2 (1U) + +/*! @name MBC_DOM8_MEM2_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM2_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM2_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM2_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM2_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM2_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM2_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM2_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM2_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM2_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM2_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM2_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM2_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM2_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM2_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM2_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM2_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM2_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM2_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM2_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM2_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM2_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM2_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM2_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM2_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM2_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM2_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM2_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM2_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM2_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM2_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM2_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM2_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MBC_DOM8_MEM2_BLK_CFG_W */ +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_CFG_W_COUNT (2U) + +/* The count of TRDC_MBC2_MBC_DOM8_MEM2_BLK_CFG_W */ +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_CFG_W_COUNT2 (1U) + +/*! @name MBC_DOM8_MEM2_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ +/*! @{ */ + +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT0_MASK (0x1U) +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT0_SHIFT (0U) +/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT0_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT1_MASK (0x2U) +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT1_SHIFT (1U) +/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT1_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT2_MASK (0x4U) +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT2_SHIFT (2U) +/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT2_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT3_MASK (0x8U) +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT3_SHIFT (3U) +/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT3_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT4_MASK (0x10U) +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT4_SHIFT (4U) +/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT4_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT5_MASK (0x20U) +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT5_SHIFT (5U) +/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT5_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT6_MASK (0x40U) +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT6_SHIFT (6U) +/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT6_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT7_MASK (0x80U) +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT7_SHIFT (7U) +/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT7_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT8_MASK (0x100U) +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT8_SHIFT (8U) +/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT8_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT9_MASK (0x200U) +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT9_SHIFT (9U) +/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT9_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT10_MASK (0x400U) +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT10_SHIFT (10U) +/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT10_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT11_MASK (0x800U) +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT11_SHIFT (11U) +/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT11_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT12_MASK (0x1000U) +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT12_SHIFT (12U) +/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT12_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT13_MASK (0x2000U) +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT13_SHIFT (13U) +/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT13_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT14_MASK (0x4000U) +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT14_SHIFT (14U) +/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT14_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT15_MASK (0x8000U) +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT15_SHIFT (15U) +/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT15_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT16_MASK (0x10000U) +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT16_SHIFT (16U) +/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT16_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT17_MASK (0x20000U) +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT17_SHIFT (17U) +/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT17_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT18_MASK (0x40000U) +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT18_SHIFT (18U) +/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT18_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT19_MASK (0x80000U) +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT19_SHIFT (19U) +/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT19_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT20_MASK (0x100000U) +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT20_SHIFT (20U) +/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT20_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT21_MASK (0x200000U) +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT21_SHIFT (21U) +/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT21_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT22_MASK (0x400000U) +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT22_SHIFT (22U) +/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT22_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT23_MASK (0x800000U) +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT23_SHIFT (23U) +/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT23_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT24_MASK (0x1000000U) +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT24_SHIFT (24U) +/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT24_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT25_MASK (0x2000000U) +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT25_SHIFT (25U) +/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT25_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT26_MASK (0x4000000U) +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT26_SHIFT (26U) +/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT26_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT27_MASK (0x8000000U) +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT27_SHIFT (27U) +/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT27_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT28_MASK (0x10000000U) +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT28_SHIFT (28U) +/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT28_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT29_MASK (0x20000000U) +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT29_SHIFT (29U) +/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT29_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT30_MASK (0x40000000U) +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT30_SHIFT (30U) +/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT30_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT31_MASK (0x80000000U) +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT31_SHIFT (31U) +/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_BIT31_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W */ +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_COUNT (2U) + +/* The count of TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W */ +#define TRDC_MBC2_MBC_DOM8_MEM2_BLK_NSE_W_COUNT2 (1U) + +/*! @name MBC_DOM8_MEM3_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM3_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM3_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM3_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM3_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM3_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM3_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM3_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM3_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM3_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM3_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM3_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM3_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM3_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM3_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM3_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM3_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM3_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM3_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM3_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM3_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM3_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM3_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM3_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM3_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM3_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM3_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM3_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM3_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM3_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM3_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM3_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM3_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MBC_DOM8_MEM3_BLK_CFG_W */ +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_CFG_W_COUNT (2U) + +/* The count of TRDC_MBC2_MBC_DOM8_MEM3_BLK_CFG_W */ +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_CFG_W_COUNT2 (3U) + +/*! @name MBC_DOM8_MEM3_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ +/*! @{ */ + +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT0_MASK (0x1U) +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT0_SHIFT (0U) +/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT0_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT1_MASK (0x2U) +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT1_SHIFT (1U) +/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT1_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT2_MASK (0x4U) +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT2_SHIFT (2U) +/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT2_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT3_MASK (0x8U) +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT3_SHIFT (3U) +/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT3_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT4_MASK (0x10U) +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT4_SHIFT (4U) +/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT4_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT5_MASK (0x20U) +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT5_SHIFT (5U) +/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT5_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT6_MASK (0x40U) +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT6_SHIFT (6U) +/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT6_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT7_MASK (0x80U) +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT7_SHIFT (7U) +/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT7_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT8_MASK (0x100U) +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT8_SHIFT (8U) +/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT8_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT9_MASK (0x200U) +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT9_SHIFT (9U) +/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT9_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT10_MASK (0x400U) +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT10_SHIFT (10U) +/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT10_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT11_MASK (0x800U) +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT11_SHIFT (11U) +/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT11_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT12_MASK (0x1000U) +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT12_SHIFT (12U) +/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT12_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT13_MASK (0x2000U) +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT13_SHIFT (13U) +/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT13_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT14_MASK (0x4000U) +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT14_SHIFT (14U) +/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT14_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT15_MASK (0x8000U) +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT15_SHIFT (15U) +/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT15_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT16_MASK (0x10000U) +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT16_SHIFT (16U) +/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT16_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT17_MASK (0x20000U) +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT17_SHIFT (17U) +/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT17_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT18_MASK (0x40000U) +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT18_SHIFT (18U) +/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT18_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT19_MASK (0x80000U) +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT19_SHIFT (19U) +/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT19_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT20_MASK (0x100000U) +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT20_SHIFT (20U) +/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT20_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT21_MASK (0x200000U) +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT21_SHIFT (21U) +/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT21_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT22_MASK (0x400000U) +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT22_SHIFT (22U) +/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT22_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT23_MASK (0x800000U) +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT23_SHIFT (23U) +/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT23_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT24_MASK (0x1000000U) +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT24_SHIFT (24U) +/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT24_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT25_MASK (0x2000000U) +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT25_SHIFT (25U) +/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT25_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT26_MASK (0x4000000U) +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT26_SHIFT (26U) +/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT26_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT27_MASK (0x8000000U) +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT27_SHIFT (27U) +/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT27_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT28_MASK (0x10000000U) +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT28_SHIFT (28U) +/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT28_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT29_MASK (0x20000000U) +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT29_SHIFT (29U) +/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT29_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT30_MASK (0x40000000U) +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT30_SHIFT (30U) +/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT30_MASK) + +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT31_MASK (0x80000000U) +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT31_SHIFT (31U) +/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_BIT31_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W */ +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_COUNT (2U) + +/* The count of TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W */ +#define TRDC_MBC2_MBC_DOM8_MEM3_BLK_NSE_W_COUNT2 (1U) + +/*! @name MBC_DOM9_MEM0_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM0_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM0_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM0_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM0_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM0_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM0_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM0_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM0_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM0_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM0_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM0_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM0_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM0_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM0_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM0_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM0_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM0_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM0_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM0_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM0_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM0_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM0_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM0_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM0_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM0_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM0_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM0_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM0_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM0_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM0_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM0_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM0_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MBC_DOM9_MEM0_BLK_CFG_W */ +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_CFG_W_COUNT (2U) + +/* The count of TRDC_MBC2_MBC_DOM9_MEM0_BLK_CFG_W */ +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_CFG_W_COUNT2 (16U) + +/*! @name MBC_DOM9_MEM0_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ +/*! @{ */ + +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT0_MASK (0x1U) +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT0_SHIFT (0U) +/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT0_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT1_MASK (0x2U) +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT1_SHIFT (1U) +/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT1_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT2_MASK (0x4U) +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT2_SHIFT (2U) +/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT2_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT3_MASK (0x8U) +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT3_SHIFT (3U) +/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT3_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT4_MASK (0x10U) +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT4_SHIFT (4U) +/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT4_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT5_MASK (0x20U) +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT5_SHIFT (5U) +/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT5_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT6_MASK (0x40U) +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT6_SHIFT (6U) +/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT6_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT7_MASK (0x80U) +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT7_SHIFT (7U) +/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT7_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT8_MASK (0x100U) +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT8_SHIFT (8U) +/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT8_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT9_MASK (0x200U) +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT9_SHIFT (9U) +/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT9_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT10_MASK (0x400U) +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT10_SHIFT (10U) +/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT10_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT11_MASK (0x800U) +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT11_SHIFT (11U) +/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT11_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT12_MASK (0x1000U) +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT12_SHIFT (12U) +/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT12_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT13_MASK (0x2000U) +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT13_SHIFT (13U) +/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT13_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT14_MASK (0x4000U) +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT14_SHIFT (14U) +/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT14_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT15_MASK (0x8000U) +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT15_SHIFT (15U) +/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT15_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT16_MASK (0x10000U) +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT16_SHIFT (16U) +/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT16_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT17_MASK (0x20000U) +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT17_SHIFT (17U) +/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT17_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT18_MASK (0x40000U) +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT18_SHIFT (18U) +/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT18_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT19_MASK (0x80000U) +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT19_SHIFT (19U) +/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT19_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT20_MASK (0x100000U) +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT20_SHIFT (20U) +/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT20_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT21_MASK (0x200000U) +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT21_SHIFT (21U) +/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT21_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT22_MASK (0x400000U) +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT22_SHIFT (22U) +/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT22_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT23_MASK (0x800000U) +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT23_SHIFT (23U) +/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT23_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT24_MASK (0x1000000U) +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT24_SHIFT (24U) +/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT24_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT25_MASK (0x2000000U) +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT25_SHIFT (25U) +/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT25_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT26_MASK (0x4000000U) +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT26_SHIFT (26U) +/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT26_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT27_MASK (0x8000000U) +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT27_SHIFT (27U) +/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT27_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT28_MASK (0x10000000U) +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT28_SHIFT (28U) +/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT28_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT29_MASK (0x20000000U) +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT29_SHIFT (29U) +/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT29_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT30_MASK (0x40000000U) +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT30_SHIFT (30U) +/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT30_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT31_MASK (0x80000000U) +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT31_SHIFT (31U) +/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_BIT31_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W */ +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_COUNT (2U) + +/* The count of TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W */ +#define TRDC_MBC2_MBC_DOM9_MEM0_BLK_NSE_W_COUNT2 (4U) + +/*! @name MBC_DOM9_MEM1_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM1_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM1_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM1_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM1_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM1_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM1_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM1_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM1_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM1_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM1_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM1_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM1_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM1_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM1_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM1_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM1_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM1_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM1_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM1_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM1_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM1_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM1_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM1_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM1_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM1_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM1_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM1_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM1_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM1_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM1_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM1_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM1_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MBC_DOM9_MEM1_BLK_CFG_W */ +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_CFG_W_COUNT (2U) + +/* The count of TRDC_MBC2_MBC_DOM9_MEM1_BLK_CFG_W */ +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_CFG_W_COUNT2 (1U) + +/*! @name MBC_DOM9_MEM1_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ +/*! @{ */ + +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT0_MASK (0x1U) +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT0_SHIFT (0U) +/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT0_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT1_MASK (0x2U) +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT1_SHIFT (1U) +/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT1_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT2_MASK (0x4U) +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT2_SHIFT (2U) +/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT2_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT3_MASK (0x8U) +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT3_SHIFT (3U) +/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT3_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT4_MASK (0x10U) +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT4_SHIFT (4U) +/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT4_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT5_MASK (0x20U) +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT5_SHIFT (5U) +/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT5_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT6_MASK (0x40U) +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT6_SHIFT (6U) +/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT6_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT7_MASK (0x80U) +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT7_SHIFT (7U) +/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT7_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT8_MASK (0x100U) +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT8_SHIFT (8U) +/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT8_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT9_MASK (0x200U) +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT9_SHIFT (9U) +/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT9_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT10_MASK (0x400U) +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT10_SHIFT (10U) +/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT10_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT11_MASK (0x800U) +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT11_SHIFT (11U) +/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT11_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT12_MASK (0x1000U) +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT12_SHIFT (12U) +/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT12_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT13_MASK (0x2000U) +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT13_SHIFT (13U) +/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT13_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT14_MASK (0x4000U) +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT14_SHIFT (14U) +/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT14_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT15_MASK (0x8000U) +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT15_SHIFT (15U) +/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT15_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT16_MASK (0x10000U) +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT16_SHIFT (16U) +/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT16_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT17_MASK (0x20000U) +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT17_SHIFT (17U) +/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT17_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT18_MASK (0x40000U) +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT18_SHIFT (18U) +/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT18_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT19_MASK (0x80000U) +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT19_SHIFT (19U) +/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT19_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT20_MASK (0x100000U) +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT20_SHIFT (20U) +/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT20_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT21_MASK (0x200000U) +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT21_SHIFT (21U) +/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT21_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT22_MASK (0x400000U) +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT22_SHIFT (22U) +/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT22_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT23_MASK (0x800000U) +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT23_SHIFT (23U) +/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT23_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT24_MASK (0x1000000U) +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT24_SHIFT (24U) +/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT24_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT25_MASK (0x2000000U) +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT25_SHIFT (25U) +/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT25_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT26_MASK (0x4000000U) +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT26_SHIFT (26U) +/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT26_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT27_MASK (0x8000000U) +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT27_SHIFT (27U) +/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT27_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT28_MASK (0x10000000U) +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT28_SHIFT (28U) +/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT28_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT29_MASK (0x20000000U) +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT29_SHIFT (29U) +/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT29_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT30_MASK (0x40000000U) +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT30_SHIFT (30U) +/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT30_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT31_MASK (0x80000000U) +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT31_SHIFT (31U) +/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_BIT31_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W */ +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_COUNT (2U) + +/* The count of TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W */ +#define TRDC_MBC2_MBC_DOM9_MEM1_BLK_NSE_W_COUNT2 (1U) + +/*! @name MBC_DOM9_MEM2_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM2_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM2_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM2_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM2_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM2_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM2_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM2_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM2_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM2_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM2_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM2_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM2_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM2_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM2_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM2_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM2_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM2_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM2_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM2_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM2_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM2_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM2_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM2_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM2_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM2_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM2_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM2_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM2_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM2_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM2_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM2_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM2_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MBC_DOM9_MEM2_BLK_CFG_W */ +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_CFG_W_COUNT (2U) + +/* The count of TRDC_MBC2_MBC_DOM9_MEM2_BLK_CFG_W */ +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_CFG_W_COUNT2 (1U) + +/*! @name MBC_DOM9_MEM2_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ +/*! @{ */ + +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT0_MASK (0x1U) +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT0_SHIFT (0U) +/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT0_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT1_MASK (0x2U) +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT1_SHIFT (1U) +/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT1_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT2_MASK (0x4U) +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT2_SHIFT (2U) +/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT2_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT3_MASK (0x8U) +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT3_SHIFT (3U) +/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT3_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT4_MASK (0x10U) +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT4_SHIFT (4U) +/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT4_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT5_MASK (0x20U) +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT5_SHIFT (5U) +/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT5_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT6_MASK (0x40U) +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT6_SHIFT (6U) +/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT6_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT7_MASK (0x80U) +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT7_SHIFT (7U) +/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT7_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT8_MASK (0x100U) +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT8_SHIFT (8U) +/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT8_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT9_MASK (0x200U) +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT9_SHIFT (9U) +/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT9_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT10_MASK (0x400U) +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT10_SHIFT (10U) +/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT10_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT11_MASK (0x800U) +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT11_SHIFT (11U) +/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT11_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT12_MASK (0x1000U) +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT12_SHIFT (12U) +/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT12_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT13_MASK (0x2000U) +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT13_SHIFT (13U) +/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT13_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT14_MASK (0x4000U) +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT14_SHIFT (14U) +/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT14_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT15_MASK (0x8000U) +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT15_SHIFT (15U) +/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT15_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT16_MASK (0x10000U) +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT16_SHIFT (16U) +/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT16_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT17_MASK (0x20000U) +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT17_SHIFT (17U) +/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT17_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT18_MASK (0x40000U) +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT18_SHIFT (18U) +/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT18_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT19_MASK (0x80000U) +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT19_SHIFT (19U) +/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT19_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT20_MASK (0x100000U) +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT20_SHIFT (20U) +/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT20_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT21_MASK (0x200000U) +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT21_SHIFT (21U) +/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT21_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT22_MASK (0x400000U) +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT22_SHIFT (22U) +/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT22_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT23_MASK (0x800000U) +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT23_SHIFT (23U) +/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT23_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT24_MASK (0x1000000U) +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT24_SHIFT (24U) +/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT24_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT25_MASK (0x2000000U) +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT25_SHIFT (25U) +/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT25_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT26_MASK (0x4000000U) +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT26_SHIFT (26U) +/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT26_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT27_MASK (0x8000000U) +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT27_SHIFT (27U) +/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT27_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT28_MASK (0x10000000U) +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT28_SHIFT (28U) +/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT28_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT29_MASK (0x20000000U) +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT29_SHIFT (29U) +/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT29_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT30_MASK (0x40000000U) +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT30_SHIFT (30U) +/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT30_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT31_MASK (0x80000000U) +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT31_SHIFT (31U) +/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_BIT31_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W */ +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_COUNT (2U) + +/* The count of TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W */ +#define TRDC_MBC2_MBC_DOM9_MEM2_BLK_NSE_W_COUNT2 (1U) + +/*! @name MBC_DOM9_MEM3_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM3_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM3_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM3_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM3_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM3_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM3_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM3_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM3_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM3_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM3_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM3_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM3_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM3_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM3_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM3_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM3_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM3_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM3_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM3_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM3_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM3_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM3_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM3_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM3_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM3_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM3_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM3_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM3_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM3_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM3_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM3_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM3_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MBC_DOM9_MEM3_BLK_CFG_W */ +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_CFG_W_COUNT (2U) + +/* The count of TRDC_MBC2_MBC_DOM9_MEM3_BLK_CFG_W */ +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_CFG_W_COUNT2 (3U) + +/*! @name MBC_DOM9_MEM3_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ +/*! @{ */ + +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT0_MASK (0x1U) +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT0_SHIFT (0U) +/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT0_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT1_MASK (0x2U) +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT1_SHIFT (1U) +/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT1_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT2_MASK (0x4U) +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT2_SHIFT (2U) +/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT2_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT3_MASK (0x8U) +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT3_SHIFT (3U) +/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT3_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT4_MASK (0x10U) +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT4_SHIFT (4U) +/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT4_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT5_MASK (0x20U) +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT5_SHIFT (5U) +/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT5_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT6_MASK (0x40U) +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT6_SHIFT (6U) +/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT6_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT7_MASK (0x80U) +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT7_SHIFT (7U) +/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT7_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT8_MASK (0x100U) +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT8_SHIFT (8U) +/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT8_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT9_MASK (0x200U) +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT9_SHIFT (9U) +/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT9_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT10_MASK (0x400U) +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT10_SHIFT (10U) +/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT10_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT11_MASK (0x800U) +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT11_SHIFT (11U) +/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT11_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT12_MASK (0x1000U) +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT12_SHIFT (12U) +/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT12_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT13_MASK (0x2000U) +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT13_SHIFT (13U) +/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT13_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT14_MASK (0x4000U) +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT14_SHIFT (14U) +/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT14_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT15_MASK (0x8000U) +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT15_SHIFT (15U) +/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT15_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT16_MASK (0x10000U) +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT16_SHIFT (16U) +/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT16_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT17_MASK (0x20000U) +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT17_SHIFT (17U) +/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT17_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT18_MASK (0x40000U) +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT18_SHIFT (18U) +/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT18_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT19_MASK (0x80000U) +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT19_SHIFT (19U) +/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT19_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT20_MASK (0x100000U) +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT20_SHIFT (20U) +/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT20_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT21_MASK (0x200000U) +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT21_SHIFT (21U) +/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT21_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT22_MASK (0x400000U) +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT22_SHIFT (22U) +/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT22_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT23_MASK (0x800000U) +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT23_SHIFT (23U) +/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT23_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT24_MASK (0x1000000U) +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT24_SHIFT (24U) +/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT24_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT25_MASK (0x2000000U) +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT25_SHIFT (25U) +/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT25_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT26_MASK (0x4000000U) +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT26_SHIFT (26U) +/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT26_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT27_MASK (0x8000000U) +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT27_SHIFT (27U) +/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT27_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT28_MASK (0x10000000U) +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT28_SHIFT (28U) +/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT28_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT29_MASK (0x20000000U) +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT29_SHIFT (29U) +/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT29_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT30_MASK (0x40000000U) +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT30_SHIFT (30U) +/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT30_MASK) + +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT31_MASK (0x80000000U) +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT31_SHIFT (31U) +/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_BIT31_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W */ +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_COUNT (2U) + +/* The count of TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W */ +#define TRDC_MBC2_MBC_DOM9_MEM3_BLK_NSE_W_COUNT2 (1U) + +/*! @name MBC_DOM10_MEM0_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM0_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM0_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM0_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM0_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM0_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM0_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM0_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM0_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM0_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM0_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM0_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM0_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM0_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM0_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM0_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM0_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM0_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM0_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM0_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM0_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM0_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM0_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM0_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM0_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM0_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM0_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM0_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM0_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM0_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM0_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM0_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM0_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MBC_DOM10_MEM0_BLK_CFG_W */ +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_CFG_W_COUNT (2U) + +/* The count of TRDC_MBC2_MBC_DOM10_MEM0_BLK_CFG_W */ +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_CFG_W_COUNT2 (16U) + +/*! @name MBC_DOM10_MEM0_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ +/*! @{ */ + +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT0_MASK (0x1U) +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT0_SHIFT (0U) +/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT0_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT1_MASK (0x2U) +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT1_SHIFT (1U) +/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT1_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT2_MASK (0x4U) +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT2_SHIFT (2U) +/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT2_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT3_MASK (0x8U) +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT3_SHIFT (3U) +/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT3_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT4_MASK (0x10U) +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT4_SHIFT (4U) +/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT4_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT5_MASK (0x20U) +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT5_SHIFT (5U) +/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT5_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT6_MASK (0x40U) +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT6_SHIFT (6U) +/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT6_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT7_MASK (0x80U) +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT7_SHIFT (7U) +/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT7_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT8_MASK (0x100U) +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT8_SHIFT (8U) +/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT8_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT9_MASK (0x200U) +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT9_SHIFT (9U) +/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT9_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT10_MASK (0x400U) +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT10_SHIFT (10U) +/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT10_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT11_MASK (0x800U) +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT11_SHIFT (11U) +/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT11_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT12_MASK (0x1000U) +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT12_SHIFT (12U) +/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT12_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT13_MASK (0x2000U) +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT13_SHIFT (13U) +/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT13_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT14_MASK (0x4000U) +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT14_SHIFT (14U) +/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT14_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT15_MASK (0x8000U) +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT15_SHIFT (15U) +/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT15_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT16_MASK (0x10000U) +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT16_SHIFT (16U) +/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT16_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT17_MASK (0x20000U) +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT17_SHIFT (17U) +/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT17_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT18_MASK (0x40000U) +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT18_SHIFT (18U) +/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT18_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT19_MASK (0x80000U) +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT19_SHIFT (19U) +/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT19_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT20_MASK (0x100000U) +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT20_SHIFT (20U) +/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT20_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT21_MASK (0x200000U) +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT21_SHIFT (21U) +/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT21_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT22_MASK (0x400000U) +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT22_SHIFT (22U) +/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT22_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT23_MASK (0x800000U) +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT23_SHIFT (23U) +/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT23_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT24_MASK (0x1000000U) +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT24_SHIFT (24U) +/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT24_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT25_MASK (0x2000000U) +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT25_SHIFT (25U) +/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT25_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT26_MASK (0x4000000U) +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT26_SHIFT (26U) +/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT26_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT27_MASK (0x8000000U) +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT27_SHIFT (27U) +/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT27_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT28_MASK (0x10000000U) +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT28_SHIFT (28U) +/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT28_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT29_MASK (0x20000000U) +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT29_SHIFT (29U) +/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT29_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT30_MASK (0x40000000U) +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT30_SHIFT (30U) +/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT30_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT31_MASK (0x80000000U) +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT31_SHIFT (31U) +/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_BIT31_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W */ +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_COUNT (2U) + +/* The count of TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W */ +#define TRDC_MBC2_MBC_DOM10_MEM0_BLK_NSE_W_COUNT2 (4U) + +/*! @name MBC_DOM10_MEM1_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM1_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM1_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM1_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM1_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM1_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM1_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM1_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM1_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM1_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM1_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM1_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM1_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM1_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM1_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM1_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM1_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM1_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM1_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM1_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM1_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM1_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM1_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM1_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM1_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM1_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM1_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM1_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM1_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM1_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM1_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM1_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM1_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MBC_DOM10_MEM1_BLK_CFG_W */ +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_CFG_W_COUNT (2U) + +/* The count of TRDC_MBC2_MBC_DOM10_MEM1_BLK_CFG_W */ +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_CFG_W_COUNT2 (1U) + +/*! @name MBC_DOM10_MEM1_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ +/*! @{ */ + +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT0_MASK (0x1U) +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT0_SHIFT (0U) +/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT0_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT1_MASK (0x2U) +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT1_SHIFT (1U) +/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT1_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT2_MASK (0x4U) +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT2_SHIFT (2U) +/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT2_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT3_MASK (0x8U) +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT3_SHIFT (3U) +/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT3_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT4_MASK (0x10U) +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT4_SHIFT (4U) +/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT4_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT5_MASK (0x20U) +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT5_SHIFT (5U) +/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT5_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT6_MASK (0x40U) +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT6_SHIFT (6U) +/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT6_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT7_MASK (0x80U) +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT7_SHIFT (7U) +/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT7_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT8_MASK (0x100U) +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT8_SHIFT (8U) +/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT8_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT9_MASK (0x200U) +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT9_SHIFT (9U) +/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT9_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT10_MASK (0x400U) +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT10_SHIFT (10U) +/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT10_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT11_MASK (0x800U) +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT11_SHIFT (11U) +/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT11_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT12_MASK (0x1000U) +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT12_SHIFT (12U) +/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT12_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT13_MASK (0x2000U) +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT13_SHIFT (13U) +/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT13_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT14_MASK (0x4000U) +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT14_SHIFT (14U) +/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT14_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT15_MASK (0x8000U) +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT15_SHIFT (15U) +/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT15_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT16_MASK (0x10000U) +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT16_SHIFT (16U) +/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT16_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT17_MASK (0x20000U) +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT17_SHIFT (17U) +/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT17_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT18_MASK (0x40000U) +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT18_SHIFT (18U) +/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT18_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT19_MASK (0x80000U) +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT19_SHIFT (19U) +/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT19_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT20_MASK (0x100000U) +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT20_SHIFT (20U) +/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT20_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT21_MASK (0x200000U) +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT21_SHIFT (21U) +/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT21_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT22_MASK (0x400000U) +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT22_SHIFT (22U) +/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT22_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT23_MASK (0x800000U) +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT23_SHIFT (23U) +/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT23_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT24_MASK (0x1000000U) +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT24_SHIFT (24U) +/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT24_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT25_MASK (0x2000000U) +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT25_SHIFT (25U) +/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT25_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT26_MASK (0x4000000U) +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT26_SHIFT (26U) +/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT26_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT27_MASK (0x8000000U) +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT27_SHIFT (27U) +/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT27_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT28_MASK (0x10000000U) +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT28_SHIFT (28U) +/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT28_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT29_MASK (0x20000000U) +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT29_SHIFT (29U) +/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT29_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT30_MASK (0x40000000U) +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT30_SHIFT (30U) +/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT30_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT31_MASK (0x80000000U) +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT31_SHIFT (31U) +/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_BIT31_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W */ +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_COUNT (2U) + +/* The count of TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W */ +#define TRDC_MBC2_MBC_DOM10_MEM1_BLK_NSE_W_COUNT2 (1U) + +/*! @name MBC_DOM10_MEM2_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM2_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM2_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM2_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM2_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM2_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM2_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM2_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM2_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM2_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM2_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM2_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM2_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM2_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM2_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM2_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM2_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM2_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM2_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM2_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM2_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM2_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM2_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM2_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM2_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM2_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM2_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM2_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM2_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM2_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM2_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM2_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM2_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MBC_DOM10_MEM2_BLK_CFG_W */ +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_CFG_W_COUNT (2U) + +/* The count of TRDC_MBC2_MBC_DOM10_MEM2_BLK_CFG_W */ +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_CFG_W_COUNT2 (1U) + +/*! @name MBC_DOM10_MEM2_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ +/*! @{ */ + +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT0_MASK (0x1U) +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT0_SHIFT (0U) +/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT0_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT1_MASK (0x2U) +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT1_SHIFT (1U) +/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT1_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT2_MASK (0x4U) +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT2_SHIFT (2U) +/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT2_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT3_MASK (0x8U) +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT3_SHIFT (3U) +/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT3_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT4_MASK (0x10U) +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT4_SHIFT (4U) +/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT4_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT5_MASK (0x20U) +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT5_SHIFT (5U) +/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT5_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT6_MASK (0x40U) +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT6_SHIFT (6U) +/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT6_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT7_MASK (0x80U) +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT7_SHIFT (7U) +/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT7_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT8_MASK (0x100U) +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT8_SHIFT (8U) +/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT8_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT9_MASK (0x200U) +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT9_SHIFT (9U) +/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT9_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT10_MASK (0x400U) +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT10_SHIFT (10U) +/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT10_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT11_MASK (0x800U) +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT11_SHIFT (11U) +/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT11_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT12_MASK (0x1000U) +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT12_SHIFT (12U) +/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT12_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT13_MASK (0x2000U) +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT13_SHIFT (13U) +/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT13_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT14_MASK (0x4000U) +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT14_SHIFT (14U) +/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT14_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT15_MASK (0x8000U) +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT15_SHIFT (15U) +/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT15_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT16_MASK (0x10000U) +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT16_SHIFT (16U) +/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT16_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT17_MASK (0x20000U) +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT17_SHIFT (17U) +/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT17_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT18_MASK (0x40000U) +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT18_SHIFT (18U) +/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT18_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT19_MASK (0x80000U) +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT19_SHIFT (19U) +/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT19_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT20_MASK (0x100000U) +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT20_SHIFT (20U) +/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT20_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT21_MASK (0x200000U) +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT21_SHIFT (21U) +/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT21_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT22_MASK (0x400000U) +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT22_SHIFT (22U) +/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT22_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT23_MASK (0x800000U) +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT23_SHIFT (23U) +/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT23_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT24_MASK (0x1000000U) +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT24_SHIFT (24U) +/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT24_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT25_MASK (0x2000000U) +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT25_SHIFT (25U) +/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT25_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT26_MASK (0x4000000U) +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT26_SHIFT (26U) +/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT26_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT27_MASK (0x8000000U) +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT27_SHIFT (27U) +/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT27_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT28_MASK (0x10000000U) +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT28_SHIFT (28U) +/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT28_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT29_MASK (0x20000000U) +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT29_SHIFT (29U) +/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT29_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT30_MASK (0x40000000U) +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT30_SHIFT (30U) +/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT30_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT31_MASK (0x80000000U) +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT31_SHIFT (31U) +/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_BIT31_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W */ +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_COUNT (2U) + +/* The count of TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W */ +#define TRDC_MBC2_MBC_DOM10_MEM2_BLK_NSE_W_COUNT2 (1U) + +/*! @name MBC_DOM10_MEM3_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM3_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM3_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM3_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM3_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM3_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM3_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM3_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM3_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM3_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM3_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM3_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM3_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM3_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM3_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM3_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM3_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM3_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM3_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM3_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM3_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM3_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM3_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM3_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM3_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM3_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM3_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM3_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM3_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM3_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM3_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM3_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM3_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MBC_DOM10_MEM3_BLK_CFG_W */ +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_CFG_W_COUNT (2U) + +/* The count of TRDC_MBC2_MBC_DOM10_MEM3_BLK_CFG_W */ +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_CFG_W_COUNT2 (3U) + +/*! @name MBC_DOM10_MEM3_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ +/*! @{ */ + +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT0_MASK (0x1U) +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT0_SHIFT (0U) +/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT0_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT1_MASK (0x2U) +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT1_SHIFT (1U) +/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT1_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT2_MASK (0x4U) +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT2_SHIFT (2U) +/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT2_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT3_MASK (0x8U) +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT3_SHIFT (3U) +/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT3_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT4_MASK (0x10U) +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT4_SHIFT (4U) +/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT4_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT5_MASK (0x20U) +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT5_SHIFT (5U) +/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT5_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT6_MASK (0x40U) +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT6_SHIFT (6U) +/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT6_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT7_MASK (0x80U) +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT7_SHIFT (7U) +/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT7_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT8_MASK (0x100U) +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT8_SHIFT (8U) +/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT8_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT9_MASK (0x200U) +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT9_SHIFT (9U) +/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT9_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT10_MASK (0x400U) +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT10_SHIFT (10U) +/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT10_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT11_MASK (0x800U) +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT11_SHIFT (11U) +/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT11_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT12_MASK (0x1000U) +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT12_SHIFT (12U) +/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT12_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT13_MASK (0x2000U) +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT13_SHIFT (13U) +/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT13_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT14_MASK (0x4000U) +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT14_SHIFT (14U) +/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT14_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT15_MASK (0x8000U) +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT15_SHIFT (15U) +/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT15_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT16_MASK (0x10000U) +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT16_SHIFT (16U) +/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT16_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT17_MASK (0x20000U) +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT17_SHIFT (17U) +/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT17_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT18_MASK (0x40000U) +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT18_SHIFT (18U) +/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT18_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT19_MASK (0x80000U) +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT19_SHIFT (19U) +/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT19_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT20_MASK (0x100000U) +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT20_SHIFT (20U) +/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT20_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT21_MASK (0x200000U) +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT21_SHIFT (21U) +/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT21_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT22_MASK (0x400000U) +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT22_SHIFT (22U) +/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT22_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT23_MASK (0x800000U) +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT23_SHIFT (23U) +/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT23_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT24_MASK (0x1000000U) +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT24_SHIFT (24U) +/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT24_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT25_MASK (0x2000000U) +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT25_SHIFT (25U) +/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT25_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT26_MASK (0x4000000U) +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT26_SHIFT (26U) +/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT26_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT27_MASK (0x8000000U) +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT27_SHIFT (27U) +/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT27_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT28_MASK (0x10000000U) +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT28_SHIFT (28U) +/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT28_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT29_MASK (0x20000000U) +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT29_SHIFT (29U) +/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT29_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT30_MASK (0x40000000U) +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT30_SHIFT (30U) +/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT30_MASK) + +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT31_MASK (0x80000000U) +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT31_SHIFT (31U) +/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_BIT31_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W */ +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_COUNT (2U) + +/* The count of TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W */ +#define TRDC_MBC2_MBC_DOM10_MEM3_BLK_NSE_W_COUNT2 (1U) + +/*! @name MBC_DOM11_MEM0_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM0_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM0_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM0_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM0_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM0_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM0_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM0_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM0_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM0_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM0_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM0_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM0_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM0_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM0_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM0_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM0_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM0_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM0_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM0_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM0_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM0_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM0_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM0_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM0_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM0_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM0_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM0_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM0_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM0_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM0_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM0_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM0_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MBC_DOM11_MEM0_BLK_CFG_W */ +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_CFG_W_COUNT (2U) + +/* The count of TRDC_MBC2_MBC_DOM11_MEM0_BLK_CFG_W */ +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_CFG_W_COUNT2 (16U) + +/*! @name MBC_DOM11_MEM0_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ +/*! @{ */ + +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT0_MASK (0x1U) +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT0_SHIFT (0U) +/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT0_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT1_MASK (0x2U) +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT1_SHIFT (1U) +/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT1_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT2_MASK (0x4U) +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT2_SHIFT (2U) +/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT2_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT3_MASK (0x8U) +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT3_SHIFT (3U) +/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT3_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT4_MASK (0x10U) +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT4_SHIFT (4U) +/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT4_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT5_MASK (0x20U) +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT5_SHIFT (5U) +/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT5_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT6_MASK (0x40U) +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT6_SHIFT (6U) +/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT6_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT7_MASK (0x80U) +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT7_SHIFT (7U) +/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT7_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT8_MASK (0x100U) +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT8_SHIFT (8U) +/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT8_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT9_MASK (0x200U) +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT9_SHIFT (9U) +/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT9_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT10_MASK (0x400U) +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT10_SHIFT (10U) +/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT10_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT11_MASK (0x800U) +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT11_SHIFT (11U) +/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT11_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT12_MASK (0x1000U) +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT12_SHIFT (12U) +/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT12_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT13_MASK (0x2000U) +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT13_SHIFT (13U) +/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT13_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT14_MASK (0x4000U) +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT14_SHIFT (14U) +/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT14_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT15_MASK (0x8000U) +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT15_SHIFT (15U) +/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT15_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT16_MASK (0x10000U) +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT16_SHIFT (16U) +/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT16_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT17_MASK (0x20000U) +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT17_SHIFT (17U) +/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT17_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT18_MASK (0x40000U) +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT18_SHIFT (18U) +/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT18_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT19_MASK (0x80000U) +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT19_SHIFT (19U) +/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT19_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT20_MASK (0x100000U) +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT20_SHIFT (20U) +/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT20_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT21_MASK (0x200000U) +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT21_SHIFT (21U) +/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT21_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT22_MASK (0x400000U) +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT22_SHIFT (22U) +/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT22_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT23_MASK (0x800000U) +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT23_SHIFT (23U) +/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT23_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT24_MASK (0x1000000U) +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT24_SHIFT (24U) +/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT24_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT25_MASK (0x2000000U) +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT25_SHIFT (25U) +/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT25_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT26_MASK (0x4000000U) +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT26_SHIFT (26U) +/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT26_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT27_MASK (0x8000000U) +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT27_SHIFT (27U) +/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT27_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT28_MASK (0x10000000U) +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT28_SHIFT (28U) +/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT28_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT29_MASK (0x20000000U) +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT29_SHIFT (29U) +/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT29_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT30_MASK (0x40000000U) +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT30_SHIFT (30U) +/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT30_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT31_MASK (0x80000000U) +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT31_SHIFT (31U) +/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_BIT31_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W */ +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_COUNT (2U) + +/* The count of TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W */ +#define TRDC_MBC2_MBC_DOM11_MEM0_BLK_NSE_W_COUNT2 (4U) + +/*! @name MBC_DOM11_MEM1_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM1_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM1_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM1_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM1_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM1_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM1_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM1_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM1_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM1_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM1_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM1_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM1_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM1_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM1_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM1_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM1_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM1_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM1_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM1_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM1_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM1_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM1_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM1_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM1_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM1_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM1_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM1_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM1_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM1_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM1_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM1_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM1_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MBC_DOM11_MEM1_BLK_CFG_W */ +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_CFG_W_COUNT (2U) + +/* The count of TRDC_MBC2_MBC_DOM11_MEM1_BLK_CFG_W */ +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_CFG_W_COUNT2 (1U) + +/*! @name MBC_DOM11_MEM1_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ +/*! @{ */ + +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT0_MASK (0x1U) +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT0_SHIFT (0U) +/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT0_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT1_MASK (0x2U) +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT1_SHIFT (1U) +/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT1_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT2_MASK (0x4U) +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT2_SHIFT (2U) +/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT2_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT3_MASK (0x8U) +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT3_SHIFT (3U) +/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT3_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT4_MASK (0x10U) +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT4_SHIFT (4U) +/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT4_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT5_MASK (0x20U) +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT5_SHIFT (5U) +/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT5_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT6_MASK (0x40U) +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT6_SHIFT (6U) +/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT6_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT7_MASK (0x80U) +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT7_SHIFT (7U) +/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT7_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT8_MASK (0x100U) +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT8_SHIFT (8U) +/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT8_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT9_MASK (0x200U) +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT9_SHIFT (9U) +/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT9_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT10_MASK (0x400U) +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT10_SHIFT (10U) +/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT10_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT11_MASK (0x800U) +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT11_SHIFT (11U) +/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT11_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT12_MASK (0x1000U) +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT12_SHIFT (12U) +/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT12_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT13_MASK (0x2000U) +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT13_SHIFT (13U) +/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT13_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT14_MASK (0x4000U) +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT14_SHIFT (14U) +/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT14_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT15_MASK (0x8000U) +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT15_SHIFT (15U) +/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT15_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT16_MASK (0x10000U) +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT16_SHIFT (16U) +/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT16_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT17_MASK (0x20000U) +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT17_SHIFT (17U) +/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT17_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT18_MASK (0x40000U) +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT18_SHIFT (18U) +/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT18_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT19_MASK (0x80000U) +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT19_SHIFT (19U) +/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT19_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT20_MASK (0x100000U) +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT20_SHIFT (20U) +/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT20_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT21_MASK (0x200000U) +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT21_SHIFT (21U) +/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT21_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT22_MASK (0x400000U) +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT22_SHIFT (22U) +/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT22_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT23_MASK (0x800000U) +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT23_SHIFT (23U) +/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT23_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT24_MASK (0x1000000U) +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT24_SHIFT (24U) +/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT24_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT25_MASK (0x2000000U) +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT25_SHIFT (25U) +/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT25_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT26_MASK (0x4000000U) +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT26_SHIFT (26U) +/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT26_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT27_MASK (0x8000000U) +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT27_SHIFT (27U) +/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT27_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT28_MASK (0x10000000U) +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT28_SHIFT (28U) +/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT28_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT29_MASK (0x20000000U) +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT29_SHIFT (29U) +/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT29_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT30_MASK (0x40000000U) +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT30_SHIFT (30U) +/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT30_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT31_MASK (0x80000000U) +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT31_SHIFT (31U) +/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_BIT31_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W */ +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_COUNT (2U) + +/* The count of TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W */ +#define TRDC_MBC2_MBC_DOM11_MEM1_BLK_NSE_W_COUNT2 (1U) + +/*! @name MBC_DOM11_MEM2_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM2_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM2_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM2_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM2_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM2_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM2_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM2_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM2_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM2_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM2_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM2_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM2_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM2_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM2_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM2_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM2_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM2_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM2_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM2_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM2_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM2_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM2_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM2_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM2_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM2_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM2_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM2_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM2_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM2_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM2_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM2_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM2_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MBC_DOM11_MEM2_BLK_CFG_W */ +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_CFG_W_COUNT (2U) + +/* The count of TRDC_MBC2_MBC_DOM11_MEM2_BLK_CFG_W */ +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_CFG_W_COUNT2 (1U) + +/*! @name MBC_DOM11_MEM2_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ +/*! @{ */ + +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT0_MASK (0x1U) +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT0_SHIFT (0U) +/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT0_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT1_MASK (0x2U) +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT1_SHIFT (1U) +/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT1_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT2_MASK (0x4U) +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT2_SHIFT (2U) +/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT2_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT3_MASK (0x8U) +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT3_SHIFT (3U) +/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT3_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT4_MASK (0x10U) +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT4_SHIFT (4U) +/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT4_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT5_MASK (0x20U) +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT5_SHIFT (5U) +/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT5_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT6_MASK (0x40U) +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT6_SHIFT (6U) +/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT6_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT7_MASK (0x80U) +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT7_SHIFT (7U) +/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT7_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT8_MASK (0x100U) +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT8_SHIFT (8U) +/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT8_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT9_MASK (0x200U) +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT9_SHIFT (9U) +/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT9_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT10_MASK (0x400U) +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT10_SHIFT (10U) +/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT10_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT11_MASK (0x800U) +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT11_SHIFT (11U) +/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT11_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT12_MASK (0x1000U) +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT12_SHIFT (12U) +/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT12_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT13_MASK (0x2000U) +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT13_SHIFT (13U) +/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT13_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT14_MASK (0x4000U) +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT14_SHIFT (14U) +/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT14_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT15_MASK (0x8000U) +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT15_SHIFT (15U) +/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT15_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT16_MASK (0x10000U) +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT16_SHIFT (16U) +/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT16_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT17_MASK (0x20000U) +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT17_SHIFT (17U) +/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT17_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT18_MASK (0x40000U) +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT18_SHIFT (18U) +/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT18_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT19_MASK (0x80000U) +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT19_SHIFT (19U) +/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT19_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT20_MASK (0x100000U) +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT20_SHIFT (20U) +/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT20_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT21_MASK (0x200000U) +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT21_SHIFT (21U) +/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT21_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT22_MASK (0x400000U) +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT22_SHIFT (22U) +/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT22_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT23_MASK (0x800000U) +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT23_SHIFT (23U) +/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT23_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT24_MASK (0x1000000U) +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT24_SHIFT (24U) +/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT24_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT25_MASK (0x2000000U) +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT25_SHIFT (25U) +/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT25_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT26_MASK (0x4000000U) +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT26_SHIFT (26U) +/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT26_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT27_MASK (0x8000000U) +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT27_SHIFT (27U) +/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT27_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT28_MASK (0x10000000U) +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT28_SHIFT (28U) +/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT28_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT29_MASK (0x20000000U) +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT29_SHIFT (29U) +/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT29_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT30_MASK (0x40000000U) +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT30_SHIFT (30U) +/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT30_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT31_MASK (0x80000000U) +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT31_SHIFT (31U) +/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_BIT31_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W */ +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_COUNT (2U) + +/* The count of TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W */ +#define TRDC_MBC2_MBC_DOM11_MEM2_BLK_NSE_W_COUNT2 (1U) + +/*! @name MBC_DOM11_MEM3_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM3_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM3_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM3_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM3_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM3_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM3_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM3_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM3_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM3_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM3_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM3_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM3_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM3_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM3_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM3_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM3_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM3_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM3_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM3_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM3_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM3_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM3_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM3_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM3_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM3_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM3_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM3_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM3_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM3_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM3_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM3_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM3_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MBC_DOM11_MEM3_BLK_CFG_W */ +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_CFG_W_COUNT (2U) + +/* The count of TRDC_MBC2_MBC_DOM11_MEM3_BLK_CFG_W */ +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_CFG_W_COUNT2 (3U) + +/*! @name MBC_DOM11_MEM3_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ +/*! @{ */ + +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT0_MASK (0x1U) +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT0_SHIFT (0U) +/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT0_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT1_MASK (0x2U) +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT1_SHIFT (1U) +/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT1_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT2_MASK (0x4U) +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT2_SHIFT (2U) +/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT2_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT3_MASK (0x8U) +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT3_SHIFT (3U) +/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT3_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT4_MASK (0x10U) +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT4_SHIFT (4U) +/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT4_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT5_MASK (0x20U) +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT5_SHIFT (5U) +/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT5_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT6_MASK (0x40U) +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT6_SHIFT (6U) +/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT6_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT7_MASK (0x80U) +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT7_SHIFT (7U) +/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT7_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT8_MASK (0x100U) +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT8_SHIFT (8U) +/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT8_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT9_MASK (0x200U) +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT9_SHIFT (9U) +/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT9_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT10_MASK (0x400U) +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT10_SHIFT (10U) +/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT10_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT11_MASK (0x800U) +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT11_SHIFT (11U) +/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT11_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT12_MASK (0x1000U) +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT12_SHIFT (12U) +/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT12_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT13_MASK (0x2000U) +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT13_SHIFT (13U) +/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT13_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT14_MASK (0x4000U) +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT14_SHIFT (14U) +/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT14_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT15_MASK (0x8000U) +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT15_SHIFT (15U) +/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT15_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT16_MASK (0x10000U) +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT16_SHIFT (16U) +/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT16_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT17_MASK (0x20000U) +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT17_SHIFT (17U) +/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT17_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT18_MASK (0x40000U) +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT18_SHIFT (18U) +/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT18_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT19_MASK (0x80000U) +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT19_SHIFT (19U) +/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT19_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT20_MASK (0x100000U) +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT20_SHIFT (20U) +/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT20_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT21_MASK (0x200000U) +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT21_SHIFT (21U) +/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT21_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT22_MASK (0x400000U) +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT22_SHIFT (22U) +/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT22_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT23_MASK (0x800000U) +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT23_SHIFT (23U) +/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT23_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT24_MASK (0x1000000U) +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT24_SHIFT (24U) +/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT24_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT25_MASK (0x2000000U) +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT25_SHIFT (25U) +/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT25_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT26_MASK (0x4000000U) +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT26_SHIFT (26U) +/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT26_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT27_MASK (0x8000000U) +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT27_SHIFT (27U) +/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT27_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT28_MASK (0x10000000U) +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT28_SHIFT (28U) +/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT28_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT29_MASK (0x20000000U) +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT29_SHIFT (29U) +/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT29_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT30_MASK (0x40000000U) +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT30_SHIFT (30U) +/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT30_MASK) + +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT31_MASK (0x80000000U) +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT31_SHIFT (31U) +/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_BIT31_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W */ +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_COUNT (2U) + +/* The count of TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W */ +#define TRDC_MBC2_MBC_DOM11_MEM3_BLK_NSE_W_COUNT2 (1U) + +/*! @name MBC_DOM12_MEM0_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM0_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM0_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM0_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM0_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM0_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM0_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM0_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM0_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM0_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM0_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM0_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM0_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM0_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM0_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM0_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM0_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM0_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM0_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM0_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM0_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM0_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM0_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM0_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM0_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM0_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM0_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM0_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM0_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM0_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM0_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM0_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM0_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MBC_DOM12_MEM0_BLK_CFG_W */ +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_CFG_W_COUNT (2U) + +/* The count of TRDC_MBC2_MBC_DOM12_MEM0_BLK_CFG_W */ +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_CFG_W_COUNT2 (16U) + +/*! @name MBC_DOM12_MEM0_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ +/*! @{ */ + +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT0_MASK (0x1U) +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT0_SHIFT (0U) +/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT0_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT1_MASK (0x2U) +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT1_SHIFT (1U) +/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT1_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT2_MASK (0x4U) +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT2_SHIFT (2U) +/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT2_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT3_MASK (0x8U) +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT3_SHIFT (3U) +/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT3_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT4_MASK (0x10U) +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT4_SHIFT (4U) +/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT4_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT5_MASK (0x20U) +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT5_SHIFT (5U) +/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT5_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT6_MASK (0x40U) +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT6_SHIFT (6U) +/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT6_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT7_MASK (0x80U) +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT7_SHIFT (7U) +/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT7_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT8_MASK (0x100U) +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT8_SHIFT (8U) +/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT8_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT9_MASK (0x200U) +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT9_SHIFT (9U) +/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT9_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT10_MASK (0x400U) +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT10_SHIFT (10U) +/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT10_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT11_MASK (0x800U) +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT11_SHIFT (11U) +/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT11_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT12_MASK (0x1000U) +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT12_SHIFT (12U) +/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT12_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT13_MASK (0x2000U) +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT13_SHIFT (13U) +/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT13_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT14_MASK (0x4000U) +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT14_SHIFT (14U) +/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT14_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT15_MASK (0x8000U) +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT15_SHIFT (15U) +/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT15_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT16_MASK (0x10000U) +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT16_SHIFT (16U) +/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT16_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT17_MASK (0x20000U) +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT17_SHIFT (17U) +/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT17_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT18_MASK (0x40000U) +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT18_SHIFT (18U) +/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT18_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT19_MASK (0x80000U) +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT19_SHIFT (19U) +/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT19_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT20_MASK (0x100000U) +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT20_SHIFT (20U) +/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT20_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT21_MASK (0x200000U) +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT21_SHIFT (21U) +/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT21_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT22_MASK (0x400000U) +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT22_SHIFT (22U) +/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT22_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT23_MASK (0x800000U) +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT23_SHIFT (23U) +/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT23_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT24_MASK (0x1000000U) +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT24_SHIFT (24U) +/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT24_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT25_MASK (0x2000000U) +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT25_SHIFT (25U) +/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT25_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT26_MASK (0x4000000U) +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT26_SHIFT (26U) +/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT26_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT27_MASK (0x8000000U) +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT27_SHIFT (27U) +/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT27_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT28_MASK (0x10000000U) +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT28_SHIFT (28U) +/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT28_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT29_MASK (0x20000000U) +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT29_SHIFT (29U) +/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT29_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT30_MASK (0x40000000U) +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT30_SHIFT (30U) +/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT30_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT31_MASK (0x80000000U) +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT31_SHIFT (31U) +/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_BIT31_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W */ +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_COUNT (2U) + +/* The count of TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W */ +#define TRDC_MBC2_MBC_DOM12_MEM0_BLK_NSE_W_COUNT2 (4U) + +/*! @name MBC_DOM12_MEM1_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM1_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM1_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM1_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM1_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM1_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM1_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM1_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM1_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM1_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM1_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM1_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM1_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM1_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM1_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM1_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM1_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM1_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM1_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM1_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM1_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM1_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM1_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM1_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM1_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM1_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM1_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM1_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM1_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM1_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM1_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM1_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM1_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MBC_DOM12_MEM1_BLK_CFG_W */ +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_CFG_W_COUNT (2U) + +/* The count of TRDC_MBC2_MBC_DOM12_MEM1_BLK_CFG_W */ +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_CFG_W_COUNT2 (1U) + +/*! @name MBC_DOM12_MEM1_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ +/*! @{ */ + +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT0_MASK (0x1U) +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT0_SHIFT (0U) +/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT0_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT1_MASK (0x2U) +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT1_SHIFT (1U) +/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT1_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT2_MASK (0x4U) +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT2_SHIFT (2U) +/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT2_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT3_MASK (0x8U) +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT3_SHIFT (3U) +/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT3_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT4_MASK (0x10U) +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT4_SHIFT (4U) +/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT4_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT5_MASK (0x20U) +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT5_SHIFT (5U) +/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT5_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT6_MASK (0x40U) +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT6_SHIFT (6U) +/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT6_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT7_MASK (0x80U) +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT7_SHIFT (7U) +/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT7_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT8_MASK (0x100U) +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT8_SHIFT (8U) +/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT8_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT9_MASK (0x200U) +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT9_SHIFT (9U) +/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT9_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT10_MASK (0x400U) +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT10_SHIFT (10U) +/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT10_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT11_MASK (0x800U) +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT11_SHIFT (11U) +/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT11_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT12_MASK (0x1000U) +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT12_SHIFT (12U) +/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT12_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT13_MASK (0x2000U) +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT13_SHIFT (13U) +/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT13_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT14_MASK (0x4000U) +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT14_SHIFT (14U) +/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT14_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT15_MASK (0x8000U) +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT15_SHIFT (15U) +/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT15_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT16_MASK (0x10000U) +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT16_SHIFT (16U) +/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT16_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT17_MASK (0x20000U) +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT17_SHIFT (17U) +/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT17_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT18_MASK (0x40000U) +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT18_SHIFT (18U) +/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT18_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT19_MASK (0x80000U) +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT19_SHIFT (19U) +/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT19_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT20_MASK (0x100000U) +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT20_SHIFT (20U) +/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT20_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT21_MASK (0x200000U) +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT21_SHIFT (21U) +/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT21_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT22_MASK (0x400000U) +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT22_SHIFT (22U) +/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT22_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT23_MASK (0x800000U) +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT23_SHIFT (23U) +/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT23_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT24_MASK (0x1000000U) +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT24_SHIFT (24U) +/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT24_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT25_MASK (0x2000000U) +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT25_SHIFT (25U) +/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT25_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT26_MASK (0x4000000U) +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT26_SHIFT (26U) +/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT26_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT27_MASK (0x8000000U) +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT27_SHIFT (27U) +/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT27_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT28_MASK (0x10000000U) +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT28_SHIFT (28U) +/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT28_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT29_MASK (0x20000000U) +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT29_SHIFT (29U) +/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT29_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT30_MASK (0x40000000U) +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT30_SHIFT (30U) +/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT30_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT31_MASK (0x80000000U) +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT31_SHIFT (31U) +/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_BIT31_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W */ +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_COUNT (2U) + +/* The count of TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W */ +#define TRDC_MBC2_MBC_DOM12_MEM1_BLK_NSE_W_COUNT2 (1U) + +/*! @name MBC_DOM12_MEM2_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM2_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM2_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM2_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM2_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM2_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM2_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM2_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM2_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM2_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM2_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM2_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM2_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM2_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM2_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM2_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM2_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM2_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM2_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM2_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM2_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM2_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM2_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM2_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM2_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM2_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM2_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM2_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM2_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM2_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM2_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM2_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM2_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MBC_DOM12_MEM2_BLK_CFG_W */ +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_CFG_W_COUNT (2U) + +/* The count of TRDC_MBC2_MBC_DOM12_MEM2_BLK_CFG_W */ +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_CFG_W_COUNT2 (1U) + +/*! @name MBC_DOM12_MEM2_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ +/*! @{ */ + +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT0_MASK (0x1U) +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT0_SHIFT (0U) +/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT0_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT1_MASK (0x2U) +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT1_SHIFT (1U) +/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT1_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT2_MASK (0x4U) +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT2_SHIFT (2U) +/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT2_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT3_MASK (0x8U) +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT3_SHIFT (3U) +/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT3_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT4_MASK (0x10U) +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT4_SHIFT (4U) +/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT4_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT5_MASK (0x20U) +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT5_SHIFT (5U) +/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT5_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT6_MASK (0x40U) +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT6_SHIFT (6U) +/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT6_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT7_MASK (0x80U) +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT7_SHIFT (7U) +/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT7_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT8_MASK (0x100U) +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT8_SHIFT (8U) +/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT8_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT9_MASK (0x200U) +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT9_SHIFT (9U) +/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT9_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT10_MASK (0x400U) +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT10_SHIFT (10U) +/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT10_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT11_MASK (0x800U) +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT11_SHIFT (11U) +/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT11_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT12_MASK (0x1000U) +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT12_SHIFT (12U) +/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT12_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT13_MASK (0x2000U) +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT13_SHIFT (13U) +/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT13_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT14_MASK (0x4000U) +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT14_SHIFT (14U) +/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT14_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT15_MASK (0x8000U) +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT15_SHIFT (15U) +/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT15_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT16_MASK (0x10000U) +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT16_SHIFT (16U) +/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT16_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT17_MASK (0x20000U) +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT17_SHIFT (17U) +/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT17_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT18_MASK (0x40000U) +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT18_SHIFT (18U) +/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT18_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT19_MASK (0x80000U) +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT19_SHIFT (19U) +/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT19_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT20_MASK (0x100000U) +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT20_SHIFT (20U) +/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT20_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT21_MASK (0x200000U) +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT21_SHIFT (21U) +/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT21_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT22_MASK (0x400000U) +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT22_SHIFT (22U) +/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT22_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT23_MASK (0x800000U) +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT23_SHIFT (23U) +/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT23_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT24_MASK (0x1000000U) +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT24_SHIFT (24U) +/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT24_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT25_MASK (0x2000000U) +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT25_SHIFT (25U) +/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT25_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT26_MASK (0x4000000U) +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT26_SHIFT (26U) +/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT26_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT27_MASK (0x8000000U) +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT27_SHIFT (27U) +/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT27_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT28_MASK (0x10000000U) +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT28_SHIFT (28U) +/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT28_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT29_MASK (0x20000000U) +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT29_SHIFT (29U) +/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT29_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT30_MASK (0x40000000U) +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT30_SHIFT (30U) +/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT30_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT31_MASK (0x80000000U) +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT31_SHIFT (31U) +/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_BIT31_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W */ +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_COUNT (2U) + +/* The count of TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W */ +#define TRDC_MBC2_MBC_DOM12_MEM2_BLK_NSE_W_COUNT2 (1U) + +/*! @name MBC_DOM12_MEM3_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM3_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM3_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM3_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM3_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM3_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM3_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM3_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM3_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM3_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM3_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM3_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM3_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM3_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM3_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM3_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM3_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM3_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM3_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM3_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM3_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM3_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM3_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM3_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM3_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM3_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM3_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM3_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM3_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM3_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM3_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM3_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM3_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MBC_DOM12_MEM3_BLK_CFG_W */ +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_CFG_W_COUNT (2U) + +/* The count of TRDC_MBC2_MBC_DOM12_MEM3_BLK_CFG_W */ +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_CFG_W_COUNT2 (3U) + +/*! @name MBC_DOM12_MEM3_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ +/*! @{ */ + +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT0_MASK (0x1U) +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT0_SHIFT (0U) +/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT0_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT1_MASK (0x2U) +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT1_SHIFT (1U) +/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT1_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT2_MASK (0x4U) +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT2_SHIFT (2U) +/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT2_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT3_MASK (0x8U) +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT3_SHIFT (3U) +/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT3_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT4_MASK (0x10U) +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT4_SHIFT (4U) +/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT4_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT5_MASK (0x20U) +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT5_SHIFT (5U) +/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT5_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT6_MASK (0x40U) +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT6_SHIFT (6U) +/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT6_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT7_MASK (0x80U) +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT7_SHIFT (7U) +/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT7_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT8_MASK (0x100U) +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT8_SHIFT (8U) +/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT8_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT9_MASK (0x200U) +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT9_SHIFT (9U) +/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT9_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT10_MASK (0x400U) +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT10_SHIFT (10U) +/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT10_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT11_MASK (0x800U) +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT11_SHIFT (11U) +/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT11_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT12_MASK (0x1000U) +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT12_SHIFT (12U) +/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT12_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT13_MASK (0x2000U) +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT13_SHIFT (13U) +/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT13_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT14_MASK (0x4000U) +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT14_SHIFT (14U) +/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT14_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT15_MASK (0x8000U) +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT15_SHIFT (15U) +/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT15_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT16_MASK (0x10000U) +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT16_SHIFT (16U) +/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT16_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT17_MASK (0x20000U) +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT17_SHIFT (17U) +/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT17_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT18_MASK (0x40000U) +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT18_SHIFT (18U) +/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT18_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT19_MASK (0x80000U) +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT19_SHIFT (19U) +/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT19_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT20_MASK (0x100000U) +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT20_SHIFT (20U) +/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT20_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT21_MASK (0x200000U) +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT21_SHIFT (21U) +/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT21_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT22_MASK (0x400000U) +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT22_SHIFT (22U) +/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT22_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT23_MASK (0x800000U) +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT23_SHIFT (23U) +/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT23_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT24_MASK (0x1000000U) +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT24_SHIFT (24U) +/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT24_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT25_MASK (0x2000000U) +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT25_SHIFT (25U) +/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT25_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT26_MASK (0x4000000U) +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT26_SHIFT (26U) +/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT26_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT27_MASK (0x8000000U) +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT27_SHIFT (27U) +/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT27_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT28_MASK (0x10000000U) +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT28_SHIFT (28U) +/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT28_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT29_MASK (0x20000000U) +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT29_SHIFT (29U) +/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT29_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT30_MASK (0x40000000U) +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT30_SHIFT (30U) +/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT30_MASK) + +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT31_MASK (0x80000000U) +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT31_SHIFT (31U) +/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_BIT31_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W */ +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_COUNT (2U) + +/* The count of TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W */ +#define TRDC_MBC2_MBC_DOM12_MEM3_BLK_NSE_W_COUNT2 (1U) + +/*! @name MBC_DOM13_MEM0_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM0_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM0_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM0_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM0_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM0_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM0_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM0_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM0_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM0_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM0_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM0_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM0_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM0_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM0_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM0_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM0_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM0_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM0_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM0_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM0_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM0_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM0_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM0_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM0_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM0_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM0_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM0_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM0_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM0_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM0_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM0_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM0_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MBC_DOM13_MEM0_BLK_CFG_W */ +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_CFG_W_COUNT (2U) + +/* The count of TRDC_MBC2_MBC_DOM13_MEM0_BLK_CFG_W */ +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_CFG_W_COUNT2 (16U) + +/*! @name MBC_DOM13_MEM0_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ +/*! @{ */ + +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT0_MASK (0x1U) +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT0_SHIFT (0U) +/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT0_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT1_MASK (0x2U) +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT1_SHIFT (1U) +/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT1_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT2_MASK (0x4U) +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT2_SHIFT (2U) +/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT2_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT3_MASK (0x8U) +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT3_SHIFT (3U) +/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT3_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT4_MASK (0x10U) +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT4_SHIFT (4U) +/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT4_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT5_MASK (0x20U) +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT5_SHIFT (5U) +/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT5_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT6_MASK (0x40U) +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT6_SHIFT (6U) +/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT6_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT7_MASK (0x80U) +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT7_SHIFT (7U) +/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT7_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT8_MASK (0x100U) +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT8_SHIFT (8U) +/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT8_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT9_MASK (0x200U) +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT9_SHIFT (9U) +/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT9_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT10_MASK (0x400U) +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT10_SHIFT (10U) +/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT10_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT11_MASK (0x800U) +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT11_SHIFT (11U) +/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT11_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT12_MASK (0x1000U) +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT12_SHIFT (12U) +/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT12_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT13_MASK (0x2000U) +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT13_SHIFT (13U) +/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT13_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT14_MASK (0x4000U) +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT14_SHIFT (14U) +/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT14_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT15_MASK (0x8000U) +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT15_SHIFT (15U) +/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT15_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT16_MASK (0x10000U) +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT16_SHIFT (16U) +/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT16_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT17_MASK (0x20000U) +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT17_SHIFT (17U) +/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT17_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT18_MASK (0x40000U) +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT18_SHIFT (18U) +/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT18_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT19_MASK (0x80000U) +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT19_SHIFT (19U) +/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT19_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT20_MASK (0x100000U) +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT20_SHIFT (20U) +/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT20_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT21_MASK (0x200000U) +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT21_SHIFT (21U) +/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT21_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT22_MASK (0x400000U) +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT22_SHIFT (22U) +/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT22_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT23_MASK (0x800000U) +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT23_SHIFT (23U) +/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT23_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT24_MASK (0x1000000U) +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT24_SHIFT (24U) +/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT24_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT25_MASK (0x2000000U) +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT25_SHIFT (25U) +/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT25_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT26_MASK (0x4000000U) +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT26_SHIFT (26U) +/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT26_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT27_MASK (0x8000000U) +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT27_SHIFT (27U) +/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT27_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT28_MASK (0x10000000U) +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT28_SHIFT (28U) +/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT28_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT29_MASK (0x20000000U) +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT29_SHIFT (29U) +/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT29_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT30_MASK (0x40000000U) +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT30_SHIFT (30U) +/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT30_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT31_MASK (0x80000000U) +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT31_SHIFT (31U) +/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_BIT31_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W */ +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_COUNT (2U) + +/* The count of TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W */ +#define TRDC_MBC2_MBC_DOM13_MEM0_BLK_NSE_W_COUNT2 (4U) + +/*! @name MBC_DOM13_MEM1_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM1_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM1_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM1_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM1_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM1_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM1_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM1_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM1_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM1_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM1_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM1_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM1_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM1_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM1_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM1_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM1_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM1_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM1_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM1_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM1_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM1_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM1_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM1_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM1_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM1_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM1_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM1_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM1_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM1_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM1_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM1_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM1_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MBC_DOM13_MEM1_BLK_CFG_W */ +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_CFG_W_COUNT (2U) + +/* The count of TRDC_MBC2_MBC_DOM13_MEM1_BLK_CFG_W */ +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_CFG_W_COUNT2 (1U) + +/*! @name MBC_DOM13_MEM1_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ +/*! @{ */ + +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT0_MASK (0x1U) +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT0_SHIFT (0U) +/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT0_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT1_MASK (0x2U) +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT1_SHIFT (1U) +/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT1_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT2_MASK (0x4U) +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT2_SHIFT (2U) +/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT2_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT3_MASK (0x8U) +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT3_SHIFT (3U) +/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT3_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT4_MASK (0x10U) +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT4_SHIFT (4U) +/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT4_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT5_MASK (0x20U) +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT5_SHIFT (5U) +/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT5_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT6_MASK (0x40U) +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT6_SHIFT (6U) +/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT6_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT7_MASK (0x80U) +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT7_SHIFT (7U) +/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT7_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT8_MASK (0x100U) +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT8_SHIFT (8U) +/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT8_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT9_MASK (0x200U) +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT9_SHIFT (9U) +/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT9_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT10_MASK (0x400U) +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT10_SHIFT (10U) +/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT10_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT11_MASK (0x800U) +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT11_SHIFT (11U) +/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT11_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT12_MASK (0x1000U) +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT12_SHIFT (12U) +/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT12_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT13_MASK (0x2000U) +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT13_SHIFT (13U) +/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT13_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT14_MASK (0x4000U) +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT14_SHIFT (14U) +/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT14_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT15_MASK (0x8000U) +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT15_SHIFT (15U) +/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT15_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT16_MASK (0x10000U) +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT16_SHIFT (16U) +/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT16_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT17_MASK (0x20000U) +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT17_SHIFT (17U) +/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT17_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT18_MASK (0x40000U) +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT18_SHIFT (18U) +/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT18_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT19_MASK (0x80000U) +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT19_SHIFT (19U) +/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT19_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT20_MASK (0x100000U) +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT20_SHIFT (20U) +/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT20_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT21_MASK (0x200000U) +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT21_SHIFT (21U) +/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT21_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT22_MASK (0x400000U) +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT22_SHIFT (22U) +/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT22_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT23_MASK (0x800000U) +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT23_SHIFT (23U) +/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT23_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT24_MASK (0x1000000U) +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT24_SHIFT (24U) +/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT24_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT25_MASK (0x2000000U) +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT25_SHIFT (25U) +/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT25_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT26_MASK (0x4000000U) +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT26_SHIFT (26U) +/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT26_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT27_MASK (0x8000000U) +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT27_SHIFT (27U) +/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT27_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT28_MASK (0x10000000U) +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT28_SHIFT (28U) +/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT28_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT29_MASK (0x20000000U) +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT29_SHIFT (29U) +/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT29_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT30_MASK (0x40000000U) +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT30_SHIFT (30U) +/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT30_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT31_MASK (0x80000000U) +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT31_SHIFT (31U) +/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_BIT31_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W */ +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_COUNT (2U) + +/* The count of TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W */ +#define TRDC_MBC2_MBC_DOM13_MEM1_BLK_NSE_W_COUNT2 (1U) + +/*! @name MBC_DOM13_MEM2_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM2_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM2_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM2_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM2_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM2_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM2_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM2_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM2_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM2_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM2_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM2_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM2_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM2_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM2_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM2_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM2_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM2_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM2_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM2_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM2_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM2_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM2_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM2_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM2_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM2_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM2_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM2_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM2_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM2_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM2_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM2_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM2_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MBC_DOM13_MEM2_BLK_CFG_W */ +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_CFG_W_COUNT (2U) + +/* The count of TRDC_MBC2_MBC_DOM13_MEM2_BLK_CFG_W */ +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_CFG_W_COUNT2 (1U) + +/*! @name MBC_DOM13_MEM2_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ +/*! @{ */ + +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT0_MASK (0x1U) +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT0_SHIFT (0U) +/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT0_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT1_MASK (0x2U) +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT1_SHIFT (1U) +/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT1_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT2_MASK (0x4U) +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT2_SHIFT (2U) +/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT2_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT3_MASK (0x8U) +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT3_SHIFT (3U) +/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT3_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT4_MASK (0x10U) +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT4_SHIFT (4U) +/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT4_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT5_MASK (0x20U) +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT5_SHIFT (5U) +/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT5_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT6_MASK (0x40U) +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT6_SHIFT (6U) +/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT6_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT7_MASK (0x80U) +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT7_SHIFT (7U) +/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT7_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT8_MASK (0x100U) +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT8_SHIFT (8U) +/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT8_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT9_MASK (0x200U) +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT9_SHIFT (9U) +/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT9_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT10_MASK (0x400U) +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT10_SHIFT (10U) +/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT10_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT11_MASK (0x800U) +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT11_SHIFT (11U) +/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT11_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT12_MASK (0x1000U) +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT12_SHIFT (12U) +/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT12_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT13_MASK (0x2000U) +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT13_SHIFT (13U) +/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT13_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT14_MASK (0x4000U) +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT14_SHIFT (14U) +/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT14_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT15_MASK (0x8000U) +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT15_SHIFT (15U) +/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT15_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT16_MASK (0x10000U) +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT16_SHIFT (16U) +/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT16_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT17_MASK (0x20000U) +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT17_SHIFT (17U) +/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT17_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT18_MASK (0x40000U) +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT18_SHIFT (18U) +/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT18_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT19_MASK (0x80000U) +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT19_SHIFT (19U) +/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT19_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT20_MASK (0x100000U) +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT20_SHIFT (20U) +/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT20_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT21_MASK (0x200000U) +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT21_SHIFT (21U) +/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT21_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT22_MASK (0x400000U) +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT22_SHIFT (22U) +/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT22_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT23_MASK (0x800000U) +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT23_SHIFT (23U) +/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT23_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT24_MASK (0x1000000U) +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT24_SHIFT (24U) +/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT24_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT25_MASK (0x2000000U) +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT25_SHIFT (25U) +/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT25_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT26_MASK (0x4000000U) +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT26_SHIFT (26U) +/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT26_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT27_MASK (0x8000000U) +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT27_SHIFT (27U) +/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT27_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT28_MASK (0x10000000U) +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT28_SHIFT (28U) +/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT28_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT29_MASK (0x20000000U) +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT29_SHIFT (29U) +/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT29_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT30_MASK (0x40000000U) +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT30_SHIFT (30U) +/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT30_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT31_MASK (0x80000000U) +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT31_SHIFT (31U) +/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_BIT31_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W */ +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_COUNT (2U) + +/* The count of TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W */ +#define TRDC_MBC2_MBC_DOM13_MEM2_BLK_NSE_W_COUNT2 (1U) + +/*! @name MBC_DOM13_MEM3_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM3_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM3_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM3_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM3_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM3_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM3_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM3_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM3_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM3_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM3_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM3_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM3_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM3_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM3_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM3_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM3_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM3_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM3_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM3_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM3_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM3_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM3_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM3_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM3_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM3_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM3_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM3_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM3_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM3_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM3_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM3_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM3_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MBC_DOM13_MEM3_BLK_CFG_W */ +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_CFG_W_COUNT (2U) + +/* The count of TRDC_MBC2_MBC_DOM13_MEM3_BLK_CFG_W */ +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_CFG_W_COUNT2 (3U) + +/*! @name MBC_DOM13_MEM3_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ +/*! @{ */ + +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT0_MASK (0x1U) +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT0_SHIFT (0U) +/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT0_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT1_MASK (0x2U) +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT1_SHIFT (1U) +/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT1_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT2_MASK (0x4U) +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT2_SHIFT (2U) +/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT2_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT3_MASK (0x8U) +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT3_SHIFT (3U) +/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT3_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT4_MASK (0x10U) +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT4_SHIFT (4U) +/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT4_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT5_MASK (0x20U) +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT5_SHIFT (5U) +/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT5_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT6_MASK (0x40U) +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT6_SHIFT (6U) +/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT6_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT7_MASK (0x80U) +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT7_SHIFT (7U) +/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT7_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT8_MASK (0x100U) +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT8_SHIFT (8U) +/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT8_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT9_MASK (0x200U) +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT9_SHIFT (9U) +/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT9_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT10_MASK (0x400U) +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT10_SHIFT (10U) +/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT10_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT11_MASK (0x800U) +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT11_SHIFT (11U) +/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT11_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT12_MASK (0x1000U) +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT12_SHIFT (12U) +/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT12_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT13_MASK (0x2000U) +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT13_SHIFT (13U) +/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT13_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT14_MASK (0x4000U) +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT14_SHIFT (14U) +/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT14_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT15_MASK (0x8000U) +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT15_SHIFT (15U) +/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT15_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT16_MASK (0x10000U) +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT16_SHIFT (16U) +/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT16_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT17_MASK (0x20000U) +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT17_SHIFT (17U) +/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT17_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT18_MASK (0x40000U) +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT18_SHIFT (18U) +/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT18_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT19_MASK (0x80000U) +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT19_SHIFT (19U) +/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT19_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT20_MASK (0x100000U) +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT20_SHIFT (20U) +/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT20_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT21_MASK (0x200000U) +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT21_SHIFT (21U) +/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT21_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT22_MASK (0x400000U) +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT22_SHIFT (22U) +/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT22_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT23_MASK (0x800000U) +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT23_SHIFT (23U) +/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT23_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT24_MASK (0x1000000U) +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT24_SHIFT (24U) +/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT24_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT25_MASK (0x2000000U) +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT25_SHIFT (25U) +/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT25_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT26_MASK (0x4000000U) +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT26_SHIFT (26U) +/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT26_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT27_MASK (0x8000000U) +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT27_SHIFT (27U) +/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT27_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT28_MASK (0x10000000U) +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT28_SHIFT (28U) +/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT28_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT29_MASK (0x20000000U) +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT29_SHIFT (29U) +/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT29_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT30_MASK (0x40000000U) +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT30_SHIFT (30U) +/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT30_MASK) + +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT31_MASK (0x80000000U) +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT31_SHIFT (31U) +/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_BIT31_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W */ +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_COUNT (2U) + +/* The count of TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W */ +#define TRDC_MBC2_MBC_DOM13_MEM3_BLK_NSE_W_COUNT2 (1U) + +/*! @name MBC_DOM14_MEM0_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM0_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM0_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM0_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM0_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM0_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM0_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM0_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM0_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM0_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM0_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM0_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM0_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM0_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM0_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM0_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM0_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM0_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM0_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM0_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM0_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM0_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM0_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM0_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM0_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM0_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM0_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM0_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM0_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM0_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM0_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM0_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM0_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MBC_DOM14_MEM0_BLK_CFG_W */ +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_CFG_W_COUNT (2U) + +/* The count of TRDC_MBC2_MBC_DOM14_MEM0_BLK_CFG_W */ +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_CFG_W_COUNT2 (16U) + +/*! @name MBC_DOM14_MEM0_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ +/*! @{ */ + +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT0_MASK (0x1U) +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT0_SHIFT (0U) +/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT0_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT1_MASK (0x2U) +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT1_SHIFT (1U) +/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT1_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT2_MASK (0x4U) +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT2_SHIFT (2U) +/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT2_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT3_MASK (0x8U) +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT3_SHIFT (3U) +/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT3_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT4_MASK (0x10U) +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT4_SHIFT (4U) +/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT4_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT5_MASK (0x20U) +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT5_SHIFT (5U) +/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT5_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT6_MASK (0x40U) +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT6_SHIFT (6U) +/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT6_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT7_MASK (0x80U) +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT7_SHIFT (7U) +/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT7_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT8_MASK (0x100U) +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT8_SHIFT (8U) +/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT8_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT9_MASK (0x200U) +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT9_SHIFT (9U) +/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT9_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT10_MASK (0x400U) +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT10_SHIFT (10U) +/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT10_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT11_MASK (0x800U) +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT11_SHIFT (11U) +/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT11_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT12_MASK (0x1000U) +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT12_SHIFT (12U) +/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT12_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT13_MASK (0x2000U) +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT13_SHIFT (13U) +/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT13_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT14_MASK (0x4000U) +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT14_SHIFT (14U) +/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT14_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT15_MASK (0x8000U) +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT15_SHIFT (15U) +/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT15_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT16_MASK (0x10000U) +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT16_SHIFT (16U) +/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT16_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT17_MASK (0x20000U) +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT17_SHIFT (17U) +/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT17_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT18_MASK (0x40000U) +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT18_SHIFT (18U) +/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT18_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT19_MASK (0x80000U) +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT19_SHIFT (19U) +/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT19_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT20_MASK (0x100000U) +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT20_SHIFT (20U) +/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT20_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT21_MASK (0x200000U) +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT21_SHIFT (21U) +/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT21_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT22_MASK (0x400000U) +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT22_SHIFT (22U) +/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT22_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT23_MASK (0x800000U) +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT23_SHIFT (23U) +/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT23_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT24_MASK (0x1000000U) +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT24_SHIFT (24U) +/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT24_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT25_MASK (0x2000000U) +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT25_SHIFT (25U) +/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT25_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT26_MASK (0x4000000U) +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT26_SHIFT (26U) +/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT26_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT27_MASK (0x8000000U) +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT27_SHIFT (27U) +/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT27_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT28_MASK (0x10000000U) +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT28_SHIFT (28U) +/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT28_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT29_MASK (0x20000000U) +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT29_SHIFT (29U) +/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT29_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT30_MASK (0x40000000U) +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT30_SHIFT (30U) +/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT30_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT31_MASK (0x80000000U) +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT31_SHIFT (31U) +/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_BIT31_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W */ +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_COUNT (2U) + +/* The count of TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W */ +#define TRDC_MBC2_MBC_DOM14_MEM0_BLK_NSE_W_COUNT2 (4U) + +/*! @name MBC_DOM14_MEM1_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM1_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM1_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM1_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM1_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM1_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM1_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM1_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM1_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM1_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM1_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM1_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM1_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM1_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM1_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM1_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM1_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM1_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM1_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM1_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM1_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM1_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM1_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM1_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM1_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM1_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM1_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM1_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM1_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM1_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM1_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM1_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM1_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MBC_DOM14_MEM1_BLK_CFG_W */ +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_CFG_W_COUNT (2U) + +/* The count of TRDC_MBC2_MBC_DOM14_MEM1_BLK_CFG_W */ +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_CFG_W_COUNT2 (1U) + +/*! @name MBC_DOM14_MEM1_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ +/*! @{ */ + +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT0_MASK (0x1U) +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT0_SHIFT (0U) +/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT0_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT1_MASK (0x2U) +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT1_SHIFT (1U) +/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT1_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT2_MASK (0x4U) +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT2_SHIFT (2U) +/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT2_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT3_MASK (0x8U) +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT3_SHIFT (3U) +/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT3_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT4_MASK (0x10U) +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT4_SHIFT (4U) +/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT4_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT5_MASK (0x20U) +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT5_SHIFT (5U) +/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT5_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT6_MASK (0x40U) +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT6_SHIFT (6U) +/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT6_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT7_MASK (0x80U) +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT7_SHIFT (7U) +/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT7_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT8_MASK (0x100U) +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT8_SHIFT (8U) +/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT8_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT9_MASK (0x200U) +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT9_SHIFT (9U) +/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT9_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT10_MASK (0x400U) +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT10_SHIFT (10U) +/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT10_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT11_MASK (0x800U) +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT11_SHIFT (11U) +/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT11_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT12_MASK (0x1000U) +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT12_SHIFT (12U) +/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT12_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT13_MASK (0x2000U) +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT13_SHIFT (13U) +/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT13_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT14_MASK (0x4000U) +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT14_SHIFT (14U) +/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT14_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT15_MASK (0x8000U) +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT15_SHIFT (15U) +/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT15_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT16_MASK (0x10000U) +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT16_SHIFT (16U) +/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT16_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT17_MASK (0x20000U) +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT17_SHIFT (17U) +/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT17_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT18_MASK (0x40000U) +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT18_SHIFT (18U) +/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT18_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT19_MASK (0x80000U) +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT19_SHIFT (19U) +/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT19_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT20_MASK (0x100000U) +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT20_SHIFT (20U) +/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT20_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT21_MASK (0x200000U) +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT21_SHIFT (21U) +/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT21_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT22_MASK (0x400000U) +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT22_SHIFT (22U) +/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT22_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT23_MASK (0x800000U) +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT23_SHIFT (23U) +/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT23_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT24_MASK (0x1000000U) +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT24_SHIFT (24U) +/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT24_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT25_MASK (0x2000000U) +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT25_SHIFT (25U) +/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT25_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT26_MASK (0x4000000U) +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT26_SHIFT (26U) +/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT26_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT27_MASK (0x8000000U) +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT27_SHIFT (27U) +/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT27_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT28_MASK (0x10000000U) +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT28_SHIFT (28U) +/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT28_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT29_MASK (0x20000000U) +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT29_SHIFT (29U) +/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT29_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT30_MASK (0x40000000U) +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT30_SHIFT (30U) +/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT30_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT31_MASK (0x80000000U) +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT31_SHIFT (31U) +/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_BIT31_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W */ +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_COUNT (2U) + +/* The count of TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W */ +#define TRDC_MBC2_MBC_DOM14_MEM1_BLK_NSE_W_COUNT2 (1U) + +/*! @name MBC_DOM14_MEM2_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM2_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM2_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM2_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM2_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM2_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM2_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM2_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM2_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM2_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM2_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM2_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM2_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM2_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM2_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM2_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM2_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM2_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM2_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM2_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM2_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM2_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM2_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM2_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM2_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM2_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM2_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM2_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM2_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM2_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM2_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM2_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM2_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MBC_DOM14_MEM2_BLK_CFG_W */ +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_CFG_W_COUNT (2U) + +/* The count of TRDC_MBC2_MBC_DOM14_MEM2_BLK_CFG_W */ +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_CFG_W_COUNT2 (1U) + +/*! @name MBC_DOM14_MEM2_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ +/*! @{ */ + +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT0_MASK (0x1U) +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT0_SHIFT (0U) +/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT0_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT1_MASK (0x2U) +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT1_SHIFT (1U) +/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT1_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT2_MASK (0x4U) +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT2_SHIFT (2U) +/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT2_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT3_MASK (0x8U) +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT3_SHIFT (3U) +/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT3_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT4_MASK (0x10U) +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT4_SHIFT (4U) +/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT4_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT5_MASK (0x20U) +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT5_SHIFT (5U) +/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT5_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT6_MASK (0x40U) +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT6_SHIFT (6U) +/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT6_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT7_MASK (0x80U) +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT7_SHIFT (7U) +/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT7_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT8_MASK (0x100U) +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT8_SHIFT (8U) +/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT8_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT9_MASK (0x200U) +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT9_SHIFT (9U) +/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT9_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT10_MASK (0x400U) +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT10_SHIFT (10U) +/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT10_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT11_MASK (0x800U) +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT11_SHIFT (11U) +/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT11_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT12_MASK (0x1000U) +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT12_SHIFT (12U) +/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT12_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT13_MASK (0x2000U) +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT13_SHIFT (13U) +/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT13_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT14_MASK (0x4000U) +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT14_SHIFT (14U) +/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT14_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT15_MASK (0x8000U) +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT15_SHIFT (15U) +/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT15_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT16_MASK (0x10000U) +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT16_SHIFT (16U) +/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT16_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT17_MASK (0x20000U) +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT17_SHIFT (17U) +/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT17_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT18_MASK (0x40000U) +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT18_SHIFT (18U) +/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT18_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT19_MASK (0x80000U) +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT19_SHIFT (19U) +/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT19_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT20_MASK (0x100000U) +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT20_SHIFT (20U) +/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT20_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT21_MASK (0x200000U) +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT21_SHIFT (21U) +/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT21_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT22_MASK (0x400000U) +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT22_SHIFT (22U) +/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT22_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT23_MASK (0x800000U) +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT23_SHIFT (23U) +/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT23_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT24_MASK (0x1000000U) +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT24_SHIFT (24U) +/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT24_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT25_MASK (0x2000000U) +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT25_SHIFT (25U) +/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT25_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT26_MASK (0x4000000U) +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT26_SHIFT (26U) +/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT26_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT27_MASK (0x8000000U) +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT27_SHIFT (27U) +/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT27_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT28_MASK (0x10000000U) +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT28_SHIFT (28U) +/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT28_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT29_MASK (0x20000000U) +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT29_SHIFT (29U) +/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT29_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT30_MASK (0x40000000U) +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT30_SHIFT (30U) +/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT30_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT31_MASK (0x80000000U) +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT31_SHIFT (31U) +/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_BIT31_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W */ +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_COUNT (2U) + +/* The count of TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W */ +#define TRDC_MBC2_MBC_DOM14_MEM2_BLK_NSE_W_COUNT2 (1U) + +/*! @name MBC_DOM14_MEM3_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM3_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM3_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM3_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM3_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM3_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM3_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM3_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM3_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM3_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM3_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM3_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM3_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM3_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM3_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM3_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM3_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM3_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM3_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM3_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM3_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM3_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM3_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM3_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM3_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM3_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM3_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM3_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM3_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM3_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM3_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM3_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM3_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MBC_DOM14_MEM3_BLK_CFG_W */ +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_CFG_W_COUNT (2U) + +/* The count of TRDC_MBC2_MBC_DOM14_MEM3_BLK_CFG_W */ +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_CFG_W_COUNT2 (3U) + +/*! @name MBC_DOM14_MEM3_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ +/*! @{ */ + +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT0_MASK (0x1U) +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT0_SHIFT (0U) +/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT0_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT1_MASK (0x2U) +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT1_SHIFT (1U) +/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT1_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT2_MASK (0x4U) +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT2_SHIFT (2U) +/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT2_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT3_MASK (0x8U) +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT3_SHIFT (3U) +/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT3_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT4_MASK (0x10U) +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT4_SHIFT (4U) +/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT4_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT5_MASK (0x20U) +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT5_SHIFT (5U) +/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT5_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT6_MASK (0x40U) +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT6_SHIFT (6U) +/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT6_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT7_MASK (0x80U) +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT7_SHIFT (7U) +/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT7_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT8_MASK (0x100U) +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT8_SHIFT (8U) +/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT8_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT9_MASK (0x200U) +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT9_SHIFT (9U) +/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT9_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT10_MASK (0x400U) +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT10_SHIFT (10U) +/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT10_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT11_MASK (0x800U) +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT11_SHIFT (11U) +/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT11_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT12_MASK (0x1000U) +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT12_SHIFT (12U) +/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT12_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT13_MASK (0x2000U) +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT13_SHIFT (13U) +/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT13_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT14_MASK (0x4000U) +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT14_SHIFT (14U) +/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT14_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT15_MASK (0x8000U) +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT15_SHIFT (15U) +/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT15_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT16_MASK (0x10000U) +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT16_SHIFT (16U) +/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT16_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT17_MASK (0x20000U) +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT17_SHIFT (17U) +/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT17_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT18_MASK (0x40000U) +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT18_SHIFT (18U) +/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT18_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT19_MASK (0x80000U) +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT19_SHIFT (19U) +/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT19_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT20_MASK (0x100000U) +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT20_SHIFT (20U) +/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT20_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT21_MASK (0x200000U) +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT21_SHIFT (21U) +/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT21_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT22_MASK (0x400000U) +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT22_SHIFT (22U) +/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT22_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT23_MASK (0x800000U) +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT23_SHIFT (23U) +/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT23_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT24_MASK (0x1000000U) +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT24_SHIFT (24U) +/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT24_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT25_MASK (0x2000000U) +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT25_SHIFT (25U) +/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT25_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT26_MASK (0x4000000U) +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT26_SHIFT (26U) +/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT26_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT27_MASK (0x8000000U) +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT27_SHIFT (27U) +/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT27_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT28_MASK (0x10000000U) +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT28_SHIFT (28U) +/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT28_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT29_MASK (0x20000000U) +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT29_SHIFT (29U) +/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT29_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT30_MASK (0x40000000U) +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT30_SHIFT (30U) +/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT30_MASK) + +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT31_MASK (0x80000000U) +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT31_SHIFT (31U) +/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_BIT31_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W */ +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_COUNT (2U) + +/* The count of TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W */ +#define TRDC_MBC2_MBC_DOM14_MEM3_BLK_NSE_W_COUNT2 (1U) + +/*! @name MBC_DOM15_MEM0_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM0_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM0_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM0_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM0_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM0_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM0_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM0_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM0_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM0_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM0_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM0_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM0_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM0_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM0_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM0_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM0_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM0_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM0_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM0_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM0_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM0_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM0_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM0_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM0_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM0_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM0_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM0_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM0_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM0_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM0_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM0_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM0_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MBC_DOM15_MEM0_BLK_CFG_W */ +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_CFG_W_COUNT (2U) + +/* The count of TRDC_MBC2_MBC_DOM15_MEM0_BLK_CFG_W */ +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_CFG_W_COUNT2 (16U) + +/*! @name MBC_DOM15_MEM0_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ +/*! @{ */ + +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT0_MASK (0x1U) +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT0_SHIFT (0U) +/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT0_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT1_MASK (0x2U) +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT1_SHIFT (1U) +/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT1_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT2_MASK (0x4U) +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT2_SHIFT (2U) +/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT2_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT3_MASK (0x8U) +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT3_SHIFT (3U) +/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT3_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT4_MASK (0x10U) +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT4_SHIFT (4U) +/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT4_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT5_MASK (0x20U) +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT5_SHIFT (5U) +/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT5_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT6_MASK (0x40U) +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT6_SHIFT (6U) +/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT6_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT7_MASK (0x80U) +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT7_SHIFT (7U) +/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT7_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT8_MASK (0x100U) +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT8_SHIFT (8U) +/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT8_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT9_MASK (0x200U) +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT9_SHIFT (9U) +/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT9_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT10_MASK (0x400U) +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT10_SHIFT (10U) +/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT10_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT11_MASK (0x800U) +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT11_SHIFT (11U) +/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT11_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT12_MASK (0x1000U) +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT12_SHIFT (12U) +/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT12_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT13_MASK (0x2000U) +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT13_SHIFT (13U) +/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT13_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT14_MASK (0x4000U) +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT14_SHIFT (14U) +/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT14_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT15_MASK (0x8000U) +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT15_SHIFT (15U) +/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT15_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT16_MASK (0x10000U) +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT16_SHIFT (16U) +/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT16_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT17_MASK (0x20000U) +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT17_SHIFT (17U) +/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT17_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT18_MASK (0x40000U) +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT18_SHIFT (18U) +/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT18_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT19_MASK (0x80000U) +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT19_SHIFT (19U) +/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT19_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT20_MASK (0x100000U) +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT20_SHIFT (20U) +/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT20_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT21_MASK (0x200000U) +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT21_SHIFT (21U) +/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT21_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT22_MASK (0x400000U) +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT22_SHIFT (22U) +/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT22_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT23_MASK (0x800000U) +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT23_SHIFT (23U) +/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT23_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT24_MASK (0x1000000U) +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT24_SHIFT (24U) +/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT24_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT25_MASK (0x2000000U) +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT25_SHIFT (25U) +/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT25_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT26_MASK (0x4000000U) +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT26_SHIFT (26U) +/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT26_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT27_MASK (0x8000000U) +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT27_SHIFT (27U) +/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT27_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT28_MASK (0x10000000U) +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT28_SHIFT (28U) +/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT28_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT29_MASK (0x20000000U) +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT29_SHIFT (29U) +/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT29_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT30_MASK (0x40000000U) +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT30_SHIFT (30U) +/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT30_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT31_MASK (0x80000000U) +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT31_SHIFT (31U) +/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_BIT31_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W */ +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_COUNT (2U) + +/* The count of TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W */ +#define TRDC_MBC2_MBC_DOM15_MEM0_BLK_NSE_W_COUNT2 (4U) + +/*! @name MBC_DOM15_MEM1_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM1_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM1_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM1_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM1_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM1_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM1_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM1_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM1_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM1_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM1_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM1_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM1_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM1_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM1_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM1_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM1_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM1_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM1_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM1_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM1_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM1_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM1_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM1_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM1_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM1_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM1_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM1_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM1_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM1_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM1_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM1_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM1_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MBC_DOM15_MEM1_BLK_CFG_W */ +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_CFG_W_COUNT (2U) + +/* The count of TRDC_MBC2_MBC_DOM15_MEM1_BLK_CFG_W */ +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_CFG_W_COUNT2 (1U) + +/*! @name MBC_DOM15_MEM1_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ +/*! @{ */ + +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT0_MASK (0x1U) +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT0_SHIFT (0U) +/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT0_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT1_MASK (0x2U) +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT1_SHIFT (1U) +/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT1_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT2_MASK (0x4U) +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT2_SHIFT (2U) +/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT2_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT3_MASK (0x8U) +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT3_SHIFT (3U) +/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT3_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT4_MASK (0x10U) +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT4_SHIFT (4U) +/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT4_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT5_MASK (0x20U) +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT5_SHIFT (5U) +/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT5_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT6_MASK (0x40U) +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT6_SHIFT (6U) +/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT6_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT7_MASK (0x80U) +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT7_SHIFT (7U) +/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT7_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT8_MASK (0x100U) +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT8_SHIFT (8U) +/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT8_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT9_MASK (0x200U) +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT9_SHIFT (9U) +/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT9_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT10_MASK (0x400U) +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT10_SHIFT (10U) +/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT10_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT11_MASK (0x800U) +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT11_SHIFT (11U) +/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT11_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT12_MASK (0x1000U) +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT12_SHIFT (12U) +/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT12_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT13_MASK (0x2000U) +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT13_SHIFT (13U) +/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT13_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT14_MASK (0x4000U) +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT14_SHIFT (14U) +/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT14_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT15_MASK (0x8000U) +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT15_SHIFT (15U) +/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT15_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT16_MASK (0x10000U) +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT16_SHIFT (16U) +/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT16_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT17_MASK (0x20000U) +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT17_SHIFT (17U) +/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT17_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT18_MASK (0x40000U) +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT18_SHIFT (18U) +/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT18_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT19_MASK (0x80000U) +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT19_SHIFT (19U) +/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT19_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT20_MASK (0x100000U) +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT20_SHIFT (20U) +/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT20_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT21_MASK (0x200000U) +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT21_SHIFT (21U) +/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT21_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT22_MASK (0x400000U) +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT22_SHIFT (22U) +/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT22_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT23_MASK (0x800000U) +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT23_SHIFT (23U) +/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT23_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT24_MASK (0x1000000U) +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT24_SHIFT (24U) +/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT24_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT25_MASK (0x2000000U) +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT25_SHIFT (25U) +/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT25_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT26_MASK (0x4000000U) +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT26_SHIFT (26U) +/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT26_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT27_MASK (0x8000000U) +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT27_SHIFT (27U) +/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT27_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT28_MASK (0x10000000U) +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT28_SHIFT (28U) +/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT28_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT29_MASK (0x20000000U) +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT29_SHIFT (29U) +/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT29_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT30_MASK (0x40000000U) +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT30_SHIFT (30U) +/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT30_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT31_MASK (0x80000000U) +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT31_SHIFT (31U) +/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_BIT31_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W */ +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_COUNT (2U) + +/* The count of TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W */ +#define TRDC_MBC2_MBC_DOM15_MEM1_BLK_NSE_W_COUNT2 (1U) + +/*! @name MBC_DOM15_MEM2_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM2_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM2_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM2_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM2_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM2_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM2_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM2_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM2_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM2_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM2_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM2_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM2_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM2_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM2_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM2_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM2_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM2_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM2_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM2_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM2_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM2_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM2_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM2_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM2_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM2_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM2_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM2_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM2_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM2_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM2_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM2_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM2_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MBC_DOM15_MEM2_BLK_CFG_W */ +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_CFG_W_COUNT (2U) + +/* The count of TRDC_MBC2_MBC_DOM15_MEM2_BLK_CFG_W */ +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_CFG_W_COUNT2 (1U) + +/*! @name MBC_DOM15_MEM2_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ +/*! @{ */ + +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT0_MASK (0x1U) +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT0_SHIFT (0U) +/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT0_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT1_MASK (0x2U) +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT1_SHIFT (1U) +/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT1_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT2_MASK (0x4U) +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT2_SHIFT (2U) +/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT2_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT3_MASK (0x8U) +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT3_SHIFT (3U) +/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT3_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT4_MASK (0x10U) +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT4_SHIFT (4U) +/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT4_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT5_MASK (0x20U) +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT5_SHIFT (5U) +/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT5_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT6_MASK (0x40U) +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT6_SHIFT (6U) +/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT6_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT7_MASK (0x80U) +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT7_SHIFT (7U) +/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT7_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT8_MASK (0x100U) +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT8_SHIFT (8U) +/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT8_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT9_MASK (0x200U) +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT9_SHIFT (9U) +/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT9_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT10_MASK (0x400U) +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT10_SHIFT (10U) +/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT10_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT11_MASK (0x800U) +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT11_SHIFT (11U) +/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT11_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT12_MASK (0x1000U) +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT12_SHIFT (12U) +/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT12_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT13_MASK (0x2000U) +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT13_SHIFT (13U) +/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT13_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT14_MASK (0x4000U) +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT14_SHIFT (14U) +/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT14_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT15_MASK (0x8000U) +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT15_SHIFT (15U) +/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT15_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT16_MASK (0x10000U) +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT16_SHIFT (16U) +/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT16_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT17_MASK (0x20000U) +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT17_SHIFT (17U) +/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT17_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT18_MASK (0x40000U) +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT18_SHIFT (18U) +/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT18_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT19_MASK (0x80000U) +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT19_SHIFT (19U) +/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT19_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT20_MASK (0x100000U) +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT20_SHIFT (20U) +/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT20_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT21_MASK (0x200000U) +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT21_SHIFT (21U) +/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT21_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT22_MASK (0x400000U) +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT22_SHIFT (22U) +/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT22_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT23_MASK (0x800000U) +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT23_SHIFT (23U) +/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT23_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT24_MASK (0x1000000U) +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT24_SHIFT (24U) +/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT24_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT25_MASK (0x2000000U) +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT25_SHIFT (25U) +/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT25_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT26_MASK (0x4000000U) +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT26_SHIFT (26U) +/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT26_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT27_MASK (0x8000000U) +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT27_SHIFT (27U) +/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT27_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT28_MASK (0x10000000U) +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT28_SHIFT (28U) +/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT28_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT29_MASK (0x20000000U) +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT29_SHIFT (29U) +/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT29_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT30_MASK (0x40000000U) +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT30_SHIFT (30U) +/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT30_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT31_MASK (0x80000000U) +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT31_SHIFT (31U) +/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_BIT31_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W */ +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_COUNT (2U) + +/* The count of TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W */ +#define TRDC_MBC2_MBC_DOM15_MEM2_BLK_NSE_W_COUNT2 (1U) + +/*! @name MBC_DOM15_MEM3_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM3_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM3_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM3_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM3_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM3_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM3_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM3_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM3_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM3_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM3_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM3_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM3_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM3_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM3_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM3_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM3_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM3_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM3_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM3_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM3_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM3_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM3_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM3_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM3_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM3_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM3_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM3_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM3_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM3_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM3_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM3_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM3_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MBC_DOM15_MEM3_BLK_CFG_W */ +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_CFG_W_COUNT (2U) + +/* The count of TRDC_MBC2_MBC_DOM15_MEM3_BLK_CFG_W */ +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_CFG_W_COUNT2 (3U) + +/*! @name MBC_DOM15_MEM3_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ +/*! @{ */ + +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT0_MASK (0x1U) +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT0_SHIFT (0U) +/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT0_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT1_MASK (0x2U) +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT1_SHIFT (1U) +/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT1_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT2_MASK (0x4U) +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT2_SHIFT (2U) +/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT2_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT3_MASK (0x8U) +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT3_SHIFT (3U) +/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT3_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT4_MASK (0x10U) +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT4_SHIFT (4U) +/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT4_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT5_MASK (0x20U) +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT5_SHIFT (5U) +/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT5_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT6_MASK (0x40U) +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT6_SHIFT (6U) +/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT6_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT7_MASK (0x80U) +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT7_SHIFT (7U) +/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT7_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT8_MASK (0x100U) +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT8_SHIFT (8U) +/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT8_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT9_MASK (0x200U) +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT9_SHIFT (9U) +/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT9_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT10_MASK (0x400U) +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT10_SHIFT (10U) +/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT10_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT11_MASK (0x800U) +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT11_SHIFT (11U) +/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT11_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT12_MASK (0x1000U) +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT12_SHIFT (12U) +/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT12_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT13_MASK (0x2000U) +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT13_SHIFT (13U) +/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT13_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT14_MASK (0x4000U) +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT14_SHIFT (14U) +/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT14_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT15_MASK (0x8000U) +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT15_SHIFT (15U) +/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT15_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT16_MASK (0x10000U) +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT16_SHIFT (16U) +/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT16_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT17_MASK (0x20000U) +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT17_SHIFT (17U) +/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT17_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT18_MASK (0x40000U) +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT18_SHIFT (18U) +/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT18_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT19_MASK (0x80000U) +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT19_SHIFT (19U) +/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT19_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT20_MASK (0x100000U) +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT20_SHIFT (20U) +/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT20_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT21_MASK (0x200000U) +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT21_SHIFT (21U) +/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT21_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT22_MASK (0x400000U) +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT22_SHIFT (22U) +/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT22_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT23_MASK (0x800000U) +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT23_SHIFT (23U) +/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT23_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT24_MASK (0x1000000U) +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT24_SHIFT (24U) +/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT24_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT25_MASK (0x2000000U) +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT25_SHIFT (25U) +/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT25_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT26_MASK (0x4000000U) +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT26_SHIFT (26U) +/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT26_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT27_MASK (0x8000000U) +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT27_SHIFT (27U) +/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT27_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT28_MASK (0x10000000U) +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT28_SHIFT (28U) +/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT28_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT29_MASK (0x20000000U) +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT29_SHIFT (29U) +/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT29_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT30_MASK (0x40000000U) +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT30_SHIFT (30U) +/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT30_MASK) + +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT31_MASK (0x80000000U) +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT31_SHIFT (31U) +/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_BIT31_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W */ +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_COUNT (2U) + +/* The count of TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W */ +#define TRDC_MBC2_MBC_DOM15_MEM3_BLK_NSE_W_COUNT2 (1U) + +/*! @name MRC_GLBCFG - MRC Global Configuration Register */ +/*! @{ */ + +#define TRDC_MBC2_MRC_GLBCFG_NRGNS_MASK (0x1FU) +#define TRDC_MBC2_MRC_GLBCFG_NRGNS_SHIFT (0U) +/*! NRGNS - Number of regions [1-16] */ +#define TRDC_MBC2_MRC_GLBCFG_NRGNS(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_GLBCFG_NRGNS_SHIFT)) & TRDC_MBC2_MRC_GLBCFG_NRGNS_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MRC_GLBCFG */ +#define TRDC_MBC2_MRC_GLBCFG_COUNT (2U) + +/*! @name MRC_NSE_RGN_INDIRECT - MRC NonSecure Enable Region Indirect */ +/*! @{ */ + +#define TRDC_MBC2_MRC_NSE_RGN_INDIRECT_DID_SEL_MASK (0xFFFF0000U) +#define TRDC_MBC2_MRC_NSE_RGN_INDIRECT_DID_SEL_SHIFT (16U) +/*! DID_SEL - DID Select */ +#define TRDC_MBC2_MRC_NSE_RGN_INDIRECT_DID_SEL(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_NSE_RGN_INDIRECT_DID_SEL_SHIFT)) & TRDC_MBC2_MRC_NSE_RGN_INDIRECT_DID_SEL_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MRC_NSE_RGN_INDIRECT */ +#define TRDC_MBC2_MRC_NSE_RGN_INDIRECT_COUNT (2U) + +/*! @name MRC_NSE_RGN_SET - MRC NonSecure Enable Region Set */ +/*! @{ */ + +#define TRDC_MBC2_MRC_NSE_RGN_SET_W1SET_MASK (0xFFFFU) +#define TRDC_MBC2_MRC_NSE_RGN_SET_W1SET_SHIFT (0U) +/*! W1SET - Write-1 Set */ +#define TRDC_MBC2_MRC_NSE_RGN_SET_W1SET(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_NSE_RGN_SET_W1SET_SHIFT)) & TRDC_MBC2_MRC_NSE_RGN_SET_W1SET_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MRC_NSE_RGN_SET */ +#define TRDC_MBC2_MRC_NSE_RGN_SET_COUNT (2U) + +/*! @name MRC_NSE_RGN_CLR - MRC NonSecure Enable Region Clear */ +/*! @{ */ + +#define TRDC_MBC2_MRC_NSE_RGN_CLR_W1CLR_MASK (0xFFFFU) +#define TRDC_MBC2_MRC_NSE_RGN_CLR_W1CLR_SHIFT (0U) +/*! W1CLR - Write-1 Clear */ +#define TRDC_MBC2_MRC_NSE_RGN_CLR_W1CLR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_NSE_RGN_CLR_W1CLR_SHIFT)) & TRDC_MBC2_MRC_NSE_RGN_CLR_W1CLR_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MRC_NSE_RGN_CLR */ +#define TRDC_MBC2_MRC_NSE_RGN_CLR_COUNT (2U) + +/*! @name MRC_NSE_RGN_CLR_ALL - MRC NonSecure Enable Region Clear All */ +/*! @{ */ + +#define TRDC_MBC2_MRC_NSE_RGN_CLR_ALL_DID_SEL_MASK (0xFFFF0000U) +#define TRDC_MBC2_MRC_NSE_RGN_CLR_ALL_DID_SEL_SHIFT (16U) +/*! DID_SEL - DID Select */ +#define TRDC_MBC2_MRC_NSE_RGN_CLR_ALL_DID_SEL(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_NSE_RGN_CLR_ALL_DID_SEL_SHIFT)) & TRDC_MBC2_MRC_NSE_RGN_CLR_ALL_DID_SEL_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MRC_NSE_RGN_CLR_ALL */ +#define TRDC_MBC2_MRC_NSE_RGN_CLR_ALL_COUNT (2U) + +/*! @name MRC_GLBAC - MRC Global Access Control */ +/*! @{ */ + +#define TRDC_MBC2_MRC_GLBAC_NUX_MASK (0x1U) +#define TRDC_MBC2_MRC_GLBAC_NUX_SHIFT (0U) +/*! NUX - NonsecureUser Execute + * 0b0..Execute access is not allowed in Nonsecure User mode. + * 0b1..Execute access is allowed in Nonsecure User mode. + */ +#define TRDC_MBC2_MRC_GLBAC_NUX(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_GLBAC_NUX_SHIFT)) & TRDC_MBC2_MRC_GLBAC_NUX_MASK) + +#define TRDC_MBC2_MRC_GLBAC_NUW_MASK (0x2U) +#define TRDC_MBC2_MRC_GLBAC_NUW_SHIFT (1U) +/*! NUW - NonsecureUser Write + * 0b0..Write access is not allowed in Nonsecure User mode. + * 0b1..Write access is allowed in Nonsecure User mode. + */ +#define TRDC_MBC2_MRC_GLBAC_NUW(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_GLBAC_NUW_SHIFT)) & TRDC_MBC2_MRC_GLBAC_NUW_MASK) + +#define TRDC_MBC2_MRC_GLBAC_NUR_MASK (0x4U) +#define TRDC_MBC2_MRC_GLBAC_NUR_SHIFT (2U) +/*! NUR - NonsecureUser Read + * 0b0..Read access is not allowed in Nonsecure User mode. + * 0b1..Read access is allowed in Nonsecure User mode. + */ +#define TRDC_MBC2_MRC_GLBAC_NUR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_GLBAC_NUR_SHIFT)) & TRDC_MBC2_MRC_GLBAC_NUR_MASK) + +#define TRDC_MBC2_MRC_GLBAC_NPX_MASK (0x10U) +#define TRDC_MBC2_MRC_GLBAC_NPX_SHIFT (4U) +/*! NPX - NonsecurePriv Execute + * 0b0..Execute access is not allowed in Nonsecure Privilege mode. + * 0b1..Execute access is allowed in Nonsecure Privilege mode. + */ +#define TRDC_MBC2_MRC_GLBAC_NPX(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_GLBAC_NPX_SHIFT)) & TRDC_MBC2_MRC_GLBAC_NPX_MASK) + +#define TRDC_MBC2_MRC_GLBAC_NPW_MASK (0x20U) +#define TRDC_MBC2_MRC_GLBAC_NPW_SHIFT (5U) +/*! NPW - NonsecurePriv Write + * 0b0..Write access is not allowed in Nonsecure Privilege mode. + * 0b1..Write access is allowed in Nonsecure Privilege mode. + */ +#define TRDC_MBC2_MRC_GLBAC_NPW(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_GLBAC_NPW_SHIFT)) & TRDC_MBC2_MRC_GLBAC_NPW_MASK) + +#define TRDC_MBC2_MRC_GLBAC_NPR_MASK (0x40U) +#define TRDC_MBC2_MRC_GLBAC_NPR_SHIFT (6U) +/*! NPR - NonsecurePriv Read + * 0b0..Read access is not allowed in Nonsecure Privilege mode. + * 0b1..Read access is allowed in Nonsecure Privilege mode. + */ +#define TRDC_MBC2_MRC_GLBAC_NPR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_GLBAC_NPR_SHIFT)) & TRDC_MBC2_MRC_GLBAC_NPR_MASK) + +#define TRDC_MBC2_MRC_GLBAC_SUX_MASK (0x100U) +#define TRDC_MBC2_MRC_GLBAC_SUX_SHIFT (8U) +/*! SUX - SecureUser Execute + * 0b0..Execute access is not allowed in Secure User mode. + * 0b1..Execute access is allowed in Secure User mode. + */ +#define TRDC_MBC2_MRC_GLBAC_SUX(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_GLBAC_SUX_SHIFT)) & TRDC_MBC2_MRC_GLBAC_SUX_MASK) + +#define TRDC_MBC2_MRC_GLBAC_SUW_MASK (0x200U) +#define TRDC_MBC2_MRC_GLBAC_SUW_SHIFT (9U) +/*! SUW - SecureUser Write + * 0b0..Write access is not allowed in Secure User mode. + * 0b1..Write access is allowed in Secure User mode. + */ +#define TRDC_MBC2_MRC_GLBAC_SUW(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_GLBAC_SUW_SHIFT)) & TRDC_MBC2_MRC_GLBAC_SUW_MASK) + +#define TRDC_MBC2_MRC_GLBAC_SUR_MASK (0x400U) +#define TRDC_MBC2_MRC_GLBAC_SUR_SHIFT (10U) +/*! SUR - SecureUser Read + * 0b0..Read access is not allowed in Secure User mode. + * 0b1..Read access is allowed in Secure User mode. + */ +#define TRDC_MBC2_MRC_GLBAC_SUR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_GLBAC_SUR_SHIFT)) & TRDC_MBC2_MRC_GLBAC_SUR_MASK) + +#define TRDC_MBC2_MRC_GLBAC_SPX_MASK (0x1000U) +#define TRDC_MBC2_MRC_GLBAC_SPX_SHIFT (12U) +/*! SPX - SecurePriv Execute + * 0b0..Execute access is not allowed in Secure Privilege mode. + * 0b1..Execute access is allowed in Secure Privilege mode. + */ +#define TRDC_MBC2_MRC_GLBAC_SPX(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_GLBAC_SPX_SHIFT)) & TRDC_MBC2_MRC_GLBAC_SPX_MASK) + +#define TRDC_MBC2_MRC_GLBAC_SPW_MASK (0x2000U) +#define TRDC_MBC2_MRC_GLBAC_SPW_SHIFT (13U) +/*! SPW - SecurePriv Write + * 0b0..Write access is not allowed in Secure Privilege mode. + * 0b1..Write access is allowed in Secure Privilege mode. + */ +#define TRDC_MBC2_MRC_GLBAC_SPW(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_GLBAC_SPW_SHIFT)) & TRDC_MBC2_MRC_GLBAC_SPW_MASK) + +#define TRDC_MBC2_MRC_GLBAC_SPR_MASK (0x4000U) +#define TRDC_MBC2_MRC_GLBAC_SPR_SHIFT (14U) +/*! SPR - SecurePriv Read + * 0b0..Read access is not allowed in Secure Privilege mode. + * 0b1..Read access is allowed in Secure Privilege mode. + */ +#define TRDC_MBC2_MRC_GLBAC_SPR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_GLBAC_SPR_SHIFT)) & TRDC_MBC2_MRC_GLBAC_SPR_MASK) + +#define TRDC_MBC2_MRC_GLBAC_LK_MASK (0x80000000U) +#define TRDC_MBC2_MRC_GLBAC_LK_SHIFT (31U) +/*! LK - LOCK + * 0b0..This register is not locked and can be altered. + * 0b1..This register is locked (read-only) and cannot be altered. + */ +#define TRDC_MBC2_MRC_GLBAC_LK(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_GLBAC_LK_SHIFT)) & TRDC_MBC2_MRC_GLBAC_LK_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MRC_GLBAC */ +#define TRDC_MBC2_MRC_GLBAC_COUNT (2U) + +/* The count of TRDC_MBC2_MRC_GLBAC */ +#define TRDC_MBC2_MRC_GLBAC_COUNT2 (8U) + +/*! @name MRC_DOM0_RGD_W - MRC Region Descriptor Word 0..MRC Region Descriptor Word 1 */ +/*! @{ */ + +#define TRDC_MBC2_MRC_DOM0_RGD_W_MRACSEL_MASK (0x7U) +#define TRDC_MBC2_MRC_DOM0_RGD_W_MRACSEL_SHIFT (0U) +/*! MRACSEL - Memory Region Access Control Select + * 0b000..Select MRC_GLBAC0 access control policy + * 0b001..Select MRC_GLBAC1 access control policy + * 0b010..Select MRC_GLBAC2 access control policy + * 0b011..Select MRC_GLBAC3 access control policy + * 0b100..Select MRC_GLBAC4 access control policy + * 0b101..Select MRC_GLBAC5 access control policy + * 0b110..Select MRC_GLBAC6 access control policy + * 0b111..Select MRC_GLBAC7 access control policy + */ +#define TRDC_MBC2_MRC_DOM0_RGD_W_MRACSEL(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM0_RGD_W_MRACSEL_SHIFT)) & TRDC_MBC2_MRC_DOM0_RGD_W_MRACSEL_MASK) + +#define TRDC_MBC2_MRC_DOM0_RGD_W_VLD_MASK (0x1U) +#define TRDC_MBC2_MRC_DOM0_RGD_W_VLD_SHIFT (0U) +/*! VLD - Valid */ +#define TRDC_MBC2_MRC_DOM0_RGD_W_VLD(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM0_RGD_W_VLD_SHIFT)) & TRDC_MBC2_MRC_DOM0_RGD_W_VLD_MASK) + +#define TRDC_MBC2_MRC_DOM0_RGD_W_NSE_MASK (0x10U) +#define TRDC_MBC2_MRC_DOM0_RGD_W_NSE_SHIFT (4U) +/*! NSE - NonSecure Enable + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in this register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM0_RGD_W_NSE(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM0_RGD_W_NSE_SHIFT)) & TRDC_MBC2_MRC_DOM0_RGD_W_NSE_MASK) + +#define TRDC_MBC2_MRC_DOM0_RGD_W_END_ADDR_MASK (0xFFFFC000U) +#define TRDC_MBC2_MRC_DOM0_RGD_W_END_ADDR_SHIFT (14U) +/*! END_ADDR - End Address */ +#define TRDC_MBC2_MRC_DOM0_RGD_W_END_ADDR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM0_RGD_W_END_ADDR_SHIFT)) & TRDC_MBC2_MRC_DOM0_RGD_W_END_ADDR_MASK) + +#define TRDC_MBC2_MRC_DOM0_RGD_W_STRT_ADDR_MASK (0xFFFFC000U) +#define TRDC_MBC2_MRC_DOM0_RGD_W_STRT_ADDR_SHIFT (14U) +/*! STRT_ADDR - Start Address */ +#define TRDC_MBC2_MRC_DOM0_RGD_W_STRT_ADDR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM0_RGD_W_STRT_ADDR_SHIFT)) & TRDC_MBC2_MRC_DOM0_RGD_W_STRT_ADDR_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MRC_DOM0_RGD_W */ +#define TRDC_MBC2_MRC_DOM0_RGD_W_COUNT (2U) + +/* The count of TRDC_MBC2_MRC_DOM0_RGD_W */ +#define TRDC_MBC2_MRC_DOM0_RGD_W_COUNT2 (8U) + +/* The count of TRDC_MBC2_MRC_DOM0_RGD_W */ +#define TRDC_MBC2_MRC_DOM0_RGD_W_COUNT3 (2U) + +/*! @name MRC_DOM0_RGD_NSE - MRC Region Descriptor NonSecure Enable */ +/*! @{ */ + +#define TRDC_MBC2_MRC_DOM0_RGD_NSE_BIT0_MASK (0x1U) +#define TRDC_MBC2_MRC_DOM0_RGD_NSE_BIT0_SHIFT (0U) +/*! BIT0 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM0_RGD_NSE_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM0_RGD_NSE_BIT0_SHIFT)) & TRDC_MBC2_MRC_DOM0_RGD_NSE_BIT0_MASK) + +#define TRDC_MBC2_MRC_DOM0_RGD_NSE_BIT1_MASK (0x2U) +#define TRDC_MBC2_MRC_DOM0_RGD_NSE_BIT1_SHIFT (1U) +/*! BIT1 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM0_RGD_NSE_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM0_RGD_NSE_BIT1_SHIFT)) & TRDC_MBC2_MRC_DOM0_RGD_NSE_BIT1_MASK) + +#define TRDC_MBC2_MRC_DOM0_RGD_NSE_BIT2_MASK (0x4U) +#define TRDC_MBC2_MRC_DOM0_RGD_NSE_BIT2_SHIFT (2U) +/*! BIT2 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM0_RGD_NSE_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM0_RGD_NSE_BIT2_SHIFT)) & TRDC_MBC2_MRC_DOM0_RGD_NSE_BIT2_MASK) + +#define TRDC_MBC2_MRC_DOM0_RGD_NSE_BIT3_MASK (0x8U) +#define TRDC_MBC2_MRC_DOM0_RGD_NSE_BIT3_SHIFT (3U) +/*! BIT3 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM0_RGD_NSE_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM0_RGD_NSE_BIT3_SHIFT)) & TRDC_MBC2_MRC_DOM0_RGD_NSE_BIT3_MASK) + +#define TRDC_MBC2_MRC_DOM0_RGD_NSE_BIT4_MASK (0x10U) +#define TRDC_MBC2_MRC_DOM0_RGD_NSE_BIT4_SHIFT (4U) +/*! BIT4 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM0_RGD_NSE_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM0_RGD_NSE_BIT4_SHIFT)) & TRDC_MBC2_MRC_DOM0_RGD_NSE_BIT4_MASK) + +#define TRDC_MBC2_MRC_DOM0_RGD_NSE_BIT5_MASK (0x20U) +#define TRDC_MBC2_MRC_DOM0_RGD_NSE_BIT5_SHIFT (5U) +/*! BIT5 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM0_RGD_NSE_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM0_RGD_NSE_BIT5_SHIFT)) & TRDC_MBC2_MRC_DOM0_RGD_NSE_BIT5_MASK) + +#define TRDC_MBC2_MRC_DOM0_RGD_NSE_BIT6_MASK (0x40U) +#define TRDC_MBC2_MRC_DOM0_RGD_NSE_BIT6_SHIFT (6U) +/*! BIT6 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM0_RGD_NSE_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM0_RGD_NSE_BIT6_SHIFT)) & TRDC_MBC2_MRC_DOM0_RGD_NSE_BIT6_MASK) + +#define TRDC_MBC2_MRC_DOM0_RGD_NSE_BIT7_MASK (0x80U) +#define TRDC_MBC2_MRC_DOM0_RGD_NSE_BIT7_SHIFT (7U) +/*! BIT7 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM0_RGD_NSE_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM0_RGD_NSE_BIT7_SHIFT)) & TRDC_MBC2_MRC_DOM0_RGD_NSE_BIT7_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MRC_DOM0_RGD_NSE */ +#define TRDC_MBC2_MRC_DOM0_RGD_NSE_COUNT (2U) + +/*! @name MRC_DOM1_RGD_W - MRC Region Descriptor Word 0..MRC Region Descriptor Word 1 */ +/*! @{ */ + +#define TRDC_MBC2_MRC_DOM1_RGD_W_MRACSEL_MASK (0x7U) +#define TRDC_MBC2_MRC_DOM1_RGD_W_MRACSEL_SHIFT (0U) +/*! MRACSEL - Memory Region Access Control Select + * 0b000..Select MRC_GLBAC0 access control policy + * 0b001..Select MRC_GLBAC1 access control policy + * 0b010..Select MRC_GLBAC2 access control policy + * 0b011..Select MRC_GLBAC3 access control policy + * 0b100..Select MRC_GLBAC4 access control policy + * 0b101..Select MRC_GLBAC5 access control policy + * 0b110..Select MRC_GLBAC6 access control policy + * 0b111..Select MRC_GLBAC7 access control policy + */ +#define TRDC_MBC2_MRC_DOM1_RGD_W_MRACSEL(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM1_RGD_W_MRACSEL_SHIFT)) & TRDC_MBC2_MRC_DOM1_RGD_W_MRACSEL_MASK) + +#define TRDC_MBC2_MRC_DOM1_RGD_W_VLD_MASK (0x1U) +#define TRDC_MBC2_MRC_DOM1_RGD_W_VLD_SHIFT (0U) +/*! VLD - Valid */ +#define TRDC_MBC2_MRC_DOM1_RGD_W_VLD(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM1_RGD_W_VLD_SHIFT)) & TRDC_MBC2_MRC_DOM1_RGD_W_VLD_MASK) + +#define TRDC_MBC2_MRC_DOM1_RGD_W_NSE_MASK (0x10U) +#define TRDC_MBC2_MRC_DOM1_RGD_W_NSE_SHIFT (4U) +/*! NSE - NonSecure Enable + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in this register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM1_RGD_W_NSE(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM1_RGD_W_NSE_SHIFT)) & TRDC_MBC2_MRC_DOM1_RGD_W_NSE_MASK) + +#define TRDC_MBC2_MRC_DOM1_RGD_W_END_ADDR_MASK (0xFFFFC000U) +#define TRDC_MBC2_MRC_DOM1_RGD_W_END_ADDR_SHIFT (14U) +/*! END_ADDR - End Address */ +#define TRDC_MBC2_MRC_DOM1_RGD_W_END_ADDR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM1_RGD_W_END_ADDR_SHIFT)) & TRDC_MBC2_MRC_DOM1_RGD_W_END_ADDR_MASK) + +#define TRDC_MBC2_MRC_DOM1_RGD_W_STRT_ADDR_MASK (0xFFFFC000U) +#define TRDC_MBC2_MRC_DOM1_RGD_W_STRT_ADDR_SHIFT (14U) +/*! STRT_ADDR - Start Address */ +#define TRDC_MBC2_MRC_DOM1_RGD_W_STRT_ADDR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM1_RGD_W_STRT_ADDR_SHIFT)) & TRDC_MBC2_MRC_DOM1_RGD_W_STRT_ADDR_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MRC_DOM1_RGD_W */ +#define TRDC_MBC2_MRC_DOM1_RGD_W_COUNT (2U) + +/* The count of TRDC_MBC2_MRC_DOM1_RGD_W */ +#define TRDC_MBC2_MRC_DOM1_RGD_W_COUNT2 (8U) + +/* The count of TRDC_MBC2_MRC_DOM1_RGD_W */ +#define TRDC_MBC2_MRC_DOM1_RGD_W_COUNT3 (2U) + +/*! @name MRC_DOM1_RGD_NSE - MRC Region Descriptor NonSecure Enable */ +/*! @{ */ + +#define TRDC_MBC2_MRC_DOM1_RGD_NSE_BIT0_MASK (0x1U) +#define TRDC_MBC2_MRC_DOM1_RGD_NSE_BIT0_SHIFT (0U) +/*! BIT0 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM1_RGD_NSE_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM1_RGD_NSE_BIT0_SHIFT)) & TRDC_MBC2_MRC_DOM1_RGD_NSE_BIT0_MASK) + +#define TRDC_MBC2_MRC_DOM1_RGD_NSE_BIT1_MASK (0x2U) +#define TRDC_MBC2_MRC_DOM1_RGD_NSE_BIT1_SHIFT (1U) +/*! BIT1 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM1_RGD_NSE_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM1_RGD_NSE_BIT1_SHIFT)) & TRDC_MBC2_MRC_DOM1_RGD_NSE_BIT1_MASK) + +#define TRDC_MBC2_MRC_DOM1_RGD_NSE_BIT2_MASK (0x4U) +#define TRDC_MBC2_MRC_DOM1_RGD_NSE_BIT2_SHIFT (2U) +/*! BIT2 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM1_RGD_NSE_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM1_RGD_NSE_BIT2_SHIFT)) & TRDC_MBC2_MRC_DOM1_RGD_NSE_BIT2_MASK) + +#define TRDC_MBC2_MRC_DOM1_RGD_NSE_BIT3_MASK (0x8U) +#define TRDC_MBC2_MRC_DOM1_RGD_NSE_BIT3_SHIFT (3U) +/*! BIT3 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM1_RGD_NSE_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM1_RGD_NSE_BIT3_SHIFT)) & TRDC_MBC2_MRC_DOM1_RGD_NSE_BIT3_MASK) + +#define TRDC_MBC2_MRC_DOM1_RGD_NSE_BIT4_MASK (0x10U) +#define TRDC_MBC2_MRC_DOM1_RGD_NSE_BIT4_SHIFT (4U) +/*! BIT4 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM1_RGD_NSE_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM1_RGD_NSE_BIT4_SHIFT)) & TRDC_MBC2_MRC_DOM1_RGD_NSE_BIT4_MASK) + +#define TRDC_MBC2_MRC_DOM1_RGD_NSE_BIT5_MASK (0x20U) +#define TRDC_MBC2_MRC_DOM1_RGD_NSE_BIT5_SHIFT (5U) +/*! BIT5 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM1_RGD_NSE_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM1_RGD_NSE_BIT5_SHIFT)) & TRDC_MBC2_MRC_DOM1_RGD_NSE_BIT5_MASK) + +#define TRDC_MBC2_MRC_DOM1_RGD_NSE_BIT6_MASK (0x40U) +#define TRDC_MBC2_MRC_DOM1_RGD_NSE_BIT6_SHIFT (6U) +/*! BIT6 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM1_RGD_NSE_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM1_RGD_NSE_BIT6_SHIFT)) & TRDC_MBC2_MRC_DOM1_RGD_NSE_BIT6_MASK) + +#define TRDC_MBC2_MRC_DOM1_RGD_NSE_BIT7_MASK (0x80U) +#define TRDC_MBC2_MRC_DOM1_RGD_NSE_BIT7_SHIFT (7U) +/*! BIT7 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM1_RGD_NSE_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM1_RGD_NSE_BIT7_SHIFT)) & TRDC_MBC2_MRC_DOM1_RGD_NSE_BIT7_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MRC_DOM1_RGD_NSE */ +#define TRDC_MBC2_MRC_DOM1_RGD_NSE_COUNT (2U) + +/*! @name MRC_DOM2_RGD_W - MRC Region Descriptor Word 0..MRC Region Descriptor Word 1 */ +/*! @{ */ + +#define TRDC_MBC2_MRC_DOM2_RGD_W_MRACSEL_MASK (0x7U) +#define TRDC_MBC2_MRC_DOM2_RGD_W_MRACSEL_SHIFT (0U) +/*! MRACSEL - Memory Region Access Control Select + * 0b000..Select MRC_GLBAC0 access control policy + * 0b001..Select MRC_GLBAC1 access control policy + * 0b010..Select MRC_GLBAC2 access control policy + * 0b011..Select MRC_GLBAC3 access control policy + * 0b100..Select MRC_GLBAC4 access control policy + * 0b101..Select MRC_GLBAC5 access control policy + * 0b110..Select MRC_GLBAC6 access control policy + * 0b111..Select MRC_GLBAC7 access control policy + */ +#define TRDC_MBC2_MRC_DOM2_RGD_W_MRACSEL(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM2_RGD_W_MRACSEL_SHIFT)) & TRDC_MBC2_MRC_DOM2_RGD_W_MRACSEL_MASK) + +#define TRDC_MBC2_MRC_DOM2_RGD_W_VLD_MASK (0x1U) +#define TRDC_MBC2_MRC_DOM2_RGD_W_VLD_SHIFT (0U) +/*! VLD - Valid */ +#define TRDC_MBC2_MRC_DOM2_RGD_W_VLD(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM2_RGD_W_VLD_SHIFT)) & TRDC_MBC2_MRC_DOM2_RGD_W_VLD_MASK) + +#define TRDC_MBC2_MRC_DOM2_RGD_W_NSE_MASK (0x10U) +#define TRDC_MBC2_MRC_DOM2_RGD_W_NSE_SHIFT (4U) +/*! NSE - NonSecure Enable + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in this register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM2_RGD_W_NSE(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM2_RGD_W_NSE_SHIFT)) & TRDC_MBC2_MRC_DOM2_RGD_W_NSE_MASK) + +#define TRDC_MBC2_MRC_DOM2_RGD_W_END_ADDR_MASK (0xFFFFC000U) +#define TRDC_MBC2_MRC_DOM2_RGD_W_END_ADDR_SHIFT (14U) +/*! END_ADDR - End Address */ +#define TRDC_MBC2_MRC_DOM2_RGD_W_END_ADDR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM2_RGD_W_END_ADDR_SHIFT)) & TRDC_MBC2_MRC_DOM2_RGD_W_END_ADDR_MASK) + +#define TRDC_MBC2_MRC_DOM2_RGD_W_STRT_ADDR_MASK (0xFFFFC000U) +#define TRDC_MBC2_MRC_DOM2_RGD_W_STRT_ADDR_SHIFT (14U) +/*! STRT_ADDR - Start Address */ +#define TRDC_MBC2_MRC_DOM2_RGD_W_STRT_ADDR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM2_RGD_W_STRT_ADDR_SHIFT)) & TRDC_MBC2_MRC_DOM2_RGD_W_STRT_ADDR_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MRC_DOM2_RGD_W */ +#define TRDC_MBC2_MRC_DOM2_RGD_W_COUNT (2U) + +/* The count of TRDC_MBC2_MRC_DOM2_RGD_W */ +#define TRDC_MBC2_MRC_DOM2_RGD_W_COUNT2 (8U) + +/* The count of TRDC_MBC2_MRC_DOM2_RGD_W */ +#define TRDC_MBC2_MRC_DOM2_RGD_W_COUNT3 (2U) + +/*! @name MRC_DOM2_RGD_NSE - MRC Region Descriptor NonSecure Enable */ +/*! @{ */ + +#define TRDC_MBC2_MRC_DOM2_RGD_NSE_BIT0_MASK (0x1U) +#define TRDC_MBC2_MRC_DOM2_RGD_NSE_BIT0_SHIFT (0U) +/*! BIT0 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM2_RGD_NSE_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM2_RGD_NSE_BIT0_SHIFT)) & TRDC_MBC2_MRC_DOM2_RGD_NSE_BIT0_MASK) + +#define TRDC_MBC2_MRC_DOM2_RGD_NSE_BIT1_MASK (0x2U) +#define TRDC_MBC2_MRC_DOM2_RGD_NSE_BIT1_SHIFT (1U) +/*! BIT1 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM2_RGD_NSE_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM2_RGD_NSE_BIT1_SHIFT)) & TRDC_MBC2_MRC_DOM2_RGD_NSE_BIT1_MASK) + +#define TRDC_MBC2_MRC_DOM2_RGD_NSE_BIT2_MASK (0x4U) +#define TRDC_MBC2_MRC_DOM2_RGD_NSE_BIT2_SHIFT (2U) +/*! BIT2 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM2_RGD_NSE_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM2_RGD_NSE_BIT2_SHIFT)) & TRDC_MBC2_MRC_DOM2_RGD_NSE_BIT2_MASK) + +#define TRDC_MBC2_MRC_DOM2_RGD_NSE_BIT3_MASK (0x8U) +#define TRDC_MBC2_MRC_DOM2_RGD_NSE_BIT3_SHIFT (3U) +/*! BIT3 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM2_RGD_NSE_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM2_RGD_NSE_BIT3_SHIFT)) & TRDC_MBC2_MRC_DOM2_RGD_NSE_BIT3_MASK) + +#define TRDC_MBC2_MRC_DOM2_RGD_NSE_BIT4_MASK (0x10U) +#define TRDC_MBC2_MRC_DOM2_RGD_NSE_BIT4_SHIFT (4U) +/*! BIT4 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM2_RGD_NSE_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM2_RGD_NSE_BIT4_SHIFT)) & TRDC_MBC2_MRC_DOM2_RGD_NSE_BIT4_MASK) + +#define TRDC_MBC2_MRC_DOM2_RGD_NSE_BIT5_MASK (0x20U) +#define TRDC_MBC2_MRC_DOM2_RGD_NSE_BIT5_SHIFT (5U) +/*! BIT5 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM2_RGD_NSE_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM2_RGD_NSE_BIT5_SHIFT)) & TRDC_MBC2_MRC_DOM2_RGD_NSE_BIT5_MASK) + +#define TRDC_MBC2_MRC_DOM2_RGD_NSE_BIT6_MASK (0x40U) +#define TRDC_MBC2_MRC_DOM2_RGD_NSE_BIT6_SHIFT (6U) +/*! BIT6 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM2_RGD_NSE_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM2_RGD_NSE_BIT6_SHIFT)) & TRDC_MBC2_MRC_DOM2_RGD_NSE_BIT6_MASK) + +#define TRDC_MBC2_MRC_DOM2_RGD_NSE_BIT7_MASK (0x80U) +#define TRDC_MBC2_MRC_DOM2_RGD_NSE_BIT7_SHIFT (7U) +/*! BIT7 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM2_RGD_NSE_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM2_RGD_NSE_BIT7_SHIFT)) & TRDC_MBC2_MRC_DOM2_RGD_NSE_BIT7_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MRC_DOM2_RGD_NSE */ +#define TRDC_MBC2_MRC_DOM2_RGD_NSE_COUNT (2U) + +/*! @name MRC_DOM3_RGD_W - MRC Region Descriptor Word 0..MRC Region Descriptor Word 1 */ +/*! @{ */ + +#define TRDC_MBC2_MRC_DOM3_RGD_W_MRACSEL_MASK (0x7U) +#define TRDC_MBC2_MRC_DOM3_RGD_W_MRACSEL_SHIFT (0U) +/*! MRACSEL - Memory Region Access Control Select + * 0b000..Select MRC_GLBAC0 access control policy + * 0b001..Select MRC_GLBAC1 access control policy + * 0b010..Select MRC_GLBAC2 access control policy + * 0b011..Select MRC_GLBAC3 access control policy + * 0b100..Select MRC_GLBAC4 access control policy + * 0b101..Select MRC_GLBAC5 access control policy + * 0b110..Select MRC_GLBAC6 access control policy + * 0b111..Select MRC_GLBAC7 access control policy + */ +#define TRDC_MBC2_MRC_DOM3_RGD_W_MRACSEL(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM3_RGD_W_MRACSEL_SHIFT)) & TRDC_MBC2_MRC_DOM3_RGD_W_MRACSEL_MASK) + +#define TRDC_MBC2_MRC_DOM3_RGD_W_VLD_MASK (0x1U) +#define TRDC_MBC2_MRC_DOM3_RGD_W_VLD_SHIFT (0U) +/*! VLD - Valid */ +#define TRDC_MBC2_MRC_DOM3_RGD_W_VLD(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM3_RGD_W_VLD_SHIFT)) & TRDC_MBC2_MRC_DOM3_RGD_W_VLD_MASK) + +#define TRDC_MBC2_MRC_DOM3_RGD_W_NSE_MASK (0x10U) +#define TRDC_MBC2_MRC_DOM3_RGD_W_NSE_SHIFT (4U) +/*! NSE - NonSecure Enable + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in this register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM3_RGD_W_NSE(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM3_RGD_W_NSE_SHIFT)) & TRDC_MBC2_MRC_DOM3_RGD_W_NSE_MASK) + +#define TRDC_MBC2_MRC_DOM3_RGD_W_END_ADDR_MASK (0xFFFFC000U) +#define TRDC_MBC2_MRC_DOM3_RGD_W_END_ADDR_SHIFT (14U) +/*! END_ADDR - End Address */ +#define TRDC_MBC2_MRC_DOM3_RGD_W_END_ADDR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM3_RGD_W_END_ADDR_SHIFT)) & TRDC_MBC2_MRC_DOM3_RGD_W_END_ADDR_MASK) + +#define TRDC_MBC2_MRC_DOM3_RGD_W_STRT_ADDR_MASK (0xFFFFC000U) +#define TRDC_MBC2_MRC_DOM3_RGD_W_STRT_ADDR_SHIFT (14U) +/*! STRT_ADDR - Start Address */ +#define TRDC_MBC2_MRC_DOM3_RGD_W_STRT_ADDR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM3_RGD_W_STRT_ADDR_SHIFT)) & TRDC_MBC2_MRC_DOM3_RGD_W_STRT_ADDR_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MRC_DOM3_RGD_W */ +#define TRDC_MBC2_MRC_DOM3_RGD_W_COUNT (2U) + +/* The count of TRDC_MBC2_MRC_DOM3_RGD_W */ +#define TRDC_MBC2_MRC_DOM3_RGD_W_COUNT2 (8U) + +/* The count of TRDC_MBC2_MRC_DOM3_RGD_W */ +#define TRDC_MBC2_MRC_DOM3_RGD_W_COUNT3 (2U) + +/*! @name MRC_DOM3_RGD_NSE - MRC Region Descriptor NonSecure Enable */ +/*! @{ */ + +#define TRDC_MBC2_MRC_DOM3_RGD_NSE_BIT0_MASK (0x1U) +#define TRDC_MBC2_MRC_DOM3_RGD_NSE_BIT0_SHIFT (0U) +/*! BIT0 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM3_RGD_NSE_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM3_RGD_NSE_BIT0_SHIFT)) & TRDC_MBC2_MRC_DOM3_RGD_NSE_BIT0_MASK) + +#define TRDC_MBC2_MRC_DOM3_RGD_NSE_BIT1_MASK (0x2U) +#define TRDC_MBC2_MRC_DOM3_RGD_NSE_BIT1_SHIFT (1U) +/*! BIT1 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM3_RGD_NSE_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM3_RGD_NSE_BIT1_SHIFT)) & TRDC_MBC2_MRC_DOM3_RGD_NSE_BIT1_MASK) + +#define TRDC_MBC2_MRC_DOM3_RGD_NSE_BIT2_MASK (0x4U) +#define TRDC_MBC2_MRC_DOM3_RGD_NSE_BIT2_SHIFT (2U) +/*! BIT2 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM3_RGD_NSE_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM3_RGD_NSE_BIT2_SHIFT)) & TRDC_MBC2_MRC_DOM3_RGD_NSE_BIT2_MASK) + +#define TRDC_MBC2_MRC_DOM3_RGD_NSE_BIT3_MASK (0x8U) +#define TRDC_MBC2_MRC_DOM3_RGD_NSE_BIT3_SHIFT (3U) +/*! BIT3 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM3_RGD_NSE_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM3_RGD_NSE_BIT3_SHIFT)) & TRDC_MBC2_MRC_DOM3_RGD_NSE_BIT3_MASK) + +#define TRDC_MBC2_MRC_DOM3_RGD_NSE_BIT4_MASK (0x10U) +#define TRDC_MBC2_MRC_DOM3_RGD_NSE_BIT4_SHIFT (4U) +/*! BIT4 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM3_RGD_NSE_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM3_RGD_NSE_BIT4_SHIFT)) & TRDC_MBC2_MRC_DOM3_RGD_NSE_BIT4_MASK) + +#define TRDC_MBC2_MRC_DOM3_RGD_NSE_BIT5_MASK (0x20U) +#define TRDC_MBC2_MRC_DOM3_RGD_NSE_BIT5_SHIFT (5U) +/*! BIT5 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM3_RGD_NSE_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM3_RGD_NSE_BIT5_SHIFT)) & TRDC_MBC2_MRC_DOM3_RGD_NSE_BIT5_MASK) + +#define TRDC_MBC2_MRC_DOM3_RGD_NSE_BIT6_MASK (0x40U) +#define TRDC_MBC2_MRC_DOM3_RGD_NSE_BIT6_SHIFT (6U) +/*! BIT6 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM3_RGD_NSE_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM3_RGD_NSE_BIT6_SHIFT)) & TRDC_MBC2_MRC_DOM3_RGD_NSE_BIT6_MASK) + +#define TRDC_MBC2_MRC_DOM3_RGD_NSE_BIT7_MASK (0x80U) +#define TRDC_MBC2_MRC_DOM3_RGD_NSE_BIT7_SHIFT (7U) +/*! BIT7 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM3_RGD_NSE_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM3_RGD_NSE_BIT7_SHIFT)) & TRDC_MBC2_MRC_DOM3_RGD_NSE_BIT7_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MRC_DOM3_RGD_NSE */ +#define TRDC_MBC2_MRC_DOM3_RGD_NSE_COUNT (2U) + +/*! @name MRC_DOM4_RGD_W - MRC Region Descriptor Word 0..MRC Region Descriptor Word 1 */ +/*! @{ */ + +#define TRDC_MBC2_MRC_DOM4_RGD_W_MRACSEL_MASK (0x7U) +#define TRDC_MBC2_MRC_DOM4_RGD_W_MRACSEL_SHIFT (0U) +/*! MRACSEL - Memory Region Access Control Select + * 0b000..Select MRC_GLBAC0 access control policy + * 0b001..Select MRC_GLBAC1 access control policy + * 0b010..Select MRC_GLBAC2 access control policy + * 0b011..Select MRC_GLBAC3 access control policy + * 0b100..Select MRC_GLBAC4 access control policy + * 0b101..Select MRC_GLBAC5 access control policy + * 0b110..Select MRC_GLBAC6 access control policy + * 0b111..Select MRC_GLBAC7 access control policy + */ +#define TRDC_MBC2_MRC_DOM4_RGD_W_MRACSEL(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM4_RGD_W_MRACSEL_SHIFT)) & TRDC_MBC2_MRC_DOM4_RGD_W_MRACSEL_MASK) + +#define TRDC_MBC2_MRC_DOM4_RGD_W_VLD_MASK (0x1U) +#define TRDC_MBC2_MRC_DOM4_RGD_W_VLD_SHIFT (0U) +/*! VLD - Valid */ +#define TRDC_MBC2_MRC_DOM4_RGD_W_VLD(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM4_RGD_W_VLD_SHIFT)) & TRDC_MBC2_MRC_DOM4_RGD_W_VLD_MASK) + +#define TRDC_MBC2_MRC_DOM4_RGD_W_NSE_MASK (0x10U) +#define TRDC_MBC2_MRC_DOM4_RGD_W_NSE_SHIFT (4U) +/*! NSE - NonSecure Enable + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in this register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM4_RGD_W_NSE(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM4_RGD_W_NSE_SHIFT)) & TRDC_MBC2_MRC_DOM4_RGD_W_NSE_MASK) + +#define TRDC_MBC2_MRC_DOM4_RGD_W_END_ADDR_MASK (0xFFFFC000U) +#define TRDC_MBC2_MRC_DOM4_RGD_W_END_ADDR_SHIFT (14U) +/*! END_ADDR - End Address */ +#define TRDC_MBC2_MRC_DOM4_RGD_W_END_ADDR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM4_RGD_W_END_ADDR_SHIFT)) & TRDC_MBC2_MRC_DOM4_RGD_W_END_ADDR_MASK) + +#define TRDC_MBC2_MRC_DOM4_RGD_W_STRT_ADDR_MASK (0xFFFFC000U) +#define TRDC_MBC2_MRC_DOM4_RGD_W_STRT_ADDR_SHIFT (14U) +/*! STRT_ADDR - Start Address */ +#define TRDC_MBC2_MRC_DOM4_RGD_W_STRT_ADDR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM4_RGD_W_STRT_ADDR_SHIFT)) & TRDC_MBC2_MRC_DOM4_RGD_W_STRT_ADDR_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MRC_DOM4_RGD_W */ +#define TRDC_MBC2_MRC_DOM4_RGD_W_COUNT (2U) + +/* The count of TRDC_MBC2_MRC_DOM4_RGD_W */ +#define TRDC_MBC2_MRC_DOM4_RGD_W_COUNT2 (8U) + +/* The count of TRDC_MBC2_MRC_DOM4_RGD_W */ +#define TRDC_MBC2_MRC_DOM4_RGD_W_COUNT3 (2U) + +/*! @name MRC_DOM4_RGD_NSE - MRC Region Descriptor NonSecure Enable */ +/*! @{ */ + +#define TRDC_MBC2_MRC_DOM4_RGD_NSE_BIT0_MASK (0x1U) +#define TRDC_MBC2_MRC_DOM4_RGD_NSE_BIT0_SHIFT (0U) +/*! BIT0 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM4_RGD_NSE_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM4_RGD_NSE_BIT0_SHIFT)) & TRDC_MBC2_MRC_DOM4_RGD_NSE_BIT0_MASK) + +#define TRDC_MBC2_MRC_DOM4_RGD_NSE_BIT1_MASK (0x2U) +#define TRDC_MBC2_MRC_DOM4_RGD_NSE_BIT1_SHIFT (1U) +/*! BIT1 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM4_RGD_NSE_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM4_RGD_NSE_BIT1_SHIFT)) & TRDC_MBC2_MRC_DOM4_RGD_NSE_BIT1_MASK) + +#define TRDC_MBC2_MRC_DOM4_RGD_NSE_BIT2_MASK (0x4U) +#define TRDC_MBC2_MRC_DOM4_RGD_NSE_BIT2_SHIFT (2U) +/*! BIT2 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM4_RGD_NSE_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM4_RGD_NSE_BIT2_SHIFT)) & TRDC_MBC2_MRC_DOM4_RGD_NSE_BIT2_MASK) + +#define TRDC_MBC2_MRC_DOM4_RGD_NSE_BIT3_MASK (0x8U) +#define TRDC_MBC2_MRC_DOM4_RGD_NSE_BIT3_SHIFT (3U) +/*! BIT3 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM4_RGD_NSE_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM4_RGD_NSE_BIT3_SHIFT)) & TRDC_MBC2_MRC_DOM4_RGD_NSE_BIT3_MASK) + +#define TRDC_MBC2_MRC_DOM4_RGD_NSE_BIT4_MASK (0x10U) +#define TRDC_MBC2_MRC_DOM4_RGD_NSE_BIT4_SHIFT (4U) +/*! BIT4 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM4_RGD_NSE_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM4_RGD_NSE_BIT4_SHIFT)) & TRDC_MBC2_MRC_DOM4_RGD_NSE_BIT4_MASK) + +#define TRDC_MBC2_MRC_DOM4_RGD_NSE_BIT5_MASK (0x20U) +#define TRDC_MBC2_MRC_DOM4_RGD_NSE_BIT5_SHIFT (5U) +/*! BIT5 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM4_RGD_NSE_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM4_RGD_NSE_BIT5_SHIFT)) & TRDC_MBC2_MRC_DOM4_RGD_NSE_BIT5_MASK) + +#define TRDC_MBC2_MRC_DOM4_RGD_NSE_BIT6_MASK (0x40U) +#define TRDC_MBC2_MRC_DOM4_RGD_NSE_BIT6_SHIFT (6U) +/*! BIT6 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM4_RGD_NSE_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM4_RGD_NSE_BIT6_SHIFT)) & TRDC_MBC2_MRC_DOM4_RGD_NSE_BIT6_MASK) + +#define TRDC_MBC2_MRC_DOM4_RGD_NSE_BIT7_MASK (0x80U) +#define TRDC_MBC2_MRC_DOM4_RGD_NSE_BIT7_SHIFT (7U) +/*! BIT7 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM4_RGD_NSE_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM4_RGD_NSE_BIT7_SHIFT)) & TRDC_MBC2_MRC_DOM4_RGD_NSE_BIT7_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MRC_DOM4_RGD_NSE */ +#define TRDC_MBC2_MRC_DOM4_RGD_NSE_COUNT (2U) + +/*! @name MRC_DOM5_RGD_W - MRC Region Descriptor Word 0..MRC Region Descriptor Word 1 */ +/*! @{ */ + +#define TRDC_MBC2_MRC_DOM5_RGD_W_MRACSEL_MASK (0x7U) +#define TRDC_MBC2_MRC_DOM5_RGD_W_MRACSEL_SHIFT (0U) +/*! MRACSEL - Memory Region Access Control Select + * 0b000..Select MRC_GLBAC0 access control policy + * 0b001..Select MRC_GLBAC1 access control policy + * 0b010..Select MRC_GLBAC2 access control policy + * 0b011..Select MRC_GLBAC3 access control policy + * 0b100..Select MRC_GLBAC4 access control policy + * 0b101..Select MRC_GLBAC5 access control policy + * 0b110..Select MRC_GLBAC6 access control policy + * 0b111..Select MRC_GLBAC7 access control policy + */ +#define TRDC_MBC2_MRC_DOM5_RGD_W_MRACSEL(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM5_RGD_W_MRACSEL_SHIFT)) & TRDC_MBC2_MRC_DOM5_RGD_W_MRACSEL_MASK) + +#define TRDC_MBC2_MRC_DOM5_RGD_W_VLD_MASK (0x1U) +#define TRDC_MBC2_MRC_DOM5_RGD_W_VLD_SHIFT (0U) +/*! VLD - Valid */ +#define TRDC_MBC2_MRC_DOM5_RGD_W_VLD(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM5_RGD_W_VLD_SHIFT)) & TRDC_MBC2_MRC_DOM5_RGD_W_VLD_MASK) + +#define TRDC_MBC2_MRC_DOM5_RGD_W_NSE_MASK (0x10U) +#define TRDC_MBC2_MRC_DOM5_RGD_W_NSE_SHIFT (4U) +/*! NSE - NonSecure Enable + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in this register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM5_RGD_W_NSE(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM5_RGD_W_NSE_SHIFT)) & TRDC_MBC2_MRC_DOM5_RGD_W_NSE_MASK) + +#define TRDC_MBC2_MRC_DOM5_RGD_W_END_ADDR_MASK (0xFFFFC000U) +#define TRDC_MBC2_MRC_DOM5_RGD_W_END_ADDR_SHIFT (14U) +/*! END_ADDR - End Address */ +#define TRDC_MBC2_MRC_DOM5_RGD_W_END_ADDR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM5_RGD_W_END_ADDR_SHIFT)) & TRDC_MBC2_MRC_DOM5_RGD_W_END_ADDR_MASK) + +#define TRDC_MBC2_MRC_DOM5_RGD_W_STRT_ADDR_MASK (0xFFFFC000U) +#define TRDC_MBC2_MRC_DOM5_RGD_W_STRT_ADDR_SHIFT (14U) +/*! STRT_ADDR - Start Address */ +#define TRDC_MBC2_MRC_DOM5_RGD_W_STRT_ADDR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM5_RGD_W_STRT_ADDR_SHIFT)) & TRDC_MBC2_MRC_DOM5_RGD_W_STRT_ADDR_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MRC_DOM5_RGD_W */ +#define TRDC_MBC2_MRC_DOM5_RGD_W_COUNT (2U) + +/* The count of TRDC_MBC2_MRC_DOM5_RGD_W */ +#define TRDC_MBC2_MRC_DOM5_RGD_W_COUNT2 (8U) + +/* The count of TRDC_MBC2_MRC_DOM5_RGD_W */ +#define TRDC_MBC2_MRC_DOM5_RGD_W_COUNT3 (2U) + +/*! @name MRC_DOM5_RGD_NSE - MRC Region Descriptor NonSecure Enable */ +/*! @{ */ + +#define TRDC_MBC2_MRC_DOM5_RGD_NSE_BIT0_MASK (0x1U) +#define TRDC_MBC2_MRC_DOM5_RGD_NSE_BIT0_SHIFT (0U) +/*! BIT0 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM5_RGD_NSE_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM5_RGD_NSE_BIT0_SHIFT)) & TRDC_MBC2_MRC_DOM5_RGD_NSE_BIT0_MASK) + +#define TRDC_MBC2_MRC_DOM5_RGD_NSE_BIT1_MASK (0x2U) +#define TRDC_MBC2_MRC_DOM5_RGD_NSE_BIT1_SHIFT (1U) +/*! BIT1 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM5_RGD_NSE_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM5_RGD_NSE_BIT1_SHIFT)) & TRDC_MBC2_MRC_DOM5_RGD_NSE_BIT1_MASK) + +#define TRDC_MBC2_MRC_DOM5_RGD_NSE_BIT2_MASK (0x4U) +#define TRDC_MBC2_MRC_DOM5_RGD_NSE_BIT2_SHIFT (2U) +/*! BIT2 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM5_RGD_NSE_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM5_RGD_NSE_BIT2_SHIFT)) & TRDC_MBC2_MRC_DOM5_RGD_NSE_BIT2_MASK) + +#define TRDC_MBC2_MRC_DOM5_RGD_NSE_BIT3_MASK (0x8U) +#define TRDC_MBC2_MRC_DOM5_RGD_NSE_BIT3_SHIFT (3U) +/*! BIT3 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM5_RGD_NSE_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM5_RGD_NSE_BIT3_SHIFT)) & TRDC_MBC2_MRC_DOM5_RGD_NSE_BIT3_MASK) + +#define TRDC_MBC2_MRC_DOM5_RGD_NSE_BIT4_MASK (0x10U) +#define TRDC_MBC2_MRC_DOM5_RGD_NSE_BIT4_SHIFT (4U) +/*! BIT4 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM5_RGD_NSE_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM5_RGD_NSE_BIT4_SHIFT)) & TRDC_MBC2_MRC_DOM5_RGD_NSE_BIT4_MASK) + +#define TRDC_MBC2_MRC_DOM5_RGD_NSE_BIT5_MASK (0x20U) +#define TRDC_MBC2_MRC_DOM5_RGD_NSE_BIT5_SHIFT (5U) +/*! BIT5 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM5_RGD_NSE_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM5_RGD_NSE_BIT5_SHIFT)) & TRDC_MBC2_MRC_DOM5_RGD_NSE_BIT5_MASK) + +#define TRDC_MBC2_MRC_DOM5_RGD_NSE_BIT6_MASK (0x40U) +#define TRDC_MBC2_MRC_DOM5_RGD_NSE_BIT6_SHIFT (6U) +/*! BIT6 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM5_RGD_NSE_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM5_RGD_NSE_BIT6_SHIFT)) & TRDC_MBC2_MRC_DOM5_RGD_NSE_BIT6_MASK) + +#define TRDC_MBC2_MRC_DOM5_RGD_NSE_BIT7_MASK (0x80U) +#define TRDC_MBC2_MRC_DOM5_RGD_NSE_BIT7_SHIFT (7U) +/*! BIT7 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM5_RGD_NSE_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM5_RGD_NSE_BIT7_SHIFT)) & TRDC_MBC2_MRC_DOM5_RGD_NSE_BIT7_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MRC_DOM5_RGD_NSE */ +#define TRDC_MBC2_MRC_DOM5_RGD_NSE_COUNT (2U) + +/*! @name MRC_DOM6_RGD_W - MRC Region Descriptor Word 0..MRC Region Descriptor Word 1 */ +/*! @{ */ + +#define TRDC_MBC2_MRC_DOM6_RGD_W_MRACSEL_MASK (0x7U) +#define TRDC_MBC2_MRC_DOM6_RGD_W_MRACSEL_SHIFT (0U) +/*! MRACSEL - Memory Region Access Control Select + * 0b000..Select MRC_GLBAC0 access control policy + * 0b001..Select MRC_GLBAC1 access control policy + * 0b010..Select MRC_GLBAC2 access control policy + * 0b011..Select MRC_GLBAC3 access control policy + * 0b100..Select MRC_GLBAC4 access control policy + * 0b101..Select MRC_GLBAC5 access control policy + * 0b110..Select MRC_GLBAC6 access control policy + * 0b111..Select MRC_GLBAC7 access control policy + */ +#define TRDC_MBC2_MRC_DOM6_RGD_W_MRACSEL(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM6_RGD_W_MRACSEL_SHIFT)) & TRDC_MBC2_MRC_DOM6_RGD_W_MRACSEL_MASK) + +#define TRDC_MBC2_MRC_DOM6_RGD_W_VLD_MASK (0x1U) +#define TRDC_MBC2_MRC_DOM6_RGD_W_VLD_SHIFT (0U) +/*! VLD - Valid */ +#define TRDC_MBC2_MRC_DOM6_RGD_W_VLD(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM6_RGD_W_VLD_SHIFT)) & TRDC_MBC2_MRC_DOM6_RGD_W_VLD_MASK) + +#define TRDC_MBC2_MRC_DOM6_RGD_W_NSE_MASK (0x10U) +#define TRDC_MBC2_MRC_DOM6_RGD_W_NSE_SHIFT (4U) +/*! NSE - NonSecure Enable + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in this register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM6_RGD_W_NSE(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM6_RGD_W_NSE_SHIFT)) & TRDC_MBC2_MRC_DOM6_RGD_W_NSE_MASK) + +#define TRDC_MBC2_MRC_DOM6_RGD_W_END_ADDR_MASK (0xFFFFC000U) +#define TRDC_MBC2_MRC_DOM6_RGD_W_END_ADDR_SHIFT (14U) +/*! END_ADDR - End Address */ +#define TRDC_MBC2_MRC_DOM6_RGD_W_END_ADDR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM6_RGD_W_END_ADDR_SHIFT)) & TRDC_MBC2_MRC_DOM6_RGD_W_END_ADDR_MASK) + +#define TRDC_MBC2_MRC_DOM6_RGD_W_STRT_ADDR_MASK (0xFFFFC000U) +#define TRDC_MBC2_MRC_DOM6_RGD_W_STRT_ADDR_SHIFT (14U) +/*! STRT_ADDR - Start Address */ +#define TRDC_MBC2_MRC_DOM6_RGD_W_STRT_ADDR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM6_RGD_W_STRT_ADDR_SHIFT)) & TRDC_MBC2_MRC_DOM6_RGD_W_STRT_ADDR_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MRC_DOM6_RGD_W */ +#define TRDC_MBC2_MRC_DOM6_RGD_W_COUNT (2U) + +/* The count of TRDC_MBC2_MRC_DOM6_RGD_W */ +#define TRDC_MBC2_MRC_DOM6_RGD_W_COUNT2 (8U) + +/* The count of TRDC_MBC2_MRC_DOM6_RGD_W */ +#define TRDC_MBC2_MRC_DOM6_RGD_W_COUNT3 (2U) + +/*! @name MRC_DOM6_RGD_NSE - MRC Region Descriptor NonSecure Enable */ +/*! @{ */ + +#define TRDC_MBC2_MRC_DOM6_RGD_NSE_BIT0_MASK (0x1U) +#define TRDC_MBC2_MRC_DOM6_RGD_NSE_BIT0_SHIFT (0U) +/*! BIT0 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM6_RGD_NSE_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM6_RGD_NSE_BIT0_SHIFT)) & TRDC_MBC2_MRC_DOM6_RGD_NSE_BIT0_MASK) + +#define TRDC_MBC2_MRC_DOM6_RGD_NSE_BIT1_MASK (0x2U) +#define TRDC_MBC2_MRC_DOM6_RGD_NSE_BIT1_SHIFT (1U) +/*! BIT1 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM6_RGD_NSE_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM6_RGD_NSE_BIT1_SHIFT)) & TRDC_MBC2_MRC_DOM6_RGD_NSE_BIT1_MASK) + +#define TRDC_MBC2_MRC_DOM6_RGD_NSE_BIT2_MASK (0x4U) +#define TRDC_MBC2_MRC_DOM6_RGD_NSE_BIT2_SHIFT (2U) +/*! BIT2 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM6_RGD_NSE_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM6_RGD_NSE_BIT2_SHIFT)) & TRDC_MBC2_MRC_DOM6_RGD_NSE_BIT2_MASK) + +#define TRDC_MBC2_MRC_DOM6_RGD_NSE_BIT3_MASK (0x8U) +#define TRDC_MBC2_MRC_DOM6_RGD_NSE_BIT3_SHIFT (3U) +/*! BIT3 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM6_RGD_NSE_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM6_RGD_NSE_BIT3_SHIFT)) & TRDC_MBC2_MRC_DOM6_RGD_NSE_BIT3_MASK) + +#define TRDC_MBC2_MRC_DOM6_RGD_NSE_BIT4_MASK (0x10U) +#define TRDC_MBC2_MRC_DOM6_RGD_NSE_BIT4_SHIFT (4U) +/*! BIT4 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM6_RGD_NSE_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM6_RGD_NSE_BIT4_SHIFT)) & TRDC_MBC2_MRC_DOM6_RGD_NSE_BIT4_MASK) + +#define TRDC_MBC2_MRC_DOM6_RGD_NSE_BIT5_MASK (0x20U) +#define TRDC_MBC2_MRC_DOM6_RGD_NSE_BIT5_SHIFT (5U) +/*! BIT5 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM6_RGD_NSE_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM6_RGD_NSE_BIT5_SHIFT)) & TRDC_MBC2_MRC_DOM6_RGD_NSE_BIT5_MASK) + +#define TRDC_MBC2_MRC_DOM6_RGD_NSE_BIT6_MASK (0x40U) +#define TRDC_MBC2_MRC_DOM6_RGD_NSE_BIT6_SHIFT (6U) +/*! BIT6 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM6_RGD_NSE_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM6_RGD_NSE_BIT6_SHIFT)) & TRDC_MBC2_MRC_DOM6_RGD_NSE_BIT6_MASK) + +#define TRDC_MBC2_MRC_DOM6_RGD_NSE_BIT7_MASK (0x80U) +#define TRDC_MBC2_MRC_DOM6_RGD_NSE_BIT7_SHIFT (7U) +/*! BIT7 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM6_RGD_NSE_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM6_RGD_NSE_BIT7_SHIFT)) & TRDC_MBC2_MRC_DOM6_RGD_NSE_BIT7_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MRC_DOM6_RGD_NSE */ +#define TRDC_MBC2_MRC_DOM6_RGD_NSE_COUNT (2U) + +/*! @name MRC_DOM7_RGD_W - MRC Region Descriptor Word 0..MRC Region Descriptor Word 1 */ +/*! @{ */ + +#define TRDC_MBC2_MRC_DOM7_RGD_W_MRACSEL_MASK (0x7U) +#define TRDC_MBC2_MRC_DOM7_RGD_W_MRACSEL_SHIFT (0U) +/*! MRACSEL - Memory Region Access Control Select + * 0b000..Select MRC_GLBAC0 access control policy + * 0b001..Select MRC_GLBAC1 access control policy + * 0b010..Select MRC_GLBAC2 access control policy + * 0b011..Select MRC_GLBAC3 access control policy + * 0b100..Select MRC_GLBAC4 access control policy + * 0b101..Select MRC_GLBAC5 access control policy + * 0b110..Select MRC_GLBAC6 access control policy + * 0b111..Select MRC_GLBAC7 access control policy + */ +#define TRDC_MBC2_MRC_DOM7_RGD_W_MRACSEL(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM7_RGD_W_MRACSEL_SHIFT)) & TRDC_MBC2_MRC_DOM7_RGD_W_MRACSEL_MASK) + +#define TRDC_MBC2_MRC_DOM7_RGD_W_VLD_MASK (0x1U) +#define TRDC_MBC2_MRC_DOM7_RGD_W_VLD_SHIFT (0U) +/*! VLD - Valid */ +#define TRDC_MBC2_MRC_DOM7_RGD_W_VLD(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM7_RGD_W_VLD_SHIFT)) & TRDC_MBC2_MRC_DOM7_RGD_W_VLD_MASK) + +#define TRDC_MBC2_MRC_DOM7_RGD_W_NSE_MASK (0x10U) +#define TRDC_MBC2_MRC_DOM7_RGD_W_NSE_SHIFT (4U) +/*! NSE - NonSecure Enable + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in this register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM7_RGD_W_NSE(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM7_RGD_W_NSE_SHIFT)) & TRDC_MBC2_MRC_DOM7_RGD_W_NSE_MASK) + +#define TRDC_MBC2_MRC_DOM7_RGD_W_END_ADDR_MASK (0xFFFFC000U) +#define TRDC_MBC2_MRC_DOM7_RGD_W_END_ADDR_SHIFT (14U) +/*! END_ADDR - End Address */ +#define TRDC_MBC2_MRC_DOM7_RGD_W_END_ADDR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM7_RGD_W_END_ADDR_SHIFT)) & TRDC_MBC2_MRC_DOM7_RGD_W_END_ADDR_MASK) + +#define TRDC_MBC2_MRC_DOM7_RGD_W_STRT_ADDR_MASK (0xFFFFC000U) +#define TRDC_MBC2_MRC_DOM7_RGD_W_STRT_ADDR_SHIFT (14U) +/*! STRT_ADDR - Start Address */ +#define TRDC_MBC2_MRC_DOM7_RGD_W_STRT_ADDR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM7_RGD_W_STRT_ADDR_SHIFT)) & TRDC_MBC2_MRC_DOM7_RGD_W_STRT_ADDR_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MRC_DOM7_RGD_W */ +#define TRDC_MBC2_MRC_DOM7_RGD_W_COUNT (2U) + +/* The count of TRDC_MBC2_MRC_DOM7_RGD_W */ +#define TRDC_MBC2_MRC_DOM7_RGD_W_COUNT2 (8U) + +/* The count of TRDC_MBC2_MRC_DOM7_RGD_W */ +#define TRDC_MBC2_MRC_DOM7_RGD_W_COUNT3 (2U) + +/*! @name MRC_DOM7_RGD_NSE - MRC Region Descriptor NonSecure Enable */ +/*! @{ */ + +#define TRDC_MBC2_MRC_DOM7_RGD_NSE_BIT0_MASK (0x1U) +#define TRDC_MBC2_MRC_DOM7_RGD_NSE_BIT0_SHIFT (0U) +/*! BIT0 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM7_RGD_NSE_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM7_RGD_NSE_BIT0_SHIFT)) & TRDC_MBC2_MRC_DOM7_RGD_NSE_BIT0_MASK) + +#define TRDC_MBC2_MRC_DOM7_RGD_NSE_BIT1_MASK (0x2U) +#define TRDC_MBC2_MRC_DOM7_RGD_NSE_BIT1_SHIFT (1U) +/*! BIT1 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM7_RGD_NSE_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM7_RGD_NSE_BIT1_SHIFT)) & TRDC_MBC2_MRC_DOM7_RGD_NSE_BIT1_MASK) + +#define TRDC_MBC2_MRC_DOM7_RGD_NSE_BIT2_MASK (0x4U) +#define TRDC_MBC2_MRC_DOM7_RGD_NSE_BIT2_SHIFT (2U) +/*! BIT2 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM7_RGD_NSE_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM7_RGD_NSE_BIT2_SHIFT)) & TRDC_MBC2_MRC_DOM7_RGD_NSE_BIT2_MASK) + +#define TRDC_MBC2_MRC_DOM7_RGD_NSE_BIT3_MASK (0x8U) +#define TRDC_MBC2_MRC_DOM7_RGD_NSE_BIT3_SHIFT (3U) +/*! BIT3 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM7_RGD_NSE_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM7_RGD_NSE_BIT3_SHIFT)) & TRDC_MBC2_MRC_DOM7_RGD_NSE_BIT3_MASK) + +#define TRDC_MBC2_MRC_DOM7_RGD_NSE_BIT4_MASK (0x10U) +#define TRDC_MBC2_MRC_DOM7_RGD_NSE_BIT4_SHIFT (4U) +/*! BIT4 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM7_RGD_NSE_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM7_RGD_NSE_BIT4_SHIFT)) & TRDC_MBC2_MRC_DOM7_RGD_NSE_BIT4_MASK) + +#define TRDC_MBC2_MRC_DOM7_RGD_NSE_BIT5_MASK (0x20U) +#define TRDC_MBC2_MRC_DOM7_RGD_NSE_BIT5_SHIFT (5U) +/*! BIT5 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM7_RGD_NSE_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM7_RGD_NSE_BIT5_SHIFT)) & TRDC_MBC2_MRC_DOM7_RGD_NSE_BIT5_MASK) + +#define TRDC_MBC2_MRC_DOM7_RGD_NSE_BIT6_MASK (0x40U) +#define TRDC_MBC2_MRC_DOM7_RGD_NSE_BIT6_SHIFT (6U) +/*! BIT6 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM7_RGD_NSE_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM7_RGD_NSE_BIT6_SHIFT)) & TRDC_MBC2_MRC_DOM7_RGD_NSE_BIT6_MASK) + +#define TRDC_MBC2_MRC_DOM7_RGD_NSE_BIT7_MASK (0x80U) +#define TRDC_MBC2_MRC_DOM7_RGD_NSE_BIT7_SHIFT (7U) +/*! BIT7 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM7_RGD_NSE_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM7_RGD_NSE_BIT7_SHIFT)) & TRDC_MBC2_MRC_DOM7_RGD_NSE_BIT7_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MRC_DOM7_RGD_NSE */ +#define TRDC_MBC2_MRC_DOM7_RGD_NSE_COUNT (2U) + +/*! @name MRC_DOM8_RGD_W - MRC Region Descriptor Word 0..MRC Region Descriptor Word 1 */ +/*! @{ */ + +#define TRDC_MBC2_MRC_DOM8_RGD_W_MRACSEL_MASK (0x7U) +#define TRDC_MBC2_MRC_DOM8_RGD_W_MRACSEL_SHIFT (0U) +/*! MRACSEL - Memory Region Access Control Select + * 0b000..Select MRC_GLBAC0 access control policy + * 0b001..Select MRC_GLBAC1 access control policy + * 0b010..Select MRC_GLBAC2 access control policy + * 0b011..Select MRC_GLBAC3 access control policy + * 0b100..Select MRC_GLBAC4 access control policy + * 0b101..Select MRC_GLBAC5 access control policy + * 0b110..Select MRC_GLBAC6 access control policy + * 0b111..Select MRC_GLBAC7 access control policy + */ +#define TRDC_MBC2_MRC_DOM8_RGD_W_MRACSEL(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM8_RGD_W_MRACSEL_SHIFT)) & TRDC_MBC2_MRC_DOM8_RGD_W_MRACSEL_MASK) + +#define TRDC_MBC2_MRC_DOM8_RGD_W_VLD_MASK (0x1U) +#define TRDC_MBC2_MRC_DOM8_RGD_W_VLD_SHIFT (0U) +/*! VLD - Valid */ +#define TRDC_MBC2_MRC_DOM8_RGD_W_VLD(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM8_RGD_W_VLD_SHIFT)) & TRDC_MBC2_MRC_DOM8_RGD_W_VLD_MASK) + +#define TRDC_MBC2_MRC_DOM8_RGD_W_NSE_MASK (0x10U) +#define TRDC_MBC2_MRC_DOM8_RGD_W_NSE_SHIFT (4U) +/*! NSE - NonSecure Enable + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in this register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM8_RGD_W_NSE(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM8_RGD_W_NSE_SHIFT)) & TRDC_MBC2_MRC_DOM8_RGD_W_NSE_MASK) + +#define TRDC_MBC2_MRC_DOM8_RGD_W_END_ADDR_MASK (0xFFFFC000U) +#define TRDC_MBC2_MRC_DOM8_RGD_W_END_ADDR_SHIFT (14U) +/*! END_ADDR - End Address */ +#define TRDC_MBC2_MRC_DOM8_RGD_W_END_ADDR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM8_RGD_W_END_ADDR_SHIFT)) & TRDC_MBC2_MRC_DOM8_RGD_W_END_ADDR_MASK) + +#define TRDC_MBC2_MRC_DOM8_RGD_W_STRT_ADDR_MASK (0xFFFFC000U) +#define TRDC_MBC2_MRC_DOM8_RGD_W_STRT_ADDR_SHIFT (14U) +/*! STRT_ADDR - Start Address */ +#define TRDC_MBC2_MRC_DOM8_RGD_W_STRT_ADDR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM8_RGD_W_STRT_ADDR_SHIFT)) & TRDC_MBC2_MRC_DOM8_RGD_W_STRT_ADDR_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MRC_DOM8_RGD_W */ +#define TRDC_MBC2_MRC_DOM8_RGD_W_COUNT (2U) + +/* The count of TRDC_MBC2_MRC_DOM8_RGD_W */ +#define TRDC_MBC2_MRC_DOM8_RGD_W_COUNT2 (8U) + +/* The count of TRDC_MBC2_MRC_DOM8_RGD_W */ +#define TRDC_MBC2_MRC_DOM8_RGD_W_COUNT3 (2U) + +/*! @name MRC_DOM8_RGD_NSE - MRC Region Descriptor NonSecure Enable */ +/*! @{ */ + +#define TRDC_MBC2_MRC_DOM8_RGD_NSE_BIT0_MASK (0x1U) +#define TRDC_MBC2_MRC_DOM8_RGD_NSE_BIT0_SHIFT (0U) +/*! BIT0 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM8_RGD_NSE_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM8_RGD_NSE_BIT0_SHIFT)) & TRDC_MBC2_MRC_DOM8_RGD_NSE_BIT0_MASK) + +#define TRDC_MBC2_MRC_DOM8_RGD_NSE_BIT1_MASK (0x2U) +#define TRDC_MBC2_MRC_DOM8_RGD_NSE_BIT1_SHIFT (1U) +/*! BIT1 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM8_RGD_NSE_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM8_RGD_NSE_BIT1_SHIFT)) & TRDC_MBC2_MRC_DOM8_RGD_NSE_BIT1_MASK) + +#define TRDC_MBC2_MRC_DOM8_RGD_NSE_BIT2_MASK (0x4U) +#define TRDC_MBC2_MRC_DOM8_RGD_NSE_BIT2_SHIFT (2U) +/*! BIT2 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM8_RGD_NSE_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM8_RGD_NSE_BIT2_SHIFT)) & TRDC_MBC2_MRC_DOM8_RGD_NSE_BIT2_MASK) + +#define TRDC_MBC2_MRC_DOM8_RGD_NSE_BIT3_MASK (0x8U) +#define TRDC_MBC2_MRC_DOM8_RGD_NSE_BIT3_SHIFT (3U) +/*! BIT3 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM8_RGD_NSE_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM8_RGD_NSE_BIT3_SHIFT)) & TRDC_MBC2_MRC_DOM8_RGD_NSE_BIT3_MASK) + +#define TRDC_MBC2_MRC_DOM8_RGD_NSE_BIT4_MASK (0x10U) +#define TRDC_MBC2_MRC_DOM8_RGD_NSE_BIT4_SHIFT (4U) +/*! BIT4 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM8_RGD_NSE_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM8_RGD_NSE_BIT4_SHIFT)) & TRDC_MBC2_MRC_DOM8_RGD_NSE_BIT4_MASK) + +#define TRDC_MBC2_MRC_DOM8_RGD_NSE_BIT5_MASK (0x20U) +#define TRDC_MBC2_MRC_DOM8_RGD_NSE_BIT5_SHIFT (5U) +/*! BIT5 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM8_RGD_NSE_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM8_RGD_NSE_BIT5_SHIFT)) & TRDC_MBC2_MRC_DOM8_RGD_NSE_BIT5_MASK) + +#define TRDC_MBC2_MRC_DOM8_RGD_NSE_BIT6_MASK (0x40U) +#define TRDC_MBC2_MRC_DOM8_RGD_NSE_BIT6_SHIFT (6U) +/*! BIT6 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM8_RGD_NSE_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM8_RGD_NSE_BIT6_SHIFT)) & TRDC_MBC2_MRC_DOM8_RGD_NSE_BIT6_MASK) + +#define TRDC_MBC2_MRC_DOM8_RGD_NSE_BIT7_MASK (0x80U) +#define TRDC_MBC2_MRC_DOM8_RGD_NSE_BIT7_SHIFT (7U) +/*! BIT7 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM8_RGD_NSE_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM8_RGD_NSE_BIT7_SHIFT)) & TRDC_MBC2_MRC_DOM8_RGD_NSE_BIT7_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MRC_DOM8_RGD_NSE */ +#define TRDC_MBC2_MRC_DOM8_RGD_NSE_COUNT (2U) + +/*! @name MRC_DOM9_RGD_W - MRC Region Descriptor Word 0..MRC Region Descriptor Word 1 */ +/*! @{ */ + +#define TRDC_MBC2_MRC_DOM9_RGD_W_MRACSEL_MASK (0x7U) +#define TRDC_MBC2_MRC_DOM9_RGD_W_MRACSEL_SHIFT (0U) +/*! MRACSEL - Memory Region Access Control Select + * 0b000..Select MRC_GLBAC0 access control policy + * 0b001..Select MRC_GLBAC1 access control policy + * 0b010..Select MRC_GLBAC2 access control policy + * 0b011..Select MRC_GLBAC3 access control policy + * 0b100..Select MRC_GLBAC4 access control policy + * 0b101..Select MRC_GLBAC5 access control policy + * 0b110..Select MRC_GLBAC6 access control policy + * 0b111..Select MRC_GLBAC7 access control policy + */ +#define TRDC_MBC2_MRC_DOM9_RGD_W_MRACSEL(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM9_RGD_W_MRACSEL_SHIFT)) & TRDC_MBC2_MRC_DOM9_RGD_W_MRACSEL_MASK) + +#define TRDC_MBC2_MRC_DOM9_RGD_W_VLD_MASK (0x1U) +#define TRDC_MBC2_MRC_DOM9_RGD_W_VLD_SHIFT (0U) +/*! VLD - Valid */ +#define TRDC_MBC2_MRC_DOM9_RGD_W_VLD(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM9_RGD_W_VLD_SHIFT)) & TRDC_MBC2_MRC_DOM9_RGD_W_VLD_MASK) + +#define TRDC_MBC2_MRC_DOM9_RGD_W_NSE_MASK (0x10U) +#define TRDC_MBC2_MRC_DOM9_RGD_W_NSE_SHIFT (4U) +/*! NSE - NonSecure Enable + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in this register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM9_RGD_W_NSE(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM9_RGD_W_NSE_SHIFT)) & TRDC_MBC2_MRC_DOM9_RGD_W_NSE_MASK) + +#define TRDC_MBC2_MRC_DOM9_RGD_W_END_ADDR_MASK (0xFFFFC000U) +#define TRDC_MBC2_MRC_DOM9_RGD_W_END_ADDR_SHIFT (14U) +/*! END_ADDR - End Address */ +#define TRDC_MBC2_MRC_DOM9_RGD_W_END_ADDR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM9_RGD_W_END_ADDR_SHIFT)) & TRDC_MBC2_MRC_DOM9_RGD_W_END_ADDR_MASK) + +#define TRDC_MBC2_MRC_DOM9_RGD_W_STRT_ADDR_MASK (0xFFFFC000U) +#define TRDC_MBC2_MRC_DOM9_RGD_W_STRT_ADDR_SHIFT (14U) +/*! STRT_ADDR - Start Address */ +#define TRDC_MBC2_MRC_DOM9_RGD_W_STRT_ADDR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM9_RGD_W_STRT_ADDR_SHIFT)) & TRDC_MBC2_MRC_DOM9_RGD_W_STRT_ADDR_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MRC_DOM9_RGD_W */ +#define TRDC_MBC2_MRC_DOM9_RGD_W_COUNT (2U) + +/* The count of TRDC_MBC2_MRC_DOM9_RGD_W */ +#define TRDC_MBC2_MRC_DOM9_RGD_W_COUNT2 (8U) + +/* The count of TRDC_MBC2_MRC_DOM9_RGD_W */ +#define TRDC_MBC2_MRC_DOM9_RGD_W_COUNT3 (2U) + +/*! @name MRC_DOM9_RGD_NSE - MRC Region Descriptor NonSecure Enable */ +/*! @{ */ + +#define TRDC_MBC2_MRC_DOM9_RGD_NSE_BIT0_MASK (0x1U) +#define TRDC_MBC2_MRC_DOM9_RGD_NSE_BIT0_SHIFT (0U) +/*! BIT0 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM9_RGD_NSE_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM9_RGD_NSE_BIT0_SHIFT)) & TRDC_MBC2_MRC_DOM9_RGD_NSE_BIT0_MASK) + +#define TRDC_MBC2_MRC_DOM9_RGD_NSE_BIT1_MASK (0x2U) +#define TRDC_MBC2_MRC_DOM9_RGD_NSE_BIT1_SHIFT (1U) +/*! BIT1 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM9_RGD_NSE_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM9_RGD_NSE_BIT1_SHIFT)) & TRDC_MBC2_MRC_DOM9_RGD_NSE_BIT1_MASK) + +#define TRDC_MBC2_MRC_DOM9_RGD_NSE_BIT2_MASK (0x4U) +#define TRDC_MBC2_MRC_DOM9_RGD_NSE_BIT2_SHIFT (2U) +/*! BIT2 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM9_RGD_NSE_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM9_RGD_NSE_BIT2_SHIFT)) & TRDC_MBC2_MRC_DOM9_RGD_NSE_BIT2_MASK) + +#define TRDC_MBC2_MRC_DOM9_RGD_NSE_BIT3_MASK (0x8U) +#define TRDC_MBC2_MRC_DOM9_RGD_NSE_BIT3_SHIFT (3U) +/*! BIT3 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM9_RGD_NSE_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM9_RGD_NSE_BIT3_SHIFT)) & TRDC_MBC2_MRC_DOM9_RGD_NSE_BIT3_MASK) + +#define TRDC_MBC2_MRC_DOM9_RGD_NSE_BIT4_MASK (0x10U) +#define TRDC_MBC2_MRC_DOM9_RGD_NSE_BIT4_SHIFT (4U) +/*! BIT4 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM9_RGD_NSE_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM9_RGD_NSE_BIT4_SHIFT)) & TRDC_MBC2_MRC_DOM9_RGD_NSE_BIT4_MASK) + +#define TRDC_MBC2_MRC_DOM9_RGD_NSE_BIT5_MASK (0x20U) +#define TRDC_MBC2_MRC_DOM9_RGD_NSE_BIT5_SHIFT (5U) +/*! BIT5 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM9_RGD_NSE_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM9_RGD_NSE_BIT5_SHIFT)) & TRDC_MBC2_MRC_DOM9_RGD_NSE_BIT5_MASK) + +#define TRDC_MBC2_MRC_DOM9_RGD_NSE_BIT6_MASK (0x40U) +#define TRDC_MBC2_MRC_DOM9_RGD_NSE_BIT6_SHIFT (6U) +/*! BIT6 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM9_RGD_NSE_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM9_RGD_NSE_BIT6_SHIFT)) & TRDC_MBC2_MRC_DOM9_RGD_NSE_BIT6_MASK) + +#define TRDC_MBC2_MRC_DOM9_RGD_NSE_BIT7_MASK (0x80U) +#define TRDC_MBC2_MRC_DOM9_RGD_NSE_BIT7_SHIFT (7U) +/*! BIT7 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM9_RGD_NSE_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM9_RGD_NSE_BIT7_SHIFT)) & TRDC_MBC2_MRC_DOM9_RGD_NSE_BIT7_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MRC_DOM9_RGD_NSE */ +#define TRDC_MBC2_MRC_DOM9_RGD_NSE_COUNT (2U) + +/*! @name MRC_DOM10_RGD_W - MRC Region Descriptor Word 0..MRC Region Descriptor Word 1 */ +/*! @{ */ + +#define TRDC_MBC2_MRC_DOM10_RGD_W_MRACSEL_MASK (0x7U) +#define TRDC_MBC2_MRC_DOM10_RGD_W_MRACSEL_SHIFT (0U) +/*! MRACSEL - Memory Region Access Control Select + * 0b000..Select MRC_GLBAC0 access control policy + * 0b001..Select MRC_GLBAC1 access control policy + * 0b010..Select MRC_GLBAC2 access control policy + * 0b011..Select MRC_GLBAC3 access control policy + * 0b100..Select MRC_GLBAC4 access control policy + * 0b101..Select MRC_GLBAC5 access control policy + * 0b110..Select MRC_GLBAC6 access control policy + * 0b111..Select MRC_GLBAC7 access control policy + */ +#define TRDC_MBC2_MRC_DOM10_RGD_W_MRACSEL(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM10_RGD_W_MRACSEL_SHIFT)) & TRDC_MBC2_MRC_DOM10_RGD_W_MRACSEL_MASK) + +#define TRDC_MBC2_MRC_DOM10_RGD_W_VLD_MASK (0x1U) +#define TRDC_MBC2_MRC_DOM10_RGD_W_VLD_SHIFT (0U) +/*! VLD - Valid */ +#define TRDC_MBC2_MRC_DOM10_RGD_W_VLD(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM10_RGD_W_VLD_SHIFT)) & TRDC_MBC2_MRC_DOM10_RGD_W_VLD_MASK) + +#define TRDC_MBC2_MRC_DOM10_RGD_W_NSE_MASK (0x10U) +#define TRDC_MBC2_MRC_DOM10_RGD_W_NSE_SHIFT (4U) +/*! NSE - NonSecure Enable + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in this register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM10_RGD_W_NSE(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM10_RGD_W_NSE_SHIFT)) & TRDC_MBC2_MRC_DOM10_RGD_W_NSE_MASK) + +#define TRDC_MBC2_MRC_DOM10_RGD_W_END_ADDR_MASK (0xFFFFC000U) +#define TRDC_MBC2_MRC_DOM10_RGD_W_END_ADDR_SHIFT (14U) +/*! END_ADDR - End Address */ +#define TRDC_MBC2_MRC_DOM10_RGD_W_END_ADDR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM10_RGD_W_END_ADDR_SHIFT)) & TRDC_MBC2_MRC_DOM10_RGD_W_END_ADDR_MASK) + +#define TRDC_MBC2_MRC_DOM10_RGD_W_STRT_ADDR_MASK (0xFFFFC000U) +#define TRDC_MBC2_MRC_DOM10_RGD_W_STRT_ADDR_SHIFT (14U) +/*! STRT_ADDR - Start Address */ +#define TRDC_MBC2_MRC_DOM10_RGD_W_STRT_ADDR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM10_RGD_W_STRT_ADDR_SHIFT)) & TRDC_MBC2_MRC_DOM10_RGD_W_STRT_ADDR_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MRC_DOM10_RGD_W */ +#define TRDC_MBC2_MRC_DOM10_RGD_W_COUNT (2U) + +/* The count of TRDC_MBC2_MRC_DOM10_RGD_W */ +#define TRDC_MBC2_MRC_DOM10_RGD_W_COUNT2 (8U) + +/* The count of TRDC_MBC2_MRC_DOM10_RGD_W */ +#define TRDC_MBC2_MRC_DOM10_RGD_W_COUNT3 (2U) + +/*! @name MRC_DOM10_RGD_NSE - MRC Region Descriptor NonSecure Enable */ +/*! @{ */ + +#define TRDC_MBC2_MRC_DOM10_RGD_NSE_BIT0_MASK (0x1U) +#define TRDC_MBC2_MRC_DOM10_RGD_NSE_BIT0_SHIFT (0U) +/*! BIT0 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM10_RGD_NSE_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM10_RGD_NSE_BIT0_SHIFT)) & TRDC_MBC2_MRC_DOM10_RGD_NSE_BIT0_MASK) + +#define TRDC_MBC2_MRC_DOM10_RGD_NSE_BIT1_MASK (0x2U) +#define TRDC_MBC2_MRC_DOM10_RGD_NSE_BIT1_SHIFT (1U) +/*! BIT1 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM10_RGD_NSE_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM10_RGD_NSE_BIT1_SHIFT)) & TRDC_MBC2_MRC_DOM10_RGD_NSE_BIT1_MASK) + +#define TRDC_MBC2_MRC_DOM10_RGD_NSE_BIT2_MASK (0x4U) +#define TRDC_MBC2_MRC_DOM10_RGD_NSE_BIT2_SHIFT (2U) +/*! BIT2 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM10_RGD_NSE_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM10_RGD_NSE_BIT2_SHIFT)) & TRDC_MBC2_MRC_DOM10_RGD_NSE_BIT2_MASK) + +#define TRDC_MBC2_MRC_DOM10_RGD_NSE_BIT3_MASK (0x8U) +#define TRDC_MBC2_MRC_DOM10_RGD_NSE_BIT3_SHIFT (3U) +/*! BIT3 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM10_RGD_NSE_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM10_RGD_NSE_BIT3_SHIFT)) & TRDC_MBC2_MRC_DOM10_RGD_NSE_BIT3_MASK) + +#define TRDC_MBC2_MRC_DOM10_RGD_NSE_BIT4_MASK (0x10U) +#define TRDC_MBC2_MRC_DOM10_RGD_NSE_BIT4_SHIFT (4U) +/*! BIT4 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM10_RGD_NSE_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM10_RGD_NSE_BIT4_SHIFT)) & TRDC_MBC2_MRC_DOM10_RGD_NSE_BIT4_MASK) + +#define TRDC_MBC2_MRC_DOM10_RGD_NSE_BIT5_MASK (0x20U) +#define TRDC_MBC2_MRC_DOM10_RGD_NSE_BIT5_SHIFT (5U) +/*! BIT5 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM10_RGD_NSE_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM10_RGD_NSE_BIT5_SHIFT)) & TRDC_MBC2_MRC_DOM10_RGD_NSE_BIT5_MASK) + +#define TRDC_MBC2_MRC_DOM10_RGD_NSE_BIT6_MASK (0x40U) +#define TRDC_MBC2_MRC_DOM10_RGD_NSE_BIT6_SHIFT (6U) +/*! BIT6 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM10_RGD_NSE_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM10_RGD_NSE_BIT6_SHIFT)) & TRDC_MBC2_MRC_DOM10_RGD_NSE_BIT6_MASK) + +#define TRDC_MBC2_MRC_DOM10_RGD_NSE_BIT7_MASK (0x80U) +#define TRDC_MBC2_MRC_DOM10_RGD_NSE_BIT7_SHIFT (7U) +/*! BIT7 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM10_RGD_NSE_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM10_RGD_NSE_BIT7_SHIFT)) & TRDC_MBC2_MRC_DOM10_RGD_NSE_BIT7_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MRC_DOM10_RGD_NSE */ +#define TRDC_MBC2_MRC_DOM10_RGD_NSE_COUNT (2U) + +/*! @name MRC_DOM11_RGD_W - MRC Region Descriptor Word 0..MRC Region Descriptor Word 1 */ +/*! @{ */ + +#define TRDC_MBC2_MRC_DOM11_RGD_W_MRACSEL_MASK (0x7U) +#define TRDC_MBC2_MRC_DOM11_RGD_W_MRACSEL_SHIFT (0U) +/*! MRACSEL - Memory Region Access Control Select + * 0b000..Select MRC_GLBAC0 access control policy + * 0b001..Select MRC_GLBAC1 access control policy + * 0b010..Select MRC_GLBAC2 access control policy + * 0b011..Select MRC_GLBAC3 access control policy + * 0b100..Select MRC_GLBAC4 access control policy + * 0b101..Select MRC_GLBAC5 access control policy + * 0b110..Select MRC_GLBAC6 access control policy + * 0b111..Select MRC_GLBAC7 access control policy + */ +#define TRDC_MBC2_MRC_DOM11_RGD_W_MRACSEL(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM11_RGD_W_MRACSEL_SHIFT)) & TRDC_MBC2_MRC_DOM11_RGD_W_MRACSEL_MASK) + +#define TRDC_MBC2_MRC_DOM11_RGD_W_VLD_MASK (0x1U) +#define TRDC_MBC2_MRC_DOM11_RGD_W_VLD_SHIFT (0U) +/*! VLD - Valid */ +#define TRDC_MBC2_MRC_DOM11_RGD_W_VLD(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM11_RGD_W_VLD_SHIFT)) & TRDC_MBC2_MRC_DOM11_RGD_W_VLD_MASK) + +#define TRDC_MBC2_MRC_DOM11_RGD_W_NSE_MASK (0x10U) +#define TRDC_MBC2_MRC_DOM11_RGD_W_NSE_SHIFT (4U) +/*! NSE - NonSecure Enable + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in this register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM11_RGD_W_NSE(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM11_RGD_W_NSE_SHIFT)) & TRDC_MBC2_MRC_DOM11_RGD_W_NSE_MASK) + +#define TRDC_MBC2_MRC_DOM11_RGD_W_END_ADDR_MASK (0xFFFFC000U) +#define TRDC_MBC2_MRC_DOM11_RGD_W_END_ADDR_SHIFT (14U) +/*! END_ADDR - End Address */ +#define TRDC_MBC2_MRC_DOM11_RGD_W_END_ADDR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM11_RGD_W_END_ADDR_SHIFT)) & TRDC_MBC2_MRC_DOM11_RGD_W_END_ADDR_MASK) + +#define TRDC_MBC2_MRC_DOM11_RGD_W_STRT_ADDR_MASK (0xFFFFC000U) +#define TRDC_MBC2_MRC_DOM11_RGD_W_STRT_ADDR_SHIFT (14U) +/*! STRT_ADDR - Start Address */ +#define TRDC_MBC2_MRC_DOM11_RGD_W_STRT_ADDR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM11_RGD_W_STRT_ADDR_SHIFT)) & TRDC_MBC2_MRC_DOM11_RGD_W_STRT_ADDR_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MRC_DOM11_RGD_W */ +#define TRDC_MBC2_MRC_DOM11_RGD_W_COUNT (2U) + +/* The count of TRDC_MBC2_MRC_DOM11_RGD_W */ +#define TRDC_MBC2_MRC_DOM11_RGD_W_COUNT2 (8U) + +/* The count of TRDC_MBC2_MRC_DOM11_RGD_W */ +#define TRDC_MBC2_MRC_DOM11_RGD_W_COUNT3 (2U) + +/*! @name MRC_DOM11_RGD_NSE - MRC Region Descriptor NonSecure Enable */ +/*! @{ */ + +#define TRDC_MBC2_MRC_DOM11_RGD_NSE_BIT0_MASK (0x1U) +#define TRDC_MBC2_MRC_DOM11_RGD_NSE_BIT0_SHIFT (0U) +/*! BIT0 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM11_RGD_NSE_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM11_RGD_NSE_BIT0_SHIFT)) & TRDC_MBC2_MRC_DOM11_RGD_NSE_BIT0_MASK) + +#define TRDC_MBC2_MRC_DOM11_RGD_NSE_BIT1_MASK (0x2U) +#define TRDC_MBC2_MRC_DOM11_RGD_NSE_BIT1_SHIFT (1U) +/*! BIT1 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM11_RGD_NSE_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM11_RGD_NSE_BIT1_SHIFT)) & TRDC_MBC2_MRC_DOM11_RGD_NSE_BIT1_MASK) + +#define TRDC_MBC2_MRC_DOM11_RGD_NSE_BIT2_MASK (0x4U) +#define TRDC_MBC2_MRC_DOM11_RGD_NSE_BIT2_SHIFT (2U) +/*! BIT2 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM11_RGD_NSE_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM11_RGD_NSE_BIT2_SHIFT)) & TRDC_MBC2_MRC_DOM11_RGD_NSE_BIT2_MASK) + +#define TRDC_MBC2_MRC_DOM11_RGD_NSE_BIT3_MASK (0x8U) +#define TRDC_MBC2_MRC_DOM11_RGD_NSE_BIT3_SHIFT (3U) +/*! BIT3 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM11_RGD_NSE_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM11_RGD_NSE_BIT3_SHIFT)) & TRDC_MBC2_MRC_DOM11_RGD_NSE_BIT3_MASK) + +#define TRDC_MBC2_MRC_DOM11_RGD_NSE_BIT4_MASK (0x10U) +#define TRDC_MBC2_MRC_DOM11_RGD_NSE_BIT4_SHIFT (4U) +/*! BIT4 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM11_RGD_NSE_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM11_RGD_NSE_BIT4_SHIFT)) & TRDC_MBC2_MRC_DOM11_RGD_NSE_BIT4_MASK) + +#define TRDC_MBC2_MRC_DOM11_RGD_NSE_BIT5_MASK (0x20U) +#define TRDC_MBC2_MRC_DOM11_RGD_NSE_BIT5_SHIFT (5U) +/*! BIT5 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM11_RGD_NSE_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM11_RGD_NSE_BIT5_SHIFT)) & TRDC_MBC2_MRC_DOM11_RGD_NSE_BIT5_MASK) + +#define TRDC_MBC2_MRC_DOM11_RGD_NSE_BIT6_MASK (0x40U) +#define TRDC_MBC2_MRC_DOM11_RGD_NSE_BIT6_SHIFT (6U) +/*! BIT6 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM11_RGD_NSE_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM11_RGD_NSE_BIT6_SHIFT)) & TRDC_MBC2_MRC_DOM11_RGD_NSE_BIT6_MASK) + +#define TRDC_MBC2_MRC_DOM11_RGD_NSE_BIT7_MASK (0x80U) +#define TRDC_MBC2_MRC_DOM11_RGD_NSE_BIT7_SHIFT (7U) +/*! BIT7 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM11_RGD_NSE_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM11_RGD_NSE_BIT7_SHIFT)) & TRDC_MBC2_MRC_DOM11_RGD_NSE_BIT7_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MRC_DOM11_RGD_NSE */ +#define TRDC_MBC2_MRC_DOM11_RGD_NSE_COUNT (2U) + +/*! @name MRC_DOM12_RGD_W - MRC Region Descriptor Word 0..MRC Region Descriptor Word 1 */ +/*! @{ */ + +#define TRDC_MBC2_MRC_DOM12_RGD_W_MRACSEL_MASK (0x7U) +#define TRDC_MBC2_MRC_DOM12_RGD_W_MRACSEL_SHIFT (0U) +/*! MRACSEL - Memory Region Access Control Select + * 0b000..Select MRC_GLBAC0 access control policy + * 0b001..Select MRC_GLBAC1 access control policy + * 0b010..Select MRC_GLBAC2 access control policy + * 0b011..Select MRC_GLBAC3 access control policy + * 0b100..Select MRC_GLBAC4 access control policy + * 0b101..Select MRC_GLBAC5 access control policy + * 0b110..Select MRC_GLBAC6 access control policy + * 0b111..Select MRC_GLBAC7 access control policy + */ +#define TRDC_MBC2_MRC_DOM12_RGD_W_MRACSEL(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM12_RGD_W_MRACSEL_SHIFT)) & TRDC_MBC2_MRC_DOM12_RGD_W_MRACSEL_MASK) + +#define TRDC_MBC2_MRC_DOM12_RGD_W_VLD_MASK (0x1U) +#define TRDC_MBC2_MRC_DOM12_RGD_W_VLD_SHIFT (0U) +/*! VLD - Valid */ +#define TRDC_MBC2_MRC_DOM12_RGD_W_VLD(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM12_RGD_W_VLD_SHIFT)) & TRDC_MBC2_MRC_DOM12_RGD_W_VLD_MASK) + +#define TRDC_MBC2_MRC_DOM12_RGD_W_NSE_MASK (0x10U) +#define TRDC_MBC2_MRC_DOM12_RGD_W_NSE_SHIFT (4U) +/*! NSE - NonSecure Enable + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in this register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM12_RGD_W_NSE(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM12_RGD_W_NSE_SHIFT)) & TRDC_MBC2_MRC_DOM12_RGD_W_NSE_MASK) + +#define TRDC_MBC2_MRC_DOM12_RGD_W_END_ADDR_MASK (0xFFFFC000U) +#define TRDC_MBC2_MRC_DOM12_RGD_W_END_ADDR_SHIFT (14U) +/*! END_ADDR - End Address */ +#define TRDC_MBC2_MRC_DOM12_RGD_W_END_ADDR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM12_RGD_W_END_ADDR_SHIFT)) & TRDC_MBC2_MRC_DOM12_RGD_W_END_ADDR_MASK) + +#define TRDC_MBC2_MRC_DOM12_RGD_W_STRT_ADDR_MASK (0xFFFFC000U) +#define TRDC_MBC2_MRC_DOM12_RGD_W_STRT_ADDR_SHIFT (14U) +/*! STRT_ADDR - Start Address */ +#define TRDC_MBC2_MRC_DOM12_RGD_W_STRT_ADDR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM12_RGD_W_STRT_ADDR_SHIFT)) & TRDC_MBC2_MRC_DOM12_RGD_W_STRT_ADDR_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MRC_DOM12_RGD_W */ +#define TRDC_MBC2_MRC_DOM12_RGD_W_COUNT (2U) + +/* The count of TRDC_MBC2_MRC_DOM12_RGD_W */ +#define TRDC_MBC2_MRC_DOM12_RGD_W_COUNT2 (8U) + +/* The count of TRDC_MBC2_MRC_DOM12_RGD_W */ +#define TRDC_MBC2_MRC_DOM12_RGD_W_COUNT3 (2U) + +/*! @name MRC_DOM12_RGD_NSE - MRC Region Descriptor NonSecure Enable */ +/*! @{ */ + +#define TRDC_MBC2_MRC_DOM12_RGD_NSE_BIT0_MASK (0x1U) +#define TRDC_MBC2_MRC_DOM12_RGD_NSE_BIT0_SHIFT (0U) +/*! BIT0 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM12_RGD_NSE_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM12_RGD_NSE_BIT0_SHIFT)) & TRDC_MBC2_MRC_DOM12_RGD_NSE_BIT0_MASK) + +#define TRDC_MBC2_MRC_DOM12_RGD_NSE_BIT1_MASK (0x2U) +#define TRDC_MBC2_MRC_DOM12_RGD_NSE_BIT1_SHIFT (1U) +/*! BIT1 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM12_RGD_NSE_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM12_RGD_NSE_BIT1_SHIFT)) & TRDC_MBC2_MRC_DOM12_RGD_NSE_BIT1_MASK) + +#define TRDC_MBC2_MRC_DOM12_RGD_NSE_BIT2_MASK (0x4U) +#define TRDC_MBC2_MRC_DOM12_RGD_NSE_BIT2_SHIFT (2U) +/*! BIT2 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM12_RGD_NSE_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM12_RGD_NSE_BIT2_SHIFT)) & TRDC_MBC2_MRC_DOM12_RGD_NSE_BIT2_MASK) + +#define TRDC_MBC2_MRC_DOM12_RGD_NSE_BIT3_MASK (0x8U) +#define TRDC_MBC2_MRC_DOM12_RGD_NSE_BIT3_SHIFT (3U) +/*! BIT3 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM12_RGD_NSE_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM12_RGD_NSE_BIT3_SHIFT)) & TRDC_MBC2_MRC_DOM12_RGD_NSE_BIT3_MASK) + +#define TRDC_MBC2_MRC_DOM12_RGD_NSE_BIT4_MASK (0x10U) +#define TRDC_MBC2_MRC_DOM12_RGD_NSE_BIT4_SHIFT (4U) +/*! BIT4 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM12_RGD_NSE_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM12_RGD_NSE_BIT4_SHIFT)) & TRDC_MBC2_MRC_DOM12_RGD_NSE_BIT4_MASK) + +#define TRDC_MBC2_MRC_DOM12_RGD_NSE_BIT5_MASK (0x20U) +#define TRDC_MBC2_MRC_DOM12_RGD_NSE_BIT5_SHIFT (5U) +/*! BIT5 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM12_RGD_NSE_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM12_RGD_NSE_BIT5_SHIFT)) & TRDC_MBC2_MRC_DOM12_RGD_NSE_BIT5_MASK) + +#define TRDC_MBC2_MRC_DOM12_RGD_NSE_BIT6_MASK (0x40U) +#define TRDC_MBC2_MRC_DOM12_RGD_NSE_BIT6_SHIFT (6U) +/*! BIT6 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM12_RGD_NSE_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM12_RGD_NSE_BIT6_SHIFT)) & TRDC_MBC2_MRC_DOM12_RGD_NSE_BIT6_MASK) + +#define TRDC_MBC2_MRC_DOM12_RGD_NSE_BIT7_MASK (0x80U) +#define TRDC_MBC2_MRC_DOM12_RGD_NSE_BIT7_SHIFT (7U) +/*! BIT7 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM12_RGD_NSE_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM12_RGD_NSE_BIT7_SHIFT)) & TRDC_MBC2_MRC_DOM12_RGD_NSE_BIT7_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MRC_DOM12_RGD_NSE */ +#define TRDC_MBC2_MRC_DOM12_RGD_NSE_COUNT (2U) + +/*! @name MRC_DOM13_RGD_W - MRC Region Descriptor Word 0..MRC Region Descriptor Word 1 */ +/*! @{ */ + +#define TRDC_MBC2_MRC_DOM13_RGD_W_MRACSEL_MASK (0x7U) +#define TRDC_MBC2_MRC_DOM13_RGD_W_MRACSEL_SHIFT (0U) +/*! MRACSEL - Memory Region Access Control Select + * 0b000..Select MRC_GLBAC0 access control policy + * 0b001..Select MRC_GLBAC1 access control policy + * 0b010..Select MRC_GLBAC2 access control policy + * 0b011..Select MRC_GLBAC3 access control policy + * 0b100..Select MRC_GLBAC4 access control policy + * 0b101..Select MRC_GLBAC5 access control policy + * 0b110..Select MRC_GLBAC6 access control policy + * 0b111..Select MRC_GLBAC7 access control policy + */ +#define TRDC_MBC2_MRC_DOM13_RGD_W_MRACSEL(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM13_RGD_W_MRACSEL_SHIFT)) & TRDC_MBC2_MRC_DOM13_RGD_W_MRACSEL_MASK) + +#define TRDC_MBC2_MRC_DOM13_RGD_W_VLD_MASK (0x1U) +#define TRDC_MBC2_MRC_DOM13_RGD_W_VLD_SHIFT (0U) +/*! VLD - Valid */ +#define TRDC_MBC2_MRC_DOM13_RGD_W_VLD(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM13_RGD_W_VLD_SHIFT)) & TRDC_MBC2_MRC_DOM13_RGD_W_VLD_MASK) + +#define TRDC_MBC2_MRC_DOM13_RGD_W_NSE_MASK (0x10U) +#define TRDC_MBC2_MRC_DOM13_RGD_W_NSE_SHIFT (4U) +/*! NSE - NonSecure Enable + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in this register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM13_RGD_W_NSE(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM13_RGD_W_NSE_SHIFT)) & TRDC_MBC2_MRC_DOM13_RGD_W_NSE_MASK) + +#define TRDC_MBC2_MRC_DOM13_RGD_W_END_ADDR_MASK (0xFFFFC000U) +#define TRDC_MBC2_MRC_DOM13_RGD_W_END_ADDR_SHIFT (14U) +/*! END_ADDR - End Address */ +#define TRDC_MBC2_MRC_DOM13_RGD_W_END_ADDR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM13_RGD_W_END_ADDR_SHIFT)) & TRDC_MBC2_MRC_DOM13_RGD_W_END_ADDR_MASK) + +#define TRDC_MBC2_MRC_DOM13_RGD_W_STRT_ADDR_MASK (0xFFFFC000U) +#define TRDC_MBC2_MRC_DOM13_RGD_W_STRT_ADDR_SHIFT (14U) +/*! STRT_ADDR - Start Address */ +#define TRDC_MBC2_MRC_DOM13_RGD_W_STRT_ADDR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM13_RGD_W_STRT_ADDR_SHIFT)) & TRDC_MBC2_MRC_DOM13_RGD_W_STRT_ADDR_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MRC_DOM13_RGD_W */ +#define TRDC_MBC2_MRC_DOM13_RGD_W_COUNT (2U) + +/* The count of TRDC_MBC2_MRC_DOM13_RGD_W */ +#define TRDC_MBC2_MRC_DOM13_RGD_W_COUNT2 (8U) + +/* The count of TRDC_MBC2_MRC_DOM13_RGD_W */ +#define TRDC_MBC2_MRC_DOM13_RGD_W_COUNT3 (2U) + +/*! @name MRC_DOM13_RGD_NSE - MRC Region Descriptor NonSecure Enable */ +/*! @{ */ + +#define TRDC_MBC2_MRC_DOM13_RGD_NSE_BIT0_MASK (0x1U) +#define TRDC_MBC2_MRC_DOM13_RGD_NSE_BIT0_SHIFT (0U) +/*! BIT0 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM13_RGD_NSE_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM13_RGD_NSE_BIT0_SHIFT)) & TRDC_MBC2_MRC_DOM13_RGD_NSE_BIT0_MASK) + +#define TRDC_MBC2_MRC_DOM13_RGD_NSE_BIT1_MASK (0x2U) +#define TRDC_MBC2_MRC_DOM13_RGD_NSE_BIT1_SHIFT (1U) +/*! BIT1 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM13_RGD_NSE_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM13_RGD_NSE_BIT1_SHIFT)) & TRDC_MBC2_MRC_DOM13_RGD_NSE_BIT1_MASK) + +#define TRDC_MBC2_MRC_DOM13_RGD_NSE_BIT2_MASK (0x4U) +#define TRDC_MBC2_MRC_DOM13_RGD_NSE_BIT2_SHIFT (2U) +/*! BIT2 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM13_RGD_NSE_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM13_RGD_NSE_BIT2_SHIFT)) & TRDC_MBC2_MRC_DOM13_RGD_NSE_BIT2_MASK) + +#define TRDC_MBC2_MRC_DOM13_RGD_NSE_BIT3_MASK (0x8U) +#define TRDC_MBC2_MRC_DOM13_RGD_NSE_BIT3_SHIFT (3U) +/*! BIT3 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM13_RGD_NSE_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM13_RGD_NSE_BIT3_SHIFT)) & TRDC_MBC2_MRC_DOM13_RGD_NSE_BIT3_MASK) + +#define TRDC_MBC2_MRC_DOM13_RGD_NSE_BIT4_MASK (0x10U) +#define TRDC_MBC2_MRC_DOM13_RGD_NSE_BIT4_SHIFT (4U) +/*! BIT4 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM13_RGD_NSE_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM13_RGD_NSE_BIT4_SHIFT)) & TRDC_MBC2_MRC_DOM13_RGD_NSE_BIT4_MASK) + +#define TRDC_MBC2_MRC_DOM13_RGD_NSE_BIT5_MASK (0x20U) +#define TRDC_MBC2_MRC_DOM13_RGD_NSE_BIT5_SHIFT (5U) +/*! BIT5 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM13_RGD_NSE_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM13_RGD_NSE_BIT5_SHIFT)) & TRDC_MBC2_MRC_DOM13_RGD_NSE_BIT5_MASK) + +#define TRDC_MBC2_MRC_DOM13_RGD_NSE_BIT6_MASK (0x40U) +#define TRDC_MBC2_MRC_DOM13_RGD_NSE_BIT6_SHIFT (6U) +/*! BIT6 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM13_RGD_NSE_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM13_RGD_NSE_BIT6_SHIFT)) & TRDC_MBC2_MRC_DOM13_RGD_NSE_BIT6_MASK) + +#define TRDC_MBC2_MRC_DOM13_RGD_NSE_BIT7_MASK (0x80U) +#define TRDC_MBC2_MRC_DOM13_RGD_NSE_BIT7_SHIFT (7U) +/*! BIT7 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM13_RGD_NSE_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM13_RGD_NSE_BIT7_SHIFT)) & TRDC_MBC2_MRC_DOM13_RGD_NSE_BIT7_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MRC_DOM13_RGD_NSE */ +#define TRDC_MBC2_MRC_DOM13_RGD_NSE_COUNT (2U) + +/*! @name MRC_DOM14_RGD_W - MRC Region Descriptor Word 0..MRC Region Descriptor Word 1 */ +/*! @{ */ + +#define TRDC_MBC2_MRC_DOM14_RGD_W_MRACSEL_MASK (0x7U) +#define TRDC_MBC2_MRC_DOM14_RGD_W_MRACSEL_SHIFT (0U) +/*! MRACSEL - Memory Region Access Control Select + * 0b000..Select MRC_GLBAC0 access control policy + * 0b001..Select MRC_GLBAC1 access control policy + * 0b010..Select MRC_GLBAC2 access control policy + * 0b011..Select MRC_GLBAC3 access control policy + * 0b100..Select MRC_GLBAC4 access control policy + * 0b101..Select MRC_GLBAC5 access control policy + * 0b110..Select MRC_GLBAC6 access control policy + * 0b111..Select MRC_GLBAC7 access control policy + */ +#define TRDC_MBC2_MRC_DOM14_RGD_W_MRACSEL(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM14_RGD_W_MRACSEL_SHIFT)) & TRDC_MBC2_MRC_DOM14_RGD_W_MRACSEL_MASK) + +#define TRDC_MBC2_MRC_DOM14_RGD_W_VLD_MASK (0x1U) +#define TRDC_MBC2_MRC_DOM14_RGD_W_VLD_SHIFT (0U) +/*! VLD - Valid */ +#define TRDC_MBC2_MRC_DOM14_RGD_W_VLD(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM14_RGD_W_VLD_SHIFT)) & TRDC_MBC2_MRC_DOM14_RGD_W_VLD_MASK) + +#define TRDC_MBC2_MRC_DOM14_RGD_W_NSE_MASK (0x10U) +#define TRDC_MBC2_MRC_DOM14_RGD_W_NSE_SHIFT (4U) +/*! NSE - NonSecure Enable + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in this register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM14_RGD_W_NSE(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM14_RGD_W_NSE_SHIFT)) & TRDC_MBC2_MRC_DOM14_RGD_W_NSE_MASK) + +#define TRDC_MBC2_MRC_DOM14_RGD_W_END_ADDR_MASK (0xFFFFC000U) +#define TRDC_MBC2_MRC_DOM14_RGD_W_END_ADDR_SHIFT (14U) +/*! END_ADDR - End Address */ +#define TRDC_MBC2_MRC_DOM14_RGD_W_END_ADDR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM14_RGD_W_END_ADDR_SHIFT)) & TRDC_MBC2_MRC_DOM14_RGD_W_END_ADDR_MASK) + +#define TRDC_MBC2_MRC_DOM14_RGD_W_STRT_ADDR_MASK (0xFFFFC000U) +#define TRDC_MBC2_MRC_DOM14_RGD_W_STRT_ADDR_SHIFT (14U) +/*! STRT_ADDR - Start Address */ +#define TRDC_MBC2_MRC_DOM14_RGD_W_STRT_ADDR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM14_RGD_W_STRT_ADDR_SHIFT)) & TRDC_MBC2_MRC_DOM14_RGD_W_STRT_ADDR_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MRC_DOM14_RGD_W */ +#define TRDC_MBC2_MRC_DOM14_RGD_W_COUNT (2U) + +/* The count of TRDC_MBC2_MRC_DOM14_RGD_W */ +#define TRDC_MBC2_MRC_DOM14_RGD_W_COUNT2 (8U) + +/* The count of TRDC_MBC2_MRC_DOM14_RGD_W */ +#define TRDC_MBC2_MRC_DOM14_RGD_W_COUNT3 (2U) + +/*! @name MRC_DOM14_RGD_NSE - MRC Region Descriptor NonSecure Enable */ +/*! @{ */ + +#define TRDC_MBC2_MRC_DOM14_RGD_NSE_BIT0_MASK (0x1U) +#define TRDC_MBC2_MRC_DOM14_RGD_NSE_BIT0_SHIFT (0U) +/*! BIT0 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM14_RGD_NSE_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM14_RGD_NSE_BIT0_SHIFT)) & TRDC_MBC2_MRC_DOM14_RGD_NSE_BIT0_MASK) + +#define TRDC_MBC2_MRC_DOM14_RGD_NSE_BIT1_MASK (0x2U) +#define TRDC_MBC2_MRC_DOM14_RGD_NSE_BIT1_SHIFT (1U) +/*! BIT1 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM14_RGD_NSE_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM14_RGD_NSE_BIT1_SHIFT)) & TRDC_MBC2_MRC_DOM14_RGD_NSE_BIT1_MASK) + +#define TRDC_MBC2_MRC_DOM14_RGD_NSE_BIT2_MASK (0x4U) +#define TRDC_MBC2_MRC_DOM14_RGD_NSE_BIT2_SHIFT (2U) +/*! BIT2 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM14_RGD_NSE_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM14_RGD_NSE_BIT2_SHIFT)) & TRDC_MBC2_MRC_DOM14_RGD_NSE_BIT2_MASK) + +#define TRDC_MBC2_MRC_DOM14_RGD_NSE_BIT3_MASK (0x8U) +#define TRDC_MBC2_MRC_DOM14_RGD_NSE_BIT3_SHIFT (3U) +/*! BIT3 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM14_RGD_NSE_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM14_RGD_NSE_BIT3_SHIFT)) & TRDC_MBC2_MRC_DOM14_RGD_NSE_BIT3_MASK) + +#define TRDC_MBC2_MRC_DOM14_RGD_NSE_BIT4_MASK (0x10U) +#define TRDC_MBC2_MRC_DOM14_RGD_NSE_BIT4_SHIFT (4U) +/*! BIT4 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM14_RGD_NSE_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM14_RGD_NSE_BIT4_SHIFT)) & TRDC_MBC2_MRC_DOM14_RGD_NSE_BIT4_MASK) + +#define TRDC_MBC2_MRC_DOM14_RGD_NSE_BIT5_MASK (0x20U) +#define TRDC_MBC2_MRC_DOM14_RGD_NSE_BIT5_SHIFT (5U) +/*! BIT5 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM14_RGD_NSE_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM14_RGD_NSE_BIT5_SHIFT)) & TRDC_MBC2_MRC_DOM14_RGD_NSE_BIT5_MASK) + +#define TRDC_MBC2_MRC_DOM14_RGD_NSE_BIT6_MASK (0x40U) +#define TRDC_MBC2_MRC_DOM14_RGD_NSE_BIT6_SHIFT (6U) +/*! BIT6 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM14_RGD_NSE_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM14_RGD_NSE_BIT6_SHIFT)) & TRDC_MBC2_MRC_DOM14_RGD_NSE_BIT6_MASK) + +#define TRDC_MBC2_MRC_DOM14_RGD_NSE_BIT7_MASK (0x80U) +#define TRDC_MBC2_MRC_DOM14_RGD_NSE_BIT7_SHIFT (7U) +/*! BIT7 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM14_RGD_NSE_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM14_RGD_NSE_BIT7_SHIFT)) & TRDC_MBC2_MRC_DOM14_RGD_NSE_BIT7_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MRC_DOM14_RGD_NSE */ +#define TRDC_MBC2_MRC_DOM14_RGD_NSE_COUNT (2U) + +/*! @name MRC_DOM15_RGD_W - MRC Region Descriptor Word 0..MRC Region Descriptor Word 1 */ +/*! @{ */ + +#define TRDC_MBC2_MRC_DOM15_RGD_W_MRACSEL_MASK (0x7U) +#define TRDC_MBC2_MRC_DOM15_RGD_W_MRACSEL_SHIFT (0U) +/*! MRACSEL - Memory Region Access Control Select + * 0b000..Select MRC_GLBAC0 access control policy + * 0b001..Select MRC_GLBAC1 access control policy + * 0b010..Select MRC_GLBAC2 access control policy + * 0b011..Select MRC_GLBAC3 access control policy + * 0b100..Select MRC_GLBAC4 access control policy + * 0b101..Select MRC_GLBAC5 access control policy + * 0b110..Select MRC_GLBAC6 access control policy + * 0b111..Select MRC_GLBAC7 access control policy + */ +#define TRDC_MBC2_MRC_DOM15_RGD_W_MRACSEL(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM15_RGD_W_MRACSEL_SHIFT)) & TRDC_MBC2_MRC_DOM15_RGD_W_MRACSEL_MASK) + +#define TRDC_MBC2_MRC_DOM15_RGD_W_VLD_MASK (0x1U) +#define TRDC_MBC2_MRC_DOM15_RGD_W_VLD_SHIFT (0U) +/*! VLD - Valid */ +#define TRDC_MBC2_MRC_DOM15_RGD_W_VLD(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM15_RGD_W_VLD_SHIFT)) & TRDC_MBC2_MRC_DOM15_RGD_W_VLD_MASK) + +#define TRDC_MBC2_MRC_DOM15_RGD_W_NSE_MASK (0x10U) +#define TRDC_MBC2_MRC_DOM15_RGD_W_NSE_SHIFT (4U) +/*! NSE - NonSecure Enable + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in this register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM15_RGD_W_NSE(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM15_RGD_W_NSE_SHIFT)) & TRDC_MBC2_MRC_DOM15_RGD_W_NSE_MASK) + +#define TRDC_MBC2_MRC_DOM15_RGD_W_END_ADDR_MASK (0xFFFFC000U) +#define TRDC_MBC2_MRC_DOM15_RGD_W_END_ADDR_SHIFT (14U) +/*! END_ADDR - End Address */ +#define TRDC_MBC2_MRC_DOM15_RGD_W_END_ADDR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM15_RGD_W_END_ADDR_SHIFT)) & TRDC_MBC2_MRC_DOM15_RGD_W_END_ADDR_MASK) + +#define TRDC_MBC2_MRC_DOM15_RGD_W_STRT_ADDR_MASK (0xFFFFC000U) +#define TRDC_MBC2_MRC_DOM15_RGD_W_STRT_ADDR_SHIFT (14U) +/*! STRT_ADDR - Start Address */ +#define TRDC_MBC2_MRC_DOM15_RGD_W_STRT_ADDR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM15_RGD_W_STRT_ADDR_SHIFT)) & TRDC_MBC2_MRC_DOM15_RGD_W_STRT_ADDR_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MRC_DOM15_RGD_W */ +#define TRDC_MBC2_MRC_DOM15_RGD_W_COUNT (2U) + +/* The count of TRDC_MBC2_MRC_DOM15_RGD_W */ +#define TRDC_MBC2_MRC_DOM15_RGD_W_COUNT2 (8U) + +/* The count of TRDC_MBC2_MRC_DOM15_RGD_W */ +#define TRDC_MBC2_MRC_DOM15_RGD_W_COUNT3 (2U) + +/*! @name MRC_DOM15_RGD_NSE - MRC Region Descriptor NonSecure Enable */ +/*! @{ */ + +#define TRDC_MBC2_MRC_DOM15_RGD_NSE_BIT0_MASK (0x1U) +#define TRDC_MBC2_MRC_DOM15_RGD_NSE_BIT0_SHIFT (0U) +/*! BIT0 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM15_RGD_NSE_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM15_RGD_NSE_BIT0_SHIFT)) & TRDC_MBC2_MRC_DOM15_RGD_NSE_BIT0_MASK) + +#define TRDC_MBC2_MRC_DOM15_RGD_NSE_BIT1_MASK (0x2U) +#define TRDC_MBC2_MRC_DOM15_RGD_NSE_BIT1_SHIFT (1U) +/*! BIT1 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM15_RGD_NSE_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM15_RGD_NSE_BIT1_SHIFT)) & TRDC_MBC2_MRC_DOM15_RGD_NSE_BIT1_MASK) + +#define TRDC_MBC2_MRC_DOM15_RGD_NSE_BIT2_MASK (0x4U) +#define TRDC_MBC2_MRC_DOM15_RGD_NSE_BIT2_SHIFT (2U) +/*! BIT2 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM15_RGD_NSE_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM15_RGD_NSE_BIT2_SHIFT)) & TRDC_MBC2_MRC_DOM15_RGD_NSE_BIT2_MASK) + +#define TRDC_MBC2_MRC_DOM15_RGD_NSE_BIT3_MASK (0x8U) +#define TRDC_MBC2_MRC_DOM15_RGD_NSE_BIT3_SHIFT (3U) +/*! BIT3 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM15_RGD_NSE_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM15_RGD_NSE_BIT3_SHIFT)) & TRDC_MBC2_MRC_DOM15_RGD_NSE_BIT3_MASK) + +#define TRDC_MBC2_MRC_DOM15_RGD_NSE_BIT4_MASK (0x10U) +#define TRDC_MBC2_MRC_DOM15_RGD_NSE_BIT4_SHIFT (4U) +/*! BIT4 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM15_RGD_NSE_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM15_RGD_NSE_BIT4_SHIFT)) & TRDC_MBC2_MRC_DOM15_RGD_NSE_BIT4_MASK) + +#define TRDC_MBC2_MRC_DOM15_RGD_NSE_BIT5_MASK (0x20U) +#define TRDC_MBC2_MRC_DOM15_RGD_NSE_BIT5_SHIFT (5U) +/*! BIT5 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM15_RGD_NSE_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM15_RGD_NSE_BIT5_SHIFT)) & TRDC_MBC2_MRC_DOM15_RGD_NSE_BIT5_MASK) + +#define TRDC_MBC2_MRC_DOM15_RGD_NSE_BIT6_MASK (0x40U) +#define TRDC_MBC2_MRC_DOM15_RGD_NSE_BIT6_SHIFT (6U) +/*! BIT6 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM15_RGD_NSE_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM15_RGD_NSE_BIT6_SHIFT)) & TRDC_MBC2_MRC_DOM15_RGD_NSE_BIT6_MASK) + +#define TRDC_MBC2_MRC_DOM15_RGD_NSE_BIT7_MASK (0x80U) +#define TRDC_MBC2_MRC_DOM15_RGD_NSE_BIT7_SHIFT (7U) +/*! BIT7 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding + * MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC2_MRC_DOM15_RGD_NSE_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC2_MRC_DOM15_RGD_NSE_BIT7_SHIFT)) & TRDC_MBC2_MRC_DOM15_RGD_NSE_BIT7_MASK) +/*! @} */ + +/* The count of TRDC_MBC2_MRC_DOM15_RGD_NSE */ +#define TRDC_MBC2_MRC_DOM15_RGD_NSE_COUNT (2U) + + +/*! + * @} + */ /* end of group TRDC_MBC2_Register_Masks */ + + +/* TRDC_MBC2 - Peripheral instance base addresses */ +/** Peripheral TRDC1 base address */ +#define TRDC1_BASE (0x44270000u) +/** Peripheral TRDC1 base pointer */ +#define TRDC1 ((TRDC_MBC2_Type *)TRDC1_BASE) +/** Peripheral TRDC2 base address */ +#define TRDC2_BASE (0x42460000u) +/** Peripheral TRDC2 base pointer */ +#define TRDC2 ((TRDC_MBC2_Type *)TRDC2_BASE) +/** Array initializer of TRDC_MBC2 peripheral base addresses */ +#define TRDC_MBC2_BASE_ADDRS { 0u, TRDC1_BASE, TRDC2_BASE } +/** Array initializer of TRDC_MBC2 peripheral base pointers */ +#define TRDC_MBC2_BASE_PTRS { (TRDC_MBC2_Type *)0u, TRDC1, TRDC2 } + +/*! + * @} + */ /* end of group TRDC_MBC2_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- TRDC_MBC4 Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup TRDC_MBC4_Peripheral_Access_Layer TRDC_MBC4 Peripheral Access Layer + * @{ + */ + +/** TRDC_MBC4 - Register Layout Typedef */ +typedef struct { + __IO uint32_t TRDC_CR; /**< TRDC Register, offset: 0x0 */ + uint8_t RESERVED_0[236]; + __I uint32_t TRDC_HWCFG0; /**< TRDC Hardware Configuration Register 0, offset: 0xF0 */ + __I uint32_t TRDC_HWCFG1; /**< TRDC Hardware Configuration Register 1, offset: 0xF4 */ + __I uint32_t TRDC_HWCFG2; /**< TRDC Hardware Configuration Register 2, offset: 0xF8 */ + __I uint32_t TRDC_HWCFG3; /**< TRDC Hardware Configuration Register 3, offset: 0xFC */ + __I uint8_t DACFG[2]; /**< Domain Assignment Configuration Register, array offset: 0x100, array step: 0x1 */ + uint8_t RESERVED_1[190]; + __IO uint32_t TRDC_IDAU_CR; /**< TRDC IDAU Control Register, offset: 0x1C0 */ + uint8_t RESERVED_2[28]; + __IO uint32_t TRDC_FLW_CTL; /**< TRDC FLW Control, offset: 0x1E0 */ + __I uint32_t TRDC_FLW_PBASE; /**< TRDC FLW Physical Base, offset: 0x1E4 */ + __IO uint32_t TRDC_FLW_ABASE; /**< TRDC FLW Array Base, offset: 0x1E8 */ + __IO uint32_t TRDC_FLW_BCNT; /**< TRDC FLW Block Count, offset: 0x1EC */ + uint8_t RESERVED_3[12]; + __IO uint32_t TRDC_FDID; /**< TRDC Fault Domain ID, offset: 0x1FC */ + __I uint32_t TRDC_DERRLOC[16]; /**< TRDC Domain Error Location Register, array offset: 0x200, array step: 0x4 */ + uint8_t RESERVED_4[448]; + struct { /* offset: 0x400, array step: 0x10 */ + __I uint32_t W0; /**< MBC Domain Error Word0 Register, array offset: 0x400, array step: 0x10 */ + __I uint32_t W1; /**< MBC Domain Error Word1 Register, array offset: 0x404, array step: 0x10 */ + uint8_t RESERVED_0[4]; + __IO uint32_t W3; /**< MBC Domain Error Word3 Register, array offset: 0x40C, array step: 0x10 */ + } MBC_DERR[4]; + uint8_t RESERVED_5[64]; + struct { /* offset: 0x480, array step: 0x10 */ + __I uint32_t W0; /**< MRC Domain Error Word0 Register, array offset: 0x480, array step: 0x10 */ + __I uint32_t W1; /**< MRC Domain Error Word1 Register, array offset: 0x484, array step: 0x10 */ + uint8_t RESERVED_0[4]; + __IO uint32_t W3; /**< MRC Domain Error Word3 Register, array offset: 0x48C, array step: 0x10 */ + } MRC_DERR[1]; + uint8_t RESERVED_6[880]; + struct { /* offset: 0x800, array step: 0x20 */ + union { /* offset: 0x800, array step: 0x20 */ + struct { /* offset: 0x800, array step: index*0x20, index2*0x4 */ + __IO uint32_t MDA_W_DFMT0; /**< DAC Master Domain Assignment Register, array offset: 0x800, array step: index*0x20, index2*0x4 */ + } MDA_Wx_DFMT0[4]; + } MDA_W_DFMT; + uint8_t RESERVED_0[16]; + } MDA_Wx_y_DFMT[2]; + uint8_t RESERVED_7[63424]; + struct { /* offset: 0x10000, array step: 0x2000 */ + __I uint32_t MBC_MEM_GLBCFG[4]; /**< MBC Global Configuration Register, array offset: 0x10000, array step: index*0x2000, index2*0x4 */ + __IO uint32_t MBC_NSE_BLK_INDEX; /**< MBC NonSecure Enable Block Index, array offset: 0x10010, array step: 0x2000 */ + __IO uint32_t MBC_NSE_BLK_SET; /**< MBC NonSecure Enable Block Set, array offset: 0x10014, array step: 0x2000 */ + __IO uint32_t MBC_NSE_BLK_CLR; /**< MBC NonSecure Enable Block Clear, array offset: 0x10018, array step: 0x2000 */ + __IO uint32_t MBC_NSE_BLK_CLR_ALL; /**< MBC NonSecure Enable Block Clear All, array offset: 0x1001C, array step: 0x2000 */ + __IO uint32_t MBC_MEMN_GLBAC[8]; /**< MBC Global Access Control, array offset: 0x10020, array step: index*0x2000, index2*0x4 */ + __IO uint32_t MBC_DOM0_MEM0_BLK_CFG_W[7]; /**< MBC Memory Block Configuration Word, array offset: 0x10040, array step: index*0x2000, index2*0x4, valid indices: [0][0-6], [1][0], [2][0], [3][0-2] */ + uint8_t RESERVED_0[228]; + __IO uint32_t MBC_DOM0_MEM0_BLK_NSE_W[2]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x10140, array step: index*0x2000, index2*0x4, valid indices: [0-3][0], [0][1] */ + uint8_t RESERVED_1[56]; + __IO uint32_t MBC_DOM0_MEM1_BLK_CFG_W[3]; /**< MBC Memory Block Configuration Word, array offset: 0x10180, array step: index*0x2000, index2*0x4, valid indices: [0-3][0], [0, 3][1], [3][2] */ + uint8_t RESERVED_2[20]; + __IO uint32_t MBC_DOM0_MEM1_BLK_NSE_W[1]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x101A0, array step: index*0x2000, index2*0x4 */ + uint8_t RESERVED_3[4]; + __IO uint32_t MBC_DOM0_MEM2_BLK_CFG_W[5]; /**< MBC Memory Block Configuration Word, array offset: 0x101A8, array step: index*0x2000, index2*0x4, valid indices: [0][0-4] */ + uint8_t RESERVED_4[12]; + __IO uint32_t MBC_DOM0_MEM2_BLK_NSE_W[2]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x101C8, array step: index*0x2000, index2*0x4, valid indices: [0][0-1] */ + __IO uint32_t MBC_DOM0_MEM3_BLK_CFG_W[6]; /**< MBC Memory Block Configuration Word, array offset: 0x101D0, array step: index*0x2000, index2*0x4, valid indices: [0][0-5] */ + uint8_t RESERVED_5[8]; + __IO uint32_t MBC_DOM0_MEM3_BLK_NSE_W[2]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x101F0, array step: index*0x2000, index2*0x4, valid indices: [0][0-1] */ + uint8_t RESERVED_6[72]; + __IO uint32_t MBC_DOM1_MEM0_BLK_CFG_W[7]; /**< MBC Memory Block Configuration Word, array offset: 0x10240, array step: index*0x2000, index2*0x4, valid indices: [0][0-6], [1][0], [2][0], [3][0-2] */ + uint8_t RESERVED_7[228]; + __IO uint32_t MBC_DOM1_MEM0_BLK_NSE_W[2]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x10340, array step: index*0x2000, index2*0x4, valid indices: [0-3][0], [0][1] */ + uint8_t RESERVED_8[56]; + __IO uint32_t MBC_DOM1_MEM1_BLK_CFG_W[3]; /**< MBC Memory Block Configuration Word, array offset: 0x10380, array step: index*0x2000, index2*0x4, valid indices: [0-3][0], [0, 3][1], [3][2] */ + uint8_t RESERVED_9[20]; + __IO uint32_t MBC_DOM1_MEM1_BLK_NSE_W[1]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x103A0, array step: index*0x2000, index2*0x4 */ + uint8_t RESERVED_10[4]; + __IO uint32_t MBC_DOM1_MEM2_BLK_CFG_W[5]; /**< MBC Memory Block Configuration Word, array offset: 0x103A8, array step: index*0x2000, index2*0x4, valid indices: [0][0-4] */ + uint8_t RESERVED_11[12]; + __IO uint32_t MBC_DOM1_MEM2_BLK_NSE_W[2]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x103C8, array step: index*0x2000, index2*0x4, valid indices: [0][0-1] */ + __IO uint32_t MBC_DOM1_MEM3_BLK_CFG_W[6]; /**< MBC Memory Block Configuration Word, array offset: 0x103D0, array step: index*0x2000, index2*0x4, valid indices: [0][0-5] */ + uint8_t RESERVED_12[8]; + __IO uint32_t MBC_DOM1_MEM3_BLK_NSE_W[2]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x103F0, array step: index*0x2000, index2*0x4, valid indices: [0][0-1] */ + uint8_t RESERVED_13[72]; + __IO uint32_t MBC_DOM2_MEM0_BLK_CFG_W[7]; /**< MBC Memory Block Configuration Word, array offset: 0x10440, array step: index*0x2000, index2*0x4, valid indices: [0][0-6], [1][0], [2][0], [3][0-2] */ + uint8_t RESERVED_14[228]; + __IO uint32_t MBC_DOM2_MEM0_BLK_NSE_W[2]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x10540, array step: index*0x2000, index2*0x4, valid indices: [0-3][0], [0][1] */ + uint8_t RESERVED_15[56]; + __IO uint32_t MBC_DOM2_MEM1_BLK_CFG_W[3]; /**< MBC Memory Block Configuration Word, array offset: 0x10580, array step: index*0x2000, index2*0x4, valid indices: [0-3][0], [0, 3][1], [3][2] */ + uint8_t RESERVED_16[20]; + __IO uint32_t MBC_DOM2_MEM1_BLK_NSE_W[1]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x105A0, array step: index*0x2000, index2*0x4 */ + uint8_t RESERVED_17[4]; + __IO uint32_t MBC_DOM2_MEM2_BLK_CFG_W[5]; /**< MBC Memory Block Configuration Word, array offset: 0x105A8, array step: index*0x2000, index2*0x4, valid indices: [0][0-4] */ + uint8_t RESERVED_18[12]; + __IO uint32_t MBC_DOM2_MEM2_BLK_NSE_W[2]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x105C8, array step: index*0x2000, index2*0x4, valid indices: [0][0-1] */ + __IO uint32_t MBC_DOM2_MEM3_BLK_CFG_W[6]; /**< MBC Memory Block Configuration Word, array offset: 0x105D0, array step: index*0x2000, index2*0x4, valid indices: [0][0-5] */ + uint8_t RESERVED_19[8]; + __IO uint32_t MBC_DOM2_MEM3_BLK_NSE_W[2]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x105F0, array step: index*0x2000, index2*0x4, valid indices: [0][0-1] */ + uint8_t RESERVED_20[72]; + __IO uint32_t MBC_DOM3_MEM0_BLK_CFG_W[7]; /**< MBC Memory Block Configuration Word, array offset: 0x10640, array step: index*0x2000, index2*0x4, valid indices: [0][0-6], [1][0], [2][0], [3][0-2] */ + uint8_t RESERVED_21[228]; + __IO uint32_t MBC_DOM3_MEM0_BLK_NSE_W[2]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x10740, array step: index*0x2000, index2*0x4, valid indices: [0-3][0], [0][1] */ + uint8_t RESERVED_22[56]; + __IO uint32_t MBC_DOM3_MEM1_BLK_CFG_W[3]; /**< MBC Memory Block Configuration Word, array offset: 0x10780, array step: index*0x2000, index2*0x4, valid indices: [0-3][0], [0, 3][1], [3][2] */ + uint8_t RESERVED_23[20]; + __IO uint32_t MBC_DOM3_MEM1_BLK_NSE_W[1]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x107A0, array step: index*0x2000, index2*0x4 */ + uint8_t RESERVED_24[4]; + __IO uint32_t MBC_DOM3_MEM2_BLK_CFG_W[5]; /**< MBC Memory Block Configuration Word, array offset: 0x107A8, array step: index*0x2000, index2*0x4, valid indices: [0][0-4] */ + uint8_t RESERVED_25[12]; + __IO uint32_t MBC_DOM3_MEM2_BLK_NSE_W[2]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x107C8, array step: index*0x2000, index2*0x4, valid indices: [0][0-1] */ + __IO uint32_t MBC_DOM3_MEM3_BLK_CFG_W[6]; /**< MBC Memory Block Configuration Word, array offset: 0x107D0, array step: index*0x2000, index2*0x4, valid indices: [0][0-5] */ + uint8_t RESERVED_26[8]; + __IO uint32_t MBC_DOM3_MEM3_BLK_NSE_W[2]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x107F0, array step: index*0x2000, index2*0x4, valid indices: [0][0-1] */ + uint8_t RESERVED_27[72]; + __IO uint32_t MBC_DOM4_MEM0_BLK_CFG_W[7]; /**< MBC Memory Block Configuration Word, array offset: 0x10840, array step: index*0x2000, index2*0x4, valid indices: [0][0-6], [1][0], [2][0], [3][0-2] */ + uint8_t RESERVED_28[228]; + __IO uint32_t MBC_DOM4_MEM0_BLK_NSE_W[2]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x10940, array step: index*0x2000, index2*0x4, valid indices: [0-3][0], [0][1] */ + uint8_t RESERVED_29[56]; + __IO uint32_t MBC_DOM4_MEM1_BLK_CFG_W[3]; /**< MBC Memory Block Configuration Word, array offset: 0x10980, array step: index*0x2000, index2*0x4, valid indices: [0-3][0], [0, 3][1], [3][2] */ + uint8_t RESERVED_30[20]; + __IO uint32_t MBC_DOM4_MEM1_BLK_NSE_W[1]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x109A0, array step: index*0x2000, index2*0x4 */ + uint8_t RESERVED_31[4]; + __IO uint32_t MBC_DOM4_MEM2_BLK_CFG_W[5]; /**< MBC Memory Block Configuration Word, array offset: 0x109A8, array step: index*0x2000, index2*0x4, valid indices: [0][0-4] */ + uint8_t RESERVED_32[12]; + __IO uint32_t MBC_DOM4_MEM2_BLK_NSE_W[2]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x109C8, array step: index*0x2000, index2*0x4, valid indices: [0][0-1] */ + __IO uint32_t MBC_DOM4_MEM3_BLK_CFG_W[6]; /**< MBC Memory Block Configuration Word, array offset: 0x109D0, array step: index*0x2000, index2*0x4, valid indices: [0][0-5] */ + uint8_t RESERVED_33[8]; + __IO uint32_t MBC_DOM4_MEM3_BLK_NSE_W[2]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x109F0, array step: index*0x2000, index2*0x4, valid indices: [0][0-1] */ + uint8_t RESERVED_34[72]; + __IO uint32_t MBC_DOM5_MEM0_BLK_CFG_W[7]; /**< MBC Memory Block Configuration Word, array offset: 0x10A40, array step: index*0x2000, index2*0x4, valid indices: [0][0-6], [1][0], [2][0], [3][0-2] */ + uint8_t RESERVED_35[228]; + __IO uint32_t MBC_DOM5_MEM0_BLK_NSE_W[2]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x10B40, array step: index*0x2000, index2*0x4, valid indices: [0-3][0], [0][1] */ + uint8_t RESERVED_36[56]; + __IO uint32_t MBC_DOM5_MEM1_BLK_CFG_W[3]; /**< MBC Memory Block Configuration Word, array offset: 0x10B80, array step: index*0x2000, index2*0x4, valid indices: [0-3][0], [0, 3][1], [3][2] */ + uint8_t RESERVED_37[20]; + __IO uint32_t MBC_DOM5_MEM1_BLK_NSE_W[1]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x10BA0, array step: index*0x2000, index2*0x4 */ + uint8_t RESERVED_38[4]; + __IO uint32_t MBC_DOM5_MEM2_BLK_CFG_W[5]; /**< MBC Memory Block Configuration Word, array offset: 0x10BA8, array step: index*0x2000, index2*0x4, valid indices: [0][0-4] */ + uint8_t RESERVED_39[12]; + __IO uint32_t MBC_DOM5_MEM2_BLK_NSE_W[2]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x10BC8, array step: index*0x2000, index2*0x4, valid indices: [0][0-1] */ + __IO uint32_t MBC_DOM5_MEM3_BLK_CFG_W[6]; /**< MBC Memory Block Configuration Word, array offset: 0x10BD0, array step: index*0x2000, index2*0x4, valid indices: [0][0-5] */ + uint8_t RESERVED_40[8]; + __IO uint32_t MBC_DOM5_MEM3_BLK_NSE_W[2]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x10BF0, array step: index*0x2000, index2*0x4, valid indices: [0][0-1] */ + uint8_t RESERVED_41[72]; + __IO uint32_t MBC_DOM6_MEM0_BLK_CFG_W[7]; /**< MBC Memory Block Configuration Word, array offset: 0x10C40, array step: index*0x2000, index2*0x4, valid indices: [0][0-6], [1][0], [2][0], [3][0-2] */ + uint8_t RESERVED_42[228]; + __IO uint32_t MBC_DOM6_MEM0_BLK_NSE_W[2]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x10D40, array step: index*0x2000, index2*0x4, valid indices: [0-3][0], [0][1] */ + uint8_t RESERVED_43[56]; + __IO uint32_t MBC_DOM6_MEM1_BLK_CFG_W[3]; /**< MBC Memory Block Configuration Word, array offset: 0x10D80, array step: index*0x2000, index2*0x4, valid indices: [0-3][0], [0, 3][1], [3][2] */ + uint8_t RESERVED_44[20]; + __IO uint32_t MBC_DOM6_MEM1_BLK_NSE_W[1]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x10DA0, array step: index*0x2000, index2*0x4 */ + uint8_t RESERVED_45[4]; + __IO uint32_t MBC_DOM6_MEM2_BLK_CFG_W[5]; /**< MBC Memory Block Configuration Word, array offset: 0x10DA8, array step: index*0x2000, index2*0x4, valid indices: [0][0-4] */ + uint8_t RESERVED_46[12]; + __IO uint32_t MBC_DOM6_MEM2_BLK_NSE_W[2]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x10DC8, array step: index*0x2000, index2*0x4, valid indices: [0][0-1] */ + __IO uint32_t MBC_DOM6_MEM3_BLK_CFG_W[6]; /**< MBC Memory Block Configuration Word, array offset: 0x10DD0, array step: index*0x2000, index2*0x4, valid indices: [0][0-5] */ + uint8_t RESERVED_47[8]; + __IO uint32_t MBC_DOM6_MEM3_BLK_NSE_W[2]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x10DF0, array step: index*0x2000, index2*0x4, valid indices: [0][0-1] */ + uint8_t RESERVED_48[72]; + __IO uint32_t MBC_DOM7_MEM0_BLK_CFG_W[7]; /**< MBC Memory Block Configuration Word, array offset: 0x10E40, array step: index*0x2000, index2*0x4, valid indices: [0][0-6], [1][0], [2][0], [3][0-2] */ + uint8_t RESERVED_49[228]; + __IO uint32_t MBC_DOM7_MEM0_BLK_NSE_W[2]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x10F40, array step: index*0x2000, index2*0x4, valid indices: [0-3][0], [0][1] */ + uint8_t RESERVED_50[56]; + __IO uint32_t MBC_DOM7_MEM1_BLK_CFG_W[3]; /**< MBC Memory Block Configuration Word, array offset: 0x10F80, array step: index*0x2000, index2*0x4, valid indices: [0-3][0], [0, 3][1], [3][2] */ + uint8_t RESERVED_51[20]; + __IO uint32_t MBC_DOM7_MEM1_BLK_NSE_W[1]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x10FA0, array step: index*0x2000, index2*0x4 */ + uint8_t RESERVED_52[4]; + __IO uint32_t MBC_DOM7_MEM2_BLK_CFG_W[5]; /**< MBC Memory Block Configuration Word, array offset: 0x10FA8, array step: index*0x2000, index2*0x4, valid indices: [0][0-4] */ + uint8_t RESERVED_53[12]; + __IO uint32_t MBC_DOM7_MEM2_BLK_NSE_W[2]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x10FC8, array step: index*0x2000, index2*0x4, valid indices: [0][0-1] */ + __IO uint32_t MBC_DOM7_MEM3_BLK_CFG_W[6]; /**< MBC Memory Block Configuration Word, array offset: 0x10FD0, array step: index*0x2000, index2*0x4, valid indices: [0][0-5] */ + uint8_t RESERVED_54[8]; + __IO uint32_t MBC_DOM7_MEM3_BLK_NSE_W[2]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x10FF0, array step: index*0x2000, index2*0x4, valid indices: [0][0-1] */ + uint8_t RESERVED_55[72]; + __IO uint32_t MBC_DOM8_MEM0_BLK_CFG_W[7]; /**< MBC Memory Block Configuration Word, array offset: 0x11040, array step: index*0x2000, index2*0x4, valid indices: [0][0-6], [1][0], [2][0], [3][0-2] */ + uint8_t RESERVED_56[228]; + __IO uint32_t MBC_DOM8_MEM0_BLK_NSE_W[2]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x11140, array step: index*0x2000, index2*0x4, valid indices: [0-3][0], [0][1] */ + uint8_t RESERVED_57[56]; + __IO uint32_t MBC_DOM8_MEM1_BLK_CFG_W[3]; /**< MBC Memory Block Configuration Word, array offset: 0x11180, array step: index*0x2000, index2*0x4, valid indices: [0-3][0], [0, 3][1], [3][2] */ + uint8_t RESERVED_58[20]; + __IO uint32_t MBC_DOM8_MEM1_BLK_NSE_W[1]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x111A0, array step: index*0x2000, index2*0x4 */ + uint8_t RESERVED_59[4]; + __IO uint32_t MBC_DOM8_MEM2_BLK_CFG_W[5]; /**< MBC Memory Block Configuration Word, array offset: 0x111A8, array step: index*0x2000, index2*0x4, valid indices: [0][0-4] */ + uint8_t RESERVED_60[12]; + __IO uint32_t MBC_DOM8_MEM2_BLK_NSE_W[2]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x111C8, array step: index*0x2000, index2*0x4, valid indices: [0][0-1] */ + __IO uint32_t MBC_DOM8_MEM3_BLK_CFG_W[6]; /**< MBC Memory Block Configuration Word, array offset: 0x111D0, array step: index*0x2000, index2*0x4, valid indices: [0][0-5] */ + uint8_t RESERVED_61[8]; + __IO uint32_t MBC_DOM8_MEM3_BLK_NSE_W[2]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x111F0, array step: index*0x2000, index2*0x4, valid indices: [0][0-1] */ + uint8_t RESERVED_62[72]; + __IO uint32_t MBC_DOM9_MEM0_BLK_CFG_W[7]; /**< MBC Memory Block Configuration Word, array offset: 0x11240, array step: index*0x2000, index2*0x4, valid indices: [0][0-6], [1][0], [2][0], [3][0-2] */ + uint8_t RESERVED_63[228]; + __IO uint32_t MBC_DOM9_MEM0_BLK_NSE_W[2]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x11340, array step: index*0x2000, index2*0x4, valid indices: [0-3][0], [0][1] */ + uint8_t RESERVED_64[56]; + __IO uint32_t MBC_DOM9_MEM1_BLK_CFG_W[3]; /**< MBC Memory Block Configuration Word, array offset: 0x11380, array step: index*0x2000, index2*0x4, valid indices: [0-3][0], [0, 3][1], [3][2] */ + uint8_t RESERVED_65[20]; + __IO uint32_t MBC_DOM9_MEM1_BLK_NSE_W[1]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x113A0, array step: index*0x2000, index2*0x4 */ + uint8_t RESERVED_66[4]; + __IO uint32_t MBC_DOM9_MEM2_BLK_CFG_W[5]; /**< MBC Memory Block Configuration Word, array offset: 0x113A8, array step: index*0x2000, index2*0x4, valid indices: [0][0-4] */ + uint8_t RESERVED_67[12]; + __IO uint32_t MBC_DOM9_MEM2_BLK_NSE_W[2]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x113C8, array step: index*0x2000, index2*0x4, valid indices: [0][0-1] */ + __IO uint32_t MBC_DOM9_MEM3_BLK_CFG_W[6]; /**< MBC Memory Block Configuration Word, array offset: 0x113D0, array step: index*0x2000, index2*0x4, valid indices: [0][0-5] */ + uint8_t RESERVED_68[8]; + __IO uint32_t MBC_DOM9_MEM3_BLK_NSE_W[2]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x113F0, array step: index*0x2000, index2*0x4, valid indices: [0][0-1] */ + uint8_t RESERVED_69[72]; + __IO uint32_t MBC_DOM10_MEM0_BLK_CFG_W[7]; /**< MBC Memory Block Configuration Word, array offset: 0x11440, array step: index*0x2000, index2*0x4, valid indices: [0][0-6], [1][0], [2][0], [3][0-2] */ + uint8_t RESERVED_70[228]; + __IO uint32_t MBC_DOM10_MEM0_BLK_NSE_W[2]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x11540, array step: index*0x2000, index2*0x4, valid indices: [0-3][0], [0][1] */ + uint8_t RESERVED_71[56]; + __IO uint32_t MBC_DOM10_MEM1_BLK_CFG_W[3]; /**< MBC Memory Block Configuration Word, array offset: 0x11580, array step: index*0x2000, index2*0x4, valid indices: [0-3][0], [0, 3][1], [3][2] */ + uint8_t RESERVED_72[20]; + __IO uint32_t MBC_DOM10_MEM1_BLK_NSE_W[1]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x115A0, array step: index*0x2000, index2*0x4 */ + uint8_t RESERVED_73[4]; + __IO uint32_t MBC_DOM10_MEM2_BLK_CFG_W[5]; /**< MBC Memory Block Configuration Word, array offset: 0x115A8, array step: index*0x2000, index2*0x4, valid indices: [0][0-4] */ + uint8_t RESERVED_74[12]; + __IO uint32_t MBC_DOM10_MEM2_BLK_NSE_W[2]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x115C8, array step: index*0x2000, index2*0x4, valid indices: [0][0-1] */ + __IO uint32_t MBC_DOM10_MEM3_BLK_CFG_W[6]; /**< MBC Memory Block Configuration Word, array offset: 0x115D0, array step: index*0x2000, index2*0x4, valid indices: [0][0-5] */ + uint8_t RESERVED_75[8]; + __IO uint32_t MBC_DOM10_MEM3_BLK_NSE_W[2]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x115F0, array step: index*0x2000, index2*0x4, valid indices: [0][0-1] */ + uint8_t RESERVED_76[72]; + __IO uint32_t MBC_DOM11_MEM0_BLK_CFG_W[7]; /**< MBC Memory Block Configuration Word, array offset: 0x11640, array step: index*0x2000, index2*0x4, valid indices: [0][0-6], [1][0], [2][0], [3][0-2] */ + uint8_t RESERVED_77[228]; + __IO uint32_t MBC_DOM11_MEM0_BLK_NSE_W[2]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x11740, array step: index*0x2000, index2*0x4, valid indices: [0-3][0], [0][1] */ + uint8_t RESERVED_78[56]; + __IO uint32_t MBC_DOM11_MEM1_BLK_CFG_W[3]; /**< MBC Memory Block Configuration Word, array offset: 0x11780, array step: index*0x2000, index2*0x4, valid indices: [0-3][0], [0, 3][1], [3][2] */ + uint8_t RESERVED_79[20]; + __IO uint32_t MBC_DOM11_MEM1_BLK_NSE_W[1]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x117A0, array step: index*0x2000, index2*0x4 */ + uint8_t RESERVED_80[4]; + __IO uint32_t MBC_DOM11_MEM2_BLK_CFG_W[5]; /**< MBC Memory Block Configuration Word, array offset: 0x117A8, array step: index*0x2000, index2*0x4, valid indices: [0][0-4] */ + uint8_t RESERVED_81[12]; + __IO uint32_t MBC_DOM11_MEM2_BLK_NSE_W[2]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x117C8, array step: index*0x2000, index2*0x4, valid indices: [0][0-1] */ + __IO uint32_t MBC_DOM11_MEM3_BLK_CFG_W[6]; /**< MBC Memory Block Configuration Word, array offset: 0x117D0, array step: index*0x2000, index2*0x4, valid indices: [0][0-5] */ + uint8_t RESERVED_82[8]; + __IO uint32_t MBC_DOM11_MEM3_BLK_NSE_W[2]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x117F0, array step: index*0x2000, index2*0x4, valid indices: [0][0-1] */ + uint8_t RESERVED_83[72]; + __IO uint32_t MBC_DOM12_MEM0_BLK_CFG_W[7]; /**< MBC Memory Block Configuration Word, array offset: 0x11840, array step: index*0x2000, index2*0x4, valid indices: [0][0-6], [1][0], [2][0], [3][0-2] */ + uint8_t RESERVED_84[228]; + __IO uint32_t MBC_DOM12_MEM0_BLK_NSE_W[2]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x11940, array step: index*0x2000, index2*0x4, valid indices: [0-3][0], [0][1] */ + uint8_t RESERVED_85[56]; + __IO uint32_t MBC_DOM12_MEM1_BLK_CFG_W[3]; /**< MBC Memory Block Configuration Word, array offset: 0x11980, array step: index*0x2000, index2*0x4, valid indices: [0-3][0], [0, 3][1], [3][2] */ + uint8_t RESERVED_86[20]; + __IO uint32_t MBC_DOM12_MEM1_BLK_NSE_W[1]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x119A0, array step: index*0x2000, index2*0x4 */ + uint8_t RESERVED_87[4]; + __IO uint32_t MBC_DOM12_MEM2_BLK_CFG_W[5]; /**< MBC Memory Block Configuration Word, array offset: 0x119A8, array step: index*0x2000, index2*0x4, valid indices: [0][0-4] */ + uint8_t RESERVED_88[12]; + __IO uint32_t MBC_DOM12_MEM2_BLK_NSE_W[2]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x119C8, array step: index*0x2000, index2*0x4, valid indices: [0][0-1] */ + __IO uint32_t MBC_DOM12_MEM3_BLK_CFG_W[6]; /**< MBC Memory Block Configuration Word, array offset: 0x119D0, array step: index*0x2000, index2*0x4, valid indices: [0][0-5] */ + uint8_t RESERVED_89[8]; + __IO uint32_t MBC_DOM12_MEM3_BLK_NSE_W[2]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x119F0, array step: index*0x2000, index2*0x4, valid indices: [0][0-1] */ + uint8_t RESERVED_90[72]; + __IO uint32_t MBC_DOM13_MEM0_BLK_CFG_W[7]; /**< MBC Memory Block Configuration Word, array offset: 0x11A40, array step: index*0x2000, index2*0x4, valid indices: [0][0-6], [1][0], [2][0], [3][0-2] */ + uint8_t RESERVED_91[228]; + __IO uint32_t MBC_DOM13_MEM0_BLK_NSE_W[2]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x11B40, array step: index*0x2000, index2*0x4, valid indices: [0-3][0], [0][1] */ + uint8_t RESERVED_92[56]; + __IO uint32_t MBC_DOM13_MEM1_BLK_CFG_W[3]; /**< MBC Memory Block Configuration Word, array offset: 0x11B80, array step: index*0x2000, index2*0x4, valid indices: [0-3][0], [0, 3][1], [3][2] */ + uint8_t RESERVED_93[20]; + __IO uint32_t MBC_DOM13_MEM1_BLK_NSE_W[1]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x11BA0, array step: index*0x2000, index2*0x4 */ + uint8_t RESERVED_94[4]; + __IO uint32_t MBC_DOM13_MEM2_BLK_CFG_W[5]; /**< MBC Memory Block Configuration Word, array offset: 0x11BA8, array step: index*0x2000, index2*0x4, valid indices: [0][0-4] */ + uint8_t RESERVED_95[12]; + __IO uint32_t MBC_DOM13_MEM2_BLK_NSE_W[2]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x11BC8, array step: index*0x2000, index2*0x4, valid indices: [0][0-1] */ + __IO uint32_t MBC_DOM13_MEM3_BLK_CFG_W[6]; /**< MBC Memory Block Configuration Word, array offset: 0x11BD0, array step: index*0x2000, index2*0x4, valid indices: [0][0-5] */ + uint8_t RESERVED_96[8]; + __IO uint32_t MBC_DOM13_MEM3_BLK_NSE_W[2]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x11BF0, array step: index*0x2000, index2*0x4, valid indices: [0][0-1] */ + uint8_t RESERVED_97[72]; + __IO uint32_t MBC_DOM14_MEM0_BLK_CFG_W[7]; /**< MBC Memory Block Configuration Word, array offset: 0x11C40, array step: index*0x2000, index2*0x4, valid indices: [0][0-6], [1][0], [2][0], [3][0-2] */ + uint8_t RESERVED_98[228]; + __IO uint32_t MBC_DOM14_MEM0_BLK_NSE_W[2]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x11D40, array step: index*0x2000, index2*0x4, valid indices: [0-3][0], [0][1] */ + uint8_t RESERVED_99[56]; + __IO uint32_t MBC_DOM14_MEM1_BLK_CFG_W[3]; /**< MBC Memory Block Configuration Word, array offset: 0x11D80, array step: index*0x2000, index2*0x4, valid indices: [0-3][0], [0, 3][1], [3][2] */ + uint8_t RESERVED_100[20]; + __IO uint32_t MBC_DOM14_MEM1_BLK_NSE_W[1]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x11DA0, array step: index*0x2000, index2*0x4 */ + uint8_t RESERVED_101[4]; + __IO uint32_t MBC_DOM14_MEM2_BLK_CFG_W[5]; /**< MBC Memory Block Configuration Word, array offset: 0x11DA8, array step: index*0x2000, index2*0x4, valid indices: [0][0-4] */ + uint8_t RESERVED_102[12]; + __IO uint32_t MBC_DOM14_MEM2_BLK_NSE_W[2]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x11DC8, array step: index*0x2000, index2*0x4, valid indices: [0][0-1] */ + __IO uint32_t MBC_DOM14_MEM3_BLK_CFG_W[6]; /**< MBC Memory Block Configuration Word, array offset: 0x11DD0, array step: index*0x2000, index2*0x4, valid indices: [0][0-5] */ + uint8_t RESERVED_103[8]; + __IO uint32_t MBC_DOM14_MEM3_BLK_NSE_W[2]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x11DF0, array step: index*0x2000, index2*0x4, valid indices: [0][0-1] */ + uint8_t RESERVED_104[72]; + __IO uint32_t MBC_DOM15_MEM0_BLK_CFG_W[7]; /**< MBC Memory Block Configuration Word, array offset: 0x11E40, array step: index*0x2000, index2*0x4, valid indices: [0][0-6], [1][0], [2][0], [3][0-2] */ + uint8_t RESERVED_105[228]; + __IO uint32_t MBC_DOM15_MEM0_BLK_NSE_W[2]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x11F40, array step: index*0x2000, index2*0x4, valid indices: [0-3][0], [0][1] */ + uint8_t RESERVED_106[56]; + __IO uint32_t MBC_DOM15_MEM1_BLK_CFG_W[3]; /**< MBC Memory Block Configuration Word, array offset: 0x11F80, array step: index*0x2000, index2*0x4, valid indices: [0-3][0], [0, 3][1], [3][2] */ + uint8_t RESERVED_107[20]; + __IO uint32_t MBC_DOM15_MEM1_BLK_NSE_W[1]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x11FA0, array step: index*0x2000, index2*0x4 */ + uint8_t RESERVED_108[4]; + __IO uint32_t MBC_DOM15_MEM2_BLK_CFG_W[5]; /**< MBC Memory Block Configuration Word, array offset: 0x11FA8, array step: index*0x2000, index2*0x4, valid indices: [0][0-4] */ + uint8_t RESERVED_109[12]; + __IO uint32_t MBC_DOM15_MEM2_BLK_NSE_W[2]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x11FC8, array step: index*0x2000, index2*0x4, valid indices: [0][0-1] */ + __IO uint32_t MBC_DOM15_MEM3_BLK_CFG_W[6]; /**< MBC Memory Block Configuration Word, array offset: 0x11FD0, array step: index*0x2000, index2*0x4, valid indices: [0][0-5] */ + uint8_t RESERVED_110[8]; + __IO uint32_t MBC_DOM15_MEM3_BLK_NSE_W[2]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x11FF0, array step: index*0x2000, index2*0x4, valid indices: [0][0-1] */ + uint8_t RESERVED_111[8]; + } MBC_INDEX[4]; + struct { /* offset: 0x18000, array step: 0xFC4 */ + __I uint32_t MRC_GLBCFG; /**< MRC Global Configuration Register, array offset: 0x18000, array step: 0xFC4 */ + uint8_t RESERVED_0[12]; + __IO uint32_t MRC_NSE_RGN_INDIRECT; /**< MRC NonSecure Enable Region Indirect, array offset: 0x18010, array step: 0xFC4 */ + __IO uint32_t MRC_NSE_RGN_SET; /**< MRC NonSecure Enable Region Set, array offset: 0x18014, array step: 0xFC4 */ + __IO uint32_t MRC_NSE_RGN_CLR; /**< MRC NonSecure Enable Region Clear, array offset: 0x18018, array step: 0xFC4 */ + __IO uint32_t MRC_NSE_RGN_CLR_ALL; /**< MRC NonSecure Enable Region Clear All, array offset: 0x1801C, array step: 0xFC4 */ + __IO uint32_t MRC_GLBAC[8]; /**< MRC Global Access Control, array offset: 0x18020, array step: index*0xFC4, index2*0x4 */ + __IO uint32_t MRC_DOM0_RGD_W[16][2]; /**< MRC Region Descriptor Word 0..MRC Region Descriptor Word 1, array offset: 0x18040, array step: index*0xFC4, index2*0x8, index3*0x4 */ + __IO uint32_t MRC_DOM0_RGD_NSE; /**< MRC Region Descriptor NonSecure Enable, array offset: 0x180C0, array step: 0xFC4 */ + uint8_t RESERVED_1[124]; + __IO uint32_t MRC_DOM1_RGD_W[16][2]; /**< MRC Region Descriptor Word 0..MRC Region Descriptor Word 1, array offset: 0x18140, array step: index*0xFC4, index2*0x8, index3*0x4 */ + __IO uint32_t MRC_DOM1_RGD_NSE; /**< MRC Region Descriptor NonSecure Enable, array offset: 0x181C0, array step: 0xFC4 */ + uint8_t RESERVED_2[124]; + __IO uint32_t MRC_DOM2_RGD_W[16][2]; /**< MRC Region Descriptor Word 0..MRC Region Descriptor Word 1, array offset: 0x18240, array step: index*0xFC4, index2*0x8, index3*0x4 */ + __IO uint32_t MRC_DOM2_RGD_NSE; /**< MRC Region Descriptor NonSecure Enable, array offset: 0x182C0, array step: 0xFC4 */ + uint8_t RESERVED_3[124]; + __IO uint32_t MRC_DOM3_RGD_W[16][2]; /**< MRC Region Descriptor Word 0..MRC Region Descriptor Word 1, array offset: 0x18340, array step: index*0xFC4, index2*0x8, index3*0x4 */ + __IO uint32_t MRC_DOM3_RGD_NSE; /**< MRC Region Descriptor NonSecure Enable, array offset: 0x183C0, array step: 0xFC4 */ + uint8_t RESERVED_4[124]; + __IO uint32_t MRC_DOM4_RGD_W[16][2]; /**< MRC Region Descriptor Word 0..MRC Region Descriptor Word 1, array offset: 0x18440, array step: index*0xFC4, index2*0x8, index3*0x4 */ + __IO uint32_t MRC_DOM4_RGD_NSE; /**< MRC Region Descriptor NonSecure Enable, array offset: 0x184C0, array step: 0xFC4 */ + uint8_t RESERVED_5[124]; + __IO uint32_t MRC_DOM5_RGD_W[16][2]; /**< MRC Region Descriptor Word 0..MRC Region Descriptor Word 1, array offset: 0x18540, array step: index*0xFC4, index2*0x8, index3*0x4 */ + __IO uint32_t MRC_DOM5_RGD_NSE; /**< MRC Region Descriptor NonSecure Enable, array offset: 0x185C0, array step: 0xFC4 */ + uint8_t RESERVED_6[124]; + __IO uint32_t MRC_DOM6_RGD_W[16][2]; /**< MRC Region Descriptor Word 0..MRC Region Descriptor Word 1, array offset: 0x18640, array step: index*0xFC4, index2*0x8, index3*0x4 */ + __IO uint32_t MRC_DOM6_RGD_NSE; /**< MRC Region Descriptor NonSecure Enable, array offset: 0x186C0, array step: 0xFC4 */ + uint8_t RESERVED_7[124]; + __IO uint32_t MRC_DOM7_RGD_W[16][2]; /**< MRC Region Descriptor Word 0..MRC Region Descriptor Word 1, array offset: 0x18740, array step: index*0xFC4, index2*0x8, index3*0x4 */ + __IO uint32_t MRC_DOM7_RGD_NSE; /**< MRC Region Descriptor NonSecure Enable, array offset: 0x187C0, array step: 0xFC4 */ + uint8_t RESERVED_8[124]; + __IO uint32_t MRC_DOM8_RGD_W[16][2]; /**< MRC Region Descriptor Word 0..MRC Region Descriptor Word 1, array offset: 0x18840, array step: index*0xFC4, index2*0x8, index3*0x4 */ + __IO uint32_t MRC_DOM8_RGD_NSE; /**< MRC Region Descriptor NonSecure Enable, array offset: 0x188C0, array step: 0xFC4 */ + uint8_t RESERVED_9[124]; + __IO uint32_t MRC_DOM9_RGD_W[16][2]; /**< MRC Region Descriptor Word 0..MRC Region Descriptor Word 1, array offset: 0x18940, array step: index*0xFC4, index2*0x8, index3*0x4 */ + __IO uint32_t MRC_DOM9_RGD_NSE; /**< MRC Region Descriptor NonSecure Enable, array offset: 0x189C0, array step: 0xFC4 */ + uint8_t RESERVED_10[124]; + __IO uint32_t MRC_DOM10_RGD_W[16][2]; /**< MRC Region Descriptor Word 0..MRC Region Descriptor Word 1, array offset: 0x18A40, array step: index*0xFC4, index2*0x8, index3*0x4 */ + __IO uint32_t MRC_DOM10_RGD_NSE; /**< MRC Region Descriptor NonSecure Enable, array offset: 0x18AC0, array step: 0xFC4 */ + uint8_t RESERVED_11[124]; + __IO uint32_t MRC_DOM11_RGD_W[16][2]; /**< MRC Region Descriptor Word 0..MRC Region Descriptor Word 1, array offset: 0x18B40, array step: index*0xFC4, index2*0x8, index3*0x4 */ + __IO uint32_t MRC_DOM11_RGD_NSE; /**< MRC Region Descriptor NonSecure Enable, array offset: 0x18BC0, array step: 0xFC4 */ + uint8_t RESERVED_12[124]; + __IO uint32_t MRC_DOM12_RGD_W[16][2]; /**< MRC Region Descriptor Word 0..MRC Region Descriptor Word 1, array offset: 0x18C40, array step: index*0xFC4, index2*0x8, index3*0x4 */ + __IO uint32_t MRC_DOM12_RGD_NSE; /**< MRC Region Descriptor NonSecure Enable, array offset: 0x18CC0, array step: 0xFC4 */ + uint8_t RESERVED_13[124]; + __IO uint32_t MRC_DOM13_RGD_W[16][2]; /**< MRC Region Descriptor Word 0..MRC Region Descriptor Word 1, array offset: 0x18D40, array step: index*0xFC4, index2*0x8, index3*0x4 */ + __IO uint32_t MRC_DOM13_RGD_NSE; /**< MRC Region Descriptor NonSecure Enable, array offset: 0x18DC0, array step: 0xFC4 */ + uint8_t RESERVED_14[124]; + __IO uint32_t MRC_DOM14_RGD_W[16][2]; /**< MRC Region Descriptor Word 0..MRC Region Descriptor Word 1, array offset: 0x18E40, array step: index*0xFC4, index2*0x8, index3*0x4 */ + __IO uint32_t MRC_DOM14_RGD_NSE; /**< MRC Region Descriptor NonSecure Enable, array offset: 0x18EC0, array step: 0xFC4 */ + uint8_t RESERVED_15[124]; + __IO uint32_t MRC_DOM15_RGD_W[16][2]; /**< MRC Region Descriptor Word 0..MRC Region Descriptor Word 1, array offset: 0x18F40, array step: index*0xFC4, index2*0x8, index3*0x4 */ + __IO uint32_t MRC_DOM15_RGD_NSE; /**< MRC Region Descriptor NonSecure Enable, array offset: 0x18FC0, array step: 0xFC4 */ + } MRC_INDEX[1]; +} TRDC_MBC4_Type; + +/* ---------------------------------------------------------------------------- + -- TRDC_MBC4 Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup TRDC_MBC4_Register_Masks TRDC_MBC4 Register Masks + * @{ + */ + +/*! @name TRDC_CR - TRDC Register */ +/*! @{ */ + +#define TRDC_MBC4_TRDC_CR_GVLDM_MASK (0x1U) +#define TRDC_MBC4_TRDC_CR_GVLDM_SHIFT (0U) +/*! GVLDM - Global Valid for Domain Assignment Controllers + * 0b0..TRDC DACs are disabled. + * 0b1..TRDC DACs are enabled. + */ +#define TRDC_MBC4_TRDC_CR_GVLDM(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_TRDC_CR_GVLDM_SHIFT)) & TRDC_MBC4_TRDC_CR_GVLDM_MASK) + +#define TRDC_MBC4_TRDC_CR_HRL_MASK (0x1EU) +#define TRDC_MBC4_TRDC_CR_HRL_SHIFT (1U) +/*! HRL - Hardware Revision Level */ +#define TRDC_MBC4_TRDC_CR_HRL(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_TRDC_CR_HRL_SHIFT)) & TRDC_MBC4_TRDC_CR_HRL_MASK) + +#define TRDC_MBC4_TRDC_CR_GVLDB_MASK (0x4000U) +#define TRDC_MBC4_TRDC_CR_GVLDB_SHIFT (14U) +/*! GVLDB - Global Valid for Memory Block Checkers + * 0b0..TRDC MBCs are disabled. + * 0b1..TRDC MBCs are enabled. + */ +#define TRDC_MBC4_TRDC_CR_GVLDB(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_TRDC_CR_GVLDB_SHIFT)) & TRDC_MBC4_TRDC_CR_GVLDB_MASK) + +#define TRDC_MBC4_TRDC_CR_GVLDR_MASK (0x8000U) +#define TRDC_MBC4_TRDC_CR_GVLDR_SHIFT (15U) +/*! GVLDR - Global Valid for Memory Region Checkers + * 0b0..TRDC MRCs are disabled. + * 0b1..TRDC MRCs are enabled. + */ +#define TRDC_MBC4_TRDC_CR_GVLDR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_TRDC_CR_GVLDR_SHIFT)) & TRDC_MBC4_TRDC_CR_GVLDR_MASK) + +#define TRDC_MBC4_TRDC_CR_LK1_MASK (0x40000000U) +#define TRDC_MBC4_TRDC_CR_LK1_SHIFT (30U) +/*! LK1 - Lock Status + * 0b0..The CR can be written by any secure privileged write. + * 0b1..The CR is locked (read-only) until the next reset. + */ +#define TRDC_MBC4_TRDC_CR_LK1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_TRDC_CR_LK1_SHIFT)) & TRDC_MBC4_TRDC_CR_LK1_MASK) +/*! @} */ + +/*! @name TRDC_HWCFG0 - TRDC Hardware Configuration Register 0 */ +/*! @{ */ + +#define TRDC_MBC4_TRDC_HWCFG0_NDID_MASK (0x1FU) +#define TRDC_MBC4_TRDC_HWCFG0_NDID_SHIFT (0U) +/*! NDID - Number of domains */ +#define TRDC_MBC4_TRDC_HWCFG0_NDID(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_TRDC_HWCFG0_NDID_SHIFT)) & TRDC_MBC4_TRDC_HWCFG0_NDID_MASK) + +#define TRDC_MBC4_TRDC_HWCFG0_NMSTR_MASK (0xFF00U) +#define TRDC_MBC4_TRDC_HWCFG0_NMSTR_SHIFT (8U) +/*! NMSTR - Number of bus masters */ +#define TRDC_MBC4_TRDC_HWCFG0_NMSTR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_TRDC_HWCFG0_NMSTR_SHIFT)) & TRDC_MBC4_TRDC_HWCFG0_NMSTR_MASK) + +#define TRDC_MBC4_TRDC_HWCFG0_NMBC_MASK (0xF0000U) +#define TRDC_MBC4_TRDC_HWCFG0_NMBC_SHIFT (16U) +/*! NMBC - Number of MBCs */ +#define TRDC_MBC4_TRDC_HWCFG0_NMBC(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_TRDC_HWCFG0_NMBC_SHIFT)) & TRDC_MBC4_TRDC_HWCFG0_NMBC_MASK) + +#define TRDC_MBC4_TRDC_HWCFG0_NMRC_MASK (0x1F000000U) +#define TRDC_MBC4_TRDC_HWCFG0_NMRC_SHIFT (24U) +/*! NMRC - Number of MRCs */ +#define TRDC_MBC4_TRDC_HWCFG0_NMRC(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_TRDC_HWCFG0_NMRC_SHIFT)) & TRDC_MBC4_TRDC_HWCFG0_NMRC_MASK) + +#define TRDC_MBC4_TRDC_HWCFG0_MID_MASK (0xE0000000U) +#define TRDC_MBC4_TRDC_HWCFG0_MID_SHIFT (29U) +/*! MID - Module ID */ +#define TRDC_MBC4_TRDC_HWCFG0_MID(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_TRDC_HWCFG0_MID_SHIFT)) & TRDC_MBC4_TRDC_HWCFG0_MID_MASK) +/*! @} */ + +/*! @name TRDC_HWCFG1 - TRDC Hardware Configuration Register 1 */ +/*! @{ */ + +#define TRDC_MBC4_TRDC_HWCFG1_DID_MASK (0xFU) +#define TRDC_MBC4_TRDC_HWCFG1_DID_SHIFT (0U) +/*! DID - Domain identifier number */ +#define TRDC_MBC4_TRDC_HWCFG1_DID(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_TRDC_HWCFG1_DID_SHIFT)) & TRDC_MBC4_TRDC_HWCFG1_DID_MASK) +/*! @} */ + +/*! @name TRDC_HWCFG2 - TRDC Hardware Configuration Register 2 */ +/*! @{ */ + +#define TRDC_MBC4_TRDC_HWCFG2_PIDPn_MASK (0xFFFFFFFFU) +#define TRDC_MBC4_TRDC_HWCFG2_PIDPn_SHIFT (0U) +/*! PIDPn - Process identifier present */ +#define TRDC_MBC4_TRDC_HWCFG2_PIDPn(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_TRDC_HWCFG2_PIDPn_SHIFT)) & TRDC_MBC4_TRDC_HWCFG2_PIDPn_MASK) +/*! @} */ + +/*! @name TRDC_HWCFG3 - TRDC Hardware Configuration Register 3 */ +/*! @{ */ + +#define TRDC_MBC4_TRDC_HWCFG3_PIDPn_MASK (0xFFFFFFFFU) +#define TRDC_MBC4_TRDC_HWCFG3_PIDPn_SHIFT (0U) +/*! PIDPn - Process identifier present */ +#define TRDC_MBC4_TRDC_HWCFG3_PIDPn(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_TRDC_HWCFG3_PIDPn_SHIFT)) & TRDC_MBC4_TRDC_HWCFG3_PIDPn_MASK) +/*! @} */ + +/*! @name DACFG - Domain Assignment Configuration Register */ +/*! @{ */ + +#define TRDC_MBC4_DACFG_NMDAR_MASK (0xFU) +#define TRDC_MBC4_DACFG_NMDAR_SHIFT (0U) +/*! NMDAR - Number of master domain assignment registers for bus master m */ +#define TRDC_MBC4_DACFG_NMDAR(x) (((uint8_t)(((uint8_t)(x)) << TRDC_MBC4_DACFG_NMDAR_SHIFT)) & TRDC_MBC4_DACFG_NMDAR_MASK) + +#define TRDC_MBC4_DACFG_NCM_MASK (0x80U) +#define TRDC_MBC4_DACFG_NCM_SHIFT (7U) +/*! NCM - Non-CPU Master + * 0b0..Bus master is a processor. + * 0b1..Bus master is a non-processor. + */ +#define TRDC_MBC4_DACFG_NCM(x) (((uint8_t)(((uint8_t)(x)) << TRDC_MBC4_DACFG_NCM_SHIFT)) & TRDC_MBC4_DACFG_NCM_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_DACFG */ +#define TRDC_MBC4_DACFG_COUNT (2U) + +/*! @name TRDC_IDAU_CR - TRDC IDAU Control Register */ +/*! @{ */ + +#define TRDC_MBC4_TRDC_IDAU_CR_VLD_MASK (0x1U) +#define TRDC_MBC4_TRDC_IDAU_CR_VLD_SHIFT (0U) +/*! VLD - Valid */ +#define TRDC_MBC4_TRDC_IDAU_CR_VLD(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_TRDC_IDAU_CR_VLD_SHIFT)) & TRDC_MBC4_TRDC_IDAU_CR_VLD_MASK) + +#define TRDC_MBC4_TRDC_IDAU_CR_CFGSECEXT_MASK (0x8U) +#define TRDC_MBC4_TRDC_IDAU_CR_CFGSECEXT_SHIFT (3U) +/*! CFGSECEXT - Configure Security Extension + * 0b0..Armv8M Security Extension is disabled + * 0b1..Armv8-M Security Extension is enabled + */ +#define TRDC_MBC4_TRDC_IDAU_CR_CFGSECEXT(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_TRDC_IDAU_CR_CFGSECEXT_SHIFT)) & TRDC_MBC4_TRDC_IDAU_CR_CFGSECEXT_MASK) + +#define TRDC_MBC4_TRDC_IDAU_CR_MPUSDIS_MASK (0x10U) +#define TRDC_MBC4_TRDC_IDAU_CR_MPUSDIS_SHIFT (4U) +/*! MPUSDIS - Secure Memory Protection Unit Disabled + * 0b0..Secure MPU is enabled + * 0b1..Secure MPU is disabled + */ +#define TRDC_MBC4_TRDC_IDAU_CR_MPUSDIS(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_TRDC_IDAU_CR_MPUSDIS_SHIFT)) & TRDC_MBC4_TRDC_IDAU_CR_MPUSDIS_MASK) + +#define TRDC_MBC4_TRDC_IDAU_CR_MPUNSDIS_MASK (0x20U) +#define TRDC_MBC4_TRDC_IDAU_CR_MPUNSDIS_SHIFT (5U) +/*! MPUNSDIS - NonSecure Memory Protection Unit Disabled + * 0b0..Nonsecure MPU is enabled + * 0b1..Nonsecure MPU is disabled + */ +#define TRDC_MBC4_TRDC_IDAU_CR_MPUNSDIS(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_TRDC_IDAU_CR_MPUNSDIS_SHIFT)) & TRDC_MBC4_TRDC_IDAU_CR_MPUNSDIS_MASK) + +#define TRDC_MBC4_TRDC_IDAU_CR_SAUDIS_MASK (0x40U) +#define TRDC_MBC4_TRDC_IDAU_CR_SAUDIS_SHIFT (6U) +/*! SAUDIS - Security Attribution Unit Disable + * 0b0..SAU is enabled + * 0b1..SAU is disabled + */ +#define TRDC_MBC4_TRDC_IDAU_CR_SAUDIS(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_TRDC_IDAU_CR_SAUDIS_SHIFT)) & TRDC_MBC4_TRDC_IDAU_CR_SAUDIS_MASK) + +#define TRDC_MBC4_TRDC_IDAU_CR_LKSVTAIRCR_MASK (0x100U) +#define TRDC_MBC4_TRDC_IDAU_CR_LKSVTAIRCR_SHIFT (8U) +/*! LKSVTAIRCR - Lock Secure VTOR, Application interrupt and Reset Control Registers + * 0b0..Unlock these registers + * 0b1..Disable writes to the VTOR_S, AIRCR[PRIS], and AIRCR[BFHFNMINS] registers + */ +#define TRDC_MBC4_TRDC_IDAU_CR_LKSVTAIRCR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_TRDC_IDAU_CR_LKSVTAIRCR_SHIFT)) & TRDC_MBC4_TRDC_IDAU_CR_LKSVTAIRCR_MASK) + +#define TRDC_MBC4_TRDC_IDAU_CR_LKNSVTOR_MASK (0x200U) +#define TRDC_MBC4_TRDC_IDAU_CR_LKNSVTOR_SHIFT (9U) +/*! LKNSVTOR - Lock Nonsecure Vector Table Offset Register + * 0b0..Unlock this register + * 0b1..Disable writes to the VTOR_NS register + */ +#define TRDC_MBC4_TRDC_IDAU_CR_LKNSVTOR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_TRDC_IDAU_CR_LKNSVTOR_SHIFT)) & TRDC_MBC4_TRDC_IDAU_CR_LKNSVTOR_MASK) + +#define TRDC_MBC4_TRDC_IDAU_CR_LKSMPU_MASK (0x400U) +#define TRDC_MBC4_TRDC_IDAU_CR_LKSMPU_SHIFT (10U) +/*! LKSMPU - Lock Secure MPU + * 0b0..Unlock these registers + * 0b1..Disable writes to the MPU_CTRL, MPU_RNR, MPU_RBAR, MPU_RLAR, MPU_RBAR_An and MPU_RLAR_An from software or + * from a debug agent connected to the processor in Secure state + */ +#define TRDC_MBC4_TRDC_IDAU_CR_LKSMPU(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_TRDC_IDAU_CR_LKSMPU_SHIFT)) & TRDC_MBC4_TRDC_IDAU_CR_LKSMPU_MASK) + +#define TRDC_MBC4_TRDC_IDAU_CR_LKNSMPU_MASK (0x800U) +#define TRDC_MBC4_TRDC_IDAU_CR_LKNSMPU_SHIFT (11U) +/*! LKNSMPU - Lock Nonsecure MPU + * 0b0..Unlock these registers + * 0b1..Disable writes to the MPU_CTRL_NS, MPU_RNR_NS, MPU_RBAR_NS, MPU_RLAR_NS, MPU_RBAR_A_NSn and + * MPU_RLAR_A_NSn from software or from a debug agent connected to the processor + */ +#define TRDC_MBC4_TRDC_IDAU_CR_LKNSMPU(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_TRDC_IDAU_CR_LKNSMPU_SHIFT)) & TRDC_MBC4_TRDC_IDAU_CR_LKNSMPU_MASK) + +#define TRDC_MBC4_TRDC_IDAU_CR_LKSAU_MASK (0x1000U) +#define TRDC_MBC4_TRDC_IDAU_CR_LKSAU_SHIFT (12U) +/*! LKSAU - Lock SAU + * 0b0..Unlock these registers + * 0b1..Disable writes to the SAU_CTRL, SAU_RNR, SAU_RBAR and SAU_RLAR registers from software or from a debug agent connected to the processor + */ +#define TRDC_MBC4_TRDC_IDAU_CR_LKSAU(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_TRDC_IDAU_CR_LKSAU_SHIFT)) & TRDC_MBC4_TRDC_IDAU_CR_LKSAU_MASK) + +#define TRDC_MBC4_TRDC_IDAU_CR_PCURRNS_MASK (0x80000000U) +#define TRDC_MBC4_TRDC_IDAU_CR_PCURRNS_SHIFT (31U) +/*! PCURRNS - Processor current security + * 0b0..Processor is in Secure state + * 0b1..Processor is in Nonsecure state + */ +#define TRDC_MBC4_TRDC_IDAU_CR_PCURRNS(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_TRDC_IDAU_CR_PCURRNS_SHIFT)) & TRDC_MBC4_TRDC_IDAU_CR_PCURRNS_MASK) +/*! @} */ + +/*! @name TRDC_FLW_CTL - TRDC FLW Control */ +/*! @{ */ + +#define TRDC_MBC4_TRDC_FLW_CTL_LK_MASK (0x40000000U) +#define TRDC_MBC4_TRDC_FLW_CTL_LK_SHIFT (30U) +/*! LK - Lock bit + * 0b0..FLW registers may be modified. + * 0b1..FLW registers are locked until the next reset. + */ +#define TRDC_MBC4_TRDC_FLW_CTL_LK(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_TRDC_FLW_CTL_LK_SHIFT)) & TRDC_MBC4_TRDC_FLW_CTL_LK_MASK) + +#define TRDC_MBC4_TRDC_FLW_CTL_V_MASK (0x80000000U) +#define TRDC_MBC4_TRDC_FLW_CTL_V_SHIFT (31U) +/*! V - Valid bit + * 0b0..FLW function is disabled. + * 0b1..FLW function is enabled. + */ +#define TRDC_MBC4_TRDC_FLW_CTL_V(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_TRDC_FLW_CTL_V_SHIFT)) & TRDC_MBC4_TRDC_FLW_CTL_V_MASK) +/*! @} */ + +/*! @name TRDC_FLW_PBASE - TRDC FLW Physical Base */ +/*! @{ */ + +#define TRDC_MBC4_TRDC_FLW_PBASE_PBASE_MASK (0xFFFFFFFFU) +#define TRDC_MBC4_TRDC_FLW_PBASE_PBASE_SHIFT (0U) +/*! PBASE - Physical base address */ +#define TRDC_MBC4_TRDC_FLW_PBASE_PBASE(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_TRDC_FLW_PBASE_PBASE_SHIFT)) & TRDC_MBC4_TRDC_FLW_PBASE_PBASE_MASK) +/*! @} */ + +/*! @name TRDC_FLW_ABASE - TRDC FLW Array Base */ +/*! @{ */ + +#define TRDC_MBC4_TRDC_FLW_ABASE_ABASE_L_MASK (0x3F8000U) +#define TRDC_MBC4_TRDC_FLW_ABASE_ABASE_L_SHIFT (15U) +/*! ABASE_L - Array base address low */ +#define TRDC_MBC4_TRDC_FLW_ABASE_ABASE_L(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_TRDC_FLW_ABASE_ABASE_L_SHIFT)) & TRDC_MBC4_TRDC_FLW_ABASE_ABASE_L_MASK) + +#define TRDC_MBC4_TRDC_FLW_ABASE_ABASE_H_MASK (0xFFC00000U) +#define TRDC_MBC4_TRDC_FLW_ABASE_ABASE_H_SHIFT (22U) +/*! ABASE_H - Array base address high */ +#define TRDC_MBC4_TRDC_FLW_ABASE_ABASE_H(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_TRDC_FLW_ABASE_ABASE_H_SHIFT)) & TRDC_MBC4_TRDC_FLW_ABASE_ABASE_H_MASK) +/*! @} */ + +/*! @name TRDC_FLW_BCNT - TRDC FLW Block Count */ +/*! @{ */ + +#define TRDC_MBC4_TRDC_FLW_BCNT_BCNT_MASK (0x7FFFU) +#define TRDC_MBC4_TRDC_FLW_BCNT_BCNT_SHIFT (0U) +/*! BCNT - Block Count */ +#define TRDC_MBC4_TRDC_FLW_BCNT_BCNT(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_TRDC_FLW_BCNT_BCNT_SHIFT)) & TRDC_MBC4_TRDC_FLW_BCNT_BCNT_MASK) +/*! @} */ + +/*! @name TRDC_FDID - TRDC Fault Domain ID */ +/*! @{ */ + +#define TRDC_MBC4_TRDC_FDID_FDID_MASK (0xFU) +#define TRDC_MBC4_TRDC_FDID_FDID_SHIFT (0U) +/*! FDID - Domain ID of Faulted Access */ +#define TRDC_MBC4_TRDC_FDID_FDID(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_TRDC_FDID_FDID_SHIFT)) & TRDC_MBC4_TRDC_FDID_FDID_MASK) +/*! @} */ + +/*! @name TRDC_DERRLOC - TRDC Domain Error Location Register */ +/*! @{ */ + +#define TRDC_MBC4_TRDC_DERRLOC_MBCINST_MASK (0xFFU) +#define TRDC_MBC4_TRDC_DERRLOC_MBCINST_SHIFT (0U) +/*! MBCINST - MBC instance */ +#define TRDC_MBC4_TRDC_DERRLOC_MBCINST(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_TRDC_DERRLOC_MBCINST_SHIFT)) & TRDC_MBC4_TRDC_DERRLOC_MBCINST_MASK) + +#define TRDC_MBC4_TRDC_DERRLOC_MRCINST_MASK (0xFFFF0000U) +#define TRDC_MBC4_TRDC_DERRLOC_MRCINST_SHIFT (16U) +/*! MRCINST - MRC instance */ +#define TRDC_MBC4_TRDC_DERRLOC_MRCINST(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_TRDC_DERRLOC_MRCINST_SHIFT)) & TRDC_MBC4_TRDC_DERRLOC_MRCINST_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_TRDC_DERRLOC */ +#define TRDC_MBC4_TRDC_DERRLOC_COUNT (16U) + +/*! @name W0 - MBC Domain Error Word0 Register */ +/*! @{ */ + +#define TRDC_MBC4_W0_EADDR_MASK (0xFFFFFFFFU) +#define TRDC_MBC4_W0_EADDR_SHIFT (0U) +/*! EADDR - Error address */ +#define TRDC_MBC4_W0_EADDR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_W0_EADDR_SHIFT)) & TRDC_MBC4_W0_EADDR_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_W0 */ +#define TRDC_MBC4_W0_COUNT (4U) + +/*! @name W1 - MBC Domain Error Word1 Register */ +/*! @{ */ + +#define TRDC_MBC4_W1_EDID_MASK (0xFU) +#define TRDC_MBC4_W1_EDID_SHIFT (0U) +/*! EDID - Error domain identifier */ +#define TRDC_MBC4_W1_EDID(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_W1_EDID_SHIFT)) & TRDC_MBC4_W1_EDID_MASK) + +#define TRDC_MBC4_W1_EATR_MASK (0x700U) +#define TRDC_MBC4_W1_EATR_SHIFT (8U) +/*! EATR - Error attributes + * 0b000..Secure user mode, instruction fetch access. + * 0b001..Secure user mode, data access. + * 0b010..Secure privileged mode, instruction fetch access. + * 0b011..Secure privileged mode, data access. + * 0b100..Nonsecure user mode, instruction fetch access. + * 0b101..Nonsecure user mode, data access. + * 0b110..Nonsecure privileged mode, instruction fetch access. + * 0b111..Nonsecure privileged mode, data access. + */ +#define TRDC_MBC4_W1_EATR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_W1_EATR_SHIFT)) & TRDC_MBC4_W1_EATR_MASK) + +#define TRDC_MBC4_W1_ERW_MASK (0x800U) +#define TRDC_MBC4_W1_ERW_SHIFT (11U) +/*! ERW - Error read/write + * 0b0..Read access + * 0b1..Write access + */ +#define TRDC_MBC4_W1_ERW(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_W1_ERW_SHIFT)) & TRDC_MBC4_W1_ERW_MASK) + +#define TRDC_MBC4_W1_EPORT_MASK (0x7000000U) +#define TRDC_MBC4_W1_EPORT_SHIFT (24U) +/*! EPORT - Error port + * 0b000..mbcxslv0 + * 0b001..mbcxslv1 + * 0b010..mbcxslv2 + * 0b011..mbcxslv3 + */ +#define TRDC_MBC4_W1_EPORT(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_W1_EPORT_SHIFT)) & TRDC_MBC4_W1_EPORT_MASK) + +#define TRDC_MBC4_W1_EST_MASK (0xC0000000U) +#define TRDC_MBC4_W1_EST_SHIFT (30U) +/*! EST - Error state + * 0b00..No access violation has been detected. + * 0b01..No access violation has been detected. + * 0b10..A single access violation has been detected. + * 0b11..Multiple access violations for this domain have been detected by this submodule instance. Only the + * address and attribute information for the first error have been captured in DERR_W0_i and DERR_W1_i. + */ +#define TRDC_MBC4_W1_EST(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_W1_EST_SHIFT)) & TRDC_MBC4_W1_EST_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_W1 */ +#define TRDC_MBC4_W1_COUNT (4U) + +/*! @name W3 - MBC Domain Error Word3 Register */ +/*! @{ */ + +#define TRDC_MBC4_W3_RECR_MASK (0xC0000000U) +#define TRDC_MBC4_W3_RECR_SHIFT (30U) +/*! RECR - Rearm Error Capture Registers */ +#define TRDC_MBC4_W3_RECR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_W3_RECR_SHIFT)) & TRDC_MBC4_W3_RECR_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_W3 */ +#define TRDC_MBC4_W3_COUNT (4U) + +/*! @name W0 - MRC Domain Error Word0 Register */ +/*! @{ */ + +#define TRDC_MBC4_W0_EADDR_MASK (0xFFFFFFFFU) +#define TRDC_MBC4_W0_EADDR_SHIFT (0U) +/*! EADDR - Error address */ +#define TRDC_MBC4_W0_EADDR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_W0_EADDR_SHIFT)) & TRDC_MBC4_W0_EADDR_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_W0 */ +#define TRDC_MBC4_MRC_DERR_W0_COUNT (1U) + +/*! @name W1 - MRC Domain Error Word1 Register */ +/*! @{ */ + +#define TRDC_MBC4_W1_EDID_MASK (0xFU) +#define TRDC_MBC4_W1_EDID_SHIFT (0U) +/*! EDID - Error domain identifier */ +#define TRDC_MBC4_W1_EDID(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_W1_EDID_SHIFT)) & TRDC_MBC4_W1_EDID_MASK) + +#define TRDC_MBC4_W1_EATR_MASK (0x700U) +#define TRDC_MBC4_W1_EATR_SHIFT (8U) +/*! EATR - Error attributes + * 0b000..Secure user mode, instruction fetch access. + * 0b001..Secure user mode, data access. + * 0b010..Secure privileged mode, instruction fetch access. + * 0b011..Secure privileged mode, data access. + * 0b100..Nonsecure user mode, instruction fetch access. + * 0b101..Nonsecure user mode, data access. + * 0b110..Nonsecure privileged mode, instruction fetch access. + * 0b111..Nonsecure privileged mode, data access. + */ +#define TRDC_MBC4_W1_EATR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_W1_EATR_SHIFT)) & TRDC_MBC4_W1_EATR_MASK) + +#define TRDC_MBC4_W1_ERW_MASK (0x800U) +#define TRDC_MBC4_W1_ERW_SHIFT (11U) +/*! ERW - Error read/write + * 0b0..Read access + * 0b1..Write access + */ +#define TRDC_MBC4_W1_ERW(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_W1_ERW_SHIFT)) & TRDC_MBC4_W1_ERW_MASK) + +#define TRDC_MBC4_W1_EPORT_MASK (0x7000000U) +#define TRDC_MBC4_W1_EPORT_SHIFT (24U) +/*! EPORT - Error port */ +#define TRDC_MBC4_W1_EPORT(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_W1_EPORT_SHIFT)) & TRDC_MBC4_W1_EPORT_MASK) + +#define TRDC_MBC4_W1_EST_MASK (0xC0000000U) +#define TRDC_MBC4_W1_EST_SHIFT (30U) +/*! EST - Error state + * 0b00..No access violation has been detected. + * 0b01..No access violation has been detected. + * 0b10..A single access violation has been detected. + * 0b11..Multiple access violations for this domain have been detected by this submodule instance. Only the + * address and attribute information for the first error have been captured in DERR_W0_i and DERR_W1_i. + */ +#define TRDC_MBC4_W1_EST(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_W1_EST_SHIFT)) & TRDC_MBC4_W1_EST_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_W1 */ +#define TRDC_MBC4_MRC_DERR_W1_COUNT (1U) + +/*! @name W3 - MRC Domain Error Word3 Register */ +/*! @{ */ + +#define TRDC_MBC4_W3_RECR_MASK (0xC0000000U) +#define TRDC_MBC4_W3_RECR_SHIFT (30U) +/*! RECR - Rearm Error Capture Registers */ +#define TRDC_MBC4_W3_RECR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_W3_RECR_SHIFT)) & TRDC_MBC4_W3_RECR_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_W3 */ +#define TRDC_MBC4_MRC_DERR_W3_COUNT (1U) + +/*! @name MDA_W_DFMT0 - DAC Master Domain Assignment Register */ +/*! @{ */ + +#define TRDC_MBC4_MDA_W_DFMT0_DID_MASK (0xFU) +#define TRDC_MBC4_MDA_W_DFMT0_DID_SHIFT (0U) +/*! DID - Domain identifier */ +#define TRDC_MBC4_MDA_W_DFMT0_DID(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MDA_W_DFMT0_DID_SHIFT)) & TRDC_MBC4_MDA_W_DFMT0_DID_MASK) + +#define TRDC_MBC4_MDA_W_DFMT0_DIDS_MASK (0x30U) +#define TRDC_MBC4_MDA_W_DFMT0_DIDS_SHIFT (4U) +/*! DIDS - DID Select + * 0b00..Use MDAm[3:0] as the domain identifier. + * 0b01..Use the input DID as the domain identifier. + * 0b10..Use MDAm[3:2] concatenated with the low-order 2 bits of the input DID (DID_in[1:0]) as the domain identifier. + * 0b11..Reserved for future use. + */ +#define TRDC_MBC4_MDA_W_DFMT0_DIDS(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MDA_W_DFMT0_DIDS_SHIFT)) & TRDC_MBC4_MDA_W_DFMT0_DIDS_MASK) + +#define TRDC_MBC4_MDA_W_DFMT0_PE_MASK (0xC0U) +#define TRDC_MBC4_MDA_W_DFMT0_PE_SHIFT (6U) +/*! PE - Process identifier enable + * 0b00..No process identifier is included in the domain hit evaluation. + * 0b01..No process identifier is included in the domain hit evaluation. + * 0b10..PE = 2 + * 0b11..PE = 3 + */ +#define TRDC_MBC4_MDA_W_DFMT0_PE(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MDA_W_DFMT0_PE_SHIFT)) & TRDC_MBC4_MDA_W_DFMT0_PE_MASK) + +#define TRDC_MBC4_MDA_W_DFMT0_PIDM_MASK (0x3F00U) +#define TRDC_MBC4_MDA_W_DFMT0_PIDM_SHIFT (8U) +/*! PIDM - Process Identifier Mask */ +#define TRDC_MBC4_MDA_W_DFMT0_PIDM(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MDA_W_DFMT0_PIDM_SHIFT)) & TRDC_MBC4_MDA_W_DFMT0_PIDM_MASK) + +#define TRDC_MBC4_MDA_W_DFMT0_SA_MASK (0xC000U) +#define TRDC_MBC4_MDA_W_DFMT0_SA_SHIFT (14U) +/*! SA - Secure attribute + * 0b00..Force the bus attribute for this master to secure. + * 0b01..Force the bus attribute for this master to nonsecure. + * 0b10..Use the bus master's secure/nonsecure attribute directly. + * 0b11..Use the bus master's secure/nonsecure attribute directly. + */ +#define TRDC_MBC4_MDA_W_DFMT0_SA(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MDA_W_DFMT0_SA_SHIFT)) & TRDC_MBC4_MDA_W_DFMT0_SA_MASK) + +#define TRDC_MBC4_MDA_W_DFMT0_PID_MASK (0x3F0000U) +#define TRDC_MBC4_MDA_W_DFMT0_PID_SHIFT (16U) +/*! PID - Process Identifier */ +#define TRDC_MBC4_MDA_W_DFMT0_PID(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MDA_W_DFMT0_PID_SHIFT)) & TRDC_MBC4_MDA_W_DFMT0_PID_MASK) + +#define TRDC_MBC4_MDA_W_DFMT0_DFMT_MASK (0x20000000U) +#define TRDC_MBC4_MDA_W_DFMT0_DFMT_SHIFT (29U) +/*! DFMT - Domain format + * 0b0..Processor-core domain assignment + * 0b1..Non-processor domain assignment + */ +#define TRDC_MBC4_MDA_W_DFMT0_DFMT(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MDA_W_DFMT0_DFMT_SHIFT)) & TRDC_MBC4_MDA_W_DFMT0_DFMT_MASK) + +#define TRDC_MBC4_MDA_W_DFMT0_LK1_MASK (0x40000000U) +#define TRDC_MBC4_MDA_W_DFMT0_LK1_SHIFT (30U) +/*! LK1 - 1-bit Lock + * 0b0..Register can be written by any secure privileged write. + * 0b1..Register is locked (read-only) until the next reset. + */ +#define TRDC_MBC4_MDA_W_DFMT0_LK1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MDA_W_DFMT0_LK1_SHIFT)) & TRDC_MBC4_MDA_W_DFMT0_LK1_MASK) + +#define TRDC_MBC4_MDA_W_DFMT0_VLD_MASK (0x80000000U) +#define TRDC_MBC4_MDA_W_DFMT0_VLD_SHIFT (31U) +/*! VLD - Valid + * 0b0..The Wr domain assignment is invalid. + * 0b1..The Wr domain assignment is valid. + */ +#define TRDC_MBC4_MDA_W_DFMT0_VLD(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MDA_W_DFMT0_VLD_SHIFT)) & TRDC_MBC4_MDA_W_DFMT0_VLD_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MDA_W_DFMT0 */ +#define TRDC_MBC4_MDA_W_DFMT0_COUNT (2U) + +/* The count of TRDC_MBC4_MDA_W_DFMT0 */ +#define TRDC_MBC4_MDA_W_DFMT0_COUNT2 (4U) + +/*! @name MBC_MEM_GLBCFG - MBC Global Configuration Register */ +/*! @{ */ + +#define TRDC_MBC4_MBC_MEM_GLBCFG_NBLKS_MASK (0x3FFU) +#define TRDC_MBC4_MBC_MEM_GLBCFG_NBLKS_SHIFT (0U) +/*! NBLKS - Number of blocks in this memory */ +#define TRDC_MBC4_MBC_MEM_GLBCFG_NBLKS(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_MEM_GLBCFG_NBLKS_SHIFT)) & TRDC_MBC4_MBC_MEM_GLBCFG_NBLKS_MASK) + +#define TRDC_MBC4_MBC_MEM_GLBCFG_SIZE_LOG2_MASK (0x1F0000U) +#define TRDC_MBC4_MBC_MEM_GLBCFG_SIZE_LOG2_SHIFT (16U) +/*! SIZE_LOG2 - Log2 size per block */ +#define TRDC_MBC4_MBC_MEM_GLBCFG_SIZE_LOG2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_MEM_GLBCFG_SIZE_LOG2_SHIFT)) & TRDC_MBC4_MBC_MEM_GLBCFG_SIZE_LOG2_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MBC_MEM_GLBCFG */ +#define TRDC_MBC4_MBC_MEM_GLBCFG_COUNT (4U) + +/* The count of TRDC_MBC4_MBC_MEM_GLBCFG */ +#define TRDC_MBC4_MBC_MEM_GLBCFG_COUNT2 (4U) + +/*! @name MBC_NSE_BLK_INDEX - MBC NonSecure Enable Block Index */ +/*! @{ */ + +#define TRDC_MBC4_MBC_NSE_BLK_INDEX_AI_MASK (0x1U) +#define TRDC_MBC4_MBC_NSE_BLK_INDEX_AI_SHIFT (0U) +/*! AI - Auto Increment + * 0b0..No effect. + * 0b1..Add 1 to the WNDX field after the register write. + */ +#define TRDC_MBC4_MBC_NSE_BLK_INDEX_AI(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_NSE_BLK_INDEX_AI_SHIFT)) & TRDC_MBC4_MBC_NSE_BLK_INDEX_AI_MASK) + +#define TRDC_MBC4_MBC_NSE_BLK_INDEX_WNDX_MASK (0x3CU) +#define TRDC_MBC4_MBC_NSE_BLK_INDEX_WNDX_SHIFT (2U) +/*! WNDX - Word index into the block NSE bitmap. It selects the BLK_NSE_Wn register, where WNDX determines the value of n. */ +#define TRDC_MBC4_MBC_NSE_BLK_INDEX_WNDX(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_NSE_BLK_INDEX_WNDX_SHIFT)) & TRDC_MBC4_MBC_NSE_BLK_INDEX_WNDX_MASK) + +#define TRDC_MBC4_MBC_NSE_BLK_INDEX_MEM_SEL_MASK (0xF00U) +#define TRDC_MBC4_MBC_NSE_BLK_INDEX_MEM_SEL_SHIFT (8U) +/*! MEM_SEL - Memory Select */ +#define TRDC_MBC4_MBC_NSE_BLK_INDEX_MEM_SEL(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_NSE_BLK_INDEX_MEM_SEL_SHIFT)) & TRDC_MBC4_MBC_NSE_BLK_INDEX_MEM_SEL_MASK) + +#define TRDC_MBC4_MBC_NSE_BLK_INDEX_DID_SEL0_MASK (0x10000U) +#define TRDC_MBC4_MBC_NSE_BLK_INDEX_DID_SEL0_SHIFT (16U) +/*! DID_SEL0 - DID Select + * 0b0..No effect. + * 0b1..Selects NSE bits for this domain. + */ +#define TRDC_MBC4_MBC_NSE_BLK_INDEX_DID_SEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_NSE_BLK_INDEX_DID_SEL0_SHIFT)) & TRDC_MBC4_MBC_NSE_BLK_INDEX_DID_SEL0_MASK) + +#define TRDC_MBC4_MBC_NSE_BLK_INDEX_DID_SEL1_MASK (0x20000U) +#define TRDC_MBC4_MBC_NSE_BLK_INDEX_DID_SEL1_SHIFT (17U) +/*! DID_SEL1 - DID Select + * 0b0..No effect. + * 0b1..Selects NSE bits for this domain. + */ +#define TRDC_MBC4_MBC_NSE_BLK_INDEX_DID_SEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_NSE_BLK_INDEX_DID_SEL1_SHIFT)) & TRDC_MBC4_MBC_NSE_BLK_INDEX_DID_SEL1_MASK) + +#define TRDC_MBC4_MBC_NSE_BLK_INDEX_DID_SEL2_MASK (0x40000U) +#define TRDC_MBC4_MBC_NSE_BLK_INDEX_DID_SEL2_SHIFT (18U) +/*! DID_SEL2 - DID Select + * 0b0..No effect. + * 0b1..Selects NSE bits for this domain. + */ +#define TRDC_MBC4_MBC_NSE_BLK_INDEX_DID_SEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_NSE_BLK_INDEX_DID_SEL2_SHIFT)) & TRDC_MBC4_MBC_NSE_BLK_INDEX_DID_SEL2_MASK) + +#define TRDC_MBC4_MBC_NSE_BLK_INDEX_DID_SEL3_MASK (0x80000U) +#define TRDC_MBC4_MBC_NSE_BLK_INDEX_DID_SEL3_SHIFT (19U) +/*! DID_SEL3 - DID Select + * 0b0..No effect. + * 0b1..Selects NSE bits for this domain. + */ +#define TRDC_MBC4_MBC_NSE_BLK_INDEX_DID_SEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_NSE_BLK_INDEX_DID_SEL3_SHIFT)) & TRDC_MBC4_MBC_NSE_BLK_INDEX_DID_SEL3_MASK) + +#define TRDC_MBC4_MBC_NSE_BLK_INDEX_DID_SEL4_MASK (0x100000U) +#define TRDC_MBC4_MBC_NSE_BLK_INDEX_DID_SEL4_SHIFT (20U) +/*! DID_SEL4 - DID Select + * 0b0..No effect. + * 0b1..Selects NSE bits for this domain. + */ +#define TRDC_MBC4_MBC_NSE_BLK_INDEX_DID_SEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_NSE_BLK_INDEX_DID_SEL4_SHIFT)) & TRDC_MBC4_MBC_NSE_BLK_INDEX_DID_SEL4_MASK) + +#define TRDC_MBC4_MBC_NSE_BLK_INDEX_DID_SEL5_MASK (0x200000U) +#define TRDC_MBC4_MBC_NSE_BLK_INDEX_DID_SEL5_SHIFT (21U) +/*! DID_SEL5 - DID Select + * 0b0..No effect. + * 0b1..Selects NSE bits for this domain. + */ +#define TRDC_MBC4_MBC_NSE_BLK_INDEX_DID_SEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_NSE_BLK_INDEX_DID_SEL5_SHIFT)) & TRDC_MBC4_MBC_NSE_BLK_INDEX_DID_SEL5_MASK) + +#define TRDC_MBC4_MBC_NSE_BLK_INDEX_DID_SEL6_MASK (0x400000U) +#define TRDC_MBC4_MBC_NSE_BLK_INDEX_DID_SEL6_SHIFT (22U) +/*! DID_SEL6 - DID Select + * 0b0..No effect. + * 0b1..Selects NSE bits for this domain. + */ +#define TRDC_MBC4_MBC_NSE_BLK_INDEX_DID_SEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_NSE_BLK_INDEX_DID_SEL6_SHIFT)) & TRDC_MBC4_MBC_NSE_BLK_INDEX_DID_SEL6_MASK) + +#define TRDC_MBC4_MBC_NSE_BLK_INDEX_DID_SEL7_MASK (0x800000U) +#define TRDC_MBC4_MBC_NSE_BLK_INDEX_DID_SEL7_SHIFT (23U) +/*! DID_SEL7 - DID Select + * 0b0..No effect. + * 0b1..Selects NSE bits for this domain. + */ +#define TRDC_MBC4_MBC_NSE_BLK_INDEX_DID_SEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_NSE_BLK_INDEX_DID_SEL7_SHIFT)) & TRDC_MBC4_MBC_NSE_BLK_INDEX_DID_SEL7_MASK) + +#define TRDC_MBC4_MBC_NSE_BLK_INDEX_DID_SEL8_MASK (0x1000000U) +#define TRDC_MBC4_MBC_NSE_BLK_INDEX_DID_SEL8_SHIFT (24U) +/*! DID_SEL8 - DID Select + * 0b0..No effect. + * 0b1..Selects NSE bits for this domain. + */ +#define TRDC_MBC4_MBC_NSE_BLK_INDEX_DID_SEL8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_NSE_BLK_INDEX_DID_SEL8_SHIFT)) & TRDC_MBC4_MBC_NSE_BLK_INDEX_DID_SEL8_MASK) + +#define TRDC_MBC4_MBC_NSE_BLK_INDEX_DID_SEL9_MASK (0x2000000U) +#define TRDC_MBC4_MBC_NSE_BLK_INDEX_DID_SEL9_SHIFT (25U) +/*! DID_SEL9 - DID Select + * 0b0..No effect. + * 0b1..Selects NSE bits for this domain. + */ +#define TRDC_MBC4_MBC_NSE_BLK_INDEX_DID_SEL9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_NSE_BLK_INDEX_DID_SEL9_SHIFT)) & TRDC_MBC4_MBC_NSE_BLK_INDEX_DID_SEL9_MASK) + +#define TRDC_MBC4_MBC_NSE_BLK_INDEX_DID_SEL10_MASK (0x4000000U) +#define TRDC_MBC4_MBC_NSE_BLK_INDEX_DID_SEL10_SHIFT (26U) +/*! DID_SEL10 - DID Select + * 0b0..No effect. + * 0b1..Selects NSE bits for this domain. + */ +#define TRDC_MBC4_MBC_NSE_BLK_INDEX_DID_SEL10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_NSE_BLK_INDEX_DID_SEL10_SHIFT)) & TRDC_MBC4_MBC_NSE_BLK_INDEX_DID_SEL10_MASK) + +#define TRDC_MBC4_MBC_NSE_BLK_INDEX_DID_SEL11_MASK (0x8000000U) +#define TRDC_MBC4_MBC_NSE_BLK_INDEX_DID_SEL11_SHIFT (27U) +/*! DID_SEL11 - DID Select + * 0b0..No effect. + * 0b1..Selects NSE bits for this domain. + */ +#define TRDC_MBC4_MBC_NSE_BLK_INDEX_DID_SEL11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_NSE_BLK_INDEX_DID_SEL11_SHIFT)) & TRDC_MBC4_MBC_NSE_BLK_INDEX_DID_SEL11_MASK) + +#define TRDC_MBC4_MBC_NSE_BLK_INDEX_DID_SEL12_MASK (0x10000000U) +#define TRDC_MBC4_MBC_NSE_BLK_INDEX_DID_SEL12_SHIFT (28U) +/*! DID_SEL12 - DID Select + * 0b0..No effect. + * 0b1..Selects NSE bits for this domain. + */ +#define TRDC_MBC4_MBC_NSE_BLK_INDEX_DID_SEL12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_NSE_BLK_INDEX_DID_SEL12_SHIFT)) & TRDC_MBC4_MBC_NSE_BLK_INDEX_DID_SEL12_MASK) + +#define TRDC_MBC4_MBC_NSE_BLK_INDEX_DID_SEL13_MASK (0x20000000U) +#define TRDC_MBC4_MBC_NSE_BLK_INDEX_DID_SEL13_SHIFT (29U) +/*! DID_SEL13 - DID Select + * 0b0..No effect. + * 0b1..Selects NSE bits for this domain. + */ +#define TRDC_MBC4_MBC_NSE_BLK_INDEX_DID_SEL13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_NSE_BLK_INDEX_DID_SEL13_SHIFT)) & TRDC_MBC4_MBC_NSE_BLK_INDEX_DID_SEL13_MASK) + +#define TRDC_MBC4_MBC_NSE_BLK_INDEX_DID_SEL14_MASK (0x40000000U) +#define TRDC_MBC4_MBC_NSE_BLK_INDEX_DID_SEL14_SHIFT (30U) +/*! DID_SEL14 - DID Select + * 0b0..No effect. + * 0b1..Selects NSE bits for this domain. + */ +#define TRDC_MBC4_MBC_NSE_BLK_INDEX_DID_SEL14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_NSE_BLK_INDEX_DID_SEL14_SHIFT)) & TRDC_MBC4_MBC_NSE_BLK_INDEX_DID_SEL14_MASK) + +#define TRDC_MBC4_MBC_NSE_BLK_INDEX_DID_SEL15_MASK (0x80000000U) +#define TRDC_MBC4_MBC_NSE_BLK_INDEX_DID_SEL15_SHIFT (31U) +/*! DID_SEL15 - DID Select + * 0b0..No effect. + * 0b1..Selects NSE bits for this domain. + */ +#define TRDC_MBC4_MBC_NSE_BLK_INDEX_DID_SEL15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_NSE_BLK_INDEX_DID_SEL15_SHIFT)) & TRDC_MBC4_MBC_NSE_BLK_INDEX_DID_SEL15_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MBC_NSE_BLK_INDEX */ +#define TRDC_MBC4_MBC_NSE_BLK_INDEX_COUNT (4U) + +/*! @name MBC_NSE_BLK_SET - MBC NonSecure Enable Block Set */ +/*! @{ */ + +#define TRDC_MBC4_MBC_NSE_BLK_SET_W1SET_MASK (0xFFFFFFFFU) +#define TRDC_MBC4_MBC_NSE_BLK_SET_W1SET_SHIFT (0U) +/*! W1SET - Write-1 Set */ +#define TRDC_MBC4_MBC_NSE_BLK_SET_W1SET(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_NSE_BLK_SET_W1SET_SHIFT)) & TRDC_MBC4_MBC_NSE_BLK_SET_W1SET_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MBC_NSE_BLK_SET */ +#define TRDC_MBC4_MBC_NSE_BLK_SET_COUNT (4U) + +/*! @name MBC_NSE_BLK_CLR - MBC NonSecure Enable Block Clear */ +/*! @{ */ + +#define TRDC_MBC4_MBC_NSE_BLK_CLR_W1CLR_MASK (0xFFFFFFFFU) +#define TRDC_MBC4_MBC_NSE_BLK_CLR_W1CLR_SHIFT (0U) +/*! W1CLR - Write-1 Clear */ +#define TRDC_MBC4_MBC_NSE_BLK_CLR_W1CLR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_NSE_BLK_CLR_W1CLR_SHIFT)) & TRDC_MBC4_MBC_NSE_BLK_CLR_W1CLR_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MBC_NSE_BLK_CLR */ +#define TRDC_MBC4_MBC_NSE_BLK_CLR_COUNT (4U) + +/*! @name MBC_NSE_BLK_CLR_ALL - MBC NonSecure Enable Block Clear All */ +/*! @{ */ + +#define TRDC_MBC4_MBC_NSE_BLK_CLR_ALL_MEMSEL_MASK (0xF00U) +#define TRDC_MBC4_MBC_NSE_BLK_CLR_ALL_MEMSEL_SHIFT (8U) +/*! MEMSEL - Memory Select */ +#define TRDC_MBC4_MBC_NSE_BLK_CLR_ALL_MEMSEL(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_NSE_BLK_CLR_ALL_MEMSEL_SHIFT)) & TRDC_MBC4_MBC_NSE_BLK_CLR_ALL_MEMSEL_MASK) + +#define TRDC_MBC4_MBC_NSE_BLK_CLR_ALL_DID_SEL0_MASK (0x10000U) +#define TRDC_MBC4_MBC_NSE_BLK_CLR_ALL_DID_SEL0_SHIFT (16U) +/*! DID_SEL0 - DID Select + * 0b0..No effect. + * 0b1..Clear all NSE bits for this domain. + */ +#define TRDC_MBC4_MBC_NSE_BLK_CLR_ALL_DID_SEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_NSE_BLK_CLR_ALL_DID_SEL0_SHIFT)) & TRDC_MBC4_MBC_NSE_BLK_CLR_ALL_DID_SEL0_MASK) + +#define TRDC_MBC4_MBC_NSE_BLK_CLR_ALL_DID_SEL1_MASK (0x20000U) +#define TRDC_MBC4_MBC_NSE_BLK_CLR_ALL_DID_SEL1_SHIFT (17U) +/*! DID_SEL1 - DID Select + * 0b0..No effect. + * 0b1..Clear all NSE bits for this domain. + */ +#define TRDC_MBC4_MBC_NSE_BLK_CLR_ALL_DID_SEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_NSE_BLK_CLR_ALL_DID_SEL1_SHIFT)) & TRDC_MBC4_MBC_NSE_BLK_CLR_ALL_DID_SEL1_MASK) + +#define TRDC_MBC4_MBC_NSE_BLK_CLR_ALL_DID_SEL2_MASK (0x40000U) +#define TRDC_MBC4_MBC_NSE_BLK_CLR_ALL_DID_SEL2_SHIFT (18U) +/*! DID_SEL2 - DID Select + * 0b0..No effect. + * 0b1..Clear all NSE bits for this domain. + */ +#define TRDC_MBC4_MBC_NSE_BLK_CLR_ALL_DID_SEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_NSE_BLK_CLR_ALL_DID_SEL2_SHIFT)) & TRDC_MBC4_MBC_NSE_BLK_CLR_ALL_DID_SEL2_MASK) + +#define TRDC_MBC4_MBC_NSE_BLK_CLR_ALL_DID_SEL3_MASK (0x80000U) +#define TRDC_MBC4_MBC_NSE_BLK_CLR_ALL_DID_SEL3_SHIFT (19U) +/*! DID_SEL3 - DID Select + * 0b0..No effect. + * 0b1..Clear all NSE bits for this domain. + */ +#define TRDC_MBC4_MBC_NSE_BLK_CLR_ALL_DID_SEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_NSE_BLK_CLR_ALL_DID_SEL3_SHIFT)) & TRDC_MBC4_MBC_NSE_BLK_CLR_ALL_DID_SEL3_MASK) + +#define TRDC_MBC4_MBC_NSE_BLK_CLR_ALL_DID_SEL4_MASK (0x100000U) +#define TRDC_MBC4_MBC_NSE_BLK_CLR_ALL_DID_SEL4_SHIFT (20U) +/*! DID_SEL4 - DID Select + * 0b0..No effect. + * 0b1..Clear all NSE bits for this domain. + */ +#define TRDC_MBC4_MBC_NSE_BLK_CLR_ALL_DID_SEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_NSE_BLK_CLR_ALL_DID_SEL4_SHIFT)) & TRDC_MBC4_MBC_NSE_BLK_CLR_ALL_DID_SEL4_MASK) + +#define TRDC_MBC4_MBC_NSE_BLK_CLR_ALL_DID_SEL5_MASK (0x200000U) +#define TRDC_MBC4_MBC_NSE_BLK_CLR_ALL_DID_SEL5_SHIFT (21U) +/*! DID_SEL5 - DID Select + * 0b0..No effect. + * 0b1..Clear all NSE bits for this domain. + */ +#define TRDC_MBC4_MBC_NSE_BLK_CLR_ALL_DID_SEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_NSE_BLK_CLR_ALL_DID_SEL5_SHIFT)) & TRDC_MBC4_MBC_NSE_BLK_CLR_ALL_DID_SEL5_MASK) + +#define TRDC_MBC4_MBC_NSE_BLK_CLR_ALL_DID_SEL6_MASK (0x400000U) +#define TRDC_MBC4_MBC_NSE_BLK_CLR_ALL_DID_SEL6_SHIFT (22U) +/*! DID_SEL6 - DID Select + * 0b0..No effect. + * 0b1..Clear all NSE bits for this domain. + */ +#define TRDC_MBC4_MBC_NSE_BLK_CLR_ALL_DID_SEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_NSE_BLK_CLR_ALL_DID_SEL6_SHIFT)) & TRDC_MBC4_MBC_NSE_BLK_CLR_ALL_DID_SEL6_MASK) + +#define TRDC_MBC4_MBC_NSE_BLK_CLR_ALL_DID_SEL7_MASK (0x800000U) +#define TRDC_MBC4_MBC_NSE_BLK_CLR_ALL_DID_SEL7_SHIFT (23U) +/*! DID_SEL7 - DID Select + * 0b0..No effect. + * 0b1..Clear all NSE bits for this domain. + */ +#define TRDC_MBC4_MBC_NSE_BLK_CLR_ALL_DID_SEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_NSE_BLK_CLR_ALL_DID_SEL7_SHIFT)) & TRDC_MBC4_MBC_NSE_BLK_CLR_ALL_DID_SEL7_MASK) + +#define TRDC_MBC4_MBC_NSE_BLK_CLR_ALL_DID_SEL8_MASK (0x1000000U) +#define TRDC_MBC4_MBC_NSE_BLK_CLR_ALL_DID_SEL8_SHIFT (24U) +/*! DID_SEL8 - DID Select + * 0b0..No effect. + * 0b1..Clear all NSE bits for this domain. + */ +#define TRDC_MBC4_MBC_NSE_BLK_CLR_ALL_DID_SEL8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_NSE_BLK_CLR_ALL_DID_SEL8_SHIFT)) & TRDC_MBC4_MBC_NSE_BLK_CLR_ALL_DID_SEL8_MASK) + +#define TRDC_MBC4_MBC_NSE_BLK_CLR_ALL_DID_SEL9_MASK (0x2000000U) +#define TRDC_MBC4_MBC_NSE_BLK_CLR_ALL_DID_SEL9_SHIFT (25U) +/*! DID_SEL9 - DID Select + * 0b0..No effect. + * 0b1..Clear all NSE bits for this domain. + */ +#define TRDC_MBC4_MBC_NSE_BLK_CLR_ALL_DID_SEL9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_NSE_BLK_CLR_ALL_DID_SEL9_SHIFT)) & TRDC_MBC4_MBC_NSE_BLK_CLR_ALL_DID_SEL9_MASK) + +#define TRDC_MBC4_MBC_NSE_BLK_CLR_ALL_DID_SEL10_MASK (0x4000000U) +#define TRDC_MBC4_MBC_NSE_BLK_CLR_ALL_DID_SEL10_SHIFT (26U) +/*! DID_SEL10 - DID Select + * 0b0..No effect. + * 0b1..Clear all NSE bits for this domain. + */ +#define TRDC_MBC4_MBC_NSE_BLK_CLR_ALL_DID_SEL10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_NSE_BLK_CLR_ALL_DID_SEL10_SHIFT)) & TRDC_MBC4_MBC_NSE_BLK_CLR_ALL_DID_SEL10_MASK) + +#define TRDC_MBC4_MBC_NSE_BLK_CLR_ALL_DID_SEL11_MASK (0x8000000U) +#define TRDC_MBC4_MBC_NSE_BLK_CLR_ALL_DID_SEL11_SHIFT (27U) +/*! DID_SEL11 - DID Select + * 0b0..No effect. + * 0b1..Clear all NSE bits for this domain. + */ +#define TRDC_MBC4_MBC_NSE_BLK_CLR_ALL_DID_SEL11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_NSE_BLK_CLR_ALL_DID_SEL11_SHIFT)) & TRDC_MBC4_MBC_NSE_BLK_CLR_ALL_DID_SEL11_MASK) + +#define TRDC_MBC4_MBC_NSE_BLK_CLR_ALL_DID_SEL12_MASK (0x10000000U) +#define TRDC_MBC4_MBC_NSE_BLK_CLR_ALL_DID_SEL12_SHIFT (28U) +/*! DID_SEL12 - DID Select + * 0b0..No effect. + * 0b1..Clear all NSE bits for this domain. + */ +#define TRDC_MBC4_MBC_NSE_BLK_CLR_ALL_DID_SEL12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_NSE_BLK_CLR_ALL_DID_SEL12_SHIFT)) & TRDC_MBC4_MBC_NSE_BLK_CLR_ALL_DID_SEL12_MASK) + +#define TRDC_MBC4_MBC_NSE_BLK_CLR_ALL_DID_SEL13_MASK (0x20000000U) +#define TRDC_MBC4_MBC_NSE_BLK_CLR_ALL_DID_SEL13_SHIFT (29U) +/*! DID_SEL13 - DID Select + * 0b0..No effect. + * 0b1..Clear all NSE bits for this domain. + */ +#define TRDC_MBC4_MBC_NSE_BLK_CLR_ALL_DID_SEL13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_NSE_BLK_CLR_ALL_DID_SEL13_SHIFT)) & TRDC_MBC4_MBC_NSE_BLK_CLR_ALL_DID_SEL13_MASK) + +#define TRDC_MBC4_MBC_NSE_BLK_CLR_ALL_DID_SEL14_MASK (0x40000000U) +#define TRDC_MBC4_MBC_NSE_BLK_CLR_ALL_DID_SEL14_SHIFT (30U) +/*! DID_SEL14 - DID Select + * 0b0..No effect. + * 0b1..Clear all NSE bits for this domain. + */ +#define TRDC_MBC4_MBC_NSE_BLK_CLR_ALL_DID_SEL14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_NSE_BLK_CLR_ALL_DID_SEL14_SHIFT)) & TRDC_MBC4_MBC_NSE_BLK_CLR_ALL_DID_SEL14_MASK) + +#define TRDC_MBC4_MBC_NSE_BLK_CLR_ALL_DID_SEL15_MASK (0x80000000U) +#define TRDC_MBC4_MBC_NSE_BLK_CLR_ALL_DID_SEL15_SHIFT (31U) +/*! DID_SEL15 - DID Select + * 0b0..No effect. + * 0b1..Clear all NSE bits for this domain. + */ +#define TRDC_MBC4_MBC_NSE_BLK_CLR_ALL_DID_SEL15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_NSE_BLK_CLR_ALL_DID_SEL15_SHIFT)) & TRDC_MBC4_MBC_NSE_BLK_CLR_ALL_DID_SEL15_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MBC_NSE_BLK_CLR_ALL */ +#define TRDC_MBC4_MBC_NSE_BLK_CLR_ALL_COUNT (4U) + +/*! @name MBC_MEMN_GLBAC - MBC Global Access Control */ +/*! @{ */ + +#define TRDC_MBC4_MBC_MEMN_GLBAC_NUX_MASK (0x1U) +#define TRDC_MBC4_MBC_MEMN_GLBAC_NUX_SHIFT (0U) +/*! NUX - NonsecureUser Execute + * 0b0..Execute access is not allowed in Nonsecure User mode. + * 0b1..Execute access is allowed in Nonsecure User mode. + */ +#define TRDC_MBC4_MBC_MEMN_GLBAC_NUX(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_MEMN_GLBAC_NUX_SHIFT)) & TRDC_MBC4_MBC_MEMN_GLBAC_NUX_MASK) + +#define TRDC_MBC4_MBC_MEMN_GLBAC_NUW_MASK (0x2U) +#define TRDC_MBC4_MBC_MEMN_GLBAC_NUW_SHIFT (1U) +/*! NUW - NonsecureUser Write + * 0b0..Write access is not allowed in Nonsecure User mode. + * 0b1..Write access is allowed in Nonsecure User mode. + */ +#define TRDC_MBC4_MBC_MEMN_GLBAC_NUW(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_MEMN_GLBAC_NUW_SHIFT)) & TRDC_MBC4_MBC_MEMN_GLBAC_NUW_MASK) + +#define TRDC_MBC4_MBC_MEMN_GLBAC_NUR_MASK (0x4U) +#define TRDC_MBC4_MBC_MEMN_GLBAC_NUR_SHIFT (2U) +/*! NUR - NonsecureUser Read + * 0b0..Read access is not allowed in Nonsecure User mode. + * 0b1..Read access is allowed in Nonsecure User mode. + */ +#define TRDC_MBC4_MBC_MEMN_GLBAC_NUR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_MEMN_GLBAC_NUR_SHIFT)) & TRDC_MBC4_MBC_MEMN_GLBAC_NUR_MASK) + +#define TRDC_MBC4_MBC_MEMN_GLBAC_NPX_MASK (0x10U) +#define TRDC_MBC4_MBC_MEMN_GLBAC_NPX_SHIFT (4U) +/*! NPX - NonsecurePriv Execute + * 0b0..Execute access is not allowed in Nonsecure Privilege mode. + * 0b1..Execute access is allowed in Nonsecure Privilege mode. + */ +#define TRDC_MBC4_MBC_MEMN_GLBAC_NPX(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_MEMN_GLBAC_NPX_SHIFT)) & TRDC_MBC4_MBC_MEMN_GLBAC_NPX_MASK) + +#define TRDC_MBC4_MBC_MEMN_GLBAC_NPW_MASK (0x20U) +#define TRDC_MBC4_MBC_MEMN_GLBAC_NPW_SHIFT (5U) +/*! NPW - NonsecurePriv Write + * 0b0..Write access is not allowed in Nonsecure Privilege mode. + * 0b1..Write access is allowed in Nonsecure Privilege mode. + */ +#define TRDC_MBC4_MBC_MEMN_GLBAC_NPW(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_MEMN_GLBAC_NPW_SHIFT)) & TRDC_MBC4_MBC_MEMN_GLBAC_NPW_MASK) + +#define TRDC_MBC4_MBC_MEMN_GLBAC_NPR_MASK (0x40U) +#define TRDC_MBC4_MBC_MEMN_GLBAC_NPR_SHIFT (6U) +/*! NPR - NonsecurePriv Read + * 0b0..Read access is not allowed in Nonsecure Privilege mode. + * 0b1..Read access is allowed in Nonsecure Privilege mode. + */ +#define TRDC_MBC4_MBC_MEMN_GLBAC_NPR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_MEMN_GLBAC_NPR_SHIFT)) & TRDC_MBC4_MBC_MEMN_GLBAC_NPR_MASK) + +#define TRDC_MBC4_MBC_MEMN_GLBAC_SUX_MASK (0x100U) +#define TRDC_MBC4_MBC_MEMN_GLBAC_SUX_SHIFT (8U) +/*! SUX - SecureUser Execute + * 0b0..Execute access is not allowed in Secure User mode. + * 0b1..Execute access is allowed in Secure User mode. + */ +#define TRDC_MBC4_MBC_MEMN_GLBAC_SUX(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_MEMN_GLBAC_SUX_SHIFT)) & TRDC_MBC4_MBC_MEMN_GLBAC_SUX_MASK) + +#define TRDC_MBC4_MBC_MEMN_GLBAC_SUW_MASK (0x200U) +#define TRDC_MBC4_MBC_MEMN_GLBAC_SUW_SHIFT (9U) +/*! SUW - SecureUser Write + * 0b0..Write access is not allowed in Secure User mode. + * 0b1..Write access is allowed in Secure User mode. + */ +#define TRDC_MBC4_MBC_MEMN_GLBAC_SUW(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_MEMN_GLBAC_SUW_SHIFT)) & TRDC_MBC4_MBC_MEMN_GLBAC_SUW_MASK) + +#define TRDC_MBC4_MBC_MEMN_GLBAC_SUR_MASK (0x400U) +#define TRDC_MBC4_MBC_MEMN_GLBAC_SUR_SHIFT (10U) +/*! SUR - SecureUser Read + * 0b0..Read access is not allowed in Secure User mode. + * 0b1..Read access is allowed in Secure User mode. + */ +#define TRDC_MBC4_MBC_MEMN_GLBAC_SUR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_MEMN_GLBAC_SUR_SHIFT)) & TRDC_MBC4_MBC_MEMN_GLBAC_SUR_MASK) + +#define TRDC_MBC4_MBC_MEMN_GLBAC_SPX_MASK (0x1000U) +#define TRDC_MBC4_MBC_MEMN_GLBAC_SPX_SHIFT (12U) +/*! SPX - SecurePriv Execute + * 0b0..Execute access is not allowed in Secure Privilege mode. + * 0b1..Execute access is allowed in Secure Privilege mode. + */ +#define TRDC_MBC4_MBC_MEMN_GLBAC_SPX(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_MEMN_GLBAC_SPX_SHIFT)) & TRDC_MBC4_MBC_MEMN_GLBAC_SPX_MASK) + +#define TRDC_MBC4_MBC_MEMN_GLBAC_SPW_MASK (0x2000U) +#define TRDC_MBC4_MBC_MEMN_GLBAC_SPW_SHIFT (13U) +/*! SPW - SecurePriv Write + * 0b0..Write access is not allowed in Secure Privilege mode. + * 0b1..Write access is allowed in Secure Privilege mode. + */ +#define TRDC_MBC4_MBC_MEMN_GLBAC_SPW(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_MEMN_GLBAC_SPW_SHIFT)) & TRDC_MBC4_MBC_MEMN_GLBAC_SPW_MASK) + +#define TRDC_MBC4_MBC_MEMN_GLBAC_SPR_MASK (0x4000U) +#define TRDC_MBC4_MBC_MEMN_GLBAC_SPR_SHIFT (14U) +/*! SPR - SecurePriv Read + * 0b0..Read access is not allowed in Secure Privilege mode. + * 0b1..Read access is allowed in Secure Privilege mode. + */ +#define TRDC_MBC4_MBC_MEMN_GLBAC_SPR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_MEMN_GLBAC_SPR_SHIFT)) & TRDC_MBC4_MBC_MEMN_GLBAC_SPR_MASK) + +#define TRDC_MBC4_MBC_MEMN_GLBAC_LK_MASK (0x80000000U) +#define TRDC_MBC4_MBC_MEMN_GLBAC_LK_SHIFT (31U) +/*! LK - LOCK + * 0b0..This register is not locked and can be altered. + * 0b1..This register is locked and cannot be altered. + */ +#define TRDC_MBC4_MBC_MEMN_GLBAC_LK(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_MEMN_GLBAC_LK_SHIFT)) & TRDC_MBC4_MBC_MEMN_GLBAC_LK_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MBC_MEMN_GLBAC */ +#define TRDC_MBC4_MBC_MEMN_GLBAC_COUNT (4U) + +/* The count of TRDC_MBC4_MBC_MEMN_GLBAC */ +#define TRDC_MBC4_MBC_MEMN_GLBAC_COUNT2 (8U) + +/*! @name MBC_DOM0_MEM0_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM0_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM0_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM0_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM0_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM0_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM0_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM0_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM0_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM0_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM0_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM0_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM0_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM0_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM0_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM0_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM0_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MBC_DOM0_MEM0_BLK_CFG_W */ +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_CFG_W_COUNT (4U) + +/* The count of TRDC_MBC4_MBC_DOM0_MEM0_BLK_CFG_W */ +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_CFG_W_COUNT2 (7U) + +/*! @name MBC_DOM0_MEM0_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ +/*! @{ */ + +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT0_MASK (0x1U) +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT0_SHIFT (0U) +/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT0_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT1_MASK (0x2U) +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT1_SHIFT (1U) +/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT1_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT2_MASK (0x4U) +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT2_SHIFT (2U) +/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT2_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT3_MASK (0x8U) +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT3_SHIFT (3U) +/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT3_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT4_MASK (0x10U) +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT4_SHIFT (4U) +/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT4_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT5_MASK (0x20U) +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT5_SHIFT (5U) +/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT5_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT6_MASK (0x40U) +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT6_SHIFT (6U) +/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT6_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT7_MASK (0x80U) +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT7_SHIFT (7U) +/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT7_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT8_MASK (0x100U) +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT8_SHIFT (8U) +/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT8_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT9_MASK (0x200U) +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT9_SHIFT (9U) +/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT9_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT10_MASK (0x400U) +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT10_SHIFT (10U) +/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT10_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT11_MASK (0x800U) +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT11_SHIFT (11U) +/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT11_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT12_MASK (0x1000U) +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT12_SHIFT (12U) +/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT12_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT13_MASK (0x2000U) +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT13_SHIFT (13U) +/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT13_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT14_MASK (0x4000U) +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT14_SHIFT (14U) +/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT14_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT15_MASK (0x8000U) +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT15_SHIFT (15U) +/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT15_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT16_MASK (0x10000U) +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT16_SHIFT (16U) +/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT16_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT17_MASK (0x20000U) +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT17_SHIFT (17U) +/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT17_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT18_MASK (0x40000U) +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT18_SHIFT (18U) +/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT18_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT19_MASK (0x80000U) +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT19_SHIFT (19U) +/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT19_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT20_MASK (0x100000U) +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT20_SHIFT (20U) +/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT20_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT21_MASK (0x200000U) +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT21_SHIFT (21U) +/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT21_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT22_MASK (0x400000U) +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT22_SHIFT (22U) +/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT22_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT23_MASK (0x800000U) +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT23_SHIFT (23U) +/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT23_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT24_MASK (0x1000000U) +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT24_SHIFT (24U) +/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT24_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT25_MASK (0x2000000U) +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT25_SHIFT (25U) +/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT25_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT26_MASK (0x4000000U) +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT26_SHIFT (26U) +/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT26_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT27_MASK (0x8000000U) +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT27_SHIFT (27U) +/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT27_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT28_MASK (0x10000000U) +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT28_SHIFT (28U) +/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT28_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT29_MASK (0x20000000U) +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT29_SHIFT (29U) +/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT29_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT30_MASK (0x40000000U) +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT30_SHIFT (30U) +/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT30_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT31_MASK (0x80000000U) +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT31_SHIFT (31U) +/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_BIT31_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W */ +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_COUNT (4U) + +/* The count of TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W */ +#define TRDC_MBC4_MBC_DOM0_MEM0_BLK_NSE_W_COUNT2 (2U) + +/*! @name MBC_DOM0_MEM1_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM1_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM1_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM1_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM1_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM1_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM1_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM1_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM1_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM1_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM1_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM1_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM1_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM1_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM1_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM1_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM1_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MBC_DOM0_MEM1_BLK_CFG_W */ +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_CFG_W_COUNT (4U) + +/* The count of TRDC_MBC4_MBC_DOM0_MEM1_BLK_CFG_W */ +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_CFG_W_COUNT2 (3U) + +/*! @name MBC_DOM0_MEM1_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ +/*! @{ */ + +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT0_MASK (0x1U) +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT0_SHIFT (0U) +/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT0_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT1_MASK (0x2U) +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT1_SHIFT (1U) +/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT1_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT2_MASK (0x4U) +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT2_SHIFT (2U) +/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT2_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT3_MASK (0x8U) +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT3_SHIFT (3U) +/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT3_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT4_MASK (0x10U) +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT4_SHIFT (4U) +/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT4_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT5_MASK (0x20U) +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT5_SHIFT (5U) +/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT5_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT6_MASK (0x40U) +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT6_SHIFT (6U) +/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT6_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT7_MASK (0x80U) +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT7_SHIFT (7U) +/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT7_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT8_MASK (0x100U) +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT8_SHIFT (8U) +/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT8_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT9_MASK (0x200U) +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT9_SHIFT (9U) +/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT9_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT10_MASK (0x400U) +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT10_SHIFT (10U) +/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT10_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT11_MASK (0x800U) +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT11_SHIFT (11U) +/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT11_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT12_MASK (0x1000U) +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT12_SHIFT (12U) +/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT12_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT13_MASK (0x2000U) +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT13_SHIFT (13U) +/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT13_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT14_MASK (0x4000U) +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT14_SHIFT (14U) +/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT14_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT15_MASK (0x8000U) +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT15_SHIFT (15U) +/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT15_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT16_MASK (0x10000U) +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT16_SHIFT (16U) +/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT16_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT17_MASK (0x20000U) +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT17_SHIFT (17U) +/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT17_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT18_MASK (0x40000U) +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT18_SHIFT (18U) +/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT18_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT19_MASK (0x80000U) +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT19_SHIFT (19U) +/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT19_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT20_MASK (0x100000U) +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT20_SHIFT (20U) +/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT20_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT21_MASK (0x200000U) +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT21_SHIFT (21U) +/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT21_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT22_MASK (0x400000U) +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT22_SHIFT (22U) +/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT22_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT23_MASK (0x800000U) +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT23_SHIFT (23U) +/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT23_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT24_MASK (0x1000000U) +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT24_SHIFT (24U) +/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT24_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT25_MASK (0x2000000U) +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT25_SHIFT (25U) +/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT25_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT26_MASK (0x4000000U) +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT26_SHIFT (26U) +/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT26_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT27_MASK (0x8000000U) +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT27_SHIFT (27U) +/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT27_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT28_MASK (0x10000000U) +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT28_SHIFT (28U) +/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT28_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT29_MASK (0x20000000U) +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT29_SHIFT (29U) +/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT29_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT30_MASK (0x40000000U) +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT30_SHIFT (30U) +/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT30_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT31_MASK (0x80000000U) +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT31_SHIFT (31U) +/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_BIT31_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W */ +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_COUNT (4U) + +/* The count of TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W */ +#define TRDC_MBC4_MBC_DOM0_MEM1_BLK_NSE_W_COUNT2 (1U) + +/*! @name MBC_DOM0_MEM2_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM2_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM2_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM2_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM2_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM2_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM2_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM2_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM2_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM2_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM2_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM2_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM2_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM2_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM2_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM2_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM2_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MBC_DOM0_MEM2_BLK_CFG_W */ +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_CFG_W_COUNT (4U) + +/* The count of TRDC_MBC4_MBC_DOM0_MEM2_BLK_CFG_W */ +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_CFG_W_COUNT2 (5U) + +/*! @name MBC_DOM0_MEM2_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ +/*! @{ */ + +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT0_MASK (0x1U) +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT0_SHIFT (0U) +/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT0_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT1_MASK (0x2U) +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT1_SHIFT (1U) +/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT1_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT2_MASK (0x4U) +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT2_SHIFT (2U) +/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT2_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT3_MASK (0x8U) +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT3_SHIFT (3U) +/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT3_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT4_MASK (0x10U) +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT4_SHIFT (4U) +/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT4_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT5_MASK (0x20U) +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT5_SHIFT (5U) +/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT5_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT6_MASK (0x40U) +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT6_SHIFT (6U) +/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT6_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT7_MASK (0x80U) +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT7_SHIFT (7U) +/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT7_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT8_MASK (0x100U) +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT8_SHIFT (8U) +/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT8_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT9_MASK (0x200U) +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT9_SHIFT (9U) +/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT9_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT10_MASK (0x400U) +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT10_SHIFT (10U) +/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT10_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT11_MASK (0x800U) +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT11_SHIFT (11U) +/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT11_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT12_MASK (0x1000U) +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT12_SHIFT (12U) +/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT12_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT13_MASK (0x2000U) +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT13_SHIFT (13U) +/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT13_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT14_MASK (0x4000U) +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT14_SHIFT (14U) +/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT14_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT15_MASK (0x8000U) +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT15_SHIFT (15U) +/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT15_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT16_MASK (0x10000U) +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT16_SHIFT (16U) +/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT16_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT17_MASK (0x20000U) +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT17_SHIFT (17U) +/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT17_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT18_MASK (0x40000U) +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT18_SHIFT (18U) +/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT18_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT19_MASK (0x80000U) +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT19_SHIFT (19U) +/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT19_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT20_MASK (0x100000U) +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT20_SHIFT (20U) +/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT20_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT21_MASK (0x200000U) +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT21_SHIFT (21U) +/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT21_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT22_MASK (0x400000U) +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT22_SHIFT (22U) +/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT22_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT23_MASK (0x800000U) +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT23_SHIFT (23U) +/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT23_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT24_MASK (0x1000000U) +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT24_SHIFT (24U) +/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT24_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT25_MASK (0x2000000U) +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT25_SHIFT (25U) +/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT25_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT26_MASK (0x4000000U) +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT26_SHIFT (26U) +/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT26_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT27_MASK (0x8000000U) +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT27_SHIFT (27U) +/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT27_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT28_MASK (0x10000000U) +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT28_SHIFT (28U) +/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT28_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT29_MASK (0x20000000U) +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT29_SHIFT (29U) +/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT29_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT30_MASK (0x40000000U) +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT30_SHIFT (30U) +/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT30_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT31_MASK (0x80000000U) +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT31_SHIFT (31U) +/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_BIT31_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W */ +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_COUNT (4U) + +/* The count of TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W */ +#define TRDC_MBC4_MBC_DOM0_MEM2_BLK_NSE_W_COUNT2 (2U) + +/*! @name MBC_DOM0_MEM3_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM3_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM3_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM3_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM3_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM3_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM3_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM3_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM3_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM3_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM3_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM3_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM3_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM3_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM3_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM3_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM3_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MBC_DOM0_MEM3_BLK_CFG_W */ +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_CFG_W_COUNT (4U) + +/* The count of TRDC_MBC4_MBC_DOM0_MEM3_BLK_CFG_W */ +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_CFG_W_COUNT2 (6U) + +/*! @name MBC_DOM0_MEM3_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ +/*! @{ */ + +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT0_MASK (0x1U) +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT0_SHIFT (0U) +/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT0_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT1_MASK (0x2U) +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT1_SHIFT (1U) +/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT1_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT2_MASK (0x4U) +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT2_SHIFT (2U) +/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT2_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT3_MASK (0x8U) +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT3_SHIFT (3U) +/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT3_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT4_MASK (0x10U) +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT4_SHIFT (4U) +/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT4_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT5_MASK (0x20U) +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT5_SHIFT (5U) +/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT5_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT6_MASK (0x40U) +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT6_SHIFT (6U) +/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT6_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT7_MASK (0x80U) +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT7_SHIFT (7U) +/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT7_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT8_MASK (0x100U) +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT8_SHIFT (8U) +/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT8_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT9_MASK (0x200U) +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT9_SHIFT (9U) +/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT9_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT10_MASK (0x400U) +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT10_SHIFT (10U) +/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT10_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT11_MASK (0x800U) +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT11_SHIFT (11U) +/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT11_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT12_MASK (0x1000U) +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT12_SHIFT (12U) +/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT12_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT13_MASK (0x2000U) +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT13_SHIFT (13U) +/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT13_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT14_MASK (0x4000U) +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT14_SHIFT (14U) +/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT14_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT15_MASK (0x8000U) +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT15_SHIFT (15U) +/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT15_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT16_MASK (0x10000U) +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT16_SHIFT (16U) +/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT16_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT17_MASK (0x20000U) +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT17_SHIFT (17U) +/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT17_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT18_MASK (0x40000U) +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT18_SHIFT (18U) +/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT18_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT19_MASK (0x80000U) +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT19_SHIFT (19U) +/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT19_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT20_MASK (0x100000U) +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT20_SHIFT (20U) +/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT20_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT21_MASK (0x200000U) +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT21_SHIFT (21U) +/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT21_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT22_MASK (0x400000U) +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT22_SHIFT (22U) +/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT22_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT23_MASK (0x800000U) +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT23_SHIFT (23U) +/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT23_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT24_MASK (0x1000000U) +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT24_SHIFT (24U) +/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT24_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT25_MASK (0x2000000U) +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT25_SHIFT (25U) +/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT25_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT26_MASK (0x4000000U) +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT26_SHIFT (26U) +/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT26_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT27_MASK (0x8000000U) +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT27_SHIFT (27U) +/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT27_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT28_MASK (0x10000000U) +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT28_SHIFT (28U) +/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT28_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT29_MASK (0x20000000U) +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT29_SHIFT (29U) +/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT29_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT30_MASK (0x40000000U) +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT30_SHIFT (30U) +/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT30_MASK) + +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT31_MASK (0x80000000U) +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT31_SHIFT (31U) +/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_BIT31_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W */ +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_COUNT (4U) + +/* The count of TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W */ +#define TRDC_MBC4_MBC_DOM0_MEM3_BLK_NSE_W_COUNT2 (2U) + +/*! @name MBC_DOM1_MEM0_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM0_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM0_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM0_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM0_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM0_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM0_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM0_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM0_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM0_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM0_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM0_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM0_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM0_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM0_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM0_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM0_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MBC_DOM1_MEM0_BLK_CFG_W */ +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_CFG_W_COUNT (4U) + +/* The count of TRDC_MBC4_MBC_DOM1_MEM0_BLK_CFG_W */ +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_CFG_W_COUNT2 (7U) + +/*! @name MBC_DOM1_MEM0_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ +/*! @{ */ + +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT0_MASK (0x1U) +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT0_SHIFT (0U) +/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT0_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT1_MASK (0x2U) +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT1_SHIFT (1U) +/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT1_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT2_MASK (0x4U) +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT2_SHIFT (2U) +/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT2_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT3_MASK (0x8U) +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT3_SHIFT (3U) +/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT3_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT4_MASK (0x10U) +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT4_SHIFT (4U) +/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT4_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT5_MASK (0x20U) +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT5_SHIFT (5U) +/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT5_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT6_MASK (0x40U) +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT6_SHIFT (6U) +/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT6_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT7_MASK (0x80U) +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT7_SHIFT (7U) +/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT7_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT8_MASK (0x100U) +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT8_SHIFT (8U) +/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT8_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT9_MASK (0x200U) +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT9_SHIFT (9U) +/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT9_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT10_MASK (0x400U) +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT10_SHIFT (10U) +/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT10_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT11_MASK (0x800U) +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT11_SHIFT (11U) +/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT11_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT12_MASK (0x1000U) +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT12_SHIFT (12U) +/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT12_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT13_MASK (0x2000U) +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT13_SHIFT (13U) +/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT13_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT14_MASK (0x4000U) +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT14_SHIFT (14U) +/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT14_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT15_MASK (0x8000U) +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT15_SHIFT (15U) +/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT15_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT16_MASK (0x10000U) +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT16_SHIFT (16U) +/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT16_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT17_MASK (0x20000U) +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT17_SHIFT (17U) +/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT17_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT18_MASK (0x40000U) +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT18_SHIFT (18U) +/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT18_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT19_MASK (0x80000U) +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT19_SHIFT (19U) +/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT19_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT20_MASK (0x100000U) +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT20_SHIFT (20U) +/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT20_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT21_MASK (0x200000U) +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT21_SHIFT (21U) +/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT21_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT22_MASK (0x400000U) +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT22_SHIFT (22U) +/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT22_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT23_MASK (0x800000U) +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT23_SHIFT (23U) +/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT23_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT24_MASK (0x1000000U) +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT24_SHIFT (24U) +/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT24_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT25_MASK (0x2000000U) +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT25_SHIFT (25U) +/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT25_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT26_MASK (0x4000000U) +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT26_SHIFT (26U) +/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT26_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT27_MASK (0x8000000U) +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT27_SHIFT (27U) +/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT27_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT28_MASK (0x10000000U) +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT28_SHIFT (28U) +/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT28_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT29_MASK (0x20000000U) +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT29_SHIFT (29U) +/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT29_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT30_MASK (0x40000000U) +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT30_SHIFT (30U) +/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT30_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT31_MASK (0x80000000U) +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT31_SHIFT (31U) +/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_BIT31_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W */ +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_COUNT (4U) + +/* The count of TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W */ +#define TRDC_MBC4_MBC_DOM1_MEM0_BLK_NSE_W_COUNT2 (2U) + +/*! @name MBC_DOM1_MEM1_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM1_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM1_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM1_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM1_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM1_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM1_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM1_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM1_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM1_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM1_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM1_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM1_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM1_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM1_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM1_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM1_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MBC_DOM1_MEM1_BLK_CFG_W */ +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_CFG_W_COUNT (4U) + +/* The count of TRDC_MBC4_MBC_DOM1_MEM1_BLK_CFG_W */ +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_CFG_W_COUNT2 (3U) + +/*! @name MBC_DOM1_MEM1_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ +/*! @{ */ + +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT0_MASK (0x1U) +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT0_SHIFT (0U) +/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT0_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT1_MASK (0x2U) +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT1_SHIFT (1U) +/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT1_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT2_MASK (0x4U) +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT2_SHIFT (2U) +/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT2_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT3_MASK (0x8U) +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT3_SHIFT (3U) +/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT3_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT4_MASK (0x10U) +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT4_SHIFT (4U) +/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT4_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT5_MASK (0x20U) +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT5_SHIFT (5U) +/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT5_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT6_MASK (0x40U) +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT6_SHIFT (6U) +/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT6_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT7_MASK (0x80U) +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT7_SHIFT (7U) +/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT7_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT8_MASK (0x100U) +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT8_SHIFT (8U) +/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT8_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT9_MASK (0x200U) +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT9_SHIFT (9U) +/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT9_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT10_MASK (0x400U) +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT10_SHIFT (10U) +/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT10_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT11_MASK (0x800U) +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT11_SHIFT (11U) +/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT11_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT12_MASK (0x1000U) +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT12_SHIFT (12U) +/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT12_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT13_MASK (0x2000U) +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT13_SHIFT (13U) +/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT13_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT14_MASK (0x4000U) +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT14_SHIFT (14U) +/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT14_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT15_MASK (0x8000U) +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT15_SHIFT (15U) +/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT15_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT16_MASK (0x10000U) +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT16_SHIFT (16U) +/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT16_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT17_MASK (0x20000U) +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT17_SHIFT (17U) +/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT17_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT18_MASK (0x40000U) +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT18_SHIFT (18U) +/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT18_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT19_MASK (0x80000U) +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT19_SHIFT (19U) +/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT19_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT20_MASK (0x100000U) +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT20_SHIFT (20U) +/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT20_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT21_MASK (0x200000U) +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT21_SHIFT (21U) +/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT21_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT22_MASK (0x400000U) +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT22_SHIFT (22U) +/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT22_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT23_MASK (0x800000U) +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT23_SHIFT (23U) +/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT23_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT24_MASK (0x1000000U) +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT24_SHIFT (24U) +/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT24_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT25_MASK (0x2000000U) +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT25_SHIFT (25U) +/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT25_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT26_MASK (0x4000000U) +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT26_SHIFT (26U) +/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT26_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT27_MASK (0x8000000U) +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT27_SHIFT (27U) +/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT27_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT28_MASK (0x10000000U) +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT28_SHIFT (28U) +/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT28_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT29_MASK (0x20000000U) +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT29_SHIFT (29U) +/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT29_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT30_MASK (0x40000000U) +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT30_SHIFT (30U) +/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT30_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT31_MASK (0x80000000U) +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT31_SHIFT (31U) +/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_BIT31_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W */ +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_COUNT (4U) + +/* The count of TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W */ +#define TRDC_MBC4_MBC_DOM1_MEM1_BLK_NSE_W_COUNT2 (1U) + +/*! @name MBC_DOM1_MEM2_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM2_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM2_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM2_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM2_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM2_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM2_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM2_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM2_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM2_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM2_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM2_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM2_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM2_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM2_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM2_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM2_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MBC_DOM1_MEM2_BLK_CFG_W */ +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_CFG_W_COUNT (4U) + +/* The count of TRDC_MBC4_MBC_DOM1_MEM2_BLK_CFG_W */ +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_CFG_W_COUNT2 (5U) + +/*! @name MBC_DOM1_MEM2_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ +/*! @{ */ + +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT0_MASK (0x1U) +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT0_SHIFT (0U) +/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT0_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT1_MASK (0x2U) +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT1_SHIFT (1U) +/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT1_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT2_MASK (0x4U) +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT2_SHIFT (2U) +/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT2_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT3_MASK (0x8U) +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT3_SHIFT (3U) +/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT3_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT4_MASK (0x10U) +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT4_SHIFT (4U) +/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT4_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT5_MASK (0x20U) +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT5_SHIFT (5U) +/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT5_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT6_MASK (0x40U) +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT6_SHIFT (6U) +/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT6_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT7_MASK (0x80U) +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT7_SHIFT (7U) +/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT7_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT8_MASK (0x100U) +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT8_SHIFT (8U) +/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT8_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT9_MASK (0x200U) +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT9_SHIFT (9U) +/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT9_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT10_MASK (0x400U) +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT10_SHIFT (10U) +/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT10_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT11_MASK (0x800U) +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT11_SHIFT (11U) +/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT11_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT12_MASK (0x1000U) +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT12_SHIFT (12U) +/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT12_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT13_MASK (0x2000U) +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT13_SHIFT (13U) +/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT13_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT14_MASK (0x4000U) +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT14_SHIFT (14U) +/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT14_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT15_MASK (0x8000U) +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT15_SHIFT (15U) +/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT15_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT16_MASK (0x10000U) +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT16_SHIFT (16U) +/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT16_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT17_MASK (0x20000U) +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT17_SHIFT (17U) +/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT17_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT18_MASK (0x40000U) +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT18_SHIFT (18U) +/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT18_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT19_MASK (0x80000U) +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT19_SHIFT (19U) +/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT19_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT20_MASK (0x100000U) +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT20_SHIFT (20U) +/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT20_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT21_MASK (0x200000U) +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT21_SHIFT (21U) +/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT21_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT22_MASK (0x400000U) +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT22_SHIFT (22U) +/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT22_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT23_MASK (0x800000U) +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT23_SHIFT (23U) +/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT23_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT24_MASK (0x1000000U) +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT24_SHIFT (24U) +/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT24_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT25_MASK (0x2000000U) +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT25_SHIFT (25U) +/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT25_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT26_MASK (0x4000000U) +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT26_SHIFT (26U) +/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT26_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT27_MASK (0x8000000U) +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT27_SHIFT (27U) +/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT27_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT28_MASK (0x10000000U) +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT28_SHIFT (28U) +/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT28_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT29_MASK (0x20000000U) +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT29_SHIFT (29U) +/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT29_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT30_MASK (0x40000000U) +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT30_SHIFT (30U) +/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT30_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT31_MASK (0x80000000U) +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT31_SHIFT (31U) +/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_BIT31_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W */ +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_COUNT (4U) + +/* The count of TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W */ +#define TRDC_MBC4_MBC_DOM1_MEM2_BLK_NSE_W_COUNT2 (2U) + +/*! @name MBC_DOM1_MEM3_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM3_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM3_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM3_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM3_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM3_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM3_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM3_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM3_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM3_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM3_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM3_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM3_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM3_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM3_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM3_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM3_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MBC_DOM1_MEM3_BLK_CFG_W */ +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_CFG_W_COUNT (4U) + +/* The count of TRDC_MBC4_MBC_DOM1_MEM3_BLK_CFG_W */ +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_CFG_W_COUNT2 (6U) + +/*! @name MBC_DOM1_MEM3_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ +/*! @{ */ + +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT0_MASK (0x1U) +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT0_SHIFT (0U) +/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT0_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT1_MASK (0x2U) +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT1_SHIFT (1U) +/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT1_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT2_MASK (0x4U) +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT2_SHIFT (2U) +/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT2_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT3_MASK (0x8U) +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT3_SHIFT (3U) +/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT3_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT4_MASK (0x10U) +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT4_SHIFT (4U) +/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT4_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT5_MASK (0x20U) +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT5_SHIFT (5U) +/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT5_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT6_MASK (0x40U) +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT6_SHIFT (6U) +/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT6_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT7_MASK (0x80U) +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT7_SHIFT (7U) +/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT7_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT8_MASK (0x100U) +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT8_SHIFT (8U) +/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT8_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT9_MASK (0x200U) +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT9_SHIFT (9U) +/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT9_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT10_MASK (0x400U) +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT10_SHIFT (10U) +/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT10_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT11_MASK (0x800U) +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT11_SHIFT (11U) +/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT11_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT12_MASK (0x1000U) +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT12_SHIFT (12U) +/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT12_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT13_MASK (0x2000U) +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT13_SHIFT (13U) +/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT13_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT14_MASK (0x4000U) +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT14_SHIFT (14U) +/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT14_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT15_MASK (0x8000U) +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT15_SHIFT (15U) +/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT15_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT16_MASK (0x10000U) +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT16_SHIFT (16U) +/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT16_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT17_MASK (0x20000U) +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT17_SHIFT (17U) +/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT17_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT18_MASK (0x40000U) +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT18_SHIFT (18U) +/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT18_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT19_MASK (0x80000U) +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT19_SHIFT (19U) +/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT19_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT20_MASK (0x100000U) +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT20_SHIFT (20U) +/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT20_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT21_MASK (0x200000U) +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT21_SHIFT (21U) +/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT21_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT22_MASK (0x400000U) +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT22_SHIFT (22U) +/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT22_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT23_MASK (0x800000U) +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT23_SHIFT (23U) +/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT23_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT24_MASK (0x1000000U) +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT24_SHIFT (24U) +/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT24_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT25_MASK (0x2000000U) +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT25_SHIFT (25U) +/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT25_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT26_MASK (0x4000000U) +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT26_SHIFT (26U) +/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT26_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT27_MASK (0x8000000U) +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT27_SHIFT (27U) +/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT27_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT28_MASK (0x10000000U) +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT28_SHIFT (28U) +/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT28_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT29_MASK (0x20000000U) +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT29_SHIFT (29U) +/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT29_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT30_MASK (0x40000000U) +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT30_SHIFT (30U) +/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT30_MASK) + +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT31_MASK (0x80000000U) +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT31_SHIFT (31U) +/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_BIT31_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W */ +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_COUNT (4U) + +/* The count of TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W */ +#define TRDC_MBC4_MBC_DOM1_MEM3_BLK_NSE_W_COUNT2 (2U) + +/*! @name MBC_DOM2_MEM0_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM0_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM0_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM0_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM0_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM0_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM0_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM0_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM0_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM0_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM0_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM0_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM0_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM0_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM0_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM0_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM0_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MBC_DOM2_MEM0_BLK_CFG_W */ +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_CFG_W_COUNT (4U) + +/* The count of TRDC_MBC4_MBC_DOM2_MEM0_BLK_CFG_W */ +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_CFG_W_COUNT2 (7U) + +/*! @name MBC_DOM2_MEM0_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ +/*! @{ */ + +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT0_MASK (0x1U) +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT0_SHIFT (0U) +/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT0_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT1_MASK (0x2U) +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT1_SHIFT (1U) +/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT1_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT2_MASK (0x4U) +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT2_SHIFT (2U) +/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT2_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT3_MASK (0x8U) +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT3_SHIFT (3U) +/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT3_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT4_MASK (0x10U) +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT4_SHIFT (4U) +/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT4_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT5_MASK (0x20U) +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT5_SHIFT (5U) +/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT5_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT6_MASK (0x40U) +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT6_SHIFT (6U) +/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT6_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT7_MASK (0x80U) +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT7_SHIFT (7U) +/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT7_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT8_MASK (0x100U) +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT8_SHIFT (8U) +/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT8_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT9_MASK (0x200U) +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT9_SHIFT (9U) +/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT9_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT10_MASK (0x400U) +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT10_SHIFT (10U) +/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT10_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT11_MASK (0x800U) +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT11_SHIFT (11U) +/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT11_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT12_MASK (0x1000U) +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT12_SHIFT (12U) +/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT12_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT13_MASK (0x2000U) +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT13_SHIFT (13U) +/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT13_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT14_MASK (0x4000U) +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT14_SHIFT (14U) +/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT14_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT15_MASK (0x8000U) +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT15_SHIFT (15U) +/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT15_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT16_MASK (0x10000U) +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT16_SHIFT (16U) +/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT16_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT17_MASK (0x20000U) +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT17_SHIFT (17U) +/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT17_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT18_MASK (0x40000U) +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT18_SHIFT (18U) +/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT18_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT19_MASK (0x80000U) +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT19_SHIFT (19U) +/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT19_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT20_MASK (0x100000U) +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT20_SHIFT (20U) +/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT20_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT21_MASK (0x200000U) +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT21_SHIFT (21U) +/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT21_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT22_MASK (0x400000U) +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT22_SHIFT (22U) +/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT22_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT23_MASK (0x800000U) +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT23_SHIFT (23U) +/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT23_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT24_MASK (0x1000000U) +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT24_SHIFT (24U) +/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT24_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT25_MASK (0x2000000U) +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT25_SHIFT (25U) +/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT25_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT26_MASK (0x4000000U) +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT26_SHIFT (26U) +/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT26_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT27_MASK (0x8000000U) +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT27_SHIFT (27U) +/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT27_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT28_MASK (0x10000000U) +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT28_SHIFT (28U) +/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT28_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT29_MASK (0x20000000U) +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT29_SHIFT (29U) +/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT29_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT30_MASK (0x40000000U) +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT30_SHIFT (30U) +/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT30_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT31_MASK (0x80000000U) +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT31_SHIFT (31U) +/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_BIT31_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W */ +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_COUNT (4U) + +/* The count of TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W */ +#define TRDC_MBC4_MBC_DOM2_MEM0_BLK_NSE_W_COUNT2 (2U) + +/*! @name MBC_DOM2_MEM1_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM1_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM1_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM1_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM1_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM1_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM1_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM1_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM1_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM1_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM1_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM1_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM1_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM1_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM1_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM1_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM1_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MBC_DOM2_MEM1_BLK_CFG_W */ +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_CFG_W_COUNT (4U) + +/* The count of TRDC_MBC4_MBC_DOM2_MEM1_BLK_CFG_W */ +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_CFG_W_COUNT2 (3U) + +/*! @name MBC_DOM2_MEM1_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ +/*! @{ */ + +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT0_MASK (0x1U) +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT0_SHIFT (0U) +/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT0_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT1_MASK (0x2U) +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT1_SHIFT (1U) +/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT1_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT2_MASK (0x4U) +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT2_SHIFT (2U) +/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT2_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT3_MASK (0x8U) +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT3_SHIFT (3U) +/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT3_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT4_MASK (0x10U) +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT4_SHIFT (4U) +/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT4_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT5_MASK (0x20U) +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT5_SHIFT (5U) +/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT5_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT6_MASK (0x40U) +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT6_SHIFT (6U) +/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT6_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT7_MASK (0x80U) +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT7_SHIFT (7U) +/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT7_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT8_MASK (0x100U) +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT8_SHIFT (8U) +/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT8_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT9_MASK (0x200U) +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT9_SHIFT (9U) +/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT9_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT10_MASK (0x400U) +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT10_SHIFT (10U) +/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT10_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT11_MASK (0x800U) +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT11_SHIFT (11U) +/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT11_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT12_MASK (0x1000U) +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT12_SHIFT (12U) +/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT12_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT13_MASK (0x2000U) +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT13_SHIFT (13U) +/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT13_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT14_MASK (0x4000U) +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT14_SHIFT (14U) +/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT14_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT15_MASK (0x8000U) +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT15_SHIFT (15U) +/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT15_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT16_MASK (0x10000U) +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT16_SHIFT (16U) +/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT16_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT17_MASK (0x20000U) +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT17_SHIFT (17U) +/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT17_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT18_MASK (0x40000U) +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT18_SHIFT (18U) +/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT18_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT19_MASK (0x80000U) +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT19_SHIFT (19U) +/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT19_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT20_MASK (0x100000U) +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT20_SHIFT (20U) +/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT20_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT21_MASK (0x200000U) +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT21_SHIFT (21U) +/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT21_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT22_MASK (0x400000U) +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT22_SHIFT (22U) +/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT22_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT23_MASK (0x800000U) +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT23_SHIFT (23U) +/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT23_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT24_MASK (0x1000000U) +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT24_SHIFT (24U) +/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT24_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT25_MASK (0x2000000U) +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT25_SHIFT (25U) +/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT25_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT26_MASK (0x4000000U) +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT26_SHIFT (26U) +/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT26_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT27_MASK (0x8000000U) +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT27_SHIFT (27U) +/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT27_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT28_MASK (0x10000000U) +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT28_SHIFT (28U) +/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT28_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT29_MASK (0x20000000U) +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT29_SHIFT (29U) +/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT29_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT30_MASK (0x40000000U) +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT30_SHIFT (30U) +/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT30_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT31_MASK (0x80000000U) +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT31_SHIFT (31U) +/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_BIT31_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W */ +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_COUNT (4U) + +/* The count of TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W */ +#define TRDC_MBC4_MBC_DOM2_MEM1_BLK_NSE_W_COUNT2 (1U) + +/*! @name MBC_DOM2_MEM2_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM2_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM2_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM2_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM2_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM2_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM2_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM2_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM2_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM2_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM2_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM2_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM2_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM2_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM2_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM2_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM2_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MBC_DOM2_MEM2_BLK_CFG_W */ +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_CFG_W_COUNT (4U) + +/* The count of TRDC_MBC4_MBC_DOM2_MEM2_BLK_CFG_W */ +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_CFG_W_COUNT2 (5U) + +/*! @name MBC_DOM2_MEM2_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ +/*! @{ */ + +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT0_MASK (0x1U) +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT0_SHIFT (0U) +/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT0_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT1_MASK (0x2U) +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT1_SHIFT (1U) +/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT1_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT2_MASK (0x4U) +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT2_SHIFT (2U) +/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT2_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT3_MASK (0x8U) +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT3_SHIFT (3U) +/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT3_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT4_MASK (0x10U) +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT4_SHIFT (4U) +/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT4_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT5_MASK (0x20U) +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT5_SHIFT (5U) +/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT5_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT6_MASK (0x40U) +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT6_SHIFT (6U) +/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT6_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT7_MASK (0x80U) +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT7_SHIFT (7U) +/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT7_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT8_MASK (0x100U) +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT8_SHIFT (8U) +/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT8_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT9_MASK (0x200U) +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT9_SHIFT (9U) +/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT9_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT10_MASK (0x400U) +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT10_SHIFT (10U) +/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT10_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT11_MASK (0x800U) +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT11_SHIFT (11U) +/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT11_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT12_MASK (0x1000U) +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT12_SHIFT (12U) +/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT12_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT13_MASK (0x2000U) +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT13_SHIFT (13U) +/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT13_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT14_MASK (0x4000U) +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT14_SHIFT (14U) +/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT14_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT15_MASK (0x8000U) +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT15_SHIFT (15U) +/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT15_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT16_MASK (0x10000U) +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT16_SHIFT (16U) +/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT16_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT17_MASK (0x20000U) +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT17_SHIFT (17U) +/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT17_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT18_MASK (0x40000U) +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT18_SHIFT (18U) +/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT18_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT19_MASK (0x80000U) +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT19_SHIFT (19U) +/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT19_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT20_MASK (0x100000U) +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT20_SHIFT (20U) +/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT20_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT21_MASK (0x200000U) +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT21_SHIFT (21U) +/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT21_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT22_MASK (0x400000U) +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT22_SHIFT (22U) +/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT22_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT23_MASK (0x800000U) +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT23_SHIFT (23U) +/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT23_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT24_MASK (0x1000000U) +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT24_SHIFT (24U) +/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT24_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT25_MASK (0x2000000U) +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT25_SHIFT (25U) +/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT25_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT26_MASK (0x4000000U) +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT26_SHIFT (26U) +/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT26_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT27_MASK (0x8000000U) +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT27_SHIFT (27U) +/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT27_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT28_MASK (0x10000000U) +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT28_SHIFT (28U) +/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT28_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT29_MASK (0x20000000U) +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT29_SHIFT (29U) +/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT29_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT30_MASK (0x40000000U) +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT30_SHIFT (30U) +/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT30_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT31_MASK (0x80000000U) +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT31_SHIFT (31U) +/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_BIT31_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W */ +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_COUNT (4U) + +/* The count of TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W */ +#define TRDC_MBC4_MBC_DOM2_MEM2_BLK_NSE_W_COUNT2 (2U) + +/*! @name MBC_DOM2_MEM3_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM3_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM3_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM3_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM3_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM3_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM3_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM3_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM3_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM3_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM3_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM3_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM3_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM3_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM3_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM3_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM3_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MBC_DOM2_MEM3_BLK_CFG_W */ +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_CFG_W_COUNT (4U) + +/* The count of TRDC_MBC4_MBC_DOM2_MEM3_BLK_CFG_W */ +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_CFG_W_COUNT2 (6U) + +/*! @name MBC_DOM2_MEM3_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ +/*! @{ */ + +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT0_MASK (0x1U) +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT0_SHIFT (0U) +/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT0_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT1_MASK (0x2U) +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT1_SHIFT (1U) +/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT1_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT2_MASK (0x4U) +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT2_SHIFT (2U) +/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT2_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT3_MASK (0x8U) +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT3_SHIFT (3U) +/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT3_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT4_MASK (0x10U) +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT4_SHIFT (4U) +/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT4_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT5_MASK (0x20U) +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT5_SHIFT (5U) +/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT5_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT6_MASK (0x40U) +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT6_SHIFT (6U) +/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT6_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT7_MASK (0x80U) +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT7_SHIFT (7U) +/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT7_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT8_MASK (0x100U) +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT8_SHIFT (8U) +/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT8_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT9_MASK (0x200U) +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT9_SHIFT (9U) +/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT9_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT10_MASK (0x400U) +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT10_SHIFT (10U) +/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT10_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT11_MASK (0x800U) +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT11_SHIFT (11U) +/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT11_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT12_MASK (0x1000U) +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT12_SHIFT (12U) +/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT12_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT13_MASK (0x2000U) +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT13_SHIFT (13U) +/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT13_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT14_MASK (0x4000U) +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT14_SHIFT (14U) +/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT14_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT15_MASK (0x8000U) +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT15_SHIFT (15U) +/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT15_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT16_MASK (0x10000U) +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT16_SHIFT (16U) +/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT16_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT17_MASK (0x20000U) +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT17_SHIFT (17U) +/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT17_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT18_MASK (0x40000U) +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT18_SHIFT (18U) +/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT18_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT19_MASK (0x80000U) +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT19_SHIFT (19U) +/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT19_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT20_MASK (0x100000U) +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT20_SHIFT (20U) +/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT20_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT21_MASK (0x200000U) +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT21_SHIFT (21U) +/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT21_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT22_MASK (0x400000U) +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT22_SHIFT (22U) +/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT22_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT23_MASK (0x800000U) +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT23_SHIFT (23U) +/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT23_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT24_MASK (0x1000000U) +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT24_SHIFT (24U) +/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT24_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT25_MASK (0x2000000U) +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT25_SHIFT (25U) +/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT25_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT26_MASK (0x4000000U) +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT26_SHIFT (26U) +/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT26_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT27_MASK (0x8000000U) +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT27_SHIFT (27U) +/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT27_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT28_MASK (0x10000000U) +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT28_SHIFT (28U) +/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT28_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT29_MASK (0x20000000U) +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT29_SHIFT (29U) +/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT29_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT30_MASK (0x40000000U) +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT30_SHIFT (30U) +/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT30_MASK) + +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT31_MASK (0x80000000U) +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT31_SHIFT (31U) +/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_BIT31_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W */ +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_COUNT (4U) + +/* The count of TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W */ +#define TRDC_MBC4_MBC_DOM2_MEM3_BLK_NSE_W_COUNT2 (2U) + +/*! @name MBC_DOM3_MEM0_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM0_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM0_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM0_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM0_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM0_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM0_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM0_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM0_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM0_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM0_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM0_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM0_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM0_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM0_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM0_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM0_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM0_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM0_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM0_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM0_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM0_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM0_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM0_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM0_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM0_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM0_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM0_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM0_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM0_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM0_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM0_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM0_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MBC_DOM3_MEM0_BLK_CFG_W */ +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_CFG_W_COUNT (4U) + +/* The count of TRDC_MBC4_MBC_DOM3_MEM0_BLK_CFG_W */ +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_CFG_W_COUNT2 (7U) + +/*! @name MBC_DOM3_MEM0_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ +/*! @{ */ + +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT0_MASK (0x1U) +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT0_SHIFT (0U) +/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT0_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT1_MASK (0x2U) +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT1_SHIFT (1U) +/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT1_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT2_MASK (0x4U) +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT2_SHIFT (2U) +/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT2_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT3_MASK (0x8U) +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT3_SHIFT (3U) +/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT3_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT4_MASK (0x10U) +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT4_SHIFT (4U) +/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT4_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT5_MASK (0x20U) +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT5_SHIFT (5U) +/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT5_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT6_MASK (0x40U) +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT6_SHIFT (6U) +/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT6_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT7_MASK (0x80U) +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT7_SHIFT (7U) +/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT7_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT8_MASK (0x100U) +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT8_SHIFT (8U) +/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT8_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT9_MASK (0x200U) +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT9_SHIFT (9U) +/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT9_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT10_MASK (0x400U) +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT10_SHIFT (10U) +/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT10_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT11_MASK (0x800U) +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT11_SHIFT (11U) +/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT11_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT12_MASK (0x1000U) +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT12_SHIFT (12U) +/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT12_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT13_MASK (0x2000U) +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT13_SHIFT (13U) +/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT13_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT14_MASK (0x4000U) +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT14_SHIFT (14U) +/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT14_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT15_MASK (0x8000U) +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT15_SHIFT (15U) +/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT15_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT16_MASK (0x10000U) +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT16_SHIFT (16U) +/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT16_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT17_MASK (0x20000U) +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT17_SHIFT (17U) +/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT17_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT18_MASK (0x40000U) +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT18_SHIFT (18U) +/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT18_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT19_MASK (0x80000U) +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT19_SHIFT (19U) +/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT19_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT20_MASK (0x100000U) +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT20_SHIFT (20U) +/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT20_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT21_MASK (0x200000U) +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT21_SHIFT (21U) +/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT21_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT22_MASK (0x400000U) +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT22_SHIFT (22U) +/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT22_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT23_MASK (0x800000U) +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT23_SHIFT (23U) +/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT23_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT24_MASK (0x1000000U) +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT24_SHIFT (24U) +/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT24_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT25_MASK (0x2000000U) +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT25_SHIFT (25U) +/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT25_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT26_MASK (0x4000000U) +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT26_SHIFT (26U) +/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT26_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT27_MASK (0x8000000U) +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT27_SHIFT (27U) +/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT27_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT28_MASK (0x10000000U) +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT28_SHIFT (28U) +/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT28_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT29_MASK (0x20000000U) +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT29_SHIFT (29U) +/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT29_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT30_MASK (0x40000000U) +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT30_SHIFT (30U) +/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT30_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT31_MASK (0x80000000U) +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT31_SHIFT (31U) +/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_BIT31_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W */ +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_COUNT (4U) + +/* The count of TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W */ +#define TRDC_MBC4_MBC_DOM3_MEM0_BLK_NSE_W_COUNT2 (2U) + +/*! @name MBC_DOM3_MEM1_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM1_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM1_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM1_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM1_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM1_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM1_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM1_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM1_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM1_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM1_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM1_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM1_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM1_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM1_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM1_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM1_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM1_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM1_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM1_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM1_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM1_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM1_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM1_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM1_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM1_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM1_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM1_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM1_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM1_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM1_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM1_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM1_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MBC_DOM3_MEM1_BLK_CFG_W */ +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_CFG_W_COUNT (4U) + +/* The count of TRDC_MBC4_MBC_DOM3_MEM1_BLK_CFG_W */ +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_CFG_W_COUNT2 (3U) + +/*! @name MBC_DOM3_MEM1_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ +/*! @{ */ + +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT0_MASK (0x1U) +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT0_SHIFT (0U) +/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT0_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT1_MASK (0x2U) +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT1_SHIFT (1U) +/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT1_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT2_MASK (0x4U) +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT2_SHIFT (2U) +/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT2_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT3_MASK (0x8U) +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT3_SHIFT (3U) +/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT3_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT4_MASK (0x10U) +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT4_SHIFT (4U) +/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT4_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT5_MASK (0x20U) +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT5_SHIFT (5U) +/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT5_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT6_MASK (0x40U) +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT6_SHIFT (6U) +/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT6_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT7_MASK (0x80U) +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT7_SHIFT (7U) +/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT7_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT8_MASK (0x100U) +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT8_SHIFT (8U) +/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT8_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT9_MASK (0x200U) +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT9_SHIFT (9U) +/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT9_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT10_MASK (0x400U) +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT10_SHIFT (10U) +/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT10_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT11_MASK (0x800U) +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT11_SHIFT (11U) +/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT11_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT12_MASK (0x1000U) +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT12_SHIFT (12U) +/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT12_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT13_MASK (0x2000U) +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT13_SHIFT (13U) +/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT13_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT14_MASK (0x4000U) +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT14_SHIFT (14U) +/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT14_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT15_MASK (0x8000U) +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT15_SHIFT (15U) +/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT15_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT16_MASK (0x10000U) +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT16_SHIFT (16U) +/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT16_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT17_MASK (0x20000U) +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT17_SHIFT (17U) +/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT17_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT18_MASK (0x40000U) +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT18_SHIFT (18U) +/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT18_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT19_MASK (0x80000U) +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT19_SHIFT (19U) +/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT19_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT20_MASK (0x100000U) +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT20_SHIFT (20U) +/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT20_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT21_MASK (0x200000U) +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT21_SHIFT (21U) +/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT21_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT22_MASK (0x400000U) +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT22_SHIFT (22U) +/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT22_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT23_MASK (0x800000U) +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT23_SHIFT (23U) +/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT23_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT24_MASK (0x1000000U) +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT24_SHIFT (24U) +/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT24_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT25_MASK (0x2000000U) +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT25_SHIFT (25U) +/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT25_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT26_MASK (0x4000000U) +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT26_SHIFT (26U) +/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT26_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT27_MASK (0x8000000U) +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT27_SHIFT (27U) +/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT27_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT28_MASK (0x10000000U) +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT28_SHIFT (28U) +/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT28_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT29_MASK (0x20000000U) +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT29_SHIFT (29U) +/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT29_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT30_MASK (0x40000000U) +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT30_SHIFT (30U) +/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT30_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT31_MASK (0x80000000U) +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT31_SHIFT (31U) +/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_BIT31_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W */ +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_COUNT (4U) + +/* The count of TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W */ +#define TRDC_MBC4_MBC_DOM3_MEM1_BLK_NSE_W_COUNT2 (1U) + +/*! @name MBC_DOM3_MEM2_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM2_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM2_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM2_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM2_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM2_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM2_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM2_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM2_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM2_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM2_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM2_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM2_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM2_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM2_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM2_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM2_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM2_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM2_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM2_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM2_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM2_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM2_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM2_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM2_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM2_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM2_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM2_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM2_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM2_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM2_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM2_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM2_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MBC_DOM3_MEM2_BLK_CFG_W */ +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_CFG_W_COUNT (4U) + +/* The count of TRDC_MBC4_MBC_DOM3_MEM2_BLK_CFG_W */ +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_CFG_W_COUNT2 (5U) + +/*! @name MBC_DOM3_MEM2_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ +/*! @{ */ + +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT0_MASK (0x1U) +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT0_SHIFT (0U) +/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT0_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT1_MASK (0x2U) +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT1_SHIFT (1U) +/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT1_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT2_MASK (0x4U) +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT2_SHIFT (2U) +/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT2_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT3_MASK (0x8U) +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT3_SHIFT (3U) +/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT3_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT4_MASK (0x10U) +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT4_SHIFT (4U) +/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT4_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT5_MASK (0x20U) +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT5_SHIFT (5U) +/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT5_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT6_MASK (0x40U) +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT6_SHIFT (6U) +/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT6_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT7_MASK (0x80U) +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT7_SHIFT (7U) +/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT7_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT8_MASK (0x100U) +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT8_SHIFT (8U) +/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT8_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT9_MASK (0x200U) +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT9_SHIFT (9U) +/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT9_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT10_MASK (0x400U) +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT10_SHIFT (10U) +/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT10_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT11_MASK (0x800U) +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT11_SHIFT (11U) +/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT11_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT12_MASK (0x1000U) +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT12_SHIFT (12U) +/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT12_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT13_MASK (0x2000U) +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT13_SHIFT (13U) +/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT13_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT14_MASK (0x4000U) +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT14_SHIFT (14U) +/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT14_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT15_MASK (0x8000U) +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT15_SHIFT (15U) +/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT15_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT16_MASK (0x10000U) +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT16_SHIFT (16U) +/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT16_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT17_MASK (0x20000U) +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT17_SHIFT (17U) +/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT17_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT18_MASK (0x40000U) +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT18_SHIFT (18U) +/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT18_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT19_MASK (0x80000U) +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT19_SHIFT (19U) +/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT19_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT20_MASK (0x100000U) +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT20_SHIFT (20U) +/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT20_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT21_MASK (0x200000U) +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT21_SHIFT (21U) +/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT21_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT22_MASK (0x400000U) +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT22_SHIFT (22U) +/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT22_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT23_MASK (0x800000U) +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT23_SHIFT (23U) +/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT23_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT24_MASK (0x1000000U) +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT24_SHIFT (24U) +/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT24_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT25_MASK (0x2000000U) +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT25_SHIFT (25U) +/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT25_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT26_MASK (0x4000000U) +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT26_SHIFT (26U) +/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT26_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT27_MASK (0x8000000U) +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT27_SHIFT (27U) +/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT27_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT28_MASK (0x10000000U) +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT28_SHIFT (28U) +/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT28_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT29_MASK (0x20000000U) +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT29_SHIFT (29U) +/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT29_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT30_MASK (0x40000000U) +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT30_SHIFT (30U) +/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT30_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT31_MASK (0x80000000U) +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT31_SHIFT (31U) +/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_BIT31_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W */ +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_COUNT (4U) + +/* The count of TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W */ +#define TRDC_MBC4_MBC_DOM3_MEM2_BLK_NSE_W_COUNT2 (2U) + +/*! @name MBC_DOM3_MEM3_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM3_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM3_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM3_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM3_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM3_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM3_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM3_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM3_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM3_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM3_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM3_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM3_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM3_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM3_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM3_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM3_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM3_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM3_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM3_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM3_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM3_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM3_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM3_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM3_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM3_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM3_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM3_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM3_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM3_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM3_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM3_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM3_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MBC_DOM3_MEM3_BLK_CFG_W */ +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_CFG_W_COUNT (4U) + +/* The count of TRDC_MBC4_MBC_DOM3_MEM3_BLK_CFG_W */ +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_CFG_W_COUNT2 (6U) + +/*! @name MBC_DOM3_MEM3_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ +/*! @{ */ + +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT0_MASK (0x1U) +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT0_SHIFT (0U) +/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT0_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT1_MASK (0x2U) +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT1_SHIFT (1U) +/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT1_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT2_MASK (0x4U) +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT2_SHIFT (2U) +/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT2_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT3_MASK (0x8U) +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT3_SHIFT (3U) +/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT3_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT4_MASK (0x10U) +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT4_SHIFT (4U) +/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT4_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT5_MASK (0x20U) +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT5_SHIFT (5U) +/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT5_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT6_MASK (0x40U) +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT6_SHIFT (6U) +/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT6_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT7_MASK (0x80U) +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT7_SHIFT (7U) +/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT7_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT8_MASK (0x100U) +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT8_SHIFT (8U) +/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT8_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT9_MASK (0x200U) +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT9_SHIFT (9U) +/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT9_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT10_MASK (0x400U) +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT10_SHIFT (10U) +/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT10_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT11_MASK (0x800U) +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT11_SHIFT (11U) +/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT11_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT12_MASK (0x1000U) +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT12_SHIFT (12U) +/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT12_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT13_MASK (0x2000U) +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT13_SHIFT (13U) +/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT13_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT14_MASK (0x4000U) +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT14_SHIFT (14U) +/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT14_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT15_MASK (0x8000U) +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT15_SHIFT (15U) +/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT15_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT16_MASK (0x10000U) +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT16_SHIFT (16U) +/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT16_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT17_MASK (0x20000U) +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT17_SHIFT (17U) +/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT17_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT18_MASK (0x40000U) +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT18_SHIFT (18U) +/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT18_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT19_MASK (0x80000U) +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT19_SHIFT (19U) +/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT19_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT20_MASK (0x100000U) +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT20_SHIFT (20U) +/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT20_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT21_MASK (0x200000U) +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT21_SHIFT (21U) +/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT21_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT22_MASK (0x400000U) +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT22_SHIFT (22U) +/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT22_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT23_MASK (0x800000U) +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT23_SHIFT (23U) +/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT23_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT24_MASK (0x1000000U) +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT24_SHIFT (24U) +/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT24_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT25_MASK (0x2000000U) +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT25_SHIFT (25U) +/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT25_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT26_MASK (0x4000000U) +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT26_SHIFT (26U) +/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT26_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT27_MASK (0x8000000U) +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT27_SHIFT (27U) +/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT27_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT28_MASK (0x10000000U) +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT28_SHIFT (28U) +/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT28_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT29_MASK (0x20000000U) +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT29_SHIFT (29U) +/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT29_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT30_MASK (0x40000000U) +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT30_SHIFT (30U) +/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT30_MASK) + +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT31_MASK (0x80000000U) +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT31_SHIFT (31U) +/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_BIT31_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W */ +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_COUNT (4U) + +/* The count of TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W */ +#define TRDC_MBC4_MBC_DOM3_MEM3_BLK_NSE_W_COUNT2 (2U) + +/*! @name MBC_DOM4_MEM0_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM0_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM0_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM0_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM0_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM0_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM0_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM0_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM0_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM0_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM0_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM0_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM0_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM0_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM0_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM0_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM0_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM0_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM0_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM0_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM0_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM0_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM0_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM0_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM0_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM0_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM0_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM0_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM0_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM0_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM0_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM0_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM0_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MBC_DOM4_MEM0_BLK_CFG_W */ +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_CFG_W_COUNT (4U) + +/* The count of TRDC_MBC4_MBC_DOM4_MEM0_BLK_CFG_W */ +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_CFG_W_COUNT2 (7U) + +/*! @name MBC_DOM4_MEM0_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ +/*! @{ */ + +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT0_MASK (0x1U) +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT0_SHIFT (0U) +/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT0_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT1_MASK (0x2U) +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT1_SHIFT (1U) +/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT1_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT2_MASK (0x4U) +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT2_SHIFT (2U) +/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT2_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT3_MASK (0x8U) +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT3_SHIFT (3U) +/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT3_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT4_MASK (0x10U) +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT4_SHIFT (4U) +/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT4_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT5_MASK (0x20U) +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT5_SHIFT (5U) +/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT5_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT6_MASK (0x40U) +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT6_SHIFT (6U) +/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT6_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT7_MASK (0x80U) +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT7_SHIFT (7U) +/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT7_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT8_MASK (0x100U) +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT8_SHIFT (8U) +/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT8_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT9_MASK (0x200U) +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT9_SHIFT (9U) +/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT9_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT10_MASK (0x400U) +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT10_SHIFT (10U) +/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT10_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT11_MASK (0x800U) +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT11_SHIFT (11U) +/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT11_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT12_MASK (0x1000U) +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT12_SHIFT (12U) +/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT12_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT13_MASK (0x2000U) +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT13_SHIFT (13U) +/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT13_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT14_MASK (0x4000U) +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT14_SHIFT (14U) +/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT14_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT15_MASK (0x8000U) +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT15_SHIFT (15U) +/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT15_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT16_MASK (0x10000U) +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT16_SHIFT (16U) +/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT16_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT17_MASK (0x20000U) +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT17_SHIFT (17U) +/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT17_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT18_MASK (0x40000U) +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT18_SHIFT (18U) +/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT18_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT19_MASK (0x80000U) +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT19_SHIFT (19U) +/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT19_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT20_MASK (0x100000U) +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT20_SHIFT (20U) +/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT20_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT21_MASK (0x200000U) +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT21_SHIFT (21U) +/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT21_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT22_MASK (0x400000U) +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT22_SHIFT (22U) +/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT22_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT23_MASK (0x800000U) +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT23_SHIFT (23U) +/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT23_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT24_MASK (0x1000000U) +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT24_SHIFT (24U) +/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT24_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT25_MASK (0x2000000U) +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT25_SHIFT (25U) +/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT25_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT26_MASK (0x4000000U) +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT26_SHIFT (26U) +/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT26_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT27_MASK (0x8000000U) +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT27_SHIFT (27U) +/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT27_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT28_MASK (0x10000000U) +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT28_SHIFT (28U) +/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT28_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT29_MASK (0x20000000U) +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT29_SHIFT (29U) +/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT29_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT30_MASK (0x40000000U) +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT30_SHIFT (30U) +/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT30_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT31_MASK (0x80000000U) +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT31_SHIFT (31U) +/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_BIT31_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W */ +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_COUNT (4U) + +/* The count of TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W */ +#define TRDC_MBC4_MBC_DOM4_MEM0_BLK_NSE_W_COUNT2 (2U) + +/*! @name MBC_DOM4_MEM1_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM1_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM1_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM1_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM1_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM1_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM1_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM1_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM1_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM1_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM1_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM1_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM1_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM1_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM1_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM1_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM1_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM1_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM1_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM1_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM1_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM1_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM1_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM1_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM1_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM1_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM1_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM1_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM1_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM1_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM1_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM1_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM1_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MBC_DOM4_MEM1_BLK_CFG_W */ +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_CFG_W_COUNT (4U) + +/* The count of TRDC_MBC4_MBC_DOM4_MEM1_BLK_CFG_W */ +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_CFG_W_COUNT2 (3U) + +/*! @name MBC_DOM4_MEM1_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ +/*! @{ */ + +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT0_MASK (0x1U) +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT0_SHIFT (0U) +/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT0_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT1_MASK (0x2U) +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT1_SHIFT (1U) +/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT1_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT2_MASK (0x4U) +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT2_SHIFT (2U) +/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT2_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT3_MASK (0x8U) +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT3_SHIFT (3U) +/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT3_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT4_MASK (0x10U) +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT4_SHIFT (4U) +/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT4_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT5_MASK (0x20U) +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT5_SHIFT (5U) +/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT5_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT6_MASK (0x40U) +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT6_SHIFT (6U) +/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT6_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT7_MASK (0x80U) +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT7_SHIFT (7U) +/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT7_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT8_MASK (0x100U) +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT8_SHIFT (8U) +/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT8_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT9_MASK (0x200U) +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT9_SHIFT (9U) +/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT9_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT10_MASK (0x400U) +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT10_SHIFT (10U) +/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT10_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT11_MASK (0x800U) +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT11_SHIFT (11U) +/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT11_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT12_MASK (0x1000U) +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT12_SHIFT (12U) +/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT12_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT13_MASK (0x2000U) +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT13_SHIFT (13U) +/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT13_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT14_MASK (0x4000U) +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT14_SHIFT (14U) +/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT14_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT15_MASK (0x8000U) +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT15_SHIFT (15U) +/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT15_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT16_MASK (0x10000U) +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT16_SHIFT (16U) +/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT16_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT17_MASK (0x20000U) +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT17_SHIFT (17U) +/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT17_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT18_MASK (0x40000U) +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT18_SHIFT (18U) +/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT18_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT19_MASK (0x80000U) +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT19_SHIFT (19U) +/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT19_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT20_MASK (0x100000U) +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT20_SHIFT (20U) +/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT20_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT21_MASK (0x200000U) +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT21_SHIFT (21U) +/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT21_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT22_MASK (0x400000U) +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT22_SHIFT (22U) +/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT22_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT23_MASK (0x800000U) +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT23_SHIFT (23U) +/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT23_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT24_MASK (0x1000000U) +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT24_SHIFT (24U) +/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT24_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT25_MASK (0x2000000U) +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT25_SHIFT (25U) +/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT25_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT26_MASK (0x4000000U) +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT26_SHIFT (26U) +/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT26_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT27_MASK (0x8000000U) +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT27_SHIFT (27U) +/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT27_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT28_MASK (0x10000000U) +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT28_SHIFT (28U) +/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT28_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT29_MASK (0x20000000U) +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT29_SHIFT (29U) +/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT29_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT30_MASK (0x40000000U) +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT30_SHIFT (30U) +/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT30_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT31_MASK (0x80000000U) +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT31_SHIFT (31U) +/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_BIT31_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W */ +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_COUNT (4U) + +/* The count of TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W */ +#define TRDC_MBC4_MBC_DOM4_MEM1_BLK_NSE_W_COUNT2 (1U) + +/*! @name MBC_DOM4_MEM2_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM2_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM2_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM2_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM2_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM2_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM2_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM2_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM2_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM2_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM2_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM2_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM2_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM2_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM2_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM2_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM2_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM2_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM2_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM2_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM2_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM2_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM2_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM2_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM2_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM2_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM2_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM2_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM2_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM2_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM2_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM2_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM2_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MBC_DOM4_MEM2_BLK_CFG_W */ +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_CFG_W_COUNT (4U) + +/* The count of TRDC_MBC4_MBC_DOM4_MEM2_BLK_CFG_W */ +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_CFG_W_COUNT2 (5U) + +/*! @name MBC_DOM4_MEM2_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ +/*! @{ */ + +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT0_MASK (0x1U) +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT0_SHIFT (0U) +/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT0_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT1_MASK (0x2U) +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT1_SHIFT (1U) +/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT1_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT2_MASK (0x4U) +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT2_SHIFT (2U) +/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT2_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT3_MASK (0x8U) +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT3_SHIFT (3U) +/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT3_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT4_MASK (0x10U) +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT4_SHIFT (4U) +/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT4_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT5_MASK (0x20U) +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT5_SHIFT (5U) +/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT5_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT6_MASK (0x40U) +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT6_SHIFT (6U) +/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT6_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT7_MASK (0x80U) +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT7_SHIFT (7U) +/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT7_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT8_MASK (0x100U) +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT8_SHIFT (8U) +/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT8_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT9_MASK (0x200U) +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT9_SHIFT (9U) +/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT9_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT10_MASK (0x400U) +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT10_SHIFT (10U) +/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT10_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT11_MASK (0x800U) +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT11_SHIFT (11U) +/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT11_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT12_MASK (0x1000U) +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT12_SHIFT (12U) +/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT12_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT13_MASK (0x2000U) +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT13_SHIFT (13U) +/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT13_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT14_MASK (0x4000U) +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT14_SHIFT (14U) +/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT14_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT15_MASK (0x8000U) +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT15_SHIFT (15U) +/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT15_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT16_MASK (0x10000U) +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT16_SHIFT (16U) +/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT16_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT17_MASK (0x20000U) +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT17_SHIFT (17U) +/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT17_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT18_MASK (0x40000U) +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT18_SHIFT (18U) +/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT18_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT19_MASK (0x80000U) +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT19_SHIFT (19U) +/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT19_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT20_MASK (0x100000U) +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT20_SHIFT (20U) +/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT20_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT21_MASK (0x200000U) +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT21_SHIFT (21U) +/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT21_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT22_MASK (0x400000U) +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT22_SHIFT (22U) +/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT22_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT23_MASK (0x800000U) +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT23_SHIFT (23U) +/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT23_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT24_MASK (0x1000000U) +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT24_SHIFT (24U) +/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT24_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT25_MASK (0x2000000U) +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT25_SHIFT (25U) +/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT25_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT26_MASK (0x4000000U) +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT26_SHIFT (26U) +/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT26_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT27_MASK (0x8000000U) +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT27_SHIFT (27U) +/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT27_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT28_MASK (0x10000000U) +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT28_SHIFT (28U) +/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT28_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT29_MASK (0x20000000U) +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT29_SHIFT (29U) +/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT29_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT30_MASK (0x40000000U) +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT30_SHIFT (30U) +/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT30_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT31_MASK (0x80000000U) +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT31_SHIFT (31U) +/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_BIT31_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W */ +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_COUNT (4U) + +/* The count of TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W */ +#define TRDC_MBC4_MBC_DOM4_MEM2_BLK_NSE_W_COUNT2 (2U) + +/*! @name MBC_DOM4_MEM3_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM3_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM3_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM3_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM3_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM3_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM3_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM3_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM3_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM3_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM3_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM3_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM3_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM3_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM3_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM3_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM3_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM3_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM3_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM3_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM3_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM3_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM3_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM3_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM3_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM3_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM3_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM3_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM3_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM3_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM3_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM3_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM3_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MBC_DOM4_MEM3_BLK_CFG_W */ +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_CFG_W_COUNT (4U) + +/* The count of TRDC_MBC4_MBC_DOM4_MEM3_BLK_CFG_W */ +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_CFG_W_COUNT2 (6U) + +/*! @name MBC_DOM4_MEM3_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ +/*! @{ */ + +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT0_MASK (0x1U) +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT0_SHIFT (0U) +/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT0_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT1_MASK (0x2U) +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT1_SHIFT (1U) +/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT1_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT2_MASK (0x4U) +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT2_SHIFT (2U) +/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT2_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT3_MASK (0x8U) +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT3_SHIFT (3U) +/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT3_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT4_MASK (0x10U) +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT4_SHIFT (4U) +/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT4_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT5_MASK (0x20U) +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT5_SHIFT (5U) +/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT5_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT6_MASK (0x40U) +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT6_SHIFT (6U) +/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT6_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT7_MASK (0x80U) +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT7_SHIFT (7U) +/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT7_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT8_MASK (0x100U) +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT8_SHIFT (8U) +/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT8_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT9_MASK (0x200U) +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT9_SHIFT (9U) +/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT9_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT10_MASK (0x400U) +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT10_SHIFT (10U) +/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT10_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT11_MASK (0x800U) +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT11_SHIFT (11U) +/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT11_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT12_MASK (0x1000U) +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT12_SHIFT (12U) +/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT12_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT13_MASK (0x2000U) +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT13_SHIFT (13U) +/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT13_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT14_MASK (0x4000U) +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT14_SHIFT (14U) +/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT14_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT15_MASK (0x8000U) +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT15_SHIFT (15U) +/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT15_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT16_MASK (0x10000U) +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT16_SHIFT (16U) +/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT16_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT17_MASK (0x20000U) +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT17_SHIFT (17U) +/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT17_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT18_MASK (0x40000U) +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT18_SHIFT (18U) +/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT18_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT19_MASK (0x80000U) +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT19_SHIFT (19U) +/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT19_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT20_MASK (0x100000U) +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT20_SHIFT (20U) +/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT20_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT21_MASK (0x200000U) +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT21_SHIFT (21U) +/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT21_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT22_MASK (0x400000U) +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT22_SHIFT (22U) +/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT22_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT23_MASK (0x800000U) +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT23_SHIFT (23U) +/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT23_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT24_MASK (0x1000000U) +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT24_SHIFT (24U) +/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT24_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT25_MASK (0x2000000U) +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT25_SHIFT (25U) +/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT25_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT26_MASK (0x4000000U) +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT26_SHIFT (26U) +/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT26_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT27_MASK (0x8000000U) +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT27_SHIFT (27U) +/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT27_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT28_MASK (0x10000000U) +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT28_SHIFT (28U) +/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT28_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT29_MASK (0x20000000U) +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT29_SHIFT (29U) +/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT29_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT30_MASK (0x40000000U) +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT30_SHIFT (30U) +/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT30_MASK) + +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT31_MASK (0x80000000U) +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT31_SHIFT (31U) +/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_BIT31_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W */ +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_COUNT (4U) + +/* The count of TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W */ +#define TRDC_MBC4_MBC_DOM4_MEM3_BLK_NSE_W_COUNT2 (2U) + +/*! @name MBC_DOM5_MEM0_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM0_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM0_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM0_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM0_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM0_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM0_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM0_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM0_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM0_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM0_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM0_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM0_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM0_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM0_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM0_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM0_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM0_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM0_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM0_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM0_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM0_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM0_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM0_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM0_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM0_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM0_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM0_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM0_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM0_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM0_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM0_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM0_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MBC_DOM5_MEM0_BLK_CFG_W */ +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_CFG_W_COUNT (4U) + +/* The count of TRDC_MBC4_MBC_DOM5_MEM0_BLK_CFG_W */ +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_CFG_W_COUNT2 (7U) + +/*! @name MBC_DOM5_MEM0_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ +/*! @{ */ + +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT0_MASK (0x1U) +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT0_SHIFT (0U) +/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT0_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT1_MASK (0x2U) +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT1_SHIFT (1U) +/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT1_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT2_MASK (0x4U) +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT2_SHIFT (2U) +/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT2_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT3_MASK (0x8U) +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT3_SHIFT (3U) +/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT3_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT4_MASK (0x10U) +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT4_SHIFT (4U) +/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT4_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT5_MASK (0x20U) +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT5_SHIFT (5U) +/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT5_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT6_MASK (0x40U) +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT6_SHIFT (6U) +/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT6_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT7_MASK (0x80U) +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT7_SHIFT (7U) +/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT7_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT8_MASK (0x100U) +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT8_SHIFT (8U) +/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT8_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT9_MASK (0x200U) +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT9_SHIFT (9U) +/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT9_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT10_MASK (0x400U) +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT10_SHIFT (10U) +/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT10_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT11_MASK (0x800U) +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT11_SHIFT (11U) +/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT11_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT12_MASK (0x1000U) +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT12_SHIFT (12U) +/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT12_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT13_MASK (0x2000U) +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT13_SHIFT (13U) +/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT13_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT14_MASK (0x4000U) +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT14_SHIFT (14U) +/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT14_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT15_MASK (0x8000U) +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT15_SHIFT (15U) +/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT15_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT16_MASK (0x10000U) +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT16_SHIFT (16U) +/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT16_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT17_MASK (0x20000U) +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT17_SHIFT (17U) +/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT17_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT18_MASK (0x40000U) +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT18_SHIFT (18U) +/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT18_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT19_MASK (0x80000U) +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT19_SHIFT (19U) +/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT19_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT20_MASK (0x100000U) +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT20_SHIFT (20U) +/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT20_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT21_MASK (0x200000U) +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT21_SHIFT (21U) +/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT21_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT22_MASK (0x400000U) +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT22_SHIFT (22U) +/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT22_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT23_MASK (0x800000U) +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT23_SHIFT (23U) +/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT23_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT24_MASK (0x1000000U) +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT24_SHIFT (24U) +/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT24_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT25_MASK (0x2000000U) +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT25_SHIFT (25U) +/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT25_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT26_MASK (0x4000000U) +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT26_SHIFT (26U) +/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT26_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT27_MASK (0x8000000U) +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT27_SHIFT (27U) +/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT27_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT28_MASK (0x10000000U) +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT28_SHIFT (28U) +/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT28_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT29_MASK (0x20000000U) +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT29_SHIFT (29U) +/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT29_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT30_MASK (0x40000000U) +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT30_SHIFT (30U) +/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT30_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT31_MASK (0x80000000U) +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT31_SHIFT (31U) +/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_BIT31_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W */ +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_COUNT (4U) + +/* The count of TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W */ +#define TRDC_MBC4_MBC_DOM5_MEM0_BLK_NSE_W_COUNT2 (2U) + +/*! @name MBC_DOM5_MEM1_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM1_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM1_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM1_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM1_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM1_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM1_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM1_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM1_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM1_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM1_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM1_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM1_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM1_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM1_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM1_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM1_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM1_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM1_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM1_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM1_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM1_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM1_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM1_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM1_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM1_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM1_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM1_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM1_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM1_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM1_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM1_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM1_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MBC_DOM5_MEM1_BLK_CFG_W */ +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_CFG_W_COUNT (4U) + +/* The count of TRDC_MBC4_MBC_DOM5_MEM1_BLK_CFG_W */ +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_CFG_W_COUNT2 (3U) + +/*! @name MBC_DOM5_MEM1_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ +/*! @{ */ + +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT0_MASK (0x1U) +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT0_SHIFT (0U) +/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT0_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT1_MASK (0x2U) +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT1_SHIFT (1U) +/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT1_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT2_MASK (0x4U) +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT2_SHIFT (2U) +/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT2_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT3_MASK (0x8U) +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT3_SHIFT (3U) +/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT3_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT4_MASK (0x10U) +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT4_SHIFT (4U) +/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT4_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT5_MASK (0x20U) +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT5_SHIFT (5U) +/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT5_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT6_MASK (0x40U) +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT6_SHIFT (6U) +/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT6_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT7_MASK (0x80U) +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT7_SHIFT (7U) +/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT7_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT8_MASK (0x100U) +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT8_SHIFT (8U) +/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT8_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT9_MASK (0x200U) +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT9_SHIFT (9U) +/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT9_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT10_MASK (0x400U) +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT10_SHIFT (10U) +/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT10_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT11_MASK (0x800U) +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT11_SHIFT (11U) +/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT11_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT12_MASK (0x1000U) +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT12_SHIFT (12U) +/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT12_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT13_MASK (0x2000U) +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT13_SHIFT (13U) +/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT13_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT14_MASK (0x4000U) +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT14_SHIFT (14U) +/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT14_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT15_MASK (0x8000U) +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT15_SHIFT (15U) +/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT15_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT16_MASK (0x10000U) +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT16_SHIFT (16U) +/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT16_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT17_MASK (0x20000U) +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT17_SHIFT (17U) +/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT17_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT18_MASK (0x40000U) +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT18_SHIFT (18U) +/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT18_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT19_MASK (0x80000U) +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT19_SHIFT (19U) +/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT19_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT20_MASK (0x100000U) +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT20_SHIFT (20U) +/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT20_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT21_MASK (0x200000U) +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT21_SHIFT (21U) +/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT21_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT22_MASK (0x400000U) +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT22_SHIFT (22U) +/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT22_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT23_MASK (0x800000U) +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT23_SHIFT (23U) +/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT23_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT24_MASK (0x1000000U) +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT24_SHIFT (24U) +/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT24_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT25_MASK (0x2000000U) +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT25_SHIFT (25U) +/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT25_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT26_MASK (0x4000000U) +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT26_SHIFT (26U) +/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT26_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT27_MASK (0x8000000U) +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT27_SHIFT (27U) +/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT27_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT28_MASK (0x10000000U) +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT28_SHIFT (28U) +/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT28_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT29_MASK (0x20000000U) +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT29_SHIFT (29U) +/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT29_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT30_MASK (0x40000000U) +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT30_SHIFT (30U) +/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT30_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT31_MASK (0x80000000U) +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT31_SHIFT (31U) +/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_BIT31_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W */ +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_COUNT (4U) + +/* The count of TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W */ +#define TRDC_MBC4_MBC_DOM5_MEM1_BLK_NSE_W_COUNT2 (1U) + +/*! @name MBC_DOM5_MEM2_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM2_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM2_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM2_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM2_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM2_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM2_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM2_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM2_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM2_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM2_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM2_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM2_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM2_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM2_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM2_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM2_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM2_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM2_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM2_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM2_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM2_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM2_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM2_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM2_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM2_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM2_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM2_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM2_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM2_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM2_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM2_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM2_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MBC_DOM5_MEM2_BLK_CFG_W */ +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_CFG_W_COUNT (4U) + +/* The count of TRDC_MBC4_MBC_DOM5_MEM2_BLK_CFG_W */ +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_CFG_W_COUNT2 (5U) + +/*! @name MBC_DOM5_MEM2_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ +/*! @{ */ + +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT0_MASK (0x1U) +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT0_SHIFT (0U) +/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT0_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT1_MASK (0x2U) +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT1_SHIFT (1U) +/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT1_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT2_MASK (0x4U) +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT2_SHIFT (2U) +/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT2_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT3_MASK (0x8U) +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT3_SHIFT (3U) +/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT3_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT4_MASK (0x10U) +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT4_SHIFT (4U) +/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT4_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT5_MASK (0x20U) +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT5_SHIFT (5U) +/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT5_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT6_MASK (0x40U) +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT6_SHIFT (6U) +/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT6_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT7_MASK (0x80U) +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT7_SHIFT (7U) +/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT7_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT8_MASK (0x100U) +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT8_SHIFT (8U) +/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT8_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT9_MASK (0x200U) +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT9_SHIFT (9U) +/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT9_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT10_MASK (0x400U) +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT10_SHIFT (10U) +/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT10_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT11_MASK (0x800U) +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT11_SHIFT (11U) +/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT11_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT12_MASK (0x1000U) +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT12_SHIFT (12U) +/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT12_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT13_MASK (0x2000U) +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT13_SHIFT (13U) +/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT13_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT14_MASK (0x4000U) +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT14_SHIFT (14U) +/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT14_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT15_MASK (0x8000U) +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT15_SHIFT (15U) +/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT15_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT16_MASK (0x10000U) +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT16_SHIFT (16U) +/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT16_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT17_MASK (0x20000U) +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT17_SHIFT (17U) +/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT17_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT18_MASK (0x40000U) +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT18_SHIFT (18U) +/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT18_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT19_MASK (0x80000U) +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT19_SHIFT (19U) +/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT19_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT20_MASK (0x100000U) +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT20_SHIFT (20U) +/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT20_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT21_MASK (0x200000U) +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT21_SHIFT (21U) +/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT21_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT22_MASK (0x400000U) +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT22_SHIFT (22U) +/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT22_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT23_MASK (0x800000U) +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT23_SHIFT (23U) +/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT23_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT24_MASK (0x1000000U) +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT24_SHIFT (24U) +/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT24_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT25_MASK (0x2000000U) +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT25_SHIFT (25U) +/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT25_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT26_MASK (0x4000000U) +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT26_SHIFT (26U) +/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT26_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT27_MASK (0x8000000U) +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT27_SHIFT (27U) +/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT27_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT28_MASK (0x10000000U) +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT28_SHIFT (28U) +/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT28_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT29_MASK (0x20000000U) +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT29_SHIFT (29U) +/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT29_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT30_MASK (0x40000000U) +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT30_SHIFT (30U) +/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT30_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT31_MASK (0x80000000U) +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT31_SHIFT (31U) +/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_BIT31_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W */ +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_COUNT (4U) + +/* The count of TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W */ +#define TRDC_MBC4_MBC_DOM5_MEM2_BLK_NSE_W_COUNT2 (2U) + +/*! @name MBC_DOM5_MEM3_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM3_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM3_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM3_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM3_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM3_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM3_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM3_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM3_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM3_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM3_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM3_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM3_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM3_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM3_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM3_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM3_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM3_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM3_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM3_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM3_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM3_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM3_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM3_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM3_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM3_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM3_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM3_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM3_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM3_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM3_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM3_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM3_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MBC_DOM5_MEM3_BLK_CFG_W */ +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_CFG_W_COUNT (4U) + +/* The count of TRDC_MBC4_MBC_DOM5_MEM3_BLK_CFG_W */ +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_CFG_W_COUNT2 (6U) + +/*! @name MBC_DOM5_MEM3_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ +/*! @{ */ + +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT0_MASK (0x1U) +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT0_SHIFT (0U) +/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT0_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT1_MASK (0x2U) +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT1_SHIFT (1U) +/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT1_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT2_MASK (0x4U) +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT2_SHIFT (2U) +/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT2_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT3_MASK (0x8U) +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT3_SHIFT (3U) +/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT3_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT4_MASK (0x10U) +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT4_SHIFT (4U) +/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT4_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT5_MASK (0x20U) +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT5_SHIFT (5U) +/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT5_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT6_MASK (0x40U) +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT6_SHIFT (6U) +/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT6_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT7_MASK (0x80U) +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT7_SHIFT (7U) +/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT7_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT8_MASK (0x100U) +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT8_SHIFT (8U) +/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT8_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT9_MASK (0x200U) +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT9_SHIFT (9U) +/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT9_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT10_MASK (0x400U) +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT10_SHIFT (10U) +/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT10_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT11_MASK (0x800U) +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT11_SHIFT (11U) +/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT11_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT12_MASK (0x1000U) +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT12_SHIFT (12U) +/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT12_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT13_MASK (0x2000U) +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT13_SHIFT (13U) +/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT13_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT14_MASK (0x4000U) +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT14_SHIFT (14U) +/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT14_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT15_MASK (0x8000U) +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT15_SHIFT (15U) +/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT15_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT16_MASK (0x10000U) +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT16_SHIFT (16U) +/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT16_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT17_MASK (0x20000U) +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT17_SHIFT (17U) +/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT17_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT18_MASK (0x40000U) +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT18_SHIFT (18U) +/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT18_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT19_MASK (0x80000U) +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT19_SHIFT (19U) +/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT19_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT20_MASK (0x100000U) +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT20_SHIFT (20U) +/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT20_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT21_MASK (0x200000U) +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT21_SHIFT (21U) +/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT21_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT22_MASK (0x400000U) +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT22_SHIFT (22U) +/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT22_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT23_MASK (0x800000U) +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT23_SHIFT (23U) +/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT23_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT24_MASK (0x1000000U) +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT24_SHIFT (24U) +/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT24_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT25_MASK (0x2000000U) +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT25_SHIFT (25U) +/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT25_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT26_MASK (0x4000000U) +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT26_SHIFT (26U) +/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT26_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT27_MASK (0x8000000U) +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT27_SHIFT (27U) +/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT27_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT28_MASK (0x10000000U) +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT28_SHIFT (28U) +/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT28_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT29_MASK (0x20000000U) +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT29_SHIFT (29U) +/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT29_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT30_MASK (0x40000000U) +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT30_SHIFT (30U) +/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT30_MASK) + +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT31_MASK (0x80000000U) +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT31_SHIFT (31U) +/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_BIT31_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W */ +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_COUNT (4U) + +/* The count of TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W */ +#define TRDC_MBC4_MBC_DOM5_MEM3_BLK_NSE_W_COUNT2 (2U) + +/*! @name MBC_DOM6_MEM0_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM0_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM0_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM0_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM0_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM0_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM0_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM0_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM0_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM0_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM0_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM0_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM0_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM0_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM0_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM0_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM0_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM0_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM0_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM0_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM0_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM0_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM0_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM0_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM0_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM0_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM0_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM0_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM0_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM0_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM0_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM0_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM0_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MBC_DOM6_MEM0_BLK_CFG_W */ +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_CFG_W_COUNT (4U) + +/* The count of TRDC_MBC4_MBC_DOM6_MEM0_BLK_CFG_W */ +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_CFG_W_COUNT2 (7U) + +/*! @name MBC_DOM6_MEM0_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ +/*! @{ */ + +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT0_MASK (0x1U) +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT0_SHIFT (0U) +/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT0_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT1_MASK (0x2U) +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT1_SHIFT (1U) +/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT1_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT2_MASK (0x4U) +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT2_SHIFT (2U) +/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT2_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT3_MASK (0x8U) +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT3_SHIFT (3U) +/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT3_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT4_MASK (0x10U) +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT4_SHIFT (4U) +/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT4_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT5_MASK (0x20U) +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT5_SHIFT (5U) +/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT5_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT6_MASK (0x40U) +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT6_SHIFT (6U) +/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT6_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT7_MASK (0x80U) +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT7_SHIFT (7U) +/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT7_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT8_MASK (0x100U) +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT8_SHIFT (8U) +/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT8_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT9_MASK (0x200U) +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT9_SHIFT (9U) +/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT9_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT10_MASK (0x400U) +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT10_SHIFT (10U) +/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT10_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT11_MASK (0x800U) +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT11_SHIFT (11U) +/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT11_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT12_MASK (0x1000U) +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT12_SHIFT (12U) +/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT12_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT13_MASK (0x2000U) +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT13_SHIFT (13U) +/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT13_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT14_MASK (0x4000U) +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT14_SHIFT (14U) +/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT14_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT15_MASK (0x8000U) +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT15_SHIFT (15U) +/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT15_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT16_MASK (0x10000U) +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT16_SHIFT (16U) +/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT16_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT17_MASK (0x20000U) +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT17_SHIFT (17U) +/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT17_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT18_MASK (0x40000U) +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT18_SHIFT (18U) +/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT18_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT19_MASK (0x80000U) +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT19_SHIFT (19U) +/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT19_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT20_MASK (0x100000U) +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT20_SHIFT (20U) +/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT20_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT21_MASK (0x200000U) +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT21_SHIFT (21U) +/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT21_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT22_MASK (0x400000U) +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT22_SHIFT (22U) +/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT22_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT23_MASK (0x800000U) +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT23_SHIFT (23U) +/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT23_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT24_MASK (0x1000000U) +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT24_SHIFT (24U) +/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT24_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT25_MASK (0x2000000U) +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT25_SHIFT (25U) +/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT25_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT26_MASK (0x4000000U) +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT26_SHIFT (26U) +/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT26_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT27_MASK (0x8000000U) +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT27_SHIFT (27U) +/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT27_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT28_MASK (0x10000000U) +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT28_SHIFT (28U) +/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT28_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT29_MASK (0x20000000U) +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT29_SHIFT (29U) +/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT29_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT30_MASK (0x40000000U) +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT30_SHIFT (30U) +/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT30_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT31_MASK (0x80000000U) +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT31_SHIFT (31U) +/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_BIT31_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W */ +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_COUNT (4U) + +/* The count of TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W */ +#define TRDC_MBC4_MBC_DOM6_MEM0_BLK_NSE_W_COUNT2 (2U) + +/*! @name MBC_DOM6_MEM1_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM1_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM1_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM1_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM1_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM1_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM1_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM1_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM1_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM1_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM1_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM1_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM1_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM1_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM1_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM1_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM1_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM1_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM1_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM1_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM1_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM1_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM1_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM1_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM1_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM1_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM1_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM1_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM1_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM1_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM1_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM1_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM1_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MBC_DOM6_MEM1_BLK_CFG_W */ +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_CFG_W_COUNT (4U) + +/* The count of TRDC_MBC4_MBC_DOM6_MEM1_BLK_CFG_W */ +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_CFG_W_COUNT2 (3U) + +/*! @name MBC_DOM6_MEM1_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ +/*! @{ */ + +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT0_MASK (0x1U) +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT0_SHIFT (0U) +/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT0_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT1_MASK (0x2U) +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT1_SHIFT (1U) +/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT1_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT2_MASK (0x4U) +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT2_SHIFT (2U) +/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT2_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT3_MASK (0x8U) +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT3_SHIFT (3U) +/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT3_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT4_MASK (0x10U) +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT4_SHIFT (4U) +/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT4_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT5_MASK (0x20U) +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT5_SHIFT (5U) +/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT5_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT6_MASK (0x40U) +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT6_SHIFT (6U) +/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT6_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT7_MASK (0x80U) +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT7_SHIFT (7U) +/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT7_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT8_MASK (0x100U) +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT8_SHIFT (8U) +/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT8_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT9_MASK (0x200U) +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT9_SHIFT (9U) +/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT9_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT10_MASK (0x400U) +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT10_SHIFT (10U) +/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT10_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT11_MASK (0x800U) +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT11_SHIFT (11U) +/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT11_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT12_MASK (0x1000U) +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT12_SHIFT (12U) +/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT12_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT13_MASK (0x2000U) +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT13_SHIFT (13U) +/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT13_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT14_MASK (0x4000U) +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT14_SHIFT (14U) +/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT14_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT15_MASK (0x8000U) +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT15_SHIFT (15U) +/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT15_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT16_MASK (0x10000U) +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT16_SHIFT (16U) +/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT16_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT17_MASK (0x20000U) +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT17_SHIFT (17U) +/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT17_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT18_MASK (0x40000U) +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT18_SHIFT (18U) +/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT18_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT19_MASK (0x80000U) +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT19_SHIFT (19U) +/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT19_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT20_MASK (0x100000U) +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT20_SHIFT (20U) +/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT20_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT21_MASK (0x200000U) +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT21_SHIFT (21U) +/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT21_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT22_MASK (0x400000U) +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT22_SHIFT (22U) +/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT22_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT23_MASK (0x800000U) +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT23_SHIFT (23U) +/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT23_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT24_MASK (0x1000000U) +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT24_SHIFT (24U) +/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT24_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT25_MASK (0x2000000U) +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT25_SHIFT (25U) +/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT25_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT26_MASK (0x4000000U) +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT26_SHIFT (26U) +/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT26_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT27_MASK (0x8000000U) +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT27_SHIFT (27U) +/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT27_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT28_MASK (0x10000000U) +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT28_SHIFT (28U) +/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT28_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT29_MASK (0x20000000U) +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT29_SHIFT (29U) +/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT29_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT30_MASK (0x40000000U) +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT30_SHIFT (30U) +/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT30_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT31_MASK (0x80000000U) +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT31_SHIFT (31U) +/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_BIT31_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W */ +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_COUNT (4U) + +/* The count of TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W */ +#define TRDC_MBC4_MBC_DOM6_MEM1_BLK_NSE_W_COUNT2 (1U) + +/*! @name MBC_DOM6_MEM2_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM2_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM2_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM2_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM2_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM2_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM2_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM2_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM2_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM2_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM2_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM2_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM2_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM2_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM2_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM2_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM2_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM2_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM2_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM2_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM2_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM2_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM2_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM2_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM2_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM2_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM2_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM2_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM2_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM2_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM2_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM2_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM2_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MBC_DOM6_MEM2_BLK_CFG_W */ +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_CFG_W_COUNT (4U) + +/* The count of TRDC_MBC4_MBC_DOM6_MEM2_BLK_CFG_W */ +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_CFG_W_COUNT2 (5U) + +/*! @name MBC_DOM6_MEM2_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ +/*! @{ */ + +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT0_MASK (0x1U) +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT0_SHIFT (0U) +/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT0_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT1_MASK (0x2U) +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT1_SHIFT (1U) +/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT1_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT2_MASK (0x4U) +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT2_SHIFT (2U) +/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT2_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT3_MASK (0x8U) +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT3_SHIFT (3U) +/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT3_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT4_MASK (0x10U) +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT4_SHIFT (4U) +/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT4_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT5_MASK (0x20U) +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT5_SHIFT (5U) +/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT5_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT6_MASK (0x40U) +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT6_SHIFT (6U) +/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT6_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT7_MASK (0x80U) +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT7_SHIFT (7U) +/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT7_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT8_MASK (0x100U) +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT8_SHIFT (8U) +/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT8_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT9_MASK (0x200U) +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT9_SHIFT (9U) +/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT9_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT10_MASK (0x400U) +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT10_SHIFT (10U) +/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT10_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT11_MASK (0x800U) +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT11_SHIFT (11U) +/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT11_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT12_MASK (0x1000U) +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT12_SHIFT (12U) +/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT12_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT13_MASK (0x2000U) +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT13_SHIFT (13U) +/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT13_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT14_MASK (0x4000U) +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT14_SHIFT (14U) +/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT14_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT15_MASK (0x8000U) +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT15_SHIFT (15U) +/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT15_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT16_MASK (0x10000U) +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT16_SHIFT (16U) +/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT16_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT17_MASK (0x20000U) +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT17_SHIFT (17U) +/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT17_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT18_MASK (0x40000U) +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT18_SHIFT (18U) +/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT18_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT19_MASK (0x80000U) +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT19_SHIFT (19U) +/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT19_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT20_MASK (0x100000U) +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT20_SHIFT (20U) +/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT20_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT21_MASK (0x200000U) +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT21_SHIFT (21U) +/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT21_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT22_MASK (0x400000U) +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT22_SHIFT (22U) +/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT22_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT23_MASK (0x800000U) +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT23_SHIFT (23U) +/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT23_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT24_MASK (0x1000000U) +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT24_SHIFT (24U) +/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT24_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT25_MASK (0x2000000U) +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT25_SHIFT (25U) +/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT25_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT26_MASK (0x4000000U) +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT26_SHIFT (26U) +/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT26_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT27_MASK (0x8000000U) +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT27_SHIFT (27U) +/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT27_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT28_MASK (0x10000000U) +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT28_SHIFT (28U) +/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT28_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT29_MASK (0x20000000U) +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT29_SHIFT (29U) +/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT29_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT30_MASK (0x40000000U) +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT30_SHIFT (30U) +/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT30_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT31_MASK (0x80000000U) +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT31_SHIFT (31U) +/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_BIT31_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W */ +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_COUNT (4U) + +/* The count of TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W */ +#define TRDC_MBC4_MBC_DOM6_MEM2_BLK_NSE_W_COUNT2 (2U) + +/*! @name MBC_DOM6_MEM3_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM3_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM3_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM3_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM3_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM3_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM3_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM3_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM3_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM3_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM3_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM3_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM3_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM3_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM3_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM3_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM3_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM3_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM3_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM3_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM3_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM3_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM3_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM3_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM3_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM3_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM3_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM3_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM3_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM3_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM3_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM3_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM3_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MBC_DOM6_MEM3_BLK_CFG_W */ +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_CFG_W_COUNT (4U) + +/* The count of TRDC_MBC4_MBC_DOM6_MEM3_BLK_CFG_W */ +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_CFG_W_COUNT2 (6U) + +/*! @name MBC_DOM6_MEM3_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ +/*! @{ */ + +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT0_MASK (0x1U) +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT0_SHIFT (0U) +/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT0_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT1_MASK (0x2U) +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT1_SHIFT (1U) +/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT1_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT2_MASK (0x4U) +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT2_SHIFT (2U) +/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT2_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT3_MASK (0x8U) +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT3_SHIFT (3U) +/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT3_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT4_MASK (0x10U) +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT4_SHIFT (4U) +/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT4_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT5_MASK (0x20U) +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT5_SHIFT (5U) +/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT5_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT6_MASK (0x40U) +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT6_SHIFT (6U) +/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT6_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT7_MASK (0x80U) +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT7_SHIFT (7U) +/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT7_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT8_MASK (0x100U) +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT8_SHIFT (8U) +/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT8_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT9_MASK (0x200U) +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT9_SHIFT (9U) +/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT9_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT10_MASK (0x400U) +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT10_SHIFT (10U) +/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT10_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT11_MASK (0x800U) +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT11_SHIFT (11U) +/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT11_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT12_MASK (0x1000U) +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT12_SHIFT (12U) +/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT12_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT13_MASK (0x2000U) +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT13_SHIFT (13U) +/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT13_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT14_MASK (0x4000U) +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT14_SHIFT (14U) +/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT14_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT15_MASK (0x8000U) +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT15_SHIFT (15U) +/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT15_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT16_MASK (0x10000U) +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT16_SHIFT (16U) +/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT16_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT17_MASK (0x20000U) +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT17_SHIFT (17U) +/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT17_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT18_MASK (0x40000U) +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT18_SHIFT (18U) +/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT18_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT19_MASK (0x80000U) +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT19_SHIFT (19U) +/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT19_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT20_MASK (0x100000U) +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT20_SHIFT (20U) +/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT20_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT21_MASK (0x200000U) +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT21_SHIFT (21U) +/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT21_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT22_MASK (0x400000U) +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT22_SHIFT (22U) +/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT22_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT23_MASK (0x800000U) +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT23_SHIFT (23U) +/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT23_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT24_MASK (0x1000000U) +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT24_SHIFT (24U) +/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT24_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT25_MASK (0x2000000U) +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT25_SHIFT (25U) +/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT25_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT26_MASK (0x4000000U) +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT26_SHIFT (26U) +/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT26_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT27_MASK (0x8000000U) +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT27_SHIFT (27U) +/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT27_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT28_MASK (0x10000000U) +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT28_SHIFT (28U) +/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT28_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT29_MASK (0x20000000U) +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT29_SHIFT (29U) +/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT29_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT30_MASK (0x40000000U) +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT30_SHIFT (30U) +/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT30_MASK) + +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT31_MASK (0x80000000U) +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT31_SHIFT (31U) +/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_BIT31_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W */ +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_COUNT (4U) + +/* The count of TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W */ +#define TRDC_MBC4_MBC_DOM6_MEM3_BLK_NSE_W_COUNT2 (2U) + +/*! @name MBC_DOM7_MEM0_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM0_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM0_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM0_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM0_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM0_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM0_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM0_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM0_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM0_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM0_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM0_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM0_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM0_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM0_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM0_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM0_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM0_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM0_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM0_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM0_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM0_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM0_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM0_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM0_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM0_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM0_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM0_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM0_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM0_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM0_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM0_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM0_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MBC_DOM7_MEM0_BLK_CFG_W */ +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_CFG_W_COUNT (4U) + +/* The count of TRDC_MBC4_MBC_DOM7_MEM0_BLK_CFG_W */ +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_CFG_W_COUNT2 (7U) + +/*! @name MBC_DOM7_MEM0_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ +/*! @{ */ + +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT0_MASK (0x1U) +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT0_SHIFT (0U) +/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT0_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT1_MASK (0x2U) +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT1_SHIFT (1U) +/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT1_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT2_MASK (0x4U) +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT2_SHIFT (2U) +/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT2_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT3_MASK (0x8U) +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT3_SHIFT (3U) +/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT3_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT4_MASK (0x10U) +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT4_SHIFT (4U) +/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT4_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT5_MASK (0x20U) +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT5_SHIFT (5U) +/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT5_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT6_MASK (0x40U) +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT6_SHIFT (6U) +/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT6_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT7_MASK (0x80U) +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT7_SHIFT (7U) +/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT7_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT8_MASK (0x100U) +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT8_SHIFT (8U) +/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT8_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT9_MASK (0x200U) +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT9_SHIFT (9U) +/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT9_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT10_MASK (0x400U) +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT10_SHIFT (10U) +/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT10_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT11_MASK (0x800U) +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT11_SHIFT (11U) +/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT11_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT12_MASK (0x1000U) +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT12_SHIFT (12U) +/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT12_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT13_MASK (0x2000U) +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT13_SHIFT (13U) +/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT13_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT14_MASK (0x4000U) +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT14_SHIFT (14U) +/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT14_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT15_MASK (0x8000U) +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT15_SHIFT (15U) +/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT15_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT16_MASK (0x10000U) +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT16_SHIFT (16U) +/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT16_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT17_MASK (0x20000U) +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT17_SHIFT (17U) +/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT17_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT18_MASK (0x40000U) +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT18_SHIFT (18U) +/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT18_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT19_MASK (0x80000U) +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT19_SHIFT (19U) +/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT19_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT20_MASK (0x100000U) +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT20_SHIFT (20U) +/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT20_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT21_MASK (0x200000U) +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT21_SHIFT (21U) +/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT21_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT22_MASK (0x400000U) +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT22_SHIFT (22U) +/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT22_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT23_MASK (0x800000U) +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT23_SHIFT (23U) +/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT23_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT24_MASK (0x1000000U) +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT24_SHIFT (24U) +/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT24_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT25_MASK (0x2000000U) +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT25_SHIFT (25U) +/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT25_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT26_MASK (0x4000000U) +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT26_SHIFT (26U) +/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT26_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT27_MASK (0x8000000U) +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT27_SHIFT (27U) +/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT27_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT28_MASK (0x10000000U) +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT28_SHIFT (28U) +/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT28_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT29_MASK (0x20000000U) +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT29_SHIFT (29U) +/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT29_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT30_MASK (0x40000000U) +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT30_SHIFT (30U) +/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT30_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT31_MASK (0x80000000U) +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT31_SHIFT (31U) +/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_BIT31_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W */ +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_COUNT (4U) + +/* The count of TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W */ +#define TRDC_MBC4_MBC_DOM7_MEM0_BLK_NSE_W_COUNT2 (2U) + +/*! @name MBC_DOM7_MEM1_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM1_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM1_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM1_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM1_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM1_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM1_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM1_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM1_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM1_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM1_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM1_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM1_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM1_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM1_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM1_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM1_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM1_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM1_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM1_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM1_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM1_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM1_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM1_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM1_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM1_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM1_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM1_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM1_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM1_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM1_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM1_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM1_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MBC_DOM7_MEM1_BLK_CFG_W */ +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_CFG_W_COUNT (4U) + +/* The count of TRDC_MBC4_MBC_DOM7_MEM1_BLK_CFG_W */ +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_CFG_W_COUNT2 (3U) + +/*! @name MBC_DOM7_MEM1_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ +/*! @{ */ + +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT0_MASK (0x1U) +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT0_SHIFT (0U) +/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT0_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT1_MASK (0x2U) +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT1_SHIFT (1U) +/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT1_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT2_MASK (0x4U) +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT2_SHIFT (2U) +/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT2_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT3_MASK (0x8U) +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT3_SHIFT (3U) +/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT3_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT4_MASK (0x10U) +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT4_SHIFT (4U) +/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT4_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT5_MASK (0x20U) +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT5_SHIFT (5U) +/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT5_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT6_MASK (0x40U) +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT6_SHIFT (6U) +/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT6_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT7_MASK (0x80U) +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT7_SHIFT (7U) +/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT7_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT8_MASK (0x100U) +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT8_SHIFT (8U) +/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT8_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT9_MASK (0x200U) +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT9_SHIFT (9U) +/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT9_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT10_MASK (0x400U) +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT10_SHIFT (10U) +/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT10_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT11_MASK (0x800U) +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT11_SHIFT (11U) +/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT11_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT12_MASK (0x1000U) +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT12_SHIFT (12U) +/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT12_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT13_MASK (0x2000U) +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT13_SHIFT (13U) +/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT13_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT14_MASK (0x4000U) +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT14_SHIFT (14U) +/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT14_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT15_MASK (0x8000U) +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT15_SHIFT (15U) +/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT15_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT16_MASK (0x10000U) +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT16_SHIFT (16U) +/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT16_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT17_MASK (0x20000U) +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT17_SHIFT (17U) +/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT17_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT18_MASK (0x40000U) +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT18_SHIFT (18U) +/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT18_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT19_MASK (0x80000U) +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT19_SHIFT (19U) +/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT19_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT20_MASK (0x100000U) +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT20_SHIFT (20U) +/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT20_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT21_MASK (0x200000U) +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT21_SHIFT (21U) +/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT21_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT22_MASK (0x400000U) +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT22_SHIFT (22U) +/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT22_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT23_MASK (0x800000U) +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT23_SHIFT (23U) +/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT23_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT24_MASK (0x1000000U) +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT24_SHIFT (24U) +/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT24_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT25_MASK (0x2000000U) +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT25_SHIFT (25U) +/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT25_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT26_MASK (0x4000000U) +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT26_SHIFT (26U) +/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT26_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT27_MASK (0x8000000U) +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT27_SHIFT (27U) +/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT27_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT28_MASK (0x10000000U) +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT28_SHIFT (28U) +/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT28_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT29_MASK (0x20000000U) +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT29_SHIFT (29U) +/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT29_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT30_MASK (0x40000000U) +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT30_SHIFT (30U) +/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT30_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT31_MASK (0x80000000U) +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT31_SHIFT (31U) +/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_BIT31_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W */ +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_COUNT (4U) + +/* The count of TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W */ +#define TRDC_MBC4_MBC_DOM7_MEM1_BLK_NSE_W_COUNT2 (1U) + +/*! @name MBC_DOM7_MEM2_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM2_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM2_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM2_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM2_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM2_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM2_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM2_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM2_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM2_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM2_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM2_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM2_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM2_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM2_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM2_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM2_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM2_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM2_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM2_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM2_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM2_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM2_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM2_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM2_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM2_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM2_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM2_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM2_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM2_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM2_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM2_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM2_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MBC_DOM7_MEM2_BLK_CFG_W */ +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_CFG_W_COUNT (4U) + +/* The count of TRDC_MBC4_MBC_DOM7_MEM2_BLK_CFG_W */ +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_CFG_W_COUNT2 (5U) + +/*! @name MBC_DOM7_MEM2_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ +/*! @{ */ + +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT0_MASK (0x1U) +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT0_SHIFT (0U) +/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT0_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT1_MASK (0x2U) +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT1_SHIFT (1U) +/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT1_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT2_MASK (0x4U) +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT2_SHIFT (2U) +/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT2_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT3_MASK (0x8U) +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT3_SHIFT (3U) +/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT3_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT4_MASK (0x10U) +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT4_SHIFT (4U) +/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT4_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT5_MASK (0x20U) +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT5_SHIFT (5U) +/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT5_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT6_MASK (0x40U) +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT6_SHIFT (6U) +/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT6_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT7_MASK (0x80U) +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT7_SHIFT (7U) +/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT7_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT8_MASK (0x100U) +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT8_SHIFT (8U) +/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT8_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT9_MASK (0x200U) +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT9_SHIFT (9U) +/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT9_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT10_MASK (0x400U) +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT10_SHIFT (10U) +/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT10_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT11_MASK (0x800U) +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT11_SHIFT (11U) +/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT11_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT12_MASK (0x1000U) +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT12_SHIFT (12U) +/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT12_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT13_MASK (0x2000U) +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT13_SHIFT (13U) +/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT13_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT14_MASK (0x4000U) +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT14_SHIFT (14U) +/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT14_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT15_MASK (0x8000U) +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT15_SHIFT (15U) +/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT15_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT16_MASK (0x10000U) +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT16_SHIFT (16U) +/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT16_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT17_MASK (0x20000U) +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT17_SHIFT (17U) +/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT17_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT18_MASK (0x40000U) +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT18_SHIFT (18U) +/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT18_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT19_MASK (0x80000U) +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT19_SHIFT (19U) +/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT19_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT20_MASK (0x100000U) +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT20_SHIFT (20U) +/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT20_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT21_MASK (0x200000U) +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT21_SHIFT (21U) +/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT21_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT22_MASK (0x400000U) +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT22_SHIFT (22U) +/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT22_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT23_MASK (0x800000U) +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT23_SHIFT (23U) +/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT23_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT24_MASK (0x1000000U) +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT24_SHIFT (24U) +/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT24_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT25_MASK (0x2000000U) +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT25_SHIFT (25U) +/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT25_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT26_MASK (0x4000000U) +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT26_SHIFT (26U) +/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT26_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT27_MASK (0x8000000U) +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT27_SHIFT (27U) +/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT27_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT28_MASK (0x10000000U) +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT28_SHIFT (28U) +/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT28_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT29_MASK (0x20000000U) +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT29_SHIFT (29U) +/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT29_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT30_MASK (0x40000000U) +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT30_SHIFT (30U) +/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT30_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT31_MASK (0x80000000U) +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT31_SHIFT (31U) +/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_BIT31_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W */ +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_COUNT (4U) + +/* The count of TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W */ +#define TRDC_MBC4_MBC_DOM7_MEM2_BLK_NSE_W_COUNT2 (2U) + +/*! @name MBC_DOM7_MEM3_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM3_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM3_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM3_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM3_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM3_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM3_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM3_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM3_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM3_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM3_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM3_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM3_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM3_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM3_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM3_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM3_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM3_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM3_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM3_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM3_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM3_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM3_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM3_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM3_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM3_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM3_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM3_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM3_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM3_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM3_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM3_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM3_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MBC_DOM7_MEM3_BLK_CFG_W */ +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_CFG_W_COUNT (4U) + +/* The count of TRDC_MBC4_MBC_DOM7_MEM3_BLK_CFG_W */ +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_CFG_W_COUNT2 (6U) + +/*! @name MBC_DOM7_MEM3_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ +/*! @{ */ + +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT0_MASK (0x1U) +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT0_SHIFT (0U) +/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT0_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT1_MASK (0x2U) +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT1_SHIFT (1U) +/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT1_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT2_MASK (0x4U) +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT2_SHIFT (2U) +/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT2_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT3_MASK (0x8U) +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT3_SHIFT (3U) +/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT3_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT4_MASK (0x10U) +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT4_SHIFT (4U) +/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT4_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT5_MASK (0x20U) +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT5_SHIFT (5U) +/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT5_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT6_MASK (0x40U) +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT6_SHIFT (6U) +/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT6_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT7_MASK (0x80U) +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT7_SHIFT (7U) +/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT7_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT8_MASK (0x100U) +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT8_SHIFT (8U) +/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT8_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT9_MASK (0x200U) +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT9_SHIFT (9U) +/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT9_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT10_MASK (0x400U) +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT10_SHIFT (10U) +/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT10_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT11_MASK (0x800U) +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT11_SHIFT (11U) +/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT11_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT12_MASK (0x1000U) +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT12_SHIFT (12U) +/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT12_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT13_MASK (0x2000U) +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT13_SHIFT (13U) +/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT13_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT14_MASK (0x4000U) +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT14_SHIFT (14U) +/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT14_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT15_MASK (0x8000U) +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT15_SHIFT (15U) +/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT15_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT16_MASK (0x10000U) +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT16_SHIFT (16U) +/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT16_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT17_MASK (0x20000U) +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT17_SHIFT (17U) +/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT17_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT18_MASK (0x40000U) +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT18_SHIFT (18U) +/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT18_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT19_MASK (0x80000U) +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT19_SHIFT (19U) +/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT19_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT20_MASK (0x100000U) +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT20_SHIFT (20U) +/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT20_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT21_MASK (0x200000U) +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT21_SHIFT (21U) +/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT21_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT22_MASK (0x400000U) +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT22_SHIFT (22U) +/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT22_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT23_MASK (0x800000U) +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT23_SHIFT (23U) +/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT23_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT24_MASK (0x1000000U) +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT24_SHIFT (24U) +/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT24_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT25_MASK (0x2000000U) +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT25_SHIFT (25U) +/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT25_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT26_MASK (0x4000000U) +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT26_SHIFT (26U) +/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT26_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT27_MASK (0x8000000U) +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT27_SHIFT (27U) +/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT27_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT28_MASK (0x10000000U) +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT28_SHIFT (28U) +/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT28_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT29_MASK (0x20000000U) +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT29_SHIFT (29U) +/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT29_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT30_MASK (0x40000000U) +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT30_SHIFT (30U) +/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT30_MASK) + +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT31_MASK (0x80000000U) +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT31_SHIFT (31U) +/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_BIT31_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W */ +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_COUNT (4U) + +/* The count of TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W */ +#define TRDC_MBC4_MBC_DOM7_MEM3_BLK_NSE_W_COUNT2 (2U) + +/*! @name MBC_DOM8_MEM0_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM0_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM0_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM0_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM0_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM0_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM0_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM0_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM0_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM0_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM0_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM0_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM0_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM0_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM0_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM0_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM0_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM0_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM0_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM0_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM0_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM0_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM0_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM0_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM0_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM0_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM0_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM0_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM0_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM0_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM0_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM0_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM0_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MBC_DOM8_MEM0_BLK_CFG_W */ +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_CFG_W_COUNT (4U) + +/* The count of TRDC_MBC4_MBC_DOM8_MEM0_BLK_CFG_W */ +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_CFG_W_COUNT2 (7U) + +/*! @name MBC_DOM8_MEM0_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ +/*! @{ */ + +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT0_MASK (0x1U) +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT0_SHIFT (0U) +/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT0_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT1_MASK (0x2U) +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT1_SHIFT (1U) +/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT1_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT2_MASK (0x4U) +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT2_SHIFT (2U) +/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT2_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT3_MASK (0x8U) +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT3_SHIFT (3U) +/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT3_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT4_MASK (0x10U) +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT4_SHIFT (4U) +/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT4_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT5_MASK (0x20U) +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT5_SHIFT (5U) +/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT5_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT6_MASK (0x40U) +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT6_SHIFT (6U) +/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT6_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT7_MASK (0x80U) +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT7_SHIFT (7U) +/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT7_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT8_MASK (0x100U) +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT8_SHIFT (8U) +/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT8_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT9_MASK (0x200U) +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT9_SHIFT (9U) +/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT9_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT10_MASK (0x400U) +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT10_SHIFT (10U) +/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT10_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT11_MASK (0x800U) +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT11_SHIFT (11U) +/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT11_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT12_MASK (0x1000U) +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT12_SHIFT (12U) +/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT12_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT13_MASK (0x2000U) +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT13_SHIFT (13U) +/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT13_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT14_MASK (0x4000U) +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT14_SHIFT (14U) +/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT14_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT15_MASK (0x8000U) +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT15_SHIFT (15U) +/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT15_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT16_MASK (0x10000U) +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT16_SHIFT (16U) +/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT16_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT17_MASK (0x20000U) +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT17_SHIFT (17U) +/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT17_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT18_MASK (0x40000U) +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT18_SHIFT (18U) +/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT18_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT19_MASK (0x80000U) +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT19_SHIFT (19U) +/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT19_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT20_MASK (0x100000U) +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT20_SHIFT (20U) +/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT20_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT21_MASK (0x200000U) +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT21_SHIFT (21U) +/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT21_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT22_MASK (0x400000U) +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT22_SHIFT (22U) +/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT22_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT23_MASK (0x800000U) +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT23_SHIFT (23U) +/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT23_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT24_MASK (0x1000000U) +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT24_SHIFT (24U) +/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT24_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT25_MASK (0x2000000U) +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT25_SHIFT (25U) +/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT25_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT26_MASK (0x4000000U) +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT26_SHIFT (26U) +/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT26_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT27_MASK (0x8000000U) +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT27_SHIFT (27U) +/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT27_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT28_MASK (0x10000000U) +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT28_SHIFT (28U) +/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT28_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT29_MASK (0x20000000U) +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT29_SHIFT (29U) +/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT29_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT30_MASK (0x40000000U) +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT30_SHIFT (30U) +/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT30_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT31_MASK (0x80000000U) +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT31_SHIFT (31U) +/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_BIT31_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W */ +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_COUNT (4U) + +/* The count of TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W */ +#define TRDC_MBC4_MBC_DOM8_MEM0_BLK_NSE_W_COUNT2 (2U) + +/*! @name MBC_DOM8_MEM1_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM1_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM1_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM1_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM1_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM1_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM1_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM1_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM1_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM1_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM1_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM1_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM1_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM1_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM1_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM1_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM1_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM1_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM1_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM1_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM1_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM1_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM1_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM1_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM1_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM1_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM1_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM1_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM1_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM1_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM1_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM1_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM1_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MBC_DOM8_MEM1_BLK_CFG_W */ +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_CFG_W_COUNT (4U) + +/* The count of TRDC_MBC4_MBC_DOM8_MEM1_BLK_CFG_W */ +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_CFG_W_COUNT2 (3U) + +/*! @name MBC_DOM8_MEM1_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ +/*! @{ */ + +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT0_MASK (0x1U) +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT0_SHIFT (0U) +/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT0_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT1_MASK (0x2U) +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT1_SHIFT (1U) +/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT1_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT2_MASK (0x4U) +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT2_SHIFT (2U) +/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT2_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT3_MASK (0x8U) +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT3_SHIFT (3U) +/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT3_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT4_MASK (0x10U) +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT4_SHIFT (4U) +/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT4_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT5_MASK (0x20U) +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT5_SHIFT (5U) +/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT5_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT6_MASK (0x40U) +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT6_SHIFT (6U) +/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT6_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT7_MASK (0x80U) +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT7_SHIFT (7U) +/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT7_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT8_MASK (0x100U) +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT8_SHIFT (8U) +/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT8_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT9_MASK (0x200U) +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT9_SHIFT (9U) +/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT9_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT10_MASK (0x400U) +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT10_SHIFT (10U) +/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT10_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT11_MASK (0x800U) +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT11_SHIFT (11U) +/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT11_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT12_MASK (0x1000U) +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT12_SHIFT (12U) +/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT12_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT13_MASK (0x2000U) +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT13_SHIFT (13U) +/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT13_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT14_MASK (0x4000U) +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT14_SHIFT (14U) +/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT14_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT15_MASK (0x8000U) +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT15_SHIFT (15U) +/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT15_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT16_MASK (0x10000U) +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT16_SHIFT (16U) +/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT16_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT17_MASK (0x20000U) +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT17_SHIFT (17U) +/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT17_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT18_MASK (0x40000U) +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT18_SHIFT (18U) +/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT18_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT19_MASK (0x80000U) +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT19_SHIFT (19U) +/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT19_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT20_MASK (0x100000U) +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT20_SHIFT (20U) +/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT20_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT21_MASK (0x200000U) +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT21_SHIFT (21U) +/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT21_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT22_MASK (0x400000U) +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT22_SHIFT (22U) +/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT22_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT23_MASK (0x800000U) +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT23_SHIFT (23U) +/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT23_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT24_MASK (0x1000000U) +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT24_SHIFT (24U) +/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT24_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT25_MASK (0x2000000U) +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT25_SHIFT (25U) +/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT25_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT26_MASK (0x4000000U) +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT26_SHIFT (26U) +/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT26_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT27_MASK (0x8000000U) +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT27_SHIFT (27U) +/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT27_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT28_MASK (0x10000000U) +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT28_SHIFT (28U) +/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT28_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT29_MASK (0x20000000U) +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT29_SHIFT (29U) +/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT29_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT30_MASK (0x40000000U) +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT30_SHIFT (30U) +/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT30_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT31_MASK (0x80000000U) +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT31_SHIFT (31U) +/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_BIT31_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W */ +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_COUNT (4U) + +/* The count of TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W */ +#define TRDC_MBC4_MBC_DOM8_MEM1_BLK_NSE_W_COUNT2 (1U) + +/*! @name MBC_DOM8_MEM2_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM2_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM2_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM2_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM2_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM2_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM2_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM2_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM2_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM2_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM2_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM2_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM2_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM2_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM2_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM2_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM2_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM2_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM2_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM2_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM2_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM2_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM2_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM2_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM2_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM2_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM2_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM2_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM2_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM2_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM2_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM2_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM2_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MBC_DOM8_MEM2_BLK_CFG_W */ +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_CFG_W_COUNT (4U) + +/* The count of TRDC_MBC4_MBC_DOM8_MEM2_BLK_CFG_W */ +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_CFG_W_COUNT2 (5U) + +/*! @name MBC_DOM8_MEM2_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ +/*! @{ */ + +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT0_MASK (0x1U) +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT0_SHIFT (0U) +/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT0_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT1_MASK (0x2U) +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT1_SHIFT (1U) +/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT1_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT2_MASK (0x4U) +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT2_SHIFT (2U) +/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT2_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT3_MASK (0x8U) +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT3_SHIFT (3U) +/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT3_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT4_MASK (0x10U) +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT4_SHIFT (4U) +/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT4_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT5_MASK (0x20U) +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT5_SHIFT (5U) +/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT5_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT6_MASK (0x40U) +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT6_SHIFT (6U) +/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT6_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT7_MASK (0x80U) +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT7_SHIFT (7U) +/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT7_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT8_MASK (0x100U) +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT8_SHIFT (8U) +/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT8_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT9_MASK (0x200U) +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT9_SHIFT (9U) +/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT9_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT10_MASK (0x400U) +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT10_SHIFT (10U) +/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT10_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT11_MASK (0x800U) +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT11_SHIFT (11U) +/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT11_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT12_MASK (0x1000U) +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT12_SHIFT (12U) +/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT12_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT13_MASK (0x2000U) +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT13_SHIFT (13U) +/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT13_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT14_MASK (0x4000U) +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT14_SHIFT (14U) +/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT14_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT15_MASK (0x8000U) +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT15_SHIFT (15U) +/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT15_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT16_MASK (0x10000U) +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT16_SHIFT (16U) +/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT16_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT17_MASK (0x20000U) +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT17_SHIFT (17U) +/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT17_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT18_MASK (0x40000U) +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT18_SHIFT (18U) +/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT18_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT19_MASK (0x80000U) +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT19_SHIFT (19U) +/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT19_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT20_MASK (0x100000U) +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT20_SHIFT (20U) +/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT20_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT21_MASK (0x200000U) +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT21_SHIFT (21U) +/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT21_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT22_MASK (0x400000U) +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT22_SHIFT (22U) +/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT22_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT23_MASK (0x800000U) +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT23_SHIFT (23U) +/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT23_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT24_MASK (0x1000000U) +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT24_SHIFT (24U) +/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT24_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT25_MASK (0x2000000U) +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT25_SHIFT (25U) +/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT25_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT26_MASK (0x4000000U) +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT26_SHIFT (26U) +/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT26_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT27_MASK (0x8000000U) +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT27_SHIFT (27U) +/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT27_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT28_MASK (0x10000000U) +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT28_SHIFT (28U) +/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT28_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT29_MASK (0x20000000U) +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT29_SHIFT (29U) +/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT29_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT30_MASK (0x40000000U) +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT30_SHIFT (30U) +/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT30_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT31_MASK (0x80000000U) +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT31_SHIFT (31U) +/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_BIT31_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W */ +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_COUNT (4U) + +/* The count of TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W */ +#define TRDC_MBC4_MBC_DOM8_MEM2_BLK_NSE_W_COUNT2 (2U) + +/*! @name MBC_DOM8_MEM3_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM3_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM3_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM3_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM3_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM3_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM3_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM3_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM3_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM3_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM3_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM3_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM3_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM3_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM3_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM3_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM3_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM3_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM3_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM3_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM3_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM3_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM3_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM3_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM3_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM3_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM3_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM3_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM3_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM3_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM3_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM3_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM3_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MBC_DOM8_MEM3_BLK_CFG_W */ +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_CFG_W_COUNT (4U) + +/* The count of TRDC_MBC4_MBC_DOM8_MEM3_BLK_CFG_W */ +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_CFG_W_COUNT2 (6U) + +/*! @name MBC_DOM8_MEM3_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ +/*! @{ */ + +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT0_MASK (0x1U) +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT0_SHIFT (0U) +/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT0_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT1_MASK (0x2U) +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT1_SHIFT (1U) +/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT1_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT2_MASK (0x4U) +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT2_SHIFT (2U) +/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT2_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT3_MASK (0x8U) +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT3_SHIFT (3U) +/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT3_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT4_MASK (0x10U) +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT4_SHIFT (4U) +/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT4_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT5_MASK (0x20U) +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT5_SHIFT (5U) +/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT5_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT6_MASK (0x40U) +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT6_SHIFT (6U) +/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT6_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT7_MASK (0x80U) +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT7_SHIFT (7U) +/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT7_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT8_MASK (0x100U) +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT8_SHIFT (8U) +/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT8_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT9_MASK (0x200U) +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT9_SHIFT (9U) +/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT9_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT10_MASK (0x400U) +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT10_SHIFT (10U) +/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT10_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT11_MASK (0x800U) +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT11_SHIFT (11U) +/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT11_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT12_MASK (0x1000U) +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT12_SHIFT (12U) +/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT12_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT13_MASK (0x2000U) +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT13_SHIFT (13U) +/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT13_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT14_MASK (0x4000U) +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT14_SHIFT (14U) +/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT14_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT15_MASK (0x8000U) +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT15_SHIFT (15U) +/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT15_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT16_MASK (0x10000U) +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT16_SHIFT (16U) +/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT16_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT17_MASK (0x20000U) +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT17_SHIFT (17U) +/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT17_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT18_MASK (0x40000U) +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT18_SHIFT (18U) +/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT18_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT19_MASK (0x80000U) +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT19_SHIFT (19U) +/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT19_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT20_MASK (0x100000U) +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT20_SHIFT (20U) +/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT20_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT21_MASK (0x200000U) +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT21_SHIFT (21U) +/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT21_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT22_MASK (0x400000U) +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT22_SHIFT (22U) +/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT22_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT23_MASK (0x800000U) +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT23_SHIFT (23U) +/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT23_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT24_MASK (0x1000000U) +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT24_SHIFT (24U) +/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT24_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT25_MASK (0x2000000U) +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT25_SHIFT (25U) +/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT25_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT26_MASK (0x4000000U) +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT26_SHIFT (26U) +/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT26_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT27_MASK (0x8000000U) +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT27_SHIFT (27U) +/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT27_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT28_MASK (0x10000000U) +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT28_SHIFT (28U) +/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT28_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT29_MASK (0x20000000U) +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT29_SHIFT (29U) +/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT29_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT30_MASK (0x40000000U) +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT30_SHIFT (30U) +/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT30_MASK) + +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT31_MASK (0x80000000U) +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT31_SHIFT (31U) +/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_BIT31_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W */ +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_COUNT (4U) + +/* The count of TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W */ +#define TRDC_MBC4_MBC_DOM8_MEM3_BLK_NSE_W_COUNT2 (2U) + +/*! @name MBC_DOM9_MEM0_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM0_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM0_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM0_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM0_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM0_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM0_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM0_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM0_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM0_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM0_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM0_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM0_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM0_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM0_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM0_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM0_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM0_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM0_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM0_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM0_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM0_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM0_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM0_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM0_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM0_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM0_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM0_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM0_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM0_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM0_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM0_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM0_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MBC_DOM9_MEM0_BLK_CFG_W */ +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_CFG_W_COUNT (4U) + +/* The count of TRDC_MBC4_MBC_DOM9_MEM0_BLK_CFG_W */ +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_CFG_W_COUNT2 (7U) + +/*! @name MBC_DOM9_MEM0_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ +/*! @{ */ + +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT0_MASK (0x1U) +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT0_SHIFT (0U) +/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT0_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT1_MASK (0x2U) +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT1_SHIFT (1U) +/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT1_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT2_MASK (0x4U) +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT2_SHIFT (2U) +/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT2_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT3_MASK (0x8U) +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT3_SHIFT (3U) +/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT3_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT4_MASK (0x10U) +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT4_SHIFT (4U) +/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT4_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT5_MASK (0x20U) +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT5_SHIFT (5U) +/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT5_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT6_MASK (0x40U) +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT6_SHIFT (6U) +/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT6_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT7_MASK (0x80U) +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT7_SHIFT (7U) +/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT7_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT8_MASK (0x100U) +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT8_SHIFT (8U) +/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT8_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT9_MASK (0x200U) +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT9_SHIFT (9U) +/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT9_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT10_MASK (0x400U) +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT10_SHIFT (10U) +/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT10_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT11_MASK (0x800U) +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT11_SHIFT (11U) +/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT11_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT12_MASK (0x1000U) +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT12_SHIFT (12U) +/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT12_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT13_MASK (0x2000U) +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT13_SHIFT (13U) +/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT13_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT14_MASK (0x4000U) +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT14_SHIFT (14U) +/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT14_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT15_MASK (0x8000U) +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT15_SHIFT (15U) +/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT15_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT16_MASK (0x10000U) +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT16_SHIFT (16U) +/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT16_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT17_MASK (0x20000U) +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT17_SHIFT (17U) +/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT17_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT18_MASK (0x40000U) +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT18_SHIFT (18U) +/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT18_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT19_MASK (0x80000U) +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT19_SHIFT (19U) +/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT19_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT20_MASK (0x100000U) +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT20_SHIFT (20U) +/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT20_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT21_MASK (0x200000U) +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT21_SHIFT (21U) +/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT21_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT22_MASK (0x400000U) +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT22_SHIFT (22U) +/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT22_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT23_MASK (0x800000U) +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT23_SHIFT (23U) +/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT23_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT24_MASK (0x1000000U) +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT24_SHIFT (24U) +/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT24_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT25_MASK (0x2000000U) +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT25_SHIFT (25U) +/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT25_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT26_MASK (0x4000000U) +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT26_SHIFT (26U) +/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT26_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT27_MASK (0x8000000U) +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT27_SHIFT (27U) +/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT27_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT28_MASK (0x10000000U) +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT28_SHIFT (28U) +/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT28_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT29_MASK (0x20000000U) +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT29_SHIFT (29U) +/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT29_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT30_MASK (0x40000000U) +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT30_SHIFT (30U) +/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT30_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT31_MASK (0x80000000U) +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT31_SHIFT (31U) +/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_BIT31_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W */ +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_COUNT (4U) + +/* The count of TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W */ +#define TRDC_MBC4_MBC_DOM9_MEM0_BLK_NSE_W_COUNT2 (2U) + +/*! @name MBC_DOM9_MEM1_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM1_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM1_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM1_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM1_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM1_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM1_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM1_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM1_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM1_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM1_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM1_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM1_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM1_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM1_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM1_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM1_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM1_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM1_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM1_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM1_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM1_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM1_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM1_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM1_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM1_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM1_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM1_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM1_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM1_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM1_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM1_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM1_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MBC_DOM9_MEM1_BLK_CFG_W */ +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_CFG_W_COUNT (4U) + +/* The count of TRDC_MBC4_MBC_DOM9_MEM1_BLK_CFG_W */ +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_CFG_W_COUNT2 (3U) + +/*! @name MBC_DOM9_MEM1_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ +/*! @{ */ + +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT0_MASK (0x1U) +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT0_SHIFT (0U) +/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT0_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT1_MASK (0x2U) +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT1_SHIFT (1U) +/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT1_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT2_MASK (0x4U) +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT2_SHIFT (2U) +/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT2_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT3_MASK (0x8U) +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT3_SHIFT (3U) +/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT3_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT4_MASK (0x10U) +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT4_SHIFT (4U) +/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT4_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT5_MASK (0x20U) +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT5_SHIFT (5U) +/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT5_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT6_MASK (0x40U) +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT6_SHIFT (6U) +/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT6_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT7_MASK (0x80U) +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT7_SHIFT (7U) +/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT7_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT8_MASK (0x100U) +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT8_SHIFT (8U) +/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT8_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT9_MASK (0x200U) +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT9_SHIFT (9U) +/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT9_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT10_MASK (0x400U) +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT10_SHIFT (10U) +/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT10_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT11_MASK (0x800U) +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT11_SHIFT (11U) +/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT11_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT12_MASK (0x1000U) +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT12_SHIFT (12U) +/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT12_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT13_MASK (0x2000U) +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT13_SHIFT (13U) +/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT13_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT14_MASK (0x4000U) +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT14_SHIFT (14U) +/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT14_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT15_MASK (0x8000U) +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT15_SHIFT (15U) +/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT15_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT16_MASK (0x10000U) +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT16_SHIFT (16U) +/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT16_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT17_MASK (0x20000U) +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT17_SHIFT (17U) +/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT17_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT18_MASK (0x40000U) +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT18_SHIFT (18U) +/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT18_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT19_MASK (0x80000U) +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT19_SHIFT (19U) +/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT19_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT20_MASK (0x100000U) +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT20_SHIFT (20U) +/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT20_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT21_MASK (0x200000U) +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT21_SHIFT (21U) +/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT21_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT22_MASK (0x400000U) +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT22_SHIFT (22U) +/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT22_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT23_MASK (0x800000U) +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT23_SHIFT (23U) +/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT23_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT24_MASK (0x1000000U) +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT24_SHIFT (24U) +/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT24_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT25_MASK (0x2000000U) +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT25_SHIFT (25U) +/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT25_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT26_MASK (0x4000000U) +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT26_SHIFT (26U) +/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT26_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT27_MASK (0x8000000U) +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT27_SHIFT (27U) +/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT27_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT28_MASK (0x10000000U) +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT28_SHIFT (28U) +/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT28_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT29_MASK (0x20000000U) +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT29_SHIFT (29U) +/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT29_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT30_MASK (0x40000000U) +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT30_SHIFT (30U) +/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT30_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT31_MASK (0x80000000U) +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT31_SHIFT (31U) +/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_BIT31_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W */ +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_COUNT (4U) + +/* The count of TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W */ +#define TRDC_MBC4_MBC_DOM9_MEM1_BLK_NSE_W_COUNT2 (1U) + +/*! @name MBC_DOM9_MEM2_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM2_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM2_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM2_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM2_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM2_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM2_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM2_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM2_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM2_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM2_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM2_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM2_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM2_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM2_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM2_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM2_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM2_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM2_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM2_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM2_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM2_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM2_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM2_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM2_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM2_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM2_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM2_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM2_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM2_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM2_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM2_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM2_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MBC_DOM9_MEM2_BLK_CFG_W */ +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_CFG_W_COUNT (4U) + +/* The count of TRDC_MBC4_MBC_DOM9_MEM2_BLK_CFG_W */ +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_CFG_W_COUNT2 (5U) + +/*! @name MBC_DOM9_MEM2_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ +/*! @{ */ + +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT0_MASK (0x1U) +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT0_SHIFT (0U) +/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT0_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT1_MASK (0x2U) +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT1_SHIFT (1U) +/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT1_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT2_MASK (0x4U) +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT2_SHIFT (2U) +/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT2_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT3_MASK (0x8U) +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT3_SHIFT (3U) +/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT3_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT4_MASK (0x10U) +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT4_SHIFT (4U) +/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT4_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT5_MASK (0x20U) +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT5_SHIFT (5U) +/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT5_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT6_MASK (0x40U) +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT6_SHIFT (6U) +/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT6_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT7_MASK (0x80U) +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT7_SHIFT (7U) +/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT7_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT8_MASK (0x100U) +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT8_SHIFT (8U) +/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT8_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT9_MASK (0x200U) +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT9_SHIFT (9U) +/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT9_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT10_MASK (0x400U) +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT10_SHIFT (10U) +/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT10_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT11_MASK (0x800U) +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT11_SHIFT (11U) +/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT11_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT12_MASK (0x1000U) +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT12_SHIFT (12U) +/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT12_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT13_MASK (0x2000U) +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT13_SHIFT (13U) +/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT13_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT14_MASK (0x4000U) +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT14_SHIFT (14U) +/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT14_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT15_MASK (0x8000U) +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT15_SHIFT (15U) +/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT15_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT16_MASK (0x10000U) +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT16_SHIFT (16U) +/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT16_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT17_MASK (0x20000U) +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT17_SHIFT (17U) +/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT17_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT18_MASK (0x40000U) +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT18_SHIFT (18U) +/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT18_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT19_MASK (0x80000U) +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT19_SHIFT (19U) +/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT19_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT20_MASK (0x100000U) +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT20_SHIFT (20U) +/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT20_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT21_MASK (0x200000U) +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT21_SHIFT (21U) +/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT21_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT22_MASK (0x400000U) +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT22_SHIFT (22U) +/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT22_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT23_MASK (0x800000U) +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT23_SHIFT (23U) +/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT23_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT24_MASK (0x1000000U) +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT24_SHIFT (24U) +/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT24_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT25_MASK (0x2000000U) +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT25_SHIFT (25U) +/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT25_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT26_MASK (0x4000000U) +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT26_SHIFT (26U) +/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT26_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT27_MASK (0x8000000U) +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT27_SHIFT (27U) +/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT27_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT28_MASK (0x10000000U) +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT28_SHIFT (28U) +/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT28_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT29_MASK (0x20000000U) +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT29_SHIFT (29U) +/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT29_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT30_MASK (0x40000000U) +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT30_SHIFT (30U) +/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT30_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT31_MASK (0x80000000U) +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT31_SHIFT (31U) +/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_BIT31_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W */ +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_COUNT (4U) + +/* The count of TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W */ +#define TRDC_MBC4_MBC_DOM9_MEM2_BLK_NSE_W_COUNT2 (2U) + +/*! @name MBC_DOM9_MEM3_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM3_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM3_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM3_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM3_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM3_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM3_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM3_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM3_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM3_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM3_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM3_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM3_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM3_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM3_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM3_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM3_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM3_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM3_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM3_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM3_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM3_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM3_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM3_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM3_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM3_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM3_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM3_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM3_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM3_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM3_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM3_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM3_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MBC_DOM9_MEM3_BLK_CFG_W */ +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_CFG_W_COUNT (4U) + +/* The count of TRDC_MBC4_MBC_DOM9_MEM3_BLK_CFG_W */ +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_CFG_W_COUNT2 (6U) + +/*! @name MBC_DOM9_MEM3_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ +/*! @{ */ + +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT0_MASK (0x1U) +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT0_SHIFT (0U) +/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT0_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT1_MASK (0x2U) +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT1_SHIFT (1U) +/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT1_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT2_MASK (0x4U) +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT2_SHIFT (2U) +/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT2_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT3_MASK (0x8U) +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT3_SHIFT (3U) +/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT3_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT4_MASK (0x10U) +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT4_SHIFT (4U) +/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT4_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT5_MASK (0x20U) +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT5_SHIFT (5U) +/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT5_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT6_MASK (0x40U) +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT6_SHIFT (6U) +/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT6_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT7_MASK (0x80U) +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT7_SHIFT (7U) +/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT7_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT8_MASK (0x100U) +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT8_SHIFT (8U) +/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT8_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT9_MASK (0x200U) +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT9_SHIFT (9U) +/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT9_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT10_MASK (0x400U) +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT10_SHIFT (10U) +/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT10_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT11_MASK (0x800U) +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT11_SHIFT (11U) +/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT11_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT12_MASK (0x1000U) +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT12_SHIFT (12U) +/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT12_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT13_MASK (0x2000U) +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT13_SHIFT (13U) +/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT13_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT14_MASK (0x4000U) +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT14_SHIFT (14U) +/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT14_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT15_MASK (0x8000U) +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT15_SHIFT (15U) +/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT15_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT16_MASK (0x10000U) +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT16_SHIFT (16U) +/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT16_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT17_MASK (0x20000U) +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT17_SHIFT (17U) +/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT17_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT18_MASK (0x40000U) +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT18_SHIFT (18U) +/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT18_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT19_MASK (0x80000U) +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT19_SHIFT (19U) +/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT19_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT20_MASK (0x100000U) +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT20_SHIFT (20U) +/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT20_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT21_MASK (0x200000U) +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT21_SHIFT (21U) +/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT21_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT22_MASK (0x400000U) +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT22_SHIFT (22U) +/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT22_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT23_MASK (0x800000U) +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT23_SHIFT (23U) +/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT23_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT24_MASK (0x1000000U) +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT24_SHIFT (24U) +/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT24_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT25_MASK (0x2000000U) +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT25_SHIFT (25U) +/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT25_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT26_MASK (0x4000000U) +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT26_SHIFT (26U) +/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT26_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT27_MASK (0x8000000U) +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT27_SHIFT (27U) +/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT27_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT28_MASK (0x10000000U) +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT28_SHIFT (28U) +/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT28_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT29_MASK (0x20000000U) +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT29_SHIFT (29U) +/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT29_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT30_MASK (0x40000000U) +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT30_SHIFT (30U) +/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT30_MASK) + +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT31_MASK (0x80000000U) +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT31_SHIFT (31U) +/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_BIT31_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W */ +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_COUNT (4U) + +/* The count of TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W */ +#define TRDC_MBC4_MBC_DOM9_MEM3_BLK_NSE_W_COUNT2 (2U) + +/*! @name MBC_DOM10_MEM0_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM0_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM0_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM0_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM0_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM0_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM0_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM0_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM0_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM0_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM0_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM0_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM0_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM0_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM0_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM0_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM0_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM0_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM0_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM0_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM0_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM0_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM0_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM0_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM0_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM0_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM0_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM0_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM0_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM0_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM0_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM0_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM0_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MBC_DOM10_MEM0_BLK_CFG_W */ +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_CFG_W_COUNT (4U) + +/* The count of TRDC_MBC4_MBC_DOM10_MEM0_BLK_CFG_W */ +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_CFG_W_COUNT2 (7U) + +/*! @name MBC_DOM10_MEM0_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ +/*! @{ */ + +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT0_MASK (0x1U) +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT0_SHIFT (0U) +/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT0_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT1_MASK (0x2U) +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT1_SHIFT (1U) +/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT1_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT2_MASK (0x4U) +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT2_SHIFT (2U) +/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT2_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT3_MASK (0x8U) +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT3_SHIFT (3U) +/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT3_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT4_MASK (0x10U) +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT4_SHIFT (4U) +/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT4_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT5_MASK (0x20U) +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT5_SHIFT (5U) +/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT5_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT6_MASK (0x40U) +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT6_SHIFT (6U) +/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT6_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT7_MASK (0x80U) +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT7_SHIFT (7U) +/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT7_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT8_MASK (0x100U) +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT8_SHIFT (8U) +/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT8_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT9_MASK (0x200U) +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT9_SHIFT (9U) +/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT9_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT10_MASK (0x400U) +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT10_SHIFT (10U) +/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT10_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT11_MASK (0x800U) +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT11_SHIFT (11U) +/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT11_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT12_MASK (0x1000U) +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT12_SHIFT (12U) +/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT12_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT13_MASK (0x2000U) +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT13_SHIFT (13U) +/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT13_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT14_MASK (0x4000U) +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT14_SHIFT (14U) +/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT14_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT15_MASK (0x8000U) +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT15_SHIFT (15U) +/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT15_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT16_MASK (0x10000U) +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT16_SHIFT (16U) +/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT16_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT17_MASK (0x20000U) +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT17_SHIFT (17U) +/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT17_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT18_MASK (0x40000U) +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT18_SHIFT (18U) +/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT18_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT19_MASK (0x80000U) +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT19_SHIFT (19U) +/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT19_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT20_MASK (0x100000U) +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT20_SHIFT (20U) +/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT20_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT21_MASK (0x200000U) +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT21_SHIFT (21U) +/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT21_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT22_MASK (0x400000U) +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT22_SHIFT (22U) +/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT22_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT23_MASK (0x800000U) +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT23_SHIFT (23U) +/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT23_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT24_MASK (0x1000000U) +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT24_SHIFT (24U) +/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT24_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT25_MASK (0x2000000U) +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT25_SHIFT (25U) +/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT25_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT26_MASK (0x4000000U) +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT26_SHIFT (26U) +/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT26_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT27_MASK (0x8000000U) +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT27_SHIFT (27U) +/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT27_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT28_MASK (0x10000000U) +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT28_SHIFT (28U) +/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT28_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT29_MASK (0x20000000U) +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT29_SHIFT (29U) +/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT29_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT30_MASK (0x40000000U) +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT30_SHIFT (30U) +/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT30_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT31_MASK (0x80000000U) +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT31_SHIFT (31U) +/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_BIT31_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W */ +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_COUNT (4U) + +/* The count of TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W */ +#define TRDC_MBC4_MBC_DOM10_MEM0_BLK_NSE_W_COUNT2 (2U) + +/*! @name MBC_DOM10_MEM1_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM1_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM1_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM1_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM1_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM1_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM1_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM1_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM1_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM1_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM1_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM1_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM1_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM1_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM1_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM1_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM1_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM1_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM1_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM1_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM1_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM1_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM1_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM1_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM1_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM1_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM1_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM1_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM1_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM1_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM1_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM1_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM1_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MBC_DOM10_MEM1_BLK_CFG_W */ +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_CFG_W_COUNT (4U) + +/* The count of TRDC_MBC4_MBC_DOM10_MEM1_BLK_CFG_W */ +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_CFG_W_COUNT2 (3U) + +/*! @name MBC_DOM10_MEM1_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ +/*! @{ */ + +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT0_MASK (0x1U) +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT0_SHIFT (0U) +/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT0_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT1_MASK (0x2U) +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT1_SHIFT (1U) +/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT1_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT2_MASK (0x4U) +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT2_SHIFT (2U) +/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT2_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT3_MASK (0x8U) +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT3_SHIFT (3U) +/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT3_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT4_MASK (0x10U) +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT4_SHIFT (4U) +/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT4_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT5_MASK (0x20U) +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT5_SHIFT (5U) +/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT5_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT6_MASK (0x40U) +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT6_SHIFT (6U) +/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT6_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT7_MASK (0x80U) +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT7_SHIFT (7U) +/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT7_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT8_MASK (0x100U) +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT8_SHIFT (8U) +/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT8_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT9_MASK (0x200U) +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT9_SHIFT (9U) +/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT9_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT10_MASK (0x400U) +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT10_SHIFT (10U) +/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT10_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT11_MASK (0x800U) +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT11_SHIFT (11U) +/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT11_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT12_MASK (0x1000U) +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT12_SHIFT (12U) +/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT12_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT13_MASK (0x2000U) +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT13_SHIFT (13U) +/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT13_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT14_MASK (0x4000U) +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT14_SHIFT (14U) +/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT14_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT15_MASK (0x8000U) +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT15_SHIFT (15U) +/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT15_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT16_MASK (0x10000U) +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT16_SHIFT (16U) +/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT16_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT17_MASK (0x20000U) +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT17_SHIFT (17U) +/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT17_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT18_MASK (0x40000U) +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT18_SHIFT (18U) +/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT18_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT19_MASK (0x80000U) +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT19_SHIFT (19U) +/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT19_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT20_MASK (0x100000U) +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT20_SHIFT (20U) +/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT20_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT21_MASK (0x200000U) +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT21_SHIFT (21U) +/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT21_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT22_MASK (0x400000U) +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT22_SHIFT (22U) +/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT22_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT23_MASK (0x800000U) +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT23_SHIFT (23U) +/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT23_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT24_MASK (0x1000000U) +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT24_SHIFT (24U) +/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT24_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT25_MASK (0x2000000U) +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT25_SHIFT (25U) +/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT25_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT26_MASK (0x4000000U) +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT26_SHIFT (26U) +/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT26_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT27_MASK (0x8000000U) +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT27_SHIFT (27U) +/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT27_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT28_MASK (0x10000000U) +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT28_SHIFT (28U) +/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT28_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT29_MASK (0x20000000U) +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT29_SHIFT (29U) +/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT29_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT30_MASK (0x40000000U) +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT30_SHIFT (30U) +/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT30_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT31_MASK (0x80000000U) +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT31_SHIFT (31U) +/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_BIT31_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W */ +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_COUNT (4U) + +/* The count of TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W */ +#define TRDC_MBC4_MBC_DOM10_MEM1_BLK_NSE_W_COUNT2 (1U) + +/*! @name MBC_DOM10_MEM2_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM2_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM2_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM2_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM2_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM2_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM2_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM2_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM2_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM2_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM2_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM2_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM2_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM2_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM2_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM2_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM2_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM2_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM2_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM2_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM2_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM2_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM2_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM2_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM2_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM2_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM2_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM2_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM2_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM2_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM2_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM2_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM2_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MBC_DOM10_MEM2_BLK_CFG_W */ +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_CFG_W_COUNT (4U) + +/* The count of TRDC_MBC4_MBC_DOM10_MEM2_BLK_CFG_W */ +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_CFG_W_COUNT2 (5U) + +/*! @name MBC_DOM10_MEM2_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ +/*! @{ */ + +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT0_MASK (0x1U) +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT0_SHIFT (0U) +/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT0_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT1_MASK (0x2U) +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT1_SHIFT (1U) +/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT1_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT2_MASK (0x4U) +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT2_SHIFT (2U) +/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT2_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT3_MASK (0x8U) +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT3_SHIFT (3U) +/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT3_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT4_MASK (0x10U) +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT4_SHIFT (4U) +/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT4_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT5_MASK (0x20U) +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT5_SHIFT (5U) +/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT5_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT6_MASK (0x40U) +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT6_SHIFT (6U) +/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT6_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT7_MASK (0x80U) +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT7_SHIFT (7U) +/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT7_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT8_MASK (0x100U) +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT8_SHIFT (8U) +/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT8_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT9_MASK (0x200U) +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT9_SHIFT (9U) +/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT9_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT10_MASK (0x400U) +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT10_SHIFT (10U) +/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT10_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT11_MASK (0x800U) +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT11_SHIFT (11U) +/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT11_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT12_MASK (0x1000U) +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT12_SHIFT (12U) +/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT12_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT13_MASK (0x2000U) +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT13_SHIFT (13U) +/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT13_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT14_MASK (0x4000U) +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT14_SHIFT (14U) +/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT14_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT15_MASK (0x8000U) +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT15_SHIFT (15U) +/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT15_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT16_MASK (0x10000U) +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT16_SHIFT (16U) +/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT16_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT17_MASK (0x20000U) +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT17_SHIFT (17U) +/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT17_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT18_MASK (0x40000U) +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT18_SHIFT (18U) +/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT18_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT19_MASK (0x80000U) +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT19_SHIFT (19U) +/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT19_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT20_MASK (0x100000U) +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT20_SHIFT (20U) +/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT20_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT21_MASK (0x200000U) +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT21_SHIFT (21U) +/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT21_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT22_MASK (0x400000U) +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT22_SHIFT (22U) +/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT22_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT23_MASK (0x800000U) +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT23_SHIFT (23U) +/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT23_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT24_MASK (0x1000000U) +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT24_SHIFT (24U) +/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT24_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT25_MASK (0x2000000U) +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT25_SHIFT (25U) +/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT25_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT26_MASK (0x4000000U) +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT26_SHIFT (26U) +/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT26_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT27_MASK (0x8000000U) +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT27_SHIFT (27U) +/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT27_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT28_MASK (0x10000000U) +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT28_SHIFT (28U) +/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT28_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT29_MASK (0x20000000U) +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT29_SHIFT (29U) +/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT29_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT30_MASK (0x40000000U) +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT30_SHIFT (30U) +/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT30_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT31_MASK (0x80000000U) +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT31_SHIFT (31U) +/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_BIT31_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W */ +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_COUNT (4U) + +/* The count of TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W */ +#define TRDC_MBC4_MBC_DOM10_MEM2_BLK_NSE_W_COUNT2 (2U) + +/*! @name MBC_DOM10_MEM3_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM3_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM3_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM3_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM3_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM3_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM3_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM3_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM3_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM3_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM3_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM3_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM3_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM3_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM3_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM3_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM3_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM3_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM3_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM3_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM3_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM3_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM3_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM3_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM3_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM3_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM3_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM3_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM3_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM3_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM3_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM3_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM3_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MBC_DOM10_MEM3_BLK_CFG_W */ +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_CFG_W_COUNT (4U) + +/* The count of TRDC_MBC4_MBC_DOM10_MEM3_BLK_CFG_W */ +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_CFG_W_COUNT2 (6U) + +/*! @name MBC_DOM10_MEM3_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ +/*! @{ */ + +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT0_MASK (0x1U) +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT0_SHIFT (0U) +/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT0_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT1_MASK (0x2U) +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT1_SHIFT (1U) +/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT1_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT2_MASK (0x4U) +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT2_SHIFT (2U) +/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT2_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT3_MASK (0x8U) +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT3_SHIFT (3U) +/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT3_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT4_MASK (0x10U) +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT4_SHIFT (4U) +/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT4_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT5_MASK (0x20U) +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT5_SHIFT (5U) +/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT5_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT6_MASK (0x40U) +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT6_SHIFT (6U) +/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT6_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT7_MASK (0x80U) +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT7_SHIFT (7U) +/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT7_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT8_MASK (0x100U) +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT8_SHIFT (8U) +/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT8_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT9_MASK (0x200U) +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT9_SHIFT (9U) +/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT9_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT10_MASK (0x400U) +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT10_SHIFT (10U) +/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT10_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT11_MASK (0x800U) +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT11_SHIFT (11U) +/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT11_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT12_MASK (0x1000U) +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT12_SHIFT (12U) +/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT12_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT13_MASK (0x2000U) +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT13_SHIFT (13U) +/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT13_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT14_MASK (0x4000U) +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT14_SHIFT (14U) +/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT14_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT15_MASK (0x8000U) +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT15_SHIFT (15U) +/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT15_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT16_MASK (0x10000U) +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT16_SHIFT (16U) +/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT16_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT17_MASK (0x20000U) +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT17_SHIFT (17U) +/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT17_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT18_MASK (0x40000U) +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT18_SHIFT (18U) +/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT18_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT19_MASK (0x80000U) +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT19_SHIFT (19U) +/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT19_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT20_MASK (0x100000U) +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT20_SHIFT (20U) +/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT20_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT21_MASK (0x200000U) +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT21_SHIFT (21U) +/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT21_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT22_MASK (0x400000U) +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT22_SHIFT (22U) +/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT22_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT23_MASK (0x800000U) +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT23_SHIFT (23U) +/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT23_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT24_MASK (0x1000000U) +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT24_SHIFT (24U) +/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT24_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT25_MASK (0x2000000U) +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT25_SHIFT (25U) +/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT25_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT26_MASK (0x4000000U) +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT26_SHIFT (26U) +/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT26_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT27_MASK (0x8000000U) +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT27_SHIFT (27U) +/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT27_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT28_MASK (0x10000000U) +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT28_SHIFT (28U) +/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT28_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT29_MASK (0x20000000U) +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT29_SHIFT (29U) +/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT29_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT30_MASK (0x40000000U) +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT30_SHIFT (30U) +/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT30_MASK) + +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT31_MASK (0x80000000U) +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT31_SHIFT (31U) +/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_BIT31_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W */ +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_COUNT (4U) + +/* The count of TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W */ +#define TRDC_MBC4_MBC_DOM10_MEM3_BLK_NSE_W_COUNT2 (2U) + +/*! @name MBC_DOM11_MEM0_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM0_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM0_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM0_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM0_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM0_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM0_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM0_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM0_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM0_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM0_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM0_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM0_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM0_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM0_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM0_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM0_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM0_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM0_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM0_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM0_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM0_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM0_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM0_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM0_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM0_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM0_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM0_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM0_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM0_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM0_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM0_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM0_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MBC_DOM11_MEM0_BLK_CFG_W */ +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_CFG_W_COUNT (4U) + +/* The count of TRDC_MBC4_MBC_DOM11_MEM0_BLK_CFG_W */ +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_CFG_W_COUNT2 (7U) + +/*! @name MBC_DOM11_MEM0_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ +/*! @{ */ + +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT0_MASK (0x1U) +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT0_SHIFT (0U) +/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT0_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT1_MASK (0x2U) +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT1_SHIFT (1U) +/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT1_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT2_MASK (0x4U) +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT2_SHIFT (2U) +/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT2_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT3_MASK (0x8U) +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT3_SHIFT (3U) +/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT3_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT4_MASK (0x10U) +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT4_SHIFT (4U) +/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT4_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT5_MASK (0x20U) +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT5_SHIFT (5U) +/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT5_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT6_MASK (0x40U) +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT6_SHIFT (6U) +/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT6_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT7_MASK (0x80U) +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT7_SHIFT (7U) +/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT7_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT8_MASK (0x100U) +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT8_SHIFT (8U) +/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT8_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT9_MASK (0x200U) +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT9_SHIFT (9U) +/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT9_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT10_MASK (0x400U) +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT10_SHIFT (10U) +/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT10_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT11_MASK (0x800U) +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT11_SHIFT (11U) +/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT11_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT12_MASK (0x1000U) +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT12_SHIFT (12U) +/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT12_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT13_MASK (0x2000U) +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT13_SHIFT (13U) +/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT13_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT14_MASK (0x4000U) +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT14_SHIFT (14U) +/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT14_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT15_MASK (0x8000U) +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT15_SHIFT (15U) +/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT15_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT16_MASK (0x10000U) +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT16_SHIFT (16U) +/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT16_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT17_MASK (0x20000U) +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT17_SHIFT (17U) +/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT17_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT18_MASK (0x40000U) +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT18_SHIFT (18U) +/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT18_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT19_MASK (0x80000U) +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT19_SHIFT (19U) +/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT19_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT20_MASK (0x100000U) +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT20_SHIFT (20U) +/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT20_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT21_MASK (0x200000U) +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT21_SHIFT (21U) +/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT21_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT22_MASK (0x400000U) +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT22_SHIFT (22U) +/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT22_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT23_MASK (0x800000U) +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT23_SHIFT (23U) +/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT23_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT24_MASK (0x1000000U) +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT24_SHIFT (24U) +/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT24_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT25_MASK (0x2000000U) +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT25_SHIFT (25U) +/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT25_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT26_MASK (0x4000000U) +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT26_SHIFT (26U) +/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT26_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT27_MASK (0x8000000U) +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT27_SHIFT (27U) +/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT27_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT28_MASK (0x10000000U) +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT28_SHIFT (28U) +/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT28_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT29_MASK (0x20000000U) +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT29_SHIFT (29U) +/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT29_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT30_MASK (0x40000000U) +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT30_SHIFT (30U) +/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT30_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT31_MASK (0x80000000U) +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT31_SHIFT (31U) +/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_BIT31_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W */ +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_COUNT (4U) + +/* The count of TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W */ +#define TRDC_MBC4_MBC_DOM11_MEM0_BLK_NSE_W_COUNT2 (2U) + +/*! @name MBC_DOM11_MEM1_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM1_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM1_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM1_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM1_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM1_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM1_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM1_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM1_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM1_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM1_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM1_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM1_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM1_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM1_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM1_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM1_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM1_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM1_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM1_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM1_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM1_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM1_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM1_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM1_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM1_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM1_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM1_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM1_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM1_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM1_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM1_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM1_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MBC_DOM11_MEM1_BLK_CFG_W */ +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_CFG_W_COUNT (4U) + +/* The count of TRDC_MBC4_MBC_DOM11_MEM1_BLK_CFG_W */ +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_CFG_W_COUNT2 (3U) + +/*! @name MBC_DOM11_MEM1_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ +/*! @{ */ + +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT0_MASK (0x1U) +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT0_SHIFT (0U) +/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT0_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT1_MASK (0x2U) +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT1_SHIFT (1U) +/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT1_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT2_MASK (0x4U) +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT2_SHIFT (2U) +/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT2_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT3_MASK (0x8U) +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT3_SHIFT (3U) +/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT3_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT4_MASK (0x10U) +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT4_SHIFT (4U) +/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT4_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT5_MASK (0x20U) +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT5_SHIFT (5U) +/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT5_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT6_MASK (0x40U) +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT6_SHIFT (6U) +/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT6_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT7_MASK (0x80U) +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT7_SHIFT (7U) +/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT7_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT8_MASK (0x100U) +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT8_SHIFT (8U) +/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT8_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT9_MASK (0x200U) +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT9_SHIFT (9U) +/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT9_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT10_MASK (0x400U) +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT10_SHIFT (10U) +/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT10_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT11_MASK (0x800U) +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT11_SHIFT (11U) +/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT11_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT12_MASK (0x1000U) +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT12_SHIFT (12U) +/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT12_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT13_MASK (0x2000U) +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT13_SHIFT (13U) +/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT13_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT14_MASK (0x4000U) +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT14_SHIFT (14U) +/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT14_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT15_MASK (0x8000U) +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT15_SHIFT (15U) +/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT15_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT16_MASK (0x10000U) +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT16_SHIFT (16U) +/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT16_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT17_MASK (0x20000U) +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT17_SHIFT (17U) +/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT17_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT18_MASK (0x40000U) +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT18_SHIFT (18U) +/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT18_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT19_MASK (0x80000U) +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT19_SHIFT (19U) +/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT19_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT20_MASK (0x100000U) +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT20_SHIFT (20U) +/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT20_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT21_MASK (0x200000U) +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT21_SHIFT (21U) +/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT21_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT22_MASK (0x400000U) +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT22_SHIFT (22U) +/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT22_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT23_MASK (0x800000U) +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT23_SHIFT (23U) +/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT23_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT24_MASK (0x1000000U) +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT24_SHIFT (24U) +/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT24_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT25_MASK (0x2000000U) +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT25_SHIFT (25U) +/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT25_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT26_MASK (0x4000000U) +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT26_SHIFT (26U) +/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT26_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT27_MASK (0x8000000U) +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT27_SHIFT (27U) +/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT27_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT28_MASK (0x10000000U) +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT28_SHIFT (28U) +/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT28_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT29_MASK (0x20000000U) +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT29_SHIFT (29U) +/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT29_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT30_MASK (0x40000000U) +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT30_SHIFT (30U) +/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT30_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT31_MASK (0x80000000U) +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT31_SHIFT (31U) +/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_BIT31_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W */ +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_COUNT (4U) + +/* The count of TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W */ +#define TRDC_MBC4_MBC_DOM11_MEM1_BLK_NSE_W_COUNT2 (1U) + +/*! @name MBC_DOM11_MEM2_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM2_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM2_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM2_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM2_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM2_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM2_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM2_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM2_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM2_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM2_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM2_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM2_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM2_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM2_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM2_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM2_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM2_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM2_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM2_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM2_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM2_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM2_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM2_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM2_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM2_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM2_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM2_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM2_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM2_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM2_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM2_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM2_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MBC_DOM11_MEM2_BLK_CFG_W */ +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_CFG_W_COUNT (4U) + +/* The count of TRDC_MBC4_MBC_DOM11_MEM2_BLK_CFG_W */ +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_CFG_W_COUNT2 (5U) + +/*! @name MBC_DOM11_MEM2_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ +/*! @{ */ + +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT0_MASK (0x1U) +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT0_SHIFT (0U) +/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT0_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT1_MASK (0x2U) +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT1_SHIFT (1U) +/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT1_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT2_MASK (0x4U) +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT2_SHIFT (2U) +/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT2_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT3_MASK (0x8U) +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT3_SHIFT (3U) +/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT3_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT4_MASK (0x10U) +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT4_SHIFT (4U) +/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT4_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT5_MASK (0x20U) +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT5_SHIFT (5U) +/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT5_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT6_MASK (0x40U) +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT6_SHIFT (6U) +/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT6_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT7_MASK (0x80U) +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT7_SHIFT (7U) +/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT7_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT8_MASK (0x100U) +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT8_SHIFT (8U) +/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT8_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT9_MASK (0x200U) +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT9_SHIFT (9U) +/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT9_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT10_MASK (0x400U) +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT10_SHIFT (10U) +/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT10_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT11_MASK (0x800U) +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT11_SHIFT (11U) +/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT11_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT12_MASK (0x1000U) +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT12_SHIFT (12U) +/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT12_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT13_MASK (0x2000U) +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT13_SHIFT (13U) +/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT13_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT14_MASK (0x4000U) +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT14_SHIFT (14U) +/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT14_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT15_MASK (0x8000U) +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT15_SHIFT (15U) +/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT15_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT16_MASK (0x10000U) +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT16_SHIFT (16U) +/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT16_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT17_MASK (0x20000U) +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT17_SHIFT (17U) +/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT17_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT18_MASK (0x40000U) +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT18_SHIFT (18U) +/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT18_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT19_MASK (0x80000U) +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT19_SHIFT (19U) +/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT19_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT20_MASK (0x100000U) +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT20_SHIFT (20U) +/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT20_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT21_MASK (0x200000U) +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT21_SHIFT (21U) +/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT21_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT22_MASK (0x400000U) +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT22_SHIFT (22U) +/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT22_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT23_MASK (0x800000U) +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT23_SHIFT (23U) +/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT23_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT24_MASK (0x1000000U) +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT24_SHIFT (24U) +/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT24_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT25_MASK (0x2000000U) +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT25_SHIFT (25U) +/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT25_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT26_MASK (0x4000000U) +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT26_SHIFT (26U) +/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT26_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT27_MASK (0x8000000U) +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT27_SHIFT (27U) +/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT27_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT28_MASK (0x10000000U) +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT28_SHIFT (28U) +/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT28_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT29_MASK (0x20000000U) +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT29_SHIFT (29U) +/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT29_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT30_MASK (0x40000000U) +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT30_SHIFT (30U) +/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT30_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT31_MASK (0x80000000U) +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT31_SHIFT (31U) +/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_BIT31_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W */ +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_COUNT (4U) + +/* The count of TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W */ +#define TRDC_MBC4_MBC_DOM11_MEM2_BLK_NSE_W_COUNT2 (2U) + +/*! @name MBC_DOM11_MEM3_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM3_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM3_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM3_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM3_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM3_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM3_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM3_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM3_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM3_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM3_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM3_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM3_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM3_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM3_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM3_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM3_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM3_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM3_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM3_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM3_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM3_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM3_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM3_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM3_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM3_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM3_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM3_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM3_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM3_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM3_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM3_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM3_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MBC_DOM11_MEM3_BLK_CFG_W */ +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_CFG_W_COUNT (4U) + +/* The count of TRDC_MBC4_MBC_DOM11_MEM3_BLK_CFG_W */ +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_CFG_W_COUNT2 (6U) + +/*! @name MBC_DOM11_MEM3_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ +/*! @{ */ + +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT0_MASK (0x1U) +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT0_SHIFT (0U) +/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT0_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT1_MASK (0x2U) +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT1_SHIFT (1U) +/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT1_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT2_MASK (0x4U) +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT2_SHIFT (2U) +/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT2_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT3_MASK (0x8U) +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT3_SHIFT (3U) +/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT3_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT4_MASK (0x10U) +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT4_SHIFT (4U) +/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT4_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT5_MASK (0x20U) +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT5_SHIFT (5U) +/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT5_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT6_MASK (0x40U) +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT6_SHIFT (6U) +/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT6_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT7_MASK (0x80U) +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT7_SHIFT (7U) +/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT7_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT8_MASK (0x100U) +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT8_SHIFT (8U) +/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT8_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT9_MASK (0x200U) +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT9_SHIFT (9U) +/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT9_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT10_MASK (0x400U) +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT10_SHIFT (10U) +/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT10_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT11_MASK (0x800U) +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT11_SHIFT (11U) +/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT11_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT12_MASK (0x1000U) +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT12_SHIFT (12U) +/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT12_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT13_MASK (0x2000U) +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT13_SHIFT (13U) +/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT13_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT14_MASK (0x4000U) +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT14_SHIFT (14U) +/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT14_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT15_MASK (0x8000U) +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT15_SHIFT (15U) +/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT15_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT16_MASK (0x10000U) +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT16_SHIFT (16U) +/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT16_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT17_MASK (0x20000U) +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT17_SHIFT (17U) +/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT17_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT18_MASK (0x40000U) +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT18_SHIFT (18U) +/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT18_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT19_MASK (0x80000U) +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT19_SHIFT (19U) +/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT19_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT20_MASK (0x100000U) +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT20_SHIFT (20U) +/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT20_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT21_MASK (0x200000U) +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT21_SHIFT (21U) +/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT21_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT22_MASK (0x400000U) +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT22_SHIFT (22U) +/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT22_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT23_MASK (0x800000U) +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT23_SHIFT (23U) +/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT23_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT24_MASK (0x1000000U) +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT24_SHIFT (24U) +/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT24_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT25_MASK (0x2000000U) +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT25_SHIFT (25U) +/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT25_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT26_MASK (0x4000000U) +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT26_SHIFT (26U) +/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT26_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT27_MASK (0x8000000U) +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT27_SHIFT (27U) +/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT27_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT28_MASK (0x10000000U) +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT28_SHIFT (28U) +/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT28_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT29_MASK (0x20000000U) +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT29_SHIFT (29U) +/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT29_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT30_MASK (0x40000000U) +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT30_SHIFT (30U) +/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT30_MASK) + +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT31_MASK (0x80000000U) +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT31_SHIFT (31U) +/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_BIT31_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W */ +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_COUNT (4U) + +/* The count of TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W */ +#define TRDC_MBC4_MBC_DOM11_MEM3_BLK_NSE_W_COUNT2 (2U) + +/*! @name MBC_DOM12_MEM0_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM0_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM0_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM0_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM0_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM0_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM0_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM0_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM0_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM0_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM0_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM0_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM0_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM0_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM0_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM0_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM0_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM0_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM0_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM0_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM0_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM0_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM0_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM0_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM0_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM0_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM0_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM0_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM0_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM0_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM0_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM0_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM0_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MBC_DOM12_MEM0_BLK_CFG_W */ +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_CFG_W_COUNT (4U) + +/* The count of TRDC_MBC4_MBC_DOM12_MEM0_BLK_CFG_W */ +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_CFG_W_COUNT2 (7U) + +/*! @name MBC_DOM12_MEM0_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ +/*! @{ */ + +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT0_MASK (0x1U) +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT0_SHIFT (0U) +/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT0_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT1_MASK (0x2U) +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT1_SHIFT (1U) +/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT1_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT2_MASK (0x4U) +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT2_SHIFT (2U) +/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT2_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT3_MASK (0x8U) +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT3_SHIFT (3U) +/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT3_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT4_MASK (0x10U) +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT4_SHIFT (4U) +/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT4_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT5_MASK (0x20U) +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT5_SHIFT (5U) +/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT5_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT6_MASK (0x40U) +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT6_SHIFT (6U) +/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT6_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT7_MASK (0x80U) +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT7_SHIFT (7U) +/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT7_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT8_MASK (0x100U) +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT8_SHIFT (8U) +/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT8_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT9_MASK (0x200U) +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT9_SHIFT (9U) +/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT9_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT10_MASK (0x400U) +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT10_SHIFT (10U) +/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT10_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT11_MASK (0x800U) +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT11_SHIFT (11U) +/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT11_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT12_MASK (0x1000U) +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT12_SHIFT (12U) +/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT12_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT13_MASK (0x2000U) +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT13_SHIFT (13U) +/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT13_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT14_MASK (0x4000U) +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT14_SHIFT (14U) +/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT14_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT15_MASK (0x8000U) +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT15_SHIFT (15U) +/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT15_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT16_MASK (0x10000U) +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT16_SHIFT (16U) +/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT16_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT17_MASK (0x20000U) +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT17_SHIFT (17U) +/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT17_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT18_MASK (0x40000U) +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT18_SHIFT (18U) +/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT18_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT19_MASK (0x80000U) +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT19_SHIFT (19U) +/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT19_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT20_MASK (0x100000U) +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT20_SHIFT (20U) +/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT20_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT21_MASK (0x200000U) +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT21_SHIFT (21U) +/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT21_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT22_MASK (0x400000U) +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT22_SHIFT (22U) +/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT22_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT23_MASK (0x800000U) +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT23_SHIFT (23U) +/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT23_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT24_MASK (0x1000000U) +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT24_SHIFT (24U) +/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT24_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT25_MASK (0x2000000U) +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT25_SHIFT (25U) +/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT25_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT26_MASK (0x4000000U) +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT26_SHIFT (26U) +/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT26_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT27_MASK (0x8000000U) +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT27_SHIFT (27U) +/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT27_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT28_MASK (0x10000000U) +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT28_SHIFT (28U) +/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT28_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT29_MASK (0x20000000U) +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT29_SHIFT (29U) +/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT29_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT30_MASK (0x40000000U) +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT30_SHIFT (30U) +/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT30_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT31_MASK (0x80000000U) +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT31_SHIFT (31U) +/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_BIT31_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W */ +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_COUNT (4U) + +/* The count of TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W */ +#define TRDC_MBC4_MBC_DOM12_MEM0_BLK_NSE_W_COUNT2 (2U) + +/*! @name MBC_DOM12_MEM1_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM1_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM1_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM1_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM1_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM1_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM1_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM1_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM1_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM1_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM1_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM1_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM1_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM1_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM1_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM1_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM1_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM1_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM1_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM1_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM1_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM1_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM1_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM1_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM1_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM1_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM1_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM1_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM1_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM1_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM1_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM1_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM1_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MBC_DOM12_MEM1_BLK_CFG_W */ +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_CFG_W_COUNT (4U) + +/* The count of TRDC_MBC4_MBC_DOM12_MEM1_BLK_CFG_W */ +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_CFG_W_COUNT2 (3U) + +/*! @name MBC_DOM12_MEM1_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ +/*! @{ */ + +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT0_MASK (0x1U) +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT0_SHIFT (0U) +/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT0_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT1_MASK (0x2U) +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT1_SHIFT (1U) +/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT1_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT2_MASK (0x4U) +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT2_SHIFT (2U) +/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT2_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT3_MASK (0x8U) +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT3_SHIFT (3U) +/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT3_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT4_MASK (0x10U) +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT4_SHIFT (4U) +/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT4_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT5_MASK (0x20U) +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT5_SHIFT (5U) +/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT5_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT6_MASK (0x40U) +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT6_SHIFT (6U) +/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT6_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT7_MASK (0x80U) +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT7_SHIFT (7U) +/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT7_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT8_MASK (0x100U) +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT8_SHIFT (8U) +/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT8_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT9_MASK (0x200U) +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT9_SHIFT (9U) +/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT9_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT10_MASK (0x400U) +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT10_SHIFT (10U) +/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT10_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT11_MASK (0x800U) +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT11_SHIFT (11U) +/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT11_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT12_MASK (0x1000U) +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT12_SHIFT (12U) +/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT12_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT13_MASK (0x2000U) +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT13_SHIFT (13U) +/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT13_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT14_MASK (0x4000U) +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT14_SHIFT (14U) +/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT14_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT15_MASK (0x8000U) +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT15_SHIFT (15U) +/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT15_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT16_MASK (0x10000U) +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT16_SHIFT (16U) +/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT16_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT17_MASK (0x20000U) +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT17_SHIFT (17U) +/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT17_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT18_MASK (0x40000U) +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT18_SHIFT (18U) +/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT18_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT19_MASK (0x80000U) +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT19_SHIFT (19U) +/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT19_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT20_MASK (0x100000U) +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT20_SHIFT (20U) +/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT20_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT21_MASK (0x200000U) +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT21_SHIFT (21U) +/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT21_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT22_MASK (0x400000U) +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT22_SHIFT (22U) +/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT22_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT23_MASK (0x800000U) +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT23_SHIFT (23U) +/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT23_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT24_MASK (0x1000000U) +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT24_SHIFT (24U) +/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT24_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT25_MASK (0x2000000U) +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT25_SHIFT (25U) +/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT25_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT26_MASK (0x4000000U) +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT26_SHIFT (26U) +/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT26_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT27_MASK (0x8000000U) +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT27_SHIFT (27U) +/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT27_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT28_MASK (0x10000000U) +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT28_SHIFT (28U) +/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT28_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT29_MASK (0x20000000U) +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT29_SHIFT (29U) +/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT29_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT30_MASK (0x40000000U) +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT30_SHIFT (30U) +/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT30_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT31_MASK (0x80000000U) +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT31_SHIFT (31U) +/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_BIT31_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W */ +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_COUNT (4U) + +/* The count of TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W */ +#define TRDC_MBC4_MBC_DOM12_MEM1_BLK_NSE_W_COUNT2 (1U) + +/*! @name MBC_DOM12_MEM2_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM2_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM2_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM2_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM2_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM2_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM2_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM2_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM2_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM2_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM2_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM2_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM2_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM2_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM2_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM2_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM2_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM2_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM2_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM2_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM2_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM2_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM2_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM2_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM2_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM2_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM2_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM2_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM2_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM2_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM2_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM2_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM2_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MBC_DOM12_MEM2_BLK_CFG_W */ +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_CFG_W_COUNT (4U) + +/* The count of TRDC_MBC4_MBC_DOM12_MEM2_BLK_CFG_W */ +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_CFG_W_COUNT2 (5U) + +/*! @name MBC_DOM12_MEM2_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ +/*! @{ */ + +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT0_MASK (0x1U) +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT0_SHIFT (0U) +/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT0_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT1_MASK (0x2U) +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT1_SHIFT (1U) +/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT1_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT2_MASK (0x4U) +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT2_SHIFT (2U) +/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT2_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT3_MASK (0x8U) +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT3_SHIFT (3U) +/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT3_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT4_MASK (0x10U) +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT4_SHIFT (4U) +/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT4_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT5_MASK (0x20U) +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT5_SHIFT (5U) +/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT5_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT6_MASK (0x40U) +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT6_SHIFT (6U) +/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT6_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT7_MASK (0x80U) +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT7_SHIFT (7U) +/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT7_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT8_MASK (0x100U) +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT8_SHIFT (8U) +/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT8_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT9_MASK (0x200U) +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT9_SHIFT (9U) +/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT9_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT10_MASK (0x400U) +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT10_SHIFT (10U) +/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT10_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT11_MASK (0x800U) +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT11_SHIFT (11U) +/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT11_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT12_MASK (0x1000U) +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT12_SHIFT (12U) +/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT12_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT13_MASK (0x2000U) +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT13_SHIFT (13U) +/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT13_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT14_MASK (0x4000U) +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT14_SHIFT (14U) +/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT14_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT15_MASK (0x8000U) +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT15_SHIFT (15U) +/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT15_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT16_MASK (0x10000U) +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT16_SHIFT (16U) +/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT16_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT17_MASK (0x20000U) +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT17_SHIFT (17U) +/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT17_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT18_MASK (0x40000U) +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT18_SHIFT (18U) +/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT18_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT19_MASK (0x80000U) +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT19_SHIFT (19U) +/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT19_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT20_MASK (0x100000U) +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT20_SHIFT (20U) +/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT20_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT21_MASK (0x200000U) +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT21_SHIFT (21U) +/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT21_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT22_MASK (0x400000U) +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT22_SHIFT (22U) +/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT22_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT23_MASK (0x800000U) +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT23_SHIFT (23U) +/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT23_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT24_MASK (0x1000000U) +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT24_SHIFT (24U) +/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT24_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT25_MASK (0x2000000U) +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT25_SHIFT (25U) +/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT25_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT26_MASK (0x4000000U) +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT26_SHIFT (26U) +/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT26_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT27_MASK (0x8000000U) +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT27_SHIFT (27U) +/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT27_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT28_MASK (0x10000000U) +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT28_SHIFT (28U) +/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT28_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT29_MASK (0x20000000U) +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT29_SHIFT (29U) +/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT29_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT30_MASK (0x40000000U) +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT30_SHIFT (30U) +/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT30_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT31_MASK (0x80000000U) +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT31_SHIFT (31U) +/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_BIT31_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W */ +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_COUNT (4U) + +/* The count of TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W */ +#define TRDC_MBC4_MBC_DOM12_MEM2_BLK_NSE_W_COUNT2 (2U) + +/*! @name MBC_DOM12_MEM3_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM3_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM3_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM3_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM3_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM3_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM3_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM3_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM3_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM3_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM3_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM3_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM3_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM3_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM3_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM3_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM3_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM3_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM3_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM3_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM3_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM3_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM3_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM3_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM3_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM3_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM3_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM3_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM3_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM3_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM3_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM3_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM3_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MBC_DOM12_MEM3_BLK_CFG_W */ +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_CFG_W_COUNT (4U) + +/* The count of TRDC_MBC4_MBC_DOM12_MEM3_BLK_CFG_W */ +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_CFG_W_COUNT2 (6U) + +/*! @name MBC_DOM12_MEM3_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ +/*! @{ */ + +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT0_MASK (0x1U) +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT0_SHIFT (0U) +/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT0_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT1_MASK (0x2U) +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT1_SHIFT (1U) +/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT1_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT2_MASK (0x4U) +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT2_SHIFT (2U) +/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT2_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT3_MASK (0x8U) +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT3_SHIFT (3U) +/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT3_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT4_MASK (0x10U) +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT4_SHIFT (4U) +/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT4_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT5_MASK (0x20U) +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT5_SHIFT (5U) +/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT5_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT6_MASK (0x40U) +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT6_SHIFT (6U) +/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT6_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT7_MASK (0x80U) +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT7_SHIFT (7U) +/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT7_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT8_MASK (0x100U) +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT8_SHIFT (8U) +/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT8_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT9_MASK (0x200U) +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT9_SHIFT (9U) +/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT9_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT10_MASK (0x400U) +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT10_SHIFT (10U) +/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT10_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT11_MASK (0x800U) +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT11_SHIFT (11U) +/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT11_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT12_MASK (0x1000U) +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT12_SHIFT (12U) +/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT12_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT13_MASK (0x2000U) +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT13_SHIFT (13U) +/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT13_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT14_MASK (0x4000U) +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT14_SHIFT (14U) +/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT14_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT15_MASK (0x8000U) +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT15_SHIFT (15U) +/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT15_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT16_MASK (0x10000U) +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT16_SHIFT (16U) +/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT16_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT17_MASK (0x20000U) +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT17_SHIFT (17U) +/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT17_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT18_MASK (0x40000U) +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT18_SHIFT (18U) +/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT18_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT19_MASK (0x80000U) +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT19_SHIFT (19U) +/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT19_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT20_MASK (0x100000U) +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT20_SHIFT (20U) +/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT20_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT21_MASK (0x200000U) +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT21_SHIFT (21U) +/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT21_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT22_MASK (0x400000U) +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT22_SHIFT (22U) +/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT22_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT23_MASK (0x800000U) +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT23_SHIFT (23U) +/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT23_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT24_MASK (0x1000000U) +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT24_SHIFT (24U) +/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT24_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT25_MASK (0x2000000U) +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT25_SHIFT (25U) +/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT25_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT26_MASK (0x4000000U) +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT26_SHIFT (26U) +/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT26_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT27_MASK (0x8000000U) +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT27_SHIFT (27U) +/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT27_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT28_MASK (0x10000000U) +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT28_SHIFT (28U) +/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT28_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT29_MASK (0x20000000U) +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT29_SHIFT (29U) +/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT29_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT30_MASK (0x40000000U) +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT30_SHIFT (30U) +/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT30_MASK) + +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT31_MASK (0x80000000U) +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT31_SHIFT (31U) +/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_BIT31_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W */ +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_COUNT (4U) + +/* The count of TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W */ +#define TRDC_MBC4_MBC_DOM12_MEM3_BLK_NSE_W_COUNT2 (2U) + +/*! @name MBC_DOM13_MEM0_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM0_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM0_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM0_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM0_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM0_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM0_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM0_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM0_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM0_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM0_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM0_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM0_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM0_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM0_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM0_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM0_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM0_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM0_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM0_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM0_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM0_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM0_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM0_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM0_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM0_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM0_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM0_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM0_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM0_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM0_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM0_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM0_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MBC_DOM13_MEM0_BLK_CFG_W */ +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_CFG_W_COUNT (4U) + +/* The count of TRDC_MBC4_MBC_DOM13_MEM0_BLK_CFG_W */ +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_CFG_W_COUNT2 (7U) + +/*! @name MBC_DOM13_MEM0_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ +/*! @{ */ + +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT0_MASK (0x1U) +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT0_SHIFT (0U) +/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT0_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT1_MASK (0x2U) +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT1_SHIFT (1U) +/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT1_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT2_MASK (0x4U) +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT2_SHIFT (2U) +/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT2_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT3_MASK (0x8U) +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT3_SHIFT (3U) +/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT3_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT4_MASK (0x10U) +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT4_SHIFT (4U) +/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT4_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT5_MASK (0x20U) +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT5_SHIFT (5U) +/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT5_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT6_MASK (0x40U) +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT6_SHIFT (6U) +/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT6_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT7_MASK (0x80U) +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT7_SHIFT (7U) +/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT7_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT8_MASK (0x100U) +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT8_SHIFT (8U) +/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT8_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT9_MASK (0x200U) +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT9_SHIFT (9U) +/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT9_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT10_MASK (0x400U) +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT10_SHIFT (10U) +/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT10_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT11_MASK (0x800U) +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT11_SHIFT (11U) +/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT11_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT12_MASK (0x1000U) +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT12_SHIFT (12U) +/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT12_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT13_MASK (0x2000U) +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT13_SHIFT (13U) +/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT13_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT14_MASK (0x4000U) +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT14_SHIFT (14U) +/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT14_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT15_MASK (0x8000U) +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT15_SHIFT (15U) +/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT15_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT16_MASK (0x10000U) +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT16_SHIFT (16U) +/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT16_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT17_MASK (0x20000U) +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT17_SHIFT (17U) +/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT17_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT18_MASK (0x40000U) +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT18_SHIFT (18U) +/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT18_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT19_MASK (0x80000U) +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT19_SHIFT (19U) +/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT19_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT20_MASK (0x100000U) +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT20_SHIFT (20U) +/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT20_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT21_MASK (0x200000U) +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT21_SHIFT (21U) +/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT21_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT22_MASK (0x400000U) +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT22_SHIFT (22U) +/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT22_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT23_MASK (0x800000U) +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT23_SHIFT (23U) +/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT23_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT24_MASK (0x1000000U) +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT24_SHIFT (24U) +/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT24_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT25_MASK (0x2000000U) +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT25_SHIFT (25U) +/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT25_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT26_MASK (0x4000000U) +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT26_SHIFT (26U) +/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT26_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT27_MASK (0x8000000U) +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT27_SHIFT (27U) +/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT27_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT28_MASK (0x10000000U) +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT28_SHIFT (28U) +/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT28_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT29_MASK (0x20000000U) +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT29_SHIFT (29U) +/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT29_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT30_MASK (0x40000000U) +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT30_SHIFT (30U) +/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT30_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT31_MASK (0x80000000U) +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT31_SHIFT (31U) +/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_BIT31_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W */ +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_COUNT (4U) + +/* The count of TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W */ +#define TRDC_MBC4_MBC_DOM13_MEM0_BLK_NSE_W_COUNT2 (2U) + +/*! @name MBC_DOM13_MEM1_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM1_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM1_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM1_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM1_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM1_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM1_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM1_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM1_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM1_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM1_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM1_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM1_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM1_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM1_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM1_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM1_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM1_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM1_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM1_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM1_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM1_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM1_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM1_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM1_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM1_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM1_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM1_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM1_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM1_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM1_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM1_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM1_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MBC_DOM13_MEM1_BLK_CFG_W */ +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_CFG_W_COUNT (4U) + +/* The count of TRDC_MBC4_MBC_DOM13_MEM1_BLK_CFG_W */ +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_CFG_W_COUNT2 (3U) + +/*! @name MBC_DOM13_MEM1_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ +/*! @{ */ + +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT0_MASK (0x1U) +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT0_SHIFT (0U) +/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT0_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT1_MASK (0x2U) +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT1_SHIFT (1U) +/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT1_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT2_MASK (0x4U) +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT2_SHIFT (2U) +/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT2_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT3_MASK (0x8U) +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT3_SHIFT (3U) +/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT3_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT4_MASK (0x10U) +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT4_SHIFT (4U) +/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT4_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT5_MASK (0x20U) +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT5_SHIFT (5U) +/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT5_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT6_MASK (0x40U) +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT6_SHIFT (6U) +/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT6_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT7_MASK (0x80U) +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT7_SHIFT (7U) +/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT7_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT8_MASK (0x100U) +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT8_SHIFT (8U) +/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT8_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT9_MASK (0x200U) +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT9_SHIFT (9U) +/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT9_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT10_MASK (0x400U) +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT10_SHIFT (10U) +/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT10_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT11_MASK (0x800U) +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT11_SHIFT (11U) +/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT11_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT12_MASK (0x1000U) +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT12_SHIFT (12U) +/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT12_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT13_MASK (0x2000U) +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT13_SHIFT (13U) +/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT13_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT14_MASK (0x4000U) +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT14_SHIFT (14U) +/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT14_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT15_MASK (0x8000U) +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT15_SHIFT (15U) +/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT15_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT16_MASK (0x10000U) +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT16_SHIFT (16U) +/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT16_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT17_MASK (0x20000U) +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT17_SHIFT (17U) +/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT17_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT18_MASK (0x40000U) +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT18_SHIFT (18U) +/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT18_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT19_MASK (0x80000U) +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT19_SHIFT (19U) +/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT19_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT20_MASK (0x100000U) +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT20_SHIFT (20U) +/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT20_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT21_MASK (0x200000U) +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT21_SHIFT (21U) +/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT21_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT22_MASK (0x400000U) +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT22_SHIFT (22U) +/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT22_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT23_MASK (0x800000U) +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT23_SHIFT (23U) +/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT23_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT24_MASK (0x1000000U) +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT24_SHIFT (24U) +/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT24_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT25_MASK (0x2000000U) +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT25_SHIFT (25U) +/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT25_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT26_MASK (0x4000000U) +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT26_SHIFT (26U) +/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT26_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT27_MASK (0x8000000U) +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT27_SHIFT (27U) +/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT27_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT28_MASK (0x10000000U) +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT28_SHIFT (28U) +/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT28_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT29_MASK (0x20000000U) +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT29_SHIFT (29U) +/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT29_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT30_MASK (0x40000000U) +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT30_SHIFT (30U) +/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT30_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT31_MASK (0x80000000U) +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT31_SHIFT (31U) +/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_BIT31_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W */ +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_COUNT (4U) + +/* The count of TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W */ +#define TRDC_MBC4_MBC_DOM13_MEM1_BLK_NSE_W_COUNT2 (1U) + +/*! @name MBC_DOM13_MEM2_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM2_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM2_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM2_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM2_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM2_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM2_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM2_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM2_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM2_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM2_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM2_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM2_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM2_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM2_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM2_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM2_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM2_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM2_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM2_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM2_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM2_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM2_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM2_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM2_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM2_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM2_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM2_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM2_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM2_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM2_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM2_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM2_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MBC_DOM13_MEM2_BLK_CFG_W */ +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_CFG_W_COUNT (4U) + +/* The count of TRDC_MBC4_MBC_DOM13_MEM2_BLK_CFG_W */ +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_CFG_W_COUNT2 (5U) + +/*! @name MBC_DOM13_MEM2_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ +/*! @{ */ + +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT0_MASK (0x1U) +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT0_SHIFT (0U) +/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT0_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT1_MASK (0x2U) +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT1_SHIFT (1U) +/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT1_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT2_MASK (0x4U) +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT2_SHIFT (2U) +/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT2_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT3_MASK (0x8U) +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT3_SHIFT (3U) +/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT3_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT4_MASK (0x10U) +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT4_SHIFT (4U) +/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT4_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT5_MASK (0x20U) +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT5_SHIFT (5U) +/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT5_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT6_MASK (0x40U) +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT6_SHIFT (6U) +/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT6_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT7_MASK (0x80U) +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT7_SHIFT (7U) +/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT7_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT8_MASK (0x100U) +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT8_SHIFT (8U) +/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT8_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT9_MASK (0x200U) +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT9_SHIFT (9U) +/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT9_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT10_MASK (0x400U) +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT10_SHIFT (10U) +/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT10_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT11_MASK (0x800U) +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT11_SHIFT (11U) +/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT11_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT12_MASK (0x1000U) +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT12_SHIFT (12U) +/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT12_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT13_MASK (0x2000U) +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT13_SHIFT (13U) +/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT13_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT14_MASK (0x4000U) +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT14_SHIFT (14U) +/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT14_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT15_MASK (0x8000U) +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT15_SHIFT (15U) +/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT15_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT16_MASK (0x10000U) +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT16_SHIFT (16U) +/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT16_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT17_MASK (0x20000U) +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT17_SHIFT (17U) +/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT17_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT18_MASK (0x40000U) +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT18_SHIFT (18U) +/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT18_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT19_MASK (0x80000U) +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT19_SHIFT (19U) +/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT19_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT20_MASK (0x100000U) +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT20_SHIFT (20U) +/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT20_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT21_MASK (0x200000U) +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT21_SHIFT (21U) +/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT21_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT22_MASK (0x400000U) +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT22_SHIFT (22U) +/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT22_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT23_MASK (0x800000U) +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT23_SHIFT (23U) +/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT23_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT24_MASK (0x1000000U) +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT24_SHIFT (24U) +/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT24_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT25_MASK (0x2000000U) +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT25_SHIFT (25U) +/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT25_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT26_MASK (0x4000000U) +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT26_SHIFT (26U) +/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT26_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT27_MASK (0x8000000U) +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT27_SHIFT (27U) +/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT27_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT28_MASK (0x10000000U) +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT28_SHIFT (28U) +/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT28_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT29_MASK (0x20000000U) +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT29_SHIFT (29U) +/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT29_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT30_MASK (0x40000000U) +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT30_SHIFT (30U) +/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT30_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT31_MASK (0x80000000U) +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT31_SHIFT (31U) +/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_BIT31_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W */ +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_COUNT (4U) + +/* The count of TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W */ +#define TRDC_MBC4_MBC_DOM13_MEM2_BLK_NSE_W_COUNT2 (2U) + +/*! @name MBC_DOM13_MEM3_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM3_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM3_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM3_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM3_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM3_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM3_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM3_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM3_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM3_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM3_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM3_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM3_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM3_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM3_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM3_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM3_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM3_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM3_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM3_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM3_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM3_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM3_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM3_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM3_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM3_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM3_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM3_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM3_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM3_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM3_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM3_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM3_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MBC_DOM13_MEM3_BLK_CFG_W */ +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_CFG_W_COUNT (4U) + +/* The count of TRDC_MBC4_MBC_DOM13_MEM3_BLK_CFG_W */ +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_CFG_W_COUNT2 (6U) + +/*! @name MBC_DOM13_MEM3_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ +/*! @{ */ + +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT0_MASK (0x1U) +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT0_SHIFT (0U) +/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT0_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT1_MASK (0x2U) +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT1_SHIFT (1U) +/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT1_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT2_MASK (0x4U) +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT2_SHIFT (2U) +/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT2_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT3_MASK (0x8U) +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT3_SHIFT (3U) +/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT3_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT4_MASK (0x10U) +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT4_SHIFT (4U) +/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT4_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT5_MASK (0x20U) +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT5_SHIFT (5U) +/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT5_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT6_MASK (0x40U) +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT6_SHIFT (6U) +/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT6_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT7_MASK (0x80U) +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT7_SHIFT (7U) +/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT7_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT8_MASK (0x100U) +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT8_SHIFT (8U) +/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT8_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT9_MASK (0x200U) +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT9_SHIFT (9U) +/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT9_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT10_MASK (0x400U) +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT10_SHIFT (10U) +/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT10_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT11_MASK (0x800U) +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT11_SHIFT (11U) +/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT11_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT12_MASK (0x1000U) +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT12_SHIFT (12U) +/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT12_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT13_MASK (0x2000U) +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT13_SHIFT (13U) +/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT13_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT14_MASK (0x4000U) +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT14_SHIFT (14U) +/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT14_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT15_MASK (0x8000U) +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT15_SHIFT (15U) +/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT15_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT16_MASK (0x10000U) +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT16_SHIFT (16U) +/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT16_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT17_MASK (0x20000U) +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT17_SHIFT (17U) +/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT17_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT18_MASK (0x40000U) +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT18_SHIFT (18U) +/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT18_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT19_MASK (0x80000U) +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT19_SHIFT (19U) +/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT19_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT20_MASK (0x100000U) +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT20_SHIFT (20U) +/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT20_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT21_MASK (0x200000U) +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT21_SHIFT (21U) +/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT21_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT22_MASK (0x400000U) +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT22_SHIFT (22U) +/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT22_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT23_MASK (0x800000U) +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT23_SHIFT (23U) +/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT23_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT24_MASK (0x1000000U) +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT24_SHIFT (24U) +/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT24_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT25_MASK (0x2000000U) +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT25_SHIFT (25U) +/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT25_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT26_MASK (0x4000000U) +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT26_SHIFT (26U) +/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT26_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT27_MASK (0x8000000U) +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT27_SHIFT (27U) +/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT27_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT28_MASK (0x10000000U) +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT28_SHIFT (28U) +/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT28_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT29_MASK (0x20000000U) +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT29_SHIFT (29U) +/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT29_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT30_MASK (0x40000000U) +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT30_SHIFT (30U) +/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT30_MASK) + +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT31_MASK (0x80000000U) +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT31_SHIFT (31U) +/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_BIT31_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W */ +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_COUNT (4U) + +/* The count of TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W */ +#define TRDC_MBC4_MBC_DOM13_MEM3_BLK_NSE_W_COUNT2 (2U) + +/*! @name MBC_DOM14_MEM0_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM0_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM0_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM0_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM0_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM0_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM0_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM0_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM0_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM0_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM0_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM0_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM0_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM0_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM0_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM0_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM0_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM0_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM0_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM0_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM0_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM0_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM0_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM0_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM0_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM0_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM0_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM0_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM0_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM0_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM0_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM0_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM0_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MBC_DOM14_MEM0_BLK_CFG_W */ +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_CFG_W_COUNT (4U) + +/* The count of TRDC_MBC4_MBC_DOM14_MEM0_BLK_CFG_W */ +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_CFG_W_COUNT2 (7U) + +/*! @name MBC_DOM14_MEM0_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ +/*! @{ */ + +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT0_MASK (0x1U) +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT0_SHIFT (0U) +/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT0_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT1_MASK (0x2U) +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT1_SHIFT (1U) +/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT1_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT2_MASK (0x4U) +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT2_SHIFT (2U) +/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT2_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT3_MASK (0x8U) +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT3_SHIFT (3U) +/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT3_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT4_MASK (0x10U) +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT4_SHIFT (4U) +/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT4_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT5_MASK (0x20U) +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT5_SHIFT (5U) +/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT5_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT6_MASK (0x40U) +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT6_SHIFT (6U) +/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT6_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT7_MASK (0x80U) +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT7_SHIFT (7U) +/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT7_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT8_MASK (0x100U) +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT8_SHIFT (8U) +/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT8_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT9_MASK (0x200U) +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT9_SHIFT (9U) +/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT9_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT10_MASK (0x400U) +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT10_SHIFT (10U) +/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT10_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT11_MASK (0x800U) +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT11_SHIFT (11U) +/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT11_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT12_MASK (0x1000U) +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT12_SHIFT (12U) +/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT12_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT13_MASK (0x2000U) +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT13_SHIFT (13U) +/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT13_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT14_MASK (0x4000U) +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT14_SHIFT (14U) +/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT14_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT15_MASK (0x8000U) +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT15_SHIFT (15U) +/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT15_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT16_MASK (0x10000U) +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT16_SHIFT (16U) +/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT16_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT17_MASK (0x20000U) +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT17_SHIFT (17U) +/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT17_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT18_MASK (0x40000U) +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT18_SHIFT (18U) +/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT18_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT19_MASK (0x80000U) +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT19_SHIFT (19U) +/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT19_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT20_MASK (0x100000U) +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT20_SHIFT (20U) +/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT20_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT21_MASK (0x200000U) +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT21_SHIFT (21U) +/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT21_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT22_MASK (0x400000U) +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT22_SHIFT (22U) +/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT22_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT23_MASK (0x800000U) +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT23_SHIFT (23U) +/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT23_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT24_MASK (0x1000000U) +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT24_SHIFT (24U) +/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT24_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT25_MASK (0x2000000U) +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT25_SHIFT (25U) +/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT25_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT26_MASK (0x4000000U) +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT26_SHIFT (26U) +/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT26_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT27_MASK (0x8000000U) +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT27_SHIFT (27U) +/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT27_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT28_MASK (0x10000000U) +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT28_SHIFT (28U) +/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT28_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT29_MASK (0x20000000U) +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT29_SHIFT (29U) +/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT29_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT30_MASK (0x40000000U) +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT30_SHIFT (30U) +/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT30_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT31_MASK (0x80000000U) +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT31_SHIFT (31U) +/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_BIT31_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W */ +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_COUNT (4U) + +/* The count of TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W */ +#define TRDC_MBC4_MBC_DOM14_MEM0_BLK_NSE_W_COUNT2 (2U) + +/*! @name MBC_DOM14_MEM1_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM1_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM1_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM1_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM1_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM1_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM1_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM1_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM1_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM1_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM1_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM1_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM1_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM1_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM1_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM1_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM1_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM1_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM1_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM1_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM1_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM1_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM1_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM1_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM1_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM1_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM1_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM1_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM1_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM1_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM1_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM1_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM1_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MBC_DOM14_MEM1_BLK_CFG_W */ +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_CFG_W_COUNT (4U) + +/* The count of TRDC_MBC4_MBC_DOM14_MEM1_BLK_CFG_W */ +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_CFG_W_COUNT2 (3U) + +/*! @name MBC_DOM14_MEM1_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ +/*! @{ */ + +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT0_MASK (0x1U) +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT0_SHIFT (0U) +/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT0_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT1_MASK (0x2U) +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT1_SHIFT (1U) +/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT1_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT2_MASK (0x4U) +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT2_SHIFT (2U) +/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT2_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT3_MASK (0x8U) +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT3_SHIFT (3U) +/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT3_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT4_MASK (0x10U) +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT4_SHIFT (4U) +/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT4_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT5_MASK (0x20U) +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT5_SHIFT (5U) +/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT5_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT6_MASK (0x40U) +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT6_SHIFT (6U) +/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT6_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT7_MASK (0x80U) +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT7_SHIFT (7U) +/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT7_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT8_MASK (0x100U) +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT8_SHIFT (8U) +/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT8_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT9_MASK (0x200U) +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT9_SHIFT (9U) +/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT9_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT10_MASK (0x400U) +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT10_SHIFT (10U) +/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT10_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT11_MASK (0x800U) +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT11_SHIFT (11U) +/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT11_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT12_MASK (0x1000U) +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT12_SHIFT (12U) +/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT12_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT13_MASK (0x2000U) +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT13_SHIFT (13U) +/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT13_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT14_MASK (0x4000U) +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT14_SHIFT (14U) +/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT14_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT15_MASK (0x8000U) +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT15_SHIFT (15U) +/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT15_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT16_MASK (0x10000U) +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT16_SHIFT (16U) +/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT16_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT17_MASK (0x20000U) +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT17_SHIFT (17U) +/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT17_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT18_MASK (0x40000U) +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT18_SHIFT (18U) +/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT18_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT19_MASK (0x80000U) +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT19_SHIFT (19U) +/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT19_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT20_MASK (0x100000U) +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT20_SHIFT (20U) +/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT20_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT21_MASK (0x200000U) +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT21_SHIFT (21U) +/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT21_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT22_MASK (0x400000U) +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT22_SHIFT (22U) +/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT22_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT23_MASK (0x800000U) +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT23_SHIFT (23U) +/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT23_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT24_MASK (0x1000000U) +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT24_SHIFT (24U) +/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT24_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT25_MASK (0x2000000U) +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT25_SHIFT (25U) +/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT25_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT26_MASK (0x4000000U) +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT26_SHIFT (26U) +/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT26_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT27_MASK (0x8000000U) +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT27_SHIFT (27U) +/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT27_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT28_MASK (0x10000000U) +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT28_SHIFT (28U) +/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT28_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT29_MASK (0x20000000U) +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT29_SHIFT (29U) +/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT29_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT30_MASK (0x40000000U) +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT30_SHIFT (30U) +/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT30_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT31_MASK (0x80000000U) +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT31_SHIFT (31U) +/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_BIT31_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W */ +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_COUNT (4U) + +/* The count of TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W */ +#define TRDC_MBC4_MBC_DOM14_MEM1_BLK_NSE_W_COUNT2 (1U) + +/*! @name MBC_DOM14_MEM2_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM2_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM2_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM2_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM2_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM2_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM2_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM2_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM2_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM2_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM2_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM2_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM2_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM2_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM2_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM2_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM2_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM2_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM2_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM2_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM2_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM2_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM2_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM2_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM2_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM2_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM2_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM2_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM2_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM2_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM2_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM2_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM2_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MBC_DOM14_MEM2_BLK_CFG_W */ +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_CFG_W_COUNT (4U) + +/* The count of TRDC_MBC4_MBC_DOM14_MEM2_BLK_CFG_W */ +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_CFG_W_COUNT2 (5U) + +/*! @name MBC_DOM14_MEM2_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ +/*! @{ */ + +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT0_MASK (0x1U) +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT0_SHIFT (0U) +/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT0_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT1_MASK (0x2U) +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT1_SHIFT (1U) +/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT1_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT2_MASK (0x4U) +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT2_SHIFT (2U) +/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT2_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT3_MASK (0x8U) +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT3_SHIFT (3U) +/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT3_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT4_MASK (0x10U) +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT4_SHIFT (4U) +/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT4_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT5_MASK (0x20U) +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT5_SHIFT (5U) +/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT5_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT6_MASK (0x40U) +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT6_SHIFT (6U) +/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT6_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT7_MASK (0x80U) +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT7_SHIFT (7U) +/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT7_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT8_MASK (0x100U) +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT8_SHIFT (8U) +/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT8_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT9_MASK (0x200U) +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT9_SHIFT (9U) +/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT9_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT10_MASK (0x400U) +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT10_SHIFT (10U) +/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT10_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT11_MASK (0x800U) +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT11_SHIFT (11U) +/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT11_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT12_MASK (0x1000U) +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT12_SHIFT (12U) +/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT12_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT13_MASK (0x2000U) +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT13_SHIFT (13U) +/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT13_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT14_MASK (0x4000U) +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT14_SHIFT (14U) +/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT14_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT15_MASK (0x8000U) +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT15_SHIFT (15U) +/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT15_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT16_MASK (0x10000U) +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT16_SHIFT (16U) +/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT16_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT17_MASK (0x20000U) +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT17_SHIFT (17U) +/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT17_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT18_MASK (0x40000U) +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT18_SHIFT (18U) +/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT18_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT19_MASK (0x80000U) +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT19_SHIFT (19U) +/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT19_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT20_MASK (0x100000U) +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT20_SHIFT (20U) +/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT20_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT21_MASK (0x200000U) +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT21_SHIFT (21U) +/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT21_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT22_MASK (0x400000U) +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT22_SHIFT (22U) +/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT22_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT23_MASK (0x800000U) +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT23_SHIFT (23U) +/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT23_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT24_MASK (0x1000000U) +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT24_SHIFT (24U) +/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT24_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT25_MASK (0x2000000U) +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT25_SHIFT (25U) +/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT25_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT26_MASK (0x4000000U) +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT26_SHIFT (26U) +/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT26_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT27_MASK (0x8000000U) +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT27_SHIFT (27U) +/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT27_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT28_MASK (0x10000000U) +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT28_SHIFT (28U) +/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT28_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT29_MASK (0x20000000U) +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT29_SHIFT (29U) +/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT29_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT30_MASK (0x40000000U) +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT30_SHIFT (30U) +/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT30_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT31_MASK (0x80000000U) +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT31_SHIFT (31U) +/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_BIT31_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W */ +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_COUNT (4U) + +/* The count of TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W */ +#define TRDC_MBC4_MBC_DOM14_MEM2_BLK_NSE_W_COUNT2 (2U) + +/*! @name MBC_DOM14_MEM3_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM3_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM3_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM3_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM3_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM3_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM3_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM3_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM3_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM3_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM3_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM3_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM3_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM3_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM3_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM3_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM3_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM3_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM3_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM3_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM3_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM3_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM3_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM3_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM3_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM3_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM3_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM3_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM3_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM3_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM3_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM3_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM3_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MBC_DOM14_MEM3_BLK_CFG_W */ +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_CFG_W_COUNT (4U) + +/* The count of TRDC_MBC4_MBC_DOM14_MEM3_BLK_CFG_W */ +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_CFG_W_COUNT2 (6U) + +/*! @name MBC_DOM14_MEM3_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ +/*! @{ */ + +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT0_MASK (0x1U) +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT0_SHIFT (0U) +/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT0_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT1_MASK (0x2U) +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT1_SHIFT (1U) +/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT1_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT2_MASK (0x4U) +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT2_SHIFT (2U) +/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT2_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT3_MASK (0x8U) +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT3_SHIFT (3U) +/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT3_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT4_MASK (0x10U) +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT4_SHIFT (4U) +/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT4_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT5_MASK (0x20U) +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT5_SHIFT (5U) +/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT5_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT6_MASK (0x40U) +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT6_SHIFT (6U) +/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT6_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT7_MASK (0x80U) +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT7_SHIFT (7U) +/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT7_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT8_MASK (0x100U) +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT8_SHIFT (8U) +/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT8_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT9_MASK (0x200U) +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT9_SHIFT (9U) +/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT9_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT10_MASK (0x400U) +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT10_SHIFT (10U) +/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT10_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT11_MASK (0x800U) +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT11_SHIFT (11U) +/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT11_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT12_MASK (0x1000U) +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT12_SHIFT (12U) +/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT12_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT13_MASK (0x2000U) +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT13_SHIFT (13U) +/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT13_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT14_MASK (0x4000U) +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT14_SHIFT (14U) +/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT14_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT15_MASK (0x8000U) +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT15_SHIFT (15U) +/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT15_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT16_MASK (0x10000U) +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT16_SHIFT (16U) +/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT16_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT17_MASK (0x20000U) +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT17_SHIFT (17U) +/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT17_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT18_MASK (0x40000U) +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT18_SHIFT (18U) +/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT18_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT19_MASK (0x80000U) +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT19_SHIFT (19U) +/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT19_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT20_MASK (0x100000U) +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT20_SHIFT (20U) +/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT20_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT21_MASK (0x200000U) +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT21_SHIFT (21U) +/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT21_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT22_MASK (0x400000U) +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT22_SHIFT (22U) +/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT22_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT23_MASK (0x800000U) +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT23_SHIFT (23U) +/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT23_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT24_MASK (0x1000000U) +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT24_SHIFT (24U) +/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT24_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT25_MASK (0x2000000U) +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT25_SHIFT (25U) +/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT25_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT26_MASK (0x4000000U) +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT26_SHIFT (26U) +/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT26_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT27_MASK (0x8000000U) +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT27_SHIFT (27U) +/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT27_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT28_MASK (0x10000000U) +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT28_SHIFT (28U) +/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT28_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT29_MASK (0x20000000U) +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT29_SHIFT (29U) +/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT29_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT30_MASK (0x40000000U) +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT30_SHIFT (30U) +/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT30_MASK) + +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT31_MASK (0x80000000U) +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT31_SHIFT (31U) +/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_BIT31_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W */ +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_COUNT (4U) + +/* The count of TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W */ +#define TRDC_MBC4_MBC_DOM14_MEM3_BLK_NSE_W_COUNT2 (2U) + +/*! @name MBC_DOM15_MEM0_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM0_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM0_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM0_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM0_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM0_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM0_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM0_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM0_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM0_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM0_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM0_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM0_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM0_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM0_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM0_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM0_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM0_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM0_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM0_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM0_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM0_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM0_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM0_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM0_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM0_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM0_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM0_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM0_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM0_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM0_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM0_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM0_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MBC_DOM15_MEM0_BLK_CFG_W */ +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_CFG_W_COUNT (4U) + +/* The count of TRDC_MBC4_MBC_DOM15_MEM0_BLK_CFG_W */ +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_CFG_W_COUNT2 (7U) + +/*! @name MBC_DOM15_MEM0_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ +/*! @{ */ + +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT0_MASK (0x1U) +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT0_SHIFT (0U) +/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT0_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT1_MASK (0x2U) +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT1_SHIFT (1U) +/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT1_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT2_MASK (0x4U) +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT2_SHIFT (2U) +/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT2_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT3_MASK (0x8U) +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT3_SHIFT (3U) +/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT3_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT4_MASK (0x10U) +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT4_SHIFT (4U) +/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT4_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT5_MASK (0x20U) +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT5_SHIFT (5U) +/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT5_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT6_MASK (0x40U) +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT6_SHIFT (6U) +/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT6_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT7_MASK (0x80U) +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT7_SHIFT (7U) +/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT7_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT8_MASK (0x100U) +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT8_SHIFT (8U) +/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT8_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT9_MASK (0x200U) +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT9_SHIFT (9U) +/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT9_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT10_MASK (0x400U) +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT10_SHIFT (10U) +/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT10_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT11_MASK (0x800U) +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT11_SHIFT (11U) +/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT11_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT12_MASK (0x1000U) +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT12_SHIFT (12U) +/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT12_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT13_MASK (0x2000U) +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT13_SHIFT (13U) +/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT13_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT14_MASK (0x4000U) +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT14_SHIFT (14U) +/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT14_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT15_MASK (0x8000U) +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT15_SHIFT (15U) +/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT15_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT16_MASK (0x10000U) +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT16_SHIFT (16U) +/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT16_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT17_MASK (0x20000U) +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT17_SHIFT (17U) +/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT17_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT18_MASK (0x40000U) +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT18_SHIFT (18U) +/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT18_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT19_MASK (0x80000U) +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT19_SHIFT (19U) +/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT19_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT20_MASK (0x100000U) +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT20_SHIFT (20U) +/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT20_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT21_MASK (0x200000U) +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT21_SHIFT (21U) +/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT21_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT22_MASK (0x400000U) +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT22_SHIFT (22U) +/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT22_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT23_MASK (0x800000U) +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT23_SHIFT (23U) +/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT23_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT24_MASK (0x1000000U) +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT24_SHIFT (24U) +/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT24_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT25_MASK (0x2000000U) +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT25_SHIFT (25U) +/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT25_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT26_MASK (0x4000000U) +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT26_SHIFT (26U) +/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT26_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT27_MASK (0x8000000U) +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT27_SHIFT (27U) +/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT27_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT28_MASK (0x10000000U) +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT28_SHIFT (28U) +/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT28_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT29_MASK (0x20000000U) +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT29_SHIFT (29U) +/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT29_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT30_MASK (0x40000000U) +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT30_SHIFT (30U) +/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT30_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT31_MASK (0x80000000U) +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT31_SHIFT (31U) +/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_BIT31_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W */ +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_COUNT (4U) + +/* The count of TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W */ +#define TRDC_MBC4_MBC_DOM15_MEM0_BLK_NSE_W_COUNT2 (2U) + +/*! @name MBC_DOM15_MEM1_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM1_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM1_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM1_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM1_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM1_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM1_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM1_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM1_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM1_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM1_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM1_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM1_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM1_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM1_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM1_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM1_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM1_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM1_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM1_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM1_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM1_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM1_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM1_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM1_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM1_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM1_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM1_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM1_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM1_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM1_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM1_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM1_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MBC_DOM15_MEM1_BLK_CFG_W */ +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_CFG_W_COUNT (4U) + +/* The count of TRDC_MBC4_MBC_DOM15_MEM1_BLK_CFG_W */ +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_CFG_W_COUNT2 (3U) + +/*! @name MBC_DOM15_MEM1_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ +/*! @{ */ + +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT0_MASK (0x1U) +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT0_SHIFT (0U) +/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT0_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT1_MASK (0x2U) +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT1_SHIFT (1U) +/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT1_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT2_MASK (0x4U) +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT2_SHIFT (2U) +/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT2_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT3_MASK (0x8U) +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT3_SHIFT (3U) +/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT3_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT4_MASK (0x10U) +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT4_SHIFT (4U) +/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT4_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT5_MASK (0x20U) +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT5_SHIFT (5U) +/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT5_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT6_MASK (0x40U) +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT6_SHIFT (6U) +/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT6_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT7_MASK (0x80U) +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT7_SHIFT (7U) +/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT7_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT8_MASK (0x100U) +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT8_SHIFT (8U) +/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT8_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT9_MASK (0x200U) +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT9_SHIFT (9U) +/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT9_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT10_MASK (0x400U) +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT10_SHIFT (10U) +/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT10_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT11_MASK (0x800U) +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT11_SHIFT (11U) +/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT11_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT12_MASK (0x1000U) +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT12_SHIFT (12U) +/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT12_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT13_MASK (0x2000U) +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT13_SHIFT (13U) +/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT13_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT14_MASK (0x4000U) +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT14_SHIFT (14U) +/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT14_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT15_MASK (0x8000U) +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT15_SHIFT (15U) +/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT15_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT16_MASK (0x10000U) +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT16_SHIFT (16U) +/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT16_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT17_MASK (0x20000U) +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT17_SHIFT (17U) +/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT17_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT18_MASK (0x40000U) +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT18_SHIFT (18U) +/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT18_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT19_MASK (0x80000U) +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT19_SHIFT (19U) +/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT19_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT20_MASK (0x100000U) +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT20_SHIFT (20U) +/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT20_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT21_MASK (0x200000U) +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT21_SHIFT (21U) +/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT21_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT22_MASK (0x400000U) +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT22_SHIFT (22U) +/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT22_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT23_MASK (0x800000U) +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT23_SHIFT (23U) +/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT23_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT24_MASK (0x1000000U) +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT24_SHIFT (24U) +/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT24_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT25_MASK (0x2000000U) +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT25_SHIFT (25U) +/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT25_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT26_MASK (0x4000000U) +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT26_SHIFT (26U) +/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT26_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT27_MASK (0x8000000U) +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT27_SHIFT (27U) +/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT27_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT28_MASK (0x10000000U) +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT28_SHIFT (28U) +/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT28_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT29_MASK (0x20000000U) +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT29_SHIFT (29U) +/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT29_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT30_MASK (0x40000000U) +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT30_SHIFT (30U) +/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT30_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT31_MASK (0x80000000U) +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT31_SHIFT (31U) +/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_BIT31_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W */ +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_COUNT (4U) + +/* The count of TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W */ +#define TRDC_MBC4_MBC_DOM15_MEM1_BLK_NSE_W_COUNT2 (1U) + +/*! @name MBC_DOM15_MEM2_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM2_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM2_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM2_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM2_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM2_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM2_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM2_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM2_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM2_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM2_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM2_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM2_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM2_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM2_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM2_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM2_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM2_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM2_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM2_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM2_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM2_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM2_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM2_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM2_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM2_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM2_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM2_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM2_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM2_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM2_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM2_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM2_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MBC_DOM15_MEM2_BLK_CFG_W */ +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_CFG_W_COUNT (4U) + +/* The count of TRDC_MBC4_MBC_DOM15_MEM2_BLK_CFG_W */ +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_CFG_W_COUNT2 (5U) + +/*! @name MBC_DOM15_MEM2_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ +/*! @{ */ + +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT0_MASK (0x1U) +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT0_SHIFT (0U) +/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT0_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT1_MASK (0x2U) +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT1_SHIFT (1U) +/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT1_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT2_MASK (0x4U) +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT2_SHIFT (2U) +/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT2_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT3_MASK (0x8U) +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT3_SHIFT (3U) +/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT3_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT4_MASK (0x10U) +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT4_SHIFT (4U) +/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT4_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT5_MASK (0x20U) +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT5_SHIFT (5U) +/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT5_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT6_MASK (0x40U) +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT6_SHIFT (6U) +/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT6_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT7_MASK (0x80U) +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT7_SHIFT (7U) +/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT7_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT8_MASK (0x100U) +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT8_SHIFT (8U) +/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT8_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT9_MASK (0x200U) +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT9_SHIFT (9U) +/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT9_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT10_MASK (0x400U) +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT10_SHIFT (10U) +/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT10_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT11_MASK (0x800U) +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT11_SHIFT (11U) +/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT11_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT12_MASK (0x1000U) +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT12_SHIFT (12U) +/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT12_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT13_MASK (0x2000U) +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT13_SHIFT (13U) +/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT13_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT14_MASK (0x4000U) +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT14_SHIFT (14U) +/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT14_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT15_MASK (0x8000U) +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT15_SHIFT (15U) +/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT15_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT16_MASK (0x10000U) +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT16_SHIFT (16U) +/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT16_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT17_MASK (0x20000U) +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT17_SHIFT (17U) +/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT17_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT18_MASK (0x40000U) +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT18_SHIFT (18U) +/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT18_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT19_MASK (0x80000U) +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT19_SHIFT (19U) +/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT19_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT20_MASK (0x100000U) +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT20_SHIFT (20U) +/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT20_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT21_MASK (0x200000U) +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT21_SHIFT (21U) +/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT21_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT22_MASK (0x400000U) +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT22_SHIFT (22U) +/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT22_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT23_MASK (0x800000U) +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT23_SHIFT (23U) +/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT23_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT24_MASK (0x1000000U) +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT24_SHIFT (24U) +/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT24_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT25_MASK (0x2000000U) +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT25_SHIFT (25U) +/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT25_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT26_MASK (0x4000000U) +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT26_SHIFT (26U) +/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT26_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT27_MASK (0x8000000U) +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT27_SHIFT (27U) +/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT27_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT28_MASK (0x10000000U) +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT28_SHIFT (28U) +/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT28_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT29_MASK (0x20000000U) +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT29_SHIFT (29U) +/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT29_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT30_MASK (0x40000000U) +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT30_SHIFT (30U) +/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT30_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT31_MASK (0x80000000U) +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT31_SHIFT (31U) +/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_BIT31_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W */ +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_COUNT (4U) + +/* The count of TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W */ +#define TRDC_MBC4_MBC_DOM15_MEM2_BLK_NSE_W_COUNT2 (2U) + +/*! @name MBC_DOM15_MEM3_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM3_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM3_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM3_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM3_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM3_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM3_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM3_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM3_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM3_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM3_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM3_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM3_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM3_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM3_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM3_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM3_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM3_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM3_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM3_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM3_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM3_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM3_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM3_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM3_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM3_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM3_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM3_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM3_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM3_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM3_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM3_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM3_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MBC_DOM15_MEM3_BLK_CFG_W */ +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_CFG_W_COUNT (4U) + +/* The count of TRDC_MBC4_MBC_DOM15_MEM3_BLK_CFG_W */ +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_CFG_W_COUNT2 (6U) + +/*! @name MBC_DOM15_MEM3_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ +/*! @{ */ + +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT0_MASK (0x1U) +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT0_SHIFT (0U) +/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT0_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT1_MASK (0x2U) +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT1_SHIFT (1U) +/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT1_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT2_MASK (0x4U) +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT2_SHIFT (2U) +/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT2_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT3_MASK (0x8U) +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT3_SHIFT (3U) +/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT3_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT4_MASK (0x10U) +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT4_SHIFT (4U) +/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT4_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT5_MASK (0x20U) +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT5_SHIFT (5U) +/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT5_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT6_MASK (0x40U) +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT6_SHIFT (6U) +/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT6_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT7_MASK (0x80U) +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT7_SHIFT (7U) +/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT7_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT8_MASK (0x100U) +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT8_SHIFT (8U) +/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT8_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT9_MASK (0x200U) +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT9_SHIFT (9U) +/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT9_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT10_MASK (0x400U) +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT10_SHIFT (10U) +/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT10_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT11_MASK (0x800U) +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT11_SHIFT (11U) +/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT11_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT12_MASK (0x1000U) +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT12_SHIFT (12U) +/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT12_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT13_MASK (0x2000U) +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT13_SHIFT (13U) +/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT13_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT14_MASK (0x4000U) +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT14_SHIFT (14U) +/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT14_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT15_MASK (0x8000U) +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT15_SHIFT (15U) +/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT15_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT16_MASK (0x10000U) +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT16_SHIFT (16U) +/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT16_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT17_MASK (0x20000U) +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT17_SHIFT (17U) +/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT17_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT18_MASK (0x40000U) +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT18_SHIFT (18U) +/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT18_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT19_MASK (0x80000U) +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT19_SHIFT (19U) +/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT19_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT20_MASK (0x100000U) +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT20_SHIFT (20U) +/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT20_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT21_MASK (0x200000U) +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT21_SHIFT (21U) +/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT21_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT22_MASK (0x400000U) +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT22_SHIFT (22U) +/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT22_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT23_MASK (0x800000U) +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT23_SHIFT (23U) +/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT23_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT24_MASK (0x1000000U) +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT24_SHIFT (24U) +/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT24_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT25_MASK (0x2000000U) +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT25_SHIFT (25U) +/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT25_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT26_MASK (0x4000000U) +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT26_SHIFT (26U) +/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT26_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT27_MASK (0x8000000U) +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT27_SHIFT (27U) +/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT27_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT28_MASK (0x10000000U) +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT28_SHIFT (28U) +/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT28_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT29_MASK (0x20000000U) +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT29_SHIFT (29U) +/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT29_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT30_MASK (0x40000000U) +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT30_SHIFT (30U) +/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT30_MASK) + +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT31_MASK (0x80000000U) +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT31_SHIFT (31U) +/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_BIT31_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W */ +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_COUNT (4U) + +/* The count of TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W */ +#define TRDC_MBC4_MBC_DOM15_MEM3_BLK_NSE_W_COUNT2 (2U) + +/*! @name MRC_GLBCFG - MRC Global Configuration Register */ +/*! @{ */ + +#define TRDC_MBC4_MRC_GLBCFG_NRGNS_MASK (0x1FU) +#define TRDC_MBC4_MRC_GLBCFG_NRGNS_SHIFT (0U) +/*! NRGNS - Number of regions [1-16] */ +#define TRDC_MBC4_MRC_GLBCFG_NRGNS(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_GLBCFG_NRGNS_SHIFT)) & TRDC_MBC4_MRC_GLBCFG_NRGNS_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MRC_GLBCFG */ +#define TRDC_MBC4_MRC_GLBCFG_COUNT (1U) + +/*! @name MRC_NSE_RGN_INDIRECT - MRC NonSecure Enable Region Indirect */ +/*! @{ */ + +#define TRDC_MBC4_MRC_NSE_RGN_INDIRECT_DID_SEL_MASK (0xFFFF0000U) +#define TRDC_MBC4_MRC_NSE_RGN_INDIRECT_DID_SEL_SHIFT (16U) +/*! DID_SEL - DID Select */ +#define TRDC_MBC4_MRC_NSE_RGN_INDIRECT_DID_SEL(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_NSE_RGN_INDIRECT_DID_SEL_SHIFT)) & TRDC_MBC4_MRC_NSE_RGN_INDIRECT_DID_SEL_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MRC_NSE_RGN_INDIRECT */ +#define TRDC_MBC4_MRC_NSE_RGN_INDIRECT_COUNT (1U) + +/*! @name MRC_NSE_RGN_SET - MRC NonSecure Enable Region Set */ +/*! @{ */ + +#define TRDC_MBC4_MRC_NSE_RGN_SET_W1SET_MASK (0xFFFFU) +#define TRDC_MBC4_MRC_NSE_RGN_SET_W1SET_SHIFT (0U) +/*! W1SET - Write-1 Set */ +#define TRDC_MBC4_MRC_NSE_RGN_SET_W1SET(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_NSE_RGN_SET_W1SET_SHIFT)) & TRDC_MBC4_MRC_NSE_RGN_SET_W1SET_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MRC_NSE_RGN_SET */ +#define TRDC_MBC4_MRC_NSE_RGN_SET_COUNT (1U) + +/*! @name MRC_NSE_RGN_CLR - MRC NonSecure Enable Region Clear */ +/*! @{ */ + +#define TRDC_MBC4_MRC_NSE_RGN_CLR_W1CLR_MASK (0xFFFFU) +#define TRDC_MBC4_MRC_NSE_RGN_CLR_W1CLR_SHIFT (0U) +/*! W1CLR - Write-1 Clear */ +#define TRDC_MBC4_MRC_NSE_RGN_CLR_W1CLR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_NSE_RGN_CLR_W1CLR_SHIFT)) & TRDC_MBC4_MRC_NSE_RGN_CLR_W1CLR_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MRC_NSE_RGN_CLR */ +#define TRDC_MBC4_MRC_NSE_RGN_CLR_COUNT (1U) + +/*! @name MRC_NSE_RGN_CLR_ALL - MRC NonSecure Enable Region Clear All */ +/*! @{ */ + +#define TRDC_MBC4_MRC_NSE_RGN_CLR_ALL_DID_SEL_MASK (0xFFFF0000U) +#define TRDC_MBC4_MRC_NSE_RGN_CLR_ALL_DID_SEL_SHIFT (16U) +/*! DID_SEL - DID Select */ +#define TRDC_MBC4_MRC_NSE_RGN_CLR_ALL_DID_SEL(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_NSE_RGN_CLR_ALL_DID_SEL_SHIFT)) & TRDC_MBC4_MRC_NSE_RGN_CLR_ALL_DID_SEL_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MRC_NSE_RGN_CLR_ALL */ +#define TRDC_MBC4_MRC_NSE_RGN_CLR_ALL_COUNT (1U) + +/*! @name MRC_GLBAC - MRC Global Access Control */ +/*! @{ */ + +#define TRDC_MBC4_MRC_GLBAC_NUX_MASK (0x1U) +#define TRDC_MBC4_MRC_GLBAC_NUX_SHIFT (0U) +/*! NUX - NonsecureUser Execute + * 0b0..Execute access is not allowed in Nonsecure User mode. + * 0b1..Execute access is allowed in Nonsecure User mode. + */ +#define TRDC_MBC4_MRC_GLBAC_NUX(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_GLBAC_NUX_SHIFT)) & TRDC_MBC4_MRC_GLBAC_NUX_MASK) + +#define TRDC_MBC4_MRC_GLBAC_NUW_MASK (0x2U) +#define TRDC_MBC4_MRC_GLBAC_NUW_SHIFT (1U) +/*! NUW - NonsecureUser Write + * 0b0..Write access is not allowed in Nonsecure User mode. + * 0b1..Write access is allowed in Nonsecure User mode. + */ +#define TRDC_MBC4_MRC_GLBAC_NUW(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_GLBAC_NUW_SHIFT)) & TRDC_MBC4_MRC_GLBAC_NUW_MASK) + +#define TRDC_MBC4_MRC_GLBAC_NUR_MASK (0x4U) +#define TRDC_MBC4_MRC_GLBAC_NUR_SHIFT (2U) +/*! NUR - NonsecureUser Read + * 0b0..Read access is not allowed in Nonsecure User mode. + * 0b1..Read access is allowed in Nonsecure User mode. + */ +#define TRDC_MBC4_MRC_GLBAC_NUR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_GLBAC_NUR_SHIFT)) & TRDC_MBC4_MRC_GLBAC_NUR_MASK) + +#define TRDC_MBC4_MRC_GLBAC_NPX_MASK (0x10U) +#define TRDC_MBC4_MRC_GLBAC_NPX_SHIFT (4U) +/*! NPX - NonsecurePriv Execute + * 0b0..Execute access is not allowed in Nonsecure Privilege mode. + * 0b1..Execute access is allowed in Nonsecure Privilege mode. + */ +#define TRDC_MBC4_MRC_GLBAC_NPX(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_GLBAC_NPX_SHIFT)) & TRDC_MBC4_MRC_GLBAC_NPX_MASK) + +#define TRDC_MBC4_MRC_GLBAC_NPW_MASK (0x20U) +#define TRDC_MBC4_MRC_GLBAC_NPW_SHIFT (5U) +/*! NPW - NonsecurePriv Write + * 0b0..Write access is not allowed in Nonsecure Privilege mode. + * 0b1..Write access is allowed in Nonsecure Privilege mode. + */ +#define TRDC_MBC4_MRC_GLBAC_NPW(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_GLBAC_NPW_SHIFT)) & TRDC_MBC4_MRC_GLBAC_NPW_MASK) + +#define TRDC_MBC4_MRC_GLBAC_NPR_MASK (0x40U) +#define TRDC_MBC4_MRC_GLBAC_NPR_SHIFT (6U) +/*! NPR - NonsecurePriv Read + * 0b0..Read access is not allowed in Nonsecure Privilege mode. + * 0b1..Read access is allowed in Nonsecure Privilege mode. + */ +#define TRDC_MBC4_MRC_GLBAC_NPR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_GLBAC_NPR_SHIFT)) & TRDC_MBC4_MRC_GLBAC_NPR_MASK) + +#define TRDC_MBC4_MRC_GLBAC_SUX_MASK (0x100U) +#define TRDC_MBC4_MRC_GLBAC_SUX_SHIFT (8U) +/*! SUX - SecureUser Execute + * 0b0..Execute access is not allowed in Secure User mode. + * 0b1..Execute access is allowed in Secure User mode. + */ +#define TRDC_MBC4_MRC_GLBAC_SUX(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_GLBAC_SUX_SHIFT)) & TRDC_MBC4_MRC_GLBAC_SUX_MASK) + +#define TRDC_MBC4_MRC_GLBAC_SUW_MASK (0x200U) +#define TRDC_MBC4_MRC_GLBAC_SUW_SHIFT (9U) +/*! SUW - SecureUser Write + * 0b0..Write access is not allowed in Secure User mode. + * 0b1..Write access is allowed in Secure User mode. + */ +#define TRDC_MBC4_MRC_GLBAC_SUW(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_GLBAC_SUW_SHIFT)) & TRDC_MBC4_MRC_GLBAC_SUW_MASK) + +#define TRDC_MBC4_MRC_GLBAC_SUR_MASK (0x400U) +#define TRDC_MBC4_MRC_GLBAC_SUR_SHIFT (10U) +/*! SUR - SecureUser Read + * 0b0..Read access is not allowed in Secure User mode. + * 0b1..Read access is allowed in Secure User mode. + */ +#define TRDC_MBC4_MRC_GLBAC_SUR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_GLBAC_SUR_SHIFT)) & TRDC_MBC4_MRC_GLBAC_SUR_MASK) + +#define TRDC_MBC4_MRC_GLBAC_SPX_MASK (0x1000U) +#define TRDC_MBC4_MRC_GLBAC_SPX_SHIFT (12U) +/*! SPX - SecurePriv Execute + * 0b0..Execute access is not allowed in Secure Privilege mode. + * 0b1..Execute access is allowed in Secure Privilege mode. + */ +#define TRDC_MBC4_MRC_GLBAC_SPX(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_GLBAC_SPX_SHIFT)) & TRDC_MBC4_MRC_GLBAC_SPX_MASK) + +#define TRDC_MBC4_MRC_GLBAC_SPW_MASK (0x2000U) +#define TRDC_MBC4_MRC_GLBAC_SPW_SHIFT (13U) +/*! SPW - SecurePriv Write + * 0b0..Write access is not allowed in Secure Privilege mode. + * 0b1..Write access is allowed in Secure Privilege mode. + */ +#define TRDC_MBC4_MRC_GLBAC_SPW(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_GLBAC_SPW_SHIFT)) & TRDC_MBC4_MRC_GLBAC_SPW_MASK) + +#define TRDC_MBC4_MRC_GLBAC_SPR_MASK (0x4000U) +#define TRDC_MBC4_MRC_GLBAC_SPR_SHIFT (14U) +/*! SPR - SecurePriv Read + * 0b0..Read access is not allowed in Secure Privilege mode. + * 0b1..Read access is allowed in Secure Privilege mode. + */ +#define TRDC_MBC4_MRC_GLBAC_SPR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_GLBAC_SPR_SHIFT)) & TRDC_MBC4_MRC_GLBAC_SPR_MASK) + +#define TRDC_MBC4_MRC_GLBAC_LK_MASK (0x80000000U) +#define TRDC_MBC4_MRC_GLBAC_LK_SHIFT (31U) +/*! LK - LOCK + * 0b0..This register is not locked and can be altered. + * 0b1..This register is locked (read-only) and cannot be altered. + */ +#define TRDC_MBC4_MRC_GLBAC_LK(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_GLBAC_LK_SHIFT)) & TRDC_MBC4_MRC_GLBAC_LK_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MRC_GLBAC */ +#define TRDC_MBC4_MRC_GLBAC_COUNT (1U) + +/* The count of TRDC_MBC4_MRC_GLBAC */ +#define TRDC_MBC4_MRC_GLBAC_COUNT2 (8U) + +/*! @name MRC_DOM0_RGD_W - MRC Region Descriptor Word 0..MRC Region Descriptor Word 1 */ +/*! @{ */ + +#define TRDC_MBC4_MRC_DOM0_RGD_W_MRACSEL_MASK (0x7U) +#define TRDC_MBC4_MRC_DOM0_RGD_W_MRACSEL_SHIFT (0U) +/*! MRACSEL - Memory Region Access Control Select + * 0b000..Select MRC_GLBAC0 access control policy + * 0b001..Select MRC_GLBAC1 access control policy + * 0b010..Select MRC_GLBAC2 access control policy + * 0b011..Select MRC_GLBAC3 access control policy + * 0b100..Select MRC_GLBAC4 access control policy + * 0b101..Select MRC_GLBAC5 access control policy + * 0b110..Select MRC_GLBAC6 access control policy + * 0b111..Select MRC_GLBAC7 access control policy + */ +#define TRDC_MBC4_MRC_DOM0_RGD_W_MRACSEL(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM0_RGD_W_MRACSEL_SHIFT)) & TRDC_MBC4_MRC_DOM0_RGD_W_MRACSEL_MASK) + +#define TRDC_MBC4_MRC_DOM0_RGD_W_VLD_MASK (0x1U) +#define TRDC_MBC4_MRC_DOM0_RGD_W_VLD_SHIFT (0U) +/*! VLD - Valid */ +#define TRDC_MBC4_MRC_DOM0_RGD_W_VLD(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM0_RGD_W_VLD_SHIFT)) & TRDC_MBC4_MRC_DOM0_RGD_W_VLD_MASK) + +#define TRDC_MBC4_MRC_DOM0_RGD_W_NSE_MASK (0x10U) +#define TRDC_MBC4_MRC_DOM0_RGD_W_NSE_SHIFT (4U) +/*! NSE - NonSecure Enable + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in this register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM0_RGD_W_NSE(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM0_RGD_W_NSE_SHIFT)) & TRDC_MBC4_MRC_DOM0_RGD_W_NSE_MASK) + +#define TRDC_MBC4_MRC_DOM0_RGD_W_END_ADDR_MASK (0xFFFFC000U) +#define TRDC_MBC4_MRC_DOM0_RGD_W_END_ADDR_SHIFT (14U) +/*! END_ADDR - End Address */ +#define TRDC_MBC4_MRC_DOM0_RGD_W_END_ADDR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM0_RGD_W_END_ADDR_SHIFT)) & TRDC_MBC4_MRC_DOM0_RGD_W_END_ADDR_MASK) + +#define TRDC_MBC4_MRC_DOM0_RGD_W_STRT_ADDR_MASK (0xFFFFC000U) +#define TRDC_MBC4_MRC_DOM0_RGD_W_STRT_ADDR_SHIFT (14U) +/*! STRT_ADDR - Start Address */ +#define TRDC_MBC4_MRC_DOM0_RGD_W_STRT_ADDR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM0_RGD_W_STRT_ADDR_SHIFT)) & TRDC_MBC4_MRC_DOM0_RGD_W_STRT_ADDR_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MRC_DOM0_RGD_W */ +#define TRDC_MBC4_MRC_DOM0_RGD_W_COUNT (1U) + +/* The count of TRDC_MBC4_MRC_DOM0_RGD_W */ +#define TRDC_MBC4_MRC_DOM0_RGD_W_COUNT2 (16U) + +/* The count of TRDC_MBC4_MRC_DOM0_RGD_W */ +#define TRDC_MBC4_MRC_DOM0_RGD_W_COUNT3 (2U) + +/*! @name MRC_DOM0_RGD_NSE - MRC Region Descriptor NonSecure Enable */ +/*! @{ */ + +#define TRDC_MBC4_MRC_DOM0_RGD_NSE_BIT0_MASK (0x1U) +#define TRDC_MBC4_MRC_DOM0_RGD_NSE_BIT0_SHIFT (0U) +/*! BIT0 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM0_RGD_NSE_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM0_RGD_NSE_BIT0_SHIFT)) & TRDC_MBC4_MRC_DOM0_RGD_NSE_BIT0_MASK) + +#define TRDC_MBC4_MRC_DOM0_RGD_NSE_BIT1_MASK (0x2U) +#define TRDC_MBC4_MRC_DOM0_RGD_NSE_BIT1_SHIFT (1U) +/*! BIT1 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM0_RGD_NSE_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM0_RGD_NSE_BIT1_SHIFT)) & TRDC_MBC4_MRC_DOM0_RGD_NSE_BIT1_MASK) + +#define TRDC_MBC4_MRC_DOM0_RGD_NSE_BIT2_MASK (0x4U) +#define TRDC_MBC4_MRC_DOM0_RGD_NSE_BIT2_SHIFT (2U) +/*! BIT2 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM0_RGD_NSE_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM0_RGD_NSE_BIT2_SHIFT)) & TRDC_MBC4_MRC_DOM0_RGD_NSE_BIT2_MASK) + +#define TRDC_MBC4_MRC_DOM0_RGD_NSE_BIT3_MASK (0x8U) +#define TRDC_MBC4_MRC_DOM0_RGD_NSE_BIT3_SHIFT (3U) +/*! BIT3 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM0_RGD_NSE_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM0_RGD_NSE_BIT3_SHIFT)) & TRDC_MBC4_MRC_DOM0_RGD_NSE_BIT3_MASK) + +#define TRDC_MBC4_MRC_DOM0_RGD_NSE_BIT4_MASK (0x10U) +#define TRDC_MBC4_MRC_DOM0_RGD_NSE_BIT4_SHIFT (4U) +/*! BIT4 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM0_RGD_NSE_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM0_RGD_NSE_BIT4_SHIFT)) & TRDC_MBC4_MRC_DOM0_RGD_NSE_BIT4_MASK) + +#define TRDC_MBC4_MRC_DOM0_RGD_NSE_BIT5_MASK (0x20U) +#define TRDC_MBC4_MRC_DOM0_RGD_NSE_BIT5_SHIFT (5U) +/*! BIT5 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM0_RGD_NSE_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM0_RGD_NSE_BIT5_SHIFT)) & TRDC_MBC4_MRC_DOM0_RGD_NSE_BIT5_MASK) + +#define TRDC_MBC4_MRC_DOM0_RGD_NSE_BIT6_MASK (0x40U) +#define TRDC_MBC4_MRC_DOM0_RGD_NSE_BIT6_SHIFT (6U) +/*! BIT6 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM0_RGD_NSE_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM0_RGD_NSE_BIT6_SHIFT)) & TRDC_MBC4_MRC_DOM0_RGD_NSE_BIT6_MASK) + +#define TRDC_MBC4_MRC_DOM0_RGD_NSE_BIT7_MASK (0x80U) +#define TRDC_MBC4_MRC_DOM0_RGD_NSE_BIT7_SHIFT (7U) +/*! BIT7 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM0_RGD_NSE_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM0_RGD_NSE_BIT7_SHIFT)) & TRDC_MBC4_MRC_DOM0_RGD_NSE_BIT7_MASK) + +#define TRDC_MBC4_MRC_DOM0_RGD_NSE_BIT8_MASK (0x100U) +#define TRDC_MBC4_MRC_DOM0_RGD_NSE_BIT8_SHIFT (8U) +/*! BIT8 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM0_RGD_NSE_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM0_RGD_NSE_BIT8_SHIFT)) & TRDC_MBC4_MRC_DOM0_RGD_NSE_BIT8_MASK) + +#define TRDC_MBC4_MRC_DOM0_RGD_NSE_BIT9_MASK (0x200U) +#define TRDC_MBC4_MRC_DOM0_RGD_NSE_BIT9_SHIFT (9U) +/*! BIT9 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM0_RGD_NSE_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM0_RGD_NSE_BIT9_SHIFT)) & TRDC_MBC4_MRC_DOM0_RGD_NSE_BIT9_MASK) + +#define TRDC_MBC4_MRC_DOM0_RGD_NSE_BIT10_MASK (0x400U) +#define TRDC_MBC4_MRC_DOM0_RGD_NSE_BIT10_SHIFT (10U) +/*! BIT10 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM0_RGD_NSE_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM0_RGD_NSE_BIT10_SHIFT)) & TRDC_MBC4_MRC_DOM0_RGD_NSE_BIT10_MASK) + +#define TRDC_MBC4_MRC_DOM0_RGD_NSE_BIT11_MASK (0x800U) +#define TRDC_MBC4_MRC_DOM0_RGD_NSE_BIT11_SHIFT (11U) +/*! BIT11 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM0_RGD_NSE_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM0_RGD_NSE_BIT11_SHIFT)) & TRDC_MBC4_MRC_DOM0_RGD_NSE_BIT11_MASK) + +#define TRDC_MBC4_MRC_DOM0_RGD_NSE_BIT12_MASK (0x1000U) +#define TRDC_MBC4_MRC_DOM0_RGD_NSE_BIT12_SHIFT (12U) +/*! BIT12 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM0_RGD_NSE_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM0_RGD_NSE_BIT12_SHIFT)) & TRDC_MBC4_MRC_DOM0_RGD_NSE_BIT12_MASK) + +#define TRDC_MBC4_MRC_DOM0_RGD_NSE_BIT13_MASK (0x2000U) +#define TRDC_MBC4_MRC_DOM0_RGD_NSE_BIT13_SHIFT (13U) +/*! BIT13 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM0_RGD_NSE_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM0_RGD_NSE_BIT13_SHIFT)) & TRDC_MBC4_MRC_DOM0_RGD_NSE_BIT13_MASK) + +#define TRDC_MBC4_MRC_DOM0_RGD_NSE_BIT14_MASK (0x4000U) +#define TRDC_MBC4_MRC_DOM0_RGD_NSE_BIT14_SHIFT (14U) +/*! BIT14 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM0_RGD_NSE_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM0_RGD_NSE_BIT14_SHIFT)) & TRDC_MBC4_MRC_DOM0_RGD_NSE_BIT14_MASK) + +#define TRDC_MBC4_MRC_DOM0_RGD_NSE_BIT15_MASK (0x8000U) +#define TRDC_MBC4_MRC_DOM0_RGD_NSE_BIT15_SHIFT (15U) +/*! BIT15 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM0_RGD_NSE_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM0_RGD_NSE_BIT15_SHIFT)) & TRDC_MBC4_MRC_DOM0_RGD_NSE_BIT15_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MRC_DOM0_RGD_NSE */ +#define TRDC_MBC4_MRC_DOM0_RGD_NSE_COUNT (1U) + +/*! @name MRC_DOM1_RGD_W - MRC Region Descriptor Word 0..MRC Region Descriptor Word 1 */ +/*! @{ */ + +#define TRDC_MBC4_MRC_DOM1_RGD_W_MRACSEL_MASK (0x7U) +#define TRDC_MBC4_MRC_DOM1_RGD_W_MRACSEL_SHIFT (0U) +/*! MRACSEL - Memory Region Access Control Select + * 0b000..Select MRC_GLBAC0 access control policy + * 0b001..Select MRC_GLBAC1 access control policy + * 0b010..Select MRC_GLBAC2 access control policy + * 0b011..Select MRC_GLBAC3 access control policy + * 0b100..Select MRC_GLBAC4 access control policy + * 0b101..Select MRC_GLBAC5 access control policy + * 0b110..Select MRC_GLBAC6 access control policy + * 0b111..Select MRC_GLBAC7 access control policy + */ +#define TRDC_MBC4_MRC_DOM1_RGD_W_MRACSEL(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM1_RGD_W_MRACSEL_SHIFT)) & TRDC_MBC4_MRC_DOM1_RGD_W_MRACSEL_MASK) + +#define TRDC_MBC4_MRC_DOM1_RGD_W_VLD_MASK (0x1U) +#define TRDC_MBC4_MRC_DOM1_RGD_W_VLD_SHIFT (0U) +/*! VLD - Valid */ +#define TRDC_MBC4_MRC_DOM1_RGD_W_VLD(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM1_RGD_W_VLD_SHIFT)) & TRDC_MBC4_MRC_DOM1_RGD_W_VLD_MASK) + +#define TRDC_MBC4_MRC_DOM1_RGD_W_NSE_MASK (0x10U) +#define TRDC_MBC4_MRC_DOM1_RGD_W_NSE_SHIFT (4U) +/*! NSE - NonSecure Enable + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in this register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM1_RGD_W_NSE(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM1_RGD_W_NSE_SHIFT)) & TRDC_MBC4_MRC_DOM1_RGD_W_NSE_MASK) + +#define TRDC_MBC4_MRC_DOM1_RGD_W_END_ADDR_MASK (0xFFFFC000U) +#define TRDC_MBC4_MRC_DOM1_RGD_W_END_ADDR_SHIFT (14U) +/*! END_ADDR - End Address */ +#define TRDC_MBC4_MRC_DOM1_RGD_W_END_ADDR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM1_RGD_W_END_ADDR_SHIFT)) & TRDC_MBC4_MRC_DOM1_RGD_W_END_ADDR_MASK) + +#define TRDC_MBC4_MRC_DOM1_RGD_W_STRT_ADDR_MASK (0xFFFFC000U) +#define TRDC_MBC4_MRC_DOM1_RGD_W_STRT_ADDR_SHIFT (14U) +/*! STRT_ADDR - Start Address */ +#define TRDC_MBC4_MRC_DOM1_RGD_W_STRT_ADDR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM1_RGD_W_STRT_ADDR_SHIFT)) & TRDC_MBC4_MRC_DOM1_RGD_W_STRT_ADDR_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MRC_DOM1_RGD_W */ +#define TRDC_MBC4_MRC_DOM1_RGD_W_COUNT (1U) + +/* The count of TRDC_MBC4_MRC_DOM1_RGD_W */ +#define TRDC_MBC4_MRC_DOM1_RGD_W_COUNT2 (16U) + +/* The count of TRDC_MBC4_MRC_DOM1_RGD_W */ +#define TRDC_MBC4_MRC_DOM1_RGD_W_COUNT3 (2U) + +/*! @name MRC_DOM1_RGD_NSE - MRC Region Descriptor NonSecure Enable */ +/*! @{ */ + +#define TRDC_MBC4_MRC_DOM1_RGD_NSE_BIT0_MASK (0x1U) +#define TRDC_MBC4_MRC_DOM1_RGD_NSE_BIT0_SHIFT (0U) +/*! BIT0 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM1_RGD_NSE_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM1_RGD_NSE_BIT0_SHIFT)) & TRDC_MBC4_MRC_DOM1_RGD_NSE_BIT0_MASK) + +#define TRDC_MBC4_MRC_DOM1_RGD_NSE_BIT1_MASK (0x2U) +#define TRDC_MBC4_MRC_DOM1_RGD_NSE_BIT1_SHIFT (1U) +/*! BIT1 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM1_RGD_NSE_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM1_RGD_NSE_BIT1_SHIFT)) & TRDC_MBC4_MRC_DOM1_RGD_NSE_BIT1_MASK) + +#define TRDC_MBC4_MRC_DOM1_RGD_NSE_BIT2_MASK (0x4U) +#define TRDC_MBC4_MRC_DOM1_RGD_NSE_BIT2_SHIFT (2U) +/*! BIT2 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM1_RGD_NSE_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM1_RGD_NSE_BIT2_SHIFT)) & TRDC_MBC4_MRC_DOM1_RGD_NSE_BIT2_MASK) + +#define TRDC_MBC4_MRC_DOM1_RGD_NSE_BIT3_MASK (0x8U) +#define TRDC_MBC4_MRC_DOM1_RGD_NSE_BIT3_SHIFT (3U) +/*! BIT3 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM1_RGD_NSE_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM1_RGD_NSE_BIT3_SHIFT)) & TRDC_MBC4_MRC_DOM1_RGD_NSE_BIT3_MASK) + +#define TRDC_MBC4_MRC_DOM1_RGD_NSE_BIT4_MASK (0x10U) +#define TRDC_MBC4_MRC_DOM1_RGD_NSE_BIT4_SHIFT (4U) +/*! BIT4 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM1_RGD_NSE_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM1_RGD_NSE_BIT4_SHIFT)) & TRDC_MBC4_MRC_DOM1_RGD_NSE_BIT4_MASK) + +#define TRDC_MBC4_MRC_DOM1_RGD_NSE_BIT5_MASK (0x20U) +#define TRDC_MBC4_MRC_DOM1_RGD_NSE_BIT5_SHIFT (5U) +/*! BIT5 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM1_RGD_NSE_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM1_RGD_NSE_BIT5_SHIFT)) & TRDC_MBC4_MRC_DOM1_RGD_NSE_BIT5_MASK) + +#define TRDC_MBC4_MRC_DOM1_RGD_NSE_BIT6_MASK (0x40U) +#define TRDC_MBC4_MRC_DOM1_RGD_NSE_BIT6_SHIFT (6U) +/*! BIT6 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM1_RGD_NSE_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM1_RGD_NSE_BIT6_SHIFT)) & TRDC_MBC4_MRC_DOM1_RGD_NSE_BIT6_MASK) + +#define TRDC_MBC4_MRC_DOM1_RGD_NSE_BIT7_MASK (0x80U) +#define TRDC_MBC4_MRC_DOM1_RGD_NSE_BIT7_SHIFT (7U) +/*! BIT7 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM1_RGD_NSE_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM1_RGD_NSE_BIT7_SHIFT)) & TRDC_MBC4_MRC_DOM1_RGD_NSE_BIT7_MASK) + +#define TRDC_MBC4_MRC_DOM1_RGD_NSE_BIT8_MASK (0x100U) +#define TRDC_MBC4_MRC_DOM1_RGD_NSE_BIT8_SHIFT (8U) +/*! BIT8 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM1_RGD_NSE_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM1_RGD_NSE_BIT8_SHIFT)) & TRDC_MBC4_MRC_DOM1_RGD_NSE_BIT8_MASK) + +#define TRDC_MBC4_MRC_DOM1_RGD_NSE_BIT9_MASK (0x200U) +#define TRDC_MBC4_MRC_DOM1_RGD_NSE_BIT9_SHIFT (9U) +/*! BIT9 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM1_RGD_NSE_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM1_RGD_NSE_BIT9_SHIFT)) & TRDC_MBC4_MRC_DOM1_RGD_NSE_BIT9_MASK) + +#define TRDC_MBC4_MRC_DOM1_RGD_NSE_BIT10_MASK (0x400U) +#define TRDC_MBC4_MRC_DOM1_RGD_NSE_BIT10_SHIFT (10U) +/*! BIT10 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM1_RGD_NSE_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM1_RGD_NSE_BIT10_SHIFT)) & TRDC_MBC4_MRC_DOM1_RGD_NSE_BIT10_MASK) + +#define TRDC_MBC4_MRC_DOM1_RGD_NSE_BIT11_MASK (0x800U) +#define TRDC_MBC4_MRC_DOM1_RGD_NSE_BIT11_SHIFT (11U) +/*! BIT11 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM1_RGD_NSE_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM1_RGD_NSE_BIT11_SHIFT)) & TRDC_MBC4_MRC_DOM1_RGD_NSE_BIT11_MASK) + +#define TRDC_MBC4_MRC_DOM1_RGD_NSE_BIT12_MASK (0x1000U) +#define TRDC_MBC4_MRC_DOM1_RGD_NSE_BIT12_SHIFT (12U) +/*! BIT12 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM1_RGD_NSE_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM1_RGD_NSE_BIT12_SHIFT)) & TRDC_MBC4_MRC_DOM1_RGD_NSE_BIT12_MASK) + +#define TRDC_MBC4_MRC_DOM1_RGD_NSE_BIT13_MASK (0x2000U) +#define TRDC_MBC4_MRC_DOM1_RGD_NSE_BIT13_SHIFT (13U) +/*! BIT13 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM1_RGD_NSE_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM1_RGD_NSE_BIT13_SHIFT)) & TRDC_MBC4_MRC_DOM1_RGD_NSE_BIT13_MASK) + +#define TRDC_MBC4_MRC_DOM1_RGD_NSE_BIT14_MASK (0x4000U) +#define TRDC_MBC4_MRC_DOM1_RGD_NSE_BIT14_SHIFT (14U) +/*! BIT14 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM1_RGD_NSE_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM1_RGD_NSE_BIT14_SHIFT)) & TRDC_MBC4_MRC_DOM1_RGD_NSE_BIT14_MASK) + +#define TRDC_MBC4_MRC_DOM1_RGD_NSE_BIT15_MASK (0x8000U) +#define TRDC_MBC4_MRC_DOM1_RGD_NSE_BIT15_SHIFT (15U) +/*! BIT15 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM1_RGD_NSE_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM1_RGD_NSE_BIT15_SHIFT)) & TRDC_MBC4_MRC_DOM1_RGD_NSE_BIT15_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MRC_DOM1_RGD_NSE */ +#define TRDC_MBC4_MRC_DOM1_RGD_NSE_COUNT (1U) + +/*! @name MRC_DOM2_RGD_W - MRC Region Descriptor Word 0..MRC Region Descriptor Word 1 */ +/*! @{ */ + +#define TRDC_MBC4_MRC_DOM2_RGD_W_MRACSEL_MASK (0x7U) +#define TRDC_MBC4_MRC_DOM2_RGD_W_MRACSEL_SHIFT (0U) +/*! MRACSEL - Memory Region Access Control Select + * 0b000..Select MRC_GLBAC0 access control policy + * 0b001..Select MRC_GLBAC1 access control policy + * 0b010..Select MRC_GLBAC2 access control policy + * 0b011..Select MRC_GLBAC3 access control policy + * 0b100..Select MRC_GLBAC4 access control policy + * 0b101..Select MRC_GLBAC5 access control policy + * 0b110..Select MRC_GLBAC6 access control policy + * 0b111..Select MRC_GLBAC7 access control policy + */ +#define TRDC_MBC4_MRC_DOM2_RGD_W_MRACSEL(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM2_RGD_W_MRACSEL_SHIFT)) & TRDC_MBC4_MRC_DOM2_RGD_W_MRACSEL_MASK) + +#define TRDC_MBC4_MRC_DOM2_RGD_W_VLD_MASK (0x1U) +#define TRDC_MBC4_MRC_DOM2_RGD_W_VLD_SHIFT (0U) +/*! VLD - Valid */ +#define TRDC_MBC4_MRC_DOM2_RGD_W_VLD(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM2_RGD_W_VLD_SHIFT)) & TRDC_MBC4_MRC_DOM2_RGD_W_VLD_MASK) + +#define TRDC_MBC4_MRC_DOM2_RGD_W_NSE_MASK (0x10U) +#define TRDC_MBC4_MRC_DOM2_RGD_W_NSE_SHIFT (4U) +/*! NSE - NonSecure Enable + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in this register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM2_RGD_W_NSE(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM2_RGD_W_NSE_SHIFT)) & TRDC_MBC4_MRC_DOM2_RGD_W_NSE_MASK) + +#define TRDC_MBC4_MRC_DOM2_RGD_W_END_ADDR_MASK (0xFFFFC000U) +#define TRDC_MBC4_MRC_DOM2_RGD_W_END_ADDR_SHIFT (14U) +/*! END_ADDR - End Address */ +#define TRDC_MBC4_MRC_DOM2_RGD_W_END_ADDR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM2_RGD_W_END_ADDR_SHIFT)) & TRDC_MBC4_MRC_DOM2_RGD_W_END_ADDR_MASK) + +#define TRDC_MBC4_MRC_DOM2_RGD_W_STRT_ADDR_MASK (0xFFFFC000U) +#define TRDC_MBC4_MRC_DOM2_RGD_W_STRT_ADDR_SHIFT (14U) +/*! STRT_ADDR - Start Address */ +#define TRDC_MBC4_MRC_DOM2_RGD_W_STRT_ADDR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM2_RGD_W_STRT_ADDR_SHIFT)) & TRDC_MBC4_MRC_DOM2_RGD_W_STRT_ADDR_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MRC_DOM2_RGD_W */ +#define TRDC_MBC4_MRC_DOM2_RGD_W_COUNT (1U) + +/* The count of TRDC_MBC4_MRC_DOM2_RGD_W */ +#define TRDC_MBC4_MRC_DOM2_RGD_W_COUNT2 (16U) + +/* The count of TRDC_MBC4_MRC_DOM2_RGD_W */ +#define TRDC_MBC4_MRC_DOM2_RGD_W_COUNT3 (2U) + +/*! @name MRC_DOM2_RGD_NSE - MRC Region Descriptor NonSecure Enable */ +/*! @{ */ + +#define TRDC_MBC4_MRC_DOM2_RGD_NSE_BIT0_MASK (0x1U) +#define TRDC_MBC4_MRC_DOM2_RGD_NSE_BIT0_SHIFT (0U) +/*! BIT0 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM2_RGD_NSE_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM2_RGD_NSE_BIT0_SHIFT)) & TRDC_MBC4_MRC_DOM2_RGD_NSE_BIT0_MASK) + +#define TRDC_MBC4_MRC_DOM2_RGD_NSE_BIT1_MASK (0x2U) +#define TRDC_MBC4_MRC_DOM2_RGD_NSE_BIT1_SHIFT (1U) +/*! BIT1 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM2_RGD_NSE_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM2_RGD_NSE_BIT1_SHIFT)) & TRDC_MBC4_MRC_DOM2_RGD_NSE_BIT1_MASK) + +#define TRDC_MBC4_MRC_DOM2_RGD_NSE_BIT2_MASK (0x4U) +#define TRDC_MBC4_MRC_DOM2_RGD_NSE_BIT2_SHIFT (2U) +/*! BIT2 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM2_RGD_NSE_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM2_RGD_NSE_BIT2_SHIFT)) & TRDC_MBC4_MRC_DOM2_RGD_NSE_BIT2_MASK) + +#define TRDC_MBC4_MRC_DOM2_RGD_NSE_BIT3_MASK (0x8U) +#define TRDC_MBC4_MRC_DOM2_RGD_NSE_BIT3_SHIFT (3U) +/*! BIT3 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM2_RGD_NSE_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM2_RGD_NSE_BIT3_SHIFT)) & TRDC_MBC4_MRC_DOM2_RGD_NSE_BIT3_MASK) + +#define TRDC_MBC4_MRC_DOM2_RGD_NSE_BIT4_MASK (0x10U) +#define TRDC_MBC4_MRC_DOM2_RGD_NSE_BIT4_SHIFT (4U) +/*! BIT4 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM2_RGD_NSE_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM2_RGD_NSE_BIT4_SHIFT)) & TRDC_MBC4_MRC_DOM2_RGD_NSE_BIT4_MASK) + +#define TRDC_MBC4_MRC_DOM2_RGD_NSE_BIT5_MASK (0x20U) +#define TRDC_MBC4_MRC_DOM2_RGD_NSE_BIT5_SHIFT (5U) +/*! BIT5 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM2_RGD_NSE_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM2_RGD_NSE_BIT5_SHIFT)) & TRDC_MBC4_MRC_DOM2_RGD_NSE_BIT5_MASK) + +#define TRDC_MBC4_MRC_DOM2_RGD_NSE_BIT6_MASK (0x40U) +#define TRDC_MBC4_MRC_DOM2_RGD_NSE_BIT6_SHIFT (6U) +/*! BIT6 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM2_RGD_NSE_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM2_RGD_NSE_BIT6_SHIFT)) & TRDC_MBC4_MRC_DOM2_RGD_NSE_BIT6_MASK) + +#define TRDC_MBC4_MRC_DOM2_RGD_NSE_BIT7_MASK (0x80U) +#define TRDC_MBC4_MRC_DOM2_RGD_NSE_BIT7_SHIFT (7U) +/*! BIT7 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM2_RGD_NSE_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM2_RGD_NSE_BIT7_SHIFT)) & TRDC_MBC4_MRC_DOM2_RGD_NSE_BIT7_MASK) + +#define TRDC_MBC4_MRC_DOM2_RGD_NSE_BIT8_MASK (0x100U) +#define TRDC_MBC4_MRC_DOM2_RGD_NSE_BIT8_SHIFT (8U) +/*! BIT8 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM2_RGD_NSE_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM2_RGD_NSE_BIT8_SHIFT)) & TRDC_MBC4_MRC_DOM2_RGD_NSE_BIT8_MASK) + +#define TRDC_MBC4_MRC_DOM2_RGD_NSE_BIT9_MASK (0x200U) +#define TRDC_MBC4_MRC_DOM2_RGD_NSE_BIT9_SHIFT (9U) +/*! BIT9 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM2_RGD_NSE_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM2_RGD_NSE_BIT9_SHIFT)) & TRDC_MBC4_MRC_DOM2_RGD_NSE_BIT9_MASK) + +#define TRDC_MBC4_MRC_DOM2_RGD_NSE_BIT10_MASK (0x400U) +#define TRDC_MBC4_MRC_DOM2_RGD_NSE_BIT10_SHIFT (10U) +/*! BIT10 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM2_RGD_NSE_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM2_RGD_NSE_BIT10_SHIFT)) & TRDC_MBC4_MRC_DOM2_RGD_NSE_BIT10_MASK) + +#define TRDC_MBC4_MRC_DOM2_RGD_NSE_BIT11_MASK (0x800U) +#define TRDC_MBC4_MRC_DOM2_RGD_NSE_BIT11_SHIFT (11U) +/*! BIT11 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM2_RGD_NSE_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM2_RGD_NSE_BIT11_SHIFT)) & TRDC_MBC4_MRC_DOM2_RGD_NSE_BIT11_MASK) + +#define TRDC_MBC4_MRC_DOM2_RGD_NSE_BIT12_MASK (0x1000U) +#define TRDC_MBC4_MRC_DOM2_RGD_NSE_BIT12_SHIFT (12U) +/*! BIT12 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM2_RGD_NSE_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM2_RGD_NSE_BIT12_SHIFT)) & TRDC_MBC4_MRC_DOM2_RGD_NSE_BIT12_MASK) + +#define TRDC_MBC4_MRC_DOM2_RGD_NSE_BIT13_MASK (0x2000U) +#define TRDC_MBC4_MRC_DOM2_RGD_NSE_BIT13_SHIFT (13U) +/*! BIT13 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM2_RGD_NSE_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM2_RGD_NSE_BIT13_SHIFT)) & TRDC_MBC4_MRC_DOM2_RGD_NSE_BIT13_MASK) + +#define TRDC_MBC4_MRC_DOM2_RGD_NSE_BIT14_MASK (0x4000U) +#define TRDC_MBC4_MRC_DOM2_RGD_NSE_BIT14_SHIFT (14U) +/*! BIT14 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM2_RGD_NSE_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM2_RGD_NSE_BIT14_SHIFT)) & TRDC_MBC4_MRC_DOM2_RGD_NSE_BIT14_MASK) + +#define TRDC_MBC4_MRC_DOM2_RGD_NSE_BIT15_MASK (0x8000U) +#define TRDC_MBC4_MRC_DOM2_RGD_NSE_BIT15_SHIFT (15U) +/*! BIT15 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM2_RGD_NSE_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM2_RGD_NSE_BIT15_SHIFT)) & TRDC_MBC4_MRC_DOM2_RGD_NSE_BIT15_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MRC_DOM2_RGD_NSE */ +#define TRDC_MBC4_MRC_DOM2_RGD_NSE_COUNT (1U) + +/*! @name MRC_DOM3_RGD_W - MRC Region Descriptor Word 0..MRC Region Descriptor Word 1 */ +/*! @{ */ + +#define TRDC_MBC4_MRC_DOM3_RGD_W_MRACSEL_MASK (0x7U) +#define TRDC_MBC4_MRC_DOM3_RGD_W_MRACSEL_SHIFT (0U) +/*! MRACSEL - Memory Region Access Control Select + * 0b000..Select MRC_GLBAC0 access control policy + * 0b001..Select MRC_GLBAC1 access control policy + * 0b010..Select MRC_GLBAC2 access control policy + * 0b011..Select MRC_GLBAC3 access control policy + * 0b100..Select MRC_GLBAC4 access control policy + * 0b101..Select MRC_GLBAC5 access control policy + * 0b110..Select MRC_GLBAC6 access control policy + * 0b111..Select MRC_GLBAC7 access control policy + */ +#define TRDC_MBC4_MRC_DOM3_RGD_W_MRACSEL(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM3_RGD_W_MRACSEL_SHIFT)) & TRDC_MBC4_MRC_DOM3_RGD_W_MRACSEL_MASK) + +#define TRDC_MBC4_MRC_DOM3_RGD_W_VLD_MASK (0x1U) +#define TRDC_MBC4_MRC_DOM3_RGD_W_VLD_SHIFT (0U) +/*! VLD - Valid */ +#define TRDC_MBC4_MRC_DOM3_RGD_W_VLD(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM3_RGD_W_VLD_SHIFT)) & TRDC_MBC4_MRC_DOM3_RGD_W_VLD_MASK) + +#define TRDC_MBC4_MRC_DOM3_RGD_W_NSE_MASK (0x10U) +#define TRDC_MBC4_MRC_DOM3_RGD_W_NSE_SHIFT (4U) +/*! NSE - NonSecure Enable + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in this register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM3_RGD_W_NSE(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM3_RGD_W_NSE_SHIFT)) & TRDC_MBC4_MRC_DOM3_RGD_W_NSE_MASK) + +#define TRDC_MBC4_MRC_DOM3_RGD_W_END_ADDR_MASK (0xFFFFC000U) +#define TRDC_MBC4_MRC_DOM3_RGD_W_END_ADDR_SHIFT (14U) +/*! END_ADDR - End Address */ +#define TRDC_MBC4_MRC_DOM3_RGD_W_END_ADDR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM3_RGD_W_END_ADDR_SHIFT)) & TRDC_MBC4_MRC_DOM3_RGD_W_END_ADDR_MASK) + +#define TRDC_MBC4_MRC_DOM3_RGD_W_STRT_ADDR_MASK (0xFFFFC000U) +#define TRDC_MBC4_MRC_DOM3_RGD_W_STRT_ADDR_SHIFT (14U) +/*! STRT_ADDR - Start Address */ +#define TRDC_MBC4_MRC_DOM3_RGD_W_STRT_ADDR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM3_RGD_W_STRT_ADDR_SHIFT)) & TRDC_MBC4_MRC_DOM3_RGD_W_STRT_ADDR_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MRC_DOM3_RGD_W */ +#define TRDC_MBC4_MRC_DOM3_RGD_W_COUNT (1U) + +/* The count of TRDC_MBC4_MRC_DOM3_RGD_W */ +#define TRDC_MBC4_MRC_DOM3_RGD_W_COUNT2 (16U) + +/* The count of TRDC_MBC4_MRC_DOM3_RGD_W */ +#define TRDC_MBC4_MRC_DOM3_RGD_W_COUNT3 (2U) + +/*! @name MRC_DOM3_RGD_NSE - MRC Region Descriptor NonSecure Enable */ +/*! @{ */ + +#define TRDC_MBC4_MRC_DOM3_RGD_NSE_BIT0_MASK (0x1U) +#define TRDC_MBC4_MRC_DOM3_RGD_NSE_BIT0_SHIFT (0U) +/*! BIT0 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM3_RGD_NSE_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM3_RGD_NSE_BIT0_SHIFT)) & TRDC_MBC4_MRC_DOM3_RGD_NSE_BIT0_MASK) + +#define TRDC_MBC4_MRC_DOM3_RGD_NSE_BIT1_MASK (0x2U) +#define TRDC_MBC4_MRC_DOM3_RGD_NSE_BIT1_SHIFT (1U) +/*! BIT1 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM3_RGD_NSE_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM3_RGD_NSE_BIT1_SHIFT)) & TRDC_MBC4_MRC_DOM3_RGD_NSE_BIT1_MASK) + +#define TRDC_MBC4_MRC_DOM3_RGD_NSE_BIT2_MASK (0x4U) +#define TRDC_MBC4_MRC_DOM3_RGD_NSE_BIT2_SHIFT (2U) +/*! BIT2 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM3_RGD_NSE_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM3_RGD_NSE_BIT2_SHIFT)) & TRDC_MBC4_MRC_DOM3_RGD_NSE_BIT2_MASK) + +#define TRDC_MBC4_MRC_DOM3_RGD_NSE_BIT3_MASK (0x8U) +#define TRDC_MBC4_MRC_DOM3_RGD_NSE_BIT3_SHIFT (3U) +/*! BIT3 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM3_RGD_NSE_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM3_RGD_NSE_BIT3_SHIFT)) & TRDC_MBC4_MRC_DOM3_RGD_NSE_BIT3_MASK) + +#define TRDC_MBC4_MRC_DOM3_RGD_NSE_BIT4_MASK (0x10U) +#define TRDC_MBC4_MRC_DOM3_RGD_NSE_BIT4_SHIFT (4U) +/*! BIT4 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM3_RGD_NSE_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM3_RGD_NSE_BIT4_SHIFT)) & TRDC_MBC4_MRC_DOM3_RGD_NSE_BIT4_MASK) + +#define TRDC_MBC4_MRC_DOM3_RGD_NSE_BIT5_MASK (0x20U) +#define TRDC_MBC4_MRC_DOM3_RGD_NSE_BIT5_SHIFT (5U) +/*! BIT5 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM3_RGD_NSE_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM3_RGD_NSE_BIT5_SHIFT)) & TRDC_MBC4_MRC_DOM3_RGD_NSE_BIT5_MASK) + +#define TRDC_MBC4_MRC_DOM3_RGD_NSE_BIT6_MASK (0x40U) +#define TRDC_MBC4_MRC_DOM3_RGD_NSE_BIT6_SHIFT (6U) +/*! BIT6 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM3_RGD_NSE_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM3_RGD_NSE_BIT6_SHIFT)) & TRDC_MBC4_MRC_DOM3_RGD_NSE_BIT6_MASK) + +#define TRDC_MBC4_MRC_DOM3_RGD_NSE_BIT7_MASK (0x80U) +#define TRDC_MBC4_MRC_DOM3_RGD_NSE_BIT7_SHIFT (7U) +/*! BIT7 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM3_RGD_NSE_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM3_RGD_NSE_BIT7_SHIFT)) & TRDC_MBC4_MRC_DOM3_RGD_NSE_BIT7_MASK) + +#define TRDC_MBC4_MRC_DOM3_RGD_NSE_BIT8_MASK (0x100U) +#define TRDC_MBC4_MRC_DOM3_RGD_NSE_BIT8_SHIFT (8U) +/*! BIT8 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM3_RGD_NSE_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM3_RGD_NSE_BIT8_SHIFT)) & TRDC_MBC4_MRC_DOM3_RGD_NSE_BIT8_MASK) + +#define TRDC_MBC4_MRC_DOM3_RGD_NSE_BIT9_MASK (0x200U) +#define TRDC_MBC4_MRC_DOM3_RGD_NSE_BIT9_SHIFT (9U) +/*! BIT9 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM3_RGD_NSE_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM3_RGD_NSE_BIT9_SHIFT)) & TRDC_MBC4_MRC_DOM3_RGD_NSE_BIT9_MASK) + +#define TRDC_MBC4_MRC_DOM3_RGD_NSE_BIT10_MASK (0x400U) +#define TRDC_MBC4_MRC_DOM3_RGD_NSE_BIT10_SHIFT (10U) +/*! BIT10 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM3_RGD_NSE_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM3_RGD_NSE_BIT10_SHIFT)) & TRDC_MBC4_MRC_DOM3_RGD_NSE_BIT10_MASK) + +#define TRDC_MBC4_MRC_DOM3_RGD_NSE_BIT11_MASK (0x800U) +#define TRDC_MBC4_MRC_DOM3_RGD_NSE_BIT11_SHIFT (11U) +/*! BIT11 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM3_RGD_NSE_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM3_RGD_NSE_BIT11_SHIFT)) & TRDC_MBC4_MRC_DOM3_RGD_NSE_BIT11_MASK) + +#define TRDC_MBC4_MRC_DOM3_RGD_NSE_BIT12_MASK (0x1000U) +#define TRDC_MBC4_MRC_DOM3_RGD_NSE_BIT12_SHIFT (12U) +/*! BIT12 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM3_RGD_NSE_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM3_RGD_NSE_BIT12_SHIFT)) & TRDC_MBC4_MRC_DOM3_RGD_NSE_BIT12_MASK) + +#define TRDC_MBC4_MRC_DOM3_RGD_NSE_BIT13_MASK (0x2000U) +#define TRDC_MBC4_MRC_DOM3_RGD_NSE_BIT13_SHIFT (13U) +/*! BIT13 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM3_RGD_NSE_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM3_RGD_NSE_BIT13_SHIFT)) & TRDC_MBC4_MRC_DOM3_RGD_NSE_BIT13_MASK) + +#define TRDC_MBC4_MRC_DOM3_RGD_NSE_BIT14_MASK (0x4000U) +#define TRDC_MBC4_MRC_DOM3_RGD_NSE_BIT14_SHIFT (14U) +/*! BIT14 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM3_RGD_NSE_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM3_RGD_NSE_BIT14_SHIFT)) & TRDC_MBC4_MRC_DOM3_RGD_NSE_BIT14_MASK) + +#define TRDC_MBC4_MRC_DOM3_RGD_NSE_BIT15_MASK (0x8000U) +#define TRDC_MBC4_MRC_DOM3_RGD_NSE_BIT15_SHIFT (15U) +/*! BIT15 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM3_RGD_NSE_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM3_RGD_NSE_BIT15_SHIFT)) & TRDC_MBC4_MRC_DOM3_RGD_NSE_BIT15_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MRC_DOM3_RGD_NSE */ +#define TRDC_MBC4_MRC_DOM3_RGD_NSE_COUNT (1U) + +/*! @name MRC_DOM4_RGD_W - MRC Region Descriptor Word 0..MRC Region Descriptor Word 1 */ +/*! @{ */ + +#define TRDC_MBC4_MRC_DOM4_RGD_W_MRACSEL_MASK (0x7U) +#define TRDC_MBC4_MRC_DOM4_RGD_W_MRACSEL_SHIFT (0U) +/*! MRACSEL - Memory Region Access Control Select + * 0b000..Select MRC_GLBAC0 access control policy + * 0b001..Select MRC_GLBAC1 access control policy + * 0b010..Select MRC_GLBAC2 access control policy + * 0b011..Select MRC_GLBAC3 access control policy + * 0b100..Select MRC_GLBAC4 access control policy + * 0b101..Select MRC_GLBAC5 access control policy + * 0b110..Select MRC_GLBAC6 access control policy + * 0b111..Select MRC_GLBAC7 access control policy + */ +#define TRDC_MBC4_MRC_DOM4_RGD_W_MRACSEL(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM4_RGD_W_MRACSEL_SHIFT)) & TRDC_MBC4_MRC_DOM4_RGD_W_MRACSEL_MASK) + +#define TRDC_MBC4_MRC_DOM4_RGD_W_VLD_MASK (0x1U) +#define TRDC_MBC4_MRC_DOM4_RGD_W_VLD_SHIFT (0U) +/*! VLD - Valid */ +#define TRDC_MBC4_MRC_DOM4_RGD_W_VLD(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM4_RGD_W_VLD_SHIFT)) & TRDC_MBC4_MRC_DOM4_RGD_W_VLD_MASK) + +#define TRDC_MBC4_MRC_DOM4_RGD_W_NSE_MASK (0x10U) +#define TRDC_MBC4_MRC_DOM4_RGD_W_NSE_SHIFT (4U) +/*! NSE - NonSecure Enable + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in this register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM4_RGD_W_NSE(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM4_RGD_W_NSE_SHIFT)) & TRDC_MBC4_MRC_DOM4_RGD_W_NSE_MASK) + +#define TRDC_MBC4_MRC_DOM4_RGD_W_END_ADDR_MASK (0xFFFFC000U) +#define TRDC_MBC4_MRC_DOM4_RGD_W_END_ADDR_SHIFT (14U) +/*! END_ADDR - End Address */ +#define TRDC_MBC4_MRC_DOM4_RGD_W_END_ADDR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM4_RGD_W_END_ADDR_SHIFT)) & TRDC_MBC4_MRC_DOM4_RGD_W_END_ADDR_MASK) + +#define TRDC_MBC4_MRC_DOM4_RGD_W_STRT_ADDR_MASK (0xFFFFC000U) +#define TRDC_MBC4_MRC_DOM4_RGD_W_STRT_ADDR_SHIFT (14U) +/*! STRT_ADDR - Start Address */ +#define TRDC_MBC4_MRC_DOM4_RGD_W_STRT_ADDR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM4_RGD_W_STRT_ADDR_SHIFT)) & TRDC_MBC4_MRC_DOM4_RGD_W_STRT_ADDR_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MRC_DOM4_RGD_W */ +#define TRDC_MBC4_MRC_DOM4_RGD_W_COUNT (1U) + +/* The count of TRDC_MBC4_MRC_DOM4_RGD_W */ +#define TRDC_MBC4_MRC_DOM4_RGD_W_COUNT2 (16U) + +/* The count of TRDC_MBC4_MRC_DOM4_RGD_W */ +#define TRDC_MBC4_MRC_DOM4_RGD_W_COUNT3 (2U) + +/*! @name MRC_DOM4_RGD_NSE - MRC Region Descriptor NonSecure Enable */ +/*! @{ */ + +#define TRDC_MBC4_MRC_DOM4_RGD_NSE_BIT0_MASK (0x1U) +#define TRDC_MBC4_MRC_DOM4_RGD_NSE_BIT0_SHIFT (0U) +/*! BIT0 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM4_RGD_NSE_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM4_RGD_NSE_BIT0_SHIFT)) & TRDC_MBC4_MRC_DOM4_RGD_NSE_BIT0_MASK) + +#define TRDC_MBC4_MRC_DOM4_RGD_NSE_BIT1_MASK (0x2U) +#define TRDC_MBC4_MRC_DOM4_RGD_NSE_BIT1_SHIFT (1U) +/*! BIT1 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM4_RGD_NSE_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM4_RGD_NSE_BIT1_SHIFT)) & TRDC_MBC4_MRC_DOM4_RGD_NSE_BIT1_MASK) + +#define TRDC_MBC4_MRC_DOM4_RGD_NSE_BIT2_MASK (0x4U) +#define TRDC_MBC4_MRC_DOM4_RGD_NSE_BIT2_SHIFT (2U) +/*! BIT2 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM4_RGD_NSE_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM4_RGD_NSE_BIT2_SHIFT)) & TRDC_MBC4_MRC_DOM4_RGD_NSE_BIT2_MASK) + +#define TRDC_MBC4_MRC_DOM4_RGD_NSE_BIT3_MASK (0x8U) +#define TRDC_MBC4_MRC_DOM4_RGD_NSE_BIT3_SHIFT (3U) +/*! BIT3 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM4_RGD_NSE_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM4_RGD_NSE_BIT3_SHIFT)) & TRDC_MBC4_MRC_DOM4_RGD_NSE_BIT3_MASK) + +#define TRDC_MBC4_MRC_DOM4_RGD_NSE_BIT4_MASK (0x10U) +#define TRDC_MBC4_MRC_DOM4_RGD_NSE_BIT4_SHIFT (4U) +/*! BIT4 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM4_RGD_NSE_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM4_RGD_NSE_BIT4_SHIFT)) & TRDC_MBC4_MRC_DOM4_RGD_NSE_BIT4_MASK) + +#define TRDC_MBC4_MRC_DOM4_RGD_NSE_BIT5_MASK (0x20U) +#define TRDC_MBC4_MRC_DOM4_RGD_NSE_BIT5_SHIFT (5U) +/*! BIT5 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM4_RGD_NSE_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM4_RGD_NSE_BIT5_SHIFT)) & TRDC_MBC4_MRC_DOM4_RGD_NSE_BIT5_MASK) + +#define TRDC_MBC4_MRC_DOM4_RGD_NSE_BIT6_MASK (0x40U) +#define TRDC_MBC4_MRC_DOM4_RGD_NSE_BIT6_SHIFT (6U) +/*! BIT6 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM4_RGD_NSE_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM4_RGD_NSE_BIT6_SHIFT)) & TRDC_MBC4_MRC_DOM4_RGD_NSE_BIT6_MASK) + +#define TRDC_MBC4_MRC_DOM4_RGD_NSE_BIT7_MASK (0x80U) +#define TRDC_MBC4_MRC_DOM4_RGD_NSE_BIT7_SHIFT (7U) +/*! BIT7 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM4_RGD_NSE_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM4_RGD_NSE_BIT7_SHIFT)) & TRDC_MBC4_MRC_DOM4_RGD_NSE_BIT7_MASK) + +#define TRDC_MBC4_MRC_DOM4_RGD_NSE_BIT8_MASK (0x100U) +#define TRDC_MBC4_MRC_DOM4_RGD_NSE_BIT8_SHIFT (8U) +/*! BIT8 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM4_RGD_NSE_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM4_RGD_NSE_BIT8_SHIFT)) & TRDC_MBC4_MRC_DOM4_RGD_NSE_BIT8_MASK) + +#define TRDC_MBC4_MRC_DOM4_RGD_NSE_BIT9_MASK (0x200U) +#define TRDC_MBC4_MRC_DOM4_RGD_NSE_BIT9_SHIFT (9U) +/*! BIT9 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM4_RGD_NSE_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM4_RGD_NSE_BIT9_SHIFT)) & TRDC_MBC4_MRC_DOM4_RGD_NSE_BIT9_MASK) + +#define TRDC_MBC4_MRC_DOM4_RGD_NSE_BIT10_MASK (0x400U) +#define TRDC_MBC4_MRC_DOM4_RGD_NSE_BIT10_SHIFT (10U) +/*! BIT10 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM4_RGD_NSE_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM4_RGD_NSE_BIT10_SHIFT)) & TRDC_MBC4_MRC_DOM4_RGD_NSE_BIT10_MASK) + +#define TRDC_MBC4_MRC_DOM4_RGD_NSE_BIT11_MASK (0x800U) +#define TRDC_MBC4_MRC_DOM4_RGD_NSE_BIT11_SHIFT (11U) +/*! BIT11 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM4_RGD_NSE_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM4_RGD_NSE_BIT11_SHIFT)) & TRDC_MBC4_MRC_DOM4_RGD_NSE_BIT11_MASK) + +#define TRDC_MBC4_MRC_DOM4_RGD_NSE_BIT12_MASK (0x1000U) +#define TRDC_MBC4_MRC_DOM4_RGD_NSE_BIT12_SHIFT (12U) +/*! BIT12 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM4_RGD_NSE_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM4_RGD_NSE_BIT12_SHIFT)) & TRDC_MBC4_MRC_DOM4_RGD_NSE_BIT12_MASK) + +#define TRDC_MBC4_MRC_DOM4_RGD_NSE_BIT13_MASK (0x2000U) +#define TRDC_MBC4_MRC_DOM4_RGD_NSE_BIT13_SHIFT (13U) +/*! BIT13 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM4_RGD_NSE_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM4_RGD_NSE_BIT13_SHIFT)) & TRDC_MBC4_MRC_DOM4_RGD_NSE_BIT13_MASK) + +#define TRDC_MBC4_MRC_DOM4_RGD_NSE_BIT14_MASK (0x4000U) +#define TRDC_MBC4_MRC_DOM4_RGD_NSE_BIT14_SHIFT (14U) +/*! BIT14 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM4_RGD_NSE_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM4_RGD_NSE_BIT14_SHIFT)) & TRDC_MBC4_MRC_DOM4_RGD_NSE_BIT14_MASK) + +#define TRDC_MBC4_MRC_DOM4_RGD_NSE_BIT15_MASK (0x8000U) +#define TRDC_MBC4_MRC_DOM4_RGD_NSE_BIT15_SHIFT (15U) +/*! BIT15 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM4_RGD_NSE_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM4_RGD_NSE_BIT15_SHIFT)) & TRDC_MBC4_MRC_DOM4_RGD_NSE_BIT15_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MRC_DOM4_RGD_NSE */ +#define TRDC_MBC4_MRC_DOM4_RGD_NSE_COUNT (1U) + +/*! @name MRC_DOM5_RGD_W - MRC Region Descriptor Word 0..MRC Region Descriptor Word 1 */ +/*! @{ */ + +#define TRDC_MBC4_MRC_DOM5_RGD_W_MRACSEL_MASK (0x7U) +#define TRDC_MBC4_MRC_DOM5_RGD_W_MRACSEL_SHIFT (0U) +/*! MRACSEL - Memory Region Access Control Select + * 0b000..Select MRC_GLBAC0 access control policy + * 0b001..Select MRC_GLBAC1 access control policy + * 0b010..Select MRC_GLBAC2 access control policy + * 0b011..Select MRC_GLBAC3 access control policy + * 0b100..Select MRC_GLBAC4 access control policy + * 0b101..Select MRC_GLBAC5 access control policy + * 0b110..Select MRC_GLBAC6 access control policy + * 0b111..Select MRC_GLBAC7 access control policy + */ +#define TRDC_MBC4_MRC_DOM5_RGD_W_MRACSEL(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM5_RGD_W_MRACSEL_SHIFT)) & TRDC_MBC4_MRC_DOM5_RGD_W_MRACSEL_MASK) + +#define TRDC_MBC4_MRC_DOM5_RGD_W_VLD_MASK (0x1U) +#define TRDC_MBC4_MRC_DOM5_RGD_W_VLD_SHIFT (0U) +/*! VLD - Valid */ +#define TRDC_MBC4_MRC_DOM5_RGD_W_VLD(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM5_RGD_W_VLD_SHIFT)) & TRDC_MBC4_MRC_DOM5_RGD_W_VLD_MASK) + +#define TRDC_MBC4_MRC_DOM5_RGD_W_NSE_MASK (0x10U) +#define TRDC_MBC4_MRC_DOM5_RGD_W_NSE_SHIFT (4U) +/*! NSE - NonSecure Enable + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in this register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM5_RGD_W_NSE(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM5_RGD_W_NSE_SHIFT)) & TRDC_MBC4_MRC_DOM5_RGD_W_NSE_MASK) + +#define TRDC_MBC4_MRC_DOM5_RGD_W_END_ADDR_MASK (0xFFFFC000U) +#define TRDC_MBC4_MRC_DOM5_RGD_W_END_ADDR_SHIFT (14U) +/*! END_ADDR - End Address */ +#define TRDC_MBC4_MRC_DOM5_RGD_W_END_ADDR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM5_RGD_W_END_ADDR_SHIFT)) & TRDC_MBC4_MRC_DOM5_RGD_W_END_ADDR_MASK) + +#define TRDC_MBC4_MRC_DOM5_RGD_W_STRT_ADDR_MASK (0xFFFFC000U) +#define TRDC_MBC4_MRC_DOM5_RGD_W_STRT_ADDR_SHIFT (14U) +/*! STRT_ADDR - Start Address */ +#define TRDC_MBC4_MRC_DOM5_RGD_W_STRT_ADDR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM5_RGD_W_STRT_ADDR_SHIFT)) & TRDC_MBC4_MRC_DOM5_RGD_W_STRT_ADDR_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MRC_DOM5_RGD_W */ +#define TRDC_MBC4_MRC_DOM5_RGD_W_COUNT (1U) + +/* The count of TRDC_MBC4_MRC_DOM5_RGD_W */ +#define TRDC_MBC4_MRC_DOM5_RGD_W_COUNT2 (16U) + +/* The count of TRDC_MBC4_MRC_DOM5_RGD_W */ +#define TRDC_MBC4_MRC_DOM5_RGD_W_COUNT3 (2U) + +/*! @name MRC_DOM5_RGD_NSE - MRC Region Descriptor NonSecure Enable */ +/*! @{ */ + +#define TRDC_MBC4_MRC_DOM5_RGD_NSE_BIT0_MASK (0x1U) +#define TRDC_MBC4_MRC_DOM5_RGD_NSE_BIT0_SHIFT (0U) +/*! BIT0 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM5_RGD_NSE_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM5_RGD_NSE_BIT0_SHIFT)) & TRDC_MBC4_MRC_DOM5_RGD_NSE_BIT0_MASK) + +#define TRDC_MBC4_MRC_DOM5_RGD_NSE_BIT1_MASK (0x2U) +#define TRDC_MBC4_MRC_DOM5_RGD_NSE_BIT1_SHIFT (1U) +/*! BIT1 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM5_RGD_NSE_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM5_RGD_NSE_BIT1_SHIFT)) & TRDC_MBC4_MRC_DOM5_RGD_NSE_BIT1_MASK) + +#define TRDC_MBC4_MRC_DOM5_RGD_NSE_BIT2_MASK (0x4U) +#define TRDC_MBC4_MRC_DOM5_RGD_NSE_BIT2_SHIFT (2U) +/*! BIT2 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM5_RGD_NSE_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM5_RGD_NSE_BIT2_SHIFT)) & TRDC_MBC4_MRC_DOM5_RGD_NSE_BIT2_MASK) + +#define TRDC_MBC4_MRC_DOM5_RGD_NSE_BIT3_MASK (0x8U) +#define TRDC_MBC4_MRC_DOM5_RGD_NSE_BIT3_SHIFT (3U) +/*! BIT3 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM5_RGD_NSE_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM5_RGD_NSE_BIT3_SHIFT)) & TRDC_MBC4_MRC_DOM5_RGD_NSE_BIT3_MASK) + +#define TRDC_MBC4_MRC_DOM5_RGD_NSE_BIT4_MASK (0x10U) +#define TRDC_MBC4_MRC_DOM5_RGD_NSE_BIT4_SHIFT (4U) +/*! BIT4 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM5_RGD_NSE_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM5_RGD_NSE_BIT4_SHIFT)) & TRDC_MBC4_MRC_DOM5_RGD_NSE_BIT4_MASK) + +#define TRDC_MBC4_MRC_DOM5_RGD_NSE_BIT5_MASK (0x20U) +#define TRDC_MBC4_MRC_DOM5_RGD_NSE_BIT5_SHIFT (5U) +/*! BIT5 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM5_RGD_NSE_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM5_RGD_NSE_BIT5_SHIFT)) & TRDC_MBC4_MRC_DOM5_RGD_NSE_BIT5_MASK) + +#define TRDC_MBC4_MRC_DOM5_RGD_NSE_BIT6_MASK (0x40U) +#define TRDC_MBC4_MRC_DOM5_RGD_NSE_BIT6_SHIFT (6U) +/*! BIT6 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM5_RGD_NSE_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM5_RGD_NSE_BIT6_SHIFT)) & TRDC_MBC4_MRC_DOM5_RGD_NSE_BIT6_MASK) + +#define TRDC_MBC4_MRC_DOM5_RGD_NSE_BIT7_MASK (0x80U) +#define TRDC_MBC4_MRC_DOM5_RGD_NSE_BIT7_SHIFT (7U) +/*! BIT7 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM5_RGD_NSE_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM5_RGD_NSE_BIT7_SHIFT)) & TRDC_MBC4_MRC_DOM5_RGD_NSE_BIT7_MASK) + +#define TRDC_MBC4_MRC_DOM5_RGD_NSE_BIT8_MASK (0x100U) +#define TRDC_MBC4_MRC_DOM5_RGD_NSE_BIT8_SHIFT (8U) +/*! BIT8 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM5_RGD_NSE_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM5_RGD_NSE_BIT8_SHIFT)) & TRDC_MBC4_MRC_DOM5_RGD_NSE_BIT8_MASK) + +#define TRDC_MBC4_MRC_DOM5_RGD_NSE_BIT9_MASK (0x200U) +#define TRDC_MBC4_MRC_DOM5_RGD_NSE_BIT9_SHIFT (9U) +/*! BIT9 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM5_RGD_NSE_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM5_RGD_NSE_BIT9_SHIFT)) & TRDC_MBC4_MRC_DOM5_RGD_NSE_BIT9_MASK) + +#define TRDC_MBC4_MRC_DOM5_RGD_NSE_BIT10_MASK (0x400U) +#define TRDC_MBC4_MRC_DOM5_RGD_NSE_BIT10_SHIFT (10U) +/*! BIT10 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM5_RGD_NSE_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM5_RGD_NSE_BIT10_SHIFT)) & TRDC_MBC4_MRC_DOM5_RGD_NSE_BIT10_MASK) + +#define TRDC_MBC4_MRC_DOM5_RGD_NSE_BIT11_MASK (0x800U) +#define TRDC_MBC4_MRC_DOM5_RGD_NSE_BIT11_SHIFT (11U) +/*! BIT11 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM5_RGD_NSE_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM5_RGD_NSE_BIT11_SHIFT)) & TRDC_MBC4_MRC_DOM5_RGD_NSE_BIT11_MASK) + +#define TRDC_MBC4_MRC_DOM5_RGD_NSE_BIT12_MASK (0x1000U) +#define TRDC_MBC4_MRC_DOM5_RGD_NSE_BIT12_SHIFT (12U) +/*! BIT12 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM5_RGD_NSE_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM5_RGD_NSE_BIT12_SHIFT)) & TRDC_MBC4_MRC_DOM5_RGD_NSE_BIT12_MASK) + +#define TRDC_MBC4_MRC_DOM5_RGD_NSE_BIT13_MASK (0x2000U) +#define TRDC_MBC4_MRC_DOM5_RGD_NSE_BIT13_SHIFT (13U) +/*! BIT13 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM5_RGD_NSE_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM5_RGD_NSE_BIT13_SHIFT)) & TRDC_MBC4_MRC_DOM5_RGD_NSE_BIT13_MASK) + +#define TRDC_MBC4_MRC_DOM5_RGD_NSE_BIT14_MASK (0x4000U) +#define TRDC_MBC4_MRC_DOM5_RGD_NSE_BIT14_SHIFT (14U) +/*! BIT14 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM5_RGD_NSE_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM5_RGD_NSE_BIT14_SHIFT)) & TRDC_MBC4_MRC_DOM5_RGD_NSE_BIT14_MASK) + +#define TRDC_MBC4_MRC_DOM5_RGD_NSE_BIT15_MASK (0x8000U) +#define TRDC_MBC4_MRC_DOM5_RGD_NSE_BIT15_SHIFT (15U) +/*! BIT15 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM5_RGD_NSE_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM5_RGD_NSE_BIT15_SHIFT)) & TRDC_MBC4_MRC_DOM5_RGD_NSE_BIT15_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MRC_DOM5_RGD_NSE */ +#define TRDC_MBC4_MRC_DOM5_RGD_NSE_COUNT (1U) + +/*! @name MRC_DOM6_RGD_W - MRC Region Descriptor Word 0..MRC Region Descriptor Word 1 */ +/*! @{ */ + +#define TRDC_MBC4_MRC_DOM6_RGD_W_MRACSEL_MASK (0x7U) +#define TRDC_MBC4_MRC_DOM6_RGD_W_MRACSEL_SHIFT (0U) +/*! MRACSEL - Memory Region Access Control Select + * 0b000..Select MRC_GLBAC0 access control policy + * 0b001..Select MRC_GLBAC1 access control policy + * 0b010..Select MRC_GLBAC2 access control policy + * 0b011..Select MRC_GLBAC3 access control policy + * 0b100..Select MRC_GLBAC4 access control policy + * 0b101..Select MRC_GLBAC5 access control policy + * 0b110..Select MRC_GLBAC6 access control policy + * 0b111..Select MRC_GLBAC7 access control policy + */ +#define TRDC_MBC4_MRC_DOM6_RGD_W_MRACSEL(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM6_RGD_W_MRACSEL_SHIFT)) & TRDC_MBC4_MRC_DOM6_RGD_W_MRACSEL_MASK) + +#define TRDC_MBC4_MRC_DOM6_RGD_W_VLD_MASK (0x1U) +#define TRDC_MBC4_MRC_DOM6_RGD_W_VLD_SHIFT (0U) +/*! VLD - Valid */ +#define TRDC_MBC4_MRC_DOM6_RGD_W_VLD(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM6_RGD_W_VLD_SHIFT)) & TRDC_MBC4_MRC_DOM6_RGD_W_VLD_MASK) + +#define TRDC_MBC4_MRC_DOM6_RGD_W_NSE_MASK (0x10U) +#define TRDC_MBC4_MRC_DOM6_RGD_W_NSE_SHIFT (4U) +/*! NSE - NonSecure Enable + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in this register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM6_RGD_W_NSE(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM6_RGD_W_NSE_SHIFT)) & TRDC_MBC4_MRC_DOM6_RGD_W_NSE_MASK) + +#define TRDC_MBC4_MRC_DOM6_RGD_W_END_ADDR_MASK (0xFFFFC000U) +#define TRDC_MBC4_MRC_DOM6_RGD_W_END_ADDR_SHIFT (14U) +/*! END_ADDR - End Address */ +#define TRDC_MBC4_MRC_DOM6_RGD_W_END_ADDR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM6_RGD_W_END_ADDR_SHIFT)) & TRDC_MBC4_MRC_DOM6_RGD_W_END_ADDR_MASK) + +#define TRDC_MBC4_MRC_DOM6_RGD_W_STRT_ADDR_MASK (0xFFFFC000U) +#define TRDC_MBC4_MRC_DOM6_RGD_W_STRT_ADDR_SHIFT (14U) +/*! STRT_ADDR - Start Address */ +#define TRDC_MBC4_MRC_DOM6_RGD_W_STRT_ADDR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM6_RGD_W_STRT_ADDR_SHIFT)) & TRDC_MBC4_MRC_DOM6_RGD_W_STRT_ADDR_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MRC_DOM6_RGD_W */ +#define TRDC_MBC4_MRC_DOM6_RGD_W_COUNT (1U) + +/* The count of TRDC_MBC4_MRC_DOM6_RGD_W */ +#define TRDC_MBC4_MRC_DOM6_RGD_W_COUNT2 (16U) + +/* The count of TRDC_MBC4_MRC_DOM6_RGD_W */ +#define TRDC_MBC4_MRC_DOM6_RGD_W_COUNT3 (2U) + +/*! @name MRC_DOM6_RGD_NSE - MRC Region Descriptor NonSecure Enable */ +/*! @{ */ + +#define TRDC_MBC4_MRC_DOM6_RGD_NSE_BIT0_MASK (0x1U) +#define TRDC_MBC4_MRC_DOM6_RGD_NSE_BIT0_SHIFT (0U) +/*! BIT0 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM6_RGD_NSE_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM6_RGD_NSE_BIT0_SHIFT)) & TRDC_MBC4_MRC_DOM6_RGD_NSE_BIT0_MASK) + +#define TRDC_MBC4_MRC_DOM6_RGD_NSE_BIT1_MASK (0x2U) +#define TRDC_MBC4_MRC_DOM6_RGD_NSE_BIT1_SHIFT (1U) +/*! BIT1 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM6_RGD_NSE_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM6_RGD_NSE_BIT1_SHIFT)) & TRDC_MBC4_MRC_DOM6_RGD_NSE_BIT1_MASK) + +#define TRDC_MBC4_MRC_DOM6_RGD_NSE_BIT2_MASK (0x4U) +#define TRDC_MBC4_MRC_DOM6_RGD_NSE_BIT2_SHIFT (2U) +/*! BIT2 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM6_RGD_NSE_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM6_RGD_NSE_BIT2_SHIFT)) & TRDC_MBC4_MRC_DOM6_RGD_NSE_BIT2_MASK) + +#define TRDC_MBC4_MRC_DOM6_RGD_NSE_BIT3_MASK (0x8U) +#define TRDC_MBC4_MRC_DOM6_RGD_NSE_BIT3_SHIFT (3U) +/*! BIT3 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM6_RGD_NSE_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM6_RGD_NSE_BIT3_SHIFT)) & TRDC_MBC4_MRC_DOM6_RGD_NSE_BIT3_MASK) + +#define TRDC_MBC4_MRC_DOM6_RGD_NSE_BIT4_MASK (0x10U) +#define TRDC_MBC4_MRC_DOM6_RGD_NSE_BIT4_SHIFT (4U) +/*! BIT4 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM6_RGD_NSE_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM6_RGD_NSE_BIT4_SHIFT)) & TRDC_MBC4_MRC_DOM6_RGD_NSE_BIT4_MASK) + +#define TRDC_MBC4_MRC_DOM6_RGD_NSE_BIT5_MASK (0x20U) +#define TRDC_MBC4_MRC_DOM6_RGD_NSE_BIT5_SHIFT (5U) +/*! BIT5 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM6_RGD_NSE_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM6_RGD_NSE_BIT5_SHIFT)) & TRDC_MBC4_MRC_DOM6_RGD_NSE_BIT5_MASK) + +#define TRDC_MBC4_MRC_DOM6_RGD_NSE_BIT6_MASK (0x40U) +#define TRDC_MBC4_MRC_DOM6_RGD_NSE_BIT6_SHIFT (6U) +/*! BIT6 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM6_RGD_NSE_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM6_RGD_NSE_BIT6_SHIFT)) & TRDC_MBC4_MRC_DOM6_RGD_NSE_BIT6_MASK) + +#define TRDC_MBC4_MRC_DOM6_RGD_NSE_BIT7_MASK (0x80U) +#define TRDC_MBC4_MRC_DOM6_RGD_NSE_BIT7_SHIFT (7U) +/*! BIT7 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM6_RGD_NSE_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM6_RGD_NSE_BIT7_SHIFT)) & TRDC_MBC4_MRC_DOM6_RGD_NSE_BIT7_MASK) + +#define TRDC_MBC4_MRC_DOM6_RGD_NSE_BIT8_MASK (0x100U) +#define TRDC_MBC4_MRC_DOM6_RGD_NSE_BIT8_SHIFT (8U) +/*! BIT8 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM6_RGD_NSE_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM6_RGD_NSE_BIT8_SHIFT)) & TRDC_MBC4_MRC_DOM6_RGD_NSE_BIT8_MASK) + +#define TRDC_MBC4_MRC_DOM6_RGD_NSE_BIT9_MASK (0x200U) +#define TRDC_MBC4_MRC_DOM6_RGD_NSE_BIT9_SHIFT (9U) +/*! BIT9 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM6_RGD_NSE_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM6_RGD_NSE_BIT9_SHIFT)) & TRDC_MBC4_MRC_DOM6_RGD_NSE_BIT9_MASK) + +#define TRDC_MBC4_MRC_DOM6_RGD_NSE_BIT10_MASK (0x400U) +#define TRDC_MBC4_MRC_DOM6_RGD_NSE_BIT10_SHIFT (10U) +/*! BIT10 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM6_RGD_NSE_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM6_RGD_NSE_BIT10_SHIFT)) & TRDC_MBC4_MRC_DOM6_RGD_NSE_BIT10_MASK) + +#define TRDC_MBC4_MRC_DOM6_RGD_NSE_BIT11_MASK (0x800U) +#define TRDC_MBC4_MRC_DOM6_RGD_NSE_BIT11_SHIFT (11U) +/*! BIT11 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM6_RGD_NSE_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM6_RGD_NSE_BIT11_SHIFT)) & TRDC_MBC4_MRC_DOM6_RGD_NSE_BIT11_MASK) + +#define TRDC_MBC4_MRC_DOM6_RGD_NSE_BIT12_MASK (0x1000U) +#define TRDC_MBC4_MRC_DOM6_RGD_NSE_BIT12_SHIFT (12U) +/*! BIT12 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM6_RGD_NSE_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM6_RGD_NSE_BIT12_SHIFT)) & TRDC_MBC4_MRC_DOM6_RGD_NSE_BIT12_MASK) + +#define TRDC_MBC4_MRC_DOM6_RGD_NSE_BIT13_MASK (0x2000U) +#define TRDC_MBC4_MRC_DOM6_RGD_NSE_BIT13_SHIFT (13U) +/*! BIT13 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM6_RGD_NSE_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM6_RGD_NSE_BIT13_SHIFT)) & TRDC_MBC4_MRC_DOM6_RGD_NSE_BIT13_MASK) + +#define TRDC_MBC4_MRC_DOM6_RGD_NSE_BIT14_MASK (0x4000U) +#define TRDC_MBC4_MRC_DOM6_RGD_NSE_BIT14_SHIFT (14U) +/*! BIT14 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM6_RGD_NSE_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM6_RGD_NSE_BIT14_SHIFT)) & TRDC_MBC4_MRC_DOM6_RGD_NSE_BIT14_MASK) + +#define TRDC_MBC4_MRC_DOM6_RGD_NSE_BIT15_MASK (0x8000U) +#define TRDC_MBC4_MRC_DOM6_RGD_NSE_BIT15_SHIFT (15U) +/*! BIT15 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM6_RGD_NSE_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM6_RGD_NSE_BIT15_SHIFT)) & TRDC_MBC4_MRC_DOM6_RGD_NSE_BIT15_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MRC_DOM6_RGD_NSE */ +#define TRDC_MBC4_MRC_DOM6_RGD_NSE_COUNT (1U) + +/*! @name MRC_DOM7_RGD_W - MRC Region Descriptor Word 0..MRC Region Descriptor Word 1 */ +/*! @{ */ + +#define TRDC_MBC4_MRC_DOM7_RGD_W_MRACSEL_MASK (0x7U) +#define TRDC_MBC4_MRC_DOM7_RGD_W_MRACSEL_SHIFT (0U) +/*! MRACSEL - Memory Region Access Control Select + * 0b000..Select MRC_GLBAC0 access control policy + * 0b001..Select MRC_GLBAC1 access control policy + * 0b010..Select MRC_GLBAC2 access control policy + * 0b011..Select MRC_GLBAC3 access control policy + * 0b100..Select MRC_GLBAC4 access control policy + * 0b101..Select MRC_GLBAC5 access control policy + * 0b110..Select MRC_GLBAC6 access control policy + * 0b111..Select MRC_GLBAC7 access control policy + */ +#define TRDC_MBC4_MRC_DOM7_RGD_W_MRACSEL(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM7_RGD_W_MRACSEL_SHIFT)) & TRDC_MBC4_MRC_DOM7_RGD_W_MRACSEL_MASK) + +#define TRDC_MBC4_MRC_DOM7_RGD_W_VLD_MASK (0x1U) +#define TRDC_MBC4_MRC_DOM7_RGD_W_VLD_SHIFT (0U) +/*! VLD - Valid */ +#define TRDC_MBC4_MRC_DOM7_RGD_W_VLD(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM7_RGD_W_VLD_SHIFT)) & TRDC_MBC4_MRC_DOM7_RGD_W_VLD_MASK) + +#define TRDC_MBC4_MRC_DOM7_RGD_W_NSE_MASK (0x10U) +#define TRDC_MBC4_MRC_DOM7_RGD_W_NSE_SHIFT (4U) +/*! NSE - NonSecure Enable + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in this register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM7_RGD_W_NSE(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM7_RGD_W_NSE_SHIFT)) & TRDC_MBC4_MRC_DOM7_RGD_W_NSE_MASK) + +#define TRDC_MBC4_MRC_DOM7_RGD_W_END_ADDR_MASK (0xFFFFC000U) +#define TRDC_MBC4_MRC_DOM7_RGD_W_END_ADDR_SHIFT (14U) +/*! END_ADDR - End Address */ +#define TRDC_MBC4_MRC_DOM7_RGD_W_END_ADDR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM7_RGD_W_END_ADDR_SHIFT)) & TRDC_MBC4_MRC_DOM7_RGD_W_END_ADDR_MASK) + +#define TRDC_MBC4_MRC_DOM7_RGD_W_STRT_ADDR_MASK (0xFFFFC000U) +#define TRDC_MBC4_MRC_DOM7_RGD_W_STRT_ADDR_SHIFT (14U) +/*! STRT_ADDR - Start Address */ +#define TRDC_MBC4_MRC_DOM7_RGD_W_STRT_ADDR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM7_RGD_W_STRT_ADDR_SHIFT)) & TRDC_MBC4_MRC_DOM7_RGD_W_STRT_ADDR_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MRC_DOM7_RGD_W */ +#define TRDC_MBC4_MRC_DOM7_RGD_W_COUNT (1U) + +/* The count of TRDC_MBC4_MRC_DOM7_RGD_W */ +#define TRDC_MBC4_MRC_DOM7_RGD_W_COUNT2 (16U) + +/* The count of TRDC_MBC4_MRC_DOM7_RGD_W */ +#define TRDC_MBC4_MRC_DOM7_RGD_W_COUNT3 (2U) + +/*! @name MRC_DOM7_RGD_NSE - MRC Region Descriptor NonSecure Enable */ +/*! @{ */ + +#define TRDC_MBC4_MRC_DOM7_RGD_NSE_BIT0_MASK (0x1U) +#define TRDC_MBC4_MRC_DOM7_RGD_NSE_BIT0_SHIFT (0U) +/*! BIT0 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM7_RGD_NSE_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM7_RGD_NSE_BIT0_SHIFT)) & TRDC_MBC4_MRC_DOM7_RGD_NSE_BIT0_MASK) + +#define TRDC_MBC4_MRC_DOM7_RGD_NSE_BIT1_MASK (0x2U) +#define TRDC_MBC4_MRC_DOM7_RGD_NSE_BIT1_SHIFT (1U) +/*! BIT1 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM7_RGD_NSE_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM7_RGD_NSE_BIT1_SHIFT)) & TRDC_MBC4_MRC_DOM7_RGD_NSE_BIT1_MASK) + +#define TRDC_MBC4_MRC_DOM7_RGD_NSE_BIT2_MASK (0x4U) +#define TRDC_MBC4_MRC_DOM7_RGD_NSE_BIT2_SHIFT (2U) +/*! BIT2 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM7_RGD_NSE_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM7_RGD_NSE_BIT2_SHIFT)) & TRDC_MBC4_MRC_DOM7_RGD_NSE_BIT2_MASK) + +#define TRDC_MBC4_MRC_DOM7_RGD_NSE_BIT3_MASK (0x8U) +#define TRDC_MBC4_MRC_DOM7_RGD_NSE_BIT3_SHIFT (3U) +/*! BIT3 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM7_RGD_NSE_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM7_RGD_NSE_BIT3_SHIFT)) & TRDC_MBC4_MRC_DOM7_RGD_NSE_BIT3_MASK) + +#define TRDC_MBC4_MRC_DOM7_RGD_NSE_BIT4_MASK (0x10U) +#define TRDC_MBC4_MRC_DOM7_RGD_NSE_BIT4_SHIFT (4U) +/*! BIT4 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM7_RGD_NSE_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM7_RGD_NSE_BIT4_SHIFT)) & TRDC_MBC4_MRC_DOM7_RGD_NSE_BIT4_MASK) + +#define TRDC_MBC4_MRC_DOM7_RGD_NSE_BIT5_MASK (0x20U) +#define TRDC_MBC4_MRC_DOM7_RGD_NSE_BIT5_SHIFT (5U) +/*! BIT5 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM7_RGD_NSE_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM7_RGD_NSE_BIT5_SHIFT)) & TRDC_MBC4_MRC_DOM7_RGD_NSE_BIT5_MASK) + +#define TRDC_MBC4_MRC_DOM7_RGD_NSE_BIT6_MASK (0x40U) +#define TRDC_MBC4_MRC_DOM7_RGD_NSE_BIT6_SHIFT (6U) +/*! BIT6 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM7_RGD_NSE_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM7_RGD_NSE_BIT6_SHIFT)) & TRDC_MBC4_MRC_DOM7_RGD_NSE_BIT6_MASK) + +#define TRDC_MBC4_MRC_DOM7_RGD_NSE_BIT7_MASK (0x80U) +#define TRDC_MBC4_MRC_DOM7_RGD_NSE_BIT7_SHIFT (7U) +/*! BIT7 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM7_RGD_NSE_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM7_RGD_NSE_BIT7_SHIFT)) & TRDC_MBC4_MRC_DOM7_RGD_NSE_BIT7_MASK) + +#define TRDC_MBC4_MRC_DOM7_RGD_NSE_BIT8_MASK (0x100U) +#define TRDC_MBC4_MRC_DOM7_RGD_NSE_BIT8_SHIFT (8U) +/*! BIT8 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM7_RGD_NSE_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM7_RGD_NSE_BIT8_SHIFT)) & TRDC_MBC4_MRC_DOM7_RGD_NSE_BIT8_MASK) + +#define TRDC_MBC4_MRC_DOM7_RGD_NSE_BIT9_MASK (0x200U) +#define TRDC_MBC4_MRC_DOM7_RGD_NSE_BIT9_SHIFT (9U) +/*! BIT9 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM7_RGD_NSE_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM7_RGD_NSE_BIT9_SHIFT)) & TRDC_MBC4_MRC_DOM7_RGD_NSE_BIT9_MASK) + +#define TRDC_MBC4_MRC_DOM7_RGD_NSE_BIT10_MASK (0x400U) +#define TRDC_MBC4_MRC_DOM7_RGD_NSE_BIT10_SHIFT (10U) +/*! BIT10 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM7_RGD_NSE_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM7_RGD_NSE_BIT10_SHIFT)) & TRDC_MBC4_MRC_DOM7_RGD_NSE_BIT10_MASK) + +#define TRDC_MBC4_MRC_DOM7_RGD_NSE_BIT11_MASK (0x800U) +#define TRDC_MBC4_MRC_DOM7_RGD_NSE_BIT11_SHIFT (11U) +/*! BIT11 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM7_RGD_NSE_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM7_RGD_NSE_BIT11_SHIFT)) & TRDC_MBC4_MRC_DOM7_RGD_NSE_BIT11_MASK) + +#define TRDC_MBC4_MRC_DOM7_RGD_NSE_BIT12_MASK (0x1000U) +#define TRDC_MBC4_MRC_DOM7_RGD_NSE_BIT12_SHIFT (12U) +/*! BIT12 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM7_RGD_NSE_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM7_RGD_NSE_BIT12_SHIFT)) & TRDC_MBC4_MRC_DOM7_RGD_NSE_BIT12_MASK) + +#define TRDC_MBC4_MRC_DOM7_RGD_NSE_BIT13_MASK (0x2000U) +#define TRDC_MBC4_MRC_DOM7_RGD_NSE_BIT13_SHIFT (13U) +/*! BIT13 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM7_RGD_NSE_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM7_RGD_NSE_BIT13_SHIFT)) & TRDC_MBC4_MRC_DOM7_RGD_NSE_BIT13_MASK) + +#define TRDC_MBC4_MRC_DOM7_RGD_NSE_BIT14_MASK (0x4000U) +#define TRDC_MBC4_MRC_DOM7_RGD_NSE_BIT14_SHIFT (14U) +/*! BIT14 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM7_RGD_NSE_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM7_RGD_NSE_BIT14_SHIFT)) & TRDC_MBC4_MRC_DOM7_RGD_NSE_BIT14_MASK) + +#define TRDC_MBC4_MRC_DOM7_RGD_NSE_BIT15_MASK (0x8000U) +#define TRDC_MBC4_MRC_DOM7_RGD_NSE_BIT15_SHIFT (15U) +/*! BIT15 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM7_RGD_NSE_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM7_RGD_NSE_BIT15_SHIFT)) & TRDC_MBC4_MRC_DOM7_RGD_NSE_BIT15_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MRC_DOM7_RGD_NSE */ +#define TRDC_MBC4_MRC_DOM7_RGD_NSE_COUNT (1U) + +/*! @name MRC_DOM8_RGD_W - MRC Region Descriptor Word 0..MRC Region Descriptor Word 1 */ +/*! @{ */ + +#define TRDC_MBC4_MRC_DOM8_RGD_W_MRACSEL_MASK (0x7U) +#define TRDC_MBC4_MRC_DOM8_RGD_W_MRACSEL_SHIFT (0U) +/*! MRACSEL - Memory Region Access Control Select + * 0b000..Select MRC_GLBAC0 access control policy + * 0b001..Select MRC_GLBAC1 access control policy + * 0b010..Select MRC_GLBAC2 access control policy + * 0b011..Select MRC_GLBAC3 access control policy + * 0b100..Select MRC_GLBAC4 access control policy + * 0b101..Select MRC_GLBAC5 access control policy + * 0b110..Select MRC_GLBAC6 access control policy + * 0b111..Select MRC_GLBAC7 access control policy + */ +#define TRDC_MBC4_MRC_DOM8_RGD_W_MRACSEL(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM8_RGD_W_MRACSEL_SHIFT)) & TRDC_MBC4_MRC_DOM8_RGD_W_MRACSEL_MASK) + +#define TRDC_MBC4_MRC_DOM8_RGD_W_VLD_MASK (0x1U) +#define TRDC_MBC4_MRC_DOM8_RGD_W_VLD_SHIFT (0U) +/*! VLD - Valid */ +#define TRDC_MBC4_MRC_DOM8_RGD_W_VLD(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM8_RGD_W_VLD_SHIFT)) & TRDC_MBC4_MRC_DOM8_RGD_W_VLD_MASK) + +#define TRDC_MBC4_MRC_DOM8_RGD_W_NSE_MASK (0x10U) +#define TRDC_MBC4_MRC_DOM8_RGD_W_NSE_SHIFT (4U) +/*! NSE - NonSecure Enable + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in this register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM8_RGD_W_NSE(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM8_RGD_W_NSE_SHIFT)) & TRDC_MBC4_MRC_DOM8_RGD_W_NSE_MASK) + +#define TRDC_MBC4_MRC_DOM8_RGD_W_END_ADDR_MASK (0xFFFFC000U) +#define TRDC_MBC4_MRC_DOM8_RGD_W_END_ADDR_SHIFT (14U) +/*! END_ADDR - End Address */ +#define TRDC_MBC4_MRC_DOM8_RGD_W_END_ADDR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM8_RGD_W_END_ADDR_SHIFT)) & TRDC_MBC4_MRC_DOM8_RGD_W_END_ADDR_MASK) + +#define TRDC_MBC4_MRC_DOM8_RGD_W_STRT_ADDR_MASK (0xFFFFC000U) +#define TRDC_MBC4_MRC_DOM8_RGD_W_STRT_ADDR_SHIFT (14U) +/*! STRT_ADDR - Start Address */ +#define TRDC_MBC4_MRC_DOM8_RGD_W_STRT_ADDR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM8_RGD_W_STRT_ADDR_SHIFT)) & TRDC_MBC4_MRC_DOM8_RGD_W_STRT_ADDR_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MRC_DOM8_RGD_W */ +#define TRDC_MBC4_MRC_DOM8_RGD_W_COUNT (1U) + +/* The count of TRDC_MBC4_MRC_DOM8_RGD_W */ +#define TRDC_MBC4_MRC_DOM8_RGD_W_COUNT2 (16U) + +/* The count of TRDC_MBC4_MRC_DOM8_RGD_W */ +#define TRDC_MBC4_MRC_DOM8_RGD_W_COUNT3 (2U) + +/*! @name MRC_DOM8_RGD_NSE - MRC Region Descriptor NonSecure Enable */ +/*! @{ */ + +#define TRDC_MBC4_MRC_DOM8_RGD_NSE_BIT0_MASK (0x1U) +#define TRDC_MBC4_MRC_DOM8_RGD_NSE_BIT0_SHIFT (0U) +/*! BIT0 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM8_RGD_NSE_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM8_RGD_NSE_BIT0_SHIFT)) & TRDC_MBC4_MRC_DOM8_RGD_NSE_BIT0_MASK) + +#define TRDC_MBC4_MRC_DOM8_RGD_NSE_BIT1_MASK (0x2U) +#define TRDC_MBC4_MRC_DOM8_RGD_NSE_BIT1_SHIFT (1U) +/*! BIT1 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM8_RGD_NSE_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM8_RGD_NSE_BIT1_SHIFT)) & TRDC_MBC4_MRC_DOM8_RGD_NSE_BIT1_MASK) + +#define TRDC_MBC4_MRC_DOM8_RGD_NSE_BIT2_MASK (0x4U) +#define TRDC_MBC4_MRC_DOM8_RGD_NSE_BIT2_SHIFT (2U) +/*! BIT2 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM8_RGD_NSE_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM8_RGD_NSE_BIT2_SHIFT)) & TRDC_MBC4_MRC_DOM8_RGD_NSE_BIT2_MASK) + +#define TRDC_MBC4_MRC_DOM8_RGD_NSE_BIT3_MASK (0x8U) +#define TRDC_MBC4_MRC_DOM8_RGD_NSE_BIT3_SHIFT (3U) +/*! BIT3 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM8_RGD_NSE_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM8_RGD_NSE_BIT3_SHIFT)) & TRDC_MBC4_MRC_DOM8_RGD_NSE_BIT3_MASK) + +#define TRDC_MBC4_MRC_DOM8_RGD_NSE_BIT4_MASK (0x10U) +#define TRDC_MBC4_MRC_DOM8_RGD_NSE_BIT4_SHIFT (4U) +/*! BIT4 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM8_RGD_NSE_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM8_RGD_NSE_BIT4_SHIFT)) & TRDC_MBC4_MRC_DOM8_RGD_NSE_BIT4_MASK) + +#define TRDC_MBC4_MRC_DOM8_RGD_NSE_BIT5_MASK (0x20U) +#define TRDC_MBC4_MRC_DOM8_RGD_NSE_BIT5_SHIFT (5U) +/*! BIT5 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM8_RGD_NSE_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM8_RGD_NSE_BIT5_SHIFT)) & TRDC_MBC4_MRC_DOM8_RGD_NSE_BIT5_MASK) + +#define TRDC_MBC4_MRC_DOM8_RGD_NSE_BIT6_MASK (0x40U) +#define TRDC_MBC4_MRC_DOM8_RGD_NSE_BIT6_SHIFT (6U) +/*! BIT6 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM8_RGD_NSE_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM8_RGD_NSE_BIT6_SHIFT)) & TRDC_MBC4_MRC_DOM8_RGD_NSE_BIT6_MASK) + +#define TRDC_MBC4_MRC_DOM8_RGD_NSE_BIT7_MASK (0x80U) +#define TRDC_MBC4_MRC_DOM8_RGD_NSE_BIT7_SHIFT (7U) +/*! BIT7 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM8_RGD_NSE_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM8_RGD_NSE_BIT7_SHIFT)) & TRDC_MBC4_MRC_DOM8_RGD_NSE_BIT7_MASK) + +#define TRDC_MBC4_MRC_DOM8_RGD_NSE_BIT8_MASK (0x100U) +#define TRDC_MBC4_MRC_DOM8_RGD_NSE_BIT8_SHIFT (8U) +/*! BIT8 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM8_RGD_NSE_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM8_RGD_NSE_BIT8_SHIFT)) & TRDC_MBC4_MRC_DOM8_RGD_NSE_BIT8_MASK) + +#define TRDC_MBC4_MRC_DOM8_RGD_NSE_BIT9_MASK (0x200U) +#define TRDC_MBC4_MRC_DOM8_RGD_NSE_BIT9_SHIFT (9U) +/*! BIT9 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM8_RGD_NSE_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM8_RGD_NSE_BIT9_SHIFT)) & TRDC_MBC4_MRC_DOM8_RGD_NSE_BIT9_MASK) + +#define TRDC_MBC4_MRC_DOM8_RGD_NSE_BIT10_MASK (0x400U) +#define TRDC_MBC4_MRC_DOM8_RGD_NSE_BIT10_SHIFT (10U) +/*! BIT10 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM8_RGD_NSE_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM8_RGD_NSE_BIT10_SHIFT)) & TRDC_MBC4_MRC_DOM8_RGD_NSE_BIT10_MASK) + +#define TRDC_MBC4_MRC_DOM8_RGD_NSE_BIT11_MASK (0x800U) +#define TRDC_MBC4_MRC_DOM8_RGD_NSE_BIT11_SHIFT (11U) +/*! BIT11 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM8_RGD_NSE_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM8_RGD_NSE_BIT11_SHIFT)) & TRDC_MBC4_MRC_DOM8_RGD_NSE_BIT11_MASK) + +#define TRDC_MBC4_MRC_DOM8_RGD_NSE_BIT12_MASK (0x1000U) +#define TRDC_MBC4_MRC_DOM8_RGD_NSE_BIT12_SHIFT (12U) +/*! BIT12 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM8_RGD_NSE_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM8_RGD_NSE_BIT12_SHIFT)) & TRDC_MBC4_MRC_DOM8_RGD_NSE_BIT12_MASK) + +#define TRDC_MBC4_MRC_DOM8_RGD_NSE_BIT13_MASK (0x2000U) +#define TRDC_MBC4_MRC_DOM8_RGD_NSE_BIT13_SHIFT (13U) +/*! BIT13 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM8_RGD_NSE_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM8_RGD_NSE_BIT13_SHIFT)) & TRDC_MBC4_MRC_DOM8_RGD_NSE_BIT13_MASK) + +#define TRDC_MBC4_MRC_DOM8_RGD_NSE_BIT14_MASK (0x4000U) +#define TRDC_MBC4_MRC_DOM8_RGD_NSE_BIT14_SHIFT (14U) +/*! BIT14 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM8_RGD_NSE_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM8_RGD_NSE_BIT14_SHIFT)) & TRDC_MBC4_MRC_DOM8_RGD_NSE_BIT14_MASK) + +#define TRDC_MBC4_MRC_DOM8_RGD_NSE_BIT15_MASK (0x8000U) +#define TRDC_MBC4_MRC_DOM8_RGD_NSE_BIT15_SHIFT (15U) +/*! BIT15 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM8_RGD_NSE_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM8_RGD_NSE_BIT15_SHIFT)) & TRDC_MBC4_MRC_DOM8_RGD_NSE_BIT15_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MRC_DOM8_RGD_NSE */ +#define TRDC_MBC4_MRC_DOM8_RGD_NSE_COUNT (1U) + +/*! @name MRC_DOM9_RGD_W - MRC Region Descriptor Word 0..MRC Region Descriptor Word 1 */ +/*! @{ */ + +#define TRDC_MBC4_MRC_DOM9_RGD_W_MRACSEL_MASK (0x7U) +#define TRDC_MBC4_MRC_DOM9_RGD_W_MRACSEL_SHIFT (0U) +/*! MRACSEL - Memory Region Access Control Select + * 0b000..Select MRC_GLBAC0 access control policy + * 0b001..Select MRC_GLBAC1 access control policy + * 0b010..Select MRC_GLBAC2 access control policy + * 0b011..Select MRC_GLBAC3 access control policy + * 0b100..Select MRC_GLBAC4 access control policy + * 0b101..Select MRC_GLBAC5 access control policy + * 0b110..Select MRC_GLBAC6 access control policy + * 0b111..Select MRC_GLBAC7 access control policy + */ +#define TRDC_MBC4_MRC_DOM9_RGD_W_MRACSEL(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM9_RGD_W_MRACSEL_SHIFT)) & TRDC_MBC4_MRC_DOM9_RGD_W_MRACSEL_MASK) + +#define TRDC_MBC4_MRC_DOM9_RGD_W_VLD_MASK (0x1U) +#define TRDC_MBC4_MRC_DOM9_RGD_W_VLD_SHIFT (0U) +/*! VLD - Valid */ +#define TRDC_MBC4_MRC_DOM9_RGD_W_VLD(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM9_RGD_W_VLD_SHIFT)) & TRDC_MBC4_MRC_DOM9_RGD_W_VLD_MASK) + +#define TRDC_MBC4_MRC_DOM9_RGD_W_NSE_MASK (0x10U) +#define TRDC_MBC4_MRC_DOM9_RGD_W_NSE_SHIFT (4U) +/*! NSE - NonSecure Enable + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in this register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM9_RGD_W_NSE(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM9_RGD_W_NSE_SHIFT)) & TRDC_MBC4_MRC_DOM9_RGD_W_NSE_MASK) + +#define TRDC_MBC4_MRC_DOM9_RGD_W_END_ADDR_MASK (0xFFFFC000U) +#define TRDC_MBC4_MRC_DOM9_RGD_W_END_ADDR_SHIFT (14U) +/*! END_ADDR - End Address */ +#define TRDC_MBC4_MRC_DOM9_RGD_W_END_ADDR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM9_RGD_W_END_ADDR_SHIFT)) & TRDC_MBC4_MRC_DOM9_RGD_W_END_ADDR_MASK) + +#define TRDC_MBC4_MRC_DOM9_RGD_W_STRT_ADDR_MASK (0xFFFFC000U) +#define TRDC_MBC4_MRC_DOM9_RGD_W_STRT_ADDR_SHIFT (14U) +/*! STRT_ADDR - Start Address */ +#define TRDC_MBC4_MRC_DOM9_RGD_W_STRT_ADDR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM9_RGD_W_STRT_ADDR_SHIFT)) & TRDC_MBC4_MRC_DOM9_RGD_W_STRT_ADDR_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MRC_DOM9_RGD_W */ +#define TRDC_MBC4_MRC_DOM9_RGD_W_COUNT (1U) + +/* The count of TRDC_MBC4_MRC_DOM9_RGD_W */ +#define TRDC_MBC4_MRC_DOM9_RGD_W_COUNT2 (16U) + +/* The count of TRDC_MBC4_MRC_DOM9_RGD_W */ +#define TRDC_MBC4_MRC_DOM9_RGD_W_COUNT3 (2U) + +/*! @name MRC_DOM9_RGD_NSE - MRC Region Descriptor NonSecure Enable */ +/*! @{ */ + +#define TRDC_MBC4_MRC_DOM9_RGD_NSE_BIT0_MASK (0x1U) +#define TRDC_MBC4_MRC_DOM9_RGD_NSE_BIT0_SHIFT (0U) +/*! BIT0 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM9_RGD_NSE_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM9_RGD_NSE_BIT0_SHIFT)) & TRDC_MBC4_MRC_DOM9_RGD_NSE_BIT0_MASK) + +#define TRDC_MBC4_MRC_DOM9_RGD_NSE_BIT1_MASK (0x2U) +#define TRDC_MBC4_MRC_DOM9_RGD_NSE_BIT1_SHIFT (1U) +/*! BIT1 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM9_RGD_NSE_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM9_RGD_NSE_BIT1_SHIFT)) & TRDC_MBC4_MRC_DOM9_RGD_NSE_BIT1_MASK) + +#define TRDC_MBC4_MRC_DOM9_RGD_NSE_BIT2_MASK (0x4U) +#define TRDC_MBC4_MRC_DOM9_RGD_NSE_BIT2_SHIFT (2U) +/*! BIT2 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM9_RGD_NSE_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM9_RGD_NSE_BIT2_SHIFT)) & TRDC_MBC4_MRC_DOM9_RGD_NSE_BIT2_MASK) + +#define TRDC_MBC4_MRC_DOM9_RGD_NSE_BIT3_MASK (0x8U) +#define TRDC_MBC4_MRC_DOM9_RGD_NSE_BIT3_SHIFT (3U) +/*! BIT3 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM9_RGD_NSE_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM9_RGD_NSE_BIT3_SHIFT)) & TRDC_MBC4_MRC_DOM9_RGD_NSE_BIT3_MASK) + +#define TRDC_MBC4_MRC_DOM9_RGD_NSE_BIT4_MASK (0x10U) +#define TRDC_MBC4_MRC_DOM9_RGD_NSE_BIT4_SHIFT (4U) +/*! BIT4 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM9_RGD_NSE_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM9_RGD_NSE_BIT4_SHIFT)) & TRDC_MBC4_MRC_DOM9_RGD_NSE_BIT4_MASK) + +#define TRDC_MBC4_MRC_DOM9_RGD_NSE_BIT5_MASK (0x20U) +#define TRDC_MBC4_MRC_DOM9_RGD_NSE_BIT5_SHIFT (5U) +/*! BIT5 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM9_RGD_NSE_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM9_RGD_NSE_BIT5_SHIFT)) & TRDC_MBC4_MRC_DOM9_RGD_NSE_BIT5_MASK) + +#define TRDC_MBC4_MRC_DOM9_RGD_NSE_BIT6_MASK (0x40U) +#define TRDC_MBC4_MRC_DOM9_RGD_NSE_BIT6_SHIFT (6U) +/*! BIT6 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM9_RGD_NSE_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM9_RGD_NSE_BIT6_SHIFT)) & TRDC_MBC4_MRC_DOM9_RGD_NSE_BIT6_MASK) + +#define TRDC_MBC4_MRC_DOM9_RGD_NSE_BIT7_MASK (0x80U) +#define TRDC_MBC4_MRC_DOM9_RGD_NSE_BIT7_SHIFT (7U) +/*! BIT7 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM9_RGD_NSE_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM9_RGD_NSE_BIT7_SHIFT)) & TRDC_MBC4_MRC_DOM9_RGD_NSE_BIT7_MASK) + +#define TRDC_MBC4_MRC_DOM9_RGD_NSE_BIT8_MASK (0x100U) +#define TRDC_MBC4_MRC_DOM9_RGD_NSE_BIT8_SHIFT (8U) +/*! BIT8 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM9_RGD_NSE_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM9_RGD_NSE_BIT8_SHIFT)) & TRDC_MBC4_MRC_DOM9_RGD_NSE_BIT8_MASK) + +#define TRDC_MBC4_MRC_DOM9_RGD_NSE_BIT9_MASK (0x200U) +#define TRDC_MBC4_MRC_DOM9_RGD_NSE_BIT9_SHIFT (9U) +/*! BIT9 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM9_RGD_NSE_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM9_RGD_NSE_BIT9_SHIFT)) & TRDC_MBC4_MRC_DOM9_RGD_NSE_BIT9_MASK) + +#define TRDC_MBC4_MRC_DOM9_RGD_NSE_BIT10_MASK (0x400U) +#define TRDC_MBC4_MRC_DOM9_RGD_NSE_BIT10_SHIFT (10U) +/*! BIT10 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM9_RGD_NSE_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM9_RGD_NSE_BIT10_SHIFT)) & TRDC_MBC4_MRC_DOM9_RGD_NSE_BIT10_MASK) + +#define TRDC_MBC4_MRC_DOM9_RGD_NSE_BIT11_MASK (0x800U) +#define TRDC_MBC4_MRC_DOM9_RGD_NSE_BIT11_SHIFT (11U) +/*! BIT11 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM9_RGD_NSE_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM9_RGD_NSE_BIT11_SHIFT)) & TRDC_MBC4_MRC_DOM9_RGD_NSE_BIT11_MASK) + +#define TRDC_MBC4_MRC_DOM9_RGD_NSE_BIT12_MASK (0x1000U) +#define TRDC_MBC4_MRC_DOM9_RGD_NSE_BIT12_SHIFT (12U) +/*! BIT12 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM9_RGD_NSE_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM9_RGD_NSE_BIT12_SHIFT)) & TRDC_MBC4_MRC_DOM9_RGD_NSE_BIT12_MASK) + +#define TRDC_MBC4_MRC_DOM9_RGD_NSE_BIT13_MASK (0x2000U) +#define TRDC_MBC4_MRC_DOM9_RGD_NSE_BIT13_SHIFT (13U) +/*! BIT13 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM9_RGD_NSE_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM9_RGD_NSE_BIT13_SHIFT)) & TRDC_MBC4_MRC_DOM9_RGD_NSE_BIT13_MASK) + +#define TRDC_MBC4_MRC_DOM9_RGD_NSE_BIT14_MASK (0x4000U) +#define TRDC_MBC4_MRC_DOM9_RGD_NSE_BIT14_SHIFT (14U) +/*! BIT14 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM9_RGD_NSE_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM9_RGD_NSE_BIT14_SHIFT)) & TRDC_MBC4_MRC_DOM9_RGD_NSE_BIT14_MASK) + +#define TRDC_MBC4_MRC_DOM9_RGD_NSE_BIT15_MASK (0x8000U) +#define TRDC_MBC4_MRC_DOM9_RGD_NSE_BIT15_SHIFT (15U) +/*! BIT15 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM9_RGD_NSE_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM9_RGD_NSE_BIT15_SHIFT)) & TRDC_MBC4_MRC_DOM9_RGD_NSE_BIT15_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MRC_DOM9_RGD_NSE */ +#define TRDC_MBC4_MRC_DOM9_RGD_NSE_COUNT (1U) + +/*! @name MRC_DOM10_RGD_W - MRC Region Descriptor Word 0..MRC Region Descriptor Word 1 */ +/*! @{ */ + +#define TRDC_MBC4_MRC_DOM10_RGD_W_MRACSEL_MASK (0x7U) +#define TRDC_MBC4_MRC_DOM10_RGD_W_MRACSEL_SHIFT (0U) +/*! MRACSEL - Memory Region Access Control Select + * 0b000..Select MRC_GLBAC0 access control policy + * 0b001..Select MRC_GLBAC1 access control policy + * 0b010..Select MRC_GLBAC2 access control policy + * 0b011..Select MRC_GLBAC3 access control policy + * 0b100..Select MRC_GLBAC4 access control policy + * 0b101..Select MRC_GLBAC5 access control policy + * 0b110..Select MRC_GLBAC6 access control policy + * 0b111..Select MRC_GLBAC7 access control policy + */ +#define TRDC_MBC4_MRC_DOM10_RGD_W_MRACSEL(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM10_RGD_W_MRACSEL_SHIFT)) & TRDC_MBC4_MRC_DOM10_RGD_W_MRACSEL_MASK) + +#define TRDC_MBC4_MRC_DOM10_RGD_W_VLD_MASK (0x1U) +#define TRDC_MBC4_MRC_DOM10_RGD_W_VLD_SHIFT (0U) +/*! VLD - Valid */ +#define TRDC_MBC4_MRC_DOM10_RGD_W_VLD(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM10_RGD_W_VLD_SHIFT)) & TRDC_MBC4_MRC_DOM10_RGD_W_VLD_MASK) + +#define TRDC_MBC4_MRC_DOM10_RGD_W_NSE_MASK (0x10U) +#define TRDC_MBC4_MRC_DOM10_RGD_W_NSE_SHIFT (4U) +/*! NSE - NonSecure Enable + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in this register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM10_RGD_W_NSE(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM10_RGD_W_NSE_SHIFT)) & TRDC_MBC4_MRC_DOM10_RGD_W_NSE_MASK) + +#define TRDC_MBC4_MRC_DOM10_RGD_W_END_ADDR_MASK (0xFFFFC000U) +#define TRDC_MBC4_MRC_DOM10_RGD_W_END_ADDR_SHIFT (14U) +/*! END_ADDR - End Address */ +#define TRDC_MBC4_MRC_DOM10_RGD_W_END_ADDR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM10_RGD_W_END_ADDR_SHIFT)) & TRDC_MBC4_MRC_DOM10_RGD_W_END_ADDR_MASK) + +#define TRDC_MBC4_MRC_DOM10_RGD_W_STRT_ADDR_MASK (0xFFFFC000U) +#define TRDC_MBC4_MRC_DOM10_RGD_W_STRT_ADDR_SHIFT (14U) +/*! STRT_ADDR - Start Address */ +#define TRDC_MBC4_MRC_DOM10_RGD_W_STRT_ADDR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM10_RGD_W_STRT_ADDR_SHIFT)) & TRDC_MBC4_MRC_DOM10_RGD_W_STRT_ADDR_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MRC_DOM10_RGD_W */ +#define TRDC_MBC4_MRC_DOM10_RGD_W_COUNT (1U) + +/* The count of TRDC_MBC4_MRC_DOM10_RGD_W */ +#define TRDC_MBC4_MRC_DOM10_RGD_W_COUNT2 (16U) + +/* The count of TRDC_MBC4_MRC_DOM10_RGD_W */ +#define TRDC_MBC4_MRC_DOM10_RGD_W_COUNT3 (2U) + +/*! @name MRC_DOM10_RGD_NSE - MRC Region Descriptor NonSecure Enable */ +/*! @{ */ + +#define TRDC_MBC4_MRC_DOM10_RGD_NSE_BIT0_MASK (0x1U) +#define TRDC_MBC4_MRC_DOM10_RGD_NSE_BIT0_SHIFT (0U) +/*! BIT0 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM10_RGD_NSE_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM10_RGD_NSE_BIT0_SHIFT)) & TRDC_MBC4_MRC_DOM10_RGD_NSE_BIT0_MASK) + +#define TRDC_MBC4_MRC_DOM10_RGD_NSE_BIT1_MASK (0x2U) +#define TRDC_MBC4_MRC_DOM10_RGD_NSE_BIT1_SHIFT (1U) +/*! BIT1 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM10_RGD_NSE_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM10_RGD_NSE_BIT1_SHIFT)) & TRDC_MBC4_MRC_DOM10_RGD_NSE_BIT1_MASK) + +#define TRDC_MBC4_MRC_DOM10_RGD_NSE_BIT2_MASK (0x4U) +#define TRDC_MBC4_MRC_DOM10_RGD_NSE_BIT2_SHIFT (2U) +/*! BIT2 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM10_RGD_NSE_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM10_RGD_NSE_BIT2_SHIFT)) & TRDC_MBC4_MRC_DOM10_RGD_NSE_BIT2_MASK) + +#define TRDC_MBC4_MRC_DOM10_RGD_NSE_BIT3_MASK (0x8U) +#define TRDC_MBC4_MRC_DOM10_RGD_NSE_BIT3_SHIFT (3U) +/*! BIT3 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM10_RGD_NSE_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM10_RGD_NSE_BIT3_SHIFT)) & TRDC_MBC4_MRC_DOM10_RGD_NSE_BIT3_MASK) + +#define TRDC_MBC4_MRC_DOM10_RGD_NSE_BIT4_MASK (0x10U) +#define TRDC_MBC4_MRC_DOM10_RGD_NSE_BIT4_SHIFT (4U) +/*! BIT4 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM10_RGD_NSE_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM10_RGD_NSE_BIT4_SHIFT)) & TRDC_MBC4_MRC_DOM10_RGD_NSE_BIT4_MASK) + +#define TRDC_MBC4_MRC_DOM10_RGD_NSE_BIT5_MASK (0x20U) +#define TRDC_MBC4_MRC_DOM10_RGD_NSE_BIT5_SHIFT (5U) +/*! BIT5 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM10_RGD_NSE_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM10_RGD_NSE_BIT5_SHIFT)) & TRDC_MBC4_MRC_DOM10_RGD_NSE_BIT5_MASK) + +#define TRDC_MBC4_MRC_DOM10_RGD_NSE_BIT6_MASK (0x40U) +#define TRDC_MBC4_MRC_DOM10_RGD_NSE_BIT6_SHIFT (6U) +/*! BIT6 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM10_RGD_NSE_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM10_RGD_NSE_BIT6_SHIFT)) & TRDC_MBC4_MRC_DOM10_RGD_NSE_BIT6_MASK) + +#define TRDC_MBC4_MRC_DOM10_RGD_NSE_BIT7_MASK (0x80U) +#define TRDC_MBC4_MRC_DOM10_RGD_NSE_BIT7_SHIFT (7U) +/*! BIT7 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM10_RGD_NSE_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM10_RGD_NSE_BIT7_SHIFT)) & TRDC_MBC4_MRC_DOM10_RGD_NSE_BIT7_MASK) + +#define TRDC_MBC4_MRC_DOM10_RGD_NSE_BIT8_MASK (0x100U) +#define TRDC_MBC4_MRC_DOM10_RGD_NSE_BIT8_SHIFT (8U) +/*! BIT8 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM10_RGD_NSE_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM10_RGD_NSE_BIT8_SHIFT)) & TRDC_MBC4_MRC_DOM10_RGD_NSE_BIT8_MASK) + +#define TRDC_MBC4_MRC_DOM10_RGD_NSE_BIT9_MASK (0x200U) +#define TRDC_MBC4_MRC_DOM10_RGD_NSE_BIT9_SHIFT (9U) +/*! BIT9 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM10_RGD_NSE_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM10_RGD_NSE_BIT9_SHIFT)) & TRDC_MBC4_MRC_DOM10_RGD_NSE_BIT9_MASK) + +#define TRDC_MBC4_MRC_DOM10_RGD_NSE_BIT10_MASK (0x400U) +#define TRDC_MBC4_MRC_DOM10_RGD_NSE_BIT10_SHIFT (10U) +/*! BIT10 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM10_RGD_NSE_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM10_RGD_NSE_BIT10_SHIFT)) & TRDC_MBC4_MRC_DOM10_RGD_NSE_BIT10_MASK) + +#define TRDC_MBC4_MRC_DOM10_RGD_NSE_BIT11_MASK (0x800U) +#define TRDC_MBC4_MRC_DOM10_RGD_NSE_BIT11_SHIFT (11U) +/*! BIT11 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM10_RGD_NSE_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM10_RGD_NSE_BIT11_SHIFT)) & TRDC_MBC4_MRC_DOM10_RGD_NSE_BIT11_MASK) + +#define TRDC_MBC4_MRC_DOM10_RGD_NSE_BIT12_MASK (0x1000U) +#define TRDC_MBC4_MRC_DOM10_RGD_NSE_BIT12_SHIFT (12U) +/*! BIT12 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM10_RGD_NSE_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM10_RGD_NSE_BIT12_SHIFT)) & TRDC_MBC4_MRC_DOM10_RGD_NSE_BIT12_MASK) + +#define TRDC_MBC4_MRC_DOM10_RGD_NSE_BIT13_MASK (0x2000U) +#define TRDC_MBC4_MRC_DOM10_RGD_NSE_BIT13_SHIFT (13U) +/*! BIT13 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM10_RGD_NSE_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM10_RGD_NSE_BIT13_SHIFT)) & TRDC_MBC4_MRC_DOM10_RGD_NSE_BIT13_MASK) + +#define TRDC_MBC4_MRC_DOM10_RGD_NSE_BIT14_MASK (0x4000U) +#define TRDC_MBC4_MRC_DOM10_RGD_NSE_BIT14_SHIFT (14U) +/*! BIT14 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM10_RGD_NSE_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM10_RGD_NSE_BIT14_SHIFT)) & TRDC_MBC4_MRC_DOM10_RGD_NSE_BIT14_MASK) + +#define TRDC_MBC4_MRC_DOM10_RGD_NSE_BIT15_MASK (0x8000U) +#define TRDC_MBC4_MRC_DOM10_RGD_NSE_BIT15_SHIFT (15U) +/*! BIT15 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM10_RGD_NSE_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM10_RGD_NSE_BIT15_SHIFT)) & TRDC_MBC4_MRC_DOM10_RGD_NSE_BIT15_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MRC_DOM10_RGD_NSE */ +#define TRDC_MBC4_MRC_DOM10_RGD_NSE_COUNT (1U) + +/*! @name MRC_DOM11_RGD_W - MRC Region Descriptor Word 0..MRC Region Descriptor Word 1 */ +/*! @{ */ + +#define TRDC_MBC4_MRC_DOM11_RGD_W_MRACSEL_MASK (0x7U) +#define TRDC_MBC4_MRC_DOM11_RGD_W_MRACSEL_SHIFT (0U) +/*! MRACSEL - Memory Region Access Control Select + * 0b000..Select MRC_GLBAC0 access control policy + * 0b001..Select MRC_GLBAC1 access control policy + * 0b010..Select MRC_GLBAC2 access control policy + * 0b011..Select MRC_GLBAC3 access control policy + * 0b100..Select MRC_GLBAC4 access control policy + * 0b101..Select MRC_GLBAC5 access control policy + * 0b110..Select MRC_GLBAC6 access control policy + * 0b111..Select MRC_GLBAC7 access control policy + */ +#define TRDC_MBC4_MRC_DOM11_RGD_W_MRACSEL(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM11_RGD_W_MRACSEL_SHIFT)) & TRDC_MBC4_MRC_DOM11_RGD_W_MRACSEL_MASK) + +#define TRDC_MBC4_MRC_DOM11_RGD_W_VLD_MASK (0x1U) +#define TRDC_MBC4_MRC_DOM11_RGD_W_VLD_SHIFT (0U) +/*! VLD - Valid */ +#define TRDC_MBC4_MRC_DOM11_RGD_W_VLD(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM11_RGD_W_VLD_SHIFT)) & TRDC_MBC4_MRC_DOM11_RGD_W_VLD_MASK) + +#define TRDC_MBC4_MRC_DOM11_RGD_W_NSE_MASK (0x10U) +#define TRDC_MBC4_MRC_DOM11_RGD_W_NSE_SHIFT (4U) +/*! NSE - NonSecure Enable + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in this register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM11_RGD_W_NSE(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM11_RGD_W_NSE_SHIFT)) & TRDC_MBC4_MRC_DOM11_RGD_W_NSE_MASK) + +#define TRDC_MBC4_MRC_DOM11_RGD_W_END_ADDR_MASK (0xFFFFC000U) +#define TRDC_MBC4_MRC_DOM11_RGD_W_END_ADDR_SHIFT (14U) +/*! END_ADDR - End Address */ +#define TRDC_MBC4_MRC_DOM11_RGD_W_END_ADDR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM11_RGD_W_END_ADDR_SHIFT)) & TRDC_MBC4_MRC_DOM11_RGD_W_END_ADDR_MASK) + +#define TRDC_MBC4_MRC_DOM11_RGD_W_STRT_ADDR_MASK (0xFFFFC000U) +#define TRDC_MBC4_MRC_DOM11_RGD_W_STRT_ADDR_SHIFT (14U) +/*! STRT_ADDR - Start Address */ +#define TRDC_MBC4_MRC_DOM11_RGD_W_STRT_ADDR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM11_RGD_W_STRT_ADDR_SHIFT)) & TRDC_MBC4_MRC_DOM11_RGD_W_STRT_ADDR_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MRC_DOM11_RGD_W */ +#define TRDC_MBC4_MRC_DOM11_RGD_W_COUNT (1U) + +/* The count of TRDC_MBC4_MRC_DOM11_RGD_W */ +#define TRDC_MBC4_MRC_DOM11_RGD_W_COUNT2 (16U) + +/* The count of TRDC_MBC4_MRC_DOM11_RGD_W */ +#define TRDC_MBC4_MRC_DOM11_RGD_W_COUNT3 (2U) + +/*! @name MRC_DOM11_RGD_NSE - MRC Region Descriptor NonSecure Enable */ +/*! @{ */ + +#define TRDC_MBC4_MRC_DOM11_RGD_NSE_BIT0_MASK (0x1U) +#define TRDC_MBC4_MRC_DOM11_RGD_NSE_BIT0_SHIFT (0U) +/*! BIT0 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM11_RGD_NSE_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM11_RGD_NSE_BIT0_SHIFT)) & TRDC_MBC4_MRC_DOM11_RGD_NSE_BIT0_MASK) + +#define TRDC_MBC4_MRC_DOM11_RGD_NSE_BIT1_MASK (0x2U) +#define TRDC_MBC4_MRC_DOM11_RGD_NSE_BIT1_SHIFT (1U) +/*! BIT1 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM11_RGD_NSE_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM11_RGD_NSE_BIT1_SHIFT)) & TRDC_MBC4_MRC_DOM11_RGD_NSE_BIT1_MASK) + +#define TRDC_MBC4_MRC_DOM11_RGD_NSE_BIT2_MASK (0x4U) +#define TRDC_MBC4_MRC_DOM11_RGD_NSE_BIT2_SHIFT (2U) +/*! BIT2 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM11_RGD_NSE_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM11_RGD_NSE_BIT2_SHIFT)) & TRDC_MBC4_MRC_DOM11_RGD_NSE_BIT2_MASK) + +#define TRDC_MBC4_MRC_DOM11_RGD_NSE_BIT3_MASK (0x8U) +#define TRDC_MBC4_MRC_DOM11_RGD_NSE_BIT3_SHIFT (3U) +/*! BIT3 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM11_RGD_NSE_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM11_RGD_NSE_BIT3_SHIFT)) & TRDC_MBC4_MRC_DOM11_RGD_NSE_BIT3_MASK) + +#define TRDC_MBC4_MRC_DOM11_RGD_NSE_BIT4_MASK (0x10U) +#define TRDC_MBC4_MRC_DOM11_RGD_NSE_BIT4_SHIFT (4U) +/*! BIT4 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM11_RGD_NSE_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM11_RGD_NSE_BIT4_SHIFT)) & TRDC_MBC4_MRC_DOM11_RGD_NSE_BIT4_MASK) + +#define TRDC_MBC4_MRC_DOM11_RGD_NSE_BIT5_MASK (0x20U) +#define TRDC_MBC4_MRC_DOM11_RGD_NSE_BIT5_SHIFT (5U) +/*! BIT5 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM11_RGD_NSE_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM11_RGD_NSE_BIT5_SHIFT)) & TRDC_MBC4_MRC_DOM11_RGD_NSE_BIT5_MASK) + +#define TRDC_MBC4_MRC_DOM11_RGD_NSE_BIT6_MASK (0x40U) +#define TRDC_MBC4_MRC_DOM11_RGD_NSE_BIT6_SHIFT (6U) +/*! BIT6 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM11_RGD_NSE_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM11_RGD_NSE_BIT6_SHIFT)) & TRDC_MBC4_MRC_DOM11_RGD_NSE_BIT6_MASK) + +#define TRDC_MBC4_MRC_DOM11_RGD_NSE_BIT7_MASK (0x80U) +#define TRDC_MBC4_MRC_DOM11_RGD_NSE_BIT7_SHIFT (7U) +/*! BIT7 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM11_RGD_NSE_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM11_RGD_NSE_BIT7_SHIFT)) & TRDC_MBC4_MRC_DOM11_RGD_NSE_BIT7_MASK) + +#define TRDC_MBC4_MRC_DOM11_RGD_NSE_BIT8_MASK (0x100U) +#define TRDC_MBC4_MRC_DOM11_RGD_NSE_BIT8_SHIFT (8U) +/*! BIT8 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM11_RGD_NSE_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM11_RGD_NSE_BIT8_SHIFT)) & TRDC_MBC4_MRC_DOM11_RGD_NSE_BIT8_MASK) + +#define TRDC_MBC4_MRC_DOM11_RGD_NSE_BIT9_MASK (0x200U) +#define TRDC_MBC4_MRC_DOM11_RGD_NSE_BIT9_SHIFT (9U) +/*! BIT9 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM11_RGD_NSE_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM11_RGD_NSE_BIT9_SHIFT)) & TRDC_MBC4_MRC_DOM11_RGD_NSE_BIT9_MASK) + +#define TRDC_MBC4_MRC_DOM11_RGD_NSE_BIT10_MASK (0x400U) +#define TRDC_MBC4_MRC_DOM11_RGD_NSE_BIT10_SHIFT (10U) +/*! BIT10 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM11_RGD_NSE_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM11_RGD_NSE_BIT10_SHIFT)) & TRDC_MBC4_MRC_DOM11_RGD_NSE_BIT10_MASK) + +#define TRDC_MBC4_MRC_DOM11_RGD_NSE_BIT11_MASK (0x800U) +#define TRDC_MBC4_MRC_DOM11_RGD_NSE_BIT11_SHIFT (11U) +/*! BIT11 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM11_RGD_NSE_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM11_RGD_NSE_BIT11_SHIFT)) & TRDC_MBC4_MRC_DOM11_RGD_NSE_BIT11_MASK) + +#define TRDC_MBC4_MRC_DOM11_RGD_NSE_BIT12_MASK (0x1000U) +#define TRDC_MBC4_MRC_DOM11_RGD_NSE_BIT12_SHIFT (12U) +/*! BIT12 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM11_RGD_NSE_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM11_RGD_NSE_BIT12_SHIFT)) & TRDC_MBC4_MRC_DOM11_RGD_NSE_BIT12_MASK) + +#define TRDC_MBC4_MRC_DOM11_RGD_NSE_BIT13_MASK (0x2000U) +#define TRDC_MBC4_MRC_DOM11_RGD_NSE_BIT13_SHIFT (13U) +/*! BIT13 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM11_RGD_NSE_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM11_RGD_NSE_BIT13_SHIFT)) & TRDC_MBC4_MRC_DOM11_RGD_NSE_BIT13_MASK) + +#define TRDC_MBC4_MRC_DOM11_RGD_NSE_BIT14_MASK (0x4000U) +#define TRDC_MBC4_MRC_DOM11_RGD_NSE_BIT14_SHIFT (14U) +/*! BIT14 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM11_RGD_NSE_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM11_RGD_NSE_BIT14_SHIFT)) & TRDC_MBC4_MRC_DOM11_RGD_NSE_BIT14_MASK) + +#define TRDC_MBC4_MRC_DOM11_RGD_NSE_BIT15_MASK (0x8000U) +#define TRDC_MBC4_MRC_DOM11_RGD_NSE_BIT15_SHIFT (15U) +/*! BIT15 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM11_RGD_NSE_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM11_RGD_NSE_BIT15_SHIFT)) & TRDC_MBC4_MRC_DOM11_RGD_NSE_BIT15_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MRC_DOM11_RGD_NSE */ +#define TRDC_MBC4_MRC_DOM11_RGD_NSE_COUNT (1U) + +/*! @name MRC_DOM12_RGD_W - MRC Region Descriptor Word 0..MRC Region Descriptor Word 1 */ +/*! @{ */ + +#define TRDC_MBC4_MRC_DOM12_RGD_W_MRACSEL_MASK (0x7U) +#define TRDC_MBC4_MRC_DOM12_RGD_W_MRACSEL_SHIFT (0U) +/*! MRACSEL - Memory Region Access Control Select + * 0b000..Select MRC_GLBAC0 access control policy + * 0b001..Select MRC_GLBAC1 access control policy + * 0b010..Select MRC_GLBAC2 access control policy + * 0b011..Select MRC_GLBAC3 access control policy + * 0b100..Select MRC_GLBAC4 access control policy + * 0b101..Select MRC_GLBAC5 access control policy + * 0b110..Select MRC_GLBAC6 access control policy + * 0b111..Select MRC_GLBAC7 access control policy + */ +#define TRDC_MBC4_MRC_DOM12_RGD_W_MRACSEL(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM12_RGD_W_MRACSEL_SHIFT)) & TRDC_MBC4_MRC_DOM12_RGD_W_MRACSEL_MASK) + +#define TRDC_MBC4_MRC_DOM12_RGD_W_VLD_MASK (0x1U) +#define TRDC_MBC4_MRC_DOM12_RGD_W_VLD_SHIFT (0U) +/*! VLD - Valid */ +#define TRDC_MBC4_MRC_DOM12_RGD_W_VLD(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM12_RGD_W_VLD_SHIFT)) & TRDC_MBC4_MRC_DOM12_RGD_W_VLD_MASK) + +#define TRDC_MBC4_MRC_DOM12_RGD_W_NSE_MASK (0x10U) +#define TRDC_MBC4_MRC_DOM12_RGD_W_NSE_SHIFT (4U) +/*! NSE - NonSecure Enable + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in this register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM12_RGD_W_NSE(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM12_RGD_W_NSE_SHIFT)) & TRDC_MBC4_MRC_DOM12_RGD_W_NSE_MASK) + +#define TRDC_MBC4_MRC_DOM12_RGD_W_END_ADDR_MASK (0xFFFFC000U) +#define TRDC_MBC4_MRC_DOM12_RGD_W_END_ADDR_SHIFT (14U) +/*! END_ADDR - End Address */ +#define TRDC_MBC4_MRC_DOM12_RGD_W_END_ADDR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM12_RGD_W_END_ADDR_SHIFT)) & TRDC_MBC4_MRC_DOM12_RGD_W_END_ADDR_MASK) + +#define TRDC_MBC4_MRC_DOM12_RGD_W_STRT_ADDR_MASK (0xFFFFC000U) +#define TRDC_MBC4_MRC_DOM12_RGD_W_STRT_ADDR_SHIFT (14U) +/*! STRT_ADDR - Start Address */ +#define TRDC_MBC4_MRC_DOM12_RGD_W_STRT_ADDR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM12_RGD_W_STRT_ADDR_SHIFT)) & TRDC_MBC4_MRC_DOM12_RGD_W_STRT_ADDR_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MRC_DOM12_RGD_W */ +#define TRDC_MBC4_MRC_DOM12_RGD_W_COUNT (1U) + +/* The count of TRDC_MBC4_MRC_DOM12_RGD_W */ +#define TRDC_MBC4_MRC_DOM12_RGD_W_COUNT2 (16U) + +/* The count of TRDC_MBC4_MRC_DOM12_RGD_W */ +#define TRDC_MBC4_MRC_DOM12_RGD_W_COUNT3 (2U) + +/*! @name MRC_DOM12_RGD_NSE - MRC Region Descriptor NonSecure Enable */ +/*! @{ */ + +#define TRDC_MBC4_MRC_DOM12_RGD_NSE_BIT0_MASK (0x1U) +#define TRDC_MBC4_MRC_DOM12_RGD_NSE_BIT0_SHIFT (0U) +/*! BIT0 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM12_RGD_NSE_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM12_RGD_NSE_BIT0_SHIFT)) & TRDC_MBC4_MRC_DOM12_RGD_NSE_BIT0_MASK) + +#define TRDC_MBC4_MRC_DOM12_RGD_NSE_BIT1_MASK (0x2U) +#define TRDC_MBC4_MRC_DOM12_RGD_NSE_BIT1_SHIFT (1U) +/*! BIT1 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM12_RGD_NSE_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM12_RGD_NSE_BIT1_SHIFT)) & TRDC_MBC4_MRC_DOM12_RGD_NSE_BIT1_MASK) + +#define TRDC_MBC4_MRC_DOM12_RGD_NSE_BIT2_MASK (0x4U) +#define TRDC_MBC4_MRC_DOM12_RGD_NSE_BIT2_SHIFT (2U) +/*! BIT2 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM12_RGD_NSE_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM12_RGD_NSE_BIT2_SHIFT)) & TRDC_MBC4_MRC_DOM12_RGD_NSE_BIT2_MASK) + +#define TRDC_MBC4_MRC_DOM12_RGD_NSE_BIT3_MASK (0x8U) +#define TRDC_MBC4_MRC_DOM12_RGD_NSE_BIT3_SHIFT (3U) +/*! BIT3 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM12_RGD_NSE_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM12_RGD_NSE_BIT3_SHIFT)) & TRDC_MBC4_MRC_DOM12_RGD_NSE_BIT3_MASK) + +#define TRDC_MBC4_MRC_DOM12_RGD_NSE_BIT4_MASK (0x10U) +#define TRDC_MBC4_MRC_DOM12_RGD_NSE_BIT4_SHIFT (4U) +/*! BIT4 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM12_RGD_NSE_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM12_RGD_NSE_BIT4_SHIFT)) & TRDC_MBC4_MRC_DOM12_RGD_NSE_BIT4_MASK) + +#define TRDC_MBC4_MRC_DOM12_RGD_NSE_BIT5_MASK (0x20U) +#define TRDC_MBC4_MRC_DOM12_RGD_NSE_BIT5_SHIFT (5U) +/*! BIT5 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM12_RGD_NSE_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM12_RGD_NSE_BIT5_SHIFT)) & TRDC_MBC4_MRC_DOM12_RGD_NSE_BIT5_MASK) + +#define TRDC_MBC4_MRC_DOM12_RGD_NSE_BIT6_MASK (0x40U) +#define TRDC_MBC4_MRC_DOM12_RGD_NSE_BIT6_SHIFT (6U) +/*! BIT6 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM12_RGD_NSE_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM12_RGD_NSE_BIT6_SHIFT)) & TRDC_MBC4_MRC_DOM12_RGD_NSE_BIT6_MASK) + +#define TRDC_MBC4_MRC_DOM12_RGD_NSE_BIT7_MASK (0x80U) +#define TRDC_MBC4_MRC_DOM12_RGD_NSE_BIT7_SHIFT (7U) +/*! BIT7 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM12_RGD_NSE_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM12_RGD_NSE_BIT7_SHIFT)) & TRDC_MBC4_MRC_DOM12_RGD_NSE_BIT7_MASK) + +#define TRDC_MBC4_MRC_DOM12_RGD_NSE_BIT8_MASK (0x100U) +#define TRDC_MBC4_MRC_DOM12_RGD_NSE_BIT8_SHIFT (8U) +/*! BIT8 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM12_RGD_NSE_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM12_RGD_NSE_BIT8_SHIFT)) & TRDC_MBC4_MRC_DOM12_RGD_NSE_BIT8_MASK) + +#define TRDC_MBC4_MRC_DOM12_RGD_NSE_BIT9_MASK (0x200U) +#define TRDC_MBC4_MRC_DOM12_RGD_NSE_BIT9_SHIFT (9U) +/*! BIT9 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM12_RGD_NSE_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM12_RGD_NSE_BIT9_SHIFT)) & TRDC_MBC4_MRC_DOM12_RGD_NSE_BIT9_MASK) + +#define TRDC_MBC4_MRC_DOM12_RGD_NSE_BIT10_MASK (0x400U) +#define TRDC_MBC4_MRC_DOM12_RGD_NSE_BIT10_SHIFT (10U) +/*! BIT10 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM12_RGD_NSE_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM12_RGD_NSE_BIT10_SHIFT)) & TRDC_MBC4_MRC_DOM12_RGD_NSE_BIT10_MASK) + +#define TRDC_MBC4_MRC_DOM12_RGD_NSE_BIT11_MASK (0x800U) +#define TRDC_MBC4_MRC_DOM12_RGD_NSE_BIT11_SHIFT (11U) +/*! BIT11 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM12_RGD_NSE_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM12_RGD_NSE_BIT11_SHIFT)) & TRDC_MBC4_MRC_DOM12_RGD_NSE_BIT11_MASK) + +#define TRDC_MBC4_MRC_DOM12_RGD_NSE_BIT12_MASK (0x1000U) +#define TRDC_MBC4_MRC_DOM12_RGD_NSE_BIT12_SHIFT (12U) +/*! BIT12 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM12_RGD_NSE_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM12_RGD_NSE_BIT12_SHIFT)) & TRDC_MBC4_MRC_DOM12_RGD_NSE_BIT12_MASK) + +#define TRDC_MBC4_MRC_DOM12_RGD_NSE_BIT13_MASK (0x2000U) +#define TRDC_MBC4_MRC_DOM12_RGD_NSE_BIT13_SHIFT (13U) +/*! BIT13 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM12_RGD_NSE_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM12_RGD_NSE_BIT13_SHIFT)) & TRDC_MBC4_MRC_DOM12_RGD_NSE_BIT13_MASK) + +#define TRDC_MBC4_MRC_DOM12_RGD_NSE_BIT14_MASK (0x4000U) +#define TRDC_MBC4_MRC_DOM12_RGD_NSE_BIT14_SHIFT (14U) +/*! BIT14 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM12_RGD_NSE_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM12_RGD_NSE_BIT14_SHIFT)) & TRDC_MBC4_MRC_DOM12_RGD_NSE_BIT14_MASK) + +#define TRDC_MBC4_MRC_DOM12_RGD_NSE_BIT15_MASK (0x8000U) +#define TRDC_MBC4_MRC_DOM12_RGD_NSE_BIT15_SHIFT (15U) +/*! BIT15 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM12_RGD_NSE_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM12_RGD_NSE_BIT15_SHIFT)) & TRDC_MBC4_MRC_DOM12_RGD_NSE_BIT15_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MRC_DOM12_RGD_NSE */ +#define TRDC_MBC4_MRC_DOM12_RGD_NSE_COUNT (1U) + +/*! @name MRC_DOM13_RGD_W - MRC Region Descriptor Word 0..MRC Region Descriptor Word 1 */ +/*! @{ */ + +#define TRDC_MBC4_MRC_DOM13_RGD_W_MRACSEL_MASK (0x7U) +#define TRDC_MBC4_MRC_DOM13_RGD_W_MRACSEL_SHIFT (0U) +/*! MRACSEL - Memory Region Access Control Select + * 0b000..Select MRC_GLBAC0 access control policy + * 0b001..Select MRC_GLBAC1 access control policy + * 0b010..Select MRC_GLBAC2 access control policy + * 0b011..Select MRC_GLBAC3 access control policy + * 0b100..Select MRC_GLBAC4 access control policy + * 0b101..Select MRC_GLBAC5 access control policy + * 0b110..Select MRC_GLBAC6 access control policy + * 0b111..Select MRC_GLBAC7 access control policy + */ +#define TRDC_MBC4_MRC_DOM13_RGD_W_MRACSEL(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM13_RGD_W_MRACSEL_SHIFT)) & TRDC_MBC4_MRC_DOM13_RGD_W_MRACSEL_MASK) + +#define TRDC_MBC4_MRC_DOM13_RGD_W_VLD_MASK (0x1U) +#define TRDC_MBC4_MRC_DOM13_RGD_W_VLD_SHIFT (0U) +/*! VLD - Valid */ +#define TRDC_MBC4_MRC_DOM13_RGD_W_VLD(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM13_RGD_W_VLD_SHIFT)) & TRDC_MBC4_MRC_DOM13_RGD_W_VLD_MASK) + +#define TRDC_MBC4_MRC_DOM13_RGD_W_NSE_MASK (0x10U) +#define TRDC_MBC4_MRC_DOM13_RGD_W_NSE_SHIFT (4U) +/*! NSE - NonSecure Enable + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in this register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM13_RGD_W_NSE(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM13_RGD_W_NSE_SHIFT)) & TRDC_MBC4_MRC_DOM13_RGD_W_NSE_MASK) + +#define TRDC_MBC4_MRC_DOM13_RGD_W_END_ADDR_MASK (0xFFFFC000U) +#define TRDC_MBC4_MRC_DOM13_RGD_W_END_ADDR_SHIFT (14U) +/*! END_ADDR - End Address */ +#define TRDC_MBC4_MRC_DOM13_RGD_W_END_ADDR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM13_RGD_W_END_ADDR_SHIFT)) & TRDC_MBC4_MRC_DOM13_RGD_W_END_ADDR_MASK) + +#define TRDC_MBC4_MRC_DOM13_RGD_W_STRT_ADDR_MASK (0xFFFFC000U) +#define TRDC_MBC4_MRC_DOM13_RGD_W_STRT_ADDR_SHIFT (14U) +/*! STRT_ADDR - Start Address */ +#define TRDC_MBC4_MRC_DOM13_RGD_W_STRT_ADDR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM13_RGD_W_STRT_ADDR_SHIFT)) & TRDC_MBC4_MRC_DOM13_RGD_W_STRT_ADDR_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MRC_DOM13_RGD_W */ +#define TRDC_MBC4_MRC_DOM13_RGD_W_COUNT (1U) + +/* The count of TRDC_MBC4_MRC_DOM13_RGD_W */ +#define TRDC_MBC4_MRC_DOM13_RGD_W_COUNT2 (16U) + +/* The count of TRDC_MBC4_MRC_DOM13_RGD_W */ +#define TRDC_MBC4_MRC_DOM13_RGD_W_COUNT3 (2U) + +/*! @name MRC_DOM13_RGD_NSE - MRC Region Descriptor NonSecure Enable */ +/*! @{ */ + +#define TRDC_MBC4_MRC_DOM13_RGD_NSE_BIT0_MASK (0x1U) +#define TRDC_MBC4_MRC_DOM13_RGD_NSE_BIT0_SHIFT (0U) +/*! BIT0 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM13_RGD_NSE_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM13_RGD_NSE_BIT0_SHIFT)) & TRDC_MBC4_MRC_DOM13_RGD_NSE_BIT0_MASK) + +#define TRDC_MBC4_MRC_DOM13_RGD_NSE_BIT1_MASK (0x2U) +#define TRDC_MBC4_MRC_DOM13_RGD_NSE_BIT1_SHIFT (1U) +/*! BIT1 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM13_RGD_NSE_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM13_RGD_NSE_BIT1_SHIFT)) & TRDC_MBC4_MRC_DOM13_RGD_NSE_BIT1_MASK) + +#define TRDC_MBC4_MRC_DOM13_RGD_NSE_BIT2_MASK (0x4U) +#define TRDC_MBC4_MRC_DOM13_RGD_NSE_BIT2_SHIFT (2U) +/*! BIT2 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM13_RGD_NSE_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM13_RGD_NSE_BIT2_SHIFT)) & TRDC_MBC4_MRC_DOM13_RGD_NSE_BIT2_MASK) + +#define TRDC_MBC4_MRC_DOM13_RGD_NSE_BIT3_MASK (0x8U) +#define TRDC_MBC4_MRC_DOM13_RGD_NSE_BIT3_SHIFT (3U) +/*! BIT3 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM13_RGD_NSE_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM13_RGD_NSE_BIT3_SHIFT)) & TRDC_MBC4_MRC_DOM13_RGD_NSE_BIT3_MASK) + +#define TRDC_MBC4_MRC_DOM13_RGD_NSE_BIT4_MASK (0x10U) +#define TRDC_MBC4_MRC_DOM13_RGD_NSE_BIT4_SHIFT (4U) +/*! BIT4 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM13_RGD_NSE_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM13_RGD_NSE_BIT4_SHIFT)) & TRDC_MBC4_MRC_DOM13_RGD_NSE_BIT4_MASK) + +#define TRDC_MBC4_MRC_DOM13_RGD_NSE_BIT5_MASK (0x20U) +#define TRDC_MBC4_MRC_DOM13_RGD_NSE_BIT5_SHIFT (5U) +/*! BIT5 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM13_RGD_NSE_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM13_RGD_NSE_BIT5_SHIFT)) & TRDC_MBC4_MRC_DOM13_RGD_NSE_BIT5_MASK) + +#define TRDC_MBC4_MRC_DOM13_RGD_NSE_BIT6_MASK (0x40U) +#define TRDC_MBC4_MRC_DOM13_RGD_NSE_BIT6_SHIFT (6U) +/*! BIT6 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM13_RGD_NSE_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM13_RGD_NSE_BIT6_SHIFT)) & TRDC_MBC4_MRC_DOM13_RGD_NSE_BIT6_MASK) + +#define TRDC_MBC4_MRC_DOM13_RGD_NSE_BIT7_MASK (0x80U) +#define TRDC_MBC4_MRC_DOM13_RGD_NSE_BIT7_SHIFT (7U) +/*! BIT7 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM13_RGD_NSE_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM13_RGD_NSE_BIT7_SHIFT)) & TRDC_MBC4_MRC_DOM13_RGD_NSE_BIT7_MASK) + +#define TRDC_MBC4_MRC_DOM13_RGD_NSE_BIT8_MASK (0x100U) +#define TRDC_MBC4_MRC_DOM13_RGD_NSE_BIT8_SHIFT (8U) +/*! BIT8 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM13_RGD_NSE_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM13_RGD_NSE_BIT8_SHIFT)) & TRDC_MBC4_MRC_DOM13_RGD_NSE_BIT8_MASK) + +#define TRDC_MBC4_MRC_DOM13_RGD_NSE_BIT9_MASK (0x200U) +#define TRDC_MBC4_MRC_DOM13_RGD_NSE_BIT9_SHIFT (9U) +/*! BIT9 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM13_RGD_NSE_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM13_RGD_NSE_BIT9_SHIFT)) & TRDC_MBC4_MRC_DOM13_RGD_NSE_BIT9_MASK) + +#define TRDC_MBC4_MRC_DOM13_RGD_NSE_BIT10_MASK (0x400U) +#define TRDC_MBC4_MRC_DOM13_RGD_NSE_BIT10_SHIFT (10U) +/*! BIT10 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM13_RGD_NSE_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM13_RGD_NSE_BIT10_SHIFT)) & TRDC_MBC4_MRC_DOM13_RGD_NSE_BIT10_MASK) + +#define TRDC_MBC4_MRC_DOM13_RGD_NSE_BIT11_MASK (0x800U) +#define TRDC_MBC4_MRC_DOM13_RGD_NSE_BIT11_SHIFT (11U) +/*! BIT11 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM13_RGD_NSE_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM13_RGD_NSE_BIT11_SHIFT)) & TRDC_MBC4_MRC_DOM13_RGD_NSE_BIT11_MASK) + +#define TRDC_MBC4_MRC_DOM13_RGD_NSE_BIT12_MASK (0x1000U) +#define TRDC_MBC4_MRC_DOM13_RGD_NSE_BIT12_SHIFT (12U) +/*! BIT12 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM13_RGD_NSE_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM13_RGD_NSE_BIT12_SHIFT)) & TRDC_MBC4_MRC_DOM13_RGD_NSE_BIT12_MASK) + +#define TRDC_MBC4_MRC_DOM13_RGD_NSE_BIT13_MASK (0x2000U) +#define TRDC_MBC4_MRC_DOM13_RGD_NSE_BIT13_SHIFT (13U) +/*! BIT13 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM13_RGD_NSE_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM13_RGD_NSE_BIT13_SHIFT)) & TRDC_MBC4_MRC_DOM13_RGD_NSE_BIT13_MASK) + +#define TRDC_MBC4_MRC_DOM13_RGD_NSE_BIT14_MASK (0x4000U) +#define TRDC_MBC4_MRC_DOM13_RGD_NSE_BIT14_SHIFT (14U) +/*! BIT14 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM13_RGD_NSE_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM13_RGD_NSE_BIT14_SHIFT)) & TRDC_MBC4_MRC_DOM13_RGD_NSE_BIT14_MASK) + +#define TRDC_MBC4_MRC_DOM13_RGD_NSE_BIT15_MASK (0x8000U) +#define TRDC_MBC4_MRC_DOM13_RGD_NSE_BIT15_SHIFT (15U) +/*! BIT15 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM13_RGD_NSE_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM13_RGD_NSE_BIT15_SHIFT)) & TRDC_MBC4_MRC_DOM13_RGD_NSE_BIT15_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MRC_DOM13_RGD_NSE */ +#define TRDC_MBC4_MRC_DOM13_RGD_NSE_COUNT (1U) + +/*! @name MRC_DOM14_RGD_W - MRC Region Descriptor Word 0..MRC Region Descriptor Word 1 */ +/*! @{ */ + +#define TRDC_MBC4_MRC_DOM14_RGD_W_MRACSEL_MASK (0x7U) +#define TRDC_MBC4_MRC_DOM14_RGD_W_MRACSEL_SHIFT (0U) +/*! MRACSEL - Memory Region Access Control Select + * 0b000..Select MRC_GLBAC0 access control policy + * 0b001..Select MRC_GLBAC1 access control policy + * 0b010..Select MRC_GLBAC2 access control policy + * 0b011..Select MRC_GLBAC3 access control policy + * 0b100..Select MRC_GLBAC4 access control policy + * 0b101..Select MRC_GLBAC5 access control policy + * 0b110..Select MRC_GLBAC6 access control policy + * 0b111..Select MRC_GLBAC7 access control policy + */ +#define TRDC_MBC4_MRC_DOM14_RGD_W_MRACSEL(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM14_RGD_W_MRACSEL_SHIFT)) & TRDC_MBC4_MRC_DOM14_RGD_W_MRACSEL_MASK) + +#define TRDC_MBC4_MRC_DOM14_RGD_W_VLD_MASK (0x1U) +#define TRDC_MBC4_MRC_DOM14_RGD_W_VLD_SHIFT (0U) +/*! VLD - Valid */ +#define TRDC_MBC4_MRC_DOM14_RGD_W_VLD(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM14_RGD_W_VLD_SHIFT)) & TRDC_MBC4_MRC_DOM14_RGD_W_VLD_MASK) + +#define TRDC_MBC4_MRC_DOM14_RGD_W_NSE_MASK (0x10U) +#define TRDC_MBC4_MRC_DOM14_RGD_W_NSE_SHIFT (4U) +/*! NSE - NonSecure Enable + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in this register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM14_RGD_W_NSE(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM14_RGD_W_NSE_SHIFT)) & TRDC_MBC4_MRC_DOM14_RGD_W_NSE_MASK) + +#define TRDC_MBC4_MRC_DOM14_RGD_W_END_ADDR_MASK (0xFFFFC000U) +#define TRDC_MBC4_MRC_DOM14_RGD_W_END_ADDR_SHIFT (14U) +/*! END_ADDR - End Address */ +#define TRDC_MBC4_MRC_DOM14_RGD_W_END_ADDR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM14_RGD_W_END_ADDR_SHIFT)) & TRDC_MBC4_MRC_DOM14_RGD_W_END_ADDR_MASK) + +#define TRDC_MBC4_MRC_DOM14_RGD_W_STRT_ADDR_MASK (0xFFFFC000U) +#define TRDC_MBC4_MRC_DOM14_RGD_W_STRT_ADDR_SHIFT (14U) +/*! STRT_ADDR - Start Address */ +#define TRDC_MBC4_MRC_DOM14_RGD_W_STRT_ADDR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM14_RGD_W_STRT_ADDR_SHIFT)) & TRDC_MBC4_MRC_DOM14_RGD_W_STRT_ADDR_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MRC_DOM14_RGD_W */ +#define TRDC_MBC4_MRC_DOM14_RGD_W_COUNT (1U) + +/* The count of TRDC_MBC4_MRC_DOM14_RGD_W */ +#define TRDC_MBC4_MRC_DOM14_RGD_W_COUNT2 (16U) + +/* The count of TRDC_MBC4_MRC_DOM14_RGD_W */ +#define TRDC_MBC4_MRC_DOM14_RGD_W_COUNT3 (2U) + +/*! @name MRC_DOM14_RGD_NSE - MRC Region Descriptor NonSecure Enable */ +/*! @{ */ + +#define TRDC_MBC4_MRC_DOM14_RGD_NSE_BIT0_MASK (0x1U) +#define TRDC_MBC4_MRC_DOM14_RGD_NSE_BIT0_SHIFT (0U) +/*! BIT0 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM14_RGD_NSE_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM14_RGD_NSE_BIT0_SHIFT)) & TRDC_MBC4_MRC_DOM14_RGD_NSE_BIT0_MASK) + +#define TRDC_MBC4_MRC_DOM14_RGD_NSE_BIT1_MASK (0x2U) +#define TRDC_MBC4_MRC_DOM14_RGD_NSE_BIT1_SHIFT (1U) +/*! BIT1 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM14_RGD_NSE_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM14_RGD_NSE_BIT1_SHIFT)) & TRDC_MBC4_MRC_DOM14_RGD_NSE_BIT1_MASK) + +#define TRDC_MBC4_MRC_DOM14_RGD_NSE_BIT2_MASK (0x4U) +#define TRDC_MBC4_MRC_DOM14_RGD_NSE_BIT2_SHIFT (2U) +/*! BIT2 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM14_RGD_NSE_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM14_RGD_NSE_BIT2_SHIFT)) & TRDC_MBC4_MRC_DOM14_RGD_NSE_BIT2_MASK) + +#define TRDC_MBC4_MRC_DOM14_RGD_NSE_BIT3_MASK (0x8U) +#define TRDC_MBC4_MRC_DOM14_RGD_NSE_BIT3_SHIFT (3U) +/*! BIT3 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM14_RGD_NSE_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM14_RGD_NSE_BIT3_SHIFT)) & TRDC_MBC4_MRC_DOM14_RGD_NSE_BIT3_MASK) + +#define TRDC_MBC4_MRC_DOM14_RGD_NSE_BIT4_MASK (0x10U) +#define TRDC_MBC4_MRC_DOM14_RGD_NSE_BIT4_SHIFT (4U) +/*! BIT4 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM14_RGD_NSE_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM14_RGD_NSE_BIT4_SHIFT)) & TRDC_MBC4_MRC_DOM14_RGD_NSE_BIT4_MASK) + +#define TRDC_MBC4_MRC_DOM14_RGD_NSE_BIT5_MASK (0x20U) +#define TRDC_MBC4_MRC_DOM14_RGD_NSE_BIT5_SHIFT (5U) +/*! BIT5 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM14_RGD_NSE_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM14_RGD_NSE_BIT5_SHIFT)) & TRDC_MBC4_MRC_DOM14_RGD_NSE_BIT5_MASK) + +#define TRDC_MBC4_MRC_DOM14_RGD_NSE_BIT6_MASK (0x40U) +#define TRDC_MBC4_MRC_DOM14_RGD_NSE_BIT6_SHIFT (6U) +/*! BIT6 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM14_RGD_NSE_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM14_RGD_NSE_BIT6_SHIFT)) & TRDC_MBC4_MRC_DOM14_RGD_NSE_BIT6_MASK) + +#define TRDC_MBC4_MRC_DOM14_RGD_NSE_BIT7_MASK (0x80U) +#define TRDC_MBC4_MRC_DOM14_RGD_NSE_BIT7_SHIFT (7U) +/*! BIT7 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM14_RGD_NSE_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM14_RGD_NSE_BIT7_SHIFT)) & TRDC_MBC4_MRC_DOM14_RGD_NSE_BIT7_MASK) + +#define TRDC_MBC4_MRC_DOM14_RGD_NSE_BIT8_MASK (0x100U) +#define TRDC_MBC4_MRC_DOM14_RGD_NSE_BIT8_SHIFT (8U) +/*! BIT8 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM14_RGD_NSE_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM14_RGD_NSE_BIT8_SHIFT)) & TRDC_MBC4_MRC_DOM14_RGD_NSE_BIT8_MASK) + +#define TRDC_MBC4_MRC_DOM14_RGD_NSE_BIT9_MASK (0x200U) +#define TRDC_MBC4_MRC_DOM14_RGD_NSE_BIT9_SHIFT (9U) +/*! BIT9 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM14_RGD_NSE_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM14_RGD_NSE_BIT9_SHIFT)) & TRDC_MBC4_MRC_DOM14_RGD_NSE_BIT9_MASK) + +#define TRDC_MBC4_MRC_DOM14_RGD_NSE_BIT10_MASK (0x400U) +#define TRDC_MBC4_MRC_DOM14_RGD_NSE_BIT10_SHIFT (10U) +/*! BIT10 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM14_RGD_NSE_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM14_RGD_NSE_BIT10_SHIFT)) & TRDC_MBC4_MRC_DOM14_RGD_NSE_BIT10_MASK) + +#define TRDC_MBC4_MRC_DOM14_RGD_NSE_BIT11_MASK (0x800U) +#define TRDC_MBC4_MRC_DOM14_RGD_NSE_BIT11_SHIFT (11U) +/*! BIT11 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM14_RGD_NSE_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM14_RGD_NSE_BIT11_SHIFT)) & TRDC_MBC4_MRC_DOM14_RGD_NSE_BIT11_MASK) + +#define TRDC_MBC4_MRC_DOM14_RGD_NSE_BIT12_MASK (0x1000U) +#define TRDC_MBC4_MRC_DOM14_RGD_NSE_BIT12_SHIFT (12U) +/*! BIT12 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM14_RGD_NSE_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM14_RGD_NSE_BIT12_SHIFT)) & TRDC_MBC4_MRC_DOM14_RGD_NSE_BIT12_MASK) + +#define TRDC_MBC4_MRC_DOM14_RGD_NSE_BIT13_MASK (0x2000U) +#define TRDC_MBC4_MRC_DOM14_RGD_NSE_BIT13_SHIFT (13U) +/*! BIT13 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM14_RGD_NSE_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM14_RGD_NSE_BIT13_SHIFT)) & TRDC_MBC4_MRC_DOM14_RGD_NSE_BIT13_MASK) + +#define TRDC_MBC4_MRC_DOM14_RGD_NSE_BIT14_MASK (0x4000U) +#define TRDC_MBC4_MRC_DOM14_RGD_NSE_BIT14_SHIFT (14U) +/*! BIT14 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM14_RGD_NSE_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM14_RGD_NSE_BIT14_SHIFT)) & TRDC_MBC4_MRC_DOM14_RGD_NSE_BIT14_MASK) + +#define TRDC_MBC4_MRC_DOM14_RGD_NSE_BIT15_MASK (0x8000U) +#define TRDC_MBC4_MRC_DOM14_RGD_NSE_BIT15_SHIFT (15U) +/*! BIT15 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM14_RGD_NSE_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM14_RGD_NSE_BIT15_SHIFT)) & TRDC_MBC4_MRC_DOM14_RGD_NSE_BIT15_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MRC_DOM14_RGD_NSE */ +#define TRDC_MBC4_MRC_DOM14_RGD_NSE_COUNT (1U) + +/*! @name MRC_DOM15_RGD_W - MRC Region Descriptor Word 0..MRC Region Descriptor Word 1 */ +/*! @{ */ + +#define TRDC_MBC4_MRC_DOM15_RGD_W_MRACSEL_MASK (0x7U) +#define TRDC_MBC4_MRC_DOM15_RGD_W_MRACSEL_SHIFT (0U) +/*! MRACSEL - Memory Region Access Control Select + * 0b000..Select MRC_GLBAC0 access control policy + * 0b001..Select MRC_GLBAC1 access control policy + * 0b010..Select MRC_GLBAC2 access control policy + * 0b011..Select MRC_GLBAC3 access control policy + * 0b100..Select MRC_GLBAC4 access control policy + * 0b101..Select MRC_GLBAC5 access control policy + * 0b110..Select MRC_GLBAC6 access control policy + * 0b111..Select MRC_GLBAC7 access control policy + */ +#define TRDC_MBC4_MRC_DOM15_RGD_W_MRACSEL(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM15_RGD_W_MRACSEL_SHIFT)) & TRDC_MBC4_MRC_DOM15_RGD_W_MRACSEL_MASK) + +#define TRDC_MBC4_MRC_DOM15_RGD_W_VLD_MASK (0x1U) +#define TRDC_MBC4_MRC_DOM15_RGD_W_VLD_SHIFT (0U) +/*! VLD - Valid */ +#define TRDC_MBC4_MRC_DOM15_RGD_W_VLD(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM15_RGD_W_VLD_SHIFT)) & TRDC_MBC4_MRC_DOM15_RGD_W_VLD_MASK) + +#define TRDC_MBC4_MRC_DOM15_RGD_W_NSE_MASK (0x10U) +#define TRDC_MBC4_MRC_DOM15_RGD_W_NSE_SHIFT (4U) +/*! NSE - NonSecure Enable + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in this register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM15_RGD_W_NSE(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM15_RGD_W_NSE_SHIFT)) & TRDC_MBC4_MRC_DOM15_RGD_W_NSE_MASK) + +#define TRDC_MBC4_MRC_DOM15_RGD_W_END_ADDR_MASK (0xFFFFC000U) +#define TRDC_MBC4_MRC_DOM15_RGD_W_END_ADDR_SHIFT (14U) +/*! END_ADDR - End Address */ +#define TRDC_MBC4_MRC_DOM15_RGD_W_END_ADDR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM15_RGD_W_END_ADDR_SHIFT)) & TRDC_MBC4_MRC_DOM15_RGD_W_END_ADDR_MASK) + +#define TRDC_MBC4_MRC_DOM15_RGD_W_STRT_ADDR_MASK (0xFFFFC000U) +#define TRDC_MBC4_MRC_DOM15_RGD_W_STRT_ADDR_SHIFT (14U) +/*! STRT_ADDR - Start Address */ +#define TRDC_MBC4_MRC_DOM15_RGD_W_STRT_ADDR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM15_RGD_W_STRT_ADDR_SHIFT)) & TRDC_MBC4_MRC_DOM15_RGD_W_STRT_ADDR_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MRC_DOM15_RGD_W */ +#define TRDC_MBC4_MRC_DOM15_RGD_W_COUNT (1U) + +/* The count of TRDC_MBC4_MRC_DOM15_RGD_W */ +#define TRDC_MBC4_MRC_DOM15_RGD_W_COUNT2 (16U) + +/* The count of TRDC_MBC4_MRC_DOM15_RGD_W */ +#define TRDC_MBC4_MRC_DOM15_RGD_W_COUNT3 (2U) + +/*! @name MRC_DOM15_RGD_NSE - MRC Region Descriptor NonSecure Enable */ +/*! @{ */ + +#define TRDC_MBC4_MRC_DOM15_RGD_NSE_BIT0_MASK (0x1U) +#define TRDC_MBC4_MRC_DOM15_RGD_NSE_BIT0_SHIFT (0U) +/*! BIT0 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM15_RGD_NSE_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM15_RGD_NSE_BIT0_SHIFT)) & TRDC_MBC4_MRC_DOM15_RGD_NSE_BIT0_MASK) + +#define TRDC_MBC4_MRC_DOM15_RGD_NSE_BIT1_MASK (0x2U) +#define TRDC_MBC4_MRC_DOM15_RGD_NSE_BIT1_SHIFT (1U) +/*! BIT1 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM15_RGD_NSE_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM15_RGD_NSE_BIT1_SHIFT)) & TRDC_MBC4_MRC_DOM15_RGD_NSE_BIT1_MASK) + +#define TRDC_MBC4_MRC_DOM15_RGD_NSE_BIT2_MASK (0x4U) +#define TRDC_MBC4_MRC_DOM15_RGD_NSE_BIT2_SHIFT (2U) +/*! BIT2 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM15_RGD_NSE_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM15_RGD_NSE_BIT2_SHIFT)) & TRDC_MBC4_MRC_DOM15_RGD_NSE_BIT2_MASK) + +#define TRDC_MBC4_MRC_DOM15_RGD_NSE_BIT3_MASK (0x8U) +#define TRDC_MBC4_MRC_DOM15_RGD_NSE_BIT3_SHIFT (3U) +/*! BIT3 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM15_RGD_NSE_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM15_RGD_NSE_BIT3_SHIFT)) & TRDC_MBC4_MRC_DOM15_RGD_NSE_BIT3_MASK) + +#define TRDC_MBC4_MRC_DOM15_RGD_NSE_BIT4_MASK (0x10U) +#define TRDC_MBC4_MRC_DOM15_RGD_NSE_BIT4_SHIFT (4U) +/*! BIT4 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM15_RGD_NSE_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM15_RGD_NSE_BIT4_SHIFT)) & TRDC_MBC4_MRC_DOM15_RGD_NSE_BIT4_MASK) + +#define TRDC_MBC4_MRC_DOM15_RGD_NSE_BIT5_MASK (0x20U) +#define TRDC_MBC4_MRC_DOM15_RGD_NSE_BIT5_SHIFT (5U) +/*! BIT5 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM15_RGD_NSE_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM15_RGD_NSE_BIT5_SHIFT)) & TRDC_MBC4_MRC_DOM15_RGD_NSE_BIT5_MASK) + +#define TRDC_MBC4_MRC_DOM15_RGD_NSE_BIT6_MASK (0x40U) +#define TRDC_MBC4_MRC_DOM15_RGD_NSE_BIT6_SHIFT (6U) +/*! BIT6 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM15_RGD_NSE_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM15_RGD_NSE_BIT6_SHIFT)) & TRDC_MBC4_MRC_DOM15_RGD_NSE_BIT6_MASK) + +#define TRDC_MBC4_MRC_DOM15_RGD_NSE_BIT7_MASK (0x80U) +#define TRDC_MBC4_MRC_DOM15_RGD_NSE_BIT7_SHIFT (7U) +/*! BIT7 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM15_RGD_NSE_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM15_RGD_NSE_BIT7_SHIFT)) & TRDC_MBC4_MRC_DOM15_RGD_NSE_BIT7_MASK) + +#define TRDC_MBC4_MRC_DOM15_RGD_NSE_BIT8_MASK (0x100U) +#define TRDC_MBC4_MRC_DOM15_RGD_NSE_BIT8_SHIFT (8U) +/*! BIT8 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM15_RGD_NSE_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM15_RGD_NSE_BIT8_SHIFT)) & TRDC_MBC4_MRC_DOM15_RGD_NSE_BIT8_MASK) + +#define TRDC_MBC4_MRC_DOM15_RGD_NSE_BIT9_MASK (0x200U) +#define TRDC_MBC4_MRC_DOM15_RGD_NSE_BIT9_SHIFT (9U) +/*! BIT9 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM15_RGD_NSE_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM15_RGD_NSE_BIT9_SHIFT)) & TRDC_MBC4_MRC_DOM15_RGD_NSE_BIT9_MASK) + +#define TRDC_MBC4_MRC_DOM15_RGD_NSE_BIT10_MASK (0x400U) +#define TRDC_MBC4_MRC_DOM15_RGD_NSE_BIT10_SHIFT (10U) +/*! BIT10 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM15_RGD_NSE_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM15_RGD_NSE_BIT10_SHIFT)) & TRDC_MBC4_MRC_DOM15_RGD_NSE_BIT10_MASK) + +#define TRDC_MBC4_MRC_DOM15_RGD_NSE_BIT11_MASK (0x800U) +#define TRDC_MBC4_MRC_DOM15_RGD_NSE_BIT11_SHIFT (11U) +/*! BIT11 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM15_RGD_NSE_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM15_RGD_NSE_BIT11_SHIFT)) & TRDC_MBC4_MRC_DOM15_RGD_NSE_BIT11_MASK) + +#define TRDC_MBC4_MRC_DOM15_RGD_NSE_BIT12_MASK (0x1000U) +#define TRDC_MBC4_MRC_DOM15_RGD_NSE_BIT12_SHIFT (12U) +/*! BIT12 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM15_RGD_NSE_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM15_RGD_NSE_BIT12_SHIFT)) & TRDC_MBC4_MRC_DOM15_RGD_NSE_BIT12_MASK) + +#define TRDC_MBC4_MRC_DOM15_RGD_NSE_BIT13_MASK (0x2000U) +#define TRDC_MBC4_MRC_DOM15_RGD_NSE_BIT13_SHIFT (13U) +/*! BIT13 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM15_RGD_NSE_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM15_RGD_NSE_BIT13_SHIFT)) & TRDC_MBC4_MRC_DOM15_RGD_NSE_BIT13_MASK) + +#define TRDC_MBC4_MRC_DOM15_RGD_NSE_BIT14_MASK (0x4000U) +#define TRDC_MBC4_MRC_DOM15_RGD_NSE_BIT14_SHIFT (14U) +/*! BIT14 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM15_RGD_NSE_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM15_RGD_NSE_BIT14_SHIFT)) & TRDC_MBC4_MRC_DOM15_RGD_NSE_BIT14_MASK) + +#define TRDC_MBC4_MRC_DOM15_RGD_NSE_BIT15_MASK (0x8000U) +#define TRDC_MBC4_MRC_DOM15_RGD_NSE_BIT15_SHIFT (15U) +/*! BIT15 - Bit n NonSecure Enable [n = 0 - 15] + * 0b0..Secure accesses to region r are based on corresponding MRACSEL field in this register + * (MRCm_DOMd_RGDr_Ww[MRACSEL]), nonsecure accesses to region r are not allowed. + * 0b1..Secure and nonsecure accesses to region r are based on corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]). + */ +#define TRDC_MBC4_MRC_DOM15_RGD_NSE_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC4_MRC_DOM15_RGD_NSE_BIT15_SHIFT)) & TRDC_MBC4_MRC_DOM15_RGD_NSE_BIT15_MASK) +/*! @} */ + +/* The count of TRDC_MBC4_MRC_DOM15_RGD_NSE */ +#define TRDC_MBC4_MRC_DOM15_RGD_NSE_COUNT (1U) + + +/*! + * @} + */ /* end of group TRDC_MBC4_Register_Masks */ + + +/* TRDC_MBC4 - Peripheral instance base addresses */ +/** Peripheral TRDC4 base address */ +#define TRDC4_BASE (0x49010000u) +/** Peripheral TRDC4 base pointer */ +#define TRDC4 ((TRDC_MBC4_Type *)TRDC4_BASE) +/** Array initializer of TRDC_MBC4 peripheral base addresses */ +#define TRDC_MBC4_BASE_ADDRS { 0u, 0u, 0u, 0u, TRDC4_BASE } +/** Array initializer of TRDC_MBC4 peripheral base pointers */ +#define TRDC_MBC4_BASE_PTRS { (TRDC_MBC4_Type *)0u, (TRDC_MBC4_Type *)0u, (TRDC_MBC4_Type *)0u, (TRDC_MBC4_Type *)0u, TRDC4 } + +/*! + * @} + */ /* end of group TRDC_MBC4_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- TRGMUX Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup TRGMUX_Peripheral_Access_Layer TRGMUX Peripheral Access Layer + * @{ + */ + +/** TRGMUX - Register Layout Typedef */ +typedef struct { + __IO uint32_t REG0; /**< TRGMUX REG0, offset: 0x0 */ +} TRGMUX_Type; + +/* ---------------------------------------------------------------------------- + -- TRGMUX Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup TRGMUX_Register_Masks TRGMUX Register Masks + * @{ + */ + +/*! @name REG0 - TRGMUX REG0 */ +/*! @{ */ + +#define TRGMUX_REG0_SEL0_MASK (0xFU) +#define TRGMUX_REG0_SEL0_SHIFT (0U) +/*! SEL0 - TRGMUX Source Select 0 */ +#define TRGMUX_REG0_SEL0(x) (((uint32_t)(((uint32_t)(x)) << TRGMUX_REG0_SEL0_SHIFT)) & TRGMUX_REG0_SEL0_MASK) + +#define TRGMUX_REG0_SEL1_MASK (0xF00U) +#define TRGMUX_REG0_SEL1_SHIFT (8U) +/*! SEL1 - TRGMUX Source Select 1 */ +#define TRGMUX_REG0_SEL1(x) (((uint32_t)(((uint32_t)(x)) << TRGMUX_REG0_SEL1_SHIFT)) & TRGMUX_REG0_SEL1_MASK) + +#define TRGMUX_REG0_LK_MASK (0x80000000U) +#define TRGMUX_REG0_LK_SHIFT (31U) +/*! LK - TRGMUX Register Lock + * 0b0..Register is writable + * 0b1..Register is not writable until the next system reset + */ +#define TRGMUX_REG0_LK(x) (((uint32_t)(((uint32_t)(x)) << TRGMUX_REG0_LK_SHIFT)) & TRGMUX_REG0_LK_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group TRGMUX_Register_Masks */ + + +/* TRGMUX - Peripheral instance base addresses */ +/** Peripheral TRGMUX base address */ +#define TRGMUX_BASE (0x44531000u) +/** Peripheral TRGMUX base pointer */ +#define TRGMUX ((TRGMUX_Type *)TRGMUX_BASE) +/** Array initializer of TRGMUX peripheral base addresses */ +#define TRGMUX_BASE_ADDRS { TRGMUX_BASE } +/** Array initializer of TRGMUX peripheral base pointers */ +#define TRGMUX_BASE_PTRS { TRGMUX } + +/*! + * @} + */ /* end of group TRGMUX_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- TSTMR Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup TSTMR_Peripheral_Access_Layer TSTMR Peripheral Access Layer + * @{ + */ + +/** TSTMR - Register Layout Typedef */ +typedef struct { + __I uint32_t L; /**< Timestamp Timer Low, offset: 0x0 */ + __I uint32_t H; /**< Timestamp Timer High, offset: 0x4 */ +} TSTMR_Type; + +/* ---------------------------------------------------------------------------- + -- TSTMR Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup TSTMR_Register_Masks TSTMR Register Masks + * @{ + */ + +/*! @name L - Timestamp Timer Low */ +/*! @{ */ + +#define TSTMR_L_VALUE_MASK (0xFFFFFFFFU) +#define TSTMR_L_VALUE_SHIFT (0U) +/*! VALUE - Timestamp Timer Low */ +#define TSTMR_L_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TSTMR_L_VALUE_SHIFT)) & TSTMR_L_VALUE_MASK) +/*! @} */ + +/*! @name H - Timestamp Timer High */ +/*! @{ */ + +#define TSTMR_H_VALUE_MASK (0xFFFFFFU) +#define TSTMR_H_VALUE_SHIFT (0U) +/*! VALUE - Timestamp Timer High */ +#define TSTMR_H_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TSTMR_H_VALUE_SHIFT)) & TSTMR_H_VALUE_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group TSTMR_Register_Masks */ + + +/* TSTMR - Peripheral instance base addresses */ +/** Peripheral TSTMR1__TSTMRA base address */ +#define TSTMR1__TSTMRA_BASE (0x442C0000u) +/** Peripheral TSTMR1__TSTMRA base pointer */ +#define TSTMR1__TSTMRA ((TSTMR_Type *)TSTMR1__TSTMRA_BASE) +/** Peripheral TSTMR2__TSTMRA base address */ +#define TSTMR2__TSTMRA_BASE (0x42480000u) +/** Peripheral TSTMR2__TSTMRA base pointer */ +#define TSTMR2__TSTMRA ((TSTMR_Type *)TSTMR2__TSTMRA_BASE) +/** Array initializer of TSTMR peripheral base addresses */ +#define TSTMR_BASE_ADDRS { TSTMR1__TSTMRA_BASE, TSTMR2__TSTMRA_BASE } +/** Array initializer of TSTMR peripheral base pointers */ +#define TSTMR_BASE_PTRS { TSTMR1__TSTMRA, TSTMR2__TSTMRA } +/* Extra definition */ +#define TSTMR_CLOCK_FREQUENCY_MHZ (24U) + + +/*! + * @} + */ /* end of group TSTMR_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- USB Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USB_Peripheral_Access_Layer USB Peripheral Access Layer + * @{ + */ + +/** USB - Register Layout Typedef */ +typedef struct { + __I uint32_t ID; /**< Identification, offset: 0x0 */ + __I uint32_t HWGENERAL; /**< Hardware General, offset: 0x4 */ + __I uint32_t HWHOST; /**< Host Hardware Parameters, offset: 0x8 */ + __I uint32_t HWDEVICE; /**< Device Hardware Parameters, offset: 0xC */ + __I uint32_t HWTXBUF; /**< TX Buffer Hardware Parameters, offset: 0x10 */ + __I uint32_t HWRXBUF; /**< RX Buffer Hardware Parameters, offset: 0x14 */ + uint8_t RESERVED_0[104]; + __IO uint32_t GPTIMER0LD; /**< General Purpose Timer #0 Load, offset: 0x80 */ + __IO uint32_t GPTIMER0CTRL; /**< General Purpose Timer #0 Controller, offset: 0x84 */ + __IO uint32_t GPTIMER1LD; /**< General Purpose Timer #1 Load, offset: 0x88 */ + __IO uint32_t GPTIMER1CTRL; /**< General Purpose Timer #1 Controller, offset: 0x8C */ + __IO uint32_t SBUSCFG; /**< System Bus Config, offset: 0x90 */ + uint8_t RESERVED_1[108]; + __I uint8_t CAPLENGTH; /**< Capability Registers Length, offset: 0x100 */ + uint8_t RESERVED_2[1]; + __I uint16_t HCIVERSION; /**< Host Controller Interface Version, offset: 0x102 */ + __I uint32_t HCSPARAMS; /**< Host Controller Structural Parameters, offset: 0x104 */ + __I uint32_t HCCPARAMS; /**< Host Controller Capability Parameters, offset: 0x108 */ + uint8_t RESERVED_3[20]; + __I uint16_t DCIVERSION; /**< Device Controller Interface Version, offset: 0x120 */ + uint8_t RESERVED_4[2]; + __I uint32_t DCCPARAMS; /**< Device Controller Capability Parameters, offset: 0x124 */ + uint8_t RESERVED_5[24]; + __IO uint32_t USBCMD; /**< USB Command, offset: 0x140 */ + __IO uint32_t USBSTS; /**< USB Status, offset: 0x144 */ + __IO uint32_t USBINTR; /**< Interrupt Enable, offset: 0x148 */ + __IO uint32_t FRINDEX; /**< USB Frame Index, offset: 0x14C */ + uint8_t RESERVED_6[4]; + union { /* offset: 0x154 */ + struct { /* offset: 0x154 */ + __IO uint32_t DEVICEADDR; /**< Device Address, offset: 0x154 */ + __IO uint32_t ENDPTLISTADDR; /**< Endpoint List Address, offset: 0x158 */ + } DEVICE; + struct { /* offset: 0x154 */ + __IO uint32_t PERIODICLISTBASE; /**< Frame List Base Address, offset: 0x154 */ + __IO uint32_t ASYNCLISTADDR; /**< Next Asynch. Address, offset: 0x158 */ + } HOST; + }; + uint8_t RESERVED_7[4]; + __IO uint32_t BURSTSIZE; /**< Programmable Burst Size, offset: 0x160 */ + __IO uint32_t TXFILLTUNING; /**< TX FIFO Fill Tuning, offset: 0x164 */ + uint8_t RESERVED_8[16]; + __IO uint32_t ENDPTNAK; /**< Endpoint NAK, offset: 0x178 */ + __IO uint32_t ENDPTNAKEN; /**< Endpoint NAK Enable, offset: 0x17C */ + __I uint32_t CONFIGFLAG; /**< Configure Flag, offset: 0x180 */ + __IO uint32_t PORTSC1; /**< Port Status & Control, offset: 0x184 */ + uint8_t RESERVED_9[28]; + __IO uint32_t OTGSC; /**< On-The-Go Status & control, offset: 0x1A4 */ + __IO uint32_t USBMODE; /**< USB Device Mode, offset: 0x1A8 */ + __IO uint32_t ENDPTSETUPSTAT; /**< Endpoint Setup Status, offset: 0x1AC */ + __IO uint32_t ENDPTPRIME; /**< Endpoint Prime, offset: 0x1B0 */ + __IO uint32_t ENDPTFLUSH; /**< Endpoint Flush, offset: 0x1B4 */ + __I uint32_t ENDPTSTAT; /**< Endpoint Status, offset: 0x1B8 */ + __IO uint32_t ENDPTCOMPLETE; /**< Endpoint Complete, offset: 0x1BC */ + __IO uint32_t ENDPTCTRL0; /**< Endpoint Control0, offset: 0x1C0 */ + __IO uint32_t ENDPTCTRL1; /**< Endpoint Control 1, offset: 0x1C4 */ + __IO uint32_t ENDPTCTRL2; /**< Endpoint Control 2, offset: 0x1C8 */ + __IO uint32_t ENDPTCTRL3; /**< Endpoint Control 3, offset: 0x1CC */ + __IO uint32_t ENDPTCTRL4; /**< Endpoint Control 4, offset: 0x1D0 */ + __IO uint32_t ENDPTCTRL5; /**< Endpoint Control 5, offset: 0x1D4 */ + __IO uint32_t ENDPTCTRL6; /**< Endpoint Control 6, offset: 0x1D8 */ + __IO uint32_t ENDPTCTRL7; /**< Endpoint Control 7, offset: 0x1DC */ +} USB_Type; + +/* ---------------------------------------------------------------------------- + -- USB Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USB_Register_Masks USB Register Masks + * @{ + */ + +/*! @name ID - Identification */ +/*! @{ */ + +#define USB_ID_ID_MASK (0x3FU) +#define USB_ID_ID_SHIFT (0U) +/*! ID - ID */ +#define USB_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << USB_ID_ID_SHIFT)) & USB_ID_ID_MASK) + +#define USB_ID_NID_MASK (0x3F00U) +#define USB_ID_NID_SHIFT (8U) +/*! NID - NID */ +#define USB_ID_NID(x) (((uint32_t)(((uint32_t)(x)) << USB_ID_NID_SHIFT)) & USB_ID_NID_MASK) + +#define USB_ID_REVISION_MASK (0xFF0000U) +#define USB_ID_REVISION_SHIFT (16U) +/*! REVISION - REVISION */ +#define USB_ID_REVISION(x) (((uint32_t)(((uint32_t)(x)) << USB_ID_REVISION_SHIFT)) & USB_ID_REVISION_MASK) +/*! @} */ + +/*! @name HWGENERAL - Hardware General */ +/*! @{ */ + +#define USB_HWGENERAL_PHYW_MASK (0x30U) +#define USB_HWGENERAL_PHYW_SHIFT (4U) +/*! PHYW - PHYW + * 0b00..8 bit wide data bus (Software non-programmable) + * 0b01..16 bit wide data bus (Software non-programmable) + * 0b10..Reset to 8 bit wide data bus (Software programmable) + * 0b11..Reset to 16 bit wide data bus (Software programmable) + */ +#define USB_HWGENERAL_PHYW(x) (((uint32_t)(((uint32_t)(x)) << USB_HWGENERAL_PHYW_SHIFT)) & USB_HWGENERAL_PHYW_MASK) + +#define USB_HWGENERAL_PHYM_MASK (0x3C0U) +#define USB_HWGENERAL_PHYM_SHIFT (6U) +/*! PHYM - PHYM + * 0b0000..UTMI/UMTI+ + * 0b0001..ULPI DDR + * 0b0010..ULPI + * 0b0011..Serial only + * 0b0100..Software programmable - reset to UTMI/UTMI+ + * 0b0101..Software programmable - reset to ULPI DDR + * 0b0110..Software programmable - reset to ULPI + * 0b0111..Software programmable - reset to serial + * 0b1000..IC - USB + * 0b1001..Software programmable - reset to IC - USB + * 0b1010..HSIC + * 0b1011..Software programmable - reset to HSIC + * 0b1100..Reserved + * 0b1111..Reserved + */ +#define USB_HWGENERAL_PHYM(x) (((uint32_t)(((uint32_t)(x)) << USB_HWGENERAL_PHYM_SHIFT)) & USB_HWGENERAL_PHYM_MASK) + +#define USB_HWGENERAL_SM_MASK (0xC00U) +#define USB_HWGENERAL_SM_SHIFT (10U) +/*! SM - SM + * 0b00..No Serial Engine, always use parallel signalling. + * 0b01..Serial Engine present, always use serial signalling for FS/LS. + * 0b10..Software programmable - Reset to use parallel signalling for FS/LS + * 0b11..Software programmable - Reset to use serial signalling for FS/LS + */ +#define USB_HWGENERAL_SM(x) (((uint32_t)(((uint32_t)(x)) << USB_HWGENERAL_SM_SHIFT)) & USB_HWGENERAL_SM_MASK) +/*! @} */ + +/*! @name HWHOST - Host Hardware Parameters */ +/*! @{ */ + +#define USB_HWHOST_HC_MASK (0x1U) +#define USB_HWHOST_HC_SHIFT (0U) +/*! HC - HC + * 0b0..Not supported + * 0b1..Supported + */ +#define USB_HWHOST_HC(x) (((uint32_t)(((uint32_t)(x)) << USB_HWHOST_HC_SHIFT)) & USB_HWHOST_HC_MASK) + +#define USB_HWHOST_NPORT_MASK (0xEU) +#define USB_HWHOST_NPORT_SHIFT (1U) +/*! NPORT - NPORT */ +#define USB_HWHOST_NPORT(x) (((uint32_t)(((uint32_t)(x)) << USB_HWHOST_NPORT_SHIFT)) & USB_HWHOST_NPORT_MASK) +/*! @} */ + +/*! @name HWDEVICE - Device Hardware Parameters */ +/*! @{ */ + +#define USB_HWDEVICE_DC_MASK (0x1U) +#define USB_HWDEVICE_DC_SHIFT (0U) +/*! DC - DC + * 0b0..Not supported + * 0b1..Supported + */ +#define USB_HWDEVICE_DC(x) (((uint32_t)(((uint32_t)(x)) << USB_HWDEVICE_DC_SHIFT)) & USB_HWDEVICE_DC_MASK) + +#define USB_HWDEVICE_DEVEP_MASK (0x3EU) +#define USB_HWDEVICE_DEVEP_SHIFT (1U) +/*! DEVEP - DEVEP */ +#define USB_HWDEVICE_DEVEP(x) (((uint32_t)(((uint32_t)(x)) << USB_HWDEVICE_DEVEP_SHIFT)) & USB_HWDEVICE_DEVEP_MASK) +/*! @} */ + +/*! @name HWTXBUF - TX Buffer Hardware Parameters */ +/*! @{ */ + +#define USB_HWTXBUF_TXBURST_MASK (0xFFU) +#define USB_HWTXBUF_TXBURST_SHIFT (0U) +/*! TXBURST - TXBURST */ +#define USB_HWTXBUF_TXBURST(x) (((uint32_t)(((uint32_t)(x)) << USB_HWTXBUF_TXBURST_SHIFT)) & USB_HWTXBUF_TXBURST_MASK) + +#define USB_HWTXBUF_TXCHANADD_MASK (0xFF0000U) +#define USB_HWTXBUF_TXCHANADD_SHIFT (16U) +/*! TXCHANADD - TXCHANADD */ +#define USB_HWTXBUF_TXCHANADD(x) (((uint32_t)(((uint32_t)(x)) << USB_HWTXBUF_TXCHANADD_SHIFT)) & USB_HWTXBUF_TXCHANADD_MASK) +/*! @} */ + +/*! @name HWRXBUF - RX Buffer Hardware Parameters */ +/*! @{ */ + +#define USB_HWRXBUF_RXBURST_MASK (0xFFU) +#define USB_HWRXBUF_RXBURST_SHIFT (0U) +/*! RXBURST - RXBURST */ +#define USB_HWRXBUF_RXBURST(x) (((uint32_t)(((uint32_t)(x)) << USB_HWRXBUF_RXBURST_SHIFT)) & USB_HWRXBUF_RXBURST_MASK) + +#define USB_HWRXBUF_RXADD_MASK (0xFF00U) +#define USB_HWRXBUF_RXADD_SHIFT (8U) +/*! RXADD - RXADD */ +#define USB_HWRXBUF_RXADD(x) (((uint32_t)(((uint32_t)(x)) << USB_HWRXBUF_RXADD_SHIFT)) & USB_HWRXBUF_RXADD_MASK) +/*! @} */ + +/*! @name GPTIMER0LD - General Purpose Timer #0 Load */ +/*! @{ */ + +#define USB_GPTIMER0LD_GPTLD_MASK (0xFFFFFFU) +#define USB_GPTIMER0LD_GPTLD_SHIFT (0U) +/*! GPTLD - GPTLD */ +#define USB_GPTIMER0LD_GPTLD(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER0LD_GPTLD_SHIFT)) & USB_GPTIMER0LD_GPTLD_MASK) +/*! @} */ + +/*! @name GPTIMER0CTRL - General Purpose Timer #0 Controller */ +/*! @{ */ + +#define USB_GPTIMER0CTRL_GPTCNT_MASK (0xFFFFFFU) +#define USB_GPTIMER0CTRL_GPTCNT_SHIFT (0U) +/*! GPTCNT - GPTCNT */ +#define USB_GPTIMER0CTRL_GPTCNT(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER0CTRL_GPTCNT_SHIFT)) & USB_GPTIMER0CTRL_GPTCNT_MASK) + +#define USB_GPTIMER0CTRL_GPTMODE_MASK (0x1000000U) +#define USB_GPTIMER0CTRL_GPTMODE_SHIFT (24U) +/*! GPTMODE - GPTMODE + * 0b0..One Shot Mode + * 0b1..Repeat Mode + */ +#define USB_GPTIMER0CTRL_GPTMODE(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER0CTRL_GPTMODE_SHIFT)) & USB_GPTIMER0CTRL_GPTMODE_MASK) + +#define USB_GPTIMER0CTRL_GPTRST_MASK (0x40000000U) +#define USB_GPTIMER0CTRL_GPTRST_SHIFT (30U) +/*! GPTRST - GPTRST + * 0b0..No action + * 0b1..Load counter value from GPTLD bits in n_GPTIMER0LD + */ +#define USB_GPTIMER0CTRL_GPTRST(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER0CTRL_GPTRST_SHIFT)) & USB_GPTIMER0CTRL_GPTRST_MASK) + +#define USB_GPTIMER0CTRL_GPTRUN_MASK (0x80000000U) +#define USB_GPTIMER0CTRL_GPTRUN_SHIFT (31U) +/*! GPTRUN - GPTRUN + * 0b0..Stop counting + * 0b1..Run + */ +#define USB_GPTIMER0CTRL_GPTRUN(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER0CTRL_GPTRUN_SHIFT)) & USB_GPTIMER0CTRL_GPTRUN_MASK) +/*! @} */ + +/*! @name GPTIMER1LD - General Purpose Timer #1 Load */ +/*! @{ */ + +#define USB_GPTIMER1LD_GPTLD_MASK (0xFFFFFFU) +#define USB_GPTIMER1LD_GPTLD_SHIFT (0U) +/*! GPTLD - GPTLD */ +#define USB_GPTIMER1LD_GPTLD(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER1LD_GPTLD_SHIFT)) & USB_GPTIMER1LD_GPTLD_MASK) +/*! @} */ + +/*! @name GPTIMER1CTRL - General Purpose Timer #1 Controller */ +/*! @{ */ + +#define USB_GPTIMER1CTRL_GPTCNT_MASK (0xFFFFFFU) +#define USB_GPTIMER1CTRL_GPTCNT_SHIFT (0U) +/*! GPTCNT - GPTCNT */ +#define USB_GPTIMER1CTRL_GPTCNT(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER1CTRL_GPTCNT_SHIFT)) & USB_GPTIMER1CTRL_GPTCNT_MASK) + +#define USB_GPTIMER1CTRL_GPTMODE_MASK (0x1000000U) +#define USB_GPTIMER1CTRL_GPTMODE_SHIFT (24U) +/*! GPTMODE - GPTMODE + * 0b0..One Shot Mode + * 0b1..Repeat Mode + */ +#define USB_GPTIMER1CTRL_GPTMODE(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER1CTRL_GPTMODE_SHIFT)) & USB_GPTIMER1CTRL_GPTMODE_MASK) + +#define USB_GPTIMER1CTRL_GPTRST_MASK (0x40000000U) +#define USB_GPTIMER1CTRL_GPTRST_SHIFT (30U) +/*! GPTRST - GPTRST + * 0b0..No action + * 0b1..Load counter value from GPTLD bits in USB_n_GPTIMER0LD + */ +#define USB_GPTIMER1CTRL_GPTRST(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER1CTRL_GPTRST_SHIFT)) & USB_GPTIMER1CTRL_GPTRST_MASK) + +#define USB_GPTIMER1CTRL_GPTRUN_MASK (0x80000000U) +#define USB_GPTIMER1CTRL_GPTRUN_SHIFT (31U) +/*! GPTRUN - GPTRUN + * 0b0..Stop counting + * 0b1..Run + */ +#define USB_GPTIMER1CTRL_GPTRUN(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER1CTRL_GPTRUN_SHIFT)) & USB_GPTIMER1CTRL_GPTRUN_MASK) +/*! @} */ + +/*! @name SBUSCFG - System Bus Config */ +/*! @{ */ + +#define USB_SBUSCFG_AHBBRST_MASK (0x7U) +#define USB_SBUSCFG_AHBBRST_SHIFT (0U) +/*! AHBBRST - AHBBRST + * 0b000..Incremental burst of unspecified length only + * 0b001..INCR4 burst, then single transfer + * 0b010..INCR8 burst, INCR4 burst, then single transfer + * 0b011..INCR16 burst, INCR8 burst, INCR4 burst, then single transfer + * 0b100..Reserved, don't use + * 0b101..INCR4 burst, then incremental burst of unspecified length + * 0b110..INCR8 burst, INCR4 burst, then incremental burst of unspecified length + * 0b111..INCR16 burst, INCR8 burst, INCR4 burst, then incremental burst of unspecified length + */ +#define USB_SBUSCFG_AHBBRST(x) (((uint32_t)(((uint32_t)(x)) << USB_SBUSCFG_AHBBRST_SHIFT)) & USB_SBUSCFG_AHBBRST_MASK) +/*! @} */ + +/*! @name CAPLENGTH - Capability Registers Length */ +/*! @{ */ + +#define USB_CAPLENGTH_CAPLENGTH_MASK (0xFFU) +#define USB_CAPLENGTH_CAPLENGTH_SHIFT (0U) +/*! CAPLENGTH - CAPLENGTH */ +#define USB_CAPLENGTH_CAPLENGTH(x) (((uint8_t)(((uint8_t)(x)) << USB_CAPLENGTH_CAPLENGTH_SHIFT)) & USB_CAPLENGTH_CAPLENGTH_MASK) +/*! @} */ + +/*! @name HCIVERSION - Host Controller Interface Version */ +/*! @{ */ + +#define USB_HCIVERSION_HCIVERSION_MASK (0xFFFFU) +#define USB_HCIVERSION_HCIVERSION_SHIFT (0U) +/*! HCIVERSION - HCIVERSION */ +#define USB_HCIVERSION_HCIVERSION(x) (((uint16_t)(((uint16_t)(x)) << USB_HCIVERSION_HCIVERSION_SHIFT)) & USB_HCIVERSION_HCIVERSION_MASK) +/*! @} */ + +/*! @name HCSPARAMS - Host Controller Structural Parameters */ +/*! @{ */ + +#define USB_HCSPARAMS_N_PORTS_MASK (0xFU) +#define USB_HCSPARAMS_N_PORTS_SHIFT (0U) +/*! N_PORTS - N_PORTS */ +#define USB_HCSPARAMS_N_PORTS(x) (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_N_PORTS_SHIFT)) & USB_HCSPARAMS_N_PORTS_MASK) + +#define USB_HCSPARAMS_PPC_MASK (0x10U) +#define USB_HCSPARAMS_PPC_SHIFT (4U) +/*! PPC - PPC */ +#define USB_HCSPARAMS_PPC(x) (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_PPC_SHIFT)) & USB_HCSPARAMS_PPC_MASK) + +#define USB_HCSPARAMS_N_PCC_MASK (0xF00U) +#define USB_HCSPARAMS_N_PCC_SHIFT (8U) +/*! N_PCC - N_PCC */ +#define USB_HCSPARAMS_N_PCC(x) (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_N_PCC_SHIFT)) & USB_HCSPARAMS_N_PCC_MASK) + +#define USB_HCSPARAMS_N_CC_MASK (0xF000U) +#define USB_HCSPARAMS_N_CC_SHIFT (12U) +/*! N_CC - N_CC + * 0b0000..There is no internal Companion Controller and port-ownership hand-off is not supported. + * 0b0001..There are internal companion controller(s) and port-ownership hand-offs is supported. + */ +#define USB_HCSPARAMS_N_CC(x) (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_N_CC_SHIFT)) & USB_HCSPARAMS_N_CC_MASK) + +#define USB_HCSPARAMS_PI_MASK (0x10000U) +#define USB_HCSPARAMS_PI_SHIFT (16U) +/*! PI - PI */ +#define USB_HCSPARAMS_PI(x) (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_PI_SHIFT)) & USB_HCSPARAMS_PI_MASK) + +#define USB_HCSPARAMS_N_PTT_MASK (0xF00000U) +#define USB_HCSPARAMS_N_PTT_SHIFT (20U) +/*! N_PTT - N_PTT */ +#define USB_HCSPARAMS_N_PTT(x) (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_N_PTT_SHIFT)) & USB_HCSPARAMS_N_PTT_MASK) + +#define USB_HCSPARAMS_N_TT_MASK (0xF000000U) +#define USB_HCSPARAMS_N_TT_SHIFT (24U) +/*! N_TT - N_TT */ +#define USB_HCSPARAMS_N_TT(x) (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_N_TT_SHIFT)) & USB_HCSPARAMS_N_TT_MASK) +/*! @} */ + +/*! @name HCCPARAMS - Host Controller Capability Parameters */ +/*! @{ */ + +#define USB_HCCPARAMS_ADC_MASK (0x1U) +#define USB_HCCPARAMS_ADC_SHIFT (0U) +/*! ADC - ADC */ +#define USB_HCCPARAMS_ADC(x) (((uint32_t)(((uint32_t)(x)) << USB_HCCPARAMS_ADC_SHIFT)) & USB_HCCPARAMS_ADC_MASK) + +#define USB_HCCPARAMS_PFL_MASK (0x2U) +#define USB_HCCPARAMS_PFL_SHIFT (1U) +/*! PFL - PFL */ +#define USB_HCCPARAMS_PFL(x) (((uint32_t)(((uint32_t)(x)) << USB_HCCPARAMS_PFL_SHIFT)) & USB_HCCPARAMS_PFL_MASK) + +#define USB_HCCPARAMS_ASP_MASK (0x4U) +#define USB_HCCPARAMS_ASP_SHIFT (2U) +/*! ASP - ASP */ +#define USB_HCCPARAMS_ASP(x) (((uint32_t)(((uint32_t)(x)) << USB_HCCPARAMS_ASP_SHIFT)) & USB_HCCPARAMS_ASP_MASK) + +#define USB_HCCPARAMS_IST_MASK (0xF0U) +#define USB_HCCPARAMS_IST_SHIFT (4U) +/*! IST - IST */ +#define USB_HCCPARAMS_IST(x) (((uint32_t)(((uint32_t)(x)) << USB_HCCPARAMS_IST_SHIFT)) & USB_HCCPARAMS_IST_MASK) + +#define USB_HCCPARAMS_EECP_MASK (0xFF00U) +#define USB_HCCPARAMS_EECP_SHIFT (8U) +/*! EECP - EECP */ +#define USB_HCCPARAMS_EECP(x) (((uint32_t)(((uint32_t)(x)) << USB_HCCPARAMS_EECP_SHIFT)) & USB_HCCPARAMS_EECP_MASK) +/*! @} */ + +/*! @name DCIVERSION - Device Controller Interface Version */ +/*! @{ */ + +#define USB_DCIVERSION_DCIVERSION_MASK (0xFFFFU) +#define USB_DCIVERSION_DCIVERSION_SHIFT (0U) +/*! DCIVERSION - DCIVERSION */ +#define USB_DCIVERSION_DCIVERSION(x) (((uint16_t)(((uint16_t)(x)) << USB_DCIVERSION_DCIVERSION_SHIFT)) & USB_DCIVERSION_DCIVERSION_MASK) +/*! @} */ + +/*! @name DCCPARAMS - Device Controller Capability Parameters */ +/*! @{ */ + +#define USB_DCCPARAMS_DEN_MASK (0x1FU) +#define USB_DCCPARAMS_DEN_SHIFT (0U) +/*! DEN - DEN */ +#define USB_DCCPARAMS_DEN(x) (((uint32_t)(((uint32_t)(x)) << USB_DCCPARAMS_DEN_SHIFT)) & USB_DCCPARAMS_DEN_MASK) + +#define USB_DCCPARAMS_DC_MASK (0x80U) +#define USB_DCCPARAMS_DC_SHIFT (7U) +/*! DC - DC */ +#define USB_DCCPARAMS_DC(x) (((uint32_t)(((uint32_t)(x)) << USB_DCCPARAMS_DC_SHIFT)) & USB_DCCPARAMS_DC_MASK) + +#define USB_DCCPARAMS_HC_MASK (0x100U) +#define USB_DCCPARAMS_HC_SHIFT (8U) +/*! HC - HC */ +#define USB_DCCPARAMS_HC(x) (((uint32_t)(((uint32_t)(x)) << USB_DCCPARAMS_HC_SHIFT)) & USB_DCCPARAMS_HC_MASK) +/*! @} */ + +/*! @name USBCMD - USB Command */ +/*! @{ */ + +#define USB_USBCMD_RS_MASK (0x1U) +#define USB_USBCMD_RS_SHIFT (0U) +/*! RS - RS */ +#define USB_USBCMD_RS(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_RS_SHIFT)) & USB_USBCMD_RS_MASK) + +#define USB_USBCMD_RST_MASK (0x2U) +#define USB_USBCMD_RST_SHIFT (1U) +/*! RST - RST */ +#define USB_USBCMD_RST(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_RST_SHIFT)) & USB_USBCMD_RST_MASK) + +#define USB_USBCMD_FS_1_MASK (0xCU) +#define USB_USBCMD_FS_1_SHIFT (2U) +/*! FS_1 - FS_1 */ +#define USB_USBCMD_FS_1(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_FS_1_SHIFT)) & USB_USBCMD_FS_1_MASK) + +#define USB_USBCMD_PSE_MASK (0x10U) +#define USB_USBCMD_PSE_SHIFT (4U) +/*! PSE - PSE + * 0b0..Do not process the Periodic Schedule + * 0b1..Use the PERIODICLISTBASE register to access the Periodic Schedule. + */ +#define USB_USBCMD_PSE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_PSE_SHIFT)) & USB_USBCMD_PSE_MASK) + +#define USB_USBCMD_ASE_MASK (0x20U) +#define USB_USBCMD_ASE_SHIFT (5U) +/*! ASE - ASE + * 0b0..Do not process the Asynchronous Schedule. + * 0b1..Use the ASYNCLISTADDR register to access the Asynchronous Schedule. + */ +#define USB_USBCMD_ASE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_ASE_SHIFT)) & USB_USBCMD_ASE_MASK) + +#define USB_USBCMD_IAA_MASK (0x40U) +#define USB_USBCMD_IAA_SHIFT (6U) +/*! IAA - IAA */ +#define USB_USBCMD_IAA(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_IAA_SHIFT)) & USB_USBCMD_IAA_MASK) + +#define USB_USBCMD_ASP_MASK (0x300U) +#define USB_USBCMD_ASP_SHIFT (8U) +/*! ASP - ASP */ +#define USB_USBCMD_ASP(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_ASP_SHIFT)) & USB_USBCMD_ASP_MASK) + +#define USB_USBCMD_ASPE_MASK (0x800U) +#define USB_USBCMD_ASPE_SHIFT (11U) +/*! ASPE - ASPE */ +#define USB_USBCMD_ASPE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_ASPE_SHIFT)) & USB_USBCMD_ASPE_MASK) + +#define USB_USBCMD_SUTW_MASK (0x2000U) +#define USB_USBCMD_SUTW_SHIFT (13U) +/*! SUTW - SUTW */ +#define USB_USBCMD_SUTW(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_SUTW_SHIFT)) & USB_USBCMD_SUTW_MASK) + +#define USB_USBCMD_ATDTW_MASK (0x4000U) +#define USB_USBCMD_ATDTW_SHIFT (14U) +/*! ATDTW - ATDTW */ +#define USB_USBCMD_ATDTW(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_ATDTW_SHIFT)) & USB_USBCMD_ATDTW_MASK) + +#define USB_USBCMD_FS_2_MASK (0x8000U) +#define USB_USBCMD_FS_2_SHIFT (15U) +/*! FS_2 - FS_2 */ +#define USB_USBCMD_FS_2(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_FS_2_SHIFT)) & USB_USBCMD_FS_2_MASK) + +#define USB_USBCMD_ITC_MASK (0xFF0000U) +#define USB_USBCMD_ITC_SHIFT (16U) +/*! ITC - ITC + * 0b00000000..Immediate (no threshold) + * 0b00000001..1 micro-frame + * 0b00000010..2 micro-frames + * 0b00000100..4 micro-frames + * 0b00001000..8 micro-frames + * 0b00010000..16 micro-frames + * 0b00100000..32 micro-frames + * 0b01000000..64 micro-frames + */ +#define USB_USBCMD_ITC(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_ITC_SHIFT)) & USB_USBCMD_ITC_MASK) +/*! @} */ + +/*! @name USBSTS - USB Status */ +/*! @{ */ + +#define USB_USBSTS_UI_MASK (0x1U) +#define USB_USBSTS_UI_SHIFT (0U) +/*! UI - UI */ +#define USB_USBSTS_UI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_UI_SHIFT)) & USB_USBSTS_UI_MASK) + +#define USB_USBSTS_UEI_MASK (0x2U) +#define USB_USBSTS_UEI_SHIFT (1U) +/*! UEI - UEI */ +#define USB_USBSTS_UEI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_UEI_SHIFT)) & USB_USBSTS_UEI_MASK) + +#define USB_USBSTS_PCI_MASK (0x4U) +#define USB_USBSTS_PCI_SHIFT (2U) +/*! PCI - PCI */ +#define USB_USBSTS_PCI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_PCI_SHIFT)) & USB_USBSTS_PCI_MASK) + +#define USB_USBSTS_FRI_MASK (0x8U) +#define USB_USBSTS_FRI_SHIFT (3U) +/*! FRI - FRI */ +#define USB_USBSTS_FRI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_FRI_SHIFT)) & USB_USBSTS_FRI_MASK) + +#define USB_USBSTS_SEI_MASK (0x10U) +#define USB_USBSTS_SEI_SHIFT (4U) +/*! SEI - SEI */ +#define USB_USBSTS_SEI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_SEI_SHIFT)) & USB_USBSTS_SEI_MASK) + +#define USB_USBSTS_AAI_MASK (0x20U) +#define USB_USBSTS_AAI_SHIFT (5U) +/*! AAI - AAI */ +#define USB_USBSTS_AAI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_AAI_SHIFT)) & USB_USBSTS_AAI_MASK) + +#define USB_USBSTS_URI_MASK (0x40U) +#define USB_USBSTS_URI_SHIFT (6U) +/*! URI - URI */ +#define USB_USBSTS_URI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_URI_SHIFT)) & USB_USBSTS_URI_MASK) + +#define USB_USBSTS_SRI_MASK (0x80U) +#define USB_USBSTS_SRI_SHIFT (7U) +/*! SRI - SRI */ +#define USB_USBSTS_SRI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_SRI_SHIFT)) & USB_USBSTS_SRI_MASK) + +#define USB_USBSTS_SLI_MASK (0x100U) +#define USB_USBSTS_SLI_SHIFT (8U) +/*! SLI - SLI */ +#define USB_USBSTS_SLI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_SLI_SHIFT)) & USB_USBSTS_SLI_MASK) + +#define USB_USBSTS_ULPII_MASK (0x400U) +#define USB_USBSTS_ULPII_SHIFT (10U) +/*! ULPII - ULPII */ +#define USB_USBSTS_ULPII(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_ULPII_SHIFT)) & USB_USBSTS_ULPII_MASK) + +#define USB_USBSTS_HCH_MASK (0x1000U) +#define USB_USBSTS_HCH_SHIFT (12U) +/*! HCH - HCH */ +#define USB_USBSTS_HCH(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_HCH_SHIFT)) & USB_USBSTS_HCH_MASK) + +#define USB_USBSTS_RCL_MASK (0x2000U) +#define USB_USBSTS_RCL_SHIFT (13U) +/*! RCL - RCL */ +#define USB_USBSTS_RCL(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_RCL_SHIFT)) & USB_USBSTS_RCL_MASK) + +#define USB_USBSTS_PS_MASK (0x4000U) +#define USB_USBSTS_PS_SHIFT (14U) +/*! PS - PS */ +#define USB_USBSTS_PS(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_PS_SHIFT)) & USB_USBSTS_PS_MASK) + +#define USB_USBSTS_AS_MASK (0x8000U) +#define USB_USBSTS_AS_SHIFT (15U) +/*! AS - AS */ +#define USB_USBSTS_AS(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_AS_SHIFT)) & USB_USBSTS_AS_MASK) + +#define USB_USBSTS_NAKI_MASK (0x10000U) +#define USB_USBSTS_NAKI_SHIFT (16U) +/*! NAKI - NAKI */ +#define USB_USBSTS_NAKI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_NAKI_SHIFT)) & USB_USBSTS_NAKI_MASK) + +#define USB_USBSTS_UAI_MASK (0x40000U) +#define USB_USBSTS_UAI_SHIFT (18U) +/*! UAI - USB Host Asynchronous Interrupt + * 0b0..Interrupt did not occur + * 0b0..No effect + * 0b1..Interrupt occurred + * 0b1..Clear the flag + */ +#define USB_USBSTS_UAI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_UAI_SHIFT)) & USB_USBSTS_UAI_MASK) + +#define USB_USBSTS_UPI_MASK (0x80000U) +#define USB_USBSTS_UPI_SHIFT (19U) +/*! UPI - USB Host Periodic Interrupt + * 0b0..Interrupt did not occur + * 0b0..No effect + * 0b1..Interrupt occurred + * 0b1..Clear the flag + */ +#define USB_USBSTS_UPI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_UPI_SHIFT)) & USB_USBSTS_UPI_MASK) + +#define USB_USBSTS_TI0_MASK (0x1000000U) +#define USB_USBSTS_TI0_SHIFT (24U) +/*! TI0 - TI0 */ +#define USB_USBSTS_TI0(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_TI0_SHIFT)) & USB_USBSTS_TI0_MASK) + +#define USB_USBSTS_TI1_MASK (0x2000000U) +#define USB_USBSTS_TI1_SHIFT (25U) +/*! TI1 - TI1 */ +#define USB_USBSTS_TI1(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_TI1_SHIFT)) & USB_USBSTS_TI1_MASK) +/*! @} */ + +/*! @name USBINTR - Interrupt Enable */ +/*! @{ */ + +#define USB_USBINTR_UE_MASK (0x1U) +#define USB_USBINTR_UE_SHIFT (0U) +/*! UE - UE */ +#define USB_USBINTR_UE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_UE_SHIFT)) & USB_USBINTR_UE_MASK) + +#define USB_USBINTR_UEE_MASK (0x2U) +#define USB_USBINTR_UEE_SHIFT (1U) +/*! UEE - UEE */ +#define USB_USBINTR_UEE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_UEE_SHIFT)) & USB_USBINTR_UEE_MASK) + +#define USB_USBINTR_PCE_MASK (0x4U) +#define USB_USBINTR_PCE_SHIFT (2U) +/*! PCE - PCE */ +#define USB_USBINTR_PCE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_PCE_SHIFT)) & USB_USBINTR_PCE_MASK) + +#define USB_USBINTR_FRE_MASK (0x8U) +#define USB_USBINTR_FRE_SHIFT (3U) +/*! FRE - FRE */ +#define USB_USBINTR_FRE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_FRE_SHIFT)) & USB_USBINTR_FRE_MASK) + +#define USB_USBINTR_SEE_MASK (0x10U) +#define USB_USBINTR_SEE_SHIFT (4U) +/*! SEE - SEE */ +#define USB_USBINTR_SEE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_SEE_SHIFT)) & USB_USBINTR_SEE_MASK) + +#define USB_USBINTR_AAE_MASK (0x20U) +#define USB_USBINTR_AAE_SHIFT (5U) +/*! AAE - AAE */ +#define USB_USBINTR_AAE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_AAE_SHIFT)) & USB_USBINTR_AAE_MASK) + +#define USB_USBINTR_URE_MASK (0x40U) +#define USB_USBINTR_URE_SHIFT (6U) +/*! URE - URE */ +#define USB_USBINTR_URE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_URE_SHIFT)) & USB_USBINTR_URE_MASK) + +#define USB_USBINTR_SRE_MASK (0x80U) +#define USB_USBINTR_SRE_SHIFT (7U) +/*! SRE - SRE */ +#define USB_USBINTR_SRE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_SRE_SHIFT)) & USB_USBINTR_SRE_MASK) + +#define USB_USBINTR_SLE_MASK (0x100U) +#define USB_USBINTR_SLE_SHIFT (8U) +/*! SLE - SLE */ +#define USB_USBINTR_SLE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_SLE_SHIFT)) & USB_USBINTR_SLE_MASK) + +#define USB_USBINTR_NAKE_MASK (0x10000U) +#define USB_USBINTR_NAKE_SHIFT (16U) +/*! NAKE - NAKE */ +#define USB_USBINTR_NAKE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_NAKE_SHIFT)) & USB_USBINTR_NAKE_MASK) + +#define USB_USBINTR_UAIE_MASK (0x40000U) +#define USB_USBINTR_UAIE_SHIFT (18U) +/*! UAIE - UAIE */ +#define USB_USBINTR_UAIE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_UAIE_SHIFT)) & USB_USBINTR_UAIE_MASK) + +#define USB_USBINTR_UPIE_MASK (0x80000U) +#define USB_USBINTR_UPIE_SHIFT (19U) +/*! UPIE - UPIE */ +#define USB_USBINTR_UPIE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_UPIE_SHIFT)) & USB_USBINTR_UPIE_MASK) + +#define USB_USBINTR_TIE0_MASK (0x1000000U) +#define USB_USBINTR_TIE0_SHIFT (24U) +/*! TIE0 - TIE0 */ +#define USB_USBINTR_TIE0(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_TIE0_SHIFT)) & USB_USBINTR_TIE0_MASK) + +#define USB_USBINTR_TIE1_MASK (0x2000000U) +#define USB_USBINTR_TIE1_SHIFT (25U) +/*! TIE1 - TIE1 */ +#define USB_USBINTR_TIE1(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_TIE1_SHIFT)) & USB_USBINTR_TIE1_MASK) +/*! @} */ + +/*! @name FRINDEX - USB Frame Index */ +/*! @{ */ + +#define USB_FRINDEX_FRINDEX_MASK (0x3FFFU) +#define USB_FRINDEX_FRINDEX_SHIFT (0U) +/*! FRINDEX - FRINDEX + * 0b00000000000000..(1024) 12 + * 0b00000000000001..(512) 11 + * 0b00000000000010..(256) 10 + * 0b00000000000011..(128) 9 + * 0b00000000000100..(64) 8 + * 0b00000000000101..(32) 7 + * 0b00000000000110..(16) 6 + * 0b00000000000111..(8) 5 + */ +#define USB_FRINDEX_FRINDEX(x) (((uint32_t)(((uint32_t)(x)) << USB_FRINDEX_FRINDEX_SHIFT)) & USB_FRINDEX_FRINDEX_MASK) +/*! @} */ + +/*! @name DEVICEADDR - Device Address */ +/*! @{ */ + +#define USB_DEVICEADDR_USBADRA_MASK (0x1000000U) +#define USB_DEVICEADDR_USBADRA_SHIFT (24U) +/*! USBADRA - USBADRA */ +#define USB_DEVICEADDR_USBADRA(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVICEADDR_USBADRA_SHIFT)) & USB_DEVICEADDR_USBADRA_MASK) + +#define USB_DEVICEADDR_USBADR_MASK (0xFE000000U) +#define USB_DEVICEADDR_USBADR_SHIFT (25U) +/*! USBADR - USBADR */ +#define USB_DEVICEADDR_USBADR(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVICEADDR_USBADR_SHIFT)) & USB_DEVICEADDR_USBADR_MASK) +/*! @} */ + +/*! @name ENDPTLISTADDR - Endpoint List Address */ +/*! @{ */ + +#define USB_ENDPTLISTADDR_EPBASE_MASK (0xFFFFF800U) +#define USB_ENDPTLISTADDR_EPBASE_SHIFT (11U) +/*! EPBASE - EPBASE */ +#define USB_ENDPTLISTADDR_EPBASE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTLISTADDR_EPBASE_SHIFT)) & USB_ENDPTLISTADDR_EPBASE_MASK) +/*! @} */ + +/*! @name PERIODICLISTBASE - Frame List Base Address */ +/*! @{ */ + +#define USB_PERIODICLISTBASE_BASEADR_MASK (0xFFFFF000U) +#define USB_PERIODICLISTBASE_BASEADR_SHIFT (12U) +/*! BASEADR - BASEADR */ +#define USB_PERIODICLISTBASE_BASEADR(x) (((uint32_t)(((uint32_t)(x)) << USB_PERIODICLISTBASE_BASEADR_SHIFT)) & USB_PERIODICLISTBASE_BASEADR_MASK) +/*! @} */ + +/*! @name ASYNCLISTADDR - Next Asynch. Address */ +/*! @{ */ + +#define USB_ASYNCLISTADDR_ASYBASE_MASK (0xFFFFFFE0U) +#define USB_ASYNCLISTADDR_ASYBASE_SHIFT (5U) +/*! ASYBASE - ASYBASE */ +#define USB_ASYNCLISTADDR_ASYBASE(x) (((uint32_t)(((uint32_t)(x)) << USB_ASYNCLISTADDR_ASYBASE_SHIFT)) & USB_ASYNCLISTADDR_ASYBASE_MASK) +/*! @} */ + +/*! @name BURSTSIZE - Programmable Burst Size */ +/*! @{ */ + +#define USB_BURSTSIZE_RXPBURST_MASK (0xFFU) +#define USB_BURSTSIZE_RXPBURST_SHIFT (0U) +/*! RXPBURST - RXPBURST */ +#define USB_BURSTSIZE_RXPBURST(x) (((uint32_t)(((uint32_t)(x)) << USB_BURSTSIZE_RXPBURST_SHIFT)) & USB_BURSTSIZE_RXPBURST_MASK) + +#define USB_BURSTSIZE_TXPBURST_MASK (0xFF00U) +#define USB_BURSTSIZE_TXPBURST_SHIFT (8U) +/*! TXPBURST - TXPBURST */ +#define USB_BURSTSIZE_TXPBURST(x) (((uint32_t)(((uint32_t)(x)) << USB_BURSTSIZE_TXPBURST_SHIFT)) & USB_BURSTSIZE_TXPBURST_MASK) +/*! @} */ + +/*! @name TXFILLTUNING - TX FIFO Fill Tuning */ +/*! @{ */ + +#define USB_TXFILLTUNING_TXSCHOH_MASK (0x7FU) +#define USB_TXFILLTUNING_TXSCHOH_SHIFT (0U) +/*! TXSCHOH - TXSCHOH */ +#define USB_TXFILLTUNING_TXSCHOH(x) (((uint32_t)(((uint32_t)(x)) << USB_TXFILLTUNING_TXSCHOH_SHIFT)) & USB_TXFILLTUNING_TXSCHOH_MASK) + +#define USB_TXFILLTUNING_TXSCHHEALTH_MASK (0x1F00U) +#define USB_TXFILLTUNING_TXSCHHEALTH_SHIFT (8U) +/*! TXSCHHEALTH - TXSCHHEALTH */ +#define USB_TXFILLTUNING_TXSCHHEALTH(x) (((uint32_t)(((uint32_t)(x)) << USB_TXFILLTUNING_TXSCHHEALTH_SHIFT)) & USB_TXFILLTUNING_TXSCHHEALTH_MASK) + +#define USB_TXFILLTUNING_TXFIFOTHRES_MASK (0x3F0000U) +#define USB_TXFILLTUNING_TXFIFOTHRES_SHIFT (16U) +/*! TXFIFOTHRES - TXFIFOTHRES */ +#define USB_TXFILLTUNING_TXFIFOTHRES(x) (((uint32_t)(((uint32_t)(x)) << USB_TXFILLTUNING_TXFIFOTHRES_SHIFT)) & USB_TXFILLTUNING_TXFIFOTHRES_MASK) +/*! @} */ + +/*! @name ENDPTNAK - Endpoint NAK */ +/*! @{ */ + +#define USB_ENDPTNAK_EPRN_MASK (0xFFU) +#define USB_ENDPTNAK_EPRN_SHIFT (0U) +/*! EPRN - EPRN */ +#define USB_ENDPTNAK_EPRN(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTNAK_EPRN_SHIFT)) & USB_ENDPTNAK_EPRN_MASK) + +#define USB_ENDPTNAK_EPTN_MASK (0xFF0000U) +#define USB_ENDPTNAK_EPTN_SHIFT (16U) +/*! EPTN - EPTN */ +#define USB_ENDPTNAK_EPTN(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTNAK_EPTN_SHIFT)) & USB_ENDPTNAK_EPTN_MASK) +/*! @} */ + +/*! @name ENDPTNAKEN - Endpoint NAK Enable */ +/*! @{ */ + +#define USB_ENDPTNAKEN_EPRNE_MASK (0xFFU) +#define USB_ENDPTNAKEN_EPRNE_SHIFT (0U) +/*! EPRNE - EPRNE */ +#define USB_ENDPTNAKEN_EPRNE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTNAKEN_EPRNE_SHIFT)) & USB_ENDPTNAKEN_EPRNE_MASK) + +#define USB_ENDPTNAKEN_EPTNE_MASK (0xFF0000U) +#define USB_ENDPTNAKEN_EPTNE_SHIFT (16U) +/*! EPTNE - EPTNE */ +#define USB_ENDPTNAKEN_EPTNE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTNAKEN_EPTNE_SHIFT)) & USB_ENDPTNAKEN_EPTNE_MASK) +/*! @} */ + +/*! @name CONFIGFLAG - Configure Flag */ +/*! @{ */ + +#define USB_CONFIGFLAG_CF_MASK (0x1U) +#define USB_CONFIGFLAG_CF_SHIFT (0U) +/*! CF - CF + * 0b0..Port routing control logic default-routes each port to an implementation dependent classic host controller. + * 0b1..Port routing control logic default-routes all ports to this host controller. + */ +#define USB_CONFIGFLAG_CF(x) (((uint32_t)(((uint32_t)(x)) << USB_CONFIGFLAG_CF_SHIFT)) & USB_CONFIGFLAG_CF_MASK) +/*! @} */ + +/*! @name PORTSC1 - Port Status & Control */ +/*! @{ */ + +#define USB_PORTSC1_CCS_MASK (0x1U) +#define USB_PORTSC1_CCS_SHIFT (0U) +/*! CCS - CCS */ +#define USB_PORTSC1_CCS(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_CCS_SHIFT)) & USB_PORTSC1_CCS_MASK) + +#define USB_PORTSC1_CSC_MASK (0x2U) +#define USB_PORTSC1_CSC_SHIFT (1U) +/*! CSC - CSC */ +#define USB_PORTSC1_CSC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_CSC_SHIFT)) & USB_PORTSC1_CSC_MASK) + +#define USB_PORTSC1_PE_MASK (0x4U) +#define USB_PORTSC1_PE_SHIFT (2U) +/*! PE - PE */ +#define USB_PORTSC1_PE(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PE_SHIFT)) & USB_PORTSC1_PE_MASK) + +#define USB_PORTSC1_PEC_MASK (0x8U) +#define USB_PORTSC1_PEC_SHIFT (3U) +/*! PEC - PEC */ +#define USB_PORTSC1_PEC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PEC_SHIFT)) & USB_PORTSC1_PEC_MASK) + +#define USB_PORTSC1_OCA_MASK (0x10U) +#define USB_PORTSC1_OCA_SHIFT (4U) +/*! OCA - OCA + * 0b0..This port does not have an over-current condition. + * 0b1..This port currently has an over-current condition + */ +#define USB_PORTSC1_OCA(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_OCA_SHIFT)) & USB_PORTSC1_OCA_MASK) + +#define USB_PORTSC1_OCC_MASK (0x20U) +#define USB_PORTSC1_OCC_SHIFT (5U) +/*! OCC - OCC */ +#define USB_PORTSC1_OCC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_OCC_SHIFT)) & USB_PORTSC1_OCC_MASK) + +#define USB_PORTSC1_FPR_MASK (0x40U) +#define USB_PORTSC1_FPR_SHIFT (6U) +/*! FPR - FPR */ +#define USB_PORTSC1_FPR(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_FPR_SHIFT)) & USB_PORTSC1_FPR_MASK) + +#define USB_PORTSC1_SUSP_MASK (0x80U) +#define USB_PORTSC1_SUSP_SHIFT (7U) +/*! SUSP - SUSP */ +#define USB_PORTSC1_SUSP(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_SUSP_SHIFT)) & USB_PORTSC1_SUSP_MASK) + +#define USB_PORTSC1_PR_MASK (0x100U) +#define USB_PORTSC1_PR_SHIFT (8U) +/*! PR - PR */ +#define USB_PORTSC1_PR(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PR_SHIFT)) & USB_PORTSC1_PR_MASK) + +#define USB_PORTSC1_HSP_MASK (0x200U) +#define USB_PORTSC1_HSP_SHIFT (9U) +/*! HSP - HSP */ +#define USB_PORTSC1_HSP(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_HSP_SHIFT)) & USB_PORTSC1_HSP_MASK) + +#define USB_PORTSC1_LS_MASK (0xC00U) +#define USB_PORTSC1_LS_SHIFT (10U) +/*! LS - LS + * 0b00..SE0 + * 0b01..K-state + * 0b10..J-state + * 0b11..Undefined + */ +#define USB_PORTSC1_LS(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_LS_SHIFT)) & USB_PORTSC1_LS_MASK) + +#define USB_PORTSC1_PP_MASK (0x1000U) +#define USB_PORTSC1_PP_SHIFT (12U) +/*! PP - PP */ +#define USB_PORTSC1_PP(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PP_SHIFT)) & USB_PORTSC1_PP_MASK) + +#define USB_PORTSC1_PO_MASK (0x2000U) +#define USB_PORTSC1_PO_SHIFT (13U) +/*! PO - PO */ +#define USB_PORTSC1_PO(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PO_SHIFT)) & USB_PORTSC1_PO_MASK) + +#define USB_PORTSC1_PIC_MASK (0xC000U) +#define USB_PORTSC1_PIC_SHIFT (14U) +/*! PIC - PIC + * 0b00..Port indicators are off + * 0b01..Amber + * 0b10..Green + * 0b11..Undefined + */ +#define USB_PORTSC1_PIC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PIC_SHIFT)) & USB_PORTSC1_PIC_MASK) + +#define USB_PORTSC1_PTC_MASK (0xF0000U) +#define USB_PORTSC1_PTC_SHIFT (16U) +/*! PTC - PTC + * 0b0000..TEST_MODE_DISABLE + * 0b0001..J_STATE + * 0b0010..K_STATE + * 0b0011..SE0 (host) / NAK (device) + * 0b0100..Packet + * 0b0101..FORCE_ENABLE_HS + * 0b0110..FORCE_ENABLE_FS + * 0b0111..FORCE_ENABLE_LS + * 0b1000-0b1111..Reserved + */ +#define USB_PORTSC1_PTC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PTC_SHIFT)) & USB_PORTSC1_PTC_MASK) + +#define USB_PORTSC1_WKCN_MASK (0x100000U) +#define USB_PORTSC1_WKCN_SHIFT (20U) +/*! WKCN - WKCN */ +#define USB_PORTSC1_WKCN(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_WKCN_SHIFT)) & USB_PORTSC1_WKCN_MASK) + +#define USB_PORTSC1_WKDC_MASK (0x200000U) +#define USB_PORTSC1_WKDC_SHIFT (21U) +/*! WKDC - WKDC */ +#define USB_PORTSC1_WKDC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_WKDC_SHIFT)) & USB_PORTSC1_WKDC_MASK) + +#define USB_PORTSC1_WKOC_MASK (0x400000U) +#define USB_PORTSC1_WKOC_SHIFT (22U) +/*! WKOC - WKOC */ +#define USB_PORTSC1_WKOC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_WKOC_SHIFT)) & USB_PORTSC1_WKOC_MASK) + +#define USB_PORTSC1_PHCD_MASK (0x800000U) +#define USB_PORTSC1_PHCD_SHIFT (23U) +/*! PHCD - PHCD + * 0b0..Enable PHY clock + * 0b1..Disable PHY clock + */ +#define USB_PORTSC1_PHCD(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PHCD_SHIFT)) & USB_PORTSC1_PHCD_MASK) + +#define USB_PORTSC1_PFSC_MASK (0x1000000U) +#define USB_PORTSC1_PFSC_SHIFT (24U) +/*! PFSC - PFSC + * 0b0..Normal operation + * 0b1..Forced to full speed + */ +#define USB_PORTSC1_PFSC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PFSC_SHIFT)) & USB_PORTSC1_PFSC_MASK) + +#define USB_PORTSC1_PTS_2_MASK (0x2000000U) +#define USB_PORTSC1_PTS_2_SHIFT (25U) +/*! PTS_2 - PTS_2 */ +#define USB_PORTSC1_PTS_2(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PTS_2_SHIFT)) & USB_PORTSC1_PTS_2_MASK) + +#define USB_PORTSC1_PSPD_MASK (0xC000000U) +#define USB_PORTSC1_PSPD_SHIFT (26U) +/*! PSPD - PSPD + * 0b00..Full Speed + * 0b01..Low Speed + * 0b10..High Speed + * 0b11..Undefined + */ +#define USB_PORTSC1_PSPD(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PSPD_SHIFT)) & USB_PORTSC1_PSPD_MASK) + +#define USB_PORTSC1_PTW_MASK (0x10000000U) +#define USB_PORTSC1_PTW_SHIFT (28U) +/*! PTW - PTW + * 0b0..Select the 8-bit UTMI interface [60MHz] + * 0b1..Select the 16-bit UTMI interface [30MHz] + */ +#define USB_PORTSC1_PTW(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PTW_SHIFT)) & USB_PORTSC1_PTW_MASK) + +#define USB_PORTSC1_STS_MASK (0x20000000U) +#define USB_PORTSC1_STS_SHIFT (29U) +/*! STS - STS */ +#define USB_PORTSC1_STS(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_STS_SHIFT)) & USB_PORTSC1_STS_MASK) + +#define USB_PORTSC1_PTS_1_MASK (0xC0000000U) +#define USB_PORTSC1_PTS_1_SHIFT (30U) +/*! PTS_1 - PTS_1 */ +#define USB_PORTSC1_PTS_1(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PTS_1_SHIFT)) & USB_PORTSC1_PTS_1_MASK) +/*! @} */ + +/*! @name OTGSC - On-The-Go Status & control */ +/*! @{ */ + +#define USB_OTGSC_VD_MASK (0x1U) +#define USB_OTGSC_VD_SHIFT (0U) +/*! VD - VD */ +#define USB_OTGSC_VD(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_VD_SHIFT)) & USB_OTGSC_VD_MASK) + +#define USB_OTGSC_VC_MASK (0x2U) +#define USB_OTGSC_VC_SHIFT (1U) +/*! VC - VC */ +#define USB_OTGSC_VC(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_VC_SHIFT)) & USB_OTGSC_VC_MASK) + +#define USB_OTGSC_OT_MASK (0x8U) +#define USB_OTGSC_OT_SHIFT (3U) +/*! OT - OT */ +#define USB_OTGSC_OT(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_OT_SHIFT)) & USB_OTGSC_OT_MASK) + +#define USB_OTGSC_DP_MASK (0x10U) +#define USB_OTGSC_DP_SHIFT (4U) +/*! DP - DP */ +#define USB_OTGSC_DP(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_DP_SHIFT)) & USB_OTGSC_DP_MASK) + +#define USB_OTGSC_IDPU_MASK (0x20U) +#define USB_OTGSC_IDPU_SHIFT (5U) +/*! IDPU - IDPU */ +#define USB_OTGSC_IDPU(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_IDPU_SHIFT)) & USB_OTGSC_IDPU_MASK) + +#define USB_OTGSC_ID_MASK (0x100U) +#define USB_OTGSC_ID_SHIFT (8U) +/*! ID - ID */ +#define USB_OTGSC_ID(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_ID_SHIFT)) & USB_OTGSC_ID_MASK) + +#define USB_OTGSC_AVV_MASK (0x200U) +#define USB_OTGSC_AVV_SHIFT (9U) +/*! AVV - AVV */ +#define USB_OTGSC_AVV(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_AVV_SHIFT)) & USB_OTGSC_AVV_MASK) + +#define USB_OTGSC_ASV_MASK (0x400U) +#define USB_OTGSC_ASV_SHIFT (10U) +/*! ASV - ASV */ +#define USB_OTGSC_ASV(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_ASV_SHIFT)) & USB_OTGSC_ASV_MASK) + +#define USB_OTGSC_BSV_MASK (0x800U) +#define USB_OTGSC_BSV_SHIFT (11U) +/*! BSV - BSV */ +#define USB_OTGSC_BSV(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_BSV_SHIFT)) & USB_OTGSC_BSV_MASK) + +#define USB_OTGSC_BSE_MASK (0x1000U) +#define USB_OTGSC_BSE_SHIFT (12U) +/*! BSE - BSE */ +#define USB_OTGSC_BSE(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_BSE_SHIFT)) & USB_OTGSC_BSE_MASK) + +#define USB_OTGSC_TOG_1MS_MASK (0x2000U) +#define USB_OTGSC_TOG_1MS_SHIFT (13U) +/*! TOG_1MS - TOG_1MS */ +#define USB_OTGSC_TOG_1MS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_TOG_1MS_SHIFT)) & USB_OTGSC_TOG_1MS_MASK) + +#define USB_OTGSC_DPS_MASK (0x4000U) +#define USB_OTGSC_DPS_SHIFT (14U) +/*! DPS - DPS */ +#define USB_OTGSC_DPS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_DPS_SHIFT)) & USB_OTGSC_DPS_MASK) + +#define USB_OTGSC_IDIS_MASK (0x10000U) +#define USB_OTGSC_IDIS_SHIFT (16U) +/*! IDIS - IDIS */ +#define USB_OTGSC_IDIS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_IDIS_SHIFT)) & USB_OTGSC_IDIS_MASK) + +#define USB_OTGSC_AVVIS_MASK (0x20000U) +#define USB_OTGSC_AVVIS_SHIFT (17U) +/*! AVVIS - AVVIS */ +#define USB_OTGSC_AVVIS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_AVVIS_SHIFT)) & USB_OTGSC_AVVIS_MASK) + +#define USB_OTGSC_ASVIS_MASK (0x40000U) +#define USB_OTGSC_ASVIS_SHIFT (18U) +/*! ASVIS - ASVIS */ +#define USB_OTGSC_ASVIS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_ASVIS_SHIFT)) & USB_OTGSC_ASVIS_MASK) + +#define USB_OTGSC_BSVIS_MASK (0x80000U) +#define USB_OTGSC_BSVIS_SHIFT (19U) +/*! BSVIS - BSVIS */ +#define USB_OTGSC_BSVIS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_BSVIS_SHIFT)) & USB_OTGSC_BSVIS_MASK) + +#define USB_OTGSC_BSEIS_MASK (0x100000U) +#define USB_OTGSC_BSEIS_SHIFT (20U) +/*! BSEIS - BSEIS */ +#define USB_OTGSC_BSEIS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_BSEIS_SHIFT)) & USB_OTGSC_BSEIS_MASK) + +#define USB_OTGSC_STATUS_1MS_MASK (0x200000U) +#define USB_OTGSC_STATUS_1MS_SHIFT (21U) +/*! STATUS_1MS - STATUS_1MS */ +#define USB_OTGSC_STATUS_1MS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_STATUS_1MS_SHIFT)) & USB_OTGSC_STATUS_1MS_MASK) + +#define USB_OTGSC_DPIS_MASK (0x400000U) +#define USB_OTGSC_DPIS_SHIFT (22U) +/*! DPIS - DPIS */ +#define USB_OTGSC_DPIS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_DPIS_SHIFT)) & USB_OTGSC_DPIS_MASK) + +#define USB_OTGSC_IDIE_MASK (0x1000000U) +#define USB_OTGSC_IDIE_SHIFT (24U) +/*! IDIE - IDIE */ +#define USB_OTGSC_IDIE(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_IDIE_SHIFT)) & USB_OTGSC_IDIE_MASK) + +#define USB_OTGSC_AVVIE_MASK (0x2000000U) +#define USB_OTGSC_AVVIE_SHIFT (25U) +/*! AVVIE - AVVIE */ +#define USB_OTGSC_AVVIE(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_AVVIE_SHIFT)) & USB_OTGSC_AVVIE_MASK) + +#define USB_OTGSC_ASVIE_MASK (0x4000000U) +#define USB_OTGSC_ASVIE_SHIFT (26U) +/*! ASVIE - ASVIE */ +#define USB_OTGSC_ASVIE(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_ASVIE_SHIFT)) & USB_OTGSC_ASVIE_MASK) + +#define USB_OTGSC_BSVIE_MASK (0x8000000U) +#define USB_OTGSC_BSVIE_SHIFT (27U) +/*! BSVIE - BSVIE */ +#define USB_OTGSC_BSVIE(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_BSVIE_SHIFT)) & USB_OTGSC_BSVIE_MASK) + +#define USB_OTGSC_BSEIE_MASK (0x10000000U) +#define USB_OTGSC_BSEIE_SHIFT (28U) +/*! BSEIE - BSEIE */ +#define USB_OTGSC_BSEIE(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_BSEIE_SHIFT)) & USB_OTGSC_BSEIE_MASK) + +#define USB_OTGSC_EN_1MS_MASK (0x20000000U) +#define USB_OTGSC_EN_1MS_SHIFT (29U) +/*! EN_1MS - EN_1MS */ +#define USB_OTGSC_EN_1MS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_EN_1MS_SHIFT)) & USB_OTGSC_EN_1MS_MASK) + +#define USB_OTGSC_DPIE_MASK (0x40000000U) +#define USB_OTGSC_DPIE_SHIFT (30U) +/*! DPIE - DPIE */ +#define USB_OTGSC_DPIE(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_DPIE_SHIFT)) & USB_OTGSC_DPIE_MASK) +/*! @} */ + +/*! @name USBMODE - USB Device Mode */ +/*! @{ */ + +#define USB_USBMODE_CM_MASK (0x3U) +#define USB_USBMODE_CM_SHIFT (0U) +/*! CM - CM + * 0b00..Idle [Default for combination host/device] + * 0b01..Reserved + * 0b10..Device Controller [Default for device only controller] + * 0b11..Host Controller [Default for host only controller] + */ +#define USB_USBMODE_CM(x) (((uint32_t)(((uint32_t)(x)) << USB_USBMODE_CM_SHIFT)) & USB_USBMODE_CM_MASK) + +#define USB_USBMODE_ES_MASK (0x4U) +#define USB_USBMODE_ES_SHIFT (2U) +/*! ES - ES + * 0b0..Little Endian [Default] + * 0b1..Big Endian + */ +#define USB_USBMODE_ES(x) (((uint32_t)(((uint32_t)(x)) << USB_USBMODE_ES_SHIFT)) & USB_USBMODE_ES_MASK) + +#define USB_USBMODE_SLOM_MASK (0x8U) +#define USB_USBMODE_SLOM_SHIFT (3U) +/*! SLOM - SLOM + * 0b0..Setup Lockouts On (default); + * 0b1..Setup Lockouts Off + */ +#define USB_USBMODE_SLOM(x) (((uint32_t)(((uint32_t)(x)) << USB_USBMODE_SLOM_SHIFT)) & USB_USBMODE_SLOM_MASK) + +#define USB_USBMODE_SDIS_MASK (0x10U) +#define USB_USBMODE_SDIS_SHIFT (4U) +/*! SDIS - SDIS */ +#define USB_USBMODE_SDIS(x) (((uint32_t)(((uint32_t)(x)) << USB_USBMODE_SDIS_SHIFT)) & USB_USBMODE_SDIS_MASK) +/*! @} */ + +/*! @name ENDPTSETUPSTAT - Endpoint Setup Status */ +/*! @{ */ + +#define USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_MASK (0xFFFFU) +#define USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_SHIFT (0U) +/*! ENDPTSETUPSTAT - ENDPTSETUPSTAT */ +#define USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_SHIFT)) & USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_MASK) +/*! @} */ + +/*! @name ENDPTPRIME - Endpoint Prime */ +/*! @{ */ + +#define USB_ENDPTPRIME_PERB_MASK (0xFFU) +#define USB_ENDPTPRIME_PERB_SHIFT (0U) +/*! PERB - PERB */ +#define USB_ENDPTPRIME_PERB(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTPRIME_PERB_SHIFT)) & USB_ENDPTPRIME_PERB_MASK) + +#define USB_ENDPTPRIME_PETB_MASK (0xFF0000U) +#define USB_ENDPTPRIME_PETB_SHIFT (16U) +/*! PETB - PETB */ +#define USB_ENDPTPRIME_PETB(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTPRIME_PETB_SHIFT)) & USB_ENDPTPRIME_PETB_MASK) +/*! @} */ + +/*! @name ENDPTFLUSH - Endpoint Flush */ +/*! @{ */ + +#define USB_ENDPTFLUSH_FERB_MASK (0xFFU) +#define USB_ENDPTFLUSH_FERB_SHIFT (0U) +/*! FERB - FERB */ +#define USB_ENDPTFLUSH_FERB(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTFLUSH_FERB_SHIFT)) & USB_ENDPTFLUSH_FERB_MASK) + +#define USB_ENDPTFLUSH_FETB_MASK (0xFF0000U) +#define USB_ENDPTFLUSH_FETB_SHIFT (16U) +/*! FETB - FETB */ +#define USB_ENDPTFLUSH_FETB(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTFLUSH_FETB_SHIFT)) & USB_ENDPTFLUSH_FETB_MASK) +/*! @} */ + +/*! @name ENDPTSTAT - Endpoint Status */ +/*! @{ */ + +#define USB_ENDPTSTAT_ERBR_MASK (0xFFU) +#define USB_ENDPTSTAT_ERBR_SHIFT (0U) +/*! ERBR - ERBR */ +#define USB_ENDPTSTAT_ERBR(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTSTAT_ERBR_SHIFT)) & USB_ENDPTSTAT_ERBR_MASK) + +#define USB_ENDPTSTAT_ETBR_MASK (0xFF0000U) +#define USB_ENDPTSTAT_ETBR_SHIFT (16U) +/*! ETBR - ETBR */ +#define USB_ENDPTSTAT_ETBR(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTSTAT_ETBR_SHIFT)) & USB_ENDPTSTAT_ETBR_MASK) +/*! @} */ + +/*! @name ENDPTCOMPLETE - Endpoint Complete */ +/*! @{ */ + +#define USB_ENDPTCOMPLETE_ERCE_MASK (0xFFU) +#define USB_ENDPTCOMPLETE_ERCE_SHIFT (0U) +/*! ERCE - ERCE */ +#define USB_ENDPTCOMPLETE_ERCE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCOMPLETE_ERCE_SHIFT)) & USB_ENDPTCOMPLETE_ERCE_MASK) + +#define USB_ENDPTCOMPLETE_ETCE_MASK (0xFF0000U) +#define USB_ENDPTCOMPLETE_ETCE_SHIFT (16U) +/*! ETCE - ETCE */ +#define USB_ENDPTCOMPLETE_ETCE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCOMPLETE_ETCE_SHIFT)) & USB_ENDPTCOMPLETE_ETCE_MASK) +/*! @} */ + +/*! @name ENDPTCTRL0 - Endpoint Control0 */ +/*! @{ */ + +#define USB_ENDPTCTRL0_RXS_MASK (0x1U) +#define USB_ENDPTCTRL0_RXS_SHIFT (0U) +/*! RXS - RXS */ +#define USB_ENDPTCTRL0_RXS(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL0_RXS_SHIFT)) & USB_ENDPTCTRL0_RXS_MASK) + +#define USB_ENDPTCTRL0_RXT_MASK (0xCU) +#define USB_ENDPTCTRL0_RXT_SHIFT (2U) +/*! RXT - RXT */ +#define USB_ENDPTCTRL0_RXT(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL0_RXT_SHIFT)) & USB_ENDPTCTRL0_RXT_MASK) + +#define USB_ENDPTCTRL0_RXE_MASK (0x80U) +#define USB_ENDPTCTRL0_RXE_SHIFT (7U) +/*! RXE - RXE */ +#define USB_ENDPTCTRL0_RXE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL0_RXE_SHIFT)) & USB_ENDPTCTRL0_RXE_MASK) + +#define USB_ENDPTCTRL0_TXS_MASK (0x10000U) +#define USB_ENDPTCTRL0_TXS_SHIFT (16U) +/*! TXS - TXS */ +#define USB_ENDPTCTRL0_TXS(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL0_TXS_SHIFT)) & USB_ENDPTCTRL0_TXS_MASK) + +#define USB_ENDPTCTRL0_TXT_MASK (0xC0000U) +#define USB_ENDPTCTRL0_TXT_SHIFT (18U) +/*! TXT - TXT */ +#define USB_ENDPTCTRL0_TXT(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL0_TXT_SHIFT)) & USB_ENDPTCTRL0_TXT_MASK) + +#define USB_ENDPTCTRL0_TXE_MASK (0x800000U) +#define USB_ENDPTCTRL0_TXE_SHIFT (23U) +/*! TXE - TXE */ +#define USB_ENDPTCTRL0_TXE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL0_TXE_SHIFT)) & USB_ENDPTCTRL0_TXE_MASK) +/*! @} */ + +/*! @name ENDPTCTRL1 - Endpoint Control 1 */ +/*! @{ */ + +#define USB_ENDPTCTRL1_RXS_MASK (0x1U) +#define USB_ENDPTCTRL1_RXS_SHIFT (0U) +/*! RXS - RXS */ +#define USB_ENDPTCTRL1_RXS(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL1_RXS_SHIFT)) & USB_ENDPTCTRL1_RXS_MASK) + +#define USB_ENDPTCTRL1_RXD_MASK (0x2U) +#define USB_ENDPTCTRL1_RXD_SHIFT (1U) +/*! RXD - RXD */ +#define USB_ENDPTCTRL1_RXD(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL1_RXD_SHIFT)) & USB_ENDPTCTRL1_RXD_MASK) + +#define USB_ENDPTCTRL1_RXT_MASK (0xCU) +#define USB_ENDPTCTRL1_RXT_SHIFT (2U) +/*! RXT - RXT */ +#define USB_ENDPTCTRL1_RXT(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL1_RXT_SHIFT)) & USB_ENDPTCTRL1_RXT_MASK) + +#define USB_ENDPTCTRL1_RXI_MASK (0x20U) +#define USB_ENDPTCTRL1_RXI_SHIFT (5U) +/*! RXI - RXI */ +#define USB_ENDPTCTRL1_RXI(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL1_RXI_SHIFT)) & USB_ENDPTCTRL1_RXI_MASK) + +#define USB_ENDPTCTRL1_RXR_MASK (0x40U) +#define USB_ENDPTCTRL1_RXR_SHIFT (6U) +/*! RXR - RXR */ +#define USB_ENDPTCTRL1_RXR(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL1_RXR_SHIFT)) & USB_ENDPTCTRL1_RXR_MASK) + +#define USB_ENDPTCTRL1_RXE_MASK (0x80U) +#define USB_ENDPTCTRL1_RXE_SHIFT (7U) +/*! RXE - RXE */ +#define USB_ENDPTCTRL1_RXE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL1_RXE_SHIFT)) & USB_ENDPTCTRL1_RXE_MASK) + +#define USB_ENDPTCTRL1_TXS_MASK (0x10000U) +#define USB_ENDPTCTRL1_TXS_SHIFT (16U) +/*! TXS - TXS */ +#define USB_ENDPTCTRL1_TXS(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL1_TXS_SHIFT)) & USB_ENDPTCTRL1_TXS_MASK) + +#define USB_ENDPTCTRL1_TXD_MASK (0x20000U) +#define USB_ENDPTCTRL1_TXD_SHIFT (17U) +/*! TXD - TXD */ +#define USB_ENDPTCTRL1_TXD(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL1_TXD_SHIFT)) & USB_ENDPTCTRL1_TXD_MASK) + +#define USB_ENDPTCTRL1_TXT_MASK (0xC0000U) +#define USB_ENDPTCTRL1_TXT_SHIFT (18U) +/*! TXT - TXT */ +#define USB_ENDPTCTRL1_TXT(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL1_TXT_SHIFT)) & USB_ENDPTCTRL1_TXT_MASK) + +#define USB_ENDPTCTRL1_TXI_MASK (0x200000U) +#define USB_ENDPTCTRL1_TXI_SHIFT (21U) +/*! TXI - TXI */ +#define USB_ENDPTCTRL1_TXI(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL1_TXI_SHIFT)) & USB_ENDPTCTRL1_TXI_MASK) + +#define USB_ENDPTCTRL1_TXR_MASK (0x400000U) +#define USB_ENDPTCTRL1_TXR_SHIFT (22U) +/*! TXR - TXR */ +#define USB_ENDPTCTRL1_TXR(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL1_TXR_SHIFT)) & USB_ENDPTCTRL1_TXR_MASK) + +#define USB_ENDPTCTRL1_TXE_MASK (0x800000U) +#define USB_ENDPTCTRL1_TXE_SHIFT (23U) +/*! TXE - TXE */ +#define USB_ENDPTCTRL1_TXE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL1_TXE_SHIFT)) & USB_ENDPTCTRL1_TXE_MASK) +/*! @} */ + +/*! @name ENDPTCTRL2 - Endpoint Control 2 */ +/*! @{ */ + +#define USB_ENDPTCTRL2_RXS_MASK (0x1U) +#define USB_ENDPTCTRL2_RXS_SHIFT (0U) +/*! RXS - RXS */ +#define USB_ENDPTCTRL2_RXS(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL2_RXS_SHIFT)) & USB_ENDPTCTRL2_RXS_MASK) + +#define USB_ENDPTCTRL2_RXD_MASK (0x2U) +#define USB_ENDPTCTRL2_RXD_SHIFT (1U) +/*! RXD - RXD */ +#define USB_ENDPTCTRL2_RXD(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL2_RXD_SHIFT)) & USB_ENDPTCTRL2_RXD_MASK) + +#define USB_ENDPTCTRL2_RXT_MASK (0xCU) +#define USB_ENDPTCTRL2_RXT_SHIFT (2U) +/*! RXT - RXT */ +#define USB_ENDPTCTRL2_RXT(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL2_RXT_SHIFT)) & USB_ENDPTCTRL2_RXT_MASK) + +#define USB_ENDPTCTRL2_RXI_MASK (0x20U) +#define USB_ENDPTCTRL2_RXI_SHIFT (5U) +/*! RXI - RXI */ +#define USB_ENDPTCTRL2_RXI(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL2_RXI_SHIFT)) & USB_ENDPTCTRL2_RXI_MASK) + +#define USB_ENDPTCTRL2_RXR_MASK (0x40U) +#define USB_ENDPTCTRL2_RXR_SHIFT (6U) +/*! RXR - RXR */ +#define USB_ENDPTCTRL2_RXR(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL2_RXR_SHIFT)) & USB_ENDPTCTRL2_RXR_MASK) + +#define USB_ENDPTCTRL2_RXE_MASK (0x80U) +#define USB_ENDPTCTRL2_RXE_SHIFT (7U) +/*! RXE - RXE */ +#define USB_ENDPTCTRL2_RXE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL2_RXE_SHIFT)) & USB_ENDPTCTRL2_RXE_MASK) + +#define USB_ENDPTCTRL2_TXS_MASK (0x10000U) +#define USB_ENDPTCTRL2_TXS_SHIFT (16U) +/*! TXS - TXS */ +#define USB_ENDPTCTRL2_TXS(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL2_TXS_SHIFT)) & USB_ENDPTCTRL2_TXS_MASK) + +#define USB_ENDPTCTRL2_TXD_MASK (0x20000U) +#define USB_ENDPTCTRL2_TXD_SHIFT (17U) +/*! TXD - TXD */ +#define USB_ENDPTCTRL2_TXD(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL2_TXD_SHIFT)) & USB_ENDPTCTRL2_TXD_MASK) + +#define USB_ENDPTCTRL2_TXT_MASK (0xC0000U) +#define USB_ENDPTCTRL2_TXT_SHIFT (18U) +/*! TXT - TXT */ +#define USB_ENDPTCTRL2_TXT(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL2_TXT_SHIFT)) & USB_ENDPTCTRL2_TXT_MASK) + +#define USB_ENDPTCTRL2_TXI_MASK (0x200000U) +#define USB_ENDPTCTRL2_TXI_SHIFT (21U) +/*! TXI - TXI */ +#define USB_ENDPTCTRL2_TXI(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL2_TXI_SHIFT)) & USB_ENDPTCTRL2_TXI_MASK) + +#define USB_ENDPTCTRL2_TXR_MASK (0x400000U) +#define USB_ENDPTCTRL2_TXR_SHIFT (22U) +/*! TXR - TXR */ +#define USB_ENDPTCTRL2_TXR(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL2_TXR_SHIFT)) & USB_ENDPTCTRL2_TXR_MASK) + +#define USB_ENDPTCTRL2_TXE_MASK (0x800000U) +#define USB_ENDPTCTRL2_TXE_SHIFT (23U) +/*! TXE - TXE */ +#define USB_ENDPTCTRL2_TXE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL2_TXE_SHIFT)) & USB_ENDPTCTRL2_TXE_MASK) +/*! @} */ + +/*! @name ENDPTCTRL3 - Endpoint Control 3 */ +/*! @{ */ + +#define USB_ENDPTCTRL3_RXS_MASK (0x1U) +#define USB_ENDPTCTRL3_RXS_SHIFT (0U) +/*! RXS - RXS */ +#define USB_ENDPTCTRL3_RXS(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL3_RXS_SHIFT)) & USB_ENDPTCTRL3_RXS_MASK) + +#define USB_ENDPTCTRL3_RXD_MASK (0x2U) +#define USB_ENDPTCTRL3_RXD_SHIFT (1U) +/*! RXD - RXD */ +#define USB_ENDPTCTRL3_RXD(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL3_RXD_SHIFT)) & USB_ENDPTCTRL3_RXD_MASK) + +#define USB_ENDPTCTRL3_RXT_MASK (0xCU) +#define USB_ENDPTCTRL3_RXT_SHIFT (2U) +/*! RXT - RXT */ +#define USB_ENDPTCTRL3_RXT(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL3_RXT_SHIFT)) & USB_ENDPTCTRL3_RXT_MASK) + +#define USB_ENDPTCTRL3_RXI_MASK (0x20U) +#define USB_ENDPTCTRL3_RXI_SHIFT (5U) +/*! RXI - RXI */ +#define USB_ENDPTCTRL3_RXI(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL3_RXI_SHIFT)) & USB_ENDPTCTRL3_RXI_MASK) + +#define USB_ENDPTCTRL3_RXR_MASK (0x40U) +#define USB_ENDPTCTRL3_RXR_SHIFT (6U) +/*! RXR - RXR */ +#define USB_ENDPTCTRL3_RXR(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL3_RXR_SHIFT)) & USB_ENDPTCTRL3_RXR_MASK) + +#define USB_ENDPTCTRL3_RXE_MASK (0x80U) +#define USB_ENDPTCTRL3_RXE_SHIFT (7U) +/*! RXE - RXE */ +#define USB_ENDPTCTRL3_RXE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL3_RXE_SHIFT)) & USB_ENDPTCTRL3_RXE_MASK) + +#define USB_ENDPTCTRL3_TXS_MASK (0x10000U) +#define USB_ENDPTCTRL3_TXS_SHIFT (16U) +/*! TXS - TXS */ +#define USB_ENDPTCTRL3_TXS(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL3_TXS_SHIFT)) & USB_ENDPTCTRL3_TXS_MASK) + +#define USB_ENDPTCTRL3_TXD_MASK (0x20000U) +#define USB_ENDPTCTRL3_TXD_SHIFT (17U) +/*! TXD - TXD */ +#define USB_ENDPTCTRL3_TXD(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL3_TXD_SHIFT)) & USB_ENDPTCTRL3_TXD_MASK) + +#define USB_ENDPTCTRL3_TXT_MASK (0xC0000U) +#define USB_ENDPTCTRL3_TXT_SHIFT (18U) +/*! TXT - TXT */ +#define USB_ENDPTCTRL3_TXT(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL3_TXT_SHIFT)) & USB_ENDPTCTRL3_TXT_MASK) + +#define USB_ENDPTCTRL3_TXI_MASK (0x200000U) +#define USB_ENDPTCTRL3_TXI_SHIFT (21U) +/*! TXI - TXI */ +#define USB_ENDPTCTRL3_TXI(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL3_TXI_SHIFT)) & USB_ENDPTCTRL3_TXI_MASK) + +#define USB_ENDPTCTRL3_TXR_MASK (0x400000U) +#define USB_ENDPTCTRL3_TXR_SHIFT (22U) +/*! TXR - TXR */ +#define USB_ENDPTCTRL3_TXR(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL3_TXR_SHIFT)) & USB_ENDPTCTRL3_TXR_MASK) + +#define USB_ENDPTCTRL3_TXE_MASK (0x800000U) +#define USB_ENDPTCTRL3_TXE_SHIFT (23U) +/*! TXE - TXE */ +#define USB_ENDPTCTRL3_TXE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL3_TXE_SHIFT)) & USB_ENDPTCTRL3_TXE_MASK) +/*! @} */ + +/*! @name ENDPTCTRL4 - Endpoint Control 4 */ +/*! @{ */ + +#define USB_ENDPTCTRL4_RXS_MASK (0x1U) +#define USB_ENDPTCTRL4_RXS_SHIFT (0U) +/*! RXS - RXS */ +#define USB_ENDPTCTRL4_RXS(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL4_RXS_SHIFT)) & USB_ENDPTCTRL4_RXS_MASK) + +#define USB_ENDPTCTRL4_RXD_MASK (0x2U) +#define USB_ENDPTCTRL4_RXD_SHIFT (1U) +/*! RXD - RXD */ +#define USB_ENDPTCTRL4_RXD(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL4_RXD_SHIFT)) & USB_ENDPTCTRL4_RXD_MASK) + +#define USB_ENDPTCTRL4_RXT_MASK (0xCU) +#define USB_ENDPTCTRL4_RXT_SHIFT (2U) +/*! RXT - RXT */ +#define USB_ENDPTCTRL4_RXT(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL4_RXT_SHIFT)) & USB_ENDPTCTRL4_RXT_MASK) + +#define USB_ENDPTCTRL4_RXI_MASK (0x20U) +#define USB_ENDPTCTRL4_RXI_SHIFT (5U) +/*! RXI - RXI */ +#define USB_ENDPTCTRL4_RXI(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL4_RXI_SHIFT)) & USB_ENDPTCTRL4_RXI_MASK) + +#define USB_ENDPTCTRL4_RXR_MASK (0x40U) +#define USB_ENDPTCTRL4_RXR_SHIFT (6U) +/*! RXR - RXR */ +#define USB_ENDPTCTRL4_RXR(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL4_RXR_SHIFT)) & USB_ENDPTCTRL4_RXR_MASK) + +#define USB_ENDPTCTRL4_RXE_MASK (0x80U) +#define USB_ENDPTCTRL4_RXE_SHIFT (7U) +/*! RXE - RXE */ +#define USB_ENDPTCTRL4_RXE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL4_RXE_SHIFT)) & USB_ENDPTCTRL4_RXE_MASK) + +#define USB_ENDPTCTRL4_TXS_MASK (0x10000U) +#define USB_ENDPTCTRL4_TXS_SHIFT (16U) +/*! TXS - TXS */ +#define USB_ENDPTCTRL4_TXS(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL4_TXS_SHIFT)) & USB_ENDPTCTRL4_TXS_MASK) + +#define USB_ENDPTCTRL4_TXD_MASK (0x20000U) +#define USB_ENDPTCTRL4_TXD_SHIFT (17U) +/*! TXD - TXD */ +#define USB_ENDPTCTRL4_TXD(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL4_TXD_SHIFT)) & USB_ENDPTCTRL4_TXD_MASK) + +#define USB_ENDPTCTRL4_TXT_MASK (0xC0000U) +#define USB_ENDPTCTRL4_TXT_SHIFT (18U) +/*! TXT - TXT */ +#define USB_ENDPTCTRL4_TXT(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL4_TXT_SHIFT)) & USB_ENDPTCTRL4_TXT_MASK) + +#define USB_ENDPTCTRL4_TXI_MASK (0x200000U) +#define USB_ENDPTCTRL4_TXI_SHIFT (21U) +/*! TXI - TXI */ +#define USB_ENDPTCTRL4_TXI(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL4_TXI_SHIFT)) & USB_ENDPTCTRL4_TXI_MASK) + +#define USB_ENDPTCTRL4_TXR_MASK (0x400000U) +#define USB_ENDPTCTRL4_TXR_SHIFT (22U) +/*! TXR - TXR */ +#define USB_ENDPTCTRL4_TXR(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL4_TXR_SHIFT)) & USB_ENDPTCTRL4_TXR_MASK) + +#define USB_ENDPTCTRL4_TXE_MASK (0x800000U) +#define USB_ENDPTCTRL4_TXE_SHIFT (23U) +/*! TXE - TXE */ +#define USB_ENDPTCTRL4_TXE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL4_TXE_SHIFT)) & USB_ENDPTCTRL4_TXE_MASK) +/*! @} */ + +/*! @name ENDPTCTRL5 - Endpoint Control 5 */ +/*! @{ */ + +#define USB_ENDPTCTRL5_RXS_MASK (0x1U) +#define USB_ENDPTCTRL5_RXS_SHIFT (0U) +/*! RXS - RXS */ +#define USB_ENDPTCTRL5_RXS(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL5_RXS_SHIFT)) & USB_ENDPTCTRL5_RXS_MASK) + +#define USB_ENDPTCTRL5_RXD_MASK (0x2U) +#define USB_ENDPTCTRL5_RXD_SHIFT (1U) +/*! RXD - RXD */ +#define USB_ENDPTCTRL5_RXD(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL5_RXD_SHIFT)) & USB_ENDPTCTRL5_RXD_MASK) + +#define USB_ENDPTCTRL5_RXT_MASK (0xCU) +#define USB_ENDPTCTRL5_RXT_SHIFT (2U) +/*! RXT - RXT */ +#define USB_ENDPTCTRL5_RXT(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL5_RXT_SHIFT)) & USB_ENDPTCTRL5_RXT_MASK) + +#define USB_ENDPTCTRL5_RXI_MASK (0x20U) +#define USB_ENDPTCTRL5_RXI_SHIFT (5U) +/*! RXI - RXI */ +#define USB_ENDPTCTRL5_RXI(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL5_RXI_SHIFT)) & USB_ENDPTCTRL5_RXI_MASK) + +#define USB_ENDPTCTRL5_RXR_MASK (0x40U) +#define USB_ENDPTCTRL5_RXR_SHIFT (6U) +/*! RXR - RXR */ +#define USB_ENDPTCTRL5_RXR(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL5_RXR_SHIFT)) & USB_ENDPTCTRL5_RXR_MASK) + +#define USB_ENDPTCTRL5_RXE_MASK (0x80U) +#define USB_ENDPTCTRL5_RXE_SHIFT (7U) +/*! RXE - RXE */ +#define USB_ENDPTCTRL5_RXE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL5_RXE_SHIFT)) & USB_ENDPTCTRL5_RXE_MASK) + +#define USB_ENDPTCTRL5_TXS_MASK (0x10000U) +#define USB_ENDPTCTRL5_TXS_SHIFT (16U) +/*! TXS - TXS */ +#define USB_ENDPTCTRL5_TXS(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL5_TXS_SHIFT)) & USB_ENDPTCTRL5_TXS_MASK) + +#define USB_ENDPTCTRL5_TXD_MASK (0x20000U) +#define USB_ENDPTCTRL5_TXD_SHIFT (17U) +/*! TXD - TXD */ +#define USB_ENDPTCTRL5_TXD(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL5_TXD_SHIFT)) & USB_ENDPTCTRL5_TXD_MASK) + +#define USB_ENDPTCTRL5_TXT_MASK (0xC0000U) +#define USB_ENDPTCTRL5_TXT_SHIFT (18U) +/*! TXT - TXT */ +#define USB_ENDPTCTRL5_TXT(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL5_TXT_SHIFT)) & USB_ENDPTCTRL5_TXT_MASK) + +#define USB_ENDPTCTRL5_TXI_MASK (0x200000U) +#define USB_ENDPTCTRL5_TXI_SHIFT (21U) +/*! TXI - TXI */ +#define USB_ENDPTCTRL5_TXI(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL5_TXI_SHIFT)) & USB_ENDPTCTRL5_TXI_MASK) + +#define USB_ENDPTCTRL5_TXR_MASK (0x400000U) +#define USB_ENDPTCTRL5_TXR_SHIFT (22U) +/*! TXR - TXR */ +#define USB_ENDPTCTRL5_TXR(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL5_TXR_SHIFT)) & USB_ENDPTCTRL5_TXR_MASK) + +#define USB_ENDPTCTRL5_TXE_MASK (0x800000U) +#define USB_ENDPTCTRL5_TXE_SHIFT (23U) +/*! TXE - TXE */ +#define USB_ENDPTCTRL5_TXE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL5_TXE_SHIFT)) & USB_ENDPTCTRL5_TXE_MASK) +/*! @} */ + +/*! @name ENDPTCTRL6 - Endpoint Control 6 */ +/*! @{ */ + +#define USB_ENDPTCTRL6_RXS_MASK (0x1U) +#define USB_ENDPTCTRL6_RXS_SHIFT (0U) +/*! RXS - RXS */ +#define USB_ENDPTCTRL6_RXS(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL6_RXS_SHIFT)) & USB_ENDPTCTRL6_RXS_MASK) + +#define USB_ENDPTCTRL6_RXD_MASK (0x2U) +#define USB_ENDPTCTRL6_RXD_SHIFT (1U) +/*! RXD - RXD */ +#define USB_ENDPTCTRL6_RXD(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL6_RXD_SHIFT)) & USB_ENDPTCTRL6_RXD_MASK) + +#define USB_ENDPTCTRL6_RXT_MASK (0xCU) +#define USB_ENDPTCTRL6_RXT_SHIFT (2U) +/*! RXT - RXT */ +#define USB_ENDPTCTRL6_RXT(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL6_RXT_SHIFT)) & USB_ENDPTCTRL6_RXT_MASK) + +#define USB_ENDPTCTRL6_RXI_MASK (0x20U) +#define USB_ENDPTCTRL6_RXI_SHIFT (5U) +/*! RXI - RXI */ +#define USB_ENDPTCTRL6_RXI(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL6_RXI_SHIFT)) & USB_ENDPTCTRL6_RXI_MASK) + +#define USB_ENDPTCTRL6_RXR_MASK (0x40U) +#define USB_ENDPTCTRL6_RXR_SHIFT (6U) +/*! RXR - RXR */ +#define USB_ENDPTCTRL6_RXR(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL6_RXR_SHIFT)) & USB_ENDPTCTRL6_RXR_MASK) + +#define USB_ENDPTCTRL6_RXE_MASK (0x80U) +#define USB_ENDPTCTRL6_RXE_SHIFT (7U) +/*! RXE - RXE */ +#define USB_ENDPTCTRL6_RXE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL6_RXE_SHIFT)) & USB_ENDPTCTRL6_RXE_MASK) + +#define USB_ENDPTCTRL6_TXS_MASK (0x10000U) +#define USB_ENDPTCTRL6_TXS_SHIFT (16U) +/*! TXS - TXS */ +#define USB_ENDPTCTRL6_TXS(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL6_TXS_SHIFT)) & USB_ENDPTCTRL6_TXS_MASK) + +#define USB_ENDPTCTRL6_TXD_MASK (0x20000U) +#define USB_ENDPTCTRL6_TXD_SHIFT (17U) +/*! TXD - TXD */ +#define USB_ENDPTCTRL6_TXD(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL6_TXD_SHIFT)) & USB_ENDPTCTRL6_TXD_MASK) + +#define USB_ENDPTCTRL6_TXT_MASK (0xC0000U) +#define USB_ENDPTCTRL6_TXT_SHIFT (18U) +/*! TXT - TXT */ +#define USB_ENDPTCTRL6_TXT(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL6_TXT_SHIFT)) & USB_ENDPTCTRL6_TXT_MASK) + +#define USB_ENDPTCTRL6_TXI_MASK (0x200000U) +#define USB_ENDPTCTRL6_TXI_SHIFT (21U) +/*! TXI - TXI */ +#define USB_ENDPTCTRL6_TXI(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL6_TXI_SHIFT)) & USB_ENDPTCTRL6_TXI_MASK) + +#define USB_ENDPTCTRL6_TXR_MASK (0x400000U) +#define USB_ENDPTCTRL6_TXR_SHIFT (22U) +/*! TXR - TXR */ +#define USB_ENDPTCTRL6_TXR(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL6_TXR_SHIFT)) & USB_ENDPTCTRL6_TXR_MASK) + +#define USB_ENDPTCTRL6_TXE_MASK (0x800000U) +#define USB_ENDPTCTRL6_TXE_SHIFT (23U) +/*! TXE - TXE */ +#define USB_ENDPTCTRL6_TXE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL6_TXE_SHIFT)) & USB_ENDPTCTRL6_TXE_MASK) +/*! @} */ + +/*! @name ENDPTCTRL7 - Endpoint Control 7 */ +/*! @{ */ + +#define USB_ENDPTCTRL7_RXS_MASK (0x1U) +#define USB_ENDPTCTRL7_RXS_SHIFT (0U) +/*! RXS - RXS */ +#define USB_ENDPTCTRL7_RXS(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL7_RXS_SHIFT)) & USB_ENDPTCTRL7_RXS_MASK) + +#define USB_ENDPTCTRL7_RXD_MASK (0x2U) +#define USB_ENDPTCTRL7_RXD_SHIFT (1U) +/*! RXD - RXD */ +#define USB_ENDPTCTRL7_RXD(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL7_RXD_SHIFT)) & USB_ENDPTCTRL7_RXD_MASK) + +#define USB_ENDPTCTRL7_RXT_MASK (0xCU) +#define USB_ENDPTCTRL7_RXT_SHIFT (2U) +/*! RXT - RXT */ +#define USB_ENDPTCTRL7_RXT(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL7_RXT_SHIFT)) & USB_ENDPTCTRL7_RXT_MASK) + +#define USB_ENDPTCTRL7_RXI_MASK (0x20U) +#define USB_ENDPTCTRL7_RXI_SHIFT (5U) +/*! RXI - RXI */ +#define USB_ENDPTCTRL7_RXI(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL7_RXI_SHIFT)) & USB_ENDPTCTRL7_RXI_MASK) + +#define USB_ENDPTCTRL7_RXR_MASK (0x40U) +#define USB_ENDPTCTRL7_RXR_SHIFT (6U) +/*! RXR - RXR */ +#define USB_ENDPTCTRL7_RXR(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL7_RXR_SHIFT)) & USB_ENDPTCTRL7_RXR_MASK) + +#define USB_ENDPTCTRL7_RXE_MASK (0x80U) +#define USB_ENDPTCTRL7_RXE_SHIFT (7U) +/*! RXE - RXE */ +#define USB_ENDPTCTRL7_RXE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL7_RXE_SHIFT)) & USB_ENDPTCTRL7_RXE_MASK) + +#define USB_ENDPTCTRL7_TXS_MASK (0x10000U) +#define USB_ENDPTCTRL7_TXS_SHIFT (16U) +/*! TXS - TXS */ +#define USB_ENDPTCTRL7_TXS(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL7_TXS_SHIFT)) & USB_ENDPTCTRL7_TXS_MASK) + +#define USB_ENDPTCTRL7_TXD_MASK (0x20000U) +#define USB_ENDPTCTRL7_TXD_SHIFT (17U) +/*! TXD - TXD */ +#define USB_ENDPTCTRL7_TXD(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL7_TXD_SHIFT)) & USB_ENDPTCTRL7_TXD_MASK) + +#define USB_ENDPTCTRL7_TXT_MASK (0xC0000U) +#define USB_ENDPTCTRL7_TXT_SHIFT (18U) +/*! TXT - TXT */ +#define USB_ENDPTCTRL7_TXT(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL7_TXT_SHIFT)) & USB_ENDPTCTRL7_TXT_MASK) + +#define USB_ENDPTCTRL7_TXI_MASK (0x200000U) +#define USB_ENDPTCTRL7_TXI_SHIFT (21U) +/*! TXI - TXI */ +#define USB_ENDPTCTRL7_TXI(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL7_TXI_SHIFT)) & USB_ENDPTCTRL7_TXI_MASK) + +#define USB_ENDPTCTRL7_TXR_MASK (0x400000U) +#define USB_ENDPTCTRL7_TXR_SHIFT (22U) +/*! TXR - TXR */ +#define USB_ENDPTCTRL7_TXR(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL7_TXR_SHIFT)) & USB_ENDPTCTRL7_TXR_MASK) + +#define USB_ENDPTCTRL7_TXE_MASK (0x800000U) +#define USB_ENDPTCTRL7_TXE_SHIFT (23U) +/*! TXE - TXE */ +#define USB_ENDPTCTRL7_TXE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL7_TXE_SHIFT)) & USB_ENDPTCTRL7_TXE_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group USB_Register_Masks */ + + +/* USB - Peripheral instance base addresses */ +/** Peripheral USB__USB_OTG1 base address */ +#define USB__USB_OTG1_BASE (0x4C100000u) +/** Peripheral USB__USB_OTG1 base pointer */ +#define USB__USB_OTG1 ((USB_Type *)USB__USB_OTG1_BASE) +/** Peripheral USB__USB_OTG2 base address */ +#define USB__USB_OTG2_BASE (0x4C200000u) +/** Peripheral USB__USB_OTG2 base pointer */ +#define USB__USB_OTG2 ((USB_Type *)USB__USB_OTG2_BASE) +/** Array initializer of USB peripheral base addresses */ +#define USB_BASE_ADDRS { USB__USB_OTG1_BASE, USB__USB_OTG2_BASE } +/** Array initializer of USB peripheral base pointers */ +#define USB_BASE_PTRS { USB__USB_OTG1, USB__USB_OTG2 } + +/*! + * @} + */ /* end of group USB_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- USBNC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USBNC_Peripheral_Access_Layer USBNC Peripheral Access Layer + * @{ + */ + +/** USBNC - Register Layout Typedef */ +typedef struct { + __IO uint32_t CTRL1; /**< USB OTG Control 1, offset: 0x0 */ + __IO uint32_t CTRL2; /**< USB OTG Control 2, offset: 0x4 */ + uint8_t RESERVED_0[36]; + __IO uint32_t HSIC_DLL_CFG4; /**< HSIC DLL Configure Register 4, offset: 0x2C */ + __IO uint32_t UTMIPHY_CFG1; /**< PHY Configure 1, offset: 0x30 */ +} USBNC_Type; + +/* ---------------------------------------------------------------------------- + -- USBNC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USBNC_Register_Masks USBNC Register Masks + * @{ + */ + +/*! @name CTRL1 - USB OTG Control 1 */ +/*! @{ */ + +#define USBNC_CTRL1_OVER_CUR_DIS_MASK (0x80U) +#define USBNC_CTRL1_OVER_CUR_DIS_SHIFT (7U) +/*! OVER_CUR_DIS - OVER_CUR_DIS + * 0b0..Enables overcurrent detection + * 0b1..Disables overcurrent detection + */ +#define USBNC_CTRL1_OVER_CUR_DIS(x) (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL1_OVER_CUR_DIS_SHIFT)) & USBNC_CTRL1_OVER_CUR_DIS_MASK) + +#define USBNC_CTRL1_OVER_CUR_POL_MASK (0x100U) +#define USBNC_CTRL1_OVER_CUR_POL_SHIFT (8U) +/*! OVER_CUR_POL - OVER_CUR_POL + * 0b0..High active (high on this signal represents an overcurrent condition) + * 0b1..Low active (low on this signal represents an overcurrent condition) + */ +#define USBNC_CTRL1_OVER_CUR_POL(x) (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL1_OVER_CUR_POL_SHIFT)) & USBNC_CTRL1_OVER_CUR_POL_MASK) + +#define USBNC_CTRL1_PWR_POL_MASK (0x200U) +#define USBNC_CTRL1_PWR_POL_SHIFT (9U) +/*! PWR_POL - PWR_POL + * 0b0..PMIC Power Pin is Low active. + * 0b1..PMIC Power Pin is High active. + */ +#define USBNC_CTRL1_PWR_POL(x) (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL1_PWR_POL_SHIFT)) & USBNC_CTRL1_PWR_POL_MASK) + +#define USBNC_CTRL1_WIE_MASK (0x400U) +#define USBNC_CTRL1_WIE_SHIFT (10U) +/*! WIE - WIE + * 0b0..Interrupt Disabled + * 0b1..Interrupt Enabled + */ +#define USBNC_CTRL1_WIE(x) (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL1_WIE_SHIFT)) & USBNC_CTRL1_WIE_MASK) + +#define USBNC_CTRL1_WKUP_SW_EN_MASK (0x4000U) +#define USBNC_CTRL1_WKUP_SW_EN_SHIFT (14U) +/*! WKUP_SW_EN - WKUP_SW_EN + * 0b0..Disable + * 0b1..Enable + */ +#define USBNC_CTRL1_WKUP_SW_EN(x) (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL1_WKUP_SW_EN_SHIFT)) & USBNC_CTRL1_WKUP_SW_EN_MASK) + +#define USBNC_CTRL1_WKUP_SW_MASK (0x8000U) +#define USBNC_CTRL1_WKUP_SW_SHIFT (15U) +/*! WKUP_SW - WKUP_SW + * 0b0..Inactive + * 0b1..Force wake-up + */ +#define USBNC_CTRL1_WKUP_SW(x) (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL1_WKUP_SW_SHIFT)) & USBNC_CTRL1_WKUP_SW_MASK) + +#define USBNC_CTRL1_WKUP_ID_EN_MASK (0x10000U) +#define USBNC_CTRL1_WKUP_ID_EN_SHIFT (16U) +/*! WKUP_ID_EN - WKUP_ID_EN + * 0b0..Disable + * 0b1..Enable + */ +#define USBNC_CTRL1_WKUP_ID_EN(x) (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL1_WKUP_ID_EN_SHIFT)) & USBNC_CTRL1_WKUP_ID_EN_MASK) + +#define USBNC_CTRL1_WKUP_VBUS_EN_MASK (0x20000U) +#define USBNC_CTRL1_WKUP_VBUS_EN_SHIFT (17U) +/*! WKUP_VBUS_EN - WKUP_VBUS_EN + * 0b0..Disable + * 0b1..Enable + */ +#define USBNC_CTRL1_WKUP_VBUS_EN(x) (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL1_WKUP_VBUS_EN_SHIFT)) & USBNC_CTRL1_WKUP_VBUS_EN_MASK) + +#define USBNC_CTRL1_WKUP_DPDM_EN_MASK (0x20000000U) +#define USBNC_CTRL1_WKUP_DPDM_EN_SHIFT (29U) +/*! WKUP_DPDM_EN - Wake-up on DP/DM change enable + * 0b0..DP/DM changes wake-up to be disabled only when VBUS is 0. + * 0b1..(Default) DP/DM changes wake-up to be enabled, it is for device only. + */ +#define USBNC_CTRL1_WKUP_DPDM_EN(x) (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL1_WKUP_DPDM_EN_SHIFT)) & USBNC_CTRL1_WKUP_DPDM_EN_MASK) + +#define USBNC_CTRL1_WIR_MASK (0x80000000U) +#define USBNC_CTRL1_WIR_SHIFT (31U) +/*! WIR - WIR + * 0b0..No wake-up interrupt request received + * 0b1..Wake-up Interrupt Request received + */ +#define USBNC_CTRL1_WIR(x) (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL1_WIR_SHIFT)) & USBNC_CTRL1_WIR_MASK) +/*! @} */ + +/*! @name CTRL2 - USB OTG Control 2 */ +/*! @{ */ + +#define USBNC_CTRL2_VBUS_SOURCE_SEL_MASK (0x3U) +#define USBNC_CTRL2_VBUS_SOURCE_SEL_SHIFT (0U) +/*! VBUS_SOURCE_SEL - VBUS_SOURCE_SEL + * 0b00..vbus_valid + * 0b01..sess_valid + * 0b10..sess_valid + * 0b11..sess_valid + */ +#define USBNC_CTRL2_VBUS_SOURCE_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL2_VBUS_SOURCE_SEL_SHIFT)) & USBNC_CTRL2_VBUS_SOURCE_SEL_MASK) + +#define USBNC_CTRL2_AUTURESUME_EN_MASK (0x4U) +#define USBNC_CTRL2_AUTURESUME_EN_SHIFT (2U) +/*! AUTURESUME_EN - Auto Resume Enable + * 0b0..Default + */ +#define USBNC_CTRL2_AUTURESUME_EN(x) (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL2_AUTURESUME_EN_SHIFT)) & USBNC_CTRL2_AUTURESUME_EN_MASK) + +#define USBNC_CTRL2_LOWSPEED_EN_MASK (0x8U) +#define USBNC_CTRL2_LOWSPEED_EN_SHIFT (3U) +/*! LOWSPEED_EN - Low speed enable + * 0b0..Default + */ +#define USBNC_CTRL2_LOWSPEED_EN(x) (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL2_LOWSPEED_EN_SHIFT)) & USBNC_CTRL2_LOWSPEED_EN_MASK) + +#define USBNC_CTRL2_OPMODE_OVERRIDE_MASK (0xC0U) +#define USBNC_CTRL2_OPMODE_OVERRIDE_SHIFT (6U) +/*! OPMODE_OVERRIDE - utmi_OpMode[1:0] override value + * 0b00..utmi_OpMode[1:0] override to 2'b00. + * 0b01..utmi_OpMode[1:0] override to 2'b01. + * 0b10..utmi_OpMode[1:0] override to 2'b10. + * 0b11..utmi_OpMode[1:0] override to 2'b11. + */ +#define USBNC_CTRL2_OPMODE_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL2_OPMODE_OVERRIDE_SHIFT)) & USBNC_CTRL2_OPMODE_OVERRIDE_MASK) + +#define USBNC_CTRL2_OPMODE_OVERRIDEEN_MASK (0x100U) +#define USBNC_CTRL2_OPMODE_OVERRIDEEN_SHIFT (8U) +/*! OPMODE_OVERRIDEEN - utmi_OpMode[1:0] override enable + * 0b0..utmi_OpMode[1:0] override disable. + * 0b1..utmi_OpMode[1:0] override enable. + */ +#define USBNC_CTRL2_OPMODE_OVERRIDEEN(x) (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL2_OPMODE_OVERRIDEEN_SHIFT)) & USBNC_CTRL2_OPMODE_OVERRIDEEN_MASK) + +#define USBNC_CTRL2_SHORT_PKT_EN_MASK (0x800000U) +#define USBNC_CTRL2_SHORT_PKT_EN_SHIFT (23U) +/*! SHORT_PKT_EN - Short Packet Interrupt + * 0b0..Default + */ +#define USBNC_CTRL2_SHORT_PKT_EN(x) (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL2_SHORT_PKT_EN_SHIFT)) & USBNC_CTRL2_SHORT_PKT_EN_MASK) + +#define USBNC_CTRL2_UTMI_CLK_VLD_MASK (0x80000000U) +#define USBNC_CTRL2_UTMI_CLK_VLD_SHIFT (31U) +/*! UTMI_CLK_VLD - UTMI_CLK_VLD + * 0b0..Default + */ +#define USBNC_CTRL2_UTMI_CLK_VLD(x) (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL2_UTMI_CLK_VLD_SHIFT)) & USBNC_CTRL2_UTMI_CLK_VLD_MASK) +/*! @} */ + +/*! @name HSIC_DLL_CFG4 - HSIC DLL Configure Register 4 */ +/*! @{ */ + +#define USBNC_HSIC_DLL_CFG4_FS_ISO_B2B_FIXEN_MASK (0x80000000U) +#define USBNC_HSIC_DLL_CFG4_FS_ISO_B2B_FIXEN_SHIFT (31U) +/*! FS_ISO_B2B_FIXEN - FS Isochronous Back to Back Transfer Enable + * 0b0..Disable + * 0b1..Enable + */ +#define USBNC_HSIC_DLL_CFG4_FS_ISO_B2B_FIXEN(x) (((uint32_t)(((uint32_t)(x)) << USBNC_HSIC_DLL_CFG4_FS_ISO_B2B_FIXEN_SHIFT)) & USBNC_HSIC_DLL_CFG4_FS_ISO_B2B_FIXEN_MASK) +/*! @} */ + +/*! @name UTMIPHY_CFG1 - PHY Configure 1 */ +/*! @{ */ + +#define USBNC_UTMIPHY_CFG1_COMPDISTUNE0_MASK (0x70U) +#define USBNC_UTMIPHY_CFG1_COMPDISTUNE0_SHIFT (4U) +/*! COMPDISTUNE0 - Disconnect Threshold Adjustment + * 0b000..-9.71% + * 0b001..-6.85% + * 0b010..-3.36% + * 0b011..0, Design default + * 0b100..+4.04% + * 0b101..+8.22% + * 0b110..+13.18% + * 0b111..+18.39% + */ +#define USBNC_UTMIPHY_CFG1_COMPDISTUNE0(x) (((uint32_t)(((uint32_t)(x)) << USBNC_UTMIPHY_CFG1_COMPDISTUNE0_SHIFT)) & USBNC_UTMIPHY_CFG1_COMPDISTUNE0_MASK) + +#define USBNC_UTMIPHY_CFG1_SQRXTUNE0_MASK (0x380U) +#define USBNC_UTMIPHY_CFG1_SQRXTUNE0_SHIFT (7U) +/*! SQRXTUNE0 - Squelch Threshold Adjustment + * 0b000..+15.19% + * 0b001..+10.04% + * 0b010..+5.14% + * 0b011..0, design default + * 0b100..-5.04% + * 0b101..-10.19% + * 0b110..-15.09% + * 0b111..-20.24% + */ +#define USBNC_UTMIPHY_CFG1_SQRXTUNE0(x) (((uint32_t)(((uint32_t)(x)) << USBNC_UTMIPHY_CFG1_SQRXTUNE0_SHIFT)) & USBNC_UTMIPHY_CFG1_SQRXTUNE0_MASK) + +#define USBNC_UTMIPHY_CFG1_OTGTUNE0_MASK (0x1C00U) +#define USBNC_UTMIPHY_CFG1_OTGTUNE0_SHIFT (10U) +/*! OTGTUNE0 - VBUS Valid Threshold Adjustment + * 0b000..-9% + * 0b001..-6% + * 0b010..-3% + * 0b011..0, Design default + * 0b100..+3% + * 0b101..+6% + * 0b110..+9% + * 0b111..+12% + */ +#define USBNC_UTMIPHY_CFG1_OTGTUNE0(x) (((uint32_t)(((uint32_t)(x)) << USBNC_UTMIPHY_CFG1_OTGTUNE0_SHIFT)) & USBNC_UTMIPHY_CFG1_OTGTUNE0_MASK) + +#define USBNC_UTMIPHY_CFG1_TXHSXVTUNE0_MASK (0x6000U) +#define USBNC_UTMIPHY_CFG1_TXHSXVTUNE0_SHIFT (13U) +/*! TXHSXVTUNE0 - Transmitter High-Speed Crossover Adjustment + * 0b00..Reserved + * 0b01..-17.31 mV + * 0b10..-16.69 mV + * 0b11..0, design default + */ +#define USBNC_UTMIPHY_CFG1_TXHSXVTUNE0(x) (((uint32_t)(((uint32_t)(x)) << USBNC_UTMIPHY_CFG1_TXHSXVTUNE0_SHIFT)) & USBNC_UTMIPHY_CFG1_TXHSXVTUNE0_MASK) + +#define USBNC_UTMIPHY_CFG1_PHY_POR_SW_MASK (0x8000U) +#define USBNC_UTMIPHY_CFG1_PHY_POR_SW_SHIFT (15U) +/*! PHY_POR_SW - PHY software POR + * 0b0..Do not perform the Power-On Reset by software. + * 0b1..Perform the Power-On Reset by software. + */ +#define USBNC_UTMIPHY_CFG1_PHY_POR_SW(x) (((uint32_t)(((uint32_t)(x)) << USBNC_UTMIPHY_CFG1_PHY_POR_SW_SHIFT)) & USBNC_UTMIPHY_CFG1_PHY_POR_SW_MASK) + +#define USBNC_UTMIPHY_CFG1_TXFSLSTUNE0_MASK (0xF0000U) +#define USBNC_UTMIPHY_CFG1_TXFSLSTUNE0_SHIFT (16U) +/*! TXFSLSTUNE0 - FS/LS Source Impedance Adjustment + * 0b0000..+6.27% + * 0b0001..+3.02% + * 0b0011..0, design default + * 0b0111..-3.23% + * 0b1111..-6.25% + */ +#define USBNC_UTMIPHY_CFG1_TXFSLSTUNE0(x) (((uint32_t)(((uint32_t)(x)) << USBNC_UTMIPHY_CFG1_TXFSLSTUNE0_SHIFT)) & USBNC_UTMIPHY_CFG1_TXFSLSTUNE0_MASK) + +#define USBNC_UTMIPHY_CFG1_TXVREFTUNE0_MASK (0xF00000U) +#define USBNC_UTMIPHY_CFG1_TXVREFTUNE0_SHIFT (20U) +/*! TXVREFTUNE0 - HS DC Voltage Level Adjustment + * 0b0000..-5.88% + * 0b0001..-3.92% + * 0b0010..-1.96% + * 0b0011..0, design default + * 0b0100..+1.96% + * 0b0101..+3.92% + * 0b0110..+5.88% + * 0b0111..+7.84% + * 0b1000..+9.80% + * 0b1001..+11.75% + * 0b1010..+13.71% + * 0b1011..+15.67% + * 0b1100..+17.63% + * 0b1101..+19.59% + * 0b1110..+21.55% + * 0b1111..+23.51% + */ +#define USBNC_UTMIPHY_CFG1_TXVREFTUNE0(x) (((uint32_t)(((uint32_t)(x)) << USBNC_UTMIPHY_CFG1_TXVREFTUNE0_SHIFT)) & USBNC_UTMIPHY_CFG1_TXVREFTUNE0_MASK) + +#define USBNC_UTMIPHY_CFG1_TXRISETUNE0_MASK (0x3000000U) +#define USBNC_UTMIPHY_CFG1_TXRISETUNE0_SHIFT (24U) +/*! TXRISETUNE0 - HS Transmitter Rise/Fall Time Adjustment + * 0b00..+3.46% + * 0b01..0, Design default + * 0b10..-1.47% + * 0b11..-3.33% + */ +#define USBNC_UTMIPHY_CFG1_TXRISETUNE0(x) (((uint32_t)(((uint32_t)(x)) << USBNC_UTMIPHY_CFG1_TXRISETUNE0_SHIFT)) & USBNC_UTMIPHY_CFG1_TXRISETUNE0_MASK) + +#define USBNC_UTMIPHY_CFG1_TXRESTUNE0_MASK (0xC000000U) +#define USBNC_UTMIPHY_CFG1_TXRESTUNE0_SHIFT (26U) +/*! TXRESTUNE0 - USB Source Impedance Adjustment + * 0b00..Source impedance is increased by approximately 3.01 ohm + * 0b01..00, design default + * 0b10..Source impedance is decreased by approximately 1.32 ohm + * 0b11..Source impedance is decreased by approximately 3.71 ohm + */ +#define USBNC_UTMIPHY_CFG1_TXRESTUNE0(x) (((uint32_t)(((uint32_t)(x)) << USBNC_UTMIPHY_CFG1_TXRESTUNE0_SHIFT)) & USBNC_UTMIPHY_CFG1_TXRESTUNE0_MASK) + +#define USBNC_UTMIPHY_CFG1_TXPREEMPAMPTUNE0_MASK (0x30000000U) +#define USBNC_UTMIPHY_CFG1_TXPREEMPAMPTUNE0_SHIFT (28U) +/*! TXPREEMPAMPTUNE0 - HS Transmitter Pre-Emphasis Current Control + * 0b00..HS Transmitter pre-emphasis is disabled. + * 0b01..HS Transmitter pre-emphasis circuit sources 1x pre-emphasis current. + * 0b10..HS Transmitter pre-emphasis circuit sources 2x pre-emphasis current. + * 0b11..HS Transmitter pre-emphasis circuit sources 3x pre-emphasis current. + */ +#define USBNC_UTMIPHY_CFG1_TXPREEMPAMPTUNE0(x) (((uint32_t)(((uint32_t)(x)) << USBNC_UTMIPHY_CFG1_TXPREEMPAMPTUNE0_SHIFT)) & USBNC_UTMIPHY_CFG1_TXPREEMPAMPTUNE0_MASK) + +#define USBNC_UTMIPHY_CFG1_TXPREEMPPULSETUNE0_MASK (0x40000000U) +#define USBNC_UTMIPHY_CFG1_TXPREEMPPULSETUNE0_SHIFT (30U) +/*! TXPREEMPPULSETUNE0 - HS Transmitter Pre-Emphasis Duration Control + * 0b0..Design default. Long pre-emphasis current duration + * 0b1..Short pre-emphasis current duration + */ +#define USBNC_UTMIPHY_CFG1_TXPREEMPPULSETUNE0(x) (((uint32_t)(((uint32_t)(x)) << USBNC_UTMIPHY_CFG1_TXPREEMPPULSETUNE0_SHIFT)) & USBNC_UTMIPHY_CFG1_TXPREEMPPULSETUNE0_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group USBNC_Register_Masks */ + + +/* USBNC - Peripheral instance base addresses */ +/** Peripheral USB__USBNC_OTG1 base address */ +#define USB__USBNC_OTG1_BASE (0x4C100200u) +/** Peripheral USB__USBNC_OTG1 base pointer */ +#define USB__USBNC_OTG1 ((USBNC_Type *)USB__USBNC_OTG1_BASE) +/** Peripheral USB__USBNC_OTG2 base address */ +#define USB__USBNC_OTG2_BASE (0x4C200200u) +/** Peripheral USB__USBNC_OTG2 base pointer */ +#define USB__USBNC_OTG2 ((USBNC_Type *)USB__USBNC_OTG2_BASE) +/** Array initializer of USBNC peripheral base addresses */ +#define USBNC_BASE_ADDRS { USB__USBNC_OTG1_BASE, USB__USBNC_OTG2_BASE } +/** Array initializer of USBNC peripheral base pointers */ +#define USBNC_BASE_PTRS { USB__USBNC_OTG1, USB__USBNC_OTG2 } + +/*! + * @} + */ /* end of group USBNC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- USDHC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USDHC_Peripheral_Access_Layer USDHC Peripheral Access Layer + * @{ + */ + +/** USDHC - Register Layout Typedef */ +typedef struct { + __IO uint32_t DS_ADDR; /**< DMA System Address, offset: 0x0 */ + __IO uint32_t BLK_ATT; /**< Block Attributes, offset: 0x4 */ + __IO uint32_t CMD_ARG; /**< Command Argument, offset: 0x8 */ + __IO uint32_t CMD_XFR_TYP; /**< Command Transfer Type, offset: 0xC */ + __I uint32_t CMD_RSP0; /**< Command Response0, offset: 0x10 */ + __I uint32_t CMD_RSP1; /**< Command Response1, offset: 0x14 */ + __I uint32_t CMD_RSP2; /**< Command Response2, offset: 0x18 */ + __I uint32_t CMD_RSP3; /**< Command Response3, offset: 0x1C */ + __IO uint32_t DATA_BUFF_ACC_PORT; /**< Data Buffer Access Port, offset: 0x20 */ + __I uint32_t PRES_STATE; /**< Present State, offset: 0x24 */ + __IO uint32_t PROT_CTRL; /**< Protocol Control, offset: 0x28 */ + __IO uint32_t SYS_CTRL; /**< System Control, offset: 0x2C */ + __IO uint32_t INT_STATUS; /**< Interrupt Status, offset: 0x30 */ + __IO uint32_t INT_STATUS_EN; /**< Interrupt Status Enable, offset: 0x34 */ + __IO uint32_t INT_SIGNAL_EN; /**< Interrupt Signal Enable, offset: 0x38 */ + __IO uint32_t AUTOCMD12_ERR_STATUS; /**< Auto CMD12 Error Status, offset: 0x3C */ + __IO uint32_t HOST_CTRL_CAP; /**< Host Controller Capabilities, offset: 0x40 */ + __IO uint32_t WTMK_LVL; /**< Watermark Level, offset: 0x44 */ + __IO uint32_t MIX_CTRL; /**< Mixer Control, offset: 0x48 */ + uint8_t RESERVED_0[4]; + __IO uint32_t FORCE_EVENT; /**< Force Event, offset: 0x50 */ + __I uint32_t ADMA_ERR_STATUS; /**< ADMA Error Status, offset: 0x54 */ + __IO uint32_t ADMA_SYS_ADDR; /**< ADMA System Address, offset: 0x58 */ + uint8_t RESERVED_1[4]; + __IO uint32_t DLL_CTRL; /**< DLL (Delay Line) Control, offset: 0x60 */ + __I uint32_t DLL_STATUS; /**< DLL Status, offset: 0x64 */ + __IO uint32_t CLK_TUNE_CTRL_STATUS; /**< CLK Tuning Control and Status, offset: 0x68 */ + uint8_t RESERVED_2[4]; + __IO uint32_t STROBE_DLL_CTRL; /**< Strobe DLL control, offset: 0x70 */ + __I uint32_t STROBE_DLL_STATUS; /**< Strobe DLL status, offset: 0x74 */ + uint8_t RESERVED_3[72]; + __IO uint32_t VEND_SPEC; /**< Vendor Specific Register, offset: 0xC0 */ + __IO uint32_t MMC_BOOT; /**< eMMC Boot, offset: 0xC4 */ + __IO uint32_t VEND_SPEC2; /**< Vendor Specific 2 Register, offset: 0xC8 */ + __IO uint32_t TUNING_CTRL; /**< Tuning Control, offset: 0xCC */ + uint8_t RESERVED_4[48]; + __I uint32_t CQVER; /**< Command Queuing Version, offset: 0x100 */ + __IO uint32_t CQCAP; /**< Command Queuing Capabilities, offset: 0x104 */ + __IO uint32_t CQCFG; /**< Command Queuing Configuration, offset: 0x108 */ + __IO uint32_t CQCTL; /**< Command Queuing Control, offset: 0x10C */ + __IO uint32_t CQIS; /**< Command Queuing Interrupt Status, offset: 0x110 */ + __IO uint32_t CQISTE; /**< Command Queuing Interrupt Status Enable, offset: 0x114 */ + __IO uint32_t CQISGE; /**< Command Queuing Interrupt Signal Enable, offset: 0x118 */ + __IO uint32_t CQIC; /**< Command Queuing Interrupt Coalescing, offset: 0x11C */ + __IO uint32_t CQTDLBA; /**< Command Queuing Task Descriptor List Base Address, offset: 0x120 */ + __IO uint32_t CQTDLBAU; /**< Command Queuing Task Descriptor List Base Address Upper 32 Bits, offset: 0x124 */ + __IO uint32_t CQTDBR; /**< Command Queuing Task Doorbell, offset: 0x128 */ + __IO uint32_t CQTCN; /**< Command Queuing Task Completion Notification, offset: 0x12C */ + __I uint32_t CQDQS; /**< Command Queuing Device Queue Status, offset: 0x130 */ + __I uint32_t CQDPT; /**< Command Queuing Device Pending Tasks, offset: 0x134 */ + __IO uint32_t CQTCLR; /**< Command Queuing Task Clear, offset: 0x138 */ + uint8_t RESERVED_5[4]; + __IO uint32_t CQSSC1; /**< Command Queuing Send Status Configuration 1, offset: 0x140 */ + __IO uint32_t CQSSC2; /**< Command Queuing Send Status Configuration 2, offset: 0x144 */ + __I uint32_t CQCRDCT; /**< Command Queuing Command Response for Direct-Command Task, offset: 0x148 */ + uint8_t RESERVED_6[4]; + __IO uint32_t CQRMEM; /**< Command Queuing Response Mode Error Mask, offset: 0x150 */ + __I uint32_t CQTERRI; /**< Command Queuing Task Error Information, offset: 0x154 */ + __I uint32_t CQCRI; /**< Command Queuing Command Response Index, offset: 0x158 */ + __I uint32_t CQCRA; /**< Command Queuing Command Response Argument, offset: 0x15C */ +} USDHC_Type; + +/* ---------------------------------------------------------------------------- + -- USDHC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USDHC_Register_Masks USDHC Register Masks + * @{ + */ + +/*! @name DS_ADDR - DMA System Address */ +/*! @{ */ + +#define USDHC_DS_ADDR_DS_ADDR_MASK (0xFFFFFFFFU) +#define USDHC_DS_ADDR_DS_ADDR_SHIFT (0U) +/*! DS_ADDR - System address */ +#define USDHC_DS_ADDR_DS_ADDR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DS_ADDR_DS_ADDR_SHIFT)) & USDHC_DS_ADDR_DS_ADDR_MASK) +/*! @} */ + +/*! @name BLK_ATT - Block Attributes */ +/*! @{ */ + +#define USDHC_BLK_ATT_BLKSIZE_MASK (0x1FFFU) +#define USDHC_BLK_ATT_BLKSIZE_SHIFT (0U) +/*! BLKSIZE - Transfer block size + * 0b0000000000000..No data transfer + * 0b0000000000001..1 byte + * 0b0000000000010..2 bytes + * 0b0000000000011..3 bytes + * 0b0000000000100..4 bytes + * 0b0000111111111..511 bytes + * 0b0001000000000..512 bytes + * 0b0100000000000..2048 bytes + * 0b1000000000000..4096 bytes + */ +#define USDHC_BLK_ATT_BLKSIZE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_BLK_ATT_BLKSIZE_SHIFT)) & USDHC_BLK_ATT_BLKSIZE_MASK) + +#define USDHC_BLK_ATT_BLKCNT_MASK (0xFFFF0000U) +#define USDHC_BLK_ATT_BLKCNT_SHIFT (16U) +/*! BLKCNT - Blocks count for current transfer + * 0b0000000000000000..Stop count + * 0b0000000000000001..1 block + * 0b0000000000000010..2 blocks + * 0b1111111111111111..65535 blocks + */ +#define USDHC_BLK_ATT_BLKCNT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_BLK_ATT_BLKCNT_SHIFT)) & USDHC_BLK_ATT_BLKCNT_MASK) +/*! @} */ + +/*! @name CMD_ARG - Command Argument */ +/*! @{ */ + +#define USDHC_CMD_ARG_CMDARG_MASK (0xFFFFFFFFU) +#define USDHC_CMD_ARG_CMDARG_SHIFT (0U) +/*! CMDARG - Command argument */ +#define USDHC_CMD_ARG_CMDARG(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_ARG_CMDARG_SHIFT)) & USDHC_CMD_ARG_CMDARG_MASK) +/*! @} */ + +/*! @name CMD_XFR_TYP - Command Transfer Type */ +/*! @{ */ + +#define USDHC_CMD_XFR_TYP_DMAEN_MASK (0x1U) +#define USDHC_CMD_XFR_TYP_DMAEN_SHIFT (0U) +/*! DMAEN - DMAEN + * 0b0..Disable + * 0b1..Enable + */ +#define USDHC_CMD_XFR_TYP_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_DMAEN_SHIFT)) & USDHC_CMD_XFR_TYP_DMAEN_MASK) + +#define USDHC_CMD_XFR_TYP_BCEN_MASK (0x2U) +#define USDHC_CMD_XFR_TYP_BCEN_SHIFT (1U) +/*! BCEN - BCEN + * 0b0..Disable + * 0b1..Enable + */ +#define USDHC_CMD_XFR_TYP_BCEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_BCEN_SHIFT)) & USDHC_CMD_XFR_TYP_BCEN_MASK) + +#define USDHC_CMD_XFR_TYP_AC12EN_MASK (0x4U) +#define USDHC_CMD_XFR_TYP_AC12EN_SHIFT (2U) +/*! AC12EN - AC12EN + * 0b0..Disable + * 0b1..Enable + */ +#define USDHC_CMD_XFR_TYP_AC12EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_AC12EN_SHIFT)) & USDHC_CMD_XFR_TYP_AC12EN_MASK) + +#define USDHC_CMD_XFR_TYP_DDR_EN_MASK (0x8U) +#define USDHC_CMD_XFR_TYP_DDR_EN_SHIFT (3U) +/*! DDR_EN - DDR_EN + * 0b0..Disable + * 0b1..Enable + */ +#define USDHC_CMD_XFR_TYP_DDR_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_DDR_EN_SHIFT)) & USDHC_CMD_XFR_TYP_DDR_EN_MASK) + +#define USDHC_CMD_XFR_TYP_DTDSEL_MASK (0x10U) +#define USDHC_CMD_XFR_TYP_DTDSEL_SHIFT (4U) +/*! DTDSEL - DTDSEL + * 0b0..Disable + * 0b1..Enable + */ +#define USDHC_CMD_XFR_TYP_DTDSEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_DTDSEL_SHIFT)) & USDHC_CMD_XFR_TYP_DTDSEL_MASK) + +#define USDHC_CMD_XFR_TYP_MSBSEL_MASK (0x20U) +#define USDHC_CMD_XFR_TYP_MSBSEL_SHIFT (5U) +/*! MSBSEL - MSBSEL + * 0b0..Disable + * 0b1..Enable + */ +#define USDHC_CMD_XFR_TYP_MSBSEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_MSBSEL_SHIFT)) & USDHC_CMD_XFR_TYP_MSBSEL_MASK) + +#define USDHC_CMD_XFR_TYP_NIBBLE_POS_MASK (0x40U) +#define USDHC_CMD_XFR_TYP_NIBBLE_POS_SHIFT (6U) +/*! NIBBLE_POS - NIBBLE_POS + * 0b0..Disable + * 0b1..Enable + */ +#define USDHC_CMD_XFR_TYP_NIBBLE_POS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_NIBBLE_POS_SHIFT)) & USDHC_CMD_XFR_TYP_NIBBLE_POS_MASK) + +#define USDHC_CMD_XFR_TYP_AC23EN_MASK (0x80U) +#define USDHC_CMD_XFR_TYP_AC23EN_SHIFT (7U) +/*! AC23EN - AC23EN + * 0b0..Disable + * 0b1..Enable + */ +#define USDHC_CMD_XFR_TYP_AC23EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_AC23EN_SHIFT)) & USDHC_CMD_XFR_TYP_AC23EN_MASK) + +#define USDHC_CMD_XFR_TYP_RSPTYP_MASK (0x30000U) +#define USDHC_CMD_XFR_TYP_RSPTYP_SHIFT (16U) +/*! RSPTYP - Response type select + * 0b00..No response + * 0b01..Response length 136 + * 0b10..Response length 48 + * 0b11..Response length 48, check busy after response + */ +#define USDHC_CMD_XFR_TYP_RSPTYP(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_RSPTYP_SHIFT)) & USDHC_CMD_XFR_TYP_RSPTYP_MASK) + +#define USDHC_CMD_XFR_TYP_CCCEN_MASK (0x80000U) +#define USDHC_CMD_XFR_TYP_CCCEN_SHIFT (19U) +/*! CCCEN - Command CRC check enable + * 0b0..Disables command CRC check + * 0b1..Enables command CRC check + */ +#define USDHC_CMD_XFR_TYP_CCCEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_CCCEN_SHIFT)) & USDHC_CMD_XFR_TYP_CCCEN_MASK) + +#define USDHC_CMD_XFR_TYP_CICEN_MASK (0x100000U) +#define USDHC_CMD_XFR_TYP_CICEN_SHIFT (20U) +/*! CICEN - Command index check enable + * 0b0..Disable command index check + * 0b1..Enables command index check + */ +#define USDHC_CMD_XFR_TYP_CICEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_CICEN_SHIFT)) & USDHC_CMD_XFR_TYP_CICEN_MASK) + +#define USDHC_CMD_XFR_TYP_DPSEL_MASK (0x200000U) +#define USDHC_CMD_XFR_TYP_DPSEL_SHIFT (21U) +/*! DPSEL - Data present select + * 0b0..No data present + * 0b1..Data present + */ +#define USDHC_CMD_XFR_TYP_DPSEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_DPSEL_SHIFT)) & USDHC_CMD_XFR_TYP_DPSEL_MASK) + +#define USDHC_CMD_XFR_TYP_CMDTYP_MASK (0xC00000U) +#define USDHC_CMD_XFR_TYP_CMDTYP_SHIFT (22U) +/*! CMDTYP - Command type + * 0b00..Normal other commands + * 0b01..Suspend CMD52 for writing bus suspend in CCCR + * 0b10..Resume CMD52 for writing function select in CCCR + * 0b11..Abort CMD12, CMD52 for writing I/O Abort in CCCR + */ +#define USDHC_CMD_XFR_TYP_CMDTYP(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_CMDTYP_SHIFT)) & USDHC_CMD_XFR_TYP_CMDTYP_MASK) + +#define USDHC_CMD_XFR_TYP_CMDINX_MASK (0x3F000000U) +#define USDHC_CMD_XFR_TYP_CMDINX_SHIFT (24U) +/*! CMDINX - Command index */ +#define USDHC_CMD_XFR_TYP_CMDINX(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_CMDINX_SHIFT)) & USDHC_CMD_XFR_TYP_CMDINX_MASK) +/*! @} */ + +/*! @name CMD_RSP0 - Command Response0 */ +/*! @{ */ + +#define USDHC_CMD_RSP0_CMDRSP0_MASK (0xFFFFFFFFU) +#define USDHC_CMD_RSP0_CMDRSP0_SHIFT (0U) +/*! CMDRSP0 - Command response 0 */ +#define USDHC_CMD_RSP0_CMDRSP0(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP0_CMDRSP0_SHIFT)) & USDHC_CMD_RSP0_CMDRSP0_MASK) +/*! @} */ + +/*! @name CMD_RSP1 - Command Response1 */ +/*! @{ */ + +#define USDHC_CMD_RSP1_CMDRSP1_MASK (0xFFFFFFFFU) +#define USDHC_CMD_RSP1_CMDRSP1_SHIFT (0U) +/*! CMDRSP1 - Command response 1 */ +#define USDHC_CMD_RSP1_CMDRSP1(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP1_CMDRSP1_SHIFT)) & USDHC_CMD_RSP1_CMDRSP1_MASK) +/*! @} */ + +/*! @name CMD_RSP2 - Command Response2 */ +/*! @{ */ + +#define USDHC_CMD_RSP2_CMDRSP2_MASK (0xFFFFFFFFU) +#define USDHC_CMD_RSP2_CMDRSP2_SHIFT (0U) +/*! CMDRSP2 - Command response 2 */ +#define USDHC_CMD_RSP2_CMDRSP2(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP2_CMDRSP2_SHIFT)) & USDHC_CMD_RSP2_CMDRSP2_MASK) +/*! @} */ + +/*! @name CMD_RSP3 - Command Response3 */ +/*! @{ */ + +#define USDHC_CMD_RSP3_CMDRSP3_MASK (0xFFFFFFFFU) +#define USDHC_CMD_RSP3_CMDRSP3_SHIFT (0U) +/*! CMDRSP3 - Command response 3 */ +#define USDHC_CMD_RSP3_CMDRSP3(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP3_CMDRSP3_SHIFT)) & USDHC_CMD_RSP3_CMDRSP3_MASK) +/*! @} */ + +/*! @name DATA_BUFF_ACC_PORT - Data Buffer Access Port */ +/*! @{ */ + +#define USDHC_DATA_BUFF_ACC_PORT_DATCONT_MASK (0xFFFFFFFFU) +#define USDHC_DATA_BUFF_ACC_PORT_DATCONT_SHIFT (0U) +/*! DATCONT - Data content */ +#define USDHC_DATA_BUFF_ACC_PORT_DATCONT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DATA_BUFF_ACC_PORT_DATCONT_SHIFT)) & USDHC_DATA_BUFF_ACC_PORT_DATCONT_MASK) +/*! @} */ + +/*! @name PRES_STATE - Present State */ +/*! @{ */ + +#define USDHC_PRES_STATE_CIHB_MASK (0x1U) +#define USDHC_PRES_STATE_CIHB_SHIFT (0U) +/*! CIHB - Command inhibit (CMD) + * 0b0..Can issue command using only CMD line + * 0b1..Cannot issue command + */ +#define USDHC_PRES_STATE_CIHB(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CIHB_SHIFT)) & USDHC_PRES_STATE_CIHB_MASK) + +#define USDHC_PRES_STATE_CDIHB_MASK (0x2U) +#define USDHC_PRES_STATE_CDIHB_SHIFT (1U) +/*! CDIHB - Command Inhibit Data (DATA) + * 0b0..Can issue command that uses the DATA line + * 0b1..Cannot issue command that uses the DATA line + */ +#define USDHC_PRES_STATE_CDIHB(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CDIHB_SHIFT)) & USDHC_PRES_STATE_CDIHB_MASK) + +#define USDHC_PRES_STATE_DLA_MASK (0x4U) +#define USDHC_PRES_STATE_DLA_SHIFT (2U) +/*! DLA - Data line active + * 0b0..DATA line inactive + * 0b1..DATA line active + */ +#define USDHC_PRES_STATE_DLA(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_DLA_SHIFT)) & USDHC_PRES_STATE_DLA_MASK) + +#define USDHC_PRES_STATE_SDSTB_MASK (0x8U) +#define USDHC_PRES_STATE_SDSTB_SHIFT (3U) +/*! SDSTB - SD clock stable + * 0b0..Clock is changing frequency and not stable. + * 0b1..Clock is stable. + */ +#define USDHC_PRES_STATE_SDSTB(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_SDSTB_SHIFT)) & USDHC_PRES_STATE_SDSTB_MASK) + +#define USDHC_PRES_STATE_WTA_MASK (0x100U) +#define USDHC_PRES_STATE_WTA_SHIFT (8U) +/*! WTA - Write transfer active + * 0b0..No valid data + * 0b1..Transferring data + */ +#define USDHC_PRES_STATE_WTA(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_WTA_SHIFT)) & USDHC_PRES_STATE_WTA_MASK) + +#define USDHC_PRES_STATE_RTA_MASK (0x200U) +#define USDHC_PRES_STATE_RTA_SHIFT (9U) +/*! RTA - Read transfer active + * 0b0..No valid data + * 0b1..Transferring data + */ +#define USDHC_PRES_STATE_RTA(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_RTA_SHIFT)) & USDHC_PRES_STATE_RTA_MASK) + +#define USDHC_PRES_STATE_BWEN_MASK (0x400U) +#define USDHC_PRES_STATE_BWEN_SHIFT (10U) +/*! BWEN - Buffer write enable + * 0b0..Write disable + * 0b1..Write enable + */ +#define USDHC_PRES_STATE_BWEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_BWEN_SHIFT)) & USDHC_PRES_STATE_BWEN_MASK) + +#define USDHC_PRES_STATE_BREN_MASK (0x800U) +#define USDHC_PRES_STATE_BREN_SHIFT (11U) +/*! BREN - Buffer read enable + * 0b0..Read disable + * 0b1..Read enable + */ +#define USDHC_PRES_STATE_BREN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_BREN_SHIFT)) & USDHC_PRES_STATE_BREN_MASK) + +#define USDHC_PRES_STATE_RTR_MASK (0x1000U) +#define USDHC_PRES_STATE_RTR_SHIFT (12U) +/*! RTR - Re-Tuning Request (only for SD3.0 SDR104 mode, and eMMC HS200 mode) + * 0b0..Fixed or well tuned sampling clock + * 0b1..Sampling clock needs re-tuning + */ +#define USDHC_PRES_STATE_RTR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_RTR_SHIFT)) & USDHC_PRES_STATE_RTR_MASK) + +#define USDHC_PRES_STATE_TSCD_MASK (0x8000U) +#define USDHC_PRES_STATE_TSCD_SHIFT (15U) +/*! TSCD - Tap select change done + * 0b0..Delay cell select change is not finished. + * 0b1..Delay cell select change is finished. + */ +#define USDHC_PRES_STATE_TSCD(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_TSCD_SHIFT)) & USDHC_PRES_STATE_TSCD_MASK) + +#define USDHC_PRES_STATE_CINST_MASK (0x10000U) +#define USDHC_PRES_STATE_CINST_SHIFT (16U) +/*! CINST - Card inserted + * 0b0..Power on reset or no card + * 0b1..Card inserted + */ +#define USDHC_PRES_STATE_CINST(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CINST_SHIFT)) & USDHC_PRES_STATE_CINST_MASK) + +#define USDHC_PRES_STATE_CDPL_MASK (0x40000U) +#define USDHC_PRES_STATE_CDPL_SHIFT (18U) +/*! CDPL - Card detect pin level + * 0b0..No card present (CD_B = 1) + * 0b1..Card present (CD_B = 0) + */ +#define USDHC_PRES_STATE_CDPL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CDPL_SHIFT)) & USDHC_PRES_STATE_CDPL_MASK) + +#define USDHC_PRES_STATE_WPSPL_MASK (0x80000U) +#define USDHC_PRES_STATE_WPSPL_SHIFT (19U) +/*! WPSPL - Write protect switch pin level + * 0b0..Write protected (WP = 1) + * 0b1..Write enabled (WP = 0) + */ +#define USDHC_PRES_STATE_WPSPL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_WPSPL_SHIFT)) & USDHC_PRES_STATE_WPSPL_MASK) + +#define USDHC_PRES_STATE_CLSL_MASK (0x800000U) +#define USDHC_PRES_STATE_CLSL_SHIFT (23U) +/*! CLSL - CMD line signal level */ +#define USDHC_PRES_STATE_CLSL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CLSL_SHIFT)) & USDHC_PRES_STATE_CLSL_MASK) + +#define USDHC_PRES_STATE_DLSL_MASK (0xFF000000U) +#define USDHC_PRES_STATE_DLSL_SHIFT (24U) +/*! DLSL - DATA[7:0] line signal level + * 0b00000001..Data 0 line signal level + * 0b00000010..Data 1 line signal level + * 0b00000100..Data 2 line signal level + * 0b00001000..Data 3 line signal level + * 0b00010000..Data 4 line signal level + * 0b00100000..Data 5 line signal level + * 0b01000000..Data 6 line signal level + * 0b10000000..Data 7 line signal level + */ +#define USDHC_PRES_STATE_DLSL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_DLSL_SHIFT)) & USDHC_PRES_STATE_DLSL_MASK) +/*! @} */ + +/*! @name PROT_CTRL - Protocol Control */ +/*! @{ */ + +#define USDHC_PROT_CTRL_DTW_MASK (0x6U) +#define USDHC_PROT_CTRL_DTW_SHIFT (1U) +/*! DTW - Data transfer width + * 0b00..1-bit mode + * 0b01..4-bit mode + * 0b10..8-bit mode + * 0b11..Reserved + */ +#define USDHC_PROT_CTRL_DTW(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_DTW_SHIFT)) & USDHC_PROT_CTRL_DTW_MASK) + +#define USDHC_PROT_CTRL_D3CD_MASK (0x8U) +#define USDHC_PROT_CTRL_D3CD_SHIFT (3U) +/*! D3CD - DATA3 as card detection pin + * 0b0..DATA3 does not monitor card insertion + * 0b1..DATA3 as card detection pin + */ +#define USDHC_PROT_CTRL_D3CD(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_D3CD_SHIFT)) & USDHC_PROT_CTRL_D3CD_MASK) + +#define USDHC_PROT_CTRL_EMODE_MASK (0x30U) +#define USDHC_PROT_CTRL_EMODE_SHIFT (4U) +/*! EMODE - Endian mode + * 0b00..Big endian mode + * 0b01..Half word big endian mode + * 0b10..Little endian mode + * 0b11..Reserved + */ +#define USDHC_PROT_CTRL_EMODE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_EMODE_SHIFT)) & USDHC_PROT_CTRL_EMODE_MASK) + +#define USDHC_PROT_CTRL_DMASEL_MASK (0x300U) +#define USDHC_PROT_CTRL_DMASEL_SHIFT (8U) +/*! DMASEL - DMA select + * 0b00..No DMA or simple DMA is selected. + * 0b01..ADMA1 is selected. + * 0b10..ADMA2 is selected. + * 0b11..Reserved + */ +#define USDHC_PROT_CTRL_DMASEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_DMASEL_SHIFT)) & USDHC_PROT_CTRL_DMASEL_MASK) + +#define USDHC_PROT_CTRL_SABGREQ_MASK (0x10000U) +#define USDHC_PROT_CTRL_SABGREQ_SHIFT (16U) +/*! SABGREQ - Stop at block gap request + * 0b0..Transfer + * 0b1..Stop + */ +#define USDHC_PROT_CTRL_SABGREQ(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_SABGREQ_SHIFT)) & USDHC_PROT_CTRL_SABGREQ_MASK) + +#define USDHC_PROT_CTRL_CREQ_MASK (0x20000U) +#define USDHC_PROT_CTRL_CREQ_SHIFT (17U) +/*! CREQ - Continue request + * 0b0..No effect + * 0b1..Restart + */ +#define USDHC_PROT_CTRL_CREQ(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_CREQ_SHIFT)) & USDHC_PROT_CTRL_CREQ_MASK) + +#define USDHC_PROT_CTRL_RWCTL_MASK (0x40000U) +#define USDHC_PROT_CTRL_RWCTL_SHIFT (18U) +/*! RWCTL - Read wait control + * 0b0..Disables read wait control and stop SD clock at block gap when SABGREQ field is set + * 0b1..Enables read wait control and assert read wait without stopping SD clock at block gap when SABGREQ field is set + */ +#define USDHC_PROT_CTRL_RWCTL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_RWCTL_SHIFT)) & USDHC_PROT_CTRL_RWCTL_MASK) + +#define USDHC_PROT_CTRL_IABG_MASK (0x80000U) +#define USDHC_PROT_CTRL_IABG_SHIFT (19U) +/*! IABG - Interrupt at block gap + * 0b0..Disables interrupt at block gap + * 0b1..Enables interrupt at block gap + */ +#define USDHC_PROT_CTRL_IABG(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_IABG_SHIFT)) & USDHC_PROT_CTRL_IABG_MASK) + +#define USDHC_PROT_CTRL_RD_DONE_NO_8CLK_MASK (0x100000U) +#define USDHC_PROT_CTRL_RD_DONE_NO_8CLK_SHIFT (20U) +/*! RD_DONE_NO_8CLK - Read performed number 8 clock */ +#define USDHC_PROT_CTRL_RD_DONE_NO_8CLK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_RD_DONE_NO_8CLK_SHIFT)) & USDHC_PROT_CTRL_RD_DONE_NO_8CLK_MASK) + +#define USDHC_PROT_CTRL_WECINT_MASK (0x1000000U) +#define USDHC_PROT_CTRL_WECINT_SHIFT (24U) +/*! WECINT - Wakeup event enable on card interrupt + * 0b0..Disables wakeup event enable on card interrupt + * 0b1..Enables wakeup event enable on card interrupt + */ +#define USDHC_PROT_CTRL_WECINT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_WECINT_SHIFT)) & USDHC_PROT_CTRL_WECINT_MASK) + +#define USDHC_PROT_CTRL_WECINS_MASK (0x2000000U) +#define USDHC_PROT_CTRL_WECINS_SHIFT (25U) +/*! WECINS - Wakeup event enable on SD card insertion + * 0b0..Disable wakeup event enable on SD card insertion + * 0b1..Enable wakeup event enable on SD card insertion + */ +#define USDHC_PROT_CTRL_WECINS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_WECINS_SHIFT)) & USDHC_PROT_CTRL_WECINS_MASK) + +#define USDHC_PROT_CTRL_WECRM_MASK (0x4000000U) +#define USDHC_PROT_CTRL_WECRM_SHIFT (26U) +/*! WECRM - Wakeup event enable on SD card removal + * 0b0..Disables wakeup event enable on SD card removal + * 0b1..Enables wakeup event enable on SD card removal + */ +#define USDHC_PROT_CTRL_WECRM(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_WECRM_SHIFT)) & USDHC_PROT_CTRL_WECRM_MASK) + +#define USDHC_PROT_CTRL_NON_EXACT_BLK_RD_MASK (0x40000000U) +#define USDHC_PROT_CTRL_NON_EXACT_BLK_RD_SHIFT (30U) +/*! NON_EXACT_BLK_RD - Non-exact block read + * 0b0..The block read is exact block read. Host driver does not need to issue abort command to terminate this multi-block read. + * 0b1..The block read is non-exact block read. Host driver needs to issue abort command to terminate this multi-block read. + */ +#define USDHC_PROT_CTRL_NON_EXACT_BLK_RD(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_NON_EXACT_BLK_RD_SHIFT)) & USDHC_PROT_CTRL_NON_EXACT_BLK_RD_MASK) +/*! @} */ + +/*! @name SYS_CTRL - System Control */ +/*! @{ */ + +#define USDHC_SYS_CTRL_DVS_MASK (0xF0U) +#define USDHC_SYS_CTRL_DVS_SHIFT (4U) +/*! DVS - Divisor + * 0b0000..Divide-by-1 + * 0b0001..Divide-by-2 + * 0b1110..Divide-by-15 + * 0b1111..Divide-by-16 + */ +#define USDHC_SYS_CTRL_DVS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_DVS_SHIFT)) & USDHC_SYS_CTRL_DVS_MASK) + +#define USDHC_SYS_CTRL_SDCLKFS_MASK (0xFF00U) +#define USDHC_SYS_CTRL_SDCLKFS_SHIFT (8U) +/*! SDCLKFS - SDCLK frequency select */ +#define USDHC_SYS_CTRL_SDCLKFS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_SDCLKFS_SHIFT)) & USDHC_SYS_CTRL_SDCLKFS_MASK) + +#define USDHC_SYS_CTRL_DTOCV_MASK (0xF0000U) +#define USDHC_SYS_CTRL_DTOCV_SHIFT (16U) +/*! DTOCV - Data timeout counter value + * 0b0000..SDCLK x 2 32 + * 0b0001..SDCLK x 2 33 + * 0b0010..SDCLK x 2 18 + * 0b0011..SDCLK x 2 19 + * 0b1101..SDCLK x 2 29, recommend to use for supported speed modes except HS200, HS400, SDR104 mode + * 0b1110..SDCLK x 2 30, recommend to use for HS200 and SDR104 mode + * 0b1111..SDCLK x 2 31, recommend to use for HS400 mode + */ +#define USDHC_SYS_CTRL_DTOCV(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_DTOCV_SHIFT)) & USDHC_SYS_CTRL_DTOCV_MASK) + +#define USDHC_SYS_CTRL_RST_FIFO_MASK (0x400000U) +#define USDHC_SYS_CTRL_RST_FIFO_SHIFT (22U) +/*! RST_FIFO - Reset the async FIFO */ +#define USDHC_SYS_CTRL_RST_FIFO(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_RST_FIFO_SHIFT)) & USDHC_SYS_CTRL_RST_FIFO_MASK) + +#define USDHC_SYS_CTRL_IPP_RST_N_MASK (0x800000U) +#define USDHC_SYS_CTRL_IPP_RST_N_SHIFT (23U) +/*! IPP_RST_N - Hardware reset */ +#define USDHC_SYS_CTRL_IPP_RST_N(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_IPP_RST_N_SHIFT)) & USDHC_SYS_CTRL_IPP_RST_N_MASK) + +#define USDHC_SYS_CTRL_RSTA_MASK (0x1000000U) +#define USDHC_SYS_CTRL_RSTA_SHIFT (24U) +/*! RSTA - Software reset for all + * 0b0..No reset + * 0b1..Reset + */ +#define USDHC_SYS_CTRL_RSTA(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_RSTA_SHIFT)) & USDHC_SYS_CTRL_RSTA_MASK) + +#define USDHC_SYS_CTRL_RSTC_MASK (0x2000000U) +#define USDHC_SYS_CTRL_RSTC_SHIFT (25U) +/*! RSTC - Software reset for CMD line + * 0b0..No reset + * 0b1..Reset + */ +#define USDHC_SYS_CTRL_RSTC(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_RSTC_SHIFT)) & USDHC_SYS_CTRL_RSTC_MASK) + +#define USDHC_SYS_CTRL_RSTD_MASK (0x4000000U) +#define USDHC_SYS_CTRL_RSTD_SHIFT (26U) +/*! RSTD - Software reset for data line + * 0b0..No reset + * 0b1..Reset + */ +#define USDHC_SYS_CTRL_RSTD(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_RSTD_SHIFT)) & USDHC_SYS_CTRL_RSTD_MASK) + +#define USDHC_SYS_CTRL_INITA_MASK (0x8000000U) +#define USDHC_SYS_CTRL_INITA_SHIFT (27U) +/*! INITA - Initialization active */ +#define USDHC_SYS_CTRL_INITA(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_INITA_SHIFT)) & USDHC_SYS_CTRL_INITA_MASK) + +#define USDHC_SYS_CTRL_RSTT_MASK (0x10000000U) +#define USDHC_SYS_CTRL_RSTT_SHIFT (28U) +/*! RSTT - Reset tuning */ +#define USDHC_SYS_CTRL_RSTT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_RSTT_SHIFT)) & USDHC_SYS_CTRL_RSTT_MASK) +/*! @} */ + +/*! @name INT_STATUS - Interrupt Status */ +/*! @{ */ + +#define USDHC_INT_STATUS_CC_MASK (0x1U) +#define USDHC_INT_STATUS_CC_SHIFT (0U) +/*! CC - Command complete + * 0b0..Command not complete + * 0b1..Command complete + */ +#define USDHC_INT_STATUS_CC(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CC_SHIFT)) & USDHC_INT_STATUS_CC_MASK) + +#define USDHC_INT_STATUS_TC_MASK (0x2U) +#define USDHC_INT_STATUS_TC_SHIFT (1U) +/*! TC - Transfer complete + * 0b0..Transfer does not complete + * 0b1..Transfer complete + */ +#define USDHC_INT_STATUS_TC(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_TC_SHIFT)) & USDHC_INT_STATUS_TC_MASK) + +#define USDHC_INT_STATUS_BGE_MASK (0x4U) +#define USDHC_INT_STATUS_BGE_SHIFT (2U) +/*! BGE - Block gap event + * 0b0..No block gap event + * 0b1..Transaction stopped at block gap + */ +#define USDHC_INT_STATUS_BGE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_BGE_SHIFT)) & USDHC_INT_STATUS_BGE_MASK) + +#define USDHC_INT_STATUS_DINT_MASK (0x8U) +#define USDHC_INT_STATUS_DINT_SHIFT (3U) +/*! DINT - DMA interrupt + * 0b0..No DMA interrupt + * 0b1..DMA interrupt is generated. + */ +#define USDHC_INT_STATUS_DINT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DINT_SHIFT)) & USDHC_INT_STATUS_DINT_MASK) + +#define USDHC_INT_STATUS_BWR_MASK (0x10U) +#define USDHC_INT_STATUS_BWR_SHIFT (4U) +/*! BWR - Buffer write ready + * 0b0..Not ready to write buffer + * 0b1..Ready to write buffer + */ +#define USDHC_INT_STATUS_BWR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_BWR_SHIFT)) & USDHC_INT_STATUS_BWR_MASK) + +#define USDHC_INT_STATUS_BRR_MASK (0x20U) +#define USDHC_INT_STATUS_BRR_SHIFT (5U) +/*! BRR - Buffer read ready + * 0b0..Not ready to read buffer + * 0b1..Ready to read buffer + */ +#define USDHC_INT_STATUS_BRR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_BRR_SHIFT)) & USDHC_INT_STATUS_BRR_MASK) + +#define USDHC_INT_STATUS_CINS_MASK (0x40U) +#define USDHC_INT_STATUS_CINS_SHIFT (6U) +/*! CINS - Card insertion + * 0b0..Card state unstable or removed + * 0b1..Card inserted + */ +#define USDHC_INT_STATUS_CINS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CINS_SHIFT)) & USDHC_INT_STATUS_CINS_MASK) + +#define USDHC_INT_STATUS_CRM_MASK (0x80U) +#define USDHC_INT_STATUS_CRM_SHIFT (7U) +/*! CRM - Card removal + * 0b0..Card state unstable or inserted + * 0b1..Card removed + */ +#define USDHC_INT_STATUS_CRM(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CRM_SHIFT)) & USDHC_INT_STATUS_CRM_MASK) + +#define USDHC_INT_STATUS_CINT_MASK (0x100U) +#define USDHC_INT_STATUS_CINT_SHIFT (8U) +/*! CINT - Card interrupt + * 0b0..No card interrupt + * 0b1..Generate card interrupt + */ +#define USDHC_INT_STATUS_CINT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CINT_SHIFT)) & USDHC_INT_STATUS_CINT_MASK) + +#define USDHC_INT_STATUS_RTE_MASK (0x1000U) +#define USDHC_INT_STATUS_RTE_SHIFT (12U) +/*! RTE - Re-tuning event: (only for SD3.0 SDR104 mode and eMMC HS200 mode) + * 0b0..Re-tuning is not required. + * 0b1..Re-tuning should be performed. + */ +#define USDHC_INT_STATUS_RTE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_RTE_SHIFT)) & USDHC_INT_STATUS_RTE_MASK) + +#define USDHC_INT_STATUS_TP_MASK (0x2000U) +#define USDHC_INT_STATUS_TP_SHIFT (13U) +/*! TP - Tuning pass:(only for SD3.0 SDR104 mode and eMMC HS200 mode) */ +#define USDHC_INT_STATUS_TP(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_TP_SHIFT)) & USDHC_INT_STATUS_TP_MASK) + +#define USDHC_INT_STATUS_CQI_MASK (0x4000U) +#define USDHC_INT_STATUS_CQI_SHIFT (14U) +/*! CQI - Command queuing interrupt */ +#define USDHC_INT_STATUS_CQI(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CQI_SHIFT)) & USDHC_INT_STATUS_CQI_MASK) + +#define USDHC_INT_STATUS_ERR_INT_STATUS_MASK (0x8000U) +#define USDHC_INT_STATUS_ERR_INT_STATUS_SHIFT (15U) +/*! ERR_INT_STATUS - Error Interrupt Status */ +#define USDHC_INT_STATUS_ERR_INT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_ERR_INT_STATUS_SHIFT)) & USDHC_INT_STATUS_ERR_INT_STATUS_MASK) + +#define USDHC_INT_STATUS_CTOE_MASK (0x10000U) +#define USDHC_INT_STATUS_CTOE_SHIFT (16U) +/*! CTOE - Command timeout error + * 0b0..No error + * 0b1..Time out + */ +#define USDHC_INT_STATUS_CTOE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CTOE_SHIFT)) & USDHC_INT_STATUS_CTOE_MASK) + +#define USDHC_INT_STATUS_CCE_MASK (0x20000U) +#define USDHC_INT_STATUS_CCE_SHIFT (17U) +/*! CCE - Command CRC error + * 0b0..No error + * 0b1..CRC error generated + */ +#define USDHC_INT_STATUS_CCE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CCE_SHIFT)) & USDHC_INT_STATUS_CCE_MASK) + +#define USDHC_INT_STATUS_CEBE_MASK (0x40000U) +#define USDHC_INT_STATUS_CEBE_SHIFT (18U) +/*! CEBE - Command end bit error + * 0b0..No error + * 0b1..End bit error generated + */ +#define USDHC_INT_STATUS_CEBE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CEBE_SHIFT)) & USDHC_INT_STATUS_CEBE_MASK) + +#define USDHC_INT_STATUS_CIE_MASK (0x80000U) +#define USDHC_INT_STATUS_CIE_SHIFT (19U) +/*! CIE - Command index error + * 0b0..No error + * 0b1..Error + */ +#define USDHC_INT_STATUS_CIE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CIE_SHIFT)) & USDHC_INT_STATUS_CIE_MASK) + +#define USDHC_INT_STATUS_DTOE_MASK (0x100000U) +#define USDHC_INT_STATUS_DTOE_SHIFT (20U) +/*! DTOE - Data timeout error + * 0b0..No error + * 0b1..Time out + */ +#define USDHC_INT_STATUS_DTOE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DTOE_SHIFT)) & USDHC_INT_STATUS_DTOE_MASK) + +#define USDHC_INT_STATUS_DCE_MASK (0x200000U) +#define USDHC_INT_STATUS_DCE_SHIFT (21U) +/*! DCE - Data CRC error + * 0b0..No error + * 0b1..Error + */ +#define USDHC_INT_STATUS_DCE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DCE_SHIFT)) & USDHC_INT_STATUS_DCE_MASK) + +#define USDHC_INT_STATUS_DEBE_MASK (0x400000U) +#define USDHC_INT_STATUS_DEBE_SHIFT (22U) +/*! DEBE - Data end bit error + * 0b0..No error + * 0b1..Error + */ +#define USDHC_INT_STATUS_DEBE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DEBE_SHIFT)) & USDHC_INT_STATUS_DEBE_MASK) + +#define USDHC_INT_STATUS_AC12E_MASK (0x1000000U) +#define USDHC_INT_STATUS_AC12E_SHIFT (24U) +/*! AC12E - Auto CMD12 error + * 0b0..No error + * 0b1..Error + */ +#define USDHC_INT_STATUS_AC12E(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_AC12E_SHIFT)) & USDHC_INT_STATUS_AC12E_MASK) + +#define USDHC_INT_STATUS_TNE_MASK (0x4000000U) +#define USDHC_INT_STATUS_TNE_SHIFT (26U) +/*! TNE - Tuning error: (only for SD3.0 SDR104 mode and eMMC HS200 mode) */ +#define USDHC_INT_STATUS_TNE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_TNE_SHIFT)) & USDHC_INT_STATUS_TNE_MASK) + +#define USDHC_INT_STATUS_DMAE_MASK (0x10000000U) +#define USDHC_INT_STATUS_DMAE_SHIFT (28U) +/*! DMAE - DMA error + * 0b0..No error + * 0b1..Error + */ +#define USDHC_INT_STATUS_DMAE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DMAE_SHIFT)) & USDHC_INT_STATUS_DMAE_MASK) +/*! @} */ + +/*! @name INT_STATUS_EN - Interrupt Status Enable */ +/*! @{ */ + +#define USDHC_INT_STATUS_EN_CCSEN_MASK (0x1U) +#define USDHC_INT_STATUS_EN_CCSEN_SHIFT (0U) +/*! CCSEN - Command complete status enable + * 0b0..Masked + * 0b1..Enabled + */ +#define USDHC_INT_STATUS_EN_CCSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CCSEN_SHIFT)) & USDHC_INT_STATUS_EN_CCSEN_MASK) + +#define USDHC_INT_STATUS_EN_TCSEN_MASK (0x2U) +#define USDHC_INT_STATUS_EN_TCSEN_SHIFT (1U) +/*! TCSEN - Transfer complete status enable + * 0b0..Masked + * 0b1..Enabled + */ +#define USDHC_INT_STATUS_EN_TCSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_TCSEN_SHIFT)) & USDHC_INT_STATUS_EN_TCSEN_MASK) + +#define USDHC_INT_STATUS_EN_BGESEN_MASK (0x4U) +#define USDHC_INT_STATUS_EN_BGESEN_SHIFT (2U) +/*! BGESEN - Block gap event status enable + * 0b0..Masked + * 0b1..Enabled + */ +#define USDHC_INT_STATUS_EN_BGESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_BGESEN_SHIFT)) & USDHC_INT_STATUS_EN_BGESEN_MASK) + +#define USDHC_INT_STATUS_EN_DINTSEN_MASK (0x8U) +#define USDHC_INT_STATUS_EN_DINTSEN_SHIFT (3U) +/*! DINTSEN - DMA interrupt status enable + * 0b0..Masked + * 0b1..Enabled + */ +#define USDHC_INT_STATUS_EN_DINTSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DINTSEN_SHIFT)) & USDHC_INT_STATUS_EN_DINTSEN_MASK) + +#define USDHC_INT_STATUS_EN_BWRSEN_MASK (0x10U) +#define USDHC_INT_STATUS_EN_BWRSEN_SHIFT (4U) +/*! BWRSEN - Buffer write ready status enable + * 0b0..Masked + * 0b1..Enabled + */ +#define USDHC_INT_STATUS_EN_BWRSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_BWRSEN_SHIFT)) & USDHC_INT_STATUS_EN_BWRSEN_MASK) + +#define USDHC_INT_STATUS_EN_BRRSEN_MASK (0x20U) +#define USDHC_INT_STATUS_EN_BRRSEN_SHIFT (5U) +/*! BRRSEN - Buffer read ready status enable + * 0b0..Masked + * 0b1..Enabled + */ +#define USDHC_INT_STATUS_EN_BRRSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_BRRSEN_SHIFT)) & USDHC_INT_STATUS_EN_BRRSEN_MASK) + +#define USDHC_INT_STATUS_EN_CINSSEN_MASK (0x40U) +#define USDHC_INT_STATUS_EN_CINSSEN_SHIFT (6U) +/*! CINSSEN - Card insertion status enable + * 0b0..Masked + * 0b1..Enabled + */ +#define USDHC_INT_STATUS_EN_CINSSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CINSSEN_SHIFT)) & USDHC_INT_STATUS_EN_CINSSEN_MASK) + +#define USDHC_INT_STATUS_EN_CRMSEN_MASK (0x80U) +#define USDHC_INT_STATUS_EN_CRMSEN_SHIFT (7U) +/*! CRMSEN - Card removal status enable + * 0b0..Masked + * 0b1..Enabled + */ +#define USDHC_INT_STATUS_EN_CRMSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CRMSEN_SHIFT)) & USDHC_INT_STATUS_EN_CRMSEN_MASK) + +#define USDHC_INT_STATUS_EN_CINTSEN_MASK (0x100U) +#define USDHC_INT_STATUS_EN_CINTSEN_SHIFT (8U) +/*! CINTSEN - Card interrupt status enable + * 0b0..Masked + * 0b1..Enabled + */ +#define USDHC_INT_STATUS_EN_CINTSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CINTSEN_SHIFT)) & USDHC_INT_STATUS_EN_CINTSEN_MASK) + +#define USDHC_INT_STATUS_EN_RTESEN_MASK (0x1000U) +#define USDHC_INT_STATUS_EN_RTESEN_SHIFT (12U) +/*! RTESEN - Re-tuning event status enable + * 0b0..Masked + * 0b1..Enabled + */ +#define USDHC_INT_STATUS_EN_RTESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_RTESEN_SHIFT)) & USDHC_INT_STATUS_EN_RTESEN_MASK) + +#define USDHC_INT_STATUS_EN_TPSEN_MASK (0x2000U) +#define USDHC_INT_STATUS_EN_TPSEN_SHIFT (13U) +/*! TPSEN - Tuning pass status enable + * 0b0..Masked + * 0b1..Enabled + */ +#define USDHC_INT_STATUS_EN_TPSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_TPSEN_SHIFT)) & USDHC_INT_STATUS_EN_TPSEN_MASK) + +#define USDHC_INT_STATUS_EN_CQISEN_MASK (0x4000U) +#define USDHC_INT_STATUS_EN_CQISEN_SHIFT (14U) +/*! CQISEN - Command queuing status enable + * 0b0..Masked + * 0b1..Enabled + */ +#define USDHC_INT_STATUS_EN_CQISEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CQISEN_SHIFT)) & USDHC_INT_STATUS_EN_CQISEN_MASK) + +#define USDHC_INT_STATUS_EN_CTOESEN_MASK (0x10000U) +#define USDHC_INT_STATUS_EN_CTOESEN_SHIFT (16U) +/*! CTOESEN - Command timeout error status enable + * 0b0..Masked + * 0b1..Enabled + */ +#define USDHC_INT_STATUS_EN_CTOESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CTOESEN_SHIFT)) & USDHC_INT_STATUS_EN_CTOESEN_MASK) + +#define USDHC_INT_STATUS_EN_CCESEN_MASK (0x20000U) +#define USDHC_INT_STATUS_EN_CCESEN_SHIFT (17U) +/*! CCESEN - Command CRC error status enable + * 0b0..Masked + * 0b1..Enabled + */ +#define USDHC_INT_STATUS_EN_CCESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CCESEN_SHIFT)) & USDHC_INT_STATUS_EN_CCESEN_MASK) + +#define USDHC_INT_STATUS_EN_CEBESEN_MASK (0x40000U) +#define USDHC_INT_STATUS_EN_CEBESEN_SHIFT (18U) +/*! CEBESEN - Command end bit error status enable + * 0b0..Masked + * 0b1..Enabled + */ +#define USDHC_INT_STATUS_EN_CEBESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CEBESEN_SHIFT)) & USDHC_INT_STATUS_EN_CEBESEN_MASK) + +#define USDHC_INT_STATUS_EN_CIESEN_MASK (0x80000U) +#define USDHC_INT_STATUS_EN_CIESEN_SHIFT (19U) +/*! CIESEN - Command index error status enable + * 0b0..Masked + * 0b1..Enabled + */ +#define USDHC_INT_STATUS_EN_CIESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CIESEN_SHIFT)) & USDHC_INT_STATUS_EN_CIESEN_MASK) + +#define USDHC_INT_STATUS_EN_DTOESEN_MASK (0x100000U) +#define USDHC_INT_STATUS_EN_DTOESEN_SHIFT (20U) +/*! DTOESEN - Data timeout error status enable + * 0b0..Masked + * 0b1..Enabled + */ +#define USDHC_INT_STATUS_EN_DTOESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DTOESEN_SHIFT)) & USDHC_INT_STATUS_EN_DTOESEN_MASK) + +#define USDHC_INT_STATUS_EN_DCESEN_MASK (0x200000U) +#define USDHC_INT_STATUS_EN_DCESEN_SHIFT (21U) +/*! DCESEN - Data CRC error status enable + * 0b0..Masked + * 0b1..Enabled + */ +#define USDHC_INT_STATUS_EN_DCESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DCESEN_SHIFT)) & USDHC_INT_STATUS_EN_DCESEN_MASK) + +#define USDHC_INT_STATUS_EN_DEBESEN_MASK (0x400000U) +#define USDHC_INT_STATUS_EN_DEBESEN_SHIFT (22U) +/*! DEBESEN - Data end bit error status enable + * 0b0..Masked + * 0b1..Enabled + */ +#define USDHC_INT_STATUS_EN_DEBESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DEBESEN_SHIFT)) & USDHC_INT_STATUS_EN_DEBESEN_MASK) + +#define USDHC_INT_STATUS_EN_AC12ESEN_MASK (0x1000000U) +#define USDHC_INT_STATUS_EN_AC12ESEN_SHIFT (24U) +/*! AC12ESEN - Auto CMD12 error status enable + * 0b0..Masked + * 0b1..Enabled + */ +#define USDHC_INT_STATUS_EN_AC12ESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_AC12ESEN_SHIFT)) & USDHC_INT_STATUS_EN_AC12ESEN_MASK) + +#define USDHC_INT_STATUS_EN_TNESEN_MASK (0x4000000U) +#define USDHC_INT_STATUS_EN_TNESEN_SHIFT (26U) +/*! TNESEN - Tuning error status enable + * 0b0..Masked + * 0b1..Enabled + */ +#define USDHC_INT_STATUS_EN_TNESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_TNESEN_SHIFT)) & USDHC_INT_STATUS_EN_TNESEN_MASK) + +#define USDHC_INT_STATUS_EN_DMAESEN_MASK (0x10000000U) +#define USDHC_INT_STATUS_EN_DMAESEN_SHIFT (28U) +/*! DMAESEN - DMA error status enable + * 0b0..Masked + * 0b1..Enabled + */ +#define USDHC_INT_STATUS_EN_DMAESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DMAESEN_SHIFT)) & USDHC_INT_STATUS_EN_DMAESEN_MASK) +/*! @} */ + +/*! @name INT_SIGNAL_EN - Interrupt Signal Enable */ +/*! @{ */ + +#define USDHC_INT_SIGNAL_EN_CCIEN_MASK (0x1U) +#define USDHC_INT_SIGNAL_EN_CCIEN_SHIFT (0U) +/*! CCIEN - Command complete interrupt enable + * 0b0..Masked + * 0b1..Enabled + */ +#define USDHC_INT_SIGNAL_EN_CCIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CCIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CCIEN_MASK) + +#define USDHC_INT_SIGNAL_EN_TCIEN_MASK (0x2U) +#define USDHC_INT_SIGNAL_EN_TCIEN_SHIFT (1U) +/*! TCIEN - Transfer complete interrupt enable + * 0b0..Masked + * 0b1..Enabled + */ +#define USDHC_INT_SIGNAL_EN_TCIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_TCIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_TCIEN_MASK) + +#define USDHC_INT_SIGNAL_EN_BGEIEN_MASK (0x4U) +#define USDHC_INT_SIGNAL_EN_BGEIEN_SHIFT (2U) +/*! BGEIEN - Block gap event interrupt enable + * 0b0..Masked + * 0b1..Enabled + */ +#define USDHC_INT_SIGNAL_EN_BGEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_BGEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_BGEIEN_MASK) + +#define USDHC_INT_SIGNAL_EN_DINTIEN_MASK (0x8U) +#define USDHC_INT_SIGNAL_EN_DINTIEN_SHIFT (3U) +/*! DINTIEN - DMA interrupt enable + * 0b0..Masked + * 0b1..Enabled + */ +#define USDHC_INT_SIGNAL_EN_DINTIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DINTIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DINTIEN_MASK) + +#define USDHC_INT_SIGNAL_EN_BWRIEN_MASK (0x10U) +#define USDHC_INT_SIGNAL_EN_BWRIEN_SHIFT (4U) +/*! BWRIEN - Buffer write ready interrupt enable + * 0b0..Masked + * 0b1..Enabled + */ +#define USDHC_INT_SIGNAL_EN_BWRIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_BWRIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_BWRIEN_MASK) + +#define USDHC_INT_SIGNAL_EN_BRRIEN_MASK (0x20U) +#define USDHC_INT_SIGNAL_EN_BRRIEN_SHIFT (5U) +/*! BRRIEN - Buffer read ready interrupt enable + * 0b0..Masked + * 0b1..Enabled + */ +#define USDHC_INT_SIGNAL_EN_BRRIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_BRRIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_BRRIEN_MASK) + +#define USDHC_INT_SIGNAL_EN_CINSIEN_MASK (0x40U) +#define USDHC_INT_SIGNAL_EN_CINSIEN_SHIFT (6U) +/*! CINSIEN - Card insertion interrupt enable + * 0b0..Masked + * 0b1..Enabled + */ +#define USDHC_INT_SIGNAL_EN_CINSIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CINSIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CINSIEN_MASK) + +#define USDHC_INT_SIGNAL_EN_CRMIEN_MASK (0x80U) +#define USDHC_INT_SIGNAL_EN_CRMIEN_SHIFT (7U) +/*! CRMIEN - Card removal interrupt enable + * 0b0..Masked + * 0b1..Enabled + */ +#define USDHC_INT_SIGNAL_EN_CRMIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CRMIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CRMIEN_MASK) + +#define USDHC_INT_SIGNAL_EN_CINTIEN_MASK (0x100U) +#define USDHC_INT_SIGNAL_EN_CINTIEN_SHIFT (8U) +/*! CINTIEN - Card interrupt enable + * 0b0..Masked + * 0b1..Enabled + */ +#define USDHC_INT_SIGNAL_EN_CINTIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CINTIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CINTIEN_MASK) + +#define USDHC_INT_SIGNAL_EN_RTEIEN_MASK (0x1000U) +#define USDHC_INT_SIGNAL_EN_RTEIEN_SHIFT (12U) +/*! RTEIEN - Re-tuning event interrupt enable + * 0b0..Masked + * 0b1..Enabled + */ +#define USDHC_INT_SIGNAL_EN_RTEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_RTEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_RTEIEN_MASK) + +#define USDHC_INT_SIGNAL_EN_TPIEN_MASK (0x2000U) +#define USDHC_INT_SIGNAL_EN_TPIEN_SHIFT (13U) +/*! TPIEN - Tuning pass interrupt enable + * 0b0..Masked + * 0b1..Enabled + */ +#define USDHC_INT_SIGNAL_EN_TPIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_TPIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_TPIEN_MASK) + +#define USDHC_INT_SIGNAL_EN_CQIIEN_MASK (0x4000U) +#define USDHC_INT_SIGNAL_EN_CQIIEN_SHIFT (14U) +/*! CQIIEN - Command queuing signal enable + * 0b0..Masked + * 0b1..Enabled + */ +#define USDHC_INT_SIGNAL_EN_CQIIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CQIIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CQIIEN_MASK) + +#define USDHC_INT_SIGNAL_EN_CTOEIEN_MASK (0x10000U) +#define USDHC_INT_SIGNAL_EN_CTOEIEN_SHIFT (16U) +/*! CTOEIEN - Command timeout error interrupt enable + * 0b0..Masked + * 0b1..Enabled + */ +#define USDHC_INT_SIGNAL_EN_CTOEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CTOEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CTOEIEN_MASK) + +#define USDHC_INT_SIGNAL_EN_CCEIEN_MASK (0x20000U) +#define USDHC_INT_SIGNAL_EN_CCEIEN_SHIFT (17U) +/*! CCEIEN - Command CRC error interrupt enable + * 0b0..Masked + * 0b1..Enabled + */ +#define USDHC_INT_SIGNAL_EN_CCEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CCEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CCEIEN_MASK) + +#define USDHC_INT_SIGNAL_EN_CEBEIEN_MASK (0x40000U) +#define USDHC_INT_SIGNAL_EN_CEBEIEN_SHIFT (18U) +/*! CEBEIEN - Command end bit error interrupt enable + * 0b0..Masked + * 0b1..Enabled + */ +#define USDHC_INT_SIGNAL_EN_CEBEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CEBEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CEBEIEN_MASK) + +#define USDHC_INT_SIGNAL_EN_CIEIEN_MASK (0x80000U) +#define USDHC_INT_SIGNAL_EN_CIEIEN_SHIFT (19U) +/*! CIEIEN - Command index error interrupt enable + * 0b0..Masked + * 0b1..Enabled + */ +#define USDHC_INT_SIGNAL_EN_CIEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CIEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CIEIEN_MASK) + +#define USDHC_INT_SIGNAL_EN_DTOEIEN_MASK (0x100000U) +#define USDHC_INT_SIGNAL_EN_DTOEIEN_SHIFT (20U) +/*! DTOEIEN - Data timeout error interrupt enable + * 0b0..Masked + * 0b1..Enabled + */ +#define USDHC_INT_SIGNAL_EN_DTOEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DTOEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DTOEIEN_MASK) + +#define USDHC_INT_SIGNAL_EN_DCEIEN_MASK (0x200000U) +#define USDHC_INT_SIGNAL_EN_DCEIEN_SHIFT (21U) +/*! DCEIEN - Data CRC error interrupt enable + * 0b0..Masked + * 0b1..Enabled + */ +#define USDHC_INT_SIGNAL_EN_DCEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DCEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DCEIEN_MASK) + +#define USDHC_INT_SIGNAL_EN_DEBEIEN_MASK (0x400000U) +#define USDHC_INT_SIGNAL_EN_DEBEIEN_SHIFT (22U) +/*! DEBEIEN - Data end bit error interrupt enable + * 0b0..Masked + * 0b1..Enabled + */ +#define USDHC_INT_SIGNAL_EN_DEBEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DEBEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DEBEIEN_MASK) + +#define USDHC_INT_SIGNAL_EN_AC12EIEN_MASK (0x1000000U) +#define USDHC_INT_SIGNAL_EN_AC12EIEN_SHIFT (24U) +/*! AC12EIEN - Auto CMD12 error interrupt enable + * 0b0..Masked + * 0b1..Enabled + */ +#define USDHC_INT_SIGNAL_EN_AC12EIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_AC12EIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_AC12EIEN_MASK) + +#define USDHC_INT_SIGNAL_EN_TNEIEN_MASK (0x4000000U) +#define USDHC_INT_SIGNAL_EN_TNEIEN_SHIFT (26U) +/*! TNEIEN - Tuning error interrupt enable + * 0b0..Masked + * 0b1..Enabled + */ +#define USDHC_INT_SIGNAL_EN_TNEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_TNEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_TNEIEN_MASK) + +#define USDHC_INT_SIGNAL_EN_DMAEIEN_MASK (0x10000000U) +#define USDHC_INT_SIGNAL_EN_DMAEIEN_SHIFT (28U) +/*! DMAEIEN - DMA error interrupt enable + * 0b0..Masked + * 0b1..Enable + */ +#define USDHC_INT_SIGNAL_EN_DMAEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DMAEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DMAEIEN_MASK) +/*! @} */ + +/*! @name AUTOCMD12_ERR_STATUS - Auto CMD12 Error Status */ +/*! @{ */ + +#define USDHC_AUTOCMD12_ERR_STATUS_AC12NE_MASK (0x1U) +#define USDHC_AUTOCMD12_ERR_STATUS_AC12NE_SHIFT (0U) +/*! AC12NE - Auto CMD12 not executed + * 0b0..Executed + * 0b1..Not executed + */ +#define USDHC_AUTOCMD12_ERR_STATUS_AC12NE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12NE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12NE_MASK) + +#define USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_MASK (0x2U) +#define USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_SHIFT (1U) +/*! AC12TOE - Auto CMD12 / 23 timeout error + * 0b0..No error + * 0b1..Time out + */ +#define USDHC_AUTOCMD12_ERR_STATUS_AC12TOE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_MASK) + +#define USDHC_AUTOCMD12_ERR_STATUS_AC12CE_MASK (0x4U) +#define USDHC_AUTOCMD12_ERR_STATUS_AC12CE_SHIFT (2U) +/*! AC12CE - Auto CMD12 / 23 CRC error + * 0b0..No CRC error + * 0b1..CRC error met in Auto CMD12/23 response + */ +#define USDHC_AUTOCMD12_ERR_STATUS_AC12CE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12CE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12CE_MASK) + +#define USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_MASK (0x8U) +#define USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_SHIFT (3U) +/*! AC12EBE - Auto CMD12 / 23 end bit error + * 0b0..No error + * 0b1..End bit error generated + */ +#define USDHC_AUTOCMD12_ERR_STATUS_AC12EBE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_MASK) + +#define USDHC_AUTOCMD12_ERR_STATUS_AC12IE_MASK (0x10U) +#define USDHC_AUTOCMD12_ERR_STATUS_AC12IE_SHIFT (4U) +/*! AC12IE - Auto CMD12 / 23 index error + * 0b0..No error + * 0b1..Error, the CMD index in response is not CMD12/23 + */ +#define USDHC_AUTOCMD12_ERR_STATUS_AC12IE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12IE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12IE_MASK) + +#define USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_MASK (0x80U) +#define USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_SHIFT (7U) +/*! CNIBAC12E - Command not issued by Auto CMD12 error + * 0b0..No error + * 0b1..Not issued + */ +#define USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_MASK) + +#define USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_MASK (0x400000U) +#define USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_SHIFT (22U) +/*! EXECUTE_TUNING - Execute tuning + * 0b0..Tuning procedure is aborted + * 0b1..Start tuning procedure + */ +#define USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_MASK) + +#define USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_MASK (0x800000U) +#define USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_SHIFT (23U) +/*! SMP_CLK_SEL - Sample clock select + * 0b0..Fixed clock is used to sample data + * 0b1..Tuned clock is used to sample data + */ +#define USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_MASK) +/*! @} */ + +/*! @name HOST_CTRL_CAP - Host Controller Capabilities */ +/*! @{ */ + +#define USDHC_HOST_CTRL_CAP_SDR50_SUPPORT_MASK (0x1U) +#define USDHC_HOST_CTRL_CAP_SDR50_SUPPORT_SHIFT (0U) +/*! SDR50_SUPPORT - SDR50 support */ +#define USDHC_HOST_CTRL_CAP_SDR50_SUPPORT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_SDR50_SUPPORT_SHIFT)) & USDHC_HOST_CTRL_CAP_SDR50_SUPPORT_MASK) + +#define USDHC_HOST_CTRL_CAP_SDR104_SUPPORT_MASK (0x2U) +#define USDHC_HOST_CTRL_CAP_SDR104_SUPPORT_SHIFT (1U) +/*! SDR104_SUPPORT - SDR104 support */ +#define USDHC_HOST_CTRL_CAP_SDR104_SUPPORT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_SDR104_SUPPORT_SHIFT)) & USDHC_HOST_CTRL_CAP_SDR104_SUPPORT_MASK) + +#define USDHC_HOST_CTRL_CAP_DDR50_SUPPORT_MASK (0x4U) +#define USDHC_HOST_CTRL_CAP_DDR50_SUPPORT_SHIFT (2U) +/*! DDR50_SUPPORT - DDR50 support */ +#define USDHC_HOST_CTRL_CAP_DDR50_SUPPORT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_DDR50_SUPPORT_SHIFT)) & USDHC_HOST_CTRL_CAP_DDR50_SUPPORT_MASK) + +#define USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50_MASK (0x2000U) +#define USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50_SHIFT (13U) +/*! USE_TUNING_SDR50 - Use Tuning for SDR50 + * 0b0..SDR50 does not support tuning + * 0b1..SDR50 supports tuning + */ +#define USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50_SHIFT)) & USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50_MASK) + +#define USDHC_HOST_CTRL_CAP_MBL_MASK (0x70000U) +#define USDHC_HOST_CTRL_CAP_MBL_SHIFT (16U) +/*! MBL - Max block length + * 0b000..512 bytes + * 0b001..1024 bytes + * 0b010..2048 bytes + * 0b011..4096 bytes + */ +#define USDHC_HOST_CTRL_CAP_MBL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_MBL_SHIFT)) & USDHC_HOST_CTRL_CAP_MBL_MASK) + +#define USDHC_HOST_CTRL_CAP_ADMAS_MASK (0x100000U) +#define USDHC_HOST_CTRL_CAP_ADMAS_SHIFT (20U) +/*! ADMAS - ADMA support + * 0b0..Advanced DMA not supported + * 0b1..Advanced DMA supported + */ +#define USDHC_HOST_CTRL_CAP_ADMAS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_ADMAS_SHIFT)) & USDHC_HOST_CTRL_CAP_ADMAS_MASK) + +#define USDHC_HOST_CTRL_CAP_HSS_MASK (0x200000U) +#define USDHC_HOST_CTRL_CAP_HSS_SHIFT (21U) +/*! HSS - High speed support + * 0b0..High speed not supported + * 0b1..High speed supported + */ +#define USDHC_HOST_CTRL_CAP_HSS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_HSS_SHIFT)) & USDHC_HOST_CTRL_CAP_HSS_MASK) + +#define USDHC_HOST_CTRL_CAP_DMAS_MASK (0x400000U) +#define USDHC_HOST_CTRL_CAP_DMAS_SHIFT (22U) +/*! DMAS - DMA support + * 0b0..DMA not supported + * 0b1..DMA supported + */ +#define USDHC_HOST_CTRL_CAP_DMAS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_DMAS_SHIFT)) & USDHC_HOST_CTRL_CAP_DMAS_MASK) + +#define USDHC_HOST_CTRL_CAP_SRS_MASK (0x800000U) +#define USDHC_HOST_CTRL_CAP_SRS_SHIFT (23U) +/*! SRS - Suspend / resume support + * 0b0..Not supported + * 0b1..Supported + */ +#define USDHC_HOST_CTRL_CAP_SRS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_SRS_SHIFT)) & USDHC_HOST_CTRL_CAP_SRS_MASK) + +#define USDHC_HOST_CTRL_CAP_VS33_MASK (0x1000000U) +#define USDHC_HOST_CTRL_CAP_VS33_SHIFT (24U) +/*! VS33 - Voltage support 3.3 V + * 0b0..3.3 V not supported + * 0b1..3.3 V supported + */ +#define USDHC_HOST_CTRL_CAP_VS33(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_VS33_SHIFT)) & USDHC_HOST_CTRL_CAP_VS33_MASK) + +#define USDHC_HOST_CTRL_CAP_VS30_MASK (0x2000000U) +#define USDHC_HOST_CTRL_CAP_VS30_SHIFT (25U) +/*! VS30 - Voltage support 3.0 V + * 0b0..3.0 V not supported + * 0b1..3.0 V supported + */ +#define USDHC_HOST_CTRL_CAP_VS30(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_VS30_SHIFT)) & USDHC_HOST_CTRL_CAP_VS30_MASK) + +#define USDHC_HOST_CTRL_CAP_VS18_MASK (0x4000000U) +#define USDHC_HOST_CTRL_CAP_VS18_SHIFT (26U) +/*! VS18 - Voltage support 1.8 V + * 0b0..1.8 V not supported + * 0b1..1.8 V supported + */ +#define USDHC_HOST_CTRL_CAP_VS18(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_VS18_SHIFT)) & USDHC_HOST_CTRL_CAP_VS18_MASK) +/*! @} */ + +/*! @name WTMK_LVL - Watermark Level */ +/*! @{ */ + +#define USDHC_WTMK_LVL_RD_WML_MASK (0xFFU) +#define USDHC_WTMK_LVL_RD_WML_SHIFT (0U) +/*! RD_WML - Read watermark level */ +#define USDHC_WTMK_LVL_RD_WML(x) (((uint32_t)(((uint32_t)(x)) << USDHC_WTMK_LVL_RD_WML_SHIFT)) & USDHC_WTMK_LVL_RD_WML_MASK) + +#define USDHC_WTMK_LVL_WR_WML_MASK (0xFF0000U) +#define USDHC_WTMK_LVL_WR_WML_SHIFT (16U) +/*! WR_WML - Write watermark level */ +#define USDHC_WTMK_LVL_WR_WML(x) (((uint32_t)(((uint32_t)(x)) << USDHC_WTMK_LVL_WR_WML_SHIFT)) & USDHC_WTMK_LVL_WR_WML_MASK) +/*! @} */ + +/*! @name MIX_CTRL - Mixer Control */ +/*! @{ */ + +#define USDHC_MIX_CTRL_DMAEN_MASK (0x1U) +#define USDHC_MIX_CTRL_DMAEN_SHIFT (0U) +/*! DMAEN - DMA enable + * 0b0..Disable + * 0b1..Enable + */ +#define USDHC_MIX_CTRL_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_DMAEN_SHIFT)) & USDHC_MIX_CTRL_DMAEN_MASK) + +#define USDHC_MIX_CTRL_BCEN_MASK (0x2U) +#define USDHC_MIX_CTRL_BCEN_SHIFT (1U) +/*! BCEN - Block count enable + * 0b0..Disable + * 0b1..Enable + */ +#define USDHC_MIX_CTRL_BCEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_BCEN_SHIFT)) & USDHC_MIX_CTRL_BCEN_MASK) + +#define USDHC_MIX_CTRL_AC12EN_MASK (0x4U) +#define USDHC_MIX_CTRL_AC12EN_SHIFT (2U) +/*! AC12EN - Auto CMD12 enable + * 0b0..Disable + * 0b1..Enable + */ +#define USDHC_MIX_CTRL_AC12EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_AC12EN_SHIFT)) & USDHC_MIX_CTRL_AC12EN_MASK) + +#define USDHC_MIX_CTRL_DDR_EN_MASK (0x8U) +#define USDHC_MIX_CTRL_DDR_EN_SHIFT (3U) +/*! DDR_EN - Dual data rate mode selection */ +#define USDHC_MIX_CTRL_DDR_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_DDR_EN_SHIFT)) & USDHC_MIX_CTRL_DDR_EN_MASK) + +#define USDHC_MIX_CTRL_DTDSEL_MASK (0x10U) +#define USDHC_MIX_CTRL_DTDSEL_SHIFT (4U) +/*! DTDSEL - Data transfer direction select + * 0b0..Write (Host to card) + * 0b1..Read (Card to host) + */ +#define USDHC_MIX_CTRL_DTDSEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_DTDSEL_SHIFT)) & USDHC_MIX_CTRL_DTDSEL_MASK) + +#define USDHC_MIX_CTRL_MSBSEL_MASK (0x20U) +#define USDHC_MIX_CTRL_MSBSEL_SHIFT (5U) +/*! MSBSEL - Multi / Single block select + * 0b0..Single block + * 0b1..Multiple blocks + */ +#define USDHC_MIX_CTRL_MSBSEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_MSBSEL_SHIFT)) & USDHC_MIX_CTRL_MSBSEL_MASK) + +#define USDHC_MIX_CTRL_NIBBLE_POS_MASK (0x40U) +#define USDHC_MIX_CTRL_NIBBLE_POS_SHIFT (6U) +/*! NIBBLE_POS - Nibble position indication */ +#define USDHC_MIX_CTRL_NIBBLE_POS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_NIBBLE_POS_SHIFT)) & USDHC_MIX_CTRL_NIBBLE_POS_MASK) + +#define USDHC_MIX_CTRL_AC23EN_MASK (0x80U) +#define USDHC_MIX_CTRL_AC23EN_SHIFT (7U) +/*! AC23EN - Auto CMD23 enable */ +#define USDHC_MIX_CTRL_AC23EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_AC23EN_SHIFT)) & USDHC_MIX_CTRL_AC23EN_MASK) + +#define USDHC_MIX_CTRL_EXE_TUNE_MASK (0x400000U) +#define USDHC_MIX_CTRL_EXE_TUNE_SHIFT (22U) +/*! EXE_TUNE - Execute tuning: (Only used for SD3.0, SDR104 mode and eMMC HS200 mode) + * 0b0..Not tuned or tuning completed + * 0b1..Execute tuning + */ +#define USDHC_MIX_CTRL_EXE_TUNE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_EXE_TUNE_SHIFT)) & USDHC_MIX_CTRL_EXE_TUNE_MASK) + +#define USDHC_MIX_CTRL_SMP_CLK_SEL_MASK (0x800000U) +#define USDHC_MIX_CTRL_SMP_CLK_SEL_SHIFT (23U) +/*! SMP_CLK_SEL - Clock selection + * 0b0..Fixed clock is used to sample data / cmd + * 0b1..Tuned clock is used to sample data / cmd + */ +#define USDHC_MIX_CTRL_SMP_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_SMP_CLK_SEL_SHIFT)) & USDHC_MIX_CTRL_SMP_CLK_SEL_MASK) + +#define USDHC_MIX_CTRL_AUTO_TUNE_EN_MASK (0x1000000U) +#define USDHC_MIX_CTRL_AUTO_TUNE_EN_SHIFT (24U) +/*! AUTO_TUNE_EN - Auto tuning enable (Only used for SD3.0, SDR104 mode and eMMC HS200 mode) + * 0b0..Disable auto tuning + * 0b1..Enable auto tuning + */ +#define USDHC_MIX_CTRL_AUTO_TUNE_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_AUTO_TUNE_EN_SHIFT)) & USDHC_MIX_CTRL_AUTO_TUNE_EN_MASK) + +#define USDHC_MIX_CTRL_FBCLK_SEL_MASK (0x2000000U) +#define USDHC_MIX_CTRL_FBCLK_SEL_SHIFT (25U) +/*! FBCLK_SEL - Feedback clock source selection (Only used for SD3.0, SDR104 mode and eMMC HS200 mode) + * 0b0..Feedback clock comes from the loopback CLK + * 0b1..Feedback clock comes from the ipp_card_clk_out + */ +#define USDHC_MIX_CTRL_FBCLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_FBCLK_SEL_SHIFT)) & USDHC_MIX_CTRL_FBCLK_SEL_MASK) + +#define USDHC_MIX_CTRL_HS400_MODE_MASK (0x4000000U) +#define USDHC_MIX_CTRL_HS400_MODE_SHIFT (26U) +/*! HS400_MODE - Enable HS400 mode */ +#define USDHC_MIX_CTRL_HS400_MODE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_HS400_MODE_SHIFT)) & USDHC_MIX_CTRL_HS400_MODE_MASK) + +#define USDHC_MIX_CTRL_EN_HS400_MODE_MASK (0x8000000U) +#define USDHC_MIX_CTRL_EN_HS400_MODE_SHIFT (27U) +/*! EN_HS400_MODE - Enable enhance HS400 mode */ +#define USDHC_MIX_CTRL_EN_HS400_MODE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_EN_HS400_MODE_SHIFT)) & USDHC_MIX_CTRL_EN_HS400_MODE_MASK) +/*! @} */ + +/*! @name FORCE_EVENT - Force Event */ +/*! @{ */ + +#define USDHC_FORCE_EVENT_FEVTAC12NE_MASK (0x1U) +#define USDHC_FORCE_EVENT_FEVTAC12NE_SHIFT (0U) +/*! FEVTAC12NE - Force event auto command 12 not executed */ +#define USDHC_FORCE_EVENT_FEVTAC12NE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12NE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12NE_MASK) + +#define USDHC_FORCE_EVENT_FEVTAC12TOE_MASK (0x2U) +#define USDHC_FORCE_EVENT_FEVTAC12TOE_SHIFT (1U) +/*! FEVTAC12TOE - Force event auto command 12 time out error */ +#define USDHC_FORCE_EVENT_FEVTAC12TOE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12TOE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12TOE_MASK) + +#define USDHC_FORCE_EVENT_FEVTAC12CE_MASK (0x4U) +#define USDHC_FORCE_EVENT_FEVTAC12CE_SHIFT (2U) +/*! FEVTAC12CE - Force event auto command 12 CRC error */ +#define USDHC_FORCE_EVENT_FEVTAC12CE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12CE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12CE_MASK) + +#define USDHC_FORCE_EVENT_FEVTAC12EBE_MASK (0x8U) +#define USDHC_FORCE_EVENT_FEVTAC12EBE_SHIFT (3U) +/*! FEVTAC12EBE - Force event Auto Command 12 end bit error */ +#define USDHC_FORCE_EVENT_FEVTAC12EBE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12EBE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12EBE_MASK) + +#define USDHC_FORCE_EVENT_FEVTAC12IE_MASK (0x10U) +#define USDHC_FORCE_EVENT_FEVTAC12IE_SHIFT (4U) +/*! FEVTAC12IE - Force event Auto Command 12 index error */ +#define USDHC_FORCE_EVENT_FEVTAC12IE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12IE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12IE_MASK) + +#define USDHC_FORCE_EVENT_FEVTCNIBAC12E_MASK (0x80U) +#define USDHC_FORCE_EVENT_FEVTCNIBAC12E_SHIFT (7U) +/*! FEVTCNIBAC12E - Force event command not executed by Auto Command 12 error */ +#define USDHC_FORCE_EVENT_FEVTCNIBAC12E(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCNIBAC12E_SHIFT)) & USDHC_FORCE_EVENT_FEVTCNIBAC12E_MASK) + +#define USDHC_FORCE_EVENT_FEVTCTOE_MASK (0x10000U) +#define USDHC_FORCE_EVENT_FEVTCTOE_SHIFT (16U) +/*! FEVTCTOE - Force event command time out error */ +#define USDHC_FORCE_EVENT_FEVTCTOE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCTOE_SHIFT)) & USDHC_FORCE_EVENT_FEVTCTOE_MASK) + +#define USDHC_FORCE_EVENT_FEVTCCE_MASK (0x20000U) +#define USDHC_FORCE_EVENT_FEVTCCE_SHIFT (17U) +/*! FEVTCCE - Force event command CRC error */ +#define USDHC_FORCE_EVENT_FEVTCCE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCCE_SHIFT)) & USDHC_FORCE_EVENT_FEVTCCE_MASK) + +#define USDHC_FORCE_EVENT_FEVTCEBE_MASK (0x40000U) +#define USDHC_FORCE_EVENT_FEVTCEBE_SHIFT (18U) +/*! FEVTCEBE - Force event command end bit error */ +#define USDHC_FORCE_EVENT_FEVTCEBE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCEBE_SHIFT)) & USDHC_FORCE_EVENT_FEVTCEBE_MASK) + +#define USDHC_FORCE_EVENT_FEVTCIE_MASK (0x80000U) +#define USDHC_FORCE_EVENT_FEVTCIE_SHIFT (19U) +/*! FEVTCIE - Force event command index error */ +#define USDHC_FORCE_EVENT_FEVTCIE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCIE_SHIFT)) & USDHC_FORCE_EVENT_FEVTCIE_MASK) + +#define USDHC_FORCE_EVENT_FEVTDTOE_MASK (0x100000U) +#define USDHC_FORCE_EVENT_FEVTDTOE_SHIFT (20U) +/*! FEVTDTOE - Force event data time out error */ +#define USDHC_FORCE_EVENT_FEVTDTOE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTDTOE_SHIFT)) & USDHC_FORCE_EVENT_FEVTDTOE_MASK) + +#define USDHC_FORCE_EVENT_FEVTDCE_MASK (0x200000U) +#define USDHC_FORCE_EVENT_FEVTDCE_SHIFT (21U) +/*! FEVTDCE - Force event data CRC error */ +#define USDHC_FORCE_EVENT_FEVTDCE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTDCE_SHIFT)) & USDHC_FORCE_EVENT_FEVTDCE_MASK) + +#define USDHC_FORCE_EVENT_FEVTDEBE_MASK (0x400000U) +#define USDHC_FORCE_EVENT_FEVTDEBE_SHIFT (22U) +/*! FEVTDEBE - Force event data end bit error */ +#define USDHC_FORCE_EVENT_FEVTDEBE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTDEBE_SHIFT)) & USDHC_FORCE_EVENT_FEVTDEBE_MASK) + +#define USDHC_FORCE_EVENT_FEVTAC12E_MASK (0x1000000U) +#define USDHC_FORCE_EVENT_FEVTAC12E_SHIFT (24U) +/*! FEVTAC12E - Force event Auto Command 12 error */ +#define USDHC_FORCE_EVENT_FEVTAC12E(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12E_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12E_MASK) + +#define USDHC_FORCE_EVENT_FEVTTNE_MASK (0x4000000U) +#define USDHC_FORCE_EVENT_FEVTTNE_SHIFT (26U) +/*! FEVTTNE - Force tuning error */ +#define USDHC_FORCE_EVENT_FEVTTNE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTTNE_SHIFT)) & USDHC_FORCE_EVENT_FEVTTNE_MASK) + +#define USDHC_FORCE_EVENT_FEVTDMAE_MASK (0x10000000U) +#define USDHC_FORCE_EVENT_FEVTDMAE_SHIFT (28U) +/*! FEVTDMAE - Force event DMA error */ +#define USDHC_FORCE_EVENT_FEVTDMAE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTDMAE_SHIFT)) & USDHC_FORCE_EVENT_FEVTDMAE_MASK) + +#define USDHC_FORCE_EVENT_FEVTCINT_MASK (0x80000000U) +#define USDHC_FORCE_EVENT_FEVTCINT_SHIFT (31U) +/*! FEVTCINT - Force event card interrupt */ +#define USDHC_FORCE_EVENT_FEVTCINT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCINT_SHIFT)) & USDHC_FORCE_EVENT_FEVTCINT_MASK) +/*! @} */ + +/*! @name ADMA_ERR_STATUS - ADMA Error Status */ +/*! @{ */ + +#define USDHC_ADMA_ERR_STATUS_ADMAES_MASK (0x3U) +#define USDHC_ADMA_ERR_STATUS_ADMAES_SHIFT (0U) +/*! ADMAES - ADMA error state (when ADMA error is occurred) */ +#define USDHC_ADMA_ERR_STATUS_ADMAES(x) (((uint32_t)(((uint32_t)(x)) << USDHC_ADMA_ERR_STATUS_ADMAES_SHIFT)) & USDHC_ADMA_ERR_STATUS_ADMAES_MASK) + +#define USDHC_ADMA_ERR_STATUS_ADMALME_MASK (0x4U) +#define USDHC_ADMA_ERR_STATUS_ADMALME_SHIFT (2U) +/*! ADMALME - ADMA length mismatch error + * 0b0..No error + * 0b1..Error + */ +#define USDHC_ADMA_ERR_STATUS_ADMALME(x) (((uint32_t)(((uint32_t)(x)) << USDHC_ADMA_ERR_STATUS_ADMALME_SHIFT)) & USDHC_ADMA_ERR_STATUS_ADMALME_MASK) + +#define USDHC_ADMA_ERR_STATUS_ADMADCE_MASK (0x8U) +#define USDHC_ADMA_ERR_STATUS_ADMADCE_SHIFT (3U) +/*! ADMADCE - ADMA descriptor error + * 0b0..No error + * 0b1..Error + */ +#define USDHC_ADMA_ERR_STATUS_ADMADCE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_ADMA_ERR_STATUS_ADMADCE_SHIFT)) & USDHC_ADMA_ERR_STATUS_ADMADCE_MASK) +/*! @} */ + +/*! @name ADMA_SYS_ADDR - ADMA System Address */ +/*! @{ */ + +#define USDHC_ADMA_SYS_ADDR_ADS_ADDR_MASK (0xFFFFFFFCU) +#define USDHC_ADMA_SYS_ADDR_ADS_ADDR_SHIFT (2U) +/*! ADS_ADDR - ADMA system address */ +#define USDHC_ADMA_SYS_ADDR_ADS_ADDR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_ADMA_SYS_ADDR_ADS_ADDR_SHIFT)) & USDHC_ADMA_SYS_ADDR_ADS_ADDR_MASK) +/*! @} */ + +/*! @name DLL_CTRL - DLL (Delay Line) Control */ +/*! @{ */ + +#define USDHC_DLL_CTRL_DLL_CTRL_ENABLE_MASK (0x1U) +#define USDHC_DLL_CTRL_DLL_CTRL_ENABLE_SHIFT (0U) +/*! DLL_CTRL_ENABLE - DLL and delay chain */ +#define USDHC_DLL_CTRL_DLL_CTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_ENABLE_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_ENABLE_MASK) + +#define USDHC_DLL_CTRL_DLL_CTRL_RESET_MASK (0x2U) +#define USDHC_DLL_CTRL_DLL_CTRL_RESET_SHIFT (1U) +/*! DLL_CTRL_RESET - DLL reset */ +#define USDHC_DLL_CTRL_DLL_CTRL_RESET(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_RESET_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_RESET_MASK) + +#define USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD_MASK (0x4U) +#define USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD_SHIFT (2U) +/*! DLL_CTRL_SLV_FORCE_UPD - DLL slave delay line */ +#define USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD_MASK) + +#define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0_MASK (0x78U) +#define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0_SHIFT (3U) +/*! DLL_CTRL_SLV_DLY_TARGET0 - DLL slave delay target0 */ +#define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0_MASK) + +#define USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE_MASK (0x80U) +#define USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE_SHIFT (7U) +/*! DLL_CTRL_GATE_UPDATE - DLL gate update */ +#define USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE_MASK) + +#define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_MASK (0x100U) +#define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_SHIFT (8U) +/*! DLL_CTRL_SLV_OVERRIDE - DLL slave override */ +#define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_MASK) + +#define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL_MASK (0xFE00U) +#define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL_SHIFT (9U) +/*! DLL_CTRL_SLV_OVERRIDE_VAL - DLL slave override val */ +#define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL_MASK) + +#define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1_MASK (0x70000U) +#define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1_SHIFT (16U) +/*! DLL_CTRL_SLV_DLY_TARGET1 - DLL slave delay target1 */ +#define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1_MASK) + +#define USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT_MASK (0xFF00000U) +#define USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT_SHIFT (20U) +/*! DLL_CTRL_SLV_UPDATE_INT - Slave delay line update interval */ +#define USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT_MASK) + +#define USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT_MASK (0xF0000000U) +#define USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT_SHIFT (28U) +/*! DLL_CTRL_REF_UPDATE_INT - DLL control loop update interval */ +#define USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT_MASK) +/*! @} */ + +/*! @name DLL_STATUS - DLL Status */ +/*! @{ */ + +#define USDHC_DLL_STATUS_DLL_STS_SLV_LOCK_MASK (0x1U) +#define USDHC_DLL_STATUS_DLL_STS_SLV_LOCK_SHIFT (0U) +/*! DLL_STS_SLV_LOCK - Slave delay-line lock status */ +#define USDHC_DLL_STATUS_DLL_STS_SLV_LOCK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_STATUS_DLL_STS_SLV_LOCK_SHIFT)) & USDHC_DLL_STATUS_DLL_STS_SLV_LOCK_MASK) + +#define USDHC_DLL_STATUS_DLL_STS_REF_LOCK_MASK (0x2U) +#define USDHC_DLL_STATUS_DLL_STS_REF_LOCK_SHIFT (1U) +/*! DLL_STS_REF_LOCK - Reference DLL lock status */ +#define USDHC_DLL_STATUS_DLL_STS_REF_LOCK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_STATUS_DLL_STS_REF_LOCK_SHIFT)) & USDHC_DLL_STATUS_DLL_STS_REF_LOCK_MASK) + +#define USDHC_DLL_STATUS_DLL_STS_SLV_SEL_MASK (0x1FCU) +#define USDHC_DLL_STATUS_DLL_STS_SLV_SEL_SHIFT (2U) +/*! DLL_STS_SLV_SEL - Slave delay line select status */ +#define USDHC_DLL_STATUS_DLL_STS_SLV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_STATUS_DLL_STS_SLV_SEL_SHIFT)) & USDHC_DLL_STATUS_DLL_STS_SLV_SEL_MASK) + +#define USDHC_DLL_STATUS_DLL_STS_REF_SEL_MASK (0xFE00U) +#define USDHC_DLL_STATUS_DLL_STS_REF_SEL_SHIFT (9U) +/*! DLL_STS_REF_SEL - Reference delay line select taps */ +#define USDHC_DLL_STATUS_DLL_STS_REF_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_STATUS_DLL_STS_REF_SEL_SHIFT)) & USDHC_DLL_STATUS_DLL_STS_REF_SEL_MASK) +/*! @} */ + +/*! @name CLK_TUNE_CTRL_STATUS - CLK Tuning Control and Status */ +/*! @{ */ + +#define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST_MASK (0xFU) +#define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST_SHIFT (0U) +/*! DLY_CELL_SET_POST - Delay cells on the feedback clock between CLK_OUT and CLK_POST */ +#define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST_MASK) + +#define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT_MASK (0xF0U) +#define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT_SHIFT (4U) +/*! DLY_CELL_SET_OUT - Delay cells on the feedback clock between CLK_PRE and CLK_OUT */ +#define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT_MASK) + +#define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE_MASK (0x7F00U) +#define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE_SHIFT (8U) +/*! DLY_CELL_SET_PRE - delay cells on the feedback clock between the feedback clock and CLK_PRE */ +#define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE_MASK) + +#define USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR_MASK (0x8000U) +#define USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR_SHIFT (15U) +/*! NXT_ERR - NXT error */ +#define USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR_MASK) + +#define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST_MASK (0xF0000U) +#define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST_SHIFT (16U) +/*! TAP_SEL_POST - Delay cells added on the feedback clock between CLK_OUT and CLK_POST */ +#define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST_MASK) + +#define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT_MASK (0xF00000U) +#define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT_SHIFT (20U) +/*! TAP_SEL_OUT - Delay cells added on the feedback clock between CLK_PRE and CLK_OUT */ +#define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT_MASK) + +#define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE_MASK (0x7F000000U) +#define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE_SHIFT (24U) +/*! TAP_SEL_PRE - TAP_SEL_PRE */ +#define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE_MASK) + +#define USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR_MASK (0x80000000U) +#define USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR_SHIFT (31U) +/*! PRE_ERR - PRE error */ +#define USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR_MASK) +/*! @} */ + +/*! @name STROBE_DLL_CTRL - Strobe DLL control */ +/*! @{ */ + +#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_ENABLE_MASK (0x1U) +#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_ENABLE_SHIFT (0U) +/*! STROBE_DLL_CTRL_ENABLE - Strobe DLL control enable */ +#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_ENABLE_SHIFT)) & USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_ENABLE_MASK) + +#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_RESET_MASK (0x2U) +#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_RESET_SHIFT (1U) +/*! STROBE_DLL_CTRL_RESET - Strobe DLL control reset */ +#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_RESET(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_RESET_SHIFT)) & USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_RESET_MASK) + +#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_FORCE_UPD_MASK (0x4U) +#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_FORCE_UPD_SHIFT (2U) +/*! STROBE_DLL_CTRL_SLV_FORCE_UPD - Strobe DLL control slave force updated */ +#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_FORCE_UPD(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_FORCE_UPD_SHIFT)) & USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_FORCE_UPD_MASK) + +#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_DLY_TARGET_MASK (0x78U) +#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_DLY_TARGET_SHIFT (3U) +/*! STROBE_DLL_CTRL_SLV_DLY_TARGET - Strobe DLL Control Slave Delay Target */ +#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_DLY_TARGET(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_DLY_TARGET_SHIFT)) & USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_DLY_TARGET_MASK) + +#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_GATE_UPDATE_MASK (0x80U) +#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_GATE_UPDATE_SHIFT (7U) +/*! STROBE_DLL_CTRL_GATE_UPDATE - Strobe DLL control gate update */ +#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_GATE_UPDATE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_GATE_UPDATE_SHIFT)) & USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_GATE_UPDATE_MASK) + +#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_MASK (0x100U) +#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_SHIFT (8U) +/*! STROBE_DLL_CTRL_SLV_OVERRIDE - Strobe DLL control slave override */ +#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_SHIFT)) & USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_MASK) + +#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_VAL_MASK (0xFE00U) +#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_VAL_SHIFT (9U) +/*! STROBE_DLL_CTRL_SLV_OVERRIDE_VAL - Strobe DLL control slave Override value */ +#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_VAL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_VAL_SHIFT)) & USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_VAL_MASK) + +#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_UPDATE_INT_MASK (0xFF00000U) +#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_UPDATE_INT_SHIFT (20U) +/*! STROBE_DLL_CTRL_SLV_UPDATE_INT - Strobe DLL control slave update interval */ +#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_UPDATE_INT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_UPDATE_INT_SHIFT)) & USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_UPDATE_INT_MASK) + +#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_REF_UPDATE_INT_MASK (0xF0000000U) +#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_REF_UPDATE_INT_SHIFT (28U) +/*! STROBE_DLL_CTRL_REF_UPDATE_INT - Strobe DLL control reference update interval */ +#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_REF_UPDATE_INT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_REF_UPDATE_INT_SHIFT)) & USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_REF_UPDATE_INT_MASK) +/*! @} */ + +/*! @name STROBE_DLL_STATUS - Strobe DLL status */ +/*! @{ */ + +#define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_LOCK_MASK (0x1U) +#define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_LOCK_SHIFT (0U) +/*! STROBE_DLL_STS_SLV_LOCK - Strobe DLL status slave lock */ +#define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_LOCK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_LOCK_SHIFT)) & USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_LOCK_MASK) + +#define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_LOCK_MASK (0x2U) +#define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_LOCK_SHIFT (1U) +/*! STROBE_DLL_STS_REF_LOCK - Strobe DLL status reference lock */ +#define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_LOCK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_LOCK_SHIFT)) & USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_LOCK_MASK) + +#define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_SEL_MASK (0x1FCU) +#define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_SEL_SHIFT (2U) +/*! STROBE_DLL_STS_SLV_SEL - Strobe DLL status slave select */ +#define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_SEL_SHIFT)) & USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_SEL_MASK) + +#define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_SEL_MASK (0xFE00U) +#define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_SEL_SHIFT (9U) +/*! STROBE_DLL_STS_REF_SEL - Strobe DLL status reference select */ +#define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_SEL_SHIFT)) & USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_SEL_MASK) +/*! @} */ + +/*! @name VEND_SPEC - Vendor Specific Register */ +/*! @{ */ + +#define USDHC_VEND_SPEC_VSELECT_MASK (0x2U) +#define USDHC_VEND_SPEC_VSELECT_SHIFT (1U) +/*! VSELECT - Voltage selection + * 0b0..Change the voltage to high voltage range, around 3.0 V + * 0b1..Change the voltage to low voltage range , around 1.8 V + */ +#define USDHC_VEND_SPEC_VSELECT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_VSELECT_SHIFT)) & USDHC_VEND_SPEC_VSELECT_MASK) + +#define USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN_MASK (0x8U) +#define USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN_SHIFT (3U) +/*! AC12_WR_CHKBUSY_EN - Check busy enable + * 0b0..Do not check busy after auto CMD12 for write data packet + * 0b1..Check busy after auto CMD12 for write data packet + */ +#define USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN_SHIFT)) & USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN_MASK) + +#define USDHC_VEND_SPEC_FRC_SDCLK_ON_MASK (0x100U) +#define USDHC_VEND_SPEC_FRC_SDCLK_ON_SHIFT (8U) +/*! FRC_SDCLK_ON - Force CLK + * 0b0..CLK active or inactive is fully controlled by the hardware. + * 0b1..Force CLK active + */ +#define USDHC_VEND_SPEC_FRC_SDCLK_ON(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_FRC_SDCLK_ON_SHIFT)) & USDHC_VEND_SPEC_FRC_SDCLK_ON_MASK) + +#define USDHC_VEND_SPEC_CRC_CHK_DIS_MASK (0x8000U) +#define USDHC_VEND_SPEC_CRC_CHK_DIS_SHIFT (15U) +/*! CRC_CHK_DIS - CRC Check Disable + * 0b0..Check CRC16 for every read data packet and check CRC fields for every write data packet + * 0b1..Ignore CRC16 check for every read data packet and ignore CRC fields check for every write data packet + */ +#define USDHC_VEND_SPEC_CRC_CHK_DIS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_CRC_CHK_DIS_SHIFT)) & USDHC_VEND_SPEC_CRC_CHK_DIS_MASK) + +#define USDHC_VEND_SPEC_CMD_BYTE_EN_MASK (0x80000000U) +#define USDHC_VEND_SPEC_CMD_BYTE_EN_SHIFT (31U) +/*! CMD_BYTE_EN - Register byte access for CMD_XFR_TYP + * 0b0..Disable. MIX_CTRL[7:0] is read/write and CMD_XFR_TYP[7:0] is read-only. + * 0b1..Enable. MIX_CTRL[7:0] is read-only and CMD_XFR_TYP[7:0] is read/write. + */ +#define USDHC_VEND_SPEC_CMD_BYTE_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_CMD_BYTE_EN_SHIFT)) & USDHC_VEND_SPEC_CMD_BYTE_EN_MASK) +/*! @} */ + +/*! @name MMC_BOOT - eMMC Boot */ +/*! @{ */ + +#define USDHC_MMC_BOOT_DTOCV_ACK_MASK (0xFU) +#define USDHC_MMC_BOOT_DTOCV_ACK_SHIFT (0U) +/*! DTOCV_ACK - DTOCV_ACK + * 0b0000..SDCLK x 2^32 + * 0b0001..SDCLK x 2^33 + * 0b0010..SDCLK x 2^18 + * 0b0011..SDCLK x 2^19 + * 0b0100..SDCLK x 2^20 + * 0b0101..SDCLK x 2^21 + * 0b0110..SDCLK x 2^22 + * 0b0111..SDCLK x 2^23 + * 0b1110..SDCLK x 2^30 + * 0b1111..SDCLK x 2^31 + */ +#define USDHC_MMC_BOOT_DTOCV_ACK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_DTOCV_ACK_SHIFT)) & USDHC_MMC_BOOT_DTOCV_ACK_MASK) + +#define USDHC_MMC_BOOT_BOOT_ACK_MASK (0x10U) +#define USDHC_MMC_BOOT_BOOT_ACK_SHIFT (4U) +/*! BOOT_ACK - BOOT ACK + * 0b0..No ack + * 0b1..Ack + */ +#define USDHC_MMC_BOOT_BOOT_ACK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_BOOT_ACK_SHIFT)) & USDHC_MMC_BOOT_BOOT_ACK_MASK) + +#define USDHC_MMC_BOOT_BOOT_MODE_MASK (0x20U) +#define USDHC_MMC_BOOT_BOOT_MODE_SHIFT (5U) +/*! BOOT_MODE - Boot mode + * 0b0..Normal boot + * 0b1..Alternative boot + */ +#define USDHC_MMC_BOOT_BOOT_MODE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_BOOT_MODE_SHIFT)) & USDHC_MMC_BOOT_BOOT_MODE_MASK) + +#define USDHC_MMC_BOOT_BOOT_EN_MASK (0x40U) +#define USDHC_MMC_BOOT_BOOT_EN_SHIFT (6U) +/*! BOOT_EN - Boot enable + * 0b0..Fast boot disable + * 0b1..Fast boot enable + */ +#define USDHC_MMC_BOOT_BOOT_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_BOOT_EN_SHIFT)) & USDHC_MMC_BOOT_BOOT_EN_MASK) + +#define USDHC_MMC_BOOT_AUTO_SABG_EN_MASK (0x80U) +#define USDHC_MMC_BOOT_AUTO_SABG_EN_SHIFT (7U) +/*! AUTO_SABG_EN - Auto stop at block gap */ +#define USDHC_MMC_BOOT_AUTO_SABG_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_AUTO_SABG_EN_SHIFT)) & USDHC_MMC_BOOT_AUTO_SABG_EN_MASK) + +#define USDHC_MMC_BOOT_DISABLE_TIME_OUT_MASK (0x100U) +#define USDHC_MMC_BOOT_DISABLE_TIME_OUT_SHIFT (8U) +/*! DISABLE_TIME_OUT - Time out + * 0b0..Enable time out + * 0b1..Disable time out + */ +#define USDHC_MMC_BOOT_DISABLE_TIME_OUT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_DISABLE_TIME_OUT_SHIFT)) & USDHC_MMC_BOOT_DISABLE_TIME_OUT_MASK) + +#define USDHC_MMC_BOOT_BOOT_BLK_CNT_MASK (0xFFFF0000U) +#define USDHC_MMC_BOOT_BOOT_BLK_CNT_SHIFT (16U) +/*! BOOT_BLK_CNT - Stop At Block Gap value of automatic mode */ +#define USDHC_MMC_BOOT_BOOT_BLK_CNT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_BOOT_BLK_CNT_SHIFT)) & USDHC_MMC_BOOT_BOOT_BLK_CNT_MASK) +/*! @} */ + +/*! @name VEND_SPEC2 - Vendor Specific 2 Register */ +/*! @{ */ + +#define USDHC_VEND_SPEC2_CARD_INT_D3_TEST_MASK (0x8U) +#define USDHC_VEND_SPEC2_CARD_INT_D3_TEST_SHIFT (3U) +/*! CARD_INT_D3_TEST - Card interrupt detection test + * 0b0..Check the card interrupt only when DATA3 is high. + * 0b1..Check the card interrupt by ignoring the status of DATA3. + */ +#define USDHC_VEND_SPEC2_CARD_INT_D3_TEST(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_CARD_INT_D3_TEST_SHIFT)) & USDHC_VEND_SPEC2_CARD_INT_D3_TEST_MASK) + +#define USDHC_VEND_SPEC2_TUNING_BIT_EN_MASK (0x30U) +#define USDHC_VEND_SPEC2_TUNING_BIT_EN_SHIFT (4U) +/*! TUNING_BIT_EN - Tuning bit enable + * 0b00..Enable Tuning circuit for DATA[3:0] + * 0b01..Enable Tuning circuit for DATA[7:0] + * 0b10..Enable Tuning circuit for DATA[0] + * 0b11..Invalid + */ +#define USDHC_VEND_SPEC2_TUNING_BIT_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_TUNING_BIT_EN_SHIFT)) & USDHC_VEND_SPEC2_TUNING_BIT_EN_MASK) + +#define USDHC_VEND_SPEC2_TUNING_CMD_EN_MASK (0x40U) +#define USDHC_VEND_SPEC2_TUNING_CMD_EN_SHIFT (6U) +/*! TUNING_CMD_EN - Tuning command enable + * 0b0..Auto tuning circuit does not check the CMD line. + * 0b1..Auto tuning circuit checks the CMD line. + */ +#define USDHC_VEND_SPEC2_TUNING_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_TUNING_CMD_EN_SHIFT)) & USDHC_VEND_SPEC2_TUNING_CMD_EN_MASK) + +#define USDHC_VEND_SPEC2_HS400_WR_CLK_STOP_EN_MASK (0x400U) +#define USDHC_VEND_SPEC2_HS400_WR_CLK_STOP_EN_SHIFT (10U) +/*! HS400_WR_CLK_STOP_EN - HS400 write clock stop enable */ +#define USDHC_VEND_SPEC2_HS400_WR_CLK_STOP_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_HS400_WR_CLK_STOP_EN_SHIFT)) & USDHC_VEND_SPEC2_HS400_WR_CLK_STOP_EN_MASK) + +#define USDHC_VEND_SPEC2_HS400_RD_CLK_STOP_EN_MASK (0x800U) +#define USDHC_VEND_SPEC2_HS400_RD_CLK_STOP_EN_SHIFT (11U) +/*! HS400_RD_CLK_STOP_EN - HS400 read clock stop enable */ +#define USDHC_VEND_SPEC2_HS400_RD_CLK_STOP_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_HS400_RD_CLK_STOP_EN_SHIFT)) & USDHC_VEND_SPEC2_HS400_RD_CLK_STOP_EN_MASK) + +#define USDHC_VEND_SPEC2_ACMD23_ARGU2_EN_MASK (0x1000U) +#define USDHC_VEND_SPEC2_ACMD23_ARGU2_EN_SHIFT (12U) +/*! ACMD23_ARGU2_EN - Argument2 register enable for ACMD23 + * 0b0..Disable + * 0b1..Argument2 register enable for ACMD23 sharing with SDMA system address register. Default is enabled. + */ +#define USDHC_VEND_SPEC2_ACMD23_ARGU2_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_ACMD23_ARGU2_EN_SHIFT)) & USDHC_VEND_SPEC2_ACMD23_ARGU2_EN_MASK) + +#define USDHC_VEND_SPEC2_EN_32K_CLK_MASK (0x8000U) +#define USDHC_VEND_SPEC2_EN_32K_CLK_SHIFT (15U) +/*! EN_32K_CLK - Select the clock source for host card detection. + * 0b0..Use the peripheral clock (ipg_clk) for card detection. + * 0b1..Use the low power clock (ipg_clk_lp) for card detection. + */ +#define USDHC_VEND_SPEC2_EN_32K_CLK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_EN_32K_CLK_SHIFT)) & USDHC_VEND_SPEC2_EN_32K_CLK_MASK) + +#define USDHC_VEND_SPEC2_FBCLK_TAP_SEL_MASK (0xFFFF0000U) +#define USDHC_VEND_SPEC2_FBCLK_TAP_SEL_SHIFT (16U) +/*! FBCLK_TAP_SEL - Enable extra delay on internal feedback clock */ +#define USDHC_VEND_SPEC2_FBCLK_TAP_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_FBCLK_TAP_SEL_SHIFT)) & USDHC_VEND_SPEC2_FBCLK_TAP_SEL_MASK) +/*! @} */ + +/*! @name TUNING_CTRL - Tuning Control */ +/*! @{ */ + +#define USDHC_TUNING_CTRL_TUNING_START_TAP_MASK (0x7FU) +#define USDHC_TUNING_CTRL_TUNING_START_TAP_SHIFT (0U) +/*! TUNING_START_TAP - Tuning start */ +#define USDHC_TUNING_CTRL_TUNING_START_TAP(x) (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_TUNING_START_TAP_SHIFT)) & USDHC_TUNING_CTRL_TUNING_START_TAP_MASK) + +#define USDHC_TUNING_CTRL_DIS_CMD_CHK_FOR_STD_TUNING_MASK (0x80U) +#define USDHC_TUNING_CTRL_DIS_CMD_CHK_FOR_STD_TUNING_SHIFT (7U) +/*! DIS_CMD_CHK_FOR_STD_TUNING - Disable command check for standard tuning */ +#define USDHC_TUNING_CTRL_DIS_CMD_CHK_FOR_STD_TUNING(x) (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_DIS_CMD_CHK_FOR_STD_TUNING_SHIFT)) & USDHC_TUNING_CTRL_DIS_CMD_CHK_FOR_STD_TUNING_MASK) + +#define USDHC_TUNING_CTRL_TUNING_COUNTER_MASK (0xFF00U) +#define USDHC_TUNING_CTRL_TUNING_COUNTER_SHIFT (8U) +/*! TUNING_COUNTER - Tuning counter */ +#define USDHC_TUNING_CTRL_TUNING_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_TUNING_COUNTER_SHIFT)) & USDHC_TUNING_CTRL_TUNING_COUNTER_MASK) + +#define USDHC_TUNING_CTRL_TUNING_STEP_MASK (0x70000U) +#define USDHC_TUNING_CTRL_TUNING_STEP_SHIFT (16U) +/*! TUNING_STEP - TUNING_STEP */ +#define USDHC_TUNING_CTRL_TUNING_STEP(x) (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_TUNING_STEP_SHIFT)) & USDHC_TUNING_CTRL_TUNING_STEP_MASK) + +#define USDHC_TUNING_CTRL_TUNING_WINDOW_MASK (0x700000U) +#define USDHC_TUNING_CTRL_TUNING_WINDOW_SHIFT (20U) +/*! TUNING_WINDOW - Data window */ +#define USDHC_TUNING_CTRL_TUNING_WINDOW(x) (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_TUNING_WINDOW_SHIFT)) & USDHC_TUNING_CTRL_TUNING_WINDOW_MASK) + +#define USDHC_TUNING_CTRL_STD_TUNING_EN_MASK (0x1000000U) +#define USDHC_TUNING_CTRL_STD_TUNING_EN_SHIFT (24U) +/*! STD_TUNING_EN - Standard tuning circuit and procedure enable */ +#define USDHC_TUNING_CTRL_STD_TUNING_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_STD_TUNING_EN_SHIFT)) & USDHC_TUNING_CTRL_STD_TUNING_EN_MASK) +/*! @} */ + +/*! @name CQVER - Command Queuing Version */ +/*! @{ */ + +#define USDHC_CQVER_VERSION_SUFFIX_MASK (0xFU) +#define USDHC_CQVER_VERSION_SUFFIX_SHIFT (0U) +/*! VERSION_SUFFIX - eMMC version suffix */ +#define USDHC_CQVER_VERSION_SUFFIX(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CQVER_VERSION_SUFFIX_SHIFT)) & USDHC_CQVER_VERSION_SUFFIX_MASK) + +#define USDHC_CQVER_MINOR_VN_MASK (0xF0U) +#define USDHC_CQVER_MINOR_VN_SHIFT (4U) +/*! MINOR_VN - eMMC minor version number */ +#define USDHC_CQVER_MINOR_VN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CQVER_MINOR_VN_SHIFT)) & USDHC_CQVER_MINOR_VN_MASK) + +#define USDHC_CQVER_MAJOR_VN_MASK (0xF00U) +#define USDHC_CQVER_MAJOR_VN_SHIFT (8U) +/*! MAJOR_VN - eMMC major version number */ +#define USDHC_CQVER_MAJOR_VN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CQVER_MAJOR_VN_SHIFT)) & USDHC_CQVER_MAJOR_VN_MASK) +/*! @} */ + +/*! @name CQCAP - Command Queuing Capabilities */ +/*! @{ */ + +#define USDHC_CQCAP_ITCFVAL_MASK (0x3FFU) +#define USDHC_CQCAP_ITCFVAL_SHIFT (0U) +/*! ITCFVAL - Internal timer clock frequency value */ +#define USDHC_CQCAP_ITCFVAL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CQCAP_ITCFVAL_SHIFT)) & USDHC_CQCAP_ITCFVAL_MASK) + +#define USDHC_CQCAP_ITCFMUL_MASK (0xF000U) +#define USDHC_CQCAP_ITCFMUL_SHIFT (12U) +/*! ITCFMUL - Internal timer clock frequency multiplier + * 0b0001..0.001 MHz + * 0b0010..0.01 MHz + * 0b0011..0.1 MHz + * 0b0100..1 MHz + * 0b0101..10 MHz + * 0b0110-0b1001..Reserved + */ +#define USDHC_CQCAP_ITCFMUL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CQCAP_ITCFMUL_SHIFT)) & USDHC_CQCAP_ITCFMUL_MASK) +/*! @} */ + +/*! @name CQCFG - Command Queuing Configuration */ +/*! @{ */ + +#define USDHC_CQCFG_CQUE_MASK (0x1U) +#define USDHC_CQCFG_CQUE_SHIFT (0U) +/*! CQUE - Command queuing enable */ +#define USDHC_CQCFG_CQUE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CQCFG_CQUE_SHIFT)) & USDHC_CQCFG_CQUE_MASK) + +#define USDHC_CQCFG_TDS_MASK (0x100U) +#define USDHC_CQCFG_TDS_SHIFT (8U) +/*! TDS - Task descriptor size + * 0b0..Task descriptor size is 64 bits + * 0b1..Task descriptor size is 128 bits + */ +#define USDHC_CQCFG_TDS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CQCFG_TDS_SHIFT)) & USDHC_CQCFG_TDS_MASK) + +#define USDHC_CQCFG_DCMDE_MASK (0x1000U) +#define USDHC_CQCFG_DCMDE_SHIFT (12U) +/*! DCMDE - Direct command (DCMD) enable + * 0b0..Task descriptor in slot #31 is a Data Transfer Task Descriptor + * 0b1..Task descriptor in slot #31 is a DCMD Task Descriptor + */ +#define USDHC_CQCFG_DCMDE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CQCFG_DCMDE_SHIFT)) & USDHC_CQCFG_DCMDE_MASK) +/*! @} */ + +/*! @name CQCTL - Command Queuing Control */ +/*! @{ */ + +#define USDHC_CQCTL_HALT_MASK (0x1U) +#define USDHC_CQCTL_HALT_SHIFT (0U) +/*! HALT - Halt */ +#define USDHC_CQCTL_HALT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CQCTL_HALT_SHIFT)) & USDHC_CQCTL_HALT_MASK) + +#define USDHC_CQCTL_CLEAR_MASK (0x100U) +#define USDHC_CQCTL_CLEAR_SHIFT (8U) +/*! CLEAR - Clear all tasks */ +#define USDHC_CQCTL_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CQCTL_CLEAR_SHIFT)) & USDHC_CQCTL_CLEAR_MASK) +/*! @} */ + +/*! @name CQIS - Command Queuing Interrupt Status */ +/*! @{ */ + +#define USDHC_CQIS_HAC_MASK (0x1U) +#define USDHC_CQIS_HAC_SHIFT (0U) +/*! HAC - Halt complete interrupt */ +#define USDHC_CQIS_HAC(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CQIS_HAC_SHIFT)) & USDHC_CQIS_HAC_MASK) + +#define USDHC_CQIS_TCC_MASK (0x2U) +#define USDHC_CQIS_TCC_SHIFT (1U) +/*! TCC - Task complete interrupt */ +#define USDHC_CQIS_TCC(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CQIS_TCC_SHIFT)) & USDHC_CQIS_TCC_MASK) + +#define USDHC_CQIS_RED_MASK (0x4U) +#define USDHC_CQIS_RED_SHIFT (2U) +/*! RED - Response error detected interrupt */ +#define USDHC_CQIS_RED(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CQIS_RED_SHIFT)) & USDHC_CQIS_RED_MASK) + +#define USDHC_CQIS_TCL_MASK (0x8U) +#define USDHC_CQIS_TCL_SHIFT (3U) +/*! TCL - Task cleared */ +#define USDHC_CQIS_TCL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CQIS_TCL_SHIFT)) & USDHC_CQIS_TCL_MASK) +/*! @} */ + +/*! @name CQISTE - Command Queuing Interrupt Status Enable */ +/*! @{ */ + +#define USDHC_CQISTE_HAC_STE_MASK (0x1U) +#define USDHC_CQISTE_HAC_STE_SHIFT (0U) +/*! HAC_STE - Halt complete status enable + * 0b0..CQIS[HAC] is disabled + * 0b1..CQIS[HAC] is set when its interrupt condition is active + */ +#define USDHC_CQISTE_HAC_STE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CQISTE_HAC_STE_SHIFT)) & USDHC_CQISTE_HAC_STE_MASK) + +#define USDHC_CQISTE_TCC_STE_MASK (0x2U) +#define USDHC_CQISTE_TCC_STE_SHIFT (1U) +/*! TCC_STE - Task complete status enable + * 0b0..CQIS[TCC] is disabled + * 0b1..CQIS[TCC] is set when its interrupt condition is active + */ +#define USDHC_CQISTE_TCC_STE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CQISTE_TCC_STE_SHIFT)) & USDHC_CQISTE_TCC_STE_MASK) + +#define USDHC_CQISTE_RED_STE_MASK (0x4U) +#define USDHC_CQISTE_RED_STE_SHIFT (2U) +/*! RED_STE - Response error detected status enable + * 0b0..CQIS[RED]is disabled + * 0b1..CQIS[RED] is set when its interrupt condition is active + */ +#define USDHC_CQISTE_RED_STE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CQISTE_RED_STE_SHIFT)) & USDHC_CQISTE_RED_STE_MASK) + +#define USDHC_CQISTE_TCL_STE_MASK (0x8U) +#define USDHC_CQISTE_TCL_STE_SHIFT (3U) +/*! TCL_STE - Task cleared status enable + * 0b0..CQIS[TCL] is disabled + * 0b1..CQIS[TCL] is set when its interrupt condition is active + */ +#define USDHC_CQISTE_TCL_STE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CQISTE_TCL_STE_SHIFT)) & USDHC_CQISTE_TCL_STE_MASK) +/*! @} */ + +/*! @name CQISGE - Command Queuing Interrupt Signal Enable */ +/*! @{ */ + +#define USDHC_CQISGE_HAC_SGE_MASK (0x1U) +#define USDHC_CQISGE_HAC_SGE_SHIFT (0U) +/*! HAC_SGE - Halt complete signal enable */ +#define USDHC_CQISGE_HAC_SGE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CQISGE_HAC_SGE_SHIFT)) & USDHC_CQISGE_HAC_SGE_MASK) + +#define USDHC_CQISGE_TCC_SGE_MASK (0x2U) +#define USDHC_CQISGE_TCC_SGE_SHIFT (1U) +/*! TCC_SGE - Task complete signal enable */ +#define USDHC_CQISGE_TCC_SGE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CQISGE_TCC_SGE_SHIFT)) & USDHC_CQISGE_TCC_SGE_MASK) + +#define USDHC_CQISGE_RED_SGE_MASK (0x4U) +#define USDHC_CQISGE_RED_SGE_SHIFT (2U) +/*! RED_SGE - Response error detected signal enable */ +#define USDHC_CQISGE_RED_SGE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CQISGE_RED_SGE_SHIFT)) & USDHC_CQISGE_RED_SGE_MASK) + +#define USDHC_CQISGE_TCL_SGE_MASK (0x8U) +#define USDHC_CQISGE_TCL_SGE_SHIFT (3U) +/*! TCL_SGE - Task cleared signal enable */ +#define USDHC_CQISGE_TCL_SGE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CQISGE_TCL_SGE_SHIFT)) & USDHC_CQISGE_TCL_SGE_MASK) +/*! @} */ + +/*! @name CQIC - Command Queuing Interrupt Coalescing */ +/*! @{ */ + +#define USDHC_CQIC_ICTOVAL_MASK (0x7FU) +#define USDHC_CQIC_ICTOVAL_SHIFT (0U) +/*! ICTOVAL - Interrupt coalescing timeout value */ +#define USDHC_CQIC_ICTOVAL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CQIC_ICTOVAL_SHIFT)) & USDHC_CQIC_ICTOVAL_MASK) + +#define USDHC_CQIC_ICTOVALWEN_MASK (0x80U) +#define USDHC_CQIC_ICTOVALWEN_SHIFT (7U) +/*! ICTOVALWEN - Interrupt coalescing timeout value write enable */ +#define USDHC_CQIC_ICTOVALWEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CQIC_ICTOVALWEN_SHIFT)) & USDHC_CQIC_ICTOVALWEN_MASK) + +#define USDHC_CQIC_ICCTH_MASK (0x1F00U) +#define USDHC_CQIC_ICCTH_SHIFT (8U) +/*! ICCTH - Interrupt coalescing counter threshold */ +#define USDHC_CQIC_ICCTH(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CQIC_ICCTH_SHIFT)) & USDHC_CQIC_ICCTH_MASK) + +#define USDHC_CQIC_ICCTHWEN_MASK (0x8000U) +#define USDHC_CQIC_ICCTHWEN_SHIFT (15U) +/*! ICCTHWEN - Interrupt coalescing counter threshold write enable */ +#define USDHC_CQIC_ICCTHWEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CQIC_ICCTHWEN_SHIFT)) & USDHC_CQIC_ICCTHWEN_MASK) + +#define USDHC_CQIC_ICCTR_MASK (0x10000U) +#define USDHC_CQIC_ICCTR_SHIFT (16U) +/*! ICCTR - Counter and timer reset */ +#define USDHC_CQIC_ICCTR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CQIC_ICCTR_SHIFT)) & USDHC_CQIC_ICCTR_MASK) + +#define USDHC_CQIC_ICSB_MASK (0x100000U) +#define USDHC_CQIC_ICSB_SHIFT (20U) +/*! ICSB - Interrupt coalescing status + * 0b0..No task completions have occurred since last counter reset (IC counter =0) + * 0b1..At least one task completion has been counted (IC counter >0) + */ +#define USDHC_CQIC_ICSB(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CQIC_ICSB_SHIFT)) & USDHC_CQIC_ICSB_MASK) + +#define USDHC_CQIC_ICENDIS_MASK (0x80000000U) +#define USDHC_CQIC_ICENDIS_SHIFT (31U) +/*! ICENDIS - Interrupt coalescing enable/disable */ +#define USDHC_CQIC_ICENDIS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CQIC_ICENDIS_SHIFT)) & USDHC_CQIC_ICENDIS_MASK) +/*! @} */ + +/*! @name CQTDLBA - Command Queuing Task Descriptor List Base Address */ +/*! @{ */ + +#define USDHC_CQTDLBA_TDLBA_MASK (0xFFFFFFFFU) +#define USDHC_CQTDLBA_TDLBA_SHIFT (0U) +/*! TDLBA - Task descriptor list base address */ +#define USDHC_CQTDLBA_TDLBA(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CQTDLBA_TDLBA_SHIFT)) & USDHC_CQTDLBA_TDLBA_MASK) +/*! @} */ + +/*! @name CQTDLBAU - Command Queuing Task Descriptor List Base Address Upper 32 Bits */ +/*! @{ */ + +#define USDHC_CQTDLBAU_TDLBAU_MASK (0xFFFFFFFFU) +#define USDHC_CQTDLBAU_TDLBAU_SHIFT (0U) +/*! TDLBAU - Task descriptor list base address */ +#define USDHC_CQTDLBAU_TDLBAU(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CQTDLBAU_TDLBAU_SHIFT)) & USDHC_CQTDLBAU_TDLBAU_MASK) +/*! @} */ + +/*! @name CQTDBR - Command Queuing Task Doorbell */ +/*! @{ */ + +#define USDHC_CQTDBR_TDBR_MASK (0xFFFFFFFFU) +#define USDHC_CQTDBR_TDBR_SHIFT (0U) +/*! TDBR - Task doorbell */ +#define USDHC_CQTDBR_TDBR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CQTDBR_TDBR_SHIFT)) & USDHC_CQTDBR_TDBR_MASK) +/*! @} */ + +/*! @name CQTCN - Command Queuing Task Completion Notification */ +/*! @{ */ + +#define USDHC_CQTCN_TCN_MASK (0xFFFFFFFFU) +#define USDHC_CQTCN_TCN_SHIFT (0U) +/*! TCN - Task complete notification */ +#define USDHC_CQTCN_TCN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CQTCN_TCN_SHIFT)) & USDHC_CQTCN_TCN_MASK) +/*! @} */ + +/*! @name CQDQS - Command Queuing Device Queue Status */ +/*! @{ */ + +#define USDHC_CQDQS_DQS_MASK (0xFFFFFFFFU) +#define USDHC_CQDQS_DQS_SHIFT (0U) +/*! DQS - Device queue status */ +#define USDHC_CQDQS_DQS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CQDQS_DQS_SHIFT)) & USDHC_CQDQS_DQS_MASK) +/*! @} */ + +/*! @name CQDPT - Command Queuing Device Pending Tasks */ +/*! @{ */ + +#define USDHC_CQDPT_DPT_MASK (0xFFFFFFFFU) +#define USDHC_CQDPT_DPT_SHIFT (0U) +/*! DPT - Device pending tasks */ +#define USDHC_CQDPT_DPT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CQDPT_DPT_SHIFT)) & USDHC_CQDPT_DPT_MASK) +/*! @} */ + +/*! @name CQTCLR - Command Queuing Task Clear */ +/*! @{ */ + +#define USDHC_CQTCLR_TCLR_MASK (0xFFFFFFFFU) +#define USDHC_CQTCLR_TCLR_SHIFT (0U) +/*! TCLR - Task clear */ +#define USDHC_CQTCLR_TCLR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CQTCLR_TCLR_SHIFT)) & USDHC_CQTCLR_TCLR_MASK) +/*! @} */ + +/*! @name CQSSC1 - Command Queuing Send Status Configuration 1 */ +/*! @{ */ + +#define USDHC_CQSSC1_CIT_MASK (0xFFFFU) +#define USDHC_CQSSC1_CIT_SHIFT (0U) +/*! CIT - Send status command idle timer */ +#define USDHC_CQSSC1_CIT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CQSSC1_CIT_SHIFT)) & USDHC_CQSSC1_CIT_MASK) + +#define USDHC_CQSSC1_CBC_MASK (0xF0000U) +#define USDHC_CQSSC1_CBC_SHIFT (16U) +/*! CBC - Send status command block counter */ +#define USDHC_CQSSC1_CBC(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CQSSC1_CBC_SHIFT)) & USDHC_CQSSC1_CBC_MASK) +/*! @} */ + +/*! @name CQSSC2 - Command Queuing Send Status Configuration 2 */ +/*! @{ */ + +#define USDHC_CQSSC2_SSC2_MASK (0xFFFFU) +#define USDHC_CQSSC2_SSC2_SHIFT (0U) +/*! SSC2 - Send queue status RCA */ +#define USDHC_CQSSC2_SSC2(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CQSSC2_SSC2_SHIFT)) & USDHC_CQSSC2_SSC2_MASK) +/*! @} */ + +/*! @name CQCRDCT - Command Queuing Command Response for Direct-Command Task */ +/*! @{ */ + +#define USDHC_CQCRDCT_CRDCT_MASK (0xFFFFFFFFU) +#define USDHC_CQCRDCT_CRDCT_SHIFT (0U) +/*! CRDCT - Direct command last response */ +#define USDHC_CQCRDCT_CRDCT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CQCRDCT_CRDCT_SHIFT)) & USDHC_CQCRDCT_CRDCT_MASK) +/*! @} */ + +/*! @name CQRMEM - Command Queuing Response Mode Error Mask */ +/*! @{ */ + +#define USDHC_CQRMEM_RMEM_MASK (0xFFFFFFFFU) +#define USDHC_CQRMEM_RMEM_SHIFT (0U) +/*! RMEM - Response mode error mask + * 0b00000000000000000000000000000000..When a R1/R1b response is received, bit i in the device status is ignored + * 0b00000000000000000000000000000001..When a R1/R1b response is received, with bit i in the device status set, a RED interrupt is generated + */ +#define USDHC_CQRMEM_RMEM(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CQRMEM_RMEM_SHIFT)) & USDHC_CQRMEM_RMEM_MASK) +/*! @} */ + +/*! @name CQTERRI - Command Queuing Task Error Information */ +/*! @{ */ + +#define USDHC_CQTERRI_RMECI_MASK (0x3FU) +#define USDHC_CQTERRI_RMECI_SHIFT (0U) +/*! RMECI - Response mode error command index */ +#define USDHC_CQTERRI_RMECI(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CQTERRI_RMECI_SHIFT)) & USDHC_CQTERRI_RMECI_MASK) + +#define USDHC_CQTERRI_RMETID_MASK (0x1F00U) +#define USDHC_CQTERRI_RMETID_SHIFT (8U) +/*! RMETID - Response mode error task ID */ +#define USDHC_CQTERRI_RMETID(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CQTERRI_RMETID_SHIFT)) & USDHC_CQTERRI_RMETID_MASK) + +#define USDHC_CQTERRI_RMEFV_MASK (0x8000U) +#define USDHC_CQTERRI_RMEFV_SHIFT (15U) +/*! RMEFV - Response mode error fields valid */ +#define USDHC_CQTERRI_RMEFV(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CQTERRI_RMEFV_SHIFT)) & USDHC_CQTERRI_RMEFV_MASK) + +#define USDHC_CQTERRI_DTECI_MASK (0x3F0000U) +#define USDHC_CQTERRI_DTECI_SHIFT (16U) +/*! DTECI - Data transfer error command index */ +#define USDHC_CQTERRI_DTECI(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CQTERRI_DTECI_SHIFT)) & USDHC_CQTERRI_DTECI_MASK) + +#define USDHC_CQTERRI_DTETID_MASK (0x1F000000U) +#define USDHC_CQTERRI_DTETID_SHIFT (24U) +/*! DTETID - Data transfer error task ID */ +#define USDHC_CQTERRI_DTETID(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CQTERRI_DTETID_SHIFT)) & USDHC_CQTERRI_DTETID_MASK) + +#define USDHC_CQTERRI_DTEFV_MASK (0x80000000U) +#define USDHC_CQTERRI_DTEFV_SHIFT (31U) +/*! DTEFV - Data transfer error fields valid */ +#define USDHC_CQTERRI_DTEFV(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CQTERRI_DTEFV_SHIFT)) & USDHC_CQTERRI_DTEFV_MASK) +/*! @} */ + +/*! @name CQCRI - Command Queuing Command Response Index */ +/*! @{ */ + +#define USDHC_CQCRI_LCMDRI_MASK (0x3FU) +#define USDHC_CQCRI_LCMDRI_SHIFT (0U) +/*! LCMDRI - Last command response index */ +#define USDHC_CQCRI_LCMDRI(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CQCRI_LCMDRI_SHIFT)) & USDHC_CQCRI_LCMDRI_MASK) +/*! @} */ + +/*! @name CQCRA - Command Queuing Command Response Argument */ +/*! @{ */ + +#define USDHC_CQCRA_LCMDRA_MASK (0xFFFFFFFFU) +#define USDHC_CQCRA_LCMDRA_SHIFT (0U) +/*! LCMDRA - Last command response argument */ +#define USDHC_CQCRA_LCMDRA(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CQCRA_LCMDRA_SHIFT)) & USDHC_CQCRA_LCMDRA_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group USDHC_Register_Masks */ + + +/* USDHC - Peripheral instance base addresses */ +/** Peripheral USDHC1 base address */ +#define USDHC1_BASE (0x42850000u) +/** Peripheral USDHC1 base pointer */ +#define USDHC1 ((USDHC_Type *)USDHC1_BASE) +/** Peripheral USDHC2 base address */ +#define USDHC2_BASE (0x42860000u) +/** Peripheral USDHC2 base pointer */ +#define USDHC2 ((USDHC_Type *)USDHC2_BASE) +/** Peripheral USDHC3 base address */ +#define USDHC3_BASE (0x428B0000u) +/** Peripheral USDHC3 base pointer */ +#define USDHC3 ((USDHC_Type *)USDHC3_BASE) +/** Array initializer of USDHC peripheral base addresses */ +#define USDHC_BASE_ADDRS { USDHC1_BASE, USDHC2_BASE, USDHC3_BASE } +/** Array initializer of USDHC peripheral base pointers */ +#define USDHC_BASE_PTRS { USDHC1, USDHC2, USDHC3 } +/** Interrupt vectors for the USDHC peripheral type */ +#define USDHC_IRQS { uSDHC1_IRQn, uSDHC2_IRQn, NotAvail_IRQn } + +/*! + * @} + */ /* end of group USDHC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- WDOG Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup WDOG_Peripheral_Access_Layer WDOG Peripheral Access Layer + * @{ + */ + +/** WDOG - Register Layout Typedef */ +typedef struct { + __IO uint32_t CS; /**< WDOG Control and Status, offset: 0x0 */ + __IO uint32_t CNT; /**< WDOG Counter, offset: 0x4 */ + __IO uint32_t TOVAL; /**< WDOG Timeout Value, offset: 0x8 */ + __IO uint32_t WIN; /**< Watchdog Window, offset: 0xC */ +} WDOG_Type; + +/* ---------------------------------------------------------------------------- + -- WDOG Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup WDOG_Register_Masks WDOG Register Masks + * @{ + */ + +/*! @name CS - WDOG Control and Status */ +/*! @{ */ + +#define WDOG_CS_STOP_MASK (0x1U) +#define WDOG_CS_STOP_SHIFT (0U) +/*! STOP - Stop Enable + * 0b0..Disable + * 0b1..Enable + */ +#define WDOG_CS_STOP(x) (((uint32_t)(((uint32_t)(x)) << WDOG_CS_STOP_SHIFT)) & WDOG_CS_STOP_MASK) + +#define WDOG_CS_WAIT_MASK (0x2U) +#define WDOG_CS_WAIT_SHIFT (1U) +/*! WAIT - Wait Enable + * 0b0..Disable + * 0b1..Enable + */ +#define WDOG_CS_WAIT(x) (((uint32_t)(((uint32_t)(x)) << WDOG_CS_WAIT_SHIFT)) & WDOG_CS_WAIT_MASK) + +#define WDOG_CS_DBG_MASK (0x4U) +#define WDOG_CS_DBG_SHIFT (2U) +/*! DBG - Debug Enable + * 0b0..Disable + * 0b1..Enable + */ +#define WDOG_CS_DBG(x) (((uint32_t)(((uint32_t)(x)) << WDOG_CS_DBG_SHIFT)) & WDOG_CS_DBG_MASK) + +#define WDOG_CS_TST_MASK (0x18U) +#define WDOG_CS_TST_SHIFT (3U) +/*! TST - WDOG Test + * 0b00..Disable WDOG Test mode + * 0b01..Enable WDOG User mode + * 0b10-0b11..Enable WDOG Test mode + */ +#define WDOG_CS_TST(x) (((uint32_t)(((uint32_t)(x)) << WDOG_CS_TST_SHIFT)) & WDOG_CS_TST_MASK) + +#define WDOG_CS_UPDATE_MASK (0x20U) +#define WDOG_CS_UPDATE_SHIFT (5U) +/*! UPDATE - Updates Allowed + * 0b0..Updates not allowed + * 0b1..Updates allowed + */ +#define WDOG_CS_UPDATE(x) (((uint32_t)(((uint32_t)(x)) << WDOG_CS_UPDATE_SHIFT)) & WDOG_CS_UPDATE_MASK) + +#define WDOG_CS_INT_MASK (0x40U) +#define WDOG_CS_INT_SHIFT (6U) +/*! INT - WDOG Interrupt + * 0b0..Disable + * 0b1..Enable + */ +#define WDOG_CS_INT(x) (((uint32_t)(((uint32_t)(x)) << WDOG_CS_INT_SHIFT)) & WDOG_CS_INT_MASK) + +#define WDOG_CS_EN_MASK (0x80U) +#define WDOG_CS_EN_SHIFT (7U) +/*! EN - WDOG Enable + * 0b0..Disable + * 0b1..Enable + */ +#define WDOG_CS_EN(x) (((uint32_t)(((uint32_t)(x)) << WDOG_CS_EN_SHIFT)) & WDOG_CS_EN_MASK) + +#define WDOG_CS_CLK_MASK (0x300U) +#define WDOG_CS_CLK_SHIFT (8U) +/*! CLK - WDOG Clock + * 0b00..IPG + * 0b01..LPO + * 0b10..INT + * 0b11..EXT + */ +#define WDOG_CS_CLK(x) (((uint32_t)(((uint32_t)(x)) << WDOG_CS_CLK_SHIFT)) & WDOG_CS_CLK_MASK) + +#define WDOG_CS_RCS_MASK (0x400U) +#define WDOG_CS_RCS_SHIFT (10U) +/*! RCS - Reconfiguration Success + * 0b0..Unsuccessful + * 0b1..Successful + */ +#define WDOG_CS_RCS(x) (((uint32_t)(((uint32_t)(x)) << WDOG_CS_RCS_SHIFT)) & WDOG_CS_RCS_MASK) + +#define WDOG_CS_ULK_MASK (0x800U) +#define WDOG_CS_ULK_SHIFT (11U) +/*! ULK - Unlock Status + * 0b0..Locked + * 0b1..Unlocked + */ +#define WDOG_CS_ULK(x) (((uint32_t)(((uint32_t)(x)) << WDOG_CS_ULK_SHIFT)) & WDOG_CS_ULK_MASK) + +#define WDOG_CS_PRES_MASK (0x1000U) +#define WDOG_CS_PRES_SHIFT (12U) +/*! PRES - WDOG Prescaler + * 0b0..Disable + * 0b1..Enable + */ +#define WDOG_CS_PRES(x) (((uint32_t)(((uint32_t)(x)) << WDOG_CS_PRES_SHIFT)) & WDOG_CS_PRES_MASK) + +#define WDOG_CS_CMD32EN_MASK (0x2000U) +#define WDOG_CS_CMD32EN_SHIFT (13U) +/*! CMD32EN - Command 32 Enable + * 0b0..Disable + * 0b1..Enable + */ +#define WDOG_CS_CMD32EN(x) (((uint32_t)(((uint32_t)(x)) << WDOG_CS_CMD32EN_SHIFT)) & WDOG_CS_CMD32EN_MASK) + +#define WDOG_CS_FLG_MASK (0x4000U) +#define WDOG_CS_FLG_SHIFT (14U) +/*! FLG - WDOG Interrupt Flag + * 0b0..No interrupt occurred + * 0b1..An interrupt occurred + */ +#define WDOG_CS_FLG(x) (((uint32_t)(((uint32_t)(x)) << WDOG_CS_FLG_SHIFT)) & WDOG_CS_FLG_MASK) + +#define WDOG_CS_WIN_MASK (0x8000U) +#define WDOG_CS_WIN_SHIFT (15U) +/*! WIN - WDOG Window + * 0b0..Disable + * 0b1..Enable + */ +#define WDOG_CS_WIN(x) (((uint32_t)(((uint32_t)(x)) << WDOG_CS_WIN_SHIFT)) & WDOG_CS_WIN_MASK) +/*! @} */ + +/*! @name CNT - WDOG Counter */ +/*! @{ */ + +#define WDOG_CNT_CNTLOW_MASK (0xFFU) +#define WDOG_CNT_CNTLOW_SHIFT (0U) +/*! CNTLOW - Counter Low Byte */ +#define WDOG_CNT_CNTLOW(x) (((uint32_t)(((uint32_t)(x)) << WDOG_CNT_CNTLOW_SHIFT)) & WDOG_CNT_CNTLOW_MASK) + +#define WDOG_CNT_CNTHIGH_MASK (0xFF00U) +#define WDOG_CNT_CNTHIGH_SHIFT (8U) +/*! CNTHIGH - Counter High Byte */ +#define WDOG_CNT_CNTHIGH(x) (((uint32_t)(((uint32_t)(x)) << WDOG_CNT_CNTHIGH_SHIFT)) & WDOG_CNT_CNTHIGH_MASK) +/*! @} */ + +/*! @name TOVAL - WDOG Timeout Value */ +/*! @{ */ + +#define WDOG_TOVAL_TOVALLOW_MASK (0xFFU) +#define WDOG_TOVAL_TOVALLOW_SHIFT (0U) +/*! TOVALLOW - Timeout Value Low */ +#define WDOG_TOVAL_TOVALLOW(x) (((uint32_t)(((uint32_t)(x)) << WDOG_TOVAL_TOVALLOW_SHIFT)) & WDOG_TOVAL_TOVALLOW_MASK) + +#define WDOG_TOVAL_TOVALHIGH_MASK (0xFF00U) +#define WDOG_TOVAL_TOVALHIGH_SHIFT (8U) +/*! TOVALHIGH - Timeout Value High */ +#define WDOG_TOVAL_TOVALHIGH(x) (((uint32_t)(((uint32_t)(x)) << WDOG_TOVAL_TOVALHIGH_SHIFT)) & WDOG_TOVAL_TOVALHIGH_MASK) +/*! @} */ + +/*! @name WIN - Watchdog Window */ +/*! @{ */ + +#define WDOG_WIN_WINLOW_MASK (0xFFU) +#define WDOG_WIN_WINLOW_SHIFT (0U) +/*! WINLOW - Low Byte */ +#define WDOG_WIN_WINLOW(x) (((uint32_t)(((uint32_t)(x)) << WDOG_WIN_WINLOW_SHIFT)) & WDOG_WIN_WINLOW_MASK) + +#define WDOG_WIN_WINHIGH_MASK (0xFF00U) +#define WDOG_WIN_WINHIGH_SHIFT (8U) +/*! WINHIGH - High Byte */ +#define WDOG_WIN_WINHIGH(x) (((uint32_t)(((uint32_t)(x)) << WDOG_WIN_WINHIGH_SHIFT)) & WDOG_WIN_WINHIGH_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group WDOG_Register_Masks */ + + +/* WDOG - Peripheral instance base addresses */ +/** Peripheral WDOG1 base address */ +#define WDOG1_BASE (0x442D0000u) +/** Peripheral WDOG1 base pointer */ +#define WDOG1 ((WDOG_Type *)WDOG1_BASE) +/** Peripheral WDOG2 base address */ +#define WDOG2_BASE (0x442E0000u) +/** Peripheral WDOG2 base pointer */ +#define WDOG2 ((WDOG_Type *)WDOG2_BASE) +/** Peripheral WDOG3 base address */ +#define WDOG3_BASE (0x42490000u) +/** Peripheral WDOG3 base pointer */ +#define WDOG3 ((WDOG_Type *)WDOG3_BASE) +/** Peripheral WDOG4 base address */ +#define WDOG4_BASE (0x424A0000u) +/** Peripheral WDOG4 base pointer */ +#define WDOG4 ((WDOG_Type *)WDOG4_BASE) +/** Peripheral WDOG5 base address */ +#define WDOG5_BASE (0x424B0000u) +/** Peripheral WDOG5 base pointer */ +#define WDOG5 ((WDOG_Type *)WDOG5_BASE) +/** Array initializer of WDOG peripheral base addresses */ +#define WDOG_BASE_ADDRS { WDOG1_BASE, WDOG2_BASE, WDOG3_BASE, WDOG4_BASE, WDOG5_BASE } +/** Array initializer of WDOG peripheral base pointers */ +#define WDOG_BASE_PTRS { WDOG1, WDOG2, WDOG3, WDOG4, WDOG5 } +/** Interrupt vectors for the WDOG peripheral type */ +#define WDOG_IRQS { WDOG1_IRQn, WDOG2_IRQn, WDOG3_IRQn, WDOG4_IRQn, WDOG5_IRQn } +/* Extra definition */ +#define WDOG_UPDATE_KEY (0xD928C520U) +#define WDOG_REFRESH_KEY (0xB480A602U) + + +/*! + * @} + */ /* end of group WDOG_Peripheral_Access_Layer */ + + +/* +** End of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop + #else + #pragma pop + #endif +#elif defined(__GNUC__) + /* leave anonymous unions enabled */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=default +#else + #error Not supported compiler type +#endif + +/*! + * @} + */ /* end of group Peripheral_access_layer */ + + +/* ---------------------------------------------------------------------------- + -- Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK). + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Bit_Field_Generic_Macros Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK). + * @{ + */ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang system_header + #endif +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma system_include +#endif + +/** + * @brief Mask and left-shift a bit field value for use in a register bit range. + * @param field Name of the register bit field. + * @param value Value of the bit field. + * @return Masked and shifted value. + */ +#define NXP_VAL2FLD(field, value) (((value) << (field ## _SHIFT)) & (field ## _MASK)) +/** + * @brief Mask and right-shift a register value to extract a bit field value. + * @param field Name of the register bit field. + * @param value Value of the register. + * @return Masked and shifted bit field value. + */ +#define NXP_FLD2VAL(field, value) (((value) & (field ## _MASK)) >> (field ## _SHIFT)) + +/*! + * @} + */ /* end of group Bit_Field_Generic_Macros */ + + +/* ---------------------------------------------------------------------------- + -- SDK Compatibility + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SDK_Compatibility_Symbols SDK Compatibility + * @{ + */ + +/* No SDK compatibility issues. */ + +/*! + * @} + */ /* end of group SDK_Compatibility_Symbols */ + + +#endif /* MIMX9131_H_ */ + diff --git a/bsp/nxp/imx/imx91/drivers/sdk/devices/MIMX9131/MIMX9131_features.h b/bsp/nxp/imx/imx91/drivers/sdk/devices/MIMX9131/MIMX9131_features.h new file mode 100644 index 00000000000..76ab6eb787e --- /dev/null +++ b/bsp/nxp/imx/imx91/drivers/sdk/devices/MIMX9131/MIMX9131_features.h @@ -0,0 +1,671 @@ +/* +** ################################################################### +** Version: rev. 1.0, 2024-11-15 +** Build: b250112 +** +** Abstract: +** Chip specific module features. +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2024-11-15) +** Initial version. +** +** ################################################################### +*/ + +#ifndef _MIMX9131_FEATURES_H_ +#define _MIMX9131_FEATURES_H_ + +/* SOC module features */ + +/* @brief ADC availability on the SoC. */ +#define FSL_FEATURE_SOC_ADC_COUNT (1) +/* @brief AXBS availability on the SoC. */ +#define FSL_FEATURE_SOC_AXBS_COUNT (1) +/* @brief BBNSM availability on the SoC. */ +#define FSL_FEATURE_SOC_BBNSM_COUNT (1) +/* @brief DDR availability on the SoC. */ +#define FSL_FEATURE_SOC_DDR_COUNT (1) +/* @brief EDMA availability on the SoC. */ +#define FSL_FEATURE_SOC_EDMA_COUNT (4) +/* @brief ENET availability on the SoC. */ +#define FSL_FEATURE_SOC_ENET_COUNT (1) +/* @brief ENET_QOS availability on the SoC. */ +#define FSL_FEATURE_SOC_ENET_QOS_COUNT (1) +/* @brief FLEXCAN availability on the SoC. */ +#define FSL_FEATURE_SOC_FLEXCAN_COUNT (2) +/* @brief FLEXIO availability on the SoC. */ +#define FSL_FEATURE_SOC_FLEXIO_COUNT (2) +/* @brief FLEXSPI availability on the SoC. */ +#define FSL_FEATURE_SOC_FLEXSPI_COUNT (1) +/* @brief I3C availability on the SoC. */ +#define FSL_FEATURE_SOC_I3C_COUNT (2) +/* @brief I2S availability on the SoC. */ +#define FSL_FEATURE_SOC_I2S_COUNT (3) +/* @brief IOMUXC_GPR availability on the SoC. */ +#define FSL_FEATURE_SOC_IOMUXC_GPR_COUNT (1) +/* @brief ISI availability on the SoC. */ +#define FSL_FEATURE_SOC_ISI_COUNT (1) +/* @brief LCDIF availability on the SoC. */ +#define FSL_FEATURE_SOC_LCDIF_COUNT (1) +/* @brief LPI2C availability on the SoC. */ +#define FSL_FEATURE_SOC_LPI2C_COUNT (8) +/* @brief LPIT availability on the SoC. */ +#define FSL_FEATURE_SOC_LPIT_COUNT (2) +/* @brief LPSPI availability on the SoC. */ +#define FSL_FEATURE_SOC_LPSPI_COUNT (8) +/* @brief LPTMR availability on the SoC. */ +#define FSL_FEATURE_SOC_LPTMR_COUNT (2) +/* @brief LPUART availability on the SoC. */ +#define FSL_FEATURE_SOC_LPUART_COUNT (8) +/* @brief MU availability on the SoC. */ +#define FSL_FEATURE_SOC_MU_COUNT (4) +/* @brief PDM availability on the SoC. */ +#define FSL_FEATURE_SOC_PDM_COUNT (1) +/* @brief RGPIO availability on the SoC. */ +#define FSL_FEATURE_SOC_RGPIO_COUNT (4) +/* @brief SEMA42 availability on the SoC. */ +#define FSL_FEATURE_SOC_SEMA42_COUNT (2) +/* @brief SPDIF availability on the SoC. */ +#define FSL_FEATURE_SOC_SPDIF_COUNT (1) +/* @brief TPM availability on the SoC. */ +#define FSL_FEATURE_SOC_TPM_COUNT (6) +/* @brief TRGMUX availability on the SoC. */ +#define FSL_FEATURE_SOC_TRGMUX_COUNT (1) +/* @brief TSTMR availability on the SoC. */ +#define FSL_FEATURE_SOC_TSTMR_COUNT (2) +/* @brief USB availability on the SoC. */ +#define FSL_FEATURE_SOC_USB_COUNT (2) +/* @brief USBNC availability on the SoC. */ +#define FSL_FEATURE_SOC_USBNC_COUNT (2) +/* @brief USDHC availability on the SoC. */ +#define FSL_FEATURE_SOC_USDHC_COUNT (3) +/* @brief WDOG availability on the SoC. */ +#define FSL_FEATURE_SOC_WDOG_COUNT (5) + +/* ADC module features */ + +/* @brief Channel group counts of ADC. */ +#define FSL_FEATURE_ADC_CHANNEL_GROUPS_COUNT (2) +/* @brief Threshold counts of ADC. */ +#define FSL_FEATURE_ADC_THRESHOLDS_COUNT (8) +/* @brief Self-test threshold counts of ADC. */ +#define FSL_FEATURE_ADC_SELF_TEST_THRESHOLDS_COUNT (6) + +/* FLEXCAN module features */ + +/* @brief Has more than 64 MBs. */ +#define FSL_FEATURE_FLEXCAN_HAS_MORE_THAN_64_MB (1) +/* @brief Message buffer size */ +#define FSL_FEATURE_FLEXCAN_HAS_MESSAGE_BUFFER_MAX_NUMBERn(x) (96) +/* @brief Has doze mode support (register bit field MCR[DOZE]). */ +#define FSL_FEATURE_FLEXCAN_HAS_DOZE_MODE_SUPPORT (1) +/* @brief Insatnce has doze mode support (register bit field MCR[DOZE]). */ +#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_DOZE_MODE_SUPPORTn(x) (1) +/* @brief Has a glitch filter on the receive pin (register bit field MCR[WAKSRC]). */ +#define FSL_FEATURE_FLEXCAN_HAS_GLITCH_FILTER (1) +/* @brief Has extended interrupt mask and flag register (register IMASK2, IFLAG2). */ +#define FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER (1) +/* @brief Instance has extended bit timing register (register CBT). */ +#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_EXTENDED_TIMING_REGISTERn(x) (1) +/* @brief Has a receive FIFO DMA feature (register bit field MCR[DMA]). */ +#define FSL_FEATURE_FLEXCAN_HAS_RX_FIFO_DMA (1) +/* @brief Instance has a receive FIFO DMA feature (register bit field MCR[DMA]). */ +#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_RX_FIFO_DMAn(x) (1) +/* @brief Remove CAN Engine Clock Source Selection from unsupported part. */ +#define FSL_FEATURE_FLEXCAN_SUPPORT_ENGINE_CLK_SEL_REMOVE (0) +/* @brief Instance remove CAN Engine Clock Source Selection from unsupported part. */ +#define FSL_FEATURE_FLEXCAN_INSTANCE_SUPPORT_ENGINE_CLK_SEL_REMOVEn(x) (0) +/* @brief Is affected by errata with ID 5641 (Module does not transmit a message that is enabled to be transmitted at a specific moment during the arbitration process). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641 (0) +/* @brief Is affected by errata with ID 5829 (FlexCAN: FlexCAN does not transmit a message that is enabled to be transmitted in a specific moment during the arbitration process). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_5829 (0) +/* @brief Is affected by errata with ID 6032 (FlexCAN: A frame with wrong ID or payload is transmitted into the CAN bus when the Message Buffer under transmission is either aborted or deactivated while the CAN bus is in the Bus Idle state). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_6032 (0) +/* @brief Is affected by errata with ID 9595 (FlexCAN: Corrupt frame possible if the Freeze Mode or the Low-Power Mode are entered during a Bus-Off state). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_9595 (0) +/* @brief Has CAN with Flexible Data rate (CAN FD) protocol. */ +#define FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE (1) +/* @brief CAN instance support Flexible Data rate (CAN FD) protocol. */ +#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_FLEXIBLE_DATA_RATEn(x) (1) +/* @brief Has memory error control (register MECR). */ +#define FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL (1) +/* @brief Init memory base 1 */ +#define FSL_FEATURE_FLEXCAN_INIT_MEMORY_BASE_1 (0x80) +/* @brief Init memory size 1 */ +#define FSL_FEATURE_FLEXCAN_INIT_MEMORY_SIZE_1 (0xA60) +/* @brief Init memory base 2 */ +#define FSL_FEATURE_FLEXCAN_INIT_MEMORY_BASE_2 (0xC20) +/* @brief Init memory size 2 */ +#define FSL_FEATURE_FLEXCAN_INIT_MEMORY_SIZE_2 (0x25E0) +/* @brief Has enhanced bit timing register (register EPRS, ENCBT, EDCBT and ETDC). */ +#define FSL_FEATURE_FLEXCAN_HAS_ENHANCED_BIT_TIMING_REG (1) +/* @brief Has Pretended Networking mode support. */ +#define FSL_FEATURE_FLEXCAN_HAS_PN_MODE (0) +/* @brief Has Enhanced Rx FIFO. */ +#define FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO (1) +/* @brief Enhanced Rx FIFO size (Indicates how many CAN FD messages can be stored). */ +#define FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO_SIZE (20) +/* @brief The number of enhanced Rx FIFO filter element registers. */ +#define FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO_FILTER_MAX_NUMBER (128) +/* @brief Does not support Supervisor Mode (bitfield MCR[SUPV]. */ +#define FSL_FEATURE_FLEXCAN_HAS_NO_SUPV_SUPPORT (0) + +/* EDMA module features */ + +/* @brief Number of DMA channels (related to number of registers TCD, DCHPRI, bit fields ERQ[ERQn], EEI[EEIn], INT[INTn], ERR[ERRn], HRS[HRSn] and bit field widths ES[ERRCHN], CEEI[CEEI], SEEI[SEEI], CERQ[CERQ], SERQ[SERQ], CDNE[CDNE], SSRT[SSRT], CERR[CERR], CINT[CINT], TCDn_CITER_ELINKYES[LINKCH], TCDn_CSR[MAJORLINKCH], TCDn_BITER_ELINKYES[LINKCH]). (Valid only for eDMA modules.) */ +#define FSL_FEATURE_EDMA_MODULE_CHANNEL (64) +/* @brief If 8 bytes transfer supported. */ +#define FSL_FEATURE_EDMA_SUPPORT_8_BYTES_TRANSFER (1) +/* @brief Number of channel for each EDMA instance, (only defined for soc with different channel numbers for difference instance) */ +#define FSL_FEATURE_EDMA_INSTANCE_CHANNELn(x) \ + (((x) == DMA4) ? (64) : \ + (((x) == DMA3) ? (31) : (-1))) +/* @brief If 16 bytes transfer supported. */ +#define FSL_FEATURE_EDMA_SUPPORT_16_BYTES_TRANSFER (1) +/* @brief Number of DMA channel groups (register bit fields CR[ERGA], CR[GRPnPRI], ES[GPE], DCHPRIn[GRPPRI]). (Valid only for eDMA modules.) */ +#define FSL_FEATURE_EDMA_CHANNEL_GROUP_COUNT (1) +/* @brief Has register bit fields MP_CSR[GMRC]. */ +#define FSL_FEATURE_EDMA_HAS_GLOBAL_MASTER_ID_REPLICATION (1) +/* @brief If 64 bytes transfer supported. */ +#define FSL_FEATURE_EDMA_SUPPORT_64_BYTES_TRANSFER (1) +/* @brief Has DMA_Error interrupt vector. */ +#define FSL_FEATURE_EDMA_HAS_ERROR_IRQ (1) +/* @brief Has register bit fields CR[CLM]. */ +#define FSL_FEATURE_EDMA_HAS_CONTINUOUS_LINK_MODE (0) +/* @brief If 128 bytes transfer supported. */ +#define FSL_FEATURE_EDMA_SUPPORT_128_BYTES_TRANSFER (1) +/* @brief whether has prot register */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_PROT_REGISTERn(x) (0) +/* @brief NBYTES must be multiple of 8 when using scatter gather. */ +#define FSL_FEATURE_EDMA_HAS_ERRATA_51327 (0) +/* @brief If 128 bytes transfer supported. */ +#define FSL_FEATURE_EDMA_INSTANCE_SUPPORT_128_BYTES_TRANSFERn(x) (1) +/* @brief whether has MP channel mux */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_MP_CHANNEL_MUXn(x) (0) +/* @brief NBYTES must be multiple of 8 when using scatter gather. */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_ERRATA_51327n(x) (0) +/* @brief Has register CH_CSR. */ +#define FSL_FEATURE_EDMA_HAS_CHANNEL_CONFIG (1) +/* @brief If channel clock controlled independently */ +#define FSL_FEATURE_EDMA_CHANNEL_HAS_OWN_CLOCK_GATE (1) +/* @brief Instance has channel mux */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_CHANNEL_MUXn(x) \ + (((x) == EDMA4_2__TCD) ? (1) : \ + (((x) == EDMA3_1__TCD) ? (0) : (-1))) +/* @brief eDMA3 has channel mux */ +#define FSL_FEATURE_EDMA_HAS_CHANNEL_MUX (0) +/* @brief Has register CH_SBR. */ +#define FSL_FEATURE_EDMA_HAS_SBR (1) +/* @brief Has no register bit fields MP_CSR[EBW]. */ +#define FSL_FEATURE_EDMA_HAS_NO_MP_CSR_EBW (1) +/* @brief Has no register bit fields CH_SBR[ATTR]. */ +#define FSL_FEATURE_EDMA_HAS_NO_CH_SBR_ATTR (0) +/* @brief If dma has common clock gate */ +#define FSL_FEATURE_EDMA_HAS_COMMON_CLOCK_GATE (0) +/* @brief Has register bit field CH_CSR[SWAP]. */ +#define FSL_FEATURE_EDMA_HAS_CHANNEL_SWAP_SIZE (1) +/* @brief If dma channel IRQ support parameter */ +#define FSL_FEATURE_EDMA_MODULE_CHANNEL_IRQ_ENTRY_SUPPORT_PARAMETER (0) +/* @brief Instance has register bit field CH_CSR[SWAP]. */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_CHANNEL_SWAP_SIZEn(x) \ + (((x) == EDMA4_2__TCD) ? (1) : \ + (((x) == EDMA3_1__TCD) ? (0) : (-1))) +/* @brief Has register bit field CH_SBR[INSTR]. */ +#define FSL_FEATURE_EDMA_HAS_CHANNEL_ACCESS_TYPE (1) +/* @brief Instance has register bit field CH_SBR[INSTR]. */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_CHANNEL_ACCESS_TYPEn(x) \ + (((x) == EDMA4_2__TCD) ? (1) : \ + (((x) == EDMA3_1__TCD) ? (0) : (-1))) +/* @brief Has register bit fields CH_MATTR[WCACHE], CH_MATTR[RCACHE]. */ +#define FSL_FEATURE_EDMA_HAS_CHANNEL_MEMORY_ATTRIBUTE (1) +/* @brief Instance has register CH_MATTR. */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_CHANNEL_MEMORY_ATTRIBUTEn(x) \ + (((x) == EDMA4_2__TCD) ? (1) : \ + (((x) == EDMA3_1__TCD) ? (0) : (-1))) +/* @brief Has register bit field CH_CSR[SIGNEXT]. */ +#define FSL_FEATURE_EDMA_HAS_CHANNEL_SIGN_EXTENSION (1) +/* @brief Instance Has register bit field CH_CSR[SIGNEXT]. */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_CHANNEL_SIGN_EXTENSIONn(x) \ + (((x) == EDMA4_2__TCD) ? (1) : \ + (((x) == EDMA3_1__TCD) ? (0) : (-1))) +/* @brief Has register bit field TCD_CSR[BWC]. */ +#define FSL_FEATURE_EDMA_HAS_BANDWIDTH (1) +/* @brief Instance has register bit field TCD_CSR[BWC]. */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_BANDWIDTHn(x) \ + (((x) == EDMA4_2__TCD) ? (0) : \ + (((x) == EDMA3_1__TCD) ? (1) : (-1))) +/* @brief Has register bit fields TCD_CSR[TMC]. */ +#define FSL_FEATURE_EDMA_HAS_TRANSFER_MODE (1) +/* @brief Instance has register bit fields TCD_CSR[TMC]. */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_TRANSFER_MODEn(x) \ + (((x) == EDMA4_2__TCD) ? (1) : \ + (((x) == EDMA3_1__TCD) ? (0) : (-1))) + +/* ENET module features */ + +/* @brief Support Interrupt Coalesce */ +#define FSL_FEATURE_ENET_HAS_INTERRUPT_COALESCE (1) +/* @brief Queue Size. */ +#define FSL_FEATURE_ENET_QUEUE (3) +/* @brief Has AVB Support. */ +#define FSL_FEATURE_ENET_HAS_AVB (1) +/* @brief Has Timer Pulse Width control. */ +#define FSL_FEATURE_ENET_HAS_TIMER_PWCONTROL (0) +/* @brief Has Extend MDIO Support. */ +#define FSL_FEATURE_ENET_HAS_EXTEND_MDIO (1) +/* @brief Has Additional 1588 Timer Channel Interrupt. */ +#define FSL_FEATURE_ENET_HAS_ADD_1588_TIMER_CHN_INT (0) +/* @brief Support Interrupt Coalesce for each instance */ +#define FSL_FEATURE_ENET_INSTANCE_HAS_INTERRUPT_COALESCEn(x) (1) +/* @brief Queue Size for each instance. */ +#define FSL_FEATURE_ENET_INSTANCE_QUEUEn(x) (3) +/* @brief Has AVB Support for each instance. */ +#define FSL_FEATURE_ENET_INSTANCE_HAS_AVBn(x) (1) +/* @brief Has Timer Pulse Width control for each instance. */ +#define FSL_FEATURE_ENET_INSTANCE_HAS_TIMER_PWCONTROLn(x) (0) +/* @brief Has Extend MDIO Support for each instance. */ +#define FSL_FEATURE_ENET_INSTANCE_HAS_EXTEND_MDIOn(x) (1) +/* @brief Has Additional 1588 Timer Channel Interrupt for each instance. */ +#define FSL_FEATURE_ENET_INSTANCE_HAS_ADD_1588_TIMER_CHN_INTn(x) (0) +/* @brief Has threshold for the number of frames in the receive FIFO (register bit field RSEM[STAT_SECTION_EMPTY]). */ +#define FSL_FEATURE_ENET_HAS_RECEIVE_STATUS_THRESHOLD (1) +/* @brief Has trasfer clock delay (register bit field ECR[TXC_DLY]). */ +#define FSL_FEATURE_ENET_HAS_RGMII_TXC_DELAY (1) +/* @brief Has receive clock delay (register bit field ECR[RXC_DLY]). */ +#define FSL_FEATURE_ENET_HAS_RGMII_RXC_DELAY (1) +/* @brief PTP Timestamp CAPTURE bit always returns 0 when the capture is not over. */ +#define FSL_FEATURE_ENET_TIMESTAMP_CAPTURE_BIT_INVALID (0) +/* @brief ENET Has Extra Clock Gate.(RW610). */ +#define FSL_FEATURE_ENET_HAS_EXTRA_CLOCK_GATE (0) + +/* ENET_QOS module features */ + +/* @brief ENET QOS Queue Tx checksum offload support bit map. */ +#define FSL_FEATURE_ENET_QOS_TX_OFFLOAD_QUEUE_SUPPORT_BITMAP (0x1) + +/* FLEXSPI module features */ + +/* @brief FlexSPI AHB buffer count */ +#define FSL_FEATURE_FLEXSPI_AHB_BUFFER_COUNTn(x) (8) +/* @brief FlexSPI has no data learn. */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_DATA_LEARN (0) +/* @brief There is AHBBUSERROREN bit in INTEN register. */ +#define FSL_FEATURE_FLEXSPI_HAS_INTEN_AHBBUSERROREN (1) +/* @brief There is CLRAHBTX_RXBUF bit in AHBCR register. */ +#define FSL_FEATURE_FLEXSPI_HAS_AHBCR_CLRAHBTX_RXBUF (1) +/* @brief FLEXSPI has no IP parallel mode. */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_IP_PARALLEL_MODE (1) +/* @brief FLEXSPI has no AHB parallel mode. */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_AHB_PARALLEL_MODE (1) +/* @brief FLEXSPI support address shift. */ +#define FSL_FEATURE_FLEXSPI_SUPPORT_ADDRESS_SHIFT (0) +/* @brief FlexSPI has no MCR0 ARDFEN bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ARDFEN (0) +/* @brief FlexSPI has no MCR0 ATDFEN bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ATDFEN (0) +/* @brief FlexSPI has no MCR0 COMBINATIONEN bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_COMBINATIONEN (1) +/* @brief FlexSPI has no FLSHCR4 WMENB bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_FLSHCR4_WMENB (1) +/* @brief FlexSPI has no STS0 DATALEARNPHASEB bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_STS0_DATALEARNPHASEB (1) +/* @brief FlexSPI has no MCR2 SCKBDIFFOPT bit */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_MCR2_SCKBDIFFOPT (1) +/* @brief FlexSPI AHB RX buffer size (byte) */ +#define FSL_FEATURE_FLEXSPI_AHB_RX_BUFFER_SIZEn(x) (2048) +/* @brief FlexSPI Array Length */ +#define FSL_FEATURE_FLEXSPI_ARRAY_LEN (1) + +/* RGPIO module features */ + +/* @brief Has GPIO attribute checker register (GACR). */ +#define FSL_FEATURE_RGPIO_HAS_ATTRIBUTE_CHECKER (0) +/* @brief There is ICR registers */ +#define FSL_FEATURE_RGPIO_HAS_IRQ_CONFIG (1) +/* @brief There is PIDR register */ +#define FSL_FEATURE_RGPIO_HAS_PORT_INPUT_DISABLE (1) + +/* I3C module features */ + +/* @brief Has TERM bitfile in MERRWARN register. */ +#define FSL_FEATURE_I3C_HAS_NO_MERRWARN_TERM (0) +/* @brief SOC has no reset driver. */ +#define FSL_FEATURE_I3C_HAS_NO_RESET (1) +/* @brief Use fixed BAMATCH count, do not provide editable BAMATCH. */ +#define FSL_FEATURE_I3C_HAS_NO_SCONFIG_BAMATCH (0) +/* @brief Register SCONFIG do not have IDRAND bitfield. */ +#define FSL_FEATURE_I3C_HAS_NO_SCONFIG_IDRAND (1) +/* @brief Register SCONFIG has HDROK bitfield. */ +#define FSL_FEATURE_I3C_HAS_HDROK (1) +/* @brief SOC doesn't support slave IBI/MR/HJ. */ +#define FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ (0) +/* @brief Has SCL delay after START. */ +#define FSL_FEATURE_I3C_HAS_START_SCL_DELAY (1) +/* @brief Has no the master write data register for DMA. */ +#define FSL_FEATURE_I3C_HAS_NO_MASTER_DMA_WDATA_REG (0) + +/* IOMUXC1 module features */ + +/* @brief Has SDK API function for IOMUXC1 setting. */ +#define FSL_FEATURE_IOMUXC1_HAS_SDK_SUPPORT (0) + +/* LPI2C module features */ + +/* @brief Has separate DMA RX and TX requests. */ +#define FSL_FEATURE_LPI2C_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPI2C_FIFO_SIZEn(x) (8) + +/* LPIT module features */ + +/* @brief Number of channels (related to number of registers LDVALn, CVALn, TCTRLn, TFLGn). */ +#define FSL_FEATURE_LPIT_TIMER_COUNT (4) +/* @brief Has lifetime timer (related to existence of registers LTMR64L and LTMR64H). */ +#define FSL_FEATURE_LPIT_HAS_LIFETIME_TIMER (0) +/* @brief Has shared interrupt handler (has not individual interrupt handler for each channel). */ +#define FSL_FEATURE_LPIT_HAS_SHARED_IRQ_HANDLER (1) + +/* LPSPI module features */ + +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPSPI_FIFO_SIZEn(x) (8) +/* @brief Has separate DMA RX and TX requests. */ +#define FSL_FEATURE_LPSPI_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1) +/* @brief Has CCR1 (related to existence of registers CCR1). */ +#define FSL_FEATURE_LPSPI_HAS_CCR1 (1) +/* @brief Has no PCSCFG bit in CFGR1 register */ +#define FSL_FEATURE_LPSPI_HAS_NO_PCSCFG (1) +/* @brief Has no WIDTH bits in TCR register */ +#define FSL_FEATURE_LPSPI_HAS_NO_MULTI_WIDTH (1) + +/* LPTMR module features */ + +/* @brief Has shared interrupt handler with another LPTMR module. */ +#define FSL_FEATURE_LPTMR_HAS_SHARED_IRQ_HANDLER (0) +/* @brief Whether LPTMR counter is 32 bits width. */ +#define FSL_FEATURE_LPTMR_CNR_WIDTH_IS_32B (1) +/* @brief Has timer DMA request enable (register bit CSR[TDRE]). */ +#define FSL_FEATURE_LPTMR_HAS_CSR_TDRE (1) +/* @brief Do not has prescaler clock source 0. */ +#define FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_0_SUPPORT (0) +/* @brief Do not has prescaler clock source 1. */ +#define FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_1_SUPPORT (0) +/* @brief Do not has prescaler clock source 2. */ +#define FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_2_SUPPORT (0) +/* @brief Do not has prescaler clock source 3. */ +#define FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_3_SUPPORT (0) + +/* LPUART module features */ + +/* @brief Has receive FIFO overflow detection (bit field CFIFO[RXOFE]). */ +#define FSL_FEATURE_LPUART_HAS_IRQ_EXTENDED_FUNCTIONS (0) +/* @brief Has low power features (can be enabled in wait mode via register bit C1[DOZEEN] or CTRL[DOZEEN] if the registers are 32-bit wide). */ +#define FSL_FEATURE_LPUART_HAS_LOW_POWER_UART_SUPPORT (1) +/* @brief Has extended data register ED (or extra flags in the DATA register if the registers are 32-bit wide). */ +#define FSL_FEATURE_LPUART_HAS_EXTENDED_DATA_REGISTER_FLAGS (1) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_HAS_FIFO (1) +/* @brief Has 32-bit register MODIR */ +#define FSL_FEATURE_LPUART_HAS_MODIR (1) +/* @brief Hardware flow control (RTS, CTS) is supported. */ +#define FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT (1) +/* @brief Infrared (modulation) is supported. */ +#define FSL_FEATURE_LPUART_HAS_IR_SUPPORT (1) +/* @brief 2 bits long stop bit is available. */ +#define FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT (1) +/* @brief If 10-bit mode is supported. */ +#define FSL_FEATURE_LPUART_HAS_10BIT_DATA_SUPPORT (1) +/* @brief If 7-bit mode is supported. */ +#define FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT (1) +/* @brief Baud rate fine adjustment is available. */ +#define FSL_FEATURE_LPUART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT (0) +/* @brief Baud rate oversampling is available (has bit fields C4[OSR], C5[BOTHEDGE], C5[RESYNCDIS] or BAUD[OSR], BAUD[BOTHEDGE], BAUD[RESYNCDIS] if the registers are 32-bit wide). */ +#define FSL_FEATURE_LPUART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORT (1) +/* @brief Baud rate oversampling is available. */ +#define FSL_FEATURE_LPUART_HAS_RX_RESYNC_SUPPORT (1) +/* @brief Baud rate oversampling is available. */ +#define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) +/* @brief Peripheral type. */ +#define FSL_FEATURE_LPUART_IS_SCI (1) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (16) +/* @brief Supports two match addresses to filter incoming frames. */ +#define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) +/* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ +#define FSL_FEATURE_LPUART_HAS_DMA_ENABLE (1) +/* @brief Has transmitter/receiver DMA select bits C4[TDMAS]/C4[RDMAS], resp. C5[TDMAS]/C5[RDMAS] if IS_SCI = 0. */ +#define FSL_FEATURE_LPUART_HAS_DMA_SELECT (0) +/* @brief Data character bit order selection is supported (bit field S2[MSBF] or STAT[MSBF] if the registers are 32-bit wide). */ +#define FSL_FEATURE_LPUART_HAS_BIT_ORDER_SELECT (1) +/* @brief Has smart card (ISO7816 protocol) support and no improved smart card support. */ +#define FSL_FEATURE_LPUART_HAS_SMART_CARD_SUPPORT (0) +/* @brief Has improved smart card (ISO7816 protocol) support. */ +#define FSL_FEATURE_LPUART_HAS_IMPROVED_SMART_CARD_SUPPORT (0) +/* @brief Has local operation network (CEA709.1-B protocol) support. */ +#define FSL_FEATURE_LPUART_HAS_LOCAL_OPERATION_NETWORK_SUPPORT (0) +/* @brief Has 32-bit registers (BAUD, STAT, CTRL, DATA, MATCH, MODIR) instead of 8-bit (BDH, BDL, C1, S1, D, etc.). */ +#define FSL_FEATURE_LPUART_HAS_32BIT_REGISTERS (1) +/* @brief Lin break detect available (has bit BAUD[LBKDIE]). */ +#define FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT (1) +/* @brief UART stops in Wait mode available (has bit C1[UARTSWAI]). */ +#define FSL_FEATURE_LPUART_HAS_WAIT_MODE_OPERATION (0) +/* @brief Has separate DMA RX and TX requests. */ +#define FSL_FEATURE_LPUART_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1) +/* @brief Has separate RX and TX interrupts. */ +#define FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ (0) +/* @brief Has LPAURT_PARAM. */ +#define FSL_FEATURE_LPUART_HAS_PARAM (1) +/* @brief Has LPUART_VERID. */ +#define FSL_FEATURE_LPUART_HAS_VERID (1) +/* @brief Has LPUART_GLOBAL. */ +#define FSL_FEATURE_LPUART_HAS_GLOBAL (1) +/* @brief Has LPUART_PINCFG. */ +#define FSL_FEATURE_LPUART_HAS_PINCFG (1) +/* @brief Has register MODEM Control. */ +#define FSL_FEATURE_LPUART_HAS_MCR (1) +/* @brief Has register Half Duplex Control. */ +#define FSL_FEATURE_LPUART_HAS_HDCR (1) +/* @brief Has register Timeout. */ +#define FSL_FEATURE_LPUART_HAS_TIMEOUT (1) + +/* PDM module features */ + +/* @brief PDM FIFO offset */ +#define FSL_FEATURE_PDM_FIFO_OFFSET (4) +/* @brief PDM Channel Number */ +#define FSL_FEATURE_PDM_CHANNEL_NUM (8) +/* @brief PDM FIFO WIDTH Size */ +#define FSL_FEATURE_PDM_FIFO_WIDTH (4) +/* @brief PDM FIFO DEPTH Size */ +#define FSL_FEATURE_PDM_FIFO_DEPTH (8) +/* @brief PDM has RANGE_CTRL register */ +#define FSL_FEATURE_PDM_HAS_RANGE_CTRL (1) +/* @brief PDM Has Low Frequency */ +#define FSL_FEATURE_PDM_HAS_STATUS_LOW_FREQ (1) +/* @brief CLKDIV factor in Medium, High and Low Quality modes */ +#define FSL_FEATURE_PDM_HIGH_QUALITY_CLKDIV_FACTOR (93) +/* @brief CLKDIV factor in Very Low Quality modes */ +#define FSL_FEATURE_PDM_VERY_LOW_QUALITY_CLKDIV_FACTOR (43) +/* @brief PDM Has No VADEF Bitfield In PDM VAD0_STAT Register */ +#define FSL_FEATURE_PDM_HAS_NO_VADEF (1) +/* @brief PDM Has no FIR_RDY Bitfield In PDM STAT Register */ +#define FSL_FEATURE_PDM_HAS_NO_FIR_RDY (0) +/* @brief PDM Has no DOZEN Bitfield In PDM CTRL_1 Register */ +#define FSL_FEATURE_PDM_HAS_NO_DOZEN (0) +/* @brief PDM Has DEC_BYPASS Bitfield In PDM CTRL_2 Register */ +#define FSL_FEATURE_PDM_HAS_DECIMATION_FILTER_BYPASS (0) + +/* SAI module features */ + +/* @brief SAI has FIFO in this soc (register bit fields TCR1[TFW]. */ +#define FSL_FEATURE_SAI_HAS_FIFO (1) +/* @brief Receive/transmit FIFO size in item count (register bit fields TCSR[FRDE], TCSR[FRIE], TCSR[FRF], TCR1[TFW], RCSR[FRDE], RCSR[FRIE], RCSR[FRF], RCR1[RFW], registers TFRn, RFRn). */ +#define FSL_FEATURE_SAI_FIFO_COUNTn(x) \ + (((x) == SAI1) ? (64) : \ + (((x) == SAI2) ? (128) : \ + (((x) == SAI3) ? (128) : (-1)))) +/* @brief Receive/transmit channel number (register bit fields TCR3[TCE], RCR3[RCE], registers TDRn and RDRn). */ +#define FSL_FEATURE_SAI_CHANNEL_COUNTn(x) \ + (((x) == SAI1) ? (2) : \ + (((x) == SAI2) ? (1) : \ + (((x) == SAI3) ? (1) : (-1)))) +/* @brief Maximum words per frame (register bit fields TCR3[WDFL], TCR4[FRSZ], TMR[TWM], RCR3[WDFL], RCR4[FRSZ], RMR[RWM]). */ +#define FSL_FEATURE_SAI_MAX_WORDS_PER_FRAME (32) +/* @brief Has support of combining multiple data channel FIFOs into single channel FIFO (register bit fields TCR3[CFR], TCR4[FCOMB], TFR0[WCP], TFR1[WCP], RCR3[CFR], RCR4[FCOMB], RFR0[RCP], RFR1[RCP]). */ +#define FSL_FEATURE_SAI_HAS_FIFO_COMBINE_MODE (1) +/* @brief Has packing of 8-bit and 16-bit data into each 32-bit FIFO word (register bit fields TCR4[FPACK], RCR4[FPACK]). */ +#define FSL_FEATURE_SAI_HAS_FIFO_PACKING (1) +/* @brief Configures when the SAI will continue transmitting after a FIFO error has been detected (register bit fields TCR4[FCONT], RCR4[FCONT]). */ +#define FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_AFTER_ERROR (1) +/* @brief Configures if the frame sync is generated internally, a frame sync is only generated when the FIFO warning flag is clear or continuously (register bit fields TCR4[ONDEM], RCR4[ONDEM]). */ +#define FSL_FEATURE_SAI_HAS_ON_DEMAND_MODE (1) +/* @brief Simplified bit clock source and asynchronous/synchronous mode selection (register bit fields TCR2[CLKMODE], RCR2[CLKMODE]), in comparison with the exclusively implemented TCR2[SYNC,BCS,BCI,MSEL], RCR2[SYNC,BCS,BCI,MSEL]. */ +#define FSL_FEATURE_SAI_HAS_CLOCKING_MODE (0) +/* @brief Has register for configuration of the MCLK divide ratio (register bit fields MDR[FRACT], MDR[DIVIDE]). */ +#define FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER (0) +/* @brief Interrupt source number */ +#define FSL_FEATURE_SAI_INT_SOURCE_NUM (1) +/* @brief Has register of MCR. */ +#define FSL_FEATURE_SAI_HAS_MCR (1) +/* @brief Has bit field MICS of the MCR register. */ +#define FSL_FEATURE_SAI_HAS_NO_MCR_MICS (1) +/* @brief Has register of MDR */ +#define FSL_FEATURE_SAI_HAS_MDR (0) +/* @brief Has support the BCLK bypass mode when BCLK = MCLK. */ +#define FSL_FEATURE_SAI_HAS_BCLK_BYPASS (1) +/* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]. */ +#define FSL_FEATURE_SAI_HAS_MCR_MCLK_POST_DIV (1) +/* @brief Support Channel Mode (register bit fields TCR4[CHMOD]). */ +#define FSL_FEATURE_SAI_HAS_CHANNEL_MODE (1) +/* @brief Support synchronous with another SAI. */ +#define FSL_FEATURE_SAI_HAS_SYNC_WITH_ANOTHER_SAI (0) + +/* SEMA42 module features */ + +/* @brief Gate counts */ +#define FSL_FEATURE_SEMA42_GATE_COUNT (64) + +/* TPM module features */ + +/* @brief Number of channels. */ +#define FSL_FEATURE_TPM_CHANNEL_COUNTn(x) (4) +/* @brief Has counter reset by the selected input capture event (register bits C0SC[ICRST], C1SC[ICRST], ...). */ +#define FSL_FEATURE_TPM_HAS_COUNTER_RESET_BY_CAPTURE_EVENT (0) +/* @brief Has TPM_PARAM. */ +#define FSL_FEATURE_TPM_HAS_PARAM (1) +/* @brief Has TPM_VERID. */ +#define FSL_FEATURE_TPM_HAS_VERID (1) +/* @brief Has TPM_GLOBAL. */ +#define FSL_FEATURE_TPM_HAS_GLOBAL (1) +/* @brief Has TPM_TRIG. */ +#define FSL_FEATURE_TPM_HAS_TRIG (1) +/* @brief Whether TRIG register has effect. */ +#define FSL_FEATURE_TPM_TRIG_HAS_EFFECTn(x) (0) +/* @brief Has global time base enable. */ +#define FSL_FEATURE_TPM_HAS_GLOBAL_TIME_BASE_EN (1) +/* @brief Has global time base sync. */ +#define FSL_FEATURE_TPM_HAS_GLOBAL_TIME_BASE_SYNC (1) +/* @brief Has counter pause on trigger. */ +#define FSL_FEATURE_TPM_HAS_PAUSE_COUNTER_ON_TRIGGER (1) +/* @brief Has external trigger selection. */ +#define FSL_FEATURE_TPM_HAS_EXTERNAL_TRIGGER_SELECTION (1) +/* @brief Has TPM_COMBINE register. */ +#define FSL_FEATURE_TPM_HAS_COMBINE (1) +/* @brief Whether COMBINE register has effect. */ +#define FSL_FEATURE_TPM_COMBINE_HAS_EFFECTn(x) (1) +/* @brief Has TPM_POL. */ +#define FSL_FEATURE_TPM_HAS_POL (1) +/* @brief Whether POL register has effect. */ +#define FSL_FEATURE_TPM_POL_HAS_EFFECTn(x) (0) +/* @brief Has TPM_FILTER register. */ +#define FSL_FEATURE_TPM_HAS_FILTER (1) +/* @brief Whether FILTER register has effect. */ +#define FSL_FEATURE_TPM_FILTER_HAS_EFFECTn(x) (1) +/* @brief Has TPM_QDCTRL register. */ +#define FSL_FEATURE_TPM_HAS_QDCTRL (1) +/* @brief Whether QDCTRL register has effect. */ +#define FSL_FEATURE_TPM_QDCTRL_HAS_EFFECTn(x) (1) +/* @brief Has pause level select. */ +#define FSL_FEATURE_TPM_HAS_PAUSE_LEVEL_SELECT (1) +/* @brief Whether 32 bits counter has effect. */ +#define FSL_FEATURE_TPM_HAS_32BIT_COUNTERn(x) (1) + +/* TRDC module features */ + +/* @brief Process master count. */ +#define FSL_FEATURE_TRDC_PROCESSOR_MASTER_COUNT (2) +/* @brief TRDC instance has PID configuration or not. */ +#define FSL_FEATURE_TRDC_INSTANCE_HAS_PID_CONFIGURATIONn(x) (0) +/* @brief TRDC domain number (reset value of HWCFG0[NDID]). */ +#define FSL_FEATURE_TRDC_DOMAIN_COUNT (16) +/* @brief TRDC instance has MBC. */ +#define FSL_FEATURE_TRDC_HAS_MBC (1) +/* @brief TRDC instance has MRC. */ +#define FSL_FEATURE_TRDC_HAS_MRC (1) +/* @brief TRDC instance has TRDC_CR. */ +#define FSL_FEATURE_TRDC_HAS_GENERAL_CONFIG (1) +/* @brief TRDC instance has MDA_Wx_y_DFMT. */ +#define FSL_FEATURE_TRDC_HAS_DOMAIN_ASSIGNMENT (1) +/* @brief TRDC instance has TRDC_FDID. */ +#define FSL_FEATURE_TRDC_HAS_DOMAIN_ERROR (1) +/* @brief TRDC instance has TRDC_FLW_CTL. */ +#define FSL_FEATURE_TRDC_HAS_FLW (1) + +/* USDHC module features */ + +/* @brief Has external DMA support (VEND_SPEC[EXT_DMA_EN]) */ +#define FSL_FEATURE_USDHC_HAS_EXT_DMA (0) +/* @brief Has HS400 mode (MIX_CTRL[HS400_MODE]) */ +#define FSL_FEATURE_USDHC_HAS_HS400_MODE (1) +/* @brief Has SDR50 support (HOST_CTRL_CAP[SDR50_SUPPORT]) */ +#define FSL_FEATURE_USDHC_HAS_SDR50_MODE (1) +/* @brief Has SDR104 support (HOST_CTRL_CAP[SDR104_SUPPORT]) */ +#define FSL_FEATURE_USDHC_HAS_SDR104_MODE (1) +/* @brief USDHC has reset control */ +#define FSL_FEATURE_USDHC_HAS_RESET (0) +/* @brief USDHC has no bitfield WTMK_LVL[WR_BRST_LEN] and WTMK_LVL[RD_BRST_LEN] */ +#define FSL_FEATURE_USDHC_HAS_NO_RW_BURST_LEN (1) +/* @brief If USDHC instance support 8 bit width */ +#define FSL_FEATURE_USDHC_INSTANCE_SUPPORT_8_BIT_WIDTHn(x) (1) +/* @brief If USDHC instance support HS400 mode */ +#define FSL_FEATURE_USDHC_INSTANCE_SUPPORT_HS400_MODEn(x) (0) +/* @brief If USDHC instance support 1v8 signal */ +#define FSL_FEATURE_USDHC_INSTANCE_SUPPORT_1V8_SIGNALn(x) (1) +/* @brief Has no retuning time counter (HOST_CTRL_CAP[TIME_COUNT_RETURNING]) */ +#define FSL_FEATURE_USDHC_REGISTER_HOST_CTRL_CAP_HAS_NO_RETUNING_TIME_COUNTER (1) +/* @brief Has no VSELECT bit in VEND_SPEC register */ +#define FSL_FEATURE_USDHC_HAS_NO_VOLTAGE_SELECT (0) +/* @brief Has no VS18 bit in HOST_CTRL_CAP register */ +#define FSL_FEATURE_USDHC_HAS_NO_VS18 (0) + +/* WDOG module features */ + +/* @brief Watchdog is available. */ +#define FSL_FEATURE_WDOG_HAS_WATCHDOG (1) +/* @brief WDOG_CNT can be 32-bit written. */ +#define FSL_FEATURE_WDOG_HAS_32BIT_ACCESS (1) + +/* CACHE module features */ + +/* @brief L1 ICACHE line size in byte. */ +#define FSL_FEATURE_L1ICACHE_LINESIZE_BYTE (64) +/* @brief L1 DCACHE line size in byte. */ +#define FSL_FEATURE_L1DCACHE_LINESIZE_BYTE (64) +/* @brief Has NONCACHEABLE section. */ +#define FSL_FEATURE_HAS_NO_NONCACHEABLE_SECTION (0) + +/* MEMORY module features */ + +/* @brief Memory map doesn't have offset between subsystems. */ +#define FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET (0) + +#endif /* _MIMX9131_FEATURES_H_ */ + diff --git a/bsp/nxp/imx/imx91/drivers/sdk/devices/MIMX9131/SConscript b/bsp/nxp/imx/imx91/drivers/sdk/devices/MIMX9131/SConscript new file mode 100644 index 00000000000..43869fedcc6 --- /dev/null +++ b/bsp/nxp/imx/imx91/drivers/sdk/devices/MIMX9131/SConscript @@ -0,0 +1,19 @@ +# for module compiling +import os +from building import * + +cwd = GetCurrentDir() +src = Glob('*.c') + Glob('drivers/*.c') + +CPPPATH = [cwd, cwd + '/drivers'] +CPPDEFINES = [ + {'CPU_MIMX9131DVVXJ': 1} +] +objs = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH, CPPDEFINES = CPPDEFINES) + +for item in os.listdir(cwd): + sconsfile = os.path.join(item, 'SConscript') + if os.path.isfile(os.path.join(cwd, sconsfile)): + objs += SConscript(sconsfile) + +Return('objs') diff --git a/bsp/nxp/imx/imx91/drivers/sdk/devices/MIMX9131/all_lib_device_MIMX9131.cmake b/bsp/nxp/imx/imx91/drivers/sdk/devices/MIMX9131/all_lib_device_MIMX9131.cmake new file mode 100644 index 00000000000..3dd91b836a6 --- /dev/null +++ b/bsp/nxp/imx/imx91/drivers/sdk/devices/MIMX9131/all_lib_device_MIMX9131.cmake @@ -0,0 +1,64 @@ +list(APPEND CMAKE_MODULE_PATH + ${CMAKE_CURRENT_LIST_DIR}/. + ${CMAKE_CURRENT_LIST_DIR}/../../CMSIS/Core_AArch64/Include + ${CMAKE_CURRENT_LIST_DIR}/../../components/i2c + ${CMAKE_CURRENT_LIST_DIR}/../../components/lists + ${CMAKE_CURRENT_LIST_DIR}/../../components/phy + ${CMAKE_CURRENT_LIST_DIR}/../../components/phy/device/phyrtl8211f + ${CMAKE_CURRENT_LIST_DIR}/../../components/phy/mdio + ${CMAKE_CURRENT_LIST_DIR}/../../components/phy/mdio/enet + ${CMAKE_CURRENT_LIST_DIR}/../../components/phy/mdio/enet_qos + ${CMAKE_CURRENT_LIST_DIR}/../../components/serial_manager + ${CMAKE_CURRENT_LIST_DIR}/../../components/uart + ${CMAKE_CURRENT_LIST_DIR}/../../drivers/cache/armv8-a + ${CMAKE_CURRENT_LIST_DIR}/../../drivers/common + ${CMAKE_CURRENT_LIST_DIR}/../../drivers/enet + ${CMAKE_CURRENT_LIST_DIR}/../../drivers/enet_qos + ${CMAKE_CURRENT_LIST_DIR}/../../drivers/flexcan + ${CMAKE_CURRENT_LIST_DIR}/../../drivers/lptmr + ${CMAKE_CURRENT_LIST_DIR}/../../drivers/tpm + ${CMAKE_CURRENT_LIST_DIR}/../../drivers/lpi2c + ${CMAKE_CURRENT_LIST_DIR}/../../drivers/lpuart + ${CMAKE_CURRENT_LIST_DIR}/../../drivers/mu1 + ${CMAKE_CURRENT_LIST_DIR}/../../drivers/rgpio + ${CMAKE_CURRENT_LIST_DIR}/../../drivers/sai + ${CMAKE_CURRENT_LIST_DIR}/../../utilities/assert + ${CMAKE_CURRENT_LIST_DIR}/../../utilities + ${CMAKE_CURRENT_LIST_DIR}/../../utilities/misc_utilities + ${CMAKE_CURRENT_LIST_DIR}/drivers +) + + +# Copy the cmake components into projects +# include(driver_lpi2c) +# include(driver_lpi2c_edma) +# include(driver_lpi2c_freertos) +# include(driver_lpuart_dma) +# include(driver_lpuart_edma) +# include(driver_lpuart_freertos) +# include(component_lpi2c_adapter) +# include(component_lpuart_adapter) +# include(component_lists) +# include(component_serial_manager) +# include(component_serial_manager_uart) +# include(device_startup) +# include(device_system) +# include(driver_cache_armv8a) +# include(driver_common) +# include(driver_enet) +# include(driver_flexcan) +# include(driver_lptmr) +# include(driver_tpm) +# include(driver_rgpio) +# include(driver_lpuart) +# include(driver_mdio-enet) +# include(driver_mu1) +# include(driver_phy-device-rtl8211f) +# include(driver_sai) +# include(middleware_freertos-kernel_aarch64) +# include(middleware_freertos-kernel_extension) +# include(middleware_freertos-kernel_heap_4) +# include(utilities_misc_utilities) +# include(utility_assert) +# include(utility_debug_console) +# include(utility_debug_console_lite) diff --git a/bsp/nxp/imx/imx91/drivers/sdk/devices/MIMX9131/device_CMSIS.cmake b/bsp/nxp/imx/imx91/drivers/sdk/devices/MIMX9131/device_CMSIS.cmake new file mode 100644 index 00000000000..5c14b183da7 --- /dev/null +++ b/bsp/nxp/imx/imx91/drivers/sdk/devices/MIMX9131/device_CMSIS.cmake @@ -0,0 +1,15 @@ +#Description: device_CMSIS; user_visible: False +include_guard(GLOBAL) +message("device_CMSIS component is included.") + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/. +) + + +if(${MCUX_DEVICE} STREQUAL "MIMX9131") + include(CMSIS_Include_core_ca OPTIONAL) +endif() diff --git a/bsp/nxp/imx/imx91/drivers/sdk/devices/MIMX9131/device_system.cmake b/bsp/nxp/imx/imx91/drivers/sdk/devices/MIMX9131/device_system.cmake new file mode 100644 index 00000000000..e59c2802ab1 --- /dev/null +++ b/bsp/nxp/imx/imx91/drivers/sdk/devices/MIMX9131/device_system.cmake @@ -0,0 +1,14 @@ +#Description: device_system; user_visible: False +include_guard(GLOBAL) +message("device_system component is included.") + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/system_MIMX9131.c +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/. +) + + +#include(device_CMSIS) diff --git a/bsp/nxp/imx/imx91/drivers/sdk/devices/MIMX9131/drivers/driver_clock.cmake b/bsp/nxp/imx/imx91/drivers/sdk/devices/MIMX9131/drivers/driver_clock.cmake new file mode 100644 index 00000000000..e91de205335 --- /dev/null +++ b/bsp/nxp/imx/imx91/drivers/sdk/devices/MIMX9131/drivers/driver_clock.cmake @@ -0,0 +1,15 @@ +include_guard() +message("driver_clock component is included.") + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/fsl_clock.c +) + + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/. +) + + +include(driver_common) + diff --git a/bsp/nxp/imx/imx91/drivers/sdk/devices/MIMX9131/drivers/driver_iomuxc.cmake b/bsp/nxp/imx/imx91/drivers/sdk/devices/MIMX9131/drivers/driver_iomuxc.cmake new file mode 100644 index 00000000000..71c55a6a05c --- /dev/null +++ b/bsp/nxp/imx/imx91/drivers/sdk/devices/MIMX9131/drivers/driver_iomuxc.cmake @@ -0,0 +1,10 @@ +include_guard() +message("driver_iomuxc component is included.") + + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/. +) + +include(driver_common) + diff --git a/bsp/nxp/imx/imx91/drivers/sdk/devices/MIMX9131/drivers/driver_memory.cmake b/bsp/nxp/imx/imx91/drivers/sdk/devices/MIMX9131/drivers/driver_memory.cmake new file mode 100644 index 00000000000..f8778e3fa0e --- /dev/null +++ b/bsp/nxp/imx/imx91/drivers/sdk/devices/MIMX9131/drivers/driver_memory.cmake @@ -0,0 +1,10 @@ +include_guard() +message("driver_memory component is included.") + + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/. +) + +include(driver_common) + diff --git a/bsp/nxp/imx/imx91/drivers/sdk/devices/MIMX9131/drivers/driver_reset.cmake b/bsp/nxp/imx/imx91/drivers/sdk/devices/MIMX9131/drivers/driver_reset.cmake new file mode 100644 index 00000000000..9b3c82d5719 --- /dev/null +++ b/bsp/nxp/imx/imx91/drivers/sdk/devices/MIMX9131/drivers/driver_reset.cmake @@ -0,0 +1,10 @@ +#Description: Reset Driver; user_visible: False +include_guard(GLOBAL) +message("driver_reset component is included.") + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/. +) diff --git a/bsp/nxp/imx/imx91/drivers/sdk/devices/MIMX9131/drivers/fsl_clock.c b/bsp/nxp/imx/imx91/drivers/sdk/devices/MIMX9131/drivers/fsl_clock.c new file mode 100644 index 00000000000..ccc9609fb36 --- /dev/null +++ b/bsp/nxp/imx/imx91/drivers/sdk/devices/MIMX9131/drivers/fsl_clock.c @@ -0,0 +1,149 @@ +/* + * Copyright 2025 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#include "fsl_clock.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.clock" +#endif + +/* ROM initializes PLLs with default frequencies except audio/video/ext */ +volatile uint32_t g_clockSourceFreq[kCLOCK_Ext + 1] = { + 24000000U, /* kCLOCK_Osc24M */ + 2000000000U, /* kCLOCK_ArmPll */ + 2000000000U, /* kCLOCK_ArmPllOut */ + 1000000000U, /* kCLOCK_DramPll */ + 1000000000U, /* kCLOCK_DramPllOut */ + 4000000000U, /* kCLOCK_SysPll1 */ + 1000000000U, /* kCLOCK_SysPll1Pfd0 */ + 500000000U, /* kCLOCK_SysPll1Pfd0Div2 */ + 800000000U, /* kCLOCK_SysPll1Pfd1 */ + 400000000U, /* kCLOCK_SysPll1Pfd1Div2 */ + 625000000U, /* kCLOCK_SysPll1Pfd2 */ + 312500000U, /* kCLOCK_SysPll1Pfd2Div2 */ + 0U, /* kCLOCK_AudioPll1 */ + 0U, /* kCLOCK_AudioPll1Out */ + 0U, /* kCLOCK_VideoPll1 */ + 0U, /* kCLOCK_VideoPll1Out */ + 0U /* kCLOCK_Ext */ +}; + +const clock_name_t s_clockSourceName[][4] = { + /*SRC0, SRC1, SRC2, SRC3, */ + {kCLOCK_Osc24M, kCLOCK_SysPll1Pfd0, kCLOCK_SysPll1Pfd1, kCLOCK_SysPll1Pfd2}, /* Arm A55 Periph */ + {kCLOCK_Osc24M, kCLOCK_SysPll1Pfd0Div2, kCLOCK_SysPll1Pfd1Div2, kCLOCK_VideoPll1Out}, /* Arm A55 MTR BUS */ + {kCLOCK_Osc24M, kCLOCK_SysPll1Pfd0, kCLOCK_SysPll1Pfd1, kCLOCK_SysPll1Pfd2}, /* Arm A55 */ + {kCLOCK_Osc24M, kCLOCK_SysPll1Pfd0Div2, kCLOCK_SysPll1Pfd1Div2, kCLOCK_VideoPll1Out}, /* M33 */ + {kCLOCK_Osc24M, kCLOCK_SysPll1Pfd0Div2, kCLOCK_SysPll1Pfd1Div2, kCLOCK_VideoPll1Out}, /* Sentinel */ + {kCLOCK_Osc24M, kCLOCK_SysPll1Pfd0Div2, kCLOCK_SysPll1Pfd1Div2, kCLOCK_VideoPll1Out}, /* Bus Wakeup */ + {kCLOCK_Osc24M, kCLOCK_SysPll1Pfd0Div2, kCLOCK_SysPll1Pfd1Div2, kCLOCK_VideoPll1Out}, /* Bus Aon */ + {kCLOCK_Osc24M, kCLOCK_SysPll1Pfd0, kCLOCK_SysPll1Pfd1, kCLOCK_SysPll1Pfd2}, /* Wakeup Axi */ + {kCLOCK_Osc24M, kCLOCK_SysPll1Pfd0Div2, kCLOCK_SysPll1Pfd1Div2, kCLOCK_VideoPll1Out}, /* Swo Trace */ + {kCLOCK_Osc24M, kCLOCK_SysPll1Pfd0Div2, kCLOCK_SysPll1Pfd1Div2, kCLOCK_VideoPll1Out}, /* M33 Systick */ + {kCLOCK_Osc24M, kCLOCK_SysPll1Pfd0Div2, kCLOCK_SysPll1Pfd1Div2, kCLOCK_VideoPll1Out}, /* Flexio1 */ + {kCLOCK_Osc24M, kCLOCK_SysPll1Pfd0Div2, kCLOCK_SysPll1Pfd1Div2, kCLOCK_VideoPll1Out}, /* Flexio2 */ + {kCLOCK_Osc24M, kCLOCK_SysPll1Pfd0Div2, kCLOCK_SysPll1Pfd1Div2, kCLOCK_VideoPll1Out}, /* Lpit1 */ + {kCLOCK_Osc24M, kCLOCK_SysPll1Pfd0Div2, kCLOCK_SysPll1Pfd1Div2, kCLOCK_VideoPll1Out}, /* Lpit2 */ + {kCLOCK_Osc24M, kCLOCK_SysPll1Pfd0Div2, kCLOCK_SysPll1Pfd1Div2, kCLOCK_VideoPll1Out}, /* Lptmr1 */ + {kCLOCK_Osc24M, kCLOCK_SysPll1Pfd0Div2, kCLOCK_SysPll1Pfd1Div2, kCLOCK_VideoPll1Out}, /* Lptmr2 */ + {kCLOCK_Osc24M, kCLOCK_SysPll1Pfd0, kCLOCK_AudioPll1Out, kCLOCK_Ext}, /* Tpm1 */ + {kCLOCK_Osc24M, kCLOCK_SysPll1Pfd0, kCLOCK_AudioPll1Out, kCLOCK_Ext}, /* Tpm2 */ + {kCLOCK_Osc24M, kCLOCK_SysPll1Pfd0, kCLOCK_AudioPll1Out, kCLOCK_Ext}, /* Tpm3 */ + {kCLOCK_Osc24M, kCLOCK_SysPll1Pfd0, kCLOCK_AudioPll1Out, kCLOCK_Ext}, /* Tpm4 */ + {kCLOCK_Osc24M, kCLOCK_SysPll1Pfd0, kCLOCK_AudioPll1Out, kCLOCK_Ext}, /* Tpm5 */ + {kCLOCK_Osc24M, kCLOCK_SysPll1Pfd0, kCLOCK_AudioPll1Out, kCLOCK_Ext}, /* Tpm6 */ + {kCLOCK_Osc24M, kCLOCK_SysPll1Pfd0, kCLOCK_SysPll1Pfd1, kCLOCK_SysPll1Pfd2}, /* Flexspi1 */ + {kCLOCK_Osc24M, kCLOCK_SysPll1Pfd0Div2, kCLOCK_SysPll1Pfd1Div2, kCLOCK_VideoPll1Out}, /* Can1 */ + {kCLOCK_Osc24M, kCLOCK_SysPll1Pfd0Div2, kCLOCK_SysPll1Pfd1Div2, kCLOCK_VideoPll1Out}, /* Can2 */ + {kCLOCK_Osc24M, kCLOCK_SysPll1Pfd0Div2, kCLOCK_SysPll1Pfd1Div2, kCLOCK_VideoPll1Out}, /* Lpuart1 */ + {kCLOCK_Osc24M, kCLOCK_SysPll1Pfd0Div2, kCLOCK_SysPll1Pfd1Div2, kCLOCK_VideoPll1Out}, /* Lpuart2 */ + {kCLOCK_Osc24M, kCLOCK_SysPll1Pfd0Div2, kCLOCK_SysPll1Pfd1Div2, kCLOCK_VideoPll1Out}, /* Lpuart3 */ + {kCLOCK_Osc24M, kCLOCK_SysPll1Pfd0Div2, kCLOCK_SysPll1Pfd1Div2, kCLOCK_VideoPll1Out}, /* Lpuart4 */ + {kCLOCK_Osc24M, kCLOCK_SysPll1Pfd0Div2, kCLOCK_SysPll1Pfd1Div2, kCLOCK_VideoPll1Out}, /* Lpuart5 */ + {kCLOCK_Osc24M, kCLOCK_SysPll1Pfd0Div2, kCLOCK_SysPll1Pfd1Div2, kCLOCK_VideoPll1Out}, /* Lpuart6 */ + {kCLOCK_Osc24M, kCLOCK_SysPll1Pfd0Div2, kCLOCK_SysPll1Pfd1Div2, kCLOCK_VideoPll1Out}, /* Lpuart7 */ + {kCLOCK_Osc24M, kCLOCK_SysPll1Pfd0Div2, kCLOCK_SysPll1Pfd1Div2, kCLOCK_VideoPll1Out}, /* Lpuart8 */ + {kCLOCK_Osc24M, kCLOCK_SysPll1Pfd0Div2, kCLOCK_SysPll1Pfd1Div2, kCLOCK_VideoPll1Out}, /* Lpi2c1 */ + {kCLOCK_Osc24M, kCLOCK_SysPll1Pfd0Div2, kCLOCK_SysPll1Pfd1Div2, kCLOCK_VideoPll1Out}, /* Lpi2c2 */ + {kCLOCK_Osc24M, kCLOCK_SysPll1Pfd0Div2, kCLOCK_SysPll1Pfd1Div2, kCLOCK_VideoPll1Out}, /* Lpi2c3 */ + {kCLOCK_Osc24M, kCLOCK_SysPll1Pfd0Div2, kCLOCK_SysPll1Pfd1Div2, kCLOCK_VideoPll1Out}, /* Lpi2c4 */ + {kCLOCK_Osc24M, kCLOCK_SysPll1Pfd0Div2, kCLOCK_SysPll1Pfd1Div2, kCLOCK_VideoPll1Out}, /* Lpi2c5 */ + {kCLOCK_Osc24M, kCLOCK_SysPll1Pfd0Div2, kCLOCK_SysPll1Pfd1Div2, kCLOCK_VideoPll1Out}, /* Lpi2c6 */ + {kCLOCK_Osc24M, kCLOCK_SysPll1Pfd0Div2, kCLOCK_SysPll1Pfd1Div2, kCLOCK_VideoPll1Out}, /* Lpi2c7 */ + {kCLOCK_Osc24M, kCLOCK_SysPll1Pfd0Div2, kCLOCK_SysPll1Pfd1Div2, kCLOCK_VideoPll1Out}, /* Lpi2c8 */ + {kCLOCK_Osc24M, kCLOCK_SysPll1Pfd0Div2, kCLOCK_SysPll1Pfd1Div2, kCLOCK_VideoPll1Out}, /* Lpspi1 */ + {kCLOCK_Osc24M, kCLOCK_SysPll1Pfd0Div2, kCLOCK_SysPll1Pfd1Div2, kCLOCK_VideoPll1Out}, /* Lpspi2 */ + {kCLOCK_Osc24M, kCLOCK_SysPll1Pfd0Div2, kCLOCK_SysPll1Pfd1Div2, kCLOCK_VideoPll1Out}, /* Lpspi3 */ + {kCLOCK_Osc24M, kCLOCK_SysPll1Pfd0Div2, kCLOCK_SysPll1Pfd1Div2, kCLOCK_VideoPll1Out}, /* Lpspi4 */ + {kCLOCK_Osc24M, kCLOCK_SysPll1Pfd0Div2, kCLOCK_SysPll1Pfd1Div2, kCLOCK_VideoPll1Out}, /* Lpspi5 */ + {kCLOCK_Osc24M, kCLOCK_SysPll1Pfd0Div2, kCLOCK_SysPll1Pfd1Div2, kCLOCK_VideoPll1Out}, /* Lpspi6 */ + {kCLOCK_Osc24M, kCLOCK_SysPll1Pfd0Div2, kCLOCK_SysPll1Pfd1Div2, kCLOCK_VideoPll1Out}, /* Lpspi7 */ + {kCLOCK_Osc24M, kCLOCK_SysPll1Pfd0Div2, kCLOCK_SysPll1Pfd1Div2, kCLOCK_VideoPll1Out}, /* Lpspi8 */ + {kCLOCK_Osc24M, kCLOCK_SysPll1Pfd0Div2, kCLOCK_SysPll1Pfd1Div2, kCLOCK_VideoPll1Out}, /* I3c1 */ + {kCLOCK_Osc24M, kCLOCK_SysPll1Pfd0Div2, kCLOCK_SysPll1Pfd1Div2, kCLOCK_VideoPll1Out}, /* I3c2 */ + {kCLOCK_Osc24M, kCLOCK_SysPll1Pfd0, kCLOCK_SysPll1Pfd1, kCLOCK_SysPll1Pfd2}, /* Usdhc1 */ + {kCLOCK_Osc24M, kCLOCK_SysPll1Pfd0, kCLOCK_SysPll1Pfd1, kCLOCK_SysPll1Pfd2}, /* Usdhc2 */ + {kCLOCK_Osc24M, kCLOCK_SysPll1Pfd0, kCLOCK_SysPll1Pfd1, kCLOCK_SysPll1Pfd2}, /* Usdhc3 */ + {kCLOCK_Osc24M, kCLOCK_AudioPll1Out, kCLOCK_VideoPll1Out, kCLOCK_Ext}, /* Sai1 */ + {kCLOCK_Osc24M, kCLOCK_AudioPll1Out, kCLOCK_VideoPll1Out, kCLOCK_Ext}, /* Sai2 */ + {kCLOCK_Osc24M, kCLOCK_AudioPll1Out, kCLOCK_VideoPll1Out, kCLOCK_Ext}, /* Sai3 */ + {kCLOCK_Osc24M, kCLOCK_SysPll1Pfd0, kCLOCK_SysPll1Pfd1, kCLOCK_AudioPll1Out}, /* Ccm Cko1 */ + {kCLOCK_Osc24M, kCLOCK_SysPll1Pfd0, kCLOCK_SysPll1Pfd1, kCLOCK_VideoPll1Out}, /* Ccm Cko2 */ + {kCLOCK_Osc24M, kCLOCK_SysPll1Pfd0, kCLOCK_SysPll1Pfd1, kCLOCK_AudioPll1Out}, /* Ccm Cko3 */ + {kCLOCK_Osc24M, kCLOCK_SysPll1Pfd0, kCLOCK_SysPll1Pfd1, kCLOCK_VideoPll1Out}, /* Ccm Cko4 */ + {kCLOCK_Osc24M, kCLOCK_SysPll1Pfd0Div2, kCLOCK_SysPll1Pfd1Div2, kCLOCK_VideoPll1Out}, /* Hsio */ + {kCLOCK_Osc24M, kCLOCK_SysPll1Pfd0Div2, kCLOCK_SysPll1Pfd1Div2, kCLOCK_VideoPll1Out}, /* Hsio Usb Test 60M */ + {kCLOCK_Osc24M, kCLOCK_SysPll1Pfd0Div2, kCLOCK_SysPll1Pfd1Div2, kCLOCK_VideoPll1Out}, /* Hsio Acscan 80M */ + {kCLOCK_Osc24M, kCLOCK_AudioPll1Out, kCLOCK_VideoPll1Out, kCLOCK_SysPll1Pfd2}, /* Hsio Acscan 480M */ + {kCLOCK_Osc24M, kCLOCK_SysPll1Pfd0, kCLOCK_SysPll1Pfd1, kCLOCK_SysPll1Pfd2}, /* Nic */ + {kCLOCK_Osc24M, kCLOCK_SysPll1Pfd0Div2, kCLOCK_SysPll1Pfd1Div2, kCLOCK_VideoPll1Out}, /* Nic Apb */ + {kCLOCK_Osc24M, kCLOCK_SysPll1Pfd0Div2, kCLOCK_SysPll1Pfd1Div2, kCLOCK_VideoPll1Out}, /* Ml Apb */ + {kCLOCK_Osc24M, kCLOCK_SysPll1Pfd0, kCLOCK_SysPll1Pfd1, kCLOCK_SysPll1Pfd2}, /* Ml */ + {kCLOCK_Osc24M, kCLOCK_SysPll1Pfd0, kCLOCK_SysPll1Pfd1, kCLOCK_SysPll1Pfd2}, /* Media Axi */ + {kCLOCK_Osc24M, kCLOCK_SysPll1Pfd0Div2, kCLOCK_SysPll1Pfd1Div2, kCLOCK_VideoPll1Out}, /* Media Apb */ + {kCLOCK_Osc24M, kCLOCK_AudioPll1Out, kCLOCK_VideoPll1Out, kCLOCK_SysPll1Pfd0}, /* Media Ldb */ + {kCLOCK_Osc24M, kCLOCK_AudioPll1Out, kCLOCK_VideoPll1Out, kCLOCK_SysPll1Pfd0}, /* Media Disp Pix */ + {kCLOCK_Osc24M, kCLOCK_AudioPll1Out, kCLOCK_VideoPll1Out, kCLOCK_SysPll1Pfd0}, /* Cam Pix */ + {kCLOCK_Osc24M, kCLOCK_AudioPll1Out, kCLOCK_VideoPll1Out, kCLOCK_SysPll1Pfd0}, /* Mipi Test Byte */ + {kCLOCK_Osc24M, kCLOCK_AudioPll1Out, kCLOCK_VideoPll1Out, kCLOCK_SysPll1Pfd0}, /* Mipi Phy Cfg */ + {kCLOCK_Osc24M, kCLOCK_SysPll1Pfd0, kCLOCK_SysPll1Pfd1, kCLOCK_SysPll1Pfd2}, /* Dram Alt */ + {kCLOCK_Osc24M, kCLOCK_SysPll1Pfd0Div2, kCLOCK_SysPll1Pfd1Div2, kCLOCK_SysPll1Pfd2Div2}, /* Dram Apb */ + {kCLOCK_Osc24M, kCLOCK_SysPll1Pfd0Div2, kCLOCK_SysPll1Pfd1Div2, kCLOCK_VideoPll1Out}, /* Adc */ + {kCLOCK_Osc24M, kCLOCK_AudioPll1Out, kCLOCK_VideoPll1Out, kCLOCK_Ext}, /* Pdm */ + {kCLOCK_Osc24M, kCLOCK_SysPll1Pfd0Div2, kCLOCK_SysPll1Pfd1Div2, kCLOCK_VideoPll1Out}, /* Tstmr1 */ + {kCLOCK_Osc24M, kCLOCK_SysPll1Pfd0Div2, kCLOCK_SysPll1Pfd1Div2, kCLOCK_VideoPll1Out}, /* Tstmr2 */ + {kCLOCK_Osc24M, kCLOCK_AudioPll1Out, kCLOCK_VideoPll1Out, kCLOCK_Ext}, /* Mqs1 */ + {kCLOCK_Osc24M, kCLOCK_AudioPll1Out, kCLOCK_VideoPll1Out, kCLOCK_Ext}, /* Mqs2 */ + {kCLOCK_Osc24M, kCLOCK_SysPll1Pfd0Div2, kCLOCK_SysPll1Pfd1Div2, kCLOCK_SysPll1Pfd2Div2}, /* Audio XCVR */ + {kCLOCK_Osc24M, kCLOCK_AudioPll1Out, kCLOCK_VideoPll1Out, kCLOCK_Ext}, /* Spdif */ + {kCLOCK_Osc24M, kCLOCK_SysPll1Pfd0Div2, kCLOCK_SysPll1Pfd1Div2, kCLOCK_SysPll1Pfd2Div2}, /* Enet */ + {kCLOCK_Osc24M, kCLOCK_SysPll1Pfd0Div2, kCLOCK_SysPll1Pfd1Div2, kCLOCK_VideoPll1Out}, /* Enet Timer1 */ + {kCLOCK_Osc24M, kCLOCK_SysPll1Pfd0Div2, kCLOCK_SysPll1Pfd1Div2, kCLOCK_VideoPll1Out}, /* Enet Timer2 */ + {kCLOCK_Osc24M, kCLOCK_SysPll1Pfd0Div2, kCLOCK_SysPll1Pfd1Div2, kCLOCK_SysPll1Pfd2Div2}, /* Enet Ref */ + {kCLOCK_Osc24M, kCLOCK_SysPll1Pfd0Div2, kCLOCK_SysPll1Pfd1Div2, kCLOCK_VideoPll1Out}, /* Enet Ref Phy */ + {kCLOCK_Osc24M, kCLOCK_SysPll1Pfd0Div2, kCLOCK_SysPll1Pfd1Div2, kCLOCK_VideoPll1Out}, /* I3c1 Slow */ + {kCLOCK_Osc24M, kCLOCK_SysPll1Pfd0Div2, kCLOCK_SysPll1Pfd1Div2, kCLOCK_VideoPll1Out}, /* I3c2 Slow */ + {kCLOCK_Osc24M, kCLOCK_SysPll1Pfd0Div2, kCLOCK_SysPll1Pfd1Div2, kCLOCK_VideoPll1Out}, /* Usb Phy Burunin */ + {kCLOCK_Osc24M, kCLOCK_AudioPll1Out, kCLOCK_VideoPll1Out, kCLOCK_SysPll1Pfd2} /* Pal Came Scan */ +}; + +uint32_t CLOCK_GetIpFreq(clock_root_t name) +{ + clock_name_t clock; + uint32_t mux; + uint32_t div; + + mux = CLOCK_GetRootClockMux(name); + div = CLOCK_GetRootClockDiv(name); + + clock = CLOCK_GetRootClockSource(name, mux); + assert(clock <= kCLOCK_Ext); + + return g_clockSourceFreq[clock] / div; +} diff --git a/bsp/nxp/imx/imx91/drivers/sdk/devices/MIMX9131/drivers/fsl_clock.h b/bsp/nxp/imx/imx91/drivers/sdk/devices/MIMX9131/drivers/fsl_clock.h new file mode 100644 index 00000000000..52d6e812008 --- /dev/null +++ b/bsp/nxp/imx/imx91/drivers/sdk/devices/MIMX9131/drivers/fsl_clock.h @@ -0,0 +1,1279 @@ +/* + * Copyright 2025 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _FSL_CLOCK_H_ +#define _FSL_CLOCK_H_ + +#include "fsl_common.h" + +/*! @brief CLOCK driver version. */ +#define FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(1, 0, 1)) + +/*! + * @brief CCM reg macros to map corresponding registers. + */ +#define CCM_REG_OFF(root, off) (*((volatile uint32_t *)((uintptr_t)(root) + (off)))) +#define CCM_REG(root) CCM_REG_OFF(root, 0U) + +/* Definition for delay API in clock driver, users can redefine it to the real application. */ +#ifndef SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY +#define SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY \ + (250000000UL) /* When using Overdrive Voltage, the maximum frequency of cm33 is 250 MHz */ +#endif + +/*! LPM_SETTING + * 0b000..LPCG will be OFF in any CPU mode. + * 0b001..LPCG will be ON in RUN mode, OFF in WAIT/STOP/SUSPEND mode. + * 0b010..LPCG will be ON in RUN/WAIT mode, OFF in STOP/SUSPEND mode. + * 0b011..LPCG will be ON in RUN/WAIT/STOP mode, OFF in SUSPEND mode. + * 0b100..LPCG will be ON in RUN/WAIT/STOP/SUSPEND mode. + */ +#define CCM_LPCG_LPM_SETTING_0 (0U) +#define CCM_LPCG_LPM_SETTING_1 (1U) +#define CCM_LPCG_LPM_SETTING_2 (2U) +#define CCM_LPCG_LPM_SETTING_3 (3U) +#define CCM_LPCG_LPM_SETTING_4 (4U) + +/******************************************************************************* + * PLL Definitions + ******************************************************************************/ + +/*! @brief PLL initialzation data. */ +typedef struct _fracn_pll_init +{ + uint32_t rdiv; + uint32_t mfi; + uint32_t mfn; + uint32_t mfd; + uint32_t odiv; +} fracn_pll_init_t; + +/*! @brief PLL PFD initialzation data. */ +typedef struct _fracn_pll_pfd_init +{ + uint32_t mfi; + uint32_t mfn; + bool div2_en; +} fracn_pll_pfd_init_t; + +/*! + * @brief PLL init. + * + * @param pll PLL base addr. + * @param pll_cfg PLL initailization data. + */ +static inline void CLOCK_PllInit(PLL_Type *pll, const fracn_pll_init_t *pll_cfg) +{ + /* Bypass PLL */ + pll->CTRL.SET = PLL_CTRL_CLKMUX_BYPASS_MASK; + /* Disable output and PLL */ + pll->CTRL.CLR = PLL_CTRL_CLKMUX_EN_MASK | PLL_CTRL_POWERUP_MASK; + /* Set rdiv, mfi, and odiv */ + pll->DIV.RW = PLL_DIV_RDIV(pll_cfg->rdiv) | PLL_DIV_MFI(pll_cfg->mfi) | PLL_DIV_ODIV(pll_cfg->odiv); + /* Disable spread spectrum modulation */ + pll->SPREAD_SPECTRUM.CLR = PLL_SPREAD_SPECTRUM_ENABLE_MASK; + /* Set mfn and mfd */ + pll->NUMERATOR.RW = PLL_NUMERATOR_MFN(pll_cfg->mfn); + pll->DENOMINATOR.RW = PLL_DENOMINATOR_MFD(pll_cfg->mfd); + + /* Power up for locking */ + pll->CTRL.SET = PLL_CTRL_POWERUP_MASK; + while ((pll->PLL_STATUS & PLL_PLL_STATUS_PLL_LOCK_MASK) == 0UL) + { + } + + /* Enable PLL and clean bypass*/ + pll->CTRL.SET = PLL_CTRL_CLKMUX_EN_MASK; + pll->CTRL.CLR = PLL_CTRL_CLKMUX_BYPASS_MASK; + __DSB(); + __ISB(); +} + +/*! + * @brief PLL PFD init. + * + * @param pll PLL base addr. + * @param pfd_n The PFD index number. + * @param pfd_cfg PLL PFD initailization data. + */ +static inline void CLOCK_PllPfdInit(PLL_Type *pll, uint32_t pfd_n, const fracn_pll_pfd_init_t *pfd_cfg) +{ + /* Bypass DFS*/ + pll->DFS[pfd_n].DFS_CTRL.SET = PLL_DFS_BYPASS_EN_MASK; + /* Disable output and DFS */ + pll->DFS[pfd_n].DFS_CTRL.CLR = PLL_DFS_CLKOUT_EN_MASK | PLL_DFS_ENABLE_MASK; + /* Set mfi and mfn */ + pll->DFS[pfd_n].DFS_DIV.RW = PLL_DFS_MFI(pfd_cfg->mfi) | PLL_DFS_MFN(pfd_cfg->mfn); + /* Enable output and DFS*/ + pll->DFS[pfd_n].DFS_CTRL.SET = PLL_DFS_CLKOUT_EN_MASK; + /* Enable div2 */ + if (pfd_cfg->div2_en) + { + pll->DFS[pfd_n].DFS_CTRL.SET = PLL_DFS_CLKOUT_DIVBY2_EN_MASK; + } + /* Enable DFS for locking*/ + pll->DFS[pfd_n].DFS_CTRL.SET = PLL_DFS_ENABLE_MASK; + while (((pll->DFS_STATUS & PLL_DFS_STATUS_DFS_OK_MASK) & (1UL << pfd_n)) == 0UL) + { + } + /* Clean bypass */ + pll->DFS[pfd_n].DFS_CTRL.CLR = PLL_DFS_BYPASS_EN_MASK; + __DSB(); + __ISB(); +} + +/******************************************************************************* + * Clock Source Definitions + ******************************************************************************/ + +/*! + * @brief Clock name. + */ +typedef enum _clock_name +{ + kCLOCK_Osc24M = 0, /*!< 24MHz Oscillator. */ + kCLOCK_ArmPll = 1, /* ARM PLL */ + kCLOCK_ArmPllOut = 2, /* ARM PLL Out */ + kCLOCK_DramPll = 3, /* DRAM PLL */ + kCLOCK_DramPllOut = 4, /* DRAM PLL Out */ + kCLOCK_SysPll1 = 5, /* SYSTEM PLL1 */ + kCLOCK_SysPll1Pfd0 = 6, /* SYSTEM PLL1 PFD0 */ + kCLOCK_SysPll1Pfd0Div2 = 7, /* SYSTEM PLL1 PFD0 DIV2 */ + kCLOCK_SysPll1Pfd1 = 8, /* SYSTEM PLL1 PFD1 */ + kCLOCK_SysPll1Pfd1Div2 = 9, /* SYSTEM PLL1 PFD1 DIV2 */ + kCLOCK_SysPll1Pfd2 = 10, /* SYSTEM PLL1 PFD2 */ + kCLOCK_SysPll1Pfd2Div2 = 11, /* SYSTEM PLL1 PFD2 DIV2 */ + kCLOCK_AudioPll1 = 12, /* AUDIO PLL1 */ + kCLOCK_AudioPll1Out = 13, /* AUDIO PLL1 Out */ + kCLOCK_VideoPll1 = 14, /* VEDIO PLL1 */ + kCLOCK_VideoPll1Out = 15, /* VEDIO PLL1 Out */ + kCLOCK_Ext = 16, /* Ext */ +} clock_name_t; + +extern const clock_name_t s_clockSourceName[][4]; +/******************************************************************************* + * Clock Root Definitions + ******************************************************************************/ + +/*! @brief Clock root configuration */ +typedef struct _clock_root_config_t +{ + bool clockOff; + uint8_t mux; /*!< See #clock_root_mux_source_t for details. */ + uint8_t div; /*!< it's the actual divider */ +} clock_root_config_t; + +/*! + * @brief Root clock index + */ +typedef enum _clock_root +{ + kCLOCK_Root_A55Periph = 0, /*!< CLOCK Root Arm A55 Periph. */ + kCLOCK_Root_A55MtrBus = 1, /*!< CLOCK Root Arm A55 MTR BUS. */ + kCLOCK_Root_A55 = 2, /*!< CLOCK Root Arm A55. */ + kCLOCK_Root_M33 = 3, /*!< CLOCK Root M33. */ + kCLOCK_Root_Sentinel = 4, /*!< CLOCK Root Sentinel. */ + kCLOCK_Root_BusWakeup = 5, /*!< CLOCK Root Bus Wakeup. */ + kCLOCK_Root_BusAon = 6, /*!< CLOCK Root Bus Aon. */ + kCLOCK_Root_WakeupAxi = 7, /*!< CLOCK Root Wakeup Axi. */ + kCLOCK_Root_SwoTrace = 8, /*!< CLOCK Root Swo Trace. */ + kCLOCK_Root_M33Systick = 9, /*!< CLOCK Root M33 Systick. */ + kCLOCK_Root_Flexio1 = 10, /*!< CLOCK Root Flexio1. */ + kCLOCK_Root_Flexio2 = 11, /*!< CLOCK Root Flexio2. */ + kCLOCK_Root_Lpit1 = 12, /*!< CLOCK Root Lpit1. */ + kCLOCK_Root_Lpit2 = 13, /*!< CLOCK Root Lpit2. */ + kCLOCK_Root_Lptmr1 = 14, /*!< CLOCK Root Lptmr1. */ + kCLOCK_Root_Lptmr2 = 15, /*!< CLOCK Root Lptmr2. */ + kCLOCK_Root_Tpm1 = 16, /*!< CLOCK Root Tpm1. */ + kCLOCK_Root_Tpm2 = 17, /*!< CLOCK Root Tpm2. */ + kCLOCK_Root_Tpm3 = 18, /*!< CLOCK Root Tpm3. */ + kCLOCK_Root_Tpm4 = 19, /*!< CLOCK Root Tpm4. */ + kCLOCK_Root_Tpm5 = 20, /*!< CLOCK Root Tpm5. */ + kCLOCK_Root_Tpm6 = 21, /*!< CLOCK Root Tpm6. */ + kCLOCK_Root_Flexspi1 = 22, /*!< CLOCK Root Flexspi1. */ + kCLOCK_Root_Can1 = 23, /*!< CLOCK Root Can1. */ + kCLOCK_Root_Can2 = 24, /*!< CLOCK Root Can2. */ + kCLOCK_Root_Lpuart1 = 25, /*!< CLOCK Root Lpuart1. */ + kCLOCK_Root_Lpuart2 = 26, /*!< CLOCK Root Lpuart2. */ + kCLOCK_Root_Lpuart3 = 27, /*!< CLOCK Root Lpuart3. */ + kCLOCK_Root_Lpuart4 = 28, /*!< CLOCK Root Lpuart4. */ + kCLOCK_Root_Lpuart5 = 29, /*!< CLOCK Root Lpuart5. */ + kCLOCK_Root_Lpuart6 = 30, /*!< CLOCK Root Lpuart6. */ + kCLOCK_Root_Lpuart7 = 31, /*!< CLOCK Root Lpuart7. */ + kCLOCK_Root_Lpuart8 = 32, /*!< CLOCK Root Lpuart8. */ + kCLOCK_Root_Lpi2c1 = 33, /*!< CLOCK Root Lpi2c1. */ + kCLOCK_Root_Lpi2c2 = 34, /*!< CLOCK Root Lpi2c2. */ + kCLOCK_Root_Lpi2c3 = 35, /*!< CLOCK Root Lpi2c3. */ + kCLOCK_Root_Lpi2c4 = 36, /*!< CLOCK Root Lpi2c4. */ + kCLOCK_Root_Lpi2c5 = 37, /*!< CLOCK Root Lpi2c5. */ + kCLOCK_Root_Lpi2c6 = 38, /*!< CLOCK Root Lpi2c6. */ + kCLOCK_Root_Lpi2c7 = 39, /*!< CLOCK Root Lpi2c7. */ + kCLOCK_Root_Lpi2c8 = 40, /*!< CLOCK Root Lpi2c8. */ + kCLOCK_Root_Lpspi1 = 41, /*!< CLOCK Root Lpspi1. */ + kCLOCK_Root_Lpspi2 = 42, /*!< CLOCK Root Lpspi2. */ + kCLOCK_Root_Lpspi3 = 43, /*!< CLOCK Root Lpspi3. */ + kCLOCK_Root_Lpspi4 = 44, /*!< CLOCK Root Lpspi4. */ + kCLOCK_Root_Lpspi5 = 45, /*!< CLOCK Root Lpspi5. */ + kCLOCK_Root_Lpspi6 = 46, /*!< CLOCK Root Lpspi6. */ + kCLOCK_Root_Lpspi7 = 47, /*!< CLOCK Root Lpspi7. */ + kCLOCK_Root_Lpspi8 = 48, /*!< CLOCK Root Lpspi8. */ + kCLOCK_Root_I3c1 = 49, /*!< CLOCK Root I3c1. */ + kCLOCK_Root_I3c2 = 50, /*!< CLOCK Root I3c2. */ + kCLOCK_Root_Usdhc1 = 51, /*!< CLOCK Root Usdhc1. */ + kCLOCK_Root_Usdhc2 = 52, /*!< CLOCK Root Usdhc2. */ + kCLOCK_Root_Usdhc3 = 53, /*!< CLOCK Root Usdhc3. */ + kCLOCK_Root_Sai1 = 54, /*!< CLOCK Root Sai1. */ + kCLOCK_Root_Sai2 = 55, /*!< CLOCK Root Sai2. */ + kCLOCK_Root_Sai3 = 56, /*!< CLOCK Root Sai3. */ + kCLOCK_Root_CcmCko1 = 57, /*!< CLOCK Root Ccm Cko1. */ + kCLOCK_Root_CcmCko2 = 58, /*!< CLOCK Root Ccm Cko2. */ + kCLOCK_Root_CcmCko3 = 59, /*!< CLOCK Root Ccm Cko3. */ + kCLOCK_Root_CcmCko4 = 60, /*!< CLOCK Root Ccm Cko4. */ + kCLOCK_Root_Hsio = 61, /*!< CLOCK Root Hsio. */ + kCLOCK_Root_HsioUsbTest60M = 62, /*!< CLOCK Root Hsio Usb Test 60M. */ + kCLOCK_Root_HsioAcscan80M = 63, /*!< CLOCK Root Hsio Acscan 80M. */ + kCLOCK_Root_HsioAcscan480M = 64, /*!< CLOCK Root Hsio Acscan 480M. */ + kCLOCK_Root_Nic = 65, /*!< CLOCK Root Nic. */ + kCLOCK_Root_NicApb = 66, /*!< CLOCK Root Nic Apb. */ + kCLOCK_Root_MlApb = 67, /*!< CLOCK Root Ml Apb. */ + kCLOCK_Root_Ml = 68, /*!< CLOCK Root Ml. */ + kCLOCK_Root_MediaAxi = 69, /*!< CLOCK Root Media Axi. */ + kCLOCK_Root_MediaApb = 70, /*!< CLOCK Root Media Apb. */ + kCLOCK_Root_MediaLdb = 71, /*!< CLOCK Root Media Ldb. */ + kCLOCK_Root_MediaDispPix = 72, /*!< CLOCK Root Media Disp Pix. */ + kCLOCK_Root_CamPix = 73, /*!< CLOCK Root Cam Pix. */ + kCLOCK_Root_MipiTestByte = 74, /*!< CLOCK Root Mipi Test Byte. */ + kCLOCK_Root_MipiPhyCfg = 75, /*!< CLOCK Root Mipi Phy Cfg. */ + kCLOCK_Root_DramAlt = 76, /*!< CLOCK Root Dram Alt. */ + kCLOCK_Root_DramApb = 77, /*!< CLOCK Root Dram Apb. */ + kCLOCK_Root_Adc = 78, /*!< CLOCK Root Adc. */ + kCLOCK_Root_Pdm = 79, /*!< CLOCK Root Pdm. */ + kCLOCK_Root_Tstmr1 = 80, /*!< CLOCK Root Tstmr1. */ + kCLOCK_Root_Tstmr2 = 81, /*!< CLOCK Root Tstmr2. */ + kCLOCK_Root_Mqs1 = 82, /*!< CLOCK Root MQS1. */ + kCLOCK_Root_Mqs2 = 83, /*!< CLOCK Root MQS2. */ + kCLOCK_Root_AudioXCVR = 84, /*!< CLOCK Root Audio XCVR. */ + kCLOCK_Root_Spdif = 85, /*!< CLOCK Root Spdif. */ + kCLOCK_Root_Enet = 86, /*!< CLOCK Root Enet. */ + kCLOCK_Root_EnetTimer1 = 87, /*!< CLOCK Root Enet Timer1. */ + kCLOCK_Root_EnetTimer2 = 88, /*!< CLOCK Root Enet Timer2. */ + kCLOCK_Root_EnetRef = 89, /*!< CLOCK Root Enet Ref. */ + kCLOCK_Root_EnetRefPhy = 90, /*!< CLOCK Root Enet Ref Phy. */ + kCLOCK_Root_I3c1Slow = 91, /*!< CLOCK Root I3c1Slow. */ + kCLOCK_Root_I3c2Slow = 92, /*!< CLOCK Root I3c2Slow. */ + kCLOCK_Root_UsbPhyBurunin = 93, /*!< CLOCK Root Usb Phy Burunin. */ + kCLOCK_Root_PalCameScan = 94, /*!< CLOCK Root Pal Came Scan. */ +} clock_root_t; + +/*! + * @brief The enumerator of clock roots' clock source mux value. + */ +typedef enum _clock_root_mux_source +{ + /* ARM A55 Periph */ + kCLOCK_A55PERIPH_ClockRoot_MuxOsc24M = 0U, + kCLOCK_A55PERIPH_ClockRoot_MuxSysPll1Pfd0 = 1U, + kCLOCK_A55PERIPH_ClockRoot_MuxSysPll1Pfd1 = 2U, + kCLOCK_A55PERIPH_ClockRoot_MuxSysPll1Pfd2 = 3U, + + /* ARM A55 MTR BUS */ + kCLOCK_A55MTRBUS_ClockRoot_MuxOsc24M = 0U, + kCLOCK_A55MTRBUS_ClockRoot_MuxSysPll1Pfd0Div2 = 1U, + kCLOCK_A55MTRBUS_ClockRoot_MuxSysPll1Pfd1Div2 = 2U, + kCLOCK_A55MTRBUS_ClockRoot_MuxVideoPll1Out = 3U, + + /* ARM A55 */ + kCLOCK_A55_ClockRoot_MuxOsc24M = 0U, + kCLOCK_A55_ClockRoot_MuxSysPll1Pfd0 = 1U, + kCLOCK_A55_ClockRoot_MuxSysPll1Pfd1 = 2U, + kCLOCK_A55_ClockRoot_MuxSysPll1Pfd2 = 3U, + + /* M33 */ + kCLOCK_M33_ClockRoot_MuxOsc24M = 0U, + kCLOCK_M33_ClockRoot_MuxSysPll1Pfd0Div2 = 1U, + kCLOCK_M33_ClockRoot_MuxSysPll1Pfd1Div2 = 2U, + kCLOCK_M33_ClockRoot_MuxVideoPll1Out = 3U, + + /* Sentinel */ + kCLOCK_SENTINEL_ClockRoot_MuxOsc24M = 0U, + kCLOCK_SENTINEL_ClockRoot_MuxSysPll1Pfd0Div2 = 1U, + kCLOCK_SENTINEL_ClockRoot_MuxSysPll1Pfd1Div2 = 2U, + kCLOCK_SENTINEL_ClockRoot_MuxVideoPll1Out = 3U, + + /* Bus Wakeup */ + kCLOCK_BUSWAKEUP_ClockRoot_MuxOsc24M = 0U, + kCLOCK_BUSWAKEUP_ClockRoot_MuxSysPll1Pfd0Div2 = 1U, + kCLOCK_BUSWAKEUP_ClockRoot_MuxSysPll1Pfd1Div2 = 2U, + kCLOCK_BUSWAKEUP_ClockRoot_MuxVideoPll1Out = 3U, + + /* Bus Aon */ + kCLOCK_BUSAON_ClockRoot_MuxOsc24M = 0U, + kCLOCK_BUSAON_ClockRoot_MuxSysPll1Pfd0Div2 = 1U, + kCLOCK_BUSAON_ClockRoot_MuxSysPll1Pfd1Div2 = 2U, + kCLOCK_BUSAON_ClockRoot_MuxVideoPll1Out = 3U, + + /* Wakeup Axi */ + kCLOCK_WAKEUPAXI_ClockRoot_MuxOsc24M = 0U, + kCLOCK_WAKEUPAXI_ClockRoot_MuxSysPll1Pfd0 = 1U, + kCLOCK_WAKEUPAXI_ClockRoot_MuxSysPll1Pfd1 = 2U, + kCLOCK_WAKEUPAXI_ClockRoot_MuxSysPll1Pfd2 = 3U, + + /* Swo Trace */ + kCLOCK_SWOTRACE_ClockRoot_MuxOsc24M = 0U, + kCLOCK_SWOTRACE_ClockRoot_MuxSysPll1Pfd0Div2 = 1U, + kCLOCK_SWOTRACE_ClockRoot_MuxSysPll1Pfd1Div2 = 2U, + kCLOCK_SWOTRACE_ClockRoot_MuxVideoPll1Out = 3U, + + /* M33 Systick */ + kCLOCK_M33SYSTICK_ClockRoot_MuxOsc24M = 0U, + kCLOCK_M33SYSTICK_ClockRoot_MuxSysPll1Pfd0Div2 = 1U, + kCLOCK_M33SYSTICK_ClockRoot_MuxSysPll1Pfd1Div2 = 2U, + kCLOCK_M33SYSTICK_ClockRoot_MuxVideoPll1Out = 3U, + + /* Flexio1 */ + kCLOCK_FLEXIO1_ClockRoot_MuxOsc24M = 0U, + kCLOCK_FLEXIO1_ClockRoot_MuxSysPll1Pfd0Div2 = 1U, + kCLOCK_FLEXIO1_ClockRoot_MuxSysPll1Pfd1Div2 = 2U, + kCLOCK_FLEXIO1_ClockRoot_MuxVideoPll1Out = 3U, + + /* Flexio2 */ + kCLOCK_FLEXIO2_ClockRoot_MuxOsc24M = 0U, + kCLOCK_FLEXIO2_ClockRoot_MuxSysPll1Pfd0Div2 = 1U, + kCLOCK_FLEXIO2_ClockRoot_MuxSysPll1Pfd1Div2 = 2U, + kCLOCK_FLEXIO2_ClockRoot_MuxVideoPll1Out = 3U, + + /* Lpit1 */ + kCLOCK_LPIT1_ClockRoot_MuxOsc24M = 0U, + kCLOCK_LPIT1_ClockRoot_MuxSysPll1Pfd0Div2 = 1U, + kCLOCK_LPIT1_ClockRoot_MuxSysPll1Pfd1Div2 = 2U, + kCLOCK_LPIT1_ClockRoot_MuxVideoPll1Out = 3U, + + /* Lpit2 */ + kCLOCK_LPIT2_ClockRoot_MuxOsc24M = 0U, + kCLOCK_LPIT2_ClockRoot_MuxSysPll1Pfd0Div2 = 1U, + kCLOCK_LPIT2_ClockRoot_MuxSysPll1Pfd1Div2 = 2U, + kCLOCK_LPIT2_ClockRoot_MuxVideoPll1Out = 3U, + + /* Lptmr1 */ + kCLOCK_LPTMR1_ClockRoot_MuxOsc24M = 0U, + kCLOCK_LPTMR1_ClockRoot_MuxSysPll1Pfd0Div2 = 1U, + kCLOCK_LPTMR1_ClockRoot_MuxSysPll1Pfd1Div2 = 2U, + kCLOCK_LPTMR1_ClockRoot_MuxVideoPll1Out = 3U, + + /* Lptmr2 */ + kCLOCK_LPTMR2_ClockRoot_MuxOsc24M = 0U, + kCLOCK_LPTMR2_ClockRoot_MuxSysPll1Pfd0Div2 = 1U, + kCLOCK_LPTMR2_ClockRoot_MuxSysPll1Pfd1Div2 = 2U, + kCLOCK_LPTMR2_ClockRoot_MuxVideoPll1Out = 3U, + + /* Tpm1 */ + kCLOCK_TPM1_ClockRoot_MuxOsc24M = 0U, + kCLOCK_TPM1_ClockRoot_MuxSysPll1Pfd0 = 1U, + kCLOCK_TPM1_ClockRoot_MuxAudioPll1Out = 2U, + kCLOCK_TPM1_ClockRoot_MuxExt = 3U, + + /* Tpm2 */ + kCLOCK_TPM2_ClockRoot_MuxOsc24M = 0U, + kCLOCK_TPM2_ClockRoot_MuxSysPll1Pfd0 = 1U, + kCLOCK_TPM2_ClockRoot_MuxAudioPll1Out = 2U, + kCLOCK_TPM2_ClockRoot_MuxExt = 3U, + + /* Tpm3 */ + kCLOCK_TPM3_ClockRoot_MuxOsc24M = 0U, + kCLOCK_TPM3_ClockRoot_MuxSysPll1Pfd0 = 1U, + kCLOCK_TPM3_ClockRoot_MuxAudioPll1Out = 2U, + kCLOCK_TPM3_ClockRoot_MuxExt = 3U, + + /* Tpm4 */ + kCLOCK_TPM4_ClockRoot_MuxOsc24M = 0U, + kCLOCK_TPM4_ClockRoot_MuxSysPll1Pfd0 = 1U, + kCLOCK_TPM4_ClockRoot_MuxAudioPll1Out = 2U, + kCLOCK_TPM4_ClockRoot_MuxExt = 3U, + + /* Tpm5 */ + kCLOCK_TPM5_ClockRoot_MuxOsc24M = 0U, + kCLOCK_TPM5_ClockRoot_MuxSysPll1Pfd0 = 1U, + kCLOCK_TPM5_ClockRoot_MuxAudioPll1Out = 2U, + kCLOCK_TPM5_ClockRoot_MuxExt = 3U, + + /* Tpm6 */ + kCLOCK_TPM6_ClockRoot_MuxOsc24M = 0U, + kCLOCK_TPM6_ClockRoot_MuxSysPll1Pfd0 = 1U, + kCLOCK_TPM6_ClockRoot_MuxAudioPll1Out = 2U, + kCLOCK_TPM6_ClockRoot_MuxExt = 3U, + + /* Flexspi1 */ + kCLOCK_FLEXSPI1_ClockRoot_MuxOsc24M = 0U, + kCLOCK_FLEXSPI1_ClockRoot_MuxSysPll1Pfd0 = 1U, + kCLOCK_FLEXSPI1_ClockRoot_MuxSysPll1Pfd1 = 2U, + kCLOCK_FLEXSPI1_ClockRoot_MuxSysPll1Pfd2 = 3U, + + /* Can1 */ + kCLOCK_CAN1_ClockRoot_MuxOsc24M = 0U, + kCLOCK_CAN1_ClockRoot_MuxSysPll1Pfd0Div2 = 1U, + kCLOCK_CAN1_ClockRoot_MuxSysPll1Pfd1Div2 = 2U, + kCLOCK_CAN1_ClockRoot_MuxVideoPll1Out = 3U, + + /* Can2 */ + kCLOCK_CAN2_ClockRoot_MuxOsc24M = 0U, + kCLOCK_CAN2_ClockRoot_MuxSysPll1Pfd0Div2 = 1U, + kCLOCK_CAN2_ClockRoot_MuxSysPll1Pfd1Div2 = 2U, + kCLOCK_CAN2_ClockRoot_MuxVideoPll1Out = 3U, + + /* Lpuart1 */ + kCLOCK_LPUART1_ClockRoot_MuxOsc24M = 0U, + kCLOCK_LPUART1_ClockRoot_MuxSysPll1Pfd0Div2 = 1U, + kCLOCK_LPUART1_ClockRoot_MuxSysPll1Pfd1Div2 = 2U, + kCLOCK_LPUART1_ClockRoot_MuxVideoPll1Out = 3U, + + /* Lpuart2 */ + kCLOCK_LPUART2_ClockRoot_MuxOsc24M = 0U, + kCLOCK_LPUART2_ClockRoot_MuxSysPll1Pfd0Div2 = 1U, + kCLOCK_LPUART2_ClockRoot_MuxSysPll1Pfd1Div2 = 2U, + kCLOCK_LPUART2_ClockRoot_MuxVideoPll1Out = 3U, + + /* Lpuart3 */ + kCLOCK_LPUART3_ClockRoot_MuxOsc24M = 0U, + kCLOCK_LPUART3_ClockRoot_MuxSysPll1Pfd0Div2 = 1U, + kCLOCK_LPUART3_ClockRoot_MuxSysPll1Pfd1Div2 = 2U, + kCLOCK_LPUART3_ClockRoot_MuxVideoPll1Out = 3U, + + /* Lpuart4 */ + kCLOCK_LPUART4_ClockRoot_MuxOsc24M = 0U, + kCLOCK_LPUART4_ClockRoot_MuxSysPll1Pfd0Div2 = 1U, + kCLOCK_LPUART4_ClockRoot_MuxSysPll1Pfd1Div2 = 2U, + kCLOCK_LPUART4_ClockRoot_MuxVideoPll1Out = 3U, + + /* Lpuart5 */ + kCLOCK_LPUART5_ClockRoot_MuxOsc24M = 0U, + kCLOCK_LPUART5_ClockRoot_MuxSysPll1Pfd0Div2 = 1U, + kCLOCK_LPUART5_ClockRoot_MuxSysPll1Pfd1Div2 = 2U, + kCLOCK_LPUART5_ClockRoot_MuxVideoPll1Out = 3U, + + /* Lpuart6 */ + kCLOCK_LPUART6_ClockRoot_MuxOsc24M = 0U, + kCLOCK_LPUART6_ClockRoot_MuxSysPll1Pfd0Div2 = 1U, + kCLOCK_LPUART6_ClockRoot_MuxSysPll1Pfd1Div2 = 2U, + kCLOCK_LPUART6_ClockRoot_MuxVideoPll1Out = 3U, + + /* Lpuart7 */ + kCLOCK_LPUART7_ClockRoot_MuxOsc24M = 0U, + kCLOCK_LPUART7_ClockRoot_MuxSysPll1Pfd0Div2 = 1U, + kCLOCK_LPUART7_ClockRoot_MuxSysPll1Pfd1Div2 = 2U, + kCLOCK_LPUART7_ClockRoot_MuxVideoPll1Out = 3U, + + /* Lpuart8 */ + kCLOCK_LPUART8_ClockRoot_MuxOsc24M = 0U, + kCLOCK_LPUART8_ClockRoot_MuxSysPll1Pfd0Div2 = 1U, + kCLOCK_LPUART8_ClockRoot_MuxSysPll1Pfd1Div2 = 2U, + kCLOCK_LPUART8_ClockRoot_MuxVideoPll1Out = 3U, + + /* Lpi2c1 */ + kCLOCK_LPI2C1_ClockRoot_MuxOsc24M = 0U, + kCLOCK_LPI2C1_ClockRoot_MuxSysPll1Pfd0Div2 = 1U, + kCLOCK_LPI2C1_ClockRoot_MuxSysPll1Pfd1Div2 = 2U, + kCLOCK_LPI2C1_ClockRoot_MuxVideoPll1Out = 3U, + + /* Lpi2c2 */ + kCLOCK_LPI2C2_ClockRoot_MuxOsc24M = 0U, + kCLOCK_LPI2C2_ClockRoot_MuxSysPll1Pfd0Div2 = 1U, + kCLOCK_LPI2C2_ClockRoot_MuxSysPll1Pfd1Div2 = 2U, + kCLOCK_LPI2C2_ClockRoot_MuxVideoPll1Out = 3U, + + /* Lpi2c3 */ + kCLOCK_LPI2C3_ClockRoot_MuxOsc24M = 0U, + kCLOCK_LPI2C3_ClockRoot_MuxSysPll1Pfd0Div2 = 1U, + kCLOCK_LPI2C3_ClockRoot_MuxSysPll1Pfd1Div2 = 2U, + kCLOCK_LPI2C3_ClockRoot_MuxVideoPll1Out = 3U, + + /* Lpi2c4 */ + kCLOCK_LPI2C4_ClockRoot_MuxOsc24M = 0U, + kCLOCK_LPI2C4_ClockRoot_MuxSysPll1Pfd0Div2 = 1U, + kCLOCK_LPI2C4_ClockRoot_MuxSysPll1Pfd1Div2 = 2U, + kCLOCK_LPI2C4_ClockRoot_MuxVideoPll1Out = 3U, + + /* Lpi2c5 */ + kCLOCK_LPI2C5_ClockRoot_MuxOsc24M = 0U, + kCLOCK_LPI2C5_ClockRoot_MuxSysPll1Pfd0Div2 = 1U, + kCLOCK_LPI2C5_ClockRoot_MuxSysPll1Pfd1Div2 = 2U, + kCLOCK_LPI2C5_ClockRoot_MuxVideoPll1Out = 3U, + + /* Lpi2c6 */ + kCLOCK_LPI2C6_ClockRoot_MuxOsc24M = 0U, + kCLOCK_LPI2C6_ClockRoot_MuxSysPll1Pfd0Div2 = 1U, + kCLOCK_LPI2C6_ClockRoot_MuxSysPll1Pfd1Div2 = 2U, + kCLOCK_LPI2C6_ClockRoot_MuxVideoPll1Out = 3U, + + /* Lpi2c7 */ + kCLOCK_LPI2C7_ClockRoot_MuxOsc24M = 0U, + kCLOCK_LPI2C7_ClockRoot_MuxSysPll1Pfd0Div2 = 1U, + kCLOCK_LPI2C7_ClockRoot_MuxSysPll1Pfd1Div2 = 2U, + kCLOCK_LPI2C7_ClockRoot_MuxVideoPll1Out = 3U, + + /* Lpi2c8 */ + kCLOCK_LPI2C8_ClockRoot_MuxOsc24M = 0U, + kCLOCK_LPI2C8_ClockRoot_MuxSysPll1Pfd0Div2 = 1U, + kCLOCK_LPI2C8_ClockRoot_MuxSysPll1Pfd1Div2 = 2U, + kCLOCK_LPI2C8_ClockRoot_MuxVideoPll1Out = 3U, + + /* Lpspi1 */ + kCLOCK_LPSPI1_ClockRoot_MuxOsc24M = 0U, + kCLOCK_LPSPI1_ClockRoot_MuxSysPll1Pfd0Div2 = 1U, + kCLOCK_LPSPI1_ClockRoot_MuxSysPll1Pfd1Div2 = 2U, + kCLOCK_LPSPI1_ClockRoot_MuxVideoPll1Out = 3U, + + /* Lpspi2 */ + kCLOCK_LPSPI2_ClockRoot_MuxOsc24M = 0U, + kCLOCK_LPSPI2_ClockRoot_MuxSysPll1Pfd0Div2 = 1U, + kCLOCK_LPSPI2_ClockRoot_MuxSysPll1Pfd1Div2 = 2U, + kCLOCK_LPSPI2_ClockRoot_MuxVideoPll1Out = 3U, + + /* Lpspi3 */ + kCLOCK_LPSPI3_ClockRoot_MuxOsc24M = 0U, + kCLOCK_LPSPI3_ClockRoot_MuxSysPll1Pfd0Div2 = 1U, + kCLOCK_LPSPI3_ClockRoot_MuxSysPll1Pfd1Div2 = 2U, + kCLOCK_LPSPI3_ClockRoot_MuxVideoPll1Out = 3U, + + /* Lpspi4 */ + kCLOCK_LPSPI4_ClockRoot_MuxOsc24M = 0U, + kCLOCK_LPSPI4_ClockRoot_MuxSysPll1Pfd0Div2 = 1U, + kCLOCK_LPSPI4_ClockRoot_MuxSysPll1Pfd1Div2 = 2U, + kCLOCK_LPSPI4_ClockRoot_MuxVideoPll1Out = 3U, + + /* Lpispi5 */ + kCLOCK_LPSPI5_ClockRoot_MuxOsc24M = 0U, + kCLOCK_LPSPI5_ClockRoot_MuxSysPll1Pfd0Div2 = 1U, + kCLOCK_LPSPI5_ClockRoot_MuxSysPll1Pfd1Div2 = 2U, + kCLOCK_LPSPI5_ClockRoot_MuxVideoPll1Out = 3U, + + /* Lpspi6 */ + kCLOCK_LPSPI6_ClockRoot_MuxOsc24M = 0U, + kCLOCK_LPSPI6_ClockRoot_MuxSysPll1Pfd0Div2 = 1U, + kCLOCK_LPSPI6_ClockRoot_MuxSysPll1Pfd1Div2 = 2U, + kCLOCK_LPSPI6_ClockRoot_MuxVideoPll1Out = 3U, + + /* Lpspi7 */ + kCLOCK_LPSPI7_ClockRoot_MuxOsc24M = 0U, + kCLOCK_LPSPI7_ClockRoot_MuxSysPll1Pfd0Div2 = 1U, + kCLOCK_LPSPI7_ClockRoot_MuxSysPll1Pfd1Div2 = 2U, + kCLOCK_LPSPI7_ClockRoot_MuxVideoPll1Out = 3U, + + /* Lpspi8 */ + kCLOCK_LPSPI8_ClockRoot_MuxOsc24M = 0U, + kCLOCK_LPSPI8_ClockRoot_MuxSysPll1Pfd0Div2 = 1U, + kCLOCK_LPSPI8_ClockRoot_MuxSysPll1Pfd1Div2 = 2U, + kCLOCK_LPSPI8_ClockRoot_MuxVideoPll1Out = 3U, + + /* I3c1 */ + kCLOCK_I3C1_ClockRoot_MuxOsc24M = 0U, + kCLOCK_I3C1_ClockRoot_MuxSysPll1Pfd0Div2 = 1U, + kCLOCK_I3C1_ClockRoot_MuxSysPll1Pfd1Div2 = 2U, + kCLOCK_I3C1_ClockRoot_MuxVideoPll1Out = 3U, + + /* I3c2 */ + kCLOCK_I3C2_ClockRoot_MuxOsc24M = 0U, + kCLOCK_I3C2_ClockRoot_MuxSysPll1Pfd0Div2 = 1U, + kCLOCK_I3C2_ClockRoot_MuxSysPll1Pfd1Div2 = 2U, + kCLOCK_I3C2_ClockRoot_MuxVideoPll1Out = 3U, + + /* Usdhc1 */ + kCLOCK_Usdhc1_ClockRoot_MuxOsc24M = 0U, + kCLOCK_Usdhc1_ClockRoot_MuxSysPll1Pfd0 = 1U, + kCLOCK_Usdhc1_ClockRoot_MuxSysPll1Pfd1 = 2U, + kCLOCK_Usdhc1_ClockRoot_MuxSysPll1Pfd2 = 3U, + + /* Usdhc2 */ + kCLOCK_Usdhc2_ClockRoot_MuxOsc24M = 0U, + kCLOCK_Usdhc2_ClockRoot_MuxSysPll1Pfd0 = 1U, + kCLOCK_Usdhc2_ClockRoot_MuxSysPll1Pfd1 = 2U, + kCLOCK_Usdhc2_ClockRoot_MuxSysPll1Pfd2 = 3U, + + /* Usdhc3 */ + kCLOCK_Usdhc3_ClockRoot_MuxOsc24M = 0U, + kCLOCK_Usdhc3_ClockRoot_MuxSysPll1Pfd0 = 1U, + kCLOCK_Usdhc3_ClockRoot_MuxSysPll1Pfd1 = 2U, + kCLOCK_Usdhc3_ClockRoot_MuxSysPll1Pfd2 = 3U, + + /* Sai1 */ + kCLOCK_SAI1_ClockRoot_MuxOsc24M = 0U, + kCLOCK_SAI1_ClockRoot_MuxAudioPll1Out = 1U, + kCLOCK_SAI1_ClockRoot_MuxVideoPll1Out = 2U, + kCLOCK_SAI1_ClockRoot_MuxExt = 3U, + + /* Sai2 */ + kCLOCK_SAI2_ClockRoot_MuxOsc24M = 0U, + kCLOCK_SAI2_ClockRoot_MuxAudioPll1Out = 1U, + kCLOCK_SAI2_ClockRoot_MuxVideoPll1Out = 2U, + kCLOCK_SAI2_ClockRoot_MuxExt = 3U, + + /* Sai3 */ + kCLOCK_SAI3_ClockRoot_MuxOsc24M = 0U, + kCLOCK_SAI3_ClockRoot_MuxAudioPll1Out = 1U, + kCLOCK_SAI3_ClockRoot_MuxVideoPll1Out = 2U, + kCLOCK_SAI3_ClockRoot_MuxExt = 3U, + + /* Ccm Cko1 */ + kCLOCK_CCMCKO1_ClockRoot_MuxOsc24M = 0U, + kCLOCK_CCMCKO1_ClockRoot_MuxSysPll1Pfd0 = 1U, + kCLOCK_CCMCKO1_ClockRoot_MuxSysPll1Pfd1 = 2U, + kCLOCK_CCMCKO1_ClockRoot_MuxAudioPll1Out = 3U, + + /* Ccm Cko2 */ + kCLOCK_CCMCKO2_ClockRoot_MuxOsc24M = 0U, + kCLOCK_CCMCKO2_ClockRoot_MuxSysPll1Pfd0 = 1U, + kCLOCK_CCMCKO2_ClockRoot_MuxSysPll1Pfd1 = 2U, + kCLOCK_CCMCKO2_ClockRoot_MuxVideoPll1Out = 3U, + + /* Ccm Cko3 */ + kCLOCK_CCMCKO3_ClockRoot_MuxOsc24M = 0U, + kCLOCK_CCMCKO3_ClockRoot_MuxSysPll1Pfd0 = 1U, + kCLOCK_CCMCKO3_ClockRoot_MuxSysPll1Pfd1 = 2U, + kCLOCK_CCMCKO3_ClockRoot_MuxAudioPll1Out = 3U, + + /* Ccm Cko4 */ + kCLOCK_CCMCKO4_ClockRoot_MuxOsc24M = 0U, + kCLOCK_CCMCKO4_ClockRoot_MuxSysPll1Pfd0 = 1U, + kCLOCK_CCMCKO4_ClockRoot_MuxSysPll1Pfd1 = 2U, + kCLOCK_CCMCKO4_ClockRoot_MuxVideoPll1Out = 3U, + + /* Hsio */ + kCLOCK_HSIO_ClockRoot_MuxOsc24M = 0U, + kCLOCK_HSIO_ClockRoot_MuxSysPll1Pfd0Div2 = 1U, + kCLOCK_HSIO_ClockRoot_MuxSysPll1Pfd1Div2 = 2U, + kCLOCK_HSIO_ClockRoot_MuxVideoPll1Out = 3U, + + /* Hsio Usb Test 60M */ + kCLOCK_HSIOUSBTEST60M_ClockRoot_MuxOsc24M = 0U, + kCLOCK_HSIOUSBTEST60M_ClockRoot_MuxSysPll1Pfd0Div2 = 1U, + kCLOCK_HSIOUSBTEST60M_ClockRoot_MuxSysPll1Pfd1Div2 = 2U, + kCLOCK_HSIOUSBTEST60M_ClockRoot_MuxVideoPll1Out = 3U, + + /* Hsio Acscan 80M */ + kCLOCK_HSIOACSCAN80M_ClockRoot_MuxOsc24M = 0U, + kCLOCK_HSIOACSCAN80M_ClockRoot_MuxSysPll1Pfd0Div2 = 1U, + kCLOCK_HSIOACSCAN80M_ClockRoot_MuxSysPll1Pfd1Div2 = 2U, + kCLOCK_HSIOACSCAN80M_ClockRoot_MuxVideoPll1Out = 3U, + + /* Hsio Acscan 480M */ + kCLOCK_HSIOACSCAN480M_ClockRoot_MuxOsc24M = 0U, + kCLOCK_HSIOACSCAN480M_ClockRoot_MuxSysPll1Pfd0Div2 = 1U, + kCLOCK_HSIOACSCAN480M_ClockRoot_MuxSysPll1Pfd1Div2 = 2U, + kCLOCK_HSIOACSCAN480M_ClockRoot_MuxVideoPll1Out = 3U, + + /* Nic */ + kCLOCK_NIC_ClockRoot_MuxOsc24M = 0U, + kCLOCK_NIC_ClockRoot_MuxSysPll1Pfd0 = 1U, + kCLOCK_NIC_ClockRoot_MuxSysPll1Pfd1 = 2U, + kCLOCK_NIC_ClockRoot_MuxSysPll1Pfd2 = 3U, + + /* Nic Apb */ + kCLOCK_NICAPB_ClockRoot_MuxOsc24M = 0U, + kCLOCK_NICAPB_ClockRoot_MuxSysPll1Pfd0Div2 = 1U, + kCLOCK_NICAPB_ClockRoot_MuxSysPll1Pfd1Div2 = 2U, + kCLOCK_NICAPB_ClockRoot_MuxVideoPll1Out = 3U, + + /* Ml Apb */ + kCLOCK_MLAPB_ClockRoot_MuxOsc24M = 0U, + kCLOCK_MLAPB_ClockRoot_MuxSysPll1Pfd0Div2 = 1U, + kCLOCK_MLAPB_ClockRoot_MuxSysPll1Pfd1Div2 = 2U, + kCLOCK_MLAPB_ClockRoot_MuxVideoPll1Out = 3U, + + /* Ml */ + kCLOCK_ML_ClockRoot_MuxOsc24M = 0U, + kCLOCK_ML_ClockRoot_MuxSysPll1Pfd0 = 1U, + kCLOCK_ML_ClockRoot_MuxSysPll1Pfd1 = 2U, + kCLOCK_ML_ClockRoot_MuxSysPll1Pfd2 = 3U, + + /* Media Axi */ + kCLOCK_MEDIAAXI_ClockRoot_MuxOsc24M = 0U, + kCLOCK_MEDIAAXI_ClockRoot_MuxSysPll1Pfd0 = 1U, + kCLOCK_MEDIAAXI_ClockRoot_MuxSysPll1Pfd1 = 2U, + kCLOCK_MEDIAAXI_ClockRoot_MuxSysPll1Pfd2 = 3U, + + /* Media Apb */ + kCLOCK_MEDIAAPB_ClockRoot_MuxOsc24M = 0U, + kCLOCK_MEDIAAPB_ClockRoot_MuxSysPll1Pfd0Div2 = 1U, + kCLOCK_MEDIAAPB_ClockRoot_MuxSysPll1Pfd1Div2 = 2U, + kCLOCK_MEDIAAPB_ClockRoot_MuxVideoPll1Out = 3U, + + /* Media Ldb */ + kCLOCK_MEDIALDB_ClockRoot_MuxOsc24M = 0U, + kCLOCK_MEDIALDB_ClockRoot_MuxAudioPll1Out = 1U, + kCLOCK_MEDIALDB_ClockRoot_MuxVideoPll1Out = 2U, + kCLOCK_MEDIALDB_ClockRoot_MuxSysPll1Pfd0 = 3U, + + /* Media Disp Pix */ + kCLOCK_MEDIADISPPIX_ClockRoot_MuxOsc24M = 0U, + kCLOCK_MEDIADISPPIX_ClockRoot_MuxAudioPll1Out = 1U, + kCLOCK_MEDIADISPPIX_ClockRoot_MuxVideoPll1Out = 2U, + kCLOCK_MEDIADISPPIX_ClockRoot_MuxSysPll1Pfd0 = 3U, + + /* Cam Pix */ + kCLOCK_CAMPIX_ClockRoot_MuxOsc24M = 0U, + kCLOCK_CAMPIX_ClockRoot_MuxAudioPll1Out = 1U, + kCLOCK_CAMPIX_ClockRoot_MuxVideoPll1Out = 2U, + kCLOCK_CAMPIX_ClockRoot_MuxSysPll1Pfd0 = 3U, + + /* Mipi Test Byte */ + kCLOCK_MIPITESTBYTE_ClockRoot_MuxOsc24M = 0U, + kCLOCK_MIPITESTBYTE_ClockRoot_MuxAudioPll1Out = 1U, + kCLOCK_MIPITESTBYTE_ClockRoot_MuxVideoPll1Out = 2U, + kCLOCK_MIPITESTBYTE_ClockRoot_MuxSysPll1Pfd0 = 3U, + + /* Mipi Phy Cfg */ + kCLOCK_MIPIPHYCFG_ClockRoot_MuxOsc24M = 0U, + kCLOCK_MIPIPHYCFG_ClockRoot_MuxAudioPll1Out = 1U, + kCLOCK_MIPIPHYCFG_ClockRoot_MuxVideoPll1Out = 2U, + kCLOCK_MIPIPHYCFG_ClockRoot_MuxSysPll1Pfd0 = 3U, + + /* Dram Alt */ + kCLOCK_DRAMALT_ClockRoot_MuxOsc24M = 0U, + kCLOCK_DRAMALT_ClockRoot_MuxSysPll1Pfd0 = 1U, + kCLOCK_DRAMALT_ClockRoot_MuxSysPll1Pfd1 = 2U, + kCLOCK_DRAMALT_ClockRoot_MuxSysPll1Pfd2 = 3U, + + /* Dram Apb */ + kCLOCK_DRAMAPB_ClockRoot_MuxOsc24M = 0U, + kCLOCK_DRAMAPB_ClockRoot_MuxSysPll1Pfd0Div2 = 1U, + kCLOCK_DRAMAPB_ClockRoot_MuxSysPll1Pfd1Div2 = 2U, + kCLOCK_DRAMAPB_ClockRoot_MuxSysPll1Pfd2Div2 = 3U, + + /* Adc */ + kCLOCK_ADC_ClockRoot_MuxOsc24M = 0U, + kCLOCK_ADC_ClockRoot_MuxSysPll1Pfd0Div2 = 1U, + kCLOCK_ADC_ClockRoot_MuxSysPll1Pfd1Div2 = 2U, + kCLOCK_ADC_ClockRoot_MuxVideoPll1Out = 3U, + + /* Pdm */ + kCLOCK_PDM_ClockRoot_MuxOsc24M = 0U, + kCLOCK_PDM_ClockRoot_MuxAudioPll1Out = 1U, + kCLOCK_PDM_ClockRoot_MuxVideoPll1Out = 2U, + kCLOCK_PDM_ClockRoot_MuxExt = 3U, + + /* Tstmr1 */ + kCLOCK_TSTMR1_ClockRoot_MuxOsc24M = 0U, + kCLOCK_TSTMR1_ClockRoot_MuxSysPll1Pfd0Div2 = 1U, + kCLOCK_TSTMR1_ClockRoot_MuxSysPll1Pfd1Div2 = 2U, + kCLOCK_TSTMR1_ClockRoot_MuxVideoPll1Out = 3U, + + /* Tstmr2 */ + kCLOCK_TSTMR2_ClockRoot_MuxOsc24M = 0U, + kCLOCK_TSTMR2_ClockRoot_MuxSysPll1Pfd0Div2 = 1U, + kCLOCK_TSTMR2_ClockRoot_MuxSysPll1Pfd1Div2 = 2U, + kCLOCK_TSTMR2_ClockRoot_MuxVideoPll1Out = 3U, + + /* MQS1 */ + kCLOCK_MQS1_ClockRoot_MuxOsc24M = 0U, + kCLOCK_MQS1_ClockRoot_MuxAudioPll1Out = 1U, + kCLOCK_MQS1_ClockRoot_MuxVideoPll1Out = 2U, + kCLOCK_MQS1_ClockRoot_MuxExt = 3U, + + /* MQS2 */ + kCLOCK_MQS2_ClockRoot_MuxOsc24M = 0U, + kCLOCK_MQS2_ClockRoot_MuxAudioPll1Out = 1U, + kCLOCK_MQS2_ClockRoot_MuxVideoPll1Out = 2U, + kCLOCK_MQS2_ClockRoot_MuxExt = 3U, + + /* Audio XCVR */ + kCLOCK_AUDIOXCVR_ClockRoot_MuxOsc24M = 0U, + kCLOCK_AUDIOXCVR_ClockRoot_MuxSysPll1Pfd0Div2 = 1U, + kCLOCK_AUDIOXCVR_ClockRoot_MuxSysPll1Pfd1Div2 = 2U, + kCLOCK_AUDIOXCVR_ClockRoot_MuxSysPll1Pfd2Div2 = 3U, + + /* Spdif */ + kCLOCK_SPDIF_ClockRoot_MuxOsc24M = 0U, + kCLOCK_SPDIF_ClockRoot_MuxAudioPll1Out = 1U, + kCLOCK_SPDIF_ClockRoot_MuxVideoPll1Out = 2U, + kCLOCK_SPDIF_ClockRoot_MuxExt = 3U, + + /* Enet */ + kCLOCK_ENET_ClockRoot_MuxOsc24M = 0U, + kCLOCK_ENET_ClockRoot_MuxSysPll1Pfd0Div2 = 1U, + kCLOCK_ENET_ClockRoot_MuxSysPll1Pfd1Div2 = 2U, + kCLOCK_ENET_ClockRoot_MuxSysPll1Pfd2Div2 = 3U, + + /* Enet Timer1 */ + kCLOCK_ENETTSTMR1_ClockRoot_MuxOsc24M = 0U, + kCLOCK_ENETTSTMR1_ClockRoot_MuxSysPll1Pfd0Div2 = 1U, + kCLOCK_ENETTSTMR1_ClockRoot_MuxSysPll1Pfd1Div2 = 2U, + kCLOCK_ENETTSTMR1_ClockRoot_MuxVideoPll1Out = 3U, + + /* Enet Timer2 */ + kCLOCK_ENETTSTMR2_ClockRoot_MuxOsc24M = 0U, + kCLOCK_ENETTSTMR2_ClockRoot_MuxSysPll1Pfd0Div2 = 1U, + kCLOCK_ENETTSTMR2_ClockRoot_MuxSysPll1Pfd1Div2 = 2U, + kCLOCK_ENETTSTMR2_ClockRoot_MuxVideoPll1Out = 3U, + + /* Enet Ref */ + kCLOCK_ENETREF_ClockRoot_MuxOsc24M = 0U, + kCLOCK_ENETREF_ClockRoot_MuxSysPll1Pfd0Div2 = 1U, + kCLOCK_ENETREF_ClockRoot_MuxSysPll1Pfd1Div2 = 2U, + kCLOCK_ENETREF_ClockRoot_MuxSysPll1Pfd2Div2 = 3U, + + /* Enet Ref Phy */ + kCLOCK_ENETREFPHY_ClockRoot_MuxOsc24M = 0U, + kCLOCK_ENETREFPHY_ClockRoot_MuxSysPll1Pfd0Div2 = 1U, + kCLOCK_ENETREFPHY_ClockRoot_MuxSysPll1Pfd1Div2 = 2U, + kCLOCK_ENETREFPHY_ClockRoot_MuxVideoPll1Out = 3U, + + /* I3c1 Slow */ + kCLOCK_I3C1SLOW_ClockRoot_MuxOsc24M = 0U, + kCLOCK_I3C1SLOW_ClockRoot_MuxSysPll1Pfd0Div2 = 1U, + kCLOCK_I3C1SLOW_ClockRoot_MuxSysPll1Pfd1Div2 = 2U, + kCLOCK_I3C1SLOW_ClockRoot_MuxVideoPll1Out = 3U, + + /* I3c2 Slow */ + kCLOCK_I3C2SLOW_ClockRoot_MuxOsc24M = 0U, + kCLOCK_I3C2SLOW_ClockRoot_MuxSysPll1Pfd0Div2 = 1U, + kCLOCK_I3C2SLOW_ClockRoot_MuxSysPll1Pfd1Div2 = 2U, + kCLOCK_I3C2SLOW_ClockRoot_MuxVideoPll1Out = 3U, + + /* Usb Phy Burunin */ + kCLOCK_USBPHYBURUNIN_ClockRoot_MuxOsc24M = 0U, + kCLOCK_USBPHYBURUNIN_ClockRoot_MuxSysPll1Pfd0Div2 = 1U, + kCLOCK_USBPHYBURUNIN_ClockRoot_MuxSysPll1Pfd1Div2 = 2U, + kCLOCK_USBPHYBURUNIN_ClockRoot_MuxVideoPll1Out = 3U, + + /* Pal Came Scan */ + kCLOCK_PALCAMESCAN_ClockRoot_MuxOsc24M = 0U, + kCLOCK_PALCAMESCAN_ClockRoot_MuxAudioPll1Out = 1U, + kCLOCK_PALCAMESCAN_ClockRoot_MuxVideoPll1Out = 2U, + kCLOCK_PALCAMESCAN_ClockRoot_MuxSysPll1Pfd2 = 3U, +} clock_root_mux_source_t; + +/******************************************************************************* + * Clock Gate Definitions + ******************************************************************************/ + +/*! @brief Clock gate value */ +typedef enum _clock_gate_value +{ + kCLOCK_Off = CCM_LPCG_LPM_SETTING_0, + kCLOCK_On = CCM_LPCG_LPM_SETTING_4, +} clock_gate_value_t; + +/*! + * @brief Clock LPCG index (Clock Gating Channel) + */ +typedef enum _clock_lpcg +{ + kCLOCK_A55 = 0, + kCLOCK_Cm33 = 1, + kCLOCK_Arm_Trout = 2, + kCLOCK_Sentinel = 3, + kCLOCK_Sim_Wakeup = 4, + kCLOCK_Sim_Aon = 5, + kCLOCK_Sim_Mega = 6, + kCLOCK_Anadig = 7, + kCLOCK_Src = 8, + kCLOCK_Ccm = 9, + kCLOCK_Gpc = 10, + kCLOCK_Adc1 = 11, + kCLOCK_Wdog1 = 12, + kCLOCK_Wdog2 = 13, + kCLOCK_Wdog3 = 14, + kCLOCK_Wdog4 = 15, + kCLOCK_Wdog5 = 16, + kCLOCK_Sema1 = 17, + kCLOCK_Sema2 = 18, + kCLOCK_Mu_A = 19, + kCLOCK_Mu_B = 20, + kCLOCK_Edma1 = 21, + kCLOCK_Edma2 = 22, + kCLOCK_Romcp_A55 = 23, + kCLOCK_Romcp_M33 = 24, + kCLOCK_Flexspi1 = 25, + kCLOCK_Aon_Trdc = 26, + kCLOCK_Wkup_Trdc = 27, + kCLOCK_Ocotp = 28, + kCLOCK_Bbsm_Hp = 29, + kCLOCK_Bbsm = 30, + kCLOCK_Cstrace = 31, + kCLOCK_Csswo = 32, + kCLOCK_Iomuxc = 33, + kCLOCK_Gpio1 = 34, + kCLOCK_Gpio2 = 35, + kCLOCK_Gpio3 = 36, + kCLOCK_Gpio4 = 37, + kCLOCK_Flexio1 = 38, + kCLOCK_Flexio2 = 39, + kCLOCK_Lpit1 = 40, + kCLOCK_Lpit2 = 41, + kCLOCK_Lptmr1 = 42, + kCLOCK_Lptmr2 = 43, + kCLOCK_Tpm1 = 44, + kCLOCK_Tpm2 = 45, + kCLOCK_Tpm3 = 46, + kCLOCK_Tpm4 = 47, + kCLOCK_Tpm5 = 48, + kCLOCK_Tpm6 = 49, + kCLOCK_Can1 = 50, + kCLOCK_Can2 = 51, + kCLOCK_Lpuart1 = 52, + kCLOCK_Lpuart2 = 53, + kCLOCK_Lpuart3 = 54, + kCLOCK_Lpuart4 = 55, + kCLOCK_Lpuart5 = 56, + kCLOCK_Lpuart6 = 57, + kCLOCK_Lpuart7 = 58, + kCLOCK_Lpuart8 = 59, + kCLOCK_Lpi2c1 = 60, + kCLOCK_Lpi2c2 = 61, + kCLOCK_Lpi2c3 = 62, + kCLOCK_Lpi2c4 = 63, + kCLOCK_Lpi2c5 = 64, + kCLOCK_Lpi2c6 = 65, + kCLOCK_Lpi2c7 = 66, + kCLOCK_Lpi2c8 = 67, + kCLOCK_Lpspi1 = 68, + kCLOCK_Lpspi2 = 69, + kCLOCK_Lpspi3 = 70, + kCLOCK_Lpspi4 = 71, + kCLOCK_Lpspi5 = 72, + kCLOCK_Lpspi6 = 73, + kCLOCK_Lpspi7 = 74, + kCLOCK_Lpspi8 = 75, + kCLOCK_I3c1 = 76, + kCLOCK_I3c2 = 77, + kCLOCK_Usdhc1 = 78, + kCLOCK_Usdhc2 = 79, + kCLOCK_Usdhc3 = 80, + kCLOCK_Sai1 = 81, + kCLOCK_Sai2 = 82, + kCLOCK_Sai3 = 83, + kCLOCK_Ssi_W2ao = 84, + kCLOCK_Ssi_Ao2w = 85, + kCLOCK_Mipi_Csi = 86, + kCLOCK_Mipi_Dsi = 87, + kCLOCK_Lvds = 88, + kCLOCK_Lcdif = 89, + kCLOCK_Pxp = 90, + kCLOCK_Isi = 91, + kCLOCK_Nic_Media = 92, + kCLOCK_Ddr_Dfi = 93, + kCLOCK_Ddr_Ctl = 94, + kCLOCK_Ddr_Dfi_Ctl = 95, + kCLOCK_Ddr_Ssi = 96, + kCLOCK_Ddr_Bypass = 97, + kCLOCK_Ddr_Apb = 98, + kCLOCK_Ddr_Drampll = 99, + kCLOCK_Ddr_Clk_Ctl = 100, + kCLOCK_Nic_Central = 101, + kCLOCK_Gic600 = 102, + kCLOCK_Nic_Apb = 103, + kCLOCK_Usb_Controller = 104, + kCLOCK_Usb_Test_60m = 105, + kCLOCK_Hsio_Trout_24m = 106, + kCLOCK_Pdm = 107, + kCLOCK_Mqs1 = 108, + kCLOCK_Mqs2 = 109, + kCLOCK_Aud_Xcvr = 110, + kCLOCK_Nicmix_Mecc = 111, + kCLOCK_Spdif = 112, + kCLOCK_Ssi_Ml2nic = 113, + kCLOCK_Ssi_Med2nic = 114, + kCLOCK_Ssi_Hsio2nic = 115, + kCLOCK_Ssi_W2nic = 116, + kCLOCK_Ssi_Nic2w = 117, + kCLOCK_Ssi_Nic2ddr = 118, + kCLOCK_Hsio_32k = 119, + kCLOCK_Enet1 = 120, + kCLOCK_Enet_Qos = 121, + kCLOCK_Sys_Cnt = 122, + kCLOCK_Tstmr1 = 123, + kCLOCK_Tstmr2 = 124, + kCLOCK_Tmc = 125, + kCLOCK_Pmro = 126, + kCLOCK_IpInvalid, +} clock_lpcg_t; + +#define clock_ip_name_t clock_lpcg_t + +/*! @brief Clock ip name array for EDMA. */ +#define EDMA_CLOCKS \ + { \ + kCLOCK_Edma1, kCLOCK_Edma2 \ + } + +/* + * ! @brief Clock ip name array for MU. + * clock of MU1_MUA, MU2_MUA is enabled by same LPCG42(Gate signal is clk_enable_mu_a) + */ +#define MU_CLOCKS \ + { \ + kCLOCK_Mu_A, kCLOCK_Mu_A \ + } + +/*! @brief Clock ip name array for LCDIFV3. */ +#define LCDIFV3_CLOCKS \ + { \ + kCLOCK_IpInvalid, kCLOCK_Lcdif \ + } + +/*! @brief Clock ip name array for LPI2C. */ +#define LPI2C_CLOCKS \ + { \ + kCLOCK_IpInvalid, kCLOCK_Lpi2c1, kCLOCK_Lpi2c2, kCLOCK_Lpi2c3, kCLOCK_Lpi2c4, kCLOCK_Lpi2c5, kCLOCK_Lpi2c6, \ + kCLOCK_Lpi2c7, kCLOCK_Lpi2c8 \ + } + +/*! @brief Clock ip name array for LPIT. */ +#define LPIT_CLOCKS \ + { \ + kCLOCK_IpInvalid, kCLOCK_Lpit1, kCLOCK_Lpit2 \ + } + +/*! @brief Clock ip name array for LPSPI. */ +#define LPSPI_CLOCKS \ + { \ + kCLOCK_IpInvalid, kCLOCK_Lpspi1, kCLOCK_Lpspi2, kCLOCK_Lpspi3, kCLOCK_Lpspi4, kCLOCK_Lpspi5, kCLOCK_Lpspi6, \ + kCLOCK_Lpspi7, kCLOCK_Lpspi8 \ + } + +/*! @brief Clock ip name array for TPM. */ +#define TPM_CLOCKS \ + { \ + kCLOCK_Tpm1, kCLOCK_Tpm2, kCLOCK_Tpm3, kCLOCK_Tpm4, kCLOCK_Tpm5, kCLOCK_Tpm6, \ + } + +/*! @brief Clock ip name array for FLEXIO. */ +#define FLEXIO_CLOCKS \ + { \ + kCLOCK_IpInvalid, kCLOCK_Flexio1, kCLOCK_Flexio2 \ + } + +/*! @brief Clock ip name array for FLEXSPI. */ +#define FLEXSPI_CLOCKS \ + { \ + kCLOCK_IpInvalid, kCLOCK_Flexspi1 \ + } + +/*! @brief Clock ip name array for TMU. */ +#define TMU_CLOCKS \ + { \ + kCLOCK_Tmc, \ + } + +/*! @brief Clock ip name array for FLEXCAN. */ +#define FLEXCAN_CLOCKS \ + { \ + kCLOCK_IpInvalid, kCLOCK_Can1, kCLOCK_Can2, \ + } + +/*! @brief Clock ip name array for LPUART. */ +#define LPUART_CLOCKS \ + { \ + kCLOCK_IpInvalid, kCLOCK_Lpuart1, kCLOCK_Lpuart2, kCLOCK_Lpuart3, kCLOCK_Lpuart4, kCLOCK_Lpuart5, \ + kCLOCK_Lpuart6, kCLOCK_Lpuart7, kCLOCK_Lpuart8 \ + } + +/*! @brief Clock ip name array for SAI. */ +#define SAI_CLOCKS \ + { \ + kCLOCK_IpInvalid, kCLOCK_Sai1, kCLOCK_Sai2, kCLOCK_Sai3, \ + } + +/*! @brief Clock ip name array for PDM. */ +#define PDM_CLOCKS \ + { \ + kCLOCK_Pdm \ + } + +/*! @brief Clock ip name array for ENET QOS. */ +#define ENETQOS_CLOCKS \ + { \ + kCLOCK_Enet_Qos \ + } + +/*! @brief Clock ip name array for ENET. */ +#define ENET_CLOCKS \ + { \ + kCLOCK_Enet1 \ + } + +/*! @brief Clock ip name array for I3C. */ +#define I3C_CLOCKS \ + { \ + kCLOCK_IpInvalid, kCLOCK_I3c1, kCLOCK_I3c2 \ + } + +/*! @brief Clock ip name array for SEMA42. */ +#define SEMA42_CLOCKS \ + { \ + kCLOCK_IpInvalid, kCLOCK_Sema1, kCLOCK_Sema2 \ + } + +/******************************************************************************* + * Clock Root APIs + ******************************************************************************/ + +/*! + * @brief Set CCM Root Clock MUX node to certain value. + * + * @param root Which root clock node to set, see \ref clock_root_t. + * @param src Clock mux value to set, different mux has different value range. See \ref clock_root_mux_source_t. + */ +static inline void CLOCK_SetRootClockMux(clock_root_t root, uint8_t src) +{ + assert(src < 8U); + CCM_CTRL->CLOCK_ROOT[root].CLOCK_ROOT_CONTROL.RW = + (CCM_CTRL->CLOCK_ROOT[root].CLOCK_ROOT_CONTROL.RW & ~(CCM_CLOCK_ROOT_MUX_MASK)) | CCM_CLOCK_ROOT_MUX(src); + __DSB(); + __ISB(); +} + +/*! + * @brief Get CCM Root Clock MUX value. + * + * @param root Which root clock node to get, see \ref clock_root_t. + * @return Clock mux value. + */ +static inline uint32_t CLOCK_GetRootClockMux(clock_root_t root) +{ + return (CCM_CTRL->CLOCK_ROOT[root].CLOCK_ROOT_CONTROL.RW & CCM_CLOCK_ROOT_MUX_MASK) >> CCM_CLOCK_ROOT_MUX_SHIFT; +} + +/*! + * @brief Get CCM Root Clock Source. + * + * @param root Which root clock node to get, see \ref clock_root_t. + * @param src Clock mux value to get, see \ref clock_root_mux_source_t. + * @return Clock source + */ +static inline clock_name_t CLOCK_GetRootClockSource(clock_root_t root, uint32_t src) +{ + return s_clockSourceName[root][src]; +} + +/*! + * @brief Set CCM Root Clock DIV certain value. + * + * @param root Which root clock to set, see \ref clock_root_t. + * @param div Clock div value to set, different divider has different value range. + */ +static inline void CLOCK_SetRootClockDiv(clock_root_t root, uint8_t div) +{ + assert(div); + CCM_CTRL->CLOCK_ROOT[root].CLOCK_ROOT_CONTROL.RW = + (CCM_CTRL->CLOCK_ROOT[root].CLOCK_ROOT_CONTROL.RW & ~CCM_CLOCK_ROOT_DIV_MASK) | + CCM_CLOCK_ROOT_DIV((uint32_t)div - 1UL); + __DSB(); + __ISB(); +} + +/*! + * @brief Get CCM DIV node value. + * + * @param root Which root clock node to get, see \ref clock_root_t. + * @return divider set for this root + */ +static inline uint32_t CLOCK_GetRootClockDiv(clock_root_t root) +{ + return ((CCM_CTRL->CLOCK_ROOT[root].CLOCK_ROOT_CONTROL.RW & CCM_CLOCK_ROOT_DIV_MASK) >> CCM_CLOCK_ROOT_DIV_SHIFT) + + 1UL; +} + +/*! + * @brief Power Off Root Clock + * + * @param root Which root clock node to set, see \ref clock_root_t. + */ +static inline void CLOCK_PowerOffRootClock(clock_root_t root) +{ + if (0UL == (CCM_CTRL->CLOCK_ROOT[root].CLOCK_ROOT_CONTROL.RW & CCM_CLOCK_ROOT_OFF_MASK)) + { + CCM_CTRL->CLOCK_ROOT[root].CLOCK_ROOT_CONTROL.SET = CCM_CLOCK_ROOT_OFF_MASK; + __DSB(); + __ISB(); + } +} + +/*! + * @brief Power On Root Clock + * + * @param root Which root clock node to set, see \ref clock_root_t. + */ +static inline void CLOCK_PowerOnRootClock(clock_root_t root) +{ + CCM_CTRL->CLOCK_ROOT[root].CLOCK_ROOT_CONTROL.CLR = CCM_CLOCK_ROOT_OFF_MASK; + __DSB(); + __ISB(); +} + +/*! + * @brief Configure Root Clock + * + * @param root Which root clock node to set, see \ref clock_root_t. + * @param config root clock config, see \ref clock_root_config_t + */ +static inline void CLOCK_SetRootClock(clock_root_t root, const clock_root_config_t *config) +{ + assert(config); + CCM_CTRL->CLOCK_ROOT[root].CLOCK_ROOT_CONTROL.RW = CCM_CLOCK_ROOT_MUX(config->mux) | + CCM_CLOCK_ROOT_DIV((uint32_t)config->div - 1UL) | + (config->clockOff ? CCM_CLOCK_ROOT_OFF(config->clockOff) : 0UL); + __DSB(); + __ISB(); +} + +/******************************************************************************* + * Clock Gate APIs + ******************************************************************************/ + +/*! + * @brief Control the clock gate for specific IP. + * + * @param name Which clock to enable, see \ref clock_lpcg_t. + * @param value Clock gate value to set, see \ref clock_gate_value_t. + */ +static inline void CLOCK_ControlGate(clock_ip_name_t name, clock_gate_value_t value) +{ + CCM_CTRL->LPCG[name].AUTHEN |= CCM_LPCG_AUTHEN_CPULPM_MODE(1U); + CCM_CTRL->LPCG[name].LPM_CUR = CCM_LPCG_LPM_CUR_LPM_SETTING_CUR(value); + __DSB(); + __ISB(); +} + +/*! + * @brief Enable the clock for specific IP. + * + * @param name Which clock to enable, see \ref clock_lpcg_t. + */ +static inline void CLOCK_EnableClock(clock_ip_name_t name) +{ + CLOCK_ControlGate(name, kCLOCK_On); +} + +/*! + * @brief Disable the clock for specific IP. + * + * @param name Which clock to disable, see \ref clock_lpcg_t. + */ +static inline void CLOCK_DisableClock(clock_ip_name_t name) +{ + CLOCK_ControlGate(name, kCLOCK_Off); +} + +/******************************************************************************* + * Other APIs + ******************************************************************************/ + +/* + * Setup a variable for clock source frequencies + */ +extern volatile uint32_t g_clockSourceFreq[kCLOCK_Ext + 1]; + +/*! + * @brief Gets the clock frequency for a specific IP module. + * + * This function gets the IP module clock frequency. + * + * @param name Which root clock to get, see \ref clock_root_t. + * @return Clock frequency value in hertz + */ +uint32_t CLOCK_GetIpFreq(clock_root_t name); + +#endif diff --git a/bsp/nxp/imx/imx91/drivers/sdk/devices/MIMX9131/drivers/fsl_iomuxc.h b/bsp/nxp/imx/imx91/drivers/sdk/devices/MIMX9131/drivers/fsl_iomuxc.h new file mode 100644 index 00000000000..c1a7bc8d6a4 --- /dev/null +++ b/bsp/nxp/imx/imx91/drivers/sdk/devices/MIMX9131/drivers/fsl_iomuxc.h @@ -0,0 +1,796 @@ +/* + * Copyright 2025 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _FSL_IOMUXC_H_ +#define _FSL_IOMUXC_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup iomuxc_driver + * @{ + */ + +/*! @file */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.iomuxc" +#endif + +/*! @name Driver version */ +/*@{*/ +/*! @brief IOMUXC driver version 1.0.0. */ +#define FSL_IOMUXC_DRIVER_VERSION (MAKE_VERSION(1, 0, 0)) +/*@}*/ + +/*! + * @name Pin function ID + * The pin function ID is a tuple of \ + * + * @{ + */ +#define IOMUXC_PAD_DAP_TDI__JTAG_MUX_TDI 0x543c0000, 0x00, 0x543c03d8, 0x00, 0x543c01b0 +#define IOMUXC_PAD_DAP_TDI__MQS2_LEFT 0x543c0000, 0x01, 0x0, 0x00, 0x543c01b0 +#define IOMUXC_PAD_DAP_TDI__CAN2_TX 0x543c0000, 0x03, 0x0, 0x00, 0x543c01b0 +#define IOMUXC_PAD_DAP_TDI__FLEXIO2_FLEXIO30 0x543c0000, 0x04, 0x0, 0x00, 0x543c01b0 +#define IOMUXC_PAD_DAP_TDI__GPIO3_IO28 0x543c0000, 0x05, 0x0, 0x00, 0x543c01b0 +#define IOMUXC_PAD_DAP_TDI__LPUART5_RX 0x543c0000, 0x06, 0x543c0488, 0x00, 0x543c01b0 +#define IOMUXC_PAD_DAP_TMS_SWDIO__JTAG_MUX_TMS 0x543c0004, 0x00, 0x543c03dc, 0x00, 0x543c01b4 +#define IOMUXC_PAD_DAP_TMS_SWDIO__FLEXIO2_FLEXIO31 0x543c0004, 0x04, 0x0, 0x00, 0x543c01b4 +#define IOMUXC_PAD_DAP_TMS_SWDIO__GPIO3_IO29 0x543c0004, 0x05, 0x0, 0x00, 0x543c01b4 +#define IOMUXC_PAD_DAP_TMS_SWDIO__LPUART5_RTS_B 0x543c0004, 0x06, 0x0, 0x00, 0x543c01b4 +#define IOMUXC_PAD_DAP_TCLK_SWCLK__JTAG_MUX_TCK 0x543c0008, 0x00, 0x543c03d4, 0x00, 0x543c01b8 +#define IOMUXC_PAD_DAP_TCLK_SWCLK__FLEXIO1_FLEXIO30 0x543c0008, 0x04, 0x0, 0x00, 0x543c01b8 +#define IOMUXC_PAD_DAP_TCLK_SWCLK__GPIO3_IO30 0x543c0008, 0x05, 0x0, 0x00, 0x543c01b8 +#define IOMUXC_PAD_DAP_TCLK_SWCLK__LPUART5_CTS_B 0x543c0008, 0x06, 0x543c0484, 0x00, 0x543c01b8 +#define IOMUXC_PAD_DAP_TDO_TRACESWO__JTAG_MUX_TDO 0x543c000c, 0x00, 0x0, 0x00, 0x543c01bc +#define IOMUXC_PAD_DAP_TDO_TRACESWO__MQS2_RIGHT 0x543c000c, 0x01, 0x0, 0x00, 0x543c01bc +#define IOMUXC_PAD_DAP_TDO_TRACESWO__CAN2_RX 0x543c000c, 0x03, 0x543c0364, 0x00, 0x543c01bc +#define IOMUXC_PAD_DAP_TDO_TRACESWO__FLEXIO1_FLEXIO31 0x543c000c, 0x04, 0x0, 0x00, 0x543c01bc +#define IOMUXC_PAD_DAP_TDO_TRACESWO__GPIO3_IO31 0x543c000c, 0x05, 0x0, 0x00, 0x543c01bc +#define IOMUXC_PAD_DAP_TDO_TRACESWO__LPUART5_TX 0x543c000c, 0x06, 0x543c048c, 0x00, 0x543c01bc +#define IOMUXC_PAD_GPIO_IO00__GPIO2_IO0 0x543c0010, 0x00, 0x0, 0x00, 0x543c01c0 +#define IOMUXC_PAD_GPIO_IO00__LPI2C3_SDA 0x543c0010, 0x01, 0x543c03f4, 0x00, 0x543c01c0 +#define IOMUXC_PAD_GPIO_IO00__MEDIAMIX_CAM_CLK 0x543c0010, 0x02, 0x543c04bc, 0x00, 0x543c01c0 +#define IOMUXC_PAD_GPIO_IO00__MEDIAMIX_DISP_CLK 0x543c0010, 0x03, 0x0, 0x00, 0x543c01c0 +#define IOMUXC_PAD_GPIO_IO00__LPSPI6_PCS0 0x543c0010, 0x04, 0x0, 0x00, 0x543c01c0 +#define IOMUXC_PAD_GPIO_IO00__LPUART5_TX 0x543c0010, 0x05, 0x543c048c, 0x01, 0x543c01c0 +#define IOMUXC_PAD_GPIO_IO00__LPI2C5_SDA 0x543c0010, 0x06, 0x543c0404, 0x00, 0x543c01c0 +#define IOMUXC_PAD_GPIO_IO00__FLEXIO1_FLEXIO0 0x543c0010, 0x07, 0x543c036c, 0x00, 0x543c01c0 +#define IOMUXC_PAD_GPIO_IO01__GPIO2_IO1 0x543c0014, 0x00, 0x0, 0x00, 0x543c01c4 +#define IOMUXC_PAD_GPIO_IO01__LPI2C3_SCL 0x543c0014, 0x01, 0x543c03f0, 0x00, 0x543c01c4 +#define IOMUXC_PAD_GPIO_IO01__MEDIAMIX_CAM_DATA0 0x543c0014, 0x02, 0x543c0490, 0x00, 0x543c01c4 +#define IOMUXC_PAD_GPIO_IO01__MEDIAMIX_DISP_DE 0x543c0014, 0x03, 0x0, 0x00, 0x543c01c4 +#define IOMUXC_PAD_GPIO_IO01__LPSPI6_SIN 0x543c0014, 0x04, 0x0, 0x00, 0x543c01c4 +#define IOMUXC_PAD_GPIO_IO01__LPUART5_RX 0x543c0014, 0x05, 0x543c0488, 0x01, 0x543c01c4 +#define IOMUXC_PAD_GPIO_IO01__LPI2C5_SCL 0x543c0014, 0x06, 0x543c0400, 0x00, 0x543c01c4 +#define IOMUXC_PAD_GPIO_IO01__FLEXIO1_FLEXIO1 0x543c0014, 0x07, 0x543c0370, 0x00, 0x543c01c4 +#define IOMUXC_PAD_GPIO_IO02__GPIO2_IO3 0x543c0018, 0x00, 0x0, 0x00, 0x543c01c8 +#define IOMUXC_PAD_GPIO_IO02__LPI2C4_SDA 0x543c0018, 0x01, 0x543c03fc, 0x00, 0x543c01c8 +#define IOMUXC_PAD_GPIO_IO02__MEDIAMIX_CAM_VSYNC 0x543c0018, 0x02, 0x543c04c0, 0x00, 0x543c01c8 +#define IOMUXC_PAD_GPIO_IO02__MEDIAMIX_DISP_VSYNC 0x543c0018, 0x03, 0x0, 0x00, 0x543c01c8 +#define IOMUXC_PAD_GPIO_IO02__LPSPI6_SOUT 0x543c0018, 0x04, 0x0, 0x00, 0x543c01c8 +#define IOMUXC_PAD_GPIO_IO02__LPUART5_CTS_B 0x543c0018, 0x05, 0x543c0484, 0x01, 0x543c01c8 +#define IOMUXC_PAD_GPIO_IO02__LPI2C6_SDA 0x543c0018, 0x06, 0x543c040c, 0x00, 0x543c01c8 +#define IOMUXC_PAD_GPIO_IO02__FLEXIO1_FLEXIO3 0x543c0018, 0x07, 0x543c0374, 0x00, 0x543c01c8 +#define IOMUXC_PAD_GPIO_IO03__GPIO2_IO3 0x543c001c, 0x00, 0x0, 0x00, 0x543c01cc +#define IOMUXC_PAD_GPIO_IO03__LPI2C4_SCL 0x543c001c, 0x01, 0x543c03f8, 0x00, 0x543c01cc +#define IOMUXC_PAD_GPIO_IO03__MEDIAMIX_CAM_HSYNC 0x543c001c, 0x02, 0x543c04b8, 0x00, 0x543c01cc +#define IOMUXC_PAD_GPIO_IO03__MEDIAMIX_DISP_HSYNC 0x543c001c, 0x03, 0x0, 0x00, 0x543c01cc +#define IOMUXC_PAD_GPIO_IO03__LPSPI6_SCK 0x543c001c, 0x04, 0x0, 0x00, 0x543c01cc +#define IOMUXC_PAD_GPIO_IO03__LPUART5_RTS_B 0x543c001c, 0x05, 0x0, 0x00, 0x543c01cc +#define IOMUXC_PAD_GPIO_IO03__LPI2C6_SCL 0x543c001c, 0x06, 0x543c0408, 0x00, 0x543c01cc +#define IOMUXC_PAD_GPIO_IO03__FLEXIO1_FLEXIO3 0x543c001c, 0x07, 0x543c0378, 0x00, 0x543c01cc +#define IOMUXC_PAD_GPIO_IO04__GPIO2_IO4 0x543c0020, 0x00, 0x0, 0x00, 0x543c01d0 +#define IOMUXC_PAD_GPIO_IO04__TPM3_CH0 0x543c0020, 0x01, 0x0, 0x00, 0x543c01d0 +#define IOMUXC_PAD_GPIO_IO04__PDM_CLK 0x543c0020, 0x02, 0x0, 0x00, 0x543c01d0 +#define IOMUXC_PAD_GPIO_IO04__MEDIAMIX_DISP_DATA0 0x543c0020, 0x03, 0x0, 0x00, 0x543c01d0 +#define IOMUXC_PAD_GPIO_IO04__LPSPI7_PCS0 0x543c0020, 0x04, 0x0, 0x00, 0x543c01d0 +#define IOMUXC_PAD_GPIO_IO04__LPUART6_TX 0x543c0020, 0x05, 0x0, 0x00, 0x543c01d0 +#define IOMUXC_PAD_GPIO_IO04__LPI2C6_SDA 0x543c0020, 0x06, 0x543c040c, 0x01, 0x543c01d0 +#define IOMUXC_PAD_GPIO_IO04__FLEXIO1_FLEXIO4 0x543c0020, 0x07, 0x543c037c, 0x00, 0x543c01d0 +#define IOMUXC_PAD_GPIO_IO05__GPIO2_IO5 0x543c0024, 0x00, 0x0, 0x00, 0x543c01d4 +#define IOMUXC_PAD_GPIO_IO05__TPM4_CH0 0x543c0024, 0x01, 0x0, 0x00, 0x543c01d4 +#define IOMUXC_PAD_GPIO_IO05__PDM_BIT_STREAM0 0x543c0024, 0x02, 0x543c04c4, 0x00, 0x543c01d4 +#define IOMUXC_PAD_GPIO_IO05__MEDIAMIX_DISP_DATA1 0x543c0024, 0x03, 0x0, 0x00, 0x543c01d4 +#define IOMUXC_PAD_GPIO_IO05__LPSPI7_SIN 0x543c0024, 0x04, 0x0, 0x00, 0x543c01d4 +#define IOMUXC_PAD_GPIO_IO05__LPUART6_RX 0x543c0024, 0x05, 0x0, 0x00, 0x543c01d4 +#define IOMUXC_PAD_GPIO_IO05__LPI2C6_SCL 0x543c0024, 0x06, 0x543c0408, 0x01, 0x543c01d4 +#define IOMUXC_PAD_GPIO_IO05__FLEXIO1_FLEXIO5 0x543c0024, 0x07, 0x543c0380, 0x00, 0x543c01d4 +#define IOMUXC_PAD_GPIO_IO06__GPIO2_IO6 0x543c0028, 0x00, 0x0, 0x00, 0x543c01d8 +#define IOMUXC_PAD_GPIO_IO06__TPM5_CH0 0x543c0028, 0x01, 0x0, 0x00, 0x543c01d8 +#define IOMUXC_PAD_GPIO_IO06__PDM_BIT_STREAM1 0x543c0028, 0x02, 0x543c04c8, 0x00, 0x543c01d8 +#define IOMUXC_PAD_GPIO_IO06__MEDIAMIX_DISP_DATA2 0x543c0028, 0x03, 0x0, 0x00, 0x543c01d8 +#define IOMUXC_PAD_GPIO_IO06__LPSPI7_SOUT 0x543c0028, 0x04, 0x0, 0x00, 0x543c01d8 +#define IOMUXC_PAD_GPIO_IO06__LPUART6_CTS_B 0x543c0028, 0x05, 0x0, 0x00, 0x543c01d8 +#define IOMUXC_PAD_GPIO_IO06__LPI2C7_SDA 0x543c0028, 0x06, 0x543c0414, 0x00, 0x543c01d8 +#define IOMUXC_PAD_GPIO_IO06__FLEXIO1_FLEXIO6 0x543c0028, 0x07, 0x543c0384, 0x00, 0x543c01d8 +#define IOMUXC_PAD_GPIO_IO07__GPIO2_IO7 0x543c002c, 0x00, 0x0, 0x00, 0x543c01dc +#define IOMUXC_PAD_GPIO_IO07__LPSPI3_PCS1 0x543c002c, 0x01, 0x0, 0x00, 0x543c01dc +#define IOMUXC_PAD_GPIO_IO07__MEDIAMIX_CAM_DATA1 0x543c002c, 0x02, 0x543c0494, 0x00, 0x543c01dc +#define IOMUXC_PAD_GPIO_IO07__MEDIAMIX_DISP_DATA3 0x543c002c, 0x03, 0x0, 0x00, 0x543c01dc +#define IOMUXC_PAD_GPIO_IO07__LPSPI7_SCK 0x543c002c, 0x04, 0x0, 0x00, 0x543c01dc +#define IOMUXC_PAD_GPIO_IO07__LPUART6_RTS_B 0x543c002c, 0x05, 0x0, 0x00, 0x543c01dc +#define IOMUXC_PAD_GPIO_IO07__LPI2C7_SCL 0x543c002c, 0x06, 0x543c0410, 0x00, 0x543c01dc +#define IOMUXC_PAD_GPIO_IO07__FLEXIO1_FLEXIO7 0x543c002c, 0x07, 0x543c0388, 0x00, 0x543c01dc +#define IOMUXC_PAD_GPIO_IO08__GPIO2_IO8 0x543c0030, 0x00, 0x0, 0x00, 0x543c01e0 +#define IOMUXC_PAD_GPIO_IO08__LPSPI3_PCS0 0x543c0030, 0x01, 0x0, 0x00, 0x543c01e0 +#define IOMUXC_PAD_GPIO_IO08__MEDIAMIX_CAM_DATA2 0x543c0030, 0x02, 0x543c0498, 0x00, 0x543c01e0 +#define IOMUXC_PAD_GPIO_IO08__MEDIAMIX_DISP_DATA4 0x543c0030, 0x03, 0x0, 0x00, 0x543c01e0 +#define IOMUXC_PAD_GPIO_IO08__TPM6_CH0 0x543c0030, 0x04, 0x0, 0x00, 0x543c01e0 +#define IOMUXC_PAD_GPIO_IO08__LPUART7_TX 0x543c0030, 0x05, 0x0, 0x00, 0x543c01e0 +#define IOMUXC_PAD_GPIO_IO08__LPI2C7_SDA 0x543c0030, 0x06, 0x543c0414, 0x01, 0x543c01e0 +#define IOMUXC_PAD_GPIO_IO08__FLEXIO1_FLEXIO8 0x543c0030, 0x07, 0x543c038c, 0x00, 0x543c01e0 +#define IOMUXC_PAD_GPIO_IO09__GPIO2_IO9 0x543c0034, 0x00, 0x0, 0x00, 0x543c01e4 +#define IOMUXC_PAD_GPIO_IO09__LPSPI3_SIN 0x543c0034, 0x01, 0x0, 0x00, 0x543c01e4 +#define IOMUXC_PAD_GPIO_IO09__MEDIAMIX_CAM_DATA3 0x543c0034, 0x02, 0x543c049c, 0x00, 0x543c01e4 +#define IOMUXC_PAD_GPIO_IO09__MEDIAMIX_DISP_DATA5 0x543c0034, 0x03, 0x0, 0x00, 0x543c01e4 +#define IOMUXC_PAD_GPIO_IO09__TPM3_EXTCLK 0x543c0034, 0x04, 0x0, 0x00, 0x543c01e4 +#define IOMUXC_PAD_GPIO_IO09__LPUART7_RX 0x543c0034, 0x05, 0x0, 0x00, 0x543c01e4 +#define IOMUXC_PAD_GPIO_IO09__LPI2C7_SCL 0x543c0034, 0x06, 0x543c0410, 0x01, 0x543c01e4 +#define IOMUXC_PAD_GPIO_IO09__FLEXIO1_FLEXIO9 0x543c0034, 0x07, 0x543c0390, 0x00, 0x543c01e4 +#define IOMUXC_PAD_GPIO_IO10__GPIO2_IO10 0x543c0038, 0x00, 0x0, 0x00, 0x543c01e8 +#define IOMUXC_PAD_GPIO_IO10__LPSPI3_SOUT 0x543c0038, 0x01, 0x0, 0x00, 0x543c01e8 +#define IOMUXC_PAD_GPIO_IO10__MEDIAMIX_CAM_DATA4 0x543c0038, 0x02, 0x543c04a0, 0x00, 0x543c01e8 +#define IOMUXC_PAD_GPIO_IO10__MEDIAMIX_DISP_DATA6 0x543c0038, 0x03, 0x0, 0x00, 0x543c01e8 +#define IOMUXC_PAD_GPIO_IO10__TPM4_EXTCLK 0x543c0038, 0x04, 0x0, 0x00, 0x543c01e8 +#define IOMUXC_PAD_GPIO_IO10__LPUART7_CTS_B 0x543c0038, 0x05, 0x0, 0x00, 0x543c01e8 +#define IOMUXC_PAD_GPIO_IO10__LPI2C8_SDA 0x543c0038, 0x06, 0x543c041c, 0x00, 0x543c01e8 +#define IOMUXC_PAD_GPIO_IO10__FLEXIO1_FLEXIO10 0x543c0038, 0x07, 0x543c0394, 0x00, 0x543c01e8 +#define IOMUXC_PAD_GPIO_IO11__GPIO2_IO11 0x543c003c, 0x00, 0x0, 0x00, 0x543c01ec +#define IOMUXC_PAD_GPIO_IO11__LPSPI3_SCK 0x543c003c, 0x01, 0x0, 0x00, 0x543c01ec +#define IOMUXC_PAD_GPIO_IO11__MEDIAMIX_CAM_DATA5 0x543c003c, 0x02, 0x543c04a4, 0x00, 0x543c01ec +#define IOMUXC_PAD_GPIO_IO11__MEDIAMIX_DISP_DATA7 0x543c003c, 0x03, 0x0, 0x00, 0x543c01ec +#define IOMUXC_PAD_GPIO_IO11__TPM5_EXTCLK 0x543c003c, 0x04, 0x0, 0x00, 0x543c01ec +#define IOMUXC_PAD_GPIO_IO11__LPUART7_RTS_B 0x543c003c, 0x05, 0x0, 0x00, 0x543c01ec +#define IOMUXC_PAD_GPIO_IO11__LPI2C8_SCL 0x543c003c, 0x06, 0x543c0418, 0x00, 0x543c01ec +#define IOMUXC_PAD_GPIO_IO11__FLEXIO1_FLEXIO11 0x543c003c, 0x07, 0x543c0398, 0x00, 0x543c01ec +#define IOMUXC_PAD_GPIO_IO12__GPIO2_IO12 0x543c0040, 0x00, 0x0, 0x00, 0x543c01f0 +#define IOMUXC_PAD_GPIO_IO12__TPM3_CH2 0x543c0040, 0x01, 0x0, 0x00, 0x543c01f0 +#define IOMUXC_PAD_GPIO_IO12__PDM_BIT_STREAM2 0x543c0040, 0x02, 0x543c04cc, 0x00, 0x543c01f0 +#define IOMUXC_PAD_GPIO_IO12__MEDIAMIX_DISP_DATA8 0x543c0040, 0x03, 0x0, 0x00, 0x543c01f0 +#define IOMUXC_PAD_GPIO_IO12__LPSPI8_PCS0 0x543c0040, 0x04, 0x0, 0x00, 0x543c01f0 +#define IOMUXC_PAD_GPIO_IO12__LPUART8_TX 0x543c0040, 0x05, 0x0, 0x00, 0x543c01f0 +#define IOMUXC_PAD_GPIO_IO12__LPI2C8_SDA 0x543c0040, 0x06, 0x543c041c, 0x01, 0x543c01f0 +#define IOMUXC_PAD_GPIO_IO12__SAI3_RX_SYNC 0x543c0040, 0x07, 0x543c04dc, 0x00, 0x543c01f0 +#define IOMUXC_PAD_GPIO_IO13__GPIO2_IO13 0x543c0044, 0x00, 0x0, 0x00, 0x543c01f4 +#define IOMUXC_PAD_GPIO_IO13__TPM4_CH2 0x543c0044, 0x01, 0x0, 0x00, 0x543c01f4 +#define IOMUXC_PAD_GPIO_IO13__PDM_BIT_STREAM3 0x543c0044, 0x02, 0x543c04d0, 0x00, 0x543c01f4 +#define IOMUXC_PAD_GPIO_IO13__MEDIAMIX_DISP_DATA9 0x543c0044, 0x03, 0x0, 0x00, 0x543c01f4 +#define IOMUXC_PAD_GPIO_IO13__LPSPI8_SIN 0x543c0044, 0x04, 0x0, 0x00, 0x543c01f4 +#define IOMUXC_PAD_GPIO_IO13__LPUART8_RX 0x543c0044, 0x05, 0x0, 0x00, 0x543c01f4 +#define IOMUXC_PAD_GPIO_IO13__LPI2C8_SCL 0x543c0044, 0x06, 0x543c0418, 0x01, 0x543c01f4 +#define IOMUXC_PAD_GPIO_IO13__FLEXIO1_FLEXIO13 0x543c0044, 0x07, 0x543c039c, 0x00, 0x543c01f4 +#define IOMUXC_PAD_GPIO_IO14__GPIO2_IO14 0x543c0048, 0x00, 0x0, 0x00, 0x543c01f8 +#define IOMUXC_PAD_GPIO_IO14__LPUART3_TX 0x543c0048, 0x01, 0x543c0474, 0x00, 0x543c01f8 +#define IOMUXC_PAD_GPIO_IO14__MEDIAMIX_CAM_DATA6 0x543c0048, 0x02, 0x543c04a8, 0x00, 0x543c01f8 +#define IOMUXC_PAD_GPIO_IO14__MEDIAMIX_DISP_DATA10 0x543c0048, 0x03, 0x0, 0x00, 0x543c01f8 +#define IOMUXC_PAD_GPIO_IO14__LPSPI8_SOUT 0x543c0048, 0x04, 0x0, 0x00, 0x543c01f8 +#define IOMUXC_PAD_GPIO_IO14__LPUART8_CTS_B 0x543c0048, 0x05, 0x0, 0x00, 0x543c01f8 +#define IOMUXC_PAD_GPIO_IO14__LPUART4_TX 0x543c0048, 0x06, 0x543c0480, 0x00, 0x543c01f8 +#define IOMUXC_PAD_GPIO_IO14__FLEXIO1_FLEXIO14 0x543c0048, 0x07, 0x543c03a0, 0x00, 0x543c01f8 +#define IOMUXC_PAD_GPIO_IO15__GPIO2_IO15 0x543c004c, 0x00, 0x0, 0x00, 0x543c01fc +#define IOMUXC_PAD_GPIO_IO15__LPUART3_RX 0x543c004c, 0x01, 0x543c0470, 0x00, 0x543c01fc +#define IOMUXC_PAD_GPIO_IO15__MEDIAMIX_CAM_DATA7 0x543c004c, 0x02, 0x543c04ac, 0x00, 0x543c01fc +#define IOMUXC_PAD_GPIO_IO15__MEDIAMIX_DISP_DATA11 0x543c004c, 0x03, 0x0, 0x00, 0x543c01fc +#define IOMUXC_PAD_GPIO_IO15__LPSPI8_SCK 0x543c004c, 0x04, 0x0, 0x00, 0x543c01fc +#define IOMUXC_PAD_GPIO_IO15__LPUART8_RTS_B 0x543c004c, 0x05, 0x0, 0x00, 0x543c01fc +#define IOMUXC_PAD_GPIO_IO15__LPUART4_RX 0x543c004c, 0x06, 0x543c047c, 0x00, 0x543c01fc +#define IOMUXC_PAD_GPIO_IO15__FLEXIO1_FLEXIO15 0x543c004c, 0x07, 0x543c03a4, 0x00, 0x543c01fc +#define IOMUXC_PAD_GPIO_IO16__GPIO2_IO16 0x543c0050, 0x00, 0x0, 0x00, 0x543c0200 +#define IOMUXC_PAD_GPIO_IO16__SAI3_TX_BCLK 0x543c0050, 0x01, 0x0, 0x00, 0x543c0200 +#define IOMUXC_PAD_GPIO_IO16__PDM_BIT_STREAM2 0x543c0050, 0x02, 0x543c04cc, 0x01, 0x543c0200 +#define IOMUXC_PAD_GPIO_IO16__MEDIAMIX_DISP_DATA12 0x543c0050, 0x03, 0x0, 0x00, 0x543c0200 +#define IOMUXC_PAD_GPIO_IO16__LPUART3_CTS_B 0x543c0050, 0x04, 0x543c046c, 0x00, 0x543c0200 +#define IOMUXC_PAD_GPIO_IO16__LPSPI4_PCS2 0x543c0050, 0x05, 0x0, 0x00, 0x543c0200 +#define IOMUXC_PAD_GPIO_IO16__LPUART4_CTS_B 0x543c0050, 0x06, 0x543c0478, 0x00, 0x543c0200 +#define IOMUXC_PAD_GPIO_IO16__FLEXIO1_FLEXIO16 0x543c0050, 0x07, 0x543c03a8, 0x00, 0x543c0200 +#define IOMUXC_PAD_GPIO_IO17__GPIO2_IO17 0x543c0054, 0x00, 0x0, 0x00, 0x543c0204 +#define IOMUXC_PAD_GPIO_IO17__SAI3_MCLK 0x543c0054, 0x01, 0x0, 0x00, 0x543c0204 +#define IOMUXC_PAD_GPIO_IO17__MEDIAMIX_CAM_DATA8 0x543c0054, 0x02, 0x543c04b0, 0x00, 0x543c0204 +#define IOMUXC_PAD_GPIO_IO17__MEDIAMIX_DISP_DATA13 0x543c0054, 0x03, 0x0, 0x00, 0x543c0204 +#define IOMUXC_PAD_GPIO_IO17__LPUART3_RTS_B 0x543c0054, 0x04, 0x0, 0x00, 0x543c0204 +#define IOMUXC_PAD_GPIO_IO17__LPSPI4_PCS1 0x543c0054, 0x05, 0x0, 0x00, 0x543c0204 +#define IOMUXC_PAD_GPIO_IO17__LPUART4_RTS_B 0x543c0054, 0x06, 0x0, 0x00, 0x543c0204 +#define IOMUXC_PAD_GPIO_IO17__FLEXIO1_FLEXIO17 0x543c0054, 0x07, 0x543c03ac, 0x00, 0x543c0204 +#define IOMUXC_PAD_GPIO_IO18__GPIO2_IO18 0x543c0058, 0x00, 0x0, 0x00, 0x543c0208 +#define IOMUXC_PAD_GPIO_IO18__SAI3_RX_BCLK 0x543c0058, 0x01, 0x543c04d8, 0x00, 0x543c0208 +#define IOMUXC_PAD_GPIO_IO18__MEDIAMIX_CAM_DATA9 0x543c0058, 0x02, 0x543c04b4, 0x00, 0x543c0208 +#define IOMUXC_PAD_GPIO_IO18__MEDIAMIX_DISP_DATA14 0x543c0058, 0x03, 0x0, 0x00, 0x543c0208 +#define IOMUXC_PAD_GPIO_IO18__LPSPI5_PCS0 0x543c0058, 0x04, 0x0, 0x00, 0x543c0208 +#define IOMUXC_PAD_GPIO_IO18__LPSPI4_PCS0 0x543c0058, 0x05, 0x0, 0x00, 0x543c0208 +#define IOMUXC_PAD_GPIO_IO18__TPM5_CH2 0x543c0058, 0x06, 0x0, 0x00, 0x543c0208 +#define IOMUXC_PAD_GPIO_IO18__FLEXIO1_FLEXIO18 0x543c0058, 0x07, 0x543c03b0, 0x00, 0x543c0208 +#define IOMUXC_PAD_GPIO_IO19__GPIO2_IO19 0x543c005c, 0x00, 0x0, 0x00, 0x543c020c +#define IOMUXC_PAD_GPIO_IO19__SAI3_RX_SYNC 0x543c005c, 0x01, 0x543c04dc, 0x01, 0x543c020c +#define IOMUXC_PAD_GPIO_IO19__PDM_BIT_STREAM3 0x543c005c, 0x02, 0x543c04d0, 0x01, 0x543c020c +#define IOMUXC_PAD_GPIO_IO19__MEDIAMIX_DISP_DATA15 0x543c005c, 0x03, 0x0, 0x00, 0x543c020c +#define IOMUXC_PAD_GPIO_IO19__LPSPI5_SIN 0x543c005c, 0x04, 0x0, 0x00, 0x543c020c +#define IOMUXC_PAD_GPIO_IO19__LPSPI4_SIN 0x543c005c, 0x05, 0x0, 0x00, 0x543c020c +#define IOMUXC_PAD_GPIO_IO19__TPM6_CH2 0x543c005c, 0x06, 0x0, 0x00, 0x543c020c +#define IOMUXC_PAD_GPIO_IO19__SAI3_TX_DATA0 0x543c005c, 0x07, 0x0, 0x00, 0x543c020c +#define IOMUXC_PAD_GPIO_IO20__GPIO2_IO20 0x543c0060, 0x00, 0x0, 0x00, 0x543c0210 +#define IOMUXC_PAD_GPIO_IO20__SAI3_RX_DATA0 0x543c0060, 0x01, 0x0, 0x00, 0x543c0210 +#define IOMUXC_PAD_GPIO_IO20__PDM_BIT_STREAM0 0x543c0060, 0x02, 0x543c04c4, 0x01, 0x543c0210 +#define IOMUXC_PAD_GPIO_IO20__MEDIAMIX_DISP_DATA16 0x543c0060, 0x03, 0x0, 0x00, 0x543c0210 +#define IOMUXC_PAD_GPIO_IO20__LPSPI5_SOUT 0x543c0060, 0x04, 0x0, 0x00, 0x543c0210 +#define IOMUXC_PAD_GPIO_IO20__LPSPI4_SOUT 0x543c0060, 0x05, 0x0, 0x00, 0x543c0210 +#define IOMUXC_PAD_GPIO_IO20__TPM3_CH1 0x543c0060, 0x06, 0x0, 0x00, 0x543c0210 +#define IOMUXC_PAD_GPIO_IO20__FLEXIO1_FLEXIO20 0x543c0060, 0x07, 0x543c03b4, 0x00, 0x543c0210 +#define IOMUXC_PAD_GPIO_IO21__GPIO2_IO21 0x543c0064, 0x00, 0x0, 0x00, 0x543c0214 +#define IOMUXC_PAD_GPIO_IO21__SAI3_TX_DATA0 0x543c0064, 0x01, 0x0, 0x00, 0x543c0214 +#define IOMUXC_PAD_GPIO_IO21__PDM_CLK 0x543c0064, 0x02, 0x0, 0x00, 0x543c0214 +#define IOMUXC_PAD_GPIO_IO21__MEDIAMIX_DISP_DATA17 0x543c0064, 0x03, 0x0, 0x00, 0x543c0214 +#define IOMUXC_PAD_GPIO_IO21__LPSPI5_SCK 0x543c0064, 0x04, 0x0, 0x00, 0x543c0214 +#define IOMUXC_PAD_GPIO_IO21__LPSPI4_SCK 0x543c0064, 0x05, 0x0, 0x00, 0x543c0214 +#define IOMUXC_PAD_GPIO_IO21__TPM4_CH1 0x543c0064, 0x06, 0x0, 0x00, 0x543c0214 +#define IOMUXC_PAD_GPIO_IO21__SAI3_RX_BCLK 0x543c0064, 0x07, 0x543c04d8, 0x01, 0x543c0214 +#define IOMUXC_PAD_GPIO_IO22__GPIO2_IO22 0x543c0068, 0x00, 0x0, 0x00, 0x543c0218 +#define IOMUXC_PAD_GPIO_IO22__USDHC3_CLK 0x543c0068, 0x01, 0x543c04e8, 0x00, 0x543c0218 +#define IOMUXC_PAD_GPIO_IO22__SPDIF_IN 0x543c0068, 0x02, 0x543c04e4, 0x00, 0x543c0218 +#define IOMUXC_PAD_GPIO_IO22__MEDIAMIX_DISP_DATA18 0x543c0068, 0x03, 0x0, 0x00, 0x543c0218 +#define IOMUXC_PAD_GPIO_IO22__TPM5_CH1 0x543c0068, 0x04, 0x0, 0x00, 0x543c0218 +#define IOMUXC_PAD_GPIO_IO22__TPM6_EXTCLK 0x543c0068, 0x05, 0x0, 0x00, 0x543c0218 +#define IOMUXC_PAD_GPIO_IO22__LPI2C5_SDA 0x543c0068, 0x06, 0x543c0404, 0x01, 0x543c0218 +#define IOMUXC_PAD_GPIO_IO22__FLEXIO1_FLEXIO22 0x543c0068, 0x07, 0x543c03b8, 0x00, 0x543c0218 +#define IOMUXC_PAD_GPIO_IO23__GPIO2_IO23 0x543c006c, 0x00, 0x0, 0x00, 0x543c021c +#define IOMUXC_PAD_GPIO_IO23__USDHC3_CMD 0x543c006c, 0x01, 0x543c04ec, 0x00, 0x543c021c +#define IOMUXC_PAD_GPIO_IO23__SPDIF_OUT 0x543c006c, 0x02, 0x0, 0x00, 0x543c021c +#define IOMUXC_PAD_GPIO_IO23__MEDIAMIX_DISP_DATA19 0x543c006c, 0x03, 0x0, 0x00, 0x543c021c +#define IOMUXC_PAD_GPIO_IO23__TPM6_CH1 0x543c006c, 0x04, 0x0, 0x00, 0x543c021c +#define IOMUXC_PAD_GPIO_IO23__LPI2C5_SCL 0x543c006c, 0x06, 0x543c0400, 0x01, 0x543c021c +#define IOMUXC_PAD_GPIO_IO23__FLEXIO1_FLEXIO23 0x543c006c, 0x07, 0x543c03bc, 0x00, 0x543c021c +#define IOMUXC_PAD_GPIO_IO24__GPIO2_IO24 0x543c0070, 0x00, 0x0, 0x00, 0x543c0220 +#define IOMUXC_PAD_GPIO_IO24__USDHC3_DATA0 0x543c0070, 0x01, 0x543c04f0, 0x00, 0x543c0220 +#define IOMUXC_PAD_GPIO_IO24__MEDIAMIX_DISP_DATA20 0x543c0070, 0x03, 0x0, 0x00, 0x543c0220 +#define IOMUXC_PAD_GPIO_IO24__TPM3_CH3 0x543c0070, 0x04, 0x0, 0x00, 0x543c0220 +#define IOMUXC_PAD_GPIO_IO24__JTAG_MUX_TDO 0x543c0070, 0x05, 0x0, 0x00, 0x543c0220 +#define IOMUXC_PAD_GPIO_IO24__LPSPI6_PCS1 0x543c0070, 0x06, 0x0, 0x00, 0x543c0220 +#define IOMUXC_PAD_GPIO_IO24__FLEXIO1_FLEXIO24 0x543c0070, 0x07, 0x543c03c0, 0x00, 0x543c0220 +#define IOMUXC_PAD_GPIO_IO25__GPIO2_IO25 0x543c0074, 0x00, 0x0, 0x00, 0x543c0224 +#define IOMUXC_PAD_GPIO_IO25__USDHC3_DATA1 0x543c0074, 0x01, 0x543c04f4, 0x00, 0x543c0224 +#define IOMUXC_PAD_GPIO_IO25__CAN2_TX 0x543c0074, 0x02, 0x0, 0x00, 0x543c0224 +#define IOMUXC_PAD_GPIO_IO25__MEDIAMIX_DISP_DATA21 0x543c0074, 0x03, 0x0, 0x00, 0x543c0224 +#define IOMUXC_PAD_GPIO_IO25__TPM4_CH3 0x543c0074, 0x04, 0x0, 0x00, 0x543c0224 +#define IOMUXC_PAD_GPIO_IO25__JTAG_MUX_TCK 0x543c0074, 0x05, 0x543c03d4, 0x01, 0x543c0224 +#define IOMUXC_PAD_GPIO_IO25__LPSPI7_PCS1 0x543c0074, 0x06, 0x0, 0x00, 0x543c0224 +#define IOMUXC_PAD_GPIO_IO25__FLEXIO1_FLEXIO25 0x543c0074, 0x07, 0x543c03c4, 0x00, 0x543c0224 +#define IOMUXC_PAD_GPIO_IO26__GPIO2_IO26 0x543c0078, 0x00, 0x0, 0x00, 0x543c0228 +#define IOMUXC_PAD_GPIO_IO26__USDHC3_DATA2 0x543c0078, 0x01, 0x543c04f8, 0x00, 0x543c0228 +#define IOMUXC_PAD_GPIO_IO26__PDM_BIT_STREAM1 0x543c0078, 0x02, 0x543c04c8, 0x01, 0x543c0228 +#define IOMUXC_PAD_GPIO_IO26__MEDIAMIX_DISP_DATA22 0x543c0078, 0x03, 0x0, 0x00, 0x543c0228 +#define IOMUXC_PAD_GPIO_IO26__TPM5_CH3 0x543c0078, 0x04, 0x0, 0x00, 0x543c0228 +#define IOMUXC_PAD_GPIO_IO26__JTAG_MUX_TDI 0x543c0078, 0x05, 0x543c03d8, 0x01, 0x543c0228 +#define IOMUXC_PAD_GPIO_IO26__LPSPI8_PCS1 0x543c0078, 0x06, 0x0, 0x00, 0x543c0228 +#define IOMUXC_PAD_GPIO_IO26__SAI3_TX_SYNC 0x543c0078, 0x07, 0x543c04e0, 0x00, 0x543c0228 +#define IOMUXC_PAD_GPIO_IO27__GPIO2_IO27 0x543c007c, 0x00, 0x0, 0x00, 0x543c022c +#define IOMUXC_PAD_GPIO_IO27__USDHC3_DATA3 0x543c007c, 0x01, 0x543c04fc, 0x00, 0x543c022c +#define IOMUXC_PAD_GPIO_IO27__CAN2_RX 0x543c007c, 0x02, 0x543c0364, 0x01, 0x543c022c +#define IOMUXC_PAD_GPIO_IO27__MEDIAMIX_DISP_DATA23 0x543c007c, 0x03, 0x0, 0x00, 0x543c022c +#define IOMUXC_PAD_GPIO_IO27__TPM6_CH3 0x543c007c, 0x04, 0x0, 0x00, 0x543c022c +#define IOMUXC_PAD_GPIO_IO27__JTAG_MUX_TMS 0x543c007c, 0x05, 0x543c03dc, 0x01, 0x543c022c +#define IOMUXC_PAD_GPIO_IO27__LPSPI5_PCS1 0x543c007c, 0x06, 0x0, 0x00, 0x543c022c +#define IOMUXC_PAD_GPIO_IO27__FLEXIO1_FLEXIO27 0x543c007c, 0x07, 0x543c03c8, 0x00, 0x543c022c +#define IOMUXC_PAD_GPIO_IO28__GPIO2_IO28 0x543c0080, 0x00, 0x0, 0x00, 0x543c0230 +#define IOMUXC_PAD_GPIO_IO28__LPI2C3_SDA 0x543c0080, 0x01, 0x543c03f4, 0x01, 0x543c0230 +#define IOMUXC_PAD_GPIO_IO28__CAN1_TX 0x543c0080, 0x02, 0x0, 0x00, 0x543c0230 +#define IOMUXC_PAD_GPIO_IO28__FLEXIO1_FLEXIO28 0x543c0080, 0x07, 0x0, 0x00, 0x543c0230 +#define IOMUXC_PAD_GPIO_IO29__GPIO2_IO29 0x543c0084, 0x00, 0x0, 0x00, 0x543c0234 +#define IOMUXC_PAD_GPIO_IO29__LPI2C3_SCL 0x543c0084, 0x01, 0x543c03f0, 0x01, 0x543c0234 +#define IOMUXC_PAD_GPIO_IO29__CAN1_RX 0x543c0084, 0x02, 0x543c0360, 0x00, 0x543c0234 +#define IOMUXC_PAD_GPIO_IO29__FLEXIO1_FLEXIO29 0x543c0084, 0x07, 0x0, 0x00, 0x543c0234 +#define IOMUXC_PAD_CCM_CLKO1__CCMSRCGPCMIX_CLKO1 0x543c0088, 0x00, 0x0, 0x00, 0x543c0238 +#define IOMUXC_PAD_CCM_CLKO1__FLEXIO1_FLEXIO26 0x543c0088, 0x04, 0x0, 0x00, 0x543c0238 +#define IOMUXC_PAD_CCM_CLKO1__GPIO3_IO26 0x543c0088, 0x05, 0x0, 0x00, 0x543c0238 +#define IOMUXC_PAD_CCM_CLKO2__GPIO3_IO27 0x543c008c, 0x05, 0x0, 0x00, 0x543c023c +#define IOMUXC_PAD_CCM_CLKO2__CCMSRCGPCMIX_CLKO2 0x543c008c, 0x00, 0x0, 0x00, 0x543c023c +#define IOMUXC_PAD_CCM_CLKO2__FLEXIO1_FLEXIO27 0x543c008c, 0x04, 0x543c03c8, 0x01, 0x543c023c +#define IOMUXC_PAD_CCM_CLKO3__CCMSRCGPCMIX_CLKO3 0x543c0090, 0x00, 0x0, 0x00, 0x543c0240 +#define IOMUXC_PAD_CCM_CLKO3__FLEXIO2_FLEXIO28 0x543c0090, 0x04, 0x0, 0x00, 0x543c0240 +#define IOMUXC_PAD_CCM_CLKO3__GPIO4_IO28 0x543c0090, 0x05, 0x0, 0x00, 0x543c0240 +#define IOMUXC_PAD_CCM_CLKO4__CCMSRCGPCMIX_CLKO4 0x543c0094, 0x00, 0x0, 0x00, 0x543c0244 +#define IOMUXC_PAD_CCM_CLKO4__FLEXIO2_FLEXIO29 0x543c0094, 0x04, 0x0, 0x00, 0x543c0244 +#define IOMUXC_PAD_CCM_CLKO4__GPIO4_IO29 0x543c0094, 0x05, 0x0, 0x00, 0x543c0244 +#define IOMUXC_PAD_ENET1_MDC__ENET1_MDC 0x543c0098, 0x00, 0x0, 0x00, 0x543c0248 +#define IOMUXC_PAD_ENET1_MDC__LPUART3_DCB_B 0x543c0098, 0x01, 0x0, 0x00, 0x543c0248 +#define IOMUXC_PAD_ENET1_MDC__I3C2_SCL 0x543c0098, 0x02, 0x543c03cc, 0x00, 0x543c0248 +#define IOMUXC_PAD_ENET1_MDC__HSIOMIX_OTG_ID1 0x543c0098, 0x03, 0x0, 0x00, 0x543c0248 +#define IOMUXC_PAD_ENET1_MDC__FLEXIO2_FLEXIO0 0x543c0098, 0x04, 0x0, 0x00, 0x543c0248 +#define IOMUXC_PAD_ENET1_MDC__GPIO4_IO0 0x543c0098, 0x05, 0x0, 0x00, 0x543c0248 +#define IOMUXC_PAD_ENET1_MDC__LPI2C1_SCL 0x543c0098, 0x06, 0x543c03e0, 0x00, 0x543c0248 +#define IOMUXC_PAD_ENET1_MDIO__ENET_QOS_MDIO 0x543c009c, 0x00, 0x0, 0x00, 0x543c024c +#define IOMUXC_PAD_ENET1_MDIO__LPUART3_RIN_B 0x543c009c, 0x01, 0x0, 0x00, 0x543c024c +#define IOMUXC_PAD_ENET1_MDIO__I3C2_SDA 0x543c009c, 0x02, 0x543c03d0, 0x00, 0x543c024c +#define IOMUXC_PAD_ENET1_MDIO__HSIOMIX_OTG_PWR1 0x543c009c, 0x03, 0x0, 0x00, 0x543c024c +#define IOMUXC_PAD_ENET1_MDIO__FLEXIO2_FLEXIO1 0x543c009c, 0x04, 0x0, 0x00, 0x543c024c +#define IOMUXC_PAD_ENET1_MDIO__GPIO4_IO1 0x543c009c, 0x05, 0x0, 0x00, 0x543c024c +#define IOMUXC_PAD_ENET1_MDIO__LPI2C1_SDA 0x543c009c, 0x06, 0x543c03e4, 0x00, 0x543c024c +#define IOMUXC_PAD_ENET1_TD3__ENET_QOS_RGMII_TD3 0x543c00a0, 0x00, 0x0, 0x00, 0x543c0250 +#define IOMUXC_PAD_ENET1_TD3__CAN2_TX 0x543c00a0, 0x02, 0x0, 0x00, 0x543c0250 +#define IOMUXC_PAD_ENET1_TD3__HSIOMIX_OTG_ID2 0x543c00a0, 0x03, 0x0, 0x00, 0x543c0250 +#define IOMUXC_PAD_ENET1_TD3__FLEXIO2_FLEXIO2 0x543c00a0, 0x04, 0x0, 0x00, 0x543c0250 +#define IOMUXC_PAD_ENET1_TD3__GPIO4_IO3 0x543c00a0, 0x05, 0x0, 0x00, 0x543c0250 +#define IOMUXC_PAD_ENET1_TD3__LPI2C1_SCL 0x543c00a0, 0x06, 0x543c03e8, 0x00, 0x543c0250 +#define IOMUXC_PAD_ENET1_TD2__ENET_QOS_RGMII_TD2 0x543c00a4, 0x00, 0x0, 0x00, 0x543c0254 +#define IOMUXC_PAD_ENET1_TD2__ENET_QOS_CLOCK_GENERATE_CLK 0x543c00a4, 0x01, 0x0, 0x00, 0x543c0254 +#define IOMUXC_PAD_ENET1_TD2__CAN2_RX 0x543c00a4, 0x02, 0x543c0364, 0x02, 0x543c0254 +#define IOMUXC_PAD_ENET1_TD2__HSIOMIX_OTG_OC2 0x543c00a4, 0x03, 0x0, 0x00, 0x543c0254 +#define IOMUXC_PAD_ENET1_TD2__FLEXIO2_FLEXIO3 0x543c00a4, 0x04, 0x0, 0x00, 0x543c0254 +#define IOMUXC_PAD_ENET1_TD2__GPIO4_IO3 0x543c00a4, 0x05, 0x0, 0x00, 0x543c0254 +#define IOMUXC_PAD_ENET1_TD2__LPI2C2_SDA 0x543c00a4, 0x06, 0x543c03ec, 0x00, 0x543c0254 +#define IOMUXC_PAD_ENET1_TD1__ENET1_RGMII_TD1 0x543c00a8, 0x00, 0x0, 0x00, 0x543c0258 +#define IOMUXC_PAD_ENET1_TD1__LPUART3_RTS_B 0x543c00a8, 0x01, 0x0, 0x00, 0x543c0258 +#define IOMUXC_PAD_ENET1_TD1__I3C2_PUR 0x543c00a8, 0x02, 0x0, 0x00, 0x543c0258 +#define IOMUXC_PAD_ENET1_TD1__HSIOMIX_OTG_OC1 0x543c00a8, 0x03, 0x0, 0x00, 0x543c0258 +#define IOMUXC_PAD_ENET1_TD1__FLEXIO2_FLEXIO4 0x543c00a8, 0x04, 0x0, 0x00, 0x543c0258 +#define IOMUXC_PAD_ENET1_TD1__GPIO4_IO4 0x543c00a8, 0x05, 0x0, 0x00, 0x543c0258 +#define IOMUXC_PAD_ENET1_TD1__I3C2_PUR_B 0x543c00a8, 0x06, 0x0, 0x00, 0x543c0258 +#define IOMUXC_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0 0x543c00ac, 0x00, 0x0, 0x00, 0x543c025c +#define IOMUXC_PAD_ENET1_TD0__LPUART3_TX 0x543c00ac, 0x01, 0x543c0474, 0x01, 0x543c025c +#define IOMUXC_PAD_ENET1_TD0__FLEXIO2_FLEXIO5 0x543c00ac, 0x04, 0x0, 0x00, 0x543c025c +#define IOMUXC_PAD_ENET1_TD0__GPIO4_IO5 0x543c00ac, 0x05, 0x0, 0x00, 0x543c025c +#define IOMUXC_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x543c00b0, 0x00, 0x0, 0x00, 0x543c0260 +#define IOMUXC_PAD_ENET1_TX_CTL__LPUART3_DTR_B 0x543c00b0, 0x01, 0x0, 0x00, 0x543c0260 +#define IOMUXC_PAD_ENET1_TX_CTL__FLEXIO2_FLEXIO6 0x543c00b0, 0x04, 0x0, 0x00, 0x543c0260 +#define IOMUXC_PAD_ENET1_TX_CTL__GPIO4_IO6 0x543c00b0, 0x05, 0x0, 0x00, 0x543c0260 +#define IOMUXC_PAD_ENET1_TX_CTL__LPSPI2_SCK 0x543c00b0, 0x02, 0x543c043c, 0x00, 0x543c0260 +#define IOMUXC_PAD_ENET1_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x543c00b4, 0x00, 0x0, 0x00, 0x543c0264 +#define IOMUXC_PAD_ENET1_TXC__ENET_QOS_TX_ER 0x543c00b4, 0x01, 0x0, 0x00, 0x543c0264 +#define IOMUXC_PAD_ENET1_TXC__FLEXIO2_FLEXIO7 0x543c00b4, 0x04, 0x0, 0x00, 0x543c0264 +#define IOMUXC_PAD_ENET1_TXC__GPIO4_IO7 0x543c00b4, 0x05, 0x0, 0x00, 0x543c0264 +#define IOMUXC_PAD_ENET1_TXC__LPSPI2_SIN 0x543c00b4, 0x02, 0x543c0440, 0x00, 0x543c0264 +#define IOMUXC_PAD_ENET1_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x543c00b8, 0x00, 0x0, 0x00, 0x543c0268 +#define IOMUXC_PAD_ENET1_RX_CTL__LPUART3_DSR_B 0x543c00b8, 0x01, 0x0, 0x00, 0x543c0268 +#define IOMUXC_PAD_ENET1_RX_CTL__HSIOMIX_OTG_PWR2 0x543c00b8, 0x03, 0x0, 0x00, 0x543c0268 +#define IOMUXC_PAD_ENET1_RX_CTL__FLEXIO2_FLEXIO8 0x543c00b8, 0x04, 0x0, 0x00, 0x543c0268 +#define IOMUXC_PAD_ENET1_RX_CTL__GPIO4_IO8 0x543c00b8, 0x05, 0x0, 0x00, 0x543c0268 +#define IOMUXC_PAD_ENET1_RX_CTL__LPSPI2_PCS0 0x543c00b8, 0x02, 0x543c0434, 0x00, 0x543c0268 +#define IOMUXC_PAD_ENET1_RXC__ENET_QOS_RGMII_RXC 0x543c00bc, 0x00, 0x0, 0x00, 0x543c026c +#define IOMUXC_PAD_ENET1_RXC__ENET_QOS_RX_ER 0x543c00bc, 0x01, 0x0, 0x00, 0x543c026c +#define IOMUXC_PAD_ENET1_RXC__FLEXIO2_FLEXIO9 0x543c00bc, 0x04, 0x0, 0x00, 0x543c026c +#define IOMUXC_PAD_ENET1_RXC__GPIO4_IO9 0x543c00bc, 0x05, 0x0, 0x00, 0x543c026c +#define IOMUXC_PAD_ENET1_RXC__LPSPI2_SOUT 0x543c00bc, 0x02, 0x543c0444, 0x00, 0x543c026c +#define IOMUXC_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0 0x543c00c0, 0x00, 0x0, 0x00, 0x543c0270 +#define IOMUXC_PAD_ENET1_RD0__LPUART3_RX 0x543c00c0, 0x01, 0x543c0470, 0x01, 0x543c0270 +#define IOMUXC_PAD_ENET1_RD0__FLEXIO2_FLEXIO10 0x543c00c0, 0x04, 0x0, 0x00, 0x543c0270 +#define IOMUXC_PAD_ENET1_RD0__GPIO4_IO10 0x543c00c0, 0x05, 0x0, 0x00, 0x543c0270 +#define IOMUXC_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1 0x543c00c4, 0x00, 0x0, 0x00, 0x543c0274 +#define IOMUXC_PAD_ENET1_RD1__LPUART3_CTS_B 0x543c00c4, 0x01, 0x543c046c, 0x01, 0x543c0274 +#define IOMUXC_PAD_ENET1_RD1__LPTMR2_ALT1 0x543c00c4, 0x03, 0x543c0448, 0x00, 0x543c0274 +#define IOMUXC_PAD_ENET1_RD1__FLEXIO2_FLEXIO11 0x543c00c4, 0x04, 0x0, 0x00, 0x543c0274 +#define IOMUXC_PAD_ENET1_RD1__GPIO4_IO11 0x543c00c4, 0x05, 0x0, 0x00, 0x543c0274 +#define IOMUXC_PAD_ENET1_RD2__ENET_QOS_RGMII_RD2 0x543c00c8, 0x00, 0x0, 0x00, 0x543c0278 +#define IOMUXC_PAD_ENET1_RD2__LPTMR2_ALT2 0x543c00c8, 0x03, 0x543c044c, 0x00, 0x543c0278 +#define IOMUXC_PAD_ENET1_RD2__FLEXIO2_FLEXIO12 0x543c00c8, 0x04, 0x0, 0x00, 0x543c0278 +#define IOMUXC_PAD_ENET1_RD2__GPIO4_IO12 0x543c00c8, 0x05, 0x0, 0x00, 0x543c0278 +#define IOMUXC_PAD_ENET1_RD3__ENET_QOS_RGMII_RD3 0x543c00cc, 0x00, 0x0, 0x00, 0x543c027c +#define IOMUXC_PAD_ENET1_RD3__FLEXSPI1_TESTER_TRIGGER 0x543c00cc, 0x02, 0x0, 0x00, 0x543c027c +#define IOMUXC_PAD_ENET1_RD3__LPTMR2_ALT3 0x543c00cc, 0x03, 0x543c0450, 0x00, 0x543c027c +#define IOMUXC_PAD_ENET1_RD3__FLEXIO2_FLEXIO13 0x543c00cc, 0x04, 0x0, 0x00, 0x543c027c +#define IOMUXC_PAD_ENET1_RD3__GPIO4_IO13 0x543c00cc, 0x05, 0x0, 0x00, 0x543c027c +#define IOMUXC_PAD_ENET2_MDC__ENET2_MDC 0x543c00d0, 0x00, 0x0, 0x00, 0x543c0280 +#define IOMUXC_PAD_ENET2_MDC__LPUART4_DCB_B 0x543c00d0, 0x01, 0x0, 0x00, 0x543c0280 +#define IOMUXC_PAD_ENET2_MDC__SAI2_RX_SYNC 0x543c00d0, 0x02, 0x0, 0x00, 0x543c0280 +#define IOMUXC_PAD_ENET2_MDC__FLEXIO2_FLEXIO14 0x543c00d0, 0x04, 0x0, 0x00, 0x543c0280 +#define IOMUXC_PAD_ENET2_MDC__GPIO4_IO14 0x543c00d0, 0x05, 0x0, 0x00, 0x543c0280 +#define IOMUXC_PAD_ENET2_MDC__MEDIAMIX_CAM_CLK 0x543c00d0, 0x06, 0x543c04bc, 0x01, 0x543c0280 +#define IOMUXC_PAD_ENET2_MDIO__ENET2_MDIO 0x543c00d4, 0x00, 0x0, 0x00, 0x543c0284 +#define IOMUXC_PAD_ENET2_MDIO__LPUART4_RIN_B 0x543c00d4, 0x01, 0x0, 0x00, 0x543c0284 +#define IOMUXC_PAD_ENET2_MDIO__SAI2_RX_BCLK 0x543c00d4, 0x02, 0x0, 0x00, 0x543c0284 +#define IOMUXC_PAD_ENET2_MDIO__FLEXIO2_FLEXIO15 0x543c00d4, 0x04, 0x0, 0x00, 0x543c0284 +#define IOMUXC_PAD_ENET2_MDIO__GPIO4_IO15 0x543c00d4, 0x05, 0x0, 0x00, 0x543c0284 +#define IOMUXC_PAD_ENET2_MDIO__MEDIAMIX_CAM_DATA0 0x543c00d4, 0x06, 0x543c0490, 0x01, 0x543c0284 +#define IOMUXC_PAD_ENET2_TD3__SAI2_RX_DATA0 0x543c00d8, 0x02, 0x0, 0x00, 0x543c0288 +#define IOMUXC_PAD_ENET2_TD3__FLEXIO2_FLEXIO16 0x543c00d8, 0x04, 0x0, 0x00, 0x543c0288 +#define IOMUXC_PAD_ENET2_TD3__GPIO4_IO16 0x543c00d8, 0x05, 0x0, 0x00, 0x543c0288 +#define IOMUXC_PAD_ENET2_TD3__MEDIAMIX_CAM_VSYNC 0x543c00d8, 0x06, 0x543c04c0, 0x01, 0x543c0288 +#define IOMUXC_PAD_ENET2_TD3__ENET2_RGMII_TD3 0x543c00d8, 0x00, 0x0, 0x00, 0x543c0288 +#define IOMUXC_PAD_ENET2_TD2__ENET2_RGMII_TD2 0x543c00dc, 0x00, 0x0, 0x00, 0x543c028c +#define IOMUXC_PAD_ENET2_TD2__ENET2_TX_CLK2 0x543c00dc, 0x01, 0x0, 0x00, 0x543c028c +#define IOMUXC_PAD_ENET2_TD2__FLEXIO2_FLEXIO17 0x543c00dc, 0x04, 0x0, 0x00, 0x543c028c +#define IOMUXC_PAD_ENET2_TD2__GPIO4_IO17 0x543c00dc, 0x05, 0x0, 0x00, 0x543c028c +#define IOMUXC_PAD_ENET2_TD2__MEDIAMIX_CAM_HSYNC 0x543c00dc, 0x06, 0x543c04b8, 0x01, 0x543c028c +#define IOMUXC_PAD_ENET2_TD1__ENET2_RGMII_TD1 0x543c00e0, 0x00, 0x0, 0x00, 0x543c0290 +#define IOMUXC_PAD_ENET2_TD1__LPUART4_RTS_B 0x543c00e0, 0x01, 0x0, 0x00, 0x543c0290 +#define IOMUXC_PAD_ENET2_TD1__FLEXIO2_FLEXIO18 0x543c00e0, 0x04, 0x0, 0x00, 0x543c0290 +#define IOMUXC_PAD_ENET2_TD1__GPIO4_IO18 0x543c00e0, 0x05, 0x0, 0x00, 0x543c0290 +#define IOMUXC_PAD_ENET2_TD1__MEDIAMIX_CAM_DATA1 0x543c00e0, 0x06, 0x543c0494, 0x01, 0x543c0290 +#define IOMUXC_PAD_ENET2_TD0__ENET2_RGMII_TD0 0x543c00e4, 0x00, 0x0, 0x00, 0x543c0294 +#define IOMUXC_PAD_ENET2_TD0__LPUART4_TX 0x543c00e4, 0x01, 0x543c0480, 0x01, 0x543c0294 +#define IOMUXC_PAD_ENET2_TD0__FLEXIO2_FLEXIO19 0x543c00e4, 0x04, 0x0, 0x00, 0x543c0294 +#define IOMUXC_PAD_ENET2_TD0__GPIO4_IO19 0x543c00e4, 0x05, 0x0, 0x00, 0x543c0294 +#define IOMUXC_PAD_ENET2_TD0__MEDIAMIX_CAM_DATA2 0x543c00e4, 0x06, 0x543c0498, 0x01, 0x543c0294 +#define IOMUXC_PAD_ENET2_TX_CTL__ENET2_RGMII_TX_CTL 0x543c00e8, 0x00, 0x0, 0x00, 0x543c0298 +#define IOMUXC_PAD_ENET2_TX_CTL__LPUART4_DTR_B 0x543c00e8, 0x01, 0x0, 0x00, 0x543c0298 +#define IOMUXC_PAD_ENET2_TX_CTL__SAI2_TX_SYNC 0x543c00e8, 0x02, 0x0, 0x00, 0x543c0298 +#define IOMUXC_PAD_ENET2_TX_CTL__FLEXIO2_FLEXIO20 0x543c00e8, 0x04, 0x0, 0x00, 0x543c0298 +#define IOMUXC_PAD_ENET2_TX_CTL__GPIO4_IO20 0x543c00e8, 0x05, 0x0, 0x00, 0x543c0298 +#define IOMUXC_PAD_ENET2_TX_CTL__MEDIAMIX_CAM_DATA3 0x543c00e8, 0x06, 0x543c049c, 0x01, 0x543c0298 +#define IOMUXC_PAD_ENET2_TXC__ENET2_RGMII_TXC 0x543c00ec, 0x00, 0x0, 0x00, 0x543c029c +#define IOMUXC_PAD_ENET2_TXC__ENET2_TX_ER 0x543c00ec, 0x01, 0x0, 0x00, 0x543c029c +#define IOMUXC_PAD_ENET2_TXC__SAI2_TX_BCLK 0x543c00ec, 0x02, 0x0, 0x00, 0x543c029c +#define IOMUXC_PAD_ENET2_TXC__FLEXIO2_FLEXIO21 0x543c00ec, 0x04, 0x0, 0x00, 0x543c029c +#define IOMUXC_PAD_ENET2_TXC__GPIO4_IO21 0x543c00ec, 0x05, 0x0, 0x00, 0x543c029c +#define IOMUXC_PAD_ENET2_TXC__MEDIAMIX_CAM_DATA4 0x543c00ec, 0x06, 0x543c04a0, 0x01, 0x543c029c +#define IOMUXC_PAD_ENET2_RX_CTL__ENET2_RGMII_RX_CTL 0x543c00f0, 0x00, 0x0, 0x00, 0x543c02a0 +#define IOMUXC_PAD_ENET2_RX_CTL__LPUART4_DSR_B 0x543c00f0, 0x01, 0x0, 0x00, 0x543c02a0 +#define IOMUXC_PAD_ENET2_RX_CTL__SAI2_TX_DATA0 0x543c00f0, 0x02, 0x0, 0x00, 0x543c02a0 +#define IOMUXC_PAD_ENET2_RX_CTL__FLEXIO2_FLEXIO22 0x543c00f0, 0x04, 0x0, 0x00, 0x543c02a0 +#define IOMUXC_PAD_ENET2_RX_CTL__GPIO4_IO22 0x543c00f0, 0x05, 0x0, 0x00, 0x543c02a0 +#define IOMUXC_PAD_ENET2_RX_CTL__MEDIAMIX_CAM_DATA5 0x543c00f0, 0x06, 0x543c04a4, 0x01, 0x543c02a0 +#define IOMUXC_PAD_ENET2_RXC__ENET2_RGMII_RXC 0x543c00f4, 0x00, 0x0, 0x00, 0x543c02a4 +#define IOMUXC_PAD_ENET2_RXC__ENET2_RX_ER 0x543c00f4, 0x01, 0x0, 0x00, 0x543c02a4 +#define IOMUXC_PAD_ENET2_RXC__FLEXIO2_FLEXIO23 0x543c00f4, 0x04, 0x0, 0x00, 0x543c02a4 +#define IOMUXC_PAD_ENET2_RXC__GPIO4_IO23 0x543c00f4, 0x05, 0x0, 0x00, 0x543c02a4 +#define IOMUXC_PAD_ENET2_RXC__MEDIAMIX_CAM_DATA6 0x543c00f4, 0x06, 0x543c04a8, 0x01, 0x543c02a4 +#define IOMUXC_PAD_ENET2_RD0__ENET2_RGMII_RD0 0x543c00f8, 0x00, 0x0, 0x00, 0x543c02a8 +#define IOMUXC_PAD_ENET2_RD0__LPUART4_RX 0x543c00f8, 0x01, 0x543c047c, 0x01, 0x543c02a8 +#define IOMUXC_PAD_ENET2_RD0__FLEXIO2_FLEXIO24 0x543c00f8, 0x04, 0x0, 0x00, 0x543c02a8 +#define IOMUXC_PAD_ENET2_RD0__GPIO4_IO24 0x543c00f8, 0x05, 0x0, 0x00, 0x543c02a8 +#define IOMUXC_PAD_ENET2_RD0__MEDIAMIX_CAM_DATA7 0x543c00f8, 0x06, 0x543c04ac, 0x01, 0x543c02a8 +#define IOMUXC_PAD_ENET2_RD1__ENET2_RGMII_RD1 0x543c00fc, 0x00, 0x0, 0x00, 0x543c02ac +#define IOMUXC_PAD_ENET2_RD1__SPDIF_IN 0x543c00fc, 0x01, 0x543c04e4, 0x01, 0x543c02ac +#define IOMUXC_PAD_ENET2_RD1__FLEXIO2_FLEXIO25 0x543c00fc, 0x04, 0x0, 0x00, 0x543c02ac +#define IOMUXC_PAD_ENET2_RD1__GPIO4_IO25 0x543c00fc, 0x05, 0x0, 0x00, 0x543c02ac +#define IOMUXC_PAD_ENET2_RD1__MEDIAMIX_CAM_DATA8 0x543c00fc, 0x06, 0x543c04b0, 0x01, 0x543c02ac +#define IOMUXC_PAD_ENET2_RD2__ENET2_RGMII_RD2 0x543c0100, 0x00, 0x0, 0x00, 0x543c02b0 +#define IOMUXC_PAD_ENET2_RD2__LPUART4_CTS_B 0x543c0100, 0x01, 0x543c0478, 0x01, 0x543c02b0 +#define IOMUXC_PAD_ENET2_RD2__SAI2_MCLK 0x543c0100, 0x02, 0x0, 0x00, 0x543c02b0 +#define IOMUXC_PAD_ENET2_RD2__MQS2_RIGHT 0x543c0100, 0x03, 0x0, 0x00, 0x543c02b0 +#define IOMUXC_PAD_ENET2_RD2__FLEXIO2_FLEXIO26 0x543c0100, 0x04, 0x0, 0x00, 0x543c02b0 +#define IOMUXC_PAD_ENET2_RD2__GPIO4_IO26 0x543c0100, 0x05, 0x0, 0x00, 0x543c02b0 +#define IOMUXC_PAD_ENET2_RD2__MEDIAMIX_CAM_DATA9 0x543c0100, 0x06, 0x543c04b4, 0x01, 0x543c02b0 +#define IOMUXC_PAD_ENET2_RD3__ENET2_RGMII_RD3 0x543c0104, 0x00, 0x0, 0x00, 0x543c02b4 +#define IOMUXC_PAD_ENET2_RD3__SPDIF_OUT 0x543c0104, 0x01, 0x0, 0x00, 0x543c02b4 +#define IOMUXC_PAD_ENET2_RD3__SPDIF_IN 0x543c0104, 0x02, 0x543c04e4, 0x02, 0x543c02b4 +#define IOMUXC_PAD_ENET2_RD3__MQS2_LEFT 0x543c0104, 0x03, 0x0, 0x00, 0x543c02b4 +#define IOMUXC_PAD_ENET2_RD3__FLEXIO2_FLEXIO27 0x543c0104, 0x04, 0x0, 0x00, 0x543c02b4 +#define IOMUXC_PAD_ENET2_RD3__GPIO4_IO27 0x543c0104, 0x05, 0x0, 0x00, 0x543c02b4 +#define IOMUXC_PAD_SD1_CLK__FLEXIO1_FLEXIO8 0x543c0108, 0x04, 0x543c038c, 0x01, 0x543c02b8 +#define IOMUXC_PAD_SD1_CLK__GPIO3_IO8 0x543c0108, 0x05, 0x0, 0x00, 0x543c02b8 +#define IOMUXC_PAD_SD1_CLK__USDHC1_CLK 0x543c0108, 0x00, 0x0, 0x00, 0x543c02b8 +#define IOMUXC_PAD_SD1_CLK__LPSPI2_SCK 0x543c0108, 0x03, 0x543c043c, 0x01, 0x543c02b8 +#define IOMUXC_PAD_SD1_CMD__USDHC1_CMD 0x543c010c, 0x00, 0x0, 0x00, 0x543c02bc +#define IOMUXC_PAD_SD1_CMD__FLEXIO1_FLEXIO9 0x543c010c, 0x04, 0x543c0390, 0x01, 0x543c02bc +#define IOMUXC_PAD_SD1_CMD__GPIO3_IO9 0x543c010c, 0x05, 0x0, 0x00, 0x543c02bc +#define IOMUXC_PAD_SD1_CMD__LPSPI2_SIN 0x543c010c, 0x03, 0x543c0440, 0x01, 0x543c02bc +#define IOMUXC_PAD_SD1_DATA0__USDHC1_DATA0 0x543c0110, 0x00, 0x0, 0x00, 0x543c02c0 +#define IOMUXC_PAD_SD1_DATA0__FLEXIO1_FLEXIO10 0x543c0110, 0x04, 0x543c0394, 0x01, 0x543c02c0 +#define IOMUXC_PAD_SD1_DATA0__GPIO3_IO10 0x543c0110, 0x05, 0x0, 0x00, 0x543c02c0 +#define IOMUXC_PAD_SD1_DATA0__LPSPI2_PCS0 0x543c0110, 0x03, 0x543c0434, 0x01, 0x543c02c0 +#define IOMUXC_PAD_SD1_DATA1__USDHC1_DATA1 0x543c0114, 0x00, 0x0, 0x00, 0x543c02c4 +#define IOMUXC_PAD_SD1_DATA1__FLEXIO1_FLEXIO11 0x543c0114, 0x04, 0x543c0398, 0x01, 0x543c02c4 +#define IOMUXC_PAD_SD1_DATA1__GPIO3_IO11 0x543c0114, 0x05, 0x0, 0x00, 0x543c02c4 +#define IOMUXC_PAD_SD1_DATA1__CCMSRCGPCMIX_INT_BOOT 0x543c0114, 0x06, 0x0, 0x00, 0x543c02c4 +#define IOMUXC_PAD_SD1_DATA1__LPSPI2_SOUT 0x543c0114, 0x03, 0x543c0444, 0x01, 0x543c02c4 +#define IOMUXC_PAD_SD1_DATA2__USDHC1_DATA2 0x543c0118, 0x00, 0x0, 0x00, 0x543c02c8 +#define IOMUXC_PAD_SD1_DATA2__FLEXIO1_FLEXIO12 0x543c0118, 0x04, 0x0, 0x00, 0x543c02c8 +#define IOMUXC_PAD_SD1_DATA2__GPIO3_IO12 0x543c0118, 0x05, 0x0, 0x00, 0x543c02c8 +#define IOMUXC_PAD_SD1_DATA2__CCMSRCGPCMIX_PMIC_READY 0x543c0118, 0x06, 0x0, 0x00, 0x543c02c8 +#define IOMUXC_PAD_SD1_DATA2__LPSPI2_PCS1 0x543c0118, 0x03, 0x543c0438, 0x00, 0x543c02c8 +#define IOMUXC_PAD_SD1_DATA3__USDHC1_DATA3 0x543c011c, 0x00, 0x0, 0x00, 0x543c02cc +#define IOMUXC_PAD_SD1_DATA3__FLEXSPI1_A_SS1_B 0x543c011c, 0x01, 0x0, 0x00, 0x543c02cc +#define IOMUXC_PAD_SD1_DATA3__FLEXIO1_FLEXIO13 0x543c011c, 0x04, 0x543c039c, 0x01, 0x543c02cc +#define IOMUXC_PAD_SD1_DATA3__GPIO3_IO13 0x543c011c, 0x05, 0x0, 0x00, 0x543c02cc +#define IOMUXC_PAD_SD1_DATA3__LPSPI1_PCS1 0x543c011c, 0x03, 0x543c0424, 0x00, 0x543c02cc +#define IOMUXC_PAD_SD1_DATA4__USDHC1_DATA4 0x543c0120, 0x00, 0x0, 0x00, 0x543c02d0 +#define IOMUXC_PAD_SD1_DATA4__FLEXSPI1_A_DATA4 0x543c0120, 0x01, 0x0, 0x00, 0x543c02d0 +#define IOMUXC_PAD_SD1_DATA4__FLEXIO1_FLEXIO14 0x543c0120, 0x04, 0x543c03a0, 0x01, 0x543c02d0 +#define IOMUXC_PAD_SD1_DATA4__GPIO3_IO14 0x543c0120, 0x05, 0x0, 0x00, 0x543c02d0 +#define IOMUXC_PAD_SD1_DATA4__LPSPI1_PCS0 0x543c0120, 0x03, 0x543c0420, 0x00, 0x543c02d0 +#define IOMUXC_PAD_SD1_DATA5__USDHC1_DATA5 0x543c0124, 0x00, 0x0, 0x00, 0x543c02d4 +#define IOMUXC_PAD_SD1_DATA5__FLEXSPI1_A_DATA5 0x543c0124, 0x01, 0x0, 0x00, 0x543c02d4 +#define IOMUXC_PAD_SD1_DATA5__USDHC1_RESET_B 0x543c0124, 0x02, 0x0, 0x00, 0x543c02d4 +#define IOMUXC_PAD_SD1_DATA5__FLEXIO1_FLEXIO15 0x543c0124, 0x04, 0x543c03a4, 0x01, 0x543c02d4 +#define IOMUXC_PAD_SD1_DATA5__GPIO3_IO15 0x543c0124, 0x05, 0x0, 0x00, 0x543c02d4 +#define IOMUXC_PAD_SD1_DATA5__LPSPI1_SIN 0x543c0124, 0x03, 0x543c042c, 0x00, 0x543c02d4 +#define IOMUXC_PAD_SD1_DATA6__USDHC1_DATA6 0x543c0128, 0x00, 0x0, 0x00, 0x543c02d8 +#define IOMUXC_PAD_SD1_DATA6__FLEXSPI1_A_DATA6 0x543c0128, 0x01, 0x0, 0x00, 0x543c02d8 +#define IOMUXC_PAD_SD1_DATA6__USDHC1_CD_B 0x543c0128, 0x02, 0x0, 0x00, 0x543c02d8 +#define IOMUXC_PAD_SD1_DATA6__FLEXIO1_FLEXIO16 0x543c0128, 0x04, 0x543c03a8, 0x01, 0x543c02d8 +#define IOMUXC_PAD_SD1_DATA6__GPIO3_IO16 0x543c0128, 0x05, 0x0, 0x00, 0x543c02d8 +#define IOMUXC_PAD_SD1_DATA6__LPSPI1_SCK 0x543c0128, 0x03, 0x543c0428, 0x00, 0x543c02d8 +#define IOMUXC_PAD_SD1_DATA7__USDHC1_DATA7 0x543c012c, 0x00, 0x0, 0x00, 0x543c02dc +#define IOMUXC_PAD_SD1_DATA7__FLEXSPI1_A_DATA7 0x543c012c, 0x01, 0x0, 0x00, 0x543c02dc +#define IOMUXC_PAD_SD1_DATA7__USDHC1_WP 0x543c012c, 0x02, 0x0, 0x00, 0x543c02dc +#define IOMUXC_PAD_SD1_DATA7__FLEXIO1_FLEXIO17 0x543c012c, 0x04, 0x543c03ac, 0x01, 0x543c02dc +#define IOMUXC_PAD_SD1_DATA7__GPIO3_IO17 0x543c012c, 0x05, 0x0, 0x00, 0x543c02dc +#define IOMUXC_PAD_SD1_DATA7__LPSPI1_SOUT 0x543c012c, 0x03, 0x543c0430, 0x00, 0x543c02dc +#define IOMUXC_PAD_SD1_STROBE__USDHC1_STROBE 0x543c0130, 0x00, 0x0, 0x00, 0x543c02e0 +#define IOMUXC_PAD_SD1_STROBE__FLEXSPI1_A_DQS 0x543c0130, 0x01, 0x0, 0x00, 0x543c02e0 +#define IOMUXC_PAD_SD1_STROBE__FLEXIO1_FLEXIO18 0x543c0130, 0x04, 0x543c03b0, 0x01, 0x543c02e0 +#define IOMUXC_PAD_SD1_STROBE__GPIO3_IO18 0x543c0130, 0x05, 0x0, 0x00, 0x543c02e0 +#define IOMUXC_PAD_SD2_VSELECT__USDHC2_VSELECT 0x543c0134, 0x00, 0x0, 0x00, 0x543c02e4 +#define IOMUXC_PAD_SD2_VSELECT__USDHC2_WP 0x543c0134, 0x01, 0x0, 0x00, 0x543c02e4 +#define IOMUXC_PAD_SD2_VSELECT__LPTMR2_ALT3 0x543c0134, 0x02, 0x543c0450, 0x01, 0x543c02e4 +#define IOMUXC_PAD_SD2_VSELECT__FLEXIO1_FLEXIO19 0x543c0134, 0x04, 0x0, 0x00, 0x543c02e4 +#define IOMUXC_PAD_SD2_VSELECT__GPIO3_IO19 0x543c0134, 0x05, 0x0, 0x00, 0x543c02e4 +#define IOMUXC_PAD_SD2_VSELECT__CCMSRCGPCMIX_EXT_CLK1 0x543c0134, 0x06, 0x543c0368, 0x00, 0x543c02e4 +#define IOMUXC_PAD_SD3_CLK__USDHC3_CLK 0x543c0138, 0x00, 0x543c04e8, 0x01, 0x543c02e8 +#define IOMUXC_PAD_SD3_CLK__FLEXSPI1_A_SCLK 0x543c0138, 0x01, 0x0, 0x00, 0x543c02e8 +#define IOMUXC_PAD_SD3_CLK__LPUART1_CTS_B 0x543c0138, 0x02, 0x543c0454, 0x00, 0x543c02e8 +#define IOMUXC_PAD_SD3_CLK__FLEXIO1_FLEXIO20 0x543c0138, 0x04, 0x543c03b4, 0x01, 0x543c02e8 +#define IOMUXC_PAD_SD3_CLK__GPIO3_IO20 0x543c0138, 0x05, 0x0, 0x00, 0x543c02e8 +#define IOMUXC_PAD_SD3_CMD__USDHC3_CMD 0x543c013c, 0x00, 0x543c04ec, 0x01, 0x543c02ec +#define IOMUXC_PAD_SD3_CMD__FLEXSPI1_A_SS0_B 0x543c013c, 0x01, 0x0, 0x00, 0x543c02ec +#define IOMUXC_PAD_SD3_CMD__LPUART1_RTS_B 0x543c013c, 0x02, 0x0, 0x00, 0x543c02ec +#define IOMUXC_PAD_SD3_CMD__FLEXIO1_FLEXIO21 0x543c013c, 0x04, 0x0, 0x00, 0x543c02ec +#define IOMUXC_PAD_SD3_CMD__GPIO3_IO21 0x543c013c, 0x05, 0x0, 0x00, 0x543c02ec +#define IOMUXC_PAD_SD3_DATA0__USDHC3_DATA0 0x543c0140, 0x00, 0x543c04f0, 0x01, 0x543c02f0 +#define IOMUXC_PAD_SD3_DATA0__FLEXSPI1_A_DATA0 0x543c0140, 0x01, 0x0, 0x00, 0x543c02f0 +#define IOMUXC_PAD_SD3_DATA0__LPUART2_CTS_B 0x543c0140, 0x02, 0x543c0460, 0x00, 0x543c02f0 +#define IOMUXC_PAD_SD3_DATA0__FLEXIO1_FLEXIO22 0x543c0140, 0x04, 0x543c03b8, 0x01, 0x543c02f0 +#define IOMUXC_PAD_SD3_DATA0__GPIO3_IO22 0x543c0140, 0x05, 0x0, 0x00, 0x543c02f0 +#define IOMUXC_PAD_SD3_DATA1__USDHC3_DATA1 0x543c0144, 0x00, 0x543c04f4, 0x01, 0x543c02f4 +#define IOMUXC_PAD_SD3_DATA1__FLEXSPI1_A_DATA1 0x543c0144, 0x01, 0x0, 0x00, 0x543c02f4 +#define IOMUXC_PAD_SD3_DATA1__LPUART2_RTS_B 0x543c0144, 0x02, 0x0, 0x00, 0x543c02f4 +#define IOMUXC_PAD_SD3_DATA1__FLEXIO1_FLEXIO23 0x543c0144, 0x04, 0x543c03bc, 0x01, 0x543c02f4 +#define IOMUXC_PAD_SD3_DATA1__GPIO3_IO23 0x543c0144, 0x05, 0x0, 0x00, 0x543c02f4 +#define IOMUXC_PAD_SD3_DATA2__USDHC3_DATA2 0x543c0148, 0x00, 0x543c04f8, 0x01, 0x543c02f8 +#define IOMUXC_PAD_SD3_DATA2__LPI2C4_SDA 0x543c0148, 0x02, 0x543c03fc, 0x01, 0x543c02f8 +#define IOMUXC_PAD_SD3_DATA2__FLEXSPI1_A_DATA2 0x543c0148, 0x01, 0x0, 0x00, 0x543c02f8 +#define IOMUXC_PAD_SD3_DATA2__FLEXIO1_FLEXIO24 0x543c0148, 0x04, 0x543c03c0, 0x01, 0x543c02f8 +#define IOMUXC_PAD_SD3_DATA2__GPIO3_IO24 0x543c0148, 0x05, 0x0, 0x00, 0x543c02f8 +#define IOMUXC_PAD_SD3_DATA3__USDHC3_DATA3 0x543c014c, 0x00, 0x543c04fc, 0x01, 0x543c02fc +#define IOMUXC_PAD_SD3_DATA3__FLEXSPI1_A_DATA3 0x543c014c, 0x01, 0x0, 0x00, 0x543c02fc +#define IOMUXC_PAD_SD3_DATA3__LPI2C4_SCL 0x543c014c, 0x02, 0x543c03f8, 0x01, 0x543c02fc +#define IOMUXC_PAD_SD3_DATA3__FLEXIO1_FLEXIO25 0x543c014c, 0x04, 0x543c03c4, 0x01, 0x543c02fc +#define IOMUXC_PAD_SD3_DATA3__GPIO3_IO25 0x543c014c, 0x05, 0x0, 0x00, 0x543c02fc +#define IOMUXC_PAD_SD2_CD_B__USDHC2_CD_B 0x543c0150, 0x00, 0x0, 0x00, 0x543c0300 +#define IOMUXC_PAD_SD2_CD_B__ENET_QOS_1588_EVENT0_IN 0x543c0150, 0x01, 0x0, 0x00, 0x543c0300 +#define IOMUXC_PAD_SD2_CD_B__I3C2_SCL 0x543c0150, 0x02, 0x543c03cc, 0x01, 0x543c0300 +#define IOMUXC_PAD_SD2_CD_B__FLEXIO1_FLEXIO0 0x543c0150, 0x04, 0x543c036c, 0x01, 0x543c0300 +#define IOMUXC_PAD_SD2_CD_B__GPIO3_IO0 0x543c0150, 0x05, 0x0, 0x00, 0x543c0300 +#define IOMUXC_PAD_SD2_CD_B__LPI2C1_SCL 0x543c0150, 0x03, 0x0, 0x00, 0x543c0300 +#define IOMUXC_PAD_SD2_CLK__USDHC2_CLK 0x543c0154, 0x00, 0x0, 0x00, 0x543c0304 +#define IOMUXC_PAD_SD2_CLK__ENET_QOS_1588_EVENT0_OUT 0x543c0154, 0x01, 0x0, 0x00, 0x543c0304 +#define IOMUXC_PAD_SD2_CLK__I2C1_SDA 0x543c0154, 0x03, 0x0, 0x00, 0x543c0304 +#define IOMUXC_PAD_SD2_CLK__I3C2_SDA 0x543c0154, 0x02, 0x543c03d0, 0x01, 0x543c0304 +#define IOMUXC_PAD_SD2_CLK__FLEXIO1_FLEXIO1 0x543c0154, 0x04, 0x543c0370, 0x01, 0x543c0304 +#define IOMUXC_PAD_SD2_CLK__GPIO3_IO1 0x543c0154, 0x05, 0x0, 0x00, 0x543c0304 +#define IOMUXC_PAD_SD2_CLK__CCMSRCGPCMIX_OBSERVE0 0x543c0154, 0x06, 0x0, 0x00, 0x543c0304 +#define IOMUXC_PAD_SD2_CLK__LPI2C1_SDA 0x543c0154, 0x03, 0x543c03e4, 0x01, 0x543c0304 +#define IOMUXC_PAD_SD2_CMD__USDHC2_CMD 0x543c0158, 0x00, 0x0, 0x00, 0x543c0308 +#define IOMUXC_PAD_SD2_CMD__ENET2_1588_EVENT0_IN 0x543c0158, 0x01, 0x0, 0x00, 0x543c0308 +#define IOMUXC_PAD_SD2_CMD__I3C2_PUR 0x543c0158, 0x02, 0x0, 0x00, 0x543c0308 +#define IOMUXC_PAD_SD2_CMD__I3C2_PUR_B 0x543c0158, 0x03, 0x0, 0x00, 0x543c0308 +#define IOMUXC_PAD_SD2_CMD__FLEXIO1_FLEXIO2 0x543c0158, 0x04, 0x543c0374, 0x01, 0x543c0308 +#define IOMUXC_PAD_SD2_CMD__GPIO3_IO2 0x543c0158, 0x05, 0x0, 0x00, 0x543c0308 +#define IOMUXC_PAD_SD2_CMD__CCMSRCGPCMIX_OBSERVE1 0x543c0158, 0x06, 0x0, 0x00, 0x543c0308 +#define IOMUXC_PAD_SD2_DATA0__USDHC2_DATA0 0x543c015c, 0x00, 0x0, 0x00, 0x543c030c +#define IOMUXC_PAD_SD2_DATA0__ENET2_1588_EVENT0_OUT 0x543c015c, 0x01, 0x0, 0x00, 0x543c030c +#define IOMUXC_PAD_SD2_DATA0__CAN2_TX 0x543c015c, 0x02, 0x0, 0x00, 0x543c030c +#define IOMUXC_PAD_SD2_DATA0__FLEXIO1_FLEXIO3 0x543c015c, 0x04, 0x543c0378, 0x01, 0x543c030c +#define IOMUXC_PAD_SD2_DATA0__GPIO3_IO3 0x543c015c, 0x05, 0x0, 0x00, 0x543c030c +#define IOMUXC_PAD_SD2_DATA0__LPUART1_TX 0x543c015c, 0x03, 0x543c045c, 0x00, 0x543c030c +#define IOMUXC_PAD_SD2_DATA0__CCMSRCGPCMIX_OBSERVE2 0x543c015c, 0x06, 0x0, 0x00, 0x543c030c +#define IOMUXC_PAD_SD2_DATA1__USDHC2_DATA1 0x543c0160, 0x00, 0x0, 0x00, 0x543c0310 +#define IOMUXC_PAD_SD2_DATA1__ENET2_1588_EVENT1_IN 0x543c0160, 0x01, 0x0, 0x00, 0x543c0310 +#define IOMUXC_PAD_SD2_DATA1__CAN2_RX 0x543c0160, 0x02, 0x543c0364, 0x03, 0x543c0310 +#define IOMUXC_PAD_SD2_DATA1__FLEXIO1_FLEXIO4 0x543c0160, 0x04, 0x543c037c, 0x01, 0x543c0310 +#define IOMUXC_PAD_SD2_DATA1__GPIO3_IO4 0x543c0160, 0x05, 0x0, 0x00, 0x543c0310 +#define IOMUXC_PAD_SD2_DATA1__LPUART1_RX 0x543c0160, 0x03, 0x543c0458, 0x00, 0x543c0310 +#define IOMUXC_PAD_SD2_DATA1__CCMSRCGPCMIX_WAIT 0x543c0160, 0x06, 0x0, 0x00, 0x543c0310 +#define IOMUXC_PAD_SD2_DATA2__USDHC2_DATA2 0x543c0164, 0x00, 0x0, 0x00, 0x543c0314 +#define IOMUXC_PAD_SD2_DATA2__ENET2_1588_EVENT1_OUT 0x543c0164, 0x01, 0x0, 0x00, 0x543c0314 +#define IOMUXC_PAD_SD2_DATA2__MQS2_RIGHT 0x543c0164, 0x02, 0x0, 0x00, 0x543c0314 +#define IOMUXC_PAD_SD2_DATA2__FLEXIO1_FLEXIO5 0x543c0164, 0x04, 0x543c0380, 0x01, 0x543c0314 +#define IOMUXC_PAD_SD2_DATA2__GPIO3_IO5 0x543c0164, 0x05, 0x0, 0x00, 0x543c0314 +#define IOMUXC_PAD_SD2_DATA2__LPUART2_TX 0x543c0164, 0x03, 0x543c0468, 0x00, 0x543c0314 +#define IOMUXC_PAD_SD2_DATA2__CCMSRCGPCMIX_STOP 0x543c0164, 0x06, 0x0, 0x00, 0x543c0314 +#define IOMUXC_PAD_SD2_DATA3__USDHC2_DATA3 0x543c0168, 0x00, 0x0, 0x00, 0x543c0318 +#define IOMUXC_PAD_SD2_DATA3__LPTMR2_ALT1 0x543c0168, 0x01, 0x543c0448, 0x01, 0x543c0318 +#define IOMUXC_PAD_SD2_DATA3__MQS2_LEFT 0x543c0168, 0x02, 0x0, 0x00, 0x543c0318 +#define IOMUXC_PAD_SD2_DATA3__FLEXIO1_FLEXIO6 0x543c0168, 0x04, 0x543c0384, 0x01, 0x543c0318 +#define IOMUXC_PAD_SD2_DATA3__GPIO3_IO6 0x543c0168, 0x05, 0x0, 0x00, 0x543c0318 +#define IOMUXC_PAD_SD2_DATA3__LPUART2_RX 0x543c0168, 0x03, 0x543c0464, 0x00, 0x543c0318 +#define IOMUXC_PAD_SD2_DATA3__CCMSRCGPCMIX_EARLY_RESET 0x543c0168, 0x06, 0x0, 0x00, 0x543c0318 +#define IOMUXC_PAD_SD2_RESET_B__USDHC2_RESET_B 0x543c016c, 0x00, 0x0, 0x00, 0x543c031c +#define IOMUXC_PAD_SD2_RESET_B__LPTMR2_ALT2 0x543c016c, 0x01, 0x543c044c, 0x01, 0x543c031c +#define IOMUXC_PAD_SD2_RESET_B__FLEXIO1_FLEXIO7 0x543c016c, 0x04, 0x543c0388, 0x01, 0x543c031c +#define IOMUXC_PAD_SD2_RESET_B__GPIO3_IO7 0x543c016c, 0x05, 0x0, 0x00, 0x543c031c +#define IOMUXC_PAD_SD2_RESET_B__CCMSRCGPCMIX_SYSTEM_RESET 0x543c016c, 0x06, 0x0, 0x00, 0x543c031c +#define IOMUXC_PAD_I2C1_SCL__LPI2C1_SCL 0x543c0170, 0x00, 0x543c03e0, 0x02, 0x543c0320 +#define IOMUXC_PAD_I2C1_SCL__I3C1_SCL 0x543c0170, 0x01, 0x0, 0x00, 0x543c0320 +#define IOMUXC_PAD_I2C1_SCL__LPUART1_DCB_B 0x543c0170, 0x02, 0x0, 0x00, 0x543c0320 +#define IOMUXC_PAD_I2C1_SCL__TPM2_CH0 0x543c0170, 0x03, 0x0, 0x00, 0x543c0320 +#define IOMUXC_PAD_I2C1_SCL__GPIO1_IO0 0x543c0170, 0x05, 0x0, 0x00, 0x543c0320 +#define IOMUXC_PAD_I2C1_SDA__LPI2C1_SDA 0x543c0174, 0x00, 0x543c03e4, 0x02, 0x543c0324 +#define IOMUXC_PAD_I2C1_SDA__I3C1_SDA 0x543c0174, 0x01, 0x0, 0x00, 0x543c0324 +#define IOMUXC_PAD_I2C1_SDA__LPUART1_RIN_B 0x543c0174, 0x02, 0x0, 0x00, 0x543c0324 +#define IOMUXC_PAD_I2C1_SDA__TPM2_CH1 0x543c0174, 0x03, 0x0, 0x00, 0x543c0324 +#define IOMUXC_PAD_I2C1_SDA__GPIO1_IO1 0x543c0174, 0x05, 0x0, 0x00, 0x543c0324 +#define IOMUXC_PAD_I2C2_SCL__LPI2C2_SCL 0x543c0178, 0x00, 0x543c03e8, 0x01, 0x543c0328 +#define IOMUXC_PAD_I2C2_SCL__I3C1_PUR 0x543c0178, 0x01, 0x0, 0x00, 0x543c0328 +#define IOMUXC_PAD_I2C2_SCL__LPUART2_DCB_B 0x543c0178, 0x02, 0x0, 0x00, 0x543c0328 +#define IOMUXC_PAD_I2C2_SCL__TPM2_CH2 0x543c0178, 0x03, 0x0, 0x00, 0x543c0328 +#define IOMUXC_PAD_I2C2_SCL__SAI1_RX_SYNC 0x543c0178, 0x04, 0x0, 0x00, 0x543c0328 +#define IOMUXC_PAD_I2C2_SCL__GPIO1_IO3 0x543c0178, 0x05, 0x0, 0x00, 0x543c0328 +#define IOMUXC_PAD_I2C2_SCL__I3C1_PUR_B 0x543c0178, 0x06, 0x0, 0x00, 0x543c0328 +#define IOMUXC_PAD_I2C2_SDA__LPI2C2_SDA 0x543c017c, 0x00, 0x543c03ec, 0x01, 0x543c032c +#define IOMUXC_PAD_I2C2_SDA__LPUART2_RIN_B 0x543c017c, 0x02, 0x0, 0x00, 0x543c032c +#define IOMUXC_PAD_I2C2_SDA__TPM2_CH3 0x543c017c, 0x03, 0x0, 0x00, 0x543c032c +#define IOMUXC_PAD_I2C2_SDA__SAI1_RX_BCLK 0x543c017c, 0x04, 0x0, 0x00, 0x543c032c +#define IOMUXC_PAD_I2C2_SDA__GPIO1_IO3 0x543c017c, 0x05, 0x0, 0x00, 0x543c032c +#define IOMUXC_PAD_UART1_RXD__LPUART1_RX 0x543c0180, 0x00, 0x543c0458, 0x01, 0x543c0330 +#define IOMUXC_PAD_UART1_RXD__ELE_UART_RX 0x543c0180, 0x01, 0x0, 0x00, 0x543c0330 +#define IOMUXC_PAD_UART1_RXD__LPSPI2_SIN 0x543c0180, 0x02, 0x543c0440, 0x02, 0x543c0330 +#define IOMUXC_PAD_UART1_RXD__TPM1_CH0 0x543c0180, 0x03, 0x0, 0x00, 0x543c0330 +#define IOMUXC_PAD_UART1_RXD__GPIO1_IO4 0x543c0180, 0x05, 0x0, 0x00, 0x543c0330 +#define IOMUXC_PAD_UART1_TXD__LPUART1_TX 0x543c0184, 0x00, 0x543c045c, 0x01, 0x543c0334 +#define IOMUXC_PAD_UART1_TXD__ELE_UART_TX 0x543c0184, 0x01, 0x0, 0x00, 0x543c0334 +#define IOMUXC_PAD_UART1_TXD__LPSPI2_PCS0 0x543c0184, 0x02, 0x543c0434, 0x02, 0x543c0334 +#define IOMUXC_PAD_UART1_TXD__TPM1_CH1 0x543c0184, 0x03, 0x0, 0x00, 0x543c0334 +#define IOMUXC_PAD_UART1_TXD__GPIO1_IO5 0x543c0184, 0x05, 0x0, 0x00, 0x543c0334 +#define IOMUXC_PAD_UART2_RXD__LPUART2_RX 0x543c0188, 0x00, 0x543c0464, 0x01, 0x543c0338 +#define IOMUXC_PAD_UART2_RXD__LPUART1_CTS_B 0x543c0188, 0x01, 0x543c0454, 0x01, 0x543c0338 +#define IOMUXC_PAD_UART2_RXD__LPSPI2_SOUT 0x543c0188, 0x02, 0x543c0444, 0x02, 0x543c0338 +#define IOMUXC_PAD_UART2_RXD__TPM1_CH2 0x543c0188, 0x03, 0x0, 0x00, 0x543c0338 +#define IOMUXC_PAD_UART2_RXD__SAI1_MCLK 0x543c0188, 0x04, 0x543c04d4, 0x00, 0x543c0338 +#define IOMUXC_PAD_UART2_RXD__GPIO1_IO6 0x543c0188, 0x05, 0x0, 0x00, 0x543c0338 +#define IOMUXC_PAD_UART2_TXD__LPUART2_TX 0x543c018c, 0x00, 0x543c0468, 0x01, 0x543c033c +#define IOMUXC_PAD_UART2_TXD__LPUART1_RTS_B 0x543c018c, 0x01, 0x0, 0x00, 0x543c033c +#define IOMUXC_PAD_UART2_TXD__LPSPI2_SCK 0x543c018c, 0x02, 0x543c043c, 0x02, 0x543c033c +#define IOMUXC_PAD_UART2_TXD__TPM1_CH3 0x543c018c, 0x03, 0x0, 0x00, 0x543c033c +#define IOMUXC_PAD_UART2_TXD__GPIO1_IO7 0x543c018c, 0x05, 0x0, 0x00, 0x543c033c +#define IOMUXC_PAD_UART2_TXD__SAI3_TX_SYNC 0x543c018c, 0x07, 0x543c04e0, 0x02, 0x543c033c +#define IOMUXC_PAD_PDM_CLK__PDM_CLK 0x543c0190, 0x00, 0x0, 0x00, 0x543c0340 +#define IOMUXC_PAD_PDM_CLK__MQS1_LEFT 0x543c0190, 0x01, 0x0, 0x00, 0x543c0340 +#define IOMUXC_PAD_PDM_CLK__LPTMR1_ALT1 0x543c0190, 0x04, 0x0, 0x00, 0x543c0340 +#define IOMUXC_PAD_PDM_CLK__GPIO1_IO8 0x543c0190, 0x05, 0x0, 0x00, 0x543c0340 +#define IOMUXC_PAD_PDM_CLK__CAN1_TX 0x543c0190, 0x06, 0x0, 0x00, 0x543c0340 +#define IOMUXC_PAD_PDM_BIT_STREAM0__PDM_BIT_STREAM0 0x543c0194, 0x00, 0x543c04c4, 0x02, 0x543c0344 +#define IOMUXC_PAD_PDM_BIT_STREAM0__MQS1_RIGHT 0x543c0194, 0x01, 0x0, 0x00, 0x543c0344 +#define IOMUXC_PAD_PDM_BIT_STREAM0__LPSPI1_PCS1 0x543c0194, 0x02, 0x543c0424, 0x01, 0x543c0344 +#define IOMUXC_PAD_PDM_BIT_STREAM0__TPM1_EXTCLK 0x543c0194, 0x03, 0x0, 0x00, 0x543c0344 +#define IOMUXC_PAD_PDM_BIT_STREAM0__LPTMR1_ALT2 0x543c0194, 0x04, 0x0, 0x00, 0x543c0344 +#define IOMUXC_PAD_PDM_BIT_STREAM0__GPIO1_IO9 0x543c0194, 0x05, 0x0, 0x00, 0x543c0344 +#define IOMUXC_PAD_PDM_BIT_STREAM0__CAN1_RX 0x543c0194, 0x06, 0x543c0360, 0x01, 0x543c0344 +#define IOMUXC_PAD_PDM_BIT_STREAM1__PDM_BIT_STREAM1 0x543c0198, 0x00, 0x543c04c8, 0x02, 0x543c0348 +#define IOMUXC_PAD_PDM_BIT_STREAM1__LPSPI2_PCS1 0x543c0198, 0x02, 0x543c0438, 0x01, 0x543c0348 +#define IOMUXC_PAD_PDM_BIT_STREAM1__TPM2_EXTCLK 0x543c0198, 0x03, 0x0, 0x00, 0x543c0348 +#define IOMUXC_PAD_PDM_BIT_STREAM1__LPTMR1_ALT3 0x543c0198, 0x04, 0x0, 0x00, 0x543c0348 +#define IOMUXC_PAD_PDM_BIT_STREAM1__GPIO1_IO10 0x543c0198, 0x05, 0x0, 0x00, 0x543c0348 +#define IOMUXC_PAD_PDM_BIT_STREAM1__CCMSRCGPCMIX_EXT_CLK1 0x543c0198, 0x06, 0x543c0368, 0x01, 0x543c0348 +#define IOMUXC_PAD_SAI1_TXFS__SAI1_TX_SYNC 0x543c019c, 0x00, 0x0, 0x00, 0x543c034c +#define IOMUXC_PAD_SAI1_TXFS__SAI1_TX_DATA1 0x543c019c, 0x01, 0x0, 0x00, 0x543c034c +#define IOMUXC_PAD_SAI1_TXFS__LPSPI1_PCS0 0x543c019c, 0x02, 0x543c0420, 0x01, 0x543c034c +#define IOMUXC_PAD_SAI1_TXFS__LPUART2_DTR_B 0x543c019c, 0x03, 0x0, 0x00, 0x543c034c +#define IOMUXC_PAD_SAI1_TXFS__MQS1_LEFT 0x543c019c, 0x04, 0x0, 0x00, 0x543c034c +#define IOMUXC_PAD_SAI1_TXFS__GPIO1_IO11 0x543c019c, 0x05, 0x0, 0x00, 0x543c034c +#define IOMUXC_PAD_SAI1_TXC__SAI1_TX_BCLK 0x543c01a0, 0x00, 0x0, 0x00, 0x543c0350 +#define IOMUXC_PAD_SAI1_TXC__LPUART2_CTS_B 0x543c01a0, 0x01, 0x543c0460, 0x01, 0x543c0350 +#define IOMUXC_PAD_SAI1_TXC__LPSPI1_SIN 0x543c01a0, 0x02, 0x543c042c, 0x01, 0x543c0350 +#define IOMUXC_PAD_SAI1_TXC__LPUART1_DSR_B 0x543c01a0, 0x03, 0x0, 0x00, 0x543c0350 +#define IOMUXC_PAD_SAI1_TXC__CAN1_RX 0x543c01a0, 0x04, 0x543c0360, 0x02, 0x543c0350 +#define IOMUXC_PAD_SAI1_TXC__GPIO1_IO12 0x543c01a0, 0x05, 0x0, 0x00, 0x543c0350 +#define IOMUXC_PAD_SAI1_TXD0__SAI1_TX_DATA0 0x543c01a4, 0x00, 0x0, 0x00, 0x543c0354 +#define IOMUXC_PAD_SAI1_TXD0__LPUART2_RTS_B 0x543c01a4, 0x01, 0x0, 0x00, 0x543c0354 +#define IOMUXC_PAD_SAI1_TXD0__LPSPI1_SCK 0x543c01a4, 0x02, 0x543c0428, 0x01, 0x543c0354 +#define IOMUXC_PAD_SAI1_TXD0__LPUART1_DTR_B 0x543c01a4, 0x03, 0x0, 0x00, 0x543c0354 +#define IOMUXC_PAD_SAI1_TXD0__CAN1_TX 0x543c01a4, 0x04, 0x0, 0x00, 0x543c0354 +#define IOMUXC_PAD_SAI1_TXD0__GPIO1_IO13 0x543c01a4, 0x05, 0x0, 0x00, 0x543c0354 +#define IOMUXC_PAD_SAI1_TXD0__SAI1_MCLK 0x543c01a4, 0x06, 0x543c04d4, 0x01, 0x543c0354 +#define IOMUXC_PAD_SAI1_RXD0__SAI1_RX_DATA0 0x543c01a8, 0x00, 0x0, 0x00, 0x543c0358 +#define IOMUXC_PAD_SAI1_RXD0__SAI1_MCLK 0x543c01a8, 0x01, 0x543c04d4, 0x02, 0x543c0358 +#define IOMUXC_PAD_SAI1_RXD0__LPSPI1_SOUT 0x543c01a8, 0x02, 0x543c0430, 0x01, 0x543c0358 +#define IOMUXC_PAD_SAI1_RXD0__LPUART2_DSR_B 0x543c01a8, 0x03, 0x0, 0x00, 0x543c0358 +#define IOMUXC_PAD_SAI1_RXD0__MQS1_RIGHT 0x543c01a8, 0x04, 0x0, 0x00, 0x543c0358 +#define IOMUXC_PAD_SAI1_RXD0__GPIO1_IO14 0x543c01a8, 0x05, 0x0, 0x00, 0x543c0358 +#define IOMUXC_PAD_WDOG_ANY__WDOG1_WDOG_ANY 0x543c01ac, 0x00, 0x0, 0x00, 0x543c035c +#define IOMUXC_PAD_WDOG_ANY__GPIO1_IO15 0x543c01ac, 0x05, 0x0, 0x00, 0x543c035c +/*@}*/ + +#define IOMUXC_PAD_MUX_MODE_MASK (0x7U) +#define IOMUXC_PAD_MUX_MODE_SHIFT (0U) +#define IOMUXC_PAD_MUX_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_PAD_MUX_MODE_SHIFT)) & IOMUXC_PAD_MUX_MODE_MASK) +#define IOMUXC_PAD_SION_MASK (0x10U) +#define IOMUXC_PAD_SION_SHIFT (4U) +#define IOMUXC_PAD_SION(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_PAD_SION_SHIFT)) & IOMUXC_PAD_SION_MASK) + +#define IOMUXC_PAD_DSE_MASK (0x7EU) +#define IOMUXC_PAD_DSE_SHIFT (1U) +#define IOMUXC_PAD_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_PAD_DSE_SHIFT)) & IOMUXC_PAD_DSE_MASK) +#define IOMUXC_PAD_FSEL1_MASK (0x180U) +#define IOMUXC_PAD_FSEL1_SHIFT (7U) +#define IOMUXC_PAD_FSEL1(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_PAD_FSEL1_SHIFT)) & IOMUXC_PAD_FSEL1_MASK) +#define IOMUXC_PAD_PU_MASK (0x200U) +#define IOMUXC_PAD_PU_SHIFT (9U) +#define IOMUXC_PAD_PU(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_PAD_PU_SHIFT)) & IOMUXC_PAD_PU_MASK) +#define IOMUXC_PAD_PD_MASK (0x400U) +#define IOMUXC_PAD_PD_SHIFT (10U) +#define IOMUXC_PAD_PD(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_PAD_PD_SHIFT)) & IOMUXC_PAD_PD_MASK) +#define IOMUXC_PAD_OD_MASK (0x800U) +#define IOMUXC_PAD_OD_SHIFT (11U) +#define IOMUXC_PAD_OD(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_PAD_OD_SHIFT)) & IOMUXC_PAD_OD_MASK) +#define IOMUXC_PAD_HYS_MASK (0x1000U) +#define IOMUXC_PAD_HYS_SHIFT (11U) +#define IOMUXC_PAD_HYS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_PAD_HYS_SHIFT)) & IOMUXC_PAD_HYS_MASK) +#define IOMUXC_PAD_APC_MASK (0xFF000000U) +#define IOMUXC_PAD_APC_SHIFT (24U) +#define IOMUXC_PAD_APC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_PAD_APC_SHIFT)) & IOMUXC_PAD_APC_MASK) + +#define SECURE_ADDR_MASK (0x10000000U) +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) +#define IOMUXC_REG_ADDR(x) (x) +#else +#define IOMUXC_REG_ADDR(x) ((x) & (~SECURE_ADDR_MASK)) +#endif + +/******************************************************************************* + * APIs + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /*__cplusplus */ + +/*! @name Configuration */ +/*@{*/ + +/*! + * @brief Sets the IOMUXC pin mux mode. + * @note The first five parameters can be filled with the pin function ID macros. + * + * @param muxRegister The pin mux register + * @param muxMode The pin mux mode + * @param inputRegister The select input register + * @param inputDaisy The input daisy + * @param configRegister The config register + * @param inputOn The software input on + */ +static inline void IOMUXC_SetPinMux(uint32_t muxRegister, + uint32_t muxMode, + uint32_t inputRegister, + uint32_t inputDaisy, + uint32_t configRegister, + uint32_t inputOnfield) +{ + if (muxRegister != 0U) + { + *((volatile uint32_t *)(uintptr_t)IOMUXC_REG_ADDR(muxRegister)) = + IOMUXC_PAD_MUX_MODE(muxMode) | IOMUXC_PAD_SION(inputOnfield); + } + + if (inputRegister != 0U) + { + *((volatile uint32_t *)(uintptr_t)IOMUXC_REG_ADDR(inputRegister)) = inputDaisy; + } +} +/*! + * @brief Sets the IOMUXC pin configuration. + * @note The previous five parameters can be filled with the pin function ID macros. + * + * @param muxRegister The pin mux register + * @param muxMode The pin mux mode + * @param inputRegister The select input register + * @param inputDaisy The input daisy + * @param configRegister The config register + * @param configValue The pin config value + */ +static inline void IOMUXC_SetPinConfig(uint32_t muxRegister, + uint32_t muxMode, + uint32_t inputRegister, + uint32_t inputDaisy, + uint32_t configRegister, + uint32_t configValue) +{ + if (configRegister != 0U) + { + *((volatile uint32_t *)(uintptr_t)IOMUXC_REG_ADDR(configRegister)) = configValue; + } +} +/*@}*/ + +#if defined(__cplusplus) +} +#endif /*__cplusplus */ + +/*! @}*/ + +#endif /* _FSL_IOMUXC_H_ */ diff --git a/bsp/nxp/imx/imx91/drivers/sdk/devices/MIMX9131/fsl_device_registers.h b/bsp/nxp/imx/imx91/drivers/sdk/devices/MIMX9131/fsl_device_registers.h new file mode 100644 index 00000000000..92a7a677bbb --- /dev/null +++ b/bsp/nxp/imx/imx91/drivers/sdk/devices/MIMX9131/fsl_device_registers.h @@ -0,0 +1,33 @@ +/* + * Copyright 2014-2016 Freescale Semiconductor, Inc. + * Copyright 2016-2025 NXP + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef __FSL_DEVICE_REGISTERS_H__ +#define __FSL_DEVICE_REGISTERS_H__ + +/* + * Include the cpu specific register header files. + * + * The CPU macro should be declared in the project or makefile. + */ +#if (defined(CPU_MIMX9131CVVXJ) || defined(CPU_MIMX9131DVVXJ)) + +#define MIMX9131_SERIES + +/* CMSIS-style register definitions */ +#include "MIMX9131.h" +/* CPU specific feature definitions */ +#include "MIMX9131_features.h" + +#else + #error "No valid CPU defined!" +#endif + +#endif /* __FSL_DEVICE_REGISTERS_H__ */ + +/******************************************************************************* + * EOF + ******************************************************************************/ diff --git a/bsp/nxp/imx/imx91/drivers/sdk/devices/MIMX9131/system_MIMX9131.c b/bsp/nxp/imx/imx91/drivers/sdk/devices/MIMX9131/system_MIMX9131.c new file mode 100644 index 00000000000..618f49a25ec --- /dev/null +++ b/bsp/nxp/imx/imx91/drivers/sdk/devices/MIMX9131/system_MIMX9131.c @@ -0,0 +1,82 @@ +/* +** ################################################################### +** Processors: MIMX9131CVVXJ +** MIMX9131DVVXJ +** +** Compilers: GNU C Compiler +** IAR ANSI C/C++ Compiler for ARM +** Keil ARM C/C++ Compiler +** +** Reference manual: IMX91RM Rev.1 +** Version: rev. 1.0, 2024-11-15 +** Build: b250112 +** +** Abstract: +** Provides a system configuration function and a global variable that +** contains the system frequency. It configures the device and initializes +** the oscillator (PLL) that is part of the microcontroller device. +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2024-11-15) +** Initial version. +** +** ################################################################### +*/ + +/*! + * @file MIMX9131 + * @version 1.0 + * @date 2024-11-15 + * @brief Device specific configuration file for MIMX9131 (implementation file) + * + * Provides a system configuration function and a global variable that contains + * the system frequency. It configures the device and initializes the oscillator + * (PLL) that is part of the microcontroller device. + */ + +#include +#include "fsl_device_registers.h" + + + +/* ---------------------------------------------------------------------------- + -- Core clock + ---------------------------------------------------------------------------- */ + +uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK; + +/* ---------------------------------------------------------------------------- + -- SystemInit() + ---------------------------------------------------------------------------- */ + +void SystemInit (void) { +#if ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) + __ASM volatile("mov x0, #(3 << 20) \n\t" + "msr cpacr_el1, x0"); +#endif /* ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) */ + SystemInitHook(); + + ARM_TIMER_GetFreq(&SystemCoreClock); +} + +/* ---------------------------------------------------------------------------- + -- SystemCoreClockUpdate() + ---------------------------------------------------------------------------- */ + +void SystemCoreClockUpdate (void) { +} + +/* ---------------------------------------------------------------------------- + -- SystemInitHook() + ---------------------------------------------------------------------------- */ + +__attribute__ ((weak)) void SystemInitHook (void) { + /* Void implementation of the weak function. */ +} diff --git a/bsp/nxp/imx/imx91/drivers/sdk/devices/MIMX9131/system_MIMX9131.h b/bsp/nxp/imx/imx91/drivers/sdk/devices/MIMX9131/system_MIMX9131.h new file mode 100644 index 00000000000..c825d695612 --- /dev/null +++ b/bsp/nxp/imx/imx91/drivers/sdk/devices/MIMX9131/system_MIMX9131.h @@ -0,0 +1,101 @@ +/* +** ################################################################### +** Processors: MIMX9131CVVXJ +** MIMX9131DVVXJ +** +** Compilers: GNU C Compiler +** IAR ANSI C/C++ Compiler for ARM +** Keil ARM C/C++ Compiler +** +** Reference manual: IMX91RM Rev.1 +** Version: rev. 1.0, 2024-11-15 +** Build: b250112 +** +** Abstract: +** Provides a system configuration function and a global variable that +** contains the system frequency. It configures the device and initializes +** the oscillator (PLL) that is part of the microcontroller device. +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2024-11-15) +** Initial version. +** +** ################################################################### +*/ + +/*! + * @file MIMX9131 + * @version 1.0 + * @date 2024-11-15 + * @brief Device specific configuration file for MIMX9131 (header file) + * + * Provides a system configuration function and a global variable that contains + * the system frequency. It configures the device and initializes the oscillator + * (PLL) that is part of the microcontroller device. + */ + +#ifndef _SYSTEM_MIMX9131_H_ +#define _SYSTEM_MIMX9131_H_ /**< Symbol preventing repeated inclusion */ + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +/* Define clock source values */ +#define DEFAULT_SYSTEM_CLOCK 24000000U /* Default System clock value */ + +/** + * @brief System clock frequency (core clock) + * + * The system clock frequency supplied to the SysTick timer and the processor + * core clock. This variable can be used by the user application to setup the + * SysTick timer or configure other parameters. It may also be used by debugger to + * query the frequency of the debug timer or configure the trace clock speed + * SystemCoreClock is initialized with a correct predefined value. + */ +extern uint32_t SystemCoreClock; + +/** + * @brief Setup the microcontroller system. + * + * Typically this function configures the oscillator (PLL) that is part of the + * microcontroller device. For systems with variable clock speed it also updates + * the variable SystemCoreClock. SystemInit is called from startup_device file. + */ +void SystemInit (void); + +/** + * @brief Updates the SystemCoreClock variable. + * + * It must be called whenever the core clock is changed during program + * execution. SystemCoreClockUpdate() evaluates the clock register settings and calculates + * the current core clock. + */ +void SystemCoreClockUpdate (void); + +/** + * @brief SystemInit function hook. + * + * This weak function allows to call specific initialization code during the + * SystemInit() execution.This can be used when an application specific code needs + * to be called as close to the reset entry as possible (for example the Multicore + * Manager MCMGR_EarlyInit() function call). + * NOTE: No global r/w variables can be used in this hook function because the + * initialization of these variables happens after this function. + */ +void SystemInitHook (void); + +#ifdef __cplusplus +} +#endif + +#endif /* _SYSTEM_MIMX9131_H_ */ diff --git a/bsp/nxp/imx/imx91/drivers/sdk/devices/SConscript b/bsp/nxp/imx/imx91/drivers/sdk/devices/SConscript new file mode 100644 index 00000000000..d6dd3c32356 --- /dev/null +++ b/bsp/nxp/imx/imx91/drivers/sdk/devices/SConscript @@ -0,0 +1,13 @@ +# for module compiling +import os +from building import * + +cwd = GetCurrentDir() +objs = [] + +for item in os.listdir(cwd): + sconsfile = os.path.join(item, 'SConscript') + if os.path.isfile(os.path.join(cwd, sconsfile)): + objs += SConscript(sconsfile) + +Return('objs') diff --git a/bsp/nxp/imx/imx91/drivers/sdk/drivers/SConscript b/bsp/nxp/imx/imx91/drivers/sdk/drivers/SConscript new file mode 100644 index 00000000000..d6dd3c32356 --- /dev/null +++ b/bsp/nxp/imx/imx91/drivers/sdk/drivers/SConscript @@ -0,0 +1,13 @@ +# for module compiling +import os +from building import * + +cwd = GetCurrentDir() +objs = [] + +for item in os.listdir(cwd): + sconsfile = os.path.join(item, 'SConscript') + if os.path.isfile(os.path.join(cwd, sconsfile)): + objs += SConscript(sconsfile) + +Return('objs') diff --git a/bsp/nxp/imx/imx91/drivers/sdk/drivers/cache/SConscript b/bsp/nxp/imx/imx91/drivers/sdk/drivers/cache/SConscript new file mode 100644 index 00000000000..d6dd3c32356 --- /dev/null +++ b/bsp/nxp/imx/imx91/drivers/sdk/drivers/cache/SConscript @@ -0,0 +1,13 @@ +# for module compiling +import os +from building import * + +cwd = GetCurrentDir() +objs = [] + +for item in os.listdir(cwd): + sconsfile = os.path.join(item, 'SConscript') + if os.path.isfile(os.path.join(cwd, sconsfile)): + objs += SConscript(sconsfile) + +Return('objs') diff --git a/bsp/nxp/imx/imx91/drivers/sdk/drivers/cache/armv8-a/SConscript b/bsp/nxp/imx/imx91/drivers/sdk/drivers/cache/armv8-a/SConscript new file mode 100644 index 00000000000..3f8f39acae7 --- /dev/null +++ b/bsp/nxp/imx/imx91/drivers/sdk/drivers/cache/armv8-a/SConscript @@ -0,0 +1,17 @@ +# for module compiling +import os +from building import * + +cwd = GetCurrentDir() + +src = Glob('*.c') + +CPPPATH = [cwd] +objs = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH) + +for item in os.listdir(cwd): + sconsfile = os.path.join(item, 'SConscript') + if os.path.isfile(os.path.join(cwd, sconsfile)): + objs += SConscript(sconsfile) + +Return('objs') diff --git a/bsp/nxp/imx/imx91/drivers/sdk/drivers/cache/armv8-a/fsl_cache.c b/bsp/nxp/imx/imx91/drivers/sdk/drivers/cache/armv8-a/fsl_cache.c new file mode 100644 index 00000000000..c0d2d9d670b --- /dev/null +++ b/bsp/nxp/imx/imx91/drivers/sdk/drivers/cache/armv8-a/fsl_cache.c @@ -0,0 +1,58 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_cache.h" +#include "cache_armv8a.h" + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.cache_armv8a" +#endif + +/*! + * brief Invalidates all instruction caches by range. + * + * param address The virtual address. + * param size_byte size of the memory to be invalidated. + */ +void ICACHE_InvalidateByRange(uintptr_t address, size_t size_byte) +{ + icache_invalidate_range(address, size_byte); +} + +/*! + * brief Invalidates all data caches by range. + * + * param address The virtual address. + * param size_byte size of the memory to be invalidated. + */ +void DCACHE_InvalidateByRange(uintptr_t address, size_t size_byte) +{ + dcache_invalidate_range(address, size_byte); +} + +/*! + * brief Cleans all data caches by range. + * + * param address The virtual address. + * param size_byte size of the memory to be cleaned. + */ +void DCACHE_CleanByRange(uintptr_t address, size_t size_byte) +{ + dcache_clean_range(address, size_byte); +} + +/*! + * brief Cleans and Invalidates all data caches by range. + * + * param address The virtual address. + * param size_byte size of the memory to be cleaned and invalidated. + */ +void DCACHE_CleanInvalidateByRange(uintptr_t address, size_t size_byte) +{ + dcache_clean_invalidate_range(address, size_byte); +} diff --git a/bsp/nxp/imx/imx91/drivers/sdk/drivers/cache/armv8-a/fsl_cache.h b/bsp/nxp/imx/imx91/drivers/sdk/drivers/cache/armv8-a/fsl_cache.h new file mode 100644 index 00000000000..0ecab0ba68b --- /dev/null +++ b/bsp/nxp/imx/imx91/drivers/sdk/drivers/cache/armv8-a/fsl_cache.h @@ -0,0 +1,83 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _FSL_CACHE_H_ +#define _FSL_CACHE_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup cache_armv8a + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief cache driver version 1.0.0. */ +#define FSL_CACHE_DRIVER_VERSION (MAKE_VERSION(1, 0, 0)) +/*@}*/ + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + + +/*! + * @name Unified Cache Control for all caches + * Mainly used for many drivers for easy cache operation. + *@{ + */ + +/*! + * brief Invalidates all instruction caches by range. + * + * param address The virtual address. + * param size_byte size of the memory to be invalidated. + */ +void ICACHE_InvalidateByRange(uintptr_t address, size_t size_byte); + +/*! + * brief Invalidates all data caches by range. + * + * param address The virtual address. + * param size_byte size of the memory to be invalidated. + */ +void DCACHE_InvalidateByRange(uintptr_t address, size_t size_byte); + +/*! + * brief Cleans all data caches by range. + * + * param address The virtual address. + * param size_byte size of the memory to be cleaned. + */ +void DCACHE_CleanByRange(uintptr_t address, size_t size_byte); + +/*! + * brief Cleans and Invalidates all data caches by range. + * + * param address The virtual address. + * param size_byte size of the memory to be cleaned and invalidated. + */ +void DCACHE_CleanInvalidateByRange(uintptr_t address, size_t size_byte); + +/*@}*/ + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* _FSL_CACHE_H_*/ diff --git a/bsp/nxp/imx/imx91/drivers/sdk/drivers/common/SConscript b/bsp/nxp/imx/imx91/drivers/sdk/drivers/common/SConscript new file mode 100644 index 00000000000..62321b37009 --- /dev/null +++ b/bsp/nxp/imx/imx91/drivers/sdk/drivers/common/SConscript @@ -0,0 +1,17 @@ +# for module compiling +import os +from building import * + +cwd = GetCurrentDir() + +src = Glob('fsl_common.c') + +CPPPATH = [cwd] +objs = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH) + +for item in os.listdir(cwd): + sconsfile = os.path.join(item, 'SConscript') + if os.path.isfile(os.path.join(cwd, sconsfile)): + objs += SConscript(sconsfile) + +Return('objs') diff --git a/bsp/nxp/imx/imx91/drivers/sdk/drivers/common/fsl_common.c b/bsp/nxp/imx/imx91/drivers/sdk/drivers/common/fsl_common.c new file mode 100644 index 00000000000..d0dcc4b69fa --- /dev/null +++ b/bsp/nxp/imx/imx91/drivers/sdk/drivers/common/fsl_common.c @@ -0,0 +1,90 @@ +/* + * Copyright (c) 2015-2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021, 2025 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_common.h" + +#define SDK_MEM_MAGIC_NUMBER 12345U + +typedef struct _mem_align_control_block +{ + uint16_t identifier; /*!< Identifier for the memory control block. */ + uint16_t offset; /*!< offset from aligned address to real address */ +} mem_align_cb_t; + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.common" +#endif + +#if !((defined(__DSC__) && defined(__CW__))) +void *SDK_Malloc(size_t size, size_t alignbytes) +{ + mem_align_cb_t *p_cb = NULL; + uint32_t alignedsize; + + if ((alignbytes == 0U) || (alignbytes >= SIZE_MAX)) + { + return NULL; + } + + /* Check overflow. */ + alignedsize = (uint32_t)(unsigned int)SDK_SIZEALIGN(size, alignbytes); + if (alignedsize < size) + { + return NULL; + } + + if (alignedsize > SIZE_MAX - alignbytes - sizeof(mem_align_cb_t)) + { + return NULL; + } + + alignedsize += alignbytes + (uint32_t)sizeof(mem_align_cb_t); + + union + { + void *pointer_value; + uintptr_t unsigned_value; + } p_align_addr, p_addr; + + p_addr.pointer_value = malloc((size_t)alignedsize); + + if (p_addr.pointer_value == NULL) + { + return NULL; + } + + p_align_addr.unsigned_value = SDK_SIZEALIGN(p_addr.unsigned_value + sizeof(mem_align_cb_t), alignbytes); + + p_cb = (mem_align_cb_t *)(p_align_addr.unsigned_value - 4U); + p_cb->identifier = SDK_MEM_MAGIC_NUMBER; + p_cb->offset = (uint16_t)(p_align_addr.unsigned_value - p_addr.unsigned_value); + + return p_align_addr.pointer_value; +} + +void SDK_Free(void *ptr) +{ + union + { + void *pointer_value; + uintptr_t unsigned_value; + } p_free; + p_free.pointer_value = ptr; + mem_align_cb_t *p_cb = (mem_align_cb_t *)(p_free.unsigned_value - 4U); + + if (p_cb->identifier != SDK_MEM_MAGIC_NUMBER) + { + return; + } + + p_free.unsigned_value = p_free.unsigned_value - p_cb->offset; + + free(p_free.pointer_value); +} +#endif diff --git a/bsp/nxp/imx/imx91/drivers/sdk/drivers/common/fsl_common.h b/bsp/nxp/imx/imx91/drivers/sdk/drivers/common/fsl_common.h new file mode 100644 index 00000000000..31a594bdc02 --- /dev/null +++ b/bsp/nxp/imx/imx91/drivers/sdk/drivers/common/fsl_common.h @@ -0,0 +1,355 @@ +/* + * Copyright (c) 2015-2016, Freescale Semiconductor, Inc. + * Copyright 2016-2022,2024-2025 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef FSL_COMMON_H_ +#define FSL_COMMON_H_ + +#include +#include +#include +#include +#include + +#if defined(__ICCARM__) || (defined(__CC_ARM) || defined(__ARMCC_VERSION)) || defined(__GNUC__) +#include +#endif + +#include "fsl_device_registers.h" + +/*! + * @addtogroup ksdk_common + * @{ + */ + +/******************************************************************************* + * Configurations + ******************************************************************************/ + +/*! @brief Macro to use the default weak IRQ handler in drivers. */ +#ifndef FSL_DRIVER_TRANSFER_DOUBLE_WEAK_IRQ +#define FSL_DRIVER_TRANSFER_DOUBLE_WEAK_IRQ 1 +#endif + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @brief Construct a status code value from a group and code number. */ +#define MAKE_STATUS(group, code) ((((group)*100L) + (code))) + +/*! @brief Construct the version number for drivers. + * + * The driver version is a 32-bit number, for both 32-bit platforms(such as Cortex M) + * and 16-bit platforms(such as DSC). + * + * @verbatim + + | Unused || Major Version || Minor Version || Bug Fix | + 31 25 24 17 16 9 8 0 + + @endverbatim + */ +#define MAKE_VERSION(major, minor, bugfix) (((major)*65536L) + ((minor)*256L) + (bugfix)) + +/*! @name Driver version */ +/*! @{ */ +/*! @brief common driver version. */ +#define FSL_COMMON_DRIVER_VERSION (MAKE_VERSION(2, 6, 0)) +/*! @} */ + +/*! @name Debug console type definition. */ +/*! @{ */ +#define DEBUG_CONSOLE_DEVICE_TYPE_NONE 0U /*!< No debug console. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_UART 1U /*!< Debug console based on UART. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_LPUART 2U /*!< Debug console based on LPUART. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_LPSCI 3U /*!< Debug console based on LPSCI. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_USBCDC 4U /*!< Debug console based on USBCDC. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_FLEXCOMM 5U /*!< Debug console based on FLEXCOMM. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_IUART 6U /*!< Debug console based on i.MX UART. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_VUSART 7U /*!< Debug console based on LPC_VUSART. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_MINI_USART 8U /*!< Debug console based on LPC_USART. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_SWO 9U /*!< Debug console based on SWO. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_QSCI 10U /*!< Debug console based on QSCI. */ +/*! @} */ + +/*! @brief Status group numbers. */ +enum _status_groups +{ + kStatusGroup_Generic = 0, /*!< Group number for generic status codes. */ + kStatusGroup_FLASH = 1, /*!< Group number for FLASH status codes. */ + kStatusGroup_LPSPI = 4, /*!< Group number for LPSPI status codes. */ + kStatusGroup_FLEXIO_SPI = 5, /*!< Group number for FLEXIO SPI status codes. */ + kStatusGroup_DSPI = 6, /*!< Group number for DSPI status codes. */ + kStatusGroup_FLEXIO_UART = 7, /*!< Group number for FLEXIO UART status codes. */ + kStatusGroup_FLEXIO_I2C = 8, /*!< Group number for FLEXIO I2C status codes. */ + kStatusGroup_LPI2C = 9, /*!< Group number for LPI2C status codes. */ + kStatusGroup_UART = 10, /*!< Group number for UART status codes. */ + kStatusGroup_I2C = 11, /*!< Group number for UART status codes. */ + kStatusGroup_LPSCI = 12, /*!< Group number for LPSCI status codes. */ + kStatusGroup_LPUART = 13, /*!< Group number for LPUART status codes. */ + kStatusGroup_SPI = 14, /*!< Group number for SPI status code.*/ + kStatusGroup_XRDC = 15, /*!< Group number for XRDC status code.*/ + kStatusGroup_SEMA42 = 16, /*!< Group number for SEMA42 status code.*/ + kStatusGroup_SDHC = 17, /*!< Group number for SDHC status code */ + kStatusGroup_SDMMC = 18, /*!< Group number for SDMMC status code */ + kStatusGroup_SAI = 19, /*!< Group number for SAI status code */ + kStatusGroup_MCG = 20, /*!< Group number for MCG status codes. */ + kStatusGroup_SCG = 21, /*!< Group number for SCG status codes. */ + kStatusGroup_SDSPI = 22, /*!< Group number for SDSPI status codes. */ + kStatusGroup_FLEXIO_I2S = 23, /*!< Group number for FLEXIO I2S status codes */ + kStatusGroup_FLEXIO_MCULCD = 24, /*!< Group number for FLEXIO LCD status codes */ + kStatusGroup_FLASHIAP = 25, /*!< Group number for FLASHIAP status codes */ + kStatusGroup_FLEXCOMM_I2C = 26, /*!< Group number for FLEXCOMM I2C status codes */ + kStatusGroup_I2S = 27, /*!< Group number for I2S status codes */ + kStatusGroup_IUART = 28, /*!< Group number for IUART status codes */ + kStatusGroup_CSI = 29, /*!< Group number for CSI status codes */ + kStatusGroup_MIPI_DSI = 30, /*!< Group number for MIPI DSI status codes */ + kStatusGroup_SDRAMC = 35, /*!< Group number for SDRAMC status codes. */ + kStatusGroup_POWER = 39, /*!< Group number for POWER status codes. */ + kStatusGroup_ENET = 40, /*!< Group number for ENET status codes. */ + kStatusGroup_PHY = 41, /*!< Group number for PHY status codes. */ + kStatusGroup_TRGMUX = 42, /*!< Group number for TRGMUX status codes. */ + kStatusGroup_SMARTCARD = 43, /*!< Group number for SMARTCARD status codes. */ + kStatusGroup_LMEM = 44, /*!< Group number for LMEM status codes. */ + kStatusGroup_QSPI = 45, /*!< Group number for QSPI status codes. */ + kStatusGroup_DMA = 50, /*!< Group number for DMA status codes. */ + kStatusGroup_EDMA = 51, /*!< Group number for EDMA status codes. */ + kStatusGroup_DMAMGR = 52, /*!< Group number for DMAMGR status codes. */ + kStatusGroup_FLEXCAN = 53, /*!< Group number for FlexCAN status codes. */ + kStatusGroup_LTC = 54, /*!< Group number for LTC status codes. */ + kStatusGroup_FLEXIO_CAMERA = 55, /*!< Group number for FLEXIO CAMERA status codes. */ + kStatusGroup_LPC_SPI = 56, /*!< Group number for LPC_SPI status codes. */ + kStatusGroup_LPC_USART = 57, /*!< Group number for LPC_USART status codes. */ + kStatusGroup_DMIC = 58, /*!< Group number for DMIC status codes. */ + kStatusGroup_SDIF = 59, /*!< Group number for SDIF status codes.*/ + kStatusGroup_SPIFI = 60, /*!< Group number for SPIFI status codes. */ + kStatusGroup_OTP = 61, /*!< Group number for OTP status codes. */ + kStatusGroup_MCAN = 62, /*!< Group number for MCAN status codes. */ + kStatusGroup_CAAM = 63, /*!< Group number for CAAM status codes. */ + kStatusGroup_ECSPI = 64, /*!< Group number for ECSPI status codes. */ + kStatusGroup_USDHC = 65, /*!< Group number for USDHC status codes.*/ + kStatusGroup_LPC_I2C = 66, /*!< Group number for LPC_I2C status codes.*/ + kStatusGroup_DCP = 67, /*!< Group number for DCP status codes.*/ + kStatusGroup_MSCAN = 68, /*!< Group number for MSCAN status codes.*/ + kStatusGroup_ESAI = 69, /*!< Group number for ESAI status codes. */ + kStatusGroup_FLEXSPI = 70, /*!< Group number for FLEXSPI status codes. */ + kStatusGroup_MMDC = 71, /*!< Group number for MMDC status codes. */ + kStatusGroup_PDM = 72, /*!< Group number for MIC status codes. */ + kStatusGroup_SDMA = 73, /*!< Group number for SDMA status codes. */ + kStatusGroup_ICS = 74, /*!< Group number for ICS status codes. */ + kStatusGroup_SPDIF = 75, /*!< Group number for SPDIF status codes. */ + kStatusGroup_LPC_MINISPI = 76, /*!< Group number for LPC_MINISPI status codes. */ + kStatusGroup_HASHCRYPT = 77, /*!< Group number for Hashcrypt status codes */ + kStatusGroup_LPC_SPI_SSP = 78, /*!< Group number for LPC_SPI_SSP status codes. */ + kStatusGroup_I3C = 79, /*!< Group number for I3C status codes */ + kStatusGroup_LPC_I2C_1 = 97, /*!< Group number for LPC_I2C_1 status codes. */ + kStatusGroup_NOTIFIER = 98, /*!< Group number for NOTIFIER status codes. */ + kStatusGroup_DebugConsole = 99, /*!< Group number for debug console status codes. */ + kStatusGroup_SEMC = 100, /*!< Group number for SEMC status codes. */ + kStatusGroup_ApplicationRangeStart = 101, /*!< Starting number for application groups. */ + kStatusGroup_IAP = 102, /*!< Group number for IAP status codes */ + kStatusGroup_SFA = 103, /*!< Group number for SFA status codes*/ + kStatusGroup_SPC = 104, /*!< Group number for SPC status codes. */ + kStatusGroup_PUF = 105, /*!< Group number for PUF status codes. */ + kStatusGroup_TOUCH_PANEL = 106, /*!< Group number for touch panel status codes */ + kStatusGroup_VBAT = 107, /*!< Group number for VBAT status codes */ + kStatusGroup_XSPI = 108, /*!< Group number for XSPI status codes */ + kStatusGroup_PNGDEC = 109, /*!< Group number for PNGDEC status codes */ + kStatusGroup_JPEGDEC = 110, /*!< Group number for JPEGDEC status codes */ + + kStatusGroup_HAL_GPIO = 121, /*!< Group number for HAL GPIO status codes. */ + kStatusGroup_HAL_UART = 122, /*!< Group number for HAL UART status codes. */ + kStatusGroup_HAL_TIMER = 123, /*!< Group number for HAL TIMER status codes. */ + kStatusGroup_HAL_SPI = 124, /*!< Group number for HAL SPI status codes. */ + kStatusGroup_HAL_I2C = 125, /*!< Group number for HAL I2C status codes. */ + kStatusGroup_HAL_FLASH = 126, /*!< Group number for HAL FLASH status codes. */ + kStatusGroup_HAL_PWM = 127, /*!< Group number for HAL PWM status codes. */ + kStatusGroup_HAL_RNG = 128, /*!< Group number for HAL RNG status codes. */ + kStatusGroup_HAL_I2S = 129, /*!< Group number for HAL I2S status codes. */ + kStatusGroup_HAL_ADC_SENSOR = 130, /*!< Group number for HAL ADC SENSOR status codes. */ + kStatusGroup_TIMERMANAGER = 135, /*!< Group number for TiMER MANAGER status codes. */ + kStatusGroup_SERIALMANAGER = 136, /*!< Group number for SERIAL MANAGER status codes. */ + kStatusGroup_LED = 137, /*!< Group number for LED status codes. */ + kStatusGroup_BUTTON = 138, /*!< Group number for BUTTON status codes. */ + kStatusGroup_EXTERN_EEPROM = 139, /*!< Group number for EXTERN EEPROM status codes. */ + kStatusGroup_SHELL = 140, /*!< Group number for SHELL status codes. */ + kStatusGroup_MEM_MANAGER = 141, /*!< Group number for MEM MANAGER status codes. */ + kStatusGroup_LIST = 142, /*!< Group number for List status codes. */ + kStatusGroup_OSA = 143, /*!< Group number for OSA status codes. */ + kStatusGroup_COMMON_TASK = 144, /*!< Group number for Common task status codes. */ + kStatusGroup_MSG = 145, /*!< Group number for messaging status codes. */ + kStatusGroup_SDK_OCOTP = 146, /*!< Group number for OCOTP status codes. */ + kStatusGroup_SDK_FLEXSPINOR = 147, /*!< Group number for FLEXSPINOR status codes.*/ + kStatusGroup_CODEC = 148, /*!< Group number for codec status codes. */ + kStatusGroup_ASRC = 149, /*!< Group number for codec status ASRC. */ + kStatusGroup_OTFAD = 150, /*!< Group number for codec status codes. */ + kStatusGroup_SDIOSLV = 151, /*!< Group number for SDIOSLV status codes. */ + kStatusGroup_MECC = 152, /*!< Group number for MECC status codes. */ + kStatusGroup_ENET_QOS = 153, /*!< Group number for ENET_QOS status codes. */ + kStatusGroup_LOG = 154, /*!< Group number for LOG status codes. */ + kStatusGroup_I3CBUS = 155, /*!< Group number for I3CBUS status codes. */ + kStatusGroup_QSCI = 156, /*!< Group number for QSCI status codes. */ + kStatusGroup_ELEMU = 157, /*!< Group number for ELEMU status codes. */ + kStatusGroup_QUEUEDSPI = 158, /*!< Group number for QSPI status codes. */ + kStatusGroup_POWER_MANAGER = 159, /*!< Group number for POWER_MANAGER status codes. */ + kStatusGroup_IPED = 160, /*!< Group number for IPED status codes. */ + kStatusGroup_ELS_PKC = 161, /*!< Group number for ELS PKC status codes. */ + kStatusGroup_CSS_PKC = 162, /*!< Group number for CSS PKC status codes. */ + kStatusGroup_HOSTIF = 163, /*!< Group number for HOSTIF status codes. */ + kStatusGroup_CLIF = 164, /*!< Group number for CLIF status codes. */ + kStatusGroup_BMA = 165, /*!< Group number for BMA status codes. */ + kStatusGroup_NETC = 166, /*!< Group number for NETC status codes. */ + kStatusGroup_ELE = 167, /*!< Group number for ELE status codes. */ + kStatusGroup_GLIKEY = 168, /*!< Group number for GLIKEY status codes. */ + kStatusGroup_AON_POWER = 169, /*!< Group number for AON_POWER status codes. */ + kStatusGroup_AON_COMMON = 170, /*!< Group number for AON_COMMON status codes. */ + kStatusGroup_ENDAT3 = 171, /*!< Group number for ENDAT3 status codes. */ + kStatusGroup_HIPERFACE = 172, /*!< Group number for HIPERFACE status codes. */ + kStatusGroup_NPX = 173, /*!< Group number for NPX status codes. */ + kStatusGroup_ELA_CSEC = 174, /*!< Group number for ELA_CSEC status codes. */ + kStatusGroup_FLEXIO_T_FORMAT= 175, /*!< Group number for T-format status codes. */ + kStatusGroup_FLEXIO_A_FORMAT= 176, /*!< Group number for A-format status codes. */ +}; + +/*! \public + * @brief Generic status return codes. + */ +enum +{ + kStatus_Success = MAKE_STATUS(kStatusGroup_Generic, 0), /*!< Generic status for Success. */ + kStatus_Fail = MAKE_STATUS(kStatusGroup_Generic, 1), /*!< Generic status for Fail. */ + kStatus_ReadOnly = MAKE_STATUS(kStatusGroup_Generic, 2), /*!< Generic status for read only failure. */ + kStatus_OutOfRange = MAKE_STATUS(kStatusGroup_Generic, 3), /*!< Generic status for out of range access. */ + kStatus_InvalidArgument = MAKE_STATUS(kStatusGroup_Generic, 4), /*!< Generic status for invalid argument check. */ + kStatus_Timeout = MAKE_STATUS(kStatusGroup_Generic, 5), /*!< Generic status for timeout. */ + kStatus_NoTransferInProgress = + MAKE_STATUS(kStatusGroup_Generic, 6), /*!< Generic status for no transfer in progress. */ + kStatus_Busy = MAKE_STATUS(kStatusGroup_Generic, 7), /*!< Generic status for module is busy. */ + kStatus_NoData = + MAKE_STATUS(kStatusGroup_Generic, 8), /*!< Generic status for no data is found for the operation. */ +}; + +/*! @brief Type used for all status and error return values. */ +typedef int32_t status_t; + +#ifdef __ZEPHYR__ +#include +#else +/*! + * @name Min/max macros + * @{ + */ +#if !defined(MIN) +/*! Computes the minimum of \a a and \a b. */ +#define MIN(a, b) (((a) < (b)) ? (a) : (b)) +#endif + +#if !defined(MAX) +/*! Computes the maximum of \a a and \a b. */ +#define MAX(a, b) (((a) > (b)) ? (a) : (b)) +#endif +/*! @} */ + +/*! @brief Computes the number of elements in an array. */ +#if !defined(ARRAY_SIZE) +#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0])) +#endif +#endif /* __ZEPHYR__ */ + +/*! @name UINT16_MAX/UINT32_MAX value */ +/*! @{ */ +#if !defined(UINT16_MAX) +/*! Max value of uint16_t type. */ +#define UINT16_MAX ((uint16_t)-1) +#endif + +#if !defined(UINT32_MAX) +/*! Max value of uint32_t type. */ +#define UINT32_MAX ((uint32_t)-1) +#endif +/*! @} */ + +/*! Macro to get upper 32 bits of a 64-bit value */ +#if !defined(UINT64_H) +#define UINT64_H(X) ((uint32_t)((((uint64_t) (X)) >> 32U) & 0x0FFFFFFFFULL)) +#endif + +/*! Macro to get lower 32 bits of a 64-bit value */ +#if !defined(UINT64_L) +#define UINT64_L(X) ((uint32_t)(((uint64_t) (X)) & 0x0FFFFFFFFULL)) +#endif + +/*! + * @def SUPPRESS_FALL_THROUGH_WARNING() + * + * For switch case code block, if case section ends without "break;" statement, there wil be + * fallthrough warning with compiler flag -Wextra or -Wimplicit-fallthrough=n when using armgcc. + * To suppress this warning, "SUPPRESS_FALL_THROUGH_WARNING();" need to be added at the end of each + * case section which misses "break;"statement. + */ +#if defined(__GNUC__) && !defined(__ARMCC_VERSION) +#define SUPPRESS_FALL_THROUGH_WARNING() __attribute__((fallthrough)) +#else +#define SUPPRESS_FALL_THROUGH_WARNING() +#endif + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +#if !((defined(__DSC__) && defined(__CW__))) +/*! + * @brief Allocate memory with given alignment and aligned size. + * + * This is provided to support the dynamically allocated memory + * used in cache-able region. + * @param size The length required to malloc. + * @param alignbytes The alignment size. + * @retval The allocated memory. + */ +void *SDK_Malloc(size_t size, size_t alignbytes); + +/*! + * @brief Free memory. + * + * @param ptr The memory to be release. + */ +void SDK_Free(void *ptr); +#endif + +/*! + * @brief Delay at least for some time. + * Please note that, this API uses while loop for delay, different run-time environments make the time not precise, + * if precise delay count was needed, please implement a new delay function with hardware timer. + * + * @param delayTime_us Delay time in unit of microsecond. + * @param coreClock_Hz Core clock frequency with Hz. + */ +void SDK_DelayAtLeastUs(uint32_t delayTime_us, uint32_t coreClock_Hz); + +#if defined(__cplusplus) +} +#endif + +/*! @} */ + +#if (defined(__DSC__) && defined(__CW__)) +#include "fsl_common_dsc.h" +#elif defined(__XTENSA__) +#include "fsl_common_dsp.h" +#elif defined(__riscv) +#include "fsl_common_riscv.h" +#else +#include "fsl_common_arm.h" +#endif + +#endif /* FSL_COMMON_H_ */ diff --git a/bsp/nxp/imx/imx91/drivers/sdk/drivers/common/fsl_common_arm.c b/bsp/nxp/imx/imx91/drivers/sdk/drivers/common/fsl_common_arm.c new file mode 100644 index 00000000000..28e3dc89d24 --- /dev/null +++ b/bsp/nxp/imx/imx91/drivers/sdk/drivers/common/fsl_common_arm.c @@ -0,0 +1,369 @@ +/* + * Copyright (c) 2015-2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021,2023,2024 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_common.h" + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.common_arm" +#endif + +#ifndef __GIC_PRIO_BITS +#if defined(ENABLE_RAM_VECTOR_TABLE) +uint32_t InstallIRQHandler(IRQn_Type irq, uint32_t irqHandler) +{ +#ifdef __VECTOR_TABLE +#undef __VECTOR_TABLE +#endif + + if (((int32_t)irq + 16) < 0) + { + return MSDK_INVALID_IRQ_HANDLER; + } + +/* Addresses for VECTOR_TABLE and VECTOR_RAM come from the linker file */ +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) + extern uint32_t Image$$VECTOR_ROM$$Base[]; + extern uint32_t Image$$VECTOR_RAM$$Base[]; + extern uint32_t Image$$VECTOR_RAM$$ZI$$Limit[]; + +#define __VECTOR_TABLE Image$$VECTOR_ROM$$Base +#define __VECTOR_RAM Image$$VECTOR_RAM$$Base +#define __RAM_VECTOR_TABLE_SIZE (((uint32_t)Image$$VECTOR_RAM$$ZI$$Limit - (uint32_t)Image$$VECTOR_RAM$$Base)) +#elif defined(__ICCARM__) + extern uint32_t __RAM_VECTOR_TABLE_SIZE[]; + extern uint32_t __VECTOR_TABLE[]; + extern uint32_t __VECTOR_RAM[]; +#elif defined(__GNUC__) + extern uint32_t __VECTOR_TABLE[]; + extern uint32_t __VECTOR_RAM[]; + extern uint32_t __RAM_VECTOR_TABLE_SIZE_BYTES[]; + uint32_t __RAM_VECTOR_TABLE_SIZE = (uint32_t)(__RAM_VECTOR_TABLE_SIZE_BYTES); +#endif /* defined(__CC_ARM) || defined(__ARMCC_VERSION) */ + uint32_t n; + uint32_t ret; + uint32_t irqMaskValue; + + irqMaskValue = DisableGlobalIRQ(); + if (SCB->VTOR != (uint32_t)__VECTOR_RAM) + { + /* Copy the vector table from ROM to RAM */ + for (n = 0; n < ((uint32_t)__RAM_VECTOR_TABLE_SIZE) / sizeof(uint32_t); n++) + { + __VECTOR_RAM[n] = __VECTOR_TABLE[n]; + } + /* Point the VTOR to the position of vector table */ + SCB->VTOR = (uint32_t)__VECTOR_RAM; + } + + ret = __VECTOR_RAM[(int32_t)irq + 16]; + /* make sure the __VECTOR_RAM is noncachable */ + __VECTOR_RAM[(int32_t)irq + 16] = irqHandler; + + EnableGlobalIRQ(irqMaskValue); + + return ret; +} +#endif /* ENABLE_RAM_VECTOR_TABLE. */ +#endif /* __GIC_PRIO_BITS. */ + +#if (defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0)) + +/* + * When FSL_FEATURE_POWERLIB_EXTEND is defined to non-zero value, + * powerlib should be used instead of these functions. + */ +#if !(defined(FSL_FEATURE_POWERLIB_EXTEND) && (FSL_FEATURE_POWERLIB_EXTEND != 0)) + +/* + * When the SYSCON STARTER registers are discontinuous, these functions are + * implemented in fsl_power.c. + */ +#if !(defined(FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS) && FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS) + +void EnableDeepSleepIRQ(IRQn_Type interrupt) +{ + uint32_t intNumber = (uint32_t)interrupt; + + uint32_t index = 0; + + while (intNumber >= 32u) + { + index++; + intNumber -= 32u; + } + + SYSCON->STARTERSET[index] = 1UL << intNumber; + (void)EnableIRQ(interrupt); /* also enable interrupt at NVIC */ +} + +void DisableDeepSleepIRQ(IRQn_Type interrupt) +{ + uint32_t intNumber = (uint32_t)interrupt; + + (void)DisableIRQ(interrupt); /* also disable interrupt at NVIC */ + uint32_t index = 0; + + while (intNumber >= 32u) + { + index++; + intNumber -= 32u; + } + + SYSCON->STARTERCLR[index] = 1UL << intNumber; +} +#endif /* FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS */ +#endif /* FSL_FEATURE_POWERLIB_EXTEND */ +#endif /* FSL_FEATURE_SOC_SYSCON_COUNT */ + +#if defined(DWT) +/* Use WDT. */ +void MSDK_EnableCpuCycleCounter(void) +{ + /* Make sure the DWT trace fucntion is enabled. */ + if (CoreDebug_DEMCR_TRCENA_Msk != (CoreDebug_DEMCR_TRCENA_Msk & CoreDebug->DEMCR)) + { + CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk; + } + + /* CYCCNT not supported on this device. */ + assert(DWT_CTRL_NOCYCCNT_Msk != (DWT->CTRL & DWT_CTRL_NOCYCCNT_Msk)); + + /* Read CYCCNT directly if CYCCENT has already been enabled, otherwise enable CYCCENT first. */ + if (DWT_CTRL_CYCCNTENA_Msk != (DWT_CTRL_CYCCNTENA_Msk & DWT->CTRL)) + { + DWT->CTRL |= DWT_CTRL_CYCCNTENA_Msk; + } +} + +uint32_t MSDK_GetCpuCycleCount(void) +{ + return DWT->CYCCNT; +} +#endif /* defined(DWT) */ + +#if !(defined(SDK_DELAY_USE_DWT) && defined(DWT)) +/* Use software loop. */ +#if defined(__CC_ARM) /* This macro is arm v5 specific */ +/* clang-format off */ +__ASM static void DelayLoop(uint32_t count) +{ +loop + SUBS R0, R0, #1 + CMP R0, #0 + BNE loop + BX LR +} +#elif defined(__ARM_ARCH_8A__) /* This macro is ARMv8-A specific */ +static void DelayLoop(uint32_t count) +{ + __ASM volatile(" MOV X0, %0" : : "r"(count)); + __ASM volatile( + "loop%=: \n" + " SUB X0, X0, #1 \n" + " CMP X0, #0 \n" + + " BNE loop%= \n" + : + : + : "r0"); +} +/* clang-format on */ +#elif defined(__ARMCC_VERSION) || defined(__ICCARM__) || defined(__GNUC__) +/* Cortex-M0 has a smaller instruction set, SUBS isn't supported in thumb-16 mode reported from __GNUC__ compiler, + * use SUB and CMP here for compatibility */ +static void DelayLoop(uint32_t count) +{ + __ASM volatile(" MOV R0, %0" : : "r"(count)); + __ASM volatile( + "loop%=: \n" +#if defined(__GNUC__) && !defined(__ARMCC_VERSION) + " SUB R0, R0, #1 \n" +#else + " SUBS R0, R0, #1 \n" +#endif + " CMP R0, #0 \n" + + " BNE loop%= \n" + : + : + : "r0"); +} +#endif /* defined(__CC_ARM) */ +#endif /* defined(SDK_DELAY_USE_DWT) && defined(DWT) */ + +/*! + * @brief Delay at least for some time. + * Please note that, if not uses DWT, this API will use while loop for delay, different run-time environments have + * effect on the delay time. If precise delay is needed, please enable DWT delay. The two parmeters delayTime_us and + * coreClock_Hz have limitation. For example, in the platform with 1GHz coreClock_Hz, the delayTime_us only supports + * up to 4294967 in current code. If long time delay is needed, please implement a new delay function. + * + * @param delayTime_us Delay time in unit of microsecond. + * @param coreClock_Hz Core clock frequency with Hz. + */ +void SDK_DelayAtLeastUs(uint32_t delayTime_us, uint32_t coreClock_Hz) +{ + uint64_t count; + + if (delayTime_us > 0U) + { + count = USEC_TO_COUNT(delayTime_us, coreClock_Hz); + + assert(count <= UINT32_MAX); + +#if defined(SDK_DELAY_USE_DWT) && defined(DWT) /* Use DWT for better accuracy */ + + MSDK_EnableCpuCycleCounter(); + /* Calculate the count ticks. */ + count += MSDK_GetCpuCycleCount(); + + if (count > UINT32_MAX) + { + count -= UINT32_MAX; + /* Wait for cyccnt overflow. */ + while (count < MSDK_GetCpuCycleCount()) + { + } + } + + /* Wait for cyccnt reach count value. */ + while (count > MSDK_GetCpuCycleCount()) + { + } +#else +#if defined(__CORTEX_Axx) && ((__CORTEX_Axx == 53) || (__CORTEX_Axx == 55)) + /* + * Cortex-A53/A55 execution throughput: + * - SUB/CMP: 2 instructions per cycle + * - BNE: 1 instruction per cycle + * So, each loop takes 2 CPU cycles. + */ + count = count / 2U; +#elif (__CORTEX_M == 7) + /* Divide value may be different in various environment to ensure delay is precise. + * Every loop count includes three instructions, due to Cortex-M7 sometimes executes + * two instructions in one period, through test here set divide 1.5. Other M cores use + * divide 4. By the way, divide 1.5 or 4 could let the count lose precision, but it does + * not matter because other instructions outside while loop is enough to fill the time. + */ + count = count / 3U * 2U; +#else + count = count / 4U; +#endif + DelayLoop((uint32_t)count); +#endif /* defined(SDK_DELAY_USE_DWT) && defined(DWT) */ + } +} + +#if defined(FSL_FEATURE_MEASURE_CRITICAL_SECTION) && FSL_FEATURE_MEASURE_CRITICAL_SECTION +/* Use shall define their own IDs, FSL_FEATURE_CRITICAL_SECTION_MAX_ID and FSL_FEATURE_CRITICAL_SECTION_INVALID_ID + for the critical sections if want to use the critical section measurement. + */ +#ifndef FSL_FEATURE_CRITICAL_SECTION_MAX_ID +#define FSL_FEATURE_CRITICAL_SECTION_MAX_ID 0xFFU +#endif + +#ifndef FSL_FEATURE_CRITICAL_SECTION_INVALID_ID +#define FSL_FEATURE_CRITICAL_SECTION_INVALID_ID 0U +#endif + +typedef struct +{ + uint32_t id; /*!< The id of the critical section, defined by user. */ + uint32_t startTime; /*!< The timestamp for the start of the critical section. */ + uint32_t dur_max[FSL_FEATURE_CRITICAL_SECTION_MAX_ID]; /*!< The maximum duration of the section's previous executions. */ + uint32_t execution_times[FSL_FEATURE_CRITICAL_SECTION_MAX_ID]; /*!< How many times the section is executed. */ + getTimestamp_t getTimestamp; /*!< Function to get the current time stamp. */ +} critical_section_measurement_t; + +static critical_section_measurement_t s_critical_section_measurement_context; + +/*! + * brief Initialize the context of the critical section measurement and assign + * the function to get the current timestamp. + * + * param func The function to get the current timestamp. + */ +void InitCriticalSectionMeasurementContext(getTimestamp_t func) +{ + assert(func != NULL); + + (void)memset(&s_critical_section_measurement_context, 0, sizeof(critical_section_measurement_t)); + + s_critical_section_measurement_context.getTimestamp = func; +} + +/*! + * brief Disable the global IRQ with critical section ID + * + * Extended function of DisableGlobalIRQ. Apart from the standard operation, also check + * the id of the protected critical section and mark the begining for timer. + * User is required to provided the primask register for the EnableGlobalIRQEx. + * + * param id The id for critical section. + * return Current primask value. + */ +uint32_t DisableGlobalIRQEx(uint32_t id) +{ + uint32_t primask = DisableGlobalIRQ(); + if (primask != 0U) + { +#ifdef FSL_FEATURE_MEASURE_CRITICAL_SECTION_DEBUG + /* Check for the critical section id. */ + assert(id != FSL_FEATURE_CRITICAL_SECTION_INVALID_ID); + assert(id < FSL_FEATURE_CRITICAL_SECTION_MAX_ID); + assert(s_critical_section_measurement_context.id == FSL_FEATURE_CRITICAL_SECTION_INVALID_ID); +#endif + if (s_critical_section_measurement_context.getTimestamp != NULL) + { + s_critical_section_measurement_context.id = id; + s_critical_section_measurement_context.startTime = s_critical_section_measurement_context.getTimestamp(); + } + } + return primask; +} + +/*! + * brief Enable the global IRQ and calculate the execution time of critical section + * + * Extended function of EnableGlobalIRQ. Apart from the standard operation, also + * marks the exit of the critical section and calculate the execution time for the section. + * User is required to use the DisableGlobalIRQEx and EnableGlobalIRQEx in pair. + * + * param primask value of primask register to be restored. The primask value is supposed to be provided by the + * DisableGlobalIRQEx(). + */ +void EnableGlobalIRQEx(uint32_t primask) +{ + if (primask != 0U) + { +#ifdef FSL_FEATURE_MEASURE_CRITICAL_SECTION_DEBUG + /* Check for the critical section id. */ + assert(s_critical_section_measurement_context.id != FSL_FEATURE_CRITICAL_SECTION_INVALID_ID); + assert(s_critical_section_measurement_context.id < FSL_FEATURE_CRITICAL_SECTION_MAX_ID); +#endif + if (s_critical_section_measurement_context.getTimestamp != NULL) + { + /* Calculate the critical section duration. */ + uint32_t dur = s_critical_section_measurement_context.getTimestamp() - s_critical_section_measurement_context.startTime; + if (dur > s_critical_section_measurement_context.dur_max[s_critical_section_measurement_context.id]) + { + s_critical_section_measurement_context.dur_max[s_critical_section_measurement_context.id] = dur; + } + s_critical_section_measurement_context.execution_times[s_critical_section_measurement_context.id]++; + } +#ifdef FSL_FEATURE_MEASURE_CRITICAL_SECTION_DEBUG + /* Exit the critical section, set the id to invalid. In this case when entering critical + section again DisableGlobalIRQEx has to be called first to avoid assertion. */ + s_critical_section_measurement_context.id = FSL_FEATURE_CRITICAL_SECTION_INVALID_ID; +#endif + } + EnableGlobalIRQ(primask); +} +#endif /* FSL_FEATURE_MEASURE_CRITICAL_SECTION */ diff --git a/bsp/nxp/imx/imx91/drivers/sdk/drivers/common/fsl_common_arm.h b/bsp/nxp/imx/imx91/drivers/sdk/drivers/common/fsl_common_arm.h new file mode 100644 index 00000000000..55544c17bab --- /dev/null +++ b/bsp/nxp/imx/imx91/drivers/sdk/drivers/common/fsl_common_arm.h @@ -0,0 +1,1184 @@ +/* + * Copyright (c) 2015-2016, Freescale Semiconductor, Inc. + * Copyright 2016-2022, 2024 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef FSL_COMMON_ARM_H_ +#define FSL_COMMON_ARM_H_ + +/* + * For CMSIS pack RTE. + * CMSIS pack RTE generates "RTC_Components.h" which contains the statements + * of the related element for all selected software components. + */ +#ifdef _RTE_ +#include "RTE_Components.h" +#endif + +/*! + * @addtogroup ksdk_common + * @{ + */ + +/*! @name Atomic modification + * + * These macros are used for atomic access, such as read-modify-write + * to the peripheral registers. + * + * Take @ref SDK_ATOMIC_LOCAL_CLEAR_AND_SET as an example: the parameter @c addr + * means the address of the peripheral register or variable you want to modify + * atomically, the parameter @c clearBits is the bits to clear, the parameter + * @c setBits it the bits to set. + * For example, to set a 32-bit register bit1:bit0 to 0b10, use like this: + * + * @code + volatile uint32_t * reg = (volatile uint32_t *)REG_ADDR; + + SDK_ATOMIC_LOCAL_CLEAR_AND_SET(reg, 0x03, 0x02); + @endcode + * + * In this example, the register bit1:bit0 are cleared and bit1 is set, as a result, + * register bit1:bit0 = 0b10. + * + * @note For the platforms don't support exclusive load and store, these macros + * disable the global interrupt to pretect the modification. + * + * @note These macros only guarantee the local processor atomic operations. For + * the multi-processor devices, use hardware semaphore such as SEMA42 to + * guarantee exclusive access if necessary. + * + * @{ + */ + +/*! + * @def SDK_ATOMIC_LOCAL_ADD(addr, val) + * Add value \a val from the variable at address \a address. + * + * @def SDK_ATOMIC_LOCAL_SUB(addr, val) + * Subtract value \a val to the variable at address \a address. + * + * @def SDK_ATOMIC_LOCAL_SET(addr, bits) + * Set the bits specifiled by \a bits to the variable at address \a address. + * + * @def SDK_ATOMIC_LOCAL_CLEAR(addr, bits) + * Clear the bits specifiled by \a bits to the variable at address \a address. + * + * @def SDK_ATOMIC_LOCAL_TOGGLE(addr, bits) + * Toggle the bits specifiled by \a bits to the variable at address \a address. + * + * @def SDK_ATOMIC_LOCAL_CLEAR_AND_SET(addr, clearBits, setBits) + * For the variable at address \a address, clear the bits specifiled by \a clearBits + * and set the bits specifiled by \a setBits. + + * @def SDK_ATOMIC_LOCAL_COMPARE_AND_SET(addr, expected, newValue) + * For the variable at address \a address, check whether the value equal to \a expected. If value same as \a expected + * then update \a newValue to address and return \b true , else return \b false . + * + * @def SDK_ATOMIC_LOCAL_TEST_AND_SET(addr, newValue) + * For the variable at address \a address, set as \a newValue value and return old value. + */ + +/* clang-format off */ +#if ((defined(__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined(__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined(__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined(__ARM_ARCH_8M_BASE__) && (__ARM_ARCH_8M_BASE__ == 1))) +/* clang-format on */ + +/* If the LDREX and STREX are supported, use them. */ +#define _SDK_ATOMIC_LOCAL_OPS_1BYTE(addr, val, ops) \ + do \ + { \ + (val) = __LDREXB(addr); \ + (ops); \ + } while (0UL != __STREXB((val), (addr))) + +#define _SDK_ATOMIC_LOCAL_OPS_2BYTE(addr, val, ops) \ + do \ + { \ + (val) = __LDREXH(addr); \ + (ops); \ + } while (0UL != __STREXH((val), (addr))) + +#define _SDK_ATOMIC_LOCAL_OPS_4BYTE(addr, val, ops) \ + do \ + { \ + (val) = __LDREXW(addr); \ + (ops); \ + } while (0UL != __STREXW((val), (addr))) + +static inline void _SDK_AtomicLocalAdd1Byte(volatile uint8_t *addr, uint8_t val) +{ + uint8_t s_val; + + _SDK_ATOMIC_LOCAL_OPS_1BYTE(addr, s_val, s_val += val); +} + +static inline void _SDK_AtomicLocalAdd2Byte(volatile uint16_t *addr, uint16_t val) +{ + uint16_t s_val; + + _SDK_ATOMIC_LOCAL_OPS_2BYTE(addr, s_val, s_val += val); +} + +static inline void _SDK_AtomicLocalAdd4Byte(volatile uint32_t *addr, uint32_t val) +{ + uint32_t s_val; + + _SDK_ATOMIC_LOCAL_OPS_4BYTE(addr, s_val, s_val += val); +} + +static inline void _SDK_AtomicLocalSub1Byte(volatile uint8_t *addr, uint8_t val) +{ + uint8_t s_val; + + _SDK_ATOMIC_LOCAL_OPS_1BYTE(addr, s_val, s_val -= val); +} + +static inline void _SDK_AtomicLocalSub2Byte(volatile uint16_t *addr, uint16_t val) +{ + uint16_t s_val; + + _SDK_ATOMIC_LOCAL_OPS_2BYTE(addr, s_val, s_val -= val); +} + +static inline void _SDK_AtomicLocalSub4Byte(volatile uint32_t *addr, uint32_t val) +{ + uint32_t s_val; + + _SDK_ATOMIC_LOCAL_OPS_4BYTE(addr, s_val, s_val -= val); +} + +static inline void _SDK_AtomicLocalSet1Byte(volatile uint8_t *addr, uint8_t bits) +{ + uint8_t s_val; + + _SDK_ATOMIC_LOCAL_OPS_1BYTE(addr, s_val, s_val |= bits); +} + +static inline void _SDK_AtomicLocalSet2Byte(volatile uint16_t *addr, uint16_t bits) +{ + uint16_t s_val; + + _SDK_ATOMIC_LOCAL_OPS_2BYTE(addr, s_val, s_val |= bits); +} + +static inline void _SDK_AtomicLocalSet4Byte(volatile uint32_t *addr, uint32_t bits) +{ + uint32_t s_val; + + _SDK_ATOMIC_LOCAL_OPS_4BYTE(addr, s_val, s_val |= bits); +} + +static inline void _SDK_AtomicLocalClear1Byte(volatile uint8_t *addr, uint8_t bits) +{ + uint8_t s_val; + + _SDK_ATOMIC_LOCAL_OPS_1BYTE(addr, s_val, s_val &= ~bits); +} + +static inline void _SDK_AtomicLocalClear2Byte(volatile uint16_t *addr, uint16_t bits) +{ + uint16_t s_val; + + _SDK_ATOMIC_LOCAL_OPS_2BYTE(addr, s_val, s_val &= ~bits); +} + +static inline void _SDK_AtomicLocalClear4Byte(volatile uint32_t *addr, uint32_t bits) +{ + uint32_t s_val; + + _SDK_ATOMIC_LOCAL_OPS_4BYTE(addr, s_val, s_val &= ~bits); +} + +static inline void _SDK_AtomicLocalToggle1Byte(volatile uint8_t *addr, uint8_t bits) +{ + uint8_t s_val; + + _SDK_ATOMIC_LOCAL_OPS_1BYTE(addr, s_val, s_val ^= bits); +} + +static inline void _SDK_AtomicLocalToggle2Byte(volatile uint16_t *addr, uint16_t bits) +{ + uint16_t s_val; + + _SDK_ATOMIC_LOCAL_OPS_2BYTE(addr, s_val, s_val ^= bits); +} + +static inline void _SDK_AtomicLocalToggle4Byte(volatile uint32_t *addr, uint32_t bits) +{ + uint32_t s_val; + + _SDK_ATOMIC_LOCAL_OPS_4BYTE(addr, s_val, s_val ^= bits); +} + +static inline void _SDK_AtomicLocalClearAndSet1Byte(volatile uint8_t *addr, uint8_t clearBits, uint8_t setBits) +{ + uint8_t s_val; + + _SDK_ATOMIC_LOCAL_OPS_1BYTE(addr, s_val, s_val = (s_val & ~clearBits) | setBits); +} + +static inline void _SDK_AtomicLocalClearAndSet2Byte(volatile uint16_t *addr, uint16_t clearBits, uint16_t setBits) +{ + uint16_t s_val; + + _SDK_ATOMIC_LOCAL_OPS_2BYTE(addr, s_val, s_val = (s_val & ~clearBits) | setBits); +} + +static inline void _SDK_AtomicLocalClearAndSet4Byte(volatile uint32_t *addr, uint32_t clearBits, uint32_t setBits) +{ + uint32_t s_val; + + _SDK_ATOMIC_LOCAL_OPS_4BYTE(addr, s_val, s_val = (s_val & ~clearBits) | setBits); +} + +#define SDK_ATOMIC_LOCAL_ADD(addr, val) \ + ((1UL == sizeof(*(addr))) ? \ + _SDK_AtomicLocalAdd1Byte((volatile uint8_t *)(volatile void *)(addr), (uint8_t)(val)) : \ + ((2UL == sizeof(*(addr))) ? _SDK_AtomicLocalAdd2Byte((volatile uint16_t *)(volatile void *)(addr), (uint16_t)(val)) : \ + _SDK_AtomicLocalAdd4Byte((volatile uint32_t *)(volatile void *)(addr), (uint32_t)(val)))) + +#define SDK_ATOMIC_LOCAL_SUB(addr, val) \ + ((1UL == sizeof(*(addr))) ? \ + _SDK_AtomicLocalSub1Byte((volatile uint8_t *)(volatile void *)(addr), (uint8_t)(val)) : \ + ((2UL == sizeof(*(addr))) ? _SDK_AtomicLocalSub2Byte((volatile uint16_t *)(volatile void *)(addr), (uint16_t)(val)) : \ + _SDK_AtomicLocalSub4Byte((volatile uint32_t *)(volatile void *)(addr), (uint32_t)(val)))) + +#define SDK_ATOMIC_LOCAL_SET(addr, bits) \ + ((1UL == sizeof(*(addr))) ? \ + _SDK_AtomicLocalSet1Byte((volatile uint8_t *)(volatile void *)(addr), (uint8_t)(bits)) : \ + ((2UL == sizeof(*(addr))) ? _SDK_AtomicLocalSet2Byte((volatile uint16_t *)(volatile void *)(addr), (uint16_t)(bits)) : \ + _SDK_AtomicLocalSet4Byte((volatile uint32_t *)(volatile void *)(addr), (uint32_t)(bits)))) + +#define SDK_ATOMIC_LOCAL_CLEAR(addr, bits) \ + ((1UL == sizeof(*(addr))) ? \ + _SDK_AtomicLocalClear1Byte((volatile uint8_t *)(volatile void *)(addr), (uint8_t)(bits)) : \ + ((2UL == sizeof(*(addr))) ? \ + _SDK_AtomicLocalClear2Byte((volatile uint16_t *)(volatile void *)(addr), (uint16_t)(bits)) : \ + _SDK_AtomicLocalClear4Byte((volatile uint32_t *)(volatile void *)(addr), (uint32_t)(bits)))) + +#define SDK_ATOMIC_LOCAL_TOGGLE(addr, bits) \ + ((1UL == sizeof(*(addr))) ? \ + _SDK_AtomicLocalToggle1Byte((volatile uint8_t *)(volatile void *)(addr), (uint8_t)(bits)) : \ + ((2UL == sizeof(*(addr))) ? \ + _SDK_AtomicLocalToggle2Byte((volatile uint16_t *)(volatile void *)(addr), (uint16_t)(bits)) : \ + _SDK_AtomicLocalToggle4Byte((volatile uint32_t *)(volatile void *)(addr), (uint32_t)(bits)))) + +#define SDK_ATOMIC_LOCAL_CLEAR_AND_SET(addr, clearBits, setBits) \ + ((1UL == sizeof(*(addr))) ? \ + _SDK_AtomicLocalClearAndSet1Byte((volatile uint8_t *)(volatile void *)(addr), (uint8_t)(clearBits), (uint8_t)(setBits)) : \ + ((2UL == sizeof(*(addr))) ? \ + _SDK_AtomicLocalClearAndSet2Byte((volatile uint16_t *)(volatile void *)(addr), (uint16_t)(clearBits), (uint16_t)(setBits)) : \ + _SDK_AtomicLocalClearAndSet4Byte((volatile uint32_t *)(volatile void *)(addr), (uint32_t)(clearBits), (uint32_t)(setBits)))) + +#define SDK_ATOMIC_LOCAL_COMPARE_AND_SET(addr, expected, newValue) \ + ((1UL == sizeof(*(addr))) ? \ + _SDK_AtomicLocalCompareAndSet1Byte((volatile uint8_t *)(volatile void *)(addr), (uint8_t)(expected), (uint8_t)(newValue)) : \ + ((2UL == sizeof(*(addr))) ? \ + _SDK_AtomicLocalCompareAndSet2Byte((volatile uint16_t *)(volatile void *)(addr), (uint16_t)(expected), (uint16_t)(newValue)) : \ + _SDK_AtomicLocalCompareAndSet4Byte((volatile uint32_t *)(volatile void *)(addr), (uint32_t)(expected), (uint32_t)(newValue)))) + +#define SDK_ATOMIC_LOCAL_TEST_AND_SET(addr, newValue) \ + ((1UL == sizeof(*(addr))) ? \ + _SDK_AtomicLocalTestAndSet1Byte((volatile uint8_t *)(volatile void *)(addr), (uint8_t)(newValue)) : \ + ((2UL == sizeof(*(addr))) ? \ + _SDK_AtomicLocalTestAndSet2Byte((volatile uint16_t *)(volatile void *)(addr), (uint16_t)(newValue)) : \ + _SDK_AtomicLocalTestAndSet4Byte((volatile uint32_t *)(volatile void *)(addr), (uint32_t)(newValue)))) +#else + +#define SDK_ATOMIC_LOCAL_ADD(addr, val) \ + do \ + { \ + uint32_t s_atomicOldInt; \ + s_atomicOldInt = DisableGlobalIRQ(); \ + *(addr) += (val); \ + EnableGlobalIRQ(s_atomicOldInt); \ + } while (false) + +#define SDK_ATOMIC_LOCAL_SUB(addr, val) \ + do \ + { \ + uint32_t s_atomicOldInt; \ + s_atomicOldInt = DisableGlobalIRQ(); \ + *(addr) -= (val); \ + EnableGlobalIRQ(s_atomicOldInt); \ + } while (false) + +#define SDK_ATOMIC_LOCAL_SET(addr, bits) \ + do \ + { \ + uint32_t s_atomicOldInt; \ + s_atomicOldInt = DisableGlobalIRQ(); \ + *(addr) |= (bits); \ + EnableGlobalIRQ(s_atomicOldInt); \ + } while (false) + +#define SDK_ATOMIC_LOCAL_CLEAR(addr, bits) \ + do \ + { \ + uint32_t s_atomicOldInt; \ + s_atomicOldInt = DisableGlobalIRQ(); \ + *(addr) &= ~(bits); \ + EnableGlobalIRQ(s_atomicOldInt); \ + } while (false) + +#define SDK_ATOMIC_LOCAL_TOGGLE(addr, bits) \ + do \ + { \ + uint32_t s_atomicOldInt; \ + s_atomicOldInt = DisableGlobalIRQ(); \ + *(addr) ^= (bits); \ + EnableGlobalIRQ(s_atomicOldInt); \ + } while (false) + +#define SDK_ATOMIC_LOCAL_CLEAR_AND_SET(addr, clearBits, setBits) \ + do \ + { \ + uint32_t s_atomicOldInt; \ + s_atomicOldInt = DisableGlobalIRQ(); \ + *(addr) = (*(addr) & ~(clearBits)) | (setBits); \ + EnableGlobalIRQ(s_atomicOldInt); \ + } while (false) + +#define SDK_ATOMIC_LOCAL_COMPARE_AND_SET(addr, expected, newValue) \ + _SDK_AtomicLocalCompareAndSet((uint32_t *)addr, (uint32_t)expected, (uint32_t)newValue) + +#define SDK_ATOMIC_LOCAL_TEST_AND_SET(addr, newValue) \ + _SDK_AtomicTestAndSet((uint32_t *)addr, (uint32_t)newValue) + +#endif +/*! @} */ + +/*! @name Timer utilities */ +/*! @{ */ +/*! Macro to convert a microsecond period to raw count value */ +#define USEC_TO_COUNT(us, clockFreqInHz) (uint64_t)(((uint64_t)(us) * (clockFreqInHz)) / 1000000U) +/*! Macro to convert a raw count value to microsecond */ +#define COUNT_TO_USEC(count, clockFreqInHz) (uint64_t)((uint64_t)(count)*1000000U / (clockFreqInHz)) + +/*! Macro to convert a millisecond period to raw count value */ +#define MSEC_TO_COUNT(ms, clockFreqInHz) (uint64_t)((uint64_t)(ms) * (clockFreqInHz) / 1000U) +/*! Macro to convert a raw count value to millisecond */ +#define COUNT_TO_MSEC(count, clockFreqInHz) (uint64_t)((uint64_t)(count)*1000U / (clockFreqInHz)) +/*! @} */ + +/*! @name ISR exit barrier + * @{ + * + * ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + * exception return operation might vector to incorrect interrupt. + * For Cortex-M7, if core speed much faster than peripheral register write speed, + * the peripheral interrupt flags may be still set after exiting ISR, this results to + * the same error similar with errata 83869. + */ +#if (defined __CORTEX_M) && ((__CORTEX_M == 4U) || (__CORTEX_M == 7U)) +#define SDK_ISR_EXIT_BARRIER __DSB() +#else +#define SDK_ISR_EXIT_BARRIER +#endif + +/*! @} */ + +/*! @name Alignment variable definition macros */ +/*! @{ */ +#if (defined(__ICCARM__)) +/* + * Workaround to disable MISRA C message suppress warnings for IAR compiler. + * http:/ /supp.iar.com/Support/?note=24725 + */ +_Pragma("diag_suppress=Pm120") +#define SDK_PRAGMA(x) _Pragma(#x) + _Pragma("diag_error=Pm120") +/*! Macro to define a variable with alignbytes alignment */ +#define SDK_ALIGN(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var +#elif defined(__CC_ARM) || defined(__ARMCC_VERSION) +/*! Macro to define a variable with alignbytes alignment */ +#define SDK_ALIGN(var, alignbytes) __attribute__((aligned(alignbytes))) var +#elif defined(__GNUC__) || defined(DOXYGEN_OUTPUT) +/*! Macro to define a variable with alignbytes alignment */ +#define SDK_ALIGN(var, alignbytes) var __attribute__((aligned(alignbytes))) +#else +#error Toolchain not supported +#endif + +/*! Macro to define a variable with L1 d-cache line size alignment */ +#if defined(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) +#define SDK_L1DCACHE_ALIGN(var) SDK_ALIGN(var, FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) +#endif +/*! Macro to define a variable with L2 cache line size alignment */ +#if defined(FSL_FEATURE_L2CACHE_LINESIZE_BYTE) +#define SDK_L2CACHE_ALIGN(var) SDK_ALIGN(var, FSL_FEATURE_L2CACHE_LINESIZE_BYTE) +#endif + +/*! Macro to change a value to a given size aligned value */ +#define SDK_SIZEALIGN(var, alignbytes) \ + ((unsigned int)((var) + ((alignbytes)-1U)) & (unsigned int)(~(unsigned int)((alignbytes)-1U))) +/*! @} */ + +/*! + * @name Non-cacheable region definition macros + * + * For initialized non-zero non-cacheable variables, please use "AT_NONCACHEABLE_SECTION_INIT(var) ={xx};" or + * "AT_NONCACHEABLE_SECTION_ALIGN_INIT(var) ={xx};" in your projects to define them. For zero-inited non-cacheable + * variables, please use "AT_NONCACHEABLE_SECTION(var);" or "AT_NONCACHEABLE_SECTION_ALIGN(var);" to define them, + * these zero-inited variables will be initialized to zero in system startup. + * + * @note For GCC, when the non-cacheable section is required, please define "__STARTUP_INITIALIZE_NONCACHEDATA" + * in your projects to make sure the non-cacheable section variables will be initialized in system startup. + * + * @{ + */ + +/*! + * @def AT_NONCACHEABLE_SECTION(var) + * Define a variable \a var, and place it in non-cacheable section. + * + * @def AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) + * Define a variable \a var, and place it in non-cacheable section, the start address + * of the variable is aligned to \a alignbytes. + * + * @def AT_NONCACHEABLE_SECTION_INIT(var) + * Define a variable \a var with initial value, and place it in non-cacheable section. + * + * @def AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) + * Define a variable \a var with initial value, and place it in non-cacheable section, + * the start address of the variable is aligned to \a alignbytes. + */ + +#if ((!(defined(FSL_FEATURE_HAS_NO_NONCACHEABLE_SECTION) && FSL_FEATURE_HAS_NO_NONCACHEABLE_SECTION)) && \ + defined(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE)) + +#if (defined(__ICCARM__)) +#define AT_NONCACHEABLE_SECTION(var) var @"NonCacheable" +#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var @"NonCacheable" +#define AT_NONCACHEABLE_SECTION_INIT(var) var @"NonCacheable.init" +#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) \ + SDK_PRAGMA(data_alignment = alignbytes) var @"NonCacheable.init" + +#elif (defined(__CC_ARM) || defined(__ARMCC_VERSION)) +#define AT_NONCACHEABLE_SECTION_INIT(var) __attribute__((section("NonCacheable.init"))) var +#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) \ + __attribute__((section("NonCacheable.init"))) __attribute__((aligned(alignbytes))) var +#if (defined(__CC_ARM)) +#define AT_NONCACHEABLE_SECTION(var) __attribute__((section("NonCacheable"), zero_init)) var +#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) \ + __attribute__((section("NonCacheable"), zero_init)) __attribute__((aligned(alignbytes))) var +#else +#define AT_NONCACHEABLE_SECTION(var) __attribute__((section(".bss.NonCacheable"))) var +#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) \ + __attribute__((section(".bss.NonCacheable"))) __attribute__((aligned(alignbytes))) var +#endif + +#elif (defined(__GNUC__)) || defined(DOXYGEN_OUTPUT) +#if defined(__ARM_ARCH_8A__) /* This macro is ARMv8-A specific */ +#define MCUX_CS "//" +#else +#define MCUX_CS "@" +#endif + +/* For GCC, when the non-cacheable section is required, please define "__STARTUP_INITIALIZE_NONCACHEDATA" + * in your projects to make sure the non-cacheable section variables will be initialized in system startup. + */ +#define AT_NONCACHEABLE_SECTION_INIT(var) __attribute__((section("NonCacheable.init"))) var +#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) \ + __attribute__((section("NonCacheable.init"))) var __attribute__((aligned(alignbytes))) +#define AT_NONCACHEABLE_SECTION(var) __attribute__((section("NonCacheable,\"aw\",%nobits " MCUX_CS))) var +#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) \ + __attribute__((section("NonCacheable,\"aw\",%nobits " MCUX_CS))) var __attribute__((aligned(alignbytes))) +#else +#error Toolchain not supported. +#endif + +#else + +#define AT_NONCACHEABLE_SECTION(var) var +#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) SDK_ALIGN(var, alignbytes) +#define AT_NONCACHEABLE_SECTION_INIT(var) var +#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) SDK_ALIGN(var, alignbytes) + +#endif + +/*! @} */ + +/*! + * @name Cache line region definition macros + * + * For initialized non-zero cache line variables, please use "AT_CACHE_LINE_SECTION_INIT(var) ={xx};" + * For zero-inited cache line variables, please use "AT_CACHE_LINE_SECTION(var);" + * + * @note This section is applicable to cached memory only, say external sdram, cached ocram, etc. + * Please avoid to use this section for none-cached memory, say TCM. + * So only those targets, which utilize the cached memory, say flexspi_nor_sdram_debug, support + * this kind of section. + * @{ + */ + +/*! + * @def AT_CACHE_LINE_SECTION(var) + * Define a variable \a var, which is cache line size aligned and be placed in CacheLineData section. + * + * @def AT_CACHE_LINE_SECTION_INIT(var) + * Define a variable \a var with initial value, which is cache line size aligned and be placed in CacheLineData.init section. + */ + +#if defined(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) +#define CACHE_LINE_DATA SDK_L1DCACHE_ALIGN +#elif defined(FSL_FEATURE_L2CACHE_LINESIZE_BYTE) +#define CACHE_LINE_DATA SDK_L2CACHE_ALIGN +#endif + +#if (defined(__ICCARM__)) +#define AT_CACHE_LINE_SECTION(var) CACHE_LINE_DATA(var) @"CacheLineData" +#define AT_CACHE_LINE_SECTION_INIT(var) CACHE_LINE_DATA(var) @"CacheLineData.init" + +#elif (defined(__CC_ARM) || defined(__ARMCC_VERSION)) +#if (defined(__CC_ARM)) +#define AT_CACHE_LINE_SECTION(var) __attribute__((section("CacheLineData"), zero_init)) CACHE_LINE_DATA(var) +#else +#define AT_CACHE_LINE_SECTION(var) __attribute__((section("CacheLineData"))) CACHE_LINE_DATA(var) +#endif +#define AT_CACHE_LINE_SECTION_INIT(var) __attribute__((section("CacheLineData.init"))) CACHE_LINE_DATA(var) + +#elif (defined(__GNUC__)) || defined(DOXYGEN_OUTPUT) +#define AT_CACHE_LINE_SECTION(var) __attribute__((section("CacheLineData,\"aw\",%nobits @"))) CACHE_LINE_DATA(var) +#define AT_CACHE_LINE_SECTION_INIT(var) __attribute__((section("CacheLineData.init"))) CACHE_LINE_DATA(var) + +#else +#error Toolchain not supported. +#endif + +/*! @} */ + +/*! + * @name Time sensitive region + * @{ + */ + +/*! + * @def AT_QUICKACCESS_SECTION_CODE(func) + * Place function in a section which can be accessed quickly by core. + * + * @def AT_QUICKACCESS_SECTION_DATA(var) + * Place data in a section which can be accessed quickly by core. + * + * @def AT_QUICKACCESS_SECTION_DATA_ALIGN(var, alignbytes) + * Place data in a section which can be accessed quickly by core, and the variable + * address is set to align with \a alignbytes. + */ +#if (defined(__ICCARM__)) +#define AT_QUICKACCESS_SECTION_CODE(func) func @"CodeQuickAccess" +#define AT_QUICKACCESS_SECTION_DATA(var) var @"DataQuickAccess" +#define AT_QUICKACCESS_SECTION_DATA_ALIGN(var, alignbytes) \ + SDK_PRAGMA(data_alignment = alignbytes) var @"DataQuickAccess" +#elif (defined(__CC_ARM) || defined(__ARMCC_VERSION)) +#define AT_QUICKACCESS_SECTION_CODE(func) __attribute__((section("CodeQuickAccess"), __noinline__)) func +#define AT_QUICKACCESS_SECTION_DATA(var) __attribute__((section("DataQuickAccess"))) var +#define AT_QUICKACCESS_SECTION_DATA_ALIGN(var, alignbytes) \ + __attribute__((section("DataQuickAccess"))) __attribute__((aligned(alignbytes))) var +#elif (defined(__GNUC__)) || defined(DOXYGEN_OUTPUT) +#define AT_QUICKACCESS_SECTION_CODE(func) __attribute__((section("CodeQuickAccess"), __noinline__)) func +#define AT_QUICKACCESS_SECTION_DATA(var) __attribute__((section("DataQuickAccess"))) var +#define AT_QUICKACCESS_SECTION_DATA_ALIGN(var, alignbytes) \ + __attribute__((section("DataQuickAccess"))) var __attribute__((aligned(alignbytes))) +#else +#error Toolchain not supported. +#endif /* defined(__ICCARM__) */ +/*! @} */ + +/*! + * @name Ram Function + * @{ + * + * @def RAMFUNCTION_SECTION_CODE(func) + * Place function in ram. + */ +#if (defined(__ICCARM__)) +#define RAMFUNCTION_SECTION_CODE(func) func @"RamFunction" +#elif (defined(__CC_ARM) || defined(__ARMCC_VERSION)) +#define RAMFUNCTION_SECTION_CODE(func) __attribute__((section("RamFunction"))) func +#elif (defined(__GNUC__)) || defined(DOXYGEN_OUTPUT) +#define RAMFUNCTION_SECTION_CODE(func) __attribute__((section("RamFunction"))) func +#else +#error Toolchain not supported. +#endif /* defined(__ICCARM__) */ +/*! @} */ + +/*! + * @def MSDK_REG_SECURE_ADDR(x) + * Convert the register address to the one used in secure mode. + * + * @def MSDK_REG_NONSECURE_ADDR(x) + * Convert the register address to the one used in non-secure mode. + */ + +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) +#define MSDK_REG_SECURE_ADDR(x) ((uintptr_t)(x) | (0x1UL << 28)) +#define MSDK_REG_NONSECURE_ADDR(x) ((uintptr_t)(x) & ~(0x1UL << 28)) +#else +#define MSDK_REG_SECURE_ADDR(x) (x) +#define MSDK_REG_NONSECURE_ADDR(x) (x) +#endif + +/*! + * @brief Invalid IRQ handler address. + */ +#define MSDK_INVALID_IRQ_HANDLER UINT32_MAX + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + void DefaultISR(void); +#endif + +/* + * The fsl_clock.h is included here because it needs MAKE_VERSION/MAKE_STATUS/status_t + * defined in previous of this file. + */ +#include "fsl_clock.h" + +/* + * Chip level peripheral reset API, for MCUs that implement peripheral reset control external to a peripheral + */ +#if ((defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0)) || \ + (defined(FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT) && (FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT > 0))) +#include "fsl_reset.h" +#endif + +#if defined(FSL_FEATURE_IRQSTEER_EXT_INT_MAX_NUM) && (FSL_FEATURE_IRQSTEER_EXT_INT_MAX_NUM > 0) && defined(FSL_FEATURE_IRQSTEER_IRQ_START_INDEX) && (FSL_FEATURE_IRQSTEER_IRQ_START_INDEX > 0) +void IRQSTEER_EnableInterrupt(int32_t instIdx, IRQn_Type irq); +void IRQSTEER_DisableInterrupt(int32_t instIdx, IRQn_Type irq); +#endif + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @brief Enable specific interrupt. + * + * Enable LEVEL1 interrupt. For some devices, there might be multiple interrupt + * levels. For example, there are NVIC and intmux. Here the interrupts connected + * to NVIC are the LEVEL1 interrupts, because they are routed to the core directly. + * The interrupts connected to intmux are the LEVEL2 interrupts, they are routed + * to NVIC first then routed to core. + * + * This function only enables the LEVEL1 interrupts. The number of LEVEL1 interrupts + * is indicated by the feature macro FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS. + * + * @param interrupt The IRQ number. + * @retval kStatus_Success Interrupt enabled successfully + * @retval kStatus_Fail Failed to enable the interrupt + */ +static inline status_t EnableIRQ(IRQn_Type interrupt) +{ + status_t status = kStatus_Success; + + if (NotAvail_IRQn == interrupt) + { + status = kStatus_Fail; + } + +#if defined(FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS) && (FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS > 0) + else if ((int32_t)interrupt >= (int32_t)FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS) + { +#if defined(FSL_FEATURE_IRQSTEER_EXT_INT_MAX_NUM) && (FSL_FEATURE_IRQSTEER_EXT_INT_MAX_NUM > 0) && defined(FSL_FEATURE_IRQSTEER_IRQ_START_INDEX) && (FSL_FEATURE_IRQSTEER_IRQ_START_INDEX > 0) + int32_t irqsteerInstIdx = (int32_t)((interrupt + 1 - FSL_FEATURE_IRQSTEER_IRQ_START_INDEX) / FSL_FEATURE_IRQSTEER_EXT_INT_MAX_NUM); + + IRQSTEER_EnableInterrupt(irqsteerInstIdx, interrupt); +#else + status = kStatus_Fail; +#endif + } +#endif + + else + { +#if defined(__GIC_PRIO_BITS) + GIC_EnableIRQ(interrupt); +#else + NVIC_EnableIRQ(interrupt); +#endif + } + + return status; +} + +/*! + * @brief Disable specific interrupt. + * + * Disable LEVEL1 interrupt. For some devices, there might be multiple interrupt + * levels. For example, there are NVIC and intmux. Here the interrupts connected + * to NVIC are the LEVEL1 interrupts, because they are routed to the core directly. + * The interrupts connected to intmux are the LEVEL2 interrupts, they are routed + * to NVIC first then routed to core. + * + * This function only disables the LEVEL1 interrupts. The number of LEVEL1 interrupts + * is indicated by the feature macro FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS. + * + * @param interrupt The IRQ number. + * @retval kStatus_Success Interrupt disabled successfully + * @retval kStatus_Fail Failed to disable the interrupt + */ +static inline status_t DisableIRQ(IRQn_Type interrupt) +{ + status_t status = kStatus_Success; + + if (NotAvail_IRQn == interrupt) + { + status = kStatus_Fail; + } + +#if defined(FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS) && (FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS > 0) + else if ((int32_t)interrupt >= (int32_t)FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS) + { +#if defined(FSL_FEATURE_IRQSTEER_EXT_INT_MAX_NUM) && (FSL_FEATURE_IRQSTEER_EXT_INT_MAX_NUM > 0) && defined(FSL_FEATURE_IRQSTEER_IRQ_START_INDEX) && (FSL_FEATURE_IRQSTEER_IRQ_START_INDEX > 0) + int32_t irqsteerInstIdx = (int32_t)((interrupt - FSL_FEATURE_IRQSTEER_IRQ_START_INDEX) / FSL_FEATURE_IRQSTEER_EXT_INT_MAX_NUM); + + IRQSTEER_DisableInterrupt(irqsteerInstIdx, interrupt); +#else + status = kStatus_Fail; +#endif + } +#endif + + else + { +#if defined(__GIC_PRIO_BITS) + GIC_DisableIRQ(interrupt); +#else + NVIC_DisableIRQ(interrupt); +#endif + } + + return status; +} + +/*! + * @brief Enable the IRQ, and also set the interrupt priority. + * + * Only handle LEVEL1 interrupt. For some devices, there might be multiple interrupt + * levels. For example, there are NVIC and intmux. Here the interrupts connected + * to NVIC are the LEVEL1 interrupts, because they are routed to the core directly. + * The interrupts connected to intmux are the LEVEL2 interrupts, they are routed + * to NVIC first then routed to core. + * + * This function only handles the LEVEL1 interrupts. The number of LEVEL1 interrupts + * is indicated by the feature macro FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS. + * + * @param interrupt The IRQ to Enable. + * @param priNum Priority number set to interrupt controller register. + * @retval kStatus_Success Interrupt priority set successfully + * @retval kStatus_Fail Failed to set the interrupt priority. + */ +static inline status_t EnableIRQWithPriority(IRQn_Type interrupt, uint8_t priNum) +{ + status_t status = kStatus_Success; + + if (NotAvail_IRQn == interrupt) + { + status = kStatus_Fail; + } + +#if defined(FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS) && (FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS > 0) + else if ((int32_t)interrupt >= (int32_t)FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS) + { + status = kStatus_Fail; + } +#endif + + else + { +#if defined(__GIC_PRIO_BITS) + GIC_SetPriority(interrupt, priNum); + GIC_EnableIRQ(interrupt); +#else + NVIC_SetPriority(interrupt, priNum); + NVIC_EnableIRQ(interrupt); +#endif + } + + return status; +} + +/*! + * @brief Set the IRQ priority. + * + * Only handle LEVEL1 interrupt. For some devices, there might be multiple interrupt + * levels. For example, there are NVIC and intmux. Here the interrupts connected + * to NVIC are the LEVEL1 interrupts, because they are routed to the core directly. + * The interrupts connected to intmux are the LEVEL2 interrupts, they are routed + * to NVIC first then routed to core. + * + * This function only handles the LEVEL1 interrupts. The number of LEVEL1 interrupts + * is indicated by the feature macro FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS. + * + * @param interrupt The IRQ to set. + * @param priNum Priority number set to interrupt controller register. + * + * @retval kStatus_Success Interrupt priority set successfully + * @retval kStatus_Fail Failed to set the interrupt priority. + */ +static inline status_t IRQ_SetPriority(IRQn_Type interrupt, uint8_t priNum) +{ + status_t status = kStatus_Success; + + if (NotAvail_IRQn == interrupt) + { + status = kStatus_Fail; + } + +#if defined(FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS) && (FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS > 0) + else if ((int32_t)interrupt >= (int32_t)FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS) + { + status = kStatus_Fail; + } +#endif + + else + { +#if defined(__GIC_PRIO_BITS) + GIC_SetPriority(interrupt, priNum); +#else + NVIC_SetPriority(interrupt, priNum); +#endif + } + + return status; +} + +/*! + * @brief Clear the pending IRQ flag. + * + * Only handle LEVEL1 interrupt. For some devices, there might be multiple interrupt + * levels. For example, there are NVIC and intmux. Here the interrupts connected + * to NVIC are the LEVEL1 interrupts, because they are routed to the core directly. + * The interrupts connected to intmux are the LEVEL2 interrupts, they are routed + * to NVIC first then routed to core. + * + * This function only handles the LEVEL1 interrupts. The number of LEVEL1 interrupts + * is indicated by the feature macro FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS. + * + * @param interrupt The flag which IRQ to clear. + * + * @retval kStatus_Success Interrupt priority set successfully + * @retval kStatus_Fail Failed to set the interrupt priority. + */ +static inline status_t IRQ_ClearPendingIRQ(IRQn_Type interrupt) +{ + status_t status = kStatus_Success; + + if (NotAvail_IRQn == interrupt) + { + status = kStatus_Fail; + } + +#if defined(FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS) && (FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS > 0) + else if ((int32_t)interrupt >= (int32_t)FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS) + { + status = kStatus_Fail; + } +#endif + + else + { +#if defined(__GIC_PRIO_BITS) + GIC_ClearPendingIRQ(interrupt); +#else + NVIC_ClearPendingIRQ(interrupt); +#endif + } + + return status; +} + +/*! + * @brief Disable the global IRQ + * + * Disable the global interrupt and return the current primask register. User is required to provided the primask + * register for the EnableGlobalIRQ(). + * + * @return Current primask value. + */ +static inline uint32_t DisableGlobalIRQ(void) +{ + uint32_t mask; + +#if defined(CPSR_I_Msk) + mask = __get_CPSR() & CPSR_I_Msk; +#elif defined(DAIF_I_BIT) + mask = __get_DAIF() & DAIF_I_BIT; +#else + mask = __get_PRIMASK(); +#endif + __disable_irq(); + + return mask; +} + +/*! + * @brief Enable the global IRQ + * + * Set the primask register with the provided primask value but not just enable the primask. The idea is for the + * convenience of integration of RTOS. some RTOS get its own management mechanism of primask. User is required to + * use the EnableGlobalIRQ() and DisableGlobalIRQ() in pair. + * + * @param primask value of primask register to be restored. The primask value is supposed to be provided by the + * DisableGlobalIRQ(). + */ +static inline void EnableGlobalIRQ(uint32_t primask) +{ +#if defined(CPSR_I_Msk) + __set_CPSR((__get_CPSR() & ~CPSR_I_Msk) | primask); +#elif defined(DAIF_I_BIT) + if (0UL == primask) + { + __enable_irq(); + } +#else + __set_PRIMASK(primask); +#endif +} + +#if defined(ENABLE_RAM_VECTOR_TABLE) +/*! + * @brief install IRQ handler + * + * @param irq IRQ number + * @param irqHandler IRQ handler address + * @return The old IRQ handler address, if the input @p irq is invalid, then + * return value is @ref MSDK_INVALID_IRQ_HANDLER. + */ +uint32_t InstallIRQHandler(IRQn_Type irq, uint32_t irqHandler); +#endif /* ENABLE_RAM_VECTOR_TABLE. */ + +#if (defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0)) + +/* + * When FSL_FEATURE_POWERLIB_EXTEND is defined to non-zero value, + * powerlib should be used instead of these functions. + */ +#if !(defined(FSL_FEATURE_POWERLIB_EXTEND) && (FSL_FEATURE_POWERLIB_EXTEND != 0)) +/*! + * @brief Enable specific interrupt for wake-up from deep-sleep mode. + * + * Enable the interrupt for wake-up from deep sleep mode. + * Some interrupts are typically used in sleep mode only and will not occur during + * deep-sleep mode because relevant clocks are stopped. However, it is possible to enable + * those clocks (significantly increasing power consumption in the reduced power mode), + * making these wake-ups possible. + * + * @note This function also enables the interrupt in the NVIC (EnableIRQ() is called internaly). + * + * @param interrupt The IRQ number. + */ +void EnableDeepSleepIRQ(IRQn_Type interrupt); + +/*! + * @brief Disable specific interrupt for wake-up from deep-sleep mode. + * + * Disable the interrupt for wake-up from deep sleep mode. + * Some interrupts are typically used in sleep mode only and will not occur during + * deep-sleep mode because relevant clocks are stopped. However, it is possible to enable + * those clocks (significantly increasing power consumption in the reduced power mode), + * making these wake-ups possible. + * + * @note This function also disables the interrupt in the NVIC (DisableIRQ() is called internaly). + * + * @param interrupt The IRQ number. + */ +void DisableDeepSleepIRQ(IRQn_Type interrupt); +#endif /* FSL_FEATURE_POWERLIB_EXTEND */ +#endif /* FSL_FEATURE_SOC_SYSCON_COUNT */ + +#if defined(DWT) +/*! + * @brief Enable the counter to get CPU cycles. + */ +void MSDK_EnableCpuCycleCounter(void); + +/*! + * @brief Get the current CPU cycle count. + * + * @return Current CPU cycle count. + */ +uint32_t MSDK_GetCpuCycleCount(void); +#endif + +#if defined(FSL_FEATURE_MEASURE_CRITICAL_SECTION) && (FSL_FEATURE_MEASURE_CRITICAL_SECTION != 0) +typedef uint32_t (*getTimestamp_t)(void); /*!< Function to get the current time stamp. */ + +/*! + * @rief Initialize the context of the critical section measurement and assign + * the function to get the current timestamp. + * + * @param getTimestamp The function to get the current timestamp. + */ +void InitCriticalSectionMeasurementContext(getTimestamp_t func); + +/*! + * @brief Disable the global IRQ with critical section ID + * + * Extended function of DisableGlobalIRQ. Apart from the standard operation, also check + * the id of the protected critical section and mark the begining for timer. + * User is required to provided the primask register for the EnableGlobalIRQEx. + * + * @param id The id for critical section. + * @return Current primask value. + */ +uint32_t DisableGlobalIRQEx(uint32_t id); + +/*! + * @brief Enable the global IRQ and calculate the execution time of critical section + * + * Extended function of EnableGlobalIRQ. Apart from the standard operation, also + * marks the exit of the critical section and calculate the execution time for the section. + * User is required to use the DisableGlobalIRQEx and EnableGlobalIRQEx in pair. + * + * @param primask value of primask register to be restored. The primask value is supposed to be provided by the + * DisableGlobalIRQEx(). + */ +void EnableGlobalIRQEx(uint32_t primask); +#endif + + +/* clang-format off */ +#if ((defined(__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined(__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined(__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined(__ARM_ARCH_8M_BASE__) && (__ARM_ARCH_8M_BASE__ == 1))) +/* clang-format on */ +static inline bool _SDK_AtomicLocalCompareAndSet1Byte(volatile uint8_t *addr, uint8_t expected, uint8_t newValue) +{ + uint8_t s_actual; + + do + { + s_actual = __LDREXB(addr); + if (s_actual != expected) + { + __CLREX(); + return false; + } + } while (__STREXB((newValue), (addr))); + + return true; +} + +static inline bool _SDK_AtomicLocalCompareAndSet2Byte(volatile uint16_t *addr, uint16_t expected, uint16_t newValue) +{ + uint16_t s_actual; + + do + { + s_actual = __LDREXH(addr); + if (s_actual != expected) + { + __CLREX(); + return false; + } + } while (__STREXH((newValue), (addr))); + + return true; +} + +static inline bool _SDK_AtomicLocalCompareAndSet4Byte(volatile uint32_t *addr, uint32_t expected, uint32_t newValue) +{ + uint32_t s_actual; + + do + { + s_actual = __LDREXW(addr); + if (s_actual != expected) + { + __CLREX(); + return false; + } + } while (__STREXW((newValue), (addr))); + + return true; +} + +static inline uint8_t _SDK_AtomicLocalTestAndSet1Byte(volatile uint8_t *addr, uint8_t newValue) +{ + uint8_t s_old; + + do + { + s_old = __LDREXB(addr); + } while (__STREXB((newValue), (addr))); + + return s_old; +} + +static inline uint16_t _SDK_AtomicLocalTestAndSet2Byte(volatile uint16_t *addr, uint16_t newValue) +{ + uint16_t s_old; + + do + { + s_old = __LDREXH(addr); + } while (__STREXH((newValue), (addr))); + + return s_old; +} + +static inline uint32_t _SDK_AtomicLocalTestAndSet4Byte(volatile uint32_t *addr, uint32_t newValue) +{ + uint32_t s_old; + + do + { + s_old = __LDREXW(addr); + } while (__STREXW((newValue), (addr))); + + return s_old; +} + +#else +static inline bool _SDK_AtomicLocalCompareAndSet(uint32_t *addr, uint32_t expected, uint32_t newValue) +{ + uint32_t s_atomicOldInt; + uint32_t s_actual; + + s_atomicOldInt = DisableGlobalIRQ(); + + s_actual = *addr; + if (s_actual == expected) + { + *addr = newValue; + EnableGlobalIRQ(s_atomicOldInt); + return true; + } + else + { + EnableGlobalIRQ(s_atomicOldInt); + return false; + } +} + +static inline uint32_t _SDK_AtomicTestAndSet(uint32_t *addr, uint32_t newValue) +{ + uint32_t s_atomicOldInt = DisableGlobalIRQ(); + + uint32_t oldValue = (uint32_t)(*addr); + *addr = newValue; + + EnableGlobalIRQ(s_atomicOldInt); + return oldValue; +} + +#endif + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +/*! @} */ + +#endif /* FSL_COMMON_ARM_H_ */ diff --git a/bsp/nxp/imx/imx91/drivers/sdk/drivers/common/fsl_common_dsc.c b/bsp/nxp/imx/imx91/drivers/sdk/drivers/common/fsl_common_dsc.c new file mode 100644 index 00000000000..19919494737 --- /dev/null +++ b/bsp/nxp/imx/imx91/drivers/sdk/drivers/common/fsl_common_dsc.c @@ -0,0 +1,476 @@ +/* + * Copyright (c) 2015-2016, Freescale Semiconductor, Inc. + * Copyright 2016-2025 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_common.h" + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.common_dsc" +#endif + +#define COMMON_INTC_TYPE_REG_INDEX(x) (((uint8_t)(x)) >> 3U) +#define COMMON_INTC_TYPE_BIT_INDEX(x) ((((uint8_t)(x)) & 0x7U) << 1U) + +/******************************************************************************* + * Variables + ******************************************************************************/ +/*! @brief Interrupt priority table. */ +static uint16_t s_intPrioTable[(NUMBER_OF_INT_IRQ - 1U) / 8U + 1U] = {0U}; + +/******************************************************************************* + * Code + ******************************************************************************/ + +status_t EnableIRQWithPriority(IRQn_Type irq, uint8_t priNum) +{ + uint8_t regIndex; + uint8_t bitIndex; + uint16_t prioMask; + uint16_t reg; + uint16_t intcCtrl; + + regIndex = COMMON_INTC_TYPE_REG_INDEX(irq); + bitIndex = COMMON_INTC_TYPE_BIT_INDEX(irq); + prioMask = ((uint16_t)3U << bitIndex); + /* Valid priority number is 0-3 */ + priNum = priNum & 0x03U; + + if (0U == priNum) + { + priNum = SDK_DSC_DEFAULT_INT_PRIO; + } + + /* Disable global interrupt for atomic change. */ + intcCtrl = INTC->CTRL; + INTC->CTRL = intcCtrl | INTC_CTRL_INT_DIS_MASK; + + /* Save the priority in s_intPrioTable */ + reg = s_intPrioTable[regIndex]; + reg = (reg & ~prioMask) | (priNum << bitIndex); + + s_intPrioTable[regIndex] = reg; + + /* Set new priority in interrupt controller register. */ + reg = ((volatile uint16_t *)&(INTC->IPR0))[regIndex]; + reg = (reg & ~prioMask) | (priNum << bitIndex); + + ((volatile uint16_t *)&(INTC->IPR0))[regIndex] = reg; + + INTC->CTRL = intcCtrl; + + return kStatus_Success; +} + +status_t DisableIRQ(IRQn_Type irq) +{ + uint8_t regIndex; + uint8_t bitIndex; + uint16_t reg; + uint16_t intcCtrl; + + regIndex = COMMON_INTC_TYPE_REG_INDEX(irq); + bitIndex = COMMON_INTC_TYPE_BIT_INDEX(irq); + + /* Disable global interrupt for atomic change. */ + intcCtrl = INTC->CTRL; + INTC->CTRL = intcCtrl | INTC_CTRL_INT_DIS_MASK; + + reg = ((volatile uint16_t *)&(INTC->IPR0))[regIndex]; + reg = reg & (~((uint16_t)3U << bitIndex)); + + ((volatile uint16_t *)&(INTC->IPR0))[regIndex] = reg; + + INTC->CTRL = intcCtrl; + + return kStatus_Success; +} + +status_t EnableIRQ(IRQn_Type irq) +{ + uint8_t regIndex; + uint8_t bitIndex; + uint16_t prioMask; + uint16_t reg; + uint16_t intcCtrl; + + regIndex = COMMON_INTC_TYPE_REG_INDEX(irq); + bitIndex = COMMON_INTC_TYPE_BIT_INDEX(irq); + prioMask = ((uint16_t)3U << bitIndex); + + /* Disable global interrupt for atomic change. */ + intcCtrl = INTC->CTRL; + INTC->CTRL = intcCtrl | INTC_CTRL_INT_DIS_MASK; + + /* If priority in s_intPrioTable is 0, use SDK_DSC_DEFAULT_INT_PRIO. */ + if (0U == (s_intPrioTable[regIndex] & prioMask)) + { + s_intPrioTable[regIndex] = (s_intPrioTable[regIndex] & ~prioMask) | (SDK_DSC_DEFAULT_INT_PRIO << bitIndex); + } + + /* Set the interrupt priority with the priority in s_intPrioTable. */ + reg = ((volatile uint16_t *)&(INTC->IPR0))[regIndex]; + reg = (reg & ~prioMask) | (s_intPrioTable[regIndex] & prioMask); + + ((volatile uint16_t *)&(INTC->IPR0))[regIndex] = reg; + + INTC->CTRL = intcCtrl; + + return kStatus_Success; +} + +/* + * brief Set the IRQ priority. + * + * note The parameter priNum is range in 1~3, and its value is **NOT** + * directly map to interrupt priority. + * + * - Some IPs maps 1 to priority 1, 2 to priority 2, 3 to priority 3 + * - Some IPs maps 1 to priority 0, 2 to priority 1, 3 to priority 2 + * + * User should check chip's RM to get its corresponding interrupt priority + */ +status_t IRQ_SetPriority(IRQn_Type irq, uint8_t priNum) +{ + /* + * If the interrupt is already enabled, the new priority will be set + * to the register. If interrupt is not enabled, the new priority is + * only saved in priority table s_intPrioTable, when interrupt enabled, + * the priority value is set to register. + */ + uint8_t regIndex; + uint8_t bitIndex; + uint16_t prioMask; + uint16_t reg; + uint16_t intcCtrl; + + regIndex = COMMON_INTC_TYPE_REG_INDEX(irq); + bitIndex = COMMON_INTC_TYPE_BIT_INDEX(irq); + prioMask = ((uint16_t)3U << bitIndex); + + /* Valid priority number is 0-3 */ + priNum = priNum & 0x03U; + + if (0U == priNum) + { + priNum = SDK_DSC_DEFAULT_INT_PRIO; + } + + /* Disable global interrupt for atomic change. */ + intcCtrl = INTC->CTRL; + INTC->CTRL = intcCtrl | INTC_CTRL_INT_DIS_MASK; + + /* Save the priority in s_intPrioTable */ + reg = s_intPrioTable[regIndex]; + reg = (reg & ~prioMask) | (priNum << bitIndex); + + s_intPrioTable[regIndex] = reg; + + /* + * If interrupt already enabled, set new priority + * in interrupt controller register. + */ + reg = ((volatile uint16_t *)&(INTC->IPR0))[regIndex]; + + if (0U != (reg & prioMask)) + { + reg = (reg & (~prioMask)) | (priNum << bitIndex); + + ((volatile uint16_t *)&(INTC->IPR0))[regIndex] = reg; + } + + INTC->CTRL = intcCtrl; + + return kStatus_Success; +} + +/*! + * brief Delay core cycles. + * Please note that, this API uses software loop for delay, the actual delayed + * time depends on core clock frequency, where the function is located (ram or flash), + * flash clock, possible interrupt. + * + * param u32Num Number of core clock cycle which needs to be delayed. + */ +void SDK_DelayCoreCycles(uint32_t u32Num) +{ + /* + * if(u32Num < 22) + * { + * ActualDelayCycle = 21; + * } + * else + * { + * ActualDelayCycle = 35 + ((u32Num-22)/8) * 8 = 13 + u32Num - ((u32Num-22)%8) + * } + */ + + /* JSR - 4 cycles + * RTS - 8 cycles + */ + + asm { + cmp.l #21,A // 2 cycle + bls ret // 5 cycles when jump occurs. 3 cycles when jump doesn't occur + nop // 1 cycle + nop // 1 cycle + sub.l #22, A // 2 cycle + asrr.l #3, A // 2 cycle + bra test // 5 cycle + + loop: + dec.l A // 1 cycle + + test: + tst.l A // 1 cycle + nop // 1 cycle + bne loop // 5 cycles when jump occurs. 3 cycles when jump doesn't occur + + ret: + nop // 1 cycle + nop // 1 cycle + } +} + +/*! + * brief Delay at least for some time. + * Please note that, this API uses while loop for delay, different run-time environments make the time not precise, + * if precise delay count was needed, please implement a new delay function with hardware timer. + * + * param delayTime_us Delay time in unit of microsecond. + * param coreClock_Hz Core clock frequency with Hz. + */ +void SDK_DelayAtLeastUs(uint32_t delayTime_us, uint32_t coreClock_Hz) +{ + while(delayTime_us > 0) + { + uint32_t us, count; + + /* USEC_TO_COUNT(fixed-point) supports maximum 4294us, use 4000UL here */ + if(delayTime_us > 4000UL) + { + us = 4000UL; + } + else + { + us = delayTime_us; + } + delayTime_us -= us; + + count = USEC_TO_COUNT(us, coreClock_Hz); + SDK_DelayCoreCycles(count); + } +} + +/*! + * brief Covert us to count with fixed-point calculation. + * + * note u32Us must not be greater than 4294 + * + * param u32Us Time in us + * param u32Hz Clock frequency in Hz + * return The count value + */ +uint32_t SDK_CovertUsToCount(uint32_t u32Us, uint32_t u32Hz) +{ + /* + * Hz * us / 1000000UL = (Hz / 1000000UL) * us + * = (i + r/1000000UL) * us + * = i * us + r * us / 1000000UL + */ + + assert(u32Us <= 4294UL); + assert(u32Hz != 0U); + + uint32_t i, r; + + i = u32Hz / 1000000UL; + r = u32Hz - i * 1000000UL; + + return i * u32Us + (r * u32Us / 1000000UL); +} + +/*! + * brief Covert count to us with fixed-point calculation. + * + * note u32Hz must not be greater than 429496729UL(0xFFFFFFFFUL/10UL) + * + * param u32Count Count value + * param u32Hz Clock frequency in Hz + * return The us value + */ +uint32_t SDK_CovertCountToUs(uint32_t u32Count, uint32_t u32Hz) +{ + /* + * count * 1000000UL / hz + * + * i1 = count / hz + * r1 = count - i1 * hz + * sum = i1 * 1000000UL + * + * count = r1 * 10UL + * i2 = count / hz + * r2 = count - i2 * hz + * sum += i2 * 100000UL + * + * count = r2 * 10UL + * i3 = count / hz + * r3 = count - i3 * hz + * sum += i3 * 10000UL; + * + * count = r3 * 10UL + * i4 = count / hz + * r4 = count - i4 * hz + * sum += i4 * 1000UL; + * + * count = r4 * 10UL + * i5 = count / hz + * r5 = count - i5 * hz + * sum += i5 * 100UL; + * + * count = r5 * 10UL + * i6 = count / hz + * r6 = count - i6 * hz + * sum += i6 * 10UL; + * + * count = r6 * 10UL + * i7 = count / hz + * r7 = count - i7 * hz + * sum += i7 * 1UL; + * + */ + assert(u32Hz != 0U); + assert(u32Hz <= 429496729UL); + + uint32_t j; + + uint32_t i, r, sum = 0UL, c = 1UL; + + for (j = 0U; j < 7U; j++) + { + i = u32Count / u32Hz; + r = u32Count - i * u32Hz; + sum += i * 1000000UL / c; + + c *= 10UL; + u32Count = r * 10UL; + } + + return sum; +} + +/*! + * brief Covert ms to count with fixed-point calculation. + * + * note u32Ms must not be greater than 42949UL @ u32Hz = 100M + * + * param u32Ms Time in us + * param u32Hz Clock frequency in Hz + * return The count value + */ +uint32_t SDK_CovertMsToCount(uint32_t u32Ms, uint32_t u32Hz) +{ + /* + * Hz * ms / 1000UL = (Hz / 1000UL) * ms + * = (i + r/1000UL) * ms + * = i * ms + r * ms / 1000UL + */ + + assert(u32Ms <= 42949UL); + assert(u32Hz != 0U); + + uint32_t i, r; + + i = u32Hz / 1000UL; + r = u32Hz - i * 1000UL; + + return i * u32Ms + (r * u32Ms / 1000UL); +} + +/*! + * brief Covert count to ms with fixed-point calculation. + * + * note u32Hz must not be greater than 429496729UL(0xFFFFFFFFUL/10UL) + * + * param u32Count Count value + * param u32Hz Clock frequency in Hz + * return The us value + */ +uint32_t SDK_CovertCountToMs(uint32_t u32Count, uint32_t u32Hz) +{ + /* + * count * 1000UL / hz + * + * i1 = count / hz + * r1 = count - i1 * hz * + * sum = i1 * 1000UL + * + * count = r1 * 10UL + * i2 = count / hz + * r2 = count - i2 * hz + * sum += i2 * 100UL + * + * count = r2 * 10UL + * i3 = count / hz + * r3 = count - i3 * hz + * sum += i3 * 10L; + * + * count = r3 * 10UL + * i4 = count / hz + * r4 = count - i4 * hz + * sum += i4 * 1UL; + * + */ + assert(u32Hz != 0U); + assert(u32Hz <= 429496729UL); + + uint32_t j; + + uint32_t i, r, sum = 0UL, c = 1UL; + + for (j = 0U; j < 4U; j++) + { + i = u32Count / u32Hz; + r = u32Count - i * u32Hz; + sum += i * 1000UL / c; + + c *= 10UL; + u32Count = r * 10UL; + } + + return sum; +} + +/*! + * brief Delay at least for some time in millisecond unit. + * Please note that, this API uses while loop for delay, different run-time environments make the time not precise, + * if precise delay count was needed, please implement a new delay function with hardware timer. + * + * param delayTime_ms Delay time in unit of millisecond. + * param coreClock_Hz Core clock frequency with Hz. + */ +void SDK_DelayAtLeastMs(uint32_t delayTime_ms, uint32_t coreClock_Hz) +{ + while(delayTime_ms > 0) + { + uint32_t ms, count; + + /* MSEC_TO_COUNT(fixed-point) supports maximum 42949ms @ 100MHz, use 1000UL here */ + if(delayTime_ms > 1000UL) + { + ms = 1000UL; + } + else + { + ms = delayTime_ms; + } + delayTime_ms -= ms; + + count = MSEC_TO_COUNT(ms, coreClock_Hz); + SDK_DelayCoreCycles(count); + } +} diff --git a/bsp/nxp/imx/imx91/drivers/sdk/drivers/common/fsl_common_dsc.h b/bsp/nxp/imx/imx91/drivers/sdk/drivers/common/fsl_common_dsc.h new file mode 100644 index 00000000000..3659d4b23a9 --- /dev/null +++ b/bsp/nxp/imx/imx91/drivers/sdk/drivers/common/fsl_common_dsc.h @@ -0,0 +1,496 @@ +/* + * Copyright (c) 2015-2016, Freescale Semiconductor, Inc. + * Copyright 2016-2025 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef FSL_COMMON_DSC_H_ +#define FSL_COMMON_DSC_H_ + +#include "fsl_device_registers.h" +#include "Cpu.h" + +/*! + * @addtogroup ksdk_common + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +#ifndef bool +typedef uint8_t bool; +#define true 1 +#define false 0 +#endif + +/*! @name Timer utilities */ +/*! @{ */ +#if FSL_FEATURE_SOC_HAS_FPU +/*! Macro to convert a microsecond period to raw count value */ +#define USEC_TO_COUNT(us, clockFreqInHz) ((float)clockFreqInHz * ((float))us / 1000000UL) +/*! Macro to convert a raw count value to microsecond */ +#define COUNT_TO_USEC(count, clockFreqInHz) ((float)count * 1000000UL / (float)clockFreqInHz) +/*! Macro to convert a millisecond period to raw count value */ +#define MSEC_TO_COUNT(ms, clockFreqInHz) ((float)clockFreqInHz * ((float))ms / 1000UL) +/*! Macro to convert a raw count value to millisecond */ +#define COUNT_TO_MSEC(count, clockFreqInHz) ((float)count * 1000UL / (float)clockFreqInHz) + +#else +/*! Macro to convert a microsecond period to raw count value */ +/* To avoid overflow, us is maximum to 4294us */ +#define USEC_TO_COUNT(us, clockFreqInHz) SDK_CovertUsToCount(us, clockFreqInHz) +/*! Macro to convert a raw count value to microsecond */ +#define COUNT_TO_USEC(count, clockFreqInHz) SDK_CovertCountToUs(count, clockFreqInHz) +/*! Macro to convert a millisecond period to raw count value */ +/* To avoid overflow, ms is maximum to 42949ms @ clockFreqInHz = 100MHz */ +#define MSEC_TO_COUNT(ms, clockFreqInHz) SDK_CovertMsToCount(ms, clockFreqInHz) +/*! Macro to convert a raw count value to millisecond */ +#define COUNT_TO_MSEC(count, clockFreqInHz) SDK_CovertCountToMs(count, clockFreqInHz) +#endif +/*! @} */ + +#define SDK_ISR_EXIT_BARRIER + +/*! @name Alignment variable definition macros */ +/*! @{ */ +/*! Macro to define a variable with alignbytes alignment */ +#define SDK_ALIGN(var, alignbytes) var __attribute__((aligned(alignbytes))) + +#define AT_NONCACHEABLE_SECTION(var) var +#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) var __attribute__((aligned(alignbytes))) +#define AT_NONCACHEABLE_SECTION_INIT(var) var +#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) var __attribute__((aligned(alignbytes))) +/*! @} */ + +/*! @brief Default DSC interrupt priority number. */ +#define SDK_DSC_DEFAULT_INT_PRIO 1U + +/*! @brief Set base core IRQ priority, that core will response the interrupt request with priority >= base IRQ priority. + */ +#define SetIRQBasePriority(x) __EI##x() + +/*! + * @brief Read register value. + * + * Example: + * val = PeriphReadReg(OCCS->OSCTL2); + * + * @param reg Register name. + * + * @return The value of register. + */ +#define PeriphReadReg(reg) (reg) + +/*! + * @brief Write data to register. + * + * Example: + * PeriphWriteReg(OCCS->OSCTL2, 0x278U); + * + * @param reg Register name. + * @param data Data wrote to register. + */ +#define PeriphWriteReg(reg, data) (reg) = (data) + +/*! + * @brief Set specified bits in register. + * + * Example: + * PeriphSetBits(OCCS->OSCTL2, 0x12U); + * + * @param reg Register name. + * @param bitMask Bits mask, set bits will be set in the register. + */ +#define PeriphSetBits(reg, bitMask) (reg) |= (bitMask) + +/*! + * @brief Clear specified bits in register. + * + * Example: + * PeriphClearBits(OCCS->OSCTL2, 0x12U); + * + * @param reg Register name. + * @param bitMask Bits mask, set bits will be cleared in the register. + */ +#define PeriphClearBits(reg, bitMask) (reg) &= (~(bitMask)) + +/*! + * @brief Invert specified bits in register. + * + * Example: + * PeriphInvertBits(OCCS->OSCTL2, 0x12U); + * + * @param reg Register name. + * @param bitMask Bits mask, set bits will be inverted in the register. + */ +#define PeriphInvertBits(reg, bitMask) (reg) ^= (bitMask) + +/*! + * @brief Get specified bits in register. + * + * Example: + * val = PeriphGetBits(OCCS->OSCTL2, 0x23U); + * + * @param reg Register name. + * @param bitMask Bits mask, specify the getting bits. + * + * @return The value of specified bits. + */ +#define PeriphGetBits(reg, bitMask) ((reg) & (bitMask)) + +/*! + * @brief Write group of bits to register. + * + * Example: + * PeriphWriteBitGroup(OCCS->DIVBY, OCCS_DIVBY_COD_MASK, OCCS_DIVBY_COD(23U)); + * PeriphWriteBitGroup(OCCS->DIVBY, OCCS_DIVBY_COD_MASK | OCCS_DIVBY_PLLDB_MASK, \ + * OCCS_DIVBY_COD(23U) | OCCS_DIVBY_PLLDB(49U)); + * + * @param reg Register name. + * @param bitMask Bits mask, mask of the group of bits. + * @param bitValue This value will be written into the bit group specified by parameter bitMask. + */ +#define PeriphWriteBitGroup(reg, bitMask, bitValue) (reg) = ((reg) & ~(bitMask)) | ((bitValue) & (bitMask)) + +/*! + * @brief Clear (acknowledge) flags which are active-high and are cleared-by-write-one. + * + * This macro is useful when a register is comprised by normal read-write bits and cleared-by-write-one bits. + * Example: + * PeriphSafeClearFlags(PWMA->FAULT[0].FSTS, PWM_FSTS_FFLAG_MASK, PWM_FSTS_FFLAG(2)); + * + * @param reg Register name. + * @param allFlagsMask Mask for all flags which are active-high and are cleared-by-write-one. + * @param flagMask The selected flags(cleared-by-write-one) which are supposed to be cleared. + */ +#define PeriphSafeClearFlags(reg, allFlagsMask, flagMask) \ + (reg) = ((reg) & (~(allFlagsMask))) | ((flagMask) & (allFlagsMask)) + +/*! + * @brief Clear selected bits without modifying (acknowledge) bit flags which are active-high and are + * cleared-by-write-one. + * + * This macro is useful when a register is comprised by normal read-write bits and cleared-by-write-one bits. + * Example: + * PeriphSafeClearBits(PWMA->FAULT[0].FSTS, PWM_FSTS_FFLAG_MASK, PWM_FSTS_FHALF(2)); + * + * @param reg Register name. + * @param allFlagsMask Mask for all flags which are active-high and are cleared-by-write-one. + * @param bitMask The selected bits which are supposed to be cleared. + */ +#define PeriphSafeClearBits(reg, allFlagsMask, bitMask) (reg) = ((reg) & (~((allFlagsMask) | (bitMask)))) + +/*! + * @brief Set selected bits without modifying (acknowledge) bit flags which are active-high and are + * cleared-by-write-one. + * + * This macro is useful when a register is comprised by normal read-write bits and cleared-by-write-one bits. + * Example: + * PeriphSafeSetBits(PWMA->FAULT[0].FSTS, PWM_FSTS_FFLAG_MASK, PWM_FSTS_FHALF(2)); + * + * @param reg Register name. + * @param allFlagsMask Mask for all flags which are active-high and are cleared-by-write-one. + * @param bitMask The selected bits which are supposed to be set. + */ +#define PeriphSafeSetBits(reg, allFlagsMask, bitMask) \ + (reg) = ((reg) & (~(allFlagsMask))) | ((bitMask) & (~(allFlagsMask))) + +/*! + * @brief Write group of bits without modifying (acknowledge) bit flags which are active-high and are + * cleared-by-write-one. + * + * This macro is useful when a register is comprised by normal read-write bits and cleared-by-write-one bits. + * Example: + * PeriphSafeWriteBitGroup(PWMA->FAULT[0].FSTS, PWM_FSTS_FFLAG_MASK, PWM_FSTS_FHALF_MASK, PWM_FSTS_FHALF(3U)); + * PeriphSafeWriteBitGroup(PWMA->FAULT[0].FSTS, PWM_FSTS_FFLAG_MASK, PWM_FSTS_FHALF_MASK | PWM_FSTS_FFULL_MASK, \ + * PWM_FSTS_FHALF(3U) | PWM_FSTS_FFULL(2U)); + * + * @param reg Register name. + * @param allFlagsMask Mask for all flags which are active-high and are cleared-by-write-one. + * @param bitMask Bits mask, mask of the group of bits. + * @param bitValue This value will be written into the bit group specified by parameter bitMask. + */ +#define PeriphSafeWriteBitGroup(reg, allFlagsMask, bitMask, bitValue) \ + (reg) = ((reg) & (~((allFlagsMask) | (bitMask)))) | ((bitValue) & (bitMask) & (~(allFlagsMask))) + +/*! + * @brief Get IP register byte address with uint32_t type. + * + * This macro is useful when a register byte address is required, especially in SDM mode. + * Example: + * SDK_GET_REGISTER_BYTE_ADDR(ADC_Type, ADC, RSLT[0]); + * + * @param ipType IP register mapping struct type. + * @param ipBase IP instance base pointer, WORD address. + * @param regName Member register name of IP register mapping struct. + */ +#define SDK_GET_REGISTER_BYTE_ADDR(ipType, ipBase, regName) \ + ((2UL * ((uint32_t)(ipBase))) + ((uint32_t)(uint8_t *)&(((ipType *)0)->regName))) + +/* Macros for compatibility. */ +#define MSDK_REG_SECURE_ADDR(x) (x) +#define MSDK_REG_NONSECURE_ADDR(x) (x) + +/* + * The fsl_clock.h is included here because it needs MAKE_VERSION/MAKE_STATUS/status_t. + */ +#include "fsl_clock.h" + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @brief Disable the global IRQ + */ +static inline uint32_t DisableGlobalIRQ(void) +{ + uint32_t ret; + if ((INTC->CTRL & INTC_CTRL_INT_DIS_MASK) != 0U) + { + ret = 0U; + } + else + { + INTC->CTRL |= INTC_CTRL_INT_DIS_MASK; + ret = 1U; + } + return ret; +} + +/*! + * @brief Enable the global IRQ + */ +static inline void EnableGlobalIRQ(uint32_t irqSts) +{ + if (irqSts != 0U) + { + INTC->CTRL &= ~INTC_CTRL_INT_DIS_MASK; + } + else + { + INTC->CTRL |= INTC_CTRL_INT_DIS_MASK; + } +} + +/*! + * @brief Check if currently core is able to response IRQ + */ +static inline bool isIRQAllowed(void) +{ + bool ret = true; + uint16_t srReg; + + if (0U != (INTC->CTRL | INTC_CTRL_INT_DIS_MASK)) + { + ret = false; + } + + asm {move.w SR, srReg} + ; + if (0U != (srReg & 0x300U)) + { + ret = false; + } + return ret; +} + +/*! + * @name Interrupt + * + * DSC interrupt controller uses the same bit-filed to control interrupt enable + * status and priority, to provide compatible APIs, SDK uses a interrupt priority + * table, thus application could control the interrupt + * enable/disable, and interrupt priority independently. Also, the API + * @ref EnableIRQWithPriority could be used to enable the interrupt and set the priority + * at the same time. + * + * API implementation: + * + * 1. When calling @ref EnableIRQ, if the interrupt priority in priority table is + * valid, then set the interrupt priority level to the value in priority table + * If interrupt priority in priority table is invalid, then set the interrupt + * priority level to @ref SDK_DSC_DEFAULT_INT_PRIO. + * + * 2. When calling @ref IRQ_SetPriority, if the interrupt is already enabled, new + * priority is set to interrupt controller, meanwhile the priority table is + * updated accordingly. If the interrupt is not enabled, new priority value is + * saved to priority table , and takes effect when calling @ref EnableIRQ. + * + * The interrupt functions configure INTC module, application could call the + * INTC driver directly for the same purpose. + * + * @{ + */ + +/*! + * @brief Enable the IRQ, and also set the interrupt priority. + * + * @note The parameter @p priNum is range in 1~3, and its value is **NOT** + * directly map to interrupt priority. + * + * - Some IPs maps 1 to priority 1, 2 to priority 2, 3 to priority 3 + * - Some IPs maps 1 to priority 0, 2 to priority 1, 3 to priority 2 + * + * User should check chip's RM to get its corresponding interrupt priority. + * + * When @p priNum set as 0, then @ref SDK_DSC_DEFAULT_INT_PRIO is set instead. + * When @p priNum set as number larger than 3, then only the 2 LSB take effect, + * for example, setting @p priNum to 5 is the same with setting it to 1. + * + * This function configures INTC module, application could call the + * INTC driver directly for the same purpose. + * + * @param irq The IRQ to enable. + * @param priNum Priority number set to interrupt controller register. + * Larger number means higher priority. + * The allowed range is 1~3, and its value is **NOT** directly map to interrupt priority. + * In other words, the same priority number means different interrupt priority levels + * for different IRQ, please check reference manual for the relationship. + * When pass in 0, then @ref SDK_DSC_DEFAULT_INT_PRIO is set to priority register. + * + * @return Currently only returns kStatus_Success, will enhance in the future. + */ +status_t EnableIRQWithPriority(IRQn_Type irq, uint8_t priNum); + +/*! + * @brief Disable specific interrupt. + * + * This function configures INTC module, application could call the + * INTC driver directly for the same purpose. + * + * @param irq The IRQ to disable. + * + * @return Currently only returns kStatus_Success, will enhance in the future. + */ +status_t DisableIRQ(IRQn_Type irq); + +/*! + * @brief Enable specific interrupt. + * + * The recommended workflow is calling @ref IRQ_SetPriority first, then call + * @ref EnableIRQ. If @ref IRQ_SetPriority is not called first, then the interrupt + * is enabled with default priority value @ref SDK_DSC_DEFAULT_INT_PRIO. + * + * Another recommended workflow is calling @ref EnableIRQWithPriority directly, + * it is the same with calling @ref IRQ_SetPriority + @ref EnableIRQ. + * + * This function configures INTC module, application could call the + * INTC driver directly for the same purpose. + * + * @param irq The IRQ to enable. + * + * @return Currently only returns kStatus_Success, will enhance in the future. + */ +status_t EnableIRQ(IRQn_Type irq); + +/*! + * @brief Set the IRQ priority. + * + * @note The parameter @p priNum is range in 1~3, and its value is **NOT** + * directly map to interrupt priority. + * + * - Some IPs maps 1 to priority 1, 2 to priority 2, 3 to priority 3 + * - Some IPs maps 1 to priority 0, 2 to priority 1, 3 to priority 2 + * + * User should check chip's RM to get its corresponding interrupt priority + * + * When @p priNum set as 0, then @ref SDK_DSC_DEFAULT_INT_PRIO is set instead. + * When @p priNum set as number larger than 3, then only the 2 LSB take effect, + * for example, setting @p priNum to 5 is the same with setting it to 1. + * + * This function configures INTC module, application could call the + * INTC driver directly for the same purpose. + * + * @param irq The IRQ to set. + * @param priNum Priority number set to interrupt controller register. + * Larger number means higher priority, 0 means disable the interrupt. + * The allowed range is 0~3, and its value is **NOT** directly map to interrupt priority. + * In other words, the same priority number means different interrupt priority levels + * for different IRQ, please check reference manual for the relationship. + * + * @return Currently only returns kStatus_Success, will enhance in the future. + */ +status_t IRQ_SetPriority(IRQn_Type irq, uint8_t priNum); + +/*! @} */ + +/*! + * @brief Delay core cycles. + * Please note that, this API uses software loop for delay, the actual delayed + * time depends on core clock frequency, where the function is located (ram or flash), + * flash clock, possible interrupt. + * + * @param u32Num Number of core clock cycle which needs to be delayed. + */ +void SDK_DelayCoreCycles(uint32_t u32Num); + +/*! + * @brief Covert us to count with fixed-point calculation. + * + * @note u32Us must not be greater than 4294 + * + * @param u32Us Time in us + * @param u32Hz Clock frequency in Hz + * @return The count value + */ +uint32_t SDK_CovertUsToCount(uint32_t u32Us, uint32_t u32Hz); + +/*! + * @brief Covert count to us with fixed-point calculation. + * + * @note u32Hz must not be greater than 429496729UL(0xFFFFFFFFUL/10UL) + * + * @param u32Count Count value + * @param u32Hz Clock frequency in Hz + * @return The us value + */ +uint32_t SDK_CovertCountToUs(uint32_t u32Count, uint32_t u32Hz); + +/*! + * @brief Covert ms to count with fixed-point calculation. + * + * @note u32Ms must not be greater than 42949UL @ u32Hz = 100M + * + * @param u32Ms Time in us + * @param u32Hz Clock frequency in Hz + * @return The count value + */ +uint32_t SDK_CovertMsToCount(uint32_t u32Ms, uint32_t u32Hz); + +/*! + * @brief Covert count to ms with fixed-point calculation. + * + * @note u32Hz must not be greater than 429496729UL(0xFFFFFFFFUL/10UL) + * + * @param u32Count Count value + * @param u32Hz Clock frequency in Hz + * @return The us value + */ +uint32_t SDK_CovertCountToMs(uint32_t u32Count, uint32_t u32Hz); + +/*! + * @brief Delay at least for some time in millisecond unit. + * Please note that, this API uses while loop for delay, different run-time environments make the time not precise, + * if precise delay count was needed, please implement a new delay function with hardware timer. + * + * @param delayTime_ms Delay time in unit of millisecond. + * @param coreClock_Hz Core clock frequency with Hz. + */ +void SDK_DelayAtLeastMs(uint32_t delayTime_ms, uint32_t coreClock_Hz); + +#if defined(__cplusplus) +} +#endif + +/*! @} */ + +#endif /* FSL_COMMON_DSC_H_ */ diff --git a/bsp/nxp/imx/imx91/drivers/sdk/drivers/common/fsl_common_dsp.c b/bsp/nxp/imx/imx91/drivers/sdk/drivers/common/fsl_common_dsp.c new file mode 100644 index 00000000000..8a1ea9e1fdf --- /dev/null +++ b/bsp/nxp/imx/imx91/drivers/sdk/drivers/common/fsl_common_dsp.c @@ -0,0 +1,45 @@ +/* + * Copyright (c) 2015-2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_common.h" + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.common_dsp" +#endif + +extern uint32_t xthal_get_ccount(void); + +void SDK_DelayAtLeastUs(uint32_t delayTime_us, uint32_t coreClock_Hz) +{ + uint64_t count; + + if (delayTime_us > 0U) + { + count = USEC_TO_COUNT(delayTime_us, coreClock_Hz); + + assert(count <= UINT32_MAX); + + /* Calculate the count ticks. */ + count += xthal_get_ccount(); + + if (count > UINT32_MAX) + { + count -= UINT32_MAX; + /* Wait for cyccnt overflow. */ + while (count < xthal_get_ccount()) + { + } + } + + /* Wait for cyccnt reach count value. */ + while (count > xthal_get_ccount()) + { + } + } +} diff --git a/bsp/nxp/imx/imx91/drivers/sdk/drivers/common/fsl_common_dsp.h b/bsp/nxp/imx/imx91/drivers/sdk/drivers/common/fsl_common_dsp.h new file mode 100644 index 00000000000..c3662abade7 --- /dev/null +++ b/bsp/nxp/imx/imx91/drivers/sdk/drivers/common/fsl_common_dsp.h @@ -0,0 +1,174 @@ +/* + * Copyright (c) 2015-2016, Freescale Semiconductor, Inc. + * Copyright 2016-2020, 2024 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef FSL_COMMON_DSP_H_ +#define FSL_COMMON_DSP_H_ + +/*! + * @addtogroup ksdk_common + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Timer utilities */ +/*! @{ */ +/*! Macro to convert a microsecond period to raw count value */ +#define USEC_TO_COUNT(us, clockFreqInHz) (uint64_t)(((uint64_t)(us) * (clockFreqInHz)) / 1000000U) +/*! Macro to convert a raw count value to microsecond */ +#define COUNT_TO_USEC(count, clockFreqInHz) (uint64_t)((uint64_t)(count) * 1000000U / (clockFreqInHz)) + +/*! Macro to convert a millisecond period to raw count value */ +#define MSEC_TO_COUNT(ms, clockFreqInHz) (uint64_t)((uint64_t)(ms) * (clockFreqInHz) / 1000U) +/*! Macro to convert a raw count value to millisecond */ +#define COUNT_TO_MSEC(count, clockFreqInHz) (uint64_t)((uint64_t)(count) * 1000U / (clockFreqInHz)) +/*! @} */ + +#define SDK_ISR_EXIT_BARRIER + +/*! @name Alignment variable definition macros */ +/*! @{ */ +/*! Macro to define a variable with alignbytes alignment */ +#define SDK_ALIGN(var, alignbytes) var __attribute__((aligned(alignbytes))) + +/*! Macro to define a variable with L1 d-cache line size alignment */ +#if defined(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) +#define SDK_L1DCACHE_ALIGN(var) SDK_ALIGN(var, FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) +#endif + +/*! Macro to define a variable with L2 cache line size alignment */ +#if defined(FSL_FEATURE_L2CACHE_LINESIZE_BYTE) +#define SDK_L2CACHE_ALIGN(var) SDK_ALIGN(var, FSL_FEATURE_L2CACHE_LINESIZE_BYTE) +#endif + +/*! Macro to change a value to a given size aligned value */ +#define SDK_SIZEALIGN(var, alignbytes) \ + ((unsigned int)((var) + ((alignbytes)-1U)) & (unsigned int)(~(unsigned int)((alignbytes)-1U))) +/*! @} */ + +/*! @name Non-cacheable region definition macros */ +/* For initialized non-zero non-cacheable variables, please using "AT_NONCACHEABLE_SECTION_INIT(var) ={xx};" or + * "AT_NONCACHEABLE_SECTION_ALIGN_INIT(var) ={xx};" in your projects to define them, for zero-inited non-cacheable variables, + * please using "AT_NONCACHEABLE_SECTION(var);" or "AT_NONCACHEABLE_SECTION_ALIGN(var);" to define them, these zero-inited variables + * will be initialized to zero in system startup. + */ +/*! @{ */ + +#define AT_NONCACHEABLE_SECTION_INIT(var) __attribute__((section("NonCacheable.init"))) var +#define AT_NONCACHEABLE_SECTION(var) __attribute__((section("NonCacheable"))) var +#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) \ + __attribute__((section("NonCacheable.init"))) var __attribute__((aligned(alignbytes))) +#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) \ + __attribute__((section("NonCacheable"))) var __attribute__((aligned(alignbytes))) + +/*! @} */ + +/*! + * @name Time sensitive region + * @{ + */ +#if (defined(FSL_SDK_DRIVER_QUICK_ACCESS_ENABLE) && FSL_SDK_DRIVER_QUICK_ACCESS_ENABLE) + +#define AT_QUICKACCESS_SECTION_CODE(func) __attribute__((section("CodeQuickAccess"), __noinline__)) func +#define AT_QUICKACCESS_SECTION_DATA(func) __attribute__((section("DataQuickAccess"))) func + +#else /* __FSL_SDK_DRIVER_QUICK_ACCESS_ENABLE */ + +#define AT_QUICKACCESS_SECTION_CODE(func) func +#define AT_QUICKACCESS_SECTION_DATA(func) func + +#endif /* __FSL_SDK_DRIVER_QUICK_ACCESS_ENABLE */ +/*! @} */ + +/* Macros for compatibility. */ +#define NVIC_SetPriorityGrouping(value) do {} while(0) +#define NVIC_GetPriorityGrouping() do {} while(0) +#define NVIC_SetPriority(irq, value) do {} while(0) +#define NVIC_GetPriority(irq) do {} while(0) +#define NVIC_EnableIRQ(value) do {} while(0) +#define NVIC_GetEnableIRQ(value) do {} while(0) +#define NVIC_DisableIRQ(value) do {} while(0) +#define NVIC_GetPendingIRQ(value) do {} while(0) +#define NVIC_SetPendingIRQ(value) do {} while(0) +#define NVIC_ClearPendingIRQ(value) do {} while(0) +#define NVIC_GetActive(value) do {} while(0) +#define MSDK_REG_SECURE_ADDR(x) (x) +#define MSDK_REG_NONSECURE_ADDR(x) (x) + +/* + * The fsl_clock.h is included here because it needs MAKE_VERSION/MAKE_STATUS/status_t + * defined in previous of this file. + */ +#include "fsl_clock.h" + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @brief Enable specific interrupt. + * + * Empty function for build compatibility. + * + * @param interrupt The IRQ number. + * @return Always return kStatus_Success. + */ +static inline status_t EnableIRQ(IRQn_Type interrupt) +{ + return kStatus_Success; +} + +/*! + * @brief Disable specific interrupt. + * + * Empty function for build compatibility. + * + * @param interrupt The IRQ number. + * @return Always return kStatus_Success. + */ +static inline status_t DisableIRQ(IRQn_Type interrupt) +{ + return kStatus_Success; +} + +/*! + * @brief Disable the global IRQ + * + * Empty function for build compatibility. + * + * @return Always return 0; + */ +static inline uint32_t DisableGlobalIRQ(void) +{ + return 0; +} + +/*! + * @brief Enable the global IRQ + * + * Empty function for build compatibility. + * + * @param primask Not used. + */ +static inline void EnableGlobalIRQ(uint32_t primask) +{ +} + +#if defined(__cplusplus) +} +#endif + +/*! @} */ + +#endif /* FSL_COMMON_DSP_H_ */ diff --git a/bsp/nxp/imx/imx91/drivers/sdk/drivers/common/fsl_common_riscv.c b/bsp/nxp/imx/imx91/drivers/sdk/drivers/common/fsl_common_riscv.c new file mode 100644 index 00000000000..c3e9bd556a1 --- /dev/null +++ b/bsp/nxp/imx/imx91/drivers/sdk/drivers/common/fsl_common_riscv.c @@ -0,0 +1,45 @@ +/* + * Copyright 2024 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_common.h" + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.common_riscv" +#endif + +static void DelayLoop(uint32_t count) +{ + __ASM volatile( + " mv a0, %0 \n" + "loop%=: \n" + " addi a0, a0, -1 \n" + " bgtz a0, loop%= \n" + : + : "r"(count) + :); +} + +void SDK_DelayAtLeastUs(uint32_t delayTime_us, uint32_t coreClock_Hz) +{ + uint64_t count; + + if (delayTime_us > 0U) + { + count = USEC_TO_COUNT(delayTime_us, coreClock_Hz); + + assert(count <= UINT32_MAX); + + /* + * Add is 1 cycle. + * Branch is 2 cycle. + */ + count = count / 3U; + + DelayLoop((uint32_t)count); + } +} diff --git a/bsp/nxp/imx/imx91/drivers/sdk/drivers/common/fsl_common_riscv.h b/bsp/nxp/imx/imx91/drivers/sdk/drivers/common/fsl_common_riscv.h new file mode 100644 index 00000000000..2366783b646 --- /dev/null +++ b/bsp/nxp/imx/imx91/drivers/sdk/drivers/common/fsl_common_riscv.h @@ -0,0 +1,148 @@ +/* + * Copyright 2024-2025 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef FSL_COMMON_RISCV_H_ +#define FSL_COMMON_RISCV_H_ + +#include "riscv_interrupt.h" + +/*! + * @addtogroup ksdk_common + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Timer utilities */ +/*! @{ */ +/*! Macro to convert a microsecond period to raw count value */ +#define USEC_TO_COUNT(us, clockFreqInHz) (uint64_t)(((uint64_t)(us) * (clockFreqInHz)) / 1000000U) +/*! Macro to convert a raw count value to microsecond */ +#define COUNT_TO_USEC(count, clockFreqInHz) (uint64_t)((uint64_t)(count) * 1000000U / (clockFreqInHz)) + +/*! Macro to convert a millisecond period to raw count value */ +#define MSEC_TO_COUNT(ms, clockFreqInHz) (uint64_t)((uint64_t)(ms) * (clockFreqInHz) / 1000U) +/*! Macro to convert a raw count value to millisecond */ +#define COUNT_TO_MSEC(count, clockFreqInHz) (uint64_t)((uint64_t)(count) * 1000U / (clockFreqInHz)) +/*! @} */ + +#define SDK_ISR_EXIT_BARRIER + +/*! @name Alignment variable definition macros */ +/*! @{ */ +/*! Macro to define a variable with alignbytes alignment */ +#define SDK_ALIGN(var, alignbytes) var __attribute__((aligned(alignbytes))) + +/*! Macro to change a value to a given size aligned value */ +#define SDK_SIZEALIGN(var, alignbytes) \ + ((unsigned int)((var) + ((alignbytes)-1U)) & (unsigned int)(~(unsigned int)((alignbytes)-1U))) +/*! @} */ + +/*! + * @def MSDK_REG_SECURE_ADDR(x) + * Convert the register address to the one used in secure mode. + * + * @def MSDK_REG_NONSECURE_ADDR(x) + * Convert the register address to the one used in unsecure mode. + */ +#define MSDK_REG_SECURE_ADDR(x) ((typeof(x))((uintptr_t)(x) | (0x1UL << 28))) +#define MSDK_REG_NONSECURE_ADDR(x) ((typeof(x))((uintptr_t)(x) & ~(0x1UL << 28))) + +/* + * The fsl_clock.h is included here because it needs MAKE_VERSION/MAKE_STATUS/status_t + * defined in previous of this file. + */ +#include "fsl_clock.h" + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @brief Enable specific interrupt. + * + * Empty function for build compatibility. + * + * @param interrupt The IRQ number. + * @return Always return kStatus_Success. + */ +static inline status_t EnableIRQ(IRQn_Type interrupt) +{ + return kStatus_Success; +} + +/*! + * @brief Disable specific interrupt. + * + * Empty function for build compatibility. + * + * @param interrupt The IRQ number. + * @return Always return kStatus_Success. + */ +static inline status_t DisableIRQ(IRQn_Type interrupt) +{ + return kStatus_Success; +} + +/*! + * @brief Disable the global IRQ + * + * Disable the global IRQ. + * + * @return The global IRQ control register value before been disabled. + */ +static inline uint32_t DisableGlobalIRQ(void) +{ + return csr_read_clear(CSR_MSTATUS, CSR_MSTATUS_MIE); +} + +/*! + * @brief Enable the global IRQ + * + * Enable the global interrupt by setting the global IRQ control register. + * Generally this value is the return value of DisableGlobalIRQ. + * + * @param intCtrl The global interrupt control register value. + */ +static inline void EnableGlobalIRQ(uint32_t intCtrl) +{ + csr_set(CSR_MSTATUS, intCtrl); +} + +/*! + * @brief Enable M-mode interrupt. + * + * @param mask M-mode interrupt mask. + */ +static inline void EnableMachineModeInt(ezhv_mie_mask_t mask) +{ + csr_set(CSR_MIE, mask); +} + +/*! + * @brief Disable M-mode interrupt. + * + * @param mask M-mode interrupt mask. + */ +static inline void DisableMachineModeInt(ezhv_mie_mask_t mask) +{ + csr_clear(CSR_MIE, mask); +} + +#if defined(__cplusplus) +} +#endif + +/*! @} */ + +#endif diff --git a/bsp/nxp/imx/imx91/drivers/sdk/drivers/lpuart/SConscript b/bsp/nxp/imx/imx91/drivers/sdk/drivers/lpuart/SConscript new file mode 100644 index 00000000000..fa6cdfab67b --- /dev/null +++ b/bsp/nxp/imx/imx91/drivers/sdk/drivers/lpuart/SConscript @@ -0,0 +1,17 @@ +# for module compiling +import os +from building import * + +cwd = GetCurrentDir() + +src = Glob('fsl_lpuart.c') + +CPPPATH = [cwd] +objs = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH) + +for item in os.listdir(cwd): + sconsfile = os.path.join(item, 'SConscript') + if os.path.isfile(os.path.join(cwd, sconsfile)): + objs += SConscript(sconsfile) + +Return('objs') diff --git a/bsp/nxp/imx/imx91/drivers/sdk/drivers/lpuart/fsl_lpuart.c b/bsp/nxp/imx/imx91/drivers/sdk/drivers/lpuart/fsl_lpuart.c new file mode 100644 index 00000000000..8e9fa360b93 --- /dev/null +++ b/bsp/nxp/imx/imx91/drivers/sdk/drivers/lpuart/fsl_lpuart.c @@ -0,0 +1,2786 @@ +/* + * Copyright (c) 2015-2016, Freescale Semiconductor, Inc. + * Copyright 2016-2022, 2025 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_lpuart.h" + +#include + +#define memset rt_memset + +/* + * $Coverage Justification Reference$ + * + * $Justification fsl_lpuart_c_ref_1$ + * (osr > 3) (false) can't be not covered, because osr(osrTemp) is increased from 4U. + * + * $Justification fsl_lpuart_c_ref_2$ + * The flag is cleared successfully during test. + */ +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.lpuart" +#endif + +/* LPUART transfer state. */ +enum +{ + kLPUART_TxIdle, /*!< TX idle. */ + kLPUART_TxBusy, /*!< TX busy. */ + kLPUART_RxIdle, /*!< RX idle. */ + kLPUART_RxBusy /*!< RX busy. */ +}; + +#if defined(LPUART_RSTS) +#define LPUART_RESETS_ARRAY LPUART_RSTS +#endif + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +/*! + * @brief Check whether the RX ring buffer is full. + * + * @userData handle LPUART handle pointer. + * @retval true RX ring buffer is full. + * @retval false RX ring buffer is not full. + */ +static bool LPUART_TransferIsRxRingBufferFull(LPUART_Type *base, lpuart_handle_t *handle); + +/*! + * @brief Write to TX register using non-blocking method. + * + * This function writes data to the TX register directly, upper layer must make + * sure the TX register is empty or TX FIFO has empty room before calling this function. + * + * @note This function does not check whether all the data has been sent out to bus, + * so before disable TX, check kLPUART_TransmissionCompleteFlag to ensure the TX is + * finished. + * + * @param base LPUART peripheral base address. + * @param data Start address of the data to write. + * @param length Size of the buffer to be sent. + */ +static void LPUART_WriteNonBlocking(LPUART_Type *base, const uint8_t *data, size_t length); +/*! + * @brief Write to TX register using non-blocking method in 9bit or 10bit mode. + * + * The 10bit of data will be writen to TX register DATA. + * Please make sure data 10bit is valid and other bit is 0. + * + * @note This function only support 9bit or 10bit transfer. + * + * @param base LPUART peripheral base address. + * @param data Start address of the data to write. + * @param length Size of the buffer to be sent. + */ +static void LPUART_WriteNonBlocking16bit(LPUART_Type *base, const uint16_t *data, size_t length); + +/*! + * @brief Read RX register using non-blocking method. + * + * This function reads data from the TX register directly, upper layer must make + * sure the RX register is full or TX FIFO has data before calling this function. + * + * @param base LPUART peripheral base address. + * @param data Start address of the buffer to store the received data. + * @param length Size of the buffer. + */ +static void LPUART_ReadNonBlocking(LPUART_Type *base, uint8_t *data, size_t length); +/*! + * @brief Read RX register using non-blocking method in 9bit or 10bit mode. + * + * This function reads 10bit data from the RX register directly and stores to 16bit data. + * + * @note This function only support 9bit or 10bit transfer. + * + * @param base LPUART peripheral base address. + * @param data Start address of the buffer to store the received data. + * @param length Size of the buffer. + */ +static void LPUART_ReadNonBlocking16bit(LPUART_Type *base, uint16_t *data, size_t length); +/*! + * @brief LPUART_TransferHandleIDLEIsReady handle function. + * This function handles when IDLE is ready. + * + * @param base LPUART peripheral base address. + * @param irqHandle LPUART handle pointer. + */ +static void LPUART_TransferHandleIDLEReady(LPUART_Type *base, lpuart_handle_t *handle); + +/*! + * @brief LPUART_TransferHandleReceiveDataIsFull handle function. + * This function handles when receive data is full. + * + * @param base LPUART peripheral base address. + * @param handle LPUART handle pointer. + */ +static void LPUART_TransferHandleReceiveDataFull(LPUART_Type *base, lpuart_handle_t *handle); + +/*! + * @brief LPUART_TransferHandleSendDataIsEmpty handle function. + * This function handles when send data is empty. + * + * @param base LPUART peripheral base address. + * @param irqHandle LPUART handle pointer. + */ +static void LPUART_TransferHandleSendDataEmpty(LPUART_Type *base, lpuart_handle_t *handle); + +/*! + * @brief LPUART_TransferHandleTransmissionIsComplete handle function. + * This function handles Transmission complete and the interrupt is enabled. + * + * @param base LPUART peripheral base address. + * @param irqHandle LPUART handle pointer. + */ +static void LPUART_TransferHandleTransmissionComplete(LPUART_Type *base, lpuart_handle_t *handle); + +/******************************************************************************* + * Variables + ******************************************************************************/ +/* Array of LPUART peripheral base address. */ +static LPUART_Type** const s_lpuartBases[] = LPUART_BASE_PTRS; +/* Array of LPUART handle. */ +void *s_lpuartHandle[ARRAY_SIZE(s_lpuartBases)]; +/* Array of LPUART IRQ number. */ +#if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ +#if defined(LPUART_RX_IRQS) +static const IRQn_Type s_lpuartRxIRQ[] = LPUART_RX_IRQS; +#endif +#if defined(LPUART_TX_IRQS) +const IRQn_Type s_lpuartTxIRQ[] = LPUART_TX_IRQS; +#endif +#else +#if defined(LPUART_RX_TX_IRQS) +const IRQn_Type s_lpuartIRQ[] = LPUART_RX_TX_IRQS; +#endif +#endif +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/* Array of LPUART clock name. */ +static const clock_ip_name_t s_lpuartClock[] = LPUART_CLOCKS; + +#if defined(LPUART_PERIPH_CLOCKS) +/* Array of LPUART functional clock name. */ +static const clock_ip_name_t s_lpuartPeriphClocks[] = LPUART_PERIPH_CLOCKS; +#endif + +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +/* LPUART ISR for transactional APIs. */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +lpuart_isr_t s_lpuartIsr[ARRAY_SIZE(s_lpuartBases)] = {[0 ...(ARRAY_SIZE(s_lpuartBases) - 1)] = + (lpuart_isr_t)DefaultISR}; +#else +lpuart_isr_t s_lpuartIsr[ARRAY_SIZE(s_lpuartBases)]; +#endif + +#if defined(LPUART_RESETS_ARRAY) +/* Reset array */ +static const reset_ip_name_t s_lpuartResets[] = LPUART_RESETS_ARRAY; +#endif + +/******************************************************************************* + * Code + ******************************************************************************/ +/*! + * brief Get the LPUART instance from peripheral base address. + * + * param base LPUART peripheral base address. + * return LPUART instance. + */ +uint32_t LPUART_GetInstance(LPUART_Type *base) +{ + uint32_t instance; + + /* Find the instance index from base address mappings. */ + for (instance = 1U; instance < ARRAY_SIZE(s_lpuartBases); instance++) + { + if (MSDK_REG_SECURE_ADDR(*(s_lpuartBases[instance])) == MSDK_REG_SECURE_ADDR(base)) + { + return instance; + } + } + + assert(instance < ARRAY_SIZE(s_lpuartBases)); + + return instance; +} + +/*! + * @brief Set the LPUART instance to peripheral base address. + * + * @param instance LPUART instance. + * @param base LPUART peripheral base address. + */ +void LPUART_SetInstance(uint32_t instance, LPUART_Type *base) +{ + if (instance >= ARRAY_SIZE(s_lpuartBases) || !instance) + { + return; + } + *(s_lpuartBases[instance]) = base; +} + +/*! + * brief Get the length of received data in RX ring buffer. + * + * userData handle LPUART handle pointer. + * return Length of received data in RX ring buffer. + */ +size_t LPUART_TransferGetRxRingBufferLength(LPUART_Type *base, lpuart_handle_t *handle) +{ + assert(NULL != handle); + + size_t size; + size_t tmpRxRingBufferSize = handle->rxRingBufferSize; + uint16_t tmpRxRingBufferTail = handle->rxRingBufferTail; + uint16_t tmpRxRingBufferHead = handle->rxRingBufferHead; + + if (tmpRxRingBufferTail > tmpRxRingBufferHead) + { + size = ((size_t)tmpRxRingBufferHead + tmpRxRingBufferSize - (size_t)tmpRxRingBufferTail); + } + else + { + size = ((size_t)tmpRxRingBufferHead - (size_t)tmpRxRingBufferTail); + } + + return size; +} + +static bool LPUART_TransferIsRxRingBufferFull(LPUART_Type *base, lpuart_handle_t *handle) +{ + assert(NULL != handle); + + bool full; + + if (LPUART_TransferGetRxRingBufferLength(base, handle) == (handle->rxRingBufferSize - 1U)) + { + full = true; + } + else + { + full = false; + } + return full; +} + +static void LPUART_WriteNonBlocking(LPUART_Type *base, const uint8_t *data, size_t length) +{ + assert(NULL != data); + + size_t i; + + /* The Non Blocking write data API assume user have ensured there is enough space in + peripheral to write. */ + for (i = 0; i < length; i++) + { + base->DATA = data[i]; + } +} +static void LPUART_WriteNonBlocking16bit(LPUART_Type *base, const uint16_t *data, size_t length) +{ + assert(NULL != data); + + size_t i; + + /* The Non Blocking write data API assume user have ensured there is enough space in + peripheral to write. */ + for (i = 0; i < length; i++) + { + base->DATA = data[i]; + } +} + +static void LPUART_ReadNonBlocking(LPUART_Type *base, uint8_t *data, size_t length) +{ + assert(NULL != data); + + size_t i; +#if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT + uint32_t ctrl = base->CTRL; + bool isSevenDataBits = (((ctrl & LPUART_CTRL_M7_MASK) != 0U) || + (((ctrl & LPUART_CTRL_M_MASK) == 0U) && ((ctrl & LPUART_CTRL_PE_MASK) != 0U))); +#endif + + /* The Non Blocking read data API assume user have ensured there is enough space in + peripheral to write. */ + for (i = 0; i < length; i++) + { +#if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT + if (isSevenDataBits) + { + data[i] = (uint8_t)(base->DATA & 0x7FU); + } + else + { + data[i] = (uint8_t)base->DATA; + } +#else + data[i] = (uint8_t)(base->DATA); +#endif + } +} + +static void LPUART_ReadNonBlocking16bit(LPUART_Type *base, uint16_t *data, size_t length) +{ + assert(NULL != data); + + size_t i; + /* The Non Blocking read data API assume user have ensured there is enough space in + peripheral to write. */ + for (i = 0; i < length; i++) + { + data[i] = (uint16_t)(base->DATA & 0x03FFU); + } +} + +/*! + * brief Initializes an LPUART instance with the user configuration structure and the peripheral clock. + * + * This function configures the LPUART module with user-defined settings. Call the LPUART_GetDefaultConfig() function + * to configure the configuration structure and get the default configuration. + * The example below shows how to use this API to configure the LPUART. + * code + * lpuart_config_t lpuartConfig; + * lpuartConfig.baudRate_Bps = 115200U; + * lpuartConfig.parityMode = kLPUART_ParityDisabled; + * lpuartConfig.dataBitsCount = kLPUART_EightDataBits; + * lpuartConfig.isMsb = false; + * lpuartConfig.stopBitCount = kLPUART_OneStopBit; + * lpuartConfig.txFifoWatermark = 0; + * lpuartConfig.rxFifoWatermark = 1; + * LPUART_Init(LPUART1, &lpuartConfig, 20000000U); + * endcode + * + * param base LPUART peripheral base address. + * param config Pointer to a user-defined configuration structure. + * param srcClock_Hz LPUART clock source frequency in HZ. + * retval kStatus_LPUART_BaudrateNotSupport Baudrate is not support in current clock source. + * retval kStatus_Success LPUART initialize succeed + */ +status_t LPUART_Init(LPUART_Type *base, const lpuart_config_t *config, uint32_t srcClock_Hz) +{ + assert(NULL != config); + assert(0U < config->baudRate_Bps); +#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO + assert(FSL_FEATURE_LPUART_FIFO_SIZEn(base) > 0); + assert((uint8_t)FSL_FEATURE_LPUART_FIFO_SIZEn(base) > config->txFifoWatermark); + assert((uint8_t)FSL_FEATURE_LPUART_FIFO_SIZEn(base) > config->rxFifoWatermark); +#endif + + status_t status = kStatus_Success; + uint32_t temp; + uint16_t sbr, sbrTemp; + uint8_t osr, osrTemp; + uint32_t tempDiff, calculatedBaud, baudDiff; + + /* This LPUART instantiation uses a slightly different baud rate calculation + * The idea is to use the best OSR (over-sampling rate) possible + * Note, OSR is typically hard-set to 16 in other LPUART instantiations + * loop to find the best OSR value possible, one that generates minimum baudDiff + * iterate through the rest of the supported values of OSR */ + + baudDiff = config->baudRate_Bps; + osr = 0U; + sbr = 0U; + for (osrTemp = 4U; osrTemp <= 32U; osrTemp++) + { + /* calculate the temporary sbr value */ + sbrTemp = (uint16_t)((srcClock_Hz * 2U / (config->baudRate_Bps * (uint32_t)osrTemp) + 1U) / 2U); + /*set sbrTemp to 1 if the sourceClockInHz can not satisfy the desired baud rate*/ + if (sbrTemp == 0U) + { + sbrTemp = 1U; + } + else if (sbrTemp > LPUART_BAUD_SBR_MASK) + { + sbrTemp = LPUART_BAUD_SBR_MASK; + } + else + { + /* Avoid MISRA 15.7 */ + } + /* Calculate the baud rate based on the temporary OSR and SBR values */ + calculatedBaud = (srcClock_Hz / ((uint32_t)osrTemp * (uint32_t)sbrTemp)); + tempDiff = calculatedBaud > config->baudRate_Bps ? (calculatedBaud - config->baudRate_Bps) : + (config->baudRate_Bps - calculatedBaud); + + if (tempDiff <= baudDiff) + { + baudDiff = tempDiff; + osr = osrTemp; /* update and store the best OSR value calculated */ + sbr = sbrTemp; /* update store the best SBR value calculated */ + } + } + + /* Check to see if actual baud rate is within 3% of desired baud rate + * based on the best calculate OSR value */ + if (baudDiff > ((config->baudRate_Bps / 100U) * 3U)) + { + /* Unacceptable baud rate difference of more than 3%*/ + status = kStatus_LPUART_BaudrateNotSupport; + } + else + { +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + + uint32_t instance = LPUART_GetInstance(base); + + /* Enable lpuart clock */ + (void)CLOCK_EnableClock(s_lpuartClock[instance]); +#if defined(LPUART_PERIPH_CLOCKS) + (void)CLOCK_EnableClock(s_lpuartPeriphClocks[instance]); +#endif + +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +#if defined(LPUART_RESETS_ARRAY) + RESET_ReleasePeripheralReset(s_lpuartResets[LPUART_GetInstance(base)]); +#endif + +#if defined(FSL_FEATURE_LPUART_HAS_GLOBAL) && FSL_FEATURE_LPUART_HAS_GLOBAL + /*Reset all internal logic and registers, except the Global Register */ + LPUART_SoftwareReset(base); +#else + /* Disable LPUART TX RX before setting. */ + base->CTRL &= ~(LPUART_CTRL_TE_MASK | LPUART_CTRL_RE_MASK); +#endif + + temp = base->BAUD; + + /* Acceptable baud rate, check if OSR is between 4x and 7x oversampling. + * If so, then "BOTHEDGE" sampling must be turned on */ + /* + * $Branch Coverage Justification$ + * $ref fsl_lpuart_c_ref_1$ + */ + if ((osr > 3U) && (osr < 8U)) + { + temp |= LPUART_BAUD_BOTHEDGE_MASK; + } + + /* program the osr value (bit value is one less than actual value) */ + temp &= ~LPUART_BAUD_OSR_MASK; + temp |= LPUART_BAUD_OSR((uint32_t)osr - 1UL); + + /* write the sbr value to the BAUD registers */ + temp &= ~LPUART_BAUD_SBR_MASK; + base->BAUD = temp | LPUART_BAUD_SBR(sbr); + + /* Set bit count and parity mode. */ + base->BAUD &= ~LPUART_BAUD_M10_MASK; + + temp = base->CTRL & ~(LPUART_CTRL_PE_MASK | LPUART_CTRL_PT_MASK | LPUART_CTRL_M_MASK | LPUART_CTRL_ILT_MASK | + LPUART_CTRL_IDLECFG_MASK); + + temp |= (uint8_t)config->parityMode | LPUART_CTRL_IDLECFG(config->rxIdleConfig) | + LPUART_CTRL_ILT(config->rxIdleType); + +#if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT + if (kLPUART_SevenDataBits == config->dataBitsCount) + { + if (kLPUART_ParityDisabled != config->parityMode) + { + temp &= ~LPUART_CTRL_M7_MASK; /* Seven data bits and one parity bit */ + } + else + { + temp |= LPUART_CTRL_M7_MASK; + } + } + else +#endif + { + if (kLPUART_ParityDisabled != config->parityMode) + { + temp |= LPUART_CTRL_M_MASK; /* Eight data bits and one parity bit */ + } + } + +#if defined(FSL_FEATURE_LPUART_HAS_CTRL_SWAP) && FSL_FEATURE_LPUART_HAS_CTRL_SWAP + if (config->swapTxdRxd == true) + { + temp |= LPUART_CTRL_SWAP_MASK; + } + else + { + temp &= ~LPUART_CTRL_SWAP_MASK; + } +#endif + + base->CTRL = temp; + +#if defined(FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT) && FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT + /* set stop bit per char */ + temp = base->BAUD & ~LPUART_BAUD_SBNS_MASK; + base->BAUD = temp | LPUART_BAUD_SBNS((uint8_t)config->stopBitCount); +#endif + +#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO + /* Set tx/rx WATER watermark + Note: + Take care of the RX FIFO, RX interrupt request only assert when received bytes + equal or more than RX water mark, there is potential issue if RX water + mark larger than 1. + For example, if RX FIFO water mark is 2, upper layer needs 5 bytes and + 5 bytes are received. the last byte will be saved in FIFO but not trigger + RX interrupt because the water mark is 2. + */ + base->WATER = (((uint32_t)(config->rxFifoWatermark) << 16U) | config->txFifoWatermark); + + /* Enable tx/rx FIFO */ + base->FIFO |= (LPUART_FIFO_TXFE_MASK | LPUART_FIFO_RXFE_MASK); + + /* Flush FIFO */ + base->FIFO |= (LPUART_FIFO_TXFLUSH_MASK | LPUART_FIFO_RXFLUSH_MASK); +#endif + + /* Clear all status flags */ + temp = (LPUART_STAT_RXEDGIF_MASK | LPUART_STAT_IDLE_MASK | LPUART_STAT_OR_MASK | LPUART_STAT_NF_MASK | + LPUART_STAT_FE_MASK | LPUART_STAT_PF_MASK); + +#if defined(FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT) && FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT + temp |= LPUART_STAT_LBKDIF_MASK; +#endif + +#if defined(FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING) && FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING + temp |= (LPUART_STAT_MA1F_MASK | LPUART_STAT_MA2F_MASK); +#endif + +#if defined(FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT) && FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT + /* Set the CTS configuration/TX CTS source. */ + base->MODIR |= LPUART_MODIR_TXCTSC(config->txCtsConfig) | LPUART_MODIR_TXCTSSRC(config->txCtsSource); + if (true == config->enableRxRTS) + { + /* Enable the receiver RTS(request-to-send) function. */ + base->MODIR |= LPUART_MODIR_RXRTSE_MASK; + } + if (true == config->enableTxCTS) + { + /* Enable the CTS(clear-to-send) function. */ + base->MODIR |= LPUART_MODIR_TXCTSE_MASK; + } +#endif + + /* Set data bits order. */ + if (true == config->isMsb) + { + temp |= LPUART_STAT_MSBF_MASK; + } + else + { + temp &= ~LPUART_STAT_MSBF_MASK; + } + + base->STAT |= temp; + + /* Enable TX/RX base on configure structure. */ + temp = base->CTRL; + if (true == config->enableTx) + { + temp |= LPUART_CTRL_TE_MASK; + } + + if (true == config->enableRx) + { + temp |= LPUART_CTRL_RE_MASK; + } + + base->CTRL = temp; + } + + return status; +} +/*! + * brief Deinitializes a LPUART instance. + * + * This function waits for transmit to complete, disables TX and RX, and disables the LPUART clock. + * + * param base LPUART peripheral base address. + */ +void LPUART_Deinit(LPUART_Type *base) +{ + uint32_t temp; + +#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO + /* Wait tx FIFO send out*/ + while (0U != ((base->WATER & LPUART_WATER_TXCOUNT_MASK) >> LPUART_WATER_TXWATER_SHIFT)) + { + } +#endif + /* Wait last char shift out */ + while (0U == (base->STAT & LPUART_STAT_TC_MASK)) + { + } + + /* Clear all status flags */ + temp = (LPUART_STAT_RXEDGIF_MASK | LPUART_STAT_IDLE_MASK | LPUART_STAT_OR_MASK | LPUART_STAT_NF_MASK | + LPUART_STAT_FE_MASK | LPUART_STAT_PF_MASK); + +#if defined(FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT) && FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT + temp |= LPUART_STAT_LBKDIF_MASK; +#endif + +#if defined(FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING) && FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING + temp |= (LPUART_STAT_MA1F_MASK | LPUART_STAT_MA2F_MASK); +#endif + + base->STAT |= temp; + + /* Disable the module. */ + base->CTRL = 0U; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + uint32_t instance = LPUART_GetInstance(base); + + /* Disable lpuart clock */ + (void)CLOCK_DisableClock(s_lpuartClock[instance]); + +#if defined(LPUART_PERIPH_CLOCKS) + (void)CLOCK_DisableClock(s_lpuartPeriphClocks[instance]); +#endif + +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} + +/*! + * brief Gets the default configuration structure. + * + * This function initializes the LPUART configuration structure to a default value. The default + * values are: + * lpuartConfig->baudRate_Bps = 115200U; + * lpuartConfig->parityMode = kLPUART_ParityDisabled; + * lpuartConfig->dataBitsCount = kLPUART_EightDataBits; + * lpuartConfig->isMsb = false; + * lpuartConfig->stopBitCount = kLPUART_OneStopBit; + * lpuartConfig->txFifoWatermark = 0; + * lpuartConfig->rxFifoWatermark = 1; + * lpuartConfig->rxIdleType = kLPUART_IdleTypeStartBit; + * lpuartConfig->rxIdleConfig = kLPUART_IdleCharacter1; + * lpuartConfig->enableTx = false; + * lpuartConfig->enableRx = false; + * + * param config Pointer to a configuration structure. + */ +void LPUART_GetDefaultConfig(lpuart_config_t *config) +{ + assert(NULL != config); + + /* Initializes the configure structure to zero. */ + (void)memset(config, 0, sizeof(*config)); + + config->baudRate_Bps = 115200U; + config->parityMode = kLPUART_ParityDisabled; + config->dataBitsCount = kLPUART_EightDataBits; + config->isMsb = false; +#if defined(FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT) && FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT + config->stopBitCount = kLPUART_OneStopBit; +#endif +#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO + config->txFifoWatermark = 0U; + config->rxFifoWatermark = 0U; +#endif +#if defined(FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT) && FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT + config->enableRxRTS = false; + config->enableTxCTS = false; + config->txCtsConfig = kLPUART_CtsSampleAtStart; + config->txCtsSource = kLPUART_CtsSourcePin; +#endif + config->rxIdleType = kLPUART_IdleTypeStartBit; + config->rxIdleConfig = kLPUART_IdleCharacter1; + config->enableTx = false; + config->enableRx = false; +#if defined(FSL_FEATURE_LPUART_HAS_CTRL_SWAP) && FSL_FEATURE_LPUART_HAS_CTRL_SWAP + config->swapTxdRxd = false; +#endif +} + +/*! + * brief Sets the LPUART instance baudrate. + * + * This function configures the LPUART module baudrate. This function is used to update + * the LPUART module baudrate after the LPUART module is initialized by the LPUART_Init. + * code + * LPUART_SetBaudRate(LPUART1, 115200U, 20000000U); + * endcode + * + * param base LPUART peripheral base address. + * param baudRate_Bps LPUART baudrate to be set. + * param srcClock_Hz LPUART clock source frequency in HZ. + * retval kStatus_LPUART_BaudrateNotSupport Baudrate is not supported in the current clock source. + * retval kStatus_Success Set baudrate succeeded. + */ +status_t LPUART_SetBaudRate(LPUART_Type *base, uint32_t baudRate_Bps, uint32_t srcClock_Hz) +{ + assert(0U < baudRate_Bps); + + status_t status = kStatus_Success; + uint32_t temp, oldCtrl; + uint16_t sbr, sbrTemp; + uint8_t osr, osrTemp; + uint32_t tempDiff, calculatedBaud, baudDiff; + + /* This LPUART instantiation uses a slightly different baud rate calculation + * The idea is to use the best OSR (over-sampling rate) possible + * Note, OSR is typically hard-set to 16 in other LPUART instantiations + * loop to find the best OSR value possible, one that generates minimum baudDiff + * iterate through the rest of the supported values of OSR */ + + baudDiff = baudRate_Bps; + osr = 0U; + sbr = 0U; + for (osrTemp = 4U; osrTemp <= 32U; osrTemp++) + { + /* calculate the temporary sbr value */ + sbrTemp = (uint16_t)((srcClock_Hz * 2U / (baudRate_Bps * (uint32_t)osrTemp) + 1U) / 2U); + /*set sbrTemp to 1 if the sourceClockInHz can not satisfy the desired baud rate*/ + if (sbrTemp == 0U) + { + sbrTemp = 1U; + } + else if (sbrTemp > LPUART_BAUD_SBR_MASK) + { + sbrTemp = LPUART_BAUD_SBR_MASK; + } + else + { + /* Avoid MISRA 15.7 */ + } + /* Calculate the baud rate based on the temporary OSR and SBR values */ + calculatedBaud = srcClock_Hz / ((uint32_t)osrTemp * (uint32_t)sbrTemp); + + tempDiff = calculatedBaud > baudRate_Bps ? (calculatedBaud - baudRate_Bps) : (baudRate_Bps - calculatedBaud); + + if (tempDiff <= baudDiff) + { + baudDiff = tempDiff; + osr = osrTemp; /* update and store the best OSR value calculated */ + sbr = sbrTemp; /* update store the best SBR value calculated */ + } + } + + /* Check to see if actual baud rate is within 3% of desired baud rate + * based on the best calculate OSR value */ + if (baudDiff < (uint32_t)((baudRate_Bps / 100U) * 3U)) + { + /* Store CTRL before disable Tx and Rx */ + oldCtrl = base->CTRL; + + /* Disable LPUART TX RX before setting. */ + base->CTRL &= ~(LPUART_CTRL_TE_MASK | LPUART_CTRL_RE_MASK); + + temp = base->BAUD; + + /* Acceptable baud rate, check if OSR is between 4x and 7x oversampling. + * If so, then "BOTHEDGE" sampling must be turned on */ + /* + * $Branch Coverage Justification$ + * $ref fsl_lpuart_c_ref_1$ + */ + if ((osr > 3U) && (osr < 8U)) + { + temp |= LPUART_BAUD_BOTHEDGE_MASK; + } + + /* program the osr value (bit value is one less than actual value) */ + temp &= ~LPUART_BAUD_OSR_MASK; + temp |= LPUART_BAUD_OSR((uint32_t)osr - 1UL); + + /* write the sbr value to the BAUD registers */ + temp &= ~LPUART_BAUD_SBR_MASK; + base->BAUD = temp | LPUART_BAUD_SBR(sbr); + + /* Restore CTRL. */ + base->CTRL = oldCtrl; + } + else + { + /* Unacceptable baud rate difference of more than 3%*/ + status = kStatus_LPUART_BaudrateNotSupport; + } + + return status; +} + +/*! + * brief Enable 9-bit data mode for LPUART. + * + * This function set the 9-bit mode for LPUART module. The 9th bit is not used for parity thus can be modified by user. + * + * param base LPUART peripheral base address. + * param enable true to enable, flase to disable. + */ +void LPUART_Enable9bitMode(LPUART_Type *base, bool enable) +{ + assert(base != NULL); + + uint32_t temp = 0U; + + if (enable) + { + /* Set LPUART_CTRL_M for 9-bit mode, clear LPUART_CTRL_PE to disable parity. */ + temp = base->CTRL & ~((uint32_t)LPUART_CTRL_PE_MASK | (uint32_t)LPUART_CTRL_M_MASK); + temp |= (uint32_t)LPUART_CTRL_M_MASK; + base->CTRL = temp; + } + else + { + /* Clear LPUART_CTRL_M. */ + base->CTRL &= ~(uint32_t)LPUART_CTRL_M_MASK; + } +#if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT + /* Clear LPUART_CTRL_M7 to disable 7-bit mode. */ + base->CTRL &= ~(uint32_t)LPUART_CTRL_M7_MASK; +#endif +#if defined(FSL_FEATURE_LPUART_HAS_10BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_10BIT_DATA_SUPPORT + /* Clear LPUART_BAUD_M10 to disable 10-bit mode. */ + base->BAUD &= ~(uint32_t)LPUART_BAUD_M10_MASK; +#endif +} + +/*! + * brief Transmit an address frame in 9-bit data mode. + * + * param base LPUART peripheral base address. + * param address LPUART slave address. + */ +void LPUART_SendAddress(LPUART_Type *base, uint8_t address) +{ + assert(base != NULL); + + uint32_t temp = base->DATA & 0xFFFFFC00UL; + temp |= ((uint32_t)address | (1UL << LPUART_DATA_R8T8_SHIFT)); + base->DATA = temp; +} + +/*! + * brief Enables LPUART interrupts according to a provided mask. + * + * This function enables the LPUART interrupts according to a provided mask. The mask + * is a logical OR of enumeration members. See the ref _lpuart_interrupt_enable. + * This examples shows how to enable TX empty interrupt and RX full interrupt: + * code + * LPUART_EnableInterrupts(LPUART1,kLPUART_TxDataRegEmptyInterruptEnable | kLPUART_RxDataRegFullInterruptEnable); + * endcode + * + * param base LPUART peripheral base address. + * param mask The interrupts to enable. Logical OR of ref _lpuart_interrupt_enable. + */ +void LPUART_EnableInterrupts(LPUART_Type *base, uint32_t mask) +{ + uint32_t s_atomicOldInt; + /* Only consider the real interrupt enable bits. */ + mask &= (uint32_t)kLPUART_AllInterruptEnable; + + /* Check int enable bits in base->BAUD */ + uint32_t baudRegMask = 0UL; +#if defined(FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT) && FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT + baudRegMask |= ((mask << 8U) & LPUART_BAUD_LBKDIE_MASK); + /* Clear bit 7 from mask */ + mask &= ~(uint32_t)kLPUART_LinBreakInterruptEnable; +#endif + baudRegMask |= ((mask << 8U) & LPUART_BAUD_RXEDGIE_MASK); + /* Clear bit 6 from mask */ + mask &= ~(uint32_t)kLPUART_RxActiveEdgeInterruptEnable; + + s_atomicOldInt = DisableGlobalIRQ(); + base->BAUD |= baudRegMask; + EnableGlobalIRQ(s_atomicOldInt); + +#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO + /* Check int enable bits in base->FIFO */ + + s_atomicOldInt = DisableGlobalIRQ(); + base->FIFO = (base->FIFO & ~(LPUART_FIFO_TXOF_MASK | LPUART_FIFO_RXUF_MASK)) | + (mask & (LPUART_FIFO_TXOFE_MASK | LPUART_FIFO_RXUFE_MASK)); + EnableGlobalIRQ(s_atomicOldInt); + + /* Clear bit 9 and bit 8 from mask */ + mask &= ~((uint32_t)kLPUART_TxFifoOverflowInterruptEnable | (uint32_t)kLPUART_RxFifoUnderflowInterruptEnable); +#endif + + /* Set int enable bits in base->CTRL */ + s_atomicOldInt = DisableGlobalIRQ(); + base->CTRL |= mask; + EnableGlobalIRQ(s_atomicOldInt); +} + +/*! + * brief Disables LPUART interrupts according to a provided mask. + * + * This function disables the LPUART interrupts according to a provided mask. The mask + * is a logical OR of enumeration members. See ref _lpuart_interrupt_enable. + * This example shows how to disable the TX empty interrupt and RX full interrupt: + * code + * LPUART_DisableInterrupts(LPUART1,kLPUART_TxDataRegEmptyInterruptEnable | kLPUART_RxDataRegFullInterruptEnable); + * endcode + * + * param base LPUART peripheral base address. + * param mask The interrupts to disable. Logical OR of ref _lpuart_interrupt_enable. + */ +void LPUART_DisableInterrupts(LPUART_Type *base, uint32_t mask) +{ + uint32_t s_atomicOldInt; + /* Only consider the real interrupt enable bits. */ + mask &= (uint32_t)kLPUART_AllInterruptEnable; + + /* Clear int enable bits in base->BAUD */ + uint32_t baudRegMask = 0UL; +#if defined(FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT) && FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT + baudRegMask |= ((mask << 8U) & LPUART_BAUD_LBKDIE_MASK); + /* Clear bit 7 from mask */ + mask &= ~(uint32_t)kLPUART_LinBreakInterruptEnable; +#endif + baudRegMask |= ((mask << 8U) & LPUART_BAUD_RXEDGIE_MASK); + /* Clear bit 6 from mask */ + mask &= ~(uint32_t)kLPUART_RxActiveEdgeInterruptEnable; + + s_atomicOldInt = DisableGlobalIRQ(); + base->BAUD &= ~baudRegMask; + EnableGlobalIRQ(s_atomicOldInt); + +#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO + /* Clear int enable bits in base->FIFO */ + + s_atomicOldInt = DisableGlobalIRQ(); + base->FIFO = (base->FIFO & ~(LPUART_FIFO_TXOF_MASK | LPUART_FIFO_RXUF_MASK)) & + ~(mask & (LPUART_FIFO_TXOFE_MASK | LPUART_FIFO_RXUFE_MASK)); + EnableGlobalIRQ(s_atomicOldInt); + /* Clear bit 9 and bit 8 from mask */ + mask &= ~((uint32_t)kLPUART_TxFifoOverflowInterruptEnable | (uint32_t)kLPUART_RxFifoUnderflowInterruptEnable); +#endif + + /* Clear int enable bits in base->CTRL */ + s_atomicOldInt = DisableGlobalIRQ(); + base->CTRL &= ~mask; + EnableGlobalIRQ(s_atomicOldInt); +} + +/*! + * brief Gets enabled LPUART interrupts. + * + * This function gets the enabled LPUART interrupts. The enabled interrupts are returned + * as the logical OR value of the enumerators ref _lpuart_interrupt_enable. To check + * a specific interrupt enable status, compare the return value with enumerators + * in ref _lpuart_interrupt_enable. + * For example, to check whether the TX empty interrupt is enabled: + * code + * uint32_t enabledInterrupts = LPUART_GetEnabledInterrupts(LPUART1); + * + * if (kLPUART_TxDataRegEmptyInterruptEnable & enabledInterrupts) + * { + * ... + * } + * endcode + * + * param base LPUART peripheral base address. + * return LPUART interrupt flags which are logical OR of the enumerators in ref _lpuart_interrupt_enable. + */ +uint32_t LPUART_GetEnabledInterrupts(LPUART_Type *base) +{ + /* Check int enable bits in base->CTRL */ + uint32_t temp = (uint32_t)(base->CTRL & (uint32_t)kLPUART_AllInterruptEnable); + + /* Check int enable bits in base->BAUD */ + temp = (temp & ~(uint32_t)kLPUART_RxActiveEdgeInterruptEnable) | ((base->BAUD & LPUART_BAUD_RXEDGIE_MASK) >> 8U); +#if defined(FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT) && FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT + temp = (temp & ~(uint32_t)kLPUART_LinBreakInterruptEnable) | ((base->BAUD & LPUART_BAUD_LBKDIE_MASK) >> 8U); +#endif + +#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO + /* Check int enable bits in base->FIFO */ + temp = + (temp & ~((uint32_t)kLPUART_TxFifoOverflowInterruptEnable | (uint32_t)kLPUART_RxFifoUnderflowInterruptEnable)) | + (base->FIFO & (LPUART_FIFO_TXOFE_MASK | LPUART_FIFO_RXUFE_MASK)); +#endif + + return temp; +} + +/*! + * brief Gets LPUART status flags. + * + * This function gets all LPUART status flags. The flags are returned as the logical + * OR value of the enumerators ref _lpuart_flags. To check for a specific status, + * compare the return value with enumerators in the ref _lpuart_flags. + * For example, to check whether the TX is empty: + * code + * if (kLPUART_TxDataRegEmptyFlag & LPUART_GetStatusFlags(LPUART1)) + * { + * ... + * } + * endcode + * + * param base LPUART peripheral base address. + * return LPUART status flags which are ORed by the enumerators in the _lpuart_flags. + */ +uint32_t LPUART_GetStatusFlags(LPUART_Type *base) +{ + uint32_t temp; + temp = base->STAT; +#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO + temp |= (base->FIFO & + (LPUART_FIFO_TXEMPT_MASK | LPUART_FIFO_RXEMPT_MASK | LPUART_FIFO_TXOF_MASK | LPUART_FIFO_RXUF_MASK)) >> + 16U; +#endif + /* Only keeps the status bits */ + temp &= (uint32_t)kLPUART_AllFlags; + return temp; +} + +/*! + * brief Clears status flags with a provided mask. + * + * This function clears LPUART status flags with a provided mask. Automatically cleared flags + * can't be cleared by this function. + * Flags that can only cleared or set by hardware are: + * kLPUART_TxDataRegEmptyFlag, kLPUART_TransmissionCompleteFlag, kLPUART_RxDataRegFullFlag, + * kLPUART_RxActiveFlag, kLPUART_NoiseErrorFlag, kLPUART_ParityErrorFlag, + * kLPUART_TxFifoEmptyFlag,kLPUART_RxFifoEmptyFlag + * Note: This API should be called when the Tx/Rx is idle, otherwise it takes no effects. + * + * param base LPUART peripheral base address. + * param mask the status flags to be cleared. The user can use the enumerators in the + * _lpuart_status_flag_t to do the OR operation and get the mask. + * return 0 succeed, others failed. + * retval kStatus_LPUART_FlagCannotClearManually The flag can't be cleared by this function but + * it is cleared automatically by hardware. + * retval kStatus_Success Status in the mask are cleared. + */ +status_t LPUART_ClearStatusFlags(LPUART_Type *base, uint32_t mask) +{ + uint32_t temp; + status_t status; + + /* Only deal with the clearable flags */ + mask &= (uint32_t)kLPUART_AllClearFlags; +#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO + /* Status bits in FIFO register */ + if ((mask & ((uint32_t)kLPUART_TxFifoOverflowFlag | (uint32_t)kLPUART_RxFifoUnderflowFlag)) != 0U) + { + /* Get the FIFO register value and mask the rx/tx FIFO flush bits and the status bits that can be W1C in case + they are written 1 accidentally. */ + temp = (uint32_t)base->FIFO; + temp &= (uint32_t)(~(LPUART_FIFO_TXFLUSH_MASK | LPUART_FIFO_RXFLUSH_MASK | LPUART_FIFO_TXOF_MASK | + LPUART_FIFO_RXUF_MASK)); + temp |= (mask << 16U) & (LPUART_FIFO_TXOF_MASK | LPUART_FIFO_RXUF_MASK); + base->FIFO = temp; + } +#endif + /* Status bits in STAT register */ + /* First get the STAT register value and mask all the bits that not represent status, then OR with the status bit + * that is to be W1C */ + temp = (base->STAT & 0x3E000000UL) | mask; + base->STAT = temp; + /* If some flags still pending. */ + if (0U != (mask & LPUART_GetStatusFlags(base))) + { + status = kStatus_LPUART_FlagCannotClearManually; + } + else + { + status = kStatus_Success; + } + + return status; +} + +/*! + * brief Writes to the transmitter register using a blocking method. + * + * This function polls the transmitter register, first waits for the register to be empty or TX FIFO to have room, + * and writes data to the transmitter buffer, then waits for the data to be sent out to bus. + * + * param base LPUART peripheral base address. + * param data Start address of the data to write. + * param length Size of the data to write. + * retval kStatus_LPUART_Timeout Transmission timed out and was aborted. + * retval kStatus_Success Successfully wrote all data. + */ +status_t LPUART_WriteBlocking(LPUART_Type *base, const uint8_t *data, size_t length) +{ + assert(NULL != data); + + const uint8_t *dataAddress = data; + size_t transferSize = length; + +#if UART_RETRY_TIMES + uint32_t waitTimes; +#endif + + while (0U != transferSize) + { +#if UART_RETRY_TIMES + waitTimes = UART_RETRY_TIMES; + while ((0U == (base->STAT & LPUART_STAT_TDRE_MASK)) && (0U != --waitTimes)) +#else + while (0U == (base->STAT & LPUART_STAT_TDRE_MASK)) +#endif + { + } +#if UART_RETRY_TIMES + if (0U == waitTimes) + { + return kStatus_LPUART_Timeout; + } +#endif + base->DATA = *(dataAddress); + dataAddress++; + transferSize--; + } + /* Ensure all the data in the transmit buffer are sent out to bus. */ +#if UART_RETRY_TIMES + waitTimes = UART_RETRY_TIMES; + while ((0U == (base->STAT & LPUART_STAT_TC_MASK)) && (0U != --waitTimes)) +#else + while (0U == (base->STAT & LPUART_STAT_TC_MASK)) +#endif + { + } +#if UART_RETRY_TIMES + if (0U == waitTimes) + { + return kStatus_LPUART_Timeout; + } +#endif + return kStatus_Success; +} +/*! + * brief Writes to the transmitter register using a blocking method in 9bit or 10bit mode. + * + * note This function only support 9bit or 10bit transfer. + * Please make sure only 10bit of data is valid and other bits are 0. + * + * param base LPUART peripheral base address. + * param data Start address of the data to write. + * param length Size of the data to write. + * retval kStatus_LPUART_Timeout Transmission timed out and was aborted. + * retval kStatus_Success Successfully wrote all data. + */ +status_t LPUART_WriteBlocking16bit(LPUART_Type *base, const uint16_t *data, size_t length) +{ + assert(NULL != data); + + const uint16_t *dataAddress = data; + size_t transferSize = length; + +#if UART_RETRY_TIMES + uint32_t waitTimes; +#endif + + while (0U != transferSize) + { +#if UART_RETRY_TIMES + waitTimes = UART_RETRY_TIMES; + while ((0U == (base->STAT & LPUART_STAT_TDRE_MASK)) && (0U != --waitTimes)) +#else + while (0U == (base->STAT & LPUART_STAT_TDRE_MASK)) +#endif + { + } +#if UART_RETRY_TIMES + if (0U == waitTimes) + { + return kStatus_LPUART_Timeout; + } +#endif + base->DATA = *(dataAddress); + dataAddress++; + transferSize--; + } + /* Ensure all the data in the transmit buffer are sent out to bus. */ +#if UART_RETRY_TIMES + waitTimes = UART_RETRY_TIMES; + while ((0U == (base->STAT & LPUART_STAT_TC_MASK)) && (0U != --waitTimes)) +#else + while (0U == (base->STAT & LPUART_STAT_TC_MASK)) +#endif + { + } +#if UART_RETRY_TIMES + if (0U == waitTimes) + { + return kStatus_LPUART_Timeout; + } +#endif + return kStatus_Success; +} + +/*! + * brief Reads the receiver data register using a blocking method. + * + * This function polls the receiver register, waits for the receiver register full or receiver FIFO + * has data, and reads data from the TX register. + * + * param base LPUART peripheral base address. + * param data Start address of the buffer to store the received data. + * param length Size of the buffer. + * retval kStatus_LPUART_RxHardwareOverrun Receiver overrun happened while receiving data. + * retval kStatus_LPUART_NoiseError Noise error happened while receiving data. + * retval kStatus_LPUART_FramingError Framing error happened while receiving data. + * retval kStatus_LPUART_ParityError Parity error happened while receiving data. + * retval kStatus_LPUART_Timeout Transmission timed out and was aborted. + * retval kStatus_Success Successfully received all data. + */ +status_t LPUART_ReadBlocking(LPUART_Type *base, uint8_t *data, size_t length) +{ + assert(NULL != data); + + status_t status = kStatus_Success; + uint32_t statusFlag; + uint8_t *dataAddress = data; + +#if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT + uint32_t ctrl = base->CTRL; + bool isSevenDataBits = (((ctrl & LPUART_CTRL_M7_MASK) != 0U) || + (((ctrl & LPUART_CTRL_M_MASK) == 0U) && ((ctrl & LPUART_CTRL_PE_MASK) != 0U))); +#endif + +#if UART_RETRY_TIMES + uint32_t waitTimes; +#endif + + while (0U != (length--)) + { +#if UART_RETRY_TIMES + waitTimes = UART_RETRY_TIMES; +#endif +#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO + while (0U == ((base->WATER & LPUART_WATER_RXCOUNT_MASK) >> LPUART_WATER_RXCOUNT_SHIFT)) +#else + while (0U == (base->STAT & LPUART_STAT_RDRF_MASK)) +#endif + { +#if UART_RETRY_TIMES + if (0U == --waitTimes) + { + status = kStatus_LPUART_Timeout; + break; + } +#endif + statusFlag = LPUART_GetStatusFlags(base); + + if (0U != (statusFlag & (uint32_t)kLPUART_RxOverrunFlag)) + { + /* + * $Branch Coverage Justification$ + * $ref fsl_lpuart_c_ref_2$. + */ + status = ((kStatus_Success == LPUART_ClearStatusFlags(base, (uint32_t)kLPUART_RxOverrunFlag)) ? + (kStatus_LPUART_RxHardwareOverrun) : + (kStatus_LPUART_FlagCannotClearManually)); + /* Other error flags(FE, NF, and PF) are prevented from setting once OR is set, no need to check other + * error flags*/ + break; + } + + if (0U != (statusFlag & (uint32_t)kLPUART_ParityErrorFlag)) + { + /* + * $Branch Coverage Justification$ + * $ref fsl_lpuart_c_ref_2$. + */ + status = ((kStatus_Success == LPUART_ClearStatusFlags(base, (uint32_t)kLPUART_ParityErrorFlag)) ? + (kStatus_LPUART_ParityError) : + (kStatus_LPUART_FlagCannotClearManually)); + } + + if (0U != (statusFlag & (uint32_t)kLPUART_FramingErrorFlag)) + { + /* + * $Branch Coverage Justification$ + * $ref fsl_lpuart_c_ref_2$. + */ + status = ((kStatus_Success == LPUART_ClearStatusFlags(base, (uint32_t)kLPUART_FramingErrorFlag)) ? + (kStatus_LPUART_FramingError) : + (kStatus_LPUART_FlagCannotClearManually)); + } + + if (0U != (statusFlag & (uint32_t)kLPUART_NoiseErrorFlag)) + { + /* + * $Branch Coverage Justification$ + * $ref fsl_lpuart_c_ref_2$. + */ + status = ((kStatus_Success == LPUART_ClearStatusFlags(base, (uint32_t)kLPUART_NoiseErrorFlag)) ? + (kStatus_LPUART_NoiseError) : + (kStatus_LPUART_FlagCannotClearManually)); + } + if (kStatus_Success != status) + { + break; + } + } + + if (kStatus_Success == status) + { +#if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT + if (isSevenDataBits) + { + *(dataAddress) = (uint8_t)(base->DATA & 0x7FU); + dataAddress++; + } + else + { + *(dataAddress) = (uint8_t)base->DATA; + dataAddress++; + } +#else + *(dataAddress) = (uint8_t)base->DATA; + dataAddress++; +#endif + } + else + { + break; + } + } + + return status; +} +/*! + * brief Reads the receiver data register in 9bit or 10bit mode. + * + * note This function only support 9bit or 10bit transfer. + * + * param base LPUART peripheral base address. + * param data Start address of the buffer to store the received data by 16bit, only 10bit is valid. + * param length Size of the buffer. + * retval kStatus_LPUART_RxHardwareOverrun Receiver overrun happened while receiving data. + * retval kStatus_LPUART_NoiseError Noise error happened while receiving data. + * retval kStatus_LPUART_FramingError Framing error happened while receiving data. + * retval kStatus_LPUART_ParityError Parity error happened while receiving data. + * retval kStatus_LPUART_Timeout Transmission timed out and was aborted. + * retval kStatus_Success Successfully received all data. + */ +status_t LPUART_ReadBlocking16bit(LPUART_Type *base, uint16_t *data, size_t length) +{ + assert(NULL != data); + + status_t status = kStatus_Success; + uint32_t statusFlag; + uint16_t *dataAddress = data; + +#if UART_RETRY_TIMES + uint32_t waitTimes; +#endif + + while (0U != (length--)) + { +#if UART_RETRY_TIMES + waitTimes = UART_RETRY_TIMES; +#endif +#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO + while (0U == ((base->WATER & LPUART_WATER_RXCOUNT_MASK) >> LPUART_WATER_RXCOUNT_SHIFT)) +#else + while (0U == (base->STAT & LPUART_STAT_RDRF_MASK)) +#endif + { +#if UART_RETRY_TIMES + if (0U == --waitTimes) + { + status = kStatus_LPUART_Timeout; + break; + } +#endif + statusFlag = LPUART_GetStatusFlags(base); + + if (0U != (statusFlag & (uint32_t)kLPUART_RxOverrunFlag)) + { + /* + * $Branch Coverage Justification$ + * $ref fsl_lpuart_c_ref_2$. + */ + status = ((kStatus_Success == LPUART_ClearStatusFlags(base, (uint32_t)kLPUART_RxOverrunFlag)) ? + (kStatus_LPUART_RxHardwareOverrun) : + (kStatus_LPUART_FlagCannotClearManually)); + /* Other error flags(FE, NF, and PF) are prevented from setting once OR is set, no need to check other + * error flags*/ + break; + } + + if (0U != (statusFlag & (uint32_t)kLPUART_ParityErrorFlag)) + { + /* + * $Branch Coverage Justification$ + * $ref fsl_lpuart_c_ref_2$. + */ + status = ((kStatus_Success == LPUART_ClearStatusFlags(base, (uint32_t)kLPUART_ParityErrorFlag)) ? + (kStatus_LPUART_ParityError) : + (kStatus_LPUART_FlagCannotClearManually)); + } + + if (0U != (statusFlag & (uint32_t)kLPUART_FramingErrorFlag)) + { + /* + * $Branch Coverage Justification$ + * $ref fsl_lpuart_c_ref_2$. + */ + status = ((kStatus_Success == LPUART_ClearStatusFlags(base, (uint32_t)kLPUART_FramingErrorFlag)) ? + (kStatus_LPUART_FramingError) : + (kStatus_LPUART_FlagCannotClearManually)); + } + + if (0U != (statusFlag & (uint32_t)kLPUART_NoiseErrorFlag)) + { + /* + * $Branch Coverage Justification$ + * $ref fsl_lpuart_c_ref_2$. + */ + status = ((kStatus_Success == LPUART_ClearStatusFlags(base, (uint32_t)kLPUART_NoiseErrorFlag)) ? + (kStatus_LPUART_NoiseError) : + (kStatus_LPUART_FlagCannotClearManually)); + } + if (kStatus_Success != status) + { + break; + } + } + if (kStatus_Success == status) + { + *(dataAddress) = (uint16_t)(base->DATA & 0x03FFU); + dataAddress++; + } + else + { + break; + } + } + + return status; +} + +/*! + * brief Initializes the LPUART handle. + * + * This function initializes the LPUART handle, which can be used for other LPUART + * transactional APIs. Usually, for a specified LPUART instance, + * call this API once to get the initialized handle. + * + * The LPUART driver supports the "background" receiving, which means that user can set up + * an RX ring buffer optionally. Data received is stored into the ring buffer even when the + * user doesn't call the LPUART_TransferReceiveNonBlocking() API. If there is already data received + * in the ring buffer, the user can get the received data from the ring buffer directly. + * The ring buffer is disabled if passing NULL as p ringBuffer. + * + * param base LPUART peripheral base address. + * param handle LPUART handle pointer. + * param callback Callback function. + * param userData User data. + */ +void LPUART_TransferCreateHandle(LPUART_Type *base, + lpuart_handle_t *handle, + lpuart_transfer_callback_t callback, + void *userData) +{ + assert(NULL != handle); + + uint32_t instance; + +#if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT + uint32_t ctrl = base->CTRL; + bool isSevenDataBits = (((ctrl & LPUART_CTRL_M7_MASK) != 0U) || + (((ctrl & LPUART_CTRL_M_MASK) == 0U) && ((ctrl & LPUART_CTRL_PE_MASK) != 0U))); +#endif + + /* Zero the handle. */ + (void)memset(handle, 0, sizeof(lpuart_handle_t)); + + /* Set the TX/RX state. */ + handle->rxState = (uint8_t)kLPUART_RxIdle; + handle->txState = (uint8_t)kLPUART_TxIdle; + + /* Set the callback and user data. */ + handle->callback = callback; + handle->userData = userData; + +#if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT + /* Initial seven data bits flag */ + handle->isSevenDataBits = isSevenDataBits; +#endif + handle->is16bitData = false; + + /* Get instance from peripheral base address. */ + instance = LPUART_GetInstance(base); + + /* Save the handle in global variables to support the double weak mechanism. */ + s_lpuartHandle[instance] = handle; + + s_lpuartIsr[instance] = LPUART_TransferHandleIRQ; + +/* Enable interrupt in NVIC. */ +#if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ +#if defined(LPUART_RX_IRQS) + (void)EnableIRQ(s_lpuartRxIRQ[instance]); +#endif +#if defined(LPUART_TX_IRQS) + (void)EnableIRQ(s_lpuartTxIRQ[instance]); +#endif +#else +#if defined(LPUART_RX_TX_IRQS) + (void)EnableIRQ(s_lpuartIRQ[instance]); +#endif +#endif +} + +/*! + * brief Sets up the RX ring buffer. + * + * This function sets up the RX ring buffer to a specific UART handle. + * + * When the RX ring buffer is used, data received is stored into the ring buffer even when + * the user doesn't call the UART_TransferReceiveNonBlocking() API. If there is already data received + * in the ring buffer, the user can get the received data from the ring buffer directly. + * + * note When using RX ring buffer, one byte is reserved for internal use. In other + * words, if p ringBufferSize is 32, then only 31 bytes are used for saving data. + * + * param base LPUART peripheral base address. + * param handle LPUART handle pointer. + * param ringBuffer Start address of ring buffer for background receiving. Pass NULL to disable the ring buffer. + * param ringBufferSize size of the ring buffer. + */ +void LPUART_TransferStartRingBuffer(LPUART_Type *base, + lpuart_handle_t *handle, + uint8_t *ringBuffer, + size_t ringBufferSize) +{ + assert(NULL != handle); + assert(NULL != ringBuffer); + + /* Setup the ring buffer address */ + handle->rxRingBuffer = ringBuffer; + if (!handle->is16bitData) + { + handle->rxRingBufferSize = ringBufferSize; + } + else + { + handle->rxRingBufferSize = ringBufferSize / 2U; + } + handle->rxRingBufferHead = 0U; + handle->rxRingBufferTail = 0U; + + /* Disable and re-enable the global interrupt to protect the interrupt enable register during read-modify-wrte. */ + uint32_t irqMask = DisableGlobalIRQ(); + /* Enable the interrupt to accept the data when user need the ring buffer. */ + base->CTRL |= (uint32_t)(LPUART_CTRL_RIE_MASK | LPUART_CTRL_ORIE_MASK); + EnableGlobalIRQ(irqMask); +} + +/*! + * brief Aborts the background transfer and uninstalls the ring buffer. + * + * This function aborts the background transfer and uninstalls the ring buffer. + * + * param base LPUART peripheral base address. + * param handle LPUART handle pointer. + */ +void LPUART_TransferStopRingBuffer(LPUART_Type *base, lpuart_handle_t *handle) +{ + assert(NULL != handle); + + if (handle->rxState == (uint8_t)kLPUART_RxIdle) + { + /* Disable and re-enable the global interrupt to protect the interrupt enable register during read-modify-wrte. + */ + uint32_t irqMask = DisableGlobalIRQ(); + base->CTRL &= ~(uint32_t)(LPUART_CTRL_RIE_MASK | LPUART_CTRL_ORIE_MASK); + EnableGlobalIRQ(irqMask); + } + + handle->rxRingBuffer = NULL; + handle->rxRingBufferSize = 0U; + handle->rxRingBufferHead = 0U; + handle->rxRingBufferTail = 0U; +} + +/*! + * brief Transmits a buffer of data using the interrupt method. + * + * This function send data using an interrupt method. This is a non-blocking function, which + * returns directly without waiting for all data written to the transmitter register. When + * all data is written to the TX register in the ISR, the LPUART driver calls the callback + * function and passes the ref kStatus_LPUART_TxIdle as status parameter. + * + * note The kStatus_LPUART_TxIdle is passed to the upper layer when all data are written + * to the TX register. However, there is no check to ensure that all the data sent out. Before disabling the TX, + * check the kLPUART_TransmissionCompleteFlag to ensure that the transmit is finished. + * + * param base LPUART peripheral base address. + * param handle LPUART handle pointer. + * param xfer LPUART transfer structure, see #lpuart_transfer_t. + * retval kStatus_Success Successfully start the data transmission. + * retval kStatus_LPUART_TxBusy Previous transmission still not finished, data not all written to the TX register. + * retval kStatus_InvalidArgument Invalid argument. + */ +status_t LPUART_TransferSendNonBlocking(LPUART_Type *base, lpuart_handle_t *handle, lpuart_transfer_t *xfer) +{ + assert(NULL != handle); + assert(NULL != xfer); + assert(NULL != xfer->txData); + assert(0U != xfer->dataSize); + + status_t status; + + /* Return error if current TX busy. */ + if ((uint8_t)kLPUART_TxBusy == handle->txState) + { + status = kStatus_LPUART_TxBusy; + } + else + { + if (!handle->is16bitData) + { + handle->txData = xfer->txData; + } + else + { + handle->txData16 = xfer->txData16; + } + handle->txDataSize = xfer->dataSize; + handle->txDataSizeAll = xfer->dataSize; + handle->txState = (uint8_t)kLPUART_TxBusy; + + /* Disable and re-enable the global interrupt to protect the interrupt enable register during read-modify-wrte. + */ + uint32_t irqMask = DisableGlobalIRQ(); + /* Enable transmitter interrupt. */ + base->CTRL |= (uint32_t)LPUART_CTRL_TIE_MASK; + EnableGlobalIRQ(irqMask); + + status = kStatus_Success; + } + + return status; +} + +/*! + * brief Aborts the interrupt-driven data transmit. + * + * This function aborts the interrupt driven data sending. The user can get the remainBtyes to find out + * how many bytes are not sent out. + * + * param base LPUART peripheral base address. + * param handle LPUART handle pointer. + */ +void LPUART_TransferAbortSend(LPUART_Type *base, lpuart_handle_t *handle) +{ + assert(NULL != handle); + + /* Disable and re-enable the global interrupt to protect the interrupt enable register during read-modify-wrte. */ + uint32_t irqMask = DisableGlobalIRQ(); + base->CTRL &= ~(uint32_t)(LPUART_CTRL_TIE_MASK | LPUART_CTRL_TCIE_MASK); + EnableGlobalIRQ(irqMask); + + handle->txDataSize = 0; + handle->txState = (uint8_t)kLPUART_TxIdle; +} + +/*! + * brief Gets the number of bytes that have been sent out to bus. + * + * This function gets the number of bytes that have been sent out to bus by an interrupt method. + * + * param base LPUART peripheral base address. + * param handle LPUART handle pointer. + * param count Send bytes count. + * retval kStatus_NoTransferInProgress No send in progress. + * retval kStatus_InvalidArgument Parameter is invalid. + * retval kStatus_Success Get successfully through the parameter \p count; + */ +status_t LPUART_TransferGetSendCount(LPUART_Type *base, lpuart_handle_t *handle, uint32_t *count) +{ + assert(NULL != handle); + assert(NULL != count); + + status_t status = kStatus_Success; + size_t tmptxDataSize = handle->txDataSize; + + if ((uint8_t)kLPUART_TxIdle == handle->txState) + { + status = kStatus_NoTransferInProgress; + } + else + { +#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO + *count = handle->txDataSizeAll - tmptxDataSize - + ((base->WATER & LPUART_WATER_TXCOUNT_MASK) >> LPUART_WATER_TXCOUNT_SHIFT); +#else + if ((base->STAT & (uint32_t)kLPUART_TxDataRegEmptyFlag) != 0U) + { + *count = handle->txDataSizeAll - tmptxDataSize; + } + else + { + *count = handle->txDataSizeAll - tmptxDataSize - 1U; + } +#endif + } + + return status; +} + +/*! + * brief Receives a buffer of data using the interrupt method. + * + * This function receives data using an interrupt method. This is a non-blocking function + * which returns without waiting to ensure that all data are received. + * If the RX ring buffer is used and not empty, the data in the ring buffer is copied and + * the parameter p receivedBytes shows how many bytes are copied from the ring buffer. + * After copying, if the data in the ring buffer is not enough for read, the receive + * request is saved by the LPUART driver. When the new data arrives, the receive request + * is serviced first. When all data is received, the LPUART driver notifies the upper layer + * through a callback function and passes a status parameter ref kStatus_UART_RxIdle. + * For example, the upper layer needs 10 bytes but there are only 5 bytes in ring buffer. + * The 5 bytes are copied to xfer->data, which returns with the + * parameter p receivedBytes set to 5. For the remaining 5 bytes, the newly arrived data is + * saved from xfer->data[5]. When 5 bytes are received, the LPUART driver notifies the upper layer. + * If the RX ring buffer is not enabled, this function enables the RX and RX interrupt + * to receive data to xfer->data. When all data is received, the upper layer is notified. + * + * param base LPUART peripheral base address. + * param handle LPUART handle pointer. + * param xfer LPUART transfer structure, see #uart_transfer_t. + * param receivedBytes Bytes received from the ring buffer directly. + * retval kStatus_Success Successfully queue the transfer into the transmit queue. + * retval kStatus_LPUART_RxBusy Previous receive request is not finished. + * retval kStatus_InvalidArgument Invalid argument. + */ +status_t LPUART_TransferReceiveNonBlocking(LPUART_Type *base, + lpuart_handle_t *handle, + lpuart_transfer_t *xfer, + size_t *receivedBytes) +{ + assert(NULL != handle); + assert(NULL != xfer); + assert(NULL != xfer->rxData); + assert(0U != xfer->dataSize); + + uint32_t i; + status_t status; + uint32_t irqMask; + /* How many bytes to copy from ring buffer to user memory. */ + size_t bytesToCopy = 0U; + /* How many bytes to receive. */ + size_t bytesToReceive; + /* How many bytes currently have received. */ + size_t bytesCurrentReceived; + + /* How to get data: + 1. If RX ring buffer is not enabled, then save xfer->data and xfer->dataSize + to lpuart handle, enable interrupt to store received data to xfer->data. When + all data received, trigger callback. + 2. If RX ring buffer is enabled and not empty, get data from ring buffer first. + If there are enough data in ring buffer, copy them to xfer->data and return. + If there are not enough data in ring buffer, copy all of them to xfer->data, + save the xfer->data remained empty space to lpuart handle, receive data + to this empty space and trigger callback when finished. */ + + if ((uint8_t)kLPUART_RxBusy == handle->rxState) + { + status = kStatus_LPUART_RxBusy; + } + else + { + bytesToReceive = xfer->dataSize; + bytesCurrentReceived = 0; + + /* If RX ring buffer is used. */ + if (NULL != handle->rxRingBuffer) + { + /* Disable and re-enable the global interrupt to protect the interrupt enable register during + * read-modify-wrte. */ + irqMask = DisableGlobalIRQ(); + /* Disable LPUART RX IRQ, protect ring buffer. */ + base->CTRL &= ~(uint32_t)(LPUART_CTRL_RIE_MASK | LPUART_CTRL_ORIE_MASK); + EnableGlobalIRQ(irqMask); + + /* How many bytes in RX ring buffer currently. */ + bytesToCopy = LPUART_TransferGetRxRingBufferLength(base, handle); + + if (0U != bytesToCopy) + { + bytesToCopy = MIN(bytesToReceive, bytesToCopy); + + bytesToReceive -= bytesToCopy; + + /* Copy data from ring buffer to user memory. */ + for (i = 0U; i < bytesToCopy; i++) + { + if (!handle->is16bitData) + { + xfer->rxData[bytesCurrentReceived] = handle->rxRingBuffer[handle->rxRingBufferTail]; + } + else + { + xfer->rxData16[bytesCurrentReceived] = handle->rxRingBuffer16[handle->rxRingBufferTail]; + } + bytesCurrentReceived++; + + /* Wrap to 0. Not use modulo (%) because it might be large and slow. */ + if (((uint32_t)handle->rxRingBufferTail + 1U) == handle->rxRingBufferSize) + { + handle->rxRingBufferTail = 0U; + } + else + { + handle->rxRingBufferTail++; + } + } + } + + /* If ring buffer does not have enough data, still need to read more data. */ + if (0U != bytesToReceive) + { + /* No data in ring buffer, save the request to LPUART handle. */ + + if (!handle->is16bitData) + { + handle->rxData = &xfer->rxData[bytesCurrentReceived]; + } + else + { + handle->rxData16 = &xfer->rxData16[bytesCurrentReceived]; + } + handle->rxDataSize = bytesToReceive; + handle->rxDataSizeAll = xfer->dataSize; + handle->rxState = (uint8_t)kLPUART_RxBusy; + } + + /* Disable and re-enable the global interrupt to protect the interrupt enable register during + * read-modify-wrte. */ + irqMask = DisableGlobalIRQ(); + /* Re-enable LPUART RX IRQ. */ + base->CTRL |= (uint32_t)(LPUART_CTRL_RIE_MASK | LPUART_CTRL_ORIE_MASK); + EnableGlobalIRQ(irqMask); + + /* Call user callback since all data are received. */ + if (0U == bytesToReceive) + { + if (NULL != handle->callback) + { + handle->callback(base, handle, kStatus_LPUART_RxIdle, handle->userData); + } + } + } + /* Ring buffer not used. */ + else + { + if (!handle->is16bitData) + { + handle->rxData = &xfer->rxData[bytesCurrentReceived]; + } + else + { + handle->rxData16 = &xfer->rxData16[bytesCurrentReceived]; + } + handle->rxDataSize = bytesToReceive; + handle->rxDataSizeAll = bytesToReceive; + handle->rxState = (uint8_t)kLPUART_RxBusy; + + /* Disable and re-enable the global interrupt to protect the interrupt enable register during + * read-modify-wrte. */ + irqMask = DisableGlobalIRQ(); + /* Enable RX interrupt. */ + base->CTRL |= (uint32_t)(LPUART_CTRL_RIE_MASK | LPUART_CTRL_ILIE_MASK | LPUART_CTRL_ORIE_MASK); + EnableGlobalIRQ(irqMask); + } + + /* Return the how many bytes have read. */ + if (NULL != receivedBytes) + { + *receivedBytes = bytesCurrentReceived; + } + + status = kStatus_Success; + } + + return status; +} + +/*! + * brief Aborts the interrupt-driven data receiving. + * + * This function aborts the interrupt-driven data receiving. The user can get the remainBytes to find out + * how many bytes not received yet. + * + * param base LPUART peripheral base address. + * param handle LPUART handle pointer. + */ +void LPUART_TransferAbortReceive(LPUART_Type *base, lpuart_handle_t *handle) +{ + assert(NULL != handle); + + /* Only abort the receive to handle->rxData, the RX ring buffer is still working. */ + if (NULL == handle->rxRingBuffer) + { + /* Disable and re-enable the global interrupt to protect the interrupt enable register during read-modify-wrte. + */ + uint32_t irqMask = DisableGlobalIRQ(); + /* Disable RX interrupt. */ + base->CTRL &= ~(uint32_t)(LPUART_CTRL_RIE_MASK | LPUART_CTRL_ILIE_MASK | LPUART_CTRL_ORIE_MASK); + EnableGlobalIRQ(irqMask); + } + + handle->rxDataSize = 0U; + handle->rxState = (uint8_t)kLPUART_RxIdle; +} + +/*! + * brief Gets the number of bytes that have been received. + * + * This function gets the number of bytes that have been received. + * + * param base LPUART peripheral base address. + * param handle LPUART handle pointer. + * param count Receive bytes count. + * retval kStatus_NoTransferInProgress No receive in progress. + * retval kStatus_InvalidArgument Parameter is invalid. + * retval kStatus_Success Get successfully through the parameter \p count; + */ +status_t LPUART_TransferGetReceiveCount(LPUART_Type *base, lpuart_handle_t *handle, uint32_t *count) +{ + assert(NULL != handle); + assert(NULL != count); + + status_t status = kStatus_Success; + size_t tmprxDataSize = handle->rxDataSize; + + if ((uint8_t)kLPUART_RxIdle == handle->rxState) + { + status = kStatus_NoTransferInProgress; + } + else + { + *count = handle->rxDataSizeAll - tmprxDataSize; + } + + return status; +} + +static void LPUART_TransferHandleIDLEReady(LPUART_Type *base, lpuart_handle_t *handle) +{ + uint32_t irqMask; +#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO + uint8_t count; + uint8_t tempCount; + count = ((uint8_t)((base->WATER & LPUART_WATER_RXCOUNT_MASK) >> LPUART_WATER_RXCOUNT_SHIFT)); + + while ((0U != handle->rxDataSize) && (0U != count)) + { + tempCount = (uint8_t)MIN(handle->rxDataSize, count); + /* Using non block API to read the data from the registers. */ + if (!handle->is16bitData) + { + LPUART_ReadNonBlocking(base, handle->rxData, tempCount); + handle->rxData = &handle->rxData[tempCount]; + } + else + { + LPUART_ReadNonBlocking16bit(base, handle->rxData16, tempCount); + handle->rxData16 = &handle->rxData16[tempCount]; + } + handle->rxDataSize -= tempCount; + count -= tempCount; + + /* If rxDataSize is 0, invoke rx idle callback.*/ + if (0U == (handle->rxDataSize)) + { + handle->rxState = (uint8_t)kLPUART_RxIdle; + + if (NULL != handle->callback) + { + handle->callback(base, handle, kStatus_LPUART_RxIdle, handle->userData); + } + } + } +#endif + /* Clear IDLE flag.*/ + base->STAT = ((base->STAT & 0x3FE00000U) | LPUART_STAT_IDLE_MASK); + + /* If rxDataSize is 0, disable rx ready, overrun and idle line interrupt.*/ + if (0U == handle->rxDataSize) + { + /* Disable and re-enable the global interrupt to protect the interrupt enable register during + * read-modify-wrte. */ + irqMask = DisableGlobalIRQ(); + base->CTRL &= ~(uint32_t)(LPUART_CTRL_RIE_MASK | LPUART_CTRL_ILIE_MASK | LPUART_CTRL_ORIE_MASK); + EnableGlobalIRQ(irqMask); + } + /* Invoke callback if callback is not NULL and rxDataSize is not 0. */ + else if (NULL != handle->callback) + { + handle->callback(base, handle, kStatus_LPUART_IdleLineDetected, handle->userData); + } + else + { + /* Avoid MISRA 15.7 */ + } +} + +static void LPUART_TransferHandleReceiveDataFull(LPUART_Type *base, lpuart_handle_t *handle) +{ + uint8_t count; + uint8_t tempCount; + uint16_t tpmRxRingBufferHead; + uint32_t tpmData; + uint32_t irqMask; + + /* Get the size that can be stored into buffer for this interrupt. */ +#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO + count = ((uint8_t)((base->WATER & LPUART_WATER_RXCOUNT_MASK) >> LPUART_WATER_RXCOUNT_SHIFT)); +#else + count = 1; +#endif + + /* If handle->rxDataSize is not 0, first save data to handle->rxData. */ + while ((0U != handle->rxDataSize) && (0U != count)) + { +#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO + tempCount = (uint8_t)MIN(handle->rxDataSize, count); +#else + tempCount = 1; +#endif + + /* Using non block API to read the data from the registers. */ + if (!handle->is16bitData) + { + LPUART_ReadNonBlocking(base, handle->rxData, tempCount); + handle->rxData = &handle->rxData[tempCount]; + } + else + { + LPUART_ReadNonBlocking16bit(base, handle->rxData16, tempCount); + handle->rxData16 = &handle->rxData16[tempCount]; + } + handle->rxDataSize -= tempCount; + count -= tempCount; + + /* If all the data required for upper layer is ready, trigger callback. */ + if (0U == handle->rxDataSize) + { + handle->rxState = (uint8_t)kLPUART_RxIdle; + + if (NULL != handle->callback) + { + handle->callback(base, handle, kStatus_LPUART_RxIdle, handle->userData); + } + } + } + + /* If use RX ring buffer, receive data to ring buffer. */ + if (NULL != handle->rxRingBuffer) + { + while (0U != count) + { + count--; + /* If RX ring buffer is full, trigger callback to notify over run. */ + if (LPUART_TransferIsRxRingBufferFull(base, handle)) + { + if (NULL != handle->callback) + { + handle->callback(base, handle, kStatus_LPUART_RxRingBufferOverrun, handle->userData); + } + } + + /* If ring buffer is still full after callback function, the oldest data is overridden. */ + if (LPUART_TransferIsRxRingBufferFull(base, handle)) + { + /* Increase handle->rxRingBufferTail to make room for new data. */ + if (((uint32_t)handle->rxRingBufferTail + 1U) == handle->rxRingBufferSize) + { + handle->rxRingBufferTail = 0U; + } + else + { + handle->rxRingBufferTail++; + } + } + + /* Read data. */ + tpmRxRingBufferHead = handle->rxRingBufferHead; + tpmData = base->DATA; +#if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT + if (handle->isSevenDataBits) + { + handle->rxRingBuffer[tpmRxRingBufferHead] = (uint8_t)(tpmData & 0x7FU); + } + else + { + if (!handle->is16bitData) + { + handle->rxRingBuffer[tpmRxRingBufferHead] = (uint8_t)tpmData; + } + else + { + handle->rxRingBuffer16[tpmRxRingBufferHead] = (uint16_t)(tpmData & 0x3FFU); + } + } +#else + if (!handle->is16bitData) + { + handle->rxRingBuffer[tpmRxRingBufferHead] = (uint8_t)tpmData; + } + else + { + handle->rxRingBuffer16[tpmRxRingBufferHead] = (uint16_t)(tpmData & 0x3FFU); + } +#endif + + /* Increase handle->rxRingBufferHead. */ + if (((uint32_t)handle->rxRingBufferHead + 1U) == handle->rxRingBufferSize) + { + handle->rxRingBufferHead = 0U; + } + else + { + handle->rxRingBufferHead++; + } + } + } + /* If no receive requst pending, stop RX interrupt. */ + else if (0U == handle->rxDataSize) + { + /* Disable and re-enable the global interrupt to protect the interrupt enable register during + * read-modify-wrte. */ + irqMask = DisableGlobalIRQ(); + base->CTRL &= ~(uint32_t)(LPUART_CTRL_RIE_MASK | LPUART_CTRL_ORIE_MASK | LPUART_CTRL_ILIE_MASK); + EnableGlobalIRQ(irqMask); + } + else + { + /* Avoid MISRA C-2012 15.7 voiation */ + return; + } +} + +static void LPUART_TransferHandleSendDataEmpty(LPUART_Type *base, lpuart_handle_t *handle) +{ + uint8_t count; + uint8_t tempCount; + uint32_t irqMask; +/* Get the bytes that available at this moment. */ +#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO + assert(FSL_FEATURE_LPUART_FIFO_SIZEn(base) > 0); + count = (uint8_t)FSL_FEATURE_LPUART_FIFO_SIZEn(base) - + (uint8_t)((base->WATER & LPUART_WATER_TXCOUNT_MASK) >> LPUART_WATER_TXCOUNT_SHIFT); +#else + count = 1; +#endif + + while ((0U != handle->txDataSize) && (0U != count)) + { +#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO + tempCount = (uint8_t)MIN(handle->txDataSize, count); +#else + tempCount = 1; +#endif + + /* Using non block API to write the data to the registers. */ + if (!handle->is16bitData) + { + LPUART_WriteNonBlocking(base, handle->txData, tempCount); + handle->txData = &handle->txData[tempCount]; + } + else + { + LPUART_WriteNonBlocking16bit(base, handle->txData16, tempCount); + handle->txData16 = &handle->txData16[tempCount]; + } + handle->txDataSize -= tempCount; + count -= tempCount; + + /* If all the data are written to data register, notify user with the callback, then TX finished. */ + if (0U == handle->txDataSize) + { + /* Disable and re-enable the global interrupt to protect the interrupt enable register during + * read-modify-wrte. */ + irqMask = DisableGlobalIRQ(); + /* Disable TX register empty interrupt and enable transmission completion interrupt. */ + base->CTRL = (base->CTRL & ~LPUART_CTRL_TIE_MASK) | LPUART_CTRL_TCIE_MASK; + EnableGlobalIRQ(irqMask); + } + } +} + +static void LPUART_TransferHandleTransmissionComplete(LPUART_Type *base, lpuart_handle_t *handle) +{ + uint32_t irqMask; + /* Set txState to idle only when all data has been sent out to bus. */ + handle->txState = (uint8_t)kLPUART_TxIdle; + + /* Disable and re-enable the global interrupt to protect the interrupt enable register during read-modify-wrte. + */ + irqMask = DisableGlobalIRQ(); + /* Disable transmission complete interrupt. */ + base->CTRL &= ~(uint32_t)LPUART_CTRL_TCIE_MASK; + EnableGlobalIRQ(irqMask); + + /* Trigger callback. */ + if (NULL != handle->callback) + { + handle->callback(base, handle, kStatus_LPUART_TxIdle, handle->userData); + } +} + +/*! + * brief LPUART IRQ handle function. + * + * This function handles the LPUART transmit and receive IRQ request. + * + * param base LPUART peripheral base address. + * param irqHandle LPUART handle pointer. + */ +void LPUART_TransferHandleIRQ(LPUART_Type *base, void *irqHandle) +{ + assert(NULL != irqHandle); + + uint32_t status = LPUART_GetStatusFlags(base); + uint32_t enabledInterrupts = LPUART_GetEnabledInterrupts(base); + + lpuart_handle_t *handle = (lpuart_handle_t *)irqHandle; + + /* If RX overrun. */ + if ((uint32_t)kLPUART_RxOverrunFlag == ((uint32_t)kLPUART_RxOverrunFlag & status)) + { + /* Clear overrun flag, otherwise the RX does not work. */ + base->STAT = ((base->STAT & 0x3FE00000U) | LPUART_STAT_OR_MASK); + + /* Trigger callback. */ + if (NULL != (handle->callback)) + { + handle->callback(base, handle, kStatus_LPUART_RxHardwareOverrun, handle->userData); + } + } + + /* If IDLE flag is set and the IDLE interrupt is enabled. */ + if ((0U != ((uint32_t)kLPUART_IdleLineFlag & status)) && + (0U != ((uint32_t)kLPUART_IdleLineInterruptEnable & enabledInterrupts))) + { + LPUART_TransferHandleIDLEReady(base, handle); + } + /* Receive data register full */ + if ((0U != ((uint32_t)kLPUART_RxDataRegFullFlag & status)) && + (0U != ((uint32_t)kLPUART_RxDataRegFullInterruptEnable & enabledInterrupts))) + { + LPUART_TransferHandleReceiveDataFull(base, handle); + } + + /* Send data register empty and the interrupt is enabled. */ + if ((0U != ((uint32_t)kLPUART_TxDataRegEmptyFlag & status)) && + (0U != ((uint32_t)kLPUART_TxDataRegEmptyInterruptEnable & enabledInterrupts))) + { + LPUART_TransferHandleSendDataEmpty(base, handle); + } + + /* Transmission complete and the interrupt is enabled. */ + if ((0U != ((uint32_t)kLPUART_TransmissionCompleteFlag & status)) && + (0U != ((uint32_t)kLPUART_TransmissionCompleteInterruptEnable & enabledInterrupts))) + { + LPUART_TransferHandleTransmissionComplete(base, handle); + } +} + +/*! + * brief LPUART Error IRQ handle function. + * + * This function handles the LPUART error IRQ request. + * + * param base LPUART peripheral base address. + * param irqHandle LPUART handle pointer. + */ +void LPUART_TransferHandleErrorIRQ(LPUART_Type *base, void *irqHandle) +{ + /* To be implemented by User. */ +} + +void LPUART_DriverIRQHandler(uint32_t instance) +{ + if (instance < ARRAY_SIZE(s_lpuartBases)) + { + s_lpuartIsr[instance](*(s_lpuartBases[instance]), s_lpuartHandle[instance]); + } + SDK_ISR_EXIT_BARRIER; +} + +#if defined(FSL_FEATURE_LPUART_HAS_SHARED_IRQ0_IRQ1) && FSL_FEATURE_LPUART_HAS_SHARED_IRQ0_IRQ1 +#if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ +void LPUART0_LPUART1_RX_DriverIRQHandler(void); +void LPUART0_LPUART1_RX_DriverIRQHandler(void) +{ + /* If handle is registered, treat the transfer function is enabled. */ + if (NULL != s_lpuartHandle[0]) + { + s_lpuartIsr[0](LPUART0, s_lpuartHandle[0]); + } + if (NULL != s_lpuartHandle[1]) + { + s_lpuartIsr[1](LPUART1, s_lpuartHandle[1]); + } + SDK_ISR_EXIT_BARRIER; +} +void LPUART0_LPUART1_TX_DriverIRQHandler(void); +void LPUART0_LPUART1_TX_DriverIRQHandler(void) +{ + /* If handle is registered, treat the transfer function is enabled. */ + if (NULL != s_lpuartHandle[0]) + { + s_lpuartIsr[0](LPUART0, s_lpuartHandle[0]); + } + if (NULL != s_lpuartHandle[1]) + { + s_lpuartIsr[1](LPUART1, s_lpuartHandle[1]); + } + SDK_ISR_EXIT_BARRIER; +} +#else +void LPUART0_LPUART1_DriverIRQHandler(void); +void LPUART0_LPUART1_DriverIRQHandler(void) +{ + /* If handle is registered, treat the transfer function is enabled. */ + if (NULL != s_lpuartHandle[0]) + { + s_lpuartIsr[0](LPUART0, s_lpuartHandle[0]); + } + if (NULL != s_lpuartHandle[1]) + { + s_lpuartIsr[1](LPUART1, s_lpuartHandle[1]); + } + SDK_ISR_EXIT_BARRIER; +} +#endif +#endif + +#if defined(LPUART0) +#if !(defined(FSL_FEATURE_LPUART_HAS_SHARED_IRQ0_IRQ1) && FSL_FEATURE_LPUART_HAS_SHARED_IRQ0_IRQ1) +#if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ +void LPUART0_TX_DriverIRQHandler(void); +void LPUART0_TX_DriverIRQHandler(void) +{ + s_lpuartIsr[0](LPUART0, s_lpuartHandle[0]); + SDK_ISR_EXIT_BARRIER; +} +void LPUART0_RX_DriverIRQHandler(void); +void LPUART0_RX_DriverIRQHandler(void) +{ + s_lpuartIsr[0](LPUART0, s_lpuartHandle[0]); + SDK_ISR_EXIT_BARRIER; +} +#else +void LPUART0_DriverIRQHandler(void); +void LPUART0_DriverIRQHandler(void) +{ + s_lpuartIsr[0](LPUART0, s_lpuartHandle[0]); + SDK_ISR_EXIT_BARRIER; +} +#endif +#endif +#endif + +#if defined(LPUART1) +#if !(defined(FSL_FEATURE_LPUART_HAS_SHARED_IRQ0_IRQ1) && FSL_FEATURE_LPUART_HAS_SHARED_IRQ0_IRQ1) +#if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ +void LPUART1_TX_DriverIRQHandler(void); +void LPUART1_TX_DriverIRQHandler(void) +{ + s_lpuartIsr[1](LPUART1, s_lpuartHandle[1]); + SDK_ISR_EXIT_BARRIER; +} +void LPUART1_RX_DriverIRQHandler(void); +void LPUART1_RX_DriverIRQHandler(void) +{ + s_lpuartIsr[1](LPUART1, s_lpuartHandle[1]); + SDK_ISR_EXIT_BARRIER; +} +#else +void LPUART1_DriverIRQHandler(void); +void LPUART1_DriverIRQHandler(void) +{ + s_lpuartIsr[1](LPUART1, s_lpuartHandle[1]); + SDK_ISR_EXIT_BARRIER; +} +#endif +#endif +#endif + +#if defined(LPUART2) +#if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ +void LPUART2_TX_DriverIRQHandler(void); +void LPUART2_TX_DriverIRQHandler(void) +{ + s_lpuartIsr[2](LPUART2, s_lpuartHandle[2]); + SDK_ISR_EXIT_BARRIER; +} +void LPUART2_RX_DriverIRQHandler(void); +void LPUART2_RX_DriverIRQHandler(void) +{ + s_lpuartIsr[2](LPUART2, s_lpuartHandle[2]); + SDK_ISR_EXIT_BARRIER; +} +#else +void LPUART2_DriverIRQHandler(void); +void LPUART2_DriverIRQHandler(void) +{ + s_lpuartIsr[2](LPUART2, s_lpuartHandle[2]); + SDK_ISR_EXIT_BARRIER; +} +#endif +#endif + +#if defined(LPUART3) +#if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ +void LPUART3_TX_DriverIRQHandler(void); +void LPUART3_TX_DriverIRQHandler(void) +{ + s_lpuartIsr[3](LPUART3, s_lpuartHandle[3]); + SDK_ISR_EXIT_BARRIER; +} +void LPUART3_RX_DriverIRQHandler(void); +void LPUART3_RX_DriverIRQHandler(void) +{ + s_lpuartIsr[3](LPUART3, s_lpuartHandle[3]); + SDK_ISR_EXIT_BARRIER; +} +#else +void LPUART3_DriverIRQHandler(void); +void LPUART3_DriverIRQHandler(void) +{ + s_lpuartIsr[3](LPUART3, s_lpuartHandle[3]); + SDK_ISR_EXIT_BARRIER; +} +#endif +#endif + +#if defined(LPUART4) +#if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ +void LPUART4_TX_DriverIRQHandler(void); +void LPUART4_TX_DriverIRQHandler(void) +{ + s_lpuartIsr[4](LPUART4, s_lpuartHandle[4]); + SDK_ISR_EXIT_BARRIER; +} +void LPUART4_RX_DriverIRQHandler(void); +void LPUART4_RX_DriverIRQHandler(void) +{ + s_lpuartIsr[4](LPUART4, s_lpuartHandle[4]); + SDK_ISR_EXIT_BARRIER; +} +#else +void LPUART4_DriverIRQHandler(void); +void LPUART4_DriverIRQHandler(void) +{ + s_lpuartIsr[4](LPUART4, s_lpuartHandle[4]); + SDK_ISR_EXIT_BARRIER; +} +#endif +#endif + +#if defined(LPUART5) +#if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ +void LPUART5_TX_DriverIRQHandler(void); +void LPUART5_TX_DriverIRQHandler(void) +{ + s_lpuartIsr[5](LPUART5, s_lpuartHandle[5]); + SDK_ISR_EXIT_BARRIER; +} +void LPUART5_RX_DriverIRQHandler(void); +void LPUART5_RX_DriverIRQHandler(void) +{ + s_lpuartIsr[5](LPUART5, s_lpuartHandle[5]); + SDK_ISR_EXIT_BARRIER; +} +#else +void LPUART5_DriverIRQHandler(void); +void LPUART5_DriverIRQHandler(void) +{ + s_lpuartIsr[5](LPUART5, s_lpuartHandle[5]); + SDK_ISR_EXIT_BARRIER; +} +#endif +#endif + +#if defined(LPUART6) +#if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ +void LPUART6_TX_DriverIRQHandler(void); +void LPUART6_TX_DriverIRQHandler(void) +{ + s_lpuartIsr[6](LPUART6, s_lpuartHandle[6]); + SDK_ISR_EXIT_BARRIER; +} +void LPUART6_RX_DriverIRQHandler(void); +void LPUART6_RX_DriverIRQHandler(void) +{ + s_lpuartIsr[6](LPUART6, s_lpuartHandle[6]); + SDK_ISR_EXIT_BARRIER; +} +#else +void LPUART6_DriverIRQHandler(void); +void LPUART6_DriverIRQHandler(void) +{ + s_lpuartIsr[6](LPUART6, s_lpuartHandle[6]); + SDK_ISR_EXIT_BARRIER; +} +#endif +#endif + +#if defined(LPUART7) +#if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ +void LPUART7_TX_DriverIRQHandler(void); +void LPUART7_TX_DriverIRQHandler(void) +{ + s_lpuartIsr[7](LPUART7, s_lpuartHandle[7]); + SDK_ISR_EXIT_BARRIER; +} +void LPUART7_RX_DriverIRQHandler(void); +void LPUART7_RX_DriverIRQHandler(void) +{ + s_lpuartIsr[7](LPUART7, s_lpuartHandle[7]); + SDK_ISR_EXIT_BARRIER; +} +#else +void LPUART7_DriverIRQHandler(void); +void LPUART7_DriverIRQHandler(void) +{ + s_lpuartIsr[7](LPUART7, s_lpuartHandle[7]); + SDK_ISR_EXIT_BARRIER; +} +#endif +#endif + +#if defined(LPUART8) +#if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ +void LPUART8_TX_DriverIRQHandler(void); +void LPUART8_TX_DriverIRQHandler(void) +{ + s_lpuartIsr[8](LPUART8, s_lpuartHandle[8]); + SDK_ISR_EXIT_BARRIER; +} +void LPUART8_RX_DriverIRQHandler(void); +void LPUART8_RX_DriverIRQHandler(void) +{ + s_lpuartIsr[8](LPUART8, s_lpuartHandle[8]); + SDK_ISR_EXIT_BARRIER; +} +#else +void LPUART8_DriverIRQHandler(void); +void LPUART8_DriverIRQHandler(void) +{ + s_lpuartIsr[8](LPUART8, s_lpuartHandle[8]); + SDK_ISR_EXIT_BARRIER; +} +#endif +#endif + +#if defined(LPUART9) +#if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ +void LPUART9_TX_DriverIRQHandler(void); +void LPUART9_TX_DriverIRQHandler(void) +{ + s_lpuartIsr[9](LPUART9, s_lpuartHandle[9]); + SDK_ISR_EXIT_BARRIER; +} +void LPUART9_RX_DriverIRQHandler(void); +void LPUART9_RX_DriverIRQHandler(void) +{ + s_lpuartIsr[9](LPUART9, s_lpuartHandle[9]); + SDK_ISR_EXIT_BARRIER; +} +#else +void LPUART9_DriverIRQHandler(void); +void LPUART9_DriverIRQHandler(void) +{ + s_lpuartIsr[9](LPUART9, s_lpuartHandle[9]); + SDK_ISR_EXIT_BARRIER; +} +#endif +#endif + +#if defined(LPUART10) +#if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ +void LPUART10_TX_DriverIRQHandler(void); +void LPUART10_TX_DriverIRQHandler(void) +{ + s_lpuartIsr[10](LPUART10, s_lpuartHandle[10]); + SDK_ISR_EXIT_BARRIER; +} +void LPUART10_RX_DriverIRQHandler(void); +void LPUART10_RX_DriverIRQHandler(void) +{ + s_lpuartIsr[10](LPUART10, s_lpuartHandle[10]); + SDK_ISR_EXIT_BARRIER; +} +#else +void LPUART10_DriverIRQHandler(void); +void LPUART10_DriverIRQHandler(void) +{ + s_lpuartIsr[10](LPUART10, s_lpuartHandle[10]); + SDK_ISR_EXIT_BARRIER; +} +#endif +#endif + +#if defined(LPUART11) +#if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ +void LPUART11_TX_DriverIRQHandler(void); +void LPUART11_TX_DriverIRQHandler(void) +{ + s_lpuartIsr[11](LPUART11, s_lpuartHandle[11]); + SDK_ISR_EXIT_BARRIER; +} +void LPUART11_RX_DriverIRQHandler(void); +void LPUART11_RX_DriverIRQHandler(void) +{ + s_lpuartIsr[11](LPUART11, s_lpuartHandle[11]); + SDK_ISR_EXIT_BARRIER; +} +#else +void LPUART11_DriverIRQHandler(void); +void LPUART11_DriverIRQHandler(void) +{ + s_lpuartIsr[11](LPUART11, s_lpuartHandle[11]); + SDK_ISR_EXIT_BARRIER; +} +#endif +#endif + +#if defined(LPUART12) +#if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ +void LPUART12_TX_DriverIRQHandler(void); +void LPUART12_TX_DriverIRQHandler(void) +{ + s_lpuartIsr[12](LPUART12, s_lpuartHandle[12]); + SDK_ISR_EXIT_BARRIER; +} +void LPUART12_RX_DriverIRQHandler(void); +void LPUART12_RX_DriverIRQHandler(void) +{ + s_lpuartIsr[12](LPUART12, s_lpuartHandle[12]); + SDK_ISR_EXIT_BARRIER; +} +#else +void LPUART12_DriverIRQHandler(void); +void LPUART12_DriverIRQHandler(void) +{ + s_lpuartIsr[12](LPUART12, s_lpuartHandle[12]); + SDK_ISR_EXIT_BARRIER; +} +#endif +#endif + +#if defined(CM4_0__LPUART) +void M4_0_LPUART_DriverIRQHandler(void); +void M4_0_LPUART_DriverIRQHandler(void) +{ + s_lpuartIsr[LPUART_GetInstance(CM4_0__LPUART)](CM4_0__LPUART, s_lpuartHandle[LPUART_GetInstance(CM4_0__LPUART)]); + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if defined(CM4_1__LPUART) +void M4_1_LPUART_DriverIRQHandler(void); +void M4_1_LPUART_DriverIRQHandler(void) +{ + s_lpuartIsr[LPUART_GetInstance(CM4_1__LPUART)](CM4_1__LPUART, s_lpuartHandle[LPUART_GetInstance(CM4_1__LPUART)]); + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if defined(CM4__LPUART) +void M4_LPUART_DriverIRQHandler(void); +void M4_LPUART_DriverIRQHandler(void) +{ + s_lpuartIsr[LPUART_GetInstance(CM4__LPUART)](CM4__LPUART, s_lpuartHandle[LPUART_GetInstance(CM4__LPUART)]); + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if defined(DMA__LPUART0) +void DMA_UART0_INT_DriverIRQHandler(void); +void DMA_UART0_INT_DriverIRQHandler(void) +{ + s_lpuartIsr[LPUART_GetInstance(DMA__LPUART0)](DMA__LPUART0, s_lpuartHandle[LPUART_GetInstance(DMA__LPUART0)]); + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if defined(DMA__LPUART1) +void DMA_UART1_INT_DriverIRQHandler(void); +void DMA_UART1_INT_DriverIRQHandler(void) +{ + s_lpuartIsr[LPUART_GetInstance(DMA__LPUART1)](DMA__LPUART1, s_lpuartHandle[LPUART_GetInstance(DMA__LPUART1)]); + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if defined(DMA__LPUART2) +void DMA_UART2_INT_DriverIRQHandler(void); +void DMA_UART2_INT_DriverIRQHandler(void) +{ + s_lpuartIsr[LPUART_GetInstance(DMA__LPUART2)](DMA__LPUART2, s_lpuartHandle[LPUART_GetInstance(DMA__LPUART2)]); + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if defined(DMA__LPUART3) +void DMA_UART3_INT_DriverIRQHandler(void); +void DMA_UART3_INT_DriverIRQHandler(void) +{ + s_lpuartIsr[LPUART_GetInstance(DMA__LPUART3)](DMA__LPUART3, s_lpuartHandle[LPUART_GetInstance(DMA__LPUART3)]); + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if defined(DMA__LPUART4) +void DMA_UART4_INT_DriverIRQHandler(void); +void DMA_UART4_INT_DriverIRQHandler(void) +{ + s_lpuartIsr[LPUART_GetInstance(DMA__LPUART4)](DMA__LPUART4, s_lpuartHandle[LPUART_GetInstance(DMA__LPUART4)]); + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if defined(ADMA__LPUART0) +void ADMA_UART0_INT_DriverIRQHandler(void); +void ADMA_UART0_INT_DriverIRQHandler(void) +{ + s_lpuartIsr[LPUART_GetInstance(ADMA__LPUART0)](ADMA__LPUART0, s_lpuartHandle[LPUART_GetInstance(ADMA__LPUART0)]); + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if defined(ADMA__LPUART1) +void ADMA_UART1_INT_DriverIRQHandler(void); +void ADMA_UART1_INT_DriverIRQHandler(void) +{ + s_lpuartIsr[LPUART_GetInstance(ADMA__LPUART1)](ADMA__LPUART1, s_lpuartHandle[LPUART_GetInstance(ADMA__LPUART1)]); + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if defined(ADMA__LPUART2) +void ADMA_UART2_INT_DriverIRQHandler(void); +void ADMA_UART2_INT_DriverIRQHandler(void) +{ + s_lpuartIsr[LPUART_GetInstance(ADMA__LPUART2)](ADMA__LPUART2, s_lpuartHandle[LPUART_GetInstance(ADMA__LPUART2)]); + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if defined(ADMA__LPUART3) +void ADMA_UART3_INT_DriverIRQHandler(void); +void ADMA_UART3_INT_DriverIRQHandler(void) +{ + s_lpuartIsr[LPUART_GetInstance(ADMA__LPUART3)](ADMA__LPUART3, s_lpuartHandle[LPUART_GetInstance(ADMA__LPUART3)]); + SDK_ISR_EXIT_BARRIER; +} +#endif diff --git a/bsp/nxp/imx/imx91/drivers/sdk/drivers/lpuart/fsl_lpuart.h b/bsp/nxp/imx/imx91/drivers/sdk/drivers/lpuart/fsl_lpuart.h new file mode 100644 index 00000000000..9bf98b000e7 --- /dev/null +++ b/bsp/nxp/imx/imx91/drivers/sdk/drivers/lpuart/fsl_lpuart.h @@ -0,0 +1,1150 @@ +/* + * Copyright (c) 2015-2016, Freescale Semiconductor, Inc. + * Copyright 2016-2025 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef FSL_LPUART_H_ +#define FSL_LPUART_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup lpuart_driver + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*! @{ */ +/*! @brief LPUART driver version. */ +#define FSL_LPUART_DRIVER_VERSION (MAKE_VERSION(2, 9, 1)) +/*! @} */ + +/*! @brief Retry times for waiting flag. */ +#ifndef UART_RETRY_TIMES +#define UART_RETRY_TIMES 0U /* Defining to zero means to keep waiting for the flag until it is assert/deassert. */ +#endif + +/*! @brief Error codes for the LPUART driver. */ +enum +{ + kStatus_LPUART_TxBusy = MAKE_STATUS(kStatusGroup_LPUART, 0), /*!< TX busy */ + kStatus_LPUART_RxBusy = MAKE_STATUS(kStatusGroup_LPUART, 1), /*!< RX busy */ + kStatus_LPUART_TxIdle = MAKE_STATUS(kStatusGroup_LPUART, 2), /*!< LPUART transmitter is idle. */ + kStatus_LPUART_RxIdle = MAKE_STATUS(kStatusGroup_LPUART, 3), /*!< LPUART receiver is idle. */ + kStatus_LPUART_TxWatermarkTooLarge = MAKE_STATUS(kStatusGroup_LPUART, 4), /*!< TX FIFO watermark too large */ + kStatus_LPUART_RxWatermarkTooLarge = MAKE_STATUS(kStatusGroup_LPUART, 5), /*!< RX FIFO watermark too large */ + kStatus_LPUART_FlagCannotClearManually = MAKE_STATUS(kStatusGroup_LPUART, 6), /*!< Some flag can't manually clear */ + kStatus_LPUART_Error = MAKE_STATUS(kStatusGroup_LPUART, 7), /*!< Error happens on LPUART. */ + kStatus_LPUART_RxRingBufferOverrun = + MAKE_STATUS(kStatusGroup_LPUART, 8), /*!< LPUART RX software ring buffer overrun. */ + kStatus_LPUART_RxHardwareOverrun = MAKE_STATUS(kStatusGroup_LPUART, 9), /*!< LPUART RX receiver overrun. */ + kStatus_LPUART_NoiseError = MAKE_STATUS(kStatusGroup_LPUART, 10), /*!< LPUART noise error. */ + kStatus_LPUART_FramingError = MAKE_STATUS(kStatusGroup_LPUART, 11), /*!< LPUART framing error. */ + kStatus_LPUART_ParityError = MAKE_STATUS(kStatusGroup_LPUART, 12), /*!< LPUART parity error. */ + kStatus_LPUART_BaudrateNotSupport = + MAKE_STATUS(kStatusGroup_LPUART, 13), /*!< Baudrate is not support in current clock source */ + kStatus_LPUART_IdleLineDetected = MAKE_STATUS(kStatusGroup_LPUART, 14), /*!< IDLE flag. */ + kStatus_LPUART_Timeout = MAKE_STATUS(kStatusGroup_LPUART, 15), /*!< LPUART times out. */ +}; + +/*! @brief LPUART parity mode. */ +typedef enum _lpuart_parity_mode +{ + kLPUART_ParityDisabled = 0x0U, /*!< Parity disabled */ + kLPUART_ParityEven = 0x2U, /*!< Parity enabled, type even, bit setting: PE|PT = 10 */ + kLPUART_ParityOdd = 0x3U, /*!< Parity enabled, type odd, bit setting: PE|PT = 11 */ +} lpuart_parity_mode_t; + +/*! @brief LPUART data bits count. */ +typedef enum _lpuart_data_bits +{ + kLPUART_EightDataBits = 0x0U, /*!< Eight data bit */ +#if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT + kLPUART_SevenDataBits = 0x1U, /*!< Seven data bit */ +#endif +} lpuart_data_bits_t; + +/*! @brief LPUART stop bit count. */ +typedef enum _lpuart_stop_bit_count +{ + kLPUART_OneStopBit = 0U, /*!< One stop bit */ + kLPUART_TwoStopBit = 1U, /*!< Two stop bits */ +} lpuart_stop_bit_count_t; + +#if defined(FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT) && FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT +/*! @brief LPUART transmit CTS source. */ +typedef enum _lpuart_transmit_cts_source +{ + kLPUART_CtsSourcePin = 0U, /*!< CTS resource is the LPUART_CTS pin. */ + kLPUART_CtsSourceMatchResult = 1U, /*!< CTS resource is the match result. */ +} lpuart_transmit_cts_source_t; + +/*! @brief LPUART transmit CTS configure. */ +typedef enum _lpuart_transmit_cts_config +{ + kLPUART_CtsSampleAtStart = 0U, /*!< CTS input is sampled at the start of each character. */ + kLPUART_CtsSampleAtIdle = 1U, /*!< CTS input is sampled when the transmitter is idle */ +} lpuart_transmit_cts_config_t; +#endif + +/*! @brief LPUART idle flag type defines when the receiver starts counting. */ +typedef enum _lpuart_idle_type_select +{ + kLPUART_IdleTypeStartBit = 0U, /*!< Start counting after a valid start bit. */ + kLPUART_IdleTypeStopBit = 1U, /*!< Start counting after a stop bit. */ +} lpuart_idle_type_select_t; + +/*! @brief LPUART idle detected configuration. + * This structure defines the number of idle characters that must be received before + * the IDLE flag is set. + */ +typedef enum _lpuart_idle_config +{ + kLPUART_IdleCharacter1 = 0U, /*!< the number of idle characters. */ + kLPUART_IdleCharacter2 = 1U, /*!< the number of idle characters. */ + kLPUART_IdleCharacter4 = 2U, /*!< the number of idle characters. */ + kLPUART_IdleCharacter8 = 3U, /*!< the number of idle characters. */ + kLPUART_IdleCharacter16 = 4U, /*!< the number of idle characters. */ + kLPUART_IdleCharacter32 = 5U, /*!< the number of idle characters. */ + kLPUART_IdleCharacter64 = 6U, /*!< the number of idle characters. */ + kLPUART_IdleCharacter128 = 7U, /*!< the number of idle characters. */ +} lpuart_idle_config_t; + +/*! + * @brief LPUART interrupt configuration structure, default settings all disabled. + * + * This structure contains the settings for all LPUART interrupt configurations. + */ +enum _lpuart_interrupt_enable +{ +#if defined(FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT) && FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT + kLPUART_LinBreakInterruptEnable = (LPUART_BAUD_LBKDIE_MASK >> 8U), /*!< LIN break detect. bit 7 */ +#endif + kLPUART_RxActiveEdgeInterruptEnable = (LPUART_BAUD_RXEDGIE_MASK >> 8U), /*!< Receive Active Edge. bit 6 */ + kLPUART_TxDataRegEmptyInterruptEnable = (LPUART_CTRL_TIE_MASK), /*!< Transmit data register empty. bit 23 */ + kLPUART_TransmissionCompleteInterruptEnable = (LPUART_CTRL_TCIE_MASK), /*!< Transmission complete. bit 22 */ + kLPUART_RxDataRegFullInterruptEnable = (LPUART_CTRL_RIE_MASK), /*!< Receiver data register full. bit 21 */ + kLPUART_IdleLineInterruptEnable = (LPUART_CTRL_ILIE_MASK), /*!< Idle line. bit 20 */ + kLPUART_RxOverrunInterruptEnable = (LPUART_CTRL_ORIE_MASK), /*!< Receiver Overrun. bit 27 */ + kLPUART_NoiseErrorInterruptEnable = (LPUART_CTRL_NEIE_MASK), /*!< Noise error flag. bit 26 */ + kLPUART_FramingErrorInterruptEnable = (LPUART_CTRL_FEIE_MASK), /*!< Framing error flag. bit 25 */ + kLPUART_ParityErrorInterruptEnable = (LPUART_CTRL_PEIE_MASK), /*!< Parity error flag. bit 24 */ +#if defined(FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING) && FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING + kLPUART_Match1InterruptEnable = (LPUART_CTRL_MA1IE_MASK), /*!< Parity error flag. bit 15 */ + kLPUART_Match2InterruptEnable = (LPUART_CTRL_MA2IE_MASK), /*!< Parity error flag. bit 14 */ +#endif +#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO + kLPUART_TxFifoOverflowInterruptEnable = (LPUART_FIFO_TXOFE_MASK), /*!< Transmit FIFO Overflow. bit 9 */ + kLPUART_RxFifoUnderflowInterruptEnable = (LPUART_FIFO_RXUFE_MASK), /*!< Receive FIFO Underflow. bit 8 */ +#endif + + kLPUART_AllInterruptEnable = kLPUART_RxActiveEdgeInterruptEnable | kLPUART_TxDataRegEmptyInterruptEnable | + kLPUART_TransmissionCompleteInterruptEnable | kLPUART_RxDataRegFullInterruptEnable | + kLPUART_IdleLineInterruptEnable | kLPUART_RxOverrunInterruptEnable | + kLPUART_NoiseErrorInterruptEnable | kLPUART_FramingErrorInterruptEnable | + kLPUART_ParityErrorInterruptEnable +#if defined(FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT) && FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT + | kLPUART_LinBreakInterruptEnable +#endif +#if defined(FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING) && FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING + | kLPUART_Match1InterruptEnable | kLPUART_Match2InterruptEnable +#endif +#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO + | kLPUART_TxFifoOverflowInterruptEnable | kLPUART_RxFifoUnderflowInterruptEnable +#endif + , +}; + +/*! + * @brief LPUART status flags. + * + * This provides constants for the LPUART status flags for use in the LPUART functions. + */ +enum _lpuart_flags +{ + kLPUART_TxDataRegEmptyFlag = + (LPUART_STAT_TDRE_MASK), /*!< Transmit data register empty flag, sets when transmit buffer is empty. bit 23 */ + kLPUART_TransmissionCompleteFlag = + (LPUART_STAT_TC_MASK), /*!< Transmission complete flag, sets when transmission activity complete. bit 22 */ + kLPUART_RxDataRegFullFlag = (LPUART_STAT_RDRF_MASK), /*!< Receive data register full flag, sets when the receive + data buffer is full. bit 21 */ + kLPUART_IdleLineFlag = (LPUART_STAT_IDLE_MASK), /*!< Idle line detect flag, sets when idle line detected. bit 20 */ + kLPUART_RxOverrunFlag = (LPUART_STAT_OR_MASK), /*!< Receive Overrun, sets when new data is received before data is + read from receive register. bit 19 */ + kLPUART_NoiseErrorFlag = (LPUART_STAT_NF_MASK), /*!< Receive takes 3 samples of each received bit. If any of these + samples differ, noise flag sets. bit 18 */ + kLPUART_FramingErrorFlag = + (LPUART_STAT_FE_MASK), /*!< Frame error flag, sets if logic 0 was detected where stop bit expected. bit 17 */ + kLPUART_ParityErrorFlag = (LPUART_STAT_PF_MASK), /*!< If parity enabled, sets upon parity error detection. bit 16 */ +#if defined(FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT) && FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT + kLPUART_LinBreakFlag = (LPUART_STAT_LBKDIF_MASK), /*!< LIN break detect interrupt flag, sets when LIN break + char detected and LIN circuit enabled. bit 31 */ +#endif + kLPUART_RxActiveEdgeFlag = (LPUART_STAT_RXEDGIF_MASK), /*!< Receive pin active edge interrupt flag, sets when active + edge detected. bit 30 */ + kLPUART_RxActiveFlag = + (LPUART_STAT_RAF_MASK), /*!< Receiver Active Flag (RAF), sets at beginning of valid start. bit 24 */ +#if defined(FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING) && FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING + kLPUART_DataMatch1Flag = + LPUART_STAT_MA1F_MASK, /*!< The next character to be read from LPUART_DATA matches MA1. bit 15 */ + kLPUART_DataMatch2Flag = + LPUART_STAT_MA2F_MASK, /*!< The next character to be read from LPUART_DATA matches MA2. bit 14 */ +#endif +#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO + kLPUART_TxFifoEmptyFlag = + (LPUART_FIFO_TXEMPT_MASK >> 16), /*!< TXEMPT bit, sets if transmit buffer is empty. bit 7 */ + kLPUART_RxFifoEmptyFlag = + (LPUART_FIFO_RXEMPT_MASK >> 16), /*!< RXEMPT bit, sets if receive buffer is empty. bit 6 */ + kLPUART_TxFifoOverflowFlag = + (LPUART_FIFO_TXOF_MASK >> 16), /*!< TXOF bit, sets if transmit buffer overflow occurred. bit 1 */ + kLPUART_RxFifoUnderflowFlag = + (LPUART_FIFO_RXUF_MASK >> 16), /*!< RXUF bit, sets if receive buffer underflow occurred. bit 0 */ +#endif + + kLPUART_AllClearFlags = kLPUART_RxActiveEdgeFlag | kLPUART_IdleLineFlag | kLPUART_RxOverrunFlag | + kLPUART_NoiseErrorFlag | kLPUART_FramingErrorFlag | kLPUART_ParityErrorFlag +#if defined(FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING) && FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING + | kLPUART_DataMatch1Flag | kLPUART_DataMatch2Flag +#endif +#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO + | kLPUART_TxFifoOverflowFlag | kLPUART_RxFifoUnderflowFlag +#endif +#if defined(FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT) && FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT + | kLPUART_LinBreakFlag +#endif + , + + kLPUART_AllFlags = + kLPUART_RxActiveEdgeFlag | kLPUART_IdleLineFlag | kLPUART_RxOverrunFlag | kLPUART_TxDataRegEmptyFlag | + kLPUART_TransmissionCompleteFlag | kLPUART_RxDataRegFullFlag | kLPUART_RxActiveFlag | kLPUART_NoiseErrorFlag | + kLPUART_FramingErrorFlag | kLPUART_ParityErrorFlag +#if defined(FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING) && FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING + | kLPUART_DataMatch1Flag | kLPUART_DataMatch2Flag +#endif +#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO + | kLPUART_TxFifoOverflowFlag | kLPUART_RxFifoUnderflowFlag | kLPUART_TxFifoEmptyFlag | kLPUART_RxFifoEmptyFlag +#endif +#if defined(FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT) && FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT + | kLPUART_LinBreakFlag +#endif + , +}; + +/*! @brief LPUART configuration structure. */ +typedef struct _lpuart_config +{ + uint32_t baudRate_Bps; /*!< LPUART baud rate */ + lpuart_parity_mode_t parityMode; /*!< Parity mode, disabled (default), even, odd */ + lpuart_data_bits_t dataBitsCount; /*!< Data bits count, eight (default), seven */ + bool isMsb; /*!< Data bits order, LSB (default), MSB */ +#if defined(FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT) && FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT + lpuart_stop_bit_count_t stopBitCount; /*!< Number of stop bits, 1 stop bit (default) or 2 stop bits */ +#endif +#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO + uint8_t txFifoWatermark; /*!< TX FIFO watermark */ + uint8_t rxFifoWatermark; /*!< RX FIFO watermark */ +#endif +#if defined(FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT) && FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT + bool enableRxRTS; /*!< RX RTS enable */ + bool enableTxCTS; /*!< TX CTS enable */ + lpuart_transmit_cts_source_t txCtsSource; /*!< TX CTS source */ + lpuart_transmit_cts_config_t txCtsConfig; /*!< TX CTS configure */ +#endif + lpuart_idle_type_select_t rxIdleType; /*!< RX IDLE type. */ + lpuart_idle_config_t rxIdleConfig; /*!< RX IDLE configuration. */ + bool enableTx; /*!< Enable TX */ + bool enableRx; /*!< Enable RX */ +#if defined(FSL_FEATURE_LPUART_HAS_CTRL_SWAP) && FSL_FEATURE_LPUART_HAS_CTRL_SWAP + bool swapTxdRxd; /*!< Swap TXD and RXD pins */ +#endif +} lpuart_config_t; + +/*! @brief LPUART transfer structure. */ +typedef struct _lpuart_transfer +{ + /* + * Use separate TX and RX data pointer, because TX data is const data. + * The member data is kept for backward compatibility. + */ + union + { + uint8_t *data; /*!< The buffer of data to be transfer.*/ + uint8_t *rxData; /*!< The buffer to receive data. */ + uint16_t *rxData16; /*!< The buffer to receive data. */ + const uint8_t *txData; /*!< The buffer of data to be sent. */ + const uint16_t *txData16; /*!< The buffer of data to be sent. */ + }; + size_t dataSize; /*!< The byte count to be transfer. */ +} lpuart_transfer_t; + +/* Forward declaration of the handle typedef. */ +typedef struct _lpuart_handle lpuart_handle_t; + +/*! @brief LPUART transfer callback function. */ +typedef void (*lpuart_transfer_callback_t)(LPUART_Type *base, lpuart_handle_t *handle, status_t status, void *userData); + +/*! @brief LPUART handle structure. */ +struct _lpuart_handle +{ + union + { + const uint8_t *volatile txData; /*!< Address of remaining data to send. */ + const uint16_t *volatile txData16; /*!< Address of remaining data to send. */ + }; + volatile size_t txDataSize; /*!< Size of the remaining data to send. */ + size_t txDataSizeAll; /*!< Size of the data to send out. */ + union + { + uint8_t *volatile rxData; /*!< Address of remaining data to receive. */ + uint16_t *volatile rxData16; /*!< Address of remaining data to receive. */ + }; + volatile size_t rxDataSize; /*!< Size of the remaining data to receive. */ + size_t rxDataSizeAll; /*!< Size of the data to receive. */ + + union + { + uint8_t *rxRingBuffer; /*!< Start address of the receiver ring buffer. */ + uint16_t *rxRingBuffer16; /*!< Start address of the receiver ring buffer. */ + }; + size_t rxRingBufferSize; /*!< Size of the ring buffer. */ + volatile uint16_t rxRingBufferHead; /*!< Index for the driver to store received data into ring buffer. */ + volatile uint16_t rxRingBufferTail; /*!< Index for the user to get data from the ring buffer. */ + + lpuart_transfer_callback_t callback; /*!< Callback function. */ + void *userData; /*!< LPUART callback function parameter.*/ + + volatile uint8_t txState; /*!< TX transfer state. */ + volatile uint8_t rxState; /*!< RX transfer state. */ + +#if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT + bool isSevenDataBits; /*!< Seven data bits flag. */ +#endif + bool is16bitData; /*!< 16bit data bits flag, only used for 9bit or 10bit data */ +}; + +/* Typedef for interrupt handler. */ +typedef void (*lpuart_isr_t)(LPUART_Type *base, void *handle); + +/******************************************************************************* + * Variables + ******************************************************************************/ +/* Array of LPUART handle. */ +extern void *s_lpuartHandle[]; + +/* Array of LPUART IRQ number. */ +#if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ +extern const IRQn_Type s_lpuartTxIRQ[]; +#else +extern const IRQn_Type s_lpuartIRQ[]; +#endif + +/* LPUART ISR for transactional APIs. */ +extern lpuart_isr_t s_lpuartIsr[]; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* _cplusplus */ + +#if defined(FSL_FEATURE_LPUART_HAS_GLOBAL) && FSL_FEATURE_LPUART_HAS_GLOBAL + +/*! + * @name Software Reset + * @{ + */ + +/*! + * @brief Resets the LPUART using software. + * + * This function resets all internal logic and registers except the Global Register. + * Remains set until cleared by software. + * + * @param base LPUART peripheral base address. + */ +static inline void LPUART_SoftwareReset(LPUART_Type *base) +{ + base->GLOBAL |= LPUART_GLOBAL_RST_MASK; + base->GLOBAL &= ~LPUART_GLOBAL_RST_MASK; +} +/*! @} */ +#endif /*FSL_FEATURE_LPUART_HAS_GLOBAL*/ + +/*! + * @name Initialization and deinitialization + * @{ + */ + +/*! + * @brief Initializes an LPUART instance with the user configuration structure and the peripheral clock. + * + * This function configures the LPUART module with user-defined settings. Call the LPUART_GetDefaultConfig() function + * to configure the configuration structure and get the default configuration. + * The example below shows how to use this API to configure the LPUART. + * @code + * lpuart_config_t lpuartConfig; + * lpuartConfig.baudRate_Bps = 115200U; + * lpuartConfig.parityMode = kLPUART_ParityDisabled; + * lpuartConfig.dataBitsCount = kLPUART_EightDataBits; + * lpuartConfig.isMsb = false; + * lpuartConfig.stopBitCount = kLPUART_OneStopBit; + * lpuartConfig.txFifoWatermark = 0; + * lpuartConfig.rxFifoWatermark = 1; + * LPUART_Init(LPUART1, &lpuartConfig, 20000000U); + * @endcode + * + * @param base LPUART peripheral base address. + * @param config Pointer to a user-defined configuration structure. + * @param srcClock_Hz LPUART clock source frequency in HZ. + * @retval kStatus_LPUART_BaudrateNotSupport Baudrate is not support in current clock source. + * @retval kStatus_Success LPUART initialize succeed + */ +status_t LPUART_Init(LPUART_Type *base, const lpuart_config_t *config, uint32_t srcClock_Hz); + +/*! + * @brief Deinitializes a LPUART instance. + * + * This function waits for transmit to complete, disables TX and RX, and disables the LPUART clock. + * + * @param base LPUART peripheral base address. + */ +void LPUART_Deinit(LPUART_Type *base); + +/*! + * @brief Gets the default configuration structure. + * + * This function initializes the LPUART configuration structure to a default value. The default + * values are: + * lpuartConfig->baudRate_Bps = 115200U; + * lpuartConfig->parityMode = kLPUART_ParityDisabled; + * lpuartConfig->dataBitsCount = kLPUART_EightDataBits; + * lpuartConfig->isMsb = false; + * lpuartConfig->stopBitCount = kLPUART_OneStopBit; + * lpuartConfig->txFifoWatermark = 0; + * lpuartConfig->rxFifoWatermark = 1; + * lpuartConfig->rxIdleType = kLPUART_IdleTypeStartBit; + * lpuartConfig->rxIdleConfig = kLPUART_IdleCharacter1; + * lpuartConfig->enableTx = false; + * lpuartConfig->enableRx = false; + * + * @param config Pointer to a configuration structure. + */ +void LPUART_GetDefaultConfig(lpuart_config_t *config); +/*! @} */ + +/*! + * @name Module configuration + * @{ + */ +/*! + * @brief Sets the LPUART instance baudrate. + * + * This function configures the LPUART module baudrate. This function is used to update + * the LPUART module baudrate after the LPUART module is initialized by the LPUART_Init. + * @code + * LPUART_SetBaudRate(LPUART1, 115200U, 20000000U); + * @endcode + * + * @param base LPUART peripheral base address. + * @param baudRate_Bps LPUART baudrate to be set. + * @param srcClock_Hz LPUART clock source frequency in HZ. + * @retval kStatus_LPUART_BaudrateNotSupport Baudrate is not supported in the current clock source. + * @retval kStatus_Success Set baudrate succeeded. + */ +status_t LPUART_SetBaudRate(LPUART_Type *base, uint32_t baudRate_Bps, uint32_t srcClock_Hz); + +/*! + * @brief Enable 9-bit data mode for LPUART. + * + * This function set the 9-bit mode for LPUART module. The 9th bit is not used for parity thus can be modified by user. + * + * @param base LPUART peripheral base address. + * @param enable true to enable, flase to disable. + */ +void LPUART_Enable9bitMode(LPUART_Type *base, bool enable); + +/*! + * @brief Set the LPUART address. + * + * This function configures the address for LPUART module that works as slave in 9-bit data mode. One or two address + * fields can be configured. When the address field's match enable bit is set, the frame it receices with MSB being + * 1 is considered as an address frame, otherwise it is considered as data frame. Once the address frame matches one + * of slave's own addresses, this slave is addressed. This address frame and its following data frames are stored in + * the receive buffer, otherwise the frames will be discarded. To un-address a slave, just send an address frame with + * unmatched address. + * + * @note Any LPUART instance joined in the multi-slave system can work as slave. The position of the address mark is the + * same as the parity bit when parity is enabled for 8 bit and 9 bit data formats. + * + * @param base LPUART peripheral base address. + * @param address1 LPUART slave address1. + * @param address2 LPUART slave address2. + */ +static inline void LPUART_SetMatchAddress(LPUART_Type *base, uint16_t address1, uint16_t address2) +{ + /* Configure match address. */ + uint32_t address = ((uint32_t)address2 << 16U) | (uint32_t)address1 | 0x1000100UL; + base->MATCH = address; +} + +/*! + * @brief Enable the LPUART match address feature. + * + * @param base LPUART peripheral base address. + * @param match1 true to enable match address1, false to disable. + * @param match2 true to enable match address2, false to disable. + */ +static inline void LPUART_EnableMatchAddress(LPUART_Type *base, bool match1, bool match2) +{ + /* Configure match address1 enable bit. */ + if (match1) + { + base->BAUD |= (uint32_t)LPUART_BAUD_MAEN1_MASK; + } + else + { + base->BAUD &= ~(uint32_t)LPUART_BAUD_MAEN1_MASK; + } + /* Configure match address2 enable bit. */ + if (match2) + { + base->BAUD |= (uint32_t)LPUART_BAUD_MAEN2_MASK; + } + else + { + base->BAUD &= ~(uint32_t)LPUART_BAUD_MAEN2_MASK; + } +} + +#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO +/*! + * @brief Sets the rx FIFO watermark. + * + * @param base LPUART peripheral base address. + * @param water Rx FIFO watermark. + */ +static inline void LPUART_SetRxFifoWatermark(LPUART_Type *base, uint8_t water) +{ + assert(FSL_FEATURE_LPUART_FIFO_SIZEn(base) > 0); + assert((uint8_t)FSL_FEATURE_LPUART_FIFO_SIZEn(base) > water); + base->WATER = (base->WATER & ~LPUART_WATER_RXWATER_MASK) | LPUART_WATER_RXWATER(water); +} + +/*! + * @brief Sets the tx FIFO watermark. + * + * @param base LPUART peripheral base address. + * @param water Tx FIFO watermark. + */ +static inline void LPUART_SetTxFifoWatermark(LPUART_Type *base, uint8_t water) +{ + assert(FSL_FEATURE_LPUART_FIFO_SIZEn(base) > 0); + assert((uint8_t)FSL_FEATURE_LPUART_FIFO_SIZEn(base) > water); + base->WATER = (base->WATER & ~LPUART_WATER_TXWATER_MASK) | LPUART_WATER_TXWATER(water); +} +#endif + +/*! + * @brief Sets the LPUART using 16bit transmit, only for 9bit or 10bit mode. + * + * This function Enable 16bit Data transmit in lpuart_handle_t. + * + * @param handle LPUART handle pointer. + * @param enable true to enable, false to disable. + */ +static inline void LPUART_TransferEnable16Bit(lpuart_handle_t *handle, bool enable) +{ + handle->is16bitData = enable; +} +/*! @} */ + +/*! + * @name Status + * @{ + */ + +/*! + * @brief Gets LPUART status flags. + * + * This function gets all LPUART status flags. The flags are returned as the logical + * OR value of the enumerators @ref _lpuart_flags. To check for a specific status, + * compare the return value with enumerators in the @ref _lpuart_flags. + * For example, to check whether the TX is empty: + * @code + * if (kLPUART_TxDataRegEmptyFlag & LPUART_GetStatusFlags(LPUART1)) + * { + * ... + * } + * @endcode + * + * @param base LPUART peripheral base address. + * @return LPUART status flags which are ORed by the enumerators in the _lpuart_flags. + */ +uint32_t LPUART_GetStatusFlags(LPUART_Type *base); + +/*! + * @brief Clears status flags with a provided mask. + * + * This function clears LPUART status flags with a provided mask. Automatically cleared flags + * can't be cleared by this function. + * Flags that can only cleared or set by hardware are: + * kLPUART_TxDataRegEmptyFlag, kLPUART_TransmissionCompleteFlag, kLPUART_RxDataRegFullFlag, + * kLPUART_RxActiveFlag, kLPUART_NoiseErrorFlag, kLPUART_ParityErrorFlag, + * kLPUART_TxFifoEmptyFlag,kLPUART_RxFifoEmptyFlag + * Note: This API should be called when the Tx/Rx is idle, otherwise it takes no effects. + * + * @param base LPUART peripheral base address. + * @param mask the status flags to be cleared. The user can use the enumerators in the + * _lpuart_status_flag_t to do the OR operation and get the mask. + * @return 0 succeed, others failed. + * @retval kStatus_LPUART_FlagCannotClearManually The flag can't be cleared by this function but + * it is cleared automatically by hardware. + * @retval kStatus_Success Status in the mask are cleared. + */ +status_t LPUART_ClearStatusFlags(LPUART_Type *base, uint32_t mask); +/*! @} */ + +/*! + * @name Interrupts + * @{ + */ + +/*! + * @brief Enables LPUART interrupts according to a provided mask. + * + * This function enables the LPUART interrupts according to a provided mask. The mask + * is a logical OR of enumeration members. See the @ref _lpuart_interrupt_enable. + * This examples shows how to enable TX empty interrupt and RX full interrupt: + * @code + * LPUART_EnableInterrupts(LPUART1,kLPUART_TxDataRegEmptyInterruptEnable | kLPUART_RxDataRegFullInterruptEnable); + * @endcode + * + * @param base LPUART peripheral base address. + * @param mask The interrupts to enable. Logical OR of @ref _lpuart_interrupt_enable. + */ +void LPUART_EnableInterrupts(LPUART_Type *base, uint32_t mask); + +/*! + * @brief Disables LPUART interrupts according to a provided mask. + * + * This function disables the LPUART interrupts according to a provided mask. The mask + * is a logical OR of enumeration members. See @ref _lpuart_interrupt_enable. + * This example shows how to disable the TX empty interrupt and RX full interrupt: + * @code + * LPUART_DisableInterrupts(LPUART1,kLPUART_TxDataRegEmptyInterruptEnable | kLPUART_RxDataRegFullInterruptEnable); + * @endcode + * + * @param base LPUART peripheral base address. + * @param mask The interrupts to disable. Logical OR of @ref _lpuart_interrupt_enable. + */ +void LPUART_DisableInterrupts(LPUART_Type *base, uint32_t mask); + +/*! + * @brief Gets enabled LPUART interrupts. + * + * This function gets the enabled LPUART interrupts. The enabled interrupts are returned + * as the logical OR value of the enumerators @ref _lpuart_interrupt_enable. To check + * a specific interrupt enable status, compare the return value with enumerators + * in @ref _lpuart_interrupt_enable. + * For example, to check whether the TX empty interrupt is enabled: + * @code + * uint32_t enabledInterrupts = LPUART_GetEnabledInterrupts(LPUART1); + * + * if (kLPUART_TxDataRegEmptyInterruptEnable & enabledInterrupts) + * { + * ... + * } + * @endcode + * + * @param base LPUART peripheral base address. + * @return LPUART interrupt flags which are logical OR of the enumerators in @ref _lpuart_interrupt_enable. + */ +uint32_t LPUART_GetEnabledInterrupts(LPUART_Type *base); +/*! @} */ + +#if defined(FSL_FEATURE_LPUART_HAS_DMA_ENABLE) && FSL_FEATURE_LPUART_HAS_DMA_ENABLE +/*! + * @name DMA Configuration + * @{ + */ +/*! + * @brief Gets the LPUART data register address. + * + * This function returns the LPUART data register address, which is mainly used by the DMA/eDMA. + * + * @param base LPUART peripheral base address. + * @return LPUART data register addresses which are used both by the transmitter and receiver. + */ +static inline uintptr_t LPUART_GetDataRegisterAddress(LPUART_Type *base) +{ + return (uintptr_t) & (base->DATA); +} + +/*! + * @brief Enables or disables the LPUART transmitter DMA request. + * + * This function enables or disables the transmit data register empty flag, STAT[TDRE], to generate DMA requests. + * + * @param base LPUART peripheral base address. + * @param enable True to enable, false to disable. + */ +static inline void LPUART_EnableTxDMA(LPUART_Type *base, bool enable) +{ + if (enable) + { + base->BAUD |= LPUART_BAUD_TDMAE_MASK; + } + else + { + base->BAUD &= ~LPUART_BAUD_TDMAE_MASK; + } +} + +/*! + * @brief Enables or disables the LPUART receiver DMA. + * + * This function enables or disables the receiver data register full flag, STAT[RDRF], to generate DMA requests. + * + * @param base LPUART peripheral base address. + * @param enable True to enable, false to disable. + */ +static inline void LPUART_EnableRxDMA(LPUART_Type *base, bool enable) +{ + if (enable) + { + base->BAUD |= LPUART_BAUD_RDMAE_MASK; + } + else + { + base->BAUD &= ~LPUART_BAUD_RDMAE_MASK; + } +} +/*! @} */ +#endif /* FSL_FEATURE_LPUART_HAS_DMA_ENABLE */ + +/*! + * @name Bus Operations + * @{ + */ + +/*! + * @brief Get the LPUART instance from peripheral base address. + * + * @param base LPUART peripheral base address. + * @return LPUART instance. + */ +uint32_t LPUART_GetInstance(LPUART_Type *base); + +/*! + * @brief Set the LPUART instance to peripheral base address. + * + * @note Add this function to support remap LPUART base address. + * @param instance LPUART instance. + * @param base LPUART peripheral base address. + */ +void LPUART_SetInstance(uint32_t instance, LPUART_Type *base); + +/*! + * @brief Enables or disables the LPUART transmitter. + * + * This function enables or disables the LPUART transmitter. + * + * @param base LPUART peripheral base address. + * @param enable True to enable, false to disable. + */ +static inline void LPUART_EnableTx(LPUART_Type *base, bool enable) +{ + if (enable) + { + base->CTRL |= LPUART_CTRL_TE_MASK; + } + else + { + base->CTRL &= ~LPUART_CTRL_TE_MASK; + } +} + +/*! + * @brief Enables or disables the LPUART receiver. + * + * This function enables or disables the LPUART receiver. + * + * @param base LPUART peripheral base address. + * @param enable True to enable, false to disable. + */ +static inline void LPUART_EnableRx(LPUART_Type *base, bool enable) +{ + if (enable) + { + base->CTRL |= LPUART_CTRL_RE_MASK; + } + else + { + base->CTRL &= ~LPUART_CTRL_RE_MASK; + } +} + +/*! + * @brief Writes to the transmitter register. + * + * This function writes data to the transmitter register directly. The upper layer must + * ensure that the TX register is empty or that the TX FIFO has room before calling this function. + * + * @param base LPUART peripheral base address. + * @param data Data write to the TX register. + */ +static inline void LPUART_WriteByte(LPUART_Type *base, uint8_t data) +{ + base->DATA = data; +} + +/*! + * @brief Reads the receiver register. + * + * This function reads data from the receiver register directly. The upper layer must + * ensure that the receiver register is full or that the RX FIFO has data before calling this function. + * + * @param base LPUART peripheral base address. + * @return Data read from data register. + */ +static inline uint8_t LPUART_ReadByte(LPUART_Type *base) +{ +#if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT + uint32_t ctrl = base->CTRL; + uint8_t result; + /* + * $Branch Coverage Justification$ + * (ctrl & LPUART_CTRL_M7_MASK) == 0U) false is not covered. + * If ctrl & LPUART_CTRL_M7_MASK is 0, it can't be !0 in next judge. + */ + bool isSevenDataBits = (((ctrl & LPUART_CTRL_M7_MASK) != 0U) || + (((ctrl & LPUART_CTRL_M7_MASK) == 0U) && ((ctrl & LPUART_CTRL_M_MASK) == 0U) && + ((ctrl & LPUART_CTRL_PE_MASK) != 0U))); + + if (isSevenDataBits) + { + result = (uint8_t)(base->DATA & 0x7FU); + } + else + { + result = (uint8_t)base->DATA; + } + + return result; +#else + return (uint8_t)(base->DATA); +#endif +} + +#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO +/*! + * @brief Gets the rx FIFO data count. + * + * @param base LPUART peripheral base address. + * @return rx FIFO data count. + */ +static inline uint8_t LPUART_GetRxFifoCount(LPUART_Type *base) +{ + return (uint8_t)((base->WATER & LPUART_WATER_RXCOUNT_MASK) >> LPUART_WATER_RXCOUNT_SHIFT); +} + +/*! + * @brief Gets the tx FIFO data count. + * + * @param base LPUART peripheral base address. + * @return tx FIFO data count. + */ +static inline uint8_t LPUART_GetTxFifoCount(LPUART_Type *base) +{ + return (uint8_t)((base->WATER & LPUART_WATER_TXCOUNT_MASK) >> LPUART_WATER_TXCOUNT_SHIFT); +} +#endif + +/*! + * @brief Transmit an address frame in 9-bit data mode. + * + * @param base LPUART peripheral base address. + * @param address LPUART slave address. + */ +void LPUART_SendAddress(LPUART_Type *base, uint8_t address); + +/*! + * @brief Writes to the transmitter register using a blocking method. + * + * This function polls the transmitter register, first waits for the register to be empty or TX FIFO to have room, + * and writes data to the transmitter buffer, then waits for the dat to be sent out to the bus. + * + * @param base LPUART peripheral base address. + * @param data Start address of the data to write. + * @param length Size of the data to write. + * @retval kStatus_LPUART_Timeout Transmission timed out and was aborted. + * @retval kStatus_Success Successfully wrote all data. + */ +status_t LPUART_WriteBlocking(LPUART_Type *base, const uint8_t *data, size_t length); + +/*! + * @brief Writes to the transmitter register using a blocking method in 9bit or 10bit mode. + * + * @note This function only support 9bit or 10bit transfer. + * Please make sure only 10bit of data is valid and other bits are 0. + * + * @param base LPUART peripheral base address. + * @param data Start address of the data to write. + * @param length Size of the data to write. + * @retval kStatus_LPUART_Timeout Transmission timed out and was aborted. + * @retval kStatus_Success Successfully wrote all data. + */ +status_t LPUART_WriteBlocking16bit(LPUART_Type *base, const uint16_t *data, size_t length); + +/*! + * @brief Reads the receiver data register using a blocking method. + * + * This function polls the receiver register, waits for the receiver register full or receiver FIFO + * has data, and reads data from the TX register. + * + * @param base LPUART peripheral base address. + * @param data Start address of the buffer to store the received data. + * @param length Size of the buffer. + * @retval kStatus_LPUART_RxHardwareOverrun Receiver overrun happened while receiving data. + * @retval kStatus_LPUART_NoiseError Noise error happened while receiving data. + * @retval kStatus_LPUART_FramingError Framing error happened while receiving data. + * @retval kStatus_LPUART_ParityError Parity error happened while receiving data. + * @retval kStatus_LPUART_Timeout Transmission timed out and was aborted. + * @retval kStatus_Success Successfully received all data. + */ +status_t LPUART_ReadBlocking(LPUART_Type *base, uint8_t *data, size_t length); + +/*! + * @brief Reads the receiver data register in 9bit or 10bit mode. + * + * @note This function only support 9bit or 10bit transfer. + * + * @param base LPUART peripheral base address. + * @param data Start address of the buffer to store the received data by 16bit, only 10bit is valid. + * @param length Size of the buffer. + * @retval kStatus_LPUART_RxHardwareOverrun Receiver overrun happened while receiving data. + * @retval kStatus_LPUART_NoiseError Noise error happened while receiving data. + * @retval kStatus_LPUART_FramingError Framing error happened while receiving data. + * @retval kStatus_LPUART_ParityError Parity error happened while receiving data. + * @retval kStatus_LPUART_Timeout Transmission timed out and was aborted. + * @retval kStatus_Success Successfully received all data. + */ +status_t LPUART_ReadBlocking16bit(LPUART_Type *base, uint16_t *data, size_t length); + +/*! @} */ + +/*! + * @name Transactional + * @{ + */ + +/*! + * @brief Initializes the LPUART handle. + * + * This function initializes the LPUART handle, which can be used for other LPUART + * transactional APIs. Usually, for a specified LPUART instance, + * call this API once to get the initialized handle. + * + * The LPUART driver supports the "background" receiving, which means that user can set up + * an RX ring buffer optionally. Data received is stored into the ring buffer even when the + * user doesn't call the LPUART_TransferReceiveNonBlocking() API. If there is already data received + * in the ring buffer, the user can get the received data from the ring buffer directly. + * The ring buffer is disabled if passing NULL as @p ringBuffer. + * + * @param base LPUART peripheral base address. + * @param handle LPUART handle pointer. + * @param callback Callback function. + * @param userData User data. + */ +void LPUART_TransferCreateHandle(LPUART_Type *base, + lpuart_handle_t *handle, + lpuart_transfer_callback_t callback, + void *userData); +/*! + * @brief Transmits a buffer of data using the interrupt method. + * + * This function send data using an interrupt method. This is a non-blocking function, which + * returns directly without waiting for all data written to the transmitter register. When + * all data is written to the TX register in the ISR, the LPUART driver calls the callback + * function and passes the @ref kStatus_LPUART_TxIdle as status parameter. + * + * @note The kStatus_LPUART_TxIdle is passed to the upper layer when all data are written + * to the TX register. However, there is no check to ensure that all the data sent out. Before disabling the TX, + * check the kLPUART_TransmissionCompleteFlag to ensure that the transmit is finished. + * + * @param base LPUART peripheral base address. + * @param handle LPUART handle pointer. + * @param xfer LPUART transfer structure, see #lpuart_transfer_t. + * @retval kStatus_Success Successfully start the data transmission. + * @retval kStatus_LPUART_TxBusy Previous transmission still not finished, data not all written to the TX register. + * @retval kStatus_InvalidArgument Invalid argument. + */ +status_t LPUART_TransferSendNonBlocking(LPUART_Type *base, lpuart_handle_t *handle, lpuart_transfer_t *xfer); + +/*! + * @brief Sets up the RX ring buffer. + * + * This function sets up the RX ring buffer to a specific UART handle. + * + * When the RX ring buffer is used, data received is stored into the ring buffer even when + * the user doesn't call the UART_TransferReceiveNonBlocking() API. If there is already data received + * in the ring buffer, the user can get the received data from the ring buffer directly. + * + * @note When using RX ring buffer, one byte is reserved for internal use. In other + * words, if @p ringBufferSize is 32, then only 31 bytes are used for saving data. + * + * @param base LPUART peripheral base address. + * @param handle LPUART handle pointer. + * @param ringBuffer Start address of ring buffer for background receiving. Pass NULL to disable the ring buffer. + * @param ringBufferSize size of the ring buffer. + */ +void LPUART_TransferStartRingBuffer(LPUART_Type *base, + lpuart_handle_t *handle, + uint8_t *ringBuffer, + size_t ringBufferSize); + +/*! + * @brief Aborts the background transfer and uninstalls the ring buffer. + * + * This function aborts the background transfer and uninstalls the ring buffer. + * + * @param base LPUART peripheral base address. + * @param handle LPUART handle pointer. + */ +void LPUART_TransferStopRingBuffer(LPUART_Type *base, lpuart_handle_t *handle); + +/*! + * @brief Get the length of received data in RX ring buffer. + * + * @param base LPUART peripheral base address. + * @param handle LPUART handle pointer. + * @return Length of received data in RX ring buffer. + */ +size_t LPUART_TransferGetRxRingBufferLength(LPUART_Type *base, lpuart_handle_t *handle); + +/*! + * @brief Aborts the interrupt-driven data transmit. + * + * This function aborts the interrupt driven data sending. The user can get the remainBtyes to find out + * how many bytes are not sent out. + * + * @param base LPUART peripheral base address. + * @param handle LPUART handle pointer. + */ +void LPUART_TransferAbortSend(LPUART_Type *base, lpuart_handle_t *handle); + +/*! + * @brief Gets the number of bytes that have been sent out to bus. + * + * This function gets the number of bytes that have been sent out to bus by an interrupt method. + * + * @param base LPUART peripheral base address. + * @param handle LPUART handle pointer. + * @param count Send bytes count. + * @retval kStatus_NoTransferInProgress No send in progress. + * @retval kStatus_InvalidArgument Parameter is invalid. + * @retval kStatus_Success Get successfully through the parameter \p count; + */ +status_t LPUART_TransferGetSendCount(LPUART_Type *base, lpuart_handle_t *handle, uint32_t *count); + +/*! + * @brief Receives a buffer of data using the interrupt method. + * + * This function receives data using an interrupt method. This is a non-blocking function + * which returns without waiting to ensure that all data are received. + * If the RX ring buffer is used and not empty, the data in the ring buffer is copied and + * the parameter @p receivedBytes shows how many bytes are copied from the ring buffer. + * After copying, if the data in the ring buffer is not enough for read, the receive + * request is saved by the LPUART driver. When the new data arrives, the receive request + * is serviced first. When all data is received, the LPUART driver notifies the upper layer + * through a callback function and passes a status parameter kStatus_UART_RxIdle. + * For example, the upper layer needs 10 bytes but there are only 5 bytes in ring buffer. + * The 5 bytes are copied to xfer->data, which returns with the + * parameter @p receivedBytes set to 5. For the remaining 5 bytes, the newly arrived data is + * saved from xfer->data[5]. When 5 bytes are received, the LPUART driver notifies the upper layer. + * If the RX ring buffer is not enabled, this function enables the RX and RX interrupt + * to receive data to xfer->data. When all data is received, the upper layer is notified. + * + * @param base LPUART peripheral base address. + * @param handle LPUART handle pointer. + * @param xfer LPUART transfer structure, see uart_transfer_t. + * @param receivedBytes Bytes received from the ring buffer directly. + * @retval kStatus_Success Successfully queue the transfer into the transmit queue. + * @retval kStatus_LPUART_RxBusy Previous receive request is not finished. + * @retval kStatus_InvalidArgument Invalid argument. + */ +status_t LPUART_TransferReceiveNonBlocking(LPUART_Type *base, + lpuart_handle_t *handle, + lpuart_transfer_t *xfer, + size_t *receivedBytes); + +/*! + * @brief Aborts the interrupt-driven data receiving. + * + * This function aborts the interrupt-driven data receiving. The user can get the remainBytes to find out + * how many bytes not received yet. + * + * @param base LPUART peripheral base address. + * @param handle LPUART handle pointer. + */ +void LPUART_TransferAbortReceive(LPUART_Type *base, lpuart_handle_t *handle); + +/*! + * @brief Gets the number of bytes that have been received. + * + * This function gets the number of bytes that have been received. + * + * @param base LPUART peripheral base address. + * @param handle LPUART handle pointer. + * @param count Receive bytes count. + * @retval kStatus_NoTransferInProgress No receive in progress. + * @retval kStatus_InvalidArgument Parameter is invalid. + * @retval kStatus_Success Get successfully through the parameter \p count; + */ +status_t LPUART_TransferGetReceiveCount(LPUART_Type *base, lpuart_handle_t *handle, uint32_t *count); + +/*! + * @brief LPUART IRQ handle function. + * + * This function handles the LPUART transmit and receive IRQ request. + * + * @param base LPUART peripheral base address. + * @param irqHandle LPUART handle pointer. + */ +void LPUART_TransferHandleIRQ(LPUART_Type *base, void *irqHandle); + +/*! + * @brief LPUART Error IRQ handle function. + * + * This function handles the LPUART error IRQ request. + * + * @param base LPUART peripheral base address. + * @param irqHandle LPUART handle pointer. + */ +void LPUART_TransferHandleErrorIRQ(LPUART_Type *base, void *irqHandle); + +/*! + * @brief LPUART driver IRQ handler common entry. + * + * This function provides the common IRQ request entry for LPUART. + * + * @param instance LPUART instance. + */ +void LPUART_DriverIRQHandler(uint32_t instance); + +/*! @} */ + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* FSL_LPUART_H_ */ diff --git a/bsp/nxp/imx/imx91/drivers/sdk/drivers/lpuart/fsl_lpuart_dma.c b/bsp/nxp/imx/imx91/drivers/sdk/drivers/lpuart/fsl_lpuart_dma.c new file mode 100644 index 00000000000..5d75e6bdd7c --- /dev/null +++ b/bsp/nxp/imx/imx91/drivers/sdk/drivers/lpuart/fsl_lpuart_dma.c @@ -0,0 +1,434 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#include "fsl_lpuart_dma.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.lpuart_dma" +#endif + +/*base, false); + + /* Disable interrupt. */ + DMA_DisableInterrupts(lpuartPrivateHandle->handle->txDmaHandle->base, + lpuartPrivateHandle->handle->txDmaHandle->channel); + + /* Enable tx complete interrupt */ + LPUART_EnableInterrupts(lpuartPrivateHandle->base, (uint32_t)kLPUART_TransmissionCompleteInterruptEnable); +} + +static void LPUART_TransferReceiveDMACallback(dma_handle_t *handle, void *param) +{ + assert(handle != NULL); + assert(param != NULL); + + lpuart_dma_private_handle_t *lpuartPrivateHandle = (lpuart_dma_private_handle_t *)param; + + /* Disable LPUART RX DMA. */ + LPUART_EnableRxDMA(lpuartPrivateHandle->base, false); + + /* Disable interrupt. */ + DMA_DisableInterrupts(lpuartPrivateHandle->handle->rxDmaHandle->base, + lpuartPrivateHandle->handle->rxDmaHandle->channel); + + lpuartPrivateHandle->handle->rxState = (uint8_t)kLPUART_RxIdle; + + if (lpuartPrivateHandle->handle->callback != NULL) + { + lpuartPrivateHandle->handle->callback(lpuartPrivateHandle->base, lpuartPrivateHandle->handle, + kStatus_LPUART_RxIdle, lpuartPrivateHandle->handle->userData); + } +} + +/*! + * brief Initializes the LPUART handle which is used in transactional functions. + * + * note This function disables all LPUART interrupts. + * + * param base LPUART peripheral base address. + * param handle Pointer to lpuart_dma_handle_t structure. + * param callback Callback function. + * param userData User data. + * param txDmaHandle User-requested DMA handle for TX DMA transfer. + * param rxDmaHandle User-requested DMA handle for RX DMA transfer. + */ +void LPUART_TransferCreateHandleDMA(LPUART_Type *base, + lpuart_dma_handle_t *handle, + lpuart_dma_transfer_callback_t callback, + void *userData, + dma_handle_t *txDmaHandle, + dma_handle_t *rxDmaHandle) +{ + assert(handle != NULL); + + uint32_t instance = LPUART_GetInstance(base); + + (void)memset(handle, 0, sizeof(lpuart_dma_handle_t)); + + s_dmaPrivateHandle[instance].base = base; + s_dmaPrivateHandle[instance].handle = handle; + + handle->rxState = (uint8_t)kLPUART_RxIdle; + handle->txState = (uint8_t)kLPUART_TxIdle; + + handle->callback = callback; + handle->userData = userData; + +#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO + /* Note: + Take care of the RX FIFO, DMA request only assert when received bytes + equal or more than RX water mark, there is potential issue if RX water + mark larger than 1. + For example, if RX FIFO water mark is 2, upper layer needs 5 bytes and + 5 bytes are received. the last byte will be saved in FIFO but not trigger + DMA transfer because the water mark is 2. + */ + if (rxDmaHandle != NULL) + { + base->WATER &= (~LPUART_WATER_RXWATER_MASK); + } +#endif + + handle->rxDmaHandle = rxDmaHandle; + handle->txDmaHandle = txDmaHandle; + + /* Save the handle in global variables to support the double weak mechanism. */ + s_lpuartHandle[instance] = handle; + /* Set LPUART_TransferDMAHandleIRQ as DMA IRQ handler */ + s_lpuartIsr[instance] = LPUART_TransferDMAHandleIRQ; + /* Disable all LPUART internal interrupts */ + LPUART_DisableInterrupts(base, (uint32_t)kLPUART_AllInterruptEnable); + /* Enable interrupt in NVIC. */ +#if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ + (void)EnableIRQ(s_lpuartTxIRQ[instance]); +#else + (void)EnableIRQ(s_lpuartIRQ[instance]); +#endif + + /* Configure TX. */ + if (txDmaHandle != NULL) + { + DMA_SetCallback(txDmaHandle, LPUART_TransferSendDMACallback, &s_dmaPrivateHandle[instance]); + } + + /* Configure RX. */ + if (rxDmaHandle != NULL) + { + DMA_SetCallback(rxDmaHandle, LPUART_TransferReceiveDMACallback, &s_dmaPrivateHandle[instance]); + } +} + +/*! + * brief Sends data using DMA. + * + * This function sends data using DMA. This is a non-blocking function, which returns + * right away. When all data is sent, the send callback function is called. + * + * param base LPUART peripheral base address. + * param handle LPUART handle pointer. + * param xfer LPUART DMA transfer structure. See #lpuart_transfer_t. + * retval kStatus_Success if succeed, others failed. + * retval kStatus_LPUART_TxBusy Previous transfer on going. + * retval kStatus_InvalidArgument Invalid argument. + */ +status_t LPUART_TransferSendDMA(LPUART_Type *base, lpuart_dma_handle_t *handle, lpuart_transfer_t *xfer) +{ + assert(handle != NULL); + assert(handle->txDmaHandle != NULL); + assert(xfer != NULL); + assert(xfer->data != NULL); + assert(xfer->dataSize != 0U); + + status_t status; + dma_transfer_config_t xferConfig; + + /* If previous TX not finished. */ + if ((uint8_t)kLPUART_TxBusy == handle->txState) + { + status = kStatus_LPUART_TxBusy; + } + else + { + handle->txState = (uint8_t)kLPUART_TxBusy; + handle->txDataSizeAll = xfer->dataSize; + + /* Prepare transfer. */ + uint32_t address = LPUART_GetDataRegisterAddress(base); + DMA_PrepareTransfer(&xferConfig, xfer->data, sizeof(uint8_t), (uint32_t *)address, sizeof(uint8_t), + xfer->dataSize, kDMA_MemoryToPeripheral); + + /* Submit transfer. */ + (void)DMA_SubmitTransfer(handle->txDmaHandle, &xferConfig, (uint32_t)kDMA_EnableInterrupt); + DMA_StartTransfer(handle->txDmaHandle); + + /* Enable LPUART TX DMA. */ + LPUART_EnableTxDMA(base, true); + + status = kStatus_Success; + } + + return status; +} + +/*! + * brief Receives data using DMA. + * + * This function receives data using DMA. This is a non-blocking function, which returns + * right away. When all data is received, the receive callback function is called. + * + * param base LPUART peripheral base address. + * param handle Pointer to lpuart_dma_handle_t structure. + * param xfer LPUART DMA transfer structure. See #lpuart_transfer_t. + * retval kStatus_Success if succeed, others failed. + * retval kStatus_LPUART_RxBusy Previous transfer on going. + * retval kStatus_InvalidArgument Invalid argument. + */ +status_t LPUART_TransferReceiveDMA(LPUART_Type *base, lpuart_dma_handle_t *handle, lpuart_transfer_t *xfer) +{ + assert(handle != NULL); + assert(handle->rxDmaHandle != NULL); + assert(xfer != NULL); + assert(xfer->data != NULL); + assert(xfer->dataSize != 0U); + + status_t status; + dma_transfer_config_t xferConfig; + + /* If previous RX not finished. */ + if ((uint8_t)kLPUART_RxBusy == handle->rxState) + { + status = kStatus_LPUART_RxBusy; + } + else + { + handle->rxState = (uint8_t)kLPUART_RxBusy; + handle->rxDataSizeAll = xfer->dataSize; + + /* Prepare transfer. */ + uint32_t address = LPUART_GetDataRegisterAddress(base); + DMA_PrepareTransfer(&xferConfig, (uint32_t *)address, sizeof(uint8_t), xfer->data, sizeof(uint8_t), + xfer->dataSize, kDMA_PeripheralToMemory); + + /* Submit transfer. */ + (void)DMA_SubmitTransfer(handle->rxDmaHandle, &xferConfig, (uint32_t)kDMA_EnableInterrupt); + DMA_StartTransfer(handle->rxDmaHandle); + + /* Enable LPUART RX DMA. */ + LPUART_EnableRxDMA(base, true); + + status = kStatus_Success; + } + + return status; +} + +/*! + * brief Aborts the sent data using DMA. + * + * This function aborts send data using DMA. + * + * param base LPUART peripheral base address + * param handle Pointer to lpuart_dma_handle_t structure + */ +void LPUART_TransferAbortSendDMA(LPUART_Type *base, lpuart_dma_handle_t *handle) +{ + assert(handle != NULL); + assert(handle->txDmaHandle != NULL); + + /* Disable LPUART TX DMA. */ + LPUART_EnableTxDMA(base, false); + + /* Stop transfer. */ + DMA_AbortTransfer(handle->txDmaHandle); + + /* Write DMA->DSR[DONE] to abort transfer and clear status. */ + DMA_ClearChannelStatusFlags(handle->txDmaHandle->base, handle->txDmaHandle->channel, + (uint32_t)kDMA_TransactionsDoneFlag); + + handle->txState = (uint8_t)kLPUART_TxIdle; +} + +/*! + * brief Aborts the received data using DMA. + * + * This function aborts the received data using DMA. + * + * param base LPUART peripheral base address + * param handle Pointer to lpuart_dma_handle_t structure + */ +void LPUART_TransferAbortReceiveDMA(LPUART_Type *base, lpuart_dma_handle_t *handle) +{ + assert(handle != NULL); + assert(handle->rxDmaHandle != NULL); + + /* Disable LPUART RX DMA. */ + LPUART_EnableRxDMA(base, false); + + /* Stop transfer. */ + DMA_AbortTransfer(handle->rxDmaHandle); + + /* Write DMA->DSR[DONE] to abort transfer and clear status. */ + DMA_ClearChannelStatusFlags(handle->rxDmaHandle->base, handle->rxDmaHandle->channel, + (uint32_t)kDMA_TransactionsDoneFlag); + + handle->rxState = (uint8_t)kLPUART_RxIdle; +} + +/*! + * brief Gets the number of bytes written to the LPUART TX register. + * + * This function gets the number of bytes that have been written to LPUART TX + * register by DMA. + * + * param base LPUART peripheral base address. + * param handle LPUART handle pointer. + * param count Send bytes count. + * retval kStatus_NoTransferInProgress No send in progress. + * retval kStatus_InvalidArgument Parameter is invalid. + * retval kStatus_Success Get successfully through the parameter \p count; + */ +status_t LPUART_TransferGetSendCountDMA(LPUART_Type *base, lpuart_dma_handle_t *handle, uint32_t *count) +{ + assert(handle != NULL); + assert(handle->txDmaHandle != NULL); + assert(count != NULL); + + if ((uint8_t)kLPUART_TxIdle == handle->txState) + { + return kStatus_NoTransferInProgress; + } + + *count = handle->txDataSizeAll - DMA_GetRemainingBytes(handle->txDmaHandle->base, handle->txDmaHandle->channel); + + return kStatus_Success; +} + +/*! + * brief Gets the number of received bytes. + * + * This function gets the number of received bytes. + * + * param base LPUART peripheral base address. + * param handle LPUART handle pointer. + * param count Receive bytes count. + * retval kStatus_NoTransferInProgress No receive in progress. + * retval kStatus_InvalidArgument Parameter is invalid. + * retval kStatus_Success Get successfully through the parameter \p count; + */ +status_t LPUART_TransferGetReceiveCountDMA(LPUART_Type *base, lpuart_dma_handle_t *handle, uint32_t *count) +{ + assert(handle != NULL); + assert(handle->rxDmaHandle != NULL); + assert(count != NULL); + + if ((uint8_t)kLPUART_RxIdle == handle->rxState) + { + return kStatus_NoTransferInProgress; + } + + *count = handle->rxDataSizeAll - DMA_GetRemainingBytes(handle->rxDmaHandle->base, handle->rxDmaHandle->channel); + + return kStatus_Success; +} + +/*! + * brief LPUART DMA IRQ handle function. + * + * This function handles the LPUART tx complete IRQ request and invoke user callback. + * note This function is used as default IRQ handler by double weak mechanism. + * If user's specific IRQ handler is implemented, make sure this function is invoked in the handler. + * + * param base LPUART peripheral base address. + * param lpuartDmaHandle LPUART handle pointer. + */ +void LPUART_TransferDMAHandleIRQ(LPUART_Type *base, void *lpuartDmaHandle) +{ + assert(lpuartDmaHandle != NULL); + + if (((uint32_t)kLPUART_TransmissionCompleteFlag & LPUART_GetStatusFlags(base)) != 0U) + { + lpuart_dma_handle_t *handle = (lpuart_dma_handle_t *)lpuartDmaHandle; + + /* Disable tx complete interrupt */ + LPUART_DisableInterrupts(base, (uint32_t)kLPUART_TransmissionCompleteInterruptEnable); + + handle->txState = (uint8_t)kLPUART_TxIdle; + + if (handle->callback != NULL) + { + handle->callback(base, handle, kStatus_LPUART_TxIdle, handle->userData); + } + } +} diff --git a/bsp/nxp/imx/imx91/drivers/sdk/drivers/lpuart/fsl_lpuart_dma.h b/bsp/nxp/imx/imx91/drivers/sdk/drivers/lpuart/fsl_lpuart_dma.h new file mode 100644 index 00000000000..992163bbcf4 --- /dev/null +++ b/bsp/nxp/imx/imx91/drivers/sdk/drivers/lpuart/fsl_lpuart_dma.h @@ -0,0 +1,186 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef FSL_LPUART_DMA_H_ +#define FSL_LPUART_DMA_H_ + +#include "fsl_lpuart.h" +#include "fsl_dma.h" + +/*! + * @addtogroup lpuart_dma_driver + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*! @{ */ +/*! @brief LPUART DMA driver version. */ +#define FSL_LPUART_DMA_DRIVER_VERSION (MAKE_VERSION(2, 6, 0)) +/*! @} */ + +/* Forward declaration of the handle typedef. */ +typedef struct _lpuart_dma_handle lpuart_dma_handle_t; + +/*! @brief LPUART transfer callback function. */ +typedef void (*lpuart_dma_transfer_callback_t)(LPUART_Type *base, + lpuart_dma_handle_t *handle, + status_t status, + void *userData); + +/*! + * @brief LPUART DMA handle + */ +struct _lpuart_dma_handle +{ + lpuart_dma_transfer_callback_t callback; /*!< Callback function. */ + void *userData; /*!< LPUART callback function parameter.*/ + size_t rxDataSizeAll; /*!< Size of the data to receive. */ + size_t txDataSizeAll; /*!< Size of the data to send out. */ + + dma_handle_t *txDmaHandle; /*!< The DMA TX channel used. */ + dma_handle_t *rxDmaHandle; /*!< The DMA RX channel used. */ + + volatile uint8_t txState; /*!< TX transfer state. */ + volatile uint8_t rxState; /*!< RX transfer state */ +}; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name EDMA transactional + * @{ + */ + +/*! + * @brief Initializes the LPUART handle which is used in transactional functions. + * + * @note This function disables all LPUART interrupts. + * + * @param base LPUART peripheral base address. + * @param handle Pointer to lpuart_dma_handle_t structure. + * @param callback Callback function. + * @param userData User data. + * @param txDmaHandle User-requested DMA handle for TX DMA transfer. + * @param rxDmaHandle User-requested DMA handle for RX DMA transfer. + */ +void LPUART_TransferCreateHandleDMA(LPUART_Type *base, + lpuart_dma_handle_t *handle, + lpuart_dma_transfer_callback_t callback, + void *userData, + dma_handle_t *txDmaHandle, + dma_handle_t *rxDmaHandle); + +/*! + * @brief Sends data using DMA. + * + * This function sends data using DMA. This is a non-blocking function, which returns + * right away. When all data is sent, the send callback function is called. + * + * @param base LPUART peripheral base address. + * @param handle LPUART handle pointer. + * @param xfer LPUART DMA transfer structure. See #lpuart_transfer_t. + * @retval kStatus_Success if succeed, others failed. + * @retval kStatus_LPUART_TxBusy Previous transfer on going. + * @retval kStatus_InvalidArgument Invalid argument. + */ +status_t LPUART_TransferSendDMA(LPUART_Type *base, lpuart_dma_handle_t *handle, lpuart_transfer_t *xfer); + +/*! + * @brief Receives data using DMA. + * + * This function receives data using DMA. This is a non-blocking function, which returns + * right away. When all data is received, the receive callback function is called. + * + * @param base LPUART peripheral base address. + * @param handle Pointer to lpuart_dma_handle_t structure. + * @param xfer LPUART DMA transfer structure. See #lpuart_transfer_t. + * @retval kStatus_Success if succeed, others failed. + * @retval kStatus_LPUART_RxBusy Previous transfer on going. + * @retval kStatus_InvalidArgument Invalid argument. + */ +status_t LPUART_TransferReceiveDMA(LPUART_Type *base, lpuart_dma_handle_t *handle, lpuart_transfer_t *xfer); + +/*! + * @brief Aborts the sent data using DMA. + * + * This function aborts send data using DMA. + * + * @param base LPUART peripheral base address + * @param handle Pointer to lpuart_dma_handle_t structure + */ +void LPUART_TransferAbortSendDMA(LPUART_Type *base, lpuart_dma_handle_t *handle); + +/*! + * @brief Aborts the received data using DMA. + * + * This function aborts the received data using DMA. + * + * @param base LPUART peripheral base address + * @param handle Pointer to lpuart_dma_handle_t structure + */ +void LPUART_TransferAbortReceiveDMA(LPUART_Type *base, lpuart_dma_handle_t *handle); + +/*! + * @brief Gets the number of bytes written to the LPUART TX register. + * + * This function gets the number of bytes that have been written to LPUART TX + * register by DMA. + * + * @param base LPUART peripheral base address. + * @param handle LPUART handle pointer. + * @param count Send bytes count. + * @retval kStatus_NoTransferInProgress No send in progress. + * @retval kStatus_InvalidArgument Parameter is invalid. + * @retval kStatus_Success Get successfully through the parameter \p count; + */ +status_t LPUART_TransferGetSendCountDMA(LPUART_Type *base, lpuart_dma_handle_t *handle, uint32_t *count); + +/*! + * @brief Gets the number of received bytes. + * + * This function gets the number of received bytes. + * + * @param base LPUART peripheral base address. + * @param handle LPUART handle pointer. + * @param count Receive bytes count. + * @retval kStatus_NoTransferInProgress No receive in progress. + * @retval kStatus_InvalidArgument Parameter is invalid. + * @retval kStatus_Success Get successfully through the parameter \p count; + */ +status_t LPUART_TransferGetReceiveCountDMA(LPUART_Type *base, lpuart_dma_handle_t *handle, uint32_t *count); + +/*! + * @brief LPUART DMA IRQ handle function. + * + * This function handles the LPUART tx complete IRQ request and invoke user callback. + * @note This function is used as default IRQ handler by double weak mechanism. + * If user's specific IRQ handler is implemented, make sure this function is invoked in the handler. + * + * @param base LPUART peripheral base address. + * @param lpuartDmaHandle LPUART handle pointer. + */ +void LPUART_TransferDMAHandleIRQ(LPUART_Type *base, void *lpuartDmaHandle); + +/*! @} */ + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* FSL_LPUART_DMA_H_ */ diff --git a/bsp/nxp/imx/imx91/drivers/sdk/drivers/lpuart/fsl_lpuart_edma.c b/bsp/nxp/imx/imx91/drivers/sdk/drivers/lpuart/fsl_lpuart_edma.c new file mode 100644 index 00000000000..8c761a2feb9 --- /dev/null +++ b/bsp/nxp/imx/imx91/drivers/sdk/drivers/lpuart/fsl_lpuart_edma.c @@ -0,0 +1,469 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_lpuart_edma.h" +/* + * $Coverage Justification Reference$ + * + * $Justification fsl_lpuart_edma_c_ref_1$ + * The EDMA handle is only used by the LPUART EDMA driver, with the LPUART EDMA driver workflow, + * the callback is only called when EDMA transfer done. + * + * $Justification fsl_lpuart_edma_c_ref_2$ + * This function only handles the kLPUART_TransmissionCompleteFlag event. + * + */ +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.lpuart_edma" +#endif + +/*base, false); + + /* Stop transfer. */ + EDMA_AbortTransfer(handle); + + /* Enable tx complete interrupt */ + LPUART_EnableInterrupts(lpuartPrivateHandle->base, (uint32_t)kLPUART_TransmissionCompleteInterruptEnable); + } +} + +static void LPUART_ReceiveEDMACallback(edma_handle_t *handle, void *param, bool transferDone, uint32_t tcds) +{ + assert(NULL != param); + + lpuart_edma_private_handle_t *lpuartPrivateHandle = (lpuart_edma_private_handle_t *)param; + + /* Avoid warning for unused parameters. */ + handle = handle; + tcds = tcds; + /* + * $Branch Coverage Justification$ + * $ref fsl_lpuart_edma_c_ref_1$ + */ + if (transferDone) + { + /* Disable transfer. */ + LPUART_TransferAbortReceiveEDMA(lpuartPrivateHandle->base, lpuartPrivateHandle->handle); + + if (NULL != lpuartPrivateHandle->handle->callback) + { + lpuartPrivateHandle->handle->callback(lpuartPrivateHandle->base, lpuartPrivateHandle->handle, + kStatus_LPUART_RxIdle, lpuartPrivateHandle->handle->userData); + } + } +} + +/*! + * brief Initializes the LPUART handle which is used in transactional functions. + * + * note This function disables all LPUART interrupts. + * + * param base LPUART peripheral base address. + * param handle Pointer to lpuart_edma_handle_t structure. + * param callback Callback function. + * param userData User data. + * param txEdmaHandle User requested DMA handle for TX DMA transfer. + * param rxEdmaHandle User requested DMA handle for RX DMA transfer. + */ +void LPUART_TransferCreateHandleEDMA(LPUART_Type *base, + lpuart_edma_handle_t *handle, + lpuart_edma_transfer_callback_t callback, + void *userData, + edma_handle_t *txEdmaHandle, + edma_handle_t *rxEdmaHandle) +{ + assert(NULL != handle); + + uint32_t instance = LPUART_GetInstance(base); + + s_lpuartEdmaPrivateHandle[instance].base = base; + s_lpuartEdmaPrivateHandle[instance].handle = handle; + + (void)memset(handle, 0, sizeof(*handle)); + + handle->rxState = (uint8_t)kLPUART_RxIdle; + handle->txState = (uint8_t)kLPUART_TxIdle; + + handle->rxEdmaHandle = rxEdmaHandle; + handle->txEdmaHandle = txEdmaHandle; + + handle->callback = callback; + handle->userData = userData; + +#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO + /* Note: + Take care of the RX FIFO, EDMA request only assert when received bytes + equal or more than RX water mark, there is potential issue if RX water + mark larger than 1. + For example, if RX FIFO water mark is 2, upper layer needs 5 bytes and + 5 bytes are received. the last byte will be saved in FIFO but not trigger + EDMA transfer because the water mark is 2. + */ + if (NULL != rxEdmaHandle) + { + base->WATER &= (~LPUART_WATER_RXWATER_MASK); + } +#endif + + /* Save the handle in global variables to support the double weak mechanism. */ + s_lpuartHandle[instance] = handle; + /* Set LPUART_TransferEdmaHandleIRQ as DMA IRQ handler */ + s_lpuartIsr[instance] = LPUART_TransferEdmaHandleIRQ; + /* Disable all LPUART internal interrupts */ + LPUART_DisableInterrupts(base, (uint32_t)kLPUART_AllInterruptEnable); + /* Enable interrupt in NVIC. */ +#if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ + (void)EnableIRQ(s_lpuartTxIRQ[instance]); +#else + (void)EnableIRQ(s_lpuartIRQ[instance]); +#endif + + /* Configure TX. */ + if (NULL != txEdmaHandle) + { + EDMA_SetCallback(handle->txEdmaHandle, LPUART_SendEDMACallback, &s_lpuartEdmaPrivateHandle[instance]); + } + + /* Configure RX. */ + if (NULL != rxEdmaHandle) + { + EDMA_SetCallback(handle->rxEdmaHandle, LPUART_ReceiveEDMACallback, &s_lpuartEdmaPrivateHandle[instance]); + } +} + +/*! + * brief Sends data using eDMA. + * + * This function sends data using eDMA. This is a non-blocking function, which returns + * right away. When all data is sent, the send callback function is called. + * + * param base LPUART peripheral base address. + * param handle LPUART handle pointer. + * param xfer LPUART eDMA transfer structure. See #lpuart_transfer_t. + * retval kStatus_Success if succeed, others failed. + * retval kStatus_LPUART_TxBusy Previous transfer on going. + * retval kStatus_InvalidArgument Invalid argument. + */ +status_t LPUART_SendEDMA(LPUART_Type *base, lpuart_edma_handle_t *handle, lpuart_transfer_t *xfer) +{ + assert(NULL != handle); + assert(NULL != handle->txEdmaHandle); + assert(NULL != xfer); + assert(NULL != xfer->data); + assert(0U != xfer->dataSize); + + edma_transfer_config_t xferConfig; + status_t status; + + /* If previous TX not finished. */ + if ((uint8_t)kLPUART_TxBusy == handle->txState) + { + status = kStatus_LPUART_TxBusy; + } + else + { + handle->txState = (uint8_t)kLPUART_TxBusy; + handle->txDataSizeAll = xfer->dataSize; + + /* Prepare transfer. */ + EDMA_PrepareTransfer(&xferConfig, xfer->data, sizeof(uint8_t), + (void *)(uint32_t *)LPUART_GetDataRegisterAddress(base), sizeof(uint8_t), sizeof(uint8_t), + xfer->dataSize, kEDMA_MemoryToPeripheral); + + /* Store the initially configured eDMA minor byte transfer count into the LPUART handle */ + handle->nbytes = (uint8_t)sizeof(uint8_t); + + /* Submit transfer. */ + if (kStatus_Success != + EDMA_SubmitTransfer(handle->txEdmaHandle, (const edma_transfer_config_t *)(uint32_t)&xferConfig)) + { + return kStatus_Fail; + } + EDMA_StartTransfer(handle->txEdmaHandle); + + /* Enable LPUART TX EDMA. */ + LPUART_EnableTxDMA(base, true); + + status = kStatus_Success; + } + + return status; +} + +/*! + * brief Receives data using eDMA. + * + * This function receives data using eDMA. This is non-blocking function, which returns + * right away. When all data is received, the receive callback function is called. + * + * param base LPUART peripheral base address. + * param handle Pointer to lpuart_edma_handle_t structure. + * param xfer LPUART eDMA transfer structure, see #lpuart_transfer_t. + * retval kStatus_Success if succeed, others fail. + * retval kStatus_LPUART_RxBusy Previous transfer ongoing. + * retval kStatus_InvalidArgument Invalid argument. + */ +status_t LPUART_ReceiveEDMA(LPUART_Type *base, lpuart_edma_handle_t *handle, lpuart_transfer_t *xfer) +{ + assert(NULL != handle); + assert(NULL != handle->rxEdmaHandle); + assert(NULL != xfer); + assert(NULL != xfer->data); + assert(0U != xfer->dataSize); + + edma_transfer_config_t xferConfig; + status_t status; + + /* If previous RX not finished. */ + if ((uint8_t)kLPUART_RxBusy == handle->rxState) + { + status = kStatus_LPUART_RxBusy; + } + else + { + handle->rxState = (uint8_t)kLPUART_RxBusy; + handle->rxDataSizeAll = xfer->dataSize; + + /* Prepare transfer. */ + EDMA_PrepareTransfer(&xferConfig, (void *)(uint32_t *)LPUART_GetDataRegisterAddress(base), sizeof(uint8_t), + xfer->data, sizeof(uint8_t), sizeof(uint8_t), xfer->dataSize, kEDMA_PeripheralToMemory); + + /* Store the initially configured eDMA minor byte transfer count into the LPUART handle */ + handle->nbytes = (uint8_t)sizeof(uint8_t); + + /* Submit transfer. */ + if (kStatus_Success != + EDMA_SubmitTransfer(handle->rxEdmaHandle, (const edma_transfer_config_t *)(uint32_t)&xferConfig)) + { + return kStatus_Fail; + } + EDMA_StartTransfer(handle->rxEdmaHandle); + + /* Enable LPUART RX EDMA. */ + LPUART_EnableRxDMA(base, true); + + status = kStatus_Success; + } + + return status; +} + +/*! + * brief Aborts the sent data using eDMA. + * + * This function aborts the sent data using eDMA. + * + * param base LPUART peripheral base address. + * param handle Pointer to lpuart_edma_handle_t structure. + */ +void LPUART_TransferAbortSendEDMA(LPUART_Type *base, lpuart_edma_handle_t *handle) +{ + assert(NULL != handle); + assert(NULL != handle->txEdmaHandle); + + /* Disable LPUART TX EDMA. */ + LPUART_EnableTxDMA(base, false); + + /* Stop transfer. */ + EDMA_AbortTransfer(handle->txEdmaHandle); + + handle->txState = (uint8_t)kLPUART_TxIdle; +} + +/*! + * brief Aborts the received data using eDMA. + * + * This function aborts the received data using eDMA. + * + * param base LPUART peripheral base address. + * param handle Pointer to lpuart_edma_handle_t structure. + */ +void LPUART_TransferAbortReceiveEDMA(LPUART_Type *base, lpuart_edma_handle_t *handle) +{ + assert(NULL != handle); + assert(NULL != handle->rxEdmaHandle); + + /* Disable LPUART RX EDMA. */ + LPUART_EnableRxDMA(base, false); + + /* Stop transfer. */ + EDMA_AbortTransfer(handle->rxEdmaHandle); + + handle->rxState = (uint8_t)kLPUART_RxIdle; +} + +/*! + * brief Gets the number of received bytes. + * + * This function gets the number of received bytes. + * + * param base LPUART peripheral base address. + * param handle LPUART handle pointer. + * param count Receive bytes count. + * retval kStatus_NoTransferInProgress No receive in progress. + * retval kStatus_InvalidArgument Parameter is invalid. + * retval kStatus_Success Get successfully through the parameter \p count; + */ +status_t LPUART_TransferGetReceiveCountEDMA(LPUART_Type *base, lpuart_edma_handle_t *handle, uint32_t *count) +{ + assert(NULL != handle); + assert(NULL != handle->rxEdmaHandle); + assert(NULL != count); + + if ((uint8_t)kLPUART_RxIdle == handle->rxState) + { + return kStatus_NoTransferInProgress; + } + + *count = handle->rxDataSizeAll - + ((uint32_t)handle->nbytes * + EDMA_GetRemainingMajorLoopCount(handle->rxEdmaHandle->base, handle->rxEdmaHandle->channel)); + + return kStatus_Success; +} + +/*! + * brief Gets the number of bytes written to the LPUART TX register. + * + * This function gets the number of bytes written to the LPUART TX + * register by DMA. + * + * param base LPUART peripheral base address. + * param handle LPUART handle pointer. + * param count Send bytes count. + * retval kStatus_NoTransferInProgress No send in progress. + * retval kStatus_InvalidArgument Parameter is invalid. + * retval kStatus_Success Get successfully through the parameter \p count; + */ +status_t LPUART_TransferGetSendCountEDMA(LPUART_Type *base, lpuart_edma_handle_t *handle, uint32_t *count) +{ + assert(NULL != handle); + assert(NULL != handle->txEdmaHandle); + assert(NULL != count); + + if ((uint8_t)kLPUART_TxIdle == handle->txState) + { + return kStatus_NoTransferInProgress; + } + + *count = handle->txDataSizeAll - + ((uint32_t)handle->nbytes * + EDMA_GetRemainingMajorLoopCount(handle->txEdmaHandle->base, handle->txEdmaHandle->channel)); + + return kStatus_Success; +} + +/*! + * brief LPUART eDMA IRQ handle function. + * + * This function handles the LPUART tx complete IRQ request and invoke user callback. + * It is not set to static so that it can be used in user application. + * note This function is used as default IRQ handler by double weak mechanism. + * If user's specific IRQ handler is implemented, make sure this function is invoked in the handler. + * + * param base LPUART peripheral base address. + * param lpuartEdmaHandle LPUART handle pointer. + */ +void LPUART_TransferEdmaHandleIRQ(LPUART_Type *base, void *lpuartEdmaHandle) +{ + assert(lpuartEdmaHandle != NULL); + /* + * $Branch Coverage Justification$ + * $ref fsl_lpuart_edma_c_ref_2$ + */ + if (((uint32_t)kLPUART_TransmissionCompleteFlag & LPUART_GetStatusFlags(base)) != 0U) + { + lpuart_edma_handle_t *handle = (lpuart_edma_handle_t *)lpuartEdmaHandle; + + /* Disable tx complete interrupt */ + LPUART_DisableInterrupts(base, (uint32_t)kLPUART_TransmissionCompleteInterruptEnable); + + handle->txState = (uint8_t)kLPUART_TxIdle; + + if (handle->callback != NULL) + { + handle->callback(base, handle, kStatus_LPUART_TxIdle, handle->userData); + } + } +} diff --git a/bsp/nxp/imx/imx91/drivers/sdk/drivers/lpuart/fsl_lpuart_edma.h b/bsp/nxp/imx/imx91/drivers/sdk/drivers/lpuart/fsl_lpuart_edma.h new file mode 100644 index 00000000000..1190ed36e86 --- /dev/null +++ b/bsp/nxp/imx/imx91/drivers/sdk/drivers/lpuart/fsl_lpuart_edma.h @@ -0,0 +1,189 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef FSL_LPUART_EDMA_H_ +#define FSL_LPUART_EDMA_H_ + +#include "fsl_lpuart.h" +#include "fsl_edma.h" + +/*! + * @addtogroup lpuart_edma_driver + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*! @{ */ +/*! @brief LPUART EDMA driver version. */ +#define FSL_LPUART_EDMA_DRIVER_VERSION (MAKE_VERSION(2, 6, 0)) +/*! @} */ + +/* Forward declaration of the handle typedef. */ +typedef struct _lpuart_edma_handle lpuart_edma_handle_t; + +/*! @brief LPUART transfer callback function. */ +typedef void (*lpuart_edma_transfer_callback_t)(LPUART_Type *base, + lpuart_edma_handle_t *handle, + status_t status, + void *userData); + +/*! + * @brief LPUART eDMA handle + */ +struct _lpuart_edma_handle +{ + lpuart_edma_transfer_callback_t callback; /*!< Callback function. */ + void *userData; /*!< LPUART callback function parameter.*/ + size_t rxDataSizeAll; /*!< Size of the data to receive. */ + size_t txDataSizeAll; /*!< Size of the data to send out. */ + + edma_handle_t *txEdmaHandle; /*!< The eDMA TX channel used. */ + edma_handle_t *rxEdmaHandle; /*!< The eDMA RX channel used. */ + + uint8_t nbytes; /*!< eDMA minor byte transfer count initially configured. */ + + volatile uint8_t txState; /*!< TX transfer state. */ + volatile uint8_t rxState; /*!< RX transfer state */ +}; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name eDMA transactional + * @{ + */ + +/*! + * @brief Initializes the LPUART handle which is used in transactional functions. + * + * @note This function disables all LPUART interrupts. + * + * @param base LPUART peripheral base address. + * @param handle Pointer to lpuart_edma_handle_t structure. + * @param callback Callback function. + * @param userData User data. + * @param txEdmaHandle User requested DMA handle for TX DMA transfer. + * @param rxEdmaHandle User requested DMA handle for RX DMA transfer. + */ +void LPUART_TransferCreateHandleEDMA(LPUART_Type *base, + lpuart_edma_handle_t *handle, + lpuart_edma_transfer_callback_t callback, + void *userData, + edma_handle_t *txEdmaHandle, + edma_handle_t *rxEdmaHandle); + +/*! + * @brief Sends data using eDMA. + * + * This function sends data using eDMA. This is a non-blocking function, which returns + * right away. When all data is sent, the send callback function is called. + * + * @param base LPUART peripheral base address. + * @param handle LPUART handle pointer. + * @param xfer LPUART eDMA transfer structure. See #lpuart_transfer_t. + * @retval kStatus_Success if succeed, others failed. + * @retval kStatus_LPUART_TxBusy Previous transfer on going. + * @retval kStatus_InvalidArgument Invalid argument. + */ +status_t LPUART_SendEDMA(LPUART_Type *base, lpuart_edma_handle_t *handle, lpuart_transfer_t *xfer); + +/*! + * @brief Receives data using eDMA. + * + * This function receives data using eDMA. This is non-blocking function, which returns + * right away. When all data is received, the receive callback function is called. + * + * @param base LPUART peripheral base address. + * @param handle Pointer to lpuart_edma_handle_t structure. + * @param xfer LPUART eDMA transfer structure, see #lpuart_transfer_t. + * @retval kStatus_Success if succeed, others fail. + * @retval kStatus_LPUART_RxBusy Previous transfer ongoing. + * @retval kStatus_InvalidArgument Invalid argument. + */ +status_t LPUART_ReceiveEDMA(LPUART_Type *base, lpuart_edma_handle_t *handle, lpuart_transfer_t *xfer); + +/*! + * @brief Aborts the sent data using eDMA. + * + * This function aborts the sent data using eDMA. + * + * @param base LPUART peripheral base address. + * @param handle Pointer to lpuart_edma_handle_t structure. + */ +void LPUART_TransferAbortSendEDMA(LPUART_Type *base, lpuart_edma_handle_t *handle); + +/*! + * @brief Aborts the received data using eDMA. + * + * This function aborts the received data using eDMA. + * + * @param base LPUART peripheral base address. + * @param handle Pointer to lpuart_edma_handle_t structure. + */ +void LPUART_TransferAbortReceiveEDMA(LPUART_Type *base, lpuart_edma_handle_t *handle); + +/*! + * @brief Gets the number of bytes written to the LPUART TX register. + * + * This function gets the number of bytes written to the LPUART TX + * register by DMA. + * + * @param base LPUART peripheral base address. + * @param handle LPUART handle pointer. + * @param count Send bytes count. + * @retval kStatus_NoTransferInProgress No send in progress. + * @retval kStatus_InvalidArgument Parameter is invalid. + * @retval kStatus_Success Get successfully through the parameter \p count; + */ +status_t LPUART_TransferGetSendCountEDMA(LPUART_Type *base, lpuart_edma_handle_t *handle, uint32_t *count); + +/*! + * @brief Gets the number of received bytes. + * + * This function gets the number of received bytes. + * + * @param base LPUART peripheral base address. + * @param handle LPUART handle pointer. + * @param count Receive bytes count. + * @retval kStatus_NoTransferInProgress No receive in progress. + * @retval kStatus_InvalidArgument Parameter is invalid. + * @retval kStatus_Success Get successfully through the parameter \p count; + */ +status_t LPUART_TransferGetReceiveCountEDMA(LPUART_Type *base, lpuart_edma_handle_t *handle, uint32_t *count); + +/*! + * @brief LPUART eDMA IRQ handle function. + * + * This function handles the LPUART tx complete IRQ request and invoke user callback. + * It is not set to static so that it can be used in user application. + * @note This function is used as default IRQ handler by double weak mechanism. + * If user's specific IRQ handler is implemented, make sure this function is invoked in the handler. + * + * @param base LPUART peripheral base address. + * @param lpuartEdmaHandle LPUART handle pointer. + */ +void LPUART_TransferEdmaHandleIRQ(LPUART_Type *base, void *lpuartEdmaHandle); + +/*! @} */ + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* FSL_LPUART_EDMA_H_ */ diff --git a/bsp/nxp/imx/imx91/drivers/sdk/drivers/rgpio/SConscript b/bsp/nxp/imx/imx91/drivers/sdk/drivers/rgpio/SConscript new file mode 100644 index 00000000000..3f8f39acae7 --- /dev/null +++ b/bsp/nxp/imx/imx91/drivers/sdk/drivers/rgpio/SConscript @@ -0,0 +1,17 @@ +# for module compiling +import os +from building import * + +cwd = GetCurrentDir() + +src = Glob('*.c') + +CPPPATH = [cwd] +objs = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH) + +for item in os.listdir(cwd): + sconsfile = os.path.join(item, 'SConscript') + if os.path.isfile(os.path.join(cwd, sconsfile)): + objs += SConscript(sconsfile) + +Return('objs') diff --git a/bsp/nxp/imx/imx91/drivers/sdk/drivers/rgpio/fsl_rgpio.c b/bsp/nxp/imx/imx91/drivers/sdk/drivers/rgpio/fsl_rgpio.c new file mode 100644 index 00000000000..aa946a35bd2 --- /dev/null +++ b/bsp/nxp/imx/imx91/drivers/sdk/drivers/rgpio/fsl_rgpio.c @@ -0,0 +1,322 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_rgpio.h" + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.rgpio" +#endif + +/******************************************************************************* + * Variables + ******************************************************************************/ +#if defined(FSL_FEATURE_SOC_PORT_COUNT) && FSL_FEATURE_SOC_PORT_COUNT +static PORT_Type *const s_portBases[] = PORT_BASE_PTRS; +#endif /* FSL_FEATURE_SOC_PORT_COUNT */ + +static RGPIO_Type *const s_rgpioBases[] = RGPIO_BASE_PTRS; + +#if defined(FSL_FEATURE_SOC_FGPIO_COUNT) && FSL_FEATURE_SOC_FGPIO_COUNT + +#if defined(FSL_FEATURE_PCC_HAS_FGPIO_CLOCK_GATE_CONTROL) && FSL_FEATURE_PCC_HAS_FGPIO_CLOCK_GATE_CONTROL + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/*! @brief Array to map FGPIO instance number to clock name. */ +static const clock_ip_name_t s_fgpioClockName[] = FGPIO_CLOCKS; +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +#endif /* FSL_FEATURE_PCC_HAS_FGPIO_CLOCK_GATE_CONTROL */ + +#endif /* FSL_FEATURE_SOC_FGPIO_COUNT */ + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ + +/*! + * brief Gets the RGPIO instance according to the RGPIO base + * + * param base RGPIO peripheral base pointer(PTA, PTB, PTC, etc.) + * retval RGPIO instance + */ +uint32_t RGPIO_GetInstance(RGPIO_Type *base) +{ + uint32_t instance; + + /* Find the instance index from base address mappings. */ + for (instance = 0U; instance < ARRAY_SIZE(s_rgpioBases); instance++) + { + if (MSDK_REG_SECURE_ADDR(s_rgpioBases[instance]) == MSDK_REG_SECURE_ADDR(base)) + { + break; + } + } + + assert(instance < ARRAY_SIZE(s_rgpioBases)); + + return instance; +} + +/*! + * brief Initializes a RGPIO pin used by the board. + * + * To initialize the RGPIO, define a pin configuration, as either input or output, in the user file. + * Then, call the RGPIO_PinInit() function. + * + * This is an example to define an input pin or an output pin configuration. + * code + * Define a digital input pin configuration, + * rgpio_pin_config_t config = + * { + * kRGPIO_DigitalInput, + * 0, + * } + * Define a digital output pin configuration, + * rgpio_pin_config_t config = + * { + * kRGPIO_DigitalOutput, + * 0, + * } + * endcode + * + * param base RGPIO peripheral base pointer (RGPIOA, RGPIOB, RGPIOC, and so on.) + * param pin RGPIO port pin number + * param config RGPIO pin configuration pointer + */ +void RGPIO_PinInit(RGPIO_Type *base, uint32_t pin, const rgpio_pin_config_t *config) +{ + assert(NULL != config); + + if (config->pinDirection == kRGPIO_DigitalInput) + { + base->PDDR &= ~(1UL << pin); + } + else + { + RGPIO_WritePinOutput(base, pin, config->outputLogic); + base->PDDR |= (1UL << pin); + } +} + +#if defined(FSL_FEATURE_SOC_PORT_COUNT) && FSL_FEATURE_SOC_PORT_COUNT +/*! + * brief Reads the RGPIO port interrupt status flag. + * + * If a pin is configured to generate the DMA request, the corresponding flag + * is cleared automatically at the completion of the requested DMA transfer. + * Otherwise, the flag remains set until a logic one is written to that flag. + * If configured for a level sensitive interrupt that remains asserted, the flag + * is set again immediately. + * + * param base RGPIO peripheral base pointer (RGPIOA, RGPIOB, RGPIOC, and so on.) + * retval The current RGPIO port interrupt status flag, for example, 0x00010001 means the + * pin 0 and 17 have the interrupt. + */ +uint32_t RGPIO_PortGetInterruptFlags(RGPIO_Type *base) +{ + uint8_t instance; + PORT_Type *portBase; + instance = RGPIO_GetInstance(base); + portBase = s_portBases[instance]; + return portBase->ISFR; +} + +/*! + * brief Clears multiple RGPIO pin interrupt status flags. + * + * param base RGPIO peripheral base pointer (RGPIOA, RGPIOB, RGPIOC, and so on.) + * param mask RGPIO pin number macro + */ +void RGPIO_PortClearInterruptFlags(RGPIO_Type *base, uint32_t mask) +{ + uint8_t instance; + PORT_Type *portBase; + instance = RGPIO_GetInstance(base); + portBase = s_portBases[instance]; + portBase->ISFR = mask; +} +#endif /* FSL_FEATURE_SOC_PORT_COUNT */ + +#if defined(FSL_FEATURE_RGPIO_HAS_ATTRIBUTE_CHECKER) && FSL_FEATURE_RGPIO_HAS_ATTRIBUTE_CHECKER +/*! + * brief The RGPIO module supports a device-specific number of data ports, organized as 32-bit + * words. Each 32-bit data port includes a GACR register, which defines the byte-level + * attributes required for a successful access to the RGPIO programming model. The attribute controls for the 4 data + * bytes in the GACR follow a standard little endian + * data convention. + * + * param base RGPIO peripheral base pointer (RGPIOA, RGPIOB, RGPIOC, and so on.) + * param mask RGPIO pin number macro + */ +void RGPIO_CheckAttributeBytes(RGPIO_Type *base, rgpio_checker_attribute_t attribute) +{ + base->GACR = ((uint32_t)attribute << RGPIO_GACR_ACB0_SHIFT) | ((uint32_t)attribute << RGPIO_GACR_ACB1_SHIFT) | + ((uint32_t)attribute << RGPIO_GACR_ACB2_SHIFT) | ((uint32_t)attribute << RGPIO_GACR_ACB3_SHIFT); +} +#endif + +#if defined(FSL_FEATURE_SOC_FGPIO_COUNT) && FSL_FEATURE_SOC_FGPIO_COUNT + +/******************************************************************************* + * Variables + ******************************************************************************/ +static FGPIO_Type *const s_fgpioBases[] = FGPIO_BASE_PTRS; + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ + +/*! + * brief Gets the FGPIO instance according to the RGPIO base + * + * param base FGPIO peripheral base pointer(PTA, PTB, PTC, etc.) + * retval FGPIO instance + */ +uint32_t FGPIO_GetInstance(FGPIO_Type *base) +{ + uint32_t instance; + + /* Find the instance index from base address mappings. */ + for (instance = 0U; instance < ARRAY_SIZE(s_fgpioBases); instance++) + { + if (MSDK_REG_SECURE_ADDR(s_fgpioBases[instance]) == MSDK_REG_SECURE_ADDR(base)) + { + break; + } + } + + assert(instance < ARRAY_SIZE(s_fgpioBases)); + + return instance; +} + +#if defined(FSL_FEATURE_PCC_HAS_FGPIO_CLOCK_GATE_CONTROL) && FSL_FEATURE_PCC_HAS_FGPIO_CLOCK_GATE_CONTROL +void FGPIO_PortInit(FGPIO_Type *base) +{ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Ungate FGPIO periphral clock */ + CLOCK_EnableClock(s_fgpioClockName[FGPIO_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} +#endif /* FSL_FEATURE_PCC_HAS_FGPIO_CLOCK_GATE_CONTROL */ + +/*! + * brief Initializes a FGPIO pin used by the board. + * + * To initialize the FGPIO driver, define a pin configuration, as either input or output, in the user file. + * Then, call the FGPIO_PinInit() function. + * + * This is an example to define an input pin or an output pin configuration: + * code + * Define a digital input pin configuration, + * rgpio_pin_config_t config = + * { + * kRGPIO_DigitalInput, + * 0, + * } + * Define a digital output pin configuration, + * rgpio_pin_config_t config = + * { + * kRGPIO_DigitalOutput, + * 0, + * } + * endcode + * + * param base FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.) + * param pin FGPIO port pin number + * param config FGPIO pin configuration pointer + */ +void FGPIO_PinInit(FGPIO_Type *base, uint32_t pin, const rgpio_pin_config_t *config) +{ + assert(NULL != config); + +#if defined(FSL_FEATURE_PCC_HAS_FGPIO_CLOCK_GATE_CONTROL) && FSL_FEATURE_PCC_HAS_FGPIO_CLOCK_GATE_CONTROL +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Ungate FGPIO periphral clock */ + CLOCK_EnableClock(s_fgpioClockName[FGPIO_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +#endif /* FSL_FEATURE_PCC_HAS_FGPIO_CLOCK_GATE_CONTROL */ + + if (config->pinDirection == kRGPIO_DigitalInput) + { + base->PDDR &= ~(1UL << pin); + } + else + { + FGPIO_WritePinOutput(base, pin, config->outputLogic); + base->PDDR |= (1UL << pin); + } +} + +#if defined(FSL_FEATURE_SOC_PORT_COUNT) && FSL_FEATURE_SOC_PORT_COUNT +/*! + * brief Reads the FGPIO port interrupt status flag. + * + * If a pin is configured to generate the DMA request, the corresponding flag + * is cleared automatically at the completion of the requested DMA transfer. + * Otherwise, the flag remains set until a logic one is written to that flag. + * If configured for a level-sensitive interrupt that remains asserted, the flag + * is set again immediately. + * + * param base FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.) + * retval The current FGPIO port interrupt status flags, for example, 0x00010001 means the + * pin 0 and 17 have the interrupt. + */ +uint32_t FGPIO_PortGetInterruptFlags(FGPIO_Type *base) +{ + uint8_t instance; + instance = FGPIO_GetInstance(base); + PORT_Type *portBase; + portBase = s_portBases[instance]; + return portBase->ISFR; +} + +/*! + * brief Clears the multiple FGPIO pin interrupt status flag. + * + * param base FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.) + * param mask FGPIO pin number macro + */ +void FGPIO_PortClearInterruptFlags(FGPIO_Type *base, uint32_t mask) +{ + uint8_t instance; + instance = FGPIO_GetInstance(base); + PORT_Type *portBase; + portBase = s_portBases[instance]; + portBase->ISFR = mask; +} +#endif /* FSL_FEATURE_SOC_PORT_COUNT */ + +#if defined(FSL_FEATURE_FGPIO_HAS_ATTRIBUTE_CHECKER) && FSL_FEATURE_FGPIO_HAS_ATTRIBUTE_CHECKER +/*! + * brief The FGPIO module supports a device-specific number of data ports, organized as 32-bit + * words. Each 32-bit data port includes a GACR register, which defines the byte-level + * attributes required for a successful access to the RGPIO programming model. The attribute controls for the 4 data + * bytes in the GACR follow a standard little endian + * data convention. + * + * param base FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.) + * param mask FGPIO pin number macro + */ +void FGPIO_CheckAttributeBytes(FGPIO_Type *base, rgpio_checker_attribute_t attribute) +{ + base->GACR = (attribute << FGPIO_GACR_ACB0_SHIFT) | (attribute << FGPIO_GACR_ACB1_SHIFT) | + (attribute << FGPIO_GACR_ACB2_SHIFT) | (attribute << FGPIO_GACR_ACB3_SHIFT); +} +#endif + +#endif /* FSL_FEATURE_SOC_FGPIO_COUNT */ diff --git a/bsp/nxp/imx/imx91/drivers/sdk/drivers/rgpio/fsl_rgpio.h b/bsp/nxp/imx/imx91/drivers/sdk/drivers/rgpio/fsl_rgpio.h new file mode 100644 index 00000000000..2241e6a17c0 --- /dev/null +++ b/bsp/nxp/imx/imx91/drivers/sdk/drivers/rgpio/fsl_rgpio.h @@ -0,0 +1,708 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017, 2020-2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef FSL_RGPIO_H_ +#define FSL_RGPIO_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup rgpio + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*! @{ */ +/*! @brief RGPIO driver version 2.1.0. */ +#define FSL_RGPIO_DRIVER_VERSION (MAKE_VERSION(2, 1, 0)) +/*! @} */ + +/*! @brief RGPIO direction definition */ +typedef enum _rgpio_pin_direction +{ + kRGPIO_DigitalInput = 0U, /*!< Set current pin as digital input*/ + kRGPIO_DigitalOutput = 1U, /*!< Set current pin as digital output*/ +} rgpio_pin_direction_t; + +#if defined(FSL_FEATURE_RGPIO_HAS_ATTRIBUTE_CHECKER) && FSL_FEATURE_RGPIO_HAS_ATTRIBUTE_CHECKER +/*! @brief RGPIO checker attribute */ +typedef enum _rgpio_checker_attribute +{ + kRGPIO_UsernonsecureRWUsersecureRWPrivilegedsecureRW = + 0x00U, /*!< User nonsecure:Read+Write; User Secure:Read+Write; Privileged Secure:Read+Write */ + kRGPIO_UsernonsecureRUsersecureRWPrivilegedsecureRW = + 0x01U, /*!< User nonsecure:Read; User Secure:Read+Write; Privileged Secure:Read+Write */ + kRGPIO_UsernonsecureNUsersecureRWPrivilegedsecureRW = + 0x02U, /*!< User nonsecure:None; User Secure:Read+Write; Privileged Secure:Read+Write */ + kRGPIO_UsernonsecureRUsersecureRPrivilegedsecureRW = + 0x03U, /*!< User nonsecure:Read; User Secure:Read; Privileged Secure:Read+Write */ + kRGPIO_UsernonsecureNUsersecureRPrivilegedsecureRW = + 0x04U, /*!< User nonsecure:None; User Secure:Read; Privileged Secure:Read+Write */ + kRGPIO_UsernonsecureNUsersecureNPrivilegedsecureRW = + 0x05U, /*!< User nonsecure:None; User Secure:None; Privileged Secure:Read+Write */ + kRGPIO_UsernonsecureNUsersecureNPrivilegedsecureR = + 0x06U, /*!< User nonsecure:None; User Secure:None; Privileged Secure:Read */ + kRGPIO_UsernonsecureNUsersecureNPrivilegedsecureN = + 0x07U, /*!< User nonsecure:None; User Secure:None; Privileged Secure:None */ + kRGPIO_IgnoreAttributeCheck = 0x80U, /*!< Ignores the attribute check */ +} rgpio_checker_attribute_t; +#endif + +#if defined(FSL_FEATURE_RGPIO_HAS_IRQ_CONFIG) && FSL_FEATURE_RGPIO_HAS_IRQ_CONFIG +/*! @brief Configures the interrupt generation condition. */ +typedef enum _rgpio_interrupt_sel +{ + kRGPIO_InterruptOutput0 = 0x0U, /*!< Interrupt/DMA request/trigger output 0. */ + kRGPIO_InterruptOutput1 = 0x1U, /*!< Interrupt/DMA request/trigger output 1. */ + kRGPIO_InterruptOutput2 = 0x2U, /*!< Interrupt/DMA request/trigger output 2. */ + kRGPIO_InterruptOutput3 = 0x3U, /*!< Interrupt/DMA request/trigger output 3. */ +} rgpio_interrupt_sel_t; + +/*! @brief Configures the interrupt generation condition. */ +typedef enum _rgpio_interrupt_config +{ + kRGPIO_InterruptOrDMADisabled = 0x0U, /*!< Interrupt/DMA request is disabled. */ + kRGPIO_DMARisingEdge = 0x1U, /*!< DMA request on rising edge. */ + kRGPIO_DMAFallingEdge = 0x2U, /*!< DMA request on falling edge. */ + kRGPIO_DMAEitherEdge = 0x3U, /*!< DMA request on either edge. */ + kRGPIO_FlagRisingEdge = 0x05U, /*!< Flag sets on rising edge. */ + kRGPIO_FlagFallingEdge = 0x06U, /*!< Flag sets on falling edge. */ + kRGPIO_FlagEitherEdge = 0x07U, /*!< Flag sets on either edge. */ + kRGPIO_InterruptLogicZero = 0x8U, /*!< Interrupt when logic zero. */ + kRGPIO_InterruptRisingEdge = 0x9U, /*!< Interrupt on rising edge. */ + kRGPIO_InterruptFallingEdge = 0xAU, /*!< Interrupt on falling edge. */ + kRGPIO_InterruptEitherEdge = 0xBU, /*!< Interrupt on either edge. */ + kRGPIO_InterruptLogicOne = 0xCU, /*!< Interrupt when logic one. */ + kRGPIO_ActiveHighTriggerOutputEnable = 0xDU, /*!< Enable active high-trigger output. */ + kRGPIO_ActiveLowTriggerOutputEnable = 0xEU, /*!< Enable active low-trigger output. */ +} rgpio_interrupt_config_t; +#endif + +/*! + * @brief The RGPIO pin configuration structure. + * + * Each pin can only be configured as either an output pin or an input pin at a time. + * If configured as an input pin, leave the outputConfig unused. + * Note that in some use cases, the corresponding port property should be configured in advance + * with the PORT_SetPinConfig(). + */ +typedef struct _rgpio_pin_config +{ + rgpio_pin_direction_t pinDirection; /*!< RGPIO direction, input or output */ + /* Output configurations; ignore if configured as an input pin */ + uint8_t outputLogic; /*!< Set a default output logic, which has no use in input */ +} rgpio_pin_config_t; + +/*! @} */ + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @addtogroup rgpio_driver + * @{ + */ + +/*! @name RGPIO Configuration */ +/*! @{ */ + +/*! + * @brief Initializes a RGPIO pin used by the board. + * + * To initialize the RGPIO, define a pin configuration, as either input or output, in the user file. + * Then, call the RGPIO_PinInit() function. + * + * This is an example to define an input pin or an output pin configuration. + * @code + * Define a digital input pin configuration, + * rgpio_pin_config_t config = + * { + * kRGPIO_DigitalInput, + * 0, + * } + * Define a digital output pin configuration, + * rgpio_pin_config_t config = + * { + * kRGPIO_DigitalOutput, + * 0, + * } + * @endcode + * + * @param base RGPIO peripheral base pointer (RGPIOA, RGPIOB, RGPIOC, and so on.) + * @param pin RGPIO port pin number + * @param config RGPIO pin configuration pointer + */ +void RGPIO_PinInit(RGPIO_Type *base, uint32_t pin, const rgpio_pin_config_t *config); + +/*! + * @brief Gets the RGPIO instance according to the RGPIO base + * + * @param base RGPIO peripheral base pointer(PTA, PTB, PTC, etc.) + * @retval RGPIO instance + */ +uint32_t RGPIO_GetInstance(RGPIO_Type *base); +/*! @} */ + +/*! @name RGPIO Output Operations */ +/*! @{ */ + +/*! + * @brief Sets the output level of the multiple RGPIO pins to the logic 1 or 0. + * + * @param base RGPIO peripheral base pointer (RGPIOA, RGPIOB, RGPIOC, and so on.) + * @param pin RGPIO pin number + * @param output RGPIO pin output logic level. + * - 0: corresponding pin output low-logic level. + * - 1: corresponding pin output high-logic level. + */ +static inline void RGPIO_PinWrite(RGPIO_Type *base, uint32_t pin, uint8_t output) +{ + if (output == 0U) + { + base->PCOR = 1UL << pin; + } + else + { + base->PSOR = 1UL << pin; + } +} + +/*! + * @brief Sets the output level of the multiple RGPIO pins to the logic 1 or 0. + * @deprecated Do not use this function. It has been superceded by @ref RGPIO_PinWrite. + */ +static inline void RGPIO_WritePinOutput(RGPIO_Type *base, uint32_t pin, uint8_t output) +{ + RGPIO_PinWrite(base, pin, output); +} + +/*! + * @brief Sets the output level of the multiple RGPIO pins to the logic 1. + * + * @param base RGPIO peripheral base pointer (RGPIOA, RGPIOB, RGPIOC, and so on.) + * @param mask RGPIO pin number macro + */ +static inline void RGPIO_PortSet(RGPIO_Type *base, uint32_t mask) +{ + base->PSOR = mask; +} + +/*! + * @brief Sets the output level of the multiple RGPIO pins to the logic 1. + * @deprecated Do not use this function. It has been superceded by @ref RGPIO_PortSet. + */ +static inline void RGPIO_SetPinsOutput(RGPIO_Type *base, uint32_t mask) +{ + RGPIO_PortSet(base, mask); +} + +/*! + * @brief Sets the output level of the multiple RGPIO pins to the logic 0. + * + * @param base RGPIO peripheral base pointer (RGPIOA, RGPIOB, RGPIOC, and so on.) + * @param mask RGPIO pin number macro + */ +static inline void RGPIO_PortClear(RGPIO_Type *base, uint32_t mask) +{ + base->PCOR = mask; +} + +/*! + * @brief Sets the output level of the multiple RGPIO pins to the logic 0. + * @deprecated Do not use this function. It has been superceded by @ref RGPIO_PortClear. + * + * @param base RGPIO peripheral base pointer (RGPIOA, RGPIOB, RGPIOC, and so on.) + * @param mask RGPIO pin number macro + */ +static inline void RGPIO_ClearPinsOutput(RGPIO_Type *base, uint32_t mask) +{ + RGPIO_PortClear(base, mask); +} + +/*! + * @brief Reverses the current output logic of the multiple RGPIO pins. + * + * @param base RGPIO peripheral base pointer (RGPIOA, RGPIOB, RGPIOC, and so on.) + * @param mask RGPIO pin number macro + */ +static inline void RGPIO_PortToggle(RGPIO_Type *base, uint32_t mask) +{ + base->PTOR = mask; +} + +/*! + * @brief Reverses the current output logic of the multiple RGPIO pins. + * @deprecated Do not use this function. It has been superceded by @ref RGPIO_PortToggle. + */ +static inline void RGPIO_TogglePinsOutput(RGPIO_Type *base, uint32_t mask) +{ + RGPIO_PortToggle(base, mask); +} +/*! @} */ + +/*! @name RGPIO Input Operations */ +/*! @{ */ + +/*! + * @brief Reads the current input value of the RGPIO port. + * + * @param base RGPIO peripheral base pointer (RGPIOA, RGPIOB, RGPIOC, and so on.) + * @param pin RGPIO pin number + * @retval RGPIO port input value + * - 0: corresponding pin input low-logic level. + * - 1: corresponding pin input high-logic level. + */ +static inline uint32_t RGPIO_PinRead(RGPIO_Type *base, uint32_t pin) +{ + return (((base->PDIR) >> pin) & 0x01U); +} + +/*! + * @brief Reads the current input value of the RGPIO port. + * @deprecated Do not use this function. It has been superceded by @ref RGPIO_PinRead. + */ +static inline uint32_t RGPIO_ReadPinInput(RGPIO_Type *base, uint32_t pin) +{ + return RGPIO_PinRead(base, pin); +} + +#if defined(FSL_FEATURE_RGPIO_HAS_PORT_INPUT_DISABLE) && FSL_FEATURE_RGPIO_HAS_PORT_INPUT_DISABLE +/*! + * @param base RGPIO peripheral base pointer (RGPIOA, RGPIOB, RGPIOC, and so on.) + * @param mask RGPIO pin number mask + * @param enable RGPIO digital input enable/disable flag. + */ +static inline void RGPIO_EnablePortInput(RGPIO_Type *base, uint32_t mask, bool enable) +{ + if (enable) + { + base->PIDR &= ~mask; + } + else + { + base->PIDR |= mask; + } +} +#endif + +/*! @} */ + +#if defined(FSL_FEATURE_SOC_PORT_COUNT) && FSL_FEATURE_SOC_PORT_COUNT +/*! @name RGPIO Interrupt */ +/*! @{ */ + +/*! + * @brief Reads the RGPIO port interrupt status flag. + * + * If a pin is configured to generate the DMA request, the corresponding flag + * is cleared automatically at the completion of the requested DMA transfer. + * Otherwise, the flag remains set until a logic one is written to that flag. + * If configured for a level sensitive interrupt that remains asserted, the flag + * is set again immediately. + * + * @param base RGPIO peripheral base pointer (RGPIOA, RGPIOB, RGPIOC, and so on.) + * @retval The current RGPIO port interrupt status flag, for example, 0x00010001 means the + * pin 0 and 17 have the interrupt. + */ +uint32_t RGPIO_PortGetInterruptFlags(RGPIO_Type *base); + +/*! + * @brief Reads the RGPIO port interrupt status flag. + * @deprecated Do not use this function. It has been superceded by @ref RGPIO_PortGetInterruptFlags. + */ +static inline uint32_t RGPIO_GetPinsInterruptFlags(RGPIO_Type *base) +{ + return RGPIO_PortGetInterruptFlags(base); +} + +/*! + * @brief Clears multiple RGPIO pin interrupt status flags. + * + * @param base RGPIO peripheral base pointer (RGPIOA, RGPIOB, RGPIOC, and so on.) + * @param mask RGPIO pin number macro + */ +void RGPIO_PortClearInterruptFlags(RGPIO_Type *base, uint32_t mask); + +/*! + * @brief Clears multiple RGPIO pin interrupt status flags. + * @deprecated Do not use this function. It has been superceded by @ref RGPIO_PortClearInterruptFlags. + */ +static inline void RGPIO_ClearPinsInterruptFlags(RGPIO_Type *base, uint32_t mask) +{ + RGPIO_PortClearInterruptFlags(base, mask); +} +#endif +#if defined(FSL_FEATURE_RGPIO_HAS_ATTRIBUTE_CHECKER) && FSL_FEATURE_RGPIO_HAS_ATTRIBUTE_CHECKER +/*! + * @brief The RGPIO module supports a device-specific number of data ports, organized as 32-bit + * words. Each 32-bit data port includes a GACR register, which defines the byte-level + * attributes required for a successful access to the RGPIO programming model. The attribute controls for the 4 data + * bytes in the GACR follow a standard little endian + * data convention. + * + * @param base RGPIO peripheral base pointer (RGPIOA, RGPIOB, RGPIOC, and so on.) + * @param mask RGPIO pin number macro + */ +void RGPIO_CheckAttributeBytes(RGPIO_Type *base, rgpio_checker_attribute_t attribute); +#endif + +#if defined(FSL_FEATURE_RGPIO_HAS_IRQ_CONFIG) && FSL_FEATURE_RGPIO_HAS_IRQ_CONFIG +/*! + * @brief Configures the gpio pin interrupt/DMA request. + * + * @param base RGPIO peripheral base pointer. + * @param pin RGPIO pin number. + * @param sel RGPIO pin interrupt selection(0-3). + * @param config RGPIO pin interrupt configuration. + */ +static inline void RGPIO_SetPinInterruptConfig(RGPIO_Type *base, + uint32_t pin, + rgpio_interrupt_sel_t sel, + rgpio_interrupt_config_t config) +{ + base->ICR[pin] = + (base->ICR[pin] & ~(RGPIO_ICR_IRQC_MASK | RGPIO_ICR_IRQS_MASK)) | RGPIO_ICR_IRQC(config) | RGPIO_ICR_IRQS(sel); +} + +/*! + * @brief Sets the gpio interrupt configuration in ICR register for multiple pins. + * + * @param base RGPIO peripheral base pointer (RGPIOA, RGPIOB, RGPIOC, and so on.) + * @param mask RGPIO pin number macro. + * @param sel RGPIO pin interrupt selection(0-3). + * @param config RGPIO pin interrupt configuration. + */ +static inline void _SetMultipleInterruptPinsConfig(RGPIO_Type *base, + uint32_t mask, + rgpio_interrupt_sel_t sel, + rgpio_interrupt_config_t config) +{ + if (0U != (mask & 0xFFFFU)) + { + base->GICLR = + ((uint32_t)sel << RGPIO_ICR_IRQS_SHIFT) | ((uint32_t)config << RGPIO_ICR_IRQC_SHIFT) | (mask & 0xFFFFU); + } + mask = mask >> 16; + if (0U != mask) + { + base->GICHR = + ((uint32_t)sel << RGPIO_ICR_IRQS_SHIFT) | ((uint32_t)config << RGPIO_ICR_IRQC_SHIFT) | (mask & 0xFFFFU); + } +} + +/*! + * @brief Reads the whole gpio status flag. + * + * If a pin is configured to generate the DMA request, the corresponding flag + * is cleared automatically at the completion of the requested DMA transfer. + * Otherwise, the flag remains set until a logic one is written to that flag. + * If configured for a level sensitive interrupt that remains asserted, the flag + * is set again immediately. + * + * @param base RGPIO peripheral base pointer. + * @param sel RGPIO pin interrupt selection(0-3). + * @return Current gpio interrupt status flags, for example, 0x00010001 means the + * pin 0 and 16 have the interrupt. + */ +static inline uint32_t RGPIO_GetPinsInterruptFlags(RGPIO_Type *base, rgpio_interrupt_sel_t sel) +{ + return base->ISFR[(uint8_t)sel]; +} + +/*! + * @brief Clears the multiple pin interrupt status flag. + * + * @param base RGPIO peripheral base pointer. + * @param sel RGPIO pin interrupt selection(0-3). + * @param mask RGPIO pin number macro. + */ +static inline void RGPIO_ClearPinsInterruptFlags(RGPIO_Type *base, rgpio_interrupt_sel_t sel, uint32_t mask) +{ + base->ISFR[(uint8_t)sel] = mask; +} +#endif + +/*! @} */ +/*! @} */ + +/*! + * @addtogroup fgpio_driver + * @{ + */ + +/* + * Introduces the FGPIO feature. + * + * The FGPIO registers are aliased to the IOPORT interface. + * Accesses via the IOPORT interface occur in parallel with any instruction fetches and + * complete in a single cycle. This aliased Fast GPIO memory map is called FGPIO. + */ + +#if defined(FSL_FEATURE_SOC_FGPIO_COUNT) && FSL_FEATURE_SOC_FGPIO_COUNT + +/*! @name FGPIO Configuration */ +/*! @{ */ + +#if defined(FSL_FEATURE_PCC_HAS_FGPIO_CLOCK_GATE_CONTROL) && FSL_FEATURE_PCC_HAS_FGPIO_CLOCK_GATE_CONTROL +/*! + * @brief Initializes the FGPIO peripheral. + * + * This function ungates the FGPIO clock. + * + * @param base FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.) + */ +void FGPIO_PortInit(FGPIO_Type *base); + +/*! + * @brief Initializes the FGPIO peripheral. + * @deprecated Do not use this function. It has been superceded by @ref FGPIO_PortInit. + */ +static inline void FGPIO_Init(FGPIO_Type *base) +{ + FGPIO_PortInit(base); +} +#endif +/*! + * @brief Initializes a FGPIO pin used by the board. + * + * To initialize the FGPIO driver, define a pin configuration, as either input or output, in the user file. + * Then, call the FGPIO_PinInit() function. + * + * This is an example to define an input pin or an output pin configuration: + * @code + * Define a digital input pin configuration, + * rgpio_pin_config_t config = + * { + * kRGPIO_DigitalInput, + * 0, + * } + * Define a digital output pin configuration, + * rgpio_pin_config_t config = + * { + * kRGPIO_DigitalOutput, + * 0, + * } + * @endcode + * + * @param base FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.) + * @param pin FGPIO port pin number + * @param config FGPIO pin configuration pointer + */ +void FGPIO_PinInit(FGPIO_Type *base, uint32_t pin, const rgpio_pin_config_t *config); + +/*! + * @brief Gets the FGPIO instance according to the RGPIO base + * + * @param base FGPIO peripheral base pointer(PTA, PTB, PTC, etc.) + * @retval FGPIO instance + */ +uint32_t FGPIO_GetInstance(FGPIO_Type *base); +/*! @} */ + +/*! @name FGPIO Output Operations */ +/*! @{ */ + +/*! + * @brief Sets the output level of the multiple FGPIO pins to the logic 1 or 0. + * + * @param base FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.) + * @param pin FGPIO pin number + * @param output FGPIOpin output logic level. + * - 0: corresponding pin output low-logic level. + * - 1: corresponding pin output high-logic level. + */ +static inline void FGPIO_PinWrite(FGPIO_Type *base, uint32_t pin, uint8_t output) +{ + if (output == 0U) + { + base->PCOR = 1UL << pin; + } + else + { + base->PSOR = 1UL << pin; + } +} + +/*! + * @brief Sets the output level of the multiple FGPIO pins to the logic 1 or 0. + * @deprecated Do not use this function. It has been superceded by @ref FGPIO_PinWrite. + */ +static inline void FGPIO_WritePinOutput(FGPIO_Type *base, uint32_t pin, uint8_t output) +{ + FGPIO_PinWrite(base, pin, output); +} + +/*! + * @brief Sets the output level of the multiple FGPIO pins to the logic 1. + * + * @param base FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.) + * @param mask FGPIO pin number macro + */ +static inline void FGPIO_PortSet(FGPIO_Type *base, uint32_t mask) +{ + base->PSOR = mask; +} + +/*! + * @brief Sets the output level of the multiple FGPIO pins to the logic 1. + * @deprecated Do not use this function. It has been superceded by @ref FGPIO_PortSet. + */ +static inline void FGPIO_SetPinsOutput(FGPIO_Type *base, uint32_t mask) +{ + FGPIO_PortSet(base, mask); +} + +/*! + * @brief Sets the output level of the multiple FGPIO pins to the logic 0. + * + * @param base FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.) + * @param mask FGPIO pin number macro + */ +static inline void FGPIO_PortClear(FGPIO_Type *base, uint32_t mask) +{ + base->PCOR = mask; +} + +/*! + * @brief Sets the output level of the multiple FGPIO pins to the logic 0. + * @deprecated Do not use this function. It has been superceded by @ref FGPIO_PortClear. + */ +static inline void FGPIO_ClearPinsOutput(FGPIO_Type *base, uint32_t mask) +{ + FGPIO_PortClear(base, mask); +} + +/*! + * @brief Reverses the current output logic of the multiple FGPIO pins. + * + * @param base FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.) + * @param mask FGPIO pin number macro + */ +static inline void FGPIO_PortToggle(FGPIO_Type *base, uint32_t mask) +{ + base->PTOR = mask; +} + +/*! + * @brief Reverses the current output logic of the multiple FGPIO pins. + * @deprecated Do not use this function. It has been superceded by @ref FGPIO_PortToggle. + */ +static inline void FGPIO_TogglePinsOutput(FGPIO_Type *base, uint32_t mask) +{ + FGPIO_PortToggle(base, mask); +} +/*! @} */ + +/*! @name FGPIO Input Operations */ +/*! @{ */ + +/*! + * @brief Reads the current input value of the FGPIO port. + * + * @param base FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.) + * @param pin FGPIO pin number + * @retval FGPIO port input value + * - 0: corresponding pin input low-logic level. + * - 1: corresponding pin input high-logic level. + */ +static inline uint32_t FGPIO_PinRead(FGPIO_Type *base, uint32_t pin) +{ + return (((base->PDIR) >> pin) & 0x01U); +} + +/*! + * @brief Reads the current input value of the FGPIO port. + * @deprecated Do not use this function. It has been superceded by @ref FGPIO_PinRead + */ +static inline uint32_t FGPIO_ReadPinInput(FGPIO_Type *base, uint32_t pin) +{ + return FGPIO_PinRead(base, pin); +} +/*! @} */ + +#if defined(FSL_FEATURE_SOC_PORT_COUNT) && FSL_FEATURE_SOC_PORT_COUNT +/*! @name FGPIO Interrupt */ +/*! @{ */ + +/*! + * @brief Reads the FGPIO port interrupt status flag. + * + * If a pin is configured to generate the DMA request, the corresponding flag + * is cleared automatically at the completion of the requested DMA transfer. + * Otherwise, the flag remains set until a logic one is written to that flag. + * If configured for a level-sensitive interrupt that remains asserted, the flag + * is set again immediately. + * + * @param base FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.) + * @retval The current FGPIO port interrupt status flags, for example, 0x00010001 means the + * pin 0 and 17 have the interrupt. + */ +uint32_t FGPIO_PortGetInterruptFlags(FGPIO_Type *base); + +/*! + * @brief Reads the FGPIO port interrupt status flag. + * @deprecated Do not use this function. It has been superceded by @ref FGPIO_PortGetInterruptFlags. + */ +static inline uint32_t FGPIO_GetPinsInterruptFlags(FGPIO_Type *base) +{ + return FGPIO_PortGetInterruptFlags(base); +} + +/*! + * @brief Clears the multiple FGPIO pin interrupt status flag. + * + * @param base FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.) + * @param mask FGPIO pin number macro + */ +void FGPIO_PortClearInterruptFlags(FGPIO_Type *base, uint32_t mask); + +/*! + * @brief Clears the multiple FGPIO pin interrupt status flag. + * @deprecated Do not use this function. It has been superceded by @ref FGPIO_PortClearInterruptFlags. + */ +static inline void FGPIO_ClearPinsInterruptFlags(FGPIO_Type *base, uint32_t mask) +{ + FGPIO_PortClearInterruptFlags(base, mask); +} +#endif +#if defined(FSL_FEATURE_RGPIO_HAS_ATTRIBUTE_CHECKER) && FSL_FEATURE_RGPIO_HAS_ATTRIBUTE_CHECKER +/*! + * @brief The FGPIO module supports a device-specific number of data ports, organized as 32-bit + * words. Each 32-bit data port includes a GACR register, which defines the byte-level + * attributes required for a successful access to the RGPIO programming model. The attribute controls for the 4 data + * bytes in the GACR follow a standard little endian + * data convention. + * + * @param base FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.) + * @param mask FGPIO pin number macro + */ +void FGPIO_CheckAttributeBytes(FGPIO_Type *base, rgpio_checker_attribute_t attribute); +#endif + +/*! @} */ + +#endif /* FSL_FEATURE_SOC_FGPIO_COUNT */ + +#if defined(__cplusplus) +} +#endif + +/*! + * @} + */ + +#endif /* FSL_RGPIO_H_*/ diff --git a/bsp/nxp/imx/imx91/drivers/serial.c b/bsp/nxp/imx/imx91/drivers/serial.c new file mode 100644 index 00000000000..4ac9096aa1b --- /dev/null +++ b/bsp/nxp/imx/imx91/drivers/serial.c @@ -0,0 +1,377 @@ +/* + * Copyright (c) 2006-2025, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2025-08-10 Siwei Xu Add i.MX91 SDK + * 2025-09-15 Siwei Xu Fix LPUART driver + */ + +#include +#include +#include +#include + +#include "serial.h" + +#include "MIMX9131.h" +#include "fsl_clock.h" +#include "fsl_lpuart.h" + +struct hw_uart_device +{ + struct rt_serial_device serial; /* Select serial device */ + const char *device_name; /* serial device name */ + + LPUART_Type *uart_ptr; + rt_base_t uart_base; + int instance; + int irqn; + + clock_root_t clock_root; /* clock root */ + clock_root_mux_source_t clock_mux; /* clock mux */ + clock_ip_name_t clock_ip_name; /* clock control gate */ +}; + +#ifdef BSP_USING_UART1 +/* UART1 device driver structure */ +static struct hw_uart_device _uart1_device = { + .device_name = "uart1", + .uart_ptr = RT_NULL, + .uart_base = LPUART1_BASE, + .instance = 1, + .irqn = LPUART1_IRQn, + .clock_root = kCLOCK_Root_Lpuart1, + .clock_mux = kCLOCK_LPUART1_ClockRoot_MuxOsc24M, + .clock_ip_name = kCLOCK_Lpuart1, +}; +#endif + +static struct hw_uart_device *hw_uart_devices[] = { +#ifdef BSP_USING_UART1 + &_uart1_device, +#endif +}; + +static void rt_hw_uart_isr(int irqn, void *param) +{ + struct rt_serial_device *serial = (struct rt_serial_device *)param; + + rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND); +} + +static rt_err_t uart_configure(struct rt_serial_device *serial, struct serial_configure *cfg) +{ + struct hw_uart_device *uart = RT_NULL; + static lpuart_config_t config; + + RT_ASSERT(serial != RT_NULL); + uart = (struct hw_uart_device *)serial->parent.user_data; + + LPUART_GetDefaultConfig(&config); + + // baud rate + config.baudRate_Bps = cfg->baud_rate; + + // data bits + switch (cfg->data_bits) + { + case DATA_BITS_8: + config.dataBitsCount = kLPUART_EightDataBits; + break; + case DATA_BITS_7: +#if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT + config.dataBitsCount = kLPUART_SevenDataBits; + break; +#endif + default: + config.dataBitsCount = kLPUART_EightDataBits; + break; + } + + // parity bit + switch (cfg->parity) + { + case PARITY_NONE: + config.parityMode = kLPUART_ParityDisabled; + break; + case PARITY_ODD: + config.parityMode = kLPUART_ParityOdd; + break; + case PARITY_EVEN: + config.parityMode = kLPUART_ParityEven; + break; + default: + config.parityMode = kLPUART_ParityDisabled; + break; + } + + // stop bits +#if defined(FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT) && FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT + switch (cfg->stop_bits) + { + case STOP_BITS_1: + config.stopBitCount = kLPUART_OneStopBit; + break; + case STOP_BITS_2: + config.stopBitCount = kLPUART_TwoStopBit; + break; + default: + config.stopBitCount = kLPUART_OneStopBit; + break; + } +#endif + + // LSB/MSB + if (cfg->bit_order == BIT_ORDER_LSB) + { + config.isMsb = false; + } + else + { + config.isMsb = true; + } + + // hardware flow control +#if defined(FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT) && FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT + if (cfg->flowcontrol == RT_SERIAL_FLOWCONTROL_NONE) + { + // disable hardware flow control + config.enableRxRTS = false; + config.enableTxCTS = false; + } + else + { + // enable hardware flow control + config.enableRxRTS = true; + config.enableTxCTS = true; + } +#endif + + // enable TX and RX + config.enableTx = serial->parent.flag & RT_DEVICE_FLAG_WRONLY; + config.enableRx = serial->parent.flag & RT_DEVICE_FLAG_RDONLY; + + // Set UART clock source and clock divider + CLOCK_SetRootClockMux(uart->clock_root, uart->clock_mux); + CLOCK_SetRootClockDiv(uart->clock_root, 1U); + + // Initialize the LPUART module with the configuration structure and clock source + LPUART_Init(uart->uart_ptr, &config, CLOCK_GetIpFreq(uart->clock_root)); + + // Install interrupt handler + rt_hw_interrupt_install(uart->irqn, rt_hw_uart_isr, serial, "uart"); + rt_hw_interrupt_mask(uart->irqn); + + // Enable RX interrupt + LPUART_EnableInterrupts(uart->uart_ptr, kLPUART_RxDataRegFullInterruptEnable); + return RT_EOK; +} + +static rt_err_t uart_control(struct rt_serial_device *serial, int cmd, void *arg) +{ + struct hw_uart_device *uart = RT_NULL; + + RT_ASSERT(serial != RT_NULL); + uart = (struct hw_uart_device *)serial->parent.user_data; + + switch (cmd) + { + case RT_DEVICE_CTRL_CLR_INT: + /* disable rx irq */ + rt_hw_interrupt_mask(uart->irqn); + break; + + case RT_DEVICE_CTRL_SET_INT: + /* enable rx irq */ + rt_hw_interrupt_umask(uart->irqn); + break; + } + + return RT_EOK; +} + +static int uart_putc(struct rt_serial_device *serial, char c) +{ + struct hw_uart_device *uart; + + RT_ASSERT(serial != RT_NULL); + uart = (struct hw_uart_device *)serial->parent.user_data; + + while (!(LPUART_GetStatusFlags(uart->uart_ptr) & kLPUART_TxDataRegEmptyFlag)) + { + __NOP(); + } + + LPUART_WriteByte(uart->uart_ptr, c); + + return 1; +} + +#ifdef BSP_USING_EARLY_CONSOLE +LPUART_Type *earlycon_base = RT_NULL; + +void rt_hw_earlycon_set(void *base) +{ + earlycon_base = (LPUART_Type *)base; +} + +void rt_hw_earlycon_ioremap(void) +{ + earlycon_base = rt_ioremap_early((void *)LPUART1, LPUART1_SIZE); +} + +void rt_hw_earlycon_putc(char c) +{ + LPUART_WriteByte(earlycon_base, c); + while (!(LPUART_GetStatusFlags(earlycon_base) & kLPUART_TxDataRegEmptyFlag)) + ; +} + +static void rt_hw_earlycon_print(const char *str, int print_newline) +{ + int has_cr = 0; + int has_lf = 0; + while (*str) + { + if (*str == '\r') + { + has_cr = 1; + } + else if (*str == '\n') + { + has_lf = 1; + } + rt_hw_earlycon_putc(*str++); + } + if (!has_cr && print_newline) + { + rt_hw_earlycon_putc('\r'); + } + if (!has_lf && print_newline) + { + rt_hw_earlycon_putc('\n'); + } +} + +void rt_hw_earlycon_puts(const char *str) +{ + rt_hw_earlycon_print(str, 1); +} + +void rt_hw_earlycon_print_hex(const char *str, rt_base_t hex) +{ + rt_hw_earlycon_print(str, 0); + rt_hw_earlycon_putc('0'); + rt_hw_earlycon_putc('x'); + for (int i = 60; i >= 0; i -= 4) + { + rt_base_t h = (hex >> i) & 0xF; + rt_hw_earlycon_putc(h < 10 ? '0' + h : 'A' + h - 10); + } + rt_hw_earlycon_putc('\r'); + rt_hw_earlycon_putc('\n'); +} +#endif + +void rt_hw_console_putc(char c) +{ +#if defined(BSP_USING_UART1) + uart_putc(&_uart1_device.serial, c); +#endif +} + +void rt_hw_console_output(const char *str) +{ +#if defined(BSP_USING_UART1) + int has_cr = 0; + int has_lf = 0; + while (*str) + { + if (*str == '\r') + { + has_cr = 1; + } + else if (*str == '\n') + { + has_lf = 1; + } + rt_hw_console_putc(*str++); + } + if (!has_cr) + { + rt_hw_console_putc('\r'); + } + if (!has_lf) + { + rt_hw_console_putc('\n'); + } +#endif +} + +static int uart_getc(struct rt_serial_device *serial) +{ + int ch; + struct hw_uart_device *uart; + + RT_ASSERT(serial != RT_NULL); + uart = (struct hw_uart_device *)serial->parent.user_data; + + uint32_t flags = LPUART_GetStatusFlags(uart->uart_ptr); + if (flags & kLPUART_RxDataRegFullFlag) + { + ch = LPUART_ReadByte(uart->uart_ptr); + } + else + { + ch = -1; + } + + return ch; +} + +static const struct rt_uart_ops _uart_ops = { + uart_configure, + uart_control, + uart_putc, + uart_getc, +}; + +int rt_hw_uart_init(void) +{ + struct serial_configure config; + + /* setup default serial configure */ + config.baud_rate = BAUD_RATE_115200; + config.bit_order = BIT_ORDER_LSB; + config.data_bits = DATA_BITS_8; + config.parity = PARITY_NONE; + config.stop_bits = STOP_BITS_1; + config.invert = NRZ_NORMAL; + config.bufsz = RT_SERIAL_RB_BUFSZ; + + /* Remap CCM controller to virtual address */ + CCM_CTRL = rt_ioremap((void *)CCM_CTRL_BASE, CCM_CTRL_SIZE); + + for (int i = 0; i < RT_ARRAY_SIZE(hw_uart_devices); i++) + { + if (hw_uart_devices[i] != RT_NULL) + { + hw_uart_devices[i]->serial.ops = &_uart_ops; + hw_uart_devices[i]->serial.config = config; + + /* Remap LPUART instance to virtual address */ + hw_uart_devices[i]->uart_ptr = rt_ioremap((void *)hw_uart_devices[i]->uart_base, LPUART1_SIZE); + + /* Update LPUART instance */ + LPUART_SetInstance(hw_uart_devices[i]->instance, hw_uart_devices[i]->uart_ptr); + + rt_hw_serial_register(&hw_uart_devices[i]->serial, hw_uart_devices[i]->device_name, + RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, hw_uart_devices[i]); + } + } + + return 0; +} diff --git a/bsp/nxp/imx/imx91/drivers/serial.h b/bsp/nxp/imx/imx91/drivers/serial.h new file mode 100644 index 00000000000..93f53bc1a9d --- /dev/null +++ b/bsp/nxp/imx/imx91/drivers/serial.h @@ -0,0 +1,38 @@ +/* + * Copyright (c) 2006-2025, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2025-08-10 Siwei Xu Add i.MX91 SDK + * 2025-09-15 Siwei Xu Fix LPUART driver + */ + +#ifndef __UART_H__ +#define __UART_H__ + +#include "board.h" + +#include + +int rt_hw_uart_init(void); + +#ifdef BSP_USING_EARLY_CONSOLE +void rt_hw_earlycon_ioremap(void); +void rt_hw_earlycon_putc(char c); +void rt_hw_earlycon_puts(const char *str); +void rt_hw_earlycon_print_hex(const char *str, rt_base_t hex); +#else +static inline void rt_hw_earlycon_ioremap(void) {} +static inline void rt_hw_earlycon_putc(char c) {} +static inline void rt_hw_earlycon_puts(const char *str) {} +static inline void rt_hw_earlycon_print_hex(const char *str, rt_base_t hex) {} +#endif + +void rt_hw_console_putc(char c); +void rt_hw_console_output(const char *str); + +#endif + + diff --git a/bsp/rockchip/rk3568/rtconfig.h b/bsp/nxp/imx/imx91/rtconfig.h similarity index 90% rename from bsp/rockchip/rk3568/rtconfig.h rename to bsp/nxp/imx/imx91/rtconfig.h index 6c44e3cb29c..6e279d91c8c 100644 --- a/bsp/rockchip/rk3568/rtconfig.h +++ b/bsp/nxp/imx/imx91/rtconfig.h @@ -72,23 +72,21 @@ /* end of rt_strnlen options */ /* end of klibc options */ -#define RT_NAME_MAX 12 -#define RT_USING_SMP -#define RT_CPUS_NR 4 -#define RT_ALIGN_SIZE 8 +#define RT_NAME_MAX 16 +#define RT_CPUS_NR 1 +#define RT_ALIGN_SIZE 16 #define RT_THREAD_PRIORITY_32 #define RT_THREAD_PRIORITY_MAX 32 -#define RT_TICK_PER_SECOND 100 +#define RT_TICK_PER_SECOND 1000 #define RT_USING_OVERFLOW_CHECK #define RT_USING_HOOK #define RT_HOOK_USING_FUNC_PTR #define RT_USING_IDLE_HOOK #define RT_IDLE_HOOK_LIST_SIZE 4 -#define IDLE_THREAD_STACK_SIZE 4096 -#define SYSTEM_THREAD_STACK_SIZE 4096 +#define IDLE_THREAD_STACK_SIZE 8192 #define RT_USING_TIMER_SOFT #define RT_TIMER_THREAD_PRIO 4 -#define RT_TIMER_THREAD_STACK_SIZE 4096 +#define RT_TIMER_THREAD_STACK_SIZE 8192 /* kservice options */ @@ -111,30 +109,27 @@ #define RT_USING_MEMPOOL #define RT_USING_SMALL_MEM -#define RT_USING_MEMHEAP -#define RT_MEMHEAP_FAST_MODE #define RT_USING_SMALL_MEM_AS_HEAP -#define RT_USING_MEMTRACE #define RT_USING_HEAP /* end of Memory Management */ #define RT_USING_DEVICE -#define RT_USING_DEVICE_OPS +#define RT_USING_THREADSAFE_PRINTF #define RT_USING_CONSOLE #define RT_CONSOLEBUF_SIZE 128 -#define RT_CONSOLE_DEVICE_NAME "uart2" +#define RT_CONSOLE_DEVICE_NAME "uart1" #define RT_VER_NUM 0x50201 #define RT_BACKTRACE_LEVEL_MAX_NR 32 /* end of RT-Thread Kernel */ /* AArch64 Architecture Configuration */ -#define ARCH_TEXT_OFFSET 0x200000 -#define ARCH_RAM_OFFSET 0 +#define ARCH_TEXT_OFFSET 0x0 +#define ARCH_RAM_OFFSET 0x80000000 #define ARCH_SECONDARY_CPU_STACK_SIZE 4096 #define ARCH_HAVE_EFFICIENT_UNALIGNED_ACCESS #define ARCH_USING_GENERIC_CPUID -#define ARCH_HEAP_SIZE 0x4000000 -#define ARCH_INIT_PAGE_SIZE 0x200000 +#define ARCH_HEAP_SIZE 0x2000000 +#define ARCH_INIT_PAGE_SIZE 0x8000000 /* end of AArch64 Architecture Configuration */ #define ARCH_CPU_64BIT #define RT_USING_CACHE @@ -147,6 +142,7 @@ #define ARCH_ARM_CORTEX_A #define RT_NO_USING_GIC #define ARCH_ARM_CORTEX_A55 +#define RT_BACKTRACE_FUNCTION_NAME #define ARCH_ARMV8 #define ARCH_USING_ASID #define ARCH_USING_HW_THREAD_SELF @@ -163,7 +159,7 @@ #define FINSH_USING_MSH #define FINSH_THREAD_NAME "tshell" #define FINSH_THREAD_PRIORITY 20 -#define FINSH_THREAD_STACK_SIZE 4096 +#define FINSH_THREAD_STACK_SIZE 8092 #define FINSH_USING_HISTORY #define FINSH_HISTORY_LINES 5 #define FINSH_USING_SYMTAB @@ -175,23 +171,25 @@ /* DFS: device virtual file system */ +#define RT_USING_DFS +#define DFS_USING_POSIX +#define DFS_USING_WORKDIR +#define DFS_FD_MAX 16 +#define RT_USING_DFS_V1 +#define DFS_FILESYSTEMS_MAX 4 +#define DFS_FILESYSTEM_TYPES_MAX 4 +#define RT_USING_DFS_DEVFS /* end of DFS: device virtual file system */ /* Device Drivers */ -#define RT_USING_DM #define RT_USING_DEVICE_IPC #define RT_UNAMED_PIPE_NUMBER 64 #define RT_USING_SERIAL #define RT_USING_SERIAL_V1 +#define RT_SERIAL_USING_DMA #define RT_SERIAL_RB_BUFSZ 64 -#define RT_USING_PM -#define PM_TICKLESS_THRESHOLD_TIME 2 -#define RT_USING_OFW -#define RT_FDT_EARLYCON_MSG_SIZE 128 -#define RT_USING_OFW_BUS_RANGES_NUMBER 8 #define RT_USING_PIN -#define RT_USING_CLK /* end of Device Drivers */ /* C/C++ and POSIX layer */ @@ -240,8 +238,6 @@ #define RT_PAGE_AFFINITY_BLOCK_SIZE 0x1000 #define RT_PAGE_MAX_ORDER 11 -#define RT_USING_MEMBLOCK -#define RT_INIT_MEMORY_REGIONS 128 /* Debugging */ @@ -457,14 +453,16 @@ /* end of Arduino libraries */ /* end of RT-Thread online packages */ -#define SOC_RK3568 +#define BOARD_IMX91 +#define SOC_MIMX91X1D /* Hardware Drivers Config */ -#define BSP_USING_UART -#define RT_USING_UART2 +#define BSP_USING_EARLY_CONSOLE +#define BSP_USING_UART1 #define BSP_USING_GIC #define BSP_USING_GICV3 +#define KERNEL_ASPACE_START 0x1000000 /* end of Hardware Drivers Config */ #endif diff --git a/bsp/nxp/imx/imx91/rtconfig.py b/bsp/nxp/imx/imx91/rtconfig.py new file mode 100644 index 00000000000..b162a6a6a28 --- /dev/null +++ b/bsp/nxp/imx/imx91/rtconfig.py @@ -0,0 +1,58 @@ +import os + +# toolchains options +ARCH = 'aarch64' +CPU = 'cortex-a' +CROSS_TOOL = 'gcc' + +if os.getenv('RTT_ROOT'): + RTT_ROOT = os.getenv('RTT_ROOT') +else: + RTT_ROOT = os.path.join(os.getcwd(), '..', '..', '..') + +if os.getenv('RTT_CC'): + CROSS_TOOL = os.getenv('RTT_CC') + +# only support GNU GCC compiler. +PLATFORM = 'gcc' +EXEC_PATH = r'/opt/gcc-arm-8.3-2019.03-x86_64-aarch64-elf/bin/' + +if os.getenv('RTT_EXEC_PATH'): + EXEC_PATH = os.getenv('RTT_EXEC_PATH') + +BUILD = 'debug' + +if PLATFORM == 'gcc': + # toolchains + PREFIX = os.getenv('RTT_CC_PREFIX') or 'aarch64-none-elf-' + CC = PREFIX + 'gcc' + CXX = PREFIX + 'g++' + CPP = PREFIX + 'cpp' + AS = PREFIX + 'gcc' + AR = PREFIX + 'ar' + LINK = PREFIX + 'gcc' + TARGET_EXT = 'elf' + SIZE = PREFIX + 'size' + OBJDUMP = PREFIX + 'objdump' + OBJCPY = PREFIX + 'objcopy' + + DEVICE = ' -march=armv8-a -mtune=cortex-a55' + DEVICE += ' -fno-omit-frame-pointer -ffunction-sections -fdata-sections' + CPPFLAGS = ' -E -P -x assembler-with-cpp' + CFLAGS = DEVICE + ' -Wall -Wno-cpp' + AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -D__ASSEMBLY__' + LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,system_vectors -T link.lds' + + CPATH = '' + LPATH = '' + + if BUILD == 'debug': + CFLAGS += ' -O0 -ggdb' + CPPFLAGS += ' -O0 -ggdb' + else: + CFLAGS += ' -O2 -ggdb' + CPPFLAGS += ' -O2 -ggdb' + + POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' +\ + SIZE + ' $TARGET \n' + DUMP_ACTION = OBJDUMP + ' -D -S $TARGET > disasm.txt\n' diff --git a/bsp/nxp/mcx/mcxa/Libraries/drivers/SConscript b/bsp/nxp/mcx/mcxa/Libraries/drivers/SConscript index 76cc1c2f7bd..da702a27eff 100644 --- a/bsp/nxp/mcx/mcxa/Libraries/drivers/SConscript +++ b/bsp/nxp/mcx/mcxa/Libraries/drivers/SConscript @@ -37,6 +37,9 @@ if GetDepend('BSP_USING_PWM'): if GetDepend('BSP_USING_FLASH'): src += ['drv_chipflash.c'] +if GetDepend('BSP_USING_CAN'): + src += ['drv_can.c'] + path = [cwd,cwd + '/config'] group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path) diff --git a/bsp/nxp/mcx/mcxa/Libraries/drivers/drv_can.c b/bsp/nxp/mcx/mcxa/Libraries/drivers/drv_can.c new file mode 100644 index 00000000000..1445bc6bbb6 --- /dev/null +++ b/bsp/nxp/mcx/mcxa/Libraries/drivers/drv_can.c @@ -0,0 +1,551 @@ +/* + * Copyright (c) 2006-2025, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2025-12-23 CYFS the first version. + */ + +#include + +#ifdef RT_USING_CAN + +#include "fsl_common.h" +#include "fsl_flexcan.h" + +#define TX_MB_IDX (6) +#define RX_MB_COUNT (1) +static flexcan_frame_t frame[RX_MB_COUNT]; /* one frame buffer per RX MB */ +static rt_uint32_t filter_mask = 0; + +enum +{ +#ifdef BSP_USING_CAN0 + CAN0_INDEX, +#endif +#ifdef BSP_USING_CAN1 + CAN1_INDEX, +#endif +}; + +struct imxrt_can +{ + char *name; + CAN_Type *base; + IRQn_Type irqn; + uint32_t instance; + clock_div_name_t clock_div_name; + clock_attach_id_t clock_attach_id; + flexcan_handle_t handle; + struct rt_can_device can_dev; +}; + +struct imxrt_can flexcans[] = +{ +#ifdef BSP_USING_CAN0 + { + .name = "can0", + .base = CAN0, + .instance = 0, + .irqn = CAN0_IRQn, + .clock_div_name = kCLOCK_DivFLEXCAN0, + .clock_attach_id = kFRO_HF_DIV_to_FLEXCAN0, + }, +#endif +#ifdef BSP_USING_CAN1 + { + .name = "can1", + .base = CAN1, + .instance = 1, + .irqn = CAN1_IRQn, + .clock_div_name = kCLOCK_DivFLEXCAN1, + .clock_attach_id = kFRO_HF_DIV_to_FLEXCAN1, + }, +#endif +}; + +static void flexcan_callback(CAN_Type *base, flexcan_handle_t *handle, status_t status, uint64_t result, void *userData) +{ + struct imxrt_can *can; + flexcan_mb_transfer_t rxXfer; + + can = (struct imxrt_can *)userData; + + switch (status) + { + case kStatus_FLEXCAN_RxIdle: + rt_hw_can_isr(&can->can_dev, RT_CAN_EVENT_RX_IND | result << 8); + rxXfer.frame = &frame[result - 1]; + rxXfer.mbIdx = result; + FLEXCAN_TransferReceiveNonBlocking(can->base, &can->handle, &rxXfer); + break; + + case kStatus_FLEXCAN_TxIdle: + rt_hw_can_isr(&can->can_dev, RT_CAN_EVENT_TX_DONE | result << 8); + break; + default: + break; + } +} + +static rt_err_t _can_config(struct rt_can_device *can_dev, struct can_configure *cfg) +{ + struct imxrt_can *can = (struct imxrt_can *)can_dev->parent.user_data; + flexcan_config_t config; + rt_uint32_t res = RT_EOK; + flexcan_rx_mb_config_t mbConfig; + flexcan_mb_transfer_t rxXfer; + rt_uint8_t i, mailbox; + + FLEXCAN_GetDefaultConfig(&config); + config.baudRate = cfg->baud_rate; + config.enableIndividMask = true; /* one filter per MB */ + config.disableSelfReception = true; + + switch (cfg->mode) + { + case RT_CAN_MODE_NORMAL: + /* default mode */ + break; + case RT_CAN_MODE_LISTEN: + break; + case RT_CAN_MODE_LOOPBACK: + config.enableLoopBack = true; + break; + case RT_CAN_MODE_LOOPBACKANLISTEN: + break; + } + + flexcan_timing_config_t timing_config; + rt_memset(&timing_config, 0, sizeof(flexcan_timing_config_t)); + + if(FLEXCAN_CalculateImprovedTimingValues(can->base, config.baudRate, CLOCK_GetFlexcanClkFreq(can->instance), &timing_config)) + { + /* Update the improved timing configuration*/ + rt_memcpy(&(config.timingConfig), &timing_config, sizeof(flexcan_timing_config_t)); + } + else + { + //rt_kprintf("No found Improved Timing Configuration. Just used default configuration\n"); + } + + FLEXCAN_Init(can->base, &config, CLOCK_GetFlexcanClkFreq(can->instance)); + FLEXCAN_TransferCreateHandle(can->base, &can->handle, flexcan_callback, can); + + /* init RX_MB_COUNT RX MB to default status */ + mbConfig.format = kFLEXCAN_FrameFormatStandard; /* standard ID */ + mbConfig.type = kFLEXCAN_FrameTypeData; /* data frame */ + mbConfig.id = FLEXCAN_ID_STD(0); /* default ID is 0 */ + for (i = 0; i < RX_MB_COUNT; i++) + { + /* the used MB index from 1 to RX_MB_COUNT */ + mailbox = i + 1; + + /* all ID bit in the filter is "don't care" */ + FLEXCAN_SetRxIndividualMask(can->base, mailbox, FLEXCAN_RX_MB_STD_MASK(0, 0, 0)); + FLEXCAN_SetRxMbConfig(can->base, mailbox, &mbConfig, true); + /* one frame buffer per MB */ + rxXfer.frame = &frame[i]; + rxXfer.mbIdx = mailbox; + FLEXCAN_TransferReceiveNonBlocking(can->base, &can->handle, &rxXfer); + } + + return res; +} + +static rt_err_t _can_control(struct rt_can_device *can_dev, int cmd, void *arg) +{ + struct imxrt_can *can; + rt_uint32_t argval, mask; + rt_uint32_t res = RT_EOK; + flexcan_rx_mb_config_t mbConfig; + struct rt_can_filter_config *cfg; + struct rt_can_filter_item *item; + rt_uint8_t i, count, index; + + RT_ASSERT(can_dev != RT_NULL); + + can = (struct imxrt_can *)can_dev->parent.user_data; + RT_ASSERT(can != RT_NULL); + + switch (cmd) + { + case RT_DEVICE_CTRL_SET_INT: + argval = (rt_uint32_t) arg; + if (argval == RT_DEVICE_FLAG_INT_RX) + { + mask = kFLEXCAN_RxWarningInterruptEnable; + } + else if (argval == RT_DEVICE_FLAG_INT_TX) + { + mask = kFLEXCAN_TxWarningInterruptEnable; + } + else if (argval == RT_DEVICE_CAN_INT_ERR) + { + mask = kFLEXCAN_ErrorInterruptEnable; + } + FLEXCAN_EnableInterrupts(can->base, mask); + EnableIRQ(can->irqn); + break; + case RT_DEVICE_CTRL_CLR_INT: + /* each CAN device have one IRQ number. */ + DisableIRQ(can->irqn); + break; + case RT_CAN_CMD_SET_FILTER: + cfg = (struct rt_can_filter_config *)arg; + item = cfg->items; + count = cfg->count; + + if (filter_mask == 0xffffffff) + { + rt_kprintf("%s filter is full!\n", can->name); + res = -RT_ERROR; + break; + } + else if (filter_mask == 0) + { + /* deinit all init RX MB */ + for (i = 0; i < RX_MB_COUNT; i++) + { + FLEXCAN_SetRxMbConfig(can->base, i + 1, RT_NULL, false); + } + } + + while (count) + { + if (item->ide) + { + mbConfig.format = kFLEXCAN_FrameFormatExtend; + mbConfig.id = FLEXCAN_ID_EXT(item->id); + mask = FLEXCAN_RX_MB_EXT_MASK(item->mask, 0, 0); + } + else + { + mbConfig.format = kFLEXCAN_FrameFormatStandard; + mbConfig.id = FLEXCAN_ID_STD(item->id); + mask = FLEXCAN_RX_MB_STD_MASK(item->mask, 0, 0); + } + + if (item->rtr) + { + mbConfig.type = kFLEXCAN_FrameTypeRemote; + } + else + { + mbConfig.type = kFLEXCAN_FrameTypeData; + } + + /* user does not specify hdr index,set hdr_bank from RX MB 1 */ + if (item->hdr_bank == -1) + { + + for (i = 0; i < 32; i++) + { + if (!(filter_mask & (1 << i))) + { + index = i; + break; + } + } + } + else /* use user specified hdr_bank */ + { + if (filter_mask & (1 << item->hdr_bank)) + { + res = -RT_ERROR; + rt_kprintf("%s hdr%d filter already set!\n", can->name, item->hdr_bank); + break; + } + else + { + index = item->hdr_bank; + } + } + + /* RX MB index from 1 to 32,hdr index 0~31 map RX MB index 1~32. */ + FLEXCAN_SetRxIndividualMask(can->base, index + 1, mask); + FLEXCAN_SetRxMbConfig(can->base, index + 1, &mbConfig, true); + filter_mask |= 1 << index; + + item++; + count--; + } + + break; + + case RT_CAN_CMD_SET_BAUD: + { + struct can_configure *cfg = (struct can_configure *)arg; + if (cfg != RT_NULL) + { + can->can_dev.config = *cfg; + _can_config(can_dev, cfg); + res = RT_EOK; + } + else + { + res = -RT_ERROR; + } + break; + } + case RT_CAN_CMD_SET_MODE: + res = -RT_ERROR; + break; + + case RT_CAN_CMD_SET_PRIV: + res = -RT_ERROR; + break; + case RT_CAN_CMD_GET_STATUS: + FLEXCAN_GetBusErrCount(can->base, (rt_uint8_t *)(&can->can_dev.status.snderrcnt), (rt_uint8_t *)(&can->can_dev.status.rcverrcnt)); + rt_memcpy(arg, &can->can_dev.status, sizeof(can->can_dev.status)); + break; + case RT_CAN_CMD_START: + /* already started in can_cfg */ + break; + default: + res = -RT_ERROR; + break; + } + + return res; +} + +static rt_ssize_t _can_sendmsg(struct rt_can_device *can_dev, const void *buf, rt_uint32_t boxno) +{ + struct imxrt_can *can; + struct rt_can_msg *msg; + status_t ret; + flexcan_frame_t frame; + flexcan_mb_transfer_t txXfer; + + RT_ASSERT(can_dev != RT_NULL); + RT_ASSERT(buf != RT_NULL); + + can = (struct imxrt_can *)can_dev->parent.user_data; + msg = (struct rt_can_msg *) buf; + + RT_ASSERT(can != RT_NULL); + RT_ASSERT(msg != RT_NULL); + + FLEXCAN_SetTxMbConfig(can->base, boxno, true); + + if (RT_CAN_STDID == msg->ide) + { + frame.id = FLEXCAN_ID_STD(msg->id); + frame.format = kFLEXCAN_FrameFormatStandard; + } + else if (RT_CAN_EXTID == msg->ide) + { + frame.id = FLEXCAN_ID_EXT(msg->id); + frame.format = kFLEXCAN_FrameFormatExtend; + } + + if (RT_CAN_DTR == msg->rtr) + { + frame.type = kFLEXCAN_FrameTypeData; + } + else if (RT_CAN_RTR == msg->rtr) + { + frame.type = kFLEXCAN_FrameTypeRemote; + } + + frame.length = msg->len; + frame.dataByte0 = msg->data[0]; + frame.dataByte1 = msg->data[1]; + frame.dataByte2 = msg->data[2]; + frame.dataByte3 = msg->data[3]; + frame.dataByte4 = msg->data[4]; + frame.dataByte5 = msg->data[5]; + frame.dataByte6 = msg->data[6]; + frame.dataByte7 = msg->data[7]; + + txXfer.mbIdx = boxno; + txXfer.frame = &frame; + ret = FLEXCAN_TransferSendBlocking(can->base, boxno, txXfer.frame); + switch (ret) + { + case kStatus_Success: + ret = RT_EOK; + rt_hw_can_isr(&can->can_dev, RT_CAN_EVENT_TX_DONE | boxno << 8); + break; + case kStatus_Fail: + ret = -RT_ERROR; + break; + } + + return (rt_ssize_t)ret; +} + +static rt_ssize_t _can_recvmsg(struct rt_can_device *can_dev, void *buf, rt_uint32_t boxno) +{ + struct imxrt_can *can; + struct rt_can_msg *pmsg; + rt_uint8_t index; + + RT_ASSERT(can_dev != RT_NULL); + + can = (struct imxrt_can *)can_dev->parent.user_data; + pmsg = (struct rt_can_msg *) buf; + RT_ASSERT(can != RT_NULL); + + index = boxno - 1; + + if (frame[index].format == kFLEXCAN_FrameFormatStandard) + { + pmsg->ide = RT_CAN_STDID; + pmsg->id = frame[index].id >> CAN_ID_STD_SHIFT; + } + else + { + pmsg->ide = RT_CAN_EXTID; + pmsg->id = frame[index].id >> CAN_ID_EXT_SHIFT; + } + + if (frame[index].type == kFLEXCAN_FrameTypeData) + { + pmsg->rtr = RT_CAN_DTR; + } + else if (frame[index].type == kFLEXCAN_FrameTypeRemote) + { + pmsg->rtr = RT_CAN_RTR; + } + pmsg->hdr_index = index; /* one hdr filter per MB */ + pmsg->len = frame[index].length; + pmsg->data[0] = frame[index].dataByte0; + pmsg->data[1] = frame[index].dataByte1; + pmsg->data[2] = frame[index].dataByte2; + pmsg->data[3] = frame[index].dataByte3; + pmsg->data[4] = frame[index].dataByte4; + pmsg->data[5] = frame[index].dataByte5; + pmsg->data[6] = frame[index].dataByte6; + pmsg->data[7] = frame[index].dataByte7; + + return 0; +} + +static uint8_t FLEXCAN_GetFirstValidMb(CAN_Type *base) +{ + uint8_t firstValidMbNum; + + if (0U != (base->MCR & CAN_MCR_RFEN_MASK)) + { + firstValidMbNum = (uint8_t)((base->CTRL2 & CAN_CTRL2_RFFN_MASK) >> CAN_CTRL2_RFFN_SHIFT); + firstValidMbNum = ((firstValidMbNum + 1U) * 2U) + 6U; + } + else + { + firstValidMbNum = 0U; + } + + return firstValidMbNum; +} + +rt_ssize_t _can_sendmsg_nonblocking(struct rt_can_device *can_dev, const void *buf) +{ + struct imxrt_can *can; + struct rt_can_msg *msg; + status_t ret; + flexcan_frame_t frame; + flexcan_mb_transfer_t txXfer; + rt_uint32_t boxno; + RT_ASSERT(can_dev != RT_NULL); + RT_ASSERT(buf != RT_NULL); + + can = (struct imxrt_can *)can_dev->parent.user_data; + msg = (struct rt_can_msg *) buf; + + RT_ASSERT(can != RT_NULL); + RT_ASSERT(msg != RT_NULL); + + boxno = FLEXCAN_GetFirstValidMb(can->base); + + if (boxno == 0xFF) + { + return -RT_EBUSY; + } + + if (RT_CAN_STDID == msg->ide) + { + frame.id = FLEXCAN_ID_STD(msg->id); + frame.format = kFLEXCAN_FrameFormatStandard; + } + else if (RT_CAN_EXTID == msg->ide) + { + frame.id = FLEXCAN_ID_EXT(msg->id); + frame.format = kFLEXCAN_FrameFormatExtend; + } + + if (RT_CAN_DTR == msg->rtr) + { + frame.type = kFLEXCAN_FrameTypeData; + } + else if (RT_CAN_RTR == msg->rtr) + { + frame.type = kFLEXCAN_FrameTypeRemote; + } + + frame.length = msg->len; + frame.dataByte0 = msg->data[0]; + frame.dataByte1 = msg->data[1]; + frame.dataByte2 = msg->data[2]; + frame.dataByte3 = msg->data[3]; + frame.dataByte4 = msg->data[4]; + frame.dataByte5 = msg->data[5]; + frame.dataByte6 = msg->data[6]; + frame.dataByte7 = msg->data[7]; + + txXfer.mbIdx = boxno; + txXfer.frame = &frame; + ret = FLEXCAN_TransferSendNonBlocking(can->base, &can->handle, &txXfer); + switch (ret) + { + case kStatus_Success: + ret = RT_EOK; + break; + case kStatus_Fail: + ret = -RT_ERROR; + break; + } + + return (rt_ssize_t)ret; +} + +static struct rt_can_ops imxrt_can_ops = +{ + .configure = _can_config, + .control = _can_control, + .sendmsg = _can_sendmsg, + .recvmsg = _can_recvmsg, + .sendmsg_nonblocking = _can_sendmsg_nonblocking +}; + +int rt_hw_can_init(void) +{ + int i; + rt_err_t ret = RT_EOK; + struct can_configure config = CANDEFAULTCONFIG; + + config.privmode = 0; + config.ticks = 50; + config.sndboxnumber = 1; + config.msgboxsz = RX_MB_COUNT; +#ifdef RT_CAN_USING_HDR + config.maxhdr = RX_MB_COUNT; /* filter count,one filter per MB */ +#endif + + for (i = 0; i < sizeof(flexcans) / sizeof(flexcans[0]); i++) + { + flexcans[i].can_dev.config = config; + CLOCK_SetClockDiv(flexcans[i].clock_div_name, 1u); + CLOCK_AttachClk(flexcans[i].clock_attach_id); + + ret = rt_hw_can_register(&flexcans[i].can_dev, flexcans[i].name, &imxrt_can_ops, &flexcans[i]); + } + + return ret; +} +INIT_BOARD_EXPORT(rt_hw_can_init); + +#endif /*RT_USING_CAN */ diff --git a/bsp/nxp/mcx/mcxa/Libraries/drivers/drv_pin.h b/bsp/nxp/mcx/mcxa/Libraries/drivers/drv_pin.h index 8b0fa056ae9..14745d6581d 100644 --- a/bsp/nxp/mcx/mcxa/Libraries/drivers/drv_pin.h +++ b/bsp/nxp/mcx/mcxa/Libraries/drivers/drv_pin.h @@ -16,7 +16,7 @@ #include #include - +#define GET_PINS(PORTx, PINx) (32 * PORTx + PINx) extern int rt_hw_pin_init(void); #endif /* __DRV_PIN_H__ */ diff --git a/bsp/nxp/mcx/mcxa/Libraries/drivers/drv_pwm.c b/bsp/nxp/mcx/mcxa/Libraries/drivers/drv_pwm.c index d540dc20fd6..f025846c47b 100644 --- a/bsp/nxp/mcx/mcxa/Libraries/drivers/drv_pwm.c +++ b/bsp/nxp/mcx/mcxa/Libraries/drivers/drv_pwm.c @@ -16,7 +16,7 @@ #define BOARD_PWM_BASEADDR (FLEXPWM0) #define PWM_SRC_CLK_FREQ (CLOCK_GetFreq(kCLOCK_BusClk)) -#define FLEX_PWM_CLOCK_DEVIDER (kPWM_Prescale_Divide_2) +#define FLEX_PWM_CLOCK_DEVIDER (kPWM_Prescale_Divide_32) #define FLEX_PWM_FAULT_LEVEL true typedef struct diff --git a/bsp/nxp/mcx/mcxa/frdm-mcxa346/.ci/attachconfig/ci.attachconfig.yml b/bsp/nxp/mcx/mcxa/frdm-mcxa346/.ci/attachconfig/ci.attachconfig.yml new file mode 100644 index 00000000000..a37fda06547 --- /dev/null +++ b/bsp/nxp/mcx/mcxa/frdm-mcxa346/.ci/attachconfig/ci.attachconfig.yml @@ -0,0 +1,9 @@ +scons.args: &scons + scons_arg: + - '--strict' + +# ------ component CI ------ +component.can: + kconfig: + - CONFIG_BSP_USING_CAN + - CONFIG_BSP_USING_CAN0 diff --git a/bsp/nxp/mcx/mcxa/frdm-mcxa346/.cl/attachconfig/RTduino.attach b/bsp/nxp/mcx/mcxa/frdm-mcxa346/.cl/attachconfig/RTduino.attach new file mode 100644 index 00000000000..b546b5f2c7a --- /dev/null +++ b/bsp/nxp/mcx/mcxa/frdm-mcxa346/.cl/attachconfig/RTduino.attach @@ -0,0 +1,14 @@ +CONFIG_PKG_USING_RTDUINO=y +CONFIG_PKG_RTDUINO_PATH="/packages/arduino/RTduino" +CONFIG_RTDUINO_THREAD_SIZE=2048 +CONFIG_RTDUINO_THREAD_PRIO=30 +CONFIG_RTDUINO_SUPPORT_HIGH_PRECISION_MICROS=y +CONFIG_PKG_USING_RTDUINO_LATEST_VERSION=y +CONFIG_PKG_RTDUINO_VER="latest" +CONFIG_BSP_USING_I2C=y +CONFIG_BSP_USING_I2C3=y +CONFIG_BSP_USING_SPI=y +CONFIG_BSP_USING_SPI1=y +CONFIG_BSP_USING_ADC=y +CONFIG_BSP_USING_PWM=y +CONFIG_BSP_USING_ARDUINO=y \ No newline at end of file diff --git a/bsp/nxp/mcx/mcxa/frdm-mcxa346/applications/SConscript b/bsp/nxp/mcx/mcxa/frdm-mcxa346/applications/SConscript index f11833c8d8d..b214b5a3f1d 100644 --- a/bsp/nxp/mcx/mcxa/frdm-mcxa346/applications/SConscript +++ b/bsp/nxp/mcx/mcxa/frdm-mcxa346/applications/SConscript @@ -7,6 +7,9 @@ src = Glob('*.c') group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH) +if GetDepend(['PKG_USING_RTDUINO']) and not GetDepend(['RTDUINO_NO_SETUP_LOOP']): + src += ['arduino_main.cpp'] + list = os.listdir(cwd) for item in list: if os.path.isfile(os.path.join(cwd, item, 'SConscript')): diff --git a/bsp/nxp/mcx/mcxa/frdm-mcxa346/applications/arduino_main.cpp b/bsp/nxp/mcx/mcxa/frdm-mcxa346/applications/arduino_main.cpp new file mode 100644 index 00000000000..c195831a77a --- /dev/null +++ b/bsp/nxp/mcx/mcxa/frdm-mcxa346/applications/arduino_main.cpp @@ -0,0 +1,25 @@ +/* + * Copyright (c) 2006-2023, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2025-12-08 westcity-yolo first version + * + */ + +#include + +void setup(void) +{ + /* put your setup code here, to run once: */ + Serial.begin(); + Serial.println("Hello RTduino!"); +} + +void loop(void) +{ + /* put your main code here, to run repeatedly: */ + delay(1000); +} \ No newline at end of file diff --git a/bsp/nxp/mcx/mcxa/frdm-mcxa346/applications/arduino_pinout/RTduino-peripherals.png b/bsp/nxp/mcx/mcxa/frdm-mcxa346/applications/arduino_pinout/RTduino-peripherals.png new file mode 100644 index 0000000000000000000000000000000000000000..3e3e41a6c4619df902ed7e5b397d1813c4ed7085 GIT binary patch literal 97187 zcmZs@1yohr7dLw7PNk6sr8|`FR_TyNN#P_LOA#%fN57Y?Bi{>9`(A9Ml)ZeggM^*1zm>L= z_KJ1X{)hb!LkXp)qS)~N{cs!D*kF=-oWShyXk+_PApi5T-svBv_`lz>x1*|L|Mw?T zq#Qgb|GgKSGFdqei{0bje=NkX{^q+k5~RiMXQ&|aNYm|PjlIil4pqL{4paA4YDC}3 z9@;aL<8V(W6^zAQcL>|XHFL}3JoCFo-q6y8yT!fgBMXb(kDHhEF)cLv+tKIW^$(x2dFuKaB?_WZG#jT%5IlhtS9B4wUCOa@6C!)vlFKxdqY^bk(&~y7J zXz~@@y1D(R_=;2%dmpQD9E^tDsnDqgvL7&svrh!A~REG zSkm95wn-Blgb?^+o+fy~C{5C1qhWUHzGy;W!>xJThK`^DNl9I^VZ6Mc<@NF+lWX%# z^~}U{(^vP&7CE$KTe1xZ8K%5s>o zJ>zX_sF!_@$tw{V?4FxU!qiPE`G3~Y$~E82TlKL`_NW%Vik`wa_P>?)D|`ti_5Tfz zpueBod!AgY_wO|>gp}a&8J`tWJ6V1#GCS+q7yn*fMagAV3xWTgSyhlnRM9pj+PsSM z&s$jBTs8kjkd^C2tw8lS6*jz~&wnvyG<3Gk>XiDRh~3jGY6C_j73S%M){0bELk$8l z_&oEn!^Tmi4MY_QGo~mu7+}wW?dDGth0z~t(6trzbjkTn3B5E3mV*Pu$R7G3O2)lH z?E$;2}usU%MF6W5-Ls#RWXCO?W|zn|v+M1HVhAli6ZaN((bM!`DC;AuS1H8KYXNV5O7 zM(~I{rSEEyz!;J5*MaK`X-Vho0kd2;*fC2v9f<1HrNX@K)0zP9TN)1-& zQ%BJ!1r-+U@P2dX|J!s{VlI^m*xe9;ozT@LUTrckl7RnB9UOMl3A=#@3i2Meuz<}j ztB?){*Yn%MZ7vkQxl-sya7(>>t8MsZh?;~B4SGu}J)Pi)?`w_t;z-?@8&9#@J1HTM z)lS{0^udh1s7T?gC36&`5>XO(oE~D^${Yl+GwdpJ0x*;4pvi≺=Xx*)ebVoYz46!m5@K zzN!cs^dE-*9Hgy13dj7-Zvqa(k(gGs$oq0CD-^{2b2P}${udLLVv}pP=C-V5o)W^> zv?o2@z0icWx{ObHVBT5vxbyCg{F}GVZ3E2DJEjJf-`G9s{!Tfx|I97?+QR zm$2`f&>EN8^m+4WKRTCoi7hERWSEz zf8!9u2h79&v2U3Nx(H&5o30!MA(=MK!A&zJQ^zr0QU?*_mKhnHzmI$Ee%W9io~^(_ z$`4M~+K&YM82LRc6A=AelCqMaD{q{!qWqW+(s9A}d5m}vHeg3n*^~1a{oZ$D8lB2A zJjNx?(1Wkh?KxF=w$1uc1w-jMX**|x@U~aLhOm2i0HPM!mM^~) zZLD#XWIBe}3Yl)!pg88jYpR(f~H0*rR=OIPAI&k>5_YvDF122?zdtN zPkh67d81r9sVB9&PXk+;_AfXRcQld(0^nOx*yPqMheXc*%>_=s;&M(SX20NOsiDdZ zX81@n#S(qRP~owa&{GZFC9zYmwbB1m>l2jtgRPj zm$Vg`oQ5wYhmm|+i8FLbC~z|&kP^v~`8!#Xt08gB;YtYl8<^lDed`yTd?N`J(24!l z=K7>U&=q&|;qDpDf+qNB*?#pUG2>NG^w-gitFMu>J*%6ebU2NaVoxRCV~b})kj2^G zj}lOZNcPmQ#|mIkQp+6&8{tGx`KaolqPQee1Tuan!h}uCz1(QbB=!Wkxqvy))l za&OEp%8KPO6z6`dcAAJIo4mZ|2l<|Pf=GD-H(GS8EqrWC1M%1R)Fl_1sXn^v*0>mK zr>aEAr4)ftN#V{vX+Z)3WaJM)EPAj;d&sZ+BUG+Kj(6<6>S8kvoar^#VX$%^lNpH? zTte4qUd3Swk7SE0!Ed^EQi>`&{dkYlPAS%cBYhEej~>jH@cHpG`2hP!QhQMsEfGN{ zTHs|nY?A3Z;yYzp2hNxWn&y`}TfWQh#_nOp%)j zf3M1+88fnt>*KY;24|@GD-ZI^3Lb;q`rIE8;JlLlq1zj6pXjJ3IiA`rQyaimeHLt? z`GrTFo6k~_g8NHhr{>^}k4y!c51OZ;L6;#r!717M9&|Chj6a$3ENx^NxI$Q%Ot1@m zO)nb-aid0W*6fC?yJ*Y*=>S-906Q5V$hmBFW>f93-YgSmpNT(JGum>Te=ibNRTyg$@-m41`rQS{vD1amoC zH*zv`AG-+GPS-ju1~L-Jaiz#)e013^%PMOxVXhC@{CbmfxR6NE3cWRyIdtxcdQAL- z+mj?cm{1elKH?_p^&?urd)h#bge2HtECtm&%m=Y}zVAJKsuEBV6=bF$vHf}NUWef3 zr$B=hDbaMW6J^R!<{MWgQu=_5?I;ZC)ru(NA7|=se#HzZ`0Cz3=x@Ta05GnMyA2ar&uN-jOMp(84>xc^0SnPt zf+1{=cZhJ)F9+j>-whaTSF^Y-B!~z_>M1BJ;rHy zXmlBRzG!*;A+jcPO9bzf=4Ln;`T7gE(DDiTH?wEXnMd}2EtuV_cfVYd9|~|;v|zb4Iy#6(_~9a14Elvd;B$}gWP52W^YOA#8xMV zsDXl=GhU(^K{AG~%~$2i3`)cM=vneMK=AA>F6hjyaC2ZWyjJ zTrn|-27WKw4;9YuwydunmbQz%)&&uV^NxT0t%+wwzK4rPh-IVC_*2!yS?w&{l76aCmdO0palsvCYaVJW;s!VB{tvBi zAlwBf&>K}6>(<0rHsZT@P`;~f7r&rcZSCJ%#B(O6n$PqSbb9ml^aI;9G=_Psp1>9< zHzx{{`0Fp?r!>{d`&+29Ty<$ycPUgJ?V_4Q_W7*43C{$SZgm)${8M2C*X2g}Xv{}R z61lR38FkGf5kQusVdu5%fXqwq}iK@ zP--guUSl@D`?BPQyCJbsU_(Jtw@EkXM%^-TQJ7a~ZBDS>(@;vU-8Hv3*!H|{O?aAeRNbsN70219M7aEiRj&t;#L~7N@`9*;gsQ}+0B31-SJ@4!1-SQ{ zog4+9EW1qz5r>n@LkzoDw^pCs2%mH8n_hplZtBhmr)0${jOUq)`FWSsOIy~r-89m! zrnXyyzR2Wx^DM9tjncDua-_?9@O`)wZxFiNVe}798iEQov~p+ubeC=$A`yuH;P7@E zN>2%?!lc*^6wI@e(I_IxKj{&V;15xl3&o_PYxb1P)9Sn*kBNz%5Lg-MTH%B|#2mD_ z%e5^NNwYt9zFHy;(Wf_LxXc~D{YB!%c1zf^DtgzOTeL<2PC{EL`_X_lTl~(fN0RF) zw$s_bX&3Rto>N603W`XU>1nPg2C8GmfxVadadBjlTK1Qe6GYuTUIYd;A+@FrIl&ph zl*seCR|{+%{VdrjEgZOf_^{PdaJtGAT7fXs`Y7~+MWeEM1HFf|7T+|l2V!ClBdCtd zhyN2XiJakz&@pj21Hp56~zo7Sc?Mv^!OPsEYe{EPF zn$+G>wr&r0&AMQ(lV<@(&GpYER_oCT)t}au?#ua5ylFn~IN&(#ar}-T`(?AP9o*`t z_@~~+S1h(EJakbhaTo$<*G(^jvy;)CK9NisB-rd%>fXolZ1oE)`$!5E?aF__R>^;p z^x2HszOj~PG-XKprDyL)?IwISk7E(JxQSV70#j~|p@y8Ksm;XJVJKDPuw5X6{h1n^ zLu?oGivJe^lcWMQcCh2lt?z5c{A%JJcXY42N}TiNgmH(fwk^&O(FG3&n5zL+yUnld z8j(V~f|VqbfC*jB12CbmBalv1KsAm$MfbN=kE4k5Rl_7FB`?Xs8Pl^glt#nSptN_itm-fT z6;MkPRB9Ho@=HH44KziNA`|v2%71>ce7=&o$GH?QP!^AS_r9cl_oN(l51@y3+Dx=V+U4 zdM*T@9lnRJo3CyMFv<12_I?&mG*Lo<+ZQEM9*YrhSLM%H6h^Z&&f#tBtgqZOE3qbm zDWL_>+}Ns~*nPPP(~7YwbxpY=QTQlRiqIpVTS|Jj0Xudz>72KdpP~&GV`of=)f(U7 zuGx-eK}@E$YCn$H&xP+V*%Mqf`Y{Uta=i8m-K3G7Qy+ihF({^A7xkNG$@XeCZ$^m{ z163Z)IGW#xlBEX|k%g?9Pub{k;v1t6Qxqk@p4^=gd! z|8f#Z05K*<%ibO3tV@N8VSh$11C(5NZmRfp51XGLdLSiv(;_QToUba*Z!09fFb9KA zzhWA8N1gu0e)#%dV(|_iVlb*NEcSs#)C#r`AGZhbi453jrp`LS+Y%D9`ZUldoBL#b zDRVVBTjR4|K*E6am&E#Ktf_H%i;kKgdv7Jb0;}}4-ID0MY^ZRh4&Ag_Q%&>mjFazS zi4U?0c8r}#5LO1jzk`_MV991*Ai)2&6}SACjSW`p`xz9T1Tb2t{%p=`9=7l9=m6+; zM*Gf&Z3H+n-z9ddcD;@Rvc|e(B z1-p)?cHJ!F05iJl`6!7Abc^dver}(5f&tC=Bd+{&14s^TjOE4nPe~3HVUv-~P61v_Yr{7=myIdF9gWcjX;)pwXv)tML zW9N6m30*dC;{u)7gI6b7iu^82&mB>4c5s+*pl`JY8YOiIwj@rrrUVT)MIusc9Hslr;TV(;Mnad9;5rZ;r%fQU$l%NLrYro%QZw1C|l=|p(cFM|kTij=O zVe?Tpo&cdwk(A#W^_RRsl}Q_*@)G~-LLG6CjEdNR01DF{;!MIcK+FH~u>dS6e3@95 zTG|yG6cM9-JR_8mq}h@xk-qX2-M^0Nialll-FA_?0{V5Xnp9mHj zc0$7x+moBItfuUXlx0faS6t89B5!nu@<+LZYJ#obu&zH$BLWDvc(RPU+yfFnSlQ}>WmOeM zTx%vM`vf*3V4g&ZS<~6Uy;3Ysl}t~)tSc6% zl|!!&W4lfvfIyMq-$LE?7cdv2{Qd|3icxS|v^8e&hYVjU-#_V%IU(QZ*c;6F@^gAM z!iWQpO=q*yWTXENWAkk@_K3;Y^9)NHjc;-;W7El!deJH)^0!=6Ba|d$JqB|IG6@3& zovZse?^)H8V7NP{Geleb*h^@m1`DnEu<+Nz8}jcOR)1TPUAR}qaN?MQqhl%wdR|`6 z>VjNI4LHDHMMNypCrW=@*$r-WAUdy=CjcBdIZjkX|BHQ;u8(Q%`sg~lLdV6XRI?n; z&9Eq$@WK}FemvhN{4&8O(JGT;zPJeoZ%Z`9smJKA%QJ*T8sxPli0LuKpx67Kx}sMUh_-33c{eZ_(#%5m|V# z2N0uQz~|PVYok9?7#7vmc%8{lf$`!)Mc(= zFu!fi9^sM_1WB+tMX^)A7;eeX_OocdgdkIlF*oMF^u^*t)dJUEK`||D=gg z?WZwdtuF5dVHZZjf$1Rc5qX7LPGakrTD0bBaq%5v)85sfUDoAR@TA}rdo?<2j=jG( zKfDDM4{ri8_e9jz0@K&Vr=2fsjQz)##>&_Iy9037D$fjF)6a_c6FSR$<8pux+omEs z_!eOTQn(5(}mXkh)Z& zqm^b_0S!XnXO7`G~!;7PtqE1eWa1-0{`>kuO5G})i7GCf@rVW5ue zhs%0GIgeKhS7kY2B|nZdK=G%KEd?>g3qQ7>+LU-<@aaUyzTE(G1Ia4O=Z+LI`?|ow zklcZmI4cSGI4xW)SG>R$WK0xfO@^8UHpHku7z;l>$OW1@meeO4vzwdOWlXD%5$A!E zV9K87(exu)ej+XPr{eMX*EN8=H+sKw22M(~0W=6;TV8po|9)zFcnODz$kr5+AV#Y;k;-m0Vb>vF-7+ z^Tc46^(b9V@K18<5*G#y*^k)|MJ&CzQjO+ad~l-2=dA7;p2T%&$(je zGk#+3XZz3TU-tgz1-NU6eY}9KvQeBCqRAw3&L_?Mo5GOD zaKG7O-$&SjAMZ68%Nu62EFLmbE zYA{Ov5|WFfKIQlt-lS1TqPfY9@uhwxbRHDsEaWG4;8gfMz-bOBb^937aUH1z89A@l z&uaG~x<_S3Q=1=CKBHOBx%x8}BK;2Ru&&>7A1r+1ypOxW>+59uILqtuc=pcacZW^O%{SrllB)SB z-r&G;f>~N2Q1UznFb3|njJLVaLEjZTt&DQgO|NFy#i!sdwqmSsyPID4S8iO3e+tX> z#{d8u&X={*YW_}SrZ8CX+rZNmz4-UQ{y0-yuQHkW&x0tR%TnoO)gB$afx3pL5qV<8 zL(&vBwi}ZHIpvmxlpSS%%N^hnk}YM(-Q6<%|cIV_o5JVcz-_ z8|>T@P`yTY^G4L`^RXEzG+b*%-RS#`vGMW-VF_IU$$q`ltTlW@X%w^N=C%6$UHsydp|@%LBvF+kPEhSq#R-^h`1Lx-2KFC}8HVWum7$#B{cQ z#NW$$YugNN^KhFYh|YSnw2@Gad8zMHGf85|AsW%^rqDlN}%}v&yZs@*$JKppn8AzfpNPRKw4&p zI%x!1R)P5=eu;eEHFq871-$4K{-^&0Xddp@KbC;`rR3orXv{O3RDKj`P|5aR5g1_6EUwUFe3b;5+j@QY6A_nncTAXYPb6e zxNMf;ntiXmmw?Ls&oxF%P#&Q;6L39!?Iek#+ttfLo^Rx9-kUE_EE`t>6>8WC${o#$ zX#YjaH=qCqV0dcdjryWl{pjfG*b*s#yZ``Kn0~^ASAq)QYd+sT^V$Kr0+9K}j0*&& z*sU+oApnkfm+!Itx*l2tgbvbX+0XCpVK>g*%e0`pZ=kb)4mr522h{z;o|0|0*k z1n2D>w5EM`ZL&^a6@g@y7+v9V?neGFRCOgq`aw)^}NKca{)S6k*68oETknCqiQuevIj)DurbPhzY1QlWz{ zREp9J*y*!0=Rzj61;XeP*)?QwJvMDuAdq%1#1U;yZ(^kKpt$y1_LIP%WW?bwJzBp9 zM|Qs9{(FuAMp`Rtm!?XGmFb7u_$~Lj3(F^|fv4439^Qw%j(Tmijv36;-?%LGekiUp z3x3qSaB!S|U0vy_Ra?%ftnJ{)G_toyi#DIOov5Zu|FLnG_2tw>5RxT+ zy<7WKdHj~VR;u31_K^)X@A5d|g-@#osp|el<~%?t27I9R`C!_@M;@Wp;4Q!xg8lc( z01eXa+8F>a$b=V)`#XoVR_A*zAaAYJJ%5vZNI+D_`ldF(7O4N;cc&V4iav-#9-P~b zDa`HaK$@>y4PQ~yz_;2nCSojm&SUZeGxVan`nbC2wrA#Z*vPa|PGPr&I1erCbvo%*wL&uLe zLrVgL+|Txf%pV>zVPdd)bisz9ivUgpXTP{-fvKW|0RUJPUUG?>6Q1S=gh&bCX}?Xa zWu6}%n0y{K$`OpJA^dm{2sqa1s?FCrkL0O7iMy5u%P{=X8E?ez_R;#v6ssY!u7LlW zgsO+c?)_*Iqe1!)CO+Dhe~_{a@sS8e>A*YxQja9jz9J8kWd4l_=eJ&;^k76DrbHSk zwSZ<$?fv8>xj){X4E;)Iu-VJoP6VT~Ohyu-RRvhT`lI4mrWczqbr1G$<pPUN5L|uvNvVOtn;-*8rsmgMlP5~(&v9y>>BMeK z)$cAi&7%j|#qD^KJ$X>jaza){T^7fPLIMIbl^;1nIO5|mlN`hL3H;Ri`p>6VR-L*$g-Vt!{So$<(>jh9H zn|2{W4r;6cFHwDCR(8Ac4>|mGj?upf>0M2KeSiX`o zCZ*yCjwj{@BtKZ`HdIa{LLP3TKXOft?423RM5M2XKJ<^`o3fo=;S6y<1I#H<+{fA| z${yeHeLCU*{o=Am_l{>9gJ=DI<-f9 zfOq@Q`b(e^XvvPekwJ|yNfY3!L{3854C4wqxDJ!5vZG9~FaPzK#l$E5^ph6LN3tiu znWGpTOF_tV2I{Hz0EZK7t)*Ad+^q$B1R*7cQ%_cm@DgMitJG^U?9$8%!=~a!V zw?O;ngY^#3_*{kJaNg9RKTIX09y2m6{6*nd4!*8ei@n zjM!W^+B`-ugZUbnP!Z<$?2x;nhIg-#L8U5rnU<`e7K-{|kn0M9=Cr2~qj>Lj%9>8} zCe(kx>ZqCjta{=ajZpDAdVJU_Gj(#rVNRJ)av}q!z~U!tkwOvm6y^8t`I@1(c(&5f zFF&qmy8JLxK$p#lDOVe-`^3-7roCg6>sb<_^kMV&nJf-*Xtqo^9r9qQ48jDvLDKD#jM#Bj32T)+Jf>rq7Py7vaCCibf% zREWyH88!q}#UV&_Yiwv49Ltr^LVmpOtyLz|s$PNf=D`vzV#UJ~CD5^vjSvYCPy_bB zp!iT#-W{vT?}ycj`t&RO*h8=4Lg!o@OsJ7tvUpRjY_GYQyEL>MJGlHaRqMIVRRLE? za^yd>6eQym;O{0kZ;ym+J7p@bhY+ntpwo&IuHjqrYU4M|6IV%#!x~;hjPq<|ug?7P zUkfZ>e{YE<3TS=@t2(h?ghIlf$RB~hZMN3$wN05i5_^bLhKmCAHj ziAsX$o&%YP`ipc?ZR5#c4s0C@>P#Sg`d<9!-YPF%`OUw9pOq3nZ@8Lt&Qx8(tDNEp zFnbZY+f35*)RTg_dh&eFM75>o^&GXLZ!v(60b(zAt&dDJj?fVx!b{(vC_7ZPgqxP13>b~S3dU84E zO7FD95+!Vx2GJi3wD`*Jz23Lu`q(6LjZuAyNp0|N%AXJn?oXz`y`{z^o5{;m-Ff}~ z?H?EsNU3n(I9Jr4nj{G__GSuH0T({CCX-hiFBUdESI?1+T2WlOW<*ac^gdWJy*+() z3K1`Ady+~#RIPMsRCOBx)R?-+lNX5j+HVlT@=yEq8PDy~*XPHlnHBi2o`=pbH+ zQ1Vop?AkL-CsBZqSz-itDPqKLS23GO#JvAxwYK*;6<-?oB5kMkzLcM*lwx94IJx7r-E zM$@P(zhN3mqmN&VtZpkwX?kNtWNuo6`0J;+q&=;B-3u1(1sr9I-Zy%@*;flBIyzm8NcYMm_Vw;a%tPch^;USQ<33ykAC=5SkAki-t-vqknIFK9 zB0(VV;p=2YDmv*I^~@9h$E12vIjKUgDQ%H#-r%G%_eoTcu27!i#4TOuw&J|6EAO(v z?@a$N)9%7B`_4$EJIKF7)1>kZtwk@yNChfB&B463B*QRMl7ZLan~J9UlR2LB1BH+eymq!iz1eT}_(+~jNc0f*bk zIl+5!g>EUzdNpJw-rP75R)^qZH%E!?suqdMzhQb!<_}i5-N;^Du?yB-ivu^`K7wTI~J$_f>VVS-4soLd116=>~hsX`<_8VeU)xTfuxd zMLEw}6NK{~rDT;A`!O%VoATm4p(+y!V|)2bwF%u{XlCbLN5Ff;jOPLOX(M~(T>c1B z_mu}X*rbl+O_DV+72`pxx(y~CF%^cdD&j9C9y4}^U3^rxl=zwQSGJVt7Rv!Z##MV1 znqTYou62lv20#Jo<$5R?X-sv*H08p3dYJ`;2(`x#AwN+ZUf5_Ft8-e$y!-IhZln1< z_i9WZ{O~I&#?nCzNE%^ZPg~5s*07l%r)6SW!{GuuLH5ThoJ9@#`xqEf4y9LcMO0Mu z;rt}jWs>FE>i#5U^EWRvyjyCQr=ES!y-}ob-c$(iWh-OU$F?JuT^ z9_7W7sT}m|BW1xYR!r*m96nUm<{UZ<`U*&N%TeL2cyWS)0u5-Ct&3i~Xzg33RHhAM z1Q!q~$)9rd45w&3j*>f4mJZI&z)0~Wq(;$a6DO~pb}6kE2VF&bqhR=b^UcOd$x-!; zb;X}>>xuVIf}TzIWIpwlX0fp-Zy@}tfmJBlDn7i*djM~kf5I}og$7pL{ zYz7K{(a|R)$fL<64|+tx_R#V@`6DsXex%`AC?b=WZlrVsi)Pa#gPAQ4xvpmP@2mUf z5%WC~3Gvxbwf4WQ9Ce$(e*xHqWApnw{H?iIInT8&0*nUlIv8N<#4;WA?uvGP&=WMP z0WA~?&0Zmw1>PNitbzHF?713HJZwL)tCtB2eGd^+TTHD<-I{bT%=FJTTQ+YHJ8)cFAh>q>_Nw<;a>rRO5R~&6 zJe=|{>BJXjIGtsVSelD*pB#R>oR{Hg_K4R+x{k+)4-Ue#$f*cV=;|e1kFWkd zQ9IK58OZu~SBBJk&dfQ66{K zB1dsn;|xpf{*c@Gmv^nlv@^sUJhS0J4IDOAm_NcKNJ69g^0<=$m7-CRyyh&JfBPt^ zL4ERZVkM+={zZkf5)a%5kKTv7zwHGsNpElDzc-}aRw}hFS31kysI8^*QyrI_{9Gc1 z>i;5SZ0ZRE0-C@pV?_ov!3DkGU(g~-)&{LZ0m68X&sZOfczqtf9SGIvO0;?i5&mU_ zwg9W;$X1_1-BTKs&`TqS1Gg!NU4cU-{zl=qP4VX!epub zewyHOf6xi=4>eRT0B9GbM;l9v<+obMeo_DHMVdR6k=LNXJhGnu=XF3aX;MR5dH}cd zOyF-fQO^e`KaIpsLk;DmmLHB-Ntkg(1^z(Y@|GRIy37u$bAwnT{65vLG_<%Mc4+bWye>#M~^Hm)|y*zyX@>LpG-svB#zJneCAVC$R zFKq$K#)RS2VAfQa2fUo;{wFoFK&T_7$NvY|eAw+~Q056t){>Lb9EZfZBUNoNknT>>Y1o+xT^$2+?GkG6vyx{&o+@(PDr~waCW= zA#Mm5Rlw!Gon&5ynpcb%IW7&Uf$jplB4OY{D36tw{0cB^zko-@ z+|okon03Ly@Yz4ce3iqYC)TAOT%UO6F-H)MJ3Jfb5tj*Bwehv56>y{{l}(o8U~Mmhqxe6T7Y1%@=# zNb<>*+p)i1n7v+!?l6dj)cEdGdf{o}H&?l)&y?zzi`iZ!hbin83h%4#5!Ed?Mpp){ zJ*?lNk4WpMNJHC)JWQ1iSyLlf3>GItp(z?oKW%`PSl1D*rALvXLN#@tJSuzqSa* z^PdPGdi+{esP5wA(DD z40q}r^Qv++U{LAA5b;?7mwp$+4>7WnfKGaoLX|J>xJtZ#Ow^vsqZsxBvrAsJJqogV z)&Y73`|c{^HqPoUe2g*eR@{)=s?v(tcyvf%H9@y5d^|_0Y2K^qQCY2NFEkt@7SzN~ z``YMmCa9l%KC>bhp3}npQDtjm2J7B9R`2`WR{7zgq%hXUHC3x0PN| zQ}!uEj?ZSpvco8g49GN7qMDpg&hTs;0dR&sd5bZxO1Rk`|2Xa*gM|lvyoB=V36W38 zea9X;%@X~5S=ml{?jMk{iboV8Qnt}_CX1RxW zD>dyY^jFhdNJEUa3BNxW}UvlPI%PzQse)K#fO2 z!uO4zIwpRbPPb$2!K|55WM4~G<276T$0I-pbZ6un=?ekku9kIJm6Wd>bLaeRD=!!i zZjf>$KID1A!|}_Eajd;0T!+lu~clL$g}!9%}%VMF{Z*yL*q zC50UwXoNs3Uq-G@8UJ-x6cMx7*G5BCp+WhP($|2&PvP;yl(RdKJZym=vTm=U_-4-O zEs)tnc<30bMp|jgHcIO{QOKAkeUmaIU0JXINzrD>A@D+Q1CwG^#uu5wptvx;k3M{6 z5#AAWc5rH`o+gPTmUev54N42UkaxM^%;(I%aD|7EIT*sa&NqbpSx6L2e5X7Iy95K@ z^fkfy@EcnbEn84OlEtzy1VzatXhIh34rR#YtemTH`-d6wkq&p4lmEo&a$z zr$C*x>S*P5pySf{!6o%=JOvhJRk5fZe)_t4(O2toni_gHEk8CQ7pFKn1nANf=0BEz z^Kgr3e+MXyNSnTf{7`!<@XbEh-gDV_;g{}R_OW`K;1r*^6-JH1=$^RgBLqxfxQbF%l1RSql16B#9q1$kt{`VxJq4@^V*+&e;6I?*jN z(9V+vfMKHgqBJPqOO)pi`njgL+8P)(GvovB2@5I#@RK0bAEdgCAz-@7Zi#U{r$U86 zSrNhe)QIf~XV4|U!E@Sc|1752$c*$mZ*IeFmlk@iD+NhsCP`9dm^dT@5q4?%$GZ9z z{*r%i8VXgFu+ceu)OM#c(r|ZWaU^$IJjDn9`m!>FZR`B}*ZD8ejS0KMdhNLJUSuS5 zSwzZTx}4a4z!p#69isLwgBzyb4KY&?naXBPL`-_c_B$|!cjD1_7LwMV`OBZ{WG~W? z3xnpKi7q;E$PK|Yev2aB^vyJnoRjMTus$8t6gF3P&I9(s^r--F#ihcxg(L?Rv~ctI zmM<5&-pSoxIKU9(CA^gjy=Z<>-EY$nkN8P(Qq>iIzD++G80s-V)ue_#fPAL$<7QaS zvt-?K^Yg{^$7pl3wb*CE&VO3E0Ho|7w^v6jNSA90?L)G4h1gj1>K-J9z1GFriJ-zn zw0fn2-$p#Dp@md)1YdPAHoWa0*o+m;gd{XV>AuWIo!jBxY_N73v(09eCy}%+nkY?% za6J7{4>wM_|GI|#ihJKvVb&!~T+pYBc?qDG_?y`F8m) zJAPX=bA@WO;ZK4V2X*gOwvf#_286hwwCalyg=LXqkEPraUO%fhZ&SXE%UKq}{Uubk z%2!JIXv05T_V0WC1SXq0#~`G|CxDM|R3-m{ggeQjQWiTA=6n}u`nB-;r%+{gCL%}L zLxZbhu9WZQfWtyoNrsY^f_XCd23blH{fBQ zD$%Dtd@AjkPx|dA>jJd_*KB~0bHL5vMTd81C4Q|HkE#u;Tge{-+bFt%`;h9QH{9)r zmobM{c?m!%FZ`%m-}1QA`<%47kKw2u)XBv+YQ#}9%CgSUH-z_e8aYL$(_f)H%XqoP z43zr!KBJvnxu(SQX?z13#>~GXg7o0(Rwz3PbTg5BY5dDye?bj@%d;dp@9AL z*NWPGdThA&!j754Q9V@d24DWr1$02*T8BG(M3oXEu-bL{+SJ<<0$3@a(QA(f`l zl|P_U30?C$_bLsS-J2I^rFBIKU?zv6&($Kop0ofVp+tJ>XXtktA3rjTs2AC7 zPiaA4K@U0+Ul}LO9ZxhPI@rJP+G3vOjGad{1FW<8G!nh_tFN8UB=029mG|--&6v7H z$~+S|jXWCr{FTXXXN^o#=MIqd2OO)}LTIS^%@HY~kYYx5sqBl&Yzc5zMAavkn)FfjDyD;&h*iMh0V zj;VyxgTAl#EfSN*IFtvr9vx2uDFGalP~y})F6H^_`4eRLN8|FzG6FOabR zV@6oM^in(ZD}YB+hhyP8AL#>4Z|}YpXIb>|T;l#?Q|aY!*8WXa^FiER_XR&mT@#cJ zDO0tX)lt7@5-zE+`hxUXQSZ5YQrf+_6U$D%VadS$=dxJ3trwNw#RT!&%*Vb8mNChW z6Qytr;^ITDQd{%drT>qn7FWhPV5-2HeX~erFNNJR2%6~Eea*NzQ&GoLN&jU)pbao- zKeZIO>(>FK%W-vjap7 z02xDo!||^S;{N006tJ#iV4}}*fY$!${BhgaH2EM$;k@VpK!^dU0RM`3`#+^*CYHVe ztsCTNxjl z!{(eJfDM4hN%Y--^lp8ZOz}LXf}^pC0VL`gCv%5wb38h5vAG><(U9kB1{e}@Q;lC

Fo9bG=4Wc)7yw`8j+*`^Z>$M8+w1PB%QDB3&k!-TEKRX9&=!Kvj5PAOUgeYs(72 zhEPCk2m+*=0sHVJkm$M{IMZb=dN27$F6q)NXife!pp5`Evl2p0-}h2g zs*!EbI3xZF^lGTWS`geZ=NeUks0X929av>vDfsGt*-DCaLi-P3Jc0U630u?qF8N4I z{-dATWKjosEH4||aC=rGK}uem%%!aXxs=f+HoKLsGw*CP?j5Pw8+tH$Oo_T!J`OZ; z0DyX~oh2DZEeY^UwuF9X`-DCjc~oLGW{&Ue)xY?PJwu%N+7XW$m9QW6EjH4vvX1vI z?)_Zh`CQjpe{JNua?ppg{GQ4r+jjYJj&Q~g^H%G`hnzdS)^A8Lo9HHZl~ra-MVP#t zMK-GDe6@aPe{YDMnW5mSsElLPudkeii(%<#)U8`)Q|8uy!J_a^EM4L5Ow!Y%kUwr! z&L-8fI+R~=?RRbMp8_JDM;J-DQBAEi1IYjXZX3Yq0C{pCS^~H;L$8I#mYsLIpZTA! z-2vc034$Rmnf<^D-v>0=I03b=@XcN8bT~ZUx8=kw1hbwZ1Gc;i3&xv5PDF0IO`6pE zITI4%OKxC(T-CioB4YJ#Z=PGhagb|jWtUy{a3;JcLDIzm>A z2dM)9KQs?c35zTOZ#zo&0Vr7dvhCU#?6bv13|}N~?)8am|G+Zm$5BO;1X(eIypiDr zF!Q}hC9@@`PO!h6k#b#W4YCxwsi;h#b6>Z7ZT#Gp7R8I`^mlDxZ3_ z(N%s+?2Q6|d6kNW7ldT81!?g-J%krX-aK$o5$DFDp`(6_lG1hGaD~B zs{(C$z(ObnaJ-~vJW#6;;FmZ76Ex|~|8A3|F`8lO`Zek8lNAAx0=trJ6SFcx^e@)| z%EB8;N2GDiY5U!vZ}m)6SL@~?NYp+lVOe1w(w-Z{J>BNe?v)ZTudE!+bzpUH(d3R5 z;xcm8U|rzhIX|NPNG_-t_?!HLf{+ zDRY^;n0m}CwRvN|{^m@Wnps0%Tq9y$Y>1x`UD)bteQ!|9qUn|9mZ|6Nk}orfH5m6N zvUM|s{aTe7%vZ2CSNqHJNpqIVPX+JhKZ#OQ!CBy%XD;~Rt%s$f;;8*b#)R=6H%=Ed zqMNbgtcrb#cWE>N=aIQA%eEmGc=y>gM}bh_$A$G>q9Jho&KL`Nu^g}jI56g>OcLm# z4a&q&m8iO(x%r$ZEqH$5BUa({t4X8D!bg#OE|>jiDitZshaHXF6SQO2VF&*0N6IbR zuVB(-PebKvIJZ3v+zSV35j$6AmhE7CRPZ#1i*DGp-iMPD3xO%E5>CigHm%70p~dQ= ziyd3sE2Jyfw&RBk_SJY`j>ZbXE1}x1O^`I3=B;{ zGpL?44@)87{~r zz_gDM*uJ!(o9cQ@5p3eRmPmYgB{=c zilL*;sr8oNplu(sgS;~<82D6$xah`iK7GJ3S+*BNE!1#Hgcp{6U(1)#P~4xt*_nSo7cCxG0zRfTk9Qd-}P*`{yF~N!=>PC3az8>eo8#y*uzvT zzHe^_Z)OByK&lG8B$l+MA5K;{`W`~lBaA|pKb{?2vV8d#j&O`gG zW$!E`rw}gFjK~qC;nK9Zhx=CSL-lxo==Ad)3(@$^(ERXB)icsiw^jzPYqdvDFIp(jvFWeJ?LG`29Ku9v) z8W9pc#r3M1!3~4^&aEEl^2DA(LvI(w?LlKH^~!Bj{5dTaYcv@7m=|G>;`1dG0!8H` zaWALh)x3gcbrINi(%CA{pEiG-6hi-Wry$Yd)C#*}Fna9LP=%w#A3%qv%tR@N$AJ(3 zq@s+0OBsRACIJsX_KZFt+d835S7=zD@hVwMamiOb7E{9R5e@2wi&I5kht6?8+qX6~ zPJ@nwk_pD6eZ3_x)P651p0ZMc4?+;{rg&=oMtKy+2p3L{oTxfTk0Boil5< z)42tYX$qq24LXvcxDyf#>CKhK&!FY|Yb!Vn?pBR8r*Pn9qKb5$gY zgzj7&A2eb5^-;RWUet$)xOodNp7p)@rkE2!9`q8}GZsHD*M%0wab0H9X%|-1w|WiU zdUq0c5{BsYoIN)KN;o;J$9VE%@AZY(zSpMOBRH{&ExrP#-;sTb4e`3@xYO#x;{Ek? z!`QeSQ{=|sWb(M2cdXjIYZx-di*N#P#pTO?k(0O3&%MeELg<$77U@z(M^?LyTH`*k z=;-5Sw=S3LeXQ$c*pG4Aj)}%B>n8p!3`YKO#{-{3+%k~ql(yR9BaDcHP~)1z2F&5Z zIlfioKW-|cn&zk;vI zh}X;z!IK?Xx5lv_9J>w(pI9MV$RRJus;5P5EKH3i)>XRT81l!TGCmX1Xh@HDI)8$RDtOh%@j362)O@Rl-s+swU$VH>#!MlBR_VZd zy)^>+tGo2I{kCc9&uMPQa$%M2WRtrGK`_dv0Q)L#Xq&Bd1XdOSCa>HbXjL z?5<!DY=Dw1N4o)G`=EhzlFog@>grm|ZQG3}E6(y0? zD?Qk&BT}*6g$=9QcGAI>-5JdPk`)opI)K3Q1s)o@p1dD@F2d7AAT#;&yO+vENVuYh zg9lUd;$aMS{k{4aIjLp5?<7aD2kk`f)tzcwCKYt#KRSC z?l|@>LjxZQd2as=&Sv42oC-a3K;$i=H#*C*$f^ho2pB6rTVy+hs`*3M3t&{Seg zL@X8S;Z|5IEq2cBJZyXZPLfokHA3p9e7}sLP-84Lw?Ar5uPe?jE=b!Gn2$L+D9HN< z-YD%-f>3DP;_UaQY*7s&1z)$|@j1JyJkC@abzVdIZngC3*JI~qRF}Ye)mrHC9!#v(J^pTFy)*D9$&}q>$Q=A>iEKoXSh?c& zuBpW><{PDv?os1a0nd%nzOIN_M zXN&cer77=z-nIm*UwMHyQ(&G03H5VHr~8CSjANmJaMbdJT@opeRFwajkw{&Bxkb49 ztK%WVo)Y_-7{~P9HA>(Ie9=6d9{%drygNl!WBnS@6}{CG5w6^IWWt>%ON?@UNY}bn zW2`!coY$ZRYm1)-bT@jl2T)UQedL}AOB$c+q~*MCGDop$tE&V-;|k>+^6j_dCUyF^ zAak@an*2@$9~hs(01eL*ym!H!UX3izaRU40eYtEl{Et5*M~3H$Gr2x)E744OS6|X} z@VJ-fQq^m39eh^_?}LQDGoS1&3K>aU&ePg)rd zFTDC*SI90x!(FGA0}ly%ZayatZ%9*IsA3%h+iUKt6H-llS{;ku1~}|2{cI=P6K7)` zHdll0a-HgLUY+%pRA{jfLS|`!14%q@u35rA3Vq-BetCYBI5y$2Jz%!!w?W~S}@tFqzKsFqGyP%iM?C1~?=@7DPiRf*o8 z4l8J2K%)JA(|c9k@#{N?>p_SAbPqa|^`u(JcQO27|nq|DRjW~EG8AG_wj9B-tI95}fJ zWP&vJkc&PazpcgJn;8ZdYKNoLd)`x$>fFemlIvfIfvb&O;qnKV zM>QTr$PCHp6Bj_N5VNOXY0CHSn!&1pWpS&$0Te>mkB$MetZ3ZzlQnGiMqpjo9VmG4 zs2sDm{R+$yU~Z5k8Vmq2r_uZE{pI9<*u!C+#^sDfmA$n z=8Q4cs9UzFc+$fmFX{}973J#LSlPwjL14MtiJee^=%nZe>~g5=*nhlVx@?YqSgErg z8sT=>zuneWALsgp`$TQoEinxDb0{JN$#!H~v8nUnK>cY};>nAOX-xPN#Bg1GJBnvO@5QxD0gbq2`R zu}pgfhF^Gct!oqh^cNhaRpBgP`b>OZqzlh{n!-T4utlGB=CJC^{#a(XY$*YqUV z0#6?iTAcT*$v+X|P=YF$Sm!;Cba_w&xv)PeOpmPu-#`RAB50cp)q^(dukv8j)eoz9 zlMNj*%9EqDWcdNrldj#CBxSYyw-elhM$RDGvaI_eFF)4Nvxx1o)a(`{J zC(=>XtGJ9V%NIKOe_Vh^%WG3C&$SVD^X@?8A4%F!C@0R&V6YG{_KIN4QK$AC#NzQUJ^X@On}MiJ zAx_(uki56UQeM8zO>8W^ z&7mt4s(_71`|wIf2D4X; zMBL{bWW2iHpkOcqKCXCHo%)gkw&TS)n_I0Hf-RUv?#^E5#AvOMeEU76s05zHpS zuagyGnUbZHrIRni-^jBE5?pRa+MBG#k?ehLgT*@r41v+OdcP^T#=)S*UPo0Q0jsYI z6dY`TP48?elIZ<~7nHqRD|CDZ-hqjo>oX$YEf8#f*>#w>#*c&oaV7IxTM(Txl82BA zHKEmmTXa4>WbF4l+$lr#tNXZBk!o(sQ&n7LSh^lYmhG92=+fvi6iXRUyBNI39*27h z)lGrUGg$GDY5ADkl8==Q6Gm90vt11Z!6ET+C22bzo-m1UKiPJLuP7VYK~yUvnQ7-o$G4*MI}hKA))COv}XgmuLb58%6}L7R}f%&^Xtz* z7&~$^=w$@AkT@32&5ev@3S&VEmE}r-Hukx?m6Q!C$YxYcRCEvtBh3*JnJf@b{<4&c zSCsJKdbfrA8@jJ()i7-|Tv{%ng68N~5plXKu#4m>jTSxX2Vu+#i?=l8tgJ6-S(;y6 zKLB?wB3R!}jf6lAK^HWCaK3vql(jEh4oo%n$|n+Y3bu6@OVo(t=mqXblBX4MXr5M$H})f8(ea z>0I$5p&^sXBFg4>2Mv6m>BlUP+?_p;VFZKoLZtJu#QF*v9xnqHf~{x zjs+ta7{PDWnS7g={E9Yt6+-^p1>Wh9jo9a{%H2VQ3@L6qCA6YCml5P=b{@yRmAuv$ z3eI>>z7;bTkV@~qYShYUK?L}sL5}AO6@;OhCocei`y86bC-zO`O58t0F@oS)g0*=j z&*3n4D$y<4#Uu(=MO{w?&eefi0leXg#tZ__*ut0>n#^S1C%AS=OV9F(ixW9&n6z)X z9au%HUQUqSj@(_Ef&Wiu4ubJ#4#F7J3m_b#%a4>9>t#m^a!!A@+e>q;2H^Js1x|bK z@X8E1#>cZwiLv&5LML8Ny*bpQ9i=RAAwqB@EnU)#cCcxdfGK&Aw8`Ux3P>I4Vgo4U zGi)vIZwWHI3YwH-lEl8!sYhgrXaubt6Fx-10sUP8Y{3a!0>_nS`hVjMRb`i2?8C^b7dVemx3* z3K&drP84+yFq|YHBwUQ+Nm-S4r6LqF@ople71#}N?O3UOM{6&}{DYsm6I(~OT5hm& z2!1v^IO^a&S9LicHn;_^XsbnnqW}H3FZ)srQ&q4>w~S9Q%}rSDwv#Ti(Yva@KH8z8 zH|2hp!XeCmTH55?*PY$z4WMNR=oB46p$=Fw8wSIW(zL`!3Cs0>H-UzyrD7$9Fh6FB z5$rj@8>^$=BVRSuN9!g$=NO|Ia0@BpiEhci-LDGc_z)oN?^}VxSD{{2yP5!T=7&H* zHyk3EAPE&do&L)J%-;h6qjo#YA`r2p^-5ACXrAN}%O1;J_ae2kBd07QH0|1637FoG z?NQ7dTdHZey{EsB&{utLkL%PviAhL)zh6F3jVJBd!@p2AqNfoP+=AZE`T8wgJ)Dyfe&gga;H=^`#_8thW00eNnIk;IZO$?pV{4H-vi-73h z1aF7?#v2pf=`a`$Z~7v4nthKtPee` zNCCLU6z3!0-J^T^twg`dmeQuL#O+Kl!O}j}Tjn%&LA*Tz?ZqDFFoIcafqMRTU;!Uo zNX(hE?0IAE*BODps5L?d$CfAdr2wi%2*QdT)lU=2H51E%6vgIVk9kbEY3RG8>M|`N za9EQK#)8kn!waKi5P>*sk{M$mf%Cr^(O5oBMv{B6hUOt`_YNKd5m-i95i2I~)xw2t ziRrW$z6=?PkJ!@Y$%vSa_)$7_td*p-^1A@$V&fa`7irMTLK|kZ8`p=6^G1y4=p;nx z5c^riSWO8kjpSG;2WZoUBU|Np0bn)taNlSBK1zueGDlXm$E6B zf%F=7`hJrniw2W-_v)E&tAd6mF|#!Njri5*G&}P4m@H|(^qWGqo1p~wp>Kc>?X)3Q ziPeBA3b^HHZZWv=nH}fo{yK}bXq1zk&oYTQHW8X#StN+l1*&diW6%*p7oBi%x;;r? zp>t^*tsi&IIO%WU-gokVA;wJc-PNm4nXS^RSNmp3603almB^oDGiYFUSzfNA1EabS z_-1nwXLig4V}sbEI^PgNtupAx@7~A%_B^)w9vY9g`&&q|`3wkLwC-tGUw5RF^HxVG zA_AYCDK(&Ou`ha zVao>t+{F^UBG32Ytaa>pLdTD#W>GZx1fdX#N-63-C-O7+c3dZ?&XDN@0J>o7(nUs_ z)jtHBg9(nJ!Dh&T7b8zuLiI{xJu3GyuZxOF-xRUVP2k&jo%n?1({Q@mB~QQlhw73C!xgC6z!>}{*XbU6aScu1c6 znNkUw@UfZdWTD$a`-rW^Rmo!?GEH~Av7S0^lR-Qe3gJ7I)>{G9-#SDfb9)?>rQpA# z88djSw8zh_Zs@gJg5>*zXaf~rrrj_}HIs4Cu!LAPr?6k{uz7Sc$;?hqme5~rtvg1p zwODnEQ*mirbYM`meH$*!sXqTCankOGUaIYzcv$nKu7+bll+m(pe&+HSC?evQ^=x{2 z)CcRN@t%<4MRBPgn zD)#%Wf0aW_mdU(F`{Tu1iR4fAKB39-R%79+H@N?HV&U}XdI!YaLWl8VRd}*Mjh(gm z*gGmoqF0MsFL+rt#M~hk0MyI!=1HDxFfN>pVtP`!JKjrgYRvJqBxLgKDu34ghfMHC zcuYDhx4hfzP3An#J~L@GzkEit_g@VHGI+R`2aVDh+@Ad(n;;#Po<5S#s^M@@01wC4uuA z!J6jgZ~zC!hR!H+!(J47VpMHchx|MmvKtDIUa}7@AdWeC^akaIf~H>wtKXlV0oXG! zy*f#Cc2xI83=_=bj!Xx?tvBWU8`2rbxp@bd?(NKxs$?X*t3Jr)=W(u___GUi{wT)QBZ#A>jf=)pk20^ zZ&eL6)1N8mRPPP!r5zD@ynuo5$4J?^4d1TKC*3~cVHcj}*kh;I zJ9vCa+1&YV%^5lU35xIh`)i-3TgrtTb1M4Wss^{~_*h?uST2E*(y7-kyoW7qTD!9I z4ZTlGr2=5m{LJwS`ZfrR90zNBe^+;49f1L|&oHqM zeAPQK1-hA_fLK(hflHMR_Ia~(lW;ovlOy605C_mu@!9ao`=}h z=m4Jdw(%0ZQkr*`iY*_$X`HiZJTBGrj~a{47&evyqlN(3@vDJat8AkBwZ|CdstfY5 zCvk6y)E)SfSilz_Kf-CE!D8aakAlm0SX`U{9Si~yKq3HBLU~~$fK5!_1OTt!f@aBq^6}fz+$nY{H`65t@T2%uJ5KT1AEEU>>Te1891(N4hLAYsCZgxEH z?~yc(&snm_@(6pA!W!Ik{{@Nn0$pzsIA4#IB!Z{TyW6_nW83s75%yqFL3~SoJKK*Z z%>Dg=%J1SFra9n0&@*(o!58uE97oT+4HtN&0ARqI;6d`~M z3wSli9>_{J1I?tzMiifBrYO|LkO_BpXft5qHt0k>DqHUeq)!mpSi;Y!DgK+b((^iU zIqoVXf?Ox8oErb#L8(0rfR;Xk0%8_{M;LZK6R-fx zY!a!fQe57OL>UeMa2ng?!pjrc0F^)X)hvB*Fh*eNJ8W5nc}1?&xBg?Z&RrnT3Cyy; zAPCPt7YbmS{rf$IQsfb!hM4mH{&p2zx}`unr3>X!UeSK-(`J%cJ27K})3qYK0Q%X^6zj`>w!Nt+z z-KffQVn7warpi=*9^1V9ev=toBm%m30IdBz-}n3%D7cWdxF+YhPCQuy! z=<$-=7%OK}dviHn>Qs5oBbyypo$rMm|KC6CVB2jRcIn2B+V>-7wfCvrzEx$Zom8Cb zvl`T1a7KCe;Me-}!{5CBqK0{u&QVTL%-&&QHBf6$eO{pZ1}^PXo4p$1ndmrA<9I-M zPMg^#s)%O0SAS6Ei-Vwy9MWC(rD4z(tVg<~>TgyV7X-tHL?kcUB^fl^oyAR(*P*PX zhm~e>*?pTyWUhV0GyLqwK_FPRdSEEm)}GudY*upUYILOg8HRC|RDADAd|Og7{OJI} z|FN1FN$lrJsWAX+A7&ULJ^mI_@juLB0Ar#D6x$Ql12vg%0z6~DuJgN)W~+NL`@^Nr zgZzJ2Y7ovQ(1pzG#Z~q}FD=a*E@oAC%QmJh1%PHq=_FY^!Q7q+0yEqv0KU4Tqx!jf3Ob1xb#}nNmF=ThiR{s`2P?y{svAc);5(mJB!g2 zaM(o(qVwepeH`p#D^fGuDah($D`ME`^uY|RcXG#OFTwafNUbQN_ABug&|^Ew5Gxx` z9=}Yd>%3vCINmwUzj{yARoa;{bak-A*|FhF<&}jp6Y^E09pIoh5L7lk=S&dH{Nzfb zBn5^ECsZxu)Ii;8fl55M3u$=xw;$4&KMBBcNXfU-yW@0iW=qc>07_eE;-a|lu|T#& zUMb@J=}F6{nki~&8M3l#3aG_A{!KRzuOJ!A2DaS`yQ#k2h8K++`A06XZojJzj(Za4hJjZmr}zL# zLl7jaQ|Q1a`Q4+O zV0tjI?U$n6Ac}j_#-WQLX~`Ywo3->?jeg4(-BzRd!*As=SQH-ULur5(3$*xCCHZntP|GF7{O3yyx)+06H0y3Du2Kd-;X+?Fd zG;uVU(C5i6jQ*d57{S8S>mjN6>U@P`dc+Lcj6cjen51|s1WOTWwipbY?dc#OcSjT4 zefbaIz=WalN_30S`M6`k6(&w3{*le}qbROj>N+)OfCtN3F6`%248ZUG1De2uoU=mG z3(W>L3LvO%3b2pkCaj!FzzGnvfDItZT(~HS!i%$l`fSjn+JY)ZmTesJ5%5v=TL7vi ztaZ}mj3-?B*1v5dY+Bi{}n+XI^=moH4y4XKojhu~}98F-a)SCc0 zgop{lOWuyWCGVqx#zt5KlD)QsQ^C1$Gl*pElTDHOSC8$F#2~FfR{)XnsU^lQE~^$- zA3Jta@M_!$NREbv$JP~>x+oRY=ZldH0MYsA!0I!ymGdCnF*l$&KF>#k3Whz%O?cRJ8NCnwgoOwy zWAI1gdfIxy_y(81`Gds5+)>_|>IA}z%Q`2C#k4lYpb4C;Yk4yStxjoNH}vphUS8jI zXk|@16v~a?pMFSUOxB-`8t#xL=xsgmUZzp}2jZ%q1{)1`-*q$zOtBHxA2SsdjjzAo zY5}Vg|Gfp^?`(73fdK?u^k7zWgTz4eGgcoRD^jp(bGWG*-#(DGh6A$%Gt?U>8c|0m z`wY7jP6_xryG;xDepTdQb_+xJe*ou}u4eK_;2u0ox0i^ zoUb-lgB=OLmI9+`F0e3q>Z?=5(`Ji82!w8vi0I<{L|l}Do}6G++_lMDGeY>{3%+m? zXqQf^^N2vCfJ`Q27&7MyQc;)sSY4+q(Uq9^ho~*7!f8yGT_p1RZ>stMnQU?OKr;sg!c7Y+m@RE|>=xe~5 zE|G`d0tIeF{@o^3axOy=#^8-7Ir})p?UR=(o6QT!2N8;cLLXf^o`+bN8 zN+b191Z&`US_0E~PphFSDda~AmD{hJqcy?~;v<3>BTtwY$NnEf&=WH@x)aFOlQ{Bs z6+@qS`8psvc{o6a@<;qW1vl;zEfO7qoOQ&U>-xd&dX9(2ekW6iK1NlNg zp+Aq9e~=;E!~j^XNFexB86?U^t(}Ll&jcTS3mX2VZ?QwH!G4H0E__rarc}H>*F3oZu2fVP zH#K%R+cca=9m>i_FZPW)HlLI{mj5bhuOQAj-g<9HVPs}V;qL;b-eS%S`+)e7NJ@^m0H7YnrDoW;>@TgM7Xm3?C{#BqqngUHB((n()e8yOm3LxU% zw(x?biFIjeV3y+m$s9NGvpD?C(WX(7V#J(Oy%D;{Ecte?u(h^`Ggitd-~n$QMCehZ zSicILRQ3VeC$N8L$;bY>oCXipTWhimE&4L2zMxxCjxA$TEwL4=jJgR^TH{X#-w0TA zC*U1gySv9V0u;Lzb-)m%&GJQR(E= zerV(3KcV>?-)!>b<1IZU2N@>S)$<_`rbF87lLU54p=aXGCbC1P_R!W|w$K;aZrmVl z(+n|&=vTSW!%_|lUgV-dNvNpnR|DU5cY0))m5tCgJ6#3un7!KAy|a!ttY8$3Ox z08lI6iE(A53cDo~szX*Z-SfaoQ722g4qx->Ay-zP@RUiN9+z2qlq4|`?P1ji?(AyT zkYQOG=`3EbDwxdBV1tuhVq+t@PQ(l417=~q+@-k6cDgqvx$FMwOf zk5wy19ljKF;R_?tZT{xNY!svPl@**&?&B_aWG-)*s@6~FqJ%>dsV7Gq+`%rN)nkE= zeq1d_$ES%F0rs*saj4o~D5J1)QM^^Zxq8@ei9O9SE=$6+KJ7UPs=4v!8E|-i_QtnM zc$mPGIops#i7qk_clt3iSYGD~Ol*edHbC@4lGE6hMz=nnlyzL&H9~S^LXq@wQ zV^|$4Mp`mey@$6 zNb!$@Tr>|wrh=Pyy>HYZe?pu^+$sN46v|Whr;c)@#CkJ)+}yDUjyUy)l%X*jror=7 zQ;sBr<2Ue_;MvQ&!%}}8eo~LnLK=`g#0Q&A9)2x#S^a4On_-uGXmlru*ve488Mkz7 zhO+QWp~oVIb*A^u8jnj}@M7Rbw4(w4P{cD7bIEb?eDw{ia$OS&>}3FR&B;t&#|^0$ zz;S_KzZ-A!1>{CH^m@s)?wl*1^$z^?DJ_QeyKX+i{`f-sT}wp>;Du4iGg`PcTJah7 z(nn;44Fx`w8fWd*M2J*uHoWf75@p1%^lo~Me*HxUk>xwpcdy8vri=Rg+av6HfgR#6 zWt+zJ_v%~5e*q_^JJvrW*5OqEC3}|8)Zz84j#szkI|v{GQV1x+9#eQ*YFH6nd}m83s!}-Acvb491?rAjW9AZ z|LM5j%twXGQ+xq2!)qel$z(xyz_xlgSbgR~7Mt7NX(8~~GqA8_NwHthU;sdwnrJK%K^$ zgd%WU`>uoSe$y8_b=W?QQUjyOsN8l|03dc??0nD}ULGWVwJ(W}g7Qt(+F-PF{>~vh{dy$?badyxBUv>w&1bmeL!*{^x%sPS&%!!-jJAC*0vGJ@j z@xPo8I1ioaVt^8Y9|FqPTh&zB#eSN@oPOX{Pov|)&YU}cfdKTyhLF#9gEv>$fOoTJ zJwVa@T8L+ZxXRa;)0NTMViMi?5A4xm1??$ts=4je-t`^>aJTzKdSTZ*^J0zC%=2JY z1DLt0$$JW1yA9@82!;3{1$5pJ@XLT$I07g-4grx2h|tVa2n{JD;eaSG0MW}T@c?|k z`Lrg8B-qyX)dz6&I(>_YK%o$jEhf>Z&%7+-|DW%edkk|}q&Sj8!@Pp>`I6X_ei9Sg zv=<3?@aaa5c2xmdL}>qOCX*T5;H_yEG`MIF#cPlupGE|SVJ{wSzk6;@p-s{d<4+}G za=Sm;Q_6!xd)HPBI%{!VY9LP$4!V|Kasx^lEQ7A4i7$`|nSu!5gHD+oTQV>LzmeXC z#A8#dEK)a)#dm42)<@CGu<{CN53s(oNeKhOayK><1^ z5D*302|eCQcrNk1!BR6JfGGtCSOgwtmypu>6R;S{AeIiOrf1#`J0Jz_ZX97XOG^Z( z;(*{Rv5yt}KfQ2*jTaFjWrJ>bAKWf4JnN>FG&HYNR88&IF(F0^n>;B|=+_s3do6WD z;RyfJqEJddg}Kt1ZIbLkOb>Y$Y_X7jRpz9T!DH)>8%VGhAEo-z)|d?GtdfNONeg1h zX5QuhoWwG=mWV=JW2zbE?$Xs!c-WX`$<#?}vmikj7{i4#PPAy*@HEkK^)}2F!t}W{ zDOnmW(2jjtukQlnT+&F7pGRJpuL(baJ9bco7v-^rF!DNfwxHkdDB~A?hCjraxL6Ng zEVBLx-}rTg4!K_^m+V_dF-1>mXkoe55Fvv2`uVogr^uIm8wF@YKNLb(U^B>YX$`|b z5E_b}fR~sbs(4+;dP>{7Ro*X+CGe#09BoxuspG3&pKTn`l=3Dx`%@7GQBX%%{0J8rqEsq?p0O7#;c161MbzwKOU~4Gpm-@0>Q^-7gkv@QazH zR?riBIN{0bsI6CW@)W#KVn9t;vZAP(I?mBYP}~*(vCjweKx!YfJ8pwz`>cn-lOWN5 z;4MouSj@ly-dQ4D)uML?Hx`nE-Bl!Yx=Nn3hd}ZdR84}g=+u`MMN#0v`(WWnLyE22 z6z2%!GM7$KL-4j>X)f48pd!t*nyugCw31pA6G4s9w^6$Hwpb?LQjq{ zh;o%i?wlqynjyp#GCzj5^U=VYUQ>jS_XDWw70!XKGfT$OZU}ivmUcRhG>Ne|66?a5 zHeczPUM%OTmDeg`i0BKxffQQFX$gJ5Ux&OaO{PQYtISbJlsYDDYy?uuYe32ce!om1 z9x%D(Xvzsf>+XPt3eAq9lDgGJ?C686W&1aO(T|lVWDx|aygfkRHX|nKhh;? zWrX5LMSr!$#^2T)F@r0bqDVA^Yi4@lOaG)QD6U|eikZyg{goKJW2RROjwWNwjRU{_ z^*>F%J@fv@WDuA2zWTRRpjKc(jg~{E+y9KDn4s|48ge$JYU!l!-}8B*$xD1Zx??`b zvm{I0npz{z0*GmX{fodUa|RMnbp!(gn$5<)`aH!Ntag?);npuM{~Y;8C(Y00ttjLD zq;x{a!#(hQ!Q!OmZ*<+s2uOHntN|ZqTo~X@*<6)==ts^txJ8H@QqiBYR82Q#E!YYO zl7Z7aH1GL(o#x&^NfO>n*^lT%vdJO?Rh&q$1rQNH+!o z(jna)(v6f#3ew%(A<`irwF&9&4(aC3_MG#(_x|H~4KZq^*0fb!V~|%xzg9RYWHg&)*p2}LG?rBS z_Mi?;nFvW)z-XLQ>^Vxy6UmWq1A_`R+pfE*R0&26JVw_TA3RX5)UpG;al5C(bvBZ1 zP=sF`ga=9XlORA?2wp45qiW9%LUpunq5^TKJweHpfRU{UJAkK zvPT1nC%iM3gZ zhsATbhYdrBjvr2(geFZMC4;RYugMjtM$B|_&&*r>?sME$@dY9Ha{l!M8MAfnWt4){ zOGLa7xLx|rl7cKjR&60IleQwKK1O?V_$)aqqZZnm7j?q3<$8fHSbmfZYr8iJLZ7>KY8X#hgPWlp*5v*050m_o;PUNcq}1CNQ59dEsRa-UI^*6X>3Cfuz|I4Wz5 zSwzB%bl$@)(Fa>>GaR8nBJbR<(?t_+imxhp=Ri>=pyPMh?2JBTZY@`u%9>?H?A$yP zY6^On;?G|qF}Ur?nkf;8iunaX2tC!D4~^*;3RHsN;tH}zqQ~Qs6A#Wu&gsMFPCk`m zpaB5b&N$BBf>N48)2PvRT`EtvS5%+gaEF}cX1SF7pE^87Xh}|h+6J`@%O^gU6cDng zq-@Tfiy*2!AMP=JBnA%-fv3a0B+Nq>izDH{c(m{|aMec+m((W3woEVtKNcop`~VX% zp1Y#K6G;2yglbiPAvD7kek7@cw3NBTK;qXTt}&EgLCk^==;VykNh%2&CXG8hd5aQh zPza#w_ZhWKmQzhGsn~PoFbTgXIO7*m{N1q2=^uEpG!_~MskS#m#S|e+#B97hUm|t06!xpy_9i>B$LG?AHas>Q$WM zU0Vj(_el|(Z9u3k7&U4#VU>6}Q1sFpV`L9`M#EJj3_j|x#@gYT%ghe*o zx~!s>gp4=P3_Fg(U92)j_jI84zdg6KUqt65+(grAhdUJ?S&f|&_(zs zs`f86#Q|gV+Z{qDUC>E;+)Jl0!2FI4K7!#RxF$ol@OquR0*;>!-&%V&$arFd4M@=- zCC$3|sp65_LnvJnTM@LL#GDBM&#m0-0_!@w9R}+O8awB8^{aDk`6U@=h3v!!;EHgDILe?5 zR7~naTZ2}sE)SBJmp8KabsyL4Ae}FN5Psz`#?}JVpU^FRm{GywV}y8LY8x@K#q4u( z|AHdLke^97c%Oh&wFoleq$h;8Q6^~guCex;?NyWdRNSIhsTkAm3w}nRo=gb~FsM1w zaDpb_DRD9;yeil|>lX2;j`+9edTv25kV;HCK*iNO$yJ}XE|*%|K&g_MHLrAgqITON!St%`p+0{k{ojG?1Da)#q<%H zcK8%$oBLUFs!4<&9eEgsma!8eN+~_*b}KD?z7Vw^0=cV+mI`*yLH-qjB#kF5g!D5{ zQhf0RVq~3BG|R4&ctrL22eMhh2vymXifrlhVUHekXL(Q#+)QU0u%q?YD@NJKH;A+cPLq8)i&4E`_=R3W8L2(5*(Ii3PQ!XszSNBEBM7lF&Iy@0B-SkKk)bJIQ*NGXPC{ z$Bab9Srn-C+)%chzs%ZK;ufllV>tu@CaXRF;1*GIIlZK_#}{?u=h3vkqXGu>DUYw3Ce$E?`Ct5ORMTUXrE;P% z>dv{3NzXn&q-unW`%s%UMx|>LX*(w{=QsT3iJnpU%GNN zpO`SO5m(^6dInCq>Hcx1_*J4}_un$#ve~IUoojR$+OsJDB%)u{PuxUq>0$aUc0nyp z5fernySu^k<%SIdkP0IJCLE^jvnZ@5^}2c6c-7VHaRsKMITe}g>qYk6mN<#bx#X!0 z;T!O9?r+d0i=0eheR*Z-uQbOAl)-Aa)M9~C?Be=TsCC0UcT*PBJKTp_7C&MOVOW34 zrmp9xTOHMnZ*=e7H#LRFo~XJwYjkYgAc8@I90nrb6YWV%BZ{=<-)KtJq-#%kgdcY} zG^>{Ftjdr(Z8XPHbAXEMBx!sZk&6D8bdi^Y!Hzj_2TB_tzu%Ay-@BNe@Ri$?^z z(b1|}xN{A+>-HFFxp0|3jM8n+Yo6&kgcGMW-T;+@{?li^tFLxNmyQZG_hwpk~2Xw%%Sk{B9Du(zV%Bd6K_?97d)7fSY?9FF~WBqtoSi*enZJ z_KWmz(qvFS3KWZWkhbw9p1?7X-*KcnZkkw=NmQO$?0Os_mLIcbnq&6#wzDgd`2z{wY7|JEaB^cQ^?D zk5-h!vf3rkMOt^&uKV4?)%9n-yFXm3K?OIg1{Cbsu7bO+E4RBhn%S)051)S$#Eu~J zmRvrRZec%z9F)8@CQbeT1u%CfAg5rW28dszh$qpr*wrcDJC?8N(g46!{Fb>LQd#5< zvQ{wsf-o5uz;pmS*}jrk2dh&CRpE434IzPgK!#d$JWm%)fAHZ3&r?k3B1Y*zo8nMl zVZasFj&S$!FE)0U)=hhNyS&YtXNOb=>z+VE04r$JDCC(1ibzEh^BtXrKdDy_hwO_S z529yBA~2+|p8Y;=$D%qo^Qyh>=m*xIV8?$qBXW`Hf9_p~V()FM4`Wd{Q-bN z0VoDW$n3xBXcVwIoS?ZrVa-(Cx2XPR3gDc?%vx53lB~1sZ*2;T*@_IYOsCJ(7jUM| z)fP_7-zME;n|yRCUqt8>Z~Ra;?)6v$@Ks*D7ba#4I z3Poq0>3l&F)1cEo?K#ttQ9RFx|L7lcYwA^{n?}=*Oqk~lq^TcLmY)@p4*hTo_{~>==dnj8ltZ@0#zEevNjvuPc-yd=P zM{4;l2%!A?ubkxFVOj%N>9*IHW1r)-iWa(w6AUrM_XCjr$vX7J<}r|&ayo@716+Y)u__&`#6HJzV;GlSpkKQ3iW| zxc4%A;QXWG6MvF;a0UQE?l=%huBKDBs3 zn|IJ8rKrA#m|#4Q5w|;UB=A&ZpdTGj9kK$&bMJlEyO~^gwS(y)u;TyI0kZCm{a4(! zzC~CsE$#nSu!TJbC~j53z|UwRcEF)+;YJO zlURT2+h|Hw{(M2L%-JfgPYM(%X=pzk^1z>l<3Ne=Qv zmPvJgr7JEtIwIgr!uO#>J8^?)rSD}jeU8W9d(*V{cj z8#+xOvA)Ztp1RR|f7c~4kpjxRw$Of;=eRjjEreC>%=5AF_Y{t7sIE@-j``kK?X0GB z5*n}AT9BKlMWN01+tn63l{qD!ApHKdz$J2Qv>7&Qq$^n#bIjgPZ9dV|8~wr?5|sV_JEkvpf{X@nKH%T)(C_gQ^&-OehR;0MIjv^_W1KifSl&iOoe2azSmBCnDjOF$e8i9Liw8BWnWJ6WTjkIL6NW ziK`%m&0iX8FWB=?CfO5a^U4uZ=J5y|G{y2#6PuB~W~4?;p*1sYzNxNStu!+Gs*JPu z*cPV%A?1hX|;31%|>3M8%gvt()#U?k^~{3mfD^%#a?Z5wYl5I#(2? zJ}fczGsigS%LEn0;mSv>oQpD0 zd%faeR^aMDr3NP z1uuNk2r=k0h&%CZCP&_o+{PgnG!qB%JSxN-8D&h)A3^<@@Y5K0-%$2LstVt?Bm}+b zg#;B}o!34@k`Yx>=k2sCUU|~^W+AGw(nLqblj{%M)cNm94Z=xIbf;(Bzc;!q)ye!u zi+PRHk3~_8$VnwL<+wOs=sCVW_q}ovW#m*731eIi6ierqV_7#SzsVJ zUh;bQad0+!B)qS3PaG3UmmmN9py&OApqw=J`XRfv7D=|;exa>KRh8~Tt{nQ^wJ^PO z-=fJUiHb}ah(tTR1t;TZq)L}h3^FTRp4U`^qGMyFO%;5Cu!D+skV#N56JmX~-S!I+ zdo&)b_(qRE?buXl4Sx!E`D7GK=wcwwLUjSE%^5a{S(t3uw5|oW_<}F;)qRWyI`p37 zjw}XgKnO9o|I-49OF^{s5%j`c1#-|B64)*|_Z&P4P#(l69hESmOuY#bLLt>v(a?hX z1%@nBB)NcuNZP(#Mx9LQ)Q6iIwP65ncINVvM|aw7}YLin-#67a>+kY>*LL48NZh?uVL(vod8d z5UJ{8{&2!{W)v+{F_mX++ZSvyDzR^Q?Bz|Q*XY14Xpkwjwc8c0IYvyHo?PtA94J$! z>|P|d-`(`9sv*k2*PeLws8EgVf1?W5Zdg#`9_Ar!PLZi_FXOSh-_L$M^MK=%J6OLo zVQzhyKNJGzEv39yH1#_&I+&ahAMx#zBz^@eW~)@ubdU9N7aR+dyt@6a5r&NT=QFO7 zcB#AdpFDrSx5gt0aSr4nIM-R1lsK+`qH*oG7Jf%Am?YU@U9mDC^L)t6OZ2P9R-*i< z1b&wnd;^bFOGm_z0X8JVy!5RHP;syJ2R7Q-tyvu$4Gm7j2Sj?Fi# zm;%}9m*)vk-p016HCv#I=gr~wgE^d@JHb5fODd;R;-kLLQ#)~$uzRm*kEgGL9E-uI zZ->d^_9iu&TB3`PU5uyh0xk7R|$H>f1UXK%F0cqq@jVRK3;Yw0N#E~ z?hm|UZ=>Ev%6*~AfCsQw!xG#Tza}qS+tOMQpEdL?Pckf{;M= z*4y$;7?x@R1Q6D&cxTLd@HUYOP$6EptJ4X(nuWJ1!Q?`cYeP;AvMA(D9b_%UtQV!b z&ZC&bB`6ShR7^`@hFV6sh;_Wd3Vl3jk=Q^kQUna*$}lS3U~zkD|997LbJG+Oarj(f`Ak#-tVy}z!qT>x&NJDBnNMWwi~3`VI(O#5-}d7e+w#wUZfs?n0e z2BcNqa(#0J&3NLfPGSY;im^-{yI!St)t>Ha>{r7x*PH@E_4x2F@uOI20-a@rz)+kX01g`Z=6f-tz(c@*}U2}RVDhQx%L3v*)6 zzv}!JUJL@C-tj@LSbx%rIc^BlE(U;NZvHp{o_a&KCx=`w{H+l$JZo}UE=q5l4fAz+ zt%QjpZeo%egFlbSrN-kecA95v5A8NH{e03y<6U5YjC%c5QOmxZub+==Q;O2TnV(*722v;Dh$l+gPs8T>lY=5ZnD#Yy z>;`VOdGMD$CDB?I`st*PBHgSwfgvh}v$29oxna}O6`a+JGyO~x75fwT$BI5$v-D1g z55u>BB10kkCu_K{2ezzRSICMp^ArO;9&|Q+`_)B>bSCjF$u;mu$yRjLBp^Y?K!o{kO63yNp-AJ26!^v6gk zwab^kk1W>>qUZF(5xFupiHlCXx-MFA5Hk^Bc=a)Wwuv%-4k-3FrT-8KU~a1F}h)gsZK0MEsv<$e2*e%9Ujtoyji@zO#a!0 z-jhJ=b&jr<)Xn~MZ$7ixb@8U$>a1U6S=Obl;!@Uh z->9AVF*j~i)_OLp;QRS`Y|NBzw%?R0UhDlH>cZvi6WzOIE7hQ}gEU*#;TrwA;*A$c z7>6!~+ZT^D8YY5s7hUy1PpzlU2zt4?-QTM$hGgQw% z+J#0?yQuQ?A20e`kMW`;?XK81AwNIitxG&{iOfuscZ6!chUR73{ds}y<4t^HM|d<4 z4$tO#zH%xFUHSM}L51jTI?DC%n1w~ph$kNw^W@9`8m?MdE!f*99u`IjrwwML$xEQp zB>&X%;LD7>I% z`!jJtYuZ?#g}-Uux8S~h^)xew^;6fWc_*s#vx}wu6|C7s(Ya-A^3X}GI06YW$#!}g zdCMI87wSnp>^|8`-!?V(X7^hjBP9jmO2~PK$Hw1Wd)lA(!u2yh*Qw7Hi-|fDhg##0 z8tUB|z_C9#5^ugbal48ydmTam+785ZRLItki6ZW2_N}<{dE3xWe+&Ky-pN4%!S3&? z3q+%B0*T%YF>o2!SE3qqH&)p>Ts*KFJ%2ddX1HcoOQHhnOC(L!yEU8KytCtCoh1QR zsruG@*T@cOc0HNPy$T<~rU~@mL$e60YuU)JbLIm#)rlhL#eX;KB)@O9eKBL>x=XOH zXWIC=Zl7t!L%nzsiw?A3#}9)0cyd_7?WamFja=rF#l(l!7p)MX@0|{fz@RYy1lCox zG9i%A`Vt^7u><={y@;S8+kML1(+oQ$ZQSc{sKN@!=bHLjCWc#x7Z-!qL1s^-`Lpg> z{K$Q8QJwjjv(3m3*av(+40?*rk46({?GC)7;>Z>}HdCf;+IdM$`NmUH;1h^UND!Ta zJ?X_!XYJ{?s20LxGL1yWNF10(S9sLhzVGOpH+C0Z=5~8F%MrsdzH3h9+D0OXPFdW2 z-BIVviN;PR)`x!WL-@q|+?y#z7gaMKA)0#X{FyjM#4pA>Vh;Ghu|;2O1<^nBUmFp< z3NB1r`dWhXz3mJi!r^`HrlWt{XkB}w#C_S{0?R*$A(vJstH(4u?n+IW)jS@Xr+ z@NXnUCSF|(2+S?e!Kx8q8|_EA@eV_0Ncl|~{pmYA16(ClDaFdB+E62t=JMP67gu!T z0Re-o0fI^aMMX1EOx#I3mxeaF{8o|YeQHgw12_=x4$%gJzb-}4`<>RTV~DqZ(2{X` zqL{k1gorO^Fypw&oJhDP3C~m?hZC7?s`?#R2hFfAsZkCrFj@;vp^MS%39XkqEFx3O zPWuf_AXI_9qq^IM3>*jv5QxxChE1|}$pllQSK;ILD7FpQ4+eF`TV9TjK(GUW-ELXQ z97+Bt_Kf#Ywb$EL`VHI@m6m7Lx+Fzf5=D^PZ*Q6*&cwJQ3m@utISwycVlS;hOA#ZCG6rD1ufAaCA;t#RSN$7s*|pydjQwuQ+Z&E`rMWe>}$R5aC`Cjs}d#uH%0`s zyTkEWh8XcK=;Tamz*>T?LL;g4PQo9HUkOMk#D0X^vP|#T6kbIW26Q{Wqq7lf<+~W5 zHL#6o+oQbjto`w(^i8L(Yek$B47+hAlkPN~E}{*|m{t__(J1d9Itry~3)lRdtkbXQ&oJ?+VX5IsJ}G{60heci6-=ZG>_ZrI@^(y@QZ; zGCi)(12p*?xOE$kg-pS~Jd*05(bsAO`6d6|-3-)N_h9EIh?i~~-T4r|R2<9drTyK* z_VW8tJKOvPV;ux}gly5q>Cv>of8d|qd#!twia(TMj{ypVLcwLa?24ryi{V}kN6UdP zb009F&G-Ju=zI5O*A@S49f54Nm^d<|7m1o|2ceCQj1!$3Y0QFhM6UG1yd3U{(i@6! zTHkIhG1*!nk6^r?ENev<4f*9r)&j2;iTw)R`Z2@njI39i2Ztc|>Oz$PwjzZZavXK$ zy@`W%NdWQ6@p|)$9!Uhhw9yJcfTFY#OZ!+-YX_^p6_somMwy(;usG95HwG?(@kA&Q zF!rwlpx;-Yh5}!VlK~Pi8={^PKcDIjo6%>B`;xO-dvZVY=GEPULcox zln^;vWml8;w6$Mf$Uvbs9DQwCoyGtVJn%Gl=}DOTHt{NKA$xnnQJr1aL{D;YCElvH z7NAZiPIm7&Kk2{tEH!u>AYDRjIoT|v-6C5J3_E-{j_4RSgy`~NDATDu@#{wLMpVJ&+rp<&L)+om6t@WLlLC74d8$=ITZx0L5+ZXr8x?=FNnsF) z!MPWyfT~nRLg4e*F8lTPEZs^I8l!Wewrx0Lj%;eaKFc8EC!5#OeZg5`=45^5nATvX zN=2VQRCzDO@fx^wpL~JC6x=uC&_BmYJa)h2W|E3j+d|X4NQ++xvf8q;^8wGY%-zLO zpwvILh8No^Ohpy0RlYI#!xZ;L3jm5xL)(**rHN;cH>y*uHqbJ5_I_1I;jCxmAt=%} zqrSyfClpaeShP2x#vpTr*|<(1rwuW#kCKLg#7df(vKMJL){_wv8aq# zq4{p87W<>i=f`sI6(P1{jJjgj?gM=8TCu&jx!sc0!J1=1NA1~9rY2lUO{w%?ly@EHH5O= z2;a~m-%_wayE5AeH`yZu(O@7F?e2#XSM^ayO(TgW-c>K6BdVbg1|mg^>+}c(zKBg1 z{Lor-Z|KGalHiLF9VJe3IVlK8nkZv3sh5tMvv~JVk>HNDO+K&N{TgNolo!lNfoal?>Q#G-alAt(S!)_Z@=V=*O&FG_}1>X-f;VX9U_csMpEOq`@E;{4UgVqwVo) z0UnPT#u(jGDr9_;+Gb`Fh_9So;F^H2JX!#!gf)P|{GDDl{`fqBI>}W_i>2+I^%Nw% zK5mbY+x-z=1y$ftAH=xtrb5-CN&$MX;lS| zGNPL6?`3_Ijc)<>GlTR?bez#VVc)Vd=AM+b=F6d-6>Ypc8DZwmHzF5y9G!wWF}px} zkMd{10=#)R=}A^z=D7<5`Klc{=ZDK}nM z_EOl>97O4}&K%iYc?o2!a-kb$V<+#l*J4r&DF?JppH|~PY0jE>bGhLKwQSD?X8m^tS8+L4!> z>h$K!O+YLb1M(c*slc75GeDZ~N)f+L|3vtCNeEIBT2$3)=n1?EB19zgk9EoIymCsn zwK4oqrfGFJyUeO0#9zF0R99U!XdZRU(VL}p?+Qc2!6Gf)3He!>u=X?0bTkd59 zG;gpt<7AbX%D$kVk*|`8iZV|oQx#S_mSR1Q9LM2<%P4gv>W`lpxw7-07rt2TyM>47 zt1CP&(}-g(R*xXhjy+#w(0>TetJe7#kW)@o-SeKTD;zp?t>r*gc*3M zaQT3}QxK4&;HQ${r*mZFMhH3OB7&>9mV@BoBc|`AxqQqCy_f41gU{`#@JzJKqk#!a z%9@L2LK*Y1QDkMP-@oY~9}UK@1|gy4iDUh2@|y!xbiR77RpfDuDj}%<<1lg6@PK#X z?^^v4uH$2fM>UzN&<4i0vCzYgLd~8~57H?W|NKQD$+jZ>VDM-;(Ie5UoyJy;e=T6) z^QOd}XyCTZgHdy;nmgE#o7sA4)k}ZyO{IAO_Eb&<3faxy=C4l}2JMq-p`W<6rEvuY z!mAY7*3RNCuX9il9Hhpf4VZh*3la1EMmu4M4jho}0m4f>ywOKua+9xVAmFS)+v&Iy zxIdhwnH??faoal$)>IPOtCW94gqaCq$nZZEA0}744K?~fDv3EJ*B+Tdsk3W_{fqPB zbor4C&!XM7Njx>Ch2#QclQP59qJ5p;)Z1fyrqf@PNY=|ww!@JfS;h@9WCayk;B1+> zzNr%4m&3K~ykAM1oUSd21n3@4UxaV3_g|0<_`Nw){n(6O5+s@8)2hOxPElMgg7l6U zm4|ai{slKuN)o(L-6P8j0f3~vJEE$c%Wm=67pRvMi1jir`;*HcE&=g3rR=Xzn>tgH z=v%6Iot?C>s#)CLM+2!iV^JR^uYpgY;?EA39*xMIE6&|&R$IyVb9X4THr1Q$v}Er& ze(}x9MqZRGYr(i;MnCF@SD_I4)=$xyPfky5ya&A_&z7>w;|Hmo9>OK&t8QWG)ph4& zlI|!br0kw;>+%O78vHdwNw8+$W5$&ruiyJ=;|Tn!Qf;LEYA{?+qxIQYRo@E_MrK2F zpEo>FSbT)iK9P`LO%YE~CEcait59LJ&|JdI-(w3Wl7%vy^`)K^yrna%qRn&5T*f1P z)lE7`hahuUI^rO~N91AZ#C*~f^(AK*3f8*;S|#U`>d?m__ixN7?%!PXvvG9Li4dY3 z@^C8Vio@M5Q?GcPb%}kO8bO?s{q_g8uakXlv zP5A&j^~oQSjYAozDILKB4F3no&3V8Btn5!%KG9~s5tH6R9G0~IiKD6*1u2?#8l%hWNdc_w0hOOQYFZ{Ag!*Y+Qe?ew z5KI-&N5VXF=QzE+Nz)u6NM$g1eu~%FIzGlh0fRkog6C&1S0>U5xVEKJv_#9{kb3R( zToXy9_+Qbz?~4-xFT(WQZ7bqFn^g^NwnDZwD4O=CMdLT?fz3|Q_4NZ~g^bfrpYZcx z{p_^pTw|_t?ei3}OE=EBwT_1ufPUmIUp!t@n?NshO3aT+2K(l$<_xY_) zYj93*cYK~}q`6*T(k0={n6*-(TS8T}p!u4Q%J1QaTOK|h5O8VIYjLMxtlJPE@a3QU zGMRfAHB=S_sgFUezox0G_r82K3D4>8w<*GokYhd3FWz^;ej-A3cqpx-aZ(MbVq>bD zpDr0SnU%>>6ABsOLb+vxSy2ZPd{;0lHvW`*^+E<5t#NLaM!^<(|k^Y{;e1aERIc zq%Q=r2e91fNlL`~KhWA-g`EMp#te4P(Ngx0qoJpmJC3J$$SaFNl_j2jENgt-1gCm@Wn~!%7 zBri(oIE(aRXfBQ4d{;^P_L9B(Vo01KmYS5vL?aS9O0Z+E+jrD`*d;kbinyvYAOAk;56|Ivh(+T%z>8u-v{Kcgg>NR#FhYeDSY-n>4#sxbY+GcCH! z&E!9DA0B@nA3lj!+mT0xA#Ou5yLE$rFRTEVNIspI)(Vh^ zn9?|3XPP-&-#`RyMkTXN&2t z>zHKVnZ!3YqzjNgd8AiN2K6ix%tzNt{e13GC4{48s-mWyK4;pZ01Tcsi^XSv#$PYo zU`^g^B=oiF@}3VMB3eFcIWiR%v6J3k^k^HHtm42QeEgP7`Z=#qbCWP1(<7&TAZtJnAvHM z@dTN9SxD*eU9)P06LThj?U0|iqHTC2qk!kIv`nyMAMF8Xq1a>BTKkacg>TK=u@Heo zXz~Bu>{Vo8XLSJft5xOZ|Fi(m&(p~bMdj-I6AYdvK5$0)n-z`uL`=KxMfJ49p0YGsv2?-Z z{m6Uw>}sjrI9UL`y0$Ie<^|S^-ovwt)Dno^JSR^j2bW)4s0T(9^=$FYt`QeHhHSOgLXYiPB4^1e z2~@^xgBs)4{MQfk4urp)UmyOoiPO7hUn2idt~~>6(Q8@>9Gs=4wbY+=a_10&Ii-6Q zxf{hqlf#G3_e;3k%FXcon4tPK0vDC9!9Asi<+JlM(eJj~_0_&jwiYm(*iJOw4tm`p z4SlzE^XQ$`sKLem{ZHepEO@FH= zmAYE3tY%&5K^M2r;g388)Iynm0b*cc3jr`j{{YE>H55q6z!nE-2cH)YXDgci8G$OL zzoT2yz7F0fTKZ>PqDuYfQE792x?Fr%-HS%xS5J}!c`147Jt`6L1)aJ@vlS8odG{EbX9l`pmcqzQakzHytaa(BHIu2s11`T z%!8{Wtx89ICoDv6e_hM?wWfwfo8V!Sq%i35%(p90u-mT*``o(TknIPTe;jif7qmHQ z2yk>>Utkc>HDl)gX^^07fZh57F)9u5|8xw7mLJUlVQ|CbV!o1epf&#gytOdfdILY~ z`5gK_3(V$0KLB6D+Nffb!$ZcT6RT#!TgpEu7oYY zzr$h+<1$+ADQ|b!@BT6M+QHf<1GdLgu#Zh-7-e&d^)@qrRXZ?kreS27`k%%-0h9E1 zgr}+T5rg3fDhEUbms(5Bcw8^$%VWKlH<{_7Spnpg@N0*v`bZdW!~L+7lh zugoWTkRw;B0TbtjGW!Z2bsCdYRdqak2$AL@2}~L={`r|Tpt;@`Ke$@`=6@Hz>46DZEsJgacZ8x?{o&;$_(;Ght#V&XMD9CoTSq$oi7CBmF!tnc z_XDHi0PpeF73a>tm@R=3HrzX<_&a=Hp#K{p&vqaR10FyJc7Ug-7&OU<^0-oe{Xold z`|yFdzuKwb5HH|CUzZQ^tU3j7namGtk zm_tlB7ffHOqoTbS@o~D`YeAvx`i9aP!n{~I_a_IX`~i86sq~3l=zq48>#r3)^8RqD zrEZ zpwmZn1k%Eqv$Cuc*?!g8$ka4RFdHF|#)oll)$uv7 znfaF`ge*Clv5Wj~N^19mN}x3>;PAj$&#lJ3WG4+~e7O9oSkp?qJ*M|X?#xvMpxV=K zKa<{^(rWT3OLBb;{7STE!3F<>LGGGmmN@2!3p21}-Bl0&!DO`9&TcxtoGTI^@r2)! zQuwO~^1{phIFBD?J*h-Y5idp6@=v;_F800NrkofHi!QvBeqDcjs}-U28O(kBz|TCX z$Gcu{CZO;$0>%lSp}*Wk-{q`upYuAV)Z49VkrM;L=Q!5|c9%CnPd|t>U;+{ikXe`K zrDa7IzX+Rt{1uSz1W&o; zosmNo;5+fCzl|U~{r?hzX2OJ^W-n*^5jn?u{YmnpS2~x*#?~|THPA=CSPrgkAhTQr zB68}z)%$#!yeY5xIyCR&jED~OQw)b=cY_l6wTA`^9W@>QOia-~jH5%&;77qj+UC+G z1k>K{%x!3`9qacCl$UNHif`?ZQDvS$;6gpFKf%$7I)%EI*iFFqFEQ>~ahbZ`@fX+W z3DOPk0UF^iHI;1wqt39Q=s&RMI=tCg;QWl*w$}hhB@SR;w{PB9zuv?D-;`Vy;2Unw z$I|Q0#Xg*i&Eqer^M3fwBcaj+ofua9RY~*nYhJBCJ##F%2NPLH*yMZiA|3Ly9bO&P z=l3eP27JLP={Vf2LuNm+{^WQq*jyDiQjNa)C+cXAXM{E=so@yA+4BY zN%FhDBn&dAqeWamo$(X<;SXWNXGJLhFsK}1lMg*ibEq`IPuqnqfI0c%8P@6&Rj(wQ zrTB4)9XtV^zFIJ4mn`QVoF7Bh#vd3HAa(U(Q(q=9v05B&N2$zT*8n2@NJmEcAnLC6 zwou>sXp|O)LEZN<0Yf_83Rb`W39Km&q*m)%`$g7Z(=X(d?WaCH2{P^URX*5GceUpM z-TU=qr5=^xEZMmK55iBKdexbonRxJiT#ryp_sRtvEaezmCr5`7#Tp=`f3m7LB>;7` z9*q=%r8>bwhq=j$voNutcX`kJUDZMs%9nf}4H-u3@M300#e_sTX z=Xt2yG-~=IQBxhTU(jR1eNrMOqnJLj4!-eb~<(mrl3{84})};7Y6$ zPPaoeLQ+&>ID8U9I8YH~+`5=O$*SQ40+Y5;o-3E2+iqh!JWY!1uyq395sJqizaRFyO; zcjDvBlt*5OR%bQy!65vZ@4hc>fXNDO=!%^`%G0@h!1y1@u%Y_T+1|=8MPl#$F)6EQ z_MKc?&x>GCIZEd97nkov?ec?Tk3CBX-;msrp7Zm_P(zf6tbC|qRry*Vd*;}mnzl%B z1$pmz*dPwU^1d6Qi&Qy8<^j|aS_5P{K=@RKE`mm5Oc!XT z5`zA0AT!ob&Cm7gnCA=fr{el6M|wO=-#w6A2>nX1vP&1JP(-ClFW9&+)o?1hO&*C6 z5|~O0K>Q<(USQ<7!8t|Y*_~$qLvRE!<_RsSy+Xkq4mmg@!B;#>lVi-f5Ce$mi?Vem z{;xf5YVgNeEvECMjIW~f5ly~rcFB_pgrEyI#>?IZz&Er>k|IIimN_4NWsf`xMcq<$ zVJAnmR^|1p*z%Lz|Awmc{-bQ;gtfT32#&8z&=zM}dubDU zK5mUp`P?V`jW9hRGP>yUC&;~S|GE&BrB&W;h~NH!umOHx`G6Dh4(@0-T%a$9g*Z;2!<2y{IP_5h-{&DqtcooCsklqGsk)gPbm^! zWl|sG?Q&X(+c!K{5a%M463XUJk1@qUU&2_$H8|z55^i;{Drbkd1>+5(;0=&VTFqPZ z7$n*=GE?)f&7J%X?b{7r+`a!)e^$nKhtRxPMR`V!ydU}d0IqrNjDzyMrFCKqFzX0N zM5zvrc+bWNTW;MQMDp)n?p7#`FKDd(BW$hM;0^&s8+g?2;!VfwhXyCGdR>R<`rPx^ znXcl#F5~7PUsvt0RC&hwl@g7%?JXKOy)~0@DOQ75rT#+zf~#Rit$OXknc7P>jf3Pp z{&&u;>2k$NV6W@i22A9fGWVrunz!Oe6_l5LF4Yj z1-xT6wt{ z>4-nS=|z>6dMR5Jn>gPPIg9Xj&CKf*9%X^ab7Ws1^upf2Xe&%vzsu!5GfPcOS^h2z zEk8EF!#AQ4q#LF+X!@sgE_w|QfiL>wodLE_WWHg+q$Z?sJE)Va(tzDmS^O z3?dih@PcGu_xa<0lK0V!pY=Z2XI78qeXlLX4&SrY8Ewa4&s}tUwZhpPJruOx1;0Iv zX4MTMh_?49Mm602`twn@sd>gf@-@1T_9Y|O>F|E+{Rm`Q7~g4Z%+DY6A1gJp2$)^zmPwX~Lj-`|Hf^w8IiF-%^l!miD6ZS&*^80nnJ$iQc zSN-9!L^Yd~HWPe8*JYKT$W-OL!CvTZk`2UaGburvJ_0yb<>~)oIj%%>OFH9|qdLtC zu;p&*e9dui+H5|>XG_5Ad#4$40t})ADiC5=ptuX$$m3v;P}Tnarhk5o(n4jL=`ZvE zQoSi3QS~Id0$1f^TMAWHC);wEChmd@Y@c14)vJlvT+db<)emj3zC8_`qtv<%j2bLS zkUFv-6hMZ78(GEHM^6K-S$3wM7>~V+0w-a?Ve>DxZNL&%;<&3zjIh+SP7pIdem%dn zhbsZlr>Mc#iI}tzh>kr#5Qh$~QMLWQHF7c&%})a7V2DQ5Bcd2oN@V;*QxXIi#88*_ zkM8YNrv=(Hp*a|*5xDUluSYA-3-#bOZu&XcG{7)DZM02F4Jq~ha{HgM(?9LPtrKg6C4$V(A_@S& zrG|~?4|b$A7iC$U)&GmDcL2_-Yr{sLn2j16jT$$$8a1|^G;VC$M$_0vW7}$MyRoga z)A#$&`RB~Elg`s*viDwVuXSHqx1HwGp=N8;yK2kK&L;wt#rJx_$nOOlpqYf*OT#k# z;~H>kHs0?DU{xG58ZC|Vw**m3mZoUmL1*e3u!RE14EmqPPeZU#Z6zpQmTTf-0sft> zJZ}dCO282w1p?7Kn}h9j0SRJ2RRY|0eFwoAB6dG*2BHFE%EN*t0S*XQheLH=@;gK; z{{i|H+ScXJ*;K@4UA1n2wtmM!S8oK-<$4ba+(};RYMG&^rWDSB|F6^R^AoPu^Zk*_ z(jA2i|26G9C<5vtZaZ3F=Mbvj>N7yoSvF+ZwZZ{VU-Ggz%JqC}eBxP2{C6g}%4I&X zILQ?FI6j6rktaUOr)%;HU5Yk6Y%m2*;}g_u@dpg__;U^K%0K0|gp!2A`=uT$5l4Kr zcgueyRelqFG{l!IuT4{%YB(u0&_&85p9CJ;JIL%=p{Yy?Qy2@=bLF4=rtaD?7gnI+ zT3+!NE{08VcUI%VX(3pF-Serv97BtGONpdhN!@k!Dhb2#A(r$Oz6@QT*r@JKMYY5t zUse5rEvh{9n{(fT)9bOO$^Xo`6%Y**fZ6fH8UV%V{2HQwskQMYv_4(mdE9gF&H2V5 z^^F}|x-eq|uv3bkq5;c;32F;hAn>Bn@nTYUXTAN_x+tlSa@s8oI*%~_vn&^u$Cv>H zm^T=6h2DYMfJMe#2@5aNsQR8SEYZA4GsCb?w7o=ppADqA@wJ6?29!5dL@{&RL(8cB zUx>~RJ0vN0^DGJ*oj7JDP>k*?(X)0lgE+3O$pSjEV!tBD{!bK;TX(o&Qb2S zvnlR9D4`ie>z|e{2WNxmjocVeaII6m{_b=CiA`iznJY=?I!EKG(ITHg1o0;R{9j}{J&hES$GsU=#$=8kpoB*cV%GJz>pwb>CIS}$c>AA$9#=>+U7gfA+!^G+R113iNQqqGa?59a*43frZrOMv8J3Hqj{ZT zIdkaQI#M%(mCQPCgs}($EWO|pe(UPNc)CMCmL~+oW!uY46tsn?`>Ini@Lt^Cz7S)% zY(&h-O=m`>>?bY&6#XE94WJbKitbqWYl$Kh(jtgzpIb&aXv(b5ZC}y~O^jK)hPo?6 z_^eaj?Z&R8199-k?A}tyAUH}HgU1>bD^eEI!+5=xd#zF6@;|@{cKQxDzwc`F)8=5` zf&|dzYZT}NN5xQgSMN%Ibf5`s{P>43xoEp6;nxUzBW2I_bp9t54S?qXk{<%o6ZP7C zhc|Z0Z2uD%O``D`i3|@ko1>6%(?EZF2--34ETK_~5Cy^{AgASbL{}>}inHykYv@9# zDK?G$2E~Fb%DPTs3P@X}KzjDk`G!(E<)U&=2_w2EHC(e+VyFhpg%YqUU(@}O#+Np4F^98no#Fj&}V zv#$K)J40~%cb@_WVjh?`bSG5XWlB=E&-CX?9OBA-PDbnrH@PDsR=)_>nGG4l<+n5- zx&~gNxS>w=Vos~J%!mF-nEETT{i!;)^{7xqW;zZAZEeQ7Esh+0o=+Ro?+qqLQ9oEz z#a7UEsL&snkS`$huY6y?vSZA%3g^3f`~nr;@Mk&J6EoZ5XT2YA-)%hJw=gi!r{5Ma}k3fB3UXiE@NnG-|7m$NLsVX0oQ^u%d7m&lYe`*9bQPI&a|GQ}E zvCEppZ@-``E+7q4^0|^+H~s*NTpX5ogJ}w2L#(xT-fdZG%4g{RAA$|UNt0~n=_bpW z8$t9z5Q*id5ELSu1P-|~GD%BFM8V!M&&YK<&h)&g0{J{L=tA(D(p!thG})Dx?=fnC z)S7g>Q%AIs*;h2pMy1>-0RliyEIZvgGa?lFjFY-s0Dtn-u!$JLJylvA&&z_1(nv%v zZ!JLl@x|2=^EG#A^Z{6C6b)@{JcN!`=Nb?r&S8=IP&4G~<_hX?CxYRhd|X5YEzvcs z&4U2Lu+T`PUminrugGlcI>4p&*ZkJ)@h7!2!3GTQXM$}%*``hVKmGFu`dsazrYWId z8=t8$ytM(Wbv603qACN@U5C@aw7R_SLeFvxpdXLT>pV=K>94;GoVqN5Y>uW0j^dC= zc1{bW+)%$F*}I7pQ@>{giB&^<>4ukL8d~x%|BGfWaiPx@wH|(~YAhh~>4ZULanA)N zx?mnDIi#p>o-A-S)at9-kU#i6^LA2}_R&LRp>I*$m*aP5Pc$(am8*Fs!T*dZu%7`c zM_526-G*PRj>Geoe(CMz&8Grlj31(S&B(F`=wFJpJP9NR#;o`jE+B#Y$^_sl_}O9( z69;h4F)JATKviS$xx<=@^1>w9`j8jMtl6XBKqFogwtde;rX3!ka$&puO+-{obD2Zq#cZD3L9D2FxGk z%-_!3C)RY{7UNaaUaf0q;7RhBER{uyLseX55t~9(D}Bro8H@s2vMx)AIoY5do)b8G z=j-O@$zKGTAs1B%Ni7LVu=x3*u+5sUb>{lJGBbrf8$kML*bwq-JxI}oZ^8z<2qF-g z2Wt0^~Q(M2xxIQ3Syvq)t zbJ=uc2oMnVso(n~2t3Gt+yL9XhY2&VO)9bXKoVn?q>`sKh`6G6pA;Mb6spxriz(ah z#=?WzxrU_ZLkDma z-XmShT&Xf(`*_0=_|K2DI&RN5%kXULaxz=vrG2#jKz|&V$3zpk*@1WIIU)M4|&I~Cr8=A ze*IwW^3e^ZONB=8#6omEvPFB@evi`{uKL&JZ z{eZ&&2#+k)m)@VQ%Dk8QKz;`(>wT@)54!=g3jX{?>z6m+%%W)e#Naxw#-8Av3P#|C zdry(PXV^ltF;H7RZylcbS-=CyG{+OED-(N|6vm93a=>#A{KK7^=1SCeZ|S|VQOT11 z$+vs!T*$gU@z>1>KF)9n;_VZko9^P|YikMMD7h zL#2s{`r8<~C6XxE*|Oi32IZP$|wq1F`*>(uat&_C0kCkhMDG+T-00 z_Gt0)7-5cFNo!y}rSjlme0W+M>N+5T-vr?B>dom$xkqp94sjIx8JN^vJW`sSF1x9R zN41cR3ApI_QV`TCjyYnMaAlHbeJ1_IEp{P>sMs*klLx*4!OQbR2=Geu0F&sypw#`^ z2twmqzKFxCX;Zebe45tjA%HG@fanfahS!$#^Zmtq>a}YUbQGOU}e@(#wN5i0dtuOAS1C!Y9nE*#2 zaF;sTz9xqSg3|&whxRHMN5==@PO>v_JXQ!Ys))|pqV@oEIzsX_T7$&0|e_-4uKi zC=u#)DB-$Mu3yyfU?TdeB_Ca3^|l~`&m;1y1o_9wl>^4JPt={ehpd$Pm-@YMUGzG(s3upJFE^9?EP{C% zCyZK9$Qa8aKQ~AAhqiJISar9*qx*Nzb!!6DK)yqP^6#H-yIG7hK1@kaMe(dpj7!6t zKWGgGeD%gm#?i&q?*ug74Xp6M>6LIe1%H%|N4PNBc{G3EZ$yBUMAs}s{)#<&=x7p6 zZh#fs==8q!G&He@$cw(lOhOR)*bIvIsL`fE4XEZ>#F*UF;nKJl)0mtFvbX(0`)g4U zHD7!f|8gZWs<~pj&`4odho5)7C)T4c#z4|KlQIbMx;1+Dh6N(|cb+Qe3_D{^rdW_~ z$nQ0Ta;Srs`WLn7QjhP7c!&5b=;vSN{XoE^Qo&NN8^@NFZA@hewz?&)K1n8!W-%d{sP;rqVc9=6(31&(YI)79XRA?3doii`nb zYkLE}JXJ#R7dj&W8vDy=Nx%xtT=kzlE7uK5?5A;lK|ta633FsStNox3FmBRObBn;V zZu!#jds5xBNxCLub+wu>%aBhqbDq_c-v8rLFMs*SpFKq>QZ*E+iBCK91%Tn%uH32a zCUO7iV%VNm$2Cd>upw0}-vGA3SG+*(7)c@V{HVx3AQI^3{_+Up`HZJ()FGJM4?ozfJf9{5OdepAKxYBX4n+8xy zEjnPjK-ck*`rdMKBBH6k&oZ*3Krba5LXRw3pt5wQ4S7S6&*p3 zg^~EbM1KtF|D0d|uCSiVbw6ch!BF}tmXP959#7a;(htu`;-iq>kY^M0iC{L5ImewX zDnyUj4Z-En9qK}G-&$h}#KcO3q%{p)`A0gdcw)p;i!F%t<0MJV^15OfIs1H9 zk$$`TbT@KtVt%GY6;Vq>y|qg}I^jVIq0Z!~a#zdA@Zrz^YZ++WmuXu?hhi=U-@3h> zIi0uoG-;1?G>=Wy*LjCAoA3>^BPmclZVB_C0A=Yw3Bsg}of0QxD7v}v^T7Ow55H~q zn`vpY>8XAdUcGfHBI#Tqy=+FGjrx7?2Rzf>?o)A|x2?ZNblk007`&a7WXo|eEzd>0 z4?GvcoLu}@OLzQzGUBI)6bne3O+7-U$|mH$LtOt zdfKWZx{M9sKN1rgY)}=>S@{Xy23!#gZ$sI5;xkb!oDI!Y7^(l9raHblqd#0w(;1&lE!I-~%DK4`K>PKach33)NoiZmPSlHJiPT(AbAdcqji0@{ECJX90ek<X{QkR?yU(noXu*=E z(kq0vn>Cz`aOnbuANvZv3ZAfiT#`}FqXTjl2aTIOuu`LkMPftJMMilPga2rF;vkl! z9sY(RG15@7`Pq3mZU`OR zTZ!MdTMYLLE@ZKco~NM}7ye8!@xz$H=VR4ao!lGQ&ukUfn&Us3Sh~20bPWr=Ol!=X zKc;ng8IuZ}TD-l^oj%YH{`@RXsIY#!K*Ecm!q~VTtpMpnGy%>c zc{z-FNAlM`o~_?I*w4)4Hmg~P+P8S4WEDt%%PMk@l%Ki8F3IGuOZh!*CrW{@GFe#t z)vGTH8mX>>OVdJCkYnd9jqZlkp80T2pYtJ6O4CKg@9dU9Z_ZIdd-7)RRTs zsWVz|YaCwoY`K?o@#fu;^XmO}^7#+1edmP-_kISaPt-$Y)fwR5AJ1eM<e*|-C{h<}1qU<+v2?7d_fd-$6Jy^F@RE-lb=KZAK za4sA#3ZB|8cc5TXhI8VFaJ?xg(F1A)(OJD!W8|Erlo!Om@oZ5EONfX3eH4`j&pC`? zKsJ__NJNE)IQWMDpiy@5Qy|ka*wCiP7vjt1z-RI3cM&@AE1_M(=M}@%lJJ0S&QS2F z?dhA2#x-G7+aPSJ$6>i{pEtBB0xQxi5R*+vCQ9suvQKD@qU}cB7T0~fw=;yv&UB;- z{QExejMQS5ov}FQkMk)8tVRMX7wUsX>y#SqN`4c6_F|Paxx5Nw z@B3B@F)&pBfkaU`#+PC+$Mv_e$_+Sif-4h-JQ2+@RKz!*S4nB1Ktnn!BJK=Pwpf_u ztiaU|Ri8-b2p~p^KPqa+d{fS%$tEzGQH30b-ME2skPtu>K@au%j5MI7s=1)ZT&lI2 zFGpzA`q+rOsJ8mK8=7q|6h+i$3pUsF<$MDJ?D+muGa8OE@k0N{TzYwd7$cC`bxI}&~D(N=cdo5_p_6{Lbm6kP-gxf)lV>f-tIN{=qE%|$1BT?Bak zA>fU|)1CQcil`JjHATCqOnWdE<5OpE5Rx6p^_5dHD6YjGBln_qnO5%fzb%fv==3HY zD%aq&WYb&tJy_4HfU+ljHf_WSO;9jp-XpirsThC-nEb=N^X&?G?1{jPj0-m9cszLCs{H?${gO)lRvk z#)|0+lmJTaB#^*YU9}NYvIyqk3$6Gnu6g;BMbeJ4S}|^He5H59QG%AWF+~keSpS=l z6ISk=#qhYN9OQVfukBb{&w@RUVEdjUax>luqMf_ij+U+sQ3J9SDaw4g7TH>97Db6> zmCfLjdi{E8PbLG)>n|%STr_MM0x%1Zl8-0s)Lll>Jpkx$0 zVdF+k&h|IMZ2?O)?kJ_Go;GpStq|3zB=<0atr+PTLEo(qBE{9GUL|~N-7y|A=#13f zPO6B+?`-hsQHujwj)|0~HKZqDV`_~_jQlRpvP5at_tULboH4Ch&67JvOxHtuKPQ;p z9J3xzTeSNqQ*#&ac$X(A{|-|N(8{ss$pzEhCn;G;)rWm0vZK`Vws*x6YT-m@9cQ<# z#a`gWn|LJVY@mXpvZEE+L@c;@;7S#%H;5dQJ7Y3Q-JWR(7-{W-Y9n+!sXX(}huj>} zT-1Vzz;_0UBuX{d)i0O1+J8?dZ}C-b1Vtc;2>e&9ogHGC*bp5eAxPLFhv^A(ez<Ht^VD9`7 zt`3^qj?zf7;lt8b0o{wlU{Y){b1tJcKax>T=qQGU)(CdzjBCC@-%&@f zU~8`(_Z7ZwX_Kd<$fWg*^(n+>Z*%&wT~6=KCN;&o%(72V!_R#LuP}kkRE4A=$TtSf zx-T6~OXH-@uDB$!%KSlHiX{k$S(;SBDSb1aW-^5@O^G8S z7{%&zDbV+wb2J596TsdoIhA5W7x~Pz#U%LxFV)Z}2EaY>)jpIgXILjKG9pA6`NDZx zM*E(H=c-9)M#gXIOPP8SI_`23RW#V)B_n7Isz z7LO6dF6wY8Q*rGSrJ+J9WD=jj6RTPJx`uCW7#t_i*OMh_aB;4XdE+*D?Qha)**tge zdUB{UI;V=M9X+{f^`gS|Hu0E-dOtw(Dm3tn&xN@cvmUE8a7_uU-C;2WVVInly~L<^ z^uoZA*AuOS;CPru;!B5VL~Ae7XE#62x{2)uxVjj@4)>>E#+pRXjQbwz2e+Y!l_}Qd zQQQgvqd_X)?ckBih-?jt^mTX6ihZY1Odq%lz~ zR$t~ip#iLX5+LJC=j|4q z2$4Fc!y0vPxI6d;CvcyKtB&5C+0y$V_=GXfhEk5VS#FN|t(FR*Z~S{FSWz1*a}f6( zcl_aRUiE$!4X2wAba=L#gUCMXZ>*RWV`}#~easBWcEMc$?uZZ&jQrw#0ku)wX3Bk! z{2^2FAN18=@_zj(*B<-(f}z9mUTYW0|BTO4E0HzPIAgC=vTna((W!`h zTpRvA@SGNFp{U#R>|l>haAnW&JO*V{fu&kzx}{H@8f~KsLukwSL^Xfn4ynxM>GE4h zAA{%6KQcX7ZhiK1YF^AE@MA!IZ{Fq8-oI&0KLc0vejCAfu+Hkzi;()|P)ZF;d$-24 z>-t$9BYIVHh~ML@4MaXhrvgnkf%XJvbfwB{*;X_FIw~s=n%u%>OhvCf)+%wXx{+hc z9=aU8Aw}{wlvZS0UW&5U^p1E&^6IKF(F$2hob(9~c!c)lFs8| zk)(e9{K3<)OD(+k9G3}Mv90${)#wMf@IKU%UH*mn2@^l6x?)Q*hJkS$u&5C7T`-5$;BTUc9YHfeG0+VWCH z?1K-oR&qVb#go7kWfCy$>ZrPgAbSx34+Cib3ND-o^m2%N$gS7?y3g#|b+Z5y9OAoK zn}X;HKFCEyH3Ubx>009B8<#>^ACuynLq$b)#79Dj#z6B?;*+eonWZ@zinJNrx=GA( z{8x4PEGoBN_805EIz(RJD0wZS5O?Z!w!B;jq+v(QAbXzJm0B2woIXp2~VQY zqGj56>nwVMjV!onj5m@s4a`1PuZ}s%+xv6QN=iB6j(?T^9zz)APV>z@L{yFP-O;jn^s8ODHFRk=Q+8(lKmNMw3@pNPJrzj61b!bhEh$HT-cR?($O*Ch&_b~vstxj5CjSsO1dE(DzL;WaC(ocU1jiH~ z4zStH3mm)P27X;j>1^ut2X?s^oyb{6d-5phJb4@p5@2|5fdlwSk|MNI2gPt;gA)XP zWSpKLWx2~a#@Eq^e_};7kYisO;Z(A$XxsVLpaj*-(iT38&RG2U7rd=3s=}MQ=vsj8RoEAnu;CTK7)n3> zc`werloVCXUB8ODmfFqJ&77qo-jQmDlIct)5+*K?AT2`Tpi@QNGdX$}CWk?6ccDvr z*E$^xnTM$$^892~JtHQ|3?V!EjXaGJRYz5u2QFIiEDze&) zHi{_H$!L3$`e`_9;+(KW&Kqec_mH*sqq;a5D7U<~s_=VlTd|`_HhUkbrt;Z{n)(qY zqrHT+Y@5{=*xCP8q(%^PbqhT{4nL%2sIY76Br6yYUQP{rm}9O@w$z;?i_6qyPZl-x zT72Xs90yLu!GNw{pq5}LXV|2((aXWx;;eXm&~NeE;>ZMvJo&{wA20+b_B3wOt7 z2~{J}74#EpvegP_m;hSRUK*gw0$TQ$-|L;udH1(cX8;|szRLxCtN49QCP;egC!cTE zD@g6zLVDQwyVrjHsW{@5r;;U&$f07HB-(W!dw$S0xI9#THrgM;NUx+x`JYnZ(X5`n z`z~Odvt!xZ?}=dsUS&2|cWxvfoZqdj|LC$93kCxLSJVf{4wf#ilQ~MCfr-Cr+6`2W z6Ts!+t*fa+ERoDa{*;%7qzUL z813Yy52ERS2W{r`T0FTcZwKi1>N8>ZI%x4nwbI*qg~CJ&IuO`@Rs;u_3&$R*P?%}O zs^LV=1)%xbMgE$zx()Wt+7c70s>oorZWCwC~&$1Y~u?oPv&0S&^~kF*6xkD*Sw z8M~U5=`$VkQSn(P7{hw9B2g_kBYUYGR`EUo`@L*(Kb@BCA?20O{9e6a9hy3l%aF|%XeF2IV1 zEW^>R`xMUbEce!M#w5zN!Fk%N-RwFc*d>A-(x|(BzYX|sMnu~VnW6x zu~ORn!%utWlvG)PoR?7Zko#H)9d zThF3l&SFyuUdMs3WG|h8%Yqo{Ho<2BPp4_a8eJXvw8$EoW-Emh-?FkB36Q$g(SK7N zjsI@@z&{|3=E48Hj+NeFi~h1zzp~_ICE|)AXFQET>AN6+)RqE?%@EOKpa-v|ENAO^ z+v;r8WSk}D?Yj!~tESUgI6zK<)C`NTU1-j@^L#LV;jfP`usdm?;m0nc_)?&dx)f5S zT6DfH>zY?o!)Qehoo!qU?NQyXtCTk^H(2%#^`N%SH9?)dw2pAd{8KI9#+H+`EBh=J zCT<@+X<=Xk&gF=&%(!-gJYuljX@|yh>w)7zjqUEscHx)JGbK5;f5%<@R&QbX0z$zn zNIKCAhym6^RMg^y*c3=7Ey1SoM{VOzKbXHfo<$nxmeo6}@j9J1;v7qS0G|c(5$4Jt zA!emh;L6t(ghZlF=A3mg()T2){Kw=6`|ZhlSs_AINR{#R5mWi=Sy)Wmb<=WqzS&8D zkl;3M2FC%ei;wV)8$_SThA!&b3Vgk7slGW~$za|8t?L&3n(lsHG5Z@>kfl#ftI<+g zE!XOgODzwFw=FeW_HF-@CLG4@tcTIUs})42?nS#l)pCFUDg@7rpU%&%f}yi2CRSF; zkG)>~ui(=$b?wZ_=Zs~h!O|$KPU)CxHs~($;F=6J%X60{gHhOTMIFa_$2OE~T5S6< zAL=lSd9#PV3$rjj#8SxfESYI`5kpmcF1pummuad_DD3DY^c$7mXpu*gllWl3XsnF; z5_tTGj15RaDbZI3Fa{fjEGAN!p~Yo5^{dgz z-}MLa46~5JS>H~|~9rA1Y=PZQAY`@%w3+aF*VpW!4lhzbiU-Qcc`qN!* zeMw2BErKa-_1J4yh#sEtH4t*~4ShpO*-w32dVtF(<_km{Mb_ou%oGx{pZ z$ZgVo#T9>4FC^AAI;YP}Bm+e69NB4#H*Fp1lM%JnsbkmC*Jb52_x@Eqsmp^sDz3c_ z(Sc_zVIl^h)vEr;??yz%*DM-eF5mh4UwT*ROV|{l&P(D~Mxm8*nPQ7g$B88GTEGn{ z`l(2>P}!m8@b4&I3t@jN5p`8lA7a(85a!;BC`D%C9`hp3YjkJ+OG%6#7;P!04N3Tb zAEekKW+3&bU_b26J|?;0GGe!U`ay$`V)I|fB}bxeJir0_MV~HXT4n`5%@HWVkTx&} zR~O|C!v^{~kVkpY6~IYZaA#K{l1qsyz=ehQ=Hk0Rh4>0T2ZW5;j3x^V{?wA8xd_Qc zBqt%++I*OLU5&(0rvdcPt(7^VC&EIQ4+?=YVykD(=SJYLvftyuzsLJM>DKBU1a;V% zQ}5sMGRm?#0Qk$*z!q5#<1jO5ih+!1mqZ2c9Q!Y3)?eRDC;Luvdsd{F)e%ICus9aD z(-_?9(6bSt&yLws1Hu!1-`J5)7qGvgcM_yP(;J_tUIwqgsEm*a4GJOjw%6|TA~xgF zb$k*!jxuxKCH-5r=fR7+0`67yt`-Prq9Tw_b^fOopfDnlY22v6QQ7bmkaV>;#?^Z| zK%hK9{jTTrGYG31lQ%%2fMi63ATEZ6w%0$nd-HASu)Zn_#1q`fzoav~z;yE(QS8qc zBLElxT%X1IecFCKhJPd7jZd$#Zr<4Loat4!X|H9wRQiu@_p6n>@+jGvJgNebW>94v zHR8NVNna%}t+V!`OlkdqvXU*fSQM-}-lc=+LCd2i&01}Ykm~S^E)pnfUy>(_b;omr zbr5Ops?RB7a5(72D0MI5yoVXd7Hj^5{je6IgtBFdI-wQ0MJ6z5T=$z#iC<8{($YKS z_R`q7SVhV#OiQp-V`TbKZVSs^wp;`00e_~g_h#4qjM||%ULNM@ru?ax;LdvP zB-V-AmC9h%@VMdUFQEq=52+V%et|Hbg(^rlyp!1knLPllGmpY)`*)8Cdri4&J^ z9h2dBi>~pAPmBFe=TK-5+i+xn{SuhWk_BBvS|2p)e%VJX)tRyuk@qR<@2wZtYF+!( zx*SkL;gwjjiBI6W9hw(Bdh^ORlh|0e8qv&+P5z-T_|hL#$D5(!M{Bw&TO@xqx&iTn z?^dnLXETXXzQ?|km~G_9okw=@E{MzUIJhMZVp-M6lV10SD-K{;Sw5%iAPWT~PR}Di z3upGjlGw*hBfgcC?k~{@IYICr3|IU~w^Qym zeo|9CpB=S6N2|pr=_QSodo1!1gI+fL2dNKYEh&)&W0>xNBI>soYcXi1p zyGf>q{v&<jtzoXz=z1(FDQ8) zg%&EkP3f%Z*KrjvU~oY6UFQFwso^+#f(d$T3y5oox%SEy2iv(!50AMaWVAGxZES#sjsT{P zldSTxbNffwdARPwWGjn-wZH1`ngp7AUF><&k=;@t8h6ka8?O zq8$3Nt|(Ut?w2`e&8!btVZ0G^4ao%xY^`D%tMTYKai~`xss*z>#*0VZU}X)Das@pJ zC0vd}J+jp7&<`O;%$m`96NGEsDm^lzL8BBCOj^(~5}uyhg;q^fM{<*o z&g6#!P50$38HgN8{{r8h_I601^?XUE^=5^SRcf7W_<9rssdPjWzHok-Ln3gNVcpYk zX4SiTWd#&k5rAE-GCButDzZM}Q=CSE@CVXJ@rot0#u_!dcAV^GVLeW|aRuXvi|Bl=de(oSJK^j zF%8jC>qNj5RlyMM(&H@fE;_-CRoPFA`m}c}GzH4o15P85s66`HS5d$sI{JU{M=%O& z{MPF}T};z=mu(%Ze)B2F{4v%04DBGEIxH)gw@u#!v3DUU?BmtGH{32B9NydI2#n$e z@+&mVpV!{OnqMxC+!cWteU+7~+IKns7dg^!YAjC`jc|9m+5^nfvSt?OpJ-}Yjp z;hi)kwr{&g%LaHngv^GGwczsm+qTF?_x2C(tQx?gWv%FgYv~&Ux-S`ujFGt0OQb$F z<76vqqBua|yl~GSiN#bNtcPtVdLyq9h6INa>&C}MH$(mfIA;>S8#Vuj^K-;)#jUz0 z#Y)+=QXX_L*#ZaKHU`wzw)AhUyKA&oqFVmX8F%7Diq0Q$P5^rP21jkFXX(eSiF&lD znRf$MDD`EN*}g096~LYa`F#d#!gVI9@w`uQ>yA4bK97r4H`FwwF1Yw%LasZFcltB{ zKimUw9<<}Ef=xYouiGEqZw4WgyY5hNIQ}CP<;DYW0tT|nM4C@-PJcV*p zuX4umLKoSFUPy(ko7ccoyyT7>JQLqSE^&v4yyVd*#MLzvR8oC-Qsn88ljCkepOM;+$(O9>1jNP(0rb5N*++dnHwtTjb( zydzC?GoXUyn*a-xARv)351vSvJ0^=#Ac7=vWx{f@BFdyU)4E;-# zxkbOQUB>9?YmiZ$Rts2EqZm`455oiA&x7Q45$tEe?t&q7TguFg?}Udp5?s zoR9%i&H%vc{RXxi9#0!WI_{q~Z{bN?t`G05!JB!8bYc%X!v>%y1Ecr83@O_>+m zOdwGX3we@p!2g3EmK!rna^M)l0*B=HNb7_V!&mW{`10NRR=U{m+0Zgs_?MDtb09Q& z+NWXq;o>*X{MbEs>}i$BfN!{FGA|t^jdwjgj-pg*EFs(%)uUmdUa#n&zunSN}nv7DS29sbkM4fn8^D5w92sk08K zqK&%!p;17(88+i&;KqUE^@ecSEaWe)Ju&l!7R04N&RT=ce@FVf5A zliZH*@N{$CIIDk#B3{|KkR0k3@nezi8oG+bn4&#u2n9vG=>2MvT*;XJY1ZSVufauC z(N49cPmqx?i@!mHVsT_-{2(Zrq@Y0r{{;V;;cNG9Q&SreeBD5n8l0xhjW7w5|Irp= zt_f2E^7TGb+0$DIv<>sGn6%0aFH@o8N)#TG9@X@KYI*!V*jvx1A_2pZl_h~TXG#g( z75(p{fR4t}wAV(g3rB6_GW7^05hYkbfsQrC9Qr}(wsKOS|Cv1`W zu^D+c0R9YssZIbmwcqLhx)vzAajMv>E;6NmWK3qw?6AL$c&w+r{Q+aOXRm!yQ^&vA zZISr&tl<;6J`$1W>Qmj`oQX{Zf6eV!Kg01RVSkd+u>g9agKUjqS}7T36_*f>@+0UY zRFWD~OU%2F3cF}PXJkCXc(ZW&8453m8Oqpa#aIlHqnbj?tp&KY7Gn{3TYXcHnP^+9 z$l#a@H1r_m@33B$@SfA^FcA3e+Zyc*&0_fqhP zl!KbHhA7;$o=5Riy8zgyHh1^@bbu+{kmDg7_uP$--ctHw-=GmMTN%S&?9@`moC`tb zNNAI~1NBPUa!jsGO+WZODiUtP<_Q~L*A7y@s6SRJDCm7JB zdGoUXp5;gNkeiV4HfF*)F~7;@s7r>eW~Q1O>>0XnHO}n0uat3-yBq1H)`AT;{(Co< zeD2=WJdw{0?Yb_{6@LJ(|8r|%hlp0uDM^5*TeUA^49%!2o8F$SI?=sHs@wp7D^o00 zy5NmbNU#i}3?9!1c|`}q1}{QgXDu71Is7o5k|KXslAGj@F-|H&0tZfRNs@a71?ZLE z8ox-R{FSGMS6i?S@6%w|&gG^=J=hCJ>#)KRcIgcz-DMb5*Ym(kV?F#WiZ0E4=>8U4 z-GlJhmG=|2c2K_p`5Gd?1{~`r}* zUr;g=UxP2!p3#BSJFciYm`9bbGXwV@3%E%Rg zDvsmtf?IPWu(NqvWv_MS8@*V8I!J9!YvycA28$fSM5ZWv@3e<0do@?oPOS=pga6kH zz>MOfOAfOU_cjC-c(isOrY?(VAKU!WGxeLSI;)BNLiZ-sp&0w0U$czR8Zewn!u$;d z?5}Ubt&&yxpC_qDMZwVucaUdJv$QEKWYg_RjmJ*7+ptnmk1CBesxBbw|c z1YXZ%D`zX3FWGC5W&_0sDA!@wwf3ckMnBS5eKBnPFNv@LG$|JQTYH{_gri>^abZm7 zJ~%4UEr*I!t-4oMURsPT!%@AD0-gq#fiCHAJg6@8Q|$8*5UHm0B9ED|O!A$PU2|CH zMO}v|6}G8|Csqx@Y-NvO!tQ|M<$ZMcEBXmvFlpg zRd{`CGO_b}@do%96#L(gpS!bTLJR}^fYysYb_TnXtP2wasLz_^99yRk^`U}MDYo1O z%BuCe_^4kR2%YqV=R~>X=P;1l;7DXi#y-kJRS472qLx8)URT! zF#NRT?y($~=Lk|}h&>L!je&E%t81L#J=uF>7WbaM=l2Fs|M0!}!n=icE>q=Kqz&&G z{-!tB=lE^F&h<x~$XUi|NjgGtl}fazPO3`MreY|RQ~6h~Gk};pWhu;< z%%7|LAj>+lU#{N7SsbzO;)Kbt>hBz%v={ObCA+g7NTF@(*Rf|6oatkh`6Fhgwxh!R zWpHrZ_Fb>h0(cLHuZMgo0j_~U3~FQcXY)*^ipJ;bh`K``Sm)nhsgSP=bO4|KbP!R7 zsbBM%q>l{$;U{R-w%j7vmPFUZUo%xj!?&ipUhw$q2PaYf?{HECgp|iRUd!ihRq&u4 zKVKNrgvs$@k0r-UuW~}bhGM>Ist5Jlzc#E{|7*Bjzzi?wdEO7W!)IOp=61$%QMgNj zs;HH*NCFddf8kx18`XjtqQb_duWiE7B-I`!J=8=$t+`5^D!I|9>fxu5Tfk>2Q=q7Q z?2399jjy|G-UFCQ6)l%l@nt@!$G(yB-Ysx(sT+(*5=fxJO*5+z`KBHPVoFy3G+hpU z*3R*lea9AA$q)3a2xMQ!ec{ySqmR1sF}-C-(WbHA%2VTggI;jJPxbxL&o`roNjnuR zijSZ2{Qwo8DeDW=5l#+upaW5NQm&ed2wh-ojL0d~iOJzx`48WvsuIc^WQ4zOZ4m8^ zVEqN7CI2((vv9`#p;k&%Kr;=OW8Y)69-lp7_n1Gm=^K6nG< zpAGyZUH0OAhP;!3W@obBrnR~;HJM0M*@G9DP&2ZFlcI`s#k(+nj98$_F|5^d@p3E;D9w$m*)PTVBz@onr_M7* zQb*@g`kh`!ovQyd3yvcAd%?o&IMyPGUZv*-gOf|z>(Fax{T$&MjK^8`XM;OU^V51` zqF^9F7;Qs8_R6FLW!_1ZZXgO^c)+;bSC7keyHZKf{{Eo3eQFfQUHeAroFW`gU=!MP zH->1Fps$QqdZoek5#8-T{6t9MB9i*qVV=O#H~6!?$q2r;7bq14B6@ zpvMS`_IB5)5HV1A{Nc6OYvP8NZQZ9pouh0DORM^u&ywm`KYf4*RcMqD2UvXD3=r5cKLQPwDH&C9>%DDm1JC%K=9su z4)7OMmp|TF*1C(@bFp)nPa{6zg?9yNz59Yz8pKWsa*?E{X=6c*e0k9vy5)!oVf#_P zgcfneAI*kil>8->V$jKg3)e_i;6{@B$Zpn3XK7(g+BC#kEbOf7*0qj!&&XdF1z--p zawO7R5<&nwBFMV>vIbvu;6Y<&l*JVp(Ju#B5t8}4P zIqEg(`TG>Qs8cXt)C9V~trEa>Ri6WCq#?RLfXRxgAA;ID18Rg=CS(4;D8>YfP*~JV zLoNTp&4JSBpJE4~&xE8!=u|lWfA*T^RjAw+yWH%CO6q+MwNle$nGsJabiB-W+mcH6 zr=ro8Kk{TJAZu|OunHdPTB=K26Cbzh^#T!%wo@L@Ma*LUwErMyx$Hy%K$Bg9y1r$cssOlYsNyP=M=iY8WFaNyhdX$XkMo6yCN?K_f5#Zy;n$=lsNr@CaLh)O2a_ z;uc9Nu1UWKfQDWF<|M#nd{^26yr*RhRF%vBUm&qDBB270AH`F&03^FYEyl9N<`$dsbTmB13a7(3Vd)WpqbZI>Q;M|I#12 zz!+Dx0FOKG^oz62q+J&^c7b@}C0M*v*ah02>);8%OIw!1oWNAJ6DMLj-7^a4>x9C( zhud+r+Db%vDZvY9rZ>=wbf278T+BfrfE;_QL*g2(zNEm_=Bm%7*SF|{h!}u-GqfQM zB1Zs#?EBjH9w7UQPooGBP+$hc<@-wW%}zq<*+}4h-R%?Pw;4cC>6?zG3IquF3eDkd zxakLia8a#HnH8AIOMZ>$V^(kXAi;kF;B{3FgpR5zf6onAm;cfi z?C|QGG>KGjRmS~2S&_PRQ}a`QveL+JSrc=C!Q=ruv~l4{k|maMv@vL`Q~~$eHnmj| zXjbF#Ka?=gu`42aUGC;mRq5wdgL<;ix}rbR1o0hKAnGhT5RQgGq>sd~&MTcP)|XdY zz6SnjFz`>YA^8?1BH$@eL_u9t4&^itVl1-8qW+dH;uVbUrQ*QQkG(m{L+Nwa@1)f; z0FsR0uHLFH+Q%W^zp04M^=F*7B06O9I=fm{^@F(Yl}YR%QJT6@hQ2UB_we4&`loFG z5viEW^gakbix5C<=6n}75EC|ph6n%cMaMu(0pk=Mi)uO>rvJyA_yo*IBjcv|3!?e& zqTMr5C}YBrX>(LgW4$qZaVv#$bMmFuDAHJvbg48&?5bteuA~(&6crT~SQ`>hT4RH_ zH2~{h)cx+QSUF0FC=?(TB_@Sj=P8q5?vA};BxqD^Qt>GX#$EQkPrrx?Y@$=@9KjEU|ISal?Qx;~Rp|bv zuK7s+8uI9Vyk_8ky1JWfr3W$?8~>9XgG^MZp8b0>Xf1SCyj2z15Dj(+B*8ZpCKv*2e zA4pl5>MZ@I^#DHW3Iqah@_$-z@?IKX4IKFMes;O-+pf(J-6-iTHwKV~Ko;`&r$+T= zdy&=?41NTLI80Fj10c+SytfE&XZBxznPU&C$~x0F13cTKfQkN}TfW9-Y-4x^sc+5l z-AUgzPl)J6SS7Gx1c5FZGFt{BjX(y<_)1|s5L@cbLKK$G6g#*!$l?4a(EmuH(ViU+l5ZGNjf{)0K}gI`@;>S^nSR+fjrkQ3!%XWi&F%h5KvBT%dX zaW{xH^zXvh>Bd3O)%<-Qbe14@ETHvjw&Yd1#(#S~jpaT+1?1fJzwfd~mRZ~8{tE)e zkS6^GHbM8RUbmT7sWFHL?mb|3AHGrFO?3@+uXM3dUn7k+`%>%BBQT$N@_2ifNV_p!poTGK6Jyd=XDbRys;&L>7*}-c76!nrz>SumRm44+Mf6PS~c2U#m?SM z?q|#XicIZM{_$b%ODx-UKKj&hdM7RzolkGkxRKCNb2YfAc~+a}1h`S+MPRLeJ@P7g zdQ&1;bsm%zPq4h!k!Ju%5VFYwyP_d5)d#c=Tq!{C8olBL=Pdx9dB`3OQ6vC`0+@GW z?)BV8F1#nS>fft<^|*`-+}vn!7QUt`aL9=u4{9WNYUM=yHSeack$^Rw4gb?mzr{xV zrda9UY6&2QNf)0~mUAD|M2iQExMQ~W`a>zShWUI@zYOUDX&U;GI!Gugog)xx=;R6{ z9b2u~uqOdBnV(1N7o#56T<+sGtY!M!i?-f;z8q&k8}P)>Eh;Gd4kl68Pdl-w|4k=~Z>oO1d}^>VqPCZ@@4Kmc`Y@@V z)CApUjp_Sb1cs^zAI^Sn95)kSA`rZC(4z2`Q8f@bS5H zMb#yAX}}4aPU2XatsHPs-_W&c&}K=JNSXa?VoaP!#mbTLG77k+gC3s&>P@x0CfaZ} z^I|LNWvf@tyB3viU38!JtBBT#0Jr?Ehm4Tp>5n}7QR(==zacLZTt`F7l>X&{{qNTT zhAgmLJ;sIx+IRs#uNqtHm*-z=)~rf`rIcK4F-B_<``dOr!{bWV-{SxS^Kd99X;+=%F0xqIx?3m2^jOTv4cpz`uI#e^)w zgrFH9Q~?JmlYmGD?~CC7ona%-rNaeGkrDv{wbtI<9;n5P!s$Ssb_3~f1BgSCyaTuw z;)*ghe%Q1qB`|ws#7ajhLWl`T{HXOn)a)$ND)r1fp~)D{!7AxZ&3##rIb1u&oi+8rSz zzVQe={aK~%rzD&Kl~~m!LlBUW0D{5IB>Bzb@q@c{I&1i^?UhYaByA;wrYr9Uq9Mba ztYd(gK6S|EAH<-;27(tqJ8Z}OE`HQ4zG6a87h;=YWf;)2GM2#n3)BL7kH0Srgouk{CH z93i1a)9v*~%>jdARCLS;7*4$9g-X(hDlT$##D4H5;NwS{{z?ztsAnK{efRB-1d?|J z1b{;;6g?oMQ{?K_Su*u_Ns-7moCcl(H`nvL+G=%D>V5i#?GDhFnML!;Z*x^GQ8YLF z9@HvlyYU#rE$;}NxZdmCXXqUs>Lnr5S&NmOTQ(WvKehs9i1)oDHD_)>Q2yr-!pJWz znH$eJ#*t0(QR2t)}gv@;A9KqJ* zO15RM*q?$xYdf93%Z!HdW6d8^x90Uv`e&*N$y|>QS8%9fMY3>uTaRybmPL4|9^X$z zh(sbTke3J-Kvgq1Tu*85&t zELThXxw2~c%QzOQQfyaK5hQwenYp=-NOR@Tg_FkcnCI=y3L7MFDbJ?C*GR!q-!w z!k=5Z9at|X6pf3g|8}!|0xcGJl*3|ilT5{}YX`+6{^l!6R^99*I_i?2F{ZiMq{ev1+ z0*y2too!nZ5Qtu!wVXY+~e*(oPX@Nyw5 zs;tSy;id?7FG6RbwsB%n|8)Krw8RGa{V|i;T|r_%a5Kl4Gk!b^C%whzF5pZR@V2`U zmy|wE@{uPK=qgMHOJ{uPxW)?j{@UK^6>D<@zJq&RNoH6m@xiF8#9o?_pq`@2wd5>Z z=9Pv)wx@ij5+{{57$KmF@patN|L=EbE)o^VBfL)e%Gjgd14p0+U>IL0zIYp!=Z<*f z$2eidWuZ}!jBSRdwVar|WvFx6;P1%-%c>R4c!rY)BcVpFCWC^Kl;>wqFoUDetZ(Iw zj@3zB!eb{cI3Q8IsMw2h<}2Z}Z7mHfdhO5D>Vp`QBz-s7tx%3Yi{Ri7qIurS^jQry zsi|FDyQQ!4?2B{3q9o!!)hic{?N^GQY+}pMH(j9Ye|T6HV^$%l`&cKr*wpL=_NR3J zP$}MwnTHL$4Savgv5`yS?8c%<-j{tZ0R(j?2(xEo{jYusLJ3}MbD}YUkc{fR?a+%~_Q3`!z z|4gIuRNokUtX+`nhb-Z-+?&^&*VdonDol0M(z>zs{J!mSSbiou^a+>f=CtWXCdfoX z2lT^yF>rQa%sK^5!LG<=O-B8Ok5TOu9pv*B#e?hR#oTae)h@(PZhw&K6%z4b5 zLMS-6m-l+xN;v@mM+v?FN4}|rGLj-bi#rehIsdbyz_P9n&GjvUyeHy;7w0^I!dKyg z9ZrJyEIE^$rsGqv;gqsqjO)ja;XQirG@jmHN&Lh~CjA4^91lbt`P6G2COu^p(_GS2 zrg4)MIQ20KOoy}s7s?%ve)IvJ1$d!&6Vx9^=5`?Ug1K8tu-w3Qxs`_B++XG_-*fkw z?9P!`J_35-r4?7JD^DW6@fZP{5%-gYcf#*Th|RJd;KMHwy^pdp$_}S~Jqr$*q`28k zu^vrsp5dbN8nMSE)gQ$^v$cPmZ2J0Q?aVL;F2kQJ)>x|O0}p9_R5BQJUB}9s8C=VT z1}7eUPy?F~NMgX}O+@l{3kZX|a zH{IpBX?WP1lL-aG$}-q0L#uln!<-2Gt|lzZSVMw_C69bp=A)j^!En1`l+>>p zL*}UTf>)xaI?bsk=jIo82FN*yL?uoq^{yEW|5PGRhcWC394|HDFu<#~=%miQ93a|m zz^L(V-&dzx)!*l}h^r+M*C|sVmAvJh*Qc%1AKg_A*)Sp;^!XOK29W zXsCIR$m3`AQ^*b{(QL6;CeGq@x*JNhoE_~^C%TDnLDnEa>7>JyUDWI`A(P?prHQv+ zKTCd{j_0*D4im1@hR2*pi&;DrjaaGBYljH3?P`<|thU1%uL32H7yA7cD)U`>UE_@m z3@1O2*+Li3)#vxY(G+PU%~~#=W@~<+`E$gytjCl=QU>r(%h*;{+02PH`Z`KdiBT_D z5`~7WN!Ef>?!q-$KQHGgSbw8d>5Pej0U0jse2c_W%bmH#M=o}Y_&EW313QzedE0i! zlju;gj5p*V)Q(J!WY8286$@PY{`V5^j$TV1q1+NDmgWS!htBoV7AIC_MD9+X$#2^p zeQpHOSDG8XPTsh*@H~9ff4wg@&wNH!61sQlHsjJUD?Weh7lHvzK|xit=<3dZn~o zy{Cyxo9+5{JyusV_;S9J1Dobf`_S6+PlIN~PYpuDlEXF2q187(rw%8Xv>OVv3+CWP zd|45NYrBuriI1w~J+bb)T%MnBt+M+1O0+QkJj1Rj zE2)SW33q+#lagG0x3*AAHYDfY&!v3p=|9++NdZjZa^~?+5Wz1ywaj`qLI>@CoeC91 z@KUX<22)=F9XEP`1s$U;8u6JUAFAb8AG7`#86K{zPW|_)b5JFZclP>;W=OwMiGAzC zQXP0MAYu+~_}SFPB!^~cwMFFlwSM>J@D)|i9t~4L2Xf-N1IETmDl#f+RKs;;HlL4U zSte==i-es9%Dc8Sx#WCCl=W6zU|@Oj@v(%v%Xh4`qLb^$pp#M4nYb*_imI7VwCOb> zBZ_d4eQlUXT9bQ^NMDhGm!8HMl~QFJI{IHPK$XcwtCdzu^FUNFDZgzq{g?c36s6IP zKAmVw$%XN1|BxeSoT7q>yF`l&!6hw}qwmRe1%~CVd@()?i1F`b5Je9>#@EByfB37% z?fbD%x=6uHfA&h@=MEnv7AdES6rRzcaM3_|Gk94SgfEVE^`=my%v0r(Ow?o%YRvzre=XV$$BUF`K-RsC7SBlqh_7HPn{Ch}e&3 z2)9F`Xd5w)`-yFwMA8q|JhTcuJUl&=lyfUwI*=?g&&*T_k}H&Sw!hl?VQyVwKJiy9 z2ivb*FzhPC!uf2q)HPq7dMtHVsiL#O8zwk9Z!z8?(c^P>H6a5!`UFN(rfuy`qPHsk zYsYx25N!Ql1bM|V!{+7EhhYT2zVrlx&+?_)2d)C~8DF`y^JHbYwCk-gc$gAzN*NUqHC$lSnX%q^yx^m6X z(lDSi<=6wPqV2oTiUn%zcD`@n;rop2el94sFRl!`RmqEziGQn;HNqq+Kg_t9!gPom zAyKB)ueU1b_cVkYrnyqYGtYl;T<_T1JHOmf^`~@-)WwJV5-csj?oV{&YCZvPfNuKl495?TGIW$XCc~BPhUvEp z4`o)shfTtJKS*K%J1xSO{C#teD!;#~wWGd8y9<7n%X#ow2!gL1@4R2E_@CFu9$pmk zc#XKUDF|hA@Yis9>dy+!|1{|LPN9j7<7Mr8ZytO8;VOV)5~(z0{axLa8CJrX;_n8 z`qFA(l@FT+++3Qk+e8HI3~=ed`N_FhYWTG=zys=tZXh6LPAt+(sL~b&+SU zGqk_b=Re~OFDCul#J@6j*v1g)+<57(p$}7NQQKecD2Q_6QOR=`NhKD(H-)H9WcPf* zK-^t@B&8T+yON(EgyE{N65-O24_dq>rHgBcoQ4CZNq4gedCh& zE=8}nXz7c6`;3qkx%KhqniV+E8ys{;-nHR>qQd+PCf)Mae=@e ziJtC4%#|0=krLVzVF6|9EuRkWy(E|TbF^Lpjtzm77-IBi{b1~asUipVg37V`uIjc_ z4c&D~=YIM01?}wpr2Y=;1w~tG_`Mh#NnlL23fKdWrrF`M3yIp<1h7|nKVW5fp1Vun zrUM%dutd?;aKyI<{U87K&+gvb4`AB-dCrdAqEf0YnHqbRJbYXGGQb1e(MQQ2t+9U3 z3dDM4rNM3I)UL|zl?GjDGSmH{+54qlq?X!5GnZ;XK1y%IvO=&0t<&q0zuG`s6?JK~ z+|prPQ$>_{ChkT#76C2(DN*pfu$q$+Qx-Cr=Y*xLQ2by^%2&iJ?zci9vM?6@P`?4$ z_CinoaJ~4K?Bm2;KMFjnx=A88jsd3V0b>h zz`1e!p+EspXt{bMwxiv_gE&rTa^$kz5EPfF6dJ}jo?t=n?+BM;CB@8-&Ll*#+Rzlq z4AIGox^1L`k&>S(+*xVuq@Y@#rRdL6A=L{|%WM7jKoLnKmHM4mt4|A6_#HTFkXvbj zw?TT$F(!04_N4NMr?of>98pYuID5>`e))${&Bww?k1SC&fzM6!>kjE3sefkm&k%KA zry>Um;D4x_3uSyBtWLCQ_Mc}o(c20qi=kGz(b~NqHx7}LUv{r!jtHf~PbO~#`kme~il8lw!O6{ewv$%2ITWD94RYs`i?_n9)V0SSR4Px&cXy6LO>#R*x4ntIM^jhI zA?jNXkjv`31zABBo-z7GH$Kf(6P8%tCIu{LJ1p)TZsUk_QeMNuNGU9TpSjU6iWG{N zBxq-_mg)<6#<-cX#}?Aip=s7TBy&FF)`kFfQ9bI+aq#f$rZ^WL{EnQPx7c^{u}o3! z0M2H^+4CRNOB{x*N<=53phAN(epJizR;%`Iaigf6n$!y$a>yh7_2J4Xc?jc`(Xhg6 z^>RTTxE8=Z^ffmIh8#56hD1F#S@=#IB_`HkqaxhBp{T<&iHF-nEu3vg6B*Y~-LNLF zm63hU9jJV(t!NCLUbOYE#0yrPz6vN(GE%GxgvMdCL{kPlzbxsznq#D5(uhxY)gygB zZrruA>O{|fl0|PC20l;CeZF+@{GN2F}ZDSJnM4yy166xJ}7>#x~_{$8Y>ET;H~xM7&*CrT9Ca)#0a zM6|ZY65H$Dnhn$1=)&@C?ooJyuF^-PAsZnkE^JCLPZC(xcCsYS$Ae_W)=EItoUHDb z$JhMF_AGSsP>$RbbC`ex6Leq?;{M`YiS0yE(1R6t$TgFRPzO}y!xLn}XEv9Mv!SB~ zdO`5%!>hj5DFuhsZXDg1j9 zmB2Y=lUO1h-w$-!@=kco)Ee4)hZ1>9je%2Faj2=Wk(aHsYUn=?n${g*?4LH=G)Koz zuBx-}vf2{!Khvf(rv;W~^f@}h*;BTRu~MhCgNqJh-Ss*M5XQb%T4;^$BzY}Da${~` z*RN-KLtlaZlGx_JE4>BMgT(3&eZG03)OKT;? z3ahOI5!@>nDGDdW{mE*{bDLgR^>}XB(r_ZhE&ebnPxv{ou8pXBT}fj z3}sDAPb{4TmNjdvNq?GhRZBe`UDC@V%_RW|+*C?y>VlyH9m5vMh*VzQQhbyxu5X`W z%53DI_JwtJ&Uf|?)3eXTO+Dp~%pA3}sVyKh=CJs#tt&>c9)=o_G8umTR7lv2wU}hg zx{rtR-I>lOSK1JX}4gXFi)UYb8@CKUGpmfrPOd#qGSK*}Uh+;_xGIaEWUrL{Yx!kYWbm^QB zh7aWDtzd^XaCtu+IcG{{&HTWUAcpSSc*$do>^qy;zj)Mc0NbS!@a~+qMqhK<2TN>kpD(XCawo*e5>{}l7-Q?gzMua`R|D?Kw3m@2B+{niwL`@{jd=Vp} zc(z>!1=v{~j%&;dW!e*k`=ewT=`_x7wW_$dDO^YyvaF>*Ng<*s80RkF?JP{0gA1Ic z7WMoqYEM)IG{2u3FI}+()Kvo~0jNAQ>+xQ`a8hsg{na*3`S^p`G0sm&5d=;0XvTKR<{F%yUG83%c{k9#&A-f`?60Ei1Wk%&pT_2ji! z>zZEQ7f2%SXzo=Pvi=2TuQf##a(A-niWexQzp#snR!@s{su7TrN5;sFdJ(7%ufY{; z>r3a!z%|C-I%}TxHqwQ5F;9CXIIDXyC&o%2*n^25h*)KJT4BJERZAaJ5(-aiZ})m- zzpO^ja@sqHPSH}E2~K1NPJg`1Ym<#BA;GWoJrSV}*4~^h24m-LdfW_5#ZdXJO?X=F12XtE|_MDLB68o^lHuQ8}5D#8MdNyo$HFx`2#K0r_rsh zH>mtn*CAYf?T#`1%te9-xo64RmeF@PVsnGK;*48ULVSQ*_K;VHybeQ*JGVYz=wJG#t zXCN4w!)2%DgBzO~3FhV59eJrm2m?^d+0T~~=480mNi>AJyMZP)swOR9digIHgaTVRsh#d6m6~kaUeg*l9mi*KRs$BHi_GqC_dWe&}to62uArYBQne0K7 z)RQS(1OOkdH$T<4Xs$%<%i8$zj)N%# zxN=cI^lqx)%~!4?!9xJ1ud>Zl>O^$~(w6ACTi3Gq&a;dkpCAG>r2$o04wP1)>`gQ=<+$a))8Qh~ zgNnL88ZrLUwLJ0iG-AkyA)>0<}h?S8IULESkB4l>GlC_=zKN@|mf=&bfBQM3X_ z!xIr<9ywLe6Tce`N}WTEI_nGE6hbzre7rJ#{ptQ3Vi&1&8@s4@)&8>f8hel0oznYy zxklL=_AXOZ=xmQMeDlmLye0@W((l!yxsiDnr+4j)`FZ(XiNs;|)#r~RLCx6kL4Pms z%7mw3kw-PhTq_Q9Bnj19bP5`1M$Okl6AW7_^4EB}Q#(g8H`H@!2}TC4Bx(gRHS#Mi z)>-;D;3*rUotNLs8sg$=Uv_W0H=_+)=MqyG00;9ClecOHu{V&tCwv`Hee^w)mLTZb z6T*D`a$kLa==b;T>*?z~X|LVOp-;E>-}H7*gO-;ru3kTZm-cD3&+a!uFJ2cluXHW+ zPpRgGV27>H`!a)PSuF8S&bOSpdFqz8(YVa653FtNTbc@2Qk5SR3~vAK*U>|sVeW1T zxJp9qM4<@_30qKkD3dOQ)&-1}29pvxjhiLtPdf&SQe3+FI@Bn5b z{flp>=o>M+K$8LXep^wKP2R>3-Z`S8Q~-R7=zfz3z=6&W?sWhJ?h;yKi>?xS(pI?Q z`#s-p)l@!v0)BR`%6ZzPNKH-cT&OX#I*_zFZv#tsme_H~o>e4Zr5AXowWq5g6d|Z0V ze#ULWWbAgCw+m+Vyen3~{XoH*hi@Q!rIieww2MD9X%+&PrkUoPoYgz${aG2xz+-H; zD-p}t7l2c3-uZ91{OF=>N|4x1!Vvl|2Ae4Kc{F;?LzHIDsM56U&jW(o?GkXA3@aLh-$lhP9 zcMX_sgDjs|X?A+Yffs`VK`#7-jR?Rwh?wL&(Cbv#_^v+ZUwaQqq92j8g}9u0NWDK_ z!QTG4< zv`&E;JsCOr{VWKd{_hX&HrUd|UFz#R1oXXJxd0+M(dtFV>^0G;3;D6Q8xDYJ83KVn zDHQ$(JNFrTlNItzdM3;x!o!CFf`8-krArbWg#l@@9sVqTb+rX5VTujpe|Bo#XT0zM zVE5eTy#PYXpR2xCHG;IHy+DKFLi{&2TowSgJUPb7gUy^&1cmYk0uOrWGsY@c8gqug zvz=aE=9RY7wEG#!-1{CUNC|i!AT~RW(uV>J-O;uhMNjO(7>^r{uaQOwiw^GgM4)lt zz*qmSj~&_}2nvOzFlBfB4@FgqX1MQL#?o)|eg|N1Km~DEKO3Q>Fq@A~{v&yGjP<{( zWOZq~_X<^-Da038ML_$sc@ygw3fws>{N1>My+G+@c;8hF2HeJ#ox?iO5M^q%mfr9= z!3lDJKvCikv}OP)WVs`pg#wWHip_3?Bt0LLhy{Zgyf9%|H?|GsHKyS>SBq-n>J8C2DO*lb= zg$g7iW7mGMA|QWgxU?wWW7C&>8ptzkCGWYi2ySt}a+$(KzdM|x8PO15CKLtJpMYHe zu7kK}K|967Ps^=vx$1q z+@IWJK3Vk9)c$ONtnu-`uzjaOxYYrmA!{n%%pP^<+ zK`SD&`s``fi>Ld*%Tgk65;OW3fDs3i`3OYKYcECF+sz9-5?=`obRRwHxZdFDZU1AB zoCzjYlg913R9sj=S4EqBrsA^Mf((l;iDzab>}flE?f7%2fDUwVO36g>AB+70Kv+OJ zq%%_!>KC8F(d*#({Fm+>YK)Pir)0&K5Xy1gqpW@brIEagC6%})06jwJ4{*(j@Tt)! zPS}{{OWXOtej17z{P6ndcw&Wr8{Mn*vd`2KMTQ&X z2E~vs6r0>%QH0^nB=cqw`|4>MH-$>cfMVo(4Y8OXqg^x&UgKC z$!)`NYS)T_kal1pgtl|}KH)%?LV9~rQOy-V^xY3TxA2x*8a5mL&3F4U*})OPVk#k+%go@x-iDVLnn`fyS^p;G?t``bKW>Ii7hUx zSL`b|RKb%V@{1~{;MRMp&_FAhROaFA|AE5E+7!?4?gN$;i|moo7&{iAX0yoh z$!kk+Gr|Fs=dS|e#2qyM5q+}|j}-@(0tA%Q=QsCpc(W$4;a+gCiYaXucPWb1no7u0 zJ20Am5%B7Hs&hEchb{T_paomsZ8#8d> z7&0$1!6W#wASSj2A ze5yATFM1u?cP%^YfaGD`=-0_PuXcHH$LYaPOt{>F3+bJ_=6p58B1i7O4@+)eo^1~A z9TKJlMHBUnlV>+ud_XUyms&{%7_vT*&u`pRHjZ5fUjx3?zoMVS-IN|q1Ll%VvWgBi(Y zHJ%shritA072d;Ms2~?zB+oeK%NVu;pE+~_HJd?pz=q!wDn}JxW=B+F`v+H@>9z@~ z@h%tF2q(ZEUF=yf_)!eIGulj3ytLmiCIRZ(iN>r>k8-`3wgv+-QzdZBcq)f7o1!1m zy96J&j&VP6e`#nC*q=`lQ5^WjmwK2PxelLpqNmvtJMR^tO(X}Bgeoh;5Ds7Ic~oHN|3^8`VY zjhn(#;iyPEBbSg&f$YgAKG%nbP2%iJf_!M=W}@>zCOzSOi^G@wtc4Bf#z#JG)SMYb zW#=Q-^@o=#LH$E`yq=~$*)bQYo(S|q;z%T%_vbze7dIqMNx}KCmgDaZInf!qyc%O& z=Yqu*-zMB>zI#EQljX%I-1a`*BGFI7HOjDNef^Y9{;&XLj_dofsjjcE-q|L~Q6zUs z6KmVo?{86{Fti8jSEhRzC`SYTo);^HhL_em=YPc5^&@+u`d6nsn`X!$iU+Sm*!hvL z%C{FU*$r+lK2^OA^|?afLwt0Y?RKU)=7#gV559EHd>Mie2n+TOOxftCn{v+h)+MQG z=E^P|<3j{c0|7DMQaRrM@DzY!3FXigpELV?Z=J)A^SNcZxKf>n5&pWN`9xlM#zT`P zec3V7s_JE>IHriucW&t*3_gaYG&*SHXEDQTpy*!LmR z{h{scqH4qVSaOUO^{wptHN(zR&YQrqi`Hb87Br=ozRdfYyR|4Ke#{AfYwg&+$Fae+ zsjpA1rMjo#6y>eybVE=zUg%)u+>bh(8Ey`w-VkX~beV69+(mIj`VH$ZVhwdcpoR}= zl$`x2l#n5b9SG^K=C3>Yqnp2HW-6g6+}L)AdJJzVy*S+?F0tuUedW@xxYWq659a49 zWFBlWwi_s{hP33gjnA;3)7TC8q{wU2;)=BX5&wiTZ$Xy}nGu>$0facnrHXtlgC4UJ z`Dj#Lwdij}E|p17u|oT7bY>EV%G7;oZ0bh2r+)AJq_-t-et(n4!D*{Uvq{a{G2ygI z?Ii_u^ycu)n~UvcH?{LKa6}@8GEIVsiR^_%my#94An&QwZ<6E$6V>+DV6UkA?ZoRq zT{{Z6GNUS>jN4463en!UZuu(OHUX=*GPF0Jj(xvBSQAwuBFW%tN==e^hl-Er3DE8= zoJoD~(fRvb4-7r{ANz_O^>4ZV3EXZmerCaDZvgVugkFK*jNaGwOhxCa;@uk)-NlXZ z)p)G&*BRrBRm+qb_BWkP7%%T3F8heS?Y(cLUMDO;DwfgSeqne<_=^OsFj;Si>&o)E zij>l3b=vs|`g#G~ntK#g{V26N_|sc01PWXDEjt8CPeuedeEoJ}WkWSgB=C62ZGci8OX zGN4}s^mwIbs?p-J#s38BOB(QVpcN9q?DCc(qU)(JL`lp>33AjJdEi3DHopbv`5+xxUD{nQi}lqS|`BMFdYNeY;tg{sr8 z(CrIKtvJ3EV~=@3t3DG$UGi95+|f(tGpP*p`56p9yh+W}t;%s!sK_C++7NcVV^>ZK zwmhMM6h>-U)pfQW#mr=d2m5E7n5*^r?Xac1m5_LH-J?SVSS@NVr~^boW>*W4m5@3= z`QGuSPB+eh!|GHt8>aF$Pqd^m&a!D2!xbec<<@cTNaR(9Kii2}Jp5Z-&qOK39L)OYSIkXvW570qHPAORp##~EcZr6$DLKj$0|EY|9H=Ae`GedxC+L%0J=Ru~nm5QpWAoj){V&XCbS_Rx zO6z-?XQ-~+HiS{Lr4(Hyp`g$pn^#^oXbS3pV+V!v~mQMx_Hxc~+ zaG#xQ^c!V!y36)y8i|~lOeVwC_!oHN?g!ceb>;Au&!Visf*fj3C1VZJ;(eY@lr5EH z_f6yXCruxn=_qDJ$jfH7;-#uSqP=`~pk-pu(Voiy((oqY$I>+9kVwfrzn>mA24K6t z+q^_pDTnH>xVfJ9((WJjcX*W+I}ebdaGC-GxAT%ff~8^*TXem%Qav)3Z1qh;u8i*U zIMMGT#$NwaBB`}A1zvb!R{Mb6YeT)v9x(~l!a<>R8@kb! z*TBpI7OB7<9c4y4nhhOO-{n;o+-qfPs&e%4`TJU2Ky-}}dkXghxo;t&$(&vcqRGa0 z%Xo%+q^Uo5E0^NXQ6G0e9`)AF+~t{#IZbsJ_culbmO{=*=s2e?91R%G#(|lRzeleg z7oa@Slvg08GZU!26{r#-RecAYWBU^a*mr1biWcIe~}V+sD63> z{Ha@gkpvA3Q%0>FGm2)5=x$x!r-87tEB6{6gOV!?mpirE&9E>);#@{J))lN9!A72* zNps2d$n4{OwNtGJR?G`fL1Pct$oEaYj{eR}{*t(2MYaTIdmLr#37P9`GjaL+9jnsd z$Pjax0%l?T!n?U6ObaC+Wh+|7JMt()RX4-$)w+H-%D=V%#hZ*T9hy*y|U+8JN%WwLqp zkt>h_Wd&#aMs!NfN>3Qw$OVB(vl9vQERV$ve*ZNKlSJji%C!Kt{i(Iw%{gmlqNBeg zN*A<>o|-*r`S|8e_7{oCA8Kziyz> z$9|;?nhY-Vg%Xv_;3s<}tBXok7PbFl9X2^7W-3S2=j_;?A##cu9t)6At zc1br1)ov{>*RbbzVeknhzp3D#KdW>B{-mV(OqjG_eqn|h4E^3sa^U%850TblV#_3p zP$2jM$Xjxi?coI%l_G8v;vZn`PGI3cO>m`v4Crqf8YR_#yItrWQd^pCrOUZO<=`JCTZEA_zt=FqKQYJG45p^J0LU{$_N^tQR+%3YhOaA zYvoMQ(Mb}H$8S`*+&K~c?WHH(&xZj=%H z+MHHl@8X_dO|sq2^vrsdn{E^j^gH2@`j&AbNZp1n(H!+y?MNFJ6j~$57tBLfNVR-h z)5rl-pB9gKa~wP{Qk4Y@;3xnusi`D@cnCh9R>3IuMK3?ei;d=%36BrR;;bvXofp;uUvS zBN2mu#$PSFjBpQK60BNJ)FlFM#d1>%eYEtZ2;BAc0d5O!puY}`)ftVx0Igbe>z2oc zgQ5TIpeDABz9|a#L?QvZI^{Q;_yCjzZ||%YO8I64RKHaP>TwI;u-O&OzZ8|h9>!#1 z>2ZTVTz`zYR(NEC2z*ZHzj?PW_ue|b*4Ekd;U?(A-aEE{1SJeA9t_g8gAd}wBDKBr zg;b|Qd@_8*;iBr9ShwRvGVirnK*x4Oj}pXVq$AGoyCx(EjA6z51Y`o4r9{NV!Raln zW=>__V%TREqgLlJi@7UMRCDE}o$cXdcHO0r;nP& zt^$qr=6j6)*srwF!VW)z#ex1b&0q3PZSboNk`(oK{>uvNqeT=z#_?XaddCY_u_l|g zuQ$SEuNK14bwCaN)b$?CsiV^kjyFdR4M-{;^kM7TArz65G{t82J?;MP)_>7cvRB!P z-wO_r)d1I$pJ88mm=ftf8B*r|L5{{FMbuyK?^2%j5^x_9Z4~1x;Ek!S?qd@kHSHOF zPNu))WmE8*0k{R3!W>r2I)C6F-zID+5~;rCZ_5H|8U!5KSW&@Nq7!)ASErR(pES|F z1g63*bRhgi85-cl^e}yfL|Hl*oF#kKcSCe`Z9sgfRK|bOuw%ETp{( zyFZ=l@p@{tY@i7<3IiH z@~EUb)1tYcD2UN(_nBRtS_em9VZQAX5*C1t5&Ovv zodU&#tofs^ipZeN_)6(@V!GGy8~R4^SQ9Ydz(?Cas8QR2S4gu@0Fc{l=Z9#E0C6W! z@OSGt>0ZBF1I`_9pvQ8wPN~3m5I@?8L~2p7$~k*1E6EBjBaz}DT)ghup2c6j1ibDx zVrk}4x9>G@U4gFv#lEaR#@w=M3xoB@UX5XMY?-!kD+zgpY$fpCr9L3QI0Q<6H$~CX zIbEvHe1k-4NGZ|M4ayuxY~Agd-l8JZl7Mjt!NH+~KJbrlQU98eHcqI8@j&SvSVhG% zpU~Ac)2=(ku!W;8i3NC6QMtyB<<}XJKmHw`b!y#O^7-qvmfAIzG=^{IBTS!KbTfU# z!JROK*ciB%G*cRZR0rOJbn#gmi)?Ec(F@gTCCXv(ULA`B{7f(7SlpLnE9F1cyhGkr z*f^%F#Fz~;g>-%Rm`$D4&upxV<;$Ku&|yMzhPM}S)DQ!03!*;ZdSLg3ei8oly&dQ= zW~YFa!O@!CB$EJ(4z&^AHzrW1=PTfCt*_JNu;FvtHB`?CX2+A`K9702`Bm4|@*;5C z^(NlEkm=noXuC=Jl-0VKWy(Yor*biAdBf|ey=V+#(y-3y=V4L*R>E3Yv$}hIPYuJq zZ*K1s%y%ze=^mMb$@rQq+;WQLp%ZRA^L-XxTA@q_Hhl?nyXOy~i4hP}hTq|>TpMb? z4hllrbG&4R3bEcg*0LpXPNRCCb#gXEO`k;f*ea$gTMVyyp}TN#{qkD*&HkF{CYeiP zP8J=5**?0KV&tSCs)uk!qN+wBI8it|AXfdFx@YoNAiZdW;4Z}JqyF|w1wNP=^(AM` zH4UvLU@76jWWDWZk=quXJ?b!6{An6vep>tj4y>qA(&mOHL^ALP{QsVp=;-uEK}aRU zHz=y+!Ra0V7|f^T6#Pdb7lDKSj}y=T*Av#3cccb+O3vOo7*2OckY$!R1}hqBbf8`J zTji4rp`8n=?s=((2614HnJ<2u(Ye#sl)57VrzeDLut9;*H}mTM+K5?K^%tZRljy_e zpyr{SBM4nR-_&Ga5_ca{Md4(Vx*u|K9x%NWfW@E|ZIjl9MCcVJ=pgrjkLEA>OXs<+ zy}YHqFEGM%ayt)^P4R9v=Q`#5tsDsPE4ZpJy`cXTENzm!peWr|MOUFrJ0nR2ivz(Nf$#Uy~g zRCP2elTY#C>kvqD5iK;mqsc!*fl#GDly91?oy$a@3<|dW+r2U#Kzum-JRugDlE0=X zEuv_y>%)33s4?&(Q51iYXr$FT@Bq_$&i8R*i9>}>N#-)-HVlbEG7vj+lB`b`P~SDRYCL_^eK30^+NjD`GvzS3{6NOqS7*uDqEG*LA*k2F-3;;*Q zB?z=7Wc@uK=U}c7Z?qm$mR$sYMt&b-zn6-JW_x0z9wNx^dgv=#MB3MxCdXZj`jy-) z)yrz%tZ+nEP7Lnq_j_d*0V*sqOFPQ1G{Ago6~z-fgd?JXOn-+ItL=4NdFIeT9wUMj zfF_=Wa+CWU9V$Om=z0FI`Z{MFjR<63>waB#*xifsE51Y!KiC; z&|U|!t)_Q5B(auC@ybX!>rYNVRM#LXzK}-k_rxH3h5qe2Ye8nnFv<8r){wj;qDD?n z{IUL^sPxMw1x`3VT64j`;{Hj>=-6ygJ95@6phrE88roO9n{&_QlS#cu^83jm7#+}er{4C;_0H2)D#Y|z46P6;{}vwW$)vv5%#So z!<^tTY=Yq`{iIT^qn`QK3SD zg5+X4JYNw+Pm&-Wwo@N8IE&(o>_|m=b~+pfg)zqEh03lqA0Kt@1CNC#iK~oVer129 zWZqHprAe*B>7N|W#Scl3D%^5u?iF%J{m`%WTGjp1jzlal*?gqhJuDhbn{14<_+ zffz$=Vn{|_Vg$^j}R5S3`vf1Tz7=vH%>+kIWJMr`mbxE zYyO|2o8YSayQJfD9{6V@EE1w{4UPT-l9HL`86DD7_sjdd5z-l6Ol*TWch9!k(4gmF z*)u2T~CKG{EQ7Dx^Hzme$joV_|C1au=S_NWD*y3q*h4_$N!0Gk)MWtVEyPhwzACTPEvPXd$QZ$4taw3qiM?lZVfq8TVCH`Y9t9REC|SQ+ctT708Z zq1k(O1vwX;7>$jUi-ssua9LF-9F_|HvdTqPNj}#zOVM${8(ByIOlS4bKI=}=}$ z?#Fa-FS64v7_b;%&V+9$5%v;j_IS4J-{t8zF)LK<+0af4pKwC3dm=?N9@wzwBXVxb zSCc3)zm}TIvi(m4E zhW$t5;}-6&|Gm*V6P;i>_3SfKM5?dw$CJVImb5J~7gIb1Kb;}u5O&enO9{1U)VvTY z&iRlQNlthJX^#V$K&Vz2aD1nk>Yu8+T<08#O~95Q%|yt#Sf@27Y&U6$aMQ;Qj?#5>7TC{-@~+RKVo?@d666a}e*6a^$!iiij(AT25&9YngsL_xZMfP&J3ND%>%-U%H9 z5$T(nG8eL%$a@8p0mr@pFPJ@$BQ7| zn+C=PAUZk_$O!m=jxpf!8zJtGK_F98kOBwT1b!|8Y!5 z&j8B(&)?O~oy(>BuNHIZ|FcC-P%guN9y8(cng4kX(AYnSnU3L~zcBwl`KIIkFTUx7 z{~OlhcA{qV9_Wm2+$5Y3%pjW`S{YCV^#z0R`&%nq45F-=gU&O@B^bcbG zC$ap4SpOonf6+g#rl)5FHa2D^=70VEe|&H}5Ae)>+y>%f1>FY5gH9Sm&qv3=M|a#s zmj`s4=^qUKHQfIofKPxi7FITP4qgyF9RmYBBLfq_FL37bzXqL=kBMJO?FzGi`9l_I zKSA}E$sbu|u2!@QSq$T4&p&z^&c-e*aza$>^cgw%vkDrTTG|&b>Rh{i!@$tU_@?FE zdsfyq_ide=T^_r-xqJ8r1O^3%gg%RS6&V#B6C0P3`u1H~`uh(Vd7ttN3X47$f2pjh zuBol7Z)oi3?CS36?fc$8GCDRsF*!9ogTdl{FD{h?=MWME|Zt3Pz~!N8Y+kC91AjhX+7Im<&o0crJ@tb$jQKUTD}$(*;q3q5)| z%q}defjLe1t4sgr(f?V8!vBBu=wBWBSAULYK%5M8fWR2|KoAg(CSQJrREFC*8Nxo& zk89WGY9&O>^?g^e5}0ZG1=6?ntuf($Cztd#1+?}H3~42e65@uZy=j6QB2uR_^m?Bc zzOd4|XXtRivD+v9fp)AKJb>wm~=eUyY#?G@dzT7bNo$?_ZUUCvKgxAl0H?xg+h z-2J(7sk<8R2P;{0HW_BUW;18DC$=3d7h8)xm0QZQ`BlmbzOURAWqDKd(_V{%w~O)c z*{(dpMx5f3sJ=D~VI-8kNc$ukrA!vNH~J0C4r>{de!bfX30~R=uRb7Q2w16_R_^s( z?deD92hVceTK{~)(V5n8jocdfqP)Ic7<5xq zPSj=a7n2~kW$Oix=K)x}RnyL%;~_rvex?*RseFG(>9OV`HqTdHCH&FshN3KjHawp{ zmvdK=igDk|ay^HlkGd=xdtB~jw5O@}bEqsgT#?mTf*thjzPfA*?L25? z@3?EAnnAxC&TYhNtnfl@zG~~T#Gs)0Wv0KrA#$<$=SZ_x3C;^*qpgyjjb+W2-Mpw; zPd+a~AMXe2!3M*b4^mM-D9sFx2RA^l0dK-2*6W*z#xaOp&yep$uEOI{wkJOY4?~&{ zYrop8_%bkLq}~F?1#)NP7*u_lWR2x8ygwtuIlA_d$i(FAknY8vy1N(7x|Zm<<{{6} zu}rGM#au;_tY@Z~1=HzG_=EM&pXmNBo=U2`N@&-d3SsGKJO;gH!c6LEA~5JGbynKk zFRT(G<^S?0R1{l74Ft6XRDcd3*C1Bn3SUpEw59 z9fLMA$sDGOWW-E-Hw2#mNzxR^Uv=6H4u*O(iPI%fg++r9rMICTdlQX{;F*m@&E9zD zUwPw&`4SlUdxt?a`#%hrjx9@^In;;h3*I5I;s9##YtK{?EC zpR-PlH@#t3Ry!;)ehdm2^Ke_}Ef5duxPS!X`R;zKLIo-vcpoI;U-o!**Z9t)FDAwo zayi`@m$P$HxGd`B3tmaS_m;`VB;aA{>$8iC;Y<)V+BlS<*}C)^ri{lb#cm)ztuBEp zdxRNo)Y+_1-%D`y^;&Kf5Wtfjjr4{MoQTu846yLRrGDNJ!p>(n*0BWdw~KOi%~&yJ^pqeJ#gH=<9wI zH}N}(PXH-)qzy~7zZLRsKM_vX{u}(W%-=xgMo+||YLwMXbmtbw_4;!sBnRKlMJMk) z5r0JI)t8&!>JRbyIybrcByBA~Fa6gs$dt-Ktfgi&8#2ukKj2JNH?3}cKfPI1s^$Di z9jvnM@Xbg)AwvAyDgFyWJB>k~iZ;YxVztS7!B%x@rQZfQSQ3rqT<(iL6*X#Sd}4U> z7^DbcqWBWbVk!4A<)kwQ@tPIo6ur6>@wCyUnmE>N@4Wj4stQ; zd@~3#5=~?tQL5&dO2rsN7JfGIRApbgbM<3(N3TSsg1kG&#f}&1T}TU4m*}rc7cJ8W zb#ptu)YI=Q-`S$aOP_meCrhPR2;Fr~Z39{VG$T9F`urA+36|{}X=<-GGC~fc)KMFa zuM-tVX-d7z6h(r@{n@6Q&7vor&Rs$z*R`X<(LAyy@emP`xcS&I=v&#xhRSN_`8)5n zlk;aDC7o>`UGDcfH^wMc^FWB13E%?wE6x94l%RHT@a6?JJP`R4h#V$ZSN%>aHz|uzs z(4rVs{1_DO4j-44qgEY*yd)TU(4spKjLaD9bUDfQ)~IWml=H+0!sFI5=27Ljwyp>z z;}#d{Tw*Cpzjd^z!>C{DU^i^(w9sM3)wwbvm5&x*C+1jjQfcG!H<{#JWqaDtgdd+^klxBe*L``}dlyyU==v5%q{o`0b;qLZB^661;ud{6~uS%Y@QSxc;TyIdz;2=`u zw$pG;UDkA|uZq$(?cTe0yn8${{vf}DutkQX*ra%S}YoEUzgKEu>L6M=}=q(BSvyQQax%H>4 zk)NPG!gaFGv&A3!#k7RX9wa@COFRY<-;y*7H7XX?za}xEW14d)hqn4_>rp z>jYw3mqU*DA{7!n(+b{7roAJY@4(aav~AgswovJZk_9}(?3@y&vcbt2e&;uD%&nP% zaN>R&4iYd)6#fos`n);8p*GzKYwYND>ldJ>U7=sa6X~=tX19BVs>ssEp!RFWAZN4L z5?exfG|FX12+Z#Y(`_}?hQ6M5w0)kkZ16!?Z~hu@>KQg>r#XGc=C~uyUg;hTf11MU z+?+Uqr%%S$Xkmtn?bysju~HYGL5OM6@i4iG#@#)VI~M3Wt+4Dl5O&@Lcj$UWe+R9u znJAUy@oi6>6zuJ&vtM4Osq4T6GY-SHSeuH}?v=IW%=f;PWNmx=y6+ncU5|C}iFLNE zc7V%%Xq9#h#O)Zw2Os#JORDRTJfSa67(jm)iK}UH5Z$>PraEsEpThLxldoElUirzm z1GEtQ=g~o;5A6P8Utl>;G(qK^UqR8kFKa2c3)kgdf#v$GE-3FtJuNC^f=^;xJf5`S zE-rs6qRql0WFSs!x^GW#%tx}W#!cdB7HmUW;nVBVGWm(b6{u;r;_+V)T;ImLRf4)052 z6~Xzkkx&?w50LoHf(nug*2MG)llR%B?ETqcjpXOqE^ZjmN!`m|){RaK$sO4wb=2Y4 zc#VVgUn^sWYvgCOCvxtn4`gkV&q>|^`Fb(3L?s+e?%g&_|JCt3G*U@+?(n0^F{p23 zzUm0Q#?Y;*-TNSaP5!A|?OCi9VSP!(v=*@ZGMHmfd`92^>HOtNt?sh?@oTNC#(R2A z7qqI1YYv0H_1-<{^b|K>2B9M1^Dcy>YsSq}IZ)nfDZd~?Z`vzOvm7pySJsv}7pY*v zHB45zq&R-O^e8E6i`M;Y_xzkk2JB(x=9^cFt@NTDFJFqr9ERBlS@4CJg+mxMO?j|A zABqtkA)Z>czxjXEX5?gQG;|iFStuH14*EPnZCp5I#C#XvPcN|Tem-e@@~G-J@oh~l z@*y0V{0FA_VL0k`aYM-rw3xDsXm^9@(@v3ags6oP;!J-SLgM~huhP(xfD-(~+Z&8# z5#(uSmxQNkdwW}?Ui`~Hs>~sfE*^76{NUQ;s%15GS+91K}mxi+bk^D}|PBW(J&!SWA3Id;FJb!<%$N>cAaaB5lt& zEjG0L2e~Gyn?8nYm1%@^hn+2B=W5SSmNiL(=y!b5^@pw%lX-Ep69<^I1tdPfz5W=~ z7EpE$x%2KA)M>W&#l;*3CLYjco~`t#8+ND)@%3ng?NH^O0Zc(>#f`^5;#Xb;qPaYR zW;7~D*G!TI6Ms(|i{&?d60dWsZHSwnQH#9faE0*!&mV2lPnvZ*TG)tNYjv_$|9u_M zhMd{VKo^|D()r&1DY4IhCE2p`i;e?LRK$~F%?GCgsd`73I z0AF;)fxlnEy8SBVQ?}2emX_zY*Opt7K&*^k`U?4w@*gdps##~RvD+dB`XNU_bVNCt zC}K^C2G|kL68}ONjDVdgPfN+Ie<1S2Jt!jQ?ylBrklnO`Z#a>onB;FY=@L`3Kar+e z$j;%deUoRK_(Cft6|C?;zGryv1JFjiXM#4aE{R>{htKuk%P~n(^hIgxGkxOX{s;N+ zkSi}dirNPR0-ee>b~t!yZKn-SH^flld}QeAj6Lh$?e0b0>)Avq(`zEa1-_uLQfAP@ zxC|5`%y+}|63;r!;~4Zxu87hEP2Nu{cM0{w{J8bO7^e2DtfS7jYH~nsdzU$M|B~nK z0G1~fwU{SIOq|dd!w2b|46LmY!4lhi@R%2MGq7?+S>!`XAVT9PUDPN$1CAu5_=t)Q7cKYgU=Nqk7MKOP~+ z)40FJcZxtojzLagzWfWOZk9cDDbq1|{A^#-HVoJVqn{qS-Dy}j9}eo_HeASIY>Gs= zacJ;J!Y7^Hu>Xed2TJ-~SRubVI0kKPkr`=SfJ=gohl_ilYD%s7JrF#;D-(KJ-aE^c zY!^IT-_2dW+D8{I2`=&}Y!Wwn0j~6kF7L*@nmlbx>6;fbHUDuVSE@%S(^piq*XuFL zYVo#G$I|}TgYYRD~r_TpEYWO7K}&l!(FC;l*> zGd`8JbN9BGmW{Ahr>{CJ0GTQi(QC4%%hD~AluUpN)U|aYLiM~TRNZTQooc$ ziO9Shm7-a+`6OK^FDWAV;dk1TieWcen(AvJrBk-I-F@u4lBJ`9+xza`yR`+D|NSz> zc#n%6GM(8aDOS}qtY=ZRb|Cz;thv)NaGr@Iu+7!1h0WFQK1hadGa-~iLffb2>J)k~ ze(sK?-r^qR{eK0PpPeSFOW1my;a-&IO_jBHt;mygyuE(jum!J2Zo}9!{rnwwCjGbu zU%wV+>#tmw}=$~Q?NFGvA-oC@OA?DbS zKTvXbq&J`^`MALUlu|v`VTe4A+itxZ#Gpwz+YP<0BG=<5J$N<@;yT0z^VYp#SfmlD@*~=>B0Q7gj$8_nvaMYB=7WP`m2AdT`)htqg@8^c?2nYjf3xQ*si@uR+vM5% zL%vVynO#IA=<#6(1v+TpG3)#Iz&M91&mX09D$P0tXX6}@Ef;$zORZkN_n@n3CU3{u z8sAcjw5zjLzD#T5%Yy7wzk{XT8Yr^Zi7J?C z+ysg35?M)^=DJ@Nhi7V=geQ889@fA2=AErl>xx6``kY`d-a7`BpeO>%JsY>Ek#HXO zy3bA-==K>UpJ-7ly9+N*`n5~cm+y{JUqdip6n?U^oUb;)v&ciNF0TBsb#>B%UD^Oc zWz)$f=``tcKV~nN|1qV;zDp(QlOB9MXBeeXkz}@Svxf0+e0SdCy|{`^hw4wtNYecF zYM9=Q_P6-^r#ZV(@ce~%jCsJ?prT#ikZW1(C0$&q4or{`VR#S~``Jkn^*B|CW`V3` zX+un-u+du%coZhR2O{D~((ZUx)VaaY9+-QLTJ%Jdb+fBn{EFzC-ev9gyTbR{nNj2A zxYR=gliowQg8U_q-MHr{5q5bcj}P(ZEW)AmQHNc zew~@MdnTdU3nt0=QUuJ}(5!mKIMryR7|gfWGebYwKh)jb|6}7dKYvEA)vs91UEBq_ zM7Vh>(hPV)!tdL-IqFbz^*Pq{S;iA9idP+_@sq?)GL4H|rnW}VpX{=`&Eqb+QNN1Z zl8tmr>~s&iA1P-qm$W%v9$@H37=iJ( z6fbcYQ!6NR4>1FbqZu-b2RRq+8uENlp8v!j)6A`Z@HA9&pgZ)BJvYy+Wz{>3x5mVi z_>JjRczj0|*ig6U?!8mR9VsauBI92IUBK~~WxAKDr)WP>0Ov7q!AjC7&Q#F`uNtj+ zU-?s_Rzr(PgvR$*UZ#}+7AUp0j-=j*clb_h@GDIowskG7RyzDrGsi>c9mcbPzbjiN z+Ui5=K`D3S$+%Ci@5dE5 zcZYKG*^>3{EZgseYsa9Ly+>qS?Ej=!@}es z0F_;Ks5<(5Uw=d3-ROO}>PeDk$=1xuOfQx@RVD8A!iiyGw&LBlAIZiHed#_OuwOwa zN_F3N{cOeW6bHf{MyM{%XWzXV#fEUdRQ;rKz+d6k7E$B}6JuM|r*knX*W{n%x|DoN zT=-cmnhKaMPZr zQ?TnwPU8>lz~?s~FJAxk)U@eRJ>6~b$A9dLUBR2ZHJ!~7vc)mQ1A{tYHy|l?hU2!q zdsg7|EP4c@kv0|a&J7<5-B zQHS_dmB!UdqT+!SKkZ)R4Ei$Ox+965qJ`{qRII9PYQ#^Eab`5t{QQy^HdH%5_w~>2 zbaaZ0eczmu&xK3p^w2`D74=^`_({EH+@oI!y1cim67(Q#I-zC>iuZ_I%176jZJ|7U z={xWw)NTICD(wuk&m{L=%GK<8dsVQC-vp|rIk?RrQ7pomv@+fr-{iVC8F69lUf0BJ zG-r@;@MiMyC~dY?)kE@J9pUFor+ijKWl>El*^bQ@*T65I^nDlJEAUlkN97vb0o`&< ztE8LlAoXY?{Xj&~)8}SaA(2{_+`A*)n0U^xm38PQu_w+cAXO>f;7h+#TcQ>Cb>i|eXq!JLa>?w#bM1>_Q}Uiabm^CgAT|11<-);6P1y`u<~vMz5zWsrJ`OVr z^!JtJF1+wy%%vgfGBeNna!$t`SHXBS}Yqxq||^FfVGRkbs6-a6o=&&UesmLh(j4Zp_Fk)uy|GwOTecd&Vg zt5vjpxPVyqh0zt^&pDxq@)KZfnJ;M^qg2Ub(1T+Tm!~5aHMW(HWZ9K=5R?&>y+{>a zz)D;`*OX|pna5d2*XDOl&*%h0)5Y>q`L8E$epL8crf^ddiTCME9Q1r7=yXy4o~L5% zyOf)gv)9w}jP@W2IzFFDVJ8WXlRtG#iUiwgQqEnEP};rJ^hM$2SjuI3)Ie$nux_}r zWgUv~<{-;-=3E*HAbVo4y2=m-d~1P!aG}RY$El_iHKs~~xGhP3(dIwAF+ceYQX%U@ zH}0`@sJ9rMRT=W_=+);CQ4n&n74N+_GUzql1pZxIf@nXDaO3jq(K-h42C|T1j>a3e z5?4c@mX`b!w9-SbCvn=mf}EfyOwX6dvhaRHH8Kj}#S@Y6nZ(ocSRBDig3sWrM)e?H zY<$T=)TU3KTpDU^wQ93nvp*gN^%*j8cprmIG8FAQLT=)JA2nMq9D|r=C_Gn1w>6~O{*^Vxjc;V zxe{S;oENj+sO?`8I#Rw>&ZQvu zWF-7|fh*I9*35j_FT8{N!tL2@n2;|JV`8aUTQFeRj!jRwEI!N0mzYJfo}Z*Wq6n-+%3b3iqL-w#{UB1&3la_U3t%}gj&l|mWTEePB7gLt+o-3hSN|?03>pln) zI+D6KaW-=Fw#ymyxI8^hdbR;q(cipkS$@6Gj4Y|Hd@% zEa(~tfDinIAOJQd07LK}-~ndVe_#h#+5dqWU}gU&asGq2|014$5dcTH1|+;00OSD+ zu<>%Raq#|srhlLb+Wvc5no7xg!7dN_d-v};1`Nl){+98-`6JG7Jp8we|LtWw^0$ot z?PWarw~YVoWjyw`jQ{OrJpQ+g|LtWw@wbfs?PWaqw~YVoW&C%1{O`W{^LKpwKfStD z%EL#>?9AaAQPI1C9kiG=7*)0onAA>H;_bO~e=bsxZcm${9laUi3kLwG9G+MA&euWQ z^r2Kr&romRb2Uu4Ajz}m*>%ZN__PwwGWTE^HT&rwsU5iKUzHi4Rry@{W+&WEj|0yl zPX~mLVowk%ot(&#eCbTq(=*mcF{&_lk;Ci|Etk9eLjM#s0Mw3)ms$!PsR2bLbSq%KR%Mtv$vFRO13|l6 zCpgM0Ys*;mD?eDRMaD`ui!86XD0za4f;jDnge1;(G=jV4FaF{9&Uhy_EzB)HIdR-v zgU~B%lchR12znmF`hfK!%SWN#>0k*smo4RL66VrSLUl~Diz1`x>2hh2g6ZJM-8!EI z>+BZ4LC~`;LC{~NEp(V?LtAQOeNtGr*`ld0RyfubdtuvRuzF23PsG#jjF!Q}pZLM# z9^J_XdRE4#JkLOZRv97QAH(8f8U1<+vfpFws#+MY$}?b-M1icJ0m=zNx8aMK_r+eS z>Hd9dK#uslW}ITQ{^Uy9#95i2h?(*rk|p^Xg^x6o0*=(z7=;-s$;+m3ghtOiGFWwF znN>*o@{6SgVC`Ogw)fUjgNur^MfY8o#NjNujmzK|6g_IO#8HWaBwNl>R0!IUr$(A3 z${hv@*VY7|elMP#J1Z?xuS?9{RFnR~^kYv9IH+_=Ww2k$=A3# zE85F$g5-1At?Pm&gj3NA{om~DWQ-LXI`U4<{V;m~I@4;FP9#zj?`ZAB>&W#Xq8>xi zL^41#c;Bs0WM#?~f8dIuME=1M$LSp!0CRF(~et#oWa<_aC*t zQrDJ$#vn<5p8GyTxO};P?X&wN-~6n-e8^H{XV3aPdn4YkK9?t3FO2*U{sWju6xU!p zxfe(fYHaaz39I$W601JYy*B#z>--mW`o1eYn~QM+KyrSon=C_0JCZnWL@N8JIoKJ4 zyZ;qF)bf52^q95b%nSYey8622mnvn>_w(K|8yawy>hfBD{;G>*=|a-M6!7Gba;$!n zCuUy4B~c(S^i-UbY&2_AQW+@FHt5sC5}VoeXD(gALBW1NX@~%ev5eolK$-9p{u#r$ zJPM?jgenYAM|=r~YHZH=k!DrDFRq&v9@@!v&Fwby=Jv&>_?e$s7hdt>8snRrHLAQJ z9c5tIV55DN$M3SRTP}}Q6R8IOvllB=)M1Afu(^U0-$2w{%Wvr@oBIYs>llPW{E|*C z3jDIp|3&ABa0TGg6CZJz;xWB z_z0qEr*q!co23`Rx6j3KH=62Fwp`%Lx%MXk`GoSB;R{}_8yN)_D2)U_yXC^}@Y4~p z!lOIV_3e(iuO1oV9OlQnTMC-%f^SPlF{*6$(%mz#L3*)+aIIj9FS;Ot5+Ua#1Bjd`2=D`IN$-e;)IT9DuCvrYPQip=XD!+v31mFM3&xz-$N!(b1BB?&n4=o1yzl#`2BC zuCjc#xBfuUrUC$E7uC3n;&Ad27{+Mqu!VS95v)pS4v9(bmws<$J<<&sK&{qL zK8GZA17(j0iVzt0+fiV6>i#M*%6O}EI$L8)y8HI1zyAE}(t~#Y0bQ-}j$bURIRJ`@ z(TH>>L%G>@rOVXgxxFEI%{#X?Zti$dg^I{Dk0MU(#ujEiSnTJ@Y09 zykzs55+PU7yZFA(G_mPU?}4=+x2X0rnWdYTK=5_iD6%Fk7B5Z=iXgtg6LWGDs>X8K z-0`uLm~DRYvf&=R@yn&9*0nP5)DAH_npi=y*6x}`a1UatqiCKCj8$x%)$)lBvg{2| zBskzH7swA%o4(b6DWBRg!*?|nMXwN4K4L>%d1r5^&wjb)xpX+9@j7W}=Z*p{YvN}# z`5NpDX@d-2M@i}hVh&T=tY?Bgo%vKapIe_?wz-rdYR%T^lBesp8IsGBatvBbNAaUv z5hp#+yaCV`K$(+xo0{8(+a7cXc5o2<&0eqd?$hR`Y^}FW6%Hw_pQxoMpJPx2vho$5 zJ6twYb4S=AH-k&~`-`mWz4XTU5GDC1LEDF!EFM{6Aj%ZoD*ck717^mAnRHUJMR_i?bOTJQ)|_ z>~jNzP(xP`vwa|oMZ_Rqu~*du?U=Za5}bYuPT*~zpqJW3t%CR>qoI|0!Wn`@Wh_#3 z-R}_Ze(shO@9Zw)r1};@S@dlrooFV@YkD_^Pt;h1hpH%T9LZAy0h7|($`)tE!%$UI zeR84L)_dUQkZIiOHwn9Hps)UW&b;~)a-a+l?M5K!4{Fv7Kq}Sat-HCNdaI*tC(8rg z&vU~&-JMogb6=iT%1u52-qIEBF?|kT?EvRRQn^_KzYZ0E4?SzGzz*@*4)Q)%IoQk} zVvzXy(Ant8T6_D?%NleCh|N$eGyzQyaq>oVL2I-!KbNh%j*@(Ibw;Jf?g*1&}H9qOD!%jeTz zpd4uP9@*KBHU*a;Kw`?8PeUTH_^sbTpPu(MB>Jg~oOqIq8NWQ&6f$>lx%CdU7_wMK zVHGA6b5OnA}CittEQ(NWG5!=lH`U0t_d%cvTHk@hdRJJ&~?luWM>ncK?D8~$!fM^ zd1xS66+XF~S+2e0)hj7_J#^72gI%u(C=$L0VGLm*ewctWh3s@xuIX^chn{{tv*8eR zR>||tj`tElT=M*~>l;5ufBYVe{Sbi6)D~egW8mByB1b&Y-ayfuM&`@Vr&8|M&8zVm zex(o6#AAYHhaO%A$2LxGNqq4@)Z9YXa1BM5W$cijYa%y`jos)XJ7txAyIwHg+ah=B zhFR}7klEm~De$QoX#8mu{u>_9FOh{cRz_b|of z*5#?ia0S>y5+RhVM3HN5(3c!7ioTiF(}p#LT4wsbPf^cmcKab?LvrZ@pm zdXKETlcwQEKy{07V_2+IP7j#$!M2WIcHKAkr_v&d*9m~sbMIp5n` zoaV zDrV|YqjBq$N}5fHm9?98Egn2M@S59&f-sN03>1#LNz+rvay%#DU~?SQSA%N;|QwKPou56niCMTE^#< zGatGP1mhy>(1xLvMF|jZo6S~93Pa-v%QK`4=3fokD`dm|ZPN4-0Kjs(u!U-Y!vWB{z8(ca{iF|>f!!kc$&Rd! ztkw$mZmET;vpovE6}N`O%&{!=wlIOmcjDnvBwdVIr(IHv;Fry+d85EaBS z0j)R&QG__!Al1>a>6oEJ4QIS|oDTxmZo4s5)#`h=a`JU@r3rQH)HY36E{8N&@3p>#F zkQ!uXIUNPSYKE7RcrYtniUQAbJu^(Rg1;HcbUaq%!u4=`v=|AlhJBLsTjWoR9fR;Uk3mV3Ia<`LGJOgAwxg&zJn{G1 zq}pLjRqsP7*V@zph}vDzcp4qF#MAFYt%wC}P0QDt;(g-#P@y~{LJD20-BS;7ht7;s z?AIq9S*ypD_qnvLBy&y#`SWN*TfXjhaaX@MwE>-c9$8Qp`K~4M?IXpokckVwIGJvo z0Kw_Q;WZlOxgs)c$fhBxjRh@Z=&O=FFB&oVle+kpl&nVJu3^r-R+IuTt5pH! z$i6Y?;?Y@aH3^9d`>v<}*Ceq3ZdLqPAXtz#<)}h{zLrZ{fsW~2dj4#8Fni>CV4&CT z#i4@;`j&5Q3_A#tyz7=J!Kss`fv?;ANY*m0>!oSj)3!c$4C);$6{s-!6qz(2UeCQF zclSnL&(n)LuaJ1dq=+Cf9l*f}95n0ES491oj9OSK^X9icjdW-DnOq5X4L(fLHE?6- z|EsE)bS9_>uP_5iJO)(+m6gndM0Bd8E9W1g+&-je%?)~<5kmW@59?ELkZVW9Ktyc? z%+&H1M9uFy~{VhO1niEbDYRdyQu#l#px8-7DTBWsctc&vGtO@r`*!& z_;27%aI(u69?4R3I@S%?BP8g;4ekvMyoY9OegzCv31PNd=T(jvHA$bpYL1lNTX{WD zJ{QuWHDX-J;glF2%!H;!t}JPcFzm|_ji@;q<rZ_!!E%wsu9cK}^^}Dlu)7+S*D)kZmDGFdB z!tF_)u*f#mgm|(R#iYvfk}g&&fhT6a&-smZ3eB=F@kPL1o)x$5i3!w4tNH59o=v}; z4@I7Ay2zLuChCh;Y1%Jv^-dQ!9$LGQF==}u`Qz}G@=jd0pIGZDR&O-y$qim|X7Y!r zGzouy;&0%7FgQ>_#Dj9(;iH(5d}4nd|V#(eJT-ac}9tSx-j~eukx7iJ-6AePPlW^m2Q;p?D{394v?=jvIPy`zj-`icn%X z`lpE7-rkUNlJJ>(a5zJ~G}q~YRG9Ujc!FY&7K*#|Bq_5u_;RS^$x)S^Dalv1T_aAw zdqi@1I(?@miSi>5uWYbA^$WsdAb#-aPLK9zw*G{8tn!;~j`s_OXZKz$aQdC{QaBSj zB!S!lM8rsKq-OYPAZ8ed^2qx&gfpoKcLq0e-G$R#mL@d>8L;-i+H!v6q%TC}{AF-G z(N`nw*Y~G6_N8$Sh{mbk_r3rNL-cX~u{-`7oAEyzYywa5YzEr0ftswZ)cvXHbT5%> zRwDbBhxRSVqIncJ0d9_H=Ps|g&QmV$J4!jD>WwBy0wP25YGz#l6Vo1CfbmOEb_?%_?{2&wfms}T`B-gw7 zks#1km%~$oXMTr?|M1|fcd@%x^2~yr(Wl?3KQ41--qvQ*X5O(!ZYq-b)=?F6l1g#p zULI@=`Ai?sR9B6<*_N}J3DDzR9w zz;{<4yGMGHJb|2cLkEI=9AWH4#54!djc`B_6u|{G5uC8JBIVww&2kx}Lo>S8^ZWb9 zy5cZIi8zSU@Tk6xV^1iTXFcNDuYCmPD$!9APtCFo`cQQBjh)@)ybF18YBhX<0U-8i zV3MO|MQChxSQPN~9DzVY0cvoHEigaVM69cDO1E=OOhHUWAJ9BsQ6X;2ZD(NVV@v zgtu9^wxg`~Dce{v2RZu@SN#CL{^4*!bjRVF@8aP_4B=Nm5zwLWofkAdD5Cv#F6n_D znEAtE2<4ve+nEcT4+0Zls1N5mOipnRjIwOpeL-ENmTGJ{6OFgx%6!q`dezXDbk)11aRG=J1Yt0e9i&&4bk-~m zE@&8_QH6yHav0Xj1iu5P6&f-$d08pwW?Ane$ojNC2tDMn+x8ifWv*so!E>Lq$@I}V z(@Wj`XXp2Jg0AfOzq%(#M`9yPw(Ii~qA5Z`t-|OCf6P3zyV2i6xU|()Bb~2n&p?a# zzz<1GK-{F!k?!Gvw}E8$An~&uN5N6vJ132G+=;`pu?_|d`fW{#x*4^7M*BK68^FFO zL(Bj-JiOd~CM5pA;u;pk|Nb6%?p(9lF-Whx^{n*J40LuD7re!Xw`^+_AA`91vO{76 zz3t3BJqr^%o?oBssz^7RYajaADV}uFsReFEs-m$o0rOWAFPTA;Ce*zIUl~b_s&B;) zj<-|_uYHhJ$ferm^HkD6v=Jm9!~;F0iz|wuDHmj=H##KN6)B~?Ipk1+PKWz`Q14W5 z?v)(hJ)rQ?F4_U>?Sd;-UB-p({R8WR8ck-a2ptfW4`BW)kUhb~HamYy==a%2o|j17 z!e`MQSPuc->GgReK3C5_0;rJfxIKOJJZ=^|@j{=Q8q2>tNn_7Oczesejj$tl+-%X7 zE?5Cf`Ew>n}(pY$Rq!D?C6`Rr1{(wH3W{-B=1 zHbmV`zKZaarv@fZD5#?lhXVyys3q=9hzsCvL-CNsj~S}%*;iGkJv()RS}?3N?yn2+ zwuj+_y!an{hX=ea_pVCnX5_PMmT!hawg$gwRh7{uj0@Z+tYta4bQt5e-ZZ8*49uSI zUaC96xrx3>X{WX{+hKR2Ab5*%2GT)Wj$~@L?VqTGqB&dlC#4Ce$38U2iCQ0+jl=8QB`i81f89yhUd4M0rB%dOx#1@fJHDo`d+_i3^5_6@50)(r0hQ z15a)8a^kwGfSZD7<-=(5IeDV)*3omW=bmKARY;vnFQ=utSb0&KjL}RewImrIlcmQ{yHbu}EItJH) zd6LY?d?EUl=RKdjvTbdxXn?AWT$*J_rcPZS!Hvm%{u)MvjR3OYL9{#2RNQRued%=d z#*8JNz7iQLj5cXw7_BijJd0l+k+??VxPlWQD2DD$&6=Hl>GYS4@!n%udVu7Cf=?}#nv z2PEDY!R!tehO368;_AA}`Ltsxo|u6P4=UrfuW8`(V}Cy{_^@kiGiK15ne=Sjt1k>W z%minlO>ba!X5wk=GWbu#uqtS+O^7AKedog$oM^B5$QCtDqf*4|=Ns886d|5=FusTa z#b*-h@DihLGpMLQac^Nvo{e8*K^ZF5OYaH6X8(&ri=9$}j~PZT)ONA7K4HQ1|X$Tt3TwB>p8$ znB=sW9=SyF59QRS|2E={Hfu@VktpmTH zIdSLCUr>Ypz#AO@jcNX$jg4gNhXZ!_-7=!117lthbqbnm>-ch#1pCb=2^OA*u4$7v zB!$0|_`Y@0Yd<#7j0M^>dqe4CcUoCt9~ozM(SUzhDR{{S{PyE-hCi}^0eS>P{br== zw;Ppf&|Bs5-$vj)dT4EO4&uXa9HhIc2)`0X@tcI16Ow4`zT~@ZL}i~^`qk6TR`~Om zT9fmyojEL!{i9f)22(juXolrlFdUQGf0*7 zx+io+_E3I~oe~e&Gha9w$&GrcDeo@vzPx6eKpNZhDRr`YDVW6Htz==~V8gsS z{Pt_;e3Qg)9u44{DB66Z^_J`BRk#RVGTpC`bglF0fZxgVcH!mi5smW5SEY>^-s%(<2%~LN6+rC^nvl$$oXaxu)CEC!2s%{ zl3|K<`GXnl6-40>(ftVvrU=Xuw-Az~h?^;7Gl$zm;{2Fb(%q37daT*mp@C&-<0x>a zbOQS9Z-)H?oCrl&aWNFzWX3XSlnd8UD=9Wfy4d+B-C$>45JbFH z45oyKbR$XfNijfi`v^1g$|S`E8?UvS>74vdJBc$UOfbN9t-4$Y2B`6HJNR%gO(Z$L z89)B}yX?0M5T}XiU$?)1`uVFWFGc;LVSm=w^9bjpYJ?erU0*Ro1P6UtJrslB{&V4v zDcJIIKcV)PFU8LY)hR70YIbU}Kr0A<8g*ZB-SZ`c5m){K3b=x2BE4znO@EUfEs**& z+`PRbv$s>1-=clB^g5-I-YKixBh)itTat)CNqP8N_#i?ExQH5t3GR$hX|^m0$q=?>uCwTn<#u*V>7iZCJRwPv5>tO3EGn87{%)a(j} zO~0vn@YIiXy6roY%PU)KH~}&Qc$Q87AY)tAhPPFes(tydl)UFg{0OkT-pM|LM?S@7p=vV4>zK!BubQiZ1z0>&xG+S>wJCx#+lSfd( zK;EA0n7xzp+5^gJfB$Xf%lhHe zI>_ReXVyL7=ow`D&P&^S^HHf^Kh}+Fn%>~QSWx4O;%YV;sx}^;{~5G&b+0}Miob?9 zB&A<7oXo>3HXX;5~WN?Ecc+r*eDvTsqi5JN;|nXF@< z7;8dy#xe$xWtb6TnB{st*ZsSH&-2{(@%;V$9>@Lt{^M|rIeb3ndA`r{d@rxp>kX6+ ze1XK3aZ3R|*F>GkD0bmXV#r4i5IJYYIC?K#4%jZzDyRhptJiq?TXPJAY#?uRLT!`L#@vy&H#k?}H(0XcMY>l~e`XtTkKyJ?2%|`#0zc&o2yS?4mP>r$9F$zcFP&5@J?m7IbH>eBA{$!$QIe?UJd1hwT zsdwFQhwEqbXy`t|CoG4Cq*gIo3>8_kVVQYkZK8e5`Oy~LPf!z;ziX<>F}SG#h;;EjZKP{O6O zRa$-KHuNPDh#g5hGGASo?3pHc*Lq6)x zK`j7V6L_4<5)SR0at=+;>B?0kHC7C6hLf=$*x(BEi%w@QmW z19G78vv|zO32H~C(Wxy8l|ayF@8uyeSRd~z|6yRHQmi;tuSr%Q|4!0Ax)YoV1{nm> zE#Z$FXdjleVkTGzL`+@ek$Opehp7W~rC@yx^T6LCa+Duz$ZH_7Eq1!OlOSez;urE1 zT>KHfq>;S$AqRHO^|xi|?774!iPW~<-t_x{wOaEqFgKzbRgc;9C$AFE=PmfBAbEXy z;&!i{Q?1}g_Cf@oC=LnMXhF3)it6({t9UUjev$36fdxGX+?^V42jWM%Z%+?(;4?D< zpOr}RFa>#9ukT(sR`Xo)Vg1)3unwdJn!w7e%?KVL36nDWI@P0&y7`!T9*9ak2n#Th zvhTiN$Nwr{D?8US)nx2;1bDa@Jp?51T0a}pWewJ!H&8eVdRRwaqjx_WAHt<Qe4O^f#Y_c{CnS zrhbN7LGJv{SCfRv5@UfopgUiVGSTW);C0#SbGj>GFq15o?q%0(UHt6xWlSp~hn7X% zXQslHB>O(X?+#bqIvY`cS#m}8N5nhxp}OOsbcya(%4HTel78ox0?x_yJLs4J`zO=0 z4GoF?(S>&Q*~N4FtBq3vZsLls{Md622`nDqrC9w>PO5W&U4vrOTO_3j*FpcVknn#>h^|bcW35}dvHv2ae}$-^p5(1 zd)ppOm+rv=awHNhmme?k^U?^G)r}2F26(^1(32nb$^skZW9;n~qJCG}HbnwT@pJS? zfaRI7#26>Y<%en=5l{#PmAcIp!xQdxW1u3dd=etiZ7=H+j?vw9$pLcInv)1H47G4C zYtbKXs2SBIQC>Y~dg_&Pzx3M%PZ7__X!xV0kHCy#oFB)5y_|8=)U49nwvw3n7Nj4|M zhfT%q_ij4_TobR} zbRN27<{+|Hl(Q}yd_Nu5-FW}BJ|>?-QIQOa0Ubdoz@Po?N5Qm-A}=FkvdX-xOf>`N z`p(_V1p9@*;_T<`k}=>7y8|-{l^cdn}7E3b}O5o?H7Dp zod&4&trv3wxsslC!c18^_!L5P9V*6vf|B6QpP-URUah=_ei(foIGePk zEAAGZkf9-1qmAuX4;C?cd%N$cIo)>Ho0aLv4Bxnf^FX zHKv2a-f6e(^>O-_mbaz`ufgLtPwk}Rj@ggCJ$C&+3ulT2{D1um@*#_R3y%LogTntR z;<94kOyuW*ZC`69qmyczeLc*u#!^&FfO3^txq4*9UIG758JZ?HwCNW7$rAY&+X-qB z_a9wtLo%gLzm$Zl>A#@PL31Qh+fn$-EUt07Eo2e<62Ujd2w14F~0;w7xtf6_dBykbE2@T=lX=@zE#Q2{g_#?cHQR=?Q3q^8Q;}@g*XY-eS4qjF8@>uXyM9~vLVVI{&}n5Xv3vK% z0yo=%WIObW+UCImG{qiTtD513)K2tMtK1XP7JW=2Hnb2{s!fjm#Wr+vrs17?tMk(K zWcF;Uf>A7h&NnE^oRhEZiy8C9ypa`sd6u=X-=X7iWGqN$lWN6ab>6W|w&3 zwNU=WYa+wbj`;2><70|~io-XLepX}Szjp5|rG|Q+cA9SDJadf_+L3v$$p)9T2jM4bIG_oS&k%k4Kws+@8n6Ps>)TXyX1*Fi#|bfPNvsh~Cix+zsUNr89f}*d ztt{ju8P!WyL-yE5+R6&}&(K=Q3PiP@2tg1(+=)DniQB9w*7$m!xBB|>{XdtJ$_iyu z-zN0_J#q#x^35yK;Dzm&hd<7ZFPp1oKhAl6UVYX5QQop|*_&DqsUMupb`g8Y`5!#A z@;*8D1p7XX(LI-8-2H3z)Hm3fLo3dXHUOs>`H0mmb7_2e0&Q?i^WcLnY!_hnng<;+JpR*pXdJcm`#N zD#v^WbTmPqo`&@-#>OPCRC%0wF*^fMDSu;v4L+}aXwpYPP%0xu{lO|S&vd^Bsaf^j2xvcsQmh8B3cC3h%ahX<3Z zsfa1IF2VA*lPPygDf%1(;X~~02>&4HCk18tC5<37q9CE6s zBdpx1m+aF7;1AO^$NVc*&&a&MwOW7OeLB7cJ_P^~k<(F&Zzn_zuh2q2%+7i>n`pEP z)IKd6mah2zc$Asd`*|uCWZv$5vaUSjb>-RkV^3NUwqoo#wAIBd#_8Wwb6RU9>NE`V z)sFHcz1d)NZPc+txZgD(8Ve!A01BzG~H(}p}>Bc6$~th_#sxNt zqptaSfbnt;Zf5%=!&|S5Q`MUee{f=lc(pIJ)^%{5%ebYHZ_Kd}1=V1P0cGnWtRdE= ziIxB|>ROh`Sltv}>9y)=CcjGYZ>?h0&A7|^Mj*w7hc9%11_RJ9oSQWiOpiotCo(Qy z2#7#BB|dj!L6VKWn|yC7 z5q$#$bc5=_L8faKdOG;UVW>p_jKFuJc%x0_*E>vqVXQkiItSE4a-(L{M{YqSy|p@kQf6aFq)tn1T-+kP z=wjl=Xv*%9-ID{gqM1ARxtrBEy|-yn9QJl%XJ4+LAOYZ0LGVHvvN|heZ>^3g9gO76 zjny#sE}rdF(dfxbn>E(X1W(`O*5_v1^^XLTEy2^F3m$PKxLfg>HbQn{)6hFS&po)& z0ZL!vmJ9F)b#!q_mu>6QuOZz69(n;<%E9n|GsAUQ)bgHgw6uMF%I4Z*xYC-th{f@9F&@*xD;OG-*2c!+x?jAfKTB7( zY}wyriQ2J!+7mkMwul2TJ}- zc+TGT^!9>%6xIV2eQ4i-K9((CJ&I|`I_);tm~Wgd|Hfb3ZEf_W5$V&`l^un4$kaA* z=qo4zaft>{plrq#fRJJ=vvu@*wp_KN)13>j?ypO{1GOSLgL(l*gW6Oe6z!W6bs%J&&ztuGUi2>n1L;~R7YLowvY5uRF{y+GU|5nrZ2T%Av zVYS)+O|AYX%=$m}k?j9wH2h;H{GaeN_J1R@{t2`Gk9{QjzhZUef4U?6-%N=8uYbh| zc}VAJ2uP{|`v~A86wL@js6IE4E}P-ZtX-zr~yW$ELadk2=-A zn=<@Qzoq{r!{mR#^ZH+q`u{Ju%KweTbT-{2p11moiIIiiQ?|V;ySRF~8zZcQh4y9Ztb)0*oZUya25fR0HXjM)>p5_#GRYa;9xp z(if+ud!&2?6E||i?`r6s`u27AOv?KgDgd<#w%Uyb z@YPrkEC)KZO=-Qqf@5o7*~XeYvVXS!=~{yXv!(XO8Vw9m2uc!B}qRt<9!vl8BD& zGMQhPBHA%TQ$%fUQ)(6sbIGH`xA=TC@}nPfttwNjh?}ebd9JfmaF2Kaf6K4GMKP3? z(K8-P)GE3bYe?oCEsxl2+dOghlH*joXpptbocYhcMd@T7R+QunW0_x_v+b z=E=|zSPC?5!fx0bA=HS8v?w$CZtZINEUEXW#`UJnvyqe^lo71?NBQGILjT1_a9K?> zuq=Y9;q*!qTW&nd40BKRRhj!fa>>@L@cNdyVaE%w4%Ur8yC9NGzstBk!4gKllK+7i z^1e#V4N-+t0*>*0UJROQb0&^ejx2p#N@B&)_B(B87VS=}31<@r-`uLs|7l-!sT+#& zQiyW{On2k2Jy>*wfn5_X~C zo`T?CY$c5IHR`J@$Mq2ob_%9|zZm-%M7wBLM>mH*8)gYuk{7Rv%-E&;WKHrF?5l`Q zFKYb!fs-KlHU~C;lBtWL1AN1FTZSu{ed%5!Ic0`eD=K>}M=pJ3{UD<>#caYhUDM<% zZ@GGA0l&x_7SHqYp0b{waCHpI0p2QQX4%mbgcrzKaK{k-PP@etDmtv7wa)(1?94ZV zvSxErMoqr*)}1-X-2G?8KREbFu5=?)x(5981WU~@;gIf?>dzZerWoyHk!@n;N}jnB zAb!??Zr=@P5tTB8W-OScEO}J)yga$(p1`=OuS~dzbImi12JW}{sW~Z_;XRj#lWd4e z`&_s)EsF>UFJe!^O)17*`YE}@W?g@IlkNk9s-5m^mbTA1dJY?-g=P-`&I8Cj-TZMZ zF4_a)P;4j_Uz%{m!ADgte_fVW;MUY{Sw(I2d*$MH@5@*sy8o^KKR4|jN^pXTT8{-J7M4$rg; z4ViquBJUMgGhmvcC9VU_y6VYJee!XB9`98jxUM}?E;3QolHNOe@!Zkx=DSwFh|W9# zk)13hkdo#^K)YD2aZ>X@4bkrbroM;?FZP&9I=kcSh4{>~zbZ_(CAvQR-3bWt1h<-6 z=H6_?M(P$86Zs75PuAcJub0a(wqmwx`W z-sY-B(Qg~x^edGK^Bi+i*f?m#Q_Cig6HMlS#gXf5&n55lGU`%W~wy^2}5 zmEiW9?`T^d@Z;PiGv9~LUH@D-Ze%V;U9b`Wi@*VH+40~p!?W;! zA1n!m7R^hmtoTVzqyyKD_V7OAzApn(p1Ic*4-UYgl}gm9paT9(tTzfDh$B>^I`mWH zow^dA>_3||eOx-F{Qh)c@ELb*=*c=^;p~)&g`g_{Hh=SPGK9-0(i4;jz)m2dG+evx?5%7FoP95-9z^mcf~K{J#cdbIhOdB6K~W0k zBm2JEmxGlz4L8j=9I;0-&scFT7#7k)ft_}1B`w$E;V>*H1+I*p1qnlq%eN%>+RtdJ|pIV98L)=XuiY^;^!?W?P3^{cd zzJS{5?m524#IIy`n2ITXzs<%o_QnV_L?CeiV@aWeL{Sv1$*W&2`OU`+w2NmAKzO}` z0e$G7gA!&YHYS1wQMHVj*sB|Rzo`(~&tUpZI0w0>i)3u+dVbr{d?Fmyr(RzF+d%CL zW}q(NXP}W7p$<*5SRhQB65rqsrra0;AH_o$dTFTkR(KA%Sd#nn6+D z(F7>_b~I-){a&oau;GA5xZlb*g$CgqCY$bce)til7{Y zuc&z1&G4cR)>?2Gxfjaxc(D7#NWP6Q;a1|(r+OKv9)p_{+1)*r4GNW z*QjCdxT$SHZ{o9uCqmuV+Rlr)wuGYb{Lu)dRtfN$a7T z!StcDSc)u8YhGqpp>?`Y^Z4(pP0PBzJuCRH@L7)>`umqE*AqDYi!bw^o`SHkm2*#3 zqvh2M)f{bs%e>KVIK2#~0Vz{=L@%=5v=e+9eve|hiKX9mocZ+^n?R6bNra)p!%JNs zoqIAb7Rg&|cE*_!uEW0NFt5Kq^Z$CnzshHv|GfqRMxkg*U{cf)Q?}b2@CS6-vdq6& z=xkl-t8l33nsGfkjE{w8KNKJqvu|&)F$z8v(bbUc=in+79-?8!5+NB+EiGQ3Kl8%% z+Jn;P*33+C-K5@;p7X9*$Fs!5yKLCmseo@1skc6Vf*eRgQ6na{8E!~G?XYdc-$tk* zQ^Dnztum0I_qM;M^irL>C!!M32d&3+5b*uDWN<8s&fiJR7HyIr`!*>+`im_y&CNeo zV3TP2^s4|gfk3uP#pf?AhIaM>`b-gWQMh^b1~u3tn~K2CLW<5Ohq8oxY{4zAsUO$^ zQD0D`Ns7_}G%|Mqkj4@*UUK+3mVf9-dX%nIt$Oq_7oe}x(UQq@^VCj>me&w>>K(cCi1$iK zqU_%eaF4I`?!K1=eu?}jfd)qPdh<>%*h z4Bb&fIR>~%R7-S&-Wx9yT)VMPd>axBUNRbbjQ$R#DP`brbcqdtvip!SFHhXq^O?Wc zsMbaxEnu1i9_6dWf`nu|;my}RJEZCA*er6+W61)wf3bZn8*EcYw%f7{32@lBp)g`l zk0Z5g>im1W-JhdQL&3ojdf2SikRgfV9-RLD$ylubBT#V;rVD}(TtIKuEP)b{k|YB# za&en~idoO&s`*Df(`Z_2iJ{Bl*z~3VeGUj@$8Ef!`g8v>7zB4%F+RoRvD_8N7GwPN z8<$J}Ome@GDe(k$p#oK}@DhHUP8EqfD(q8C~h@o=H9(^bG$r zC$*UjAq6jZV})Q(x_xEu4F9x|5Iavz)~}4d@)PciBPtz@Gh*DiXh~gJXuAs!s}+4fgOz zcitZOxwW8F<~wAigD%D{6a$=DAPAq1>X6~1pgQcU=&BVFDtXf__1f&AZy%?E^p?&# z?-cO+GGDdn02IhrW`1pI0{9fZz0QK3*x=wGYm!KPo@1b=?jyw(wvX-y&seayA5iE- zZIaR=G8V+Ot+^4w-Z5~pNWLq_MSRPkINjYt;VFLe4qIvy;KJXby3p#%-~qJb3quJx zr1Frkl-5V`jR|K=uG>CLx+9+=>1R5D6@|+JCVY%pZQw-OKPam&_hPs4^ShLu81*#1HEL5+n^6 zTND&At{oPO!^VXLS7t1olo|F*clMa!D-x`qmOks}79?+>sC+4~=h~h&DS{69g{@BQ z&_&2U(SuE>c{C+_>-hTpjJCF5j6XJ}B0-6x+k%{yW+`N-IMKmNOK{A0^D* z7C&9n6T-g@_=~OjcXeOm0ch@!dk-CjCEwjnMV(~HI>1D!IC9U_ZvTGrqh@c;QUA@6 zKVDwGK4at1-o1J8^^xU##V?>AB6-NiWe(0y!h$veyh9}{c|Sg@Ha#<&#Qzk>QLD&) z@E90Vk2l6CmE`JGY~CpWiQTkOUw2RU5@Qu0gy{q1Kq`WXs^fo!;B0~(@zjenOnt0j zsha0|SvOtiS=Y3r{GV?oazad|_W#z_(4|EXFR(_5P+qSb&90Da<#Hm%C(QlI9q6|# zh7iu#3+#s$?^AhuCs}jt>50eUDG#WM(AB@#!h_FLF@<5FR83|^DLEw7?K!y&SEE=H zC*o@;xZL~l-9d9`dgtC8^t%VibOFuH8idyKRS~yeiB>bCa1tN##@}=JYYigjzWa8@ zX6?*G`~UGb!#U&!3lKTn|j()lVk*FrSCi50HW)|v&zq&Ru_JMri#R0??>IaCASN%!^S{QF~F2NU!6dm zVBSA!*6=^eLj_(>;~n6?B8IC=*Ptm_vJ-#GWiJ^XGWx5uh>yjh?(I*XKEH-cm(TdN zJPO7QWc|ff|1dK1^Xd|I6C4O|MJ9=^gHP|c)Pr0*(R*l;#LCXZfI)xX$T0=B=Hs9W z`|EDaVolLe#~%cWpB&}WWj--&s!N{G&JadLAAg~+W@Eh*OZur3MZHSJ$=a!;q+i{jA7M6Nz1*2OSa&)=%m2l} zN#UzJH(CoTg(FzR+mC1Vb9<9C|J=HJq1%(43{V$a>9SpPYsT$yh8N}H*ps#sbB>w0^*(~F$<kDjU%x$O>bA@JR zc+P^nWRkc@s;f1;XmK~u%Gt}{*F9TFM;sC}#(c6{r8mohAs5P!)fNCTXovNqjawZ@ z91@)?4z(LjPJR4I`7!1^;lM-j`fSAH&_^8D6VUBmX{LBkHOZ(KwPjhOaOmgnc>nl& z8g~c$9}E60@>%A|`{j(LsN9IH0(2S#m8eesY>cZ7%mM>vAg=VG^&Ja)bh{{`?v)Sj z`;hy)->e1TRr3o37>j_*;epVdg2i^{i_-Xub>6T9o*w4E$Gukdd*dU(v{UKA5`+)7 zmk3cH5v&_X9O!lywJ2IgcQ2Jj#|71RtNTRcoBdR`=vde(Y)X>wZg>uw!oFm<7Q^W6 zO$y1oT$xL^Cw&T9F+sW~r8^%?qPp8)%o2c<8x5_K3xhC}9ac0v=`Asl#;4ilZvI>q zQeiI~t3(40U5sh=MYKTM@lCii(N|hzf5H zeIV!27U#0HW~X_DxT}*}UAUVk?C@IR;;afwL8MFla76yRqK0$7RpZs$#}OL9pl!jv zI)>6PyA5gpEj$QGyg(6dV2w9LS5bMy`PDsGVS@#!RI4{Q;ZK^TKOx=xQ=eGutZ(yD zv~ddi-N%5=`gXAK?AeV4hWn|kkF*uD2|$9uns#pN0-ro1iI*A#5>D#%)Sq`uaznn!4v1L|3rpip<~C{_@WXd1&zxnJS=Wb z;FVM<_U*u~g2Dx8lEfq+3-+<>Cf z@#DkyCKnN;9V@*!yOhIv>9-{~fp^Y6!6PUt_l`~I z^w3YUw@5Iy2E`D9P)lhfx;+p_@&{2q3=pMF@BC?Tyfy38+Hj_!2dbfs^x|3An;-7j zYe;|pnUERk4S){GA6rhULyN;=Zi-}v@?AIf7dzN`d{;kVmAfdplPAd~#JkpO>6azza2wSc(WPUG?G2<=RvhSnUClSPD{ zICwlV!5%)S%dTU4=G`(kqjVJP1EF1rQi4Nj##(NKzW+kMW6q3AUqjpu4Wb)%rAoI; zAw|QAbEnkYc5&3dpIZo_Z1;$OI1SakMDURKD~eNIhskM=>s#`#DF5i=$y7J{#$_W` zcIu{R5*=`EMyWBhPjnr)z%cv{Ie$w<-)4O8Q0n(aWEY0Cv`MyFq7|K68AYCz0#e05&IvLu(`YjHgEqt5z#W|@* zDK}35Rhu4QVL&8vitHi+3sgp?Hq3MOJ0#fuw4p;rKzAD&ciIV0mwV2cN`m&>{Liqz zX=cAn{X5LSz;BPVAbl6m_)Puq0l^jj>VZ$DPn5Sc*DyjV2G%6gWaoH}uWOOdyYXzS zn4jadQ?;3sGDL9A2>UblxwkvEq1!_x^MTO8)h;wmDYhq7lD4(o4y^&lkkY$W(+QB* z)BPXUvt9<)I}q>G`mt4)X0A$mviAcjX8u5~u=FdxpyLKevfRJ2wwWqcP2otYKlL38 zD;MnIx%i)sVaZ`ShFiS=Wm1r(gdknI&MD?YuQk)k!I~(9$WG}&` zPEorZhlm^tw-C&wKWy=87Z8EJ&!JvN?M&`v)1?{rX=qB>!mf-eZD8S`MRL)kA)V_C zOuo({ZtQ~jQq04VbMC+E~|kNIk5v-;0hg{8YB zHb=`pa&}1j;bTv9$s|P8g)F=-T5Z*5asQ^@gK0Zr{NrTAhqqN8N#;z1^CWV)UUhr( zeQBdAwhl4P>V?*8Aeut&h~>7 z1n4+TAA&d27EZX2-jBUYX~Vu9@o`u9#$77tGAIM{vM_K6w7;cTQBvvrZ?LU^l(JcQwg)>Go zA`n-lHBEJJaaJff{>|)LGRlf@i|qhR-DVcUmFRaEZli|hX}7wUEHR1KtE+N&3fdmJ z7|V^A9kID)y~4&1x8EBlkDTyjNyF~(z>=(cJ~&=16vK-MeJ$Wy!3uyE-UHptda!sf z(SEbhtE`!$<>V))u6H+o!`oA_nf$AkekS!`H^yn=NzSh_LL)80#PG+pBel*jQpM7} zgtR1t2YSg_8{d{ya`uf)OUy7^pVuRYuQFKm;w$gPKWu~ z?X8N_n9ze8ix7SY3?HQTp*-u>(+7@48tiK|x)pe~_@D77_=x6vI-f5+!Ml!i&reXr zOI&^m-f#!K&^!{mgcbDyDDELOi%j=*C4I~DBi>n=pVRPTb3k^XTICKzIFHr6LYq4IW6*Ystx4m z3k}j0rmWNO@0n2b;pEijNgN^K=;o+EV5bB{07HfCRH^R3PO5dTQ0 zPjVbM`a^D_CqaOS>`=F%;4s|retSh-u2Oh!udbx3EFU!=(BI-Z_oOd22~bmUz-i1QOn1DJg)b(j#-h(e zbEQA3YPDUW#f!?{h)|~k-51(#Aw7|JQ|c@7YR5n*?(le9;&b8I$sPQS0I6Y|KYK%v zmqNgPN0RThjU(X5-(omcQ!u35MMC_&^Hmc0sa}f_=ts+DHEV~yU!x!3;0>9IZ4XA3 zy{QN=O;MC_8hn$yxB6<=|Abta{#Psf4DFfXgLjv7Q^oFuKd#z)e+Hq?8fw$0AwM8y z=0zyTNJGK`fy0%SW;3C#sI66>mGaQ6`0*_Fx?#oOwBmZH!@zdp#giDLq5a7nm{)_F)N*dX_Jp?Ri zcm|JqzBF_Sx8lSbfBKK=*YGl+ik)Nob2fQQy-q95XXq)cVmLE*P*wftG-T zgZLA`AYei>y^xe!{dC#RLykO-^3=2T+VzJBrwcbncMQl8#C1>h@7M((;V)EP3y6_1 zY{-UaxUHu7nMv8`Aue{4KK+t#cg?vynYx4Q1#~n9RHs!0^rL@}Is=59sob>%U z>d!a*!$OL;(BTj32K|6knlREDCBTw^0VS8nU^Na}^Ub=k+Ws=f`#T?^9nMt?e}}_A zAY+BNg28XlQ!14$O7tKaCuH>JYn}-AmA*I~HOU*A%91m}+eoqlIDTH1qDE2^#Wm+* zSRLfdTwkj9gAShD&fo5DQ#NrAJ-*!2dlzY1%wPvhxRPeEVBZ1dWn2P)Ozry?CpnJr z{x<%^c0MmL z@T_~nIjeL_c9+E5ihDnyh{wV1GcqiwLg4+%<4%{scG!i|5d%<_TIccTYrLAvhW*rE zO21=SCyC%K}nN82k zWV_vh>s#o~%DG%j<^E$j1zYucE{^vS_H!@@R)7EU4_u=)u# znaPw@svd1T{K3Pld@XXuKz(7c58Ldq7&Q&po3UF7{TTYxwypFu$^?;sY?nuR68LV= z^rUa)v* z7rWerW(Xpw1g&3irUt*#mPv5T0V3DxW92qb&H*&zW*#$~i(F`>otZg)D34H~A)Sfy z`DU;D_?B-#TYH4$qLvW@thtLmfLi=^g7p)PgUTk}w3^+y^LN>4^-2emfPIF;+3JCE z%51R z8B&cmo&PklXt*>d_P&ht7u$o4Rl-bc58^x%kOTLVgvLPm${}&e45gfgzI zZ7h3mNAA9?_P&)(yvGo<9vjsnK*mtJC~7ebQO`_0yS(S61M+z-4|RN3(#6~}72oBmh-g}FY?}Y$CLMYh^Edf6cpsGlfUIgg{(I4Jc zL;l71Vt0%9E5h+P9B}~BSM~uWoejObL=sKi&!7KVXa_l&)>%siz~PSXtXS} zjZlO^7iGOl@8B#-*8?nqk7-=|j4aa7JMf&jb^(J9W6aXj7Ek)KxDx4i*9|3U14L(k zLCG11_X*VD_H=!(KMz9fl9p&+Y)pJ)PHbK_vzcN=VLj3KsITA}RL5nCarb~SBtm3B ztIs}Y(mvhfo{lLwCHvv+qmkkEzsu;{Q#9kHZBk$a#haQ+;d`4&+qJW}QrT3^v69GZ#B?{6zND)GU zARtH)5Ks^h0RaUgy%Ty=r1wxlf=Gu1Fa%QE?>DpdoV~ww=A4;5bJjY0efwWB!@T5q z-urp(cHP%i2pC2`C6E-dQmux?#B_?03VZuNb2I!ixiuRzoR0neVTK~Y=*w=bU7cg= zY|((FFys)x3A^ye5O$LHjCEtKOI2o$44(W!4GWmj&VtR;n-M66}*3K!L(PG!)a zNzG)@%$*|;D4>#z7~H0rx~oxq!i1Fi#$wtHmCrlT=2NtUF#C+Ri?R7*B z8;e;E7Iyzqdj|945i(9&ZE|L%d|QL;;sE>Bv?M#77z@YBw9dFRrrfQ2dKs;LH$EW@ z%+WSqW@8bZwZ4Z2gmRPkcR+aeHLTk6c7ENM(44@P1~;a9wA>VltpQP1FLo z@47a8*~d%v!}QX8AAw&Wk$lr%aF@ZOwf==@qRVQe3qVllAAkn;!bGS^p%6h&%^!wQ z1jf6u6NXVMFq94YZKM>i}JHRc{clG6zd9 zmK!FXDp$?!mc1e=yWe^SqXm8c3j92@pDrC8FhAlnqwNPAfuDeaIK|2*$hFE*H&NxM z&8ZyyqCwB1pKJ$iwdT4FHZ-PMj|mzR<=%8BCCHob+MHNi&yG2ow%Px5yC@f4cgK+Y z0JbD_=BVERzSFGjRJDlNJZ~19E)r;>cpI~Q;kF|@^af&UY2@z2AyrfE@(;AS>~e~} z2-ACmnu@M_9oN$)pD2SfK>(}_`@4Xw0h`M!p~!$|*GF7&EDSLZ?G}DQr#aJp)Lje} zrMvJ1F%2fkO#M27)T}+14^6FvhkV(nRi}@Wv2(1Cfi*~$0QihpMap@6Ke89W2@RdB zc4?pf!=`^Ys3A(PQpHzMMP^+wA%T2cEMfRB?O@0|2L!h2YTP5#I5l1#*- zdo`s#0`oC4$57zmO%z4^NG}GR9cs>EXIPHHEsA3vw5DBb5F(W22|i{S<>&mYs#zmd zseBq-0-1yNF0td+w#j(fOjqM|+l~9{k*%llB*QJ^-CA)9XsA-$Oboy2&#V5Q?uj^8ILiXrRk8$zK}cs^29Py z&VZLB5{d6DC{eB&YBvm(w*5BWx;7}~h4^MZt4Ay&`H-a|*6avJDeYIE;!MqmlXi38 zePn?N1=m(fh5{3;p>yoB>hu<*X8=jMs0)z}XNH>K>+DFbpG^2_e8e40gLG=hI_TJk z?@qO`31e$zP{`#Jn)r+?*sH*&H!Q1l!@l!b(4~b7Zek{OF4vSId6&rWC1uuq4${?9 zwoq~y>Bsn#-k^*Z6HgjTLux1Erp!qr-aW27BA{2uJ?oJhTXL@-S9_p=gwtk>7*FKX z6RAo{3ve&lP%dHt?)nDIJe1kJRT*8F;riK;`sS(L&W`fB`;BIFze`Fc5|u;ln>l>B zB2%qrO?}spdh1Er$;n#J!QDaW1YnB0|tRN@v=UQld$kNM` z_P*X+HsZKto#) zYtBkC=$6aF^(^h~`}*hMHgVS_GmWU`Qs*?U2=E@819!nY5(_p;lpbiA)t`+kN4Zs* z!>Jjc+NF7%B*%G*lBmlFI1vFz!2?0P?vYMh@xKrv{;U&cW zuKMUjTwjK<>E@;CVEtmUJcg(B89zF22m$(j(tdsQQy_qf8{xkeW zWX;GHprUoz#}4UIl$h?tk=3ZR8bsaT+jn#SOZUtr23(LH2R?U*OocZwlLByxu3x91 zrWN_`-*Jm54a&SfT;NHj)xba$E|MNTZxn?m_e6#z*7JG!?Tp@C2)_GfDKc_8_sCK) zCHnWsY7tNaP)4AOXy;gcwZj8vg#3{>ojWwFn{WLzv08SlJ8Le34}7E#wlFT6GJ44;Jq0d1Ao72TlFW^@t@XF}ZOH(5xs#3M+}5U`RW6e+48+2`1&@I!t=SI0{KARb>>KJhGYM+i z+kp^3T{KQSsE6Y@QPB%|zEk!E&RmJ=mlC3=-w-Y7B_f@5bVI6vE?r~-sM(~!0upl} zlbv!td_cR;?Y?qu&=u9e;DtZm-lZI2^0wfQ($g_QFi~j8H1g43I`pkwQ&*eul1x+n z2XB97ny_9)4jzDhXN!RgRW&47tANfOv_`E5l7wsk#F(@I?qfC|+~tO1&rYGJww%o2 z-#13l17rF;=M9lA{s#uTS|IyB0qFZQW~?7s87kXKeUJ1A5b+^)D&Vg;8SI;UF3Z{p z9Ke=k{nGEfaNJn%ZS&mMHD#XYfa;AC1qu&0k$pnj1hL8Od1TWXwX~p;|A^mWqN()9 z=A!Gtd3=;jKLl?InME!Cr5gx%76>&bKwJClJ35;}1o-SzrUP5&Uo^S_Y1^M+Px^I^ zB%!rbICiUunZnH80-!&ci22xKf7e>B#-GN15t0XIVZj5+8opHY@gD7*HcW{$Pn;t~ z;Z3@hsxaClQ43 zXa2~V-7hCPBfG=jB`vzLjohGtcXn6Qd06xSUy!MZNNI55Sm7cKI<`;k`nDU%#V(pn zFcol8dh!QdgSOR=eJX%Eq(1;4;x>6vni5BbbzNgT^}2Kc0Lzq9OvyU1 z?j=@&dwO`0AgSDVynbFLM>tPoSGIR3h;|}g1Jr25Wcq2GfNQu4-3aGFmWN>1CX!!E^LDwSI-U`^48sYKpF|Pm|Da z+!sVXR@8De@4>6eOPrGKE=kg7g#{>?7p$-e5$R}_`=kkSC~P)wW;+Yp;YCpb=Fs*E zoK4&>jEFqao|F7bSC}?TbF?UW6}w;i| z2&X83`F9@s@4A}*<(Y8){Q^P%%zy;Wfsn2$^rrK}fck|pTvS`dmtgDDloR$w>@#ybiuS)xwhKFQi0bJb}0Ul^2mX?j>Zs{J`u;KuruKNNzLK={Gxo| zQUu~3$lM_D+f=(00c0*FkDp0szaeyjz5xh=A14oOBEeY~bOLSRPiA(~+E&0M$$@-) z9^@rD;JLO+wbyhy&)I@DTBHaS+2j*Wf@`K=@kC6IuWx_sT?@~r}I+&Q|-!bbY(m; zw}{xt47NXK_!&5l(qK#uDmFTamglKLYWmUI*lfSGWkn+93@#{9b z4>344U6A_WLPr~*{Vp_Pnlcokkl1irU(~jtK8}~t1UyR_rc7d4hU{EtOzxE2Oe*mV zKe5`0TQsT~>zB-zyfsgMUP(-8?*>q3ZDKFNV$cUfIl|c*yqZPafXT-N{R(tr;ee}T zjx3Zk#sB+2yD{KZ%FM3-3U?H79go_sh9jWbq;e0%2$MdWtKr0XPqbZCfP}eR%BwVI zHT`?@XaBf~sG8B~5~*JSFI53P6^e{m636Fu1)NuV0X4@NrM+Xwi(YIGo1Qsm{q&_H z>b&G-s~d|4*VMaIupqoX__=-RNQ$-(VPHoH5G@^gVsa}a$-Ox=FBrU)*B3`)ynTa~ z&OGx&W^?+|FKsr-*U1wHBc| zg{B@S%$T3i?-*+6XuofKe&n*p0rUOrUuX96PJmos3H~fo z?5Ipy3>YkFHbJ~eKyn!!ftdw*E&Ir;Efbd*X{QwPUR#_PlcNXA^#MSS6>XfH={f%C zp~q2+7=#8+rg#7kmeS-%>(oq5{JA8?06OyjFmg~y|9fN}g2ezQz#Tacen22rK0M;H zIoT%_88yG+JcEudb$oM_wsGNlGr2cz!Gow^0z9XW_M?vEGGRT1o!$w3>T)((Q|qFP z{sr=nOG`D^Xd8=vfO$uG+Bld`1p{QK#PW$RFpy`Hb%wW(M~PQh)+yPI({)OwS5j)z zoEE?Koe}jp$-wh>n@aQ`=?>Fl(9~ar7bdEdpOu;i1?oOsnX8kGX6Ij*Zsne&8ES)9 zQay+^q+)_iPu^YgAi1RiptABbIxSB$_xkq_qejx1QNWh4S2bO{2Jh(zE49vx&01a zU+4l;p^C!0FL#O{o*^HbO4#RJ6kSU}?5TKhgot7NIB0s$K_p&=lEdM4Ffq#{3G6YF zblrZ|_>;L*VuOl_XKu*PA>ZW-^p)>RjurkPSmOyy96^H{Nd?g*aNk)LV_$`0wp!2X zT``^gK66UFWl7qx%o4JsD5*$j2kr@;L#;g5Ju}unobHN!Ti8SWog5W?W5MqGbt~Jq zHLJ^K8U84rA{_vZ%iT{KHhI$A;_IlEfMB4Xq<+AJ)3owv?|0|@>W9rvmw-k`83{XN zi3OeVoulOzzuINem&eD354;`v92 zrU}?bDdz~sP8&fhus473vg3(LYKwj5$f7yv3eZ=MCf|k)MOxP^lP`t>ropJkOMPwe z?6;#s{S8NlVxV#!xCw4AnMSI^m$Q+Lpcg<1cgu{L3$^h)vS&a=G&7x;5XmQQ-{0ki9SuXHS*<7>svI8I|dN7|F{Z=Nm1m>n@h?s zac()qAs5q344KvgOS2897I?g6yfR_Yc23{4b1b!NzLCEhu=@@QP z=DJjM@}?;kE%=7lSkyJsCa_&~Nohjm7)$1a4HjxpYjrh@2^_eaEuHv|?9EO4-zC8U z)K2$k;OyJ%j$i9_-TfFD^dQM&i;==7zBD{Sv>dO#IPtRoY}?~k-$BeijaP4cJ9PU2 z6K~I_F_k|m*@Q56N_H#D5XV0E3V&k~U*9y5vatMmsoS70GpuXpR| zbJBNoZ&5qy36(GuoKJ4hcmL41e1sY#eiz==xI#dn(n;dhO|D)92OM9#Y@7cd(aUJt zEYMTG-&(`)o%f$^*YyFmQ37Fs8j}@h)71n$?B@|IS%KHXcH+xUV$Ow*S3Di5!c*^Z zA4VCcw?Q5P=RknQhH(U^B0Z5@x5fu6)QHvvL5i!tv?yEOtwtO>`&~ELjHT8%cGeFT zXiMPpx0laq4rQ{!L;aQ?Q0WjG>BKkGcTWocswGWoQ?!m^gIv|`>i*X{tBN9?{! zTVE(yDM;~D2ERkZfI+&-@NU&k6;fO`(553V%nom`SC^VxOmYX5V8e4l9#(3FG!U_q zJHD-__L`K;?6zB>sRhuG=H+-QhNKqbz^5PI& zj-;js6LQm9sb;2qtZsFATpZ6 z{QC9Wo!lm_s*sUq16>cKS4a;UpCW+aK5qo+G9iG5?W-m+R0RFHDbC*-9DbFdN0481Hu6Dc zIxr$?NMmkU0i#2(5>PvQdAck`ckgMCOJkP9-M$w=&FwYK1KVk*8=_AETg+fZYM|x^ zg@+QP?zXlz#iP}^rg5gbCF0k1w^C=f(x_J?_W?GCfc`~?<-Hx95d6zNbk@cRBsm2Q zB?e@1PRSXc|4Y|Q(exlS-$!=>QD$uKIs|kWz!PDEvq@+uFay)g&p%~tRQ%2wCKUV4 z;b-m-X?SE?mIPdCT!?VMq+4#Ms5DO^POE}O(pT7;~A z>n}CU-08~F=02bwX8esB04EC-?QD=;z3dT*Pmb&7O}&5jnoKOe4#;5v=w@;sxeePb zew|&be!!fAI`ktyprKCqcMS1aH%JauTLh3flH|K1>Y0+V`5VV3x2F2%V5Fq z-n2td5lwz-1d>I{qaUd|~ntWF<>%!d#KC*iIwP>mpkm+uKWxk;uyeSEX%5zeN$ zg72OBZdxY^pgZI>8uLxE$QH9&BGTt6)c%#7SuXMGM%Wl%=8Z28gS1PR>>MTn9hZZc{meMWQ)OT*FJfat2EZ%Nx(M`xVWFD__ysa&}8)-Sk)sNLNV(ApgQ- zd+#Mlyg|C^+shwwf^6-s9X#HbvyxB<+}fA=COEt1jc@-0o`%JjIjq}XN=Wi9zBsXi zYtk1zJy6WJUyZ)Q)WhX(8Ya8R$A>P9pU#bJ+u0M3cno>)iucj65KTu{G9mzHNa5Zh zHs-AK>`5v`_#ZBAaR1=QhJPG+2h{nZ?G;_JsPE0o9;c4Xne35dN4EF)WBILW##AaP zX4CV?I(w#Ro)*-Cnwb0ITiOMsv^gBI2!UoW}nyE4(7{LgfOnJHcHhI@Cq0vv9R723ahOrU(KHF=JM*dU9ufq&y zAob=H-V&^HdI@?1UZ;?-6Z)APCx!NJ@YC)NphFGTDrA?sLG;&b%ZPW#hC>*~hbYrsIg*!n2QlAn$a0}yYdfT3X=9RaY&>JOA#a}K{w~I1-VZ5YEz-?+m z;$JCxUR3{rTB@z#CfUmP;&N>Ve;ahxuffFX!Tv{qE{;`+FA=`AV>36>d%i@Yun3Yg zWZR~KbQxtu$W8oR3kFm`wlw#4oZzkr*K}skh?t6XS-x^F*@u5L2QutU`;Ib8zAF6B|b9D zfi}VN_aRAAYdfwU1f}jq(r7~24%5-}F=4I&o)u1DL<*=kg>sz9cgp&sB2uU_~ zdnS50eFwp{kvIGnr~YW+H*I*>sv)%6|H3(rLKsbN?2MV-F;hN8Cq(oy)#mZlZv^bBsrywNs(SOWs$z!E2p z)jUnE^dE>>VPJ|alq|)vcbYV4lIwt%M}!cY94vL`JOaOQ{(7Nd73yZS5TE<;CZYlE z1F$ay^p5ZXu_6pa8zBlkM7A31YjH`vM7W zwnoNiQ~uHw-C;63oWXy=Z-QCdB`Rtb{GYsJ4%zBt08b+eAtbpXAQQnxMx1{y7EX~U z1%J_yAlvWhvB^>W~CX2?s7heURDp0bZ-&)fz z+A!inVUVnyyk5xqatgO_4~AvO?n0I=zPg>S_Sz3rg>BKI##%Z0qHsqN0tjMeF~r11 zYBEhBBCZ>#v7B#;jQ&NK^R8KNFgQue)@gA&aA5~WAk}_8>vZeANFym7ekR5O_E$t3 z)IB$`Q$pg$ifW-wR=+Ln4?QBvXj!DGwP(m?g2AEuA|lNQU^*(+9~wdcU>AZ|3^(N_ zVJ+qm!d_P0V{f||X_ZvR?=?8cKRi4vuJx3yNeUDpBo15{6rSXWCkmu1m)oi!J>w4j zs)@nh)D=X+zIp(*ir5^y-A0C`K7!Ymqy2DMj1>#-SN?ojH$;PhSf3=@Uh|!7=T#BM z#vfn*$8{4n5rO%ZOiR+%@Ce6Y=1_Mhwga2&N8&FeE6o}Qx$wZME$tU*_V9=1X|OZY z9Jm)V)QJ$bw7WE*CA=u@9;={gVv;18E=!1Oj^Cei@Hf|yIT-*NG+JFqeu{+0N>KuO zsQHjm?s!tcm2A3(q+YUaCBeo`3Z3SUFG!0IUo0us8_;dkM z8$jVr$6hM$Enw_Ig5sy+zO3VWU7GL?9sOl}*DH)x;R*`E522W=A|5IPU{E5RxC)fs zy$Zt3Napyrg%aJ&iSDk!w8jBN0d5{pfy(g9mdl_6su|l^zFaa<1yuZyeXi&n{=P~OS zHen(Ab$UY^rC*3{^!KWMK{f;i-?pDB-vhS6L_A!O183@IBUUZBZ1X3^z(AVz z<1$DXoPkVr79k+FFOfsk()dlhs$?5lLWe}(@x+qNTEi5$fb^0}GLBYK zJrF%bFZkK;xil6=te-#SSXEc0CYd+8+0wsywFyO~q#CZ=cmf8B_MYIgOVFDn;S~&n z*RfjU(o47xljz;dTiuLn$&_B;aBD*y$L6u%7qBxvnW*xJtR8gLL0Kv4@&3)A)HNU1 zH>)<*qRsD1_7u?c#6FS)S=02R7f>Dzy`1xx?!jwG>qeioVU2jTwRQ2jrM-gus{GgcQy(y>Pq-McYkg5NnElTP^UakZnLcYZp))^E zV-@(GTo;)2AKpF*L-d0aI^`Rwl|WkYnUi8piVzB5ji5Kn6b!I}hb!u_PH%?8Cyb@E zLMEje7#99;%muxVqn#@w>-B6iWP1I2KLRNnN`=M4W^?w!$ubn%#uul@Ndfnr;aiIp zS3v^sZWXR*2#tAFH<$6G2dd})hIW{G5%k##M3V6D@OVm=-LyA+_rXu8FFd0*Q&D^U z{i~q8Jo@5qP@i@ntN^MUWIX(y`rKzv&|~c*&p!+x5)oZVzS9kGpU5b5IUIj=X`YZs zH7u#@1P#UCVNcvK7G$tlNu+SSeXKdNBj_n2Q~pwbe%)@@0DkAa5>Q{^J7CpdQFrqM5MwAelNme+jn1bqjPu!itHP7MssLu)#;iDQUFqL`e zRcajE9r+T>atHzeK;4m-ZW9Vm=Dh@Ne)%|Pv!D1@&@y%PweM$%=mnRUg_XZ_Zs~EL z+T9|u3kQ3I)<7hxf5^NW{kSRYC@;IKrG9+Z^|geoe{#j%$fyvCbd|u;3#nV9@Q_zH z5@=TzQiZ@`s>)k~ajRV;frN!yEJd%GPhBbh_-B4P)_j&DsYtk!2P%gL>XXToP@Io2 zo8~m1`=X+fad(gS)rIXv9`=Ug`@mi3GFjE&#JD0~>n@c7Zu<5bkov<|Dp3o|Q-6aZGHd%k1pV>4c=?`4OQ*{d8Qg{tw56^5eRpN20l z1WkoJsGhVx)H08Q;|&n;g`6{zQ@U~yIdCC#0U%Eq{|8$5d84IUKkUck*5;}QtFHSmyPQqmKE z95!hu_H}la?t{$A&HL)Wz*nc}SK#1W>GnH4sL=Ot=9B>`H6xSp(ZcFfg=r|eHLQd- z2(JbH0_+~Z0Dt7EI%-l45j{yO7KyT7oh*p)c$LiYL#C8k0{1}B!zRG2DjW%7nl{NS z33k?x&jmWzu6+1cqMK*k%WGZ_5+fDJh_)r9lUy~fz9D(~RHOQNar)uYDePW6nw~C&Qn8P@48^nE9=+;r zjn$FaN8rE|E+PZb4A@*ByMbIb$@4m=#!%?;mV);#!8=xFQt>OlsrRsT9AMwiJ^x2Mprfh&J(@xuofx;x1(oGc*k@z zZG8VhQw%Q{MRZHWY_##7WMdI55#imfqU8zgQXl7miKrBpD{|GYwl1kW56|ceyyqOV ziKC5T>M*@~==<1(zjSP!61_6E#>(NG=DywXa=%k32<}(2>XK>#7v7CpMoL{0l?~+i!YRajFx(XDF4pPCTr84YX z=u_4sqR`VMKlg%8$|pexKztjvgzD+Qx*C$QUO1N(6T+o;jW%bMl6c((7M>r;fyL<@;SMEsdjpF$xzbv@T~1y6!ni)U=1;# z3qB{aY`DGZ569Y){AHYO-JX*#0q-FmizQh9;&AJameUJosDg43LTJoL@^z>S!MScF z{rvh2U*0rQJDfkuenI=uFY|UQ@bm8!{m7YF*eSeJJWMb`&jc?Ot4uoV;4plC(=PyY z+hX^rssO`5Mo} zykH0Bqa^=^BmOvw6cCi1A~_i2ZQ}i`QAT5OF7@@#G!0p$IT?RxPR6GdCZ7ZAc1ps# zm5^@mr&Fk~8D}>>PN;s*<$5MZS%f?J2%Jz<+tj1*9Kx)Eh^3vXDKZ~b zA?;ccQg-Bie%w{!NqGz-t3&QE*Q|l-FxzZoUDyyzu?R3AcHg~uhrGERKA-tI_2jG9 z+r|AX4*W#k&7gnMU%mfL`ySIV7z^IE1ElSR0SGTat-Dju0vBz7!!2VRjSiGAV_$0a zq=gx1NUYxT*#L7z`1H~gM)$OpaMh|9oAFR4v`oH3#k8keYU}5cSf=+}HF$+I@Nzb$ zraWbhY}FL+4^>eLHp_}uz5?HQ_t6$bIinwy-VK`VB?eN9oVE56#n>AYty9jc$kYZX zbow{vIrZx%)dSX2@gX)nohC=?h1Vfa3Q1lB2+k}{zOwqI?e=W+N2BE@FSS?(o}b{xELSp&kpGA9h*X;gZqXP^~oJK}(ZNf&+nngZ{)9s${m8&n%ow-wMnL`Ycyk05! zDkJ8TVkAH!2fS2<1L~U+QU_>&Y|6De(>LZVVRfHv`?J6N)Y0C4B+!}27i%z*jW!`D zbfG=^icW2H(oahyo0tZVJJ@NjKmW#e&nB#Q@=LJJ7S>0Bbctiz^=uY1HzkPW_!DHS)M+^(B;^n85CGGFD?WF0YB%?rKw!Bh#RuOMPjC*vbR&jZ@lD zlkq7S;P=!rZd1udi?iMker-h+Evm9_!mi-&hUWcR^Vj3IHtiIRyElO8EoVM_QzC^E zyQtNp%Tx36?%3fQF7!B>cV6VW!L?-I1*dESA#nku?hf>BJE{A#7r%XOvb+jn=i9E> zzGq1+*6qN;QsC`<7bN(a%26~OFuzei0dlKis52=P$C2QC*^AqRz+0M=%f{lDVQID* z?K24WNT1VNMr}`h_*jHr(NELS$L)U!y_&E!m{EYyE_}PK{>iLowdFHeA2x&m+?p4L zp?evU)VTlM%_Cg&my!cGTU&A9Tmd4X%gv>F+hJ0)H;(#g zwj`ODUj38lv9JsK*rp&HVb+V%JwFZQ|K#XsZ?~0`Wj7>O`jL5D<8{fKU(QxvBS$Uv zkzGZz+(cJuQD}YuFG;G`JQOE<%U;ynvS9a%xNI47it6l&ma*Ui#yqmv?(odL`n(?E zrNSkwkcLE1cIcy6rbF=+1drdl4oq;{Z7#J~SVP7wlp+B{4Is)`2& z`WU^IPLra_^h-SRTo@9TI0wvShs}TPqHo{FE5@_80OxX%n)hcU)sHY$t->M~ z+Hj>I`i=k=CDAusXF+$e77d-}#qLo`qadl8#m}KFin;&4PC&+LAc%ry0|+ z9?y5`D}QPDTB3J+Jwmmj+c>lTjNMDW3jR2 z=FG*Ie6h#A_x4lkA4l1Q;-i+!dyAflaqBXXoIZ+57$|)YmisyWlh0U}aMs#IDLH(+ zZ{DFWyTWT)s5<4uztT^1wfYB7j^Ha}p5#Tnl0d^6L_)hUunFVTREi0%1~;F63gxQG z6lHRCwXx>ayM4d0So#sX-^Vw$N61)69i$sFw_@5l0plXMvkC7YI&r@BGh8QU^DIZ| z;pf&)cWfr?GTX}ZcV35$z|Ycjy(~7sd=xn^9MjI!G_#v!6CcgvKF_+<1l~I{J@X%P z3k)BrsZf>A`c-NPd!b?Rl)eNS&F=kQy3i6~Jq7X{!V4fcVyFEC@z+PI=@ZOj<>Wq$ z88U*bum09*Fmt75cy|r>ej9VrK6U!@1Iyyk4$miGBH4DjN)E11^_*WX(~p7OBBc zscUR=W>m2~cynSfy5aRNPLb+W585e6us*9bLGt_sqm@%uH-G^JI-WBri%~bnwJkni zB0~C9GcX%@?-U&Xm4~*HoU5m748&5{px2jyc3%L%m7*Z%K$^deAL^UQ388*q^8fOy zxhd^NaC0hI;i0L0*ra8mV$BKN*|UtNTSj;R;#!zGo_h400{PhedHv+I0pL8}^t~Ds z4rNVvUw4oXBs3!gETt)1)@aAB@SDrnx7%Mc5h( z{!nc9tvWX&g9i~G17I!Hjn;%*e4L)~i{B}m`mW>9aQr`J z4tcb-g0P?$k)q`1ty9JAAF*0k|-{VBg?xn{Is z<f=Cf_~V$0%zE~bT=sCW#5{*D-4{dhu#ZCq z?<|!ExT+HC!RI`4oQ3gIDfaHU<+r~&INT@}PgYs4D0z>_hJj(d;8S2Pu*ilOm{js8 zJfvbnwP(Vw;d@gWjyHI{c1JjEeCWt7a?-I4WVa#YTvY63ZGSn7si}4Xo3_N1`$7NQ zbA8Zm%o%7F*@V`MVE}uldKeI-`YQIYll8W=5fLK)Y3@s%`@gT!OT?;ikFY8}t-Nv) z*A3$wh0y(E*D0xxGa!PzgL=A^`Ze-t+qq0bBH|wwV1!=9iLR z+f(8)0o`|IBj2R;0mExMa#4JB1gYMitqa#*8CZy8@P|V zbwzP01ZM3YBA*r2L;9k*apkF*w0ZmS=bVE?jZF2ui%r1< zl%}TI-HdE>P=EAi*6ZC|H_xLpDy-u)Y3mcjm-aCaM!S;y zpBz8uGWTnH+VtkN-}iSr+KRt+9%Vu7*3qU3&r0n)?H{-Z>u56VyiXC?PUdBb!_(bk z>;;#R^J-*GV$y^@upblP#xpgg2yX)H4aF~&3bfw%m-K+R; z3TH0Sd$fVConX*{h{$23R-EAPsLOGEFHAj^;xXI20^NHH42PS@)g-^gK3G;p@Q{pdiVa@8sD zCgP_ln8x&-tn5I_bh1B!5ZHca?hc8)^GHy>fqJeatLw!wQ4w(8QfVC`4A`0~_%YBv zrD!yf0zO7qXsfVQRVqg&ybG!bu&6)I`XTA1#@==?YBLEx1LGi>FPry9OJD zKW%ZKA0N0~HdNG*i{IQfztia_dn@(r{!u(~xd2oLtVXpQRm3K0Khbx!!lbfFoM1oZ z{-(~Tm^G^Lx@$M=&r!eW;nxpU^V%#xy>NRTUqZ~mM@FdO3Sav#$C_)RfAjBusdm$G z7G%5&l#o{)npN;&aey22q2|_iSSU33+4KqZ*NRZ{94bDfcD((N1lfON_B#PFz(JDq z*dAN?tf$sHyW7t4X*YeXF?(0;Eq~%!W|N0scdIlI69|@dK3yLCQZ_dFn#+VyL&ErZ z_}aTGobVgcH!z5AdnD4J|lXU>l2b( zRzbfrG6yEcje)%&v90`l)#_C?69yM1tDk*u>P%0vSx5bb5RDM|G!0<06?M-6R{Lk9 zUzEdo3d)FcIA)!>zrHUmIo@QadhOV$wdR(h=Oum^3y`yRo}yeO+!fO%oEa`7F!tqq zkxbZge0{g3mO9OOsy>^>HHT<`U7}patMvmtjZHB+Qc{`W=k?Z1-yFfSOcJ}T*N!u0 zK7IXlj}I&ZjNZhmQm&iKzw}eUc_hg~b+l7f%cqXpN3QHgiJvP^*Jo^7peI9B z5b_M|8~`7d>Kz0pfH?e|F?zL%npMMY;ZM`nJVGXGR0u$SH1-jNZh`_U)WR2j#&NJp zKvHk{shLl*hFSiQJfNHX_LDmtpU?%mf_pZvw*lq{NDEj2CYr$>a6Mmr6BwTrp~xTm zQ?mJ4?^&kDj{cX_8Zr4DE)+xRYbZBCiuerAzr$PUt(KFw7n4zvuq6I*X;n8k*0lSL zuRQ9PgvRe@MGt0vAnW$FiiEJU{O$8LL^vOIxu69;DV(tHN?9Ip!C-X5-g_g>Lp zq^>YNpNA(p8_z-nQX{hR?1BSS3QwwOZNHbRR`+dUarjd({WogeT%ZgKF^!r+I|G|! z@d_m<8Nc?PW*VE{RJF{HDm8=M>QZcdyvF`9M%NdgPT?{n-pB8joGtkxUxN$spU-5w zb#w$WFv`?MG(`L1!9)j=4q3~4>CzO8$19+uJlR=LzWR9;{$gTSH<#K1==#c1tS`(O zHdZJNjGbVq_3eUWWs;R!8{X!b0^8mTfV|dr{@{X6P5J^AGCQ-|&{3}%Xz1e`tN!TT zi}w$uE4og{zEu8~CgS@4sRAvDn|4kGPY(zK@RPw(u`mJIaG{36&wen!(u_y^oPC)k zSHg~O3irxKU!eyE8e<3UcKPV5+WO%!L85Z9U^>f?GZrN z5FC5Y;^u!>;rll-vVYLq6UtJiO?w=O;QE?Zg z{+{t)YO)LT_y1Wo_xzKxf9-?tKV2XHyB>0mzyBng`=8u>{^yhTPY3b;eEnZQCeZ)0 zy4wGF$N%N*i2k2hTmLoQ@p+N)(f=VR{5N67|JUI0f7icb{O9rNe~q{NFSW{lhrjxd zUA@3=McKmgxr!NlRwH*u$C;4HiVuz#gD*{n6pUq~D$5HD7H=-VrTbm9a<>Oktw;a3 z=zb_u`?{im`#k@i=z9jISa+FS`gY41wMNF3TVKR}dUnJdm8rc-JB)S_C;CDf3}c_- z;#-n(BM(cqI62%0SZ0k;k!;%%TEo(?`o!(o*b}xES+J&6M|{$8;+o0U6`g#sTnpW> zcPry1KI@#s>%WVpUv=bj`OKEw=!y+i|Co9QLrS}vuu!o5izrntZ@w|rIgxYm z4Gy<+)L*7AiJY5q;p_S3Ucfv1_XOlvmu8$SSVT%Li>4A0+JCa`b zAtORROIg&|%=$|#ZnRtcNw)4lZLc=Okxk5pbtlB&OT64$LXMtpQO((gmX0pPI4}9) z?ebZ#=_l`bJ7)wrMiUs7RhvpGe(x)g*B?ZOr7f%wEw?YsCNuEo;c4x3mUgPNAAA#cb#CzBJ zR>FU@T<(N(nuP|5B+cuMmZ_Yx@f_3TW}P28?C%({e+yN$N^)qVr=sT`$`OB3kw?a9 zaT4+atx}^qf)$C0{@`RPP)6rPOkxhWcc96pSgqbytyRy=$>PA^B~wVPz^_U73nxLg zgLIgAnfWjM724N`_+#TJDba63_O$Ncvs)<1@UBX`D2Q)Sz%Qd#*~)@k^O1^*`CA#! zK;CXA=X8q|)<8{=A65bEPG{M8w;scvdK=)WlSNw!%;4Q=_}u>d8`xr)41h*b2o7mI z%$Q%TWK3|kI+h=fzB5KGQ1~q~kNP@M?ES4dmT+_L)zeCFjf&a;x&MAzv6AsaX}{p; zPun*^@q1i)GTvvt|1qa^=+v_r&(cR08-57(2FOg-7Ia#-LHN|gwZL}J(U2OAa}clV z&_B`&|Fa3NbEEV}MGyfhibca8Za)38@HyNE2n$AF$_;t^Y?H6Smib6({!1UK*G6s{ zn4-War(!)GOYEcw*PPB8oF}_ljjvng_SldXfez*yVEzZe`;(M=XR^MHx8-TvwMPlg z1I^{nEA=%XdY)6y>uWaAQChR}^@$;GCbKq!Y(8%k<0XEclezI9>%;z+{u@GM@`(?U zJ0i_J{r>$kZO@3oPka9KL#G4ogcb{34{Ot56`7R$HFc<&^WUg@>#(TaZhag@1w}wa zIz|Oa0g;j%krol@W>mUGLUKkxx&$NyVWbfRq$P(&32BCop`~VsVPL}F{=6ry-*wI> z-V^V2-tT|1_iUdX_p{b|?&n@>p*a)QE^;~0$6R3p!~>$}z55HzF{Rs(DE&%5N0|ya z{mCPo@6woTq9o@Os@NRZ%o*>9e9-igCZ;rgq=C~wWAmj#mFN&bYFOD!gga$1q>c9) z4$6Yl<*~JAz5n>W?Ke~R-c6y&K-)knsznQ7IqpY>BD;%#^nK}Kl@6-*_BI=_a501x;lqVJz^&3(orNc9YJj5V@7}2{;HAm zG=vLXN=X9QSL{yjFP#z&ZGt(vi=k4d(JUvqWG%PqSl3Ju<#TM z*dD;&R-aUUq&}6mWozs3mO5T2csk~aE&uk?j#x6)_0Y`Daxf*|0 z`Kf#Fx55N7nDy|(PU3S_2tgp8LgU)=wXwdN?5VdE-AbL+7HKakc^xJMj2c1b4wE*@s(9w|39H6z<)vX{_P-SbuN=4PZFS{e zUAo=AVc%RO^5s!}vy`p`F|oG${h7l#l{5=lDetydz9sSIqgP2k9&NvWEWc4jl_Roa zAug(2U7+SN&WEV73VpA=4E*-8g|@bxX!M&|S=S<j;w$J&2h&1*nEvsuklGWT$^KawFhq`~Ku;JZy=jN2f7e+Qdl3L1IVv#*LJxEt<|Stk$E3nvkMImK0@hC$moP z_q7L^R$4kqz=+DzyYGsuokClSvCh&7mLl{UcVnVEA)mVLLKuC#886;Ce46!P1PF53 zzomfb?MG@ScgX_<^vWhL2XwAarwVd(vCc&YwwrD6FB{gmcdCX3+Fps3cF3I5SAJGvJQ&{qAPi^!)q%@@w%tMtFJhFqP(B=N5}d*mNfN#JsRL| zt|eD^zKoQR6xfLP=?CN&r@jF)uR`S(ruh2IRl$qTlhZ6H(_>>oJYUg$!Mf|Td@3xE zdfar%3P6a>XjE^{oR8oL-pK@C_s!ih03KBd=zwrIYd2^f=*W!}FVy}1GEYP=J>$-r za`b11ALQJ<9n)}Pz7s*1+9J*4#)Xn+nFR(QJvD6YZ+AL+kl)+!o>nF~xa>eCXe<4V zlZ+m_&=~A^oc*)(+lrs3<{7mXs@^Z4&vYc4b8lQaPWUAEaxynL{4N`Bgt&3fpg+^% z;y68uNXGTG{xa9k`vba#lG@cOlX6Nq+Ghtjw#`5V=Hw?&0#tIz>vlBLFD8sfgCT2oq;@9!wo4CPE^4top1G*ZdT`FLyX zAy@1N`GW<&O)JiLDHv)EJJe`NUoibC`itx=gHDrDw#Yo<4Xm|G>%Gwf4U|01ZQs=4 z%ZDe$Ae^QgkRhyi4`@zj0KhO15qU_}L`*-G7Tp-<&bl#-!XNX2S*1;+l-+%jRMTu_ zU#pb~D55x+L!zs{?PNJR_cq)jO^;r-ReX`gc|?tfsP=z9@YzVfMkld;6PU19)yf=n z8>uD%?uZ<(cSK-?Sk1EuC&&2C&{WhViF^rM^w-Zd~@?x2&Ls|=g7LfM%D5^Ye z_qLq=jBHgzZlckSd$26yr?8U3yJC60ZGMZxwgy8=B@PGii8h>_s0^N(ye^TXTeA;I zpH{`i2l(khGAnIvMmQJzBO?cycbw}8|q&?gpmrH;!5^%dXR_?AB?9y zTu%q4s&$JXy6JI+X311;eS3)9(MeAVSXKE>OLM-kv}N6aWg2m9GpTrCQs1zO z-E>O1#T2a4Zw$g6Ns;KaDQvHM&43m%0m*W{$^l&Er2Z4&7cK_C7LA2NffCrGx%Ir9 zW)_`nV6Aa$pPqKGqb9?|=h#lTx2QYk@*zu3zi?D6hP*Y>>sAsj`mtt29H-c;D>e$t zUXp_-&}%PVpU-kY$wE21%N6s=ouIbgybc&=JWsY?_&z|R@b1i6>lrUP!Md{h&ZDU) zk=L=YEqMVdPg9UjnKO5-fV^?70RX4x>pCH1^WvLMD0v0LTDE*DFS<#2?SaQ5&>J{< zi#LP0K4IXZToaQEdzE(CWX}D@4;c|8oxKACmKGj@T-|8Scmakd zE5#!wFKkUtYBasfP+Ml#*e$}6-1uW=lS*O4u5V=Qm@%wy07&ePBIqp+ICUJK8k8Xl zwLEUC^+9Tsd;IqAQS023{4606*w?~}(GC|1khc|a+bQLa<2E6G6h+Q=G~l3xp=$kN z^#i&60LbvLk0~b}ebAwlHMvB?dHqXa!`W7~I@4~3V6oueZa$w;*1mz8oGzo3=DSvnsz9jXDg-b5pNA97+l2Ax8D5{2fpg?x#uI(+jZcF#Vdiq8#c&JSonlu3lar1 zKMUcOSh*hG5vYT})u0jGKmA?xfGn+gz_k*8t>YR|Y_EI&>;Y-KH|{6*i>M zKq`Lxgg64!LearJ)VDlGXGz;q_#}ku7a0hEUbGCP2NYsD$Z8jR=oEkKmQ5bX_H5eI@2fCSfHC0lbRrnwY?d^6ld~^Ien&^RXO7E8KxmC z@bR2p18x)@)~iH~j5&;$^}29MA5VbBsR19`<1A1ZG68o!KWzdSj3$!q-I8KUL=x^o zsUR#KcD^i%nA&}++}N!;^DPdB`3caDA?X}F@HoT;hWDWEX_-ndYX2)eYhx;y^~Dc8 z&X#h+%y`Euz(dx9o~~Q;xdH8L2~U|YwJ~C&L;92;>^_i!8bbXb1mhsTS65le>G!g#Hakxd~VrYXi4f zIEAj5AZ|ugpWS+)6^!-!o{EjeQBk?1q8Q&4EhOqj%l>n6?Gdl<_ZRQsl#tS;S zyxxl6y-f(r?j!AHyZsA16n%l`&W}&U!r3?a*1o889rE&`9lt0@1%O<1wU~VdHSo?l zzB{0qn<(&}oi`tV(>@GharAO|oTpwlY~_aAC<$Ls4nUFi(rjUzrxM%Yvm!;{&f@{> zJuo47;6#f=HNor~m0uQvip+ky5m6ix?P)0#glUPyhHrwfp)JceHvrKQyDd@y995Y@ z!U0aXd6j`fZrOkU_BW`?1TY8B?XF?EW4?4>w38ZIq%AuI96)&z#!59MXA#_eGa zu&JM@rP61(gpcAS$YuL}Q%rygM`LAKD2p-H#A`zbX)3E> zbe>XIM2%+r>7SPCv=x70s|9f?P&pc6W~Y4CRTHHz7!hTzXfHw}p1Z{^P`GruNX2@3 zUM04>WdlZtGpBPFsKT>c*XAO;JJRt4^CSA)@nZEQB--|Vv-`ogJy5wrBxrwD!#+!H zIHux7$4-SiZnsNNbdIiWhZZdwFhG(WM)u*Snqpw4>9o`2i-7~xuipCXsrcBq6t|zU z(*y2y{NB=76;4PHhfL|s6cV&c8kK$H_r4oAc6(3E{WVx zkRdR(T%Lf+4BL<=)skpQ!g*hCOK1;06V{IIQ}K4Ln%V`$HXvBv_|1Zjff!ntQuQHB z4(C5u)7B{tlE4oY1Oo0#@!PiujXc`tC1=12LIQkvqeipfc+7Y?P-O_v#vMKD|F+J1nLYbIl zDFsjzgKfIo%D2?@F7&h!Xf4?j>gliiKAy`a2wm6J7;9m3e%R#5wqxn)*nSCMVyjG37=?ridGHgqXBz3UrQf z^1iKv>)rL-<`jjm8#$Bce8MD?%j9&f&qEE=zxK44#=ADsZ$msDFDz*h8-TjJ^e4A` zFGz_i#ZP2wzd5aY$3W0|QJPh9rF-FVwLfe(yz)Rq3!Oq0sv}w9`9hkDTznKA++*80 zzNhbh=M%O?1uu#~7rAtVTeu!zZoUV%;a16b8oje{dTKTMw6?l#!QM-RZ$~p9=lTTF zD-~#k=MXa<@W2p)J(i@57cE7*GHMkXrNMO(L_a?QNLj1GaUUqu0{FvngPm{KbG(aN zDRab{>k7m1n35+19_t@OOQl1Ayw8;G^h;Up!jh$U<}wsNK-65?{wX<4#u}Niui=j_kFrL#CJTw!73_ zktis+{X}3VK{PS2M{31w{opl)hmZoFlc=k(Ojrcj|zUcDK#LCjb zh;use#=aykKiY6ho(EhRW=c!}s;^)&>)4WtfEedrWVB5V=R0bXP|V9gfFRpglkRkU z63A9~+PEt*%>8wTlZ@!-`?enRGPI`ya@9h0-nHf2`^AVza==iPM52*Eu}atG8;cZY z6=+A-az8Lg8UwvaJc_%z$|KgIz`JP%h*JGVoPn1&Ga_O)c@QITy>Le^YUO}m1^p7} zlvUQG87LN#?0Nxw=^a5}{Gqs7XVN>l%Z1=m2Hj69>~HQ8K$*dBkhcb3>cQ7_3fmf! z_!Hge9(Pnmbb}8C5Kb%FRR`i$I34cmXvbr9;ShRq}J`z z+N~KREg4ktyO)@sEX?2I+Rp)poxZ!jjb!(u6^viko<5=9zE6-E%aA=v^gtd5!c1)j z+fQ5>lD*zPqi&=84c`^p;OF>Y!fl_i+cL9@R_q_a6PXkpg5RR0u!MDa1x1p0bNO2$ zJgp9Vd3V=}Z+g2|+Z}NEtmRVef<}>yLYAAiK)zpZAZW&#OB-k>Pa@zKyOEx` zJjyv(B<8R6Z!zgOlNNQ-p$p&OHfwgU_Nd`D;fCgow;y(A!O1diK@D2{Jc6;$aamm! zs^Evvd5iGv1TBR#n+XEj6MHP-uiDB|z@dgZGsO2^7n3R51TJV9P28GC*J%5V1U`KlTJm&L!b_Mucm?qLW+hel2D+2yHEfIL5y`8(Q4%+HAA&Z` z@GveBt2OOH!sS32h$M)9UQ(6PTFH=Y(eOQ2Q{|Ra%-&dRPW5R|flfEp`0Q%zc3o=PNomIIFdiJ{u9Yd z0Tw7;%bh-9*zRGY`TtHlV7 z3GT4Mw@en$+0l0!eG2f`58f!ILr1^CZSCQ~j9svmr_FQ3y_95yi|wDnFz1&7i0EtV zetHHjL-O#nM8efzRbIT`Htoj&6)&_#8Ph6;VdUFALq0b01K>uerjmDBC>27q7tmP@+JcTWf@wT}F1Kf7|xzqI9 zgYd=S05f#qvRzn!C}$&2u1iT@W_kDX_3QENi2DxO7Ao4BAIqh2@vH;+9c;8G_S8N= zhQW< zX5>g_!$m}CoUhz|1$DQkSxh$}mMmNgg%YK?9v?eD1F{;R1o9+mx%9FA3wKXH6x5W$o`GL` zrvMS9ndXU6U53v-OvZ9vwdMO2CHw{Gpyn%X%N5dbXJEXE;6*UePrfNgPraFTTMB&>RLeVc#2bfR$%UvtfPICc30smq*t5hB z+a_>4Sm#3>OX`#Nh*J9sFUB``$`m*7Q^Zv7&+pDmYK_5HW+LLSI*nTcdPwk7+9?FY zMFg+(ux0-+Y~h?npa9PvwidX@@5m2z{JQF%urE^E2iH8>(*rj&R_4{F)4pJ7RQD!6 zl@sU(u?}JUDWjTWLaWIkzTb-m*8o><6YXw-R|VTf19fT6oeeU zC_&ifGR(9AW(^Bv!gf5y2+TXBJOLfryRNZ4<&1d3PuRf5$fw_N1KJWz?Vq}Pp1N#n z#}@WBC6MzTKbDCy+ndzHIw7jf_?x6|wj=27pf7vdn>p8`wTF1r z8*?rCdl$@W6h^UJ#H`y#8L>9v{CW5X@9?s74<|Mo@sU~lcoVwq9K#A?D8d$h79Svg zduj5EiR;>njK=G8t!4h5pbDn#!leOTT@1%@xOHXR9ILM|SJPKoX2@;;LBFB2^r3!E zE&nF`%fj~HG6yG8C#6TPrTS|uw?V3I{iU`rwKH3Vqll*qQ-u#@Z#T)xD8^7~?X*Ss z?<^<_N)(GEI6L+Lb=(KOG-`lCzpUe0MkQf~GVj69?+5V8F@x=Ju@C;DOscwnn zy-{^5QX9B3VK8Y?)BmM^k9Y^rZl@#{%S238_6M~}#=)8f`P~KswW|}%i?YCzAz1T> zXL1zw;GMh$f`z2^BnOfMlKK_7kdm~RyV zG0^srP#sWm@wVx%D2|i75kLB9^3(>GJAG&MfeM}i+Uu^ut<>sWy2hU3aO<{0c%c0t z@VkQ9nJTm^^#@H>5pXVfeR{GN=U$cR{p5EspW+}ZM$^&xyao+&}`HCdhlY_ zLZx!d0B}d#{Ed~fkI7C04*gXP5}qST00V=+Wv2WbsPuQ~Vjb*S(vN;%7|R;s8<>qh zgIlE!D`m9TO^2$J)WRKB-sHMs>(F1Qo@IrEeXK-$LJ4#=l-=u*y7GV=< zZ6nu+Ks`L0shs^hoKtQxHiY6}z#s#Ao0zg{KSN@eNDCGYqI(M}V@sFM3z=$7hFL+T z3hoBL&rT`7S%1Dqb>f;0vx=W;yJ{aEBJ^PJI1CbBDB(n>1K``Tf|vld9Z--^hk`Z} zotde*Rb~#XfaMdq8(`O>%rgAlD9mQgcGW5G3(`98Zfb7P?}DFcSERu!D7JqHhpx=i zMlJOaj?xV&&~v7OcqV9H)XN2$>Td837o3<5uX{Vr#|0)ayI~FRN&qR?-cm6;SEpGW zc;U3!1(pI*EPAcl6#P2RiQ^z8Tu_S1to4 zb;MYhO~&&zaG0s+UG_{Y{ukNdO?RCg?%tTI>|iUADSh_x_8m(0b&@2eM@QM%jv-$l$1mXCn3H7Itu43lzc-9fjM! zCC&gBr@GvU@|7cxc?pidciT3=i#SR`o~17Ben{A(O&d@CG2eA;$2o4^e>5Fe~ts1IwiVvElI4W3_}imgihB4g0=mSw#{>Vi}@H#uDcQ&;C1NHfP){UXaY zh%TQT#acF1B$R1i!LvLp6EOHUpmH`cuTkYHj!gBY5Czu@0;a47Mt= z731yT5ObIA*?XZ75~$T>^$6Mys${|tZV%@HTcJR!ZO5THVkE-4#L2h~YqsmK2p3g5a=ZAvq(iXG^8M>l*P5 z*xG01ZefQIpZ~c4s9A|7i8%?YD@w_>l=XIaneCAp=tuITajq}^66qVVwqkk^jZmMW z>)nZc7w^(m6_pHrhM2l52&+^?_i2QIm1D!V8ZvwN>b5!XJi=9WoVeUb-m)U zaOG8na2SIhWHK77n=(x$iF3-2DE;x|+*?rR-a01#$Iy19@NcHs@~79=uQ-navCwG+ z6SAHHsj(-2vplg)Vd^bx4zIJithx3V41RoHRn4s1cEJlzsSbCbXVj;AcsrUOw;yW~e~XK)vzfi(H4At(tdnTpe34N!B^-NDn_azi(MX zg?~!zCH~8QB95W`>qL{Hf_t&`J=c_JGhw!cX*iG0P3iBP*T+N;?HCRN?T@cc@_p|9 zhsbR`6a+gQt}6FX@%B2%-MHGZw56W3oAXxmsElv$xYUD9(dg6@B&q4|d^J^#MJjglV>f;u%Mi6>8DmhY*s$FExQfKi1%y_ag? z**~j|YTZHS3E~$ib|RNckjzfFfv?hAE8T^sM)S#^kM9&#T@vJa@q1d9GFT@N^K?wd z_%(!A+H;#IT@H?+?0RPUP<+Nl$tb%g;AZf;HrggD;f3a{xBDood4*4>Mnx0GCI`CF z7X>AQqqe#K1b+YBJlqyDVujV1Ys*=mkVlm@czvTaN?{t`IL72x_kNMRI$NEO$>FV% zUvFa^n(~o-P*wMKfSpltqwKM!KsTAh_?UdJ+4*Z>e*ju@QfZlF;^vxZQ$juYOYBGL zu@@Wco?POmWPhEoQ(OnfZ1Dp&bNsr3KQXg11$sN=ob&jqGYI=y;?PUK?z!1{hP3v7 z#Da`QvpbQ}li#M>o6b<~)?oPOAENahr^qzKJUn|8sObf@(^T=ZyYokIJ%b7Fj3@=# zdxF}VHAaQ6-#fZ32C}Mz+$uh4`<^)&k2U*Z?y*mrNj$g?IT=T`MXiM`99L`TsKROWWOvp4PjXY z=hQBudpgErpc9<@G)+P7)$2HH`C)nemI<@oR4BvyufO*ejX0KpeSzr`ud|HYpodFc zB}4FB$$WycRBH%{A8!cq%87~ZZIt=IguclDi)fEJy!_yQ9|wY~@iS*^l9s4iM{An% zj1GN{zE4@_x~ZIFu!{wp#L3f|=_rP+P-FqYOrA1NR7>PP5DtD|y$Ft%>PYvvdvR-DtU_x2BM67Cpv zQ4=;T+y0umgipBKM-@EPoZm+b(j@$vQVnbUu=V;G%V*_iEEsjIgp4UWK#<(UJfk5fM_gyNy$ zH9C+7wfAU)nkd#g@NPaMZ8OJ^XG{VY_qg5T1ozVC3zaSfK8Wg^{k=CS_#X4l@>QsW z59Y&kUk`x{DdFX(dngR=jPqYI?}lBNY_xkr^}Sr}^A~t)e6|;q=bDjw#P7|i|KYKK z1ibTiE2iyVWS^VycSWX!&faCeLULnxfqR?PGX$f_Rc|`KG`Y-OyosIUMeKHYCtv@Q zDe&8DrTsPZSG5!hG)Sc_@04jX5O%UfySbRW$hY9y-3zpMIir!}m$UD#>0kQ;&+}h_ z`F}R29+m>r;=o(X^O8r{~qld zx$D!95VdxZmM^~-=UtABi)BjuIuN*EHnzF(Ow;b?HNy)_zxTC_Pxn)Y%M<*ng~3YZ z<3Qy-kq5b$+&G+>E4GCxYVKga%Ig%FH^D5j*f~<(`H%7eE9El|H(*nH=2x@d`eM_l zkP0t~<2J&p6r#|Nh6a{6u658qfCC#^U)sp~*o};I?}c9bGe}bWb*fRGTLbi+GTr|1 z_Pkb0HirHoJkq7+B#rje?q=A-)2K4DHxHs-|7Yp-|AIA?j%U0Pc&pW==_nulb|$-3 zmdy94oCVebRzi@Tk?gco{CWR#&*Og$sn6`c>g3lN?4hMG(FUcmUv0YyK8^=Zv{aNe z0IT&t8dI}xg29-dNrgNY9y_g9fsP$Gvwp+9r>>bswGgsbd(|{~P6?-TD4N>+{|fL^ z#?1-34YO@(Q$Z|yBP~u66P}39cqOW8BCQDrztbjH#X9^V?!J=9&fqd{EG3= ~$# zRxJtQZ8$FD$E>#nU|;ojv2WrBXbd7P7VZ&e;z#OBfD&ewp*_oLVrU|#{N*m5SKKi) zP7R;$JREy&0YTl#X(qq&zwr70Bc@J5uD# z5Y7>xZp-WeV+Qi>x2q z|C6uW9Q7aH)W27yP~gFp3s=E_a%oDV&XYIq3th7MG`o_Hf9hFQjJW*R(f^w%s>y~o z)sFN2jSO~@#6f)_zB*nL5Z!uC8=q~bZkD`+u=omFQXA@quw4@T{Qp4QLqE}!xIZ#| zjAD1UxbWcSY)p*)YT!d;pKb4c4x$N|4cKN{Gjj54HAi%l2ZPZ8Y@eG4cS2A^LA=m) ze-{P$9R zJ2LZS-+r)tDbwr%oTz%*-~fExlF^E^!&L`B-_0RPPdkXM=sq>1Y!-~p-LMjg4P_X) z|0f3IZ%&7rn@nSo=4jnit!psUk5t1OE)HULU=1r_d}Z1ecrGcnkmA@8|Mk;Xj(}5a zxO2B`tm-@uN0z?cX}TjW{(gY3UvlH_W+b3vHibJdjCntuzd1w~tdQ?qIMfec)}{7P z=6W@=*hBP!U~;F`zM3R}Bjw~mJbrq&!jRU0c)w+jRaH9Y6}L2Z$#Uc4e8i zYvjQ?F`CajINGyb#!%ZE@I#(Ii2C@4CgWdDJP^B2^?O0kfAN@aK`AC_NjT(lVYnB9 z)xMTB7m*@lHzu?UhaCsh22Np1IrLC&9nDu!Y!;Bt2CqCMx#;Iq(NE7#CUifYZ{&EN z?Xnzy!D4y4f%s->v+^g;;L4bV&rDnG-3T|Y88%=p#W|A5Ex9xUq(|w?M3-^PQW-);A!T8j%3B_P+CrOsp`c+2i#ej*L4%sWc(M)yNYsT;iKif2(nqR1>O} zD-ne6;VE=@`HRfC)`RE9V~y`+2b!2ilIdp|)*c&?y%bz`boF~-%ASl`yV<`@f<6}e zR(97yXzA^j^ha5310Ig-c~}{v$yIva@~?hLmI;?FUCO5eM(fWze2TxZ2dXNJQrU}f zt!AnGk)kaig|8HVuR|P=!_QjCgG%n?G*bSBb@})B^l(-7^GWL99@W&uO;y8MBFl1>MQ6=uL zSO=Y))@jb=c+Jz~Y^PKiEKh!aLa3TK?*;iow&EgGc7v}(piYfOo>RQ|mEP8;myM#< zuri;03-T9t&VMebjT*PR@L;8KC8{P5C)?rvAf6_Z-8m%jn(YTO?n4VHr6Df7thgYL z-zOc*F7$GzhiQO1y6%lLpon8y8l{Sb-}qLpMzh^7AVfRLD!B0&$Ty|0@g2`m0>!Mx zxgE7h-8j1JTb?>#v}X_A}B zYF+8*F#BP{X(&U`(C_gO3~D+s;r1nDk&>}KiA|U-m#MwCeV~th1*v2F6xdsjF2Mj_ zFXkV?U9QB>q;I;wY!=w1Sr*(b(Uv?4E`xVQWc8oYE{)w>Xys&kEj*O&^|6OoX}Tj| zxhfPKrSvE0_&bWI6&0}McyR(`4IIi?Ro)3>%nPCAHr(zYj`Ts4#`|7A(RuRZziBZ4 z^s+PID6!a^%bNxSAT+uz=#~qU*=NGf9LoM8TLZ0mzB4L&@dtKT=RSxp;Nb_v4hMRT zc_=xGEs2W;e&-%2KM-Q3ZEeSyZ7j1mN5;|k|J&ALmGQkWE+1-979-ZocgmuVOVhCk zd-hje+SjP(W(gY7lYdH0p$9$@yai*2SLID$fi4LIF@}*wQ_G82?^Eb~JtTx$3B9)` zuA&!0_iAD~ zJtO%w!A@VN?YO0$P?q_#9whJDWsV7+&2t}Vz&lyo-xRtnDt4XXHe)o)>|yy-Eq{Dh zXnmUjX&}>VVcpzl!^?lt?e#(7SKx6J|LSpm59N>m=xz`5L@~9tT&s&yKg>`YyZUTm zD`uOsX6?Db@TjVxov1vqzW^d5^=0g-tZ=D~MWw3#BF4fpS*}8nEw8^@ameWPM4@jX zb?J{O3nPy2;>hHskRQqFkKdDrm~!1E1r=_w#^T`0b^hP!NhZbX3_lT6E?%;T7@6Cz zUWhXpA}gAT`hv3+2fRk+=;Y(aq69Yv@9}*+cT`61MliH|`5}RZ5<3vk?bZy!a7;q# zHeM~R=psketlr?(JB}gN#7a3mD}Ec+uy98`4(9GN5?BdOgUyXNM|ptwZQcCcnb$vY zPOHHD^I*j#_PTrzLlS#**v5JQl}Khz$^v4YOJaJ$_;1`7z?baa`Q88Fe`fc~6Tq$| z5{<+ZInVs4w2#3$ajULe_lmJJvp$%nyo2A||Q;zSmIY59jj#De^I&dAFcU|%l+*D(N^sJt(3E`72I)^M%tLVHv~H?ae6A> z3F%xKsS^{~OxUI4Ia$cCSG0#${z9AARpK&x)QooSQ*>agBUU-T{&QmY^2>YAe$qH` z8D9FP@NCc-8JPwvg*^WS&P{-nWnE|D7W`bC=(q?BDg9x7GW1324-**chT;g zzkz40%dWEQa{d^w@dFA;umAb5dsyv|YH5#Vvjv2=!@A6Uj!^BI286;KHS1LYjOc>; zVy(~G-0p*dt~RrhNtXKg9u+s-6c{%!=CpjK-DEv!{n7-%o7!OwXDwzd6mp$F?_OA4 zzB3-g^A3KIAX40K=rrR~x8LY)YGnHO{gN!j==q(-?hREFRR@?)X@c7lPwHZ(lsS_O zw1i>4(1SjRb&-KXd%rxtWF{N^LB#zGMZS<1OX&Z8Q2!r%lu;_d3bPx6?pO+s4Ddk7 z;tpqo1iF1Mj~vo|IeAL6J@`6zK55d)KwPWwZSugZqb#!GU8wsbd4gZH z`N~z%uZq8X^(d=v0+Hi(AwU2JMgsw^`d9!UM+jT%9_pf<5gvIyr16u@fv^=-HL7PU z^pH~+XM%=xSzd3%bdeB_b#*!stMBBVnfon!-R)TtX^VE@p>zpQbYxXfZn3rlm-@;@ z;WJZ*N{Rv`a4HNRQjO+CgKm%~v8i@KFPRjlz|n<^zsO>%r-Z8EZ24n4Ui$(0{72LW zdiu+OT^?m0oDN` znz5&Gk~`ckcp$l1X zE(y|q{Jm9$AeWi?!o!9GdLPQi@=l2j&C-5MpjdWzM+v_;QNZcda}ORgt;_g^R~!XS zRJ@d+dd(>3>3_+&{e3@%@Iq%_^ntglmN&AMxH8ny6h!a1V%c1&Dup0iKo@~xsoS;i zarG~b!(0E%|IO$>?YT=4w`mOE?6o?+;co0~)ozUg}V&9kD4kYTROcu+`&>DTzjbq?H&!@a$-R?yKwKiue2ODcv7MP1q*y#&OT zmS)6c)ReR98XZVX+F9_aOY4q>w7Jlm@a&XZBuskUJP&XMkVeny`Yyl%=2f~OCSWor zw9;d{kg@75f3L%66jmeBlWAu@At#NZR_kJ|KuX9G@mUvLZNQQS)m5`xK>T0UqzQNqNdR-5jcDJ}=Tyq7PVX{1|!CjJv~)!=P( zVt@y3N_bETMH>O>V>bVZw6i}1HKCHBvH`A!u}BmsB1EN^uEb&$3U5Xwzn)0Nz9Z%o z3XBkRF`5h(A2VI?g+x+;F=+%`Etw&bX@!yP96}UtNx=!;nQz&`vDL&P6K{AlCtnXS zbT^zd_W3)^VQ>1O$9t#%?o&&{-0?3mj+}2L88WaP4ZPMYo6A*^C`)cp&6_!&#&*q8 z?(Gtg2-5H`vg*B^3k|7Zh8-xz`obR04^hv8PmSGgeh`yN=}VmT%732g`>p@TvAQ+3XSfKrl%tJ-L zjkj&ZbIMWhjyERWha@j5!v}usk6<<0J8IV*ZsIag4w6T1JAx@a%PocV#A1YFLE^~n z9x6WSVn~{%W2&s$5`qF#di!;~9sW6K;)?lzmmS8cGnzX@7*<`-voa8bGhhKbA*Kr) zpyRwCl5Yy&Y11#8mwfB>@u<{@3Rznv;wSe;g()a_QNoDCnu^T~ zDera4gh-X()eT@Apvus+)_06s*Nt${K2rlg|EcQ!gw-H-bc#c@lu$j9 zvsN*Vb)vt>HiWBz$GdXQtWZDn9^tMak>fdBfo(IN|MNm^#^!vW>L3X+tn^^80;g|_pnWQ!tGR2|yStgi!9b$|O~3`qI(V8*?s3~c6;(La3(lqBmDqdM z!svbkeiuJ2f~_a!BbKt|913x4D8{;_0fF|V<*Mqied8Nu{+^d8756i73rSm+Cb>`~ zq;@X~V7HZqTKIf|NqF72D(9}uUEPMh_B<}lTWqKq4`03*@uX{!+jgtRkXtb zyIy}gkxXp0LN0K^nH^g2`$f1Pc~6Empk9N1XE{x-ap|JfYiS9-AtD-SWXNW56B@)Q1Zg5^LXE1xT0zfr7O6n48!b9JTnObImw zqAVW#B6|`*M=bH~-=0S_l_IW9l1Ap)Lu*8?IyU@Nb9rs!^1x28ku>dETp@=YLV=c< zx_y)#c;h4vulyn_(fc$(f^5BV~3$>w`QEcMau8^F_(n3U* zK)TsxBAdUuMD*UgCYOtfKE2m-rwUv)MiyI&b3r+kht135Vo^mBTFgD`(|w;U6X?GM z-@mX~zZA+yz6qLU>S>Wim$!m~=5Kt#)uXmD-MSjI##dLs)2|dB>}1$6CqOrQz2pT~ zwA7aOx=Urh)eW@>`xNX_#F_vxg9D5#7GJO+Uj>v?(t9epLd=2Lv#iGXw(#JxG;ZQ! zrpGsJPC-&pjUqczc#X%swzzUsoxq)oND&<9__XMJ6|oTJAbY{K5?6})s_8XT1_9Ds zRvgnsrc<#Qq3?5Wb*NR|a)LG>R>vKYIke#|NaIh)DgvHj?8$>NU4e3<(vD-`TD6^L zmu6V6`HhlfDN^|t8)Aed)#A7Y%0 zLQXUW$O3usssZ-6IW)F!DRUwSv)*ONJt4tCzk^JD>&PTIp^1&u2)k#(VQQq0(mjzA zc{E14hC%L}cS8e_5V%?tkl<;V?N|!djJSIGy1A{~8Gwr(r)K876^C_Hy&Y4gAkBj~ zTO@s~un1hN-I53h7p`0xyf*$cxKF>KChFcm-tB8@*P=dJC*hF&2~Z@g#-_KIp_quMqT6_f>};~@k3_%>JkOU#PKt{CUr-Riwn`Uz?cLQfYpfr zLC?3bGr;aGbuQkt_ymToYtoL#Uz(*q*(**YO+sp%M=pX;Ktys(lQ!YnN_g|`%r!93 zl2ecRdxLiLyx@WP)07D}wnGQe$FLbHY-ysRV1OmYa%m{mb{n?ykSt$n2ZDbxD3Zww z3|Zwlh+Rb!<$nIqp7y{dYRHWNAGmeu2dwU2zL-TkwwPG>JRx5@I!lOV`P?ru*9ADS zRJRLnOd5NVm(Ydr@5;7ee(Ke?Ojuh+f24ND+d?NaU8r*imYDnM_aL|o^IZZ2x<=3_ z&x6vEfMAKU3T?IwiGZWRBSeG`GpPAG4;Hj!+l56WAEFzp#MSyP-%Z=vxvzX;xr{9* z776d5YQ6%%?up|{2F<+s7;N`by2klrw)H?7UiPx;m5 zkPo884DluF)o6*@XrXFJSxSpfH&zI92aww>A;OWUSQ%3L`u51od>gmN`MF6xs+k~wLG@91hoE$@z9V1_NO1{Ha^hfU9*{#?qoBx1ijuNrXW=Xo$9;iWcT zF~}%q@sr*N=xFJz*|(VnyQ=^ST1rysB61ZiOTH|#^eOv_L@S6vXJHozk6j2l%Rmyt z6vUzR=|Hi$h1rg4`1-4ekX=D+2oN!M0=vKS(C@4i-O9-IW@MAnwM6szZ>>O6WfKdr zjk1CkJz2+m0Rw)8!qTAB+j;qu1nDotPY7obx}P53f$JmYg&MPLXP;NLG`?u8dd(GC z8`m7_M^nB`i{q;c6B3fsD|13zaS^J~!PoONAZ(s4%*TEJl$Sw8<+X)Wf?PdGyU;XC zTs-QyZ6WNmJdQwK+*kDf(e~a^O?B_OD2j-RfOMrr1w=tWsY;82G!ap0QlnBsgh-PX z5|t)30s;a8N|8=LdX04Hy@ehGLT^yZ63h-*L`&_V3)W@A(f_GO{vP)|zv^ z&-)a=uZq2aIZYGBnXi^C5I?ou2Dbc)x2N+MY(lc-r9eD2Ic~&FaR!zpCOH4Ov_Po5 zHD&R|j0tt1q|4?-gS2kH@W&h+IN(x-^!s=}VFTgF3ziS>vJXX;+jQyw58%eX{cFZ< z2zplA{o|B>F$~3?%sxEe_e970leBY)(zJypCq;jx24Lm=pFt**P;SuGYI-vA;^6Tu zzs+Mm{D1L{m0Lw0oK*;X8g9>t2IFs81c`5Q@Hl{ z%9z|%Yx!~iP1?t|HqIa3S=`e2sgci2+9i8al(K0CWBc%Pl!@O{6ysL%U?8&Rbz{MK z$zEN;XoB6!5_(3#WSHi~0eC3Lva7U^KLs1ta258RkvlWcJE@tmUvk^>^S)SL3RQZ^ zC}6ECgSQ$x<|fFltFIkuTt5?TGl}0Oh%KfInNq@0Um0?;LsnlWUIj*CBeuFv^N+?@3+b`eIVGER3>Z_@5jjK07$l}P(> zVH&2LBunf<=+b~NwHlR(X!d%1{d&TmfLpdOX;3PJ_y}G#i$IMl$vik!TAFw&;-OY& z-5FRI{lm7BHD^Rp{JPo|dHo2bhO^sIb)XX8Mey9xZyi)jrac3YY`^s$3}1UN>g`f2 zSEbgXI>^nEqK?J>JZyeBj^blwfTl4>;DdJhs`2X< zNAR*;&WfW~MruR(Avk}%2B-VgBiA))8|v#q5FYBubiJ5`aQqdFD|ypCi7n02x2t=gzhH1AK7B6w>os{X;viY7-aE>Wl7<+rYl&YS zc^V0139n#yVc=tcU|WW*-8=)-L`m~uo-N&0hPfqeG;GCFHMcdOw<|Yarm0yXPcXWp z6a$n?NUjrxwWA2n4o~(XNqFYjI`W*I=fX*>ONOp-CNASIO!8H-(O2%Ag2E|<5(fVY+-Oo+W?qsn*e z7HudVS$N5Vuk01p@&ozCwz(=Vat*$lya2a=-t5l#A3@N#)mEL^!WS<{TR^bAf2kOR zVn$qkSViSXSY`{{D4Jk*(`c>wt|OTF37k?L>#aEbdw~mKPfTmetoRH%L*pvYEBIsK z8)sw7+dXsL*{d5{PYT6EY_7qq^JVp}2w0p4D&Ex+cF<$w_{dXZlI~!Kpb3{~!E2@Q zPt#y~U4Z63b&m2u;tCIN|HOhQhmYv4IU1lK}*)&=p5Q#tiRYg{WM zc8cWp=ERUf)sb-tFItNEQSiD$L3vc7nPrQ9NlSnkF1?00s5z-fz6_ zOd>#BT^5Ls*o9hfQR`UtMgdS*rGVs#ThP|mLZ)s2=2vv^vwKeyl=O?7Ni@MkfN(12 zshx2r3$l7%cgA)|-rJ_Hs5MDJA|a{vi!8Vnh7qfe3i$Bk=~HD9zs0@hzhP8udWz=l zbx5Ue3z(f|J5nOp4&(ZnFjL+gwmPpH=Ezz*p9kH${B98SPit4sMXunHH~jyA&2qj$ zE#?A1BSM>qA?uLr@|IwEdR@U+U&8zHLL2>wnSQH1!ncWE$hOOudb5mkVznEqO zX;*Eu3+kZ%63=PYazx}mZeiQ#o|$V#kQN9sB%ZEeA-8)oxI1gIWtW7o@~)*0*+EbJ zMwb|Q*%UdW$*P&xVAqg--h!cQ@72a{8!eg_D~Yyf^hyoDvzDRHR^RLcuQgs3E}(Is zm~|qJwa0wG)Ar=Z;YM&CCC`-NTio)^HSPl8mvXV?ve~?KFX+~x|B4>pE`eR~33M~S zxuthd;3>k4m^=9p_NjCPy8t|0bGi9 z?&1SqAK!<|t5`qKThLXPo2ZQK>)%4uEG>jXgs`xM>7u2YH_f~h4!0MO&;!+`s@3A1 zyC>|-_M+5pbdJ=gC`WIdjz0yGQzC+*5SQ@q<9=ZWt8nimXnvH%89hp_( zn4O%J^Y7adj1N5%u&n^3xr||k3W^D#9twHPUojj0@zz^J;%t$4cm|!|EbbE`%H< z3ifJJ;0WIC+f-Y_e90Uq-zK)T!v&Zb2J-1A`GPNG0RhbFG?z)_Ez0t;PG@qSUsQLJ zk%IAXsYA1YSj6Sd1Km5CcgKzVGig#-isVP%kv{ANb)%pcin*`}9La%d(Jb+f zs#RQwwaOhR^8D#0uBy|Oz%b|JvbMQ1vS^#^+D-TKmZW1MQBbrMKD!Ov;4 z1#l6R_Ml8^e*>CyW%SO{m%tLs&5Eqo`v-fSNoq6)aSpiBEBj2#xUc%D9TxjR! z3(XqdGF2sm<&{xqeis9)*pGrT*98!~JE2kVL5|#{x0!&w5FY*x`0{R|r;-gRq+(YK z?!Qcf8lq1k_BD;XQuA8>GEH6Payyw$O16PkM9l3$?c@siB8+$Q^4WZeZDgSlpXboO zOl*cGnG?2smX(7D~F z0=sXrr-np`Kr!BfT;uI&LR! z-OkzMTPHaig%^5Ek2wA@VygS9`j)@y1V`{vLr8r?bz@ArabLLbnXefsdC=7Isz5dJ zZpnvNKRl)5Dyrfqy9AX&iw%QVR=>IlM_nBl+r6#SB=a+=>(86k((&J{OcpyHKqcuk z=7^=2`+Q6~CNS;Yq7M8zeJ;>w|G?nJ&QfKi)r&~yYX4t zQ#QQnZRqe$R~PEdJa^^TKD)bRcHQXyRCBj4%=4X%n8y#-yrs;ycE_veY3|MZlx356 zP8O}*N{`mgYmL~Hp0CttcUX6iS7ah|G(7W{PmtA!FId_KM7jDBd`2-wY-xKlaj^l+ zO0m%2WpBrQg!!Wi9(1K#Nmy|N#uKqVbXG(|l5qx#Ur+Z&^SN{vKb`-SYMDarXG_=( zc_9A*+ctvzn*Z&iwWd?Rx40vJ*y79rT2<~n?ON{rq{j>E**#dtUhBh%P9Cfk!-)o8 zQp290jM@-w$BKMBvgU0p8{>ke*&9C2H}^+R=0#Wwf3#cMzYAC?)zhp@=dg&jK)nk@cqc2C`!n@Uy;IIEt zn6}f@EbZoD$sSeXOpu3F>ps128D~^VNM(R<=Hov#iT|6&nl0(o7X-+rloV`p!bOm6 zFM1+%*4Ta;$>WbD7SY7kf&fBk+I2c25p(xj%S&F<=>Ot`oc~%emM_b3S@GEJT3h>L zQc))XbcS5*_-6fcRS=(5ucuhqV@v-3y`JIu<(d-J^K&0c_b zhh3HX<^7kbH#24Yv0XvmKb@D425f6uV2vieL8RUmQ4aZ&RU_WauM0UZ8}_C=?xx91 zywTL9wB#BP7s$Ruos73aRyz1zzy8_$_Mk7%dXQfuK;e8l7H{|V$E!LwO8S;o-r zmVKI8DA^71+5VOOId-XfujEh4BZ_f7p5z;rOE1)9rwk0-%rOY!JxO@|LEK+#9bM3Y zx@RR@^W4KpM$jQ{-7n&hR%)?bt zgW%?dbvm<;ex5J3y?ZI}H4S$3mZApxqD?euHD|CyJRe!mtA;5;>a+CUf(lBzX;)0M zp`b2bf)TXjDRQV;qk<$3b{_jWwqiN-8o~LO39<|Un`t|6zRD{8H-aDQej@O^tr8uS zL1m~=!k)q9ruqqNrChE}wEu|B&kW0hM}^X)8pfHoi~8ypNWN_~{a##SRYup-iu}R^ zna_qhZ6DNtdcM;1J;Lj!H*uJj8FWl$`Cx02j7D~5y9yUeEc8?88$GcrNW0Bjh0QDg z4B@ElMuIJ6MBtl{B3fOR{#V8}mrZ)C@;;f$XD~0b8}xLixY-{>0{9<5Ljq?{yJ(&v z&ZU1#&e2}6!f8bb>#M!F33&@9nsZJcw4ly58Z2%{XmXZ?>!x+Y8H?sR^E?y!^y*$u zdd+cd&?D*2ueSqzy@nGN3+6-*fw5N5KOjMrgdYmXp$zHK%Ou$^JKY?~j)8(zmA?Fk zERki;7H%?2<_0a0ipUPtl!fd$E5F{Q`84HhnSvV2%c*J}?x>ZtnV;Fn{e#lf`H=%% zMN{$g!PP)OBA0JSeee`Hz>sVd)M!82w9@J5Zacgt{??bYlTfy{0U4JI13SqDFPxwq z%k>jz1G8U8Sh_hfx5IlKg{IZE^ongV{T zOA|4q(YT0R9qAm)OA8&4&bpgR5&(sYGFOi5r%P^TPEV3a?cck+#CtyT9==n#6y_0ZL*uo_+U$neP!*IEBK1*H}YZVF5BV>`>H#@|!F5Z@XVeN&ThF>y84KOY%*F1n#h zUHdB^TTQ2J)MD+A>r}O<&|7rAOhGS$$&JMMbU4)<@p#00k`3k- z=;bBavO_D2cu&{IOoFFT`0em*O@2QWJL0b&5GYAp;AZeU42S~_QD`@{eIT07F)L&@ zMOO&M>xGqizb!G$Z#j#6{F?pZY=fSd$i`0IGKOGlkJp!&L?~RD5s_M1yz;o_Rkt0p z59a50;p*H6kjfy=qV_RUsHG41bfb@Rpd+4O3CG{))o4!$6$4#w|CzV*+$I#I*S4g2 z(mFJVl?cX1BTov}gzsMvxvrEczVcAH`@${odnE@0J4pgKf@VQX)}u$M8cxu`|6!_(B$zY~6E zuu!&18#+3oVid2Xbet)sr$vdFBL0zcJ4JIM90fKW~V!0{8T8tc*9PHu;w&5<1RaCgmH-To{q{av9lTQZI|FXPEa zERp8`Gr>11%aAS!PS1j(dxU1uY1|)CH6kHqqO4iu-SXo~y|I+YC~>H%(7U$0FWy@~&m#P1(Y>&HBmkIj8P{zCX2Ji#$ zVxpD91f<+Jq*TUIW#Nxt^mfe!T+QGG)&*B&6$S9fXSq$>%3a!?0e6K1@;S4DG_{$R z${uH{htX|o7WgkY2o@cdfBykc_rOGbK)>uN3YhjGrCl;a#&U=QRRtSHaE=NWR@@@k z{!Q1rKrwC$`sx?XOzdKLz04LGpBVxx={f=MP}tj5YKCP6|F}5D7~a10^gs+euY@KB zFR4Tz)le;pO6e;1$71q{7VqWUv%Y_?pc)P2YzTYiNG3k>?cE{lUC0y78Psm6+@?rM zb~+9*_%`M*`6*6oUU4O@W2Y1N!x){)*BRb%J-0>gD=crzTD)4t2H8_g@R`#a4~YkD z@ag5ni5NWU)cQoRteo8b`R7=F2T#YjHCdbP&*d^TpP$L`#TZpe$rT&|(*=tbJwX#h zQ=-@}F2rCt8)Z0yOO@E~Ol=5ypWw5^Tn>Cc*mIv2CTRz51fN1JCWFc?-XO100!`>y z$San45hdQR>6euyXXAc#`@jWzc4mWjY8D;~yY1{dpLp?pA>r|iHRx-z82xhR704fUZiQD$*6HK6vR$bg@=e<9Ky&DwiTbQ zMG)K)0ue!6A)XO)RFKOCxJp{ot) zak(FQHfNo^ZYrhQM!p;C0_b!4fW`(ARfD`u0e_*Gvlg?NIe#&(2Pzm%`6>|6I)ubd5}j zSO%Y<6agHH(ng78TV-3xr{Aa7toqUN;G5c|n>;jeK{6eW$8V4mEz*aI!W-p8Mk zOHZ+n@z_24%p&gneCJ-YjD6R{yFb*;a>Hv6nWcy@(V31xiSY&{Op>iv5=ObpY@l_- zAMRDqcz@;;!PYDm)~jF(I<##JNuEGAnEWsk-*@Sv@x=rBl()?hl@obp?xJ_f@y{(@`c9&qJ*BP(B*1?W(#Go=d33+a31VywCo;>bc8D7cjEAsn?~? z_`Ju-3&RP7R&Jm3bNVA>*gh%~r!5j!FMoEsSneH)AIaZ^2MMj)fr##*rG8=E&J98` z%Yo=>MTehZ=62C2+_qh=p0}q-OqM^8QNsmqR|z0jkvj2yEZ=SC)_ps9g`P(mhBsc% zSF>jdV#3Tz?Z$rkN8YgGhGBz26J%R!c~2<@zVv;GB=(N-V)JEb9E13LFdy@{RGpRh z!VN-+zKYTR=f>iHQ(W>1{IXYH4tV5@LDRFsr@hH+jH9yWw8HFqg+K)Wu(N3b<{{SE z?l#Q?2V?r7)n1{o=R}LnrGFgGztj1T{cBr^!b!=O_tu)25F}!?DJmL#Zj|!DlEKUl z(Kr7-`+gJ9m;4u>|G(6{|H~JI46*a5((H@{E|N~G~b!bG}{$bNJQOZ)W;A`j0bZX39;?y)SE*h8>%^qz*h zKVr@W8ejM9hQT8bx-?OiO+(vmVq$;~ih<|Nypewpe{+y;*!0)eN_6wq^)w55P9xva z)Lq6fP@C07US`@A4^<%?ky07K$kS6I5dGkG)zvuVEH5e2t}Ex)zXs3NzWp--0h>pD~km* zkfaV|n_niGPR|BAfzPf3OmNjB$NjG(&tPo5QJ$k#*=G^iQYAGYSt4xsqx&VMlh|3|=#J-= zbY&T2216$D2)xbwK|&)}AOq>kfCeQrQcZ}TtH3h$te<@0ve2X|q&qqP! zj?whWDMi`rdcYDrE!0l55uZHwNgRJ~K62iCY1VtMp!!#X!a>wh4UNx>>_~Y-f(GDS zGk7M{3&d0B$y4gCq<8&-hCJ1~UA>7mM`vhYdJ{0eU7;5uuRtf0Qh9!>f&m_(?`IYUx=yI!{J+DvmmTqFq z_lnZVmow5b`|T2!jrlO>7nER*tbV*=6JwZan&+hfz{xin0#+I<_9}?Jj5C8o$#&6W zquZJ?jSLXU)Zwl_90r%@X!zOaUtYhb`)jFryUBHVD`mlCSC4T1=_Nj>X%PN;8O%!P&k<|XvryUR z<~z>O<$YeQ)+_L|Fq1Lo4|+GxTd{QSDv-DF0JA<}QTZ*gnUi<@sFAEXko}23aIEyd z5@tr78TP#I(H*CT8P~6J%w97YcK- zEJ<*YYKRz6;j~&@RK-R%8uA|sE}M*(PRh`0dduz%h?x$`qvNVGw^x^Z+l)<80)?aI7G6_l(W z@iTw4v?>a8agz&tcfQHuNll3KWv&SR55vxjd(x~i4|tw^jMU1QwJ4(bjL8D1VVL0B zlzV96%Gk+Ml46%{J1lB~r!h|9!~vZg^m6cW*Bj(TKejI1$9d&36Vovz)_A?9n2NOs z`Qr9-wad{KCR7#V&<>5iv0>E5ny0`e;Pd;PtaB1!#`SjU`?IxYHA2l?rK%*2_W5qt z8h<_#v!xd|gCsUb)<;|g*sdL#WnUFzpS*-t+Ue>9M@?wnt{UCrWS^<3PRskbo9t0- zkn2tnIlenNiEFgsH~(!)j^1j2(UkMj^Dol{n)VmJq7LPZi$pS_s7Z5j!2JA-`m<~_ z&D-L`H6lA{HW{Zeh1r1Q zWfBeQauUcucBJQ}yBuE&vl3``=JlsR5n{wI1Cr|+yn_E;TK#Jc8z>5}Gq=9Vj9?{7 zOwbgO64N!4K8Y=ZOEvqL9=WNuF4g;flFQ&9OJpg#46ZtsD&dMhWY} zJEX1_uz&lO;66GrkH2+Jmt-LN1hStax*6bvl>y=dACfXVAs`rpyAg%(VfVF88_2k$ zoWJZU4yE19dQ;f+@yuzx&%^&=oe6PabOQwU4&!O=Wt$qJPDxUE4vZ?g+V+V1dr5?tYhb6+m{h+n2jsg} zedRP+A{dj?C>t2WlM&=iN^r+yYF?zbT24bnZEa9DbDj&{wmj>``Dc;x(npsmJiz9_ zmHxRga0x@HpZrb{Xji_$T5I^;Ap`d-Unq56pYKqTVOd{<^7XkhQhulbyj_4^zxS63 zSM+oQAwXPJOM@Kqd#&wR;{EO#2J=bYe?`7S?B0v=g2QGfC+3SXaumr00s&4HH!h}V zcd9Dlxam4 zK5k~UYn!J~IiTQVvmmh9Km*@HTm2GM%g+@s@@eso-)?R7gJbp$mg7&>$BT4aj6JPY z-x;l4aqC3c`A6B;PZ-CbUKr!b0XhvP3cZ}xB(dKlU|I=d*TPA1^{*&|TV9sgN!DuO zU_P#^XT^9&dkkDnGkRPlBpgCacS+svY(QO|;g4c3E{CL)J?vH=f11rq$@GV8Z52#$ zu0qJclm$E>y1-8~ki0tbKiI+K<&xca6!hHSXF|ewWyUTaOXytfeddJChEKy7XIQCM zeuF9o+pugDY*#f7(AxffZ7z_Me9qQA7IrI1;4q2*$@x+X_MeI`PwEkTsYqlmQktIJ ze9;fJv>ik6p~Kp(ypPOEK0cb&Q_vXNnV!B9E6>Fh_OeREDvqb`nw0$34`$7=q+FX_5H}?XLPFM{@R__2qe9pE&m|sSUTXaD zmgjfc85zM}N-OZ3ZPbNh>kQr`#=h)Adw{xN{bgsmsB~U}gR=&)Ax&gvw<$uimL7RC zi)KXZXul}YzhAl0=p84hg{ato4DroX)`u2O_n%uRL*(D!ZnV)ph%MCPDskz}^EYHZ z%_}SXc4+ci7IYY9ccr?#-YqFEGd=vdjmvcQ`g!lc(@@y2AL`=|^=@OpFsQ^Bd>c{q zbOo;@EC_Ki5RF=jQ6149WeWzS>kPS zv#9*&WQ zH}g=^OBY&m8<&cDB)R?*Jz*6d28fSn+Qhb}wG#-{vVNKVhM9VsYw?$hwVBKKR`i$u z1i`jMtjQI`hk4m9%n;(rFPzg?rx#-{LQeJAYP~`vyA@sb1_ws(26y;TX6s&v=Z^hp z!;45~-a_b8X1@FhPz2y;-`u7obO08sLb^A3tRi!+p1*5SiRyy~p93fg@7&h~OJij* z4+I@kPk;HXCV(OffR+6GW=Me|bKf?B6YDb#dQn#J%Y z$^mA~MF}G;F=mMSO>x#9yHT^8SC7#rz=8D7lii@QS;+al&M_Z!NKL?5g0C<9WG*a7 zo^9$S(RU!&v+M!4W>&o;=>jH%&JKJLWh>>(WlnT8|Bg8Mbq(&Nfui%(6~|_#f<38Y zG}yt5x}LlL4_f&DUee6%zQ0}<$Sb|{0SJlwR#rq)w$T)S1vz`#P2OTUhN9L48-qn1 zqn%2#V2GWO9=rX&G-UlpRp~#lnf~YZNw30ZxK~QRPN?@L;+ladr~0?+b%|bonT`#( z{#%_o%HXKp4z=SvJc}Y-t2i`<&&dRsN!9^!-4Ct*#TowoOYgTr-?jswV^-^R2c%Au zJl9R~#q0EmMF_TKQkW-4%!+F+AJcJo`cJg%|L(D4gB0L`w||4Dx!+yQ_Y>w?>U}n+ zi%R$FrIU_Cz&mTJK6@75z5a0vf&%J!q7_Rta1-ZwVreOW{&IYwUY3C(AtO*^BqDUjL7> zlOtSvWZ$r8!(j7^GoAL_T3BFKde5GmPhlmQbUmTiw=;N%E34mHe@OH_>WW9V07!vT zQQVfJR0KP{piu!|B1e8gfq39GF0Va|7fRqMX?1g%vyb!Gdud@y<)ax=EQo1KO(kpS zeUH5ULRWeJxUvoSj|*gXl&XQd&Q{!!q%Tz;xFR&2;`NM^`rcDYl8H{$&9Q?k+-tA; zdNSLCtgsTO#V;9Ghkd}Y)ko={%WNT*9fB3stzw}B)6AsaYk4Z~%*HqKDSZIUpODf2E#_if?R+3uHa zea{KeKT*DanI^Jcxy>5npu4Xhwl zvP)Hif8g~|+;eWDazs-O!9+=+O8DuuXex{&G;;jHb-zbW&zn6)ew$ss zOJTJ}^np;SBXIKyXMPbUGpunm!-=}j=$YY55TD9J68 zN!)(+Hc6~l{l}W!aP>DiQRuqpP=K@Tk{ao2{3y-HQna5GWlK2*EBIr6gpR08_Z%Tl zkIT5(+fM9Y9-8F(J#T5qwiL6glV^$4e`MUYNoy)?FT>Bj_AH3FV zpcf+~P)l&MD2OCm?mmQrO;me@fjh)eVrU9y@8RS$>bqWKNio8szz-@3sc^lK({q0L zAj%FYX6kL?{Ksr2DDR=}+{}qdiTo**M3x@qwdmbc(q-SzVU@D9OPJ{mFGI3WU>4WR zEpv9;)rx$S(@bfukEeJ=E%RBP zFG9bSQP4R?pLL{uq6u}%k$c8C-v{G9kPyLo7uUfc_ZO*rcA?`~^pKZb6Xoq2LSZEHL)IBkyg82fus0s#L!%?DqSw(YU=@h#Q$Ajdu%NRh4oH)iKYu z_{ldfhP}R?FW{^DNBVo}!Gmvu9KbRa^VF|!keoKYLefok&Y^!BnI?#pKe_~adBb8c zh|p34AX#oM)jYG`*?KZ8pPhJ?p$~dfAhRjwjy{rUOhDDc9t6LKFu*wZVqnT0r~&$&+njU6wz9I5YP=R`rkZ2 zJPZbJTLLjRp(v$lfrEP6U#hX03f8kTWq!Z3!=9)`GG*I_zeDig!S9h*z7vx}2*~Mz z1?8#HOL}z@wM>s#r;k`ShnG0t;P$c6C|A@uE9)ufr~2xly#k#Ta;}HaN&O42PI#1q z)I^mtvYLGW+JHKM+67Z0JeCK!?s8-b>L%3(B^DCGdIq==wF!0VE1!4zjCESyB$npk z;!rL38FG}i#qbEEFyao$b}O#1B$^**v=!xi)@zo)B5qg^CHtc{W>9qE7hw&vQpJ?` z?sK*Wa|sJ57gafthyra2P-P%`-3ON5kDH&$)K?j2p#KD1a(G%=T8;gevIWoMG$ zWis!K%Z9)#Q1)eJGSTr{`GpG6@m;(!1_|Hmj$}v&i>r-bd*fh+W<^ue1jwKcTi#gn zvY#*WGxbB)+xC}_0zIYeM%!?mK(pvXCFyLlw51HsW72qKz3G#$Pg3HRa~B&z}C?3nKv3->0y_NM@2)*s}?q|5!ZgG zve$&?lEya$k%_NlWlRVGj=ksPw%tV%{ES)_kgup=QkQK<$0`b8sEV#O434^lAwMi% z0w(6)qU^+=Wm|(hJ+3N&xE5*2xmk>uoRsE)=Kf(6(b$~ggGb>M^hlDO(!<#l&u#M{ zt*yJK{DR>M;+~Rsg*5qU!PjVavY#)MAIX&dM)Fd+NGev7GA3E}{?xTCrS0k7B@m5gqqF(s$bKffE0_;q;O92AzN6o~U)^ zDn7H&fli~2i97f%R7}R8oJH6er@!KhIQd*v`7`m|3+6R(&NX4nk7^q}BvtFggzZ>q zyfvPCr1osWxy{yaQDpEv*3p=4oy*TvM8#^j>Oxf-Y(dtAuSqO{}#UP?qvn0izc0Dm8-XgZbf4a^NUzVeUOt~PN8zyE-}+I_gOI0(!! zcntHb%lysJnTI3a#t9v(O)Ot)>%(L|-#y)CAILdTc;>jy68B8`<7;1HQ^~D{dTSxbQqutnsfV}KO>9%0mV1=t(F=ECxcr5&KuyxmKHiyf z?%g^o?uNE~0pBhqec(uv*(dtrAi1)r|`%o-_JXv$@jb?B5fe6MoAdPK){n2a$FP9bTQMPCn)W^TCe7C_J#G zIYTo02)=4p5zvD`);mf|R@G9^3uyYW)Q7c51#PTWgpJ=)n%#S)yygo|1JdXP&t`~? z0}x}%w)(9aIgzx7tT^@NqGoUtWqBX?Y0pp;+UFG~mWc;pm4|Tn%Cj?ju)9SfpY(u#be0y@|~!q(MFSd)1(lk1pu5{^5kkMmWe$0Ww&cUDWMc z;wo4YVsB)+)OOiNwNpD`Nm_9Z_-59*?38Bdx3V2ATBCQsS}eGQwg}m{^y>r zB`BY^aS&g2jpd*65}r0+f?8;e34)q0CS3T-LP9x#?;?IqDrMl zUn*3sTum;$N) zgI>KIlO@gLxr3mfoXDTV>rQeUKSFDs)$C#f7YNBas@XK2@~ozWe`HKcAASP1P!skH zLADkKmKdAINHn?wiZT7NIK;Xquw<(T2_}Pws%%9!akGZG%ojTs8@+%GW)}6w&LXkc zAh)xfOZU=(GfEmVH>}6!gl`3<3|bHlXk0YE_<6X9fy>>p)T=$x9P0an;4hejLGKph zqd$S4AQJ9T3|AjQHXUI49VapO~imYqzQUd2LqVMmr>azy_y;+ zdEN6CMH-i1S?%bpqG^1FWHX{(t9=&2hN$y7074TNz(Dh@?kKmcoyX}U@=%cL>}V_6 z5yhB#jrNi1`4^r)Ok34WI54&t#xAC1R-bIJ z2l6i$!@1_Xxoz&nfT)W#e2@-69m0w0`VnxVS$q<4TB*OJvDqfdP0>qUj?G=IBhN3)J@_vDIPm|*o9X4(-L@Q2;WgYE70VTXsO4O{7(g^vl~>mBGJnm1_bV~vtQq_#Gb zbwSDZN>N5PQ?J=4P7=6T)}FugNUy3=OdA_;o0$dsFyt8RDCS0ho4eeW$)OHDnVA23 zIJcv5T2AfL0N!?HRifNxGL#{e7k-_llx0%@mr|VX)3tV4H@UW9f3@@H0Hqv1cosRN zsX|1zfw-aeROu&U_gr$BS)@3XNX9^uauL&peYbFiBlO#PTy^2WP?}*$!}&Y?Nz5Wa z*OZ~gCRM;lJZZNnI?LcU2gx2T6S(Av%l`Z;TO}g~VlUIbsfgtw*np|}1Q8oTQz2#R z63Oo#n8;=d%ouu_8%VtLVDwCQQR2KO)&?^xw%Z2JAdE=S^CBc4TJ>wvkDacvWe>Y- zT=QfVJx-I^^(HvE$o6>fiJ9KU;4O|nzWOEZUL(lAy^M<%O|zR4L@3rqDQ{G6>cgP!c^E%tillr?E!6HAsp_Eaj`ZEmatC1z6`H?T`Id zVZWCW`5|-PxX$k%!i;t4?-@LP;aX|!s*v{gj4tl2-BWg&&56G6uT1w*Ovv{rmr7tY z%BsnoZmMc*GR?4-vi|yq!DnAj7E^#U-|i(gxiE$_DKogy^FYN;s49M+AAj@LpfIel zKuVtN*iI(Rd(>PCP=n_Vp3iYXhSFq*8OnZ9OKV|1awpc$Ej+bqk;(CBzOfxI4_k$E zA}&#K3uuspAIiAvSYjeH83e7b67p>qbA0X2aWl-MtK@{9J;4|^*n*U%q=DY62h?zP zITHU&%+F=T-Ty#{`DF%q3p%X?uz4jrK{zk%V)fIC)_zPX4<<9MUh7s49}N;W%&^8M z0KHP{T{Xjeug289Ce5SPdwO-px}Hy^5;N9Hj9ea378Z>x@bDiS8*b-L?Gxnh)mA~a z51rK%7(nM)}sItL=x5V#3%DT;0cueqL$)Q zGzWcb^XDAS)y=I}=-T(ZRcaf1P5PXIU59v`yZ@kJX1vM*+x#S+^WDBNHwE*gc32U1 zFIBB~odkIA-g5eVyA-m>kx-xwr|P?aS!udMgK*v_>$t?qQ1uxXSy>Kd3~f*Aq~18J zo^$SY$}Wn)SEO8!LsMalOhO_M@Z_EX8ozy%_sv+M~MJ}^9^~w8hS9)@c6djpVCo8N?baf$Bf;*be zHe)MCt0q1|M}(xStNZThPY)2V^PSRfMrrINe{kZe11W5_io2i8#h*MS|J+~wDk$7U z4_!?T)J)6Qnm8~Y815B{mRJ3J4tBHyJijk&47{kkG)*XPX$SUh#uD6#iII3G=&1%r+dg-! zu1VaTvyDv+W3qNT47_2=uiH=w&&>sMccUj?06bXg>8I>)b6oFF&AnrEHe?^Rf{{!$ zW%Q$tBS6c6KT;tf@T#B}-VY9IUIW5kS_rtMY05u*6x?B>LgRHNtI;#n)rcH}09j=7 zFt;U3=j(#r^L!nbkwbxV2GZ92*RH+z-r-T@MY|j86TEP(zK8LX^ z3Vf+|fvY$Bhpc;iCx6P_v z#1*ephrGWl`(PwA+FoR4bj(7@nW{$f#5UB80?P{XpBf8gxVUGI@}P8f=c{Gcli+Kt zxw7WMKPShqjtl4jxi%wXJfmT;h%VQPyEok8<>L$b@c7pU-Mroe*vI*v(07a6(g$J& zz?DNfJMQAJqy_~b896TM#t{3dcsW1>u7GjQnKa(~6a~VE&SajdRYPQuYz%!o4 zO3BRr4Pvoan#kkjgc7%(P(?Nrjyt^@Zzkz7h)7VWjFdF zazMZD#^HCvvY_FghiGFHtKFif-FB*?K~yMX0L!U)g3&1|kr22h^sL7{uSK~hJfZ95%aXSs@BUW~nG{fZ(?xNK+K zgtSInp`cJC6TEXMLkJrEWVt;xrs@4Fg_Ys~zF%EIQAspu&D>3N1Hy!Q6WN}sf_7JD zbt4_E&f{@jExrS{fEUHLE6(T} zLXr|k9^}=tSK3(@OiGhz=oZ#M1vb3tZ%q%wUcYeReD=Fyj#C;sSBgz-e{O7o-!W9^ zxil8y3{`JQeBL*F-xfwypYDS3&3^wQucZu<$#$aF;=Cq4A2O zKg^H`B|F)lwbrwq68a{9?XArS|LsJc0@KeCXpMoE)T$i3rgWNQ@ktEp1s3n5oRA6` zPO4rj06X@suGB^zfBI=YbE`A>Ip-(Wey)Y0UDX=a0JYn5fbf&&BbdVxU>;ZGe3DdP zT9oa|EBx(hi{gKTms`hgn9@%{b>SjIa3g|DNG(q=%@WC7L{w#dR~yu-9~b{(L*!k} zP9JXNYr4~eZqDU86%@y6ZCqShz1^jITKr=T*3Afhs&gUCaoBvc#15l-Pw0`f2IFos zZS;~u!=sxL+>p0YTpo~#VWJh9;8at-Gh7exlw{YIIPiaU_P$!PH@uN;ya5Ro;-!K- zDdWx1vlYoJyAAidHmqdW9C>0o$0}>#?yqPu$BG$j^+NM^C04G)Ow9Qt(nZNRz_SrJ zSAy&0=ho{oEXUy_DNmgZ#K>D0euKp9cqaPZ>sQ|wqC0y(fZ7@qhg;B$w7c#^KSW1| zl{6)*WmVYNqNYUJv}ZVsbl=tpYd@W`JTEU{Yb8OH*|rR&%yUu2Q9%3?^iAh z{l8OO=}aAkFcguOjBhOA>?m4!EZ3p1xcYVL`d4z#~+U5Bt|@X7oh&j%#X!)=caO#4k1YwU{O=J;{d#EqECA zla-}D5u<8OLlXsR!8{}w1E#{0o~9}fNbkrNTO1d6TDHD&Nb6H#nBHCgu(D=3swA6L zftm#z>;SP@++T)sJZ+M8zv;unRX)~T37|2o``W1ood1;D@U$U9&rVH$a4-b&usy$? z@22W^v6jr>@kdFWa)}RuLXB|^eAQ&`J+@yJNFdE=MS$>Mui^iXlK%htE!Q?93GK2E zEycD@ygpji{)Wo`g3NjfzIqpBMpaj?p&HMv1+N}zh5@#75>_bP4d(xBFFX351(Ie$ zyvb>-3E;C+8E`{tmUrNizOPgDUxqq<(~@# zg-@qBEp3~Lzq+2d`YOw@^8f&_L$Y82pr|!u{={+2tg1~_WYwu9XOYeMqtSyzi$&b4 zwEB=xx`h0WhfMzDHL^LZ5kkHS9dunUII^HA9i!{Db7>%IZ|?Pwv)RIR!@H)8>%Ch+ zTUj{l)qRMR568rk!Ec~2pAP}_b2pFEUJlU2$f?AABf|^ON3I*GOjpYj7G>M5@!Plh zyy|ZB!Aes8GT1<;rrPmkrk`ZgSYNrgluso_taYmDd4d$~NJue4KCJpi-EwxQ8 zkNXRHGCt$pZ{a9KFN1kWSc%T)za&hwFis!uPpM0H{cZIM{44sD?>x)dWYRiQfTT)n zhVnd2=qK;iMQ>|fc>k>uS+@D2qMydi+HSgcdkSd&*tp^bpIoaA*quz6{vk&1eb^f{ za2u`w{K*g0xJ(P&l;h#85k-!rZjmYR7ki{6*EZn(y(s|YTqY-p1;?)d2x&M!<>06^~UCU9jM7(&4DL0#uv*rsZ)tFPxoz2^w$vR1TS?Q zwNl#PpNS>sVEt`E3}kEsO(I8U|LTy|W5kwHZyU3Tp4AFT<$9odIuHw%dW#~!s25`J z#h~ZLLT%LOB9#2J!L{ix0}p~xy$FU_RhEIPz89PPuD7^QKo?jlDpOG{iw27M^Hm`b z8P%Mprr}ql?J{0AE!-q?PVmhgUdZg_5=ANrSYDg9qNjee?Bm&K#x@RVunM)fV8(+O zv#0A95v#%0_y!Fx`!NYEXX-pajn*Xxwz2n;;}5w+ReC5R63^@mlL*Q0p&%7)?VP@vl*T~E?a+tAn6JA z<BbUXeVhElF`Hy`=^@fB79%x|ePuMfha~W~A@v}?X zTUz6N_=F6!F|-s~hDGh*QAv!gdbw$_TEl9Z*~k8c-#3G&yLj(ggX8k$qRFhSt`lNJ zNJ|Mbo;v2|tv4#~D=y3;SlBwt`DG3y62%IxSilM(?Lh2skpA_p$KzhLDH)dB&y+)N z_4hx-v7#*mkbxKo+=9#)(h*z_BJ%F^$bad~xSN@`8QJv9Ql@D$3d*S_Ln+1+6=M;& zkT8X?GY!A@8FYq4+B7z3oQS8ND?`>8X`*68?T;9>6_ub`rrDO?&ILhsX4|y3C&yna zK&-1cgVCQ1%s8;Hu)r31V8OLnK2?W`4M^f^UE4+m9;=+ zIzY4fI)A4)q=TC{i_=lyZ!51zfsAtmfs7vyn{yWK-8mL(MexQCK`uZ-C2f*l9?2E{ zvD`bnFfL21n_`h(V(xuNGPw~f7)J2xRdBQS(>{W%`51=sjm@`=ldUE!Lbh$fZQkm% zoH(DiUy_cwM)fwNmASyuFZKrIY{grO-i}?+BRDy(6I&c>^#O$FRY@ zsCWwWaV0rB1ew=H*bRKdy?vR~R-b?Ib)?{^-*YS`JgTNSr`$z;fiTx* zQdMI_TRV7{cJk|mfs=7pzG$7xWJvwWz+kAJ^pF9_BL8!W&P1Rr6G|FgPr&7d!Q!i+ z2?}iME<*M0!#%_6?IY$hB^$Ha2TxT?o-}FP+AV;PjUiLWIqlEji>sir<)(&*tQ`2Y zg!t`Mo+KFPWkuBN+>4a56QvHK(Wb{%re_k--rXM2Uscd2fPxHxI0DTUq6aKO0a!zk z!Wcz_=pg*FgFN*|lKtk(*8_qva>ZcVh3}^##z$~GG;Uv_R?6v0^YKqo72n2MI>U`2 zlS@wZ-wm&~+BCgzd8{%5)#I^#1)2L`@jnxt`|J$ zhEgSE2NgPn$@ovM#U7V&wi14@;N^X+2TOiW5QJnZL;lM^KR;+gCid~OoFaUZ#yZs2 zBt4fw`ia-RU*Op~);IWJq72ZD(e(4rtpWS*-%226Q_bo@HQgd7wjM-y6Uo$|>PtUg zhgf&tqX2L|cx4Tm4?Xvn!4)!T`rtSPE?P(p?BMgm{7Qqp|NUYmrt2>Q2b;T-W1fg? z+kWEYNKnUYr-JEK2~cY4DHKsA9BcEh0yKy*HQj!*QoBjQ#S<6~7@{eYQy= zsp8kC^bao%0rvu73WOj=;ySuPP3Cmz$~F`nJBaVOP;6e#mICZdd<2^bSA_uE~e{P*EQ!+Gc|!`CO4pO?&*T zF?Xa03}@(+nb>V)(CexiSN)6gd*R193J_F0n4jEM9QcZWy$Dm8>iiWjbMiOfOR*SB zMWqQHJEVfB6!LNtno0W;O`MG5Hx%qfvGj-8U}9`x3t}+t!ekzab|p8>FyON?Sv9|a zE=%}aLPKW#Q9PWj5sj#fm-1N9a2$TO^%aVlICTnDqOhb=Sy2pK>*&C(m$(;LSyk+8 z%sbX610rG8`>jGLn7E8ndsTF%Z3+-da|{TW9MD|U?e?wbe{jKZbDQhE(zww_CWARi zpMFh0|NO=V)c`jJsGX-f|0NS8dV7l`acKO&bs;6uxQFd#rcz&@YP~eOK=?J5x}>M~ zW6=^h*H=Nn2b#;Y6)eXqjP6>bsIHfs%2jvqkB8o(<+#m4Sc_a}oPZolnci;#sNR|l z*;u%xOf=&?oGhHayfG@5JI+v6{O;C~mi6o5kd`-4%*Dc`kE90|`$`3rHA{w3{7Q|R z{@h+;fRqLPD%;*XHLY-<@6D8(>hb+5mr&vn7IQq-*e5icJTeo&l;j>Ojp^P=mF2IJBGrIGfji<}G zYuFT5AUL3f6_o(t0_J;YFoLV0iVDNQ%@GMs8F?0r)eii>qn>_t6t=cwXTXFM`MvR0 zEBT3Vv-d(g?+=PRt2M;_!XC-hm50}_R)J-{{-%uW*>TpWX+@V%bnnXeV* zD;b+fc=N)>81+TwkxR*!-khTlj=|=p+N#?K2;hV%!xOSe(=DPY2DbB!Wx&7Q$Gjoc zZT^&ootJ}^EMSRkRi7m3!qlkoMyac0ns@1E*&8j_?7kif+dSQ8Fx4`a82U9FX0_XA z-JE@u=qH-91gU7MqtnkHTI`h$Z0>-rFe ziatv!QaE>|e)Q_F_3&)_ypHwl=*y9%bgQ9;?OKd3*_FnjK`3cIQ$g7bu7B>HNrhTm zCyIt@-ij1ixXFF+vt~0Xw7qTB6Cnb;iJDZ7hu56NI+B7$?$Mfcu3ZK_<1&|_ib7hL zt0PAc@*}SUM0zSGP!RpNBErb$vi@S^ToU?Xk*BYHLWh!^gQ@ePJn0;`p! z2Nerq9Ak$N-mFI8Tjb1J2eAXz0Kq*A#)`ka3!#dz2DzTrXvTBQh`#E!GMBbk`B{7u zd1@71hFo`=e>I0i%?kWVcrqy2-Ey~~3Wu5D{LT}73lFg>k9{y%i7-bD`|LMkIcczQ znjzU_TAiS80xOnsjsabHV8%iz^sC{eIjta3kaE}dl3-IS<^ebp(WzJXVbze-;ugb` zNU#A}L*}X$zAq=Qk^+t(V@XU%N(W&tglNb~-PSJ~^@t>Hbgya#m`JQtZ`VMT>z@U^2BW>0z z=XYJ}EIbkGb`b1ati1-6q;6|aN?IYGg+%IxUVm^|U)cWoKv!1e<=d$$APjEbTYdsi z651hIs2lUdGy7pOB`%WAq`B{SLvcyFxsrHqzvK2CvaLU%A4Em9awEA)f|G4HAd@a4 zulVmPx3{?xvb(1j=%D9Rs}3TJyc{l#tf-e|?u>r1ywE{b27fCMk|ys5R6zI@W68jT zLUNldz{amyYePB~w9zIZ+^x(Adk-ID3T>)C@Oj01FPeUX!~& z6f0nyinvGG8ecJOc1yQMpFv3A;L;=MK^}GDy@g|>`jD-@7U0gm&JN*Srx_7rbCu9V zGgB$*&C?IJI^SR3>hD+e8DHQ0EK2qaX)$C5K4Z+RdXy;C!Uvw(!Xa^A4?tF6q6OPo zN}h}s&4*m7cv^-su0t6hWpFeZjH%Wzvb%t}zQ z_QRu!UxuqX9W2&{X$V;R#w+jldcOa`jCP^s%)jMxC9!xH!(y9bt<2YCJ3MXoc#nH& zPURm`)2o-TvS0z4#?a0RMuGN%V*7o|sdQCm__^@gr#$<&KYZS-pt`1IhiUhKl_>OB zVhK0kx@th)#l$+>TKAS~Uo+x&Ip|Z}DJeooAclOPq%+=gn;~F<0oy^fyMm*o_-h}b z7YJt8d#A0{My1Z&z#AXlIsOJd16QG1XG9t{j`#aHd2%`yh))kxned|^L4Mx%@`_G3 zmh{QsO7@J%Vqt3T88nAs4>#!s`-cX(QznnGx85Rsiyl-e1=K-!v2&Sd0YIg3>Ipz+ z!k%?-aB?T;yixfSq}U~}#h~_mf6fMb{um3Kt+o#OS#$uwW$o!%O77g)P^N?AmLAE> zoq2&^7o~vU{~!4N@mR9ynknD{=wfsFgmdvq49G3f7`QLFXxRgd<9J3e^B=y1M)YSW zFZkMu((8_U!_F@Uvd<90^$oUM#V;fKH4T)!7RD=SCy&t>9vF7-D-}8i3hxpMA^y`w-b~uGK+1dJ0VK}gyD&T<74<&B2N9CnC0HIh z8Y{;r6ipIe>CzQw9vdP{Auf0h{v@6$pX1|!_&5F^gFnyUQwV={fH|RA_Eg0B! zok#}2zGMs+DoiPrwVE3Fp~z~|!r|wv!EY=5CvT$8&6`zbb1JJ&>NY3MWM$(68!0x=%Yfn$TBTGo~47%XTIjW4Uqs$C<>o+T?QwMpKgk(l$|Q z)&}SYFgW7S_P73%&pV83l^D0#KZpXZNJ0J7+MWBxl zxKG_e@^ld_d5GN6FsUKM81G=SkNAn3n_V;~Rw9VT4w|>~_eiYxLo@#2X!7{y#jfQC zMrQMF7gE4+C8dUW2^D@QO>z#6?MJ)$c!nY$nnzjKLMT{8hg7vwtk;Sq zYxSdiOcJ=3LWp;TO>16r5zgw|Kia%ncJRbw=*%-rpeyn1;Lf(O7yJG6_yi6PD3<9`k$`I)UL8oS6@=irCEKOT&9ep zC*n}WyTwgkQn0d{y}lQdk4)jukAGrVVX-X;S&Hi?HL-#}KA4mbKc2tHn3SA-E-kDs zjCrObu&wus7tgMyOpzgiK9;~$i{J)S_qn>r*KbhIs=_JG8=kzvkUCu zjBuj5=ctp7iIoLpj(NsV(gs}i?ci$6)KoVqr#G+VQVhQLLU>X-se|?mWB9d@dRH-uxp5!F0e7Y75yny| z%+E$$iXi3dV||t;PGPU3K+1x&;BQ|}Fw=wrLO-FNP((nNAP%fiN@Aiy)D4= zUZijAJeUHK5gOsDDWMcJ{$*gIF%f{T4hWVpY-PQ^``dB8L0z@ZqFKWlZqvnSOdxvG zvxo)Kh(24+8khjk46$KJu0r^^l_Z7yga={O+hWmAbEUeDX0Q$FVxr{Rx>WrM`sp?ftg_n@$kk^21q8;FYMxUfh137UsM)jI=KjwOZolQ1X>nE&~#UOGrJpqi& zI4qZRy)p5eLW=pe-e_?K-}ln6RNhR(a*+s_U*;R7^n8StQ9}j97{S2eWK1>;f%Cc^ zY5cim_2+$ION)6$ZhZfGH+)%LEwAT9Y6_4V;Z7gm>kq8gq@ddlms`kz>J69=&cAgR z+owKm^Kz8RCx;)gJ=s6+E2IF;t_9NTIT5{B9yo~N)S^;;cAv-?u(LR7B-NTRCVtJ# z{gNoqtvoKqYMEP}KhkdEv67((1rhzU&Bz^LC1-jUN+f1+T~gm;6PaHB=8E(0T6uvf zDRKf|Y49_&#Gs$l$DUZKiOY`06fS-n(ka^nvC?NSSB~7NzHODJ2|^5`9%I85Qrr@~ zlz^_XzKYp`#ptHVI-y;P6@coW(@zMutXJLZHNK~PA!E~~p*3vAtfQVa_gEs8^8EnxJ9vWvyyU+zP7xrUF5Fw^t&*)5WPr~tNrQ%nwcWs>@kMU**r!iqY>9-2% zqi6E5rRQlSp4W6%aYA);)#a8AupP9)pE~A|>#Il_d7t;Y0(?M*kPhY~{FKxKiLCy` zt}^A!PfLS+eLsDXe^~dPuxFD@E!ZA5rikuoFmS@(czk#${IRaUd+!md@4Qm* zjw>(Rpnd@UOLTlvSn@JFjdTanjTMK?W#BKw}XPc2nuTp3o|i0 zF^k$yq}852{L6rT^OJW=KBZ^8qzfxzvvx3aoUX=1U;a?>K<;Qv8bE~ObKPgHmwX<+z%E>0- za<&<;Otk$KqywcuqB#!uvQ9MSaQ}@$p3RQ!<&*d{mt)@KU*ZqU7 z)bjQZoCqbs5LUQ@wPMiR3G9t8ZIa2_PEW+#ld@=x{4Ntk6M@p@^A z+VGFa%p8sG?V|k=7huaRY_Pid@08V9smX=e7nZug8Z@ z%ghz^4UeO#4>2&U3(PR-EyeE+#2a*G_YGR^|I6~*C=cY31c$31CE$DN>&#DEJ7e2MUYCFQA(6ru0*B0jA`*mzhvQ+SdiPudlHgFMI!B2$ zbvzl)ONO>VgYi5HBz~hL2+4jPS|0!EN{kG&J7z!$95oJ?nP-ungHBjv^`+dbpA2LW zo_E8qN^JcgvW9ya^1w2VOh&^GnzbVD-*|RDGYTCf;!t|K+~OcO8JQCpB%5G7%~wK* zv~^{5@~W-B@GQ+GZ9e!kUpl9PQwfR1V0HiU_5#o)VIsACeWhs44yfOpGIQl8W;BQr zk=BjdRBvNsx#G7K(P(7Dd5-N2U!^QW5wN1ZMKhdBVI<_VVyTbHx1};Iu2;tmdpNr; zelPiBZ_Xwa6#`sbpRLNMk(gO!~p|p6W$SZ*Ad+!!%J^W z6*`VW6RKKGfkTHK7CgA&vM@vvP1@kESQ1_$wZ8py5i4bS|20BPZ}CIP!g5d7R9&&E z-7F^TI1a-F1nqXTqb~lza1GmxfV(^ed%GgsIE_-;!e}?NP}Zv;+%N$g`C%T#$zNAl zHeP;t`3Fk}JEDjfG z><^`^CiU(q1|L-@N-k2D$1C(*$eI4dmpW4#@8qA#_&M%zEay>MIs8P|`Uqnk17VwO z;J&jfUM>ORnYNE~eJOppq16a26GORt- z-tRfPUcvLpnhGIUYUolPVMJ?^pABsmZD{7>%I;IN2%R!(9S<*oa;%g`Xr`2h+gcPz zv!(61azA7K)N2=h)p-k7;;1rno54>&pAo8LbT~<5e3r2$oOl`Y>OG~eTUT&j2+5Zg zMgUaFY+{lB^w(}RTS5#3)lO>r*Tjm)hZSvjG--Br**T>&RJnCe! zuYPg@d{DSRVtYSL_XqRRY=^9?ew{qKG_$d0C&f>IwWjo<) zD$9OMXN|@YnXbiMd^T9i_WVh1R{Dz~zBeBw7W#3l9V)H~b_7*f6{p}gNqErBFFDK0 z)om)Vl|dafG=M57hwDEwgdIBFXf?XKpzXNBvIhft()r1fm3cZ-%e#HhFYgw)`7@Hs z>N^&BnjS6ILOIj&Pj38It0L`R@JhY92>w@l)-}Hgg%qi&l_fc(A{Q-vfN?D(6qtPg zy1@Do`F+bgvV$LVYHF=km)<-mQW}?DQyKh3YM~l-KF{k6*qf0T)HXhWIZyAh;-S`& zvzLiyI@;beP!q^Ai$gmTFYSYZLVt-^w1^m_Ix+TnyN%;2w3VW_NceRHCvTe%^CjVU zo}J^1dk)LV#@mw8*S9k5BsZ6AG=jy{ql+E%aan^FRKQ&|FNX#BvRmG?8K-yTTV*M??Ma%~1N5>hSG8M3DrVUp>dhygJL+N+O zxz!F-EpJkN8-`~MTNd?$a96brU*XpmN%*X6DW4k@**0xL3OJ!7`r+!mnpM+9Quw24 zGb-a=2h{|7fquhcrei(~d`;~0+gMZjWV~YJ2A_i<>#S7t*2zq_z^KtJ1=~o&0rW}w z0JKc2;7AT;F=yI=J@14Alnj6g!Bh|P3?J;JEDoxad~+l2!1gUIOSUXSgJBs_u%Sg+#P@0q>3S{{GG2+1u28 z^7foT!MtG*U1mg0f$;gR7iV>4)%P5n%$o@3cTZ(zG#@wa_WG4j_S?{vV(ZIuuIFi% z_0%o6T^4m+bIIWeW*d~qnzC3gQu_7T!Sf&DeK*Eh2GN)LkL=+dm6X1mc_@<;V@prI zyyT%@jf3;0<}{Wt+1GOFF04LBzI#4YG!O`lubnL*&$oiu2;@C~!e-eTkMV~S8VBz` zMNN=ywh6=_Z0SPoLou#zR7Jw^+~ufHI`?rA<~m${2z+M-cDscxG)x@dERJyqDr8x- zC~d6lq*dBkF>G$z)(h`N9%s_8I_xKLp%J7ooOcw!FX(6alPb!m)Y7#OoYAk8h82KdY^<_ zB+l%pq4sj2%rNX6s3{T5M0NCqoR=LHsrY3Yv$}-S`pPtBVmT?fYOuZXLZ;DhqFE*k zfd1;;0FN}x)!3%NKeyFwvNR?6aa&s&!5aL|@0B<;C;NzgH)E=&3vCc%kW$h9^+h6- z@lPt}sC4}^rBIJwA8uy-2nkraebjbBz58Y0s`3m}oj!u=XcnO!Q$EskD*V;7JqZm$ zQ`$FCoF@AT+_GV!xE~2mJ(MMe?-bU52EQZc1YtyJx2aX+6*ZosKeJ%8nSXGg$i}$2 z$Js}jVWo32UnxTGFf(-X!`rQ?oYXZUe=u3AXub!^wZg|;bowwr-S(L=L5nN5{}U`}q;%ih}NEZ_aCXpEZp(*P3~hGSkLC@vxAUuhAB~3ez4JLw%cQiXUW#q!o2Q-^pCeCM86GDk z=r0*mCillKDKhq#@nehhq&U@7(^ly>$AI~e8Rj#%S)p%ElyI`Q=KUZVS9$HkYHRrM z%j06q37At0_7Z}Xc8OA)Dc^%-g)6s>?$)~C-5rOk`4P^4vR+7oUyC2dSS>F~2W8tQ zWvA`=q~^=#hJv3C-M8eeW5m4=#3ywo$ydc&yzEkJzbSHGN7c}1m31g>AXt2sW$NUY zmeZG5Ow*XSK03Fl^RD2Er|_cXsjqR(^uDZ)1$_pej*yC8Q)sw^6n|5ERX|hg{?>#! zcZ{9_MD4xboc~9N(%IUE+XQ;zycEa?NDj9PX~LW=A4xXQc{|YWQN^y^Agn`4Xl!5h z65K=SOk}>Cvd5M+)Vl(X(szBfUcN8IO{fbz@NtfJJ}4R5p~OcMT_=|b^=M}L)m7w$ z9l`U2^5om1KT}urD!(jd-csWKz8u^kKO3s&KDQZ(XQo+`$M+&WH{-c>jprkcjbp|L zn|uzIB|mBpglD(l^U)D+$g(d$?a8j}Ft4Sa=A`{kg=$x}Ih=n`c)OxRI>&%6Vqa zF~ZsA%0~Eo^@8nv> zi!K}1-dQMIhx-zbYCQTQ4tJt)2T>k>L?aK~1FHK8&>#@mq@ROoY(;G&=-s{4s^G)| z;!D!{AufXY)>1_gOhdmt8ZR?C%3TgIUM-Yu?S&bo4Jn)CS*T2~C`bWw4XV{&XS}?1R+@x~a6awyGo7&J7e9l!qI%8f^Zj zOU*@F2IdAwNrk%>^Q_Ii(#;^{jh%vTX-|3W5{o|ygZBHE>`!g0&H)XN5dnpwvkzC0 zt`Sv3T^`Y)@$a9=yVtu7uvr0nRvt4T!E9EAVw$L!=q|9aM~S%yy3^@K_Zj;#Be1LR z=y;OqR@71g0}orKuEgwZT{s!p)~f|bh&4q1tcrN%os*AfrCO5*5|8v` zn^#f6YP$2REPqtE3aE-ZnMaDc<-3=aOK_W1(f!sECPy?QYs<{dSu;--l@HQ3i5)#k z-@V@CdDWWsowEr3Pa>Yy7D22}X^<8p*3T&0X^nr@~~bY*eaqfCAQ|ntT1*#pH02zKo zZki7$xO6NjwHV@z=i@dK(hz<7LYz?JXq>4NHCnIi1unE z=NGWG!C5#InOt4!<*RwReG;BIFA#o!oo5C9$w-_xNnLb2G)tB$v<}&OhY8iZtQ9J; zF1787NB0FsT-&ij(N0rer{1LgAojD-REAwPJq49}2ckgLO3K!#v3ekmi3-^0UZD9p z8#l+7Qhm1i+RsT7zrN`g>&5zwrp?BcRo?IZTK zno9hld>6_nJoijV`AL&s|HBP9D|x>atTr+~v~xr4;LXAfVUfp-?i5pkP#xK{&C6UY z{D=M35$7jFWz!`SmXT9e-XEgf+Gn${%;?&4LRG*Qgnu?cuEVZ3B>iRBldUbMx_eRp?IOS7 zbB`Z+xC}yuOx63=={GLBy?6b!)3?1FksMUOc!fh=i`?6iS;e00g>su1>^=vN`tG-x z%e9YQXPd)c1h_)w39T&rmNkioQ5q@4Rm`{nP$=6q1{V@tz5qHBIzMT?1lY8iw{cwl9^j9CM!Tz7ft^Y(e zy>V(ANk5NeO5PKrxZmiH_06mS$chGG$RgzReLmZCCkF?lr?ZIHI047>{G9HCw?=zP z8WsMGf;Ud>hU^#Hdo^_Zz(p zGmA!|_1{a1+7n~ug{%dxKGrfo)a3tpgBnC#SW6Y5v|LXte4(C8wc5XjyhFOc6eHXP zuAqdhZ;O50fdn{$Cj?VAD-0Up1Xv^m@TDzsssc_%pG7p%GeKg@@Haj zfxALVY7hFthwV$wA`z9;=&9@li3;%MSyQtSZF0Fa|&K~u@|jKG>Z z#2nO&4lZ!c{1cD+ii^s>7REPk<{SLXeldD5NntC_`goRqQGgPDUIBBN_Rx^WUWorV zl?It(@^m(}q^u*Z#54*H8rqeguunYr^;2=#<)pZ4&NNmKYl{c2bwzNQcMcFRQwcsZ zP|s2bb>KGkD^+?1*RtXzLK6}1>U368<4Pk3KMxx(V7ZV@(ntsV8LFxYB_uR`Xi&Z* zl6{sLt6~u-{E1(&B#+;HTmeUK2bBSb)XruE9ZVHHdN4^%HlPTYzr8Odp~X?q1L~2F zc{o=0jbzM=f{6Y8pm3AhC#>&Kus@j24_Bks0RkYNghs$Qz@^Haz^}?!K1Nb7jh2x% z;lCeDB;`CwZU>#5;6<*qV7E|7*Ul z&T{tEgj`zHeLwL!v)q-MHPCtFYy4R&`tKyuc5Ebqoq~?=^i$Pnu;1}jjJoVR_xz1w zJ6HE_d>z;p$oSb509@hGdw-}cWE2pba-)RFY$YM}V$#xL>e$vmm*=|#1HCqp@J7XT z|NYxjIb1SYcUGgS9#L~Bdd=osC4m?g`0Y{JRpL>>a^m+U(e85=G7D2}Y7j9I?nBdI zGz(ZBc0|-K`VA@X^Y?QiLPAXUlConL9hSQJ6G!4M&D;;Gyx+&D>O0ytr6FG7G!1dZ z<8JR2KBtKiV+l^!5I%uDIg8{@qNzpVMj1v%c_2D;giC;<`p`5A?pzH74IRNm(ZTY9 zO6>^IQTZaiv2MH(s<*tl-dXy@QmyziwX=JLIQfRbxFbhu$vo1ZgkYtbc7V?fVFdAi zxZkgOkyjpf@HI@m_$hgBCNll$de>sVSUBab@LoH$qqs79Zj+muYftBkH45-OO6F&F zdnY`r^lKu#zx>Ud`|h9j6}=VOsz=&paE|IxP#cIv%?%Q!;CG*>g$;00er;SAE&0Cm z=HXdGAgmEyrho26{z;nRYgid){&3kRvwN>eb;FU^A}<~Y3(XKQU?JK_elfg;?l#ArP9R_3k8%uQUo9pATF zlwRAE3TMeNc~;1)Xs8oAhx!I{=I!L#-I8$@4Q8XO|z7WzCAO56!{oqqf5bn5X&e znpVs?>C;Yk)}5_e>dzER%u>rdq2HfoobLQ3p?Y~Bvf8R6 z>%G-2ssn|Cus?w%sFC}!2zb(ET8}G+jKSSW`~BGq;i9OLOF{KA|kF9_HPJk92PrZ$u*?X?hfdqrJ)7=H@lSRzF4 zPi3XZ1lOO+Sy}TXhLJ@5?ypW8${XRr7{B^so)ki{k3d%PG-XP{le*(1@KxG1SH}KA zJnXYY)p*Vr@&4e1q^i)1{OcTEeKpL%;P3IL29UP>6MC)4a@PP4ynut1bm<^zm&H;4 zQj3V3q2v?EYevE(8$#*XyWqEbCGi+Bm|Z*cyqZlB?JDJL#->=1f_NH?kl6dPI-{+i7=^lyg?QfGjy zE&1cPlKQ)Dc32{!PH=}OM(Rg*8=ndHL0rO1O_b|-Ki?(nTcj;E9Kk*cv2|sE?VC|f zo78FsrwEvumMO)tU)Jhi^wzHi2FV-_!sqZ^=1^a1dd ziu|6`rvUd_s@6OC(AEn6dCoV*9g1@J=K!_7wZzTN2XWQKMuC#Ir*} zgkTZxm-rMPmJbK!mE6}yfu!c<@V$%wBPN^4d(Aqm>x=WcF3$0!E0s}(;!&rZ<0KwJ zTOa7n+5Iot-aH)2|NR@*N2RRUvStb;A<34=d`gxQLQ%vdWoNQwWXu%Vw-Aa@*@?+I z)|sr6B>OrT#$JXQ%ea`O`}*9^aUb{ZKJM@H{oT*=JMRA+7yg;+J?Hy8U*~JVFtsx$ z(Hww}y-B(_%)IVw+&9ZbjOesg&e~JpTI|1ojQ#`KGVq^KGYX;8@B%^3W!MWphZ`jb zmTRlY4)*#(ed-<2ZEtT|@?(&fQTcy|m(f19#mYWE6koFRg)P%gNAnxY_%pf%emlye zNho79vz_^q983Sn@vl%G%yI~uN2jEBE;pWZgn2*jr}dqxq4kB^Mt4zten}DpFpXS$ z@P)oFAj){$P8K-PT8PN~JF?GuSn7Kf{?%ULnTLL#CH!k!%2a2uFSp@wFc8v>Wh#*s z`yar5P^7=Tl^WT%d9&j#T|J;qZvuVZvgSyy9uBQhkkMY0SNCD$$;)GNMU)9LpRG+D zbtfrTVVqKsmUBigIQ|m62b%32J=Mqi`JMBu>)Os7EDm+-Se=TdI5^#U?-q*xf=aT$ zq=+yd(7Gd!>H`-Bt)0@3!V7=isylD=*r{F>R)9qLUt&458P~py3-oaX+YcW>q%k$m zB4r{UPN`pxSJkC6^KE;Aa;et6uCrb<=cw>@XcYamr`62m7Wzkx_*fdVL8}CN1&TYj z8I7(s6cA&&prAmK1D<9PT?-ZV$kLxEb1(~nrZ)-q*89t?UEQ_ym*#H8cw3_b>xJ$>?{*`mTfCE&TNLQEkZyx;^7dB!wYLZF54D%?E?{VsD!Yr6i6 zUifvKutu%^Cjd&#`id70OrpR=fYHs65Y51>n_J9Rud&y_aE)i9y&zI13Yd{!jWSi{ z6*WU8LsIDU456b5vGb>c6c3|zy@H1mdsU{-%iapv? zygv^&g!fFx$nlU4u8VF>_fhVG_T`u^i(`nP*+5Wmt+4^=@%25Ns#*3xJeW~P+E6N@ z&WHDjwrs2GmjiON`T2}4kOJtDqXtk44ajnN9vt`7C(rf5W#hk?ym@*RGnlPJ&!gq! z%{G-?LLLJBi`&e-9(xKUqsZ=e`P=-z`-ioqKIeZQ=*0xZsA139J#}~?=976)fi1jq z!ukenq+sWJ)9S7we^))US)kUQFLkgId6fzp6TQO2p*W%s+I3odUaOu$4{N87ug~g;TRl(4avg4g-2&{%q=bF_rg<~fxm2R@+=_h4otVc4m(S`T zcF!&Qs7I7!w4H7kVjcmK7y`d!cr2noFAAiLx6kKr3;qV5l+aJkJ;4Ht%$bQ*$8c)T z9V#?lbK0O2TCM$+Wu!zor=6(i(jq%*k|n2-n-Rj_e&zY_wm=QC8$5XP#+?Fj8Fs3z zFmd3~m=T^jven6ZA@9m~ic^vzQ6>4?C7F>nAd2n-WX)ot8x>vzwjB11>ka&rIP86{ zV#s%_ZfddmnsP1}v^ht!pj*4A-=vvdMW&W|T}f^_{sc}Fku|^DVNZ(D zSBaDgVSJm5>cJi~s%&ez?caSR7;|=LUB43z_gh^G7RpOw(}&($$5vH-+|Q=%k|_zf zFO~;2ND+q#H-@)=JBhAQz3)sNHX-9cfFulxsJ=(F4M&~!u*ID`Y08?bb=6z-@S{wPxApbO!4%kV zc6v{OZ)$83T8C~UMa%HB(gGZ8%||31&JfLqKDAs&eY*A`DR9d3j8{(4LeSSc!5}7l zLwG|9AV3lv0nlbh2(X`r#qD5tf7xEXvhNWz5L5od?Fn(ID!GCCz4Tp?V8I;wrpWZw zN#pudWTLr4oN&sGU*=|LGn5!B3hMG37D1PE0EghuwFAr@1q^P`B8)3c-Xbt6i#RfM z`UA~O+Xq^vcdE?f*K-uc` zHdbVBL&1B{6T>|LSj?N}IXk_C`@-Ru4={C8eV{bbC?159fHQBN7J)$^^W8cshlpC} z7J37IAEaT377pwL?8NGCe5%y`H|*5^rF(#C;AhK)92C~<$(mR%`ONe;XJks~1t-xY zC-gaXXtNaKI^wW{?i@Z`UlE}ah~_~^N_D(D73jYHxH0JISN#!AU#Z9q)Kv26a)A(5 zVJ#6JGpW7SSv)zxr*1al+=Q*gqW7G=8ed)bluCLz*^B}2g*8%{JL+%^kT+*lRofHMe+jlr{0;U+8B7&=}F*|>>x}Z6I)swg1_+UgD&ZyNziByUC zj+qpmcf>NTA??RdDu{54+QIdm20>h}TYci$`M;wJa9cQzDN46~_F<#n&K*h=$hhlW zs##Jeu?ZqJaj#}FF)dgoyBJoCsOjm9Z+sBpbCg367=6P&?dMvpzc?fhl+5-`M$x^% z{Qz-Vu4~ezq&Qpb*2uQ_byHu_eyxh?2yWiwV6fF+4|m*~wV0@O0HPS??0!e#qEBJ=BxxM)rtkG*p%-hE?IfDCW%o0MxM)d{><(w81% z2Icb<46HxmSJ?)>ViTn*H}`OUCC^swzBqUH1@SkEkM#wtc>+WWI~srXXTa8ESmOkj zk^lK9SI(N0mVt5Cgo2>gjq@L7eRs+t7w$OzhJp>2E0o9s3g2GYZOma}aKb?4H=KwlVHG!!kGRLHOEYU9d@knjrTQJ zJ3A%v60=0B6#oNriWpya=izYZhr$icRSTkaC#*JOZH#8z2IB$!#9fvttihtblWO`FGiHX&N&~v>g>!r7&svm ztW3c|XQo0+rsF0$`hW}uH{d^S5t-En69bK8i#qHc*yeiI)@dLAV#rxqb+XOg=V|GJ zU&t6)VeR4!Kj6Ty2ijq@$m9~BMeoRNot^g&!5jV>>I9`pL*-~_3wPCd)DmL#w!8Q^ z*m{P&wqxF+85Mx?`goX7Ah0gg!4vFRTWGfN%oBOQ zO~##JJ&v)X<)Mkkb961L(goffJLX>-`*Q0NmzySR4)RLRkiR7l*k{ZwZX_~Qy`Md* zuTE5aC3dUS;JQnUl#>J(we0p|2gubaggRNEEBiRu20-|sE)$<|Jpomx>1m$Nc8~X$ zJ#O2&DIqWK+qdW#LuG@0=R;@=6jW&3Dj4# zc!3v2&)u44hBOSyS5qU(S#|F-)XR+N?|eij>^RzYqnrMAm45PKryLfWTdmz?5$?!C z1=r&zSIi1mW;Db5zN9|&`xv>C_!K(w?VG_XpJ%zZ|4ykuC9->S>ngJ6y_Glr(U%PG7PCTW`;@ zF||H9X8!|RE_Z643z?oKSrRh9*Aw&q)~V04&}b0Y{#iaUquE0qZvQB_O;^uh(hzEL+iS-mEH2Tcsr4KrGYY6M!|N zfi*)^By%6S7JWGTR?iL_>35Ln^JF&_&jND zdb^%-|NXc1P}55J;SbOt^lUb%68p7Jj44_Pw9~Y&MRi`zY4Ck|GIC4B+gr4`oS&qy z-lX={*J)`-oqLY#(|1735U@z~5J}#Z7%HhN%6q<)X=x|BB+Iq<;5_ zgVt)+hlH&?$;A#dw_`+mfFF({N2g{&ui|A{ONDd^iAPFm^dFj2>-T@fz4^e=s;0RmQ#qcMP}#Gjh&R5+^@Iujcl!l*Yhc zJMq1?y#4QzNFjd)|1%J-*!5whj?W8!Gas%#JV&}#YFCDqm)&zNxj8+N^xIMP4@W2}>c0bVRsZim zoGzOO6czK#g*-%mQ@t&*!Ny(YVCJxLy!9t&;q48Vj`he-5SUvDnYd9_mQO)7utUyv zy6SyXcB`%Uf`w)+G(mdgnJdKyL*w5fL)wacYV(g@e)BNKDX_H-Ja#W_XLl+7P8irP zv8OY{m%P`nGzpL;ilPUv&t=aB!T53D1kn~r#YX6bmb)bsn-%5T{0^^K^U2>ITgR_4 zXgX}w6+d8UQiJ`oK2gnUwLelq?pG~U&+vG$f8I-@ zx8vSLrOCZYM?Wu>aA(TFNcr0AujJ53bz>R*}LEITuO|3;ZObFhrR=T1s zJ9Dv^`r_isw288<=IM&%Az!8waCFXF5+V)!?6Vrk9~SE~6x8tJn@;eX;R0yjk?w&F z2cRQlr~jHUy?896iBKUcPoH^WNu&>&Xda2~$3r z{STiTCqZXFK)FG8cvYinR;C86P(CGiYR0D=>Bi=39WX5zTgnj zJ`eFOAmg4DxEyk|K5ArMk)MM~ix?RYYt>f=Dt;RS4%GecT_XG+5o|4RW{~hF!ww^y?`4=q?z?}&)lPCt=op=p ziIPd1wfeqgGGr2@oASfLZ-jI(y?7}VZa^<;hYCX7R3mb$n)fY0eTHaVPUb;dHRGor zew=)=*MWX{$}_&c9^X1*fK^cNo%Gng z7}XZ4K!$~x=Cgksmz*j&AD>>Z;kDg;yK*Q@!gC{scXn)hHG( z{B^&8o>kti6{qXdQ1cM^+x2Jv?fnZ&H7gc(kOydu4$kec+NCD#c4EWnk@DJlvsZ%; zD;pkWT_v?j{nVkrjFCa$Nao)+PdYroyp63I)H5uaGWIRdP=ZV37&01kCrs$`<)^=7 zCkoKpnphQjPUyL$*xVYQIMM8a3KeA^6&rOQ{00Ad`ILus(6~YT?SMZVd~AZuG0+1W zUc$UQrojqo-;elg>v*mf`}W3DYxsuT3)iTh&nS$VMQYeE6AA=T8yWKg9V^Xp)Mc{< zER_^f`|*jVN?S}}4c47U;q83Fs^DG{(so5G0XmyycQ|5>Bt13mDdv2iIuxxje&2|= zdf|w3{ZnyTr=6X{>&5bTbUf-5P(9Z-aR8}Av+=Yy3(QfvH)vz6Zl{DSlOfHIEBzzE z@kS!3Ty5E0cfj-_?+yB}M~R4<+J$L3^f8MjT*Gpy%XcleB{Uo|nbbC;PUE2V7JLqR zF4B2k{^h5mA>O_}jqD5j?Oee{@dQm@5_mQwqg;5HF5@v96MJcPJn0dB8thdd8n}X___3(jCIdvnMCDUu>7D@^#M{XP%XH zKK-L(PJ+{!$L^-h@#U};oEj}D4Cl)HD4AhB~HyHGW&$eMYV zi=swj&`ldz8G114uHi_)wDav0QqNGi_tedoFES9o7{ zN_+B|Pu%Gs=Vi_fW*PIY4>=(fDv5U~mYkpO3p-^rX9n3bKe9BZ+gc=;4Z%-i-Sf2-l{e^uVKIb<>3I2i{l?AdG516KL zmcAl3AsZs~P~C4a@y~ZZBSnJBZCDvg(pC*;%OHgi{_QF~9oJ6|km-rPHw67Rh3OlWRaL;8YO?Rr)Ri|fNc2{B!z6UpAd?MN z)66ARz!}b=%xfnfyKqYGU{cKumOl&>D9I;{xG|3~>SC8J|L@H4|G5VIk3R|ggahY# z@!1R^#7NuvrcX`OKDwh#wC^|U+ad=l3u%B01E)-o9QDfo14BcL*0sRv>Qf?A&y4!* zI0tfm4{_iCzCxrkE2sG`Xp2Em^6KD!E8tD!>it6Ft zH^+P?)h2_+$?rnE;&nFr(t~9iVG~Cy0;Zu|j;E_@B$EfN2Fac}&=D{d;XMWCbH$@XY zp7s?O1o{xpT$*p-{VedbL*QpABYBjtJVtSRm|+A!{6)8Bnvl8!^IqF=J(&x^&a9zi z!1f#L{Lt^5b7nS#u||tE9fqMN{-6Mbvj7o#hT2+}vSZ!*7mea9uhGrPTlG*#E5$^j z^J$LQfL67UJPe8pa5n-I}9T~ZCwl1-W=VipG5P1XRR z6kOD}f*92&q%rUeC5+Us8zFX@syP?mx)s~wD`^;sXnSY-6mrQ{`mUM4JakPB1CYqO z1h}AQP(Q#%3p$WiR4+Ojo*2y>=t}O25lWN#!+{XLQQKwgajPOSDuLi%|V&5vGc- z_6v%vsW@fhL*k+`I-r|(^Y5HT4fl^Cku!NqqC0&Q2ZlAs(&BAC&%VG)TO1rCr{~l5 zv{5JO7^)fE@0%PNyDA0yrp`UcH8&HJn}HgkUExu=!ag|Z6_g&hbm^4Bh#+!phME@| zYZJ%sUC%H%A?SRkqfKAmMNa-1rX4PcNF^Jubu-YvFZU&GfZL%MOt~{j>-AC>`r>1Y z>au*!T^Bi_qjHST@3D5--{OM>S94F`#K0-)I^GR0i0~wDBsEJEC`0*|?8}r)m7>cN z<oz!O>{kS-QEfH*Yv>NpP4$*C8g320RnHze*0P!*_i0y+GpojDWAY3H#4ZZ8^6PxN0dC#{`Q}QrUKfAsL5_}A=KU1c{Axvu^ ziFR|7WC<<~bVMD^vNROqRHFY0gyw&1T^A`=GB7Vh=qMxZ+QPw>JvB@J#TO$KvTz0p@W_Lb*Zl0&^mU$#TuC2xYVzh%J%;j13ji(JL^=`uv>2s>94CT6xchEA4U`_wId7%Bw3E z7bCfP2tAwR4>hQl=+<+e*=LhtFPHDWV50K@Q{xC{$+0CG1C0xb)M&z0Ubun&g&gW$dN(fNyfxx~fE@V8g<1RoWE>l~aV}g%P!i zqEGC8wg#&XcLDXo@dOUQ%psWCRN~ixaXmj{A1^6OhVj1U`wiiSEiKN7%>m(M1;}(C zE028!MFjncp{`JFpog3hF*r2mlf8JuJ=E3ZOa70%wSiv!$0>h{FDOn%PkfITv=#~- zTF(U({&0YBNl+V_PXn5eb9z*xH{{M}fVbfeqiovf$cKJ8cy(@+Nk2drsV&*1A-5;(K_5E%f|Z)NfgVcOJ+&Fu2Yc{Q`9=gG~SUct(3L zXO*Ig)b@y|c$D&(B=e#8+rVE<4q`I(-zdAPlw5`hpfGQSjUbYv+9|GIb0oq|@gsWB zGT5c4+ZnerPsALNG-2>g5OL}QpE+pj$uR>28)wKg2mMg}VLqriIp;1KBL6kV4Z8fIi?V9V9aXaCz zsZnh3xpgf@!id+Krd%6T?|u_-Oi>xGMuHH7#ePdK5M6gYGNTJH*E)e_9Xb$+^_WxXYw4 z^;p&Vr;*Y?U^(*wVCq`5qGeZ0>233HnKCUiIP`U5AujUL9ESw)w_RbIyBDeq$wz}R zg^OBA)sP4zm={VuId*99gvFh~^(T$*X7=GZZUxm?qmxQcKd{zZ6*K{VTCOGFTgtpc zGcTehes|Dq9g}>uQDFb$2m;Lh2tQcK*%;<`fV1`{#9#$Vh&xv*&rSeKUlvXz)ryt2UB;NcxndNkJI{Ocl*w!5BB*L8L4k&; zhwGi+n&L`lKeM`U6?Nx1_aBbS^<&58J2WX+b!OlA#kV9r0fS9rHn;YyEf7V^n#*Y0 zIP$Fot&&Ex(Co=Qf9mxf$UE`92Xcu!p>${9>KuuCqVMC%ZmPqS?$WO<_hU_}x5EeV zc%)jAmVG1&v|bS;|9W4mAhWiQx2IAfGeQ=xs&#~~Z!h5#SdC2G{0XGepl00at;zW6 zW)Jbryn{)Lu*T&$R`wKg_Y9l}F+jKS=R=)+k>A zRQ(UbnsWs!z4`4N%!JmB*3U|yX;|8cK0V+eiFUUB*29?hYzd4xM*SR^?Dq1%r$SNw zucSiF!fJl?DtyHsC-9bY-tZFp;aIBIxm5H2c>ELq5VUtO^E9=*w+83O3KLP8YD_54 z?Xdj}^2ttBai8P)H?R@spP~N@$|}WL5k#A6ig?0wO2e8z-^$MOU(TIqvwt$EXIa>O z(xqm!BAkEznGPmjDNk5Tvg+1y`;D8KZf7g3i~rRJ`d@xFuXn%rDl7SE`j+B5UDxfB zW~pMLWC5ZI!6wc(gY<3}~3n6wh+$8E;Q(DS^+=Y^=TRZ9=m*)2F35&kQs z9jnGKPR2v<9s==>GCA(sl^>3ShWIZ%)spLqEnuM|h=k5az+9mNcQU*S&o@^`rNsTJ zd@vclcp#NGyGyKbY?Z(iLf@vP;oC#4+cJCezpSQPb<2C7JsBg9Zd50hBNLIStu@Rf zS1|YQDd=@%B`#*kD$qaTzPWz&;?!IedPa4pLYDxkB!T_|p8GaspQp@<>^r@Be1myT z9*Ikr+C}1OgC8_JeZzuUshP4q886VqwK>4u;AjkC#L1f4dega|I?oX_UUrDF7AI%6#nV4y{&3%Wq z6T)>k5?>>2SOuWaqv$Hg+`m3>va+f^>3e)%(T#%8O0WsN9fpiMS!&SCXIS?7W^EkxRV|rf-UjHM@uAA-JKUL`3?cstRuEnz($|kshTJ z_^Yr$L>4`V2JeDQOsb06BY7IW)aCZ1|KYHV9n|sqSk<>7pD?bZKV0B_q+vFhX~9Z5 z-^^34+J-paY(}2e64X> z@zPH-OMsz>-{a9{gMyG|;Z##UnMySjch-v+Kx~1;i;uV}Z5nmoU$52K{ zuz3M}V*89bbsg(UzTx_m;w|AB@-p}Jaaab#ZY8$){F6|NG<|vIF+6R9vd!imb*iUM zC&l}aGbdL+slAPwNNetx?y|Wq_seqylw>A(7zZubeW)Zg~8?U!jSpl*V)-K&_7VnPp0-fsDXdn46!-{PK+CfjK#5wD}HkV3#bErWguh|_L`9tX63 zjs^#sxHN_>32fIR*ZdEbc8EObn!&xpj9N%BZ=r<%bSLB(Qi2oqBb|Ngx#!3G$Z33t zsO_$o%g2oe%zL!uS7;A>teqJq0%ib-*EFob@wQ*Vc6w@(N!A zg7V%$7X1}WHI>CO@pY&Amxf>KxKZ%zP#hIXmF!gElODWM1cF+XmNZ)e>4=AI&MD7c z?XD%$a&rrLPOfx)Hv*N}9?P5thGwN;Q7|z*%h?kbjZ%olEh%T?a}h@RzD-k#BBPyK z9-#(Q-8nGoZC;hj&W>q2Y7x19FhPz)xU5vahIIwxfxpkGl^pRV;6wzvbmqUJ!OeL_Y7}5?;uKrT{`Uhfu?) zOT*1UVJI-B@*W4Xc7fEYJ6BfwEPkN?(hfLaFV?XiWnE3l)O;n7(RY6(Swv(LsTYNo^vS)j0Oi zR$eXerMb4Bj;NCPIY(qIHNMSchGA*)sB+U;PqCtrh{|Fo zjs0udU)Td!FLoF{izI*|;3Ys!)RqO1TXeNBLCh-5G+J-kX!?v=mx+9reK^6Oui|X9 zOe<~Ix?vC}!Ty0d6DcQccRo!8`+7>C=KhRQ_em%vMTd@gkGs-`@zj^AqZu{dEohGJ zd?OB;p;O}bcgkFRbs-ZQos)(c(E%&#r?i$$!(O;sn7946Po(X$RCe7WD6n4F@K5Hnl%P5*nGZo_$}vQEd-_;o zR8noi@t;52za<}v*P{3;6Dz9gUwkr}vdsik>1C`mz55IWMEeb@Yg}!Mu3h7Zm({jr zxXz~EBCnrZ=@-2x7Bv1e`veEbCmb&bJ-=cK_2YzAbI#%=F-&C(en0{#;XOAJpCCy# zY>Oj2eKz;PsulNyqjVY6ag$x!L9uJ!tk~LbPB%MB;YV*Lv_?ic{o=H}anS>Zj4-D~ zWY1UrmP;NVjkGR907U_c$}BwLIEjxf3Fu1^<493;R-Gk|4s8!fz8berB?y9!I~m=nA5upGF=zmJ+Z|4S4(4iyGyBuniPN7aNr8X-pn|bVA7ZZJ#%ff!8lFwMxEN$`p*%i%mt<@u`V zRT75qHywf)m@4Y2c}t{PhKw3Wne=~f;evuC?XTXeS?0@NFpfLNY`czt4hVdsYE}6_CzkYFimFfUrdq=jAFs9;f)(e*73B`Z7-3Mh2N%w4gAPgYQTnk_>Ey5Zhv*I>=~;H^1|DW2Y1gKYPcYIX*?SDI35 zv!rh9NxhdAPKKGWe~_q_0tuIAvYi>a;01U0gMh^EU2K#|W27y%rq(k(eJS_}Hk8<0 zFtyk`B4xV{X}oT#!fv-k2}KcL$7*2-cpgo(41(QbKfJ*e=Pj4KHc1whB~L7nc-5-E zoyb_+3xDx<+gPjqWmX1T4@BF1Y8u7bLhY|Q*tiEOIb1lEu?A`t)IZ5*i=RD-63rL- zC04gQ01^zBzrJG&_RJ@Vv4>zBnz_f_(w|*8{n@XLN=eIa70kOBoX8CLIrXd;NnzL{ z1dOmiMj;|;4%_bFI){%yT6%iZRkUqt)2H*AdJJVb&jbT^z=X>FwGW8pVdr?`MWR&EH13IIPGarLhg8(!?2!i zIa6~$PZ{~x_Fhfxh%$M&sJ3=X;!&(rp4_EPS|l&Ab>U@Zt&(m`fl?kl)dc9Hj?J&v z&Iz1Acv>`#>@?_|mS&$e=Z04S-6-_l}r%cL0 z+ja!5O3|PiHron!D?d$S+v%Lr4V}6(&hHn?k@fwJ(do0#gkOx$L+v78==ZWd*T8w* z!M0fLd;({C2@H@kuOBw$j7qBxgW3V#Q#toRURhX(y+I-S8=KqospWFWME>;jLSt%f zp&IOw3F*9jg(q`x{(&)5m2A&;-OI&3d0Hna6U_u=pkWCJ(K7aEk}O> z&4&a1zRTp60NRoU={4^rfC?TJLz@tHgJxv9wC!>RQ{+@XLZHp&)8F<#)32%b-LlDjPAUM~>9G;ng)z+cySbG>k-|+vyX#N*Sq4<|PD{R@l zb(6$J)$EMROgM@iuUG1p>%~b3?j0TxJdmY7%!2VoN$vTFg2|V=%r65`>8r*q) zNz~y3@p5j20C>px_0&(-Hrm05DBUqnwQ`joqXJiIHD!k3ExvYO%vQd}}@T6W%uW%1Ww?M?4_-%h`G`=tCrcAj+RE+Q#KGf%wS z3$Z7rUZAKwj5S1F-Ff-{)3EB_{hL+Dfmz5gm4YuLj!UA7(#(|0!p7kmd#dN>O2No0{hWojX$svmAGqP(=zypLn2*@dsYU+OZpA_8wZ^`rpry(%usI1(-X6 zpOXb{Kh+~u{c7GNF4^~UEx3MFFr8$nM?r6k- zWN@u50$X}0^OxC0U?#dCAxvvFD3Ul}uaN0^O&;@+k>*TmM%n`c&NTJ5Ikrh(=526M{F<|Q61u~E?|se8DL z!uF$)M)Ez_-JYh3p+USCbT$Jm3fH>}i3^C^TWS^)mLK@m^CC(*9J>lTojZgRvbrM8 zpEj_SM8T7x!oOfO_^=J81>Z0gfLm=UkB$lvXWa#@>SD zx)Z8v-qIM9(q{ke+S`S_wkn^l3#5$0jhk<9C5INo%NQ;QnRi9Fg6HWmsm=3?63`cz z{@gG~wJODs8rMljA74WrDl;n@w>Ld!o}M3>X!7mnObcJA#;H(?b9a^3o(eHNfnKsV z+B&M^`FlDTHX50GkrMAeE!BeB18x6s%1pUYl*By%rPQlxPWznFP0unEZ1q==6JP(s zarLI-n$PLaeLk#8wj@}~#n|E&)J^6}*z%pJ^kthT34^fNkRZLVqI5z53WC_B3xUiL z_1i#5A?TU2_WX^bJTA6v-R#`49^vkj9BMyj-$Fyna^CN_&3xLm7{Me$zKpH8lOYki zGty?Nrc~U=!tt8)%!Jyu_CUeJiFeam(_Q%}Q;w@B1Yizr7~pr`mpnL?EJ<76@Oa0_R7Z`s$Mo3a4u zc(!H|?T~69JT^zZrWu!cJ>lEk*C`wX&ZT08fezd(ZNNDDpM@Qo12DZH&zdyeIrKW8cq+|Mez>vj& z_hfMX@Ww*hU(b>>8!AX9tT>dWr`BtWLig_A({mHtMtiy}$Y6;Im;YP9mHPKI(=`>e zQhK|N)G4_pZ@{Clf!t|7=ZstIeh`Q$!h1j_2(w~smmxYi;v8;MpORZFA0@ z*q{)ocUDNpcXTvWMG-QiT+Q{^rtD>Fw^Eds#n#6azrxIf^sp+OP)|AmbmF$BnVJph z1v{}4o_NZqxcj@`w^Dog#a%vLTjuZS-!utg8Iu>uXJSC_c96 za^xN(2=VftWHl+~g{Zj^AZ7l(*s+-xw*04vmDys8dsXOjOMZ=7w<|Y);IUj?x}lEq z#tlPjF15Fo%-+h|j>4+a`a1EGXv-1Fjn1OBI!Wo|n)Fd>UNiN^`*`ftYtJQ!B&ZtH z9TJ}_sxQDE(O3RLU2pMSKzPt7ULW6XM94n2`NLtm>qmIMgDGHMp{g6;@px7-TVuxX zO7_n8~q%$9a81%foP7c zmwlr0JV%afK8p$VEcAFLnLS-P(+=13yTQrow$kGLhMrjk`mGX@S%2jcd)P<+a0F93 zy#vu)o##JzTOA&99@KwWzc(*@VdD4CUrbAYM#hKZlxQ&{`rHT?G>=<>zNh=bjOlW5 zt9KqzlY3Xu`%%(YSWKpC8z|`&OVaF>Re9EK_Fj*kQY?FY%cGBv_ z=lO(EJCFWO4ehhe>596Cjdtd@Funt9?inP4^-=%qFF%LL)kdS2p?+gy8JIe$&^~#m zB+OY)g%5%H9%D?tkAU_3p{Vd?U9uEhctVBpseGqsKmDS~#RGfQ*in2D-wdXPr81jNWO5_nBs{nbH)`-Z04U+B+ z#a}c&U8>*v6E*MOI*HCcBu(nTpJ)Xof?^~fopdYCJd%?5O=Nw%rGZ@X+fg~xxXn%> z;zNDC*1miC4cXV>$I|))AkgVcOE2_GfC(}*27Q!yit1=_2*|xhr4*LW{x%&ky>cxC zJ=3j$a~4n>J5UczKzf({ZX`t4-rvCp!TL&J)9-uzgOvI-qQrZ?Ext<{)40xQGN5VZ z7?9X*(SZBA-H&*EP)m2-&4Z;6tTKFC;f_gVSg+gJQMp0n07G{b)lv|+BaZZQE$ zJB5pVA4P%6!7!v6*LL_zoD?e?cXGxPbORE*F&J>dXtonx)GA?pqNz%pF1r@`)m!dk zY5lwuq_?j_V4RC=+@3p;Wx)dF(-o@&tC?xp*>gj*v(53pgk-uR5$Rb&q*(1b1>Z{g7O} zw)#})>+gA&5@d{wc?i13np-3B`|tH#QoYfd+2w=mP0i$H?DTl?DU11Q97)zRqhzmr zvjW!e@pxjq<@eu$=m(0#+~BBHHC}1*lv9lxSYDDYs zg(|yz&eMiCV{c+I)>+;*8e~PgHZ-z|Rb|Li*UV!+uD$+?uPsZwFEeyJ1v;y-{Sdk3 z&$!6$*9x++v4slkyj>W!)4)!^pj@X?`>JW%Pozy=Lq|Gr%{J&y3 zLvuFecrHT7R#TvI+3m4)^>sys%H7>0^rMXz;QCxoo1DM}VjaXj;J%~GfUQl^&Du&u zcz{dXkAz3b?ZMIbj@Bqt8a1g+HO^5BfY7*%fn4f3#Ve2^IQ=oX|7LvEsYH_ngWcqT zcjC`wE(Dhx`Myjfi9u&eU^S|p(7%2`_}8{6!maz}mAuK0*|MXCIp|C4Z(>fT(cwB% zw|y42U?(7xQu8I5le385_r#7rTlEy_2|oGmWYT)k+alD!&Zo|ehHXexAcj~**oTKT z!!(QHk?6S)2Xm$Ji?Zi8ynTF>m-v!i>&QKydrKS3q?3pObP5nh+cy)Qg>~YOKqAv6 z`Kx(xCrwVQtA-n0W5y_ZIIGF&M(km;n`ix4CN?Xe#n6Tj^B_$R8#mhT4InOXC#b7t23m9Q5pgzTOD+|PC2*Y9FlVZHT7UHY{~ z{;36;rc2D6z>Geqt*>y_`_;~oVkdlDv;gP5Exy+(7P+en6~Y@6q=AtyA#B*xXm0`E zl$7VK0KZZ18^->f4 zSz+t3-Z!2PQ&!e_QdIEA+k4+Oy?{R+_I*@XyGi6mP>A&x(9* zs`dt>6|nKd2AGpxl=VHFCu0|P)(+?{Pczu1wzjUme)4Bcv?etBI_F)4$YDbfxDGI| z14*k1^D#ZJJ0wGel>3I3!SrT^hlAn6B{gr|^CwoDkrc60K9*kQRYTBg z=wKw`Ak7U?!+5}r60k>WWE8?)kBk#$GtD{ub)0BrG-4W53d~3DQ1% zk#9Z2t@&o-Qx!O;SO`5L*bTb2kvPCU{adhn$#0A>Iddcx6K80Us#Ylz6w*C8=uF>` zxK_7>=Mo9UP75-fFG7Izv10q+A)XA%hZB-X#l*Cg76%NF%q9rhxxGb!zw2nD9@d9c zfIIs#;NPisDmmn{WAm64s-RPzS(m||m5URz z!4A4$Y~WmRAwlZtNy}LytFu9i6tanuMr`G>f8hez&@biBQHy zzY{YNYYCcVy=v|E))!tyuGBPhhYk{KXY8(oek4iT5myY5*9fD_-gu$`{1=!TwpO5r za*av2VdY-*j5eBBeH+SyCVH9|Hq zHNtCQ^u%!u>IRpZO;=8DoVJfwbH4w?zMnk~s)vU%ozYyuaT_I4Jx^tn+5hR+#z{)X zAKfh;b0h5Wz*;KK;Dozd+Ub)>0w3{Z2m^2@bBaNr8SqDtL{NVCJ+l8(j0vdgvQToE zHHtB-PSFI6!d#|dpMP#-%n@8qUMOITc}nF)jU10#^BcZ;H(S~%rEOli!xzqktfU=+ z1IirK6JHTAnIBDNDt^XGtBjFdhf;hzduT{$?Gr4OU=j5*+gw28<5!bYeN5K>WtH@w z_0oU)jNxJvQ{HyY!HoM-xMvjLV^>xtGfA>^GCK7 z2XAjuR186>(T)TjI16X`s5#;T&8<%My{^iN2$L_H$5A88HJ8pNa5LKrgPNrKI{p#c zo__aChTt0ih0BlP@9FAUeq**2sop|eFKpd@tBhdDM$^#)tw z9wcs*2ev2CZJ}d%`NxiKV40&%NhX^3`Ql&7k>%U7q+1b*F#sH3;t{0T>FlqGU?GdY zLi65%DXJIo!y=dL8XbPMjdkvrz8?~er` z5L`xF4HuPffgm^*Bd8}$#tn{k(P1AYDQJJ3+-imH&1%SWQF=Mc=cPV|5FPF)NbJoW8yRX%#HjV}fp~9IUJz|OiMy3y| zzh)>-#}Zb$LgmVL7Tdt+m!OaOI6)ov7wG=t9Wh%W=bI50A7i0u!pDVe7YWjbFZ?ta zK?Zi(PLb3Vx;IHF2B<-3z@D;CGI-naZ0f z^LXnCAd9Yfe_2kGweIdeu3D1S!@Bmh-Xr~kijD%?x3~){3KZz%y4*hs$$bHNZNs!> z2{ezHD9TG!)$^eG=w}yFG%PA5{T|1oHeBnf#EE(9kekx;xP<3T9AZ;v3Kx25fe$|4 z`I}7Ibf|z+=0!K_n~^tq(yra&ny_`e!uL1!;<~Kz{)%ItLD{hC)>N5%Jn!!1W<=7b z+q6#jxrEGzCok!)hX#c9{svHDpk_(OB8yvzQaMkxds8`?jY+=zI(CbstI($tq3oo| z6(#w@Lc4sJ)6(w!-&QMSf9Uk8#Z)p^k}tt{u;w~|CLZ(~at%_o8AKzc5 z>|>~#6HDz1h3zUo9{(r$@A@4G1Jo4rT*g>t;irBGg_wp-Y?Liu<hW7L;d;0)aWhREK_nX7MBtM@Piv2x>=0*mkCgpaFeJzz@@VF26y2~~0lipWuX zAtki9uR6e~?bcPgc@fMUe-M_jyoUlBqI&yB=uRL~dbl6}g!EqO&o_6jTzMpO!o;FY z`++7S^e;v~=VIS$1;7i&lLisD!S;F}oTeJiiu%~hwN}zv>%1xu|2o?0yIn}}WEd`* z_!>Yk&@B_55u;zv60DHIFOJNo-zsUWOy~ZH66T)gdP*mKp|y6OZzkTA_q}K!XcXKA zj;>w3*2;gy_e!6VNPa&1sx5YV^~lV%zo`jEO!=J#3XBk^sH#$2b3O{ z$+;Z*%0TP3ng|KG(M^aI;pQ~L1wgWM{+QF!b%x*{H9-uBwS0i2H09aK zLhwXC6>`Op4>Ox)=^k5mQ=V{p({FjlgL%0SN{Yh3rsykzT3IF_p-Vs}sZ}ugRv|;S zz}7%ro&iD@P1qM={@!c1iJ&U!>{Bj(x6b63x|faKTgb$sQl_qcpV2uK&tH{XF*AUfvU zDPMnoMxO*jNL4BT@U^a4)VJ_KV=ba1wX~pf_I{Dj*Zu!uPWgX_K7qk&1*vovp+I^S zxlq%vyt!;;ZLa&5OOs>jCm;h@=ZoFT$c`gwf(XVx{Ir}-eeElXJ-6;0~G<&Z1w9@a*8L`*>DJ*P;mkfAvEoAqZ!PL1BMP9)+^*%$)3mvVD4VSQBH-Go5BJ zK4Fzi~p4yXRw-l$>~6_fC;vt<+)UaMc<^-pUd`^R`}R#^lSu;*WbzSwCI+ zSht|yi$2&^AQ{xkVms(BJI`ud^(gBTIRVnG8hPB-;R(0uGX0^+IJ}bPoi98FTvgkE z0y6;(aFYl?i|v0nljh}KFnC+s)S|nZ`XdRW*rvH&`^EfT+DY#|b3y2MZKwohHI~Hq zr*SokYouQwF4J_gwVrj&*{T&HZkcL~@ANt=e|K1V^cF!oY=?}|UN~OZ&poKl zP4P>Y<E`Nq^bF^k;I&8ygL_iYq6Vy>GxO-fBJ$}^S1bd6C)Y7xF_>Ty+=L}3cvzqK!Ew8 z;0vSX@1?&BTWE|w+Ao#bs!Vp!%658MSrVH@-2O4zwCH|2D*J2_8QCF9w;I3;V+cs- zU0_JlVX=tFF6HYuC5m{kla<1nf$Ocjy!>+Z`%0=# z=humt@YmvT4Z`o=*Lw$@mp6kwfdwibsQu&q|Z z7Xk_wN%9;%oK%~p1c27A07OUtA(f=574GRXW_ZuF4w7g?ikbBN6IKHYR_th|o+1Bp z*{Lx~)5}q85%7ik-~?e&r1e67S$FJ=0bLJ}eN|uAJT>cPd$?=LLw8{O?vYpC8QVKk zy#J*|8>}vOyLTDDS(*XSe$(-(%3-;BMEJv&wsa(`j-0;^i-R0mMszS@?@9U?(HF

w*T=)Z&Ru*st?KEynpRn#}x~T5D)}x5Qar zT^%8#!sg{m6&Kcvo^3x5<-$-Cl#NLFK0eIui?7p`Ui){lOppZuJ|h-_8QMSk49rRp zn%x*9Xy%#fh^KQZ?)+s{$fXg^L|?s~|HM@m1pt4dVa!l{invx0mvfe_iibJI7%NNF z&mOfg3Pucc(hFsyeQZfCU3JR)#BT^s2o>QfPBM?c{~H$wj;?7hTCyILs#9=Z9Z`4^ ze>Ya=W*ggk$Pa7L8Fzv@O7!mD@dELkOKPgWjzWVS}4kJKu0zf7IPHdlA@u0@=GG z0N#S7;qxG*9ldeTS1|gO6<`$((9q5ebZE@=RQ;YT;U@BXg`2su)5BK`j;!Hqr|M?yxz+=1DPxjaBAh>oW3@J1k9?H@(;l|Ta zSJ{+txDiKrte?FGSAmRQ?0Qn|hgyA+D&7sD21e{3*S5$)7|Z?Pm2TtNi;F|U^FY}( zCLAgkn)9#r=?tR*sXFc^+UYCY__3V45ZAVmH?EBDiX&mplEoAz^Tr?XlKrH6&NKe! zCPB$-!Z4c$QH49q*z&;gq&2rnCblv$i`vDrhP`d+<>#-Ogg-;mKaCE_?G1A^iVfV=tSGD! z{1du)mh&jP@LmbyQ;1WT+zF%d_i&vCa5GpQn(*7|wnW#RTkmm`okG-YAC#OnokYTU zXqvq=G)oT9*?S6)8cw}q+}63_Yz=Cma0 zZffE?;MhgIi+#lTw0qw?Ti=`JTCkrwI1c1e*W;fs5^v156C1quirM*wa`p7oqdB^V zmUlL$gJszI(iMsW4WZt}q6Jb9r>o)KMxI%P8zIq+cdZtZUOi7^ucLBZneS;@d3$Z@ zcXmq1r$#Q8%*-b?Z$5HF`aY|xjhFcH0CYqZI${-;MkOk2pE%ydcDw6cF!Gnxi+0k+E{x@*$acpt zm1o|s{siU#-mE0~GGc4L{|L#FJS)6BpxI`Rx#jQCDZup`D}`{1^f*9)%*)I45AWZ# zHvjTokmSp{E2IBI5ulHc?%`nDw{9^IOXiPrs1u%jUh24^Lj{3kkB3Kmuh(4ezobgQ ztB%S!-vg<-iXO1YE+#vGZ|4l0Dy~ z;#8!5CAmPFiqaM7zN%&#^Qgt$lYJfRpc`rklmT)D)cMTfi&@oSu>_ZxBfj}p`(mr} z|*yxkE8lrEws zE8yZ+B$aH#ipRub3~BnA=zi4gDglaC*Py@=s^C|UfYx%Ow^s_xIKBuFoVO0=s8?)J zdlrvIsivpZ&y)VVviMcCx^pZLzNLnUrJu=R^z$mJ+>Su+_CnhIFq`7wMmGO`bJXOX=M(pd?&w)$ov8Oxh;Xpp7$gGFDNwD~c z#>VjXETSs*-3kBb3+Gk0+BQ$|H^Ey82W}jQW=KFVRYpY3*{`!?m^{nnoQD0Ko0n5M zaveeozb1#2!e4aW$hLpq_|_okYMViZMjvd@9%w!n!D`V0u0|oK%NFa-7x}hiy!P9~ zBGy-vV?Oe*Rim#}gsaojkN{Gt;f2oKrFJj)!%o!Lbo6*%VyzHmR6k4Q}6I5 zFfZMgf%WEwSfKP4SUcd<($sqEkT7L-r@BVH1@Z{92Y-`kpGX9Z$d?*OB(+8Y%S>eR zUy8nH`RVUZGG60v`%8A%?yU}K9}2HntO=%yW&a ze%p_7Md-26(5qHDVOH#WcV=7h0I*hbLljxnvdWg0(76eTaySG7Hbfg2`y$~tWW#?> zd9*HGU+ChrsQ*TD;qb(x*`ZY-3Yl`pBq%fG1_<%|q7x{HE1(a{pxzU$ED(a&_*SIG z^ejv1ALHa&Litz9Sn)F#!YADB_%J58yUy?OEsJi;NS5Nbg@wo*-D9T8Ks$WNV}k4C z0Dq&YQ}OCkrnHk+j$ec-#q8xcH$cxW>DN}iltOJV%XMMW3O$}O6B{LAS5DZT<||#a zmH(8p4b*@ax+veBDu2Y2aGt1To6gAeI5ruq1{vE19NXA=VrE&hcn*ONqtm?(VZ9OX zS3`5$ebz1qRxX{^;dy=RcCC4Qgz?Pw9J~(E4ZcGV#65y~ie%-hl{?M8v2w0GcV#ON z*bNO17$eLjhhnTd(}5BS5O}XsU_`qi_XAu_FnsT;*(IN&iMz`@EYREWA>Nw}N|(ku zD-Dws2P96Qe2xCoDp)b)Mlf&>kh^_|ov2+cW}$RM0d8b?zZ4n4 z#XficuK=~ooL4`=FY_@J9Zzw(c{^~rQ0_Rjrx@~=YA`A~nd__{KI(lJif^4xSo5R^ z?FHDt>Z|SSA%`^~vO{Sm=O2uzBH=$g6kJ4Re#R?cRZ_8jdI|D1y$RJ8u)Fh%F7%e# zGFeP8USo%aHrW9q2wysJ02hX#UvmimDf@{)nHS(=I#Y62n}uspT~M6>4PTNwc)G{` zYiFW$vkCGZRvFm^i(r{b4A6W^>chB~FPsUKCIJDpiLz7q z=j1d_A5`zz1Z1C!tGsRExvuadWVICf9xq66X(gtH^73^ZNc7jR;^lH9bW9YCEdsCH zi5x@U3AX(}V@=FOIAyqE2|!@p#{IiE=Vs-~#di0GTpmk_R9oWcfY7d$EOr``u%C?f z*Cl@UBq;j!KNr5ulI4BX!VSx4$(jOrU3JQq zz{`7AO%HiIe|YwI%^)5el;qZH2u(%{lwNfQxsZnC&m*A^(I{lB3Cn(vXw(_|W3DQT zyhVnN*PCRXsBOT!1DSWk-Xg{U$<=o!2^Ik!iq0jwSjzj^AxfveEQD$k-p1Vasw}am zyzm$3yHd2B7x8i$o(kqTgWn)L#;Ku1=M#N-XMDjFxX--b3$t`nYgsELt2UQ1SUHl9 z^E-h^Vw7l)5{3ROKvDDCvz)AESoRgPF=p?SV@*(!?6%j1*qJpko`L4ekt?a_N))oY zCj*$pJNWTl#KMn*zR5NzvY`I}QVgodKUl9_8}Yv_#>0b-LBhSlsaT}*Ez4gaT} zc^5{t1?)3vaMWv_?7wlcisp#O8h2it6s^v-)#8$yf(r9;^er%d=WjKTt#?4)?**+s zxkLUdUx8bAA)*4_D|(e6juS^VB}Dm^2j?!VJgL-(X8tzZM%je8TAg=cMrWd+$3oD+ z`Qmj$CqR@YYj?7|?094D6?<{y(uUjKI!WX>XpditMuOewk?;tP>n&*O+@j7Bi-00r zvqaZ>bDr?7`25A61Xt#!-&%w%wC=$vhu}DO)thqc;+v1}-k7UEW{fu1>MDN2B!{l9 zfb*BiH_MsQUv@(OCQ~~M@DC)!Zer+GBi`S0BxfN71B#cnhy}K>^*LPP*03-3X2 z^uSmgcfav3L@U?+s;Bvv@P_}*81Nqv#<*J~st_A#;5Mj^xu=Q`9g&*{fHH@Pu{2DArqR6AA1g!e#efBou9Y zA*jo=AtH2rt=TY|`-^O{Gb=)9<%$Om4z-!HMpvd`;Z_`+hyiu~yyELW=(a4JeDiIjLJxQ9LFc9+F1M-_ z5*8)f!Pg1kLL5yG=-U4FM718vAAJ{x9&f$Rivu(*O)0&@Cw80Vp9+LQs+OclIMW$e z7^+s>S(@`E_cvp$@dTVpIq~TD{OwW3${7qBhUQH`J0h1y64r&Pl#*xQ&M=z6x_;8w zJDpAFvg#orp+>}lo;Z0LMxwMSB@Lz=yD%b{Yf8lx{k=k{Gru?%y{q{8*~VH4H4w-= zvJz_FTVK8;x)9b8%8C))U&b(YHjc&5>XOhe^?5UU_rQ=L@HymWD$q-j5>Bz4C`!QgPp7)A3D!W#}LezAk!o zaBW$%BL>~nvBEa#CSB~V>NNWb$OVWFxW9C~RCad34DmZyn(&d1uGj~73D5o}i%ADq zGYp|)CYL;Zmwb^P(u-CWFD6j0KDpa8va0O!+>E52Tz&O}h0YZyQzo|GZKeDo{IxOmx^8qaH)r4OaSwXf?AQQp>B(xBT z>eia*Rj7B1$=FZy)@SL$w{&pPyKGyM~qAaQom539Snq*o5R{i=kOiM zEP!*)DIsk2b~WtoAbX`qs&pb#z_)u#9}LDl^%I-RNX^r*o1s16%KRQBg_pQ2lxWzD z`HKn^MUrb&>-?iEH9GRdn;de#0w4Pwk6U;t6vG$rOZhta_C6RxW3)*d;yuvI43*s> zDNU3sbK~^Z-G?*sKIJa$8g#R?Y~(67T$LT&c-_0x^K4@rPe)o(!`h%BT~>^0Xz7uP zKxFV-{-iZ)toi)2@xH{~$G#5y&1`3GY^YMVv@p$%P;yM%dFNyy5n-F~eqp2(2@1Q6jB1ue3Txt3JZ&2-%!EI5{r*_$O$U4!z+*PQN7pX<4EO z@V0HWQ`B7XQ;xMaro|_)7A&6FB>9`dpfZEbXQnI4;Eyj4e(PDD*^qzE?c4mdUQTk z0U%iDLCL-wq#8_|!ER`Ze0hlK#nuLLif%Nhuv8U(uPocVQadGM4(4v=TSGA5j!a`Z zSEwgEd`n;W99t|rozz;vS+AV!T=MNtW2&s0F`;mZ@G^Htv~X-={O`Ia7BQv|SmUu@ zoR&2F3iiTw%;&ztgJA7)t#YA2H0Wk#KG1iItz#UAY6Nc7R)3x!^!2PJS*Q9KsE=GoHoN4+2mNkC>~E_%g%Gdq>({u;SI9%uCEh82 z1yY@K&|no@Sgjo>}I)^yOmJT?tD+|)>m$>ZRq~-r>k*8eJ|bsg`sc5R6ws5v80vq z&m`0sgXji063ccSl`fPv&UAID?%da7A8U=vQ8&HEr4#(pokdV z_8m-(dWfIDEbqH))M+PM{xA*el@FgF4Flk_QKls3>cXz*!IXrszVe+Pi^OI4S9@5` zV^7?J?kzWx=nfA2DE(3Es#p_b2hy61tGF!C*8Z0S}r|3jaJ9 z{rgY<9Q1&g%ZiqYI&-W6^4C3t#69xcGm?dRiMw)#FDKs)3X1?`Y~0Idn@a_o8I51e zzo*Vr{VbgP5NjPi;^FOWlenk5lKHF7cc*k-hI(h0Uz@f^KaA$3i!s+1KSPFZ`_aIQ zyN@(QN$~d-ZCSMe4~5%SZNNdYt#JOThhGWqV(a|NDDV9gt7d zRHSQZQ{fWt_|2P8MAY6y@-FM z8~?{Kioa+7SBbPd72(bvY=)lQFT`kCp@|!fq1ldE%Tls;#pAUGsT(w`RoWG!uksyF zt{*K5VY|oo-B-16HKl=Ky_;Nm0Uk0rP;XwEi%eHl@M0Bq;KRO)5GK;VS^V7GX#tGK zj_(r%mBu({!Je>1J_E7uh?w-O1zDO(MPnS+lS}S6w1yVAmOqf@TP?j{9kbIFAT|6C zc;WFejK%3D2umPVzW!lZ*B$p7{4)SZr&zrrL;8Aw005DTf;JpS(U)z<7p&$F3D|sa z+)Gv&aGl;k74rKZw}V!}-BzcLvY7~m3q(t$^yr4`Ie<5vM(KT85hQ*m*dP&6E8H!Z z8;!n;1v9P7oygDoDhsUpx)H-U5xo-Ph!nG5kHl}CotoR zkb3gEs(PwDM-sRk_GodjxR#7n(WT5n7`g_VO%L z#U4Rw?fmNec^VI(LpX4R>z&cA6~4)@n)xn1ZSOWj)3q3O*N=zTcJ|0eg3|H?MSUDe z^l&z2SuUxQk+oV{mL>U=cc z1XXy$GAv#YVXT=_w9I1y=pC^j^BMfuKmN_&4L}Ts*R%#2Yt+s%NZUYjy5%0z`PBv z#u{1qymO7QSk@AyuLqd}cs!pUJtbae4{pHJC!*g@vMfaWlu+CP8yeeAi+*J|p+Q-L zuyLMSQX5eym|qv+LaG-rWwD_)5&q4{N-gPO{cFVAksg@MvtGmH22OkCKdudSyVZIE zb_aEH+|0dhC)&h(Z;7lZX^GzHm9?Ldy+zi5!_8a|_4G3CQs8rAQG7`+nX!&o$z^gs zz4D&^6m3T%N08Vb7me0gciWTZ$^lrUVnR?|OvxcckXydybnwJMa#tYRpn-Y$fpjD` z&h(5siO0^cNy9jw!_d?`w!?ahrUnu6}zW@z0wKGf2mo6bq- z+Vl^M#$;|*SiDFU7yQE65Yv@NeIWPhC@g)%aq1gL!te5$xnZvE?$g~tTMPAcrFMIp zQ{F};7K=f%zscUri%!v6(dX(UFEgu_9Gc8#nbln3F4V^Kvl)ALXbv|g?kp4~^9M^k zHu8V{$t&n*&hxC0n?>H1LxQ!y~dkYPb*G28)N6ksEkZf)<0y(3#In`3aH3B*}e`^mr4R}0JK=OnLZ4_=v^Jc_- zmFB5wZn&*a8+|#+lSHyl?e~(%+Ti|RLb@o9m#LnK7@!pTicJ3_uDSI1thn$|%!zks z%_y6_&Y|sr*K0%*O)cBu>Agb#f^72ofvQvTwP}OinXe@uf4*v%b*yW&(1~zbQTuq? z>&x@{`j&Xr)SCl7OOu7bY3GSbcO*aX?3702E)BC(9?B`2NQp}`N;XWspxRE`yDa;e z{aIHJdY6}$L@Wh4eNph)=mAMnYl`> z_v#zrq~bjP;(T9YehGda7j&=w3jy14Q|)57mDzAOFO@U1&Ur*>0N(FT9|qWYO1&At|;0o-J@E?oUT5b$!9=f<1|#; z)(;%%m_>bcn){BWvXp{-^QdhvR5TsjLX$rr9~qwK^A$FBjJYNYzpp8tp|GnBt^QO3 ziM+^li}pg^R)hBpn93X1B$%RKWEZ%YV9~_FtYebxlfJj3OVUTuq{IN{*i0dwaBT&6 zl;hVdo%<+SvTotf0q7X8?!&+!v{_DsXEf+~X$@zuZlWjoZs-oRmj^45zd3xJI}YcH zr*jJO1V;T)Ku#^KrgOg9qc7|dyVNUYNiwPh7x-^>ox)H+hKj7sd_b(CZ>wEM>b>7o z*3Fz@NENY8`s-ToMyS-x7W?RqD6;jv^O_a+vx#cq+RGR4tLk1gPeizxwvWquK{)== z2wxgnC>XunwahE$IR5BJx$pJyhf#`ek+%?y;_OOZmcEYo4R`I}SirNtmJZAt$k}2L z2NcLrYE9%f0;}hyb8XVk6!EtMRvY~D6I;Ue?5QAVqa15_8_RSAvT)N>#yJ&&cj3A1?@4P$%!Uk0aU02aWUh&X$3P{E0))C2^24QTj1UtduWNp2EKUx6icX4K@@g*t=o}fI z?db>kpA;3|xO?uyp&sDGGloMZc2F0H!l*e`yA_1(*fO{FB?x6MvIExB7tc9A*m1kN0ZY%)yRvL6N$Z!!r-CjQpWGFKn0dR4#q{#_u>KBpo2*cr8M{=#DiVK?xSG}s4i%u|2h+ZAoew31+h~W$8Y@RAb zOg>fHg8gybT3t}Q$3A)(KxaGF|3e~T zryeHX-a>8MD}ZKQpWdp&Yv>?H?^!VM#0PrN-FAOuq0}NYMiRt%FRlY%ZW|2yX>pwB z^OX6Obpz3*$H((Dzl}$SPqW0iH&z!S*CQjExk#*-{ICU?NrKV6lRmD`+APn?f82h% zc8V?k!k}}PG3f87P6s4{^Ecp7S9v=a?4NISY$U_UV}vm6M4XZE{4t>fhS1K@f-E)w6S=>9}df!k*TBncTRThB~5I4G7&SsbOe+Z@^OF9$- z(b+Xct5F8T-*HX&rvstPGf6@81M5rQa_0On|21joT_{6_jol-b9Fz8_TjvqM zCYO@nHTbX?>A{5(-Wzw`mC1!`_g}*gM#zhN;KsAbtubdC`=9e*a3-fjJS~7poM&Bs z&;v&P0Jv$VF9E-L?QVb78C1STDnwV^hy6eI>i_jKigv)U?wVRlj8f)h>NDgq_x4$m z$#tRGfs8tS1QxMO5C_1U^yz>zHgi+wWdX9E+kWkWX{!5##p|d;2w0?d;RQJSjh^L= z<`)xSLhi$`gLV_dfh>AT8|e?XMr z*WkJQPEd71f-qh5d3W4#I<7434Y*=UJmSH}=WtH<`ZwaUI+9xP~tQdfv1J;Lp zggs5+vc>?9H_JaBBI738xXC>oB$TveDQ`q%zw5}SBRr- z4Kn{hZ&3|`Gh74FxPse!gfnvC@Klsb*iwDRJDE6j*2|HFR|y@<6sn&>tl!2#FugsQGH4w$9s_pU-L1LiSZ1E6 z&MheBpm&uWGa{(U*GB@4oq_0G7d#`X0|zz_k+eMx=e9xzqa2}KvdZkZ zy>-3$;&yA%uJSD%^r96ZGy*=PLz`HsT-N)AOG^bs)%2n)Ne zthiU3$yptI6n@`iMwZ3xsxeEpbhf3Yh_a>T=4VV;zgJxapCJ|m2r6zkO>7qKRj2^2 zyk{1e)p-7}=Dv(ruTYUiV$-nWV+|;w`R!K0*F&fm-qi_At@uw~^Y?W?xsH<&R!~J3 z_vVEj35=f@M+N!5v;wSk5~{hl%j?8Pb6v)+=?x0LPB;7Da=SpH~*sTJ>#n>SoAe7&W#rMal8 zxU>7x`N&lDWNMnkeb=fgey?qX<>rw zn$jItCXscW+WI8p&n0m)VtV%FQ6<#lt#vXnt!sU)raj&lsI$T+p;4rX)K)MC(y@Ha z8k4b=^)sOEdG-Ce%iCVnGM_qK3*`Aqp7f<$Sy28xAIRIkQ>nFwmZRo!B@;$&vk)A@&+S<`$Jlhg#O;}YsA z`o~*6t}S|jxd%gKfXSEYRRSHVhu#TsQ}Jo}n&|xt#Jp^sv0tiTMS`8qJ$%-ML)`F($l_z9Z-fLBzCXgt> zNDxr=BS+(*FyvlAHSyLH^mNy(zX2PQQI6%k^R?Ms(1%t&f)K{P6UOeEj)-}C;NJnE z<_Lu+f#^;*CAd>0|?sK4+)&oA_T=m6wqsLbxlLm)wFjVAI-0IIW0Y^cU*11r|L|dT5{ZNwH1xf#!ayL+Hj8)Wa84Xbnw$v$nO%F^Uxu12GBa zga}`ya!0t#H$Nc1GzwdKlx|&mjX7mPD_zp}Vb#7JXvpt;P4*d%BmQTICdLOT+Iyhc zZcPQEZPrs-ftNUCs>gDMf5A&IM{BZmGx!&~UH7&Sikm(mlQU-K{PFgWGbcEAbnb;p z0jXd4PQ#m9J*kOzDV#iBUpu|p;v`GZWgT?5rkF5-7|fKk{GlG3a1P%J-Aw(PtkED; zi!cD(_X^bTaIz&XXwGt>#|EJ$7;84ZIYFZD^^_q0bjXv$3qeu?h9ONwR?B&j{}|sc zDK*!bJXZc#AFIqw;+|+`#I^vSQaCyEwiSi?H}m{YBCUgdPX?tFD7i`3A>;F?%}&V^ z#VkI{vvS;nt_jxiSh2f)ng1rW2LKjSAB%}H;V*jiVvCLJ?Ln!d zY_pO5$WglI_}u9-|2y9;%SmC7b`D;QhfUaUkfbuJl17 z=o{~a82B5ApAQ>{Sz;bmHue@RCGuHK&?n^W5_t33wkG21KS8E0lav3l%db?AA{ZjS zP4NW9wgnyXep1v$RwdxlMic*Z8Pmi|#((=n-29u&eocNt{hJ~LnQKtFYv{p#VgQaN z7)kJxrZZqmP=`8ePRBRaTMvlaQpeD1unu*L1O{C0I6dBY?cQTKTgp6bq$k6R?>y7I z4?@_Yw^G@*0Z@hnezQj;AisGd|a zEFv|$O6bx%62gPYGrxX5L5kAx(n?cCGJ(bO5mCMqVIfOHnr}8><~xzhTYlAhI>2vA zQcR?CWO8E2|M>0t3&al!CG0&1tk>`^?oIjFL-2x+#Wd>qcrFtXwBpk#(0&45{>dST zkOs2;^(RiF376OuF|fk*y4 z4g1YkDBNy}5(G+dg`J(tjN_d{fKBo1zy2oMUiht!1O`F7v~&$@Y0kgP{WFGYrf7!r zZ;GWuy@Q(kqIX~XT2P88N-q%sQRyfh5*tkfR75(FCeoWgfRNbeO+Y|Eh=>RXA<{dM z-h@bpP?HEqPbeXf;(dQ-?wxb)-1}c9A;U~&zk9E}*5`R1G3#Bs5z@xi#8GD}Fo0e3 z^>v8?0e|ef-}sgEmsSF)t{EtbEw34vN>vj{Fz4$%n6aZNXbd^Wz0H$ou{4htNM9UR z?=unK57f-Vi+ILorR!julcRh~Fq-OuCO7l zJT`iIuPNQikE8b5W(1}>$_lfr6Y+c2;_;BO*cF>^(S2o};!k@T(p^^Hj~lKX&0I38 zeZT=~7EBl)ACmpYrYSzipL$^N{#1ninwr@7+E!Hr<}QJgdB4Z1o^DcmTEjGJr6xj# zYq>tV9_6N$)T6Wb!B%I$B>r)h$djDMjj6V;I4iQ+&>9;Uo!TAMcya{SW*iG>DiT*^ z3rK5DS1`{FuCKS<$+e+j9-PT5md~hAqq|M)TfL{+W`fW!jk!(nl3K91++M)kRy7Cy zy2Qhh?WM|Wui0)fb!|~gm-+j6MQ%OQ6H+?5VOQFJl)=B=nS3mn?yx=}c@o|+(jw4y z5Yo|Jr@UslYmYmQ{jkv!kl=U2ZrqPze9!ZK^HEjSq|D?mHIM8M(+DeH&9YL*P*2z- z)}z7Ne{#qRVU2Ey1luQt#FRwz7=)sS>K^u$ngw|VwnaGvqo_RdWiyG8hZ(=zvm=)} zCw`;miUZSECNh6~Yve5*+mfQJL0##h_{168*E`8dZ?K7$?_lNlnT>U#_TF2~$5I14 zUUh@kOb4F)VXk{APnV(R&qQtrQ@_ZF`dmOQ9e9o*cypiIBF`^)sPD`<*y%hoT#-6y z@}(7d<6Fr{fB{0hY`F)V{~Z@1gZI4>2pV|fANQLzJysAukhDbE$1Ht9c-!!;xaTn> zW{a4G#SM^E^K1KO^(=Gj$3Ca^sqcWpT-OJ!(eCnB1|zbhvO6oijeP#FPY*uuT~73? zQ&CzyNc3hFS)d1=luJyg3QiuV^SUvK?q`d>4;*YQod{FrOQ`Y~aF4FKrMRzqXgmEj z=|=PJV{l=aoSbBHwwg?F*hF4nY|U6d^)88W_D4#NXI8>uh_1&c{I~Lphw4=)*|$p1 z+l}C4`>A;aPlijrc{F~g3*IpaysDh1Pl^&JwqB#vIg%`B1fn*Cn>K0n`z7#GmmY;XmiabmWMyv-nU(8$ zd@&%s$PbsHP#dJHK7CL(J9OK&q?%F1xtr)W5wc8dtj)EGOhr=c`KKUJ&x)IOPe0u; zh1eu2fThcjtrTjLl2{@s(8xstcrLgjy5nP%pVFqj&npC7XI+~Rgs=-#zC{h?O5>7S zd#D=C(6X*$xB+S(55#VKK&ma^e|^Uj(zTa%T?@uqmRP3YtOTK-&|{yNp{0F1iOy#N zfgAGkZ|$mF38M{{ST7B(wp|6jB)W@J_AR|!m)4VJXN2v}{>)O4fxl((H8-L<-(#JT zVrw}Z%+V`6D+eV=$3=&|VI`b0Y6xt+9Wy*-*hgx4JbRBTQ7$c&SEJ2MCgcZ3f~>fC z>^t1D%9odB&?C&i>x4x8OuH8OuHuzZ`##rcSqDI5+2X_}a55z1K>SyrSICbb^I_|V zm9KL~q>?R%wb34}J;elgU8OVRKCGVheytReT(ij5HWS33R zS~B0Tk&Z8Vz`M;tJuzMN`aDBFDexv(d*TNSKWXY&u6g#qg${k$7)s)nr5j~uTc0vi z-FIz(r`Cw2dNCvK^7~i_L2e?UV$ZkEn58<(m3EA;Q2OB9F2kAbl8Q~R(M#8HMR#0L z{?PIPX_I=bIh0e#yyu8TR0<61M3QDonv)g(v7wB&Wa&u$%UG<;z>bvziySG<&Dj(tCOYtJPv{>oj->D zmWcWr7RP;OYkv)W=WoiN2NEP1SzCij{kBxT$?y!Sqj3Pp8TEzvO%s6j>WEum|JZ=` z#KV<;Y?33l=?@Vj6J<6t#L0MPnG*Y8h8ysSHUDayY!=<{hec7C;kKN>V&#DX; zm7cHZt{+)`{@=F4JpX?Gzfg!&h|d&&+)mMnc%SLSQ%k$7EfG)>#K!DdEaOGuJ^5_g zlM*TSS9C*ok!Y7cB(aiL07IGjGTAjbC@@hN>FFAdGUI9i z_+%)$EELFmp^!SEd@p^)*Rba#Vg=g53cISYZp`2Go0opzbPEyST~P4~rc8ABjw$tj9%ra5VP%GSpGqn|cr?7VhzA;mm zZT7*oN^i`YgM(kVi@-kfY)ux2^2cbJkr-<^Wp~A7t?c@yQ#)gJxNGo#j}gY?81Ikm z64}8y-JUCfbza<1{V;1_X}U*$2TxM&d`*>9UgYAk6zw>^gd;(hSZ;3d#SGk9*!|x| z>Ag2QQXGO(KJR%gl?>kpPxAWwlw)7FF5I?yc>v*K94BtixB>QQg$P+7Kpjc3qN(2} z7w*$lnjba$w{ef&=Iw5^4zS{?m}9I1Gb&)kCj%iG@C$SUAkFG3Gr!r2CDAxR$Q!*s zLF~!(44zoFvg6~J5mNDE6eO*AQj6ZSX_Y_+xVMtGdODA%xdrZUbhvXW+uyL(3k@$?FeGK+Ymp(yr&> z6QIozo+Qvr0Rhv6j6t3(C(%5Kh75@J*Q)uonK@FZ7vWB){_5_3E&dEE%%=fSeucAN z8qJ))-zQgs)tImMka3V|fsJ&ENV`FgP5QSI@9#bCUmc8elBF?Q{CCdxEkwzWhJZQ% zyV=Fe*2}b#61W4ciQpUKAk#WI+WuR*3O(1ER$QO7Y-n8c(H7)4xeCj^c~SY{lkxFv z##xQJmxzvQy>7JV(Txozp6fJRz5j;|IhmNL8^31sbT&1^%{#g&+OK+*wT zks3J`lq|MBO5-80UMtuB5RO>C+E{C;@q!e4AmBfsotzozklq)Q@O31N;OxDruqw-b0cHl zujot;fod!}7GjX+5PX9LK%0Vt=J}|u-Z(xd;l0g>lFcolaAMW>>@Yr~@*>;<*|a6R z)28PgBgDDP<3MXGr(iAC*Ez^Inbu-N2bI-s&vHoz>PdjXqf;xw6`9=S3$QS@F&mS2Ev`F&6A|gF# zG2*$s(0;CuwrnhVwg-|<4Sn9OaTtA7-Kp7(2%%usDhINWD|mJZ0%YYvvqoTxlE4zfx(4;np>>S4Yq{yJ*tuC`O+Lj!T>olwag?2Hxcss zee&6L@YTkhn!d{)em=eWAjOajnLj;r>=5ByL*Yqg9HWR(#b~+YnMbs6iqlFrSdqdv z7JQT!XFqEw<@%IIL>r!9^boq-HxxGMbH>pT_l6o0lD^l8CdDkLL(8M$KxA{ihE7HH)qn^;EwNYe-&)q?+pgg&U7L8+_9D0Jz{Ph zh$}Q4{So8k7+7@9eX??9+DLWmV|sxG@2kphox$|t_*`sy1n#V5zL8lT>gHT3(=gSG ziklWUi$~RLZ}gCGCtzvalkeA#_=~6!oSnC{9uS=88-nmlArYj5+FWc{39?Nt2o<9> z8G}$+h4AX=MWCTHgfZt`v87*`V7pTJcEczAR{P1I$cQT{>8F2p-BGeMfn&V6R_9ky z==TZ2^ObNVy8}L2i?z)ST`R>XOz245e=X3Lhdyk;@P(i0#L?6a97?-oT>9n?!ROdzFgfwuj4giObPT8Sujos)=M z4#u8CdZCd7#f?4!51&z>cR6jL`&?u#NB#K((caZr4CpBYm0`mW16J!h6N0T`Jd&I$ zB-4^$51hL4eF8?JZ~cC0%=~5!0%j9X9v2}8epuN^F7xY(;KEm@%|MR&4HKKVi-3Fh zLXO)Q@+2di@|J{pt7Al_6Xh`s$?Wm!V-n+z3Ef@0bGnFh3ZPaADuo-3V!h1x7)lgW zoPz3l1jhtZ%q8WQDJA{kBax!{LD)wxtV|TAddKja>;%mMg;M9%8jm$tsKaDf0rh0c zTXBuj^Z7HQXe57MDJU4f1U}DfMX13#7I7VD5bK=nw~F!ofo+NB$KUClOx`O4u`@K7 z)g*FjE{R8wb|gZPNtd0mu5jlSQVKBbGOvD)Ev1EA?NegN8i*to4BC_xx(!R`lVP8p zUa?v=FO=24CN2bwET%!c;A5qNJ@>7Dpj0X&TF3K8tR_5I2_vT>c(p zqlXerj80~a1Cxo^Mr|7pH6v7YsQ#rHQ%#T!oyRRR?+~+WsyN{HQLevGj@$HwPm2&$ zLu<5DU*XHx#oFB|%ayv#e{7TMAVsgJa+W zR@4Q440|}{-gI9U(Ji`ts8AR8sr4p}L@fb43>A+7MmlC)8a1W3^Kt?v`Cm_or5NT@ z>m6&32v}jJC)qOLGc9@%&Dot1yy=xa_$lO+n&8z9O;DcazV8JUQ4CK8fpX}r=<=zM zzpkYgnMH7ceIG?@SmxrZv?PQc!oG?{cpf4YR_5nd%HZlB%FE*uN)lM2lfOwR(AAZ< zBfiliyKV&dJ#>Q8F!XnHA7FrBxjPOhx7sS-c`k4S@#q|4yuaVOycr2QgT!2V$PTpl zHkwG=G5jcD__acJutam5Y*TX8$GlKsetrGLZd+eR8)&sz(*B$PH3clGeEVz>LA&&M z!cVp6)Cs62CkcBq=!R|8flUYLAPS)bSC8&S$g6aHv+I*nuI{RE{$qID9~RzaEkr6JN? zN2ZYqjycAAhikEU1f!>qjLTv zdaI%2q2(voIyH;=x!O7i`v#ci>);V_KBpmW;3q>l2K~?JZHSMU@&RI=aQcx{=v3nM zfw4mzAvyXbmLGn9WRK^fgN|BVrbc}(__<_8fD!9JXL3Dgazlb_2CYq9Xx|-_#d*2B z@e3|a6Afqy#f0Z~pm8Z+c2INEifx>(YeiQ21T4 zX%isR%qt2x`{upSmb@^__+>LkPMnnSPOty;4_U(DmyCJKH?G&DyevK>@X5BFczS(~ z8`p^7L(FDRc0f<#VIIEhQyvHWN->w4Lmh-T6io;gb;4*0l1ilbcA=sKP+SYQYDVPu z&yZ3>ol*+rQgYi)5qdOA{!A486waLPa$Cb{RuO*sW9WKaq8JM%LbXeSf;3wyp0#mwFe94?xMB z+l~rnweJ5svNqZpYz;Qx4}P0nZku!@K22PRJrA3qT8?<3A2O5gH^xm6ubu8&*`AyO z3ASEh*i|v#qrp6|rmjZd&e`DmB4zH^E6owGeF})6a_RUAefEj^vo{UNy0}<>VFVGMlG$L6=~+YA)S( z2HWi1Nr?=c%${PtVrf}3c*uHlm~OME$;U8thfFmG$+~K((C^AieN6H~yI$C70vKor zKwhBU0(1m$iAugeQ*3VqjpwaDc_m-A`kZAIq}>Ldwd{meC2!^vpzJgr6Ed{BBq-LA zytw1VKYikTwS9qKmw)Y#n&Gcz7buubXUciRwORN>@;4M!>{O_@yrzPDZNblGWEtxp z8#29qFgy)5O8rW4i)0v3iio*@4bZ#X>ubl{E+yKh8ulg<%(7UI^_Qh0u7B`iU*^ix zdYA2@Hu7NGT{Ox0PUm-s$PaC|%T>p^tU!ilbSp-91I;*sthL>B14rQ2b2jpJImBg( zu%9nQeZ2C-CERjwtoC>{8I;s)Mjq{IbW3E2!6vj?Q?6#8v8)O?5%O5W5$c7C#a{f! z<^{NK(xUHB#+g`Z?x%?Z{y>$(hu?^|<4eO3)d91%9x(Puupq5~u)TSbpvVrZ{UtrH z7VN6rZ!DV1r6mra^A16jD55PUj-{OKdL4kr4!+-BQ~T9%^n{s@HnnW;ijJ**6U|K> zfP?5SWRGU+$IJF-IAwdCT^+eRZvSHo#%98uSmJ!41AE|^=nzz|(_baKlkoF64^}w% z$~ym%!DdOB{f)YG_hP{v14%E7wnYGN^eqMWALs=|stXpKJY`mibYBhDiZfJly2DPe z+5vVyN_l|YVhZ%{Z045P@(ZLO!28+bH|o}b`R{x$rSD^jOIWXt3`Prq_o{tN!! zbUKwf+3W~Ne?6(TlKSe8| zt2nTFAT>{a%!^n4xMBjbe*gStq|0uq63tiPMUG#xY)wk-{vu_<`~&F9@)+LiQJyUG zGuAPAdUO#mP7`DGQIG24;P#|J1#jV9>lWVjl-o*Ie?90E_peVkB;tF7JQ#RpE=vUn zS3T(Vwe0~*-ehfj<%&<*7M)z`p%MRC&DIIcsBd!kN*BI zV=np2Ge2#@SH;=Lsxc!kIjv7kDk&WQHL&Zo``?%EJ{tGz7}H;}bNA)@Z0}ArJJL;n zqt|t~m1mZP3;Xgy9gpj1QB_ToE>jnOIT#c`=*<=Md2H)>wi^p(Nx+RLD_y9Iv$Pqa zep3*U+lPEidT=%;$7$~#DCm4BKIXrq_QprA50c*@pUIo`ESzc)Er+R#JIJ>ZwD=}U$wURKm5#|O26rNj$R9e182(N1`e+!Z~@5(svER}jD z5^hXK$}@^lLP674)IrU?ozH}696z+qVt-~LE>}=`qA_p@p&a|VF>k5S-wMQoSQWuj z^M~&h`RI;BSuFnYF7;?+5A$XR7JiGCT>PRoge8|K=29VW9&>cZ&ai*ze!j^UNX|0I z=Bu$Pm~RF#iHF8u-7);MFS~$Y-?Pd2ZR7D8_vbUdVjF50(Nlv0%gSXwvAcUe*M3g^ zQEyLln+H0Q1ECW)LA3j#wl{73(*!E7UHzi^@MmvBdnKHtBkXm4d0v~0i`S7L zi8*&5H0!cQp%o1;Tap&HKA83d3ivEleL5J7NTkam#zCB5Zg({sWS8#=dsquYwoI*s zFj3QB?9aWCa@s}USmw%u>y^w6b)S<`8&}GcpZ-FYHPDY#1Kg_VL+x8X_xXyE#wEWb@HjF%`=570+%*3NP&gbE#5E&#k< zaFQ8*z$$w_P`)7vxZ~_8SZhE#ixmE>OX|V0VP8Pvkf$K7C=f&bcX^QZjJI@I zDt=bZ$ctJhy}2cB(qCNFt*-2(6+UTB*Mu7m>+k@j^J!W# zUN){ZHk_9Z;%;gF2~Ey{_1K(9p={-bE=Cx4gM@QBY-V?1kJpA+L=z_~>!OC;uVBNS z-lxa@_!1A3pJMo!D8yA8hBRfaDB&q@UB)B(&_I{Uw^Gu#U_Fm|)*nY1lg#48RcI4F z`IF0!CoYp7hTd{|;5qI;#Wlf=dQ-zG8!u)H_|)2Z>v;Ni9x@r{YHh_y?i$pa($B!J zC^DOO!zun{)$-3Z;JVVYJf4B!lD<(IPef17Hoem58Jk$xSRz6rwKChWF;I4$muc2h z3n!a|_Z#8VRiQ)9B6AT9`=3-*L!MTw8#W$zU>K4>WwSyteZ9z;%a+WwHrc3Gi$?lW z!;u>^BcmqQOW81LhtLYX?NkGyN-ves+l^!e9*sxkSswgp`08XMI= z{9}{da;#!6-$o<8S|O%UKMvYa98lQyqCxvWQ*PMvR3R_9>Kkry@|TyI4n(>Ss(8!zki2{I1p~EKiMgeEe$J%`dMfcAlITExp+9≫`uLc^5 zKThqV0m)05?b&r3gaQw|$@aVb=M(ZZCO$#gj@oVqkA8mBJ1+__k_fR?TXR!yIVg(S z&cpx=8q@qiJ>^69I^lqthbr>On6P>2`7JF-3D{lS+?9;z|JbheJlG{eyF>;bBSEyN z8H<+e{f&K*UW;!jUoRQlxN>Ui(=i*HZhJEwOaX$QH4YL%a08E@Z#yo!kurLdN9Z_p zYC_31ar#7nk*~~r?4N|w)6wMDzhAjugfHt~f8m;O<}p#Srr=qB1jo+R;~Qu|HO4H) zdT_Q}An+u$N~uq&o;g`&q@L#ZVn^kDyx#<+2kYMsKU|80VLPF(P#3@gcDi+Od*ddl zALBbN_eV|+XBOYIvNXQ?oz{akDuG|8-7dlj-f$1IXYeR!I#Mei-(V4)cQH8z6NUV^ zRe17%g9nQkno|Ken7hc9n15_X`*n1M1uIYNsSU}|W!{?V5!u%a8C_YXDA^vf z;iX={n5M~yDlQl=9f~tvb|(GZKC$Q$;R!$*GoOGRmZQly>G`SK$PXt154e%{+!nUB zR+gtFnLA*B9eN{bB7<*LYD=Em_&ozYZ02JgwCc@2nM8)&0 zLBu&80uN{Co4az#1ItpOYdh%+lE-pmGx#uPY0!+3LH`edaj1sE0k@jNS}xNd%c;9- z>(&VV*&_^9fm!T>eX+pdL1ih{M0Iq9iPEJFpL{VpepZSjj8BsboKAg|>@Eu=$R!2b z*Hj3#Rs78C#m@t2@0RJrJQ*J0w7EnFm9m;0gH1=e^$TQGRA!NThA?ar?u=$k1dGJn zi`Uq7o!NCv?*ANM3;s|q8zqfe{{2(^MT_l5MpUbeMbWHX7+>B0!BNKTX9CCROL6D3TvANWf_36Ugs&_}4|?+n!4!_=$426E7-DodYZw8pz)}oeAx;|+L1$N&GKk@i z0tBk7~9tKz~3BrzVpVhbr8iZrb}k_|O$vbYuIfwjob{r@C2FhvgKd zE>hz`&h`CW|giE(Q*OZs@_A-0Uw z>11qoLC=7>XV)C~M~x3hPH!n7^wwJq(_UQH=GrWydA8rT`Z!UNH9_@%_X)YVwB{fK z_Ny#B`+S^bFoCMf+zbR#DsFG@g+qB}|7No?&u1)O@m1rBm@Q?LY3iQFWC0h##m`V- zhBI-{w;g$=l^4WkRA46cSmb%OJ0Jg@SMOuHH-ww(+I4iQe(T@QA^|L-8bA3U7i6y zdUd9RgWgBtTM!-$+qn8iep?}27d^raTdigO;5^ymt;(dn+u$sm|HejV{HS+GA!QRV zUlQ*BdUZ-Bo0U~4Vjc&P$g6Tui*0>;67iCS2i5j;Do$?`anXo#jO*k`Oss06n_1kp zz@tHJBl)pPy^9a^I7^&&#C5wOwr*#dcR&48ynzlpW0r15)Bz}ilK@LYJ|LP!F^fJonwtsklJ9o!+~1LkNiz6&yyRBkU!Ie6BLuLM)L?%u;DaY`PwZ)X zOa2ULjEOg{33tiRH8Zt-s-C5AaZ5$Xi`?O?G+TsSC>Q$qJ=ykKZi}g#MKz+^4(#R~ z|4t_0?bxZ!r|3SmIL7s|P|y3P=JY*w%Tf6r_@)4SMEc;*pW9pyNQagL%b(l$8!V1A zNfC*N$Cj zy{lHJpQrNmDqPly6kMaQA^+-2&8Gb2hTk=^nzP@v7(HTIlbH60#-b^oChKupwUwS~ zp1$f~MQjseC-lKJ%);oW-^$>ktSbmB)&!)6XVVf0tu?D1mD`I@F*^>+SksQUd}Iip zHagVll!ivz?a4Z<&>az@dAc-E0Zj2Hi2J5AMW7QU%AN7HUm?c1y(wml(e;T@aOvuR zGO>B>V{Dg^t#fVe)ml{GN;nd4NhQ*FNQx%`6te~zwRZ?tBpFYYr7ll9?S4*mI@M0y z>K6+*+bwou5K%ZgGa%O4>;DRN^t4_p$-TtKG44&gsU(+1Lg1T-QZyNU?Mhl%QXT)w z7Tq~{-PY3QI_urAWrLY*+8U-H{ljD#_uABvoDBT3mDbR|zGx5avsu^l)$f03B{jL@$71*rt_TU)fH z44us(mF`x+T#oMT?x4v`W89|e!*KfN*AN_v-o^MCu?o9cc&ph5D+)G@940!M$aQb) zuvXXTVPf?xtp(|hq+MM|+zX`Nf$Na%9>R4yQ+wR_n$?y1JblbQ-q&V+xxMqlO;1b% zGm<=wp}rcyx+lM#fby1A6TUk1_)BNxKNktm3p&jOubLCG;+xwI+_g02uU<0GFpfy5 zxL6=Kujq_#ZaEas8(#%+eC75o*<=e1xLm=I&C!5vjBtrpUWGc-Z8jhIM{UlRe#sqY z=w)H3C1EJ&3BLtChP`4(a%8ItE!NjVQHI=_99|;D>gF$=7V7KnNezEl7qKana&S^7fp3O3SrXU#V+t;9?XVkv(xNtb zSj4bD871<4tY~@ab09RmW_xO4(ru+@6GeXl*8|W83>P4FsG=sQ`o=mazk86%$14K+ z8f@74sN%FsL{h-YX#sf$0rECLxKtue!kx*`cI1rqy_ml&&G$BVdo4Wki>6diqLfkD z$Ii7>t+E)vRE8S`og{0XI=?hK4vCk-E0sK&A8_9PF{qqv<&x}}7)M#~e(>Et9n-mT z)+RM}{DRYP;7tS3<<@7ksbO1&TcgV#oSQFJEQuRwM$`VLW!y`1kV_=X?S|&~Sk`)E zJ(H!+i-3m23=h7i8Dt+@x1EaM=Da%Lc8R<5nj?y;hX{bVQUB5=i6(c=N8#7V89clS zS$^b-x*JVbMs6)stLs?)T$#?blYMt}bU6TP3xcLD?Nx9DqRrD~5i-?q0cME^QM6Tx zoL5J%ehCtHS6s=xu76#8+<)0?p0DonrNyM%Cq4V%7WCWj0CLFY4OjBEZEan2N2>%Z zwSW3eg{^zN^<517Z5t++HTC_kIr?OCs{7vRVcs^?LU24+2wRDdILb?>8!*CYiHjIv zm>EH)ZBt?9AtkEee5yrOh_{feI5-HJR{u$dEBNX~)0*#hw8Cz3gRr@SlwRV!i##=kf`2 ze`E#{!Z$c%;ZG$DRDz(>(f=cC7ySKYCG)!RrV)aZb!M@WHIEWNqvaS-o_3UMy8xF_ zgKNEOhN^~B+QwATE~e3uMp+cuehpAq)ndJwreu=7@m-DoNWbRI`)}u#Z;&{XTkPsh zC2|cEeNDRi*MF~f{Wz!Ce=VBX1Zlk~{AP-n`N8VzK2Q zQH>B1-`|Vgn4~{O;dy)Pt61$Opw2KZd5KyB`HO9@yVc=8|2RfEzQvVVl$VTu8%f_7 z^ta{~ej;|?!rXuEJOT$2uh~xG2TNw!k1UR;@^CqzKaur~=rcbMK8KGX97lX#+jJ&Z zH7$^3go39N*h3V1az_O8!gb4*=s(W_vyV*y?ZRq*t2fqQpO&kZJ%ct^|2j*Ku+AA{ zi9Jy%0)fPhRQ7v2*d9K{05Et4Rf9S!mJT&3;>E#X$U-A14(=}EZ25(0hNs;D6f^0- zr8b3l(Q?^sRpNiL^w`%H80Y(Mp=t)()90`qVKMBZ2em7ZqIKvvH}LWQqwGZf8~%SW zdrALO7xBm;E9$y}UojS@Hh6{$6F{S?x@;`vzu*5?e$DYh@&~0^+MA(~06rhkz-*Yp z)(z+=gmFQB8%5QoTtTUvsH>USKkfZ>^U^dw0Pwv|bNI$i`>_wrT5$q6$H_Ep{n!Et zL9Qb9dDJH=X0=AP;Bd!d^hMaG;kBVKANrydkf67fwsNAxB7$e$n@wK-t&!k&(L$nfK<&H|@2wVm|1iUARYghSTl z&G)-0&~J-t-&5e_RImV_=|j&fA7!$MUgG$gB(6f_^^>{V=zPiCG+TpcK0M8TZm3+onUk+SmawY7Qn@qm#LVgrn zH~`M4F@M@4%K^=sqaX*_52*sNYl3M4zj?I`QA2SaJF#Ui#~6Gx5P61V*~K$sKx&C@ z!-7E3mbC}jIdcoA;X4!nQ|%LcfSH%v4rX}n-Jm{WMj5o3#T@l?|6_||$pftv>grcp z&pJyh5-&Ge)>p1u-$7s*U%G=vbR_+9e^|8P%oAFONl#f00!NUY7d(I;!P4x!S;;NA zrMlrl!pbCcVvcoUj%Iy}O8|N!Cr9ZBU4JFFb$2FqX;Ig$(D3;t@bA9RXlm8s3>YG@HVAnmzMG7>2f;Rov;g5q+-$hP@ z=dlYNKKU%4FO735ToSH(dzjxeTjr8zx|*B7O}5$l9rQU5{za4xtF{Bl4Pu9qocYaU zi+eGzAs(QanV+cB7!g9`UA&`Lc2;?Q?cUO;L{n>sUu+%6u19T_45g zMLW|)S-9GT(|cmj?)mHEi<7NVu;1v3I)7iKbctExubg#1a1P6@?Ovjr%Z*AD|Dxy4 zkMBROj}?)1(`@timQdtp&;K)WB*&U3#>EMt6!`bw|^@raF*wnisV>`e*dxp zx!a2wS@{#eZEc5B7a3jAzF~iWC2%HJ1DPnEQ*y6AZub2XO9e_0 zhPWm1j}4x6;0KXLE@G5b7@TCpu}iQIyvWTVxTQq_vP~CYKp&E?WcpGt)X0hbL}Atl z-gjf*p6k1=YAs127uSg9fWEQktsM&8qwPx}Vi;hCzJzg2<@X|a^L#i9*wGO7I^ z+ga81tm;Hn`R=U3GUY5gDQEZe{(o#C+EbIH$xTgi5dqnjYu=8n{>RpVieKqInwxL& z4pgl&7R?k& zp7D1l*RRRrz_#JA{(Jw|lHNfikDHCt8nlUln=Ns_FCLS0vooC{z_=JQ0NTKQzuL5Ew#1OPH9UzB9)tv93VgXKZ`KTL;P$QSvg7l_q>bDEl%T@M@p@5 zDUG4wYG019$&It=bW^y{qz=fHBu%l8M5DVJwe@bURdxpN3MFe-)-Vowtko1%29$pP z{B|g<(G;@mO95vpmflyDTGO_dp@~AGdSf-6pD6 zZ6svzODm*44Q{5}`i&y_=FBdKUj&SgqNDs_vj4|)HzzN1-@szsd9uf%$aZb_+a6E_ z-Jl9}xRm<2ueaRZl0CG*_uyCi5rDL1^yRZ5*&@Zo14E^{y#S*6}CuRqYn zy3kBM=mFS)oMQQ9lwr1>>-isCkb6D1jz{ zg!TB&rja~7=EByWS*b+I@O#G35X@|VM@1Pq3%*kn$_<3{HNgjxF?uLB;Y5gAL|I`p)?VmSC9`(DOYlcvR7Z$%R4=; zd=T?{)1>LXo8QbT^ffIq!@1(nM;s>G^rSeqslh$)Z$QJSg;Wt9k`lYfgXbhncH%C2 zh>MeNN7(P}|ElvV+7iH=T*rTPb!-Tq+?fwea|&oS7^fh`(mZQ$bsb}ohP$I7ch86F zuJ5?9I0|ljM2OgQ_<1kePA}>Aa3Cz$S^s(NVa_-rWb)-%icIM|wQ$x7By$;Nx#>oh z>~uIm3nf4jpnM3WqQvGWyZEodH)8}Na$f~VT&3T-1@=wjX8dDw0s}wX1IkK=_k~U^ z>H3<=)MKK4@9>g4EW2aSa$5aTT;Gq6*)Ll@Nosa4!~w9H-$6r6$rjUaX^$v^AR%VWC9DMFSLbamlHyH{vZ^9h=Pwr6ZynIie_a?zs zW#&iZ1;s&V7P78rLx4O(aC;Txn=H;rxnuPsZw_jdu0K#z|6T$R#IfgYfE{~0R?@1= zJx}Hz_K|rO*<*pmAymMM2Kh;=AItXhA$}12@@6p9JsX*2;Qw|g!t)5QumX53T=YWK zTy(rwvjDN00!D{w$xrm9-gdDtz3hilh``xdc2M*$8*}~b@(DY92?_m$>jDrA4|c$z z*(--Gdtk3jtZz%{mKbn*AE7llxKNFVl!*q*t?}C0%a2)B-1fgn0i|^4U)$+0$&;zRK0R|XbB!Wb-FQEMH;ylrvJ#DRg z%?Cv1t0A6Kw}@>l?Q@Hw~pMaWPU2fZ4+I9==x85K*Ocgfd(NV z#o%g`2M7tWUUQwLEr+q!E7{A2EWNKM=g!#zYmd z%-o!gjM@D7=NUH7a~l+eS3mLoPh%gaRTr50qWOk{ryRbk`hng{%2 zXu+~#B&hC6A-U)lmKIdJx=iXk@@8bbAK-|p^Q#nGVBdCr%i4#jZFwor4MS6kFVnjhX+4ZNw?zWqiVXdzM#?vX>fb@{itSIm^NZ@0 zddmIwN?WIuzPK}K%OVqqxU=BDHpPm;1Y}rGufsLwTh=AG8ZEhuAvCuCQE`v^{)vXS zPwVUwDU7~G(G2z~?(vJ?IOlS}wpLi*sjpE{<&Z zNb%;xyyo>;sUPwb+*gpHajGWaU-J0_AeQqlc_G7!CN60iW$VrMEAUBcrpv+EqoluR5@*7 zFX^T6k7}`A!sgX2o3S{x#B=p2f zTWu3z@37+~eNH0ORcN#>O66+Wc{S zLtQt?Z}`JbFT<*i;IK*Ji9>MGX6V-!Y-yH{>Ti=9=welsr>2>O?{BHY;@> zg;xNbiC-*5*1`sER}U?KS>rcW8!Z4|tF>B`i`vBSNqmYv`1b1q*+b86p=n1;8usp% z1`w_hha$h%D;f}MjC$7mhih_|K-u5Jo?}gim5daG>ovCCzU11r3vV?9ZTj1R&&uo{ zB?d#Y6=OE{k?R#lcsCQR3H=>1@RfSts=bwa~evWvqB7lHYCpB_yha zr|fUJbMgO)v;A-J;{W#*?JkSMWePC2lG#mYE8=04*i2HEZh^i*Yq?qZ>Kmc-EBFsH zFS6Cjr}tByN3yfDWRZ)>4BjSUNH^+r7_=M4fELoc)~`u-6=oEQz7`(0`feiK>Dv5* zCT);`c+3+Pd%vG>p_qbX@JbSWfpkMpDDNg%f`+uJ8ooJ@Xf!cp`uIsrVquDNrq5`5 zZqeijRtk+SYN}7dPpD;1xwyR=Bx+VJXE-R)sIhw(1Mnz4c_XbeBbAQ1X zA|4-?3vP_0sC&@*?~%Ji7%K^{dVG;NaSSFcpWM^~I@Ro70`MpCg?(Q=vmfM0$KCEw zBpZn^Clhb9ioS+Z59#gJlEJ z_~4Ntfx5HXftp-9;)V}DvpBmvq$21AKuvoWe2L~u$cQ9BxM1e`fFhePD5e8(C3eQN z7M=ZA;F~TO(F+3g>>qk=AZhn%yk!ZQ8%qjBl$>@DN2>$_@&h~m)ZU3;`^a!V7CuGF z)ofh6cW_VVJjU$SHI?6TJL8@ zG==Tmt@iE%O9ax{5R(%EnYET!&V5JecL=ZYc#)q^0^kk9_-kjiC54Uba;8D@G+*m+ z9Wi2}dY7|7iBjNvxulI~*`~Ty=b*QSMXl>G(MNzx8(uJz3s@fy9siKNnk+k+sQM6WS zSB=!(QbJHlt=dBDofr`^zSrmXzi#}`b?3U{(l*xZt~u;F)`CU9IiJ4Z#g;A`{pubuuan~m_|sh(AssJ=ebM@{Y?~Ib7QVrS{}|*LPTumOM7|Zxo|KSc zN5HP~S3T%TI#(QmM&|67kO*COLYT(Q0^e%8(}~u;6V&Vxf+t zB=i3A@-AS+wt10;h?X2V(g?ZfFB7ltSlcA-kW*kU7#SS#PBlBke4U+ob#!}=a^EfY z(Ib7p{SN!!oB`UxZLb}pkFh}H;=@>a@C4=$JN=UQB5tx1gKxkL#Xy|N9+!G${k|8Q zjo}-tYdo7pNZXxYwfAGzA3uhb*@-XhO=*x~XkXiJk~MUR;qLrVrNl>lj^`WLyl<_f zZ!GEOx419asJF&g9MHDMC-t*MwvYf9-O(scTZN$ zE`*f3LL2@#=dlhaOQ>~%*aMf$$z??LZnJdr_u7{UE1g*Hi}sg~{|=tdS6$e7j9di= zXdel%Np>NbVRAUAz?hdmf^B-Hzsykit$}!#@hnCzd+K0edhxUO4Ve9mb{N_R?iqrM zM6&?ap3P?Myl?Bk*DetgzNTswn7g)pper2sF7LCb6P0#B=V2&^an$yS8l9P)Ftmv5 z0;W4%1U?{2d5FVe(p@!5b!;InaKXLU$+Jv4jq%sk#L6)$n(9Fm#pIqNLa^TF$Xpoi z+w1d^V{+xP&hJw!Z@t;s#W~E>Z+kkQL#@7*c{H#c>b^L1mW=JEGjA;+qJleFY=c=} z$n)d~FFsWpc9*Vt)Szt*o#8D*|24~?a?LN15advQrdZeoJM!zLhZ76whCwPGpG4|a zs~>-g&nd6|7-(4zs{>yRT)Iz$B#4ZbM8BvdOu3F8 zE+0JXiWk+4Xz}u#NeUD^6L*M=q$`juOW+;q-cZH)%gqy1y;4@I$#_q0{blut0cd

eyQFxrZ zQ$GI(Ub?B4F`U-i+?ZlMWa{D~$Bu_TX^<&UX;E$ElzaKy zXIiljS7?i)FtrdE+C6Xvf7}roK++=MFzd2MLPmI<9E#TXpAn?=Kdt2z=Z))riza*Q z_>KEoM(4;4B_5e(hy{btCj%DKMtR-7Z}J+vEek_OKo2Ib;XgQWZ5V?hhLNL^+h@J( zY00gE*z0Jm69_4Kx^T5UrG+T=X+AX7em3Y2{EMLPo)5PSP`*ARJIV;u1gGE#rh$7X zSvqJ-Zf$$2MxjNKw z2lpiP2$Fo{yLqc7!Z$nago(5l_Zu9Z%h!_Z8z503a&80k8Ap3f|Ac3~y-h{m2q+KP zqh8tAh1b#Lv1cf1sRe>0T=U+k`Jn(L3Hkk7ei&eaC$PtR3TDpdcxI!gN}wTL#*izp z@vK+0Ol?Wcf_KGfH_Wt0Di@x66?}f+hIFu3P<<>N?vG7@f#G(0XWsZa|kUMAg{sK*gs^!a%b8;O)A??vtT=j?YwJ%xlQ^gI^6n>Ps?Oc&OesNE5sd5q}J z%;K%%b(og?^e1Osj{@mp4C2|jOL1F|Z3% z$)<7b8&*XCG}!W;cV+%7&3?Bpuw6-+;nS8gzZ{dsNssJtcLgU_VIr$niP;b1P(~h8 z!LmFH!BbDQ(m54!m&EkUu(K1(Hj3-U@Q&xZ(O6NzPhXfw98Cb07qE-EnAK8n@(?9& ziYsOO7{)pH+A_X~Na3^IgXCdyraIF|tB_I(7rssRrn12dl7EPaBXx5LQIKRJ5m&&8m$dyZt!1255U&A6*?xr>GA(Cn#R)c2EX`UW z(oT<_x43B?cR9lKE$RU7OA@f5extRakdJ8J=?q)nE*Jz=EO+oR^^ZNzqzTfhy`c&L z6m{smCh|v5#`&)ozP=^lozGXyoRuALZU%ob_mZJ_eJ0-SSiXW$`vE^SKFN7(k}k=) zHcCbOGUB%(53T{hbyL=XcRC9cIF|>rhTeY+vXTz`itsrTAhi7lu8U?~BcvkD z+au#ZFInwb%OKwA;cda3HUl_MyT>Ten`mx;-F$~L=0x*Y_m5Pd8P*0 z0{Q+nw8+jl!@KzP)U=sc$px1O?lL$=y{JE_1)`#I!jZyZIE6b zLC){Zs3V2yPLy1RO??X=OUs!deSh9=uQrkq9SPfKSonC+~jw zucK+fhsc@eg_3R%e_-??4md+8kM#G%e-0Hf3I!7*8Dn=9sdUa|!D38?c+zp$rFS@R6-6vom z!__ep^=obf?XRiE*4oZL3}2Kq7nWOD{%5&X!7nI`qKQfMWS6Vt#(;@yM(DY`NZwmq&W8 z%&e;Fzr?QIap^pO+zsp}y#+WeAhJY2Vk=WwKMBFLsbsm;TzLDiUbiV+VXeIvFKmDG zCs65lP3BGV#wavSZLVe)GKmcpqxYcM#7B2WJY)>n?!SAOSSr7FxtE>=QQ0@5a{jVG z{lf7N{ED}Pn#+IEdq_`Y+lHl0>4*F^s2Y-w3fP6ESHJO*x1YH-Nxf~xL9SF0!&<2s zuUje6uSLB>PdRyqk$bK}?q+3YyS^=)EGzOenQo!0Zc+b_|?EbY7VI4wA^-XcFqm>o7PAF(tocm=!pLlek5-DYQClY z1@&^`FFe{}(bQ;Dk(AW;c(7pN;h_xaD(wsXI&2Wk0Ci{TV&t~FNrb+eQ$-5q8&&JD zmKA#3c+kJ5;3C^_XW=~x30_FH@9BgHsi!bZyyD$9n$pp9k-qlbVT~1arLG*-{HrUx zAsly9CK?0-$m4R5Rt=7m0*V`zkDQ6*Z)Kr8p$|2vX27pdRW3%jO~~@5@A5wVlEOPT z?!@q9L&WRyLukp{HDDpL1Z;d8m|~ztgc&Tnb|~^2;ixG6dqtkrjNW;ly3RhX#!f@! zCJpnwIv6b#fBT5=c^284mc(bP3fB#2%3LX&<|sUg5sH5v_aKuV@?*~qR$^mUT%1|% zWj}c5t;Y&FNtGyxP1M2L7Hxa-W#L!>W~$Nx9%6^gBW7FD@k8>NhQEXTf3#G~Q1C2s z;B4!$*cQ@vbb?v>vA$ZZu6ILz{d?eyEKN2baR854ax>wHaXwL4``M3pv22>m0d*K6 z@Nn$}WcmR;<}pJ-fBj9L@tq`dk#fi;OK`^DB1GrC6#4uZ>WFRw%T;Z_yE6LHoonvi zVIi$LpC7*CLC7$Pvlp1v@zQMd6_D*`V5iJfL0C+uP4nwb!l{*^<)XX8-T}<=O&UV3 zJMsV&;|e)z5jV}XXoUgC_+5m?mV5DD_$qp!uu>o#=)!v}oK5W~Hgtn(bJ0YmMZGTX zI4eP6Ax@kQce0?MHqZce|9ZdLpX8I_FUH-^v)eLllAf3!H2=+RujH=1zNt2tYIXu1 zMj8O3i;n-#TvkE}M*It{!RlW@qla6RQ(!?t@x8r+URBD($hpp#tX)%C@7>lS!2F&Eh8u!c~?sCUPePike= zdcbVk$!qMQC;jeMzxG4R%eh)uD_f7sf!iHl4(0@QW8Trhq}bQZ{&l3*>we^^BMl=+?asY?jxPHFs?~wOnXHY!96$!}SS& zYE9PPPy1Kv{#@wlTVd11eV$-hEHjF<;z6XE5;V(|T`8QV7!q!rst98B=m64BzP$cDGso>4H=p{8~mb&_`R{|JyY z;8hoP_co|*Y~h$NpU*_2HJ~=*K3ux_e>_&eAMk%8{~u=-K)~__L|Tj>)S@fboT~4% zHnC=uL1!E#7Lv}9G5KGB<)HCB{%L6&gYVs}<@tP0C#Hzk^lyNnD`P#Gj#bZTZE!iM zI7)n^c&8_Y;-C$o5Bb(TR@PG zKTbIRXw6f(b78z#<80^SS!sy;D<%~+eofpGJ4T3W$q2Kfw>a1kApV&L#dR`#Q?8h2 z4!e0sK{At{{KxRin5sIyZEp5A{kI0+jV6JvWNeFKK)}*n`Vo{adLerjXA4HP9)8DX zhQ)25j*f*j2%v?eaKa^A7tmT#TU{SpK3{RjA~knQDPEi1_x zHb8@ANN6D-UqAWM7BxjG>q{BHjQW}x+$!kjmvL@LPgk}~vT1uEL*kt#2Wj8_YRLO&mGYsCL-bSzCR1-m{0DthgpOab8M_6;*7uy{ z#r}$nCUSP%L*)RkCtx;I!=pRkF`1wUC=+3DsVmV}Fj4(?N?OLJ(iP1!Rpg1f2blvt zR}$U#3oDMf+q(0X(F7uBx^kXbqM4TIEfy=lm*`Cf{8X>r&^!(gI?PXTUARcqjCS?E z?9tw>#>Le*_o8F1pN%hy^p83!lrERBMi`grqLiA9Gt?d?(7vEu_RiA>+Aoi{@+<`H zRyvHKGEajlEqLU5IT)s|z5UKm&K?G;kqm<|LGKaKNrzH@<^bb~i(>DWWYLXZYEs@$Dld2}yRrvPy_T-jUp5I_+dZ(n`C5h3Vi8Jhtc>a& znOAdtV;^k3-YTzO{=!w<|95%NzQN7L3}3I4A2U##-vMOYkAFq4^Pg4q?HO$^nZ-5} zI`a%*J4EyVM5}Oo3(Jn(ao2>RZQr?}m5%eNoP&-RueCe)_M499T}p2j$uVb{JOoF8 zsxvx~AB9EGL`jV9*qfrU8&~>S|14)*`Bai1Ix!+$bbpy^QwCQroM=1m}n6lIljI=~s=jCt9&x5v3jY+|$sy zm7=+{1svn7Hy5hrY;m)=z?TYkKC(DLsRMb|&-S4Xp{(z%KTDIGQ>J5v24e11HsqdQ zgUa*2gI2RP+X6q7yd)E6U?aDEZFq+kYYJG)hc`~~F|WdfR2>?7C^)G zvJn#O4)k)RucbXN z#XY z9mhA`zIFdekH1%6KksC{dh)+kJ;1PPfSiIrh`M=rkA96Ui#q0~L++k$?IVSf9zPBJ z70P&3!AKr;XVEz@wSS;adxY#tC|exr07|nl3y`QxL3O!A=6Q!0=c3fS6j$%Bb5&y# zpQs>O7W5iHz8mQ5)eCoNR1DnR+sR0NGWB={iip9gJ5SP8RveTrRTxoba;_No&dlGa zaa*l)e~wh%5n_beS{&#;KHTs^i2ZXOtnzDIC$DCQzq?XLmCYUX5Hb!z573(VUqt6i zUtG~!52|Fr_jJz5;P)b}JNXYIEc!(>V{5N0hL}3viJQFatZ6HY-;M1uiL~-koXU;{ zlsOl8_(g!ed-hK6RDtRS?;T!#)^V{bKwdmE0o>%p|IkomV3of|qTyt-A`*{o)YnlU2# z=R*a9g z%Uu5T%)nXce1VdS;D~$z{G;FG;f^*=Ant?nS0X}DkFGer0=q&(`gvc5I!tIQ2_*Y} z-z2nhe81QJ>2~0af$(ZCJR<+-Hw@{ ze0r3Ko!otwPx0ujC_u z%(P6XkBXteb9DVVM?Po~(|Xcy|;_DuK z5k|?N_?D-~rG%^LV7&Z%GZ3>wo`s&F+}q%`GD_TO=y6udPKZ1I10KUf>1@5@~u9f*TGC?owFW=jMWg5?lUbxQ{ZArt0*p)NNw(S52V*LL^R;t!0ah zW!xRNAyGIcO-6z*rT_zCzok>rbT{4Qq~t5j33f#E?vkHj$LoE7x_%GT(8#e)1}+|V#t%NN*2!-dO_V<4@E4rhf8p}52HVG(qTs1?^QeUZm;g^Y z-qcb8C;$~!|6E|j{gi-agLf#>8Qs)d`Tvm0er!p-ekfis+dB+xYk#=`_#a9(()ooV z)Fo0qgwk^IgM1!d+Ib0ja+0LBlwf}4ok@90La=P5AMjwYaF#Rd`}rS(+J&r(cU8y( z_5nZ-YK@lfVjpBDVy)2iWa96`B6tamedCk(>Ja8mG>sUq1HTWt3E1}`L&sF^fEOcq za{iEb7xZ1h#DgyY-RpTzwRUa@gxtuTH#80MlW4k~ z<*6U>iQ8GjqTM=kt<}=ALXvuwNw2=OEmqEvD4c0#@cu+J(J5hvX`OxTewbCwDKD)Q zsv#M7q@~_1N3C%?r^f(N9tmAwgn7a{o@xti&4Xy4wS_l@MVjC{fkz2OUOT@FKlMin zx4cyg^@v45H=}>O1rZE{;2ozZK!u9MUCM7W0P}9{tab6mtfUO*alkg{$G=ZzndW+d z-vu)1LDC_vb;!r$iV>q@yu4-e8|AsjzkHEDCw%$Ck#vv=gt5yab~IrjquX)fSI1q6 zQxGp~Dp!+W*F^CpJE=x^$ttTpR^fGhDmyek?}Phb7*Y}slY(JZv0Db@G+%a-e>1bl zh<%Nc(E)-07QYC5zV{y$4n5+DC|A1Z*rG_Z_#lSZk!LYW#^l8)2 zBP$a=(?xSh7lJ7+XbAlZfSd%oA;NK2YUN|>xQH%cb~lCOJu4#yBMkZUMVu`NTSKcd z8)k89IThQmSFnHZnvyQm6b9c|P0qc=X>_GEGqE<)k?Wk!>Oqx-lx<0Z`EK-f8pSct zx)WKW7cB=h4e}0k&DST%^jLprQ2pe(?0b%N4f~Am#3es;$fDxn;JMJH3Hmu zapCZsP?>iAIxK`fWOl0d5iqY^JcRIX#Nu^FRop#~?*(AJZhR^EqGcQdE`t4`57T9c zDgz|2%U{n|ZNo%^&*IhtU0Ops6V#3v@Imv;B0PG!o1V8g^DWb* zC`jy`;rTa3`k!`PWDsqcgX;MeF0j|+gO1FM?!D=W?s?u}n;G1udL1schgzF(NMnWd zQO(Fq6i4Vqf^Y^=V{sy3nf%eY!2KU#Q<%4@{t}5;Zf|E`Zt_*LekCIc`+l_na%PBx z;G=y3jO#Piw&{3H%ahk0p^{M2Jh`uqA%$^ z@i#D{1~-!%42c@Oq|*Uo-iF>Bhg|LCULGOdFe&a>w9C+>9x07h(9XX}7b6I*)FT$_ zko{L)t0~PCQHMVmr6*%I-#fh{1L&9tcW@0F>j6e^gU`O`p@4cg?cyJwAHC?vxo?{8 z_2mt;(EpEV*czJt7fCRJPa_v5B1OsJOW*T|*FJpK^OcS4w^J#5`nG61&D#DA>#tXw zGJTcWEcD@dR$FlAH0Nt0SJdha#3o1XX3}_?aIQBz!*3IBUbK&b@9wDfo;Sr4vzCFi48&%T8S|}>Ij-4I) zN|?W`-CCec-ptKvb$QWr@iTQ0KHanRyn!uxPj3h1O8j4eT-9nFC|)H|od4qXUOR@j ztJ-3wx6)3{tK>uA|A=3j;DxVf&UOI+4x53`vF=d=I+{{9>})@_8P^+q`MRX5#g{4w z=hiCKE45{BK)*o)NBn9;58`73m|a`o`uNcwdFKHo%gOdFeMNnN@nALG9Z0nHSppA& z8v1>n?D{M78mT3?Dkyb&TC_zP`^(D@vYVO|YG}1>a+7?#xR%(?Lr#HTgx(+a@)L5I zGG4B0F-$rC$xHY6vPRr#I7wlcs)o1K>zThcmLoEL)ONwzP}`hRx(dR(@aVCVdD_ArHQ|T6_(_46s97iEbdqM!{IfOV4dNj3p1O%&$X$DM zVmJ!y(aQPmqwIyJEJFM78dAMbaRk-}t`uu4Sd?}NT1aMLfnMRX)i%K?^ z@BCdjN9%TB0WK>%THyb9&^{}dfF5o&%Y51RzcSDN|0l3Ee4+G$J%ye6aG#CYQ!)S; z+uUbd&`3}em>Ce*W{_vsVG86XqVJ0;bW;?hVg1xA*KSuJ(t+bj_2VK1L^dI`6s71K z;uaFUGgU&?(5GdfT{J-FHUq5cW8T#DROJ#M`2yF)8G&KlGcSA~7En0Zml%&nP`Qj2 z^rGo38v)Hnt*XJH*fRH$ReiggI~JF*t-bM5;u+ajv}7)&TW6Y#^TB_bV^Gr?9mpEj z9z!mCRN8kpIzt=bUnvdgSSs4B8~_{;zC8PT|E77OkoJEJbBw=4SO36#fCHU|!(TbD zCn&NM|0s5ck-8oB<_+b=^i$7Zpy4O?3W^d~?l8LQ;i#KgH)KI;(UhX-c!2AT;#I6| z!M5lWS*tsK0`YDo{z$YaFzC#cOJ^C1&4fhfQ1AP& zX?rU_C`G#D$nn7nkBgX?RqUqyqc-J9}#(L`jdOf5MH#-fxfZkbP% zPq7LwlBK?pt5Y|=!*=6Rp1AviTvBUX%zQhG3 zo@rsQiomDIJ=_1izyL?D0C>^I25JjnNU#uw`*_|r75Y)D8WcX1?2aj@zcG6GMTfS< z(4R=j+}9*C&VaGgJvuXxciBXq*Jj(S7nUA=anO;`E*UqhqS6${zCBac$mP?*J~CHd zIi;bxct}H#lZm69>EN?a-=)wOyA!>mer3lj#jmg6_)>p6Kji8%t?oiBo;UN%>~Mpz zfI9(n^?1X!Gb;_4+t|Bj{@ggaK5TR=74Akms!kcdmd14lv4(*Qdyr5h9l{5lIPBd-dGT0)ebpO$XI)Fi?)^YT=?UDPq7j&ZhwOwC zB`~CO#A&KJK|75#4He^k*wVy3sL?m_!oD`_Y`dGe?o3#zz~1E23e!P2shuz%y8ucG zfV02ZLCGJ%nG03bu?634`g~OzzDp_UzYn0Ui?jVGYovaADd__!5=(V!+lzVB3llFu zQ%c?1%oBA&m&JnTunC-4?Cv9B8{}*EtjN&T&t{}+r-_u?(92|IJaVdk5r!(G%Kzox zUBWa&%f0=w^h=U6FCGsJ5^K~l;X$brZ%clrmxRGPp3yHsMF_{+aJ&&0IiQ1IF5~-p zMzG_Ik!uOYQ_R6*GViVMRoydby`n0_w4I?2TXWJwqITqh(Ud?}uu%-Wia*dltL@6% zGqa4Z$7&UdKKOhtQ&dXPOE*?AW~d-(ib~RAJV$(fYQe z{1HB{!UH+g0=czhYnPqhfv7CtZuqV+N^@w5XIe`Ys$> z$U)+XfU&?k9tx1SM{7N~o)0?^oVX#=_0xh?k29AnZ(&cKH>7_LXxQUc^_+RkH@80# z=MJuO-Ql9VgAJpZmD33CV@qwws;h=iMh*I{XKY%1q8l^uK~@hghzLALILmeh^}Joc6*wf?^9BNj!r~FrlsNm*5XLKA=}EjEqSxyg+}>(!3F6S=)l{X!aZN956A&aMv=k_ zW3A_iOa`gC6Nk|pv(vwgXXB3@phWR?Fl zb6H~c3n^@d7?*X;_XxYT2(-O`XDb|oMeOzIb^}m5!-%e+^gW{cx(S%Ib~~4ne_dk6yB5S zeQl^CIryE|gTLfG{Id+7!oWT2s-|HiW5F<>7O&Xlc;q85}e4h zGgCzGh5?bINKfF4F51842lRrCg7@a zjyouzX{Amzh+v*If|Vsq;qKXSuSth_g9_Y!x6_TRb*24Pw4e5!z*LerP;onS#SJM~ zNmU>+b*q0)#hPPoTM1d|%L!%vebl>6 z_6vBb2>axdG~R@lXCU`?s@p|YkPCF1M}dxA57L~X`;wHKF}{Xb^mag_DxfWmcM$_&N@Oq`%Q91@k=+W;)?sA4dS)J~LL4k2O!V;UA(Z{1tams~e9q45ipLh3 zYCO!_RP@-y#X%a7U7$GO%i~l=-v#s~H-NknzLV%!{AE`x3zaQ)a0hyD>~?O=DDGcy zVq!yB#a^Y=q8MT4^WW0D`%7O}-sZO^cy;tVJCa#EcN$0wTk@kNQ!hSyw%jTTK01;O zF{^UDJ;B&1C6(ZU?w?m_IPH$}KKV+iJV*PD%m>S$7k&iP|8agsDE**RBV`i~h#T4QJ7Xcfx6N$n<4!k2bIt3=^8yAtB@cX&^HD z3k(|S&$QUk>u6`qm-IG!Z+`oh|3Om^UzaJqlK!JW?q@$sC~p|J0-8vS?@&i{4Mo~X zk%Nk#rXLI6s8ubyh4fbwngXZ6bL>PN%^+9~tcpLM4*eo6OT1*~UHh|RNbG(X9doQ6 zy&YLXJxgS3x;ig5T*s350K0N#|5ZqoIDVtC;4FMWw~nesVeJ8~;wg|V4OyX*WznjK zw{AqqtB9F%)L=xKb%8t2_`%ZdF{z3j|DcAAkeNNrm6SWvdv?}9KG~!L zR~;QSLvpGD(AKwR^(ysVIR$!qzN8#QlPjx;tcUh}+^z{HHfdXXgO=+z>ryG2v=hBno$FP(LZGR?G+K*frq zkiY^Y@~F+)WE@Wfcm1(-b{;Qb`#baG_j_Kft`8=|q( zvJ2#NG@-X?`PxD~s4ZkIQ&%K0L0CV~^K&g$US7QLKM&Dct+=|-3*C~_e`$kv(MqH$dr@#qJ)wRul`)8oDptGT&JTo1KtZ6_{ z^;{R>>~pyInPZMF$=aJmlM9!_#%n01upWN39eKy1Ei0EYP*kgJ0kr;jhM7|*<3e+(LV);0$~N#G0PQaI{R>Jehnk@TCKS~5)r;c-|E z_g2Z`pByDQDjj~1H2uUET5F(y0pB>v$OOrgY+X#f0H2!v$D}QgJBCs2qSGxWch$rI zXmubveemqWtWR|87bYW?=sx#%x=JP?UI@u^Y2&G%%Lb3lz~E65KMmyRNR;qI*Xs@|X8p^)=Q$szz(bC(mK%bHs7ig{>b{fR1b~lFKNXi#} zp0^WlW|E0oSBD}oR24$@LpM&MU6w}di`b6FE6s;*d(%W@tWo!-Zu{Y(>1MphBS{4vjsdp#J{YJmtzY%9$eBC?c zzVzcu1;Lm0Ey1r4(+2owc_kb0T63(?j?pEn#uNkVyQ^Qbyb1a0dYmBAl(lyetPV4O zeTC0XUpGnup%N@rIM?7=vqt=C`?@jq*)>@{FGM?3hj4CDG6u$o+Fow9uOZ~LvIv!$ zG`qRJc-+K@UMb$UMG&1%C)SFP+u{^!GUr{WBmuLe{2s>dB5_S|_TEc1%B92_#4i8I zE-w+xu<@@XXM|McyK25ZRROImw@PE)Z?Rqu^`OYmd#!l3H=B{MN1m^Zu90yz4;q@o zR~(X5HR7-!Uv3wWQiDXhA)#m6l41`PCpN@FEh*a2N27i+-kh_VDJRQ8L!d8v{Jn_t z{rkI`sEW`FI(RQjYgOz^>TNcMWZ3tDcPEzYZV+`YAE*~; zD&Ms~UjQ-$p4l6U*@8bO^-EhCN)HQS?Cz9&X6-(M0_W-|8rCENPM+HMAIB8roBfwm4jbev2S%x zG+jXb0Ah=ooLqeU#KcN@xV!1}!Ni2QZ2KEQ;oE_zA)}di(qkfWM-u2OgWV;_mAId$ zvo_5Hc)Z`ub#6`7lS&c!KIK1^psJKxH~wM3RM5IY3otuemE04i5Rpq0o#-jF-e?_A zkJnr`zz;(y)YrLv3;CMxqp0@=(^Iy(gJIwult=IW^qr;h^*+*cWEC(_w}0;-tjY*6 z#T3`V+@@ZJ&7LwX810AxxPV*&E=ImxxNfXD6!3FS9sk7XENc{Xxt_n=!1k3|wqO7p zbOLtN2qCuPyKu+71mq-4cznf$KG4?KRJ-q(TJu>SpO%{6R|Ns>_#anij_t>dziq7Z z+jiE_Li|KK;->f~NVepl3U{l@=5{fnYwYgGo@smR;~3r!4h(>k&*@BmH%P5fIMI7@ zS~)-4RTQK`{93QzsE|^@SfDQDR&H&23v;f>FH=)W#IA5wraLUO3FR6k)wr}Ul|3XE zxs-0cukXZkrp-gIe@Qk{^dGu<{Wn1mV`%k;JVP3#Wl`-ZPk^(>G(7Ccz)bGorj z(bl^oG2?vY-`UDDJ#~JdI;L$*5Je|Y3B%3r9VbDUh}RU7wsAi#yb*RnIonQ%wD7uq z?Ru0M$k=8Sb0Fo>R9)r@5?%4+B5~6SG+l}E7-3mj5&aer6hd9J)$?~`Y)UJ1NyJnJ z=pwpoRpJB{yDxrkc5l+Cx3??NOiN3V8Ei5vOSLV*WbD_n>guI^ z5sN+!+&C;J24i;Be@-hUP2BJeW%+&afJ-xOsJU*O4FOe_wD1@8l%9UPb}6-*LjZaF zjMbafeR8?9aH!Y&61+nN>|w-2{sE7-<0Cf|S_jUr5A67DDDVDJI5{@FrTD6W5`B&2 z-GTf7s)bW;pgA-ZC`QnGb;Or+xhih%M6cX;(-KqXn&vJ)3GjlXdVAF^59hs*E!$Xs zKVHTxGh?y{1nu=x(LNc+r@w*r*)89|vHa{k<}x9gqhOXbY8K5qg#j(F9L>a?1U<5yr+6>Z9ojF@!q6^8@$i}+V6np!7=i~+Ue7Wea~zZX_s>@& zAH&wil6L9B!i8b0S40jA^~M0Aei=00AQPKG)yyENR~_7FB^r`*FDSHn6wN8j7KVq{ zxNp!lYk=v7QJMD1U)IQAxHi<}WnIt-iE zVv7daFw+WY#d*W6j)a!(vPF1|_JvHHpRG8NM;j8%iSzQgN}p64P3GRdoCphK0xsf` z_Ulkf!vA`1)bNZMaeipV#~Iw*+%=j*%2l7%OWs@&b8j;))U1i@z_)F4dq-gwLO&M- zbt@xFds>Ia7M*s)QXbzP>>7P~$F>pGliH>y+N_@Lc`*sExODwCzTKRBaO>fcAn9#o z57MaN{hOn$IC?I@=jJMFdr!BIL%ZFObn;hS?9q>QZ=o8Y*L|1;F%dHG}~PS-6K=H>a)Yr1fOyIx6xE$bCD2 zFy%U1lt0ZgVKGSq%$c!ACvxu5n9|WM?4}u&-GMAgx#=;_PfpU7r@kki1xV9xS^rg) z>EAMb(#mW*XRZNW$z)`31wZRw0$f`azDqn^h$tM#E$>(LNDR*<71dOI6T?<7`zR0zNuoT|*3fk?&JoRL(^?fb6bI zN&dFXv>2dt=D^3sqCA!3mY!niu42x|2Bddx zM9{7EHf=-l4#eCIUBmwIIxV-n{mj;&|3%pm{oEaM507Ktawm>wBKT1;wt!n*sBkAcL20dUI+Yfqe;RWiJ(ly=k)zy%J zM#c>N94Wc^x5(WffQ(dj2USCMz=VENBI6JS!n=`PZ$KbI zHJI46oezKfkr+NOpL=MsvU|^R651v`UXz@$6;~>IaWjOeW6A}P6bcsiqn8!t%0gAy z38+;iQsxIM*k3f4tZ{=#Ai`vAf+q2V?!UzN#w90X6E@SC(k^rgQ0*3#%~yNY^Zs9| zohy~&m~M0dL}A#3P@bU6E;0PyJokU2|6j)>+`E@`Xxp1;&qP=s0n;eS0;exR&KoUp z$G!SL1U$cXj*&|LAVkdd9ZVeLsYjNgY)GyZZN3ac1Fg$|EGcT=~sCjS!PHvXY=d+n#0gw`-?A@YYX$ zORiS;+ah1aUX&g=h8s4lRZ^baJ*77cThcz z7T2r*S!gbHG6-W{XEgzSQlp!n@_!oyb6EGp-cA3G4N|FhZZV4dB$kl!`y3*8yA~W? z9}r^S+-g+atC#up6(;dF0b`_HB!h{-3`BI2XN`<;OgC@Pxn#%XfZk3zM*>O3TVOy1I5`deI&zilyluRx2% zH0Ix*_MHLA$vY)RH@_#g7nxRi=^b<4y4dqh^Ql&5rM{=9bd*zM;WM=>EbQ3&q7P*k z4n;TjAMylC&Aj`e#f<;LDcjOM$`+E+SzO6hr}OHx=vhpZ#+xd5-AvlyWofntmmHw2tnt2=9Nn(+yK4?50Hz(}Gi0x>GWYX-?ZxlH$|1dGEZp{>mXZ@i- z9yQU8@JYFUq%v8>Hl3aOTMSM}nEHL`w?V?P(+DcMB7YF`Atc!NDE&9-CY&nTr@pPP z3i7dKL+0^{+GZI@npHlTjF(Y*?HAYF9)6~YKRkK$V{HPd++T~T~W zToq?wHa|A`X5EVpxw=QzacqRt6c+g=jrT*YtXxQxdQqFIkz?{SYIo{}&%iwfk8EL~ zX!nk_f9PzbA5u#K+MOU~n2<2fen)c?8UXsUfeHl%XIE?a9dZLb)82|Z}bVTo%rt9?6GB+`(a(PwzRqH zTgIH5Uhw$jgDy|^fCv)@E8={doR#Is3eH57{u}b6OR8l2`8itxm;d`oZ`R;H|rd zg^ey@X}b_omWMq+nC&%vLY+UdgsRlR%*>9iO_^UW5_fBR66Khu7-%-f(rT=G83|tj zsZIPVM@84J*SGrIdLhYYdbZhpnPY0`VM^ej>$i@)0)?sHNV~CuPGTcieQl(K!j@xK zjGkr_HHrks+Q9t&5n9gB>t0I{mc^N6G6Y9x7mcE_BpI#Of%#*HcY4Lp#~^y+fz8hL zn;Mpg;IqqV=Ps1btiP|nSF7-&>h7%{XH+T$ZoRZFWAga=5_{L}>9i&f14zarDM3B% z72(iW0{e+!O)U9<-@p2cd1jif{blQ-hgJrcBT^}}{rrI??=IDY8 zH^TeIME2gpT(itcjnUWh(RP~G^FLgoG67RRE>Wz5Q1=Di^#@{n30Pa+;?-$E9*6yX z0p`_aFerRTtob$KF(HD*P^|tMY6wb8eP$g9kqe%{L4aeZ<4|Jr@eUKf8I9a>4{|5< zdR6S%Hyc+iy?VH`Cmdd675@KF_MTBqeP8@0ij5{+IuU6~ucEZ52nZ+QKHM9P2X03V0i$JpOJ)E4o_h&zkKlfx> z)D$To{SiI`jiL+8=`qVqUJ;wr6Pi4H8_kf=_x&5ttkAu0~K85zR`NZfHWJ9)B z`;{}9|5w*&5lA-Z7rbh=9~{0~E61yhnZl*qYIf<#bp2UaZCV-<^oCs>1a=2(mIeJf zgeZUts<>-u+HLJ=D_xtW^kJDT)$RD<^UlY^hfx)d zKFns&d0hdA9}nVHeymk&M3S>rx!|2zK+huybMvdb70Z&9m8mJBp`~lf%f8>3$I7R$ zB0Hg4d6Q6{OEXpjXWnGEDfOMVO;s;g}_eg~IO*1PmE=Wb)7^QVL=eHu{VX+@#x zWq7A_fcge~i17)mMZe~ktMX$9?qs$P$8C!m0$iV9Q^kyv_!2*(O_#|0Y9r+uGhi90 z2RH*FNEP~C#cO5Ru%j0>ZJ%{o9D0&_`glC@6==%~gmcKOr9E zhU*YvS4DAKQLe80&xm!TOtIF7w%7$pI;V@xnIzXU{YAAxv+|v%RZVkq-GTeY2b$5X zdO16sM_=k_D!3PRqptpD(85KFcWcI-#A&&B*aS8GQN350c7x-{Kc&TEydnyA(fUU`R)9KkH`pPrnI&N`v1+fBH_vUf}iStc1GYshqLuGg8azX6#W% z)G}CoW?%mN?_P-#exoW~FuPNqNuIEMJuk>CXy8Kvl;|<}vnljd)8~5@*1|&%^%63s zikuY@&?IGbELRT_$bLK0si7r8qi*FD?B=iQ_5FT7w?tp)>V#A4&%zkfhndZGioM zrKdmNg6<$I)bTbKd_^wN%+}&TRxTU^fh<(4TgDL-Om)k`LE;uk37n z^~#K92G=P6~nqt@M?zS8P2<$CAI|5^-xW*GZk;86nDmvljYa!NQo2*1%fuzD zM;%P?qPR*t0H>j&#KK?Vvsg*fJ)CK`Ll+L-%Q?&3E@$r{k*D zTn8rQftGen{_ET)v3^reE|SLgg1B~qcxGAy*AGCwvp_Y|Pw@0FgXJMc86qBeXEqHet)UNm~TBa8ueW^%N{j zX0Xu8Cz@cq2gJFAD&A6YGjQ4%TyR!lt4B+Lc03wr;j}ru+#^pNI{GDgv{M@<^qH}E z&<&m8ejxO=%HURmcdphqH7d;xMPL2P^&cYa-ogXJy$g_AH3LlFottwH zHsp!F$&*s^cq>4um9Cyt4_)pTX?TBda|6-WdUS1-cz5crRoZ>D+Zh;n3^wyRu;kb; zy|tyx))4dUBAGRZXEc|M#*-;JHi?`tj2AvW5cUg0gAZz4^eor1lx1CnkaS|Bn-MEDJA^ z`%9g`0{bNxmvd6?ReRMxtKn$}$W`>5=QV3&$u$a$rXK~#l$1-PLxXvM8RhCT;%zgp zg`EknG7Y7~y68bMeG4tF1CiE)At_XyI;H`a4{WlL0e3O3!5Al?hZ*8Z?q0`Rh%*ML z&U&IjjRP!Dq2bFY~>EnJik+O@Ag?~1(0nALSat-C@#U^23VD& zP#13+x_bi2ZdF#Da_vuF*F38_G`dZpt9n*vSjz``3oBUTUb#dHwt`NS$Gc7W=Msy7aHoYV?A}_v9d_ z=av&=N}oKNZJwUD{_W>jhcp$~h<{K<;RHzus;V#uVE?GYAb~UrYaad$8bP@@-|rz- z7Ecy85*8(9(J zhXFP%2VtRJi?ZBb7GvVV`$enW!|Z(KQWqDmpH!^Di7X(EUvPT>Fd6U+|7opESPiok z;ue?-{YUWz>dQ1g=Sa)WaSeLF`*=IMo&$IM{-t;+Dj&R70vc;c zAkjUb`F3id_Od$lUF@>>bo||RNRn-0i|oz9lIVbGHS&!rtWpP=XG&Ed06cq2Q;kJ-djh&zN%I@-=F??}`p92cwf4uiMyluDD9!#JQfMbvP+u&=N3G1QbbtN~1rdC98CO<=a zzn#->No?MEV#wy|i#mhy*5ndxNu}_$)aLdwjE3C!dh<+3dyS$NJCb53Q=d`5_1go) zmO*Cf(MXIe0PI5EYIVT&qpuZVWzno7#%3$!19q@C&-i;B87ZFfus-5JwRxGb9o)m7 zb*o+lM7WC87PHC zN!5tD(C^KM1NOa`JR8r+7rCfdu-(z6UaZ1~<`?DbD%i=NGm;yT(2xf3;d0IRosh#f+ z;5clEl|Q-(Gcb?pY1T;f6>lrgqfU%GygT6K-jZ}yMnyGu*FkmR`}<6 zznWsa-cc@% zRr6c{l2r;xjlryBp`eWvr!V=fap#P{`h+&rHzGRy(iRTVs9eQ~*k5sps;eVLZ2Kwq*LJOhyDq?^S)uM_;GiHQ)%vd*R{pfa z#?b%-!DX@azb~>9eB$|izX7H|o5)9^7Z5;O@xgA>ROs6me_iX~mzd5GPj21yTIqLJ21DNH}#}X;im%yk|C|yy)^}2FLfyO%MVN3>L0BCVJ9|A zoz*9E(%GCeC2L|~Djn&4m+3cytrqL>P2Ic&`kwDtJdk~jn_51m!ILoI)W%By_TKaZ5v-L@q_nWml0iU zGQ(Y#lCh>ii}vL_)ynxGg1i;ursjb9REKQ3a1tkW}UueMb8yQTKa zgNS^VckV*wbu}?ZtXP?~fIhvTZG-Vx&k*e~>+8Wpjbirs`alIrUEu%KpeH0q=MF^I zgw{wN29k1J3XLDd#8`cI#H;oGdT3W2`}j}wCA}Bx6^vSv@iUCMHgD#$9`bgx&hj$$ zttb7CwM|?9O`6ZN^(9CXZzGeP%5>Ie!hC#g^W~aSN>aW4$E>ZqtX!tUSeagVkp;caZX)Xi}G&PtHib(_@}+?F0-yDe3Se95!UOk zqzv``Toa*O1Ax&3;6T@6Poe}}kh*b5)%5o?GufGfwDq@bJCW@SSXx@2MOU84O1Zxn zWcZ}Tj;MS+XbdI{@-L5cf_a$znR6H0TJn48e-r_;uFRi3 z73*HvL0-+|vz~kx%|EyC7h4b{rdj05$V6m6R}j83E0W1E^ZUcQ5a~?SpgNMFSOKF} zUxEeO?;uUZNPU~p^)j9B9ZjbxO5TxM`?d8Y;G5jJ+&;&QMac^jO?!O5FRMlZrMyUt-`q0klhs_7ZzI~m>eK=5h_-`#l}=t z?R;X}r@(v`J1*6pv{;@}rct)_q%^ErK^~2^R(|1Nn4&*L6&mHw>^t@|hd;?OyEKE> zdc^6|(M%(`XvnqnlU#boLA@Yvn73(|=4|j2r@ha7hM)_O+(As72+N(JtxG4PcvKfPaaV5}u zX?HpglNm1VXB7JN7gNLUMsKCwR_4NfNM=%haWf(y4E$C)+H>IHo~7J-*R!g;Y!jEO zzlGGJe;(55wf=I|uGR?7+Gj z-o6dUz3~*L4&Gqah4Nt3iIed-i=0w3-5UW9G)tTGZZ$u{iH|({jr|!b< zZKG+)-e#cBR_tHag)zs8{72$FfsUKKsc-*Lq=Y(!N>9vwod5%AmMocD<6miQ6vqmL z@)2vsJ#qBI1-a0hTSo557e-D|9>W2T8m&1q_L%~B@W~}KYT2p!y6oqLoZ!MEEpR6& z!f33;t2S|P-WF88Ti5&W?c_obCD475PM@0qQz`p$#{y-Qo13%jHyf`N^|Wsc;_Q3K1}R$bxD2(m~ncrYMQf|sFOhC!XxDP*t8Gl_^`rM0 z@_PH7evYOn&4-ZlcY@E;to9^~iw)tFkW)AhF;@Y8qg_~g7uQS`xUoeqBe75hSh}6i zC7^SPeD{A8V46s$h~t40f2)qLZW!+Hhw9>5MX#N$>E8zlw||rJZd?cWte78UadUw< z3x{!yoI{uIOmJQp0XM2S%xda0%i(h>1~<)N2~?0Q3&B-f6r*m&KtmeB;ygE3c@N+sgJ(8v1# z4fVuoX!gJ&-^wAYHl>$Kskgfm%|*iRB&UXhEB34q0M{#7mSJ1X1#IxQH2A6kjb?H= z@PyMpR%_e?vj1PZKd1=a$;%%LSs-|xBDyc4BngW@K?7;z;z9to^ncIcQU06yKQaVK zU{^k8xD6!g^PhF_I!}8)fowVt#JJEO!I8UnDe@@gDDs|h71dsv!{6N4Zx@-&JBg`c z){J=EH|96{7kK5B?%4rSrgD%tZX1GCC*(+KFsWU-{QIFeT? zu78j^77s);E2R_%;%`IPts_5!S&4>?X(o`lr)o*BwdDJiD=1$O z1~XWy8Y8m%i9+o{>L!x;bxLCD<6_G`6_zxdAIeja&@OARM*XkzU z8?sVhSC|v{*?@LE_I@+2coNp%%NbBPM6KK4(CFg&xh|GEtXt4E_@WnTAxlYSw$PqC zNH;eT_W4Kg>KQvOuMs=ewsq|!vGULE3;)F9W|`@}{%C2nyW2XOXT-sWZnB0N|JzTKwRpuS4GtIu$+SnGf4nT(JHRg29#q>Lmt232= z5`EQHTI&~~_?UO2p1ClT-sIC@vE-A1A7qXSw3tD9&y-UWxewD%{YLb6qr+@|20C*^ z-QG`PkAeeTO6{MtI$0+}b!%OEE z8irQSy{cADVB|2!xiO@*=ftI;Du%Tn0y#Qn(UxE#1#mjwyR-8bLPb6sbgF`FhEo%C zKL%x}>Jdd{Dqr$wavYmf4WEca|73+f!C)mLZjnsCbFjpNb|9AH~&JUaC7;y?z-TUjur}1yJNLBd-`y zv|Ge)s5sM+!IaC!nuv0>^=zA$Kb6*kVvRlKQ0w!L-I*`etkd(%u$nFqE0MzG6vD8u zTfboam32OsIuE&KZgllz*GH;&*Dtg3O@}=cm3VdekEdxftAkcwc4g(fhUPat99~yT zIPdQ=rgV;VKbaErZF{D@vwsFmdy=-y#<15BM3prcAr*su)jN}apGgQXYRdn`F7{0* zU@mX^78d?wdBtVJ3F!gTL z2mi6V|BInz`lg{oBw@xmtswH}Yh3fEn_>K-aq523Uh^58@!Kj^`crj$`B3u#g5}ez zxL8^9SzOZjYyHhor*r=Bs+$kyO|v{9Kkw{vc5R0AX%e0k1GG5r^+W!w9wTX;7VCSB z(X4Pa)U|eND$6pn82+DsEYhJm>;mmA(=HPeax%&zdsX~a-rvtM$C`}@tR!- zZp*tfWnKss9A8Vu8(MO(dzl5ak5dDYpWonH1o+Z#FG;8c-&FCb7>+#rQvBea*B#gX z#2u?T_&&CHcV~T3GQy9pukdIy%DX+vH-NO#=CmN;cBrqm*+i}JnESJellcpgzf8EI z9C_Ce!ItK)853~_#$tzd#&;)}=wKxbQyF8C?$3{rOpeV-`N|YNi41t#H&V0tadKCnFQmOaek*!M=W0hkDU*7@Gf+-G)5TB8-f%| z8mbq+Kl?gTEkmYus%Bq;i*3J4^!xiTNrb6JN5eVBN^d)G@gAlWl7X=rt zm%Y%P{*s&dRn*+6!Kf;*c-s*A;8LfLE2?9ayZ%E*`VM3xz^n&&n} zii0g2r7CyFmO|_5+dTQ@sNl^{2}3dQs@XYhSizYrruHgWJx0md_-n}awRiuO;vDWVr!4roB<&I0oT_=9C)jevL3+ll<0%QuZz^NZZKMTR6BreYeiv z(H>I1`$zLaM+n{m)Ro*E_kElEwgNPxzI^ApA4*B@bWH8tX7OzC!^Y0b47XP|xejQ5 zpUDA`RxESc*|3Qi_?SU5Lf9!){GcxIjFEPbx>8Uz=ZM-3cUVvLuI(%Hk;Po}5v#W4 z;9v^vRVs0Zcsgs7_db>iQ?HN<7foD26FvTECzk#egw}nyL3c%^ANZrBBve0YEF)am z<-qFk%_MRtOf#a$O0Z4SUlu#YS8xMO>K!)|y`VT}_%BLx38+D@2-Z||b6jU*!Ra9j?=%0eSlMoJ?V;a zy&Y$1XZp6OGty-KhV<7Zo+aZY6@)m*91viABHxGASYnNP!9edjus!Wv{FV-DW9;R~ z9DyD#02le)#=D{tD7?ZK(A&>2;NXqPQ~ck2Olao9hnk;`$1I_L`e11*x~TqPpu|$A zsgk{KCwRm^iF8FSF0Sw3uY0a%Q98~pxW(4xxZ)~1zbz~q9v>^094GcKpFXJA{zuUV z=W3TCYNYEn0jxukL66$=IGZ}Q2L0z%ikZ~c9$a6^Pj|6M8(RcrukZl3w=uwSyqy`` zJ?KT_-)1o61gkSp(iG5>;^$+1=)Px}N)RG4k-`Hk)*M>l=p&Amh93Dy3tg>4iL`N3 z?T&^^ummUO#(GcVcMy35>L`RWxdPLIOZWv;R%;+u5n1zoi4{)Nivw?3*7X~_T-MIleQ>#$+h~XdAA=MSvNO&;CTq9!4E&f zZkESwplBQu`$AmokND#0Rdn-cQStle_C4tGZqfiMs(;r!o+E28e=FgDt zd5{vlyUR|WFq%Xbe^Yz|7Sf$&+yfwl=o5Urk_WvV7-M1l-`0*78@x|h3@o%W`?G*f z#TV6w#K+jINL3L$rFQH_x5C2rVf*6ku^X+lLW*{)Z7@g-_>I-V_4Up2RDbk~yK0_A z?R=knWK;GPt%aIdXjSr4RFMAzrP~tq@#}?q3vSVF0RQY-!+4M2%GPvV>hEv&JE{(K zrKqf1CR!(PIixS`{6WK+QsZ8FMHP|zr**4W50YxDe1%8mBNC6O_A&sx*tZQ;`=yHo zNj(2qPnpxY9=0Nc=V0VpXA={%fBik0)%(SfkpL*z5+x|J3e1`3!pd~Urtk+2>l-%&DdA&&t? zA#j)+3h)xuo<*mtVatEI^94T4V>GEa#FR&^daI9$7aec!YY}b{FX0z+0<`dD*!bNI zQ*!4_g-dT;+u-M4w_~1XemFf}suXq`q3EaxRu%+YsGexaaQO_YXHx>dT6yS*UmtsE zE?jMPBh7t1RkltrGp;d5E-{Skv9WOOYvtts*2O^m)aY27rQVHwzX>J=(r;HE1oY`Ii)gE<&<_(dy@E95lveS$=qX?!5 z%mDbSsNS{xy!qb1IkKh24^RJCXC-ruaI~5`ku`7-a>q=xpwN2mS{yrj74A z?)Go`b>FLZm`yag)Yc|a_PFS_9ra5lmbJJ{I?YE{{VO_E96?l$KD;8W^=#67Iwnb| z!;u>Ilbd)Js{KGKf?B|XaWZefBfMdW>3pYC;jT};f$r@-0U9wo0r3C_?DA&HhGy)$ z^w0#;c6ew0TV%e7>bQ8UaF>Y{t9@?$xTFjD&Ei?fDBL`)TD&bUvTvkgv1k7DTpcco zAI_CR;?DjA_TM}L$MyegY;2a8U?`bD(!uR%9cD=iF@*r?$mZ|@Vv>1IAW8gS;2wGe{l)rKAgiwTX6&MANJaAo~%Dr~<@wrT_1s z!~geBL|}a9bGhp3TuPrBBJJoI;5?Zns)(M0e$cnTtx+uaef;#DDes4Nn3+$xD_S_E zRIM0F1~EFae<1j~paUJOfjMHmKP-sRiE}H$smNZ`yQJUV_OsTJX}kA3NcwMT z9T(?-rCCw56~e54f1B`-2*%{)>fsmrvY7s+w>{Y~Xl_Y8`rGX-G=P4@5ycHkQ4MVr z(U{d&;&bRVA++d_5Oprs*TJ8NG(|+6_O|33A!98C=Ew|g^qL!7fQ0X24modkHfAji z8odv`O7z5(7-E82%J*bp!9A5w9h~XHgSV6O9MK*Z*&A&E7RpKo2!W_7v{r60m#pn4Ka(1lbjpzDp#uzFl-4=XsjQ9g< zEYtDPx>Yxw*-_W6`dgP5_oYd>ZUng?cydJ3pv=)bt{|*@_G8Z}@Eb_X%6Y6A-(X{a{F78$L!vVO`bhqfoA5z@pd|Z!a$J*@NA}4IdHu12 zfwT~VPb$@K@$fD~H&3LZ9~6Nk4U+IzF&k*W=l0)lSPwj!^C+snTWR_JMBlwo1Z@nz zraMDD2^NUqw7FAD)?A4&@FT-uY)u3MAziQXK( znZB+(J~9x#uVI_@udnVriTQ>qY?mibfogg{wBC@g=CJ)#+chgT%eiw-?~z~XZ1Dnm z^}nBsuQz)92-QnSh;H*=-6x^5zJNJYnep_v52TD%RcG(XrqFr{{M1>)1;rl!JMDDtpUqGNc32V3#T+n~3tXS*vC>7&vX7gcRoN3;Z zIf?l`*|W-f0`gnF3O$kwSvWC3G*+h8rOHN1a{-#OOCsMSv!@=XQLzTwp^j(tTdl9G z1xFiO03s;?doDF)sJX4FcZlH#;S=Qy$wcuC9=UN0AgALAR7^I zhQE@bmMoaf(HUgL9f*sIOuD;Z{UqPF*7QeVZ>vsZ8z^Uz>Nw-=D#=suDyu%pd6il% zGGD(_VE*2a(aISlZu65XtB*=+dK`xhzfnr-RH?;|Ak&-!L_ShBm*@3h{s<$_PFv{zNWrqX%vkM*6#G&KrzDSGWaq%vWm*_78!4AQCuKDf9x>e#`kff0EzU38Z$sj$d$3 z%SXV<&KBW1Xet=H;kLSj2+k;A)$P-B$qXYXJArGj_dym5`hfFVCt3}o(~IL|Ev5g_ z@4}^mOKv^*bT|^O$4zDS7@4f}{>N+-j0>lpfEy>(s|q{vieZH^?tl5SUb|ZJSaP&R$?2$KzJ^TYgxSD-B&ExNA~pNYW_X2X_?z7%mfs`~aabpz zV;?faoS(mH7%SM?nW#0YQkcT`P^8qbch3BxmHCS+5(Z=Ov()@{ zR^Nnlb){ej-w`XT+yE}E@;5JNDi?_d=7C7TR}y-#C?DrpRdZWRJQdP^5~S+r8*dgP zG*3JWpq~+Mmk98{K)$q#n>)%96|ua{appUEOQWpO(CV)m>Dm>8NgV9Xlvd*}!uA0c z+O7hl@Urg3~nmkN+4&rVg@006@%hi-}!m#Qm)1yhmoixJSQ! zVu0G#-eQK#pRo&IX4L*G>-vX}jU-VL6UOr1?>W2Q|0wPUarGNG=Fa~78_}e2DakyP zvY;(skl>I3A+uPf-ANSB^~-3-aX*PJftKufus5< z?@Vd{)0w3$6@T6#Il$2WHBgkJ(0vt!4h!0XA>9i#mFF7|qD)=8iqHx9-*vpM6{b6JG_bj;p@}yz=*bkY{sfm@v-vy?-m|oy6)iq; z7puAMww_HzR4>;xcG<6NJS>~td*R05G+dX71OEOe@6yel`4BBQW4c%ib?tAp{s{S2 z;;i`JYx!zDd(%=Mb%E2LZm4HHNyA#KZYG7uJg()@>A z1G?avOIZ~xP*_Xv6GOKHh37s23@jB))dNQ&~i zr(tYWX^S({)&3vl_HPB75JGwGzGW@4q-yose=U=OM6+0%T{V0_E0>%9OcyS0Dl+j{ z`&XEuL|4pf_}FhO8`WOjM5TmgMC@fue=nJCOMgfn@0&VWSKAyh`A1PVYVTl{H&Q?A z>1ez)xxbe&9DND(z>$#2-J^v@m)i;EC=bEe@L>jxCuK)-Pql8ma-mgmdbH=)`r)7* zr|}hgjH}oss!;2ujh`zf*%UO1Cl{eh!q58om9?g0Wt`Lq5XxpDJarlZwqp*o$6+TUM%iUKR{j?z~DGlk7EK7)|fFgcVt@W6m-W+ z-Ni7q|7}jzM04T#&aq>xc9P>gS7_5zz!P|Y#PTB^Lk)0}9dyr9*q#Smo3^Wf8e+Hx zdQ#U=T`=e98K|{rh!tFVx5APCu}_AJ5{zKI1cb-$JhEwh7x#dWlU2c*Qk{Q6HI=rj z3M9+3@6n>(bCEKFSyuy;TV~xVPDKwOdIa^>9S$9jAHFZf(DVg$F#N*Hko&)uLy8`1 zk05%^E^7U<;+(w3pM*N^F-#)(aHW0O5Klc)Y1T`pI zLXSdxvO&`g)jB^F*FX34M*>gG>6ulX_)IdqMR(l8l)|*nX>cL4WMPLaHgT6)5bLT# z+6!DNbJR1C^Ap2&#{8s1(X)RPv_GlmR!OKOOmfALi~vRyQT$O&r;#*)abPIuVw@VPUF-9R9fgV_|pXE?0{z%D`>se#1kbR;U zw)}ILPG*n0cQT!kTNwh_Wr>d+p3Y|8X&F(wWcV4;A8XGmhDS)<8bqfTLLUx=0FjEb zWXLD?h8iV5t7M8-_#(ynVUB^`Nj z!xtaaw#zVXKzM9Fz;a%O|0HufMv?w$v?0uOrW(X&d(ljNkN{960`an*HVE zy9F{F^%$>$&f*%z8g$PXFOZhEvOIB#X;fJrRVEQ?llW&9TL@ee8w~+MG>SwUhysmj zU*Yz}uzu3T`7|m4b zpxNCY@KOvpw}5={iv0)uBaC>aJhP8VqHzQRUA@t5YfQzCKbb0v7vW0~!l%ESbT-yaJAonz zPjYT?n5@soEGONlP`fJnD(b{4wL1b2%28V5kWxJpzRoiH726MSB*%po5_wC`z8I?% zPti2ZW|9*NvPCirz6MRH3S!wl0a0rR31(jh}3BQ z6ndt>xM`gVI`S%Cco1vm{v~5kQ}EftA%n_uR`aDs_`$8 z?^4*V?Ay`W5IQ8lil-GHRqxLbJ%2b_QMKQ3qAxYu@l#G4%||+U3okCL3gqg89ayM0 zx@U^Z9_k*>C>GyUD(oB9@I~x*=cBNcU6!};=^GV{tE-EnK7#cz*?E&<@i&gI#D^$- zCk4{^AnRGo`agp0R>Ks-LhD*c%qCOvFc*n@om7QV4}s{HC%K5w2VsGThjP*eRgx|E`D74`hLOGS1-nD;C0E36kTpbsIkYkQX7 z0=>slzGOq0CpRwX!l{1^3_h){+`rRIqR@Ur<;jIg)P|mxX5#vW_%qp#+*6v&WjpnoHoS zmYtl)M+w-Mv*FYOC=&B)sgH$VlnT~ zyJkAWsRco2RowxXFz^sEU4Z;_`(5Izx=`b~#M0+EqvtGZS9pdw_X3y+=0s(n;lmzq z&-cguIJ&)WuYG4^S@LQ=KKU!YV_xenS6Nk{;be>)xu9JY9>J$@MUPcZn-yr)v6ik!>a;1DZD7jKKpto0MEYFv#WuvbYC6ymHV4U_m5n~Zv6_0Tdt^v-*zIk|LQ ztj{!5E2MXNM)$tkm?C(<R@`a_JT|P;k^+Ex*>#tc;WPbYsUlH87gl2GUoLeXv37a?1uUIX?e- zCaCHb_xR9haGxmqBS4pwz!#4iwt#fM9^iPzc1?CbbwqTsNY!tQHAtAgZ~Np>UE~{g zd$Q!U#how@4hr5ENJB+W}{k)%z5g8I(@(cA!2 zY(r0s(S*}rR3JjTw&A7Gv#B`b?%b&Rco`?Vqet3u!N?yr!!(^X(!@nA0`8#z&>%M&X-3Mk7*lTAl_`k&qVS76MMm;=YD+c3iw-8c7VO zkOTy?byslk3A;}>*pcVO{ZbXrkmcL-G4Fv8yU;(1Rz#tzDs&!zlRq4NYE1EccAsJ5 z?mr4?p(7!?WyQO+{b|H4QZ?{=DS7Kf=^S|oeu>}zC|p%6itUWySZ?v2Y`lfvvjHk# z>gjzD_W3!!I99rPIb+UV=x~ggOy&C%pU{=5f?r(&Gw;rF=HTC=hkiXj9HBh=uJm!U zs>QxyIx4UGV}3MumPBc^dQ+`vsVSu-NxJ8K9e-o>7pW{~GDI61%SXtQ5hEd0 zi|I1S^&G`4EalO@(~iPm)3(-dQT%cZaG)>{k?bc z1|He8*Qw=EW9C_3h!^hgv)Vt(4_buNxWH{(bPoe14mQb?kB(d2T{MKnB}Y&0o|l|O zp4P~|J}c~m8uCPA6`Gs$)D?ytgiKDN30@TthJzR1YmM9el50+O?$2?|e=;u?n%-GK zMm>lD2FXWAms7J!@6d4>q*g0Onf|^SXe2XDJRo<0YgW5J3;eqH5bX7htQdh`GZVjW zHxTUW#ok@B%UF)xTKp9h+Ln1sm)-C5bzQ6Rmg1iEGBEYT3u?p{6chdMO#c^GZyFBe z`^FEqD3wszvQ8n&zJ$s$ZT5t0StlVe7_vJqv5c{18D=bF zn5F0b{+<`l|M|c1VvfUo%-r{VUe|ej&d*ZUI9^LycquZ>w&wgI-YG%fF{X8i+@x5~ zwwAST%RKvlkVFb3%9F!eo?9i$Ug{0H3jq{Ft__N;VtJdKk5`&{>kP7_GOJBdnjCOH za6r6i4=!l*9V!$`zOm*zR(l9^Gp8O>SqWHvI@_3*Y)_y{Q~CT5SDQfgjG<832k$k; zCg{^B_Bis?28a(lpAKv(ZUkY3+Z}Y|=G5HI-}xF+HxbDp<_U!6NQ0{nrSTR1VVQ01=cR@$6OY81MWKloftJM{EYeo9RTFt3`7RRi ze+?RZ;wq5?qAoM)R!ja@=DG?V?m)P1-02w5B|Gi??708M2h!F6$e*SQ^Jkf^#Lt1W zDCCEZ?3Z@FkW3WmNj5J$qy@MM6-AAw89(zH#xC(qwK(qp`V@mBEW5W~shxgkj~S4$hNu-HkC5(u?;Jrwi#C>7&f*)((V!rtp2U`>go7F1b99zB`xsX z&li6XzW!=4f6mIK1&Ge+zxf!x&7QxNXs6KcZFeK(&+7NwJ6lf@nM9o4hxLUGeaUZS z4*8V`O{y@N(~@djfKa6FFWm4KzPY$bWJ#_0pu;I)+;IQM3Q!}E9v7c9_|qhbupRR7 zvNaFaO;Cr+NzkS>dH`GXPgcK&2Y)!dLd<3HW)_rK%ctudNImh}FnNWf6p>ul5#g-4 z7YPG1Ry*P=V}lr)^gA84!?eICG@ZPY7~Q2fzTk(zFb)_Z0Td*&`@oqQ3yXuh;?u+^uoUmA&)HL(R-K^ z)CUCC4=>y_3>TuIFU4yu+tA9(XE>iv360TUR7q6(UxWy*GnXu&k9fwKE?ij7NY^w- zZK4EI7MgUz)MW_2&tJ2Q`c&A{_(oe@KfU| z%}AV`XaItuM*64&UMP7z6(+Qk!0=00D_CeuTt>SY>=O>1En5l40 z9!97?y^BECWghIDlRgqU{GS;Qz{-C=Z$J4R#pXvx<#zk?`~ExjXrdR?|KlWyTR8X3 z5}K?+i>2LI3&6ozU+(L~f43cH4_oEg<9~R&X!4Lgj;QbowuTlP`yQ*(e>^#{%(90; zgP}jJrL=h8%b#TvjE;Qdv6>SGyaN(YZJk6{fc(~g1_lZ5ec<8NfN==mhU~vw<6K*z z*LN{Pm3a(gTlovVOQMwfSQV5w{;~%63)OZ3NE8GU64fa7nbXB}Gck`!_s=mm zGOX4_1Q+um?AL$q?A9458;Q6;Oc2uldmMU0t7Oj5D?zr?mX=ka2M=z}w#4jZVP?vvgwj2~SlitU2uSl77C#Cf zEPLvrSf&s#T~od%NrjRN<);NH=#b7VNirpMQ94%5iX2q5ZVVGLNZ`5r=&H`yO8Di~ z4bxW%!(AJEo73~4Xh_BB`gy}aUb4KyA*C^9Y0sMK9!&!+RR zJ*ArEKtboR1nw-uSoJ5hPxE%;EqLq*K5_0KF5t^pYDvKdx>_hA!lcm1@x3C9R#0@< zDGBKVZZXb8bVG2Fu#veKR1kXtJD-c<)-WdHZ1GVkfH#6n!0W*4i#=iHAA}xSN4xwx zR(JRlg9~DwLzB6z$c@$X>#sLmNR5?=EkWlg_tzY(g|@FP3BGL>Gb%JKQX8{iVdy_{aBku<|Jt zZ&1zU4hMNaKnnfjBAUZ}g#Mb;o>m;C;rWVNo`qD3~DNS0eF7d z5l5?NBtLT?o5Qj3kA`__L&V?`BkcA&V^w`+bb8h)1dYJ?9#s(+{|)ho1PNF1`%{d# zeU&*pvQ)DZOY4fSnwj559H$#*#JMlBiAn5h#R3#JG^Gw$LpB4yAv8uSqVq_Z0~xaW z?0P!ZgvjrQ&yyzd2=9{jOXMjWRN6f3{T)!03itxF)a^~iP=oh$Z$4L;kkG-ZXsm~2 zXMPNzt^Lka9Mw2g0B3tV{1sZ1{vJ6ls8I1*eK zGd{SSp~gZe67ZYxuQfIg*3A7c(GUn4W2gIQU9BCh5Dx09$~B5pYm=$bvQ$OX&PMIZ zzXJ<-F(sJ&z}?;4FSz@nhBT1r>+3PBAgxkYFnvL!5NhEwE4H&W{-QemYvNV$Lp$?8 zlL(jVXT(l^^tHKQ0We4R2Tx{7(oRD?Un!Lu1w)k{^;cfJD%pROnfF#Jg4%;3ZFiys zw1fvq=^Yay*MHR{bn-^6@H+AV7+9P?QFS^1ue!oLqweLc44D+kcN3~pO*(dKhj`^~SItfbN*3NHKkI0ffqg)P z`v;92a?3W{UN*eo(&O8*k7>rlC|TPx=kDwUD&16^wu{Jt>Be2aCi^fg5DzO5pFSi^kp!0OJ6o)l#+r`xEaRLWBk||Ml69)>bM2pO-{Pbz#R;5hDbw|H_ z8yd6vZmej?N>?ik)7r-w2jQUGFQWMnPK?ZbOq5Mmq^G^mMw$g#Z%aG{ks?nE+vRV( z$AUU5+>lO*CU2vg#Hpw@D*(Q`EN-gXceli@;DzaE-H45ZsRY+F)+8Qh8Jd$BbI7~?Sf6Fpm%%S|E*cAh zeMk=VGHCEDyvt^I4|INN@asjMf5$%k8f5=qHF0T1?;T<+a!RM`5P4KxEe)K1CjVQk zuKqxH{KV9puFXk3E4SK}4bUOKf%yHh zV^9}7wRqrRgC-=~^%03!O5>g3eOY4hWS3AfM#kg*tz#wnf_e*$&zOHem3Sg6NxAtA zHXQNlCO`ebBA9xATed;-xs2S4goQJCaVxJqd#ih6@S+~V#_rtdl1>!W4FaeGus#D$ zbO1mMpn5>A75k+7DOA`!l2dqbe!P?$H=n#0=kOeQy2TQ*Yc4STU?Ghe1sMA|Ae0$tsF&ba zfv)IFyUa@G(?GJ(-U+9RMe-y#R= z0yiP^*boP4Qt>ugLpR^9MJ_+rAzQRFFpON1rC*}u`FCmAMC=t38Ls6<7G$0?D*}$u z6|P}S6@(b6Dx1JNy!UjESK!n0rRW!*`b1Y`YqSS0gw6*DjmCB1@Ku0a%`}0T1f91< zy|a1)iQP(Y9reGyTBUpsMhlC(d|;6NFg3oD)NW74Bwpk((RPM-q z<+aXBJ4}4zxgLJWJhf-^${D&ZqZ&w0+y*+W3UmmDc^Y-ZQpep?3d!76ZV4NwzciI`9=Kts9LhGB*z^RvLyX`H~&E zLo-gCn68&tfu*4MxBKC0ZN@lh!a*Ad_W@o{c}3D{XyU2+tb01#^M?_osQHK0N+e7D z&MOP0**BCgrCL|;$YC%$*3I}boHl>(mTp91H0UL`qjL>iW%?=Vp}+gR-#P0V-|R-h z>biu~c-FGZ!U5l3xO)ELzyQpogRqSYpq$IRBirx zTPUhn&+<){Cs2;#RP;Q+h^hz$ayEk&>gCz8H|_7M+ZI0pl^MSFcEXj_l@VE2JXR}% zb2#Zd4-x94NKvZ%0uOLz_L3OA77Q{Sk%+A5hx1O+8xz;Sg{U;<9Q84&VKu{xNm*-f(^rnG(n69ye*zF3ih(mxYg)I zQd|;HfU|4W0s%$b@jdW~hosyGGWAMuA=0g{_r8{x5ioB7c3BHJ^a8?=DkvW&NuCG? zLffKP-alzF2S3|Ar%TJj(I&j5I}n^?bQ_8kfv_S6hI8!lA zdq-)Lg9Xc@CcspP=YTJUE=vLfm`-{78{TYk>qdLlwI+DwaRNhY9JX0ga)&!9dwH(V zxW7w-c=PxYp3gaJgOJjyK3&gUmO>NRIc9NJS(|++S}1??7dRKOQ|}$v^6kOFlb(V!g-nR6wk+B69O z$z2LSM^>bIpjs#ScI4&LK)V~w>vWWX@l^EVV8eOi@a?t;k&`lyqHbTuw5Tw{sIqy6 z;SR>Tu7rjlx-|mr9}W-;`LDG9K*HV}=1>-^gJAEfF7&E4r2X^^nOKf3Ix+(+W&B*1 zQ~Agvnoi6!fvR{ugmnmwa>o#bSDN7j2=m_rfJl4$Q{4Yiq7o2~wX@W1t@&OVe)Ji& znwM|KOtUV)S|PX&q#zahAMX z)8i*H@xyN^N2R03nviv5A^koXAIcO$sEs3~*1hERWF@-iitaZb{>87ybJCoDK#Gxm z$aZWcs2z(FTQrXPLJs}Si{u%un2t5xT>q-wV0h)BAdNViEIEulO8|4ee7=KddgAA4w^Z9oAPPA;WZ)q9r)zl?pI6%0q$Jk;!LX1Zky>|@0e0q z9T39st^^StehZ1XN&0Az8~E7l)dp|LFkMC1BS0=of_8t+w(*E5xq5YP=OI5>5l3$sgh_|~eeoH!5TwhGplBiChi%+{ z4WSZPvnAM6ASD9G5Zzcnp*4&P4LMRt6U{?LS3gS58D~F}o!K;#q={`fxPUtGI6S3o zOr^+p>Q(P_s{_X$mz{L8x=-4&?U~^jy^}8-0z~PBIx9<7d%Ub|o9N?l1yNn76ETkd zb5C>!#|IQGZpgck_3K}Y`(>SG_)_nhkgQ*esguX{?Pq;i zNrw*#5!S%|@ZJr}FAIL*R@tus|I&`;?JkZnJ|BPBYFwe@Oi!i9!khS(GL&PRpSz~s ztNU1wBIsIrMt40)0zVte%2wW2o=*-ZqqRv0Z#ryjb3ZtErfNf_S&t@`bng59nnUkb z<37l5#67dK8odo=`|fIpf^DbuzXthb=t}&LQpr@&_L-BNQ1YwAMHsP|Y(|M8yS8B8 zSIkM95{54#+woC*>(N1wDt? z>4ryJuPc0`DoACk4s^f6Ms!+(nHn9iGHA9D%H~#~ddgKy!^feqTC<*c$=B0YJeosL zy;_vZ@en;*<``3Q9OcY;0pa_Lgs136`te-oEia&HB*4sfomhVyhO=&^?eE616YK)V zHe8e{^DpcB2L`1&mY;tUGcINew5H8kdZd6#p#PJh#*;%R=9hVev85VsX5J*-|25V>SaQwNLieO$^by{iLpd>GP3LC~}Lj+D7c$T@1r=B{CI%NrK=u^1~ zJg#7pC=`1RdE}%*RaH8tvhuZZ;793B?|7-cpC~jelr6$+ThE-UBB)9c5~T(?g__Sn zRjgDla7F^8NdT2#)lh_q4_i;oxvL3yc(>*+-{Z;e4+SBuqqc54#z)bbxWo9ed`n99 z$|Q19(p<+Rsql@Ry8Ab_H9nQOAcf85pbVW$M z$^BOYefUYBXuXm2ONXhXO=txvWz3eKoKqXUVEg)M^VM4s?~TW6pMPW3 zoqfyhH-sc~SuKJkQ1f3Lq=4rB41D4-^&J5Q>fvh}yg1Y01atKeJ3VJ%G$_>FGeEk$ z%}(qH>LOyvy9=zF3=*cL&bYOkUX1G4>2g+ayX#UZ^EJ{Emh$@*(vEc6*nKDW$u~3I zuRN^1gXks&8|Ey&)E-ET(}1@vcxWk&>`Q;%-15M=NrWSYDzfb2>!cRXv^b-aZV@5B zke5a)8+}{va7OM|>d95sO9xH7DR z{l|-O74Gq-SqijZ2Dd8Vi<`)%9QjQYAjVX2s^b+tguqRblp zqB8M{w-$I*Mfha%-1Uiy7(s@-L1TS&clWMiXr_|Z7pn!`7Hmv5$wD3nYEfg}q&_Gr z$^HH^klj-z@^m6hrd;=O(l_l?p6}}XZ{EDin81<3*w`#TtXo-?>!l^84T-D)&TKe7 zN&%w;7}2`z8HbqR{sKNO(ghJ3hDv2myD1`eVf@c^*_Z3H?|30JZS$K<9NqliTfFqgn;^hZ(#wc54I9Sm+lwBO&5>wQB2UDiV3-)Z9-?V6xks+Qoc&@Ut_(EHt3 z$e3&4UTI>?{@?>zm2nC|1af(R@6$*i5ql_P;i@9(iJqO<&8xx&$2ObmJPdN!WQzL_;9K z;z8ls!f~$d`Xr5>6MS94UnW|s926K$2_92??{j+%*$S(PQ3l(M)@Qlll+Q)$#Qd*&oUPmFEIG#4CP8@IbjvU8Z*<)e zC*F~1bkW_-fyt~ww1P9{_mJrflI}W)<#yr9_##NKOY5Pe_|z?kjB=e^`Ef40on=C3NoO#n-%k>aGCSld91quV`65Rhg&@|EwB@RgGAps zUN*aE+E_Y+A<@z{F;RX+3#DxS&REc{Vw>Zb!DV;Ohtsg5Ly(F)@Erk1U%=P?ph<9o zd42W)0IhRu$X}?5yESaa`B}$F{*qi54r#V4Pnsx1j$;Lxigb0r)b9hJ50$9?Uq!5-d ze$v#6wMQRcb&0EsN5NmbQLO@{aM0J1CQ!e-le9&s zcGX-O=1s3Zhw7l&$=3IYBL;Q(i7XJM|eY3{@e|*dYtk(uK9XoljFlvbn z_7hCyq{S2P|BeZrehZFXy-}&^dId4H^$L|IB>-IhtYYYZFLCXjh6$@9LC`0#=$@Oh zYL{4&ru30F&|N#{R)ES5qW1n;gir0)kIA%!&9dC;2%KkL$EqA=@GNgtE)8m*;}t)d zjqv{g5tEJEX9%;S+oa?X5l#}tw))|M?s=FC;q7oRF$?d;_ymaMGrBxaI-@3BFrS%P za7c#|vJY~sNdo?6tWp|t?4E0|k5{2Sd|c%@60$|a^pi)^+k0o@DO8*2Nga8^s^Cll z7`HnQi_j2uTr~W5>|#q!bj`z9o<$FrM4_%-|JxX#jd2Nj-6V$`0da%fjL%F}R)@%1 z!oQV2H>QLxYNHi6>$KLuq^o8Th>`ruSTImYiT5==7Tl1R&m81teD-6@gfv6=8*C&K z2K8#18jSS5N<53_Rssly>}3;x~NXj#~=S%MX7{&(#8ng-hf=b5~uLiqHiGSzEs9QUVPw&cO@$35bo z>Fuu727AWSgKa;-uCoF-eb@S?VGV6J>3#{HfP>?S3MkYzN7jA?VKAk{${*Hko-Ls= zYiqWi&4#!&g1G4R;%0$Fl6a`No20LJs$=(IQJuAN>`WSiBjj<63_@FHOn=5XM(S4z zG>RB?@c2bvnccBl9sWpeRE7KaMGVUzzYxlABKor~BRM}u^XIpGnz^PaNsT1A-AwSDE%aPh-o`UlUWi6YBbgU>czY|!jjN97C= zNC$tchF$UCx+B$h=DDL$}cOm|KgGw&) zH-uHgco7w$C@4*QlqyllS?~9GO5lqF(Vmm@*7N+xAC05f2Ron193cL-PfF)ywj(la zZOc|)JsKeKg#rc==R}Eq&=2zoY+4|1y{R9 zZ6b^ogSlF98qrFBKPGBKykbcZVeMo5kzUgKUR5q)SAAw!2=TR67>d4>WU!kMZ2WhN z<*SVRdBXKkhh3|^6;EbvWQpvUAjj9z5fuswpcxIe*J0c0!IA%taaL}Z!&8r^4Vj&K zj3-Dk3Kw$1GTn>K0^IE1WY~FT5BDluNS4UHDP@=dA-Lg5nmJt;0mdYx{B&*sBCyg( z8S?9rhipuW)zvf8jCEkuo`kkjPTGwlju#o^szjTLUsThb{~wmqOpxY2o3!ye%j>AS0w;G$>jau>Rc ze~&%p53n-c1mp%0`fY?&gKu^|(GiSRXP^8@zGY>0QAkD2%L2ehkF@v)2_b|AuY8fdrJQk&q0I;t z4dV<$iu-{Z?i7WIWY^nSl_t7bc8aKK|2y_f|KG7Ul0%6XU=qRyW;li3*O-ZkR`d=9 zB6z$1dE1lZ-W7XpF}yBU1>22wPdSd};PNQ?eX1|Xih1q^pw`AjGL_s!IEP^krVA^H zM76--4z;O?-!e~x41Pv6OJN{M<^dQ%cTiz5Fv*j@#r0KD5=f2196ddmpL{k!AM75r$XCAlt>kl zgw@EW;&mfuukC~g>7}#wB?-+l2nn?nb!a^;d#j=kdG`2SiP~j{Qz$+%Cv6X1n^&oT&@0y^%tCvX z`;)p)jvg982LBzSbA?lGP}OLLa7d?!DD@XE+79mfBx*?3(@Se0CYE=1#WB$JwvYlQ zmyluDHc#dXJAf4U`@4Y}@a)KQfX6-8{2?IR4Sx`Qw<6;(p~1Q5=FXyfMVacV??^Ec z*h*T|92@EwznZk%@5IQm|GvKq(=WmPThmm2!COk zPvt1mzdnZUMwNTki`5;0&H@+F#&`jEzcXH_^-7@i!n?Dknb;-=<7%D-FsGIZ;vw}E z@UrhxeaLDpSwi-2gyn8oGEcPglqcx?&hhe@&YHs1_5E6Jf}DF2(D3irgRmSe3q~Hw zZF@3=@_`D*tOKUHS)gcvb_Ll~-p6vHb(WX=d+9NmI?BCdNExX7VUt<|BZDbi-TqW$ zqWx@+?X_V8Mft4>cRu0Fk0<6<>V1Ez*r`GURAzB+-kbtOW;HG?l-Oiq_AtNGmtzNC zB(EmJ3&GUX-x~wQdnE`(lUo= z|Iu(A^k`*SF1UqP+x^aw!=Ptlg`TBDa|r5D{sby7RyoiW}iVdYlgshT0O~K8O+FvR)3CXnuUy z(L@)7WZbB1G7LOvudqYg&7GO9Wkoybq%?={zuHLOkT#P(@7pVxu!pHccp;9loH$kTsKn(_~Hsn(Zc`^7J4 zo#MSlgqYAz!KR?i2R3YQK0}&oq>A8~_F@?SC*fYU#2VshZ24b9K4#vt8^fr2cdJ8# zqwI`+lOu+%?4H&$>Wz6#t}bj9wmlui`;z)cLmP@Zi7WF|?2AOXbU>M3|$Wbg0t|=XB*Uc zORvptswL>w;4153)`|zd2f)mxznsZc+&(EJ-K^T1V z=;%MclE&Pnii>?{cgjU{-RWrH4yRHlx&&rdL$uESRej{?ul`jjbZKTrac9vu&j$N| zl)`S1f5|jiOq&}&ldkcI;`{XWtJh*H*|?N8Nag4pFDWdOtVYN{at+fZtJDqqRTY=Y z=Z|fziKlb&ukz5eNqn7eFmXsOILw~RRCD!> z&eJ$g_sus3*z-dBwG{7I-wxB>Y3?+jw_}ZvGY17hW z8lvya%$<{Bg^7D5eC=31lshc6%!Upa)s+{*19o+q_}&X9SQ4BQsacQ9bVv7HevZ!1 z#+OvpZe~{plmbWM%WGJ61hjZ=dcEpEz%+8JxOos~9!nU693aE6T0bk<7;9LB9r$6F+N(%1+MdLYtUK?p(Utk#Cdk_EpSf)ha^o_Mz zg*K9kVSDyvq%^!uUw|(fVPCkRdc68jEhS+fx6$}>f12gp3XSQ&zUs>0t2FU7R&&M| z4RPYdWHz?2`g9oS`*m-;(Xv~+u@i->9ZY%*3&UT~;94+_!e2!A2j$MR`3J)LT|EU_ zS;Do^4uHNQteMFv3iO7Dc8&8zDI0X^w zqPv|5I3G*B5DcgY`n<=t+53Me8lF8b1X?g_VMrO&GQiA1Egmu}@hU006?BOyNjFQI zyZrN1j+>>Dws3s>y?f$#;-1QKlNhyn(fF;vXA-tuUgTv_{@U)vTsxb1&EF(Ng7fsB zV#5IC4|lS!z-i4u@JP31byjr2_2dCCye!>F8(w}&Cz88}V4$z3 zRFX8qfl)i>n$^Y6-|>NN-&(G|KY$tEy79uK(fd^;=^(b@#)AAQ>U$IiHQ&fn{z;X^ zrTgn9ad#FOKP_JtWj|+jqRQUTgC{)b4}MU;HeCJYHi3LJ(SIi8ptpX=q}2RW4G7G0 z6oDt{;KOk<)dDFIh}S>Z(o=;$RQ37M`qG}#P)MixqR}JU3M`_9aT9KFG);XV2kB=a2|7~yKC4oqLi7m z1XuKrE%NHyy+civFT!kmJu3Zb-w!3AIPSfgE^#i4T#=mM35L;WpD)e4H9cf)M17ZL z%qkzcgSXGqUodJ)Y!)e@*Y7&b~AJzd!naMZ{?+l4a@>@MLwn`$kP)ftx`-EuW}2 zMSlm1MP1uFexwGpz+Jy;8yH{Yw!Q`zx#Y~2b8eq*?m%X&zd5x^A?~fc>>ij-GWQ-k z3g=XJ#1|aGE_9_|+Fv!=*@fwGG-OErk`jI`ngu6DSpdI8j{r=0^to9q7&jY_i zzj=tAg!&&s=~1!T`v({tDwP3dcLNQ;=sdhM8vyHoY8nVzGy6l}@%j7e8HC3fh?F7XON!GqAOF=M|)eEQ=9k7?+w8c;{@|r_mQftJf2V(R3 zAV<|S_2ljTAlFOUyg zs7eiWhrd#a|5LCeus;}qs(^HXqYje!{vEqO_buG;b;~BNt<2Q@JpZQRWx9pXyvy5} z;Fs5z{jgElm;4}X(55p(bh85MzarOs{HDcjV~vf zLa4HUOg(^+m2d|LLk6CTAc4SZHcVesLiMIpu zwSP`iE%B{LcG92GZRhGBw9?MPe;ok+zd za##vsFwB8%%y~GEY_a+3knhRQRu)y#^|{^wa+r8w33*pY08J@kgwkDUitv#Z5!OV9 zO0v;*+<~quY-}?TPgnz#e7J?qxGbKLYugrQfC!ik9Q!Rk@%e_gN+D9su3H&V!v z#kqWG=Pa@3rk%d6S@&1KN5uC8I2>_ZC2d@~m)+j;mosOg8WF5W(dWZG%%_ zN-*`^H#!t(C5U1<&?Cy*kshei>s&kBU8bMX{niIfx&vM627B(sXIE+uJO?|_C)Pn1 zHS}qwfR+ja@Gm=X$hT|q?~1n&(YIw~M|>krhP|>%8ED((f_zTFlb(S2+_A^CuFx-* zkvuaS@$Kxorl0I>nlGwpf))VFQ0RXUBHSadJE`^4rrJ5%W1X z<`ThjonikAs8(f!Ir;4Hmgs-Ovmt>=p1SJF)bHw%9xN6XiI_PzU%OBM-MAP;`B;Uv z$Qo&93f9@G1XkQr8SV+JxWvZ}t5WrFN*0qW!KWpSw@ct3?25I%Nkk}9bMxGhQo}F6 zB(%F}sWseibF*VCn7us#+u!A6(SwvHXpM;R+@(IBT>pL^+xSy}4 z3Sy%huBfiaOR-L;tgBndJ}^hRi*7y3egEDk@lViLbiKYuo`PXa+&$K-;m_Gcd(BN) z(jU(<%HtYF^m}AZYc^g#InyLpK_pBBRm-TY z3dY4lV}KxHRXZ$60-`VKnNyTQt%19TA}TS584Mo>TN=;o+#Eup5u3IA-TuxYF>NO1 z82`zWN6aK<1Y8E!L+aT#-UV|mw%0B(I7_~bU5Q#ad*!*1n)F}k74&pBBWFH2=@tH# zkufWXDE%CpyW7G1J=pt7lC~E&$UO5-JY+$wo%)tB?WW4Yc({#Tfgat&bPkUHkK)g% zNT$18>&*J_ae&HVwR@IqIA008w;-Aa-I1h|0)IC4lQ1f`w~VS+>4-o(i!Z)iRH1h8 z326nzwD*1I`y1>$l6Cr%2H>VOGJ$&OiK4_(O-U&fMbccRf9^&<3YNQ3(h|^J1uIhm zN4v-LUAfgJ`DPC`RYd3m-n(ofm{i|#@!zq$wJg4|ihkApj8sXH=b|5xWLO=t*hYp& zruwASDZZQrd`?33yvyU9q9-ar*2wew5b8D8b|RMni7yJtRs_j6DlB+pZ zrqFx~Hyp3v66%6w`(|j5nsU!LUbXbCMs;Tc5t?U#Vg||@fpA?cN=kTeLeO4Qk7lu1 zd>|GBtRye9c<#+Y*pa>Xv%ng97vWgXs6eXg@}{3XY*5cV&zYptEk1S7Pyt%+S)NH* zi#eiSO_}JaaS~3ma@ZUBz?Xt^UX)m0yn0_CcN_eNaZmDvwXsd!D_egQ$k)Cn`!#!s zuZRYzI6Dr(xd1-pu6VY1zmF|i=ZSg`zX`I?8+DE@O7*1~x?{^hz<4GGRW4Tv^#w)3 zO1@W*Tr;io#1XUx{RXqL>yJ;&Oi-}zx3U~l7GCu*Qgu+iqjW&61Su;x*H;c%LWa@L zQDuL^eJQ8YTWqfL-Z_Zfi*CHX^1SBC+zt32z%KphV*!;3$C3=QBeQrD=V!NDt+$Ie z>4rJ()yn#=GVgD%M0qI0U;H&#`A(a!K|4&l+`8(@zHm2r#v^P%8ige|UC}?}mdsJq4Ph0pyF~+ zo26}Ir*#s)AOZ}R@q}Fc0a8KN(>f98(b^02&UcLhI|758pK&qCaFY0g_&0Bh0T+oJ#x(H z4ag8uaM-tJ7v2{57@SI;8YKTcVus37rSP$I^`H4~kpeHR$ar|k@R4o)``M5_uf*d* z?g4wifZor4p~eW=x-pNXb33&T#raPQgBTWa`1Tw%8%V z8Oosrp#}xg_@sCa9`(oxNc3sbT&$$^Z zJlRj$+cTjd?BzLJeMr)i?hKM)@9iy@?W^$%iO=vA$%1!4X-xo4?Y$?wv(1F6z97$DmFfb866_6b8TD6LZ!Oh;Z*~ky zzE!1J?M*~fI>q()m=`=qoElI=^%v>3xtM0&A-xK$qg8-i?K&<^-#z^FpgBiVj1J`ccGYEC0oZOxA_7q4xTSb^D6qejy+L<6a@oU1&-oE?~??gpUZm&TAAH#N*?yhuE_qGL6D4~#2c&`N<3gr%G_2^ET(ty-#= zK2A?}aQ*In3JbjY>M`e)zo-^l`t4k*7{!%pI*(@WT+8`u^E1HYb!;uY-j+2^v#S=z zsdA)7DLz+&d+N@n?VDo3J9T75N?6!Ig*u!|W8RZ(ds!vo#Ie0p0v-A)^{R1$YzLur z7@HN!RI7{zsP4=@QWQGl{9Kcp7u<`zttARKYXOnWz^C|`0(6tn2I*YtOCxf^5T4~ z_2qTT$gn20Cq@^Qu=I-QB_zPWtGP=Y+%T%+ebT?-fVwnN<*GI}xGj;~PCMgaW%TVH zGakzVy3r9p!qb+{rL@9zKY(B7@%5e7@qaekTU%24MUe07?Nt>gq5;c}Q!Xd*h}m5-{$s`a{}A@( z;ZXna`>#^T9MgHY9MtC(A4fStzGxe47e(ZJg43vEyguE>}DXznxSf+g)yZ zXn89A)jCm8*tL9^nABy2llav~7x>%uzW?1_8{hb3yLZ<`n@XTGQeM%dG2mac`VIy= z(#FzcLj10w&jNG62Ud~YI4N|dYXHPh2HU*+jl-yQB=JDWc7*dO1(y$4=O;W_d5({d0e0G~m3uoqnpKNIJQqL3XikSFPyjurlSvSMdQ144P z4_RfmU+H`-$bqr;W_5)cwAozUFdZHRmNkyY`mz*;gm(~D#Uk1p-;N5@6A&@wMd~#} zFwQssQ60*IhI#m$lY{_R3P&euT@Cb$nL@1#8JXD=`4zepDgwm#4S?EX+^eXl7D+`} z{6x@n|3L5^*?&DwVS(BXw9Q@vs7kjJ0hUs|G`jL#_e}D$onk+S(_*|dIT<*@oc^P_ z9PnF^XV=IrQ~_5?)GpI3lhuCo z0K!$NwEwY-Qy4;rD6}kS!i>qJ^^3Ym$Mimq=<^tw?}+;gyBpA!gNKRUkb9JANR59t zz~dEuL2$usuEM*_30>1xgR)X-<(@yZu}QV(b_Ze^@t#7rqiMr#F3+6U>MHzEC zwlhr{=!OmF!{M)G)&X(PCP=#Wbn|XXqqbcYlOkPq?W6=>x-1=bf~eTD$7>rO>a9P4 zUVH!GIZweSj!B6Tl2$5=X?ZlY_L!=fSMEzj@df?Mqs z^!92@JF$Q`OC%+73mSS`0Q{IlPFF{P*ciFPg*M421r#XIA|IA`hR`EvfF z+NSUJg;lpVHWDsjcL<9*UYdhOc?vk0FiLvefwxq2o^N5gCx~HO-c*{_Ph;^JSxITP}UXhUdzfQ7ds1m^?V)~Tk;#cHY&qMg$=UO%?xB&QrZ z6WrDhBim$K3Hn4TD+1E^L&Fqks6?wMjW4OeM$S67SoOmExiU*%+_${yaFsvbRR7@O zn}!50!@CSW*CVQ@Hj%+9hrB)L#A0@G7hLebFpU@h{f}w{JdLnII6-2Rz$}#O0alMC zy=sGBPDuA{0v$;obI(#}aOHokIhiX@%B=(e|jc~2@v zSB%1{{vXxAkUC6{61v8G*1d%=!RG+BJb!a4DG;3EJqHU`!F6) zRMt;d{nPV2_s|UZPW}JWt_b+W!2iwsA4ainV9&Q3DfmZ(zf!}z6qemiZ*sQ{f});D zMUgD|dHH|MXU_@FH`#W-X#Yng;S))6yRZcwg_G-p&|%8`KYojfX$|iOTLY4p_+Y}e zku0xBGaG?Zi`k@%tps)?82!>-tWRKJ%5vlU+72bA_)RUCu?!rTdJ{kmADiUMEyEw~ zzhYIL+6G${r!buFBdt59bH=VP?DQ z@$WRt&?i|Q5|73z6c|NSe4FW?%<(Dx7Ba~BZuGqH3OY5~bTP9LMbPP>P-A8ALk*v6 z_l84q#yyWs9&qfj+Ix` zM(n16evGbCHIh=EM?`r&_j&T%5-m+DtY_+~^Kx-G7VlC>SN-ui*RG|I+yi^>Q@CxC zq+Q;op*IiP*WTZWEH=>9reB9uy{N+{9`jK{uP|W;<;#=qaOob0uvL(bJ*pz$yl|Q| z|44H$)yKiUWen)L=cKJC|7r=MzdSMEzU=(-h@)k7>1CqSPDj#n34&F5`n1T-$XR}* z=3X4F*T1BHiKtFNHVtoV&C6U{?8~Zxv-^RPV#dAN{=OsULv8^h_;A9?n&u@S=ChkN zHvfFAS)|;W7f{lMLmpH{+wT^v7|aQT3Wrs@zj5N5U^D0s@*CfE(1W1|@SiiU@55H^ zM2_FRDgOQEtNn&Xsiu~ZZU`$0wwBdfso}huQRf$aRq7wrBW8^~NIK{=)y7Qp_j;)& z(~shha(wko-FEjeE#@=9HX2em-X09oDSd@`hg#XJegIYK%QvF)6L&FEL7Opve3cuY zBR^(>^xknRl=x{`DP=MM_y`0r5e}#5ljUubAbN#m$=v%rNck?~vo%C^edC5LPyHBk zv;vWt4O07VX*kTSG*R2)$fg0vZ-sFo>=O7t`xxX81ae(kko_8S+J68yxg;rhYtdt* zAF9=ZyUIg=f^>W{{Tr5B$^#p^Bgx+@LwViIK~!!Mt?!@qqb1$7$~MQ_R0%L#+-h+r zk=9*9q`c3K{>Qo4Syk!51JBfvm@e&XCrRG=s0nPMQT*_G*T1%RqvUmW3Ts{36xs_$Ezaig@C$M7vpCgCmS73#iHfcDKn6n z)hT!b2!CG28)&r$4a{-hx7CQ$xyXmsnsk}rbI=rAs;5AIjzx8LU3@W#e}F! za>gxXDMhSi>;4S$m3>;j`>$tfZrBa=lPK_`O;5r8z6#wF54Aeify^@DTPq}lD6&QA z8eb_uAkUUgm2BX3suOy5y&ryu!hVrOyrD%y63USewxpMAz*T9HnE!p$*@ozR125%% z4j3^OoHdEEh7VrQZQ8raD?J#oGOTqjRs<-Xz-nCfPTgw}NA*wLAoY_4oy<#TiiIg6 zHtW7#R|0rDgX+sx1(~+ZnmqF={shnEJ*arMyNEy4n9i39QWmjnLD=#w#O{cbI%BFYqvF9hmEO2EG z;>4mzB5VA2wsPdgE9xr1q5n|{9o!c8vR%Ia>z(oAdq)|z0)#+7)S0<_+>ygNeiHZd zzG!VtEVmAc(ZtWUnzwHlBl&5^P4C4E`5#$aRnJuHOz(URuN-ON@)I~6Nq{tYut&jK z%r#+_f;gGzwe|Kpi3{c&>1kUO;{&N275LiVMJlcubab`D-E;c!thTl)`yhd>-Ikr; z?G;=cp#P+9T&Oks0H}Ms-m>lZuX%sRt-Ij2NejndWA=}qHriV#sx!C-7T$@VBgpqy zp@9B_VrxqXA>A4OqyMAAq2R*%;3;jnh)LU(Upkx0UGOLf){Nf-Wi?$0Xh7W;PQ_6P zlZe-mv=zSu-}D_FC3g;G|6Lqes#JeS;04Cg_l+|iejz@qQV|93RHVfk8@|#x|LA5% z41!r8g~pc8-d&7)no*j*iW%irD2H-K_1Iqdi#6}EwotrXGDpsOaS7}rUv1aRIPoL3 zgv7Y)#YkXo$3vKW2b@y0CRT_FFZA-hb(6=rJcQavha$ao9m zulXG#^1$ampY__7_m*dZJmbndx$u?GoLo~CQp8!R9>=_YCr257V@aT`_!{3w{AK4rGsbt$K-%Y{~p`xqZ+}5(n+iO zrcL!atXKW6Tt*z4Cxw?;Ge;)`NslKEZk2pX&FNl*bqes}q~qLH7JUpOj}2??8gt)d z7qDpOIw?KPWdItAs%pmT62#F*GtV8}0t(`}Rwa%S!s|lr$TL8V_43CSp=T--xWTT2 zxlw)1RPDBchuN^iz&&#ZEjgO_q<<)xDhOH_hj3NXpoy(p7%-9-g7tS38+T7`Hq9T%DBsMOb7my9N^{KhF>KfHDP2 zFy$JTu4$R}Y`RYkj*nyM?%3ui^dTL_(uP6zX8!wzLhl?NY-GX;FIxd2bk^Ehf`d-e z3L)NQe@r{(D?aph2{8H0b&eP7k)n61-_pq*?xBn$&ohS7Kq+zTk{?wYEc;kSXmYsA8>v&5U%ZI)oJXtMu;8gOq zf`}!riQ96o0`hTNICK9;u;u~fK9m;65iZhJRj?p+LQ6@k?%}6B=|6#2B3=WU{I}{U z_&VdYEXnYJC_?ZNSnq-%-)aXn{KnzTVGIJ6gZPGYC;AJY$ z8PoFUm}@g5nZ;}4E*f|<4CVfs*$QRvDcGKT7v!grC{+E;upi8^gBC4b-8Zqu_GFV& zieA0az)uG^&FgZ{-ZLv5&b6f`e4ircLoxHX1pbn#Vo#QVZSuEHe?DLjs(}}>;vGs z0MH`l8TLczic3V{xQ!v7hhUobUG@2|;x}IAT9E)NO4ui;H2E8ai!h))0eb_#fhrxw z^*43@;1qOkX!!c{XijWhOL?e~T1jOaGi}~DkIKyRsP?edj1;8vA@Dv zvjCQYHFE@l?If3TXFz@%zrNO}4-HJX8P0GmXq0BRI0}Hl!NX#TT?J@cX6h1jv}Ou6 z(5sWV65hnd6SyAWszG8=E2G%1rTf^kXhqYy!TPdGEP=8z{oH4%# zJpM7|9#F8GpL4OUYqCdnobJY2O8R+I?ArV3-rc${hx8=jDAS3VF6kQ2m@0Y+mdw*E znTRFM6m8=3692_K;`fe`)+<~&Dujp2L+b6vJ807;9gPRg5;9gDqf#eC*c>N{=LwMu zt)J!A>=75=Tg}8=f0g#L;ZMYCMz`+p_L&QRq=yoVpNHar>x?^5nyWW=tLhO9-NVxs zNUlE!m0NUO;`)y&qItzykV&79O)CGPkb$3?>=km}R7R^(n0jVWoqS|PjyKjE|CLaT z&FaiVAqD9zI)d%shWrbEY#v*l^{C#XU@y0w0iz3vgML-|V>*uwg{{7|E|Fc|FaZBX*(d*C3UjmGlDwY7bRU6<`a{=s2Ba9KC+v8{1W%v@g5Ss527sQz-xp?gidDiaz zTX*v(2G~i6HFk2E;1nfl{@o@@K4$Sfetz|us!zKjP#pFExfwc#F3vdG*bsvzHox9H zH&0n!@Q5$lLdbiH03rrtM(Z?kSxY1`J@AIah7~G8xR_mgcv5lCDT|j+K!VI4MXUy= z%@7B`0{>BYs{4iGV`nnt>jOL-x&Nc8d{`13=Opx@UxjSwuk7;)kP*Z2)!EFPR2WIHl6%OC7Ks&W+FP4Ov6r5*ZYskCKORh z*5L~MM{*)m0N?T1rd@m_AqGyFZUZ9{FHSx3Cu$eP(OUy<#MEoLqOsg2@7LC~PhV)`1M24{%=2|_pQL(zY6+f1#u%CLBY9tZ*r7JR$p5lr=|^7{ zTy_Lz?sl;O0zWEnua$+e6ALj%BzjbMaTm zxuKktDe#|}7|P9nftQ?Wtx+*DUVB&G@BbaEyi*gVB0`&E|K(7UZV&p0IPmrU#Dgka z)V=|cIY1fzj9}v6w}yzWzd&_s+Mb)uKbbIB>MQ;T?JJPGn)L_0Zltf&%^Y@m-fH!+ zwTZ&+$*Uh18Oi1FCODFoi~6wM`_p+W)j^9XHf1&H)1Jvo9PIO{rckFgU4yw&GRm{N z>FW1NB!TBRlh(Km`BCzLt?u5v4^=4ck;`G>ZXS!_4Jtq%LL!J0*6|2t2WJeZ_ljW* zS@n?U%B=rtSLABzS2N^szv`Jbv^Egr`%i+wuY#@qpJM4cCj>Yq9q)giFFkfBdyd=?X)__2Lhv66DB}NYAs!TAPm7~8o~#N+Eoor) z-fR7O<*MYk{YIO-nXZwxFQIMmYd`(Hd;9KqT7)}v9k|?GCMe>(Rsg^ug%$dc(1&ws z0~#qT!#2<=YhH5njt%#eGd$iYorj-A^Y>qqywnG;1}TL0)n#C~teDDnEB?IkijU1^EZ82#Na+)-hILEn8xh9*IipYYtph(> z8K7o84g{u>Qrus&$`5U{e7AqP_J_OprPBN4qAX7tF7j0cBcV~nfCH%bA z2NFQs8N#2v7SD9gLsTmz9ugq1wPvCRb$ipx26WxPLGarw-_dTafxd8bO`~%yNuHcB zVT4PHZV_Cg{#Oz4dpHrrl)u%w-9}4bSq=%dooP|ks5Ve+-mkrEP*|VX_-ol;unH5o zUuzf*;Xq%9E;=AVTvOHt_JO+J+((M_Hes(BAGp9c{8}BJVL3@+ZFk3Od5L5Wp)J!hR> z)sPkDs5YABQM=}+Xiei+4@2h|Mten!zus~GzD%9IW#Ik$*)G1Uia^F`tqRoOtWj2o zF7S;4qaCZs7|C6_eS@7(wAAE^M$krE1^GKg7RrtF>XZR+U4$zClDYaS&BCEyE?+r< ztGMj$NY9y47h_)EcdO=+;PaV0KkHf2#46>jilna`M#BD(H2PzFTqMqud}=qPLp_R# z&DIrxQba4wy-kCqv|&uM?)~fB%L2hKjM%5@rn3X^Gxyd<=uaLq&5(|gfYc1%H5x0)dXU?Ng?;yJz;+Vk^^bzJvFEpAo1B`VgE1|rk`vwIK z^M2GV7lGb53&Co$43}c4?2Nm|XM{`Is(K7}4|{{Q>>u-s+sj>EDR!6?(j38=U;SnB z2`TB9P+g1@rq*fFF3A-Oo|i+r<<1>h*gHx%mpqg>04v=e0FpBk+~dG@^y~R^K=?b6kSn!6yBG zT-%tkLIigPfz4YQ5eL@7X2PeV-|`d`@>97S*Ro zHnind}}phJ7*dGT#h>S9Z&V2?qF2s1bCOJ5qz9Q8l;N)m&r6DNu3))J<)&0SVa=$;vxElREU|`X8-=E(mPs6Yw z4i>ltt`*#e6j4T+y5Uj(upi*7>1iTwaz?L2ysG)^kAwoKZl3e{Lkb;C;psEjwNujv zk5Z%t7zBy9>HH|@?c%K04jC_ddNeNPtBRCCc*SfHgJ!{BV0sP6Dl;!Z@F~tYx>g%Y zo`zrlVWm2N;td(R;NY7X$pz9qum6V$#v3YRO){E31PD_2w+Sa4E6or!9T=^3@XJ6lta63^%P#ndD zzNUHqDpVc^)I|+peO4P{4qCj6c4n3sroH(3BrGJ~Tel=kk?QFl{zv5<;fM9-Ta{zz zuT-pjJGrQtQ!H(lKG9|T^02-KwMQggC5aPQRwoHDWjkjeb(|)g6gU*ZqjR;)fo!jn zArH8eX(heq*{g`pD5xgzzU*o%eGgAV+@Xd#EblS4TclRv_8cOhqraM6RrL&B-xW|3 zQ`)6)Ec2%EHb-NSWto7x96<0JZ*HC@KhIr;?QH@C2)!NrdW&~?K&5_fSHL9Xz39Xw zLxX}Vta|hFDFQ8r#3#2-I(e8stL4DW20HY~>F_>I@fzMM5sNqPYf~*H7se0XH8wJJ z`D-a5;^&q#^^7N#=Us|dYVnysAx^o61H%Mms|Y~vj9Z_K-;xi>yp-_QCy`%b_@w@(4iwL%}(=$9C4sed()i28BEj+2%07MBh!@-&I$WH+YYLX8`+qU+4%aP z85m1IgGOhi;GBt3g6cg>KexuAu)fyhOfR!?=sg!8z)&-BGGIC`OhA>P^7ScgO9YBIjy|_^rUAaEk+OC31bi-oBld&QM@C#IB85q4KuCL1Gc} zDo@gl3Vs$$q}H{@4jjSC45m^LPkauzSB_4GlmK|z)6r`V$pQSkS${vDAB7Yuzs63T z)!xT68C$!Y3({Lsj_mWE_N}oW(*Oo@@ohwH$XS?Q+z5;Q%D~8FOx7%rqg(QQui=R! zuh06h?rS2NAtq_|IZV~RQ%^`EYF1kz@1+k8ZfXn)lJhW2Z9s82*lChnMiF$$q4T-{ z>s0p7cNL;6t*;)hdM(yIuZ%TqdyTorcoyNaPUu^y8n`*N$Cv&rWzD>6iu@HA6o}01 zT6u_g#EO8vlvG|Uq~?HY_Ki=qHgys(Nkjw389~zd^AanTBrxgt1-oQhP@a!Fk~lnS ziR6w@waq{84d3d5W#-MDxxCIb?fz`=Zc6gjYU6b_<+-S@{g2~ zR=H2$VuTprd1PQ^VxUgtgshdbE={d=v`+LL7cbx5eahI4V_N3~=4|GJBi)xFgpmOh zdm&GpaQARpvVqJo`?s;vhP@G@FjR(|3YGu;Hs^YC%hX|APr~7$m!8*mWb?q|$8;s( zJ|27x;DDL2U9KnSe1R$KT%zil?EA`#bi*fh+g`Wd^{Z6I>2u!ilkC;$W4R@0b-~1I z-lN@_qEWZ<_TQH@qYc?N^AnOT7EzynvjPQnt;psHot_!nV+|jC96`qex3)}yV{;BI z)cAss?HCu@jeVsfT5S`FuV2Iqa<3GH<6R8r<~uaUVc*>Dx8hGmYkgBVLSM{ zw)FTPX;9NGTj}UrucPr=)7EpGYMGSfG62)u+x8+Fkd*%rf=k_G@{o2Vs1ojESqbH| zWKk;6u$#l0%w9A081T$@@(ZpQ##J7?2nfBaon6{PgMOXH)dH7iJo?fOZ9gr|;nvR# z=}mZ3-Ym!oIKZ!T%(Uo;<`$Do37Cq2V&sKQ^y@#Vcf_mUSa_C3Y!siPOb}V4cGN>5 z%T1k894v$~Y)G75k|oJ@DqT9KyFaO!{crKW)T(V9cv-XzR0|C@Y7#2pE1f-l!RJ+x zM@A1o8F27@%FP78fF0c$6edxYG<$WNdlgue3HD0UQ9$CZ*<`L!&W?&f zQ~0{%+md+8win@qrj%FTWNinonlPkyO%M}`d3Qo=>Z^NGx}q*yJU|)}Q z;tYzz&4iAUYK7pM4xC%>9u7hm)9-| zTTRqWtbln4?;pGI+uo7Zh*T#vvb?fhR|#0S?1uCtX|FXL#T5k(}}(-&zBj-n9=B8*ntOj4&a+V6pj=XQr*NjsLMV zcpQOztOd8JRjlDc|9IsQ+N?S)+XrZsKOwdp<|g z0();TCzO-9TP9KsFakAF`ZKFV=jsn+`*@?Y5=pTH44|2W1uyiu2z&?POm*zz&jOOi zRWeLK9|N;wft)J*(-0xV{x{Lj2vrn?Ubj4(atWp}(6`CUt zsrp35K3#yK^7>~=C_|VUfh4T536O3otms>XaqSqlqzBbD|BB@ewd~=lVI^DC_z=t! zm;~^Otz@QXLZ5_M`8UbpL*j3aLCR88i!d8yj+>q|6?!ZaJ#TH_m}i_N8dci=J2 zqGr=N#dS4HK*mO0v~$*QO7XWDJnWF+m;^6^|*3fZ=xq(A<*(z-{`cEf_N zPK@a8qu)iz2`8ru$F0skR2d)NKV%Sgz-`){pd1-x{OiSo|A}^9x<~-d+pxbkD6?ta-_Oo31d2ZX zN97Ye4<;Odc_K6POG9{Mh(zIa2u;|J76dmV6Uy%6e%Pb8)PxeCLF6t~ zaoPTz)3uwIwgj0u&=6L%mO_QsFm(ygZ;!$1A(-pnonSu9;;W4PQ%3jBo48sn&sf-D z1*Y(WQEJ{j8R5vv8r@vqdFVatXO2VnGiH(c&?i#8q_>8jDO8Tgo;`KOjkZ4TYnq}f z#l7dsDJ!aVlYm6T(8BH_`_%nkz(3XD<4M%J5+#R@3+VoXoT^5 z1mYz;dR9J4GdHZ|``dC_QA(i5c;L_eP9$?wD1FR8xBJJOVm~m29TQF`s5bkwHMS0d z9|ngyfcN%f>@%=B5p4hJ>gEzZ*O{esfLNP4m#prl{2csVv6kroQq&A#Xv>S7PuF@F z%0=L@NENN8c7Akc+Z3^46~LZ9i({=4V9qe&JH8Jf=BV@51GMXf1(`@!1}kHW1v|&5 z^pmJa>ekVD!R*%{tE}%N0yeqhf}Uf9#nNAoPXQTO!%L-fqs0R|r+IeRnU$J_2Psc~ zFWJip4Vz0BzdIZXB($sv8pr1;=WV_I!)0aqZKbh?fWfO0G}pX%c5*;74lS>=Ol51^ zOp!td@$Ofc3w_q`5(Gi+g|C=P`|qbnr?HW&iq=_ExicBgv5k0UT0@#As5DxUyqmdI z=^eB;^9zYGu#-md>tOrCPaJ!%q~N-TS&b4yrdZ&F-3S`!rU+32$ldAWc(C(s+A&1G zQEDNs6xNdivmcowKrwUvs@q@vL}A&kWy?+glF$x-zve=3^IWFl zxvyJ&$GLW_nt+9qsjo3)Jd{X`_P* zje?j0U?$j^sM~MLJ*Ah{1uPkAK+E81b$=W4srBK6!>5GA+iQFy%1EN5`-GKyx&M2Y z3&(M8TLt^zug^HtUY|dH3OKHbgyB5GjN~Ur$DBCzqqo^)lJOZ}lyqU*=8lRsH41>hIr_ohpJeaTj-pQD{P>85s<4d1)^2%pBU zQAaAPWEbZ45ax$Hx-hkzcG-=`OJ{nBc=G=-# z`3GC(-P+03w7z7TZ}CMmdB1my-x`-56&NqdLPR9tlBVvNYI)J!BBeL}jE$y#{U!*= z$u+*uIG7qwhJ5v}rlV)HF&141k>sdn&yI4lRV=qr2j9*%sw@~pcRKcWy-Ld5^0}41 zG#h%G@bcfgcGS0TZPEdJJ6*ffWc>Qdm6b}k)%F4X`B>?x=Z)M#~WJ<6HSnk!Okt8rLBG z*<*2C_JQ?khqNw1P-UUFdNn0$*IK0!e*@^5^%70k_1}z)9IGXlzG}S6e(`BF;wF{( z@h+g5w~GGH<@1b^mb&uN(${9?2L`%mh6mr$|dt z*r9GbLqkXN+dTWlbNm*L2M#?F__9u8eR8R{`%z5~=X0#I0 z7{~^>(dsju{)b%WVOSV7q+bjrq3hlz74VDpA1h*>J5EOH?=?!@1?Oi(XW5a)f$);p z_rmf+>O~=rSUKwZo1O<5MTK2edMRDqcj6-%m~X+gAQLnlxg`(=*z#`}2Z?_r3&IdE z)7hk)Xjg^49lS+qynGiWqQyYmhtrXP#f~R)j9~3zfdK!MLMs?peblDDi8GiO-8;U? z()iEQ(6-$?+mMz^KXYR^-xbx3P_c20&>)(dF9Sa7C{$DbmH=0s+rYWb!Ro_g)Oagf zc0W4T5vl>q^Zub@OQN`guPeDX1Ku0ZKWp|2&YE+KFEAt9kP6$}KftBPrBMEr+;Cu= ztpi|zbZ?SpwCLHMZ;I;JCBGE`IkaIDD{#4Z*u*L!;g_X>f5E`b_qiY?j(xuH$|rv2 zm^xS-MT2CDHOuy+9jlG@@d|YFoKIVEq#3-UY%Gplfu31aj|!Q53RMVuhi=7HN*j% zJjk4w0k#4Yt)QuP+~3$BdNq5|F%}X;7(oFu0*E0%czGQ=Q}=SBI+j|I|&LZ1&d3zr@c_QjpcC2&k#Y z3eb3KP~?`WAw=sa7g)8RLt@G}|L`Y&|0e8FF4l15dVoww=t?Gn_XN&T01F6An z@qIJKFw3O=_EN~V#1M(&nl41O*Iwx=vj9nd>f|u4fg`e07!;rK)YdIHVk=o+Y~-#n zmCcQIv+;#!D9ya!RgK#Y*j>EQRBdidsHAcbxu5=YQc)cvYpdk7P!0-Q2&ZB&-(rpj zNpH8^Ab_1#4LDYTY!l#tPwZKg7Vesn(^e`G58NF8^}N@252l_g2y=s>i@TPtO|~cl z2&b#vD`Y-bx@ru{v&S?5^B%P!J3maL*iIQw-(AH3-rSQud1m~R`VG^$<3F3RJ+wFH zogvtD#WL`p6JYF917@umXyDp)(v#oh zObNHQqV;u)NlH$bMjXa8&%nVdmg&~`Vl!SL2U!{MMIcF z$JMlJ_N4>MbYSC>95zY<;zDn>S^O_P+>t*ce~maH#7Jqrc|i#}d{ z!S2Ir+iKTJT?)3<)Vja$1G^kq#$iTR%J594b~JU%<(s@{XNZ!tv{~A!7yGx_NjN3pZ-tT2?4wE z>E(B7m+xe5Wb;K`Kf4hL`uG>V7u4B5R?9E0iXRlN{bV%qD#xN5c0ZtNUx)GkhW%_9 zc_=Mef1k2vU}*%^k+76W^Gs9tK62GMqvBP$$G;Z?Eay=dGDg7HS8**su~H8Hi!_`l z0@>TW*b0RQgq)ONuD|8PQ7ahF^%z+nUP?R_sn50JM~mM}DDW(97HIPpXDZ^Qd=g54Pxi_9yi zQ6f+5hFaMFr_=C%3k?51KbQwc2ogR$h^ojI_|&PvU74AEs{g2Nxt%NhWFA8hMB!1A zr-pH$+cVOm@^3F5M~Z5)>Mn@FZn>SLm`y_;&9GYSFck`^m>Er)ZwFrc4$C$aw=3`aAHzJbyohCiI1N;N|w{yN~#Dg4;{iZY$6RAC?jX!8s&ZPvL)1edHw zb-4~9>&HS)?gDEHdGu1+i*xBAAtk$<6RtdkgAEPoGEKT~KBVdLojJSL2v&Gn28eYx zeZwndh9>y?fr>h$%((bTn+^%3pZf3>#&VvhDZx6!z3SZRw6Dvrc&%{?YUv3YrbU_? zHHF&I&(n|LX`edm{h@t-*SxjokARIJgI|L4GhAp?g>-~WtfYqQ`^<0Xpq}BRE7Ag5 zw;y~cqQPiL-S$lS9V$gZ%aWd9Y2sUGJPLPs45Fgzu2=5u3+&li%^?M7W2hsX7LZ_> z3g{sYyuyEo9HAkIbz3b}c=?wGpr;KUy6;j(kQ` z!NZ`Y*k3Y9kQ<=;E`rP?W$!Xui`k-L=Zyth)Z1C)85IvG}#v-8~+SKh|7~<9(vDq`yjK(m)fA)Lh=lW_0K+Ldvoi5Bx!?M)3gWYn#)qty21ifx-++m-F%E zKItu${brSOx1Ydw-rHtmZP9-HsO*CEz zzs^AI@e0{$EE?*(Ew-n>hKQgrlH)>Ica+<1*G$yT4+NA$cQeNCsMSp#aaVk@2M6NA zg??QHlSIv?8 z*=1}`et`@L=>o;UM0u!aOTFwvfh4bzz>-b2KbaQ~l5csIo|GWo7_two81gp6dPq~r z&2dR{31(9>+z|i%%P*80Cz?;w1!vn8CD*&(|JU$hQGy#kt?QLu+PCdRBAC?BSZri z_zIlMk{~|ZLwjf1Q>G|}b?v$34Sm-bnE~N`z27JE1Do+YR&V~zqSn68?ZCP>uFC+pjc^3e|J%j$Y<)-K*(exnX%!UE1Hw57xcBzdf7-C7ba z=B-&;rh>rRNcBUx;0nai@Ku&0l6Pi7W&FCjz(bs}0nqpkrXrYk16?apwOo7g^~YOm zfsqGy7E^AeJ0EIv(*6TR)Zi`w8Ni`vKzvHjhhQlwUikqEE|(OqUwQsXT57+5nF#oV zKaJo_-`>@&S@sgJ4KR6u3oQ#=cDv`hf7xa;;-k%F1ofHL-Z(?N=n@?*L4LRCwp7VZnCD+;*Fso9(Uo@W+2SE^KoK zWBsmsd|$YKTO@usu2rsJ?dyn@TEvO!A)0L&^NDg}mSBZMQf^UZW-5QC6J1%nuWWn0 zD{!|U?N#>&wbMkELqpF!$)$#tC><9k7#DE zA27nc+W;es$p2b@=H&`0eKh})`e6hK8w2J~AVJj4fCxYOHg8P7Em&^@nEkWPTgJd+Rx@_D>;OvwLf~>Sn7E?>^MkqhZEi*qf_v@)SsBdo!i{<14Yvv7v?AReiC*fK1bzAI9#&^v?`~H)EpY46lwIGX`wdNe-9`|#Hswa@M ze(G;l$n1twQ%ye;OYaH#NzlsWSV)X4;WJg?CMF#I3ZUWH=jMp-Ic<~YV@Hmn7Vkf6 z8Ek80vRK)eU1P=)gVf;UBGuzjU2S+o@LH%wu-Dxxz#3dQ30zQB2JMfZ6! z*xBKK5`0;%`B*#LSx0h#7w;buR7$-V%~oy3*op>FRPIGGVVM0F7KVMp%X26UK1|*E zSIOWrAKmraBflAh{SE+J%)rTj5V6muCKY7yd~k&=v&8)#9^jI#1PNNNX5|v74cd6? zOE1_Tu5Re)$loN7hZ^>IThlbv|Hq_mw6<;P`-#lxByMFdpeT-46@PH6>~rj75mnqO z)??m&LPN{VE-Kq(HPTCvj>=I~t`_PF73%*~Kh4d{TrR(RL9iyuA}w6IZ-pM}!lljK zw>%B%FjYHfPn9^e6?xOcIo?KEQa<9i5VLY0b4v~%T(=wB4Mkdl4B{{jY<{ss<3v2d z^#Qhcg@#*|bVBj*EZG-l2q9jvRR>xF1*80J*H?sh=ec#z{%w3C zJjeYrWE_1f`(_)M``Ao#ztR|Td#<6_z*6vyi{YDzuYVHyshdr=*pIt(w8f2+`M@_7 zqUnXlJ#Pt=kH(E}v~|7x%OxJQk~7l-PUV4$#x8r(itUAzgymF!dM9iD%1_`iIdOYs zSH|&oOsh(z*zem-uCmyHuq&{_*M>P2Y6~?=Iru^MiDdE8t{a6CrAdGF4wJ8y7ol_Z zU-fgXo3Iy%MCE-J-}y}3rORRrT+(Px(V$70l)hWK!O!g(U`IQKu+Uybz9JLV0BKr0=#fwZ1 zuy4=J1DmlvBJQ1hH!8EBuA~t}C+-)}l@<4@FHI`{^`Yf)r$f1G?gzIql8mw^#~D7` z`Q_1s=~c{72LIO&vIa!Wy9O0NVPUFdXLXLq$Iy{Go&=_QplIV(@%(`KD$>L4d5y|& zsbIr{$dVW}^|ybVa{K28q<4k{OyMuKL4z4q;7^8f%2v0Hgro%fSG3M^k3Sx~HR8Tu z$vS}z4Uur7zgS&+UH`==C)P3S^L6)3ZhgSvv>7B12=5gDP@>$+4v)!gVABM*ol?U~ z*iYB}NgEwLur*$!#j3{`2k>hqmOf}I#wv9yEoddNBa7v3FQ??v*ks$g^6N8=-d%!x zH)%fAR;$?1Zd>^Uu{#qzLEgwb#!JD*49iYF}@&oAhgiy56pd3D$&q zkT;FV9n%}+8Cbj@%MI(8!PiRj^RqoW#F0VQ(g&S2PyQ54hF=aeAR)6n`teF?zgpa_ zHE^gEx+ppSB8Oya&WXQOb5M0{eVXrH?n6FvvlzQ&O@qGY(0fMKJ-@f4{X16{Xl5^m zMI!OGIKBl{Rk!l-|-9+6) z25N*ID2#@0&q+_)aGRzo^uoaQGE)vg%$F(sUYahN1PA!b?;ujcyMGjhyCu6^1E9*K zXxiMo3GwzA-$&`dxIJql^WXDT`}C&Sg){-sH<5l+iH*XuT;BH@37kxY%n18v8rT;F zp6V*w5OQxn_j=N|eZ~w=EUZV+FSTX#=O^rgKKG>>!Ay1?m0BNg-6R}ryu?cE%U zZW-HDE_D#3!33%C&>@TO11<;ZIw(EvYrTnFDtSP4ZEv#Z5}Mb- zs{Lx^SFB$ckP8I4OXKg6+~t+kxrGu5Wyk6|i~<5{?!?3u97mKbXQr9-r6V(Q?mr4) zvk`JJfLDvWnz+pHTC&Yp?cM|~bML9nQ!;NkE#>{|vU+RCT}wONrM3^y z;QYy7)BwH(V@$C*lGDf+Bz8}8lZihNc64`hI~Bac|HktYJM4JK9>QX|V|UuHIkldz z7krqPCni6y4$2xOScceE#%owV2o*hu$~x?x-^3(h<{}3FVt}c`-T`(Ev{mm-pm|>z zOSt0-N!yx z{lnr{b`iHrkxO01rT9JBCf)LwIb0ihhk;D(H#Lma>oI1IOBpaPvn)6m7QI9fLmef2s~J1RTRbgG(7o>eVQrlMwjM9a6H@q?S}#-N9cLge*} zn#jPepsqsmYsZ|?e1eP9ii|xeVnYJV$A+GR@Hw>LcjSWvZR(z@O?JSvYgK4FU8rB>Hs>>3X=09}Yd#X6 z%zU$!6H=hpY#qWRQKXd=-^iYSy;@R%1MW>Q!39z;tso-)dd_6s$o;~ih?K7%BFt@a z2>zbKPZF+Bby-O*&k|zyGx;Zk2g5>cF8mDH;(h6+ai(a~Ob{CSnd{ z>1==I9+d9-N<*+fs8ON4#mgtP@K&l>wYt-CU44D3)9Pp1m;;xB2pT5-F-B|=q7B$B z*s8-{k(txFOn9i}l3KK+b+X`@@Buf}z6UzHui%}lrfx)YbiRGAS3t_5EY>!Y1{U^b zPjbx1);#TS|GvwgfK=5rzJCU}CM9-1u%cO0*YMi!h#HCH} zUcCmN+j#KLnJp#&zc+rGi%mc6@Z?-=_Whb$zF9lY`uB$&TgqT{R{5-8`QqQeyavQ=hw#g+ zitKN9?O1*`#RqX^%zp!buzb`np7%3KB5b;1mdA4+B#bkaflY+Z*w5sOa7LcXY*Cer z>cp`~hYxhFJkmvz0xs41DriT3(2=_7PcE9_QfVZ4&!wnapf z-1x)@qlxg>$=+adex7Sa*%dLfcoreI&N_DdR<%~AW|0rBQFh%i6tK0jVQ z1L2M1`tv*>&6*~-?X;h7-v0zGDAK;_nm!ca++*P&qzA{Ibz-g&dfJl}WU;6)CkYP9 zF<;~X_18F6?tX=%X31D{0>&69OXZM%FM@Ei4FZr|^QyaL8WJ?Js{Td_T@jV&Is+gT zNtrrfwVdJmyOw)>Ib5+Va*x(T?)VTpSP{{14xfgY*rJzw)pb#%3e|~GXSgRCRY+}6 zuruuOAv2rR;ht_=-Gxc#;uGNa1jDajy}Kp|f@pI3}5ZLBS{YH z4WjNO9=9A#ZdoxNavH5Nr8w4FP=mlHXfRGKvPy)~fx#!Vt9CDcXL6kispM69kVuM5 zokE8V=7#?8<`)!cy3D8UXO~IX4u?Nq9lk^8QICXRlX5u=^M}7BD9u=&adub0ZEyx{ z;5%<>QQb1g9o#%PDQaP{o?H@5{$u*M>lnWa75Kg&;t+5r>9CVYF#opGfsw}=D4ky@ zjMQW&jZUcs1GAKVBXAW^a7@+ISp_D!<^F*B`P>)N690NimDDW>!KZR;>+|cKtM;#R znV-yV{h7ot$g%w*d^qbu>gICn$D{{u*~e%)-6&Hl@s(;9nT=iX?hXhfwzoXUwDd23dvP{y!?d2+MKpJ0mONQ_$KkG1GvP54G-uV#6F!dZUAXO__H_TKDHWa6 zwfW+gC$FZTS(!|0s@n2}zl%Owa5UAsu^^DGRNuuz-F7qq^Sy4C8M>;9rfi7G*YVH^&IllHN2~3L%&nM5bGGLOz`I^ zM7L%_-^P)xyIVrghcIe^hSXb)M76)T^Bu=D7h;7I9 zJy^PGh<4@C)Zfu3ZNC|hME0EuW_ALp9r)u6x$j&;_l{x9m78u$s}C?`0~kuU!>Yqy z&qtgks}D+oyPBK+Y&<%;_-3)ehcODtu)}Bj6kN}8y6y_uj151IAC$I5=(rqd-70ni z(`&`v*!`?4#=`Eo4Luhnl#%T^5qIm|))!h#Ptl`r9`X%X+`20#4h%3vib2s#t(bJl8?-WchZpjeM|C~5xzf}{ zRDp#;%2gdolVDEg(99Ezt!9iJs8e-WUs2~KGk%62W< z^)^o&2vMt#Tj$A4OF^E3XO$)GISoG) z4-n$kQPwt0>QiAkmsD*tr9EReMsG_lw+Qw53`(?52vU-@`Ax3jCU)2D-uv)o0|)TugrkK=$8z~)?^@j&^JtK- z8Dt@VVW3+_4DW~Qhb!S=p>`8Z^4?Bz^p+MKo7GL{%VcFxbYMPQ0ax30$VqwyV0b4cEAs%nwkP8P1lxf7H%aUq=%E# zN=O_)OdMP8P2u02INDR+?d$N1@+b`daRjhTG(J5Rl^C4m?7B& z`mN2Ym4VOZcg_&^n+#lY6^LdMG+(0kj?>BY1-n$T%Z)zHO^_cJmfy;C5Fcao{wom( zf=p4i*p<~*)K?}9RwUhQ%EhaRMn7#y$z8^oKqj6w;nQN{E z^-$_)88N?LDiWH^WoHn^3qiI|AJ2X!RV?6W2@vuvn`L{C7jTx<@Ag4U%>z#DlQx=|DTK`fZKKB zjKsJF#`dtr$RIxM_yY2)SF^u>A4*ci+RSN^dyypdOu)9@>(zsmUz^V0RH z-T4;UYN#(PyZ*xg<3+@!R%o&$XatpjquJ=X$Z@xRh+OSx_nTE4Yc$i~@(*-lhbddVP-7P`VWG*QB{9|EV@yvxyqDxr258iQOc2 zb<0KVgt^ei?UBdvOt1E*;113OL0$5+WSXmUKjz*VXEj-&?jJ=pWEfy966Y1vj_rVM zDP8iwWsb;ywH8iDr}$+A)1P@10?QajWbVRF?saC$)Z(hUazkob?oZfaH#W1~lJKu~ zGhe?vjwI!8yfe8RTXF`EmvSJm$)Sh^AZ#g6!n|rKwTI+Oxbc(3gbnSubR6#SgG3#Y z9PC_u-I?Os?LWd3Sc^Y=BxB3HSlW+5zdVCxU#4Mf>DWpBqty^rh_#uI$jV}Louh)_ zB&e^V+8(Q^%CdHBdGM;^g;mE>>Q{llnTAIT!Gy4hwrOjj99Iw`3E%?LaC)ugMm;ky zPp2p5eAUUZr+=j1F~{}VjDs2n;gHwNE>a%SB0nci@T1FShfJG%pUsp7f7dzbvwflN zp_;@LL|d%(bV9BWRs$Gxae7}#Mr&;Hk|Nav{r2JCtnW8lEql0_+@$+qZQTm5t>Q8g zq<<;xgT5_c4biM!Yq7H+y>U!AqSD#vMDQ_xgYk!u3l-r_^~&zfMVnzrGF7hYKZ=U8 z{h3v|nd}vG7@5UB^ZKaVe{xz+OV4U4)el_7l^E`)N%ho({fs|2Yd{A!N5H zJjHrX(?y6Eo+M4YB^ouk|A0vEaydzG8sFbmGU**KIDraYRC-)2XYW;t@Hx4~w zday;@WzHxWEtPzZY>w>^iB%BAdB?WUk-#`uWbsN>bxX@+no3L`W5_HUOj>0e7E|Hd zrinV(Yyz*)b=`(817%te9o+EG!-xR2j;VJCk8{{;ynxhHnBo^G&&L2GTqXVs0Yx++ zJ)DGlOm#m6^lh1t88%IpBZtGJ6fGPOg=>^9^I#v#Dm zA@9@9g;Q{Ubx}&b=_JjnwlhXFla4#rf&QcMWflw|HBf0-6`RWw{GcoYmdYURX5*dLZE^VXk`i*IeiS*lA)}1HWQjsAA=oy zs2^LajoXMgQlI4Vy{bwNUc4TsACa6Ij02IWr%HV6@OG7z6AB7eW&}Z zGK=$XuaDf!W1za+d_J_QvD%VL2*O@#52U(`K81ZoQF`crjK&U0(!Oq| zqLxIRrSy{Q`$dai7!8d?Xiimv&%1ZapB7jn2N~mOi9%c|-7&Mz>mqs2kk4gJUQp1UadU7a0zfXBM8MpCP z|4tgH5_*_SGo$pjrMf?G2x;;)c{L<-4IE)EF;s|M>tMzw5F*sy`o0TUR19 zN@dZfzWSdJ1A84YY?u!iHlMUk#C;49fo0~fhuxf=IP|Qk)Z)UQ4UDMcRCk)MYtmtZ zrXq;7dY3VQ^l){8w?lyip@F&+*jpF_xi`J8*Y#5sV&cs zJ1|&1NDS+6l(-XQjk!~V4r(rxu(>-lrxa~&7%O|zjd?RrieW6X`UKqtn{i*}Ovr7i zhhm9ZbviOPB4{iG4Zp0|djF#^y%lhPkyLX`m3^42IY2f8wz06=4w?4|JFACu_GIxX=jl6}UN}Ess!m0-_@*$leqwwh>MErQs>e z9ipOYG#wq%f50Ly@Z*<&IcGi^PIH+{W(F9Op|n*L!_1B!UG)A6N^5MZPKrYL*)erb zB3IklXQ$BgsbKg=f)Gw?CG~$Eg%!IpAAVfTO(fm1rc|MN9^Gczsdh%@lG^JOHLR!8Lk%8F<@mcNY94ido3*;l0W$OnA<9Tn}H) zh@&@%6{ecI0s!n&uIA0f)GMY!pFBInlg_*~xPulTAs}-sD;2|q74Y(O{U9<;>~Oxx zdswYRb=mxkoOqJn!aK2F&8x9$a0TqcnE@pYtW9Dj<;)QS!*dmBmztcRn{*^be}i!t zTz=VDjk4Er{tE?JGRl)AH~@aP7vQc&&``+DhI~SXWDEYLq5GaPVFJoUAbe!TE20FC z5NTlAwGU&+6NL^ddP< z^(Ot=(#Aey+^mzKT^1E@JLcF>zP5yY85wQ>Ox+7ULwNItu6bSbcs~GL+(YlkVCcct zVXqYxRVaMyx-B^V>@=jCf5%tMsVjA`C2A;N%UEmnv7~c%Ic(T`e|_uLy2&|aO<1z} zDgM=0yw(xeX{F(A5@e8feq_dFdd~g1!a=~cy>l2{a~j7?G(yUt=Uv|4yoK1juTOe@ zJV?TVkor_v67~T<#^1f8D}}=LEzRM(Fl7w^sKxz*!Qt<7vuZt_@94HP=w_WVW`s8q z--BG!9(tDUn&ru^HCA%Rr;T=H%l1W$$qJ}azq7Ev;ujBP(3`9Zuo$pnhD7SWd|?~1 z!gn+*@0HZ$SA|QB+8(MFJSyp}e({^nf!f*TRivO3XR(f%R(Q^}ry4z$Qz6GuI@NK1 zcG{=PDQDK5GNI(_qs@uqkr|_OE}aJXvE7CQi#J=k@;6tAhCI;+8mBh;oyoUjh0WZ_ z#D5ggG-6$ad}(~I@=nWk0e#4%QZe#O!B+CCd!ln%{Kz$$ z>aeY99oi-OqHaw)AxFauY5RbCcac^KGs2d|!*>^{-1jWu%Dqx|&!Y%|VvyMs%>y5M zO_&8Y7P%u(p{`e@8M+~aDzTR{FAvjT*ImBgoY)@C(2VKr_0RoFUEfhi-YM{m{xJ1l z8EaA_f->2u^;kI1^gdbGxN$my$3*WPT*++25-@K+x*@7JCJrZPbqxP@@ap`#r z!+5GkE3`GHraEH_!a*jAO)(m1kjXf=$2Dlq=rz*rN|2GUEL@`)d@V5(LKd#ikebIk zx_mH2^WS(U-RVm2ET>n@MDd1teeE9wC~sa3>a~HE7_>INC7Jpm;RR54WE~uZS!8;= zun~;bwGhPYm781KbgJZ0c-Ugp+J1gSi}Vg=qfd**&KMI^!%TBi)0{4q9PtNIh*E_YRzXo_?bT>ZXON>D_ff66r%RmqK ztyr<;f(Vb2sOYg8bF2NVIou(|F6<6d zJt~I4`-qz~gWKZIPncT&QE5VoMQ&j8Vm%tA7T_hnEyAymJ#Br=+oXz3n7>FfJ1BcU z0S#e(0cEdkq2-n}63I8ic~c)QKiW~GDaf!$4J;z0&KIZM(Ie8zV);^1;2UbV4={N5a0AG;( z_(mC`T_R5vO~bOtPiBxy0hMS`g`5D1qBJQRb%w;xn>MwlB?|c(g3}#)6SU_f#udET zLw|3xMDL%e>!2`}qGtp-9m=J}&dw`GIuFU!$c~Zf=}gH=FW&JcUbhyb%FC>D|+{7$vHv$8(lmlc}_O_+W=+7cY#es6xJ8e5#y*^Bo2wMKu<{UK=Rhu$r- z-ZA-Ki|yWlIOBsi=)RkGv69qx}tfiQk7G!8$+G=U_vka+KW} z>Z5SP$+gqcbOp}z1V&3Ib<>f^_6u>Zkl~Mmocp`9M;!Tc$fgUc$g9QiZj$So=VZ?j zc3z3xC`6UxbS3oXbk>pOAlH>Mb7SuFac?ALn(V=xz~}CXINZ63OuK=e4Pu|QDVJvW zj>DNi2t?Kc;u4jjOo9=F^HdaDD!Q>zY!!XkcLq1a16rPVv@3SwhKzr;u_{KXiYE;1Hu zg*sa;ZNuYK0zU?R`9JVP2BM9t4P0X!ucnye_!W?t{eVm|{$B=E#J|!17e0Xme=K)i zs_^cntNOi>g)J=w3e2#-6(2!ZzE%=2$dCNrLH?hgWKlQfb(o5r1Q@=5d;;o#jCzyk z+i$BPjUuoF6IK{B_+YF;6 zfRan{2HEJ6wt2fN8)uiZ9;)g~u2#U_bgsh}+E>A~hyl}W-dH^iOiSF4nBh*O!<#4* zxc+lBDv%|au{UrW5ElC`$A%mc&Q`3ODT9l4DlC4#z3!eMF^@X_%^;gz4fo>9Surm` zsa&Aclx}$x<~3A;@!gF{QyoiJ{+<@~H$JJ}iV4u7SAP(;YR024HWAL%f+QHMphC}( zr3tGTikqb#;cL<{4)ep;n~pcimvP4?KRy+2{&I9(dver$8}!&GM#rE7Qv-^WdyB(s z^?C?G?=}ckm&NVpSFUJ%hpZ^w*kTVX`>s@WsyNRmW^HYhFwL!hAnGcZs z-FRUVoKgC*r8Zkubb~xaXBf~7fBr-wX6q_u&~i%Kuvu@Xpc|*6@8bO-+qru6Xkk7t zB4^F7R!I;Wgb&pVGB+VH(&+$7N_VGxg7KVAWqrnhiDdVRQ)>2cK*}1fE8y(5l5?(} z9Y#=km)A)b(nWqsfUeQa4X^Ak{e2DF&=cx(fqI+U!Wh5q@B|GxVZ7gUG`ep0z>Lv0 zm*wyqKqr0WZ2yc1cI0FneLKcK3ER&bXJwq`&wv@-TUtV;OwIHOXQ->{Ev_e$x1i~M zpqffPjv=+Dj@csoNRnoDQ_SwilT9^Zx8Du?(;%1dBw?L6X9@EJEl6x;auRlk zVqHWk3pnM3978Ekua$A?9JQR=3I5}lmP($$hmdc;1MYjEN1mwYp=Na8-b)A1ocpbN zwnItuMC%D4#&UYEYJ^SK&wo}r=BkxGhR(_ zsaWegAERt>|F%H?GV59Iq1F3*CI-LY7wEAU7KDQK$}_XgyOp9fhY(z$)-hykoO~V5 zFsj`;Vf%cj0zPdN*J6zkU?qFCP{8$>N^okONZ8j?@B@<3l&4#^J}Vp?94(M@YnGTj7>ELDxv&5RnRPp=u|lU3D*rrCHTG z!LS3d<8ZDFJu2eF#qBEEip5wlHffzmU^;>T1SP+%A;3 zCfPYnG)5=N}P=nA;n^GIcXw6W~iV1zp)N80auqSt2Xw~F?;@=)Ey)4V5vo2rI@ zr6SgH>c99A-eJXblLz~)=rwKP<*wbrs9F--Fy?4)WjLzjY0l9>skoIQm(3qpi<;Yk z*T`Mqd*F8{N)jtBv38#^ch;IveyCkT=_G%!6+id;Re2j%wm=|O%9sPX?PH#3o+2~y z^R(eotLQxxWrS!GgH!vjT?(#!Pi`>UjK$7%6P-Tp4;d+@^fz@{Z1CE=w~UHeD7egj zORyrc18RBxzg>U`zdIidA)s{QeMxHW9}`qS>0TN<3BLkPqILh=7r;SOe`)%hza5V^ zi41h&=6$dGml#B*uFqD?4eTOcPZAvSgWcZmcwf08m#k0T_H$|_?d@}H-7v;T4?&3U z^-Rvw)NG&CcSz;?kyL^6dZZ6st0bx_w6)n^x14EqD?-A@W`a-e9L6r?^_zv8*k*cc zH7_gO!(w};cf_G`fKmn!LQ@jUvfX7my2-{j-vY#70dc_Nliz~_xf}w0IuMOWqB7n` zD-2_&7rf{3!%pwE!`q%8M42fsiKVB(|0q()AuglZr>0ZfxDr`)e5It{Ey68Khh47L znp)gmsMinI@r}LXHS#Sf$6?|#=$P-|y%>D!CmE?jUr-|AnMu^zhZu3IyHlES~N)%I@WfPBG@+u64k0jlKmg!*6b zH-yLn`$g*DQaCfVv&YHXm+m4T(~xk->N4HeH5P9=b-GCRr~^?t9Tm_#!N^0}$lr2b z&W}Xl-SPvhQC^t1JyexiCmkCQo%aQG>%>YidtA=qy%W!1JdNUWYSsk8)VwtdaC`j% zhh*&9cbZtx_N!-|%yE=yW>10ARLmAAkl{?}$^IfnX25-_eFn~X&uk)nowUyveeqZdL3Z zRi~;F1^JifYGkwMUCG$asn2nC^aEuxll;j^qInrj!v^=XX0&K%c2kLuTZ087?#4lS z=!t5JJAHu=M4LhG_#=YNN_WW0S`GAwM}?o(i~U233*h_)&t&UdrjhRDz(p%W)}+^J zk}Sd)2Uc~m2kBAx*agN*;Nia@Ft*av{K{C@eG~Z1fsoYkC|4uj+KTd7@`wTh4i=2~ z5c>tgR041F%u`w4rENX`G@$+MaN&fj5j1Df)ezc42)qSnB^bB~d&bh66rxG}&Qpwwz;-g;lbYalI}#HPpRj_SPUt36;P`&< zSaV?~fB4=DwhT8dKfg&9N~Jm~C?;{cVu@txkyRM`?v%bx5usE)KRP}BU3lI-RVrfZ za}t#LtqZo>u!;E)+P#!oWyh-l=+kV#%c(8mO(PN|kk-J*%|ux!R>eP`rw5klJ2beU z3r_TkJ_WlfKS6Dz4q!Oe^{P zqNf#*O;zrDB7gf_TWTx8R+tZU(Y39y*DTI~WdV3;E!BLbd1^F(wPTmRVm->3+VUFG zCZ{2|Ih}ub9{BN6geLbfhR4n^IY_IbaXjxvc4df0%AHjS0MK9mA0c4-5`L6Wy#|T` z>MQ8niK^i{yEHIpE|X`djq~Fa>#$!`*NOsmFULCAUy9CGJ{#gfzj)l`>n?A0Y&MFo zwtuyKu+)2Tyb2;QEUj$juWG><;35-z*qClw{I_^)P^PxsA-`@~(I%MigfkKxQneK9 zmCTwm)$sm1SsSPBt??8{m_W{+AKb~%gdzp}P6PL zABDRX#9MpksYmP@zJc#!AL>s?FQfLofRBG2z)g~PCwvg6XG1k?W&Dmy7Frh)rOQVPcPgd z^%o-HCnZjcvRC^bvIy*b5hM-ctX^#HoO545Ll>|pG3HgFi7EvqjMmRSj+?!l-IxS) zWVsp)C)HWjuA$PLaQ$=-l0#5ERITkjdJ*e`DuZCP(Kkr1al>sWkPm;`;?qj(ax-%A zU}*herq6p~#np_&Pi#d%{A%rTZ8WgbVxwn)Y0D_Mj@@br#IPn(e~DK05lij&0yFND zclBq#(K~855H%BgO;wd&XpIZX~K_>0s zDgb2pOT>mCW+aC@nF3#6{0Y_Eg)@>i)hh1>@66ZGaL%CVqc!6T{~|}ka@z#pQ(&nw z=nlY|UxUDIlDx2o5u3)6N%YTB3Wn%ao2ifT;N_qw=S{e;zRvQ6>TR+qodwm zRpx&i+YA{(b@f|hK-Z|E$esHhCa)W9ZPJ^dk0{8d#oUd;bXqJJY6+SpI+8ASfux`I zWVI<0TGo0aW&~xEZlXd|v9D$2@20yuGrun-@;J!~UZ-S*_&Z4`=yE}Z*E%%fzW^o1a);ri+G>BGOG;6{il33~aXZl8mqREMfLzU;~xdlj@$uy0Owei*IJ7WuU?;6{bT)jbe8w&ZzrA< zQRWlvFN^Ih{}D>oN@Tkl=t2}8`n)J=j!ET26__Te+yp zZ$A}3oQdt8lwy9a?CE_w;d|njN;+{#3S#Hz^qoU8buDhmkO0LwkXSrdW=N19ga~S* zsyQF})z>nm8}Z_Z{6UBnptb?3Gd&1)G>IpZ6GpSW2*P;8s`|jgokncgsOJ_-Avcqf z)lTl^D&IGMpZ;1*+~K-oZj8pQ?CZpdsntp%-#4&);4`00G9rpo5ZfJnwJKCA;z`p; z2T$Do3y?A-JQ-4s4uVT8i-h}4MTwA_Ez~OOnn&=1<#b6jVR!^{uKQ?W8sI_+^69~c zj7nfaKvZ&1^2{w&evxG3)*HN9W2`C;WBaAan+l2hsQcjMEc1|Bjyckc5ev<6Pc}s- z`O|*NL`vzSkwDAS^(mY2K|#=Cf^2IGGtMhqDokRD)qJO+DqglX`5%R((&i!9O50;*|<4)18Rh2qsYHTKEX7e*9q9a{*ptbT-?h#6rIJ9?}~?!z8_Iq;Bd zj>~CjvQpWMSAH~42v2qv)x()2?0^~cf=|JB`+r)b^~+ng2PlYC(^veLKw&rau zzg>1;f%Z1Qc9TRnho5N#&@RkHo{-T-$A!s6#l(7w>^Gu|WLdZ|SHVVecU#fiZC_g&&CW#zmcl2>iU9pb<*uJi zN%ZG$ciR_5mlExEm}2kzfQhUBC)9tZ9W#2%?-e*%2*}zvCBl5royh-j_oz?6)*Hq= ze$sdIfqB&Xq?Y{>E(I^#FF&pOf^87Nl!_tb?x;W-?#~zRFx;IryT2<>f8EnWsuOSh z|8aoy19E4<_7I@;%zZg%rv*O07mRr9aRq<)mmv$-F~FUzOvMBpnA`?AWqYTMhHK3) zGa4pHo$;JfYny_5kRq3Hr;xz>^>p>aaO<#5&m^MBrzR~se)|5rg<@@ga1s>9hBvGq zEdj0-OR?yaN!m#YFH*hTj-`$K7Ma<$-p4IKSp3}I%O}~bg>D71wg5S+-9;FxncMv@lLD%gL{tmcAKf?mSZr%~cANP% zA;=tp)y<&mAwMGY6z?EtNuVsBTFYdWx|@r9#sQ+;Vmyw=>Jcm`FQqrMq{US9DMRST zqb4bW%{eG!4HFAC0DS6SB1w-g^O`u}9IFsOPJBN|6DWwJfxa#iC35HyC2_3$F;Y)k zuVtFVEL^U&Vs2K0X1B=HGt02AOIP4JAK_NO`SNvh<7AV(P-_j*p`jsT%~#a#XKx-8 z;@d{@qfh9pwDP{VK43?7qe+cO8`zIw+yMNjMNqoCaI;ZFxj5|BoNldt)m)2zeFW&S zucmuF%O`f{#n(_=dzkD(bdkMfOxKTN>qMZUdqdR1acj1wIWB0P^bz>HAu}^OkOwCm zf{LPTKv|ujdNS8YW5#>@u9jJ|8^W_u5zAG%)e@M971Eskb5V;=8iA|b3Bvk!`2nse zA@8=DK<$mQ)Z5JiyUVD<$F@`wM~TmcVv5>Y9$;|!k>Vm$J0HWnOPA&xu*t-q7KJZ0 z(%qxV1_P5ih(>S;f@^7Q3<;L+lidknYvS;C&r^P{Pyk+Gsb<=p^bH43ew}XWW@b5D zEOB6vDpGiYJNP7y`2tu-cdF0PJUEH&a=!-WQK64t-D%uxPQ0Ha(e!YSp{V@*!&YPL zqLZZE%Ok$Av2)}%+eYg(VeF=bPhrzV_|(y#ak&64aizZ*>m}@dbRF*K$ej3)?3>yqw3+LroJ#kl@;oU|b()rnIB| z;_UBM4oL=!3Oan6k5%+N zodeS?E^2J5U3W!^YI(jt`eaCJNS_M9H>}{Jz17+>xp1`|2zv66^&PB%rRAJYM?1sr z^+%zS#~r>dA66Crd{TpGo_Cvs`34$Pe#&-ne&+vq-{S7Qepc<6ofh6VUJPxVsii0# z+=rr-#i?ASv>uc$d+kyUy%H1qFz0R;2LDMXVo|rTOo22 zlKT}IQ&{RaVy5PF?@?|v@N5A8je$~sgfZLTq`FX8-NQ)m1M)M%)+&$a4*5PI0KZpM z?@2RPw~2h52=4*eMMtF_UtR{Gnp}g9k~?B!tf>f2#20W!!gH=gN90oM!Ab95=Ql=L zB9+tH2S+W(O-vvUC$Nu4TWRk{w`M&AHg+FDl!NnNz2YzELYg#iYF(3);Q;*FeFQFZ zP%oAVuwO+?!`FKTHPwe*zgSTaktUs}ARtvhK#Js66a)kWDN>`-K|p$dkf`*o zRHa2ldWqD~L+?d;FA2RTln_Yq?B{vU%$fJg;S)1V2AJ&p_r9+6TWjgJHEOoMqPYBR zV7vpf9JhAdbC;G;;8Nof$2Xe`(>sl6X<(TB2 zJ$1Kt&Qjy8PE5wP&%!`_Y~z3z&svoS%9*)fUX$IhyO8Ti{f%9&!AFjwMCoWhKSd04 z6YJ0iZ109CixmCS@Rv3Jfwl2sbhISIQYP;zHSU27sCRgar!aV%e1Iqkx=`T6)7s0! zWxfh3;4cDT5Snp&O%V`V4R-CdIE#^-q5wkRXXKPF{pSXL53hS6)Ka78-@HV60A2Ls zq&S)P^?Y9IrL^tK;OZ9zJjd1<$de-Sehc7&zCsH0r#WEfJQ|ub$5JQIn`~S*vLJo! z1AUS{JZS)ho21Ryy3enVVDi1HCs?K^sdsg@ugZzgt|ZMi zDN_C$l7Oj(gNY{`2yJ6h*%|JCgE^SFNv&Tpl{+%*C?o9u=$dt*m;S7*Vful2+t7?M zvx5;lk>W<+vl`8c&L^~ZWK1q$c5?`(I7BOCR{dqeXoGr?t6g4orq{I_{o8EjJ?w6q z6)Jl0wBcV- z)B?H=llVvXsQrDLci?wc(<$TM30A)g-OfGp=J}rv7zn(#NxTeb35{phCvZOb7FrW! z?Ah$c+Pqrhj`en?3bLqi^=zt#l_jyd2^<~OC7M#0l`~)X-qB~%3-Y#-2wdM)!PgVR zNo4RxZ|UpbDI(a$C!)V67sNm2-V*{hTw-6@;huTqf&y9qbt>@E$WBKWK|bZa)hjRJdyzG8 zmjtT0UL#ScvV1zC`Nem6-xM!z=bRA#{VYR`Z51`DgPQGzaN?qXOLh3iTQ?QaBb}=yE4DYn%}!3^Ojj9M zw#3Qxt=FV3;kS!kF%%U2?#+ghGa*mUyhGOEFqCM8vIbs zo-IXCdx*5|1l{bTc9u%GbEBZjQk|}Omu&LAKQCx2e%F}os=jN=@nfrlWEb&lhhF}Nk+MUZ96VDc6ZR9k@xWe9vweN zLc4IBEkYzy?EXb){Y$h#j&?XHg>-z#Wt3@qX^@e-H<^Jvbqs`BwxTA*3^ILbRyH?^#|p}DXc3n!?D$z}-s*(>GNZH;!d@GS{E-Gj3B zd&slTIh!e&`3r6jO`j0m37T#H==kQLi!VuC((NwtaXKc!9*!v{{91=XFHO%TXYQy? zp|I{Zyet(I72KJ^jf@OUtTi{jn`elc|1Kp*=%@H|oF0u@o=l*G~-xVOGA(VYp`e~`2Yh*!qo6-m=GvV0b z8(>r^L+pP2MY3xWdQGvf8H0IULpZtKz5A^Q{fhO)&>zhE_idn*rYdR@K-5NeBAFK4 zV*@N+Z&xb{&)Y#^VKuRu3%19vzJ5I^B1)qf2D?cx8FnekIuP~+t z4RWrNVYD#Ag+2WBncK$T;CW6QLUnQ{Lr^=ERFKsMx;O^BielvC$xrsj#Wlp zBwkyZ3p(6zo50q}lRTG}7e=`oNzCLM&j_QfGx4Ed$G#GW*CVLiJ&E0%k-QPw zxCig*9ZosQZzV1}5R||1lzLPX_sU0NaIPMi%GD8|3Nb7$Y@2DFcxqTx9Eo$Sao&9J zbYOu9YJCPo0bJjVi}citS7#{p6KnYNAUlt2UnzNej=cz!fGG#C63uqpU8jlz5gLO( z-h8$#zzVa=4~z`#&MC@k+4&YuiZ|~my}lcp4dZ&UYYP_XSKC~V+5rAjWi!C6mWYpT zQxh0l`!l-hqayC~G_m{ez6*DTYPd?q?TgijXpS}9ow2-vNo~JXHSJN_Wq9iutu_y8 zp-KH!?gH<-KA`oHhr~!P-O>Zjc6y9 zT{`{ClHn1xe$CEy<~nnUtIm=PvK?*!h*E~M8_pjnYL%pICtRb(RqyR+R|Vbs&rQZB z?1RdG7~bD{=8LJ!>qJB#u7ck!1`|kNGX*svLTqkw&OnK-Fwew2Np#P>ujn`EbI8IN z^a6?}JIO&@Za6kA^1!}`tVFp|kN&%la2T2q9$8+#l-TuXew9{u`!j8cvb(AR>oq2| z$?XC35gJgMg=C>#nyDRz>QZRp^GiD^dH1!{S{k#}V*G(DCMFBL4Q$7lTTc=HHHI$H z@mkiNo1sPd^nTNKn~zU%>{3#fAu(C^Ki{j&WEEuk{_V1{Oo4w76EI_s97E}=3|u;b~nxlwAMlDJFLz|;}2sFk+DcT6_B^T8a(VM;E=iyehqoWgPp4!!Zr ze9z4+&OJU~2M$@RTxrpeYJ`cmt^EyW9Q2!`D_;ZU%H z#s`ejsjuL@!LpGq2XC43=r*mpyp0L^>M1~zEGtx}6;Xw1m%iY_!_GGQdaBJQ=W6!# zXm^>@KfIpD%lI4uV%HTfr$hQ#2$+3QZ7$w_y|+j6bPD|qWPfK~mD!nNd(?)git6R~ zKyvoYkjh9?Ca?}YOqI_PVT#S*SH7QC;oI0yU!NsUeoMKIN3`0w;Nlt03LWckNYOAM zbz#MiS^eUh%u|y~`=4Oq_(W~OQ2Y+y<419I+g1lwYTUUzl*k9<%QXZemd#&gYjD+S z%-lsZkmH1w-w(01aGC!p9CuDw^&KXo*Jc|rY|G3ueb|oFV4CDYQ_|-N-VQBXh}5_d z0O}0D<|S?tBJcEO#H^Ucn_M+YJ9Icg)30%Oe3#;B)bz#j2eCfQVi0#H_%$nn{a=|> zbOWJQtr!Q4Ct*gS0WwcQ<@Q@^oF#>iRFM8E5KPmT)zCoJ8Nnj(`Sn*FrZ>4R+ z@DtPyBWN|xH#N~4Ajonj$D$y@XMpG!LORY_PiR)%cnI1X!P1z5L9cZhx z5Y4zF0(nUx}qGN~Bw?VVTX3OedB@*ND5do+w?!QbyEkGo1gU zC~eh66~O|M4lr5j;Wax*4K_GX6axRI#Va^vjST=G`qa#sw2)q4=IQ`NeCi z@Eom*1OjfmO|aB0_;@RLZwRO#?;0~*7uon&sGVvsjcK$zbC>?_BKOf@nAAkr4q#O>lu*i2} zoCJJ-yVf>#AawrG;dS^m)*zo~%A;mF>Q2QyLJnoD7P)}q3P!7146~qMbpyO`)u|VzbnYm9sE~wJ=>e`y6piJ7v zEJgm%7+;#>FJFOP3QUq=c#sgd~)B zca1=d#{NgjE1b@*i2m^JzsDX7dWlzHnVVDDsDRlEk6Vqo!=!$TXw#=d$(_|Rh^}ZA zeO6gBpy7zE#XZPhU?aCCO+V|F#p)pawzVHwhGbzFyzCyYYT>{?5xcYv%@E6XT&_*z z>tP58Ql9YHM7v1+)br4qKT<6szHz66D*U6vF*=(I=czT~V$BJ+>&U9#U6q}#(yjmO zQ7Jl_)UD9+z9JzpZG(!hu)POON^suB@9s zrNb1v+VM5Y_sJd4{5ht1DC&=pC8qRI(RlN-)|;uwwIM}b18qO6)RhR!Kx0Lpp+4&s zW?}s&75sbR4fq%5ss_}Y1ZAIbwClA50BxB-e$Sx9ANf}_(^LK$dfG66v{mIx57oMG z|Fua2bO||a-wvZ=aIO>OO3~_pil~J7A%E@?6rl4_((78K0hG0tz)!59E*iFF|a#^Z;Z3N`7fEya1|+MYJu3-zdpz z!!S8Dfj&x|pSIAvPM>RJy2iX4j4g5K0OMckPp{4Nwz_NwfxByK9c`q_BowV}Dw46L z&T+clc2k2eW37Rs6k1G639III$bm>2;htrR(D`QjY-sgusV9o{=OC=h_Y_7{eig@y z0jd`>3rrO+j9J#b&^7}7b)tp#Umjh8>8LHVIliZgpC12hl7KEQOLx}L9>B*z%&HbZ ze*U$MgL)^PoAEY+W)_2aD{)VQYK@!c;D_jiQ@A;KkNcbvINctVn5S#MGVC6LIuTp7)6c2-^+ppnml)fNOED@}Sco!dReTT$LmIvm= z$>@ZK$I*yND=SUzq13x$xmF=3;u)r+za$*oTvp`F%Zeg1md7)bCO#MPWhomb4K1Lq zYd)6naLDmi=qH%#)Y!hmJi{8z+j@>5pdg^VSsU4-%LM@Dip-mm3-(qnEyVW(D>!z+vC#g|8&t}?Zl%zD{^t2N)ko)Drb+fAFr-gi>IEh z6_Zo87?Mr={poBCY6v`2)Q%CLF#y4}U7g@ib2d_{I$3<$`GzLvw<(9gHuTyBa&B&+ zZ=G1WX4rO<*#8Pi`zsK=cBi3!OltYfa2MmA3V)ZiG6OZNMzoma+{{PO z0dK6&#DtQwnUm)qC3(Iw8QVwCy_>=2(8ZBF;0^0;`?Yue?CRLfCS zEf026p4cQ$-3V+X*X?9Qx>7C=>lEDxqYv^UzJ8GWqM|7(18MXZbku^Rj@xIVhyW-? zh*!JJl=hkJM4{lU>YFbS?5?L}@tv644;E)J#MHzkJruqk=g<;l({4`P&FM^%N0txq z=&ap~_bxlVmNWUt;16(|ScrsPduk_^XprCn&tD&xWX1rW?o7;;20MH-5i)#);< zt8Ki|h3f+2!4rxIj!A!ce`lT={q981=TFX8#!F!5YB=CT`csTx*yus{#pnfygL@KR z*^Gmi^6M0Vz36n7>-j~UbO@$lytrv_;)81JRWl_askOFi@tsXwBv8(Fnsf_@Zlg)$ zEflkIo4tKZ}Ss=aBCc-I<(W39fRh}8?QrEYu z3Tl@!Zr4W=Fr7o601&1U6pTCvmm&!)7%T(Egg;Jxgl0^m%$sj>yQgt;NoVq&S;Exs z6bSx=$WD;lYvdikA-PClZ7&18pNvFgOO{!ltM`*wj78YIeK;zXA)2q{)te^{d{z>j zXd>%|ecSi6x1VBe76&nsb!mf5U{X3zg(^r$ZR@-Gs$=2G=+3W{eh-z|Vx7MM+4+E_ z#JTJhag8+k7W*0|>5pGK*zXw5`zqAO7c7O5Iusa~Mtv#>>4m0V(q}TM3n|d^!@Nd& zO@tJ^b+{*L^`Pk}NQ5lAiLCUCINFZqrrRcFdl*3@dfY1c85uuU?s5AUdR z*li?$I?*Yv*OB=aR{Qo(etZ{tVH0lv;STSz`*ziS>V+V6Ha7`2KarQ$XI}AR%Pn*I z%)qPIiD)R~ci45#=2PS6L(}ZB2b~`DGe4b}pIxs7mms7hE;)6KYfX{;wIror7XbN> z4X+phzXN+X{6L=(Xg!&Q_>UBpLT5BBO~)`7;fxeXJm~Y0c!_wMLYZ@_vJZOZcbbei zH>?c9dt#GugqoG%GsI_rLYlGbPKWy6rHyS?tgnuB>J_J?KnlK-O-Rg!q@Q>}YrJB3 zNjrK_Fy)GojWDalg%OM*uo1*CGzo5jLGK&vaE;1=kHlL{Sf}L%L%jsgM{>JO3qS>1lgI?dHa-l=@_=i#iZJx~92#tY z$u>~q%b!K`+FUrVer=(7_)ZCqpO^Szk`h#OdAz}IIepel=XvOAb+w6vDHtkeb80%G z9_Kmr{fv9~z@D4l5B{%?EME0`VF9ojaXlDMb ze*Rr>&U70Na9ph^(n4KLkoU<*ClPOG?XUbf@lgo#ik~mIGH*AL(A91NbQ)SLd0{O+ zVAtzvBX$ld##fSDF9;+j_N>x+x=-%~5GvG{n2-HJbfqa)b2Z z`s1(b55?Ha_(o4obB3*)P6Qrle@irs` zsrAj^;=ET`dYg;$zEpj65jW#?aWk`^vn(o}6gDBa&gZcYQIAWeGA>P0A{H=?B%07a zy1-M$X9x}CEx;TD8FHX-vZ_yYgQMUTb70 zPfoA%ymaWbGoL71!<3^#DO#?CMZI{fbeEntfIbBrRuVJfVV8{ea7qMY?E%vpAi4hWXD{urVuXUA*PGSx1gRlEQ;?l9UEr#Vv!CJ!pS zW3i>peaGy4{{`=b%%XlZ8CnmblD^sX&TKn`9d_5__ok_*zm6wEA4B)_Ox%Wri^BE! z@d2Krm7Q2Vb5pes_hS48g4D@s+hAtbO2~~(0g-W##-!WbN>{06Hye?=LZ*-Ef~_1| zEkJMj$ShmPD{A+l0o#USofwyrD=5j*VOS;WbH8NQd0p5e!UFKT*^1$(yzXIr>~(2W ziv5jec7}J90DOi`rPBEfJ9}P{vA?6<>6$zgnysUf9} z?5y$As|4OIP6$hbLq4f#ZCWCWl<=oh=gP1KUC(w`0PDnBCbJsqH`tE<#T3N@Ki?1= z?Q+`Du%!X(UOClK%c*URO&~F16?g4OF?I`#>kG}wbUFp-Syz3jhtGt zVB5O7hnIkAO|K~Jmi{W_IeZ>j32Bp#2F7@$Y|6b+PQ78(*5Uuk{O??h!Jq%6Rbo&$ zEVl!hzQbL$KP5cWrVOuAOARWR8*&?Io=SV*^zA${6biKR(rKhn#_%5tYm>?z0xl8p&$mcoW=cyRVI6 zKvtg6J2saSbH%H)KmX|b1m#aa9Y9GDbm8V9is*@G_VHUU`Y4d|B9dO07 zOD&^Qa=#v9-1Hfy=!GuCIY(L`6HKJegwYq%LhCP=)v7;`y5HRXk52Z+Jo821xWnuQ z;e%V1rCWi~2j++$3@@^pg5nky4n~cpSEtM)l@5eneAtnzt_aLFLQ4V9b80?_ILI{| z!Jz{g0%CG)y7eftAf#S~ZAQ-FwgRQ=14uURSJM>mAj&~OENwRU0Qqj=z{5Y`T29K{ z_---9OE3Lk(*sHyqHb^;$?=7%QVwInwO=E26heI;cZvUXHRrgn0%sTt;e0C>@Kocp zXWw0o`K$SDKDaGQt)>I+0OaCCk~yH0Eob|&Si++*HDUamU)_82o9nUrZbD2qef?tf zRnAQBs#NbNB!HPjQBT|dx8mst8NwO;mZ07`nV>KpZ-8E>U8X-SMn!bm5a`=GJtD8? zL0<=+4*bWR#a`nAVcX<cAmU5`NajO#{~w-K5C)=W+@ z{}a@d9r=%Le)9M)753LB-Bq*ASCO;aJ;|aIh0HM3zaV{iFuXe z5&>pGxCSXNzo7nxnYnt!q@aDebW0e3;VpcJ)sohQxY~D2YySx6es8+sgNYP8t^=P} zYy9;`0Vpm0e+`fS|KEY75KE|B12X@7#31{2nmu8wHt`IHNlK%mJ^~I=m(5{)Ts)VS zkn4JGnouaAnHTQ`ft%;dSB-bn3$pU2xP@WNu><$lmnn}+?^0qBtYRXceS8ugv)uHf z_t+&@Okj9mGT7;o1|@u+)gdbmx7?Y^@{9pBv|3!<7!+NwywJoJ1FBbC`5)X3c^x(1 zHAahEA93@pPpMD-ouy$XgKdl`YIA+_HHE4@l~?eQ>5fXy=%$PI(4AlEdJFFu8;|XG8NoJ0U+0?vm9o zL$0D9b|P!WZ@X7a&px$H_?rkU_JO)7`rH)%vx;15HXvBJ$1GMoTZ{D~n4irU{Y|l} z_&j*d^_u-syi7!oMAy5RlqF^_Bs*R+n&PpWgwJ}=)x?NY(Xc8rLMIBL~^MF zS^G}?xg*V;vSO%Q8-$-CkD@$HnPH-TLAE^szmFb_jq$DUcUr}k4+#IwCQt209R==B zGZW()NR0HI%Y0z`r=AC?H!O7We`|nc)j??~2jxE&piBE|$%UpGekXD1#Hp;&7R=2i z;52)u&XTT)2Z#SmoA6;%XCH3f6ndtAJp@QGIA1zMl%XQQcHo!=9s;HvJR^;x!&jzV z8xk^?OdhWaiG5#oIv~p!`gQfintYth7t_S<{IZ`1%$=YJI4>b+Asvf3=X7H37Yvhd z`#Fqj%9yhb%EEamIJnmUylDP?xj2`0Qdi@1e*F+t(-Np)d!1%DefFh%{NQ7 z?XqmK?f6t7lpD;eE$KGI0}d?2OWT^7r^vJmjBcqN)7BpNKV!5U*$QqK!X~x)B1pq zl{ zU5N$^HcNo1pt?VW6Yl#x(9gf1XyJilO0Q6YZP4zm*e2`KYs!-mFbEY5q{ZyhZ9y*Q zjlewKzQt}Usj6^>ORSJN8hU!|bAP3hl^E~iMXO*qQH`kcLJc_5{p_;0AA^!Q;#pH zN*>J4U$pFuWj`t4)#xMo-Gu~D=R77b58Za%-j~{!H-`SGL3{Ci?ar~{*JJqNf9ZLr zSP(r(ZqMcy?AjQ@ep}KV7)rRRn6J4I174YLXYukpo9!rAI6ct4_72C!C#0~tX8*QX z_08mWTF;DWR3)$wZ(F_`yAHfoRw=qWG8vbSq<^6Ke7h5&I1Wk6ex z$jhNf0lG-8*SZS}?#qZ29E#BXa0wxPpbti&=G(~fF`bqUo#vV`#1aG3!2NbG6 zMf#uKnB9^ql%?WqL)MWbCjZHu+l7|%u!rLk_MdDH_AtI(q_CEu0mue(FsoZ2%Cu~2gXxq@>CI1-1^pr=#L-2KB~GepX`JUHR5fyI~|5bOX|StPaWcb zqxUnIH`=i%D3GTsUzUxhvA{=P&T%O9&V9Q_;ycI~5Z(awDT^tqOP%Dm2K#T^{k8DC zYVv2I3d6FUr$v<|;EA-pnXOgE!@24Y=7Bsa*Y|+2YdK%9>MRSSk>t$S$uo(YLgH}vzD5Ra0W%B zD8lb6etJ;Cqw(R554b)#k@t!8a~tc+ii+|*t$cEky-+XSZ`i~llagg#$!y>B(=?oi z(bn?4;ly%tjCJ_#3%69!ica+|(YfNhFs8rbpEyDC2xjB8^#q5_DEMA@F9OZyiD(mt zJ%01yQVE8Z)CEbyTxg=BwE`1xvkG$*gj4O#{A-uL&y=^!-*bNHc;Ho36KjKZoH3pI zq`e%RMx){rSz_Ao9eD435yM4s!9zY`rr5WtUF!@?!6baBNp@TwMG{%;au07^F#4-1 zYlqYuvwQjLS7m^IjnTLZt84?7sSbW*hnTduwd85&I@@0xAxu^=t?J#SX}HbX#rRXoKD-@4jlo z^1F@e^J%vlt+Iu|4g%w=9~M}%0Zy|PwlX449x&Ta- z*7&0KvaLzb^jTb?-c_>Q_*unI@Xj?6td%?9EDosyce#`9Nultw9X!QpYMJmaH`8w9 z8h)87{`_G6VDFvGLOl@1sRYKFC?AXzNY_0fs%`^ovjA~C_>~$RZ77SAn%N*3hy`5* z(vfpAsl#=W&{qNc_4gIxollo`hn*4^aN zDBq~%?mhthimcLXi=XkFxm-J3t?A(VWY75EMDqc>D_44QSm4#pfV=-XO{H;Af|x;0c;gtOcN1$ChCv9)ip%H!7&eD)3A&@r1OTO|s}Z zgkC<;tgWrHsQ3Pwn=F{}(Dpx8M+=6j`NIIy9X=5&!#tBB({jl7HVdP#XAb21v=#^> z#{M52w?08^ww)(6hT`sV?GG<`{;N9Y40!VS*V45`5e>iO!K=qgq)Fm1wJC>yi4>-$ zHeGNb)?LcY_MEY=#}!S}hThl5_56y0e9sQ`XVn>73OPn)w~VFO#6rUwr%EvD(qRgk z)0i^9a4-*G9P$d-IKZwa2dDluKaxJs3=1RTa*uq zz2?Z`dxMVZazG)zN>TI7FP^R&eRm-InBf`R5kB2TR6~;hMVz)yM2*Osxr&V1MNRAp z-WrKC3-9w;;mFvPtY10(u&CH)9nYkPngnugzROGY72q+uJ)AoMK>A(%V`|)v_x8|D zrYARR)j$Z@!KVpNZw_-_`nvA)NbQXpV1j}CmFs|3Abyul&V(lUK3swO9Kmb`3;wPz zzEb8bpL)`6YWhR0WJ+T@X0q27wEtJ(>v9+;XI)IBsH1NCH#+ZAAWB=wJ&6FBekhG? zCuL}M4h=Gs#Mwfq>6KTX-yUtR?k}bnujbxb-|Z-*h>fe!!NlBSeAA+#5Q{PIS}C7L z3V@(4!(X;=eQz)nC}HxA9q+TA%%orp3m|jo?^sM#&Lo8`Y@G-hx4>S61LHwR*29v- zXUdju<-scbRtx?!<;m0a{fFQq3DXVq4%QVl4F?eNYmyBnwzL`D%R{?&JYQt5&V4$8 zO&fJ+aNjjJAj+36iq-B~yuR%g6enJX&sLG|Y?a~psJU((8|W#=qw<|5&e}dPQjZnt zzQDho6(%ifKzUM{+Fb0_hjVB{;Ef)pK&HsApLM<)f3Uu?yw@8LaEwX=yE8L8o9FHD z0;?i(y=!f#X) zx*aY)Uz7O*9+>{vOLakC&gLo6EE}*wUmBP@Q+}v;$@U_P#mmm2yaix%gV^Af{iM}Ue9ywIe?ZS!N#$_hECYT;}v+) z_c=~Mp0w5`$;9?10Rn301gFu@setl$6FX@;ZI%>xujPN@#Euu^&3WL!0xFZK^{w=2O-)m7U}koyjX!||p$m{%LpVQ}yt!s2e*GW{^I z&*hh+js9U0{y<#{LOb=;#6pB&PpRLUWGK%85SjVfw4>qdW?y!_dhe?G z$ZtK#5K%6vm*k+ztFf`fbYc&7>OvXxJl%5iEW8uTDa^O2Rd9}t1vR|FSAcb{D}OM- zQtSfMsPGo~E5o))9P+28LN4c@XPK*RD6Ak$JaL;E^0lc}`rF7Way;J}KD{g~-qh+M zV6cH46t#4?FqHlBX)`EjAWU~x?5XvG;bnthsf<(i6I=N+{d1e&x+agn-_#O8 z9eFhR)9m&0S1#IuS~EVb9HDluho4#zBge=_KmP2TEA_H{9zr&b=uJ>OXQl<*F8R>C zbV?`|Y9U-m7mrz@kM!xg8loIm03uoy401i1FqnTdE{k9|om)dyv=||61EwE=onk^% zDh}3P5tt*qho(c}S1_$5=KXUG0rlI~M#bg5d5CWs13wjD$iPn!Gm`qUJf;IYh3eqs znTx-fjooF~*KAC#)7$3UyB_qKgW^JnQB6zF6RjbqO!m?EsMZZ^Q3c%h0#8PVXk4Uf zNa!MmsyJBJPwn=AO1%T zf%!4FJ$j;pxne16X)zDrOCYv6ITYJ9(M!*-#*Mud&F=)P9y4KC@tz*Zr~hv!U;gf;yyqe!o2CQ_91ZuqC$8T!n$S}`80XgERgCt_`)yRR zZu^f8_5Dbs1w37^PGTwCR&EN$#p;*^y}f8CiDk%k5)qO%9rA)`%w)v*ca^{=Q{JR- zUMUcsuWKCYEBiK7V&apgO=auh+1|J!9C zXperGNhW$2p0~?)kG4aFY``M_Cu=S0|75LY0af97rM`lmS+EIJf`mVugjea0B0HpI<)kdXrmhK_Mcf0qPTvZiviRKi7n zBq$S%vP*MeXDss;Z9%p~MdH51b%TTKFGhRx+i7lSyC0-@b;Na2LQhrTJQ}r`?Pd{9}*` zL)zA7h6XOCUTG$Em?wZ9)O3@ekT9bd@nGXvMdS_b#aFkPEzc{+r?d) zDHHp`9$;dSI|h;Yotyr*e+;Jddu#Ii9$DM{K411PS3!a~CU>gscgKo_#GfDQ*M6_n z)gndij%qk(t`686*T%-qp=In|{J4BOU`(7bxZ5TRd9MU3lpN>u%FkwD;*FZ^8|I+g z{Kkr0i))A_;i^0X`f^`Z6|FuuWA_f15`05laxNxY-Qj|z{@sz_L2i)JyGO-c>L*atVZGANyV3awEyLKQh^JCs9U8+A$y2D?Z)eR@ z{tn%0^8I9dIra^DaRy-*y*sN~p*FmhbhLOMxEj9;2&F@I)=XCJxpzCa@%=ROP4i1yR()6U z$~EqO^+!QZ{qw;rG_k7ibo;W<&MR&&J{ic$4KlelW*kfnutNlwqo|w@-E-Em>22q zMuy@2^k@9{S@auxXAE`fInmo~W zk{oG}dx~OdnfXtZSg7Uj;B6{zQ*IO7`}g11B}At&bWd|piZ5DN!`||mX`(5UaB*Ce z@{0p2H^rbQSYHM8NNv0qs~jBWSbUbo>T#x7mjN-$=t+8}TCPXRc)joTj3+QvF6_GD!fVP5avCH7CU@ z5yt)YmDB6f9;-=DPlrVwP>7UwkTdbCU+S!GOh0JpW4~7TXsfE3^dm+ zJ7Z^~jFEYyUKxwW+?$FT4T)~A1thzG#%k34PlGsi8TqJOuw0AbLwSz-&`>v{o>zIUX7ohcJ8aG=&bK#Siq4+C^q#mc|GoOvWtp-h z*REXg;4QA|y+kqj+Z7JqD3&Ay4iwRJsR5soc&oftR%2M(!m)K7?6(cMsSoVXHV9R7 zI?@#30``uIJGYZA0J9)bo;-PJeR2Am=98T34)DCx$Rz37qseCd>GYQ*8J{4p{H@r+ z9xtwEu7kc_iEXAMhf}I${&E`Sc_(I`;;UXKru=bP!Z%hiPrX}96fdSe-o8tDZphV2 z?B+0e?U1yeBH*&(vP$|6bmJ(*m+NgNAu5U+R%(>rgB^pZmRYaokm@IeqqB2$DJ`X{ zdh{%2MT_c2%lvKu%pZ5heRS+UcqInM+gSgjgKQvzj~=CHjMChPL0<_M_oGiQaZsiWr^+uTOjg(zfkZHHG?6EoJ63oc((${ z?Ha(wesT6wj1MYM6i8pvj7&qEL;e&#srpr>^5Z0 zAv#KCz{ahcmX4jJnw@3%#kt%4!LL%sG#@^>ay-X`0MY?&Iw*o!DLVJ|gC4HfkOtt9 zSO)66!-ju@HtphvlrL57eec89l0re5fxx6n<0B=u(3J54Wl4wbJ}%PtxR%xjpUCY( zMt%5y4Gk$(m5~8B@zNz~1uzPJ1hJ}uvHM}fFHYtcC$zvbwpE-@_F$QWgvAfHx-K{= z5mDa}F5sC!+&i$TyB!T z(JKFe+ch~TTeJ~#tHp4dDs=HV=6h*g#n|1*-(CrGJ_Tg^=p}$mcSx5G=1i;FApI#m z5FWK>Ob+)$-1h^SAAx3!RWA_5AKA2Q+n)^5j8KmGMXNUPUtQ?o@0QC5b^)5LkQ*~3 zQ=D)(j<>@;taVN4`sinctY38|Yx*`P;=~~m;1XuoOj%^BvV!j$;@z^{?PM)Do3-q_ zF2dzc1<5Z-zI~4;8`REprB6s}wbMpX|&Evs#7u)NF z+RV4yZ(z6pQ{Ym$#5GAdx3nJtx_<0VdhC{NTv>;1s+}zTnjroS`=N76SfSgLyXEL? zq9lh$KN*0jL z0VqXnm*TFW-Y38F-__K$;>7actl)z1CJ&V=g4*lssEI8@` zBn-o3YDpVK4kFEMRR5UIX>!ND_$*|rqB-z+3C{jJ2@X@oiEqM;r6a3!9IFCn(<7xs z;?}@2!YLZk!bhM5p~+3tT}iSn%o}K-m2-kHt&%L5Kg0RaQzdC<4|DClO(n}{a=$5H z*#9qpZ#j7Awt><z{VpE*Na0U;VcoJr?jBrXrEx3(dD?$n z*&g!*?5r~sy~z9E5hqUKjL-aTQ|N8PpWnG=$+Do698KY}{39uzdR{HyT?BBGP#=7p zm6u6n^@Kb>xVO5x(%?=7pUw3xUrNok^(Qi5IB9t0vw~Zx zq2WIdkx^Mc>`9NzC}zLzTq|p;1}MEE$Yf{D9cZ+-4;oVA_ygP+X`8H z)PGZUUHmNi|6%OCf|~r^=wDQt6cLbKqJkn_x+oG+=>h`Mo6;c^=`AGEl@)isR0kS9j-~ZlC@mGwXs2PF^_& zf=uMwxR&k+oS6|eTmX5?Y3S-zN!s7b_F$2jy{CKl39ZKg&KhKo_5nW9;$ak|;!KY5 z`E16i+A7h;^$M^n_wj3O^QQW0{3BbC8b{p*@*_wdrxZ}NK!-S;f8~^q4ukRTeYHEn zDe(u}(1OMDi1%@bo*F0{N4^kC>Z#TGNEI3x%A0?TD(bkEWUgW4#hgCSBIdoubm9@4 zwFDu;i;}vbBRet-OGLz`7k-n~1|L7umD}6=j=nzm%X|K#GZ2^rb_Wp{%<{?jJ3e)H<@b&oUFY!a){YYV74pD^#SZ zbB8_s3vwdMRI|WphO0xT;v+5P!KyGivV|oz+mwKt?gV^gcbS&eCRE*T1yybIY-$)ld**!+&To!=ZBn|$yTBnJmR6=N`qNH0 zt(Cu@PgQ$J^eLzE_Jr9Ai}8MWuTwPoFGv&5Rq`uoi>7@a7n97aphRlF;U1G|};3sJv| z=G|PDs#$w#Vk(J}L(jK56CmH6cm;8XQACOIK50%^c`!xJ__N+hm8wTttMztVUP)O~ z;aZ41xFc$ArUOOmJ!JZ~qwWC`i`a3>SHD#kcrC15Sq4r@2fMYm1&TZn_o;Pkn}YS`nTYM1pNW{e-H53erBDd_K!4j| z1JTKG07j=Naz9JwiAxUK4Lq(r?QL=|`#JbP;V)51&2|_bPIG3N!-(%ty-?WYWy5ZT z6YuB+eZC0vI;Rx+adp5sk&;rU))XJl4BqF<9Kf+UrGWsgU}XQPANd6}wzL%o z6o1CGD|`UvvfLye-FtuHtQH=F=iGDvX}9emRGQFINa*RBzW%Q1Rl}s146S$6-iBQ} z+g?+zjVZ(Rq-E#vKJI2fafO*fL*t^kn?}CitIK6GnrT!iy{}c#@~Hfi>MyRO{Y&B zkj0yjJ9AO1k)IoFIfTI-8KOvJmo+;3w07C%1Vp=G;6CXGMP`2w{ldbcNFj4ViW0x_ zwDMW&5naOkPp4oJA8?(+eh{#5=EE?<3BV2jG`5{a>>rnkdT*xqsg;ZAq#rR0%*}l; zSiBmy)dEAn+Z5JuEOmPuI5spx9EsC%$Mi6IU!e6@`sRYI=}AhiGhaN1ICA5vEID!i zsF;X)D5EwsXH4k9zan%2A`kg8VSjCj3V5aPa<`g35z#%G?IbgEb=QXJEe^>N?ZomF zPmpl6#|-E?)DzeJ3HM@+AztyGf8bbk3%IkfWiyu|=XXFss+V-VYns-ItQm4Rr|MW$ z`4ZJi=O2V;L*k7lpcK&blY=;~{6+IHcRXuzy+}8<_8*xHGJxrAe*f-0q;MN#U1U?<<7cIq9XXLGB86L zTYnx=@Bh$z2TtX-TYe?o|MfKk*X}0pNyXr^2_b9nPk<3%=(OWvpA~f7KSpCxWNP%X zIsj3r^tjOWNywi}VR?;t&W<-QW70C7Z5o)(bh__Tcj{RzcX<{uV71)25L;HfGv>bX z%V=eZ{|)$fGuL7)Bo{h(DP1404^M1+_DO=y90V51ZXxmqENz~F#*K)~$>FGq<%B9{ zY16E{SXKRtrA3m@ar3Ehy^tJ>01-m$!%=1u5Nsqqd~+`Ft(iCm11ov8z$1kayxP#l zPp{`Ae|V7y&wY=oFo^pGqA3%jX0ijNeV_tnIalJZW3ud>aqGstjWc?Y5EJ z*7ob=W~4KYcf4VBQz)ZK6EkopW^e}u5nh5`a;$B#FS-andacplGY_Iw zkioHGP;FW-Isof{HiDZo>f`;-I(a_>o`~LxjD_a@@{}^)N9=K3@NXNzf(Ya*Qn3^% z2OB?m2_~$qvPjM;^rF3hc)t+%-O#~5GQ+1FZ~3BQg{<{9D-J-|{MK8l*!H#6N|NY%r==e1n!9_Nq0FEun+U5YP z9NN9JoXLq-3|ANRbLzyEI)6?eRbGi>@yf!a;1*@8`z3VPe06&YlA0!d5#&|6K?rKK zYe8LEmIu`G1q|p@HIjqS@xnsWWOR;me6>kf#U^{kzHE_weKRLA-Ez}mW*!3 zqdFB;z9$OJdlwBoEb&}%Qb5N3-DP%VZ1z#gpM@P`-$OefHZ)b+AR_w>sX<)Copu3^ z5`$EPPcYkWFzwIAvC^#s*ZYp-?Z&qNVSTFuOq!rjv6a#q70y}{!QBd9x5#fB^q%k4AbWNjr)ceT;?|sR3nP^&wf2XcW z%q#^9?weUpLws;VBy00Qst&a)~ zU{;rwQ*|&;-ZP_)c_?J+&a16$%YdiFviV+Ko3=@@MyGZ(=Jn3%zCZ!2mW8wCWPR+I zMhPmgISO#*SApABD2aO0t@8dhud+tE0|{R&%}WPMZ-rXZh4tI~au>?2AUy$)MpW>DjBj9-*Al9k9;S1~45_S5W;kgV>0bwMgbBoe(99AB7- zk|UDOY^QdOgj>-nKK1t?a^ZA35_Z$A)wf>q+ebqJ-Wv^uz7hKKUJc#qGP!x{VT148 zOmp&uUlX3DS*lnF{=wx}(zRW_&eki~56I4k68_>R@|O4@n@}mre`JZWZQZ&ryiSX^ zYbC4XzSb+Y*8JtjQ!IO2{?sz^3np>Y<9R)%?)ZVi!Wr9VawtfvyHS!x|NNLjl;N(U zb%>bF4U56}>$=@uhAt&y7^TDjpJmn3@T=trT=CVUN)QLd5%76&Gk3g?{99tU7 z|1%%GbNv>>MoFa#%^pl~&Ax@toB&w`%5iwN(8y2K4`jgC7u!F}g!h{mupPL7{aIEE zxeL#divuRKz*6Z z&HakFq%5CR+MOJkm$92YD;pqPZ@U1^`Iq>2Gfm=&WY@?sS z`81gww6e-qYDB_zVyx!~f~ckm@`lv)F!(9oqB}6jX0&Y7yVAXd^x%AlFvH8kc%Lw(?l? zxE7k{rwT6$WHw9m4Ic*Ld93gYmnAhpCL#E&U_=J|iPC-0~pk zkt89ieGn--cn49gvCm&Ow$O_`yg@j{h(|WNf;xMB3{W_JH*D*l~xNEYVg7ZOuaE#;n6JwNq@L* zsk`qQ-_e0&18flP=yibfB69K)+2I+gH*c^!=BdpG_NT*_QHb9c`)mG7l5r^L%Z_%= z-8?)%YWfy-CAnz4{rU2^`N-4)F^b^1&xUab-SAt~u6ld5aO=|ZxO@pbuc;x&cCJ_w zTV!3Ac)#x~9wX5O%m3}eG-$m79|aV0Qj(NjIR$S5JYCT^W!V^8>2t2fFU9n*`P>@y z>(*2mJf+e!iQ2)iBagvNP;c4Zwf>?8so*D|XBdiBT^d2_3cWJk=ir-9d~Y8b{&nMv zH@*yniE2ksLEnx`mooR@6D{Yq*}#wxzR#U>Uxokf?>y9D>4@$a?|d;gWu!dXIr&5P zP0rrf&aa(Q31yaQ4c7SwozF!ZtVC6oz8?3mpwGqka9ETQFh!1O7PramQ%qQcL^ZV3 z_}!K9-KVx_x(cw#6c1T8rv~01IrXurN_MuX3$!2?z3185;a3Sk=**RN3)!wU?9if~ z^1Y1S1DaRrFe@(~{%O`QtPT1w3dU_oaUO1^X*y`ubolXc zZ(~S;qVAhd!E61N;8hDSCmHG9*U(QPp=?N)){Fn+li+$xF>kzUC>P&l$dT}gClYcV z4m|8lR+Ri!M?meP5q!F}o*miQNlb#fp7BAA6z`&a z1h?}}A6zf^6CCs9lZHzj_k{t6xB|O&w;JWdWQgf=_HE}3N#vAa%1bH|qo8qs!URwATmN zNi^m;4&i76F28m^ueQ9rY_zPh{gFBG{?*EK*3A}wNw(8{4Y&i3%%1x@ z8Mrx|MCzlbz2Z7lTDVM#e;~1QDC%tcITm8{laIg+_6KJK$`us;olW*}Qpn}(74SJv zfS56VgUd)DjB#t%XaJa^{$>Y=VyLzgvJRV~Cf*hMZm?+?@SD?iwO%$>)0}_<(JI7r zHj<+9)klIVa=}s)Sew74?Juif3@^yOam`5)?=BvYd=SAG?}-96wvH|`n#u5Hy(>q6 z`A|m}dUt&APyQ+ib^?vrlt;O_M-)X*&s!Etp|D@CuHhVt!|)h_#+{V_$bYt>rJDy} z!glG@D>-o?ZD4BM$vtBEUu8)-AEnO14Em9EajtWvSYV0Z*;=q^>t!8@bwT;o=k3#p zv#=-63+zBxfikDj4t2{m@#|hiuFBQGjV*G6VEv)#Ph)v9vbmyrmMAw>2zOlx^Cjt~ zPZ)~IuZre*oX=!o2}Wbz3(<=Ht-OYoRtq+0py`(GrnAc*spp_p-7o_yqRSBL5z4-!W$6XD>g`k8;4zKv-QwhO zu`VU|CJY5P>Jm9VTJwThLR(Y;zL9~cmv3GP%&!Z|5Ytr_p@r7deXi-+WeOlrAfBr6~S>z7%$Rotd1FR7hKqxYOu|ZJZR) zt@!L_WF9#4JXhG+Zs=;^WcA`|?{|dhrNC8jf-9-`s1T+iFU;t68@ zBcYL?wqr8;fc-EXQ?8QF=Q5qCwm3UgV+Og>XvfbB(@pP=>6B%od1b=Bry_hd@TgOD zmnr0U>}6j;o2>5x{x_1&(;B`HuT)L2p!1pEe9E45>09`my_^%Qs)aagjP`tQx_I4? zG+IuD$W^dX8fJ${xBN6sdP^Fu>odB2V=j+t;q49T-Fak9n0QLZTJwjk&8wOC4E^Ng zoC|#ezTlTH@7MZ)A6{#99`y6|cTE)MiSW@cREOMuqaVm?R|q+0Y-v!vT`5cJ`UfH- zGsFktb32bFIS*BF({#Q`3|vC~c!%{_;yd`!!iiraxSwLU|%?{5Dh3j5ppvuUnLrO+~a-ofzP&`G$N*wUNNW2NDq z#!iwMQ0SnN$rji#{(2z2)97fv%BfVc9ZfxdBgndb`dxT*V9KwWuVPg{-{z-=?d#FI zznWKy-RBYdWB-Wbu44YjU=@0Ym)ATQGR7mPz5T3^VSB>myY<%{)2#G6qh*3`eV>PG zq$#|}R%v<}c2xG&Mv?#-e9>lYmmA?4^y+i)$!&bsv-zP&oqmb=dPP)}+iATjg^A;% zUDF_928GlGM1#f%l}$c=d}$oyrC`c6-Vb{IL>eRO6k4WQ z2NN{CjZ!Ph?1_wB=9PEJ;NccaR1Hy~Sfxxa{{;m3ZS#F0&A!3ngYxN-n?OVxg)AqC z@sxm_2s%NVASwG&-r?Dyh9NQ-Md5r~)N9CT23~2jA4)aR{OTiLeSM17Hlq2~D(C5u z`)OGF5cor|e7+U!^xrQ5Zc!AFP4NZ3_S7sv?A?VIfuf@1VMA0TQ##HI=p4MNYQ3^W z82O0QL1GzIV8gxMd2KbqvtWj1tfwC_z5I>ESV#n=-FGs4@l6geRXrq{6)Za=Z4uk8 z-2cdYVR;N)TuAW_xrg5nQc3X(%J2uETLQHWgcyv;KL6hzNw4dL2;Fdh$T5M+)I*hlxmr)8=>3~e2`hVI05G6zKL@uT-r7ED*#p@{U*21YU=mcN(Lq~HNXAVe z!fNxkU65E4oyeJ#`9KJWI)5@R!obd{{Px@Cw_i_Ru9OL{k1Rk)G*oDv`5<&{GPdV8 zi9VzK+%2;}6`rthA9Nb;IFJ&;GL*njrSY^}Dmusn>!GaLM4nk!DU z%+}!E3$<~ZgvBzjY0qWK2}DbH%{~GSFNl-XSZz!BeiWgJ{tR+hi?bg4MZU8;^h6D2-ml?1L{Ob3#WAO#PP(tWwa9myxj z7da2P)QA$Qug#3H9!=k1$=P`eT0z0|=?yyap-F!@3x4>-$yb+ZtZ9oj|6cIg)pw+K zYn+O)DD;1cOQoGGJ5Xl4c5Zc9;k|(T2(Q#mPlv{*;0@D#j(XyKUqk{mL{Y#rF9N`< z6r!Ehqm{?qqCG}gENrOKd6lg==IbUeaxc6p&oS^zNtN`0S#d=3HA-J>=ktuDpQO49+YgvRkn zM>IJ&{*iPJ3?=Byy2p`du*+d+cmyviwl2yRb(J>A-?}!&vxDn)U(#eS1cPGpfASn) z6Tk6CwILZ@jb38wVxclV_Yoqv5SqnmJ_>L+bY~4`rE99i_ej?NkjSk6iZH;|HKb`t z(B#P}WGS9s8zhDJ&y@r&Tb$bKkvP_ihpK!E}j^1_`0T*qSJFV2D##Yly?sRl;x|XHNpsgewV{D7?JuFeb zKGn&uIKu1lJHa%6*cx>r6y&mJEq7QC-DNI%`2QjvzO8hJUK@eVbi`Jsv8!EAXjuQ7 zRa1SZ|An0=^^SzPDbxQ{^uW{KvI#J0f8l}GgY%_DAK>$!8FtNkIzQUh5~45}0jO!^ zqUGXXLqEz74+sysTO~%*4IhM(CM$TJ{WZFe`n64&f#DGwJ{m;cS$m!n%Oqhnz$@`Y zl@=(ohD9yDpXmW7jF>yJCKanB{`Xu$Wr1T-1#@5v^Cw-sN7?cChn?|Z{c&FAmUK;P zMd#u}Y+bswT!%!&%)JS8V{NoQ^1hnxmvfwf_r9QADztn8U_2`v=YjGs2Qn)q}tJ9eXo}EFfeI>5Uks-1*?||}zaeJybdstf( ziBqxXXG8q2|6jxjng`d8dPuaCA6F{LV>|B2TuPT$batFETlL40!9w9}Pl$JXN}y&a zT%edWc0W8EbnYbA3w|}TW4fc`Dl+OSa<ia77k%9UwL? zhXtu^Ia|tYQppVZ^!LUjQ50u`M#Xo}F&&!My*w`|h==3W&Wze{i7k&Sg0269PDIf+ z=_3j+wbYA-?u~_Du2hApzA%yz^FDh{Y<4)7At`j21Ls(_9k_nYMfRD`Wra;`3_c9^ zs0J}$=-78^uasmZHglet2=4`;zkq2V9D|Az*WW{tNf%!*5>3q1)I~8?H)1|L`$v{y zCg#gL9lSi2YH#V{xy8yZlap^KW^2zk>7cU7Y2zz-rtB}D8~W@0 z`;VOQLih3VKe8R3tN~IUoOJyHyMVVRgkj-$>(LXIX`;KeOHO^(yu}f#3su(U_UWFo zh`~)8KWuE06|X;}i}w*0L1eyoQ;)T*^ZMCV1br_1IDM`mqU;W7Alfl`-J<;0V`S>1 zr#s)%U$|}c2Cj7Kfcz^vw8xrtF~XOY1DXjrHIYXmKn4rLRO-jZw7$muo{{u1}61g|U)GKKsLaWKHp@ zrOG9l8UdwwH5YFZt5a&nh)wHSdvZ*ad%P#FjT%IVo`i_J-A3^5k*iKw0#j=#L6A!e zk?J2Iib$%jilg`0cmBo=AUhVeD4*w(<43qBzo=T3ASLGP({$&YLBlj25rVr&PzL23rn8U&b(6VvZppIqwo3zTVDx)GZ zw@ufsQXW}LPhX8W3 z_e}nxy;UB2`tcYUg{q~4-6tr0FOTyc66j*;%ijLP=+hcD@{U{LXQV=5r-Rd<8}wv# zia@_hXrh1Bnp`KnQQPtZLMrw(@%}`qO;b(f=SJ<*JiSDg6t!^~x)9F-qxXy5g|L1U z7aTY?(Lm`4h&+F8=SDzTajjmdGF>QPdR04Pq_q){QdK@2dCz*EQ|=M>jcS!k^1Xy| z;1lZ~2f)3EIL<*MFrD||N5&z#N=xU)rNVmBP<_0h300=px>3C+V;FR++{TK5H0qZn z+C=EU7~r-dT%c^_W{c8tkF}A`DeuiBkFQFf!M3UVaPI@(98)x$vtaYhaYC?m-n-cR z5Woo;tZFbte38Fo24b6^Q}uEe{kbS*u69toMfK@gQ3x_k^%SzDLl77)$MEp2#dR*z z5$qT`N0{#?1>8>~Pi0(C%=BU>w^aEH+Z8;0-{CiObaP2NJHBUSg$e9vHD9#~ZqH=v zMAmHmM$q{eSy&p5uT9rb)sRL%S2lfgV_F%sQ#7p|Z=z&FW|VL7{OPpJuz=|X*b81O|c_Sx{n zFV~TQ`05s<$MOQ`Ce)A+Qx3HvATaLHynF^0FFO4uEC&4tjm{e}gapp1|l`%*8+km1&GHadVd*s7v)+?r$xE9J$-NmGr!dtmyj)uui0iYJdt8!|b-Tccyw#@|0l!Ob{AQ zrpRvxQw=mrKB`Ov%Hhv)j&?Y+ov^TF;dm@TuKY$RkpR81B0ojFYnl>}Cp3&1F9 zIYY+a8ZXydtrGAa*p1`AGNpq%80OEaEJr{H))ns_f;E#O7lg&C`ktAhimGNv-6MUK z?x$a*NYt6!J!^+?8#*UW=t>ZY!jBT141dK!NIM_>-+%j?aH=!z?%g|F<2haX=O07P|DhkX{9ekc$MW9WqXzqLvn8th^QHmDmt6O|Fh3%^xAhyP?^I!* zCu~7}q<*LPK>Bh~47$cTe?Iu=>9vO}|Jln`luYAD)n$QTv%$M3IWJgKv6u%O>(j}z zS*=0nAa-9%?JQ#=E;}dFfW+t?uGR*7fUwFd6>Gs*(4! zvJL;L<^>c4XzS~{Xam<1({51YeEER(jt_ZtQ3 zZ~PJ7k3F7xV4ZH6&+OmObips|NMb`-yVV5Pf91X|_ZH!vk|m9zZ3hic#n`U8byF@+ zA@SO;)&_BMsTNu(!WtB!3ewze`+SVI9w>GAFwLDJ_xbs6txixJ?oVlOyR?%qem{)?`Fwn_y7l_>h?a z|HIC$eid=C86DuO6%HNkJlr%Zjw=Mt-W&>wJ%Z&DmLHhE>Cb3kk2)%~v~rB_>m->8 z5lSO@FC7+d83l8L&1S1QVg&GI%)PQm>L0g_buAF7%sXE|c$q#EUn7G_}3G>`|Qmb`81MTM{ z?nxUG61n?&;2nC7I$rcy_wOyocO#@H=A?le8P$F2sdvY#?Z~?%_)jU5E);)D=)&Mj zmu50qAPf{c@K57*IMW)(A z3TsEDx&E-gYf013F8X^J)@o5f?ZY|ma&#z5ZZDTW8!hALt}a|CeYvsG?QB1OoMTK} znAU?G4#m#okLZ@hQ&8vEPh=Yp2&S*;xr=#DWW-t( zTzFt*P8JvTBs|f=d{>-Yr#H6pZSbSgksGuAZmWx}F|ay2pq!=c#c0WYIrSjX!4CHCVY{f8|1E0U@cU0aMw;FJ+N|-lOgI( zopMbB(_J9fKtvAbC8>?&^E%)|XdVfbNSO988daoLoXY##M zHi}+Xw~#XdET~|H<--d$;BJ(P$HE?CUMakzMq|d+-3D}_WS1ZLO?ZG3Q#01y zGmV`_ct7~D6+sXDE3R2fdZpT@Bsz>dPNNf9#@b+$_}XmnTxPA-1MWu)YC(V~;P3Ln zUje|jp&XA#XG&Am$KWLBWCfJ{GUWN=z6-V4ifc)i75RvP>GBJvn58tGo^NQ^$f)Jt zQ0mL@@;i_Mu+vj{>ucP*oR04Z5=#c9tyf{~QnhUtubhU5-(Q)Q?)pbI8uz^S*JVF| zVLHw5=>W8wtG0m2e~<2EmixY7KJOwV&;dj^m7XNfUR+V*2V=)&>ANX?T4X$?YvNU- zEVShbyBV6KcWbAW<-`Y|*&C9BE7heRMIPq*luBbtIqq(hjhERaxk>DcGR0(I zaFeM>R`iaiX7}Rs@T`CEUQ5n@#Y&+*+kqqm#`f~Ni#<}gDRNWB)vbqtUyR375ij|~ zXxpgk@G4OX2dn!|Nb0r}31**vz6;^@^LWA2uJ*#c!);|D!Rp1AasS7K=o1Gt)UMN~ zJ{q>bLBS*XW8Du<-%9Z;bd1EWeyd=iEvNv&^ZwCxm-Y$+jCw`&vKZ7^fw!tJWtpmP zvur8Go0=bR-%EE9Do>zy;#4hw zsx~bLKFU;qAATw24fytym9?`ZLu_fffxMORGAsK{6p1x>JS*%JhrG;J&JTw>q?K*d z)e=(QSAFL?)d&NhP6k21`^_7W6X2FrQQ7m4OkArMN`;l~egSlm37vsvtC+Ti4^ zeNH|Q948~wRhD^wPXN<2iK>%=KqAHDc`a*8M6#|Bz)(F$(w$J|yuKejM@2_~g(GF^ zuOeT-)A)stU+T7vF6%Px*+oz!+3hb)Gp(QzzlWY_u^>8yqxd}syf_w)&z=^GYhf9F zXG>LEG25lR>z7ohprk_L<+Cq>9#_S5@X+2Lki&O>L*9U0dBBzgRfdMl?CaVbb(!<> z61dnSSqQP7RDHE-pTL9-0KW&>(z80~E*9#aZk?@wtgeJMb~U6a@~KNZzSlw0LCec~ zYv=(CL@T-Z_QbZI;-j}^Dn0S&moWrPM7o1fWrquBF3tX+!rA>gl)(i3iRf^beU&;# zqe+c~TXS<3b|;52WG$NYt+AnOT@G&ih`KzgnbMIO(QAI+BYm`2dT2a}g@?h&)Ys@) zjv1H-Jj#t16{ah=sv1@Xgw||)xTLz^l2+K)^efm|F!R($YZ*fh(8W@SN3@-fNqiID!FT@}Oue&lb>K);QA)fDu!TdDW&d=o=;K%ngc21!#^6pUs{g_Y ztmcHkbNaghcy(yMLUHi$bKA`pq&XoUyQ^GV(TaO|RKkY)RI(MP&cw%){mvAl-eP?s z=NJFy*s=8Z(eWpl>8rwzFn^aF+#7i1Y!C3|!oLU;*b(Dur17|n3~J0}YCdSaFH~H_ zHk4FzYeT-lV$auWUT_vi4Thku>@;e%HlZz8U7vFt&^hr}NJ}(pbXknex;_=&nY&-r zSXDPA!tzp1Hz%fUEOKW&wZ$plyRTG$!RO$ON#s%!g@ovSX8i1jzO8RY-^+Q@wyeJ5 z4nHBQ+1e1{um=@b_{Y5ZW*p10z2m;i9Y~sWoY!E8;?|3q@oI%@xDm8pSIo==6jUfZ z|HaX2ua5ESz4j9{s>#w$MCYk$Sx*6WJVHj8^SrJT9LdWK3?!do7LqHc-8bWD9r^V} zgnNDCG6G{yivhB}f<90eea=ikb;}mo<(c%xc=+8?eD~6(`#Eu{#`!?5`B>%6wwKAh zhEGAb?BAb$8v92MQ)YCWcRJlm$%$4dl=B9-vGuOv_*U!<6x~?IZvJZ?dUO3ZBdpR1~FxIX5ykWDh zNA)rV7Atw4+6Bbo$zfw`O!LG*T;%w7O%Fy2`0nR&G1~wo8c#J2`SLaMmjT6^Q^*53 zy3si9jO%XI7+`@1)^#w10%C2~wZesM$s9f7_Im@~)^oqhd!NEzS#~x%PS>+ z>|`Jl_!#XT!vIXA!54e0xyroFsfP49D+m z{q;k0?>}>%n%=N&l{Y&R298bL>e9rlf{LpFi2)i0>Iaa0@raem$QTTYS|AP@P&EQU**fW7&Jq@M;xX_l!#M0hyA6gdqDD}L zhgy>M^OlF&`jeL*PFc2)w@5SqY{xzKi<%Hr7E87 zVzz7zZM3&gK-lUuT}~?B!OhM&G6fh(J^TF&PGHk$0%ko%e7Bg!c zBP3r%GkHm>Dx|)${N~%D0cOoa?|H4j{WGrVD=8%Qy1n@4*FesfZ!Y6`z-SG%vCnUu zjlvY0Y|A0{^Rf+)UkCt-^lp*+#lXo^H{0u8d<8pBKbT&v(_BV4F%xkar*m&IAWqum&D91YlOI`@H6N_Pp-}9kQ0Z0WtfuH6v56TKBAFLsuZKN{LT}i?9~SIj_4fR94ltO$=R?lIh2+ zI#~_7FEiWtk69A$MDovnl-iA+PjX9_O6~05mwtV%!E+YVdW$e~VMeqi$l%04)PKO& z-4)(_AGxYMQ(G)(N2hk%Ma3$W2d8Z1dryDrs}&u}{Q~s~$tjHtokw+KEYY~WO=cQ| z2i=$yPu1>-uQ|UVy#O(hZ4W#dGUQpt6#ux}cEcBw_=F3-Piy_%#(!To)~X@1iBWS+ z)erLs>8vKdM%lm?_r>kS84XEtIK#LP>8cK5CryCr7$U%SD0Y9p_Vk`e9}tt3f9T?H zg^9GYfx?I&+0yCKuy4e1`O|UKY9WY5-=bm+$O!LtS<=@{ZZL`-i4 zkjb*g?&}D|V!s{0E;BUy+-w2O|B|1&pIw5R`z=lGU1*QHDM7w95;u7kgD)ivVBn!( zY9BbSzy8a|(?9a}?n>&U6lPiAiL<(v@Cydm?0M9_33}w_PUB(38g>r*`;(g(U&dhF z*I)bz^}_Vu?OJP&jkzlf+6I_MihO@H?Cn7-){q22olf|FLlI-_;a(NC-JQ!Zi&sRf zd{AF=^JCxAZAMDtv0uK4bM9ys0Dp=EsywXl#n@7O_B-2U5Y8_u^X}Af8rOZ%xz38M z#8@Tng4>~aEiN5=Z+;Dz2w7^(Sd`i9%cq@K4+yhrC)&hps|NP%lZ0F zuxxtu*P4>Xfmj=&Gnfhu4)pK)G-}%)=UwhLZQUkS+3NII#T> zUA^|A#6Jk|WhUGaP752);y}$11t6kf+o`-SM+cQ$*532EyXe72t*TQ)P!6t~BYHTK z#Gq28-q86w7d^C7t;xF`VSlM{*Lr^*KAFFiZMmeolQ!mWRniha(~jaKvSF+uIxrJz z=f2_C;2-M^7A2o9A(&t@5{=F3i{QsVQ=@5odH#ZW#Ua&o#A}I5$UXtyL3Dd(#jKt4 z#YXFBX&=rP!aVm1?jkU2xB#W3j!{w?Vx}LN8&*sf?{Sw%*<{( zT48ljbW7|q3{3uf`V-#5S$bIdfvTCGg+MJ{@#!$rYWmr*A+Em&(PE1_`DbI5E=VJ|=JMz%}ZoH4gl=3bS zm2-C_nk#Cu)b9jWSpC|9@nU{`Es{1caB33tR)DfPXyn*EaUDG~Qv$BXsX!kFWl<~d zFKkND>0fY4!fiUu_1JeRI~QwhFu_Iu!Yz8z)FKqjs~P)`EPFBb5kMX}YZY58zwE^Xnae?UGKk;A1~&1O%Us})euwGx8Om`=r|M(};wc<>AKFg~MpX5N9} zl&ZdDql7Et%?6d0yMs92qlwZezfd+febxg$ZdSJ%6qwbu}_I$JDH!|F6r> zaC1-(phN#Kl6F$}k#1CAz<(ihpmk!>4`Mu4TV!2@HO57V;h{dy4Cd-&Wm(O=%hMr6 zLcN10h)63oq7AmmqH@an$+lKa^H`r~vHZjSBG|j?V}3uDQ=R?n9O4t4dxr(p8Y0Bo z5QI&XR)PGMkDGM^Hp7DRaYu$BF4t!Z?V@v6o_lJ`mp-Z~hIm_vF^y9WuZ4u{YyY-h zu>gqDb)v{+?!T5{*pOxgBokDzRWwbsIzUXzPu`?z9U_c_hht9Oz`D;MX zf|SqqM%<0xQSOiAAsMo~G~HTE1y!?V-~>q5QEO(>*l(6x6W+W3$bi<>mkX<}$3+S^ zSZPoFYz|IX2oWyk<}b$t{cg|{>}dP5q%WnkGM@|MQ2X*Y2Q*+5W{`2GB&h9h-aE-e zE#x(5ThC_;vY#xZ6L#_GQzQv^n;J}fP77<+Hly#fOg|Az;ik~^Hc|affN^t41Kslo z-l<@hSBgw1BX^G1j zwmJGohFZvlhz>eg6%r4(z5FS+FvqnC>e4XU)+u}se=psD?F3TvTi_m_5Bxc}CM)J$ z5p4KzR2WIvAJ6W+uh_fthi$riLrXjfbWpmf{Ey6}o=gbTZnXgB1zU^9TQU$#N(jhy zMfquWqG%proD1STBfWBR?mgOs(K&Ph+@umb4~1>;M4h?im2O3zS^@~eh2YqUvp?EB z-#bMF;1?oqzx1oHTl_A&XTxzdzYtP*MpC~`hZWX&89g1WH_g@Y5h$)Dq>qu;f{g(3 zA-U81L5+iZ+0JNb3HDz5PeCShq(}Ps3NWn1K3yjUJ<$jTnQ4zvpwl*Y!K+T<5?2w`@A`uUs|J(*tLiWhh2n?!p`9c zh(ALG4tKY;Yn?UQZQ{%VC+rUN@U-$b{n7nkc0scy5#LTvQW-??Gt=+dguHx#pSaf3 z48c*G`Eswh3qE=KbTX949#_v@zUGTOszcXl;qz?dyk#ZI0<&M=k?MLFRe>A_C28gi z*H#;7s;EFt`-l{%-yay7Djv1^!!~*M`=WbR-$kZAwys4ai2_zT&2qUv#(*jb-?j=} z8L?Lc|9sJ4Tzc5{3?#vH(xzlLdF~ItzSdoTz-+Amx!0tbq zWAw&eAvWD$#!vE2i<$1uHQ*Mx_K&6>k!aT=rhR&&;jIjcEV}D!*|U=AfEKweKpOc9 zP6m|3%)ZE_cElC(L+oVrM>B|zN1ww zpM^ks{LR$X8$Ui=`4wX;bCVmV_>bmw*|)4unJEXzZn6L?*$iB-xl?^8mnJsqB<9NT{)}NK!9OQwy-o76gSl!U zoJWv8A9BEYlOD=3c%=Zk;L^pQ^bRF(Lm1D(G@7lMirHC!o*5tVG0k-b)uAmFr1iR;)o+ zC|7`s;USqF&(X>h3p)3Y#uh>ENaaaxw_!pv>UmCkbn_^J**eRo}20hhQKYBBvxHP!GZJ6p1DKq4_b+FWnfK=nM)4x9J6lArkUn2}?5`z^!8PnWX4`Wa7dAhyqc z7gTBuy-e4n>PLwQ6vYQ%^LEp*yH{V}2C`M-f>9;Ol4Y< zqVGvZs_y3{68_p}Eb2NqC$uCB)++x#Xx8eB+yed3s<~mf)Q#2mL7#!SvqeT(El;)( zyNu^~s>jMR9{s!`)$OKYa{5Qx+Cx>SST1aBEIlvd+kPw@r>i5m2n{8REP>d_uS%17 z1B|N1khWD-4$eghPHWCvv*{eX6QCD6gsX)LD)kluHtlenHVJdt@uW!*FWI4UL5pYw zWpGzpvPkAkU*psqowo|}zzl$P)*3w8Fo0V?%z`uy446$3S&c?2!52102gSWK(y>-A zl-ytSTy$o3@;)UT{4rS=9wi;vqX2|P*syn#5c)_(@8y_hJgsymaY$*EJD2BWK=aXe}jctUL+MDbhl0=Jdu>&c4fw4g*CFK0*IOdiG0p{He8dkLbV zx|E;Cv#4p5DJAQ}`0nyp(XqVewi2xuq%ZWHaX@&iHs^B8F29^LJmkD#>?f&sVmNfk z7g!3eR`%?!jbU`^6@4Si71ao}+L7VVpX8=#BzMtQyCW;$CTnv56Rez9qX1{MkSlKS z$#>xCK_hO+K08erxfCu;r@e`l7f$%UVvRzD*2=dvUN6`~z z#DGoQWtBs)C~U4QXQ&yX)c5f@V#Y1gKfQZ`qL;B5Vz=@`wkF#Q_%5M;G(Eof^`UrT zZqq*U%;_eTe-f4Rhy0#mMSJ7MjaPJE11;nGN5#w9FRw1p6}0eAHu=T;&}N{5W8tY8 z(z@Ca!mtr?{A|rT`Zs(ZgpD>om*1CQ|47(uL=Y$lA zsZn9P)_R$$O&+l&gJCnKF7M(3WX*mjJrnpnSETa9x-vW;=xWV%k&sNsne^g}tN>~z zeYR1u-Y*+7{g!u*6G_~zE?P=Roqj7#q5kPc@3*7HD|O@VwITLl)>@|O5h_~HZzfDR zWDBBE@zw>+(LkH*d22hz)|9^~HXE0y@GFD|T(S;PA%)mYInKS^(jhT5!HI?SOiR?% zoq*^y)3>qO6>(2H^J{yAnqG;nQRE1Xl=Nc^2PoL7!NFEW5Gu}9_P6J*_l_3N>fNTa zyV$u|nLP7c_C&|j`U8cnclid88C~?$nTYafvorQvOfZwaVNQL!rMNZL@uTEM*zKKsGaa^u3unNV-t+&zSqF ziMNTu{mEGApXnvuP5gMi(51q=;|&iBEF8UmM{zmlXuSgE>ZjH+Y53Iwl`6|KXyE; zPytb&6`$#4xF2+tvanQV1u`7-s^_fa<=YdTHS4rVW@iz&=Fe92A-LRpyGYxzqVMiVW-)4sBB%E{(yRhI6?N7OGd|A~NIsMculB0* zH-io1=P+9M$+I@%7yClaevPg}GAurTJro~pDMQ-7lPpTH~Sx$ zHe88ub9HM%8($t|HBqz0WIQ}IVti&$Ip%D>Z&V*OI0-^Y58jD|m0<26RYT1ySMm)f z8sjS8mkd6gT}o-CmxP!9##5sS<)gRZ=WNiQ4$(o4I9{QJxJN||!77ls{)7H5@esR+ z=vY#2oTF)!SDL0{LpEja+o|*D(t>B=T0fNN3R&A+$}UvbNiq|<1fZ_@`hi?IPgi=3P-Kx`r4%GwAJo{=WG1;OwA3bJ8%J9UExWkipGpOXW1>zP9MJWRGBtMFqi6O z`%hVuQ~{!GuPO0EigAUB;l?wqy2c`QzA9m&lBM|9**>=*rVPw5y7=BV_HCQEL-$AL4>9lao#WV|9`cLE zF+#6Gf^=BrFp#P8_!m(nW6RbT$vrebF9p?gxsaYabUwEe&h1mp%LuX ztZ2bc5}}pNUrNKCKDMbeQ(w9^cgB4j&$O*58F9o5YPaSae>W-JsC%QPqQ1%*H*h1J zi^+9jW69NP!@y`IJ?HPNNofaJgII|}VU=a&z^r6L8!U2H_Cp29vsFqi<%Do)r+@eEV?NV%OkyK5UM?-45rww`DU=0-O6~ZX$?Cq9Nw&Q`{lcQMZ;?eRr*)^M3Xpk zKv|Y&;tR9_to1VigFj-yartN3tb@FJ9%csWpKOxeoD z51XH?L7i|2@z%cizA$08^0DRX7k}#2OLKRAtegq&N|GKB$J#})$ZKSSQKXEI^Ve1h z<@{VY(061ZvP>$5@+>SwG~#WT_Wsc*{xL8#dHz~gqCfgxj=90;oog37tTfsReVrP# z3bdi|M}?m5bTojulzkzSTZ-0JI5BtFdb7$KD)oHGbr-Sk4!NcT;fToo8YA4-y%hv; zgv?2$jUVboz;93)$f60nQcHGmp8JgRTUu)t7MA_Y^EY-E=yC(lLBF=R8RwI73v*9> zj894<@6<$A3zk-^(~T6$*H?X+ak$%o?~0-F`SMNn9(F12hJBQXw18I4iSa?sZrSt{ zerDuBm_scSsDo-{vor>SjynJ?HvJSyu@$6br;`0vJ(|WpRhDNa6 zBwc?*CvunW178|`eMvR_`YbOh;@DF^=8gDV4cl@hKHdWpS9+zC!C>yim&ajRf^Yu( zd1P8mb8c?*-tO^GD2i42VO|Mx34D3$%;*zMbaegIh Ic=w`E#cox`CaFnt#~3J&XZIdXduQv4(k1+&@?9`rN#m!X2sHjHX-l$&CnKpA%k2O3bf z`o5$uAwdni#ly=p!Eu>mSX8?bMN#ElSL;miKuBSu#GTS~?EB+u1r_mu=-X~knTjE( z2alSd9YnOi*l^>?=3};eKmv$_M)R?b-5FPw3-YSkq8oAEb-tbMe(QSN0y*j|=97rc zyZ8%o1wG;J8gW);GhNb#%FLSYtUli0`~!bG(&`-C$vIxN^yeeP8TzR4%9V%4pbLeu z-*WdXHJ$ouA@*l)0<)sr)$FGjuT&|zaCJEBe2t&9y*27NIY@dhtUw2S;Wu`KkzSj) zEWkBuN|GKh^2;`{lGKa|WiR}ueA76+3SnznXHnwOb>l^ERddF(*Yw7t8+%X~VHE!VgBvKtx*-LLZGzgBdomRP$;pDd&P`Bjbgn+JMlVwFU>|JKbWdb3PR z-#w?(P2_ojM&=~@Wi~0F?kn)eFn>Z6i?x%46uLxfXFhK>ISzU$B z`ZV8bQw{VlvYDj{p&2QnXSn}K8T=pL)_>^#i!?+}$rpG;9RRZnSbk^_DLGfO2=9uS zP@$pnUw`OyuO~O7^0CnWN~quu#c0J_R0Tod(_hQK4{|;_Ko!H)`Egol#kO#IvY}k; zx~Xy%^xR(Dh;}1LymA98N3G9rk+coEt+e;OjGX1Rj4u>-$lEp#nhX!>H~IQ~+W)-_ z{Amy9eG!a{y|GZ0gHlMAT9Uj(7McKjE3axFH1Oxo^uYZBZV45ah!6gwkx*%Tw&+Ew z+(cY&;^d;a(7>E3}>R9dr_}m|rI*e+UKa`+8 zH1*9R00x^;VcF%F%`^QfZ{wCnk3MmB6|zPhA*Q<)ts`wnvYSAPkaI|?*HDbpa_xjz zpADp2kx8c~wr!!DP>de2vN$8h8VTlaon_FIj4hvKkvYdzIfy1YR#$aK#ls2Dw=%5p z3~BFANp7hmlUDERn;CStg*4i(nXIZY=j%E@PwU@-5mZ_<9%;ky(-y5q^ay7e%i%zS zhes`w|Iuu}F8@|lUelDsPyprW*7p^*7iQajos{)^O+U(goVZS4!*zuRYX9dZ9DDZX z>JaCaVn;_JSCe;XMLeISL%p{gfKYWr^-@sElFqoHR#i@5Q@lu1CmE@%RMf`WSQimG zZo*T}6MCvAdX`H3F)*4X(iQZN#&FvqN3mDZ8TB-;YhU;kB@1L%Y>c}Mm7E+QuGF>3LoYEa4Q{Zplj1I;LWJ|nS2QsOoXGt`go(;8{)FAjR zCg44yw>$=FfO!ARJI}E8|#{%&tv3ZtTeJk|}ED z_g4IW1PgmJRTW~B^u_yq7lH%!A|ZoCN&PR|4`|`s;{dQwumxx-Cx5P3Feu(CHj;Xa9R?XK0Z0bwRJ+w_m)bS= zEb?D+sw$dNrEIfQ{Ajtw|897JUd|NeG*L^u{+q2=>n|ZaUC40LRpMuTVmD!9MVw(^qTS(}&A!E-38B~mwLbN#Q~oc;y|@||<`!E|8^@79>1Xu=g|N$q13n#q zm$n{B&>l@?yQH)Ue813WOvN27o|7ajyd2XBj`W7J95M2nqgT;K6qw$9qZ;Q>~51GMcsa8Yt^4t}Lu9MfYt5>x5oME9I(XbaEeRr*oaeeL8 zb@O|Pi~QUW4|AfPpYf{|T7K+v;ojW<;jAM?`FJMoDUqS+fUuJ% zgTZash7m9^@J8^SI#i}12LJiE!vv?(0OEqbM-S_pFCA)!_g?XPD^xr8kZ4jUGhqE1 zTVyE~zj~90pm2#_IlqqGM@JOif4wnk?%;DcN3prpI@Z6vcA8`= za;T-Qg1A#hc7lDKCwjC3xl8m&hkrD5`y2-GJCB&}_pMPD-Qnr5r}m^}gU~X6)>E{x zidujS-CoY`Y3v8bqA9eU7tUtQYMJlw}#hF2M?SBNIB1LH*YBK%RzB_1F+xH=i(s9 z%P7y1w-(FZd{woom=~KBN^Wam)-(l$*=DbkrqhaVZiV`FDowu5;`f}aK-WcN>WLE$2Et9u(I2G;qzp+qdxd|PxikMx zX|f19SDv%$QjkAGZv&819DAsLd9|4Ler=!l`%#c7z}7gML_cksq;fd;zeX@i>qzd@ zIj{C>_6x?Us(nHBU$_oZBs&xJo$<>ZfJMzv8?PZ@Bvl<1TY2HP#pUJDJ2llj!Hf~L z>dMIedD_4QutAEDEmcX$-)!!_l^K7N`>w4GMn)@Bo=)cUsM2Zc^YCgQ#5r4gasT?= zYHn>?Ckf>VFIsOuTNFKf5s}rA3@?}4y^ZwM37pERP8ZKI@ZnM&xGm4W#|(B(C|uma zG{B`&vnKeR;4OUFI1;rlHF#5By)FuZhU7o`)R@*6(S@Q;f30frphV7G1rhH-J4s;1 z=kT&@#gA}F$_wg08XuJ=>MklaU@FeV$%+Ka|9%9rKhKs#q_K+{uC^3K{X%wbOMH+H zxS=Z5DU&N%@Nx=B5(e&~mM1Q@<&+fi;}KW8+Ny{usgE7y}4 zWvwd<0EKSAfQzUF1iLjvQt@q)#uG_$;nZ7g9MdcA&utuTX;XM+8cqlc#BZ1ia3`F_ zk&m-RxD~`y)KT2Ymxv*-33AhuOZ*B`xP35_dGc|U$T6ooQyPpU641Fr zl~vcb->Y|9ZGQ##Q7X6QxC-!B4Eph$d47tL2b#yF<7_hO52^2ARlPsSSy8^vHo-j! zu%q}oy?IqYxCicWmI(c zcvSJTkQ>fGud!MB%=K?C& zwgyqYDcjhQ7&c{91=BrIti%^wULwW1TrZup9wuak1HnV^>o5UFa7B1C{NsPmHmoGs z3eujE$#XJa-^;EL!f`aii6UQW+85|})h}53EooW3Xcc}p4g9sm>~(g!g35;*C>}1p z^Y}zqUp(na;CV=j{Y5^V?_b;x|Iz$;6o2v+l@tUxs5Q^PKce0sczn~0LW1(zxz#8G zZI2FmDzfj?dYtyAYoaaC1v&s-pnZ%k+Y+9neWM`9E8gaKym(nqRW1GShegXP;hA8R4;Pq zxrX{Azh$x{_Kr#hte2xx9Kt>ys6pDlbk5QZRO~LJWQfNk{*7c18{8SpM@(Fbq@u@_ z?P&q{W9EG9$@#!}`d}fn-mVvQwwDK`9oUh3!R`|Q)o^$}*xA)n z&s%srik)%bikBH%>b&bdw5ofi{-BzAKKx7Tl$XQ_dFTbv@%zLinDFonJ)A^ITEvhO z3;xmgArN>b(()D2vm2+6f!!@N2)hUvqGC!)H-!!sN^ ztjo?Wdz1EF_0XNPUq#hdd6L`U<<_6E2%>N{2S9yl;Kx;4;QRH>h>@$TTC@NNG0NHZ z2H%{e08LE9h9L+dv8u=J=ScKFozpKD{r|^15nWl zeBXd~h{9=Mrc=7i1Dho4@W$0en>vDokrsxp7NNd_avTTK<-4OPj~ZiTK)2yenCUhx zN(xoVlB_Ts_`FGA>_b%?VZr!{aFoJTru(i4iQ^eR&Y@q(1QB7+S0{?RZ7ei-p8*7})K zvTmAX&}rAjjHhhf#&gK*A+q7sdhOyoV4|pMnor(4Ef?pze_8KNi_fQ>d{=?3X)J@I zym(EqIK&_DMQ89*-j2)?(`Wye1$T30ywa~fz;Kxvzp;dSm0G{er8c8DcC*Uym*W3y zrf|Gc>=&O=H!+FXqrtURIwtiaA&3I1;&7l19=Pdkc5RgOPGm22Y2nXc_@BHP--%96b4 z{$oz|p3{Ce^?vl0LA1uE8meud9>^PzDy955PWNt|wP?bf5IpZFe9~9Gwc|NIdyBub z=`xXjaexPlXrtJ*;(e_u0b+rLscJaf$x;>}G_!Z!FtK{=BD;*Pea@w?fNf_u>MbHl zQ7*bd+{3i2YNDb%zZt#xuDK1$|D6l%x16g^3u}a-5f`cSfoeqBLh}uCot2Ec)j*&} zRb)hxgu5(bk@pVu#K~yhoz*S?5tj-kvkDU`#&_P2>xCDKV`DwSn?mYuy8emk_c-o= zOv76qp&Zpp6V8@fMI>17vck{nHeo%;8~USI4@o`XFJn&~S1duO7CL8Hn5*%yneMqP zvB)Y?23pGiId8BRbtLxwY>%DI&3;o6lKBmW#vde@k>Fw0KJqdVPQAi~1zoW4^=f#C zE!HD(3xz3d?tNaU5FMe{SdSyA`AW6}7J+~zhRV`!EP~nhnbxSj^S5k?1kF(|u#Aw| z!;??TP)C=QPG$=}z)+?|1191-3gJA4Gj4|Mu?WQZa+~Iy)^wVEH?qLY8txk?A(Pag#+w0}A?2K#RZlE5l>Cx1SB~J1+t@Q-uT`u=sDi*QaT0>KN0+ zPT2MGQDAPif*Lebj7hw&j~5H<@0LZR9Tw9PdUvQTYxIJjt0&QiDh4$^(M?OPo z&;%d%g<4R$FKt&Wraj}_ure=un$WC+N$1|agHYbh6?k))y|hZ7B_&hYjigCdC%P?) z?%wUw9#vK;v|vA0Pgpbi4{qUPBS&>g{g9g>`Tufj<-uV^)%P`?~sbya`@ zonv=PuB+bJYh~c0JaR|lbp-&AJR2KT{>_em4{xRg;)1%!%ECpcXS+lJb$kE&(}jaJ>Q(yNdei5h z^YVkoo{)1vqo@=ey*B@n#B2xd`JK1oUNx%;Q=j|99(@N3R1fBURP6x{AzWJ;&V6@Q zqPrs|=hH@zDB-EjQ;V!sB^uUBSaF+=ug?}tzuow3sOKhKoYTU7GfX^8A>{pLwY)7C z&5km98M70#bTwU$P(*~gdHHT%*~+~m_oe15@57iQ!8p;wJz0}hG(khCHP8}@B-hSW!#N-f+nWS`_8A5Km zHOZJMSG}!w*i2rzU|kt=qXfE%!D$1{SK$(#_!gjFY|g}%B<49(*Bz7d@v)C|)MdZk zK0y1V?)))Ve$Xx8Jy>~w+4Ud^6VU`sVl>kyvQ7YBY2KFc(!S0(HlmGf+-&;R!&0b( z=G@yvx5Yv`hWqALSIiOj47=nlKT4t5E~xHMVqn4>{?_FlxPUHwE5}s+D2ZRmz0F^o z7^$OaCBH!17jm2F1U`X5fzCJ+vVf}W&nGKlbw5w8i8*H-#8yqexJ>>l&lsP=_Ht0= z1(>yoj;u{o-~$@atHSCj&(qqyAweG)h==BvgkYYe?rGl3``cFWQJ@c)D9p8?&+Ejj zT)EJq28Xb+4#sRDR)m>01cFRVuV^vBn6w#7Nu0&X*-_vlGJ?>plP#DJQY zex=ebC`a4){-av_Dh#v5ebNfL2^&hV+@SK6p=HwI!=Z8!EV{}jZwR^^ zralIAK=T?;iwlUKz`ua}AU`i#JiKFD{G7R!I^Z>nh`d!5sy86Eb89MJsS37HKv#OW z!(RsU<~L7lTP4G+1?1FccW-m()YATTA}_D3Z-^cTXh$z~Mgu&F!aAZEGEjL^Mh9X% zo;~JClCP)@Bq_lwqpNCbVg$6mJPTEl0;KVbPRU^|{gaf8206S27QIW4)9$jC2HJ`G zbjdc%wa)JY?B5P5D|?GDl6^Zd6oos0k!@mmA?fa-rmGD+Qbqli;qL%S*E(tW2$LE z(gM0)q_P7BiA`oqy@tQKZ8yP&z|<(w#Jt_aPo!UpzZhut7k@43Pf39v^loASPao&4 z(z;+7kX`(}@By3K4s;5nnk^G=0~3&P-~|$B6F4HuhRg7Cf#$>yc=xdv^^+^q!Iah> zsVR(u(hq^){WsGh(}PDgClSjx$w)jCL5sLr2y_s)h!(hKo!ok139A_0s)jL%oCGDc z!GXgD->Zd&ZHN}@0UOmy=g@%svQg1N}z%hB5Ki<@Y-1tR;Xb_I85=2&_5 zkRzh8Kh8bd@2!u=L3|os74Uhnp=3$s)=%ufn0zyPTeYk*Lp=iyN(CN@a&rkRU^TcD zlsyb8UE0Ov1mg)$D1U^iIKBqn!5g->-HPSgSqV~Zn3zJ@fM==#nDaFNUR^QMOU6gb za6>YW94yI^G5pa3G{J-d$O3k6Q8443u~L6GotNmXI%SJs0} zz_a*iUR-s{jR=V>ERGc>5szf zoFhFa2fW&@100{Mh-w+)*8WB0X>F4E9!=5K9bU=UTDX?Od?(TK(_iK|IcMRo*6BD! z_%wz98w+#?AnnRuWZhA+URH!;g|l^Q(2ZWg-e9JJ#8pw8#VUV*^wL?Ga(wJD5ZtIZ zfQWG+YeJ78E0dmuec~!k%d>omw5?@gw8|B?^4}?7&`Na^`!ujIS$;ZI21gWA1KlFe zRS*|3QYe_zF=i<<-!@Z^n73%|TUD!6eHo@eYJWdIH^L{pta5DzjRmCq%Ia)^ly|&O z1mCRSA)YpB(<2YA`EI8k{H|u)p2@iZ*W|~&ge2)rKav!YYw%yls(rljQ?05g`iIxK zLY4N}s#;|}An$Gr&n(<-T6h9_-|N}ZOr8ZECjv`8hc%du)X~SeHP2r)VIpzq6)Xha z4d467un(2X+4ibr)yyG7VTJKw);vfgkWgD?vIQ_tY_*oe#8-8F1(N zv;gFE>vZOqZv1xD;)*BZjY^6R0!fgC=_J4#?|_JRzQwtfVCX-*P=hrtd~`2(wY0e5XGkwEQHyDX1{e z3i$9tC)yRLyAFt+t_wInV!nYeQ!TT+GpK?ZXh^{uB0{FK#{nWqf`hw>PS!F* z7oMj2qlQU+gp>)g1<9B?^$ONIbE#Z1ynzFobpG@=NIF+Oqq|ido3A(qv& zFmT$aj|W6m3uqX3NkO*n9~!>Nv%U4fC@qePi2NGHt?wPa)79MAny2zFtC_Uqb(Iee z0TIzhPyJ@So2v?q=_yI^8ch@gObl3o5x{?myvtDD2(p^<1Cn}X)M!doOjV!zKN=C( z<@G6llWt5EYG;`wPaQ;+bA(kiGCdz^7k_$ox!CKrG{P}GOXtKuvv$U2A<{G_jhEtluv2t=#f;0a^K=I%oRin<3%V+CsOd=6gHqOHa5| zL{En)8J?)Ab$xtwye$P;nf|mhAmD@@SZUuCDHm(X*%xZ&ELV zoM@HMuAyWMxcM}9SxiO9h?J5tKTJv?04+$Ua1OjhRfY#MUDM})Rifz9YJBfm*QGjW z$^8JBgINbi;5Y|ck)1OZwqFz3miA>bwm%RO-d|jF5*G|4ybT9;qU5?hut`a=vphw-MeLwG5}1& ze;y`3GEBa2u#+-3WKNX98B*yxmMA8g@z|6Imt!W@w$=VpZ6CLr$osKf4|}5;H5@6* znhoEWk-(;O8{F3@V(>a>dxN{FU$p}G>`upuwZoQSTTv)3+`B@6V9XE$zUWG*F9SV+R z7}kMz)4q>?}w`=aMU@!}> zgOJIYjl?;Mf%cq_Y6xzkTknd4Q(H=?e92vctzyV#^~VXyewf3e{p^1UprMn-g@zN< z4^S48pQ4OU80~}b=@@h&4 zYC5Y^5jbVhs;opi!_S7pPg1q*c=9r2lB{IQ{JPm@RDQYiIbTfO1T7|6^9}>@$*kr1 zka=ym${-0S<+6(oi&97APGH0@PSld^> z`&;=H+3|=-;Q|PS<-|tPGqOrOr6v&SK|x^CC|=V1O!j*yX+`(!A|b0h`_nN7|N3Nw z8Fo~rWT-YYkNf~>{d-_=u%(5l+m46(OIxEHR2=n-LIZ|g^{?VM{N1&+! zAQgZ}kPE&<<=Mv2$n3{(SEY^;>)Racpmx3qk9Oi9Nl#0nyuXI27#9+G2m#T{NHXg( z7TuZ#X72m-EWnxX*J$&ntQu9%1kM$`mp}i}G|>8u<)%AGZ0v=k=CKDdlT0`GOT)tg z#dFAvl=KRoSi_|d?%2vg$A{9*MO(9iQD#E-OAc5=&w2k|7hofGVWW8ibZ~m1M<~{K zV!D}wu`6bAh3ET{{_P>yldLNVY5G%9yETP-PM2GHK^i59W>J=H6F1?r_IPBa*96fl zNqm^%L%FwkuxuZhqkLA-@n*3u-{b4gGZQ0F$a>m1c@ij3zsWqfYo$1WSHvE-JiCq= zhO?k-xldE@EFIN0u9v$4Yr=bLO{Ksv0H*g9CfMOX?Vua;S5+>wHC-FqcS(oWR5gF0 z^Ra1-U%J~+8&H`|jw`Xd*Wrf<2mH7{5s{>4zUP6EcX4D#fJJU0=x=^cVT&3`OKw7PyvT4=#E%-D z`LyG@sCy738%NHc$-bBMll2JsqKq;tU(l$x{F#tqg{aVIKgO)VJ9G-u7f_q-=m?WG zZI7+DWmhOOl<$F8abpA-N^A;Y1Fsv-5!Db>^43#R;zg0MwO5x9Bz^g|Kg0ux zq=Xzxo{J~mBcMPb0ZYvJPpsEs%|bNH-gM?G zwNn`%-C{q`zHa)SS@5Btfm&>%#g=Hlj3^VJ8pRpLPYYWSk@*|O3pa_##qSc6W;>s( zQe^R5BV66{;+5@h0!vIgJ3cB{{iKfvuIJh-w_2!ELhenuHBhz#qIQdaq zfKrFUp>iQ%0xuWggmU!4>wR>|O9)_;9eWjV+c`>LZuG5EXY+?}x6~7+cm#_yG!pPQ zi}^=$-P5(|L@~4@#zg=5T#IYjCqcW}sO_BC!plnzI`z^sr@*!OEV<;`&kVjl=DCR! zkl_FTRpvD{0Eo#&$1+Pz^vOqyRV}{vFhd*FhELX6NMIUPCG&H%Lcr|gJ9zdS=yKzu zZmXX47i_{A(ilO9zoP2?p||55_1m;L6kfag#2BR${A1ruviyAe!9fc%x?Vx;26G(8 zN2BP09MVIX!FueEL4==Fe1=-*h80Cu-eya5vo+6k9TW=dN;L8M`+7^;8^wCiKN_49 zRd9LdhnSPQ!wSNjAm+Q_E5YgiI$$nLee@5G#Q8vaxi7bpFXCNMseJWZ0k3=vQ~%nh(i66lDmz#qhCV+gAk;*vzi@pU|BbevJ$!#=GR2J~GsCe~RZXc4{LGT# zfuh{XDI#tR)}Hpiz8EaK=VJERt?vmK2VzJ-=iMSp=D-;)7V-1Iu0jm9>U86VV|66B zK0LCR*DO_YWBAIL=M?ih{KUe0?*W_x@II}$_^Gn~VoguvdaMOs%oK7{gG&E4s}D<& zTV_Q3SkvI02v4S)ztEFLR`cgn3jmDkbQ!cq_(=JuqnfsFF4VJrIxdoAwm(a5#KvlC zjqJhN^5P>v#lPSuwr*#`@qe|=pv`Vo5LTW3R$RJrTG(eUd)nqc{2 zcx;1g{PNel9>$RJy3X=?*AHRpN^axmX~fkA@d6?bR^v07e~ByEO7Gcdu{czau{LmO z`3li{OKRay`u(qeawPH%3b^!FthmN0^@1S4Jcbr(N zW5buL8bvxS>u0H!LW(>3N*-VP;p7GCm_vsfN*ZLB3>nDp znWyp9k_-cHPEdu39&K_6Ch;lXl;(rz=&MOzH0~WVpTb<~|H>op;P=Ctlwrfx^yN6F z$h?%tWBX4fvOC#~FNCb)|ZF%v;K~V zjSh-Pg?y`cirB{z2~OXpb<}ZUoMZr68IF?dzWU7Pco_crJ3&X@6soU-3dBV1i^{q74qy zEQex%F^FVr9VtUyKR*=yaWWg=B_lsGW&SYT-{sJ;s~0z@)m~eX|ADhtm($#1-N$%( zVZonji)kK;;RjGN92UkDsBXWr8YL-wvR`@k<;o3M2c)QS1pWaUe5h7pp~X8-`SIxK z)*5yM=kI)~cAvFnBJ0X=)4lAbu zuFOe(Y+bF56Ea*4)*hU!C-rh;TA89%FORI@=_1H-GU*`~Fa7Ag?YFF?6I6;Tw+FjeLH$Ecq!Sg;Q-t1R?u0CTg_JrAW{s?_JB$1cuI$&ZlJ!HhQ zom)^+k8D^|eHds)l=?-!Jwd(ZE3EJQVrx%4Qc%0@7U_fqyode?>*D8@9-`SsQyK6d zj=bx1e+6rGiw(oxoMmnyZke8eQH8?BqQysJXpP_X zBuDZa941mdagpibmZ%49IZt$(3*6l&s3qxCuhv)vq>FNFZoxL8vq&;P_c*Wy2c5a=v+1DO>TPPxCLOrFUFo0a_QI4mJZn_K`vZk5b z4P^GO>*%cEy;Btil|SE%M4p2jo}ZCp65IK$+*S|GU4k&!Avy&2Px7$+ zSSwvk_mlLV9KDaO{xR;b+w|N-fs5^Igd_y)OhW~n6O&0+7!Y9?U7sjwWY_FFovTkv zIX;ydpQS(~QRe=c31+%Fu<}x>w}!U|pA;_R$8tQwR@03MtIW@@s}kmOVwNCXnMPvMq z7x%K`dOa*l#Lf~4PbsNXfk5#IvKt<;4EqiB!80w%bf+FH0G5B5<{dojmu1O0QyGmP zF9?pz9PK@SasrSSv{_EB#q%qq;e3NPGM3DFKOKhwuOC zKvFp`~TzXzoXgw|M+2CrEaG*LXgrsMrU^c)911bsG!c0%Q^2 zEdLz6GWAkP*dafc+y*QBn~?**(vT&Wc573F#~>L zE9wh7id3pSlCjPQF^imVeu4$DfMAvN-4w=a)L0d*ZsV|^`fkCz zn4u7Ksb6g1a1FZAQhaBZuA`_Pajc4#G&y{@=3DpTAODK$o-AHwX#-n8a#~4?f|8Ye zOJ5$%)U+bSlVqxswmH;oG$?HsqQyvMe zhTSvy2sk|ufysVCrJ3CGo@X(utFPATQ)BMr`SOEy9!M|(u-mpLfRt7@0((K}2|*DU zc3GCAcR9O%tUu$-YKIxiaB1!GFlrvOPMSKh{yJu>g9HsKJHsbIyHC#D;1_@;<0Uz* z)$Q|!B-16s;V#f~d00sO>2E?$_)A6k0wZ)a_`T~iyCvmo^Me&-HC)=n87_uw;wIEm zAC&zxqCv%qNH^HfBNmWswPBt4rXQGe((sEo$qVazqn@t+=y!+?OE2Vl5J2(8!zuW$$fz+)3I-^hdryu=rwo&hpyxb z9c(-El`mO$!b#uTt(?ACMT>yk4PS|8LiAWM;SqH%YH>>JZmK2S&s;0jUt25s$AvXo z{6{l=NguGne-s@Iow|dFaO&moq?kya`<#%c z4@E_ibTGw>ioBVi-Au+fuq}uV&PED{VP~!GL@iPzosE>cy{U8qzW zgH+*mS66kzO^#r*E3T2R(B)S57;b2r@rzGN%^?sJGeMIbSaMiOdvT+FSEhS7caFCxd*0cG(}U=d zUBGbu66OcCmkc%7!Z0udI*0}f8l9S!`?~-sdLAT><>-TO@HM#9lG7J@_q>^Fxir?a z0!OEl-tZaI*B~>|5%)~zjW7<~TRUF%dvK%Nt`#i36Yrg7{=RW>n_9)Nr_A>NtF$EW zXwXx>U5m6TkJ0hRdzuS7>caz_K7|*Kl@^kOv~X|OGtTLDqR)9fo_=ll-f?h#L9PjH>Cp_7Qalx$ZO zdXo2Yu*pcys8MF|{435U<#k_ACAtaDUB63*U5ksfcml8$7Y;A?rB9g()#g(53ikV0R2YRxAV(1mQ2D zWWVf#{}S3^@%^rtfgZ9u#1+KmF+G}fr)_?01G3!cN>KZHXx@{*I9)er{TDP{pn)ZU z&J`RuX*=z)Rprgfo4M=ZhDY=l!I$0|)$P4K2lue_Nyb3$-goO0!nabSAb-s27*}D@ zGF=-SI`WU7v@}l>ZxCXTUv)W?g1-=do7Js#MCL+3Yyx)#_O4>WW zN7f$2NPuQoh_H!d?MWAbBbPFo86f}^n|7Nz4MLYJKLC*9^e^~^Joz4dxunBD#8Ehx z?vA0gh@{~@Mvb+ce3R0MP~2t$$2J>4m&IjZHxq07g+2HqT>5StqlZ!9NJeKW7m2U0 z_3Z6hV`9}OoZxr|^O5>=AF5@s#=qGido8*BP22kI(j3tSZ|85U+`38yZ}&^#X6JX| zHwc4mixF667r2JA_2_XAxz7jW9skvoiNtw6AAQt?Fu^^^yU`~PE9QFKfsfKYk?xnt z34fD@+VIDANXXtT8!LB*JTp0|3qc*eMian8Kw%Vi5%OIRGGy0#bInF=ly!;-?+C6ghq0<^_R?Doi5+9b8 zKmSVb+IUbT<<9)iK}L~@qGjZ-gU>b5kXXRsy0yd2G^320Npv&x;Xu#L-%>AR zv#dClrP{$t$Ev)N&+k*?eoG$PZ3FQ>xU})__^Ua7KY#OKYGckfK-m+3MA9yz$%{@apCLSOdDYXEc%b@Z<$7Xn% zlQr|Hhv&w_?&U=4B&!c-R=!(>kJPoyc$?(gakwqd3GKbMxAfe_PR!@)>TFXgE9GJ$ z0Uo{`-U+Dd6?97Mv#(F8aKl2hF=N+byUQHKSEAjzJ?5Q2L}yYBfq!W~aaFBibd4bQ zRbsQbZlsK9BYiS`vtV&?=Wxu_ctDtCBdHiU9j+E=rwb%4FBnHV?+MCDz$rO!|vFOLA@~+cu)Z~zYR_kpXmI=H+ljM!rJue~&XG2$X zd0~4!x+D!*R%XiXf=GqQv2*(zmXxf-7H1)4vi}xk%j)i)EW849|a*3%pYaiWR-fuOdqDUzpuS&YYBZGd}DUPLM{{ zPp{%j@T8-atI5QAaitf9GtozwB{g4>Q`|V7oFVpUs|FCZL{mBOR#{i`ino2JoP@jQ zmP~>9kScA%#QOZbrY5S@w|51dsK{if4Z*5Zo4y7)x_N3c1pl{tX_qQY)*Io-t01^k z*xMyIl2RFcRMnzWGRZMh^I8)zBIX)4hV~yDnxD*m{eZ=Cn>oHMj!>dOKr3 zQyb~&kS}xD&!VsQs|IcAy=%;^2o<0t_2Ddb1?um)KPvSIGhEa|vV8%H_*aB%@Vx+tBZIM( zS20l*Tn}bxEG;@$L3?*y0q#*ny2+sZ3`lJ|3d1}gM$t`_?j47z0~;=$PP|Bw zp(?rG1huu0Bly4qb|eb5k2@S^JPE<)5ZmhOf#Gg_g-2nHc_Qi4ofG3X9jBAWFV1N@ z?@{6rEO(*PLuHxZ1DlGo$yM(>|0FQvdzlW%V%U`D|K_s&e}AG~cO|p2^^{{jvelc+ zh>@S=_o|(Qhz$et9*7o??l=Glwi`;w6?7PabF%c{A5f#3_aac>XhA#J!foWYm2~Wp z9hSG6&uj~Yf32)AaD2e)sQ)xg+SKgXy1E*_CszAEngG@_8E$sz1r5*O8=sgJ=_pR& z*!lP#z;kkvb|{UwtA6I&q03=e)Dy4P@&#Q!m4UqtXIkp`0gGQ|k4EXer3#OKo{G6e zT$vy~{v_P+;X2vrh$=oJi){a2ZzAd@lEEJ}s#7yRu$GzidiMlm{!i%s#EoRNdWF6B zlLwbFfE)kATUt_(Rf_KR0|`e6|7jq>3&R<|G8l#6hBbAvkdSS|+mn+9I(9C$85$3L zRDZD!p7{OdIk%oeaFN|8->4uMGlYH)R)SN=PrH1maW(Q*ZSaJe2hvYiQPVCdv*925 z7<`F(pgRl-`S5{~JF@?b&_P7waZx~8-HYXa3YenRMP`_VMZ87D`0-^nBGJt{8pMB~ zRY!LRkDXU8IksE1+r#3ekRKV`56E^-D+jEwRkb+vYE?Je(BsR7u&CWr{Y%ZYRD{0h zP{U`|_;eQ)DMt_k*cEx({4bK_9-fbceT|>d5noSe9L=+-2qiakKo93{t;o+^H4Sq- zU8T~MoU6knNkA>ROuG-3u4aO86}7BIpBa$(B{pfi+(qz8bC_G1aBp<4=lsG znt(SJ^MI886L+rIQKkwN^GS$2?n%;l9;lHAZWaqo@w?AXTera+kEAqXc&Q^QH%V#B zI-bD$7P(8-SqZe$jdV_JO--E^Hx=RUs&IQdmBOz$3mm?4NGHiKaCLbK8vbAm>i~+> zEr%6!613L-&Om=QpDDDLoDW5?J&;RM!o9iq0xG~Tw%-N4nX`1#e!xrSr&N~7f+H|O zy!_+X<%{F8tG@SV+Ch~AH|%$g0*5Z3%_tEn*I>Mx#HR!`zy}%G*cFz%f|}tIomK+7 zdh`z8BwC3zgK9yrgc=lvk%;THxwH>4aZSr6llP^emu0PH4>cX7)6$1CsrL*O;X74^1Bi4mz z$ju(~g_ndH>5E8x7LDu?&CiwtHI?l;%v1iPAaD9un)l;18+K}j!ZvbqWR9}51#K*vpF|LjB>gZ&&(Hefthjsr*ps;>Ry71)8(is zCaj6?!Hx$r$@WR$XcbXiYL2w ziB?Q~Mob}VKJ4MT7FlhsUQpM*W--x1Fy9ox4&eziR>zPc2zBvU>vTl6;A>fH0u$i*O*JgEJdW>br|82N9j_ zUZRDXm7vlnUsP9d&GSmZ21-5Bsp*UQ8mVFB7XO_qlDRRcBAr~SEDLoOTQi!CkRZjl z$4Rb(evdTK^Zy-;R8a(Uxr0PLyvvW(dB>ejc|F*|$|Yo=+hJqp#4Hn}CAnjuHmoMF)fo&>_>^7#W&VGpB?Zc}r zGj_%^>?{b7A_I$`F@~b|CiRj!T&G8M>aV~L`sQY^SzJDD zf)@BbC-Adqdlbr2uby#GodP3^ORnwH|6&atUrir>Mc-p` zmNQ}2xg9J7?rON^EqgS61vOkiW zeWcroI=%0%Qn1IN1fIT2j_*g4MEc`USDNK-$nC6Qe$i{v-YwM$I-C3r{uPtI(@qtN z+E`d2b$H%Vjg6dYqP^gBp4`SG4F{KEWeEFn#$Tvve{E_rzt5?yb;sp(Ygz_l%+TM! z(0Rqz@kED4PIV#sHMMmriP z?6L)!%I@P$QJq}1+qS>|{rk^PN@*)|N%_&2Udlv1A;-cu9b}jdCr?qUA0<2Wk@N9u zh~*9@$n?pP&60FGRtULN?1MAV4fAp15QgoScP13GwQH{t#SXogw|2D zO4HnH()Utm06ll>DrII5{vI%xtKh`}sXGFPFKL_klea4R&rnP2>z8LxQRF1wpyc`8 z`vVAr=w&5#j*+$vsnVR?)jnl^ant}vRgFuj(fdKK`24)z+=&)44g&_bFxd_Qpp?T` zPt1@jccZndEfxLJ4*}||W!jQc`Zg^n5zgAu~6B3RB*TkJoLdyqaGi4%)|Ej=J+H29D)x(n&MAyy}k5qTYh75^eCh-MUdMh%puB z27+wXF{N#khhMtdrB3=lz%OyrpLNsMks42A$yQ{4am9p^GusC+8jr<^P8R}DVztSGZQ?&+LCvzOZ*^CNBE5?j|C&tTXS;aTh!GVUT^c)I!+gV2wa4Io9UW12cb2m-+3*x^T)**;@#0CY}(>rDrXx<-p4>3-5|qZ!2W z_qm#ht?VgK3~;%pIRFv|spfX#l5I|-38IcH%$m_<0n z>8imyoAbRMZeR3->y)k*=}hH{*#crness>!rAV{3eg9k1B|;A*F4gTr|txWv+WTJ*hpuW`+N6hj=>p2#F5*T+gAlE zAKzI$&RLR3S!G~fvinpGj$mh=hb1j)d|K#no6SGs+PJpfm~xr1y{cp2b&mU#Xu-AI z!PinLf@wA0R+sF<(C&2ae&Y`Y3uLEFmTkRGp6^(*v2DDXYd2E>`~=Kbyx*1@24CxP zRa<_t*+8%(-!5Npz*?hk|Bn5X)@WTD5ZXW=KV}jK*CELhMu}eleJuk_bO|~i{MXY# zj@hxo>NRvNy=>*;U7ipd=BHh0$!+{^f ziN8>9z~4l5is3S|<-YH_aVJj1LEDD~NNkVla zIg!;jptQL7$cM}t@tuwBYsaUqf~;$-1m?N3!d=$$6Fl8X8@LX;E9-DBm|y3*JQzW} zc&o?eHd(OOtjdq&=cR^K`&=oVPyO*ndu`f3vLnyM;J_*lPJl}h>OvlYBeKP-0Do~i z@*;E9Y;>l^yZX^pu|3XQjpltSxj&SBWBZ{k=?USe0|de@m2l>_EYnwyH7kFI=^v<$ zmWR(}?(Qe)h*|x}PkNdgxOO4@YIL%7E18v005HYZ!A=M9ih8{U zYOUKm7X9J*>V8h-OMUs5BIRzy$NyZ(tN|SvjG@#U@LPDvuvI3Z%oQzBafNwPyWI(5 z*|kfQ#rc@?C^`icNkn)z9$3BKFeKLie1Ll07*KP;ZV*Nq@MWlob%||=#QOI&AiV%y zO#Jt$Q%?r21A^B+mbMPZrub5kjn9XR~@0( z@$xvV{)z?2oSIvJ2mL|XH;1~<sCN#JfpBHuSw}^tesJDP4 zGIR;a47=c>TD6nPGRvPGw5ER*$+?0X-RyYHSb@2U7KHWnlb1;M2mu|Cs>RPrFU}>Y zV=8wrqmRm-2P8~J()V#k3e#RE+xwT~2NJC01Mq`OcHIXtDy$^vxtP6wVg>VQBPJ(M zAXBHYUgG%^XjCDiFxS^8D!gRZ@&5aD#sxK9l1eJrJ->L=v-6eJ>Liu6Y_L>GOCq)q z*yh!$qvV;%_m8(tbJ>7ivI+YYlLAB5#v%pm9M(KYvgKK_YD!e9yvV@6A=cA2^pqb~(dq`{0 zbh}o>+_MXI$(QoSlmgXhp@D)c0Q_&)S|-y`X+c)17&|WW+f!{R!%p{0wRA@RasS$%KcixD#0GS*I=Ax@SC6V^`j7$7QFOx zP?S0i)I{BAMi#Ww5G_nUq1#}Clx-E%2BNPW*_v{WV%CFXfN}u3Nbe~q2ZGl$jzmJS zS5C8Z%FEezh}W@a#}xNB{}=9~{crgHp-#L_$(>U>SA-k*{Kc?N3{uqxGWZaD|NBrir`Ictj$bQ1+bGA3%&GaZby{_3-p2Ng7-LuIt z2c(%QSaGI!uDfH7+y#stRQa0`NDlr!|-j$6`o_K%~1jVp%x?<2v!T>h0N zN8!&oT9yk(bo@KjSEM$6%=zDRIst0xs-?PcG z5UaJtf(^f~Su63LO(Wh7vH{U|s+$Vz1>9(2mVjuq*U25cA~(3srI+bEtIH54+_r2| z@v=sBp7`E+|HDj2NkrG^a*N}_y+A)}X>g-q<+Kwc=K!>ze_J7;CVawP7h+!uJ@&6? zT=QjyFzl2k&IQK3!DSmK=`!y0=1?x$wC&U;b-&Nf9_A90HLShYgr`tua+6J)EG-UW z3^pM@%1v-!#(kB0Bstd`5DI2Qu|3!ra2&Z6Y zm}VVrEjlT<-Ej)oNnNFMSfTJuOROjDO#`+&s(A9yv*J=ny^JfB`lPdG(Nm>z? zk(e$KKrv}Wsmr{@QzWkbsOZbSKvJwiF63P;_t5wkNSVl27 z%Di~D9ImMAk1c<%kF7So_P&Dg^_yD!VC1Hc-KecjNWKgZb(HH^d*btRquYnq>t%7i zZtv1$R&3Y%JWcn|m;aQ>bqvO`IS(WXPeqAwc;kuy!cnKZoSf$XL$5_v564|_THP7l zVI+o^tX>h(i{WjoXKXM0oTQ56Uio$W)<5nR2G}QTNv=wLtI11SADr%E?HCr5WF(rI zR*$kUx5sk6#@L82UN+*uu##UlK;)@R(5HMi@!6t5?@D?A4>Ag>6(Q{?=g~cSKJ;6K z6|Nd-?u{@1-bp~++i_4~CcjI)+p|o+%0d~rr!>rcC16V@3VnM`%WTyFovuq|_3iwU zwO0<8^}SKQ>h+Q{QH6(W7%E_c-}oWId+pYfGXCIBVWe#*DPACz^n14DPkgHeA+uFQ zpqB6|e#xn?M?A89z>c4>BTjUSol=gp&yP~ACD|xEUQ&GK=641y-@eoA!z*zs7oppw zB-2iQ78NH_`!PAHN>dA)jk`h+Uh&-%2HXJ!9g_sC@_{|kd zfTE2ucw^@tjI~1`HIJNdJQ1jx5*?ITM|7ApH#-r*$aA%P*2VE8kh=DeEJmsdwTG)b#21wN|bwL?qC_*sDrR5RRFj}Z=;s&x~k1INy2(t zN1&>2;~TFB8;=Qwx{W_40<-U(+}V>Gqi0??3`|NFxpUHPoSI9A6i zMf5FuNrDpeJ~&vkb4FUFAM)1aeeT3LI(t8k=3g+~_CL+>)d8H;;+D#|F!XnWq3Tyy zeXNZ*Sih2_%#)pGCmY-Q)-r_qw;txiQZ_JE?{%)wysGsnq+4nBLQLO1-Row$3l?A@ z|2co7>A6`C&ygP}4XouOd&WZ9GfQ`-1~U6@t}%6>c>zB4_;}tpH096Lu~wcEHDksi zx^K};({n7nM+dK=3Tuq1N*TDBE*Tr01TG#m-=1syld@GmW~|iQF)I(h-r=59HcxPO z+!)*H-2@|Z9NA_%>!eyg1|z>Fs6q0c2_<@U_>9p0;GXzb(*3*FFwckI{z!o*!t+4m zW^5p5_Eo2x*-qSaWu^mX(4VF2d(RydGOvi!PF^jU?P4y{{+JNmJIr1VTI zQ8qn*)&r5qticHJe6cXrJ}^iVrz1_izhFoaJq63RHCPK< z@3>g#sMshKCmLird;&`#QZ{fmM=I<;%)Tx6`Byw?{;}@G$+vh-L|X!kwhIl|td>AH zsDeWGA#dtY--i{={6owip*$K4o&e?2(Wj=KmB^YH+f>prLGBILgZqC0Ns zv5t?7?$jnpRbmQ85tm6$OOPbysjDvoK_{M#*2&|OD_@&>aB&pV%ZOiTc zogbo_n@QW*>{$6^X_{>de%cz_ct*zx)UlY;siN$12ENNE!(@!&#Q0UuYs5LFI?$55 zpm)Zkt)Pl()hJ11T7su#%UE+Dy`_bgZGy!$ z-8Av$ZI6$%Sj~07&Ax;}Rl!f>>hOPkAV`Bvv⪻ zscY~4wlG&JaaQE%qpR&k8W}?v!>a=V={0KNCfeIBzflF@f1aIB#1oBv|5?A+v}UsQ zxH*%>yrj&)BKx1zqXy@Q+!6FO@!QTF4Ht9b)v$N_)^E{TMje5Fl@vL!6n!YN@G!{R z){d=|yBB!n`VYrWwnMJNd=iq~VmX9==L=uW$D9}ASG8t;Ju3RS{Vdu~tl_|PFia}` zwFO6@PyErh#b^xoG;H)$!;tsisWvyctelL~BkCPSqDK>D|HpEJgn%=ftMa7#aqBFk z5FaN0u;-qLp~a*@Z&#yiP5KsshLWbj1%H5T9EUUHMr%lnNpPQrDP!lvM_Qb>e1B-x zuEqs7-#81C2gSmQ2WtQHs|ZEq|7^Tfn+aR4>u$ZdrjL9-UzutUb()tvQIw;6CAxs= zb%;mna@hXr?cwEFeCe!)%GXkYTyMl(a}%? zXattL(ese0=gTW3clTUvsaqYF;vLVp(r1{0-!~xZOOgOg8>k(P??wm?x#rZJUkj5revodE^bjzY<`MioK0N#pie)gLWXRX;a2&y5q;svB*^ za<2TRWqEd1uzrKxa86?vVII66|B>W?W*lj&$#^NWapcsW`=% z{}Y!1W@y?_iDQPFkZZE@lxg}04Rv)H4s`!IL_JAkhn7zgcd6neYXC)&A%!euA}={w zT}{>;e)&#*dZn(`fqi(f-0@Ut)JTA=PqU_hNxB!)KCp92&}M;PApppwE8E8gtg*T`VOFBjs>5*LWGj zUGG$%cWe3Tx~+A5!U^lnOx-T~xz-kgV+HAhR$AlJbHh(2zSfONA=aMigA>U2i!*5* z?larws814WwTWZ4{9GY}FKX)1g(}i;TFOuAUHF4xFDJ>*o({kYiQDTODh`ucoiA?S ziENoZ0)>O$p=VaR+{z|m@iUaYsi2MDA0ol>-V{;e9pVK_saUzd$UcTw7nJ1T(qC~Z zJnQox&6e48nwPyfq771$ohvX}ir`()9=7iNdYMUnc)E7-2^!IXt&xZ=(#qMP(lypL z*G2cgJ>U{3`J42>MtrX^E7U6xyb8XA7(Yt`IBI0rB=FwqU(fQ{Q9T0$J4z>KU8yI;mhiC;R;BmZ6mlfYw zjYSJT4g(s?tvDASI^+ups@C9wcldZh?jj~YRUg4sv@u@b%it(zvktP*!F_RFxp+^@ zPatu$?|dMe?YkQkCGv4(Z53R0HJ3PiI?1G#eAI{r?Qv3cNiBlAV740MuE%f>sH5rY zH?P&6M_$53r`9#b^A^GqxV!#<1hu?;TPjgL`9_#J(=+XCnyxFnMJw2NfaZIT-&7|- zR$_esAu)pk^L6Om1PQ}#IvPuO=Y8d!F86K+$-BzF9at`^G)Y$nz)$L8j&(#P){P$+ z&+MzGr}#7U`o0TviWnomSYc$_i7tl4>o<%Y?3=Of3#a6zhwEaxVx`PLXp9gg6aj*Z z43V!BKy7C=dsMWyr?ptZKybv!EgY8#$>}hBW!ajb)iv98L)N0zL#nsGb?jK^=JuxW z^4O6qMH+lC{~VhcMQuI4KLWnF<;MXlyL%y=;>k*`SQXgQrQeYpI{(8p;`#XeNsU;A z+0E6_WArA97<4#GY@O%=WXv-^pVRt8m-!)XXaxG#02&%jcLiXJqBeobYfB$dWVC;U zM(R27GAin8u zGqU2O{XO(v%FR$0U*4unK^*x?C4l~ZK;!s{n&68nbw7W}(f$7!{r+#D*#G+zSQ5O1 zmN%~bA6oo_wN*$f%Sk(qSy7=03&vk@r0N}YE54y!0RLi)1Xoe-ZzJv`y^7=U=`0d~ z&0n9BInAKNM(fta(syRtZn zQgdo{&JGJ-<}D(~w*zx|&W}0ANv7@6Go4P|2}fizZ}!{-cw~{*zXEaR&>zt4vkj(u>d-KwPtUrMG=mtS1|^YDkLQzLx{kzdcPC8C1iLOQ4I^wg%IxK4IF9f@nzueF){Oh@+ueS%G!#W~4 zNV==W$ppv>ZMaJ_#2fnE5@u^^V`nA-|C<-5;^TeVUTF;!%oG4E?L`;`7~_%(YFUt^ zc(VbTlSu;F&PDg6Hw^OByetNz=7~_T+&aZJD*kav)yFyV!7n^AszyFeS@Bg%li%yx zs;>N-TR|4`D0&q^2Vzk`z_N}pm+z7~(V%#9)Lq-iLu#J8VW{T&pPMMR8y?rb-pS;9 z_4l*&L4Z*}tm2#MuWjB=V$xTy84VRNOuaiH7XIq_FkIs|J+jd4$0;|}_Td9CXEwr? z&W(P<1y?d-sjp%KgwsxHXMg)p5atOgrTESNJvnN>l@JMB0J~&>A?1{AyXzEgGh4XC zjkM2&f4=)4jcEb;iW(3$ZPLey3?V~GwwbpSUPT551YBbfxMiUw@LQ2hRlhx0?-7-j zP?k6AaH0YlyVqz?^D{uh_-P>B?Ey>IFf7wbltv!Dwm7jXcGubNLZGyd`%}vx3@?mg z*hF$Npu4Ie=lPEDdww=KZp&c9CJrGJ+MgDw{nM(VXqo%k8&`Iy0dg@A)N{WKRZacukNb~j>cBRkj z&pW@Yc*^3f>6DcY)D`|if-mmX%k*cznQ7cwLFPp4mH!oF@?d!3kH#^KB*`vM2gI$( z8yknckD-I<#Lw4-56tCKeD7accYk9K|BuG12|v1u?FNUOOq>Av#OC*fe;MpIUPfK- zsaxo{VLpHI@)WShGSE1})hM|tPsrv38iH;oBc~&0es1Ea=E^gdNDx>AM-$7Awn3Xx zP(Yz2C<>sXbc2-i2wWX?K0XSPVen26G(FX67AraMa5i5qwOgL;eb1$Aw~3#_+`?TH zzR@LTFgOV1h&S9cTKy6l-TR;=0gNwvYSv259I6(@|IOnxg0Yj60J3S^wi{Wm_K%!WQl`q4(9?g6$YeTldlA?z-&*k{Fzl|q1KHP;w>u;XWv)0kst2|8n`)|9C_24 ze;L;_(LTf7(J;#}D3zxgEX;KI5I4PSKQcS36xF+v^mRGkrUW$E=fN6`6ECrzxoo}F zVvkBmQ&}wP*?qvLE+Ju9mwHND$Q@PY_-H_ma7?errKq)amDej+HU)!@?QXfLgg_7Rs3%VT&w zzYcG#WsY^5YU=E*BV25Tkv5i9t{#N zYu{7|Pj0-fIUT&^e#7pYNm=p;@r{F-VV#DN8 zJ+>15$}yQ~&MwSDb8a=Aed!*7m3)}gdHdMj;XTc-XF-m95P=(;7nPtm^3_W8SL^M7 zk>v5k4aZ;qs9doME}6<{MCS>%y^jhO)tVnbFS}>7_E^-$fFY`?=B*t4>_eJcI?U=J zuG;(zIZ%)Ga&Y?Nfq6x=UZcB->R8 zmZ#mW)AUrj>nzb>q)qNlFZ*Mz{Qqc%a?H=M%dVf`@0SBA3D-MI=ynymW{`Nlm59JF&XlaD8;y51JQJDI8vMobQ zNWxG8MKk;FRMbc7Q&dH$VJy32@u!RNPeo5l9{-VQ_C2}Fdw_j<&9{M#FUusEdSNV1GbhO8;+i??~=aX z;r)qie)#B{+ZR`I1v$Q53fzqN1{4x4?fChiY>)m z5R1`b3k>o_d0J&X8H@VD*1wY4eOC3uE>_*0GPCXllpf1>$WJnpTs!0x1nNdx1_lOV zo86j6dnPoZ7{5{M3ltKfqo>o$m`<|@mx#cz8=MJ4b)R(?EDy#SyZ=41R41B_?K}I- zR;9*j-!iWZ{vI^;Z^tx&+6%!Otx1^;67u_J(zq7St^DX>4&8`RxUFm_;tZ=tLAdU; z7q#*0`F}M1h_bh&*MkszXu)TMutP0IMEysQB=h#=4Epp{?p|y6x{W8Y!&_&@i8);i znD_#rOjqcgs5{U%FK)Y|UtY^Jq$49)^mAS_O-ui*7J*eg8&dNAF}NJh`PZ0wcX*$J zQ_JG_h<#tTM{F36VN6k3#0T|vrh0Uxj!YM*x2$Jz4ULL_D?g1!?;b=0GU`v0H^h2o(Y~_X_ujyr=+`8(Q zF;Pl|xr~y--!d%j%|#z8X*C% zmX$g%)H8ge?p;K0Sp^6Ce=Do`=xO{v|1#qihR>D5jKuY_YI1IEv8!OV^z?Y4s7d8` z`mK4N==GncRddD< zG43MQ<#Oc1zu^z-bYLQH15ZOzuz-CdIEP zTd1esaJBO-nICl7qD)4v+3-(A9hEUcCY22LuXyKsL?CjUao_x<$l^b&8nGsWD>Q zM~>(rQhlxX?WQ4roDTTo#JWZQf4u&d;E8CL!*OKp@bX+ap zdcQPY>bGc?1fLwg_0|EwHQ}Y`%CMcG6H83AeHJwW<4>KJ`!^LM7h64WsTIUPmJzF? za^Y*^^WSQ=k^hR{GohVYbt8+$mETMmtr*t=S)_Dny>NWxn^2u}RVA;;=#AXo4zPEI z4G(i~`zN8F_wJmIrn0{)5OI{WcCr1Nh+S`Q>!OA-3K7TzIRDGCbY_fE@ zxkve8r*;1npqeZm2n6r$lJ98qD&e8)ofU~!^L{;W(M`V*joX3%t|>j~5yUk3_D4XY z+S$!IcwRe<{)cXR{AbZD`YqNN(bLZ25|g|S*HT5iLwp5rYE>FU7_v>Q;1CS`kA|jP zW&>ATFiI7i1TRA-Luvlc7yi!=<>wL*`iDXYo6qHF+`!zKFq!~2zc3p} zz#J>nP=&;Hm#H|XM4`8Bmyup;;{njHxi0?qrq_D>NQ;7Ti?!Uh8}ezR5%IGoIn z>!zVzYNG-`9Ik-|<@=JnH#CUl;N}KajjRSR{Aa*X5okIGu^^=`OzJi^oT3INVwiD@ z4;oe9tLZE2hJ#%Pr`VTHg28rE2o?C1F-aF_vkFvyU1$uXUz@2@pJ0*Gx^I@&n>hMe zQI2gjip=+eEtW@QLaUDi{rPx`lAHJY8+JTu@APz)<1ut2kr~;GT z*XpjT`XTJDIGDR9opIW#RVP#(Q)z@;OGDdZ=3pADjxeop2vnOFc&% z)YVeOzsT5obrBm!X2V1-t!D^-RK8jX{ra9Pny)EwTEufqO%`@ap*q~zGv^yx*tW>W zkwaGzry*0I&b~owsatB7T8LQ|h{g*HyN{#D$mUUmO39!qU}SCA<*ikIYR330D*yg$ zVj)p3 zy*Z`cJ4jus&qg^DGRQ2rICXKfU{70cO_#XxC#g*mXsYNye zMUw7(q|Ha(!6HY|$hm#va7Kpkum0ryS!&Sl%!@ABHt8n>_Nerf-j<+S$Wt=j_)1Mj z{cpuo;Byewr66-%y^0pA2R&cF3sOzwG=#fJ#`wVMvMJ@m3CW5JeqpeOK@7-;VA~C{ zIegW1dWOGH!5*Z?JYG8=W!QXqw1r>HQe66Ip*v#dc*bWicZ5x}mIvfSd_G6-WUAnc zpxXjmD7CR(MarZ}&>SJE_BIB0!(P%7R|-y{BDE6V!#ASJ8?FrfnV%5GcwjiykkVbI z_EjVA;84WwMTt!h=h%U$SVkPH;>A5Dga;6sb4S4OAQzcKwKuiP5O#u#2EMf1Iy!?Z zq7QQDpXPpYJp7)BFx-97Pv%px%?7MLGv{Mm5pMg@mTg!rB)Q?AH&&pEW#Nm!b zT@{_9a>Hs2hDIvwjP>WwNus+dWS zOjQoMhlscag+^UW2)EiZ5z+P!E@CGiySsgsF6nO;*Tl6v`#8!zbmlqex*0UxZu;gL zzmT29tFFgo^$NbmK^)A4%2UOtsGZ->xI^}wQwa6XLHO;|9hXTupLa?c>&Cc}LM2PN z5NZ9?ZuSrEdUB>`*G)(^n!3nY>pzY7xVc8tAMb+?Mf~tpT3r?S-gB}DQ;d;vMI<^g zy{djNF36#Fx79u~!M3kKtK)sK(6+g0=b>s#Ce4&XWmQRGOSp(Of1Mq|y;Rsf;!_Cp zyiBIYid~U+%+y{M9|DXqMRfhuwt`Hfr=(gUT7YtB$+B&5+^5MB!Yn4@KdWO^{c*B# z&IRe!bSYgtS-fpFLf4HN}`a z-vU#@CG3LUx9%XN5qIQsWfH@2nzYA5EG4T&*o$haNlca}(R_2f0sz!)6#r3V z=%HSWSKt~?J+FWh{KSBGHCMIYe=m}-s}G)n|0SR*wAv-oYsiuBj;}1^iG19r#*7SHc2e3>jFAaKdySlb*&kIC&5zkN3U;0{-i8Z^S z;#5u5MjKmfpw&Hg$)Rid8-U1iU%+?FiOvG}x;bPMRtH#?W$EB-Z<#>sLISUtSWk)= z@42j-lG%GRk`b;Zzgt9jhEb`|%2YI98ND~y2v*bMl{k{FpGX8ZyX5ysmdP~T!c?7` zocHibB){6Nbqz*UJcC)Lepq_*aP^C6k1rOiH!~(~FE{aug@C;lY>~V0Lz9)0uoy_c z^xy$&pK!`LeQ5Aq}7r9r{$FGYz{>9x3Gp;Ern0wyG8x#*+TJ>$~jb1mO4?w4q7R zb*s$Js2^v3a;z)~(M~DDG2{-S_6!P+ZA>>u%I|Q8>QwzNI?N4pvkM30xH0RV21i?Y zRsAz?xoF*lucMUH!HfJGD8l_z$Uh9XZ|?nlA4)x$Du_+xBk0+b_C$t1qod~u`bfGb zx-hpyVqNn%3K+AsfQ|ovomh4EDVCg>Qute+Me%H(?_mf+yiw%<8LFh#Z(p>ut0l=C z52+$p8Izf39f$BVB%EUb>?tXJb%dzA;-)X|1)UqTe0BNk9pfz~@8lLB2w8=T^wEc) zB13#KR*PhocFJ1VfqFmS-@SeQx(T~*Io*R$)fgaTsu&;lpN5iRWaz*zN5}$ttAjy$ z@|r%O$`3HvjN&7aOT~kSlURUCHND@n$TtRL!w1Y^FA`Do1&jJwGMTsguXCv!wNRd) zmmfFPnhgDf%$Y5l=3goi5tDF`izNvgdnI!5lt*JH)mz4l7MrF0#FwuOA4`mAfM@!%hzk_A+4-8# z+R4$9q)EkkI@OJ&+-%M(Tp9GX$}lfzZHqCLSVnpWneH#d41$8pz}mi`C{uP@=8PdA zLsf%q*&P|Zw)%B$$`|go?S=z1wfD0TS929+l-l3F3b_%u7nG~==iddmBdfQrH{vzU=#L?AVTnPLsB1~ zqzA>0N@&r#7Y`)H$FB09zk<)7Qf|sCX>MG>W;q0A-Ld=(X8Zbu-NZ2gb6&?fb?h&= z5HzUg3~=CfGeE+b#(klUyC=bO!YhePi&mfW>5d{cJFclr;868ZJEY=(GMrFotwgwj zol1V7^Sv#9qbG;3fyfs%2p@OiRz~?y2DXD&7Lc(&B7zSVrs7+TS7vsOX`zL+>;qs= zv3M;muEy1h0QZ0%b8%fiYJs)}jX#{~+#%4D2Ask_U>|Gp)y>t{Y;Y!0z5o6tWcf$V zXfSQbIWsDaA;{gJLMr^*2VR~Dof1CYZ*3Bt08v5~!yI4O|PInJ-_9GbI0enfW`W|Tid#katuq^UV_cuc7RrMe#_3PTHWRXjy_*%&dFkT5xB>eFB3ciIRpSn`<^NpRS}p+tBBhM z3!dla$4p&Hk()t3vNW>YOU3~`N2NH4jw)j#6sKx_zW=PPB5>n_NgdHY)mHfpI7;jCjv0|c!rk!CA zF1BL3$Nx{L{QrjsBCu_QHqTQd>_UwA?|7?J6@IZJg4!H^{YTO6NtikedkP97|Fpf+ zjv=I%5t?Ppst?w~`aF~W+&`xjJt^^RZ0}%C^8fsVYFHMI?vkwML8asA8zT;%3`Hx% z%@9@aDr9t#&B~|u3>i?o?x|fIxl-RanNN+)zmfSnX_b5fa-}!+xD?w8 zSsSWaK}UdP5C$pRo)8x-gZ(kjR4Wt*b}+aD zvw(JcP+2WmWoKr*u%53K_&SsLJ+UiniVEP(869pIYz?0p=<*-Hp20_sJiJpTFpeH^ zcFV{}xUh3jZhhMdh|z`7Les;|&sNt)$Mu`Kj6|K`T#+VP_R<93zbwD|nSIC5?O;kL zuJgiwTIN7WoiguFgMa;GKD>ipbDhm5-+%B3aT9Hp(R*{rE^qXhVHROasyVhhh~88X z{EIpmQ>&Rk*U=*CEM`=tYQ8X*n58%*YdvLH__Lp8wlPIyS^BwD8x={GaR&O}-76)Q z&>t@K_ry8>qtJ_~*s&G04jd7n9~jZ9Tq(Gb=r3%_PvP)Nh50D5_xG7mODtBuA-F6i zaXeP=;f}#;_EZ~>@YW}eA(a4u_8_zWVe-m;gR0wi+jB9%JV?W1@%5Gd@S*707+MiE@8Q%YQJ#m0~8|TYoVA&*j zH+I%4@IE6k`>_Te%`Eee$9cO&0ni?@OvaLJ+t@eq$Ou`e{cCZlNJNN=jBw~H#BCwq z?z5ij!!@>ozRnT&wXB}EPVF%pY9~FaX-N6&msAk2CcW%PDs3=U6>&iPB!PQIX7n?s zGRk;A zOR=+@51e4x_{3F{AEQ2HB(@oGSq`|UlhL34s~={)wK=)*zh<@}?C?p>q;bGrX>!A& z`lfFI%=)0TN1^v>NTedgcjbPjo;L0B^WSU3q-zH(7}sI=U6;k1BTL53wFG3q!*7WX zh--<`x9>?NYETomXO-?c;^+*CZ%SO?Tx4t{?m{TS{honx^3#8k4Xi17MLAIhD-yJX zsIJ3+%WgkQ*>X#AVTng=#&Z*SHp3qFOb#C#fU0ZG0>a4x?iHPPS5X9W6!S?_?B*ZtZ`}G@t>V)f|6wkk|jDbFPnN(XuHuwGF~Q z$C`@BC!o78c=PRWEn#o#r%cD5y;grC@=PuLZo@mtJ6|8Ii4tESVubTunjO2`M4p^* zMe{?obH8bss=FKMEo4QE5TUD}NQL&?)i!#p-jr{gv74{Q^-!F!UGFIEYVOY;*2jag zQh^32Uj#Kk7t|wk;pGf&PGgHKw}ONsD}8jQ??pcfdFTwgRKs3<={a(5<4F zVN#@K*cBX-im(TYY>rq8n`E1)bZZ}TXP8A(B>v?~q0+c(CKh29He1m~y;ijjgoL-J zJOtYhN?Q}M@fGdzgrn|@_2N?nr_njO`#q=H8+R%y%r+L-?D|X;XWoa=p|H@UD*?S- zJ!UF5LU?g*@WI6=t`)=cFVJ`9S6!`YY90L)UT+k>wZPt1?O2Yb5PNz};DF)_L%r+X zOL8Zh!}NYrEg^cx?pg-my-~A01~6IKv1mFX>MfN<`v^}^Qw)BjpV%B6{ zWks-DXLg|m$pjK&!ht?tYUoum0j||VmMQ(#F*2pIhI6L#1kR?ogx5M3EOL%My`9K~ zxe|~!D{G(bzG}vU?1Rj=-$eZS7G|@4j!ME0^++V2b`jh+r73b`)V=yQZRsvwcR2vi zU}Uj}&u2H4zr#O0kL(M2;knR@7G?iVY5Y8jw9ZXMWQ<&YODdJ^_nt)1+OCqX`8q)_ zV$nUw$*ccEr|A`Y{eyTia%!MIIB;}_rSUmaK%e131UH#3747N&EJW}TzGl4(fI+Hy zjsE7Q0~YwlVwpFQB~gFB8jUmw00m3eFJ@N-EA|~Z(1sqMu#>un!0ENxm457jbLpzA zMEBA^c0>BUmVN>b`kq9H`{{0wS@nz}{jOY(O6tq(OtIV?e?C#Bv2H7kTvx5?-MZJdG7y@oDNK=7^L`(SC!xc`V} z!bl6IyDWQ)Z>%OYp^W3ZK{S!(dTg`pk{I!K)!Kg)t99`;u!xywNn&iTQFyxO6C{mB z`}=C^yeOX1^5)_QF0uNEn@YRa9coIl-i<|x2~U4|BiXl<;~F#-v8qOn^$R17Y008! z3|ek8scwc@_k&UzA(_VZ;aDN~8<5pOyyW`sQP}W(J%OO1(1o*H+3AycvqE1r`Co7B zjdIDVCrX`D##B=6;WvyeA1S=J-p|`lw}a>0icClN)-* z9WDCXtn^R#sg$>#PZD`cTf{(qK@pEx$21@RdZTzLjxe%iegq|i(KoDI;a9NanIZ3r zFJhL@S3u5V>YZO#jQDy}1`Zz!3GonP0&WFQ3{*H*2Jobh&go~(z4@~w@ir^b#;%iX zzs@J>zQ#gRAjjE8>`KL_cP5-J*-oR6Uvx;|*f6z9Of2)-h3hd}Ph=3T1Th$Drh+dO z*^&bXn%c;xI}1E7L#!kbhsVK-1lF*7(>ZoUVZt7$1`J5`zROT)zut4*!&>gDr zGrY5Vw$*+uApE<%j}VvNFS;PeuH@Ex_q+ASNHku!5 zYOu{v((Kd1akPb?nGHFd))UM7DkxjCl8ufUb#Ynb9ebynBR^pHzpr^v)5a~m+{H+I zE^qWGo{7Ly+b4c<$;6l5BKi*X7W1e)IK*z{n+0}lrn%?#>=*3)9mLOemrur(lkrgs z!dr0$Xadt1bk6Gc4CwHWFas!^aVbDy?R-VWBDlHwKZ<|Pn)z=%v#gO=Pzj$rTV#&a zi#h!8_~+v?)2xQbhZXP%H({rbqQ8?=hl+&B1oj$UUyoZ6rcLSThd~1#;b;i5`sPYPVcN@1{ZQT;PCP9j_=*;+w$x7VqQT>sA?6?L3t&%A`O9fwLVG1}5j(fu;Q|FC^&(8wT9#$nyTs<;Ce;z4Uv)8yS*& z=-<)0RY+bx@D-+9D&E`bM0AKC-oAQSQM7f)IKSon4hT5B*X~!$I)XH|*Mbmy*>_Ck zK|6!iVPoX`DfkQHyTIERz*Cow%*B3E}s+!^RF~dX8Y%Opu2}J260fqC^&v~^^NWf*tHVL z;=x4jGf)_m535{F{xj)N_lfm_cx>Io(nG9i6@Tt-OVJw%+Jy7U8vJMJkm7!O)Kspef1Hg|+hRzFT?hj<`6SQ#M} zOs}IvUye~V<7NwLD7RPAcy(IjJzJarNGG=o=7LvR%07C{aJ_*uOx8iL;F|gOokRJ3 zoIRZ)s{Ha~#pcrU*|9n9)+QhsHPazJPlc4@v#S!~Z8c^(WY7Rv)bpk-{jk^);R%eU zZzJBB-7I&ypj}e)JQHZBOa2CL14lL?R{TE~z8aOOj^b*5hg^lsz}JLTDBF^*C7J$y zs(3k3hTwn?+*-5@czDP^MF-^r{i!pDk#^0;Q1>B+|30@`T*@rYX)6*QZr=NFz_u`s z`eJO@g@zAghFdp;?tSWQ`7x}W^klcWnTb$u0^q`r^45#@QHXt~p((xMk9r}n`HobW-j&%qGd zKhxmA-8Cve7bDBFlz?$CFS;odQJBrYFJ2x_1EuQLL)=kr2kv>5IDk>VvnHO@@umN& zhF59*9>cm3_Wz+wuoq&h`#{M55F(>Kk+QbTh3V+XyqF43-QNB#JDa~G~r#92w1qifJ!UlWQ z7tKmtho*#_nY6_S+`Rv6qtfL=>7)U34Jh~NFOe?U;kktwKl9yfLdfh;9P;zKoPfPe5I`a{kyj6;X_Y%6``N+G; zqtiI^FY>A*jVa36hhQ4uOa+EV^q=uo9qo4s32z)^5cC1=R?)e8*^~w~m1pnadx~ap z#*EsU>3Q*wCP1yN$gEoAtp8~|9`bQ%H8Oj}>GeT(s#d+9K9Zd5!Ev{cDP*S}ynwDF z^AJ@>+eL_q!>u9TzQpqAix06IbC+tRNbePJ#w(i`J<2j|3i#yJq;XbLHOAUu)B3jJ z+1Gx zY72#MEc5aZ&T$}K*c}inOuQiOO{q-sw5HHNr+J?thO}dbazfNbbp!vhfW)DWJe~tm z{a2hQ)I;8|4%YbwQO28K6A+Z#9aMK$gfDNnP7}He#xQrg##nzZcqaabS~Q1Aaj)kcjERJD zCG!)ajO(U~Gluksrz@r*8AjWv%-P134~2p{vqv6>%JXK?cVa=aBCkeIm0IJ_?X{Tn zC7e4Eh6QJ#Ecoy*YnT=XEG559*#Q-CcR-ZifiG z&aposC!c5ef*1PtUk^;^g!%hgTDc$m#=$N+nrKnvB%e}y8#1p+zy9R)ovBTsSU3}W zfJ~!nBj0^WG2aaPB9kDNN3gtjAzgIERcU;Gg06-dE}Tqk~dOW#|SBhp}z zdd``q+YtbB%`Sz`$qnFpD*W(~rFvv1au)g%Mc<0>&hJ|B;DvD6fOme}ypv#7WrL}_M2H6Tn^87 z3KEa&G>0rPy{NhT)5nvo%BAE{g~H5um}un!)e1fivQ`N%Ptft(bGF;g?ubdfTt>o8|7U9a-#Rd8wd5`}s z{kv|J3q>Iupkj zjF}o~CrolhVB6NnKM<@}r4jz<()H7Rfj}gK*L-u$Z?g zYtA`Shp7-sGk3@QS(CI~acpMi9zN zKYk3Wp?X%Q4q2RCM1J>f5@#4?m`0y|08G(9mtbcUBh2v)YtfHP>FN1a+Ip_YhQ~*S zita-LiriD<$=r^y01Z&KpyX|_zB0!Mok^di&3B8ZztH^>v)I*rEQkdVM=tFkE)}*O z{o{QwH9WtxrBAl9>ik+jUHzu2i81aq^RR?<;(Q#Pe!a+vZ@jU`nsCeWjao$PQoX@W z4Zdb&qZ2X93>j154}f56;;0|4yli->oz%2ceg8KbkD5EjhBCq;OUNu;x>NFMi}cpx zfJ2imQDO0RhnLwi>9HTp?p;?Gl|O?nOL7{gI_5`_?1m0PYU)0MOcx_|D$kG76tN%BP!;dBw(tgDszg)!{12fpxO4m z19brIzG&l6w1KWem-dtiGDnxqmR9*I+r5sZ^W^ba~I9{s6+`slTOmA^N+ z5&LfYqwU5AQM=5SP?$w+Ga(Ex>4D(2fA60nq+|tgL$8*O0E*$)HR83fa8KDIh5F)~ zjp}DkN6^1st^DdXwb_R%p#;WD^#C-^wRxy(hb^b&n;bO&-f7G z-D|!KZ$w8D!Iv83sdhfXYYewc#nl<2bW~b(xKO{5S_&$db{jIvP1|`#3@aQMDVJ}C z5~(^eC;IC6w#Bm^H;oaHr@NEj70XS~ZC9BItHzB(_t>?c^b8QaiDQNyLO}IKLci5Mgf;Npn>R?9~Q3=cZD&y33e%#yi2Rx z&s3=h(-8e&rzzDt>zI22QWe2?7Zq-A1W zD6Z$;ouh9?&%@@?lx_W|r36v|{11qpt0(hiNP{sZb*DL`((gR=hu8pOTD9LS7rCr$ zj4KTk6F7J5cU*^JT8#ev?OR?HJZ@s&NydA3gSp`}(?lSUka2FY-_!Go`NgB~-JxxW z7Q4VMWCN1usd2^LqF3mezJI*H=&@!^XzBJyg4u+%T#fvI=n-layQ_;w>5{(efF1Wg z9$0kw3p_Z~^ZOWIEobEKU42$yzO@Qj9!24U*LKDeIIAEV~aD7U)bey z*n2`So?VmRiC@xf$k^|`!FJ8LhEGdtQ4Us|H!%dWBNdV50JIFWw2bH&WaHYNqcs$^ z_%M(iiSt@o7=#anFPGnN_0Fty2@A{2OI-TA@e2E!MaK4I$6G;j*AqXrg6a-o2a10z z5P#O?42oW7{E3(Nb4_JF6eT=sphFUQxgOgfdu|3=yW?6}$yrJ7HugQ+Y)R80sL51( zGCW<~`96>U6M~te-Cjp+*j_?rc{$5lqdEmEffjHG=xj++ zKls+~xHnU$Egy_dlDrtET4v#w`tl!zli9KCC0`eB%>gG5@9ero?Z$c939qB<@r)3D zD0dJOiG+uBX)MH(oqp3paj3a>aXi;l{aY@@(X)sUA;Q$;26%7he7=NCaNN0j;G(!6 ztI*J0;`_<{s(D<%w}_8|0vkeOU(l0!iqB(zub}+2aG3rjmMZ$di53CmCY;B#6Koto z7!t7zFj=!-RQ-)Ko;ExByo!j=KpZ3!iuHg@<9k~-efb)k3VtSx|3`7h;|qF*D2|k) z)ZYl}26HNefKErocU)`dLJYbLU8J0=&RvGQem(*~Y|&vD=n`f7oPt6nP|c zGlL3iKHDfd{-s5AV!n)vA!D4Sk54zqG^v-$+ZnU&F@gTx-pXed_VsV*s@y4(8jdPG zmeE93wPnqyR5O5rBTI^(obnQEoviQ0aeOiIORo6~O0fI2=d0liN(MD(Vo9{8sidzb zsOUu&3o}*SU?`8$K;A3#jpmRugB7uz4c<@aFW@&4VL|^<^Z+e-lo=px{c>>H_RZ!w zzlE7#zWoAbbGAj;$#cRVtWgJwR#@u9P`PAbdd`7-+=ege{OZcB0yphUegSC(tNNr0 zCC$~~0HQAXnSHJNjfiiFZxRgbj`yE0sT!LqGJxQV7&e~;NuuJxnWd9V@Ek%%5 z{bpE&p@OyLjj7T%sB_#%Yup?$C(!nV03QHFx|Gg|#1 zlgOgmJ4^X#7QT^eQqwji#41cDjlwtV&fsbG^;%jE(C6`!weUFG=<7 zPb|z^=C`TL#&6!ubNX-{@zc40UFqJ@X%?a5d%z^N*FRI$zJ|;6@f2gi0v__r8PY)2 zGgoUi;j6t%9!!X%`M@w)mNLimd5g>jj1NO$Z?rl8xVcS^zfSrke`VLU=_^oEXtxFy zH8!+1lE-WL*O{7jnUkx-#7~-1(mnqK07~zi#4NCMa-(F*je$NACYiMjh)XT|t z3xR^^J7|oeH2WCKh`c(0jV|Y3tl{TFT1+xJ_g`dsX)?hY9<-GuPXf<;GgA>r+A2ET z)@@CEx=GzH(f>*`cNe%OsP3Sl$jaKX?K;2Dem9>h3SMix-(u9Sk?7-S;Iq-+u4G8}j-{ipvcdGvr1A-_+Jf=?NR)DVlfn1Y| zlDPNxviZ%V8%zap+zGq~3L-i9?N}m3(JMIPme%Xv@4d(U(DS_qkW+LI=qll23c#NmYOW@+Ix+T9ui|t=p6XNdFKWM3(Ueh-|dnmD|aT&aY6KNUfu-AiM5#< z9@cW{uRoIlA7hi8+6O!$D)%H-YU-e0Zh5#}p$Iy+lO-0e8tY`RlNU)04Zs#0i{R(| zdukTLMxnORhLA_pJ(sp5Pv(h}HumW*_5YjH;{PwY_<#LG zwLU~-Jrs=r+qGb$KU6`p?6j1Pz0u@wQ%o8#5;FttU8m_K8$@Ry&u25MPkf=Tl>OxN zq5HZLbdWAzzs4D!mN%N!Q`&go9~s5J_OM|#`2=hFvb^f;X@gO9Ez<~?;#Rb zVYfnsy?LUWAfeuz63kX5dDD|m@XC>2q{emcZJUh_hFR}rL>I#?>i|U?fb&=p;I};} z?JQMSTc6U3>IvOWXa%)EwoEPVlncu9WEt#hu6)XFu4#I<4YW}PD;_heov5p=wiHk&j{a-d@ zXsfcDBP=Ui((3#a_Zrp`xt0{HUONI4$2qA-qIlwIY3p)J zJVXch9@_i>)k`N%?5NNIi_DxQT%GHXOO5eugvl2!Zr)(Ka%*x##wlan0KapX>K9Ct zoh4|ul6&p+C%)*TL?>-;D4ovgih$*C4KzZ`F~nm1t;5MolOIWRPDv4{TQmuqD=5M< zS05{7l`idr-+DYJ@wY#Elm!0Kb~HZXe*k{SRq;Yco(T9?-MCN4&bPJE&x-e}_g5%y z=;Kb}Z>5#|kHS>h1p2Q6Q0d0t91UoCJkh-mYq#f`PFOCb&i(60DQCDYq*Bx88j{s# z{FzsTh%BLC+JG7z14crmg_6icWj?~6rRrMX-R4_HQvXrRKUhiqr1^NmsFsno;g?OGf2QzHt%I>_55 zwITABc)_L5j@c%Ob`tKab;iM)G_QXvxQ>#ea2gtV(H( z7q~K^DVW%O-&{w)?)f26BFIBbpsu=AYgVG#3VTU7zlCXiva#6W!3Z3_TCgXpx;BoT z+Z8}85yT*2*Wm+q&-?rh>(hC4WmP?2r7_@+J1{iFp{ew~26*=hX-ZmPJ){PTca3z4 zH$3IQv2FXEpaUatsHJ@xCmHP-F#BO_d2F3}_t6nQ$58>u_Bdsa#_6EVfJ`Hs`_@eb zi)9<#9Ar9SDCxK6mH9PP_f^+ps77B_OP~GEK*zI1=#u7 zX5)@9>cu1UC?Cm>U$ltI8tPt1^;=9 z?kr@ved>XDpK~}mzTMN6d?Iinkb3>8oEVvW7Pj6Hu%p=DC2}&$=eZa-rkBSwPIh?~C0hJ;6g=262d5p)Tz) zBZ7PdwD~^D+f&3!-N`;2zYqX!6)UW_{iWoVe=-gNwrR09(5rgR zaENaEHmS61`tEQ^`353O<^IHf6!CFPEz+ksF^KA?M4;UYE$D;F|Kt%E@O&@(>xJ$1 zx(;VMQ0RvuZ0A*-ao?YR=sZ$C%-gL!g3PN>kGE?_!M%t>zZzF8jgK||NiQ_p^vQr_ zVD3XM=liGqk_MMgfB>STtG1S+^cy|^VT0tEt4WHf!N-3FP!s+>pn^-NW+7FeSrDK| z-`j|NQVBVoq;H19Zom28*-Vv9G>CY2u&T&(%e}x3kIoVwmvpNmzbC8&Y-IVyBaBZI z*$_JtEuqiiIS3X!D3XaDw8gafkP)wcwEUfO61o9wQ`r)5Ltxuy`4V502dCT z^tI8kfEg%asT&$TuHO{v66R_qepwESJ(hB39jLLKI3Sq#Ys*VKx3}Wa$zl0>rp%1P z_DDnlh&NFd5QCd_C%omk-`A&Q((YWGdZWIFllTXY@+Xx2MPEmBsDd3lxLlmS-LLV? zw;q_|chi~gphc~aa2bY#U39~5CGkJf+}DpdMHj3dRxThF>OCWh4UKYkW{%O_3~{_S z2sX<=bi%5QhN2#m;0*!fhIGcCUpU&ce!F$_2jUZ8@76dFoQmDuIl)lc{%gN8F5t8} zUiiM-8~Ny4JR@oO4z4{aTuH8X!(3syPeos2)S%3U9tMYMG8nOBw*j

EkZFao3YJ zl_itWVykS?U)?|SIDYqW!8)*)ot4z<=#3o9lF05?h00@9$4NQd?%~Pdl1fu|ZgOUb z1yMBhp`&G&2oI)q8di3VHnf_?WyLjgoo~4brYAea3G*fW*-k!2k3HrJt(w=hL{H=; z)h$(GlRr7gyieB8pT7XDpsAW6b0sj-VDqW)TWFZue^i$9 z#(5>*$Y@lv%w-A4jIIDJZ@~i6_aI&J>{lnR{=fwazSS6x4?(Wm)*Q^?AmQx~1N5<2 z70Ooj3loAO*PVC10tyO#zRG2PrQN9qr3S87olLcGG{Qz^bV1K5)b$yxAZy+jcJdRV z9O14rU_&ot%;_{PA7@YfF2x8FK!GuwtZu&tAHmS7un^>*;~NrBCg{Hfe76;@`%SbDXUxUs?pU z?EY1$o2!)V{R+RT&TVd~@Uybzo7k#2trf-;8X3g{rk0;dyLoE=O$_wcx9ca~)A{Bv zKXN}96#03V$hoyg%Z0VRfS*>Qf03t~9E5@%42@#iyk;O*q7d^j1V15bbpsWahCC#yt*C1tR%AQRnJ>~jf|bY z%{n^=5;TYoHOxB(CTM*g&loXaa>{I|T3EvMVTD^5f;!MX!B9S^>e?bedT?f#Ygq>E z?3RHj3EeK7Q_<~1tkX4PZXE_9uIH|fY30_d1YNT!Ajg={U}Bh;DS0|vHxxt=#oIk4 z%pEj5BNVQ*sch?1P1yzVH?+R2F3#k?d)bl}k4!@^qVC}I`QnpQRB5}!#rfq6ZB0Qi1f>}IpxtX0qSFz>&C6F4do6=;cXdv$+^HBMH?rVL9kk{1X*78pT z4yiYdqf)ZmXiDGv+1G_W(xq4Kfd<%8h1rBUW%HGV*_ep`8rW2J~%}HIzx9w@^AKx)u;b95QrszsCPk_TuKZZC>7~T0O&dn6XL{)C;4 zEI{=XY^sd3uy=Sw1@-!1zC1OMK8qdH?PXKCV0_Y+K&;%YSMhQTRO@JOf-L@Qg#lYZvjHIh4sjt~it;l`!L~Pd&m4JO znIe4XkZI{1WKLZ7+MQV+<<_r7sF-ql%5!5CT>{YW+|VXvx3dJ4UUvMzekTBQyBA44 z-g4>OdafxY=fm1!$z|zEa`Tk|L#!vrj-grhl_4xT@)X0O0)lY(^u2pz-SL3d)6o-T zUaUVDN^{B=Dpf3-C?Dk+V12J=d}eOqx{G=X@1V1f;|EC&ea0HW{1T5!3; zIPg$1jpPCIaswbrS@8$#v%s~-|4~T%$rxSw6UooF5cOms{W@D`)`c;y7z>F+P^y5i zczK*$W3z3{`>IbjjmGAc`r7zo1GYc3^=AEkIiX zc<<^E!ayHq-Hf|1v-(vQOD;)Ro`RaH&U^*!yGYN=!p``lCiDntt?c2-6t}5Gk+GG8 zv+35el)UdQHTmw8?Y^WUw{c8Foj{}9*(1Gs-CIxGrhl7l=5c_XbDlBHZVYTBul*cP z*$H5suZW~)oqHmlsOM1If)!yk2@dUca|5RXo@-y(n#GC!ODNVdh@V zK?FZLJcjY>l+_J=`DuTGcW%}>Ri5e!nhGOYeAUDmT-}ztASZe~udf6_FBs20p2{w( zfJmiqb^-?b5+*h#?r{%KV`JdA<_NjT1zx`oH*|L@^dJeK zT2v>)NB`k}oUJv0-$dt4X8mfLy^rlCi!-zG2hu^#$Xg998~G6?q2zcX81QfoxgGZAiO zecTnOO^z_2B#)!6DfyS9BbA=u=6uFu=D5u$ex~FcCu+`ChJ?AJ-NyIDj(K>GAb7zY z1&8cn;o!KqDC*>IXM$xjU4I{2*4jAfZ}Qr^Qr=HD(JA0`J)bm~Jv;SEHICA&!-q3T z*DpOPh@)QE+G&B#)p@W5sCC(bfKce>oJaq>inAJi&wZI0=h;3aPGo={cbSIg3KzTm zMyKPP`hsUOO-Z(#mK0L*=^;4i$35Viz#%_;2K?qme1NM&lYMsk6(z; zD;pI3<-bUn>D$#^FML~Qp8iAQ`(VaTSBLL!uFs__}~;c^!q0vx(e`yOHu>$_D_)pko~Dn5%hSv1C)^N zUh*Lh;Ncotl=t1%k(ckH98jtMn@B^20k}-5bZ(eJpdx-439uL4@tqM>UBi9lV+8#H zMx+0SZe#s7@_(t=*co|qKvxK0E{MWDpO%8L!`&>hXuKntP3Vhb3bpgmZ*$P|RgYfGbdXjqmZ>nd;S?->=t8HBW5dQ&oiHiO#8(L(KV~5*h&|OeuJO~L4_F>XQAN@G zMP|Q~Jc*Ki%K=uI`qupHfW9fFM;eE2AM$J2Rn8|Of}#W)17?3-AOJB)P6VY`9G0$?YlOYq}z*4k_0=$d3n;HVQddxc8 zF=f9U?9caiVeY3X9P($6tT3AvJd4U7+XTBX`84X{Dhzs!?gwJClUo9L55YW)amRa8zKXH^E@e^Xp51N9s05Tf zd>=|IEy=Q_Un9fbA3TJag~&tW%f4K%@L&bSc!dx44g6x5-@8>8755r3uxXWN=uf+b z@NzpDd|omW?sHaf>+{}Gm_vRu4M231dTMo`7mt0ndY`_PQk@U~O$9z(~oyUd^9iBI^E*N7xVyi4Gw+^>KMPCEy1Pur5cx zKdy~;?WL^pdTATqH3nz!RC{qH08i8WB?n*<=?EY+JaP8qn8CW;@UGcyHy>zkEMyea z+vm}xNmg6)@3y{IjO)3`RwvwX;Gc?A6>S)SigBAKvE{hcdwYMSMk*m1uK~Jre5>q@ zz=Cz=QvBZPW-a;ZFh29*c)fmst*H_&RdUbe^mgFcq4QYhMyebE{XSD*{6)RMkC`>} z)Fmc`WvTs_?0^L0$28{}@!FqkCCS9HQndZ0PadOXB$HS9+EtA^o%H&s!Oc?T=j?J% zMOu5g9_B>-mfHaX?5ZgVX{7ojLT))>YW6)yD9Up(XieY9ip%=2N5EP0L3 zkN}7yXybp}I+eKaeb5#*Z)dDu;8#=@wz3ktX?Rst;C9|-bp|22=1 zzLz*CDeSt+$gC{N?t9oMlrSqD_cqqcl0A9pXhmtm++SQ~`3EdfFP~CIzKYOlY80Z% zeXmgzk0}KNq%XmM%fJ3597;(UDxIgGNv?KwYLnAxzRJzJZw5)`bCbpHwYiSU@uu4| z2fI-|c)WC*_3*TH;e+EIf+Af!Vh&HSB;V8d%;CXp7!+`AO4w&1t{rz>eFX14;FN;Z z<>Pw&7S@ewYl^9V;VrqH;RWj4R9beN50(+cPQoVpWh_FSgbWnzH(QtM;?lJG z3!-j0P)QW9AaG3-(#6S;Xh|A4u>f$QyZ=hHp1xSyHuIlb4J$GVGUx2{CCda40V=ipXI0d_ ze=I2NH;@ACZI0rUHrSn*Kiz(ghLHrf54otks@64rUh8~))F~$;`azqU$veidBQKNp z<;ZM&apsW zE=nQhQF49YYO7}@yZ1?I%Km2#e@1ff^7b08>$y9Q4WP>~V17oGzjv6^)mlah9h&ub z>cZ4-LqE>E-}&~r5lTY_$lB|lCp#)bRyjwqFK|F@HA}0GVsno{xw!Ix&Dm^J*K3qK zb%0#dMuulsJd%;9S{u2c|v}4BNP-!th!k0n~Z=GdR~7 zL+7hzxwc(0lQ|b7Rk=wzOVtKkTaNqWA2yg`oq*Ue`rGS=N`Sp@Aq^}~8mj~%MFNaS zGYBD(L(Kq)GP^@y`0M~}I+PCImR*$47Q}}44Igirdu@B0+Qg&^Jbq2y$97?+Pc3*- z!-3wxMm6g7MN=3n(tXe?!Q!eXGWmCP%-6e$_BG12viQ^2w4EIT&x-$Py`k}H7?))Q ztwWa44C!)=q7tSGlAFx6C9s&r5zwj=``g1UXJU=~W5&L{`ci$uW|Vfjs(|lmDl_s0 z0j=?Mmm}E0&@TP&AIkk-<7msM&lyv0r$midw>{dy%P8lMW6^_Kzy|Yu98ZJSIM+6O zX@1({LDevDoChwK;GYM7gvm=wT+s!#BaUb#S97{y1Z*Cbay+MSPqN|ikv+*o)P&Da$-+P*w0}){yWz`vzGI<}i?P@rsPQR4>BrQySsT}!=R}FE^_@wN zYff;AUuERU1alD_poi(I>uP=Tmy|?nAzK@}OvB~v-!|Tbbfz_K#f$#Bd=x^Mhn+0F zYU{0D(NG7^`_CwDCGiO^pM0hdMW73iaqsGHk}!CoxX|24+GX_(#1os&lOW}5xgxLS z4f|jp5s?-bcYmPp-f-RNhJ9QoW%qB3e=53%hxINsi&PFHH)avM#8$=@TVJQ_-80e> zt?k?sC_#B5D3*oj<_Abg#Sb8lx8kal6VAzy!*RZ&`BRU{HqYJlUHGuKES&nD22FlR zmwO4RiW@uP3!`*+k0sod5#*y++Q&bNr})BeFUC!;xCm@^5kETJb~txyaTEp_YP?E4 zLExHBBPMT7do1jnSWh*GSqR)(uB_G)f4K70Huhk)^8HNf9&8#Vx^lyv^&P*0+VALR zzokYeK^XTktfIFRXBoqyP?`}}0v2K7#Z;-5{ywRgs2567W6CccaToc$&})qaQ}5@X zq;Wc%jk178NQ}t=D6UhASKzM`Z8Zg=Bc+Y96Az^#X|hX9zT*H6_Yt)pR^@_9a-)9L z$qN5iBoWjoOMIo_(f4FxY_bE{4ye5l17D--4V%I|Gp`H^v8&>}cci2BRMvL4ecM8c zXxEY8kGB}_4hFdGd#{cnZC%hm983g~?iyTb5BZtDSBxlW$>hw0lwN)Gk7f7aPt|8R z1^-yCCKCsGx!%@6--CG(TsMJMa1F(Bi*MA73L2FcnKxu)6&vz33Dz0}twjwss@E}U zP*U(i6wB`<2rE*bw0WF*nKxXuIC%agMRCL^@%;Bi{XxI=%ichxdGMxYR(8hKcIf)|zp~;Sr{2S$RSS z^*&wh0+f%MO9V)bOgZ4yA3s0!SL=^w>X!-?%8eJFKXWV9p6~EW1O!1hNiR!u5b6FV zQIwp2Eb54(<*DzpixqaF3KoD@jjaeA+0kNKHAiSTr;mgyU^FJ+!A~>*HWVr zZH>8955TH37siT#a2?8&@^7z;rkTa%f~<;TziP22Y^R_VUJ`OlQ2D>kwL zdB57Sg3b?Rt;5gbOQwt77wE3kyW~Yeax37&Xytd3t*jo=`yH$e^D~HlafR&vMefV8E@ce&m{fvVip-*N2-ZfB&(guyH7sO*^E5HQ_wq(Q^wuV0*v&UX8G9=pfYrv8tmS{M#gK?AZeps?ua zE++1m4uWlKt65FFd$H6Sm(CUO($g+~%OX!Ec2HSSm(#*S zc&LA;?^WkLcs8Vvt~|;Wjnb%pb-iGqu0nmV(wh^JB%F3b!^`OyRE2q7rQ*HfT{+#vX2JI^C=Dcz2y4?y4w~&7{r!Fss{4pjXOtn)3e^Fg1^3#f zCpxjjk}EnjoA;g%)RVUy8$+)u-b-AS*1yf$3g6Gh^yu_+~pe53DP(SnC-ccc4)xg~ui zIE_~M#)|*6w&)^ARt9Ew->w?J80+#DSv$lOwB65S*LK88TYUA~9X^RLPbCX?gxeWK z5PlaH1MDTEv-YC$_To^*srO`TEV?Y4**pCGQF`+U?~gt?BL0v7(PcrkX;JpO!fk0+@^ggfvlT*wjR2|OgTc|1XJye z$A$-aZ}t#X_}9iz&<`>-L$JVsGkNEhxG3>4sFM#vD~n}Mr*p#B;!bOA-6(uYN!5CX zJt$I=Y6b*pJ>KkI|5!4;+tF;l9P82pS}|u3<2Pw%{;|XyV7G4Uq|~>;KPXE_+}j1A z{hZAFUr=_{EzUnQfAlGkPnM^48*>`WVMBj1;%}yGX5%R!VZEQW_SEq|(kuKxImc#YJg|Jz@k9EOtcc~m>)tq;*wG9WZC_PbP+*zl* z3}T6@m-5OT&a&R$#xT1R_D>G+X+T=hO;SVEe|wdtlB@ZBI#J9TJr_#KNyRH=|9uP> zd4*j<3)#UQ;SO=Pw|;TlU>byc0R(3+@14IA9R};`*t+D)UruuZRu$GK4!qKQ`>p37_q_&w2|cQ=(pci)Seaxvrfz+f@PAmK|CbN?|N4n_1w!X*7nj-e zC@$B$5LA_fpFf=F*f@sn2K)yKMmIzBpe2Z4;u0muYasD#)(dMly$JSB?8N+5n4h0d zLOWmjf#}8oO4#d<$8!3ulyqd8|B z>w`k7z7HPxV$aG|?{pt3rP67!50m(d-RQsQDHIWvy6RVGqtw!${<>{XA06F{)wi(w z>&N?=`+WIc*5&;fAV+CG;dtE%UC4m&(aMirG0IN&kf$ADgNKoW#ik7rY|)@Z60?%> zKaGvU1TH-KT{Tm(B7wQ#IJ7?t_D4OJ?%8PJy>_lHTU<@SyzMO<@vh)gc)2d@cBVj8 zeg?B0Q?}DGFl9)ICwJgE;H^6EoOnn%&_sK)XMdVQf_}~_)f*}&d=oZ)-4gT)dzw*> zI!6Ujf*9YBH%a*fO0{M~uBY6KcGIMo{I|B>x%Ig9Za&CRy}{PtW3T{M9RRqLw+Om= z7?G=ey1`(zH7Gv<+A`(Xo=?dTj7PlYyY*(v`%9SU=&|F1_d7HP(wpYiM;H*H?zAx# zjVdI^kk>`3{UnnhPnATcjMfgdqR*VL^m$T}&Nieg*g^DITy4djq8b`7vg$nvW~an+=$YiF^(a1WL@-*%U@Sp!7I^vz=QHj_*K{dAFIYYi3)Ue$Z3`#w6Dn~us!kCXn3zvU#0a_?LZ@uS{n zea*aGQ&;;&ue9dWDU8W;FZaJnb}Zk-KH^dS*3!!x_MM7OW|~j$G;w|U*#(NRtFqUq zjUvjnyR5Q=OeGj?C-je5+bTUs8KJlOVeHC00`sUY=5=FA-NieX9+s-r?~7R3g4p9ITW8nQv+R4av{_;GTm|m9rj4DlkSg@%7Et7}C)~B?yAl|vtF^WG z`ucA^gW~K-uplysIzaOEzDk8Ia+u2Advhp5XVTVe{eGQ(ElNn`hxG&(+k4G!j^MdG<5)G8H;=b1iU6GxiyEl;y6-OdCjJR|#;%LyM{sU5AHPoaFMOtHIrr?TJ598r@zu{(PQE3%&%yv!c+uyh zPz||$CHTHnp(0O@m#W37&k1U^HvVTD#)0&+jt(Gnnw<(K9Ddy17nQf2+t{RRT#V~O zv6n7A7t;;8FH)`T4MJK`6UpYs^On?jqWuoH!(>+MWtIHE=%*dNk7f|3kD-}ysLvOe z;gE$Sp|C!h)&>P}^!#8t8U$0FlYqIUNM~+V-1#y9o`utU$(k88iQMz?G)+_H+NlK` zRsLid_0qRa`qr2W8+z;W7a)5;+@Dv|>Ba}VfL#9Pn{)^o*bkk=ZgZVNFPTOjB(I@*CqP@no?_cURQbH*Lh45%7B31i3N6KIaA?}Y z5%-Zprcz_0rx?V$2=Mv-Ys9ApjxH+As?-F~rVbDjK7=mAY{}$O{U~?GG%)YAp4UaT z8p9Q8`$c*#Pizu@PZd1_CwVdX!D@Wg{&LQXA;t4^$w!!b7_O(F3N1P>zDRcD-}+1nehSqI;yS>- z74mMv2p}S8tvXJLuRN;jwC&$*yze+}Ygr=iz(9bONY9Zpw$a37WyFH{JQuCW?uj9A zzIx5Sf|JVliyvk<-9GPvCe@V_Yk3 zMoIU6RLBQW)cA$5NY=iGU-iL{t#KJUlaY(_@4)O_BGiC3*cm0T!rhSIhHdE&lEFrc zifQ0rPg2Zy!47P!@yrnAs~(ci+|dO)hg9JP8(Y2xa_h79fsW1B_Ma69;ZTvb^|FNz!98(i#xqt5Az^f5*%O`w-0nHHHSMt znRq3rHWe7hC$C6~L^0zKCNJD1WGIrc9Wxwt$qJ!AsB5`d?7^vfr2$Bh!VgK?K_U_Xtf{ zB9AqYSBa}JdVb#_Q+k(4%wR9hIkSH((kmVh*L73eY=t4S?65okqjEZFM;B+LADsO( zdnrdDP+2wMOjV`c@oN4eEHJXUgG(`=!(vlTW}`ceJ|OS!CQFnDSJ4vT```pd23Va5 z96gcxK<9j5yT(E!omm#F~!L*HP$>7IGn00 zm!shJQw+TZuEAYpW9J!SiLY(>ZncI9?ZMAKn=cL;tRHYBVJ;-|bk6c?H+w)nX;3q5 zO{{!B7aA79QuZy8KNBIDC8i6oC_oD(NX@0WnPH8UvvcA7f2ObfW3hD;J|&q(6MXmK zCuesEoU%xHN&OH=wp>7mF~#TW^v81DCDIEAcD81-6TzEMNDSHs(Hs$ueEaTO$tFmq zs|_80v~p|4*K!3dgd+|-_VAgPEwT>n37f;cBjkKXC0cj0)=}O67%v=UxkRdVPsh2e z@Hn)W{6r)Wei^1*K)ycmgUwG|ZeFf&$0f-StoE^%BQf@H@)2~Ei_Vw-U*aRimscgu zQdZ0kvQ$n#7nH|-fRmNj#N?wm+{klgUGcH7drsv6tgPM>pjIFeEhPC3mH{u@?vG%7g+Hb8mP*=mia@|=>30@Qk@cK*ZH4=zOpd`D=cC_JoT(JU%J;Q@-is{B}d)6 zKdP*x_|Z^tezK}+_iOcgq5)y?lJxFc_0!8MjlbWm-O8`5-}+APUEho=z`3DgGS81e zo^4>+kj_*IH&Wu_*=#S!1Xk&4((H>&qsf(68_+VByqw&XPNeFRh{r)&sKee|eWrY_ zywzf$qk3^y&glEe&W^FlS6yFWH@VAhnX4)^clo#BM@j}XYBQ!C#u9yBCM#** zX)u6t?Yg)u(nKV!-P7hptR-#*O6xYbDHef~0bbG>0)~HZ3%O_!^#<-CU3S^$%A#JQ zC);TF7d!9PA`~qaEu-QZ1Xdhbw>$gBDjK+e$LVe5Q_pN0e17)YEf1sncd)v)_t>3- zt3_zgjnj9MUrw;<7wM@|lT-YUg9L60Zj9B%o&V}OB5nZE?&o+lI;7Yy%AxdBC82wj z<;F_wIbtB^p$yB|XMyeBXGp^oq(3P$jEH#$*7!ND{@d|>-p7K5nz~T;-CUab*Lba1 zF7vx6UjRw70T=L7G*!m&u$gh&A^E>*9QjO(aKU|}?oWLj{j+3#`{E(Ve ztKt*!gq7=CP!GwIq^hph`sK{5z1iUc?NOiV9m6LDP1iO(owJ^eIY!#zT+_gr z)ej%}IkJYke5NM#eU2&kwGF^Ok4pb1xNwQg$ky0B2T!JQ zDm>(^GTaNxqGBmfst3&zi9k;c<1y3Lej8fo$#}-6x!b&Pev+{RLe*pm>EVH(ebA&3 zz8NHdexV|?fhli{F97QDl;%GA!2?CEG=;l{UTtEteWGfbB4O5A%2k6MRq(@~*C|J> z%2&_eEI%NP12Io zjjaS!#?6v?Ai#*(QbPtDfgjE6$f5|O&muXN~tqZUlMf<-Tb8f@j1eLu#sZOaF zEdG0JZVEm@ypst>mzRHC@=;wBH(4V00eofi-82(&8gOKcUAg*%Hh4kmiP%REVT9CQZPW_gbLoz*)^ z_%DZ9xqCDxKHgJkl}YbI-5vUsXhiucjM8Pmn{iKx>y4LU9`Vxd_M5APRXk}-!?QkL z#}pD)=ePOvxl(gOh@83P#a3g)ags49Y)T|O^rC1F| zIES<$f45+n=%4vb09FQFLY=05d_)Z+1Uo*XEIxw2s*Sh6T!3@?3S)cI6A%a39<^c( zouhCaKd1wCA9A4Q2s^##=#ZRPAKbU5A6lQgMh{}?AGe#7SBo4CXIQ_{xm9g z<|@StPOWC-uas~JcoqWizu9P0+UR?=n ziK4~u_74QurKbWAjstBMBk{Vj80Q!%CT|M!dGw(haJbkGcBc7{H;AllT;Z@^eR;V` zrAegefr4Jac;DahG2>j75>ILe6uF*}Ka(o24I{in(w~eIst;9^P6%h# z%t=H{jqM&cb&26mn|upDrPTi@Q#aA6T|z$JfV;%d!apzBvKzl*CEu+MhwsSv?X9+8 zcpIyzyfRTZ;FPMA_r>FjUZS(cP5#>%Zn(Yj*f)yd zZ19&p6P~8;NiIC~8lp4q`s6^zo6SP0ItD2}SV{>oS8v+9EG&)Vge>Hdq^h@a$)^pL z-^D%I+U)b-LvggDcP{NSEG7`9RMi9U>F>B}5VQYXJPoD+m(1g9u<1lX9wEKz2WvIm zWP5{l;{U{T$$sPdH~N2Rodg-#e!!$nBSX%wfT(v5id7DAf82@r-#~aqdEouPGEAE9 zX`Zo?hT|TuepOwMjYnr}mAy*EG+s4{ntNhTUyu@e+zAn9En#^G5437Ubm?E8%aY(d zQIa#@n?Ku8a4V-mk&T=QKL+Y`-rC%gCSh7PUfomE#HjJiu2d&W>|;&OGF6gS0&7Zu zoTR|U5$mTd;MLRUI=EV!oksOXJ@I0M9Z9**V9LlUj--1s3%4MX%1rQim@lkGf?6gO zr|h9JND{=nY|`)}K#+#!#|wlXXg`#DA%0t9KDqso_mROSbbRjI&!KugLIZpAu|ze+ zBXX1Y>x0e9!Isby;H@Z<+glTJQ>e?ZO*=8Ed$moC+2+I>xu`$>LA}IjeY!~}W;3W^ zETZ_%!}<2*Kj?7{zjQ5H<>6Q!rLM1JG&85sEn`OIbo@_3_NR+C=^Vb6P4Xr^_JBD} zSANkE`ntq>eYFWJ%1F=)SP0>1MFXIYeEa^Oo=S0_Ofq355qxkTxT60xF=p>4T zv=T?6HPu;!Rsc!{qCMfag}feD3cW1ZZ@WVZH>FV`azXB{?Oe|>vp(GZviyLR7aF_K zyT`#p$)zfltgZc+hD$+x4L@Xgt7J9TZTwzek#7bix?+^!p|i z%RLTY=^hIG_IJR)Ow(95GlZ;52^a)~C8EaUNJ4*M0Kr1A{)zC%j|Nl8?93^xp5Jpd z7Tl=5Mipw~@#{pgM~6;Kd+4*~(r?j<-mla!il0T!9soh$92OJC`u|w4z23qQPyVEi zAq+RLIs_37@gKnaeJ9tB6|KJy4PJe~jE;{MH=Cbrq8F{mGTD&s|C3ZizeL7->{%Pc zPPEPVz8%+OAA|+;rTg0c!M7L}Qh3RnavC$obYA*!#Qrm zxL+&u82V@K3Sc(kqQdTt9(YGmRu=6WZhpD=HOctef6C~|zF-@qnb0dQl@HHRpw>*W z)yuH~2T|Mr94hS2E$y;9M#<9Y!+Q3Gpo@k?GjGOK%ODju!6jS@F6x+-l1#;aqu*;J zm3y9v7J7Ae`GSsKMjZ_rZ~py}j8Ixv_Ca(2N4M=5>*d=EIXR8gNg;GOt{ry@sT<Qk^egrgT2Z#=0m7s`@x!as%*}Z)FIF zRHPa%)$W{F73@8>A_9o-hqj3wrE>K5Ut}d|oZ?Hyv~g9=J*^9GXsEZ?>yeY(d11ls zGzi*+EZz;DT5Z*QPhEU=1FIQf`99ssbZT|X10}zl;-qZD8kwFe4EwIf)sEsE1+yW3 zn@1czjC_Era;>q7vFNE-Wepf=?5<)|G;%)UzgGQTJuUh7ofChiKlo5r&(@KsQ8rpS z8V4i0HJAwBdRRn@dkS=WHZx}0ux!_&9UCiv;YC_eMylONjJMCrD&6pMkNqTQ<7KFU z`AX|}(sYYAflJtaK$1Uvs^2KtcVcEs?|58a(L-6BC|!Y0zCGSoubZS0QRq4%*^qO? zZgUx{HUApfM;7Qf#9Y+#E28#q$XCZz@wzZer3kFcFiW~Lqo`hmfIV$U0KI?xa^2VN ziT31uQ4&!^jZA z3N>(n-FQb?+~4SXdMk@A|+0v6A%hPKfszpV@mK-FAFFTNUszuB%^!+S> zAy~GqZ5cjjMCN7bAS@T}Le+#_+U4q)pOk5ViPWPPaPRF_Dg$%psG82|C&xiIY)@w= zt#wC@GxBk67LoInpva0otu_Iuj(bVgjbw|F5~DqWQq1CtNJNu1lQe7m#|(0vX0MI_ zLcpjpxG=iJqL&&`0GM4bZ$P;H_0L5Pe;>_Lot`$zUwRyEuj`{t`yGyYW7KXqGv8g6 zW$~#!r*@L}@dr&x>2H&lO4Huj1+8%IwQWDn%cW9Jf-=86v~rawJZ76qZt=75?GYpF zxuW>UhVAGH?-mRD! znhaHe5>PivHx(;F6EOnt1*PrsA4YC9i18ekKd9&P;UNZFmKPOoTj>$QxCCVLsRL)Aa%_11;{dh;$hE5!dRnA*8NDNiKMr zcs*9%WXj&%mDVkN>s=fQ-i~tvO%~l|B!LA@NgH=YTu1xb_Q!{3jY5SC6WPMpcj*N` z6dW{_eenHn?KCm7=sk@>mr)cjc98(zAKNRoJwue^;Eye-Bdpquk9Z^ z+<6NIA$1rjV4yImMSMY2*?+KJ|8%voz+p1<;p60&=qN)73A8=F`WZ)p#zj^MR12ZX zN!Zpg%R8--f$xnBX-}7pAQ_6%FvYPFles~emDdK}-#rgzZH550ymvsZKFySL_9JPa zwJv!5mmqUm)qwKH$6l3Bk5gd`_Y6IeMmXG33&=vGS&ymIYY|~wT*}iAhi%T^vz;x& ztB^7uMXNHUt77C_so|0%8I5)+CeNO>Qu$~Xs2&85*7qnC#C&^DM=OqJEoo)iB+cGe zc6jmeqk89R)E?{Q+1;hBqgeRX+LEeA)UMz27MmVjTjlqUMx&FxYVCeS3yrxB^i?&2 zE~dR};CdL@9>;@gszH|o!rBHRgtXd0k;fhQ2Hz=RFFU2oC%c0<5-?M}8Yi!J45;)H zVslCflFStp5L7tMxz<=fz5#I+@4V zPmT1?`&+u4#Hz@~b^GU*UO;K_@7C_mMOOZQB!(2*Q1l_q-sKKqWNz~rUP4lq?to^ zm9R?Y&3b3e9jfU4Y;!+KPuZkJm9wH6(761k<7%~deCTOVOCvi~igt=BK~QO1W6DXF zDeX=UD77cM3p}$=DL-Vq-nXM5JYufjQ05VMo6r8^$N1Ljp{8?G&!SU~{67}CDbxt2 zY(5P5fMVY0!c1QL5oL2ZR9a6z9hmmJ^_;JENyn}P-L*1AoQ!Cad3|d&o%KIFLsV9vuF{f z6I&^r??PP5^pIlVUlqJ9c;LVZ|4uy*YyrSj5UIQs#`!J2(ln0GP*La0Mgg~}NYsN% zAt%FzY3+>z0>oIIR~ru>ZRX4N49$XH-&={W;6&h-t<}NYbjUBpS1`xA9j}^ZiCd1D zFER_t@#_}Y0mZjByGrLxBeX@oES}>TO?~y`N5Qu+>SEOH?lvE`y{6v4^@scm3y&55 z@m9+of{?c(*JG+U?J)wjsF}|QhiA=uRu73>?XJD&*9B2l=w)i5@W+R3-XEc8-dAy# zwIZdGF8)+McW1B@w*?$CKD%Xrw0)o!Rn{tHt3BP7XK*#$mx`z}pPJv+q_fl5fq|N| z6N}QM0@GRt)QSI-smrrPSB0xJuF5vskZb+g#ke>$$zlsc+-dE*4Y-dN*>Rj3&|DG4 zrvB2hCkDG+gub7b4q%#xtnRxXV%;`cZkb^5>_|4yz;4IJsmI+ zq+7t^?--FV7r5M2K83@3X?43gY_z>|BE`>6y0CDLQddRE0Tkxd&z?g|;To>VrrRO> zwqeJWS^=*QJqqZ$kL!LY_{$n$L$F(MXDd3r7^}yiR9`OIc&9A(Z}#%7C>Dhy;Q4#I zV0Wq%seqg9tR5jwZ|t>90?DuyC#ct9f08#VbM2~|GEN@%gQV9fTpDqQMSpjp&sO_a zK~4H-(~6Wlzbmqf(P9UCT3caHQu9MAw&Vj^j9;adGyCD2doez}N611Z1Eh{>>dN;7 zvP5Rt_U`q6_p;yIl_yC&REuYhvue;13GbD!)W+vMJR!)(bV2+mNt?y}id%ajimt6r z`AB}Nn^LbjIQ1h@!b_@-lS_k+ySdax-)c zXG8iv|1f3ASD3N%fYLU;$w9<$tWWWRMaY<`Z511|Cm$DE>)f}9RpuE-17O#2n$9TH zfP4tbMyipOauTMeGR6T9oylNV^E-Nihd=u6q#EIK8rZ;lVtP@V8di!pNo>(prbB#^ z#)p#63g&)tMdE)1A45Gz!p!rBV{eq zt5WD5+vlf9JlURL7}Ll`-FZOuBXhQT9~WPw?qBY8Yx}ew7RQ(D8}??ZQGQuEg54Jre_#UFNb9L87>Fef*v>I&*IPi7j< zSxy!B>YIql%hU#bO_}HkA^^|HKmGi);dzB4WuC;Y;?D{MW33zhZ z#ha${d(pX$BWQrkiM7+nQH8wGyR&nnUD!O0E>|!U>xVXBd_`%_8(A_hI=-BZN6dT3 zFEIqI@HAc2pQ`fQjAT6Q;xq3A(eJ~{EpZQR9(1w=XoGkWFk--)Xg@?pi%@BJe*Igi zn)<2)-aW|gq#d)&Bgty7RT;jsovU*z4)U!tk9>L*U4LnwCzi|ZVMGwGO{;`*%e|A| z^lUl3O6C8yx@wl)@bFY#ra~Hfus_PQ^JC%xb`CZrV&6={5yEcSK|}WsB!N4vA-dn2 zvQ=OGkzzZRox!f(I`yR8LJ%BOy?Yjind;8$oyEXWO+x55m5?duf0fj*yxT=K@ADBQ z+y7mw?@mj+a-jcud_8|llz@qHx-eMpxX4gFo|?v62bmr8C%VRe4~e*IS?=7SG1Yjs zUyE)E3ax{Ea5XcTw<61fOW0>FOLEt`zeqcR*d5~+<355p5r?fXj(U{^cHW`4j7)`% zn40sH4<{EgX)jHMn&vuisG+HRy!WKxUD8SnO`rOGh}IDlmZAZlwu<%RD|T7_aCr7X zL+9cjArj;?a}LJ0Zy`2?z_fXK{#cVQPV^*CwZ?zyseT#2l^OW#9kyUI&Vu?Ni++(x z&PO^>v&lI7h!#=sVE*vc@Hw$l@eop5iiubDh0SSoxNeS{+k) zxfI;5uvV>1nZZ{zk{GKBxK(gX&mAq%$=kbh zyr{x2GUx+X95n)FC#%HhSp~bR=<$}#NM36$TZwue$zJVy0_lTr1a_f%bo88OR&^^PCDOL{tiaOs* zM}bzJja`!{PH0H1G+GFuBn?21nHu_#DUBa<*GcL+y%(q8uT@PJ6?^ntWe@bm4_*D(yt&}(s7n?qg+eoZps%oM zkF68`BjcZ{N+I<$4Rr)&QQe`b@QMc?c0_m|$IMDNL?6mb;c~DO5mUObNdbb$1D_H? zAK0SZC=952LIpZG90)^h<#XCdhFIM7OFP5M^5DP!A74Nz^Caso3D^X_m2IP@F+cYV zICAUC>MrXZc4_Dh!~n98i4q9APe$R0`C=}As}|&gj%GaeHI8p`9E>E73%po5i2_!U zV+db#Ip(v+HZ^irmBCYE}vBfC^ zvto`Dksy-nRHH=n_goXt12fcx<2m6kNg0C-3D`_$d69NA=gm`Nzl9m)f3eAOyB?5G z?54JYU<%mB<3vog`>Eh4DB}6secugWV4vs ztm4g0F{pBDbvII$T+w`}S^83YLFgZg#qK+1t|47v7jmIpV=I5XA5UCP-UZ;`U2oNX+zmlZqvP4U)`>)PhL9&-&{FMOJI2e_z)#L?>38%SXShYA!X z)T~!k;+AiCV}$>aq_J2hI=CJDY_%RvfCy3*TF03pGvoUU^%7mnG-Kw-pPhvS8>pXi{V#1W6+1i-?j$;1f0^bl z;dvbfACit2g3W%vP<+As6k|?R$GV4bgE=G7^Y&kUe{f?3n7@v-<1v|=t@7KCYun8gvXc$2|7zc<3H?u4$oeby z!YxVJoVbn+N8-eHgFoe~`s;%!xqR4oVSC-3fvZ3L&%Lmd{t(){8hVeDZ8!L|Cx0M& zy346dcyjvmw%C8q12}9yhsOn{Bb$x8uJG8sR;&DB6l!a8u!yzG5l|{EeY>nI`K6Qn z@YZ5#eQIyH$?&9om)7UBoaa0hK~;03;x5^w+M3$R-y_?j@AV{J6(#ml+#E$RT0PQ< zZw(!1^ha>IKNp}%SVO;Hkx&1betfWUjY9dBbDL0wxAs zG08m5gokzBD(rF{M^eT~_{d(N_%ex>H0eZKZZ{`UOPj038Y{%d9R!4FCk^Rsc~6 zdNZ!&SSl}DKPkCTq5rVl<^{V*n&z4LtDmhd*iw&t?ml@|`ce%w14oQWSOO!&%8{ak z&3%jST@r!tY3ZP8Q}1w~DNmr43;4#yN^V}t4jl?UMeu}r=74uc7TuiMQ$O;zXaDR8iF8UsR`b`_(yhh$RX8h|~R z${aQw?HO$G<{~w3Xpa(-MAR3v0Lwiuy%#&S!G0!&-gN`5$B)AGzZs$E?o6!`yx-R= zqd=3){zmqpu|4w;WqpG=)zoOUdzm)1_Ia?z;sCeZAo>9*FF$V}*GWHSSi)3HEAY7p z60dK_$9^kr9!Hg2j_z1ciE{K|qUw4J;}iJj#M49WqM`<}de84}A%E$f7{m4BcwY8e zJ!e*|S$e5ao=4Xs|nDfbF_v$F!LK{VUUY?&Xb}*~3Nie73`lJS%KVPc%9z}%;d`g{?*on9 zvZwmM@<{+Hw)^iJPlFCqV^9BM8ApvDY*i*UXcbPs&ajx)wneuDAE2|m9@riMW-FRA zU5;8roR67j17AUE4+=l9IPYk%r!B#v)cVrz@3s6rY_FbX|Fub{KoN6Q>qx~>#*-o4 z@@G8Q+mrZUY%d8iRYbW=#T3)sM*T5iojnUUk(t{81vf>grol0^9M!w@r=|Bk9{w~7 zmTAX?LN0FOp2fX6Y`iq&T1$f98`KQTwR}6OWO3yy9$y>hHZ{i&ipaO6iwr)Cni^YT zw5TO+hZ9uqO$U=Sxcg{>%FDz^vcmP3BzpJj2W@ zzP$DDUfJ$xT0mx~@!DY->>Tn0iFGTI#M63=Z9PlnM#6|@#?{ifMW|!q>_oWX)L2;7{zR~vRIY0<^x$G7!v=x)rusoBR~=UA)4IlXQ<ui8iB+TP+L%BYM=g>?w&?|pK!_dnwP?m&7Wyvwaj?Z|6=Sd!zEbtXUu%LZIpIv3kS^4gZw^%Ejl5=}a zKX4Ur5{@FWHlkyUKGZV`|LSXdIc4AQI^ktvwO3-;=p|9^WBS#>g*&DYWq}iNX%k}r z-KuC&ciUk7d#UbgrSQ)-rfr;UAg1A}y$RADRG4Ag&;k*@Tgk_t`eNtUg=hv6L1T;b zzj(HlFV>C~03TPbvq_EO$30ObRHBanq@r#5mRGFI-KDGdubIf6ttv1{C>*aKxd}Od z4hR}$$xFzBJ;0V~|2@jXBG#LY&&>Xny^T!oGz@*Jg^<8vDTA42yKR>YlkNCYX*TpV z%7A*cX}SU*hqt`h3fal=@D1K>XD1E=j0c`W(OkR$`ZDy$7tV%_HjXx$wylFcU;N(9 z*S7_y=reeBK3Fk%(TRP5fo^yJ8kl0mKJZG=FWZThvOw_n1 zQQx$d<(&UX!1R@n84vd6Q0a*VjRn`$GNP!-4RzKel-=}=_s)WuQq?aT@~5j=Dl0?I zVLRpdPQyFRpu^@K6I$3tTw=GNA;rn8|B|c?QS{ulFUk%;t`-LY7 zPlaHavq08VLF2}J8~MHhHP+#FdO_vJS51++;$6x4MFofD<=7=kTsm%)szZl7+p1*e z!FEVe^G88(smiLI?oqMY4+<7&Njz;ev<(Y&aYF`~H==jSOI}x7IAY9NW_Sgn6WP9J z%Wu7BLIFN?GPGnL^b1hw#kbwZt5r5ft4?M){7#(8;7JZJN?IOsQn^otr)V#37>hY6 z+kMn;_1JOHq<>@?CV{6885UX6qBQ3zuOqg^Pb9o@56O$EYT$|@-VFPe>wQih#M6L% z&n(An6&Y#Gwu`B-yoShp3J`6!7lkg*8?+WcUm>?u*XITnS_sO<^)H;UibRTlbp(xn z+Ql0QOV-H>akHY@19D4N<8&t_{}f5o%Ree6s+-VXw&J;zwrp7`V>0ktfOxDL+zlr6 zmt5QZ>`_i+cU)n_C|wJF*@r>0D2-m94njr$B-@`{4Z7BOX?cU|SHpc*SzrT*2R;@I z3uXkx!J2HT$BNul_X3NSyEwmEzbEfFLn`lBPKtf`R+0R?Hpf;KN9_dT9EaNivtd(* zsG7zz3ysmyb?&-mMaoE)rJ?caT>N0`bNps`u$c>x6iAc4a6O|$JkepL9?=RgUXn#d z7wtJ$04Bzg?1h-B8K2=s9y6-fGy9saLkvUww;hLlRvsMDUnyb=yW4B(4-q(sf5t@y z_TE}5AiMF1_%PmIJipi}IN9xa;&Dgt5|9&;GrVMn*+Wp!SKWyQFCONaEdGFZzCf~; z--oUh0=Fn9@Iw5>^k1;kaSY=A5e(#LNj16h%%-s}efH0Z%@6BH*c5|_MP61G!tre` z2s+oGl*jPxUGhT9kq}bb|NHBVrl`tTNn07+NjGQ5W18tlQC@)fisW2;Z3}VibG$Uq zVdKnPE9hwweb}1m-fvNmukiW^sJq* z=hc6O<09{b(u~0BPFQW~R(yg6a^K-Pyr!>1{|$@2duLxrMcSBgBy)uN$Up+)&qI3= zN-ZK&QXsdzx*LfsEh-5%`AysygLw9#mrP96jjb*Z2fRsAZ1?@?ecHdqI0w0I5cvuK zhbcu`U;Ete+L>HJEKG3SaLF!t!1dX^@H+m%+VrHtr`p^2>Ed6`UW?cat$L-U`umt{nV@jQ zL~U>XrPtZ>pXaJM2m3bOkEO@7WsIchGTgcBrLR6oU(cRA4Z8A-4M2En;ffJ);9EqF z?oA!+GvR(g#SNZrsTSq6auv-_X-#dJJhfjpm~D(HpW50gIEQbG_JKjO7PmSSXwVK{ zp8~6S0^eBI2fcuJ7N;3ZC!N;-^|8bwLmoLIJ!;n^)Q#dr)^skskxff}Y#^BIqMT3- zw~wdCRs&6BzfL$yfA7E0J}n;o>ag6fUxNm+YxO@kB$=eZG90YZNOhnPw8jH?^msRn z!=^*LoV544C*~G}+OEJ{>91>?wEd5HPG87fq-1J-iWg%X|GyV+yC#QAG(snLHHJ&r z`5XBW#S-@~S=$D=wI3E4sc_A$O&1rcajQ9GKg&;8H_W>A;sU@nfr@87&Yh26aRJ8U zujt(v-__8zJIRXU72>RBRQ7%isWXz_yG%*RTOPUcdk_0i6q91T$GM(p_5skJJU~v1;I&x9o>!LqNAd%l6)#kP zLa+t70cu9nB+g6c7oK5?NN0i7QK@T>3PfPjEMBqvX^a{1^z^Nj`1v6?Iwa5`im-)7 ze%U~0C+GWnYk$v@RQX-^JM8X1!OgpOfyAK}A>M436c%H1v16C|Q=!;P2VV{&j_EZ- zO^6m1GW1-Bdnj>9ht;a`%OfVD;aM9a5^GYp?;r3V2`*MgahGQ-)$CTe(YxM2>-O;m z#2*i@r|vo$*1_wOC*^5fk9~^@n$gIJGPiGo@}oZjDAjV)lGIFI0z$;Muo0l$Rd@#b zll@>Sh^8Xw*|e{xZ_sHEiV|Iv7*d!GXV$_!U<2axzwNEQ%b4j$f=edc% zkaeeTBToM)^?hT< z6P+SPm?llWg8%rj33@=Bg5D&)a7iz(3lr|~AU&W>tv9ehQEFvAnm>K4yPt0s=aNat z7KCx(f$WG{Xf#Xw*9tktpZ)GZi_$s%wAPh}u^)aLCSGoz$UvwMl6q8Pa%zwx6AM6l z%7QFWrRE#Y#?%WV&Wrsz`=Aksy4koOHxaQ!|EH6Of8RN{02E3PaL{C~3pX=YSzEyC zC~$B4t!Z&V2s7Ej+2AHEH~L-j=agM3BHuNeybMCGSTCw2GaoAp3lEF%SrN(PYgSeP zN44+6;CLSls23Qtz8O~lnFifY?&jbMIaBv7deYoavsTPu!&#)0A)v{Tb?^_daPPtc zn^M||KHfld1u*Ji3O|YAWM!KJjLC)C`cDNSOzIk!j74ni%#ie_Z#%7BUYElih6sy1 zD}wDYeF=i(nF>&&`)Qu;kzSx;g%3z_pV z0MZAAYh9L9!xY36agzRR{TteqPir>_P>q&TD~iu3gGtXRB^e=FqB5I= znzjDyT&~vOT%0)G6eHXV4F_RNoKE&&Ptj*xLsw5?dhGcm$v;T`5ydOwx|&4z#L;sp z%&N=Z4Dsm@Jp8qHRE?*UiMFuu;Nplx;D9jVJ26Fs>-QeC_+R`8St#FfiM1wG3F#es z7xuXBjti(W<~VG5byzd7Yd5ZNF!^TtUGQ3d)d(1sfni>HpKOd|ubc0=1EcSQ{*SuQ z1V=^=r?70_3VLXk4f-pNq<8ti!Gd0nY054w(P6JGFK=Rgn(lOeD)xbwChZ;AJ6LM) z<^~A+q#uP?KfYHO1?o(61~r}*R93asXJ6A0CTZJ`L4@z7ik9SPo(l+e1Q_Ej8exOc zICZt!VAA;`;Yr=(!`E{vUGhmDtf4VmLL-d_nIu{_cPdZI(1RXgsV6aVZw$kmGC|vh z|Clc?@wC^YF71oq>)o$k;-shT0N$Xl&+t!p792YD|Bgs+{5SJ|^o|Iy3;A(*yFGQZ zpQ%g4ku|!YW}v@rkyo7{`V!QW@?8tJDn&0ysDa?*QkRe;Bo1p6iS?}{(s=@lO~Jg` zH8)m+q(XL1dp|IEzOH{X5MyK0N#PBh5XRG9qAp(q*`&L0Ik8>GrX`VFd2S7##9#X3 z51J{j4Dt!??;$f9JkuZ3ItgBygYMQp%tpLkauw|Vgx$lI=W>`w&gO{Yl!cyj^^vQC z5;jEmj=U=E6sY}^#Q2`7ZC^?kx3BACvmRf$+Zb^yJ84FstN!&O-IUDYP6T(_E2^~KAixNbMlbs6b((xvqHcOlSbAyreuj8iL(XdFH{1KK= z+JakE02v~{^U2dI?p0w6$rmQ#W)>d%?&f%DOlDGA#Ou8GF!!2XtnWrKMP4~mKbccm zs&`0TS_9l}!=oq-Oc`WQHgbQ7`lBzho0?(xUS6jpz^MjK#U)0;>qtAPG=6Gm80?wH za-)*Rv4c1eA|M>aWmP%8i0iI3kos~rD;8dPF!u;+wc$XSbmgr2L44j{r-NlQEtqbM zlUlIb0khM9XRiB{IFIG#Z;UERIxaK5BP1(4(z)4Et<<;~ zlcZ292Cp3J@q3T-W#wgm4>L_mgV+oAW@cx&q$CXD*n*6G{J8>MzK6d)RHP^X+k&GZ z-wh*;ufx}jM29fyD}6P1^8xNgU(3RPb>Yy}TFH<{sk5Dox^uyKJIaZl$vj}OBR=G7 z9*c=jQk`n&K!4a^=m+huwr47H)BBgA$3fZlY_B@}Gv8Di?yYz&&u9CU5{JMwj8Wn| zGcD=?l(Y39n2MLqNs;~qFZO#J!m0f$pgrt~GNT_Oq(mq0mWh9z$F|Ki-@(DV{1))}h78kPSxm;`))Z;Z7DS~^ zucRzzV~ydFNvtH1DQ$z5*F?DdE4;Zm3OaANFqOY4p^?_8?RQ0$e8Gc_y+0;wP}9j4 zPMxUqA4w&=$KS1cq-37*!Z2ax{ZOg$QM9Fq?L_^N13WRO0M?IqD44ynu?VS7=aEX} zRwo@t9YFKI_kutHYlv_e@RxJeuqK4|mmw#b_te~H$oygSX|CT>xEwaQ@B5qU6d7Yj z@u5XOnfOD9FW?LdkynN!cb|x$gb|)lGfGnn>YYg4wtVRt5d;1N&jZ7+$+V!fFBXYC z%Z}bSergtL$sxX1KaWBDZkKr&ww%KXr8dS7a$29yD#G846T5FI9k(RU(hnLv9AV}9 zXdrOpZKObx=}aAP2V($VAhCzY(x*R5*M?oRFFnnrwk*EgrT zj4o>ZOEaYpRuzS9U-{+S%U2eCKIip9Pbj?M{Z)UtX^+Xhd2^M&{|zj`;gvOTOzY)>sxtb|yr*e#Wc1B%Akf1G^QhUrd56A3u8_@nz>`JTLEF zT&=A?ToqV~6C%Qhn9W4}G+Ed(( zZWj$q*Z)Hc`5oR}whw#f+<;!fKC=F0F3)NqS|A-_228&~tv7K)^3^)PGfV6Hz$C$Z zb^rVePW!gj`t0&=kz^FmZQNbTJRvW$No-1&F#SVAw?ZHIJ)1d^JL*;K^w(D$p%AOP!?+rdd}v9Q=_k`s zF#q8x{L((C%@FScEO*h`0MwlaBhkL$|I^wWD_v;hc&1@$o+Dct<~j)NsJLNl<=qxN|}eu zTgwWR`dKeBS@4?ZrLIM#79HsVPd{FWM+@muO4QP9jyI%Hr`GHb>rNljjOZ#it+`B_ z2`0TNr*e$UCu^RZ;v>fBFpoJQ`LDz6x4L$817Fn!)=ql`hc`jURuZrDo>ODK0?6G{C>>+wPaOIRd zVT>JAVmdf0Bou|;&U|;)Ywv2<+NfS2oS>R-(3C{~s$=u7A(!YwNR>=hsN1~&k6WbB za@Z2yXVO6@wEecn_=3~%?j)_D<&TaLX;*u1DEe(*9k^P&HR+1}?b-@6qhGX+koNg>Uo`=o}D;;JLV>iT{-U5(C9;HSOIg@qFg zBc~V-93|u))|@K5$%~D3Ncb8g~o0zg3g?O-2&0XlhD-?ewuXyHG&IAN53? z8Qem*3yLLyeFYLbx6zk<@ao#Ja39niF@nm@(Mb8Cqd=JU)pPi=9+(AN2!w8;9M;PT zhu1#p-Y&&2-Hv`H1XZby9hj86bJs|*E`AOy8uoRgSiGuYP}}_XL+%CynS;5VR;5*} z>ND$gf_m=F6_~V?{vlj9Q8nL1^xc!ZkvP?XCBqw(eb7f-%%ZUkyI>9HWs(B{Jk_S4 z#+BHBPxBWA5{iGSRFkaj`5!>EL>m9 zjBl7B;xyQr+46sM9;|B5Rl~*3@eGf0&*&2?&z1jw3Onx5-M9(|<~_dY7vQ;BL(R98 zdIv0~V~DHWom60A^EnK;Mf?O-1@s*p+>@?yR%KZCo#VrLmS27PF~`QIiO|y7bVyRw z$Z7HXsOm?8LpY1S_X+H=mbJoW#I(P*2qSp7LH$__ z%8Fe8BIYO0s{{nBYP{l1twe4~NW_ko@Sl!K7ekmnCgoL3z!NXb#ggM%#|bq4;V)yq zH%KQ)cpl6YyW}l6K9qZAu^E$9*!I^2p9Ea6xo#s)K~u82?TPqa;w($}1){GNa_CfE zKpMrS0+0TJ>pYx3I|J2`g|t0i_BUDw_ugw&U2pFiqcSxMO@1w`ki$LWc}H!_m-%FA z_vh97`@!HzeBm2T%Q!&rO`SI%@<$W357(F{Z)ozpYJtdEpe7P6gz@ zcE9_x8ud@`+V`fFSfE6c+3kfrN;Q}~i>0`5N@a?fkaBwb^5zY~4r#jqjDFv!9_Z(w z(Rjmx{q#^7-#!Fg@10aoSpu8T4BO)}Gr__5BL>iipMN_71e50asahQ0qKBDoL)fZEM~y?w*n=B? zQr%;O%LcxnO1v_%;9fDs=j~34JKlqwROJMKcBFQS4kSrTkCwb+&InFF5I^B)Z4X+1 zR^Yc=T_D?ZuUHU>XjdU>%B z-if?tuKakL`bP~ihq4?|ZttiM*w#X7RA%;E9MIHVG)gkL73X-8Fi%5Z2C!Dnm^yHz zaL50J`zyj!;!B&m@_l_gXuF>oEa5~7lwjv-5&kZ^eE4@atq%BdN)W0X^pH?-rnAt# z&e%V8qp(~4VJBm{QAn-4#`4*eUiF=?N>-0fCR4n^)Xv4|U?j!|k{2_p^Js;+%&mB! zH+~ws!D(;3c7}RM9sJ6ZOIqqR8R68>=xu#~!u)-2rp`;c8xqkT1wXTi2DEaa5uIDS z=S6wH8=|Ct>DLVSk7-HQd_)ud_?Nv^zToxYtW^sR`I^@yL5dE4L2_9gZro3r0#_tZ*ViDJ8rK3(sydt zNAyC}{ zh^zx!mn*IdG+orL3$r?oLxFj-@w*8jckOpdS8d}AljB=&+&o-8mmbbtb3=>!`c7PqoJ1@D@P#}=Hb4gSmq?sJ^!}xt*GFIS_7-?TH~yaAyG<^>Wu&Kh zkrVTf+g-}_G{M+Nott=d%}4v4FW9 zyp}Mj&WMUFEP23S!Kklt$x8n}AqW;TDxd#1>?|$FQ1eI4v$dMn$K08p|NWdDnSro0 z{^&Mq;HsO1?$*c5`#N8BXGux^f_}z9DGl=}TZ>!WNBn+IaqbfI=tsIjYSdw6CH2~^qog!`8!uY`77V<($Pb}L0Xc7Ksbu8fl% zI58jGpnlk*mC5Vk>-ir^f;4i^^7dwoigHQ|ozwDis}WGxQUuYlA{0Kepv!OPQR7`*FH|*|Lvad4UP2_0)sMkPX7oF zZF>l&#CuSw#PYo;s8d$-6z>U}Hv99cCh30QbS-g$Mjbb(asKRQGL%&#)wX1?v@~ln zzzB5CJNHcCQ*ia%I*e9_j;EKX5I!%aKKrvgg1>2-PXnyKt1Fo{)IgsM`Oh_Na}0I zx7k}9?lZd_`-?J1t>Y)8_P+&`m6sfO+63^gXVP8DDf~x5B$q^|-h)dLAFk4h4RwT> zIdX3<#!+uV{exa${c?hyqm|=7xA4`^O0al+GeM5J+X<)(0Aut2NM7wh%dnsO#H$b6 zvRUW?%q`ATN4K!TrH0?G&R`Dj>n6XP<^sokwpc^!xoaa_7^|X=+?h?aVawF}h_K(E zG+nZN-^^=OLkHWA!AKhw(h@Oxo7F>)uLHc+`x9)qp#kaUAi`Coza!N&<&^i z0|aasMm%zml5JG z-qa=dQ#)GAgA9WWN) zXF8@jsCUB?HqK8^W@mLtC9p==<%-kM_{I6I*Z5u3RXWT{w`@Upf$`44Xt%p8!2z5YBL_u{wjAa%f-m z)s)eNB^A;(KCN_3dwW6yT|?y)w5`3LUW1Z|WFLh^nnI+JaB*vSoEe-==FM4v6&F!k$1E%_NdE5N^aB|~0@Zh3rPfz#&14@!0vnYNaT+TAx*vX zM!JvDuiw1Sq&}LS^7R&!~mYBE{~;I2VG^$Frt!R|0x7Dd@Tux4~^nr#72XAhg#Q#LFKD+vr)I4I0suUlhCgoFmiWF0#8- zXk^%$fm`(|VSB4$d=FZSwbN3RE|gX%49~V$vrn_x>6;Z>gUm?__zyqUz4~3sNXz|- zeOD_BJx%;t-02cLw&OIJ?q+PPFyfW;Cr$Tu%%x}gd&HXr8mbO2nKiwOy?@~>5BH-P zPWq~ZNA5h9k-T14Q9pKqUB#h^Sxg&9bu^;)j@!J4iezN^xn1p;<3Vg4E?+@@rn2Ou+Po7P4{OceEo%Bjkr&;U@{E>-(eGr zAGa%tOmz5|;#{tQJ$Q)yvc&?B&T3OFR##Vl(e>2*s1E-h$zko@x^*Er&-PWe`{M;C zga)z?&e-j9RH?|V97i9{nYqf=Vmc&Y(#dLjJ_2iKFeBs69~~QI2sDvMSDFFnGI&J+ zrlzX!KVvKAQBbV;!g41hP%5D>pz{FWr<7nF>zyiraobdyk`&%)W{IRJNP5iM=rOi- zQcgdK@}y(%6KxN)C~5D3p>B@KtetyU`$$^ z2D`nH|Bj)LEzq!np{u@J#kqQ+*i})u?>`cjN-Fl4N0%e_Fv)#hzxcaJU|7@f_iZ=% zH(fR5kV2u|8!PReoL6-ZwtQU^)BpK^BR&!?%B}91DkYA|s2ox+Q?0c8u~ZGuRnd>h zsFHo&7^{(@=kfve9JYw44@Z%sJua#+?IC!ovL|)n1u=4;tCuifHvdk1rceRO*i>Qn=updn}SS z9>x-4V}IP*`|jKfz@IeR-6Efu==4OkS$;B}+dMhpE3-l|X9B}z-S$Q0qjX@QzuYs1 z=XG(|{*Pppl&bdiCXs>_=de_FrNF!Y5?E@n*TAoDYwDzS?fNz5wWD=GixiGsOL*-m znoVfpj1(z+6uZmCc4IU-lmf_?&JBILG6Niy&JD6h`KZcMCl4dWpa?CK}l&*xP~ebX*ss zNlzo&_?-brUbL^ri1om)ej>#~oWmTg8#?X1 z@HAT|ayHb4U>q{dxFa9Z#eW@7NNcg$fHD(D;M8(X8wcS{Gv~1^Gdo8{Ob+Qv!p83WvZT4S3<4dl-r82E3ZiRZ3e_2KG>^N7eCrij&@%6X9k;r6i2g9fPyn> z!4Z{L+ZFkIl}IrB|sXTOOMFS(@Sp7bgGp+SYshP4|p6n{AQrzMZlx2t50PV8-Z=DyFS>w%5B zxBdO@6y#TK1Vijt?PY_Nr4H)V!gex0$t1b_F*$l%I`tg@BK+%D%lTr~0?iofkiXt3 zRj+^wNh~F|tm)o=RF)r@-hD^2j4T#{;~LFMlcP-kCFj7#*sp;w2wf&!;G~qq**f@s z&>O21_1fNRC=C5|wj~B%=bqvkoyVT_-rKNHZab{)6?#^ZT}^$s4`~I|v0XY|;ogm0 zt!99k>;2QnPJQCEgQiT6wa4MPW8@mIA|#@{{&>3Q9$#*Dl+M%ig^}x|i6QUo{-}8e z<9sS()jR4wEaHopn86fqKKX`pCT+5VRp)L_5pfC0zLFoTk}(gg`nz5gzZ27LkRK>$ zk39Yh60sZmUGBX5JxaI9R-h?4kRI5|akqOk@@(t(Zm_F24JdpsrmJaX zhq?cgbUQijoKAtW#mmIJP1aB~!g&Bt3z=g;u4X zr3OTPF;A%%pAd6RA z_^F1!h7a=;N+Vs6XZN}(E#7FW73v38pTwMetxWhNdXu?hS-#? zfUwAo;o#THzuJi-5h~Pd0vU+2UfBL#+F0QG(b8Ja5qO#<|0>S2{Rjx4&KO|CiJZ$F zY<^rc#frXdZ>4nGh^bBxQ8gu+zyx322GP_WSN-ZCe6C}PZW0EN|fCHNn{DCiJ9eK7I`X9+dA6%b; zeU>ka+`FxtL$5mVd>b~>J_`T-@@RV8-%q8vNj1{4FSRSkjO;kRD<^Rc%ZuyHkGl4G z7l;Dl6{D7x4^3LUcbMti$tqDMRVI-ZnQapRrEKJXMQ*fygoL;eCH&%tK1nTql+KG$(KceEAUI)PZ6N1eHdPO`3WBJxofy*o&eO$JnrB&w zLT|gDp1nA}f_a!ye#}f+Jp_Ebw~>BT=(Zfphkd8APs;uk_gRUgzpG|l)&T4Uk-QU= z)_bXN1M7#mXE<}-$&5HGem`%VgTp#}2CDj1gQwmHfgGYZTVn5OmEU3UTJymOxQ`_? z`^8LNjH8TVi?{iG*oS0CJEVQ2fZ-P8Jp&+$(;8n7Y4$K4K_+h!J%&nk=o9^ zUKe#29ix6LJtN)3xT?ZbS$XTm+doGW^m5N~XccMfZ4f^dQmi%Y)$mL1yQD?;;f8T8 z{y%+2X*w6~^Iw2B$s)JgvEFFdsFYo#+s^M)3Ec!Ky8Oy}-oiu*9`+vKDzxM$8%J7f zdrX`iCrkQ<(zu{v``MVynf14B|L*aOe^KvM_ZXZ*GLrF5Ccz zSV|GngDigGB{8>QoQy2Cd#*`pEGXMV?FYH|wVk?*OKm$=jos5-q`z#h0s{jE8?KYo zj{=LiJiXz*ENWiO&qZ$)A~Tiy>YE`+!``uFtd*Ps-K3(WfFJGZ15>%1hJ42C$B{w$ z=shAs+vlHh69q=N_TBy*if+S>A$d1+91hs*A}-;c*Fv$%f&T)=P=2Vme;qoty?eNc&f$u6 zFXQs0<>V3(T8knhi+9E=_6S^57_n$)mIopy_>t zo-b8Mue=fa1*hyN!NH7O-eiCHrrylVEb#JVL#HX^CFs^-IT&98yQpvHav^Ef8rEimtf5$^n- z<%~x;3b3N8*a}x`HF{;mAC15$V53GCO{yrWHCdE~BHeSB)UfZAYga$1XX()`&KZS< z!rSmAdKBI-4DC zIH&dn>-0evY&tJE=n3TtPq6kw>XuBtqzQ5j0wa&^Z(#^K;@jz=o~kz@DsBF5QG8EV z+jJKQDjyAhbQ*tf4Y4tOW`T=4%Ede0GSaMn$#yhI#zR`0O|2ky6_udkxl(?^!Del1 zoun_AU*y_ge*0)KJ2XmR0Q3ut)^-!_UQxjM;Z*Q6vq3tASa)2Xsd!lHx7n&Z4O?BG zGOTs}grwu;jZ>>qprT((qA^?SNP~0W`RNILH(#pIFOHj!HMSo|eUe7G5XpHqgPA#; z+MfG!GHvLch)*B>zOB2o^K=s_&e#LUc!i?@BO=@YJLZQ`?Y_K*B)?mTbX00n?%|Vs z^mX&7GWj!T_>`8UblWT;yKr0ZPio>mwRluAiR(|R_|p*>u!`&yC33jP=zM9D!h2#; zQLG)pYs;D{GGPNJ>kZj!;c(tX_y0(qDH+xQZEp$Ti0>YlTMTFOzW38WOo%6TR_`_h zd)3J8Ku2<1CBaU&)-LaDuxvRl5%YUsfGeNG#q{-?S0?DNuO##mg>51kbI;`gr9d9M zQ{IBCGd>n3%$Oe6s_@zN6?%#y(j7C%>ediIt=DW8e-Sua1M8Nl@BTp~^H1v6*Mb|) z`hGuWjYypsQoQ{_?6w+FKLr#79N`zgq=!a zw0V#VlGMPj6WUuuH*#?r*v)>wY_^t3F*o}Yo{+tDc=Zrb$q{GUH}Yq{pLxXmPtHz| zw4VE|pSw)E=>t=701arFNVf;3@{L3t2N`bKtZAvLz!jLoLTByQr!NaARk!#*4-y=2 zg<;bI*OxW>P5W}zrL#9R8#DgInb7r3h?3a4#SSb#-HiWub{tbl9FtMbZ~qE=XyPKe ze;s)DxK{r44%h9YQd}q7-KdwVeg1o^Emt=#`|%H5F3hm6Fu5H>K}>ruyA&|2cYd*V z@weJq%rI2r_{g{cn5(#;G7wlE$-`x~u=T1GcH@0$LsLgE#2dqo(-NdL{g z_W3u7<;njN!=>dKeQcj%2J!BT#S!X_N9RT^#EMt#VPX!?z{Zy^x?aL-x zvWn8~t1HMwQGvEBIoWhG5MmpNa0T}nPtXRD3=gKJJYm8zfxcc<&_*?Bk@Q-T+ z^>1YmnrV;n@cJHH&v5Pci0k45b;cf)VX|LpTriM-h312C%^DoD3iE@MiRJp+%|Ez; zR9oFT-8LYXZ2Hta?8<+Ss>9|2F_u2qlU9|bweo*D*X`P1w*+v!P&d_r4+oaHuzPbj z^@CAOnCd&m{P#jqP4H&TEg!g5cPeo_aS3}(P+6_+jkhc0i5LFh&hS=(jLbtkMrx-d zt?rxtp36NP1%j_;4&D_k$`0H%&}CVR>`t+p%~$%Dm9OJuQ5_{|EZ)6E`Wi$<6FSJL zD;MU+H-y9}snrt4xvYPaq8_?yrbF~MC!h<&m=lJH6*FXc(J;)bDt6#|8{E&z&b&`0DA+C|lCuE+6<#WjU z=M9;?)@d^Op%XjxwBTpW3GG0Wbd@bO(Lc)D=|1&ah93a=?WyIAZeR%iFH3F%C$JqW zlGEtEqOWdj+J^jA&a3KBO1~{b2xd0DdnDw+=5N#8;y#3_QKp`FVZt*v3HcTena#oK zh`2M%<}1!pEeBSqi}KB0pPdDt=`T2jg_5|<*}i74y~3W6f66alPb?NmZ3??Va(w6F zy~Gwd*;*Nm9S^SE55CNjcmYMut2BvcclYA7BtQ|OX%69w{^rCt;owz0!el}s=bfFiyA5^0T!RbNkCYQ{%TY$w^tDpXC!4tNi2G#TORTzrzzBF)$A%TBpH^#Y@`)9=HZ^$eTl zq8a+yMXA%L)h?XqQPT{uRaKpm6~@f;7Iezdq5nu{r&i&fuC86?L+;hTcFyEuo%`S!oDsvB)%nN z@vF89{}Tl+Wf9U~N+7}PMm!q1&nCo}ot~6?pmEfA*Uv;Vu(_uLEP3D|>P5DfnAjPS0%<98;SkGUM*N6*> zgKFsVU2B!cO3L9Y!=%Vbsi%k;3?`S+{yJO5%0xGZuiUafN(=WI8?tW6uG1+K*q=?G zzkKalf({C(BilhMWH|5z&#Zq2ZY{blxSMHY3OastV}tviRI&%kn{bw`LNTo-K-W##piLlM52;_+oCW#*|7fLt(k`j2ER&!HQqwj^fFI(B2B z2>kv_0-WmGJlt{Fwd)PXy}E`tg-V+ES^5znhD^V*dGO-Y%2eV5Lf%ugAe3mw1zMEw zZ!Qi>#1^CAj&AV5WYh{ty=Lgv9j^P}bvnj_?D6VZWAhGp9Rb1x<(bDV|6E1DTkIoiW}(>gk`VQ%Tga$hV;h+;A2^Lz`CwJez1pl5 z+?S2OY3?_DSz1(Hi{MOTE23QcdO+;er0x&4zUM272iHb?#SLtdA#wEMI^p>)f%ek& zHI`@NMF@`VbVUj*Cu!FacLNCE9)M6Z-Vu1@&92T-1qex8`=KGc)KHL!9yIA=hY!~P zf^$F-_g2MM=a%U}__6(~Y+&`FXG;7V!mnbCr*P!JM>%FIl2K#P7zEy{mJD@||M}wju%SgGA8Eif>i;3^E#sPe4Zw71}=W+awZo1`3^WTM41txwhWsfV+Itfcrfn~XBJN>aFTV(AdRrZu^3JP8=dP3VP-CwK@ zrx}m{94L~;waAhv4u_2@78mEGz%EPHWCGz6#$&h3SR}Kxy4w+-4_UTl z>n`zT$kJSYlcY`%V6%!1P1}Uy2(8&@SLlaVI{uyN-9V!hguFyY>*<#Sg)g8Ii!m6i zT|hZ*#4oPaOQs&1dMW83FHulFwOXOLR+sYu#}%cdb~^My{jj=d$u$N`Yz!vqfVPh3A(Y)s*n~dQ{}!VC?-$g6 zga0={hVp#Uusd~!z#0++wSiMthpiYNPthLRc^^L#^LEyj-Eem!bXnfMV4lLkaW&pJL>-A#38N#1x9@U+w+j}p8 z>k_DZpB51kq#iI)up0a+3&K0>>Sj4?xKJx~>hQs&z9Udgj!xR3^xtTsNTU+hlI{{$ zTq*6&ViL%$N~2mty)aXL=244qz_R$i`Rm&J`+o9|{j}F860`qC{Oz6SsN{X+tug8g z7-hz$k{H!t7vvXw7*`+XC2LickkU_D{7~@mwVl)2PWIsznwy~#gl@)Rt=~4Wzbqn` z$hK*~)%VI>T6a8exY9r1)ZI)~>C>r^b+A?5-jD8Dg>INdfZq^nY9#3rkXWjX2d)Aa z?(Ij_*S|s8E!io3rYK!At%|hR-wP3$A8k@XI8!*5wq;vzm5&8I-^uh|o)dvCtl)w9!P1%4CSwe9Yw&_=pKz z^g)$6Q5^+t9GL!I&ML<)_b);6jN^|tkk^o>xJm1UrXpg~0{hlk@GtXM7Q{YsT>SSf-w$3p*K^rc_u^3vMf44& z^IH)2`EU>if*bgA+K61ye&WnfFZU(I({AcoOR!4K8A&x`>U_iN2eU75w~*37Gvo*K zcqDg_#9D_4M;i7k@eaUgcRDM1|1e092>jQ!eMTTa{|V>8$kpSFCD_&sRSr1^V*+f5 zMP&bBrx88#)3afTLC-V{FrE{kc2IAyy~%mu8QQIMT&Bp~Z#nPY#WID+`C{*xp}as9 z+_Gdxit~;}265->q<*zskyT}&;}46;1M4-G6N{*;=1;y$o{BQxg_#Z#M=BtkP5MEi z1leZg>FUMOh{gH%?8~FyDKR1YLO;AO?X3#OJ_QeOwe7pr6<-odWE=c3#gJcr$qmMt9|h{=ZjZ5X&6DY59A(fxXkUE<4?7 zq0}lBloK=(FGqxIk1Xv*&GXO<0+;@0j&*xI;38FF^z7Lyi!+j%AW1*W6g4%SX6C>6 zCG?Y388lFGx(>=IhW{~6<09OHPfv`+572Uh1+t0x{$t#RqbQnBah7*pGT3WM*T*=q+zWGEtNwh z=Bd{aX7n7CCuVY_9W06^X%W{FD#LE;tIoGc@oSo2Q^3^buFG^x_Gfj<6%36Rl5<4x{{s~pduR(|~T24i9g)7eF_j3#1Fmx`;@Co_ja?!RY(StnvGQj9>=)ZlkDU08k5O5U25qVsacxYW z%8lt6kT-)PZEUu-u;=;1IjU_}KP}lb`fnbw%`H zKw3jeJuKuUg|a&4$Tm~G>v4qdfQLie6-^hDwk&~TA_09dUx!g$D6HspMH2oQ^7+ao zUq+XGHC4SONOA$R{hfM?;sm8MFQKBx@xoOT7agCt{c^Fg3)YTby8NCUylcDF{A$NE zneKa|0!oFpoIJ*H$&bF}hUNb9MPp<;lqt z9k&j@ueg>`yK21O^EJmC>n0Y{R)?eXg4*}z!iqY~40)Kq&tPrp=w0cJuvwQN32y3x z&FT4YFk4VYdy`n5huxgc)XF{cEsy=c1$Z+i7A1^wRWv00qS-VJVaIA4QnX%t%+Jg( z{I|n(Hd+^nrN=Cma-F(!xiArP>v3wK&}M0RJy=#9W3$As^Sa#J(+om>M`@FGW)+%iYhdl>vJ_-<`MBF9vqCOY4Vj%@UI+G8vs*Vu(AWqy(BEN!A?w zsG+_p=?T_t=3Bq`!+><#kB zKnA0=Fk2d_d;RA+wJZVb*h4mWR-v<>Z>(7aps4cMrc`d^I1)0(fXpFONliH?Rmn@i zE0Kfu0cG2!o=YY~nV!zfF29YMX(hi!lTj33c1Q82dZw5zqHQ{8Bl*_65@d?t6;!)+ z`k8C{6FqS)+mEAmj&ZQA8MZH@Cs`)tA%J-6j~0v~vzE{hNMc@;jmGYZyH~i6a5&^v z2lpEp!~hB<5?TF(U*eXmxX1BPo4b%F7x(j5HAZ_aiZ%g*Cwjk1OlpiC|Js@6>weQS zn+i( zssoY}y{!CRBDbfilGB#9otBcehJXw^u;38#@&Ms6NhDmqC}mz3+?TJ~yZ@r;El{*0 zfPju8L31=HRJd<(ChK&+X=i!mquiAD8`Iwjh_W#pAik&C<2nbjz>5*GIkZe}R^tVS;@uX!ou$ZFAm(3Ta_ML^1HF@5hc| z401~>op$^Rzz-QAxP_`hpI`zi{KU7v5UyVJlc~c*&CD~u>!1T7c@vZ-ag`#T9~8LQ zH;|YV{m}l-HAC@_aWT^DuS_PkU|SCCj@K!&dB;32mU@(>frQw!gJ4(@H(@mHgX+PE0UXO)z5pk2@3j>L(6kJhI zlQ5&#gKQQ*%xM>(MVCL^yh&sf<=LB&sn{&2i?}?kk95x`+pEACb$^+2GE@xH(Pu(1 zBytx0ymNZCOb`hN@w+gzhjf|8jNa(gjY`A^Iuw%fhNXx6*pABI1t_d&DZ+lw6Yo=8!WW|wFh>==MLq2GwP!j3^rlqi^&p*p zXz6{BwPn+1R#UGtVTpoJFhM1**h7zpE3lep9%j$9cLdS8MsA zd^AZSwID45qxk-_Q@Z`bXMTyj0C@ceBtml`g`va2Ah&Y7`~C;>mgj6Q>wERG`1wL6 z)}d`65JDK>>jNmNBQ2=&1?41or&}{)Wb6&Ef!iu`BMjc7K@b6}WN7_9~YH?qwhjm|*@v3Jw z!pL?i{ObQ!0U`lm}jTC_+RACYu0xE<#VT9k*|Xf7JwdUcU+_wdZJSG-M+C!Zl&^Lsy`m z_PMeiou2`Z`0IGIZtxkJoO^jnexyNVp%K#7Br%5VyJKr7U&KxQdN7GffS+lR0L#c&d+h>A%QDT%4whu!wAMc=W8i`obO-cK0+nhG`w(LG*|0IZ&Vm`!Sji2n+`mU``M4U2A| z&yE_b2dP?_E_}j>nj_9spu3hTw`Cv2GRA|SyBz;<={IadLBKi@FfxI}XR7*^{%ZlO z1!*{4)GY3U6)aca)SqVY z9xHQb9>yJ`V^LMe@ce&hG4;_ZoJY}dwr1_4PfV3gXCxSDbPHs=7mjQ~xji*Nvk(C$ zoF=bP>m|#vU)_@A6QzTp13LfP;r|Dh`2YS6=?p9ndp#V*Nf930%orQ4O0odB?MRQ~ zDq_Y~FA3Ly=dB{GzFo{fapEuB*W4d~dodp?m=i~gYNvY)E?lTg$^~u-Xj6{Pcs zzZ?Pcj#ZE>)(!5QcUa)hSWC3+uQ08x-ez(YT zJd3)sl1Y0%*wniO0ZwdY2oR{%@lDA~VDWj<=STDAQku9fKrYzo^M3gKOc-c+;P+xa zwLUoaN%4EQJ`e}&#(u>T(u z0cb6^ryP^29iv*okfG;e0uL)@JSKkhzm#+YL({6S0KWq#Kx6&^T+||pg9MF9ihvMz zXqj8w@PX{saQAQFGcI*oo~5_+V*g`$P#(Ph^kylSdcN~xcJ7p6d^+C zCcxe>ZX|UwPNht#zuaD}vZ{Um;H`{3Zy7G`4IrR7{KvcnY#h6>yEHSZ^@hZCl133S zvp>JUT~pcTnRiOBbX$aQwT#C5&A|}sb#%)B|FjKb?!%m;X0%i~ihaPvKg`$jdAvXd zLYq~CKrNt-3ZsGNQ=+obY5?dfOn!kr!GiktHLvS6=kXP4iOhTAj?7(SgMG-;JEC3a~wgylsHX!GNK-;R&&lr7*pb!s0G zX}0V<&Y9yQQo3_1@6V#ThhVT-3qLqlJ&Nb<3~f#BZO6ISVb_@GP|8^{E5?OS@1M8+AaS>#)JA*`2MReGZGRenFN<|m!IV*Yz0YnW_^`@jruC#sTMQt(e8 zJ#I0H>E9*0e~x11U6Dc`&l6PNxAbcK;YU9F34YA1@PuO^7vh4OtoUOq8@>Z%3YOUmJSMKoX-JP%l+lb%n`PSw}yYw4>OA#95DU&V>SIG8B-n1M1^!aWo*Oym% z4^?TY(MqwGbq%YoRTjUP{`!VXc>SihIQB;;ubRq*QIRgv-L8L0+}FA%{rFMNACYL_ z!P2w16}J%BVdL44^yqg*tl( z*Sj#c*7TaDiM=O_wM9ktt1kmhW4o0-t98|NAH@Fi9lQBVYB0hoI_{=$$t7q`;K zC;eoBlv%zcDfuo*t4Yx_`@8Gr1H}E#alFKr_G$^y(VW5USp#Y6)ZeN?N%8L@&%ZFc z#=DldJ+to~@()9`+GdqjFV6I4DVrxL!hJlq*;@l1e)PLGyVn3Rcg!Uy$Dk#02c0QC zBrcnA>jyPcx=%Ln-eln(&{UFkWk#b4@x8Cxz@y0T6{YiUosJ*MmGiW##eZ(`Rpm!_a$Y zl6JlC&^DKnCdH-UrzvYxeOk93)xL9}Ian_fOa>MDo@sg?eAX{Z{+Mwh>R$l=;ah zPl|^uB>yhKZGVP)51+gK@8s9JhNw%I2s4G4jSd_a#3kDN)-403;Lf(~d18WbrSlGG zyve>iFi@MH;X}dClXsPmo+Bq(3d3$Y7PP{!n%h83Df>R@&TR@xAU^ZGpa98X{{Hs6 z-+huY7ejtN^4N6%ubGTh&gjF9v%D4jucm|s^L`lWQst89Xkyk~FkU%+z;ZpoldGM6|LHtz#^`XZQ%n6nSdX>GYM0E%kvDf#$) zKz0UqIJ;kfwjf(%T33|sgF{Ck3psc-qE)pRsFJIt&#=`>CpG*`i}o{>g4cyQ%Aczz zR~skDMfBVzIf~%oZWKcrIbdrKzCvuLaRr9{ss#I8H#mC8*T4K9lgDslEaRd}jo!co zk;!aNb*r%nzp4$aYj#Cl+Do$zjjtgRS=6ftM-ofN?zZLe4@vSsa*%IJ#3N{aNCSV%SWuK&;}{KzMUj%D_rQwp z%0E{cu~4pKII&8lr7hLt4_Wh^G)(h5}j&OmrF) zI7{&rOR1EA(-2pRqok^#wXiG~y;IhrhgH9(hCe!O20uCawQBw@9Ob5YB#+j72{;gT z<0T}AcYrW<+`AF?I`N{K?2WNf>DWuTvc7qq-+t;(HyzTmn;;Ymay;=mDI+pRL#_Gp zyS<*1pf*)~`1bglx>K~3d?pp%FCA7sDO|u}S0;a1yQ(b>-)b&+tF|)}cyg{*Tm4vYtwVrHI zPJA45pihft7VKH7GD^Hx))>_uq;^`C6F^^?8 zpuF1lJzjd02K1i3*L0L>7%50Utyn4*0Je`%b&3^)Xvoj>ATAX~_o)OaIJoc|8(LT3 z9HTf8q}%cC&6<6aCxYZadYPUwX}(Pmf3}G@w;O?QDCm@`7O)okW;CFsh;3CeWXB$k z+9cXzOlYq0H4a4bOCl$tr@LSdTrjpW*&f>(dN(xctzr~SQrGFY;zj}UL~#CSNy~<4 z{8RA;G3$eVLsJIt&*~}A2Pa6vqq)x8@fV)n0oopd7~>$~Lp%5sW+?&F;sKB1BIrNb z>A`Qqw&!1*nNvGYFdDxwHPE{~>ZE>xG)`0SLK^GJ+wbLrEq&D%WNCaw_elfoW@-x) z?dZrr6#F6MVuO#{9+3QbBh|H+Cy#h@Lp)N_h5f=(Eqq!KFa(h}2M7u{W}GvKWtu{@ z818NVIos{w8~P>xd5Qu1E4?R1iOgMpt$pNYe5eMkkFBnZN$*I9CU4JGjUK=!*T_@A zRgp`S618C131_>rs2qL5{@UJ9>|!sRZ~X#&3(DTVEfy_oLR;2J>5cb2xfngKv2|`o ze#v*XN$47_5*s&J=eug{{JCW`xj5<4U17!HCR@SRWervZE3Vssp75;Z2!omS3>qnM zdQhRk0iKuU5U^xp&j;`VUfvJ4=S2uUx{-wHvd)cwFQFdAZsh64=$APSF|tqQUUjc> z%$z^8pO{$v3>mv#>7iMi2=@r+6B>H6X&dk?b4OzNI)?3!`8 z0f|0yGUw_OuZ|myKOwXlC5hF42CBBhu+Mml+E>>j$DF8i>*m(cq) zo~GstEL(kg4npw9OQ2>pgUIifbZ*o4tm%mON=>H5+Qn|wV;A!2E>2B?WTMAh%d19h z-@5&Z#*~B06IIdl&qQ+LcgmMrBM8gIxc30W-1`z!yd!z3_=Ei=KS`oGPVBR|$9@RO z@0SVM$zMLvl__EQ%ueSw@jj#`rIo>ILkjEwtC2vFfLGxCBg(u1akI{>P)G^m0Jy~a z_O|a$4ppI*eR+DPn~E;?JWE(jv$4I}W3e(x(6U+OgD!kdN!=H*}^i!TeYOm3va_9U!OJ=#ipGhUsJ8CRn6#{_Grhs zop(f?UsuYy)W9P7Rm=xgK!NGHK2F_9${aw=y4#iQ=?&{NIaEs=4Bv6eN9D=6eW&%T z6<({pr0jl2UQRT)aHVF1ug93R(cl$M2&wcB$J`{|N8)n){l%g>aY@%X^4zIR1>;O%vOrl)ve0RG!cxfPVIzKV%RjbRaQgMyb5nyLh zgf5I7Y9<0&8lIU2HbfxhjtHex-tDqo=SN7kR4h1(w z&5UlE+lsPG$~?+04%$C#F*5FbUK6VP9@&badTSwzc<>1*Hn;%z-Lh|e|< zwl2KzxI6)SI7xL{=xk5oKsZvK6$I5c?>Cf)HCfJ8;xSx87$9iZb}^*w+F}vlkk06yC1-rnI@(wqgSv9y{X#0G*K#i2wPZE}dkC zjLM0=~GQZ$+?TR4nMeN5pbwp~vb8VW1;{-<1Ifa5UH1wZFCyB`V!)LjMM zHy7`wBiA?>;PjJbj*MBUC6ZKZfLHOn}aT74iQuJ$19T_&0ql)&2~T zZDE9}OGj2*R|!-FBS=~9$bfRpIx{`N`bsZIW<+2&Xfgb zdq$rTp29u#-1(=o-5z>|Sni@54s(0kafiFFcWClh&x$7q>F8akVtMBq3-(k1t*}FW zeDz=OICtCK?LPx0)|2%}i|}l$k7q?O(L*(;vlXU9pnnUW^uD)>;{#Io*hR?$q$e}j zlmXK-C;u_!81^AS9q7)ef(>MS3#0{Ic-(1WDA~5D;AuYi?!4BelUUksy54Mfd$t_* zQ=eBc{?29X*$f`Jfzn%;X&gnCrH#(JfNp_D!z$4L2pPNS>;Buc;0eVx>~5crVw>&@ z9(uOn+?t7xn6BWC;0vvP+&K^~?;YpHy39TM;M97fNg?6q#+_@HR~6_&0DNm<*Q&W) zyHF^-$x&Lm&Nw0?Hfb@K&6NL_Z3FV((Ep{u`GoTlP4%M6AYjQM)e(nA|1s^Z)E69n z<60W`XG2H|C==a7}BSid_}eY(fV z!4$&v#;JyZ$5zD%Y9_|4rZO--o3If;b(Gz)G`|RKGxC06GpDY`^{GI&q26Wf5Cdfy zJ3+dp#US?_p?jJ;m(sNbWH0}Iz`^DL(w<3eJwecI{XPL`I0X0{5~#y z_^cKt4uI5hroH+Gn&Iq0vG^g(cOo7K_xBa~v9edCn#BnJM)O$N|5+WCyyL<}|1Pmh zNQyp*YTtc74T;9NI)wba^;5sDPc9ib;wC~s+!DLm4n04SyeOFHjQ@d+MXdn_-2Z{&c4%{?s3*sf;DZ00aei6=pPs2OE zoEg8n<%{mGT?~wh1C-~LCEIz8D84Z9g)n$)1*+K);p2-!u?q@Fh*y_K>qeYIrDY+# zDGdKm2J6|SBI5=i;w-93xG~OxWQ8lXGvGv@;@HBTn*}+$!QY z6^G7<*2eAZp%kU3TAlFg*5RK}=a5mDa8#q=J|IRotMD2Kf!l3AZLC%M+YvQ2QeuFR zhYetS$z7iBV(+jHj;vJ2?g+yrRhxNF_Y|CoKN(~>z%3*(Q*z0_|7Yde1aURjebvmq zQj6VNvU>WaFMq@F74`!;AW`~0I%Cy}itS;vIWkAJ*1_K+xoKwfObjr!@cc`CpiDE= z|B7MZePc^M`XGqu+Ev6j@x$Eq#K<$kt}k zaCL6oq4rvZZd)p|hi|ON!`#69F!dy1wLKWQe{69W=b1EB(4OHNmLdc%h_uXjlT80E z_!s;(Tq3M!gKK(*yi63_YFs?_T#nyhTyK11oWH)wD1F#@+C~aiE5dLEDS1TZuB_tj zlOnDBzhyOfMa*l?E1b0*? z{=^-tb5Z1y+NoJDP%@0^X0K<_NjRRopi6Wn^^?L^y4ElFQ82a4imOb4=lDk`&Y>X|IifsAv!oYFXcbSsR!~U(ZHty<%-&w*nu0C?f#j-g zJo3EsJ^~~kahVE2{*hp#bW^n`7M(h4Z5aNkC!2+@CPMThHf|NXtLWzKT-ky*##fh` zg(Vuso&2zo%R@I#46YULN*;igWa^3Y|(6QqjhTW=?=>svF{iXMS@Y*CKyiYFA~R8cLTD4M{_`6&KwR1g+BmWbgl zoAA1^p0HARd$H?-WLel3bITcyj-kzg-Lu1s^AbPMJp1YoEWt8Z>Qt{$&TF-*{6}|R z12pevr+KPEk`osxw_Ry2bHi(vHnxx3HoRg$6zv4RSV(cxd`e){ezhibnCbcmfEZ26 zf9avTKX@FY2++tIBg9Rz8%3XL7G%le1#QWe!9|%Hy)l-M`BW!gZP7x=9&o7o&at}< zTSCPHQnr|9nOrPE(0kd6SLENK57MF)RJaz8ja{AStNe`Q2Y!oI!KugtyS)0jUTAa0 z-b;<8p9jORx5Jd8<`8rngdzhE$C|Oq`Yt9o+U%G=PH}RRHq>(LZ4jZKrN~mB)5J0W zv@43Y-Im^zfXbP?<>CXs3PeZ5U%IN&^;Djuq}oH$uCgW8D7vr?*ExED4Bq+?tfwCb z9GMRxpHVumBBf~yH4E_6wCl zofis9Z52S3<(>BUe5fpZ*W~M#Q7(NnmXAKvAS}`})2c_d=@1oc=xhx$ zZ3ECEXq*lt8sSkOgpeZ=S`GXqWrV#CL2|(1^R_FHP+oY587zBJtdMoz14#zW!N@er zrZwNc1s94e*7cEVg$Ga?&jt#V+$YCUi0;B5E{3u}r$UDY0IIjnBLte2Xd!Oxh zas@kr5Qy&vMp{<73;l=xnK3Xk<+F@TkAtb%t8a(%S9mK9F{44h^1VIL{IL-~W~^om z6vZ2Mf`voOtm7Ty4h;eNu~|>SyAm>$(`#0z`^nw9_*?u%p>T#eIp=FFW{p#~?b@ty z?8lI9hU?7D-Z(gmi19!IC}5$e@xZr<)mJKN;txOFozAU z^+xb9S?}Y3y{S5G3$ITxE-dR&Pyf*nwmWCW45G8X0gF?P0rvc@$b54a=S=JCKA)w} z?4HrJ7kHEq9jV99n}FB83!$KGN5BH^B8WGiBK`nE=L?Bx2ils{mIH90`hQFTfnaKC z`;o}kY!eL)&L2%2^g5a)<|T~%dE<~Wc;J=tm3zr5HIl9c>oDs~;4G|IEiduN1vs2{ zo`@hy?h-uuWFX?uE%ng|VdU@5)?4S>#Z0>CICn*LzNSaVrz(KHXTx>_R-5(=Ktn@h z)cE#;bvwL~ydLR8sA3<{tK#IZ69iBT5Saz4*nN)(ETp6^Mb`Vc1@kZeoDQ5^$$F?v zLcIOBgBhnOr)E1ybFK}nja#M-#Ngaeu}D5Z-RAU|RPc_b%My7|$p17}=-!A{^at7G z5Eh?=KOwBgC%Es=i;EF2%^#nF)q{xlFG$r;WC<=QdWLR(Ov&}f;opj4z9v-@(wFA{ zfMx2+6tCQZU#ZZ9f1FsXe!ox^ruN95wzPU@1Yb+2Ev{m#cQ&Gp95SLlKb4X zJXN9|_d`wMyPTv{R<3G@^5Gg3vkl#q@(kHGu8*?Z5jY&YZbr3FoGSvBrz?62zLd1h zT{v6$P$p?1Ot^KUZmxSe`DU$Z@Gac9&No?5E6vhM`$y>jg3?QUNxMwpCIUVbIzV7P z`{$g#`{?w%1<7N%S7tGs9C+CV{nL7yUo}7uqK+t`USo9NcyVr7VOxIx@B^)Je&;YH zfAix*%ljqgj+Ws^^|aC9TCO|W=y+HqGK;G7?_>gyYI6liY|K9#9#im#33M{|2K471 zW!p^E)S(GZl_=IDOpg#!kY+#TEi?L!m|pv9AYj$*OQAwRK#K7NrS>UJp0=#E>OS*Y z(>oRxL`)1#Vmz5raJO-2c>juKeRay&*NwLY*-{@(by3zMP46)c zyo;h)YJYHC=}Q~BUw&5gJEdGHbxu`4t1w+V2f?d%A^VXKiW`ylAq7n`G#^(ohc9Q) z`3Jww7N-b}YJpT-o$TyxbA1M%1!}SGT7&p^aBghp852uv&~4GjUzRgXW3p|0&VfD4 zUIk&2OV#zSpw6{EWkbERh3VccRy|u8lcL6;@WtM%91jV=l1__;3QL+g+{(Sy8sRXs zkM2~5F}S&9ii+1y!g~IWyU(cnL58q?6udOy_r*)TCFJ&iK;OL$n>?qaW9REk1LI#7 zF+BE^5d0?8D7QAsGS12Q^_TKmiGvb9bJ^By!xmfbhKiu^HvD8-*R`EUO^X^0Ud(Nk zT^NG0wj}$9O9H`7`8dzvmp-VhsBqApiU<{1pWXo@t-MvQIv;}1QEb#^5ci4kBpwlc z$L6=#cSLvQnr>V|=bKj9)&GolUd0W+ zKmKXYfPUwiMszpoxCwJ+6)h@V&u+_In= zc{p-X(iR3zJFZs+rt@xGfWviXitO#^-_lwj_TG|*nEs&EDC~DzL8|f|kYoY62JHjk zrtu9&)oAA@&3?Y==IwqWd3!UIfF0)#9ZS6XoJI>1$GTjB{QPSt=#dQiSkfOjAA%DI z(2paq*9k__EaABu$#`{qqkqY4oR&e(*S}8lW20fS*6EDtRAlG+5{lCeRIbO%#&NCR zF3fhluRC^Q(V0G*{H5T9Q^L&Wo3~lF`%neKcYm3lHO=yHMuMVaEnU6W+NN$4FnxWk z`=W8=qZi+)6Tt0wCO-j9{x~+LB=hz=v8v#bz&{B$jc%5%H%Iy?RyrRARk$H>g>kof8FCxe>BH;Qfr5M2V_jOK z(=07?Q4Md+f;saqCVRRv6$TtPVO1^&?9OzLB~(svd!7NAv{>GhQPIAX4Y3_$9jv|E z|6nOt%4+!i-rnDP&=q5*a=8Sst9rLPs{YIF>5zq^8`rf1e5X`xZ&A!HFcW>R|n-PG-6lT4i<7Rw|0S*@J2J zX17G?cCUaFEFUnja3Z9E0~`?~c$c07bkc^(P9PQCd-f@?X6i>#L&q}{LbGRLS(vx+-cr%GIw7h?**s+HljTCH5w53OeM)%jU$6mKix$r*p=8-x6YgIYiex5E7KF zvT(%IhuAmC=S~c9N_-dR_UeX0PSn7cr)SlUV*1=W`P{05FR`3KJGu#{m|cv>&*E}K z6KwX%_Qu-YR~bIPdPCi-v1>5G3!gH+F!{8`d_NmX@-JS!x`VW5bb`e7?hxPYE_qeGEon;N7>LA*ZfZ@Qb{vbstrP+J9uo8%L$Rqv3sZnnt&) zWyKH7rrYc+R&YG?Zno+9RO#lQ_EVFvbsf)#jvZaxC5+zCCT6W?W24ObfqniEqB&R0 z38)P=&Ad3CMTlM$s548bCbw0+zaCUtYHD<+;I9wQns`OKxzX_vd5QujaxG4DL|0U_0Ea*iI@g+0J~c!Y-vWiIqm8@KGrF~Wpb>o8Dreq4gmnz`M33r}l5g;&ceO#FwN zHt)`RDJEtf@xa~Y-nH@hOnf~Vscht-T6lcE^3L#Gi<)}xmE}&6Lz#E6DyDpb=M2n9 zi=*c@BhUCIm3YkJrPrdiFS{9jagu{7)|DG~J=>~(h0J*a-la$q>&Xye#Aryt_60(h z|0n+$BiEsh1gT=r)o#40L=*$N6)a#c-fSzeaIu7Fw%%eG~OK!wfjSedt}!6 znZOHPH{N{h@cJa?Gosyx@}vl*_FUfhkLk`{w!XLKf#JX9iWbS)$9I=~-`dY7RqjTH z;98O{K0#QHTAL9^lOr;bsEIQA`&DO?U6|V zN?Vslu%EVHG}E`-t(|=7%fgtA7r67uROj2V|6_gI$Hlm>wR(4{MG2qy!jz`g`dm6g z{$tWczzaN2l&M9B5Vu8-uzQXLO9eDO*dn=+#7nLqW`xs}%DR6Ah2O4sBVVLoC753W$>5={iQExN~xZjug^C(t4IGaVXSLdoV4JJRmZ)kIsx4G zSI3XlkV3t$=H2y@RsuegkW+&l*66|obcJC{qw6BeHkN2%M3StWF0JtLDxST!8P1*= zQPP^{nr)I$pH%Ac4?US{THQ#;f>k`4z#lc^{fdgnSevqj%8W-+f8W;s@?=ZwXvC|w zjV9W~mAt2n0X3Ve6GW}Op1`8>qcdL)Aa+f%PlA-&kr(TJQ*xbLeo_KdR_&F(eQWs= zqG7kgf5^WN@GtNMx*GX5=||dvWp!L@*}px-oT=Y0Z@UIuEc8C4>9$TK`oj3b6EF8p z{VJ;>H~z<@3(B!<9f}Z1)Sb!(3Y^Z&g5g`$`QJ`exoZ-@Xf47arjGTa>?=$*iH%|6 z>CT|)E9B2#FblqHNtwPEXuUk}CvEr;N|7^cv)hff^2xI8*R2}9QrCKZIjP48e`#J0 zF2z%iY6zJ4hZHdJdv#nA0^`Xqz?TM3{pHI#Ltdo|pL7!%m0K9H#Df!fTb!xB#oc7+ z*UVVS+qu~QgzXDtsyQKN@!~}Of-Nuj4;skhF)=Z!^sf0Orz??8S6?Oi(!3n-ptaz3 z`(7?6&rI$%*gDW?sdMn#@BNi>L@_m-43DEi$w5T@j`S8ENK{G6WtudtBoEXXOZ!Pr zt(>W!pV}uE$7((fR$RONhsX+84$t8X7WMS)_4eJyV0&cHiOtIM>5Q_8EgW5HKj{sm z8rqHqpfqwY>+mk}5vgAJ&t8NWUfbzvD{%RaBaU?Dw=EMBl;6LPQC!b!UHY!=!{l{wgZq2n zkeZ+MHU?pIu0|>R13px?JI@y9xIJ*0)-ANll-)Ep{Rq5=@>NDRy$*TCy=p>r##l-R zX~W5iDlqwqYT)XFeS=j6BrM^T$p{r9tum9Q6-t_AFC`IPW)R`&bCs1er z{*XR&xaA=GK>@r2DS}*2yZYcsgi_K01PFxlK;CGiM>X+I&R@tKR6Oi^&X33{-$rzB zmGfRQKRm$v+g$Vm^A90KC?3Ydv-u?jQMiijzB=1$!Ac22$NgYyMcUm%&mD|)yMiS` z!rJ(0<%8l~?<2LIr@zL$!z4jn`$=2~Ex-mZN75nK6PuFr+`w9O)^3Cf|Jaq``xRwx zp`uY?Sjr|12Q?4-fooER#cVjb}MOZF)&HbhWL)K*cpWo424V1ItG8x`BN>YSK9YVGW}lL zlXxk6o-kinvBV7$%ho3Ka*#5Nk``95&fuyTbxm1Xp1LLC=$?_nLluM%C?ulJE>{W4 zG!?0p=G$hoaqfmO_F2Q62m0qHLl-BKnp7Es*_!lvz2JOY)B%h)zfFguA_+fxLE~Nu zhOQQS{vG_^RvV^A{;-2vIXw{lr4|#n6hb;_$!qE{-O-VIiQVABQG!ocDe??fF6t9| zWFLxcVUQ+$IjIwTBk`r*@kiG!E7F3Q|30FA;uT=LuJj!gA?+z#Ya?6+k~^(5Ua!Qt z5+*t!=a9WkrzlV&21c#(S~Z2l2&P#;N247$s0p6WUr&!F;&f3fpBa!A-_nd!Z2_ zFG0O8gyucMnNR2RiyFoG1$+=sx=^$h(;1tbJ|!G{q>H5cPkAWo(4oDE1;-3^y;wXC z4@$i#XGgHI#oGJ5EA`z~T5?*0H{28~{2!JzctfvH}X4mE{q;qjWe{tRsg97HSp zB=Ih~)$$RcZK@BRt`&>B;^_)({d%UJ7_Z|kE&N0k48(oFG%JKnq@h{i`t0jEQXE+5)n75qXEI{{QJC*r!^lbJ9Js#I zcKm7HC41YYkiXPYc-FGeypdMpaLI}K`{W>#U$iqci`6&rDVAqy z!WHAv3<@8+c@@erqg|S3oju;|>zk|antfb@bv#B9=$&z9ODQoBCpQAWUnJ22$D~G3 z5p7q-GcQ9O{iU=j{=!ibCG%uegNH-2xdE2MUtvfh2T_zhc=&c?0;FA5YAZ(vR=757i z;_o3kT-)4a`~QMI_g*_R3laK(exb(oqZcD?^0VS@-?_^BZz9u5SCxoGN83Xo=m-zf z%1Nx(uE3ZZL!@rtBcRO}Mf&V=y#g@s#c^|wxg@IxtqXZLt*kxfYv0^d8Ttm*B%0#~ zThPE4TS=Z}Nt5xDJxSX1)e5LPbyIq-F^h2~MwU^n+ zCPz(Fr5C^!bpy@I#m}3JZDudZ!d`#%^?kk2R_$TQc*$%r zxID;8)F*7@%fxS3jP)1OsR(gv)KZVyJOoAyoi#+L2R~fUU+SIV&tGr6F`WIZ`&)8fyU!GQg)Hh% zyDYUwnKw_U!5(McAv8H9C_NYO&;BZG?;XbBHW*4&KZ9>c^a+rlcQ=haUHj-oJ|gn=%M>CU1QxaQF^78m%SqXQ zLFXDLZYpdBQssDh_?}*QCjirmc^wnsq1#b5H#v=4ZghqmK!(m;@0XuKu+TK_cpLfA zRPE&Ei5V1c^|i!z>qYX-Aq9#$b6YU3Coo5>vGKQcC!ILRbetkd2yaHdnc-OjsdkGM zV|r~Jp%Ih3dHG=lC-&e_4K#FfN-hi{<qrjP`g5|YI~e;gH%<={Lce zZ{-)@lk7+GIt&?U?voSSTBYcveq}I+Lp8jf@@pNqVMg$kM8~Eb@XD> zAYsdL0}Bf0rXaWg5vr81$K`a*a#g;aJ#UuoxvV<+)}q&FYR0|N zrC*s4^p*Gw_!CTMJ@a5hBdx>4#94}HfCo=qyvasFk&M$yDIgjEBY;vEj$Rk%K1o7HP0Pw_N zH1fV-jQEE4&H&j9os5gEL%L~BaTL|!RQ?WzK^YoVq+%;U43F`2-y%Cs`WlZO+PL0s z-i0$4yC>@3wb_QCClVTt6|S$FnDlt{QoS6bj;fVW@xE<&t;x!j$N@#V5V;Tm%3aJf)9Df+>GGk| zMLupko&6v}qP5&&i}hKf`}y|Miq|_0eF^sr<+Ro)7+Y6%A>4=-d-8KaLYr)OES7=B zae;ZPRC!9`#zs)xeNg*r&)n99&&bx0Z@9_73^NDIQhyhbe$YympV^(Jrv zYST@tK9Y4!=d!8IfbS+$REVd^%t-5`uSiSa#&sV2pSgE0vn6Vywz!}3?y}m+dG#Zl zp_K2;pwk=Jf44)JZ9J5p}Jeyb-!GveNHteDCdq6(Goq>)m^q4LwGa;|^pEpzVA$wtl4CU<%!4eKi2QIBI3s=!X!;)s$-fnB}SeR zfS7PQ7%kkzTSPgTN@g>Lug_@L3A>E3`+bzB#A=5vuvFqyJ{=#ARGM*~vkaq>723-> z4-VL|Il7gOvQi^wG7H6<60xkR`0GCce)`9aaA|8|VmdrrWFw+fXV>nBqmwF8Q=+G; zLse^d5oBA@W7nmGfjF7yzN_Ww1&81FoT-;>1Wr*|M6@=AEhR@8Nv zUJ3F3=+9cb7SbN0Q6aYfB??tv7F+0lnZ1VocZ+{zlE~b7sa4ZdLxASZx4CD9Rz>lA zT*xX-0VM@LG70}{^f^;dQw>PFQ*<1Qp9UGj`vFc;BT;d=XPuNyl>5DzdGC# zYhz>W63x#QI9X0~Bqfq5$wNlTshAGPtw-7U(_L$PV|Nr9$U`H# z(7&KQAux)DFN-e1DK+rl!^(`gk5`$X{NMRc951-O2Rrd}mij8RVa!uoCcPCn+EXRG5k&!cAT4| zrZ(vJ7xVq2Ss72#PT^=X3ru0SnNuAX*Y_rpV7V+6XZAv@QPuCxT3{wMxV4##zPFx~ z%`b>tUOzvRpRyfG(Mmq&;HJQ-d~W9OmyxH&T1bc-3lRT`n4J~ETKzT<7URn^sNG;3 zgBhN~`H0~2;7;|H%eOMh^pojXTu}?&)iJz%tbH{9K%v)P(6FjfrP*KZFZVTqhm~a7 zlET$V<&f2NXhkRUZ$aq=IG*T?njiyB3{(927d-pLFw}VHVX~0DE%jB6BVe$wXZ8dw zo9h@C@VPAgAoWcyF|~q7oAWB87)T1h;~7pr55shM}iV z5NDjs8?PNm^pYqNe2PxSZUjCtf{GyBrV9l64{Ux1yca!u&wd!ozvR{$%&@FSv?#+J zKP6*U=qg8h*U#%v;A2M%cj?Pz2_t zNYyL@rHMiqI&$sV{7+bjG2^GrrT86#+RvOq~3SddNRD34S=Hf zg-Ix|Vtq4{Mdf;Y8GFF*cjZuR%=kwoc;xBY*gh9b3b(=XRAXmD_*!(B93paZ#(lvg z+1@{jP<&dX>wBJVoSG!?>gmt8QEUw$!gI$TFMy#-q$u$l{j&ZMf#nu zY#$C-ox_%puWrExf;(iw9lzv6xA!fCFQ{lSTvH422=7FEmVcb(&(Y=!XU6Sergw{3 zogS|ti>g-x!J{Tv*5g^o@ z(a?27JcMNsv+y0T)~Nhn)|v{S&~EW{V{`uMKEQbud@6%uA&?Q3Al^#LK0khokjA8)M6+U$pU7hHzwF$h+1hyLCHQYL z4^Cm=GSaRp$(207@ioH!->c&j^2u8qFr=8bg8Hj{#SuzF}vv7n$#9YVCit zAz#n?tpEYDizGgh8rvs=fVH4WDj;eGdTZYxiVU3`++OHOc$AViuP%<#SMh}BVqR4u zXS`04gf~kfJj-2sdRP*F3z;=DxW*UX3#okj<{PKu2ifKTtBi#zRgC|6G~k!NeC>#+ zXyKEe_-&$uoID%mlapP;!$U4{lS!}qT_Tcgooj zC321G8V=iy?Cq}2EOFcD99~Yi*)amin`{zj>M6&CdxWIroiK++NRXTGI*j(+y%n## zc{xOQ^9SwdOlsWV-WNB#_Ht%buI5s#qH3~*?ApzLpFJXhAjpJ?ikvzhNl~IKDU0}W zc?UJ~ywmbd4F+-3KTll}&X%yN@y%?m*o9lqVa4Nq&6%^`sU~6NQfLcGB@UVHTLJXK zO2j?Wh4Sq;C9OQ+yP86cUeS5yUVrl2o*jbCC$@v>ieU{a7<%#mqT+1tOQDl#wYCt$!v2qG-t@WMLr82g>MZxOlx}9jW#w)2k{QhbLS<8rd>ni>XkX8L#bFD%s3p8bwN#c z0QvTB(~?&JAd_M=x+!3t3H+$Jamf)stow_JHgnqBB zAdMbCbPk@ldT%X9O`R8UG9K-8_;9mLu)ZBD9$E3G0IM5ayuV#K~P0u-{xDVRWJu>p2dzjD$rWYa>g|o@4 zxt$|7>$IF?LH&b!T@KZV%81Cy@i^)Anz&&;Rn`0It3}f1L93J9667RXn&N8!c~g*x z>@0(Hq~z;Z_6*#uTLF40Hb5^0og4(2VQ3GGVVtk(Kz){YW88aeeXB`QwC0E{&sGCgpoh9mXH22kEZ&vWeY4?YYN4IdDCjC4hfU zd^C;{r|)Utk>S)I*kinGr#kt0b${Q{=4Rd2nCSId7rTILWfhUeOB?*}9+e#xBID^I zHYL1K5pTbu(k}C>JmGJuW?EN}G~b84(%3E__4Vp(+094#EN#!?8jmoQ&|Nb;bcH&) z3JqWyV1P8;g}k*>@y7Q^QQjqgrjDP)yf>ZVmsrdA%WC`uRQR3U)s0W^PEaK>1oEB% zL?{9xJDa(+mm!Su9y42;mm>S((>&k)EuC-nb6~okvHJC@ctO<&Kyu}qODV#C6di#z zabyAbzf8>*ms2RMihFi9g z@Ny;Nxz+?xo1e%Ns8N<7>22U_V#-1qZ>ag_$L%pw@inXN$So43I|?kZjArfxtjb51 zCnYNl4Wo_fC7O{R~znCqinT5zrf2 zBqa}dBd62+LGb(2F?YZOS9hTSjLYDZ{a+L{nUWy7OxIK(0-tp75daXyV{&i^B$feBTN4MTQLyj!ofcIc3R6c|0wh(v8@p9*O7%$FRDtzX;jXhd3$G(9eNi6%5@!Nx39}o775#)^0yK!x<))2DAAB*_xLRs)yiI2}d|Y7v%o6s@n5?#IO;OEO9|wKmZ=K zR$ctC%Z;h2bIf!CX`l9~ zHaWNaN8wZyZBL3PI#k$BsLxBc$`wb8@^8gVo{)V+Pi1&;a|xt9kQk!n;kXT{yqM`h zS+>(V5aH_Ni5D~yRR!4BbzX2nkU8O^4B8uvNA6el1JFtLVFOd>qscD8w*kL0PS&6W zm!O+UBrUgpgq0Qk-KrIaC}2i4r1|+)^ZjU*QKE454+jI>VuaXU+*nV*Q1&;X|FBR?OdR4=aWa z7UnWL69BwUwD>_x^OMjO*4Dw>H6NSrcT&{WetufhXnU@+*ei(d`4sMv(H9dMGnp5T zx1nVx1Xev>NR8l4xHN6}As_FQULq&C--x6_ojxNK!6me}ez8h+4IP^UFqN`@ zfBvJWO&&x%UteSfEP2&ko!Yx72AC6}EN{*~uvPo}OP=R@`<>ERU)~4T%~;f;o9#%M zWB{K{395))eWs2bt6=H#^f>(_o3XqBSv&$Gh`!B(Ux=!`_i^80@hKv*UK{Ydw9mae z-~gkHSwo222gG~m?Bd@*m&w+_2*_QR(Z6SWSR=FQh`t(EY310Q==;Q0DRdE;72d^y zpoQ2ia=`8l5nt3SJiu2~{yNj~5o_mYmI!*#V>C1V#UsfDk5q3R+B_l<3)Co?lYfb z)a){VQ_odWQdLppF+pD4!D$*gyeafeQ@n56p`@Dm8U>-#-3DYiUBjcc!m;$SyF3o3 z4Pe(?BOs>UQEfPRV_p^r;5fo%cYv;T?VgK-%n+Pt^+TppxV`Um9r1Nb|3_hh*{~s+ zfUC|AvfzN?SmV|jO#@@bMJ#uG!tK(V&dAt_-Bw68et$^*R0b7lwR~VZ6=m>engsS& zgZ1?^U1Xz~QYJnp0!(?eS#NL(DH&mtLtqXnfN2q;OKW1l51m?O-Xy=W3iUNRHx4U;s9zE zPe@2qm+e$%rPc9>iUP30`tH`xX8xlv3JD#T!kA@F;+Req2raop8^jFs^gBM?bTVex z;$d|)*mZd*&3&Z1h@Ap(91e>uG?Qb+o_M4iEx{k*l{w`4v-Pf*s4?n5gAfHLbu29Y zFu7QjB0q(^zjfq}x&>wS)pYuKAw`29HVudA@56SWmG8w6(}~b{h|E8p4;p)OS#F;s z&(@reW|t>-u|WPAs>ThdiGXKz{ZWc&Sfhl!qnptDoJ*3SnC!r>`)twW|1|6`7tz}$ z+)pyu^?YPIvU~DN<5jk1E#>jy3A{E*%!IT{D7+O@&9KLW4`1mBREa#!&})_SWcoGZ zB&96+=hduwCoX`Ve#5*>t_H!%X;kyo?ygmgkC4z-R=E#~XigAmELz5Z@#Q6{A{cE$td%?wKD6OUJhmX~6H&nYAt-l4P5k_RL( zbbVQ^dsnz)1+&&8&t+rhIuU^|*|LO@2G13qB6e&i5n%cGl zm6~|@h$YhY5znWN)sw8q)T({3e-pz1a%P82DXItoOJ`QUU&H>Rcw+Qic21Q#)34_3-~f1g zvLa&x$s8I6u4y3AWzk9wI#CLZpr{79#)PA5UD>+Kje6IjNx!)Bbf?x%f_4;COq!f^ zD%)o{*6znQSEX^R$kk7tDnp6)0zn*+gsHu@b#xRQOdee1-XLVzU%rC(atl-s5zRat zQe7+ZoJ7c>!E^zKYi+z=8r`4jd(#zj$Q-n{YN6`AbW(LIq!*_*PTfh_@(}!}J}DdF z6dTxO0W^$lwgO>>8s)-|#n_}(mtWs(NO~1|7PkToHhcXbHp9J6W~Iq0JTyjPTQ*iU z^@Hkr{x#EioG;G=GJVC-T(mCFY{_0pp&!aD+h%tpyQcdxo!qGPN*L#mLxZZhA z%mGYSf}06oOAzJu=Wng<2`+K2mzYl~zSI5CD1P}_=#xc(+4Q3=s3edPTjAP}1Mgz} zkD|P$GoYjd?c;#%+%aMzeYH@vjY){j8PW1D4XotMLGY*==!7*6#)$))GY~#&u%vx` zkw}YEi4{M?F}L=)#*56UUaM?BxM9iUaob(XfTOMjJv=y_w-iOZLXg28gz1_q1qJ7x zpRv|F4Y}i-_Jy|j`2g$3y5oXY-Ta&Yg$T=H_DaKzA&173B6jwF@^5}?#P3eK8$_Ii zK3J~DLt9ZvHThp3eYIcj^e}JFraFRlO)mpK#DeYMV#XyXu!FWOG86SlsKx-? zMhmxj>Uu-oJrP~Q8|AXyrNakqiLMkeH6>oqGHBZYGmMUuCeMK@>I`%rl~;V1l3>{$ z&)Zw#;V0a8*>0!n`*gmldVC3gytNh=G2qvRc%&2RQ7rU99liq!s zRTfW9{9MfP6$NP|ncs1Eta_G&TYg9PFGeD+1F#Y(XX7(CB>}g^?iVh?6U9-YVLtnk zzVK_3z-SM{4|ig|^zAOxvgt)5lI?RC!)fgDe&fEaK*J^+wG|80DbvWM#m|*U5Fu_< zbr|*_*KtO;=1gQwkr&s=L*;tj>`7zV4@lsBq(mDiYI!k&!K3;_6Qj8A2&x!F zHro1J%0Q=JuW;yCx6E@6!(^E!-e=#wudqH>iv9HQoNeeM_=Ts?OpgKQt-wUF!pWLK znH)sPyeIfF?J}1zV4$BZ)82qG_+uC*)RDh!OsTTdw?E> zJ&mpCh3AE3B5KEv!G^WrSc`w@YlYuqqgj~ADKASc7}k1R`@VoYRqm3qf}#eNdBcp{ zFD4_%6Xa`nXglJgY~E)WBM?D`_6W9pHmm%?K2C-P(P#j-WWYk7XAEV)xYYE|98RA_ z4dq0Isii$aQj8G)Hv-QHy}5&{4Ht#EW^pTlOQI zQP=xV%~{4Q;@b+Q0@(tJ0@1+vVb*y13a&<*c5=Y*0aeyYd;njv@$@kK9c$n|U31mp zF{&bBufq*553?QrP&psep3|(}*B9*^xhyDIU_9%TJA4MWd`{Y(WZ{3@r5r1uR~_3F z?21&pmHIBnu(%MapMtdu)}(F+A-U;DsAdsD-sz`sA<&%}GjUms;ec0cVeNLe^?HSW z7uD2^R3mKA*C7D2$qq#sbAumGmy()@j58Mht@0nm*Kz03znAvNJWiGNU#EbX@S{JW zOX=PEChUnig7-g)e|>}&T-Rwd4vmyxh{05#qZ+4AR9B+k4nO($6eaxO)*bMw!WA;h zJnH*~3!ofdCDRdo8%SBdfN>HBjx<%Y$eyLZQdQ@fZ)EGo!YAW5X#fI6hItW}9#ipT zMH7*vK&>MAceG7T=~CVEJTOzl2FG)X0oHm-2jni8#nfb5#i+Ky{qPN&$x?k{_m!~T zKSCXW=+?#QofZBVvY;^xpfBZ-$7Qt-yh#dn%2AK~Twm#mCJKI~r~c>dRq9p!mUjhffd0uDD^27{%yaYdkPuA+`}vteu~)3S^+JbM@`I_T_G(V zOLs!FCol{v@5dbi;dwj6`~Ok+Nvy*?hk=NNy#Mo@3Hk}B!|I09m+mm|nWjEsO>!Lr zFoXboBkKRU{5Sgl@+KuhT;FY+z9Q7#2DYG91%Je?#vy8afP?mTcR77erUqeZH40?b zj-D!$by8>0(Tm&Z@AMofD{)b>+fO~((qn>^5C*_F@#Pz)C3>`tr=qft<6rK6Iuo?= z=Mpu~W8&bGN;gBHu?uP94ctj*llvLN{c=PGk6{aSlW9Exgynm1ySGsG>Ri<2WQTD> ze(OZ}hg;W_7g$6DU^rFoRY9!EYIOJ~Y_CP+ol{cMG9tjP3@QjY|Qwz!kKjOK=- zu|8=GX>UDMF2(V<%#oK>rPE!b*UNysK|#?!uI2uaY6lR5pb>1q?y33w@Ny-B$kgz6 zkqP5~h=kk$^Y~{ER^auM_gt=j$BKH_!4fqFV(ZM{!!<%N?Cahr0xt*%Vl8w;*l`Qu z1)2;Y7?ADFfTa&lCpY5lXFJLPPz#k6LEVL^sVh!i$-QsjVNI1biH5yO97W)P{xvhv z)${|X=5^mgBx&mCfgD)OR><3##jFf{wWdcUTnCs_u}OiN;I`12>3>4 zQo8Gs1;08zFS5jkm!t7iawHphCZ9xN&r2_Qb_22W1x2OHl>(46U-E8b^ZG_&&U#`o z$AW*Gfr3;7##;4hm@MR!Jc`DvU&|doeVha#oalZq{Fc6mQ$~i+I^XSDxwUyjPZiFg zErP5WBsm!a{k%9(#jb$q<;pGmY>S|9HU*il@GA!+qJk_miBK0RAb{xekb&^GAC z3eQxf3vt^SLEu5`j{3Q6%n-FE@^n2*6O8Zjj7HX7tVbslj4%**FuV0U!kHoydHfXC z+d%gvcEV?a$k=!4{K;ami@pDQ*LBAdcL=_tU;F89cPU~i7F7{8kanvB-G0k%t`ia< z`^I5dRl&V`7I9G60w~)dugJYtUXYFwU8q>KvhIP_TeDG;-up}a%U2`ftH9^V@a`?U z8GE8|iHU^RVCq@20%Rv89&^EL0#raDitwK5GG0H-ZJ)FPZNp28cmOx$Eeu)F+oSHb z*97i+8-TVJ`MFbH5)r*I>S`4mKeJ+x`3UKzI}lw%ri>zm5CVQW)-$xBZ}|sl)SK;y z$Z1v8gkuAkR5;ZNSEfG>u2>AEojRVUr#Bzf4c&S&-Lu4yqdcSZ&snu7>TPo+i=7}h107^POpC^loH7DLqV#|D(PC#Qn&3K{PWx%u zQ`4$vlK)K7T~;@k*Q|GXb0mL^swF-==J29&dF)H6AXqbvQ%a@&|9itHhHf z?O2r!T67thXHPig^VNUs3rOa92lx?rs;!kZdurJsSkND`s4%Jo@no{w{cDjx^^c3Y zUN@^p04LRry&}3$w$tmW3tWFX&8$~S-XGEl#%<<&H`wwl+LV+hpSWvMDwgTb+3M{J z4FpJXBwHTJ8cLQ_^IHgZ^_|-pg2#rlO}eGd3wwhfkMuqrjW;LJk!uW`tzQrA>WNQ@g?=kBhD1v3W%0 z*a^v;%2)qU*lZbZ=QO?i=^xk;KC%SE7f|2dhlUsO(KOv*iIXy#hX zJ2!_gwVtPmqwx-yy_&b+R4X->dy(A7E2v6k%s5HQepGb+f&6bCu3( zqD1kRStosu+2*Yexw8ymZTRZN{f>n&}Dq(c4q@#*sk8=bM@RUp;p>ESCN zul*d@5JIrx_MH%#6`iB#Tl%Q1WI6fW~%tmlNraN zlFuVSX@@W!Le`@-H>PbH1h2@yA`~L=auQPNpVkq$b05#0=LdUhr8HLl253Z3id%$z z8zU;;VA1b%M@7l{*r_kcq6>uH-X@ zZv-icrDe~?>w+$mxxWWyj0?w-3L5S;KOh|8FWc+oHk*0z$yLF5maF2=&3kPU{iy7} zS#ntrG#-H%K=u(K>fN0=rb%4ea$(GK)_~FpZHC~~MZil$dc5swML_itwC8rjC91(3 zMPPASwpBpZ$v?35DDVe$&B#Blml3hAq3i!U&&EtJ!=~|7jiHZouh>_7ExNYZqG`qO zC4&L`WalBD%5)1)P5|-i!@fFgJ=2@lPGVqlqiUjpS_-$Wck1!FcWe3gt9U(ID&)LL zfdxYQP90cO6b17Z%zcr?YG#-oy&&zVW)A!_$$Y^j!BdU`C{T}9Z z1j6Or&O*3UhKglONLzhH^l3j)tm5VJhds^BsCm#<&`D@GttDk(tmRCI)R!Ea zrt{(mlOI)@6v%cYZ zgB|9HcaVuSwZ9-!*`^@Ndi>Osq;AiHmc8^byZN@Hty$@!=aFj>>(Z;4|#$ z$3N-4OlpG4TwK@_9wdo{hNe#*04F%~b$_HWK>`;zt6AZk;VKmUI`(~nQ^@ei*9(1h ztaaQ*B6%Lp7~giPGUiQkeO-g6Pg3|i>CEfwW`5OMw2 zIx(-U(mv?)p_GhnPmI6m-UDQq()qxF_(6Fbp0YTg@2_-+>aJPk4){ z2{}s_=Y-7Ft=t@0$tOCQHn%qYIGlHJtXNR;vU`x2cK|leq?Vru`|9-fmf?{NHB?rE zafsO2WSGMbN3R=_stO z>ZHSaD#|TrPxJFPkRqjXvi*YlLL7qUwxgKHn4XzSWOm3DkiB+5D8I9Fio=`EBOfjZ z;eKA}>IeJG8&?D+!*=SxB=EXN^qztbw z`nVeL7m~OsdK!vDoHkA&9Ng~hav(;ScoZ0tt4Mb6PHsQqGy7JM{2B(!I)cQWzMs9Y z#@uX2uvq5piNmRarIg+|{r_@500s#-@E}{>*@}_7Dt@-yah|b85u*?}h{u&zwxGAj zg8pq-%UTHx&HOna`-|L95TR-t9u-2NP0xVsb=GaUf2~g|Syo@o=nCu$2lx4r&`8@# z(OdJx>9yr&7ZPjzI&Ad^dujM+3!GNb(wojS7yFXgrkpXHsr9;gfVBTv!yk&6n6P>B zxW7~zf(wus=o-DU{V!j}J$5^m3#*qHuOD_=n#cUgz5>4%mjD_gC`KBcQNmzEL0atXJEGeRvg!WjmSOFQjyxrT#O> zHY4VFVvpb9{E7{rsa8c*0t^U6^4K%=Z1Mz#k!r@aGcl#+;C^*o!oMF>QKd9i4RUqh z=`N@B{jWWFJWrI{G6RP`4_qbLW*<(Vbiv2z8fQTUGrj_80GcXq>COxXz;B?i8S` z4?o5Q{G@Tk_}sYN(?fKQALqUo<03Zqrcf*xYu0YTa zkBN#q+wj~eq5&x$vh-V$-98*F(*|nA#0uupx;XVSen3~R{0-T_TJ@?xuetn96{SB(LB^O{uemQUXeh(Y$pzm@GQI+#Cp^ebfKGk9CF3M zHk?eYXC=3(Ug}II_1TAr&HV77AIhCWA)LO_23;+eJeN!uTgfp>9qdhH)x;m4*RxZQ zbb^rC)Z2fy4ud0A3zg0D*P8kj=YGQ(otp&+5qStV0OmR=AuViq;Ws9J{)A7J zx86jpVbGPsD#8E!i}}VDv<_8vu=@jdfQ^V~q#{2W*@fxgnU<^LFG#WDM2?bUvmnO1 ztrA8ow6S6Ia?bhT%fkLP7y`EUvtsp?&_D2&B{KLjTawbU)+r z$7&FKgnvGXNv7?BSi1xLHyHZ64B24_AeTamElmiT5_C?Cvpo;q^6<*2Ht(PEu+64M z-B~wH)#A*{BD#XgNdrk%0l0fRhN)2+HVxHdfBh{v@9@QGH`2f0&@O?ET3lEEcM7^L z`gu>DBY)93Rbc#J_HBjO6&{|P%AlB~E0gdwP?!x-5$A&pbrqitQc#wg92ZgAX-6Gy z$BP|ezn*>5w{8CQ`MZkOU{K!jGp8KP|*nPiM_sSQ@a`p zuy_yrhyXd|$wpspjhQ*8(4npm4ajYXAc=p12w};VMhO;6%Wydpr|`1A%TA|< z#BZ1MZ^&Cr%M1ho%M_2_jo5+bt7jVPv&${T+hpN}nSK{!#>M4wvWGr|TJ79GX?L7f#h z0ds&vOWzPtiXWIuQt3nC-aO7io(>KhDpuu;oEW^^UeMZwznDCUg+_v^UJLvLP*L({ z%ivFigow7~QKiSH`MGf~IG1kMbq@|rey#~=RJ^-KCwZB}<>^n{A>?(^vv#bM4Y%t| z|8905DMmb(z3V=bqq7r~tnwLVR1+)Dvh^>d7)kA4_2p>q_9Hn}ngeJb2G4M0RES&- zW*T^!Lg>a|>G1T+MNSOkVQTWA(qBXzv%*suP{#XOj_2b&LHXkw_l$o1P$V;ovZWq(Z)_g~LM551s2-4|#Tx@~o(?Zz*k54793 zCrzxQ!w`0Z5tel0la{!ywk9U^v3LJb7$_7|$Oa)3LidG$R2rdWw1B*1-*dmWzLTMu zYXK7hX0yva9u_9eAdb(!N<1M1Wun&oIqx=<=F(Vp>%}xj>cESI@93DkmVgkK@ld(! zR4c^B5(*dN{Cy_*nbe0EeV*3(Wf^FB`9`%6^hA-1DzAIDKP%PB_cSufjfPOkFlS7o zF#WfKm&}Z(d}S3ZtYPlrZO>sWrIWgy)$;wqN9K3ajet^S;&b^>BhoiG?e=7Uu@mB^ zw}s{Q%gfen=8FF)ex^2M!Fv%myv_O$w+UWYmgry3zA9%-_g369NgSwsVioCX1&l1s zP*^8ty2yBx#2@MtoHIEW=*`WFH&;5k`fqyehmUZBks0buiFu&5n$%Pfjq?=^ z%zIyVX@8!)8dm=PJ}vH|$*^BS%W&33828F?wmmCJ z9wy_^O78@HrT1fvcdKqhJQaiNelv{m+oV-tdUs+eq~>oj>i67ts^lTGv4xmI<+lfw z@-I5QONuAocfLSI%iG|VM~;lgZG)m4KG!vT>=TX3sBsJI}KXLJ)`G3 z9iM0ZuM^}6Z=dlJuU@3x%cx&=-Z_t06KN9(mccGkD`G9UZ&AMvPIb-vax0^HxO!pX z>DAYny%e;mjT;TCL)55B=Wt3@rV!te&B}zUN{sxUqIP%f?MU zQBz>mdkY`8Zku}wnZT5|8(0@8nV*|huC7iYtmYC>72wf99fQ(Jbs}?hb;7*6(Bwrs zNH26+ZB32~Vt(B?XOwRyw19{Dq{J-vR_QyFR5q76(wgn6p;oc%b6c(8Hz{qnJbFI9 z+H)J=1^P3pF3&;TIp6HJqu7<2aIvq{WfEPw^lBRfFi#w;o)0zSaoQ1Y;E+%P7 zKZ;+!cFgG)O89tn<>a!;yYQvn|H0Q;#x)uDZ68HNK|xWZnF`X4fYfFI0wU5SOr=|- z28>NXIwl|>Eg~X0x?$1{(lBy#vyp>^&v{+Xi~DoGc%CD$;oJj z;?F1ZXNndU-2Y6F{y>jr(ag7ae(dJH^c<7$xe8y}dErKoQAH!IS&~Ufni<=V>KYBM zQrdGK!!-n!g^dbNy%Jxb}DVEp?1ERVymJjr3B@M&dpGU%eXu6ri2HoiWn;;ow0O)zyW{y?ahcfo%>j3WeLyCD+8-xcGNS!yfwB<=$%*kJ%sS- zskGcS^he`Nb~s%Cey<&Sky4f9H>7bl_=jmw3u)wSuMdkyYvvVYD6WyVmC85-7xR8F z$b`Kgoo5><#AQX3nHk^idsu$8N;cis@bxrwPci?E)X0zDf)4)EyK+`|y0+WW=D>f< zmdn|yMt6|+o#?bgg7w9(>$Ci$@ztPuZ8jW87+X&9z@?SF_O?4`iBA{LtAYD*r10=v z4k;9AeT;Si8TO6_NDX}5GdOw)0EI;6g}5cPBUv~By_6Mb@=gifEpqR~TnD%HdzW_; zRf14g(te5HCVtJYs8hzvX94KHjpEFmC_ak>gSV7~aK9SqHV9LLp;%tR1J1lBTsBXx z{-c@KHe3O4#>`9Gb8HRHjL0z{nA|Jrc-CrZGG(EW7&=8${veTH?17YT@L$!L<^fY)dpWM6$RLt6*Yoe#21!OgJcitm^ISFDI8lao-4xi1O~7RS`_D+u+-$0xugiwKrPOzD+(J> zg_JkH)uI~H#IiOQ2wuQYU1<|32d!p}A=}{grqvf$)`H28{eQkVOViwQa2KonV%B;+ z8q_P2{!PgPs<1g<;nqoUT%X;9-l#nJvOrEr=+mVCM^h40klBK{R(dupZAaW8)UC&R z5SZHZZ#GL5SX8Mm-8UEmOOegShlf?HI#T-AOD?{VfzBvINp&|%qemsJA}x^nW3LDu=&^aOPq!;b3C7*9x3;TejND=_W~gHb?r?FIOGi? z%5cm^$z`FUzCHs-dBW$~e+q;gqK@BD%65j=j0pm*^S8V5Zq#O&x`_X}Co`5t?xbuV zY-zU5;N7mk^gArUgo~kp%AmJCg-)#dr{2esA{xBi1Mf5Yj#o1mQ5QGo=*EtKa&{HF z_KYAN{r*l(NeU>PiE!Sdnf-$I8?|e?>gr2CFeT&`m3uwqcFvN^%~vB2B(6U_F1qKR zaBpsvpR-!cpv<-TLa~p>NXlUaB?{@pRuN3N3cV`3es~h203?q{_GmG97~D*iy;XGM5Enj2X`aRgt883I;D31*eriYZhv1FgU+Adt{U}nik$r7 zzWRLs;_H{78E&Kf`quqqh^%rRsl`t&PyF9a%FFg)je#Bj>T-0dOK z)ySR}2jLq1vc*w&v#3wLyi;&}i}w;J#=-PlqgCFPU;0$Ul3{(u!_nHlIPjBO3$g*8J~ACtz}PKtkZ|0L1Ow8u!rn~X&~AD5}^ZLzUfx8@5`w$1UTx#UZKu3Oa4 zXjkOxijMvol!rPFEuU!B36rxtPZ*3YDwK6vz9icn$0zFji7&j?YIZN;2znE40pJ42 z@*azO?3>3}@o2YyG!n*om$To@%H7_os~N4{SKP5hvEn6mx=9jnO~NfOGk!2;XCUtb z_4SRuxJTt0X~Lbn!B5ObyaGf%v?=gdi7+mtY=8e6B`g=UIH5!}&y&k&FK}xu8Fa~K z68E;Zl(x`V$mpo?u+9#3VF`8_m6$KDT!Ob@ z85ry52wd5H#{E~Fw;*62!jZUZ+SDuJ`%TH;I6kuIerS5~nA(*w_0O-N7LiGmt($2^ zMg@!gN{=Fhj;5E(Le#K)301|uOJdM=SX6*t&B;qvm-1tizqwr%vUf1lp{fY#z*b-N z7aP9lvOmANUPPcvREc{Hy*Hl)Q8?v=**mg802kh7bH|JCc9 zwXRPd71XYHGjQbQiCOAObY=$Lmkck-f z>rMw5=lD;y5tyO?Q-^7B_F~aHZt2mgvBcHK9P#V&JWc{nh^as|+cxo!X0i?v;p~cj zZSyw9OO)bw^?+zRiYrMDxrZ8mmx>B_0V)p(=k$Q(s*fDiC`)<#?z~9pn!WX6(vIu! zXhUcGXh-Bx*xXiK+y>$9^s2VN*UxA0PKRQsL*#0dSN(Kf&gGfETD|_gYl{?bRK=ib#THn4UEwN)p zF}bEXW_5V^f!=Rx8-=T!H93mFN{N8)XxOmx%Ik0LUZ)S1uVa%yGq@gL^EY|!R1Iyf zV8)6Q8SFzW)t!Y=9%i@$$Fcn1{L=w++d_wrvtjX?g!_SxO+2Gnqhef3aB();js0<^ zu!ewz!K(vRbG!tW;$)?$LJv)ru(dBTmhFlrwTn&YTc=6duJ3B^6%RdCB_=N*Z_aXy zw9N5Wj=Gj;gs^{t`z*;$Tq(9viZhZ8u~If-#FQ6#9?n1gl~k7I8mD51>pSt-jM#r} z3NO11F*^aQ>`%x71&X!wU(=85mJ|+exko<}M9=CZ0VN`O&7aB;rcS<(xe`K0hHcKA z{G%~<0XE19XD1{kvIssmyy>>36XO1`-sw_poBxQyuD@~K$DjE|D|WHp#yr;#cz5;j zoj4Zq4RwJK(a&G}+LA#za6>@Tc;RouwV!Z_zd(gh5oxYK#qz2LN=BbB=_$sDO!vJf zh8Wa`}N&*uFdzj8sf_$5WUuU~_hF4`}!^^yT@S>V3!r))yo!tby`a(#0 zfp~QeOi4$pf-e-t{1l+J(Npgb=)&C}a`hMpzQjs&Q9Aj1H^y=Xd7pLwFh>iz5HIrs z+%?J94XQ>46=Bke+>dpkJ@Oq+fbN8twWy^c^u(;w8+YsK#bb06eov+-I!nNCt}{Ii zx1>?P164&V!%GWt*3YVHz3UK>HnNnFKqF2V*5NYu`!M!=v8Oti5%G*({i?*_MMxu8 zmzDd`wSF4^>Q+Fh$PwD6b6#sHK)|d#*u|CF?cpL5oG9HYIIo5tgA)07#;T(6N$nY& zGHzq6M(!&@xY&1we26>arJGj#h#mWRJ5W;+U`OLq`Ek*hVkbtdZz9Z0< z(t!PFQ!7(fSFPJ!Y*RZtyXbjx?BH1x6zI2FQ%^FCdCR8oHe&ehxj??VA&yaH3ttD^ zALqq;l44^oiwc(v^1M6v^oYH#vQYkdLtzg)E1T?5^|l+yb1SoKnbq`SFYUS2?EaVew$O-#Y=z|jt0m~<;ISK}L|Gw^45h?YnlwNb|7f=l#F+5$ zt91+UDNvd{PM)8Ba3Zv}gD;OO-&~9~{)4}?(}DR^@6o1A+Ix=~Nd>)!SzoGD ztQJnTJC_C{sdrGVNXEm#%1vqho#{YTKyQ!{rv(4*0sW;o0VqVRpp!bSb!KFTYXsUQ zaTK$oq{+q9E>@R=_KvYIHAb+n{2I5CQT;vE1_S~gKq;fjQ^(I{qbDNfxS3iNo%YIy zA5a#VWG?u|)h9YwpEwIrS-8m`=C~?i%a@`ul*XS=mW6hI2=ie~{-HV<{B2nw|3cSN zIPb-e-2xa#rzbbpUcR*FU**qoCOoS9O6M`%%Px{Jgx#vf57&g8JGlq1P#O+tJL4{j>w(+t}>5J*! zW3qDij!LNzn0itj^v=oNFh&^zfW5H1fMcUlprsak8|cH>ni}xPpe5=s!Db;$_;ma` z<|{*$=CkIXrwV-HbBctK9LMShYm`}32J$T?>>mv)Tny*N4fFX^XO!yyMy!4Nz+#*A zHt8{YsL%XtOhPZwu7k=r4so(@0^Wtg)h15i4YYg)+a|@0ZDoG)!d}ww(VMXiSzF(e zxy~)w-0dY2gsczHY$s4;5L3AFQ`x!)%u}dR-;!frITyWvei%?`1e(Dgj)@_ z5L4XZ=To%M^34>9X6#(Gi(JmH*A8+w=dN6BvH#YRQ=%KM(&%)swm|pE(=8mr(ZIW)0xKPn zO@H!GTuwf*LtKl7QbuQX3g7(tUh`+xkX*ne-S7-)q25N+v3K)(}c4QLbPSXmX*{Km8R1otm0hRp2HMe#X7yFCb+b?EI|##V=bmCejO zdK$unvEK_xk!aZqD_hUtOhTl3T(0@Va2m}lQ|9cgqSJdeF*rt%`qUO+b?s&OW-;96 z`G@{LuL%*a3fpL;b4<72K z9SItA<|sIKb`H=*4oB>@K&vh&ikH64?Q|&9 z%E6QOi#joP_4cE^5U*%{hokkPqTHG)+XJMB&#mZ6mH~sEnOqkQL2@YIyI+`Q zqC<>Qm$zhFC%%vfP zgA{LVyLI>K3n`I|#>>B+=NC5)LJ9c;17%88JK05-KE@|~t{Tah%ScE?I^0wP+s;QV z1fd3kWM(1O^Vr-rOxb*tEN7Qzm+bsCSjxlgqggrJIg(*YVo#Q9bSR>M3se`qZtCnHVD@u-+WsuPBOQ{07lRi&2y^1O$d0T2`9|3ih-?ov4@`P7S$g!5?| z{G7qhbA#B5Gi{J5YUj8p#%5R(1Nqt$ch~+G9o0{5R$X?@EF-VjQPCwM-alU(AWw6) zCp5$>{k$S|k^FmdQF2-6P2)NTc#)D0S;z!2Q$@`+2y}~4*|^YFmHTlnPmRaFPW9d| zBM);vU$rReoBs3uR*R}~*olZe-RS<6x)8k* zUreJ*^EaE}2dcJHJm#=-prksU5OKiSX)9IAgE1ST4qoBp)f^0jh&%k$xMCb6-sgSD zcd=B!ZmA}`E9s0g5FMD8I|jyU@I?$z``C#ox`>#LJ%C<=!p6^r=ddR? z=WaR4c>nx8xpi=J#H~q$uJ$?A^MQp7&SfwN$oC@akMFrq0li=5yGnZ-mjj``LD6rW z-}Y}CF{(*r9G#I!;)roeHexPQ3!7M_2-7v#9xf)?E89}Nuz)`^AXmdR%qC_7Y%+cF z+`Ed?+Yil`$Jx>L80?~BL5wD;=KevmWky3;1cu4xMHUW896GH4g@3=YPeyr|sX}=G zGlvwCsUX)HUJOGwL(a{>I-CE|a93Cuky^@t0&}P`Y`6G<);9~jnwl7>)Iywe{U=xT zS%_wovS^C@@7;iUk}2GXn3@j<%7V{6ZJ_eqRD8DTc;#LN_mernVGWyC!0zkw;n!4u zao3Kr9q^#`H`Ru;j4bTdSv5qXu=mI8rf#TF*AjU4$eyDJ7T}mMAcotF0T&n6!W}Dk z+u<4P=4_7M zk0K7L-IRXxYtB-gS)BenWG{ufh<^-B2MsxWkXfhlTp|j7yoZ`+`z{0ZZ6#};HlQlh zu@pb~?Y+g`$#DB2my-^~*wq-PvxA35ty+J{5&{#G!QbB&m?(3pt$dK`! zl7RURNk^I{0N9CF|K--U!}h5sI{2gZ{?8#om%v_|7vY0+QE;s_w)Um!TIC7+NtD8> z(iK#&B6C?8MQ6OmN}|=cMbqo8&xbYg{U*MrHM1CSv=(bb!*i1dNyE}-uISb01lM=p zF@A$ZzDA4_ubx06k5=3gk9BuBvVl7yyG{DzJXQwurZsc8>>rJp2P-4gaa;E5Tcd`s zcq(&%*Q5R2pV5PA*IvnoHM~QPJMPmkzR$l1+5+3%8dHqv3jK=X9KVPrYAL@W>cR zE7bY>B~r5|^!BQQ+-CjlvMA2bKla^Akn3TeSY2Z0#|zAfo$bbVLYsg|fhR3Rc&S67 zEGnsDCOG~LCDoN9+U+JRW5$I#l2Co}@B$*iM%lQi`-XZ`z{2~sgOmpO+pCs?Q)7AG zGxUSs*X8EDfYrCtN~Nn}=Kk~p>ia7?Vcux+3%)@#*FT!2ij{WXbnB#w$q^FoWz5Qy z6d^Rsl!o-SGe3&MonYBOocHCYd!tS?@_N`RiP-vWyAKz}UWkL$Tf}+?6n#aOkN<{* z%g%27qq)ft49+Lg;fuZ6lTj6GhL*GE6^vL!KHTBCL%8d*W>`Z@$_jxbXbD6%JjaIt zjpAGK(+fj9QhmGA`JG$^m*@XTGu?&-BOD}tDF*;%kfZ!gGQZgYO{C}AythbM5}U0- z7TIWWPUo{LIV_F1)UM4l8vo(WN~qcI3|Yd}_1D}HHUbqA$M&Hl6MWfzzY z4lsj=bm&Ei^hi#zLaHjY!pW_qFF_ZC7N{(@QpO8-R<%OhT(Utuja^pxTX}0H1wgZ| z&hP!3_t$$NKn<87u=48JHso^@hnLjRk71ejqo2s?i{F~GzE*`dN&ED-+I6FnKp`uaDB|`@ z?&eJ%C##}iR))3J0ZFz8%WFN zJ};MuY|!NpxS=^KFC2TO3kp|$v+&Z6xwC8f797>l=$5amWfeKyvy|G75Q|ZTRjc#( zO6NjJs~K>^#oW1hCzH;%E32hvl{_60g*|KSV8Ms81^JAmHz1O%gFTPvgt%ML&aU`M ztp?xZWP}t7nOK_}@-x0nKH8L9tv;Z@{_lLh%WsvD5>8$l)QNe0boS{)YWEToi@Dk5 zVA6xxpY{{HhtsN8RTMgQ*bRyvHnNLVN0F_#oUZNkSh!K|M+t#W`b80fgpV5hzIRhD zbie8j1WvYX6GtKY7^IVKNi`ueqWCSdT1m%Ge9y03;BX+d4TVS-N?%uWR&fLuX`ry( z*CIO+{0ScP=7F7Gx?mK?UDVPbbF_C$t076o+*0#ipMCQu=cPuE@s<&TY4em3wA`=? z#H^wAQ`ifZ&exvB+Fk)q{e^dUc@oH&Hp5MIR^Cma9~DjaN3D7qp8xbwXjf;7sMJHH z+9!u*-+&5nIY)oJ^mwtzXlX?YmJrG&>QHTYf8yPJaMy1-fc|Vkas8RF?U?x42*Ec# zWxm7DO1GP!clm7mt721*q{3v4O7M%)xWuT)d#1AfU7v6|xMv(0Xd$tyZ#x6BbF_tz z_zpRqa~h1ZRMkE^p6=J-X#@`!f2@8n9tkp%UVe9?VKrJDd3z=YkpL{d-P-0k$Y4BU zdcZ<$+`QiC(dD9N{g+dFqs!wgn`r`3?ze@1lG&G*p_bPVic(IG%f79f*Ah@!PL@FO%L_(A92T z>jh~1Qc7n-`v?j7!VbF{3z=A*C3(~Xooib=Xzcnp;?9Wbp_1scTz|Wh53b6_-#6yj zn`F$I?`|QycT=y9uE__J1J69luecm4x3uRUqS_&#*GtpURqvYWwn7(1duW zCyWh*OesO)yx^}Q>;f%bcds%Ve!d|-1e9~5Be)l|{>%qty{SkCLek<u=a`PPRBvGrEk=TenYQSRsswB-RAo8cXH&ARre#ODr6(JGMNm zC~y$BHu@wbpP17{5otx-qD~>NH>sGWJN@AZbVw}GbeR>X(t8n6kD5~k9_}OQ7fmdN ztk+yT>M~p+)8$RUc}S@HE>@>~FeblUHZodq@w(LN&->N(t1yW=!d^A)xojVEN+5XWqImtnzA#64v!rjrVc)Piqj}t%< zkhQJ!?ENi;mU$mNYt#bUXg4A{Ayps0VahKj-)(i@*8zeCsg6O$GHCzyXWWe zTI+q8)l981?j@Vi|7gDU=2J1h|C>4a-#@hf#{SouJPNarr5ld40!4H|?Z}!5<u#KA?>=ce<+fHdpUBXl9LYLBEiZ2M5EXY!RgMs{IURwaS;f!{ZJ z#Be^!BesDOjl^*ieYnm#Q4%_BcJ45@pEXi>=}mTF{64pKh{pc-Onm~E8Bsez4;CMcezngPL!r?^3%4p>tQ4stI-!EIA3XEbxDL<>KMiN3C z#uYfza~(+EC*sPv)XRe0EF?}cvYT}c1#Euhrr8532{eGrm_)KZK(i3zU;W)7vvW5# z{`6+v?h80~x0(srQEvf*TLRoH?eD5~h4L{}4p_B*^+**o^KgqZGN{5CS@+cA)RSfX zt&`!(s_W+7ffMygdswg>C86jCxi|ph%b|v2jq<)%KCQs1vjKI}m=h$f7OK`_IO6Vh z>}{B9;qJ;trOl6B6^v;M_zJyu*PLx3)g$bPh7FJ_hOo0^@`sBF6*7 z{F)9gRX5V+952ObNtlX+csy3U8*KW8m*&;QmZ*dAkC0!ese`9P3!q>>q@eCmvXtF8 zVWDP(XGX?vuooO17>H) zev&^Qp#JA?I8RJ3zIdz&!$+k2Pkobn6_Qe zPO^&27?t+t1Q{FCx%}8H5Eg{G;vbmFgmY>h3>A1wGbnrwlBH}yn z#FgT;+oZOfF7`Udtjc{(^PC;VR6&C`j-f$3mqYswo|%bfq&9j_cR+Hy{;oF+XzcdC z6<-~2%qYrrI9pA3|FQX3tUqCqZ8f~ZaHvV|S^$HQ^73FeXbSVEPUj#obwV2{6X^Ik8NH=_Yn0fKjlX>x19HJzk{n4QSH=9-(NJEq?}G~4ebnp!>c+F2%n zCz;K%l4S1Q>S8GZSF8$^RSz(=yh$3U95LSu)vzT^9_F`sa*OARMjw<5DQ7JHw9x>Y ze)QU9(ws$mcFO=Ed-Q|&R$ONwnKu_!&|m){Qfr_uNM3eDa8A!M)ZdREVT2g6 zlpsnFINK~~C}~JLMKL{G2Y*Adk~&)a<}blKUSvrR8r zdX81wTv3xo&Y{(>5hj-kN}tK!Ew@01yqV=IFHigNshYC6I*>%-3k@W;;BVC9eD5_a5eXy}Y8R$lt#)w`o4I%#{Tqf|gVum8Gldz#?$)GI zeRF%Vy``GePLZKS0hYpESz%H4b`;tLPN?3Jxs~%zJCO@t{hnF!5Qzbu-x+xVzJh?+)^CZ^IK~jDQUJ0C))7DfM5Jt-H0pPw|G7~nvZgj|KrS#hq2;9 zFnG~5p}b5-0oeEcM~ z9Tv>ZyUDAuu4}K5pZIHH0lC>952)21bw_y>KABuO69K&z!fS_3+oDYE*Mpzb3@?)~g7`eXJgi520 zGV57#3#&-6`!!LovqFA;KLW_xVuQdb2P{CCVUbI8or5&go_VGthr?+8-G}_6_k$yn zm_0&)Hr_oZ4e-aU0iP!DJ)BwbO3BcXi{6OAvvcB>o}SVYdir*})QeErn8B=;Nl|{D z;0LE8Uo-uyZT6p!$H5}XJ{*!_s{bI%T?Rv_SDZkX;J)Z|*OpcF#5sct56=10+&4#&0^PE~e;@l8GFl$x2S~bqx?0h3tV8!F&@@4YWo$6a4^_4W2K(5s^wj1unK?IQt`BK1)`|{dHS&_(JK`#`e{yvX*F8ZD; zvx|e^hAnT#l>4+~(!!vIM1jQ+9>waEX}QwZ5B7WF?!4=yT^4pHL$@bRPG|>jh@!-^ zHPdnOU^lH@>cN3Cd`wx@XfA(TMgF*9OxX(8$h%;?!wHYy@C%K1;mL9&HOsVyp92SX z_>FgxZ?U#xCpxr!aFFKt&}S5Mdlk?VpEC@b;nN<B!AIU?=P+eUVH`Gbf>uSn@r4Jeo z9z$>-o8<@FoKCHww_#0ZQ*#>Z)$MiO{5}ewO`muSY1N%tPz5a zB{AU{hn=8-)T`C?3B~*z)>nt6x?Ng*j?j9}9>73T0lkn$oyXRsI_zm3*lm~?&B`LW zzDS?zLibA$1tp@7W_=9sknNQP(>WEN_7e@hRCBiQv`#i4@jzf*_uc-B`&%efFr-x)n+G}2CO43ouW zR;f+|?_gY2XkQWz2QqF~msi9cJ$Al4DWhvu=|Y|lW|sU7V*x6^v^7=`9ky48iFuV??l zxha2)2lN}UQnN@=!M`0nS1E!K*+4!W?iLo(%;i0CEjr=J#t%)9p0z1%4{llRKu5qg zkliXEBe*4!dJK5jw@=>#f$vmLV24rl_Y_!=Qdu6~egOo5Z&Xm`Q(%EhgaITy4cULJ z=?1XpP_4??U(@szD;nvGGYRuFI6}`ri2{OJ=&2Z;(rM20C)2t$*LdbMr4}asS`&c8 zFk`Tjf&(tSK2z1vk9#%VTYPW9zI|vTCgF4msB&(`a6)N`FtgG*iKhuF#E0k~18)-e zVaZA-Lx4lGRN`|bsaJq-ttyjGNFuT6P1r}+Q9I&SG(F*kP=JWqzU)I!$FnUy=c0WbQIP2}M=`CwMF-f3dg) zu}f>c$EtVf;cQI3z04-y3~C0B5gWIU^JRTa%p*f$f0|r zCdO-1yV;kSOV-9K#BSU>KcKN?TFzqZa1H{w6r?Y)9jFz8o$M@Cem7Ph;yS zhtHSzrlaDtg_?pMb2L$Yg7gRi;a+QabYR6DWzs@qo$(u!u-=46w*uCb#pp!lI?-F1 zRdm~xqbV31>8d@h*}A(?X1%6GBx@$Amj*UV%eBpSOUQfU=MsHmG*lZa^0Sb~O` z9p@4x7QM^7T>N!i_WSQVizQ;u-z%OG{PRlKFG91^9It*M$#glb_s~z(}`3#*&3r^vgc58gI^n&T6rGpYgz`%#!KXbN7R~ zdR)1LXt$t49R;{ZU?rsf`Fo&T23wI>P^fbHcZ1&lxa}jU^QBHk&@!J0;};c@4zbO) z0=C@G;srr@EW~ppnRT!P0n|Bv&cTwlN~<5Xd0cMR&g-J)?{g4yyq)@L7o3p59le>E z2dSE9gGBgA?8xII+mRqLgB5OXyW`sv&&XETL}LA)_fUq}I*|UJg~WDf_6!ldu(qS^ zgfD3I`L$=oJ^RV(avd|DgtkF=i2<)_B!+HfdYamKR@y`D40K0txj0=@PJn4UsK#xkM>r$7(M zF8Ey(>qjq6ZpW2$W`Vl!o)9Uv{T2)p(vgXCgGb2ivWflK@K))@@zs98S53OH|7gZM zsoa(GAv)huQb7X7rNr~A51V+%YSjtH;oF6ex=%ICEA9j!>n(>m+`$)OR^2%4ZKx?a4%s6!Hh2D(6{f zJ_j2uPvGbx+%OdwH#c@bwk{QKX#bdY_tf7Qlw-BviJZ>w?MA$9pWn?yE+cYaSS-~% z^IpFXpZoWRXNK3nErMc0wy!aCXw82#+Qy_(ayhVIt9VV8q!ds4>|9%7^ax)BNaR&g z6GzFU+ozfMZs=uTn}?6wKqgI1fN~I5!l-30E@ z#l&f>QJGU|Ao$z+m?W#Kfp?|!SK4oTM?N0=FL?vc`pK~asiX~UukF(8u(Ro#mF(ad6?0VJylTd)F!5P|j zj)DFj=W%yr3}vs``c4lp$xdwumOIE(4WinnHEA;nYOf)`j_xQsPM|lD8r?$b`lqQB z^wO|;%%SgLBx|`wMVpLF9DItr;Zwbj{<cY2QoCO2X?05;gZv{a&LS7Vo{E@nj z>L3^$kCYlUeWQE@a}i}0)jO25Wfr-9K^WGLIYLVF?v)y+%xhQq&fPJNZTJm(G0{~0 zFsBp%FmW?&mlI@;5s+KJ=1^}CcM|qM#ZgS!LWZQf)=*cOBImC3SYnQyTmKiM&ZS26 zMZ0YkLhtcCqINEI7^~C9aJlj~mccyL>7j;`*XTLzQf)~Q@hhhxZB+b#aB=+Kevty1 ze&j-mPlm)8#@R){qBLer*Qa94wbHiAO9MOi9Mt!=XSt#u#Lz7eK@lRFqKW6XjvM|S zY55Qn3OMV<9<7gq`An^<0u8NJFUX{?$~8~Ncc|)34!I&Us3Sag>Io-1b_9ktiSNi3 z1?8kcuBvF^o_BF9CcUhdR{~ONHc}R`%Y*jQle^I$mA!sHDb0jOyqg&eidg;`W1ymC zQy1~$GfnhXWA&Y`OL=z_O;)3JDLB&Px*#porZTuX{w90+SuD0JM?-SE`BTSxds;|K z6CJ^)4PZ%{5IJ$wSoh+sv-ne^@x<;X4f^GH@*UxiS~vH9U;Oqdh4KcUw4F+VP+LC` zeHPI>$xFU#gdf^0)OZ}~TB&cGmN!$ADXWvD5!=A}yBYeuxN_QMw`q^#u5pYrgd6L4 z8~f%jTnN_|Cnh~^WK?tSopN_E7re>(8#ESdpc|F(n(UH2KVz>rmRMo0P`~4DZx0d$(?ll?&UW24b?L*@AFbod!3}DD+66P{o=SQFGgX73oD3bKPFAYj* z4fWQB%C?N{VcY()0_^{fzfi)P6cBxW>9c!b72#f}%Z1-635*%Pw1nQpgH7XISF622 z&HP}uI*a#hv}*z4Z zR$o3`5=!CNVrUn2=jG0x82@d_H!{fnxba4a&(&el9Rx5eXqHok@MPkb7GuiMK!Qqr zl@sxWH`eM~5g!BlR?o^QnU&>aemnD*y?0$qQSN%i4Pp?E1>+PRPQIw(?CFlqumm9<8C1sZnFFWpqp^5#h*5D zImu(&N9B)q3cztM6QZANYA0R77muv)o#8oq5I4?@g z-nG*FTL_~6x1}X}+~n@ntdk$SJkza4Zaa-GIAHrp6r>CHB=u@#GTEOfcBHe+^sf5u z^YUq_47;wa^(J)Yj_1qOfE<92ZHTc&1!Z2OGQiZ^AdC;fD=1G+pfTf{rV_5jg-k-zc9vb*?yqF7L?hG4`Wwm@6M+qpW`OI7r2Bcd7akF`vp7Dj^!8 zN!wCl%TtW3BP^C%W}^}dFz43=Z}MYDd3@0v@qf3~m!R#v+)7Ux3F9aN#3Wv~a#Z=0 zm*m7v82J7Td+}&M(RiiE|64$eX|UtwvG=%H)N!H*C7-S9${n`3ngOTZT@)N}3~OoA zleq{nxC8zwpoyw<;SQKy3eYiBOqz5~h~D_ z(=S;_mKXd-*9M`R;dD_~Pn^jP`l})E6@h^n6LNWMD#{r}T5uw8 zX?LCBwJim1pQj>uhHiPQm=dO)`+0DGym$Ri;(%%`!7X%^SzAB{JiG)p4_>D)5u7|e zD!xgjmm=v9vll42p(%? z6A$>LXF}^x+_y+)dn{aMj^eE}&q*CioTmkFs301+D&c{hCBZH7L9b8Mr&RkmZB)*&o{r0`T&sprOEEZ&Ma6q4%&`l(#GkqIvmIS zsry!KZ=n3~$8-G&_sulpeoUDc;AYifpkl!S#HTbTP}3n zIKb{|CV$pbg=XAh{)gt5(sMo22tJ*g5lG{&E4@CpsEM{$OtjU+QEh5@t{L?X_{bG* zNOFgp0_FnsW)6WiiBSEpr5K7BI^m15t-?9pyP<>|sE(!-ybr2E=N4S7gqTiShz%I{ zCVPb&vXN%9!nRWp!a}mKWY0AZDPbc^pRCBU2b>}3g05OGMHHy{^QC}AC@By}ZmY%H zsRaKeNSg!C$e%eznyF{3QSi=Q9`wiT&Bcb?C&XHkHDWR)BpXepjhXlZW*k{@g4x!l zIwYL!NITp5EW2Xs)tt`g=>D+t(6WbhuKNAW?kbvlDGUU7=YGY|&VYzlik*?6Q?jq&ghOupL5@PZx4RiSo<$T}m%F_}$h&`X zbed^THXZ@mj-g9oK&|{y-wqt2n zz9gr!u6aOwkA1_QOrQP12~!SyBG?zoXeDWq`>na>r-VRpTEUT$N1CN{)CP$zdt?<+ z3Fig`>Fw88o8_vItd*QD#%)>4GTM$(w>wDTLm!M&j%XRsj#RUOO`P4g37D+o>%jz- zodBlaS$eK1$7u6w*jie)x%V<#(5N%IPUv*f60`%t4Obv4{GRkhaMaZ@U2O9n5`Fdb z{aaAOS62b>5eXBlz@rlrB7ZaO7w)ChbbqE&>XOLNat!dl=`SP-eq;Pz-VB6|p0nX8!K~LN=Ld1~bqnvL#YyTH9UDMQJcs2{m?Yit_w#b`CB;68$`{#nbE zTv0jL5Wg0MT*yrcZS4Zf*e4qKP&sQV72~qBp6odVdMxi6Pk($#*AKO&b^|5*%Pf)_ zSIeh77^V-*>qdIRI zGv~b%+Y{M1%lyuB-UTa{y%L4NzFYtY{&w<9+<5ZjY4c?nQNgAn;Ksf$iZrI9 zZ`8BgpxHP5Ek+xTBiWK|3CKSZQ%h}-o8-%hgN2hic5Vz70;#ukR$qdGhm$Ycc0a$mJ6+A2^d+!@QvE>VhQdMp!h-c_jrktO%ovyfc4QY|`Y6t+dSYEmV# zgWB|?ucbgIHmx*WUvAe$PsBzHl?TLk#HdZN(OQDd{?Q;o`Wmk8mi)1UVSCIQQ#L3D zPM#2D@52AX*Lwyv{e|DYSWysAdJ&@1lqy}MLSKgudB0viZl4d=w9&qpiEL{#A!4*$Djw{WKk}A z18*G>FAm;LUl8~#CpW9*$5|*lSMt>iz9(yW?Lp9x8U)BQ;)Al87>rl+};t)wb#$Cb=IH0W{}sQX2}QFR*&bLD(XDaVQ=F% zt7MrcD`x5nULhPOP&p-SNQYb1;BM##B-_q#!cHxeqT8L>B8~8J30js~S@jWHO&GAN z;R30iLbt$;DPfDUlv^rWV+&X|_~<_dPM9~#M0s|yf?j)C1K6$3t#9yn;EVL|3iO4{SPah8(M zHN!5u{{NOvw$Wc02uhSx`GiW8ar)ZtoLR>m{)!}fSVOxrM*j8pWC{rytqGzaPki9B z;43WwW$@o{i5T3}2N>VAn!4JC_R2!hpI&|AnFrTq^cpUJWVvw2nwF-Iny1IasxU&>r;$nXUkOkr z+%PqM9onScviX=rry2AOTkF-60HQMe+5gAD9cW}&J^o@+guC7ILz3tVi_6gv@FU`9 zT0Yo=h4H=-52Y6;9fu9aKMZPVuu?sXnE#osdlgX$ol%XqiwSeC*gwkQ%owMJoJzw< zJTvYxt;xk$39VpxsMaK}g?&v`TKd+jf(coJc5jbD<>^<>&l)TDJVbTp=p44PCwF1G z6dFkYhwajMqG6BO?7?U(j1i32wf)y?HGLlWttx%2zG`SyL55z+#vI&oq6C||48vdc ziLd*xO*1YcdO$oBfa$wJ$tz~w3>7}K(7wMsyCeDbsf_OVdhkMyka!F7zhb40%R;-# zhLUW;z6}mJMBF$<-)o?jybnyD@LAcQKG`I_+$spmyVNcLWvZsi_(5xVx`!jt)d^wh ze0D@kuaV=p^ulQLtkw#zC%2}0Wy;B44flRegsT?@yRf(pK?=bbUD?7N8{+wPj9FsY zwPM5d`2qr#;ciWhId`p)TauekYqMY}vQ{Pj1ueTqHmr$IR+owM zfaSRERV@z1uX({iH4ME(ZHdYtuVHMskp3=HJMMJ4b(q~~@ZaGH#t&g=OK{Pmeku@Sh%(O4rwC{>*H=5I)*Vf9bDT{c9GXil zprp0|g5wh_N^&Q-W+;JZ((Yduod0>(Y8vWgvKpGdM#Tvl37mr3Orvbu{Q4qttR$$v z;o>RbeT|!wIVzr}fTb@M@p4#jz3l=mv&9{MF5TL?ksvZw_LJACv1#xHJimo;A#6T^ zXie57BD&{{e_UxH*O+Aw#cANvMTg@}nJw6B`Eh%@aU*_7AbA$@&#^Wl@QCr%*>i=n>c0$Lti z(WnT$HAdXG34GM!;F%sv@=En--QCss5CFQ?$H&)>Z(@6otwqG_9IUso!R`}7UfL>a zHQk*3V!j}YWdLiveYAMJBB*enI(@85cgCbvRRgq)FeZJ~6jBr^8gJDrsioUS%*|hD z4gqxE6#ov_vuuL929?c(xCT^@7X{dpdJ(?j^B(?;A2zUMq}}~NuU+y^AT4@gi`HKI z*W_Y-_fn&&H8j)z8MdCR(l3UufM+6b<>v!53)$+a1~MflXa1ikhMV8n{!RX03|lxr zw47e0^Tyy4rrUr>m{-2^RdN`x*98LKH5ll33yT@@+P|O8eyh>~R*f;P7wBi%2w?rb zf-VM8#ETqhiGD$%X@jwDkY!ficagw$-F@mO^_eZ;^YZPvXU48`W)~~y^^2docZxT* zB1ow9yZ)bz+KXMErJj9zY#j7G+4$48z5q){+cR1{U4YWti)MbK;rlanC!{n`+&sqA z!U2doAW39)Gy0TrE@E1wCXpQ{59tN*!#QD=MD8dOb5Gh{V1QMX zuZ#MKVvK0)x1+aRtp*5I^9IoLSo^#JaXW^jMgC~5Hco8K$_P~ShFi>Hbt>xsUg_{z zWeO_2$T7!jGh1WB2YxVsu0nLI!LPx4ZLj^guAOW$DO=DymjCs2jLiKr8jWXFCR-L4 zY{T%O3glHHIkPa+c=sQ}y~>6U&+fiQ^ftV-7BY=F#PtanwZ2$GRF6RjhZgH$egrqz z@Dm_dP6PB4T8HgrrkN_fKX|oZYAdj^+d~v6d>)6j+CT#qg%-3Nst3;KEtc6h=#{!g z(ftwtEZ2I)ZGRco(1m={*C)ZKR%!F5NF}0b14D(b`HrWZ=qjuwQ+YN*JH6jOyAmVi z#;I_i7Lr~H;nRR;xAmtc>K&<~0%I70y^SRu0732jlo)-PKX-lydv!+jkp!b($bY>Z zxZaLJ4ldGvn~Y>-ox-$0(!pQ;n}D6ewb82Jl7l+Rn=ByOQIs%nQrs7t=rC|Vd^^Ci z+0@=Nx0v&JBv|kVrFe>_20K$h>?O1U48%-5Ma?7hlGS!xfmV*e3Y**(YJZZ&Rq{sW zjH9+z*2bV3|2}$J5(gzX5feJv*hX4>Nuc}5xcYFr^joj;#zZ2Xp2$aB=@!}jeB}aC zK%agk{I|h{tRP}99{FBV2AH~;sy{<4%tR_RgIEJOPUNK@j7(avbOk&ekP&%a;xPR3 z_`q1h{Wrn|jZx4eq6r72-UXhnxhIk|ww|V~-}y>7%WDZw>(z{BR*!TjL*0TZ-vtfz zgaDG{oZV3RZ}AXBbJ8^mGdmQ-cJ8^?(tt~254`tNR`s0( zt&a4AthaP7_x+|+f=Ke409%9Jd4>AtA7cOOo#k&frJD7J6-my9!*8Fi z=8sLH8+IZ_azPi>L8sY1za%ptu#ubj5k0Zu)uIXc*3lvPOMWIFqK|a~i7v|lA8RuG zXXs3wK`PX=q=zHRs5XWk=UpSW(BpVR)}U0(O= zOfDL&Xs@g@-t^7A&H2b^-I#ExV5J;cKkkW|QF6cr*Gx6>{Ao?Kw|XTOk;Lt;($XgRW)&W0l0sD1Tk<)BS^ z&PTqsPU#+*8Mz4`G&Nwah$w2(e%=mFE$Up z-Bq8sUZ-Dtc`E9xz5mq@Vk78--@%+9#qzp4#kwh$DG7JV3p$phmq82kP5K#TW@!ck`d!fGNBP|^vZ!zeiaYE=0EntP1x=uD%S5Zge{05W2b}gdBO`r_x^x&#t z3(w-OB+_bLY{mD_*_}N}5lC2selmg2LHXeVFg=o27}yPY>Nz^BTxKb}M`>)JxT~~7 zK7Jm+S6$zri@qVH*wv7KZHMuI3KOG%2NBMN=Gaoye(p|-Aqy;i zdwOIy^U-F4Uhzo1b&){#0!z1H!IpC7LMfJ@uULt$kUQ>~gmy<+62cbiZq zM7z!#k4J~(2c(X_Ge^Uo9^$_7=66=k&BFQ0FO_fd84fflXGLYAx0rJ`tX#I<5s4c< ze4?$@D)+9uFB19q{XZytlfBjbDrT5REr3fp%#^;C@5UUX3c<8#-7cW_Jte!Zn^@d}Xc`y4_&yFk}0M_;s68+h6$25JV2<{R(Zt`gL zr@Dr|D%lz~Ur+^~K>!h4fewJR5!xO3Q50!1DqL^)VDculCvNfaMP*s64xj!xS9d7! z8Hm?S^J-0k5ydq~JW9s&nni3Jv;J)MtGTIKn62ckfrgw@VaZ)LA7w5|k_~IhE?wEdtK4%4V^Kl0>chv(NPq z^envKed(j3;c_+8h*Jiq^~JfUy#{Pz8G0vYc9C=@y9E?SAO;*k#;E(uyOO7pbbYTr zf(`^l+N_?5KZR<9^U(W{)l(eubZ4YUv6&rsBk4A;pDFez{bcCMFtH@e zy+4PxWNkp7uRk!yIA*sYuFwcEG{?n1nSvTwsRfe|91CT7zB%I=PI3qO4^EZbFI z|6}uXJNEqHTxmC6`AN9JHfM7~GK0hh z2r>aB1HDH`g#=0PcuZF(4K=zJ=~*%x3buHxINVwEmO}6!$EvV9edZJ$YRxV70qgal zCwRv@%rmF7QG0H^8wFbj(nN~rf^TV2_~wZOM%;X1MG*tOC;2yB)L{p@3J_Sv-}auH zu1l7?93k`Uwu^LViN@PTl^8>xlGUI`PbN0}SEH%se_(9DK5_(I>k`!_MbViT6kF_Y z`Z2cc^)%+?*&sa!!_F1||6ZWxKrP6{w}D%>Y6ka3n%Z3c5EZ^m6c+U$Lufrb(R4xj z7`htU3uS@-L0s`jBHFs$mszTMJ#gz)NyNpmU>DC&$!1#lxvb<9D8&U|5L1&j(Q?b% z$whSVH1HyRy}hP$cMm$s>3sy3<%#HevFsV_8{RzUfoM6hd|JY9Z02{Ed`C78%%cd! zoat#hPdxkyju>5Q3J5#kbPqaL7&&O!u~+f>&agDJ!JIoSHT7xUR+dwHoO&m6u@_v1 z(4bUCg!9KUGHv)iQJ|)XdCk8e}N@K5mfHET1jXWn%V0a`Dc^U`p5Wei)~>U#Es9Vj*z+Vu`HQ- zqHX;G%^4%GSTv(}`FYp{BKM+5=ol1Gtq~1DQJ-F-nUyk`P2;F1YTrpIw*0pk5q>Dd z&E_r<*rbP{lp5S+jkTU6Yw(GdxWAGjx-8hsbrc5FE_`E4TL zKBje0fL7S61u<}Td43Y|lb`-01UJm}*Uie;V>gd)Ze~Dba%f#HzS?v|OotvCXRb`+S}r+;!#X z!kJb>&nRIolb_#Nb)l9HiP{p-Z!aKNWKDj(FWZ(RKuOtx#>;DHl25Y&(6zO^`qRE$ z%fWGTafXAzNDzG(Sq)C0Ys_lpQt$i`YphLzO1P7ar9DEeEQ8^oV6@)O7TON|SJ2}+ zC3g`&+?{b}X!DM#kzo1OYZ7|f?#O6h#aWBiZeDY{`qkeC+83}Ra%Q-b5pVQUasr5j z@w--Aqoct1rBgzz&bVRoFb5MF2iJy=fT|CBcBY$q64$XDHH}i+qt8U+tDP-o=3c3N z{504MfBpKke^cUU+<`RcJAf&5dqu*;V#jD|4nwnAUeZHX&3EY_eZYsMC-*NZu37x)o1jPJB?^)HUiPBp$>S)SB= z-5MQTQOPqjulIehy%l+)@U*J!T7|yJwNUqC(FvstU<|-DCcQf1wFs@Y{*oURag{Cj zu3V>YAHwTm9-0=bZgj(KY}y78ha|WtGh&2KwB3AnutZd!7e#ER8*z$ymG*sw8 zW7bl9HmG+m@%CE7@QE2f6;$#NE-4Pj&TEn&AIq=4REgSMx07q*efqi4aSOtUPoMZS zUl0Z#2DmFwg1YF*lfX`V`vkV@E`sb|ffrbn5Rdy}$Qk%V-|{qp{2Nw8;=$MDooG{^ zlXQEakqIpEB}I|T2JU8(yt@t-_IiihuWsDfH4-aKJ`SNcunb}^P?;5T0UeP&hVO!U z@^XA_J0+T6EYP6;6PuVdv9~chxRdbnHC>dIE{JYOacJb2HsIq39sbI+Ftx{0G94Px z6~J9j;?0gU>@xE5SSzCo zx@VEBEkP^#b$W|qnLN#i+y%gPXU8fh<3}bj9aIB*Ld>LV5(5$u8nimZ2~dA6jc$aHrAv7nllm?a$tmEm(+dKl*@jDkcMMP{Vg+)fmdSoZ2G;?#AT{524 zDZikK+OG|%VO##?Zb}uTRq%nxQKXoz+hytq%9b8_6kUq`+rKbN@55fm7f!~7-ULxt zs$}<39hIQ&w4xIh&^yrM5etF;Pv4#Y*DpYyz(gyv7O!bUr_P-IJD8=jvv9=;%NleN zeffwAv7f4uy+>eqwasi>P>*w*7JZbIgX=b%(rj3wA$N*>zhD}UeCCF zEQQ;3Nl?PzzlcCg)N>UOTZ>En`uFEEn#sZ03*HHHSrfq4m&%cY2c}@T4;_e8cyvU; zxVo!mlc%BpT6m~lw;}pYT@orKv~TXh521Miu!tp)mekob0YQ>ycda@}&zy2?kgM=lRk(d|U*4qS$ zVj1~}E5F8JSC@6yolC<#9NKGk9&t9+X&1j6E4pm3Q`p(D8 zbb|kT4skAe*7D`$c9VTDd-tZ*tG)E&DYE3aVyomLA#9})w~6HXE0$8m949jvmc9Yn zT0iUo(wZJmwfslb#gO*!vOm4}{!#$71_!aGJCaA?}iqVo;H}QgJz(99WN@FpH4UkTTNNE=^EH zQx*U>oVx9?wX0#a+l$Y_e$=6pM8|xDEV<{hi}GJY|o<^XaLdt-rN1S;4NJUJ_hE1DS7Zy zGCGCWENeDJZgOEE; z^(dfz!1iPj^w)*#MH#A3gI4f#H2}~V`^$G>D<6txxm*{Qcxsa@?CsSYcjC}(YKda2 z%ZFVFAFzNW>*mNy1Xqhv2+m-pgTRY^_e1}|H#GnR^wBnne-^m}*)ZB-Ar0VVqv7l@ zZ(2r+ZaE7Ch{k3vg|3avpUaX|@ZyV_5b?_B8!YUP_}DuTovVMOfP4S=x8lc7TnfqC z5BsF387I+&3iOcqe+A{Ec(*w zwWrQ-ByfKf-Y}zq$v-8*qiilPX|#XHDV4dzp!dUL`5>1iIQ$=j(a&hw1=_cqhCiqS zM4jur{G_dl-^HMymFdJAzDq2diP5Rg1HftE=tS4sFay#n{!1KI>mwUeB_5Yn<$KwO za94(lGl9y7WH`xdYwZp1!N5g==tSwx_f%_iy<|SQrQwa!#g@!w@A#74 z=;IhVlNV{)?-!i6&wZi9L!igMDaq{2jdPNV+LnBp6S~9uxhyDp{J;lLW+OXor?R)r`H4M>@_E* z!A|Y}7!1alD%o{UlaepY0{ROUx?k~3X1Oc627x<5TXSZt;s9-DFo#vYAPlUkFd$W)uG~ST|Z*}-z(2k52 zeI2w}bOh7}=cEH2Xz8BUYdd7gncrcoEm`2ZM`!348y8C$$JFhJht@AYN?mUb%j@xd zpUc*duAwp=`Tz;LiV1yzyF4qqdNiiiyJlU^7d+}d1;2|v8X)Jyt0AYSx<@oRt?zp+ zsY+bz+q(nGL_l4@+oO-E3b&vHy(13#MHvE!kcaDfqP31GMixvz|Hp72IvENK!T_a`SJ=>7Yram@0jeJ{Lq6OBRiR?rdt{cXKf2IL-eO15iGipmO6_?Qy?bE80l}(h zq{1$CArA{I1{?sJ-~hsndg-D-1^juWH|vkHFIMG}s%Fq0?Gv^N2UKtP^*{p)$~w^j zpGK%%TuoA=X>}ydlX1Fh4KQO)_%ty} zmd(TB3h=?J1U0WvaC^dZz~Y;92RBWQ(Kqgrk|!@TpD7h3NMJk8{=C9pXPj7(oy?VE|=g&e@PM$>t5mWXIV&g z!I&?>mqKykqDB?S9lov|R;2V2`==J!I);IQ04*u7shp(iC44Dz8}bE8KfM6KC4`~f zG<*RwO*H8Y*?ICTiBeX3>&>R|{TX)`l|EQAy|`WXBqXgBh}F7V_Ks0r@Q+2?ppL)IcMAlenn;XfaHa%{DrtY**HJ(h_`KC3AglXE{juG7L8Nu+AnlNAFXj%bxFq zSN>yoc9>gYlh<0O%gry5DuL9DN$P!vXg5~3#9@Wp(JXEJ6lJn>KzC|@inDbHyLe#R zxV>JEnu^`@c;;uMfRtwqm~u5zkJi<_nCtugK|R2pGBo3(NaTiV5rz`{w7L#rPIy-R~6ec<%}CC zz>w%6LX~27v7^rA31V->1><7AoV`OHIVOpepL%s^!dFgs68%l$!GXwd{zsl$N^fN) zN^XjNdBIQ3rA229(CXk|SF(>pueT_L??uB5B1;8?>qD)fSl3L85?49bw{ZfYYe&y9 z16OoyQM;-;lv@!1iAvR-&=jIF5m_*lm>!ICevfXQoys(3O~lpHCcs%YwESo2T+7sz z@?P%~O+>pkV0-{`bv1c3nKWy?QN@1UL@C#Q<;CjqH0Rr#1e{4KYC{v$ZuX;dT)t_0 zV)ap8^Trr7h@@03TiTyZG0izfqUf5yFJc}fX z+~-#(?Ma+YkKQaCEPKxD4uBcaj>tF=2iQ4O7BAb$mN0b}p6u;#r)fmSbGvM-%$B`R zJ_K~p!aNn=D8!!c)|o-b7w4{2fESqWIPEO-fcluc!*}h&*6MYvJq$H zmG0NuqQ-f@)`wK~CQvOzpPP5=7iLj!h9`jOeX7q)pr@y0mSvt@a^LEiBNMMTo#!@Z zAAOhlP~b-W#~=zBxQP}Cq8!pEt_RB>xkCj2?=-@^*I#7seYP~Dx#-dkJr4(D&h3vhm8pzGZ1{CbgbNNDhRIJk*P7Bg`=?tfT}$lO zPj3GmwH)18sia#k?kSNWUC3#2?*b#0qq-N(SR-wA;5S+m(mYeLdY=dBEmES`%(3$K zn;pbk?cS^bWa}v0PIpF&3%$)Z>qyYF^fjKJGgW z(lY}yqiDgQ?P{iy-liSUtionNYLTnS13$DXO=Rp=oN6TJcujb0q96^TzoEX z`Xf(p-st;mypd{-7KaMcsecUS)+=fa$MGEP#ebtrjpn1rrtD19pH&XIg6rAZfBj?d zl0;y%42f+8?l^DQxmbe_FcW*nOTdWZ2?GzHde9d@Ms_V(Eq zxHdZ^+`S<7wQt^5fz0GdRA+7B&1=CECwC^cUxXV!Xl6|z9$B{r9%l^rN_Oqt!%WO& zd~%9<8XNB&y}ZzVR2fa5>_@-jz>^RHQsS4a8fBx9?26bA*h^Fs62!uWJkML1x^Djq zde`ineWd61P7PdXV`?PNf@hP;Jm53l>*nlmhehPC-0X_Y4y#FVJh<^+qs@uJ^Ye=EwfR)7OqQ$6NjV0u3nUz@kn4Z zquB&wD}~+t6EOqRdiBvJXKPRIl&$h7Sq!_9Kw5a{L~pc}h~LxEEnJQ4C71#2E7%JF zCgFePuP66n(6MEjojL9?;)B`FCz@jQUg;Vw`4jdz{tHi@fM3d-Vy{~L+gC&=JPWGY0PK z^P`d&G*-I|>F5?$}5wXd}R3RefDVrN%qnft%l z7G0w3q78kmf@Eb0_Nmr)P@Xxa@z?yl{uZ(QzHVmA><#4tUNnSrLd+?kA#xXl;LjoB zs8`%WT>{*H*ravKY8_$G-UCzKdf>^4GAh z?(2I?Gw-)K9dY-?H%HN@(M~&IU?H@tmk`X0l6ay*HAu$EgoWTQg0@~CwR^^OB^wCs zKWMY<63#63S@K7X-MN3Wqcpd?Ms;&vw;a(fudY!-6{if7_7+gF<;I&`7+9)~rGu}; zkcU&I^CvY}Z$NrP7ThxkHT^5+^}7&%6mv8tu!owqWGMc_&VJQjA({lnJab0k=xOZN zZ&>f2ODkN!w+^!+sZu5fx@nn+hVgx{C?J;3sSi*Fo+di)^9H-+jrZopa!6^G(5W-i z3f0yP!DPEOP3mnh_0wN zu9vKCY)-MczrJIh(7z}&qx_#9n<73dKkJI+*cwlbHuS4hc~0~}qy*lvF+1O^cOVB$ zjRK8Yp16}W!#k$%kZv^Fj3&)o!^a;YoEqhrcD#~D$q__%V`r?};p~HH{SqF{VVUy(FV3i>;<%!QM}OQ>ajLqw@C%pb3eZP4I0r>Ig!FSEETSv+mtfr;fm}r z%L#LvgrL{dWfYjT7$43O(}uIv0a=Egmi(=sQclAL^P#Iy^-L0 z+4*}~MzG)Avqs~=0y^gpRt047#RdI+$nNQ@<15Hl?Pq1<|~D)fuiRiEm9VbDRR*OR~H zgFchr99r{^5Sj6pn3K$|)-?guL;osZy<0&pu`7iS3UO5uXWxm8$)K*Iqs4^mXBE2- z@0?)oUWR{!B+_TSyYaGdSVpS&g6JL<;U#G(c~3V}u zW=B_wla96=aQclfP}o6VnrZhYiT?z&o^rOS{%7b`Qqofgs2(8y%iWV!t!{neeTiuP z*QvG{y{ThJOwYyQ5wt`7hsMy)G^3#=$vxqNdw`|F%`-c|&|0DEKPNLIMW7A(0)lQ0 zltRcX_x{fS67+BC|Kh;j1M%nVN6?C$uEmuj%NT>_$J-Oq=fMj$V15R==KogmvR1dh zZU;w7k1hxF_G!)^(DZ}#YY*O)V*1=^rbx5)*@xw&)WSJ4bj!z+ zr#@WYT;}sRx;RfSOhJWhE;UA4IStQqPNeAD4616@KDx_si|5%pwR)xlP}mTX_<5al z^tLAUbwLs4A`1CivBPxV){ZJwkecPV*O*cabV~1A)n45l%lC;>3yht_l#m(t# z$Z>VvyON!yr1mzI?~JavdR)JEa(wLuh#l==gmGB({06jT$)xiuhN9op6FV=N7cK{T zaaZ<0*8+>*-?m#*b$-w00))(~<^~em#KaF}5 zxd5QNT~q;*q2zSKg-PY;5ImB5L&2@7Ek``V+gFVzRrf%wad%pEk;rvVKAPdyqUYVc z{qHQf{Le8#bFYbWT5-`3iIW8N_%A5JD$bBrR|ZHvFmWHV@yu}?MoypDS~Q12N@H4h zU1@{q3^7&T-6CpHX+rFasZp_nb2gVd^JlsPF-aZS%VPub=LDjIT}I2Qxit8**Q-jM zhaK`1dsYnY3=V1W{8eFZy{P2(by{cQD0J=b$PF&uM9b>f{cgWhtkQ>9Ck^F~P}+XR z*54jqQjv#sy+?c;b9Aw*y^`<;V%Kw5f6^lL;=&&1RlN2u#>q0Jfn29&0oQpYAlIVZ z(iNNK_J51({%JXS!y+i;m^$^B z_pkDVji=chcqK8hiU6Eb*73>Tj+N z2v>VUdnw0;_IVqj8A8l;%lCK#ZWQ0=%B<~5OVrNazF&)cIjfrwKQO%Op_Xl1SXVWu zKO3IiT3^>12gf>b?R@shemVL$B(9@2?_v)`d%u!@es&O+7M65PE{qqCmWIpFe}Zdd zyJVx%S7TauNSKq(Ce|F;3=hXqTkg6`s<9XHwP&&pc9t8`P2Ky=*7t1uK$6Q=j5o#OJ$y-i(j&Qz?oZV!-^{f})kSd(*Sq|5TMBk|!%n8KJp46Q|Gp1d!5 zOivC`pG$&F@4mRUXA1lIVf!Z9vaM6L-#6hAX^+V_&??GbLrS_eTm4a>D0?%f$ZA7D zuV)f<)H>?IdZTZG75#SC3$cwMSGAmjy0P#@&oafC#_vg+j}3}E;_Y1>SgL6qozaa& zN5S7*1qsoEg+9goyk|D|AhK0mGcG^+wo=Ach2!a~=eZ-6uiB-lo63pSa6}PG@zG{$ z1N^7KkG675ICytUa$KK<9ZDN&EJe@1bPYHdzEN4af5M{7SXWtPtvA4ZLy764XTkE$ zbA^s6pY(w0N>dyc$Q#KVcu3Z!WviQ^pn(w`X!h>1+;YoTgUPzrb;KD60`BQmK(5`( zOnDFGBP!fkC|IDx+fSmZH?y~HY#v>BJ7^wqsf}~;A~f~)dTT$A;5`xT@%(1ro z+nY=Kq9|9$`za_a`cSkfylfLax8#Tqu?)p8mLxS+e-LY3? zulBoBHN<+b~>9$Xl$sHg#J=pD;eJt(*(2+=brK zwv6Yp=X?Il{uGO(E&I(1Z17jTkyLdJRlX%UUaC05SRbNN75kIs@K+hsxjnX1MxS`~ zYNg)tyYP9Hr=|&ym3+oJ?RPvpzq%(KSN8+@FHI6C0d~q4XT)Svo(Ly^5|#1q85-B? z+W3;m%(Q&Z<-I)0K%*`($}@Uf zIKm2kW!C8JR}h!K|4{Kh?DHt>xjtTIynVa9uK&lBtKSbWl>~CI7 znWDrJ+x-T}pzfwzP4?VKResvjy0QIDnKv|L%tX$bT^K-G|9Pm_5p)qd*>YS{0)ZXa zOpiU{#8s|iSrVr#p2+R;A07inOt9>ZrAQ10~d7*(f-837lMFh_gzYw!ywV`v0Ur?x!wdmlNbhA}|xLE+*7 zDyL7FKIXf;*EqxCu(j^Ew-T>(!|X{4DF7fg3dJ&rV~=b6u!7x~(>W+DsAVSN98x7& zZ9?}taK*QY;*l_gathM?9rxzrMCor`o$Tea6^Kc+Bd)PAlYnv6lKO^v1v!eshdq>< z>+^>u(&UmP?RHkwdeg|0LL6;bWZAo%(<#E&8&S*R95r}DJMA_!r$x6TuE7TnfN;;6B!OO#yWY)T}v4f zKsLD_&D2;TyMmD^7ayKzM@X-?OsNMrZ#w$<=-<^dn;NUt@)mK4V!g9z^*P$vAV}Cb z9{Tz9bfJf{j?}XT#)RPWw(>IT0_uro_`tH=uBCJqRukwryg%!WgvA~djjdMMLKAZq zb+^J6deP}e4wKj1zbf4JzS`z45_#prO_1!SalCW+FhGjGLJPu25!D49F^F*F=@wp1 zKA2){7?^{IMA7%gi>uQ{O<12 z(B<8(=89i32<~FO{cvD8c6N+bN4;U+L<~=(WrljF^E=R34FAP9pM&HY%7X;&j<9ES8Eb1@i260;R;7EZ zK~w)4Yt5xKd+l(!<+{U@UX9{S)i~|w;6KjxL;o1uTB_obZ#q9f$U#SjYF%^D@2Gd1 zzNLSD9pjD=Q#((52{oZhgSB)mZ&vnN5d1tLc;}7`miz1X=oT z=kA3=cOrq!Nlj0t3rPn{u+m9%QO@Ih+$C&dUE?f!TUP2@azdVi-bP6!xt_}DqDQ$8 z9LFfi)2Yh(2+-4Jdf$X&svOg>-POX8fyO|(7|`|v21Be*SSY&WP$HDTM=HPxRTs>> zdJ}UZL7h!Cs*p$Cl|DKOU}szZYbO5VYt9KfjGgiVU7rTTXsC5wW@Do$4?BOUQo&pY zxj7kj={M>J9wNy>sQ2KPpi|WQL+wcqYgV(D6W-;ck}%+YL#31}OygpI#wuCIF- zx2RstPfR+DpCAgklVl&ZKtBd&Z}31}-s|aGLMHD2{Eg74vsD^tQNj!AK(A1IK$p>9 zv|W9cFS9{EJ5D)Wm|q)$GReW*Nvy-&R%Tgo1%dFXhqcw|`ky<7c0sotT>S|Y^ZK`b z=c*{~ByQ0f>$JxDu|?K7d(cZ&yJJXpN<5@;2qu0}yqoPpw=kEbUkLBt`2M}@ z^`feme~N$DSK2WaG08#uG!=WFOCHeJ(74QESgfQaW?ScLxP_*U`_W%gwS^m~UM13@ z?b*`&rc6?-%ehMAvhI86&O|HE3WWO~Ln8{g1aI1yV$PkFNp{9IMk`*(sVICim2TaT zc^tl|AxTqCqIJM^cT-eO7Ky{;mJ?m7qIgVL|Hn^HzA}#qS@f<)(<>47wTWOy)JNCb z?NAoi91ywN8~PECh>4p_K`-u$07@c;iOP!fn}*_=^`aI)dQz#wOYj}iTx z^g9>JCB^|3?R+-r+Xl~;N-|a@3$t6=bphf;XWRJq%w zP=A1mEulT=vmtUK6De?6${5ozgltSX@HkPTx{bo6=hv9=fi-_U7ed64Tg#~%+#get z9p7H&JuqfUlEhkFl{!`f)M9P>$OI760!5m*hx1G$Zg!BMy08w6-g4r+^xq4K_s@EJ zI?r~UcZhHKM&#-W|iyhDy}41S^}8$jscZPQk&L$|bWcJ-W;I=*^P|`b8uH zw`qh?LezOEWi%Jnl>90Uk4n&R^k^Q~EpSO|Mn8wFt#)2e=MyJv;#yw^I@pX!?I>mx zN{gT~oF>X>UvKD_XWG!Y=H8$=`Mf{F=W8}3A zf~0WgNhbaYj_d`*3ju+tEQKN!VLHxcLqU98>52*~O@VY>`+FL$X&kpYg>RohDcyUj zf9YK2Y~r^i1TxPx%E8I#TimL6I)iA_>05Ts6SSVsc9@4P8pC?Y-`U2%Kz3KhFc;N{ zVt1lXIn&8glDlDhePlmVUSRzLElWAcAam{HlvgHa{HbgF`+DkvC#vwDX;V)F9oo|i zfNe}1|LKC6a@&5>Kl`ed0o%Os4$vlV84d)!evuV8Q#0Ev%r2UpwHMm3#gl%$${{ zO%ivUxw7~fsXupBpB)NTLTzEfv?xs>n9!)EBGrxpU7V3+hsltT@BK0a4E&y{*Aa)= zz6IDsV6^Y+Ee9+BUh}v6%HGobTBM$B+c?>qMLb+|U1@f`zUvtHCn@*X^QN#Y; zv#X%VCc);P&i1-qk6y6P-7V5)j8`ztbu~Vn%sqE~vGu&m28ha$WZFzoAVHqAga&O{ zKYcIxrSz*#CcEC3U$X&0L!oLOC^VdzeYWBNkSwya+8VwN|C{p(;xYyNS5}mN`V91$0XPM0T30+(gm9V`KTF5NBWy znyPrPP9`kBzxi;<|G-YUX$B;~@2qY^DL03=LWmqV?gC>*)gR}$S@9TF;0iPN0uv;pT-eD!( zx!}ngJZKlm-Bi&g2!I)V_{R{NT0gK0cKY?ELz}`wXVMo!if=6jPsLB-cFNMl&Zy-X zzb=>#cgGu1#1F$2S#&$;Qj^PdJUo*q&lpL>fNYvNgdFjX12N4xLwAKoEY13n3`Rg9 zbAjozpcHsu4@=-M;kty;iG1Mp1No%hGcS(+7hh)`)$||#dlUf?5do0~m68^vg-t|S zItCJx?vjSFDJd;2Ez;crf^P3)X9cG!1BfEt3~WZ*+I5FbKBHwg<}?jPh-n zsHicj`97_Ow{%ZGh6rXt4Mxd&{t*F2P4$4awm8&70&_F$W$wt%{O>75elNGNJ5{WN zi;VNJL8~@S1jdhM?@(i(AAIWKxq8RGj%%27MGg}uYn1u>sC!4iFlBIVOSIK!Bq1n3 zu?RedkJH3a-JQ8=u$(!I3tu6r#zL%720O}ex~SxWAo~$}Pl?O;r;7=Q_EipMr;31!QzBT zU*`lgi`7ISkaHbXx8iQVB&XgD4k|rgGErVUa^ZAM^-S=Q#Ql1Jp!8b}LD*1*1G4pB z#W3e7q2o%Jf^QtNz)4udn_&CHCNyCN#)&;JtTrXSHn^XPotlDrVlI2v7;V1pf7xnozB^W~(huu@}%( zyoc^U%Qr!^)_;~rWCCGb{At{C`q*qZk7P1mY?8f%OVQt=V6k72o^09)uS46nfln@U z>m%14A-HjsM+5Ruao<%8HEzVTlIb2K+;m}lm5-^a?8bIR6P5^bJ#u1$8$*-*#J`J6?}f1E zr2S>Dt2!7cfRDX!@bNYin89mumoUA7XeB=Dd2lqSbn0=eC45k{c8(>q*W2WkFE8zT zZw)^zzc0_WDMFQT%=#^>VI6|z&ab;`X8t-dt|6Q&VZxNl>wwl`fVyi!Kf-KK@m@8EVIHNYZ{xP$)-9E)+0_~v)uV5VS()qAjcx9t84 z7N&Dw+U`t%c2R1{Z%N0UReo{4O#O9xjGT)^y#)ixyUqYR3O|H-py@`l0#NJw-RWMX zB>@rhZAyn16Cd~oV7fq8HiFWOZhPb#-v6^G?p%#$PMEvJPT*U_9rCZuP?5B{Ib6e; zuL&V8yg3<0N6&;G;6FPaKP@xQwtW2}Yh!L0a~y=I5$08y4_ZLs3<={ ziDS_6&wFggM|H8{rZlp5{1llam0mCAFk%A;G^3z`=A}Fp{j} zA5l1hsFkyg0_$qc={>2kV`8$Tvb|)Y7VYu{327X>`H??38gEe6!$6kO7a3x#-Z0y* z2uUaxbahy?orO}l6grFVEo?g9ms(gUUYZ%PFiiJS9158G3xF1#N@H*w>mG(D>suBf zulQlD>#d2HFszg6HI9B*>pP!Z@$+VBxdCMrzIjirSIouxyqqH|K>-q_$ zc#FP>Qqo6Rc1oyi99Bi7Q z%!F%E`VE*8iPSs&9-c<&ejJfvf}_6LO$0GiG4M7H_<|X6RVrE?{9* zMV(tzVr9Ctyahfr8sCFd`^#VtfbT8DdTdbj9D1OyL#@G~>GB>0 z=(tq(f@LFHnnG5@8h7g+nfh@A!8T!E zj=p!{-H6X39fI4_o`-9uoR$uZbZk8L^2onz@ZGGIe6Tl(iKpXhjb0~E5;`GlEICrbDK z5dn%9JD}R|K;rN~k+H!ZMr{Vr726~0TViBgR9)|DHn?z(BdfYx)$cs$gQDRS}MJ%&nSa|q&Ag7x_B`@^QWY3dv9tpa0K&d{mgw))?KxYXpq;OM!spc0l;T3t%x z6^+$x56zY7D|*bU>uA83V!ba+>)_x2Su+Z6xjr9X<)s)iMXjiI`Tphao|Zb9*pcQ@ zS^h(dj3?x=O8(fl8_%w`pX*zcM-}|>G;*q3noGj_{it&#wNKoWD6=OC-P0KKAEf87 zyV!1jjoPNdndOvh+NKyXWry!n9m=8{06bX+N+=Dv{6a5IiOKqRHc6U<2m>EH3!!=m zoYa_`=!h1|P;kp*GUui{d|B5$LjGJ;Df-d|iPo6E`VycvwSgia zPIebi^|T_^a~KWx0sXsga(-(9ceGQ)$>=NDOYSzi>$utd-W)oR0L){q;MuS1#a%7X zlJM{nuzihUsH6+h?$s({O$NC*&XIK+fY5gMO^0>6Bh%D6yyWqO3%$%NM zVr;;AT=%jgaxB86Ahv?ZLcyfsB8S-wb=Y&Ao~_%tCK>FG#DxL>kkK8jNP+?*3-Zo>gG12 zP22K>N*=~KN6d?+y(d2Iqx;Q&f}uNr){}LrK^Mr>P=~QKl`8qd;a+6z6f94mk`g5T zl~k;O`;lSt8V^c!S}w9i(=VsD%(9GOeEsyeSMVVa6ZXo}8DcV5S>ff(1sZMSy_tnc z6L`#fay`rAh)e&2Jw{Ow9`^T8g%Lmvtq;AkZ^VkGj9Azt*i|g4v5owa(h~XW$Tv^P zBc-pgGy>fm%FCYF3I!qz3b0k<=v5ZGYM9-1BcAfxQW+~p=K>if^Y7j(BfUXnVC*UV z7Szf&u5&>mu9d6I*U~U1EN5LgreS52)xza(08{xrMsRtb+IlL|5gy!c;13WBzp#toS{3$Ye3eZV9$e=smp-Y@G(=F;KI5>4=dJE1G& zG3?m*3Oh_2^<10S9(^`lo!kQh&08Vmz{xDoXS3Ld`?eVXS%wp#Qo{i#Ifo|J3mN6v zFfJgtviyB9Q6v$#?h%2joHd|^`A-A-j8Zd+i4DnD94y{0Wu32+^z@GoXL9ZXzpNVI zN9;-X=X6nhPA>|1htcJDRS?2Ix<;0S{xL&f+5W}920a+a$5YR`;N2_sCD??}4Ogwu z1&^a1k?Mul{3#ZOZoL^r#1Bv=U?$&W?U9oTJ+q;yGhw96*>o2r_MS9N<;qy>}M zv91-PCB@?C{s|`D8w4-x1YoGp{{lWtUhi>jXRZ92M;slPta)CQv|$`*Av|<0yK>JU zPgwUfG7_M}|6hy}aQfA7@EkUxnm$rp0T9mX3eYA5!~Z|@Gvoh5KQjifnye=m;oa@` zr$7Bfp856@C-?B<+c0c5n|I?ais@V8V4XEw?ss`r+SJ4;hXTtjOpS&y zRk((?w9!3(D_zoX)T&$4lNkn7{qNVfULb&wjiXN<}S5y;44u>Bc{b z{Jaaj>%ySEWt32a>#zv@JObzc9cP~UOCVgn051(0)>;&ieKynhZ2_w)s{=mxy=MHi zc2Jl3*I4Qs>vHk>Y#LOV@d|7I!tt_Z||(a^5mChLqEaTR-haY z$1CA&?J@7zZUaA$cwJ+E!A6NndM$Fo_ow?4wm5g2LBI8PQHRmlQEq7R_3d2L7@iiV z;hj!(2kUX~&KH51RJN~u3!Sb26-MeI^abI5JJrL{4?kFJPs$PXD96L>WH2Q*yYP=K zmY!z{(7I;5usnp5qK2H9UpcdJ^k3tO)c;d;>^9egE2VZ29tPMwA7IA_aJU>5fz0-D z4q@!41eS+Bxoa==?iDZ%bk|IqIf-hFaCj;60_r|#=v#(in%q{0DxogI zb$qV`q-7Mfn=lmYbQcOCKmDeh^K13h#OD0fWaR5v)ln zI{i~yPSE<@_MRba6`%Y*iI?Blwtp$yDe5)j6fWLOr(|y{@n!KqJ#S zf+I0AAV%o9`-~lF1`-$JP+8h9_`MS1L+?f^<#o&J){MKm?W4H&Z!#xeEqLIZ%v!ShA@l6=7q9AfCx@G|%k@UK9U}t%$!W~;y1_xo ze~i8nrm7A896S#!NuBC=WV=?$4^vl#clk)gvwl2|8q?xZzU>gz4vI2PUbZ67#`?684|t;*x~4bkYY zw~n?$nHVa{<*!SSf4+Wk)5M8_>W~-gqJHd0vwEj@+a#nxB~kuMq(#UGdKYo3f>*9* z+`3yO9J0z~*)N0>wqv)-L4qzSm=Wsg--AtSo4S3ux$?=nnLyUP!Lz>i%-cIWe=M?t z!wPb%_vfZ{=d{Na^?oQ7@;6&P$IdrXpTo331<1n;Umy|bM+I`p$@j`<(ahSZTj0Z- zr82T6t4}Bo8BX%0%Is^IN+2?o!MPO&5p`$OO-`E7q>5E?U)!(XJ*Oopfj(1ICh~}$ zD~4RShR-}5;|k7gn7^!aC>4;$WQ5XP#jgW1Xvpb*RP>IwzB@?03^*pMB>L(woec~H zB3UWM6n21};9m{`d0n9~HfjwKQ9cnF+7|O+xl!pK(JTO9@vekzyEBi2`cjc`7%g_2 zCYHN(B2^>*!ScdB=OI&aO5QEi4LJrfSV(Fy%Mg64%16$>&7b~-Yu*5R6y zrQCqnWEQpDyF44dk;c?zR4D!;L;*(nk`jJv*Iq0(*YCk(>-^UQEta?2J8V~)nw zCi#cwW*2aU@f`(oG+6PiMzk;5lM+&3RgZXag_2S`$yG*%ZkJX1>#iQ)x%c{H=12(&(BE7fcYNJTR*)*Z=oNR}ZKrdE_&P$*E z3AgGQY>wVwDC1`|OjB9%==e6=|1)B}IZWaAqo8kW;bPb1d*bQYb*PNaceAPXULIat z6}e6K+g7z>R>D*KTBZC&-KWl4fZJYcmfFBMXW%oe$!fEhCsb-Ue zXTGX)nk}u9q|IJ*Nr}cak&quh-B~_S;h^INqCj|89=LJtV4~O;ygt?iCe2}4S~c{I z8Oh3nCVF_8|1`W9M0(d%4TF!B9^9-Y!DHlP7Uzth=sD-}B_|JXYPUg{R0)CeJA2)xEgB|MQ zKF|I<7$7YjtdLp?$<8e+{xt#P^vw8cHp}ZGU+qYpOm~JW7z)10`4)_MatCv((MwT(?qTIL%tB# zF4=#7{gRx=y6V*?0BRuy(x!O20_1pb?|Rk{bDmWPJdlPT(~bH0hdgeNPN4&4Fa8k? z^8uXnzW@>9?&?JjN4n{g?Y?d9Pa(x7wqp2I-$_a})$68)KO0sO#63D9JVzfVUHi9; zuup(cO-Fy>;Yva1f#c34dwqK0M`5A-8KY136SuX;-Hm8oJJU$Md(q;vVm3oaU%enZ z$)`Wo>>69ZhFyPa)stI3?H;?XeMhJTTi|j7a6B;1W-|iQl-yPMouW$!5{M)mn!XMS zN6qD)ZPAT-{r@!}|L?2pNl=s_^2T+7;Be7h8I>Z2e?%)ME(nat+)3vv_Ivg!Xu z@|uj}X96wk)hE_2r2^Bn__1Z#GGx`CxV55a0>2#_z}uRQq8m-k#n!lby&T9t!RN=W z$bJL>!-vpJ-%t9wUHTaZW2MNi9*Vp^VE0NGb6NSE#;HJje#Un#&84%7ESjw&m{iF? zB6TeJjHVY~#RwwFlO6{P)ZCRQptnIhNBj`{*^lN?YKi>2TyPX>4alPHZPS$T(>Z-@ zT2X8t@GW8fO#g^9Y7rMq(w<7|lK;JjT-w{UefRjD_y<6KoY_hiF@Ty2r$1d$0~Kmt z?8yeE4s~6S?<|fp?(?10A%o}5eA^~V&6>L@M!iv&2dp8rKR&jUZ)(^wh@;OiW zsxOsp>Cue!#LYi+`~|@@V6{@eIZz5migrF(BA|_!wqRZIwwYGfj%QJrFF;4}1r8kU zx7+PDzWn$V+(2k z8UZjNtlP#2R#;ANql@N+N6L+^#?c~eUm!C1EqIC1W7w?Zvd*>s-LpD0{JRG8oIi)$Mw>kIh zJbdZbC87=ly`iQ;!8Qw155x>hJj(?H_42 z@UXFTASsed{`1ul&=FF;`N1LqPIjfH@w(O;;K}aWa~jAzez};5JFl7vRFelbooHqZ zW6SloqeGb&J~o&HyQ{DQv1X>Fbp2?8syVt2k$HO~t6gHHIN_%N*76;yzkkTt5!nzI zZE%7<_pHt7rrv|F+chMRb7~4GGR_;wF3JOP(S={9nEvZRxU6scI$IWMYC}MpvjR1w zWmNHg>hTlG5f;s@`iw^D2e%pAV*~kCE$HLVbMO!9Fl)`&WYm6lJBg?3-H|-G^_Q|> z=rmWmmetATO-HLAe8U9{J0Aat>KdD?CZY4LJxtbP9ql*!^RXcIo5sL!9^j3>DShaZ zAm&g3Y@bq__|Ep5V09O zbL|R279Dgd5CJ(@{OgA_i>8xIquZ85cUdGQJKv#(G;bRB20ZC5?tOBVID%mJt?TxM zb<^FcE6w9hs5=3_`RyS!-aVRA_w&eZWNpan)-Sw30Kh<4TMWz*JK($`t=fj3^HY%z zg68ewzQ?-jtae*wbpGfQ*<9_a%9fKV$?1w$EZbV@esm;nkSzI<@}N0aUtIX`U7V77 zButnZm+H3B=2s{jdYCpk^7_6Kka0f}jx>1@SCed&mV=2=M|gL!-_6i&Thx!0;7NF3 zH69FJ@FF6r0h6Mv@U#Em*tTtzp;vd1RBJv>w0Fixl4`{gt}~;83xbJTCeRK2UWW$53iQiOn8>^ia)*DV2jTdi!}jMV--&p>if! z;%+l4Q=wV!6qJhK@5`=OvdIc{WO1hR=_hzkB%!clQxx@;PfK4o_cHs%{e1(E>JsE~ zsqu%MMbWZc)f-ECIjZNN!XM2&4P5GsNcsBWoo}K=>PaVb#(R#MW%(N2Q|f%Z7~bFA z!WMkj4WXrN7meYcLVN5x@MY~(JgSg4++t@q?H6NrsTE$t6wHdYL>yN(oen|Zcdw6wt;y}Gjp%f$TmeCmKSFVhwDwDsHpQ^1aha1dyhfe)r zd0nI;m)BLMaacc)+D-coUu!~6d~Vv5hr1)>Evzx@VYc4G%Q52FKu@4P%cN5}S!`r{ zu!%~V$~|pOAXCo|a+LVI#Z>UY9I3u`7(v8VVE~|QsP?oSv`rp_@!NH7874TU`xe-G z7-|7#QMu+BfkL%cLCCg!k&gY9W?wu<=}iNLMm>sX{=~5@jTEk@hRxc}OJT00Z@a{u zgKhKJ5USBwiye=Ldin<+R4RY3(@JIWe0YpJRF!)3rPf*2pa^=;r1nx*fub}sOu$2P zAz#?07eNkHE&T~|D~m1o`Uzh$Yes{X{ZV4>jarmekd}$&l+rV6V%VJHf~ju0ix5iONCr#a$s4Z%oexKynWPgu#;TtihKpZ-(jVH@dwy>^$rLU* zFChsIa(_y3z1)BX>#IVVHFX%vZ!32GBif%)aoUW(^N2Zc=n zrd;rxS&0KCp&jwv`PcJUMu+m8yC7Cgr$;|g@F-FDXuh@_msjkHsu(xP2(2h>tG~1P z;_Xy2FN%OJDI`F-dg38S{LiA2%k7Il^kP8F<5~jEiHqjZTn6MKIZNf&aD}%W>yul{ z^)+Kolayl958W8NiRSKBr#gR6P)?AQnrM4nv~T7J$mcc6&=Oq>HgSb!i}UK%zNs`a z$RDB(_q3cZdf^$J^xfNc+AT+ic>^41@~^TDR_l%<1;599pDr&m4*rd#WtRL6Jpx6{qA@pK6yg_|~Vs2~CAftv|<8uUgt&y_)DsxxEUFbxak5<9Ze z@zr&T7%*aWaJ{!1tQaBKb9SJ1fOTzDa`*i0F#YKaNmLY!G|yi^h`|o z!)i18M20@{1V~Bv!6{n$Ai@QvRP>GyF~sm)IJ>>C?Zvcyt-^hnaq&i#Jl}IVx(ekC0=1!p2jLMcAsO0r95Nnb zr)5+q*Isg$n#H|`0{7RBE%*!2;*5POqe=q4{-r)UZ}?Fjy=3MII~ty3SgR+6&|vAQ zdoE7nYy=lO6SZ(PWwj&P-({e(W1uJON2zDI8Pb@1tYdT8j4QrL#gy?dMdUi3A-!)6$DAi|Lp< z1s2mJI#cJy;6>)%=X-8^*FUG!Q%K)_nW(6a1DlkLO}2x_>X>{NGN-2ujsj=pQ^&~Z z8S9VWt`pD)fldE=J9PnYYJ4{^^H`t&gEk_rM&q!2 zt+DMjRIzlB$48!Sn%@W$A9v2!vxpEJdjIFA$c)!^x5FXYu7sLCQvR#7|8@qZ53ZwZ zS{q&(E;~s6##J@(UOUco>>E%A&Taci{(7=-(6z9>ZD=7Oz?E32ysOaT{y=fTf4#j> zM;pG2eOXfYt!9x(`#V{VstUyadzjPX4n`SW^;PYXc}mkr#hIPyseCu2YJY3+h04DE z?8S3T$_vp|YOKYDS!&mcm54(;W#6LPYP46cvx5YIb^I_t!|=rE(DMDQ*w>Yq!}N_3 z@}j}C(h@K4Sbu;386+TZw)`5i^>EH8^WB0nG{S21nXIE`FXDb19rlIEB#dW6P(u*( zkI2xRHUERS#7mY(n596+ksiHd*+TDejX;Vv!NhLRoti|mxwq2JnQsJAY44Y|#FDCu znkmTEOBj^1F^SKhD{-jAUI_R;5*tvm zKq+)|B+p>;wvwL5?VRpd0#VaeWce%-*YoTX{jz$wwz0LH1eYqcWd#x~!E*a&mLZ7$xssuZy*Rbog>@+Mas z_^+ToO}elmv)S!P?{k&x98@C`^b4(NkfAyr^!YH7Ih+%I$Z%fu4Q7O+TeV+c9oY`9 z6e{qsk;rgsvSIBvYnWH!!NhyPH%>BfJr0Z@XH6l`%OBf_p}=-BkL?lKwVgYR|3o`dAw?*IRSNA{iTM zHoiW{m23Lly{Iy&8N_M19HajjzjTxKE|B5NUzR$G z9c~xNjqB=W49D73wm*6EIRfIR#S(f~N%dTl1y79*4{D{i-N<^Ix3JPA&r~)1sSU|< zUCO(5T_C0IDe2z4%}f%}ZC>X3&ZKPas&U1GosvL@%~_8v5YIv`TG=+<$ofh|bOFSc zv)2(C)}57l(!HZZorS|vUnDfGK&0d@^|gm&zw7+Kv6)%-8NMauu4IG22NZ?~EB3;} zwqan~Dn{&7mvnfP%!^yPO7DAR5-$owc6?Pg2rO8>i#`H3=>DYh?4q9A-+i7Ns^=pn zwFEN-*C-2nwD-MV0#>;^FmPXMML^Z>T^U`ZtSvIO3C3S`iEx=(;q~eM{eF}m<2=|F zV|Tf=uDQv7@Z14DGDwwIgU?vU2&D*91@%oVd`~nzIG7kyzQK`O9%!reW1>D|*080OSxxEyB6zYfu~u2UxPJ zS^#vcUs;7Ixvs}cp=kTk!ClaMSco<{F8bV%WYTbVpgAuziiA^mSk2k8>x?A5bwJNJ ztLBsC8sabpb+I8kOkke&%vdGIR(AG4-r1BehUt6n#wQ8QUS@PJnNGj=~V`453MTL9mI-oZb3 zJ%%jmJJem9&0AwUKCD0du&A1&clx6=YS_s+)Xzl)xB86k3~}g)Q^iYNC!e`eu3+;z z=Rn+0T9biWDs~(sci)Q)z{}^E75vQRJjP={;W2>vI9)ydUh?X9<#ld zO1-H1#PXuG{TK8bdO&uhoYwTsqqK2)xzVX5n_mK;(j7`u#>cyjl4UD2pPtO-rw%W? zwW1?ji0y3K2fkC%V8s2cgRSmPmbs6}Z{IQnECBH$AAWG#&We?+v$Me^u@V?K7U6>i z_nQUm&L;HV?6&(dUE6#ud%JmnD(x;jqGB8$=QOolU@AjtO6p%lY$(u{lGdr=)14W;{xB*elU5f9CD0!|AU{w!eX5Cy?ocv8OV`av~h5w z*nB8*uc2h{LsmnrW|^p$&iJ*_gcmEj$@qa6P74zhewLz=DaeV< zd%ex}S&0*uVhdXerCF(rj>_*;7az;W6ZSZEHarIo?8_@-z5X}aPT?etcSGcs8Vg|ZmOw4@2y0nv!kE)} zF==n1%g`o3#kfZbR-ZXHk?m|6o}$wEb@<@03Np{q6m80}OYNBKm`PJqyX~3*Rz;h4 zd*y}oY2+XBiBE0EkC#qq+`;7-DFT&Rlq%PwGsddHwiX?X>`OKXI&K3T0>9%6+UUy` z|M_gb!&`yoZtKYpw_^V7F^d0oFrfR6^eF}_e3QqmFC9xP4=z%vw~1SFd8z@)q9u|* zJ?!Dsuu;-rv!GViX!*Ox(r%)-M8dZDpq-}OK8Fm(hZYVyW3?Dxp7+htK0Lo|!f^8i zb>_tZ{M;vp5yWS=O4j;F#=U|k=Y3^Vi211tNf;G8d3z{K1f9Z0;a@qlc~}B9EbtRQ zQ=kfiGQqgewjESxj&Adew=wyOw{HG5$6ZpG1tP~5iaJ)frtroA`Ep!KX7@stOq2Gv zDnBUbBFnoMXLFtH>vPJy70UJ5Z5dCGYnJd#*hAFmMq7+{BMP%WruO>bIyuB?JZ1E` ztmM89%murOWdGPkt;yg!+&<6Qq-HlMa{BUzaa;#P^n*;N%@B`!{bF^XO=>M>ZgNfl z_6%DB)U45P+Ni!2S{h1mAK$4F({j~wg4f@_qu;L1sz&OX<~l4(&H3s1NW&9+CdSE$u)Fy+|#F@s5l?34MRp=Ylb)ofXWN3@e$HNf+!N9ny>#7KUy;_ zN@ITAe9I%-@r>&H<+Bv`>u~J_I6PIdASUksUPJHcM<3qq>KaDiPg$6IGbL1*zNabp zgvf>EVuAnA*obZW>5+F5&C~Z4(=M0Qjw9=_bbVI(NHtpi#>LEu#*II%TA@n1^OUG+M~OgzaEsYE4oxYY z_dOd?7`!4)e?&!)M(`2gpYN}Zi^}s}_#Esx{(Ww@df%6^ zEs3gGxK*x9)S~zJoe#&YMCcvD${dXmo-tO02M;stXC_`PAtYli2erFjY@Vd8-j6jV zkQ-O+PheYme`*wzjA7J_mEU;RiacffdP3~E_z7C41pOIj9IOFhd(+I&4{V=P;JoTe zGMSbQshbF`&Gfa@64yStZB*a)&%KO#&&(I?M-W^&tUHcX(QuKhKP@UHOEmrMqmJjt zq zZ%3&aC-QV0Gl0J+S5HS<$K42t2X63pO<%`MshaUp)&c}}^xIkL2e!3Mk_LSUZ%34b z+@w`3|9#C30hv zUvDhO{ONDdRv2I71^Y&RTy}3_VIoQg@)s8Ay(NE_Q&9`pTUa-}mp~P*)V+wmI^9Tt z08ax2zZ+y3HnS6nv2mE{dG=rkur0h*|D%1bjRB?~v>->)o0ZooIuSi=na=&b>3DoL zB<~~&8M44t)O&ny$w4|;&e6I;A;o>>p-Vnw34zjYnFX_na!}J4sTVA&unhb*{|g@T zzayKsVLc51^KKzg3Vj%lVzW1oBylZj?pKg)coeVkvyUH0DOK;83OM+2EpDEbqzsxO zKS{C8ymC~!TPhu>$mdJC`$IxTixl$N+}Am;Ika&&`nLS|DRew1`MU#f6j7A)em4Pb z=W0L9xS3cJ5O~QWbIn_kM&YreiG2$Cn#x`))N=P(hG99^WaW3oM86xAH}7l0Dd7@B z>&reHZDpwLPAED4nP)rG-vEK!fQLMz@kXkenJ()2u1?o0{yuqrb*Z z-CyiW(Jyhb;xJ*<^Tdv1?iRRI;>PD%OYkG|Db@?&gF96AS7C=8v=;qFPe2E_@-(Vgqw!aV2 z+xRZ^=xAPtYH_2lJT>v>b@~>puiiTPdEvntdwOfi4rb}PNT?FD_>YKuW|&4%u_yMa z_eN%18dDQTc%*Y(&5U;~C@U=mDW}ZWzEp83^^JbK>3mUPKc#KqB~201)E>-c~wFQUT8aJigy}Y#p7`D_aaEX^T*$tZg?7*w<5Wzy$0hP0;h34nOw-xc9 zzABr6MW9pk2kH(2|A?#*A=>;j%-#N;fGlWASssAD^oY1O*mIokF-<8=CqWpe|KHHz z|Nj~ME%3axc7o5~cz|XgGmH6&kz!|dNcErV z{zt?lJD9IS$##Z>gk8_?LlfF-==*Y_*hsK5NHB@7uvycOalBk> z{`D`45DPFRd-JK%)s@*wyUIXv?1Zs|_)LO8-c4GA)LckA+jqT<=u%sk6`wpb*Y*_* z%}_c~7xGs*5n;F(n>q^z0Bv!3gk|^sd|$)AbK~|l+gr|6nP2(D+ijuYLPh6( zsXf1PTyd1}*I^~>)Ga-h$5s~ieAm;54T#E>IWNBDKKiu5*+QE=W6i1qUf=JO87JjB z&wsLli~yON0Gz=69Xxd#3W%PH3VQpy9Tm6ulIqy+1NF7zGq4Q6pbrEc9b=lXDl#PH z>&~8u*LrkGwPv68FC-e%RxniVNJcBVGhDicA1; z*R3?vn>W82F^C?Ojp(yerTL?+F+9l<;Cbi%321-Hbw&V#b6KOllge6D^D7rPg8MK` zsfx5L@39Nq7#p~-p|kAP8etYq8x34z>(7U@DZ6Pj%&+X0n`?P@Ia z24G;n2e`ZytiR)RP~n|fG%ueDdbx46H7a-7+uW~8O~@nh7FT+yHMb>`Lk*)qpJGa* z*4cY2$p5oUmFY&Dv%XMx{sKR7yT=W|KK7*Yz~hv)er<}JJARcg#U_*3N1&Rj57b3^ zmmrzJq`!e1{GJ0u#Vur4bxUXV?`VdVR|lVdZ4pPI#|3+A`&w?!omL4{8FDMGi#ZJn z8HY*P+RBE^o(QM96H(XesKm5)8GoqrVr$6qhfUOYS`U@%tN;~8P_Zu%x_Jc-2iW*V z_7aUuF^Ou$#;e@|s}@bCcl^wgH%7Niu5TCN0itnG7IvsF`$gka+jCQUGpY%hX4VEu z={`RO>A2*(4ktB~d;AFuR;g+24bzu-|8?mopLJ*-1dZrk)@}%J%pyOmtehNGgMv_b zpD#FbjkgB3(0}|P9W#sSqUFQPEqDIHbj=HQvmduj)kk$B>|J@^WJddC_~(p?<&qt< z<7sqEf$KyD>iQ{ZPVVBeA`#Djep9!)QD*M4bN%h)`ddu^6<|I9UVa2){;%h92EN^T z*+q?t<3M|PJ}UR=(3iwgZe(V>WlidHCuqGbmTfl^46DQCLcj@?XtWbc27#${MMIw95nLHg-(T-Px-`;|V>#nj zz1X#642bA)k1ap^2r4KpitXtN+3t_p2KM`QS57II zh2%5w=S#{QF;?+fb&c;CX4|G%Kl^;oaI6`6`dT`@F=51-SzREMnsi&>50U>IZ6Qn^ z728}A!=s93Ex6tRHwSroGy9_oe*h00`R8lZqZ-?l&$b%ES|_`1`eoer&%B|n7D&=sMzXaj(sDiHr^|yH@yDuc zlyx?le&;$^k6Pr8j+ykct(GA+I<8RQ8vN5={8~t*!2)?djYLwKQ!r>3tTwTzshzI%&`Ch1Ub6ezgKOH-=JO^yS~j zk4YAD|9Ymdy|hH~%FSri75r{gDq9*~-PS_Kq_@#5lD?JUpxXJxs#vs7!Ubf%$u`(y zpfe(J7C5i+ecB%LL|8~X#WDvrm9(NPQ}1IQn^x%+*E3Q;{<6;HoxMY7W8~&TL+kgn zrDgZPcm5Y)?-`b4|GxoSR#uj#;65j{%@Y=4KFwjj)M#MUVP5;bB=~PM`8EU6s%1x)|45j#r*7fwhFS!oQHZ=n=wyLJjBag?tC%)yimDpfg#x{E2mF-5G22 z>@@RBq%Yj0vAMR%a^8&daV^susS~PL*Jw$~koz{y3<>$%1+hqc{0p4pGpyr&34NXK zrcM#@vhUJ@BImmatnNvWYsHwjeOFcZ?D|!g6nW^nvfSj%qjo)S5zQ+bW3%Jh;p(P& zl-_Z7^VaO^6%!?PC>gVn?c7?6Ebot0)|YhHujd=RG3iz!;`X_LrFx&|1C6?K-?+5t zb%}?xgL2KoEk)K@j6(lR<#Lk3R%oH#`)PGM&ktwX9sRc1!dj~zKS zeOKHt{W_G&yJU;HYG=K3Zo2{^CpXx`c6w z;%2p=pYn&zbzU{LIoH>Tu(ZV(?@RZ^-Um6>m-i?~N8hb3;2{R<>q5EKpZN0SqB(en zc;j-N?thoNmCwngulrl@K>jLpGR@|Gz2u)`H&d;=%@@%jNEQEEUw7ZCs)m|x`sOvn zTjY=Byg!^P6RC{M54oVFG-LWuO*B1uxj}w)REafeT0^ZBeQn_uCVHuCVJ~ z5T8WFFb(P%!kwX*;$3-N*wWx~ph)|jk1^<~!9;(l8!IWo9Lu$)8MQ^=QnI3Kq2Z4c zl>yuL8eYLVG6p5;em}g1b!0k0=B{p+Q?)8Q*t=H(Bb zPCsJxT(`;`t0`CON1oQj$}7>yrdru3{uQXl{1v*do1i%!PLnT5UKuKlX6J zXmqvtUdoEZTRynVKb;!#*T_Z>o`2in$j?!psqzbaSzY&@utfbCe<@m{Exn0ri*&HAG|`lM;%-;R>*4YQ?cvc^)kJWSbJ9p%Gk4I0D^fxZ(yUG>!7 z``$g#pp*V%9V}V#(a_gZL^sn(Y|O=JwDghqOzD^Chn5}2m57srV)6IwRROtAmdbd> zl8Z+y{1V)&TvmQgt~)xiY~Zb||5U-*AHhXkrB53WxL()G{jT}f-u4A)^s2eGgSx&8 z%nKH$Y}2mPmE(Oa>p{FDFU=b&iyVW3z_)44q=omZl#t>c-(pJQiJo~?oxMt;(sroY zJ3CW_9a}$pgE&F8OuG!V-IHX=@#o7@qJR2y)NP8bJJfZ&Jy!ya8l!92F8=JPeSdAd z_}99Z3vMdu#k^9Zd)>oXUAdEqrifO8jgk*q*kYPCtn+y~JSElmfv>NpzhHuA$L=LG z(lube>EUhU5G*ht;o$m)!GE{o3OlU^NHyn8*Mi+sq6Fstc8|Fi{1SJlJ6d&~|dUYu0DRow%pTNYVtl^Dz zU2Q%?$t4=bFn9xkyKLo~Qf!=zW1HqOSTr9b{n*5lZ?P{y75JZ>9F^8_SZmRlIQ zEi}%dUFtI|J|owbqwE>Hb1f`uk9nGJeGb#f`si8pd8Ik)S^MqvYA}3*YbW=n`y-2} zSRKEgOFL3>_rFV*!g6@^d=^8;EJ|$DmH2!v5H~cfRwg3gz8gE70elofQMy{# z_rW}n0z}>!+h;iPKAP$Fzw9*tvz94aaX3M-GBm8QVW+P5E}9>z{U0Cb@c&(lgD8?) zlQr}xggv`qm8}a$h~EOB;G{}3p~Mvb-?jL;(%3!iLhC+OuGj8U!ZAJAbu8lo^^P&4 zEhuEJTBosY6c5I^yrN5uwxER5_n>L3b`#rqw6r3P-1d9JOx^i%L!a60*Pz34$;32@ zAi?n`{*q;3Sj)E5>)7IlyO(@H(mI@ZZ#~>zt|}RPC+Hfo&ZcLVz<{KW{yX9@EHD_dy zu!Cf!^#`V52laZZ0N9x&6h6$&H!4ZN0dsMS9K=lsMCCb*q-TMJU7p$vZQd1$IyV-$ zl%}<->hJ@iVCzmbrP$E?sc&4t>~)XCrz-{Qom)PR54W*K*&i8Sz_O zH6L=kVVECRG*jxxD1CClX3P?liDrOvB%{O6*PMD5Ubp)qB->=OeTV;KiNHBq&e#vV0_y?7qVP|M;{!FjoOMJFsrOKn zYAU78pC&c|C#KH0_Mn%c{s1Is!*IzqhJ1CM=NvO0(T+3O;;7rGq|y9mrH*Z5UF*G` z3t^OLDvU64xD?AHg*H4$*jZiGY;U|foziDLvPv&NaM`)AWlc>+vjhT)&I-NAAzkv(T7egTdK zV9A`@hPiTpy0T&Qr@3Yn(Pi;K>`KSd4P1i_#nmHEqTYL0dX|Qd_2zx$t?t$Ftg&dM zpl|sLju>d(df95?5&d8A4TN&tMd>OY1#P}Rx~ss)`0gB67ebr@xfe$@ST9pQEu{7& zP*&7r}Ol@nrbgt9~m8P(V;wYr5-WMD|^+lJ#hpJFL zg4oS=C!RK3Shgr7fw(LEz(w?Y`--rE7GzPY3i$18bdztP0bwEe?nz0Xu8t7%jirOq zUg^%EFGm$lzXLZ;dI$C_5Hdal5ZDZRA_UoNBI+x*Lzs7}n(UyGgMG%h%QsfT(!ybq zkgya_@8ICeug2zrQ~MfZDNWpFv% zhgjQyRFNazH*ww4nk_xM(!1DsE-Iv^OFzcvk625$-U+`ZAjxnccyD(fXcML^r&;l&c*mP zKK)0iPJ9n5`>WBPjC}@x-$;auVR-tv3~a!fJ-3zHNoCl}kxDA`j>=P1h%N{}-Y7wX zDvYA7L7J4SM0PZSgKFV|VTZUvFF0dJ2?4u($b^!$+q!(Oq^SjSczZy?q_^A=Xt+(b zjT86r)VKUJZ8Y>9gk(@liZ_g{wpNgr6opu+wtYU-$R^S=tx;7353< zR3-0I1H9X(Azh$Qu-J&3vD$#QWlivI=()uiJm*(H3G-ev)4$D6%Ns0vx^C z@~=H-N`iO;tB?7*jW4*yB&BpM!nE7kk>4EbQ{&jVI@8y}6RHI)zYKn#fxq6=cTlUf zt)d0S!Zxmg8w!utfcJfmDuyfPiAIi|qwM%pN5ntIxS9fAFROW`6}m4l|VG|@fO7xHcn>Tw$>h8egZy7r9^wotxNjHEFtr^j?! zdk#~!vsqzJ!X0}2V(`&Chbrg1%~MvEj8X;3OKWC1R2aBGH8}_a`O|rf# z+Y-TLWz;~@k^yNjfi%-L4G-n8|5Z}i_qYtW7!2yR8(q#uv<%xXS0#W|%gzLIX3QQ- zull3!uoN0W6BbCi55B^nR{>M2tdOf4mKYOf!7|s^eQAP6UWIRS_|3w0G*vKa=CZ9` z-yUF47A2od|ACNzh0O&W!k^B{`mQ(uSK%i!D>^qz+Uk;o{6(|^_qk4H3Gd(~_81%i z6^6`hFX0nJNxd)FFt5_#+F#Q>d||$FoQa!sl@*->W(sccu--u#R$29l6@MC+?Gx)o zba;v;edloU_IzkhlIStgl(t4#Hl+05Eo1D_(oSUjaFb4dyrCq0bQG|fXz!!`Wt!?H zIuxg{2Rf^3=J9<#Lsc9KOypp+i{mN$GzLBY0MAWxC$Gk!oEw5&aD;PZ<5zWl)Oz`W zWVf|J4cF%vb}lk{`n;kQ15)|YaN#aqCw&Y)Oy+3ma%h3}_l0G;=(g*O^}AH5KbF7;CsV;Bd%^{hk1(_0#WnIDznF5VSEt`LQyGUL zN9KfC)3oQk<(piWz?f^5>$BMfzh3?OeJt~6jUw9L%!kA?m?#!X`m*ibI*O_>$8pX( zySG=FS*LMoD7!v)1Nih2(R^Br$pzzfRV15b$B&8K6DphNs3iCK(h?7p_y)a_ux59o z$LxdsS6t4?vRJ8@+a;5yX!yF^PBGq#oY zBe#||UI0m0OMtcM3&oqNj*zCH-e^ulP4w2kRqn5t4ttvlj)_3RHslM!x(wp&b%HC` z^=HQJ;Y8yLDr0Zz!p(AzC&z#k+Q;0s235KvR^x>%yH$gcCD+WS zVu0$U-#e2L9qH&z`VwGhc}TvtMPENgU&@fDHyfWi;XeROD=Zy+0PO^i zS|Xs@`Z^kc^?ID-j_K%juFBh4Nlx0)^l2^JmfSuzC@_T26Li>^k`O~3@uVKAFW>v& z`aTFZ0o?;{(!)e7P!6)ElbN0jy-02Ojj7a`Aa#bkj>Tu^ogjS~A)fo#4qhA?*H71$ zMpFefI2^J*an0cWGL_=waf`Xaav4TtB=MG_%TFxzh+8_Br|!44evE`N&UG-jb^>g| z4`;Qta>GVtW$W&Fu3%FyNc)fM{31i&^PfwgiZZ5E+1r|!J3np&L8ABfD@Xa>@Zeu| z0lYt(|GSzEXbFg?q%sD6b|WaID5t$7CRi#fp;1Z#)Zn2-=q5lb$kb02jcoQ@eUh0a z^eyBQQhAXi*X{YWdpMK57{&$9e*-)WPY2Z4)>VeDTB6P5&Lv*AJ%9M-Nhj;FAJWEyh=8u35+UkD$Pxad z5%ib%&;Pm6i-6mBOV!j8Cd|A6HNG~T8F;X}0$34M>C?&4 zcZwg!f5r8II3*uZt@4k4F>-rKf2;|0N1OMP28-BlWOJV4qNUKhD--*OJJDPDYH6~0 zJqOsyMiEqP$*#JAsO`Sx?@{ypA<{cdrWaL>jpcTS-aX8BTjk1(wF|hY6~Iy@J9=f6 zz|tWQn0NUiwD@C7!2G=Kd)EZcNh-CK@giL|dT#5Xq{Xa++@cbRv7XHZ-Eiuv2YroQnNLxERW0mQP?l66jMp6ilvtaew*>a-T4 z2c3TqEQDcqmE3b+Z(2A)yOr<(@hygShxl9OXWwmvKDa~ostz?JE7LgHO=BL$YXfM;Zr% zQf?uxLIYCZOzr0y_<}!wNzyxB&Z@f(s%HyMrxnt_GSnek9Ap*n&H1%losl~U?pt?0 zA`+~-KeCK{lU!YZfc8OGC{m0IIi!h4WU+^RR-?YP+r^8h#+0PM@_!+R{e?8xUa)SJ zcBu0)9}^xooPW(to2lj_mgWAI`MJ}pLKV-MMN)&g1Vdaq%R7?NZi?Pte8!?&s4rGi zed0Fo4)P!#cEVFz$-q-&NyEK1O6ch==_O~IAI~?1^jRIXr`5$77f*i~In*SZW**u; zPi+2tt?;Lz%(69>0F7Vxf$bJzUW9DjAfQ13%?tbw+oeAY#`H?Jec}YrppHPCgPx<0 z=_Dh~2N#tsm`ybq-k;1Hbytd=Yk3a0G=9)>4tF0o@e3SoKp5TKf;KGoLZ@sj!sT1H zuS3D~U8z?E);|T)45|N|IdZ&D{o1(hLN%$@m$U-0Gg|n;X++Q#_6H1}LqY4NsFYX_ zOeSfy?8J@aUOetT92vi(gaZQ3d8~Yi^V%HMVX>(7;U@&mgexafp_C-sj;v|*+O8gq zgpsk)J~Rxt?E$)JTXs@&8o~Xd^?m!HR%`35`r^{>^ni|r)vDS5G9k9lWlXX$6FeXU z#{fOg>nPZymnwQ8A7yLx34Mn1#nv6df7La#h$Z93A2GE5cJdehGWFpT+AWkuQ%~#n z_lUkR^r)iTB;R}GPlX4R9Bo2tJ~%R$e+JNI4e1_+CSke{O^e`>df5#0^wAwBa{ZIV z-+eA><>lS)bg*hwyr&tyNO;RU;fdYvHL7AhcFnHBcfn^+9rNPjNH8pjt;ug>ni9|r zbKszsJs!%15};!&n=cvg%?#4JpRIsf2C54>8YsU=ljWQ#x<$qOFf#j!{`#lX z`^|q%b4>sL56rvP3|1*`F;F=&>^oH{uR+z4Ao#6}^o z0T$DGHj;~<=*R@Kj%9g&xGH7UKzEbK=Ou`;z(L_RbMi$OKJn?W?veTCWg=YdW$9A zLoMEXj%xYFyc+W$v*hYfvDA>KYQT z(6@qdt~h=e3Zw`{_buv`cv);$38^yXZUhwE=G0G^<%N1Dq}+aO)3J5yy&Hl~b)wnO zvlMsU1Ik@sjmbWhVNy>9CoDESw6WSV{|u5Ot~;b&m$RUC-*UQRbozE%p@(N3^^{(z z%fcxj>R5P2p|~u-RQgL2^Q)9~wSLlqjJflPW8np7}DEh6?qwyYlfA~fLr;5;eqsVa8zwC>RM@s;HHH&Q$B_rk(MXBqWLK%wVE zpVP{*H_ZQw^Crs2oB!3Z@cwU@z6VMoTlAmi8)GH{r)>;Q$A=z8L^HlLvM%8xf`BpT z-oxD~@$fs1TpF{|f~Q|c)7?vkCeL1uf{br7?xY-)O0H3r?R8On8{?QOw5x!Cay>n@ z-P?|F_1EU>Ix;8{{!af!_CMZkdhQD%1$c4NmxP9u#lK84s7t;!cA#m|_GwJpRLOqH z!_^MCTS=lFVl_3vF5yh{s z17+V-iP6=UU&Qkza6W0?Q&;N>cG~g7ww)C zvk4-GY)`};TA*wURHAiMm+p(n*Pz2v79}#z<|(dz#yPT2_2N~yubX8z zDeS`~q%XZ_QI-~M&k#QWrFb57&^Zo+=b))VhSTTprEe$LpSVF zU!6m3lH^;o!2vxkQ|XeL6Cusjt0NBy^bWMjC}m{q%oMeqgbhpSe}7b5`Qg%8mpflS zegx+pU^fhK7o9deFG^ekoZzR(d`69`%fD}%j+U~?2NIi~zl*GO@X$wPGgMkpu9^#* z*im{eFm%r5uiGYL!n!mOomAJS(kKUbq`$3aO`?>Z_tnC7IPBXflR0&&6M3Pfk^sKZ z`Y>3fdk-8Thp5%5n!<3RTBVVYxpmd*3X*u&bY6|)I;8p!%Grx*dlxx$ksAW6`_PA0 z-%+j4n!y_XyB!-X2Z_Xo^Z{5l;w->7LRTX{nU~k7 znvJ~1DeMI}n%bv0AIzK_3!|5Iro}rKm?3tc599M!>tJ}^fR$GFEo|m-+-dq6ug6@f zO>azg+F=QV4fw1S?o=&YyjMhyAZk@X(6UQZ!z{RX8r;QGeBeFEyQh*) z{XD@b?oeW|%5s`6$^#QJ$a>*MPgSclKCTYJZBCGa4`V65zC^=th+x$++5a72NPR!J z&APqaiG5O6wVX;DqRFxDG@*6qPWpHsxNs=vVgCY}L zvG0e_1ONliXjK-^;ma|sk6xkl&5(y}62jb)^CnNcQoMlxPjr z3pu>Ms$yEGtK_P*U0OX_2V9<1{X{b#&5~qV5Pr~56d3-_WAA6u6SU_Y`JdTt4b~~{ zRVVFKRob&5q!bdLEkwyzxS8kTB(kmv#0lT=N$w6u3xO zPQm-Q#P#!RPMQ@-7YS!FTRIF+`OV1 zGF!hpCA0xu+CMRmhIkBE6AC&P1QsafEdv4E)}Ko+YP*)WuXHRZ|2*ZDdoy4FIro7; z6J`c!WvQ!r6+F^}&Ff){)YDd!U`9z^<)8jCG4Epzk@Pf#5UIgBsjK-sCI1`cuy^Iw zdr_rXf9{rGbm>EfRLKhIA`Xafc(IL^N?_SDE99XszGlIMDaA&z%yw)wKI;7sBccKtkD) zpG#bZV+&-T0RCV`M@obLsR)==((x6^+@t z$u}=OzUe&WJYjtztYsM1X^f@zD4(l80!PgsA8T5~rZco$K)#A~hE}BWEQa+_8D7T) zkYua63Qxpx-cOBls^*9I3wgV}%A4q}3eZs+C;>-$9%s_E)D2+<3sJl~{gK?mG;?o% zn5QRP{bN_TjyLRl`m3v7$yYvRavxyRfe9ZQ`kxSO5mS@RN~u_c#7)fKu4`_*s{>d2 znUNQFsi6N|L7I5YoAWP`YoeJSwGSLkwIW6fO?*aH40cL4k6lall)X21rlE%~fJ(v# z#1dIzK^G+YZh-jWL21S-U#_v&5h}wf=cHoaQtdVCCH?z|Y zzCaJ7!Ga3|tn{9IC7R3hnUbOvdv=3CSNT8deiCK(lJnnt zy*<)guz&6-%DaJAjW<5|yn1HP#G;W-ueO!C)L}Zso-Dh>(m}tXYEBN4>W&4EF zy6#f6@JQeuap8)S;a&S}`X_xSt^f=rs{H&0GzbWMC1AoVsdN59 zuwKbOPwY%*L?h>6W>FkTeSQMTeai|MR8XANebbB2bjJj6U%L#<7jjMxs2T|4I!X^o z4d7L;VVB~C9(AaC=>(L;icj0$;_H=tIaqAg)Ykit2l2&X5)>VLe|SKUNBbm8dcj1w zv!$n4Pl_q7@;2ORHRr5XsdxMVJtDc65`ei8Lz!{`IUcRP8^&FNz?-hNFl6ZENxGEW zC2^8+=sxb!+Jt$<;}WIL!8MTF^gptO8<3@;j?qZK%%mJ$*&>84>C`&!BEi zi?WEOxOtqelQS498w#nCxSp~xlcY(LBmW$?G0Dl`gV_#x5@;Y(iS@o#&TNk_J ze^_emE5~cYsC7YCA1!JB*vKa#pZP@-*dB*@zBkNAiIC-iGnfQk0bNFa{I70aifs5E z^%^8diD*5^AB_9{@Z`0NuZz?pbr+?5Ii0c*7yX|due}G5uWL4ksP+IpuQ130_CpJm z=ko8@4B3%6*CtexDX(jGJLau=_tfFH@Qbf6t}YLRz%QG$(;w*OE6%|8MT%Ue0gPwT zwNO>Cl}hDDXu!iK-u$V@Mf$SFK{}=@y+ab3`>wd+3x8aIiGD~Nwr?|venlEfX1KSVQx|wa+B&P9XZS^CA)ieek!dwM;k0P1C zWJ3>;GL54zhnG^;c8p?;Z9Ar28aNEnUTRri0(-oj*q4dB?i6U?pUsl*?df2u`pGdF zd+pl3*-gWPcd2BoB>l_Hw>0(PSANqY8{9t|f-&=`uwbx|n&U5|^Wp$~lS}hAqIl`f z`Yd4pVM;|&FrD)p6cd8=&RG~wkjC6##cwss{$D-UonOCHzG1e07WJ>?nAOJ?-RD_Z z=+(^hD=DgS>GgFTFvuyKJ3gFowvoJ&M0Rv{dN#79dC>LAR%h;a%9RKUkzyc{&LYtX|>a|<6$zp z^LSj%Li$ zhA+k$5M&QXh{i#HbI~;6g3h*5KJgYmf6{+{;k@Kw`LWPJ@)2ToA`QwB9cDRdsxjFk z73jinDtMT}HykH!IRD8Sx4_VLC!vY5opgc28gfJ{K6*N7erDbCh5jpnSGkcA3#Vd! zDF$BNmg>ei>MlHx|?@3SrpZqkcGGjsBc+`Xe4k-?$2ZP^xeZ$swPTt){x z@8%R8eJa^C_{)@#b*DN^_e9pW>o1dX!Agh()f1sZR*nFS+av9ei&cTe2LOC+TN$=? zYS(eAebNejgd#vH^A;IHu_h``?=fn2YQD*6Uam zHLFoAU}B(;z6XE7$wM3$;^!qO15~JuYkDVr_|HUjYLSEEYxu46ub4WXqWtfJ|9PU#G+_T_cHcQJ_fEmz3Mq%=vz?=le#`Z(IF(Q2LW4ooku? z0#hv14)ZU_DGW!W5eY=l4%`3Bbb5W@>w5Z@z+YK|ON10#4NUMjRfRYs`>jq#(oIyMXx|wA}cv7WqXLh8~ z32JjQygkMO^b{-V+Kjx~PVes}k>=GK@gj=({5xslxw~Lx^?*Rr*l(p~<3;@&G`U?^ z(6tX_q5a2;!CcrbJVnX~MS)2$j73$ILM1fzR+wo;d)xB3%9vfcVJ+e2_D@>J7n}sd z_HiZk}@qd|g z9F8Dvai|2vQ?yS*|L^OBK;ipMhNh#4ETPA#a=AZ6#n1hdn+!FHW&ogV5i{a)1=(hG zCp}n^89#ca3^0w{aiW?y%59Cn$D1x)gWLX3(M6mq)EmmuSoBT092z>xR`q%B(h|BC zm+Ra`{za4d8uuyBEvwH|EJ3?q*)~q`%{>zr)AAy8Z;FbwXtsilpNh3Q{P16jra!r8 zu{!5p=Y-<)!z9I^@XVR&nlxdrw||+cFMyH*Q#Wy>2BJ&>Srh2zjlZYW{(N}Zmm%!J;-LWS#m>gG8hpJ`RgD3ta6AdzcR4mrU0G^@_Lqr(<2>5(C*gphj}t79 z5G0F7>I*&nkQmVa zWUtuk+l7Xm?K`;SfGYXk_@ZR+8vW;f;fmszSpF2YDch9lfW$XLMjQ2t0yYS~C*UMv zhO^?FZA&-iCRc5i9L1ws>CoxDPXn;Wqp6b$J{+iwukSn_`L{CBftNGz_BkXxKZM)- zZIN!}_t78?+||`R!4TETSLdaJ7%cz14V~F7RK_%PFGF7*fRO@MweUXspd7?@<{2H+Evk-u1YVfGQu|cN+UGMK2ZpMgdp@{*w3v>eE?QX_4T0(63>PiIEU$0~Q|{-X zebTNS@olMsc8NS%SNNT00#;lA_5kV6YxBIJdRBTU<#TlLVD2VDL7=)1oYA6V^Lsv8lhe+KdyO+kkpFFRM8 zM*v>jJj*z5-7NFVz8l>;qFj~tY3_wbTspeN*K4emv5Qk1zzCL|OQ4GqpT61P;h46X zo9SUY7I0>3j}L)uThHkMLpqBaT-~=QAYO0M?rnaf^xcro`ZIhhO_^d657BCV%kG#k z&lLfo$ibY@TLu<%fHQKD4s}X>(Du4O|RCyJNQ@m(;lza>I4E(5UD> z^+z53YTQ8iChK#uZ!YVWzrC_G2@Xhg_)@KhJc^gP^mO=`kV-oMowCr8fjSc~yH>x| zYwe=ifwb-sb$^_IB;2b1LED$o933$s)}|+4TD{)!h*`;)>{nf1VoU?rr^9+6MnP|Z z%@UzP((jiq8aT|zb!+K5r^A%YAg`1#`kECUv(fTMjV5JG_ z!V>G<9A!aE&wdmaai*Q!IK$WJ=Dm{Aa%);be*mZ(DL8_102&XSQzwk7HfC*({Rk21 zh&7!@=&t&ODdwg41c!V`JDSHp+GEN7X7O${#}a(8&);e_H}Zqja8l6y8M4Zr!PQQp z{L@}Z;oTxU*H}JRaL@t?jH2ui)!45gVB-hU!UPX@yWjvbO%*e#u=@uqI17(fw07B3 z`p;*`_f4D8gH1XzSQ>t?(J1E**f9Ckx|HtSiSeJUAADWIec0l--<LDjONS|-s))_bJj(z8 z@z|8B`qkvkLp})-%m*JOQ(Le4A3Zt3-g}-lburSv9seFu+1&}Be$PpvJ8wa?-kmW3g z$SMA3>w%jOHQC~kFS|=L>!zm6lWaU~*ZSuRR%N#uNG8P9PP7o>MkA>p0zCB<==RYo z>dQ}l@Psxw`&-$)2>K8SxM7(Q-qe2(Vxf;ImO&}Pw}uW_L$rSN$R-Nqut=@QKEn6y z*do@NtejpuRpFBm`itz8+dNwwivtRa%AFwsTBOu4@!)`iEUS5k^p*AbxzJY}HlMhs z*~f842sJ_$Ppd885RH#ei^S*u@hh{kzOm}|CN7sutiMb0Z;<~!RveQQuQ~=4O9`%T z)g&wnPH?*m5FFh(D~FOSTUF8-O{h_#ImI5q`cDd-@d1qNV^N-QoC7$7ih2z3CC;WX5XZ@rv@~9)iVy8DeOxiG>+{?1_l|b z*eF^*3*WvFhdKwAurY*_7P^AWqYBE~^)G)SnrR-04&(08%&E5-W6+9-ty4tVSX3E6 z?_qN(3j?qwFg<+6KiyCzVOU##9h)Rj^xH!!`sC@CH?3pYAntU1*g{>miK$NzezS%u zL4yy0RW=r?;9C!hE$0L9CRK^U!(Bfk^j=+mKHHz`x)tZA6=`T}8N*L!^RolL8VESv zmd^_M%T#Z>t|OYu{-sPOl#eG{^5BU7^}3og(lbMk9{*)mBa?@mT1ccuWKON7Qx*<4 zC<<7FE5*c~uyE<|@H%&TtoN5MtKpZ}Lh7)~gS`EsDP%Sfz%0d9?L(e*6Xp==g{9y2 zK-1cX%H*96_6P`T74Fiy2z#V3$56?>Ku-?*_KWE|4l1aoPiG^B;*2R<)Efc$xYyVS zD0AcKjQn3!?A5Lr=MWoF$&Eei-;BF=x#-e*oq|H&j6WeS)W~Wgq4k>-(ql^8?rHd~yI+;1MiP=W;sOS92zZKwZ~*~FdE|B= z1lDuUezc(eu^VXD{mWELojRh95tr2s6PEsH#lv~1)wAwX4O29{=_1T{B}-yE#G0y% zxIkuU1D(I1?oHHb)Fiq;%1HIUlfZtwl2K2GwLyS8>N{Imia+%+!jRnbJAYr}l@Le1 zp>)$9s;v>fSab1wG6Rsr-SP;FW zcrBqSW5WVR8UmgDfOAB5a>vO8n2McH&42F)XoIYTr<1wIslwE9KQHyGhaD7`KCFn3`0DKk`)u@cqn=i+qgu} zocM!^Mqbkv-<*TA%&Gc%3rD6~^#;s|d=tPeK1Nn8WCp~9W8d|KL?0DauI`pY-`~wm z9*wiC-cRZ7GQ*X#Muw>9IiS(B`J+hBMf((Xs|Wkv_`E{SK8 zPL{x!SgPAEx!;)zLBH(P=A(XC@;ho>TbJ6BpyY-oU;HFZe!c=F)Wdga2K-YR7GuUX zT+P8CBSx?7WwJP+et4_O5{7W=6YBh&t;P1{WxVzsj=cpyc!O)8e?gvePUWS5w24Mv8Tg{ZZq+voX_A9U<#)x8vfv@?dV1&hU~ zlft+Tv(AyDW9e(u>cGiO@$qlpI@f|fqbhl5R|osrf>M&n3X9DJs6xY6>PUyIzQB=x zO%g<&pu0IX`~gXeTI7?-W=e%E_o`8xLN((!W9EOA~gC;eFq(Xr{o{c9@h z&zofm-|%XU$+F=jb`c$mybz$)aRQCK7?}Pw&nZ&eCi?s=Y93o=XNNSy_S|n!%}H}o zD*KEI*SFr*9(#FrJ6^~n<<9{$A``|Dw52}r%anewcv#0nZ~V(7hScjo?VzrI!R4?g z{x9Fgkiq))CLlH0A=pBXP*e3OJim^A{br~mpPxE@u!Mh)yhTdEuvOkj3Atw-u&fjN z^xvZ3ee49D0=y`8ze#y83em=Y-b z^rSXTYBah>Se9ewYUelXS}x&qYR7piRKuO|3){{thW!<8yb;a{Ufo_MbmP zrRQ81^}u^WN|&XclU8s9O0n@zL%|PEu#Ae|>Jy7*sqo)@MOHlbYZ_A2eVJhiFX)zD zlYVuI++eF7`7b24rC3weGnLJjj%8UMB2jN0O@>R(j|9JYWFOsGTlUCH88NdS$I6<2 z-K?9p;8r^ISct`{|KjfSSKTt8pa-0KxkHvUiQ1yA$cZmU*~6#97YO%~za!33DlP?K z+TGoq%sAuSW2g31w&T`pw+aDvil#yq@@TXsSresW{`hA&j-*O^3O)$;Q~0`xQXO-( z3j~}xtv48I^sEC`;11$kW76VP{d2hJDNoJkp)G-?jZq&cMO?cL6S47?_K04f?&3hW ze0nw_>7U@p55|p7YPMTh{wZC4S`noR2J0<3qX2e0?4WHK^8?_m)0V@Hrxtbc z(FU@Na#FR(Ua!6Dtqx%;)OqUIUSjv53L=m9#l->stKtLVeJA7b{pUmfFL7+L`HfvMc>T5 zHGoWgt$Zwv&jeHJ(Gg)` zT?u?QiV7B0EdBy^97A`uOdo~s*xsE`wV8g?m-_y}0Z7X1d7_R&+H1SbRk5T*!@{EL z(f=9aPB+I=%-zr6&LU-Jubdrds{Z&aJD-0u0@VA(`qXa#s6VRdV83*}RhnMt5F2#d z2c0bGcNWB+S$usmu?vqKkRU*|c79Q}dFKm$4pP-Gwwm1qzkG8Rr7R47Wlwbq7+0fp zEX=U;ivMurWh9R+x;^)-a#}l1?gDM=0YNm?)wowlhVSk+4D)sm?3V&`-Ikm#=gEalGFCN}^KQxe=ombV*C zUM66)tgX8tU(y*)2MZTmRoOxbbRp$j56vbJGMREdmE5Z)B@9K63{`Z#MSu@>_@UHZ*8qz3#_m(eL zb+S`|#S4pnWPYb@A19u@`S<}(VQD^10aA_BVoWHfuv6V=kD3FF)dF8f`OVz3KkJ_R zl;LW)WDD`nbLFY-3dwiJBrBmGGz~i5=X#vt)#b(VX#AV)T7&z9S0Lgyi01dcw`>Zz z;gptm{(gSS1tZp5Z`fb`a}C_T8UGx!YB}KkyUuaYJ1L#1v3jw^pY6%U8uT%;3ssrC zx``&2&vfzJh9l%kyV8->4SK59if@mHma@nkP1}ki=WdEBt=Fyb15C{0Q+OvwfQ4@lAq_B|6 z@0#oIW-@cnQbPYJZuE_?~H>3spGqW?UE}ts7or;BA!~QOt7zRZ2on zJLSJN`#irO_z&S?`Ceim7Kd^&WZ7VVhLtj8*%3GDNdDP-56k8#II1pdR#`INi=W;8 z)G9L>wh5<2^yUIp!J07&5|(A$vWJj$F8da;XPppY?8L~JDMDonA;c(Kh_UZX*0F@_ z`@ZipmNCrIeO|x&d5-6P{&|k)AIBVqbB<%q@A+LmpV#~S?!Yi2T^XUvS(U(fmv=i$ zrHp8k-}lNhcQC&?_hRs!b{|&f1f0c_D}0VeK#~kf_@(YPc!jlg?;FV)ehp{Y0cM@G zf%z|CV_)rr=)l2CeVkbimpgtYY_pdayF43P=?xtN#0Bwec|kr!Xn&<72Q7AHNiXI4Y^FI0 zBEQR&$}QrStUqr(gVzb8`xUS{q);Ix)#1l($dC4_OP@FLkY8KwqlrC|Oe2TdJ5v&* zTySZ@MiiN)b0C8xZRE{TTIgS7)%C9uuN4jn1c1>38M#5(b3`Ys_5Bi`@j;fFBQmDz zC;iGXdKW|ceQWIz#rYic1>aSf`W>vk{wF}kc)c<$Y-Oz27M%N+&B+u zRX8VCIDt!$5SR1CH3W89-ka2`q5@2cW{)8={;e6NcS~M9mqHwzUjnR_P}bDCVm$51 z;(zQh?EqEa>P-6*s3|+Xd!o-`gI&BibcamD4-87j6D_w9Lv6@?laohNK_L@8pjvd`(|}X7nf()TdsN%>1fbfUT3NK*OT&Gi z7pewdot>Y8-ksnJvF~5yWS4)?nk5U~D{;dv&LO)N$`87{r)!rLDaD=kvSXrqyQ^uw zH3Qr~(w%6$-XxX#4)LLn$6>wKL^V*DJ!RC~{k>Drr;(W9fZ^fUg^0M*6~R^tayfNZ z6{o!nZvW>zbMVda*=^&>cd4I69xn(BDs^lf-Kg^*piAJup7*j41trmRHT@vQ%j$T88=1KcGK{5O4I$?q~U zgPb1}gVk#(UobB*A3#-c=wf2Tf0w?BeJciH3zEBTZBvT*2P~ZQr$)t`dIGQirkZOD zY|cz%8c|GaiFfk{PA`RB93=dkNMrM3@HP2Vyyw9SSj+;Q8d@rrE@;C!1b(dSo;(M0 z*p`9zBLERsBTGo+Y+zxBV(1RBXRaqVzV7RZ%5C5tC-Y%R!rQ;+ZWQFlli!b>EqVF^ z2h=$L5UhwYk2X$Sp4l>5mqE|G>nU7Z%=}BUnPpE#{(@5O;SxEzam|;bsKJmC^+Wi{ zFsycvTzsNPQ8dL%0v9&eVWSGgjt{}rSrpX!zE-2B`TQ%vt?R+x5Xst$UD3d&jDT;z znMz=%kfuuf>P@Zl&v#2Zke;!JLGfbWr@nf&c8MH|LJ04C9w#S@^bFWMJ8~m|+>Ca( z{c?bsxhL}GrYT|?bVUZ*XEuI3bxgXHHIy^YU)4~TEU!M{CockdNOl=RNKk(Rp0^)J zykwPzV6w=HO}9XK%>AwD>7&bh?+D^oKN=l)s#I^_$Zlr89DKfDR@ZC4@-M9RcKU0* z5;i^XZstV?<1zqOAR6E^AyYf8fuF9fRu2aRjoN85yEE(h-2b%qmnQ!mA{pAXa1G9l zucXpzFQYD!wbKKJz3&ARrZLI<=*vHy`4-|7ZlAEG2r4FXp(P87%>*RsXNOZ*6%fEt zR{`?&yb|ZVh-zPWi{M4Ifp2)a)Q*%2%87g3m+l^ZI5SFEZg%RsTys8gmWNtDsr2Zo zaeypmG=lBghs}h9%?LX1GIEaBHJLLo>E$NkE)hi1CM!`&JRFluhQ3KoL%xfzcsbmN z!X*lEd+jyF1feI$_eug~G0(hLvUD}xC;!?wCd z&(DE+IJAS8+fnLCN~u$PVV}y29A45~^o8^hwB@AnnDrh?tx47T-Q$7zI`l?_NY1u5 zEGrY&3;pnDPPM>R*!Ho-2?r}WkZC5G{a4q&=skN548a+sfsp?KeV<0`1Rh1t5l^@& zo^KKK?qCfHHL$SR33hqHrn4_za!*wHaQ~?;xp>nE5IM98B3DLM>VKaoy0v2diam!l5coZ+63LVMNqXIHq(aSLsWf*57PU?-XUnzR2>F& z{oHoRlG#JtPTlDal4<@P<^jOfb0J%mRHVrNj8Txm?YVC&p(<1x?@JrD5@VT9okHSFB!H&xGHSQyCyaY3Vr=g8qmt|8=AVSh zsXm&K??-I9%f(@Yn&#^U{kbm}A@q?+t$p_j!o zZth*yJE2S8aBw*C;Ey+jOw?PFs*KV)$WIVFryt4tlPqIT)VZyN|unP%bRn6!XJ=k8f=uhAZ`#5jS;af$kn9VYx!( zZq=w`s#VjUm1hB4jXZQkiQ=FHtVcJmkboOfLMv;r;>>S>dtupWzO+wF}y)TDT@}--~A_|aeGAdGL zm-+d>hC&ZPgccmC%@`Q)^f;AflEz<}Z)BD60L9RW+jJz+TG!6chZdJvacUX3UGiwfMCDs%bgVR?cJ@%TasB)D31V+t9JQ9f*j>r)g;SnPKl*; zfVE`=o{Wjn78y7*E-D)CjITAdqq85`I}ke#d1?Prj5X>UHE%2Be8cj6;_bG4^lE4)9=a?Mg;~tPR35y6OD{o~W?|uN32&K)wH4nauvlEoWA>NUF&oj)z&ajP)tN>jhz6Up3o2{PhVeNmDLI@hWOtT))hkP z14h*d`47kzRN-)%*Jx$$kGj?P4ag@{IZ3++n0wTaZafB{FKpX4)7ENci$J8+f*lAX zL4x36O5G+8B@q+i^BYuwn;VzLsT(wG2ipa{wW+~Xur(#h!in$2bC)>55ui4+q*2cU$+w{Ga%5_I2K_zf@ z;L^M=Qt`+43`xss3}&n-@bZ%DiVQ=;@%vjds+f?RlY$ zu0R#OG4X)Gd(&+LOD@6AFKaH88_|Mc>9~c-kR@sfuvrHlb}TzppgKvv5uaph;KlRA zqh{yAQ=d87JIMreT&5<3735s>G3abJ6fE-XU24@(Pcb~6hmru7_z9~d7!iAxC|t7X zhi9cFVqwQwS~UZ7>tKa_uoET@L*K-Q)0zNQ#+z_$_Q(_OYYX$C--q{_(q8EDi#Oh? z7tnps{^MTLHmj57P_e1T^2BnGW&Tc4Rd(rU5}9)d_}am_23{*G>>Y~g6gqFV0Y z*E3hVS%}3J_}p|~?P}_uq`QJK`|8QF9YUPOUoFk=lsJ}~yZ1B-i76=ZJJ>ve0eF(J z-oE0ArN;`=Lm!4X?}jKHbv@4>g$ z`QPwID-&({w?u0jAnlnK=k*i);PsyEiYOA%354T1MFIU=p#Arjs&m6lG2G4SSg1{Qu@F$DZB=w z;YjBnlnI^}$qFCA?&6S8%wi^}!=@Pg0abGv24^k48*P9S`&R!Yo4+bL?JX8?96Cnr zNdx(mEg+m&GJpw!ZlG=x{Y_d(N=XWADc!$0t~v3oU(ZoiaVK#o7^d8>b}o=@`5yokra29CAM{Xml=5w8NNRB-fve!2xC7gd<=LwmZ zLh>T`$r6pYjrRDfh(8F6UTBxcV!G7(z zqw4*Zm2tG;&pCw;exr?t&DEsA1hRQ{{FMI+=xzM&-byWAx!}F{5J=M|!RH%)f~nIx z#j8G(CVh3c(kbqvAnJX&TON|1mBJp=HHW$~YA5EoKTKZXwjsA@_xav7=hLgS_?(34 zIXF^4(ci6~c;q}6FMcR^zSoa<3_J=pT$|MK+oIT;NT+8U7{S3E^3K}he#D^)s_;Zf zz?BX0dxjsFF?AzKyWz@DH8S2X!aE>N4ZDkceM|38&DroW^AFK7$kw7f8H zvqUN1kuC=};g4{9Z4GbepE9PnV;LcG2|7IuOQo}bjuzKI8Ds7=`P!Z?EHP) zh;27r#-*e=p=jzAu{7&?iYxW%9LeIDJ;$Ts115JL&r45ghdZQaJz>)Sa>N3Q#v4jm z;@G}sP1vD?j-@GOCG=Xn>-t!~1ew{NF!o#*R~_b5KISP;&U*9M22H$=*(-q-wg4l7 zet6x96Wsi9|99K`vXLU|fDv#pGNn??IYmf?WxMm+TFuoLrpL~oBFWPKvNg$&m=V*~ znv@z$E?IPZZ@pSEIg6&C1pyc&$GcO3co3(9D5@OJbre^2QY-hOVT9f-`=iGmZ|?aODFK;}|z8_XX_67G&;ts(HSo@`O75qBFw60Lu- zjptVRQN4|2#OcYGbq`RV@UEBE;M&$%_h2pd8sjPB`x_Z>V@j^deYhs>IEw>vL#(;E z`=VH##iUB#sAy*uNHU|Lo`LTQ^iP0TerQy$33k-LzB%)dPA{qJ^dH^VQXl zY#b*1S$et_w+JO9F1gm>PBMOa-f7YBFpE>2evGc}{%5Op0Lcv-i~aTy=B(y6li{7v zo42AsGgNb6kYCJ+=8%fED&Hxa*o^zGjVFb_z9W51pxz?nZ_S|9bBVt$- zo2YZG!8@bx6=;t>)9F*`UR8)rHsOh`MwsmLsCf77M-KcAH(yR{&}%V`*X@`YNSGFV z=5nPK%-jHX&r}{=%>ND(*JZrpAvqgk8Q`w5o-B*)4_Zg;zvREms)Gn%4#(I#3K{4jE&3)H}#O5dDYU zuRq?MfD~V+G5&;du;nO{DYAGa5IFU{`lmX-T+EH`w8|M)H3K;_u+&VVO7gl=>CgEt zT*W_Jp{p8=9qqhh{!d3XxRj2BL5*J>o1O&fTIX>k)M^DiFBY(po5efjEmXzL>pRt4 z7JjyE(_#}SILk%VD`_YG7*8a4?}J^>JJ~@o4dV@khR>1TSk|JRNiI2n)kON@RAVeD zGo(0(o7w^=z4dls!fF}sm*PL|MV@C4&)ty4lgG#ToeEz9(Z0OxmSRU5?MOr6$}Q`L z9%^9)Y^zhQ?b(?@PixY3L(W%9f}NlWP#XrcJpyeJ9`Q@`V$N`}5+zc^-3T3U~2H>s3lx zTm8^kiuEZ{`8?uKVsJ=Fd~)t7b7ofOFZFe{zyOo5HG+<;o=v>(DQNS-Z@iT5&loVE zTp)>8I8Imx-!H|qJq*h2cUyiq9JC=+68Ccf{ORo6Y_9-nBIF$Lo^F3}y{Y$(WPGx` z<}lKCM40H@D4^i_F^sz2-%Aq8HIV4Al2UHG%Y(2U!ezOC3(}-?L9Bkw=x#efsn=1R z>6-fy$QF^1v6=fr1JV!$J7lX0*frMPA^3+|YN7Af6#XzckZC6(wG9@tA_$P*x#V~e zZj)F|&)wJFZ~o(YA~6iFE{(zkoFCUk-?a{0sEuv%wQoAN|6yAtyFa;q0i8bR6P)j4 zZ(gKYyXhU(G5l1wD&fJ%NpmiPtG8|VlTbyQ0AbGzzEQ3-)QPwBS9v?3&@Oz3L(qmM z=W(WwkgCffh+w4b&W&V(&Yq=INaUN1-&zvwuW62HS*dp_E04n8+5z3D+EY`uO5dN? zF?n#5YJ2e+0quuA_HMt^P)f%aD_qoHGuSEJP*xo6#eJETqN? zBg*+4UY5J1chR@+I&U%|xR=td0u@5GXvYJ)J88g3K!TC1GX~cV_)&Ap<@4+>P4m&s zF_OPSVH0}QAodLKoVQ%A)-+Y}Qf4N{Z`+2kwL@pavHk|Gi=lq|V?j^uwxLh!w;;Vn zd)(iRfRkM;LUhEnMmCm!d88F`?UOFHwjWXrGjfhdTl8h{(!tYW@uOar?88uV;6_i$A~>=-oMzEG(q;6m+dBxQW z=;CG7Zw9yW-XDc4vkuK7u)h3!Ds>jwiOaCs73Y*p@#K&dF}OX=GZ5U`LEf5dJI!5 z_)>sG*w7YL3CjNwzceB)Vbj+fEOQa$_&y4ka_5cg#0T;NJhq9fM-q3Vf*YIu zJYx88A}{z)-(7~QX@3r8J8gXC{?de+DF-kIf~8bMiC8N=fQj0yQA68j5nm6@Y&IP4c{&Dn z30Ehu`?YiQ2t*pbwmf$-k!_!)S^^Ud2brHzyc%aTeY>leO%@wm8HW<4r&eMd-7aA& zwA%#f9^(eSVorYxgYyua@2ULFMiYP*h7n{u^o;xRe@D9iA3s2!{?g#AuZlTSQmU@G zr1qtNSf@BrNozk3R6!|#El~!l0$?$ztZobCf45$0Q(!8zx!F$sP^!r+}H8 zQHAeOF$Z?Riw^!GYi#e=it8Uxl~KFIl!!eAb&rTAJr>xAVjk=OO$r*07Pysq9o_oe zyOd=lvPOgMKlN`+-vzsQ6Ytkkz9LDfnnqUMi4`;aUJ}a_3~53J zM?bj!E$)iEr^u#;&9)B+r@v!Uk8xY_&9|AhwVQrv{dFj`!SwpAIy2kG8%@mMMXNnX zDTILx4lY8BC|F>?;Q?0 zF|g3-#hz-X9@YSPmErb+cqi=PhZ3?xws%!rH{$H`B9OQN71>lNNN}UxANw}y)KZ_N z9|QWzw#|Z6g{azfLSN-s&GXfst3}y{J^sexzvEE^f!;wGo0K_t^Xnm;;+nVK-h5}H zy5?tO8sAlsUp;s9(8Ftoiug>U4f>)XG$0(YANL~8Te+e%*Gc~8??EG=Jf?;i{!4RV zuVfd&3R?%nVk5@CqaB|aIXB1Yl9bwXA`h0^CjK;F$Si2WepAgCaIEJe^D1)}SXJXq zTS-7MV|59Y&BDcokS7NK1NAErtnm@MeEOj}lur*YgUYy07@C~XR&EscNt)6s;eJkT z_XC4v5U;n=P3QF{4tx706*FfN?LPDjz7E`^v+-uoWGOH8L%yfVgc!a5Cv{-p^>NX^ z&I2UZ>4+~$F@c3o@^18~a{RM0|AkFsC_>8MZhV}S$UVZT9#l(5UkMnA^U1#l$0dmO zCnCt^%b<5uk;A(tjGnStUG?z^{tJ`WbU$RB%jA(NzSUrjLD#V#4J8>DR5 zji_AJTsk{0ru;itI7^IJi#C|yTz{Mw=xR7cuP~BS{V}Y0un$ZW^q@XO0mOgIi9{4a z26qslrrg;FnC~Eb_LAxr8&yoyEvIDSl3?6mzr#_9oU3KuM5a2O+|FUI)iup_N7aTuF(jD|9*+^{SW_&Do@iVVBSr+>azJMW!+4TLTLGA)@ z-IIxvdPo$i^na>zyg_(zC_{AFe$eW(#P7e02iT-n`Ysj8lxjURYJ7%#UCuc`G|7ygb{lXfzAD#__Yv@c+jL!@E*>PYd`NA^p#+I;Iyq5hveF9#ozFMTWoq;E5{_|V6?Y{ z-o&=#WxQHhdF@DvP?*wX33bzoCjSP?Fd&q|aH3+$9B1A11UpywkIdA~-bdLg#CbI_1^Ofa4}o%U`= zf3ip556S5lFBAR-1{ZFKbH#4%l5L7?wHr-!lU?8D9x?obo$HP96Xua4xC1_E(9uy3 z74}ULUy$0kaW`1-di9z2`Bv;NvyMN#MUVgZ!HW)n<#Zs&`c}$a`#@z0J6u5o*=8wx z(VO|DY|uQwI9T^{6Xq+H-`Z-Xj~+I8 zq8xmVBIql0cXA#Tr#QF@yb9q>{y_%g#0!`En0O$YY?V9bwr;E?BiPgkcEyXxt21Pk zWZCjX@D*5e$7}BxnYkKk3M@A*}lrx?dhxy8V1P>5!(D{i-HMlWL zOq_e-1~2?j^YEWAOY|Loy|~~nbyeG#i1yX<*Ie36x&b@>MKhwled1k?ET8E72U*Yh zi#9Ure`#8vQ%i5Oidl4+ACC$P#}<8iO`}LpCVhNdAU)8W zsbr@uz*8FXOjO{Gf?t^4%9OzB^HC9&_Q2Vs@J@s;2RI^U)YLZScp;*8Xx>dBG6i3j zekIUxuH7QCTvQ>VgJJFQq1Iy_Ca*1s#oZg3s`nh<_$t zftbJ<1^oeyv6ZW`rg(Gk8?)>g=4hZgP0lqDM3fWFDB^ru6TMiZ^ z-AdPQs?_;Qvt@Gs_I?DmW&3Q{2tayUU#3ce-+6wOxb(it6onl`R{^%y`7oV^k|P_) zb{BJ|#nB`oPY^%|` z#v~BZT^HSs%g~bZnCY$Zlc@%`X9Hv6I2XjjUD12ta;!4s* zTQw7}HE@))-P{jcbJ<-(ppOFfo4@rA{=>!6I3{2L$JYM8s(- zzKxTQd7oiOzoaFSMEBJ)H}7h5*Ra>_`8_v#E8539T|$I5b$_ldDZj^PJ_dGCTjzC+ z+J{ZfDl%^`eUg%Yst#=79W+W=j_+a04^gKtbJitA7M}M%Pz;njx8%X|Ed{kpMBDR5 z1E3r$S=xKqQ-SWt!6rh*gW0b!Cr!2qDWuF{S#Cn_{`+XeH%MCq&~d_u7jR+c2GAwf zw;lmJ29A=Hl1oXpm%OrdE!U7GtA36ovBb--}FL}*6g@g-sDov>*Eu$l@H|Ad_Nv`J4HJML*v`(fmY?U67wHf z`rfmBw%#3(NDLEI4CY3@4XFG+5#zPz*0m~WTR7$I@H&n5(&3{IOA9VPnEIk+D8509 zt0mYFS#eV921ZMQ@BSG+5$fV1EbEHzCoA(M`rlPO?hLV+>gJ55ZES&B(?442jWDiP zthoHq7L`(U{K5=VU6-+@ldnaAURS5g@CY2_Of;!2cGd>U@@o2WUYNPFj!AeNhmsX{ zoo?mz#d|M-!&~Hu_ki|#YKNlRegKc=_eAHK&+QLjFPOX3Rv(GO+H{YSYlWJYC|}SXn$c~rA{6hQ|24tvJIu5uYpeV9DXfr7BpowK7x2} zNeh`J4)N_`rWlqXd!{QCKKmw0ZqqHMcl#dsZ`=;H1k5AfG zxj@Nmxk;p5Mt^L12;&o)R9ai_MhjF;X z+HLEx`+b4{x8&fAZ!nrxV{jY68o7JS`$`^i$;S80tpzNs#ikvj-6EBvdj^8hnZL`W zJM``xy!hmyRNk|a7i_e51CPaJzLNFOcP+GP$XYr5Le;|P;Lbs~65ZgOf!|fFqsJ;9 zW0}*wD*o$7DC;BdkKk)cj6j8|2Ek5@VwvCyeYfBi;oyH;v`#2SB{>QU&4S7|z}FGCH$hh(Sp_iB zYARR1J3WMa=}Y>+f5G?oDGemgKTCr08F7KEj(@cg+hn=;mqyxnRLhHtb1j0`=xozT zt+*NUejN6-;F`&2p{kPGPsE)+M!1bekL|yj#=QGRMB+dl)GI`{oK6RS=X|@)yqS(h zYbzIvNnP)jT_aO_1Cjt)dP0RAPCE<-FJ~~7L4)K@<$|6*yrMBna+W%edsjeAmfDTstc z&-Dl1nyz|Ku8~Wl`|HI0JpIwuNOKAarD$EX{a|kQXUh>C7I6WG>=?Y(v$z0yxl_Dl zxNOYLZlTNm_{FQ~?qH>O>u-w-SF8b389P)v>S~wRv53SY&Fj(YT<7m^Jz=sV-RBjcF7zOH?BJ|1Gb*VB4Zwi#8F z$cY>2LV$;XSK$UJ-prfJk0PI~!6t65<{KkStIB`or8<~D9*$v6!mRk+{j$uXYxX&F zx^~HN{TnX6-Fl+aPHx3{En0Uul#8XdD%19dnO)ye{K{iL7L;{)0ht>ID0VW?(Z1H- z-Ou0fdSs|PCr&>D5h8`1!`j-Y{q84c86#beFNQOQ$In1wCywaVDTAqdO_8Y0;06qRAh64szqh7T2uy>b0O}&wn^rrSV z$P!67pUG|@{bXd>`!qMYpZY}Pa6lT_@)7Wr86s+iB!ZDpnqwUZd1=#D7lT%Q`oZ5MBp7k%AqjRZi$>?OAlLUAbp<2_vt5T zCi$m2u#sJs6tSlpVY!YLMHz#j|Chv4XAa57SAv%9+>r^ZUq`^{PRIcoq1IFFb zt}P_*q8yAWZjzb)5l*r!E$njE{p)e7*y4eYRO|ZdPpSRV{J6=Cvvw=4Ew$!cCox#D1jdM4u4 zyxvb)_kPx9kg(h^re~wni(foSxDQl00ak%NN5=a5R7Im3m#HkFA|hk73;19lF8P_q zVM{;Tpg}mx&sclm%8_YsbDX}&qpof~+km#W7F)Xx^1Tr5y8idzcL=ldtG6#Exg!G* z=9V_?li;Fgs`axbgCTuP+K_ z7ZF${)YSj4-%pzCns@#>&ij>LsOs_II+LE82H*7yAUz&o?*Q}e&L;YYe6*WFZ5&ZJ zrrvs$Z;{QEbW&8m$}-1Y<);WUluPYjnk?viP}aOSeE~36nm8i*IQgZDo|#FQ^vxBjtFz5Tnr&q(#jLygzj;0PwVsE`qeub!vJ zFZG+7ZxAdkW{^1+QJ%}yGN*Kk`(XET(3l116GSHN``GEdq6yGLgKb0ezGOF(N7 zUpdD;h^lVYYo=cG_Aw^m@?`b}eH%@I?>CLj{wpbwfr?_Q_qY-98IoZV5KB?}MrqE^ z@Ehk(>6S_meCSyM%Z$5|aRlY7jU z+;|WH$Oulh#G(^UYu~9nA`9S|-kpf)wRbc~{mW(+$X3>2+1~Q)8`(`m-`s^}t|E%f9*%MkFQArNQ_RyCX8>i!Cj0beq(ewOj zO4(0oTC=PCeeN$i{_5Gll{`2;PP_5!!oR;WB4tNuv27;RM0e)Y!i6*`W4KYr(kB1}?ays*uN zU{@3y*&0VED2Cllhh{wF*|Uk=sOi0?Jy_E~_nyiIJ2Dz-5!?#0c8JsH{e2zT;1sra zYWv#q*w+aky%?B)Q*19}k84uqO@8k9f!9+_LJmB~r&y`G%MgN+K`bnQTCTy+1e?(& zfyD)mmkk5OKkTd?$)1M}&+4_wtJk*$(9`v&lWz@??Up@hjar5S?DU}eVg}!#Ka9)o zbj{Ubn*tPV(g(P?>TOR9AS;kgbToveNoIMF3l{0=YE{-$8TV^W<)50vH6t-&l~uP- zjpY*{S?CE9p_UlB>^&82i5uLDE!Zv$SutXUP@>E$&bWGV5~nIF?~uFS0xHE2)6qsg23*%ad=21kBnm4lKh9Et5`1) zI?d{vwi=~6ck5-SDgA(t7(9OMoZ%F^h}|<~P$j7mx2*J#9j)D$0-Y~$QR@M=agvOh zf-H%;+`XYBnFr58ZT3JS#;N=iqlqo}gLAEq9ixB({r^*v{eQnpegiz)BVGXP0l^L2 z_5q3{6@y}wg=6k%>hq(n2eil1)N2W>vzRJM#mqlG>4w<@M!2HvRRlj%7e@c!k+Q{U z$LqY`vU_X61^ymN{*VHn70Tdmav#|8C*_uU7k+k%$kZ8gxT~6LS2&oX0R_%ZQ+%yi zf_O-qCs3dMHLY=8TDTPdfo&pHYfernkl6~$T~FZHg3vBA>U70g%H_ouE}4_6QvC@l z9f&*QqQm=-7=03I%(0gu2_=Agl*aQvuQa5j1*e>Q%Qpk7k)P`XJ=(4z<+hP}W8>in z?ITW-QO^(Ayv6qi@*gFbG|J=xplblFZ{Rl*YLeLqingHg)me^$%TGIuXviYO zqwlc6<(SkDOV2!I9!RWI#Pspw?W_#wl50giyZAO{jqT*5?FK-&$^Ils@S8_QG>E}z zruPn!j20_TM`gtPbkt|*o_@Hld%?Nm<-a}C^Y#4*pvlsz4fn-W+ECsr@f2>dC&2m) z#=Jf6{_#qO%lu53DGRzM*7D*5N5FG(p?Aid?lyy`(SY}V1|Dx+@aR2m*?eR6sfFQV#_5mOJz6KXyGHgC&1D2mLt^n%3LnV(-V zmDfM|Gfz!uBgc!nuiOclDwnjbLGZ$@tH&fT?t{E71*}za*9z^bq70F;Q(>s4xTc%! zba?a);)f+3tr>HhnHO@mY_&=b4>et^l9vXf8rI9~L!w>7#{c1&YBBwIe(`W>!$6i> z0POnlW*Q%<`nxsf7rAqfzSju{4~*bug?XYzNA+$-9G#EfzV;NJe(>={ngYtbwXXc* z#_EUn>z{6^=XOR-c2vAJyXn@tk~HY3erw_5Zw5KpJK38gd)gl4gb+%b~y$*DhU@N$Ak zSZyXw|NK;_V&&bW>27lM(Xwkoxa^;hkztnEnW>Mbzkc@eJ$(PH>3Pz`4lY17r+ zt-n$Ugr%WyMvx1dE8wZ#4Z9)4^_SD*1qF7qGvdWXJ0_Fuq4)M2(Omqwp0l?V)z(`| zi6Xehj$3oYI6EVPBVd#!@N(awZj>MIxS;wlQN`(S{MsDt4Q_wIC5w}*BDPdtpvh-2 zintDU9s!~?kp`7@bvVK|e*9#AT8X`s74OBV*{3;D#jiHUcCEels`0697}{LoW!&~U z_!=?raK||PWcLk81Mkk%*ll%3TAfSW^3;R#?do}PM0_xj4<|1cQ+jN zRb7ui;%T(?Ix)%9l0Ty__pOvM+wYKUvSK_(Q&>@8t~=3XuZSS8TmZTV<$T#5CuQ$>=kL z4kcOuxocc|Qh3NjW>FFaRcKYQ>LrB~6keCdeg&V8;p54-Tkeli+2HCUv)(u7W^_TE z{{V<9Z!!>k;!XZoICGYF4odbNKRni+%+U{(-D1sgc1#l;TftO|jZ9Pf=Y^f0{^=#) zpXhEi7)la9Qn3SKCqkeP&OztBD!?fz?CDj^QjL;Cvy^6BNo9;D_(c+`j}MRDF~QJ* z?cW=#s%p~sBkqT5C+VfwxzCAvE}peD>~D;QOoUD9F1j7?CqA$i5Zq7tgT@yD`gT$gE#Jy5u)$0~+n z8=r1Kk;OR5v(2&J!Ty);@?mgA`{BP6;x4MV>BfR>VbG}0`OS-Sk{D1QG7sJXk}TQBMc|L~9Mho6racg+)& zI6Y$TrfAF~2)e8cvoNmZ`!@CK0rA8#GIBv?L@i(2V9Ky39fR)ic)y5@O8x0nljs^i z3R%^SJngT)G)C9|#r|GT5Q8%dT)UB7o+$4* zg_eJQXkBer%r9g5P~X}$7X~uIbv9RzPO~iUNU zdw-U(JTyCOFfLFm-Pkan)3!DYNm6~4y>iVjmv#U3*b~?*RZ0DX#-j2aixutqFvAW{ z?`)mlKvb;?3Q@`^r~bc~`^u;$1OHzPL`i9-CW3^3NFy~BX%Uf(HS&@~);Fl#{#Ls42Dd|@4K*QpFAB@wdYobQ;7U{Q}Ml`6> zj}OkhmTq&U4Xz#Y(zPilwJdIwdWu0TGan?FUC>mfK66oegq!$OW%IK4)Kr)9t*vo1 zFNuA0#rVXv>DPd8@MT@R^KY}sm&RKPp-cDS)w%Y^4oK@~3nFM{F5Iq$gg0E!UO7JiY`KYe1PuVR`4@~!yK6M*-;a9(ySri*p_V@DvGKXIz zS>rUv7pNs^FS3*E80mIrz>)yMKp8xhT3uAD(Q|!UWQ@c(tTK>qs^S6sq`79s%b@H| z{#WZ-Kkd;WByX(dm zlJ!1P+D6x%z9s9lzVhcT6)IkumRq_L&s#}jSFiT%(5Uxr7o&slw)57+nosnD-L4cp zmzZt=(Y#B~;$*mg(kdIU1H}fFTj8~BOPw=7xXq30rsWE~ohd86UDwxNEpM>ma-_zbSG>Vo{MgrN z_dVuJH6&Rdk(oCJcZlYGE54`V=qnoWTF2J`WL-JA)htQ`Z#TLT-MMO-1qdltdS~|+ zAv4v7DhITCv7=|~Rw&Vov5EqpG&Ivk1!+W;AI0Bh!InwHiV~eZ&&NQJ^z?Rp3$+yk za5m|ZKH!=c>q;)n+<{7kpEy{K6%FKEg|fEju&j2U-cMH6EhBo=<|5kRS8Nn9!QIn2 z&1WW4o9W#S{x!Q>`~af%O2Oo&t~)LCra#9NP?&x71%;_}Zf_oTD}m`r^tHCW9vEWU zrP{^8vzw%n)~58M&OFJYSA55Moayj3Iy07`)oWF!4(u;$ndYT*4wOm@!&+U~sjkRID^&8`!6cyLm0l!d44UqkK25vu_ zp{=9JB=WeGp{ftV_I_>}4IIq77=I;*q3QXYg=5`3KqiOJvni8|IcTQfy7B}~Nhg44=!8aoZt#0E<#0#MYG2?= zLhq)&`3nuQ`n{IL$4QMeZO3W1a=JY=ME_b?T{@<4eI*3003tP)9Ih1UdSghnr10Mw z>E2DtAS;&(DXP{+_JCohg;VneUY80SGA#96GFa_$b*v-_kevw&*q!x~4~=-nmE+=b z2^D8v&UAZy%xf0Q{eN(|M>P z?#HhD({xx#Mv%PTg%OJCfABw57#i5Pz;a|;9fCWo(Qbt8;@erAG*drBKVA?o?>OXW z@fy)!i{EG|*>+&dq0J<_pqU6FRf5ac-eqsEzS}sFE`diQ*^kTzA2`WEPxKY;hJbKS z4PsEN-pWDh=*i(CdmJSu!u6H?4gKCP46q*SMH?&W+gatA*#XmMftb%;Rq653;|6_{ z?0ys6XyQV6H%lYI(&WkWAwfZ^MVTSEFsRxS5Vkby3rgR-ocMW`m$5w_g7ni78!P?` zJ%QC|g&RV~!@EGbq+8@N$^#NDE<1N+IgIP?m@N4j*4>`m^`SoNxzO{z8;oooQ5&uI zVSgYufPN{qqiTQ|iLjgA9A{2g%!?8U(VbbKisamXWjvF?r;}SEUuyTOwaY)3I$V)E z+?hN%3Ct}c0D!86`&Wb*09+HU0KqE^**b8qgV{P&$b`7Z1ARsE1Msh0`q#FC3?A zxN*o{$s2ww|EOM8;=1Y#&AT`JzaSN3>~aFuT_s3?Wd_utF*4i{<9t9+9R zvH%^ZLjljXA+qPSc-J>RjyB|W{m?VXC=2<Fid$3LBIHPHJpO34jVT%lTw+g0*I&BUy zpG>|h#DCAt#D3hx;b@&qiK}aOdth0-eC>Y;=c zT@^xLc#|`IB@2d2mDx4zl6I623M$E}h+2Y-R@`vc(q|8h& z=6P7^ zD+Z~Cb^z8!j0gUz@>$CLnhhO>%_KCM^oV~v``x&q2&QDkkL5yhRcRr5^$Fkz-dVK^ltj%6FzP)u}~tQXsA;qQ-3>yT-M-9U-% z-rZ7MRABA07{N?S5CHdo^aca!ByUv2$h7Ex0gP?`eSi_*?0ueiS_xP@-H6!qT9T-` zG`?QhDo5&gPO}79`dJ6SnP6k`r&E1)@jzzk{g$}reDJ&Egy7X@jjxE}jm8rEAM%r! z>m6HQiJf~BFvku5BcqD_SsqY#QwBF83?|)5WW9DJ+2>CS(b?oH88CoWi~)+@hmr@P&_@Z8OL)4fhV z0H==3eHM#=s-vkh{LEDzINcS4Uv=68ceK7i9u3_4N99%c7ba##h%x*#-9j0L@ZLi? zA|i4za;f36`>YFhlDpF_og?h(Ak|d#8Cow&uAWOFjW<;tSCQCGJZN?KV|XX{Iswwj zB_GT%;p@|%?^Lkl;x90A-asE4+xBI~<`FXCo{D<;(%&gH-qzOaAjzlxHgmIiLN_el z(1)`ANWJAId+lw|J`Qp6fZ((W4pCz!)L@VZ3#QIxf{sH=UDHpLJty;>>LJ$4UH$cq zB0+I%uHI{>X9x(vex--74DJMn*$AihP(Yk&CavYJZ>RP>xO!V1wR!5Ug>NdpY6`zn z(a{jUlEY@rZ%O1zq*()`0ySZ{f-v=AfQLz&AaYSyk7c;;%p4g=n!uf+c^67nP^^o}7 z9vpAnHLExU$MlbtkLNKQ@v7aO5fwK6Y~s4tLBQnfOB*mr=gz%V+mz>Buk+1yhqchm zCiek_FW?Uce{hefhFkn#w6`}Xja5^@!JKK)V;-Tqgm)#uu1$=DZXWIxjQ`MRlDHY| zI>68kbI))FT=OpW8sawFZIlV~K$?@<)nBPbO@GSlC%muLV&9fyDFg$fY$+?=>9{hG zak`*?*{d0K!Q$q!sQTX1a5-&pvvHNzg;w)2&JyCDp?7BPtzS~S(Ji=q{mp!Ysg~e- z^Y>TgeCe)nM(tYv(G%mROYlKigsPamW*ASs^FyVU?fAz!v$e~gydtc!rjUNS52!Pz z^QZ#;9M5(jPEBRM)n0U|j9`X$?^>p575EEbmt_*#e=!DvdgveaXv!yh%)cKB5+JI> zrk5@fh-f_^&@XgKi7C>dUN7QUOvj%gXUW|Sdy7~McUyNMW%&(PKu%kUcMVsyB5<$+(bfgEE{RmWb3y@se z0_%3$mu>RHIMzsH{n2iRr5TGTfhtYF2|WE+A)CHOb8q0PT6c8&V}MR^;b~@qZ_0>BKeVkiMrF zoOAEmv%}kYx$*6bOV#?zkGcL3iIi)xxOt4k=BFA&gof-sql#I20isBQO`m#wqOyd= zEgq(w7xlOeTH+BW#?%GA(#%;7>!5&f24QQdn)NvOD*qyvhs-A#`$C#u_LIZ+)%mZ0 z(PvuuURvmh;of*)dVMTwaLLaFpt)ts!b1)>+ec(i&wA8zPL`~fLPKG9 z%*2+}?SC4+xL=Xj?VBhEw;|a z8At)!y`l$Sok2zcvv=Cu?g|*dwF|rs@z3uP3Xu-6(HmNYqd*eWx ze054P1#N`&2!jQ)ANFDm@`Z|tcM0gL*MV+6Wbc^(qs)G!0@9vCGbB$$1@O?~e^fOB zt0M%#qjk8eJ6#xe^E`uz=N2VW0R9vvM|Pe@_wHzmeEas}qast}l}G5v7)P4-l$wLA zD&@ghL9?^v)nv`8h+bmpG59T7wl!aP!&xb-$uhlIwM*VKamnh-m-*bjy@0zS;s$GC zXKJAjOp=_`eS#7a)>XpM23RIs;_9>fQa^YbSI6?wU(yJ-Xl#^S#TvteV@rTRq<0Hv zd%zuFYEt(~hou$v*k}7I8fzeHy5CPZeICqBF)NtVa*?z)Y!B}-ET&Ox0rzbHygp-` zL60?`zAt*?M`KoUbHPn}6S2zkm9P`!T|zwZHEaY3iwOQkKy*u4L-@r6P2alFYXpRg z9t2|>TQjb;nQtg_8%gHs9CmuoZ`hkjb-u_e`E9ea9RTS-0G=y!6nQ7lZ3zAGj5oLn zwA_xk=hui`=7zQh?R3;2=5tn-qVX2s;OW}wUK54rH{(}7hTgHQcJy@X@i?2-r0L9@ zs|7QEOl?w<+VCYaDmCO^HH>xH61EHa)|9(YLUj(4?Ma)#?m)f_=lxiJdh#amG>R)M z-!a$e)S@C^dVY4c>rh|peKF6gs!E{MU4n>!u~?$eHNKlF&XyZSC7sTOey!8+qGlSH zBs*D+q`qI(%*{$98N8YV^kY)E{a|s}Z5OTyDL=UJtJ=D+LJBJQbFO`r2bdt%9xfHG z)9{Lv^B$~1x2)sczq4y*{k8{BJE=p?y8~R+(|RZ_o~?3Qx~3s}r;7VrBnZI+w{JWS zWGuQ&o$GHDT&s(7X!poM4VRD}6UK2UbkbBUMGb$aAmS8vcCz!n%YSsO!e}anlh#oY z`R3=5!=&*76kDGy$#mtcuyzxK2G1c@6k?h+oX}tf!tmJXbCmL{SYN7r@}HNkLqXSX zzkcaB%jlF~8q3qccu#kG{YCd^8B$}B{{7B!)C$QT2xEXVRQDYt_?&Tnr&z!#RZpLd z5mcZx>-IBHo7XmqDtA95RqJp!bVzv%|IkWx0@WaP$IG?>8|&~ceQC?m9y*p3?-xUV z++US2O_u&GsOw$4yRE6t_=vA&-*G`KeJx5-DsOeDX4pziEjEzI8R&DH*;Tcek9TIp ztn+X?z-lueDis)U)bi}c*I?fE_DeISBN3+S6}b%zEy?d)h=HNozY7d?_kV!d2Iu@5 zX8K;<6HGk4#R2XJG>ap2o+Obo)OcL#vab<7;RT+K$_=pOI9EIPq;S0Ap_#e)sGWxI z_?*!?b+SjlC!qy#r~i(RFN8tuHi@6mX&+P!<;T~ANA_fb$5@uE`Z;!2`njQhxp{S0 zrbqr!(WBhNo z3}!tE%I{3T_33U_7DrLM@$p4{DuJt#y^*a_{k~biIxkFBb@e%em(UkASknNE-8)8{n`n8-K&wrQyc3&zNTE<9~ zGNFkbt;0AFqL~hF(2)XDBDj{%yUeklGF#0nXxUWu#U2U(8J9)3YkTd!#t8A6rjJJI zE7*Cv#a)}x4B9%`#w}{ymA`QxnbS78j-<-zcu$e8dxU8scLxv0*FBSptr<~&P0N$# zY)~-@nVVJL=xEOou%_T+h<7qSFnzHjdLdN_-|;ys$Tof2WotqmMzPupwS1yyqOLkY z4EVb8aHKB&Flg?mbm)u@%HGegTT~CNF z5gzHM9KYi3vkuT|)yZYa=X3v9_iK{cxh&Pkn{04n&7o@dC_@>^`gTw&MdIF*D7II8 zH6LbEFO4>PJID3SY8gI@N(-*moU% zcg)6kJS+{4yIWLq=bLe2T#P}bB?x`-N7cCOnTmSu-Nz;U-rR1zw|`c&^jHg*sLuC% z5yWW@qqh6okqYztNxN>UQjq=yV?ZZ4du$xv0X!{0igR(fJs0{2KNX9X(A);g-|*J! zE4R=-&^$WSU2}|@!})eGg`$`XatsJTtL1dv3MaN+qfY4|oG-o|i?UYH9=u(DnPzyh z5ZC*rc3Kf03$N~N2hR>)HN*5qvg%DpvdMDX&$Y7d=kwU`H@xyHd-Gxil$-pGLJtiZ ztEfSS!1xj7F4Ag~?@YcmeUws^xcuEp>=o9v$yqoNGX>gtruKJL4rZB+$-lV2$u@1> zi`s-JW#?LE%iv{B!U?=MhZPIxb9`1#IMOb9C~ocrRwbfkOqRZ*ao?-#;XB{ zNYn%X0f}5MHYqVWH5oBf(v!(ExZ0xksYNj63cc#1eH%`^ z@<}j(6Bqn4xIJ5ZN_U&S)$WT1>(EKi^5M7x78UF9#-kppVqDTB@FR??^|sX)GsjXt zF-u%{l6zm`=n4(Z_cJf zc|_J*-CD#fHSxlqywj*tLyskt4Vw@W>vQ@%abRk>q3Xr{8Yz4c#J4mOtC?GkyRrEb2+(tdediSdqnx|W?+M6O@T{n1v~Qy)2meVLQOc}jkPlSL+HV_b^Q zk~(*=IL)FOuB2eA(7_!mI9~U7vcEPS+7vN~9}zQF8z{WrJDV71w$5W#e6>1G$K=Mz zi5pc4^()17=Q~k7%M{gHFV85-q`wmP@SrW)HRw{(4|e*q!1f-LG8@M< zhI%~a+c=pZ*C_7sDK42}?iX&9BVV)zf4=^Fy;HN-026_MwiDQ`jgLo_*t`)<)PZf88f1^ z@0koAvRa^0Jy}<>VwgY{l&)iN$Q0LfI|@i;)E`GTOdbKzeU@@V#kGg<>Uh^=%Fu0* z1z#{IRun41NVf#e24>&;ge|<@s&Cf_;c>Mj!7QL6>!wl#BCq2G_sb2%>z9|>_+*Yp zo+V>I>_7p3M7V$fGg=e27xQad;A#s$&oVVv2i5ocDEE%a_tFYW!7p1ufHTcf{EFxX zPM|k;E7d1-CCrQ7{HEAO6NrcO>K7rp!0(5vyr|n|wY+D@L-vL}vDl29$BTYdtG7ok zPt94(7uy(XD#~r}$>Ys>m66O_2;|@R`S$v&>&Daw)g8GvHL9x^*Zm%QT=V-aj+DC5 ztCw^WBn6@lB&l3bH}23dd~z-QUoK{u1!{Ta@$@5B?<$!TBnXWu1{nd2i<=Uy!rMlE z(OPwuq3-uYT^nAg>IY0!VnC4r;-dIP3*9uR6NLRAKQPB?&GtzXQMtr5bc?6g{^`_@#|tcOn;zn=5S zwZ^H8-|jH_>MYd^`0j?vg$lpY9)(&nPp2>17>~~n`PF&6zEdMODsfGO++GN$iX?{j z!$_yk&m}FMgAyhse+w;bbo6Y*S*U+1_5v;k(3>Wr^;yxqk%-7ASXv0GqIO={n>fTmTd!1M!WpP$0s z-%KYdEfw1-e`dD>V!IbxQ0Mg<;uX^U2zMfI#w9TAJ`U5#SxfBiWt}0`X8u$HrBd3W_;%H4J|kJN2)z{Tcdv4 z>11ZQwIPpc;d_Ak>nxgy2$JkI6U|eEIEQ9H^H={ zG51P?Xgc8Bx8?U`G@2Cw`9wMiO^#FJsK{7Fgf4SexYup{+Br>OeOwwIWf}Nt^l;hV z^Ng0XiMUHtQT2y=Q=Ss{R*?XT4L7^vWnL6wlUoU1_QSzNPl5E?>5fSV}HVV6lloO9&w_05)VEg91t z`<9i}D>*j|69Q^rK7OY_sjO|@JW(b1dZS&{wX(`(vDe#1R7Tw0w!8&X4pL_B=x;i} zHkg*=kl)j17tX4BmuX@5U+Po zk+Z0is9$4HbE1M%BRKdrkPYXCATy#C5*8m*MA-EF;Rg6&m6*mb#kX=mpVR<# zqTBs~OFAOFe8W{}ziS8XBEiuilAR}^z7+`q)=m)yEm6jYI%-^}lVBnh-S9m zMrbs<^$$-b@$hk8tdq-$O3#kOv36RJb3$GS;@~~Jj|1Os#3&64={UH&v(3t{^;lri z^_BUh2oFW^Hv6LyGz5$3b{PHmo?H_+@|U&XFH7NblkTHOEWLtmkFq+$&R`Z3ghC(~ z@bM&++T({`C)za9wq%y1nXs`(;eOca@ZIex;tgS&`wsWUS)z*Zf{%O|+$95RhEW+O z_^!Bzey^NRF)SoEd8eh#;q7O6JoN>fN=J`-J%wGEkPM=CZ%9 zX7O#mh%Y@e?4&QaT6eDa1dMf)wG#JnA?lGd2;f4$eM{W*Cy8cNyZ{7WCf}Gf*=&1# zYqa}j*a%4a(}TVd^@L@==_t}eLOa_1#xltm&Q7{thdZ=3xI7@&d|{)eB_@=)Zu zGo`njlaA}0v$vF&vu&AmpLKnOQw3tSSY7J$CrrT#1tg{AblX@cm&~G^rM!> zRFy<`g=$`!cAjeIC1j~gdsHKuQF2fsxO^4B^;!*4!>7YDr%$=bR?b%+@FhR8l`)+pF<>M)7G2VPJ6zm%zd}Loa1VQi!Jqyt znk9T^yaxPPN%!ab+$KM=W=?f<%iTS($Z39)Y`im(s_>cP;qjunmmbZ+&dP8c8uOv0ozu5*PFRDGpd(7 z+hiB@8(D{tqJrhfxkA~=C2Gn5J>LzL3l+kvG~P*#G;&?gBlR5b-u!y=x00NBl#ii&HOD0YN$SMvi7sTP;9M+O>sAfMhccOFGVEE=4eI|1g zqpAzW0Bb}95t`chuHov!DeQ!B{oqdDTh>mS7Gh4Si4Xj5CuoSD()V(kk6xvm%ITb5 z0)`ov{W)Rue$N&O^c^aK!!Cz4ORVfXD95_)3o)K$7TYs_w|kgD_2S0f$UC#{$*+Jj z+>!E2o=d@hrakcda(4KNqPg`L3;V-9KFhc8$*#d~D~yu>z+VNl0L>@235Iyu-ToXI zv$_|k#d+6EiZV)9S3{L9B%07`>tSFb~eout|WtFnt2~^rh9r zfb;?^xEk&Te-eZ{j~VaVXN{DXe>|NA8>=e;9woTz#xc{Eeul!NR^&-2a@PtCuN?S8 z0*k=0B7_mjwMVxQCo{OH1g$j3QjybtRF9MXlQ~uAg7Z9i_+R-|!GyRt3P%HT(8_ZF zS7ffa);av&N=pIyZ$L^j{YEWemi(M?w|V&s#owtQm! z2e3a9!q%Le?ivt5B$nWny-0vzpu}Dn18nddb9DWA6GkIZY#EAivTia6KtdQOcc9{u zY0`IJvCM~4XQI^Q_?Pz4d$tt*j?CH^_rrHs6@DTUK@Sb?)g;v52CQxXixjUj#Qf z*B}{p3G=kOmhF#Z-|Lw({V0+Ffrh9F8(6wT;1%xNj{;vop%tcvhPn>7sb7Nx!%qVp z!7YeaZ5ULG3VWwX>6fXO&Y8bXqW0Hdu3d7r^iTbhrzN+8#E8sL#RSP&iTEXg(yE@XEw zrv0X-<1Em(uX)pFmtm5~!1c0(kU6X7Bj@Uza3#P1pe3O|~?0B$+>upUl)#`uqlz%o6xj5Ca0rg;m1mkjU@C;NLy zbe5P_9p{vXyioemgW)5F>@x5iauW9yR6HWq{$lBR`VkcPDMq57A;ER!5*dg^&u#E* zZdcAPc(<#69zhvbE-Qv&LZ~b(&W9whl4yJ^g~3>}rF?*mIgJaC{52?$rN@LQ9mG^m zovRv5{6gA`ODEs4BbBKO>DU~f#37c4U0+*a#OI#~W=E;9QC=385pv6(BDn6Dt7r=`Tkhkr5rOgsfU6||Cvcz!Fn0E5lBRD}6-gQVcnXS&IPno+C za>1*w?!bIj_Jg+gKdOM=zwLlqrU!Qm>Kj2Jt1&ZU{#b>pNh}l5NoHC(jY7FE(*TU7 zO6rrsJU=zRKifw9jdW|@;`hzS{LRb!e+2y!W7nAHT0h~1KQ}Ysb||!~z%2L(#~11H z-6_%`v6&JKNo@x9r#IaJSrn`$4jp?kvFTR?)Gfx>vI+i%1ESS&mlPr;fQaVL6(-aWG&GGtEKT;LyJpAjV@;qgkBLv;kd5gYLu;C9> zcRm7b%3Sp{RK*@Yj`reYoU;iop7&>NSkvK|HXYtvOps+bLTX9(=+@BNi(4w#ePD&W|5vF|MtUZfVHHfqHO_s;LuFjN|e)yv3IY=Oa zFtZMla@-bMmz<+J2_oklLs$`W?yG89MTAfl;lf^?bYoh_x@<-BC{Pu0a9xkL^Su$t zWc$slOz-=7bJ^jWIc<75p{Sc+_eC%e6Lzs$7AG8Xq%7kh5%NP>XFWwRi>KF}`{&uf zy%kjk*iuHKO4$l21ixeT)wsb@v!+!{>V|UtCL&)i|LN=L-Q+gGJ}OM(TD4u(v9gYStOs>-9`X0g3S9+%i@vNfPXL{r!wuG0>KD_d$;2$pW%22nZJ z^W~M;^K|*Nnd=jFJP$TE+>?03)z^c67Tt4zeSpdWf93vc@5vdCCYYoL2mGC$ z6=Gufk;mL=n%Yf`aqiV@64Q3^>pE*2DAyPpy)&_#FRR%#*|aJ@T?PkO&hpai*$xeU z>7Ors{oeZ8o0%tY5~IdpA~A}ki11@apnM)S?k?A*6;v)k`ZDz^*ZkgR~$i6A(l z_Zopmx?qwrt(8We4!`tbyDaSK7qoSfK)tl|+NaQc8(tNAiy7L< zoVL`v5ajmTu@~BukGb`+n0e+4o^3@-M!z>uj45@F?+k!r;L49>Y6>^$2|26T0N_Tl zIIU7xAk^k^OKCyZ=I@fwHlkn@cL2x%T{`d|NA-`_p@F~yb0&DA8J23#mHfiC_x7>R zMZWZ|ZGX@f5Y1L+@1!MzuYLWUVsfp;U#Of=mA-U%q((=s*#*SIsL*VBa22w{oo;am zFWHf5id!UnYBv;&lKD{82RY3@JP6f~@Tj|iTtt25=c1{B{16fG=0~zh*OGbarG=-hMvsCuO4A|*3nKmI?S;BjN;S#_3aBabbSH4MA z{G&=TdupDAkRa#UW>9XfVg$7K5f1V1b$AI|5IWfKa-{+A4Wi(ek8-#O*_+SnCTlw1 zvuF!)zh>?;)PCx!DsyPInnvNck=dD2uz)H)hv`RVb6;F%+E6x_Z89U218IL+kwDcA zT)wVfEF3QGwkKQg;ibsSgJ2hE+lOX2omm`Zpp~DToxR%QPSlAu#b+HagkfAgo<{th zU5ei$B2darN4wO}sv?vxk6xqIfX$8z2@#m$KBuBo1x2o%k_=49VbDjpBdd~;+1GJJ zaDoKhI|zxKhFs4VCd{iAv}1a4Q_$AWMh^B9f(O5EgeX;7oR zyF>`=^>*L~s*x6d&aNQg6;vl+1`B7ZVVdQ%PWeY=5;!yE=USMs;&yoDK6W-K*?w`X zImS*TFdz}N&z9V}7Etd$d2&CtrI!=lb&6zg+Q-?RkeWu_EG+eyc+3X`#AA~ZT=FFW zpRQkGu17=AapH5oXmfla_7Vmjsbnm4*tyIo={0aI?b*eMwfT?Wxil-7N%rk>?NP63 zow`$JO|Hy4ka@MAdK*V-Ipiv+J!h{Xh1L($j=j5;eZQIbl>Z7-QjcQu5NbEv7KqOA zmn5;7?*Y>`0uUF?Fx@F14*zc1>*@hI@0j}4|H}Z$>$K|JU{v}-vJ5_QEJ=O2P&X-6 z2cG&jXdc&e5*-HlG{@8n;#?}9tjH-aAeReC)jbbMdYKGv-Q?D4fxV;jTkJ<2!{?Sp zy5?dMXB48TPjc^ayfbi@KYOTF9DhKj_BH8gtdCKUOeBuTFntacR}b|qZs#}$_SdKGHL^QcPq0!n%!l5X)lNc?0{v(^mftF1?mSr=j5~F*tQKn z^=x+fIN0?*x5WpI+bc`h8&h;KGae6$mn2C_vbNDeEG_m%uH0V)uV`leqpIfn@wm+A zDtE)XmFX=UnoBx%QWL6<5iKmc3OWgyRN7YhK+NfZ#Qp*!C8NPn(Lbse$Qna<`8A1G`kYuAl@Mj8 z?c54!=b91hwc<##zVSEOeH0T?>gq{MhEH zkuZwtcH?FgaK~a8La#&@J$Q6mKjFRtYjxaLcJxNGBt0*U1-qo}pLP$Xx{_kWy+HC( z)rpRetX)yjco%cy`WyEiR8FbKWv7W`<#({~-LJXU>LkVUKaFE7#$Uj+hdC^25vpn6 zlSZayFxT6uH>y`)$EqzJ3jykaihi2GgoZJoVd(tXsIXY}yA}HZGFKsn!uX)uPisyP>)9Q$GM@Lo{-)F>vYwCPOu9&DJ1d81~YS_k;5# zO!$)VLn^+4O6be;ht6pZk}TqJ0tXHILtx{nwVE2~c}+Ut-yGtbysFl~Ht4vQn`pqX z6Pq=vsrGT4CPuC(Px*%q=lBg|<$1!oVo=i^$jzM(OpCLRnTXFcR0zG+hAHDl3z5=d zpptv*ch4F4WG609IOt+K2@BZcXqL@rTEF)AGavWZi)Ey_~WU-@>%K7{L`# zf%DzhY$l_5&I@a|@sJ3W%9h*W*J##N#&m#_+x0cqD0W_4Ue2bqRQsdj2dzJQAFcA5 z$IafRseL?|iy@mcPE|APiK?&#rc^Rc-%^vF1geFWp*GaEyo7@TpHn2;npY-S1{`xj zrmgIhU2ik&Jrh&!Sdy5i$=HdOcs$8}zhLEgHc$_6A?)vS5yHj(a2Sm2Z6E zVa~h|mo$l&I8*6BWx)(0Ftka|vc5A-9CZOZDItzCp^_GZ6)K1q7VD`3P4Jub8FI`&mJp5-Pa*i!O2Rojb4A_T=KWtWbDoz`OeP9Y*R9S}&J+K5A-zS2L&w<>}TXZp*h(gy2}ba@W@As0=)1G1>t8 zeJ2F3I-cq8GGv)ym9fj<+41uzm%TfgKQ#GS-&`D@OuANTT^GX#?gGc;o7_J_|K4>Z zq{6PO8mmxX-%_b?}vPD z4uU%qubTpeL+Do*^<3b4(Qu4fEnD6ry@2>kGai!ppoCvF_&AW^XC>+Jw6T4z>9J6@ z+U@P8&tIrNAUR~HxmDY7l$*Q#mKeS&E_dxqjBArJcy$wcg`V6Q;|aW{)Q?o@$Az6= zoxB07kkGWE`=BQ5T!}(gx#xR3`%8a{R6V-E?1|IZw3pti7DYdJoje&y5lK`D~IZNVJlqIVB+AXUhAaY&!a8i1nW2aUlI< zbTEby*?#6wZt+je$or{)VozA%B)E<9;1~p6$R-ya~l@ z*!KI3j`Hzzs(n)vbjg&Wr5TH-2)X#3J-)QpP;t$#KdrY!l5EvcnTs)qkUG2pzzGF) zU8>$!{T-h(aX*d{^=nBt2#5er?%wP3glbIHrY_W@1ZEg*gau7bi@nO`R)qIn*Y2As;I&Sg{TDViU_G{0B*R^^CT0N?4FtS*HIE0wpb zT+wkqkDoP`2x8QOm*pX{hru65M(ILume)qvUpZ;&-RjYY0S*l9I`2#<+*>qHo1Dre zkm^eDi=Pb1E?bAm;5U2FlNZx9rfT2FA!<@k!4?7pz0Bm7_<}NsH=66c;S#Q9(&bEb z>A@TmFGCRdgNiDnP!02@&m|F_90CJ8jqmnozQO$r_a(=p0>is;A!h1g-8N6t6_RCs z7ui3JfY_B!e{?w$C7gM%kMtPa(4qI0x;5eWyzYa46+?yAFnQ+~aV=}h_(&@}hh(S{ z5JgE<6BPMIlgs|9?|s`E7y0cNeB~#onlBVL{tPFd`2FuriPIErt^g^mBc5$_>y{A1 z05kML|0+2>rGidfopP-kgW`m05Hj$(dxyQLN(#}<)@)|ugFo|PgM_mL1`P&2dh*X* zp&ANe2Hx&Hg4QwTCqu zUbdAlB6{_JNq~CT#Yc_gkfYL;yS_Tc>N@IR=+w;$-sV*DoYBD; zSBP!GBRe<^03~qhTK~YqDc#$`4IRl3NG_MULA6Xh|EM^v#2b6^-Ck>o|I~UHeRXjj z6bOn1JH#tE3`Y_jpwIr4V_C)q^obgY`*Dz4!HCBSrq61CTbwf?2Qwt?moj@SBE0O% z&{CwFcf?=kw)ME+%br)Z0Qnb1RfirBkqQR94|J3o;Hjk*G&TBMnB$B-lAJ?ee8VNF zDT(YMFZlaF4$4~S*5XIhBfsD)U(Z3Ei0GW^-UyN*J`LT9iW&G35OzX4Sm8j+uI?-WdjM0uU@5^I zTL*pyBsd`X{Hl7uRl;!_xSrB0k>8yR#W{V7uY;ZAv}grrYImoB44TQPoHjNix&I}H zMi#eT@BOe0++%veIJ(ORmDC(S9XlVoXfL0rM6VE)peDHBu54Qdi$0)hOxq8^tp}e} zY6<=>vwptGH%W3_jcTzH&O@mmJ>&dGl^XpgnMGQY^D>_za)aeC2#F0Ut4_Q+H{Hd0 zhL~S(><+NGEO`>Oe6qix#d*(4`i!Erf2F~edbjGDc2`8m{c|(n^?CDtS2mDz*X#r2 zQAxn_N>X?DRQU+7jLntM)RDhI--WrWsN&x*4SrjtT*@>%?j~|K|APGnUA0TAlkv0E zd2sxX>VGiy=Fw38|KGUYEwYq^?4}};5VB;Msbr4{A?uW#u_QagRJO8)kae<$nCw|6 z>txTq8)M(ikTJ~izOT>s{@&;NyU+QZ-}(LL;JA*tuIu%BJs+!vF4dx*$a~r)9RboE ze!=%&O&9-vN{ix91k3Xv!eA(?+aZ8RS)B!u@PV-YT87XM$hLcSA2F_aW{nPdKEp>K znXE;I;RsL(7e(tELiR_F%W~aVZqCu?N|tGrkQtg75JMPFgAN3QksJNA20%Q2&3(|} zIcj<_*^zxuQEOOM9xm**4PY5Q*9u^shuy8`#`c>%m(B>1(w1JVj{HTd35(+0pP#gv zuXe0^a8puFkRJy1&fClf){{T`cmw z<9v2Ob`Kz5C|lkFXsv^KgrMR|=mQuzS*XM1#=CP~VKeDA4R4KB{xI%Ac1nPkTZ8<7 zq82(}BLs|eWMQ*bB6pP03NkO#p{g;k!XZn0R5izyquGNtx?HD$$R$vg)4GOc%mBy_ zP!9|-S-G?_6CG;Dd2jzBhJ@lIRVwQka8Jj2he{?$CESxC)#I9-(b zf|k)L6%f{ix^@%-g_6COxLwX4g_~MvR@e8jciG>Z@e@h-Fleo}Je3gMdWk;Cmzp5f z1^{{H2+?X{Y9XOW&D!ni{NDMlebT!?d;fUOP+KFciq&h&Xiu*$=hs6Nlg(7{Jp!o` zkBhQ!igNRj3_3JVoncIJDWbTZy!mC1^82UgF<#5#fZ1$?81A^x!K|kdSp*Thw@obxA=a4?G z_@%Bb#U$m*Rk{;O%N7c|KXcHrTuw)qV>+_sI%ZlM0v&?=13kU(qa~)^ zf4k^j)|+(4&16Vt9O;p8aa)Lg5-}8E`YZrtHSR;xT|3-0(z`S?_{*EQJ%y@Gg31k(2e?+hLSFOX2w;Vz&BlE{>@4Xeb&JGFJ~Uzt=J#8K zG%Jr*GQt3ib=CrS)U~<^&Y_n^eJqjOn-eoWcTs9xv9Fhrsbq#IUY;457a&$7+!7sS z!$^LIe}vc5@oe_Q`w-f3vzY0Oi=47GXdX>-!43q@|I_UsLQp4S(2OKMMd46Oc1|IJ z7C9+1*ZlP5)$|LR{KEXkLhoCgmc_6D%{Rln#Ma@W%I%~WE`NzdcNC#`Zre|t$y75| zTU5W$c%52pq4gU4ht`C7l>k&wpAEf&T~1)7nzRC)Gr4n?mRmtKl_9JL{l{7^sSCGe zMYKNcBw)l-=ds|AlZb_dm9+% z#C7T``8Cx#952^<^gPR`a{LIUnU2wD87`CjNiYRQjJjq`OAe`#~I zheK2j)7eK8V7`Ev4nxcptB!9^7EG13M649l6wjWRk^JA4f6q&4>N|woTuuqpTM3Dz z^F&W#2CRR)`3vFbO`|*p zKLl`e;}Ya7ye&Y*%e@SQK0P;1^P0p*?EtZ6Kx_#kk(U%;x*27|K;2%UnDZ98{>z}E z>IWm#GSa$Es!8!2Q4~%b>V(g&;iOE?1`6p=9;jeZ>&oub{c4{q;+B6hd3ep-l#}?` z$=H5!EyUXS(D<`$s62fT5H)ChP}Qg0N4S$6mep_y!aD@B3oG z)%ct{ckBhZ^{*AY@&Nf)WJTIIt?YiFF^l|WCt@L^oEOvGtI^? zt)ad-;yp^%pbw%=GU^uo_%?+y_JM#j%|)Cu?mE;Re0yo5L*;>_v?d z?%OSIu{K9n#%i#_?ki$y;bnArYBYf-RzqhjU%w`#e9Xt~05)?LIVAHiUrWB@v1N{O zoCSNqx_*;beaT<$U7FJ}TP*G$Fy}T{kWe_^GQZlH=KZ2TBd3e+dJHeK()Ott7sVuW z5XJkqtQ_bFX_Mgpx}ZQ9$cb6fgWDS_q54dc`_Gacm~#^h>ssw@EV1U_X~(|~h<)tU zq9KVG)jzS85PZ=rbhAZgyr}lr{a6--#Z05RL)mDkP-f~)g2BgI^lFD-uQE9Il^ezg3>`Vnz06sIpT$T%1^B z8J(>>T-wk8S0lAz_3zfzNMEaIhFlsNWr3@l|CvhX=Z9N<)SMQ1FQR@^T&d^TcO+je z$CE=IJ73w$Wj~z`(2M>0PcTiW#VpQH(vv}Mqh_}8eMtkc8t0PwmNU_|EWZY){zHZoKzR){CGhDP6 z8YvPrUiH#dn5-!N!xsDZTf^^JSSJyp8;>oes)YR>_FQ_}E0WSfQrgtVq|rsszx_R1 z6E=gX2{1(x5;aah(Q7Ut9)6N8e;%hXpKQU2O~&L`MF?A9B`hGHb}X@lCtDJ}2O)yv zR%AmmuT0O1yeXrW>M1$EGARp@7%zOYQNC`A0bE`Xe7L>^w-5b^0F%uLSbSXb4}=^c zG#UTuHA8yMw$fsfH3sL)k0QEKlgNJ%uN;7bsR<$BLrus(6qDM@x*zqadd@-`mccPD z*tMRTGq7?C;!4l0@&{U4%#qs?F zh#f8l!c29s^Zlx|thWhtx2{Jd)2;I#-DDKlNeuOn*sF4Ta*wQBkw31h9I}owHVqW( zK+SlPqG<1%#UMNDOZ(xV*?K-T+E|87fel`AP46SiUV^uDz6u^YqZiG+R!aY=|n)u47JiAh+j7depXLa-r?h$OK% zhr-PR5B-1VW;~FUEu=rbyl^S#Mfy*P{EW|>+3AP=;dGIi&~Y4)y5E6|fn987DhUWy zC(Jh$)%$vLdP&439qh8()33`kNp8Y^tiQ_c7jYZnsX(Z##eCW-yC1`>BX8TT>UzaM zbMtzt0*}zqBuVS+7((;ot(4`4O?KfUH2>(TOL+&zcsKfm(_VDZYT`x5Tk(uR)Dv1B z=rZ_<|g#fL`YLzJ#eJ-bbr+xx40Rs$vEXKK1qt*CXcP$GtrjGc)H~ z8Z7(1-PB&sHg?W1;qg0Lw0Y3@ZGg{m2Wofz3LEzP4+Ar{9x!ZJU1vN*C3s z0<&JzoN635^`F*c-VEJ%>&LOTh+43g6wknFJR}}cGt`Bdj#}=jkmP&dwmpJsy1l#Zd3bYo0Muun_7*#AQY2&k;l z$R<3tuYb*0I=NICTQHxvNlRW!n0?Hc26ViAi}p+TQ^8Yq`86Oh)FrDg*2jaD5o*BF zVn^1(!WhcA4JYrr>lwm-$BJ%gR8oAgUwW7i{HTR3+>)@oRiE1vedBlbhJCr{Yp-=E zLw`6(8-3{#!x>k##|H6{@WS%aos6}ifl?$2Y%7^;kWAYPP-JSa?P$VTswZR>ypfztnbyDs84pzxA zt2Tu|dkFjN;ja@kgN}FF7TG@1mB}Sb2{XYzOJoC~6g}1tj{p^qL zRJ^uK#maY3^~w2o^x1$}lTnE4{(Dp9@p%AG`U>ZB`1ZmBZ|mpjKT}XonH~(-fMz;r zT`ac99?Nw1Q(hW(d!GBaFhfUdVKy7P1I2R`!*N$aA6N(YHjCqT--w1tYiV4M(e?)) zU7Dp};&EwQ2^4k<^<@@ZG=z8mN;*}eoR%?f@^uUb| zKGlCtuT;U|0&Eeq;Iw#^TBB*9R|-ds zFo`)LW-6+Kt_bv(mq{YKWva{(G9xQ>5mIf?n>s8aGI{mH)v5KVV6&g0!}qiy9&F*0 z-Y#-m1o@OK#ZM=1wO`FRmI^d(Qynz?a0dNXMAF97b_gXJ(!_3~j^W zU<8xj8IW1I&WaJjd`#%LAgRcsHF;n7>UcPiV{i3>v{y-(mQl_JMzg|1VtwR+=nnMcSq)1ZXZiL`ArBKeEBHG3bm0gIa@APTVWp}WWIzi=0ZPLN=ZifNN z(DvHAly^-x3U>#9_JUerT=B(GB|OkFwK=H^g+Xspz|rfIEG}2A%B$btE3?cxZ0^x& zeEIi3@ZmZ@;X+)^leHli%sv)HAiC@>o6t?@T&mBPy?*2^_oD}@WPZI|hoyJTrg_(s zc`5o^I4-KWKcNY$3?i{bf8Sle+agL5xzU#n&n~pSYg{Pbc+?df7@|E0-W-Vgy3soX zlWn-$`(VR``-YbMu8{6niY0^hpsVv>pk2mCKJLf)Riv&UwhpE|*oOsv*?$>^bcVH> zo{S%uFSWufXz5$4Np-R*P5Il|FFAfRVX?LS)yMhVP8FG6r00Qm1_Q%f2f5Np?UDj>v(uxm-Yu45eZ+#O*N6o z@-SJL=-p9gA>VFpJ-E$zb#_3YZc)iB-l!h{JRsACwZTIRaUVz-5}=AI%@08gE*~h2 z7Sx48J)LYFXZ1JsGCd?mLvbT+|Hoe4NIt49aDICKHgpWkOv|N85MWC~9rJPzYbI;^ zf9l9EN|ElB&4E-c4&u{W#_q>13yEf3t5i|_U=NORn-&*N@0 zSl_~g*RquRx1TD0*n8^eZrZ!B*$LZf%eY4k_O`5e-Fig)SvFdxRJms=;FR(4E&VRv za)jPHQ)AgHFK<{0L{Ck4sP2MquPWIMYI(yNUi%ujv#D?t@IUySh3=iBjD4Rzse&JK z3$kUcfdgp8z)MbJBsq|+y@+h)qcF1!out9;af8m(wTCYlk@%UD3FjsID{VvyJ$#YGLn_w$)B>-%-4^5VhGIS_ao|ZRqt#$s_QMw>h&E{e zVt=lqfb7}fPpX?Z9q4!44oG`q=eS$y?>(xtAH7m0WmefDKfq!|)B97gFMVH7mVVMP zXFbz)H^S^JBAV&fZcn+UUG(3Z74he~BiG@ksEEh`3%~h8o)+ap8zGPKh-8&}`wLge z$~e8B>p9{dZ*Wm#;!EevK_(aHQLLd0u-f$)j04cHZ25wqnGOHus!XH)`PpLTY{cTT z@Grw_^kC;(jAA*W14#*@FMyc{&g8OX>36T$F6apO|FdyYS^7xq#$5MKZ?T&7J(bD% zl@m4QDQ(jdqd~Jf#?@6?e-<9l(Ddt6U0R$lEf2`f&*l;Pu)BX%g2KDZE$RHJl3PIB zdQ0g}fC^L>52T0x%TULLWt)MT66+)B;#im9%VFoZ*{vTj&o;k#+Mi>bS2qGSuG!ty ztuxfjx!R202kuoG^@{O0s3a6>swyw%0j@m>nRz;0Df}~ftjA0By^^h2AkW|D&ve8H z=G`7y{P+A) zBG~x-_p_IgdNu;rNJ=+TgTvzaiuYQ1CGuPbw+$0xwR!kjN|mgop0OFiP>z=XVd%tP zr|S2x=7f?Z4y8k!|IJo)S}EYYQh`m!Pj(y(YQO`M*jut#MZ^AVDZNx0qC2w za)_(+WqSVt_h>CYMZFXr)Sn=jlGHks1UX8=P*^@eW(I=N%~&S8i2_x6(EXQ$m;lPaL;?PcF$;DGQRPE6=r5(GhE@@t8+7ZW?ilDb<#M9?l!?7bf?q=dXk z?*lV8Ok8DRMY=jaUGRi#%N*N1MFy7r1-u3u6Ik2U2IJH?Zb!;?Ve9hmPRFdun4*f+ zKigCpN?^eHFCqCf{Qj=k;z>?7#`>I}nPQ6T<*D>p-ZzpGc26tkkX)rRpgl+1LYdFU$H`%F}CiQ@yi(A4?)9 zkdh}bPE$ThLxs(o>mF@F+9Je-8l($AIsh$6$m-v1BBdQA&*`b^MZ~3Ev#`%U0r#Dw;q?>_vI z{Pr14dDe0C*-I^y$qi^5IzE(>j0fZhI?eL@mIEAtW~L({WcxPHPNdHyQjj17690AA z<1EMSD{iN{*gi>Y^OHHT%cj9RpMFY&>H0;e0{3G3+w3?>2kvHebyqBm?hO;6PXMT_ zLIQBmgX=Y=Vkws96RU}m?*2QSUI{s7B%_DN1ECRZ2#7Iwz-6^E<#T;V(%4G3t?AX+ zveqa|ia7O6+VXL`wrcQQ_SyMc{iHM?tD!G|?(loJK^vX->>q3_4W9h*pvQi?#jW*t zB_*x+(ISz#h0EL*;Et6+L&fQHQ_$kB7Fb9h=v}3;^#BC)F?NH~?63F%{y+VJ zfCi<_Gk*UAh(*{qmCrFBJK_B8?7>awd)(D)GnPjq7J5oIuQuaHd!KiQ66H?;BKO=; z6*r6ty&&5=5fuJW_{_UlR^**iwK7Z~VTl=}{ zh!kFrbLc%zKFaq!maPM)9tRF!$JIWBkwszQ&Css_Q6}RED1NF|nrSmHb9RxvyATFNTvlYf)oZ~}A-3QhJ-oQ`%$ioEnrMg05N7syI6rO^4B_X3Wj>C+wR|t+no9h?jX6ky%_k^7bN5UFQWes+i&vU`6 z4_JOdxT$u8i4Ma`LgAr>R6cL?v*M^rZIG0}{;LMOQ*YN`UjXB%n(MRfkgru-7nuas za$W4FxIT03xV}vlH&03YC-&$!+LEk8TwW6Uby%uTSR?xMwOF51s+ZNo7hKp{G%qm(Nw=dvHsacm zT*WayoH`z+;x}f+<~zf9sS;7+wR+`F&zr_8W_^y6YAQme*51200#!RUafIR}sX{_A zc1A1V?>FJ5h7pIub8@WM>o1>2Qa8@Bb=%x-A*RLDqIh8EqnBSaLSP3Uw$| z1c}dUKcg@{J^IRq!7SzgZUVmGlhC2PWg(%gpjC7@e9$ljHr$1EhblEenKq^W&_EIXWd{;7u7A>V z>w2Vr`l8o_v8GpDVYRT>`@sq_I)O_P;iiISzT}P24n$;s|oMjI$jCY0!%n)!Q_E`s`oj4d2 zg~lSMs(#Idj@q1+?Yny=rrT3S_JUmm>fEUhwJX#Y%lE31jZ#HTCkaS@7f0Vm>dNA5 ztdxg1JL9k-Lba2Y?bwc)<^J`nGfMI^0zjh(gC``jS}WXv@|e5 z?Oy5nx>?2oYFXU{boo7yLc}L6<5)Iz*k-pWW~wAenD|tScxy{Zb7h%P)hof`anjkE z62>AKo0jyqc>b)4(WdKmp!J#D;+F!PSudUBk6=6IuLvE6v?2soG2+!&?ue?mWarWz zJiT@3!fK>u=muI$iYv;jK^kmTYuDXgZ!BGJ_UN) zwRRgOcCU&U2FJMtTrT^DgDYpRp-Xz5np-n;);_&u=@I7k`?Z{;vs5k4diyIIjC_e` zw7i(m&Bjc9QCn^O7|OaJIXRtO_feBs)?@cmcQsua@n{Sz1>io=&dlxGJ01wVZ_pru zWh|CAyYIYEizYzC2akJvXH5V6dY1XqLb$h)eDelV!1Ti{-5hcAcf8guj~M?%KmM*f za&|TpOm)DJ_m}a@G%fw8r#}_0nL=4XTZc{;V_pNsa9%Vg`)_ULg5=TY^3EDl;k*L- zx7YBRK{@Ax&|TQ!M4`GH^x-<3LdcTNh;N?6SeTZ{+30+O9DS zmq$f;Vd{YjkiyU!^I_F|V&l#~CGQ2VJh*c~H`&H(5jVSzR}5=DvxqwPAE39fx%Kip zGa%VVr7&mxdoqBUw=RxA24|;F!0n|gQ)G#y`uKG+ipbxIyi#$W5_0Q^GVMXfy2`M! z+*rDQG$S(fqD+Lt@AI%;#rk^xoe-bNegH1e52j-DZC+_WK_M z*7Ka!Xc8k}MIa3$R5G9n!lZp`WYX~GfqCdY?!oMC*4WWmk{F%o;jN!!^<_9*JcB9C zDxy%hQNC*Vgpc+#F|W2=wJAX#n+#j${#Yy7`Q^(g(C?NIg`Pbio`Y_?vp#vwTOZXt?!6<4N zRLIv_Y@6vew!6qt9}iz+o2grn0GL&z5OrjZLwA4$zg!O?p4t*RLmXLoEG>>*=@1I z^mDQtxYY;fMF>B^q;#!j-Qd!Kc<5bPad_#YmyVg+bj{;wX_nmsd(d;?)91y|M&m5LnS4u}x>p3-4 z9+(XpWleG`Oq*QVj}Wa&<=|%W?moWJ=&AYK37&fQM8tQrnqSxkXkc8Dve zCugHidX;E%PA=%JRyN{=Kut3NuBZ25l1Ff}5NKlm59St_a}nJDJBd68W^#d?MeuTm zA=LasN@bh+yaNLaP6|90ea<}GkeJCI^IS5G3TE{^#}12F=gm>%{W6Iijfu`|NyQ0o zi5nGs>rVEsk_ahXU7Z{3j6d15fVs3doCu=Ej?iDCCPxwFTkf}wMpj?f$68)opqjuF zl;zzwR?ZCddRbMs+t$0J7VE2ZmksbCKJ`A@{D4D^A`5UsQKbok4u<@9sderZ!=PHbNsSgt`d3uQNUJV|+d`zmg36dkr;*lNVY%RF}=y2eSokaa}g( z3r=?kkbj(MB05j0w%o0EzI=S$E-QNIrd*mMRa>5H;>t6VRI69Ld2@4g>LIDK>ZI?} z1J2d(tQsf(kp^&yxr$P1<(0jlgm#o7Ma=wZb~}FB{~t&=GAPcd{ctzO_uJ*B&{tuT zGnjfMr!%)#{&MVu%6!q+<519X@(dlo*h!CtzzwX`R**HSdTU>Qx#xRo8W56!`iGC+%eovT8K}v2h*tz^YiKfYs z<~z1wKO7ornFE|hvv2v*{2l=A`%ef4vhT7daFL6DK~Z2yqBt>|9(&99TW>{Gk3f=K z0rElOhlhSrmS4GcJ`F1D96Y`gGS0vNevgsr7u%H>d~K?~^E~wGF)4OfoGI1t4|`UK z#GSRHVlf$oouivSGE0;ZhBZV+x-%rAlL%`94F%0(k7N8L6H+3W#L40ODsDS1Atbb^RMIIs`97ZBbFroy7nv%rHG3|^Pcv6*x$XxT%ktFWz3(L&&Z2iy;%0-q$N~Dn z+(yiHMoW?PtV>3AR=wOF{^J{-FURHQrY(U;T+ibd6D$_-K;vCYLC~oaY1^}as{m$Zb1Egyw4u^ zV1{feF*f-{EpElT;hc8V2qsynjBOy=9b|rfF9G%R{gxcp>SuqMEC+{&iy?}ppCw2R z?3UQoZY5@AW^&16;|P?xZ;5RnqR-{--q+}ZiARx<4s84(>WJFU$rhV+?d`q2lHf4~ zL{mVx&QbfN+AYl%GY#X`$VxyA2TFidLUtvHmP-m{M1K4bHWP}Wx*5@I$AhV%*6u|&J`?t5Mc$bls9e%}rQvMz8Pd+nE{Y?7eHKBVcTt3b5 zfh91_&>v)w77-k_=*|Hk7aX3sL<97zVhxuP+a#iiLvmc? z$gmIc{rvF5?yjx&tB2Su&D`f^Yx1Rv;=yWMdvJEUKM1u8Uwxa9mp6x9&3`vqYKJeL zo@6RI(a)Pzd%9ia9eHr}z{u()P2*Z4TZG{{ zMp-kf=rMmkMb+H8HA=uN8OCPdu`{C-{b@u@Pp~HkQgg#xxce-toltkd*o_c_u2%u> zd-(`~r62`;OJQ#!cS!Vmdh)H-cs{4Zm$5^Uw(Q(eEj{~Y zyA{h#zD*oY4!Yu!7+8Rr2>+x+jQ>8Isb=5n&}I_@Pcs^`P}(ne#BasLBCfH~LV!X@{q^ud!1^w*&`27Z=%T*V)^=dxjDPXbCKAbu!-8nDtjG;3LpA~>ahZ%X{KOu zpuJVM`4_K;tx@;3Q0)XM2&rzYLvY3DkFzNXPpO|4js*=REW8$p6J3cI}fTb0B#2fGc(= zvW^x#(drrFq0WDo)ditCcJ=neap4#Kp{O|8ranI8TcoQ}pIw$_%* zYsCRCi5OBr&aKL(yJu4(^()l+7BQ45bf0(3c-NbXM9;O*cPaG!OZ}%k(rLy=@I_=N zglqvjkB}$o_^IuZvRik=G@9!l-vS-apaxr2fDg-Z)}=8uov4RB?Bws{ZfwVjgd_Sm z-}b$uA6AE&6b6-k-%y;UNAd(2e3rltaDu_p^Ug4Wp>#w>`4epaj(s{(+<<2?9trsRR+Vb zwKZw-!4ag$=J(qim#@h-Zo^`OsM-?^T1u;QbvB0hbc-PbQ5{V!rUCP|C%}_aS!kIx zxQJ^)=Oz(mOJ)2`n@MWQIKNtuS60ggyG zvIFrkWtpuDI^)zWB#3IW0L5Co*sUr1V8NZCQ+${Mm2Cf^eZq_FAA}3H_fJ9y=F(T> zf114Tahk8OOV}ZM9|vV+Y-YdcZSmy});iGPDYQ?R+OAR^>2=M#%Ge7h_EsE;1SOJn z_l3Dn8iZ2Fs}z^-iZH@6=yc-*AwgWIrz*I9wg>c$>xio8YlFlilVwT>C;%~N1LVr^ zOtxtZK5ilfpIHdG(yW`{S@`6h#XSFN(oRC=-dPI9tSi)>>OxCzW+AZ9nT~yzJg?1n zlmVmT06i_x+kcIzAg&;D5bhH)ke!$+3n4a$wyujOROK^HyrBYkBII{_0lL_ZbV%|T zcdx}wPvYxJ;CBYAocUfmnhpxOk144h8D|`6ZNgF`;pMKpjDB|JBxL*aObgrR)?&y~!ao7hOV?rnm)1gz zJ9^Xejy?%qa231O9jbYzsT?6m@u82>naOqpoH_Z%Vu|&Z>Qo@n>Vh`eb zm`AwW@nLlTT34X_tv)|L;~1wukSexcn;0j+ZL{4@KQsPJw2sI>ps%Ikv3L0xN@i#e zz0jJV7EsY^p&>A|?kuf4tVj_DK29I^p#|6OMrRzPxJhGHsV#Br=r2n z2V76ZK{E2xcOT43gtu}F5`M$TcisF32$sK$Uj}Y2F_}Q~nD4O$)6Z`~u0U+_)e5A|_rg-X6<~{s37_Jbj)4#X{pI z6pU>9pf7fNog!!bmAjFPH=ye_KE!)vtagzzp>{w>oKHdDRqyDcUs;D4)Fg{K-x}{w z@ppSv@g;tHUfIq14-8v+kNaRL|1uCXV3pGCkPqMAh0e(LA@2buz%-J>!QpNbavK)- zS;e8Y#ca#FFL#KJtE+Uu)vxcIpq)D$OM*!k3+zF1BK|wy_z8X>U0QleL`rsAgIM$s zBzprtyL(zCPSvzUZ<27z=U{7N`Fr8)wmocCcs9}>Z2BQLET zxDy&Z2g@OkPb{qLOHaIHCL zHq<}%)+%u}yQ|ygC6MTel=j!(IJ-<~Ydj{elgcOMVSv35-HG{VVVFW?BUE+W-Cec% zGTn@meC>tJl=1(U!B+!m;lOL6tZEoN=)N~7<8_phwjPXPvZy88%MCGhp#qSj@NBb= zPaTM$yU#WQG)SpmD=E3SXRdPs%@$VmjGqR)#vlT;oUJW~i`%WfYaILcHRH|P?We+ztd6v6FXFuUNQ?APJM8Pn9~d-9HP-**j@d?VZOa-1@A z{;~CB8MtZdM|_D#s6DVOsnfx1(c*=nJ&=n4`xX#+Ko=VuK<__Reehzp)q48DjTQQy z#Qy$U46{@yE0vFceJ3vmBE_YAqdfbt`eZk08M5=2DnXJ`HTv~Bl2Q6QfI^9`(YGZ| za}=yjDo3;YW{;do%VaBO=|O*}^#iaT7Vkaxk`v&0I{&iPlq`%_DgJa;sOoXW1NT4m z|1wl0yhZY1+_IhU008nGp|%Ji7yHD47v|=*ze=vKe|t9VkriZi?57{rZnlV!>l#}% z^sa40Wt(Jcd>Kl#*%Uxixf<-osEUNVgFS`19C%D^c2M|SqP-I>2c9_Mv(JufQ*9Lw z2<{F-l$TQP5O>QP=Vjm9U6s8sbo}IF7W$iL>$Y%;D)jQJDr~LEeN1QenA#jEB=J|am@>&(=j}%OHBlj1+oBvI zW>Fna?_Sl_Vf`(lDHJXrsQA8>1EER|RLJ#ORN)#KeRh4|oZHjjNu}#DOPKeS<`W7< z%yqo=ePZYyRPHMRvEU?0<*WIHYZ-fiR>&OqA>1`+I1Z3%sVH>qcZJGNZ-KdK`IyE0 zVHdD+^ZVuY1$McanOUpE6$8>YTvG=EqZ*D1$uCEmk;S7{I+uu>*6n;j^`5=!ee1iy zcYK-vEA)@!=)cf#SS_T>b9!&~nU0UO>A|9l>vz>;$*lNaVoF0vUf6{xiK9aot78%x zMNGS}=|t?T^@Q{E5%dl<(>X^0RwEAG`FB4`B-=ay`x}mvI0cHUP5@wQcl{J}z7w*K zyq<^2OGp6@is;Q7BhVmg?n#lV2`C#3jwa|;W8LY@-QyKw+ZKq7)>TIq~)HHQ9w={FJ%zMR#NKosE z*Q6<$?!u=q(Ik>M%m^yjAwT*4=*3Gfez(EpKi;sE)90Yt)LNq6vj$p*>H{Zy99UI7 z811T}`my&&*l+D5?7~)tng@{31TI8_6S}%R=1wwz)ovO2B-=H2G z;_R<}H;(TIQ~R>(Cz<&1zmT0c%GrQ?QaNETe_3C#iv;Eyxv!V+8E|Z>Ws{VYKkG*mSywu)!PG=M!|1@{&wQb zWE7n#m!jAn380)ac3O(SR#L%USl0zIe&ZV9XFdv9%mh_Ul!bOYr4`Yr1CoB5ky112o*wSgw2O!J$mOw{fzt_M)T{pZ z-Rx?;V9G=10<7qyL-f7;Sz55SNiv-YPB@bNL$#_I=VF?3pSZ`cFpE&7aRmZB z8q0X6Ya|SO1}_k*^a09as^3Tk{!3|Tm(Wo0>CS{baKELQyNa7ZgqphxNAcGd?*y_O zSp#t}*wXug>r+kt`K$e8--0a*gKTf2jQqul^6Wh+cT)k8?LX&b75k1#8`G#9a`U2!gERl}p3g7^5e(SQ;sE)gJGm)$_P)%nA!lVT zxOjcrY6pN{aF?cCx|i0MOf!9zd;Vp(EBFr&E!1hy`S^_fCqSsx20@7Vav)!lNyDqm z_e7Fp!uAIwfq!wZSM*YOK!-u37!PY2I|0e3))uTeA7cUhD53qCc~8ka!s(9>zcb_D z@sJQMZQkAn{;rW02_%fFrsW8ctMj(gE(+vEYvb!bqwN#tD|ILDH)+W)4^5@IGcF1h z5|7(M?^RB^-)FL|AOAZA36{@FR??vT4SWoK8FX1?vOkoE%u5XGPMm?_p^RHW1&aNq zOkZmg@rj=o--#-C9p$IQLG=x^y6CJ#v$ygTG&6Zr52ZD}^P9ucs;I~K_3z)uToizY zJXb+bD9k0pyFr4gy1sE&7m*AkJ`T+%^P$&5J^tv7;kJeIDh z6U0ZZkUw!P9Xpi%rjOk)RUhnxo~kzqPK#@PMbX`u1lH#$`CS#=nvuQpEx(!_FBe8G zJ~Z*T2cHFBrw?UF?~D>qOYtb~cp!v|5BlAFbHdp2MI6c@#nb5F2x2$8Dbyxg-=%MF zZq--n#0{ZNXk_sw8vl}s31dqy+3Z>|Jk$&wdqDjGKb@ZRnXZ8N-hKBL62R)TfQeOo z6NHEC?*E}lN6>MqF0rHNV)$}SpR=~#n$afmQ0{#uD=Hc`1Cvo?M5TI z)0$DAjKcFYGgWNboFDBP`nXeAHF7IQa_z9+QC;TomLk5@3?c<~y_op77nduSGMD3zNl7j;E?>OUfD)HWR_cpt8Dkf;@jeAnic?oydUZh zh$7=e0x{jzb)d7&e#!sj{w)b`1*BShWAX#gU!j78oR2T1iW`U_y_w&3Rj1wZDXe1N zJqd|C>*TV7e;L^C5>hI5b4ks2Gh;)b(=384#&tE<(pcBlSR-#~vj(o1x#K4q>D^;M z%nrLFFT>q{?uj0Gy4lOc!Y`V*fm77*|Dx+XgPM%mcVDbX5tQB}2q@A8L3$zcW3P_D0MQW7ZL+`zJq(i6)O?pBN5aNE`_kZTh-gEZ(!iP*4nDwk@t-DCMZtiQ z)Bj|)S)&mEizAMw{84vFf>vCJgPBT4Q511I=pO|E6HX~FO;2J_J?=8|%_jGZCT8gB zN{?g3?;e8MAS`Hk;NHtRx1BZV_lLC4cy)R0Xx6KKM_HScsn!%RD}+?M*lH%;H`+nk zV54z@iq!ioA83q=chc7HgoZ*rpZ(|77``aoE;>A2Y>|BBc`3DI!8ASu^R9V?$W~>{_xj>xYzwDBCz)YV_{m6vDsu}0G#{cvoGxnyqf97ycBM)T%=E{ z9|^9F^h~xHFbV^!a&_~fN+3}b@ToGjpe4;Ft^K)l^7S49pc)@X;s zWC%OW+?z-$J!#k6G3wEOavNey7`Ai(6}8J%6rH0z&>$eq`(oi|toI`^#1aZpWs@J0fc4659ai9A_dTKF^PfnD5(Qj#;yk5v zfZrfc`911&{uJOYz|0kq=3xgS3TW?yT-~`g+-^2$&}$f_#_4+4*K4qYSV~1zInDoA zM6{JQM)JCd6voW*p+2U)$0>Cm70F%AmP8N*5If;c*42_EsU}{POHb8lO137L`{5pW zz*_BGl#A^u){r@&Rr+^E)h{EnO|>1AepD^x^HKp%2wJ76S4aslh- zDG)k8roAW?rLG)q8?>obE3Q>`X<9hu}E*?`!qRPn1nA;;q-koAkB4d)&14RsTw{n;Df5vdrV9pO&{u3;1xRlo`TbYX~0NsP;8 zqxuRp?&II7O^?=qf127bEX!V4l5_^YTj5UKA}tfZGPn;<_n|Qm^PW2;q5mk%P*;KX zPK~z#$WcsJ=;xL5F_Z!qMbj6KtJ*|?hSK4sVP;dz(>NOee{m_<+s0M z$1L0c4JL7OFYyfIv{*juegChiBqhNpnWTe%RZS4bLcb-%JjKn)7yP5>f5#az ztwaPYBXGmC%PVlcxOyX9+snqtK}n&?D(EQFFyUl_mG(shf84jM`2@?r+chE1Jyee z34d@l$>AxtQxu*6Wpo}E%*pVJm@p>uiA}yA`*X{^6CvB*@xs*E;6cWQAbwv{BO(g& zZ6rbRej1>4p3DMX(m;2~>eTGEIlPP!=*uf=FQJB1S?xGGpdoqoe@HB7hS| zPMCeshDs^ch+&!9&HGr*wHKJGSY75yllpA@5}p0DobF4MefV;H$I}8EXC)@r3*i@? zhZ{|P`Xie6lSe(-`N8r5^^31Q$sVpxVX~oj_`|%XpJpOFjBM!SvL5V@rw3hp16s)* zU?uY`csF(6YwhLKK8@+wnv-P+aR;>JBv&Bh&=#dKM&{#mTK;M+`Z(3OQ2x^JVYYab z6QOQdI~0#t{oW-6Vi_@fl>|DL)+uW6}0I_PKPY}vqW7ZQ5$B&`cf%zbkHqBOYh6jw!0x~ch!|u zEos$N<6_ZvWfR?(eJ0W-i2g1UD2Fo7Tzu&z^3GG3{riF@GXp17TfSVeH{km$wW`IY zn3j(Du&a0vFgx(rK;JK8`I8ZAo+;tfG@n0|h4a4&_K0-iuyu`&pc6iu6&$qJ@88gR z<^lKrmL+QtYsSYdRQ@ymoaS)lvycqodX%?dMdI+s0*i>!*p*{hT^mN+F#TuCD9Xi+ zg_Ndyqh*?1?Mgo_8>TFh6Z5~^MKIf&h4H`W*{G&u<|Sscht5#7Y~B#f#Cb+sH|zQ!>6PCJIN%<^MFRHY|O(;B_12L5m{ zXOLg2s$873kk+#I?b24*#OTpH828tN2eU0H+akSTLrl`?R1tNy68V0w!~>Iq_cb z&T@LL)PxZ7z1*uCmc;6|u>69z-G4q@{sor7KYjV_OrfVUnEIE19IkeAtiaaGKt{WC z15=#w&c*J1a}`ewR%0dl&95m%#SDih@J}A-7N4Nega&n__JCUW2^P6HxI7-7gmC%nJ9jZbuiI=n(DSUc%CTf3?@Uvg_+k0WgPiDH$q4-)dTjuHx z>^eV1io}gaL_Gx7gD7c-SsTL^zU*;5sBqBUFhf|aftX5P#)Y?h$jx}F9gdy8hJG>pk_P+wn}5L`HH{3dOuL?mTA*+Mlj6nfBOeYyoA3+MJnf6*EbnI_2dY(qKl>l`k4}ck z!1xF!t<@HH$0}6u&y$R1cVp(oZgus=^!`b0mRW`dg7AiNqFEQEmF*v9OSA2NHzxOO zoLV+Z4}WCF$N4&ruN{EL1Uml|qg7ZS(hty4;FAC5#{Z$OZx=3BdAEIs{1wt(brD6_ z9RBYTgR%cpVt^uw=7I1T4VPsAK4Y6ow+s4=YmN+>`~*o#dO-1CPpWY^TjKRB{$81Q zr(=kcL=w56iN0+F-kEkoQ-$tcHN$nKuRqlOQA{>v+^??ALaeC{zlXHt{T)(z2Xo?K z5Mt#zME{lAg@dGcR+218hS_RSm#F5|P?-_FfaHv!`-nD6zx(#cKCuCf&iqOPV3b450Gx~qy8P-?I= z7B`uq_Z7h98qNicwS{DVpxCelq5^Zk^ogkRm-HBKoX7RWc0cpN&`f0oq^yF94n?Hj zHIa1zVky+#Twze|ds?Bk##uuS?O*o;Z*nsYNIc1s&!kf|UGwa8?yG8w)30psPJr|< zs`3+UwC=SH-RJ5*E(LEMqJzg&9hc4N-c#(QbY)!popD@qA3mX8#3G_MR);T&QTe3d z;z}N}ca@`T!BzBu5i_E2{0Ne>(37vsKKr!0yV0%uv5)P}Bdqu>;@B~an1I!$!6XkF z8U8^#75%NMOzSl1g`sv)o z2?`3RqP%^>rYz{F`Sj=D|&%8ARZEGAS;b|?v6?nv}; zpUKkG4Htgzem>tI_>#4V8yp%tHEyk|Ur?>Yj9M8oO$NM+$3Z0^puLJoz&(y8&~%+G zWMntR*@+fpWyYhMmY_~(JsZ`&AcDW|t|jwgn&3U5Wm<7jQ96CSM-a_siF zAGdLb*%TY6_9c~U2n@Lnkar#TIgkB_0q5p0ipe8-HV067QBDNuo#-4;)563JC;LPS zEKVDmFuDI|WHw7W5YkJI@y}>VnG#mr76%|95L|bs_;rgd5L<&F{a4Rf$Lb)b^!IN^ zj$Ke|Xiw|qBJVN7(B68^t7ePEjuoSK?cV;dA99ST|Ff0pD)?b!PV>MzULdDYF~_{C zE+cQ~ge{srsaXb4QDq}&ngmDyhXq@71=|&Ww$)qw+$LC>`-6bh)$e!aB|icngX(mt ztPJoe{#tNl7Llf1-moE9Nuyn>>hp&B@SfE-zJnv?ku-&q;%Nmg$!8Svrf^nOq!|k0 zi3K33V)n({YFq8Q;nktxGX~0A`WP0BM#R)U_dWQTRo=lR((CMR;rd5UzbQ@1wQ<#_60-skRt1l9cmLL8?MK^%-lu70c*p*&jv7EA?uYXn8-p_K9u14 ziyt5rh5Wd+>R+ZR!(g;6Lk@rCfEB372YFLxGkW?Nc9F@)s^c^E@TSVFVemYuHVLCF zB(}Y(u2-D}m!2aJL8_qJR)mmFZmEmtihdVPqC(fJ-DAnCE<7&wd{JtqYQ}8Uw>dN1 zih`Ms6cr3(1F}Jk>9)*96Wq1nQ#4nPpaZ zw&E=^6%i#snY!p1Y5M0sej{u9F+zAdJMR z!(+-0#m3dchokVbv}Ww9tpgH$cwU@=f%W7d95SlJcx-x+ihh3)VGFb>P%r)2rRDah zB0n9xQwPD^1TqRD{!yH5t)s7##4bu8HZ(w+j20&9@4`&fUDG|@^7vKke@93Fp9?pvyUb3PRm z+5K^B(2ew%8&VTo<~5N#7A2~izY6hB--i3chsc*MY7p zyZf`ut*G+$*58bACB1Y!3c-3c6D~uqKEoj*C5nQJ`~?TDd0nJ|KS6TjwsdfX`>?K9 zS7YiSJttu^>k1Zij`2O}`~}31CCQ;Zh`y5vk$evky%?jn(5ZSeEhN zi&>Qxlxt71W;>J};Ve$)18GaU`~{oZ6h{|n?_xRD;M}EO{rb}pM&=T9e1=ZpL0&sk ziSg!K`Iq?kU05Vc30hPa9XVFLX>w6dW+1&H4lapbj)Z9Y@4OrW&$wLm)iknZmpe^n zhhzmL?RlL+R$+|FB_C%e9Q6+sv$~pLpv&99<_c#O@BjGv zxA0I3(7I!`vR}HV>*iu>Lwt0gdMtI32kw^cFHi&3yp`?)%KNQP0hsQeR{$++4Hbgq{PHwJ!O8bV#MND zHRp>@qTyOz`p#L}j7+$ql9jM>?&2&)o)DV#9GC-caF8J+d`;vqnEVh%k2`-3Cm)fz zRRuby-u%hl`8!;g^xCgHmKap5<&9sqXvW{^TXdke7cx^Sppp>2eCe9ETchIv;usJ| zes=J&>h!xdg+$n;dhKgz8-DM1bjqId)otzVAJ~peuu5aiLcAb)cQX072z3dHFV^z^ z*slI_syIcd$M`_HP^a_1yubjT_N9al`kSOz7is9-qb*M1j+(f8a`ja{vvMLCYbxxt zj>nMaX#tw*rHyqV+b68IRQ9|4GD=q9p6fmd9W~B8ZA-2aqh-3fP-&|V$yAEK7;)tU z(v0YX<}TwSGqTH_4Ek3hjC~#_VJ{GgW9w5DEzV8-eeDz);@f zMahJk(!R|XNY86ZTvx)f3%lKSHjhTZ}H=MCs@1r_<5Sf4r;q&>Ex87YH20W1jfUMVKmu)gCen_62ZF=-e(!x?7g z`4<(SU5_PJq8zs$X_WZ9k3KM_b~4h6M=ZrdDngJQb=|E+UIetFMD|SR_O0A`CqDHa zL-LlN(e|6PyY}9kzpKQtmX0J0LFT5RT=@#oRP_-2g6Xfj(g2!U*;eM$k!_m3F|G2@ z8ivi*3nE1RfN(@aamyy)PQC$7(0dGi|*Qdz6Hw^)42O)wfB4mJ)sCN zpJS7^eNA>WE3I(;$py(X3!A%!Y4&s`E0zP@;{Y4L0bwOw1yop#y2GJz6O~t+Z6#79 zeZ4->AuyeYr`6Uls2)MGP$jyCbJ2b{>otAMg7k0#56q7`Fjm-UDBv%}jgGYG;~YgB zs&&3Qs(uua%qcs}R=p|Wlz~0$ziyN*ace80{NferYm|-GJnpoWGEro2ZY)1!PyL<} zC!!{>@zOR_l&?EnpU_Ia$(2Za zHMtUz!jZ2+_uvwC?p906mz4EJ6Pc4vjevBmrsSaqm+Sg@ZLOlyYGenm&E;uzM69!K zJz-Gl*yo8-H;Ik?q@RdiNLla4$A2OICBD-=?+bMwRn26_N_M$YToS+Gr6%!Am59qIA(J`N-{&m zLaV#K!L)G@Oh#7%SZoYYhAy&Ln0}VB_5ceNdwFtjX_1I)>b^)MU0uA5ct_9Z;|(PY zG|}QCt3$Ph3gi#tM=X)B=V@O)A?On|2qvoU9ZpmS5gds3sgNaAfT>@HZoPnmLNP|+ zFa5IPn0$P>Oa`I|nyZA;5Z9vS5|aoP;YkR+z!9hDWK{^Y{^$1$F$<(|2LiEK%9UaNkdMlVwSLMQ^%zEHLc zaYThYmO1;dz#qSl>DLY4xuqx(lO_3NnDFi!dQ)(%cWednFeAQ3-`#c%+6@XVCs_~^ z3yB*e*w2I!(R8ml%g@X=!gt2Jl#Hj2PR^N>j}bG%SRvYX4RSd(-I>vpfcdmr+^p?b zr`fYjAtCDj+jRH;?K21~VyP;Uhe*Hl9JD#x@e7qdGiP<0M7o4;?m}`C%{t_5L*F)X z1TBPEPICA(Lct2Mv~bhY2d^fCn!Oi`?N~*JOCd{1X+T!+6}o(kMmreN=PRv6dm$gX zB(X+MV4iK&15n~~Y81%h$^+NS3-@dTNvK{3r+7xnjk6%5%UkS2RTRidS z^n36P)F7WkT8>0u9#$S*2c^8RlPyBFEFz&5C*9~zD5hdK2&OR3i?2$}YVdY# zzmv%zh5lIIueP5dvGvEYi3*qjhIBQvH8|zMo)NzwF0zUpf@lw}8c*HMeg68}5D3BN14UiBi@%kPB+{3`R28 zBff#KkUEpei~;Tgub7)Fip#(u1HVMRSrbbMuS_C4nj|JI^d^Qf+>FU!8zGo6F^8kB zb6M2p`KREn3^y5i#KLQqXC8ZDi%e2J5ge)!(&0?+MV@m6bv!{q<2oHcQ6P?z+YJG@ z%ek{H@$aIjsB%041PQ1WPPP(Y&=B{(pqa8qF z|3W;meGlMHcuz?l=nb3)MaTZ5U?B^sgQ5i@Dzn40+jHl3NDX~32y2rF#;h?F9a&l9 zw1Umh(pc4L%IEK7eP_)NVug#CJ})u#nKBEO{+pLOmkat7lMRhnWV5P0xAfUEH#zhD zqE|iqf+H?nE)Lk41&lE&zdu5b{ffPUtWC5dnprLDWk!gLW|}b)Yhqb$ zXrv`S?mrE=Swcz-0t=qn2Ph7}{OA0^(Zwo5@;hrumq-Y^7^^i|aViU{G9mWu!a5fU zOpWA4zf0)C%%%tY!Nm2_91f)D&j&?+gt-zYsUH#paks3_bIwiogby#)nMH@Ykx?=O z+$T7JZ#i!t(k4~Ta=|4>yjWiNLnE8nw2~3VXWdn>$00iAk_UPV%Fn$NkHLz9BissgsaH z8zTi%N+C{A*IopEy`Qk#P|GGeA=XS>4PZYPg1HlSWOgp$*V`pXPo`c(6`?nd$DZB) ztyrpPq{r`eIYv&ema5=uR=~g zzUhd3^Ib)oCVImF@?o5)umlNY0GvBz+861GR=A?Bk_12Vp)U?({W?AgS8+_wx*L|A zhWq36-m{rdAjFxWJLxz>?1MhYs_qL@-}YXYVPqb1^w#5D0OL&b&ex2 z$$I-4UK?i~oQn54o9dW?i~CwPKb+efWDUmcgWW%tnEjkn|CB*j6ay!qBf&zj=MAF( zW@qmHEsZusYOGVE(UB(mpcEw(A)V{p~H`DAS8$o0U_HC+IT2EybtHfRC;+$-ya4 z@LuWJB5>{$5L7>t`0yv4rHBZpf>P@Tvwl&3eBjKW={Wp8QU1@6_{`(_IO|h2=+x|xkEKrXiTvd zd?50-6<+VyM!pB1fY6humK^t(U=Immi3L8{ce%W(`WBpNkrlmB=a&SyC(g6qC9CMq zF+!C3_p5S-hJnB)At~;-{@j~rYc`G=YG?{Kt4+jT-?&$nnzHm!Qk}GQHjMrR#{Unm z0L(upS{>xf&nIWC1GsI=qGO$mE87X3h_nTHErjD!$Q(2oV)q}`f2kHAN{udC3A#hB zT!XTZd{8t^Y(B}j=T*&4+VrNJ85B-U&ZDgF{XNmEB%~<$&%lGFAJvL6%?056N&}UM z{9_|Ufn)89f{I~`!!T4d`^9gEI+0RTDHUzR(}CWh z9Ur^oSvay@r%|w*7DR|RNB17SK@J#g)il#NssgHr35=(V<3hEj#XkyHY`08~2xu}f z1HXP8iuaCay8It&T{V7u*QZdygq`OMFU4M;`oqcVSVx?e9+?_a>}XV-ut-H_ao{)( z$tgW>p11jUTU&3H@9J`zR)F&hEN$t}6fMP9cb}#Tx*d2sRt|Bg!18p%zdEm=UHCR# z0zs80?Ryx?HovUnNU9N-X13Vkc7F)%eqYNeTpilPMmTX3ZiC+M6`bK^AV?rL3YKRyIpeJm1Ej%B&8c`#xMgHc!XSrQ(8jvisMBI5RFi8IxmE5 zxQWqCQ2godR)+SDy(t5ulJz>_iX_u=;vM{~J~2Aixav1uiWT&pnZ0e|F?})t{RLRY zr3@4U^eMLtYAJ4+_P&Z)b_E^BLu>{N%9gab8$>r@@U155MW43Csm z?oWJkJPcUGkKs>RKnz4PWdci(t0(0*kDf|F#dMjLACG9?)$O#R(T9%bN(hy)qaEo< zN6}Xc!Uf)XsUri)f5^{`R$$64KT~o<+usZ2NI5L7+McC#(MaZ)7XB^5!BTO}v%;-S z+!wz+&@*epnhCm%b#OfivG~Gi;G+c8hUbIZHMnNioQ&$-0dST|S$<*a zRN~&-QmFB-d|Bz0?y@+Lj(%nmjhSz8af&MKjeUjc7cZ{H1jJGk6=f<4WJiPdo{eb7 z)2Vhss1PpnL5nPK0WEwLX2?l$)5IqHRefS?E6hqDkfdft>FhT(d!08E{|Ne&~oA|IK?nECzv^8lh*LAXQK9(Q&~4)Hn`)Xq=`s&#$9 zk7(9&w9&$8AIX!PVWx&jeD0S&d$L)hp(;Gv+d!~CNVE!zgkYZ zu#g^1Rs@J0efoSXXPE+MAvh_vSaxd3EYgRnJEG?wVdBJlctD&jgtz%cSgT$pTGjqJ zBu;mfnW-ZewJIJ3#@yC1a)BokGcdq4O=#q`ynu%2mqwa_~~ z%0rjWJhq@RpMO&yVO289oE%KY^bSJIfhrOT=8FeMd7{|hLos$E3SZ5D8f-OYcF*~X zA%*JrnU2BYBqK$8CY+XPW6Z#b~be7@V>mP zA}?Ac>!|uDHv{aLjWj>tio-anOqy6WRKaDxyF+O{dv}c49LhDbiovvU_jFlwlg*~W zdMm?ZGpui1Ig5tQvV&{vK%$}Wb17Z`(40#u02)ztdyz?t+viIP2o9o43u_uU$s|pX zw~~&xBJy=@lK1oI&#o7XeT}eZu3zj{vujfm*C3_qJJPx2(M7r=D4P#TEgW!OIPw*> zj9R?UQoTRY)wU=hTz~TrjTSIo6l&Nl_Twfo1&MoUF=rU3|8QJ_Gux!G4ZQqqoS6Qa zVt25rDu#>xHG%g0Z9^dPGLPyOnR!)0XfR=msQ=nxr(0)Ji&nj1M^>p|tr_EZjK+6w z_h=fmh^}L4#dz&}2-rMt^7;KFl*>{PapR6q$&dBO zp5j`YcXVyww}Msi>E;^rBh8lg@dwsaN=xokQ4opqR4WvRMiX?2mdF#lvpV zsX#>)XV+lrNgLLwn`f3eUzHzQBN=`La$WHJ`F?;V*)zfpzVEY9Y|C zPUiM(80pb9hPrrs^aTljoY*V{GnKIO)=0z(1fzu{H-0~ycoQS%*8NF43yy$~A@Hx8 zX-GE+n=pR7_t#xT|7E6q@{}V}Fk8_;cq4BgKaxM|225z_vK;!^{eJFu=A(@8yYAA?cry}i-5XZVDLF2$=Vce$o;1F&Dao;w*EQgOi&3MeuY3?`Qu{o<$y2;6!osit}$EWe0|97j9hQjV3u)C)Lr16j9rQO)88|1e|2Indd*-)P|D9-d+ z!kw8}(Tau(o$Nw|mYwWB2K6ZpH=ZCzD4`n6vb>EMZy__v-IWskDGzkIE8p0+-X7)& zgGdA~T~{h-hd%<=gob?GVUmL~Qe@9X+~wE7sDj!AG9ji`A?)OO!<#9PHl->?(`uss zqo;&HK&-doax0?Bd;0|EWOWV})!2KMgstl22KMxcj1_OZ4zV(TlAwpv4s2q8foq6A zaQ7U4?o7akU1%t##P4F5>E}s~Ex*&S`Pfwp)Xdyrfi*G7b6F(^GfkW$&x1LAMa3GR z_&r1XP_!RbmslVPo9|jRC%Jby?#;@Kxp>SfJyWe=H8lF3iSLtFbi3I?HW>S1%S0&Z zj?1o3IW0C)7~Zb;fN#tXQ9!7>V*qaW^%q{F(Kqibwin5F9dw@Q&C^z9Hhp+<@`Eyo zWD2|+dEH!ys_XTusOB8|!uF8}$oc`g!)IopA^@Uy6m{G1D{@Fkc%Sd+f21Nn07Mjs z{znnj8qx#8=RSQ?v5~o&-1|f)+^jF$4D`_dVez+hBD?*N<^G44h8-w;af3cn^>kc7 zxVs*3SqKP0w=-`~bD(w#dCx6PUfnws28F=y_VqvhX(QNI`j#5yP}9UtU}6JVThg0% zX9*-?9qf0gqo^xn0!?HbL1MbldGFR&N))yr&`uW7#jF@T>U^8{$$ znv9lwi{Dq zepy>E-2U9yOGH=+euqdv_GdnRG+x4-`KY0B;Yi*0m3SsiH#Q+M3=pzHD93zqr?BX# zXUpdbSH?>+%Lkgt@Y@&2aPm_cWH1@5f=Tk>gZMlwUT;~rO6bh_cBolj1i9eu`>QU@ z0up)~L9WEwnp9oSh8i-h7pOX$#Nn31zpme8RGpNmD%^K&DLfU)nccUNCf)q`Hb20@ z_K?dQr%xWP{jiG>%y?CM71keUVKgCh|8i5ZtB4ch&`2J6{W{7eThr-Q@PgO0!oxv7 zrjpTJtB+IU65Dow6}rA{OW-?>nrM*m zUs?>U=BBP3<%>}W_b>??T)VaKc0UUl*9CSsjRNAE>TdO-q0~J12uDi1?Cfg#n|&p) z{nmDgPl}Sf5Mz3>`O6%yJ@+lh^xm;NU}Vwlj=NMuJX`KO^UBPvnjE8~x};ar#8oXy z9t>!9edo>tn92WCU8Mc=DZsI#t9@2KcBu&7sXY6{%<09Gd7&S3J6qZhp}YSmEPne( z#x2P+^Nj=6vQ*jx+f6~1G4DkOT-5D8qxWVH&o8?#;&Z38qt&fB3$$~4`+6oMaBUY^ zDr&J06k{eF-;6q=3qNC+P4o}{-at?LIMT~g@5>3FkCZ*M8j-$t%{tP3dmR1CLVgF6 z0X{k_?`W@G@~5H;Z%;FPIqhb@{xU|Kczg=46sog2))l&QpKRFo;mwh34&p7e%D}`S z)#q;hOMU!t7K_Q{q%Elens7%$%@~@Joi_%Kd7^ZE9+ zzAy;KW~5K1yS#4g4g794{a^*{S&~lrV%H|ZJF5Ay7IlLO_mEneIp}q2;DHXsHp?#; zx_SBNTK7%C{0+*o4|$;AN>8T+ODB?J#z=)ifo7}QcGlzX0gfS@2Csgo)#)dBGwO}) zt~4F|e*HSieM_ep<@RJq0y;n}yr%7<;H}i_uq%H2dg0z1$~!HY@}9jQ!u||6BW(37 zGd?K2bOcSa$NC}X58X}a!$E!R^{iP5<;btFoGty51G7gjN>6hLV`M5%EDDKWJaP$3 z;~@s-+RL2fMI`$>`m98Wi#WBFS7ApR>L5hk;dZ6f72@wAly23Z%Lqnj`nyM=dN~}g zgr8gW)T4aK1JE*;kY*d85dhre?c8@8CyQL1BgbRRGwo&x)mLnlI|KMXIKMTIe|bBA z3LV{1Ex(^%ZR1fQmMYiZJg{gADchy~Q0M6qzDF_agKlSo#Lxik|Fdq$>=hV`-+h2~VWOpm_fn z;OEDMD>MX`pEOwN4KJUk*Fq-xN>RdTU&w#5k4ldJh<{FvapsGxr1&Ea4gC?grGdUV z;ilWz#w1ZzV&*B=4=TO{<}QD%Z?sRyVaUOPxa|>S6gcIgA&n<+1Qt!tE}`ypUt? zpm1?_zuwB%z4ya^%n&sFHjd1dg;ZA!H~G|-Awoe*m$b><<9M0$9qvpH@_TYek#6Qn z6*!v>^9p=$KY&%|=PtGEa#*p{P1OOBS)-~)7M>PdMKbU}E+?i!5I$m4%_~DF2O2vO zoxXKjY}|%#OxlC!f19l_;L>u*{#>DlsCxIH80VOxzQ7ZJk}OO`U#)E6-|Hysu8?83 z{C7JVk46H;fD}K~PAKyxSezixk!na2zLBPURe~p&XR+-%BDm%!@Qs)SHX#<5Fu%P0 zUJT1TB{x8}k-o5sb=4AL6Y^kYJI@nEe(x9@%FHRwnFUcoZ0E(7kby-c$_!|4A-|*| z+VkVX-JP8@O6HB*K7NjB7*4y}to)>=O43Z~>M&zeQG_PW38fm+)vEW}rPSn5$>NDF zbI`B=xJk-*&`VWC|7*&FZvnE@HZNV|8=o!>NlAo}+TKHKV& zTEq8e*G~8S*P6P=nw`+09NM2h!1%1P?KhNSpMt8HT;yNqe0pJXL&leas*4YwCi-%-9KC%=j)wtvw}xYOU!r1pgY4`n^|YmR2$xU6WGmIu1+Z zMhTh{x7$NXWH;n+d|v)c5)-+_rXLRdU5J8!nfblZ(RN)t`A6;`8z-c2Z_rkz(lZptO%L50$@db~ztNZDC6+AamKT*)P)kzK{&?jW)9!Yjs+L|rP zzIKI{LCTc+rV*`5O)~Rx_Yh4sOov^*vdp;^X&NVqM5mIHM zNV8vG91DBr)-6yh@q`*#TK!;nvhX6e*k^e833GUidyL@MA5Z9Xm3w4QekZ%m`6W@j ztdhX|5Rm(I<$lbk|4(b~$`RyPtu7ckZFQVF`aVu44e*Pn^#vP?1`@;09FMgp;Ihrz zariUwkhD9am7EHq&-7jW^UP^{L?6#p?}2LNhMAqFzZMVo0Lut8@z7zwTBD688(y%6 zxmc_kYCWB^q~egBFtPkc@$SZh9Aee(9@G!m7Z7Qnyy?^5!p%#(M$kR7{8M>TV^J@7 zK^2pLZp9*2N5sW zahX2pXl5<+gs}RsV#V8g$h=y(9VxR#(_TiIA6IRXU19mTPK#Z>%PxwB-?XjPf%#@A zZ4(a>VhYryzvi^og#;U_bKcT&0i0?#nWx`|VW(7ULa!{m5OL(WE_n;v+!a^<`F(20 zXP9ci0MAIpd2;WaI2{I-d*K1X(}fUgV7Y`Wt)U@F5hGs@s66%qwJl8?YE2Y-wn*Yj zC^jF2Nhv`qq*YW?m&49y*D3omZf(^3SFr5KBVu2rTqOT5~ zd~kRnWNZp5#|X-{cs%t6AJn^4I{-)sY^Sj&8+yn8SWNCBhI|V#jm|=BNa`~M$o)UO zIHvyzr~eyM|Ns1eO8}4T!)HJs03mX%N8>yw5VLVZh%CgT!%HWu+gpTgETqjPnEQT+ zZbfZ)cLGDtvA0Bbli<7k7B%DbmD6f}cYP_utX`L&gGPeX}8PqFHuK z;F{)*905VDy$FD*4Vc5p;tea8?&vB!AFceE9{O4Jykmcr;evc#8b%oY3T5<4ymVsY9F%d<8j=a+%3kxC&Y6l-B=8S>w-bZH{->zdXG?cS8ByXHf zR8_(m_1Z;59Q;igrUuSd)5c?c9rz9kjuVMRnJ{Z&X94k`eMFls;bT00R&<)%onJzT zb^5%qgR0Owj077phr{9}Pw^lb5PgHd^&%$2YL29Gb4@4i zjf|i>Q!WcHU|lN|k595Btx8WL@l#zuf1bXH$H%=}-g@}jWDvr|Cq`fadas=ePBC@J zNiaG#9wUQDcP=u(qJO~xQx!$t9T=M7yo(yMWX_}S$)PMf*Z)y0kVeFoV;8$k<*!wO zg-eNnc+^uo>-HL0)aSOM_^-b#^m+Zo8_uEmo6lh1cW7=H3G#nZaB==eVM^*CBJ+G) zOo6NC+YypdS+ps{KljbB4cEG4QA13*3ea!$w`b;46}9no&zV;aa9ERbT2a?2J+XKc z2T2VmIDbvjyGR1d60_U8E$GV#tRa6x_J%6 zGJG>;zTvgGZ#))X#w4V1wtZT9IA~XuV8ye@okx=k>S8y8JkwIaHHHn_XQ2ev5O~D2dnK$7g>^}-791ICODpie2Mq{?y>zy({N zgqBSwoy9%E!!%`=X*x9N)1x2bf zkn@flkDB|YM9Cx7NvS9j9w3!sd=J^bdUGST@^VQ~WNn}5QMw9T(*b!r+ygmcD z$(X!R3B|=W5PcIR(X6|!t8r;w1{lzl?)W-iRDahqx*Rp1cS=vX-Ynznv{nziS2^+O z4ehI^k@Y2JpgM>K(Smxwo%Ut9`g^U~0Q0?>dsg!U55~UQ3HiHc98=%Y`SuRDG`Gg1 z9$}h)`m4uHZ9w;&MeaV9hX#`r9P>z` z<5Kpcg1Uw+69ksb#$^9x;vpZ(ZWy4*l*#cFfIyRLNo71i! z>eymxCVy`(K3lH%tv!8W$ib8VdWa7a2@i>CU)owF*1Y%RVo0g9Nb*+vIh0?ZJuQ5m z3ndCdgOhPGJAC*btq;pKra0FA7hnG!)npg-fr3~N6%YXdr5F_i1p%chEh^Fl1O%i; z>AiPCqSCv7RDq~;5F))3=^dnZLPGBeB?MBO=l$l+-1W`ed;fq%o&{^Ma&q=Ld;eOr zvmH;@E06hwz8_4avgc$+LxLTpICZIZr*nD#Dp_s(1>Uv2vB+yzKr0;ud;KTZJ%-$Q zFAZGr9mzyuk8^Az%CQ($Mw@32iW}>%Dst)O0Op-Sh=#b| zqNLzH(V=(1{c83#j|1Cf-;N+UjA$Dw97Nj$$CY%Za2CV~r|(r)Rb*;N7~ZxRW=cc& z%avKKDsNGv$>L?LSmZT(bAcK`iwWm@4Z6)tncsn0NsY$$B^%ehW*7PO%xoQ$JQ4o| zWg{XkOK1XYHA1U$9;2}Z5fHv(dw49dNs*MF1vqTzDlB{!L>f-rec zNFL%m*itkYd<9C2F+oQLu*EelGcj!b)`b7sajiGa*eY0plQ6!UAZeEI-kz25~+NN1?pk9_St;5`U@s9Zr#;3 zzLVNpe=SDQhc_6K-R6@#lyuNeIK&5??1J!fe?Y(Y!*lH(EjNZ6PVMJ7ciml8T{KsC zfAzTr87*=Whf+P_p?`_1iOeJFwN2Vv=GxVa%o@MAiGBLv<_m~3Lf^gh18%=~4K9B9 z*!ESEtTmSoe!7W*lIMUTW}XbH%o^$s zB1uO79L?@_fiA#c)uKiLrbwA7wlb&)@#&&i73Bvs$kz3C^EIE+d z%G=JFPG)Bxgh|5s(6u7*xDtY2(vo=+&b#HVU!q2IfyEmQXE|w2#A4T%ej&Dtv30F~ zRt#s{s&6}8Oy1q+)K5nAoVgO7{M|=c?9aG%BdX}SL<-0grA6fja%R4!c}77yQ#ocri;^;a6I@cG_u8Odck)!ErT2%AyR%UI=@wb<5*aL2r@!X@Bns*DGSGf z;t+IHE_DJi&RWVT&R?>(mdyoOJlC%S{F@7+meHl{Rj9!i0x z#^}kPsqNOTikzS;jdY6!ypn&&P<;?R=c)_m!go|n8xp^F-)GAAyeQEiZ_8s1zE^pq zU|t0|@*IXGKfH$;;})qJA(tB=?Rp|sGDn4&7i-2@UWO}Ft)>>Q-^{Zyh+sF4Q6sfZ zu}RzczV_sQ_o^=y)nsb`7Rbex} z>bjb`GW?cO*23(^)QP$P)yMiDHOhnE;W|K0Rn4Dogek6Of3PTSY>$ZnIS|LN@`GVT zBwDgeBVMb(%R9c-lu_6XGW59rp0mJ+-X28=<9YQ>fq7n)7C81up+KZaH;)r~RxR4r zeILIM9G=YB;Skt0TtOG;^1L6sEdxq8fZNmi913VQUjOZaczFLs*K!oa4W~152d5pT z*DlTIox>K97XbWCn= zNa%Pxeo#a;&y%|Q&Vc4@N-q89t4|v$>ucbw_vzEw!S~-gL<6=^R#MN_2GI;zT42@< z?fjpW^c%J7RR2TN(I8A5-m1R`8zEWx#rilMcu|BEP#b-oXUjNbr{C=2EK?7~G6dPn zdl(i)PNPWtzm>?^)GPC>R4xG1PrCw|)%7|iNla7RAv2mZ|7R}>|2Of!@E`yQCyLOv ziGEUGH(@^PEpiZHs%XCsKD+*%X7QXqiZA&#o_0MH zY>lSb;uL!{G;3Y{;_ebJBf4j*@na6>-VNKzM2a?uO=ncMu;Fgba(3-?dhZXngcmdw z0SE4W12?&5c@5kAEsB`jLltj5#U)g2v3H~doJ+DMp2Dm4Iu5gmz%_Y?M}kOqFW6pm z&7tW37%c=y1lHu7q~)NQi{^IAz80|=yu>+JY>T|?D(_y>X#BA;f=v0#?su|sH)&Zp zPfV~SEjMX+@a;M=uTb>|LVGTFrqVfPa24IUNQokbN;=p?f~{P#%x%4uDGomLD2?|dL> zv>Zjeq=qNyypbzq^SxakUu+V~0@JR5 zACS0=4zy%fW*Seh!FI?-X;4{#EcQyR%X1L-u~L^rC(uy^G+zMp2ON^}jz-nL9cfAO z9iOG%!>olDn@s1zFp5`nD~bYnNBR%b$B~>q3)zQ(et+vB!fAo}OuIbo5z~hFFxwb+ zqy(&=&FZ-~9r$2i?ArI|vR|eKR2xq8gYEld%mYX zJH6QV_MNevuI*mA&>?B?`G(cV%JG@!_1E&8J;F4M*sXcgA3p_5p&a^#ZbH9L{8IY# zhq1>L2fzBs_2dGn=H~H_Wv5@(J>t8kv?&5k-m~I5HMt)_37>cr87#^PdrGq%I$JN5 ztq#(d^`d`!wj!n8<)-3I^SL_iUI?#dFQ;ztT)E4MuAhz2 zYG%O1#ff|mpU&<{RF*imRkFXR_=e@VI}4G}a|+$T1*{4`AgF9WAwO zB025fLW?z3oQvj68{1i#WWY_|!Z1XGuO-qypc$s=W#!4Uo*RO-gh*4&m0u1P#x@T3 zeJAqQo%CJ?xHa_|+h^>LomBqpFro8;HIuyn~$sy8LC*LhuDo5gQtWqKP z+@4M7#+Irp3pFv%b7pxjsMJ3_k#tn(P;+QqJ+l14u*h3qb9Gc5(d7J{6+N0R5K&F* zcg0JWB`jp4&Ei>U6>uj^O>f zPVN68Y&1g@f=sv`dxrsMe9eV_gW;4MC0kdZ z;!H1NYMmW@`SzpdR9k1$G^v9Gj$}!) zomJohZq{atrW?k}^`(9#L(VV9)g+s%1iV-tZ>DUq*PX(b(!kfv50tC$!rvcg+QeHHA>#FWn*+c(E92mweWwms1C{z;T@$GO(zi%z#bBhnu3LM)+bl<+1H zcK^~KCYH6m0Tx_B|EjijVnt7g&eY>287(D4no8E|;FNTDF=}9@>L-&rPL8MK!L5dQ zs6%e{GRO!?Av0Ue@rBaSwdor(GN0F^l-IxWah`IbY+5aIVt#Nd$)`t$^HyG^(w-5-Z@4|R z6O2XOBys@$d*7Q}mmDWYyayGwT0e}xKj*@H^Lqjt6?gh>_lUnby1F+3zfuF@QQ-Ac zX$Req(_iM=-j#hf1^#_6V+*SmqWhS^ShL$@ENQAtXaEYJ#q_+b|CxK@V0m7nTeJF8 z2@IBwU9Ur&rk~U@TqbXeB^oGn|5dmKbq1hQ3~${SOhC~ZE6TK)=uk1Oa!t$fCDok3 zMR%dl7|^?;tE6{L0Lam2kzo|-?{f&T;z0CIM-;zHk(GJRImVf8{aNe!HJ79;O?e8ovB>ZEUuAzk^*G%>_`+XZql*iq}elun@Y9*|4Aa zPgWXFeUo~>9-VqB7tMq`I#x*rumhdlCbN99{is)vp4!+^{57LZl7!b->FDJdX&AZX zd?KlaWO@6Ta)a6hoY!GmM3uPkb{TUpj>l1I&)(54NL)z`*tGxW?ePEMC%P35GP^)4 zXKjqa6~DVj{n77?(H$c%l@G7_$Z9mV(S$8yc26kzaK@;Ox|7}KP#Xrf z*^kb?UtNxheoeDyOVozV+vLx z`?kVv;P!(3v83Va4lDG6oIamwK3n@RL9K@+M@oH}iS^4~hNEeSQZP=f1PKte zIH5KZduh=o+UFs?4|!ll7Er4C#HkqCZ#f}*{EGK2r3?RmFyjA^y#D)Unn9!fKkh(h zvIM2~h-y%qt>5SyIgLD?UzeE9)V)jMuz{dguu%{@RSq@?t_klF*8a2jFja93NxBkxDcj-$DpJvMi|HVa}!TzKP${48wFEm-#L3)VmF8HA0HWl=-{y!g^d z7djly01aFQhHi_3lX4F@g+-0RlvR>6+#j*DuKFW9G!czHw5hz8K9*wi;N-!U?CVue;UbdTh zhZtI7JU3%Tj3PL0-l>jJx~M76KEoLo)hw?i=KnpXgpx&;#-MIO{fL1W2>TATYr=b1 zVHT(E&SlaoLuW|%@C8Xof37PwRI{|*+oWvQEF%(4{7jv^^Rb&0f| zmYDqra3%VaM1Di`a4j%&er}NR&f~>B?PnEYV5Y8S%T`2ncn4Di0SU+L6EtuNMYbF) z8n+{?A`xGFWZ86QcBI+J4v4g6E_Nsfe)}b{-Wjil0d*lhXLH~}Yoak(db-(~Tx#sT zlfLX9)SoiE+c#S(VrZ7%UKgD?S#tfO%?TS`yh8*SBC7bwoRSUWtig(S`dJlE2Yl%- zy;qe@3999^_oJVEI6&m7m)oiUf~1@}R5)P*_tSo(l$#JxtX+5To06#9bF#>eD$RKQ zKlQ{7!~$FjE)UGT5OCXsJbI}`a56mYT+RSQbQ4tCGejlsCqy^3$k#{7-?tkco`L8@ z24@QqZGXc7&S^@-7?ZU+ojtzdVV=CQ3###@z1L7KWju9E#B>-#Kb7NpESOm1%iOF5C&LR z!1@jb(;TP;V9)U#zS}{C4(FxcL8GooxY?!|F2YHS}TCINz;?{N4(UC-teH zAQQb1({qGnqV~@PqBw@GOM?|t->V-n{OC~>TD0f(Eoe^s=^D1WSMF_Z@h~gHWW3}v z%|0Owz^T-%zvQc7LBAktRjEyoB1s6=!>O`!BEKFDRl(XfnPCU@!K2pi`(0V3(KAhz zJ?LE&<QEJ{(avn)?S>f7{Wd-ceWQmpc|8rw7rGa=UWG0+BAei;E^Tj|ID3rA%A);Ni!}5Y8TXALdRf ze0P0>PO8Oco^^yYwMXXZe5UZ?Yg2(_u=m5kUG%=npv_bD>5Q$sTeI8c8wap<*j*fY z$F~^R%UAKVrR$N<7e%dwTO8tHQ42AFaBooG!1*0>?Ph<(C%Ek}@u74(6TN*l3$8m} zA`J@8iA^C~k<+^9G$WK+W6*7mTx@nwxbL&-FkK1;e1yy*WFkTc-1hObpa+u{cC^# zM2|(Yc4wFBERxJ4_77t_Y@J45-mnz=4q9lpZk!re%@$gn@fMV@f6=0sl+1KVPlIl#Py$!>@w!TOKB3Mr%va4tl7^3WohZSU_mSJ#;BY^ zSpT9>Ii;c$ZZ9lgsJ+vOdb0Pui%)SS?KKQjvgY823@y^0QBR^W6ru1^v#{_y4gN&m zb&?vTdoEU7>NJz(c`wCrE!KoEMaduw7i#BjQ$^z@_bxraQ?l)^Ci5{LXnJA)-F}hZHw9DkE8h8$`-Q!C?&i)U zW7q&pm{QPk-|ya;5Gm00{6;%PQ0bfKBhRP)40hnykJANsLuYQCI!?l^MbDEph-SFY{h0mEXFnUpy^Qk0CRGswAj=_3)04R&G{N1>)Do-3 z6>%UPjATMTEZ|rzhX2UcOMcsCVfyo^I{xQt#FOQyY!TQ7Fxu{!3`a{^1r&TLHRfU2 zoKECRp1b{ZZv4D%);38zG=tjrlbk>VEHV!z8oydbJ01vO5yS_Ef0&|BRVrHRdiQhHr~Z5Zok#g4s@&bpB}*H+#b-i>F5+@damFTfqZ@n=%0IDqh${ln54!>)FJ z(xR@J^r$u!=$U-t52P&hZ*}dkgQZ`Xm(f4Yp_G*v5cPrIzV)D%!*T@#-~p9zG8@Oz zaIgeA9Ks|S#H50wH23$7m}tD$kce$w#3~05e(@o7EQcaTMI#_p+O49W4mZyPy1*Ro zHWcoq3_Y|8Wig7*{4md_I>4MMH9v*SYKyZrzJa^$qP6>v2I3zh(!!expF}!?h_*zHm0!%Wow;Bs!QG~O*+MDMH$STPy7jSW zM81RPBA>M@n}Z%-`qNnTGiSD!cLtc`rcSPDl(7qRTY~m)i7Dqr)f(GIcx`7v+A^rY zb|v?_ath4mUj1^TA7s6Ak)n#s$!IcuYTqb}V1c!QFDmc?_GBt0ej3=&3j3+itZ>Oj8d*`>qu3z}XWm=Yb8M3yd*+~;;@t&8~SaNOd5c`f>kAC4C zaxLvSBHTS1#B<}%7a5)R9u#urGwV<#44V1wiP^ivJL2=^bp{GETVM`LfA@XfZf9mt zpJPiX?v*?CcK)^9h${dY3vr<-Xi4;9JKIntR+xWXyH;)GAW8bFP9zNdP;wRWySCjm z5=^6TaSr;J82fY1KAC%pT4h#=0u7O5rmBTOfs*^y`(WVWVqB=>J@1NJF5V4ve6_^QMn&$1f9^$7Fhh&w#`Si}G^Mv8)9Ku_01)y8f z7=(0kAUUGQIt+#~^STw$ffs8J8Ql4w&VPzeBh|YS+|B!4N&2t>ovyo(C@R;>0>(z2 z5bnc$b9PH@=8R=Q{dPTPf7qq*44q0_H4J=KWl1_tPTzG2eZg;C1An{Pjb6p^!{e+h zUfRsh2+_W0t{FhC_ZZHE&`uN}DQ|(RQgF;XV&v043k#*OmJ+<>nuo2 z^&$+D4D-~hx1Giy0YJ0N1_e{9TjY$om$ajp^8HNO6JIAT1|jTxuX^_JHiA!TRt(F@ z0hH9KPM}gwg|=`*A2iyIQ*T#l+w%`K^HDmawDD24Euf|I1E@zBOKF9guE0Y zZPJYO@2ZEM>NTSD+Mq#9yCZmXs}$r)lP!jxM?g7YchaP?oQuL8oA+%fX$&klg>GTS ztt>L)!o!*_a7Vj?!kz9^h@XpHlbF>EtiQ&3qol9p;r+ZsmH2Fn$3ro89~LI|yf+#Z zOh^8v2;4-DB;YJ{T6KFowbi(|DosmoMCK$tGaW%?S7%78Zv?=rM>AU8yM&7Qg?T`q zmop&jb~gO8oQ{1|bke$Ra;>Zz2dy=R@^Z-jg zK=uxgef|$BVyXf!W$UH^h$(Qje+}Mv0F3T}O!|aKkG`M(|7OZC{hRz>090!{QA8rd z4t)78I`%|n%=vgWC6juKVt3(m>pwGGp!t<$x>^*!E3Nh{_RF1FaD)pR#fPYV1!$

#W`_;>rEy1MT|GAI(6HRvwZKH?EaVX}PGUObVQvY-YBMoP1C(11~I6EjCmPU$E) z*?UTGr}~3AANPAMryu8;=<+-e)jMEjFJT!pHvXezx>p`Uh2-?RmpLyk9m1mE?d7_J2s6pCMI(V4B3{vt%49$ckP>H8zb5{R$X z*|ZGqcn$hJiS0-*QWN3wSyXn1L}zq&#?NU3kowf}{>(528NUmaw#>WV{-@Spq}SEe zmRm~BMCYKQAJ z;-ueTS$?`&4vYHTBui&Vosq^}^YB&qlG*=!6F6Ygkn8_w?ET<2s883jd2pSJsf>er z)so*+9;Ccnbcz+fWQy!#V_mb6Jl6Lhb2}6#jtWb=Ds-8T%=VnZJ6XtXz}(oA`WMWE zZNLuzQ$VOV{(7_{$+6R_{n1GG-5Bc{nbW9|gp=R;;RX8%3|I6w&G~)RGxcT0laXU% zFZ5DMpX7d#v6}QAAkmo`cB*Z83ltISN%jtCPD%9KHw>f=LhHA!hszGfYRb&KnKqSB z=d-t!zSdJ(jkdUBMgk%-6t-VeJ}L-o!9*GxAhVt(4ONG=+O9Wtg{Noz=}zXDQA=!R zPJ$yp!t#^(_IapIm?YH< zPK(z_F}DV}qt;Bsc4QvE{`6Y`LTxr4KaePT3Ir=!5_* zdeC!9GvEE4jYuKc!N$-WWIg-^1L7@`$X5IZpmV>SrBII5v>2(6Egf$(5hDL_UXngZ zTP{Z`C3ci#yT z(r&cl`}7tIUMTU`3GMDvu#9h-i*=vS+Uokc7(+l#i*`e9+#yEeAp~E%Z6pfw6gSoW za4Gop>mAP)Zcs5qU(!<*^Y@BbiWb1_~S`YgS0}z&EM?Br`1;DtncaZ@vy3=~+Z#9xz zIBQ}j)}3G^Txt~?)6b2P0{eeT7!t2tLw;6}q;>(UJg^P=v%oT?yPKjV8ex33+g(D; z{8?>%GJ-0P3KLAmQapFNYo&!XA*=LHU^xV zqS0_WP4<2z9IC@)_D@n99gh)&XQR+SOOlx1 zdF`mwBs4LF(6KNqJi@=Ed4REcuSIfJ+3CPCNy_;V+QbJQP_ znt~k66y3&h*FWZ?cm{ZIz{SMzGAbaR-kvFQL3I#nM1uQucig6>WJziUw$}>V`<+a> zJ?fdZViETumz?^B;EwQ_YT<1YhS3@IXDKo{d7)XVE(zU0yDEdSrw85|*wsn$-Q|ZV zt}Fo8GHKA}w9J{GOTVRXDeNq24-W9I<0_$y#OM1t^IU+VdX%NDmEr!q_vu!ky%;7U z8w?qXx%y_=Zq+S*@0<3jBUL3@MGUUvmoD#2-0_E#S>ekZK!!Y20KeFX7d3F~cfImD zcJ1kD3e){u4{eP3eOF-5WKx>soP7aJelRnLj;t_RaFE~hNdHN;+-B;U?}xtc$dQL` zDTW`1+=*w~CpSv%POE<&$+_;zOxWo~!Hycvc$i{goUl1`Mdu(Q8p?&ei(O!mzCKJ_ zo9>Y-O+Nb6wd1|wg)F7=lU0Z_z{d_w?_XxHPUrNDm&qcRm_~ z=6l}eLF&<^=~WrZ7l1_8U2b7rB^HiG5G<&jXZTBVOJ?g`@evB(bUBk7bZ-*rBdz8b z{Dx-uhW5o;swkgf4*^lQN^AXChvB+@-H0gTFJIAq2`-Ow@`OV(vSU=M4HRs`7MlCj zzV|`(%#o0Y{==y^-zG|fbO?3#Bj*K`p2LSHQITK2)e~G5SL5d_J6i++e*6g*%tpMu zyHl+pdgsdWQ>!?Y2P>ei77zsiw*k$H62gd(?@+B4;)qmozQZLo1D?^r$4`3RgwN`~ z=#iwv|8eVoocZ{WTkDqow{OO0Ahxs# zWR2rkJR{}_SqSntPdmlI8Hw90==bD^DPl0StMzv67@*|C9ztK@;6Q#Bn#O4Bz?cYs z7kJ(xGUARVfACb>YddR9>LV;OwC`}RzET{|KCA?H0`pY804 z!QiDBcEK75;r-I8^k!hj+kq`*$=kcKy!|35i{Uwo6Xn|iQwsbugJq$lm(xK%o!hip zAnBFw;RS5_@Cw7u_&Cm{GgLb=p7T{?;ie+xHbJ$oF;rH)o`l@WHQ+YU3xATX?}xcp zG?Z1khAhgzstHkA_(&;zw+AcXS2)XP9Y?%G~PG7+mxe(kJA&jl5w zGyfhKh$~ZY{l<`wg6y&Or2lx$#?9bc=E_ph#Kxe^bt@$NUdfH!nZ>SCse7eLPxXCQ z1GA%XN6aPNd-=@-RH58GUy(h<&a@%GRL*+a%#8?Z=KYt ziLbTr6b&b)@xOFSt3fYH?QxsvE6{UA&_!tK>;5~W_VppUYJWd8hJ*F&HI5;*A@#F_ z?4Xp&ljxh$fZd_bNtta&?=Qt7|AC<>__;;Y5Y&M88<&ps1VY>S>Kg^5r$61yy1<7O z+imk<#^&Rrhg{_%;qtKR*w-3SYOLCew%92$o5rqG1|s+ubp3JPlt=F^@Ph=O!aIPL zwnv>xT$&n8{0oDW$T4W+-x==u?$~SrX`foi*-LFFxAocs`2bB;;7%(%FQ}>JS$yXm z_ZQm+=l>U2{b2j~mH!J6l5QJKW{n{_V(D64&M33c~3wr5VspQMkStQJmFqp|Eu%Jp7OwU-zmV|r<+aQ3o2mT+T}sIs98oKYo3a zvHBH1WK8j)q?T4~?-TibcX@A&-OT$;nAQ8V@QU%~*^`Tg`Eknr=$&0#4495O>hozufQDCj4)p{vR2xz%o`P<)ok!u`AkP^Q=`ppRB~VOhm%fVT zi8;F+%I&gV@1EmAJu$k?-$G1x#fLAguD6y%RPD0@gO1AIwV(Ii(^P_N)8ul0JFzi_ z%9`x^=7A$K^o&8$)G;yO^t(LuX$SfOe;-i&blK`mw<4xq2 z3gHf*LZ}dJlM56Z#OPtF-}g5Hk&M|}8SAD#cZm!KE~&P3n~Y?w+H6V!#5VLdhx z%7lwU24zg=UxhtgwN~C@i@5Yrp#}G7DivOC*eMhkepu=xr-C`XqrBdmXkBOMeKb$Q zMtX?T?kp)Ja{y5Z{aKF|)m$--*HiC`S>ArL{1n;Vq}HLHVw~Y~f>Lax(^RW+c2Kz6 z5UkS>JA(DQhE8{{^E8r{AvV^BfgT!2%No@jMo|spq)dAcv&z1`KKXzRlA6yajGgzt3*v2{F#K0VD)dd1X=dOW_l8x;HC97tCRY z+`G^UHUY*{Nl7XNM8vX9tyi{la{MQxvE8t2cN#Jn@K{m?#lqC2qi;k|^D{A?U?9x)J=aW&a(cup_t9Bdi5?{HChvHd z#sCa`9UeW6MQ*MW+!E0kaAYamcK-_64#l`M3Vl|vWe`w3e!Y4)8n(cGx))uqbtftI zQ=B+u-ay>vc?<8l=-e2lHdH|pHY9`GrDKdOi^U?t0@^pFGctWP8O-n1B--tg$Gu4F zLvHw_Oz1Y*2=v(tBVz3_TUmZ2x|5Y_&$+)VjO$mOvWzoRSnuEr7)XrCDab4UdYr(U zWXCPn$n0xVl3?P4^+>>DQM9$edUYkBbiklNBCWPOTe1>tk8WOmyBMa@^WiYFEN~`O zS9I19v)&B~fiQ?P0iNS6Cz#q0r06n94;*oC@_il5M>%ura2BtGPyqh&UV?Zp4=;d4F2 zvDYmVP4eE31vFDn8KSz+MP(ymp?Jq76#D{`G)Y92K9lWBVfQwq`}QN8GFYm+ojEvk z|3=H&KbipwD7;errUOf;t+U495`;ZpkMy)gHcXo;m;t53lBE`aR~#=8lc;ZSEUUZl zEJ0ur?y>}4#|Zi{br78iuj_Wdz)PPrF=3(58tviHA4H=L9qo+hdJVZhsG675OL&V! z_TKovQ4U1j&R0AHhQ~put~zuWR2fMf7(~_JK!><=C@a=m7WQYwYnaVOo7OMXaJABh z_cz;H@)PW(Zz()!a{IJFg15b~;2C6_xfnn+sD?T(1%j_@^|5--^6uVlElCn~BYk;h3ur0BNFdoO! zY1fW;@ksB~um@Yc>1ecku_HL24v3cBb-)`0vJ8Td5 zm72I)>s-EcX_#?O=xmG+!)?wboTrt`Gg^MCCCaLm=dUjMk`K3*pWteD^NV|or}6bo z!;*t4#=}6vdP=0ZjKr{*M=*$z4!>^m?j6H%r;=YO@ds6XBM1aZ2 zAZ}wdaU2iKB`!8mVtIA-Fbg{abc(+qNa_^Q2j}|7nHQsw#2$+K)|Rjlpj4w;9krCT zw_wztVzIkr+|u~$Y*CzPr_#kio=nsNlO~mD0HJ$CftlVQ`E;QQeMhWnX82nQ&;RzGPWmmJ; zdKMC4vyK$<(2vXOl-LDFmcFSDvBsPY!;# zsb?6W%r@o|a>B}begh^@oz~`6v=TdX;U0TYm6^;L+U%3-FPGB1TCapF5xeg5HosHu zOZ2_-i7UV=Bw!~qX7}5S)y7{1vm(soC8cCc^BldpqmrLw&bhaJtzOk3q8FXs> zD);Kbp!;Np0G(xV@}=~xGwQceN9nEK(|rm3m+$xCDgq3YYQwAFhLlcJCG=eryYa;l zCwKBF%b`pS^rGM)*Jj2bj-QwziVRD;n*&i#uo%lE390D0ifY0E0WO+|Z<)@fagLPRo9%MU^{H*dv zI~Yj%QFsWID4%fhZe|*kS_@njlg?soBaMWg+zMZY7{~G&e>SwU{2G_%{%)Z^*nNXDEkedbL9J`_u@bbS!eKOd$7`(OmG0(QR^}(0 zs`LuC^F^+dOZ7}K#@f+jHQXeeo~WXnaq_02E^=k@qI!9khd+#LxWO$DoWk`uq_~97 zZCO-CH$*091<1;SaCHq{q_T~F&weCyx7OkcK~O3Kc|Sa6IZ+kecJ{M}PP@D}eigD% z_XvGuXVlwp5e~+R#b^}na-3Xo%_VMO`V}#n2Ksvjlh4IZb)-UZ_Ym+P#DNFnI9Zy^!)7Q7YK%*Om3$BR1mHBB?J23qq;)2G?D2afPUb1*dk2ZPYbCY~Q8EdR%@!^HYnO z9bgrplNvJr{RwL4wPwqC9Sj`wLbTPfqOmG% zwBpogGG`%%BG2%M|MVnph#WcT|_wH<5(fvpBo;d%=mmS7~a+`m8z|Dqy zVN=HyIKkX=FaS{%n>Xf&%}@9aaIZXd=*nI*#SaxO5Is8y75)%h^j2b@ihhj`C}SM% zxTH5)3?gWWX}l9FvC9^JULqPM$+zf}=$yOki_uvmT6WEvRyyJK^86AK4uwmW_KvXC zMnm*em}t{5iIsyKg2KfUsf_ji8~*sODjb-dJg!d3%l!_(m~#g+xl3B6w52 zXNG8pDG1o`-eF`XCW7||0Xa3?&cX-T_K)U960oWo`&984io-h#q*q1fTG)xXw)tNF zJ$nOhmxIC%TLu9&>2SxQuNh*xwh<*N_)!5#38P*mI|K4ddtAHeL<@-cxvgv1P&pgB zuF>%M=FcZ}zW#i%`Y(%y`B7!X0G9aw0Sy05{V%le4--+uc;0rYfBgi6f5QN;{YS$B z1U)|oeSG_WxEH!Ek?z+?S62OiMog^;q%tg&oE`oZiK`|(fXcSOk37z#(xm>;G`f6; zi%zyg-}mX#g)gcErcRM}=o7l3^n6=z6pxQ}RH#9SE{FmSaFvFFEy3-98K1^uXF{ zoYq4&&sbptb_vu0I782=XWozQ76Q@~$|8$xK?(V`zc>X+rir45$Hl~Tl9CSo(FhU} zRuYSHp0-kxX-xxLR@tV=@@g(}hL~wxZNB^;tX97Cnejw6KmP_`m!2)gAK1EFpzNgr zxt9&cpyTAUfU5xBdgywxm0fT|0f)TdxP5FicIN~s#_;nd_T4o5gE zfbY^4c4x4mL=q!o3oD zOu3{jiuq0>hQaE1(K!KvB<{aEZavrz@$t6kl!PeTh9MzZb{?HRh^tHbFifAStN8fz zYvD8V<1>Ozthd|Irn-z1d2i@pyAP~^%!mheTL(J$_GMytaaXxHFIm>V_l0Qa# zc}{Zc>GCA%ac6rw= zp|SM!GkM3e`#CFP3g>`>JBm8S8NYLkdu>E~i8ax_>DORbSziCDrzX@t+w32Wm%EMlo$BMM$q03hA{}*lV9S+z3 z?~9Tqdi1E11Q8`fvO ze^R=O0F>zszbfIiI@wJ_vY#%dU$8ZLYV8c-zl3E;EP~yg5_r9rl@!O2cX0XW>2^5! zrE7%ATT~}JnhmHrC;;xFeymw-rPGhv;&+>1rP^;94A6D<>0Sw_PrxlW;X9;lZ& z(^5_>1)k9NF1_nU%#ZvYOX!K=NQM<~`5S=5*ykP3DZ~xC1}5;26m;4FZ6LO3)mag{ zfl~r*p{HZ?45qKQ?F;(v5vOMl#0s9F_LF4-I4+I9%g4G1pS;9l;gW zxmvvHmjat2YDK{TL~Qs?uc)1d_cqTToGhRaE&)W_1{I0qSv`scT2_ zk2>d81W-RenJamh?&M}>63kRguT2gq3wq??d5VZ1(vKH)4`O$lT??T6wUV)JMcWj* zYrzL<_Ig54#I?1eXJBYuR~iC;ZOT500{1S;^T#dOuvk7VH+nQ&oKTO3`1>F&*>);r8q2$ZXN z&U5WAnMk*L76^j~fh`q03?ru1uqZ$b$3G~d?<$V9e)hfQNOT4se{rBfTlj&20z1Yv zLQ>9k#$|j7zVH0j`^;Y_rnGEdD!{-zuJzX+0^*m?Edlt7$)D+dVhaF}p_p+UJ?c3) zXY{ms_KLV$tKiY9Rj6HQiB5?lOCOs4Ihd!LV=c+3n3l)%F;d?#J zic_|5k+11RXBb@*GeRvf4=jlb#WrJtBKFGg;MQ5meo^@$M?J`?3a@zMH5#ti? zp2e#n0pWlSKq_>)MxtSt10_~EG2y$Ni#I2)q^RW2lxzqXYutG5Wma*8Bt;x(YsdzX zw`VVwu^62tsMYK@p#8qej&OW3Z&}PP{0&0CgkN<)vJj(610`VPnk$@N>0ebaLd-;G z3KPzXWrDMfc#jZF^~B89YCxX^C}*qTZ87OTF^CAsdIaK5La6ucbK9A^4Z1KLP*(#1 zI(}!+zBDaPBl>r$@!jUU+H+_G+=9_J$`tyFv=KN`2>nfoS0c^9sha(YOeM)d>J^Q_ zq|MpeeTl(a!=4cJz*mz9FfakNYn*^0QH&`hKDGeH*$tInYA(M&D<@p6ZEleEgDl=e zgtIZx&_J5Ew8UhJ`k&?%>v?VuC(LqwwH-dz;VAn$sBio{+hI7KMis2Rx9K9>+02Vq z3KR#DePU2oa7Mc3Mz6*@&&wD$Zr90j;-}FrVz&n!MO1l{j+D%an_J9&cfMy<*_H0~ zy0jAgJ@2v+@Y8F>xkhS5otdO!7ltAyAb!Riy?$UD$c6a(_kE{Pf! zA@;$wI&i3~IWVuqGnr9=l1_KS|T^Q{Tb>wOr z>-_Q$5{7r%E3+6;Wayby6mhe;7&-boIVW0V*{Qea6Gon*8Rkkm8c0kQ=a5kgx}kwP zuoYM`SS?a<5vrsDdj`7qZxmf2fsLbM%>i`XOYz+2sOE?J7QT%06!hzZ;^mV40i!Bl zaDRjTuKDTM>T#lxD)-a=Vd1VJeP2J*i_uj2NK$^YAYv;W$v$50)G_xoQT2*%&q$(s zH0Ch+aZh?lrzESV*cbBtj$^&W!EFh8oE4`El+=u zVDJ;eoU|Y=u1Zu>o@#8^*DbKq@v_DolBh4et;5AEH9ZvPN|PAOqoW^Yo?cCbUg=drXEKYeZbb z)j`l=(UPrfIFt1&yfqA@88Tb-n)DND6(Mf+Aw=fyzIWb7%_dB*XMe) z`UzeKwTb)6W0!avJkYI=W59DH%-Xe0!8rD)#&xO!Gx%o9@n{*pT*0}##Q%6h*5X~SP)PhIpLH` zIsB1KLPIqoKA_;0k$F910$i$jHW;cph9fg zwUOFLn!@jF^ z=iL@{jcH@g%ggwDUG8+M@i`eJhG_fHd7gCZT|NPPADkrdKrLb%RO%g|8~~7X-$J$D z@Xjd9>FH~>b=fPY!Nk=AZ_Zb4Caton*XMo{ee-uTF86KuvRovfL$Snv%=yBsxfMw{oset@mAKqWR3!( zP|84Qbf-NJYlyA0T<2pU$su>4gSUR(<=gCR{HhO{v$d~d4sVkBTdVClQDlpOFENK7 zYCv?p9zE~M*6Sx2oXylFoL(pii{!Dk^}X|VE6V8cXA=j>*2R4VT1muU`G#wYAs#J# zJu5YpyhZCEz*ciO18)N+BRC!SkvTyFBQwVvC6YFiTN}^Cc=Uy<*6rH0@rmfARy)^l z4uLLi>K+Nmu74H8-hEE0E}|MNR^$4hF@FU={ zUPQs{cRBPHcl=%Qe)oG7zSuuf-M>^E*eP$VD0upVbP4Fa;6&coGJ%H>C|5YIOL8`V zr$xV%s?kh&=u}_kvvRM2P(6OQ8DArQEj|M4Hd!;|y}JsJ<+$hSS{}$=YQE61YNMCm zJ#o$B2F%C(?d1YtI9e=W(1NS+_X@57woEImtP0m0pB>grkTwo}sQN<96|kmM$`0SV zJpT_JymdsH12d&4dJGs^ACkiEk$^_Ff1PUT!TOf0(cVv(KQkMXS?UI>Bwo9EliA}N z4V5$^Uq?jlpTDWy*&`2Dy=wIDFFODJ!WHxL+T=;D!-XE!eUH2*=-w>yQ@|rESzGQU z_`g2!bMMlarNKYjdLZQY=Feq^3*F#t&6(bxwAZskz6NjW73rJa`sdAa#w}nAg74Nf zzg@k1)gX~t<-vb9KIgT4yL>5@DqiJ3Hq?DW)^?J6DNLLC+rRIM?%wL3e?AlV6WC$R zSIMSix-b4u*y#TPkp9O%{r&x4;HAxJ5_OWh;v9)?_K-M|T8>0v>x^kgugGzn|02%4 z7FlZVdmP_D`A{jHu@GU~(oEZ^N}o3$D+VeC2l|ipPsP(d~W2II6VK&%|B!7>X(Zy0(2YN%Bm}p zy+tVzjKjNobgX;bw?5X9J@4~o!mS|1iP?%a5E@_L23|ritt8E0pfx`CySqXR-&w0# zCy2x~*YPJ<1eI)7JQ8!Xka9(%bm~ukteQW5SdiZBI!z)k#LQt$(Y=xHorR5Yrg=(v zzL`&(LzdY+kb%0$m2%ToFR48g4~f$OeiM8Zm(VV4*U>E-8Kl)1kS?OBUa;GMK)2<-T!m6BOrFa0h%E;QQDi zm4&YNOJvc$P=gQ0XwuPyjgvyjZ|zN9zP@XreWyhd4fhNzAG%wFqHEE1}?gT&3=X{R3E{j4H zvLmYdFx2$>evOEU&Fm>fWm~a|uh&-NuR`U3@w<|jx$w7Gx1vrXW%L>L7%(9V?x1l#?O^`2 zLxaXo%G@P0LtLe=PhWNxw)jmx3SiQvD;@v6W57GV4#<+>e;Vm$EnI1FDNivX*-RLn z@Xy5fBS`_ycr_t|U?Z}%2ip)iKv!^O3pb9jdp+K|Tn>J?;5*RSC>-kg<{gKG;P!C? zmjq4RoaXUa$(9>?nLL<9&#gJP>Qt7md}Kl?9{cqcgZ0P;s8GC<~X2aT_x6ZAj zS*}MbE|3}4&f**viE0wBBlR+FOv8m-HY)g|=ysZ*^<$g+y{=`@^bY2E$N6;xLE1g~ zvs}^G)ypZ-q?iTJy=rlJ%_S5CZdD7&8!3-^i+Fu)vBILGs<`zB9p|-X$cpP;3%a*k zktWb!2}R?puUXMDc`~zKx_0AEqzlJGUN>({4chml{BHc`Uz>t>HqwwkV($z+y|*Zx z!FkBOQ^J9of9j)JF&CHkEQ0!L(OH6rBT-?)rT?s1I3OcX_F5gnShXI)uV<#CV@mf0I>+bB^n6tao^?hkKbrYYMg`0_kkF zV%LGZSh|tmz&Gx9zq;GW%vR&K+)NgO!X7FIomjecv`UpKE`5R52%@V9k0zjUemvAh zN65A~k5PqMKTa8EE*SZ_<6OT)2~Ry_}zJG+3hD zq6i_v`z< zUkypm)ozC$`mguc)cn+D5h@d<%EyA8h;gmfS`t`Gp4%AJrZS+}5!LOQiT|B%6|b;P zsP7C!Nn}+h`T`oZt3i#J1BzIqyRK0elWKZX(s`xPs&|(?V*|z()z)WT%#fIfj%)5G zhao@Gt!oo7cYGx)Y<-;UGSG^%j!RA`5R%COM0dYDttX%)#&7k@`Smwe9x5*(INgY(nHk_%_T+#6Et76Pr zKj^7p3A7(n*#)bL=s0AVS_W8%1s5yE@`CyB@8&)V2;tnF3F`KHEReJ0~fV{Oj+Y7*p($7>v*dPG5b$D&drVz&aFGIKRZ!F$jPDo-|i-8&dD7uNIeg?C^Q^_nB>S@4OJ_AUn1? z{pitF%LEqR*^A+0YzT&UP-gumJbHN6&`KxA=Ui<`c!xd?Qnilgf`#^@Q`$0Od^Lt= z82KKAT>c(XpNJUr@v_ztU*%w_xM`po{c2nDi(2lfR6NU(#xbf0o&FIhjcsKhFnLQs z$O27B9nChvlIY$$asij}eGv`N>jY+uVmpe~fekE;Nkzqa*?S!Q+S|+Fy+R0%-3%Z0|eKCQMy6ok&A{^~Q)wtOIv(o#<+`pnk+k32cnn#A1aoWmG8s0}s zm}B&JrVHL}kVc!XR2=nN79L8=B3uFQ+dCv9LGU-2{rR>ZYn+qwLMqf)hOsw%Z$|0} zwo7v0wdr{lN*^1hVhlI#3qMMmm;Z%?xG`v>OzDmI6#x{1 zFn&i5!x37%pTA3}2u7=kt=B7s)(JQV(NkS79>07PZjvZb6aiee-)g` zZNvfd)fMb0U{bqAABkdXHt<|+!m}Eeyz27D*AmfR2DRkeKgjj$X3-ODE#ujFFXEaIsH#>;5)Hcb)#++o$>0Qgr$~S zIj5kOZ}cC@hM;W#Ow?*U5)7$^e3bWGrH{Gq=WU_>=(gGd zr?zLdWH1x>PYj7N6)(J#O@+3Lv>ZDXmYQ@e<83gSh^!WIt+1O5!SPY- zr55>SpE{i)7&=)J6NZ1rA8}WFVXg#;@6Vt+iMgj`cE6?~dxSK-VNyKz$M#MXnRg%G z{VJ^EShzTE+R6KYdo|inMS#1HY*WVmDrR}{890% zHC@5pIUtDGD_TKB0SeOW^woU|z0oN_*Yf2f+dIM&sW#Uo1PI5gigCVdKo2|!LWIjZ z+buzE>=1%Vl$&9C=eb7cR5|b}3L0lhWlw>qSdS z_w-YUtGML&s#BhBE!_O8j8PwqhCu0w5$>6F4Ji|QGrlqLBG?WNHaT~%&RU%iEOd6# z@Haa_#6qv5;h|29Ai7zRaM|2C$I1HSCr3i!Dc9#MlOVPP-zKzc1oT!Q2-Dg{*%lip z^fPUdFoV*0r-A zBJwJwzE&8-NlBVo?*g~nG$zXpT|i9Q7cB5DTfHf^KStVN2`GYE;kNt`9|5o+-z2-C zH1HZ);h;Elfag~I^DLg+y`diAlM$MqgfFLe2>|ltZUAdaP3W2xCSC;x5&;M)#7eEO zE*N-7)guDCMnc{W^tc(`W|{shv3myNg(Q7q42h=tPgl@?g^k(dt!w!IiJa5hyk(QD zrjt*mqCyrlj*b`GJN)Chip&)kZA>d!ZjyQlUF~!mTO+~p10Uu;k!4pX-goY5%uYwA zFHaR=VpbqwB-VH7H)c@2X(Z0;cJ(Wd28ZHC>XO;UQ~nt3d{jiMBBCi)xTik?X3DI_ zS0)}Pr61Jx37LYPphRoZrM$P9o`HF8I?SpI>K=~P$!H1!lQs4mIwB&F34>Ukj{Jr` z0}PzAJ*IwLY1160#F{6ut8eR{b*bag@Z2%#RSSnat>)A}3qGu&Sk9YA4pNg{c^aP{-o%dpiQ zFpRD>EJzCf#uwC`Eesst5P~v#C_P+EJ|M``YooWoShDq9^0l9FzjL3lM0D4=FK#%yN0#HPV7>b zqVYzJrkZ{QD*e%S=Dy6RnbFX#>22wrK=zz!Gh`yclC!9Vu-8Z~-(+!5mq6U)M0?aV z6fz6?z5WC((}uW?T-o<|kzhV9#eI9Vp(a}R$4HXB7ZcZ}aGG%6!Zb7a zAq1^%%ZnXFFHzTX%Nbk&5EmlLISC#IGd}tMW)}Hxxb^?OuaW;9{jYdaA&EL60YE=L zf}~-iUajfln*c9E`b3VC_!r*f59a405(us4 zY)W{*&8EZS4aUyB-)J%8H&RQk+!oFT-=Qj0keTEvYi%3g{1%8`t)b_9GNgebuZBI4 zFdqv3W3&a^efw(fTObH~Ri@-~7mmL0P-J>s$eTKLytkcORC+#Lze2|Zaavi5><}PA zLUwwA&Kyde5wAPP+b`0WR5K_J5Cwg*YgA#~Uix)+#E6hkqYXj&P}ZMK56!AB`Ew+Z z7^+k+nWtVx%9a7+fzf@t%Skr&7K5b#AMjnNRvUrEy*MG{&Qo@&ySI449N)R~7St3(`aS${P++VRoH@5Xag+Q{ z886{VUE4&PJRkkLO*>kXL2~$`=i_2f&nK7jw@0w396?2mM!a@+IO!o$->sYE4r5T{U<2D zbs($Cz3GpLs)mEJmwaUnjTck)m1fQ(ECl<^C0_X#1z+&5q?E5lg5Hl$O+GnqK+wM3 zmYXl3GkvxBF8@e8<3w<|)b8Fq>*O`}=e7N;-kZlI7nKPu?lj3$g6*i36R8#0O-0+o zFc6RA^*}LaO6vDa#}LfY+&`q*M`-hY`gB<;HC%3i*kQfiRDCmyy99cjQKQ-JTl$j){fx57WSVzmo&J zX+D~Ske~K0D8>Z|zb&x8@XC|s2x|7Ot=(a~_x)vLWD6PfQLsh)W5kr6p6f<8?X`Yu z=es`iePjF|K|WU!JR#!p+|v7=Z>6ibiC>($>U4TyGBw?uMxR6V#8qBYrdMRTYI1bs zZW_v0``Y%e2h~xj`nKh~=X~j%-^S>=$C)o3>>?p#enml zdB~%!Q2)I^>FKD?AJ{CD!xYzh&PSiVYkml@E0cY%DXoXNOJ8FrpAn&uRV}bv!_g9{ z9qgdS#Pt%%Q`_7B$U5U!wn{|Gm};v<(Vs8!id1y_CsHZ|35Rjv(u0KTCoc5MCIfuA z?Dy5f!A9O{nXP->ctwbrPEaw9SG&2X-s9*6=F*^PgCrnBd<&nM1!aS-{3)W~rSedO zI1n|mtp#7k3FvN>HLN|Jl+9GyLnOFbl2et?WWI$8W%?RKp z&j%}o7>k7B4*VbVPCkR7XgPt_8k_T9KmSy=FlBH9V~XBFi=T>AIyM{al4*mPCY zFg2;ccVShCc0~?{5`^z&NA2Uq9FV#Tlh1}kHDIGBrUAg)yVZ9o%RSMTv;LCx7TW~T zI}lBU1{c{VxD@5ahqABQ4|{QqPWjp`%XA)Inb9i13220>)uz@}yTx9DJ)W*dhsDl$ z&wqNeHP1olWlI_Du@W-OBJobc{*U z6RmCDU>5X_u|@vMU@61%S&Flk-LYLftg{(;Q$9m-<sWgKe5Uy;x87_=!dQ<1 z%%W(fHt3`EJFc^EN&5Y{>LU!kq9I<+D1YF`yDiM0x!F?2+anJSDy=GJ(sv-0Ns4MC{i%! z`=x$&cRxN_Qb(8(Q3=tQ*2^(Zu>M}Eq@n$e{67;=S9w_qgYq0^Edl6G-^4FhaHD7R zfG5{&kAa$+4$(RB_KJiXx-<@iX4HD7~GO@idvCk?(2X;g5#2cPUb(D zYv>SWbJZsd$r{sL!O=Z($nTzbJM2XznPRi9wlFq=L^)m-_!uXPVZvsi%O)3UQ*(X& zi9nd=j$15x`^db5AZwO@Dc0im5Sfo3=}=^=HW$DeqDdu=D*?j0O>piRb7iZ#3i&C+ zI4J*7#7LG9&Fc3JBpeOe7g&;m#X@cp)DgZ2t(wv5Ik{`mlrAgk2f7 z>B`?{K|`)x2_ayCm}UNmecb?sY7Y7YFFf8+m|w(&caE>z7&lAt>**@E<_xqq-~o7m z+aD;tD~KY!3AkcIcYWSjiO^|Sv12*Bi4`EG04%gMF+&ms3RJ0^5Y4NdL^zjU%|H2h zrzg)k@SXekwN^09$@y~UEZhEl1TH{jVyy|iUt+9mFVT>iQ+;I3N$%1Fc1UOWmU^nF zQlk^49Z0|8`oW(ri61x-%fMV_{e_NIC13JG~uA#MyWEi?k*K0L}i>5>FQq7=y z$26abr)~hr%`!9{6{w4s!v*NnrETg}py|T(&nz6(c||IFn&|d_BiEk%sllYH82RMBIpd8u=f?6yp^@tY2v_j z(R-=zq)6n#<3IAY{-=y6K^HjZ=Yldx%&ndKt3+NBBc(Lx8J-U~xy)NrVbYT1SX6L1 zGqfGfeBZ#Ww|ka}^_1tuA5Z}Rkz@66Y|g6*Atd? zb*}g%{pI)Iu>ZWQ*Y8M)z2y1iy1|Dlv6r>}>ow`NpZ#f;%p>cD|4J$tz3HkDB$Np9 zAg~9qk=WT*TT-{P9oOnd*BLC&Z~2uL-3AuOW`M*VXDO&4Tbzbv+zCoTa5}ql;|5=uMF%Zy(nkqK$Z3;isT7GaO!rSkNp6bFryM4_AC&FrGKP zx-$D5HEe8lQ9&*&yA@Z&FFCV*frysZQQX^HZEiqMwLou)(6|P$eEmz7$&s|v zn}ECSfKwz}N*_dcp-5}g(&h0QOVv(nsk40`&q=usVHv7g7%Ch_~% z&sPWy4nReOac3$h7FGExjhF{z6M7g9zB~4WHp^~bcWHVH7VYc`z71AoZt_i*e?w&ps`hZ5190drRxu1!I8O z(^~BWz!o)^6|DSj2Q;ZRGVp2hEawCH(Md|G%CYVfz@@@O(1S0*Vx)8;XOXR*ZfV^2?`SAj}Psvvu+b5nnBEU4k-Jl7t^TlbdjIjG^uKKidvji$EyGCXx zH93ljKH|9lbjt5`(*pC`RBdmYgw#2ah9Mt#6+A-fzUeX|tXT{r*JcQoLCZu*QAdos zp!8Wiw(?)+k3YAXU50S}G(8VC?k#dQeVWk04SIss>7k#MP(wGTRc#wuP+|DXs#(XR zy7Wz-zgdwr^?n)~IOw=WPYD3|6xL(zHpQ0k=r7(}+mX^@05O1FRz zxEHV`bKx_cJ%X_RxZ3)I9stR(29WmXNlk7;>ygV|#yqkZHv^-|w`LcHV#4jM=kMcK z-$X&2Qz1QIek-4yblMXqy##LG;zwP&4*E1_wnGrC1;f^Mj&+xq8O(y;ij!J+;cz5*}CCe z)$l70X&C}h@*eN;10(RhId)-?=eU=mgl#TX zP=l;%QpCwyrTC3G995i2O%qc;sOPJ5!DoF70TU5>-l75~BV~Q(=&C|Ju?#$nYOcUjK7^~HZC&V zZgc|ein^FROCoA=*US_1CvJH1(AwecNdq$e1Piu09Q^yd0~_P@+}8)>`n+6MQD>fT zY{~XF{D=3Jzf_gDLWC-q9bZOcqjKd6EAIKze7;%|v3vhnbpj1$b6*&3w+xGRYGzqI zWK{mXGaIXF>RWh)LgmrYlqwu=1|3eHzSBu!y_SA;SDXVGhosyVZJzH9o4eGAv69Q{tqWhdaC-Hmh~WzIrd0i*+JR*e7r*&y;1ub+RF zJK^icb&qFk4d*WOMIye4v}R?zCuwMr72~xTa@xviq7q<9dT}JUK%@7U%&o6g6xL#P zpSQ^DLissH^vg;a&vX}bRjLjGZ86qaaB1IB_giyudW6c;^!qNsyv_OrHA#NgL@^@7b$rReR57YE*`+-Qp3?DBRSDYLZLHhly`Ynsg1BUHEoj<>z#9 z)99)f6NlAWjy)Wg5+4_N-V3bXV}XYb%ii~Lyy38$->JkVmDyz&tcYZYTQ?XaM0>xeZAq) zVt}b>Oy=vkgP#&zvGC}1#~lO(Znqu9P|fLj)0d*l`{E$Mi&VTa`~<_a<$VI~-9UJ< zd_Y8eE1uN4=~=MnbxA!2w8*2d)%1nbe}&-N)yHg@2|oNCC+VgfOyj*FB$;-#TgQh$4)7y&`X&q~ zE>SowK~o#@c3(Qq1|e&{L++o3{W^$$m+A3yvqcL7?U33#H?6@Z-P1SC4Z#5Y5n<5F zDSOC!n73s$Q_qhW2>l){ky?KUj^EHeT?v;7&nsoXG?*(Kp*<3O;>f#72XV(#7eWmd z;72-T4kV5$O($mF^J)QG?8-*L{u27ZS;;Vbp z?ax}W3Op>fGKS$f4*u2NGPA`8HSu<{Hk-9O7c>@^*&~XJUKNTulUCEQ7xQ~xb6W=&<(r%P5G#Nm zFrfV>J3+m;+bTltSvfNjrL@?vK(Pw%KrzZ2au~%p-)TwQe{Eq|s;vVO-?hl5r}#XX zD>SjR*SKS@u0Mu7QIHsJj!pIZQ};vB#Ami#akGT!6p`jv_S%BUWvkUrYcIU{_$TL@ zWl)?)wlF3(~>= z4xt($8_FTnA}j}o47#qydVVRIh(1pQs9^%I00~)X@&jGZotHkC(q268Mo5wqh|?&; zMR85nncXF9f}PX2JP%*8ccA;{^=%93w{%YO>8Dln)i7lw53b3v+@94xr4Q?Q^X0=j z?bIIM&0f}v>LMCO&hQ>epwe$JONF%}<#_+Uq3UNZb#b5?4t+sU|;N zvbYOn@dexhNoE>8*7duutpveu`5t>W;5vcP-hJ|vTeBNPKc(`QOvzNPiaPi#9(N3h zKP5$>6V^AW1Z>( z6&W>&6nrv7CU_-ic`C~~$-fAst37y)A=*r)u!Ys~F70#cL~DkH*m&#B;zs+wknwzm6Ur;vh7Hw zyc|6BNm$xVBEBXu?A^i>TRrlv=et@|z2AlmK1e6}-MkogcmnO6Yoc&17bN3bqSIk9 zB=3>ALR%>Cty?mL?s|LCPuhPJ0+)PWRfm?7Z*sds@*(J#WdeBDRf^8mtG?bd2Q`Lh z>{k~SRTE=T%A*PTmjr|4Hm4|p%8xbr!}I;tzhs~xQ^ViGj2lK^x01A}GqyT$6O(7- z^Do+Y46R;{pklj+)d2W3z|dDUFPZZh|vd;B`?o3MrI%`;U})dt3}4WSRBw;Dl6iH)CF224pS68JVV%!w z+Pi*j$78YCDhqk%PRkrm3#J#_jYh~smz6{|V_Ywv$1pm1 zD+ZF!tq%pU+b!KLg8pf(It%xro*W;7cbfB9OSqB8cWk$o+15#cWr)qE3KV*{eYaUq zY%V6(c&5|d-IHqNk)|n-0O`5MC@CQ}aQXB)3vW?&98v}0uvJ)_vzxap9qSUAi z4-PL`Pjoy>!RlhBqU`VzfudujeAIq+%e!Jyd^d-;+D8c2H(E0ZW+}!`>yAkg`5|#@ zL$1*fhPN$ah2u7Fua5K;3lET3eB-A(XA!fAm4_0o7&`GG80%QU!nMUcY+iE37L*U| zov z(VYKUgm$?GEdboxI0LmY_u-*no~^pa*t$S>+Okqxb<;)Os(q$jMFuMHv7~X^AM8i4`qZDs2 zZa^;k8ok2Mcsp3wj_(yTUT2%=ii;jI8BmtW9~pzsT^lzahgl(Jj35)1jiXXTb}7fF zDZ=euoXR3l)203Q!t2*8R^1T6Qev};*pSH@d#PQZbIpP;{bl;07O~75al&bHlc%H7 zKb4j>>^<=tNuHMfJu@z1g`qHNXgX0!vn)HnD=|SL?GTa+N52?}g0YaqpmP^?(egek za{JJu@y@!bX{Pyx)VNR2ujq>J#YmLEkU?6Hdb*|e0zH?`Q&focCw>C2s^dpixTv zQ?}cbZ3-7_lR+sGy9u)a*eGHe7!2(_+C?#*?o;7cc?t{W7XB#ZnQDuQl%IvO=GA?E zb=RElnClu)0uP}kwYw2sw&+Ao|83(`bw?2*XBd+~#Xjq;iuj}tm$ z=;Hv07ZL@&{HYQB3`{*Wl>D5B8$C~LlVam~yk~4&3+Ss7mJxP12DCmlu8|mrXqL;} zBGEMdmbaWXDQh{56eVvO-`l8ty|CZY^Ln8+IWHvy`nKpES`5ekf>vg~VJTccm=;;S zxlM#W{!3;;YS{WWJLcs~47fR)XKbz2?IwbX-qYeKiq)0RtoMfg`Sh_sB=Xi&pSUos zio@hcWB-vk`hp35$-%mHJK`Z6Wm#WmL zXpX}K6w6-xC1aHm&{NgxP%|Z8%9%sGH+eyg&;pvpWk*pq=Ao>%5?i(V#3-O?x#uZz`9(^I2V)c=r2mM$8RUBtab2i znh1P;{3f3E8H!Ep62P%#z)-6BzS|}`sk*93%ThrO*IQW+f6ADsW#jGw2h-ZfR{zS4 z?*NHqsdM@R9)~M2);E$i6I6GVW+WI)Y0KBt>6qn$h}k(QD{0MrNaJ8G9#8gL_@Ijp zu%xYCY6Ig_v-_G&cN12SRhzfds6E+K4dyA&D5U(5_lK$<&yw$F902QrqHer{U@NcU zsh$k37uK=RPBrz#%)?VT(3~pwZI1P6F@U%qWH`S$JryA8lW;{CuRgibUgGJ?d4fd- zpFVAJ6HkMcxUm>dp`(b*ipH{Bljqm?u+`RmO`RGu6G;ua`J#oPhleZ7($fV)B5wm> zY-C1<4R+j}?4jZOPv?8PRvw6^8tWlDdlOjtX5IxI*$=E%A74@^xp%r?@u|MmJYME$ z_ar7(R_J#kMc_C^oU_aW-{>%sXir$rjoBXPpbk!3L_09gu6^SZZj4dUhg$q(NMn_y zQfcpm88<{hXv(^<%}wv&ztL#Q#{1J@gy=psU!Z;U9{3h9$0H-~Tj=p6H5Q zb}S$?*t{Bt%$)2J>8FU@f3Dcz)>*;4h6$^x?G798x2nnMJ}EYMHFm3e0(^JdP{y{q zOjLfU>1Thn!FA+4k(|$e9*a3i>l`5_(Vv2vUk!774r8;j#U(Kn9a+A8yTh#|4!vX6 zC!=DYNWmY>vi+CL?sJg)4Y6+i*iXsrGZ9|$`kWSu{RHg@(Y-`~G}B*L9uOd7bBv zgo}L+tGoXt`N2#AysQ3>-Q5YiBJM)Tj;;4h^7h4w`q&^`(95be_UF4vnmrFq4yYeK z1xWO+Jw?P^9r!{$)6Vz;c-=KhaHaE63SWQPeem{vI<+J#H8DZz zbmU$}abiz~U%Gv{z!*1PTC#Y8B_#pEWBWPqaa-^xCU%R-@^XC=q>!b*b zN-m5|<0(R5orLaE?vSK zj#Y-n3mIKp2}bjcM|_fCqwo~k zXOc_nlGtl@*$hO4taNYN=kHZGwNZ-8OC{LNVu&Q0hi;6?;K$Cw$j-EEM@5e~UbdcG z2yS%HD_x9Ou`zw+b6Ktzm4Ko@2Dr<^T`wByuP{2Vj*(II%@ak{z=L{0khpKxtI~f8 z;qi58zZkr2Brf-p;-DRODD0C&@hEB#s<-)$Ijl^4@*f+nD>E7>{6A=~nBLo~N{2fh zTTB6f`A3@@qS*rJR^L4KHNgG3L@l7zE%RU6RTGBB61k|}jJkW}Y527l#=a+JFX*Kn zYv%`u%l$g`d++HI^6mZ$v=#}vJCKIm;D?V_ZZr^oXGX6bbuu4(7p0fRh=@@9N4=rv zo|b@&C5o=GJu{sD(_?3?EAy_JZToTk)k3WHMMaQ*q2ln0xg))Fh5DdRRe98&ZKvp;*5FeJ$dW_tXekP4lmrh`ZK{uy;KOUV?uaVRej~xnLC+)d8Vxl+osw^-pw8^ z%-Xbz0sVV7xh!}6E!6WdW4bkR0Q&8Ph%Devn}vyh`BJTco}}?1W;%08J(rjViX?4% zuanyEG^d$9ST(ut$S}7O?Ewl-B43Z;-U+(jb8XVOv0S$1IHw$jTOitnzRqPK2G2pN zl$Sn%*{UoCz!Yh%9fCYtcvVt@YK30{V)2rB4bg79!%&2|1KbLrHyBC$dzEpk@xfaM=~ArJwF&{=er=EZGd!n! zvJa`2|1bG%(7&<&y94CQV2M~obT|`{5+51urQ2R+t24_8nW1;!i{Jlu7nRMNV$X$D zj#&9AZ9({@7A~X5Xe2bISY=^cXfq@#i@*x>zU5 zLD}4X_B4tX!+7UzMuH{<4fa+QsjgHtV@FFK8#zp2}R6^QvljOyfmxF{OG z)!kBaC#evMYDvBXY>c`X%!BAz_1!g_lbBkd|4!4$o7IPolAdmJbPnW#l6Mhlk%lIX~u6M;%2^D!&5?w@n-3_ zYpv+ar>t`G~gJj`#{fSrYr*@=(T*_;Da>}eJ@?Y7wo z3LAhWY1WOSfCG{(yh&;`Uy}b;iAV9wR)V&1c0k_9EEq!2#H57ovfh+@gmF2(ggDhm zg#u$`m%z^853wZ6MRaor9?8{RZhQawLPJB=ElI%}IE#c~^g`!5_i13cg)b#;uT$A+ z*U}8Jgwexj2bCPcq%zb<4}9@NipmAMP2}kuW_4HYZAS@WVgW_R$fe;ik969IV@(!`dFp_b zO%*mlZg)so(07V&)o}{sZq1ceh+D0yD6k$e@=b3(E3b5{=6X}rMSkq;PX4*Wm+Z~Q z?VnaU8cjC5eIUQrwg$@JgE;95l35p|hQD$S*%hw%;$9L2c_$YPS#GAJ1-psslO&Cu2}iEm6N1<;;M#!OB{Edj>u;Kn+bz<6a^hZ#aAEl4dXH_R|_2DVH+IjYKe@ zMe%4U5U6|^J@YpVB)U#&J0JNMP0wdeY3y5w?4Mihcw&{WZCgJ8Dev)gkMK#*oc z)JM;_p8k~qeMjYl7v2kU+`OBN!_d_reI8cT6`2Uk=AXTi+TmRC>MAn|Z}@GeCiyR- z0xt6rHvXz5F_4Xv-%-rllpMEjdiEJu;dm3$In~P;lV63m0w&NgAmX!gm}G)crvckj z$;geK7lnojPp~(*5N%M}=79uRfYKNOXwlneXA+c7krY0xDqHN;!G3G%b?pdHf5|e4 z^7Qa5XRb}+tSX{181lhrH_CTqCH1b-0@=~&=CCS zDc@xd^I6^c-=E(g{6A`;e!!*RqdWit3wFdrVUd?5yCch%^lxuFW(_U9u~sk=4yl8i z&B&jeX$WN9+bTXs_S`$J^!l}UvOMQDwp~A9^m_{MAzI89I@?SX%3OjZoK!Gs2_EnZ zyVlnmWVJkRooW+f9io6`*DY&7Qv=t~-YjOjeWTF7{wA|60Y! z4Z$83R84qu7E>!s_4EFQSgGDWHs3}0PGVkzrvY&DJxMG=)vR*k#n6~e!hKAYF(P!I zCwV|EQPlDmh-k8VhIWe*SOB{}rg|#hW}Uw!x$jc@X+n?`)|20$Ir^BIvA(z?k}X#U zk}hV^RK>#UJ(qelv^l;5$Z?_50Ty3lvyJIoxWdM9hyPR6yQgf%0VE{M(x(AXA?R&v zwQBK4xYW*}_qSXjNphF*kR2>=K-0M0Hppu3ct6?xbtf?H=)(r&cN_?H4)cl#H$ncV zDQAE4A5%ef*HC5xdkq!tf(2iqaZ))qGkRj#I`iGo!lR#W?Y;bLo}oMLyQ=+%qjo1495{n zu2v5bym=^Lx>I+kzD55CR{<1oD3BmxZ?D2zHa-gcj>pS{O$ncy=u791(J##M1J@w{ zOy8~q)5L+|8TZ_px++3=q83wid6z%m_^gRI;9p|&7Hhov@))5;{g=niKRMfrypkE8mt=$p5P}GSO6a4gp*~_gy!&v#Faq@#I_-`PwlBX;9fnSiAyWh$p@BRw>EYbTr z>-*1OWQ&jhMXP+{1n}xmjKt|f=k$q&E0wnP#BXT+uNrsP0u zVQ#`&`Sx?O;@5A@QIg&bov#QkfLuDz^{}pK)u?>9e3f^#<%E)8H7&?)3BHb4ERQX* znx)+zK{;9^2!xPz&p$iPyM|q=K;(YA_>W2W+Pyu1dYtl)DW(JCf^iA49Y9fT^>#IK z;Pb=g)eK_Zw=WgKqofinfJUH})mivBqFomJa`*#?vqs8tNv7*B0)NB)mP>W4PD3J{ z6Rr?cjTm-N-w2(Dzge_spW5g&CD(G_J1n4`rzeZO6NRv-D!))Wz5XW-u~f@LySKYl zUf!(E{rYBd(Hkf5C{pQ&9e*5}Yqn^)m33`xh+=}T5-W49Tl>ePsTV}KOck|L$)y%Bar7XTEh;Ok0fih{%}dS7?fce7J6Vf(H zo#(HvS|i?}L;g&NPtBxfzy;#LJT4;u40LRrp@BLsL`>&*&aiXor+_OY)Q#RPR3oOm zw(c*S$4yVWf#kaje|~lRLd~Pq8khP@3w;y%jtU~?FPI~md zaKP$Mp!N8QZ5mL~u$)|`_u2&$r0x6;=- z;<@{!hoq>%cq0hB1}#7bX!$z1v=#b-4qcn4#?pXR zVdCzRnOH~Gf5LAc*qjkz9M4z>Bexc)+)bjEkV}4AdkGr)2IcTVxD#dcuAPcWv#^2K z;`uF~`zU{BVyq^s;@qt)0cOfww<$E`JoTn{sU7V$aT5{9?+3w~$NpoobP3^;qN>4r z3k?QfH~&OxUm4&6o|a(oBdQ#ucSSb}?~qh`tW+mZqP*=?b+uLYcG0s(R}KW41Zkwb zNz;_!tezD{`vdst_ZfO@-+)ePm&j3ga=W0~JqQXTkZekXY;O`xsZXnUuqP?SQTcIp ztYxkE2W?CA_~{CfDmA_n5Mg)v5Pl6l24aD91`qC3A-->mCu0o6^{V!I4?}o7Q3xI4N%u98vNnDey}uFy-a1@r<-{lUf=P5jU z7G(xX=i}``o%JWBHZ_ICVH+xsZr9GkT?OR?LrxBgJ~uUHw5G3SAh!>TH^9|?K&g*p zsafBWx?gfIW1wkU@9MGq^|SN`xWj_1?)hE+UC2GgkXHx_N|?b5wqml_y7V*Egx?l( zd|dwO{egHd8$F?leH9;4JPGJ_8?#NBwIhB$L*_t}JJ2$rdSLcB-7~@Va%K$pn z7nfrNK%I4Go;xwDFNK~RKM9Wc9QOZ{?9SGOp-43^E$(*y>U2^*==G|Uf*`Sn|7#+9 zof3TH3vUBm-5xm=w$PmoO3!SNx>mvfWx>C~xT{FoC}JQ!Yd-2sJcuR|U?OWFLf8AU zndrs{CF!J5rIfacPXsA0uZAI5ni9dAI5#&_-4omA2o&Fy50+;KeU>%5`6x`lQ}6jw zXsBy-aJ-YSt4Bn}??|y$ZY7;vtlCgQ4Pz*`v(rk}7g$%nIMwUW|1~a){iy$2AhL-|^do^b>k^JJD3qT@= zKl}5l-cjpZ)HJfnWh2ATw2NV!??{b|^)kfO5hslga9cFQ2$<}s ztH;df=ysU>zz(ENx53VeE?4W3?5f72V9jW^*yGG+5L$4#9dJ3=S=ZTo4Dgr(&RQtw zr|wCtMenBOw@cPnq{+)50O~rEMo+UL=tof^2z(y@JPu~(M0?ehVux>JvX_$d4VG}>S0iNmQ|03iK(4_Vca@ zlnr?z7Ly@Ay9-Y`eMt&k|J|@}7rpvE^DjdiOu`Kt78u>?f;_fp1QJr-KRs-~w=E>D$v3U|e;H77bhp(D4AI1_A;7vXFd6XE)+T4w9$~ z#7hl?zgU+SN4hAr@oJ3D;$#hg3!OpIlRsN{QLGrEucKJOBlnQsYYE6EnJrbD`Ey~w z%K_wIocWgAV<7^RtXwtq5K}mYv}v9T-18~C|M%V#K%|4FX~z5H$XX(Nw`l=cG-9M# z`1u9m%U9rHVazN4@DSKT(hc7~k=4B`zL9ij9A;#A?TCK}>N3q}0%<&UpPJbn=3MjTiDO&?^&?XH;oLZOpI%$l zT<2q55ukeM;HI`+vQ5J4LXE~R?>Drx%*SlM`yX{)n|ufw<&uDkm9hXmL2 z?dN1LUqd_Cc`g$TcbnX;)jSOn&(K@tT}W(OX4LzepEoTX#6pnUa=0wQmxgb6xtFX~ zYjOVIz!Fq1fBR`JR_rc#OUVmR$pHNTGAWn@^^RMxPz34OuvxQ#sq2K(_)2v$U~B|~ zMf@~X0^Ke&oYdyy7f$R)gxP>T`WfL+Z5eDa9$E5p;2s-0o=^41T)?+$d z16}L!qTGy1K=Z=*CKwN1qg6*?It71Ii^$N=d=<+f{)(?Y{&02y&3a_9DIL4>kkt_v z;QjNmL@aQ$#H*`M(D+=I)cEzY)Gwc#nq_HLx+$B|@+!W~o)l&A*!NRKqnoLvV@LrE zONBto@PPcseFzkZw~UuxxVFwyC0a!7I%iZW{Bkd|L949$svlyF}b0Smxud zRbRu@Uq9YiHJ?Tl`Xer>3%>^QsMkWgK3L$N+R0sT z8CZPl1MId?qshOeLlN{%JHYQF5m~FyiJYF?)f=V30FJHu>%Ey?xA*;8e7KizOJcB~riim`0U;`nY_{IiWK)Ls{BX%44f~3|v<~rx>JU(!fEx|;0${W> z-{|3wACF%By!GJB9ihPJsCmr>mG{SGTMbbiaahqpJwSFWS>G`JK#>?U$@AX|uUaj( z>i8IiXg8usxs)%6eP}t0sGxWmr46K+vsLM>36S478!vPSM!?_0q$&A$NF3wL82ma^ zd~wzlyI8_1D{9)~O;X%4A6r7OR;hyD6@H~!+|2t7ajp&Fb3X2tv~V$y2-w&0n+?Th zd{*EEOFu!a9Sz>wD5y+~hTmb#FPvp?QI^app#%XB%{7zJucAGZH-vW`n_YferVIuf zwL@^!MVH>@{2Zt-!xr(M+>`a9d2Od`4PMEoh#<)O>3YipGa^FX`l+u(F|@?m>s2MJ z%eUoz86A>6s3Nd%77eC=mIBHMg6BI=Kk)}$Zm`CGb^JL03pgzO;@}p^mGE)U#RE{> zRm2(j%NmIv{V$r%S#aLDwio(qZol0VtV}s<3#zG_c>7m#ulP#fx_fpSIYICdPH8TClsJCAwLe0@aa+?uP89|mPh z+v~pEE+No2%q(ANf#2~;h!_7dnY`*gsuJ;L;PQn=J)1JP*m(cXCtJ}%I&T7nYWKfD zYAxF{QLz=o2UzpZUYr-RXIR*&U>p|*DF_o7e9(JT*49U{y!(44CRNZ?TiWzMd!p*g z>xR-~N{0Sw2+2~anUC917@ zup~;^Q_#$Q62QoP8sc#vKBz(qRq?yhiTC99lmD!JhfcTe^ zYb(s6ONB6n??BWv06G!zV2kEaFaK8E`BClY!dQd!JQqz39Gt`_7=YbO7qW!NuKJw_ zv1G)IpZMY-+ss6>C6_RNwvV98ExMPPp!vcvOs029QM%99~AybCXRl=y<%T859kRXDD-%k$E*D*u=ykij9lW|{SKRP>n)2?A|vY z6Zk7%8+Pc%-sGBfq)-}r8w;x+tHE=PpZBGePq0UxPf-!E>P8%Na!^_i640q1-r8TJ z(7Z_Um5fdw#k%M>i}#xQ+kOaI=rET!S^*rgqwPnFNSs+at~U|J?(AFm_vGw&YFaG( z`>oT8ALgH5*lL(Uv~Jq(fB$m)#2hIjyN50WUY`~{`Asd$$LB)V$DKZGTfg`jrzO_3 zn{ErT;68L|L*Urj5H&90MWnUPDd~zW56}7jCn#=_bWvl_r@}N=ULpRPPJ)vu?E6rq z;8@f>wXPhs9#`^4uSt#8b=q-vuv~5WfKZfeWzeuI_*+2Fe=9m>4nZ&ed+gms53y7` z)99ysQ_MG-(n?BfLolI*W@-AQBb=>nU53P4DX0Bga!&(tnBV?m`fD-B7{=6K+7oex zf~ISD`|X2j*IVG4_K-KvU$<;+?esr-e&9LLtz2T1Rx)zQqxUNbnE-&#iPO7_#R)Gd zJ~u0K31w9Fcs-AsFH%{=7@~neBJ-Ox4Q0PqbKN1pI*>^KU_P`u)V{@*SZr-?h?@(u zn`t_>45*wwz7>IXY^E4JqKS_GsVtV(EYxlH&HhHcpmxtnIqXpr_o~kNV;pQMf5=)fY z_E!@QlG@3&bx+sR=evQuBXCDtTX9DMr+$eRLQx^@_3TjbJki_!osNk$w(p2`9lR-Q zqMQ+5M4oS}c!#>Lxh-4${X^bM$Pjc-X|_9tELqaH0LwOtNu?29N@W`@JyAoA3?sUJ z%wq|R`?NHeG9oGt?T}qdm^hT_fW-Y{x&l{(%3*sKE(2CL2b-zW;_P)H*3|C**@{s0 zrL%8~>Ux*0${%njrUOx&S^DK%(&i<_*#dLVfVFHj34&<4yIC7toiVX+9`hv)xYAA?HkZ(WDlOnnzk5xkZ|f)xL~T zs(j(_^P$PI&P=;w^V`E79JO3pBRcym;pF0dn0V?t7r22Q75sYL z1#G~{ONqPH`{yif1^63N+Nb0+lN#RM+XS5hzcz}1)W}4xk}NysEUB9FgI$&Z`!^z2 zC$)!0L_PMI7CLnLgH{`Ttj|d&@ND`{XY6-oej#6dEP3fY(uSb^fR(0HYtL|y50QO8 zTjh2leY#{I!}Jj7Um|{**E_A~uY4E~?fV?~pAp(!QqOW91$fr5?3zZ?N|Y0`5;;CY z2cH)Bbo_%OZ2Gci%twr@{K}GhDc85vt)z*_T=6mUrDj#C2E7REg5tKD!MVcat8}F= z?4_cTspctX{DTHwWb-n9DwDYhd!7d*UWO!cld&R=!y`>K-OxfjY zaszgsk-fe?OV{>zBw&{Mr4swSTCxazMfLDmobla9w@W&c_m+53wMqL=lGPNcH68F> zL5bUGZ_8v<-W9!RzntKnd+%0HQk$L6`jd|WtGyz)$`g)S7bpDLNC-F7efzwd#`kWZ zmycjQzZpYI2I6I-UMKly!-w7jqtJ@$hjUIy}q)|7`4 z1)KjbaXIyV;40X<_r^kM`90&Xh2uAdvUiE``}_YfDq;RN{(rMo%or@; zY6H+synPwy0D3TIFh)Ph`0pQ6UIi1J=UGBp@nEUjga0*Fy7DCL+Ww81hahwlg!Ug} zpsz03hEjGXDfwvqTxyQQiAc?w$VMJIl>$JgXEG?v#7^T0e;LpKut08B$_nN!Xf1bo zo_m}gEts;PHvH5tClN|R(OZC;vTorg>cjovXq-$8r}>zFmW_eh*2}2AkbtiSszUl+ zUb0seKfc+!qP&Wc+%R#egYo=mobXq(HK=X0b;b3qCI;bgAf(Gg1j43{MSg8-WKm_a zfXbEh`ostN^)1`T3Fio8b}&KQGbPs36G_)_1qVq zt4Ua;*D2l|+SSYEJLT2$CFyQ(HaFD<_6*P~wIwQ8qDOWa0|Y^nrRuRH!<&Jh@cmb) z8n@62^emX8V-90LU5a8s5D58ts84NP7v7h8`Px&Y>0zEGWoE(v9%OH59fR(JBZ$3o zBN>sWHv|4LiOhi)k!Y34L$>qo5Eh!gu>3-JQG&{|XJ=Xq-X;BGf+d|yfN|C2)*52# z;aa;<1ZxH|=8)BP0E+tPw=Z_y7xl~z01e%$c+*EaC1^%kn?L?K=9<=grUb$>vv#-A z7KbC%Pg4TRaTI-9$bZnLo%JiNunm*!fWC`DJ5`m2v!Sblp=>vBRNgS1+E52GZS(K9 ze;wQP*VmL!5g&4mPJyK*W}lEe9}kBAG4)ap-z$5PRB>m{A%Zv`^nzsgY37H}-dPd) zD(bvS7-P5svEq{d4zX=cw_FYFgyrbLQyyNqjQFaQS0`6$KfJ+RZoGKgCq;g>Fvm}r z!3lW>AzDB#FHkzk6%-}BzI*r!+(cGZoWk|R?wdV1W>EE#MuSl7CA6KbSM|NLw$OSp z8V7cf(M;e~)gpQI0Hciull?J(4r=GXu@ACIA>vKwpAK{p;E%YE7u!l9772!Qy}wUa z?zs7L^nSB*=d3RO3&raie{M7Ts4~g9Pj@@Hz1ZwL&%Io3a6i9Wi>>*H&8lo%gcz@>lrhoW2%cvpPGXtwCp z?NjGuq_mj~T2CiTq=rzx>#%Vb_#N)_8roq)4dRx~0@mb-pR1!AJ1A@2Ct~mYR2I0Q zG0yd42W3H?MM;^jFY*rEqgXCOw$A4RX>%=T`{ojA#-+CkS?&53otb0XaO^1gwciu8 z*Uy}of~LhoEI)Nl%l$z;3AtzvQ2K_)bIE) zSJa;d0Kux^Gk4fjw1Z)!p5}|YpQzEq2Bn76{xNyTMDhSs4(HvE=!>Jz-75^XKA#MU zQb!G(t~Y84ZC8WhVe!<{P(Z}kG@1NxY=!{K792Yi6t!Q+{h3gGuloL_uh6c-+Vej@ zw|g5<9Iho<>&1eG5XME%Jfmocz&|FuO`i%(#6S!D6GqfLt`LoYRm~iQAQn{ueIZp5 zKJ!iAVPf|gH=NpTHAw+sLsnY^|EebNuKWd^8UBYFqKlJ$EdZ_J4#uB%(Czo}_Rg{{ zx(zQK2D)8uKv5iCf}{iKY7b^=!GMAyAg@5z+Lghbi0B8t{b^~IBih0($v&>42|;jU zyXB?0)gL7<78A2uoKY|^NsPvo+0L_2t)721XH2c0+&E_Vrp@owA3xo-an7E4%uS$yby&^ksbL)0aX@m2l$#=O92J zfW!#K;Ff8_^-&!N)p-dDw>t^wQl~5-qxjK{K{+_L)3zm^Z)}}=Q|s8_+boC>#a&1_ z=mNlBKvuK0$GZTAm{EQg<)wVJ5f3Eh^dL1#X`syqKg`btSMtQr1@8VXHR%{FJn!BO z*Fjzolc>fIQ|^eh%ghKYrFEeB&V~fg2Ea6gMm6 z1_$}=-^vSoLl6I-a6>btbdwYowKK)KjV@(zND0s5#`MwWUr$Jh#GT0;@XTTwo^zvq zeB3DjMfKfla#K9Mt&)#UhJB2&@V+Yn^g3p+cyudCfox6!*p@UkP9ucZ8U7DGw+H$q zojIFwcC7A{^cUsE7mJPL742SyO#st(uj%nLS*rN!c@S2f&Z3Ex%4x6+vAFEg(fITCV;+^`KaJ4;>ZE>$55b9pYM}1@@31$qxOyQsAll^l#Vd!L9y4k{HN+ z-~~X7Vd^3j0MkCRM*&W!Cx9fh88NHe(sV|6Cu#df-wlnU=%;sjbL6*QDdM+eIi-oaESZkG_T#uS4*iaSBO6fj|jz8zK3#jSumI&9-V{xbJ( zJATg)PX~JqGecv0C)F=eEOQ~yZ~YAOxagJC02N=};|54DBj7hpt^0+qq@gU@#$=K% z8TtyusmHZ+?$9NKY5~Uz@zXQ?ZVQ;|dckzdG`F3cKw7Ht`|94Ok<<;08rZpjVn#yr z?7>GsHOMYo!AA}WE6a66+DvR`4P$#MbhM0iJDk38QptvII`(3F;rm+Jb=*Lw&%OvC zJ%sapEH>l3CO7RyTX;mySO9DdK5per_*p+A3@yGAGkK>YTx^v|!N?3@qDf!eRJANT z(#hl4oA*B!hCNDsXml)3sRD{cs}^n2QK$R8w~qq?Mpdi6udpVwWo|~G=4k>2OI@-a zq3MWqNuuxc!Z~d5YUqBB8>lKWkr2w(b8@k|fn-2?#<2Ty9M_}$P(cy$MGfXfePKV4 zgJ{Uc>yx+?zx! z<^WU#+eIVJ*9*0f4pDcBIe|On^vsoglLQV+7Hoi?0v@7*Xuo?axtAZ)1HL@_m}EdG zJ2$6jR}OwHS29dEJZ$t-PL+rde*x(|mq*){K($ZpyYTh$@cK6(l0=N@aq41F z>>}W2865r)+OIthV?>OS*|mhPs5*uOd=AN^dNxPBu-HA8a9P`=4maAZ zuhQ(TkSbtoxk|HcYXHhC#Yma+L<`-8yfNGC)$^Q&5m!rFUxbLYgFnJ=QPPOy&K?KR zKg)ldF=s#XL1jS1zJ!^w$xEKcWykl_+UWWq+q36?=WN5t8=(;w#m=g)xPLcf;wAw_ z9>=6E*g282T<7u{j=e{B=EfqN4^>D!-t)P7xi7T#_^Z<#(bwVW0cL8?3XK1X23@dw z(pU5$S@3bp;3owC3GZ8ps5sI5Y{E8ecVFgoMO0#*nhbs`PX4vA-}Tkj6U-mb*-|C% zomSC*OrmhxE*5&l$yshXKkPeTScU)tOm+PL4w`7wek8B^#g)Kgcz+*xreEKHm$N&lP^6sU0_&VJiEE>FiS=iC)WZzz^ zD7Nx-Q?>AuQ5}q;;Dyx`L_l!D1)49g^PAo70xf5+cQBQF+m`x17x6a^`hE9f*dHDa z!XLWN3t?4dN{4eP2|f18CsTwcuS^p#?@sob#@lyMlp{xbtA zyPA_;7uFok*7}};JwyqwDLc_2;aA-Banq2AK@&)r3mx80d2b z06K*7Jw<=kiWN(CZij9$nDZ z_~c`hJ=9|o>t^+V9H6vtS;rsoy@uoVla#7qvl^@`qWqD|cb(!#Oyb`ZxbIAjakIJG zCaH*4nvx#h5lU8>c`P_5cS`Vl@Uf6g1d>htHZ;V7;z7DJHHhDKIAKZWzSb?S&!;Gx za{T@zc(n1D>~qCU!DRqk1<0)uWqOb`^*w`P-O9e3*;k2Nq^b31fmif6VWPi3BRKEt zH6%)nul#JYBw)Khmu4xTUSLi$+_O*aFBW_CL-J=>nm8MQsd(@Ytv4k@+*TApS(0yAQZpotVw(u|+n zyt@5%zqwEJ_pcbs3tT1C>EqUtZo9~1i=@H=0GJi`8w}}yUm=mhNqSO74@nl=t@RmA zz8$72QMUyZ^rqYGd}9v&0yLqx(lmx_f>$()d}Xo+M*lxtxXRE-8cRUjjMKGKd$L2m zJr5@5ha^fezNGKF^cY1uZ~%EKr^;e|xc_AboDuiB@(MAb`Bhcr9lHAE3&np-Palxf!E+bbmaL_$%SJ#i8678xE-5ea zsnG)&CTRZx{-_(CYMHyVGd zCDPU7hH^wbPIP{Mw>JanawTYv#!bnhNFSN1DarDA|O(fXg)=EM25@%zTt|3~=Z|3E7L zpT9AaWEd>o?`R-OpmdOZuyZeU62;)A&HOn(3ungIf~GhLg^gav7oqiazsZFh1E~#$wQ_nK=GZbSOsq*G zA4#kUZ$H77Y~s*QD9+AT@(IgG(}AvZMUhQN&w=Fk{wIf7DprR;H9UVKvBzZEHK4-h zx%xw{=Tb1BbUf=>TQdr0rm2igpSGWKKjIPddK#Jnq>q1fAtg{pLl(9C{uA)8o}cg` z1LQj{%acpc^P5IA&f6(OnQbLO!u7Gtw!mBX;gbpa;LvFRNBd=0KjOY;6E5F;$-CzY z;?iZdzs2M;bYzPzRhClxw0Yu?SH2k$>%dtzQT?Vo>{ri#+~aP{q|a?W-Zgph2OIUw zK+-+qmVME8>Bb)|FagkZU;(?8={S+qc?CWk*x`v4pUnkaHH3@t^JKGjBpS}O2wNYQ< znRvl=+m>6-XPsv^%>8kZBRT>VxIyPKJJ)^P6fM?p%%HtsZ5Fa{kvZdQ zVW6+u&$q>F&MjN$gI9pWjczd-mB;iW_qZ9<)1Y?K%Rlj|27WE8F)hyTc24cJ`f43} z{+O&grA-Z&rbw&RP$0O;#Yd6xay{Jv8co{Th-7oLB zoz`2Gi;w5M%QmO084z#C&qWiR8RHwe9rCmxDvKTk!TXy>8uke{odg`3wPp zq6xz&zM^8mPQFpl3swm zM!SZk890AmU*K4)X-Hu7-{T4(*IOE}T+`p9ePofoGRa$+!c`0ABgh;@iF}|pfM11x zr(Kp#L)jj-HcqsFORURJY$)xNz+6WK{QTw6LtD|>JP5(ItF%T{#G z){5bl-qHNdESmcF>_bo~U~@uaUP7E=v?FR}0qG{b64z7(0AfjuWe#<{+35at$4>QQ zwRoNI0=o!ls<<)cWf>;tM|XkVt~s3}=AT#_V%! zFAgaCs>$80B(;TbozBd!@)G*sx@7smQrnux+o#0#VZ{O0<8zOKNzd}%DwV(Zi}~TQ z?Mwi%%~E0?Q-VVLy<9^dWQuAK^glGz5B+1BRVn+jp>Qe=I|ccX)|Lol>eYdOkWDGb4wn7SsM{j1cM+-HgF2teLf`` zZ{_u=;Ex`{{Q|;4A`^yJ5I9Ed2@A>6bVLTcScMbp3T~pnRn*M%69}tDNiVYn*r~uB z$0o0`0zdUQC31HV^*TK=F^K=rr)j1{m+lIVqs3h^E7^DbSvz{pi{S268w9tV>xqf| zWvyDZAn@}n!21z={T4nmf18NhS|PnBL;+4^_d_+wI70ig1@k>${tGQf`=>NSW40ay ze7B9>_FY5G=#zs1-#mGmtvVC&e7sJa)XRF?boTtygwEg8Ps8Hy4P8F%tsI97{nA>Y zmQ)GGv;v~4c&kCC2Fz>=40grQbfKnX_uLEaA+}KCsK=~pPM<~oV(x)nog3mL`%WIL z11#3zn0et5|BJOOmqR)nu47zR1)Lqf+ZO%~)7Yq7hI1b%&^U{iz#ZU=u+yaC4~NMA zUORA;%1zyP9vtzcil2NSZ@V|DrXyEED=YS{Escid!2qD;%%7%g#7sWE^>;5UjdLSz zne-XwF)g-_+Pd_=qmUx#W9l|I%K7$Ik(|JaTJRz2YtFz`0%iyzxb$X~jaqgHcEkrk zF3OlK0=|G}09_8&LC^-Qe4CNuI0NrHInuSHEQiP?^eX|2d=x_|! zO$yPA5UiDQC#Q~cY2kS$dZP|f0*~t+3G|`Zagq&15vHN>8RhbC)OLA94<`rpPC)sO#PgPm>h%_a z+87fUPBbU{H>SFKt!?+z>q+-gO68=1g5gMR{L4=)@2hrPAn8cdKyxbWMYGpb{vx@R z_-OG;3VxXTzowoFpIgN~Uh^~COyZA2$8XQ=7=$7@R(TT-ZyMe881EWiwcHlMJQ%)r zR!gIuA)BVQ>b_VxIa_nmh{kiW71#73G1RfjR>z)Kk+9^q#fF00Dq9Gf}(a=cqma$5c9 zQ>ieY*sMs~@U<#=Mxkn63-O29WDQ-#eFICUN^WtAzU>eAT?Xz$@5wq zY-(YpApxuT{*?;G56^FV}sCqh`k&fbh5 zlYknfcEMTp??Wf1(szm-8DXG+tsPco&|}Go<6i1*s8?42ruL{a1S!BQxYID|e*M?m zy_D~kcBqtyp6A_S{ zJJ0Jpf7vlF`o;T6=|PS}=!lSqs?~5F6I;nL%oZ`bg%R!0`fLFjA8!wE%?mDem^x<- zpWLtZWiV5BzwbNH&$hlrO-U_yiMo+J)r$ww=-%8HsNwZNH(Fr?v?I91G7z)Ts6V}U z2LdM%3=r$O7Wi!J+-k6lcZok&jK(54=E~RgkezhU6R=OqKfqE@=m%+^gLEJ%mS_I@ zFq<@G{2X0aG&NOWOyWyON?WRhSXxpb#%r!{~7mw}SN(bp3 zTC3MwwNQY;En|7Ma4m8V5T5|TIQmbj#c4m{}|5Y9{=Oxysn9a3!5lN zy2Kc|&`;pohGs*--U&%74Qb~)24($mo#Gl(WL*wRe>dg%%LDF#7l6oe#mNqBI_x`x*XwUNH zL&br!r_tVxo^GuW(R)4i(`B-f6ZZFXfUf%52fjN#)=a~15hf?kb%N?@Q|&IEmS7Qi zfJ8I_SnyNVCL{MjLD2|DAAtDGR^88;?pol`ar=z zJpp$ABb$$mLb1`BKZlO^y_bGGUdV3yft&`EXPJn7I#etk>%@O{5@mDr58d5|&vjtU zM$BEA{5dy(zPjZD?Gr_5rhJ1qz1oV&X9N2Z`lyJbG1Y}?!*@}Zd>_{HMCOR4z?ZXP zqm^Ds?b49b)k(QTMLiz>)>*$`T|@sVB*42o<9E|)_=CC33y=VG;2cql_|(L|IvfGJ zsmSP%^QdaX+X)CdkF(N>+Y)!7zpp(kWMM~@_0YA2NKXFG1yC&=PL`O#$F#Yv#K0n< zlGxJB(>U>=1=IQ7y)IV0w}RYmX5yTN@g~39>$@Grl~2dMu_q}4+J2Mh1^3Ehjq_E&qmo;J9veM`q-&N zL*hqfHSdw4CMk|ANVLJCLTh3mpAeL$tCU|34{b6#8}f-@`)IvBvH83M3!lV4(srH< zVHu>Wr0|wUK@5O>0nB0UCx>anf51`qKTm~JhA)^5)Eb)gu({AD2hS(He|R~q$n1#I z2pTA(N12FEd6oKK3vtO1}K$c==@&PDFOCo7Fdao4t^s;Zr3&s@Y3|g;eGTj&dDXg+UVQ78e#lqC3kKg&m+T;A$Jx zKHXYh{^YzyWi(B&z=r;wRn9%1KbXt#J~=wJ7Pn?d7L2>+v0TCetl1JNA<`%1*yU>mCYT)KQ)yGgpB1!*T3Xri%7sjRIXVV@c;BW9CR! zxypHQk&YlqxlL|V<;YwAuvfoznER+GY1h0`Ts2)qp4B5ZcNCQg zU*etwp@+4p=%X=OevkU8TrfBa@m%uLk-kqb$WV*u7xY3wu*Ita0ZO0cO3_wPR=kcm zEfLI_Tx4NFCA^8^G&>us4h*4e*s8K|8bE&lXm~^?fQ$oKiGSgDw=HN|2)ub_$czsL z3sOPzEpLnFZOC32UeFbc zDJwT(=CPj($X=|2BC?@u0MFD}xP6Hz!}_*?b&qdG6Jts5|EG0_U`VE#B187`v1RBT z?x%qIw#=4^lr#eL76FZw|GiNDJNds$iR8#MK^ORNY`wUmxu~`xaTtWx2Jl()swN;` zF#cfb731hrFZW4v%@>SUNE&3|v#~nMk$}R#nk3qqBQNG>*W>>BYomo3kB{%slb-bJ zaYN_bCQ=+){Tjhl*h5TebQAB|;axv~+v}`aa$s#|))4g}_?7dd2ENVw^xpkwtx$2| z9()6NwnfTs5g~rS*RN?slBK5x4d=DLs;>wD?DoWVfuC=Sh(9W6_>s3Od|tRw$RRNWM`vjmQs9 z(Z~+~uPQ>sQYBeSda>@}N>}@jLgn1&z7yVmrG+s0+@V5$jT4oXYixTq_)>RhhaYUj}EVzCgb9an7o zwY0!i62_3F&dt&D2p#F`Xwm=Kj&X7yIb1)=Zu_WUyf)>6<28sH2&pz5lXOvBnTzAk zZu)j%VBQKx*l)Q)O?Jz9BZq`HuO&frspIoY%dFaqYD=&G4k1^wk1LM5Qv8XD9(~ag zDcqfzCUMkz>+;=MriY^Ol`cab0!=m*`@ojSt)8*wSD2>S;WCq|tUfn?`+liY(qG+6 z!#`W2PNHS5J%uS6!LG@Ky#2D*t2zqBpAII;R-1iI!4TccIMd{thXF7DUKzM@ij;Y2 zWA=FvB-jKpW4%aSO9i%u|5B`N#RSo=LFmo2>`L%-+VN*&Mz=UERk->#z_lm3_`s}7 z|6s?ofR-`2=xLRS1N92qK4d!3>JFdP!VK@rIs9<=mx95%K`Mi3z^sF#>Ov`owv=i& zf@wUmQ!g)Cf34w>lBBKQ0IW>{Fg5#e(xl1Dxzm`?Er!>7NbD%fNbZuKOja+?TAjhB zB!?;OeNBi^wwOQB?Lz6+4`|{kl{jN8x&=YHPm5TY9wdW3_J|8wc)`QC$CmH$qJ9rS zM>uO7B^|_ za0=%>ja;PztR}QU)_C9G6$smGe*^4`@Kv*RHs@bF6v<1?)Z@^*K|ENyHoE`H)@g~? z?9LQGnte)q;&K%W=F5#J90LSIUE`qZ=XKKDBdn$3DwD69kW;f^ycqScTMNqH={{Xp zrd8!U>iX=>J?qAh(=wlr&-!exaohTxAV=|PnQ^usOfhzB>_v(A=L+KdaL>Dse6I|v zkt1s(2fF^sDqn=u4x#yj|Z0+rax>bpx%Vr^yqkM7a z(#n|CbsXNHCFFU^8zvdOl`N~96(v}S00@1!-0O_8_4mmgx3{+6eieJsyE|14*lr3= ztu2f};#&$Oo69liO1iyMT!{q=XV?j*RtYTrN2+?HvE2qRC8T63l3aT8^PZl?^O<8C z&w}twSj+uWy6~mj6(h)ecz@t8?euiH(Ea+7na!m8%NLXF%#U@OTwf*%f|4@Oh2~b; zsBp$A*X{V^;TT9mLM_P4ZRh4Y(Zvh*sY)NaaKL+L_pDIJTuXP?N|2Mzi69;%R)ODk zC#V_E4dqDX%*^#Y{C06CHiYU3jsATl^^V}vG3Xv{17tq$n2pItOHkZkdW zt91AObGStkwblkH@UYH+vTvS{?Lr6$`mH43)f0GVn(QlXW+&bkxtFnyedanLO6mQ86j1sTXZb5-PMSTvU&6~Fmkc{4s zn3@t}R8@?bARsd8D$?T|Pm=ki`l8=tnzmT}`N(ez5uZ|`tO-it%HAII=S*ff?8;#Z z_#(=)xT~Lk?Y`MGPRb$FqePn&niTZwn2wdmjt|Dsn2!djuP%zY)zDr!pKCl~$@-+? zp5p{rm2O8|3xbU8Rl~oSIPRp(c@@|*bxXBKA==Q<&2O1u>Dq;A&x$4YYLDvUO!U@k zl+a&bv_VWbiB=x~uu(6(_I=jh;`Lo(sAyFv_w07H!Qtm;F5p%&Mk(h$H#N{!=!YF2FC&6eDkrJ8JxMSl60 zfg~;&&z}q)bxFGM6%8BS&;%0K-c(iL^8<^6IPu0p%hc6j{!%%Af1B(( zq+2;xJSX)0OM!$Sw$27f<*w%{b}RdT*x>kNEkvQ(DgIT22XQFQ*+MG+=f=imYFy_; z*gMse;RtjM-G5DY5r`9f) zlquS1rjv00gcpdfOU)WLlgrfUw2^Sr64eX~4G&;0{@B2`XNP6$m`g4@NVW+;Iy_8f zD(LOcZsnA9x5x*ggMc+h-hYjQt*3?OcVaN)`DK4U;JK5-degr`U+?+A~RZX%uy?NS8vrJtBljQ*4WD*;9k0xxywCdoP^1J zzL3uuab@RO$SYcNo+Q~sNvhMD%@!(t3h;Z zW=zf5>4Rs-YDa#q-3XY5T*V$hGNwEA1_g{uOiwwbO0hV##QK{Fgtz1c*$(AF?4`St zoQpWjR!!=77rq7gao%z>W;L}Vla_9^J7cy!p8sHfgq|=t@SYqjIJQcRyq2V&8`Uo$ z{iN~IsFaz@8^fz_wC|-w_c!PMsBn-BP>EhOUdmwo^an;;|3r@`;v?J0^l`U%asa-_ zpu}hWT;Z?eeWR1%$PxK~Kc;X!Pm6QNwrJRlulmEPUA{}uSNH4n6~0FRXm;!3JwWCX zX@Td?>YNGSvmkP{ERqv8cg6Mr2boLJFi_hyTo$|xbs65fz;@5gMypA343ej|c&3xm zU{vsZ5Q=;Y=Tj@sTL`mM>tp=LRY$X^^vbs!;%L+TgOCQ&DuZRp#BO>3U#ze)f#lASUvCzo8`+ zr`aone>iT{)WwBRR;*7WiPm^33_J!*D~V<>{Y(36cdEe)mEhP&ER5{a*#;g;IbpSQ zWiX)7`dw-2t$!&RFRQkk1Sb;kT98Ua;*&{W}grF#6d zn(XCd$b_G07t0bA&K15!EA=d8SE(`LfcLA7G3NaWs2}|cJyW%YibdNaLuDg7-Pq=P z+`KZ%x_)xq4MK}NGoY{|G*%eEbNh-tRuc~bhcdlVOo|%&D7>#VdkvQPS+1@xJ-0~! zhlk&DDk5+S(wXS$=Fj!Wt(tpkO`1G=b@Y8c{8x1ultW<3RQSc)+Qi_gcPS=)Cg*Y= z!ir99UK}=@3Y+a*YUE^q-g=nIJYb(@uGF}`iLWUX;---3*!p@Gbkm7Vqw6TOFRYzXTqdulip#(^`xAD}gCm+bx_)fW z9n8KC;@TAV)POBE(_HB977`?0&kEtP)=H<@`^#V+`eYTrn(Ycvh()o z`45b)Z~a6$`nyHHsO^{FpSM3X-JVj;_n2<6{v&(Bc*r26K-CUu@~!<+|HDc93vKw{ zMUbYW90~Fk6=A9%@_~(E@RdEx;8%%Ukf?5AWkcP#x6*`5!SQ{%G{ZnrVZpLEWTAX^ z992d&vrMn-kyt`|cEMO9mzixjw<_nB`hJ~YxTUgh3S}oinZ*(wkn4JrE_?}o5O;LF7-}a z?(3&4w)3B0F)&G-W-iRX7-F`Q5j*Ja>&rd(tlVRm=W|tsLZ79Ejsck8!#P*!9pB#J zo+PXUA9zL$)H}ZVKFAwRDt+^e#a(KaDX&)eC}9K%=|;2H(7q(-H>K)KidZ)_)>$46 zN~H594C@SaCI%1c@-lHJufE4s7*IY8iza^tuOyh%{6SPLckN3JxlHr>3b&Vl>Kp!u zz*dY%{9Td4bKrlVcks%BqO++h=y2C}8PB)Id3}Vgu$icbB#}p3dz!)R=O$&5`v@G@ z9PJB8$3A9Jd{?LDEADz)g3gQWx|@sp+Dnm^1>dyR!&aTi59;yo)l9^VEi(N@je5`c zxi^9PZ8wPM$#fY>5GaBH!BqQv?7vJvQk1&nr5V`Cz3)@s&YoL)fhyuo54(nEeU34R zc&mtUVEanfq-5h?pw5<@LeOtW8|0_~1h(PkAsGMO6XZi+fr{O3;l)bt!}I)7yHXmw zWaIWD;)>->JStG6Kgc_`-0M)6;6a3ANg#?*+Wy4UjfxnIkHH0Y{#O{G`~A%a%rK*$ zn@-j5sBZ$nVSW7fkEVaDvuxqxpjvoSNM?J>qwye>8%@4C4&y&}89T%pl|8P-ujUrS zNvlleD3B_N`Z&-Exfxs4X~8zS4>4)1%Cgv=`Y|~rXDIGsa|3m+&HscCce%VK9eyIp zM4p0B1&J0({$cec3c5UbZ7FBX<}AW-Cs=~`tGP3|T9KOcOP&Rb!kl-0X%fU1nvj>P zs>jRXbG>+uQweG>_hl&wh4xR_K;D(IVUVfRJtueG<-I~|&ZaigPwZya%r#VE9Z7(C zCs^YD1tk7IXyX6y7nBFq=4$Z>3&%`YlTT{~LMaJ?j8z~ZQa?qVq;e}*L9@}jxVgdCJi$yl z*FO7~0)5FDK|5Q8nkI8W@L#wW%89sflq5uD(ssl(gFIWCSQsjI4C&G7_$6w$aK`s+ zOaY{VFMAesY>G^eHxkty47vhvd$Ln*#247L*7IrKw;C-)J~=PspCqyu5x>E^(W=-1 znmxZz#PE?F=OaQK=YvwB0x1V(Px9#RX-AoyhqdtFW0b2?)yE6QEw%3Sp2-FvxTu(# zRyer8P4iX$i^H!j5Rm2H^SbTk@F`LJWBqSBc<@j&`I61CR9wG?onM)kIa_;4!CZgo zm@1oNR>Gi3<;3YHSP4R(z%ZFe&%*Wnznt3+>W zD!#uzS>pYyOLk(XugzQoD){P8ld(eAW|3k+8sX)~mT+_}xD?=`ZU@@dSYhIP?4~4nUyiTHBA1v3{kDt%8?9zMZR6BTcqC`esr1Nd zyG|K@o8BC&=)jSryl|QEq5~bq=`f-9HhkA$O_nZvE7)WaJvJItd(x%jIQ=+ZV6;e< zelCERzIkP%YC^<&{hPl>KgYK_s)GSbKr`2B44YH9x92D2gYQ#nfeSlbFH8BTs~hY+ z1Im#uE)JwPJLxP-_FtR7@S=urjrvAIttV!m%H{M6ecVnBg`OpuG;5Z&eQBNlff zo^F--Pk%XOnRd+~FA#sT-{3CO%gg`L)~<`FMkra;*G`@+dj11fp1j4WvdE*SDRe?3 zW@Fh89rF+y(G$F1tp9$AZ4U*TID#|(HE4M}DJf?KvgK=w9*h}{2>8~eVa3*Rt=2w3 z^VMh~F)_iS?Nj7?*y+&y!s>Bh?xdki>n`c)#1Do)RhjgmW}KQ%tCfD&?vraMdugxn z0f5sRXz#};n4{L`uY>lf4t!D7$i?S3OiBDQ;Da@AxX!gb1YQ8V{{R=$2?hn3V*wR` zMdEUsB4^6vhjC%8x@~UF*sr+FZGW{TE}{JH4zpNUH)xa6UMKFaR+-gcS$vNA%dJ&NySl-Y zqNtyE|EjNY^YpX7OYb{X<>!A*)VbDg$sk8W=jgPt%y3{~VXekNVorUkvF(mN=Md)v z>-4g@k*0U*54+El>cY*@GbN^Zh&+=ql#$H8&1F(Y>uz#X_cn%>2xfSMIl& zHTW`tBc?!vOF}G2^RsP;isjb6E-)GpP?IS3a1|BTB$Ofg<&bNlRHTM25L`Lum@wN% zAFb*y*Mt^JAlw{Mr~`-Q2$Rx+WWF!I0Ma`GP%$-5G5J!*Gds%tY=PRJo*qpg(;pLa zG{xeR)&ErOz(P!r?b(56nYe-?Y{p_Wn$id_s&|x&cyj#HXEcfl#WCC0L!|WfD{O@U zG8;E({9BZ)07T+dy=}t927UCRUofGG5%ZUyE02<=fb4B{Ll(_oWFO zK^pja>;OjVOOWtwDfHbY-k&CTn9ip^+{b16)7Bmrc?}%PVbg`JIgd8{l?_ANSJ|5E z6kTNB0C?VQciVJxlheZI&10zE9{d1-m8e-u`U=>-?qcI&WpkSIc8+%%eil8YFGbOC z-KE+ozVAsMZVqN5yd-zSafcYb5Mj);XW=w+O3Nx*K*(;&P`;Ya zxOB`B*a(^ldO4-`a~`soR7n_ZW6wYfC7(D79>_}#00*nk+_qd(zX#9unPT6ZiIwzM zu!XX~B^MD6&$nR77ROkX73nVYC%`I9G=~Oh0FPS0pLQ3CVE2?G#j|CxQyh^<^}KNE znfYj3)dKMEeqo@{{tsA-}Pv18S9&tK#TZzxbwbR{PT!xNzchlNZWq(e|zsDN} z>OpO=X*!8A9JjCzdhF;O&BaZ@1)~3^I?-|G#pW3}*3_FXXAee_a-md8&r*{7rq!a2 z`V0)~l^z}+nl7>62eGKGhO|+6-c=xnq~)Vl(sfK)_>doRi|V7Tw+fw*zVowhT*yEL zc=_cZm7+dRkj=_6aQ%$W;PWUG{FZlN9&lu@Gb;3W`g(NlEuDTBG_jd@{*dao*o-^G zxTi_ucKdTRBN;^_olt0zqyK#&hQeW)gZ0@9BrwmJNEu`r(!+-RQ-rqVjE$Y?mysJTE$7zz~WGME%9qvb&IWqOW@3~el(?$x$e)c(B54Kc{`m?27sk1fV@H92U_Onpu+gatqXq}oVNF2f=~70 zgg1o+K<8_{M5nP%d|0x2^v>#r=%RpG(R`EJMI(#)lhWS;iA(1&*aasWZkbFqyBdRr zi!BkQztTnI2u)ZuH^r){ocTM@Xhwin^=}aKW~7!D2wI)UFsOX$*(Fw`ON-9WVHK+g zcX65vj#Jew1Kh(c?R>=kA zSx3wtzn|^^LNca_jEI%mbe4{EMUbiA>a^Mm7dznBdzW8!nK-7hyLi5+~r$<4!{8)jER%RkaOm~UHTM^Exbkqsqolb z3ubN-QlYoTLnS+=+RM!(d7aMBP0&kTrOX25SKs|QlqLs)tntcon;q?}oSFWV3GNOb zTy7U@sx`S^2mdNheCR%gPCuspT@qEM!zQ)78l3#(X#8FM4(CtL4I-}gRlXh*bz`OrP`vD_L;^VL# zJz&P4fQx%a(6r1~TfH%G_sb82lTgyLsB4%O*y3pgj7Vl{ODU+m+aqv@#*Oho8+E#GB)`F6Yb+rfcX1C#HQke@;~F| zigYJz_IPCpP1&`m$ibpFUGu6qt!ZXH3wj(X2&jtoyEe0N zbRCK9n$jX=PSYdg<1#=0X6m#Bn>U!`(NVQNTb|dyoP%}sNIjaR64!oZ`!P&=U&{F4IJ=!NlYL~oF zZf)iC{OS}($^cA_AA%?=v4`ynf@hAXF|SNQn#-xMhOmfbPH-och^t6b&)eeTVfGL1 zUBMeqHjV~3Bn{@wFSClb7eQ4%JBs#gx3yOi3@opRSRMPZMRK7TT3?<{7tOyd!_nKu zlZS7!KCN5vJZ9Z++0VZACZ~qf_zl*e1mcc@G~1$P=}&@{rQ-7aT{g6f&eJNHTF;R~ zz{#ek1M&qyC;td1*a4%jj)C8)zMNYy>hkBDUK&l0IYp|H;EGp?mROaj zAa@+VEmnk%ccbrR$gXGa&x{rFIJ8(4E+$m> zvt{9Qx7jw(F*&~QEsM@GJH|Wb#;BH*e|`_I&wqwVP*d^M_$xHXq&Ru(KaBg$5kXZh zYp@|}Q$M;beC9NxNu|9oy}1RDAZ>se$u|yW&vC80foTX{=#){EGr#{XEyMn2%7(8> z4{wYa^`ZwZMibj2$O4voT6Jkbos|!I(q{Zfv`TQOO_TVJliV5MjjkT(|j10HF zZry4O(X5~I$vFL&V#W%C?o10Z#aW%j;nOjj*q~+l@}Aje>3SCxH)Mbc{_v=-aR}Ib4K$4EkubtuVO)u_c zs)mtH{*extzCw9mBRri!e!Uv*Y-Kk)K0}PeO1D2C+5yAy5?@vBH{bqrr-i<%BGDnD z&^~EaeGBmTwTwQo_Obj~E*(6DoCM#&L)zw;vKk;^&)Dc_=G3TVw|x?f;hEe%TuMVr zH3gpOK+sXF&B0OkzZCA;rd3Cw<7b~q4QT7-d-#}EG(8yvA=-|Kh?t+48{aeF)Kr5n z&Akx#+OPcgCp93S5R5(muVkTbwLIQt?dgKWqZ#BS!Jln#8>?&_Qbr~-pT;%ZC4}f| z+67gMIRBAny)?7_=vBFslnag%mUFhd<8unucox`b{&s*Pe50w-G`o^Z>w&f6XSGnfLASbG9L{jPL-&zBfcbWLIWw%VpPVJWSZ&&qVi(T3LA0X=hzFTw-vPuUhI=Evc zOzm3KixF%JfOa#cUqW+0X{b9YjN{rAjF4pertww zug2h{%LBn~ZR!@X^f<%5GuPl+_3?0)3^Hj2eZe|*DglgK!{muwpH#cUv%iJjG)=d! zocs#ikTbjt4ntL{9DO_e)xFm%DerE#(dC26jf;ABCjk0Qn$mH~@~@geFR$Cn~i#EQuB*Fd5-u9o5C5;cbTC~3K4;4_m z7nBd@_io%;#R$OFbAk(?Q;_O{T+9ZxAQ@|EgA1u^fg8l#2l~&yNaLiC7JJy$|8;-8vT)o#ZNqt@2D49=&2TE7(xJh?t-d zB`CoI2-%iC7gY$LBB*y;Erp~1$NA5Bm{d@Kn*oy;`|kiHo|acZDUA70i!8&5rLDLR zdQbPeM5qWgkD1wv5)j*J-|cEN1{rU7o9CP|zH_CFb~K2RniwB*=G@X7`*F`-i!;}O z>-VWKCDVl{aNnHi7swMyefJW0%M%KJE_g5854&7Nv#zPjbc~Q*eHQuFtTkXFc*Jn} z`#+!DwLK)Buj2v&Bon3ZTp<;!fcIZKLGJbc|15Oif2aO8A<^b8na1EVM0yIny=rwG9MNqjgUZqBeS};kvcgpi#2;=X-_fv^#ZE5?qbSwPzO<0b5A~ zF$MW!k6+=)F=g8+o=yhuER^iTlG%BBIpx1*zIgwF=yXDP_8#vKT+Izq)@o!skaq09 zvckHx!{!=ke+DRglB?Gxd`6nEA7n8p9Qct}i=-7wJrj0dRBtocO&@*5KJY7X^2UBG z*gu1|UV)ej821B$mv5ClI3s6i1eI&1HJ$w}h5J_wi16^yD-yw982&2RNoE1{79Kw; z`vgmv9@XLX&yv@)Nf(!2@nul@gD-{R;cCEDqBK0m{pyzw14ME`ffq>$fo- z1$~!sB3)$V!$sc4$h9lQ^MA&h)1wPR0_??}Au0bU;eaQH`mt5%)FxvXZyY3Y$|b4q z-k&-+{Ad&;Fv@G0Iqydiv?`}f>7n%E3>INUvi6BoOe@QiAK#Nwscbz}t#BzMN(U)a zOPL1aG?SF^=KOT-Hxl~xl(eQK^iDkL)#*~}c9LT;g+%^0#_!d6VIKU-3D}O0((W^f zB*piFdAkoP7yGxslSf;lMhPeAaKZ3J+fO-Hf0tb91S!Cc$JZ*GLYFWFuc!;aeuj9# zFc$fKFP`G1sld#U{M7E!;B2H<;EkE6sKw}CEk-xd$r3l-SQgA)W~tc9dokviHz9)c zD|XE$NU_;z)E{cu1)dQ3eLAy0an^YAk81v{aj%Q&xvsN+O|qv?qcOREWGpPhwzKW_ z_pr9>-sN`pi_C9)j%Ryr==@PRY*dfBl4p&Y0%$I?fscQUx!u2&;Wwl7fjQsf+szL$ ze;qt2Yp9>4tVnyw?C=i=*Fujr%QJuEl+s+=n^}Ck5IA{a|JIC&KR#FtlDpoYQqGoj zEWw~X^3TQN7?6qYycfUnp%gPwDR{9sC%~)KY+I;}D^YmqQ?x&UhW&%lq{ABk({o_3od>HckluowL-FMWkEC^Y zi~f798a1haX!s(^%l`Y`(_{{u4o~OR`jSG(Y(LI=HvZV?{8tpE47a3bSD;o@O!C*N zuKPlJVsF(mjU_6Tp6?F&M~y$z=CrK>2{w?Q^<;FuUVr-Vc6QTLrJuJ(z4-Sn&mq@? zCh4teB+6Z(%aEnv&SF0!{M_jR4Kftb-(0gge5B625*2df_r|)Y0*)ovWv%<;PVaMvTTVk zuW|RTtKBzdBwua54e*VzSq^V_JO*fVAf0u6-kH8vY;6?7T(mQF#?6R(xl!BdOfh-y zj`h;><%Ly=JTHM-80A}gA#i6sWME#rh0@ks{b6Vpls6Yu*?DrkWkegXB)YKH^ z)#*q~P@`GCRL?M2i#%;4Nu(PMjpi!zRk9MBv^=^jVr`S6! z$&0$rI}E~$H8=H+E-R)UHk5z2nC=x+q!sSfv&YqayawLT2^3%t)C}We(jc5GS zbw|qGMuiwlV+$WJ?MRYJFsCL=;>oAp`NLs@4wHozlfKk~r=A^vNgKKKF9n$!9qL>ox;ciMjZhbl`N)Zz*9Snz=X{xY#;?{WtDaf{4` zcO5sI+)z*9G^0h`3Rita#g_8KROFf{k*TM{2g;74{B-Y+ zi-hTt7$C77LrdA<|E0jyH*v||B8yEhyzriLNi+``FW^YM(=i(d`ytPCgA^WtR=TX( zbeGjnSnZ^rLfZg-V!{)Eod~rF@(q+CT_j>Q&x}^#aKh$)VI2?f!)kW~TKDAXRu+AG z$iibpCd?Pw?xND6lr!8X%`LYAzk}eCOM6ln^g6KJL?}}3=G?|3B0K~`FYFYFD$M0^fd+r;de~>Y$UtF=Z5|& z{$-EGxXc-E_-%ZS8VMgR(@U-u@37?1yGYKEUBk?){!l{O&_3+F`TLaZR`qPBZ-V74 zc`s(HV2(lk-j1B_3^b|W?R0Sk$B48cXY%-9o{`q0NUdz3CZfS!wZEL}W6_WCqCT^- z!OSKWRr%hbr*hNkc0Y1MMBMswzXpBJvP?9|mfZdI;`zZDzoP}aYUJD+jlkBX4H-yz zQ)Vse2Ru-p6pwS#@>2eEKTj5Lb;}(^&>D%{Tbwj=PcVzmck;H8d$H-;! z3!XRpwJ)l+)ZZ{;EHTuPwZU%B{N@~qNo~?-u51IZ&_I0rljEZ zQ(pDCPA>jS@uBPXXqVRxWPU0???*Xz!cmV$8PTDTGJEq#Q)+*2@?wKvNqmlv#DQ0W zTBz`_pHd~iG|IZX*B@Pd#puMx?X$G5|4R2b=V8!9IaGqkPfCNz1UaIotCu4cSr9s@ z9rS&V^Xd~BQDPB)Y&L9eD$l+Av7Ti(+_Rf8Lo9RTWxP#_C8f9?04nfIg7W;!e9%yA zD#vKvC;AJ1P#iP>Is~pd2TpVL%U^0Ou430>X#72<1HSb`2W(jL6fexYh8CV2IG$Vc zSq~eI09HHEFR;6cijK=y6zQEz>|$N3@BcwvHaE(fxct`9|D5>S)fc1p(4~_gCDRPX z!1r0OB`ZT{T;M-bqVjSW2k%z@Z7ky z9v?-<@g`kwdcFEOb^kf;TZW0u&^u#cAvxdpELrO-!FGqUD($}XDp;+viqH_^M0fgSR58Y@^%P-jb>%1si2BQi6<$GWKOZbu!iDq^aq&ODwbk2~PmK z2-u78z#ECT58Pdp8nO;ubqao38O6gEnpf)lb8XjfTzjSvya$Mzu8*NI=Jv=VmnF0P zn78T$2Wf%zMt+!}=JED=XYiT1-?FhCl>m3Hm;rgwnoPjbq;Pe*mWBjue6y;j=eB^l%vf(ckPsnnK- z0m7c%yaFmj1kJ~th2m0@6?3iQ zd<#TVH*!(QQg-hFRaXeP2J0>(BcDP3mqM*)2vh{dY7o$(ZJ_G?FItkDc<&-r215Ju zeBFO3a-)eg#gFBFmuSC`To|1m4CoLI(t5jkNl5qcCrZbG=8-!I&{XNy{pXa|;|&Tf5uWU3j(T3B#zNsIWAoC4xI{HbNz=U$WPiqBj+M_xygN2tdvR1Q5qvpuUf z-&n((bJ79hV%p1+8qJ;ZqJQgqxm%~fxC23WgNKFPz^9T!$XphgD1`j(VAxQ8T6>%K z(Q8R-a^r-GZ3*bB3ALcXNxw za*U|hn zRck5J0ly`G?b-xpLsdA)P`+}xl)2(>#!pYx9*PH#oDGlM&)ASPD%J@S8iF@o&%F|} z`b2R~u9=vGw^wa@TE3Cg5Y!!YD;PV?d{ZhaJn#HqbOF(q;LH{g1R(3tCZH&JzE!tde*+@VO3xD( z?LCz2c+d{@Ro=-Obu$L$pZVX{pChYIfOi|#)7}70I57%NkOTWai!ro zp@M`gS3!~X=nIhe;r$2u5J~6=x)#(0pEG;`I6@+V{9S&|Z09^kba2Lum6Cfy4k#!; zE|DTBtcpta%LcX@U1uB1~A{D zKG3m$DVSmQz+8?;+&P8ZF`sSj6yKgob+)qSMs+Cj#H}PgcoF<(7Th&5dCxmzxC4n7 zNR4V?$0IS18}s~ltC375QV8LRn`|_-41&i63<6T3aa zs$7{BrX?FQyFT&gNCZ0WZs&hJVf`z$`D4r}g?F)55sedP2mvS-TE=Q4<^q+lw&`o& zD}GMuNo}J`0xiifH&+y$AFfI)?x&3=mjy#?VsK=i9hpju;1GhqE1w*~@R=q6pbei$ zt~dehO%tv{$3QnEhe3WFtC0~WgL0}`x15+q&CMO}YTaAV0QL6Q9t<9RmP382le|D< za3AuCyiKUzcoZr1PDRQ@lN@dHTpv$G1bs>JRet@{2XeKsm_tNczM`l|`InJ`c8_}4sh$2R^61-GYCv(3wjE>8;~tT{aH zgbgs#I8~r$YHksWq&UjpRu)S%!d=>(y5%Vq4x}EzB8_F;b$#H6V+S2z5x+Q>l`7=< zx&ALjVed5%RInMy!=eeghu2!&bz{e0(`>1l*y{*47P(!)(cz}dL}JPG3&~omyi8+k zc~VoU=o-O7qg?zeaTK90l2j_5o#EW2QUJymGyF3Jq+~GuVyUtM(xU>{71H%w`ZE=a ztbXtMbFFU6{x~3YY|W)LNYzrgRVmU18E9jO-6nz3R^T#B!{F^CB^-M!msF*Ad;|cW z-#RNLr0yN4?nfWOY1fv@>2!_OuqBv`M@g@ywCT?bThD$Cg_Sdb|0X7EM^AnnQjjK~ zavORuI%si4KRk-?fGC0AEuYy%)0er%&IR~G&8u@%(qsr*Ol!UftlHshXpV3*TD?To^_X$7H*E?6L%rpfGcnh+!hl?+V9<(VFm` z2$Ho3-P;?FOUmP*rG^8RD(~+&_2+2BK#w&yW7w1g&C>kbbiM7w#0m6o$sJRVV)v?3 z-tGL-pow&cYrf=5A9=TMsL0_qzF+gi?NJ?zv}nV#r>f$NK0;E{FN(Iu`{bP~WL&a{ zH6({5o1@(1cX2r}r(oWmNqxZ~^`f*4>-)LZ z5lS{6X(S%sbR=89=4W^cTBKy$9{=bZSrDOFlrK_Mxa?r~H0pbEs48zc0F}fQza=dtcU*j3w zedos1F}_SO>^^mjs?a!Hi*3ix`Cb?K&Oh;^Oys~M9gRDQAP;)x)oDIO=A3BIMVxJ9 zgQsJ_jRmTtL_&I^^+n-z|Jd7~-ki#b(R{5t3%vOY%P}&qWyPbFA|1 zjj?2~YRyJ%7FT1Sf$x>``1(QiQ0@@Vk%DhJ8?-MIoGVjq9xA`!`c)%X(=4qagJ(~P z_)zlEJMQJ~m*Ji#az@adDF0WU+M+NDZN^Q*V57{{WT>&-S3Aj*vRGI)mwH<%=Tql< zg5+9ks=HUG5f|W`4f7X_qW7 zFM1&K!75ji8kH`)sV=P}07RQY7jPO2A@@&f3Sg0w%K|O7eg&4=UfvvxuF{fT(jnfH zg|c@-fUQClPCiswD;JhcVRooP3dDOeji^uHANqxKd|7A+r;V0VfgYcAzByIS8nB*F zXi3x9o=+tg)e_gmX)Zg$0eN7K2>!qjMU+{q}`Cd&=Ca9QAdmf$dG-`-SIv z!MZH8N3V)we@tkz=niD7eJ&hlS{vybsN@`3DH|6kZw<##rNfM#hheUPswpjc8s0zO z=1x_xgf(|bna!5`@J?FKsjF<(NMIKG)7zI}Ovj=NotK6w#v`_hWCDAa8T!^zm_B2D zDwL{UbulL2%xh?^(-DZeD1EltXgNvGzWFP$?`i+FC*0;Nnhi?EvW|RqHhQv#_-}jA zR1A%N;Dk_b{(?oZ>|Dlho@ae0frK}@-?ubA!fKafdmhD;{O1fS()c7Yu&|gd@MgMc zAxC_Q+`u}^_PrN97sesU>9Qj!cCf!suzgQuwCQz3=7Kh!wd+;DH_y1GZrH24?|z{p zUoYg8S`&C2Zs+Q2|Hkveu!m9SMBTe%Oz(xJjGNjgquQ@4!*m3r?>;&&WyHj)3tF4# z2(R%nrTFq@pvDM$%AIFA;IRxW29X{j#Fq=}^dOLJx30?nNkpGf@W5h$MDj-uMyg2) zfS>YHwjf{$Uo}~^w9$Y0zRqKeEb(QlzR=r`O!x1;$YIsVL2TgsY-iV}({Qm_rUiokG|K^qID7T=(^4$wm&u+|Sad~MV)AlWq!pYRjr9N3~ zc=eV=vNbKTLw>{=8&V;l@au_9{aYgaXPE3$+Y|5~6wb69%hEQ_F$|XuTq?a{7OeSM z$y+Ag^0_j;vx&u1tM>XIjxXgf0s!~|($nl#Nw_+$C)furBT1WRs}`5WzU=pJY>q3e5E8#6JR0944%!;P7~Qap3YXdU)-cXU0!3J z<5Z@q;|z{eeGUAni;SO)zA#*V(rQ&W8d*C{Z};gE z`?F63!w~cbp4U{M&y};oN(^02tOaTZ-O#>rgfdBbxRqZIhwQxn&6tblOXoWiSJBq@ zeUA{BJxf_=mrTy?^ssu8me5P#Qd74vg55-zZY}- z(Pz3E#0IAAkDpE4pK_fX*qFZ`&ZsXQO%FfqzFelRvQ2a8Z8~ciU8&!TLxlyQhq3a! zUaJ>lzi#=#g)d!5%Jy+kfCPYK_XN$-83%}c}cR)Im?OA;cT z336q!_>W3N#kFOI@oH1{o=7|Oidk310c1nKL*ld$HG;R^=8k6r)aIZB@3`s^k0we6ka$A39@>Sz)Tv$$uxi)(&u?+Pc0?jowg9;S(M3C+a7 z-83AAf3ycwnRFs+!uA>#!P6l!rCe4Z4@N?{nX84faZJPu|DNyvQ3Zx7KOzp8zkOWQ zWn#G8^Y2#~CJn(2U^WJMiQSDFp&(h3=osl%E+NwHbBBKVKbnTvp%K1{p2O9cE}Cwy z1u;Z897Z_69h~|T{QU8}%bZ)EyBT=vLM74y8>SfIpD87`0smXwtkGo3sGn2uYd#Gm zy+|s=Vh)vb3OtiK+I?KYtpw?UxNH6t?QO|f1{2Rem;Sxuq0ICsJD@E=_ettNaLy zX!EMWXmymoc$tIE8BYj}_xVjy;|LOn029RL+|Lh3 zP{Zjao6UYYOE;Uy7oVvQqjR3Ul72|d?Qa-)Bs_@aijnp8-UCl#PJa+Qhk)Zi>d$J#_-x$T`8rT zr27A*uCp(Pb$GB7>NF-0^z($2wlwjd{JFLHZxh@vgHtwcv+3zJn}`K54HPJ43buO? z9t{TLZ!IIkD6HG9R~m<9CGKg)W0@bsB-jU|^QkCC7tj4}Kg8Xm`%#M9lUA&IRYd>9 zXwSrlTrvNYhl=$v#dp+#;3b`RqG3_gA7N;lhM5Z~U!C30C)#UsJ6@|$KYAUeUC}V+ z$fpLqm#C>>7tIX*QU31+c(Ih5`lMig4Tl0oTxM9Ll8~hIG*-PY{wRXx2=sdD+;6Ga zwOFDsI#(b~%fj1iK#lt?0${;w@`08$Kka7JQYo>ka0^CsNDpY$*}c>V`d53r*TNdJ zAO^?adnh+WSUw@d=i$@@k;PkpX3+ZaXnKEREVX0@M`Y8y%v6HXx2x_-s#jN(iW`%) z^q2Wxy7!9IJ}+o+k3BdwAUFAVV6Svt)U|`TVCE}-xanoy?qAsVr!a~l;p&#^OG9_f z*brN@Ig|6-o=I(2116d6LoRa8J$z@wbyv!d-L=U%P3r zS$iX`o~`~~mRm3THdcGSAQuad2-z#@AvmNyLA$^SJtL2s3ieY9ss$_5UWX!uVEYTw zo>?^)>!G9-WT52 z?b$xe5E?cJ!!2-729o!rdOU!q8hbdYURwObm&(tYg?GCT5pz+xjxnVY{wFvA1s z;!EID+WGPl)2mliJGg9Vr@GnV^o?6tDRT?ANxsVkaK_~*nr4wAtGbj+Ev%7R>`yFz zTQZ-OHCkT!ZtzFcBF(KQJ*6}v)<$dWee2*PXsQAG@sWOlXBXTo7w9~=ej*WL0=~xJ zpe43WtG^i`ii+5EJU&6*kJ%?eq9xPlA(cNGv#|9^-{O5VfXB-*aYpr?=GXkg#Ltug9%s z_`Vg(6;ITmOjy&AQ9eZ0iGi9@53{I&%38g8{fNsNBGYj;5XoMm2i%QdFBcMsPhZ+L z-K0G1{92(NX}}1dezqWPc=tVYxc7;yaa*9vxSMdwn$=!IrllX>9B889;(7i~asVaW zxpd1kP>JvcX6mPPUCpTk=wSSXPN z`_v)2|ie@>2L$owD8a79}4Ni*^=87p{qsTjx4uuSbyU@-1lo?!Xc9!}K z#qpf?aGuAn3;sEhOgR7Fz)b@3dOt6#*|~xk^qPZyYnO=6Q_Pr~DepdlQ7*)7p@*YL z2ktLt_`mLHlU>txy!$k_G*wAz{%qeop8k}G;2!1T%`FK?HQ7b&cH-(tjE*bfsCW5$@>gE_x7>(jvbnfP zEZp@x0kaj9s*-tue{Z|Ja1$<%--DarSvqU2Ihsd)F64uLv_BE>mr8gL->NTgV+IBH zE8moEL$biR@uq~Vl|PHKQ(JzaEREJS^@$wKj`hpcu|4B<8CjG65GkuOkP3I+uN3w2 zd8fnvfB`pYK6fehkwg=)b)m`h*m_!{(?7gJcP#dLqR*%I78B)8e#Y3WFi)t%@~!Z} z9zHMVqXBPevo7)*>Dq|-c@xe&XY|yv87JwFNdh#pvMGG$*%EfJ z)#_yv0)iCQq?F05S>A@tbOi$*LfZf2uetb_{L9xd>KIG2Xi68${a1%{{%kdz+{<=W zV&%2Q-|86h{N5iKc^jLxJ%_Z-8rhK-V?HwY|s5C>-H~L`1rf-GsB;V&m zVK##?*KIm@X?nS8Y$;)9-<|h82km%W(dN-WQR!T1?_K7$=-PYW|{NK>16O89P2;fGuQ?X!@)Sw{=aAg1@p3uI6l8=ir&rsGx|GXAovGRgC+ICr69TvF=$}H+}3Fwt>?Yd#dC-g%O&PV(+%z`6OD9H=-Pul zAs`q1ncgj!-V#@~&635OiqC*WXE9Xybi~5qV}d`cPB@47G-vAPLl)Y<#gcglF9Zfv ziS9yU&6=OGwD;eTSjVmEYkA(Ar2jLp!F+?!-xBqWk`#qsIfW78iBDkZnt;no#HmC! z$V4~l&7p0)1HFb!WjFoYEg}2E!Cl8Pg~M>m)Az=& z3R(q!U@c#Jz4tb@4y+_{=C}yyKwpCElaqlMEu{$=|Ko!@7Tc9OX}fDwiqRFl!Z*%N z>|8%lHgBnoys9s5;!XkAV8Y-^OA=V^9tt-u^T+QIv6|a6s@YC25@ZsoKCrn?rjR6o zu;=nKHHO1N;RH*IC|q)LNnF0^62wSK zO%@P(6Ho9}L;i65hsuZGbiTVwJS6|zb-hlUi3<%FY5%g~=@xt*e?GY`cD3gN(>|mM z5?0=9Kvab*56h6B(en8F_R}yQE+z5Q-ThZ3^99|1_=W!|vFAz)y|Ca(pnP|XMklHo zRDp{e?4H-5(;a#@F6R5lo{>FuHN`IKF!P7tl}TT3`KtCtQthND)7&TO7V5nW@sXUp zme{y1+_s+_bH^*&da7GD-HS$@TWLe~fxWhHeD7-HYBWU2abz@8!v3Ym@;WDua*t)S z?~6=1*W%of;SUId-pZ4uG&xBn`2HMKSy!M4lfs*eE@#7ql;>H5=wW2Lnn0$l0Q21Q zdh7f#lWaYgN*Gt)Mn@T!)O8~|g~H$}N0pb!`A^5ptswhsx&81)ossPq;+^NuKgh0` zU;B;fQq&n=xn8H$57O|Z<}MSeb-r3^G3_?Gufp5)A&ZxbPs+J!zaryu{Kfs!6{isu z@hM9;qG>lZe8LiA{O|E-@ToBS3}kE^m*aPrppM^t?2#FZ3rH(nVt0GTo~oPQ_jbQ` z(LiUKUg(W}IR+2W8#>b7`dN*)8d}=RNu^S0wH*jZ3D0YYoqytLA-TsX%=K?S!yuE} zxsD`>fu%tt+CJ~EeM)=ySH&f)Lqj`1HP7ZWJbSh^uTUjw=GL43Vq%%A)0y=H#hEVT z4d%fG@gR{5{90EMI$|$xmYIgi_{xtQl-EPn5{>=SHKm=sA;PW<7(;%`N**yg)@O-E^UKr zILk^GOP@_p0!uGri29|R{Q7vl#s{P9M;Kdi02;&ccz0u5tHVg<(@Q4_ln@N43W6jH_y0>t@gLx?{ z`-38Ja+A6%jvh{hpFla{>41rqV|RnVo|l*In@A{MPqJ_S@Ho%*^M^Z|L9hN4$*b zV_fsfRu~+%h7x5cQ$WSwpM^LG2QX7fo7PPF=-uBLflLw720QkcN1sc62y{-ONA+9% z5i;@-i=W_Eev+gU@aUvye&!+d=#pF7x*jl$<4ADEf9*>0J8} zdo?~=qb^Nuy2j8|sWFl?K(1=`#qlnKd#nt)P*ttbKHyu{PibHw^;NOj|F{)R7Y%A< zJW@VhH)ZaTy;e$>vCwWU67|Z>ONaSHW{pi=U|ye!Q+nNP=3*j_BnkVr$x+E2#vP{#EU%(9;~V*ILpTOD52>u%j6oDl^`0yv3w^nKv> zaa}=<>bNobID*>oblJe4G570KH_nYE8wN+m5qLgNquiRSHDG>UiHHRT-zdi1?RnAh za@R;!Qp7=ivRKUc2kE4lJ>;Hy|T6y+mAN12UEQ|M9|mWl4>148v9Ykgk_fS!m+F(!%l1c=^s(tIWnT+n>>K z&DP7!Kqqpp2Ax}Zc`;afX*MfXghsK(uOR>&ZY^+htGQxVg{6Osu$}{^uL*A@xgdcN zWXI&lNaC*NI5=`5OJhVM?Du5NUxOa(aqxPQhQi?Bn9j=H2Y!iL#TOnNcWPGpV~^Mu z(#zi_KM%8@;{r{XgEMU;wu`$|DNn{$&#hi_ZMYf2Mj4d~bI;|YzOTpHU^1lX;Etk-7LjI#-094cc z(fQ07Z-~)cTG|bl@cTKSS095kbK;iolr472*t|sEJ>F`v+>G72-EL9pwJ(B;Q?bI6EI_`J1jPX zYWCXEB3@>GBE-uvCt`w~ZcnKnqu{ zFnieaJ8&2+09v(ugC@oVl$XbS_k=&rXIKMG{9{}V>vo1hX;$y0&wfJiZof^o*J2rE z5+sSbSq&9vu5kXAazRdJyyCY@nPphoRvE-BZA8lsm~Ov^zLR5)zAYN{`T3Q$QY(`# z5jXh5!|%OS3i@40!$s-o6)zXYtc?xUe>^|KGi)kSC1Ub;?cT%x`0nYeEjKmvGQ6N~ z@w6b@_hz|#viF_N)VtLj_})c*l26zDff02*TdCF4!*Jiw-l-^p(O=)FSYyNUAPw`7 zH`qj*g&Ftg&B&Jl6K)65V#gcwvp?H5$AWBMzwCTZSojy8!2ZmHI4*>*smrLX6yYl$ zel}EmBE+lKY{pr+pC$)C?vh*RK9kBWVYbPA1~OJr3u1=Et`=SqI%Qv8;M{KHUuBjH zc%P2>qSesbw$t@)hNO;8mVxfc+Nhk?LN81%X<$bT8kS57`*x*PmihW<;&vVR%z$ZNe;4&osfkLIvPY~3k|iOYc+c~ib%C)S$Mn}iMu~j&A(LD zt1I_e+M+~h-)1jfo5I+i*|aiJC$v|8g;Z1pfA;ZXm09&0L-lsVf+;w?Vnw~C=>zq{U}qh%$pFgsDouPXMg4<&5ObE$2_BA2zuSKmrN-1jU1MkQP7uVOieQ3~EI zO?;uMid$7A^PQnt(R0QwW`@58ySkbOkpqBuQh(9ovI|JKwvvSbTkTW<`mnA(lUP?1 zRDR3LcWlDgm> z7|{0A=ml@}2^9@+$CdG*l%nz?EKW1f+7KloGgjf!x`b%_`M44aYhm)O+qGH2QS@q@ z%FC~wdtFZTT7o2vvm`P)Na5}|*g4gDExQ@F)@UZ6T-R-;x2BhPnvki#8r6P!CM7s) zzxa5goT&%I{(cl&nVn&fGNq=(jn(UB5!b{GL~ElOrSuMqfqd@a6uC1V72A#v!>Qei z&&UCIU1fPv4JTPM*^f5kH9%Wdi?Z&R+*0T)eR&`{@0XCh&%oW}$g4+mXp3(Nt zVqN|2`51BzgKOi(rp=V-8c4(#;X0VB0VB!YMh+y zJN;`G%ioar8<219=nL*qFOyr}IWcQ+eC0WNwJ0pidnuETBUyCFIVW3l%VX6_ z_Ehj(!+27Wn-XvnC}^pzN4>kz8(mb-7Z^E8)_tRQ7CpkD?dGq~2dOrRaHu`f35oXd zK0MbmaRWOw?Gz|Ck?%11C|7#1AD1G>8b34^jlKX0c)&#HwTNolwb;BA&g5VZv6{Kr z*RN=>n+Y859Nx9)yXeK=@4t`>O5GFp=be(hkPG~y7bbrk&-KOx5;FJWO8*`)MYSda z;MZYfB*Av?b0pQHA9N*Pn?eRKmbmoLcNUHNYW7iO`ZwL;dnobMkIVo2!T*Yi(bZJ`8NztX9br6i zs~GgjE2Y9*i&yP-3jLL}l$mKQa3+->K*n(IIpQ@=EAT=25tN6`%*knn9(OYHrbWa` zi!{9-vQMYxz$Lz~9#!ADcL^f)n%Z%3Y9uiI``QyOYt<8l@?Fq{lLruedId8$?b9M! zPPtMVB&SU|(<)!rz&Ie=3Yz0?L`lZ9hUQ3+$RZa^+n7$iXBOq9mtPr~4xaKc7{<$) zSJgF|+s`>#k2LcyWmkb+RdL)_&sm{dizMmeJlabAR^;1}+?4T2^Ny!0 zH%_!<-K5y=X>uts&l>^{M=J|?7?SDGJT7@RpDO}=NWwJsGvq%r;;(W>re4h9=$3ua z-HA~mp?`PQ@V%LXUMWu(~rnrw_ic@WvGBg^2__gtb9@^ylDGR?7n z2VxwTT>ELXo>XM-F7NQ|Gyf-n8ymR+5+4PkVJJ;hq4pOxfOuYRwN)CuV)h@EFGZs; z1sa*xJh>iJ4)cOOuDFaI$e4yO>7z!6CitD@=?{#4I$DJH#Vs?fy&3V8*Ep(L1nL@Y zgMd79U4-z?e^hMcZlkKnI~E@Y0_n1%WJdVnW9nV$KNl^mXzbbGdH*cbu_Hf^9 zJh2l*3t=KuwJQeJ6g_86_E-L``**nY4f(^y{yO?LLK*&H4CyX`HCWR72-o|8Zg->8 zMISy)F}fzsmX{!>6vg+Jd8&|=*p$}H@$1kaBOhV7+e(fq{8d2~^MA*0n(`$2+SQCS zoo@7#u9xF{vGpxC_*{j`>F{;!5}|$+9=#ZBO4wexGJu4M1n18+COe&G-<9)IK`O4b z8GjSOicj(wuZ@wek#o>aapByx9r;1xlM2h3`=aPFWn4V}I&A9sXjq=ZD-G zT5j3LjMK4^9^tMR5|yFcG-B0Jux43-V6hUpzn_dQ&!EJ*6%{i$PA~(IOcV}S$(gqm zd;WN^z!WJ4e4zUi|4|JCo}R0I@zf8HGpZZ-^6%va*hLXYHl$D=fxlR!wrVz1tBtKW zM;cV}@Y=lP0Z9u2=J9S4tZaBI-q{0oDHDQTDWdhsd2wE7kBVEH9$406^X+xfe1S}lkdznQK6;@ z`*_neu^`tUaVHU^oyt1g+NM42eWjq6lIz#6pv-%005&}1P_FwQ@ns+{wR!DPb<-v! zDPi81cTC0sO$A;|L)RexfTvMFx%B9AUeRe|?a$&K{+4RyLp|BfTdqZt)owFrzc-4L zL%2Pm@phvxzDLwq z`!C%2OLMDQ8a{r3UyPeRSVXlUIS7+0p;0a}WXH~V`|jcbD@+5=t5m)z$XW#J;ndD2 ztA?zHqoo`w@}&t#G0o47O<>@9IyP;gUCIeU0xiVnuv^+tk1MceLJxwTnz&eL{$_`1 zfyJ#|Q)UM5(gMA-YUzBFVVz#9Nl$#W9^`bpmu#in9#lN-g0rVrY<2}Uaz}xyYZ|A4 zt8EOT-uBWg@en;;v;V{XviAcpoVKKqt5ZR?5Wmb;S26~XT(%o8q>O>oq$8{v(9 ze(DKjGgf0qAQV9B=m&ZA!Ke0QbhX|sl1fDBF@z-wmRq5&bkmx{t%pe0H(A#lU9%Gr zb!+F|bpl0*Q6Rn$D9CcByGIagLtR#;4!Zu+ra&gxp#JldbzfK7rqK`d2%>$H$??_0 zd|gB7S88haeYR$Tjsq`r#e;@ zK_;K%MV$_^n2+gP|UAS@+0QzG5s( zal1e+R8*#kwUw$ORN&IpkjGE;zPZ!eEHl5@dRzL%xyvvoAPW?l&R0n~Q7It>10Y><)O7P(Mz(X_VLmj`uTCCjjb-`Q5OJx8s8n1?PFJ=qq;#S=0OZL* zFUn*d8Pcq7oA_$X^j?JES9rqhV~xS?v$pb`XxaNP3UkL=mG$wr)fOAM|EQR}ml=I3 zs!D?xwGY&R?&@u!8i^U|WlApcgJ457%O|;vlAq-_?GRK5U%VyqlClNyDPowL`IwH{ zGPkwn7pSoK>8(}vu)2mTz0X=W>)@@6CPQnc;WpB6yS$dEH~D8~97&_aVW0I(gt#3@ z&&fHi2oXwKWBHe6Z}MAt==q3yH3qojD1o8! z9)a(_?_uBD^6M`kK#a4;wX?fZA^!3$Qtd} z09!^3zzZB}1b2cDAP;__f6^uXAKUv3;CgpgJ8M@$KZXzQ(A1&(+;oxVRHWPG%?GU> z(}7EKxd|yr%1`g@7AasvtkrEqUiHe$L-$BV7je~@9BTd_Oc%|lKMVGuEN!p zI3a(|9Og+;UlP}~4Bxk-2VU7*EEj3~yO=9+-eL~3tVwkKquW4&R@UN-GsTM9@@B<4 z2mJ*Jda@Yv+_Z>hUT^#i<)+pW-CZbz8No?-wyYLqFu}H0niTiZ85dvt$9n)xD7e<1#@31JFT+p_SM0>rGB_c}BGjzz!@%WNSI_U$r zBkSTjv<;vW-1-?zp=rT44e~KaFzJFfa)fKnj;7W%R)UxcA3|EdIIROL%hG<_qQqU& zeSB?;M~=%*;OU&Q_21tevd!@!K3bgLJWSYne&(Diz4uiR5x`8a$$~>o5;@gJJ1?}n z*T*#AB|7?NMDl=5^Qe}QuDlqz zm6`%Jn`lILU@Bigx)dKPd9j_`P!FPz&0j_Ock-mE{cYA;41Dmg7GL)HAL)}o_I2d3 z{VUmp(8&rv zEd!YmByaK)x&PgL8kbAQ=DD%;JG99fbiE8jzL8gIYETi;iDCr*|># zIU=v|qhctx{S(?j51k|}RW;vUMBf6uswxtWrGww`w2wNH#BTf~Wa9#~70f^aF!(RI zk)48>uXJQmQ370*AmlJCi|ItsQI2uQ>IWPDQE?agOf7ZZ<3$)Xc!9$q*Ge6s>5vEz zr_<0oHN}`Z2=Uxl48aTM8edPw(s6Cd)3VMQ`HCQ@$!FT}KSd9}Ey%wa2#Z3nSan57 z+;_6~jz&7E>QTZh44??QPdsKMi(I+B!eDXs;b2s zCk1&nF+8io)h@JIqh-;Hh0<_NTu<8`Z~KMXKwkFpoTIUJct~|G@661zn04trWf6wL z6VP}GqeizQ>$tgi&tec$1I|W`3ek?}Hwn-JCR`Xvziu+mB1izR=2+ejuDdC^E>|q5 zQqPBwJ)Vq$U$b9cpx;8#wkkj`G&+#eiR}zeJ%3KIy$iK+T)T?+kLuv+{6PKwevlV? z()WbcuyHLMdP%(oZ_&X8CZiTQ>L`r3Pw&Jyx>iQ#rehfDt`4e5`C4Uv!iu+6vA-MgZ^tICBzcE-i zx8AP8wPcP~*PHUxS=dWa&mEr3va9Im$@bOeAE^Ii@~&Q(Y?HI`o4L1%teOjGj8{1W^$tvk8^`T^F$xetwRHJ^AXRGnrgA zaZ*A`nz>JbGXdQK$TNx8jpWj1`Co7q9Cx&VDsHS!%&$ zgISWOh-J@|T>~fF$9@+x2rLVqVOARQ-;`~x;_WD89zaOM;Xx5@y&!<|u`u~1~x6bbkv{CvtXI4qziA9^5!EA~u*#m)`yY+I0SQ!d2rOT48xC6u{J%u+ z|9?9J|9{_7FUymd*Y1+|3EmIEQadSBLHDPtNFhl1Z1x$QK#<$8VgvMx=8slk%P>_EfmydYO^#hbd$Ne^&!5f2)Y&vZxm z>gprjM>OBS)b(5F*G1%1o7IR3SU{6m-EuAIx^zsMokiVlmTL7I#5WLpm-pTnqveKq zv#x0Nh=Lboi+{l6JGr>Hr;R^g?nyBUiB9W~|CH>WDWYrM9|h+Ml6eO9LzaVHQj9D< zgw9J=hjM5g&sdVccYIgJ5=pw)p%$AL*We067P|JzpGt(^INk*lTl0HyB1Giwobjoj*22| zS=@?tQ`~N`5_4T$yjJqcd(1HPe6B-MRI=@tOkIal(kpH5P;BSKAs_C$+-0Qykt7H$ z=96X|RoY|2U^(M{)oU6f`|=JD?l($jEY2~*%EgO=g!^_qF3s-X@}jW`B?-sWeN=v) zy>0AwO3x_Q9$nl{k;!0PNgFaGCmkym%3v5V-vY0&hqSqo$;Gi?x*C*hPQvv@6Y7V9 zy3U7^um3q2=sZoQa11qT+2pGvjmK+VQo47jWV`Lr=~Y_Ik0(Xj9zR9``QE^ZOL7{eyA|Go94~xweoyUA582 zY+L4St@*2|rPcuhdHTOfaL-zQkfYs=`%lXV+FrPt?uENsi#)b`)omu+5%(rmtBzMz zz+uYli^ynhCXgtsZYiXvTY{Z{GH$GjdR}KHP&+IN{}Dg%{(%--UJ@1dB@VQ&Ab@U1 z5d^7&Wzf@tonZD>0hpiRILXgD&uUxI;Y$pkj^kSBAy0zr%|oTP%BjSn4|}t;Q0B&8 zuEaRP5m5?(3Gny`Vskb>_)Oh_iIi^rDqcOsAMaXYDxPP$pCq0-{VMVf;;@miE{hfs z4>u;qf!`r%2{iAp@L-to%n64dMkbG9M5XWuO9&sPPxeP0IMK`PPij zQSDLOq40Y=BTUlP{uq}hV5hNKUH;Q*T>euc^z@K|l-Eph@#TEJB|2ln+3jBQQwjJ&+2C zZwSF>4snKR%U`67Q3QT5okAVuF5&L?vW(}{-aMvK7puGCQvn9<-2=DPKX=0 zvoH)`4_jt^F=SDEmsgA9m!0^!*Iwq20FzChW`S&T1v?{c#R{+VJ$q#D)Uy9fba8Df zbHdRke6El(gsfZWxTTIqcY?q4doE3OCTMWjRZG^*VZQBd)sb`mqXH^kM#0ch#x5Ys zJ*yl)(*~3vwX_b;{H-6MyOS8Oum2Ao9FJ|eebl}i%GJY^yo~l)W9>U|xVT^p9l$eu z%Qk0rmMfj4(BMvMR?vh;#=*Eo32fvtr4LM_^`O~J$<_7rbVRFCnoqQ7M&Zg@(3FA; z`3V_C5sQmK-K^#g?{%s*aQTg@ewHts*uBOfSgUTbV~vc+5R6|ubTK8RnyJI%Fu)u8 z(i-cmj`?AJL|}3Gp$e?QnAc6`7Tb;RIP?fQaZ~@a#`e~JP<2X^_hItEX+F6O#80xp z$8~T|FSIe6SHWH``+U_b8Yy|*_ildOj91kxtWRW^a+xv>x!dfw661aP0f_FOF#4ou~J(p;vjbnBL zjd;+`x`b)ejR7l+|7l!3y8`yP)*%o8t=HbiB>k%6*2`@D+-r|6s?#(IInI(}6l0)* z9{-M!*leH%!{pCGWb1W;{vw%2Oz#a|D`rh1;f43Bw`!^_Q=g%K5%P$6E(wAl@r6V? z(6Q__MEEdVn!IndfswSL>b3*>tzE^})i}o!be_|P`{sj8q0n=k zZ>gCs0>?zKdcKgR+ye}Q-E>z-^f;Y^IJp1&cNMkgJfV`QWsa`9k&@d}04b#buo$%f zskpEgyh3D;*&K^-acC^~UkQ(Nu9YlI!#eH--FpXmq^ z0(R5GRxRg;!=Jk0ES6;JBCE^qXs^xPV_?=b6^HzTWd4S+fyPf21Vcf3TiUy+C@=O5s@ZH zi%RcZlolHxA{{|$lq$VR4~ZhuAp!zQivrRi(xoNRQF`wsL3&FlA&}yEzi;NBIseSL zI5%7{1W4Y!*IxTsPZ{mK;_)k3z_iV64h*k$1E)*;XGuX zWzAaaIlK6&<~Pwth}NtAp7}*79dJ8kh^i{#$}lOn4X8zYN!8|KIXvFp0t)bDgE)l;kJLWTpON_Z0#C`hIQ zRMQ=~bGXO^)fl{aCuy?R7;4PE`ltCH18FRFTz;Nz}QmN{+;?}6=#k!wq?B)kAuUNc&x$G^t^w;4C zRW9JM)evI7dQ!({*r6Y;{?*T>^D`$o#Su9)hYs z6>wp%a6^tk=Wejk9k%2iT`^lsyap=qM&evhg8bVZs`xfct$3Xm$i zX5KFa?l69Zo~2g5iPL+aX6G@gH|9Qaji3{JEAkS{4lzIJ3`c4xw;=S$b z?k$)5P5imyoRvZQ^SidK6Dbl4Z@vqPorG{4E}q%sMzu2Xs6#p@tOVDyq}hRt+X)s5N7&o{Nx)U3IBd6^ry zh*#Z!r8KQd%!ndplAh(|^zV=L&9j_-0*8Zu0X5d-^G*zmHse6VKdMuoWqI6#ZVNTnqGS zY;Kt*wYkUzq)Q(gO`;iIU(XRC=oLTWNLcpJVFTZTWT>Tr-gw%K?|W@)l3!9DQ1gx; zoFp%tSLBXjxo*3by!0DVeyr5?HsVUro-p6jqxpV^)p1S!zrHd~D^sV=#CX!l(&97{ zo7&w0;$RCdvSstg+lYpT1_%9G3cY>w5x{i;Z^gH;04iWK3iMR8Q2;c#nzvlex-e>p zFYoYCnlBP#-|*(jWw)Dp(+yY`aZi@_K&oq{?RNz)k{s!-yeW~Nes)~f>+Zd3G`rB~ z`f%96#CeDt7>~ucKU}F8e?GF9#nJwvsee3?gHf3RqWCPfAh)CNYGf7vQ z#PJ=(PwK@zFKWb-K3qx5y_7iiDHl4zH%*=De$)^tv6{_HT%;Dkm;lxV0@yaQ4A_b6 z?=CcnG{M--89Amu+JfO=)i)-+Y!LxGqbn~lkzrTBOxWxjp%yg4{P&H;T?U&)J;W3_ zTC=wI>&+eYM!Q@`N&O)?$Y*`Elh)pRLO= zabeotIXK>xP`&eu%VYtqL1H0$P+Uph$m&4|Tq>fS47naO`FP^?=*`iZ@5vVnb@Euh z`YU=z-r~rfz#L#OtF0zIJS9E6WBg)H_RG8Bz_@SVY^V+Z$7dSHj3^7W}aV|Ymg)+ z-{<{#QAI^$Wk!qotMG6X2S`4@&TO9ekkKkjxt<%NNfkc6^KM zn-U`bz7dB&q*hg>CBgT4xH(q-vj-w-QRXN8AKFemAw zq}JT((0{}3;d{H$oTTEVEf8Ojtg5B!&21e{w^G!f^{}zY2vQ0$55Jm1z7O!os&~p` z=XKv~G3|b>g4Rv4iuqjAU%AiIBCozx6+D0U;iuzOm#{S^-kkguGbV}{jbUUow`eBf zC0n@IkFLr;H=^jw=elgMgdQCh=J~UEF{Vr{rH>cIw2q@*F_=|7HtgP!_1{*Gr4#{= zqHQ)GQe*Z`KKU6MRNtds*Ds6ezB@h-#2IM6pGbzm^T5KQsP4guw*T_uN&t7>tt2w?ZL8SchCT)mivFmaR5W^-|+vY$6)~L8SgzpDVAC-{sGZGa`)A7j9bG4 zhS?P!SixH`J3x>7?=OEu^7r9Ot2j<63c{ZGV(_pe7_~*)H}#qx{59zQRZ}{LwLJ?bj?zGPe%R{QR{+;_JX4uSy?6)>GTxw;kTqYXMlKX za_M2?!Kta@U4_2}vsK5PGxe=h5p2}^uW8Gsgo=6(r(%}Ypj4Yb4Ytu%o;&lU677&` z?QX!u^j0Ius@OF^MJqE{oGHWZq#{Y@xD{aObyq^pn_pbeF!uaiDly)QdB-DgnV%_{wsY`78vGJ@8E7}3p_gpuG)y)R}`ajYS())6fHm!C5yG!d@hO zFV;<6<({+*zX10Q!FYtY!lDmY7WH$lC-_S)x#18MDrKB7hAB7TRQlv7IO$-_OQ~`9 z+Lu@#%=n4F1eV$VnhaDD%eT*>Q+}E|E_vvOsdi+jcKu=1-E#15Cvh7VG+WPH4if(j zn88rK%)d>oG+oS~3}XCQB4;fkd?2f4Z^{uF+DC#K?B?QrBh{-GhP(P5+yrB2&kzL| z6SUfZy1@TwJIypS@HLk8QRx1_l3-=xmQqd5n`^l`2MJNfiLERE3Szo-c)bwiFG?d_`s^0CgV%BE~Ru)YGuuBn2bqd#P(+W5MEk~__yMP#BbDS`G5}bT5$mDr5L6AGkubey^ zEW{{wKXcNLuHsR3{U5oE%|Cb+qr$j|L!ATQ=xgQES)2!d8)R-RnF$Kjt)2YNwrObj zE8SQOyY}K2(4YKDbkk#*4tyC)+2ha~DBJe$ek}h4=`z!R`U9NLkmbc41+pU406&R< z^1Ql^!Q=Kp)eBQxaVaX5G7Xcf56yWD^qU$dPRuT6KQsOi#?Q2x>WbYucnR7h`8Kq0)(yM#^YIBKVbED>~o!)%9Q5mzkx zpxOjR?Dm~N4LctpayLUtK=I}azAY*)Zvvz58_70pQYvLaxzSOphm>&vmHPlH?-QqeiYvAV%=eFVcyx-mW=*KvDLm_{Tyco!{k6w+aJbQP8orX7d#Zze+~l z#~D+#52d7^Bk(z?r!tp;9V?)MVZ2*|u#>qr7!p#1+9<-jA(2D7Kf#9h*(cO|0K0|- zW;{-DrVf>7Yc-Rbbv-rj>76ygn>R~FnpBIoc=*4NIXiKP7)+f=$KH%c8yeJt$FwK-PHD3)Sk+=? z|DK$cH5sqEF;x*Vxs`XVA8@Q%RZ{*z;PYI!UvPa?U|a;7LzV{^hZ`9De2$u80=61yfDR; z>!X!MwMQDU)MVII%rBs@wIZ)pyt;l`7O?0xHi?<_M0^ni@BS5`TtL75SlNA}{0E^% z|7qgB1DEOtmyOxm4KaxdEpjKZBTdv%@!0018CS-B`=84QOPcAOAC%hk8T&#ft|K@BoB+u=VZF@mDkv>#GbpDx6ZkOS_>rpq<+P`hRj&u9J|}% zKxcxI+p(x9uN;Ya1-<%IFMp-ThXp$MVl|Q7yF-rmRU6b5dtT`m2>WmLOWUC4{P}W| zhz5YOsufh8WWgDwagGF8Vop$F$e*{4wp?B9(s}#y^YXw?s6@|;Wj`W>s0phH!v*-B z4{m;-yx8%`$Nkdn7T=R;d85 ztFD*wTB(^An`4EO93^}tz%V zH)VG%O^ICH=Gd$h-hs=rc=}zlm%T}SaSqy1XwGuCRYItgdewFL7xy@V!d|!6t#J!~ z;A+b^z7mw#SAXzz|8L#3{3!3)4>!4~4)vpI;P1K8hyu%LK?@eC=1bRyfnJ>B#60@m ziki(8k@3xq?d3N}lj&Z(Nx_PkzdHq(;{7LyU7b|!w**90(f`OE3h5>0#~T<{tt{fz+py8){0O!JfJw zU%oQSD892IMQn20J5sZ5XE3V}wod##&8JLZn;7f@U)+Jd!pn5Y_A#a9N!F#Gy>sn- zO=(ij$V(2CJQcw7TmykZ{}pm&o*HXPjZeaWEQE1`81FYe z4cQ^Swm@fb6fBy!?-)7(q4Qb|wShR5Sw9FD$swn-1Tm4J2bNlr;sf ztsvoCZRE+VY;*!Pj3t|*p7&zIovK&f?47JmJdax2RUZicarep{?t)nE+3_42^95?z zCc2EWM{Uv2fI8tXAY7I}5h@&q^(qni^$I&$F}3A~~7?g6xabkqX~H?0SBO%XA@ zvIo_H;}>5LIOCPF%DYMf$_m)+527ClDEA{jr}Y99WrYvz+VAI8?nalSqWWgX1?SWK z5Nsln&MgeReCRNP85BcM@tCFC;&Ggd$oP4nSS#G(M_+8>^-D2;#x*!@cXb;kH zFYRi+4~GCKq<<69l1uHhGkuc9VSI@nXgVmlR1AfQ0O|s$P+TDT*MZ#iMC*6IA{B0@ zlkfXA7cKcfN=UD4(-_qfo>{FRBx~VV=aesP->ntml}8T*fHj!@`gAdd;(|}N87j|N zGa6d)@%Or{m}84&XoNVl&{Ju79?H~0Ru+nj|l9ZU(jG*)cMw{rr@1|Ya+;K&6Hyg~OK*Kb_! zy+f>hp^le#^|!OZYSmMDD23KVAqP1N{ zK{hus8HRR$dG!&p8Qjtj3#WB*UoXe*O?$Pfm^IvpUA-%$%JnLh+w2u!tMrTD%sSNf z6U@X;CH?6S5k?)qIFzRdZrD4DRBO*dm?vq%Ngiq*O1nqo!uS8^_65AigZtWpKwJD@ z(%e@>+J8xNYc$3LN0Avci>t=V>1vBOXXxs1^?lGgrPDK5(6w0rh+(90ZUoA*mY3wm zKgDZ*`A0X2qQ7fBrIYV;tbKF_+cYaf(pH>&Pc^DXaII@RCG5pn(z1(YrL(Ux&Q_iv z;0J&_N^a|SFNf0FDbj8{H&F!JIbRcq@Q}Na^0p9Tx%(WLQm8CfD!og4cq|;A6y^*742wEdJ@Qr3t^k zJ2|OkQC|ysu+tgcKYy3C@aEFc*(jex1O6ki#s)jaXB~-O>^te31X!P3dfCA?wwm-M z-)>izZ7k(}B=7?EGpBoGWh<9cApcT;7&U^*6LdKy1{T3LN=~juflX0=`pr8vgeKh; zsS=js6?BrD<|6UkB0Lw(!* zTh3#yBwe*AH|XxZLv@aBAg)S{r6eeKjrfYx==9T#%-CY^(CwY%hYT_3ng(1gnPdt! zaIHwA=UHOz%=T-`7)M6^bwM4HW0I9>=06z;K*PC&F~k?bOo~793%*z z^5u`!bF>0{BTMPSicAg>f+TA(S()GPuarY)MY}*6T`EnSl3<#my(hzbwNtm;xJ~E% z{j+EKea+j+u7|Bmqn1yW8RdZ)JL(amnX3yD{N>dK)mATWznz#f4z++29&QeHrW@Pd z$z%_h*hdF6>rz~R5v;{Ox=LLwxC1gmSYRKJUMmzZlQ=&%VXP;QoFL903O##h?0xWs z&C}}5%MxR1|IHWtUtT5uZ%-3?JP;@tG$PY(5cvc=o^5-GEULGLD?kP`>B2Jcn~spF zlx6m-f4vBtkxympdWmJURH_85{}leAW^eic`#d$fJCmtC@^G2OK7RL|EIxu|mnR77GU^Ngo5LbN9es zI$?R(z-p+bL3%DcsW&F>Z;G=Hew4U3j=?@4xpjkC%PAJcLC9Ydfx`xluW}pLLt;;~ zRD+cmTQbiEhd%r4xF+I-T2i8pE-uX3HVS(92=tgK&2py+{doUl?Hy$CaJ&M#%{-1I z3F&JdcO%r>EP>DdQs`>Rm|yFuec%QpMJl}e^{>IR_0h{sH#E<4TLyeDa^d{3nV~sW zXI@t!7#YNum!@nRpO`P7v?(#{2v{@Jg{C)W;+Ugt1F`uYX4{n%=%34a<*_n^6x<T(kKGtkv-o6C1QBqbOnr}Zw7@==VRkT%12U8bRNJ)bc?H*ccjQbZb>fb z3rx}b?(Qkd1 zZFhhu+!McndF_Sp`*45;-rXPGVwLiV2Sg1=dSWf7@jdWs1B8i{QWlbh@)+MR_s8F@ zne87PTnvfF&{WTsY1|HqVCOpLT7Ms~J%j^q-=yK2$c_a0u`XR*3eGu(TWGz|tnn8R zVw!qovBqnMUPaIk`jo&U2`!>c{P+8x7;1~>%FCfp(i)CWWleLEb}Q(;(dgc7SpyG^ zQhz~($07MiHJLVH(WskW`|FM`iwa6?cunmGmxEmq5!G!?SwZQ#z#j-%Vc1uC!VKVc zZt#RfE{rp37J(yH<4ZgINCA5<8a_A$rQJJMsZ{fTaaH_25+|~wPUyugzOTWYhdv_!AvD`> ztXjhyg_g`4!y%Fd*P&kG56EQ(H|@DlK?E5JdmJ&F0FR`|U}e}`>(VmoUppZ``10;D>`54F^<`6Q}m2GqCLA;W&XO@ub+#;)1{f%ng2 z)>yp;;L|5=g^1<74zC$zoJa>~7GyI9$MR2TaBY|kerFC z6SEJqeo4OukA~MX@0bv@^?wdGdl9YzB~-sjt|qORqxl*eqo+YK*GGRk@^P`64OyGw zJgnwG6C6^rFW)dj3)WOOWlVc6zGQuT{Q-Aaf75u~$Gmt$#z#BIX(VKrV$WZX6N6e5 zk-|6C;}p~NH~(;XUzYQNr5;8wx_JoC-nqmZbx$PO?Ib0pvespJ?P@m>MZYrTI{jG0 zZLYjX)89Lnx%P8&!CaF82Qs(>a&d--{5{Ad)v(#TOVZy07}QEuMBIr%c$CgqT31V3 z2wAhu@*lNB9}-qEKs}@ZVj+4ri9Fkm&-D&559BL1vdqW-1~v3@UTn$KUgdqBW)gYz zyJ_u{69L+##d6ov$(=3yp4FtM?UoS+J?8K;!z4XfN0D6KiCO4}LsF@aczoC4e7$|5 zC4!<~uX5r9V?dG4(wBbI$DX(j%kKOzKfx}yLuST+I*7Rg>uzg&SwI==#gHUeA1Qx8 zv(L_@?IVpbto9WXPy7%Q&6!waN2wP{#0vpagx(~)sdlaW?d%bTt-BPx>uJH9yi>oz zlWZucuKYMmf@piScR9mbi$^l;Ko3O@a64?+|NJMXTQ=2g=d=LYx{Ul_iHtbh1GX8j z8oWrISWU1pX&Oi2KEg}uVs{sRYtY<1fjih)#u;=UsnVab9YYeokd9l7Gl$uJ2>J0l ze|`Y$!|vh!D#8(MD3Iyx^)N6HHC(OD{WDPeO3U%n{8#&<2FYp^^|3whYMk>nb9A#+ z!8*54cXYF6(Ie;l+3r;xABA@p5qy4gO2N+UplHk`wD5XJPC0&8_g>BGf*_Qw=wlYI zE*s>^a{=DJlP80`QEH`;#kNnaV|A3*!kEVej)KruTlNRNLys0t zaaIR)RhFE+KApyP{3sw&UNwvelIexyEi%B^))z0(c-P@fH8&FaxYc<0O(rZ}q$gpP z9%oRaIxN)kB7a!$)@DKv!m?{10c(RR=Ec#aF&kA>INOj&eDQ|yMmtql$#GeI>jZwL zJjAy2Kx4wVMHog$5ynu9z}O0y*gUP*+^4$?omW(TF!(p@^GsYFeIMHe-n%?L2QdFr zX0i&b56&%#c|D7n@gjbmbgxBm2x{2m2RJ@GN#IOrA!>7rKB4ubgxZqtOzvuSzk2Ug z^~uY%e{|ACrKfe7;^iWeA~lGabP9dL7~Gv|&;hEPK;i)hLPX3AFa*ZO&OQ8tbF4CE zaZtr1jFo9LNNt#b9R?#y@m9pc2^d#dLBNQj*sWk@La)&GvJoViWZ6tb_qxPqf1YP9yO3{4tPEIO4`279snSz?Dssdz2`6(Xcd-9%rY{9 z+5MON1jYKvb0zh-GF2F5@}%ILKAfnZsfwk9&ePy4%;Z zk}11d}C1pHsJ`oAeiZCbz}rsuDHusLp2RCfvm_gZb3EcTXhXUygVIisdw~?M72h z9v&^#XjWFzSsk=9=*hrQUYwn-?Jam}zMiGv_{qqvN`pZG(1vC3@r_u$Sg`K7I<=IY z$lw^CLGuD8SjcF2-SG#g7|uqSXoRmVX!y3U`SiGIzMC;c$8O#Q`J%iGSYo&4(aDgpPQa zJ5HmU-lTv7{l_y9W6pS#c9f9&Q(J?5d*m+|GAJDf3HL{^Zeh;Wz@zWLZje%oEE=cZ ztz=HwK9=H5%Ew4H!Ds^^=F88c!Zjpl1OMpi3*UNz-BeK|OXUR-u;Y-Dc1!Z(a0{Vp z?XvGCSL9UTB`41V_l#edk2#9xzkdGViKX5hWLlwQPCeNF!dmJv@5d>nLcZF$e{@nm zm_%Oc!7QSzNgp=f9Ey^9#J7Ij^po!OF8dlbnqnPRmiRdK($XZ+_8Df{4w2dkb$*op zTO^}79+2U8!>0<(>+ppDHFHM0Ye8akTk23x!WKz3uxLziZ-jdI`M-^+-<3O8xy+*( zXg-o}@yS0z&9yoPr_}C;Tgy(cOlA^!2lqK$#j23i=jDHB~kBz8z zIFMiO;9hOVyb)g?DAf5mefxIZi!4|qh9A6?9fFJkmhIwlR$gk*EBw%`5WM>2{;Slc zmwB&L-v<1n^8&SV4f+A7Z71Ql{j(A>7Q!s)KQ(GWxLPf=n(EZrJ>y>95!DyJ?BY?V z3L~EPHO{ggLzTL3WI5#td2k>mOP`D>^OfwB>hPDkRR%(-a<-jb@3Lx+)e)A@Hgu9w zVwd_+wQy0NaDdj+aAZmZOTw2>6L{rqEH)-X**U6X*xhGX*V39E32aIr0a&{m^q>5; zW$e`yyt5%m&g=VY?!_r5+Nf3VO(tF;hggVw@E1G%Gwxz`4U7|LE3tOkjFGt{6f0mbxxI($CD3N?QHGoycVLNt7;YD6E**fH-9dFTlLT2a4I(kuk{=v&ms=GBM2p$UamQq|QOpry)86FUCK7MN%(qEX z2Sg@hK9UCY+ZgTkX5GGP45xI)8((N9wf?=Z>WLHPelx>T7(I3|LJ>|!vYg${P>w1e z85vRg8-XCj?7sM0NxSXp_q3`o4ZE&U56`7U=>`NEJ(gEJu-@wwHKiy`*!z4m(@=+n z>@C4hc#Mv;?xlUU%!%sS_iU^875`y(i9eNwG$OH3s?C?}JX;H5E+^I3zR7p;1F`A$ z;`6$C6Z#ZGM;ORIYM}%&-3y(6bXPVC7F=EgJCE&7tUNi#SM}-vf2P~PT$==0>(YOw z$-_sVRjFD5G{+N#USxa7g&5%UW^Ei+JLAYy#>xFE)37#zS*k+b~QUgn09z>~X-&o=~Sd3dRa zP|5skMY6HRw%WzEcch_mb7r$JDGqAbvd2h=NmLf{=$KczRVL9AvyEIDjD|4M1e8;7 z%vVzGL^dJM)O--liAOhK5wW0)8aIPJ4+^&|mrjn0xL{Ut^}LOE zLp&M43Bj9rpNfrBNK(fKFSbpWxyFmoKytJMvN0ZQ``13authKH$Eo?Dk_?(5*|@RaEgU9*J&b0Fm;XpHwR|q ze{*1*X^gK#y=FkIhA&stq}W2ClamnaeNcj;;eTa;3|~o?CwO8|3-`O8;O4%*Q9H<> zwbk^i8WWR8FdoDE;8UOa-(uPh!sE3Q zysOZkfAN3yXWwXMTIMvIm@zF2o!kYE#Gj0S5x@(IZ*YJZH5^QO01YbX%aBZLufytP z{#sC|H$3JxjfVVa?KJN9X4-gu1MXyZIw}~~3X}4yRh;(Q725}dKuexs;)dEIg=CZS zp`oVkRWn4=MbNL1u5Ui{o0cZ3GuilR(LS$DW_z34>kGGHLDElzJZ1f?$9;ZUOpBE> z7DkjaHt`-VTpGXH!W~ za(!WZTayMXO+JUa3jJP6kGxC09Nsa=O%t=s8kVH!F0DS2}JyhzOo4HDD zjj|ca-5AH9<=-uF6Fl-$fmf3uqO{k@wr`R-vaECzit;}}!d=6?XLAvK3`64=Cu}e( z92!S7k5y6#W`@Jc5;TghzYVHHxK$00JPqo{pOcE+_n zlEQ<9T%4x9ZwpZ>NTC~Goj4y2UEGbGi7y$As#c2kgl>>uk`!?N=n~METve3YZWJIo z_I%F7ZI1?D9o{{m!RE|YZPK@cflYp^zP`rI;6`m(+VD!ime=uYb-W+MBJI)DBHF2P zpnUOQ81qw-82L7Ap_HKgkbvqOj5%;Q)kk<&4Lb9G6Y6P9FzDy+nEC8QJb+Yk-jQAS z<$?MdyQ%iKtmuZp(s*lzihc?4T5bA*sf@?dMp#_IhB(mZTl&|=ffr;SRyxy87|myt z-H#Y%&~})bFM6+E)gdJG*2D~d{gpN3Ip}oBR}NCGOWCt^kR5LX-0fE8ipa4Bm0yK^ z4@|)=zeg5_3cg{rDxVf|cw30ZS_LHa+)QUYkllcM_3pp?vBNdq8K31*BQM`D)xIj= zc7?^jO|_3YpuTl_n?sp9u!f=|2Z``A2<5bU(lJq9aP z)2aS7D?qsUbM)TG6aBeoT`T^evo!nDM$I3UmQQPj$wqAQKe-%ll&lUo8%588pP7By z)J}DE6jiN^de-2+qQg*Yzlpv)Qma$8>u;m(={WkA&8kV%o;_~PbI($|gq*ZJT`y>! zTnDXsa#XT!X(M{_QZlU4O6-A)pN#VzfQzGZlIvJXoEQlny6~tY+MsvOVzQW1FTdZ# zB+y)?biJ4V0xT7=@>66*i87pxEeZ2AesapQE|^xayn_2yH@Z{qkmD945UZQaZKiqI z0d6iaHaRG%wz1eZm27p-kzuvFKHRT!xPGTgZqIh%f*8)U zRQpSSLWow+i64zin|4_sv`n}ukg#zRlK{mi$#@b!?d*#Ki)Xo(IJlioR-=u88IBOw zHZi<3aS(rdX*+KKF|Xf0TvJ5eE8SCBhKmtmlyF*Br1ECN;#mHD>XGwI+)JqenxG@O zDKdb{bXVxNRPBYuau{5N6(eKs-@rEgY&YSfZ18G@0VCIE(Td=gg}?9kYw3RB7b$&h zUK%XXed(ov(esoi&DN>{w>T(%pZ`A35%!m=1{)Q|7mDi||HSWPK;SL~*$lJVl)C-& ze!wb^&{(E~&hPVKQwR$x6MrSAWQW`BzWk})Jy9JfY{3DVX2)k!Yf6tLO(l{jHzz+< zL7$b=dzFo}>^@dhrP6$76R65(dO((yce2Y=N|c)95BuG81-eD8QXYdW+Uv`DCbgSc z)v9LRcGzcKp}N?O$m|@fSl+?;?IY9bEo^W3X=s5g^XfGsl&@RP>a3PGNhHcQn_fQ^ z>SIv$e#-pL^PEaKHc^scKfJ4Z?H<5*MuXCc^wiQ13Fy>9sP#MdYbU5H zDb@)Ui@S+#$2sSMVa)X6K@^pu*%lz1duw28T7QNQ)&3tn##g*{yy74WKvq}du0VQ; zlJ#m72Gioy5T8BNw+<~7<2qE!zw-Jd2cteOi*rGpq&eg_)nX)Gzj^7SR+CYxnxv5` zCwX9@H4suQD*P=>{M0T```5;MNLuf$a?$)#{&JPWyggwJJ>ipguXosW;yJmlXn#{O zThwZ)bP?Qz2w6&0`KoJ#`fH`R<8tyoK6RN6kGg$Ef$6+aRr`d@Dz zJOm35Y>MH6^QJ^m^N6hf4)Osr$~b@K84Z?cc&|re2NKUa6MF{q_UO2OeEc)@3ys6A zu7725mK1H#lkcCP%S#Jy&T6}C%Iy%A58DU|gb@4-!qe{5OZlAh`DVy))2>oUb*sf( z-XQ7brraRFj#SzjimERbnnzl2R$h-PTpV20aqSa))M`7valH|R*m1b|$NAx%m2Q9~ zGu@k-QM!xhh0Gw@(^aB&H1Rlz()W(RfklrQmFFKX$p7Ah*uz^*)RaS)nWtfk&xh5t zUe@5thIITKF(A)p5$C(ZqOPEEm?2yCfImOBeuLypEJwg!pxV*+c^HvF-{256jhwEt zLE?4ciTAslW&_1hZK?1^?&{ zCGJ(+hZx&w{VG#eZnwQXp#<6H6L{K)9;;_3OJ38FTuCq5AG+RiYSe!f>tukFVF+q! zQy$(xOAYPS=r)-9wugF1HJ72k2|X9Cqv!(vhBH8C(hKd(VINoYxI_LdEhD)SE~b&V zex{iCanz=*uRM=(7Z|ZgiR*>7FK~`4smtGfG;cX=pmy23!Xe>?mPW0%7TzG9qOF*= zz(3^AWcC7fYB|%ZDl&Haj(EejImy1Ja?tZ1V?0kVRT&E>T(|0z@94a*zi*f@O|01K z23>$jLhk?uF(8t*=@9qs89(M(DIoyf7=HH(fhr8Shim-sC6fU#d8pUmgL7Gtbj{Kq zCIr@=P7QcGgoh4HSM!rgK_}OWhLcks00gmMcesMzIDR zn5a7$Hh?JxMW%=pz~rhRm9jYV+f!P=_Pg?jLDz!+L@#Ra0{G8ws8mTdy(d7KWw8fO z5kpSMYR&LpMQc`bk~&MMNH7ap&_>4@Pi~t*#yCa4yS-88XLAzT=(V3zM^ox^ZPYLR z=BmuCQSTy+guhdx;O2)(=N(S-S~C%m3eA! zx{U*1?1r0DLNKP1$133+PqsdgMXAc%6t@zGueteO3yXd;#;0`B!4MQ?!o;_)&~rfW z0iTzyo~{Xgyg$M+Y&XwSIN@u($D&iDHUm#1kaE0&jDtxNK6FP@bl`#5F1*$k0#o^s z(@2s-;)Mi@jC%si^`awQue$wW8$KrbEzMz^2|U69QJkJHTM<2}fyM_BMz zK|fBIo4%d#a{+Sq1VHNODI2W2bsPmX_qa&j0Nq1CekSdMb_$oJKpi2Fh&NI^Z3iw% z>oWdquD-<}cLfiRca;Nk+_cYN`%630UXSp2I63aTe7V4i z{U06jQ2h$1V^EJ^km!$O*K)5Ch`INRFJwaFz0gua!q?R&1HntjsO5V`5i)G^Y27~_ z5FYLhI96R3`p$dZmg;uENxPg{^cx4d7{qLbHcP|}8jpD_oAGkxKbb@J1BnIsB&$eM zQY;7CJh7Op?Q#Wf8h>ZZHx)JWxjr*C(S zpqKjFc`0Q~aIsV>Rm(gECxsZtkc8zev~y|0lOt)$-V}|obFQjgJ*x)Y;>c{6u~`wP zVQvxN_@q|M;BpT1=>IlV{;ve&f4*4zWL)f|6Jn<`$H4xS!!R|2ZSd``SzqY$yz}5a z+sDis8Mhf~;H^4Y$~!2+J&rhW8;f^2i|ewiV0kxe#((bNEvne`7>~p9*Fk~6zYrZCe@qQaQ5%e3(@fi%;a@aja*M59lhpiw%CMG_q`xSf7 z#}~P52fY%_m)Bko{wYjJ%*r6;T39}m*B|FH)DJ*By=3dWp}j3u$hI`dvxzw74}GmY zZd!kYDzPNK@ZxzBb!>l=Kb2D7*|<8c0ZF2^V}VgND+t`@=US~MqnKZn5o$*>vsbn5n%;Fh zX_462fAQ09UXnDqpE1R|aZ%G(DnNW9;VMG|AE$!aWQO}(X- zM_t@m!w}L_rFW~bN>XsI{S@}^jh^EA@F*WtJYe5ep88Vur={ZLZZHixPh}$9c&;+; zCreAwBhbnu=}_W{!fq)KhNu(+vZyD;^9s09Mko^JbHix2LyITMlROC zBP1zugbO$Fnnt2duYRXLhWq|AVc!VN>2T1 zC4m)~NXbfxGy>XLU>7zH6k>~_h5IT-YeVR6OfyV+VIh`5c|-`_qx)AN6^Z79%#mcY zavYLzn`hRnt#hda0D4}0*R)ZG&b&kTVlQqOFIyrT@hQXVPSfXCRWC-3VZ(Lf6@$ru z_vlh;$c6CplOHrBwzxf}K??1cyOCWYW~hRfnY0_sOPLEnaYkd!-jdP*UoJ}d(ww|C zJm#cFPbRD%bt?wV5C5jdyZkW*sLP(2#IaGS-U)_`LRHsUka9hRL*Un=J{>e@D>J3w ziZj@jljBfkdxdNtWWKyw8~oh`&4U@1E_?fiY<9zeDLL3S6JBng9rVClpjB5fsL0fG zd%Hd)7k|<(`FMg~&UG1f7S>w{Wg(%KQPC6J8)G;^rfTp7uw?7%GpAdLtAoPmhCn;& zJ-)4dTS;70*0PyMdfISoeXj1Idf9cBSKqcr(f{b;G~}tJ7`q)2V$Q@Nh}AkMfdUTA zvr@|AsAr4Gb(U86^Fv%`cCtJqDjt2_B}a^!^NpIb>wmWHPDWU5gt^nTku$Ec$?oK@ z1c)0myIa{+NcaaS@BOC0MH}YZIYyk8WwWFK3F32VDn*?vYvuN1J);AC^Cy9My6>2+ z?T4b>Vt~N?vN<`s-~#4pH-k!QK??Cx?W8lOBcDT+u@lY{rIOm&G5)?Fm34xxviUfz?NxGay559YZ_42i4>u>L?7t zKq{>q!Z@n}Kax#g*x`V~dFo0%@tR)TS#O7YguatSN1*YdNIR~9!c)DQ4c#}J{^_?slv<()^k z!2~t?z-2h+LS9$B@1Ehgn7W7LK7_yzI^RXnv*><1-8ZPNpIfn*3CYnd?A|kyL6%c7+p-PF0bde^#M5T9;4k1C2ULq)=lm)?6#kRBkR zgh0x9pYy-tzIWU)?zenM27{;Uz1LcE{^p*d4WOKz9&u3WeAD*^Xr>|uHnNqs0SyG* z3LFs3I3OZ2mZOip-Z?fKr|d#Zo4!728K~-1_+t2m)##kjX-Y5{JPWLP)@aA$59M=O zF{4!@){o%CmWP&M9_ua7p2|)rO_+Y&1YLoz6hW$|yS!r_f;$jbT=^(gNlgl~yKD8R z=w7y$$xRLeD?Zbne#^B;TzolglqO3G#Lj!d#sL(h+9iJU@#^;XUlOn>^v}QW8im*zL_FX`evB9ElxBRLq&!k?U!TPG%yB@& zPU+gG+G()(+;0Lxf}}&Hqv(#)9=L+|{ypdF9hXSpHpHX$W#?ascFsH7**mAK?uj^W z%*6Mfo3Gy(Den9{#X9!pWXu(8teV^6dzAjXE}N6mmQ{zN`PV%Ac)KC|UdsJTj1y$@ zjTs?lQ@w%hv~Gn&=dcHmXv?uBr5p8#zNW~YL0%d+9m;CGf=l&RDs zu?o9}KKFQd&!#Jk(`7#?PE43+4bP?H7zxXmfP6sD*KwQTR*xTw{n0ljcyrG(&w}eo z$iv_m9NORdB|PLTn&?f1E?2Aj7HiI>VNMRNpQXjwu?qblLE5pu-mA{zVWCTzPt$H)sJd+~ z_}Iiw?|e}IH~rFJv84tV=nZpUd+lW7(_2pDXgPumZk8-FJCE*NC_ zD&_V2$D6%@4%dx+^TFj`(>NAP?rc-%FVaS*RXZuZtAD*Pp>CUCJ^T3jOprHP_#aJ! zM?vMQQHY0Oam2A|+u;$(OH0BHy()nfF(Rp6uR~qalnjqvWh^zFSZoPRhRm0nX7V1i zshFR0>X$cAhxAeG(9kdqxxHLI*aEs59glWh{xApW*uS`)7UDRVhUChVTuQq{=;5e( z>0zdHdPp)Kvtyu5j;esZ2l<*NJJgSrSK$8oiIimqwR`cSTjEY1l8z2YuZ$-ZNHbG& zxgxL`cvTfOzoG^$2vwRK?|`#G?_TnN_@20b&v_tX12TrRogK0P{h#foGS^#&Bvf+ksY&Q!N6YtjoE6EztJvpLag!uuqZfH=$jI zkh%1{Szx}^j*eTpOghF-wqA!y zPcTn?`Vm$%C4NUZ$o3ZEwt7BuhieaDM>M8J!5txjuz@93f>Y*dwr0O!>vXL_?bEbp zV>h+B~#~(t?S_5#lf%zj*zR85ehvW?6M`2n&P4-d?se1vG+UZ6!&e= zT_|le9(Q)78@_BQ`C`#~!Y3tu|BB69zrkmNZ23NPdVuMRvrvrZ0G+YwNxb^7y z(yZJma>Za)fmni%j=F&d_V|l3%&yGBDkEDdy^^s!R9tCK&a!{mN;MS89@nYqC-HW3 zlIls*nsS`21hHruRtR~T=#6bmLC%4lvc*guWeIkSu@*3y1ml3bc&o2xUTt zc2OJ7XW4purR5q=%ga;j%(c(x0A!*V)*z`BgzwJ$wrxga{I-4T?C)^auluXwHS)TL z(^IY4WRJOos)d@to0pRBc3jA{IxAPBo1HF+@y1pilCqrTB>cE%(b!<`9&{w2qeId7 z1~L4~KX7u^I;)N2m21Wt&D#b8@{~o!N^YVTH3tV{fGSK-*x|ukwLf+abwrN`bVn<@ z^fKNM77;B$qs9?VL_5QnSUF^s3t#1(1AY6h)n$P zd9HmlS26hadqy()HpU%@_C-WIMD$o2T(O#WEBl_y;wA}o@N*8BV`1EMS5bSC{~?=O zCU)uHa}TTN*4&qBlV%1||cQBcLN|wGmOxSL#NjvoUHOhV!laAAg*lyu9k3R?J+eWEw%rf-DSf zIajpHuGi=wTQ{c7uR7KT8ihX(=Ga|PxiasJ=&|9g@RqA?i-ZUEU` z+_gY=0)81VOsr0$qQb#K|C{4rLURAbh`duEg8UqKezTT}0PtO9D}crYMn4G~@}hG& zdwqVKzhbp3lq97vrJBt@cTk0WEg33ijC2U5fCXxA1?RZSG1cRkthpfk-(4Ry z(bKidM$cCJxr!}R#>$%_Bgjc2OBI~4YMoWtg&f|5*KT&?Nl@O7JxR=f7U#T?kRjQH zXum?~XEOZg5^YaKZ(zm9ZxIJ9h}E>%?B&_F5&Lmb5Jbim=R^tPu<)XK-R4|^A>4b! zh;->S^_#2?uVu}wxmf;r>oZVyi!$T0@fRRnx(B0d0+VZY0op~ zjAmPOqz54Ky!Rqod6RR+K-ULNtbcYWYoARMh~9}G?wLd)X0BIU<5m~Et?(!SdES0} zQ#m=TQ4T1DB%<_nXBmd(eRpgn`57e{gatAZtCX)kR=xOeqMaz%72HQQtYUSF<9d|- zu|XnQpTFqvJhWZ`k;-X5LUEvHXO;#mzmqxiI!C z0#nq!quGY4B;*PZue0ua;7hmwEyzIZl9Zw8;7DjemH2G-o5<+Lf$M)ypA`hWGGUAg z;fqW4cDhxmvo1-8l4ZQhtTm-%I~uPJ8>!zhj@4vgIH>%BU5GQ1Y?(uv+8^;2*Yw+&>J zI1G}KvLtk~ktIaG`(<6aL>{QoMtJKJ+QqU#tau*JUHeVO;uZ+vGUsaGaqz@sk^Ds*jU*Q7W;d&K)0i`%g{LC-8g zQ%2mnh^}*-?$EkK=-YapH^=^yHhGj!hJSrj%86(Flm+UU2TTm==`x9^cuJF=Ywj$J zZh1}0$g+3m_*Ju%ki^2L)E9gmWq7_o?M~on!WA%IKh?qHz1ywjSw?UIORR$r?HlUb z#qWIGMYG;NqYRvRD>E!3bqOcp3u=YWK^$#R4Oy}EI*a**i4tsV19dL9yMBA4b$BtZ zHZIstwBiq_%Ut!l$#VntXUhkF0QOiZ^ie@Apzm^QlkSCd9&{EKqHL}Q|g z8&@m2YG_N(ZJIwwRasHa7$~9&Mr%S7EERIi2EKQh{vyZnoX2vT{>Y`7EN5vFm??B` z>P$_RGC}cPK8K}Ldf$m*TS1X>SL)a2Zd(g`DmSoV6LN~Xy#J&W{-O_AgnN_R6VH~6 zcAIBU>wF#?A^V!>Imx^$z#4CU2pB5pJCinOY%(8yCDRZ@TieHgD0HB1cq{H4MMzAM zXY(H9?E+v`Zhwpy#-wEyXle}bb-F#~xrz(f*s-%yJs9=;+A>O2A~CdQ=%+^?krCqh zooS=IzB@He&17tPM7dvyW<~KgjmAF?M!(f+X|Ja5AHql8GH>4!Ht@5p4<+I_i)$5(6%%1u0Dpzo8M)t zWGlr&g_u;#;_aKA*FARtO0r`k6nEq@P@a(r37SViXu#(>;xJy*6jb=qZ$2}s^Qt`= zEq=Y4YdakuHm1;?z=;iPFb-Zx1M}4;zCOJfVdDM+^8~(z zc_QL^9M~0hRCfblM4P5?eES%L4OeRd+WXuq1_HFvR_<|_$ag&qSu5pW>y~0<+TxXP z9a{H_g842o2E6iPxw>`(Q49Zo;!~MJMzm8Cf?RwSJ?_4@eSga{N&fn3x#P)qb_!YjuGyeR^~eoq#YG zIqOV}o5eeK>$W>fXd-%3sohG^vtDEqmAw&?C3y>uT;q2v3 z)Z#*X|D4`RD1iTFpPBCsRjKx2(^7a_EDCuupMmj$ujE1gfx9wGS-RzL5H9Ba*i2`X zdh;ZC;gonF_)FYxF}#ES9i+R`!ow!d%p4_I_qSx+rgT2r7DeG86X9e2C2GueL1wh! zj;bF&b%ybmq==RuC)<&is{!r_-I^6OE=Lb zaDye4jCwAI7)M_5b8Ba&= zr6;D>=VYFggt3YHFYN*C9(HG=3ym*#o)#hb5q8-53!``MX?f{UG6NqJgYFK^9c*dc z^V=}CdfOD7ZBwK4z3F=$fB~h~p{A=zxgL_3x?0&L#H!Ik=ILSHSJKGyYZrC{UZGS2 zCQg>|M&7`4;Hgiy;{2gm$*07{%CS_-SG8VyOy(}zn-8#~Ivx8S6T71~Gn-R?>vmeB zC0^JlAt!uk(`caj$o2unG)u08R)42x8|;>alI*qDQg5mB98%`5Q70A;*6Xd&^U6d$ zQVYRdmsCyqB^Z%Gq^U@zlulB@wQQ^OK7Lz}*r*_$(aH^o#dQ}7+Zi<`62S1xMFEdr!~WgGzm=hDXuo8l|F zilhDhpsS%I`=rqOobo))QFBWWymR(a>SiNQI(jQw>p|du{_3&($v(?M0JVts{>(Jd z6z`Oa0YxkcH8s^udW$tR)Ya%Gp8q;z`8VB*+D!lW5+9Q zN+^FJS=5BISa#llonw^?1%Uo;e1D+*wfFSV-*CxIJg4MA$Go&!`sdjaD!z* z<)nPAk-fe77pWd1Mx59IOYCga66e8#U5Gq10I>Q01`0a)214o{+PBDRE5jqiE7zm$ zK-}?zvZhbfPtFB`hE`Z?>;aoA1s{P1Xvgm>K%ZC*XR&Dp)GV^UNO=nI2ttk%8KfCx8 z#mK(M^(vg|ei3_755sX;A^Eqelg$6=omcoP9SU{GpbyJD`&CpVd`{_=XRn}J+c!p z(d3wxb0~oUGZ-BQQIFQMpl|w;fNOE+#kM{K#tqr7FecjvE6PF5(&*?)m1nCjV46|| z2UgJCQ}pB>5IwoXZB$~QR;;8tPDv85LR5Q+iQ;Mft1?})&96KO5jIiFM2DL3+D+MD zy{>-%^dZJsie4*Y?UBh>mO(_iiuuaD?w~EmCcU!NpVPmHDKtscv7&3Sr{~Wrb*Wz@ zu3gT1DZ4imL5O2y@532j%KI+TvJRE9w=QX+X&3myXs_p=aB$H+BVg5QQv=&uGe00Y zlfuuQ=dDVTwJV^HgMEwn(GRU-PVO~jCr{m8hVQK|9^6v6x)C)(V}k=faWdd0jjyg( z3uGiEec_W%D?HaUe)6ZV5TRqKb!PNeqUqCGQer|av`CoOjFW>6M%Xg$IDFiM^WiIQ zN0Y>QdY1V~466+9rj|Q0E^tlH703AX`(Jy!X2}V^L%Xn0clx$(o`=D}Cc*^j02rIu zdx#%Nu4R<_B;|t5Gp$6wwfQ_fdIa$idrdf7N~uIYKb)=AcdIGmQ1mPIQ+oX_oqtqu zU-pTr0!9e%EL@l)@naUbF$}T$fczt<$)J{erzH5tOjt=_(?@s#^Sdr^#AZlbzxv$nU*LVSy-RE&WCv>I4FB7p71c|Os+BW<^ECh=jv zVah!2gzMmZ^#H;!X!@jy7NATE5DN%KijWiv;cW`Q-He`AyGTNpk(_&SZZ%AZ>h<>? z5hrfltHxe?m;b3RQMeoXg;%tpf=h;b;QPw)#PEzs^|ZZ08yGOqyv~h=*MMUHGtqp7 z`=iO$%UwlGi4S`VxTlCAu;&F~Se`BCCQ;z`mlHEGHxL<{s451u?|T#XV0V|PLus7SI@7+4-+?#wkwqC9sYl~P0WaihC<}f# zigt|xm>$7CNGIcZ; zUxs19F_NYA047zA*mMoz+GgvG)_VPa^gha6lJ>lJIB%_aA;%+5NAr`b;yDNCd_95# z%1wQ*c8_90awVL!De#$P;)#2EXY+Pd=eCIV7p&UH+r?r(xHCEl2c2?G3;GVdI22Gv z)P8(LB50nMOKr4C6%t+(gdu`FfI#DI(e0wmA}` zv0_DPvs`W;g(iW`;z4zN4Ydv?B8!iCda!kH3!KQ;&XP&EKHcVj9msxyn9%y*EdIG{ z6rFL33wpLLgCX)x#YQW7N|*T|qr)Qc#TTVh)F1S1V()Is%}`Kj1|p&c$wOl5spHG} zgm0ip2mRvp*xmQ=eiiS*&K%{>wl_oCQ>BN=L+wbMs|N2IvqB*8UVi<>pB*93(NP3g zuCNzXA|wgSNJQX-*j9hj9@eG!f>M24Z`&3i8sEZo&mvxYsGZ*bDg2SSoWTe(AOKW% z!n(OKe`rhit!2^Z;ll@xbziUF%a33`k_G5^yqX`cUAzb3r#s3hqMOkZ+K{;G-bxZL z3{o~GMKectn!P*1wz{=J!)J6*Kfa(0?A$jGmQP|pxjv$_La_P(jGrPm-AoT$D-{wP zX}1+1uO>vW%MT9zu2Xnz4mwrlEDLFnq;@2BOpvFK`XLkbfgwgPEdss2TZ-K)4gW6y z_h=}nOq;eadPjEu?o$U)5D|F|f!W0+VCRVcXbAxL1<5YEtHIs(vn@=G0_s{J_>INC zU%z)4eipEv$fgPH_}qCqq6;f90+g@~4ErKc4{$&vdS5Ho^oIr2Qngs;nv9mOQaR@* zoS9tv?@aoz{<@2VMP(kRW z*_-q#UQWL&uV|e=*x~yzm*b<~Vj|hQQg+f_c*FxNjh~DLSLS>A8r5ati!XT%Cgglg zFqdm2#EpJrDkQn<>}A}?kj(R>J5Q1~8*NO6z@fs{nt`y-W%x>ru=5D~m*1@K$+sHT zDxnW0$eJXbq|Pxvi7Bfrmb>|kWQ~i1%J6eLhPO5{7Uvs!&ru};@tOq>+7*w@kXeX- z1|^4F(Iz9bg?zCvLwGxP>5sYO5|Ouomt$4vOT#TGKYho;I7pYvn)fQUjfe0%CD-wH z3VPNK2-^ZLO)a7H$V>BqpKc6sy9ZS4;HAxVhBD11c-IA0z3zk0??`4R3jKR-uj;!& z^x07r_hFv-ks0z<^gq}Q;)tF~KCH;Ur+uP1^^U*i108gI!b^SC0$)AEvszOiqbll7 z^_5o6QPG;u4~N-jy3$o+6p^Dpzu1g3^I%K?SE<6z3kf@~wQOZfQElODkF&jMQ;%2E zO~WSno>?Gi%a?Wy!B+jx&c)$Jl%i~%|o%?I$6o2hJE9X0*IvW zqi~Lw!D`1lukL!!^?ddvJrC>x;tn;DWxP1qCNq@7xj$aIe{|0(2Vk{k<87_CAt`%P zGvb2A###r+ElS<5LJdvlVbg-Yd-2ij=~Wlww6PM@H=X~U(=Dg*)z7H)#WE%38Cad< z#pnw`w}3MfK7kwT>R|MS0eLY$jLtY`+2N-q|ENBs?x}>wb-e$$_|oqy_TGh#TeQp5 z<;Og87HsQ_4p*Mzu07bY8NOEgkW)UysVaXNVlj|55PQSs{PjPT|1AHW`}Uz?Vx)<6 zXn|mJv|VOVG9DrQHQvPDJR~k2qDqV(Y^8Z{X$74V3m+8=+%mnbFgo` zAS{@XBg?F>*;T8_fE$W8vDA^v(nDRjdAW}TYJOE#RRcfl)!#d0VUAJJNPE%wV&lD9Qe>9SaP+$W z`m#uXlu~IgX8yZw%lB^#B_7iozJCZT&(-rD2lC5D2VRn-FL@h+3Fnv(6E`!Ndtd^z1*Dx2JpJr$KJWO-OQ40gF_o}OZ=Q`A<;M^vZPxZ zY!Uyd!$o+D=>FKtdS}gZcokw09<(jnAnX_GH?In512IwL@c*9EK(yOk8ZD=&V&?Df zdfPi?vI?m;ES#mORLLzc@!pJyc`0R3B)Q?fR-ZBcxggVHe0I^If|?E;KD5qmZ7TIC zcvj#fd^%092I`c?wuv;R36FVA^S@pkdUI9sLAMa^1TZ+FcgqlsEUlOz(6$_)|D3Mg zLhE9ntwr42mutCV4t-jWc^~_$J%IpPBi@@YQ#Q?TI%_Gr_kdBBSqw>%z@_oAzaV^T z^ywd8AT_s=JMIl@(WkW5XpCG?AkX?@+$e>U6!(!kj5Wh1=fWspakECO?04SfG8?g6 zfHUUYqq>J=nY?qI(|m&&uszoJO9HPR$27SJ`}!NyXz94(?R)V3!qzTZUIGpg5ADHt zK45xfiBE%_BF}1L(Q=7FFy^4`b+$3fHjduKVxZR6Fw4boCsllAtl9K3a8B~+p&m)x z=&aY9!@*~GzU;hyN-|&l<2ez}Lc47(+#0Tk-n4yyA2KH7yVLFRZt~#N*&bHfUd-&}9XW5PBemaP_1Mwohe0pF38U z&i>Ln6kXpzX5u(wNyo4xh@uq7%?Iq3T-wT~fh1A#3nS0MeC1;ymvgYsd7WQ`tRLpS zleylt{PpPqZ{y3Et5>KkTYITYVz35l>%XiY=3A%LScA;O3tEVt;SvXEjcB`F#M%>Uy(xuV0(Xe5E+4xz1Jg%VP!_ z?ELVSi8@}d$5^YSX2;L|AT_w*jFMLdJ}#znCu^Muey;cB%J~Tib{Yl}`o=;Xze-oM z4y%|juz3mhzw|i?D{+;;0MxtxO zG$tkA3(K`;i5!piBiidEHc*59K^;f3=TAWz=l&=DGsL-LovXjZu9`C1{zT^WBsItu zq5`S*4o~>am8&zZ!1fSStp%}8>B(f(fCrr>4AQnyd50u=?URzvDHm1U&jfR0rMqZw z-B;?#$45UjBV*FXYqd-MthPA&iX_fo!b-*9IJmZhkb{F_L~Kg~iCRK(wuqXOi7F|V zM{s@n@pM%0eaxOOts>h%8MX_pQ{da2`rsM*?>Td|c=`y7IFnDIGCfsip!)#dys6Cw zujOOo+?g9|$4SyzY1-!}4XwTW_3Mf0c_EL3fTVj1RoE6Aji9mb+x>a#nCsgUFIJn> zG^wA!F6bCE4^5mj-JvF1`!MXoRD9`{ys=iDo;&=3(}RxV-=R1Sj7RYoM9>geQNC#JxM0=Fg@_ek|a%Z4VP$T1o{r1i`FU1-{yd zK4Z*hmcGWp%Y>uZR}CNDT~E8-9C%0{%!_RK@T2+b^t*9({nPv-1|$2At&?d5fC4AS zfW{$_JKH-g~oGk3>^feGep&O62xtCgMD4m+T1}UglEK2xdu`nr?@9 z)rRriyI_4sdfm)ha$Uc(+b~vXaVXGy(xeanvGQ}}s%S9-O{`2$r*5()tZ{g<-SQAe4kPF1iH%LvbP8*J$I1>*t${#LqwC8t z?AK?>Z32piV)u||?UkFH;MmNW>F1V_XG3>ni>quFN~*D{FmIAXAkaD7MY{}hlPdcy z#--bBw?jDFyHx6?4p;}03$(x8(cHgd+e_l322yj>WL?wlDh4La>|@gQ4c0Be!pjzgC z&*7@@W`bI6gS-Uqm`Yez5pVi{MZo*RXGV><=iI6@<_P1WjS|j^;rGoN7z2`oSS0LP z7x{@DRNK0%wp!n8RhtPkCmeD9PtcU8=3MTB>nF(Z{aGzycpbF>cF_gI&TAk2B3Zw( z_=@^k91)cEh#~*Y4sP;=!~8^h(X0Q7fPtWL4N8O{@;D5Z%mv%F( zOLsNs1pcvXG?xpun2SP52Z2|McNNGFVBtYt}6eFcdufsr)d0_L-Wg;(|NIIVc_CH z>H@nF;UG2@UVPKa)K^F8{a8;kUpd@GU#W2$9{Z?!EgS;x>T~xm)8Hl1#c>0ox@F_E z^T##|9~%|-ffh=Q0fi%-=#C#mbS)<=@!(raR{rMP_Qv7f-nqffcC9I&w(s-1Z{N1l zOJKSMHVUa*TgoL%1i54Pe}}1s4qu~aq)6J{k`dlzv+SEa97wKQv6cU9G}6FX{%her z(KiB$s%}YW$)DQjrrpOYP&mAaaMBxeZDj*N%Iz$>#>ZyI4peVQ=y1KUCE~^{U!l=dZ4?*3(QyPg{f&UKABw^EHb99^?FUym%2zp65ia=aq! zIG;m8qI>Zq9n9)3=bG3_@E6^;t=TLsYPV@~$s`4$G;p+Wvz2*jdCYQc&NAMb*ZRb0 z$(AiTSm5)M@-U0bB!=JM|9XRkAP|fTwaaf$usm`-ewqRt!bjDEHP;v4_8GCN{ODLc zaXVe8UkFB;Glh2;CzP5ZT!ZSUu+}FW|FR0&Xj2e(ES0Dn zR*{D`G&fVCC3>$Po9sZmY*RQYV7{HQW}vxlexb^%Ha&@Mg-LmL!rZ%IN&v1~>$mqg zTM|GJRbc3iIW?=R%3ZcykoVz$lkaVoK{|s}N{ifcwCEVh*X)mZ&0o0qw#Ja$+aR29 zFT|XrUV7K^gc0A2_)r%i(KhAbecDrvd`s)WDtrvICZgZ0wd z|iR#6saaEhbIDdp> zimaE&am;#+mn-&m%5DkJBn`9~e=99)K}_yQHW{$FmOaR&2YWv?gCgH z@)<4!_Leqpht~iRKj3H``l|c7`7W2bu31UgD zbhL5w<<_fO-I}?@NAqy`9%wWiZa(Mq6_L6kdxDwOB zw&GDwcykYXOo?K5xnRC~ZUN}ma+j_7szRGBOV7h4W=g9Ad%f*Dii zI6FSGEA9n@ven6Sw8>vk`1r9m18EXlL(oh!#xBV85;HX!_O7n6ED>*_^QxfqkJosb z!?;fK6gX*sHen@Km0C1uF-miUe;uZc!UbDzK;@{VP+9)rq5`*e(tMCW9p~e6K$k-G>QMb*oPbm+L5SI z@Z5&Hm|ST?7T2ICNnoRsC1DxGg3Avq4$58CuPs8ako(_xOO5jUHMUmN-{j1P(xFs* zAjN771g}(J9^9yqR09asoOc3xeYy6&$p?Y=vf@baYxV97>P%Yq`!oN3axET3k{Alp z?2C=x7F+wzoEStui!WKF^RWY4o#@gs@o}#BBjc@GQ1CU#j`zrIV5IlI(D=DDrnnOj zJ{c;UfZ9{*FTaM~4NhwSr`@K*r}>#$5LZ)sH&p&kZ*ne-&e4W)=?gU+(hhBd-Wd(| z-&$C2ZiWW`sBsqcJ>vkp#g%@;S7)S;J8r~Xn)s=5v~Lrb05y>>(rr_=xiQ4}HxPMf z&iOvGYr<@M_-Et-t5|rg-z|v%;?(4$Ezh?(n@(K$Phh#$I~DsKI-)q3~U1 zY2pgZpEeHSq%h+9iMe=|Bo*I+lF?(&e`u0s*^e#upuf-i%)Gq_kCyAB_>hWM0ILEM z!5|JMP6dSM<^;#Ai~z(pt3|0lt#6c_ltV5sgn~TF4qu~3ytoT*uUQ1O{y7Z+vSvSl z&r6oo5Q^i=RUQPc%u74%F<+!Ls<#yss0^6P-3gcp80#KLi) z#L}C~f9BTMJ~>6P z+xStj%k2e)0Tz&)DG9!Uo~b70;G<(;oGv?_*hHDOxq^yX=Va$P9mdXN{ZwD3S5fMm z*rNQ-IhIrSxdh<=WW%s^kUNnH--D1{p1s)7F~yesdP?t`#=Lfg#Gbc=D`jw9^RjN@ zG7eiBw1XMOnUmR=z(THdqnjCZ)&7FzZ!%|{f?p>0WIXlStz~`do1}PJmZHZgdRv6L z8>WxJVJDjS)oxG|z^^lR!4`n~!e8E58?O`UVr~D)9)zI_!P@(~~jwVR* z#a^v&nH~+&?k$RW)f@zk@tnbmw`b4uzS$1iIhZgBs&tt!(54ktzBo=qDX1_xk}r^2 z|2@~0TZMY>Q6aC5b#LM+{M_X)rTF?~qbqMVmgt>+v4Luj*}wtH_8??OMp%}S%NaTr z3IBCRm@lhZ=dZ1>w?cBw;4gt)-s}FA@vpN)4IrT=Oyg*U*N_-^buNW{hv-z*NK9F_MD}`?Y8Ottxz~J`3lr{tY#R&SD9JRnykV)lz!hXEMrCs z^&yo@!_a)>gfr2qemzxNVQ&5Nr08CC6rLpt?Eso*e=<$u+#(bef2Sx+5MKTq!k-5C z(jlr_19^DLSbqCj%!#6Kz^Maa6^MI>A8w!XLD*I`J;ZgJ+ zoXxIK(Y?xO!Ik}p+^XT-2z*^f&)L$u!WoPCWt+#|{>6GkM&Sbo3E__=c9w5uBo{c5 z0|tQfrZe}$=->)ywrK@QJS4eeYFqlBc`gqp-l_Zo+tg26>f@;Pouq1naT)2B+jE+3 zR|bx*V8O$tBuaClKZ<` zHoO0IRP3_xmPLqFmUnjNo<-P=^{rO!*J{NTFl?Jgt8qd_fm0^o(`s>avp%K{@nWnt zvOWpRdqwKUz@LpZ+F==p#0dqF?Kja^C=Uq3CU{hPwlY~kYqY{+*YVL?WIz?2R0I`= z=;SkaD_pg@eEB^p$?rv*$g;J)AbiSvcOyaM?v8PDusq&JKmK%+1pI^g?3}ME8*e+HtJefkPjNP?? z$?d5E@NAj-xtK-`VJp1)#TI z`T}AXi)iWr4#;#bev3SDfL~o--ZxQ0e{ad}`hTZE{GT4y|NaC9oX{&MfS80YrU~8! zixF`vR9N2(t(G!B!Z2^gXo&s^?(CT>Kqu7P_%yv%ms`96XN7We%|0K=i52K5SPn}bQy;- z;mq=ptD*gXG7;v%&<}1eR#`_UZedREPI8<$j}%oRtN|4#;_?nmETZ$1Hl5cYFZ+21 z{~<+{Kw62rLBkAhPy)Dywly?m{M%A*TeI_5alI*c~ z$YpoDGncr=6CMADI$Ax}Iur=d?n&VDiU;y^P#qZoKc)s>SDmIeI)Co><}fa+hW?H? zc}(M@d2P64xC+r9tV-#YD90t>A1vu^`NtOHv`kcfHijD3N)R1kUn7^WC z27=RsOi_#Vry8xMUh_Xg2*Yxi$)AA4)~qh}$G_+7ceoz@DkA=>k9(sEMX?~p!oh{h zb96LD^a^}#e)R!tBm>lW8!%+C1f_NNS+4#@tGMO12VZOuhrdF8 z`1hP3g*BM0WD(S46>UtC3l!lB>F;MgE{HE-0r%e(hctxqawfkM)Q8rIajlwhSw9#p zHUUOrFTGP%ghnP0Kx`hPm}=aX%RLY%WJ7dX}=7g>lKIxrHlK1HTqeI82BBz zYv+oEkZwKCCf^Biw4q5EC?B$0p5MZxY-w5mw}&QY+oC>_fcb@&36GRZUCa6Y)g?q+F@w{1eS zS4d83Iup#{f{8s=MG_({gcxZk_ z1F~4DpMFeYN|R4(N`$D)FbTbnuTmw97W43n0V}M z+fHASLCPON&!z$amH&)-JN)NxLXAu!oKppOc^PeFO4SRjIy|{&Uq$Jw`!Pyw?k%}h z!d`u3SlZx}^O3U^Cub&I({;CvJqD44H{QcB_S-Zif&xMmh4)K0=LXo)?`Je*4Xb%o zs^1Ltu`&=mHYJ9;z%$N|sr9%cnS@+sHIW&st$J>u7 zVbA+~C!$1oMfPMm-kQcpE};EE^S26;BD%n=FDDW4fML*2r-Fk1$u2$lxm6pb=8$+} zRj~E-JzI`aedFBwi!`S@l3#&X=Efcho4OXsJa82pr*?zzYrB;bKb09;>RRUnlECWh zuDaSMZOzts*!Vw(kn{6!%|5_2AIFRBs;JNt#xc{e(UC{q9IjmKZd0w64RgR@+(r&L z7{1(glf8yh6y9WR&Th;ZR#^9#M_hBU-yDQD00WOQuNr6p%1QEGP1K#+z-Sz=C8R8s z>Ih^M0t1D>$N;R$%R7rLEG=Rk%QM{VkPFAVEGy_v7Qv1{cY@55DUW?=+fJQ3NOInV zIv?<0qvHJ9@PKY8w*FOo$wT>+u@j1yI}TfjR^LDiz}w`HL9^VLsWO0v9NjbG#)o`Y zE2wtRKDIPb&do~wb(`3CAUL0;pkbV!`(?VBq64&r^*ew}V1B6OD8Mr5#<|WRzb#_CB9F=gPGAu{+Pyd|mmMPaG{Y^?u>cpgqZL zm&L`_;v6#TsP)%Kz$wsah57*1DhxtC$;6$dCHgb(mVX)Q-CfY(x1SCFb`^nzcOtnd zF9}OXVEqV0druvgJVmjsx}3haDUsAydd_IqF7!Y9nE5p1f}hOg9nb|RJaE(BQ~b9aAt@CISOE>JcUAs?k-DieUb|Uz$SAUw&_4j{%Z6lzXh<7~U58IIm|HP2NkcY0JobPCawi`eHemaJlU^nUsEW5WXu=m8j zLr9V{V>NT5N&FR_VD-(@-6A0z4lwWm%U%IGLHKYu);Qvn2%__3Ye&LdoZjJ%87P`yV0851+mJLf{?o+2*(q#2m7q<>IsAFK_KvzY!}2VJ9yV+h_i$ z+b7SVE8bois}#PSFW#D4LZZoMiDSihzW!Wv_u$mavQM`9{}_AIc&PsPja#XdB}G|d zDqBcGs4P?2LQM9oQ-lz*?=wlrI#Jdzm7SQx*v(`eS+kdIjC~tsEMu6Z`~3d*|H=Q! z{klEyc;?JG-|zWepX+*GZ;ZSY8pLE2My*CiP?lk$zUX)pj~$3F#p_|7W_dhHvLg6~ z=(T~(SLQc+kUpkmV;|hEc&X7G7{^>CAjThy%^JeDKI~OKag_WdA@@)>KR9xx@QNN< zJ3tM0%yY?FWa8E1b|2CDii@GCp+aA-jH2bU(tR=c7gF6P|D;%I^rz%~wkX?4Z+m@9!yZS`-?v$=w;y4IaZ>`Q>YJYyZ#Psx)2j+5KY4>eAMimTq=-jGJuK zarPY1uIYX+N60+*LbnC4>A8|iDMGG?7E)wLf@yH7h~A*@J;BFp4otMt7s&TC{k-1t zX?L=lgRh;8ot~(5?IQ0UN*>@R;5x4Hdv=&AtgARSycmkoG4NDyBtwDA{ABp1?Pm)S z2%Q}Xey8s0eHG`&-e$*J^R!k2mNr^CVk0=~{TMyoYzfJEn*I>~`r$n#>c|as!};NF z7}LK_)GVcJwDBiN#y|?UH`~-LKWvCz@mG_-a8pp={^L^JBe763Z@=9I z3W*%l0n}wtdm&?*AS(VbX)*5E`P6}N)2cyQ*J0HG%!V2WnUtqw)dRGpdC8)_{6v8X z&_R#YVpgF|RoPl6a5s<03l`cTs;@Dk^R&bEz13o98MV+_&(4P=l#jQRFMfoF zsNek_1$AK^k&N5qq+9o5^wx4mEZk0pA6X51dd-O;bBt6>qJ1IIt8OA2jn$_BPJ z#b0Hz?cAXHu2GB{Y_wMxP=7eUrg869D}hB~_2N+#NehQOhXM`^vfRAE?e>kM`@dkn zg-u*KTOl=y#hUd3{bAOZ3e5z*sKAwjTUvu3eYhSY`Ie`tHZO5EjQc$O0iUCFGqki3 zEF+fZCwn(26WIR?NKx&l>Y> zUa3ISN&!r3dMaOqFjA1ZW0+Dl>#q9d-tp-8Aaf~3=b=YxrG8{oW8{#QYNx*SkBiiV z1;f7%vlM3Vl(6n!5kH%Xd3fA;H+@&0UAn$uk9Wv810Hs&kJ zTqz@OJFRjSP8~SokB9pJw>y?=4WrmFwmbw!Uyh$wd;Un~Fs_L$s81*K1mF*5evMBG z^>nUd3wzM19W`6mzEtmOq;rBAe*xlN)w~PaNIZ;{EUimwhP-&x z#&mXF>KAnVww2lgOgx$ZZaKul<5G>jkf-{OuU@Aor?l~{M?VAGx3?h}=7*WtXw!Hb-oBeUe4^vr!-RZzq{-#5- zT%IWQ#VF#up%Y=sxegF0;iy>RN0-p8?8g137cuyf`~d!$Mp$63J}~G0ZWvi zdbvj)!~@Je?tJib$sJ&%iH)k*m?v_=@m53Z%<2E*yczqy&YN~7hq3^IQaLnZbqd1% zhbQ7;Qwyl~!m&e%|MlGj!ML$BPSxQbZ%UWyG&B$Xv6KOd#yNutaCPjPeUY-Pks6## z%c)g!GSoT+ODU73bpz%b*m^baImCWCasE^VrP(FvgBb42w<%QQq-fRd9_7o26z0XG z-c^m8n4B<+w=Bp{b!eB~ha|*gHExZxKnWuU#d#L19Ob-EkQF>PuU+4$`NU`I^9Lvk zG+d3u9R+_%RO)!O=F_{tv37aPxgjektJe-*K1h>}q*^Ugk1Cv&E%)FaLe9yBr();;V7FO-|*pRAc-0=Dmz7~5$7VoONy+U_3; zBnr&4ClW>h)HD0en0)sm^H8N#N~-kvZ(l)jzokmMuVNo;W5-2bDZ+CjPU&u+(aeBH zxu)f4rTaJ-?nr0gdLM6{*g{o3JbW#n0Zf_oE;|)peAt=db%;|Qr`qY=DEHuOwGFR& zU9nN`*xcOvNWwM{o`T`9)7G$Bj@T|2Nfe$!KdZ^KA7eVMRQ^peJ1WXPIB!vOP@?^o zbOt4&cDAikI@y0Z^gAD@-nZ7%Q32%8rW9w2`nNYj7EGeq9MLBswY~c?+aKx z(osWH7n#DlL!W;9p!b!ne$Y%wp!hQ?upR))5ZneAglPmjP7z?ya}%|x*HU#-=S@6R z^Td)YvJ%t~nHZJiG%PTzFF@1u+VL?NCyyhDpWY?TbglX!erF#rTELY<`T8@uM~r0? zhXvP7NQ~IIU?;suXmE1Rj8-Ty(a-jIP5`Q3L5Z=M{4UMmsg|T}ge;kr$*y`U6hzdb zsRpAuABqos#zO8u8K&RvzU96mRs4V>LUxpJSeN``9l6*BKXa5%v$ihErzz2&)TG2_ zsK%i0r>nzp)lSGB3~-g-Jaku@VRpZ_Zah~jH2Xz}cPQ%O2SjI5gp%jdm^>Z7?2Afd zNX<;3wdy0G8CEm71!|e1`L{j|dU+(CIbU8p99$dVlta0A&@2U}bR@ffQhJ*+ulv$T zoN`e5MaCy@jA23HexJNa2kyu>t-mCHcV_~sG@fCRXh57_l(T**IB`E{E!VK;owyZ^VswP!mcWn1M zVMg%QOL=QRSVnumD1&m8$xT}67Owiok~|~=_+eQ0(E|{h@gWv|vFz;%l9G_^S1w1$ z9wR3SjgS?=N^k2(Y<-o{u)g%@SHlFb(BvpM2d3pQX#F>*B7R`JynKY*4 z$A2#QrokWKu}c5}>gpY89wh_kV$>9xUaF&_9JunMIk z=z5EGwLVA1BqhSBIDiBo6@$63$|FdmgWa!&ylc%1?CqBpscUeePMmcMeRBG7M#nz9 zc+Om7O(nE8xKlPUp1xx?jI&RiS}3x$)yyxiQJDH$npT8-`s5A0GtTQ%ga;W!$)n=u z!PINq9UP#)ViYHrdQvWWc$ymJ5CC=xh{jm4p;F)SU^`_a5g&P>p6%w@Ud>E_4W{98 zpX`fofmo6mJbH*O%ZLd-Pugu$RC|FrH(EoxV~yEM`KEL^2xw4!z`X!10i6hF5n7m& zk3`Q%r`#H(>eU=NNw;11c!@na%N4&BHWHqG zb^FrfUAOTBm*4LlZ(hGAsX}waih$?JLn}W$TL8yqr0>8x=5H5TJK1?FgnY&!=Qo-> zBkImvH*%29&JGNppk*!3n?H;31g|f%(Jx@1jBbWMBeB{HJB1}ViYU&mU;89ckmmfZ zt9T~IiHtI#e)tNcGqnNlE0|mU&HjuMgd`t@248p3QTdboxZo0IThUZ$;CMXahd^K5 zjo$B>&HnhN!RL*%K2q*owEMu#or%SWELW#5fB^a9^AKGtw9Y43&j_h{t_Xj3{y`@T zh^Tffo1Vc)+=89-0JCeV1Sc#cS2>+(n4cT>(IC&rbajvL$0myuJ?mz!qS6RL=#4q@ zUyP6_L%&m=&b|$hkX>cc?ka_f<5wdh0r3$`6iyt1jKaAXm2@>yKE-yN4qk9Gq?Qw~$YPzB_qlv_f3zYFpg_6Xb9Q<& z8PaC&+CF=h8bXf6rG^OMIx1j>f4-_4)N)*9?o*knj#i8uD|GuE_g?btX;Yi=K!~tNrdt32h;RC01iSP0Q?@sW6_|xZhrq8M=e6q_MDrm$w z37VDPO}nD+?L@@CabN*D*We`RL(+}9N->=a0|%<9^r~M$KD(N&e|&Z(y79Gjn^WY2 zd8ycD6Eb%@ly@9{!uBub^O5+#P}?{Op>*2J7tAUHnMHNiTiuQkdspUyUftC#$ZgI& zu-^=$=BN|iE+!JcGBK`LSSL)0bPx}B!JkIO5~Iu3-V5J(f0ncALrZMs<}#+x0p`6s zi_NA^Dkj4diZw=&%MmW@c&jLTQz2q99ZL-klwEkJasx<;&faV=L4lLy-+*1bW8r9M z8__q6;jLd2A67z~|3hj`JSI#)CRZk5CfBX=NQvOgM!b;mQ0m|k z5%4?!cIqfb1BRWt(B5})BCW7BSR}A)_Q7yX{yx)U6<#;^E&#&CoC0w*>ZgrU}6 zSsT2+yCfP=?*ianBH8!G`PUDNc)4t~OZveb3o9#MOkXjbk3>)%h$v{?3em^S=`-E2 zahNVfxYcBf`th~wT*%{rxQ6KxsTXp|9((^-2rH4d@G&56f9}}OTNN64(J#_}iAAhT zjSbRplGyBK-T9o_BEDp!w3#lhTD)b1u32>XnZ~g?*9N+poqG>;pvP29;i2O>9!=5+JjlS+B&jB?&UkR9}iDL%IaYTn)25pz@FtR2c> zzki~GN6e8eTxjk5*}F8;|H{7nMfty@M*|p|gC-Jk5?OqfA|KQzw!y?Pn%dgYK^yAt zr@8GmqwCrSb#TXbpKm-%KDwr#{S>RxPs`0}d^*k>J?Z_WKr{)IgRB8>=9Aed;IU?f ze0SLOr2WBjoodruq9ONUF8aQ%JC7NMnj~|DC;2%sVg*Jww+rHrq~Ss0FD($@;G2h$ zUwkp2BIC+88YkX)8yBM7`GwN{9(y#Q*gQ-K<=V3TE`1QXj4qw(bS_!9;^+Gfn!(+w zT#aRN=DZpm@$V(OE%u_@aEqjR3pE~jV(`JKLN%R z-KB$qp3~;O8@`xd(PhDow9TOctKq@ZSMCK#JYdK$k%hsrI!b?D*q~>kTh>oDJSp^>S(3)75kkO63E>h@0U%b7?B_?lS{E>nwj~-9CCxpzG$Wd-po#ztAM65V zVfN!M)M!W%J~sJBSQ%S$mH%2EtbK7ifU?TicUEM==_MwNzWp1pC{dt z+pB@#k&tn?#6X;KG}B`uw+ECbQ^S08>pUGn)X?x*NQK(oYmWvjl0jn+aZ4@{;) z1{A9fV+F4^0f{W|@n$!m5O;=t9;o4)`O42XVRCB6%X5)dnI#ge7VACQ#-Itq|_t*Hb6rUs~g7eFy3DK^1Hi+_5`FY}hB z9Pk^ps4V8tCOSa1Y_Bs2*e+|j!uXTDnY;S7Fp8Vd$yxiR>hsxB`I31hyWDR~0MU-O zS%U=>N}2x0f>&f`)RUK;M^C?F6Qg~_BB=+Ab;K8j2?0t&dz%g9CqKzLC<3#~ttiZ# z?ApEDCA(Aa1=|I`?Hl_X>~d}4EPd~rz2esC{oa6Pw+q@oa}$7~Aiop;Sb`CmxQ&>S z(Bdu)-d0NXRxz3NK3PrkTb@8uyshrBlg#JJNu`Sfm`IOpyf!7eLb`7D)_3;59yThmFc4^{+ zTuZad{J2k}HFQba^whG3EV+mK5AXagbgvamp7+gea!0vwO|aej5gAXjxM& zd`L|cF7j3y%43qRJS0o`IyB|LgznN=n*#m@CDeC}(Iis+SL z+YSe=B!3eb_=`h+30wNj4K{{yv$8vs+GJe-81|=^q z*I_&95>^>GGf3i0&fTbf8-BYubv{p}&=3<7P{kgqeOR<$KXIdG)jzC7ciw{ozHhm$ zR3put=dFQVL{KNT^iChkHeiwV^+_b(JEOw_>!;tL0zb@YDLN0X6E8yNub6ccm7Z|1 zRa^U#TXiF^@v9BTQ}7a!)7XsbmtZR@LH+!k_hj!}Y%76g9xP^xC3!~&ctrm&?3Rc1 zE3c(wT}TMuN>z`U+^nBV+pmN^gVvTVZ_}jHug0R+I%SRHeJZ^>aw`> z!Q8F9&Uc+ARAriOxIa|@fa~NbH2x+usuiKFENkB{2u}(|Y1`rjODMO99^8}02MT&! zsKi<@?+uv3RB-jE#K1sDQ6K72&}03MS?yPM1|l&yFL)s&f4^h@0h>#QcLbM+gU*g z9DHL|7);mx*7$}B%fxU|XUMSx{5$z(lR1>YdgBdL85}n=)-qi#frHQ1!r)Xs52a2# z4^u371B&R^Lfsg4Jwxs@RN0v_atN#4tSWj!?nh*H{Y$@ zcCXd<4KH|e&mu*sr}E6)`FN;Rp~sVp`ci)BByJou5r}5^Z_J1h1{2W`uD|Y&e%NU_ z2Z(csp>(f6prJ?L)d;ioRp=wF@C5U(qyJ#!*F4YG<3u3S@q}*x@4Eh2|hoA(o2O` zQ#?CT%D*MQ0loJ++>s?0tDm3tMY>iiZ?)pE)FVXJ$K7?PWjG#8|6k- z_(E+rA44HqF*j>TutJHZu8a(YI1Vqi#d~9W*3N0ccJzNNaq{~@#VO&!-^b~9$Z*P2 z=*18tKj(R(*SKLf(@Z^s_nIJxD7w#3o!DDGS*)+jaED)*=d}=erW5LV+2r0OE1*_3 z@-{~r>-7lPrObuHPcKlr3phYka_s--DU|>eIbpcZ{09Ct{v5jWhFri~RUyH~_f>}7JHxi+RdWV8 zCHrQ{Xe8^a8P1V6RlTXZ%SM{z8PFbp89A8k(cq+@<9=y5DzJZ9`U8BIwQZqo$$ff5qKzi@jajc0kiq02b3vs{X<+jBq%#5z&d| z{;JP2VKpm}^&F7hf?YJdx>j3vYa5g{Y0(M-k8~fC);|@rbfs5RGK+Qj($yw)^Gn0F zBQOrJNNZ-hs00;HHpIbX7+;&U;La{y;zk$Nc1uk7jDJ0R+H+p__RnoQ!0_zXk#{Sj z1I)t|UKiSH+>WM8y{dZBTu?8+VtDRFum9P&oUrkR0q+c#W>Dgnn4*u@bT3s-&aQ#6 zCMLy}$@TNJxT9+=4Lj^qQvJ zeXjlv#mt4If`*-D+@zJ-eNd+Zm`rN}^JAYyc(=`}lDNC>(4Q5r*XhnK4}=_ZB-59k zM}@}^H7>fo;ezL@3uic|DXQ}wuf1qE*=E!;IlGPOrnlehuu8sKuwYWim)7_aVM?td zi_L@DAX7oD{H!Kv;dd4?{WspC(+2<6I>46AagelM3|S!E{3f0rPL0f`2S>Hy+4j{o zSP3FBYAp{Z71%2~div(z$MYpOkH$lSPC5tpJrZ#nw#)m4Hxjl=VgzVg_LX;~>G4-= zVgg-T!e1~70CUeP%V(O$_rPLaC=NzpvnLrmx4nrV zwLTl)`b?IJm*Ah6NVvj_$^vDlEJ5EP`8Za++X{EM2ga-&Lg)O=^=}`)qBpm~jYDk8%Gv$PtgW%#N8A)q zYCajh5F6DTMyl&PqJOB1jqh}tzpa;b*~Pbzm5zCO7*tA|G76^w+pHSp4ON+(@Dpb*)dnc6-Lkrkau~C-a^yvN(JvBS3HNVM!gU6pFs|{%<0tZ^~2Bk zIH++Y^m|yenJq?zO8jQ9aSsaV8_ndQN#qZks$sU*#Sdc({qLqsDP%OD){@V8F78Eu z&2}!0Fm_(-;^S5M&(WpH=&{6pPe1Q3>x!K+3YJOZle%ZQ9SdBrXW`Ege-|hvjIWwp zhGe}~e2ry3f#4kC;~|=>Ox*k;UUv)&zdA_!J{5^e|HmRd10AL-7{|982S}H?W6ge+ zNAPIuQfwGsfaMoEDLXgV33>b2gD-YI_N}(cWYD{5nd?>k;#Kvj+7F7fccyw%%$7L? zBcDE@qsjRc(;?XL@XMogp9KVhXDZyUdMZpZ?QAi!ChJmoO2pI$$u>x)@$FUF+5GD& z!h-6`cddLq1`P%5>u0L>w<(XvD;?e-W`7*h=4JZwHT%>viw=X= zpDIPnqW6-pGAhX)JJ-7|d`T!5@C@>9CdL%5KDgDz|Jd?=4Z`KnP(2MuO$I+1!ojrkH76KFK@Eb}UCc=jrz zNmFPYF6yl;!UObW2-7^33vRZH<_27<;Pmi{J)Kl15P-)G?pndQoJX0Zw!GFJ60+gx zsGS>ydVOCJtLbVpYxS=Mf6bZm2fF!iHt9kIPXr9Q)3-h`cJ^<422O8wt#UI3JW+BT zwP$La3gV4DvW;lEKqudH&h5kRKCbNx{w4NkNxs=TB0o_b+>yuE>A*MXl zV_p|a89aw)BpdPuu5o?y>9T)h%RcAxJDve2X$Pfaj*(_+i%V*Y0~-UXQr$v=J_d7~IR-_qbf5%0kOIv{^WYd!p%MF$`)EA{R>>W)_jk!nmI?tq=qGgOviSiRjP>eH^%hyRea~~GKaJl4MtKvcL4D!~(NFYK)vndz z9V9u6*&J-bLFy6-ffX7OcyQ8=#+}{I#<35v&#|oG0`S+_+nsp9U>ndmhc!gt!SNRz z#2*uK@7n3un<&+jLSE&RvNg%RaI4OR?^)tbk)@kUce+$}UJj8^F<58FB)+wAH(ZtU zDOk;J=$yfbT;o)YS8M$9FMn32j0ug+<%C!S^CEzleDjaxDb+~bhwQSfZ;^UC+d}wB zWK_&g+}Clm%roiw`BGfK*WCuH?h`6PskiEmh@ElG62DAKY0cCG1{t>vuE~ofpyI&Q zkDwRSAp~ak5BK6#8f$&kEQ32kQ?e}^ zjgU3LIyN;w8vod!HNF;`nk3dWTGnC}z2(`r^Vk=TW4ahIFfpo`78RJOaG=55g$$so zEO%CR?YREZp#uL-w^tMk)Bjo7HOqw5mOa{FC0U9CdcHjq97G0vJKz#1EDDh zZ?>+a(4&5_H^R3+CyL9Qa}``g?;7+kbFEJ=pq(sWJ22F)hVfZSn&Kt#Pfd%6#l)FF zIST6PIRVN0l2|C#h1M#+X-%MHS>AJM&|@p^RZrV|&cVEJ6tI%{VdR(9szA`N}M%hwi52lfOpP<-e`ZLnVMA z{l&e)cNg;?w-4m&`+*oWXO5r zWWK;5Y$JX-V%d=M)(i8}xTLXR+BQ>f7$)?HyNWu>vhPoP6YLKy`O7 zgt*Gq;0p(BVtDdE=S@ap)n8^i)M~adK8DLQ3XpJ$yw3(~gqJoATjtwiE#Dnrd zxTjlXK&~sn>L)^O`7Y*bU0tQH+;xMg(_$kh5d?>{5LMzj&|J~l#f-n2i9sn zro?aMGo~D$g8!U3{W6_x(Ng{F7cBdZ&+R_vySx7DHaBZ?X?c|(j_BOex{sTSBj93R zM}Z3@AD73)DE6;l?fjwdLqPFbPl^ZLzkgotx2AbjUO{QscIjRba~fL%Nz~-0-y3S? zCk@)wSEb6zhV^UXlE2}ehbPa4<4raUYD3-?J}9#-wGI^+>bW+GGN#?0$(x~RF@Jv# z7Ndk#lk3`(wC)yRXUA$2a@YbY5WiNU|boZ7~P5>)(0=E6*|zH^Ks^5V#6& zTa9vo->+spPl2T0=DrwwQGE1=q4Dr}ZEf&dbO1K-rmJNkJe(BYkE}*;wJ)v!gFgJx#KNT) zHL*Y!xe0-P+wf=$rac5rMpi`s*B=AYhv9tknPXVC_8e}i;VmbiJ679@GWK6Q;D3S4 zpnv24*VEMt(3AkH{$#ao0yBhaiTlSQ+SCl7l&<`*R2qZhkCdJbtka=~-)-1tVK)##!DwFf${>7fj-FI^3`yT2fDy6fys9S7a6 zFk~V8-asGS=&J6^pb|lZ+QWeeS@D>w^%@T^Ol0wIW!J>|Bi>`(P?0c6AWb-rI=TAY zeZiOn%N{l=>+18n{;BnmRA850t;e`HBLgE)_r{yf;XaW*X))6fe|=!*9Vka%NVP{L z&j%`RCcA{XJ0@~iyQi`0VmJEC7~~4K%`>9Og$qq+vTcYeknC5HK=JaLu3>rf6eY|0 zwBPqYoM0tDh1X@|dA`K{fW&A&wjGq{Fc$ai1rVfiQ$<5Wdxf602RTm}%jw9FoNA%u zf`XbRbtnP18TXlLOGz4sT?X8PlU{jFNCS>Y;pTVd+Z;2pTee@VG0>)|c;e4FLbP3Z zx%cwGBQLpm8}F}%Th|_bleu7tf~kpKihU37F0q9h%cKna=>Xrfi(mJD7!S3z+xq$D z2@<^3E%cvzOBtefC_EQ{;gd)hZL?C_oJ_iJC3#-pm*n4NXqsnhAV+wSxR zI&y^o;{vqz=E`&JyNC`?o=LMI8zQ``c_p^g;aj1Ruy}*KZv+^CLLaMikV{S=v+1-n zypMiJXiiLhLS(H7;U?D6WG0zocyLhRl!`VOQ@LQJs2|2eeKn`viE^|6_rQ8w%I| zT(wV&mM!>--A)ZaLXSH(*u7*OQ_9=N=65+-t*HCcH;A`wxHpDe zm5s7`>?{8+S}wlv>r_+`K&}7rI1&D7_$7UffyFu_feTyn7Jv3D)t~aqn?PH8-jr&! zvlJ&OOY7L5sw*DGyl0ePUG0@9AE+GiZMlwXa{Eo@Z^Aex><+DJHq<>_2fAKu-O!g>=Af*&f%RrqpifYBh<$SeaqP&IrVxJY zH!#SLnuN45_`K26T@K64&B_s<02TEvob%jC(9H3&3)$(F%f6-kd=*YJIa^(mqeHq= zY11B|*!CCZbvj0_Zet>$m)LP1SVW5Ap~oeQJGz}-%I-olv1r_83wiQj0TxFygY{>B z0-c+j(s7P>UZ|D1(6huEUMX-%QT4O)nwce6`PVh$2^|mztQTH`z(M0@xv7yf(~S}) zKPj=d#CGkJa2PRqxq}{ah?)=ez!gcO?^jn zVKY7E`GoK0>U+9U^VjlfHeqGehse9n6M+V4`6=ui;8;K=gU)QKvyoh%2-!`9COVmM zE8VNMCVIbb^h=@{a?f{7l3vwk>In;tU7XJpKNLa4X&wVO2S7o`U#Q`jzjxG7u+UOK z5VucQ(6aJ^C!3@9&qMyo*|Z~9k_t2lc9!}qtQ=?2;nPw8T0xYiqL zQ@?z<^&{tM!k1rr{ox%uz~H}!xlm;BwK4AsEr5Q3xtYr{QYp?BqNxs)XP1OO4a0Kb_3-VkjO>>QgORRP@AaGkHvoV^WR3M>kbN22(v4I zFTXP)&Xo5>ED!=IiF=OB4^RA?|kcUyAK?rx@BUv#RMT(x7)GN;cb$wN<15~Qt zh<5?!35&Vo{c|rCMIC~#{PB9{RCjS5&I+uWL<3rvAz7933EN2KL%H3|77mM}lf~nG zIb-E^q?yP5v1~BYx_kzpdK~J;>}loZGZf6q!1a^5!#P_STEDR`!G90BkiwYj^xNdv zw{LICM=$EQ1PVXayO|*#>I3~;4V_khR{3i9SX9jcs;ioL<%nq#^W~!JSr7Wm(3`9oLlHiJW6i5-yiUuIRLxUz(9Wnc75@Axx2qp1p%JYkU%qb zI|%g+cDW7h=IB0hPzXuGY&S{KBp#%`2~*3nqGaE1v%-SCaTUuNd=>*r#C}+a2ecYb+@6QT%94!eM&7Q3XuQWYC0(2K zDRtTId|2Pv9C#pRusu)e=hN@*$xg;wJj;kd`0r&LLBb^IMR;_B<&*&2w%g@2=Idbsi*sULDV$ z&}QbHg*VP{EsR;pk4==MNDtC1!;dA0sX3GFYX(EE#Tk@8GYs-=kF@)bQBm9h6~^!s zzgE96)I6Cx%^Q-~-lNbZ5QQB{=?_@^Ybh3^bV*ZH#Hb*bIbVFuQMxDXj#skTeDNl6 zftwEoK*U(&mJ*meT%yB0xBEP4rAD8;{-!fY44trp&84|JOkVnN60VKmb)x>0an;S4 z{AX#ij{TRxZF+q=5lj!3VK)VePrc{X*bMS<~^D=8T;^{>H#blkP6@h)C1H+rA zWS)G%!$8HS_!`zSEBAWtNJ2Do*cH!j75(e6FB|KA+4-iMcK{c$$Dta(ltU9TYkzcY z=jR?i_K#5GNew5zqltQ}BQpYs{-Ku+0aWQhd-DI_jUd?oB?7hL%H)Vrt|Ft_%Kc3! z(Ifl1f!kGuZ?DnYAF~mR{`WQAY)6IobFhL1RtImr0uu>WC1-S@cs($hPrSTtiO3lv zJ^ku_r5YAX%buH7&;|jjxQFsy1+EkEcb6bfR3?K6XH$y)u8Z=I5@?3&;HDJM8#d~_ zu7b{Dg0$uXWmR5ua`r|mvRWm9CPQ6VP}gKZV@5=~=1;yk41|jB@Vs;SApCmvzNzft zNJ;coPi-Vb*l*XLQlV{Mi%p%B7K1FTwwIt*`I%>M3me{?bZP1bns&I=m{$Nti%`$( zFqhV2-`_gk-oh7Z6Mk0{xezv81>cgSDDSf;DMOtFF`-^AkAtzpyx@bf{7S=Ctw>*&M=+X+f zWNwp(EU{IgWoDV5EeyVJ%*t@I(m#P3z@ZiQ?2hRE8kUr6vyLO)Ew4G7dD1+BKs0-L zI$W>VQ0cl7xBQ)B$!E%c1fvYBra#) zS7K#85-+GTaGJ?etnA`MRG!l4bY{mB6>!R~7RgIIc&pix--?Y+V-Lj+AG1wkfCJc@ zcg&#)ApQJS-P42blM|fK>*wjFZu#X;!8;!92-*)}&`neZOgY?=yn+MAs{)g*D>EDw z23xmNC{jQZ(a13q%~g&kU3@COo=;Z3?TekLxK!5k;8-`)qG$HOdqIiXJ0}*8*e4|= zwcO8E@qb`(jja74zkjMR(1Jzp&#`-gA0MBblAUVN+~RuBV;M6)GyZVKSkT`1J}3#c zME7g{!6*gLC0U_hTm;kz!Q_=cKHce|+;c_EMhQSy@lWjW}_6fP}|979bi_p@Vjqj*4g7ro|P$QID_Q7>0F=p z=O%F28r9eIAQEj}yb;{d@^k|x)=-0PYRu``z3KMh-K5@O+&vb0NmvSpt(NdyMD)yd zM?d!_YALhwtBd#jW-B74(%gYI_k3a(2tkrBOr$U%1p9GOY-yj7M75y6&WvncwPjs{ z>J7!HJ=CwY)xp`amzH@RVNDq+Q{w(5-#&9!Of^3IuE11OWGnKRYFje_DP^K4HnAdP z`8Lffq`D6IIIBF#mSmJ&LmIPMX~RbLuloD1um6A1Vpz#aOb#zeAZeyXB1g@Gh--E7<%~2E9JvDR zNB_T=r|zC8)G z=}Eg9eveTIlcy_;G;5Sw2fO~Xd9M1{JsVazArx*}bAM4k&)k(qTD)Y}9;Q2!Xx6A5 zh9ih=&IY=A1rOSp`zNqpW8K@JaFg{qP|4Yq(X?|LJe?t=VpHq~+i|(XFjrd-b-U&V z{xTbvstcaQ+SQ$~gwijlQobiFNG0>mt+d~{QcX1?9qCjLSG@e)d9sf}K9qZ9wRFh4 zoP6xy0ayEWHVb`HYG<$D^YQ>@MxD=$ObQjXC*2~>?zIvaIje*5iF z_DyChCPgmyP|5lit=BE+nIDEvYhOID-0SFlow_DwfXWM>Z{eUsQ1j>ISsy$fdl>*Z z+ngA;{Nv}3fuEbL-T0*0j^TTh(Ie3f$^oM~+>LbLFm?;U=9aHLEC+&&?uXfnx}?tD zIn^efTi|S}G}w!?MD>)VrpK-YZAu5+(&Q#%^Wx>ivS-rBy$^ft->0&`g^nl(hCeVn zdHz;6ZfkVHZ;%7C3JpVG|3M@|7k#kEWf%O~$RFDfm8Iv8R!;0%`g2SvaJ4~ePid~A z5O10xBgXpAs?$B{(2(ghT57_tLbH{kMXrA7CfV?D-c5ZAh>$V4?_Vmy*Z$ z29v&jB0FJCVQn&^{^Zx1ls73$-ZM$@RnZ5IVdFp`H(Za5V4jJcqajcKH7a$-oEqO= zNk9Fux#Goe|MJWGza~YXtlyPs#`1z%91?=yz>8uaNRZW09+!-7Np78wH(B#Hz&Q@5 z9~;vYUY&#|DesXgoAUqOcMb3eyA*FY)pf4ftE@-M={9Y8ysi~AB{Q`!*f|4jb6_8G zMYh>IKZ`RI>l$mNtD6+g9;ItHkV+x+on;?NWyw} z3hgO#T2)h$Y>s7t@oxb9OR;H2f(@CKO|B~WFW=3m;G~dgy}r=nvK!z(1CYO{c87EI zR6mk@$58Nx$8}e?&6^Z{aUPg{pISagfa$D$1|*oZ`iz*WELB#sHiFxX@kptB_7YT< zvBJm3Yk+Zcigd9GO2wnet4ORfmCc)EfnIJoOFpp(%h6+xj^Cm|saam=ue%Kl%19 z^7Z!c@z>8I@?6ixGXHibP!&)-j3l~JDRbOGp1MyC!@ZKqn(r62KP!Ti!6`335oV*E z;eiDldWke?0wTS}Mi-IZiS#DD zLr4^)g9r#njY{vG&?6nBN$te8sljgd3s@GDM^T77H5Vyus0X;G3C106LmaAk5&qE#!^adHAv00<*%Q|LpQ?Ny{N7FkI4Dn8mod?dojH2g*Zd_fhJmOir+GLQHjfIApqXq`YV^WOuBQ} zj^Dtk+I@oMFC3k&iPMK*?_bS59Ox_~mIV#vM;rzaZgs=ivQNO;8&!5iIJwY+)$#9P z)B7>hD<&xy<}Q=n3bpv4w#M~S=eaX5!vJ8=empFPt#)V4Z$q(}&6i;<|9VTtd&cC? z4!%u8kwM&2x+21BCrMbs9%yrBM8_ z)TnqDrL)C@JEYn?%Pw_G8boRM)sI`9PVG zyVcU?#xT4E;x@}`EjS2sPE!(K)l;^fnNw5PwQ05>yhvtQMX>?f?|lc}z&ASow}!%= zm%6KKo+!;czG$Uqmt@O4pVGlRo3M}K$bl+0HQ( z#6QXHaKPm^tuB@Ht~fk?9C#R83!5uKoiO?5aag?nwJjF1+7sOh5)Q)!uAEg>)}V2J zha;0>qM1Syx2%M-+SD)^R#N2?9)AptzpHd-)J1Cq91c0u6-mIA6euRW5%;im>J!Zx zKl@f%9Cv4>g~et})g}`vF4u%me6yZrDajqrWGw*6h}Ou`^!@3ZQ*OWqKsP_DS+o;N z-On*cGgjwB`l!d0K#Q;KNPxV{gFcqU4k(-DWTfHBfTJqTv^K8$Xr}Rs4v%9>tnYy& z?@mXZV$z|1x06uI#eL32P#$#hk6!J=xz77JyUM%?uY^P|4R#Dd4>?lWuSCL#KWVqm z5N~wDeWYoJHL+Ef@Q>?#-i0xP~9d5kQS!$_ApA(I! zMI4;ixB|=jV8XERL@6?I>-)4L>@h0Sxx{NNGvNu1^v3wQ=z;80pN(+PD?%@v0(K9_ zj`j6i0flFYjmdeg#%gsDT8fO!mAy^|X6BGq)udBkA%CufC6SUHg#cu0_o!)Q<=J56 z@3{lxI)P2Pt=vH3r;9voVC0MAW;3gny2~`5&NGnoAk4G3%C+-@*+<6m9#IV^F?a=x zwhdm)VA}-C79yy)xTP*JvJk|t;Mb&nDc7KL8_e5cU(4AXCW&mHqYpn^lH_VVP?CQF zrcysaYZ2LU)C>h`b?Ryvc248LD5oX}My{tDRHvWny|Q;i0Tn?vvr*Kw=xp|{_q0Br z>1~HLT$E|5Vj_ZfX`y$ z8|~;Ng8m7Dq&=0UW78v3IT~7(c{odFxU)?NR1-QCZzPQIAMyS**eT3Z`W?IX1 zt`qX?+g9~13{qfU@k^0&=29uKXSm)wc3 z&o25dFl|>R!MXD_%PD?(wN)pSTXveYNNP~g5bPvuaG9CG2*N(^fRwObas)1PlfC=x zqIEBUz7$pm8~VeEkEn6T9-5!Wl3c_23$I2OUB$*Vil6T_f z>!i!0fFfJNq+Q@z%pqa0)Oh52*frho*K_D_1#M+`1i4!!cxJZ=Hqb7BPMLI{zy527pmNZ@eSYSIH4>K zf0+;B$RFyDJECPQOH2KLG5k}xRpZKBw)yac!J@(o!9CZ4u*%0bHj~JQcc5FCEX=kR>qlpE90gY*<#brjY;yoWy>&o~F*_|d+ysUt{w1fmJ-sQ+FEoXH zp)U|vTEEm#1ykz+p*na7WIe!;KVw>D6{G=v_>XAd647>*Rf|FCW3|xwBu)#WN*YuA z&G(8qF6KLt;oQd~%a}tJRbve02-jXbfD6vtslIJQDP&P zqiZ8_sn25hLIDZeD3v_P$7PkrK$H8N!8mJN5FhslS65?zg=l%=D3^x1E zJVGH7A8%rJpoI=<0Amd7t>Uf-VJM^w&`$rSrv`rfoBDq_2PEZ2VG{vz53H=s=_+PE z4KeMWNaO5p9sdU~1N_S#6vVGwsJeNa_l$asQyiaz6=+M-jA*@q1$FoeO**i}=8Gx% zTMOL0Z(c`n|B2j+u}pna)?5CBqFk~MBmF$TQP19=Uu8=Tb5EAVee&e=EC?eySHnLx zHLUX*4*Bw8LM679*p&VcE271M&^$0TW z8z(KZH~lytc4J=^O0#LSAAlAgrraMjKDIaR+clnISh{`I&?jQv88WX${rkY^X?a1n z%BeBxEH7C9`~zfK&%7C!;eiFC;?@J0$%B%9zZyntA05Pd#;GL>@~u5D z+cjyp*(|)jS=&(k6+pZc^t*bHUFk+z+ z>L>gRih6S#7Yn~5ruhYO_iQONi@hansKYoy>7@OZDx*&Q!-eDX@(>*Y>BY5F8N$K- zs;+3%M2P!)O<LOQ18fYbXjLG9$5F24U-Pt= zqzq>{7&4mubb-E~j@Gb^Y;Ed*(XrFwX|4yR4;cuDPFa3AV@jvnVu#8_+Xj*;VEZsd zbCF>Fa2zN7-6nGz&|#EY7gs_>{tILvaIM+}AF!+D2x+=^J)(P%C>aKJRQ!RIGPUk56UV_LRP4fQgHlvovi%i?TWEoXDrY zO~kURrU&GHY(U;WBv*#&TRI$f|9ss{CF5QG+p`3PVCIj^8j#?Wv8?lbGkw0A%*wwg zGLfEv>uwEtpW1}AFUfQ>iU5Y{X5Jxzm&0O1bdmGlERE_M0h z=OcrAs>V9fEoln45id&ci;)8{R$eiE{d+n0ett;$BJxr6l-B85f(DU!xp%^Zy{geo zPq5Ra3s$yxD6Q+WHBqF9l*8>SxA;T!eSNF~Vz0psAT{^!3+MXH(6DCKnUS~pa*Kd^ z-M#DE`AHYiT?lVy18;n5jsx<18_Mst*KuefbdLCJpXF3%wOtEao-OYbnOTrp|K)|uTQdjHt;WGq(%3j)mfVKOJ^zrM%t#d}~4*Z&59o-E9%_)=y<{{H_``^cYNT_l- z)?Sls)9J>yI9-OKsv5@1UBvb}kGE>#SK~F&&DLR{@8Y~80vxd_m517wx7cc*%RN+m z#W$aw<#Zmtl3A9T4{zgC;Mmo9630y_G2p_rTF$pe=**=>e$e#=)9yU)>oVe*0#{A# z`(tR%E7QB^vTmZPD$+Y7D(CM94EJu&f>-g>+>EyG>JRcAfj;aS^pf`#|qQYrc}Uf(H-?bzWu$;_WH6XdFHe&za@9T zu?+L97){1%f75lp&B9XEwf8<8|wKCNkjf zE$eaD+en+7EL~e7sbN{VPWg*Gib6@hOW>M-WTfCZ? zCV`9*6a6NJXx92F7`H$!g8WX9OA9m|4g`gY?|?~MV&l4oZ!LxjIiC$mXk-`8c{6s2 z*~3bVaH^Ug=|K#xT>9feP|wxj>Ycs&!wJ?_EjjXa#jxO3a(s1-^eJ_mOlfBKkE_H! zCmYGMgZj8w=F`0VLgEh23iVjjri+ELEX_j~zoe)>!O7ROSv z!J9|TmCrz-@WTnbrmQ4Y6=OiLUXx{tCwEoGh4|%*>-8@l4!1qk*Yk;1iye*^9Mi(5 zADR7Gw$92|Z=lZyBk0sfh&Rx%G69@5M z6&`@|!w={Qmkfj?{EH-b(`y3jAbc?|$VM^HF6RGdqaQ$l{O_wUet4U6_HY}RNCUrg z4;VNu=_kTN;o{@}w@da8&;jmuk#x?XzQAZIv0^ccV$BT+OPYK<2|7c;hMOq^1Zttj zzDtM{7dOYRAUD_;>IT?p=@T0t*1rh5rI)zI`X$6yd?>|j&$}=^Fz%VOb?_c+=VhfX zzvTY%>Cq|mzT)!IoPZ9N8sposcn>XEjc{M?cTQg^hYJ!mE&659g z)zRLn1ZOGfiW7_PVv)~C!Oy6`I^;=$J35lPyNZsDhCX0jJg2*!Vu}{4^nnIk-39} z#}3bYX{PnL|ND~gYA+Dmv)bSIpHAaW-;e|EjaT8X#F(+Nk*Ae8kAG0xnC;$XKq}1J*)K^`Ho~$F9>z5K>aX({|p0Uo#%_} zX**`o2j7gL&CF>`x(WS9Bs|dReNpr>5af@8V++f$iN8VjU=MLZEn`o_V{a*XVd@gy zslUeTlFU9H%P}h!D7-BZqzI!Mj|KgLRE%;jX0Bd475-6nd7s9$Z{2pA@Z4a^!!eJd zfqlzI;4(4VdyrpPvzIW3zJ3!$J#`{rY9@=@Unhtg{qpP3q_-G^LVdt56K(I55}Y@` z%)C9GaSb?K3h_+|@2WE5WVRQ+*YhN|vU;71>FVxH{HbR6@L8L#+(mneOmaSE?c6hJ z6Rj@SD%K?X?tMh5%?m{KO{Xip@|~F5&WfPU>GIW~6=0c|;lGxN<31`dXMPVFrGyqB zFqlVgYjL;MGRgWyLm+=pI_E+FV$cgwet92aJhw}CyfYhGwP0e(uF8>gi!Soav_|?0X>)FrruQOrPa4HTv1H8js6mX9#eIt z!t!^CWpec%N85)VCe4-IGH?-ys1Ep+m#;Oey$Nd>priUso3QOa6%B;EAZCtwX2-MG zf$!RZ=)3WC*(^A3r?o=)2JI4dDt8-3hwk|-W`kb(EXFKIt#OM@BZG__*+4F>u-WJ- zBt9fE&HG+p!sUKlR=79|F?5s4LH#;gJ7 zcoYgFgNk7N{e24o`KC53q`+KBYqK`mg0n8DHA&C!0*IeWHjC(#RO>T7vNn@@%tk9; zVsYf^x!U3Z!SdZ+6awgROljgnK=^nB)2h@%F@GuP_ccZi2(&KA#D_BI3-|2D=`4Nc z5kIem2iah*jgnr&O6A*)4{`EgB(uhE^M%)}Hnt)LHVo8_w-&E@I);g`)y5SVI^?f8 z$F$ZMqG10-|IkbDBiEF2@u^EsAz!}obzBcKgt701#7_IJf`PBXXdHjj?f~Ai<4QBK zCOVU%Q$ov8#(VW3ZP8}_i+qy4jMlvS|oeYch^5Re7Lg4 zO{f2-R)Iuj^WQ)j59pwyEg(CDNg(dI!1!mdwnJdL1?&C-e!^KaWiG(zOJ+SkEG9@{ zfkAC#nrQ(27q5a^CkAesCpvdOacmJc?YS%2nb4>+%M8!zs4AYTSL|36D5VD*%lBZj zSMonL+x&1?qydIb&f-BlD%MWw4r_P6e(xTs9*YX^2EO%B5)6%6<%pc~%C(t!zuNnA zx88aa%WV7O^Mje18^6~+nSGOL63^QaH@Z%7GAnPOxD!6P$xCRxhFpnTYNH%Rs`wM}2)(T-KyR6Gx>zLZ zmwH8?T%zQ$ROh^Oq~I&nW#usWu6?#=5?;N5I3Q0WuFNHj)}1Ff%67hEwvA0N@p*-k zRWLt$>k1^C88Vo&rw^pQHB7`&)n1-+Ms0O8lnEiI#)12w^q7#ka3&u8 zlO#s97jV_y!aYNSI%G*kU~GP{spr+-LO6_jYI+TRdR`zfj&@%Z?gLquu|auG<|2Q8 zj@Jq@gRC>#mOz6jqVf+X5CpvBGN+n6HKi6dYS471FRxjw^)6PdM%jvmnpv`6|JN7S z6%wiPuW8>l{MlmG)8rw)$IM$KFQ*fvP6B2!v zwBG84`E7bxwdS%VWE43|R6fQTQTq0C0Z+Dqe<{_usT_^b;`0=V3sS3OMqRnLv2Ayl zH`rSQ)+l`mWOLV#_7=I|bi>P=Jd z-bg@@)0s8xkl)Wc}Uwmoh-G(sY6jvh3o9$L=$gH5lkES`f*Or(v6COT!V>7-I*AL+gA8?oQ<|b*Z z)G(Vr)np&2nwKFQze-pbR7pm9uqc0&O*Ds5#pLRwehJ7H?V+cCy0~2_^TFu;h$*#u zmwu>C+d_iVwN5x|h1dvYdV10MYyT!O*VGrN5k3pXjB^`@ikJBv|8Y12kpj8bmp_tL zd40p%D30TkNDyjQX%*VW8M^DM9cw(lmUl`7Ja$t&~0e=*wGWh947bV}aeF zt?woMfj}a0S7)etgC4IY%alBQHh*9;d+qq6co!L7@y#oq-@>6+)ZGgP=buMP$_#)d z21-|Nk<8ErrPs;|25%}9aYgwWZwCf7y0_x6fM;UtniE@WHs1WA#82&zdBNC-C$;oU z;QL>7cJ2il*hqbX`)K2EFsc&ryL@J@OEOCWYv)`@`F3~Vz|+^qHkQ*WnY`Zgl-1L; zqP_jurm`~9*`s=U`j?Lz+3&JAjS$fy_Sqn(mZsa14VP!vLBBxl%4?(@?eFh*rS!6kXp@f zHnvpw3fttS|7N^y#fvuGYuOnU`cxWt-`x4lNxaS=Q@&n#*mjXwq z_QkvRLlrTPaaNBE_*0a`ti3Ol8E>_Cs6lte1FNqfHtlf4%MMw0L_4a%9!|xB%{4JjxMKizSHP0vxzC4;6{}F5#9o^s}XgQ(Bh$OwUbT~C9>uW{0lZM6h z^K@9*=Ieb3k}yfLe5&>?cl;`UW%y&WFgjl&`Z<~|)H!=b3GDZ`%;q~l?p0;p^8CF! z(T&r_r?uV%P$^7^Sf~^ojv9-vv~m@tYWovJXxZa$(5K6#e!q5@q%P9g-c*KYW+TE1 zEH4G0C$yoj`f8j+Q(bKJ9m?z|W)_eSS|?79_J5+U{t*G>%TCSc#vGklRD?I<=pgAV zCF=Wd3h3Ygn7>iljQ3AePALQA*y&8H@cVcY|8W6+$K(XH9VCyTS(*AwcrxQ)Y!`b# ziT{%1A+#K;YF2G!FAXVIJ19NKtu;JIBJUs~|9Isy7)1L-kl*uL!URGbh{JM=Ve2hk zgHSj??#uCjLz?xN7wnOrgYsrnwRm;vZyIbezolkN8piPe0lF8u@tL-@UF~*XyqsEk2kvFb>+vRt6c1v68m1q1=1?UY)EBG&7_H*J^60qu%iXBsg zJ%#=LPvad#am_U#2pBG0Lq@Ygx~}d4gWK{IT71*r|831l{{8(wC8l8lg{0^bCE`o$VW7-Cn zdG?puK?n{Wu5OTaZ4^v)z|te%^j;5D2!vuwk{o0wAJ~y8XIU- z(?r%^^z;czOM4i@)3uuis=EW)FLhAoY!~Dq=5NUKuIB5&2zUQg(h^sYAJ_B6rmuy? z9FA8k{#5iWiMtVaEgF4o@Gz;NGkg^h7k^VChk5?T;7b^f-?Y$LVS;Bbxpc7+m3h{; zfh^Z3WVfMal!E9NPGG8%;d`^DSp>t}V}R@}Exv?5mF6ei>n)dMj(?vWS}Zj-IWR|= zzPezjj3`oAZmxHKuvPfZL*9wS>?Is zHt^jVI95e2sASH*j`($?O}*QX-ky*08X7-w&(TvcA8cCDZ=0-26>08#ogGN@w+UMY zIecL85#P}%)*9KOjg2^?*m+o;nLn*f`Es2m6|8pbXz9pPZy4a1Smt}rAzZ(C_>aMH z8RUR`ME{Kgd1LG)&qWkTMOmU+OP1l>!EN_>gGIN=XQgjmM%(JBCuMXk=EApnC&!Y^ z=5O*>jC;q>8GS=&3tX{fGI*FF#CByf;1LRfevmfbG@s11xci0}4)wskZCqDi3hzl%b4*MqBx;DL zrj=FMLyB)h9L68=nUwyH3I6eZ@^3y}tl&W@6HY++MN=!itnK$daWhRi z#V^UzS!EKPsW7Y)y;;0JJw9%6>6100-q8spzafZiYlq~Oz1|gnEK=*NHp(Y-B)k?i zdq?<5B2iI9LmyAA)i&flRB|=?b2WM?#w+vXs*OsTA@G|krzWXL9( zci6}uJI3idY2{Hh#eoGxC-2kjSCb^YxJ1gLG}Ny9jUH^6aotGDZo4c0;#a2F1&|cw z%`TI4ZADLcNzUFh$+kPK955&O@dc}Ysnfgg>JM6lg48ctY&o5+{1ZOS6%bsHCI8$%mf>mm`Mf*eHfqiloKG_>ND21kvx^+U$h<_Nt)<~moaa7etk0DWJy7=Th2fAlO6CxP1BNMXi zL)UgSrLAY9K0Ei~lGQ%ZO)y3~Qp8*iL;396J+gpWf1WOI9E4nf!o+wUr-czL54UQO z`V6F7FRsvU_Oy5}Z)w+D^6mahslSiJIE#z(R_B@Sh#hV?q%-cM8x;^hdb0Z6VeLYXFq=WcI4UCiKdag9H>LkZ+cv-f#3Rvq_yS zSDk255~h5cxZ&0iDICSd7{jR_ArrJ=OBC0hSBJTs_GPnnoX#>6T6dcYwNNIWYI%U! z_QJnSFkKv|y6Uc=CnylKrhQ9_L3D}*W~PR7yCes7h&>CQyYf`>0(n_Zk;Q(0KG0Fc zmNPIF7A?gzExe~z8>q%u8&5QuZeNx7I?+7zqzS2=l4EV5w8Q5|Ihs~at5c|5tP4Iy z7V;mZ?R@jPbdtyEh@|wTX!EZxv%6^K)Ar+AB9NV4$~P37imZ>FF24ReDS!Czveot$ z*|3=5-e9Q`$Fns;fC{B)O&J%0U@R9JhODD-mL2rD^FF@qt zSKQ0=ca5JBLOa!2sks^u-5wk?(VXP`OhuzCD3(yFT3jC`o~Z)LT3(wiGR4NPdYhEK zF)ozS9-!wLZQ8-m8pkE6&`~AtX7-jfD|w;I155B(JhFP3?ZH6`j+H{ih3tz{`^v~y zrh8JIwFA4dbQRyqOP?{z2dFn>&B~kcWYRyr{T}Ecb;r!qcd`UnA%j`B>Qt=U)Y$yo zTKIFnuYPNl;9V(vJXOtuFlnud%uhSL)GD;Il_IAv6xY zaZ#ED$30`$cYkii<=$aL8mlX5&ZKi+TmEp8Yu0Mc$dx3RKEw$UF+aOP zUh}})o{0~~!Kw1Gkr;zc&6RrBNTw$e?#i-X8wSR<96vSP(1KZo{25_1>?ph}#VD&x z!R|p7F+A--J|@ok7wwWKGtHR0T&?QPYgp8+3phFc9{w9@IsMA@Km)x1d$QoSs!93$ zLUcA-}#)D$MO<)-^4CjD~z6wbO_Yf}^ldYnV(8($)>a&&nP!r~^GS=I>!O6>Sr;FV$YYI$6qEsy8A>&@r2hZd~6T+l@; z!k$)^g>WacD+p(eEo6(f1;X9){S@$aCy5t7y0f<~TP^y^7lxuy6Lpu8F7N zOVW@X$b>Xh+Wv(j{7pz|lAZI@$okCY(|yCK;iR8m0US~} z2(3Kn^j{OKhu#T`x<2OQ&4NOr)%eFGB!J}1gD&swo*!i+vkdSB?tKe1^Eog6Cme7E zQ<`J@SA0S!H)Ab4J}mBT9x@xw+PvE@+^kBOW%Rv2=2rd|D~q;U)7+oAc7qC_mCCKG zTZNp}HR}!a{SJRzbC1<{r1-_%v3S7NU`m`j__y`dxjKQI`2Rp08w+0aU>VIzKSgY;uCu(0Y4vlPg~=b&uhzz0@^ zjPzQ%3)Kl8gO%T!H#VKo+?pGRuj?VI$|iml+x9JJWinW69WZkGu0f&{gvW5VmMPhs z?aU`Y{m9x-j{)}tRWSdr@+bQ*i((SZhp$zDm?8$0O<*Q5b=2f!WqBlfvbxcSt&>$j z7hU!HQl>JlFPAz_?$W$a9x&GpRbLKe9ejGThy0nQ#dG>HufdlC1r49pgnot@6gcLH zgk)^h67ea$WBf#P%H^GB6-A_-!*W0B4HJ>tUNg<|fo~6iZ%mGU#mUOQWKWXJ*@4ss z^2~^e)?@k>#zK!7@=hTZ8-4wd@E1Y}Q_bP2 z-+Tj^{Zfe|d@{Wde^+_w1o=Q1Nc3ZK4PAO5rWs*Sz0;`wv%t?;e|M=wwB)2pG^@YI ze10+_u@-xIt&V*l{1Er*FM-WZVI1NYHB*y57&!dcXu*W$Ph{=4$frualuLmX<-<&$ zKjOvkpC8q+-N!(Ybb@X!LhnOuH7{-TpUo4zPX`yH;SUouk%Q*x#g`#b2ps=7DrFt+ zg661urM`7p&9tsTJnqFQui;{UKISNq^6uptZ?m;QZz=6?YkZH1gKvDFgf!od-jlLs zl6=AaCA!+CVJe5)&h+|GUHwtDb!=&2->3Dhop4h2* z;p?dvhvN{=45iQdm@#$IqGk%_g&kyX?=<%n|Jkq&Z^IPE=TIb0j|p+2!)MHm*6rRd z2N*<3S;u;KX6I_MUA*R?zUyykzbTX%d=jM`-oZ;7Q!+QqaA5whLi!b)E$mO8WW_na zg%xoyw|Os9=3lT@i!OQ89B8FAo_3I|mvHPL?m_#;w2|%uq(f97D9t`o`L+;WhbB5_ zL^{!tp6h*vZ6ohSs%~jO8q3k1RsegWPx^9@GfPMX$#k8UZfh}dDzd4;#v=w z;vL@{Nz_R)B%!-BKjN`B28YxIhLY{)<_y+$V@5pIcYMRR$lOQpngb<6YTqz#(AVqXyMN1Z>d;S1DY3-b)1!VrhA9N4zYOKK%?SPf9t6O+s~tfRNW z{^nLKh*n&xEk)l=|u%Wz&w3$Qm9@jzF;3uh6z*&4n_ zYregFuEi>pm}fVT>|DHSLQ8JH2#PmSY)_JRyDU7feK11P$F^ZThT}YWnNnHo)n}0w z45Gw3xM**hS+GhH6*iDa?->56)%&}6FV6F?&}p&snv+v(IZJd5)5aS5%g2g{`_K6n zOgAg@%^mC=_}xB4;v{pQM7M7AQ$-m^im^(Mhj88tycM+DO4(o4cGRshSW03f82xdEcT9jnuZ29xfd=u#Nsl+19=O+N`8iMmT$ zA#b+6id*K{f4w%)gf9^5tM7h`%-v%7M}&k>#Qxc_qFQkcGs*k{<+#EE5PR)f5p0$hQdVB=SuKad}~ z{4O){mL^s%D*Moy=eHX*I?m(9CX^Xu7Sr;NZ3}@W*4A~}7X3@(`t{CRHQeXDMkBz~ z+Pb?DztU92vo`6hB{k9UVrejS?c59>{3PQk{@3ZYElHS}uNni`bn@HMO|Zo@H$^dQ z%*TKz2Dn*Wcbsvl#r8G~e#MXdYoIOz+ejHh`~2PB$5>jR`TIvSPl6NkK`>J_c^`-( zCXqEuGgIf( zy6)_^iiKvwXlD(N9Z3mnI2vD00?lg?Ab{mbFB$lX*5b*MnA00s(hb9hXC>;OPXtoq z&aYi-ueH}#nz#F|bPk~0XiHZS=VnWnr?3w)?nrb&m|Z&RGMvojJN4xiU?(8uX;=3S zEXS&*8QL+dK7S63iWqTXs4xL(Z<;$XP7TIco^@HN@gO(nN)$07d#|hOcfma*FS$l&w3ipggRgW9MApfpFQTO2;&XD z%a9Nc8P-=_HzlQ}AAJ{c1R%-FI0ft3@YwaJr#?kuz09EGHKURqafdnTZLg9h;Srf% zhS*ojX6pt_u_@8H)^)2&4)vgmzolBs;NY~-7^S&R%4ZITJc1cGI?2^4m$BvyS2S2a*Rf>%YSG0j)9cq%=Fj zj!$^r#SWj8B8huNt%#oby&H#Lr zZOs{x`+zzI3F+fmPR26O3X({U#F8oE{c~u-`F_nWitsk!6L5Z0H9YcU!dYl(AHscY>Ak_?~w{)^DLH3oi{~Mxsu+%WM>{VK=99H`$DPSe*M z*v@K!P#pOXAtpatU zvgE8RlByBH9}&BjNkqK@4e@qb06Gu?h{X}_bYaFX<3H>NBTZ+vjG2bV6fkH&?xDD-nN!V{SxZIbI}BwIPC4=Bs;?jp9R0qOf;$ z&M5Ct{W&nPb+!TvO6jg@r3T;LmoIbk1_-^v>7L9UIJCxvjB0;dBh+kUCy|5~frgtl zFf$d~id``0_bxCa^b)-Rx5VCNa#RiohWckg}HnOCVG=4Hfdg zNmZqv`*wnoL~O9@%V_tz`u^g)&Y@*`JgVFif#&MO+$LUkm&dkammKXPZN=pCGP>VS zAuJ~t$|Vm5Zz6F8;uv;$e;6w;T_5p>Fm1nf9y^M2l@c+%e^=#Weg}RMa~|UYdGCk= z{EB_Mp!8nfQr2Y{drEkN!#dK%Zl_zs(Jp$One#(qHVY-X_kho*40)~=!?2wJu2s&I z#4ktJjKv%McDx2*;$*duvZujciTbA!&`%Lk5l+I-*?wAsn{U*OxCTK6U-4^GX*;cP0Rj>@O=YpR~> zO_|uO(v-W;AKPtb(VhECEe>mHH+ z>OYgB{ljZIa)wg5MdjtXIbkY#zf5RmtiD*muSONfo-ZLWD8RJbJ?Uo9%5hO+)(P(D zTWWm*bK8iKFT2v;JGRk&S7Ha=*~guuD6Y(aqRNpDfO;}GTAdrt)|!W844UM9jjqke zEWTIx2ljDStyc45a?9>Z1`ez?mtmcl{g<{0P>;mo9&dzMGWmGp;)immz!9m?d2Th4 z^np9>szBN)>k@F;r;^&m5Tkjrq$cu9+sDhE7ls-Q?(})-myal*8h=YKir+8zIX$0< zoI#i3c0BIUMli93u<`Yh>}quvYF;^L$%Vo}-wnQkV8Y%bqz#PC%v+SBh3<76+sjJp zZv6U))7{K5XCfnM!!zapnRq6wJf8x?gmEo^y-hezPfO1dq#$Au=0Hz>3U3Jst{b50SnokG${`a(Gh&Xxbz?|O6uWHVCCC2=HaG{K5 z03s==O#Hs0sMk)idIoT1W{9$cl8hc8b-^-vjI~>X8SN&;WLxYd$%}a_06GKXvKI&V zveCi)K-I&&*~AK~t$i(p>~)9PXYWo!n1B*Sc{5@J!$U<>%F7IIF8iF_cp-dojk85+ z>{LKXY@#SlFQIm)jxsDrDlQJ{0=7dpoT1@kTjo|QxjrKRtJ?`2Frx~+|BHV9^c~e5 za@<4^`2cp%Q3I`@qd{yk=slRfa@bDgJ+)bX+l{wkGb;%d`zPq?;`Em*N6(sHn8Ytt z;wxs}=A>XJj7o(T;;Ant)L@=pDKf~|ncB-tA)z8@Iv1HHyh=lV4HBGZedP z98WZ1a$YN|3wnZg%CUXvN>BFape9LRHt7SuqCSyG6w#P-UvMQpced3&FeTf)r!cmGa3|V zJt;f}!_C3NHgr04K!Kuf-20b2!qe|2dTKSdHhHw>p$~LsWqXF$@_!w+7auYaO#t)K z&c*13JEV-Vd!gX2bf5WZvH$3-UVx-!clW{o1v2v;7b1EY)GISHG~11k9k$R!Odx-%X^n6q6i}=u`y=e^2b1{;_O<2RB8#CkD}g*YNb-yJW>7;rSA>PY^*;dlcc{eU zCD~|i{nQZ=dSFeYj?qHhNiK3@+_oC-n1Qo@>TYjib}sm#2S6lI^O(8{RxFsoZ}9H1 z&YcM_C(G*$=RWk`yof)W`q$25zq#yNXZXE&EtULrh|kH=xNx8qBOeVMS#eMel+d%+ zm7v@;wLjArd}F~+mhD2C6CH8!ZhIp&mZmyKc|mxH?b-ufis)_UF=8qxHP4&nHGZZ{ zL~BtVx}ULgbTwMFN<^X!IkP^YzOOf&3S5-+M>O15{#tba*|}Z5&69-pBr5ApN((jG zvPd*OauyP^{uuFrWQlwY1?J04NH-atpp`D);ZoNuPISOoWL3Y06l&&~6Lc&y`?_MTaxP3G`HnK}7bUDd0g@?LpeGO?KDIw|*Q&29?I>_Iy=cE=wCDD%AQi^LJ ze(h`G^7B-!P=4Jmb8RxasvT{B#y%naO5Vm!Te5t>2eQY5xiI9T7aYi>EbK~lM)iU8 zBY+W=NXnTHt#}c{ykb;RwQ>i%DO=p;@XfD@ei z&DzTv{U)(A-*E9{VhkC1N$_C!_!$ZLC1_PnbsW)k_wyTsp7msuvY$_A0AoYfww2vyE&yWx{**y#9W>_L);HZ)H8Ptz`*< z=Up1+gquYyA$uW_1Pf`*XLUem@pt}T&aQ&HZv!i>E8{0jb`h?KzhG917y)yfNNfmi zz0Ng#Xw6&a{`#@dlNzn+o4vcgE%1jn<^x}nM_XR*R=NngI38n{z@4ZWYaFs;P+pg$ z?*c2?q6zv&468r{9ai=Z-`xEzF`q(hV#V^O zVd{bI4wLUX@~`p|EDY|w95T#FF&`pV(pZCB<;`!BsEKL-f=l8!(kDY#EJ? z&enZ3%C~FnpFDBn?YTUO?%rh;o>+3=CBhiCXQFB_NTdsMzE!lLzF8!4>AG#aj!nAr z5%=J0Ysxu*BOqyI7ZmuMux%;zOI$7U%8Yg6JP?WrnGODVH(q)Dcnp5SmdOO|P zvd=Q){dej~@}^0;Wu>VtCR*^r*Ju3}QdVnUW4rEyrFX?W-!3djFu?e3y&e;By>b5U zArzPdJtUFIhO_Dggh?iAerbBAEZUh?;=GXE6DMOWk-uW-IWSOwc~L9c&%rN}QkMqJ z?Z%3UhUKZs(MB~Zd z0P&v5X(bJx(ltV^TF?B@#7bg-fv}@e?k>W6YmuM_nq^eQyITO}!`2naHnxzrumQXe zrR7|^jB?09zvwp98qv8}58m-7lpXs3w#Jay2D3A5K)}1TVLUxlN%uYN)&2urp*UVK zh}0)IHr}D;@1k!wAS5SD`we2CNHFhpFtsq-`|n+|Ug(^B$x$0I!1@4`Q6yi>a|D}_ zIgX%ys!NIi91@|?^iPSx@h79wwdb+bs?PBq+H?0)g=nUBf9wW2sHq5PzzyLV#$*2V zYXol%0nTF@Ime@o5<-}+lIsl-@Dl36a)jE{8Vn!iPY5xgmZ;ewE?5^PMdFJ^TQ2_< zYKcb{>R$0m&TR0+hczK=UNqUbTAY^5Nsc7R{!E^Y7pRk*^-N_J`Au3;yu>DWr$B38 z)P?TDnd7lI$p{CIgVqAN{S*d3_qpMpc>{Z0_tl=KU+)X0y+}T=|Bx`@ZGPd9xBD9H z7wsXb47mip2$zYP(kB=kriY~cWlAY#p;-%L(tEl8LAUcFewTVHG%T_%2Rpue+;LNa zhKJJxxpxYk5l0_Z95qPvzfM=}5HAnvY5;l{lFPnB3snPAK zaFvneyPfMyRIRx*a;$R3I|y0zlD!6K&`1-d**$ml$4#EJv6;n83f{b&LjSRcSo71c zz?(Kd7DZ2mW1;%|!|O_+IKrYCDG&!x%Yg1HhT`;1ac$>8@w9@g6}z1Ef~|r0c@t`- z%HePYJeq78B;SL$Oq#CvM^nNyjQhJ9FKk&>2=3?4Dm+ep5-`(v<6&QPrw`_wAREPu zu%CxdYMAx3a^J=K{f{uc9aGerw1r}vA`82$`ujO;EBS2cT_ zcg7UyZpQL=wGIKf@|QZ}?AOqcqPK4#n#v#PJZpH8RZ%Sz#xJBr7azY45FP7`4w|CL zbsF@`-`xUGHxT!17OgZK149YNJ6gAGOXWmu8u}M7Frxtv zUqkMWfTIpHJ)WiPhT3X|(0}|tvD*JXz90a2jpv#@!5z1wiZGj6a|mUe>BDYAhlby` zs`>+`$nm~>uj3~2seau6huhF*uuF&Tx)+?;E_B1<$ zQkZe@C8lK;kwMy9(%x|-NZ=Ye`-fwj(=lZv43>vKuPKltt~mKBR}9}ZrAiJ%BZPys zm-{b=7V0~P^!59|lYGOFZUE*h`a&d+E^eK&WhAAakJK5%Eah=Ax%w^}Kzr&FQ!hw9 z@DRIG8~o31=~YPbaG?_o5CW;e0zwTg$hZg6$%MX2NF-c8-*TH1>Yh6InIY@xOT!7; z(tY)!l9I(z!em!NpvQ9iJT-0i5E*I5O-#a~1cDrfd)2uUWpRy%A=^k58JRss9Tg`D z(5D!~U5pY}mg~iOWuzN4ww@+Nvd1McSkZ<`2?%C&VkK_8r}jtNs*hI3*F~vX>j*Z` zUc)?JAi9xuiDE%bJ7gt^;EOwxVlk|(kmXeW<2Hy%ea*=3yA)!PBmb(^yX&*Pu{^z; zkENeTb3+Cg#a<%}w?H+JUO*EBu)?+qjI6B7N8KI~|v$a)WNx zQk#DK9#o#l^-j$n$EyzvbU1^2jYmAumXizCvnmw@pRp(1FmX`_OiyB(*~Kvx=5m#n z-Z?x@I>S={5BHp$qhs!-g^cg+^E7%F%iM40M=L$PNfS#jugoRS;B7^K{Liva?;C8TjQ8cyZUU zx6I7qk}+-YKRWI@nfC!_4acjT&u49V{Oqr_6pq{fe0ADnm+RhgF4nXXF2nJP!>3Qv zz-nWtK6`;7Q|SC7dipl=I?Eh+!FwAi56r6(ZXOoa3Fu}mp@Sr=KMREJmyRdHH`UkQ ziCX?-P6tQzXPHmujx}3HFko^tQz39G-s%)&mAIC>~|(;yK!69vg8${nDgV zD|i`GYhgR5Uu>9;ame%;+>jGzPK=?3giK&aVx}1UV8gT$}-Q3aAkpBI;CajonKs5QF}X za@auFo2Mq77Dei>`hHWpqVP}`WQVO+yDY_kG>F5Tdu_)&;YCrz#j!q^2~s#M)ZLSb zkxv#E6uVN@`%kfaDl)nd_ zT?Q8*aRHUB$cVaV&@VeT)HQXn{y@*KJ={P|dpPDb;4^p^;n>6hX(!hDyD9L*Y1h!E zFa$$jSc@21tN}&SBsSZXQ;jD*7e;x@0t@4JDB!H z(?-I0^|k9u4Hv?{<-H}Rp$E@C(f`ZXu`k^+TVN$Be%1N&w{7R@Pyra69z-)eR_txx zD&m5N{XxH_IW3Q4YPaARL9$~Q|Na9gcrddska-|mTG#GDR^qT}s%G%Kcm3nY9=L}p zC|{@4X_@u5kaM)JY@f&Yv9~2D*`JkltNtSZfBBJ;}MEf%c-NwEapYX>kcWVuRa>t zZe066l^6cXL`e@Z++Pu>+kbV}IWt?x88eLGFKb+{UB;v#Jg6D(9ombP$bb)h>{w5+M&TF#YpxSm{?`MvG`Cb(2I)#@Q-B}gX_47fB+XIgjHO;9gU9RuV#{j&( zGtoRL-9&9N3(+gL1{*|~OWKOQc#%C-rN12ABSTNQNf--i!DfUH8y*;6@_1F7;zGwl zWe((l#?;zEAJr2LBIjU*c0V(WY~<Dmdef{gZku6|IO8p-1(Dn%|+1(-uRn-kj6#Wo2e z!|u1zZibo{hAMe?Oz)aT7RUA&yUA^D`50kw61tr^l_LOWP=+L`{Sz6rAk#`nz_m{7 zN(${)I#%V-x=YFR=MiYM46ueB9;FnLgAs+4B2{2{y6&uY@w$% zO@$+21^r=>iN?Ln$-@<|*b*x7e1diNwr^A@_Vt$ySGKYu$ZVqg@7>5KA*R$C-zW}(()mrs-?k0s>Kvc6Z;lJ?8f)-zDIGfF_fS?qsw zPg7or*IX9%i5{*0O>$T4H8I^Z@l=``bThDVy1Az+fD`yCe0|Q^^R?6SfBnB+c|GRn zBsDAp6QN7nZ(X9)AQg{`w%!6sRx`@1BQ=M$XvNNum-({;(WeWy*&vjc_hG}M(2(Ip z>YqJa`kR&zMZ@aBWT+gm&OWH#ZRLWp#ng@;v-qC%WYINCORfDuLBFRqt62mh*^)M7 zEKW}fD-uoJT{pqnwR%H6KfVfXch@t0qmVOh)t1QE82|8cny$q$FN7Vi_#rG2y|PPZ z=l?~?-)l{L^ykz)CwH4VXC9X{gE@Yi=zVD_vG&*L&-uG_Y9~FOQ8={|Ub{L;B>{tu z?V=tCSM+<69DHb!_t;T|L=Vq1o|9;q{Bgh8u+NoJb7}@t`BqhYhTfPj=nuU{-S%#+ z>cUn={{oG3gbg?IA_>36G<(s^t?~H-E^l@y8ysU>BTbF0-hy0w7od}TGO?wSMQO+2 z+k>~->+ZDr^m+1ST!zed7tSYXYFRv=45{Vqz<;HMZjRkK?XHC1LttD z>zFE^i+P+P{VO7_7F90H)!g^)oeu3D{f29k5(pbOk@q5`2qL7Lso?bp_)}z`oW9Kc zMA51BKo5cQ$7n>0k-1B*7CujrP<&iW&7y&~je(&ZI&Q(%_3`T+Sc<-`3nLRqRIhB^ z^N`!^jHC8fh2yJ7zkj_6E*CQ}u;ntk-y&D`xa|os>A86Ev0`m`%u2v3jl7ktKevXR zh#cR{AH3S|Ww;YxEtkTWW1e8SLze4fZ-$_bvH@eI#NL{>$)wcYW|#0*<>3FduRIi< zyJ5v)8w)mk7v}=Pb}d#utRQYuJV}bg`mOzb94K*VN|9d;mVVJi7mnGx=x-)CXJ+Uo z^T}1I(w<^NEd;yBgv|_Cfx3tJrP8an$|vi$g$G8i9wpymt|6jL3Fx>(R=yy_aE~3+ zR6da_s_t=iNWaOt`uMn`GSgy+JrE4c=$2|9vBsd799^8#;9yxN$FUPCq9Wqde7OP+KXGZH_v6_5 z17{&k_!nc#tVkES*)4wOr}&Ll&TyKoUR##>_Tolx8$Mw-J5VYrA0}Kez+AVSruP8! zq+E{K=Fg#&d-qvgQ3S4^;mE-F>@i1MMY(~(fzG18V8S_P^`Fn_Es0DxtrZd(7a)2MIN^tyQHnwim*Z8yyul6fWcJrU(G_$Df2JTI+fS;u_x7q1jxM zf7vUWnHdk#e{TF8{6T5;l^6Gl0^59IL=U(chF4q)Wg~afBuI|v%`C(0>seb{?hNqH z4gjw7&ApN~%cKi!@XbeJ(3j|cQ#6L2Z}Z!zA6`vG{7>{Pz7Zd;bKeZlcc}Bs>qr78 zyyb?QboZ!la4Ol}4ITe$^*mBIpK_4U z{UXhISF2uWT{-g0lj4#YaZ!bk`{!On>YZKxS(%>P!&toq`a5|p;v3@?6+RZ`2euFB z`(_W`zPt3QwD&9*Wbv9^uZ9;KAouY5)2gUDgN*p$=b{Pszapycyr?(G(_{YNR#ZTZ z_-dKGc+Ktj%!cI++F!2o<{5L3ugwI`P<&^vYci)+^C8G~WN){V~tcLN}fSLtx;vpee~E&?LWE-RWB{J*%0*w67~_IcCp4PYW_!kNC1ah_!Eot zKh=_M=D!VESZ!V)47=`fSBb5%_qg&HJ*7IB&7l?3;!_HTr$_F_uRf6GJ*WVXx;4Xg zb%;T0$DkFuUUNSmn7+SflnXY7tjsCxZLDn=T7F{a(4K!ep)%6SOF6DqoMe@*5%KvZkDJ6xP zfIN?M%L7NopDe}9&}nQ;9a9`8%#LZ?SVpSSkNR-h`$XBg>^f9CxoqWiaUCF^O*jBA zLH?X>A=~!f$(z=o^l0%>SX}j->CHn*De#)^X>_hq#Vy{M;U{Z^PK%GnNIx-5>gTsP zXPlOzp+t3sZ3TL^Q{PvRTeH;h;SK0r%7aO`tP2@5M-kRnO@Zye02ge_XIOmAt9bs_ z$e-L$J<2Rw+OyE7XW9q<(M72*vQYCFBx?@a*I> z`V+=COw2M?8cuU+jz3j#*fXQY(X;hcfa@`tEYJDK|tQm$V69e zIU`lMA7H|DXhC!99i~&kC-+zj-%cw|=p}~&mDL;PzWc@*8C$=3vu|`{k#7Ja+4q0g zVTA_2t8VO{i(GDK74u|X|C-$52@gk^+S?)Q{Uge}2DUnggZ4nVcr7gSvBd*b%AyK$~fD>u_(#U_z~@?@{gPV*@eL#IHfGaCd-6IETi2% zwsES@F)^eZp$8;~%06eUmNG{k4rw{o=d8^3yHUb{|0KQGArgj=bgg2|Vm9oABddgr z!~UcDV*YO$Oo@{fsG=GMQ*@|tUQFH*FBYCiEW4>Hc{;Gx?z?U(dM_HM{HeQ9mOJss z)r2y92zU*9~}5|ZPPCelvB>NV-)+w>`bTezej2%BcLuwlc@ z0BZWhL+%S;CsYiA2{1o1A{<~5665(JhYwXBy_=gG=rC2wDWIvC^aQ7lK06fruDu}x zB#oI1Js^S+h*$ZiOn64w(qiO;fc}IKbBt5CbxB$~G&%7}6{sa?PZp$p<0TCP=OdVR zfum5&e#mnaVfSDK=G$t8=?hP@2Qz3^x`LHEEdtitTKp>NUhgMdrA;v27)5k`~Q5ur0f4kn9_UFd_7!g z-Y`1*+GK$|6Cl^Vj;gfkf8l3@*nSvIV`9G457=x{$Df`WZ71*1Q%k-9BisTcqewU` zf<~Y9H%Z)p9U_qgsi}B?>_*CrXJWkhU#o~@)j60tC;VM;%%=i_e2N&$r^=D}ZAnf} zNr|WluZ2ZTOdf}D%7PEwk?DQ(YW&))!YRs>na$+@3OpcqYOb0sS;K(HYgk1}E~h;F zF=p4d8sS4 zagdb9``iK4(cWcA{f}NNd$lm`co{eKSU7G{lXPm0UnX&9+XDKQyAG9 zIQ*x6kZ86!_ze=hxcefz%sNj9M1Z+IQz4;-cXl-eo+CQ{9+o-G>%Ljd$JFiMIpRjW z>ayFr;ZA0x^$T!PQMX!&8%eGDPRpP;fqT5@VlM9i&u;8Mkb}zHE;bWHilO~OCxDkq z1DNc|W)#-Rm8NToi_=|P_buX;i4^QC^O^bVpKh|vZ?_rC*-U!?+RFB~Qa5rTncMagX~XoBPx?xqHPWQriDk#_RTH%9h`$Txsb8Gx zf)#=UhMx53CL}aXOTIi-WdJ82IB>K(vcs|pPHj3v5*xmU9=%+hCi|`^bowF}joTf; z2jlrmO6jRhk{J%3@jI{3;lL+5$9QJGQn43%1e%$mF*4(rLvS{ik<27vynuW4dztA9 zC%JwJ0H|yzNI%nF5GL3BS;-lX)v~!lz{Oz$x|N_AclWvO}4|jr))8rmMOlDS1Uo1H17I zrZ&9=Rg-zs8m_M@%NUF$nlBO|JfpwgG`_vzDk5fLcVg;4MpPS+zCKi*lU;ZG@696N zg-m>d9Y4vwh#~@1f}j1t-2HVad7IurpS;RYPT`29GoInxB59Ccl0hxtMB>mu!^PjRuVEiparce~a0Q&hCLV z!Ap6V8%MSw$H*o^UMpU`YH7)c&Fpk$)>SrX&t6AxA3c~92EF`}bc#z#v@-oB0F6;l zO|9I#VmMkO(YG#QxE*=6+$d)Xx%AmNHDWAFW_9sYzW6%VgBKC z1YHG41jsAX^Bv#k<{rDEb#vlUy`E?xTdxNP3=>)14i_&6xpaY;z)OWZfnAFiTcqPW zCi}$i;k-DzSisSw|LAf`%Evi{({#3CId*|%enUKm8UzY?YHE_ zehn=TXam@Z@MS~EVCf4CdI^fd4|IL~^?z-4;iwgszMg|s_(eX98!H2xi)a>xW96{! z=Pzn+L5wkU&T6J)V#(?gr)y*wpm@kih{GKx6QQ`oQs%wbR*kaRL6>U3M(McBR~e*i z#wSNdvrv(rr(WP$TFByvQs&OehTe@F&j5@ns0_@iW)iZ3iC(x#%sqs?WPjHy)CmSTVVLi;S&`9}ua#|)2Q2kHf^LYw&syqI}(UlK`lEv*~OrB1)a zWsY(gn<4bB`WQ{F-g7>~jWuWHWk3hc+Nw>6?s*`ChY=El8?t^sjkD1=dN1qfriVj@MgLliL_*d` zSuY6F&YZCMQv4m753(XDwG`o2ZOcQs4qOC+9@PQH26rJ9uEcFehUEJ2oq8>{IVyI1 zMvXIOAIpp?c={d>lD3yT5u*<^v?e`{RINYXee`SdxDJ%HidWoo*ut`YUWYgPm_*|o zQ$ERPrS2|n!E4C+o5&kTr`KvOWTjz+u^`r-G40U8Un`=HQEyH){w{eWYr}b{snlo% z)XwmNIs)8Yqq&&trhQ_tl#u zjqPj)^5y&H9zPiG!d$+7_Qlz&-eS}xKttF?rPNv9cUql}=HV_trDHeQ@&mDs|y#S3qG(AynhIm&Clh z$ZDw=xlr{+VAJklrQ^ppe4z|zB?S&K&EjTc^2G2!?(i@`!?s_V1URWNMlEqcm5T4* zH}Ty$_0ETFL!Y~Wen2}6ST$R?plrqCb&#siuk;O3vTo>jT+$$lywx6+(U~OoZD+U` z`D&PrHUi~YPr}i^Q`2<+I!jTl3THS9iSt$84raLio-sIJ1{qfunz0Nl9{;0D^bgg9 zYr7L$%o`^A=7lhh@txQiuzb=`y+imP;(v4r$C%o{pZ!TpB;THP86^Mf=JAv#UIKq_ z3)sme%FW@|oA&5vf10D;(L{Q15Z1qQHvbk~(%nB<5bQ(WCq%Tb^f=Tug~;!p98;*J zPSgU5DXvU}Fh3j}{XV}XhFYOkTFE>f6S%X}81H$OML8|AzAACF(ut58MjiOmAoxk0K%skW*ymQV`Y_igrmM;quS1Kn^1gXV zt8FX0)S)(>bkVP)69*MalJH=LV3+WeP=-VNBTc@K?6K#z6YHi)Q0y5joM#0(S;@ID zGbo_taj^eke~G%9e71mmEXf=wja{oi?KF_h5u?pXG3`=tdBSSeaV##a8c$WpK| z_<+`TrJBrAL#GKJTUz)!@W zu11V%TS@>gYc)yQfyOJ#Cjm{4O?yByYvivJCA;Ux7ac zhIAmTRYNS^ZdXcxmsxM$y>Zzo);Yy~z2#+NvI&5^AfSNk2Na>3W9>44kariMxTjsh zTBn_FKrqo$-eb`NtD)?D6q>h-bQyp+`m7E{al8u7z zwjR`#9PFfkYGj|M!oRQ8)bMM$Vzs#LBg1BB6)TuHdaOHNvr}SWSzAxnQO7iT1_JM(21A+I#3M4F!t;Ii^^VgQrK=GORKchK7IFtK~l|b&X zlTQVJ&zHUgaY5=cO!9OUnRKO}%XN6Wi#v??%$~za>;kN1xRhrP@uh>U|d(T*1t5$@je?9%EKyV%z1Kh*GKA zEGQiFlaaJf2_=0U-~{9&OqFT@q7TZTCu$1hoq%pS@N_&Q?Q1_r$>U&9*XcKOEUNTK zm}5uazR~|Befa;W?(u(r;~WXdJ(udjwMe&@cnbylle(WpPf5ARg3cJw8%!GGyN9;U zT~=f3N+(Ln*KIU!aZd|L@>>gZUw8y+|BtTrs1TK)b{$4G!X!Z69RZK=Tho!-`u^1@ zqxRM~mPS|>MEO?e%&ElE$xl!AW#rD-QVSaJ(=sWHtwRc0)iv$g{ZbfUNWS6(%cZA( zSf=qX`7dI=oryqMtd-fBU3%^L>`W+6fN=b=N>(L(1h)E4O#PoXX#zHr(Yr{8bYW$) zqHvGVSpMY+PAI(B-IdV++uiBty0P|W3yo8Pi zmgt`BE393xE3OMXlHA+1HD# zwWaos6Yo=of+=*AZ9Vh4Ot}V)pXz+HUc? zGG}ew{B0rT-)Tdb8*nJ0zl#$%?nC6&X+TlZm$ab#V`P_wRNP{beh+{zc-#7>Xe|_T z{LM{-#ZYa4y#mnwm=cj4@f|9GJH_K|EsWJC_0N#06WmAuVgBuyamP7Ik{9CF2>*PU&0kTp;gh+qu5v5C13b{l5jqFo)zclv5!VP#|UsBpyY z=DUwAte-A9Pv_;B*L|uB)&vc<%l>h@@0Ng+qa-EQ%De}0s+sdgVx!^wS$^m*kgFs<=BZ@tY(0d0CCSIu`FCUVip*wC9AyT3GIEVA;X&8#?60o?=(|CkYkuO z03tl!o3&m+0*>GR(cv~HCF_`#O~><-jH;8K)hB=;ChfZ>w;+mFpG!2SdH>>5e!}iJ z1*}=}QT5SyU$P=?l*^8T0EziBMiE99TS7O}_g(92!poz?PV|MIt+kR??=NqA2h3%5Q+Ivt2t62n;WIyVqI!EG7QO-cHqlfnAnGPv;H+Xo+X*uSIj~G zDW5be#nJ%?<}sOPlj|HwArF{;j|RK3;7fEm@-Jgm2-?RFsg*QAQb5--q=R34vvxiR z;sL|giIxXm5*F5F(&ycoyW+9RCb0qjAaIkEP1x?9LS1PWs+(vpz{Tb%|43gN=4g#q zPUYk;=nCf*n^N>ry147$j=8QDvdqfrn#W9}kEvtU*Z5O&%*30W=~Q1gCrkdEgEs^> zUwU(ttnsez!u=D)U1ekq7=PU{A01oS&P_^`5-wniEBH1ad`F3PhX%c{ZR+3^grCeP z{d*AVs@OQRxX{}-Ts-h#YL2D|2>OTs@L{f>>b&EB+-ba%t&jaf-EW>Qv)Nn@LrqU= zG)$rNqH3MTbBj5Xz93y@ab**CXRz$3yxrM#+P{NK@C@M7v)l)skS~60A0DgoR`-LJsXG&k zshEX6(D1@N95t8GSU-gJn$m+Vrd)D)IJMJ5lv_%vPq)HGuQtvm45V<6G3A}!nwmvn ziz{D)YSA660DpuLahoDYFb}Id4r(w2j0zp}KYG2&(-dd!c3Hb#WcVjx8>@m26BDA} zl-bdM`O8GWt%!08GX9Le%HJGKuY49M$pM8yDEJr={1=AN36025F)9$^U zz53Rn*1a}J?wsHot&vyI;}W*8*EMUfao&Ox)m_Bchj5Ec3BG~{?KWdS^Gj&0zQWr%4A zdyc{d-+eI$en0_Qpl~P3qbc>96bBG}s~az5geL4-wZ-E$km$MIhxGNK$pOQMYURsi#hE54|1hdKD9R1kvU3g5ce%0&w@9xu)qa&^ zd*hm2A3I_RI;Xp)vyrFca|e3D(+r&f6p?O^0J(8*dg|u_4<^H~nwXxtZg=Y80~AC1 zsqWx~-c#Kk1SW%U3}Vf23R1WJ?%9V{H58IN)SXmL>;2QO~rEC}j zfYig9czbYK&!$QFOU9$r+5-YFYi=I+roWckXqpuG zIUrJygI4rrO>FGfz0aALIdLid20N5DX-LU+dE*Mj=J#UQ7V3td#BcY& z59&P$V5`#VG;FYJXarWFo|nCMCDzfi&w`RxU|48e9+3qhA|<8ON?Uy| zvM=6JaY&M!T^4f~@bMnB#%dtB-1|SeM#fz% z5mW(TeY3{L5}LIlnc`XkOgj47)OA|DluYmWi7ig86|Wj_ssVJI|f%`z!KjobQ+O!h#*%WSXhf0(<<{xQi+frvC zoe;<-;}r9NDPhGpIbMe!>e?A((u|TJ_ zk&-$?J)`x}t`T>0$&7F(qT=qi>YxzQvAu7jQmsGnOf$X9%TLZx7bxeFJSX-ye!^lF zs|@1^-#0p;Aawz^EKIDIb8ZycQJS#;Sq8-KP=V1LuTvd2YQK1--sgdirM4-&;6e2i zQ9Yn`+;!B{-v(290;8~PbT-dpy7o9pP5v7hT^U(nH8o@WT{l|{lz}%fGP4tG~u_4elga@!j@>J%M zO|2G_Znhm(Ts+=Jc)K}5WPU3}zr20&N~aAujow0BKSnc~{N3|ELxE!4wl>C)1jFHT zLD|dZUC?+8vm$SWu}nBk$h>MyTKKjISwnC7HTbV8pjEiFEa_*5tiK7Z3UXR4kft zwC~;(=b^`kmH!80?-|ba|HhB%)M{0&QY$q|QPfr=`F5bFQfiOX9xG}N5^}o(_&a?9*SDs{jlDzNxe%-I(rcf@K{b%M6LJ+UV z=j;z=CY2?7mi?W`xxKZM&C)Ks@Y!DR_}L&5jBGLH0)A+BXrt4+kv@~9fK7rXJk75) z0mk;$3M3}I{`n88Mcs>V=Tnkmu3}#=pbP<3J1>=oUaJZQHzL>8S-#RvNzX%J017Gn80e-J0S zVov1#QqtdITr?9Ef@-f7IwoFe5xM@0xi4-84N;&CAi0Q<$0u#aQ|HuS_n z)23ZlPEV4_8MRl)Z_d(MLWM97fwo@h*<}@eucV>* zJo+tA*X}g^5=W~ZS;Qk54@H}Qoj&fs#@@7^v50y19i}FRf7N>w7B2iWyk$K(;5?>Q z7o{eD?>sICM;0FYq=@@rT?mtlxSQTllMi2vD|8>-!|I)*?K8a!sNG$BcC;C`+AkwY z5UlhXFIc<14*g?l66j0|=tMDx)>yv!cIcsWSeBI77Ji%WQ%Mn%+pAfvYn8z}qVLW< z=8b&EvtvDW0yqj?V*K6JR7w#Z83-Ra-OEe` z^hd{1QNpei6KXV=#hG?}Ox1;GyJSQh`p~H8=J`#=N;W5sA;o8QK^gRB0dL)U_K*^U zAuzSTP*EtBvhZ{`T<3CrP>pk%3hKl)*eXKNt_k7CA})pPrQfNo**69(um6_6g-K4|M4Lk`n!&GKn<#5f8qWR}{?u)S^i)ghT|h^YDmvA|w|=afHAJ z`b?Ii!*6FAOg1JUGNJ6h?Zej%1Vk^)jDJ7n&UqN>R}dY|-dBDtWKhS|Bs1AyGCpU| z3GpJ4b6zyt*Jh(kd_R?TOe{>x)?SaWDmr*Du zIp`@1LkS?YMU;2TnX~VAE6zGpeTq2cZTv0%y}AmIWrn*x!;@|$`{wq_?5Nj=KD&l3 ziZtpe;kvAJ{smp{QQq&%nV5^ewq>40)cS0&|pLAB_J}dHj03 zudO*o(67r7huT+F9fUHe_^BG$I|#-HUn#1PUojvS;C*HpL-Q}&RX~RU9hKfO;Cn7^UF^4t!h=LRsi7}K^K#BRrAaO zgeI~gb2)2-O1t2KTL!QCcE+&fF*)-%Yu&=JNK#kM(oL(?18cPj=f?*@)+<6w-0?NdH>3%ER zg|0$aHDJ;OO-vin(DvuA(|PulhBcr#yD1Fzf=7hff?? z5;fx?&d`gr;riUI-vHzv^|-p|Tjv|W{p-Mp66Ge@iL5#tNNoioFpo%|r<4D-rJso{ ze2KkPvWJOYxPee3g|(OiA>&f)stN1JJJkyNszO%{Gg^Pw_zKGZLdX-LAvgzUh{8O> zaBe+r7$JV~=dQzomu%0rc=@a8Iwz5xarkpxXi+2gRKuqw7fVWiBXHU_Sx&-g#{E!C zw28bYvN_M~lSTN0H567$L@4azhlj8L5PqOASLBo&_H5$5n%$D;8q|xAGgU0LQUkeg zmcIdM$3^jRlkvngJ-wpGl*HHI%oRl8FgJfIZ(IO&YxGQ#B0~k{1iVNXe(>KDncim59*lOHOjuGP|f_ejMi*SKmu5(6ob&G{q#9HMcvUSJ=*PVm%?=XT>ckMAIg-g;XJf8b9RvcyNqA0x!lyVQZWnmMP18BF%f(c)HFZ?ItAbGuLg6Ds-nf<%TK&NJIJ2bksPi2h1|9?NK484v{8vT zrl+vP9NAP<>cDh0tu>}E#_`e?=JV}aNpyy$Na2pq-ow%i_K*2$$b!s~|r%%}Q3 zCEbZQaHTyYIQL~bh++k|usecln5nfRJ+kMSJUp@sEJWm;`;*^gD3p5h#bP%@*PgP_ zBa`o`o=yASP<@4LxAzWcaPq2Md9t*@QN_X|!(q% za_7vvthr^^_lH88KPugpXs5Zqfsg{gdrHD@v{RN`({Wrso*`rT$X7V`L-LYJq*!`` z$+W@HrZPiD%J@u{Wno43|M~}yP3V-K`EOMbj`xy{Cc%X>++lapd)4D*D^e#1tm-HF z#(}fRv^Chnwu-FjCy5sH-Q5B38RW4MUWUUu6uZq**H}C?-954J6StjFh#Z+Xjcd%j z?#VQ@?s_p*cxli$8TbCWgjWslG&+zeJIirj?9EN0YwGdz;OudH+v&6So?iTK*={r@ zO~@;`R=w>TjZ?4@87MO+GErDfj=acbOBtZkqsZ3U)!mM^>(bm3vJaJ=ES8sq8|S} zwI11->4~2nyQl>m-qz>86X{C%MQ_${wqT=U*F*#-vdY#XVLYy^yg2v->yq9jvJOEr zQiPZqU-|b?Lh|iZO`hViH$6zA_=fliudUdk>_c08b}Y{DuxHfhUd|ba!4*f;)eASz zECeO(*}BS1W|}S3Ep5 z!C6D=48raN!}gyqNq0KFaz3+KVoU8gO5qbjuJ2k_#qDX*UD5d_h;Sn zbPr};ya}#=KAW>@J7RS5hOvEQyEiNoVSw@Hbe+FFuAIlj6z-|5mAmhrWWn^pyMDN0 z6&((tqev4Q2z*UTXvWz_FPOCIr8c&9z9j$WVuz`O`R~KP$WJ&Dbg8^#H%cB|NC32}&@Dl-Lg_ zyn0^rWen=U&Rfi`PoXdsgShdJj?eJuow4uuf4x!XRw~m~OP8rT$ze;B{^=Jb$DabA zxh2f~>*8iEr)efQItnX_bPAcib*hxRLby%_{?S1? z9TW13sP7XG6mlc<#{|29o%cl|s9TLuPLI3mX-Y>`>Fm?1i+%?Xg(s++*mMejzFu4; zgMfa;0v^*@pRpF*+|`P&sufUq^J;BPeG`Bp7^w6Swa1_ohoN)q^Fu|=N2;;LH{^@< zCr?ue#~s_Uc+L0RrZttup@UB!n71|jr%q3I=`R}t*#Whfon{#Dv2}4~9HVrDbBkuw znLw1cJYx5Xu8+nU=9LL3IdJM)RWuMaw>wmA2s%tRI`QJ^sOskla_=#pq-Qddf!F5) z>fdEV0Ldf*VM3U*UY&)bavm&}WFv`SkI4BVxN;*mI$j_{U9k_)_WxeFLU5TLGJLXx z-kJlFD#~zpHCSg_cn5?S^FUh26l^O>?;2z7pn}yYWD+gs5F- zCh(E%4vigetAyo%GDSxF9VxeM*MAYyzP>g9& zBDttb8YPZONLH;=zt_bjMdm+yhByaY2*oUydZxIQw23o5Z?(pw#egDHo6*&+S(AM7 zwKjA5cI*Y`c{<`>=Y#DVvleZ)e|AU)h>W4-SM;Jup9j)1^-S<#p1aD04#eD-WAR(Z zxJV1eBk!b&(}`-6u;vuYq?q)jHO`N4Ob@BblAp~w^mL4r_jG_rP}H%1r<0<+6MKMc7sP%OJvsD}T!ZJnrgsZw(tKx> zf9~}}g51qsugcw+e39GJkmx$kn+Rw%`O=vW;w3r!#`}qzR#D-N5}zkE1v<)>XeV}- zzJwLsj`h5)onVeK+8C%D6YUWhkI*H~tHGdexd(2!IGJFMb(L z)gGq6k6nuc-lXY>(yM%*fj}~l?ZyKyCn-5V;VUAejfiU@G#=}}sf_F!u$3{6-De3M z{;^1b#tK66aR@*V5)8@uW75JWdB$ciZT>w>_p%dThe2&R;m3pK^GbufSuZ9&aTLrH0ldwhXYpG z@-;F}M^f(tZE_a8(`y2jMPQ7LPUFDG{cv>N^MWe?3#QzA_Bts3kT60{IKwdK{9rdp z@NdBojin+%H+&?d@DYW?N~?7~&dM5{tJ`G>k22ZMwy!5Bw7qyi>{!lxh)D;{^wSO$JRR;`|c?XX#36(L) zR(piULJb1 z;ccYs&dl`zbAOy*2;mUQl25oQfd2}2<@2eZKy=K>fL;(n?;C(y4RPzy zvrETW5H}a`GYIv7L%mz7oY)-kev2h;r~-K%AX(Wo-=Qdyy#X#l7nqq(=FdS*f}}4j zL*v<6T}Y18JN|Rb?Ml|prpUw-fAr}oE|@=CL=`=_en#M2orCw{0)Ub;bKSM zt0f+)D^=nG4cW_*FNUh|f921X*)QQJ2 z%T;E8yykS#WDr%2i7KNQk+NwlSLLSUidCA#T1&ovqFbHm=eI;3rTdB^oG!((^)n9^KMF)35>|6^J=t!5=~osdbp!D zt$#5hPb^PjTY<{==Rg|eyvyj?e1qJ&q(d#Fekg;Bt@=3wle{z48(M)X7yATQBC?9^ z;x}2zasljA^^{_LO(M;H_rsS%d4S}k|Noohln+2`)v=(^1*W`((B?Y{ey2N?shD<9 zDM}4;LlsmE{~x7`KD1IPF=*TI=$dn)@eH?IEck@Bqx_qGXSaJQ>8OYtxrBLF^C8z7 zbBSzhF?WOe{8_25>8mUjnSXTtA@QH(Pv-EDFyjdbquk(yZd|2&eyCecv{o*0t3pf0 z;v|tZGD37rr+g*iSI(GauWJ=JjoKvXgNcN2;T-1lHyDGm;ZBc!&$^aeyY~6M=aVlH z4iH)>4C+mp{Uc6xWXe21dkA-WFGN;cHc7-p&l1^w`UbzdP_UY_i$UjpSW5TEOiaw(eR@`APqiy0sb zkdi_|FF6GHb^jIL&wmc{l`U;cN(k?^8+=~vWXw$-t~-+;UgpF?oN$b@Ew@#(yqeOB z**_i}m3`+PdKeRbSvrlf%SzEe_vmMcrShA;D%pU39}s9vO6*?V`D(tMG~^D5x2LPfJfGDW7@&5tj8cP-jO0HG#ALP8 z7@nN5!&SQU5i%o`M}YO~%z7JvSLa2Qh*n&>cW?qCdG@FKxmw*X{MYCSxFm_^)4Up6 zljkL3e+F1YFs0UR4>e0e9Z|er{^(ygeb>ko2sjd{Q;R5iXM&Vxb>wjTw&a3Uj6r#l zUQ>Ck-+LWaW$lv00{8f`u#D2Z9nR&O=Z27fpp~gHC|6W;1;vmQoY9;vS{2bZ{%f*A z)6?C_9`p&obqkOlntOtLYteQ?ZSPXRqNynj}b+95<9O0ST+%1J!Or9^on&XZt0&v6X%{|XGs z;Y>nIkIAK(n7Ody~q&0t0=C^*`3RGiCSvATf}t z$W9a;!j76NkL7{0{Nk3nENj-9|Kw7^&-2ss7mWwRzy>3p5{FqEo;pi$LnRO=>Z?t@ z3$Sz*Lw7qD{>V2pQScE&Kzs_({jM1ws*Z$y7%54h6}&-Y847=!us8f8DUvuX7k;F@ z*By#lVBgQDu)mmd$2s#}=&O@0Cfn)V1rqvDGH*=wS}Cy6Uf)s?sxRa`3Hw~_B7j@U zA-&hZT%=n~t0)_n)IfC7F>UZ-lH2JPV|?TuHXF&+V{v3l9?P@rzH=rq5h=pCct6hf zKHRgdnMf0Mnz82mBT2tiwd6wa3cis~=pYXEp=>mrE{f*QNOzdXxV^BSeELP6d}t62 zdH#>i=GCLcAx<5(+VpMx%TMMZ_b0|i*UjyZg`cy%$ki)FJs{b^WDEBw=WLx5qeAS-_4Ml>6*T))ZM#5nHX~jB)m>p>m)IzTrN%-2YZvx`?|AQQ$J@b zL=ZTe`CWex7=b^F^1FPJocm1 zWqsJ}e{>=+S8aFG{?Vzb`cEhV{LfmP0+6PoLybq~zo$*`u}n1jpUJ^z+Q1wYK~$)I z^uiWVqs~csR%4l|RTqhb*BrT#>z1HX7XT8cT(IQo3?a2`rlH}bD@R|Q`@=FWXXygzH8|nqfe(Q%slPzBC`Z1WV zz6q$cYL3(YfL)BD9%EDEl={cuoz8S>KK6Sf>WtGB#0jxyia^q#^>r1yk#wU2)f%s# z%BCkXNfcw6_*Sn~HL$NkgJMYHV)@Fxf-1CAbCh4N$i4;NtG8(*G3aBHg`muUT-pTC zH0!-@gwVG`*eJ|(;|MdSn-!6UagJA2x*Ax_E;{$DHQe0bo^Dz@@*0LXQ#qakk(Ypw zSAhnb({_$=nFrO}^K-xS!_PzCl$Z_lRr1Jy&fA(-7T+9t$rXzwOEbPjc|naS+j;p_ zA;suVf9~Ee;-w4?LSq8`w}VMALPmavUJQt#3Ukw$%c>Wq%gCR6Kk<^Sf$Yjl#k*b3DcPKpP?@B6X?X+%ki9U;(Oo%tM&I`-@ht}8s1}-+gkyDo# z>~RdXqYt$nDK#s#tUN=9K^AjR461fZ=!IQ#36+lbnc%Ya+4uS?y0xe&IBrw&=Fwv^BkA$lQ4+Be-RaKsGPNDYxLoU; zvd3WoA8^}y%sRmBC$|LxX`i0a7}W6?PI7)1V!P*GpqgRDfDhAoa;gR?zXfy=p+MZ;Da`@&43(if zaQuM#n;LPstretY^;OT(pv0x;g`;ixMj}eOy(e9&MKsT>ZfZu@P^6m>J@Ljg6 zOjJ^n9>GRWO$gUr5E!);_5nzqZv%>NgoX zh$*(x>70I=V(#%yYyaZg3u`X~d)v3%?sY9yHxB*JW&RKYfMoR8=4%LbDn^(@%^sAi z{%L8ZbjLE7yrNl?BnXj7evQgN&ZMqRIocU=93r0Expd}DoBXUg^(@>wd{gze!23}X z#BhCqECOkhipo4c+z4G_;xN_4Z%cJ5GN&^N8??WUEtmP^`T0$oyvXWn@qGqXfO?V+oJ82WpcE(9Zx&j+&al zM__?$byOdoJgpeWFlLl`c`Jnqx<(_`kTq}%ZZFV`Npxjaq3I?b%j8ewoL@Zm*g+koO% z8F?9V3s1ySb^e?s9bG4@FQGzF6-P1nUGDxj@^RK$^7Q4k9&&$IAr0>?pT&hVMIL{i znDra?2lNbu4>vmz#&5<&xD8&Vq^jJLU^J>qyGcW6@^+h3pwz~LZO8qiIr1f6{Gh8=WPMW^DQz~MjGG+hYsK)IpVt8%w%X5GJmrTKpyhqNaF$6CGrwBrYY_+Jf zdjpPYSCkzpbUj{X^+*bUNv<=SvD!-YrN^iww7t^}t~S$Q)VWdqrjVHLyEeM3E%UnG`QPM1O$Yz8`LJ^%kN_)(pL;m?#5VmYNaofO0l+FH#|fL|pr}A_3Ljt0)q6 zkY2zSl+4|%Wv5Q#aauESG>k2q*DQ}Bb65RR4w|HNkzRqAAZ`#&_ys(Ai$qlLj5JR3 z$Ppg*)vFNVmr!E4A0Os<;jVwRj?I6Y(58x+_G_A#KF?fgbYXD<^p2puTB3B*azY;e z^l)uLXlYAsea3d$)hLv30p6laN7ydZ^ovo8%FI4S*A2oYCk-R#yt+D#JJrA8uTflW zjX)TXhF>iD9$Ax=3V3tAC`Pj*SjpwYV|@}+ce?~U_0u`8yHq_Xle^P^*+%4KLZ-{-B{cO0AEkiCrd0THL8I=xC@_INgXU2YHIrxkCN`4he8l9Y0RI(mZ_WYo_g! zI#y@P{kU8`()p{{i5Y;8dUnJ{%>oSn#ZAfi#A2i1!12A2ks(7|iXbe1_p40ro%r=v z-8_*&9#2|S4Sz^n0};&`4Hp}g{ohwMP;XeEKluMX8CNcms8;f+&E+Rx)~JgKQ?V$~ z=_d*+zqn6!vgk~J4vMI^8=?TM`%dJ^A=d8>W?~i)%+R$T$Z&8-7An^t2HGZmpH$T-Y4D_&zP_oykEG zP~28=l`%&Q^|js!4g~QPq_RrD#bCJ2$wbz>k;dQ`*PVz$LCtHazx*#qKBDJ^$$z;2 zR{YfS{H_*g$aIJx&2|&{(m+ycy)#e*^w_9JOL?U6gI2&nOuM2N~ZI7rcRlYhw4Xbm?JHATvvM*+?a7NADfWH`--TeNfFlFUvz#zR_65o%a+S$hYV;~x*b=flFPg8aYTLLw!|G# zoSLs|R)=cGXkYT0ImkzJ^A;awFb&u$2J{m0G=vzq6rX!n-w-=Lpx18@A^lVI2Wwa- z>_}@Wxe8P{=x|@5$JzuQdT>v$DyWKjjwWW&H7yUf33;T646LGy87j{QlkKJ%~01 z9mmn2w{{B3CZ-?fZr}__glNiZDgw~VN7EhcPUZPjQ?tSBvwd$8;MgaA;C|Fqd1|-* zx&M2JyXR?n&P_jk=uvwDFEgRt?q9s!kVf;2OuIh8!5W-3Z>4-yEA?zaSwZX_ zx)W1@YVqW;P{Twc=yRazcl2APa}ZK5^dGM)YXy>LbKVh3o8VmBP;BPlpwLTQu@P`FAB=_R6D z3bZU(ht3?s$y$q#Fyz#=jpaZ8=t>?&QYfG!g=;5QA^2BhP*nst*0pls3WD`bF5lR@ zqqkyN9ZKZQUk<8C7Y~+MAn*CEMav{uJUEs}OQNwWhV|U85sHtL`$so^-+SWg%N}A( z77y?ySe4qRYZg0<!cEYUgNt z&)<#%+OcQw(yY!eU#(6iX6+g^`Ano3@rN(xh@xXm`*2DeyNnX zFT_hgThxu--zhczrB0oe9BcinZ2StzHY%u}?`>BnfARt%kQGz9UE~pLFV^>9S%i;! z1QpG@VBmtr$MHv~{sh0D$dF`f(=v;h{&^11`+#Q!ryNK&)HO`J-JDk*$zb#Sz|M&4 zuIKgj(tmXKPxA63hqZq*6})loR{41dsqZum&hRp> z#KHSzrG!vdxkQQchqj`7Mxb{EGwt<;*X6E}8Ax8YFLRZAO_MX?5=1esdnla1Pq{uc zismTI2suQKH|`!9GR#dO=f2YuJz|#tb&^Iwcc@RupSsg3JMhi6en*3{-lW#)$Gnqv zz~3t8Vx=t896kF>gQE! z%`&RHa=iFxWXX2QUyg>3oSff~WcT3vI#pb7 z7K7ry*De@w;BoC^?n~{;j`-iycwlk-m;GSUtt|Q8)OX7%yXQp3uu8c^2@ds&(Q(7N z&Zb5$4{-i#^GRAy1&!^(x+OU_CC()1d_nt}zyNjm^2fj9Ld+{tE0)lW9Z+ItQ5-Ys z_4=Ig1EA30eoBP0ZNcJIr6XUgCX_9e4_L!*we39KniQF?&}+BgLj?i88WYRp-K%eE zKlA}vy}@^RPD}WEZPtl1I*fIb3G2~X&0H=XGudymM;ggw#gJE9YlS}v+UxV}c(V8F zurFE^Q44$*z~l}71y1&%fZD~a^8m1;L>}w&j-oUIEFpW?c`%G6AesfJuaFE0*VdL- zuUGjb=2UrlfR%)}wx ze{`9p%TuD&OGO}7ov(T;k&+|)1I7|xT$it7Hk?41*vwWlZL?V z0k~tR*B%UXXZ;$5m@v3Ve&wYOczjpzZtE_+Yk|O6$;cr+u`jE8+4T>Ep2pYCG&TBP zIdjOn@AInXPE3YZtT}BSh!zYsd>!+i)zzI`0-Sz!$d2eIRnZpSpXd1h>kEz-qX1xP zWxyk&OY~K@^TW;jR7|p~qVh8dSq*hsNUn8lf7V20FD;RFHL?Hv8(62CjltJ#*dD57 z&DSQ~%;*9|C>x$TYm?sAUbrsjr++=J(?PG5r^zZvx108J!it_LLRmSiYDS)(B1Tp8 z+f~98jpIm{9=sf9*S6G&vdAtTMo8Iw?-7ptaz1&e%9ovbwf*Go{p?FTcO??`;3coh z*{#gN*$+hkC-6%s;5a8*JOTpkMqAwf(HY=DClA%=kh)}6f@Tboi(ItOg}mOR?3d55 zeg7MKqCyvW*|1f!dq8{wDN7rJur^E2%?gcTBMxA-b`kC(T8=e8KV#9$$U^u}%{$|fYtnvB=4Z7-2v9rdwkxF|Wj8w>M& zMOe9dKdb6fj7-H>wi;0tPP?ODq|-I02#WHT&FXfb0CWR8#0Zp!XUsg~7}SE;_2t{- zd_5aW9%f&7=P%+HqtljvyaGD$kQ!u6(x^cZ)B;y_<#}JYNJeu4GRxNnA>4z%YD5oX#&nmfKd}c`9g+=qJS-^^oUCLtQiw3Eg=OfKJ-AH$C0mnWh#W@t@4} zpETQr^a7jL?_`%VTVx*%{9Bbbm;kxulF8%FH+boQ>+3nmTLkI8g02bc#xj_wgq(c* z+Op>M;n@?40`)ssTD=q@@tc3d$Lhvhi2+IAW`7})Sd&RAu)NX3G+4P0Wib9=#=?F& zMy$kAlqU#wdDr4>*=)AgI?-!}5AN_6w%eS=pVwm@?16Y;mw%`*8lMP=Co@ zHhWB4vyK9pfZo!(`hA|oZ^t;UMD-^>Pi7T{;C~YiF$tY7rs zA#crmk;nmxy0ThVZs7*gimaJMf8~$o$$U9Sg*&R}noaRPBD7ZOR^^O@YJQt+uocd8 zKn9ifsax@eroV-TI?Wj z?DjTia)EJo6`3h638DAb{{uOoTEX%bjNC^*h?U22_SGg*ce8s@9+Lb|-ZU_W%1ZJ= zxuL2i2Zv>F!;X~BqE7yj2N!8+mie96NDk)D zT+{vV8fG^5$ALasaZZZ4*F9D{Y2PU5ad5)EBZj2Xjk|N=&CV%j0RF8dqG z%G%}X7fry>xp)nRp0lwq#!3Egk8{>ID_n zBW5p3eUOl(DFT+Y^pOXJwzd0}o3P&RrU#q%kk9Ob!;Li&p7wWQGaBHf0b6=^JILN7 zkt24p+q^J236J9=JI*{K-6!huaF>3+<;jDz=)Nd+OFzEdPhrXH1O_AEIxth6D7!$)c-8vI2rX`YVfP^+l=lj7EewkVV!qa)05u38kJx9wXCFJHfnX;!$_WS>JQk_$*H@`T~Cf`9F#rBf^hvw_@K9 z=AJF1cc52AYd&e~G~9EQo+=4(|Ge6y`70DUrL!ak&G;S1vc18vqyJWY6 zc+`NOF0)ua!NlRp{o@az=PA}08uOV??bzX*@R{z<>vaMI`|F?8n(?a*o|oYZ1gDmM z2s`BpsSEA3Mou*yowZaNaCtLgYrM}Lxvw9e(KP1ceMVQ1--SIS}oC-wZ{Io>tOx^ z-j>~~S8xYyeoRcD5}ZQfp|uICNPbc=LYoAQqsY3Ka>qzqYpKt=-wyUEf7eQXmVaWh z%dz$3jR&Cq_I#hjha<*M7M_;apmI^VD@Bv=SsLG<70Fj(_Vj!75fjhStncHj!{CbV=&=c9#kMyAmFj&D5b!KU;j} z(;TiCMX?|r>&@(BlP=n&y4s26+v`8phv)9Lov_{)k$V@%wa;MNmPRQ}o^`qObhx$)k_N zxZw&+uIAY*+VFJ#_7jp(v(QGG92gYO&F!u{-Z%e5tlbmV@Ou97^2#K2cwJYV1u-zM~@eem4WYC#IJ z0M$;aT&aeVD`lFxNvMu>BM8%hhWvi&HVS}gbn2%}43YkJ;4#cNl_q*Ev!guEK>pn4W{v`nzr&2M%Iq=>EL^v9BFq zFKxJ7`5LtIQO|hL82HY<0Cbp^RNS>jQR0HpgPIO;Mr&PlmhrpNk8*X{K2-d&&dRyg zZPgbnCiOd~62gA3Scu96Jj^Y)P&JtJmN58g5ZI_O*E%ZA4E`9}gl0a_TIp$hNFQQA zyXC1q?FDf~ITe17Toehvp2(OdI+n`Ilr}b1mI~uZ{0xmpC=}eIU7UuU1F?d3G!zbV{7oo6j z9=#xE0A{fHF{)B|lBM{L^2DQK{loy9KT>7oeSLNe3PPV^2w$RM z2d>h%ifHEP%ftXAs!ft@=Uqx^3!b*EieL`!hP_wYG`_?7#1E-=$9Am9P{5)@07xPQ z9}|Y+z_->>Oukfuoqg@m%JezMjo;LtvdgVp9*OrG>Od{X&+J{a5l98#1UG!fM^-dK z@|Cup+&D1hu+JdLb6qh1G)iz#)*MVTq|4sjyN zZk(d|eM4b)2~=qr6BJN6bxjq09q#nLsB8?-FRuKQHu9P83M|VXS>VJu=uLXIBe`oy z6JcQX^=6rgZ?CG$N8}pT$HnU=!}Zs%mxMV#bP}IQqX6x2XgqQV!iaKOh%vu~A$Hvz zbwfPK(G2#^2`-oerw6Rc^zt3wKjU;4#|@Y7E!|eAmiutBp#JFF%m0Q?@n?d)5}2)n z2}L)d_%*9fVoR$RdOvudOwn`9|%mEEIxjHObuv%aNb-*O=n@xT>e_Z1V5t&0+G{=RRqSfdDlkx+}d=o__Nr zI~3@N(ImxI$W#rUDYE&Rt7!HD)XFt2ug3ej%bKNSyYEW(^{w9hOK9irL@8M>$*~-^%Kx67}Pbz3&E@! zVe|tCjwaKGX=x5EHHxy9KlYkkPq+d>DE+nXWBF#wUT+*>Jn>7Cxp~-*tI%zo zH#IjcEoUwNt4J27m|`~^ak)P@e2j(&_kEkoRovK2asu$`bY5VvCW>)3$N5(`=M@>) zN{9d*AToGy;j4ajFSXM0}^L||&=j(F_vBC%b!H1=#SLa2WE_~ez)z>Tn#7Dow zr6xUF94Ai>TCppTElVFkBBb{8FzWkh*5Kvuif;yhfZC@u^=<^=^L3eKv5BiLX&SlW z&Rz1&Igu;IE%~KYf8rYKE+3ao*Q#2XiirPp-xf7rPaPSjIQ*RIQXap7&9-#C zZ`P8+_JbFWVU1+7vny~E9u)JMv=Gr~SPbLv^K9m}dTv8!Q*#k((A)q!^_C$?mWfDa zUbPYUnp~FZz3luN&sCH!>$eXc5Aik2a%il0t?9rvUj8+>!v<|mGf6Rt`Sdj>1C7l! zPaBplNYzFzA&rzZgB$$1Ztq(5UyEH?(VF7ces%UiPH}{EOuWml?`^objNZ5E!C zbUbZqkl%0L``h}df_kmTL0**PEay@AVb<&NB;$(TCV5q0fAaR3xHE`v>8B?P?6f&X zIHLnK^^5I+9mOV6eqU{Z!qVPWXXZu|fk&U4fL%mj3dEsfJfhvG$vPv|OP2TV_6M6! zn0PNsPpX?&6couL2Tsoxv26j(m&kme3;*cctl%NW1g)q0p_T!kmx{f*H?3z@7n0BF zK-v^Txeh{kK!hNx*4x7Bt!i-mC($#deVKQ#k7r}1irUG!xL+E9e(a>mb-QorF;1{J zk-BG(RC@dcS&apM)_=?>&rI&8VxrR&DNrtvkG8h42jIWeOYLw3vGu>ikGWPpNQ1FF+_Iz~;OQUH|Lz3+AT_PHO1$ zfyr^X18zovj(K154IF|SdZwYyb7<^*zBWtvmZlC5QwKD10>VrK!7(ii`I(ZAhGzOU#}-yU(f0r7USJz~Wf@GJwdGwz zVGaE4xh?j`AWXpK?aJXK*o z{8LUlWfFtx*9rcG4gB&-=$Kf`zF`D&wo((&xo#p|o;a^L+X(HJ|y(r6v|2#(BCt^O?Lu%yd@m=|}VG zPmZe4reE43iozb~^9yF!)$>o{w9&B;qOCxaGk`^=J9zn?j8)BN>%0&j=K05PTa}y% z6S+C_=fN)-5AiHr^RxjuC*})37;*2v@=GzA9+*wmpJJF)Sp7zkGrkCh*B<*R`0;x~ zWG)r}1@wSBUvakO@DULft#fl3!v`p?grxopW z#)1fsGl%0Urfqx|9zibOu{_ozY;V0@EizAC`EZOyBGr9F0xLm!ZSrB z=UXa=!@rb@J4$&KM|h1HR7bx^4R|ozKokvYWEQ)71bt`|5o-5pd2P%kaI5!Jq5Y;_ z$f-w3A;vD~GcRYMLL1P_CP8ZEGPaJDgxO9(L#;wdR}Ixi7cTXVC!At%E4GvA`R?%3 zWBajnjx(#^tH^{EGw>kYu{XWCRI}W|sfM#eyfhQB%dh&Sb-$j)HaG0Gm$<>>a{)Wa z*!4v!x3?jP0D18a&kVZ7ggp8=B1y)sP+cb;>}Jr|$H+$Vn&I?hs#o=W^39S^kTtn- zX-5|Ch5dyP538`&Er&MsihcmZN#pnj33_uY4h}=0ci26>y^-+m;}|%UEaoX1O@wb#z9pg9aQBgn>-|8? zf)TkE&wiF%g11U&)g`Xq0}Bv)iz9V#-g$iz(=%_6{R*rZQ#)SS?J%8gU3i|bjjruB zg8~$7k=m%hJ6JdFx^=u2N=)xgwdw@n=zaS^1l?i)_d*fVeE*!Kdf zXP~U1O!N!&1Z1oYrZ2^~v*N@%E*SP}qmk!&TQm4eVQJM$3Uv(GyJ^8ibG+rtDdey0%2F(AiK*BdnSg#$!tRtm!FUQ=k zu3Dw0gV~^O^|n~WXZyG)yThux_~2L)V2VYF5F1kvHxy$K`o*tiDuuuvXV89K3afz# zMDYct0#7-WNL`X!2ZZN6Ie;mJs!BZB6cVtnGYbh4&)V=JACr4;`PkPJq45Y=ybrf0 zXvTqOyebGj$i467=#h7JGx#(3O*&vYDK6f$(e0?6l6R@i50h5rot-F*WObcjs0R4g zST+oC8wtv#+SwuJQ3b5L4kB$22nSB5C{pMRly|5Fj zAL}gE=$Rqg_Ur9TOs2(d1o)`5#J69CF9Yu&?jJWowl;bf9`qD(wcS{HT z=|eCxt)K$w>ctIVn%NkIR@lzU{U{e$m^V~YFGBa_tz{F`Um}!YdMDpe<3`OrB9H{I_d-{?hz0IM4V3HeybyY zG1$!Rp8knl@|gvYBM>e9;SAHgJ8kPe6c&RKc`WEVfXTOO$lw)YukXl@y<7@`40zj3~=j zhR96L+Zigo)LFlrEnnw0-W(E=HkfLBLohu&}f1vsTgV5=TZX`*vu_<+$WaZ>_AOKQ_R@VoP)&JGpT)=^DlUV?Rb_fB+ zrkDyOA3G)yB;ukW|F%)fF(1XX>);XqGJ1M%c!?^ z;>>6B3o2>bDAewb&v03x{pmOS4y66Y?IIEAtDI-uOo4BN+J>TvU{M6KoTvM;2Z_`J zwdoJEzst<98P*V=KQcEvzco3u*Dq{g@$54^1f5zvXXtkPE1=Yw2lB4!;+1L#DGKQF z(}AwP*pf9=&)$r~?4t}o@bB^QX1%Ty+c6koX{x-`hQIQCuiO^sN0Me_fc zVxee350NPjobO&dX{=dctEV_sZ3JxEB#$urS{J~HY!DAe4~XIVGstaWkZ~Rr(|I5-IC_(}w8&idvEBOFC&0UB4b|xx!IWI332YkD4>{NCKD{@b~ z^9Q@${e4+n$H>tuQcX>}@P}3Y$wf9vat}d@E@YiAV~b?-yllc5Ah;*yBxbeyk6~K{ zNw^%vS$(7;U;%uSZ^M8Pr^jCOY8G_o44N_pHQU^j#p*o&|9B5Dl6dGWfk^xWLIXG# z-p==d4!7aQ*in_=swp9+<35Ux6HnTj<1Q!wo-_;Zbd9@m=gJ@5{lXKtPot8u#f>`FoBbJdDJNwnKy za25~md*>a@_<7D3HsdrHld&$uMpJ+R?mIDw;TPIVP~_KBJBcbN-W6|3d0fc+!q%6K z@j9rJ)&BWB=_u|RG5BSUTSBXBRVcitG22V0ymXdUu(-V`=*U1S!h~h}uJ}#25lnLr zL%tF9GDz&*?fg?g(_hD(#)72k$UVhv?VoGD#H|@>X*x4v25$}NzB)oB$yX^<7AZeA zB7x7#3vg-d9Yt6Ky9FzB*9sTqW!!cSe89B9MCJ6v;h@|Ix26`!0cc#5h#q6<pTjl$Wt!|HvqA%TjJ`p=*E;C{%*OsfqfQ zMJ}>~33U5lvG!i~##f<^YY#sE9xGk<-afG!hSVPcv!m-G8+~B$bp1%|0$-9bDI_^? zIVi&StHH=BuD8_J`OJ=@co(7s6l5y9<2qG=BD|H1e0&`L=!%O)z*uc6Tvp)n*dwON z9QK`J%EM6GJL9cN%cxi3sToDTYr@nT8Vc+#eRR&da_<2RiBhe@G@^Gxgx}}n!8q&1 z3RH0|XQa7rUNq(}jFR!(6#x>TK!lPWR8qz)l*HL>24{DX%lK}8E$L^vgI&p+q~s;5 zkMKnxEZPu{y66xJh*>Y!-@JQoQl7sTKOUTd&zkA&)xVfW>V*#NJz$F8iqaH$|>*|H@uD(`siS|HY~aq@5_sgAT}N*ljn(6_a_5=Vxz8Oi1S(1*Ng*% zie6Y6Uh-o9v0T$@#q?r?%W&4wrg?+kXJ?V})Z@X(*^-`oziGmrK++4}E?VDPZAt2x z!~+A2`y%T4{8q>Yf#yDfH;5W3)pq#VyDP^vqp)@ycY(TLpZcSa*hpyX*?alz4X&|s zk;@@8e2oD1h|NqJxad;&TA8~qvbkCtTTk=p(HdHR)v6z%08pmNby%Jo&0#KSsm9vE zb#abXTLmQ)cEqU+ygBSFx<{)zCa4^9;n!BUcWHST%(1PlMX*aO;&Ph#Yp~@A%+yr3cpRUz1NUoT)HgJZ#3qbkNJj>d0&g57OmF0Jg=WpZfxm#2I`s{Ubb z0~bg!-Sv{0udHy+(R(TBwIg`H&oOJ){D~Vb!S+K@FvJ?^`WZYz(Q?o5VjPCWSGJXERS=9Zl68G2oTE^O=+eEWa4rk}%VsD8xy zI#iQloZK9{$pnL4FZ*a{$lwfx_$%)vIT_v_m0TJz>-hE@hZGmgqj)$_i;e#5uEhBtIir0*hlE_LN9mZ6<~BHaY6 z|LWm>uF)UXcKAvJfcFO&J{RqzvsxM4tuS3#GkB+Z=VnhpRAStFrn zGZRt0W{h9UPy6rT*mxYmq$w?=^?dxOAa);{C}>E_eHE*cF}}XA5(b_AZB!ni&25G^ z!IHkmIRE(!!mG}@4Zai;O5BGZ|BMpRdcE@I@}H#m_vr2)c+zolmbH`1&4zIhsB>%R zjcxdn)ir{asbFf3oBknV+a!*^T{D)Gu2ZPF{^H>P!B36lSMM*OvthM(+#^)&p?iJ0 zp*BU&5-QXk&t6i-_DfSDZ$Yzx%|Tn-jJl;kG8Hz?p278&ivd#L?AUUoP!&sMjAvxT z#7Ii(G~3~5^j6~DKL%TOQ8NO~G%Fok)1V+nnxurJGt$hhR}_9lmGtS*TjLH z*Nw?LOOLFesXq5pJ#8U;9*ss(W1r+qFYHZMp*Wr@_RF{rKh`yGE_|4wj~`OWVtg$3e?_l)kfe4Ewyfl-F2!}aD_lIpceXi^<&jQ|6 zQKrv87Wp|Zy(*Yqg*0w`{a2pO2KJ3WTjCZz*DZOk;pt{!PNjO1O1%9ZW4jijeoD?o z;;+8kRV9R3i2dveHgpzYw&RT&CyEFI>4xSY%@YDg)Vu`FL^jdOQ zv`Oo8o~vWIWLUL9EqVoQkp2p{G&~A^9TD;Y8!fKa^AIl&zBU`bBGU;!aW0ZL1u^n$ z<&?hGcbJuS9@1jA$l&^^9;;$l#i1I*$A0%~+x9t`WSJgAUh`-1-E`HlI?b%<2+NjW z&~@G6vBwt(KFqCG`@CMzMl)&RFAAl{AC=VL&GXD^1$C@G*j?to`z2`AGnb6g_f?2_ z+R1TBcD$|W(dVp+rGRJ_ zZcJcj34402)@8rl?o5T$qf&V@nWCje-8d374*$?!o{n@`E9)nu$UdEQ9uG*4UHjG+ zYg(~tAu`4{9y)R_WuWVcKPF<8VUkEDbajgRd45;=&0TkB2KNi-2voUBa*Ok|wpHd_ zbY*q7C0E~#h-paV_PLRq))O$CsVnr@w-j14hyc{YL{WVH{HI!yS%(%ZVXxw&(rx*j zZv)r#`m}HV847y_`wHC-bE20o9mRt{ixYSxjnxKoWAGq0uJp&$h+|F@1vO)Jc)RKO zZS{^3R+)kVhwRhpw8PJp<^qRc8j3Lv7L7Z#f6TNEM|Fo(rqVHK5uJsEF`@$#DSaa zLySL+BwDtD1;~#8TC6#HCxn}O8}aTFj?=%eR)(8_O=;9>(j{zfx=b&}QgiFk!|1d% zK!i7jW~bg+^k^VP&*ehX^_vU``?NTVT8mw}A{7G96+n~kRPJ)PcBBRKyoyxA{&D5J zHpu_TB4?D^+3xY;4K817FyENq^Kz*vUxXau6Txx)7?s7BfxVb1kxc?<_%-cPIi1s4 ziay=9(^U@G{W^)V4R(;XhRD_%ylZdI{$o&hsEY1gWXiSr20M$pty6MT6UP{WU0M6; zLT)2s!qN%Lw6yH@sk>YB9?1;C(x2|@*3^rQMTv?e^!NT%wR|G(=ac=jE`v{>@A`eM z-UJD#ocGD4s4vq}CUt|mXVWE*cxR}pEYdywlwWZm9PholqLf@%VgYA!z3tmp%@W)B z?j_~SAE#OvYbzg2McpJTcGh_E&~FfTGE?(Q`qqlZl(RB^o#x4b%61o1tpZ&HU4@}W zo`Yy88N0;J@mN1>8Fj9&R5#?(+sOA~R}0w>8!hs+@t;sPpQo=c@1%T5&b)j~N=see zwJ`hXm$7(h7yfrn2yz^p`~$2Ws)t*AScg1iqxbsDzLOP-^I(KXI>B0eLiiFh7tqR* zu^(UcUZ4KQATs~wZzY=D$)&todDBp_w?RjpSQ7>Ap2m<@9&blEL7#^5!D?C0=y+vudg9sV(V z_^YX=mL*E|HCiM>d&+!!^+LIbOmpaZVIdU#e2Z|x(~#1k>i!Txsao54g))hdzQJ(; zztwXi)C1r4%x&a(`Wa*gaG7}Cbh0Mf65%G(a;=7k7ksX@!c&YiMN*hQq>BWJcCYg5 z9^12dX6)*f0NaWkeG1qUT`Sqk3SHJKFYBtfS>!i&H-P!=QHL6$?ROMm3DE^mHSPYT z(w-5}ZG!kVtWL7)LSWxaXuH(deffg)$ZztPDp^X#`=|fIj57Uy=`t5Mtd{EcypisZ zvwBGh*4dMwCrmB)}6ZYa3*%1r~Sj7fb z)Gl@$DvxN+(r`|-W9<`mFas?>P`!)wBRkRrOfsm>rMjD)|F@sJO?E8z_?QZL{~jDJ z@-|-afWv;oCiPQ-EU2(Ro7Mz$Y499|*8n^fx9tFoQ}^0NNC#8e<&M+ROh(7X^b2jI z#@l3j0t7_v>!}v@uH^7AOy(9vpd_;x2-UYOxZS+iBWA7eX->lHn^BPLMRhIL|BVY-{*`vHSl-xApSeQuM&>J_P0T~QA1uz?j`_!9_ zSRK!xTD-i#gKu&4sm`L&`x|l*`T|Dz-y>x|lSX==$(Sp3#w?Im1yYmsG<7{!?$St| z^rHLoP)N_LWC64?3MC}!MD48Dv-BCPvWXZ1} z^!*uU3&HD7JNI{Pv6(A$=$k!)Ud-C(Ew-=FN?v<@wW_a^4klH#m9dz9f+4`9% zcd8!^wUP&P!(PeKsd%W9qRFU{;ONzNY_(yvQ}|)4T`sqyT_o2&o5Ex|EzhAXRVa3P zgkHC^IY5K|6|Z1Fuz~R%^u^cjv3X(y=u++{#d($|d5xFx^m}ag9;Boz2z**jJVqaO zl7y4+kYuQ2{737$Emp1J@k?pPw_Z)wX!Ml}!}$<;HDfp8X}NE!dx1WrQ_<}ws_S#u zovfOO(vH%3#L}67mm0h9<0I7g$&l4MRHktRBUp-?9 zKek}mdXl>qMvJ&d4Y0wHN+(;pu8<1xl|bcjy?uC3ytq6%UcjA#lkh?gY+;qN8U zI{E~z+L{O$$K7Rk?z>a4X5nEw><)Tc`}AxS;CQ<*=1RHcb$aZGP(^A143@({W0HKz zXWbj*5ap2W{;KtToPkZ-*8~!oSJn6o_ z88_HxM)12O6fLSAK-DCGGj8_1EA|WzmmZW1`djh3m-6;WtUvoG$f%oafgifNOiv+< zMLGpOqna(3=gU8Kddf{nSaM$pnDEThp%B^_LM^TUsUx5|7*IHki#YVA6@a-sPxO04 z{1jU7w2*#?+eFGQTWfs6LuW)}=iuVi{$tdDo#J*TsqZkHtVjt!=#t|}{9{ze#}RNX zceI%0cx$k-NyxrPKvqWY`unBNTx^G`#%8NN@eA5yX}}^uNA+aeaFqj%sjAe^har}qMXXnA zrS^HFo?zMm3@M1M1vvWKecS1a%m}T;T3TZ)VY;%uU%m=`H(7kN-dgh-Bt7nA^fB01A%8{x##qdnxsZ)baT%+DJS95twFnweiMF@IVW47J~vt80wwd)|7YObDOWxl z?uEj&GhE>KnrcsSB}I?wM4mu;l_K;>oSWI)StOvxN9w~h4bxSC(nwm&DSyF7D{R+n zwItey&YHERPXCMqi#O$$T=4R35larsZ4y0ZCNaN;*h8EtkO!+ zG*QvNL*bR3c9qmu?{{RB5~%|M#bLl81Z};EB*w-)qMN&HIj*XdS0>)iJ;jLmsT&HR za@n^orbe+h&%RKMQ8_@H9VS)N>%-s49<88y5znl;M$>_Ygg^il`fNGKPexq|MVX8T zj<9dSmuC;tdlvyH`0(a@_tTpEih<-)Xb>FwkW~uPzUD@sU>< z#W*MH>m;+bvpCCXL-EE=nboasq>CXgBbTUW$z~;FvtF(FlK34jgi^`xfRQ3{;+Eyx zfsj(d^&UZ^EzVsXC%34-$K{Vjb;}_C30rD2{~dLnbaVT*v&Wv3-Xmpmxk#kV$qAI} zuAgX26?+>}mgLzEw>XK?KhlpUHRzk1(B0HOZ$0=Kb#E>J_o0S#rlIFmtSOTpOxjcn z6kuHv5h?tM(sg?N`;LA*;!**4()M;O_T#9kEugy#T>4M`-voe{j?+;RYa@OqsXhD+*pAKIQM0JgkT%=8m%x&v5&~PEL=`f zHrB;t4O?G*IiJ8HR;$J!9?n+(j&eO})CL4pRBW``Iz9X5UHVkB9`lvGsY`M}kLjC+ zrrF;=)jbP8q<*eS>I@O2YXjOnsY^H3_kht%mZ!sMd zn)1V>!%{oQKL#D#G3!uCfZzm{_qt#&`K@|KxQF%76*$`w7cbBWrPNz=;aYO|-??xp zft>bu*5wAZc33ukV|c&YusqoQAA_2U&i)&>N9@~Ty9fg`@c}Hk`u#lhRt;G;QZa`6 zmgV2>h5LTt@3?Q4pzxIXLu@B-m@XrGk#XVK-9GGg^)2p~biP%_6w^SsotpS#=%+nVHv!VPNt~y6!yo77VnIC+^0;<*+ja< zr{m(EktnqaDjn#0^CFKdSNE}CUVtx>eG#^$y{~n^=DQMahc4x=q+G78<2<&+c2v&> zQG-ZEiZ4OD2)+;?5Y{H?S&i{?idfnUX@LZ;$1F>++K&y7;S^<5jQQpYv1hcq+Cxg( zfA-T}^=}0G;hutcXOW62R(o+~@9@J!yBZm&rbV;5j3aCQBG2nQ-_7uCO4UqOxJCJ1 z+P7|J)x$n(dy8yF+MifzO!$*NHfQW5n4R`RiQ!vcmR;1<#v@&XE`&u1i3{?*TwV{3 znC;h&ivN6&$bWefrh`3&(-X-_ZY88 z{Ux3Rgm__SQm11Cgma_e z>xDxuQMOT%bNt{BE>#{`HVa8w3)Y(t`uu!U++@Z4S%2s+!SP45MjZ*DP#9p^6>`S! zd8ZaM{_c2fF9neX?fJoYx~P{Ehh&{R0&F))Z_s7G!^y3~nY`nl=@Z6#V0<#~eiP${ zC8HXAKU-RNf9~%>JMo>4Uj~dTYILzt@&%9){E8dN{@4B*!SY+yf_75rlOT`_2WN6& z(6ftp%)O;l&Tc;mu(i#j`V6lEVW*T-?(DjEe^(r?n!q}0LTkHRg3j;B>F#{K+uc#P z@EqCpy?PjQ1=*qZcQL+^Uo#4H=Y&!lx2SMjL5)@dTyU}VYd%>2Y zbU33P4V*np}I~v0h_1^mz z>yMmF<=^%9yloZDe=3Kb|HHF+H8hYCRkFetPnp+C6~$+xGL~Uo>|BUPx%VR-AuNv# zBgKnMMLnEiT!`zR#xlrOYg{E%t^)d&0gS_%dUkS+c%lSPnrus3(lv{_b{k$RyW5Fz z?GKG~^3WPD_3|oR)@seMra0ZDeWjlXtv*CdK|F3M+rAkM)agM!`EhoqZSCBEEAyn(!;~KxIO7Ie@V*b* zGdCV)@!@`P9XCj_%5aq!{s~r#ZvVhv^tGX9;pYWrt;R3a{V+BF^61gU0Z(dOUwk`b zX!){CD3~?C3S|Ppv8&HcOBY}7yM8h4!`V20bw&G%aO~7dvx$y{R&Cz)_}FFXeY6RE z8dN`xrhwr#l3k$qD1NXuIUk?S8kfc?s4JKflOA+ygb!yca$9v71Smkgs}mgr z$(SN42k>SIN|2OL4`_XqC??3s~!&)c&)_TWe!0? zwaq%WMyD4u(=rVASQ$7E6ZWl}qljvs!rg?YNJl$D09>&k>z7))FEU55Z-Oo@EAiE{ zyu#=Hc;yz8{5@UCyQQfbemQjFn`Wuaqgt>#lq{_d=wArXi$Eg;@;kix0xmS4aBorP zh_hKygTk~D;D)T4^TT=68kKZ!SHxIk9#2G#m z*=iV5*SMp*44J9DH|8bKb>yH(LL~`X*F|y<3QfHIakfZ?@A-gKr?gz(s*ndBBst3ib@+0 zw7tCKoW*xV$MmhpSo0ZBF|Xmlr-I*k_cU$bu6kun+StUDX|RM{wjOWa^tW`lGDxI_P0c7CE1OjDBhuQPPL5!|V(IB)1L8``r>s$UVHh zHlkvN)+}IR4bA2>7?VJ3i1s^HPK-CBUn~+IRnIIE6j9IG`8TG4Y!t!lXikQZSUPV|b;z-wx+kj8 z+J+6w*G?5Z5I0!RymE;m=wIS1$t1+FoNC9^=zp{m5yp;Nuxn!<6`Jjk@|0Ml$|q7c zyaUA$RuqRQY)<2LJ$IVlQzHGKH>+_&tTFpxOP7a}p!cP)^a_85UFbj_n-;bvY7i;- z9`LfUZD4rh>bgF5lnn)NJg$4`Axe>}yf9ETw<}{rZBv4I=v3a7PgONN3U2foG_O`L z>jAX=pxKP?i(em)2O1BlwwmDcox=#GiBH*QwvV`O7?GcOUwzdJb}S+5!8eexn9Fsr zL>PPPO_F5SeS#@T{!Pf2qW2dZIf7CSkId4@RuYO*rSadpxFkueDl7PKLFM#+4C@O` zd&yrtuOqHcRo9WT)@+^5wA%)XIP+B_Uvd<<7_ooTIA9N9d05rg!&*KRYGYVA&Z#u_ zGn!Fl>>3~A)eE%~0OMgQHEO=mtF(=jwkTVF*kGV=Y5DDG{YtB}sdg8J09&cY?-uV2 zdbl?1+uKWBo-O>blltm?4c&qWq5`>!$vMS4UqeCWXuW#Jl+Qq3!H$@ZbOB?~YNJ)R z+qe7pG*m_Z{tV$tPH)|9EQZlJxOU8TB=F$A$t`N9A=Je)W>yTDWli*2XsY-|V#w7b^-+qTHyrA3*jp#;l)sMV1^QhT~k{-Lj z?Gy0ACxZX8STDUvvyY@WN>C&y?uaa5W)34|^`{B;Rp+Xgt)LekLHxE|7fux!N5}Zu zuJ(i;bz^Xt?+~^pqpFLXWPjQp*cEI25YMqQ9DCkn9f`CtqlO^U47B<^^nx7N@X=S4 z?0o$Z$bhVObdLm!{o}(=Hd8+duJ_JX>uHinndvLT#%_Y@v%72|NgKo)&@ZhSb{;+D zrZw*yZR7Y{06Wm4w`};kHeMOCtZ|RXH5LDy+MuiLKYey@uIM&ids5u7mS>^veIB?K z0{9|I2JPJDv zpjCN7)B2f;fxP3ZDh7dtJ4;7%rjR97@*cl~5$iEMeq-+1JdXYiop!~Fz_hgt^NZ?% z)LX>>U0Rny%lohkY}q|vDa;pRArbnd{LW6aQW$kH?d_f{&+R;EK{u6C`+!~wD2i}U zB4Y@ZZg_o^kLiahct+j9K(f?!DPS{YzP4-;!5};0&Nu^c%jKD*gQ+SLj|kf-A$Tu- z5hacN!R#7f5+bt&z~*`wuKZUn74jeU|575r?LS1oiB~tWj_IZ9osN&+h~sw>wc_IT zmm2BGS56)OW1w6M)yA`@wrl;?lI*fK3`}`^ueNQr;n#9w%7rxaWFTQ<16FN=?D<8N zB+3GB-`77dzB(iq^}#nx`X=_lLBp+uz~{M7wW$TZS4l0&lg3Z=0|+Cyll30DAPwEB zx#W}FegkDeqMjs&L>nbqH1Er0X)>g(m@uJOo8H@>}%Slt~NK34l#{9d0X<}uvD8*@Re1OgV9KEw$ora=cq6SYYVDXTy z5tbP;O83o(hg?YdweI1Hqh4P)-57Bj?u<8Q z_p4c47izb_f$K@)sx{@zw7X=BPa6jScu=G(8eB=LCL0DG4}eZw50_4n9~=roT7uebf=G72^vS|L=_(kb*SrD=HV@s_zl#Y*N1K!?3k!XhZCd)vS8~CbuPY6G_ZG8Q zh|hv%$0k&zQZBchA{Z!^!{C!EaegjLbIWAmc-S;D;MRFVNwJj)cfbR|Bgs2*L0 zFa!tURcRW`J?-tSm0wsN)i{LAJu;x*isw}&hE-JBgXR|4&DMT;A`?*Xe+;TQGX`f{ zPNw@(&cG?M)Ter4Zh9HVi3h&^?J|;!e)C|v#BckscgL(0IfT(@J8x*;V{CmcvTjHM z6(W>#X3k-qp*LD+_FQ`p;H)$R#_vAvEF62c&&AH<#@FYI)b?*x3kaWQZxL6TwA#F| z;Y7v37rf9aTQE+!s7urka(2m9xH25)UH@6j^l`)7og|UW`-&5VPE1uyIsq#nP`j)L zh)2hd=aq^)U!c6!&tX~FQ2&d`ud}pQWU0?=iB(ab#w2KOMGx9=gl_AvQQ26FaS0g7Va72 zjl8(VebPO?8~Io_-0kgupT7U^ucCyI9X^8Wap;Sq4J@8VMT%9kLF<1(`N*3K9N#9N zA*?4%E7wzlnDE~ZLp853)3Wh-J)pz)>2Eb%L+POudIQ2RP)9PV5# z;Y!w&j$u{y=v2FPRTfrYfLfV(z{uX2Pf>tXcVo!XdX0o?ZudjA6U%JB%8}CEP1ec^ z%fs=R1hDrFjK@f+MAD`Z8Sb^|@?|BM#pE9~s#7|eX+i@Up~+nf=NZGdkAU#=b)dnFK4 zs2DHIMAYwU))70x#jaKQMFh80?E+&aGxn_cPk})u+Uqiz!Wt9~%=9tMZ3DD(xpWYvSC$K*A=i)-&BG{o&}15$30`LsQ|91*zZ+*KC`T!@%@2i4GycNwCam z*lD^3eH1K73Q39*COg`@_8GUnwVV5pD0Qh+ThArvqAyUpTIqBD}%y0cAXQ)m)EuE zR~SweFiGUz;_TrZy4J%hw|nRLIYW5|N>$X)#X7fm4oy{`cpIFqn1^y*@S~r6Vw5JO za{ow~N!wrXDs^rdf?dTRJM?C*3rZF97#>v6>?2W9Kh7QF_^1*=q zR>*ewAsjSw_;b~XwliE3(i~5b=1)9A*1Zh=aP|w>3HFWvK`ENiw3lq4G*~BQx9~L-$DwxcJDNh#o}jd6Y)YSR${!q3a?(cq)~NR%jPk+1IisDsZR zaU!}875k6j9Gx8@N^BnUqTc#e*--jllBxQUC745h~!2 z-R%HrHWAPpul50U)-0O={XQyMwIchtg?qHg?|C~9-sdkW@9I!BZ&yGks()Q0nRSBI zYGnml=4^SV`ozAz_B&=iVRSgRu<88vS)j&MX1XoD`dDD{7~lukNDL;nF>}mRqw`D8^mk<}a?52>*E)HEqU4EX# zzA%5hh7-r>3*zM)%FW2SJAK`5em;t26p*xgRxR1K7j_DvUc89g!daq8vQhbE*25BU zcxlB-Wwl^c+7s-bH6EJ~$SV@0`>AelUWYD&@8YEfWakaPHe-J!RByXQ?V27QGXfJT z!qj_I?^X|?zxtL?@@UXB02zK%zDi4{LU|c#=YDyKxq&tq(4(MXj1JOiiwtp5L`AVp z0`(7f`o1H%bQHN(LdG%Kp8N(eg+q`K1ZQDSs!_s~g8CCs+%E%HL3S&}9E^6lL#YHR zXINrm?Q;HMf#;6}sTq3Ooe#d!zmX&wX0z@59~0YMg^`7C*0!5EmdYm!%pp#pOng z`%^5D3Qk8KH9s`fCJHDCSo1z~G??VQ$h*XVQ5bZZ&lg1cfA+J_^#+UuV~+{6!o1!BRo#)90|l=gk_YnLNs-i}BQ?z3H6$*ZFr2hx z0=T8nhmjN92Yv0b>@GrCZ(ls>QTQt6#JM=qvc-K&YAq!eZX;{+sy|T`#0n>Dsa=paOkJeo}b= z{)jUV{M5^vkp}x&m$Q}x?uP_YACTMdi-}QJ09cbgPtILtiWen86SgatZSBDi_l*Ut z&##E>-G9QZIqxvwLJT-8rxpEUaIa>g29oDLc`O3U$YrL2AGWi7e9CrRaLp!}SO=52 zEP?r&k)N_OrEa%oOX!=YHE$C!ZHG!mH+LJU(7wXh%2z$6d6s!YbEPB>iYfUrVAckl zhV;6$-*i4wZ{B|Yji}uVLY0X|hLo1p-;<3k>^5Ylo<;T`WGeC;U6PJH;+%t4JSNv) zb7owz*SaV8V)m!KMQ0j^UD62&pgf== zXlSs&#*tx|OYv`<1&ty(3?5UF^$WtxKV*0k2`>iTiR4hx2jq7YC_7o-fuXQblN) ztv*XAVG|*AY7~zO&NLq`-91s?rEL3LZU1V9uM@53T)RHmjF{Uk%t|W(pC7@$Tg^5j zC0n+OG~Zx<=YW4aC+oc)+;eA!E}`<-MdfQ|Epvk&|@#8?d%`O z$J156To}>xHmO8A+8p*cO|AJI#mKW;9hVXp|1_uy&RJO;hvpp785flE>t)fD{4INY zNGw7#0iPw5><;3k!blGJg`tfPESia}*n=cQ|HbsC)SGjce%Ew&Rk0#n$pSIu%o?p; z8upaZ$Rp%Shz{N}4e=&-!io&~h$fo&Bw*=UWR3;FX>rauvho%Md@YJt=X~JEM9UnI zTy_AY+GlUX8KVWM!f%a?`h&zVS$cZ>?){<%Jx(z(U%=P!zC^Nf5uL0iDQPBCq766> z`!+qI)qL+Ip1$|u65Derob>c((ic1?%}>>CYtldb0Q8}wSpUr-5;!JX#;V5JUDQqI zko9q;K|%W84*WyHv4>3T>a^^;W1xgJ=3fc3&3I7VoHx=1lPtw6jb!nB&-oqDM|sGS zLJn`!N|ByW;18XGElYMGUt)zJ#J^N*zuRZ|;Ji}h~WDL4W zriPwwU8FPXFZ;~GEJmsK7kICC5VeiI#2M$BfUU2&z7(oj3(|H8(zjb?n`3)JY)VuO z(45Tf8WrUK6q!Nc@r1EeAzhIS1H`h9KQz7_dzZ(iu$?4P`LTd`+^xC9lLbBv*@8&f z{lV#?!lbg2wwd~y5B+C7p)E|JP1SwuI2^4CvQ)Bo8mKGyQ5S!o<;Tyjb90&_YqGyX z9qQLrY1rfIbB$JQVnnwkor9$R>Q76kT)p<&arfou?d1I{R)*KD z?{%%(&qtbghoT5fJ5Cf4`e*?wQE}&Pr3Vlh26&glKEjPly*_3c+%*sh^P1}utTEyI znsvA7a!P9sjc=?A+a==_F{}kK&hx657?~|C;PkcOJH_^a%uQ%BN z?bwuL6c=#A&ic9Ja^Up(80V(-GaGes=rcd6h+mpXyhAd|;&*uSrrXNjwo`MjF=UA? zNo|@$s+y;3l&Z}fb1j{JN~?o-c{vfd%P%yOJ&2)6tfFGuO_Hrf|c zK4b2HHd^mg^qp>4OZl4DsCpa(JnZ}^vk4$->uwMFg19=GCy-_u8aM>LB;ir{%V(hL zmk)#U7lFskglkF(`|f%mJlF#0sv5y1*y_aab#E-L@$#ddWl|wiAa=)2!f~+(V|E1GZ8`b zAc#)1s1rTv=)FX5QD#Q3GsGCCB}O)JDfQ zOv8|XIYyqxa(r5wKzxA#M=Re%as`=@ z;*>$iQZnz*+lZiYxWK`&1|p;|G5S2o<}fOYCVMpNEkXuiYaa3pwiIbN19NHe(G@{Q zCU5T058eGZhBTY+4#jy?4|TC>{`_i3I}`5zi=8|t0XGKs)Dl|THFb=WEa{eGJPE$l z<1#pdTO06x8V&VC&5NMPq2IBJ!SAYSA&I?We5;A)JE$PK z@Kt)4Jt7KHH{K5hIht+t>2bG;ec#cy>N{h1ZIyRwH&`rpHy9}SsH*i9MjuS>f%b6U z{e8N+5QI#`tmL}}kunQ<9YQz_D3fk}8>Hj>5Hgk1*JgG96FJ|ul67c!LWIqF;|QU? zU+&t(5o98U4M5|IJuWq!!)^pJHj&ej#A*Uw~rk7sPxsqtFy3>WS?%2VNV;{Ny^k3xN6o#4&3 zFyv9}x{m*$OS1VfuJ!SwfdT2W$Y;bUxdb`YjAK|nEu`>u_))o870fFvsK$Y~SW0mU7RyG%F44t+!y{Ai+8x?+Vqnz-YPs`Ww`KM|~5 zj`w`A0w?`;?(I}h&EdH-Te<_2Nzh|BFL`Wa73X~H3c6433AAg-#a`)G(u=yAG1osa zzG*4b?Z)uDwvUl?tcMb*z+3SHZpLLLHdl%!(YJIOdn{M@9#1GgYi0tuoEmT$(aM%J1CSh0MJl1l31SbxjaRdvU9%|R?aWy|KyhE)}N7Kf*^ zRm>9~YenA2sXSiV8W(;uIi-Z>@02vV#sQ7{byblaYJu7aEpO+h`)r9T%6SedV|`BN zOQ@2tTwE+E4=R99>#FM4!9=9UblGys;HtSkgI7XUQ@m^hgO0n;l3>8lqYkGs`4i7u zXZDX`5V016hI8nl-NQkb$PDR4NmDQ1Wf~@2JG5VtU?uZpYK!1a%E(J(&eqxfZV76M z)StU)EOHG4F;REzZX{}+zycCR&4#$A=!}L54bsyX}vPKiD;)C?CupLKqO zYTR@hpw0hsP>adO)*ii-r9*k4M z#P!Fti;rLSZ_vALzTkM4yuACM7>%=Rv5O6Kr`&)SiMC$>B97hLb@XB;Bj!zYr_L#I z)d}swf%Le9`=syWTjbGZ%C0>+P9g&~q^}m{3~gW;R^5u&8_{@=QG9xy>^>qrwPOJ7 zhSbO=9B`pBj~M;W^w~AL;Wt`!%g5ji0V~hH9ehVtBS6wPE>)XeP0Owq1LQDSx`jsE z%ghdW(5+S#%wG5Ajf(rs$Fi*kD{+H8IbPSZ5E_Fvkn!<@D1xBB^O{3=FeUmZG9%NO zoi6HL>MTy<&B}`sHyx#0Yf`=kbr%z(m61%g!K-WFg>k?g%_VFZgxvaYns9sPcb05# zc2=@_?xWoYdOzWLxyXbAEK6jSvaI|EqQRm|L*L>PS2=sqc(JdMr&faFl|+01CJonz zxAqSH9Z^j=*t);X^n_6(P=G#d3O9(aL{X7>AwUdm8dnc0hWI^uoLchfcM06V} zk1dICU9SbwC1q*(SB(E)7cF%zOQYHDv8gE>J?o2cy#+ly+$Hat4=?1PQ1)VcNsc};rgCx?OBW{FX&sTT@RiYsr;i|bTU=@sUYbEinx!$o$!|H8kcdff~%A3%9yA{YGqaL2XNX zD(v_KqNu*|BQ2dU&P3i5hlBZpvw_C&A9w+5B(gZP(7(>PftweD3H=`Q8ue~bD`Zg* z)sM7lBLLainyOsH08;jTJ2jrS`wZdQ>@3&TI{nFJfY}y&_&D{?;UhLQwJtQ1bx{sH zvU{>ss(1$Gcvr6YF`DB42nZWgx>UwA;S0FFP7b(jxcDh+1=5Pkh3 z<vyuzv>-wUm8SMU=zjUY{$=*{@(qClA0!lHf<^4VU;fK*5C8+wW;`Ku3mG ziT_siO+Fu~98fjOAgSVe36Fz?XN~HdmmdqYs+TM;6&2Na5D5z(ScO&gPTws&`9~pr zMCjgh^}=~iwhI#V@cF25cK_ISse!gX&#$xg!1+!zBwKxNCS*2^2Imvhh`f{JoBoSa zoy}J5Irqd$%q_>21X39s8|{_ts_U+)01dbv)gCE_+5|~T5NE593@q?wz5wYMkazCZ zcKiI$30{L@2ggK!-8})e;&=g?fii27;%iT&Bt{s`4?Ni-A3roU{)}d5>o`xWPH-Yt zB?0KX-SF4RYdxh`0}PtR+un~-YkMy(4H|a1*tfZef|T_b@0`DTejiiCZF3eMHX zsMz^jL4j#^KiV#ZfwB-o2!B8}TVzX0gx=w$VfyXLLO#EaD6QFPvPLZsrPGTzjdc7} ztG>4x4p9F;!mj?`qO8C-5o^C_Sup}#(|iGOrA~Z+qw?+e2@~E3qppRGXu}3|HiNsD zpQ(U)=FBR;J2uud02spwWy-yW=Hc(@mch@i6;{bo zC41Ov*Hee@x@2}fjZ<|3?vCJ|al0UN1i`YjCJ-$f01VVz@+g5%s@yyl4JpQDdZNxu(`%ye$JmC|By44O_i{g&Mv>;FO+GbA&TYsr%C-z0(92A8oq$>Po zvDsE)42862NDvwJaMl>j4|Pit(PqU(mH5PBEx7x>cwBwW$U%ZQ>kufd0V1$7Ss&lA z0E99@$lW$;qwPgl4kYd03!weNMc}oB!FqoC6yKKvy@zj%{O7+geHa*6ChZb8UoW3j z>)0fRW*Mt%&g9a;T=ZfPbjoyvMCGX|-5Ht6%i0@Ls;iD$qqb)>mc)`-Rd(k_46ofqxNjSG-le%~ZQWFl<&;a%tO4 zR8Hr+KTNG5PVDdYHyLe@MwcX^F3f7zL#XT`d3?12)I;~dOf$+mTd8ZQC#q`ksUsb( zTwCgOVGv@P-=Btqm33R#wJ2IyvkT0k9JB^vUiDw?3{0Q&aaA8Xu~I;Li%7fM9dDQz zNKf%bLq7kbU~T6oTI39Ep;Qs7zb-tR&8eO^Rf~RGq31Qy&$_i-7FE6R_oe=Y18}ro zZb&I6<*_2tKtvH;H)a9CBr6824#|{T^)#kry`p$Ds;S|wgNhMcjI^x?f83XR`cg z(s1LE2{I(agBSw(^uIUKuQb0eh3UC`V2ZeLdWWK;FzeFjeG0*|oo9OP&nQ+g#c-BL zqHdw{)Kbi^ze~Tw%^2SE-5vlr5O1;)opG5x0Q&A8o=bn2O2?>)TD`So=Im=$S-Vr| z()p(L9(km*(6D}>lJ_C6{LPkJW?1KAgd_M8c{-Qf8~z!5E5D_2vf{6Zt4h)ZUxc-? z9}7df5!W1RV!$8gwdRp&k~`_!p=dEF_ph^#&`k^V5P!GC2*Ar}4Z=`}%!~6Md!?Rx zK+gHSWSi}{k-b#ujUm}VDnU(05?f7b7hMm8kYCLsnSf)+e zJKX16|0|TsH{ANH-Ex7bOBYLK#@nrdt`J=Sl8IIv{j}{@a`$h`c{bY|g+hYKx5R?> z&GVEf!ZL1dCAX(>`dn!br-|>hMuwR8%>AB!a=}%YHW%pM8n1(|Ea1pdr*=bXf&<&% z(>e8#B1W{;?6I46+gG%w@6QFA-=M zppzZQYlBIDo%wqX9GZsI^nZuWmYXg}(u|=6s^MS5&gj~Hy#3?I;l{Pfrkb*uBZr5< zi8@oo7`h1WrJzbfeRuH{^YkZ@ylX!>mNx#(pF8i=IC`Rm2LHap13m`w)0Bc`>1aGh zp?FLsd5m55Ag^)O8}a#!x$)gz+@z+D^J+nO2OAT~e(qF-N`RvP4|STXr54E>5X`$J z-CtFTEU$=7Wu=^K*KM$AYneOWK-VeO2D%esP8{|v_!0A)#BpJuXoO*z=!(}ZBg!niDL^>jHhdcsqen#F?uQJ`V--{<;ZHSQ76ODlVcqbSHV-TPzNWrG}dAc_lxji>ZK zU0|){I}m|R)%%kJKkr}+i=d__kiqiT+asO{m9Kmlm(8)l{zo{eX=Ou#0A2w1{*{!Ev4ph6^=6XQ2kkIyf(6Jm4o)XLU^iRgM@V2(9qTBx{ zwCbB06W(MnEVoE;-$0gcd#FCpC@4|#t`vOr^=Mf&lE#y-DLH#eJEXtg7g8;8;EX(A zhf(~+@ew1a{%dd6B&Sz}%s(Y>24*>Zr5Oi`xJhQA1y_N=KnR%HUrPaj=~ z-oKS!uig$8!UitR^~6aJ;}HBPp+-qX_Xo`58xUvW4WOhI@&T~>o0bs+uwQe;at|c@ z?sT+{a7y!%MfcSd#x~&} zM}j%VFs!ENGV>(iBTJVA`*@GAa{b3y^-zuL2?QzsTs=}%J>8=5iD|ftT|*K_&=bm0 zRa+~)G3d61$^3z6?E^;*EqFBg7Js}GW_m|N_!XMYIJM%ih zBKNn@2Ri*^!MRGGmK`y^+G-u!#3wq^bW)n)N-37Dff;{~;$gM+Em#O(4)0!#`MoE( z@ER|4Fl^4mul+>+x=nTDm8p!=>J=gVT>4?zS8e0=s1ySH#Qs%{CXLK{BFP<}V+~{| z;8+^))mYRpS|hR4%yiL0+gZG%WR$J9r(tXJ&5#^%jbfqd2u-;^he}|BP5?=_?TYxo z<7+=LogZ&z^7u-1Qn}fXx#MC@iiyTWG2TKm#Ru$$VW&woutX8w4Ns4pW4%L%{NNX) zGC=mhK6n3juvd_myEny~FH3bzv?o4ru{1KZIzjA*8maP!v|`_cHNV=~X1jneCQ@CwceqlWP;4@ELP;0BVem7ZXX+QToC+K=_#H@bI!yF~ZT*Vq!{OGcLGA!Ft+Ys)AV zFMxl2;*oBtZ28o3w=#bVQk$@!2DHXF;cKg$xVdHz>gldHSG^5#7|&hTSntvTTDqc= znz+2IA_*qsQK&F}2kjnd#g8Gwovp2rLL+GpMmW34qAj_CwoBeS>c=PCx(@Z;uVCacal{yk$Y_3 znVarwzkEo-D@E+*?I=X8f}8x%b|5b{xZC0hNly;ny;eRR1)*$p#tc7ii61)YRnlF_ zzH@TfK;V}_W|qW=rYs6loz|rn4XM@aoWLaXrv7fr5|Vo z)KiR*Xf-4V!8)}KI~!qF9PqhzWx=xj^TY)=#$ep@RiCp*bFce}wNi=1ht*b_YFWPv zG+tpJAViua%XJSET2)!_dR@8Iu>H*plUQXn@qFYFP5!UumiYN(w)C?B1DW%oBR=3{ zlCcgL(LSbdw*6Ex+%m?`gstjnRt*SHt6omH=`H!hONC&4j%R^!9)` z_WJNr8JoXfW1UcUUv7on?t}!kiV3abqo#VqfT{eBkg9EkH>mz>-w*gH&MYCkU5v;v zmxpQWmAIkBymDyb&wyHf-7J)HH5Sgn*myU>*v@*?KkXyJ2DF%fqU=k!K{O%N68(z( zle#-5srE%H1_JJo!oSH8g-UuY?+Xu$ccu9Gj^I#ojz>$i6T9B#0Wl(zIPTVpp38`4hm?z%0;> z21oa?P;AK}fef-xY-Atgn$PMDB2^M=uukRGdPn;#^K;`Q1_2=f2U|22?!f5BoH(ed zZJBkpKaSBD$A#e43WDWB4G%h@Q>7zuzjT8HF8U~^KCqC!h-^Q2V&krOR^h1jSor>s z#b|@hokRz>gT9KcimATcKqZ(`Q}&&4!#TaQ!sUnFuK>^ZuULb-wu1siUPvgjrR(TT z{|&{2VmfSR;yAEc9SoG_H)QQ6hPssx-5>xx)!H@D*9W!D-T~B_aeZ4%Vw(r!%>DxV`7oxMNl6SGW;$vcgX08)=aLGS5u~! zJSVA6I!j<$rI#?r4H2t^{R)2;yrMY`6(aovJGe*WD7FHnSt5PD7nGmHc;ij)(y~J$)N+WR}`;$lS_f+8HwXEbGs@niFVP*J8duimWw7w!(SHDc#roa5bJz%!V z!khYF#$V>*oF^UXu@#1$_gm$gzs9+Xvh_?{k$c6-St@oG@#h5c7}~d5GeJsk=ia%v z<5c5cV4>!PG6@Lo(Fvyj%Jbir7 z96h%A;vwjhD*x(T?fVge1>Q!EP8QfY><&f>=xu=?wYzKVRXCuRCK? z&DDqOq_X>c1gA(+PuWadame}F^;YvN!Bl`{3$m2l{^PI`* zSpVXN!icEg7;DVJlDkN*7V#=6=SW!*{jFV&=z_i4E`y!!MaPyUU;AP!^z{#mz}17r zvI6B>O~=I~;D&RO_>_A`Sq(T%e6SLjIuxsKD$JDkL>Y1>u^bm_Y8W;Ge%%D+Oh#&b zoYdLjQv2AJk20E8sm93WP$sEix4#B}CoTb61P~*B2?gt;HJ&rVrbTT$W}cJ!+>q+` zrG195aOD#8W&Jv=I{Xt^7Le`+p{;8D+1DX$NgCyyx+4o0!ot)`bYZ0$-hwlJe#x+e z^KUb~hLxO8UyF&|X+I@vRzN3nsfe0bx|bNeDDS4*Oa6YwA9vM=R#tut;Cm1gu|IQS zOyl1k^Pu0Y+3Y}E!@2~Ae1evaRdpDnyo#v*BfF69gE@|eT{QN=!fNoEoqda3(8-IH zi!q(l`8$0tFd*8WKV{L78u&gI1&?T_!G}6xUmS>@LRe%PMt&-Mp%~IkZwovW)eQ!Y zD3ykwgXA+;;3@R{LRrq?S6+vl58lOg+ zm8JOA>5|_GyxXb_at92|CcOv-VgLsH8nY88(?)3!e@v|Iu3DfU)H{0ri|Cw_s%xA> zHQ{#bc6JV*;FuZRdDUB1Y9?fkft9WU<~+K62S2O`IvxN3X;+>W<2B8L9=2(}lzuU( znet5|rtkHee-v#e#{E&`OTgRgL4W{ZxA~(cONp)(dgfW2T;rRVP*?UueoBI=igSD# z-OQG!;fgkCY)jYTFqbFB{3*Q6{8)8X&+2X5LmmyUea?zTb91YjPXoob1 z^%}h`YC&UVi?nX)FyW_m0q-L{s2UTHC%2Y?2r%yY^CN(~jShEhm&9L#BLk4C46pOP zak{6t*#j5QlGxt{1@|FnAO6=Kaj*3sMb#GCk_nHz!2Bmq;L_e|EwR!ayNYbxn*}p$ z?}OLm6HU%kfR}(IivNBA{hRooN}Pb#8mfB`oWyIwv07x#dkH_x2djyr6i|Ee_&*Bz z)A0zha*V-bfq7=ow-FQH15gHkSn~nA&LtQ`cz};EAE)9}|J^8=7y~(ecS5(|YJOap@ zv}Q;Il$SilErSmz>8N)0RoZCVEX>pTm?zcJT+Fm2Kz9;HiM+;+dK= zXr8wIIW4iMtGG1clQFr=a8*HB`Q3}YE5%n#fCKC`nkg8P8&8Lz8vLL3d+LW{9$gJ&@D?0{EtzE>7rz9RQV~e+m~Yx z(2@ZHSguS#^18DRHU0TV7(2D*)_B*_J9lOCLi6X+n^un~xS)9Ws_uKUKM#);F1MS@ z)_Q23!anIc#RZ6OuiG>3k(i5X&mi8g=cq{8%3Xh z{ZVB}~0mzU$~7&9oI{VzPZGDKc|)~A#k$N&!7inU8+U3^@y`mRjBy~E^Jb#nuZ z2PF`#pH)z549cDS@p9%_W^|)59tx_KO!9w&|5|0$I zP<&#lsYv>DIX`fZ)$G58#J4j>{pqW*bma?_N`(A08!D>*gVSHHFi@bx!nY1p{!#e< zw+gbI=^sVY?5X0;s#D5~y6wrQntrVJ1LrpW;=ms113CfT#ZTjE%~WrP`#A6L{<{0^ z=Yk5D9k(r0#JE+R=vf3-A64ZsEr(8Wt4uN)MgX}XVI3y5efQo^JlebM!qs*{+&hEd zxcy)Y97yQ_&ru{n8t9ZZ`HO>)59rkK&XS1PGDy>@5z{XB>;E$c<$rHe|M!OVzrMSK z2kzx-J%H-t2E5C{#(l}hGsYoA= zU&DgD*gU$rU=vI&&JjP3&ZQ52hKcM2<27Z177C}`Wey(qnZok|=384-?HFj+Nq^9? zFVOv93i3@N9X@5vJ#0mFTG_5VSSLpBr@#HA?NmWsW9=_#9p2U|_4BB&FSCe$E`C35 z+Jj-9$pVoQNE@P7+KWeI$(XK2+Jck%hJa}CC$NJrHj9C$XI1@xoe?XKnv1xLf2_>r z6M!7Q$|e4ASTIbHZKzuY~}SUZ>lNZ5j#+)|o!48xXIjJJ1nicYJF~ zm-JJb=W@r|by202kAI5ElEbdG-H`_nNC$Hmwiy-dhymz~+)u%}A)rthg`!NI)@W0nDc2;EsC?G} zOPl4e(>yxl#eb+mx=A=*AiQERBAxKWtZNf=2NUr|>b3$Azsf9>3l@ zDM_2b?&$pig&G8`QUnV)26t95OrT>WDEc?$z}Y@x1&gmK<0pYYlDRFTBp(j&R6JAm zGgDV~_j8l=$ag3A+T!K(r{6ncDN%2g0UG2Ph>bkatPGnohC}Yp8Uk@X)uz@^hg(J; z2JaM^dVJB)&C(Q}T(RQ|>G%TGZ~PxP>bAH}qHnBm{=O1jgT5OZ8+-A}`_jb`L0I!nZtYC?knnjV z5XYl&bo_Z>e9d`*Z|Yi)nD{;pK2rUYL`?X5^kHx5URNXW$JVJcf6Vg?juPqO5mBoW zo_23wEGt%*CrSV*=tC{WdtJ>QAPk$s^){M>XOo&}D_J#VSt>aA_Yx@_VFSAkokrYh zRV(w)eLWp40*;hb<7BU_OC;r<{T2yu=WM-haOn@5-iTrqr4i;{WX^$Y#ij|Pd=5PF>tlJ$y7K>^v2C2wA?0e*~IRl)jaRTWxeJ*w5vlPbD1 zXW)TnDEZPir{7jOQ0!fYzorqH^;XDJ$}Y2Ex>LoAEaUP|k__7rTop$}f5O#0_qZ=~ zRY={mE~QqHlMW4q0of^X3Cgj`{(hEqW=(p(^Xk=LA+*pep%=lmUN zMpZvfmG0tQu5c@7OE@u+HDUYPlBKi1`Rf>w`_;gJmo>L#ns&op)@i8j)MdXU16fp} zcoYB7H0>cTue*zV9*}sgZu(WJf~}u|TLie$SCUb@MfP|fTx9RsvfU;7r?96lzL$h` zn*Hq@Hrwxi{&Ta<%;IKT_6wt`PkM^omF6mR9e_w1@a-Kg?o#OX6uwb;(s z)8kdX*Z-E)S$lbUwmcqXvvo+p+bM7=94_CZ3-1m5`v^`;9r$yxT_uRQeyYoxmV{O#ei-x{tsn3GNWj(H>{&_Y1 zt~0e>{x&!Nl#h^i!1vmO@sMwex1_DCi}4OUFNKwHYq!=Kd1|`miu0Z0D-};HR+MN$ z8{60PtS8HL3M>kss6XqTta2i4M!KBww>HePujAfW-h0?mwHv+Et@PF3i{&eP&|*DI z*C={duQpj+6FEF+E5hm0-+o;XM!h%jN8N|UHh`h;z1F%z#wPr8iL=FQHkH*@`L0>e za>eJ07LPAC#$`JJEr&|w@Uz`xD*Rn>-wd)l%7r8AeEdi8u++QHU>}vHY{oB=y{5WS zH+0(Sn__+oqh-&NJD=g+9qH2inskS_G)xI6pQX&Ei+{=qgovt-CwzFd2KrI_^FW1` zE~7PwKtmozFcHnm@OvnUP{UVqKE4`FO$56?*Op)2RrvUBF7FBkt_o0pR zI-1(Y>Y@xz7oQ^@w`Iv3^g=@;#;~up39@2|y|Ns+=6I8iSt#T0eQ(|Ciz@PZlSmzB z9aimQv9(xNt*M2l-rxINi+X}ypR&P2;m^D>Gk0HUXqQ-wrwm^@{joN&{!t_Cje|<( zp2Z%m5U(y(T=+uB9;@n7wUs+Ivm1IJEAin_`C;C6Wr&|Awnl20{gY(-p&vU56t+W9 z_7+x2R`AgG%r~H4F4)9ka?uQG91@>QEodGPEGWTvk~y%om}8}GFdnS1q!fC6;K|_M zIzb^?9<)CFps%y&1Z9LoV#lo>GvoEK><`AsOwEfA`KlR#Amr(4B0qM2RYr++=nk8R zNM9jI)fcYo!GHPB$_%FjPoEek%@RC(TuA zZ$&d=1Kv^L9EPo$JRlk0S~RJrhEa}T~n&Yxia&IB-ir&tq%=uaMtlM9st zW=y9Cu_P?{F<0$B8sz3B*>6%U(_bBXQ~mehi3gp zv3b)YY$l~Z0em*|8u(zrXsUu^!zamix4hx3fWYEIYL!V3D-*m<&Xie*6q-on!2(u6 z_ldw*N>lyNA8t@KJVqq{_eQeA-GUNur7O)p3W+pgn^cZ=jNY11C#D-kpRyux>rWXy z(cp;`G;`N^JREWR@L&WoZ*UD9Yf>PVc7`f7eY##J8pDCVfgnH_IKK-b#u@?Ant(u7|e zB>DrzPjTSqcrh&Xx>oYLI7SWCzmt7sKxKAOITiMW)%VqU;;n)AD~k1pG?{CSJzyau zc{r3ENnI1LcEDYD03Sl&MXP_+);;+1%aDu*cmCJvm^!}7rC)_Og05}LjMzmN?A-~Nz4b>E^U(|{*=}YHNF)h700vP#tZ^Rw^<3EBNIK;~Ex|4r0FYQ> zpgeeaEo?|cE=;8;wWV}1iodqqV8F(P5iYDoX8OAf$po{L6^R<8JY`o8^ifpc$CX{F zAMrBLl1#1ia4lq3wwH7}kZL`H)j+ldmWt?5A22$aCe0WR|KBYhTk!idu7cZ=NFp4=m z>QFk`@5F5S%*j^1c%47%e(#NIg-t`c-2>pkpPDS4XME)o+u-u?+)2Hf^?#tK;k6xP zCYeeAJ^eW~W3`vrL!o~e9l+_#!o9&EE*Ump$$-pwzOI~iQ8d1;$QXC|0Ky|sJz9$f+!qX9%k z$oi}K&?nF8Dc>lg$i4Nz=#B|7`G*&I|nKUjxG$72lTs!nYAPmdtU|7gYxESuof>_iX5ZoI*1E==eLX1?Y!j z7-75^)j5NupT;q*1mypJPNk+Kvd}J(=^>xWScK=Ao5Z$_AG(1J&rMFw^L9_(v9DxT zsogOgF0oMetR8CtDow+}y$|DJ9~=r^!KERg*_iR3Ra$SlB^LC$v4KQ+iH{}JvrAm^iOi;3+tYO-UImT zH3WttS}qdlRy51L*NC(PF^Q0-qNv?@B(xe{T7mU*Q*U#{!y4A zb7QFse!T_%@P(< znlpwGZuL5;>>|U+^Y^+z3%q9~$Kdo}=lE|%yFt3S`y{|#M~#gPM>vc}Lz&v}G1x18 zi`iuXiCVY^^Gl-wDL=JxgW<+krW%oUrTtDP8b%>kTBZx%!G-g|1TpYND{o%k^So+!;V6b?e41{ z1)5Jx+gdyL-0{=A8{IamTtWpq85Dl3Dr)1G5pJ#O7zmCJa+5p;zE!t+)5!#S7hg&n zTLUrwbM8k00V=uq?f(>3^c+0;Wds@5S}Kh_`i)=3os-hZ>_BYBZ6X-6)Dc)*Qf~Ff zaTEqq&EuttDzxgZ4`wpWd_uAzeS0JKkD_)Z2Y1XYuT+Wt1?sMU%SsaY zlN3-8mF%$tq!%w;^Z+Zs7%J3Hvh0#L{2t#Fh;fW~Hx(TH5d7w z=XLkPes`Ir$L@)DKJ+_9s%MSj@&h0)&0LQf*T`2&xdu1Xys_X2kmi8$tq96ym-nW2t& zs~%`voXfcUtRd>GA$hW0%?TPN{gJ?*pBa@+^~6&o7igPQ20B8zF5t05u5!7U(xr|k zUi|XzZXd3507zX=QEUHN7jCcgEdkJQ8+IcGUCWsNNE&11KC9iGSZm zd#*C9xD1&!f*I;Z>(_uI`Il1W_07`(qH_q}hpq7D$PA}^&&jkavT1}BFY@4h_-DXl zismVd9zU8j(`B>Mm9=;VGlmv)D=7KAKgpUo6$7qFzcT#Fft1HUH+xjDW`$*hW0hrQ zZY%JRR`_-jgACqk}YREnH;{*FI$}G)53c48^!*XQMxXamh|AaS7zA0 z5C3d!C+bxDNA`G9l!x3?ZGBt9eRuXQs7Y|FwGXEOykY=4+6P2rq2(~o} z8cpK9T)vjul}2U|bE7*CgcUoLWTOR5o9ewv-#j?BsN$=}C%-1FItGJqWdd0426Jai zMPP-Ex}&Ro8|$v6S;H|rf0at2x%_xr!w5^|O1jQHJeF~uyMb@2dwqwMNAj6Q<-Rs2 z>rsWd7AD$DFzijxuq|kvm5ZQYw+9)>_yJhk6NNC2L1D+;*rHTxiJ&{{SbjtjYNsnc zk6nvsR58%fv+r?aWrO1M=K6Cc7jGKww9Bg*EgLaNQ1_anaWX`?8a=XkD9<%Nl|YZG zT1vJirAI<+-HG?jI>383h>qyqz(&P%#C2JHRIJhACTPJQw!sTy*#r3<&`{R0fA!C_ zd{>jK2sw-M{f&w>_uX<^Z-vuwp-d8b&APNxvZMY{1Q!0nLVvB<+w;!P!uGg@_?vPz zDoUs~d_VI5-JkkkFX^DoDsy}z#Md}rnEuF+Tdc3k&yYI(1*3_po<4@Zyh4w*AD4sP z)H0P?pa=>y4nM5-Ze*z7!*&epKxWc4JU;hsyt32Zg=&9$S)xaOpElaYYC3acg$;XV z2FI4mf3tbMttlbfl$4Oke3D3@w}=AG;? zZju>W!Hdr|O4tey+p0E8UF~Hj?$x_8W#+lf9O}{Oaz+<09KFWIg`V7h$H2S%6>GHA z*M9%0;%in|4IQ}Bj{QziX~{$NslJTqUEjW+KgoBcGo0~gNW^QHALr0(A->yz)5EmS zi;Qx@Q7U?dwNv*Ib>Da&g-0KZIgh RcL67Ri?7ZP&px8rePd)lKo0<9u+tAeP7G zeJH6R!`4a!D^p@C=P|MptyR_gI73sq^x>Cfd~F}|J+mXtmkBvWQT?;!=D=Lt3#VUl zzp-^mOOeaTm^&*57suh@-_qmxq$T*)Hj@f(9x)J8PMCU2d@Bo-RxttEyT_J@z1wds${QvC2s; zM)7gsdx|m!JfKl|Xq4=i&vd?pi*w4XoqqMV$!X3I@$1?=P3Xi^ZI3DobA|9J2JllL z(K%VaN!N@&2{JSwpEnM5M7a70Y#8FFjFuESRt6JV!g7Rf#yvY+u-vE*`62cCR!Tx$ z^1O$zBm3Xx44LX4tK09{oL}uyZdw+;t;#kT_8h7#ecppkC;~i8eIVAo6?VLJ>Fy$L z9ZS3I?TXJ(TL$fqfQ6!EZGrH7EL*{Z(p?Pz*Awcj&c#frGol$m4b)I{T(g{b3>Lj5(Y!J#T zsQ{9$y+6#>Pkv}x#oW>8cNsBDqg&}^4~_#fuwRSTRWo}6%!#2IdgS3(5~`v^-Ra9w z^$m?`i%d@iu)Ttq_RHcp>3cel!4GXA_ft=cO^IQqkaiLO-xk^@=ZOQV zMq){H#Ot+1$=3H_-rNU=XmIIGjsim zjoAAk#0TB_BGKgQOCBFjC3BoVKO0R=L)~iD`PB03lTBPB4X{F?M(cq4^oNzmH~0J6 zFJ1W>{6e03>)h=c*1UGcD!S4ohVd+7MuF9&PmBfUJ&z)OD2KhW0|OdtQF5UxVp4t|rLDBH5;5w`+`6*=DG>{$Hs zIrm^h_slL69^EcyDSk-h&S$-mauNo`d(0`oM<967s?t&?ZWX*)%2ZH{1mfKviu=<`pB(sAXVOThqSQ>oX-E^>_i+wmWl_LbkNO!Y%R zibU8#pIx?3oN{083apNw66H*2;S#*`F7NXH@{<0W`kx9yA=VoBVR(qub()s90Eghb zp<0Ps0@wt-u@7Leb~>UZR!JKm9Cea!o6J#@4tYlK13H90hLb13 z)Uw`KPAf*BwB2Xjd_e#2*6R(89i9h(h7hhV$bVDAKk`75;2!KsDy#T=z=4u!kZaaR zd1zt2u!CVW9JLc_TUgPwsY^Vo9)EU9hZk^N?bQK+{F6?Q#=m4@_H-`EU`JXiOG342 zTVVlS$GL%JPK%5x`iF>yrv!8I5KieuIFDFLe-w1;M>u$|YF*oOKFEC&!BzI=9oj}y zuey2KZEb4*ZBR^R8WpGhJwHF24`tSiCj%03)y{s;ub2 zd=~$rdN`17IE66GqKx)?d}~;pvMTa0tJci1Ax@?ub+%!^H2w3FxZ9rE+m}Nj<9-Jx zzzFte)`!;c6<(Gg<5cci^rX`L2R?d!(>Zcoo9SzAC+oI7B)w_=aU9Ut*A>7QU@TAlz?WWMAddq|pZ|-w_Y7(>{GxraB3(fQ0f`ETQl)odqlt8pPDGGi zq_>bLNH38tAVfq!y7W%yh&1V)Kxk3|2_*zlyzl>OstSWAbE%^WGC z9T2ywL_m5MJ^*ZmFRz4u>pd@;GCi(*(eDxi790uh$E#Y8{!#p=Zlh`?M?q%$Y_eFb8b+{SM%^~}{DJZ$C)LlU_$5$VgoMdODT`<#|@Ynr=zMQqbm zTRIKqwDdEQieK`iPD0g4@5p+%{T|dDtudg_O5<(5=cmTkTztAFjgfyWrDzlA@J8zI zB_~-29UhL|F6k*Wm$HmEEa)#v3Lwr0OzY0ma92h zL+7DKP^leA>ULpC;G<{@_8~t`BN<#_9F9~Dt4DXW{kdbKZ4=~} zFADxfIK8>N`uO1=Viv(4&l069h#zmazJp8s7*tU2P&&)aZT9(_j@MZ6v;4@%EeS3J zh8|Tuya*t8!ks~!0Tu1C$xw?45pEs4%=#Bnna|E;O-%ejcCHK&)Ie6R!!-4PPDzd~WTMeji#|fsR>(uh(S%R5hmFRRnEkEeq~q zaU}$IoE?mjXqDGj*iGWv+lts}o_%RMlw&ji+Cwxoc7AwNugpT|q_k4mVZSr2rlLg# zD#(x0(1TT@Hm7hT%x*+DH7aRrWA$x@288G%0_bN&t5@3n$ zhZplvw47X0mK^WTKRXTd40;h%~%3xzBSTmV4%$_Vx;-h|*rj9tZgtXTEr z$8SdSH`Qcs*0Fs~wfEDA^k4Ml$0{QXtcSH&g8Tugro}z8?S}B6E2s|M7mmxWk0|%m zb|DRjYSmh}S?^6L#hWuk3`3iXmns#zgIc25NG)9gJWgu^zqEgz|GSV^PI+7k(!c1lNY8d&*Ocn zfBpw;sLI)Dj2|Zr_xjB~KJwY03#wLmD&A*CurK=OdR2DH>+sX@t`$C3Po}NgVs^S- zGf5gZevpfXs*eXHl` zFVj_-P2lj4l7xobz`Ge8}+Yf>tzOxFv8S@NHE&UzWQ zHX%C=nLS~UVgwmLK-!gO?2jg77@WQ)$*Z4JiaOu8Pye@xB^qj(NgG`g<=cAW^tqMA z3(Y$Z;Q`@6>=oXk(9co*KB~g1k*f6HAuj{f!&b_;I}2Cfk>oqU%!O~=@Lq$DuPzdz z!Zc&p59jF>2o>9Ps2}f)dA1&?7UD09WrmxuSJ4ZP%6G=lthNMj65pJ>?w^MUJ^5^} zFHAnf?@-lK;GHO0SaT&n+hW;>~OR_@Hq|)%Pyr{JPOL~xw0P>1QqwV7|)TC&gvui-EH&?CqJ@S z!Jq`?i)rs{V;0IPl>QRj(+c@@^s`oCIBygBd%Cp=$xb$+B*O#(TnK@!#M2_;iSc-g z%eSHlkKJ+s-&lu?_#ZF#SiR^sBY-8Jzv8>ecs*du&j~vp;0=IH<4uec?dp>BB?yS> z%Ez)Q79hDcmoUW6+fyV%7byJu*R6>)9bs!(_}Z)U#<}r6+e%AvM-F3G!e|{adCP5` zV0x-rmqups2g1Nhn5+{Q1j|Qy1{(*nQt62f7~R~JW^v{vOUvTuwX15^y>@x-EG{ss zxJ@O_MBm)e)mvh0N8^{U@9pVLx~Zx2~2 zy#=So{djlTN_k!)DSt0mdUb8ByzE2@j*WZfXjDDf8p7tUilUUa36Y=GQVLYL$n?Mt ze1E}`3w;uL_x062=~5J!RGA0rZS$a%p`1rzAs4{TGa@xg8GN{nbdR?pP2S5r!Hn-u zKc2at)*)A%4hLa%8l{1eD*+BKj?t~(F$4W8G!EeU!sk~ z$h7_zkK7zb)lf&9*Dc^8zq~?TdQy*J`qX|DFrwCrgVd^QL>4)#d(b;4T5GY#eyHQj z-ME_*S+HLQ)9WN(dv0d$8Qu5P+`w5?#|n*8S#Y;CWb5k8BIdM3?rL8oeKqnE&xcFi z8!0n%v>*8_rZ|m(^up&&RzV-zz}Cc(PD5oB3-m$BE%vg9hN`&Ko`|C2gdeZL7(R2 z;g&GCzb90?Ui%n-%>l1RN967Gqr>l|)jX0UlOq?M=jX-weq9I?1O#W zsuZs#&@PHFGr{Pn!`EPFbj^O8a&UeC_o_^9xYP1H`rfw7PUPI%Os%y0tD1RS|j6Qf+omQ0bpxk zTHSAC3r431b)M+0vGY&(s4fv#NjzjfV)N?I(_UcnOLaTv>R7FDbV6qQJKMP8*PqE5 zn09v*!knnIk^-t3359zw2@`@EiS=axgs!e0kZGn;Y}iG=c=vmsw0QRKhGvb**^#@& zf=%X^@tlf8=bCK(FK_k+-^}|rl8W-x2*Sp-q!;z3f}1HDPp6B@LnRN`pWXJJLh*I# zQS!y5Dsm%Ni?p33w@7u-ZmWWz-DJz5Jc&qmuSXXEo@u`cNkk9P174DPGZ^~3k|)?? z9ZtRu#He()a<9sDfg@C}5I>@sYZguP8d@4qQqosNN*+8KQ-scR9-UM?<(xBDx~Y#g z0+S$#Zh1w4}TvLhmoHdD7p2{YUfG6H+{FczRg(CzqDy z-076*%iX;_p{nNb$3JA_Yk5kVwB3e2Z1yE$+nP2ab#jmxU+}Dn0X#%rW`pott*S^x zI4$C*bP@iBjgVO?LgA<)3grfl1+HVVY8xE@TE4Udclb~Jr89`!>i7tMJzh4lFL21c z=e~*DD{(umG>FQIlcs;Zd%8(w-^3zu!98a;3USS=J`nC3!clqC(hB0NW;T)U4q1{# z#%_Hc83v4;JX{pB97p%UL+tdxMaCkYqP+*NQ;ypT=Wg8@=)1rvJ zR=;WMRjKdCDp?SdU|(I`jwF|1Ox$IW89|jEIKO9TtM~5T3Lo+e1qG9b{ed&I_~U{* zkTl0pM`cg@OgQSY>>}u11(N3-UzKF^j z6&gqkqwN}*9iiU$h)9~V(Due?B*}B_W3^ic-J1(Kg_*vwU;N~?%ypW#jOqr>fe5~o zGT>XYLvscdDKgO=Pmp%6G^PL#An`)%O^Qf0A+op1n1Y^FT2dGBQVZt8*YM!qfRSOvCE*zof z7`jx2nut0pSn%_4uGPn^fgC1t;YVRZiHrh2OIqAC0Pp|4_zVzZ0(*e3-<`&hdU)kq z-JV)Z`0Pt=Z0Oo$oy7eZ+3T;V4OFOQl$M+n(yumjrgX?I6^@nMhgL0bG@xR(@=#sD zhZWE9vt|SAU8m04a%sTE%{7^Uc5KUBYI7c=1F1}#p!%?}foI6QyXVgD2b{N!Z!pOX zW&Wcv{K5Y5Dz4Ilh^x6#$MIw~Rk<&$98Z5`UVbyInUZ-tLQkEcTVk`2$Xzm?F=PkLDM3AJkB_CGlS@bRi&UJhsG*cW~=?W z_ZF#_p*&TXoM?0JwIRiFZvoDrx6;CX#pdEQUmihzdP8!6%~dm{`FcE}6DvvXt(QIH zN&5AJ1)XI0J&b}*Ua$BiKPvpR4V8Ola;1Jq6^+}(w6YU{Qusf+U*{H~5-2xejNZp% zHF*~u^Ul{A6sc_PGn120Mg8-m|7~^k+`ozcpX$UOfUB$i$pZ8h(cQS?%ina1T+luIcunFKjI??n2TpP4Wq^=}O`{lzdTf_reQlrQ3_sZrd zZQz}<%tyLZxVs^&4#aQ?Ey!czs`&2`8WM+*8Qh?KxnCUHPG#K$r4hg~^Jo%AD=}3r z+9Hh65$wLIX1fxA^eO21noJS+N7KT6dv9x4_`t9_p=W3j`6r#sI=;NQ3kVJjRxCjN zSAjY)1H+#b!YZo8Xpmo(9ll#n-P1~dyAjl3@+dc!*De8x(!ka_oGTTAf5+x1QHU$p<^67tQo(|kqj;qQWzl4V@l^zA)M*S* z6x+s%ou+8S{M53aga=nC-}zqnp$xVTsSi9|@|r1U!3^qe zgP3aFgq)zsf!E?K{?tD|xCTz&e)L2~eU_j%qtA^%r3lZ$bMs-~956e+?voJXWjnS&W| z6Yu{5r_vg}P*>-v(wwo^`9=6W74my&9tA{7u#^bm+OvZ=r_0m22k4$IdVda+FtdVJNqnP5< z&z)3!7`j#RA7&ce>%vqm)pdtff2EDrl8V5Hi*+w&o?uMugH~6IWWMm*;5&f_O51|1 zT?RYhEzd{^Dg}9;rpLbly7UQK<}vC$$^p>4=a(h?*6%8ApDp&RA zD{eh~cBQ7Sx_*sccITtm;=(4f-ETocAN5+hp3W z*h;`_2GE@O5==;H;HPKs&JAjX$;9%#G~C_6Q~ez7+$;h^73>K|SdR z2PNi^Z57q2`+Hn_Yixb=O4DT#W8W$dPZ6Zj5#DNIDs7KPEc#l@ebKSu&c4o|kA4R~ zPrK&6Rr3F%sZBmL*&o?`tk6J7q_X{P5A|V?_(k2u0P4;4)BBGD`G}BPVyhRVH zXJU$Db=RJ!c>O+&Qr7ZdYT2s!N7J+paJ~CUzF$*9ZjtUf3U&jwv#whpthPP3b=BwJ zedp9#LTyJ#j{!>ec3*eNd#T~5|d%r%v6sHE1jDduTvo%)mW%DM9|f!O1ICx1AzSbZ2MjZ-_rcb^6~F~CZm-5z}p83*M*VPYMx5= z;WmwYL3>pu8w-#SSgo+Vhjsw60Yz8K9SjMB(N>Z0fX(yHNVCF_U-GtWWu@kHoXIAu z)3C-_cvpiHkkIa+3rik?I9A)Ob#|n^ffu*o5Gfb-w>i_jkd#S-ael>DH;+ z!{*Pgt1mLFNAezH0U@m$`HSj?FV5QNlGzCIhyzNGiZ~P_l{X*~BiAh|;lmAKaju(_ zCR8_&o-Qm1ev!Szn17yeQ>9nR${_)4<1xqAp~_AS#*}2Uk<}jvHhqOTaz}QzOwEnly|9Y}>B;vfArD-0_wErAd;`&tgXjqfy!Z_kNO;ic< z*O*6i@)x9OFaa0F=URcj7gY`FMP1yorkzrLx>A%IiQ%X7{MH*+rLCw{@BVjOl>4Et zJe22Q@$Ay3BC#>v9`lCz@uyQ8~?WvoI~!qC|zeUlA=OByR+J+Mvev#b?#oV$D7 z&~=WVfzImYatEh2TRC8%GhxGY-!5SV&uy2};21PnXu=wqNNHU;^SE1hNdA?}z9K2C9Bj%oO#Z_?6T6!Q5vU-Wt=VFrqe>fI%`HdK6V z7e_xL#$o5_3{H8CzZQm70E5g(&^2X_VoS@A63lQ0W9-AZ(Nl*YEucT)nLhS~OmN

^iD1HIR7xAAlTq1z5DOSW%-6 zfsGFHsPrXV@GdaXa0kBcMt+w6GA@*B$%9%8T`UWzJ0x5rl8OU%x)hbuc`p#lR(zYs zZ-=*kv>dwVm3!Lok4B?Wv=7%OH~^_8dh4c%hrgSlZ+>YAksep|mWGXR3sr7;O!6|| zt5?+0KfvFjKBCxsYaQ^@-AuOnlNIg){LS-qj7rtmTA&2Gr<)P)kj$VG0Co`| zZd!EuPfbA_0|E~=6K*7E9-cgvcIQVRvo50^b-&DyN)@7;&o=%Dzlh=+j(KO8{1=1X z4mqxX&7!Ic5X-+>eC6U@-Q7Iy9F}2MQe@_HECwD{3?t@gIZG=(f@^uB@fs`fCp}ny z-Q>@dUp=z)X>HLgjK7@+V7YJYfV(}xFvvqBLYs>b?RaTBgDCU~~ z7&UTzzn5k14R~G<^PK#!4WC`u1rO))$z9T(7CQS7Pd&tLTTsn%PmT6v%~7^(HxZGa zh{9T!$Kez?~3t^F3e?)R=eHNA&KJJfCd?|CoAR7cKPy-#?o65O9Nu7X0h&YmYsyC zY41VRgNd|J=Fm69VlWHr|0muyP+eDY)4tFj-x zuDe-H{kL!bJTZX8sdD2}r^%ATt++^IqF$McA}UHo92=_>Vh9(o(=XY$bYP*R|M1j; zsrie^$#j^Rl~CaIO0OSZHw~Q6ejJhYhU62P1HyHL=fD{!h+PMKum)am*Jc$FQO^|( z#D1}j)%pjxYjv7waZ3jX60avokYx_^c2h}GmI(8zi0kbx)O|2 z4b}w%>U2@7p9CUew>A-`_10p3zwnpQi&pB#I~^5M0_ukhCO|IbOIz(2;eK$m+L@Io z%a|m6db`HvX-+L}?TXJS;ec^W;%sd)+e>n~z(hskJj!In$}7`4icFHNpIRGrd2&fC z4-WM?n?5W7)K*#|8jrwm^lVYt$QF%6TS{tC)G?c*y=Z`#V8hIFHGb^_H@ELV{&^q# z@9>RoqrC7E!*5Nm$Rio$jhPyMN4h|>C@snd7%yNnqui?w#7p&T{2B>XuB0HL+IP~d zvT{tsHa8O&hdr&W@Pbb%vGC=u)^xSR`XZ=!=ZNGnK)Hf5-V#A{d%Pbh zk~{b8gl8g;i9zi~;SQ*QLG6M^uzn|}NbV)IcwFhAHl>@u*!a2L=f-M+&{RqwarzJq6z zV@=fP9D=EzH~q4tkqa;I)*6iQ{F>WA)1oZz$I92E z5(Jg9K;~os4HTLYV5Bw;b`<~Mhq`8${0tXS!js0))Gczo)XPddGym6HJy9N6y@A>R zKbfHzL}SrQ>%s)sH27j09qgAEkrrdJ+q~+8!D|qrVqAPC`C5{+L-M;DqJ&-F>UWd z72falZE1b4G>J|!_p@8F)3B0H`MxFP1Kbf2eU=vPOR^$6CHKO(M#U~oWXfjoAX}l= zKKf}UGO(n6Kgj4zGw$^_nOv#nl7CSbx2=9qUBA?yR^@m`i%IVTf20Z$>yVWi-S=zZ zv=z}c4GG9%vqjO&i*Idtw8Xr^Ke}E|z4O_X)JJ=m*GWB(>)Z7p`4dfm>%G&>9gPu1 z#J;*x{x(I!yTqwL9j++F&#ixhMzhc3!O8pH=N*PA?^10<3wd4s(O8F1B)Lh$4(2T8 zOPV!@Hqr$Z&Zg$#$i=f2J>O~*TYNQ=$S#yT*iGut*^Mj=BF02cHpspxNQ5tQX-WHi zRh1GICpdWdIGK#T+GjgIcv;`90%p58*Vjs2pn|8UK&#WCj8zWAP;U8%>RE7!;%b>b zML4C9vl_eZ466ulLuMA0D`t@^ruwp|NY^a<{7}GYwYHFxPthHXR}_{Kj(6uwrW#Q( zCML2-hFWxWdzDB0wOBa46k{fo&LPX-_?fMA=g1#o=9&(_mULF&R!qe;;e+Y3RINfC zQ>s}p<$g7e??gev(LMOo;8QgS+!Ko zC}Xs^Po7G2agqCSCJ#(@9poa?+ff`;F=BMNPuXQFCvh7G!#gC!nsQIFh>0IJZz>LD zT6i4uKqcArtS2%v*Q~8f;3Na4N-Xgtz22FN>_pKLLq`CU6@#>W#OBLMaWm2N26`>y zXI?GtAn}F;v^eb%xU)``cU)QEo0BR_hTtDp5lrZB)6ZJh6MG+C@jcZEx%_N0=&%P8 z!to8Y5qPu4ic6x)!VLnn*L;rRpa(;`-_IRY{8=jO>CU>a7iWYLYJZcMb2LeFVJtN0 z(}EkrL8958kb~Z)JGh(2Ox`+?um1RQn#*z3H>v+^ezj>f3r1o0Gd4t9qB$PreB*#>x*#?JSlP2R}ES z@K^p~Nn5G>>uoshJdb$y?K{wD|33tf|1WTGj=yacIp!bc*#8!-r;hY-qe;64hU8lXGiz69`YbS{rja>ZCN z0fg%kfsQfFUhSKKe}&fo1LzsLE1nkPhw#OF2^W!h55gy24JOK^erkWO7~lTZ*_NAI zlN3v(S0d@ahS4=Ia;^dTo3O2XGj3a&b!o_f0FhlxUq@^x&D$89M0!Kg$hJ$Fe^_>! zm;Kw(k&qg>T`gQm7o5!}PcAukwzYPU`E^T8n#2dumYu^p%b=%=E@5z9fNfQ2Jdp;! zwkzHy3+0XERd0Orf&BRUBj!K#pP(p5HPFHMAG-!pZQf*t#%<76a>DnM> z@WLlC6cVqbgVuW3xc0)Mc5*@xiF5C_(E68a|_}Vqt)&_hr zAGwz{{7%vjcZ^1 z%${1iq?1+oV8%blGv;*LV{UcD2V4v3M8-GKO})nLe{>_DJA7ERKZiWVS~#4OIv6g=F@T<;`vigCTAtrsYz}jJd#|{|(6=X(_2w@mA%D-&os( zm_d~teDdmkj~Pq`YK~{=POF#I-yXkksabZFQR1uSINyxJwvL#UyPj;CvVBa|rCULm z9Iu&8)uj}gkIQZ&Pj&dN)A;QW4SE$1AJP41UHW3bhjN~mx@j=|8JzHnQgDozh4=cm ziH!T?PbCr9W3-(F9c|sp8rZ^JPYP<-%R|oLSqM8ghh9Wf9sDXxj4Y{RT=V8~mcxy& zKpQfQv5V`gd-_RnT9jlCn^wI{$-}x@=-?!`xDqlvZspgmaa#0t zEOzfT_jD4!+pLHAE{tD94ppVm^Cv9$aenWv3QHD9W^Ea@bQkskBct?=;)g0TAfK2N zLz$7g=$m9Z3F<9x9c)hhec>Y_a-+LWwXT(tU4xEBvce>Y$$hH#xh@3wcZ<3k*er~- zu8q0M?<&%t77`+ePn~db7%OzwfSZ*spjOvsY`mPU1#Z+djUR@E__iS;I4?4nqPF5i>46w!O}UDQiRvY7zp#x9 znwGGUiW(G;U!6kTkN82seuz=RK31r0F5IE~k@)2@t|9BoQn%4TU8nX$-X+MG1L#Q zd5Sd$IKo>g#5uniX*_D(xOVBk<7)rkUx7kVI7<_~UA>RjQU)k_7I#`N54=FE16%Wy zf&r(?c`hnskW+2KOQ$zXKl{19G`V9N?CjrzEmb+GztQxt+X3Fsh@%)C*6A)3eXX9P zi%W8#;Jmr1ouggdmykc~69-&?+B2uugT(2^b1W0`mPbD1aA#TIDdQT~6@PGC>v+5V zyMpgDNwKu~({)R}O|X>yTLxq%j6G?Jh0Tf0+F8<((C<&19ZX-X?Z%65dr5bA<8hk4 zf_%jcV%|fS5?R`I-qD(usE6k!X`BBkGpNBTz4)xdzI&+2m@e0B@ILW__hD82ae4SL z_{4(hRlS|Ir+DilUrSX&Lx_%<00Q!ZbHZse1Rn{`~eHtbtla&M*G~JC@8q zPVi)fNxqjOONTclLkOz?MA8vP1wm8H1GAi}Pceo^fymy9VC*dQ9G4-W-b_jLv9ML^id zaz9+ohQlhH*&eH8*VdryVw{)-G;*G)I*6$1`T_H>Us-l)%?U6_+Z?*6jT4mcF@h+>bEW1KJ912e!oUV!bvOt2v; zE%3~UnxDMHOA*aSUZ4`DI?Y~JH6{FcwBh|A9YdiU=hEEn-1 zvOp`=GY&1B7OC{K?5FnP#Ia-WBr~1Xn!NV@@3=C1i)f$bv^vtS#;rZ!jS=F5?r9Hv zSJ%5?|Hq*4qg9U499L@X)*1w`fkWaGJv$BmqZA*8w#5)NbMEMc!`U~+`CpB1RFCcM z-L^?f3oiLnx2`hHaytE&7SAxV{f!cIWnnM ztF*3Deg|X(wt~5W63GpKMAE$rV=shrckHXRBuX<6&h&B0;D4s2gSCuSn75Uk|77)G@+3N`I|#W49+J@ z;t=5;Tm)%iR^d|1VEDtBCzrb5J|@R+A>$1<6~+u5@Uo)!r;{G51!-I{c*G;u{eX;M zT#%6OKi~GM{*y#V3t+=hf%@s1)k>pMVXl=KL61~Ko-f68mW;-R_ zZwgL+sI1x8bsqIlIC;nj59F6bv?<{t5|_c;ME7~~Q7CvlB$VNk#jgXCH?GjVt@miT zA+j+s!k~M$?sB{$XHfio+3Dn9s>bM4$7u0<(lf|aVEyhPv1nyTuG3lpM^=o;`nI}z z^~;Ys`tu)nm%?ZmgH4Qo1o%ImA`6JWSJo=%DhUWOWnC;SHyVoS&7-kFH7B$>O=5PJ zlJlL*C+1!Hn;{1hXA!p!t=ys2xv&mo)lwJ+Ow{~}i*8P|2(qxU)ROsD@A_;}qw-fp z0aR-lK~Jpi1f~O1H9xo?HOBS_%j>IMeX(|tt{xN~baOf?qu0$k+?%%f9@rWdt$aegW zkbUpIi5h_zz(#nbDMi3SwCF2w1dOX1w~^&RKG&UMToj;GFLo0xTbxkb#%=-T_z zMZ47WYzp&>8&V*{V&f!D!ahBjj~Kj+W_QU^#Fc-pYeGlq?(BrWdGTeF(>)6z^LKmE zI2``ael|hyVFk8is4fY@Uy8aI63^us=f=dsN1ViQufY3;xCXR{$=|d3ed;C6t)BEg zSXn&zBflO0p^=5hBrs$J&gh)O0AiLA6?#CHO>=tfYUa&m(fg1M^hkIcJgwZfZR*PU zW5ThyZ(sR1-M~8qTUxJtxB_Y)i2z-^jjAQOePepKt;-e2h~Q7)`1ZD0)MXn)3j;Yr z*mhN=7M&iGt@3-;y8LeTvRzWpYtp4-HOD%J=_d7BkL^vHjPRQH13=8ru7uRueG%+1UAUzDO8EMu zdg?TCA;5IdPf;c_pWPO#W3o~h*(Obt>pXBZ&9*cbkRsnE3SL^R{16A8~IB zAHAsWX(3%Q^zuf@)N6mMBD36U(+d0X?Ry;%A+aSM4ySDckvaZAx**IxcH?dia7lYc zyG(mhW8(aVlFRt2SaU|l7Ua`rU>%=a-^i^f|CAHe&{X=D4}yiv`GZhhgg~EDs^yi1 z<+GErTdy4BNlyarJg(SI;K(&p(2*VKJv4zni~5?H_gh^PZG8;~v<*ZEP8@;<$G~{z zt<9~7m81LJ^*SQYN|TLp~ z*3IjZO%H{hMr?EXRfLhffdNiEB@yaUqFpw##X)6HGePrnS*xe7-d< zS+@IiV2a}BVV++nOtdREa&h40y^3X2s4C~!*QT+u^>mF|7D4h0F+XUTzc9I1m} z$+802d7t<|H3nPg46m+joiDspwkx&{I$4nVRnQiBF09j@*|)M*^j^PFigA*XUKqHx z9$SXLuzEQb2QUGUmuzsu8Sk{M7cFO(X8W$w%W;@Fh_vn=G?KDHwson_-{V7~>OLAOGqKp1vnHvu>Iya{aW1d?ae^vLr~H1Smiv zl&`x!J1j9%Cv$OJFWY=1o(2juEY=k04i{cL+_$b@5og$HV+5|16;a-Wc_&4g7C*m- z7rJF}ad#0wiugf5TxYBKwJy260`$_g(dt6P`zHyh_J0(zU#{8*4tcF_QS2}OT5mB9 zbo0hMD82DE(2ZU0E@hdkM8o~%4ZaIYsJbf1i7Du23{{wStW+?$FF$ak2NepURaO4$ zXAbUxGxbyye72LVlIp*RyIF~{OJuiczJO?Mukfmsk+Jvcg_i%t!y~{y`*yc*dfi*A z@Jqy3+O6i|nR6k!E9E`8)FVK8ybmWJgm)l%$QqqHY4En7%-`{xhT-3=o+r5PqRvZ@ zTAg?4_#oz83k^TAPIO);kh-1Wl^)Deq&#bdH~D3W`h;N}Z++tP;@W$TU9vpK^5sSt zhfYWYoTr6FunQiWX+juINjfErU6xod9|*mn$q&h3rsG}y)DDcUoZnSTeQbQ|y^e@L z<8(b{$CvkGZ1KIZOefJEZu23fisKr}H-=_EI`KH~p*kV*6*Z&fb}22N&+hkFbHzFJ z{_3sOkn?j?Zx7ns(vQuLHLA-PkOTXgNbisti!E}tN=DjxRj)Xi+~%F!jM=M_Tt2Q? z+Y^n)bAcewP6t-gck^%qt0yr~;Z+EiwXU+!%KDZn z@-RsoOENl7j6B62+PyyK(b)#R6<=Z=uXyV&O6paust4se%FZJUU2C7{;($M|6fb8v zu0FtI-4nX-l>1h%B#)#PcM$vj!KcX{G6Qhog^*b&UwoC|Hv(?$*Mc~nUjM{oWRRk1 zaBpSs-CYq)&tAXedgTL`t-lVndGF7XjwC&&HdDy1l%J|9WM1NjA4I-RWHq63RhwJ# zhN!tr)5Aq~?)qL)?7F4jdYI=}%Nsr70}ZTVeqI>Cc49Rk@UwDI^6L=QU(H~ylZRiF z!iv;h7Db!DkQ?SD?va13-?wp5ezcw2st0kkTs?b>j4ShBa#TzJ$aPDaGsRjwpW|0y z7kY^rH*ayZS&V|0lOa{uyfI{sp8Go@KjBm0j=Bv>x*9(zEC zp@apJk;>x)p@T92K{&YG6SlupuG$-EV~amsB8>&A)}NGn>8UY5SRj%mCKrEJxZ4lq zE*uS*L6^Q@Wm54HpU4t;j*Rya^PsYj!V4Xxzhe&71JEbtIgwqv+jY2aN$N}TKU#X0 zIL=JYk{`piK)+KVt#>EH=IavR^goLpz%qs$R2aJt(4sT+Ns_xAkHF>|4Q!WuY!AJS z?wycTiXV9@c{YH4w+yV(c7f;sqe>z9uBupqL$wBL(MPPW@9-6wuGn0zqwEK+!*RSq zFI^sV`9QHN6*C;m%t*hcv}#HPM*f;?pIhKN8&ks3h2Qku!R{4b$!fUd$9PDWi}*(= zCkI_zLQ2;_WnJPQEv}>vtLY8pgWfg>)29_jEBD!>&!zipR)tj>;X}a9Or>O3h~3yB z2^&_cDLB4q@hZa}?%5D!LfDo)BIm@rtj>cj2N*cSKCOB)^=E`{@Xdnu)mv?@4w*+) zgINq=rQ2iXC?kZ#P$g&a^K6rEO6*Va{9S_#@A%!my@Q2V?n2QLzW#9~7rq1;QDO25 zC+s6%84hzn56DF<7YetuF8w|TRdr?gU45eL>W>&}a+=Lknt@LHl{olKKgxoOoW5tC z*=VByPJQRntQ9eG<>~yL^E#{!>U>nQ(>(T56RwV8eHdVl24DGo{FdSm=J;FDjhKD% zA90$wzP&Vd71&@Ls^l=J5m^cww#=j+Mn0!8|L?im;D1y9lOBFPB40eYa8d6|pr;ZX zeS3O?hijcs!o6hKe3RGYT-D=VUE$*#hR*R4uIkLzGU5Ut!bf`=e*60Eq_McEj8f6> z<}2;Edg)mOV)LoX+%Q@Y>&?z%I|#>Dj88!#f*Qmd$dnD^vb=jSCodD0wk?>{F~hbu z@8o4f3KOUQq9WIm+*tH7O%8dr9Wy>3+uxUT!S9K58RZ!=XV&h);=4WD5hV3Op#L(DE7NjIglbl+V!ZCv&Nt7O~M64btTqv48B}%Q${L z|IJ@>GFI$?XQH=(j=udYNf zNU^;?f6V{q;;VGO`l->y*%#?opUd$l{(Nh*&H2uG{l5})1s@w@_uR_AvCjRjzOyX( z(B?FTruzR(dt}FHV6h}MvL@wA%gq(Nt5E5Pv5gbs$+iJyf6trOat{VxzmDViFyymR zRGj(}V&ts9k)+YPNm!zMujT&iJI{cX9h)=la8sV8RReUA7F(cq=PjJ0E}(06q&xL? z-_VmYs$T=vSu}Kdq3?E>dGv=N8tfV$CzKE%iSzv5gPHl(ylZ_kXB=gb zy3U&$n87prR>7Xs_lF1e6GPuyOTd#l23 zMJyi#^Zae{dNJo>j7jwwaQ|>!n|S!7jlo#u_{>06fF{{Q5WXz8lYFi)7f`j*Qx$Og zm#<>urO`L^yw7zD{Xe}nyVeZenH)A!XJsli646j)Q{|+RRK0BMf2lN756~OTf!=#m z6hDZZ16RlC_H{k1=aaO(vqJH zOP1XM-k(W8oFVl<=4=o9V8A~r^TrHhmnZQLO&6Hzk`}f%YGMg=w_M=5*6S8;NE6WD z;BUU)v!+ZBuX9C-ASWnHhrKkGdYHdnO=%y^%r8P6g%~ddnSX-&k6BJGp<-GptXIQc zsf~v*LBLNyXrMdF4f{LMf-SHXB?<=CQkDp1&$lWy6HlJHU-pucQkdMlb6R&IHZ!%b zs80wM4U`b<*{v*g>@B}+41W3NmPqbpK9~QwB+@?fRORR?^t*A>16X$LP3~LGE%dFm zC5V*`QvH&(diQ4Y?7OGzaLoq|WMI6L^X?F@se7$K-7d8GM6;gh-9+3)m1y!OS(8zU zM1WUdo^&b4t&VSNNqnLNYDiTqVXffJH_~jLvL;-`5oOs+m<%`N^IxR`lax3?wFB|6x>ul-iae@Y0O7GPP-`QNaDW}5Q1*swpZH%HLTcTUTPM)t1-jJAp5-B-+N@zmWxj!_JiST@btM$dHx%jWxO z#>Kqvj<2BU$wj^cJY5)mI0OY0{3Th9x=Y-4cE9x~(eyw7^6~8MWdyBc@qIH*&~(oP zOnrqT@`$J^4E;Wcm_EhihjzIh4)EuRxlLb)#$v9ll!VvNhKHx8q^f^Z5<5OXxg2r^9t?<;n?5MU=>WMNv>Y+`tGY~(UyP?nl76Jc zcNgId+h3mrZF@ZtmcPh_Xemk?_y+oNoM9M*-T~*|<)6uxU{`xXywvm8=ax-&{SXbp1*F>Cz-vaIRr{V+;Jo~RqO*aez=HK)Bf98eCCJ}Dv;YkF_1^Im(y%|t9lS;-oB zoo;d_TnD>r*q!-kQiM+UT4u{v3Vw30^moK<;v|F`&w2L{XUGJVY2yuDymr{p%+Cl%idqj_65>1&^cva$gbjyOi&Q&!@rU22)GYE9hi3z1x$!QW>8?oe+HZQtH9 zttT#e0cXet@D+hT^hM%B4#Dth-|IAFS=Z?-ormhs2lrMU?L)H6;(P^%j_*Xcia6BV zB9EVP_>`pUMZaE*^t<5IxQ<~$-|Y6KNo-NSyh*R%%5m!_XJ25M&4O<0DJf|k!^2{F zf4=q+6-L5)cjAkk=&zgPtFib9LP}|Mxqml z5ZNz_m(ik|x29aH>ZA6=K0ci9;px%Z9>W^dm@k65X#UcpqW)32NM3@A6H&nRQzB~# z$-FfqKOw24#~vsMJUWBHlZPDa+nN6r2d`ej8tFA5}H075*~oZOvOt-0N6AgJ4eV%?TWLSq1?|9ajgiEfWo(ZqPBm> zy2sYiN<-FlqPsi7S2S(pWLHO&6n2^=KFGCdz`=P%l7ym9A<)xS|e1yU^GH%Nl#9q6Yu75|p`5%?FN4z3Cm>jf4`PFVdVe0d!wcxholDPV} zfY(_Y&6+Ef#Ys_0_tgAbUi!78jOjnvms3Wn9#L8o!)oq+ob9CW%R9S&M77=_TzQ|{ zY+d5^_i|wM@|Pb{-U;@@W0geADM5!lV!4NAuvxAC&z~8_sE4Es+G+WviR9&-uN`tf z%C#mv>xn+h`gCeNs}0XXq`OU0HAbvym4AN-q4%_v;;nQs_$Cu6$1-s_D};Mc{=KF` zQ_^0}$Bj|3I}l;3mW!TmgF}4--Xzf*&J&uX`0wSp&x@eKNuZ`D?;Uk?+F`w1!2IA3 zL!hirNFNEK-;O=9(fYXk%cQ{$57lCpKhkHgchpO}Bj4`k+J+m9tHJJiZ)UC}YNd@w z%xk#fiJ$&1nE~iNf3;U8i$!okF-OOl3G(K+fGW^TZQ9vrm*UxV%kV+h!M1)*%rcBo zcT{YxzOtFab@%W_+tL}lRwDoFCi6nvuRbf81Oup zd$Ihu+mH0ERFLV3#W(-QLA&18AJ=}G*x9<2itjBQxPAKF8Yg$VSTlEOR{P*<@23av zq1W0C%!?!MwbM~~^-KL5#0aj+R^F8Z;*OfO+JC;Rxf!gWbX zA7q$FTUDs@n06!Lc_yr~5?FQ2=Omvt?j}D+bSM@+H06WvRgbjh$E42lx_u0e%~YW1p3{3adcEt5+xobuI+-jr!WgME_QXp8E-sq_9>uCu&ZCSe+VYXr6gxu^4tVd^EqvKNnz z$aP(yL;tBQa}#HtIJAfPSjzS)UpcH7hxm8sO|RehBJ14A#CGp_*fdgZmc&Q2YW!AB zOh+kQdZjq~A#aqeXz?=qs<{3ZT-8LvaGwj-ZwDv_t&mv&-26-JP9$mQm(z!(EWc7G zOTbW6?;`|+-koaBc^F7EVI`xrR5nLw;-QYw_CBF*? zsz|z+NZh!%Ua?6P<@cskDZg)1F&ZB}e*qW833a!?7?ZHs29G&OUvp}~+YFC(Bc&;A z9c9~G^kI2p-@w$q9Oic$HV2`&T~HH<5oSaR9PuPREN7ub$&Er-sG?) zxH^%?TV!?0+;=w`v203I*b~_kAf_y+o(@llgxVKuQZC_yNC|*+$?sCA{+9i!+9`s; zH80Cv4Rxa9{Vw#8l2RXjcw&8;Eo=Pt~W%Sbv8>OE^N z({jQ{BE?zQP0=Anx0!ISIhpx1WA>Hh$uw5s?8{&4 z1AIdrdguF`K(j_dNps&JW1|>Ua(Bm}9Jdhp=O=EmzD{~^d9m}jtD5vU+CGi*J_TY~ z7>Ju(c1TXtK?`uo3r3~PrSo^PriXkgtLVW@adMQDvj3xEq|gt>c>#ctOJ7K(j*$;e z@0W3^@Q`E|CePdxZZ$9XeHdc>0lvI%&iju_X66O#`kmxg&znjgP-r$3MQu+~~y*cxzJr zuZjRm`txgZB>8V>-gA%t%t2qIWP8CRcimF=)x_LXfL!x_;_!^#3w!sLzuz}DRoRRF z7kGB^f78vV70s<@OtDTpUq2vL3NT`Cdgdv{Zu%QQZSHgc7iIqjrt=K>3GYN|29&x6 z`nzrcsL`Rm)jsy$2YcG70~d5ex7aaSa9M9?;PS52Rv*YIeMb1HpY=D)?G@!s($Hvw z+NSZU7m^(<=#06F<_So}x<^-&k;~0oC_$qWWFO5{^o|G31cnD}yGv(9q{e%OeHIxXryT$wg=_$!Auq!2Fi zbDpeP{r{-Urq6qmW2u&v9Dan(`5~_#BcpBZVQ`aCuj{HB8XAVhcJo_u=sbDsLyEK2 zwexbW$fM}UA4283&s6})K`|5rSDQGR1XB8wAVYhd`>T+xl+N`%w=D+GT@6*T8o(Z6 z=v_AKlw<**&#={&THIi^XOYfzNT^2rVGAZ!WQHWY73Y#2`MRUpK_ zs*b*9`W-zVoe!Qj{WVle*&HXfTcSL$v!XE~wR~xr$X#x~6+k zE<*+u*=xuSd_f-})h9c<-t@h3JI}14lLsBu)6R7RNHN2d#!TZAJKo*(Y7))48e9iA z*-NiTa3g>9fr=cvGfnIJe}!g3*{a6b$5@n}tFC3+9HL*?M^Ck{1g-qf3KrE@KrN9OJpzc$HF-idZH0&Ec;S2Z#Wq{ z-hzd|OUN84a_+I=RGjuGnqf02gi@C4st{50e0x-nuO(Tm=k@hqIXNBz^@%Y+bo7LC zkW1iq@El7jW%!I94@8H6WY}tJHD31P$TfznkOI6n`|r%efKB z!s^6MbQ^RgZEi+4|FCxG(O(eba#9&pdS6XMZ+zi9ED3UmQ9T6uaOu z;}#=o0ohEwc^-l;NECSZG+Sw4mCEZ1LqM^rrxDzrTz{;8#SpZKq&~`$WE7M1=ZhdT zn7>G$HxHuh$y*90XArrXCqn>ZlQ2oN!Y)oHZVjs7tu1js(d+5Y9-B zzt2ceqA9Lu3voTqEMuqskeu{#Oe_OgXVH5oJfC+j(F@yzNC4L@#4JOmZ&1b-X~jmn z*hdGTmmW?!d_7prTv8MBj`(FBy>}hlB0~Ka6`mtU%vyON)QTSpTfvQIsb8;4DVrIb z>x0JN9j1v-jN6w!DEcy6iTLPU4@s)<^0`BU?= zo^Rdtvp^y&NPg7i`eNa2%*Fc;l|s&iwiaob0qAN~RFZ5Kg7@!8X{t+5UA;It5yhN6 zqUOmuIORyaCcrtMf9?ULh>e#aoREw*uI4$+HTc4~qit(9MbU!#4EyB$`+-H?3Dc}T z)Uo7mN}^?g6-m$mKMo~)vk4xA6QCFPo)S<#%)=TOU%o^zK&vHq5_itDjE z1HfW==MIb|GES&)Yz5VJ1lXRmnVrpUdesqOD7(*0GoU@3w!0C0T$T z9~IO}h+R8`MyB;~h`{3!AJL>rYu6|JA2avXm*wOyQ~vU21+ElEy9 zrxiZ$Ud;8Vyj)jSe)XR+;TKQ+hTo68oa>){ zVb`YU@0-hbJC#651!e-`T9lWPX7rYAnsLAPyHe?bttL_yjYhwJ{&MqTu-}lF77nLk z*BwODn>4GXPP~Qp??hbQB{7u|`?~mrYvnvO^Lly9i(7JkE8Z1Y6H0mo;MytoLq}~G zi6Gpf9)2?MXqH&3@0k~7_~)kD!xH~M$@#iiK_$#dGc7(_lCUri2V+}V9+PubShf+g zJ}8!c@tS$avrM`y;Rg3+`pyo-@H{3evKi#fvJ|lS(PnIEXGyNlLA#5}A)@s-g*CF+&ogbxkIk*pr%dw=mM9+cC z{0{hF!U)kC7mQuV#(^y=#%mGmt`j{F(>2ca^MSR>BP#Eg22tmJf1CWf zvK5yLdqGrC46THc>bXoD*~J!0_v>0mk5f!+uKVDFl=P_!`+-5CJ;dKt1c5R094NT%-6Y%-i;6;2?|1GRW77+l zI&8=G%7i0_3}V-G7T?qxe^Kgtf1iUVQd*UN6sJyzz?t_lUU%hQPvbq~FU;*HG)<%y zi$tF2HYV-&dVF5;&}}%i2t;LJ$(T1S=0#9%5-ZUdi;BtN!jX2}y~|zhcho)q#qUqf z7)-YGXxPdQ0Q(f*3(Dgm>x+k<|8!JvYbgB@3-1FU5_+=ld{4kLcpP2dF#|l^MHq z#c)@05k*Ozetb2Qvo=brVPwahX&H);ddQNIaGEe(*B z00TP)j7s#^*Hv#o>0H7y8B!7qtI^0Zs$ftA!c{U1{eY&MUk=XIvFkzh>v zp&|6m>7O|(GI8}OKjWCac_y5m+!)Fe`iEaQOdTf|sq`!pw(&{4Hmgin`=~KTY){Rj z^f!YVaCGHhy+COF{|ly@AO2_Esc&ga1-!{1;7BcJY10SDp)@!wIc{Vjcm=W!&7$}0-HRcDRqpfKK zp7&{KG%t396`0Za24BQUxxS(KMlvP>C_h9JvdX!Un1rpHgd2a|t_Vz?*Sd=Av$wYp z@G*sba?c|Fz+zr08Q`DhL#9Gl~Z@bG~dLA4tZxF?h|9Id-9;KN$_makpyw5NtJg1(uA$cLu(F3+$Qy9O;-5vRz#lgK9S@@0 zQ~cdO1bKHmHhmaR?lOA%^R8Mqm5`)c4b{hIK*Itcctc8&IGtAa<@Hp&RnLQfnOQ?< zjL*}}6NUFreqCR1e%=_Gb)aBYb8_3W39N%w4ge}Ho{om{l5UJTi~x8o3x7X~AUamm zxhxm3SAY^LqMTbt<|%?OK=eQ71U{2bvM6de??j87WPIo_OeUpMNzO97QmncE^`Gi@ zZ9j??GdRVE1|icIMdgT5`D>FymvO3Gyylw^OJqk}Sv2-M7%v^8!uu!pjmWdh*Y5&g zo1ed%Gc8!@r>A58!hvh%xd_R{+yipXKmYy=mLp9T{oR2gL?d$pBIrE!ZqH||Cv6a# z7b6xAjFkXl!s`SuFdV>)(E$%gZ_R?H0jy|EQg2eMUk+nS^~e(Lc&+QOb=cvtr5T{} zySJDo1aS1C!ZJYAO75U{`?Aimp9j)fX9wJ_YP!7p4WA=5! zCmwm|VMv9Fctt~C#FoU!YP!*w`O+6p+2c==0%ypMEyPZ(!@8&3gES+l$hmv#86GEo zgAWe?Lp99@9FiiU_e#fuM)rNmK*3@c%+|$ChmQH(muBAUla+5LT9^(kx+fT%yw5eJ zT+SGGSr<4W2N(5Q+#?mjPYO8SpQco$Z@3#DWRlIu?+p-kC_rr?P=^85m@B2YUG$kY z^&wl%5K8kDyq*@5m4T+Lg8M4a4pz~AY}NV+)pox3)yMnbCUa<)|AbW^D8 zdGEQ8Gk0%7C?i}Gpwu75@dX>=j?=gw4?*{iCVl0~+ zi;Mm?Mbx44to!T`j#zC8@%eA*cL9x)@2Z1?@>Q8w@V7E=l3eXU$%!0X<7=JGO;O>RRGIZ9ad`SDj5C^Cq}yY~!HlVqClG;NTpvjMZ+ zHwHM_IiyeT!DjtGZ8fhPa(Q5GdRX1zdjR>lzY7K~nsDOU%K5KQh545jTio^qOy4;3 ztLsLyr3z$fKCFSt*Wryr{o_KQ2mggtJOdu?OQf3M1QtR()Im6a!nL&%HM$;?bU+q8 z%)Ifmh@)H+@Y=LifQ3s7mm_YcO0-+vmT8=)wv39m%S~OEoqf5`-zHP#{>E4KG{Nk2 z74c*4QB*M*cs!}eA}K%ELZD{t0G!$4@;;-&x;%sh;B^ZSS-`t?A?NbW z3s<-SY0-G;UD1>){+FUo;Z}O8ZkdwXUVGKWYXWb=a;8yNfWV<6CY*^xO$6a*mr)V6 zBQ;a9FW|~pk-q!q0ajt|gn~z_N)>vC<#N}|D^ShG;6!E@q!glEkHQ`xy3Dw%1)RH< z_aYdhYMzW7oqvLr{W^$Ak>YE!o$4#*B%GjzTJW)Pb6-Wi|7UG%Jla)dFb+$e&2j0y zK=o+QJKit%vURh^^b!Fyc~HRoaEWD4@!7?T@-zi5HB{zD4;Xhi&J}^9G5p#Jih-zQ zGO=4DNjJNlnce-R%6(GExvOWI4Q(s{Cka1{mvo&_emcMZ6^povSjq;|0~Q@4z)mp3 z`IXKvw$E!kbvuf=b8x&XaVFOD#$HS7nNm9@G<1W?NA|Sv+yD-o2O&OV5WSC0Z+7I6?^Yl z&m}|BvB>@WEkqHCPe&<=j>77#BHMB;Z(;8Kd=>M3#0(Z~3T!(cyJ7D5zRo_EyAFV< zVyw##amGwih2b{vC__Pt(r02)f>9j}1JG(28eslsk#1H8M1vMfuzQ-mB>>C6TK={7 zOnhj@>em9I@zydr?PLSb^S~GL9?4gB)C>!T;0mfHSYGfwzPlEwbHhSpetjdmh(-z9 zV(_la5BwDK>Tf)n1z#}!OJ{cwu_TO6niw&xKXv`?#`hlo0R z;kH6a4&v=YfOZoJ-Spsk=pEZR#PZ~0{#Cb;slgXb_l7@~PD8P%p8Y7$l{clwpy;zy z7r)67P5^YiM~5mOwsryx=jEYje%>0qQ+VyAF`wpf@$181B4>0zgfP}R#r1jX2ELSz zY5yVR29^aHXCaVuITd&6nmiYY^QE_8qp0ZoX6{B9E8*4T|`25@{$_W0;W*!F3*3Exd>qsdpnf}WS&n&O^XG{1( z?UVX+nTbYO&zyQWDG_qD1sW=YycW=`KZg49;ig5$&t7mF2ny-uZst%74O>D{Htqk4dhY>GneJwqG)G z8AG$=HTMMcq!}|y()>?f;$sEki~GxaKC&7p5tDYp3pdh+S@qG_*@(~ zIyTn*1ui$66VS%dzEVxJWF}&{;!BO68r2snr&3>{;?OsV9LwFM+^8-Hy9=7FzES9P zhH-P^w7p79OF8s!h0l-4(qiNB>H$mP-=Q?bVVpnK?5k%Uk-B$AGUk}acVXfzObM%@kUa3zN$whv&`;+~GQ)sNxLbLa-1(YB-aKvCrC**tfrSU43sg{iK|m*89g-`l%4%BF^gL zVO`qx0c9KisI;H8_UqUFqr%VZmgmK404M0Tiay&TjbDXC=6Mtg9i28O9;P3H({1?v zQO(<0$l?^TRnOF-UciBfyDmC&`or(30R}~lc%x- z#oou2SQ@4pm(RT1+%31+y4+ZqBRb{4rE}9a%@7-rj`qPX?jp_~k)-kA=!^J`q#YmR z4b6ArjTXY}`|;t~*eBY9SLOZK77Zo4CX1GJ>1(uP)25FMVzA<%ZtlxbK$^MOYOBdH zk27;-YeG#-`pG;WU+8mD^})G96#p^SFo%ur(Gk;g3&@8?HURFyLQy0M67ND`-gvv7 zhoL-jzb$9DKGhsv-g?e@eN{qB(Y4~p6$`y5V>;a;mNuOakh)JgF>z>acUF=to~=Gc z=I7dhedcuH>kOW{-wB5TyEm6mLA#e%@-lR;9&?q8!S21q3-(P-M4D)`IacyI^$&ErY-#NMY^7?7DuIK>2-|M|)SG}La1APUiH_s_E*Z2)e zi^HDAUsa9dxc8R4@C`HSDj($aJ#~uWkR#=q=luRqr(!JUQNL^IlhA`AuHsRR$_TBG z+Q(F$ncYh(l~VopUPPU94{)Uj+pCY8f6Y(TsYzzz`g97^)!Ih9FKmn=MA#TV|IKqW z&(`eABQ=MAp-_{%sw;EvJg(IQJg=AtHMY&0b6>A9JK=NH1pL<6!a{L$)> z!pg3bghuv|>c}ylIiyxEZGzjGE{wIVJVN{Ua!@SMcGMJqCjkQku}uYJbOnXyfN-*z zpI+BAINLGamXx~9S6DoMgp%gbfi3LGAD)= zTFuVtQOcp8POe#fxzX$E4Ct zZr6Lg;!pK;#0N%BIQZ=!=(aI+Z17HYfN?L3{5FZ@ZwI~+If@~&BUc~d3}YeVgN zo)r|S>-&-!(aXBELKfR!iE)~tH$w;iE6fM|d%yH-0SP4N{q&+glDWDO@CQX2R~1Aq zz7_nR1a0bnfBtt@SlXhOph*Y{WJdfI#@v_r zj6-GoRPD@TD4xPXEIikAS*$islmW0&^De+l5H^m_?&bSs4aDpE2u36ZydXe#j8X@> zH*N%MV52$~0V{SnJ9-=rbT@WAR1vDFoUbhJPTZGb1uwqx%0r7>%*j7DnP1zHW!q{hdd(x{SiR3xAvoUT4-IY04Tp!-Uz%HOSt zCZE5yjr9B_Lcb+?XVjbxOn3pG;~V;3=(vJbJmo48xvY-~uRTwSu`G-#tVOCRm`*$o zEc>lCXAN7;q=P-_2S&CB@g-7j^NrHIuGZe&D}+LFnF=EmeDw%=O1gz> z0&2_0TQt30Wb^Y{yRLAS!E8*7@7kSI9xR815DIbt0nCjzX$X)n4< zoj!j?G|<+?p&oMgO1I&{zG}0!EsyLV+=!@!A}Ug@wPRs4 zU6wvgE_kOnaaqw2rE-U=nlagE8~J%Httqe0g)nIXrGs;+s{XwMv>fut@jI+&}*( zlMDj{Nta6Gk}cuVIBpfS2K+^>m&$hNA*l`s}D`PJzP4OerZvr_i9V)C;owFlh)3Bs4|hU z`%G)c==?Rw1UK2$tH9BTiS_C(-{g+#S+q|)M5@Sn$UkxfDToD!!YfTZMy>s^)C0D^ws^tX9caJR1iWF56Lt5to!)@<^A+X%udf$@qRP z=7!!%f&#tSa$(>d^^kSxp45>2`RlhaM)7|lL*s~w1VQo_5(rCY$RQaeG%4GvU?f|% zULEXRtamBas{mZ1cyH;9_H=G$5Q#IpmUAXmVMCI+OKlfL2X8(FR?W;0^8cu&3$gW) z7&~{)fNg>U@z766ya3_00OjYHkVyVEit-_=wG4?4oyQ1j@U>Ttoq3Ojjzek+!+--i z$20P0gky69P-q4)%OTSvDqj|S6F)oMB9q7GJ4ne9Pj~rrapjfW>LtnInoX+pR;sf>Zr=li<8()wf|l{m8xX zV9k5q3W0m>9?gG=n02n=jG;$^Tr&}|aIKXAgnrd+K)DVpjy-n3`Nzd zf{KGQlSgH;lplTh344`zyEkQ)RRW<)nk457&jSA=134Z0`ojc8V0Uq+kR%cfD)c=~ z0M?+B(Oq%0KPUq=4ebQ;s8BmERwaeid;*$1I_mjZD%ln06UhB$=Il)g=+FtL#OLu`tMkIz z8@`w3h$jT!v7^NV1Q4=@g%j@-izO55^&|QC2{%mn%_6rz4|s<21&j9>w$1?f?KIwL zSq4#c5=mmts8ivXBym=6Hm!g56*H^959yT2c~jN1W_401<)-|LX8lS&8_NcAde&$Z z_{=6Sb-YO0V|gd;i3}Hp>=4I3F_81QVuv+XsPXyEfik@pvhvDTd?3a#fw~<-2Pjom zZ7R2Lb!Ej?PzAFx`xI;KZLcnJo|I_GuCm|J#c&QqOcX!+Xn76etR&W+U#J={k&NZh z*;zZkq|f%QrFt|UTA1Vw11o*{d8g3w97?$UUKBEQxU8Vb@qtJE-R~7HDduj>lEw!9 z2le*v|1~!D-~WYLpQX@w0l=+@PTY>%8FGh<07PI31@mXH-0z_#aF!7Y$2OAbD4S=6 zJ>N4g!0dQNv1Hr*IDPTf6me#nr-El~AM(ltiPOi#W0;R0`9j`Cf>?;R*JgJV##c)m zScfmFzHZJq`$l2qvYuPPK;5Uc+83*Oqm+cc+7M?XnMfMrmM*?}boUEpdgiI7hZg4s zJ>=~CI9Fm%C6_l6Ws@S&4~OA_x#7XP%K1oWtxN6B z;e0<_Dys>RSeH#9a9T=j_vHyxOr6?zHOP{3p6Swxh=?9XPCgw2QeUEopt3p+{7bhb zfclPbzWM-&Gp)bX>VQ| zUG=v;mJsB)+MfQbOJ4L(Mzqm>xurHofj2}TQ*t5i+`oh7&86>zrz>(w zMvA)H@RdvE{#ZS2;40;SiNl|Y9S(hc)W(;0>kwf2^*}p2HmzTh4Z8#v87J$lLY)pL zZQ^h#mm7(NOGMtP7}>ZBXX z)zPP?is%CLLvksKBni~Op4G>|*-Gf4hGSprKhG#7!|oMk2m%MnDq}G2-qj~gJN3S@ z89fOX*SX+d^lIvJ-9!oIFVVq@G2(7t4BzWk@M(rp_d@oc9f3<)ME_BFmuz_%>uk(Q z-&;ZI{;u_}^)~_CUB}#wIUl1iJt@5A6j$79nQ!+)IHTNZi=H$2=4%0auZ!8!C?~2i z8=C(0v*kN~eL=MbUkkPoHLEJZBRsptPz;?f(?yiaL+vMsi_qgcglidtG=I)F&^$#?B*&NlKtL|%Md9l5@onm##Gn48pYXuAt?uVily?2Ge;NG!Nvn9Loh-aL@H5%j`$xso;#oXJbWzg3?XtPN zU9nlJPm@#5_05O>#p2aep6bdcLD+R{){;xbOLM(isu(<|i*+kz$>q-?wd~&YT4Q!WAN^$}@}`cgL}!(CM|j98Sj7@(1S4;dpStB48tO;10XE%gescZraFH)ugNs+0;j{<8+`boGT5!7Yg6LtIYHA zU@(SKxm?-6k84uXiclYg0Xft_4;jfB;f?`Iy;)S`S#E;)dF)SKiiY_H?@R4w!$(Db z2kw$Q!EP$tYDw>MXq!Iw>65?6frvbIN8K-^L@VATe^7`eq0wpfh!VKqhFC#Z#sTW* z)*IS9jVg&FL|Rl4st3tVTvMi^~djF7$~NO}bAxW@U<6+4n^S z3qo3emY>)7a+sKG)7%lCI-!+ZcpNMW4Kc);)q1jh)OTm8{UsGW8bP` zn(npu-o_fvJ5oeuk{4h89r6KNi#Ip@1yd1W^3mlIY zL2#1{Ce|lwi*F}V`^rCCFj2pnd(-rSR}jN`3-&)W=DW@p?k*+D`3$*IISbm&eEEJ+ zN=jPwdj1e+F13L4kzv$7DyZa)Q%9y_);FRz77;D8tEiM`&px*mw6}Om5kAZUEEx@RPBd5jR9lsdPZm~YR#S@3oXsBth4oJN` zo+=g}{ciF{gh0c2VVW$lOjY10i*TdG3c?sLoc-2FsB(4=H%R{nC?`jdC8(Q-!B%{06$l4FDBxbH zz)+s%l}A+Ozws3kvrrNNzyESDgJ`}!G#Ow9-l-0?i*4+_z*qo1rBmOR2&dKa83>g? zw3~{%A0uNh^d!Z+juVb5pnF=-D89Pcz%vQ)aqAdEj~l$4LMo{^SwrCvYa@7sh9FFV5O6 zZzQSQoCYqRxKFNl8#TAZtqA1j+c(w7T?a#xFoeFx5bdA7L$QU{vVnl!;evluq97hC zu1CXP>5la&G~*A^+(^PY8Ko4myw4L5yEog0VO&kVIa>CmcSFlv?gJHtsj-tiv?ZbT z2+{@MIE7JdNY>4|QMf|-c02dl+bg1<1Ou_3d+)C2Ww%$8oZHCI)oO||{7!u5|KROC zgPLmpcV7?z1r-4SsZl{Gp;r+|RHO??kt#$4q&Mjh5>Y8qrAv`0MMO%ZcS7$)dhfj_ zln_YBv)A)GXZHN(?7h!9vtR5t%)qPxlF3^4eP7?}b6snOf?_t`Gg6M^!DWB5Q-q!E z%yfI(-j|N73jb$0MiCh7%ouUePC**zJ~O%)UOElghgy3TM~^^3SLU#v^MnzP5h z+icUP#aICQei?63apo!|Wg2^V#g5uuXsg{vXZQ4nZi0Bo>FUIq_5Q?DzAYnz{dgVl znZFzJE>8)R4!C6lQJ)~UFY0*5Ad*{hk2XHO{Zp1k9v*&LnsC4Fj^Ghmjn2fC<&z9DHDQz5DvET`GI;oY61@}cqlwP$+SMp*eHGE_S{0$Ntw;D+1L_+Vk&d}{X5;Zb?u=ZK9prmqX7-G2@~ zr&j|(8{EW~ei0+fYdg%TjpD*tnczWtkX6#eNLyF#7W>S&qkhBt%td( zBQO^E7R%o^7Q$BjzdqMiq19+eLk6k|;>0XQkxmRVLOYADnBTKo2r8_1+mN=KbGzBv z-oVsV@Z3Ul=R=kgwKf=mpJA7{-2Xs~VBG7!800e=Ryit?7ysGnx+fmlT_w7jnLwZF%^K!WT3kM zni=rb;z4MyHNG)4&IKhNqnG=R*mT*xj<@NB3ERwQl{R*6-nus?L$kjt^9|_NDne+( z@02Ht5d^AYfGwlxkE+l^mruB4`pz9#0U;p!M0iRDIg9D%QMKM5{ehmoU_Wp96y-5P zawr_kOd@z{eLXh^e{R@TS8hCTw;#G^XG;?>(Q5Jo!cqIo>K_V_CALdCH}IKEgzp% z2YC(jjmU4oDzQ+#Duz=NLn3}-9Ag~bSX9j_n--NG)MadNDOb0{!eVtR+1FZQ?Yf~6<1T=ahFA()`( zqX|=viut0CBF+Nwu@~PESKu0>@UJyKm`<6QiBCjviK5#U8k&Nt{n) z^QlM;lU{v(5bRebmfplWlXlcAJI8cK@y=F62DHig<+cTVO{~n(>7EQx4XC5EBOnwt zJlOE4h?7!$CTKX(HL$L->Bdviycv@m4@rpBW;mY0XD$@6ZnrY<5i8aSr3Yqq!P9vi zB04T^Fx*jlk>!SaJbgD0Y|gGae0S^cP=bnTyo)xsLi0aD6%K9NK)hljhWaZ@)@(AzV-4Z*^ z`xUp(dRG5!vDt81LbgDslslmnzMcJGd=BoZ-`hd032)ZnWbLO)j|Arq_7xZAAFh45 zJPizz7y)#?`l&asW_do`3}I^&Q7VVAAzB!>E>xh}bc2CI)M-p{F$CoF$mhp3jutYR zKIktM_0+ZBq3XF1vuY|o?wy^7$VC*Y4Bdo&zi<e_=W<#;yV1SQ>f7)(Ammd`4#nBo9h5uz13d{AYT=%8i$H4CO4 zcNt3 z1d>Zp8JCTZnaIOM1te5W9*3K0nQL*{6Jq4=Gc!x({;yPF;w>=Gn(2BTMN3QD` zDNnEbP3RYRM)R%DUn@NSgZUTm;Y{ZO9b5?q;5Inj(0VPKQ@lgo%v?Kd#*pjTUD|b6 zI#&h4qfL6uSSLw49kOuu*OpMy-CEVo4$RadqK_4a_zSyK!M-P4UJ%YZ<`tN)*yi`v z1p^4N9Co3`-R!drT)o8CQ+}M51h!nb4R$;^g^7UP<iZ6vMwaHp15dXlh0Tm#llyxA)q!r_g zdJm<8aQXS_;_N;YiMdpO7#+7RuWvuyy!=6ft4-k@bg6%Rm8|fU}h+<)NgEJO=dhYsSx3_jbTRGqbIj_ zObM@QLz2dm&uT_;M)$}geB(z<>3gd^OA{Zu%-7uNU@qit%=I5wF8%B3ZSSFO3`jBM0OOSL{{fw;3{-2hv@JUhUzpy> zOW{@YK`6Vvz5X*|@sH3TflC4ZUC)I6GxT4k+LuCeohNF8=F+%-`elj-(O&{D2|yT0 zD#OxiA;)2~{aNxQE=bnpOw7tt3I zvw3UdsbVci?w*K04w4%+?`TiZ!`5y70mwE86_JY5ZlApb4w(5J4|z9zp$`w6Da6m} zNIx47hea$0HA+hp*A_z`&TRjtL=Qg9mS}ym#$cr|y)lj5zf{R8h3}b=-b4@TRs%Fg z)_Z0u`A+F_imw~e<&{n|}`uis^gBiMe}u^>uf-EAP&D(O;V9k3{3#JnyfvimNE*iQQ`po+MUE zI=!Hvp}hoLA2Bi@$Me)bufT;9^Qh`Ed#S@Co1>tg%fo^XRyOQMt9nN=3=W)&WUgG# zB{9xEReuxz%lp30ljh?)92A)UnV%jOzkoHui^GMm+$)f_*fxQhIviM20SY6cT$d7S$Cwns8~Tp(ewmcD;4S_(znS`j=r z5%gre%1?90={Y*XwR6q3$2-ZU7EK9xt4qIQL+j}m(bS!MmN)-8 zOB<#fL<0E8X%M{P)n8gu7&Uo}=kCRKIQxnSTN{}LOO0-42$eK#C@#z9W9)OuESN7P~@{BtWtJF9>qqi>vGk{nCvv!&W1Dd(z`a`qKC;V-K+v9{bMncIkL8pwR&g}lwlZ~P}*`wQtI(iC^Cj#hY^c6o?$2lLF0~eFz zQsiL#@W{n=+4M(H-knnMPN18I2F?ilsr{`A1}Z->^}odnh2uVYDuVw|1pnT@uou{_ zH(gwy^E*;Twem<0yHqqh*x+#~n$?mPD_^y}{iYg2Pog2*UraGoNUep$v-86ipX_p!aj0;_o3f73DGf+H*dy;V3NE3r(e-8VjxF##`fX-d^FZDFK6pzsJUNya?pON7hCf8mM6*O&TN%B8S4fH{8ha< z`>Kn=!3I1QPK9!$a3mFn@!Jp3%!YmN(P0Tmy(K&SAnr}wo$|8J zR-qE)o;#Q7LG7@Tyxp3W*xMF=eHGoxz9@gpFMCZHbf@hH&^9Xk+{9CxJs$Ma)9q%t+uJY7Ex| z3a)$sxDwt1wcoX$&Ie=3JPsU{*`6OoMrOkIxz5XnTs;4w2zo&qcR=OSm4D&zSmPU-|}mIjTq}Js6Jdyk!Qm%GRX z9odwR z9fDJ3gRb)-^rtEkpT7^-=S7f-M|FzpjUuB^JF#ghyjJ`{JFJOaAe+_6#@IZ$WRM<@tsBNoYXb(CYH8S$`mAfPVB- zHxa;iczLj*Th>CIP4238l-D}O!L{N_+P3QJD}!c)-7)eBKr}MzulH`t%;xz9S-Uqr zZ9j@pW7&YRaK40vP3M>?RoB$SU%k~fH^McMq@AY+`h&Z6Ustd&=Ul3}kpbB(lS3d9 zAI3(Kui~Vp{K^JvHKYr^Hdk3+`*dY&Vne@`DfOtEDB9C zuDtfK*@Cnu-){`BEFs&{f#0p+x#Xg+boUK2=ZLM`)F&4b!e{R5=^QX*Z$p)ar0m(^ zI1RDMMd+%~<2jDDd0kH~E$OiJ>EBdIdJBB#FIAl0svOrUftTe-%mypTN$8yeY|Lfc zX{dBywrf@8a4XmDE!)VagCr$V z3=THFb=8bI)*CKrzoTDs6uVoJ6;#%lT#NpyYz|?0d=PQrTwSLua5%u=0ppH!ngPu= zG6A!bPbs2%i3fIN-mL;6I}w{ClL;uccj30}@Cwu|^xu&-w<^GdUbMU@UGTCkrz|ts28W0=1#qSjdlCitewS9IgNw z!G-HZ@Dor;XUlsX^`UGK0T85FVZ|H_U1Wy7mnARRQco^ewlYorh3x)I6!QP-TS@}J zb5VE4je|bwQ65S;?V-Ghw1kNz-4BIuaK2xa`X5|J?t|Fx+MXN>mdaN%)m@H=9qJP) z&R*XcMu~0&0pk#;?Kh!?CFrhQj#?4nZKtG0kzcal^|9G9iFg(DY;j4|Ld2_;3{u0@ zL$_(r%0biMbl#HELAw~o1^O}J$m)JYb?JLeugDqcL_vEhH^x8Fz2a}L*C4|^4Xl9X zSitflF^-TTX=6`Y<}R&+!3T`9kv3_Iaks3g=TP?6AuqHM!G7uFtNzPw45ZsQbVoRu z&w=Ax-p9QI(dVpxGyznrmWM7bN4P@#fzb>M?7=@`HthOu)C z&%8U1{sFjX;7={r13$A0WJM?l+&J~QL)pDLdhHx+a#7GIPX0?4sKtVIHL}d+Hhn}^ zw;>AS`cHDr8{PFg#FC0_EdAGzQ!_^sSp+sb9YMy*HYgwdMgsvR44OZ!&8#Ud(-ICT zOR9|Y>9wDDs0ZqUHW+>juNb_XfcL)m4MYKRrZ+g@H6|uH$rRU)pdY+XAK24qSXp`2 z_;=26CZOs|Wr8@dRQOhcG4c5pN8YC-J8WL`uEctAgn{Go%%#gzw-H-V94JL|20tB>uohcLN%HvD!hNa35 zDc@htan?-e2y%j~6a4b@!F?A+1bH8}#k`Q?qQ{9f6;)oZTQmGWy%r2^4 z!OB(Eni+aaS~nQ#AKFsISCruf@w$WpqM{$N1$dVu-JCAcS2(RbZ0{$M-HoQvYwA9) zA)VJlx_BFchBc>AU2G8RXY-mznN17&Qo~UDHsTAS*Qlj;Nu)f5 zqIPah;|>);6L$gLba*b(;F$yuays0#_~sCR+E%;V+*v|^omuxdK{rCfbqf@w7E!kme+?%6cJv4v-?!(bO5Q)R zzd0jywJ2L*ULiJ_1s)Yj4cf7kA?lOF2wF?JSN*IzU<{%wbqzR?vB8W=Ue=pm|L_PL zjW}gk@96dCXGN6R!HDcz2~WNgvJQOIQkf+23Qy4aGGI)t-ecZr%vZl3M{kord8_FldG$}bk3?e6|;T}~j9gXcq|rU>tTjAQT1ns`&lU{bh;WffMd zb>RxhcIC6zLgd0`a#!%~zG;te=>`om!INM-vSwtGrkoj?&g_uT=|YW;HdC@2(Lgo7%pd&dgYHt8`f;~_gbtbVU!p1 z7bVy#GUGJ@EZ0C$fTdItcv_Ta<`bWhnEr0y)IO5T`Qo>Yd~o$Y#mXUPOJ5$WQy~Yr zzR~!k)#Q_BG3B%!E-H$=L?~RWc4Wa_tDtVxKl6I01Jqkz9J6ObG~W2ymmWsQO1cK* zn0(fYerV>guo(($ze?}({Qz9uQIG>c)L0?HAvD8Mw9uB; zXD)Ra(9=L69I&WHY9KF43Fo94SMFk95Tadt|9+c{noE~En6O*)g|ZdcePAMF91qR1ssJL)~GJc2y_55*;ERosKP-^`-uyp~uAjoZ!{ ziVjC-?|$7VteHF`bM)cDNVgQ0!`d3C6|ZBBmt6C62@5 zLh7oi*sb9fI~kl1q(iYxdwbM}I5b~!JBlw)MWwC|oqEoORep|JkH(HDmk@G2@t9jz zkRvdkWe`6F>L+;YQucpf*G1hshqy~oVG zHL*C)@yNo+d>YTeT%-f``0TJ25>7H^&vi^@9aro!mLZe@d#fiO2HT(&{7t%4J3en$ zG?QF-QHUij+`OX}*U$&duE1Oj!U|U5o)O=!8KjR)P;^|ldTzJqHbswjB&eWKj3g;6 zcT8$Qz9;u+tjOx0{WGMOE03-iwjHiQ1U4|uP=quIMmX`sbuMkRrMo=XpEc(MRVlT3 zPBm1|gy)3IGRwQwk<`W;p3B|LjY@j1TVG_IYkA=;q{4I!dM3xa{49-fV42b1li;Oy&^%z2pDO0sr@jhX;>` zVoC8t!una`o2$Q;XJ68d3JB4YIsg2c$16Nsska|Im(DUqNIS zbVyY2RtkFpGi`f0`jSi7GA@ERpC{~F!;n(0FL9Qn`zi*!CVsQQkDJ~k8mGH28g^M> zkq3O8-rC2Bn9dvW#~s3U3y6g4exq0(Gkc?@k^ABY)FCzoTDs6S1G>4L$sXH*qV|sT zGR>*@$YvzR4i>7fnX02;VX^`}?7COy5&dh9IaH&kk1%}NNoKhyKspbGVs2vWKs1gV zH$E=;ey(Ux-i@37L4P-{FH>1EsI@G)*LABBW5@qR>#oG&55A}XV+g%TkHwAJbLkM( z+X`ROyoKv~F=`-%|@beQ{w^Rd=W`}ilTo96VgAo1PJ@aqWb^KrN z+qDoUHq`cXiA?Z70uJ|kVukG^f^RF$(2Qy3XPAq70?nVBq_rUGo48+}N#0d(ta zBc4XjYh`X(=518{%ePmeJ_1|f!LZDmOeWi>#8)h{i}!Ma}quVZ=0FeJUHhNXz%5+c#!nv{mU?Zsqm~D@SL)A?eoCJR}Lx zcf%7ktX~)N#nO^5gGY+6WgIZZ{rP(#vcdyxuU}JIItg?u_^)GPs|)7ZyNK$}8n1h) zXLUB-FQTkq?_p)IW}vhH^bdt2CYpbx^5d`VbLaEQJntNx_*c`@-S-xH*LepiV@12V z3|)5}+&kp932+sg-C-kQ&##)o*vWsLSG0&5Cypc#p@?X?wE$`a7cK0uI4mnbKXG`bj3~-y`Mam~{5hQ7)|i%gvwig~ zJ2>Nky!A1c68nnNc!!}ADwhaMw&hoM3lW3=E`WnAm}$1w2?Q5GWXVFSl|$^qQdLF7 z`1X~o;CruqgdecQU3~>_Rj8SrQ$@6yYgKoOm!fjvG#()ZYU~f?e0&VbqPs2Sty?t< zvqvLHOc#w%R}?GEk7xpPqVU3}p}~dwycOf#*CjlEIbMD5dN)Rc?swMePuh9jb(b32 zg{40d#CrU`ecvIUjDsJW>`s6|MH$J35?@Ank|BZ&( zmrJ_6dIFQhAD5M@(Rme`w>G{nmsa0jwl+5~N)gBFh0Vx)q;pOg4N zL1TKDdqC@&yUA}oU}Eo|p*(LWSdVne^onb~XoH0@}9*Aw@L zI%a;B*2o1{c8|X=t%;j3k&a&CWdw`J@usrd(C$s(?tsLsAR2jPy)ZyuDYS zdyTl~yVKQwxV1_#w^Q_V49CK;`%cGUY4ZtWWBo=0HoFs6aT-DjBtElHtQ>O4ne+?P zFsS(^qAu3FX&y($DY=8UV3RA$VV@OUmKX@iB;7ntZsX=&?oa)9?m1ZN9ZH8Uh$H%s z(TUwFMz_bzv@`*`XcLLyd%uOyS3v_^GZ*+dw2kQbnu6>2hmI~##EdaB2c`ZiseHud z%nGu&cjJE->mc@>)Fajeb(C$Sgl_izmVcf15FLVCEHMTL1!6OaiA-A)w$@gmPa1$= zxrWX)*jHRR)KmMM9Jb*82@s&A5f6r7;i&Tes1zJ&&*D^mPiZ{t5ymC+6x5}W305}t zdI|eUm#v52^Zyt8b@;yw3W2HHe@1Wr8(&uHEf&RS{0`~0VCjONr7dU;n)&ok(Psr}iu;l-g2*3?kVbNFQK znV(h0_y5;f{r`R)_zVLqp>yoeB`3ISj}^2;^v`_Wo?>ik>;RC*+X$3vc4RUU5`H)# z8H#v-R)!dB?uK&vR|7Wsp^9Qq$%Nw_*x!(e7A1oYpL70DvKX8{RE!?h?RKA>?|v6# z?GLe=L}0ng^aM@PEl}5hK3}BW!4%b!T3ETZ?jlcJ-i%-R-cw+W8hJtV)Nt-H4da(^I_jK-ZGTM|)O&>@F;9@`sBm@o48l;MAMLVg`p@eUUR!QI5_GHLnVoT6-+6(;jkVX4 z8yOK_qcf*~`yWEMjs+agWhqez@J^bray$7}S%f*aj$+O>WQgN-2AYYNhL_=6y-Pci z-~aYj|Gydp3z2fMLH9WzW`kBZr5x4=$akaZ8Jm1+qCX;=9$z>pMaFEjER?+ub>s0v zum|5W-~9U?TJMCXddXm&Kj_$cHIo|t)&n%(j+*AVS-0q@)>j0&T;u#_%M`@yeYG4( z3G)k`NG;3~HXb#O(^^r#FpgLdH8s-8g1jCBXuIjoP{bwsMoI$jTewVdP<8LGJ_?r^ zo!#&MQ2Y$z#BfwBp$P&nC)yZdAWXQ4J*AvfMX9B9Q^h(LA*s*BV@O}&rPu=+@zf+yI&3-}{|g7*lfm_LF2lliA>G*yMYkU5WMq^Fz&+V0(+R7IYhTYZ z7!v8o^^Kf^i_r#4>mfmloF*b9iC?BFG8y6>B`qTB7ER8uL>`3IPR95*;dduc6zJ1D zD}lLyJOwLgFDh%_J7?{fT+SnKVl#owAnJN;Y+Vzy zLak}1SAN+MLD zK!hNgB?!t-$4Cx1wYEmiDxAv3hhxG)p-6GC1mAD-(@$PX6!>;m^60!gYFR9_k&Wa* zKrc@Gg)1-9&*a75c7gO;1!kM|g-S3&C0uffeJ@Q7=GvD_%}tUM$-IC98wD#%2`8Cz z?|o{#4&kn~pVJJA+e@2D;-!FBzkcd`+5tX$auE%+7vaSF5GtS%aBb@LgRlw_$a)KY ze)7^`;YYz%mVF7rxKO~RgPYe$4)BclLbAnHoJQOwn7TOuV==S1#&*~Ib33@cq`BtyO2{miUV7SqfcVign zu;;5Uz3cp5ecP#al*a^sbQYq`Auw?3@L_-*%Np=djfowGKPg=zsr{??S6NK7vOfbc z!TG^n+Lq0jgVbTnvrS|g+H(Zz2wcq0wt}bixzJG?kT`u09dGpi;Vc`7-u+wr4+Xa( zSIOPD##xlWK{I;#fYDrR#&oFavq?Oys}oj7$)|1j_(FFZN|%HkYd|U|jDDG!Nr@G1 z`Q>m*0q(0W6}yKKG(!zBJbPo&VH5L`?pAkqzh^$xv_dym+u9XyOvS#HoTBrai?*qw z)7|#pjsaDBS6AlD&BuP$r)yw~tJcbQO~S`Te$ea(KS6J5;V%R6Q`dl$cjz&7EZ`>! zApdGcUSi#iJ^F_NAin(bw}Ce5T{>{}VaxxVulXNV0fwenf~eXwkeb$XD<}g}mwZqk zDa_EtLE^=ReRd_WFMs20pN6xZ8k@#LC!n=#(WRT-Z;pEw`8NiLpj(&$k*^jkA>X4e zyEQ)YL$(=ncvVVH3(tcZB`lJNhC4U9+;|U96X$QQOMPKbG^l0zOBy7w7dcsS6H1o8 zdA6n%HGa-Fo%8=owGgx|bUWIocbYl;e_6G8o7NXCMik4B7jv_3_ zX)+;ORUbB9R1C)96MH`MI)7P^vuf^S(z}pCG=s{EgNd5(`=c_*YlH_3mmKDAkKRbS zfpQY+rBDf#57v%*#ui2q-JoK6Q3G|_f?6L?Y+4GJVK;Fy`*puAA{6{Zua`SUa%%9h zUsCsMqLV$vf7h~JjHN_2zx|2BwCU3Mi6B@b!9hsh;>5790X@Nbs#`UDm$&)&$!1N=hM z-`Q4dUF*Bq?@Z}eNEWAW-ucQ+m0!=F>$undsKT z5P*eF#o|K=Qbbut6bs~@Q$W%(=}A0&osyJp43o>xq|z>niFX@)R0qao39#v&&Ldb< zFmu$gE*Mv zevtyTUSI~!igmxq{bB{JE4m+y(`D={}c23 z#c_Yi`u^uXyV9a))^-_foldQIuS)Zo@b3<=q;U0SU%5X6NGikk7n+2nCFB%mYf9$b zi?n*B+|H#U>!wG}@p6&H`sVp3T7&oBy6;?Z=H0)75egY#s|W%P5tow)+(a2b>#L*u{J!w#UbT0EU$eMLc{%gHadz7_w>1|pD>kI^;ycSR}>?%Ua z-UmkW=Fc#H{Rn2+CEEm>oY3(PMQvi-t4NvXX8uvG|p%%M4Gd$Ujd6sBEffsAwnkhsvmjU?J67! zM0g0FJ3pIivSL3hW~6sx$~eUMF8m^mU1TAIwve|G4=nvKPliKde+r9Fn=5}CmUjQ3 z*v;VkPQ&ea@N_P}=d++SqIBLAnbASK`A+8iT27k5yr5Jx>I=&bvo1dHG@A3ydw+B< z&gpdc1Uec+t3_m>OEJl+3cpi7b{yENz$E9-@6OLypLwQfd}AKG(__a~|IVa*$PO8$JZB`{)LmxI zA;dR(>Fz19n(|6MFAbl*YUput4ZL$*O|9{4{K^E+r_~~)q=(JDGL4zuLue%lk}q%b zC6ZhrBJ=e_%L5G#({tISCwnm$=WMNV z>7_LD-|biqE9%9BV^==_9vCEz-^NGplH&}ywF}epg{$R%5-{&JCJ!iQ)+C^s9)Ct< zlTFx5Ho<3(2%&8PbxGIHoWE+xW#v40Z|2B=|yGIMBYfjB9Env?SC*Kb)sOlVNbu+eM zP4iP}sD$1FleV>*3!j`pDb>}UgUG=8c=muGS=YS zLMn6_lmkVRWPeb#RlT?%XnA?SGIoF`%>^zdv+OhZ(ayNo4CqY{T)7qBZvdg^Fc&17XeRDReskbr6-@fLxqHzwYA0vQ}Y0dV9U1 zkg2oYSRc{C%a>q2RjR(aZ^bjbU=VR8D%rP^ZaojCR-Ss2Q^XysMHOI}=%{nhSHfNN zx2I5>5CJQl=OXW6gh;*H-nGpaoke>Nr?-pBvDOaH@P70~KSU>F@0DXtUl_(WrGZ-c?!Pk!nXC_As-BIs_SZ zMWTeSE4v0!677!Bz&PP8GMGo2aCPyUTI;+luKgd1Hg4q?wQL~!x+4!)*_Gbd{&?d~ zcDHmic4F#nO(h#+nAeuoC@cut&B87-dakJ?@$)e}Bs!Z|{Q`1Itnd&K^*4MRRB+^& zm@8RhBuErE5#mJXjhh zd!(*iTgl+C@sL-zbI;wM+8@2=oSz%|8TU23N-vgmSaZW}f!ml{s1IsC(l*F*&6i7? z`RAI|G1|<>v6GKkXG2ORisO}YCVNR}5BrSQ7xR`l)%Ln26=A)FmfH>4{Kd4F%7(z) ztlPb~qTY=+H`NCjgP{5)&6UDCl&v4yfX#fp3W+=K28shH8ZgumZRIa(1Kwkk~<4@zaAvgSt5 z(xe2eLI!j^+igvYmCZC}&-vS;6->+&Oa8p6anHW1L+wsB9FXF&i6HAN|JE_70aX0GG<&lKZx;SR=xF%#wBNWPf=;{( z8sgA1?@TiuXm2KLZT&3QMU!NSIJXWS&oj)IJ=vq!6S6*Ucd~ zX;qHjQD(AiwY}ym$b|w2-}_0DedJmsP_%kQ?ppE*I-%1r-wZzD`zV|9UZ40YHc;IF zgX0E7Zma5u#DSwSDRBFwBK@28!Nb*SB;RGAQ91Z~vV%(F=8;5|pJu*~T^k!ha%f+r z-lOOHy{K9w&vzQkvHN{eQ3F z{}#T#wr0Z7N}eCuE563&I~`PCn(;N4u?$7ru0J2m*LKPuVSgFc^s45ON?W8S`NRDu zhnl~FF}NW!n)#`Y?##KOJd4tftp@Yi2p5A8h+(wgK+b{`#PQ;LBR#aef%iGqJ2u>E zNcxw|l>@P&)wfn2T>ecV#{1qf$3bCJcS=4!9~N1c#mA}9u^Lp-iOaj?`d2#|E?Ih~ z&o6`w^l6(8GSCUSAlvE+2&%1Z(?N~t=qdW@qT<&LpXu$GW-4FA&A!d82{f&slsRly zTKkdEd-Mfy&_`yhZJ^#=pNo|{jSyrv^DcETPf!8pv2(BaS-tqjQqFYfFj{8AAY% z{@Ip*bB(D(9aA)_C9hXES+j$RosLAM$Nz(_&|Z1cQNE7=>j7ePS;)VZIaZN`zUm0* z!5>f&5`O+}x1{pPUzOXSBnpfFt~XQtGxA?_=u7f^>Tx-qA$swSx7}PsX*O+*csgo? z-Uu4RN6n>+Jk_?i7qp2CM|jmG5L=H5@W)jf&kjpihR7>a$I|EH%=*TW)kUwf3W0=y z|KW)LfAVMGvqE6)nbIl-MK@A~Zr&L-ejHb%PVDfhMM8Z^msKJtNM{#`GP;onRzg_d z%0CnzL005Bpd!!H3$P3@ettuQ%&HrLRyya_5EZdFPJGryR-?q!t1ZYQTx0%khtdS$ zWG%s%3AcJZ7ySbAc%b1VgB*t7Uufn>*Sf4!ATl58?LHn~OO+m&L|tD4ou?9V%D>12 zr1}L)5)8W$*?4CYij5}(KF{d&xBjEa7wf<-Fe^K|L6c93KiHcgK7&&ewg8`Cnp@LO zpbJfBYf7nAs|{4w$`p= zeu8yAoj|W*7As`0pvq%EqOET`q3It-1u~^f_>sK<*J?BSYU!Vg?}{$DW#ZN8k7u)^ z#Ld6zAkCceqcVS8xB~BAOxuHt2#Da1J!|KM)BauBb7Nfd3ol^IVZ1Z(VNXmHx)@KE zmMvnBS%5`oyz}pzw%$7E%E5~&ps3;WHGyKcw&d_OWixYaJ=Lp?ORy>kcqDE6Tw$+S zXQ(=GqU-HYeHPNvPun3@Sr8T5!{+n zq))r2s6Y1nXZgfi1T&D5XuiI+>=ixN(p?^MUt{39gZ(*w1pM)^sb4_Lj)AxSp|aDp zgwnix!|TDY+;)3py1}rD(mf)P-=bvHbw#o$x=mlv?!zQSL;q*KHRnfEI;)3AD4(?n7AM0t5$aiWcj+v*)XApOJP~mqnsv=jxtz zvsQ}TZ0AMX&a;{3{+s!|12H?In1p4()=H6E$vYCf;Ih8B zKji+87AboZIHJiY;x0*W#Er}|GYfx&wP&sUIb; zePOb_>$hLgirHmbl*sE2a>H%3j?`16gxuxqSkOI=(YDF8kuC;&n@(bg5EiqO=R z+@s@y>i(Rpsf0ZyLE`tdunNSl`ChnaZYVOTxtl+VII)!BK3mYTV}msGGyMMNL_eU? zX~tB=!?k(!a$LWSMz+b!x1m|8^&2XP=jj#D#%HCu|1qI-GMvUULO zcZ$^?J)8B`(vMeUYqjLUsx<|<0R|=*BcZkr=7?Y!bM~6K**chsCtOy!g3-N5uRs7H zA+53pF2uVez8ICs&en0aD4#fAz)ErHG6xyeyDh);eR>l~^R|3cB8e%;^dyL7o9FTW z%60w!FlJMd0AE4#J2o~9Ey#C1){+xBC#y)VAmn4iG#Vx#0t79s5wEW@JEBpmqPV9^(I1V0kbaA*p4L-TJ`<%8ZQrRH`ayl-{y+xjGS zmi@G{*~*yclr)Fy6H;<_8pZ3XN8uW_OJ9Ffj}{lZ@~qCNc?g8cdVm+N34jTM#2CX?}QJ-#qRe1LbUpluU(|@mOwa%_nk%EIF15# z{u^uW71VUtfBT|{D2S2XgeXNonn+VxR0LGINH0+k5ke7Z0RmA_I)sjNl_oXx4xuAW zq(i776s0EA07=}x_dR>g{AbS0o_%p{xMGGG^5iM&yVhrE|Iqb5w@`)H;y!nhvWmTf z5iM0ZM=H>G0v^MVnXLuDRf-Yw4;B_A8kjcR?HnTT$fY_u{SN8S8ySj6+dcF@&cu<2 z7^U+fIK{15KhH%hFU~vX2w6i(@8*%n(kCCx1~AW%mNB)v>=Mzq%$J()hV0+bSL|Uw zK!Pm(6U2n*VwTbkDftjAM_0gKD);6MKQ9y+wr_IbmGt1Hwqb}xOw^xm#4bt?$(?r- za-J;WE}j@~t$Gfrn~Oduiv6SQ1QHGd!;jH}GS?`0hts5vL*L4N#Vw4Go8y#+rLOBp zoffyqm^^8S=nWSkWiEevs}*~iIUq($OL>KM6M#0Sl2`H0+gFtK9T){?OKfF$T|{o8 zz+(%A#am1@F;9B+CXV%fQWZ@hIg2DgQ?hvEZit#h1EK80WT4!b)OP7%E?1WsP&LJ7RGNn7CAyI+}Psa~=8(gvCu&~KLosP`v z4W@31+DiCUhC99`ts{Aqc0k4qIOB%+eS6SE5B4TvVMgf9pZdYdm-x4H zTI}h7zJMG>NEadGh#G*3bZ}TjOwKH|U@|#+^G3T=>9Iou*GQmYbtqX6mR8U<@Vy1U zj3S9SM5@q1dQsO&4@i;{WNU{X?Kh_c8WSi23)=8S=UByorVCe4&&WR+dUt}53`Ljs z#AEy`Xe1uc3K3{>1=$sXg<8~rX zabf%gDG!#!pn||T^_fdeNb#=Y6vRGZ0Cd@CxBeqk4cV?&`gM$Y7p|paJ*1lbS?=6HR}Bx z&BW<>-+0Z>O|=iuzioPn=LX(pS14}ZFSC}+2)x)_;d9TVdG>tW$d@IQUuX}e!e?7- zNja?aFq_WW>ZGv6;%D9{zFy7H7Bv21Ki4AIAFN63=FzM9=E#3%%nPO+t+c!hXEs?@ zjCym&C+f~7)V}(8_x%+y)#4Lmgii>-sKfEtCr|vG>IM{Z@z58Xg zUc;P6Ow!)F)KfZ>=Vvmh){8=ba|;i-4CBB3d)G5S^g?|yw+djHb04G9*-)(wHJdGW z5K=xOhdhPe_mQCsY*S=rf-+7dxcN~K_8*M_sXfoC@69?V&28TsMFCs>XA#sw*eQz9 z@I}F3EhMDk+PjSJ9TD62fkS+?*|Mk=m0N?gpp?A6sP9Dlp<-O{Y+Jxw;=!TS%c;HW z2=mh0>^RLl<-h*f{_#r=CZ7tprz=%F?5-MZefY7ZJgS9v5o1&Fw&a~VM6cI$*K-vs zS>*gdRup@F8N>g4&1*98C}!qIXjG~Gpv3r{Q`1yx)kw+CcZovq1y$)mtbYcZEo9fr@BLUJs)dzoQnLE$niM=N z%5Dryq<=)tOqZHgi>L{XKv&OLK8{}>v+O!`zK^UBzl*_HB6x%G{b9-*By{OFXFqxEv|C}Pl8ZfseS|E`d>J$-rU#(G1*)XvCY<<_&Y zj90|ugu1mc{HyF|TEyfSJKpL;!4bdT^*Pe%O}P=~dcw$op4)I#X9|P2<*TORD=!?n zOlVvzy}15H;JViCyO?eZ1aUF!;=gnejia0&hMn7tcn|M1;^{09u_4V5? zA`)~w18)(!Dw9HJgan0a?c{CrS>di6FWy?ZA6QM5{4lnxLSc=Z3n9@e+*dRmW6L^& zzN^$cSx_K!b_t(d8110&4p5^Fw>FOD);~wqQg0JHU)i523?9iWMMSGWmp;C$die5V z)JN?T!TX0p9?w3T9LpICH1cKDEUPN(j|q(z)a>U((sFI})K51CJpMP&H*rON1wML?}vDApA5e-oNm_tJ(!cbuDm-H@KwJQz9xjBU-_KSFL7y5;(ZJ zAPOD_Wl9I)mLBN zKb`+GNKZtxY;NDvyPdCe4Q2AqG(}QO_dw05g#;|uA2*uP)^RJka`#>vzcqUjJswYN69O`|7d=TTR_7WnIwfpvn=>sS~N$>=I;A@-4>8wt zP#7mN<-qZGm`$UF-&-OhAxyY{6g9r`+C~vnUwCzHAK@xv4tYoF9F9_SUNow!9lg#3_+|2^-Qod7J;R0;Uq>pzU zCt3L7eiCqe6gu0zC>^8hYM0|T72UrRR#r?7Zkvg_CzsI;msWgs~3xU{rWD4r-umHVsj zB?#lcP}xF!Xe%)ESqD8b=-*l4}$iZO*`i(g#>_dARx z*^&mi)l}fJPscBqv~pD};D`3Vzlb)P^6h0mu>%I}g^dmML{z8Pw`r``uOxRNdo6PH zzVG@N9c9_R|J^;+t;jnC5g83Pa$FZ>340MF*4_WU;ORw$J~RwFn;sA6 z(p%r^v)q+n4nD++((3)cx)|u+`2Wz|XhB_yx5l0{WcqzifXbk*Ik67zRNbW=b3p=A z`^@on+rmezwJDHixDrXFM2F|kP7}JzoMH=sN~qZNi6WV0J}4aMi$Z{qrAX=4yWKzb z&PK%|gc16izMmBa1xo9{AX3g#f=w0PMQX}oijh&=yIyyUeS;R12rgvb zEc9}buWyWa4d-%Y5kFslIILqpA6vK0Oc3@uA`}v-;gph4CbuJ!PvHSX5ghG*!AQfM zMVB!&<^i|a^&sAF7e5HaJXy6SmU|u23xs+`Yd6sujwgH&J-4)0-(m?QEf2uVe-~IL z57Pr6rW5T7Cj0f_W!{I(uDIdywGYbweOxh!p8u2gELY2Fzg3TL6>mBhQ1p7M%>TX#lPxj!>ybm0I#H`9{XO=R3xKZG zuyBhAyd(2LYWa#%+@VFWlj#DKP1!eW@Dlw9dEO>VR8osi)>sG}#~ z5ZEsAlg%B$GQKZjddG=p-31PPi&rysxb!^Yq;Q@U}F- z*?RRm@X9oTf$~MFMpbWN*OWRv;pS#gqIGO<7ovJ*mL%-Uh)OAgEd_vV#+#M>+zuMf zKQqixPP}s)f8phXaQ@dOX&*eElLRdwhnNQN!KLaEw{IQ7OQWQWO*bA{5KG90XUmx zO%Z9zfGAE%@A50Hn;wu*dwi|K-0Cx3>X&50zHYfK?MMf}f7q^pmh+dM#w>rFETd~S zawKYSAR};Pw%2|Du^ip+nCSlC2Y|*-ff2g?^V@>WR!X7&sf@a)mr z(`DOSHrngsX`gGePOYn;nqys-&ZR)np6>Agl^qXMRBfp|Zg{^@2!2Vv2_RNFw|GiJ zT3h*>NxB8yE*^P9g0m;Lc657i4$_oSdb*}5Yl43#^dcv&t_#FV?Q#EO2oLT`n16T_ zb_oXGy(tmfE#P{>to7^1odR!PE7Ly*`6rQwR}vRz$nF<6PSH*YMEIoEK5 z!~2?a*yL~IH=yRASf>7M%k1i1yXcwSw9^C}2;fhi;j}tiWZM976s28~sW3JWz9P<( zn?X>>ob`BtAB?eZ(bz!55iE~Zh{GL_s6Zvsgj%HCGM{B{++d2~e2}2N{4u%7Uz#yy zxgI!kP)7~K;ca~{Tm!-~_wT7ZCPZ>IXp%{l+peoimbE?`V0^ZQsG9E?vt9Y$-x|<& zwex|ai_8EBT|3%u9k*59vv9L6W?@OEDTTS><%8h{^5z)kZT2i`Ic1wSk0kz-$QK=w z1PZcOyd##rcNq{O0*9sy;L1zL9(|U#1QOnG-1EeX(cI*|kR9*twP9tZulITHziQf<0_c+M z+ENnfZO0z)0)x>!lAS&7>`S$^+U&sD<1EqGFQr1d8CyYj^;j7=y>XU$KDRSiwD6o; z9=XVF=PWVfIjnR4C;U$MwI!<8sr9=luv5}J^<)U41|!>@)phU~#ORAzn#@=%KZ;OS zykPp~xbE_q5*fPmvk!OHt>Y)BMTYfuF3xsQSfiJ+9$KFUzNPwzqDN8tsykBmhMk^W zaD%&9))OXM3O0|jH>*$ZsR2hBQ&Xp??c(LlO?Ae_S%+~CI5l0t~>WLvJ zxn!BYgz6`&W>2&g``xGH32-&GJfkdGe{ep&`9ar1&3BfcFg1%|uOrvWO%ksMXPkSn zOerJVM2n^9)TO}N2ACsG8Lo?j=I?r}5UqS7OX)A5QV!?e9Csf4Yjt zP1#a1sC3j{NRBNsH&I(3Xy;ZFZOM$zOiprfccDwpX4;tRYZ2B@_~2K2&)8<=(@vn{ zAHR|`{wlkYP8MC^DB`a|(YYwQmu+`;?iDG@Qu2MJ6eMglrE4_V-}{~W`_SG(l=c(} z?5C3HMrTr_I6*JR-bm>y5lUswCAAKF@<2G7UH*g{bnuCH0A_+ zM`^2WHbV7t4GA0D5I}Od+ZZpiw~fF56*MG0gP~s52fDeHNwb8rWogvPNbX2ApT(kK zQxJB0H49RSNe5q)H#wQ`lSe+JN?=ergxZ?IA(Yf;|MHt*9W7oN>Wgc2kRU%%3DK{h zF@O)uH+QO;a`u=Mbjf6C2BA3d0Yys96^{bxC+?8N_n*_fQhY>nPo9r^L>(V~=18ce zz9y+JoxO}oc6<|_vf-;TrR`IslEMNMZwb=Et}bKllu(XPhq56A0`=F|sXcUa+XOmm zKs#%V#(d;`eObWOO5?;fbw_kG5BK+Py^o@6JG+AVq zb#JOFPR*hcl8JE2&129#P(8-gZ8@AtZXjy`bd+Q@lhl9}VfT|KOib$F{=R%`cIo1i zX+z!}7Lho9GGDtjahidQp`fW(9MiNqD9ZSrJO?+NDzw{1ctTQc`#hGeHbhlm;VFkm zjQmN=d~w4sHNp|PHAyd&_*u!@^#1Vl=1~@4^=ac1G)PrZFN7Oeh4@OfR|Eb}K6{n& z3ariJUh(oB(ak7V`O-7XKx`lr$NGcUbbp~GtmU1 zErET}3}IJ_P$BMywhF*4X3dE7;WwLVMtAULqvE`?Z||_;7F4HZ#NLPqQ8REz1`48N?5#j{GTU)Jx>YEku9H( zdhu!%UP38;ESvEfDkAze3SI2nvgHlG=C^wX#ZLfE`ClA`w-d@DFRA>vM&Vk2#azob zE=zMM&Y`!!-Nsh6-Sn^FP-*nI3+sX4k<++~3-#)sQ~PS?GL-U9Gdqu}BeFPlXfu34 z5qpmIB1WMbv#31|NS<(kcyoSs=~XRBJmZ&ijdA8nai2tJh`-=yM&KL%1F^_U7LzEYBzFtH8sOMSb<242F zqvojva96LrNVk6Y-oTYnQm2`(5go37V^;FGLhcOQN(kjKYI|iDRB}pnXeB!| zVSrk`e>7AMRG7<9OBQJ3STc&HO#2BAr}wQ*@FgynaR zWZx@5>H_>bVF3IPIx8R8!u6v!2|Qexkl66W@Wm6u2iFTCU82|0T#{<5GH9VOJgDt4 zTqf;NLIaS-eTq9NUqwoqd+6;b)W5ZNVQR3@@Eywh8rh9ftHMnf z>op?F5n|%J@NO)#-^?YeSNAWN@_kqKd5tEX8*KmsuM2{K^d(YoPwgUzDo*m-#~oF@ zLzGW_EfLT>`*{5M_57IR-qas6Bt6k%ptbJsQ<3~o-(+vb{;5pqR)!~*BIO!50jV+V z0?pLfR3@p2@HgPBt&RFxz2AM;d;bAF(9{YtguaBcc3mTNb|~pbe6tQVu8zRFs{M_- zt3|#D1b72E^HNs6sEj7Ly1m81s^6E4uPskRS6ofblzZe8if3i74Fz zu+HDFYi4&=a@kj8K8q*Y?IPwkPZRDC(l_dzRgEL`ysmRfL*b+?srN;Cfvbsb=x>XG zL*Qy@;0(n=JK{H}tPN)hRrwzplT#I0+borZXdxl@$K&aeN|0-;;TA}z% zsWhjoqTsTACYfn9e^0Gmevb>qL_DaNZWc@-*bR~=)BSe5M}CR^%5d^bsOThnP-xJ2d#sMk1=+X5>e#`j&PuC9w ziQf!6l3ZaYq0F}mM76&ikpF)1>)!sAk_UCVrm8 z;6YRBW4Fe3niU0vaMO41#a0G|ZZHK*ns>^(r>cp|7pRK8pGSsI<4dEWZ~xAvP5|TX z;Vw6<>=Tj?v7i%4Pu8*>a9eJAcU1S*m$f?N#wR}+_B`VHQ9Q5}t2h!MG3W(ry}yi> zj+2G0%hmwtp)qo2;^>PTsNzdw{cSm6q#N(4dDG%3(4^ZF&Et{S`fL4X;D2g_zLSIx zrzKi%0%eB;YLaKS$*xa&g}#>9XAw$i1G-L44DpW8`!SFS9J9cGc^S6QpQ#MICJ%#{vW$wkb?4=Ow^K4PZ_yX2BU#+d zM9xp&l834{Q3A_Ygj-ZO0ErvFQ?iRSI*R*^abRSkH=X*b6x~{=5~rH0!{Nb$It*{B zOe68A@J9ZlF^67lz&_m_gDw6(%CdWk3#=LQ2qJ}_*^}IGi|xa7WV^=SYmK$Us{Y#K z2%P=nsM@=MfA7)mmx0!Pw`h?8+kE~dDiLfn^{sXbhC6TLStDahF>2H67rhC|#g zzQW|}D#FS>F#P%$(b9?^%<=%a@Z5={nBY$?&p@JN=SOd^~)KcI6&A^VeSeO9%GL z*7E*I3>jDyb5VTJMcCRfHXSbwaN&_mp)svIBvBG}Px%|)xTU>kb?x4Yw1>b0#l+`q zit|117e(b)>=VV7Wejo*XA~QrC*^p=Qo@mr+x|!2Nyt)oU6+M?esn;t6V%qTTIyx2 zoc4`Z%~iDfcHFAsThqDR_FQFiQ^`q8}&a66J5qxi{x`3|A>(?U-dC|7WhcP9u_aiIIk3x#Nh#LWq8{fhr#9#TaDWh z=305iqy%My*I5h8m9k7xoY$3oe!iP!6}rk+p&}}87JjDWBM`rq zgrXzeKl6`9F6$)_I`No}J}T#i&8-#_n-V!4VX`tjAh+ zwhauHK8Q<5P`)?KUv2h<7FrE{i1~7AVvH4vw>*I_uHXE-Yn_x*KUj!?pMor7ON&}T zVo}~`CEu&hr1#J(W#S3ZZvv7apDZ8y-eQ&({zcDzg2V%vr|fp{Wq4DU&3U5R2lC?- zKla04*%HaaPG`9_ao@eqt)gged!Lzpj9)pF-+T0t(o#mfPBuU-xwV67bcv8&H8a?km%iRuYjjXQOO&K?`~ls3$@gG&p(Ti09raz5AU&?HJ! z^f8OKD)KfgWn2#^k>ZQIA-}#(0u`FR)7$*|cR1B5UJUGG1Is3%mFhb5St+IIeS54! zjD0dE!SXuVgv5`*r2$SP|gt2twSSXWL%lL+Xs>w)-bP>EE(DZrl@JlC@gk zvgp4mc`80Tes-lwtS~%xB|oL`2--2sL*iTxOa_h{uhQ<)zsHRGU3xQLk{yJ8gckyY+3w9Y@eZD%XAH!19gvXDZYvAI5$F%hzET%0#~T_Wm(rItY2P(DX6HRM+cb`t*sI%~+auLk zk^BioLl(ZSQt`O&MnTJ(Gvq3p%x8qIrSY8VQc^1J&x=mHq$D2McC;G>6rF(q&RI0H zgGcx%&Z|grBDGdmSzmm;N08<`bHsX~7Tw{-0nY-{!j3F3ALX?R&s#)WFta`9 zzW3PY`K%8=r{8BP-^9v`Uq1}HC^iP(CZ>PAJ&pP{jXN6&X{}}Ro~n$?`rDV6ke}5g z_<4!jE!0#837N$4?QYjJLfuvJW&IP`3=v#FcYd6{B%`U|4sI)y1 zmHpXK(6^sh!PBcs-)FMAl)>%C6c;0X^ z$KFvg?{~&+!EcXd{Vp!IN&t(XTS!Ko@E*G;5$jmzbQSW6>jS#4er6#WlKm$DNW%T2 z;Xq1{lOKJ@Fhd;vD>zBbXt>F*Fk3%e=@bep`$scpqEfdcezrLF_)*9BBdW8l=uzEq z%5@%^-~Yn~KJh=tQD2B*U_$ibI@OowL}?^7bP)9HAB`G0AgPLhg9;s|IDCf87x|@B zwOfJr(*&VO>DSjVF;c^Ie>|x?4%T`zX87X@JY;ujT>Dr9nM=LYe`2h$h7sIT6NYYI zJ^{x=>WqJ77f`1$l?yq`qFDhv%0s3@(KlsN;vOs0C)2vF#HiIAPjxQxkY$K1Wp%zw zr2@K2YZEr&-`w;13I^ej{Yg0ou+G%sO`^l<@Rl?lI@6>@NiGp2&3L?`6#Ups8|ZO+ zb$4EBCej`ZyNA6$Tqr+7mTDq4Qu~1A#vbzFc$iSetLnPjuC!J4L|#1dsX*L{0c!um z{hol>RmH1wufxwBaBc;ksgl_zk#^`%tSfqH`|cljLg!=(&!lo)vC>eEi^~ zih4PKNZ%XC<=Cu9gmmp$0}XrflQ|-v>9$G*`~36fkz3|GGl~_*^JygQqrX!KbKpp}JVH)1bG`yadBq`p*y}>_ znZIT{WoEJRE#n=Kx$5!Y@eaa;xQLhD!r{@3o8W8JVZEJb-VH;?(HYf#E1S2+DfE|K zW~!OL99~cd6dNW#R4*EfG9-j{ErJ4vvo9Z1lmV0fuH;IaD#anUd~;3E>Ek~I?(@Ob z{)X37cH4oE1k;TU&AxVkyoh)oAkszUBl1m;l_DPI2x9vj0vF#eoQ@2*FpXGSqMiN( zicm+gIS}T=Vng8iZ$B@q-vnp?+qR8Uhox3kj;9Wpg9az=nR`0;4CKeJ+D6&INBN|A z0uoTxg91T;W36nX)INMecXH~o?)haS=PBQ|7=Pc8KLafEOpD*Rd%cK8M+u}jNcSds z=J?2skXI1i49%J8MwZw(rQDj*8GDsZd4B)FuRRFw13po1qT)6;ei3^SNXD(VF^S_b z!On=QldbZVdxxc9Lq&syix+%p-)U(emqAc}ggqtCOBzJhtRk@!P`bf3#QFK0#d+27 zCJDK8`FpI^mE;qT=rFZIn)ep;+tT>m&_w_jK^Vp#)+V{T;8TTaM-C~>xg62{;GrW} zSf0d46{xE6ktyN>sf5mB~z+|GFjrzdvj^iN7>-dAgVf`ZbXZ zph8?X;#Ug#&v0fbU;leQ<2|yS{FLrnr1}dRqID&xA2u4u`2dNNs%kLG5Q;$F{*&E? zSo5XgjDDZiVx-gr5KvOXnE~}T4{&z3pFuX`;o#1|OP3JPWwUW!${x%2$!^OXj!q`( zpudaT9jb>I&;^jL;(n(3*EE|I@@6MkqZ8YUO zSrz!)B?vt=#9&bC>Cw=QlbJJ5r$u12a`v*h*CMY7L2TYiw zUMIK~`buTylOl1wM=d+4%`J@^%=4mi>5Xi&Tao02OPnt{Gh5odQaMAi?i{(xT_ zuxPbEY^KYD4`>oNdr-8b9Gp!tS|`?At>HDsF74?h1CC{S_v0|`Uhb0$o6p3vqdow| zs!H1IL|#Q`=Wg;W)Gfoa{4E3c$F}27-acC&xKc6?V$3@C^(tl=x~)ps#F=(ViZ44v zyd1v?z|%i21CcMLDkh7)4Yvk2zQU8{;aw1J*9P)6aITgkOMV2wO)SP?!l-Q0;r1L@ zo18K&=CK_q%bf@NU0W4T0B0V5kZS;_7~w(CizHU5lP(u>FB3(=s%H+BZvixtoB{R* z0gZjxW5VSgWfO;FSiCf zMuTD$mkYL&2#QO)F> z{@+&9e|R!RoR8cQ>YIOZ_ zT;B6CF19-5>gF2z14TP`d>Tc7K;MH5!LYP)Ss?5P`E?hltc|t)IsP~IlG!5F-e&up z)`bNL(eK1M8Gr#QN@uqkzwE$rI+B)@kH;mNf}9Z!99geNtGI8jP8a;zV+&H5|FYcL zG8rgMmiryZqfLx7AhM^C6qFzO$;-t)rEOb$_YK<8bVKy|%JL6TEP!naN+MrM&<7Sz zJic>5rj}4FbvX5!0O;*@TK{NNRaWQs{I}61C9MkN+v92+(mexiEEZroUOR6ug@E#~ z#3WmfpEo~Rw|I2ZAU*;vns&`rMw@Bj{y$mbW6k2lIS<{Ii!(X=U2gK&i(kjQO>w;z zuTYEK0CaR{v>y=r0n853kmc-N&^1fUkyTo}HH=lM_d>F_B8$MU-DCF(zvHh0#@SQ` zdcv=czBKowa#G zSpo$%O8KJ;2iO!`VB8J%G37O#IGkyA z_;ZL%TOxU$$@h#;r?vo1YikM(haKG|tOqrF5NfTVUB^6F zZ5R3PCyKRk3y@vKz8E-H`-z{QfxgiS2)lU1MoK>uvv8z}Pp$_)CuG&UlPs08bGFhD z7kpMer}epW%j6{Gws%&hIL=A?c~Hbl_Ol_tS`SEcL1A$1HY!^sB|GrGP3QN&jnDch zsFK0iS7tK<>9Cm23)#TLU`cZG0l0~Wz8hduiH&`oXqI0tl{TuZw;maC^S=_-xq&u- zVK}JlB->GI^{y2qoL7k1+kym4r_$lroFis-GX6_}ozRV(lU!#zRQ4OD=VIWm>*`}< z@iP;I|5){`S5Wt%To#)~M`3J=GW|rf|HUS*Ag;Avm(d|Zd>gW7y&XvdKpxC_b!YWW z*eCZ4pR!~1afez;dZ4_`U{Qx8&$2wz*j=rvleGQv#;Ne*)*IRhp_>SdT%f2^_IZSR z4qWRg@y*v8(CryPZEfNA$FA`KeGH;E#PFo5p@6F8OwJ>5()m-)ARxK~G9~JV>!rJS z_`2Ks*@g8f_{+ti?b@!J{-J7}q#Y(jMS>zA1pTwf-s;~}I(VqD1D~mZ?{(1YeV)cr zP!G7go~W6GGpB+!8!zS+Hg;Z~tbOVl{m#3`n)|p?cFAqFn*rufFS_aN3)=p6#z(3< z^5o|u*8WINuFaD3uap~juI)H#x%6fDI4(Bi=UH6-H#J@1hNKunZJu$n(&P%NKIpA#*8!a$t`wle8E z)B(t4m9YlY=j!+Rl*Zl%V9k;LyUq~JI%Kq%~lrdkTLRbhi%C- zZZeGW1u0P(_Hq%t!D#;#r-XNL!aHI3rIq(FeSxYjQILLHjDr69f$d(bz%}(X#tebb2{+H zDU#pokJ6Pk5D8$!A-w)gvt&7^^fM!*dg27_1f^x*>dL{ z0Woy}pgN?8ccJwQ5!9~B0i6bX5xqm4dg+ElpdonZ8K3ROn&}sncfW`ldv*O6*#hsE zIOJL?-x={J<^sYqAxg9)q<-C)R791E?Sr^?k@XG{Tf#~B#!S??s~2JW2+i&64O9BD zTGMCQ@%LNa`&!%zVQwj70Fus+nnS4!&UF^YJwOlXUnS$jW7Fh7-m2(H(fI+6c++!_ zQ0g`@I)M3axI+a7-5Q@d{Cy(56xuGX4~7q0kE#hlZQ$w}g!}}L5~r#2{ZDsZ)z!^> zxN)Mlc2{h@Tz)4G!AOa?k-V_8k8kOkmV%0)bWvab9HdUftRgfH5<1X&L4goYy-RiH%BkvXXu!*U3{BrrGk2bHV+%G)K| z{Y0nI^{%stc-T?H^RK}XEq;lpLEBuGOYQ8N+2^U^iwGuC6%HM7`X>8gu?KE8yIQie z-9EzLr(t5{-c_z`)pYu_=g|`p!K*%6lmBRHklUSK5pcq%EIN|U(mgU~KFlI$Q)w>V zic;j?ba;WO!0A)8-@$<2)qgaZ#z{QS5`7IzEh>wp99`K=*67Ee6;UG(&&EwlB&!oqU)}dC#r3QltYak4Fx(>WJ0M-m+%8@K#Jw(nj zEVLUE#yJAFGpq|f{}|hD-!Of3NlIN)t@4_ZX<}fH8tr5tVDf@;QGxOfsk|b%N2gz+ zffXIr#!N>lUCX8GBQ#A*I4^niUbB$rx+_#zC~kACXv3tyu%)E+U}ghJcy_7!>}Q}5 z=@;esZa3?qWv@{DtAdzY=6qrE`%F7}calYHQDL z)|;yx38w4@UYUiRV50Ujrs%spVxay#wcE zSf`hiW1UPmDr8P#evXuTY<}K^nvgF&27q+*o#Nmvm_*V#q>-I?{h^65T!j9<+qT1r z;8?rn^l1jBAEV&6p3L(bB-}Xwd+0H``l6Qdp z5FM6Xxf@L73!LMp0g`5)f;*>lh08DnblBfrdvbR*DOrlW{fq54p3hut*6lq(1DChgJ3M8BA`8|_7PfV-u-L2Do={agfRp^k zl9Y50b$J#E+5xN&Cu*d_0wpK&%*hUP8-gYMrAqBLB=)Y5JCD$h{BK2DXnZ z3;1mY9$DTH`Z0QW@)7lC)-6f_0*rSHW1$YIv4?ge-=_R*iC9(FVksHrvT{w6PT%!G zZ=&geET6faUFe{LlYa8<+V)~0!S`T8vqsEtV#7~5N=+DHPf9(5A;4pRUyIR_ByIH@ zEg{)D?3(x7Y$bh=#Xd_zdHA}F#o=%;i#icZWl+Tz4~HwnSzD8Q(PMfQP3OjWy_tI} zz(K}p$VtpMSqTL&-Nz)Imi_kz2y|&W5Js1OYMdhJA}x=Mhr9@sC$V-yH~?rNsw4ZF zT(M(yPepy4Q1Tt7+_;|ZThY`#Ho^PsBox8Td=eND204@8je033D;bwnyyD2}BIm87 z(cZr0uSidnC-U>Zfk(YD6}3(2G*Q5$Bfrh2{w~m~`3tGs-4msDs>w_s9Z(Sq9JR#i zaJQxG$Yh2Q>u0mJ=C2$cJ6E*5PLQdqifE&hleLPdV`_55<8IUy#e}8okYbnI*#_a{ z4b3m#JbMTB+lLPkn%Gx_$gd14LS!v$^1*?KZrmIzk#2bVY;3ZPH@AxI~+IZ&hod zpV576_f0FSQu~sOm9k0x-QrL9+s&>$QyF;e$4gEJuK|!%Ao1)jD^e;yDLqHUPgfU=3htvza**y$%S}LtZT!N z#E{)k9yq8?maI8$Gb6dETVt-%cO|)2?~TzFqjIdVI^xSoaTUpW2^o#75!sH*2^>w! z?(88+7m$p$rWCUfoXl$9C%4+Z?%PEUCY#L;yqV^Fc~S)(VRth8_W87{2=+6nRV$@9 zsd)$-^;}z#%--8}%yQ24J9g+dJ}A=e9g?`k46V3R^-SkWTcAduWmk>roGf*jJTsz? zE_CRB$Ml-?eQ6f11@(;l^{QY#TNF8J1_tdMRL*Z8L^ zmy+*|)cHm9hOO|!&U^%>=yga4DA8Qywsl0UCWu|Xr)oicNuNbEUPH2N%$1y%Xs>;u z8+B$nV)C>-D?qXE#1MFjHbxxjUnK3pj=*nHUZCD;w3)xSzI5t|o-ls&e)Hhou8k|d z+OmVO)~?L?*tv->DFK6A&U}B#n~nlE{Ip_Jx(Ustv`L5pK?=?WZYT_&H?RH7`|*$N zdt56x)!0YKCa=+Bp+X)Mszx)3Fw8?}PaVLtrkbU%hfKXleE>82!bkExdC&tZs^*l+ zmrHLAT`A~716n|*Cv|$^{8%8j9n!_^>aod3!PeBdtr+gqV^_l-C9kz6xMo@*Lxn3=da&_SXxNVO1>&$6 zj^u(kBALm)q~RrZ!fpq)yR;WuE$WgtmS7NbDlOi(#|z_{<$v8xZ0XtZfO=3zk?d;p zRNx|3HCad)z^$dY<-%-4s~f6E!qC1*8_;<)VI+S)2WsG+bh~ zTU9O7%hVLkZ1XEP0zD@Rm=tM`PXwJu1LUgT|P+JTRpvO>FJ#dFnk>MnZMDJ#0nl3r{)I7T1J zf=aov`;DJRt$e=MvvaV$xUgwWuljrC<=w9Fh<-D6_M}v&-r&F~9={D_6)Jl2sY-?0 zTM_#4-WxCf7h~@o*3|o^`=Y1_f*?p2q9TG+>D9zW69MU+D7^?s4-gWicLW3!grEqB zv@g9kY0`VI2}&;sN?4HMS-+XtbIm?8d!O?kkc$hFwbuK-&-2{(=Z38sjm){?5ml?b zk$&#B!{P>_3s-B>>FrpHt|TPAU0Lo%1;)AU92QDcQ1qI<%m3q2zD{9|N6O^RktHd4 zR7tW5;D_{W;+D;d%kqzj=I|~F?y~cAkkFW*tqC?IvmFL2wz9Sm;{29|^SzH#-ehDx z#cLh(h;CE@f+kli1yw>eiBdz2h8d=PCo*p-+2SRCK`-h4&|DSxy6#*L5I`Zu<;^z;wCY5kmzPn zeBF0`7AR!ecPA>{Evw;;U!8H+oBE~0quzhYA-r-&vF`=>9H(34;Xeabx2Wq}b@#64 zVB}F@s8*BZ89+d~;x?%REv=4zeg7<4N-nG^ygvf-p@wbyr)Y80_ zDuGgFYOXrUB^`f(zvi=qGMM4kp_`qXe3GHi+#}nL$;_2u*nB2!XJHJpu=h;;=vb}& zNUq{TnU)tN+28K@MeD9BlXuENvFU1s&b3Cp@0Z@`wEE@GLG+d|JMdIOWsL|LHcFuj zhsDX@=VQr_DewNxXd_CR#i!-BL`75wUwSxnz9p^M+3HuU*mFkG>N7g6|IBQs`#b$# zht3}e-uw8YV~V%yiNVc|{xz`A3$Afc)!=+&PkdX`DW>>UIbK9ky6+b4)A*zEwfAMc zOTG$!w5CM?NRftmFR4)O=n3Bs-bvHb2dloI(^$S5IkSz@?;5LdZWF-4L467&9_dLq zCWib=j=cw+%Lk7?%^}(zGUrS|;Pb7*1@ALJEXnP%?kJZw@wGHKs(U>fq5`L3*>Q z=tAer-YD_-c-5x0Yu=AQm|@GgO(PPUkxo2%?k~+6XAJ5xk`DA~rFO%ZkcNS4I?QUd z)hYcWx{~zH>g`O^$akwubFN!ZdL%bcid#vfUZ;G6s#vID_jG?hp|+2z!aNmn=27qM zf7_?58=vq8!aqtbZREVWifq6y5G@EBu`t_vqTg#xW}w%AD12MjX=@R-XkP%a@!S1~ z{)>KCO{~=?QOfiW)z~8pEkdZbRSqA}g`Qu*@yAGHt+hCH&NO;PRku8Zh=fS@D_S!s zgL}ZbRU7Gx@pWh&B?Wn}6fh+^0uI;}R&yxko69NFJ5%|?kj-CaJ&%HCUZX~-7pH|N z)oo79(H!yLd#litFMRC9qmnx+JSPWoR0xGepc0 zBj_`CJ^WsP!R51X7L)+;esx1CcBAJ+gcN-7VGH-c_EDeJRmKzJa5r8sX0XmKikwe$N>GqepZ)mekUXV%30w+VX^?@_RKCre3(Ygv5I$YW zZc?0;4Y7(tU!6n_L_~5u&Id=eV`zXTkRVfgyvK%12++$E7wwjBy;eUV(T}<9jIB$# z!_K>(t^v8b*ITM3Od`fI{J$GN|Is-vzXa?)L7@7ddBxz-BFu%@krQtHBWPfiO5U}p z;SXi~PJiy{C8Q)bw#Z<8_6V|4@htj>XohJt{o&jUDM9ULhzdNJ2NGNDIs2Qq1>_Zz zpQCr-7mzQtd0Pam{9rE<4~O7`wK;kxj=MIGMy@ei{7%~Vv{FMXC-J-P6p>Au2*}Li zcsU&yN#O|?kcDt)YHsLY`K;lgeXWAG&dcTop$Yq!raOrN)zenh7KRdYO$A4bo(hSw zuLR#6WOnW`OD1!}?n<6zr=#S$KC_|-jG=AOp?x?{K({%N=^zQI`McNKQ*I%n-Z+!( zo%1U0*8Jkv1vm@{wFF11p=AjF;cYPsE&Mi4*mA~iF#j)2+OzaXz1`HcILKT8NVq}U zGsk&rV1WhGmT9CwkyX;o8Ka2<-a$l)lM3T#PF`5wpN(cp70h|%><;Gg5qj=7*8L~H zJP@_EnWa%RA$!beV>%Dj$XqS>m8jUGB{cp9<4ESli(weSfGG{^&%>B?{CaM9vKWz6wUa1EHN}1opbv5|5Jc9>l(VqMZ4;_+>-+QSZE*LiXJpSal4z zbL6jFsA1B&n%^5H2d_-$lMwiQX>G+0GF)_~pE_T)fRv?_p`G*+mt_ZloBi9rH5${O zo^WtxXg+59hm?1a-nS_rRO1i98+vjhz(ty)2Z?B_Io{339YmYPF_kPsCS@-z>||W&<~yB74`}iJViNdq zcBAwG_~uoC4*YK;z-1MjPzH4QTeMbuMKnEmJ7>Pw{mMer-*(yg;jDFc(DBWsk^8;_yrp`No#s-4`TV zgiw2(?mvitUgbEobAeq!-iuwo)nEInKTb`uyAN>$=$;W)$kONtKO!L@!dEhqxXe;# znPuoPLTal30Y&~Hxf`l>2c|td$KgjwU=))Al-Z>bpRPx14Gi}mTg!yz%c{g}@k?(n zM$e|fqH_l+1)%l5Eh1B)1I=RX8kCp?iBymCK6_FT$n5!3p8dir^_9l+C?02vfM`E7 za0?wNL=u}p@r{uUW`Y)3LdSK!bQWojC)WY`Kg7^c9>K5JeTbbs%lCluXgmkWct)<2 zUysIBS!P#ShrTvt2&=+=VVD2z)yqEcm{a*I9OeqTgIiMk&#iR(@uQ-``p12@`}s7G zQAw*01L`U>&u+}ONX{-UTH6u9u}|~%8N(`gOhm}MZUJ5 zEyx}HzkB~hPyV&e%%l5!@tgyocM^Njf}Rjs!&9rzoVegEyV|ZIB?%CXCO{^@%LTX7 z0PVA%uE^^jQRu4{jkMzbnW#(z%{-g{h~PWGtY`Q~Z--sTl`94gJO3(7%&gdcH?BlQcc zwm84ha(Q48_VY`ZuU)>kNxKQTNd2+Gh4jQ{9<0$t?S95+)-FF5BzTEv9QWT=0*i!F z$&5CXeKSg4tPjt#zHbvB>ok71m2R_c zHx5yYBm$PLv}K&i>}`8brgc!Mknq1WDutrMPldn9{P(@KYz@1T=!cGMRTx7C=eqMm zM)>h9p6M}acJgPg@`ZMdzNXmg#qg}`F;JIxJh!-Kyh1nZ0g#fNQsjFX=Hxx{BOe*h+z zpOnpwFpe&`*h22yRj2-(;fL#bmo+DSBFM<+QDQ{&13XqTm4@7UY-sQ!yAcIs#8~O) z`l;NB>gX4VX43e9!-XGbNG(1?NboWg>xIIBJDAQk!7QWNNt5|a!NuUvUax%B2!92K zKG99LgKsZalBvjUSG2~=sc9$XtV>W*j80-UcE`;=u*@UnVs5)tiq%)EnbkrvyN}^0 zGVmMn0s#}bR8lar)@J5$JE`BZ>SVh0ahWn!n-fmdLGInjk9{Kad4IDBV?-UFpX6tv zx-Fx?&1cnK+SjYMKukA6Iu3D5-DoaW?xO)qMM+}>a zQM&QTe-R4*yXNkH_!-@A@XOH@)}BOTkzQ`t8Lp0CWy8hB6)x%U-v%)4R-0cJAb~Gcz8fZ zuKO|~Yq0juP-@o_wLZ5adH?Nyw#?LsQGJ9x4wPjw*wJx;5^6FvwN7_M@ADWSc6tWa zH3*k;hucGY_6;;Wayi!Xf4+P@Vl z-NynN*jo2PsxoQT_T4>RZUkF?&E(EgvF3YHiFwHUq|GnSwN^PKy(qxtmV8k3+xh-Y zV zJpl>F)S$ngz#J~2=dy5)sb5?3^R}fIosZ=&rhp;uce3m;(*KAGDBKS?E6QEmkq2UO z49n?dW?MNHmbpCq&LtZ1zW!RpQWCahy|-pb`7{+V9a`lCu9TT zgueRz8E-AwwiPsdhFVew(N%5Tus0bt3WS5#?yA~2t{Tg%JNt5y($3*eqQ|12doFo3 zF)sLgBrn>wM&@}XMjhT_eMz~DAxcsbeM@at)a!v4*!RPqQvz8AI8UF(fBa!*suFFy z@rzV*!U>*oRy?CoX9;b4%r1C~PQ6J#YgVq5@dd+l5LH*xoPA$fXej$lZ3?QUFS2Z7 zh~8J(K}W)*F-MN%vpL^A6S=2q2Wm7e6gnYSTut|6PkU0o9z+@ZzM64%6xsA)m>AO3 z`17cIp#NxWK+frTKA&s!St+gi5N&Et?OPiZsBXIWsX@gK9B<`4@$6A~=SR6;zL)+V z^G^uZQm0*^;Np*cfmipF%G?egeTP(;#)58UCqxD@ane%&^LW~1RgE#8XEo&W-S;<8 zRuZs-OzO+EeaXC(sZxg6{b!YA=H@=UM2m1gN#+e;M>;o0R-}CE?Ny%=_hV-0@bf8} zGrKtF7`pD>&5~4aB4lesV$O*DBN+v$3W!6}lB@v?F^;+%8p7Fq`}c6gJQ7!TPFfwY z5Fv6oq?n+JjyJO)WD@n3zvO{oS=K6)jfO`zz2N-gZJU9Z9_Cq0ccWz22GC2o0enS> znoNFik@Vf-%d3@^5*y-v)^BI4<-DZH*CP5sZ#HR7qg#)At5u#-1ih7D<}xl?fGNB) z|Ja`I%{%qv{oX-iZPVOlvmeyLYex9R*=~MIaw*yp-T6T*gLPwfO8Y_6>?xes1TcR^ zA^-)*Yvc`83%_3xU2K+OUrsDzsw8H;v|F^EPZ1? zu1XFDUTC{mlv6Tu>r*EXgl_S3kR&rqLo?H_jF+oEUQXBESB)K^GO&}R2UOq6w)wN)r4sO7>Dr^LgZqj5*7AubAU)qY-#kjo3`5)q&tAN?u%{v-*;$x3e9- z=2zbnQ>P8_1MmQC2Jo)I;>aO*<{plq^BK{SLYP5?+X^Xn@}&d4)%$K{m*_4{{gJQ2 zKO#m0JpqrKP>!*SuS@ipWs?qle>R6!- zb9$8rRA+ewuTyNF>XE8vHd{w1CbAM-$%f6q9O*8i4=GTxEu-b-<-Ci}&3V)?sQV_e zS4k}Ki~US?Hwi+W!f=7dJuQ+Z`2k($snwfh6_>g`VZ-`x&Cpy&D#^FJ=o2pE^5l07 zw)oB!PF;Du)^r_k*Njr`BRuiQR!$Gko`-4Icyc0`v78Z~FqVzhLTVGAwGkgWJOsFC ze=T;cnubFbdWrUq_HcG``)U!$QR{EZl5V9Nu8*5v!yA?JQiWzr%Qct;87eEbQD=ZD z{J|P3qjU=dllaMm5D^SdN&NS6UWqUd*|3prqlV^tcX!tGINaD=A8rqH(a?Om>s`qT ze!2ldzsqww9OV#p%!xk;@Ai~Gwu!1xHB|BM2;LEhd+fcaaZFWVG)j~@ieWt0Qq3 zt`|w2aDOkx9`zKM`V|dct={AL)@%@cU6_|N2R$a*0hX$-N`Jo9J+AxtYhNJEK2UdT zD)vkgmi>AVK&Iz__Bq5=DVia#3$U)+eW{{9`Dars>)bUqK;PhQT;YNfD$fl z2h<=T&K~Yn7f;y|e_L2TaY#{UUy2+V*fa{Bib22FGki*UR|Y+Y@U(~`1?x|;8MZb% zh+Z8Rp1%p%6{a!lM)bbXkKi)&5GjXInt~S&Brwdwhp9n_3wUlqDp4Ew1Of+mu`BHd zjMnBhJ1EXZ)+O2TKvz>%d}8P4bc)EvYuN)3u^i_9$C?d3C99*?scg`DwIbE?)}ALn zr^k_+_bcTY@3mHrLGN$XQj7foSteUU6al()yE~?a1yj`)Cy;MwddXcs2vgwntC~i- zSGK4p*HScgtS@|d|KWp%+)sPf!Xw3R!Th)F@&g9#K{38fSma6ZmH^b;>X7?nht8)SiB$pwj5(!ZKE6g*smgrA<7E}5u>cYJiW2|BJ)G3>rpBIY5GV(diDjQty z?JoLpDLPe@kZVFU>5R7yt@> zWt?r4@seGN?hawkrfxP)?C;(FZGux=ld4+#=5a=s`JUSW$)#t!xJNWqx!a&?O~@i= zxN9Qr$zV0qGqW%$sIoHG|J-x_v|p=E$j7Ymq}!ee<+nm?6_IJ`SD4=iln7V8-dCMD zzWn$v&73XLQ3i-_dbyb6a@tb7;%rgyft8;Ba2oN9?M7Z*wf>Pm7BP6e+EmcEf8W zJKE+U#K>{qk*F1h8c{SO!sdLswfg!xVU_dn?)QfV*9Yxv5Taq3h^@I@h?pq&Etf2Wq#$OviXBWCpo^6;K@wM z$`9Up``v+t{h{jMA!V&qDvo#zCGzqFAqg7N{k=E1c*qB!>Y5hm4j7UQ$b!JKXlp4z+QTTXHM0SU%Dp9l78$wD?llqywyy8ven-Z;(( z>|G0ui^*lT2BkiK3HHYap6K{Vl6H73=oPYY-J(j0KCt`kyG7^E2xBa9~-Mh^; z!zz#GW&uxPJ0+9sg|k-p4rK(w3br$czmmlFKL4iG1jMU3)vO2;a)%mSD|0@?Jiw3O z)3pK)rtA)QE$7s5!C?Vk5$I=cFWO+E4j9C+tEoPWW&Z5L?1aM^8}svN)4o*T>?oRk-GMCrN(s6;a+xIjO-5NAD70E^0f6k^R}#tbxW)_^W;}P#5iqm zm5(FzXV$%J=&m|mt>B8-g>n@O6f&07NPb^<@0HmFl)Aa0L6z#ATM3sI#C$|Gj;nZS zyMvk;!P%GYyXHX|rdJa-8ogdxFI1)CV2ZcTc&hMLJr#|w*qU#fe9ErtstA5&RgiDmTXl(m~; z#gQEXK1{PHdvl6qy@S4Z;k8`XCWH7TrPlKv8egOM?}-(oA0 z-6L1_?v{!ct6*{+%m!tJy=~c+PeJ1Q2>37#hvAibZO|NxN!&nP_nVn#tqyjL^fIlo zD-EqLQ@Y55XpxhGHR3bM7brU-&kX!Sj)a<)jPN4^2ThN%$KDI+Bl~mwN*8`@mfh`5 zSdvDTsO#BebBW28%7p~4pnDA`K7ANVGjAju!*!=;i7Ruds~Kcr(9Q@-fm**bMkV+~ z<+wiy=`qWTRsH9z`lYr2!I*uwKJ*JVN(Bxb1HbBtl^VeX&sg$iz%vHS`Q{#wjZo|h zVI7UecmFsPTY-)RxJ=ZQ7-N^|l4{*P(3$%)$pK{bG9fx~oN=wZh>`C%moy@d&ZQ9V zG_s5faMK*LZyi_(bz|n@dWqm-4`1`_2ywh8)D^!uk(X;`pO9hyp3B4ROz+{2bz0?? zarTpBe`H^IN=1h@e~~&%N@JDY`o1R_4X6=()^stsz|9HM>N%v9(b0AWMPr_XU_jiUie6}TNbk;}*bY@oMr*$>ege&kr(Yw9-8WRVo zkESmx8fd56^mEsXH0C{!>^6GNC-N6wW16NjpT9&-O&0jf#&=JDiMZ;dSQx^%E5F^t zJK$FA@=m(hvlk0zLU%lOlKg~ZiE>$@WCi{FOS2M7#w74c$v67E<|d zsaEIF!BEz8t!B}@0jYsL2aiFGVs&BKy#FkbY5&gr*RisKQH?^Q`_N~~mVgMfz8u_F zvF8Xk(voIJD1W5j15mM7{*o%i4+~g1U1US1AH3J^eCYLU&$|ym;|wCGgAII~i1lK~ zSw!g>$4a_6D;}y_RJi%19MNf7Bl@nVb|z@5Yknwkvp#3^p?(8nXMXT0)3@9s8U|_? zejt*d1ikFlRjg!*Z@_<8SI!afB8JclmoFu~`}f|R-Oa|d=Un``qqLj3=dSbDSgg;_ zAJWw}#W+Pih}3x2-?_+NeTFX)V^`2F?n`ps`(*ewSy&AcIu-LG(r-?L&T4~ETIN2R zkw?tUcYch8Uj?p@(!Pik7PxXhRF>~-{29O~`~ugDx8OX{RXw?Ec2f8cExX|Vxzogs zgYcOKMD8i|p5CXbr_P@0@}*TNiyuRM>ZH{_df#)^lJMVH*G~%CEEw7BJ5;FeZhP3f z0e*i3i8xMAz-c?WT+ltT3HoR<5d@LSKBVaS?}iv!^~QpMd7iw^hXA^VN2jc&VCZ=7 z;D**`D9MUHWG9;Hub6a!d=3!D6Hnw|=Kuk%v2p=Ys^z?TN;#=Kp%V{!*sbu(VK~h_ z+nMT3xvP~qDqlGeU7<=?B`vl94V#|V3OnhT4k||@L9H%fV|?!m;e1+i`dhf{^F!${#JqBoYzOBdm&s!8 ze`zi^g8yy`)so|RMYg})>ETjdKHGpnmw|Y?^ z?ZLCn&UM2`fw0k;_gm4i+5`7PO1 z9)`h#=-m!A@|{vd?{~u$Kz*cx^H~RqL$4~NYWQuSw`P`qWv_ty`G%!ExIS5)@)nE& zZ40-#4wV3cSNT+)PS?qlVoh@p14oC;jz0Y8+3s_BTgoSGT`QIFT>_}_<%C@&>#sJs z>veNFM<1tZNxi&2Uw@xOcgJTrb}H;tqKz`FhUmGFhHWtW8D6St&0g57!5q?;I7 zpVWct^x2`{>Ee8s)8#C`&)d^mes*ZK4pj;16pia5+nuAK&a{w@90q)O=L+L2LZ-vw zrLuZleqn~Y+u6ND!M>Nmrzvi9;7FVv#RG@|(ST`Zx`h*2u#VZUSWJqhE>-hlKw6O0 zb6r%yYiLLm@hm0f`Lx3{863iwML0A z^$Sk0qq5hO40+v1{gED=Q5#>Uf9--!bZdtf+!!##uDoex#y-YF!hJ<`L_5a>dTLo7 z7J1g{waWXdRQlY9C=QX%Qh%iGh?hbl=e@OVeRhgqEOI@Ryq@Lfb!FqDdw1|k0*Z|c z10wQV`1uJo$?VIR+~xUgj=S+a|5%xQZ11b`kPmuBm#_c-Wivv{K=2j|!5}@rS?|K4 zo?@^$QZ|&U*GM$bs~K}#2@_$^=t5Vh*I={R)(Wx|V&oh~Ef7Mn!zVv3onI&uxRsNY z#C{4kAXe(iJK8QFMtU$j$XAuX!}*?HFMl~k3=J)=h_|I*Vei4AqcdY(K1B&&B_U+r zdZ3PUXDf$~Ftu$BWPNYkB;BgKvN7Z?tAqJ!MP7LTzoO5?@IuY}h8hjKs+6{u$ODFq z6m^E&0P*�K};n&4DE=fbw=?|lXQPJInQJ3B%o?fcTWOu zu`an5?irKh5HMWZcMPxjHrq%*`6jV)dtPoK_x7^0QA0FT;U)4#RLd)p-m=-Y5oO># zylNM91r%|g=_H8oa?6Hzb~fH4dslNO*o3HRUOGqmqE!v)X;lPUsIExaFkCGL=NZl8 zm^%-N2D`4}^U@IxY{JO*KaP9cM#H8)dMKL#O;m^gHzi-MYlx%L-yoQ*&(lg}m?t4iLw2aZOoyY{N8T1rJA;X}@-9mmQmKh|-fPBiTth+t z4xXT@Apk8d8UUlhrA8nLYO41XRlfM!$t?PdU`n5Z&ZAEZS$WGHPF&4Azdor5oHA1qL3wCULR6UV$~Ee^MH+?Jgl5&|2zPM) zG%@z(`!JoP{KdrvqwN|_k)Mk`^m@CMWja{*MzP;4Q~u4Px^+atWLE?IXSt1wYIw9-}s#K%J(*f z9~z{EDmVnu+sl6$kOGg_f_O+5hRu!M3Cnv=LGOd4K*W+jb?VcUv5Sux2QU3}&=|nD zidYvU|0cLS`Xhs5-oud2k#(9Y`6YlPxnJSuF#m{g66Q4nJF+?0S7w?_*GKmDNNS+# zC=YrYc>|Q)F7!^ydNM7_+ z`bVC7r8wp}jb0cZ>I#yRaJ$A)Rb{pQK;q~_$}aZ0^BAsL2DzfLx0Eo~bIXfY+Paq};p*{E~Kz9JwnuM=X8*^`#%D)|TmQH?M zK7~@1x*zab@u)nQlHJNl<^|kHqCg!E9&a$+i%X9wx{9tH;u&DC{1MA4y!aqQKfGDlfhNLLad91yAMP>N9KQMPnm zzI0e)+0;-_8G7+~#EY~%XCa-o9u`R(<(Z9Nb={yU&jMaK65k9VJWH^&!Mp!T0ELrB zN(&*|m$t}F#kPCDRT1YKhGll|*mMaNM0FV%$o|{8_8N^GNf5;94%o2bGdlIoqekIZ z$f~W9lc?*i%yyq$Qg4&AHK)~+_SoX3D?;K;VZL@iF;98Ac-r{@yM1^xtg`&OB-=NH zP#5%K?YIL$3{+`Xr+=4CSjD`!ktd?qBf7pa8?|aZ(ybS1a~HS->k`ECXS* zDMhPnlYIM*^PC=)KCWVjYcDo0S?aDEs93yqPjn4ldi~jiVVYVtoOX=2e>6Sr)ptC?{@A~_a5IvXJ z>^VO6Q3UosZ>_V5)sRve!GDDU|0};$3#-TKnsb@JpM`6=k}UbBIC}qu#HSgglfd;O z{_1nS(C}%PtGK68mVQ(9sMw!@?1!GJ1D>~XdxZ!u&#lpow*(M_Q`biJGzdaZfMBdz zy*9mIysL8fU5?oP1(<5(kGxCmCl6pUrm3o}AG7C9d(3+gi+t=4c?Gs50bzLiz{ngZ z%eE;8PtM&IABj1_ZgDCjH9rIw#LLq}e&jj#8hBBMf*deO&`WbjTS9M7d0dc5HX-P@ z27V>Vcjq3AW#DUVZiRcjeMSA|P{$8O4V9qG?feG@<3fWQb4M?yQPUMe$0wDQVp}wx5(2`%JdSn0t+R!hotCkAQX)1H*WlGWocarD5b>@Cx;~MCz3^s@ z3n~H}?e>1amA>*HZGcdE0{*z0Dn}`(-g7f( ziEE!Q>+=);l|7g~o^{b=|#7S=nYqvxm+5bLD5-)KMa+4iG6ty^Op~I14m&hPzq#f4J9O)&`!y zE!yk2MZ36g*x1!!9U@th1x&f&fR^tXP|}|C3qC*e?}e{7 zReVC?$oi(Gwj9%qt<=~P5|zc16Ra_%$3BM5#!{sT!J)sOu5dHzGN|^6LcZ8@=WsGV z_+C|2uMM*JBR~NAZGq7%nn+sQba?;tM|8lekzep37JO&){>&5++UN8k2;L=H7}{*` zU??@-7gqqjUEZ!;21-QLwq_Yf0=}Y9!1wNVGs9n+jMq8m35qAEo|WupQ?2aQKxn^? zWLJ=ZjYY$`-kVW|b@SgcqR1LiUyC2c>D(LqmA$$=q1tmmR08e=Ut4hjTnZOQBw#@T zENRd-iTSN&Ns{s`g8%0dAbCGbgSGe9;9EkI=Og$R$3Q(UJG|Q^6IQR^1+qJ6S5(y({9RqosNoPL4W7NMZpBa>RRt~ zc2Gs^-A{vy=xFRp<*;omigzg1voj>SGk<4wWeR=y+AEIfsAF-lI{Z25A>M3#%2pxmb{u+^6_eOyw)y1-MwGs05S`K_K z|J38S^Oz}Mz3lQ}ovkv?x~YZ!*G%^`i&j{Mkjl5{(ru396w70N7)>VbzG@={lq&)YNW5W@8U90XP@=r<6C;!rXo!bzn zmJPyc@Rq?33ct6C8msvBNdf4Dn+T2Ws;E zp{npR^viZ{wKh4T44`uo{beO5#llc$VzdMbP4Kl#kbEM8=Oh{ORL$ zPxrwk`jfFDNOgJ6SX!v8aO^FLgH4g$W|A{~K9enkVj0DSh?bFb`}^pOuY5wqj+zLLyO{$7sY#sjaYG&E;H3G-0TEj{<%KWKA zQlYz^&~{aW2*T3lwobYsE#zrpjg>S14I`z0FkXu7k2Gdnj?YKF2goYrugAbfhgEgU zKg}pVGXUPLQ|w&w_GP9@{qkdvV%8k3lKh0i{;_YJnnVce7EjpxvdCknNVSv4c4Exq z%{B{e`#{3*(;=6`!e*HWRLC@xG^~%Kd4IKb!6>3>uGTRx!2~@ zh6@(MrYys&r9hjghK3Suo10!Sz-vr&kn)S+j6mk~h0^zqC0f`7l!I99UJDb-zaG`v zc)71BQ~vaJ3!~-qRGhDfjs=f@?PfndjW`5Gr$3*GZHfJ8s1`hO!4eS%?znywsLGBg zV6%+l&hYi_zJ6mgNu8Ylx<5MP+Z@of+H#mqZN%Jc6}M#B+~xhID+Tk=u>F~NdqNNP z`r4Dz;Bixa+9v&da=YUtx6lKcYuR&;NU^6mGxrI8p(oNV zt==#t^D_%pO0CS0_^*Zf3NI!q>Sf)nXNHu6J+?yC?w?+$90H;E=ZGFsaB;&M-Fmv} z{)S%KCRd!H*ArrOY-e}-+owR#h>!(A;SE^>`vd3Z)-<5bqSV6}*Pk@VK%#Q?yJ5Zb zvo&|UY%%u~t|Hw$S4R>CoIO0L5ME7eyqef|=Xs4o;P*LK^H$d-y{HwIaOMz&sC|d% z+&erPzZJ0XMQ)Ga@Q7Q5hK2-H8;zJW^~uNeKp;UdT{OB`D9G09_*GUEHnSA04+d}u zekbzHnb@cz6-Ba4V+;H!?hG227e|42o3}nRYvn^~cz;us46+?&%(~x8KA*VVh@q$6 z{&Ki>zaizyXeyTweh9K7aps=uC5laVO@#}J1F0R&s;c01E2LA43pV^E3R{gs)|L$EqdEd8>h>~|cw?;$2BzDyT=-Q>mfj-E9u5DGfi?-^mi zR2bRJl)GfTrG^Vw6?ugVV5bSE=<#AUXVcyt9pFSiq))RV0FRa_9RaKM`T#;ClN2dP~* zX)uLUlKW}twILvExV2oMv`+tI-w`tl6!P9O@r*>X@oZgB?c@|L?>Vx+j;itSjD)j^ zIf{B>MYEzCIoKXyzVhx=5TKVloxOUaygc^1O#mN)5hp_RhWECzqvktIM-KSum3M#0 z3qW7g=H|=9iD3%mU^^0YXlFNS8ECnEtJ%tiG&`qB00K<~8wrBTdavL$iY0s4feC1cuHqer(qimx|EV=H>u2?yk>g+x=zr&cK! z2qPOdBNEc3jm?%flbl{gm^{wWlgv$<@g^7U&$JURcxv#n^XL+xRX6)ZpKshTvc#kw z!|}S91>NBx&wRl2YqjU7hTNA*l+>5OHR?&p0T8gU_u*Gy8~&S|dtT1ljlP zSsuj<3>Rzv>l8|<&8B6JsC$3hR6%#BaFwPCeC8Ek?o9~t3}EhWIwmQ0jjH`h2WVf(sF(c2y?%>SVY*k%$1$#!Io-qcMX%AA=H|C`KdG8+ zQC;_}t41He7T3SG1H$c}9}1uO8XXt@EN_(2aPxnsa{Y%c^gjn-|JPTkU>jkzmQ4UP z+DacDvPqWYhT%mQO3+|O^(SXkb#M~PP9y4#^ZokCecPJ&igsq1a04`}=pRescgkCo zBAF2{|DkjTeZ>QH9pT4uBbZjtD?!-=ch@%EoISPns7G3HVdz4L-r%;d@Z6|x*R zKsBZYv$aK|y5|;6kPk-2G)CWcVieb z@bekf)iyVJF%=Z@y#A=d_gS5GU3Vj`6tW;m>;lyAh7SqluVq90$XaWAp1LX1%hSEg zcD5dG%Ri{*u6c)Lhplf-D3#wEM~!b-6ubK06Cge(97i-OkhqXa`255Kg=kfUug)3r zjr&FR1l|zoz;q4F-h=*H=`MTU@?o$ufz^1k>oD0W4hZ173!`5C+1bg`-mxU*zsXsa zMmC&v@RnyW!dUDy#Lj{$i{kR?dwRq$LO~%|8mQq)mA7}bIP&NhQyt}od0WRX{`gZq zH8N+}sT|b>2LyY&%g+J2>ZzuY+I`J$rR}ejm_p6|(u7=1DibwB-c~qH1{B(UiEjHm z&HW#`rFndtXa1Lqr0pU4h2DJBYSM0Z`A(|>kg+;2!V1Ky*ID1(p6S0mET%kswttiM zu4r|V?v&On^Q7enAfC|?GEtVjDjxDq{i&X)MVWm^yPvt`rH|e`t$Y+rwIUl)oKo24 zJi^6%6V0tfNpnbzaErP1+kS4RQ9BI|(C1%$B$Yv>FDA&6WyZg>5w2%+Wwzu_`Yv$@ z`q#mw9=QiH_w!{mCdw=)s8AV%=lPTK00mrIhaNLfZh?3BwsprZ=>7+$GP~#7qkUm- z16~yA@||UE&36LZHId{yIot^wyWOjO`@B%AFT%5ys%yI^u;bApSqN~4GfYwf?72ymS*wi4w0yYtYSV znU~~g0`wDZ)1wS2iL-vP{d3Dyx@&ac)o-JkoUqNOxyYacFFcWn)CUWL{0z9CfHPX>Lwm9eUL2egmGvOJ74u@M?T>p6>gtyy-jd`B6T`O;I_Rcf z!=9jSAo(Z_5@6Rin|ZA*S`}Wr(|T#@ju;-3ME5|GltP|q6hD*=7@X7f_0=d|;TI##rZH9tbViVhTi0FDb z$l5o@o5s|@=@5yuZr_~i49%AwqeI>Nh1XWz2Ijuo_wjx9ERS#JIDjZZ`9@~O9fU2@ z0^GQJ>f)EW+L&sXYs}+{&UO@A%2w8;CobKJeuC0nJ=@a0-t{OmRdYJEM$PA7BoW5n z%1wq49+B?@2{;{9$*7kOO=Ew4II&tSFKXt~JT@GG1I)|i@4yiQhK0(7&|XEyK^1}1 z;X^%EvI)U&8uQJ@!m>~5!K+6-uX8D&UrO_YN+5FKIwrj08fMH3#hH_-+~jj+XxF6Z z6*ef#&drTZ=-KK0o1wSgQ)++hCs%RX6v+9%NGC05v>@Q*tA<_tH>RO?o#kzA%%_-b za(uE?XB3dumU_{PIv=F%lj>XrUZT}xe>@_rXN8kYlW~)`jTIq}yU6nP5=6@OR?yyW zjSYCpe0p|Zo~vn)dft`D{eJW7netqBZrSIBQMWEsOUpRtp8d~wV9~M$FyV+y3b;^$JM@L1ZpywX^?IWlyX%KT+$nF3+Kkd&}w&{iEfL7(|g$o z5sTC9T3&bF%U>CLb`l+r_>!!r<}*~yXW9j?fOj2mZ^3HF+$H}1@b=zOO*LGfD1wTDh*AZFC`gm0RHa2!x(JAZ(jp?A zfb^bFq&Ect1tBOPB4DKVgbs>GZ=r;QCMA%7gg}aOo|*aXde^-(-+gD+toe(QaB?`1 zv-keB{lLx?lF$+E^2YX#rswtA*&mgsmSQn6-Woo+OPa?>U3i7ATl}3-h)TJ zehBQ4zoxU|V_%G|w(9j3*#y?vnR42fCi%nTe0~H(z&3*7Cf4fG!-sXRP;;N0j{#PR z$7$S=ceT2SoK9NXLe~v-N(Xw+<4v?R;ZugUT^KCyr^x0156AqL=jnr$TNikqn)kOb zJvEQA_-`NdWi^1W>LR38;-8*jyC$`47kN#py(n8a@|uma;Y< zYvCTYh>jY5_=RV(p9Oeq3^*)s^e_D<{`1J+|8e&U`aAM3Z7}ocwK$BD?6#QBcvX7^ zf?^mBUX=x7RH?I(n&WHxWvd38C9#!{Za#={3)IDZUMGxhi2d}2J9_&3dCYG8kI&+NqwD_fG{*nx@!(2uqRsIH z*l@w=fWEg2{3&W*PwY>ED^G~+SuJvQf(2>Ll$?@a{SLu^3Hp*zwTAUmL$Boix0xem ziXcyneB@f2l?@pP)(iu=tJ*&AT`nL?z)pzibet7|1rO%YEe%FN zjSY#5DUFGmWkc@@eA1sOZMpK!EQ1=-x26^qW{`Nks6v|N_%^bZ?s1PlU3gXV_Z2It zu1oTds^`{w?2N>FZvDQ1M&{7I<3)>G&Q^p9o&W4y|A+dAWjRo3l1@T z2O$^LDnt5@zd!5BB*uGW4$O5}`Zod);-7G!%|-fyCVA7G9itED_>6^OfAj@3H2Xd< zr+2kbUbr3m(?Ey;o{u7})-6TY;E`MC(rI@F=cH)bk(MfET`e-6RKbg7AsSyOEA7cQoxHv5lCAF0bo(>VCV-d!A~=WA<)RI<~wriuatF8`U$ z0_5Y;IiQ-pK4YhorpG+O|FAn~a36|mTbkBJjo84xLuywRErFCYymU-zmvi3DeqjEV zUL)(#KlgNJBZy_R`&Uwft}(th_iCf;IdMikeqwI$XAsOvWl;;{B~0x4_c6in7Bo*U zj*>KzPCifnR-8U)`ZAXY(W}S6Mg1PATg5JJlW}_WU~HuRQHz|1B#pa^JQA>gV5^f2 zYx@R%o%^N3A2`I>eR>U$Y0GO_whP2|djDnW3#n)VAhw}dE{w%R^y&TTc9-Qy1F*6) zuV~XFxC0V1fr3yTVK9w1E>}K&)_fVb`g`>1d(P%W^n)9Ow^6j@$<~7BVR!v@8J*a= zIrXS9&d&Uh6808p*Fk6Or7BP^TBfkm%lO$bn?BUejbl_>uNlst~< zm`_lKRVVWN_4FMeCLxOTw`CUG5saxL)!@JhL-a0yF~Pe%zWF*3GMz`RZAcO*p;#cl z%&B${X0B;3H7r@9i5=*A&g@anSi!aJ-p3ILL{|Zv&0X#6a}&ueZmNA3ly@A>uF_Wh z=TXC4JM~Mp10^YAmVBI!+;PZt)#lq|(&-9$m5>PDV!dj^V97$4%*1|m5B^xGVyR@C%?vs+s#q*7k69?XP31lQ{mE)$!<@q(Z&I92(!e%H`x z(>2J3Y5vjIA_3^OT0nY;0-7=_1iPgs#G&nYptP9Y=N%1rF~A+bpOKQ;enc5lps5|_ z%j~&!-gahApUL84Gdbj?s#nlfT6TEGgR{C z8fC=ZeSEE3l6HqD&2Z|xubWlDv`(VQp|Bpb38#R`Y!u;1L;rOYf%5UdBM zbuJo3wtCrk89TY>boRRp9>MBd%566utRpyRZQa%%p`RKtCdk=+M4V-IebAlr_nu{|^wrSkriLNkcDe^r zmGE-du6dA7D+Kc`^>|X3~LIz@meY|v6Sl?dT&{jDy$?fC?ik1FxPBK&!vaa({JN;vH z^ncQx{>M=K&r>+p;0*Qz2!jjzvI}&nY9c|K0j-CZz(AC+uA`x(x)x53;J{I1y6MAr za)1s-Amhn%jYki|a+&BF^hzL(*^(wl?2FYt7XFxo=>n#VYr3D^vPos4*RX+x=e5Hl zSsaBqtq&1hFm8Imb`C?LYQE+0DNexv$ZHs%kO@$n#0U;k^vN~_fwA)5*-vk#mOj-k z+*+-l#kp*?H$U1gJ|c|#wE19AEdCnk+VA9+{LpWkqdJnE=w&E{gc5^+zf=~~w zV-^++7M`b+MkOi=VYRa~aw|FJWyrSU0iYB$$jQq6X%&w99AZ@CUsWkX{JFywogz&) z&ZwQYLlYFJQa~IqxYL^{c+Hf=y@BaVC~c}AC**>qFK1s9)_kQ$D15H!_npU6c{^O; zfehdzx^m9<6ybrn*5LfaTtUFxkj9cwe)7f8=Tr4GDS8R)M)=up=us43aP`{VZxf1M za#@bKC&Qt8$Ngl!psw#laua{t_SgP084NaaUMteJ z>zyavbP8Z%x#bVOilhnQ>56;^ixGuN(RiKOHJudNNW_?yGS^w@EAUY_I5@Zarr5f=?)*mgi&gdzakdC@Sr5}aO#%F_fgtap%y>k$ zJ(z?^q>1A{N4Y86jI*@Z`~Z`!nH+;5-QW4&AL(NHrhFP+aSlOMfTDk+lYeykje*+b zYX)kZ=6zaH%z8vblG(`!5hBZQUdT=QRlh}qz||ae4hlu)H#wPY;AZ1(dl_HMUJnx{o%|q~e1o29#v((*ZD7$r{--aUmcv4L zc|tR+m_GqKXn@{|OA3D0)#~U=Hio0Jq9%F)A=;qK`4036ehln1gLalv9|C+tm7c{T z{-*4M-T{Td!HOKFRugJo4ID!7FKMF3Q-oFzecPpO?)*~((^1DMV^q6v8xm*FK%>7g zC^^)w=e@e!&!~#8^C>=epwciAopW?-*&M6&>9&zkc!voLgaItvc_IE z>{Qo}xe%45d68u^)4>!LNP>#gL@e*!f-WK)r`EHRq%F3KI!g&Wu%Ga^5T4DGI;cbS z&ZYf?neUy|@_|?e?~s#5!`+Y8q8OSKbT30{Wbk{V`lH2Y0oi~H1DB__cAx5J3#lF> z7hL86$IioWLH&vKv89juOK zH0@509_a7z)X4w@dj@9E2iF31)Sqy?-d6tIhi6z!`unf(Cw}x%p%_STxHe^pv`LPn zu;SrS@Us%*CkO=ypP;hob<9Jna~m%VW^%$e_j<(k#+`lzW{lHM?0}RRos0U^r!;_Z zEKQI*##;3q^b1{^6y5o6-sbg7DX8h}wf>6isK9}G`>zFKwOaNT>HaY$4+9aow8ti&=G zdLJ8lcl|5n%h;-kGbyh{VEH@UeZC=~^?r5Un{j8Wi*a1nzy%)3xg`zYGLa{d{s2yb zT4Csa3)dhWB;lt1%nIylBxag7HzdC4U(+aNp)TxG(QJgoW6QD3s66JCtI(f-q$Av= z!>n^vIqO1+KlzZ`+`f#~&)ZE|>Qm>BR5nKjzwDPglXzms7s=O#3R ziZC8V2C5kg-I>g7zQv?lA|FcKo1Lp1&Q_M#^@KR8@1zCWYTidLoGm^6==ZXrnW4~0 zJ%QsFqotUwNt=jt1goc}gIX8erYBq7CE*ej{k$!6>(?6N-MhdF1d-X5rFpUyf&lbcxI-uKmxZf))3Ax;}k z*%U`eaylg|{`~#arFQxC?p;JZq(`DY4d+i+@x94beH{$6(7?PnPWhm@@oaSK*{z$F zhG$Lb`;au0S~qr4fB#|Y<$)Yp+iN$tXL{088574(U&BrTrYZd9D2fd>20zydUm7qy zwW$uxyyO4)o#?!fsML2Y8x?|+tp$YFUb*x{xwc0_>-Bc0L+CxHt7#-FZSqI7Eja7n z?U4R|-W=$65Q^N>x3CfWvw`>Y!WGV0?)MNT;cp8$f117o2{6RM*+~|ZDO}tajP}>b zQOvtXcbuiG8Xcm9qi8Z4h*Zq6q{LstQ3%?L&GF8f>YwG8!Fq^vt+F6HiswQI$ zBm#f_nD$JQzx0U*-_AvdS2X3O>d=MD635t<aDVNhZG} z#lCDPP^}^Heen7Gw%CUUudlFj!D?lus)jNFo|fzZalrUt7&Kqy0wvg{GgJ3Pwudj{ zQFHZAVbMU%@GnEPA`_qAgd)`79gk@6;_%z_VuA|j?Dagu`eA}-1H$bzc*of}Ly2bC zFF;2AY);s+ZD70F&*ppmPF5l7yNlaH8qFkgGuCMY3)%~bv0CJ4%YMCx<{bzqd@OS% z^nRiCgmXgQN15>N>A2~3PNO5QSq3{l)k@bp~+Qa3))dmX4q8b6@57n zjklECbp0)IyVhm}80G9rf!hh{inS-?9|1e2$>q*7WtqU=$3uPA7)M!OzPfCUJR4)M zbx@skq!Cno<0jk8dJ|1vKv*!9G;T_fX&}57JbX9&17vp{AhV0yjZ(P8fbAMoS} z#y*~^^cQKIr@y;2e>jx>qj(&?SOMe~RlsaC1y2-aZf}k4wJ?tIKl7&S0e`0F^g1tb zo4Yx8(oD@u3y1Kd_)l<(j3lAT3%_9gk$;~t$O=vxNRsE{171CdP|_%w^}!(GPZwR{ z<6kBQ+XU5JUo?^XcCA*ReBKm;`Y!dDqv8^St%vG4_oJrEr=$}-mu&c;lyM}Bt$YRn zP~eAPuaj?DbN5R=i)mOGH862fxCB|B8fH3U--}4I|^gYBZo1!9;X1W4I~mmFBG0LtXOyG`2M=~^BsiuHV`~p3ycmOws6mq z*HHfxiZyC=~^EALqe%*t2s@jqd2ybqlu-d)i7GyMZwc?(Ol;+&N( z&2Xr2(}8^CP?RhGvlg^!a?GI~OSIgXm6)$S>dgXEk38YPzONq>Ku{v6Uhm6~zV1NP z7MmC6+=f37(N3wbRBL-s%BhbTBOt+IM-qRZb=n6OY10~A$(hP}wMW-Fs!si73Kk^h zOH9hN>HWYg1!eiD>rwUY_dY$Vb@(Oi;|yp-p-TY(hH7>?|1yExreLRP#{CHzcSlPz zt)fz@>D7j!hgaUHZV}eJ)UEa!J|{~D$TWEdiRayCSn7+aIyU@e67KQ1VQq5RA}Gma z+lBB1nBl4QB%n`GMkJtX_CIA6P6vB*#o;4FZ~V04|Hz{hQsfHV18X$wFRdbbO=EL& zVw8~y+QQ@7m!AMYKSxK{vGL3IRtOESy;6&YI`QXSHXtOrHmIYGa}m8Yu+#?Ep+r2- zWlh{6U^+?fQp((vlgT0QR@DsEBwE!t5KCOT;?-6NG9CP!^Ce7t#HnVuHo?E;^XMJVLjHQLZ#NW#yq2`H zXuAp>oIu_e6WSBP<{HZEhT%_@mwZA9um8(*CxcJiTBq-4TGP^Ju{y0tlIbiO4@%b- zg^k%?ZKfpEfB*6uDw4r94ibM>2a=!LpL>E}oPYq#%vS4XL=C+2PqGkeTe9Egv4_Lrih4n(@o(-ZH2#pkPJoEQ#=%4rP9`_R8HHATqP|Ifz&!J5$)u5sEemHi z{KlgO&E5N!<2$eygQv)R^bg9M34+`49{2(3JkKxL4~D@xxT6J762H~QwS`I18>JA0;k#+f_fNJ0`7b?-{06uenf28D=O3ob`~i2( zzyyN93^qq%-vf%{jZvEPm*3en2ES&{#f?gEwxT_ITWV;xn?V#g@gtAWwa$5)+pTeb znQl=fJ|>EnSA3&?C{AejmGa|$J6Oy@bg`|Ai2v^mwaf-+W`NvE!BOSrHxy}CCzg^1 zEHP8o5zDvnzn+Lut3#fbJz-i3Rm`|?v%Q^l7SNuZcuz0>H2T%kD_jXz+L*6e(Ydg6 zdXrk8pM{ER{0-ct;lf*6sJ;>kq>JyP4wcyK>-pwD+{$~uFi)@u?>Yn< zC-Ex-4Aqd;8Q&phH|4v{~RLHXM+pb$#5WB3Zr-9 zxf@Lw=SG}OKBe$R$`KHyr8fg_y$)BD_F=jL?GlV@ZcU>#d2VfvUY^S|j9{?ak+y7# z1GP^OyOoyK0*xmvwLhHbTw)xlyyK+tm6Nj#rj2pn)BW8<-8v#ug!b$$ZU7HGQBE() zaP~m3QY;^e#XeTBV%;Ryf58%uyfF`DKZMKSpo94@XBTi0H>ePBK9d<>TN;Fo`E^70 zL1%*XHUy4Y=~cHKo2cnHxgRHk$YZdPs75xwm40hq7-?0)O+?_OWor*0mu;x8Yb!`IwW$u$nOY=+979bL&I_X3hatld}?|}0L zfX-`IE%_505?jG;^bdtIhas8fEs>g0T&6fF^ZTqn{RmdPLC@?H$V0OlUAg!3iFr8F zWSY)WTTst}3Q4PVY|tAn?^&^!F5=byF6c_CnAB!JtJaAS_|_w$2QH@%e36pg&d~HI z3ve0UUM12iTMLZl+bwuFeKxlk3f7&%T6xLHFLA>n&JDt%-NJpE)zXtAub z=y`|NSny?v`+m3wp03jhk=dT|q8+X|G%euW6nT^3!BxfBXO2RkVTG-Ipa?Gku?sRB zkSBn=(gfqUL>sl=`2XRHDlUi!3C?_nzRqG7ZDRZjAMlgj+Jf9%-bv46!LI^b?I55SQH z>I;D}CAQ2yW6LU((>Q={NxUat8fOlXdkb_%3JT*4I*}LNsi#2m*wvfMcrW6XtVD2{ zx4jOo80SrYK+$&%fC&CphtY1L8lK<$ZFwug7(8R#d-9=)G0gU3VLP$huD&S zDlNnX0NhyS-Oo?Ehk8%PHd~AL-t`qj4j#lQ*?*uF27vju;qG*n_6AVxRD8JKi3;oR zbMA7u4yK5k{wNW130&Lq?ysP@3tz{`DZr#DXGIPtqI>6AZKFN3#LP$P+On4oh5I-U{r`GS&Z)>L9i=8 zwW!;KoARqWR}p6|ClnlObIc;AH_V>Q{%|~VTs-6c!~I9)ufnYPd|c^2bh zDc`RF*3R*Ft9oW{z4F>(ncTt^Ny5DiR9@JKwPe)3%%DsjnR^ps9janAzz=pY?}6FlGJis~_@tU0v4n3MRzWyuQ^P z9>V=Rj$=59X^bLQ6z)snBs4&&w-$oKtVhDRm+}S4qpJ%HC1wmgMPcS{6<3eIG*{EU z%F&1p(8?D6t8C*x^c?^7dq`l?f*QAYfTOJ}>@L0Vmdnx+7Dgl;wo)0oS-^^cq1MHh z*mF-a{xTt6(}o7LL>~+j`qr#{8{3ywg*OkGErP(KDR;FF95QUT^&V+P*;A=k2hLHN ziU3r#LgEE5Dt*;Mt;I<)W=%qh_P(mbR?F&BAj`0psZ~H%%bAMiMJd3Bld00MU%Ab} zK~#V;K*^FoZzMB1C2(?;!!(rNvTvvh2K^;{FO@X~$l}L9aKdGzgLckj>z$N<@@FDz zIwa*PyT_1HlBk2DD}-8NlXQgW23=J42HbGR9Vi{73GPmib9EB*_Bi_O$ow~;>bq9` zOdINc>g#&x(0Pr)rh*$fvp%UUO+gUzdKb~7Rc1|lJttv7- z@PH7g${Vvvnp@?C+e6_4omC+r){R zW;$zLGMk84G#^Za=1Po3r=bKq%rCI0GUJo1K;NkoNsNIj$znNXluO@vGbpwF0oWyZ+;YWp`U#ljijA! zXdqU1xH3A^PwB-L)<=vbCy>EwW{4c*#Fzs64~e1hn1aiV6sJlLK~QQ1K5p}l$Nbfe zL9gd~ufhv_uYMQ0tPw@H1%huNE&}T|_7>A#lhX0q<$N)vb8hukYKrPrgFWL$jE6pj z&Oy#su1ZNXVqaqG4m#n<3qV8tlGP~QYFOp)sajxm^LC!<+XM2zK}p?S+fAWVjadB3(undU0wwJ)|(tCkdqLE-Jni$UXT<~l+Ux6U87olDH*9B+I0BH$vcTYSg&K9lblOxkYio2K1BU? z4fXnOdr_j@YC%qO;0Ni}NOh-=%@3!|(zj8p!$}+3rx>%^Cr4X7mQrn&ykCBp_ygjz zk7%{FneE-q@MSv*ZH4xQjv9Q|5JcB%*Hpl;47IU+Y-GV%JJv1{)-kcMBK}mKGb{NB zki^Q3MJb>IASu%U+HBy=10CKN4dU-94I|J%?j+BAEnj7BAQrH>q)*9xLuH=d51Zqp zGuIQ)i+OMn3AnuRpol7gkpt9)Ld%Vp(@!$NG;XVk_A>qjAb8`HEk`JCsmrKMif@*FN9C`Hq_}OP`j+!p+K0W5|a0s^61hX^+kK z-7=Amr{NBq$zFFIEk-h)X)otEy@*h%Dz7DCY25Kk+C}wCR^xv(G@Myk2`C3zG;;6b z4fmA1fvTx>z%*}~8033sPN^|S(mO8gc1qxAG77j;T8H}v^L?k87e>F_VqRQK|9TZw ze%+3&I>k7xMoP^F)dZItIrk0KJ9dyi0SdX}6_g31xN^Kuc#FMO$KqY?0 zX*<&3SFzOAM@6Uf=iyqvz-JyVF-}{MrsLz*dQc*F?@(Lk470%pJ4q1BS6``uKJX4X zn4GYRynMJ5Zly7`K0l4{3y!XGpTiQ3y;GoPEaoUXIt|m;iu(;{fhATG&t-@oj?Jcd2NULkr2l=!W6hovNRJ>Z)aF z>pT-?JDnw_Qw5mr+0gtn?y#l2xez42@`R9=p+{%PpWYwHFZc4p&I3jx^;Wi(; z6v00};tmfEAJnqaxcipGj1|?A|D?~yL_6PbTtB!`x^H;Nc0O(vcqeHvd z^`*)b!@xxRm#_Nol*%N>gxs}DFL`-chEb>7yrsi}QuXHwxp2q@M}CV__;{3v}i)q>usr>FmJdfw?Eo=U0F=e7+teejJd^ zQ|Fx^qB5d+{)6t?hT#01<+r~47K~o65~eZe85j=K&q5IQcDM&sb^~&{hzP6vuz})E zzuz=25*%3-E4T7E#ZcSlvS)N*C>w2|ijL4$3+7&wjHOxNhd3%xF?gHIFK$!k4U*wp z21#OE3O_ooJUUx661V05F;r2kzH}QwiTxaz1Z+t>mn9gX?hGx=n#@pDI z&Lf>6Ip)@nKL2Iv|7L~r_c2sXzUXc@7g=~F!={iq zQkz2IT=aNJp%X#vD9wgh7u64*Ub4#~PT`?;eU*$zpr@cf~ua@Amc(TBq7lMlGh2{&E zzyw~Z7Nv_kQ%zc-ag>J3R*!!55A)Ni;<}<_Gqm>>Kc}-N`4lz%6|$7xt#B&bizt#v zWGA~5f0dO#rWjkaj&~FI^k<&1apa}#o4(D)rj0KNMZ5fb!5F|^lovI0AdY{%;BpMG zJE{n$Z*`D{%#1(P5-Z2*-u_H%Sf#Os{yu7@a)$|@0asxO=T+VZeaA_6`}(q+wVt~IQGF}M{9C4^ z=8bJ*4PoW`BM1Gq4ClHut|Ip20Dw{$$sVp9q1ZpE-;4DJQ&pZnX7nIxdkfjEDWZg` z={FWfxu&PhPn&SNgR8&<$>MJD@o*u(vwFA0O?OrLjj7jZUJb8w{cvHQO~Dat=|7Xw z%O8Ri)j2s}eb`!1Qh4tuP3CHG$iS}wHpB;CB|9TV2e|HHX6?D)o2w4|xtdKl&vaAt zB=A#$LCOFs866Ir$iT3_4ZpC`K5%#HoNNq(8M1Dp&p16mwX^+A&W&w|9!ODq8~c;l zEQq@wJLC?r`fM%+?@$4IDu_yFwr>UPLuzMFg3MPfdx12<<7j%7{980lGNCu=?EvVd9Q%(mP@bIZitf-4*arI8lUxXm+lE}1=Z9ds z<2AxnI@l6(X|G*_jQEk;b=@vo0ytH7#-#Ibg1@mL3+Ua6xtpwGw4*7NVt9u-fckkq z&g`0802z4W9{j2?y=cS?aFX}O4#$paV-{3ZI4KhG1dr0WgipkH%<-m6T>+jyI5mAF ztrs2XF9Dy5#Q6Pmg_mBJTCA=kREi!xKq2$dm7qrsf$HAVO5}pn;@QQSl7~0uFMj*B z^Lzh+_p}E&3vxv=`fEe~3m#>sbTqbP-|g%Y6b*=a;TGe|W3}E)*a1zMrlMEfDd3%Y zGml$9VE}_Y4xLURIJ`$@DaN;p_A_e8T)e~efJ+yN+1=joFhB{I$K;{>lj; zCF;aSjzRl)4972#uZnv@Glvj+~H&*7<7KBv~ zN(C)UAIQJ^4XX3*0wuzIz2E*pveoYzFy=f4anA+!VozeH_3>J_Wo#r+ zwbUC)rq|@}@4WRKa{rz=&S=zB`=nbG3^y5dn63VWk&J_tWY{M~|XCb8Sj&**%bHS{}veqML=t=+I{XVc}Vb;IoRLGS5i zh$Oj|a(kLpTXJ*?LH^1MuY`N--~GR59QilVR?y$^f5lqYz!($`igx+SBy^LZr4BS^ zs5lv--|aLh<$lqH8#)m2bT~me1Xg-Xv(p zgB(Cs!*!?@;i@FlWX5&I(1HwcGEeT0Ha|%p5pl&)bYbShQ#(5UrAJtblztb8mu5@P zq&Y33kGmnuH#1dI$dgqmt#Ry)`Q)&zGahr`4AVjtFlz(=K@3GA7x!|ZOzT5@N=>MN zmGkM9u;=KleUb|xHHh{N2NNx`aG(Am5LT;Dc_vNF(j{q=l%FGrz!a94TO#Guhp+){ zQOX|GFr1sDWb++}{h5f3D~BS>Se)uwU(r6lJM&>heuTk9Mi#0Nd&L%dN(l+wZki;*HTCNqC;=HD$MSGYxh0vZ zF$kD#byjZ+c_!#xP&pwIMGWf1p3_!f%%~3$jK2i??sUS=j?%P%Q(t|}S8_i3;K38| zy@H@vlT~01R#kTX66Yt{`W0`eD8@-HP zZ|X?>0nK#bKuN7Z9@N|7+o=JI*f;jG2|tx%D9)`9g>qtWAGZOy9~=RqdzxKTn(xZrDo1 zfzNYZpas)ELjTOhl!oh1EHw^8w;#@$1i3k~iyB#)H(!^jVsG^q_{#l&(uYe=vgeqn z<4hJ|AN9@(NEpd(rUa!VdUUKf`5JBu(vBWeRDb(pD_9uLOSShw5ua<}>Bb{RBco zxz~4m+YtFNmqKsq1<{o|MyG+I3xzg&b{6xC6~5j9#*(Ccx>HuxjN+RY=5r6COW;!syQ`+RUq zkG9;{hq20MZpQjP7k@6EP53<6*g#C8jnk{bp&le~C!z+?hvjwSZ-#U!lOl?bO0teT zU4bPlm2DH#)N-K{zl10d;omF-B&M$$eYRDXDo49l2et1qt3z}(tX_%3ORF_^4vMr_ zPQ3uQw;b5zS`-OHsqI3%MA?}LVDvRi9COqn&0vqJBp!tQQ#&BAa4`# zDS`j{SgVGgEF0@ljfV)O|IciFKJ@}6>`n_EaFx1_&dN?&BjYMLMh%*{g+A8+0W5Ys zsZ6k2z*s@k;KxrzgUZ%uK)DQR2XO|6 z=?~LxXo?*1wza;tH8`V)QTc3dA!GqPK1a#KyTr;*ky+^l;d1!Aebl+&rTf)fdQ?1B z$#$+c>GVdT2s4$9s>WbTE)LE#qNnd0XtD}T|E_P2O`OD4LF5gUYb3ri&CoP{!kmL= z^Re=-QdGwd58|g;oJ6J*PIYXNXiBy<_N-EVHvU8zB7c3CFarVjrw$2+(GT?ZG`(C2 zkSXMX2fOFyf&GbdhfWdo0B_<=k?zSas3L+p3xvjBKm!nh!LU&$Ey0@-PnUL)0f0C7 z7%rWM@dF60lrDSR=_#ko{+&=Xt=ggW-b9&8PvgQoZ_fHH&?``_cLK0BVrY7Ze2*lV z5O7nR_&$eh9vl}I4FFNqy2l%In?Dx&(zlh;D9AGO;>U$^6htNC*B%9sE%gXq#MnoL zeR5Y8Nl?%n@HFqgVr>kcHrr%DROGEUE**FIETrbeLh;klAAr}Y^d+k(@WOhAgEL&YyR1~}cMYaC z0ik>sG9pc(I%I8od*N0}SVLO?s186n;ckDK&bh+R(ws;qBgDD{(JyJHF5;icK5C{t zwfVGb+rLwnt$DsNVzO5#iRlkG1;U}Jghx}P6*}bft<$v35NF)gxPiU024oq@j1}0r zP>JL&a>4+gc41QLji^++*)^skv-1-FQzqvB^#F2ZioveMBTaqenudUxvOVSl+)^#W z;4CI!l2)Wew9xazBNWm+EBKDwpyGAM&s|CW$+$8YHU&Uiz;D7E+=t(f@1}>2h7I27 z+698qxS@@^<7+2!Rtw+MfeQi20hnmU8Ocx`{y3qM+(f(SmtuTkE<}pnKK&$}zGs)m zm_^h)v<}+{5|K}1e?BxQtJu?sG*kPsTC-+=ov8s<2F}o%fuwrL&R1?Ab`>|)I5~;= z@Qoko;UTjkbD1k;0td)r^h~s8IxB4G1*H!!(&Q0T{m*y-gv?cf*ZPnVAn``RrvYaH}K7qUTdvcqC$>VjlNqvflRqn8L}@uOH+WfgiEW$ zOSkI!6?+^7%tVP@FSlvLTnL;C{mT^E^7QML?{fs(HJ}fD5bD>jt z?wFv2XJDs1tH#t}czF7zT`kewMkGZlEdCJ=9It(qbkT%Iux=D}!$*vCG`b0dyc*;B zt&Qo<8{4-+Yb!VREBV-M1g;vbJ`}Vs^^vu=YzsJ3?Ne*eh4|HG%HWwwmG?)g-6!$l zT6O0JR>5L>AA?o6Ax}e67KEleUw(5Bo!_{3c2Y(unp1mUB8CWP-2mXkW68vF2J!Nw z)m1oYW8|pkFKN``O5=3rmUj<=b0PuaZe>$GICDB6ZY z&TprS>RRv)K%Pk7NrB$6rBstUZ#AagY5Kml&^px(I;m-nOLc~FcONlIL}i?%GeS-- z?{7Y-DEVcRXl62P$Gw9hRb3_)OBT&ktgat~h1zz{T0Yum4MG*wJ-A%~JU6CT@};s@0-apFU)h zY|@>=!wBfDj-TTbP!8=W-Fg?G%w_M2l0c`~_{)h7$V3%{`q|$JTI6`f9v4mRwi?rP zaXhB^mSwLz?byN;S7G`s;#7MdNi|CuJImi026ODLxRd^?GPr9|y9B3U9HFbCF;$;& z&F*LF8~FXYFC89D+8rVh-iy@y+uJfKlk%tl`V1G!m@Mq^8_dS|F1S#H`(4Ko)U6)d zn!)9qC?5VLP{msTRhb)h<@NGEX5~X13OA#2an85gn{hat0JDdm9S;wwL}j{E zF6i<$Zz~Ge0vjC~vVALm1p80F$5Cv!ncimJt7X?B=8AUIlF)zjj(Ll4fhC ztSgsEjTdHRUPK&zyucyncVkrlbFeAdBCi*ti44KBS6(~5C;GH6^Ousn!;(Uzl|4sW zg9qJxb?@gr8NR3YvAtCx5ev&#ZGZL1@#E~vkv}}Qkn*q61X}z0LHR-IK#%4J{RHNt56H5>atKO@4Uh$2}sfRhU(L-}?+61)k|V?Vyh zs1#yujVoge8Oi?gAB{S!A!T+1qRx;WP6nE_wLajQy|66(or;=RZMH8hbInbyM;6-| zIz>2%4jv!5ZYcKp?4zvsOEHjRmKU=wnsRK1#V3K?!RhuY6nF%&t5^G4%Onl_*_5~Y z+x%;pcbB2-)JYL%HKrG)4t7BVcIvHgC}rORhZYFNt$ZVH=X*6f=XiVF3rr$^;j_9c zJsU&yx@gU9xo^(VFLQypx6KUhQ8d z{(0ow4zNnb80;bk8zt4VPzGg`9mg99gfo`t+U zgi+OSNsLAS9w6tswC}{{2E6KNYlyG?yfk!RIVt<-Rp`pUIcT2XIYuJ@m*vGWYcHJb za-U4;2B5W!FlMD#E$g>KgoEL@(w?0&!8<*C`sM)ro2fZ`HBNzAf4a+Ow~3Yb@yZW1 z6JfO;1ctu{2rNfkL-tD5yEezB{L#|eFHPHY1$4?5 zxV%G{B&B%Z5wkVq`7qGQA!5s7ZXS|itlSc#mXP)Hg>`p(%tfL4oOiu?fb?TwonIG} zfv655sIhh-)8L#avCSh5`*qm)(d|D2B=?rJB#i64N&o$=HXHi;sUdhBvfKMqxHY{f zJcuOO?yNr?t^+6MS!OG7e{&tNtrm%WfBnNH1=tU4%{sk^A!;8iu>WYpp?=Iu!Fs)S zMK9j#Z%$p1;W2Y#G_o^G@YyM52-qoFI z`qAHBM^a0lTp|!R2HlspZk3iDSs@3Us5-8g+rbEGNJ7Bjg!;<^JgNs*uN50_>h}gs zLiWT3xM}JrUKe1hKOt9|2vZ7A1)rOpBj2xW? zBB<@;1}nlV-t~hICSEk76Sc2JykD53eAHRxJai63&;q|bz8NHKW;wmj8OPwKtd#5f zeVL(*u1YyZ_O~~A62nwNCaWSyV@54Ll4-~ZbYvo1+8@n}SPO;nzHd}hKAKxwu>U&E zB}k<^g*nGpH>lt$5lLXLSZBG9o?6%*{zPBzutNbwzy7gmb_Lu@KVHX&B)oN{Dzj(G z-mY|D<=q9i^#pM>iWF~OlY4NR1S|2H^tx8=Bf5R$XTE>(DAi$9C0rkeNEP9IG^wH> z;BH}hHQLtJ@O4Xr^@=={279d!L#a=S73iG^Trj#x`~4&=)b_s+_uf%Ww(p)VzA7jP zNEZ;I(o~w#YoaJ!1Vws@fJg~NdVoMcq&EQp0RibXM0yV*O}bJ-FA2RT(gK9M^ZfR# zJ+seV`>gfOtTSi+O!BNn@{rv3eO=f0`~6Hz3dY-2lH36K#px@bEuy5!2d%$$V7*oC zt-ff`#DQ+KsS8Rr6k&qjdAYd0(|TjBKau;(n)IO3rKH*6$=iHDmt+_}OiHkaGI^DG zUc2=0yu#XJ+oP%VVwdG#=LH8l7hJs63+J3}OgS6``v>-PuToYugdX&;ETe$WW<4LA!C)YJ=(bd{xYyVY%O4X+AHn-{^-S;+-k_VD!r9K`lIxRKVv=5IA zFX}fym=KPSJ`#9VYJ4c7v3DBu@95h7I^62A5xMNLiZn?3q3S@~H)x>@#^VKZE!{o_ zFHa&bE5d5VkanQB>2D*4qBi(TUHHp8Q_tFQNIR7V@L^(qC1WwBj4x@dMUq&i(yZVG z2=^-To1a%}E0vpj_u4d2q!$pc>WKj0@jZLGcr4ncc>*DRJNtPfU6PcOOfM5;=NjlZ zD7TOy-=U^Ai>ILEtuU^iQ|6nrB zX;wb~Ta!`RU*7|!SaqK)sYqxT(W3)6w?J(1{{HeJsFk|J)p`Cz`vEnm@PK`F$f(`3 zn0@F2vO1}N_ymuRaH(C0P}rHT4B$^Re~|w2rHr*nOU=+Y5Wew?W>0-v@yxfYh@?Wt z7)y~2*CUXx&&)jba$}!qRaoS~=yaeZy4B~BV7xSP=&=ZhL)+Bp=E9EmJb1+R1C@3` zUsddUzGv~XGLYiG^0w;H9pb?t+FgY1V(jytu6e!|+xI_)ro9p_Vmw3!GAg+)WFN(G zvfRLN zi)iS1Z6Fs+;(J{`5GjYkU^z5%k=xs`Q(0?l9{;xm0`1kmKZ2R^ED#OJ9 zFDBy;C^PAamc?;;a$eWrSm7;{K>`x0`&;1cp%c6VGkwv^FTQV?*a z;h_e{*_e(VF!v{yv5B9vgo$lm;_#2t!?*%l=^B<9t;DX|)_pu0a*D`S=r?ccWz)w; zExu>9kj#HKgx-5__kv?h z3U*YYrBb-*9UYa%*Q?)YALLPavnB9`=Bk$Tmv>-->d*VHg~fNPfeu_hxP5^VsJ;)mFEtY# z%xbHbeE&)ry3|=wYajZv_O7&O`~emvC$Fro3J9ZusFh(GpegswDKOuL01ubRu2$&q zV7zD*Y)j6ML2g=i5R^vDx2`hR(%o+RdG1u9-9@=VNbRI&M$*F<)N8Q^&GBunUd(;r z3p6>$Z0Cl^FEqh$|D${7spN;n?WG%8RNov>`OKX{^a^U5?zH*k{XHYCd)>S=graza zaKK_V$HqrTKfyeXWaaXoTr$r)T7HU7_y|=ZftT)r<7dVeapeJ3EFC(BVT$~HfanP|r9!!=a_Xi%YI#128UO14cC#VB!ear1!IE@jZtDq;m zMNt_wl>Jt(+;C*-%a5NNH-t}@SDP2E!;w#khLK2IHq(@9@rG$Wvzdk2^BjCS;KWcj z+`Pf^2*hHBY?o@Y>DLa+0$njb(P=)vxj7v^_1&dx8313LS!2pc7Jx@$uRWf&XE8pE zOGJSo@@Ca@(Ht?Ofsf=}lm3T77uy`E3W%`9y`Vs8Qs8h0$c<^Z@FF3{dUx=%%pr*?mIFE7Ot}t z3}xgw`qg%=CfP|LH|G`Y6rT^{=o@IMj^pEi?tF*%G^oQ6!$pd;5y_saM$Lt;(}XZUB_%fs>4r-9*<407m<1A}8t3ea9czt6r#;YY~0e#jF0ZH*!HOyTR}rmC*dU72C& z5L$@SAjmW*h6%TmSA(uBfB2NVn}L^O)QRRW4%e;%Ys`e~Q))u2!#VY1@>WA%mw zG8;iAkLdq|G$X}a6sZI$oOLiP;Gelt-*l_aX5H9^HehS=9|wt2{aeRQUMVqf+)qR- z*if9-_%dG^b#tpc`EROZsz7)0_4xKGgaKia6vEF0hnusvz;Zsz+?Tu{RQ=#05tSXm zEA#8XHAvS%LUZRl15r6V zO1c>3g@WjrMeGQEdD6rlVg2X^P_20j=SEMcl#n$J02Vk0hPQcKnuf4~YXX>%596DY z`ET+b_Q0t(=lfqmA6)3shgRCY0u)WP;5eDdQ~4H)zwGO|ybj7FmhMXaL?^XqE$NM~ zWL|ll8NOty7cOjjOtB47Zi&!9o0qS(bs0|vBxs(Ta$#1sDI&j-YJ2xLGdXT{-8qXpa0u3^Qnd z=H2Lc8T!OI`K)AB@$@TG9Of`$jS4WT7vwJY6*x#j;XD`D+W-!ppYJjuC| z&0L#l^Xj*SE04|yC{0~2xep;c{(2Mvz-ByI@3pI)X^~2#>n=3+k1+yov9Y$OhVXcLZTp{vt(=Tq*%6G%|V33Hn zW+t@|`o4(=L)mU;`sn8);yHhiox?Yt;1wI(gUlawL0@n5R%|Wm%!fGmlmwJ|M{Pc( z7H~PtPg-UP+=*N3qCA8jWRR>LuY9<@KkEVIGqwCW_Hu1+x+TOfOHEQ$Dq;%c1Aqc` zkqrEP`aLyIsjT8tqfW~3;gKTJJnYgOiL)Nqiu@#Rh1T@e;YcNuvP`4S>doudRGAhT!qd;x zf24nsndcc5th8lZ2@}wPv40Y=dYKh2L{v2TmeDbtZlPJbr|)3yvzB1VLcsbr`wxDL zm(aNWMb@)|JAZCip+%IL#|FQ)omZ%ePs7}|hfb%LZA{SFF(#U1t$Zqe>UE-@G`8d% zC~36Z_#vr$8_r^AWeND=U8DWfV_N7Jv#EKc%TZ(w8~(p;O~q}l8qWSnfqr&TS~^7E z4f%fe>s15W$$_Aqb&U`SMj~(^i<#tubC&IzzlfD~toHy6QiE=!|*7CGn$n8tQID$V@g@wy~|l&qb(JKqw|?br{KVhPro4q z2(NA}tLHlOXCFJ~eN7tqr+(>w1(*Sj(-7A?@EM#=Z%?XVX6dcNzQL=I)9dI?Wrn^9 zJ#5W6_|(eT*~5+XWgncWdzUSP@)v`B1aI$|mIXq%fz*cTA(&nY`QiPZ+aG%OdZN_B zQq5b#7DHEuiC*Z7U$w3Amh13<3AXMSYy*EOY~3@7@qIrh(@x>fJpzol#td@kHsTV0s>_PoZxb~LuL za8h>uk59HZ_{{AQ=qr@)Z1AuCu56G?i;zcgG-xM4!q}~aPn&nemo4BqjTRt=Jc^C) zz=D_%s*C7rdnp|qM+CEPL*Cle{B~GO#(k^<&q-i1Cvh!o*BR&#G8v)u#XaQhIksx-;yNQE5!p{o6b)rgdwX zWEnGGgy!0Sp@}H!>HBYDnpy> zMo|3C!-D6TbM5>I0MU3%DgdN6ekYPI;JIFy;5&&tjPU#+n)SO+Zq*6X#kFdNqE-uI zG52JY$Nog;$P6PBRLMl!p=iJG*@gEdz>a`FLa zPFIW6k5|TPE;$>BQ1j_xl+TOv^9G;-wcr%e?cxnX$~C(CY84+MFT7|<>gHO@wkfVC z;njYX6DhC->CmfiQ}j)WZryU-o0*M0VE46Cgvl#CDc7l}>hUVLlrrH%uHhl- z7sM1@iqBWl$HTOb?02GoqzkQOPjE7!C+i$%&OZ{EnYytf*jRb}!`C4NtUUoV!@h823Y-u^TKI5~5GDWth2gYZdo||F zs}?ge@FC)jh&QL~NBGJ+KfCNN}P*N|U^!p8Epy$?QWz*@;OxZ?J z`0BS$#K2n^WW+K4eNtuQ8NCgK>li1fhQ#Mo{Y~|2>rC(K$N%e{gZ~8RxcE2rKQt2l z(~JKr57$~WaRC>*PM@WNB1IA@-GdiTZLwp!uA;ig^**H~r&hbMVR zWdTsM(AhLW7^c^5tVnh#W9Sj$R$+wkw9^83+vI14nuNpQ7|FW5!;*j%K7ufg(;C2# zMo$4!>QRN}95OG-0f(}r_jyb>L?s{AAsTI-vCYbS31mZwWYcJAd2ZzY9*n?$Szyxn zjf!v)SBuxlZLMDZ_s+sU-_`!h(5bdm2uWmRz45$E3TDuADjw>@db(192Au#lxAcW; zKv#SLe;n=9!m`LCp`-h%_4R|G6E{KM6r-~ez-hn)DZyjL!&bT(Y4N?nS! zJ%mABi{gfaL8jL9&(kSFGgBsgM7Tdx+@tXGvLc@L%o0Mn%0~c?_awYk8V^XDiRp0f z$pkqfAa$A;2Dsz7paZ*cuk-AeUHL)R$8M~4_Hu!pMhB}Viod1uN}rYZmdv7hlK9IT zcO5UK+~}|BZ)jLc|6Q{@Z2qezi!$q4of-aX9CmiLp^>=jzB8Jn^|Q~PGumreXa6Dp ze$={6s$qu~ztvUCS3u674NuHH!8?mX=v9epuhZv8#IuZd!9TbZQ7xf+>M!zGj3#Q$ zwvg32_hKmxZIiRKrT zyCJV!T5~TYzd^Nef63dhho3930I!2kc^$UVQg~x)I@fShyvnZ2t7)vqy?xS0D80IH z%QP#!TSwgOwE|;zoz|9zY~}F6?A9Gzt*DCwBoIEVg-Cs;JQ%ZgE4<%{{mFY(ub1i% zCv_{f7+KpkL`1)zNX{An!p~35x|J!9$D77$nrKwIVmQ3T-KTX15=1f$WtQ6H$_MrJ z#%j4Goqca7?2|ly+7WY7m_WP8Wte92S znrh7erI5h}>up9GBhg)POEZMgD1GC|{&RZ0Uuxv7n#3M65zOmuvxW-q+f22J z8BVYTY~#vvI-Ipa0F(69r9^s(6>?R}B0)G2%elQLV@VB*3#xasd=nSt`XoE?ROgPH zo737rU_Z8Q&nuqE+>}v1|GGxY?%-R`g(sg?!|w9`)TzcN5cG48-k?h~>N+W_|MBaV==?8W(VK_()FK3n3Y$LbbC3oL>-pcBpUh z-ix?*pI3s+unijvWC`qmuwm|yTt>U6u?zI;vYV#Un!jrH;|3BC4TcnEUFj2c2TRts zYl84EaWAW+!1n?>0>ufmQ!=6D;t}8pmys$|*^k~ke^XJ*LZGIkz)h^baHOb9o_%3t zRFhl>Kr1%N4)0W{@%?J2;KH4?u_*pQ#se<6v;^ubSsiI%gSj1PyD|SwRp40vS?FiY ztPJiQqL;C+fp5>wH4Vlq+At=v{JUJ#`rF9ULJib!rZnn6y-~LPn?P(;((u=cYRM7s zb+Z0w3)8i9nTqNTJ1-xej@g+|pI5K$uG_fPhR_}X>Za=Y;5M9o(au$ZP$vL7<}_=E zm6>RA^|%!b%0Ao$Mn@u(i|%qicV5*#bsCPcyqdtQuEMlm8}Z$_^_~C3@e6|WD)tyh z6O0z&-*+zhbubaRpZOE}`y=vx;;_y?-`gOWt|T!A0QIaxVY^1oo|?`AV?5<4$s}Z< zLsMLBv6+K{PEBfReIoyZ4(1eJeveRtizR|V;8Ehjb|VfH1im;*RwdSV5;T|S)nUK_ zEI_?GFGIOEQ)#ePwYJi`w|tZ(N8)rSD2xa6vdJr*mhV0e3#+*NW%r43J}7c0-RJvW z5QMiVT!%!5*Ul8`l6cZ~Cj2Ve-aRi_9r`ItA&Zn#I*4;aO$fzEJ2f^e}Kh^)UBo3 zCG!^M@e;mYe(rjEiOuN*qC08>YKsDf?v8kt{mH~;Sv4f*NL;wJ?tfenr_1TclsDsx7shxg9 z1sJ-Gs2ML>n8X|AFzdj_zjf{j1W--!-kuQ0*H=d{*CB-cXn&4-DMoLt`A7EiZe=CM zroO|xpJXYrM6Hx}%QxS|HvRK*he%^%+igb5BKQJbf`Z+`!;(`%6b0|g{KTI<}3#I30@_x;%$Au z$7p4IV+1AZ#hMOna{m+%c4O-EcoKqHOq=dqg0Rl$91Tl{wuAhq8);hn%QkAcdp-DD zDi5WL1e-JDGYm}+DG`CAcJI73dr}xpn|<-o=azzDn}(KWnngBz%$x9+*BehB4KJCc zBV(kSofWsS%!&D4Tk!?9%TuM93BhhYNaZE-%_>R7xQkw8DO|B+3GRLw`_<<$a)Y)< z0~J%vrHCg01jI|L2m;vPzwh?lZS)^lea z7qu}R7h98btRIwc?#tt4tz|Amy<7L7I1g}KpEr}+=ac7do+y00w7~l0il&9ZviWPY zR=3RbQjzc%gYB#UTuYXlXgeo(ye+^b9o^w1%MVi0Qc#%r+3vkpZx^@1c&EX2_Hik$Oy88QTavsncRO-Ftj_lV-a9IrW zI$>92dY-JdJe;QI?#$N*mIxePUdWb zvP;>)mU7Jm#!fov+OgYDv+nUBW#(7spPhKL3lY0Xin^6F39rQJlqHY&0;sA|*_(kc{M^XG3WXw5w1@?|O@ut|66DDPjQY}tCk z*TyoHMJU)2V4rayVl87+f+3{^ItHMf}6_VE(dRob>xcQ={)yqqGGsB8Y~ zvciFQI9F;^O+1UKBZgI$*Y?wIU5W22vOPD0zs>%EbO%A8E?`avg^8WVjNKr*Dof+7 zbV!;9yBf(=sWzg1nP$uKY?0m(|9e+T`^=$y7qu)XpV2Uk3UtUC&R&ks{eD(_3TT8) zm)D;~zjJ|Kh?GYUx{`#^Qy>iztk{aa-+V6g7J1&1T76Uw4GMchX-e2!5+MwJL3d=t zE?h(?{C0tg-b_};_-(b^dn3)gUh&q@-xJc(!%s`;>d)TQm1Jo1j`tiVGveeuf9}mc zE5SXG2brD-y)=;;e7QMj+|(n~7oY~qV-&7S+bYO8Gzvn97R_$-mORTCAigf)5l#X+ zU7oR$DvhnxLY_KbvQcu{$0-u9Cp}8aMYAx4^A9)nU%r&J`G&6AA%k%J{*taM!sLd_ zu?9vJVKQKKQiy{MuGMQoXV%@l&yTUdFS|XK3+rG@H0Zw?%xhXG!HyzdHr_!Xzmnup z1!g}lc__UpQ+pV)2fh1UOx(xRH{)y6vuj@6j`lkx<7}P*;kbn>aG8D;W1Sy0Rkz+6 zosHu_>`qcT3Y*yDjv-FkPsv6V4li9le|n2}K=?r_GfH}C@?>hG!>iMI1FA{NQz3aH z9&+U~b-BHx%@fyy-AA3NT9+f_Q4W&!>1B_lx>caGuLx?eE!}W1)9*W@x5r%S26iR- zItsjdH*)ChJwVI{^mjB?T2(t={Ndvf9-?pqnR%33<0iEYoOnLEZCGi{dAHTi0C!-3 z)4az(&-X&ZI*u{%9xK&2kugrHy#Q999#G!#=9$WlvKs6@%W?YaoSXy3_Tfu2+PFh3 z87DCIp^U%v;Y+d>0UIWz`03YJK*g;$i4Pk1T>K0ji}os{YQP4BMy`n{5zk0gbo!#K z(!|`+DQ_mMpx?^bK9W`Y{XnZDQCd{mI**<)9wS(gl~&?3YC}7mIEioG3$o;lHfwIg zqOAwK1180e_|K$k9-zVOIud?_<#pK4* z9+ET;LefH*@D{-h?L|2})Mi7VX0RsSVD=<8XVIExRkx`wgG8Se?AgDHABy#HNky4Y z=e#xWsPVVkg8Gpdb$>|#dO?T!>CmXT)>)Hl{m1uLq-VQ+oboCY-!d{zZY1jD&xG2Y zb$V}E@+?03Gi$D~wmhjWos#%`mCfpnZ+r(bv<`Fw;xH%l zd-kv!w~>CnLehuXplkOcy&^6c7yJ?3F{8fn)W-GdG3-P)zA`TM`775HtH!ZHPb8bC zG8l3NO3K!(4HF)`M?aGI^)J55UziTit6N9YzgCf~B%AIH8)sKglv94P<>-y%rKB&R zyUjsp@z94XCEWFS><-!~m)hz<5!3zMU^bFyVM^U^@Xd9FfR8md)#{T}1hdS2?5=&u zezFO}MV-HJLPQq17A(w_3u381&q7kU3OUnSW#ZF;fUL!g>1nv)QC=nBOr!1no9Y|c z*#VpuP&n7sL>F$~|NU(w>9&S*(M=a=`$(t2+`w4{#tw8S2w+{{=8!7CQq}7!nMg>j zI;NSys|_FTXmah$ee(E%erB{TyX{AHo=jn3lpBKJI7bLQ72tu-AOcelPW8vb%7a)o zfq%NIfrc5$9Ly3*`h-NMfGtrgg?G|YA) zea1JtL-N3D+q!q{2J@Ze^|PJ1UWT~K?khcW|C`FuaN9@0;Cu5#Zgn^WK@Euw@V6z5 zYPLq4S9O`Z4{03|K02GxFQt3ZuH=tIlDnK4ixKpTKdpWp z1XwLGKk=ZFOaXPz!G+ zF@z9d?`Wv*w6G8*kbZZ?&$euR5c)lkt$EZ%lu1J(XWFb-X~aKLlra=-m7z8+F12Pj z<0?4PF)Doo{5Zn6oSOJum7*2qZzV)>@=e$2S24%N$>QtZ*93rB+rEjQ?BDhOVzQK8 zY*r_#M~f!^I?Q)-X~sbw26AYLZ{%qm#BJ z*>J1hg%;ZCuF^i%s-TX8azGyFcM~i=p4jKBg6L3eq8;^mXMdX4*~X}(_;o|};oQ(S z-8-M6biTfa?XPuRhr)e~0~9zB8=Q?)ZrFxo9d%gV7GntVs-S{%cfIGGhO?(;F|I@4 zWF!1>FhbH6Cw~|#&GxR{SlmD!m8_#O4N`)$cj%5Ips=FN;!%}XRz@*Kv!kT~0&9=eCzL8g!sNa6fd+nE9s!2;7 zF+14xjm&9SJo=H?8{@Zf=N%Q;KIGN2aq=HH-6AG_DSlf070Cmq*rNl|0T|Y(g2pG@ z8P3X<@Xjb)^Zl?x^DIfIK?i&S%IMKQVE;#l_coCmSi8W2q|&XfEGZ1-_gLXylDG7V z`QmT0QLRUTciu@K3q@$(bbp4I`_x?jh*}dp7f%vu-Az8zMKBW4?eUQqu8|gBd|P;e z$UK+p^{&+u_SDBo+x-fZ6K46m?OE3s$LdtPzQp(+ZM0xsM8NsygJD{@#KQNiyH!NC zbW)h2RPvof_+B}&c4cn$e&UST@3K?tl1Hot|36h5|FlQ}{Xh8W7ZvqCc3CNY?Y%My z3Pn8RtuO0w^Wg9CEa=<44=l$gj9p}G1#|0_(aajVg3!W(GLfE=O)W0hnm&znS>k*V z*Z6+Q+Z0tr@5CGX*tX=hiEB3AM=^VuwBC(nI15X-^oL4Jih6x^Y}as~FS^R9Thy96 z8WED{H*uUACZAt<0!vo+j%P+CRmo-ZBAyW-9m?!$ot6sYHX~A7dd;gDx7~YaX-WV9 zM+Rj)%1?pkzF!%0$QP_|+0h9LBs+uJy5EPNjdr{zWGZ)LX|siY zs1FX`0-PYGt*67?fmcbYN)k_SD7pD^xoqEa0xe`M(?)SSTGPe%=0YuXbw0xB8>xD+ zU*G0(sX8l`ffTkXEi~|wBe((d>2Ip57h1~>s{vcQI)QtMr^QDHH4XPLh?Nw}F8LO` zKda7%s0yTqie}hW)QUO!=l%LI@xnV{;}`@Ayg(Kw3`a=EYImRN&zXHczHU4-TRy>Y z`EjRxlwT#jO&UPVW!E6dtc)G=x6X4=Z$_PJK$lZ0t45}M7!Wlq3Qr$=Z>F~BOlWNQ z-sSO*Vx%DHRf_WCX_!^{VxVAG0T#YRpf4W2%m-XRe^uoDuoR+v z_xbP<*E4Vhy@6=zXGl`KtA9S-I6u5Jct^uhXd&j!-Hj~RpeamoLon-9@Y>p4H_J># zL7&3Jv4b5Nybd<$jc4ku$JJNnx;z5!5x-2&fAnl^kw1xw%S#vKg(c*4PHDU4J6_*3 zeD?Dw`Xh~-D7AEc ze`$25Gx%r#>0~Np^ib?qf48ddT10JosZNHR#v{qmEv>6+tD@^dK}x#CBu2B=v4m$S z=^q5;^OUcwrEk_k*f)$!J?m4P`iigqnLHmI*5Wd1c$}q|q#eLFJ1A&O|5JC#vJ0mh znc|#R8&=9SeKh%+ZBZ_NyRS)&F^cRaQ&5lrGtY%E49Iu6V^}9#TNK|_PbMkZtlC-` zme(|jN-)@gSlfim}_oKGWFdR+vR}i-v8K_{0Ze&A{ft4SQ@lJO>RcBhOJKS z0cfpLMG6P2LRbEt`|zd8i=TBl%kK*arWMGPr;lWPGw`asO&}hcmm9)zasRa>3eqhEc72mjg64F#k`^w0@I#v4v?NJ^4}^ zeHlpG9?A|L{d&R@7H7OPRbSvM8{;*nZt-XFmFT6{b&N}4Iq7@fO(QZv|RjJ~^|q%fbz>o+lyvcT$zg8Yy% zrAZT9AA5i0takY2y>HRxYoAFI-KLg#xUE=)Zb64x`f~q$^W!kl=b?rD{()B|x`MNW zvkYH2rSI?x6QKCjG=k4jIUpgxe|lUn-y<5@Idbz#P80XjjJB!Qvi@(|UQkPf!tj4-*y6L+LSRP&4Qv1-B9nN zrZV`5xFC;B%t={0eAM{Um z0Sb__(s+-ONpJ@os{P8oZluYHMO!Mlo4jeK*z>3jzpMgRXV3mZv)(^7Q5NsBI(LO) zD6cN;$zaw)ng0owY?gXiWw+3F38-^`Y*ywLPFtI$^S2X^h;OsG9zSTbx@HuRqA^P@ z$RLH!(;S{oXc8BGv|U|?&NLlI)ogK_fh`IfDk zc6ioxQg8vOs{P-hEV3-1Jd3&U zkY{V>3g*s}l8v7fWGeGhM$>bxPoo-#i*UPmvMPHClDoUJz5bF-$!cBTP57UM4j&z> zz~-GdCm|r5^yodIoXV0VNF>JuqsQggzQJpe-+98N7k}WF%lcPNV#i{<^3$I>*lc8i z@G%P6VItcguY_8i3_sc>vKPL@%U`3W?4_N-$_$&9=50}?E|OiBY!(+$0J9zu6I;+) zHc`75WoVkY{VcIs)v=}Gfg;v?bA_)Hp;~4}ilV?)XAKl+573w3^A@r?TyMk(*%kN4 zM)@n37`aq=K4E3Vx*bN36E9+0GM$}0kz$_mGrIfJ(?gF_L=>_e4@HgetPh_E zO;tqqMgPHWY`BZFtSOtW?*7qkRWlOhZ^=%bZyjx4VD~(!Dc*iNXN|2470;qqufcZl zG2%I5bH_cqYrZu~ss-*FrNJS9gz^KdOU5Y8irKyA=BuXk_&IQRD=FFfNZ(RZzR83^ z<=(Q1ox*My0466c5c)UMdLEKS$z zGgm3;cT>RG=2^zKLldQ(TuLzvLoVztSY55+Lkc9V6m7Wnm{esi(I(=cn zq8=2EDAD1?Bie96=Y7&~!sC9fCqm1MusZ`@f_OCvsBzCFn@s+8W=rJ>)c(trI>3a?WdMI?gf$rx);- zQsx=3FXTgf&qRU)p>y(dC%nnz(5^<$EyE_WtT_D__jP7TYe&hX64tX}HXqqpHUDcwr>HOC0g!7& z1uaIG;Rb{%JN~qeDBbKXlGe^<9lnIEYT>wIlPGh)uj5(){8n6dnbBO<)j86|ZYH>J zR}(UFx28dQa=UlI!BaQ&{)77+!awC8_tt1C(UaLEA+Oc=uke{Ap&h=$u9DuxGCE__ z)4Bu}w~GTxYx;ogqWn6QvcD|WSadiwP-vlN2{PS`^NFZ|Mx>{93X38;4JBqUc^BJ7 z3%5ufTzrUzWp~zqh4eO5DeN`vy`cZ&qnm$PO#Rz+pud0rhdIwhn$9){%J(sFXS<71 zq*9fi>$Dp*8~K}&X@4_qGrQ?c3uY~qVsPU*gufvE8%nZ|3#xuWW;ChND}S`K$dhn z70*QVapU6yu;LBxx`hp{094Ox(!h!4nB1s9OrqDPf~*^G>iL_E zT3Bv$Fwv&1=#m~y*5(2`Fs>Z(Bc|dH_V5sz`Ruv5h|!_?wbgUH^AN`uwu(0V+Kwu` z9?U>6+CHZ*ic*3uS=-jenaFgwI&iuA79Hr_y$52X%mAd1uQhw`(+|;IHy!+jK4Mdk zgmhH{B-Yj6U0l^|Z8ah>2yX(n0;qMsLh!;poKSas=<_N^Ka1AZy80XqJe`I9^OneG z_$Q+X^W@=?0%pX-lIvCSOOouF9{Clq?Y)wGaXigD>9HwxK_^SwA1?kNGWqEVUB%T! zqcLQqP%uUa&VY>c1~H3E#~OIi8}=PPZyjItO*eDc&J(L-fBU0HaQS5lwM`lkucc^26L91;%TR z3P;HmQ&5t%$(`{#AGy6hynRIZ(JI@O#ZHR!DYPUT5eueg7Fq{hY&YCdOan+S3Ar)X zAMOVV20@+x0S(zxG>hV0u0f`IU6APd>4L)}l<#@w)sc^tBWb`~*K|FnzPgTapkaor zta-5IN)nI_s>$Xuhnsa-D!m%@dSCRUdEchK`E`e)ZE(juh*tD_ozKu(z^0jvTi6~y z6NG`70;dF<@ms=McT)}pyn@VT&9Ce)ueso_fMOBIvs+sbCh2HrecbSSrNAtnrj$+L zGG#7@OKyOil|J;M-_DB$!!e%B{*(-m55i}B7elp<0c1j8Ol!L#cPAZd}05g{3$4ow5f8lbiCkqQ0 zEU3#eE4y~M{gW}?KS1k^Wl^u5It5|@nkKMx%{uq&*b?qPg^CU9|5WA@=%IwaG@)Rj zm;Pd7_gTNv&BFnFLrcS)=_0M80W?-^QM>VY^4HeaYSb@~q^2^^4vb($eTf# zk0%G#QznY6DRq%;xKhfMZ!dUSmmL*Fw6o6{l97%;pFw3V7c~8JX@#D434q1romqay zG{gXwUq|tf2Rf_-Ah~c)vK3MD1F%>eUOg`Zvzf6Q)HXLzeV2M=%tJC<8=_3zkS$B2gu`#I)v&p`9@p?8{ERw3=E*}JYKY) znUZA;;wb_~mEK-@;in^%$w-jNO$cxULUp`fT5uhrG}dm*+HEuyf$A7L?2SeIl+V;c zu297wx5to9Poc&j&`va=E625FT_GW%VH(BWzK1QDrA$H?=Gp!r6n$33FS^Cw01Vpz zeZqv^I-Pyu=sU^HRqEv+?ra0n!j=c{ZHl>%s!1l`+O=7d3n8Eq8=A~NP3R@Qo-U` z7IQW-6*vi|4HNLsrkzd82&232d~rq^Gy_&Sonj8eQZ7$>!>u=EFC`1U!bd_J(NuFY zxwH00R>KRt){6o1WhOuD+3%vncU~+$aj_16-2C#LgoPX%9c2tdBPr;qm>MBAn##!r znO;Yl*~$TNTk)4U7S1E(UJZ?l)po)bYLa)$iPNGb+BX&yFCr!n25s~uRt?o8JL`rY z6ODEr6MRfa2IUAyJ;{iEsG#IgFLjyMJ50cr$rIa{Qc0eo%;q3v;bEnV0Dk)!!61wkEcb%i$`CHH1SIE zt~e~=D7Apj7crhSbwdl&ktMup!ta}zpB&xHY@C#+TOuvzByv|hMbN-;sH_>hM>0Bl z>cD%SL{l6%0Oe3IH~E1U3PV>woxF{%X`j3VdQbE2MZ1g1PS@;~7}@RJNig$u zOk9s4p!nj1C>Tt3IxoW9hjV-f0&>VYkcgUCqt2#x{^Iv<-12E^jFT0VV`9Uo@vRO? zLZ@C`?|?Bs{_6@pR;4sJC194QHrjs(>`E7QIiQ3pu*gOgDXG)w4iCrUI#vJP)c)Y7Hr97uzty}! z49*G=Uih2pb^LpPuZa;ss1U_Uh<@zNgrW~M4rsf26_*csxndv`OGg~rGU=UHCyEE`bf9Z{ex^&|vVmOc^v z#1&KJ`yj9PJ+u0DmGjiFyYPXDbBk9Yf{i%Q6+g|evK^LLqF&I&szGz~>5F&m#t`EOlqw689E68C&_AUtP?5(o2?9KgyH<*R#A8pXOVX zR6uoDZuiL5LzZ45J2c2w>xZW>^O{Rw;K#rU#NEM0x5ZI;+!T)EcK<0XEV^vVJu|cp ziJ}3R?L15mUB_%Adxli2-Xn>pJ!j7uUs{TCR+0Tk@=R)@v8VTjR_u*{{iblEtp@rd zzr{aRQ@roP?Mv^9*C=Pjl+h^WZnkhh2%Dv$G?h2@VMs%G7=L|& zG)K(&w#pae(xI?q+|uc?&ZYCBK>D7Dmpz6L8IAE2OIztS2ju(XXY4u<{qUPEOi$hZ zrb@WqR%>KUX$phv2oMSeERAOP*cW%`oxnB#)X}d5w8Kfr+)1I>Vzfv9w5U+2DL-DQ zt1#&rFSk03_*4MU$#3{xvq?ES4xzqHwM1Nq%5y$@Oct;G@>CREP?!Aho_*4-GsNNG zd7*t}Br~$(5m~^j;VaBS2gRfNx%Vbg7zpJY{#oMLHZ6{OsV$;_%E~1Kf3S^$tgOC5 z+DC6ipddS!2~~Gvyk$;5_HL|nLyr6gtARhu>pQdOT+2T5BeQY|bUa5VIrgvrQqNLb z``vwk^Q;o#Y@C4}4FzIWiSQ-eJa)S;eb~b7YZu}M^!YDHW2+TjSK50O?c65#4=0E% zVqyvxle(^SFf0hmY<9*UC6HjOu~mJfFN766W^h_zwZ`pp2PVe&Ho9et3RfzR6yE1< zr~j?JYmbI{U;D!-L?*!X^fh z!3gDkXNVaRg$y!AX2$#5>wWioc4wV+*4b-y&Te)3Z`RD3-+br!KF{~^d7kI<8NdUF z`G`Zj_Op07>3p+6<~G3A%*JpREMVm63E%rEW!yW@=KUEhpLx?_bRU#U#X;If`Mqz3 ziZ@FyZqx%-EeUlnI)%TAi9CBu&wMRS_|?gVZN{g7ns#i2;#@|C<(c`wOYBe@15V91 z+PG`kKm*hi2#; zx4rP)Cd6B4UiK(Ers(C9SVSV4b7%vO3wk_)>{J~?8XMqFO_XbqM*O<&W=J1Smz~#K zMb1JAnyYe=#|^eMf;<+hPqFXNV*`vsSdI;ZDzv{9Fg}vgf{N*+&Y9f%g3JaDI!fQ<} z1tyw-Xe=Fx37f`^h6n+dB*GCSStag1v=Xu0%k|{M!4c_Loe!R`gVK#eVAB(X#Am}> z7RHMCU8g_kkXDwRfZ*1P4IpD9nDW7j#zQ~u?H*1wV57jLCF54s&t~ls;8x_h%R&Vd zd3UW!x8kdy%P&Z!W;3^OHP|sb?KmQekNAR3^`+RZsPsERZ+m-FYgZ9N!Kdv&c}4&6 zGmK{v_QB@W1yoNl-K?4B7%?Z~P2B+GVd~)Xv_Xa9q~&AmScmORqa9F^ZiX6r&+y zBkMUC;Jj?pc8j&c+=fw$QVA|W!occ_T<5aiUDO#&4~#Zbo0!~f!VYa36DBM7g=ifwaKCrokn?$Rx$;Igj(@#(s(@W%Svjqp2%?cXW zD53Ylz^t(*m(NYlJX3zXI>Vfn5Z!%%PGU_Vx^J5OxB(@KRG3=4cu`?hiPOt-?Yy~{ zkIUMzuBVgQUWu3IM{1!GD4|u%()y|y3EvLmd6x<>!cp$Wpmb+!E8{u?aHocXOQjL_ z+BS45-phlfspGV#`RM-Xr!~=y;;2KE_B$Isd>KzOCo#^GZMp5&p3HUyv`_BFpG9%k zERxD0WhI=r=T3S7Zh#CchwfhOurJg%_NOwcjlqlpm|G$kJ&557 zfJEwP#N~CNwnbZ^&np|^_{92mK=mmifb22E0mL-h0bRw8t<07$^_G~kw?ZJDve9oV z9g%i1R|Y=_#X%2ah7Wga9UOaojpGfyL|;((gKYIZxtgRG3SuRPn%Nf}v~ka$EDq#< z8eXcYJXz2CY7SSP`!N@CleTx;mX2g(8y7%ZUVC|#R@=B{a?b1{JP(n$YS=%-(z}4{ zRriTQ2%rpST36ei&%`d9ImH+%-OxNDa>jFd^4w&MZdizdCm3b4nmW@Sd-Ntx@VwL?ohL1LVu5M&Qi_aOE^+@g1*<0NA33BUY#v#88Ar@bFxQkeS zN?4Ei5!4(fwy|uA^#Gl|*|wXr7cI}~ZpW>XG8YY1Rg8mrTX?+Kc3(Sg0*{|TC>us; zG3HnKmh}aaihQ#9by;3WDzHq}b9(TL?N%VMJ)q#0F{NaV*-UltX4V)#yyjIc-J`m>YTXan z(9WDc8W%m+x|`CyFucoxN(6K4>d+HEr6bJ0;hLN?O(5Z{HHQWTmS0vIm`Q zeXo?>_bPsFHOUc+_SN6tbEN(BJ@dwu97o|LW4|p+w&TuI`Che7AqiUZ_^lTpBO}m$ zA3^Mup80L#mHN=9-nxF-^TZGZD^l{uTrQ|v-5P!6P(x!qE*l--5F)`BO=OW96i`dk zvF9~$*5{J4LR$)rxqTY-CBY)Gyn2U_$uu8;hu5dUsQ9$8RAuN}#rpa*VS^8?dqB(x zJPA-fp`5A5-agQiyxKX76KxZ8EEue^f9(!e%zIAa<3K5`PE}#X<3CfP zFoTw&K?sqA9t>m4I;bur|#E{9dUD))9w zSX?92ZV0f920fgC#?ldN8V*x=y{_J-F(U`wY7P&n+-Y>j#erFUjDQ4g{xq`euU zt}$3vUg}a=D{4DnF9TLsXbSJ(hFF@6N{Zt5!LDNB5yJl4;&L-?u|5Hd%7^KlS7j9{ zPSS{CKPbeJlCihYS=%Ob)IfmXuu`MsBG&z9;|jMFrn{eK=dW!i69~e&5Wccb+tum# zfL_R05Zqz3y!@lr;aG?Ba6cs+bzam@%rmgK%>?`)mq+6tFEcr}e-N1r`rU=b@yEQYGmpjn%Xye5XktR?X z=kRqc@Kgw_Xa_U~XL4?k;p2X%t5-*3odU|EGe&5&b#^ef!I7WVCnk89iHg^0B!yK( z!T$~9D?-`-P6=5QQK6k4jd_$8iTp(-4&3*_N^vGgPlA3b%+%|HKPQm-7?K-oV6hPk|5EdSxab%r1BC|VP-Wqnw@r!(}mfTA;-v<#y`g> zUq)$kZFpqqB7Ds5R&hM@iB^@BxgmcZ+JJoj&pmicItA5dop-QCqw#}US0@5 zbuN9W9A0vc_L#D*g{xS}1KhhyXgFNN!@;wZNfl@#SM+LtKHb* zgjkk9csKyn%SKCOHEYWxw_ShiKXF-L8=?}^T}NZ5Xs>Mqh?YlvVjGoL6|d^FGGQ9# zHMu`(Ub$T%nV`b9aOWY-ILnir8Cx_uedbOHg76+P)dZl`$TAKePInoo zBNvAGLrxNRBH4|=asHwT$2*RW>jj?5&Fm9z9>H2xBCj7g-pD`TlvRx6x(;V*86|Ne zA`slt{%OahAC{QBN`5pkhsMh7mja05hRgKEruYZW?10w$#vE7Z)GM))P$)qql9JOO zWNm8r9;XUnq?D_K(ghy#pYEF$+k|OH)n4 zG-y(MRN}y(D{T3E3nufd3)`|Ok_4CO2g%42 z5~IeIw-fF=H6Rl^tcXF51npqLl)bxP`e5S?Qvtq*8XxLhFZ8>BKQtUBmkda(n^xsS z8OrcgKz}L1lldsQlJSBad^;eEe$498^DJ`oAEt!Y8WNXcVJcb^)Sy*t;h|1);@-zg zPO^O}xnajK3U(kk7tQ0yGhNw!cv0A4hJqAXWlzziqew~7)YzachWxMGaP}Z$jj2rW zn3^Ko9VlaWern5oq2!Ts14`qAA5wipq~EO#R)X~SDHU4G_R8M!aR5%=6WXw!G$PX& zeyMdsc0`3Kn-&76oj{3J$x(M>tNfv^v0#9iIUfP09Wn;g$nQTS4oK~QDs4d@DQ>ra zP;l;BvMiS@ePRfuElUR}Hg^HEpT8<+zahTJ-T_UkYp^y`$|J_sAC70=ngA~StwXV7 z?A{{cGuvE=Fb<$EI5St-B>$bST-yF@dF*TZAxP)`^K?z}IEP9Bv4UOl7vA+P%UyRq z2LB-ai{~Z7_Z9NYyJipH9RYNyE5i_*53L#UtjUx|5xq_lT|1zO1`OH3&LKE5MnG;R>B{$T@c}@f z9-AfHQbRqM4oIWnZ7)wy?HKozCOh3JSuMUgVkytW@5t?dq%2t~nq`E&=A_xQAO`O@gN_Jc`1p&$g1#i)dBpT3Lk#yl;8E1{Gr zxXF3wSo*PE##S!p!{64)j-JcFk45Mam6LWrM4N|He+JfYE1aAd3An`1+k)+|PYQ)i z7ZORDO$(MrLWEwPJf0ADjSvVu!onvM#&#z9FzsjZtPH|8A=N$Y6I3Ne$@Zl+DY5wu zIekinWkFG3-v7?gddsrlQ)^p~;oCslLvm{hU6V5Lj3T^1J(&nRrz1HD-3tSiI?dr| zNOIAA3y}NA{66D8>+S!4))PWkOfaEWby@Lm#~!Z1+)o$o!MPIu>(SF z1?3~cq3kJAtU;nD?4u}q)kdKi85SKSDTb7v$;yp-y`&ueSL1!rnnK*5ciWnDnO!)#~IG%d{m z)mY1Tts@Dh93kCv{cZPnku(RV+7_A&ZU*?G_tK^88}3r{BBhxNgUY^JH~r6pl2Kwb z6V}_|%?HFhc=Vk##+(7K8HvMiGeukPUqA~CoV`W%yaY^8_Czj2RxTpqwKSa|lhD955QS_(Q- z*h8h9WhBG~o&AQ>dw4M)_jJ|K;FL=0o9T-*P2>A>&pKsuJbN%Cc^>FH__dO37HOD*zL9>Rk1NsFqLMP^#57O~;?|N}j z!YB5~W%LX3vc`m2O%JNX-U=wWYqXSq4EFfPw}pR>h5eg9{Y=sh;2_$^8n-9GXbjAn z4k$u=eaPUy*&5&W;~}3BS^pWrsehfq^D`5im@{*5nb-7m&5_9X}P-POLRvx7e; zjrblw-=MF8KWoAJ9zb6-fW8uQfW^LA&^!dyWp)Cx#4t)bwLf@|dc03!=nn=7!p|m)Qxjj| zFTRidqJi+Y!G3@BpEE4IjM1P64Vp#J2$bG72?))Jz0GC7Q~lVF4Z7$K+@blS7o7&T z@UnA~kLPu-0;L=tG<-fyboNRXrG4hy((6Jx$0{U7c`nv`=;%kB>cyM(f#KbeG9r4R ziKiJ?|Bz9Jd=4a(hnK=!VFwlv2LLhPBLuWOu4F@=j7t6xAz%H{YA;IzbfhW z4gM}doH@|Q&nO^``1{0QpXwF6`j#y8nYss)m(PN#hn4dKP*3Wt#fl7wH&}Y#vXF`F z1lWY!46M})JcDgp=4we_b?3&8e>!8`d1#OeI(0!rb;{*Q!zB$OL(OTznC{(v>|N$v z@WSKY7a7>!V;=JD&aQjAGAf#)edSr+*szSL=(iV_41Hw`9ABbQ=PSz1{{_}%`BG%- z-;Z4XU*`3-Ar0SwkZ<2PzXKuv4Rid*?&#mQ?*H5=`P;YfUvJaD146#Gt>mva&^IuG z&tZsf;1B&5{)OY)1c#o2B9C)|n|?Qw+v?6%8}pdt?q5)sXN}4ICrdJTXZ(Kv^9R{5 literal 0 HcmV?d00001 diff --git a/bsp/nxp/mcx/mcxa/frdm-mcxa346/applications/arduino_pinout/frdm-mcxa346-pinout2.jpg b/bsp/nxp/mcx/mcxa/frdm-mcxa346/applications/arduino_pinout/frdm-mcxa346-pinout2.jpg new file mode 100644 index 0000000000000000000000000000000000000000..b282d62ccd1f635c334edc06e308c241ff2e33fe GIT binary patch literal 794767 zcmeFZ2UJttx+ogDfQWRdQEAdUC@rEQAOa#vmncO#h)9!2RC*T_P!K{D5ilYp^higF z^e!c#Nlz$YK|=EK|7V|l&lzuwJMMeq-8aVFV}Ds|Fij-88xh zqM-qS45=Rw1p_wK4|abH0-2bAq(LCiDG(zKCy0((qM?33Gy))ozsn$yC5_-e%MLV` z{!xb(1fu2oAN8Z%LG=HqPi+(QgL+fH<*%0h@ssHd2*gDFjb2e%St*6)Kgu+;bfDb- ze6OUam`n3NTFj;W&lXurbLsxG%m^xE{6`&XV}Ao94c$N9F#cD(Y0mr)ylHs<8{Rbk z*&2-q?LWUoMB*Rq{WrWRlav`y1eI@p0WI~Sqot*#qo<<+Jp=t;z`)4xH!%JKnEr-S ze*yD9;qU*ZrKP7{%!~|-|9tpSwdKN@WLq|tTPsc#Tms<11UreXxVBoxuwBco&E6O&WZ80_NG^2+L;wRQaN-u?mM5I8!f_JaQ)hx+`#(ZfNd zhnAk6j-Kf+dT3~as5c!4J;MbhMov9*rbm8U7nNU~;=Y!WSJA>Os&W^{Abr%zGzCWib{WDDu&kKTF~8!v3pYTEKv#5)bg07HHhMrngJwijP! z>#5T0C-UswAbT%N=tcX-VbpA~DV zrwD5fyEOcKQQ|QqtLjKFdfE>aIIno-$(gxEEt-P>p4}?jpsg=8xU%}bW(C6n#+eZ8(pvn9lqZ0`u!@jMEu0qG@)Oa8{hU zJc^NR7nb)*dzDB21KteFn0qJ%X`6NIyIS#Gb#D#G2s&N5JbQ&fYYAjvcI!~!5?yab zmxJO3W?Wc)L%zIT=D>w;Z{~L3Cs^aqZ(iHV3RCWCIsPcq1ZtFZOR0I(W=>LBo~cj! z(-S5yA+X2V=UjHmAepo>U&-;NaKSmQd}%)L1AHf$+!V~T#f+b3e|^^Nu9;f~Wcm={ z`e5%=m`e*w9h1L$Fx_x72!BZ8nP^3v*&h(_n5KXt7o*r2+*Q^OeF831K%*_-_cJMv zxbPpQ3%x! zOx-H=7HgbMg+Lp#D4?TF^kEkTq;v3?0Hpt&|x|X6r=a98%4>Lge@Dn-xpUBhJzuau?TTjw}i#@mLV#YqXyv`pGGQ3*q z<6t}LA~LtXsBsEDv#q`lv4UlhNB#q^qFp4OTnC}DuLu2+odMp`4F{2&@CvQa)7~U4 z76)K@TkwS>SwdN1+VQ=VO#!FP`K~_QyLwAj>r5^18RB)I3$F~1O4p>F?)MI^Nj0pG zP)UIdHhOQ~<8N~k{S_k$KAn1&X$;1xy{_Q z{8ffyb9U^cr|OH0Jo(pCkL7>yw1pCww|99gk@FZXO_n5_4ZPHm%vUb9i&aYaq(<2zyW-6C6MOSAiA zBeJEgKH|>>%nl%j*eorFiQ$>HL<2lOPm)vzB~yp0OA6Y*o3M(R=8u53_Kfqty@{S? zS$!IJq6{$O+c5K6GB{`(1l-IytFsdYdr;g~vR3(1@Wzg>=JvIrZ>OV$@9iUZKjID( zRLi*ttw1QQt*ye?Jr@YSTm7*eb=SxJ?$OP0RuzN8(FX5C!SmkI+*ZdS@D}Z&JqpMX z9sTy>iiwK9&$@Nb(%S>ID1pj=;+tj|bGVeh9R*}WuD?=MXBA53rGQkN2pzx_7Wt9_ zIwRW%#axZDsXiqqr0Lt!7kK(~0DU-=t)FNX_IvBIXUU_&4pnnm^h0wO*IiKeg_Pgx ztShqdjaxGuf=>eRh;oQ8Iy!T;eLg~6L~zhy`U+#Yr&d66q0+ts{fVVeNC)t9BvS3> z{kIM13hO`$Xluu3Ji9JnC+|30i1A{Gh)9Twv~o$myib_j%%@`t$W|n|IBbLhs+s+L zd`8wWRdD>MyW+b=V2-bKG$DEWWw`QF@T(DsoCTz6b!%QEK2+^jHuv2we*xyi$fWM; z%uH{rh!%%Q(4GgFw3`%A!-OwiAqCWCGvg5KCtTL}-nuNF(4?4kV^2M?FM!rn*Q|Gl z0%|(!c-&OH^~w(u-y4!XY#9m^?ds3HPt=`PntpU~-KqCMFW+|Cr6WJo=}8iiXaVlU zFQRcm4Je?T0%Gdkg;xf@CBq((|A;J5Kvlk5wG+o>qK4MDc^$16Jnd+`e_G>ZYDYmS z#>`r-2-~Gj7ZhSQQMDygHK@E2@@rLXT-ghBcR#%q4l{`Sb9N3a`Sxjc^ z#TvJw zzl49&V^AR^aFUt*+<%x&1>^Z}eZ;DSvDs2~NS~+V7o0Lg{!Rfc6l99k&m!776Y0vM zV>l05ywS4KnnHoymlw}FqUFgf!Ns>S2<1&f*~8aF&JO8}KK)92NvoVZapBICu=nC| z4h0klZ-MG6!khrTg=9Jp2vdN~e#zHrX0y#KCJqGD`GrP3RgxYxuC}?}a6~o~h%9!H$JjKB-`=T7a_xl~g zcMtbe^J>=)qlu4EFlKxxR=r?R&cbXgz+EEhimUaa()E|0d-zh^xgOF*_9}MWe4C1Z zkjEfgXs_8&g4d`V+SzdearSX#CBiJ?fvr2SBJ^A>1!P!P%^`7q{_y3%)w(74Q-D9B zC~g6^!7ebK@YeM1Ep1eBQ(Y#iEFUiF_~f0(>bYBL>(YMSk`h@7_YXa!dU~rI=UoQp zaMg&2foN^J6U3w9(iwdf(d)v^OLB4p*M-~5qD4=Vomnp(y9C`gahScP zx?)n7P@{hG{Y4gvk?v=70<1WW)SZRxBJpnj!h*RrWc)lavsad~9%K=nZqItV2=&2?YDMi-=`n=kGV^!LlyWx-6?Vi%Ql! zr8k)2At`l)u`aCRA2acpDcxO4lXPoUcGz;eHF5u0Q-jye65M`Cmv%tqX9fQ!v*aS% zY;k!{=|Ru*GnQ3rH_7Y6(_U2&O=_2HdY=5cYCZ|VcfcOYmpbXjJ05oS?VWTUcF8xX zQ>mW|&l-Qc)ZJ-j4(-!uMQ{g07RKgd%c|LYEj^2>8>;YE!;PymN2mMJe`LYd&vskD zXhI%LE-h-q^$@tHpW-pZofxQ)g2VLq0|!BNhW8K3F*!@uFL&M{B|LrkhMDg3;)y{oe69kDjV6C6 zgo|0g8?bs!6s7l9QPawVA-z&(r`dtX)G|usy+_GzXMcp3%53%z+vvvJ&?wHF~<+?50;-)9dN= zqA5SDb&f9c0pm$g{Nvg=?@_p8ve$d3Kn>RwN2PC^226n(&y1)`{5@UeUkF5-_n;|qM$TB88GxNszdaBj|i_k9HM0*k!`y*5;vWwg9Cf@>`^{DWA#ysY$nnF`L?JVEplZ=q(7g$C2%13?|E z6DI`}P#WTH2T@>6Q$4x__(0MZdkdJ(mV4u!X#LLoOui^Lv}4JUa(0?8?WhhpH9vLO zTC$M*dQJ#e=AVVAu=&D&OV;J5Sh{rXC9#ih7-fz=4Qhwr>b_ztzv0(ziGr4tHQtj9`;vCE0>dnIuFRdFF~CkGau~+ zvLC+KSWBLQ6Z!!);saysrDhJDQ3Njjrzg*%>9@_ZtLLsq_|@GE7cJFVsAr&56X#|Ja@L?dT`xd1Qeg+T*uNKN1F(p|OxN z0Zn|Z^%T%+k_A>~3^lS(0ddIg^-W1}EA{ksEjt!JJRNp3aH|Ggx-;EHumG%x_x}ip zgyXN;zpwJvlYdB*?d1C4$K^^#EL?=pja63Vx4)fGF+l^wm{pxx*I2_Q}kHOrI ze_gT^^15UT9n#;+<7u3g{_9xFxF)(|j`k#v%t!&Xj*QBpQR?b>&n`wZl?_FwVz5c0 zFBZckPTlP;PX3tu&ZfmtZNf;#0L-^XcHF>^!@0A6cKF^xuk{o4su7g|Gd7AiK?& z$?ag=4LReMbj|8S5wX*ZO%Ek9q%MXKpv-b|8??M)uq0BpBqVN`% zMkAyfudT`0d}Jf2ezw&^9pztDlNpxguNsr+7DR&zVoK}?I$MWaHdy2th}IP*K>!WB z#6+8b331kqvuJu&Pf-8q%ijBrkorydsq64twzHHpB8x9b@ z#VSlY^C01*0_(Olm4nGOlUK-YwiGm$UhvDLF6&4@jF1wN3vbcTJ?-}V^=9TsE8$7) zESiBkx$$|@Wi_%Tv|=T1VJoc57+ifIi}^|YFfWH26}5y6`0}##5sl}Dn!2U zy2n6Qq|y-M$@e0|{q(hMlh>nZ3R20+Dw;p5loKu>eBjpn1;3$A`<_Gr$S? z3A<0u*uls9>5ulbk!%s~-2E-yA$Gp?atP|^49pELzc{QPB#nQGw3hZUu{(N@99`vm zmfWML5GmRe)v;0?sM+u$4e<-n$68za-TX<|SoNWPC1UQy(EU&2aA$K&_T3rNs7|et z9gOE=qNqZK%O1xWlN9TB*9nmvn(1xa-O4P)bub`?-c)-sGS`wf|C4||D64P6vxVo3 zJoG>LZONNWodr9nd=E7%>2)cZF_v5T5YO*u61X-;dzQR%gO7==VlPVYo8CUMAA;o_ z^z(d6M*&53%#d3tpu$Hd2m^B1Csv^f!yIP0WWqxmb&VO8TKTx^W@IsjC?240}z3+CCam? z50}Uj=r(m5>eBe2OE%b^{Rc}AD)O?8+y$zGqRo*4T4_zEjiZ1vsv$VhMYn^2DMm8} zAW2Slu7#m*sDriq1N2f9#O1C)UrdC5SwhxOg!9g?b5;f=!3_kpQOPl%i*YTHb19yD z=>$&Ll=+g%PL-saRgBMzp7)(Y)urqAsC+aEYft$-JtrSs5>n%5KreTKgzt9o&4M?+ zO&)lCybnMY-oY!ps{(OtdFvOv!F>^MPiQtW?Ftp;fmtD;WRDKOEP8%w0fL)sM6av- zgc}Y${3Gt`X+Z(eQa~?Ze2bHig={D%Nk$=pe95i;W?kNcwLhpDlscz(y8grUrIQ@x zz&C#9pJ)Yjyojd?w;hMr49#~7Q^qrG78gvrk9bU|n|w8+z5V^SF};~E>f__1*rfC3 zm(MxK6xC4)xJ7P5WrhrIldizU82Ym8tVVT-^21Ymd)-?fL#;-^APUF@5e}}rJPya) zS=+NloHaT<(dk*TeLLAF>T>s9b`8c<*WR@$EV?a3R{1ygw{Oqx`Va~t@9~+At$Tj@ zI$fCYVeM{SS{JL#m#T+go zahTE<{v^b_=8nyu?nMV3)}NMIn~8%He2OR_J%0F33>t{bPAuSFY)Y(`VJE8GrGRqZ z%^$WyNIoA``>&rP4`q>oXbLEC2!5VmPIdt(ppDHfl@N-#0&iO8&ux>2yW{@Fjlh~XB&{uZa~=ApR2N_o^F+QGZIXvG( z0ey`w4(|+=w#Y9k95$W3>yE6P6(#)$6M~5Y6*wq{B;cC7AG1HdX>x6x++|gHr-qP7 z?=5KWFf-HjY_E%xOLgWV!#fofzk%a0>ReaU{8vYT!7kR1?ktWK!c1t5?7eBl0A$U=M{I8r8(B|M^g4_hcv3n-!>l|#tGPA zLLm&nygkAy1|!~>s_zxmahK)Fy~_s;xD`7%zlgaN&|Jkfk}TO74iIIJq;_ZREVGEi zwjtJkx>n!EO$K9J@7McH>+tpb^e#Ho4kf%rkCf%((wfMxLcR(%J(USg%z0n`zA`Av z-oCG_=R&Ne>c<1tB+ssAz6{WHHgJ^JGtc0#iI=;x!J6lCK^lx^`!N%*iyCk@89g_5 zc!LF7=Pt($vvW_gR#m*Wzs9N@`9|tCsnB)VQ8D;4Ob)l#lEaeenanyVUYG%5dT0~N zI`p(1W03oUfYe~R*67DmWKR70yO~s2Gd>u$rStqc7RV{ia42WG_0fIAJhf?l&$H-+ zHwqmM)5-^|4C8O$PO_U4t86aHSf`%~SL)?S1ew=;_gr|ifIb6`)m0y@f-?PdQJo%5 z4)Ifne3Tu)Z#yo|RYraoGU9g1<;ZBJGBF>m?}jwmn|<2T`(;~OS6Z>?ZdT$^su7{m z%&dNvJ<>~8L?N~~xn)uRTeW<@WL5y?)Oa`D*^PP_llJM=n%Qc?c$&LBqG-nYcJ~gw zk>I(Jo@@87iaXIqI9#^>ct+-0TtUpG{5a61{QNVvmN9uCP>^5vN1PTu*>slVANHJxt^s0-5YjDOz|B<^Q&OW;J-V`zu*{wP=@|3*MCX54*y%O z|B`YY`L|sECFMH$Z@K-fLr`Y$QhiGR!WUsA6BwqO7Mckj@s{E~9} z|IDq#bus;~p809}!OT;Y32xB(fA`k>+m!w9{P^GM&@1aVvl!X;)?Kw6`|4CxS$Q+v zz35>|XPmOJ(w|Foc=kmUiD!;5-(>;QIr-2i#TS1IGPOABqdmpD;)D1@z(4w+@*CB^ z|5apz%mO94!-VQbcF=CVk-UUV;r-9B(aPFN_@&+Z!iB-TixnN9unzLTd=<0}JZ;>f z7(9>ZKT5yyRH7=2IlycENv~Ll4mEY*iRa8xQ&pVvYnw$QvCB8)>6G^An&^Kwm`7QP z>(M9WioD|vlkX@Z&!W&ZUn{X!e0;rNvKb1DANb8BKIlYv4}RA6`(<_oIR*5+7FTf! zHg6DCndiCmPM=|`yiHk8y5T|#Xcxj#A`}kT^#U{T~T_y950j6@+Tkd;Bkk+zgY^e8@({VwjL&jmz%a;v(;(L zu(IfWQqgfrb`wr>j|q!RqUJw-e|~kh2(Vc=Ku7u}&_jEMdR1A6#?HdBYKgNlGZ2>@ zKuUX_Pgl|e*M%L3@+Msf4Mh=^jYFfdo#m*zT$X2tn*PxJLC5vngl-| zvT+J@wq(fo%v1z=?D>2=JJ%hhSyQas#!%%e%IgLDq6|-i>Ei^+EL=F~A}Zl4iLKaf z&P_8Sh|_Lba3L<^lL|^n`R(!OZ}uklgq|-pF`(0_q4#NyeDQEH3mmuF>TqEUrh-G? z)|E$Gt5rWld9AQ2UHqu2FCo|`lT@($719F5-8i+(-?rM^ZouRn#!ECl^Vl(s-Vu>P)(nD1)8~UG>MD-tkw6Q{+}K4+Z4GF5q_j zH5ngmSY2N;SS=IJA7G{yF=AT2_s-tiZQ^o&*!z3==DUYmp~R~uL^T-uxUQu8^mC8; z!n=Czk35zl(^oJAi7m7e>(3wiUzrFOPD&4;)6qXN(+jX$Ok|D$E;lP$)?VlNWyMEz zVkQ)jVmGnpxj=3mVNo;p_tK>Ui4E3-W!Z;^*IB@Hcx^w? zXDBYqczHLw>kC&)F~7Zh!aOx;ByX4kay4Ps8@u`8r17{PSM3~kM>__eo`xq~{9;3% zhR{#6A+aVFRz#h`t9*_TN(YmO;K)+ef;qAX%nYZ|VZsUF3}(NdY&o*T&uQ?6se&o* zD;<_;OB`4F!|E_cWHg}HcWXwLuRFV#7i=QuVI8-^fq3-$#qogLqL&t*wq+Pn9s8p=uJHp*4ul zHtRKa)_FP022JzQ-YuOSTY(6MDF8tW$!+}>U2_*N>bdX}b-q1GePBl7kO-~#!~lH- z;W~iC!&#ppVxF(W!LPoURtf_B=7TDf2*)HOB zX4a7GF=^zocw-Il`nZ=vsFh;A0UNA436%{4#(p6MF!0rMVa zj=@XY_1t>*LEW&dDW-_uKJO8bwqR6EM6i6V_Q`C@Yp?l5bb-Ru{J`8~2tbFCt=Iq5 zBsPJ1KH7Tj{CB9P*u z3qPl?C?NAwcmLE~@Ge_i=myAmjQjjmovya$TZq^yEgiVo%Ji|4tikzZ!8~lE0al|+ zCXw!rH{B1-yFk2E&0Fu^z879!4qj_aG8=v`B3wxF$6Q1oBcB~! z3BPkOQ`WdJHs@5B}4?A%FJ>^r5@Y2d=VcF$zsTk~1iqZ%Nq=;$yV zK4tZiRG}5V!hR3wotyh#)iDU=-|pJ~%8&o8x(l+`7mz_Ds41|KdwdJsC)mBT^-FDS zOr0*vG4;#jQImIS5(b$N@D^#fD?C~N(zb`MvMryFMSdtZU%Ascei=_j4x-A#Du9L- zvH*TH8rdj`-O^;Ux;2^~?24*OFcK`FJ#)XgirEXU2(IKIR1-DGQ%)_KkE;e-J^`5~ zoGWwcveaxO!=AXsv0&ZK`uXIXD|p>k#20Q3^3CJbSDwupcPM#}47+n&_?~2q>5&Lb z{835fxnxLAJNV<;fEy#(dXG#E$d%>XULXxMw^baG*IJORU_b&9*DU1$7Jzx;>987! z+Xv+`<_+~jB3kj$0Xf^8;#^`O(^(eVn`Hc#OACv@5ME|shs4d)20cSv)nWxY>lU2xkwSxw6R+>PzCbBP;@M^MT_5LeNR}&f}2-E0&4l#QJcVM#R%O z+UxKi@1G~!G3`pEZhoMrfKIBno6nixa}Kc%c1q??-Y?U4<6Mvz|t>f`>Dw7v<%qhw!GMGQ`^=|^7C8>2ij3#+JX=a zaO6|d`{>Xf5c-ZhkMtl}hLc}egxIVgHldA*9Ob6#3O)YNKoavwGTa#vE28)oJO7g8 z$(~SvY93|r(;5rac2zT=cdSXbw7xHuP#de6` zRSM_;SZ#&UP?JUtNKy;*_~;m)oksKgKWh>t1#7578S$TWExRje%O`&fccG7*CKB$? z=-Ka3Ko56f$)bbQfx$j)g*E7?B^iNZ4^*qhRh?YL_Gav(W<-AK{YJ=yzid!XIe;hw zhuGCE+xe=Xb{!}I21K}qTa3k>yuK1q(ZZ-0S@2G|3svBK^hH){l4$V*!9W3dqvLWI z#;Txkhvs_z{#@sfpX$1%S=loVJsMd^1t%ZKbTAkYi??gnWQtVlR()|DQ#87=y{@<7 zox`6gY51)nY1Lw_L#+CO!!%+{qotp#(*X?l<-5br1~`>(tkGtb<~L|)`6s|Dp)!9F zPt_x{Fw|u0*%G}4;>5Qx*mXbNoXQ)1(rpsAXV{&-Iq4oej=urxC9;rz&NDTOg$-CX zYXXUda+{e=?H%R==_wsPMCBL8Z){=@ka@n^bi{KcSKLl)n8=zfZ)CAuFjQU9!|b$T z7f#Ic*J_kHcyU`i&Du8;_FSUo#d)w#+YwfP9VEbqF-4UCa10@3r8_+noWZb3sHo{)O2srk z9M*t@+}G<=>Aywy>ZA~MpZFpej&X^A2sg^e1VdW{3i$-Wil0^(Zm-|cBYaAn>FYEQ zH&8nkrJ^!7{)_@TP401!KFK55eU{rUDxdQZNG}BLam1g$?+ALf5LSIdykyt)2XY#` zII&fM_w5WjpR*lm0=_Z)mG9Qzrd>~b-&6Cw*}4=t5F} z5hK5LOLqCTrd4d%NSDEoF2Bc|&e#RJ=s`J2CDGG~d!U!EHm;8ehz`IXBLrY_&~Q!1 zii#26+f2WbpmLAX3J0|8RhSRBt*V{Z1P6gZY+UOcvDZl6o*`+{&{!L3I?X{a zQ#|>ow!;EEszx#a8F#;r&h;!+e=VDVHAMJ)VSOe86$g9`$C~BBrgN0WRE>L$1zCAJ z-wP~9Og%S5^QV6>G52n!|s8uDjpnj);2^@{qc>N7HSsn_+5ri(ZA<$W)u+D z#tzOM#(?du2noUP?rIg3y*a1+ZM!N2J>cJqL z^I`_$s?^-oFU>!p&V475+AbIq@HMn;L zerUT^Gra%6=xUs2d?Z&@;$X-hHo7sb>bHm~&=>^n4w}s) zOcdxX1d4Bda2jeJCLl}@SM({s9*{Aa*eo0uu@~{`SkFJ zjyW)XsB%;iPm*$+fQN1dez+i-JmRM2#h#0HM)11VL!-*bwCkFEJ8+E7HM>x|PcXsK z;N2cX1`naLX~Bf)!I-RC*5@AkwSlJF4?*N#T7$6$J>V+Ib_M$NIniNl8EFdWliP%d zSE=k{^)|L#3CwU4Yis5g5@ghJx$0+9R>=?HBBl%M=5eVheI#={X-<21hb*iXX9xEv z-WCh|B}&F0BGYtf*SOX+$0lAC)|rQfJbe`9wLdfZ%HXa~5R|`~0s^jUKPnFPx51x7 zH&jjH^OCh#pM9=MKDXKtwTE@=`aJpbob?#rcG7P-cTS7ZV}DH3P8*uXExF8H^F~nM zvHnl%xyi@Y$wOft$ANSAGPzS_H(ltR&-wv_Zr1-*D~3@19sK{V{P^E%B_yMLd|w42 zs=%A8STkC;@zzzF2!j{JC70#=e2f{G#-gY$Fz_4d427OCYeO@rHK3!Qd^=3hRW_B} ziO*QFWV(&c1+3FKu|W&wsf*vjCrD*iE1HF>x&Q{2;awUTG^x|Vx)1O5hND7sxJF0w ze{j$(KJmiG5#{ERlzJi+gllvlKh|{dCeh%s^)@fn*bN0 z4-ka4Z17`9j}GFgGV-~1)HjA#cGi;r!m zcebl;5WC!B^o0)Apm9*#El(2&6qqV^o0Az=;PD!^shX4r)nCxMhkK*fYMO7dyW6?EcEaaYVXS7+>+~bDZJ(8K2>K0pA_rzkc=nf zoNB7$=6+e`F#Jv(aPs@G>o@iaEVXqzoDkoEsGe^#RtVq1`?m;?(~t(9^j7{htdpsM zvFP!O3EQ0V&v~}&S2te~U2Ma~LBgkwtEmvVjvS-=5WWFZnpoow=M_xDD5Q zzVidYA4WYYq6XgX8{Nzu?^7aQQaX2bt83fYsdt~|ebS4KeGM|R4IW9=9@UWCRw;F<&HY-Y??zWB|GTudU1v)*ybwR1KhZ;NQT?giW&HuP_ z-E|E?;t_0RgA>K5Dk;p<*V7fxIPQ5$-udODIjQ%tkM2TV`KJqCR@;vzakZJ_yx`w` z+jbZxH`FI=%U3?Awb!g&{3$D8Al~*VSSF<*oAIC%&0L2|A`!7HO;9KBEF zc`r@h9F^n$iAu8|+g|+4U{K-EiT2gKLY_pQfhiC**1>$*TyXa?lh0F&rr)zkABsYv zW|4xhMW3)oH8D|L%gH28Ppha6EL9~BS7kHW-u(IyVLA5fu!aJUP(O4h|k^xj1`{6=Nk@qKO>RZ*rVoD}E^t~WC@on(_G9<+Hx zE_=ZJi8!f5JDW|JwSZ60!XV`y>YAU51ASx{P)$VptGo6`kRaEI ziDgy(`Rg&%(GWoHp666;aM$(^?9-OR8ZEM+m5d3Y24a_QANY3-TG0_N1{Z}1hRx?F z4T1aOwE6?dV~d@gyPy2ObqjvSxx<6`{5KT1u{Y#fpVCn4NLgNKtNYW<-&62_3POBkz%|1(nll9m4*B)$b zo8qzvCvy-by-e5NV4Ni)HeFZvB)teXTlmvYG7k9=C3uc{IGC=dP;%}{v(ZUPBTZTG zDw(+jdk+WHjUv5}YLX9h=dR_4MRXd3o$=Gl+npeBp)f)1NS@&N&SribIMGKJ45SZt z8=tzQ>^ygK!e9dhR(rm>B}bGck4+%n&ZG6vTpAgF^>?q|MTS^(2F2 zhgqqu8@qt|mg49cJ*%V)>Cs@{UinpHYzu(pA^8q1@H@; zlimOPHKKj7m&F*CbA%l7X0@xT#0Aupmh?HIs;Y0M+XVMWpHO!zgJES!vQQbG6!xwU{KIEowaKE#5e`xF^(Vb%7-b#FMn*qN8;m z&-4SrI}aq=Rd`>V>G1n)Cl(}A?VKV0mKK3Sw+Wy+q2W0f8pn$7XSMp9PT#xK;K;{6 z=M1+keFjbmC71xdm>t33)eg<#xCPJN88;^pFB@xE=VeIHvTQX091nNi3D;FkzUA$C zJFtGZ*l4ki6P?*%cKz3Hjo}hnTah#jJR*k?=YtNy`m)Bn(P^qbUB)cR*=+yO4;Yi90mFj# zy5_(@P_7YHfy1!Zr;Ni=sctE7Gk&fP5e+{_(!z_ckUJ}>QAb7frr)}TZ;mCk$M&9G zI?5o_1BsY^k74$3Tc3UdD7rQ_!W`Dm4(a$~+jt$rTYw~S0kht@8cMVAw}2S~8qlZa#6KZJI9|6S>5V1vugKj$k-vPS=6Og?kMgId z`!Tg@4MfPCQINKR>MrDp7QVw=$1v;+kU>4eA`%Tw3Xl@%Y3;$m8G71l87$oP9H26!JKJF*(se3g-!E-5XT!5m*7$jI{X#sov6jd#G<@5dVj)*7Oa} zF#^6hTAg^k%~fNtkW;%NKPS1$&q2Q^co4|I=HfM8JAd#o0j#$$iIYF97Ygt#pHe;$ zR=bj!J=laCq%vCt-OCmdsw&U#xx#N9yZ)GVeYua0uF*W{MELBQJx;#je0sYNt;{w@ zy8rq&&_;NS8%QW8>rhYd8jJ@*jboi_n};PJvaPPVmQ0RK{?N~HMtAzuKR(rwHaC31 zqtCz%GQaxw15EjM?&be)YIXig-Mc_Pk&E097Abyf4n!{WhNu~xu_gEC{GuLc&?F{K z4bE0V8DS38#Y`Q>Gpa56LZM~W?%q(N0gKj*_|is@r`BgJ$0z1CK_VKAi^DHv$t`3_ zU>+wuZ+Mc^d=aLarJrgSZT^IdRm>wKtIwooJ~1p6=6#Z_dnRnKp5+gi7j}j5dkXFO z+AGGTj*n|3%! zg6p_1)#8h^eKA`;SHSmHs;(h*$*bFkZeN>)w$n0?$VNKb2<)(L3DR4Qhbh>Nq2G7- zlasaA62H;E^2G!;bp{nL1 zhuqgXjf5wcmr@2~H^cBH!pUcF$W1F8>IYh6`6RbdFr>uYwqyFX{O00Ewd|i+B>^sv zNpx09#9QzdT{2_XNSMq>qd&IbMcziuL$QhHc3r14{E)LYsDdRV?%Pq*ANsNvi5La8 zX#moCY!xXhnYl7!Sd%m^B@gZUkSfknG+*~)!;Y^e@OfI{xCTzVzv_=usuZ`fCW>A; z=TvUNo*))V;tV2$;?eOwjW(DU7S=c!sK3sqWLZy-r32|yQDxUbb)C{tYJ`|-S4$#W z%w9T3g?Ao%j~8L(eEQYx`b%yLKRUP+_eEt#PhGbQAN0CWX0cpg^(sCv!}p8zY^PK3 zYNGSGhX#VLT2{+p_i|f8+RW#gw(#xF_Nl1ILN(XPACrxg;6b!*Zw47 zpb1O#6#?LP&^X>YAu?=t?Q|(m+kw2JZ<_M}{wo_@1;Moq!DtVI;1ZJ~CC8E4dIX+H zdE|T5ZOHU_{|8f`*X-vBRQCHXnvu9P7LXlajt9Z$*5k<4*8wlCU6-4fy!O*w$+sC6 zjj^fxSb~(nt&%vIF!!@(%of>W!XzfPx?5)o*F0W6cV@brn+5(1WrxvW=A(4khDppA z!=+^7;frT~h`;HT7~B3eYXWm28p2y3jm-GPt~TtiXsoxvj~r$7)@kEeRZ%gFe|2GE z4GFmXyNr2p_|;4v=9t5qL&0G$^bU+7QjNvi za+CeLpFW8nybq7pWvT;W7j%qU)q_~w)o>=?FN^D0vUP)Rfr8o;K>9dhi)9X1h~?Je z>Bn#6heUrK*6t%22jMPtqzicEnNA08Jb3C^@Qwg}Qw(JTmiyS5x*ECiQVRCsq z{(9#(V5cQa#)Rd-D>C8R08P52zT=N&(}j?)X9gA&w){#YC$+utf;XGL#ojPC;3@o) zueRV4n#nwR%!*OiJSilpG@1l%+{>~Wht(Kl>RV$4>o*ghvv(qcyD%b^~gv!iZfQU^AwYeg<~940PdPiw|HCAyR)g}!S&B>kxLZ;(+`s#pPR!iu28L? zQm0k~!!tM=>{2~ok4n`bB&dkbZhBnIH1g3U#qkxRhCg5Vzu0@vs3!YwTNEqOm0pBM z6A_SCssa)LX(EF39tDvmM5IGV6r?u+1qC50A|kzaLN9`VbV3P9C{h9mU$qVF`3Zf1?% z8~?P(H&uT!IS&t`uaqC!QJf2Xv<2h3ES)sG>ZiNr#I28mU)|@{oSfxA#A&nCP{Obx zAeLFBR<--jI)iuQpWc;QR|G1|>g0SWl6Dy$bc|9+Q~lySTw{E$-gud+`-f@h?pK{6 zU#9&n$Xo+CW2Wv*HlU6xs_0nPa4prnCi6QW$>6GXq#lt8u>^EAc3xwRBvMUn4)1x+ z2xjP<5BtR;=mZZeJ*TwYew?DwjdP_L#0pM*j62s^BST;hd;7_)@!gYC&XhPJK&d)g zR|4YOwCVB5u~nOh6@Q8fG(z<#>p$z5(&m7K_7Z});WXg#>L zY(3&g0=7k}@<*w7T|E0=w@!fZR?PV@9f~v-B9>&|=_|G~Zg$n9=9VsFEU# zJ?zf7YyD&y*7SClbRwGcT>f|}HX_1mmJ6v;F_(mU0l)hiC+cB>`mv1(JlA_Zo-to7 zM*y>Xf@U>*>q-&}dzN?fpU6aTwQws~uI#9p(8C%hO!}kR~{YXwN1(I0Tycy}1qKaB|Lc!ibpI)S) zH}Qt!vSJV2);!}FKD125$4lMbP_$vUK%e@2YbJ@S$EfE2@5lo9&p$&V|C(|AXGr8^&i&kzh+$j;W_+k#`T{@ z`@d#f|0!etHRJkE{rayN*Z*(zYq@KGpEmcDDobFVrc+f*dxL9+4&N{^_VhvDw_}Xi z?0;=#{d@1^-lwVob%V}6|Ca$bx&H^i`X5m1Ki~fU@Jjx(m>(_aZ|jfcLgA2YdVoK% zV0k9J1a{K`<=gZYHgBpR=!YIcF5T@GvE2FiuEG5R=xwtWm}mn+JDNuKw~J1~9JOCR z)tV0@1PLC9c-?DOxmr4%B=LtS=(XdPlXexUfx)Uw6{X~lGWf+%IMW+DXVS%I%I{V@ z2oxywk*d%#EE<-4vbCu(Wp@Ss8{Px1?~nPz^i1#P38kXI@9q zc#-7dAMKnpo*5e7a)pTgN0=#!AK_lt5I{bt&v~%+E!S`da6bb1yhGG{hp7S}P6xeC zH7QLvw4xhaThv=bWuLYo0RC28`mp07F|SIWU-9GOsI3?n9lds5_!T$!eWaZ2_^%AnX zYmeZo-(QgybTNkU)iXLb&xG6ViGKC|4F&*>j8W$0e)XeLQLX{dmFY;ofBF8M7zzf=pN-c8WMU5W9+X?npDW}5%$xyNG>m1hqab4zF4HYP*z03tRe5c z3Y!o=rcxw(D83V}R;%95F;l8KAH?)l-tS|Rxya``cV^#nq}V!)t7z(d@d+98B7eQ9 zv|v=(#}+8E@TF)2{W-VPk!|tvj@*36h7`B_7sT>yqxY;i4e_)aA5;K?lEU)*Lxp<2 zraW;a^^Z`wM!KAry}h37fL4^|*hzKuzZ`TA)h$Y|8mKF`oU#`Cl>eFrK=BX;>s6|; z52D_BwDUWcJ#o4QtBK@Z*r-qOKO41J>h`)z$@#-#YadEhGg_P3|0W3a)TnxP0NZiI zY0r5RUsbWnMrI`;({{jqT%4iaGri5t8@A~B_lN$5L9&S(lE$Ct2M@RJ_v*OXJOh_R zl(`vIztoA0Jk^@^<6*ivvLk1l{mj61K=k9$0exPFaz{hrGX zGM~g?ErxnkL!%!Lw>?C#ZR(6JO9S%#q7@Bp^kRhPJaks32U5$Gtfj~m!;th;yr33R z&oh6MBt7gYP1V|6V{&ur+ik5gRgsziUxUd2ylhu`la`53NC+0gD6HS22ctKxh+ z=mkJdzTezI^NHw05FH@NXv2714W(h3Lt@L!Sl8L`b5e;&%=V_BnEyJrZLejNmH53G#?LY2~hns+i9~JYy>#5z(u((>+sP?04?Fv1A5I0 zsk{g)%G{lEx-7ysNQ=b_TDZ7iLd|y9v=PbsKCyO<_Eqmgi42VoL+&K{6*AN0&Ej&T z_(-gWNpq808ASK}H5E`%K@+iSf3obA*4P_7g{$L+s-0rUJ_hUcT zerENR;^#?NKnFGgg>eY4AL}^`kW-Rz7(&yd3pJgG50RXhAFtoRAQ&zO18x$Sd^#0vB{ zE8;NST&%RaKc1PG@oY@bZ06RizAa!UWp0VAiY%BjhlPYdi_oSKVV7dr0==ZtQ;$nT z8Ebd2G9Id8DDsK~bzi)K&3qS`0Yd#abuf5erZRgt;(_cr_l&^ROi&&Z!gvUmq@dVY zMM3o*ntQ2@*#o%sI4b+(i6Jg=`TiJ}@EI(K0Ib?m&q=8TIFr$njG-m5SUZaVcHy=K z(;(I9aofKfIGOxdvlq+`Jr@BO6@gvHG+?@WqwxI>&ZRF04-xe$vI_iWeUebfS434D zjkl-+T)S4t)r}FbtB9tB|8x+6st;FBs_kLi(<{5~1gxO0jZDMNTbDJ84N(I^k>o^5 zBr(`50bEly2|>FEt^sA11Vn?j&3s=2bOb1{0D9 zb8sS)zxxISJ*h}IulQzYRZ&vYz;Wl`J=cT-?KHg-v0RK2gr8-MF(fIz#Hbnl<}ujS z)w$a<S%kzn)sI{61n z=N=lnE!jtD{I#4Jb!MzFl*Pc8;Fuw_Z7p zZ;4>zpK!Z}_%g_OtNQKgA0}&l9k~YRw-0ZdI`&6}V1QX>)K~a`xjkh9r&d#<79&+v zVEpB~Z<$?2F;c&lSoT5BA&NQLl09qb2og`)9B^m1*1AzWc4W01s|aM{6|oEUPe zrrOV5+-)$W@Ai6nR4ZO)`}fVX@4J*sW`s`Ab_teEk&7Zu*a0XOaqBg)LHiQ5b(V2W zZ`Bno_xg%<&*vxl;6bzM3|2|1J`6!G2t>w$&#g@O9XQ_|AuTw}v4u%yEJ7RO&`ID()y#$v{IHX!JCXgafZ5~FCC)q(i zb|0#8&M|jrmar$)l;K$RL!XUXO_5n}Aw=|jyqF^njNWCi`cp4aqVJ$6+gGj}loYEe zv{$%$l0zK-8c7Iw^tH>hsZaV4JzKGaoQozW6A=V35oro&U6>t&NnK>4Ui2NeUov2R z%M+feC(Dq&Fead#1k`wx8sPi_yq5(!)8>475oZ~Km=r~qiIpnAvOz)ms-b_-`77V5 zPn*ud0Zp9MU5Ye>AWE7i$NhjsAV_Jwvbalu#(-;urPrxeQtg)Hb&m$4$q%f@qnZY^ zX0{4XzW*2%1?c?0Kc2`Gg{3u0zYNlsIj8_gDP%2rJ;GZt8C35POXI>-oHq@_rkI&e z-a&^o)EmL#m-D7oWra~gb-}bbT>NvoevwrPLXmMCMHTRPTM9S0PP<6 z`!o2lN0SfRkNZnyo;lft8Jb^RjsC+_HquS8-CAVgqW}ZVr|jro7+Ua=1~BKgHdknh z)(z(Pg2{)?LG@8M?9x~VFXEF_A`efn(@M~Lt~P|*Xo8p=rG=^*%7z1{UQES1O>aAx z6uaIN9w2=q#i3h|ck0}~HmG_q_5VcJU3jQ>LNUD%4meXNprgYarG+A3xV!{xr$0a3 zH`lrZkp?Gup2VY{fz^S7I~!3i(+@_Q^em|p8~QjbFt$nhwGC}`ZxvkY-?EQaD}kgg zSGx&*+YzgyD(GB_HRisAwzreGAf0fHDLjX^N|B?wzzpdhz}_gHP&sUDicb&`+F5m@ zj$Hqf@o;8qFYTf!)yQM9P8XCOlEsu91N!vu^{YOUj{FbDzKJ_nNu8#*sZ3&@Ce>`o z4k^uxc20&tCk`?$au$(XE*&TQPx|mFm^jr0J}o9ef75Mb`^;=ObniL^0{}N z#|s^OwKE;Qk>>GzD+YS!ELS6;yll7ZV@vHz)000dM2f#PR}Ne_JZb&y-F_gY)WUhLXBt*GOyR&5Bh4GAG5%hiVO<&Ke@=29(TK zpo8elEtq z2u9t4Xi9~?lK6UXx?PEsM&kpK*(qt*jaFqmLDF)jHupVyR>*IafIc(m>rW3F!_!7S zVZBv^ye;>PFU!PJlJa@(U&P3>PtEmQ@X6X|dpNwt}$K)N*!LYi;o z{PxtS*1JLnE+DGyT=MeqZr}#77fCg|Ly+h2WZo#E@!KxTM9UCkQ>ey{3qwA*YvsOy z*FS<()Pr{}W+|tt8S{%Eah6fnPQv_w3mQ*P)aHgy3xks@7*fug^`q}ieR-M9GOk%2 zeH(r{lJSrt`V6|SAbojcwkY{7_M4yZ2md!6v=M#ps(Mf$h~UCkjLyf4J3gM zF(FFPvM&^iNxmPEBGAKMZNDgSJyq}gvtl&FJWPNpoz=g;76HTAApKiVDfw;szcS^*Ipspd2Yy@{bb50fQI+{qW9B4z_q zB+$ARn`Y{+iwi*2X6G2^MEjDbnMp3s1KxvvO?Kzy-xWPgzBC8Y>7HO&=@(D&np`8* z)$1wCX}i9J+i2%k@F1ETC55!hU|FRaEQb2n#Co~|t%PX1aeiGgK!kqdo(0BgzKn~# zb6N;Jdo+%!5ItenK;n!k@|pG?I$h|?H~gUa#oH6lB8gtJxjDnZQT^{leJH<)GYMM! zz#QB?HIi*S)NP{mTE0eWQ^wjOHeo~2h0}?tsi~ zjvv|)%d`D~0>c1GFe%i8|G0=bdccnec3fRY9Gb#EFnR!ASX3OKW{{s(K+_|&eVK+| zj2~(nGIChz7;d>^L!vK!YvK?edK$cJ`BQ4N3o{Qfg(gB8ps5F3ryM_pX!O-U-HvOX zG;FkUjd_zl|Bi<;v&0Yqk`$@ULk4q08%eR}(}b3-*6m$ie&jk@cb#GXmi^mqYHn28 zp{I#SRZ!K@E)n1Nhe-r+zXBb;)s;2#S&lAXk=SiJfqU7ORp={jAapkl_P9c1S;J2Z zhx%kT4x2)K?TbsO5$P_j5(MMe@i$HBLKv{7I<>!G9v?BI+u5`AzRc$-vR}3)qNklDs7zNpudtje z)AI(4dFFXUZCxj#Q$Q;eZQEDDPt$5`$#a_yMAkaa`#~i~>t4h9W#2K+&W>nWy$Zw7 z_#~~T7?wRw~A`*j9Nr<$6@0=DlyYj~H7S`^xVjDtF%u{nq?P^=3u z^7Pqh(Yd?8q5oXg-lP0SFxW~<@JR6Uj*s9oL0Y@yMhf3o1~6`W0#GP)xY7*M3@cW- zl5O`$Z>4^pH!=BB!Sh(MDlH2pL`V8DkZ59coxi>Gr^ z{;oTc=!MHfauJCWa^5a8Fl{Z!2ohgnu3W&zrTOWFkIVtRe4hmXof}^Go}#d zcHt7=sT!1ZJEYB6QB_vtCFiOvA7jE?z;R95lA}2EC9wtWWO3;bL%9qhOq9c9j2Opg zqEqleT;6Tb-@V)CN8Nn?qAy%kCz@W;Y~XrpDavxX-GGRoac7g;NT?WsmKV-U%-%D+ zci1Ed>K+jhraJ6Uy=`n|IK(uqWhCDoEKjjF`-JDLGq1hG0z>K`Uf{V-mQ zl++5%#UA<3?q>CNPVMVwzOt3~&4$_BJnH|&=M&@`>B~WQm!u+arrKchsgU5qvyo@s zGcVl98Z-8nk>k#~wu04BrM+PEW5i$}Vhee(j#7uC-`vm^nXKcm_bYc6dU4PDxNq#O zo8MDb)$fb8MVL37_Srp82uRlVKux>K3;N_ht!PoN^3|pbnfwEs|#`4S@9_IM0DP7jUXz!P<*f@5DrryYdsq}vTivGm0yp- zo7dLFswo{OR^3mf^2XsO(ygCp14(YwEiZ?@1nNbnt?-sR^&vTh2jqCdUf9(awt=Dz z8V#$EbOiA(h~JrOeyckt=A(Q;kAQH`(}#hnK4EK82#f^MLb8f(89LJeXQw1!w<=ge zcW>2_PN#)lRVZ6AQ8C@Ei#v&6IiEU3%Yn}!Pw${y)6nJ0#E;}ijXuSit!DO?!Hh}e z^IcAP<0k{%*LTH_)r{P)`BlVVh2jRa07;pXbYgZ&QM^3**IEp0v+dlDLg7n>kd*EI zJ`vFize>4*H)DeZj+K2jL2zx7UNqi&kzv#kR(2TPDsON@IAq- zN`+}&Lf)C#22#s+=hx)oyNiDM9I4V<8FHbcKo9hjR#3^$;2Li+5lUdD7x9c$ZSXX| zWtg%PN*)}c$&aCrqZYqQ{06;85cTHDIpTUFp8jEKv=98u#+a91Mh>u2w|c=uz%y|6 zuoJE@-Fgm(5H$1n>Zu-J?|f8SouHVL1!7Rj<+N=*P7I}dEfTXh z9>kMY@%u((7%>`e*bPY&<4o$uu-3&)9~eIjy@iu~;GO|)PdPu3dS+m=?dK(+9MKB3 zbRneyj`K2IOMEq%mQ#wY_sYV~0(G0X+*YFWUr*OO0;$}NPNpTyCldRtA z+WwuNQw|Kxcr<1UT=msrY`Tgt(4gC1o~EN8fV$!*#5#961lfpR2Rl0GkT$yo(PF1Fu zm{PoC2q2uusTPu0Q$T=E;n1aly6OgmEL!!3RE9eYb!c@ABNhIfs##76(IFY+siome zHRi1=8!a+)g1Ak2O4!fd>plU=76yjy6_;IMcaw06(OPC@q4vJJZm5RJ>Z@TkdwtlB zL<6&{woi@>;4V|fhZp-dzd3%XbF@#$(|znp%NFb$E%!MxrMH4TkOJ^NaIJG(FC=FF z`)5y$#jVX|(beYH)Kl9}p&66Nmc7g-9W36pQQYBEK{l}j<^}Ale8xn$bOliQ@z&SH z%59Xoh7umD%m*(@e$;H2dJRAm0#~{#dl5GICy0iz43SWEL!!V71^#}6v9f~Nx)%s` z|77<3?eMA{7o&Nr3PdYF^?!H3QCspQMG2i#YETSnAR&gan5|85f%Vc5Z*ic!CJI~8N{1*ZB6 zabXH&F(ZY1wNGBy|6ttA9GIW?WP5ovhgBQM!lRtv-^Db6$wbbr5Cpfv>AbSg=HHrC zK5Y*@%RaFdL#y@<(bW0*KIWmQs|!^^ zZa=K}wOBvjQ3WHRv%qp5O#&}}0N2LF!&P7rsgaPbtc!*y-`(>HnzH=$XO-xa33h5z z7qAA~yHdc9NBMecfZ`C#ABA`04it}0d$Hj}92E#nt?}+x`v+I@qRZG^)8;YrTm9K6 zPQ*h%nXm&whXV!^B|yLA_4%QKo59j)+;JF;&b8E8^hm4yWKn=J(6zt zB4Vd5DX0>7;wLKwLmsD>wQ5qOVOPy~7Unt3dcucOdk|s^HLbi%O}}+UKC4cPpOVns7wlHP6!^skA9ELvz1bVa^+Rrym}wX_HjnQg6e@ zK@H3=+J$@|HCzPSqOc*HbbVt(TYHpv(5k~o24ih)@(4)XjwLMMwHmxj*mBmFfMop^ zNRh#Z>7gm^g6keX#cUsOJ*RCJ(Rc+ItkNX)PB8C9dLGJy#b(~F_NwEiaI$$)ZcUhf zl!EWQsaG1Y=KVgR{oc!o>5?7m6j`7<6J1T*76Y5{ZS8-rbV7I-mNU29#Hh{GDpn%N z*AIFl&rz9yQ|NZ9KfWTKA5pVTkUd@$@3$JEDe5>tl_!J=oSr5#eJv5c+yRts?FLT! zI)+(@&fD#Z@M%bm8G+fSB2)l(rL2fz*lUv%^x3gQ65XlVF4^3$mnXz2@(`(XkSSV1 zMvxy+N&-j?%L32aFL_^-{NmI6kbCJ2Vk)WbNQNnxj%yJ8a)Jb9u!d3HXkI|i?VJxW zcex>1u@&s|!He9rcS8+w#kh{G%N@NMb}hcQ7E$YSu%npTfT{*0^@6aY3E!P<6D~!8;L>Qk1!N2$DOO5Tm99{r0in>aXKvjYm!MP6&r1C8@q;v{HkxbN2}3g zw3sb|dp@a$Gk^uUocAL#lflZ2eRF#HoXeK%Of)0qNvnn9bLtc|06s6wybVk?tJPII z1JZKh`vP|=J?6RP5%9I;wA>-xo2;!Z=bxPTi)KkgBmgpxh`PnR!yc|U^kKY+eiqK? z^#MWm26vA}Uf-qTgQtmaPh5u@xCY$55GZz*-j49a0K2(g4afljd`hznK0b%{NxI>G z0weNhliVBy0+wO*&faGom+KWj&5S7}A82M2A(`H^SX+i~R$0M<%j{j-wNxFRm!cvC zeR%ewMu}(OY)~|aXkIZd(v=UM*eTPp{X*F>X}Y6lFloOl-jeY+Mqi(ftKVZiau0Xg zAwl#h-5nUB?IOI7iX(pr!sQAUdNlfi&8GBAU-l0@7t3Y;MiqE(noN7j<>18=Fo(F0 zpvWS6${;wKY+#5wwawX7^=*6igHk66$Hn=j%=&9r>SOFrrcmo#PsB<3!$`j%G`>u{ zVy{^==uE3MYj^FV724I!u3L>;LQAx77BzqDSYn(@9)3-b``{{i_Pl#wpsaS=KD$>KX4T zD{+~vYz@4=KA2%;N5DUhJmTE>$`yW8(~smsEf)bn$ggt8p%MViz<9vl{+)#Jmr=2z z!V&!1UfOpR$*0kKw6tVGpOV;nIEB%JsuOJ>I1^nk{kCd9W<%pl^Ga2d>_Wnfg9JIH z(t^#hFDo@C=QYV?CeN&c34kZ_sVk(JSnUhmkQ&VPj9{8wRimTGqU$xr#FLqnZihMj zSm(_Z$*VS+dtci&b!DDA!Zd&@pdam-LDLbQNjPz<9Xk7P>O$6P_Aadc&UPC(+HYq* zpf~ac^*Ex_Sj&eb(@%s0n){DEwM+uX9XHTLFBPP-*3Rvtmu`NzC#~t|bGb;;?aDTf z&4~a8>lUd3klh*LiVXp=(j3FExse9Gh6IRf=C>>_al1Pa1DlCLjT_%#?!*Xk9Pk`P zj312SP!5<}BN7mec01opX{f7dyg@4nyV8TdaSuq3>x?gG?QqRYGFVShK{SJ;?mtXI zsvL$ER!{af@+Eo~)Ss;QsU0Ge53nw>w~N6_`LC&qr8IMr2SJ1?4uKidvvMmF!e2 zb_@8jF?P#6%ixj!+M+XKO+wGZ`vEE`M3rxs;10xCn4U@tDAFT+!<)C&wO+J*P##}S zfV$dr$NOOy?qxIH4(&bU*Bg6=&;xGHnSRVk#t#ImN=1@3XK>=TBYVI5xe4++4{)9j z|1berv4DYv;1eH`IvG$*jQR|-C#|RXX`f>Z{-s)2+)U*a{&beDOz+-XM?YV;`-A5n z8-5GUa=(7$c_!Z)_xBho(WYV!{X_dAWiK-DXO(ZpGDe}i_)+nUz`5QvK><;-9nvNT zyd2(%Y8c6+I&2&+@sZS!oX_!#+*w^uBuWd|c4Ubp&0+fm&JTs^v5)cdAyRJHOsu4pZ+101+-iZuwUISZ7(U)sKagn{ombLOKVEuhb^!hDWxJt{uhXF=HuNf zVwdv0&Iu}U%=xySfAoo~3l)PPT4CmuO{*tiQki;qx|@w@4y-{lag9e==KuGqvMjK~I7mzi^O$ zkq%@{Q1IL?cCCWAPp%+7UJ?fuVeI}(>}w$v?T_*#5l{l+C7of>=CEiS1Lbz`L7fQ%zHh3KM@i&WM7l?RoHz^0%xjU!X+uWWY8*MqGRVIwq z*K|;Z-8T9bX>(!4)}G1&6RDy|Qxz$a-S=)*d276W75@3->{0&C(XG*}-O95`jBknM zF(4ga(zl3+!QOq@yxUX3*yUCF_fbGDU zR_=ZCp+k4z$6&D%5kfGa1{!U_+_>PRg*;#Zr4ZzL+EXjOo&7ee9B>Ht{pvqy&O8oRprD9y;t8_!j zE=a*)@mrpn?Ac7Y9dyU#=+Q0fKTMAll$X=C=c%$@GYnBuYxvA_mBt;#wVAcYdNOZi z_eHHDd${(#CNhnXkTl*nvNF-SuCN!=<7jHN#4(WLWC^KG`|Y(N8HO@{SQp-Ud5PkOGJV{MVrV}LhMTIGcs}B*Ie~FTg<9eaN*}{QI z(o$r%+*FfoiEIsU^Si6I{(9lqz`_mh(cZKqm*W)497Jd0K9HPjtFC0;s9sW-s5ELH*=RL#Ze*)nzt|37-EoQVUVP6W z){Nqyfj}?Thb=je&PGQp9zi@#VBnZ=CaQ?(WG&sL4`Vf6?$%n{tRtn|g~g={K2&NZ z>ipuvfzE=x5pxq*zgC6-C7Q%#@Iy8JnWEQ?@gq{~Mw@^?Ag@xF$VBk~RL%QwU*H$u z!{Pm%D3R*WkY4zuM3!9BCfj;csxjf7`YYe+i-S^vV8!qBWw{+FI(m62jkLAwk<>2i zz1f7S$uO}$GZ?#f)`i88TF$(66LbyOz<;$Xy1?w{uT(^QT_Nh$M5{dte5D?cXtauW z8WOT6r7tsO3XdE6_d)RgKp+1Ld}IFK%?`AH%eUwSvLD5vWxX6fE4PJqUQNs#Q|*yY zLiQvwjKFTFWIS1eUaU~J8;=hB;jpnA^wG!v(xPg$5mqWl=Wy8K!eh?&qD|L6UO?P~ zUm<31&rw}z>UFiGV-s4DSbHgxk}%)$(VfCh=Rt**(kks~@z_UjVokJ+it3aKCB6hlOS0cC>7ZVfUs>ReU^? z_gqF*p8=Et5C6%JRXtD`ZXY7C7Bf#d3p6u=%v!Bs=ktY+Ms=TDk?tmuVF$-oE7 zIlg`wnW&9jr)fgA@=tg~1i0!Y%GKUloKw~B)GfrUoX}^f%Ly(fv`)Ep{Br$W6 z0S3E{3U45pP>(BEyz{jioyEG1C(94M8`$^pV}?^5T^}B>h>N5Vm-DCSu_om|UwU!i zWb4=h$Hx`57T;Rkl<3=49v)eIvwpqT_9plh7aH2{5CXJN?o$f-ARJlFAtp^NH4}l| z+!-@SkAw#o&(ZsWq|H8XK&EV;)gB!nPliU^ZhVFw@+d;<5;HSJ47rPS5p#WV<-u02 z&F_emxgU^)!q=~RSE8Tlh-h+|zt3S@Ism^|Qlx+U!{iC#4pqb!el#xL4EbHQefArb zDe?NlSINKe#~U+Rs(y_9rZQMIs3t!VRSkWL+@UA%;5bx`1nDHv>##XFse1Qz*5aFE z68V+NY7o)CK<$tzrb=lj<}%<^wqW5xDu={?-7kta-ppWBc9^4Jri!Zg1Fx6mC2^(_GhrxOU=KT zw>jo~r{9(sTnsuwJl7glq(+qm%M2evW`}fZ=*2+&SfH&*|FA6GdIMY1l5%&Uan1In zh>13M>y1*xecJN7f9 z+50J{DNUfPOR39bFi<|8Tk8Ex39*{=xM1kxqg86=p27xNg?s~=Z(?C};Q8F{5VFah zDZN;k%LpyR^^5PS(BG=STtq_QC}9ile39`hu*BEp@D3(OBlA3qYGJdG*;hsB_Skl6 z9D@bu<()doKRr~y7`MEU`0+?Hh~UMmpO$^!d??vX@EXvXO@aYMPn0)&d`W%Mm!Nfz zG~dm*MmmMu5wD+CZ5i~N@L#*e7|Uq;&+N$nDp*1kU+OLRq&kWVF5{KC8GZv$ z&<#X+G(|j0HL|<*xJW7>IburTm&h!AlnAuFGs$;|9!aHu-u9gLVTiE%u&ue{!saQ$ zw2__0!^?7K1y97fIbw)b^YLW}SBPj>H2rb2lMiDb(yiwPW(KTXK(l&Q^kN1(>?S1| zTjpO1P!ZXNE4|PWy22uJHlXVTVal(roY9vo5DRb$*_I>@EjRQa(1vD2W&(%goY#a@ z)x7<;-N#pguC3e?{Zy`2?RUg*N*Vs3@se$fYbyi95gO8g;wmJfUIfktwt$1d%LZvd%Vx8-04(-g z?OAgqBh5pR3U;r44G=jZS&z7uZ9BHOl8{6b#rO#{Ibah2N+-MMyY zC#2({pjg|r5@#bvaZF7=jrS5vnGVQu605hYJYiw)WvhstS_9KLfCW=>XY7{Jcq4Ot zrv+o=57X&#Z6RQ9YqYB~#`2}02cz*h9^{}X?WgrV0V_fxPpIR=Jr$7GR)?QrM}a&( zN_1r1h*Iafw{3g?v;lnN8zlE|?Guy&01j)VXEEeqH>b6weCnIavI;Bi&e;0fEuHcG zlz-RdW~|!fk+8>V>fHX{jU+R287!x$VnfhX>HG#BJl)mXv<1LL4Is4O_Az=s%4766 z{JZus5T~}NaoEL|SEQRkey<;859f*;S()je%eOxAwT`YKJAT*I?b7&k74+^pb<6aK zG(PK7(w>kqJKA?iq3RfZfp-DL=@ud(T=6QqE^|b_Q~~{`NwA(7PpXvNTS{78SnfH0IYNlpL>lx-BY*} z>?6sr*N=QWaGo0WoM*GE1w@fN?Bn7Jtsnz&j1gZ_>7+4KY(tg9?@mXsSfT5JTbkg>8Xn}UG3E?LA3{Xy0rd=HyupQ^Qc<9m=3ZLY zo?S7&c*(vL|A>ok0ETC23Aq3Iq0E@=uiU?}YahPVPf02~9|uJ~{11wp`E4)@V!0M0 zvLhdeI0IuEcSkp;YfOLUO@4#DsA)HFpa{VB%Mz_3MnK7yR} z7Jk)`Z5s|dYkK}?r^SUkHGSQ#>~3Q1wYLg@V=EQJ4+jlV%`mVh^!ykyvdHACPWilk zB)8+xslzuH-yZLkiXQSh297A;`+1$w2ooi>bcP>xq$uN;KEShFhrI zN7c+=@rA1d>#V%h6J;MKet0}{eQy|M}iP~~B!OG08@X?t2*_Jt6b*488r&=Wge{AO=ha#J##93ap}{&2Ah^x}S0q}p1r;*+cqSpD;Nds{;D4O-9q$5?5= zHi=4sPYNFrPLZ}O#`2`Ai4DL|lFE1O!IANCJ#mwyY!K#k_K6?IsS^)-sQt?xG(Iyj zgd#$WyGilFn#GA-s5F(Bva!QbMGU1U0#srjSHLaCr-{Aj%+EMnk4I0=q2rKv!2>zHh&(qU>p0Wk(d3+-w_?>OR_21#BaU(@9@ChJn{`Qv;< zt6hH9&tx9mhwtIAA;W~!!gt6$xwTP>++nQN)e`vN1SQTURgnQY3_*6K8Nfgsl?$6pTqg{}$vW;{-HGV}|g`k0ENv(ci;NG9~op zU`~1F{PKGku+Ds~jdDrsS$tqLr$(AkMj7b!ZBYx>E;FH!2jwf6R#zBp&g;Z;7#S0bJ_`UvS2R5^$b z5XmQszxar|U1e94y1GotEIdx^ye%-Y2A?hc!}Rv^fzgOYJq%Bk&<7G4C8A+R%XQSF zQ7#8(ikx#xJ{fI~s#$q6*khrTlwck8Nb6~vPB{i&(FLZ+K?!Wjxrj3~v#|?pW5Yj2 zrqw1q$=l=ohhlo?KeRjLr(g<|riWTp{oH*#xAWkQ zk;6G2!db01)Pfuu3|K<`Ist!}IM%U(>Csvt4&{3hG4)9Bw?eiL8wjG^5s=wp%M>K@ zb$`gj*6y=rb{OQW18eE|Bh&}voMU&s5FpixC(Z!upe(diI44rxOz7n83Ek?!i-s0E z!{2wjZ-doP%XK;GaTh5v%X#oM!M-MFxkyCV-IFMfj3tA&%uib~lqsw~fG4qC3{Bi6 z3y=!SM&I}ncI)085b&$B)9EcI$@^~sI|I)X`yd9(^+F2Nl3rB{rWjd^IhtykH&)t8 z<__RRo@iG0J$!I5>dmOxY(7Q{f-n7L2e^T5P~v1>NSOFTOVNu43ISHG$H{oFy&%lkYC1vSI%0Vbn6S)50(6fepUc&BU#_`kb8Cy zL6La$+Do7lBwf5PYSF9YX7=SV<_707rQ@?Ft>z+-+ z#k+CFQ2DY|s|Tv|w(bS>H`4A-?t=Ap{`vaHc*xQWB}C_=dGkD5?Dw4e>qGom+PA54 zxdkl@s_Nc(RJ9r55Qjv|8Bhp-8P`*wnGoCNR=hasrSR^aF45%N6${zi`{*XWmL_1H zU;`-5ukbdwD!%aN?ctzT_WU+xB=xVD!efBtuUx9I4R%e71xPJ152&})C$xX0jLb}| zrZx3ioWKLWsZiDoibinx(dy)LXvHYdUmQN-^GLn4G21aft2QtN;fmp?KA$}qhCEbWOd3@v}molsKwx}UyeMF!ti+gVernvF+xgP$q;I}v|W_A zRzVf@X-=)Y;79?;*KKQ9dW)&!+UVB)mYi)k>DUsG}a`R32*AJ%%n^7%nsQq>n2 z1|G%+zI1oE&RY_l-@^kLL~gT5@4f&pzt0!> z(JC%E>Z^BdYBuTeYUH2A=RN=W^7St!(Pw-Y5Q<=;9fqCas7o(8 zSTxaTNJRf(avbyBsS_7uTXT}1xRuce>ih9ADuTdA)uG-t8V5qGNwb!^Ef5kVp&4;BWJ4UB?ci`@ijJ zB+i&o>>)gF=-5y8ZX4v-(SwSgOV7a4K;l(-d4hI|X#K7r=yiY6Hup;K)gxu1&o2}G z)HAgaf`nI6awm0|ehS?0;B#gI2-Eh&-`(UDfT5<~4Um9WBLU(mOZlUT+C^a-_j>jQ zCC5HBSxDwzMtg|J#2w9>d$K+tknYFm=*&l2(Aj!tCk#hF6jv z+)|LBnb_1@$EKdGB)-%FCI)43$asxm%t@4+ud;Ox8!|zi|E13iv3@#Va7ix2CA>gW zt5kWUgHuP9%uxgkdXu&5iB@p7Y;5^ke_=^vGT3P3Tg4H6M?g;XCxcz>u(M3Z1BW76V@&ajvS}8nKA_<8bDoOpggK+ATSdJ z@R&}z8m3FQya*Q&scsQ%mY`5pe&0)SsgL*A2^FZ+Q$EO>zZM7hYJjuP85qGM?>kYh z;xzM)Pt~@3B9_F+&ap(pxijJXNXsR>{a5CF}j zziySrDVTL@z-vlFr~9dT=FM$&iD6PEA8+er+w^$85&WG)Gy~A7olL3*qVpa=mTu|r zPf_o3kt0rcKiME4wB+|4C<<=h1DLLW(*Qt=jizNO zII=KYfX25DrCseS%ty^@xPW)@=FB4~q6H$sR-2ce(|!gfE1Znhj>Gd-3HMB6U>noH zW4kvCcG(9&(8y;Y#jcb=ARxXV4zuobkI$ljVgZL{XgJL~;zfkkZaqDFWS@HUd_U)` zSlHjC%I}75$Q*+FtnSBJ+qBjV;(*f<#f9BKSUJ zwg4NK3g^-%?UJL$2(1wSq>^BE<@4TV68S~!l9$M%Noe+P=3621iXUsy@%ZQaP=YDo z45LU6rk8;|+AOiU-`%lDzR<73z^gUUG(GitL4CSRJnp;vw~PW#?Z=OQvohj8S%=O^ z30a)EaLCJ@HUObW_4v5Ck>-tR@n$uocUw%N%fj7H)ZKe#HNHQ*KN%@sHTf*lNwYJv!_xWb%cz%uHT|yel|=Y;IXf82 z6g$(q@Pu{xDb7~%)%1*UjGD~5bx&}|_PaBN%>MUjbl1htD&OerWYWg;mwmVfSpXR2 zkt>FPmu)>!2dhvGjAI}WSc~C>XVaGZD!O8#7O9V3I6c}Y-xSUz632iR4zkhU=Ky*r zxW7d{HSz{*U#UjQC81AuB>i_^;dIp#hKZV4poBk%C7e8M=e<1@D2#JSy2p~ZuJg*` zB(LK%o!4d^jB-RgvfP|f9(fmE!9KsALEl;kaSditGlty5*7q&gJ%~syJFe*k=1Yov zwH=385#FrdD-C+^VM@0C4#j;)PRl z2xjtWsnCm|ZfGRWoM^1uzN4>CsZB(X&^q6*>bU)Z#;-SZwo>4;j=+_}398nhI3$~z z>8FsS?^$Dv&*<7t71=Bd=9TQ9JR^+|sQKY>JR%p-LlE-SXN0?MsD@emH}sJI1LT+x z&hTV`qa>Frruog$-t8*T+wXN{f^lc<73WtjuJs=R<=`U%0jLLe%E4Vn62T28tvGm> zzw3N#T=llX%rlqPkXxxrCUT+z>}P0jOzX_9Pak6L2tBh$h3z3q;1N%~16FI*{JyUV zH-3Hf>}J%X7lS|6Ui{Q?=1VuBM*E~7SKh!IM!H70=z>ptaBqW8;zFYKe4NG_RRjD_ zgL0A)@9J~tJGpG!K^n+== zcO9qY^g}DXy=p$+krZG1rP|@P-Ge)NM1U}cjJKm<}w23zw$fiWpcI(G|2KK zn~m0e>t=;wwty_Ll81{rJ*9B^vkrhl`UiDDWv*C)_mX+_fO-v@-Lk=>nOnDfhp}I9`A!=_2DJ| zdYSyP{gvYLqsLEbE+fikn+`k8*QEOvz%kRBPv8utv9MI~FoYKFO)C|FWKsj;2t7FW zWlLX^wTUN@bqZ^?dzNqDIzn_s$BuQ zizoRcAm|QO#-X7l3rTK{Ek7D2t1ts8R+G}HPY#1R#@TtQMj6jifb&f(7;6cM%{7Bv z!1lmIo5rimt5#CEc05W2)Al2oQv}aksh8%veLPM7@b4j{_?wOqTd=n7e$Bh7pqqd79WD&lfQVUP1h$Z5WQqE^T_Bl!+Q92 ztkPwz9KlO(etmnhFWz2=(0p#YcTuVA zVkdaz4T2gb3A9jLFjZ`Txk-(htR%UXs<%=xp7A#=g)aNGKR=8iOk@;bQaO^`gyg+V zzD*wK;Axo&7-6w}ucZ^va8)C(w9F#CDT<3}AjfCdh`=ua5LU<`y1* z#rL9j5DXzpk}hA`o7>~Nj`XicR}ySKynRa2ty%9z1B6xJ>`8@J#54ki!G@F`EyD3~ zL2pD3yf6u)u~h8056ASm7@pf_T1+O*feg1<5m+mDqDpxGtHzj_4|Pb>Ydys|MbDL$ z_(qtzR-PhSrcO$BrGTZ=7q=o6FA0-?I=44XLoKgCHgln(9Seq;wS*CA*H`|8q1s{2K+z$i8(yU znV{zmqr^g@YO34V;1%^x++UZ6r%K*-yH9x}>!lT?FyBdb80^YVBn^}5$k#lM$lYWC zygXL*zDtnLUx5p5+q?`_COy#DrpX? znSpL9?%?#{94Skh#h{#;{B2uv9$|h{2=3264zt{BCNdLF9^e@EKvxDss^ndR(dK5>8$1{(lGJ$j@T*i3Mz(NMg=w3*yG0zuVs7cl6~I_hbTGm zjOjb3&IF+F;{Cnq8io}3L{uL`$r5?h+4a-JYJeK!%`OSmQNWGdHcH)NpJCRKd^HGl zmG}tB40e6u85r)+@8Oo~t~k%vl&K>SO0S?=tzmq0VP?F_?d!-_pkN7RCXW@c<0a)F z^@?#Id)%!G@a#S>3)6_Ri;#&=0sEn%&J}a})?n{>-+zP{{hC>izJhDGz9QTprX;pH z!0Wy)uU4E}sTQk`h9-2UE+vc0^7o?^;x9KobtIW4j=%^M#d#aT6<1HY3`Dkhl}0mm zvx8o|wUVd3_9jo!G2n~zO)Z#{gfc&s4-k=M+FS^FTQKG}JQqPT1Y|SrMU(YVx5ajVp>fj!0x}Wk(Sy^?gZM84VPwsz;~-ch(uzygR)^_&TqxW@=-r;IiJ|H-Z<| z-UAb4h>x4`83Y+pYmc?_`@zMnX6wfXd#d!01qvA2`DTN%?6xudlP;H~62bp33cKNP z93bk!8lq}hH*qX~eW}~+lX}_$HA(H!PK1oi&&s525j{)>_z93AAZz=o2$E3s$v{J% zcqCdDr&?&Ied8?2!w0k&?T58dmat4M$ozv$06W#pmGtq7AaU7=Fs{v(;>PmpGm573 z6>3!}t!ZAfps=djVd_`)4Gg7mHM@)iK6e;sG68Q;+%VuH{%KYsYvvkSmr@~N@<4c> zFoOon05KAp`*VGJ;n=A)A)-e6STg8nguy zdWlc=T^buFoF_izUZUJZ&C)WaS z`a-^-%#9-{lSjw~t@l6>VjxvPmECZ%tB{CBFkY)cUee3a+3{wB^jQu{WnQ(hCyt$K zcvtEXrQdFE01W7uaf)?HsbHQqyHz``2lbg7UaF=o`3hx15yav-l>5D_Ba1u~#s+R>Qg#fBOQw%&rvnz+ z1x?~@tx)%cZfGs>Dl-?B{iO(D62~t9d6px_Ww#r5)I+|3b*^qM;*!LG4+{T5lKol4lk9 zi5dSU$7wT?YkQ=vw8hzI_ICMg_$$Qcw?h@N1=ot;;@RFE$))AsCRs!duK#CVc_8g)_+3!_1`tQs zp`3XBk`S)`4vBVLN2|-VI@@hFKeh4tfvm$q7m2kS`^BpUa8=+iBt?xM>;g5r#QCT_ zM2DMn&0ER4PVH9~C-c8qeww_NadAT9PoTIHtQMd`z@L#UPY~GQ986kl#TDE}3?{_n z>Ju$_E=AQ}ywA=|9zYwMJ0Ll4)AQ2?;IW`4?Y&mQ4XXtxFU~UdcZPoLV$(~Xcu(Oa z8tLH$oA_UzV@|{mvL80TGV|x}opu9Cj%j2XaU8uABR)wR0O8+sNDO-im?brA=Dp!( zm{A8v9jyhKB*qZ&mE-2!V}hU|w&GrvvJ3VgPHJjjz)-?4WOPud-U}GtdxrA&tPumJ zyS>-GXmppL*4m8$(=QBE+UT=%+2|#?o9pUw#|+Ard--HGUq{{cI6$!gLF5tG zXNgOHQiFA8nWKJ;sP9_krj8%0wlq!Y|1o|^Mjn|{aQ{kBu<>|i1HA_)%_M`U0e27e82Cd^r$05#Xa-RoRbh*3t zpxSeV@QD{Iik?qlEH-4C!9ouez!|*!?k6jQa3Rj7_i|;Fa+S5>O;5_xTCQ@amu?G% zY!DfP?@!AiBA4Z}&FTw=q~zD$+>rB(dSK)F_U+Q76C=bHFe{hi@$W&^Hur=JcW3!+ zvlY*e8($N#n^*EiXWe7=3;I;=yJd0(FHXMl-lf!SnGK&uMSibduN(SwOQKdroGSI9 z7<;PTdDzTr*y3M`FB^SnuaKP8V0X}5*7V8A{DBd9Is~v0Yo53G@XKD8iP=I%^B@at zK*2}#TrVpuB#KqWW zFSq5)L=#nYIuCTh4by?jexvoRZ)H$+?5&T*oszxpQ@@FPV=PqCdNcRRb9S@s&cOcn z;F>UCiXT4!F6rpQF#ofP8@H`e@-DT=D%iHxo}sk!L*XI#WQmm5p#h~MRY33JPQSxA zJ32<6Ph)Vm-j~nWv;%H@1AN~CzcMl`?dIP(`%?MYe^~t3^5hDsMdKE1N`>5r1}qR+ zC9iKbxxEM!2P=F1&Iq~BCA82~?;=PaHcGuM3A+IA^pZm`yEg*_(&CAR!HV}X(~@So zYDNv|l}GYTlP*RtdPL_L?88Ma{sveD2u8RMWHtl6R??FPx?*onl$ntkbgs~rn10dr z>dU+P%t`WPP?s>V!j1e|mhVJod^^DjhUyR;4d6o2*x5em6;%m(U-V@0;nO-Dnw;Nn zECPkSwcj1YaP-Oe-S9sbA_0rT*^BnXmxS1ZvAL%|gqM3rxA%1bKD(+(d9UV#fO5kl zt&R^a?Jy>&Bk3L74K+)Pd4*!vxN2>;gtwnxw~||W+{f0MAh9l#r+$zBTf`LwX?Qx8 z$5uljBE^sg-f04NKScAVLYiO;WY+FxW9^XHB(A1iBR`}ZMwPt}+fiWzv<2eQK zD_A}p=nP-#Bt;YLuoh$trnyh`esRc~!@0eHcIi~-hUPq8r+Q4JU}U3dd3CVgiwl1# z0uGUQ(bHXVoL~>~I_e}HFI+TIH2`OZEU+r@=bmsS>2zra(?|{RIhk8rJ*p7l<9^=( z!eYoYIRt0Ck9ITOr4)aAp?8_TA=$c9ekx|;Btu2S{Ae|DW+;#>m98JWp?n#tN-zpx zJ1OIpG)zP`)WjX@OB(ihI>&~6#lDiFr4(R245Fm$T6jXg0Efg!tjf`(Y~Z2rh)eXBs5_n6>} z!>j-(MY0-E5U1D$VTx$#;A;pmvHLjG-bKVd{)kKzrTltsbaRqyuO_-GH4oUE7vii> zt_I{(?RtM^TGxA}BrjLiAC9Mka~Xj1E))1ZGoI9NRz6XHHVgO>grK+N33$n%O~N&UqkJ zpRa&LB+EVs7>C|La0;qEEs_YoRB>~v55dy7T{b*8X#9J)gnaok>Bhxr8ACCd1Pm@o&Tn$y06lF9s7L>Dp* zO!rYk0H24A4Y^(YG)BW?6JQ$&t&7B=#3i2Ya@WavoqeIV2XbI4KfJ-MB>KGY6)6@5 zUI`m-Id)I;_qQ!$HTU?u@>-bknvU%jjV_~hsjx1qF(XMDg5+rw*PpCW0G+Dw$ZE^v zV=55lRO8-Nvb=3#G=JhfADMS)#R=YdQ!X6x03VLCpRuUV`i0&LgiBuhRJj6IY4fj%`?>qz#Ti~fJ<6aecpnVn z(&miH@kn%=0p0JWtXf^!w}*q`UJsuyw6o~;#DLsuW$C*O&F{>jlxl?Iv}Zm8d#74;s$50ZWLj*F#q5J2X^@u$Lv{+v ze|>8_%J|f9*R;f4#c&satuUCX`dr`EJnA{E^W2o{SkV6q%gC}bK| z^@7nU$jbNTk9~fIa7fE|XQ8t++_$*dYvWdvkMsu55B39unT;-h0gLK_L@!I#j;>Ad zw|ql(OgKGLjd0e5=;yT`s7K}MW{Bqiot9`g99Jj)8gmWQZ$tRrHa%u^IGlj z7P>hmnaXy*PnU&633b8k=V6=CU;wD*{wBVP2rgP$W_p>OcuS;kvL3B@EXR}Q8R+w1$H zbVBZH$|m2r!^L_j_}Gg+Tp>1~*1fn|T(~FSQkc>RUe}A#F8x3~rpeeMSUqFZJ(@fk zAKz+xFHKWglgZ?%i_&@oYuTce)lv+>jB)78T5zdnxU43tIVD9Yh4JVGTW~Mc63|Xd z%J&}k>4WbrZNCQnLJ=9~-BwAJ&Z!*ctag{roJ@S%gL`Iqzw&XCi+PuqO|GSjr;mQQ zoEl}PyLE-SbV#Si-28&sQ~Iu`^6#-6)U_WjJ$%4!#QgF?qRE9zym$9B=~9(e?P^Q! zZeAACqj=skyjQ64wPchkEGaCk^p~Qv#1DAPq~5(q=6tl)Wmn33A0sU&q9@I++t}E|vf?D}raqp!2+pLiDz1y&mesuW zMlO?6nOWsd=Orgj!9*pahcvG=?@+K)M%*lZ&3;|$?lv8Ti;bJL`P&rv%=|k#sL;X` zGej9>!zM*3RU55nj-$~=1r-Nz^FlUj(~OQ_OUx}zKbFZmBQ$Kj6sy^Ow>m5Cg1LBr-KTGv+! zW0g8>RGQ2T-;F45Hn#b-jrCLrAwn}XC6Cp&hbW%Ax7fut7TayMd=^+8CX4drDsV7x zM^r=~Uz%Bm?-mi10M*CL4sZw{Le7kuM^eiFE+F>|2;_K5u~+}-Lgej7rOZWG5axbR zZw(DKHttG#1=ASb!2a0gFr4K4ShUH>ng}9rJ#PAPL~pZ;{cO|GN-;#?Iql%aX&YQq z_RxjKUgyrll}R0xWuNQC$K^Kj3)U6dUQAt;`qv{wB$f<$HYu$H616M?ul?}*ocubx z+?^sNokve4s-#pfTB~Pn?WtFvbgHx_!^Mlt4HPC95-F@l!W9j}8au+C)^$!B&)#!{UhTeZHC zc+2(dy%Drw3Z$VX5vooQBZ5bz0#H=Tiwo|&A~=b1rZKNVuPvXeKF6t_eHKXA=;Boh zuvQxvT9V;AjA^Wm5uNAj_IcCd^_+E2I}=yHmFPptmY4rUWlsMyIwX~|O)KQSPwC4G zXV0DAS4=ch=T*L7LA`zT14Aa67S;o*cli!t*TtY>$ZTG+HX&=T3~#Ot_5E1yJARm@ zWu(-vcfK5D^2PYSW}y1F*pvU65Ka9rkKq49uD$=hr|n}umAE0{^#^W z`M=wLH~Ec7gtRpv3r)~KK4RS!FT!}exH1xx9X>)W`m&Y<|p1gHyI$;!mQVN^E% z!UjLNQ6QGHVIleH!o%)WNeZR-ZHvwyKTKtu(uM)r#jC>ZP;pX)yUtERM%r{#M;QR& zMfmLVuq6?o;wi;}JFXYyh!w7j6Pj%YkRQA(a4C>35xy zOgPB__f={%e%6vX9Thp2k;0EUOUOI7ffgT-`9}qf4$5pqH0p)%9xrC`avnY3ZSptdt-Q0o+}9I;+iQ-+^&R7NrR5| zNWB$a`i8BGlHQJaE_TUWpiGy6RRsM*KZ)Oyds&XeTV^9iW&F=}bm#6aG9;?W$+ns| zp1mZWDUsZ~+KkbyU0oCAjd?zH_5A%icS|OBir~-5tAR5OTEk2C7BST~AA_w^0OJmP z-^Sz~K!C3D^#Bf%s{p&+I8uV^j0sTv0sus-QhTa)zr8OGKT6-3{^Y|JVs(|S zVm=u@;q;e+llFOLv9WzlH9lOYCAQC71;2Pf<0wpR!S2n2MJT=`dO#mRQauPJTL=$l?CmGhT( z($s-Ty9?Z8zN1B>GQg%BAj>fjzyMqn7$P-bER#+f^`9MQg8OQ$-RHf|ed<~h(cz9S zP(P!U(bCr~-*TQY-vU6eRcj%)-42vhLttM>jtVSbK+Olu9<@JJwE#D$<^pH3J(NJQ2s<03`EZ69 zum!ZVmouCc8I#=Wh?-c{rrsG(fZkobMV7N;BV_}CZiL~!6uiq09i8kRMEpxJaaSL} zVEe?vlgyexR%UQ(U?86Z1G6!~pWWBN7^AOSIWNNdk5?SP%wAm-&hx35|JhL?2HMfj zVXpgSV|ik@&otAg!QMV;s@pL6F>7Db%9x$$p?wFAHLmz;>N%O6YiyB5PxoEh*Wq2h=6k+eY!h@8Slq5c)O62SxMQq6Tm3F zs_(uhD>}JyMKzl;)k!#Ob-eZSPel!NY+$8>ZeW-ngF!Vr`K?r%8i$|&o%^I*v>2z+ zRU#etkH$<#&X&()v=eS4`dLuIagx^$8O_(+Ftdl45o*IUam!}qt)tb{z{Q%~{J@&s z9Qpo~wwvz8-hpARzYqZ&)bfuF<6$((7fJQrXG&+>iihPbw>T_hY)qVEf$^Q17M`k_ z%6Fo~q(9Qoz`9xhwvc=FC2(ec!G{@+C}NBA9#=1n8^@MIiYx7Y>A>N8BUb#FMQ^8H z<3^oBw#r+byL`t=;-=z;{XfWKG#V4rOd{hF#ee!wG0|UR(;$vsOSW}JD^}rym*ndl%c+!*} z_l$3dO-uGC&et*^N8#h@0liy%O;|X$JBDvVx$-kUeWir&b_JWpw@;fbp%%A&*JBi) z-B{I*=G@s$Dc6eQSeyf-b~;8_1fW`2)kRvJQ4Q^lhhsG-3Se@$>^)Q;jJ1W{ z>sUwVkbJ`JYY^90!2F*06?lsFi;1_B;dQmSUa&F!T;+e>I%{fV{6)9KO*`6+kw;^*nDl0T*1IwCdN3E2 zXW2*7j|Ksvi*D0?KZV{b(K3>j->%iw)2@*U?l4^P;vPS7-8wNt-4ppUc;&+32XmeX z>pHc@yWf}#-U+0+d~B|dwx~VOpnl`w6Kj3+{UgIjL?LAx{T!oYqD^^ENz}dM+_n5b zoimBzOmL+`kxvs+P;XlPdiLQIVn1qd`kkCtYqiF&+S@X=#nc-Hny0x%R~3Gqs!(d7l`k@*kpXc_0)&KWA6yHaA=$u$VsWu-squO(|EBUk#4b zs(}Bds7*?sz@Tz5Z&~BdY+Iy5V}%VQnc9NJek9j$rX%!_my-{xH=mi=I>zjn?v50f zsl1p<_Msi1@XA^UK1AJ;H6tc{&fYD%K*6v-t{WrPAQr?SU$owRu`B4fZ{DyTh1|ac z@%4{o(WAEIp|y?Wq8%&&e{~p~WVCd`k|v)j&fR+>8}Y4ZKu{&qRm--z&$+jZZq4Aj z_#(@e9<=7>(*XLb^USGJpJHQ&-z(qsE8M(NCGqDVmQA#{cP-)i?d8Fdq7YLyUv5RQ zx=_dD($#XKDUk4+ySkR^s2uWrYoYh2YGS{X=$a8lPssgwu4avM1q2V_N9W$|W~Txf z29uwjvGy5JbNgBfj8{LWh6>zI+h32NqYT_UT%t=H-v`SuzXBcb+fUikQ9sIQ8&oxC zM@Ln^2pcW*f8U~eB(OPp%gEPtmN&^$cW~3WZ##UvIrZ;9#^sFSH1ND>(jRey;z}>_ z`?Vh3uCsSk9eJhXzEHNnI(~EVO?%nnO7()0dp+ZZ28l;^Lz(mZj0onTyX!O)_IFZ+ z`s^Q5uTR;=IaKM2zo|~UHX5fh)kzUcb48xpV$W4itKi9>i!2kI9$Bj?Plh-Dpkk(L z^;e}-bh_1CgPN3COnYS?-mdkFC=lXXe-mY-aX+(dIB1L6Ayk2I|3MB+87sf0|^>amKL?;fW z^HzEkaix)m-$nJRRUuQ|^W7XJHydKnoKSzx>rcWT8j49;8hRO+eqPkNluaRaa$B>w zP0^_L4svJ*wYe<`kE{8uYnR!T4NiW1}lLPLu> zN=$YN#X|PGcjrk%4JEFjilrAD{Y`uV%uIqxe5^<29z3DRpLO>cU=hyZk#`Kg7qVy2 zxxk*;<$dm5%FEo*eGg}U7QXtF0B0#Z@o*e3u@JL-;AE?rBKE-8aoZ-bovOWO`?dqE z6bIN{Nb_{clAk+HV=V*RnP2FI8~R)z40{^}nYFG{<#gSyZ z5<8E_4M;kAN{TC(*M9{j&pWcHann>^zPz;$To&KzOr>)P;r zpRLL*^xoIe4{uZ*;~&32&$TvK&V~vZTqe&GOKy4<>AnE3-1_`R#~Bg86z!*BVdOV> z{OM=En!9K#>9_T8>u0<-I|4HKtlsT0^CPr=_{G4Ig>8$My{(YV=BokeFZ7;8$T!OK z#Br(Wf0*!<-Fv=ry4sRPcU}IH`NM1Qc#)w1G1qRc#~QuwU3xBE7I$;>WVU@ub42wu z6MN_3jp9^^kN(dbVXsbQxx(bL$bdDSi;~6rs925YKyz0Y3$4hh3=TS88nVN;MFxxa zdX~Oi*XBKCT8AWzhnB1&9Py?TM)kQIQWC$dnCOMX?#>+-zY*P$)UxU&eX7#P+IjJ9 zt&soQpEI}Y=IIvmrH;JNV7jWcep;@t*WfgdRcvpXas}+ZIf|qN*jDq}a8kEhaIO~0|lsOpHTHD*Z3QDL3NY)PberVmb z*g2m9e58A?B=wzBW`P1CbinB~3V{{EpA?J}F7YbiKRAV~V?)K$GGD#pC^Jlf-HOu1 zMn9#GJRd*r^@c=1-x4wn(_o@ebJ$0(f&}gYvOWwc#Bhm+d0mQ(KU8I}!Bu)!Yr#jm zzA+kW98h1}{hJQhunivlWVnixh6+AA)`}>BuI;-}dOj^k4$tHaKpDf)YWTO&{vmqW zwl3oNWV2JCg3<$)v{M5qk5tjJB>)-Rv)!^&P8dH_D@_8*rk0e3_I78)39pJS?yYzf zX)0~pN~?B&Z_JW1!5e%aW*DE3G%|93MsUs3H#ZR3a}duD9)~je*-Y7-8`Zu`ZTNX& zM#xI*N#h;3{sv5CS5i*{MKGy32&k$F2d-n3M10MUTTnl5>LL6Rp^xzihb2V5WeTHS=_y9o9`;$)UgR^N@l6b{EfY)I<2;#uO?nlUA=N9z zv*CwV+1Aw3VvJFPLU3m8T^rw9vTzd)PMrGEHPacO+Bn}61bg6?*IYG`r__2VpDJYd zN|_73v05vlADvgCw6P}00-nz_A#+j18J1naBWnNxu0YiU=>qkcnJLtLdh}H@R;$c! zc3?K220lOKMZ9G>WqCxOhEeG7n+O4!#z^=5UT@&T*HjIE0}@5ObN<yqX3$%^kJG3Q+F>llbm8Z1{X~pe=%wRrNd*zA*;2v>O0nB#Hb5 z5L(pNi+lpy(=UmzWh?4e@_~UIopDvxLlA3Eh~*LM2&QQ7w`X@3=UdM>E-MCbkxd%L z4xRofyKCmhcPF|M1TiRW&kd+>HCav(`?gMTTe%PcYKsN2iz9U_-? zY5c%?;KmZ5s4<%b`jw!e99js~V4YmjUKUVusDyXz2(dzFx9tn1k1MPy;D>v0Q_vrl zn8zi8%^53uI-io?3`P?xEDV#S``ze9h=S*lp&Eyw&?@krR)%*TL;2ZTE{s{;f=|pb zQ=;sfck)7DE{V11k#PEx+rEt%xq}2p^7}96_4|4Vwi5o&KJ?3>j<3H5f-*HV6l_4* z1p3q9XJ4k_3o<*pN!w&cI69zN6{;FyXpbPdS0lM`{JK!dGGM;bNj zwjge~p`wL*ldtK&MNAstFb_rsK10&Cp9wUO7lCq6+!V?ej1F_tj0o^p4rhwPAARDZ zCU6-Ek3KZ32lD*21=;h~eSNlmJNm#S-tkS2RKXUw0L)mqlsjP5YnMd({r1nVbamM(;pdS%41X!?)AkbKKf1RMxnW9p8xI*P z)E$Tp`25(G7=kUecwXDVzV|zj7bnYbGv9j^k@JP> z(VE|L!A-8mj}XuJhk(Dv=gsZIqAuo^f?W+`&&0fM-@ou4`5Zb`xgNcY-WAdYybFkT zTIn6y@;!H2mhX~8_Xzi(vQOI9+wxr1()jDtx8Y4+mK{!**vOn9^fRS2lQ)mguIu)1 zSz2O{-9a3j(HM?(R&G=BLRSZHJsl*E250N_+#IFt2R@O^iUjRZY}i9sVNyn${#C^hh^lMuH_lI6Bbp* zejE}Vkjxmk8O+;j3*T+z!%tzqz59fZqFj#9fM*6s3|>3W2~%bSrGl>Z3|EBM;fS@+yvEriVK6G21G zxmQa)wxbz>>5_>eN_2`cam2S_K0&?H}JTc)=>`9|s=)0M1(_|*hfyzxLKE}Un4GxJK3jXu!!}A8K zYQ_$T>+`K4o|K}sDpHG`)uZO?KV+(tISg0DmR^pzRTSR&R7#onzneNC{u+nz#6GXX z0TH-(JwUT|Q$_s?h>nAU!$1?tK=tk*m6Y`Sm#CT|izw z!(guAoG|h5)-8HNc}5zWDuX2L)(~C=5JMnRmQPvf+@X#A*7yxImqbj~#?Lh=QXvaj zYP1)hfCJsdgRvM}e9o#Xkzl}dL*Sm0?8vwh5P@7*EY}&jAy;6t$mZWF%_)I3Jcvs~ z4T7mQxBCb;Na{(|YLbWUm+Kr$=VWu5Qw`a89E)>&3eDsGa9@H3Y!OtinAk96vvQC; zvs#?MXyGN}@qtqZh}WF72`XM>5tQKg7eEjg*f3hd%b>h%U%pOu@bs=G1tqS}xrETQ zWAr&SP80g>`H)ZVTB|OYu3_SPO+PB>g;$=xLpFfEA0$Bl1@kCLm;xSh0;t{{>>ZRpXf(i5`zJAp(26DMWcy@;k#@jYiwUK(d`=*U?z?W9) zKtXi#`+k4>oqjJbFWY652|G$^PG>pwCtHY< zfDX!gRpU4u?aOZy%P~;>YCml(#Q%oMY*4v(gG&=sOhmHgrpePTr8@dPjIoXg`QOluOvfrSXeXUMwx%4OI%m|pHRH7#STOl62LM~z< z0!l&Cg$4R}Pw&JlK5TX(#H--qJG{=L9JK0U5Gczj`ig5 z%+tZGn$>k&H{QN7(gd3|MufJ)^`uA zn;I&O7qtq9)8E6KVq`9}tp`>5Fav_S9cm%e4_k1-5gkep_X4qrPqO`<20a3342Q@Y z4%9k%f35fa%k3Lk;!KMlZ@pPqTRc9PtpHvh?fwJWoeoa?n|L+Hl?iVDpQVBx@7Uim z=|q1{+_o_280z!b-ibfeu~hqbP1;WG7;J}L)US$8F8OwFsAq$2?|FUN2g^jaf}!|> z#H9lV8J|E)K(vd*@DA>gHm_(-dauDVYagQ5rHWz>DM0V;CReoc&Bq0_f|Cy^(@Y^6 z`h*+g=>mD|BCjOA3|F~1UtGri)kdn}=O?z;-dEPHxiWz77`EEJY=SBT#`jqC{)`cw z6PyM=Uot$&!t1(Kgb1IcAp!mKZYII|pWKW0#glSwzZBB>`D=~c|EPK;Y~}~J9^45| zfHw-KcJRB~^W$sELZqRpfdU_5(F0QJirBNnOTH1xW%V5;DHg?|Mz3zF`h@W?d;c;vA|@=L-2+eEs0Marx~60TVBU3_JO~&5?-;LQv{+3)PgDh_0-K zo5ZKbsV#=%^=|&ohi5RC+>lhIPtzrbBNp=OV3rPnt-lo1Fm?|VQ=>@l_i=tnX36ha z7OV1r5dkMUWAva5GPm*;<%nj8g-`;go_WMWNGgg=L))OmLH)kSnYm>NCbP~=rdenO%jx?jHgUuqAX|R!!@hO%FF{Nm}6{aP*$;_$M17F#35O=uAX`ErVw?hi=3+_=xr9!?i^cZm1^fBQH-(OaU5Y%^IB*$SI zbdrn;(6XUxo<~~ql4mR?8c2TM8GT9@dS4_iX{KMGAP3GEdVq|(8@CB=qvZ#V6CG>~ z;?;3J?Q7|_s6=$&j1N!9uM%eYk2~W*L&ESiNKRi!Nv{!Ju(M?*`9Og1;N{KF%?6-T zVuLUUD`C0j(*=pO7bAUrKHVV=4Z#)dN22THUT-zArqzjbAwtsmQpv)aTMjJL#wfD8BgCPj*O==W}bi zNj|-&z|imt5rlBR9G+mz7w^baq&B`!6DYn_{^`S7(cZct8tB2!ptbuAF0Q0?LgLv# zOz?)=jJI>0WqK(_h81glT9ikYs-pq5jou}FG_vm?iB}dUe`H7<$GQ<{o3*1R6XN5Km%MQ^$w{n^DLO+jiFM+`vCE@9D29Em|2~tTG8w__TA6rY-N_a2J+| z53`Kx;gm0Kb-Z!^@<&bsPNY$?jQAuBq?WLn7g8s^rh`gjDQ}9K$NVmeMig>j!jE>C z^hUCV#UpUMt$^}_a0R~e`&-wO@x@HXqv%3l%8xib6-L(XQDz+S`@E$(-k#co0ZSzj>;g`f-UjT>_-s6uDcg;ilhnI@ z^Z@?M$;}$8-(Di5wdegy!a-}ZhX;ujXgCjShLx8W7ndjxp$l;_9d~TW$vSx$Q_bFd z(RZG)yg#<>ekGpzq$KV;{8FP0f@#w_WM z1NI(6l7{qDNx`|D3OP);aq&rLUh0*liQH|Z3u>-u;iP=x7@Q2}Jsx@-5*YfKm9^>A z5cD=@2a$JJX6^laJKQ-;jyTX}1x)J=ayR6_|u8OdfVwq3(h>Q zM=AkA50$Nf(CYh^6uOUV{_bOV!SnKzxFdDHzbwHwy2L+XrrMLtgFm=CjdUXE9UksW zEiT`um8}ql?w`+$LIBW(?n>G`*lt>0bpN*3jqXF+rG+28C-$Brg3WS*dh9v9jdVGd zCs4eg)Si<(LkfsP?P00y=WLmNH!tQQCcerS)OCql8iIJoK16Lz@*k;q2*dHZpBYp;pWn2Wrn9(taCK8jU~)(HM#rPD%L=+x{^#(O*JvZ-r6Yh{_(VhS%HUo|_V z3%(07wS#SBo~WRBK#QHXV8Is?S0oBXrL*=$U6SwdIu19QMc$P#)K8PJ(`k&9>!( zU-bP^9_T?64iR&YEgeDc;>ntEhgKTG=M})`$99oo%_fCsOF%{Gul?P7d;bJ53udC`I>`-Y~Gf9$B1zq>Lc(IxLwc<@gI`LZzjP2FFrY~jCD;AoZ1z-u$K zfiL}{p!d}3YJmX)KrExyFWAebORgTOySl)o`>DJ5zf?!P(1V2k`F}=)yVb!Hcyx5s z@y<=Db*rZ{TVJmi7#FvG_IWZVpSUVx@kIM1j)F8?uxkw+{A`EYi93QQG*1RnPSJ3_v1Iw_9t4F!<5fE}<>L$WdVK$x-&=6A2d*xqN4`Y=V3kmoIe zSBAHf_@_Ewe*l1GvobngpG4^}JG?qG`zaT0lFc-s%Us&S!ndIwCqH2#kq6Ai^H^NHG0FrC1s?~T+osa}Pc)KA~S9}Bcu&v}TG6|Zq$Pgdb5NzU&J1g? z{#4D-SbOCV;`UF1B6il%BI#+E&7-Rn`{U(eJ>d@IPf%^zW3V9hs)zNKR4X(ritn)8 z2xUjB3Yg!VR){L#m%bF{uyVb5z{4aw?xv3Ti$EO}`V5Sc6gJcVSHrz|k z)8H)EkqGSY_6}n<#IfL@y;y@^(TdZ>DZRb+M6pEMnMtHhtVfP(*Dgaj-TkdDS{89rRa(C{oDKAK`82n%l&Bqc$en-E%U<lIK+0e>0tJDVQ|>|)^EuKOY1m}s#Q zEOZ3>`k0TWD+IY;vRYYTNor|kfMTaHg>4mKwldTC6M3Udj!3a}i~a$7>EH45Ri)vy z1QSFW4jf%AC<3L=LfgsgGSE{D45cWj=%A?ac(aj2DZ&;1>|TSORcWMhl*y-e00)sZ zuJMoH3yQPY>+$L!zD~d`F=Z8Z)_6EeT`%{;B9mCngiD`Pt0^0O*SNnG5u7<~#e#H^ zq$R+YBvF!K@LJzc*{zQ@^vlzrB*Vkh`-*&#e0dQB@TLyUMqKAq>mbF-FF2O`JC&DR zRT#vwKq^jx;$Qr%zwk_}BiZg{o7pNH^t3n%S@+P!#WR(WexQxPju!wwXb%7Yb)iH% zk*6$&GQ4sLwtsATT@K6Jl?DN`OP_Dh@XrFI84p+O<<8;q{Ed>am6vORs~XN3XoUkg zCll*r+)iN;@|ZHuoOfnY_zISZ`?G<{27qLKz6Tku>P_PC3!i%*Mhg9N+Lw{Hb|8!m zAI)n@MKi<)NAMNrlyiNQ4ie9n zVt%}Pmd(j%l05Ds{a#r6%=Upt$^%ySoF#O%LIl)-^nANVo0L!kWcJ(WnOmE2`r^NK zTZ;b^FUMNKO!go8ys7CuU+k}LG!29iOhb5uyNtJ5a3nAI`o-N#UJC5JPa1-F*mE1| zY1tqBu6SFpwMVg}Bi+Xe5}9H6SJ?I3JOa#!JcZ+y>SpbF?33$5SN8rP-N4&~O3vLu z*uk6D=ae@;iH=&2u!fD6q}3GP-(8v$zYlYBuEi+FeFC>so*5LXZ@DwGsi-ad1hzP3+}i6%3Qpv5^o1?-gjgI8J)&9xpI*}`Q8pi5cM z>&-zJ^JXX9@Ul&8y2)_-6H?-$6JSa--_YKoBO~ zs4(2jirknzBL(zS0e?uGlTSc;@G+jRW++nYYQT z6CdP^;c8WSFtl#2^M}N{ed;ey+BwfEtxbPT5Qk-oeiHhkYsZu$@Gl9EDCq*WICd2D zl7$N!;Fj`Dsm7YRmPD&4kG}A(w>lJ%EH2{FZx%`oyW6t_nA7S4GD&~~%eMoJ=T!4s zc6aj+pH=GfryVI=-@k!ik$r~U#H`t+2Fedl=zA`ibpV6^Qe6W3QjUnQ$4bt%ht3K{ zAW`jcka9woZmRDY40P&xXorbtgE51xDQPfT#RQkhgBlx#E<5*NR?b8R^A6o2rA+RL zZjXdrd#razn2;o8Q>#<<(PtzjnEo>xfR3oNgp3+T`)PGS*el~Z4sRj^5*2MHpEz== z-?jpHwcVW#CP3!?QsLK0KgCra_&uHr0=C&+l|K+z>)4eRZ#sCYMmhswKhmC7TB39| z=w*X}Z zY6!`4^WCYiMQ*b%!~lYk0;(c}Vzk_eP}P9FKt{^tDt4UV4nM&)=LGC!TwYU$3a@e<++nfGoU(KYWu8#|L-jsW3{w|`RX z@XR(-fxjHf%i;9LqLBsZM=$*4$p<8R$8(P*5z>LnoUoFWH?BK6S&N2|kV5IX`qN=; z@GHb;q`I2n>tMa9jj>}oQ-8>y?`zF12^PA9)J~y=-@O%+&`|gMBf+qfRe-|Swk2u2b&We?zv!W`GL^FVoR9zVL zdc|x;zmkeHt&Ma)uf|u#j*vO2&&1M##6Rb%TZJ>{UQsvlB|}eHfEYt(sEG0os+BdQXYu9~kqci@Rr||XyePFu{qEg6#5RH&E@c>R zmvVu3Bo!Ustlqhr4yxQ9x%bvFTK%-uHYdVsoX~P6?%h39+Q|A!QCv`nBKUhZr;RxxI~3H$2!3z(|42&0FdHO7P2zV?&f+ zUOHWtyUku*98$nNhv+FGLbA?O^UJIZyXi$pJ@G!_64rA`Nwf9F=slaKPw!_KrJklr zpJ(lj`_@2g2@Du%%BQe}%fNh4cr(`11#nHA+nQJzj*C)*7yl4lRIMtvd-Q6&0EwVf zxwA(rMCdR53HVi@vkKek)8>)&w`DaP-+jW(f3=^|O~3z3wP}pJ0|u=C=YRFg33dWP zEREsVP(PPVJDY7Yy)`Z2i#+1O&v&`SgSx?InLCVztxU4wC8Lzl^dCrZP$F8t?$>zE z9NW~5rAq;jJt}hYEch{LBW5yc=(la1ZZE(+D#rXK`pkkoW))Q|g?hd+Rv%}l1?#rF zo{uT!H(!}_&#!&+>WgwW9}wZ>in!U?NlKLbO{~UBb|HZH4^@*$N90^gXPr)-hPT+9 zN3lC&ittiG6+{0tc8f?PQxc5nN%@p7x>FnQ*PFP&e1iS6#tYk;66>3M222T=9{Zj9 zu!B3@?}@{~#Re0wUwX!FU_*jNz6-h*55tak-!YlWU)o|@oFD4?rY+A4?%o zqOU@36WJQS_+8PlaxOf(b*PXbG5pV-<(9qM1A0U6jPSxWXeaP9gr87K$pyXAer_{0 zDUMzn+Gt~^0vCx_w>@UA(RQf{KWKkXc5E&iyg zIeGj}p<}v5;}6Uf)&s0_>K4B~hU##q#=t}0Tv*o`p-jr@wf-zj)N@pf1%CTplfq?X zA1R)zojWY}IxhFjw0hcT`>?3aHs3b(7#7atG3{aRpgf=Xuq;T21#Ru!_F5>rXxJ?X zq#Zj(%>U~DiDL#6QB={}G|#|8?t*hR+aS;c)g2UoPWjb)4~_2hv^%r>?^kcPaC*bi ze^oAT(7*fYk{`(Hj$7<+2i71?L#v^)I~~*V3aP1ii)eih?6+JLWw_fJHUy>FAxjV$ znrjG6Soo4j%h&V#?1Z=QIp0x~Rz_2~!|@AX%VKDvB|w~8;F*S*si=-QNtpn}I$;1E zNa1GDydIYCRQqTtdrE~_5v+V|2}Gb!W85lY=5F=Px$MZ7Pql)b`rqQi&KL^i#O>4< z5y8c}QeRCwA{g4V31AR3%t_PIk(wlSWEkk4U${O(&?y^vh-IhS*RmGjU1Olo1Kt5+$Zjg~1* z%H7t)wpBAX*{Bm{_l^z!<%*QWu_es#S8BO+JICA7fUvn56YEf9>r)Vzg@i3B>TN-AKbD%Stz39pRx;d8q~FmXG7mq)~<_M z0#RGt-#T*VyU?^y6jz2@Pj6jAw!^~a0HNi_fv)!)_-hjACio-Ne;&%8%(`kwwNi-zWaxwPtXWhUSBw$Ai(!TvSDO0Pc?(kwRDP66}*AlGe=ATF0%Qbbc6h5vuU7-# zx5TWquFDNw>f zwtJ3~W!vRcU2x|v3xn40DloK{+PzJQD2#76>@K%R%cjRVQCi=lVTDf6jjdMB#MNsF zy9oPeEzpx~1!GF2Sz$2I9a`uDk;6`=w0z8M2-NYss}n2GxbhBP=4AInvDnerd3;Sv zef=4~VbmJxlSq-ZNZ2OTp84aAaAnSA-&!c!TeinLGr$a2{Jh`(RVJwamGJfzgjQW` zVUEb{uR&>Jaj%y-^kXaerxN2}S5SADvgF-f)$vYlIAfib?oDTOp|Pbz<&V<7{^;2e zIQ-&5-hH@rF5m3ip_HQhonMAdh1LrT`j^|8#MrPx+Bs2|H6vT7Xb(S|mp_P$z*geR zE1a*x?CErqg#sVB1r~OSt|!i&vwJlPw7DG8Sp)HL!(TOV_l87Ret=On*SI?w=hfw} zr*Woo^cI2bzWd4aoEyG{GlCTg2_<6^uk|iIWTJvz{QLu?se5F8>Q#ToJinihtBse6 zV23R@TtCG`gnU5L+1d20^{Zsk{E`mvMC~E5BAXxMt~{MC&uPY8k8&#c)3&T#&=jn= z8a18s1XD>cldZgMQ1$5H*&8nUvT8Z6cZb#SR$eP|L#_}yEHv6vmZa6q3#gtvIF2|H zEBCl-A@KRANoZGrX4zz1$;GHp&Z7qu_|ds^%NGKe+I>B-D|x+lulxt|)0G7d_X@eu z*4tnv>`*B~q%shDr2cba55?C214RS`hWrXSFfDoDUn5;2Q#>%Ve}4Fv>P5Ybbwg6@ zmH6OFz<@Neuj|8>&4i0+UXVO53x?kOZNjl~r3b+o|EYP8qXM4(KnJgQH+yn&s9_g8 zr6EgdBp=C^?R&}=L&lv&@8NkMHEo1W44`e8cl+T^wj|->kL|f=BHGziBVG#_xFN(2 zT}kgVG@IB#t$p>1)6H3!-5$4`YcF_fT3q0acex)uwUC{{cK(f{QUw<>D1&*WJYsCIx)Mc>N*kg?u%16zxMpcw(!P)zLz`j{ z_B^N$muOz%z?T5jxZ zA{PYcXx#1rL{XlHYXO>MWoOa-&i&%Sq*1Zq~yl6Zd-K z&AUV9=#`eK!l4la=)x3qQMA72E;&*@`G^&2TQvgKd))|%m8DhjnYksh*v@?c$>@9? z?*-!^(-M9CX~3mcoVqjKBI){C)0$Il)|Lv zSsa7)ElPBWQ|A`+t15oWP4I}6x&%VitR-JH>H=1%8#Oh{@y5hiOyDV8Q-39fHh)?| ze!g~E@hZLOFuBK{CFk-HvGkG2uU~?q75bPQ-%4N-OVN z%x}-2Mz%~DopHUVi5!Xd{!+z6+;9|Dgs$)}N9<+D)()&UE+30su@9njK$zsEu7ndnH0ucsv>dAWF3||yZ zc+i!K>KLk`AzJQGR9V)m{ZFGlg)+@7VrF>Dt z@uVh@=j$uY^pRq=v_MgCw3bS@75pjEdAY^hr2M|k5B(6I;b)}nsjQDd&!d*#E(lBe zi6`7n`h<)2Y3=9hSKob)(^{&jc13NZW7LfC2?4hS z5P!&$m$J;M$t%qMK4B}o2qAu_kMVkf6Hf`lnG?-51AU8-94XIU(Dfw}SHV(v-D=egSIue^QPvs^w|J(Z7K zu_-|Yk2=2O*yn*MvS#j-vhTgR;~}*fM2pRr->iep?q|XZs45H*IijWT;f9R$?g_{% z4TH7+qqYNf&Zxf)Nb(Bo^R6H{H+Sla#@gTw#8k_G^ma>6FN zwALiM+}az!{+NW)H{i`w&ybuXjw69&7zyt>E^5ti(X4X)lty$!=KrW#2Bv`KK$KA- zsZy3jJb5#TY6YJ=(gm*U)JP!y1J4~B;m1x}@FrAHfk*2p)b zFW^h5vD9%yYWFhzcc<*m{0Y`+^xDawyMZsGkKdU%DOx^D|Dy9Y;Dq&n`@gL&vPQ<{ z-6oisCNx~01FgP|nh!SXGO~3&0s`H5UIudstkBv~6O>SJtWg&9nP;q}L}J|> z>jcy_LO*-)5_igA-?#6ttCD*b&Q8rF>PCnms)JGnT^HOyeTywT6#K%483nkm{7Ni6 zz)yX-Hq1#V9tA#Q(nSiVi2tRMU)}iNd30H6dIVZ!7DIHzDc}P}RPXuWmuy|mW9ytZ z!frUkbH@JjrOB)kvDLT#d$0GXIX!sv3 zD8H{fC*doC;n5A!X1>al0O5h|J-JgZ(^drn*CXfy)H#UnyOd7S@gM)<*MunSGqJ>= z5QA8}(Ji>bc>21nxI^iJ`yab`&e&soNG{KFI@3q@4Z`h2d2x{Dzg zvl5QhZ$&FzHNg9>_%?kgE?%C}a+Uw>U;d`9NTbNFV#$Rz#;P=MDiC7jq6crQu*^d; zt6tN2I~o&+gQa>V2zeg^Ny*NjZsoYrfkxG`@)W38d>S|ZImfAdvhY#J?#7_ho zCn%FhW(aj>l%#Cw&X+8j`6ftOQAD(bn9Jd|7u3yu^$)8)NR42&A{k~YRX6zqYs~bI z>=@kH;)mZi|4&~a9=Rdb+~kJ@IpxG{_)L1}koBjLoHP8!7ljJe6Ga%n(N9c3+0k{* zw=y08h!4}zWt9_EU#SRTs&uYa(YU#?q5hYuszuLv1r{tS+R2l=>;I_#$!d_d9UlYR zq42zSjZ<1YvRUpx`4!el|4+x<`tFZ?`&(jN3a1@$)@W-M`*jd!jBFjEe^E{0b3d|Li1KUl_v0hU6y2?-? z$3isjj@@NE-i zv)-a1>9Cm;`)@i{bF36PD%M5k&f8;m?T1S5rYH|;Io^Onx0j}x&ucX{MnkwG89?o3x>PR z;<;jjMwa<%TVaoJw37XTyn(HbK}y`_&pNqu+5n z4dVyAFJ@oAe$O!ORnm!~xZ`Bq8hu;$>Yu*7m;>m_>*UJy{9yG++33@dl7p(?x2cWkq za<}(p&U*62gYxPl4O&1-6esq%9UQn4R;WRPJh;e zGr>QTqDNsUG~L)_UR_n9@es|KpC>V(+E&7$*x5(%4F?Lb$7ut(OO#Iv2nu&JCLaeu zGACSdw3z6F)Lo-QC4ae2Ne=0+skCkjJlknr02?)ZNAQO|xQ$z_|ULGTqy zNa^@^6SV@co2vaw6cY=mQ2+=1Jna48C8aU<-w$w!RqFIpGDEH;! z&cJxr^rU6>&Z$EWjnIKpx}QSNwHnr|QG~QlIf_qo7W}hhMa&983)!Kks!CYaxSqsw z@UG^=zFfdinl}#6HfnvtWGn5BLEhwty={H*P|Kl;SbqoM1vT`WKr|DU_Q zZ(gXLdeo#YGjI_gV<3r*=MwpipA;)fyZs`E%WEVa}Gl4}o1o5J* zWc)Shon^DI*Dvsm_P=}LN+v#2m(% zmkYym{io7JYll;lsitL#mTe=^)~S%ZA%wHiQB^MifqC%MSvJiia#e($P6cw8U>THg zeD;H3J2!d>9zzf*|5JOG{M;mU-T}6Pyfi1A{-QJUeX=M~oe;DdWgnF%@y{irlkyot z;ipi^H$8^s0>Ic0aK>hyJ5tr-aVTmfV{vyvAWD^C`a#_5N-67q6pDn~h_0K`6)X=q z8nb&l&@%DfT`DTM3d%YaTPbtii?wk4U`!&_<>qzC=yWDcUj3V)%9o9Wfhi(KASP_R zOKq$~%d-m8Or{OT*;YORjlhM~lRoaCarVJ8Q&iRp;HHfgZNGy#9|Y+4*__PU&cO0c zev~I6%elv*s=RcCGDvhDbXBSO-jcnn#_VSB71jiIsSxavq}J#AKF+UdcMbmu2$##| z>jqy_Dz_r`FnH9Ma6X6LA*fn?vnLPv#Kxu=j1>>!_%Ly?(d##FRdHXvnK{Mb$?{Mx z<7?`&`$?v;NyDIx;4&~w(mp}F8XvD(euJCAa=4xlhAp3IR#k6;H{Xvnh!XAWA>P>O^mtJ-y}!SwpS7eR zP}?9HZrDFMUVexv z?(}kNs;bmMt#g~r1FJOhrWP+xI(%7I{HQbFG->j}EdLW>$Yma2GHR#${=eNSd-Frp&i~5DcVxq?1(4wquoM<~!?Qzpki-15@PQJcIs#T~F*OzL=ok>r092~9U9<^gOk?&Ad^?9Sgp2&!jeh#ECJ%L0Uqb{cj?D683z>YVC z3o8v5cWEvBoeISoz&^=4n$F5mxP+ejd%?jf5MMjpbNi*bJ$7v1%3w9tkJiLNVA$Sy}uv?0j;{ zMjy@sK9EGu5)DR>ZYH!W?Lsg*iyeWB8CmI1y@ zLMU_L2s=_U&I)(b2?31W?>#J~uQhRdTmxa3kuH7pwCr)eOWquph(1V_v>79Tlo%~1 zSv>sEQOKoSG=pr5hr1x=H1s0_YrE6w!Ic|~!7Cea^1s(q(5%PMHsG9K8=S(3t2ptb ze{$|f{<@i3Yj*8c0zdryKgPt(89vp?<7PFCse(u!B|*AT_{Uet<2k1 zumtbYM$Ug0a|8{g{oYFW<89@|5PEXBo4lSqpYEm8CqFCmBV0nHP(+2irQE=#{Oi`y z@bhGWdJXHag{^b5qe7Y0%B|EZxhMCqr^lp7glf!ZxfP)#V_d;c&KNcnpBv zT~)}>66Na36_qWft7sM*=5=_nUIV|n^3Fo#)_ER+vl=mJ=X6vlQ=atIbL3*9+hGtJ zxNpI}6|gG>eVg6}M92+_b}il+2kYfMt78lJD)q;z zukc>(m&-RQzTvKPHiPKKbEELhxTKm3+2?@U>2JrvF_Rrf!_U%DxQIBTb_jRNw1@bj z-`;C!>F@owTRxpspx)J6tVpq7|KQi1d1E*BZ8tjYt^qw-6F0Z>`t;Y=P0p0`}0E z$n}Y;n#fab#WjgYoawzr@Nk1d8^b&U<<49uF$c8U0VYEU%kGN4P^af`nLG#4FF{6x z&o49}iA2W9HuJLcVvGHd82Gd97e%Kc45ZThuEWJ4e{g3)Q@g-SG*@`$W zn}`l6yB*6ETOsMLOG#lB!%YMS&TFIic{FLA8*t@jx84Kpe6|`XlYOXF; zSJPYr0ru&ELR*$Zt?}$j6t){PSd9{l4F-*V42{qp?aY{juVv2^Q8Q_se)hzW*~oVY zf&XfjzufdJKR5=OiYOb|ezlUh59g97lo?7E&wU?U2$x4|7!GHN6eaE_u zyE|?^+74R5YAtUBL*)Hb(Wq>ig!Ic~{Vpb)Ty<$IY6W)&!ifjo9j0MPNT8gdE5N=T zM~g7G>-TMsdE$S+W?570JQ{rWptR%yNUq<&J zx7+<1jJ-dVBPi8d>9ozr)(i{7AC6OGr%aNa$jC+3X6$s7!?&lU_mp&A-mqZoXjE0a zs5yr)chHRW@;){XEqQrTUadA1fHPO-;)Q z?02bSxS{lWlgEWIf2mw0!_f>7hB=~fI_aZQkOO1>ywz>TtZ7cbt~*)mxI#}F>noLG z8zx|&W9-wowatS2Fz3Eyzvg)p+OAVms$z(ejBLHyFjgIBGQE2Wf5>ZPzkW7p(nEPU z&>w^l5bk=Cd&!KpKrmi5<$?MagHQKcfiN%yF*GH`xv(~1R9n&o8KO)i!kKW|^5Ken z2yci4E;%*ygHlVN(KT_m6=|hQ*=)!M?XPS_8J`CS^yZ&tac@1C2g-oeF8sin4S^Lb z1Q2F#ttU*jj#gkd@eMU;V+TC1>Yoy7`eiSCErU}@Gra{et+ zPp0ukxRk7wCU%^-K+o;|j47-J3RNH=XAvFEjR$@3rfYCH6rS#Omc1A2l0 zbAKpSzPAb2abVh_;WdGw@fzm4?+A0w4ytS>2u)5HAb5 z%}=G%59@?9Aoj15*XZDDm%x_;&3%5lXyH~N~<&FJE=Y@CnNGZA68t61^^q?nq}xE!h;=C?0Re)=-uxN6PXEIk1h%H ziJ+SOzRKF237iv!JZY|*=T_R4uZDvzc+(v!alr`orJIizrn=)wbBh4 zWwABQcp3()d7KKj+;i6npd>SyM*O==?0Hy3n4DFM^lYWdgw(!v5+5Rn1zjuH!37FV zg|kXaq>_C^!JySx>=8>C57b0FQpX`&8WNS=)=bE&_nR~pw9LE67m z+Z7v`a-7Se9qED9Fw>7JL$13Jx9z`FwOZW>-QgEFWCZx~X*T_6KCMbu+SS<4Q>{w` zDV#zlkW-b{8O^9H#jNJ(H_Y65@49w=Y}iL&98?g=|fMWo{kkk zi&kjDky8(H9{7wPfVUbAV|=ZW@@&)H8oiC z`L(mjx-C=<%U3qIupvr~kl6uIa{_Zaqe}ih_@95NDkR%FVN3G|cA|bD{2H$Id&kPM zXQ;&S0)x>PF7YS)?q81Ey#JWaf+A$HnVNBO{vv{J3nvkjBbDCoYr4S<=`NNbwpnEb zPCw@t(Ruo0jsHb{#OwM&--oNga4GbG-JoK#>nkrgA>&1fo|@;*r3LTMj9?EqgR%@T zO3*Z2iC@A1Bsu=sE;}8tm$4kf1CeAQKEVo*kYOJ!uA0_a>E?lB-*={yTt5@6F6<;L zEI<0&j@m44q(yce>hlMtb`8&k=wk2BZ_TkK%jf!*&hu~cc{VXqY5Gh9uvYkj)}~2b z0Ee^S^Xis+Oga;*x8hxQ9x4Nj7=r!MlY{ogb{cxkIQw>Mfp1jl^<06$?oK~j^)=@V zZ53avzG{N7Zcmbsoo4g-4K)>) zgA+U^eg28cTrxfp`ttvWOVEGyS}7jE>DNaj(mvf|SDsFTnRWhdwE7p%C{`Y(B?*4< zI;qer{7m5`Mts+M_oL_#6EBh|495RlqvFlm@wq@TR`>?r$qtB7n zhkC8~&zHkVx+@ze#L{zdf(rHu3UJdMk*E+AYvu<%c#QOaTFpKS7aDse?5SGnW81b zELRU@6nykx>KHA?(0H{F-d8O^N>EmRzbAmIafsD2HbX(am7G_X>ApSDg9WF51u`Uc zOgR@U*r*L>_HCO}bjGT*1a%{ufpLr3I#|^GK9^s*^gF`6AkjB01LAc_ zHkD*flAY1h$820Z+>)$)6bq_JY|oNsICWI3zz%I;_q%!by%jt8^`&zyrb7tQCub7| zA1FnI2^t0hq&MMML(f@Xi^==rdCim6$@Q-|>YIL%`t~37fAx8(f}fscUYK!7VQXBB zq723h(Orq1ULNhsDe{|36_!(9%l&3mowZmECl(8om=I0b&Tadz^YP&aHYyA)iKigD zsz7ZBo6FIIE$Kq9E1B3DoM2Z`xtt^gH(^X4n=C)z8#%D$P(vLoa8F~Q03(w}wZWcc z(Bs^*;fH1whGeHztzD%H9WaoTEz#^H7zY9LuFS)4&(3SuUsk`>%RHZEK^&HqG7j45 z69$UA5FcQtyU^@lV;pQx7-M%6+R=nvgt-4;u7g88Mfrn7DSEYE;|N(e4OokiRbZh7T@Jj7*h_%B>elXt zYu?P(`ZoI~aE~{670M_VC<-MA4TskpT%N6s@G9PZ{IssNUAZO6MkMBofe(o=WJM}? zfD|o`Mp!8g6dMy*A0Wo2G!C8FAbqw&dmk<$`kU&eO3Pvgvk>v3#N$jenablARx^oQ zfu@-?gL!6BePKKg{@MP$pvhsjLcL49RIlue<64G?Hm_HWNy-+x7aE`0^}2q~(JJIN zJ4RC3Z@<7~4&~XL`CFbebVtQ)w*&nB$U93;yZ5lshew!&A6x0`Rq{{cr0N@y^#+Fr zN4|{Q{{2vzjSEz(J1GQ0OE^>lvXVz^WulHRfNb-91LXqjOGeg0DMW#?1qc)PG!*eBYe+SGFGuE@n3xiDbIb|G-U zY#9?}k=AxpXh6m}oXLFU_%z^dbW)d<}{ z9^qGsv*7+b5yKk`28)l9B+z$ndDYEd1o9Y$)0+rJl_UN8SplXAt47Z)1u9P%h)no? zb?invfE}z>Rbx>zTLY`q5qjaksD2B??GmtZ8tZjn%Z^+`2j&v7TZQP zUDz)9vNx`d>1HC$?nj>=omTWneRQ4fajJIJTQJUQdRxuSTB3fw4QWafOgj=%Joty1 z`+lkYmR&nSAm`+<8`%58Pg-zyayfFP?up(^irA+Fax(kfl@MEn3uUnD2-K-!##I}) zSVKQxD^@T)U*S^A@ys9nyGI=z0CdwM$)8lGAI5#u~w?fhIgK){u>k<8<9FhUBR zDrZ!^W7(|RamDqz!mZm6rAVUKzf@!zwGY3DyyN_-_qC?%P5MrFjSDL|SyrMJSfpGuXL!h%`HQMy z+soDhmx?iqhA{bwE;)seg{}15uO@A?D@=KunP2N()mRaDK0fx>uZ!nBHw)wt37WKQ*sChHzV}6~5)V#<2?PXZ-SLC0@k^ zG;?{!bOQMXM6X}coOs5(sODi;%{X8}g|~e|>8=%`yyRT5juy*uE{*7seHf1GP_@G$ z&57E1-q3|nU>`323&mZ(*?AxNwfOnut4A#`OUq7m92zr|@h|=pyCcq_J@CTXKQfwy z5&x9qlF!8*9CWs>3krBmI9YKAE=i<1e_S54bX*0%8xj3|>d@*EJl&I)~#avn|OBkTaSV`Ih0<78@^rQ_}9(j%84pmvx^6 zyVS4WaIu71DY#ueWE6a(Hk#q`wq}Rvo4{Uako$KtOtV#L*#qb2wQL?Qil1+j*cy2z zfWa&4;Nc5hYZYWDQA>H;9a=TSrwaSIjO2tmK*@Xcfxo=-H zHSik#=<4iE#s}xO+8Nn_Feuu2N5A?&kkf$%dTiaiRFGNJj0A5LASh6*W+=`di_&8r z;G6cPgEy*1@5pnlq_1*Ie|#D#&mIucqh|L5S_Qsi60xi1R=21#Ug2J&)hJ*Ray>=k z9eF4EJX>s_rQBxkAw$OLsF{shN}+VYiLDl;({Go0kVvPrtRI&-_yEo`nA^edjJN_c zy#y5@+0>?3Btbgo>&B3Y$|gEE9;aW`o;!UoEqdgKm|F$QlHy-s2#6GU%5X$}}JsejQD>|D|GAl>_S$Zsw7P&~y;C zg3`-YE!A^{v$yu{%Z7#A|*o}>gg-%MAvh9^Rfrb>?brI8%l-@lMYA8g3KYA)`%ZKU5dJqQam&CUPx{wx`pvx ztJ32aO0)ao^s1-8bp-iZFH0ZlG)&iDl9F!mtSpxF6!K;Qpx_~T<{6t=*bz5{p4-|C zV0oQuGGBS3(%Vlx0~J{Tt78V0x>KY#)4MdSlww7Tc{HF8UzQBTX-^iMSn&W@N3rO= zBpkF2LPhXE|8nXSu)W6Z|^C%9Qp& zu762yU_j*i`_e+ju@^-blO$4yiC{?oyHZLJgukuzUn+k1y1yKg`@91r0qoISOCiuX zl*YVC=h#D5A}}V&nySm?%<&C~VFDjM17S&I!Tk@~-aD$Px8D~;5l~tLDIz5*O$8|; zML?n=T|kP`iHg!fKza*AP^xsKH~ zGjsm~lC=qYZ=U^qK2@-H#_gMPK$d*TeYq>=5P`4F($Wk(25LO=EHi_CG&`9e0v7M! zPp*KIQ9$)f`<%O*@I^?7JwKY6;zwd3Kk!>OAVI{tpyw#^hP>7bS)X9m`}bh4-L>Q zpBuw*q8O5Gvf@}9WA!jHmq+0|(%G~B`YQ7Ar9TXln zQp6R&4Gus#Qj2I3i@{S6j`n*5v*oqiX=UDs1x~Av5L!(~>EGqjETF{uy0WWb@fgqy60e0-QsdmpV+rOUorPS) zR2bf}-jtIv7R@-D;EO<4dgaPeGv)W*A?tDgFRU2vbmn5d%XlxNCI3UPK334`KI~K- zoblqDA2zhmB(u<>7ri@IT>4vI_bK{u(2}>G7r4Yh`?T-p4AlgW}tKIq~Dwb ztYGIhYTMhWIk?1iJJ-y@nK01n@9V(jIhl)Gha9>IDrW`0PN5_#V#+5^z{n4;c;ENk zs_c!C>)G)5f_D#RzjMC&H$`5HISS+X=SsU|urCde3i7l|;M^ENGkZ9j%tgPCJ@7_z zc!En)w0fEpSJ2Tvblc@4fZ9j}Ib(J7x+Q!TP>Stn`d;hZaYDK=2m%InVAJUc};&Jfv{HJ#UGIS4$4-*TEV7 zkj3f+!x>NP5Rq}PTTOyMQqxbV2=MwGcRu!k{9l1LVbub+nTJ(Nbqd;Ub3)(!LFGm? z2T%LJdh1r#$vm-@Mi#-qLr0U-b!`a`jPN3@lVw2`p0ra5Iz zJ+`|36yHL66~|cxwKV_U9xVq1P6S8T*iWRyK%&6(?IvUe1bf_y1&euRX^C8Ho0_hg;eZ~8v!m7hw}I=^n#Rl z*n_4>tpi$$frna5C3@1+Lf&1Jw_4+RxK~1&)_c}O7 zsg(Z^>s8>^>Uf6hrH1mm|B?dz|Iasf5k+7MiJtWCYuEUy<%D(~X^hSPR^!Uo!et1* z3~iEQS8Ld)Cx8L<#|2lev95y&Qb^G}1q{+jf zhv^nkD=Jp~P5PC$LeDP_m$@e}A5vx~Awi$P%VgW{n@z*oDU+CpRaO1X? z1X1%3kWge-+;q@b4giK-`e^tcEy|}-D0peS9#D!lPSCxlF*}jnF7#q4k}ZBT@HQ3V zwtD0|Uh^+fi?(Ph+-Ae8O{5O3E^M8P=C`@kRb;nuSg zxwuwjM_q5Nt&1tIewHAQ+UqLcg2XK~Iqc}YA;54Bv6Op6&fDOp)7P6L%&e^VT^)>> zAtS7LQX?JTyg!2ycxlY~WcaL795_1dPK8#uf&wc)jodImfjyE2IM5vo*V+n=M^C3u z0hLj-LqQEaxM+j?*B`X?Uo&baT!dmB{6CXk%|f=B#2&rNf)c2L)pl zPa=rs&yc!w`O*|_#iNCkIzXEBTRVtXcf9i-x>4>D$a48oV`uyzu(Y)H|F&}6GQVzkYJX~st;6frB7t71dCDr8Xo7@!c?)Rm=zMfEn-Gg`x#oIJj8&mVqZqjqmu0^R@I0QSo zp>U=0gQvRNo8nmpqtSr_T;jgry@m0O2cAO51c?tWQyLZq(i zEH~s0hdUk@pO)BpyK1hq#Rrh8`=A7)r8!T`;(el64xp6fUWVyE+MVxA<+;tO$!DR^ zClZp*faMcklE42r6ZR+!P2rY1S`J-Ub^~MOAe8zbas5TKe&cs^;X^lo-g!)Ievv%_ z9Ot4=Vr+GxQP%&f(|ac`F$;Vfwo49O);3uI6{sT_9B0}|m)&~vfFNZgy&^>Mv%$O%tjEpUij+T4+vy_(2>;mM{(!We z>W71<2h5qr$Qd^pvpo3)LWlZU_2x2^%dcwOXslh!ukipQmEm-yS7^$|arXSm+XsBB zv2=dxasOf^A&s<;D{Qa_5qQ?8QpqJYRw3-k#qjHV7P1F(Epu28!w#QCMc|`_)8>ko z8$aSDMtC-a4Tw(dwPcOL4@S-$=?2(&pA$!I$W0CWJ2if4#@|>yC}|z1RI%`*9Ff%D znZ0dmsCGyd_G8fmB!Nl$gC>(jalm zSU~)C$QRM@9DI=8aFT_q)U}uhk4}GQL%P%5svlrtT)_AKW#n=Jq#k%u&0v;`GFG4; z;u%n1e9P6H+&xt#lri*L!tVT(7Kdj7(|7?e;rY^>8lUe#)rO~-Y|Y;ix>L#*!!4+$ zdyWDy8!^~Xo8)z3l#MqmD-vUBd-F5+g$f>1p22--%viFk`FFVd1+O6?&*7=j9#t|SVqfsWPl7ZOig?#1PRf^Hay8Am?7t`@jO#bjTO&0 z)^l=SRZDkU&-^BrMq{2NJ4%*|Q$&^M$q#{zc~p+VSR)0Y0bcU%6p)P|3Z#lY46 zg_#vspZ*M!_oE^7o45X7x&kDUiCuFzHk-)d+w-(ff+Wy!rfvCw+PQCDG7(V&pz-L% zXa^0+dn1;6;ol&Y&VVViLG5*Matx5i3L(Gtv+8~u{0q$PjgD_xG<)amxUBOU`{eD@`t= z=c>ODEaY|H_8maK9J1CHjEWqMi4gkRlC;zBC>=5c8{cZ$E6_4}=RPt08AX2_`JFxO z&VA?)vSL@I%{Rl;LftsDT=a>FwT&*48P+P4>^#kDxtQbmD#ACFYhLpyC-Mr7iO9=s z$kJ24Wf~v>>7fN+H4mMEbl%`j2qQ|2HdMKi5q$O6LubU})VFh&f9s@Ev%mMO21vMp zQ-UL~<${`1EBX`p2ivZr_*5QfO47qnS=vwelXxL_YxkD*DS|wIQ44%un|Q<6Svl|1 z6tdQB=N?%a@pwY*Dy=`0TGUXm$xO(SNQ<)HPfxnu9J+FB?61Wj!p^^u+}23VMZN(= zDf{-p_GZnF@+Q8t63x<&Q>PSmliC*giy(JAIZw2&tCO3@?=w9y+v97BY?0izOwR=G zJ$u8Aw_9eCRk{w#Y@E;+g>e*#}_H0*@=f>UnV4kW`zh+>eBYPSh%$t$-_ zh7S5C+-^&`6u1c1bhP!q`?|iW-=mW0c;9$_alN^BvyFaj1NwIJIT4ns$m6>`uHh4YlRKU@ zMn-F#vBhsMYDz9rNRG*<)u|j&;h~v56|ovh8-X?)Zx2*%O(E+T^I=tfTD`{pdG?<= zN8s1jU&=1PpZ;Ozc`W{x{_V0^4Q&8iJN;3OZ3}=Y`p~hNF=i7>_Ij_C$3FR7ip zNqu&r*s`5{2HN7zEA;x={;ebc0P1*kJzsRL#dKqMlPo;z9Y6binK$h4f)^0%KRoiJ zBc_TZ!akfof7N--6#{pgiJr;%LL926*~&FuXgPI_&!q4(;o>=8ZQT0%Z6tBCgZ&>m zH-p*!_@h)pcqNg1FdGadEjjz zjL?2etfje0PbDpWd&FDph=1JGQ2waJ@QRc`|8pBX>KbtqBpW3U&a6pi(!opg#2)SL!kVdxK$^Hd%W@NDugR~f zHw~LsDSq@ZZHY@}ujg$E8GU0lz6!Qcm&XlhPzo>ym8%b^j8M{aq(M4lwu==E~}rhnkR*yO7MP*OqfUhWTx@9**r)h{_~9RQPl0>I$iR z=pQ;~l4{i-n!PGtQ)_Q!r1kS@xIk!s(y852YNFEe;AH0%p7Ra z%R!U9fjA+FnU)76&8?$Xz*8lJ@|5r!a-Jqm`Z_h(m8#EKpXRA?!>b998$Aq#sM$0# zJdRPZN2|N+(FAFOU?zk-PT$Q!`)@VKvaoGYw@r0MuI2YHl^XGADkQ!+{`QFD(|$i6 zMb9*a9P;HcpZ20tAz$#$09h_)bMbCdKV3FP@sE$E%^qfHRuLE9dqMgtfv2E#w7%~! zlG`n-m{rm2_vJmdgYDXneRhuf%GPsPwRMR|80~-pQ+!=J22o|h^s${uKft7}GRL@d}Zg^maq>2r$ z7$z1WR)}|`FD}l(QUmVCqN;;#B#Bz(H;Ud)5iDN^|5C((dJSg)BHUJDEcluh+q=nz z^S~VR`E^3x!nVI^@1M&I%=gRJONi{eOo?^`1Nif-*tEjkOCMH6rq#Dbg#0e)kiOuC zOuBQg`;gh|;Gz{}oeHB@JFf`s!7Xyzp1_zdhqBxdj((h6 z&Bm`MM2!8@?tOUgkRr2!sAdSSd_Qb6IgvkY`WUA|t~S|)zJoH>8_p;$FDxckY`%3? z9Q)xWuky<@G6eS+maF|hLX|d$u0tgav5iFI`h{f7?F+sj&!)PJ2!$=gE1MRqUmSQ>% zUye5z&pnqjQ!A|fdhxNr(9RgYD9qpelsI3%bWEZa0lh%=mi=7{^Mcr;*yb`Cb^wrP zxA(}(k4pvTwJGi+K2ERu;*V}tI8Pf6M`%A%cardf!+{xaLv;EeR z;ufa6wpHT&*hr)p$qQIa&84OWrhL;g_{Jqoyt>wR#Z56mcxA+!46JP-W6RYe+zgL5Nj)-KWSUEK80d=+Yeg5I1HNQ@>a;uh_aTK&Ue1{0l2-3WKtVM-74MCg2({F4T|Ics(3-c{J(yP*^e-G5yMp`(J}-^n zAeKK1m*yFH>snb|$?Ji=^%t~X4c4XB-6w(~TK+um>LqK-7aKeq_smV@$u}T_Wi}xI z_^@Mxrz(KXk*4wb$$u0iBNKH*YQthZxVFttR(3-tPglt|ND>+(I{<}JCH#(+%J{lb z%G|$IKd43>(~CcfDo!UZTBK`UmaI*abo1RD47;Flpp)IS6T1vJIJCMek)64G>2tPA zwQOk24YL8Wl|sMu?JPnYl*GSm^m*&)Ls2SbFG<_IybhlDI8@%AunFTu`y&Mpz-o1nx=95|R$BalvTJA*nB4DTj5JA{*9 zWwDq1?eD+LQRh4O$7;1Imx)Nvkh&}$@x$prNzL&zn|nhC?Y$ecV+RR?*dyOt1}6ty z=NDu@b7{UO{owVk_MtQJHkihIfuP!ZN3uy#@#4#GH3C98TWjCi1>^B8WoSg={K9Yo~Y4stIkO&P=F6 z?T(f%rvJ`Z;d}vC?PHFk4>U{mlQ?=vEeqz^Sb9ZB`&i$m$M^d{bl>cf?6FV0FRm5U zM2}|zX~rTXOHdZNrw|F@3y%sXXUL*tV3P#<j*>z+Cn%>^W1vBY==$JFT7?5RBbAa4lBG8+V_?8<8mA&7; zcl)LkM842zKE`*90PWhUvP3Q1Q90qb=ltlbGttGLJ-9YfU<$ex~e&*OgC9GAmdEm_=ODABNJfWdT`7??POL3U0E zAN5nY1NGV>S8pENdVQuhAU3bhBKY2)fVeP1)Ro~Qzqd__0_QPyht;W-I4UB?kQa_*_gCMq9eVITw(DalPKl_iWF-wg5iiA3BoT3QQlQ zPcr-ZizGAq-FAQPxK?!|?h;r&D3Po}VjRZ>H6|~&nWt*sJ!Fn6ufMk<2`Fz$@uJr2 zED>GL+mhf-OEn!z1-tQP)O?C4-taOBY(hYXOMj_roxWXAmsn-RQDID3j1 zIzs_u?R~_1)rTd$<@K(6Oi4XGxi1HHrkd+iPhNU_&j_^quCoNFy4T=?iYkBav#f}B zqd^ES0%IZJA3B@sor~{YwV2MoOffJ55XdiPJ)E>&C^&S(mY0Z(*=|6yY-sQ>{z8m% z9$icJHBhs!B)P@Oq)VRrmY#_iQoMm0D!*)6c<(;np?zhwAN`Rd3GN)lqW+TJg`=;< z-e(gQ@)Pa4^!};E-sF`xDa4v{{^Es*BmNIHC)*C`7+d=hOYV&^L`7O}t_)FYhhzD^ z?<0~EixZx9hSl>V%kYPmNmKNR9PW5qoviEk*izjNA1nMM&;m6UWBN%w`&mSj}T<>(BBHPKnz=zK{CS_b<13} zF)+%E+VSps9`1HqL%?J3_w{$}plXU1(LQH+kG0bQHSyZ?>F0!x6xXHglHb!a%7wrl zXK5y)hqw{&goA{(XfU5ToJk2Cpg1aZPb``6Euc(INoizT$0e>8^j zTAouv!$Ea)J4^M_JkohcKmjHh_*2DY@qU@li~R5Y`ok%uGwETI1vUPFNcvcqj<&T$ zGLiOLP=Deb|Fki6a^Ce>3Nz<@&CQ>`MyegDd8!Xr+*lE>35^W|e6Kv1^PvwzN_(D< z4xesw#cD+AlzbscMw(oF^cUKJP5VNA%sDGi!=-L=B3hccrK^y4VTcm*^BF zfO;SR@_8O{^Cck}bG&$6jbHKX+SD+;gjMY4T~SStVI`wZ-sSl@YYXc^C+|xSRV9tJ z=efP!C|wKreNjud_~Ezz$sP&e2=ABkdJUt@9D0Np2yun@`_hjxZ|>#xfn^Genx*4S z;xO_H!Q()t$zNm?O>`9SA}Fs72VGgH6j5|qeWItxQR_1^vi^)Z&bAti{WI0DlE*@! zLxzk}G}|(lbXy4XR=dkOV&>6hui^Sb`@e%`PxSC^+f?#Bzx>|Wk=S-wvictmr_+Ur zro=gGOKU*Smor$abP~YnUz&$Hr?L)t>!HcQ&&~&pG z$k&D;NpsYq@uMul$G9yKUJga-K2|;{=k$uE*}X<;8jYl8L%i@k8^-Uk_W+rUr7G{(GF1C-a?F;?@b{_WN(C0Cafi1ORxb@AG_AILm zh*U!fi7B|luM`TEO}0v&4z9ISC#)vM9@7K!8&L=!d$&3sGyO3pm^l5Qx3!)a-G!nt`lS^_G7o24g?d8x^fQc5Z65xTV3_ttMGtAA#vn)8z24U>QntYY6#xQb!7K3j# zp8iN~({a_Pe=izY{ROy$EOziBQVe|y+XO%>qYPlh=gdo@o%fW8ZE+twfE1LQjYY55D4L%TKTf?f(A5AAa|(c%H&|=xd*oD7(e>@}p$x zC&aZC!R!0dycN=gi;rGjiGIwpHfH<8V_lF7$kBgBD&oIaD(P7o1Pb;_invCZ&>#$D z;VaOru7@zV{ELp%$wQX*-m|@Y;={sgkUOkp{89%_5!?k1I+MO4;qOQ znH19tva%-Hg#WpX9~p)Vzx?ooCi&S_4DDj#5r0Q5@YQq=XfA%)9$kvcz$4$&_=)g_ zHvd<+Rqbt?f~qM0GgRQ8MX*4-&`h69aWjt6eu9dz}zQpVMdV zp*7Mbyi_vAYZWpCbeh$701Ad);*u^AmM4cf9bS;L_>lbGL9TjF3lhwDR^#ZLZ}oN& zOQh@PxHU!)*LT6oUbiq;r{0PLNh=z-)7zo?}KHq?0WV(30)ZG^1=)TV@01lI&$;uZhuB*p(v2vSLxuFfT}oe8>mV0 z`5_o$3YTx2aegax%Np237$9c~r8stIoTNCUT)YI?`1Rvsk%6{<=!B{_vYS-#E{u$E z9L7G;jf216K6;xW0K74gz^e~p3m~e z4@BGlbW2inxj3p|MyOtYLXJ4d_EBz>=Fn-;S=gB0{(#SEysd}Ji)Mu)< zf=vxIQvVy@@gvjaQW_`3lIYkjO?(X1#&#bUX!pdF93Bn@SNBjjV*OO5Yv02)N2b>N zTy%Ac-~gH>NaT4diey_Tze+BCNo%k`+#@nCLeenG@B0I8#6zag;{VVY%Q-l`~@2=yDEVo~vW$ywpeo)Am zi~9b&wR6*@HZb(|Z@089X#H|?{6_)_T++u*d~ON1Q}*~6H=FmsF_@0n_}+mr@n<*Mpfw|^ zkHVwm7TbYjG~j=a%hEObVCcGL=u9xhZYif2jySOc6ampU^mK6L1tJIEk+DH(oCGPD z@;tF%F>*0QW6&N*Yoa`eGX>t|vGyn+XOwt4HJpQkM7r-Teg4r-;9CLmwn)q<@VZAl z!D3>|$5b0EQ=JrIOj}4pKK7!}nUI(~$ajhVJJX1&kQGk_urID=r z;9@oPuG#W*2WFl(?+t0zyv#K7lg+Mw)u5?AJc4p5e_3NUkFJAs_f(ab`(W~Si{$;0 z?8ybheQF}GCInhc+LJ7no5oCxA1_EI`~Q;7jkcKy3num~Z5g}?$z?A*c>^o=pC6p{ z=-}9_L8y_^pSVfIiMj*5^Gayc*3bBk9o6(!UnJFlkgk&m`*P(^}JV%GCL>km>m0#Z|@ zAZ&-rcvZ-7xmlK}MOoQikY25yFh07UXAYC39FLdlh8zXdfkM>8zelHK>S>B>o*NZJ z+rk)d!9FWP+aHh0rd#^_@^PS8RrLbvKgwz0v~fHC$TiK}tCp$47zCn5;uEy=x< zY~TBOIAl1&%B@UGt@_JIahD{!h=U)Ys=2cpwU@;`1n?G1997Uv(7#iV)REg$8Z6UA`N%DSuex{;&&@6B~-?qEm+>VBTxoJ9fKl>^kn1F+$zX&jQsEY}G5b^|`S zn@&j1WG=C*UC;7&h3Z*IiCktDHJr}e4dx+<_XgPfKDNC+&JY!=+xPr2oLoa4-+{it z(5|da$jat8!$pRj)5B-AR}mHfZh`-lcB~whlWjI?`@~wa?s~mW@;l!h6Vh`L;HDLw z{{++=LXzmPBX@(4%VN!Pd90q%=}kBKHsX{%I$ftg*-_W~?99ee(jW>m$?;Q_^9W_) z&;;5JE~CLG@MHWMJ;9_EEH-wP$e6p$w-ZA% zPTn;)%N`_OK-|cqUdQ74vhsh(Xj{F%3P-h@ZS#qaal~5|w@(kyE$K?>;0WDt> zy0TLEu8x@LoT{3Wvux_Tym7 zOYdhIw0vG~I<*A2g$dn`rkh%uTmZ4O$8T7)R(IbIv@z*MzL}|2>LQ%_db zE_qVQ4;+?hPPY&vo?mZ^!r~yTh+xcW)4LnsUPUB%trf&dqVEM&JX9-ZeX8yjE?JqR zo10e{aL@3=Opd@CK2uAMK>5<9m8FQ*^{B%+i7Z)8r=zzmpHwc64dl|z&23rhA;gI` ze-mWtLub!|GBP|c~)HEwESO(aiBR<8i52CwQP7W09)?;~B9Fa?W4lXgWUH)IrxcYAta-8{R z{NE6=60x8%4TkHcUf=U>nj-s~)aR1h zSkaFHNrsj7O|NXUENt$lO!#Wwv2y`DxT>^Tt?R`@3~ETtV(7+dbngA*=(F^|ua zYT`Ryk5F~Tk@sdIa77I(Dv$Ri<&oRtcS=|j)uo4fiPRrgsMgf#e3EBjaDVGk%<~c5 z>1`LUp7nU8`nA}DvfsuwafF`)2!l>K|Z0peO6!@TPnBIwzf+Pd% z3(GA#hI+fA^mL?W3oiX@pPFLwx4LVDbn|vZ#9i?0oLK{5^Zd?o=x9+S>m9??J4}EL ziMrR9zjzd?a|3MiFM#bV!i_k7q(w3W*pzg*0f^m7zW(%8{8FucgX+ZLFS9j)w^$kj z7SOX0blsv2iEiD#5Pp|RDZ~YLeyDXr*ixp|;F+XFXo{|z2;*Gt2m6My?S+_9#0{!1 zF=Bg z1;KFBAAYC&z3{SW;_ly^ra>;=tF(j zi-PpH2PAd88#BLuVNKn{i;fypt;2g=X+;Eaf?Ueyb3k?1;Tw_d-L8h7#b z0+5q(KK&t#r{M+Mc=vv1h-$FespjvkR5+GYQh86yG`jfQF(ex@o3(5cu}vnf_khpW z2fb|gcwcts2d`Xlve;l`>VrB^E1%-a$dwr47#gW|9)OqCXneuL|Io3$m^_5iSs~y= zpW2$NrdFN}R*r$oD!1{i^C4X8>*SqW44uE!h-^0skr=@ z$+)6YTwCP0<)}FQ_PEs(vf3!)w3m=o3OUQPRMnMU2}#g03`4R63vVGg-Bg2cA3+?p z8!}GaKcSszH@SS-6f+{{@2oaTs{|SsE8g;Tyi!+ls#A#&B1waK&fu0ff(I3#zXHl7 z*(xl5&01?#VCmZ3*@$s@N*mDOksUCh*zo<)7g9W7ec3l+x2k>!WYQ8h+c$jA^>w(4 z2j^3!A7q|KTKAPK*D(eL29hlWDWeA?k*e45)fd`t;$wvlv|$OB*Zj|=u01F|SCVk^ zI_mwnR6W)0$hd8EEqs`Nh`-17weOva;<7``N$*j2*a9y7T$>-KCQ(3&A8FT|2aIzyo$tALkyj@QdTy zS!>DD==AwznhX1(ECrt#`uwD3zya2fyyyONT8CjOE0Fb-^^0UeW4VhGN;`5K zW&Di9!+FrIM|w+cDYu>kXK7P0KS%n3alGP}#<9Fe=AWVn{+Ew+usVX`E zOl|(-L4q>!vaQdwMRucFE4A$}^4EA5`rKVM$TH-esJ@AHOSBb)Q_@7k^{1wy?zv%~ zAJ*l`??6qC^<)lipG$>%A4QwE_>QO#DT4_;TrLI7rOO z_gWJ>AJsWK_wKZa-F4`lb;!;eV5_t!ghn3&97u zWS@{bY5-uz;U%1MN3G7v^_3&StWpxrt{d@Z&O<|U@#gfttXG?s{ljEy$joJ@`!Aep zQu0|eVgNryn$?S;qe3XWfi?Fkk?-0V>C8rB8;`|%tFe2ux~L5qBqt0o07&w~IZ#T*av`{as44)Gt|d*!u>6Bc;9hwOW&8Mib_=`L*YEY(1Ic zRn;Y%2JT3L1cnns?=btwuK_%>yt9suEw&KKYb^VGQ;#>gVZ(0zIE){~Ws2aSwk zhRR_*p0=`-#RFcKf9Sl}Z{>_c9hOAwz6NV@V-3Z+TDHzqXqYzLkd8haW1pD>ksGcN znIhj{M2SXAEVfDC3BZ!FI`gA^(rrb|25D(>U~{mkVW}Tzi#St~@>}4Xz?AVI;Un~Q ztdnU)ZnBEikfE{7H8;+;RV%gA4AM~z-AG?V&++#dGsa5{5hYolq`Y6bbAKH(5t`j? z5If&-%l#*_9W0>#sqsPX3HKjKMqW4jc*yMYfP+}t;&l41)eq2vhOe!=-yS%mgTGFB z4id7_7!b^=MV2V_Eh=@kbllytS`1zGy==+x>3y!}EK)!ypD0#&GB@q&mBp$GpM~7O zS4H~1&(7rSXzf>`>j(o*PlmZApetZ%LuH0t@5ZcwA@_`*?XgLF6FQT&GSn0Co&UjX zdbJ{Nc>ZPEY?lDi%_-00;xB{F!NQZ*Q!@EOOZ@2FI^F=fEtphSDlv2=F?uim9mYd! zBikD`Z4rl&4FCbd_;uf;~w#OOqIAybZ)~555 z3vxHjO6N2YS_VM*P4XBd<;xVJQK$huz&N#x6QVX;Sn`ETgogpPaanJWn}rauc#8^Bm$OVD(H8?fvN)OrTeH&y5qC`OD4RA+o zNxiHUJ>Cp0WpzvQ!i=#;E2YJT7j%IZ=JM>y=B_g6r55|^#k8@B%WO>=Ft>6e=!gD6929aAlE5a?k)`YdvQvC|Ub(_0CKb?6c9H!PVWX7a5qmVeNSqODbwv%7**;gqJ z=beey?YuJ8B+L-E?s)o~gkS*K7b;nIcj)Gh&ZP31PMsfI;J`k(IZ(QIE9GFODWIm@ zPf~8w+ywnbZGvC}Ntp8Ibs?zDe|xPgTnMuW6m0QufD^Rh0pSnfKf?YuGDGlRVu|pBr}@ zHGWex(D^e|4RUV%bQ(L=6CCev2dsIi#4Ounb-jLaQ9 z1&IqUOaGy}_BDCex^dDHKk3H#;#*<@HYDD%(haZV_9bagzg;gqUxX*>!+VK23G1y3 zx@5syo{g)Khk=bfA7#(TAqrMzZfW>sXh>}}u)}7j(>`ciSLTdsaC6B{L+vZhj^BO;>}zMgomPre zjXDkg#z4_=+N%jbr{jr2qi@hnD=4aM{%Eh}Vb|rasq7zpYYYlf-&>haXwnZQZbU~1 z!AzosMeBbFH{L3HvEi|B?NPzWaDHb%!*1P|hQ-ggHH!iRMj0-GL}PV^^HBbumlC}) zUqAo+&t)P1-(Cg%Gx2YG<_fqm?&TX}_e{fAD=np9StHNE8wEhBdjlNR%fkbYuB5=feoA~{h<)flFzl7LWzVx@*L7kL(c(2+TOzh6DSZ%i!U?A$}=RHjvE z4>D5iCaH2I#|;mOb=6pG!n35dwj~uASZ#q%~%m_2%NR|xrAEWgcUZ7yat6 zm6tY8j}!gYxaTfDk1~1$(qM_sEdZX#WbBGGb}te_r$&!pX(zp@(8=FC-3?#cXN-OQ zPUPji{dt+i-U#`Fy=_2T#z0TXC-CD_j$>7wJpEVLn4psKDmTTu7_#1`{!-js@m^m& z^DIKZ`>XCwjmapuRe7DlZFO{ST=k-=l^q_IV|=Quht0>ldE3-yQ+%x7!6R~S#Xl%F z26j?FEkLP~ijUGr=nBenqNIeIRDPp`m3E7smAU4xmrP*UXRBFloPK}gVqAA&KdE1+ zN$BMYAZEi$I$~A}gPwh~NPaSPm&I{={CQK8;>87Z<_|GL0>};>pLhJu+%B#wO4Yzf z68au+|F$a4z>J7l0Y{_M5SG)l+oUq3 zFB6C45b?zGKb~T*e25kuc^X-EC-~@2!1NwydjL4HFUbTFa`h*~(XW`W6nWP#Kg89g z@=Z&9yY{r>i$q4hy!Z_5xj%tMFc+pDV8T;0=_WWFrQ#>A#ztWYOvH6Oz$#RiSU;ZH z^ALt_zy#n2=jQ3PvHah7i(v17bMu@wiaw8Yh`)%?oJ7g^g+oBUoOyU&&DYBriuNRa zUrpgW=Og;?@1D+WI%>Ef>6XK`*6lj$c){;kXVk2mEZ=#?b^3Et7D3&k_;O}Ms)cDy8mY0V5n1e#@a)~c1KuRu6nxaeUE$^zP z=uhveK19O7$y~`h{KCUNB@aG(?pOv?cY}BwmzeM7eKZ4I9`*iM+!Ray>M3!Zt*&|b zz%sEhVgX7plwgz7Aa=wxyy2UW*K2xw@muF(*Gk~|-y2MZakS&D>>+J^2Ee$_F5%f2 zhfN}dFD^1^HSqH(kNFw!!^&q~w}0{%&K6p0|CPh^WpTz&&F>0a8CNNVU5tzqcrG4Z zA$=HYdH4OB%53;SoiF!ip)mZ;*>1Lbw_Wyve-^Ae3NRn$eUR+co%A zt21{11_12J9)%mLNu2K0_r#zhscLrD<@o;~?mdH=YX5doEQo-JB8b!|MWjpbL`1rP6bU`jq=WPp zh=>%a0s=~l^iHIABE1Pn?BFniQlTidw5-X1~S zaJNhB=F+F1&-xBQcDwl3p?|Xo26*UM>NwmEdVNb#q8SUUcZ~jSW@^9dEI53mJSjOv zxQvCQVC8;jIeU4?$?ht48!dR(F3!rs#)XM77s2b9H~Z?v?d)jke@iAPr@gliASOS9 zm5IG0`y+8qBsDScKdKXjN4MHFg_we#R%~%nv+T=kR(SUW6`d|Y4swHhndIVSdSK3g zefh~{ysNl49!YqvT|DnhONfyRe*8ypBc~y^T!-l$s(aG`v|N&O00Z4Uy42CEoCjTl ziQ(YHdu*-R_7u@XT1=VQn;}vn+@Gg@1ioJDdr;9Za~0(yfWdxYXBo@I2QySOM3Cp( zYir#h2auB;mFq><F_sMjATXeE2!^4AJcA@j9}fP?He26$Gm4v)R(UL5U0jEpm@R zC2T+2sfzNa#Xo(|w@R3q0YViQ)4mZMd&<&85oLlr=VlC#*qmn-*`AtKZR}sP@o`le z^4Q=2BQAAi$m9y3EB>?}@)&P}>6x@-#rX`)&pS@u!P#UO<272JXRlz2%shOrDK02m+WueI8n&d<*E9ZG`T2vVeqj{C1_gy zWB-VTpnl$+{LOUP+br3UXuqJW$J-Xz4k{Zq{*S1dha+o>NL5ULT~R-+c=gqlgK3kSWZi@%w%#HnLrjmg(Z8H;Bg ze7BR=%|O0UnROPg`C1^`P_xGgi1*u--U7qNXGD7(R2!d+ z4f+YXt@u!D^+Bu7OpH&!W`+ZY!@Rtfe00c8i5q`k-#~Ft<*4#Rhxlg6FPJDEgiGjd zm#xy$U3fmxt=egrq{UCYQa{R*s{DW$(KN42+v^D*HXlRnQ z9%Ve3>ZHW+dOYv$WAf)yUq=-89R)vr!vMk`MG#RPpMa+S9m4G2)5=mDkdfbf_nTDF zxgs3}4@J}*erkV&f6kB$slRJx)>3J7zwxum##;NY zjYbdZRKYx$cvC4?h_`>*nKyoPRrvh`X)2NEJ9Qv$;b_I)#P!_TCI6Vr>*mG9ZbD1L zJW2!b$qUE)P3r@{Z)e0OR)mu#P|@m0Ng>A32<3a9!SlUv=Hnmdu@|<7-oBW(1=IzT zfA3sLuP%6=e#*4j5$j8lQ?WwLHlNH9FA_T==)T%NAJb+CnZexM@eJK2Nko*r*TmF! z4W4{1MJ|g3JUljdky0DW*>nM5HgaYxPrMyoq7?QTTNLkJOO7pna#*wgOEmw)b_X(m;#n#{D#2hn=YO`h84!Keq!Wg{Gl4a9}D|suhR6|M5 zM-hD)BX5C0v4o6R-opV^pxPT1^4ykh*Yj1tj}(g-PDO08>wrq>!pZ>swAMXs7WRO$ zyVph~^o0cWh*Hd-@)P5Aei;FZs(bAd%dN)$kTGRvj3yFpTd*q=B5q_DD=j2KW}f^kC&>V~xqp7mX3mG&tqdy{#^o*O5{WwtRor_l;Z1 z0YgK?JWG$?OuGawA_onP2-MFvsyDR-^rS&3L3n^b!kp~PFX;7+Nz(0*`BV^j`%VAm zwI0Onx*>`tR0PJouJ7&dh^0@E_1pQhgk4v!0qK@S!yQXOu`}}MRK*X427OScLy@q@ zu^vYI4J;pDA9$D_&t)ik6;4`-l;)glH1Wq9hi{vIRr7X-sOl>?;vU)Bsm{*+bg^eY z-5x^A+?ym?P3GX^R-p@o*VqzVc14NVk|S>Cotg({?aSB@Z_4xM!V32r592+y(-V5w zpf7QdxKmd--L_OIAka~%qNdTSGdtyv=dsGMVv%)LK`sypPq^bRN4lGE&p*c-&a#Nl zP>!CyW^WS!b2pt-4|uqlpm|9XZTLkz5i8c;7kE;vq+-JA!}IH)$8Irj;>=pK>5|_O z^)3pgX1B^wWwLB`B`(>X^!IAZ4!#s%t?eiENX%6HnX~^r9QyBm3EF?A{tHU2H0Zv2 z@Mdm1dN7EQZ6tp3pdl8h#^mcUefXr5?Ej-P{Xg{UW~+M6$v|H3{*Fq3Oah@b&XH)Z zfSrDV#u5{A_jD@tXQFYRn{J$R( zZ;$)L={|2|{Hxt%Hd^<&I@9ifRp=Q<)z-D|*z<_fQTiR~LI=qNzjvyd#b~t>h45f% zAFP2Y-r{z~nsAij!wCr%XsX?Wz`E$7E+27OD;Aa~FXmmG{G+Lv-4!Q?*^DA_<3~w! z+qfcXRox$E&pg=D)#7r&u=ifOc*wXZibxMVE5U)f2>*~pwsYdFP<1U01nEYCyxt-? znE&clS&OHAl32Qo_m9z!4rN!3*8wz|--dYnzhpw7eJ7OK5`de{LTUC~9vWwjETWmb7ae`u(7b=h z8v6FofcONDKxZj;X5Vg^7H|^}a?m@OW%g+ELcvp6+$~RQd6xw<4T@6?&U?Med2plhM0#jxW>hEOlDh-7S4|&CdnXo(7;6IMEd#(50|9pk%PuleKZwruA*j zs7bCV*VdWl=g+(A54w_n(53{OmCV(cd8vSO07MrB{GIKn#L_=xUC_NO+U{cHx`p{R zUFWZ*5xWFO8fY@REYMU*V{o?ho9JBZbiX0wPMG0D;iOvy`tCy2#|W<~RjNNv0R5I- ze%$LOfrRl^#6pZtX(!0iu-T75P^k!Z)Um9{GA$q0O@4X-(qAx?! zc6B)yt6_pQ1%A}r$uJ8tk^gBU2Z?-0{&%XS!S{uYtqOr*7jeaVloFpKA5gMAPaB76 zinowFH{^PD7W-WT1b*yEOEKLRqXG063(~Hk!bsfy84&DpL5}0F^wi$IYx;|iN<$n;)CpHN-c+J(&k*_20t~ZV_hs|;*8gd z#@nNDs6OcIZZDK!!7%LAZ*+^9eZNlom62I?FwVUfQH>;u7Dda8 z*kR&WUQZQSduN#43`G%)_QzV|!mXGSkMGU5hg_x;tq2O+D>c0>-(fbvbQWd=N4tr< z#+u{0n|Tgv%M1O0S$|e8a4kK>`-2>lqUa>tuEJpL{5=S*of7TuyA*l0vM@1F_4#1! zPjIRKsIJohmI%Lfp!k$%J?7FXM0$vg$RQt8l1!ofDnOALo1{F)2&Ya^B1(8Ha-AsJ z;G0&pz}K9ou?}a=vCOYes3mH4-bKAlu300qavDVP=F|L=k*Lj%Y<>1UIUB zGABSXRaCcLMvvB_abb5@#zAxX*EZNz(6Ubrhx#Z1ZcwuKtpCYyi~eb!?s?hyAn5MA z^SprHbbM?#Y_O;ecE+z7=&g8fPu!o0M8j)9>0##RIK{ z;(cPH`~a+<6mpnJlE6C>p5t$Ws2xdnPzk!fUES)O?S;GrU#w96^1uA^Db-LwV|%(S zI;bXWA5;#-z8Z}TjEsa^gCm}9O*cz?Z1!o-^x4X*4;8i*bZfb#8%NN0x%k@aDYK9Q z9-VT$I{ZX}@_RKxSHA1r>!=g{-_cv%@GJPDZlhyBo8D8W^4@NG@e}v8nIVH#5|vX= zmAe|=4oA_=oN#9J?YpH!|CMjHQJwT6WQ>lI#Y_qsNLBp6s(U1qYJB3StZESuPo*1^ z6EEWv_k8)K-TaVMZ;$^2d(s3rac>4_ zN(hDJ5Q|l;Z==WCKWxUzht_At(i>)UDUY?ves}OIk1ajOzh?e=y?qM$m66Oo8vE|J zF5qwWFckfwpEtQhf+IAp3F&`SX{*ny27?LqDZ*=BLc;EgI?{#JXEd8`xzlaW@H?^ zovTQNYYB@+V71_%{vO6CQsX1hBSmaw+skBaT4vNO4y~x#zIV2sQ1`)g^$}8mu{|Qa z-Sgv@Dk`m#gK4Ahn7^R>>&Fw&^55T<0 zVIZzAvIAbD+d~@-zb!9}JMNPTxtTOz?;z%;lC^hFz1{ZhUfk!*?<@-k2Y(?6ak1PK zBS8-|B*5PII}x2d z<}kj->FTG*62@%X6UD>B(Hd)3CpOlJ^j{UOuUjldc(b2cKoF^I>aZv1pnfaskV7}# zEj(Dz+4a`MW3wm>Bzt{Y+L}Bo<9%^!l6HtZOnhqMZ0xeZ$31Gs{Vd@+jOT_R$Bhjc zTL>RF=Vimt<<-BCWHZymNW>o>1K%QExGADCTB}BkU0bKDLk8)X?JD>zyE9(}a36$o zdi#*>ML%wHXdSMok$S!-@(|Cn`N0Q# zg)~UIJyB=H1quA1TU@JOLQc2yeCz4To^@-ipq$aT-|xfj$&G@#I>nJ!@cyFrzQn2h zY}hj|z|mTn(fM@fGKW7&{(GK#rE|hPe!awY7Sm!RGEcGS-Hs~RwTl^r(F#kZ)pe49{|0Un2Nb3xQzFz!x+T0?`Y84*YS3G3 zrzGVlRjBi@HedCLEI0gZ(m~M5-aQ)+M}in$<1J!T!|IsR{e|1qnMrK)sUylKkkw-; zK907)JkI0XaX5vcWYXWwW%;XFQK~M3+UqxO-|EO9+4;}+P8Kc)MZ*&l4Qb4>^mMOMKJ!1EhQc(SXFVdHqEQ^Qd6 zX;mwL^0=YDtsb@#^nu(?Hd_11LAqEh>+9ud`-AFwlbIsL6e}Hi;Jyir?M?ojBst zr-7_77%*Rml)1t=kzPyb$GCdx(L~1~6O~7`2K#gBY~mfKm3SB}LCgVBD;bZtUm=*> zGry4(?(a;nfSoUbnSjm+P}()3EwOKW?#EpW)Dl< zm_J$r{`Pd>l+F-ui3Bim37@Zh5?Z^8b9I ztHZSw*FRvS__0*2kiOQJ(g0W*8y1MZ=EJUXs`zwUKEkR}Kq@Uxd3a>pcYkyWI>kV*kk%CHy zF^uOjHAIp4Zp;m)hDCPFggl%O*pNKZrHs?F`)U2n*F5v?#bl9}*_>0LF9PsQ;x4OC zSq^_FV|y=Iq*nw|w*d+vwD!G0s|E1l@nuyjqr1CTDNzj7WEL@tn%k$jFd)s(w}yul z7RyYCi2p-2D|OZ}*&Q)~w)_D@wzYA_fX){xoeO`1SF^x%%dN@MSnl5JH~KxoY*ud< z=G2CVUw_(E38KaGxbG(vn`bzLuq=P4Y4{cJ2pAYCoNkAJfF&vrrh^Z{g`o>W3F>n_ z-|;rR>Az&%5w1QA9RbGfcap;E89SI1Nngefcy+aD7r^nTA8C906rpR=@-(Yo#pB%7 z{0kbgyIb|aX*0hz9k(Z^-6P@72pX8ghYm$ff4Et_nYs#c-eupm^;0KS^d7cC=0ti) zPA>a3E`@X_1W-EPC9yfOKO8@-{aDkIQoB3%{pc;{O_F&c%Fwf{;{+KEUM+2ge{3ap zUp6Kh-OWPsD`~a@pF~prz>>I9I9n)4R4OmeF@X9EE5Qk)AKzDmU`8%7l;M> z3BKzh|ESPx=dWOEs_ewT&0}G^25C{5KDjgs#Z$ZrLAwJT1Wq6+RAFD|`!Y*ZmU+;$ z-ihV7InqbH-zq|Mlqm6TuBp1rBHhMQ_suiL0_8YzuUda#fdvd5{&m*XIWkFg>uyT* zQ~vpib{0~nCD)k!RI6A8eoXtlfp_7!%=5=nwDF!`qnR!!Ux9Z^@+7bc~LMya#4mL+D2tNF#`vmGDQ-ghSBIkkzBh z;V#D(27s3jm&-Y>sl~eQg<<)7+8JZ|^k7QUx)JQ|9Il#zthM(m8!1LE8d*;PA!Y^Y zZSUn*5~ndT}V1}-Gb3v>NZtvd72&h zPK#@~4T6UTz!7v9$SwN={s<<&PI^?EVKK>7on^-%c3YXVQYB;$2AULK68?#GY!08G z+#{)di)ZR9L1y(CHtp!C)%%0{*y)>EGPJdd|76`jKRP)nMF13Y7aG^F`jNzr55_z> z0nsfiEz90ldT43kJfg)VnpTf*0C?doc z8jD)Ow4zkx$2z;#J%6ZW?MOC^E}kOWvV#?=O$1L`$rWyRIyp}k?)S$O-9UPxLSa@p zTkZTY+B1iA63uT~jP1GOg2TS!?K{sPGqR)vcWMiZ1i?*nk$Kcl+QJ~95xqvnx#nUX z--InP0UCIka0}@8JnrFxG`RKow8yd*zgeIBn2NY?s@qjLjfQO~H_RR=zmY=U568xX zBbbpyF2p_4&3)z*k>SmGO3oBmaWwpj{ewP_%$Wwpip0%buPXcmyod-!;VT$p6d(4K z;cL35JCCM`r?;_`=^pZwD3wzX~-!%JYpdf{v&4o4_;JE)8P@A41ZqZfzk zow*O@A@(ps0d{42%RAHjwudkRF zvkNnzK$JF70$3EwBm0^^&YyRz#Jnqt7=K#-H+(-cQ43fJkH+rV6jASLv`~AY-RG~N zqlvQ9Fx}Nl{yx8KaYdT!kv{!zuSuQuUlm`t*t$e5Ngl~=j<>3gqTRb)brhIg#k%}v zK4HiO-~4`d6cY}4(&KyWcUb0SpniOZ7mLpLsi0V|WV+yKi`mNjO5gR*{Z9w@2Je&w zKd?r%X1wcMe)O=5oQWM@_N3}xq`rU#*f@kUcIdm4NSW(nN*N-}UD+S;Q>(<8jS$#e zX6ROCuydg3Ew%LBqN+=0$aj?wKm*TwyU=A7%7KOvy#d%kf#8d~^1QkDuAl5&$!jwKu#+#P$^W{a{+^ z2rE^_cQ0}pXoj+-OVgCHQbg%-1C?!we_a)r4nb7HLT*IzaUl zTiWCtZ$}9G#}7ZIf<$aCCt>w^G$Aqc7CpSS?%+PNi>zguRi1GwLGhbA zL%CVJ*--fN$GTpj=Hew!CVk|xj!M@VbgP_)I03edPl<`?ta3MxU5V+Y_D@eICA!j7 zH|ax_!H>6(yXX#oBkT89m>%g!SL$Q$y_5RkH!tPN3W5mSnp->ML&?G^N^5JUx4>|!+l2}T)HUsQ{Pk(C5uc9b zj)@0(n)iNlbz!wh?!sm)(WJz~5TKhKe1GGHcPzu_7W zs1X;{1YBq>d83N5T4#`q-T|NJdNmOl74HC}ui{;z7=8sUBhP??D94yhXt_rv={pA~ z9)6=Qsau2R!B%?G{~)z>?%U_6x(RLJz~P7=_IowhFcaN-c$?0O66gCP?8|G0SqHyv zw=s*uKQo*zr2lQ#l~fZVHh4w<>C%tmwv|1#Q1fLsk#OXEQWU-8GC=z%+&7!~)n^M1 zV&7X2OE)pR%Rwj6p4vY-xN2=K-qYjN`>u^%{_!yLC``&he-_lyhqdY?ha*w#mrO-v z`5Qa`$Y(!rk0XQ8ONKHvlNkTUcdLv<`ky}IA8$QIgMY%qq1X4^ya9tP^L0~E%QreZ zS{jd+zX_U{Nd4l~n9G|YrqTd@KfXjO&)dsWMWR#=Zy;=?KC%0Pm%JM3c~#ix7in&@ z7g-+TrOwg&f!nh|kSGK}3uQCqe3`{M8G~q*p%~8=T#U~I80pPw`4pCz^)G!CN4Yzl zU4}pmsDzwtOHGq9>yN>f#IfcNEEP5idUXm+I3Va-$9?W5zSzHBnCfMN$f981T=?RO zjbPU7Q~L*Jgu1gYPgQQlKjAdC`E=bOs*x(@=e0TK?C>WOZK)e6e9du>&jek8OuKLy z2#=cw-sqhBii+|;pIgcp-d1{Y(9_!c(m8=1kf06!7&J1jFp zU-RIVv7}ve7>qet-2g52R)FR!k7H<%J+?f6&QE-!Swfz3HI4#(9qNT_;G@#P(_BEsf=N~5|P|% zg#B#bGs%UyF2|#uN`s`%%hK@91Tc&hFX!jwgGF^3rPB-#UU&{ufkcug1e>aQY;-c+ zJ%(G1PutSSQeJ~oOrqsty)XGI8fViT(;kJ74gsd(xpga-2RA;iNeu9E`6!w13AxiiH~R*A6e+GN_DnDFdQ)B zw%_#liaRgdKPKI9nEB2r=kXt^)YoLkC1%AN0Kc<|c1ydA!>)80g|OF*^1D9JUx5(%a83v9BY)iV%qD7W ztOfnv-9KzSz!ZtRVH>$$=w)8`!!!&20qr1o$oY1$(BkJmWUc&l$OI%&HJCv-l$;^7 z_}^!`|Gig1|IGYX4C`zjZX7WxU0&*9?k838^NuQoc5YFH^|SxpTm74y_TR4zh;2VH zYxl|_1COg#4vvK6GS9mJ#iWf6OI_D7p6YPt9q3@}gb#j?ipU0R3h23HH0tBu_pE}; zWp}}cYHnQ@%qPDRHdFr-ghwIti+DlgttA8AGK5GPTxo!RK-nFVZ-Hq;_#M*Y+9Unk zU0e_MbB|v@n{O@T4JI{#J5tZYy+woadf=klZVBw?6QFGv9jl*;r$HfW4 zK#j%V_=fa{C0)TGb=zdtFD#0BufC7h_5V@t2VqUzW8w;<5+Vfi+LS^cHVVWY3=Wu2 zA&3mSYcFHor7y=gzvD9a(Z|ngw2w$DP^&?BCaK&68ZD5}T8?M+x203uB>|}o z{%c2-!WdxKlZFBHQLjYO`Db*dz9)ibTu-Oe-+H>+H4viL><2pJV^6nr=;wD7XeWfD zpjcz~_xePMFL*iiDWtqXiP=}v&Ydf_j6Br~jE5vQAUAcf_I?eTXn8*Zf5=$7z;7Z5 z=stxqpeHKp2seceYX=S}Qg8i~ZIzci?dVk~^9f26Ot7rQs#am`yMg2=;U1P0oZUgp zb+17||CA!V5jvCte6_g!DK@Ql2yqi;hy7)m{msYj-d4lBTakf6tmn3&v|ImyJKcxjAv8E>hwBXm>A78&eXiEjC1y0I z`xi9nP`h-7$=wOfX{W*IWV}fmRZY?A}F!5b`U@eOYzpkC|63TqXT|oL8#Z zur1AB@7dU~1f29zm{v>LcPQSxjIAVbI4twWbRh1Cv%z~zZ-wnOt7d@bX-

5+A$9 z?4Rp$R=}3*;5eIANX)P4drsMuIPU5c?w9p`>}FEBXn|PBl8!<#ujb$Tt@dkhHvcYz zAApn&$*hZ^y>qBvy=bn*yh=XM?$`MVuH3jcfv7J4wV zY{`YMB0R!VZS+0I@x+UN@~O~Bl86`}jfFj$Z=NIa9HPHyFH zA2u0%788Wg*1^mVX;*)=(0!*%$yid!*a5D!-y2>-(JkPWJ4hl`?bGh+X3n-kg*LH! z+Fg#)*Db|fvC{bj2(IczhJ8Y3Xp42B?$lcNzlcyx7gU{Bg^R=- zJhFB1=?T7VaU*4J6QkdRqae}`{alv933ml4Kvqxa9wWnh}R#))}1Sz5io-=p5T@ly*VP5B(kMECp%YtsvGV@~5_bqH0()wNvtdOP$^PA)& z32Q4oEBEjteH!CF`)V(6w`Nj(XS|#w0|UEYik1(vt)=Wlj;~mz5pKiGS}!wTHYG5R zX?f0oQU?vEX-0D>=#C7TrM2A|<1l3FR#4IQ%1CoQw3hV8bAymADT)$$BqnoL4 z-%V$B=NiLW`O*avuz(VtcS)c=Y~t!ZhJdE+2-^GIcf~)^*Y9)+%ZlP!k{kEu)tQj# z^3*t7);rqYomH1h@$s{8~ zD1RQ=l2l9BjNR9ir$X#E>riwl&m<$H!Ex^V4}Pb}RBXGz&0oh|ya@ePJuoAIquu|6 zhR!-0!=RIKSUcU7GESJKsrEJ zjTqyiM$nyBXrS50xC$G8^ICMH6K0XeRgGLJ-c z#c0MZ;uDJnLu-v*)t!T-`>Uj#7!IelCkdKIQx#ltc94;-tQ{o5&rR_s1lamJ59ur9(qoJ z!LrQ#l5e0$??U}?|AI}MpYB3WDK3wAp=uL0vCrGNU(CwbTxBImj8`#aXZPdNB6Cse zXg6wF>aSA=65)*^u?JKXTXokZmmjn`T9fADt#t=W*r}%YfYPwdxr_p}i=nYCQ%iUN%ws$$DmUto`f>ma%e(H8Phe+-K1q4(TpbhmU`- z%l~objIK=$0eMvUNPDW8N6+js1R6XR=Uu_@1E)CuK#fSEPM#2=tH+qY{yxd8Oz8)0 zGyOfi)96u>MTUR^H&VKO-ZGZkam6e`#qG7pt2c(p+krG|A?N0?4@vY-__K|pXGl!7 zPfsdvS+1wq8Gd=nP7NQPe0>uAN=@-=rLQZ$O5M@4h29nFW5!;y5EBpZGHN6pOxFOiYYd}CZ6?o0n3*SXG{u^29Ub#57}9A} zd9Fn~%o#Sy?(3@3^eTA~zZU-Xr9nJL{ovIz`j(W(b=VHDB$AGPlWIUa945jam)@!~ zyParOdb&bvk;&rY-=~u({Gc&R1PjXu@MQ|3V?K;2m7BfnDlL1&Q2{9WH)y?0{noddic9>fP(Z1k?6gUK#G@|xIqP-*57n3t0rO(~2UhE|Bdtm66YPw&Q;m&@Pkg;Ox}F{iwS z960$r(LXcWvMxlRV-JE28Ak%%fHgCLU_&uPntlQ>NO7=kzO3X%yEfk({}nXdR2t+4@z0`P)5_3bK8Meaj0enAl^jqD zGi1_+|6wsAJzW09$2(P?)*O?_OiUWZ!A<@12qf3oTlA^up{}M!pZH zj8QS&LYIeWn%M-aUZyQ`xPJY#3pdL5%;h0l~s#q7`AzPcGw78)n(A=E^jTZs# z|9Y34j7~n# zczUktn_F*}d_N=MOXls9{t5N#%^!3FA!Wa7OYW~lYNWKkUFg#sO%c0F9 zjKZ^m<~X(V>jw5mBh$PB7TN;Jd}F>-Cwftm_mQQKxV0BdoS7PL3DM1A+(ndyWZ0($ z=4h!a$}CN*)E7Vd*@vAtb;g!1EXg|Y`Az;dGn0&J)<}{6pujIZx2=Z~gY_*pTj>|p ztBIFPa7#AJU5(eW|2+Y&IRQ2lL$mAviQKZ+ZuWcI2RhAeU!OVZsBaG&-`RdeM2c1h zUNh0GFmk5y9;5G5O1Sz~&E|J{DC)-|gV!C9o<@*S%;j8JP7HXZE_R5+_G+mo{fv^O zh1RiL*6+GnDt^(<|Iv8%-~Sce+gQpMN%z<(#C-Z~_77Qc0-I!XcHO7{YfL3B&2m0f!rj$D8GozE& zq1R}q;Cv@c6vuh=?!alwM&Qqr{UOM5AZTyK8DI?2KBzcF2?vhxU>z&L=r z!hg4e@Ih;lF(;r1x2{g#^q9V)nkLVB;yaB2IZrjT{!4dP-2xI|^yvzrz}83R5XHt$ z059OSY=48pX-4ribN+rYML*xs%On2N2Cd69)M{2FIxa1NqiqbKRa382sv~5i!NnK$ zi$$zmYGsycTyZ;+Kh0pg7W@HKrTa02d3F~})5@3wQ%!jNnaf?^v$pgHm-Qh<%vIVv z$gv4Q$uXN@j3ka9(!{>-P|00zqAO^9^$%HDl<-QNLgEoB+>4;&XuMT)+t9x!c!8j` z^LHwt<1kECr-&?@O<6g9f75$C>s`w=K&^hW;>Nk+5}pOHVvt|PkU%i1aTqUv(Qj<_ z$SQoTPrRp7)fj!IV$Q^TV6XwG{VgT{Eih1M!U;Fb+^cWC`s?y$_@WN%O~2tO3h!WPrQwNo ztz7`cEbJM(r?oCzO8N&^I_g` zpIv*Q;!j+@A=sNWtT$v|CyPqQ-Rs!-EE|tpMZ|-ce83=>H1>nPmP*TA4wKyQ0H(kp zq2YdDI5l^|u!E>g>jg*2>c+t6mzihWyx)#{vpk~r)vwiH>R`Llu_cS^(dmsk2gX73 zqpOEKOZ;8u(0lTF7|<>M=+1Fzw*&7J(efl!*;TjxQHfvpnl6BR-si>8CBhtMPKD`J zio_NMO1AUo`q)Z=JK)g^m)oMAPqbdm(S?kF8HhBXu3@#+%gFAgc1HhpCN>wJxm?g( znn>9(>$i*CtScbqN2-NZSu_>Ar6Vd*HW3}0xRhg&85N*;PwG9ku^#ZPhTl2 zIxKu#CB|BkGh(IX&$W19sICUFo^DPi-oPdN1kny7m2eGRNzT)ZM&YwMc#x*v(78KpC@KqJSH{jg@C);97H9b)>I>2a%T(ha19EAol3{0LWki+dQ zXnzLsM6@d9nOouy{yJ>dO$sa`(>T@TYd^dF@!q!t{w3ru;)4*;ij>m_f(PHzH@hT1 zkMP9iUi@y&sArFiU_nt$xq3-k{>}CxJW7}|Jyf6eK8*Q|Z(r%l^?D4H<`{h*K7$Lq zeVTaU^G-vck#ET#DR5aTZ-;-`YETjC;}Pye(vtczmv9^^7xY zMgEoa!DyQEiI8wqy8vDe8~GD-S6-@Qm|eN)}e(ej2VS5VU^ zcQg8ltt6izRt7{a&n|2)R#Fxg(+8{Dg6|pCPVTYU1@YQ^qec!|N-m1Z#YW$sej7!g zngC`!3FV_0YCtpk8Wl~H!B8_+H%_EUdUUfK$csLF`@EfiqPpl)#tkFG50FZK31w1MKy~@ z=uADosBk*8d+IRq=bhTO!NlyTBj|h5qZODCKBbVTf)BP?U)nmBpRR(!^PemhJSAKY zxG)|sQc{vG%DY#*T=W}W3))v+b58*5$F<<7?7P)t`4j7mC2%XZZO(vb1KP&R-lYjY zbI8y#v-?$J=ifsZyt_m&H!BlIb)sN__u+AWk`3_~qQe@Ka%cV5K}a8r^0I^kq_X0n z7~u%^E7-Qy5L&!r!2)+ghQjDK4-dET2YHP5+Ls~Ma#!scjz{++arPKe8&8)7;~F#+ zSn_ZCYdvexm>%prkVDq!;aD$4CAFY?wJ_U{8Mv&2%+ORQ0vb1q(y z&>t~9Y5F25|Na`~aq*&Pz^-K&+I@kuFBMenmP6p&Qe=+UnR%7!m+|V=(XaXmbuRC_ ze3$!uECXxN-(y|i&j7bL=wmae%RMZRZmx?9a?b42dY)@_d|9~ap1j3a$ba&@I-(~$ z#GN#`a#daoy~4HyuSL9c|_qHN45Od+7xu8E@*J8;Bv325ySV7$5y1+CXjKMbPe>2CI zY&8UGOG6<2$>79X9wSEl?^Cr+pAR{9>P*q`o>P(62Vv zy$_+u@cPY&5O#dV*#zDh?fz*TKmfw41cID$@lNCu?znCk{F%&MT8Q{Of3c^dWM&2Q$WL<0lUIFmwvY( zn;ThJIW*fj@m{ZP42g3B^BZR691K45{ce)#`mB86x|tRX9q}C3E2VE_|EH>JVk0DS zS9fo!!a1AsGF_2%H{?l5(PU+9RM*g>q5i}s^;v|`v$`$FlZ@U2ujuWq5TKe`Q|sPs6o5B|mQ$>`O9yYH?H2OC+~Q|!R`JYt+h5hd@IhR&fyI^;Z= zdruc<%5xL3@h*naGOsAyQapu4A$K|+a2+RhR0hUqrD++#GS&c1b=a8(-UDd~$dxRm zZhd)6Y^2A5*%p)y$nLKa>#`nkx7F%K0aErD0DnwW1(Q96yIn!$o!} zs4AFgM*G!^mOdC9U>Bv5ExUaa9Op5SzPT=&X&NcArS+$GeM;3M7LzabA^**l6QtT_ z%-MS`lV>K+tK+*3dGy<#gWiR zwrv?g&O?hjmh})Czu;(UfYgV4*Ri(BNxTa!=?T5+6(wuY^{^ zjrJ(GttgM@S~1HvIdZ?c7}0vFf+)8t%%UV& zCFc?`xWntRkv1nF{{VxOu7TKSvPjPWY& zS|-#~4eYDudz$D!Bx9di!b9Ip9O^Z3`Bbu+YNjo^M`n0Q8<$&6)Hpu4P~tf)UVpOR zV4ZltUw^l~h(4>9J7MsXlKKqKe8Hz2u7)p7qvi%*WD`g1@MS&AH}S#fV71 ziG_sJqWQ?XQn@QT#@O$$VJI(9B6oE8g$S?E`tI-CbKl6T>H?$}cXFDXX~q7gR4Wkj zNk8AlAf;xuNJl44RBh%AGVhjW&oGsn*T-?SvXQT&`A$%@m$;_l3%wJdpDR8xgD?F{ z`c0FtJ*Lwh;|THR3(q#1Ndv>dI;hScCS879%ckYAUl(uC*g7Grai2Ylo%@SeFx(-1 z`Rh(M2a_|O1kaxHYh{mgO( z=HZS#R-U#^GtJ)IYf&72$nK`O1`ZEMf%2>6sCe<%Op!!M6Ywi=`{KPcOj;CX0x3bh zLSC-ddM`iWCY%MS3U`}6#pk%JaTG=1wtey04GAxh>@yrC6lNqne`UnAvQ^$5WG zcs$K=!FsOMO_t`>^U4x61J7Vte1wM_Uvt?)@W!mVE$*=3e>ne&KADpZ3 z3j{0D2$*cD9A<{OKIt>`zC7JB6Xnos_1M>rVlcGLBHX{aG|y`yPI3r(1?4yz2Ch|T z9mURHR-BgIcB{=eJrcHpLItwb8W;JuAkuQ`eRYA-0lZ~-@fE9khDXW1#9NnqCvVNbnXRxhSK5|7n7G!0C`BCwA+nfiSPUlt_on*hMTIVDNMUQfkL70%5>C%M* z6=(Oiq5SxTvnf3HsxDhXL>i<<3j-2=W~END*z<@x6+5wvStET>7=@K6g{i~^-`|IKc(R(m=X`fnFY;24I@rUHJp5-IJPtp^37 zsw^81))K>BxyDhte$Q^Itc|tdkB<$_YTT@Fm=jQZ=O^8#8J$*BRVQb@Rrywg?fW0u z8Ih`MpYuY8J?A_JM)gTOqfYa%)z+`?=^l;4O;2? zU&Os9U)S$KegNb3A(5yXI6S2q$6)Z3 zkleWzV}z+oB0#=QDQst3+6wp#fhVU_r$pXMbpwhgTS6Z(7PUG@5n^#Cx z1rJMBo)v?vT9Oh>;Ub9~lsoHcbD!W>o42K8O{}gPL%*BjjDO~J-S*CPRj#J5#C#Gf zyroI9GVy4+I;N6AWS{mvp~Lf}&zvSW)2p0fpz&4H(tB-)8%BTeS?#JTms}W7gWQ7V zxn?*y?$x~xyUcb*)xF)*eZmReo$5qYuz!N{lEK8R0-`t8AX1nhA8xNBQqfRjaL=n; zizny973*Gu7ummZ(k1Zc7yke`#Y4{S_-svpP_2R0`iLV*-LSk!X2Q?$(Y|B_T_O75|lI5ea6=S~NZkPRG?ktb7y{|6dp*TMWH(JC< zHh}TjT_#P;BeF~Mt}mzC3QA7L_GTz!^yQzu)CdZsygY-_bXcL0|H&tOXB-~+1YaH3 z#6;GeOgm_&BW!aSlSkVS?w;2!RwJCPhfA^kQt& z0j=p~^SGw1iIv2}&@g5ui*kvK7?JJ4xEjQyO+~=;9R)Jf@XriQt_{Q1jetXl9aI6$ zH=$yU9|K~8$%b$8iA&ai`rs4wne>vnOv;ozE%Gl)Zt;v0=PPfZ|BqTkBy?)!*-dDV zEIQC#u{GMeWP;fC5QIS}`YH_>DFqnj&72cG~e(^2a!~rsiGB z;)?FowX!54+;D#KkF|NSuH}>9o)W-+n3sW1Z3E5-Venf{=jl0yeg3bbKis{)5yq2@ zj>fp4KH38L(BSBE+gJ*Rlb^{6S7x&Fbv7{>lL2Zi&e$NH5`%&97i;~;tYA-<;9NW- zg|>$zV@m`*9)-(ou>$}y=;hQBSrI+IB=Gix@yP~XG65Zqa5#trT?gKmZyU~zFCsv- z^+F6|^yhqU?c$~Rbc8cd$slRpyflyQoH>h3(;Pi~`AM`t-XsBk9?a6gv@uv$fp~c3 zIlUV-<(zdAcKhNRkPHTiZeaaQ+;vn&&iSqWMP{T z#g-*q+h@U1CBDT1f8SHQ_nmS-FKeSt3Xiw~U|VTc_5nSdL$dd`2XOe$h87>z?DB7a zb{R;T>+ci`3eabxZk;W7lLs%(khDU~yDc`Z>Rprg|TGPE5&-7_M+C3E4e zZ0L!)z|Yx2-8nhCnCy!9HE?x2rLX@?qm$d&u3fs>VcC#@HFj^9n7=%=r$-VZ-@hnI z?OeJF=XUw*d>&VQV*OKSlN#u&2gF>?UzK<{x2pXnY;(UHJom=0(U|!Rm?oN-h z$m?jT^90*+RK-EF0X3x$Oh@5^aS@IoIHMKIZzY21K^A)UDlSd0ABUBFd#`v}u-U&Y zGFwU{6*Le28X8R;@=5jbLMgPO3&;DG=tHP^6`MYBT#7WSnvCd2? zLUjbF)rND*4L%m&3n_SZnhJ7om~l$HSsX5*Lyea0fKOsB!I{W1!wrJKN*79zNU|Jj zcvq&+n%rL~bMoiT6?s<917upsYVlQ=^=JbeLk&|VfQ&KtrflqhZfEk_6gj4rz+#@a z^@u`~-aX~`{mK@2KU{gNiQA>=EHv5ZH%*)E%%|?D?$$e6wR*f^9e~EcDbUq z%M2~aBbX>g9zPFPZC4lAU{HwJcjb?VU?2{6`3r{5r}*jOQ71)ZLd76&R=3v8{-fJS zQd#{$!iRsUyjc%0z@YmrV+iJ^tig>EjL45BU>$la&d8_^PJNvf{K$Gqo&cMRH;}z= z=(us_r+MqUV=*c7)crJ4_ti?L<&+mcm2Jyz2x64sWuQ%n36NR@Cw+X4_*!=D18D3oQbqi{L{`S_O#^@j(SrTd|jMgbbI` z9fK5S6dRHKMDrr$KefOoJ{ba{bEuSvz4y~Ipuok?aDTe(tzVUAX+pv(99x|#n0ZwN zSfUxQLoDW7ODrmHB{nMX9tDyWTmj$W`BvCJHw_)!iu?R9o^0ATn!CHxN$P3BXqS! z`Z3%rTsoTYXQ|`cmNDhl(_W7KlfCF0n)26 zrne0gFpqO*CW%)oz#*WV6&>O*e3{JUQ8pSW-kMx5?k# zHYnJ)GybJe60v2qaU)>mr?y4i3}t9MeKDJ$Q8C<~Vej$x`&8X4H9?@d_(b$$ z|3;mY_@nF8z~07NoKZ=O;rmq52b-P0j@hxq)E|-aY}p9b?P;7Pb8GLbN;puOw`iz9 zemY?)ms-;qBWD@9VjDoY&QX3c;`S*GwKZvPsU5W?wm9a>zQYsoL$=$!l4I zJ75-sJ(`Vdj&CX_xGp0j;dI+QzAOOQ5?>kCaHuVC_6}+&*liRy7;SJGFMi7QZt?QR z5Pqrxo=?hL_aEdJC!-AQurd=1BL<3nuM*^0_boLBB!3Nw&oYD>&5t zQukh~>%)**!~?Bw57-_Do~-{4Z}YYZQ+*w84s-L?xt3e~o|{lCnU#{Nb_pm>fOtM! zJ1{tE+%LHCJI%|9E3OgOCXs2efc&O{_CG5NAx5&E=@O<+J^}_eDHsFZu?-P{V7!gD zjdjm2kKZP?TxY|(tMin22q>>=3zb7`Ptw;}3B>$s6N$lw$KxzMKc_U#FB5686L|j? z5H-+(dI^S2K$V0M$+X((&gy|E^TQbYwK?_L>?bX&vU3pI|xkAH-T4 z)8o@;2i@w!CL$Q-u3-M>)S2Qvc}tTPhpJ-2e|=ulw4(4i+SKa@HWNrW;V(0C{K*>P z-){yXpOQ_1aRh*`F`&?8Ve3J3Gs2Y_6AfHp?RPM@Yn-fVsV|De$gUlolJ?t3Tl$K| zYlwG4SD{8H2^ZDyyU_HNy&r^IHeAW0t&_))uqR$$KL@xUVjuM)>udH4mzV&@8)O+! z&w-k!mahFkJ}DmbzVugFSl*ve@FXi|2>vN+ zq2(_+J6gri{&Vb<2A0z<$@YFJL|Q;~L8)|N@jgJv8x|fVk@8IJe8(k!sOE0+an~KXM z4BnLHs~OxToi=027+V%tRz&hi2E_9--@d-?mwWn$LVi{Mym33O_xddXfd!Y#X#DzK`gyLY6%$R}pljw>a$eevgf~E;wTw9t`I_RN)}JWbj~AJ71Up4t z^&Bt3olRxLx@#Cn_3yQrcc0IlR9@sYXfA`V5?z-OEfY%w@va2TH!hZ`f2!Zo3b&o# zr&$vYwxnS_>jNBp!V#?oKn&1ETep<0;Ut#XdfOry;RN8J)}D=bCrEtiJO1{Y{(3t>PMScU9K_ zW?v9v*b1)}P4HxQ_Y3>a{WlJ_Y`)oYM^VJpkc?!ZTc%>8|BpEw|3ADy^FL(Gqs0gp zohwz{b5;q1;z*{_B6(H0VY|tjfuXi*CaxvQoL6o&|DWj-{DEnC=FAgNpQpY7;ac5w zLErORX9l{$8v6gCB;3bcY#*l;F_IdBX@kPx5{MSJ#bww{JTpI^9yF{vWW0JtWDYrX zjDDiMd>L~YE~x?evCxCnBS2Q(N9ccfY@v*L$nE!M*_YST_APwU=KgpECW^w0>@o?f zM9@Klo{xDts7GqgvuGVy^z#=)NQVc`ZXjxLMA9&JSni54a&y z(enhxU2%f{Njj7qfVX_|skgHixT_t;9Y~zDHBW~2{qK#nZ2QH3A7Pd%IQzIVL`RGO zT1TM0HfH=!yL2PM=c!r5C9)#P#TBT7eUPDC@#%TQcZc-42Wt}^Zp$eq zRS~fbpXo2_4Yl}| z4WtCoa$kkBWKIJ>C1~S3VpbY8)sNhArprog&oQ*SQ;V zNl)z8xIL$WOc$3b@^`scJW0x%X_!{jjm=YFc&wV&##iVec%*;)zN1RR#n$B_>pk7Z z!C~Q%y>u}Bi~3_QGld)W<|5m-*kuko6sBS?^6liOy`}g!`|9$3`~5nlJ(`el(~(7$ z3!oM0CKYXJfrwJEEOB~4f2ZB=NTXnGPQd+ul<=K2`II+~ThDtB^0Az3hffW!uw;ys zvyhKs*MGwk_-QF%e-3VYzdE=H(-BQ35km@hP_zJs6?1a|ifTXX%5yzbIa;vnT@iEl zxQgYZpSfYE?G`lNVWGK*A3k21?mKZOCJ=0JowjTU$Ad^V3d2N$I6^?1cU()S#C=BZ zQ`hw$a!Sd9Teg>B7KEjCMkd%x0uAs7y5y+S7`%8Jlsrr+y?%WjjKSh1@ zdiC5-FTpR~&sel2*P3VnN2_mpY_h~Ga zD@1YV3n6GhUVSO;PanpZ82<96_gOor_<9NK*D98y1j9 z>{Mm);iy;;8Pn6boaqcH-|tIpy;xbwHL(1GtoV=Iof;;K9un=q06j#8eX;?z@j-ye z+>4K~1-$KVph53<8pMXw@*1@%bRfL#@?QQ2F!o0iD_N!?e$Fy|cQ!m%b-t=}#!8x& zKIZWr#+#v-toS>9gtKeK5tx~%=ob;C+GlNJ$jacEN`0<%@jmmX;WIK4yf?T*x>^5r z0I{a-pjj<36;l-@6mswQ>{*Ozzu1FE+Yg>7S1sF@8M-DbOPWXF!B|KadKSELwR%}9 zLW%cF+W2Rk^P~j<%MMrOKibZ`Or zta>OQ|ATi2w_^~IsfekrtgjeG^U=@1zVfv8mg!!Mix&L6osm*>oFRH*4m>U=Z+^lQ zCl8*=jjhh;5Wycxq`CluI9wEVr}0zUifLFSBg2sV0P~V%gTN!DJ&F4WxaRt!{jv#EF$2N%(v=Y1_u0PBdnS?7e;jdz~I$ns-^am~jnDIYkZK5_|ZUwOy z#U6@rc9%ZJus~zGJpC^+|NIP&d+}56A6scT_yMOflEzoRE;J(^ax!_5roupyA;z?x zvxhclij;a6oAvkyxIXNVsCrhyM6IF@jHpGg1aTc+7_>FfR$Zh6>W}KmZ)8o+6013t ztihr3yB=ckA=N8@-#u;CxN&~!< z=c&&2p>c(Mne=I>`BQt*yHpDZK-T$cKYdqsaQt+uWndQT*_?mI|C*{jIj_H5IPx>H|!jO!2<^N~V&-OFD4eU8OCQ`cy00w)JR z*@v$7n@B3j;;v8kHbObbXDCFi72}rq#`?Q1_2!kPatVw?34+_x2Z4S1Gq?*EU-2t@ zvM~g!NSp9zkimOVYDx%?4wFUQYRj|QdFjlSxF8(&b3b#nGc+=ruXwa}eKzLZ7wmyK zYG|XwHX6l^aYjeY-YX{zVNGMQiRM51*0r$|Y!zDmW{={`RU<7dJHj~8_ciozFL-xWU;9$m4N!foKWdm)M_Pck*U^XJ<;EB#O_Bj zxB6}{jFG#}i0)Iz`P76N{^mW!ze@X$Eb` zS!%<>B1tJJyJ4A~Ab`T!qf$0>Q_OeL${nDQ&Sxek18t9Nq9GyZNdV{gTi>rW55`LjxmOFJ*rM=|@hzUy#$z)Y4~l=da$tjci?c zk*ThRz0#SOHXRMpmtWKpTw z5jlQK#~ClLfHhCOy}Z)U;IbZ`!KiUY@i8c9&K#Z+^zz4(I036?5l#|0ytmqwBcn{e6Eghn1X)=+}K8 z4MG|68Zl)7DfhHLFv>1LpQ<=lN2qvrVQoZ|i3Y3wZ`hmOkAC70W2ds0&BQs&Zel5y zy~c^(xV;zitEmqh8-4Y#4=hm`z@*Oz6l%*t5rgrLN;UCW_7u$$El7K_;mOzDC9bQc zQ~#725KT=wyzyR_C;E&L=eXyJHJD{t_OUJh&(irZ?F*k&Q~c-zj&vPv9QrxA?~&cv zQ9{_gf{&+#I8U+8qKf%*CAGi8C0*MFyQO$^JLU?;@qh*&}0N*D-WP|2U<$_R7P$(!am7 zXLH?WZcioAxal2h!&3K|26uM`ZpQ{vWcTKe+$<}o6gC>+&&XQCWWZm9H;SWf|Ll~C z&WUut9n=xlPZc1<{Fc`xqKa)gknJI{?3&_8GRtRtR;mfB?g9fLmm>2jnA zB;siVy=x#FH7fEdI2`<#47sS&w7Vwo=P6ER6TFbE^!xCw@C_Fo`{t6oW5rRh7{XmD zH1j@TW6u%qZ(T8b0BMkQE~B3-bc%^Y1SMrODs%*#?iChO#%x(COYz>VON?X#P+J^p z>(E8A$FsB|7lnCKqH66a>yfYBXi9qdMBbR^)Y~BNZqf<_w8h7d-}op4302B(!%)x6 z_3;b^u?g4KbTR9giTiGdV4kgsJSUF1;Uax8RXov5fAp>Y=VZpW#3!wCMFWSdI;gj%<$V(KB+mpVGO#qjs=Im|U*WF(lE za+&zE&7h%f>^Qy09+S49t0QPGm`soG|LmH|WRPLDn6z3iN&XK))PI)zmYCs92!uqX zm4p>NkNm9X$Z^rCbw4^T*$vTLKh>20Z(FMP=OX`jLCTnLBij>_*ADo@TVIxbomfGx zQ^OIH_OTvlN$hOK*tXm6MY_$4nX-x?W$_@nZ~3m!?6_P+!g)$lNvgHCW8cWOa9T&WJ4N>q zI5|)l<|jxjI#&W+q7(l*|G%^A!1zC8ilg}mvnh3psD~m7B|Oi&C%H4x&Zx4sn%BEl z6l0fq`_j*b&;FaL;eX%f70)EdlRuVV=Fx%=05)(!k-Q=#EFs5+J5gq{8u*LKzf=~- zzo(=CZcfCHOf0aS<1G~&0AaY)GItgS)W|wTzyRNn(%-AS91G?GXoTIUu%&9p4peyH zjRb6D#e%rSSOv#R?#m6~kB8klC$GF+C2ZNWkqmAT(@9UD0!N**UR#T|Cywjsi=PXF zYxum@sKC3!2^qzu_9s7pCjbH6Xl|k(Ym$U1j{>wb*gc8<^NiNP`XBD|IwRG}ik+IU zMr?qT15v%eDWNsD-TULtn5WD?2jEh4vjG*^9^bfE9VL0MM3%m=N7AT=C%~Nx`{leq zq!!5o?`yh$k%n;sF>JvVDpC6QwTorajqKakIThzH5G@;dx=WWmX;8{fI$ZtmET{r@v>*9)^sc8Bl1G@a(`MMB60fgyN}C2Hk?T4qg}vXJWr| ztS*Wi@`=9aK&5ydc^{sZ0Bo?`7Chj>Yk77+xxDFVPz2@Htx7yAa>&Syx`(UQ&0JVg z&Qw?^J(5=anx;FGD(rny#~6kx+Xx2&o0em2uWgy6<&GxZVw&NtG0ZeKdQH}c0g{5sYnOqX=H=bLD7hcd?r>+Y}Jhh{xes?5sohdzXFOrA4qL=H{GMKrtQf2vuNRq zT={!!zkAGZ3OPd5mkI_Yt6Ibb50>IEc)d9PmCQMr%0z|ypspuR zK5g_v?yntU>bXClIf+9+Wx9QlrFMnr_=Et7yP7PLQ8cgVWHGxnKRa|^nECxk$-|Id z2q$X+N_q(DjTP+z(O5dSwNm89DsqyMV!>j+2 zE%l1EcMBghz^Gu=^wm?s$fxI0IFT3<9HvARlxn}GCJJ>lz=vhjJs*a8?2GF~M7v#? zWn*0o*i78mF`w=D?XuDKFIBneZU{l+q%EQ|Q*5|F^Nl+=d_=T9)i~2MbKN|7-iuA^ ztcs_eU@h8=nP%)l@KLT2Q*j2N4MsVgO+1PFY-4X9aIPi}N{e4=c1H&CWU0D7KCth> zINHv#;27H&{PpqR5EaYdY+{i0cyY?f=v4;pv&5edLtih+sVYrnQRYCbO#%yKD*~cb zmu&po1}d*J&RTrD6J`E-X-(|tx`s=pS#tOOo%t`tg4ntXFQVu&cs6LIdN&GNEWR9H zX>XUwHF@AM@uq<-wS+`+k;%o@)bQyKGs(!FC@CD0`A)GkLswc&W_9_!T#$dG-d%Mq=Lotz%S@k?{JA>Ft}iJ78aTJ7 z#&?ms>t=(!^|;WnO6)N*b>q$qjwehOp^bNpZMp}GGYlpcVG#Q>QlZ;j9tsNEFJF=WkREN z@d`FNwst*N=L;R*)7Pi)x*iODPy-QDAtY-|B*w$qZ^vkYEWUguYv%q)K1sE)?Xu1{ zNh6|0ec6p7ZJ8?BGAHu(Md==#(}FT=Bb180#TAB*IJhpadn5l=sXot`7N4de_&}xM zd&zzmFIDlL-=OJ5M1$n7n74=7gs|1C5ZsN)xqqo7UKK~HDWNyLDYWufsmm>RmUg~- zm@!GIzrlJ|HB|xc!h}*3_&+fuguiLF>j$*(?-quI{R<&pW5NU!uI?cnu1jwEYifRE6ycDEv6aoyFkKsM}ASJsgwZ z{sZaHVdpqJx(9Y|h@hDH;C->kDDn)Xp0SL5oS3M+$=Cw9MtnL3%(TM)>KyNwzhir^ zy6E7YejDAbJqPa{hB-4iPLQr-?k&~Wo(1W&kP<}XHaQ~?#E1d05M3CUC*ZQx{_ zm5s^Z+gFBuY?F4H<5wkQH2pm?B{S#kV87ea$QHA=$xCbFu)%`cC!<&?mE`8oACRvd zAK(XCg8@YbecnArX6Nv+@(acsgnOJT_B0If4#TZUP|vCjF)D}3kaTrOPf`y(shhb! z8{*GEzUt^JK(!L&lqoa{c3`+`%Uqx%1v$7^vF3S1Z+`8CcDaHV#$r+VyMowb^CD}t zCBXgnDHwwMR=f9V^-R}o%9+IQa1*Gjo;u)F&-FfE=?@F;yrMeskNek-pc&Xg&Nnio z)8d`4s^%f*Pv+8pyg&Z^H7m#lu3NYepE%jE$I9NS&`lhOR~pq0{BSki;49y?J+tQx zN@?nH#}Y#U$}8IS3MyW%iu)rOBPG<=9k2Y}8qZ0IT65TGsUh_EZsyydan9aXD+CG2SmWz;?-n? zN@foHSx40`K|ERmUxqB5XJ|gS>}kcZCFPja#O(j;Jw(XABXi>8P3c&qeqLdp>qGh8 ze2$&y-7G_|?6|7+PEEJNOTFrQru<_YiqnjI6Gb~6P8Rwp_NBF2H)4%s(C-M!4eEjc zH2u9l*v`{de4XVBCULS1bPR4A502u);>;~Y9hALC>w=58hS$Ol>|`tb28Ru>CMGT4 z{Lq2Ve`}>>n1=bB{isiTKIds3xSp=0FL+xR1;l=JHmH>?Wo;hnO$#!T$ZW~GpQ=t6jJous_71d- z?&~b~vct2_3W_CM(68Q3EP1nnNImC&#JjhQc<*;{`rW46J|BOUEGH{@Uta3=X@@%z zJ_gTP{~>gjRf6WZYjmT}^1!CZy2*rnm}A1Mm3Q^}Ws|_!tB{0{x4wnB)_1a%qK>3@ z-o-wjda0c&RyucjP3`OvT$x&U<0?MuYFPYNa-A;Q1r+gufEeEJx36@5tGKJRIuaszE9 zX{}bG-KQf+%=nBso%84hnW%`KEl6-xc3}}Xe32&}!dfPmQ!->4xh`~0 zmr|cy8u@?hbp4I+W-e=?W}D@FD&gC|RQ1m$QSIJK^wF4bm0_wQ(J#xvo)_XHJI^o| zvwWd_@6jD-qGVi78H^q;eE!faqFqb=1>9)e;+Z=5bO>Z|+zn2ve7Vb{rK@lWqmOV# zR=I$<8pJ&V>LvqJl=GjMr>01ERSSeDeov_-d6D7x_>U#z>y3>OhWO-N+qaps`}`80 zuJT0Yka}u@UHf)@z|3<{J+r#ucK0hCMPW>VyPtvVl#HS~yD^AM4Xy-NtY`#)^T#T0 z$q>n7ce8j3e^En+MjJbifOv2W$;`?*&9vRwJ+~IWG{Bwnnlrfj@A-=dh&d_Knh7`? z@zz3J?m#hcm5dIt@ySQvy#P-rT-kdEV>QL7~OOo=8s3WF_^9};R}ghW@#(+#qxYBNJh7i{hHF{?(eAssngDv zaG*{=wliOzaOlZONLz( zk@@lG5O(6uiF3p&cg43UC)kyEZ2Sp*SzWkR;iy+yO{xXx^5aQ)9{~Sh)ZMdGv z>uKrrml+6KnWd)CF%lSY2QezV`2fN01zxI+r22di_wtKS*`if*89MEHZ}d;q^d{q- z9orJXiGsU`R1+doCADLi?1zhCEWa%hQ;j4{QX@@ob66wbqL&>W^{5_JSm}A=At!D` z8bV^Qy*c5u`G5t*2(>fK9P#krcHfoJ? zSiZwIamuh>&cb$C#&}GHe`j?Akq@pouu{xu9`&_iIR)@y|f8=pOmhf$qqHEc*!wcqQ0-N@^j=(Sv4K|bJ4hW;^SHX!yZ52 z)AiDzmZA&|TJDN~bM-)$Nw$$EQcZ$y&wopuTrSBc($38Z>-22dnr?#1(R)XP_&)4o z;!f8KVp4N8GH=^tc;4loNrhW9?LBLSIy-!(Dc(aC?m7Kf?rb243If0-4w@0vDvC5Q zJ}Dozn(kn#svAey)8``Wk1jq3uLMr@VyfsUeFhq&#+Z`>fA7YMR6PbW_4%uhTyK6sDWNY+szi1TNkMEqbFso+RES~<;Jpj*w zk2Y~$L`Sq(qL|5&L_OTlRaZjAP0K}_7Oy&s{%K{$#BJxB`&Jhnmy6zI5>Jsw45z( z0o7dz5%J_H7rgW2J+FD-K3e&rpb{LlRF%J{?T%$+Buf}j5ep5*WMBu6JovL0x6`m=*BBL&A~5h5#tS2qu}Q79+SedRi%0+|Yd z?>6}n@D`tnkx^9 z8OxZ6I;l2eJR)Lk%;$*?7An~gA^mIr>e>=zc<%U@&(bUk>mRSeHwo}kZr7BKZ%ihd zW5<4+IgCy3!+I{(dO(ZC68*cu#s$!N3N3%3bJZVWh#`Te%(7}a;hwDGb$(23#V$2z zVwfy*0SuV!Ff&)j+Sw4)dw-D}(>wm2^Ih%_8eTr`{VFr1vhE@~(FD zP1qCS$J_|8n&UR%2`uTEVJmi+R+!o0{(Vie-S>zp@SeUq$rPqBM)n7VN;Zg! zpd3$_Z>J8Xtjl_BIt2fIkREA8cg$oGKIaM5^b`?Mv^wv0GrI>W5Q(9z@A1P`cSkcoWWx+ zdV4aukgh9Rqj{@s#C0)mmqU--D}XiP|z+a-pSX>FeUhKTW_QD{Hh0a(nBZYP=UHg#CiD z4HD?oRygiSx#EsIwyLHK(##u{PTpq39+Z>j{4QMomOmk+wheJXU0P4Es(*7g!gdAO z{7`n_+IWRWh8&=KaVmD0%uWZpHX<1WY?D5w1_jl@WJOCg$jZ7V@qC;tE|IIhJ zSGbRm*{Csajw^V%@U-nDX)0~vn+l8Tx)%HeL}3Vho+br$)_=LuE0|4uIcgcNvYP2f zpGmqFj{%Mjk#oYovx(&!&dayz1Pek=!pnm^t6P`*e?W}CxRV)E4GfTJ_H0Zf+f9a;yuPQahsyGm}bBzkzu$cei$KMr_ZA(>R^M>;q z>17gSzjh55{N!Tx=^~okox&iNGjNBZ>{2Rzk>2KKa)@VbXjLaCIBW0G|DJ0;Tq62S z27ILASbL307c`aQ?xNdAAKWQ~^{<6je0M{>B6cIivCT+y!rUq%G-WSeC_Ps@_P=2Um*j<65~^}%eGqJJc$3YziHjfm z_EkaY5c+2C5fhJm;2%7lJ4vHw;zEDw)nV*g?H2+BoWTMsBpcqB!#wFxq2;*!xz_>oNh zxAvg0*N+>ipD!Q|qS5Yv&}dXF2u(M~rpoE4@GsS{cmj0E;{2s8g3Jtbiw_#(MhKLJ zRwd#)MJV@BMl2h^*Hg-8+@pC9dAZ1Vt*vtUZZ)bpMHM(>+BC6u)_MIZ=#5ABw?Y-# z-UiV`QiK>pn+ebinbH8EqNo$d{VS$+>V4Q6D}-Nz320XF(sigRQ`Bk{5&7^TSS3>ST*BPTYN87d^4v*&lf92bG5?il%_1bg32_+>3~O1|~)m zUEoRzRr$b0X3|PZNMoF6J_JNzKXe=52SSMCWDDC_Hr$O7sE$taC60N%LzOzCcUbth(xpQ z4WFFC_CWN~0qIX*37ahj3`kR=tar?i9dxX*9%T(8YJ>&y$x55v`aQh8}vne=N zs1}rgr+wpJDjxI=bi8-d7YvJUXmEVERNU~H-Mf)woZ)9`FVJD0CCsnt%hOY?e;$1= znd$)(*Q`N2*gn#%(s}YzMdJkY;Rn>8r70q=y=(P(3q4x)>;<|_;57eP^Frpv03S4r7iZ4<) z1JrK&s#>Fzh#EC+o{?5CG!h!zT z1+Aqs<5&?JJ4Jo-Y$Jus4s}^S7S>JDh<0k`{`fg0lX&KWgLxY(k3D9j|8=|Y^q7=< z_=W6Kp?VIEG-_4!5woHU+uFrIhcy&QS#LXmPnQFB>O(!?z~PC;Fm{obp64c>ges$n z5%Tk}kaz7UkPP0~NIgJsXz|`v#xd3_)q7NBRxu9v9c@~bKS|)cUf>uIxuhw1hazM^ zYd1ueQjR+;P6Z4lrJS{SeBSRuKkXZ9QmR}%%{u-AJztEE}-iqnqRP=6#5-1~bDKKydw&rK)#o2s)m|5BZH1Q^30-)~=JaAS<} zI86SQ{#JY70&+58W7`5&Do*v33_%+@Th7FBDj1D&{f{kaa1k`@-SF;UlMZbr5uUhncH41cBwCeqNn)8 zo0`TT$EecEAB$z3q@Qp1GFo(GQ7e$>sdMAbIeMLY_M)JNJkcbpuJ-AX77g}mE(32u zy`mD;WUbCLD8eHTe{i04UnY6J>>|XNzkS%2GxxQ5{&BZ1#rSLh!o6+eccQgq=xlvc zgD|<4<(N4rl=xgwf8cX4@h2lvd$$8z7CI%?a;KdiSU|$JdsE~7vUvFTJUFk2MB&0K zZ!hF+8Y=QI3FUePH$DA>;jZ)vS9BaU4N!QitJ{T(9!-t^K9uq*GVJO(vklCx@zWZt znANe;=epJ*4>(^x?+1vdQvcUpR(qb!&43(KSM+f%4rW*MYvDY-hzF%UOm>*cNiP7qR!!Dr48Bh6b1efo?jzpvYZ){|Cn6xE#&q5Zcijb~or!wwSVz zMFbAm15(DUW}ozZ(3+ogBuf>}$cly!=|uz6K&ny(REgZwU{_~akL$DQ@PcU|>o074 zo$AlD_=0`1|82zGaB!Sb{RTXpE@Ap1pG!7QU%xT&9*1M;ZDI>r!-Fqai9Px3AH5H1 zl{Qnjd*z2iLH2I1zwEs%+I~gaUr756mznTd^BJk0xKc|zdRN+6r36cw*O_}v{Sj5H z?MjGf_lkm#{A@#>y`!)4-h{gB=Hht1kG>jukV~s=$rpkjT4C6TyWLPV>616&D=xZz zX)dIF$?J&%k8EHr!szW;V*mYD1ZT@{EZlQ1em1Ur`risho%p}gM*g8~7HL3q$)`+O zWK0zD`Al@V(%L`bk0IVtlFMr|7KzChz_4EVTbG zubQf^_{Xc>_`7D^w|2iHz&wJ~a6uoxA&DXOn>mg=&Vx>TFl=91?BS zygvIX%EF3=rc1-5ftR57YSgW%r=WYt@e-?bNKzNQzDqdL9UtFFpkJwOD|TsXv#?m0 zpX-)v_q<+K6mt7tDsXQ@Nb?Kg0d@#!E=y1Qqoz{$o?sHuS&~-O^yCY{8Xe^Zla%;v zuk-!vck$R1G8g`xxPt|Xh8-L@aCGZyW7iwCB)(aW+vdV6vlQVJ4$H!HrK> za|?(Agm+Weh>vPg)-8B$>pB8^__1=NP2bC=SV03BW%KWMXi1p+u$r6q zL@IzI{Bbbu@%O+CS-FVRtlf$Ss35zDjY z*BnrHGwIrqN~42SDSI>C!}vT@Y_I~^l+wufkKK!hi8Tp+13cPBjT`FfPG8Gynog+3 zUi<33e+p=L-zcIiFrA!~;y(ynew`yfv8%$ufXZLjxztPPep-DNtbZG&z!_ToPsy}Z{B2QCV>svHZ3 z+!;kM1?^_& zqbHURd~d?j6;f*XEjEUa^Jrsum`?yds&(6syv;U5tS4C*ttk0OZJ(li2+q zIDQgK*_4p`WcRD$Ig%1yaQ*rcSCKI4Bl3R;wX*>NS+vzN>6K>7p<(|W%8?v?z>y9o@0#z3$wQEX_q|tbAg=Mc*mNG0l0SGFoSz7l9`3#zp3b}x}lkG_AUF8Jm9>@2?oY}&(P(qY!QsNowy zN##|Zn3w-J&Vqg_%1P}Hi8AQC-aOPwP4+LW4ySZFXClAxAHkR^!c-g`{k<{TqLNj> z)E1sNsek$VsCQ(vd7UsHL1W}7>a7FvGz(N@dBUc^+cTB$8mhYtKdB?F_9NzNmg(ur zL8UCkm>l2y<(3yvDzn5OV{Qq&W><(t!kjm`ev%y&=()6_4+6OabN3f$~u>j z`q!t|`$<(MkH=CqsGhokb|J*smVY6cCgHe{!BB{uQvYH?L3!Rcemzpywc(xyn}y(a z{`d7zuIkkD z#LxQOG_K!-{}`mmkjua>&uF5`=~a5BzoS_F>2v~!yDR9`Y(d_2%j_t8a#r8g?AV-q z$Gih1kYSSDwB9xauTny=>RX)EdW$R5Uz+a~4Swldg;Vc)DYW0< z1Zq18XOYqcD@J+~)){lRF^#nz^Xz~f`Hsyg1l@Q9sZC`=c-L}7#sU=9;?(@S$_*+U z?@Vqx-U(uqt!-sabZWIkw_|E++czUyI9cBU1i6rhgp9xHyScXTUNRXooBLJJm#Eq6 zmJrR^D6tB55BdXMRAXXUc^plY?mCKeF6MDnD)UrObo4dwlW;PSePCVid$#zwdjnKy zqTH_AQLU+wIv0I9b9$WIT%Pf`)G2zvuR_dX;d}k@>UFjnD+%omk8a^lB5}vHKvp$w zaDLTxcz*I&2gd(bOy}sTwXgtvXusHCPX6kzJewCc#m={+0K5!YWH2kwij97qBgG!B z96e^Zk)NsU>Hj|J4$39(CNfZ1I5;|vDUSt2I}WgsNXusv5?yhAa(QF?d%2mXFOv!H zCtCiDFIAxdd8s(g3;3k2ly$_W>Mg^69Nix8KQurv0jzWApQ@B9FBtt%b=~mO_e(9~ zSQnhNnAwXKTmGCm+X84k_NR_R(e)QQpJ17=qTN3_AAS_GGWNp2FWQ%<0HvDDtq!ia z$H>RysN?LZ+BsS3lL*qb-H2N5(!IEguS5gqg}P~8`z=r434lU5SfR12-`x4ml;3${ z@U@f+R9d6ILnR@s`-ShHAgw|<{nWFTR_SSe`;4RT9AlGb@?#;vE}Ldc`vJZ!sC3b{>p zvTp^XiCag%z4NfnA2!gE2sY-Hv=WXo73a8s5KpE2L}l4}UbQH+4$PRzXgtdTDJ1_Fm_)Ieq+L9H>7O`963GGm;0XN@hMsac9WyzHKR3>WT#q z-J@eo);>zLuTTOWj^`N4QiuxsUe(g@xNj#6YXb$XDDVehep|J5J0>Z!hQCuwAD?j-E^8c_pH}hCh2$KRdi$3Cq}pez!sp{ci-J_$PuDtk>oo}qfuwWJ&A*_ zztNt4Er7TtX<7W^$a#HvLpr?VCmIxI&)j|lbQS>Q2f&xSspV-{gxWCLPcB(2(`4Yk z|KdZL->i3{1zrenYY-1I-j*y)F||^JtLhu~FX1 zJ`s}KgT#1zDxjwKy+4P7l0?;aRMx*ROg&*$H5uj0sPjY8BTaXS`3cp67sZHI42%xT zpg-Mc`0hf1J9M<1UdRYE)OjjVnHp;4ODVAnyqYNeJG4yvK!$ot;VCuh`x}9^xY&D< zxU@nM5Q6i}+%M?BkIW1f&B`?z(O>kwD2Bz#?Elzp#r9T8n0Jo+9F80=QE8&I^KZL47}J)ir-Z5WdL=u+@rX^#LiSk%xP@# zLuv{XHHPzoCx9obXBg3RN`^=dj=Mi%6YK3#l|wh|BAt9HbmN#AJv(cFq@GHIEBJbr+)EQbkGig0Sj9+MIT{);6IvVk-Ag{FQQ6qT(w0SdREjS=W*tq_Ry^O_4q_C@-`q90dgwwfqe}Rq~_Hj89 z_h=c@0wuJ{*+#3G+H_8{j$Al*#`tgPBe7+ZaFaYXICdXXY2jLfOU}PtpIY9#I%$~S zaI`@)g=6?`_RKMvY+_6+G<7edHlo_S0l^b%e&6WYif8k|rw=rt6z@=o^j*da)cAWK znCXakL+zmwU1t`nL=Wp`Ov6ShM|DE7G?w17L;w|Ofa`6Hc}_H>uZS`(lqC3WvW{NIH}C&`Q^l_kIR#kFC$$r{vXWOPrJyRM%+YZlAuFL3}&5jyiFCVE$t9?TrTKC?VIJM|~ zD(0KG-hQ3*kLhMfJ61l&!!D6Hc!<{KgL$ra^eV&hfl;8cygnJLDas*bm$+47h&4mwqgt!G`|@oSQvbHJUc#1&fkEngSo0VVhzy{ zreJ^k)`5H(jE(Y%S%`PZ6`gH1XPR7ga!RJVflzg&K85ouYKYB)IA!yw2IJ?cIkn+s z%zgD&owwkN_Ean?U<-I)Dsy1HEhzMNq-Wc9-#>f*EOuXFw5m)7GrlXCtd zyc$n~?k4YFf z?&X1~M{Drfr5H%p0VV<^#e_D|T<0=3g-(RTclTZo+#(rD9@jT_90wn)KTuvEt7z3x zfR>Y?^19mLGLN^sU2bZJY{*OR=~gW5@Mrw0%|8w<+g_{lQ5SYknsoPMJnT?LJpzZg za?~HlX{bzal0`KuTZdbtF>mEarGpOQ($ym3ZD}0Fovs=xB>D6GGjeVCwsFet-OeTkL^0 z^;&m8$Yul>^!HXMxZojRO(q;yFGx(iSygfKmCi>3C}ch@Fz0!IyG-pq6xVafIyKDN zXUUUM`;SAW&nCaXrRqu(C&P>RaDuJ2Lf~V%6J%3C)n0X;iRHzFF^EvZonf0R~^U0J-!&sz5B&g6TNAs5$Dfr6v*h3H7LH;kwT`N+poQ z+IEDvGF;fhEk}o+>p0V#iSAM-#@>oFMqd5(qedgAERr?L@UwG8ogxn)J43vnv)>nwnj#3 z&8Gh8?Bgf5k@7=K1QC0*CXeJ0>i+!6C`s{2lmWHzPr@I!4SZ~HBR!k-oz1(Nb9SQT z`pS^IloU;^;}-SisValILGjhkOWd1IINRSywcpDPRaey!R`-o~&_N};S{_brD$y<| z9IC$|s=4@)$BlUW(3-8u&I9`yLgDmCNbKHKdqNj~NR^U`4PJWGwJGji!a_jI{JNtd zOJVySUg=Y+jzr)DA$C^Jq-*K#VhRHd4BCt#0(5zavl}?#noOiD^eO0!53+Q{<}t+? zZcL3a)Da+#)M(#aQ}C^S0h+vYEki6x3FX+o26xR0Hd|jAO+8+W$h?~DpzLZaR=uR( zM@5Zcs!=7xI9y_bb%d9B+l}Wjt_fr5VaTM6L;EpsQYecTxCF+s!O!Xlxs#Ll>{wYo zLiRI|X1U-wZ)qZrLW?UXL2$2FBJA0xo^)nxsR9zzMmXPELb|)O%Z2U2e<861L@Sp_IKC_ z{|nQP8##;>jmL;JHNpJ>R)p$-JQ6%26x%U))O}E@@iX75RVCk7U+!PlwV~|ht`}UE zH~bx?%Ko^D4UX^XXBmsDVKg0*)Tp(Tvy8_c2dE_7jkqW7?pPwlreNULWEXT7m57vY zra=n?BBuX1Q)-gEoAef9$zoXE7+=0z<&IGsu9=qFGoJUcG{Hih0NJ+RcdPFWILjHX zz@w)NDAhDa#OdJ3pL1f=CwQl!4Jpa`ud>1kcH%4rWY!z%REvs`j>&z4PIgW?jW0`&Nx4~%`Uaf=+dTsOT`;PChZp{kLo!4!C8>1(}=s%H1)T)@$y zqlq-(@7HS^e$=3^`7k!sE1S`?TWJSLL&;9PiRjY!JLq4JE z2RVsSJe`&6kT-i$GA&ifdk-5P?QF$-SJpZjiZ8=&)LSel%4wN~oiTm!wK?U=|DVe1 z|Gg4vk@;xxEEmm*BSm~3pPB@+8`*J*ORCgzixkkbbFS6!FMOi;atSz82S$IMBf^s~ zRNJfhxb;zDUPE}TJIOPsRtmRV3sQx*9WyeR9egfsui!}b6i#4c1kK63NzEI}+>G96 z(kf_GCUf1EocXeNtNGforRfUa%Kwn~W5}W)R58#!)4*Rh*t9-+S`@x%d8}e8}{b8!6K` z6Oub~4`8R*A`~f4?e}^njmff&7br6jIA9h~>t66gTzWYxC_2Wz+9uwLJzU06WE3gfae z6n7P(Y}OY~p6ESOaaGEWdMj<7dOfe-<)Qwce;l=lZpf=?xAooPWwtzCjpBTdc7|S~ zYCGegud`*>bGZt8BBt_ij3)P4g)MoqHE5#*F4VpZfJZwj0(PVz{ByWXb-16g=qX2S zcT9K>AEr^~$%mYq>O${|mHSv)KpDdn{qu%S0M%pfKFxuh74pT{W1@ztoO0ujULZ39 zzjxehi0pp5OJM*EPr3V1+4ADVnpCa*frW_*d41J9+A`GiOoBE=Cv+l7ZOzFz8ff%6kwiIGsBvUp{Mz8}3`xnCMN9{V1CopN4SMkzTMlrg zZkti@3H~z*V_}4y0MWpH9x01n9&KH{yI z2-~*)?ziTg&U%kJ$<&=_xg6Yki$>4$f|d}qLk2Ps@6}UT<4s-i;lQGLs{(6&{5HM0 z9uFONQQ1Lob$Tgy*%A1^p`Xo)fh_q8iw$nbI(_Z#M8{emGVTj7*vS@;SR8G)rO;E3 zF6sajW!G1(Go!%?A2i7}CwqJX6jS>872}PyuPPdD7=E7ILr<*{x!<&?0TXcU;F2zS z4yT#-_T7LmP7~n-hz1oJR8`Ux`A!ZD>>|-#+w+}``SyK?J@aI1elvB} z#d6;#2{~jkSPpX|yn@vvb;73Tqc#Be-#BI++oV-8s5|84c-=eTCUkR7v7(n3$%v-a z>+BY`97oEt>eO*j)3^@IYg1y#*I|{7=Svk))1wq6r8w07sXcAMez5+GHEM*HWo5F` zTan0frbPb@I+6I{h)uaMIQFz{Jj^G%Q zaLvS0hH=?`U;o!OXhlEATD-w*!e@cBib>WyjH#9j9{7XyPDv*VFL{cnSNTLJ(JG3S3Ilq$b6dW zc4g-L)Cz6meYkkuH8i=dG*2?!d3(lTV%Jn?bq^G~zwq9~esh1C`ts;h!zUHaWrY>& z6oFn0&Rf(McA(Q6PU=zPhuDu1Lxvwm*&ALp$oQEmdFIgQNcp*m=vfH$!RF+awq3tA z8TN{4%T~iP?>{zXY4_^4WWrUlzS*FoU)70hPPEupHxKW^Cr8@}Je%cK_>NP^n_Dfv zm!1#H4jpknD|qhG^~IbnyXme1N~}9W9;p(BeTC-M;YR8>d^Y8?O^?~-UCHu)`|{U& zyUmNYPvMWl8WeU)*gW5yv*@O8m0s&ebbUrOHdXMWVL`&rGLBAeI=u=uKT0&)$h`kt&6zv1S(tx*s^sZ6am9DjKPp1 z`ndw-n)tm2PavXq0O2kh(|?eLr3j&xu^kHTX1RMt5+jZ=whEk||4$Jk6#;Er2`IzX zEm=?>X>x2C+{YxO3Yqj#`>eZuTR)t;$+pA&-@UB*{cjUt<;4oQnLw&fekZlEOR#vZ z`Ay@Bber@FYToJO#~AMREg|N&y9uV0&1S5P*4*+58YNVoa{j*1~|Mx$;7A08#SMJX-)_|cGTfXw<7QY0(y&W-pTn&@fkWxsRX z{0exkPED+wUE7@wlf6b|Q@~UtE z#N8MDu0CHqgnC{LNSwyb6HcyPq+Jj=>y6v_hC2FDZ!#0x#{_wm2sFs$ZBv~fl8{IY zpK^QFqB6~&mOt8auNS|QWtO~Ods6jfULz36uK zg^3*pD?1aY@X?%&t@By0eYE$V#b$r5)OO1W1&JrO`WlC{ni5ME<-X0BWA(wQftKu3fj3&WOKWlL5w^hz^#8|rRvH$mKzIPnX;sRx-<6;8N=CxmKF5OE9+ zolWD-%KmRwflt`9BIyc-@tk`J{%O$X=^ULJB7r&C#klwK zAE8zdFi}ibICaoV-ERpoy|@t!dzut85o6SSA!C~lJ$e`W7J4jL)shDGF{X61oE_?L z_eUsy5_dU~`*A5@KX5;k&kv4o;*GaKi6(^N_o0Y=bj}s3_k?_p41H!W_ki{*cs-3V>6ccCiNh% zLm6W{E z8p9s9-iPCY@_~HD+|ak^2bB_|Grh7V^dj-RnWj>{m8PVo7y2^s*2zo{R#uZcL!14( z!Cp$`Q~nQ<7fPW_uML)?pccjR@Tj|JqfUN6=RtCBfT$`;BBICqC^z z+bQNvncMG2SyCqe=3TS~?RasWvs#+;<|A8nfu)iM6L)*Zt}iQe;r{jfS^l+J_wFJr z`Qwz4hAtrIG7PNI#=G)B$X$?n+3}F<9d{oNeb?>l%(Wc?Jqwufp>oeBmXI37PbwMz zW~fKFZJKEQ!l*E`28nR|e$MH9RgrceSaZ`nX{m^`<}q?_Uxv;HD1{KQuS26dO-~}i z(WE00Oa8fg5yK927^~VB4kh8tTaLQN76il066I$l{}{HeWtU{`_pPa=sm9RCweQwp z4N6ea>ZPBPvRjl_ly#&@-8CQfD{LIL{v2Xd!V@t+2D??jY7x{C995+i9(4t1<3aqb zt8Ymja8GqfRyPw)R`_=N83!?|85K=@b4Jd-K!TR4b*|tv;p@}7n0_Oj#x!IQLp^wn zNNB~xVotKv?DUDalR)|ETv)jBB&WpXS)NZqLM};*@*dvTA8290R;W>PhW@(ieB;_N zD}z%;4K*J>OF2FX5!z$Wwx70O->N=)`pCuevBP}HUHMtrYNmjQk#VN(b0mmZ9BI&V z;O-(_P~n~-ZM8x!l52@?S#~+xADMAOey?`0e{sSWa1-&yJO4OF%+`qhUvcI6o{vrh>$=;-;0gsqL7o)`8R9M)C|fi)Amwp7ztlsd3WRsl2G2(c}yfR7HW^pAS< zq#8i}?_u|VtJRbGkF^9XRPYLXJVOb|rKxOFWWn0XyIB1<1;3$_ajCOzr=BImJZ|#e zv+1l=kDjabhb(q^zB_%_F-OQs$&6n}zV$m&W@QE5EmGW_mXi2~P_#ZYVv8BHZXHa3 zh_MAwLvSHwHeawg`($tb(}RtDfW*E!iG%OMm*$dv&K})toOpYp4XDsZVrEclCMWKE~QLXw$(3;(Qi5jXY+B zHel3y`XJKuM!mEwrLfV#(X^@wX!aBH@=}pbh@O7LjX7t=E{Boi8myPP*TLW!ai$Nz3TME9*0Yj#su}`E zrQf4N{Ac*gzM{X!pqyt*4nVWr53x^DH{bUABvg^t=bM9Szv}$C(vb*rV&rfkTp)g?7a1`yz??+iLA6>B;x?O+s=;TGQa(ld5B7%j9 zX)AEIOka%oU~e%BI?cbI&IsXN-_0`(UUKc*?m6Zy(DfW`#JFTud*rA5TednmM7~38 z2CdB;3{7BxTkQo27uDq2tBNuDm*-FD=S$$!ah~w_xwFGeZTa;`26V+e2n+lsKg~V* zHBwlQxMdEGwl9@|HAAJw88DId>7_{bBU(zuuqI_G|9XeUh$i;4Nv|R z85hi~Olrmlm;;>%UyOi`+o?t#xe@G@_8(i*Eh-{rO#vd-sBqNw$Y-!ub)K+}A;G4V z_gW8d?YKy&Sfp9)m`i#;u3peS%?}WRN!MbbzEhGq!eh%U!JB* znQco)Op9y2EK6$YPE%(ICJtWf<8o$UZWX9|j3(gkdOZ)hf9l0zm~41Gk>B$+7+`bu z)}CX-TR7hg;NQ9Q@;GzYYYQ~i5MCwOg8bEdW}+H+X`Ws-mRf9{P?k`{LT%sJvqP{; zsB;A|_L><+6}9TFh}4b1hspG~A(qHnoh}IOthOZ&CAYy(WXyw#J97OOY;PPb|0K^N zwrqG^11ZgbvxjU&Up2v0eq!E8yqI8ylVaHYf2S@uSH`wH9EkhJp(F|DGkHn|bs$tu zwouX(wgYy2Q@xN(3yLKt8n57`z4lHZE7xjst?7$!D{&3|Hzf{!7A0~TxW=>C)j_Gi zPv0hbZ+9V$8QPu%KB(BAV6aj(rFeGD@x-0_R~HaFI+w%~ugqk9-q%}Yaj}wHE_f1z zn?#6+x7HITeEH6v$j{{d%eN4mBMo&)qPNw1t=x|r38*fN7KeT`x35^Z$5Jo*MW@xhamXf=zxc-CjQG=>8pf#;+9mWu@$@t9V zrm1u$38$X64hllN;Np1PYz?9KmovRx`A~LRPXf(f%dC_zZ@pc>G*6S!j}>eX0f^W+ zD0TKjT8>l>?c~5vj&P+YD8|!+-C!Avmb*39&g!5ZkPqXskw(R7K4yliAIx_bteN-! zDB>@(8{WZEbjocEGeU4T{Px+w4PjP8kks8SFD#3@AvQ zK0avD6quq<9b5L!h!*rl4PrQX=drG&cO%JYbTbwTS*TNzKQoL zb>1qaOpB2me-{hlA(LS6qtG@(KqLmBITvk6h4bPa3%Cx?B5Y`r|bK~?Y z_k!Dy)E~aq!&xZ~a;SpW(Q?Q1EA)?4mZ4_crTA%}>ah79bcdPzC_rnph|?{di@qOsdEdCm(3 z5gUsWH`S{KPbJ33TO@Tn;Pxp1v+ADd}uxeV2yvTMGczJbbh_lb*)5lp>|+k{P$7wP@zJC5hU zvGxr!oXY)19VWaM3VFS2?4-jG@+{oXh&!WSBmdAg-|xFz5x`5{l=1`-61L(R`b3k( z&uZ8y$KIgpw*tQ)zuy_8o_{GidHi5z-gMoa#tXV4s=b`=QsvmSBGWx?d5(D z%V8lhzbzd^VOPo?SE>3={F(t{&`vJVaa7rZz;8M#1;9J4lVVB;nbaVaKBo_`^qHaU zfl&uoH)Lv$JeNToHU2)PM8ilVb@*kKIuu&xLtKew9iRX3Q*hUThLZr#YnQd zF(;ZXF{IobIcf4y&#S?XicxQG2d73eKZMVVh0$8*11LG6dL9j;kMkIUPyl?2y8|s& z)*=UuJ>@ngo%nM}*~fsMyvh>$bpf32R2=uOA&7f>@-M+Q5o#^EG! zovYqMzmr0w{I&(_yZ7qKl1@(LV}iGrb7WH-Di!}r{tu)I$>S*+tLASPS9zr?Zpv$Q z=Q(+pT(j?%8<>}KIc{C<_t0!lkfKWhOSV^WoJ~pvkJ!UE2pzgEA5Wrr2l-;%Tz(Yv zH%E;rMj!I4!%Q?O&~J@apEV`LHw3;9&P09DjVFmeB?{gv`o|ICXK5l{`(=jRhdNJV zr_f}&P)CQMXJDOS5Fwt&V>@B~$@fYh{x~J``Eiz^PHiD}bnrFmFwjo?$MF&(v_m+8 z`aQHPkzXLvS?YAKV*Vga`_1INTg1~=LPfvdJW1B3-ImaABUJq3h^~fBZj)4jB`_z} zq}(=G)uuAV)NUq@C(zDbwdAm0)!Cm0Gug8mk^OG$F~W(KqrvG9hMI0t<>&pu6QCpW zgP;9c(2!AVG5^#SIVLSus9xs`#^|e87$y+B^&v zPCR`_<$UE4OXTyFvAwScp->wDS`;vF5aq3C?$m>T~9PiA_G{L+4TF zgW+WTZcL;^;E#F1ZeHv^2cn8T0!c%8!J%>^RJvT;8(|tzc^RB5`gwA=v*Q^|a{;A>!M6FE^hRZ z47TofC+m3Y;?;ZC2sMay$TXQ``UWNL&K8(p!ou>Ezn~zNQP;nrm8X74oY$`H$IFj= z$aU$yk9fy4fX7aA0&X2_9@;`qF51UOCx0Y(!{@I-#fFp-1^7yfU0V@a^rO7Cf`B+mwKYk~>2S`5Y)I1rQx@&H${) z?Cp6oqVBW1`8O`r4knLaseiqF@2>(Xy5Y;`B^!C}a(%J#`WEb#Xz=md+tw1!gaX}X zoCn?jf(BxsZxGetzW8|;wi5Me)|W?WH@Yy#!z&gS9y=^^vUZ$IXBl;y@B})Bk9n0Q zPpUxP1R}}(lEmKNT*tb`@bkB22=2>xErY*zEroJgTdpQdQtsbh((#Y|3$IQr;QGNZ zVBQ{6sy;F{pJJ8m+;ICt+I4D7J7oP8ya7b+@1Ip3G-jo$xmCZjhkgkQQTxa~)x-z+ zjl<|T1`-+Q5LCegC=F*!??5ZZn&iAn?nzSky-me!nWw-_H|gjI+QZ@6OrLx1k754> zE1i>;i%Z+sZsaKpQ=uQWz%tuG-p9Q_r30tO-Kg@>8%yv^J6;re{&4Baf#1*KUjB-2 zW#{<53~>MU>qnPV?Y1G4$Wt&nE@MBO;mYL0qr^}nb7J^i$u+wI;7x#6QM;G-eFlP{ z4@n~v5(;q8RF*ebm=>I=2p9*kjY^K)ZOhFf5)eN zUVO!+!6ck*lO{=pBbeNFLq8rR%Ii;^DB;MN^7?8c5){4@Jf_@j{;r+TR`V@&P%`T3 zWt;pmFJ9#-`A;;uojHL$GW#hOJ@|B^mR5GFDf{ZBHBXl1yr@hMOhd764>?(MT5x?C))PxAjIhIp}bOE!4DTzaLG7v-|;y)K>m^G)-?U6f`Q z()7%rPDl<<^^x%wE9k@2(_fpC`uW4?azMsBL~0cZWhJuDV?-e}7>ao(n;Hr=oLF9iez#ypLHYBS^*()X;d0&;>eq>Ml(S;DV<6FO4 z-xY9jQwC6iGdTDLle8emT*;)uXYatr7z!E(rb^HpPD&SKG`xN8g%d zns|URmRVcF#>!<-4Pit)3Bqbf`+qRL7;@UpZeI9q_1i=;Wd#DGG~ z?T+Y9!bzQ5iIso4>t<%cKW}1|J|NQcVIjX0F&B4PqA^VK9$JX5k?1i9Wp;t) z_fL-4JE&;pvD&d6f`F%~S~2xH|H-2Z4%VMQjK4FOt3;r=P`_-2Djb%5pU11Vt_}N9 z<1ZMYm&rucIP>Z9@rRU&fJvPN{2E0Y$U%lUyC15_N>zu5wp5o-t-cTbDrxZUQPjLG z*mtsd2J(s4A3o8LKI01WczrLi(Wvg1bVH;gOwz}8Kovtdqf0)vH5Dp%@HV=A8RZOQ z(RqNpc~c1wlp^Z`>LSRqN+Zf(85gqEJNuK;d!C49c$X)4y-7+t3w?l=po7D33f&-* z9zL#)i(%{1%xLh0UBKRcP~vJ7(^g_m*YorOPl&uJXl;M{Ip_6T_M- zk!+E$55^Ze+V_Tv^AIXE!R5V_gzoYv_htF>-cud{!0r}i-MByXN4M; z3cpjHEyG-K(I61YOEoqE3`r)AXK#5b#AR%IVlKd{j9jipJuVG#^4oMs?}A6Mg#ZF| z%^dI}-}z`u;20hh(3uG#YbD-nEFYZ#S}4dxm3UX^#gK88NKA%`LZ*3SwzlfF#vomQ zRbm?D0^A{pmMXEO3_;8HkF2;R;Q>FosS0Nf5~nGS9dbCO2RJZfm;x2l{?tFC%PkPY z3(YMqeU<&HPYsW&>?O@YW)I`6$pdOXX-a%hla$fgs>}~HKn*pMjmQ=L z@{3M@-SwXiQ)P*Tq)Ro)ZplD8-JZ7j7Ux0WLwYd+K1nDisW&AE_ucDL>Y4YFL_G&( z^jP*Nq*Aa0K5b2Unx#=dvQfhv1sjn)7*ijY_Ff+qn`@Vm-@uO%b^h!9KKbdazDez^ zxFl9{QIAA`#0P7u@Gj~jn@2yNyH14FQ(4_6M6aSBpu&F+kI>8An=j+ZF7u;Z! z%RwJjdSo%%&+h##aX0<)g<*vHJ*NdG-#5#X(%WES=r*mgmEo>irggU$yW>S#p8z7~ z>(Nn=3Pgu9O=FGxkAosjib3j=di{kaZ$48!6L#~zj&;jJH?_?~>vh*QuFPFnsM_Lr zB7JKz$NI>@qh`B(@i3n4*=E7f!AL(HdhJRRX4j>N(&>ZJt>4~_TeEX|^oP<90$Fy4 zjIek9ahR6~lP+X01u+W+2CP=?CwU|%5mJx><*mPjobTQEmqmH_c$`(%@5p^Q@Y90uI6qtq|$Bp91D zoV3-zyVM3gv|b=p>_BFg=F{Vv481--+w;rto|Vx{R+U(YF@uW>9`nPMga`H};|ckT z|2Q1-yp%%(DGCe`rY%4tO(O5-T&b)Y8P{m{3LdHGxUq0pnUL9l{vS0I-KK{;Z8hH_ z?}C8`x4!}YG4mr|A`IrAjX8Tudb}D1{NRNuCw%QSZt@iedyd72AXCE8<~$FP%sq8$ zx+NosqJpONJ{l8I^!_hR^5W3n!7Al5WbfUEu+8tFS zN_492_b1`-=ha~Kn|Hw=yhiY4by7S*a0x)<5-#LS=O#fzL@%4c&mnWitkoGenAgVG ze9Y^kP^mwTPM%RhFUC_dn07v!yIU!u7Yi1| z!hgeP>w#Ewq|Uvz1#$cD*E4mtB7Gy*r#j(+{c>*g^zvE~mV-SY#Xnj#)0s>#7$q8q zxx{K}h=M6ZCc($SS^Ex3!2L$zOp$V4?W)hAUw_e|O?)M<{GgZU8L8T~UM!-H$#p~h zA1lxkz@{_f!E%etFiNV7p2|*qoVc6*EaC66Z?nQ*G(Y%KIw&>3&$0o})TUW=bz7#! zY6|_lRIlB@-brY!tqj5rT@Snd^M&SwZ(m!wPBzwU;d^oSjIB?g?r+n{MP@@ znjII>Dp2q3S$l|-V`(h-5J1ey%bWIQed#tAl=BLLJz;Y$+rp#ON+|M1Nxg{^ywBdh zIAlY9$Wd-bwo39V3%0f%K9~JDjNvXlms{}h*ber0@zaf+tCgGRj_HA`hLB6B9ylkW zg(KLBafdzR@K9HeOcB3S)fH@SJ<_5^RgR@;wr3{2M%p>0XL=V1#g0c`47;NHHpdTs z=@ZS>2+S^^cjyvA)SCG%R7^iGyXwK|F9>N@GgQu&(5F3+e<|0*a0x}E%OFsl-Lt>v z(UpyuX1KTev~|=!4mXv^X~$Tv0^<<3-0li@;=TWiw)YHY>ks^fb!v;MqH3l^OUC@E@>R8f1cAf&C@BSp<3wQ5W4Ew-Ze-jWox6EjHC`~06*_w(j{UfkF7mg|u7 z%{kxknOy4+`bC2?yUl%6A~#<5|9o@$EPqfS=+AHa&RI)OB|u9OMkKsX^hR?hO?Ii) z_VFy-O5;}CnxS$7z>*OFNAHMUYL}6{bM@)9gYqz$CV1}dbYd(4S8Jj1-XO2R>izWZ z{MdpAwiBo7RPF;JSbNH~*&rKk$f45!+a7#e=gTj#vG!;|cylitRV5xJwR~x-m4i4P zo!HfwjCT1`o)`bs9$FQ+gKOPVB+?3XTRA*`>ZBv;6dau&XRMc0r{q5cemflHH$`x; z6eJa&4Mp=vI2Lxg>yPZ7LLAS}SJppEK`uG8f(T0}*W{n}6%n5b+rF&t#cx3sGd#*U zWkN;n+(7a(x1<<)TNT!nrX8Y@Zt)6WxxG2tn3%Zv&|r5sGbL*r3+@*6>Yei~cXO%f z6(Llvtj77{r#CYAgG#;At%8+f%~m-}B)_iYEv3xD4y$Bd zS~b?w58#zd2lfdC#qVVGNoR#;UeA&h6)sv`K@wwj6yY# znWSmGEq~_l&sH9i*$YZ4z>|cQeRn!H15jB7tw=kO0N^$hwh)BZs7o6sdd5HE3*TME z!kceDEhl5{p?jpa@Y($3ySwL!JC8=HO(sbK$658HwPEbuC1dSei+)|DNe}XciXn-q zX31_aK?lX^gt;S)x@~VMpQs)t$eT6)I$lfLBVeH~^P77b)#pUvSwyG%d!bh5TVLl* zPj|i-OGjvQs{BQUf-koUk+eF~lOu^L`q3s$2e;-NUuRSn0C`T?Z~>C8%L<*M|4MWE zG2X2H;C*AN6|x3?)1~XH&~zC+xBPP#c*4}OfA!l_Hd&Qz@ed5%(k-rYkBqiGRIdJ^ z>r2ewqDVsZr%#M%1_$_ZmeX*Pq)$;4srCO8xbS}~@xSzM`yu)ne;^pCT^Xox`4r|B?m@40`0@?w+--H}z+?p3>k$v8Y*l;=6L(ryc5;GBt7M{8A1@};D~C=IJH^tqWC8GEIYZR-%`d3Z5K|~ zZvC_|zu;m?Gxb zwD0a$N9HLF1D|%H7r&a`#UJ!gM@J@n{nW5V!LGB{Ae{VaiNmNS$`4xYn&kL+PO-CL z<%-oO$KQx*hHo#p4>j5qY24NK^FbU0w0byMdq4NL)dhA~3$85QN#y%S(?+BSy`kht{WkDe(4_1tXGe3b~n7A_OY zg^vU?scx)QRDr2X0>o|tz)`NK66i4^O0-j#0wmkOiF$p&kCX_GYTR(ZbY_Mac@! z8ns|AC0`w!nn?}%tqv?p*<`WVR5)KLu&MJt1qR;k2b#=!3ET8=jo@2eFj5U7TR@I? zK&v*R1dwbNDOEi2A)v@ZhwY2+Hs3GV?R^d$k8v9St$pPg$-h0ZgX1T6n}ppzn&5!m&m3qFgqpN_1z$DV`B#COiX z{l7OzjOiNH#K-5UfcWT&5(yTa*34cKg2dWGsKfdKWL7$?S&tc&iQC24mlv=y#~FxF zk;WB}HfMbLXjkvjQU5z0y`eG<6fv?Aj^45Is z8Qxbmmd&jt^yq7@y+GV4&HU+Il63O4#DNIWaQCqDytdtc#j!GAxG3uPqsptKn%wL; zXIHQ7oH8@A!HC#}E=l2=#YX9otJ1j>V|ULyA3!4;`NC!|?;wvIWk|U>{O{Fj8rly3 zgB+A1svI8#ek*-pOabFk!fJ%;x9^#SHl$g^^YC8Z@6m>P0E+PFmECVejvP95*-pNG z9Ps_N&R?-1cV__NDmlX&ozY_y#+v_{A{kl_=Imn5c9!_I<*_0NyhUse+6M+@ zDFA7>{V|C4SJcaR0j((vojqXLS%odn!`#626esFEzgvjmencRE=7355y=`xOGX*S$ zzt;fIBhv6Ql%R*1rK-{EJcjwxyGp|*5KNW$!vJtCA#-`blmL$6J}dx4QiwJ&Mv@?U z`%ho9`R0GXD>wTSJd_I|2~KY>^)h%BGnPdoVxh-F%uVNU2-2qvNU)j8KblJbU8jj5 z=(^1|U{(+GXh&xHbn1Y2H-b9kC1KP!fzu^xTR#MAqIOC_ekW}IXl`jmi3S1}UIZ?L z2#{ISk8NXCHcxsttYk^AQ3PGa*(ChU#+GA5qw~Yz{Q^o&2o=$`VtLa;B}Jer6v(!b zz^vpTs-Czk7B3%cSV{D5m`VU04~X}XDUZq)y@wdScK)NWEjAgtPQkQ+aSTL@?Ly%8 z++y5Ff&$wUD1=E9wCw9LS^F7yg1G%~~+9oeK;J zoh+G!?)ZIO%&)nl0Y=rzR21cE4V>xRD|iT?osDc)(DYj=l8$E|d9PXa!%mXedvNtX zs^G$=lIsUhdQynU_buGU1J<>`)!}aFh1nw6^y25r?S_W*jOX=(hR_)B%^69A(~ny= znF-#2Zr16KFmYEy4W1-~O4Xt@aIh-CgF3(TgKMVO*+ET-D6;PtvMtF|ZgT)=?f`HS zobX^uWQG!o7-4LR{*EO^W9RRE+3aUIeE5u(I`9(39?XeZoYJR~693UemLMaaUCv4h zKhkWPF;RLnMzXSwPy0lsK7aO_t$+6x8NR;Je zkEU}&>0?`WM3Mp=LXf>XY5nYw9+CeFs4Y2lIQkUyjkWb5OyuF=L^8yd9Psad7|5NWFx2ooFBgj; z&ON~Kyr?VY>3ESq)+I;@Hyk}6vko5?6m;!fuArmjmBiQIQKLcjS6K4dh|bS5ZcbhZ z79g?C2su_H1X!7oA0e=Iq+52r=-c=SS&~uEO@&`hklD^#<*$mgU40E@rvj2n{ibf0 z5;UKb7u<_#fad6z-1uT}Z#Qj-#juTa7#8z&Tnywpa%+8guDP_6vZOk;fDdMp!-THQ zJ-)JlKSJx50E54X{d;>sm^ek4fpE`~P7FOwHYB3F`#(%aGH= znD6ekSH3dEXV@5RBXS5iT?)H7Kq!MSf(nWH#IT=xr{r5`2gW_8HdW z8dUv?{Ln1F!Z;^@uL)g`Qn-)3UPF~&=SXo=g)wqqQ6*=sB34sOCm|r)Q{KFFnWt4i>Zgv6V4c~Al4vvcYnENke~d;_ zl&({%r7&08iCK`#<^o}EShKH9$X7MV;75&`qe7B7vgS#2OU0UBmF^45R;&eIq!b48 zlisb#U*btaICwlh;A~$}(TJA*CTbptu4E!G_JU}nm+8o?#GO@49B*r-Or)EwpTm>Xf~zWP1044t zBC_{eXamTqMA{t-pe?t`a8w$_0^8G_{6RR#tJP5W(8-Bblb|Ww+3kn4Xin?S9Bx79 zA-z|r>lRa1DY_HrY*@M0;;;KD?)SJeTa(Tt&)E^}%E2sfFeP1DJd7$gUM}WCc_OM~ zUp9Nmbd%?;_@6}7SDBr%FR(#%;TQYoeW(~7cH)B^(%Dv*FO{iw(z)EG0kQ2~PEhBX zPvs3-yLkTuQuBVRRj{glB27f9;>Vl-$ZkmU96p&JQltrDR;AZ-uA|`TFG5&ZF%dqT z(M@;fF8GSB$Ek*2J`L6JB@Pd&e(K%g0TzoZ;)Im&($d3W=HTB{Zml<}QGWZQHYtuP zpryHe*zj*{8<^j5|2S2eltdQAB0gJk6AX$?7qvu(lALq?D#x}MuwB0Rj3uS1_(9oC z;bS^V37Pr)iR1M6*6q)6$Gb0&)L_kh<)!ueG5nr9vX}7+YZx^uAEMn1Y_}DQP~*AQ zG?gs;s4GPlWIaz`AtT#mZMP6`)5CoKIBtV;ywWrkT*F3Y`F3nTYC4x9O}8s?HMF!& zNjF*9U5TAc?1J~a?Xc+e#7bnW%YQ)kppihd65I(F#MYk0(A4UY>k#0~;O4*?ychh` zQ@+Oh-F(x%IwGwu0MbA^T6rLxmYZ@zDcR5OjK23I^1i+FaRwhV&9{PxMX zB;2qq142z}nV?gN8C`hnUA!y4E*Bp|*}gFnJN%Z!xdQ%t_D42LjHtbv8(3ndaUAbM zzb32Uh53CY_}%Hcd{tx1w-vV-xE7vqu1b5{XOC^ulCOGvr(9`JsYoIV`|iy@nm61h z9(s%8*T{Cm(7KdkFY1^axzW+zqwmVM$30J$USIx4BXnxr$>{G?X5#28Q|2#*lJdLy zK+o^mjI3L}g`%F2sX3*O5(mVeTqK1bM-%P3h9l;ZQCPamBW0yiqJ~zSpF?{GUAHko zh)DUOGVyt{;{gh4r&WP0L~0Qwx{qbWx5~JI>QSiu}Wkw%v_&e%Er0URqsMH$L&G|3hD=(>y(cA#6oY zOeu+)fTLd|QyIryr5SJLX~udK6=%cdR)S_yR%d4ZWWh|Qri_HYnSqpoe=XObcVr1Q zqSR~TTT@c=FX1YMQX`#(bG<@A<+gA5U-oP6UTcAspW`q+jC0}LpqlWIW=Z0CXEK;c zK_APRUsp{yeBG1m_hZ9vo0E;!_suRJ3DKlG!O^IcPO2e#;UKZiS_18v;w!4abixD< z_hGCx?W5PJ^Uz?LsnCq?X_7pFpa-Cl0X?Cmq~O!TmVka2xm|DzYnKb>$C(|gjKIko zH|Fk6ytZc*(UWp%_)lQr{Rgm~f&uUXaRGTR9DwQzbhBB~#~QoE09F|XY^%oQ50m&m zLQ*YG1lRfQ?wDb2!rji9X2`Tq5Ul4fEChe2BKt26TFXIkxfmN(Ft?b|XwX{3 z75;c$i>q%n&vO2zap3gPYm9f0Fp*w0)5MrE4NS!z_T~D8|7SB~zIg63?}x5V0b0z} zkOGE$`+(eo6CIb@9XBDD&J1KvZMMz+aPreZ3osTnC9Plao2)!44F%lUM58b%+S%gG zbc@xNY+9;mAM<6(OZ3P8QB*gEclZO=Up$uO!1OPMsYW=u#6ne^8(6zX69<%UdHsq= zrjH(NwVuimSYsy}O%*ll*qtHT#YrhECxAyh+Bmr zY@0~5>4SGBIu}?oR&{&9-cdkZnO8_-#jYjCxDN%=&cpk2bj7F<1+r6n`!Q@ZBmIER zEgZq(0>}|a!LN&krql0f>>;x-aS8@2+nut%`Sj^{Y?6>|k~hBQMwZ=(oBLu(enM&r zh=#$Hx_>G`s-NFQ;17!k(>St6!7N$EM&zo>qFD^+d>2D+$z~TP@hQLIpua`1JFgFe zHHN=Wc;Po<{VGnQDSQ>!nrfRt!oaM(XFJ^Heiw1##KJC^S*D)WiIJVS0?+S#40~{2 z@Gat0kxUt&jIc4CDiRWL@U%gC7N30u4>fFn-(fEOe(NH+0u6uDC3Cew;zQ@;XaFjJ zA}rM7VMxb7-|$S#f-PIGK)WO>91ERY@6Nhh69j4xzELsaeR{Wl#CVvaeJ$X_ylG>J zTR8Zx`5iaL(m;9X3E&WhKRTs?KX`5TvdbMg)IE}~J^Q9QrsZ+G%n&Tv=V|=+;sc!v zPN^O!65XUI1nbx1r*V5;*(6;@mahH{8`%3pDyk z}&r$hKjC%nU$OIpso zDawI7JMi55NY750wv#amS%I!r@c3mGp~FZy(T0RW@9eD3Gls)wmYXd8llgx>yEs{e z{#bkbSghx8RYSQX4#YrxYz{|f^J_A4mS=;{t`~u^hH%q_JB<0A;}=YEk`_#aI=Lt+ z(;%Z=c>!_@RnhYiy;+6>vB0@UYhsn#ZvUQUx|6cWI6xZT##oDA{59acd>JlbUo7#b z`j%$b@iX+a`vk1>dRQFuyk?(?)5z%aZ%CD~;r6}ADPO}m*TnDhDh?N~;XXaOAI1rr zAQVOg1l_6a?Z8C()*e$06VMW%r)Cky*(VE#q+qic!m?u5;MB2SlUz`~RGB-7zEwz` z{o&}yWA1X^-h?f#nq~SLe$-{bMqUi4# z7o^KN)%l+YWTT-B*dJb@MK@||N)HtO_qjJfPiWmbF#5gfQN&b-x8`}{h5@@S+IrDz zBZvO2Ebv#KbCvV*HfdGsV?BUY9**>7tY4R*KyaKc>U^5%7I-fO-It5C^gT*a92AHs z2)YX;i<6RXbi3s9&vM~lZJ?7;v?U3;GKlDGa7$geZu5U3 zk|poKi47lXX;jFP)RcGHVWz%DZEJ141)BL44d2Lgv}JI27H!<>pYRpGFrVwTuhCNb zHx-F-tw$#d559OPsXsdBEF8#r&uYL{)gTjl4l;&W8`cr+LW0@;T5?Uf?6=x}#j44_ zwYGOW?gmPho^ZajqYj0cMLtcq4=DEZmLHLYhj6ZRIFV(hqh@_i-^!+0U)E>(G0xT8 zUVtPL7o%GcpQrLTaZfPovC&pjnO!?!9`_@gWy?PoC_$6IWd34)*sakF6btter<1In z-i=5MF>Kgcz5&00@rmR4+Ll`0cF#4%4c{-oc}Zb2NiLUrxfT8Z2f)@?(`u3`@p6uTaz%$( zq2&Eu$^kSD(IqdrsytROhJ@pLkQtKnhUaM2p%oCz)`@f#3t9LB1xt=38M=y;I>Q%?1NP+}A${)m>N z2Qt-|8ub#tub;Tq%rK#u4lEQUhrwWR$m@D>?D-ekq8oE)&=P5VTzVt6QCX$@Z<*IXC=qi&;T4!8OEl z+9P7|N~;X&&C|tnivA-kpeGdmUNlxXogfj%ld&vmqr^%{ETeMIF3iDYtF#5p!Kv%N zyKK&^R0D*_!lZbiuJS3>PvjZT>j2pS2O6l>+*051@Rl^A3>^k^-y;pT}oK{SRM-&CZj187vo!AhMw8Y11`c>Iz z5Rkp%l7qZ+y+7emm0X~)9}PfG;GIQ1Ej}k<@UrgxyJTZ8X!-;JDU&!eJ*QW@`b&uu zwq)G7XxfGxPphH`d6S^%h5W&+G6!ofYcHPOFq7*HXGYl{2+`8{(z<^~hac!@PAeQC zZ1yhBgf)ycbAMM2d~`Zz>)+0GNdL4flk?b<+BGdMU3PU@dpx`4v)Xa(sJ|dT6n90P zXtW_sVtdxpj&(Bdb=sFS4$w8_zJlpMve&LpEDcFrqN`b~04B^UWoC#ljzf0{y=;ZT zlem|6?*TE`tj%1#(*0|`qbwj&k*%+0df<`MrPQUfBqIlPH>B-9V zjH--~L$p4au+ALW^;Ca0^Kp8ne6pAl6D$mOKYB~A&G%t;2-Yupq*_$;3zAD_ogdZT z%2O9YB5inDywosGq_Xl##<17b;$}8uU1;+wR6%yzc|5WgK*&ZLoB)2{3EZ9LH^iftQvaDloZ~X%<(>B3zXtrv3ue8&|PAx$)T0S ziP@4pdn#K?@0oV<`ax+$E01-BG$mhS*F^_7>mU)K!MtxCxfCn&+ZFnN@w(^^vs9c9 zrj_|-ldkUvr$p*~p8(Hw*Y)S_$>Di$S;Ey6tbBB)Iwaxwv`3C+xmQ9#h-CwG1}>38 zQ5VS%--a0@agTFa+gAVoErDFy`>S{mTm0XYGAp ztmdtdI$AX8jro{dqUu%HTrdG0NC3)4Nlp&$qJNg8pK;Ze6%9hO2la94AIx(^x69a< zvg~My1-x+87T*Gb_i zETt@%aX%pM9&OoiLE+aRi=7AGPh1Pf3|w1GRoYguxlj9UfKe1#0>?0zZ^=K%)G6qk zq+sBpkCXibmzTN|uvF({#b180bX@K8A(dG6$o5&NDVkB|o2LccI;3a>NV?QP-yY6e z>PB4P6Q_^nMRxlcaJHB|9}iK=4`R&_?DYDLdo1VYxONsNVQ|*;T-*KgP$H@yZ9a~aS^-R+1mu}ic=3p`E}XQhYZK}a2w)+?H&ia9Ov z7QUMS3aBc^-d;5XNk!~N$d~@neX!iV1w>^UXjp0ehzsJyziLrA5#tj^xd(56G|`3c z9yuAxsHY`+Bx|G%j}>Brb2dUL>g!~gKi z;84qfZTHc$!!x7H_u>yLW2MlSy*XS{Jm8wMJ)xB}=3a9x!=2ztqn=?72RqYI?^LVL z`xtu3v zUA^h_wS}-$_1#h5zLkGGZyb&5l#+Znb)gZIZ>@htkD(!VY5vKTusTiE|4$uj-W^*xgQ+sX{+wPRTzI1Xd|H7xdr#~tiWV}|G4 zk@qKs?cum5=2eVBr1U<)futk9ZGZJxB_7f;HV#b*#b>ftHzoeIB^bUqQr91}GwF67 zEor>yl_hV4y1`taJ6@EljtLulJR5iW?r%Q5&o!@(!6Ck3keDpSbXtjsJ)CgJ62`IS z=Z-($9qDs72D2Fy(DMnn!a^gwPY{MSIa&VYM&_iCfV<;bx8ibijhV&metNh1<|L~K z0Jm@%nmZ3jT-8SP$*lW|*#|!+AY!CCOGsezifNHva&1L@9F`Urnq05ZDoy6DCbE%v zWvNnQEOx1grXcc0N^4Tr8 zj;o}ke)n9{H}JVG({H2St75DixK`yhn>N79+$5b=x^*TNT425z(A_a_YATQ>QtDn9 zy)ZQ?U}LSN&)K=mq{IcQ?6*+wSP~tpdFnC_Z&h8;8ATf1@MG*LvWGG$almp-f|xsb z1jc<74evMX?CkO-yp|_NIelXFPn+IefT)I?I2_z;ofH;&;__P9p>shxTfS2JYTwNU zCs@(Je+h3xC|GC+nE5NFYwym2_K0Jh&CTU4?O@@qvp1i>tyHA<1o3W3*;j;&XSU0= zwR>s-?@%mvO8rjn|K|qDhr98DF_VJwP28^ER!~e^hWd_kVv!FPt7&f%%by?qnF>bb zEI|RYgPntE;Nr48zAx5K2DW3Wz~>-SH$&W5gF%CZoEDY`CZ_92LBt#5U?)OyUWj6F z?|o4E^phsha*m$O*|PFWE4@Pg&IJpygXTVu6GED?*3LX`A9^gTgddqzHHcF0eEilj3WLH+V+x+JqBz#xjQ1Ow~1~ijxr}|H_!6!}+{cLJ=%EM6bacl);r#>PrvEa@5WEw-#N52nqsXro*D=T;223;$?bH{@;x-rs& zm0&z!kj*_+%8&GZmZUH}p7)YFY*wMF?f|VirbJ8Dosyb$trow!Y^idR^x4XfQMdlU z;wwSg5q_(o6N%%h6E7H!F3v$aRs9y{vk*FS5ilG7Q`u52|L_y+xDj0M7~S{N`@vh? zVJq|C;bij!#m(0R5kE@CCl&Q~Z_OKHllTno9r3mdA6pxXg6+ZAq;w1K7tpNOxW<;C zSWX3Xv~s|YiHvlh?N=|#j!n)u@o8dq#4Eq`?;B`D&~p2iUJi}=@U5aAPjL(X&Cs>&+^GjcIi#qne=ETMnq9(1ft3LY?J(_$`>oLz#!M%rBAQ;-?|PuFO}mAnV&1P=pG_A| z+Ww>29XaF#D93XuovM8bs7gItK#a8vuH|+Qw6y5ro(iZ)sz^pTzlVqSJ|h6V%r^V^ z3wu-A@Iyvc$O@8M!!>bne%SZbZPrV_W2AdlhoSY#rGQ*PI4G$+g$Tj!CjLlH?$jZ) zwB#}0S*R=(F%nuN^(r0x25PBoI?fi(P{$QS#%RQQ$SfUJ0Z|z<_#I|vWW3tiQmHF7 zCf#-YNpk|LTkC2a2%6j~$0I@X+qrc9h=kN5q4^BWtcr;u zHM)O(;}q2D5^VQlcQ<)TPMpLq-U$xRQX)-y4j&1!`qJm4=i9gpTsT_Ar0xOAIm+T!&p0Vba-c8z9TyW={CL$fu$bm=ox#~lK zc2P$qW3jJZwV+>aknWDVsOzk!0~#saW;!h6W$M`Rv?cdA?-;Y$co`afzwUJf`^=YJ zrhq%WgNNw4U><7!awS_2;_7CWAgKngB`Wk%RCMS2MJgv}tiq{~p$UEO`XcJSy)2j9xnrgv`tdT8*vVFAe97IJuMadCt=%t^wS5&_=5 zMw}h?IoDCHy2l~Lp6|Z^tJmJIX+WVtZ0Bs`$0P@$A6_JwiInR;;_#yf2jf#0bal0! zuM}P0u|ahtj55h=505~?5tZTFfp|9%X{#N>1hDy^@8H|RE=Sr-H0L#%+^X>aVvg7z=KtQ-hAm-ko&GwM?NA z_x;fi{I6S&dx#>x4=T<&7*p6u9svBlG2Q%HLAH4F>~D(Zviao*+A}+x)Xfb_VW*or?L27J<60veR(l&=97?vm^)-m z;&fb2U3mA|WKU^wUh35Q%a2^iK48zbe>M8O2>!IC#Sz@FM*s?2R<-Cnn{=iJ@ z=aG5)tKkE2ezCt`K3e^jUUkkc~Wt@%f0M`oaMB?{u!p6IXv9a>c z$AM5+EnW78<{L~(D&qYYJ&ku1TLuG=+fXcKcKz6%QbV>PRGxPwD?M8*h^W?nFW5YK zd3(NG)aH7N!m4tZ_we(leHVV@d>T@3K(y;OOPq^9$#hM`-?fIdh+BO1bv0vR&fg!K zYYU{M@n+BzkDkiUizhsmnf~LpJ$rtgY)&Zx2;Bl4ZKv6wG$d^I&ZtQFn*CZcYT$Nb z&-{&t6Si~aAG+{-m&c;lW+qGQ1H{S9@;bzx*mJ8n2P)U6NuNbo$YgHv)M@{V9WGTK z-i`WC=s30D4fIqQUmLj2wiZp)?`DQEchsI?kYCzdZ6>nx8A?6wP6;x}+PqCXzysZJ z(CgPNP-);w@V4K|a14mH*$1y>R`w1OnRRW_aA~PmJKoxsDXH^b4-PUs1QWKHL~n0- z|?7DK)?SxGOdu*hg4$xuAP zw9E4HB>$AclZ5ym+QQG`o&V9Se$~c&(G4~aG|D$8gGWR$w%@=JUW3ezCynG};-gou zDthl4Sx}}w%uDhz(_{#jfGc zfN%8Zi0u9@+X?=;~VWbZ=E^k17kI|nzn9~(b= z9ju)=R4+d+d=n?VB1mVdZ)o>WIkA+}GoV&KsrKQ7tF~@Kw5Q8$XFe`mUF6vVQE8O);?W}=Ei>FiYjJ>qne4D!u%M-ZS zBH;dZY)O=+fDz(;zlsE)5d68QJAj92;JT~bdj4H}Q3z}A}Z&(r;WLc)JW&i!hT zje~0o?FCtGq`q}uVeC`Y`_^MA;0bSWCCbLInmnZ%3=5P;tRm^KE)^U9Xl_Uc8RRu5 z?4PZ_w#N&cjHS_>T}6u|b}tEQTkdbvd@Hn0P^a{_vd|x1sZfa$&@{; z)?no)x;Ae1-Kh#<7bqS&vV`0s6~Fv|w47kARNC%MFID2n;NBEQL8xUbQ-7BbtfY45 zu?G|7K!V2*SHiNzWSE?gN-wOcau zK(<*&0dm&sV$JbVh&fpVSOG{E9cr{GEMsAs+E)O*$*$5&E2@zKnTgSG3G3Kar3r~x(vTgsslVUr*wnUv@I}_+kHFkJc9V|gqEPW5&G3(K97k`K+ z7yk*CBwp6t4pQ6Hxj;WSepvd<;Z4E7FYn&)pYgMod7cmzVk~L`KghXUMugIK2S3nQ z?wc0#?K?^N^YqNaLdt!@pS z=E;9wp6Rij8GXlUzMc~7rC4@o8OB?Xop7pk`$oo%MpTk3A}IjUAtO7k_YGG$l5ZQltuZ89ARkW!-`g79l@0V|wV*tg z3TG+7L6`!1J5o2(}0qvh6Sp9EPh$p=N5A<*my-M#5SqsEd(3 zH^OcLD6?xeP(x@sX0kMJF*vxdT_~Ap&XOf^g{GA+WKhO|o9~Utb=g1&-Q0=^In%wt z^6uzk!SS8jkfi@UD%h2)U;YBLJD7tW?+#IoHnb6(qy&QwCpO*fyXKDp4$!Gmim?34 zPKmQq%Zz&uu;aqA&U@J8bjp0EYdgjV4TFnMOEUwzsR9*~;)&;aZ!3pZFRomEMWAKv z=D2nK@-*NX_m$M45F?F;)^#yQr#n%Ql7&AWN$!C3n48r^K_7Py(4f@1Y2J(ip(k+R zHyn*B_7EkhuAR)?t^DDlH_?IYUYS3%0qrsms{}DTD$iQ#EOh+i2rYhJ*Pu^RbLeUX z_BRLocMWZ9&0^`GdoOsYSe8eM$T(+hyq6z(?xFxHEG>GSd)>=3)8iMRtft>Z6}NmV zRcp9#u->nPRqBRWh<>VEqOmolBaC}3$Vy6zem^H4P`=^7-_+uoQoVDQ4m zDa|))bs@dZ2`{Q4yVIDg0~7g!i&)uEc8txB$Bw)30`FUdLQmSRt+(QZze3iyGBbPM zq~@vx8zaS6+)5Gi=fXFVBR<0I%JP53qTgRfHk$F~g>(fJH8~ArJ`ehC#cKWm+*7}F zGjn$+AdQDx^bSrP&v?s0OT^Ps%l*Aed*l#pzDX@{_h+%M#qYcm2BSVru?;3F8e2d& zvlq+-LmM|t>}Iz%C#>Fpe^SZtDYx!E+d1m)`Z?(TxGUUVUAT^VTHb1`Az;1s$Yvs0 z>CH}le4K(s>9yOS+WwbR-UU?I69|*z$vw%X;a(e0$^U_)hC)T9l+tV__(n!*i9EG$ zg;~2g2S8n2>(sM6RM%NZPV+DyPlg0*Oi{Zc6P<8pk;wy3P8WnhM4F!e&A=*VWWGgW zcfijJ`Ds5DCG~Ya>8({jM6v}c_$`H|IAmsa|E_2A<8l(a)4L?TloLa?(lPJzc1IKX ze@@p#G2#{9u>PZY=}d8SVr1K#G7|N2@w@kgDM_>evN9Q}X^y#GWB!d%$oG$;R(B(1 zw5rlC{_DV9k&~76B_??wiw6 z(e;R$@Q!a`5trI5fy#BU$@r*mbv+VuUpIc#ie(u*_Za2gYmW_tPWVtv$Mw>F)b7XU zE_ky1IYj37Bnfe~Q{v^8P=G(V}Sn?|#epZ|wiYQe^_ukUlTWl3iCr zSMDlbAplK>220~U0b9}l%)o&nJsVMXUnlM1+r^N+J(A&vq}IK9^ns4klHG(nbGGzb ziA(iE!f9!Lg(}EiRF>h?+a*~!*=*bcQ-1>vCJ>s(ix-_>&7$t_FZUFCof;K=OioZ^ z4dz=n*=1Tw=^v6M>O?s_$7ki1dDc4=S+GA7ySh63@cZJuXX{+PrC2LrP#U;yIYip5 zjAI#hGm*dc1UN&jGTwQ!{hlrZt=-I1v#BIb$(=T$eDTKcY@C!`&GsmW4otbkZ_#_6 zgE5by7PZ@cJ%A&H(v7?~_rV$_oBj!oPf+O%M7IxQW!zpU<^q-!?I|XPChJQLx_J-H zzh%m70nha~0oG(Y=!};(=>Tgs9EsrZ*)b_UVqAy zCzB(fJWhL75;mS9lpn;YIE=F+Gpl!)TGXOS$v1$eopAKb7jw(LHQ}sa*q=yUJfbV= zyb0SHjl(d)m|u=HI~B$nnbdsbt8ci(V`ce|#@q;J?$cXu$=5zsAS8pPCHniy|2#b9 zN(kVNQb^sKFev=ttukE}e2G79**l~ERiH6X&0kB}cySqI;hWx ze241CvXKvgerxo?*VOm->*{BO|5#k4lHo7ys_w5+r(!)JCjjEOWi&DMEk+QnPvG#% zd^Ii$IWHmD&7*2kdc~vu(cA>gA8I78(sC37C6SVI{eGN*SiXC(?Ma#FC4-dXWD2Sr z2}Yjp$=Hk~WZhn8!$Z>2q#fGvje}bdutmVf2kU^pB>-sB4&mlnw#VZ<)E>q(WvU zxBGndbvG~2?Z?j(OE;~H_0TtNS?;EsqEv1&#@Qv~yw0jzt2{k|zM5(6D``@SgF!Gq z>~K$D3#jAKv8c@1-QDCX&ZTbmpIsX97;8?Recok)$`W4P8rMY&mL-BqVP?!w_C##S zbns#B9g4HJsrKSvb+lqhEb&Wc*3k*FWA9Gz2#Tk)?6B-ouWu`Nw8|r{FCB%6zcb#V zOphPym7=P0cDxQy%%0?ym1Hot_VDa>N>*6!jxv4=h*~6T5ME3jRHq|DbFbo@-|CpL zgR;q6Y{#u5psuMbdQwqtPVQzcPB{6}r@L2Q0X@`5e|4HSg+_x!sp|NKE1<&30SS%y zEJ*nFxr; zcekCA3&kEZzv%#Tax0%5KxsEtXD^0i$xVmHdcxAY+_KLL!mE>bxO0k{x);&>^OcII zl~+$J$nFH~qM_xTyF)<}9F)?@)Ng%eid#pmY|#1%DhF}O?fe}RV&JTb%Z7P4;Pm7; zmZXA3#DM64eFy_AN5)zjTfKo z#0`J;W_agvXU_~H;{omRc+g<{;bs$rcH=et1?2;fh`~eo28ZII(Ht#3Mfh)mb`9Fv zt~Rm!nWz(qJhzj9LzmfiJ*_U-cN=PY0sH}s%z{(iW0O@o!!!EEM8m3cVHil4=v)Qy z9@XM{qN5SNlbe*lmwXyAqolt9HG1{OF3SU|5ss*j4np$gP_|Rj8nP?wPh?$%ew4EP zwi)JM`wDIK)(-sf!T}l3Jq;KBPAbs?O#SFKS1F1ivzvQEyF_1mSpjEPPt*k2pYo-Z zf#d|hO?F-4p=XjcyWx4p5TJxJE#|hrOUS0tz4yg%F_H&%F9Zky)c3%OUsvTfeN*K9 zHz6bGAbV-%cz6+=R-mD(DwaTjIO=<@VcrB|>z3x@yCp*2o}hoA+Wg=6iQ9`19WTD3 z{K|WJgu`5F6<8VocX0>xpK3p#bUqzMJf6lb=!2G(L4Vap=dMrmK>ESop4HEsI8S9} zFLOm^Wqgb}y(niQzD_ zCI)pY-eSdBX34^L*l@lzbpBVA;$76QL-PVk^S7N-$z9|e`Z$YJ0f@$KBC&fk?F9q2 zBD`i1m>*ISTRCA+O+s?0LlDlwSNw@aIoq`Y zng;n`>pm_cd4fE?2dH4TbOPT{k|FtNC(|{lC)3tFSK4^3{@W~R=uOy;F~w20{Acos zbK+@kV*!H^I%PN}({6_=UvR5Vq%>tE*qy9R3S#R3;5<{n7wO{4Vdf&UZX+tNB=Pf# zB=zsp(ra`df?WYns#k}r=6|vFUQtbTZS*g`RzO6MCLmEjk*?BfUZshE5fD&Xq<4@W zAS4O`QX?WDH7_C{HPWSq-g}iALg*4msDXrd_BYPe|KgmBGtSMv$VDxTl{=$q50X&lu@c7 z+-aiZa5&-=k&zE`dzzw%@mPB^_<#WGXK6?2n>D1Glwh94Orqbz3KN%##uDsMNvrwk zdPAm_N?t&N5iYreo!!@Ij4;9;1PJHN9h=I@2r@9OZ`2$tiOZT@l0t0~B@MPSgH}zg?4s&rbQV6qa-vtNqzGniF>`CUWrx zNj}`gO{&;WP$pXN!q?oJzQ78v2#SZ2M7p7~P=W!my0+DW+hD|x<$PblN!jpMPh|%? zMMB)cVX586qT&!HaSQ2|lYwrboakOI@3fcj%<<%geHH1Rlj)=5Nm(~cw7I5yDM#>R z-d8IFAxoRzVQFeqx<7fL*g*N8gomB*Y=y;+-m>+h%TbBN^imrkg(D<$1A)t~;uKj(5$*?1Kjw^L%w3e40*2lAfiVPDl5A96`hLbS{?$9i#lRpw^_L zyxh$|Oo6rKlRp=FGrxa5VO_VbG1@F~5PfN;iy7b@ok8EAw}7~4PRmF(7y<9p$zo)2 z7N{ZU7VyixPt%8I{qdiw2ylGRaVI1e&8`Zi+5nU|#%7*Hh!ab7hiR>#ydsj2mKE%w z$$91>#omG}`C1qvw{0RKTko2>6~y$tDa>VSrk0E*uy#Y@aD31s7s@5v8??6F#l`=i zb`RrNAL)c*1*I!eTt~>zR@OP(QBZj;c|Eex4b*XedF`m{-e;$1Gtl19i-vK`{TYGe z&859Eb^!SD2;RpyQ7qsjy}CAeLo7Le{@a1hcewjmB@F_!QJ1(Q;D%?P+~F?E8(Bg% zX;-+qWTHMLoYlnaNi!ja(Y3e^2;(fx2*hqPD(%m~Er05F%&u|!d13O?G;a0G>Eur< zsxs{qM#4U>R-^;qzp}+f6Z2djDfille&RBhuK7&IGU_Od$$YzllFg;y$N-Fa0!4*bfwky!PPys z1B_llD!^IP7`gk)Y-N|mrF3w3mPFJV?QDldwpdWHsp@|jXm5EBZeHH&hvtDuhN03_ z;3FWqFYxY)^iq?W32sX6CN1b z`m+`-eQh7Fh94V_)~v5~26YqJs9v<^l)nsl!+2fUL76rI&TNOYss%yT`}%f&8O+xE z5H9l6i=gf4O+$m_p4>Rx&lElAmS? zDDXcLs6O=w1WZ!asYaDa9m)l*P!>zL#)BYHjDpH@Tna>#;Nrt~SpXqMhF!7c_4qAn z^7c2amyGRz+@x8O2bv#I;){k$UDMwm{m_T3%(k5 z$S(s7$4O2e)!J7huOnfL1s7P`nyx&4GMdoSp1y0mZY4H5du&`;QJ-nv?k(%x`*4$2 zhT#>U`cuMe5V~;xARPfe1TSeZ5l9oce|tY`symT_8oaY-$~5Rqckz(-);B1-4t7+P zcqO>F_qW#r{dt4ybFnF(9elBp`;WwK44z{?RA<7JB5kn|%1&J%l(|AgwZ&#hPM9c0 zXJ&QJF^$+F$_}>epuglg0z(=>RB^z*(@j3VtU#06jXXVycnIrCE4(}7{AWcObN z5JC=aHs(>q`cYkKLXN0D+L356bP}fEI~Ipy_kY=s)8O-Yt&0cFqlu{5#EAt=`wC*mi{ABv6g7Km&-PY8(k(TfND z13OZA`sQcz__u0y&6b^Px!#`Bm)fc&m8p~n(k=nqb|%!G9+j|N=GO$atkx@)n~Cfd zOw>R%;4bjOG{+1HPqEgYAwjky-caWF#dmUm;Ytc|Zp zsa==bdJCI6YB%x_1KWB1{O%6cCv^WE0da~3Rh!-iy51y0-NN|`3w}(hsI?q8 zid15wv5t^vY)t?P-%Yxp4jLoW)$<|>yn@skQQl14@#`p+bGFxZeRp5)1tkxms=!Ny z@?d5Uuw(C?s8?P$+>U0mFf%5YF&ByU6tm<}aFkb19sLjiU=4#6i0=dONKPxnVEWlw z#P^3L6V1Z`k{x?p5nlxH83Qlv_E{SFJ&XUVs$i-xYfuxXGyb8f!p$iKgyHLOQ&Q?j zDfmOyuu@NRtLF>h3%y8LgVmOpnT3WFpU{Vk*vFvfz~dZ7vmTLbl*aE0KsSOHzFd?d ze6pD76_o$?v(8Mz+N~}Y566L&Q_vMldLObjbvwdl855`MS*9xKk*6twZLXO7W*5Y# z)VkMfCpr(gmNi@)#85spggM`)7d-J|%4yX0#b%dz6#1we<$=R$(!qwX8p?=LuA zsAV1sPOoZ+7&a$?w%76hlM@W93sTk#{_Oop<(-c70 zul*V#qo(p^k2J^OeJip?a!mKnAL!vzfrBAH8%Er0U&>-`F>fJzCc4~ehlT43z!h#h za=>THpZt6Lr!xo{!v{o|YW^gZ(r%Pa7R2ogIBLz*deroCgA7l`(<}7Xj68l*j<9*V zlzS^9gH#dcPu;y?^fSv~u20}SK`gq_CIG)qzk7;yYRBzDg@{QPtKu$vWL0wml3tj! zeps|qU%5={Ug{xM{rTsWe`pzP8sE%_?Ae0ikvWH|5c(P-nWoqjv)@vG2_x$~HgDeb z+q#`|>f@BblPecoa~9N(pI6f>kps7AD1sPt*K2}ymGVctpK3z+tdnMAvwQ(6i%ypB zDQ?*Kg&{h!(4TqT$#Cw!_F;ON6QKmEGomBwPvW;;jJ3ch`q&3 z-fMC4$!}<*C-^sb&G=t-1Gg1^40@EC8ogU}Erg34PD~Xh4?yM57F;yGfJKEC8?GOZ zys%%b^jg-(q0X?R|OT`K&|&wu|poo3uS*|9N~ zQgr2OZi>b}RG#>^vnq9E z+N+1=Fe>?Dbh44R@R%06*6sGtvE@>6nUxJk#o1TpU)BySz($xZ>=pVV zuEHtIjxtyRH>o8zXSk?7bmcOB;*bDR#52A&3CyR7bG*^^wFDD|s8E`I1LZYPfqAuy zSK<>1=e&=ovYPJm<~?kax26L>cdLY!oBK8}GiNSuba^K=RJhCyoH`v9p8YtKj^LdN zCqb9!pR#XLvX)WrfWBHjby{4q4zr zyH>oB?B(4cYuEPG8x#*<8~C=TCU%mo!Y%(p<^BoOIPWY4>uO*@kZLFcCfMBtt$1v- zz^!Zfiqm}-z}I~iIa_>f>P${y3izp#y1D>`TK*TNU;@Nb#dd|d;EZ>Du6Dsn6q>8e zW#-hcd0L3qy;Z1(pAfBO;MZN#zo~->YX(^Tsfwwto4}7(l?wpwx{%xrb2&g?QQaR= zHD2{gxUTLCs*XcU7yJn`2)aabIKu!AXlV{NL;8@+ER4H#_QuCSV%xWJ$*lJ)_K9(E z4*~>fxx1j(Nn_pUj@OZb*A#>K`uDUGFrmP$7ClRAG)FgIE^=3X z79PY>^^{}mF=UlddfE@v| zuL`!66;3S@-M6$e@d{-r2uy8aAKd%rSv}Hr0i;LCTZTj*Wh;&f?5QY~ti|=-e01ry z^0S!VZ@xS52?-X$eb0*3@3^Ab5a<4YS^XIgSVX#N(nA+^vfkOcNJ)J#x-+lt*Luf* zKmUtwoXOq0q6?d)4NZ_&XE|UOT+HclxBUNz?)F5n#odmSJ@@8`Rjs7HB)&XG?6G0@ zbs>0^D(TWz&hqXD;5-YCw7ykOdGAK{f{;yfb2~hDWM94q!MzKE*yUiH_AQs+SAyGI z>(YO36n?cMvwzvpdrI5IjS4JKMG+%jR0H^f2C{Xj-6b@}d0MdlMdWWbX0Ct9eeYu* zT$Aa7y>VOoyeRz3In%qFVC9{5+H4RHi{p2i>aN2*i6u?x#PYmaN;!;Lf6G^8t_VGGeYOK)U#pEam(&6b%Sh%K<_``&uhn{@o>G(z~|e*ki}n8qP*~K4Lw?u2}vJwlKK+^zbR{R^;A6Es}n|YvH0p*q0ePG z!iv83+H9!!(1xwfQt0<-2y#FK0elr6NSa7j$1YKI^TI8E)jVj0^8$Vo!U=0=gK{N3{y8pf@GEjv^Zkkq*4@U=Pt9mLKYg0Wob0@wWo_ykRIL=%2kGiudSyvZj^-YWOX<|QF;DICa{~8 z9lm?J^9LMCY4GvKu>m0|bts)0CI)HVcjt-J=tOj$pH-7*u%bKl`lhr?#dA8KVgS)Z zfsHtv=1a;d=-foyH>cd2dl^McH$^A$d=^!A-b>W(i)rTz+;#Wo#FCIl1(ZoVYrH(D z(u?Ty-CU~#%EppV&h#B3qr2Av?K_)D?0d|#^~3jFyT2PZxVpSk<3aa$DQ~qELBylf zjqZdyEz#xJy|NhtEH78ySIcYPX^bQAE0}LJM{U+sW%Oqp&_?c7cQ*9n_|7w-L%8t!m$RQ$`}!aKMqNt|0h$$q;ic~*>gM4zIo zQj|!s%gP(P3Q?~YoYJo>^8AN-!yu9}pr>L-D)qXG7=>0zx8i2`5yQ}1yW6T>PCrj>ic9jRrIU^$IhAwg2P9j&vO4VII_l=d$mDk^O+%RF1-EsYbHI~ zPO^bWz9C&UGnjFF&jyd#CT&#vovOaD&WoP*UtV8%CxdoEA*=+zA&>`Mj#WWLsN2Gt zcLAajS_U-4EvWTR3cthVDu5U(T3OLDT` zE|LFsc{i5xq?@$cjjV|x1{M7g5T(cz&%o75k{<>y<_>arj&W`ojh^) zj&a-FFIP_^#~!6pM5tOb^kE#2s%}2zyX(=ibJ^JRnucJC#$M4+kmynj`pE6=Kr*kgj%ru+f4eqg;pVS&yYYeiY5>e74A*JZKH^pWF~W(87e^s6g! z_g@JA+~e$f6hXyy#1$l%Rz*zZzx0)O`KFv5K|IAql|X*js(s_4w{n zdvDLPu381QZx}&1HRo-vr*9@XpYd^<44+p*`lmH3eb6oLzpr$z_)|K;U`)0FcinX_ z$W+<>k>&FizXVwc?B`3G!hdqe<*c^O31p;}WaUr!=9|D@oqAp|yuNOP9D z3~6f*59SeMN9y3HX#?vu80M&sqC|c++>Ye5t07|}cB}-sYwmN_^aMnMo01R86%>JE!;t2Jqg>GVA%y_RGCOanbwu1!dM{QM6HOu`JN8JaWZy}aw@lC947IP{b%(N35FW@m+sKCUk%1})Z0|Js`a1R@T zsJbA`!tAq(+wZ)SIE(t4;S7+W9@U(tPx%kcgSbgkr34cAP^_;gZIkS)Nj$pWLxCo0 zi|-3mYGFdh__v+I`iUM&5}BLew4Jz&yaHJU19_@#f%sBW((C!zzK@QYmJU&5$0m(7 z(5=STHdGf_al3$Ua|601HTcP*`Ro_m5pp3n_XnMI85FPB+tljlUw0xM0v_bAc~6!( zdVlt_S;)Jc$|n1p03uUYCh|@IR7a0e&X@yk98e%&!IG*4a;Y3YSiZk-cyY+zf&@EA6%$W zDmAVtNdAJXubDpdT>{5LIhuuNc9d3;?LVaFlugs%$Cu3}31GitON_&r>-xt=1*$e; zDEJ8dg97ekA;g1BUWOgoE z+4{#rBG{`P5}RJoj*dl0pu5dGk83H7 zssf7jB!v$L(TmJ5*%4b?j;s&+z1^h_Yc>*=TfN4y)kAI2Xfz+v0Tau6`JK9~n_Xu! z16erRB(hTMy{eAl+#TybyU@@rHW_6D=BOBxYjMht6rPA%NEvTFiqrU#_dF!`H~mWA zZmD(tzlIEi>GV_2%3KmCk!)0B2i7{d$XQOdu?#3DsEO;PmE_#pBfk>YU|U5re>qq9 z4HgcWwhgF6W(!4WOd5EOnZGmC|9>kn|36DTSpSayA1aSDtaA?rq*L)(MBMZ9t))OU zY$B$EW{f>;FkP5l3s&R{aqwMjdib<vVx!eWsuK5TMJbZcDcVD9P_oL zy?jf>Om1?Z`yHWtC1GNlhqPEws#~hoUz3(tb8Z5)Y5nKhzp?*WS@?Kgd)oa!@mQ(# zngz$^z;cIfh$bpkQ<`%-M)x)r+Er_la8D!i5F=l?6<;RRQuk8nCdX=Q_`BfgyS;Iq zL8+b4ORp#mt?5(mgENwht5W87ED1i>Ss~^$W>Qxo*^>Z(%OdSx<)_SAz4kO8cL6n` zq7oHYfAz>frx)2B6_MNX4*Ys_zN1+B0??evS+SG)UV`YQ`JH78lg+lzfYx|>%Zu;q zGZxw&f?r4#I$=E}m&tEXUCjm*A*#1X3x;VE$J{IfGd8WBIJp14=21tH>Vz>h^Ls>) zVVAZ>=+-KJn^WLH@1ND8qIl;C-|3=|7=N|QvZ)lc5WEgij|?UZ{w_(kM>JU%&LU*P$~Vj1Ga)A_ms zjGZKYo{O0~8t=S(BiY&f?0dDgVWFB>^*6Qiz=A_%bIDWW0Cz=!>B*RU6hs-{8K^5E{^a%crLDO70%+{8`aohJW8izXoj`vn<&2 zKuJ1#I-613X5U>5HMy%EY{Iy}B(&X_YIGD?mrm*b6 z-N6+cI+S`{7hm^gR9Rk`Q&m8`A0Z4(vWB;JNp0)+=ID}pdCRv97ac52FK7v8L045T z7L`8F;#S@Z$z9vCZ0E}wYhRId#`>7~xan!tXyN%#42WqY<9KWRVp%#kUiL~`NoQD1 zFylWDPe!pHO}v0Kg36R6s;aJZEYN$a@7m#M_7UWfto@HK-nT?exlFNm(*vPXsiQLB zQyYy(+OCS${5Lg~gk6G*lCj+ZU=DpMd8#CFyXs z%m7RZwyIE6s)XLw`(U)iVdAa7b$JZbM;Uo-3jwNWjPx+ob~Bbh_!OQrHpWwEGSFO6 z!15+yQ8P-vix^&%=QZhlnY51f`MD#L)xP1j@xV{iBwTk^&yI{@lNm6z5R;zq9Z8<3 z!sZOof19Ht55B63;w?&_@e%E{nu9(?N|?nZS$9)aT@g1al_XQ}c{j74d<*O=m-fH1 z+s0R9KHN+Yujemo+{F3Y?Mw7C#-bQ)e3kuXz0r@XjC@?A>vC75XTz5T-j~s!yjK<6 z{o+~sE2SAPJ3|jMzzY~V$ZtYh^P>?z%tsspJVY*@EDDec(UM1d+GcA{3aWkZ8{-(| z&ydB9kW7uQgbLO0bC;hTtaA=8$YbbEYSaL?^oPKJFPtXrTQs+2Ej*t4&t}dW$b75F zxHl&3z(3JuzBJrgN@lU6Z&7DEn}4)WfH#k5=e944cASI0-+}&<5=iM^TKiz1pT~BU zbqecLeJ-{xU>yVSsVGiozv;KhJ4`nR#gWom1GQIuimgKkn}=55)>-0On!B{4o>I$) zOwakKywE1d2fBVi-3b6%zCfU$@T`$whGxM(h&vM(0#2{xN$z}$VTN2~dVg*P7r^@b za1SuVAzeV{=##jc0^I~$+zw5gl&Xa$a+$+lJauR`@w||Kdye_q*%Nf?+FG-D>8p_Y zMqZ)A=E+J*LjjZSh;5oEIjSAROSz#pfw*opXGt+1;;63FbJ!cZkLSA(!XwV|YuBnW zCqV9C#BHY79X18uS+~IVaHjUD-Warny?>xYghJsu?>jja(`Uwx60V z+O82WE*7<_kgPkoTw@`uf&RrJ!tzS`a`B{el%S^lct>?!y$Pg$xTNbEXlgO+c0*VgeoM&CO zJl#9f=fIEC_cyD5A_Obwh9KX@6KjJ1Q$Qx+-Fa*(SW5)GAUcTS*SK%M(%%sb1xYV_oJAdytZ zWsx>lezqL8>;~9VnDhy!LU=s4VqY)uHeEm2b_xth5X3XxCF373oF3EpyAQ&0D}S^CtE-J{<^B>$EhU}piBAF}{tVo;YA^>Z<9`)OE<+-Lpr}6Z zlF7+BC+WFEwj+O^hR)QD z6kTQL9NlY{O5trwp(lo4a>U&*^7JSNCF7$Cf2*>jTO^I6Oj0WGoOiJWMXbv&O54vg zs;g)6jrvyr_gO9HH(;wP~mE6iu)ZB#GaSv0JsyRQ2y$GC2kj4B`9{w#Jkx`zGn zklUKE_79_k!tu1#XLBszl47ty~ueO&a|%j^7qItH8+4mYk5N^QWLI{#k2+63|GMAr3e{~nY8!Y4F6^GAsWZV8x}jV&@DDeI`qEPD zr#B6CRP9`EVL@HilnR~e%$Y~$@3{5Qh3JEzpI8*wewd3E0uX<9iE^QWEsNi8EDj1; z^i*7gmw-F>Caby5 zr3}qPGZ5z$R6d#LV8)vF$lR@H$~~PZ_$xF(MD*>r4y(Q;!Pmi688r2cnDNHtdgMod zkzkcO+XOiL6HB)@C6i}9h%NxlZ^Rh7aySO*2#OB`v0&DDKWSWCObxzayJ(@0^uIS> zbM3MA%`Fz7nNhtSrY_W7xY4Xcz7#hVY|@qG@lQR5Q7qpQJaIN|ouyRR38@=6NJd2$ zFRC+bm}9!YF@Q$aX_>`znV|Qp{#DA&^?(>fyGuGx+qoF)UM8ry{Z~+a$lA>shdfth zU_@ws{StZV`* zmEm&LD6ayD@@4Pe7f@Oa87X<9Pe8h1D0lBgkc5_+E6IWQ-8hU~IDV9Wx+XY|O^O=u zHi6vBHUB8(vWszIwie>4i@-HX6jx5(;5QfLIEBEy?ptv`J0;xro(2@8Ecq*KhfLlL zjS{_EcU&8TTtY)@rz2G5>2e_|O;7IIP&I$fY|%ZoUE&A7!aD=RX^#~Ysspf__C@3ckQL4Ej_#vPY0uyu+}G%y8WlnJy-J!G*pT@Bi#BdSJfEf z0=__F2?|_ZkT$b%V2#39>bc1>r~IC)*}jsi5`NW=gz=*6lcbM+O*oMN-VirUVDvy_ za(8N4w|=Yy&)zHK7ris4bHV}2Kqxy^Uw_Z?y=xxXdKc-zlP(wAKI@JjVl*)Qeeqaj z2B|-t=7OzMAZn0gj>5;)Z_dFy7iiwTUPqz%V3oed~^wLG^1LbKkP%_~rXN!9!P z%v)B1rEmVcAYiotc3YJ1&YXKAT5@X zcRRssIU{gLzQMihdWr6g1@&dc_Md#O=T{E+;os^o@6ts+xMN*d*^0GZXI_Jn!CqFeoTLYtcBU~~Xg0_8b2haLR5`Y&i;>xN43 z^rlYy|FY08UZe!(x!`W9axSag=;XzQ9gv-hzkwd@Ewvxhe*YHh@t%9D7BIQk!#+V# zSVq%0+Pl#=X+p&my=Aj^2NvCv9*AyXl3d5t_qw+~IDK-kNIzKzMh!t^6@pot*F_p1 z`H6XJ4n_EWjr>->@S-I`-`d4d>313^{#iopukFygq{^co6f9wQCbkpHU^=adYNuZ( zt&E-|Y1^g|?L(v1F1vj49159UJ$#k&Uh87S{qA6fGcO=#cNfSlggQ;NM2v zazS2KRduS1GSu`DF^u|`weM!oEMe_*x);p84ZJu?ut0A4t;&yGk-YuR9mE8Q}VKDQgT!%Hbdx_&OQ< zW$>p*jgnPM!xK*#mmW$+g&)NFv?fd1T1u1RlSejpz|}eFx^eHG{ms0#g2QqDQHRjOWf;&MuYt~Q_=3o<}@)NJyblC`e13BJSXdqX2l zC@Tn}4#l}#%ifja#W^j8|A))#^p>H-VDM%f`jj!}7LV6*`y?o9*1xIaVf}rhjG=SH zLC-c}v8|^fvt`-chm$(oMc21)kqzawmG}%i&d{<= z+?v3M*Z>&#H@+@gsGr|F)tbj#V6zMBl)87a(8Gl89OgIEqgntK^XqUmJn%fW(?us8 z#%T^7=XK?1gUuFtX=S(V1Jwp}SSY4F6cgo&4}_3Xbt>8t)^Nm4=_lW#t0@oyi7Y=T z#chlBzWomT64~C?+LQa{cj*1@?xEXe14xoFmYHJQA`iL@7hlTIEFZ55QTZiV8t$oX z`A8=$R1ee`lJxA@sn$X&nP0g0WuRv#H2xfd0WpJP#yW%eErtQ>!}YltSD#8zuiI7H zH^YKY&ZX%4W2Oy^3CNbOeyxOPx}dXL9uJMOW#t8sXe_=7VO1`2 zS`FMzPX$+9Cax1evoh`GA#)V4Zpd6pio-0=yak^H3~)nz&+JWTxixuO{-f_Ru1Cc- zPtsq#{llAi*FpC=WHb@SB(LKIi^FS_DeYR{DTSv`p5Ecp@4gV~R!~lKh?z+d8RbWJ z{AIWd)E3v9uTgNV>H_|}W#xI6k6p{&3MYO7_8TiOFKzQIyjcYn(vD=2!^~hhf){Gr zF+8uf%-Gw5ew^d?VSG@L%iR{eET+x3EA?<>N@fxyoi+K=o0P1Tmrld>?C;Lz8j}G% ztY9C6fj((Ij8Zi&gkCXwI)(wUby)Gp5`_AM z=04dNm^0f`QTjZ$Viv`&uT zr0<1F$Q_A~qrDr~ELJh2*mzJCwgnX-z%;39QABAsm?~3^($kZa-w`j)sIxcv@k216 zg}$FD7L!^ylS;6QDlli?SC;^`5o-#>a;*6#<+!`Px^iZ7@jkXz@1hO;r+Kt$H^gM& zzW(v7+ku$7Dm69xqRWkgY~I*cckk7z4QUUz>*YDLeNvu|yp(Vql^Hy#yXCi1K2}es z(h^Tf|JSY|bya`YAYlnLS+@20srX_7%Zg`RobFn;tf;~_a7r(QI$aCbAfrAYT}#Ea zDG_+kY|Jzs5#{B^x9B`NR8uRz_w#J&i!7;5yvMkzkj_8#lvXQSR7fap-IyWcwy}jY zTQas2^f5)9i`-RAfJQd6RZQp^6hVYKg9N&sUeR%EO}a<|NA3D!WY40IPOLFFewx}c z(G0)d2^a?FTx!`K`+K+_^OfoMJS%_d7#*<0mXw|BeDbTU8u1j`glhI5o)KxqRiRjrKhsWgXKh3{N({K|bGPGI;l>2??^FN~9Df660RwmZ zv*yqLwRBeE=~95nJhL$>@sBO3GKW)-ia7u~VI2T%4P*%ykNAh8Ri614awhD|wHcUO1AL1moI5e(0NjxsPkEg`_>* zo~$1e*?Qd}nL0PJ7y3*t=|$QEs`+0~JPb+HTM{4sh^}->sFD;lH+VKXO#Gz9)Bn^1 zlK$cv^_^V5f}gchU}~Ru`5tz=mJHFP^iw6Aap$XsqhG)k$$^o)ZZ7&IiMn#xdz%t> z`wHox9wyX0MOwtAp_!GJ`<^W5S;p-tzQzwdhFhO(g~>zvU52&fGHC$T)-a zqr$S!O{w3b=pCh!P!a9|4)3q!x_NL*2v^r9e}14sO9S9whd}MQfA$|jV3Ec=uFmCl zI+-253}w>uWuCJhyj2Nde&(QS9Aq^Y_{C;|vuN#S#q7_#kEp7d1%${jx@Nco$%Gg~ z@;CF*Zc)_xm&MPnkxCbczxMCogkzg!kpxX9J%Kbu%v8p&^j?qc%&;j^Hy_)$7z6#w z;{|kJ`<}@|xdIl<$*tP9KVi*6{)$X5_FpZ^&&&P!ve8iS&`Ln3!N5X3m10Q1@xpJF z(zGZ-1n_y7`})gC*-hJ8OF{@i1-$eMGlcuyy?h+8N_mEKQZw!}qA8KHQ6T}UC;a~k z?+dH^v{=P~?t}-M36Ji*9+;Hyb1-&HSDjl%#n6Im$j7a~pJ0VMP15i8`i6K;_fhR@ zYtch|iB{UvOz%><7do}btS!KLP6JRT7q5|7BUMERV2UP9>o%)b;Tu}BRXv?3k6vCs zEHtRZ&lj0C3P~!Jq#f_JLVvH)`Qh4i6f9YxYn-M-&RcDmE17=qDUpk(k2}D9$tGBA z4XaFNp(#wz+{i*l2^258G&#K{ajn9L5d-7}G|k0Z}ik!5^F(*kzL*mPx4B48NxAI$`v^ta^S(u=O=3c#bfjOX zO8erQv~5Y-h_8M)-U!7bpfu{ zg8M2v&-dON`|x9xJH`E|OpbfdcMpsCg}?J0-TCbyLK=RX60wY&OEsee;%~W>!VL>& zyTzgA4Vps8`!b*V0x!0l6dyp2kY|x_B~rL$Bbhr+4ni?deT=jxR}YRWiK=EjowwMR ztgo)iX1=mDnQVIGP8+0HErHpA(}MO{jyew|cm`9w(6uJ_arL{NN~9gnA*L4lW;g+R z4T?|6T4Elwo_kE@ik0|e<#Jqh+sOp{=LQmb6lLPt;Oz3Q4ccQZ1NH$ef$V1CR*$Xw{lGuvt~o=phKK+petA# z)=L!S9Tq#nr3P?^nl+=To`1a)Rh9LV&v^mJRI?SS2o}`^s@d&~zwtCh0UO7sr|HSv z6CwY#yGFEgA-jV#%*qtFbx4hu{_V6p9gbk#Lb5k=(Vk$V+MDnEn#z84rx|(2id#G) zkg!;fojXtH#CCWwx&R=(X72Z8Zq0X^p5EmuT`%!2oQ3qyEf#NQ*Ia8-i1Lo=EI*D4 zr%8G&d0l|{wgwbOjF#N4g=f;qI>V=H_0B``na7-krx$r|7Q@~aY?v1uoFNKqYss8Wa#gd!k=TDf(tzni^s z<`1?-D6uyIB10|Bd`Ra4$vMMAC*f+OHlUE_hCiz(uT?MW>`8jqqA+HXVh|1x0G2xu-k$hF?-VpO=NUyoXrS?Zs0OR)?FcdkSdrcvTT_HEuJZMF*CWfUWk0WexVP?>b+WKv zAUUl4WfNZ{maM!0Kn|)ecjl6*T>=7U+3FnTbFi-vWr*5@`1%$3>{q(SFYfO`b5m-} zl&z!lHn=~?&RTuv+U_6HcfJg5%ez;l9xGPJTfHhbas&?Z5rie|DBP6x+Cv{hpx&hX!h91QSBo(IIuvd)JOJt*qg+f zT-bt{mzvAHm+FFxsW;M6KdakJZ;8+PDau_Ut$&nu7jnz^01@Nq_W6PAYW~X*^%ld% zTW*!WuV+095}(`RX7LtV6cX+Mu)RN9jkA;gt53f&qsJganGT0CD)vpuj})`4mOW0e z-1XG*JNmpEb$lOsS%g2)GWo&b-Mkp1r!VX>uXg`R>iGfW^zon#Q5^=~=gJBgW>cAY z8Q=Y7K=Kul{&4H1877&TBAhe2zn0(aZ-Zm*qSUA+zGulQyG`RBI~IJ%kPAMa)M}Yt z=EStC2g|se@KV3ex}SP}E~z((Gkv0w`pS;&(rE;z@vCunRfyx%Y-y%~>4(+aG|ma) zkwZ~Fxg2wt5I8vB=A$>Sqmb`HzciAcvfn-{fVK&`JtI7IRIa%aYN%kktvoIZ7EHNG z91?HfB~yAu?e4A61`4V5kEDsFaFzn$)I9H;Vx8#m3&HJU2e7re$rDZtnbc zVfaY;0ra9ZqbHC}Jb5y7ZaohX-*OVF^YxxfR7vtnR1bJI%5og26`ZAS$X>g0L$f6G zmfZ`tKE6(_ftx<^E52xY6B1_glV~*Zm%-?l9^bPdZGp_iQD|bkf6>f*-6v~V_8Vcn zqLwHMBd{$?s9T&oyVN7#BBb8rimqC#a2h`|7B5v0OR1Bs&l||K+p4`5+rpy4h8oJN z!v3s0TYk!GdA6pcR{V|QJ5F|HJTfPFBq>?;la=)=D0bG|=2qKv&5v`hkhpvKH4~OK zCvrE-yu)jB^{(L-<*Ig)Kc(D|%0jxQ*X`i0(iLGLctj3YWg*NF*CF3pDIwABtsk&Z z=e7yR{lX#=RJ*P7Sb@uU9j&{2Ug;}gAL91DTiLt11mo3m za!lAIs*uJBTv=`f6q%N{6xSE{f_iVBFW>$$Fw7icGD>$m220+y29q8s@ZA-=j8ETl zoiK4zFnA3rdmCWjuQJq8RL zVnmr%kSzwvZ&xEx#s`c#7Zs_OJ&mr&Wn75=mNumm&>P^6?oMy;SPr4G-K{~D&To=> ze0sg!lJ9Izh|ZZd^@J4MbyZ{n+`EO2iPlqu=Pm*+J0JFyE;KZ+sVS$(js4y_b^e6O zE{uj&BY1nzb2z$3K78T@PoOsB*)_WnUR9mHIM#FOTCx@jEjw0<^k5>{nxA z<`R$+%dh0{r28b1fDq(~Tg=EmLTx!#b};*XR-P1jx_0#zm!@}Bv7dTZ^W^J|;Z=mT zx3WU}Zd5aG?Zm;LP@A$rY5p(BT&~`$u=$-o>ns_Tp>ATsOQ|htYUV1SC;{H;VV2rw zRTus;tSGnQH*0-0*E#J2c)25K;&?szpQN&6x9_uD!$~ge8eE|Pw@r%o@8ABZC{*oC ztaxNNu>n^J;wW%c+!rFgJp5>+hkK-Rwtno!<6@XTj2F9lu5z{L=Ec~1Qz8k~;~~ZT z-r@Rd#KxOT{RaLtT@QSyyrebcFm-fRQ|dQ$FdnG#4_{>9hu>9$1T5fM4J0C(CTyx# z!AH2x&7|y~cSUkAd2-m;vd(dLS6{MPmq0EM_le+9NjJAo3@sCOkw2G>?!%&oW4IIN zfCIFVzV^hVXY0H-dNDhAnm~hGSU*qg-#Af!Mrml006-w(rLPF)0-1;_DX2f+h{d6e2tYu+GSoAvz(Sq&d#uteGSci{X0u$&{%Mb4I* z{yax#2XR8TJRFywnlJC@UiEC^@l*u`FBg6+uE;1~(ut~wUe1>K7M}FS0ok~iv>eq@ z+$9Q5sCIn5HTz-C`vCWn==tr}uMlc~yMF+sqoR3@xDang6ni;VGN)7buJ=)i@I0w% z8U6X`#Ax-PMSJZoGKUhjuA2?{(gf(1?dFS37Bo8O_sF;R;2O&zM9=#;m|k(+JqGd+ z&!kwgQjk*C$Jg>^hqyAT9MN>B59o+)BQGH&XaW?EGHX4uPWy1F%Xr5HTMk`)FWic4 zQ}Ko_*cD6>p^+iXH03(O+xBGM%!2m&HaKtMr=2!cq7^iHHpmo7aCy(g3qNbx<-nwhm`X3hJ2_^*Q|HsZPkBi zMrWJzn&ur>6TOUAOV&T;tD8>pbJgv}(>!lRFU{Kz%@$V^=!V%t;4BV8-#V9CN$>e`~B=y9d7t5$>wjdgs#e`$&AJ{#dK;U1x4K;2S$brK zY!X#m)fqJLQR{2R)(JwU2B&}((Ofw)QZ;8|bZOc(`+0D9cCm`~KRvmgG;OvrwxQQeB zEZcd7>U5zZ5sd2h)``|4on?~H-_;ulwfi=|9kcj5uAN6I`QmsdCIOT%IFiN|qCMM& zU^*m@1%w4l@=IF9{|*h7IAB?*Ip#6z%wOX)*2#kZi#9!nVLXBQ7s3`vUk?4|I; zawI|VezJ+evr<+84j)Ixgg2kmy~4t02*VfQ?cgeKq`U^o#$8dlYk;X$Xx!&2zT3ZN z7yl!OyxLlHn;@>-FVmAgn%PttZXEvUNi=6`s86^>n0!oL;ao_tNo7*Fq~5(G9H@9I%}~X_TNCvZ`UMWB`o-+beFyuYs_ujLJeen zxTRQpgop&zBSdW0RdrsxWSsX`s|V+{Ywv$+nWL_$uhz{FWfJZSo*yTo`VX$Uib!`2 zbG{A!oHMJO_e5FnekO6~TR7ES|NBENjgzV^Ti*8PpGW_cPjMzM(|sN*^Lb-F>fb9+ z7N&GZUdQ;_yiv5(H{Ghu#mGB@n1H?y0Cq2%b8j&00-|(IKJWu}kMjM*X7TCQ*3xr7 zn>9h%1$Kpg)@v%SJ$gb4u~Z1rb~_|4NoyvU0N)yxv(!<6(Y+=^+KX6+*Xs;{ap;(*;uU z(zR~{v=*r-&ju#f*y8PTGT44H`MxQ1=q;w&#d6IMhEOJvE6& zRS-}VHbAS4N9|l8lo)`o`AJ4$wr(HBGv4=Mf|>PKFWxn0XvV5%H%(20nGu*T%CT)F z0OkDn9fhkXWb<_FQLSuvX{b?TZv=SRD_7m~c-`bh5r^7#=#hk|E#)&|F@CRA4Q76` zEIIaY@tQu$wu??d*{nWtK}xzdNx5Qe)oBv_1;Pjf5rEat=y-e$$?RxVB*+)$U6p<; zxw9(~vr&PRfy}w8hxsTSp|q@YOcX(tZYy;ZHYTDN0kqv!wvj764)cLQop4)mBf?FZ zH}bgOfA`W;d{lWAd=!B)tQT*fe)@ODhZ>BvXeX(v6>cbZSA=6NKU5nzpr_S43obhH zLW1i^_52kcHF*UAYS5)*3VR-05_YeS6pHmdThlUBB4@Oz|9zO7craUXaX)4RnG-Q* zdF?^~0C+%qA!qV+@rE&hC5w@#zHh40^q#N6DUH$9gn1zQ7qOZ5@ciBU)Qh3r7nBNX z7-p=&rYH(~+ArcFK>us{5dtzz+TYzYP+yo3d^_74cykxv;tiCtPA!W>O}5feKm8|b zneLR7h(X*4i6y=t^Ew=kbG5TDk+tnrYbpJ@lKUuigg-ED`EkVeO&c}Y2j{WLf62BZ z)usi4A8z4bO{ls$(i zG%&Ve7Ao3-;$Mw*E0@yP@e?&AO`Al)vgNzIk|L>!PX{hL)woUrx&dF2M{) zajydY2E?!YJM%Dd=1+q=fjrEwbbOH}^`+>X{aZkQ`MwBSj!SqL7$$GvXl#80NJ!%SO)rvplnjU!5WZfQYqui-1`Zt9_u&nY)BQFimP`n1^+~f43M!#$;U8Y^E>Iof za{I#f=n2Fdb>e&zWFCiRY*nFf;L)$qo`%;cm+%*hzRrn z#k8I0*nF-uasPQRVoOaW0d7J%C<*F<4_aNrqTU`^HHQ{jb580v@P~jai(rFh^XQ-%xmJ+mXL9^_1G`_riuH(>dj#N8RdK z!#m1m;xe{bm1-gYmISZe5P)Wf%7#F3+~)9W6;)(U!|$4F_T8W$(mX$N$txoDx6tZx47GLwZc0MzUz~@Y=MzByVLZFd+IG5i2fUe zxFcpD-9ZMp5OwC65R~CWxl@?y!*^h1_c`l_&hFiFtbdAUVtqu}iH}jUteE6BWHe}j zEgq}W^|n=TVX;H-X5rS`Rj4jT?EJ+Cvre$u38(bgMb)sq?Hqz4jo}1Hp9MCNBWU+U zCf)C(q3%=M)1O^0_ZQlKg^FMO)5ymyQ`vN3Z{aP4U;R8D)s>BmMsqzQwcul>$UFhz z);9BElglSKao3dQdSQvD02egg zIeU8s*R#elee(71z2u~_VQYqjmepkTuu$C7QSIMFdC%_47oJ{g;{70BJ63)%%T`-5 z;SQf<=#^C`pYSS;;&?m7*k%D7^2VI52iBW^&oWDJfiT@BxLdMmF7NcNpj`ZKW>*~u zRZ^3)(oA%4Oj2>Ft(R(LzIn#t8e91z5iT9;Q-SWa5XV6vkFY~!zcjfa{qD%UrDB7HBhcFe+pJt=r1(60D;vBQ@SY%lm4yS*>xt(M zo=!PF__^p=2X?>f!=?L9{_<;}XFr=xW3`j&M!!a0M!UbQb|vMw`AZDF8779772U1S zy(GnjpJsg58t4?o)M4s@4Nsdq&293%X=P=-Q5%*z*>@WgZ579_^y>`k;%j>mLN>;t zgDLT)yCU-XouVvqN9A5s?t)#clafDM)YZ}iEp_LxiI+2$@6_9E+{0qy4;RnEEb*la zmq_W@egpr9NRG(BlRWYLm>8{-{J)%*G=^TXa2MR?Yt^LvMX&gv@oQ~64JPnK z(v9%Vdnts!t?b{-Yo?FZ-ZYD2_Rf-mq%OnMNBRC#$3HvQ=2bt3XkOb>sUxtanHaJO zKW@0yQY@TY_v?>kh?wbQPYp#hAfEidql*9Qi)iR?d4uGVIW)dG$#0|ghqo24!db}9 z9nF2M-;!G8BHA0ktn)+$m2e!$&+LO9UH2x;^ z%r{ZKf&J*D=mK-VdoKnb1k+Kpb7k=sG4{vSbv@JNfmVswTExi)%iX`pw1xSOT5&)b zfCpg~dk~!K4$N?VOMCmx)5`^ZIy}Alq33#6&+-Rz9y&IrW>qX1Vc!LO$zKCj@uU91 z`~3?0K}%=O{1Q0q{yo*#_^s7_yGBjVzo#m*f8%`TxJ2asm6q1-zHSL7<<4D#q6Lc3jGWnP;$h}!)cEPk&CLZS;SPh^cYW>C zbT4dvMc#JOT4x4%zBViP>?7H1Vqi&SiQzH%#v$1=Vv#-Eq2&K-Cc5GXl{+Vlo4>dl z^EtPue;L9EMaT*|=5Jich#<$*Uw zj_PmKdwu(Cog{%HKKMPlw7HrmKfW|r?~|+CSP~|?X-G!`#(o_R=a^!0&yRo};mN*M z&n<+Z$+EFB{l{}ZmxM~vNxFD9tlO`KqkMdwR;Hfe^=4oH)=&`uHTRj{SM@?KFlmu2 z4SM?f_SiC_zhcAsC?f?IPH&8FZMkB*(bz2I>wg2+wDjIvK)w%ln-q>;!k}XJRKXa7 z>l%5REOMC&V+}d3GK}S5_;!gDhg_PD8LTiT)L(7KX>E@M{tHajzZ5FcOzUmccRNAH#RGifobk?;>Ou-=jg_~LNCuzNfbJ@;8y9@T5GK-x-Bj1uU zk=Klh4O3@$j@uCt5W3d$4CQdn5I?UP1}AAX>Oc%`C#5l2`t;(Vtwp}AZF6$-z9B$% zblQ^nT${^+6p|f*bIB;waGh=V&0j%z)m%x4!hP2PUnGU672F6$I$!?% z*YP)hs~4%4EC3%` z5z2LHPAda#*kVe#u0!Ic#t+-B<=)V6kr@#NvPce;7jMCQ+Q<&2U8>o;QO&Uojd-3 z9P>gu6n;yFDD zQ=ewo5N4V)OlXwqN5X3+DS#9N55<@&BJd@uN{xZ@m}!aSeYLJJkz>`KlL#WapND5i zy$^T39=bLxH^Di`bxvP;7urAy3-!qrj%0ALoY8u5`;_Qnk}a>#oS zh{axoVSXTc!b?#vjv6`Ooo^e80N!dAMHB$`||m$%MP=zBH4h-F?qUa>0*t@ z+h#K?d(Ff*@6ox9(U$CiaOdg$w7oj{I^_zi>F*751GymZRdq&~1WCe87>V!KvXl1# zvGnx}<{BO^L!?pnJ!~spKM5OO55GZAZ^)$k;L5{bB$M;Lsy^H6xB~&{l#M;hnFH_f za$+rJKNoScWIc4mVP_x6bj+5aYr6Z+Z`gVXsGE36DumQN6@c%+Ry$dK%Pz(4`tyc_ zSAxYg#qKGEj;~|Hkb=n&k_lM~cAg}J%OD_Lt15343%c-Ut(x464K~g`1;09UV58i{ z(lh!Q!5)N}QU<0KO2!y=U&#`}*wu-%GgW(|h{5 zO({rEfA@ozn?ZR9#gor&UEmmi0U{j|sH#ZN)J(RmuDchh`Ed=H4l*ZcokWKQx1*=S zh#@4+QqUv$rdfC?CNFck~?7elmIW=W3;r+xw9cn=PJXt0@W?Gl=N6*6H-t zf2@yWasTdA)8v(r$fe3O)bt2d)Z1|3)4|-NN^X}bkFwt@pO-XFJmfV@C^W2OUHOhe z-RbAm&CnSA>YeeGl0mote88cqs4K^vl-<2R|IWZ(dtgc-Ro80_X{Gx02fU_iJ5=fO zkK9|8q;g+ z&sA=4Bg7~oUCAfc4MI@^hj_808g=Lxdi+{J)*r5M*bhT_nvW^z)8VMz@^|j2w&i1X zks-7sqyM`0n~~*ncVCT2KG=C?I9Xxyp^npM8(eI!bHIK$6)9C#3X=^E8fB7Plsw^4 zS~~$oVoY|%CFT~>kl*_R>v3IPuSJmRr7;6PYK$b$>{Xm#f7lv3H=2!d6$7F0m)uh2 z?gEo6if9!Wr*DsCyx?8wi#T+YQyjb>%l7;UhnLoQKptQ60tg>;X^!FryT8U%e!=At zZk+RdEcU=uUcfhDfyLvAs`6;D(j8`h$`2h<2j*iA1ecp01t_YzV}XUHPUgf{OW6C! zq53wd2tQ*yX1gxq`{eB1TfY-iGAeSt-cSX_>w)@)0#d2o_+&t%HQZNiDKzYBbv$!eDyoV1==Avfnw7oyb?jA{gttU_P-`-9 zGTgNJMZBSk;ahe7Dgvq_TyM*6%-5~Dv0mAwInt_ZS-OFiv`%wgK3h0gL-4i)LVpk?tIRrPjnL37xZ&6Dim^9E! z`2pJH`dS!ua@3{mxcyPT&V>8FGkjAw-TGMa9PqmCt}GpxPs@d^qB$HvL{3B@Y znPm0A9|CS%)-t-(+smj?=Y>qi{7&8r7AJCp)9Yq_=4dQGUax$0O#jBA9?CHex+G*; z(8x6-wD?9aC}ZfCmcY@;CHc5AQq(VV>nI&Wp|0v2V_yNT9tZ+l9{q$?W2@0J!lBQK z8F$Hgj)Gtl#n zliSHnC;?0^c_ze=+%#@Cor)q~REX;P3aiI?q?7k!%M;D~Z0$s^HnLb&vRmAifSIzz z2!I3836e@sdvCINo{)47m3>qde?W~g8BV5s6ufr4VC_JMeM z@YAvcY5Fgyj2`Tgv3XhXu@&gL)BcdhGqIP8+AbPoV1L-gU*yl$$W7eL;i;b8R;1#s z(8_^5JAl=PE?&rld@cA&_wtxj=4mksyr~55nL?l_57Db4_=iyPBSf1(JoWRsqPo30 z*`uxip*Bu}%K>l6TSFJ>Be7cLI5hQh;x)wZw#=ljREHYIf%1@--{F82k$S0B9?{0T z^y&Ha;kxnzr;>CqX?Jh5x(D!akp#~(kw_twR*RcKKV=XYz^kncsrtG2+t;u&NigOw zvW+da8%+`f_Vu9pptNEI<+dK$J<1P10-DBfd6D1F@S3*F9eJQX^QFhQa$9kq=Q;rh zCOF9uz-#Js0}<5ckqe$Csm+l@<&j~U#`nb~DGCci4v%lqg=;V5s7_Esvudsf!qpM+ zejR?Ba3^Qp<(Pkz0M>HL{Bs?q?cq zn9>EF{^+}M0hh^&I)S$?YeI1dlEBtNqtv^&=ZF=6Pa-v#H*4-&gC+?qXXL^bL=&HW zW)iK50;YBmcf9_dmR*tTkhsH2(2NtVDQ#WWpnnUPv)A9$3BlBrgv+rME_I56G-TNbg{}P_dF-(LLZJYlV94EGg-7Cm+rm3al#t z8cdR)wBNro>;(@i_c$9T?m`GdOm)_X>5o3${av|&D^=fHafg6#gYIploQJA|yH&S_ zO^co;DWWX7yG0g5LE;Sz9B{(%^zFVJHg)mFww6EU<~sz-qV}28*lm|o1IxM1ZDLFd zcf2{*o>O#(D*{|%%8XvN99A45ld>_7m1nF-asSSYEpa%4vN{p1CZ`9M@BhMwDjuY1 z3Y!ftF#4aqqk)IMFGH+~cSNT0PAJ9qdh%*)AOJ`Sq9Ev^7Db?Xk##_xhW-LB3tza5$HHG2Qjkh|H6Y7rGQ_`=pCVM(t`)wYTk%>7r0_C@B<3 zDJY`w6W7`@FRmHfnYFBtXoB2TX?+%+2&8aLWNN3jk69vO`W9j{q3&!J1!paJ1?^6? zMp+|9QnL1CrH(y7Ji`!@Sd*%#{|)I{qF>5lk^I(CxdUyFN#ic6Z;y0GxXjy$%&%KC zNUJiQl3QOo?OD}BXvuG|AjH1B55b|WTE*-Eyg&_*P153~HRYg3sEavtmz!-0&7W`T z<+#&B>V9b&vuB!qDE)mdP$yyoTtQ2LyuH&bUq;cX{^L4stHo;Qxnix2VLFOGE(u=B z+*WfTL#*5Umr!wyp)orZ=i0mllf|9*LZ2ISBppfKnCoLdsnrTUPn7zjs*edIlz&?K zt)NJ$2no8oH+O2m`GYpVy54A;S&UQ399*N!)PuVDnQ;rw)u=O48_`~NI>b^!OcwI5rp72tM(Ev) z$opQon8!Y$N@hGt=g?+or{uqeMB6FAji%EH1RL%Q#{IUDg|t$cF1m_nt|=*sC13FxdEzvRpap?m0kY|@(gX*|G8+nt z3t)86>uQ_thO>fM{MjO(=zm}5UM^SK(z(AmeOmUF;^J|u)(*H0Ta)@$Z;w5#j9cR8 z{D3Ht{db1L0jq=>+?zG&Mu5s79=?&U%H#2y{hhD!!)q7%^;%~LcB&CBj}!Ov>>Jjl zZBZ6ZAvURN32>k+y9AJ>Au~1|%IZjw?WM0Fl56_)2eb*N@0N3(titWBPg6LhL4z4j zLeG!322s-?E_(@(E3E=sS;<|D7xy|c{;X#va?j>J8}2@HdvI31a{6y~c=9lWk@5iO z?oo_tNhuhvDwiMbS@HH(kF~ei-!Fyia=hrM7j9W3BB`~lvhWFF(KMfZ(0{Xt1}HMI>JA?B(BwAd?{?8rQu(`F*BJR$yYqV?$JFI{lfar z!mjMt%jI0Jj-SFefTjBNzWh`o%%CJ>)FJNX@|wluH}uWK&SR&L+@*m7%ihF>tMm5( zwf^_57aLB8bxXb!b|?WiOn_g+=%)8I^eZ0~ySr1yLT zv>oE~?@Z!?ED1r-Rp(nIv6_-l;f1quH#D3ZQf*XXp8f9DvQmGXTu%x9zC6eEH=j^K z9HxF%4I`9vE-2TI`@%Rwi?y@7vL3Re@zgX6xTP8!^$y{B+*LkKKzLyq)QUq?)QnCP z{I(VJ1?e)6_M%y3>S^DjXC4+3H@|gvUErv2;Z!~RVS3oW;<>g?zcYgGC&CHn2z6fC zpT^9tuw?nPzD@_Z#|G%J9H()KZ?!?3SH#!^ zUs1+a#^gbj-r6cw)+1cd$Jal$9nO!wp4+C~gh>+iy1^i8(iLoNns6OzA@=T!wvkna zyyTjH`h9k7%L?|x*aXP4#hERv@F%9kW*ht|j#2qnS!bnYAoS%e%UMYCzHoT;wPW>o zQUh6&luZO$KyRcTlDII8*0VU*7`)hKR!AqNy}7_u>SNMH+`x@y&85X{Dmf&iiLAe* z*fV@-%VO(;uPYmq{ZgI_q#XN4E%HM|a;ZJqehQ)jN61C4o8lDHN7+=2DxZY~4cYh-# zAS3#lZuz{!7XYCH-kDUFq7A|ssGn8uVYTo_v9ZzFn;?77hNje^8*%5fzc;aeYVLmC z^(kUw$iJfaWZoeU{Bv)oi+($hDS^G2BUdD|bIZ%=gDo{33w4lPkyz>d;43S5_2mVl zJFD=!Fj>M>PfM5u0K+Mv-oR3v_cy0*dMTE06KxvyYxOKtOwUfKPb~9_*Ce9d9M0Qm z75li$dz*`T#jV`bU}kYzFM!LvoW7oOs18GIQ~@~{f_G`X3+#`k|DMz(w8fsO?kTF% zqlFRPdEUE-9zdIHle`_+s7z%AlVx9WoK&i|9EPVTY{D}t=$Trf(PPe{sw$;JL^cPi ztC<~vuaN>2A}NQTjS5-THb5QT#yF#(w?W7G{himSP6)?zYj65H-s7AM;!tAK)SFH;`W5x~Xd zZ%kO!13htpFaHgmS#1An%G`fed-kTO^HuE^j|Ajynq&&*3#_Oq5<>{iPhSV)R00A- z&Pv2zYYxZNd_kX4eX1Y2z+d~~)${QL#L^LiiVwV*w7?~1xOb-qPj5k1%v5M#&V+>A z2TImFlWZb<{9R(>zUUq;`QMpolb`6R-0>J73dQ8!ERM}?{!uN>LG2#Gt?Yq3131ox z=gBiVx3$pX^V%22ffNjWo7eL#VFA2%fgSa(~93a{?GL9phPR1&>b&`b9D^oZ_@HQax zq#v3(pGJ8wcMf9hPdS_7xL;QD1@(E?{VY{h3vhbayVO-u9@djCgbD~~;1m-54w9?# zhDXbiBT^W%Yl2>=UgU{Jt0-4@^R!S+p)Bu1E*Zz~a4Erc&f0 z%|ysg2j)m9paX-1#EFuwD`pzFEOB7Xh4`};&rXk5H%?2SoBCDbwKJI<2%;bn#oq!(_!PT_*W) zIl)gT3*qr7Jhxn!iTR~YSf?g(>nZxzrECw{%Obp6c{-J>j-N6nIl=yOr5WX*)|3skVy?tFsxu2Li z5_8#;+tWOahqK#H5Horl6n?qIsw?n4G+k6a*ewupqQgWuV z*j>cUEU5^E%`@5d_3$t)4nWP;!(MBexxj>HVeILjm_w0`B0aom=kAwUuUWY9M8s*y z|L2^Y+m)RXKWT;r~wO{k;DCH3vtMPD*KHP)o z_MYFC7WjuGfH^`(1t#i0wR@t!<*mW~P==4|^4e#VeT{|cwlB!M(>S2v&ZpNUluO8` z6F$B>flE-j9`Q?c7PF*^?+~m;?>?gQsItW{wRzk<$aqP)A~LF|?vrEddD@;QR0^${ z#xgFB=UqGNJZToOw|qd^aL~;2YueH$+|j`U&1$>H(wd*&5|ERnT6pz4NLiyENIR1H zYV`E7EfjKcL`q-8DF3#hiQM^e*r_RSl&4PT{S<5)x5HTC1qR2J_G-j5@!Eqg9LGO{wI3(1nYcW6 z=}wpWCZVP)ND_78f42D3*A6(ze5qgY^p`rGKEvz>1yVgH-WLyZhmk+G{*t7H;g8HTav6jJ!)WjW0*zwl@%~Rl zXzG8NT=E2Mm0ByU$CyYaub|=N4anIizER2=a#hKP8_NIA z1el<)`s-HoJ2JeKcM{C4(w#Lf20Ryw@tZwn6_G>GB2AyWN!Oj3x*O0W<5OtPn5RGT z>la%3lL1_ZpOz={N}`-u6N#sAprd!(#f;~Z#aS^MuyP<$2T27a(p#XfXWV`QQt zxjow#@1R-x_Upp103sCcF(WLVAe~VaDLzl(`1$E+Te0qyTfNkopO75OI+FBP9i;lc z2g6px1^q~ue`m@$(z(PuR{^Q@X2*j`i6bu2k6k{c?BKMFy{yAmEVZ#+OBGdJ zo1y!lI^;*lFHob+YO?Gs_j{ z{M%LwW;TNkZ0q>fD_9in4Jv5yd3QtQj&9y&>{l+P=ZbY`Zy|Toel@&mrzz@^6!M!d z7}q)`@*T_2s~($eVg2@`l8t$;SxnvNRuAt{;fY3#4npswud;bqPoXuBGr;ak@Q=#a zI~F`!w`XwaNx|lXjA*Qi6-re@d3xGLG}Q_j@wR0Uwu!9k*&c)jOzJoU-^TdbcszD~ z725@mOMM~fmusBvbwQ;oumvs4`CRnD+`uWlCaDYqC=RrJc|t5q0Sj4npp@YIpWd(i zJ|{PeBS}_-9xSM9=gFE5{z(=4WWHV0q#sdZarOCA9POje$Pnm5l za&n@-V!vR4-Szv}D4BqW0|~9?e9RU8z?1!V3{SsfhNs81qOQHhpjbtS9|}T)j*WD^ z_Q4Mi9xPME7lie*5$~hMEn;)=lMsQszBb=- z@UD9Ley#rV0Irqmve$dm(3g+Eu^>gikSM*sPn_MfuPPUc6Ac+RZRFp{=IHBWtnJT| zpWE2Xz$d`$J3FR=`Z%?R*jFxvuD;`0C*|nTO-P4*Y@hy%uXWdr?(-t?dzi&8sdx(+ zE0`R!!g-@xnF7!dh`jxZQ;9}GliV4s*J)~AN^I+3(^KRI0TN@i(x_mVmGrKr> zd)=@Qq0m_Hwn=TKK#qM+G)0gECg?07<9sMw_&Uurn@O*-g-w0a5Ud}Y*Y`D+kb|jw65R`3}8!TVq<@9n%;Z$X=F}ad6Q5Z!le` zVunl-Vy<3^;$hv{?SYgAQXUKmV9Z)vcH1HwOeGlG;>hfB-L7z+P^T;4_aQ||;H5Mt zUEsy$g%rpCu(s%@!9Q;TI^+%;iW2#SUDN1_xeW%$Dduy=qF+}kC>tm zyy~nl*q;J|V*B7TPv%*kOojcTG=HCP!RS^;S}(b5%ic^?>z;YQ*!WfkZ-JVflBc;AjaZi?2##dr*aX)z>{^j*&n^e!g_8z*zFEoUOJzJk*prn>o>~QYOTpwd|LalO{hAh@^M;;m-~W@ zBE2~syTCnM{I#{OA;27^Ywv6b$^Z{ZXa*O1SQCH#tV#S(I|wunlm1d7@|p(+f+!6q z^{P`&CGg*iHNtVo9q^l6F|G4{&Lg|aPa%tsrag56LL{h(yP07M$YPsb4}YH>?)L-H zf{9a+rDeYb{!E6S|39S5r)fmdPdfk$bus!tha)}BI$}qF?+7I>6Vx_|m`9|Eftjg- zA*a(2tZ-93)Fryyc}_2>ru*a)l0V^U(ge-Wm3@vN56)Kqdc#=GJ1^SQTVskxY}7{c zrxmf50mI}*)preZxyOjmSV$^urt*trQu* zD{XqlBoe^b;J3_(Dws~uz{*c{AAvbTZYPzJ5a)&*E#>Os+Wgk+o1$Gu%D)q<_#Q>3 zd@knwY$|n5ujvstuk1{-&3OFrAX^$ohI@p!i>giw0)Rz_bqEq=m zY6!^>Te5N!+oI_OvBHpjm+Pa1w7|3>+tj!I$xo3cqP zdOv^Jt=`DN^uC2Wu4w;IzpnefroFZcK;T_!=!S7$RTY;O;3{7gI7C^N^dsgS*A?q6 zRum~Wg!`@}PxGr3gJi5pv4+k9wacFj*P-LG5MUkQqP~aohIs6i2Z|ebs%f9nF8vX7 zcT$+!y;T>eel#8ZZAa`oFI=*&s$lvE0E$fWF5%L9C%gyCwbr>|6bgflhC231-%GWA4oRYbsiR|~D zJZK5SD0Xr&MI$*>MF{83EA4a)M|^P^oAXmIQs-NBwHMYLRl*4l`Mjp-6UkL@d5Ro0 zMO`oi)rn-Ia1wHd@7GRfG{tL&%eZBTzB}OHLviwCw!G>A94WrU&lMyO_PP!Zeu6?` zo?SdtvBgkWiTKm^DDmLz5d65`O5sG;rch+3f$T>KA}GEF(1vxmM!1HnEJv@(D1KGzGAsidP5kwW*z+R8oNG!Kc{FTKp7&o7wC2SD!$m8cg^BHVpv z4ruHYKqqlz$O4tXMqSns&hj3A7Z{5`)CNsy1m;oL>rJ-cu`wADO7wOHWj_AX zoBKA#&EdET_<(usono2m;nR+UCM+a&XIE8?Al0qBT8!H7SbJY2nsAK=H#P$%V#GL{Z*d?t;Jy8#xb+VpMLty6x21>Mq8Q!@=1_GEBP8iF@sMK8Cj)Hy zIhX2n-7>b^-~VvCHki~>^6J$ggZroB%tQp{y#r(J(xdE$q~tKCU|c-vFl5(jBLD3B z-@h;C){`5${CP!z88a}=cn8wK2PbR(EqkA{++24>+%UDtjP20N4aGj@{yBG4XACe? z=ulYehz}-O*?aRsdbAx_NxwqhZ;lRz-mwTW5p_PNgbm!!JR_4@6y%>a+Nwu#1d6G3 zd{HC<$|KNWuQ<7_>V`isY8)^7QltMhvqb*0&j#Z%L(S9$zYo}!D&wryn7U@8KZrIX z^m7O>{J%tF-$33}XZ3($p(WuD7!`KA>0N6Yld#S%AMPX!q~_gMH;FNRDI;qS7;EUT z)N*H%EPlAlfl*HCnr2x@n(+h+ZTegGZ%yu$o+~HA3GcICenEsxD$dP14ey}c0iP_8 zn_5x;yZ`6m%;H=52H*VVn0ZNs!RFM8rtmHc_EUX=CNYC#KnSBT^cU;ma)J%)pmw8A zau`2lKoo%lwzI5ntLoWjDiy(!jD{*dM~{;~!MMm*J%BxJ0Qk*fb#S{B=U>791A>U=jLocHlHEWc-s#7 zaS{JyYxs&ip!;|jXyD($qWO&!%GIf;V02XnG%dJL(VhG5d!Okm3HTAr5SWwDL}0=M zRE+DmK+@1=H*R{F<@NqgzMFmDo|q=`)wtmlw;k}oW+V~v;}8|QN`jX~ii4fL&tyfb z{_MbIo+Y&x{#n$gq$xtbT^jb^nH?1@StpX{aNdKXHV)e^XklI|XvIVTB&B7~XCDnW zoS^Ur*r`}mAu{6@f~8pvKLd2puam6tbDm`{TytI9=)U`YVt+IQ8bx296o$HfeE(16ZWuhaans~?ou=1A$yZZ2shxSJ zmy0z)Q7cSYxS_!`9yl53`N2goUsr|}Ne=7bV4zRY@SDo;2iw4V^N(=K3+HMr)n_hR zp6&;BT5w0Bgj~ZSd0Mp&6|iD}jK`P{AUEJD`uQR|M&DaL4+|Aox1h3i>z|pW4J^%O z(Z=#`rC7bXehJkHMX=Zx?Xf|k!N4Hk^ZNhZ1ol4_qy7&ytpA^f75w^g@hiXEvu=;W z|GzO#|JVD0|4scry9#TD$!T}2g_^@S6Hq9FxgXo ztP5V}V9f%=!fs9KdEZ`yKN#wVczD0NC)9NLS0yP8KY6-r*@1(yH%KH46(#5*3!x=U z=}vxk1MePwPTfu@9Ni4oo>#57^U~KOlJkiMx4D0l=xijk*C_Z!R+ZLRl@?c~_yHz? zc?yrptLFNp%0yiFU);S{TvJc=2OW?Chk;vYcI5B9`5X1S3?uuET!647^ymeQ*1fczZq*WHlC%R)nZLzmOwXre>EFfyOE42kPwQ0L2Ufw}a(@?X6RT7hf_e_CYqS=JRO@PHUWEN! z08Ns0bD?+f`r!a{sqQFsDoMMkhMr#40A?MqOIyf^`buT8CO^XQk3!vXrt7u1gz;Z* zuS9vTSo7FFCL1(gA@OigBAG&q!DU8$*raNMm<;D)$~x_L)Awf}4eAi&`ujluF2@eI z#iq7BWU&!wvZ4@IUWOidZY6AF2;iDS3SbLofcc-u!2U5&QMSmos5x$X8yJNl6Bo?FEuRIZBDcCL4Z>3MWe-W6BW zcoX|b4>MAsUZe(=s9&zEb^_>^fZ+|jWUW@maNnO~#`pB7|} z3II?8VeJ8n9gF9uiL4MnLo=^_?A`l9zVD+_$`6q%DVWCzSb=7E6TO?(fCl*nEd~_| zc7b1=gZdL`-<~0&V7!aHKZywaX!wYYh_9+uD*HaikMz=c;3o0j(E7zYwg2w_c*s{D zNEot8F3fXnW^O??eT7iT_@KcY^OgO?un)|Y3H;L|N;aU%1qng3HL>PGRq(Zim}ud{ zwuwnycZWM4wS3pQ`JF_lRnggWF)CXDajZ73-lmjB@KP$TFn+NklB2B22UixDZC9ef zRdVvAlfx-?N%7sB=ksEJG>%VBi8PPpkgY0-cbIhsKw zO==Cr9#Vdo)6%IMWMlk$bPd?4I8%NTCc8kjh>uV(7GUmEMNX!Del?o<{R*+GvR@V2vIZ-3VNIHCgs#9YV*GLoww`_n4w+MAi#iv;aV| zu*%E+7A0R9@KO?>0)7niSW9K*^?Vy5)yDQ*#ikEFJU)16u+tbbJcE8LcU^ar0 z%>+I5n+hRKOGuXuMRtFn4gQ?_dRwwxg1he&!p1`7)6ge3KA_rsNa^@(kCemywUWV+Sr2HmHAse5(%N*Zw3>~iaxkH zE~gxWr}euQXvWY>KQol{KTZt8Tj{Z`vMU|c>I)Yhl<2+EOg4La8dCp<)Y+^amC4oP zgFekTej~5joCtoUb+NDnL<~$J2|`C?s%5>4^B!LLvWAWZM~aV-jqveNv%TAj;bPm= zI3ZbFLvW4JHV%Gnz1r-XZ^(a2fS}=ZvKRnKM*<*t{VR^cn>K7DIFS}J*?##wVz!Im51vVp`BhMf=f5irN`O1vHedfP$Eh#l<-E3$9Fe2pD017rGz%Aklgd4QrM%9)I$ef zJP^OW2Ck(Dtr_ikrf<4BeIQ{dZLaX{36=+MgcK*KoT;) znMDFuvwAZ?=m#xm>|Z2q z8|q3@BC`;^m!rWiDXB1}mK>Ye`o*iI53XA4<8)}EUxKH6_9xK80n@))Aa^pq5aOLX z?hCAy`K1+-cDDu`s8`N`!b_XHafjU#@ah^B9nA=R#g4yiVqHI2EL8H#G%N`FA?WIh z|7bcEr@6aqF5qwGiq#>YoDRyZW=f6?!Mrb!*oFFg3)m+56>}?n=B2l-DZdqj*8i@I zqL<9T`~0W|3@;Dj)03q|)e?taUh8Y0ULoj@-V!9H52^I4xZ-7I0C<2w zgma-HeZ-jC1AfhE!v^jqPPrz07tPeggwkmoqYRtj`ghvwMGW%Nw;$H5z7l?)pdJ^* z{G9R?ChWJZ3kd2WrUS7i#0fX$dk5*N$1$&_8AALH7Nz-^${H)%_{}z-9hA5qcz3Uu z;nCp@K|JE{`RAxu-)P<>&O;ed&Ay2tYT@#?OiR?4dg@d*y`z z#Qb(yVEf-!!)4fKbI+Y3{x?8%fPJYq4s)L^)l;V->C~)r+;MSl=ty9X?G(82T?}u` zSR|-x-l27!{Q7<+P9@gRcbR&j*roun>W0=sFClqv4EtzI`ZN|N>X3Y+?Vl;Xb89lI ziZ8}u5$tl%dMz1Pw$2B<)wgNaFizPu2$zM(VAxr^A#MF^gTX!|_jLsTgZq8}7Vpg` z9l`XeJ(~sSU9F#1&S&49-%VcU1EA!glEL*|#SUx~fhqms)30^X{*9iAwA{b9$wl~I zXhHYK8mC}WxFxPcA~b=N?zj+{?T3DX#-YMpZ=UFkV*)J;EFXTqe`(UtZ0)r8RE1Kk zd=7&OS*!*{LoY7vss>3s8*v*^(s4;AtsBH9RE#5)(8GPrT;yLS04 zd2^a{@z?!qm3}2f4w!%~F0Tb4Qozp0=~;bBM$J5*-Y_{Z*N@OoH{Lz$~1Kcq6oaeRF3k?VO-2$rQk zR!{r|)>Eb>`NRH#FE#V~9kz2Nh0D5!yJ8jWNw=_@PZpGvG~4V)WRrSbBlNACCSzfv zV4MN`Gn^glqy>nFl>(q>d>Em`a5lWuK{Kl^^a<7Z{cEFoJGmEgKSnf{eIP_piH>b_ z$N>~Q0%gnIG^?DFMG(HYi+nLf^h#;Cw~8#q^-8VRz|^O$gHosrJyHwCg?EmX^xnPz z4NL6IlQgNV0XIWH9n2tN#>i~Dg-?@*So(N;rT#S&o-Qs8KF#SpMYC{tizeWNf}U0) zd?QL{Z-SU=bbgz4q?qRO5Re;2Ga8JdB~_<+uU`C#ay6myAuTv>ObUaqy6nNHu1*m4 zmoF7EWzmNZ?GGmEF|fUOOjo;5W#hz)IDdIvA*H2@$kqd-y+?DzF_59tKVtPTgzi)Pp zE^BU!Z+^YIm5?6)+t>X^pKE>7jBd+b3595D-;^13n1{bb&E_xD?K(STzFCk9?$sK3 zFZ#FE!mGPN|3h!}phU`^&P4&^_b)8RCV|7>g&o{v3*tJ|0}bLi_N$IQ-=$GsAH7yj zlG5_1Y(LNbkH({6c9G5HiA~pZfG=QgCV+~nfwL2{x;jf;9U1r8ekbf@i{&{EO3m(Z zuS6q68a)7KSQp4=WTjBsVhAtqBnQt%deDu*AWgL;|Tf_H1gsxWj^`pe75ib_*LOyvC$ zf}N-IJN|6#8%Uh~ESw3TX|XlEKyx|Z2qBo_`!frHukWB-$2k{7a<%xn-@Th^nA6wu zG!l#}k83y`$4M{qHsU~76=XYv*-|ag)8z(EhMktBm#y8AgXjGgGse(wdASZayCpBx zqg@qSm%dLVM)k0|2{gNT&A;Vg^>r-0O54^ff;S5}o&{egIvCeijF(*Y6Tcn%1pt>_xQ+cA1*E4u8M#P)V!%sPrA3 z3yJS7@&?p9%kL1=U)ETlpTD`lHgEg&)YQ?sAk77DM>$^+2uoI#r`ymX|6tZv>yt9v7^9r%1T8* z+xBYJ#f(Upj-Kg^kiY4h&d0u{4_h{0o;8&tr(GV^*)uM8uz$Ztnc zjE3t$aQdcN|7c#p>7Sn33;ezSIy-fz*1*BUHuoK7Aj{-Wd#sa2k5t=8Vig`-YzhQa z3qWJK_bF0?QUaCtz3}SCju;1kQ+1rpg$XQG0@a!>_f>f25m}##9UM--v^Hsoa|$a< zR?Z>}U(4S#Vv@Dl==<)^`t-4S7hT3NwR}{6YlZ-hbjagdgRw$C0Kl&r!Cxl_jJMu0 zOMbIG_v0{vI^p^^)h}7Wuo#gig11;~PbwspGGjD`Z{92O&iOxsBmV#V>A#`>XNhKQ zapwF4)>^o8jq{}`y{6ACZjWW^Y1cO7GqKA3I3SnwzabzVmHbcG>1y=agDo>^sP9y! zkFQsp#*tiH&@6xzfj%RY8)up+5Jyaykelk~3~Cn+Hg@Z>9v_Q-jL~WPf4p@O+ zBBFOLPsEsXFYXq{^%35{P}DBt=SUn>EY=pob^mYas?cg6NYX^H#u4@fU5<_hS}aOk zyuy^!W`PA++%Ot$d#La_I)2v!C|XEHCtcLQO>Tya-7dd>=v0sTLw=qe8g@;)nazTY zj}t}mhbM0?Z7CR;ZDyv*X1;m(D+o?8*=xSR>)zI(0rsM22YlGULP@fUu?MncXn)o< z6>&Ld$JGjSeOdH5;ob~vlj5%TEs+mT?YhM>jxT?#P&qA$?^}U-ldPx%Tqm6oZlE6vS@Xelr>Ja_$5*jH=Oi+!t+oDfJ zhteA`Cy9)w4QKL?IQ0V5ZtyFBfQhE1$~)J>I7TI8 zOE2#6{VE^39iC&r%4@1lOMf@;7}K1--WlF3!Z9%+=8&u}bmz zR*rTIp3foX_;_gGplPl7X3lo*?tLv4)954ejz(3QTgeBi0A6DE4$1sC^79UicivB} z?fY}Cy)}#g%cqRoRn5b?q5G&YNC@)kdql{>xe+p5PS09bzEJ;t4k^tp0l*Z*2YCyccm7FJM)8Y{ho)eWVoD`t(SDC+`V=X5OIVKt=$#; zoj<^R{t|S(d9?#p{O9Uvnu?xc*Fhjj+lk60fz4Q*(T}KUL+BrE7Pl8uG&0HekTNG% zMC>l!I7j+K;sd1p`AAx@-Xur`XqO(#j|-YeGpKeoboq*jdG!+7ZNh6^An<8Gxz>H* z&S~KCB#e>TNoAwN9qWL@sgjh!XNZvZ3^`4SUE0W<4=0XR_6iQ9=dF*0)E~1-4)RvZ zX$WhqvKe~bZ5VbWysqz$jxPD7y>!8$rFuhB{FDLsmM1eY*!7*`+_`)lk+BWfh zOCG;@a;0|YkU#TVFwLIl%hkrtU;Tiv$Kby# zsc1dh!~LfbLh8J8IvGopCX^B}+2l*$D%A>HfTsXruX zmFCKs-K2LS+tHMtmqC=iaL(zL+y|~3?$?!2HVOSM!+&L;>}i?NvJEn0rR#P$hoi3l zE=s3_{|bI;=;8OUEISsIf~?l>Km*&fs^m*}t2Zu5o0x!W-MTmO*C02tcdB!EjalJK zD*pgX!%Aw|IUlGM^Gr4clFYXktHGgEt~p?9XV`#Dm(N&R=4PfWpTMP_7NO?_zH$e6 zLliFFH>o@Ad_ae83@@c!!qh-qEKu<@nEdVdPra>m#Hd?C(}wsFi5qC0Svyg)%zqo+X~ z3wIH1AQmVc!FMF*2Oa782hVD`L-i=LeqQ6~8{PQZn8Jx zu)R;mn^ab&o_QY3S*bb6mfRQbR5%T;jzYI`04%Xrlo0S6iL2y$l%LJFseS017EEe? zGE^r}?`V<@c3F)rKc83HTkfrY#OE;eb+E924N(eS%CzCFtfQ2o9WT~SyF2ja-m3QG zD}h;9E?Th7NVhJ1BHGu%-2oACi4Mq2*m6)<2lEADoW^MN+Nka5Ue=feR>78}q`6@4 zZ_r(NX>q91;ntyv#}tlv<{wQLk_qgHnyS*HgpyTIkFjvh#mg}{6Zufnikih)f$#cz z(!ajMNFVMh&DO#%6{uNWWK#qBOQ^DcG`8KU!z2h)Jn|usx6AfPYxlX&%)-*(-OXsC z#4FD%!=D`HXium6rJNkIb4k|q{ z`lrsoOfF9{%6f9P~ll@hP*^s^`Kw^6hO3rEU=Nda2oEgQep0vTap#r$~ ztg1iXi!dnpziI(*G6*Lt91Z>s1d(s>5dz1c^hK6X7|}EvDBP8*-jn@NdbPhwm$xhK zEzZz{4^C3^9bNZO)(VM!SEEHr7#siX=tB%C%bC>S)mh^HfgrO^cHUo6X{nolIj}CZ zzmmkHE9JB8!K)Cvvp5Hg@6LXvA7A?>Ty??aaFzT4%lly}N?O7rNq z+GhINhRKUF*`s2Hi#e2hweP;MuZyS6Mt`5NLCUK>>-jniUby?L*LDINuv!Dw)gjds%vmY1M`BDhL1haVv zp*|%-fO3!x=2?(OaKj*5W82S#e$Fec(mg1V2WD;E^?M$m3n_xQ^uhSY=Lyi*?T$b; zPG7*v`@Cfc47g{vI8LyVM4X?MeUW0mKJ6Nn0k{EZG<1XZDEqCy4Vl-xwp(~5D~4?G zCTn4Vmk{36BK+=(r7r-cej=AbxeeeTT;B5Df?V@MJ{q5DE9k%Adoy{XMSt*&#b&{X zdP3XQ@6$5SwUw8T`D$U-5aV@Dp~DZ^dGEUf-Imk<=}ydi%gHt**NLT;*CuS$|8;#l z^cIPQ%!QL^AN-n_A(hlFmT&DmSrzvxt@nYA(FV7Q%L#U&M=V~0MYIB=9&{7k1LDAY z6{okxCp7T6TkCIAIT7M)r&XHPD(UfuofuwOftSB%XJyG{)G1HmKN@4eCE5YyxA&)` zVCzKny*j_DaV@^H;_2{NbVTFt7Sw1HTP5LSq5Gg7u^gdl%Exx5MpDya{6|y1_@}qv z+nvD1`T@FyYvBg;zv6942J_4;W^|f50Imu{99du7EfH6i!a?RW=%?J2J6=gWzQwwz5+G^rq3=p9PTR4{<@qYRXoV-Ossg!Sg)$ zu|spK**-D_zxVm49}?>x5w~O$2M@w%x{C{pW?$=-8J-eBisf*;rgcAQpq|K%Qu|{& z^2k28g2^UUaCE7C(_^13;Rk_VXQNnR&Zo)uckztpuxo55wJ*+s3Dy%(73@513#h8J z(yy_V;MJ85(JGHv7+>~e7h`eOGW5!hoNqQ%3*(2{{@w|3~vX zqCe+KXFH_EtUWSJUeWhs6QBZOYaLawSy4`|u&`j?O~==1_~+FEo|R>$59pb5Iyvbo zUeqw?0qjrr!R^Nic)Ko_M8p^Gkerl;1oAxPL|qU16nX0iHe zDNf@LS5kjqq0L_6o>R=ceO*GN&Ta0hC`QjTY@wTM<_2&#cG^)Yfc2?zj4GQ*v@@}H zlrPSw-oIV(SD$e!WUyPuQPpS=q`iq=N`Wv@S)fmetA+5^`QTB*iXoZgV+L1MBCWf( zj9YOM(?KkULQD5r>IdEEz+Sa8E8O}Y)b!u+qz)Snq7SCmSysg7l8dX{xCz#7bQJ;0 zg*uRIsQu^)r%>uO7hk|ZRA%wY7FRN06^E{fbRF|5lxUD7^FZ774s9$twFypUlKC8yjMEt87=iS^lHZDP@Gzki)wS}l^pfh`a40aEC2PYKMq#)RU zO}7(;Hd3_z(Rh9`^K6H``u*)Y`x?q#V*cSmG)QzC%}~}P;H9^;HG(qnW_?Uj%?HU+E(RdAF`TKY|=pWYYk?9R2P5@1S5E^OQ?W_hvk1rC(|&CzRY z0iez#pn(L-$7pmZaKUE+t-hbJRvZ_^{84ywg3>QQ?FQV+Fnq^holQGrh9M%bI%AZD zFkJSA?lar>|7UkE4l`9j+1Ft(tG_5=)Qf;>PKT-LM9RXO zP4l;dZ@~5W67BG?q3eQp)gNEr0R$ER>^8atK=2vjBHgcVR%X;&cI#6I4UQuucKINM zSYLws9v$#8(7m4UOL`6|UEu?I1$nbjbz)G!nutE@rg#0;b;2dSgMeI{xEalUOtIJ| zx<1WszvW^C^R>;6qylzN&wn(CF$XOB#|W+4c)=7yiRQ(3VGPHo8-yct`uR4~KqI&( z{5f7fRJPX{C1Y(d`XcmPGJjo$f(aeuN9H@zheRZ9I{qQvCjRlpvmG$mTIg#oo3D(q zN6p$Umn-`5K3)VfBYuKcPb`jFSpaHy9pg^KQd~0_jorQDHz+^!{vS>AHha`h^eUFr zKVcmiXqYtDiHw9_>4I=^Kl5BYT_ZeoAaUbWCtS zwy8tB<*LElMEUlSLAo&6-dlz`FStx<8e#yWN82yh^3-MK)>rj%h-DRy=k$hQFY4x) z^W?{S*&hoC$-ee3xpcp$#mLuk$4nmlW$`tq#k^B%UmBg%G0mRR&@qQ zyKhE6nOpxy1Ip!j&ADq3v`iiB_(wCCeU0T)#NpoGjcz2A|!$W1eoU*;-<}f4~77w)~S{S3r z0%v-3@Y*&Ynn1t(jU9Y_i`3$1ep163)E7WDA=+*?C|l>mZb<-G3GCJ%ViIn5Oa^vu zlt=!F#2qk61v2^IAI%{?XblM6@85BxWLn^%SBO<~q)e{6THsZHMXjYOOqL3x_(sa) z-17hZ1-^3(g0$Hz3`2{<_bZV{lfPNF9t?ro8?@tqDf5 ztFkr0y!^T}UmdgK9DoRxW{5{wrwxZF-xPGNA9Y)J0&iU)8hr-J-ie4V$Po!n6)$0q zfH1wh5Q+VLub44d!VWl#EgvH%%NPH9(@4?I--Y0Ya8QSSsQ2{>V7}NZVhO-N=EK9m z%zXN?Wc@thfYfeaJ!Kl6Q2{xU-tm(ZWfV_(Ixr}uK<(NR6UqQ@wam4JkN&q#l&Ck6 zZ7RX~L>-yZeDtgxFj5=;_j3u9SOmbbmLetdAlaxKPcql=Zt)QTtbvySC;%uIf$eHN zeQ7Ac?kqky#IQjRCQ<|tt!Q9c9|$BkB#|4E=6cnz8f~MuzxbuyaM1~LuXw&Xl*&4Gjrj%|)N*EEP7Q z?kYgxOPbe|7w(Q`8x5t_e*_bcP2#ZbZC@+a{IZ{0oh|&g6&NeO=29Ai_?LL?ST%F$ z?*TJ{K^ilFL*n9{8-Kh4g4pxl$SjhDs24lon7gC+Z9)N>SOoc>jCO#ol0+V^LA?3m zutFcRx{|TF3cid{^XP(wS)h5pK*7h1)8xOjx8AhqLTk#{sg{F;=lY^(s=X87&+GkZyh3f z*s;@gaJeVKBX>Rj8@=KH2%?Fp%(@Jj?HAm7w%HOPY+=TxUuC+)ZqD92VTR@kol8r1wHy-7RYc zzGxzGD>Tx1%)&p0(?-$xp+TH}PgEop($>?)0oBcG9%yvKKBPEzVa?jcFCbZ+e==Lv zhf(_tD4Ab?^;Ens>#wQ;?+p*?1FE;Iuv->IDqZ16Qxp2Xbmy#q)jrk(yAPH7WRi#1 zOUXQA^<@VF1*p#pktqPqRZ5?Qcl&|#H+U% zGwzPYvwqYavxe^%4Ljiat&Ji6sedK$AKp8iNLhk-i1Nn2U8VIVMa%X^q(z>wwR=5? z^08<8WugYGE?n}GD&J^(Y*e|tBo4e^Dg=G#DB65)^s-HTQzU{MP)QwXg%1L0s|1iF$(Cq{SY&O!l>>9} zOVXo{THlpiJ{|X06(LJSfU3a})x#hwN|6LrIGbbyU{1hh3obmV4+8DhPac#LQMf^) z1yN7*|uo7{R+-ymZ=Qoa)s^1@*NZ>sz31>~s7&NYq%I<%D#V=n^5{YG(1jreDPzcfTBOD_<`c;`+cNrd=O|k@XJTRJu z-Bk)oqRP!!Sz<4)JkbQN5~<37Fjl^BxOt z=bKRy^)*7kFR19QkPk1ZT;{tTEF6vQ0w}n>GAzWD(f6Q0iBCkSuMK!e z%@oN(l~SHrW2VmmcJYjnRj(GrDqaSM%~(Yt+!V6hXXuvZ8w}(lT-p7)`D>Xswbmc9 z{WfO7?2NeeUhQ=UD8|}t>(8({FGJ<+F?=_o#|z{w0phYH%V3L9k`t{9$@q1> zi!AVS+L6oht)##o?~v^u5S|{7qWR#GsW|I#ln-9yPof!mx-MnBN&b1`7rj|?gsqED ziXGRlf)e`!#(r74XY0K#s`A6JwswyRB3eX|Kr3a+xc4IcQu5BwqW4re`{>F434)mgzE1SGNAzw^BCUXeo5 z)wN1!F|$PdXDT~;+wIKMcGI6MX-OTA7P(bfe=<_wr2~=KK~v#;nI5$sgf^W$ zvHXs~u3>Q6Mli4^VLhTXSm|z( zVzL?$5C6ZlnwkF%|3ACA>u`i0*R7&rwhyU4_aq@9ekF03v!ny^pbjnB7&>a#xI?+> zeQKO3Utt5Qp}MGWt7fYmLI{6|5IogA0>((p#<^=C%~RC|6J3Y2hpj};=ML?5zio$q z1>;P9?3(v4r8Z5V$D1;wB-+-~L;6vf>TjaulUT0&d=(e-3<_slS`AOb z=x)C@m2%b=8t|IhzA3+d;}^8sns`b6_{_NQ)@d5w%f1}m$I(QJNJQC7NcuF>WQ1@1 zRMzhVLK_1z^_xKzxmf)ctL2Zik%5;SES(d8%m`v{+8O*OS3~Wpm z&`tEB8}PETg(t~~Hs09J9^*3+n=X8t(znGZXQch*=wRv}jrI@ua8dOsna!-8UDm@h z)A)lvFXs*^yRX)LI?-zFtk16p$?fVrT4Sf7CRn~My4)Y%mJx-ZvQ-~68TqETCh$CI z&R!0B;%LBBJuq8t*82`IQYMHjEef@y|4~6|wsbl*1x=ewq(u$e-=Fo&*1;>|B@xfl zA1UvtQQ799ifB2-+EiC4qxfN#T?==*`+r^KB_%|pUarIi22%0<}@`e(*YuE_iSk@?Zd z0wGkj!M|@^T*AI_-c@JFD9JH1Q&hkCI^N9kMnSJb(QaXO{UP(^N5`^nJs;nztzoY2 zq(9~0IiB%wHr2R#gO4UKR@>D)#?*~yxBHK#mhX_qfiCf32b>GU(Wxr#H+PBgQbVDa zBIu}45g?a=cLqbjmml6fi>M1M+6stOE41$Y;J{%d z8b#9hIj48;yogR?BlnkImFc_d`oHiMrZ#gd{YF2TxYIRW{7zIriRY%6e>8UT>UeTQ z6W1w{(?mqz>0Uf$0;un@IzL)>X2o{)6 zUgpaWNP~J0XJs+>CHUo;Q(o@jlIkATRWTQL9$mzf7j7t{?dg(ow2=vT=>D zGhlCb2{lD$xlU&r5Kf>u&L^`4BPO?~kG8Ip!_TUh_fpRsoJ&fTFq18=H{3>Gyl+ga z^0oLzZReQFK9~)SU>WzK-l}KZ{g6T0G7OO&+5}mY*M{5GFkHdO-JU5vx*|8uaU9<{ zc6;UQ2$f`RG3w?cJ}VpjtU~eaM7!&pbcQ-C;riA@IOj|oN_8wqyJ*8@m+ezc>Z?cc zAGL1jLPqvW_Z(iCz3~3dK@q9D_^DVJujQj5Yq9wlX$YlHR8SW1EC2aa=XA{02jh=& zK^=#M-kmTA(?2yhWN*%V7G!(T-esu6J7<2TH@dQYdvItnHJW-MGG;v)%J^}Hs2Hfh z;V0o_s@fDfxNS3Rlmu^78xp8DTVW^P3?68OPb1nU%^06`)PS-+{UOz-ifgTx>OTS<1gcf{qiTCo%)KchyxkAU$*8mH*z}mdCL! zc~_$Mdc`^5YWxv!lk54pAji;$leW~LH#h}V_y&Z=@@cuQIrOg3xcq6BR?D#=3Yph7 z#MW}Z^sK9B>42fq;Ej4+tNyRhfakLn(3Chf9tP^5t_;sJG@dmD{-}R<$@R-mzAce6 zO`RqMeIv+@r?PWdoG4Ac1$QSVpic z606#oc~W9>g;J%TakYn3#IVp9*yJxGV^Z>?VN67J3?o6u)p;qe;Z=gAs(-!xpYk0u zL3F7AcMkOa*(B)|br8%BcyJ8-qoM8kLljpw!R*pLt&^IauJ>pBuEu%&W9gymimg`z zDjo{YCT6#R%5zdconaYW9Tk4T_l_FHo<3-@eAaTC?zH^U;SnmOW$g18J3@TSR=KZx zE+QB1ga8B;{si$6V8gI;P#8{(LJ1AY*U0xzjAUA2_k1Fk>9^_^p-NZCdyJ>s%_M1( z8HxM;7>d$TSlc~i=KMF3zf`uLG0NAyofCEYcJopAnB#o7O7Z51ukuj|R3Mnf{-G?t zL2>tWb(W|D%}rB-BUH=c^ob_111=t$>o+sfN^w}^F|yQFL+Vari^y)2WU@0()kksu zI5FGlZm8C-b@^YYmZy7je}vx>&ou9{B~#Te%MU=FF_QK z>$UnY?xxz#mDA7XuhOkP0=)yU9qp7dsu<)SO{+50?$+dV_I#zK-)E_#?wN$fW#kNk zkVVwRiV10r!tRuooT%DtWY$LMUi-F`WS@p0vOP)qZO{LE^e7t(ijY9Rmbf@gwg;-c zXR{q=p%rg}NrsiR25dvge(X?JweFS4^|~Edk_L4Uut1B(Us=b7wS6vVTXr6<_H%ug zHFmwv|2ym3yYXd1vy(1}z1R+C7bO<Lw7=ILySpe$U)_Zu(X zGYXReXY3;aCc~i+{3tdl)Mx*i^RKEF{(ODy? zNaf2?T`Ib^21jd2n0*GKnxS*`CTDgdr;lA4NPFh@ShaIzV1d0cKih4_*B_OgmP$wa z@mP_58TsV=oG6pPd{5)%^KZe-$ILSXOC)G3B`Nes?8!eG12ysZmu{bX)-E9K$22VNW22A)P>&NkIBH|wyeD3(Qq#I;GQI>)b%rYTE_#?ieMUAo7($*>wR zcipjNRZ!#ik%J9x+hK(#z4G10NcDc%A`yqV<4y1z_pr0hRNM@yW2Po8$y0sELalJ_ zhlAEHrU;T5j&0~Iyb9R4C=P7_WsUG4@lxK%Pb$UM{W2JSPJX@^vw(c^Vh&Z@e70J@&$2+67Jz z^~WsIIa9&o)%zk($GWc#@T>Q@CBN{Jwu!?Q^1%8s7(-u~fMST=u74H z!~wy%AWu^nYq?eT;i>c9hzaz#F~E{D%OnT76Hv)SUwpHHJIQ#r#&) zx<*!kb`uhAM&%!z13Jg8h@V>`wEss?Zl&y0^KjPIHTO5G;n6>&b*;r3RsIq6dwVr&b6HU$O|2sjVTanx)~7lKCN|$EWJ~)3-ek zH40m(PKZZTgV~cdqI{cV8{n_fOFn!7{-`XWC|wi0??L0(eYe5X-9~Y4_a*Pmw*wcQ zaO|P)N>>8A8A+1Wl7fZI=loPxl{-f5G?arcU409#_0%`7GHW9;1P(n%J1j*@{t%k} z;*wFMtL43P>*|C;)3!;nb(pBWY??GwJ7fK+*K-Eb7aG%x6}2I*7(^J7({@C=i$78Q z$vF(%Tabq0fcqG0YPS+@UxytDTb>(O$bX5WVy!)!Y2h z0pF|g3lky8FtUma+$B;cN;JAXnv;Qelg(z5W4XUHCcw|C#&q>VeUFU(m42D8_?!jE z!a>}JMbcXK=Qb*ju+6PTovTeOMB_lHvE7IFO}v*(-hFRS&fvlAJYJU+DL!tE>oBOp zt$$uSH!{xn1y`DeY%OE+{P0U*HMIBG!pdjuGe$)2v3Kr|>9fjqpw;7;DFb3?ZTUVT z!y2_ZnF!K$YZh1RwJ*SwC$Jjt1Z4xH26B1b2+-0}ckz1^F4LWC65s$dDXsv8V}>_L zymuztxQ6BR13k7%(BAL!BhH$-xD7cS>3EwKGfz#m5)F{oma}EE3@AGKOYY2?iz;b> zjo)ihL2c-(H52$ZSFZ+mLYQ?PmipJOSfvJUM~9cztyZe29yx{5%rk6OG~ zUv>Oa3rjQ8RaO_SYx5q<*Ek30+w)u2;TFThEeB%8H29sq^#+44mDOnyeG6Q6`H1kg zNsD^5P?tb&VT8SDUYchdvQn#-4U=fMglFS2*dsg;C$r^RF7`V3*uUGq`!JD{_0`v) z%SDHNM!J8qR)J*tq2BQa_Wl^bd&3{-Gg%;;@)9z#BtBQ0#d$|c0;x11+6EfIQ^FQLq#h6BkiyNa)`fgkQ zIc9(urLVC$j|J=Rv=gtg{KZw~M(A-HCvE60&<+V0_S38fKPqM+%4=64C|nQZGL8=x zXA*Ksz4r?p{Y;b!GA%}*M{_-^ac*~F>|p_F{V@@uVPWn@UY3``-`T~N>65S2#d~V= zj%NO5|5#`?RqV~}Nqo(Hx?DbTbQtKXWOpY-xyN$jX6ZJXzDXZ5%e;%YM${(hR=uX_ zmu)Z~-3ny(wzPA05H|F&Pt}}ciTL~AI6DmW@c!?(`83L4h)f}SZxHI+17o}iA1*QV zn(n9@-xR|>tK*XCAUF!x(irLgzsrj1?1-|_r-Ueg=m zaDkFStcz(v?2cV|{aYC2>Gx;Vqb06dmfPyp_MYL{en3a7Im9YVJ@f$c?wuIdmKpf& zlicvLi=|*FQoK%uv+JCJV#-S&#XLY%;E=`)7g|_;>{uNK0x+dzpO{MfYR&H1CCW{8 zpE72&f5<{ll;iY@T*mOuW`FTky-W}P&dwTkbcO72L4L6QS(i=l!7$L@c@>-bW<&Z9 zN-)F4lpvX#gmKEht3o0uR#;15JLcqSu~=}0&hM|ix4Sn2&A|8x4pcKAWVXQQhHJ=- z0_{TcAbV6n<(Yfw;tI?)aj8HfT%>izOQP@KChi#dS1z<=i8mNEON8}FD`l;a-lJj@ zRg1S^g*=xybu_c?U>fNKL>N_H&3`CbtvIrHr>HHZIqV$wC5k*?`|Tdt(S&v7q4sE{BYFp3%@23{*vlVwna{eNa(<$aXt1m`*`L&wG|0)xMEG!<`EN}d2Jhpx zDLBH%VsyXtA5GI=N%!W^TkD~$I_|;*x){9>fhRdICS!2OC_hSK32YEg(s7YJ=MaqPp{?ylPyB95;xzR8>(UQ%>c)%n zMtP;_)J?qxcSR}%F5cQU^K=!&?)F}L;GJ^t^_`{t(-Ky(x zvOkWA^exKUwpO(K8b_QEask8QVyKJ=a=QMOV*f9|eck6Dtfk zPwyt|y{kP9(kXi&+>FebwQ+w{W5DI*DDsE=_Ik1I)_e6(F3I?W5>r?4)-{|(+xfw` zU=v^XhU^f$RX)GT^0;`FbTeKAdc; zs*4MTr zR6wK)Ql&&ex`5P3jZ&mUnzSGxQ4o->RH+dWkQ$I)BfS@?(g{_1LJcJ3`@g@3yE8jG zv-^Z+T!!S%r=0gWufv_i6f4d&x$8FYe(7`l<%Wx7mqytkl3dCBLAZ@TXfAKQsQ3PVRCy1zRMqA}TjVyz z%}bTrtx|rBO2+0l4@mn6XnicYFbFhLEj98_cSjqTZuw$FCv^ivZ8Rh*4zh35DN>b* z+Jf~b{BG~(Z;sB1^4oFhUn2f2ePvjMzH5-hyp`li(yjWuT^xw3Mac-$p~a)jVzI`? zcAEhw;e&Ew_iCfytqmlDSr?=Zh775 zsEpIzCT&_=RY>edFf~bhdXR5FRyZA(_d&w{(~C9l&>^vYl~?W$ZL)rSxnXZ^_L2#< zN$}%tH9=z2&T6dnk}8`_lEA44ilhXOmk0UwhSKTX1}fM6MMduX;*5iBu-^*;<&|7z z`sp;zTD=NUU=U0VyBeXlz3aa(G&Q@;wg%oX-1XG@)|KqVbQ1 zFXZX?ZeC5|ubwZ}o4@yKx4ix?c3Ajr-j#dR z7J;`bas96vAP+kXGDh3~KwoY*F_z9*!DqEw#^x=K*K{IZW#;m7pDe~2_yiD`*3Wm7 z^!ZBkS)e%H)v0M5fsNm8;;4a~hKHBPUElCZusYB`)DE*XP)dGf`K-(EV>&kfUyI}< z@2rbF2X}PN>{qj28)K+>%(Z0EYTcUW{>-R_!mFkS{l(}THCe;hmRdTidsCp`w#k8bFEBu<@^H1>d`?<^T?o3 z>P^E_7GBP%^~cC$6Z!ES&+p|20FKR{rG$qTac*Bx99qgz^qSE5(oOT{psLitp64P_ zW0_OpUcvYIE}8+9uNO_>tj)ww3f?NxDeTjb0^8;bv-XKx@(WoD9-fe*gmyC%JI(%} zc`ab=)~p}R*g4D_&=?w$Cof|?d=E2t{O7UK1%un&Ru{z|HU{+ydMM8c_A##_a|LU$ z|7^cwt-)D9!sP$YWaYon|Jzsv6SsCPj7i^<7602y43A~YMTF;(u@6Uo1Fjp8^yX;g zZ~udb78*$st(Zd#29w-@f%N6HkW-Mx1EevHF@ zCFJWgr5A*M&Vet6pQ(xHGgVTWTv0Pq>L$(aF0D~hx}>2qk8~F9SOT0 zbExCuK^(6}`&5?Gh_w7$l}3w;Z^zs8Cn1Xf;@VC`Uch!B z9Lqmj;6j)LT9eJUW<)~SE%Ea=LX~mUQE#C9O^-38K^fL8MJC{~G=*>os6wtjb%E6} z$8*m`4W*kIYHJMYg1Uo|E=?w#D0!ztK-O3_hbK~`YTWn;^`CXEbcky z_kC8Giy*&$E5S2nGPRG*t9#LU3rv&R3x!BWJNni9CPU=Ee{-gTDMU8r`J~($n(*g`qalH1gs?jE>7!@nj zMO-~Y3tik$QP7XAAzrM|FrJjkk7q8ufq*88)@r*i4D{(QWTfoV*kG~JK4{qllpwgs z6_x_Vp|;j#P8u8~;u>qGa>!s}E^2xE-|oKbC)}KjP|WIO>^|LvXE?m*MPBcHF^oWX zJ}A*ThCuThJ-uN!x!0t>oGC~91|_*G`IAJSe!Ox(0{24dR^sS{Z0el`(euCpYcF8=a;#L zaO*xDIJIr#X}K~IU6><;KV_wR}=hJY(2I-W=(ncyZ)NA9e^Ejq@epcOowOZSD$ zi~nl;8}!#7@O1uRgKo!KyAzXlzTCga0z1`5_bgs(y3=6D!_5}~KD%577}?R4Y$<}} zL@@4t#<+_GU|9Q?o<_(6eyLKy@cJLrduZjymD5E!mHVs5^ErPr0Y)l!uGG#3NfJA( z&27~w{o-Q*9u5C5b3zUAf}ey0>H?{xo8!HLU7;=M>?3M0|%(&mquLh__)S1xqg z=S0gDa4TitdxZgO1M6QZa*YMi<3Y)qEAsV2D?ao`wJXS>10RmG`fsU{vK4whpbl&4-#&geB7lB zyw8^btWC!j2-Gb(YEkiXvzPobq5n~pLf@3%p!f$y-ym@a5-2|)gAqnC@h5;Q&%wy( z)2ZGicX@d=z>&RedY?v@poZ_442cX1zyHLsZ4j(B1Y40fXlN6G1L|0FO36>cD|CU1eoM|c3ozRH};b} zevK_dR6ciuM}O9K@|kHl)c?u(LYUy828w4(C$BNvIr}h|_?B;DKGjAtn4law%;GbE zsnuk$G+8~q7b>h9s=$V%X--+&H(zrjP8i#{|p~ybeFI7stPw5tzrpgji zmKW&cuim$NN9b$8Tt6$2hU_9{CBTyt|58L4hsh$lR24k_7n$zo zD|-`9NcWN5oqz>1YsBakDF#`6rm>=;krH7a@#WpriOEI0Sp|p&p(Z1JXa#V6MO(KcK@bK+?s>H89_joZfO4GquQnn zVCYhN0XS;ylfMq3X=Q(P$2>?&J#dwukd!O#FCy!nxF%|o_>i4{dJhnHM|Ek4-`|1> z8-;sV2j;)+ma(iGILUa96fc!etM4iIgl#Bt5$A^%KxM9h`IY4EZW1%H^V@w8oo`~* zOUGxZ6C_O8^db~xZ)?=20H!-Sl8#}%8`OxnKoq8eV{H@xsWQ64i~{VJ5(_9ll#7TT&;^7< zm5rDD!eaczwdG7~x$ut4Cu1c0^p_YPKZMcx*ci~v?)IxW^LiqM_L#)Pd4di*sRNb- z&`dZATxAX>20(W1#pEG5yL2|QOw9xcz~nu@ZlTDE@}d7S83jB~>5@5!zEno>tZX0P zFR5oY4AWBD(G>uoz;9QoEBh8P0QRcbB{6UC$EJ_}GoP-vu@&o1LPlbr$FY-}76pn% zu*>;nzNi~&qHy8IQ?pN7@KdwvkgI9Ak7X9S53dc{gJRS!$5MCV>-oVdkb@y* z`F>nfBHZ^_)yNqcxis?FXwRACIOAJR~C5P!fCB0BSAW)ubL1%nKF|DqOqP=iz@fAnze|a7CHulT-Vw2zuDX9*? zV1$0nA(4yCxjg?CY&BR%?8Ub{U{$^5%8B=O=cH7vWUu}*x=6Dby+ym*B1#6=)7512 zr}Yyk-=&8)ELMr}OC+7AiEuxPPmG{<;tTP8QQ$3d*1|%9Kb2C1$&XSDV!z3tEke`) zU~?pvsdS`YGKBZ&>{VQijZu>34}9Tg{Gs)o8sMaboI@~d90IdAvrC!{kTpZ1VZu8w1VIo)bK7PQhu$v{{Xw&vD z|AXFzyR7F$O53JM0!6BexP@BWJgPnVC((X(CnZ*(Fy7^v4mK#huW^Qg?}M2Zhvb0Qm5a z__o$aNB#XqdQGv3w$Safk6+;1 zzB$z84^ihaAD}$!h%Ur#NP^l(3jNRH!e>Q~hZueSqq-%Lta2w&a0o=Fg#l ziw?O_oFW4T-005NkCag}sjWO_?E!3^?MmHz%qgfNQOd_1jLP=Ek=3;)m;;hnNuwc{IG)&wQ3k-Z!hPjw$?A8MDnVPnNP=EcoB3VRB?8{gQ@YeQUBRAGVq zU{)B}Pb zux5!*84~?gN=?;&sav`))p-gTnbs)Gg{rlcs|k}GiFt$!NCcEvu&j?|g<5y7X$p-| zSE$~gDgs}!*$R`BbgY)$@UK``WI#SfX2GV^Xb^WNS`^98M%B3fot~UKO%{zZSJ_Ix z`2J#~F@=29SI9?1ujfLG$N{V!%lNK%0#v(&_<GIpm~BUhJ(^$3VLVM?b)hRm};0UxbsoW zd0B>XQ7_+I=>y~J+`u;w8MlCunQn!ZoNw`LTN>^6?Z-ZTjny5V;-AJ8fM3yH7#UpT zR5k7jxBIt@)mEYXe?)0Y`HV_^|y0}Cnh<@ zE%ZsNroBlhi1VNNjjq=2JaZUZBR=t4nrGsgc$q=6U-)C+Hs z1UdK!++}nHMiCiB_^U`S4~jb6lD=7OarZ+gm~dl5AYSjxxswH6Bo(=#N3i=glV9lc zE+rrLwa%M2!>kb8K98(^5b*O)!L;-72jC;Yc2Ky9S7A%BG`QH|PM&y{&5*YBwriIK z<9q22zzp5!#<&2;+Hgn{^~z!tnz=~YM{6o9kYsE!I?}}+=Z!bW5;w;rG zdnF$QLDc8J3i$@rV1RtN2GR37<&T%mmKq)58rs#NK=%hs{l%?0E0wot0pfILcc9@a zj=q>IiUK?WSZqSRA-n;%==5Hffv_Gv>qnH|pt`Qa={2GH$bbi2;QJtj@^k;qGzQNm4s)gMg}x2B^>p{RM$hHkpjY;% zVpOZ&SGl#E8@hiGDZ8wcskYjH&nrU7OjLQXd-pP^Z+pFt%bdSDQ!7h~^E$|T! z&SSrt@jv~R!i&V;P$U;KpS&h8N09|cFX7I{Bfc3%H?|L8zpOf4egB5I?qz-N^=|YS zovoa`HMv3(-p1?}EMa1yY-ALEv>)Jcgh%Hi)c)*AN|u#XMR#WhW_X@Q@@vNF{3)mD zyRIbc?If#H*L-%j;L5Xk|hp1I;$%hAa93T%jF% z3+!UVrCCIz6AOmf{&CN>fWhheIZ__=cKw+x4I2J{a$cPE^JC_M5*@55?F7d4Ea5bV zVyi&<0Cu{b+mbOk`<2cy;8qT@VuQR&3D& zuKZ4{8vMKKvP#Do`-+Q7$s>^?2~evVUrqIxY~w5YUyJrZiM*k&lp7r=SM|WODp|vH zqrNU=u8Yb-c>4KY05_+aG21~Z`=QIJm>}!4BuN8wBu_ROFV&1!SL9n6NR*sN&sg?s zFj#u0es-Qc`o`XnK9kzf%)Nn=MPB=8*Z;GJ5ZK~F4db@XEd1m#w7xlF5&y}#vi>52 ze4odqscLfHp7+4srJZ7V_rpy0u=#}okfl~}f};VF> zzNuTm5lqF)E!ux0QCCbNTyHU#q5#@8-uO<=U&>@kLv{61oq`4XTf?6Z>`__T;M6r} z3{gV9GR@Mp|2+3!T|WKR&kK3HemIcHx4@gXS_}ErZ=~*8fAo8E`R|;v z4|HqX93MSGQMIyPEF>0^)Dg;!c;Q`FzKBTPUgwgn8c3VwYISo*Ke{^3=LpkT zTx^~Wev>0M`poM81#n%G^;Rxbb6ntaGNd+%Rhcorz5>*inllzQTBT|XtX2NYg4+6l z+%HyAG-*if-s=rK`Og`8bkxGJG18(Fj;MSu#7OAD!?Gltqun*-v8y<9miXkjhv_SG z+aLKptREtEsb=TWb?q%uMB4A0t+=qITl}4w(wN$n5$kl9=gedhrF}N|@?=a;@biO> zy6=p(0&s0>v>Rpc=5#+kars5%2Zx5J$)^dA1HD&)mOZS>&fbsc_AT*MT48*G^3*2h z1VWxwRgOH|FGH7Ex6@|}yrnhh@)kK_qEst(+7r0jvXml(Trn{8tMZuN_LuYrLVe?m zEo(6M>cQdZdtXQpGA)6FpY7!~2nVkV*FDb8Ny{kgiEWL`DE@2+tn&7?V zYMNg%S=K$eRu>R6SZohlw#sze!8B^mgKroXxn$hv-P-MIi!X*V0mg_?sm=9M05HR>;i!gEsDL`zN3iBoLIqPurGyaM_Ipi^8 zVp=(T^-D{&_%Ndz%R|;A^tFvbSzI33rOJQpdKz@SuhN5$X=Sv@PGmqLtl;X^{o>t? zk@I~fMSti_@>XBfzLv$Jw%_=v(O;3KMRwxF-!FH@1b%}oF!A?3_m{fe4)$u>4!2#aT$Qh?Z@J=S^YJSvv%csJ-N#h1XE zY~vwt_5H`0jjXC8MbB^$E8;52yfX;Dy$lU2J%Y0EIHxZJ3A{HY5wHtPKSD#(SAo0! z1#B7Bz8_1uf05}Y;_e4#{^#!Z*5ic5djiqo^QUsOWuMk0%XPGSG|D8g5-c)UPTb++ zHPntOTBCC{1Wy$nYVWdmE#m(y$j0)xke&vEw-cr^>ujrPNmxbmYqTz+g?Jxn6-N_bhhJE9E z!8>_+h3OP+B@0DBzS{h6$pp=Y4JVW^+rU`91~cgR=XS3X@)h0*$K{>2BW8NV0*x_<-oLbp1MarAe-m zY~%F8qW3EIy&9C`@F(Q`QS>t?o7tLw$39?#7ky;=JY1>KG5_yt3fxTu$Kb)YHBo5s>|-XYYrsIB&&AQjfK9o zuEc(e*D5SfD`ZE&r~wAvF!+j@uemN63i2%%0O3W?hj>xD(qQ?OAo2A4W~?ltby<1Z z!*AZuOmWc<%(+QwH@nRhotSBd&NW6LE%__vv7 zQbBn(%4Z)hJMlmFl6i+Z-aay9Fr(Dv2?c{zk><-rRhG(ON;A92*PicDFn5~e)KBhY z76Q1H-NK){1M8$qP5a(o@i8ufr&-etj>6q0+LA0?W>8@pGXJcSlRG!2^SB;_o%!F{ zyS3tuETA>+R$Mk?O>#`_A-{$rEHt>M-)sXgKiytvuFg3}S0!?^CiOgQG4xubcR`%{ zZh_?$9M#_M-FsMZ%AI+5gfYQCrwCp)Ui#bALK`sBWki_ zq1q@$12|Qd`LgS9RJu8>{2jWj z@t?iuEAK^%_Dxz@ijismz`?mv_R~rmACG3a`>O9ct0~$;*eYmTNs~8${lHz0okvyi zB26#;IG$_mKdMJ~KldVwhs3Gnv}Pw$E{pHeH7ITT3F`|RG-E_IA*$|+{{8u;^=8tE zMW!}k*2s2aqq6?WrKu0rj`HVgV6(tXq*yQ5+sedapH@2j#iW1^bv<$1GpfmR$(Q=JlXPeYWoJ$ z7h_b>;<5T!Kwgre^~82Z~omV-fNKX+xQrDJQ|;n{kAKT{)U|sT)>s>(&MC zYBk=mjGi=|j*=+!j!%?aee(}!71lpvD>)dhc>Qb2z7<6GC~6v{PU-z6OqSRlN45C&hhS|= z-)a9gfIXfdJCqWYJ4T)!Y)iepduZmE?DKnmp#?3xcEag0>?|VHEPx|^FgssxcqBO* zb9<_{CQ!4xUG*v1u#)KKRhDW(PBh0dzi4 z-u(k>kTgWCV+9AfspolWmN0gfmrF``#LNQkht#H8;7{X^?l1N`ljue5RWo9=u>CGWz=ieXjxE@bE=}+rnpn) z-Pu-(yHDyL*g>kf;(Ku*8re4%Mgk#XYsIelnobT0OthGoA(NB+KS-Sm;g3)?>-~UK zN>VTT0efS$b+1aJkF5G@%1%(%;n{2KbA)x_Rtq)$Btoh^i*<(7KH3)REvpeI!0X^? zJ9h|$we=@5TU5&h3byPOtjz^opX|atNG?(wOH5wO&a748>E;%S=#0PNVv)^WPU&w5 zV1y6U&GH8>H==mS)_^qYObrL)*5hFe=PplV6EXe5T#B<(0i{7G%WyXHuCaoWbp2yB zyBcWZ06$2m*lvrq&%h5-Wh4m@h(lW!q{famORKQIV3Jf#w%7)>T-7tV5roI6_-$e^ zt`LKtlIi)P`5~mDTmq^TSFF#W*X&X(X@0s$9`>OL?OgN2zi=B}Pn9hpmjG;r<@#qe zsbiMKdoO0GNakTlMKz<$e6RzTpkLseoT5gx*o%~VVS7!`H$~6Fr-T|Et~Fsh$7I68 z$~mR^R0o6Oqyc?=^o-)Xu4GrgAV!%dr>&dxMc?6RH2IOq%YCMqa~^}d8@kY(f^q%{ zSjL>iecpJ)u4VlN@7rS^BV1%reDIsR-82Wz>+g7XDVrECeZr?19DEHw9y~w#jJ(%eDXt$gKc1Po`VyAjSV^7$1!xVacR zPB!qt4PW^OnXLIINB{E@e zE38a@@Nr)j)aQd3eHs50AEWRnxYF7GO_R0)XBVbO; zqeZUa8V%7os~j!QJ;?aj*j1F=Ihv2)%o1wd1x;7c&>j;e2*>z>8P108jPJ1uOJ^z? zH4({|Fe8{7@IeZ1{s$Z=yj;W6l_C3C&t`)&9r(o46l(i<`0w*%IN7ilSDv9aaR)3B>>0uWA7vCJEb9Fe@ zFGb`9%d?I96k8Wp)(()jALd2m@~W{YciJgnzo4L_zV%H8x!d*h@VJ;ix7!sa3;$(b zt*IuaVc=^yQD$(B+b?N#AH3CG6`M-FKJ*>-149JK@wSz!DCf^(Xh5mbt2O^oRn?U8 zx5$=y>PKy8HD>}_?CkpUA&B5R2n(U|cR5jXYciN6eM4s){H||9h%fHlIi&lwAG-p* zXaW()Ko5@|h&MY>c6r7t4jkw8FN1Ks$R^E2cIo;~V8_qS475zw{ng}%^kqhb;*&3p#OS5JY3{Q4 zXTN^AGxK;Ubt223HQs&t#`E{^CNvYC)EwuaeN|!K^rI{~mmV-!0_Lla`7mdfA?yVkMIqIJuZrUX0 zm;CQ9s*9Mv3pgqo+N(Ecz7UI(chZ_tnh)wcL9&jP`Pu4rJh#e8o^H5ehwW=&0pm?Q z!)wx`E$4`k=k-;(-X}k~@6Uok-zw^Z3)xwyMcIjw1f|odmpIsUHG_(KSv%R_g^780& z_T`)1i$>cvpl;6@hqlE_rR=u;3)X3Zicy?NuQh-|Nz8y3nJvB$82rC98+DzzPz@G$ zKmM3I9LzMeblQnwK)~>t=-4K4PVI+Z^CMfxGTQIWJKrhS4CIf+#C>mZkn0y+tJ|uh z1EwrIMysxLnSK907K4&6ZErr;rN0rtw2}!y(>Ofsh}FCQSUQ0Q92R^P?=~_sujAOW zw9C0!M|XjKza{1IXT#okNAVSjt&`jSGubkd!4PJ_8 znYMcNm-K`rw#(J3e5EPuWDpse;8ktY&amC)3UhxpucNIMe2L(Eazy0A592Jt2tMix z{8D2o&xhI5Ya-X!vmYROHeCJBG#@E~A5eA?wck*!7IImDtfLF!LNeOHt=k*MKS>-5 z2EPAaJh@b}E?n-58E;KDsrjK@3w@}qo@tg_O7aZg3of)2c0~TR9`u;>pGuLTEiGHo z{qFrI;mK!|0K{VRJ+Jd5RZpxEi50H@H@?Tn(US4~Trl!44nNhCl zeom&zVp17mS(-0McTZ1Ni1O%5C0LgSwGQgdkeHdTt#xs`hV8Vo2OB7^`I;6`IWP$* zAr|$GO89hwuI@YF#}5d|gudd{iZeRpwhH!>#rSupzbMRp&6t{>xz2q}Gq;NJD$WO& zz?{UOW#JH6BYvWlXO-)tt4r+Wt-??9-1;vt*IItgu0^+bbBk z>&`vqa<}qabF=l<7m_zMS^gcC*tPvNVcPYZPep5Rjs8G<_TCwL9`*}SLFq>dOrX7*m$J9bmUvJHboO8$R~zj~=1^$OLY^xi)!R|Tu)>Z(8L_?b)Chw_)iXU&*P;c5Pi%Y+B*ozuO4XLN;p z5-*a$Fe6&zgjGPK95aneK!Xh2Z+9ihuF4TRb4lPTJ<4}#0_2iJ#SwMvgQ!?LUf}oG zM?bIjZm2 z6STWPY~Qn51hx?omPxd{Z<~~^;woE0hps!wJxDPKuq9*6uZU$R-KF*|hg1#0iA&jO@RswNDr zx88x{C{lpw&Z*#{v8$o!k!|5Wr&lQ|UNj5$nj+dzH5|X0dEEZEa0`F>9(Uku7GoGs z<-d~SRRqfrU$WWe`;hWVJ<$uAf3oMcJr=#@X*x-ECShsDo$+R}-(Vy^$GM_AL{)FIJ zu?2OVTfwXZxZH)ng1Na&N^BFKSKVg)dJ&-bi zvp~$$Fi|+-lT*0Dh;4VmjlNsw)xnZaccZljoxilOYi}l#E$n<_MPm}D*bW!Fvh?_b z+aCSc;lhP1Xt$j%O>G9Ye03E#WcZ~}7M}#POksK605Yl@h}sq|ted@#le}kZ@pL}$ zmOhyZU5cD9YQxk!Jb$tcVDfJ_Ikp{a5E`48(K#2f?JPhc32b1a$!zpqn&d>^qs*y; zTGHc3pt$S@2WCZlx)kH?eAw~g6dZ&2O{s#y~ou)u{Ko6c7S7QN^g%Za8*3MJ(vku59s_0C(mL&bbd$ISaJY zvjUUY;*B5i!>%x&T{J5~;sOn}heot;qGBkFo}aS8guHL{2{Qro&d$_SC|^B1x>rk&X$>@8PNthTKMx}-YyAK4Z)JlK!gSQk*3cSBdI-?yzPD}(i` zotd#bEMubYqV%=x2WspGUK|U{ofeR9notYxqLyYq6kEH}yGiCbH+mJyh>P>HWS1;u zVf7|xcaV|DaS$((1z!7Xd=_W);TX(hw|QRL*_1x+AIVrvnoWo=FLeLc-7-UdLahGj zHj^4JCsJLEuC@`;WX>cvJ^>BYPyQ06;QIb?ch!D(^S1e?FuHlF8B+2^$?)PrD~S7? z8j!uhtB0?_NslLw1DET@rFM7szIHue`108&{v;MUs~+_598D;zCLCH51HXZHE`oD9 z%k=ZD=Zqvv%J7o^K6Kq6)J-jiP!<8pHkcmqoPhr5Uh0cshdpxqPXDi@YO&h-_p3AN zw#i){_l@F>iyUixexj^)EAr9C20ors_C323|?j6L`Y~@-)nyY@%+5vZ?ss&$pK8MFcWlkxFtR`IFv- z#oJF}-^53s__KGnceEn)|3m~{3GnAwIZf!oHmNTpm43UU z#=EfDB1YU4pA->3@%2)iY;nxZxDPWZ2G!Vd~fuUzibiZv$cduU=UqQCa8>-y_Xu@v^J>Agx~uuqz;36B!r)cGT`a_nHDJQwP<&qgI z{!oJQi5qa9Mz>~*5jNs|o23lLqPMH-^1eumdF1G1Eb9iEtksVj+GJx5_U-uuboDQi}}o zUhR}?2+8*R(xN(q-ABSPLttKn+@u=cR@cl1E;zPhihcd$g+N2fswD#-0Xy_}c7N04 z_!XOzLw}1nJhXMHa>dm| z+ot5br~|Mc{|!+0QIWA6z~YA?I}0Tx$gv2E zA7S6?<34|X|NmUZ-8&^5#mMnI8+GhG+c($+H&-fiJ2ycCRs~4umB!q&Ieg=c%ERWL zXZ)^QPj3=ImzC-+0o&(VlvTw(pt0Lb$W#2G_hq6|*Sw2u+#_Dyt0_+6n06AI^ zsQwx-*~1__q9*y2Vr#Ual1t5P873a= z?%FUKZF}?I;Qln!jPMBABV&tr5Gh60d^5E?$rUGX^Xx}h_ZpNBVU}@%B@BmJ&7Opm zr}VeU*LtfCgp6{UGhO5?IuEF?9-hK_yZbpV(1x;VKuu_IpR41@aK*y`z9Nwp^V*y} z3oIQ_OZJ|^T}?>+&CF@Ea&dRpL0B_W@L$wCgEHEKa>=+RNH+7Ae!(eA9(_^(O1^w}ZtN{5i z`arGX;v+SHMCc-Pw!jSpc~QS>rn-&0Ws!oDFEhLk_C098$Kz9pX?Yi^8k7a{pXtQG zCZG%JC}MRmm#0&}b1lgH`S)UvyOwp81nX^(ZlakG|2bo>e56Fvl1@fQt>;{Mbe=F?gM zfVuQF^uxQwHu_=!_=w`Z7yTqiS@%xV;Ht)&FxQtkzWNn9)$PoSRFxoS!o!nagvIz$ z_m*~8k!zQ-OGfBj4MEs?@Cyct-02H=uWl;)_$Luil-zAbim< z)H3xl?p+6c{_k_;F2KAsd6u{e&!rf1iWR!cw=OP@nfdFQu3fcmujaddJ~N;Qca&Rv zl$tEzby`s@zqLek{!@5zhlAU*;9n2BOM}_)Voxr<$p)38G>D6`kQR>G8aOT}JkBDi z;;bIJG>yhuuGPK!l~j>buxHSp7HFGJxaS;}7haICTu7nByv&h27n@y2LWtc4_+xCW zTn)Y?#NhsX|H<22x|@MG)l{NebGZnM4N?)aVPhm%Je&x_4p4g9>W!}IjuY$6FWi4_ z#FFdz3?U0GEf-Of%cE0W93t^D2$5lYm}%(w)VL#USM$_y&RI8)sY#zxa25H_L3ZKm zll0O9quU8aReidAYJ^o&`#urF>H~O|n+{3zmJs&?tmBI;-4AuUP&lQ-KNYgbpyKN8 zdWqG>R+n4Be)qaD^c&vHGX~a6(O#tpn16g5Ch{f^G=NiMrS$OwA)b%R{T(0{_wRp> z44C}t6A_;V-x9KVW1Fub333x~>@w&RfPD3Mq}}exV(r4>`rxZLM$kA7O|iNnF)rQB zKXD4+FAGC*xg`#Uex&vaEaiM%I?No(mmBkYa3rEUTO6#m0%-%$0+!~w7FE}ldy{fO z#j*Uoklm?7y<)~TcW`6eRnR+4=*jSeehlDonHX#M_tl}(I zq5=}LBT&~Jyx=W@F$XjL1>FAr$A3VN1U|o)&X*m?nb3maw_v8{Z_SSD_rVpFXrguc zxOGdwnB#5K@5wsPXfK;t@{@6(y^X6^Fc`My{RQ~nw~PkSDNd8|H|=w$62NI)I_gx5 zo#q~n0T3reHbS}8+=b|k@l({_>3lHX_ec)06P}PcUywu)qzg2ST~6%)M?79i##p!us~%<-7x*y)rtBU!U7oZd)arTC@O0r~V(Q87+&-+}Nri z?02{TaO}aO+Y?KB$5vtmRitUTmyqJF2wGex@g_;pZaY=qsaC(c01k&KL#agkiQ8ASo1j9|TGkjS1Q&Okk zSS|l+jPPlPx63ns#X#a#@;)$;G@Yx9A=Yp?$ra9OE) z7iUhpp!dDu*kduR7hy2wyBM8)3mU~w{TWL0QDUN&rvsKr*lL<;Pi$u}5U_qAy+J*L z6<)T|T{eerb8TTwPm$D}x-awI7yj5(vuKt_$p&F|@)I$gvuPCv`Ditxi$gotyv6an8Ooa3FjShBpcq=^9 zDs094NGRk^YN_xDGNhz{mD-15elDx!256*bVdneITq#5UQQaUb5!_m3gW=-m`yW>| zu9SF<=3i$OCh+5mON{t7@njeQ6zUgX?YYZi4bS=ViCQ#bZ5T6XWzub&0w@V5=|+=- zynlCcS&U>maNv!(!0%0Ec@7(~Mkne7I}8R&E2r}YP}3gtq+ShR*HY?Ivw@@`)QPC2 z;qY?#2;97$fwQ?HNu%aLMi65)o^vjN^N~rZ)w|m7VBbFYLSVJaOE2H%@x&ywkrY;A z1o==?nW*3DitWEU($m+ToqXWKe$Td!Dtm%(HV&#qMjvR;;ghrNb{C-MrXs!62BKC< z=5cS?(i*7dxA(!95emQrs9R_BHPI8Jy#ivgyYIT=@rnMrXT}Y*k=r?vt-!LrFZ49I zYOeu(b@`eYjbYX!&c8vwu+8MsH^8U0+|`Ja3O|oaTz0WgJdQP7riay8Jo)t9v*qt@ zO(lR0XP#7Xsn}{^X|8o_dOq5CV3c$9-PGJNex$3R&W+Jd9;Hx!cF#O>yq_NgiZsYLIg$pfkL~bbzn9Jal<}HfnuW z={d#jS|4yTtaR;5M*JVr-YcrfJ^uRCgNh=8^iEU|lqy|mIf`@vrS~XEZ_)#V#0E%> zbg5BkA|><=k=~^D4hg*`)IiFa=l@>Jnz@*F)|$EDj?~nHNJUP_w3BX~MNnK?b!2&GLC?GJ&V@gcRh;fXGxkoVRh{ zG~A{Z41=OgMG;whtQekogGu~LHvQo$hD)RNI>DQK}eox$6La~T4% z*tp+ko?V6o6lLf&AiMkeY3?TY>ai$>sOzt_U+tkD9cC-DOPl8(JQeOQ8JT@`n5>qw zr~4V{^L!wz-ArAC$rVcHwWtfR`ZnI(C--o}|A(`VsczqZHSRc;LyIWo`)ksvCEiq0{PSSt^h} zAJ->UHJ-gT8dt{x^D|`ho7q zHfqstcCb8`c(YC6HZ)(oXCJ>0faRf3|kJRH6Ha8-(7D=5EEsTGEpKx zEW}{WMun`D%}&VV#;R;ZqsEU5dvU8ez(3qj#asoyuc=m+TsuqUJNR0 zZQGZf8XSNNXKx`Y9rIg+S|%m@`z>JNf2kLQRVQn;a1p6<~4I5r~HXItZ9RGF$wvbFV*r^)`b@ zi7IW-Btq8ROZNDX1*02XOI5Ucn)r+rn9DNI<=DcL(J>1Lp48;4TzAX+UD`)FXvBfp zM)gLABvEK#;&A&WzP%HlBfn7_Z5Ye4DI@b5E=TEKsb%oK#vy7R!!INirssZg*z))M zuey$>hwhIH9+EV55>(OsMYxKnjfb=*Yhxogx{^Avd?ney2#ay$gjK zL4=ds2AiUPr%J2ZM_QDEF5wW?rWdr&moEa)($!TOaZ}uZ|6O9xGlKToj~^G~UMnX8 zsOE=VW#8oitG3y!F-!GAt0sQC6Ptw#v-OQnuuy{Usq{zzF@#{XGJ%Y1;jz&ZjJH;4 zV2W%x*Nu&hU7AniO{|(a!GzVNLz}L`e)_IvxW0nB{aCj*GK?A0A_PWboD6PL2UUep z%LQRP>eW*$p`9&H!q=G}3#@l7d8IU`p0cFsPGB6Pm2M75k8XGL2GVc&Uhz4P_zPa- zKiS@xkl_{5vo+bqxNs91&*d(7hhO=g1(Xv|Z88q{?$dqLGkmc}!Iq@*)~S~EVU4U( z8*U7oY(OCGVyYzfjDC{ECaQa2DtU8jo)V?GS_$HP4ls_{M*Jm6N$3I{Lp~y6z}oA< z$~h`yf|lH{dZdCly**ys!V7aI#^Ues*^29TJ^4Ee8_}vzS4be~-rdv{T9`hTyT}N+ ztX3a{Uc<0%DZ(^G2CQZ^q)DR~Y~ULQs8zZ8%lA)ILPiz8MxZ?>h*&4vRFT(3q6#zu z!feOgZPCefwRO<wd=1c|Ax6Z;?ks5 zxZqK|QRpqkAr$f9{bN%^#YQx1`-Zk`3X|X9!j$e2;*Z-3Dgslr5hI70$!Np;Qzbc* z;KiMxD_0r)vc58Xf6%7`yC&t)p5Tj;p&?C>0_k6UKCFIXvRXAqX4)_vHC3fh62T4y z__N*K9I^uOV1-91RzFndz(h~+oZZ{*P~N_^|MectyLkjR5q!Es{6W%oooX;>^O}`x zo22p+-+292Q#j2=x@`1J#`l&f`${>){07xm`^@`}W?MxUK%|R;v#gLnW#w|3Ql9;p z!k=_VxQ8kq)KT)fjb6~t{495|+_Y#Ne2{&=gjI`_4J%Ws&2L3BZ2jk@+ALC*-%_3L zEcHV^G@oRN8B^Nvo)~5DZcYn@c*-RXRpQlAthwiUrt)RlB3`q>8W2Ci-Rl;-Gm$9TiJV@>x9sDD9>9!+dTe2(p; z$4Y%r(RbZ`Bk|KY2~v9y9gP@u_}z?7ichWdSFb(A#p_5XeI1z zLyA1t6}U-{+h*jizF$(|$LQU`D}dmtIk;{maNqlrv813g&hb(rq`WsIVnBST6BTJI zLGWrr&*7-dpqWql8J$$g3HS11=fl=-6+H?+d-5zaI?a|2_i&}&hGZUMJk}r*gMTSV z2<#qsKve4l{E(sfk!xB%jZDF^>j!Zls4LbLkUoZrZ0nnAVrr zs1LRvbWL2oxGW#M<(zZRA-eU}bc;++;DZ&n z^@cxj@t&0I3_8NUAEQ@?n05)yB$K* zJ8{XnSP)Vb1fNAzdA0MPWaWYCHs_i}mk%c=C2j?3`qh9Xz{@dHOnfxhOp!d@d2>~nKb(m)C+O+!ODP-8 zp$IPd${S>iKq|wrh}0~jZ0CkjEF2csxl-#h3%sQ^`1Y1gnPd~h$ zgByx;0yD`ux+kt*CKuh~x^7E0I|_eO;sUAPRA`%R63zG>P5^sPXyws z64k_Fq`s;+$0Rs7BYO})56a3}l(HycPKVg~3u@71zf3fpA9C*-xN+#)^6(vxoxE>W z-3eNQ=zx`+t_7wiB{#eIFORO_X=B9&A);E~hMII+4I{_R%tI)rIQbc-@qt-4w$3(O z;9()O3njKfRPZv`@$I%9FmVmtPuplfv=cEd;5lDwAk~_uzVw)pK@7Pn%65yd&R{|E zyOW)HoWAIRR}`d7b9WCnAhM*7r+!i9`}GGL7?ke-1OnIyc=S;ePtd7D&_xWRY3u8E zD6Bh?+o0&s#wahq=?p#`WdP zOVvR`ZLvz7OSN9nO``ZC^CoV|&*aOwbK-|xOR~Ed(H;)cAye2+8O;tPFbRi0Tp8Ls zyBVTj_zLMH{I=y;f+xE2;4OUCWswtq_E|PV@)pr{!b5gXRWM5M)v#pYzU#Djt(QPN zWFudaL)r9RzEJ+5NA}r0%RAT44<@tOCIF^`ZMb=a>xNC!Nul`P=$ltp*#RnKiP6iA z(b&mwu@_|wqYpQSvGE8GQS0W+3|y(#;K-bA_+O8{_~k;G1~>au-dt3YIKt)H`p3~F+R?(AcO*uEb6@5(x{n-4 z$YASQ(9yWVFmJZiLWfx}J?EEXhP?u7W0o@!l?A(<1oX;OBnanO6N@+<61gQ+t!8KV zV3bM+p`wTBa*-GtzgQV4)xj zWKueKnoP}3RXr%D08v2p2ebVvjNwg^Bx`N|l>-i&9z^?h5W=!^us1#4#RN)bG0{?3sy zBHjF2lqW|CX$86;D?E9$94_6~B&mp0)oWgbXv41JOEXG0vy~pi z+aQ8L`=q5=XRL2qg9ko)a`tSu+`9KG7Y7~ZxOhyINiAU%*!;P8YyLP}iEWRQPCHo~aVh}M_KvHCWU7eoiIJ9h2`qq(2O z;O@#ne{QgaAH1B?3r4geKes3m&u|A!(8N=KFJ{Z_niqIt&sUo|$COh8Z>+RFl*rnJ zzo3p}U-O#TIW5894|b0eXIxb8Y3&`?ZS+UPk(jivOCGTvY4$f}C*x53U?)u6(&hc# zYGibPOa4Gn`62fcoE=F6jy9#*fitzFjXrTB%5HGn?)SSK^Hmo>EL)A*sMe8`#V9CA&c} zll-DbsfzZx9;*#a;1C}V92$}#chOCHsHu#&L>7^hNIBf-M-9YlTt=w=>%C_*&iKRH zA3Xq?HPWAIdPTA&-fW#zKsbLixCZ^Wy`(2uIaJ>h&GX--Pr@j!IP=?Xie#7+`o_VSnmQ%G0>IF2bZjk zl0^ZI-8KuDTr=H-*sjF$x)3WrHO{!ZXD>a3zaQ9e)P!pXK1MPT+dH$RniP@I{?P-D zs|m3F{z&0Bjl(@wY&ki^#hs_sVSX7mbwhRnE$+22p{lz2hjTVQ8M5DU!YUxiYQ>DV zcWm#COUg;L&1?HUOxFCFNzR!zdptW>I^->|q(2mJ{ac!q^rvyKGFA3!%Xwq)S1 z`h-8t{$h-9x2=?i6Ap3RhjLnxe#)wtf~Dyj0-y@XkKaFB_oxl)-M8G<7+O_FC_%gS zzFLv`PgJ`jk_nQ-7g0OUD(hdokXHgq?V1rPklJsz;gcV)1w8*a+e&je;fd$J=pGp0 zGL8q_JM9-aOIYL?;3;v5pL2zSMmDPINH6RL>9x#Uz<2i4!z$F3ix_Xkc=FYwPjncF z>YIqWK6C68gZ3dVw}%RQ-u!veBI4-C;!k_LkHXiLGvREMLdgX-VzZ6o(A>(~yeL zKXpVEfyoGy~!zhqPxcZ$civCyg2 zU>Nl=;k0C>eR;sEGjIyd|6D7lBK~Vfd3Wrm{DagegR9Vu?v_hqrGB6r#PIe07Y%lA ztFOq4@q9XbVoLv$)D16stvCDVkm3680&=jT+9HERLh_-t7GQMwm z75H6EluPjALPWygfO2t7rO>#WVh(1jv)) zg-lROb9aL(mz%PoXK~3_)|$zrZ*Y1-ZO2fAsjmx$0g!ETEUoJTzC22~gP74)dq94u ztX)j3?XG3oM%^ZB`l1&)q*z}35ku_X+XE0E*ocvG$9Q|Oa>kksL#DzFhoo{ONGIVG zSvazV;(^O-zSGQeX;B)_srh{MIYTiM$NOt*j>TvuBB?uDE?m@r2O70w6~1U7{a|1I zHga1&>_pa1rr5+)wabJDX+QbrovmJYX?fM75fiVFpK-}pMwTsZlY?+s6w|`itbTsy zzWWMHFz>w)>MUaMcZ#igu?DNaYtD@lXtj4@(e*Yj`-Qf(X?L+A{TOE7K)Cxw>M6&# zhcGdfz^LQgHm{klL3p&B)H`&Hj{VU@()=Qqk(NozQA@MVhX{7tma%kkfC7mI1E8c; zImwQosQn-3(v;3VZ7Ih$gNmjxW=zrndy^RXcg_?KL&Lk6aHY)`lJ6P0*v5h2Cl;z0 z(d$LD&S;bWZ>yQPOJCa(sr$0FQ3?#n$KQCnT9_rLYtYl@^X+&3IEriX=;=wUn|&dh z;TZY8O?71pwoKrVSMAd6ULyW*00TCg)!F;=3RJ#v$5C_%Vq(CPY8~D9Ysh=ge0)H( z4?b$>aVC_l{o#k&c9qM0hRNYXn~8n@kVv^u&oy*4&qw-7z#G0^alfu+TKeght#!fR zd|spK#}q!J&n`wI_Z>E)c(T5T;W%c+D-tl7!0xf=<1x{4eDYnOlYp;fhi03cudoI@ z#QtuE5`YvWnLdDO=PA*WFT*VdHl~)xE_+gq^?k5IaMZROA_mNAkFf_`ca8bk5BewnGIzvj%xuE>>s| ze*HNB5(m0{l#ht}y=}Wuqfew&W2tOsFlAJ2?MWs00S+1XFsl(b!o+qG1c)hT{iJOB zW&1@GPtHT0AaqQ}mf;J^wJ4vws}enYA7XxTk=}7!NA_QsBKFY@vdkQtn11*4+?%Qd~m22wpPq{f97*yd_B%u-K zo^H8`#PM`i#dy%=dOh5P@WcjP^w;%_NhN6W_*U{(f(%1OyB*~SUv-)?YPwZzzB&ZC zCE;b0tZR>iv|BaIr&O^y3^b8l#7wI zS7$pbTxt9zuX~;M5U|J3&mo)0=phmq?;Dk(lwPi2x-HdCI@j-X$h zppiAHVB`G6Krv@k0Rm%~+}+^ zO8vQ=>TmXzgcRTC_BWJRF4?pr&VBYiU;5|X&^{3(n@~n24^ym53U+@bzd?h6Z@QAh z_PUA%s~&z*S#Z`&o(qu;2wSs9%iNw2`# zIFj3zGzWD?pE82yHE~G7aw8nRlHJ{=l_7|Loz>hk>AQS`W0Or$N{!K0MIjVbmpcuW zU$t3Bq)atWuH{$FOBtmv{&%VH_=%jNoX_t^!3C_S>=ao~W%b`XfnK4di@G6!ch@bx zRdS>K?jafvYaMxShpPJy-Clb&9#T0M&Y$%_L^k1-&g7PT;}~3wY&BZKp@;08jrbZ} zeY;PeWla3YOxPQ!-{UYSTpT>IRic$qV!10iyxv&k$Qd=FlRH<_9rm%ur|D)Ue%#o) z*2OcB2B*+52hI5a(}i8JckU?2d!vmrVA&2(0JhLtMmIRAATl#K=^}l-C=DkJ3eG{u zB&0H|u?i3Ad^TG09Nd&O;DTnfIa+}jU8QGA{&d6_!HQK6?p1gkNUS9oAJ(QQeIrfL zm$Nx>c3BDJy)GO7tzRvel;?IneTJDaJq&7*w6@H7qmlJ)ux_`}Eu5hDSAm1W_O1Ou z0ydQFPgy~ui=b=cOBoc#zj%+9I~`W%_7`dW*dg{=qDzz5#X!5u-MVV=!w1Lwixd57 z5-Xprr~0r`Ca%?k2Of;0j~F92=2(c zo#LsG{Gb1uF{C z_QGK$U2wjAP1&&)CQ6{`qOyE+gWTFV3rLw#=KP!%iV<9`lD{DfRjD(e7RP?OT3HBiiZH>H-I{UkOss$eC8qndOQN_84SwsT}Bfn-=Qa73Qkl>9OkD5Qp(CnePn=dXV74uwg%e zY<|kq^ffg~xfEz2`@5#pUwF*=Lno8%v3r$j1SLhG8-dFzi3l-2eH|hP&98<^l%fUF z5J5CwwYT-%b_tOEBs26nJS1_B45qT*!VC(O%}m5>?`8PknRP#u z;?lUua#f>R7F%<8r-h(eUCcHC(+oIEWsVUXlec0E08)+P#Km#t6;q`-waCx0LU)Zr z*`v(KI=|L48f6NT91;t7RdfIXQlec>l6~8<@xMzhZozMq^7g#XU#xrC?p zaI{{J<%|jqb3CoGySS6-UK;-@Qg@GHu5A6B)nfPKk20^Em|0`e50Uzv0ZoB2-I;=r z)GF~eRSUtRjywrZ?8Pe+W7}F{Dc>ddmpTK?B<8LzBwZ5qNB_)6jjuL?jj+OojE{2< zP8}}zx#XH!vvBV?8M=x#xd*FPlxoId;>8QjV_JbaHAA1jUL=vKS6_9Q{5&t*94hU2 zgRiUFGW(bilJC6T@}z}8)6*h?Nw_fE9IcTu0d)*WWU!|N20MmNQ@3m?Shmaun_W{A z7vkyp*^%NRFLk8mdU~mIZv#TyYAk}U#g-umv(5yzHAN-Q${t&_Kal$I?^;?3gB z3oL2)rkJ-DQ^Dz2XY*rtPZ%vnLN03yrM6ibS3XkO`zgTJ@)S~zzk0qM4EoD2YFzNp zu;wBwl#NtQ{`+O5eaa z+$n&O`0G4F&&iy&&o@2$t;-D!Lk%}_cd%aNwru?hm<=G~Az@%XyUPDT`6i*I?$KX7 zi&qbwo(f6Jgq!jDiMXu{@lZP!B`B#U*MJ0G$*xngqFfCJdCT2L2Ptyr*)mN*%=Dj#{qh8b-IPAOf+A6E;eju-U7R*SMB9?+~>_Bc-A#Xtk zf$yOBy_tLA%bGE3&-P#hLX*BbxBHMYb3J4qrF8;06w{cimmh0oU2 zI`1eY1@ggvHt)1E3pkr;6-~0tp?e_@zuuP!36Slu+&q8BJKuK+jNnu0boCHr;uLD4 zo7L$`x6ZwP_e<-x$X_>1d9Pe%)kA@y79lA6Q5Th~W!QaxvCZn+0`pr^kNG=wxL3gk zjMq|l%^8AG*20c36e0O4-f~ydpSx>Gl3Y8xxj2W^p(62fUn*Y6^OxRKIP)Ac+%6eD zDmUKNA55$KP6Zs*WGRv=F-IrlmsOYIas1HLD#kB%bQ;83kGT~798kHi`=gfU3TD2{<`-~smGy6;+4;oqj+Vhp4SchT$& zyZPe)u$%*fQ4l*(yh)p&i?uDfwS=q|b>epa3X<~>cDU2Xelu|-w5SKpglJWn>*B6y z#!AjAy==**hQzdqtcVmn?o+ksszmCA&EnmmwK_t~5<-UHe;N}H98Q5eN3r= zbHV;4rU7N&sCLY)5{;Y^ojbsL$Q`fjt6yb5Dw7-W($#yAN`_c0=rSBYvKX3pO0BB% zb8fGn9P+`H72w#v#Iwqfwt)L{r;s z@8ZYz{5^OBnXSZE-o%#NQ{Z_=w;@ov0=WfET$v)XPMs!?RsnPYm{V3sk`emG^2)e> zkm0oK$Xv~V)M}Kr#X@8_ z(ez18&ls?1BzlJ?D!%FOFJj~-W^~v}6GKWM{?q*xOvdi{OM7i$}xw|>uB zeFS>AaF5Z5tC8n!g!v^VUJdCyb4vcqf`R&*;(aik*3#e5-%rj;tyNTB={ft`@*1Z4 zJj97wqoe-im>a`Df~oDx(VFzgZ+|DhtdH}Cj2T`__;(-^Fl!|=8KiwUe}zMbgQ^g_ zoh1F8r7Gc8NqTfgtYqg%gSFKoA?&<%bviidfJY~`RHmC=6xcM|(6b7F^KVb`e>%vy z$&$41Wr1|Tt|F(`JPORoSLo07gWM5;Y)47>6BAoqmyjib$`j*!+|cACg>hW>W5>Ru zu$+Sw*yFo>a{UdUNRVe z_E8r4nSJ(t3_D5lY~tF{`Fh>fvxzn7ZT;hM{f`D|zZ=!Q2K_0mmwr=TwESyt$vRu+ z(UEcsYx)?b!^~GGSY8Iwt9lo6nt=*T{qIs^n*Ji$_|DNJ=K6N?1WiGyH& ze3b|DT3{gC#rU3Af#&K~P1&6Ku;7E+m$$;uwF8y9%kPd|nsd;=E1BAdf>48A)LhOo zrUUb3smiR?fE%WYpXjP~`eFUdpX=@{^W|HsMh^XKf2KL9Y!_jr(A4(y(C*}7*MJ7U zgu^0VZ(c!)Lh^v`y2(mpe_4`?n_w38aI3Y@^|c-jb$M%~XbGC5U8}h{6zX{y@X+mW zK*pTB^l3D(B=Ao3KQFg> z%=0dIBK*T?#qyL=dYzTpGG-Qp72adQTXom)%Mt@~6(W@-0~r%TUk|IaG3WYUZ%lkg zmFuD6(J4(b%R~IsF-R3Ef_m2(anow0D=oLz!@sa6UYD1dC+KFHg0i=$w(yNGz7|*N z{ED@P(TA0j3{B>r6Hhc=HcVQHOTrfz*>i;-`b?h!Tr1-WxC{9KT*VC^#aup4liL$E z`bT$8%U;^U{c8Hd9D{E;I1#geG2^DEBpd29iZj1*q=kk2upVDU;5B#>?()g^ze_3- z0+9lswBLE}SKgI4)X|>~I^3T)Z}>Z1&6f zXfrr$l(E|KMJ{I^Bx!G920+3e=D=XT-H54=+s4}Lcit5Cr)lU3F9_EkgP9HLJl?5p z@kYg)oGQ@%+OcIDKG#T2l9*@dDPs5dvcPFCNRMi3D62UguJwCk32ty2N6^4pmyse* z{{|ZU0!VJlQ$TgGhT2orIlb^XxZzh2^Ot5ySpTITOTr-8=f1?LG$de_ME%fOQKgp{ zqO(?~^!HAko0X3CCzlP|J`aN{0%EnR?AAWQafuF6^nni*b!U;$Xx(Dra@5Hss=eDO zn0jOSEe7vcpZE3UTp#*~|L4=$mP7$yOszSvfdX!KXk+|jftRTJ<)rL-^mSry9tGJJ zSQMb!MPU9Da51%&)<9_oKk9dI?FQh$3XV1m`_6xtc#gsRL>WDfQ$@eSlJ1OqcCw^A zLe>O{^al9M{O;^DoP0&(FNB(6kqy5jg&240DZ(CK^GyL>+(Ym@_X~Rc`GY{w^3-86 zVc>uVI~AP@%*~Oxl&rnRkY z-`A(i^i>I3&+c8`?)U(ijA%s_&VtBHxYOSg?)FXNUQH^w%EOV*Sr%W6=G2la5F!gn zfYFPcGwK|Dnnnp%RfPA=YGeSIkKSA#0$brqoPXshE{fus8pd2Bhpz1L1NzIK?EAxeCrUQKP;bG!Pj|f%X}qTHHJWb7SsgZl zz9U!=4vZhbmGjx$6YkZah8tZng26EX6+)y}{0p7%^@D+;BSx&*7YRwY;7$YOqkQ_A z8U6Mbog{i%kd9D7a(oT$)eni#Q2thpa6JMGvy5J*^q4oD<~!=uTUAfOhlGhu5E z*Lr=(HevpVpMtQ=2SSO|}`x7R@lEbRdZhQr^8#Mj5NLAgI ztOa8A_{f87_*$!!qbSK`s7GbP7M~doJkXRFg|>-Xwz!XlWGbQ4LA?;Jd-NG zgKGb~R301A5lIEj5K%aen70H_ti)@nrP;Drc;8&>?B)l!f0s-Z9Z`WwM?;vy9kekr z+d^yG8q&3Yx&&tixbe^5(f+w85FfJV9y6t!wHkY`%ITvEq7u{@jiGl&;9sF)7sbk^ zJY*ZKAk2KU?(qOhr~Fb=VLlfBr|XBlHb@?4`v&(|8FXQx zoQKAdt!ML+1ZfZ7s0sX&7jcQauw$P1TNO!I>X2kYw0mqqD&%S-WP^%Xw=UeL3f-BV zAQd;V{lV?!(%!pn%OK(d$Ziv=64d4F?zd;X!)+GrfikXj(U7?3D=Juc=Xg=NWS%$R z=f&r{_M42;fy=_($T+}{5ExfAbOlIRh$wIQy-Y$@NX4n8kFt`BiO`Q|0QyI+zo_00+O>pNwVVs#ARWpBN`joht?i}DFu9PG zXP@-b1fj`-i^j4sa4)r8HwF)PH~TFi_o?-RZtxdXCOl*>aRtPzo!?u$!wvp;V)n(V zObHyCh2CnUJ^Hyer$*SpN|M<`v66t22WC>H!6L6Xw{3L4(siuGbKOgr?Cl!=@?&AW z$$r1yVReJ;+}JPb1VazFoX-mg*B-S@_QxU*w z{w^(du%};=UuV^B@5r#y){{p-jba4wR#c6{+C%EEv$|Bugv`m!HY4j9s6e}vbzM;I zn8&Q?E99cbdX22;hR2JJy1T7x)L&zeU4+0ng8`-F0u{a}R-V#*TJ0v&EYMliun~Z zy%kzmd(Zc8XV9V2a+PS1_eLMz`2gKLx_7kJp2dO#uOqI|>ujv$4}^{Fr+#Jf9Z*+s z{F+|jP7*k!8O9O}KEg#TY;1$%)4%H8Q|b^5`;Z7iZdq7Ll37riBeF|n0|dXaI~9*= zBB3XsCiJHHa#^*{HrV2K&dxT116x;7W0Z+q)8S}@#8U8mk<%C#OYK+@96_7rH4Q*driqYvr+bh;_Yp zlzZA}5_c8Gx_5P#t7;7@VU|1&8@}o{ZXKWR^dvz8{o}r9cE*HQjzEGeFm{N`{Wn~w zj}*JIUc6N6rh-ijcD?XfI-ML{6@P%cl!iFaf`ei6M%}7wwEy9o1ugm}l4@+y{5<;f z5z)v)D#0sye-rnyh!GTLSzs_-v=UR9KNRDGeB|&{7mnaNVco{>1VE?x3&`s8otl(| z(DjqlT{V0iCLK@^bF=lD*yNW`mV=3>0z{v?3FdIAdCPk6&OdXn84c2kDr6sfYd^IA z8I(wHdXzQ#v-(J7?9_>p*}_kLL{Rvm{AOi|Uk|6EYgDQGWajU^$M%ChS8V3Id}o{F z!PCMkFQ%r>fQA{I+}}gpa`<0v>A&Wm$Pfv)opQfJr;lL-(RkaTdO{t)V%G|xx;#EV zBP)dxK0soCiIu??$Y%A%U*FJ(x9nb={K}`qsxr&f-6S|}D*6mCKbsF_Z{cgteT^%#fN@QGV6lvg=+9@CLmGZ9?1gmE;3glN^PP=vHDhip_U1`@EM6r5G zT<2Z!7@~f3ZBAt%sYsOpmi8~T$V4g~sk@iNKo-xI^(SWe#pAN?_Fi~y8A||9_S5iI zCl9u{^EzLaXk{mMpNoI?N6_i-`4QWOJ?A|<{|3>8Z1(aQ5 zU6EqK>@ZemZr) z3uTcMksqh{CF&A2j;J#pg*^nZUw^5uTS0euQG+dh6_f~7Ha2m8f+5!M@ztvh$PI`Z zs#_?`Jk*{!=O;uWV(=|2G^T&WEFm3s*m62QH3qgrMLb+r_aeyc*CLZXcv>J15}#6{ z;9S4Y^$1EY<2H{Pm>9rfaxk63_OFH13nUsDRRY-~+l*kr-tu3KELg33J#C4Ne zBP2N(pa8=`MBO_q=#IHHZK$E;ZEdu{?7ROi$+a}ZPDRh8TmOzCbs|rhh|bdqpvbdQ z#kH7g)#4aCOgN3IQ%7_pUCckqACQyvu0|{8N=<$UniRO$y7btLWK;eUu>6X&S`d*_ z+Jc$;_MVz+#y==gs{C1tkj~V18v?FYPQWW>Nnv}0LqPfPaF?oxqi(S7fmk=`7W8@L zpsI*<5WQlt>Bh-Gh{7Mp%%`WsH@|ljCy}@!6qD6PCMB;}uOVSsskBvx@NgBtlCO%z0}lv+(eS~=&=%smFm!sm`+@oC^|19 z(48!IUGfrsaxqSG%7=dq42o9lm#*$4YXzI-?MmNAPnj(TqX--_4@E;QLRZ^Qg^6(S zbT>pKN1FFx$?YHx~o-WosT>FXX^DrNS^gQ{V>t(~9XMR7>(CaaHSS=c>fqq4LAyFriYj_{G__NN7qXRb zeCX4p3_luaxdiWDyi9b#xgq(Xz%9;Jpgtt%4wKG^N33ACu-8Dgs6rQ{Lil}?71nAG zVL~XGXgV`ej%9Vc&ElT%WrPL+2cGt&j zsXU?`ROwkp{1C+YeYH_mOlp(1-^gXDqPF#$ZAb`;Pw!o=_im&G)>K=mPL7~DcF!a< zy-Nt0TYzn`%gK{N7#0KVi0xkt-y%Q@%7={cNkG;y-_|6!+~6apdjys`TD*YY6)J6hO;fS z4XO&-?j|PPw*yXIlWK!qPSH?rE`v_qF2vzpC{A{18ofefR%7f`$`{VR_uhW1?#Q+f zpL42@hrDkJ%qNnb5<1t>LHT08hx^y0wFC_rp26Bn0@o^f9c1yuq*WvfANCrU;~6xl z(^6+HnhmG+gZX z1O)%Yn%(_`XH}VmhYG_dcvV41)<=Y#-LW;(W)hDXq8!p*R85zy(j41HSv&Ma*(U1@ zoyrhjRcRs!3{(P%EyPdY*tO3qVx>i#Z>Y0)&{9PAK#pgs)+v!)*1>$e5WbVlM1*^&GR$D$-sq{fm^IK`dZkp{ z{u2peTnin1(JytC+892YfS6%fcALA`i@o*lnPKg}N*v^oQUQOi|Ty@A0*`$0RISISX_(LM9!retdTcY;BeyW~-++ z>mN?m8hDbWmHWj5^A_^4TTyz=f!y_RmhNe%G5{kOAL(OnO>U z)|vrsAd55%fAIG8^s+En1n0{QFuO z6ps5~s|k#AC-8dt@t(?Rg;JUCT7p0+Bao+Yoes<;1D1JN@i+&VL)z;{+sUlyW=oT6 zA(As@%eUfFa3oFR`XC<#m9g6`%l01f1~Z?QOA9>T)B{(F|fF_a@8eK295 z8Z}k%01YpRMnyjPD|aTosb>#(#ctPqZchE;e9%{NCvYD40txc!ZcF#(6i6j>))8TN`-e$s|#VEHxmkFm`ympqDQ~Xm>KGvp+gq#^$R$1)-vg=vG#z32@{9a)yCHF|I5YhgvRB6x% zQw4cf1|I@`?^t1QO(-DVd#!1diD+VFFf(`RQz*ePMBor1a8S4_x!MWMQ1@ z4Nlz^A2KO!hz31O1!p;l9f*0Qq?2C=baORj<(Y(bO??ESl^8#~bRFJV1l2TsvL7$j;oCf0tLn}2jxrVnQF zjpSfrY~8Oree?z6gr1=U+H6_+k3Ck>2cpTq8gf4W(@9UuKVwFccMjk^&^AvbuD3V_ zbzSbAaoG+@f&!`C3wojdoGoMi+%N%nih}^}Skmgy(Qih)!D(n)5S-10jyFf9=gHYd zy5CV#xl1qc8=|zn4be%yWlrTFv%7^gsd8#wi7Of?EJm1)J#sWC}UAWOeX!44U zP$+GCuxF&d_i3TK2QDnHOX1w!)0=3vs|uRRvt_%ltLqGt4^21is@}`m^^-N*E9eUQ zUxR@EuRkvTH~D`<0ceQJc=eoiu|C~{HibO60JiuE5Xf{)9#XqXHip#~%qvF^pL8D< zZLevcYom`Oa>Zs<6WolJ!E>O~e4tpA)7(XsZtS+Tn^cd{%PdQ+@3a5DF8m`ga~=r# zGqtLh+NtCPf;PD=RcREJ5_1eRnB}UI2pyxDtND=CNJfKrnITT}F-IGmwe`)R`FfSO z$cbbTNj{)?((cHiU)e-8ypiNiQA0gByOWkgZs(8tNdSLxe72IF+ZOqmYK$Tf1FI(z@4IOg_J_Wk6+qGoT{CU^& zE|X2yNJmhEd)pit4q_CR3j7lN${)S@br*ZU4Kk}`{@lj*z|8WFE!pWx;ni$$)GqHmciwFw}!k=e@e5JHu=z*FuZE zFM1jBX6fwqyU2CX2#=V81hHP5m{}g2IZJ&AIoK+{a%~k*pIWWuxvW`vi_rpNfO@tJ zI_KF<$apR!uJ(I**sC`bTh;orR{#;D%?jl}-xD^nw(;pz(6nJpBmIeX<2ViQ?$&Zy zjQxK%I{~HA zSci7_!XK&5Gyd{1OWF|i875z!@c#}H1+4RSS%4qx5igust@E1brcyX~@eZzU@#n>l zG^b6&=IeR=Sqn9zU3(ZAM@dUpVSV8HaEIpD=TP&?re$f`21`c{WTV{A;)$`{A$F2@8@y-4QOfrYPl*Cw7LaJRk{qn*F&^F zQQ5WOoCwhnQ&lMMKayuJ>Gq)IO{L>R(wN=vWXOe7=sn+uFDA~SgEaXXC+s7S z-}Nzb=esUD&YoCmKB@cmMR8LbE{q*g$`7KgY!}pX$mPv0ZX&k?uIsoWf6Ynq^c>~l2d!gZ%iDV6P?k&*Psw7({DPb&i+_F9+P zc$xOc`;`7RaZ*v{;n_Gzh=RXM{HqfhDcL-Cv$p1q341~uf7swV&kqn2con&));)fu z7~$efzXGc!l!Auk2lf~j(*7xA4aGhm<{#O4W)LsF_o68-yy)*bI&7;w_vx>sEkQ0# z9*V778LkK~fnsCP?#_pd^}93^OP8ncc2d*?}$q5YzSnBfo&1>Nc+|KQIb(q zt=pM^Icb+z-hEE_LxgQ>?~Ws<^6Gzv916lg(m`E}5>%kyB+%c6D!)SRoNc^$f@j^q zadswqvUaPu?5MVC-~*)tAcvThBHc2 z<7-aiSFn#yP|eTQ1f=(C0pj-k;D`HAb;Y2fCP!mY>Y+~^gAdtbXbe?r^x{8~=)(%q={@sNK$~R*q($cAiWwvv>cg`zAe_Oh7S@^M#?vdbk3zr% z!EH{BNL>?91K2cwDTPC!>pK9;-`J<5SVxkWYdOLrEOos5XYF|;U9vY#;nt|U(-3^5 zNt$o%fHcAfpR^KUMYTfI9o|JyK~Y)=O$pV9NphoC_PX#4y3xs5{i zP_pNp*O_A5hhKPWQ$!!WVh~9cGnEg0B^Zup1~57-a}}c=U;Vg{*NqTmlaYTtv9@vN zmB-aPeQKDr7W1T?xVk%CE*~ggD#50##>OO~u%UP2>@Ux|AYN~qk=tqn0hxG1?V=gx z8_Cj@BR5rXkp*=Gt)aV zdz|zy9(K) zW*@cbByZUP4v$G2=tbLu%h&I*Q;D@SET1h~)$59qyyWnl8{pVgj9EKr%BI>`!}8?Y zk}`(B=p(QHk(~;b5ls>5v|IW}6VO^#K<4x^F~6Xgi`$J!9er&XbVu_bI`X7(pp9N_ zk9=!B*VbUb11t%3eF*R1E*qr3Svf!2z`4Zfe5N=KTfYJ%Z;oE)05Y>N+SJBxL(UVm z99%clUH3(lf7(RK(03T(*nh1*&c#cF&EmPw6!%afDtgl#M4ebJg~s2Ce2V{@JNUBw3;}7wIiqR6 zUEFXHbv7HnND7NNm1%6t^Zmy$+^q0b#n44xoEGMEa?%=^6(S z?gsxeme&Hui(3}A0iDP3t$Sc)9b@}ceL~sw;zXNx{6fd7!I%`7*3{vxsks)F*_WUG zRZYP+;{Aq5>#W+8DqAKMohx?CLjN>pb)2J?^9{Zd--L=QHRLUC^mX=(E19p^cOBg& zC?XTLyV9&1-)jk#I*s06eU{ zd>U=oRA?Gj96m)(w9F9h1W&Gf?CYgV^F+d(>-^#|sD{ayQ{3i*Q-8Qo{Ea z9BrE>IjOW=doSX~z8l(d5I>OEj&09y<>drV5**$e840E%Xn7$VfqV@=#`7BbWWA~`$()ZiX!|hRvATm0CK_J?AaP|R!1|_ML%sGeG+zV!OwC= z8jz7dDcU;(eO!=7nFHsenUTyOyD%2J@iWn9%vLe!9I!M0Gw&PHH2Qm~Lb1(Adk()G9X@B13Mo~5kmK;r**SkK+) z&B$?L>w>>on2|_*UF9wav4*vE98IGA!v0*?yuD6nc@QOW4mo-PGHgmB{7+MPkdk!$ zxNboj>_hynH?KH%{Mjqtyoik)&4)3-mik?o4?N!EsqFX7po!bFB3_rI*Erv3~5aye8&xOljF6KXR?{Zz5d*x@;!|@V|_WAHqQq0B+nLr3( zhML1jP3&mcqzm3u)2-lySC_%O8VSDiS0=sNNK9nnobh24!3xYCzvu{kW+o`{_J3oj z56oQrBYVHPFYCr-0l?j>AT@eAvU6rbiHf9U@B0u^jKA<6zmJ4Q7HCnbVLiG|5Qk)R zbLPHQAStc)fe{FXbPeO341<GeA+K>coHJ%ff;P+eXBQx_&+zNq0*&; z$=W_vM2J=8wA@i}9PhbRagQrXtYv~x<*@H+@BBvC3M~!6@ObJn%clycW0*AHx*Ay# z@fTCO+2tmv&7hwx#2F!=nlB2` zZvF662)8U*pz+B!Z1VD^*Y*?18qt?O4O~=Uu<44c$2u7j=%FV~q1yaW9 z-Ry#a45DtGQRUa!_N+o*A1jGd$d(!L=AYUtmiRIWb1CFeQoX2n!Q;F0CWwCcZn)jS zcl4OywO#GLmu9oCO0zc2j4WXz+EwA|ezAYZ%2H@;ea`5#17UZ&)0LHK)H9ROavKZe>d%Xm%Xq zO;gde8u$C9Et78X{YF)Evb#4(cL}mn#p?(jpGB53dyk|Rgcj9I8?CbY`<-%>Oa+*? zz$K~39s``VAZgXp5~Jz+;@a|a&oq85Nqo-gjEZ_>?yQ(@T{9!rHGSx-@BFoy6>ss9 zh5FCgdC9R!r~9g1=B>}4Lv{?9O27DlfkOJ42-31CLX714z{9N?VvgR-W_iH?J6aWr>EiE>GUlsZyMl z*+!NwIVRLL$ zJ0X5jdFg(2y)Wd*Uv$I5+gZ|9t&(D{Kz%1pf*Qc>FDnrnQ+D_izkrBfi zRl2u0r;kncjh?)JY8S|`oT!{K{&?{|eQy0^R3p==?$hLW-NC5!Fp(L1bhA75*#J{sbokw32pXjpnbAdzKrYAL8MOC#mljW_m#(YZ*gHdz!-#wH_h}v;D&n`b zlzeIb|85Wl!Lt{^W}fU`fDu+rUmlE z@(9z1t6h2-NFEQ68S&iet@ZaDavrdlm0d7?cDugLnqPq>OIJs>WOCOCcmGpWT>0Gn zgTnZ(DKqi1JRxyqMQ{`Ao8v#{s8-NAQ_iD3znSNM-tj2ZCtNRiT+Pm7vgE6Vex~35 zYEb})y;$CxT(VftlBgl0xY;0Rj*pmLzYN~Kr4;HvUtw>EDsi4Y6Zj_i`us$y>E3%^ zo(y{>eiS;8qQ`$@c0|a9j%8aW+4stFi>6l>;(yYCgvLIIVe&vUfyb*W-5}^Qo z*)H;{y!*7l@##nVpXjKv3saZocy>Lio@%$Z!P+(QGrL#qUw+g7%#yn@ia$@@B(0M{ z#XxpW%d>1Ff}0yXwe0*>@4Fr)8MaKi@;cJ1E3PM9XnqBi|F=7_w6HSBF+HexEJq&i zk#=oB_uVi>`<2V#>R->vs-((MZRmTw#`!<8w-%$e%1r-r##0*&1HX%zl|%&0C8k^KeLPcksKjr__RLs#I(N_2 zxWpvIWf+gy&xfi+CcWAD`N}nmVP$B^2+FoO)ts{E@dni<54jp(KJ@K(%(*%2Rk-AT z-2A#>!+ytj@@)cIkB)~Ep6p*+eSh5f`^nV9l>B65%W;S6TzCb!z0_$A(bqOs-ad-c zM&GqR%~R#$o3svj?w7!g5gGnI4*psB)(wG?I1`(w!;URR8$E*`-o=F+x^Hpd@@1a zun5=auQ5d!eeaygE^t-xAn zgCo!d9>dC<^-@XEVhU8G6^FCiXA<|zr5;YkFuXUlG_!l+;>x7Tm%Jp-kJ{7wC={or zMB$oz(hw8mprqqd7R!RziZx^w(%pII)}mo;^O)J7j4B}Y@ePBpp}mn3z3F6IFD6=m z=}(Yd(@R%f0#w5K2D(+3_77h~o$;5cyA5v;D{|i}0`~2C@ zoBt22SlWNH|A!xtg>+z@08w^x0{!`36mrN);p(HPMK}>~(V@e3QX3i|v;%zKJ`!+I ze*0UPV8{$|XdzNgVh7Ez2;{ylf;;NcLHTARg@{Y{>?CTkl zqkbgIQ{8+)G~7qh9&%0Qw6v(o-le=j>_bdIK+m&i%1U1D#wqHyOepFRpF{PU8?tSO zq_Owz8a@c=f#9blpeDE^dXdEq(ItQW_)V~iam)#=Gvpn=HHw>Hip%F4s;?|kg#JbV z@_FD4K)#D9W%wcs>1z2qo6SyqdRpSDB`}R-9@Doyu1a-YK8SHSo&^jI?9vG5}{(8Y71B zGo)tXkUca`Le+PX>$!@?#E#W}3jyIal_|PGkxnw&u;!Ns^e0!wW@w9cp#9qs7Rjq5 zzV0Ky`j0|Yo_}Pc&&3Q2aJ5*L90#{?-JhYm>Yt# zI_dQp4kQo{1$1$mwLnYFsw`FVSKT98Mm9W$KoEnIh|GhAgYGvg&ycTxh9J!zNJ?0$ z=K!fE?*N@PH28bRk$V=w5_YM(ZcL?|vg!E*fim9+YI|FP?pi1X{+%Zy?wC#PN$B)x z&;XxIONakRR;uhaOz#T#G@1m-30E+^L4hsHjVxLO2oEGcMvdi66JB!sL6yfd?CLZp z{248ozJ71iXf*a3YgGRL)J8$PDbRtNH0)DZFu4%4%3>Dp5*D%V^9i77g+sAwl2I&m z_b4YCl)SpL1Z$>wtLvwkU5}X`#8EgAlh$?5qqG)wA@g6Br64~%aMe9`dq<{bEPRju z5WihQO;M(I7rlR8xge&EC~4}{hJ);Kci$y-6Z!7nXSoPC*n1Pw3w(x0Yyy6bpP7mN zoc7Q8M~2CS6gBd5-I#pj7}9Gc<1hqvh@^qI{6OWb71dU1(HS((;heixo*=2}x1`^( z%U9f!N<~0MyUkz)V|N_vzuO_8K>Df7^~#kD)kNrJaOpW4dTYan(qfWP&t#80`^PP_|SjGqmSNA3vqCU zTy-VLViD0v;gI?2SzA(@^b5L2FZM4cDK1oy|G#1hO-Nd*WQzorwud<_bxunCXBO|P zc@=^FI>aug?DUg_w7aQ;N>QhXtreN{&M8eQ{F_H!`M&=Z#wotZN#4{;Iwpj~Py7JH zLEi$lf9PIUGvYdi_FTMLU#wJP3x2m-z0YH6@0i|0JaS5~Eq9rC0cxT4?UgEPice-- zC)EkKm=f=f#rdTP>C6Ic={CgaYTLnPLMmlDbuStt( zBXXIqrEaF-76?SV6FaF$%0GsiIDX}~SW0Wb$$#yemtzOAixxyRmqF|H&RC0(>w=_( zCneDUWs5=P!Jmx*G;r3{Kex18KLy$)5L^^Qa5j1eG1EdL9%H_AiqDgYfR(5QKMlpl&>Q7sdoQ;QvW@IrD%~y3&=CWTwaZlpVLcZM=uZ z5_5$Tb2zL=cP$SgXd1YAtde{D7uCNcBC~ayl(qBxZ;$Q zxdt!XBE{1I3uWbI60vit6qmE>CT(&(%8YuGbw|JC+YqpVKHM29b*bOR?KeieJmG4} zgAjzZ@Q-t*^uH%d#n^jRaTgaJ*H#?V2Si+>Y_N;n#Sg_DXNHz<%ynMPeEdhoN$}*l zUXCs4Q)iu9MH>R>#1=ex+SH5IAMOf)0nk7mhhb~`uP>lH8N^!B;#8otFMX%2lL1Kl z`|7D&DU8SF$iL{iZ~DJkFQaXAe1twvpry#o5xG9sTBZ1&WhY4RlH>U0^1Zh&DjXrP zQ7J8z_yp0rlT{xO*h0$~Xvza5lB;AG+uOy@RwM6CvrMDxQ_c@bii#VHUy8WO!zUK@ zayXWE28D@AjnLfqQv^UGB76I3vTtmYN7duT0S`}Dlo((ew0H0%Etayr+g3|BzYf0S zip(_pM;5w?zO9=!GnMF(@aP{I*5@7J?U4CJBK~WT?vNWnG@FrEaanx6$K6CQe$R}K z;5K{sI8n@tQGpyn|JAOL{eADYxXwEUI zuHTd$mHI1njs1q=_|>Tmr=`1X%ID_;@uL|>(?%be7zIV8)fHT|V3_`^Y@=xP05Ip_!C%e>q-tVTIpI#~lc{ByAj826Kh=1QUZU8k!NI$eQtDLS zQF808n-aUo31pEews<R9&+IIWGqBj%u3LfW#-n9$D07nEC$}YkD(S?T0U_J%Jz4 z;hhMO>%!AmL6TI&P%G#t*~(?t7&S96?SgiW&A*KZ9x^rjE-K5aXmmd~x)Hj-?$>Qe z0iGZ=51+P8yJndStLaXCs0saA6bYO0quWCYcpX@PNp~z}hpd~p_@B7WE~eN(+X5Y4 zNGh%};WE(p&BvJhlFAEn=PXKGGM4innF&TF?!)g1QR`Ui$*(OBRSzzv^_soFSysS_ zpW}*-e({)9xjbQ|9RC~ZN*Fq5C4Hb+(Xt9lPmfenikW|d#CIh zzBWhXy)EZ%CJcGiH|}XW3ntWjg#B{Lt_JtUMrfTqYCg+Ri_ls5CP9zdTexEuWKCox zcBYZ0h{`T2shKvVJ*!8P(3ijZgOp;7^?LI}HpGL{OiZ@4^IX2(vFrtjA~v)4d+|W$ zY<3@QxM58ro+*B9&;cREpKv~qFx36Y;NE@#NkS-9aI$_e5Si-OnS`j zinIg@Ef^krpW&JQWli;W@S!Fby;#pbvTx9pvq5;fdJFY0s3LCoCl34)>(d)!T{|Xx z;^X5kV*6$k_@D_prtj3QW6?XFjnQ!n=48cHW3+n5o#6CtZ5)=F+Ae&F9lL`5yful- zeu9_bhhjYT3vI#}L^$v^RN%TYwFCBiW}5_lwWKgh89sZ&bXj5jRuAx;)4;#e-{pkN zqrHUx<9@*E!DJq>1IAoEp(uyvQ@lt!T8LRl9+L5sk$0~>UZitvup3$&$WA)^)ZW+) zbGxbbN^PQA^7Vn2!t1&tK}k(dhROxniGq4$TWy%Lv-yuFQEM*Abn`|kr~k>vmyd3{m+!!i29#{i4d74 zMG<6SHjc0J53un{d}(Bj5qIB8ovqJFV$c;?GR9JAsXTeKOewdv5q-TdTlx9P)SIF^Yn~F|-D46!3 ziJ7Em>;I3UT@1ZTQnX+EZ;JNN^fI$Xn?LYx@GDrlw$}`ip_L{^2AjJJSFoaYP|cR? zTTJxd6bPzMTTIQF^GBd!%&$-5Pq(T4R7Lw4f9ZU{H0ZpoUV{5!sueGK!(xlQMX88)aZ_&&>O!@+l5ny(yquV&=^DGQJPE-<10U7>P7p_{_n6kVt z!X4Yv{ZzUvWGGHI8=<2FdIPu9)-uP6?(eL{)8kSuYe{}_rKw$(&IfqLCyhgQa;QwC zKd*W4dK17f?^`j+R;rlQA=V)i3OLI$Rwa~vJ@tK2o-k2tWxh0kV61$y^dB2hDVL|9 zu})#u0IPi70je2or;TO;IAN!ke1W`ow%?dPD&~r$m%eM0C|2WY#9iT)-O*NajU>tw z-r!X7aNK{|$lBypdXP@AW+g5C);QLhE%AQN4>7~XmlNt$g@a+221SD4 zf>jzt%Tmb2x^5`cvCJ%5tJP1tzB%RT?c4rj@5vA&Ek*;Lqebi0iX4oZ79+yKBF*XR zd54qs(}0@?o8fA+X;zB;bf1pmpBWDyJWth2es|>dJh*dL@L1@w(bj}{Q*>zce^eJJ zKRyup4wrz5@8o2i26F5rI*b-sY1}?wE0rLR54b+FUTBH87zeHWg5L)+ED*=8wj;}G zg~=Ap!J{7zs3yDJJZclRBCTUR`j$5b)Db(J_tvujU6?~o$Q5(3VQr8b67kpGEFbJ} zX%(>p%wrtt$)|J-2Z(y+uY=O6omplfj+pd zgWG3^g`a~7z--b@q zo;8`XL()r4=dSq9-EbUOiOvB{{o2lR$m9ycahLl zbrc88Sn;jV*Rz22?atT73o~b1&m|K+QVj9anOc57f6C0b39l~f(v8lhhC2oRBb!GW zVk2oL$1+ z`#5>6;7^Z1<{}hFx9qpjg|5kTZu)97$Y7UWY9$HBZU;{aU=uLu$?}$`m`5)03+67H zdvBgNpwW*w!q$o7?6d7~M(@=Hg>#-MMF|uyu97*rf}p~kcLh!to>6Rh_${MO+5XX_ zjXh`Wb^iJ^4SV+{VBYWMy?)3sGi> z?M)ePgAOLKN2t+u{1K%IRCcnx-M7Wfo4^pC7IGrrx88mjCT5x`sJGJ(x=#cfC0-$@J>Avi~h$yx8%jw`GEuA{~=jHv9^HK%F zt8#J|h)|H5Zp4ZVhPhJ)iHZBQ;58`ek*dRUBVvQycq`*xaBeh;U6@_7#UdqaE)2~y zj;;UHau1u-&1Mu^T6n-;Xa?RB>*ev~(@SwQ_67NN3gpb@-oFmSxTbpLKxA~r&nUC& zcA38ZvRJ0QbmP543Tu2eJ|GH>-Xhnc4ebczO`mnn&Az>qx9F#YUwbz+;p}d6;c@v< zVu}NK?SxkJ4>%}k@$FCXziZ#y3bRkwP{*Srv{_M)$AWL-fF!6D&cq9ZeA5DDGn|w!y z-LTg6UfK_`840LrdBurj9hJ>r|8vGF=@v)54K%rq$M7~5@3k>b)W-TQ%`dMkc1v_# zcl=>D{+LS1YN*1)Zj1rihQ?A^nmrHT9p6&{8~KBK!1p1YJw&>eam9yav9$UPZ;L&> zj$>l3SHBx?+V{GJt=1s-(U>bY#yt>=+0~3GD)^DZP_Sv?2E;I~ zzeL5>WJn-WV^D3w)3{KN@7d^USSW1ZVnw(C$GzUF)sspKEG#mQ%oupy&I9803w+-; zjMEL`;S@+53z~PyNbcne-D=~?6p+NFKfsJ%yjyM+87L=61)V-8{CC`4YT-&%&V7>A z>U?5+eu$gJimo#ytoOA6R?=C0ia$hd->2k{xk)xUm{Nw55$Lpo>QYIIS*5$w?)W;8 zHW0M<0byACF7RUMx!;&%b_D#vnSzpAXKGdFBNcqHwErhrwYh{Urdvg$Qddgr$aom# zRNK97Y{&JY?l^hjf}Mt}tGdy8Mvc+=B5xL#!0#;e#?{{_-H+wlvAa{EzB(G`W2Y7 zavA-#jJO4gM09wvGkBPWQb`i067lo%GX2_pg!oCqQ><1mjItK@2g#bXisH-{T_|f& zIZ$mDuKeSt_V8gF}iil|m4)8JOHx+jytq6JVieIh5r4t>{LJ?o8`H8y+Q<`fzyLs+6(@k9TefpW)==gBqj z&*S0ShU_1%0II5lm|JNmAlEMJF=S*YmpY!-Gf zeJ$c^HEX|N)QpihPe@%aD93B;As@Kb4D0_%FP!+1ue_n!4*yaTmnl7)1Mxerz=rnj zU*^MYO|+OJeIhq%f?he&CUef-8hX@R3-`5?Gt$bmb{M7BR+TKsEnLt5pDIG8ighk_ zJ}3+8zyss((}!XZQGmrKmNp{*mc0uje3rKdF~N zMvP?S5k-npLFCF2&F&ad&#W`YBcLCH3pldP2Myuj(t;HJS?`ti}H2PNu zqglxSt#h;eIQZw>$YIMjujO*@Hk!94RPbVBQ}(fLcOWO-$ZAl}GUYmRl+RA>wP5#n zmuuHN?~Fgd!CQDT0bG*8yhneXX480w%w{z|$S=a*g$+_B4UCa9G+9|r^CeAes?=?! zDy{K$IH%O-4)tJLz0H=qT+Z!VQkO?~AA&YEJh+V)Dve1EJ0uQLM6wdcUi4VnlG!h& zU2(FvPxjR6v<-;EJ>5>_?3U9Xq2U~m)OPq?scYX|4_<^L9bWKN3p2@{M}f%^2gYdC z2}Q4;xGy6Y7|O)Y7(<4G`ItasM8~D8wk}0PH`;Mo&J!Vgvusy}r91l-; z?C)^bA{=5`-7jph*&SWD4vxa5CcbUA$%*cO(^PF)sadh*qb@I0632V)aZgHNRu5<~ zy(nZig2BXrNQ*f_xUNc1zg76>{`dncZsnyc&YH^&bNJ;b=4dPa$snR z(V!3j1Hlrbg9oQ}om1OyEw1o{tu0#C-G`l2+lL|YK_A?riPBBk-E5-W^Z8SUr_Dvb zLNgn+yKX978J~feHh%aDQh*tC(qc89X*`{{lJxi9IINvCP(z85G$sZ}J?fN5Jx1}P zz_IIT3*F89&5u4(s1-4s3OXkjSBPTnif0_n>CZ31^E~f^2l3f5qBkIKXbk1wElcqa zh*iM?(+cGZt~g0T*6jnVUqp*rP{B^Xa_e}Ka%0xZA_-~U$WPbv%gfGZ_FW1hQjHbw zsjwf(YzmCp3}XIv(#Do+rp!*PCd>yXUw|Y*E(k_QQahM5NY=JU6!qH_ErHcoK74%e z1MyAK0|k#+y*c`c;9LxuCK%-6V!8bs?=U?)P68lV5mjr1T+yzL({-!ZZM|VH-zp52yZ*JI_jn`HcM@|fl; zna;8z!mxb8oz@r@8O_Xm7jQv#4n$6d-!d!IZn1B9GOqS=74PL>#b1e8z#VtKOHpu^ z%MEqO?dyLJd~bvl$6U|r_Z`$BDZRHbyG52^j96=N zF{V#VNa4f9EdN6O)_L&1sZh_z{%@ax{*C<~$%6EMWDfqUiV7cFW7hDeQn>giKaz&O zYd(0QL`C2F4%(V;q0oLDVyt@ITMkc~FiHYu(P>m4&z{dt5(RbuOp4U#>|2n4Ju_m@ zs=#&Diq@wO#ukDRVQVaQZGO0DZ1{OTE*dRLg)2d?mmef=hvq*tS7VBY^ys|o$}8An zw~4L2Mz=Q_sm1kUOiFNH^6zR=dp<YrWRZKpZfteSn2PZ(f%YWuVH~?!piP9805t`2qJIoqU)~5qt=;^Y^se{XQ|v}w-=CK8&1OASw)oKwMV*7lgVLzE4mBd>Mve*u+xvwYTgi>Rwo=>hDyKb+PZT@jl)6ntuI~iI zO>a*J>x*PGE6Skn;DRve zof42F%g=Q>vFza=qeE)BUyN+3z{>wvFw$`KXfir^PDZt4C-g^@?&tb6jzOueTTs~W zsLA#1Za1pob@&7Ix%f@@FIV!i#;R9Q*=YE|jtyq7TXYR@2WO|tu=nAyp_)J`H~h{6 ziRwUd#8}}Pp15-L#RJgbvAsn+I@_|QdjGC5ZR#Y5l6apVMT*bw88zwlg2QHkByzBI z-A1pXIG6p=rNOW2&~vAA+Gu3$B97LW^h2;35O&tW-skzfBnZuC`FuI+YQO%JN?QKg zb6lJgBSX2!h`{;8hT0=Yy^G$tbh4jE>5lZ(m+^@FOuBhBmp@W~mUwOs{OpO6rcAH!;(b^T5Z$b^K_tS?7M)>4>B5*k4 zQquj?Mgpp97yR8eP132!LiZUR4_*rBNZ^dO;y=OHa=|sEo=ONG_AnWv3ZjR+pE)Ss zY^}!Y#d5sxVttkvG^V<}77Y5zo~7uJ^BxuNPQ>sgp>x~z43TyK`gnwUCi4Z#$J~u%B?#7K|6!r;7o5|$ z!L;w5*S}T$lZ44b_Xb=%UlI(_FQu|HSC}`6G@M*k+e3DMA_Dxnu*p-XLugYft5$*?Y)XDmbrMb&OxT(F2GmY$|Epo@rW$cCey;= z;O-)JE^=g`?_4x&wJ!UB4!gI;L~0(0V|cTR2s)UVV)D>~;6wGi`UJ1@FQFSo`sH8y zMtf-a@*%VF@Q?AhXUKLWjRhnGW#8e#tv;d5V|VP#`o=>s{FW%=qUcbN^MN}-A-SYF zS3h^FHMLOZOQ7k(4xj))Mtls(Ma8!x?m}NOHBhO{430+483O zEHX{1=TU{=RqyBNzr4^MXOIu~Gr=3PNqYSvT`s+{i22Pt-QXA2%+Hre!rwd#Rqu{?ywqHjU$4;fNN`$#bufMQi%S*grqH|Xh)pf!x#Cx1`MzhsHL3K$-7iC8eY%3Ce%X?XQ>u=k?TW#{{5SskZpk*>YPYHNwNvWRE zM`*$#4+indz1Ze1I63SARHzP1eHekeyCYOD%*1e+|F)#aW$!ZTig}H%M|T0<1>;Im z#*y+Qp#(l__n4WcTar50t4m9jTZT(CGogcsh|F`mLd-+Zw=tXRdU zc)kZ#;qmuA7lBx_`qcP5E{<(4+{Gri8v=I_8z8zu;@B@(e2U=u;fDt=_G0un*H1pM z5jeOfDvMnjJ~gtG8*#~A*q7_Sejpge=TMSbziL~TVwrd80KPA$@KW|#Fu*%wv(K#Z zQX-#Z;TlSDm=P~jFmCNG%3Y~u&?^6OHy@tZ4MDmsMGx~ngF@fl*1+w~)kSm%k{!s2 zYr?MszKDc(#Z#MJ7b_|RtVP%8GcK?`Jc{VQ3?X-Obv`RuVk(|6@Nshn_e+pl`pSXl zkmsYgP`n286&CQB;JB{9L1TG;XsO!VzvS=UvzRXIfJsQw727qt?$?w*jK_*EQz!qR zltTG@ey+ou#&qKg(}}W2GFy&jcuRWiYk-H1i4u8V{7!a z2957!1jUX?BzMh!(gAVEP`J3Aht@-o@nvS6T z3~_jaSe;)wIK$UoWs_r+tezI@XUa#31vk54cxz4cHLCxDZ^CAg)KEBPTMs)LM%Z>? zdnkPNEdhnP6@!i)P;2Nzq^1(@$FHe0M8enUr@pAKDhR&vl$g4?M@nRGW>MQze$UY1 zH2fBnq-DP6<1;p3(&V90?iy5zu_vt$^}?cGHzF|{*uNtc$1lmYo)alyEES zT&`Za%B1XRzK_nv6h$-Wx1C+G$(z5n&SvS~dqHk&j|`Yfk4ex?t>@@~Zh>om3mdq<#>sHnd%W zlMdPmbg{b-*SOaiF#DNciDYyA?C&Kbc-vKXlJP3*!@S5&@YK6F#rYeG8Cap~wkz8Mm8pH!44HGEvgrZ>3Q{8?H3HHD zghWAllioo@Kx(9SB80Ah^xhJBO{jsC{oc>}?R?- zpqic8WcnEvt3MwvLOsP!hp$;54z&L`Zx^7-NQ>Nn0xzu7nTKJJH7Mt^hL*2 z)4!J80`B(O*jK#Sh-a-X6=GudV~1}-)7rVF#C<5L_4BU>s`JlGM%xd7`}J!#*8QW+ zZDM%gugtirGAlj5ABNYyl_$*Z-Glcsz}@9U7ATbdIxq0fXX z%Y$r5TGYP?W&$n7RdVhZ@^)R29|TJ9ybrS&x4?unK3Vac=~*ah1z~2x0b^Tcj740A zWQ#{-9`i%(dUqGe^^|u{o}RzROB){-@{sc3cP>*W_$}wQUEcmX@1$6RX%|WrVi2^J z`SH8q7+beODQZ_XA94f2yCl9ZUp=x7UgY9%f3wB?b8F{i*mCa1B=9Z1K(Z0TyW81_ z_sU>Rvj-Mwn4u{}@flxe;HIFBD~i{^&Y z68Tn!;{(u9uJT#P+g9ov2`<%cq5CYW#`Z|`+0BDwuYa{S+QYYdquaR=Luwq9h+1&` z>_%q+md{8<#4VCXM=FK4;nti>ek9i|8=jx|;)s(ahAj*0af^yJ zvRR^)`O*(R=2ctAM4=dF_iUeTI1VuCy-sYwdjav@`t-~pYS*$ll^sIf{#Bir$gj#W zG6&F{RZzMXKj%G!!TR#sDqs1iYPAtc>@p<}E>GexByiw3Is)T)o))?^L<_C8XQv&` zD_5VtDR?{^#VNpg$OxY}m&KtYGL_-poz`B?s>u_3m-p@)@;ZZ=YMHNW^79d& zmJmbq8wt!2wsoKN-Q7k*VSx2>sm5 z5 zxSJw2f5iMTm%EA>3eXg>NZJiNHQG5qFfd)d1Q#b%eXCC^HNN5AhbF6lsR0}5JY&cw zD)X44hC*JkOXl}yuZPqJx-IXXSvfkFFLg$RovK_%|2UYo5XDlGRIdLN)eJPB#x*&A zUq@$??S1>qh-s_CjVr@vX`6x97APCDzSrNV`=B~ebEfA$%(EB!eCE$5PbX7fB&*`y z&1+FrpofN6?&kW4P?je6huICLWlv~z>Ar6^%hzWkN8Z*%+{f+5w$j^IEOgCAkq0m; z7dUxp#SnPc?+_fn1wKV(5ED=xOuc*F^^+y5S|ZUBMp{KXKYEZANa&k4Z_!L?y#i;- z5X`d?^UVLv70J}MB7V2*PfWb<^LQd%IiLs7YiaTjM^3=m@eEeTZw7>HO@}m^)ALyG zXNC*8o?iVZEZo9oR{K91{htlqcgbI>$};>kF>&iao#u2crr^yN|4KgYsvVQIs2A4H zJ64SjH-47_?qEB?32(%)_{i9sN@=m(U?Lg~fB(5FWplTqNVX93-L z=2Xl#SJ{=}Zq-+p``v|h_1X0Lt*aOb=Vm3Zl@}J}TIjAF1~r@Y!4kv6L^Bbj820{D<+7j=BoBF2`Z_MW;zOU6sY$Ou8r1G+OtghrjH>Dx~)5twX zLYm3XF{JZwtU_~r{CC~NZl*7ZZk)CY0*9{OZo3YYrFhB&X@k)#j~k>`sNBEIdQ8@T ztn5=Zekpt9=s@#9WHxt9E2p#A|f&s3{#m13w=dBm$8rR18M^o22j17+?6#X<&CXy4gM=x^k$Exnt>O0%`M z0f%DeGFzJg*6$H&$PN?vjb=hICgYF2eoEaIZ4ok%j+z4OeQT0^u!ihpO}ygnoJuw`@@8E6+cH3q>>-pL*}lrGrf41X!Yl(Wj`kj zD|)#+>k_Z*8z8ya5W}k#-2WI%7X|!#6LXWhxY9!9#2OX!=@cdRc=#ij3Bj@i({x73 zQRuPzv+HX_e|KT~rXy)GPiw>6G5ZAr$%*`m=#C@_yHG{zr^@$DdS+kM23YCHwAS=1 z#r_m99!&0#$W2$;vfi(NpQgUbco9CA$rs zPfVv-x8XIzjKiRT9mu1eK*fQqzXTLFjH44=Bel1%BE>+yK9PH*J)Zl^YEHxF6fNW~ z0v_uqomK!8mY5w{Q zaw{54e3^MGc6jDL8t=cjAIm_;b%_hbQiT-4yh+GKry!nm$C>nuty8tBT5ilMRp<9e z=Fa@eKoR4%bbTw2K|XI6#JafU%U}n$>OFNvj>@ckbO7CTUpcTLaqO}a1b`r?QMfxv zpKO-a%d+Vv7}WuvNg0EAaVFZ;vGno3(Qdbm&x)c}brEtI!Vh`b9Q86=OC-(a^1C0p z`3O~}sUoqU7z8tQLQQf4X}@RJb!Njh`Q|0mFSHw-abNPeGuoxUPVLZ->#VnHsir4H zaW|jjvW>iCJMOAtZ&&$GeYK6nU760`T#fMpUjA;`k!-9T*PA@wD?C(@kLj>`Fk_Ha zTDV=A?=EBD`ZvnG}*MoG_Pz5z`Dz0=DC4Vp)y3H^OTv9tF}! z7YoY;e@CLqn(4IIW_*Z$Jswf{hcn6R9?jVT_tc6%<15Bt4g=uwPh0V-tgg}e+}|c; zG5eg1I_{M}*8qwrorcTI;d?i{WPii1IL0Ns34+e!t93kH36t~=9oYFwY6Gqp0=CCv zNG|U|27O9CLNShEbiuc#Y9tuKk>F)_9^C;Bg-4R?VR{|ZheT_SBI1s@>*c;dhF;jcqt<#;+I52+ zNYV#Q$s&*{X1w60^8+!-b-?1pVShM+Duno*S7R80w13ck4`$Z&yNsB5H_2i<5+>~> zl`eau-lXnvAN3HI1hJ=fQ3VNRQD{efW^=;JM5{rzq&Y3|Vkz-k?S1_cK-RSE9%Ot` z0K2`;`JIIdW3sRMg!N zTW6_>YRrgk2)$fhsG7_;%2?ILc{a$D^E5$a`Wn^d6O3V3Y#BMnbNW8yG%%?H%~?+N zh1&v)olM)qP0O#_Db|c3H_4OLv!9y$5gTnEMP{6QFw;4|e^2RQ z0B))cp-XlpX!P#skn~}WE1HQFQlDEvA8ZKWqKA?yQ{c2zvy{Y}AII&Sx@>6+EmwDL3?qG1RKcZZI2tn)nLkp9pxXT#`CH65`{X=o>Nmdo zm5Gd3)t~=Y<%IdME0nL%`w@0*G9hCy72}T4DIXvS{Irk@dv3^0jJG z+@0*Z2Q6xTL=<5k(+%cUVaLWQc6vD}a|FBYx{B8p(>(ucsSU~H$dHAgL5%RHicu=} z?6D6jHh|Gs?ceA1HI*}Onf|iuK+<7TX@TPWH*0?6RJQrFQEu*DS@(S6EI?USl0Pio zOLH%=q7LTDDto(nh-z~s^ZyHdmV|!_022lZqn9-X=7$>rST&ZcP|P9|BKD0?wAb@DQv=rSBIsn_c_-HCg-Hhu$9x zDcv6Yk_q2)2@XQ=={0^^DoY3?;zcos7M&ZAHoe*Fbv{AKL2$xdh#}Z`Hm4<871LRn z`T2hLAN@@qo%|F8eP2-}1Kvz+Z|ts-Bw^4~i}nc>S1g|+$$)jk5MFc$7ZNiqvlm$_jF-%|to?qh)xX5A2C(CG4KcPv0sO4@2$|hgG|2Kr zN-#rg@z4FT_+%t&kQfkTC5K?bH-yL?TqoWZ(iby`yl?vSY$X!;0};<3-~@1PMn zaA#*Ri+VHzPnZdFF-~sBjSHwjX}(k0nHDxjvwwU4=B06Wu=~XT`2({sD1?p0?e1or z8xan04izMA;x2U<%^?4{_JHw?0;)v2!}#Br)z2pyy@puu?o{so%rr)h!Jlld|813e zoTM>&LMKt2%bIhrs3o=#2PKgnG zui1b&UZ%=k3F~{J)gAIjg)oV z6SvRvnhftmJRp1FeVYihr_%(c_|I@dg-<{HStKgDf4a-DN51S$emK1Yu_p6UqSHEU z?nUS8A z<;s2=RslCOM9HI-o~Igp_B1=V6KUe&LG^%?*l^b6c*Baau{uLoRYkMqMG>>M=kjN# z9^}fv$4pA!+_Z1=p<2d-(Q4rLQsH^ba1&e}BlG~L(|QH>`tAKO<5_rEtf7`zU5KP1 z!4E}?dG2bZ@S)HkPkv0_&vXi}*xjh?woA<1`4wOqN$BmoP@z7^!U|WE>tEqB@qI;) zetMR*)_YcVx;QlB{(i79eRw9}iuAr2`voX!qS&IIX)eXHMXS24+&{ys`A5J(r`b3J zbGUV=|I5>CoSqEeJ;6!e6RD#R`W2E{8q3e1lCk&E(i`BE063Rml~p|nuqGNc_ky&z z|J_m(+?l)ss=4`nHoHt>tRz%7r+3|UvXOaa1MByxl@3493*eHI`E|9Q^xNu6A2}Bu z4hy^`FF?P=y^87rB9ou-j5jPxdKXn*fOvN-%%Tvgu(BTNL%eI&oU?SzwqoMIcX1D` zK0YP2iPOAY6GGsxOl0R4SruApIlHYKglVM)ia$4sIB$1r6WfE;T(W4_IuU=ko+5G+ z8t@tya@Le*nd?Jv?3vZ-MbGkJ?&PwB>}}{etwe3hpL%&&xndd?!6(X@;02x2G>99|7Uc2*N|0KS>y zWjx}L`r_PhVQChvx)LMrGTm4%(^`O<_kF9xCclmFhp~16x6w^C65bF8p$!-tpG*V@u`~)3=q+6+S3%t~RL8MUkwMBAi#}Q{pwGvsn{a)i^@=<5(>ociMfb&H%7V4h%d&B~;l!4yMJk)W_*=cl z*auuUjLaHw*U>6iGGs~y&Sbtno`?1Q>mo127T}tl=K4@TOceem^IYJRGVU-&rKN<) zIi_xJi+^caG1w;W1V0eTvz;<{=We~2-F6cK5H+s zvriAOOYawj2Q!hie-e|huvQ(czUGsb1%v&2A0j?%N8!F6qn7LwUVW>2y;))D>@U!h zoRs}GH+*Y9r^I}bSYDVeD^C6ABkt0(JskVR(*ljvEz_T8+T);s_NU=_8qC-_0 zg&6?>WT;lRHn_0Rl41b;GHm;y@)a!? zACmqIbT$3mC^x%n?^XGrdd(!`2D_-*6RkgomgznWpMlmPHN2tCO8O`5n$mC~EXCfR z&-+YJ!{?I6(rEFuChPBc7OQf9x#g@{qf^dM0|zmAH5}be?XoUQJYYu%izU)MQf*v3 z@!zN|%QvReg6BNGYCBU0i)@a`Kb1mtUq>vm3k;C!AA5M8FPERFt6U-(!lHW@r5cH< zBn_DGV^|;+MJdS*>Jbba|0_^)=T^sinAfS8GY$QUNV{ToqCK<;| zYo-4?cjb%(sC4QZP49pDBkaWa^p2iMs-9bp6COb22j?mO5DTziS{Fai4Epw-c;#`% z)O)mhoPx#$2QR1)VT1q@shRNB4IjNxHzG27uq&(ePK~#^{H;m2mKwLk&JI%UxxCWpYsfJ?_d`(f`p34?Uj)7Fp*?k0+>(6}oe5 zSpqTqwWGWbcBV#~CgKX4nEHgTOo4Pykip7A1>3BPI&x9doUh&jekzEXUlVK|`uv&? zTmnNW)!iyt{{089jWzvIbI=x@>~3LR*YY!Zy7K%gQx!v;%Be4~5a8x+>Dp=$gzM9K z_u5kaT$aR4cBC```xiDFz(rNFf#Csj5N*Urk+(0lB?={l8P-L88$;jG;E0Ak!|Wsu zdd>K87d;j+tqeqQhEbis-thGAW#1AKn5;T3{~t}vWr-(Uxev$JTH9*<;&)HmZ7&H> z*VlUx#va*@QFz0-r4DqRg~g6?@2A$Mft7GkbRAQPv%(;^KZ~Zhabu@+TQY+6J4+=rBe}%QU^6@qzEJ zx0Sq3fMh!uKrBm(+fJ0<>_@TQ7e_0vD*iylBfy9eFf-CYjAy}2fAl>^*Tt>`dtqU= zQN_Xp=5p1+zt-KJTEg}Hn-i$WSZ-@SIk%A}K+x|{qh2ARmJcvYCO}r5=xPH2(#25l zW5Kd<8viuW?q*xgZ`q%FEqrCakgo20F34J`E?^%J(NAS=PQi`)+$f$%@q{Qk6AjiXb;Qg ze$pykZl|w+I9nJitO+DEm{bfzUY?RoNiVD#cZ#}R=GKT4IX88WNar*C*QWP6y0Vd# zG9tTP0}kc<>={(1QcWq43HqybgqqrZ4Qm%Q|p{G5R zwBrfuIb5;roBdTn!nneVxF$ZI9{}8e$zsLsYPM@d{8&lPI^bx=plL=`?FvH(Z8W{>)Z|FNMLSO7n8l21^rcMQ1LK(YILK(v`}fxqrM)jvo0_w z+7@eucxr`{KZ)e$lK|v|Fz$_uUz(le%r59Mf!=_DOLNmxgpEj+`bQKo3E*9ko^e4h zxRyaeC5A?K{i&>GSY#Tbm-P*CZ4PH_$gRYe(Qdn|h_IGN`x9>rP0nX2$w;TX=)9V# zZgljO6%mX%^}bdqL_6(~rN)OrhkMOgzdcV01HTlsF+RO@K^egDWF_{NlM#fey;lUW zPPrHC3#O1AnA5tG@CP zw%!Ld1LBXWrvz3L?blT@_a5*4D*r(@t;h)YpFGDZbiX`t%;(_{NCMs8sL(d=*n-Hr z{!_)k4i;6()BSq|47&|YeXGgeR-B_{m}dY7?Fv0fJk~ zvOOU@)aTZl#td81zp|EYlAqZa2`qW($=ygJm{xS>cz(rwL zj^H3`5d{b)D|x^*z)R%l+*)yc<2)uo&AW5MbtLsRO~IF5FlP2UP@mgdSajeaU5fFx zP~R~qBj?~{-6e6O82bsPrjhU>0#lX=|p@@(&)&Du|>w<)l zMiVQ|jU{j|VEZRv-&WtE)@~h9ZXG7GZ?&8`oZOuF$g3NfSG)HvNI=gvKRZZ={oTE} z7T(G71l=#60}}of)`(2Fbe>K>cLPYKVSec~N#r^y?zr}n=vDlY=E=rz(~(7+8+yuy z59r%XL1eK*wdbO!Vwy_F?qGqhi|4%zYq|RV=|I?~Ho#xxUFTH{x%}y4nru93(5A*L z7&uMw|6_m+!dncgn>0}JT6yeT@9Bx5Z;Q;blJ@utJK_(|$R*GN3#qS^RlL)E9A+<_1IflqZn zKWeOIxj4HP&b#5mBwfoIxD0`JviozO+D)}Jz0wj61XAIxRC$n_)G zIOpRHexBxAtn2BRK3b5C6FYY%Fn>1Fo;rCAH}QNgtfTkwMMK8A67|4^g6eo#koL+3 z*whtHsiKqYo#b}kwOh%eT)|K!qI>TL$-aEOxOTsRa!eR6s z{DBQ2s5b&GfCEOiifN~s%#8M zFqGlQL4IxO%Gcbkh2JW-gFlBqIg?qAKd{RLl7xRc?#dGK4B82D-2YA)f3KP2VHaP1#+~^!rN|qLiz#JAtnPqemnUSrT7cZTNjt@tc^PnEMw^ z!uLS}T za*JI$R)?sWjTIzjI2y?Upgc^(PdFzPxrUl zR7N8DG-8U%wvA?!s8HeiUif>K81b-|X{$l>t5z#+eSXgHN${#q5mU{?+;Z{m%u3*b zo%WcDtv$|*rmyL?zpa+lUBk4)N`@XAW}*T5W+9-zlNIdS#w1tF>-FxMeTt*&Ilz`Q z^$&`D0aDcITKVvYpzwB}cnVecD1N!jOdj!QE^d-1W9U;Dx z?|$H^v>w#E^ETdJyd}cx%=7z|o%6{AWwoI~@GJ=%S4Lpy3b3ziD$y%-;dX9OWR^$I z%svqQ;`W)*lf&JDcmNiKz$cBS7j_ZZ02u(@Jt7&vL{_@Pl5i1l78FrdtD$;av+C+M zp0L9LtwWnf1G>ObYa4=smREr&A>c`j=kLZ1(~@24+s3~|{2IQVAzP+#4-$OG}p1!eZ6Kq-HTy@cTv5dbxELK2-o*ARb4HkI3RinNL}R2#wz znZ&_BA|1w^wA9`56_uwZz5oO>tpMYkE)YA?85)bwV?frZ%PsOJ*hi^$*MFk1kwLa( zCa(p(7_LP-7|!mTdQp@+*%GJ+&~5dUK5Bpa)2>Kx!!00dx(WgMhj$ z-XyXRz-Dd07n&DeWF7drDKJ*2=&z(*!uKz$$@C<{m2T4pk^Gio@?A>EN}PEeIxe6! zScXQ=^}6-&zM@-Ys$mESZ&0jV=?WkN-xRF}d7Rt?O}5S+PGxXpB=`V~Bi$x^xQYxR z-1fdPTp;@q*{a$7R<*1ap9eI))16BgR3Y=MUze`}tAeB)Q4aY13u)1*!#}Ba$Hwy2 z&P>)0;se~u@M&1Vc4oX^oV>NyKf#N1$G=MoGZ(0XAF{sq2T~!JE3>U?%(C6= zuU;QY|0u+*P7N#y5l|6i9qbfAe>L`I+4^PrJM(ehkLS&sle)#`zbBxv5PG=fC|ry- z7OqnaF?X`LoBYkH`P|5=?`!=HE612z4R>OuNc=J=c=h$a&cY?7_7mtynTRHViKpGS zV?&G8JH2|Ohbxdq$e$sGBD*=u5&&Wr9~f$^dIzgZ^(16b{}m(a{f`X_cu{CGaHu$c z@%Lk>DgA;c6whX=WpQ)c1 zkLkB%X^bwXs*Bg3`fk2v6oZE(n2O7F*SE#J&C*^eqr6EYrS(xY3aKYZS^Uw<=sk2j z?=6e^F~t}O7P?&v0u5@<2F+MT=%b9L;r|+$bN{bwhfOtCZQx1#0jJQFo!Ti?_Z7Xr zn;0awTJcfAic@NkTrs)!c7F@?qGC(jjqQ$cX~q_$Yq~;AcjE#YPGwYO5jN)WTL|7L z47x^Ag45$sy;-ilOlDmi7WULgxwqP`30`Y|6b06%rl-)D3~LpH;*9U4wWn>hK@`}0^ zVYbk=#C!4TNqzeCyckOpv7fK(@P@M>@?Tvut%;>7p^Z~5%t6%IBUHL=Q^`UA3lm8zhnSYTq2(awGf$|J#4`wDi1HK0E=aVWrK7}?!&&LH( zqYU0(3|Id+7%oa%XIFu|r=}C2COfP=SwHG^iSw8G*zs_!u6ViMA7GM}fmbI;^TYw~ zEd4VTt<#T0rWN!oYv*5>RChqdewr)vLzq)2pXqc zuD{2m;X67jJKi+_@_beUKVP~R3$sCnwY@J>D$9QJAzQ@wZ@B9DQhKqAU!EoCzB33& zHHb_NA0kL~NT~0=adQmQOHo@wEV-%f{6(-(=c&TPLITJDZ&QUII>Pu`L@Q$g+s(V| zUp5~3VK^_<PYq$34)G zO^e=GNtE}w_gzBitjr}jPnpE{CLTWJ_^iwWz=-8K(Vz4TW@m^W?&8tXIsPM&TIll3 zW>%O+G)`TtfJRZEgx8HUEq|VBi8TOUV!Xp0Wz`56NzC=Pxt}vkAK5Gzrjh@rt{Nk% zL$RDbQamt>Il(65t=YiO1k(lUKml#8EJp)Y`yf)FW3l=4+_bZ)2cScKmY%b;{3ri@ zm}n0R3&&R@b3#J|EKV?o8!?=CYis=?)2Og7C*Fei@0XdaMe#ULPRg5vv@vgy_|aAd z!;s$)rST0vk6{-=&5Y%x&(>q)-e;~geNR$gV=|?q_xic>&Qzsn&7Ca$1$mKI)Y8k^#>CG zc>EIbB&c6a05GaSv#W6ZfU6M}vwfIA#&k{UuCVVW$*GDUk8!|5p%z3GcHiC0-yYev z0AxAnDS>b4ZKk$u>`=gyZtf<~{!dix3W&9aFv?QE_FOpi1i9lyW6_bN*5gPFEtR!c&i51vq*_Hu~!$quvQB8msoOi@ura$5TgqQ60dqQ@;8z zJ=@*BP;rWMDMSpd%fE|_=V^bj@o}MS%QB;Np(JdBePv@_$5Jtjo84G9hK(a9%TF>< zzXkM={EiZdpd))uAXkJYL-#+SltUAb3}913bH9!Ryc2ZJIMq(d@am^3M0t|3wH_AD z$g}6zO&=GHgl~2WB>jk!(|FqGw@RAYjPHKm=}+J1Z-)6jIF$ws>Xp}hdEPX+5e&DY zG`70q|D);Uu;Cm*a4l|cImRz3X693R`sSjJih$NJf^0X=X*mPG)8eeDwqvcWwX$lq z$z>MOWFvCPkjL_oUgm@2(f?@VJcAs9;u}=-@s2A8djiW$!W-DikN9CEly_N-(_LKT zjSR~a3Eg$`DfQv`7zTpZXa1xHn!-&=o#fbA)z#lCsBL*vZa==nzVGXd^e+oY?(?bBNJ_RG^X#1|^?1v1 z`>`eUl-0;@G^w}k?gDk}CmT2QyjT5RoVd-h#w9~*#%v|rKoEyLTR&5+nT%YRC@zNg z^aaO-SvVXO&#PzB(R#m8W-TX5Zzn{bh~)|| z;a?cW#2L;Y7`Oi^QWEp@IH7b0wS3!DSgHke>H+RH`E@leggd!CZ(d;+egQ=-{|Q{L z^ReX3Q?6WQ&eCyXQ{7oh%gveC2PD0s+N#5~Vlu1PvT9tVyAPA2RdemoTCGfHlxlRj zWgp~+{F%b1l^li+1p62nv=aTQcJ#RM^NWAm*pMa%5XBy~`#4x)j<~A!k51(opP->q zIXj-3S;XaVy?7Q(4NdyZ1L7rYlQm*Xa7xn5SxD&a7w{}fL^`Ls6eK+wy9zt&i4XS$ zaggas;cDai?`mr%5(NC;zA#s4{GfU8L6j(s@6{kaz@O<7JyrsvqoehezJD2%=2=a2 zR%~H^H8(yL)|lDqDUv9(-*mK8Ir(!#ACgs4KrmZA_=He~y&?YdGb%*%Kk)vy9#t!k1qH+dK; zFSe9|u0ixl=)Oo!ILPCt%0ZW|%aNG$I@@n%b%}jY$#-`sK70D1VC}`cS&v2d9$-r9 z##x{D+2XU1zuo=$O8`t6RJPS5uq7;GLU!duec;8S>Z6r{iXc0sYC)}B{%iMRfV7j} z__p>Yp5sSdy9v>_vj%HZpJ&fAR+%f{UWArYFML`r@wky}>!aFm`Z5%IsLizy`-?z+ zwe_Z^fAt*GyE3tM2Uy9t9K)6-p!y#TW|H}<^J%6=ON}~|*F%I9MFaX;IXYnZZzG3< zGjC!-@X*KX0B_XiE?k)*i#QNpaq?u|N9`RENC6|V0$Mw-3YgHmH9KWAV$7}($?ea< zOed`15m%P^hqy&pvLqS>xnxR(9;j%kcDmWu89&?W1&O*)^qA63v8|fS;@#sfVjnjy zkQbKn)PblSX;+EiL=@OPFOtww(a`B?GH7^E-o;!wy|XX%v0ZoqAwgE5P7^b}OC&)V z1ZAdm+wKp|Kei=5Yez*AMJ{2|MeXp@-Nx{Ne#=QxiXn?~Bo1!KdC0f8qBZVq)$I27P z=GdFE5l$nW6TvaIWeu}I)5e%X8||}$P&>+#*E45VZ(Vm+AM_88m9QTl-Jkk1UmYIr z`$WO?TcyZ$x|KZi3>j&ppC^wPhSbCZsjV*DdmCZ<>)Ej2e-ky5hzg1SfHF`XgtOq| zyh!D1OQCh^nNRe_r}r3KeJ;4q-{XL)Vi&8_I$2fIP>Aj;eeI1K7!F^e(v9F{dYs0d zQ>U~9*3Gk zVx}rVj9_}p92gK2S-O$qBT}2OT_Zyn0 zn_oM*4Cjc0-ylB+D8{@cXpA=m#MV_UxZ8S(WL(uc+^7QrgC#h(E-FIfqRL#aGJbsc zeL@Ek=C8H6yqx;7qI{JtM>PhTPhFk+QoLZM|`q+_Oq<2Z^s7V z)0LjxS;#d(VllFb=*eb(QVRztSjMB}1rBUn0l|SS)zyMrkSwx#vyEWGPDnaUCl)Nn z-)abJeXznXcN}qDiqY^c_^j^~H7bL&@6P!AV4eLX+ucNTYVgLX+yQ%27t!#vfb!kP zRd=y-=NIej^t_Ciz87PZmVswydo%G9u)&$fbIf;7O~`rl{I4dbzx!HWXw?$?rsMQ; z5It`5ZFP*6TAe94Lg$J&wUhHWWLIPP4sR7_cwNGnZg8Rg^vUp*-!5|J{L@zxW$TiCP^n-i_ZjF4 zq<8q%(^BHeK`M1p>fs_(r?oyhXNFfkh-#8MG2n5lXJkP@=-NYH$H80F4x3B(!SYNH zS*Urjq-X(I9_GyIOi@e8`Ht*RM$niGAE}{K8U?u|Z}n6zbUrkj7$*d>YYa~t$N0AZ zAm+=E`r;WdJ(Y(jy8`~q9IOI%5UI{n^T<%=YVf)3(T7Th2a&D~AtzEQgO!Bxa zD{V=lEt~qP3cOqN_`+=CTq}|*3=)HiD%#(6%Uv2(7I}7C$5&N$rFi#z85w%ZN`1La z#Zu>f$hx*)J95dkxs?Y;yLXAO0bpOz8hF$vH|`$M;IQc-VYQZVGhZVWMK*_|itI_F z(bXLTu>{`uP_$EgtS1qr_ZM!v(qFqaA;c0(_`;D}9Cg78@Wo5v?cxFrac_>?1i*s$ z`YA{;`<6rU&sOQE;;4brBWowBuLFlqlCd~ho|1{+B&!evx!Y5|`lp$0U!FJUo>N0x z92>?i(X?~J18QnRu-9|P`it+~sqR`=jP{icZqurRw*un}{u)sSo3W*+>f>FgAv3>$ zNj}~bB;=rYx5dh6kg#lQDrUtNxk-f1X7<&m99oMbLSeT`J)MpbUlDe@%GF}d`~ zMe>~a8n0LEFPsbRfvRJZ&m(-M(Qd#7z!u=eI+o~Lwch3ORX>ol%9th(Hu|AZb*WCH zuS7)npc8+NxEqPB){ee|&K*z9L2|%g(0m0MsX(xR<<7XLvZgm6FP*SAtw=GO6T!OC z+GF=_R7p;}QR*#3_@q0+GSgwpmS=XQY!9e}KS%%3L;^h_S(c#WS|<@Ox2IT7`$&n@ z-{;nd;vkLzxpOFtNbM+<&q;boU+_lMAYF3NJo5_w#7V1SOmXG}X00hy&p7lynm@1Z zE@v0Cs9Duh3Xss2cvk1c?SQKxb~N|&WUAixtr8$E+tf?r2pO2^z*ui))Ni5wo3=O9 zv~Vc)3lX-lfoi3ZZhO}Cw8}}P2fE*rUNJ7+rVc=uRGxmH*;JgYVDxoft4+9t5}As^ z9=lJ^EpG(NTS_1?lWAf;j(0uQb4hJ8nbn}-fAO8?E09?-4YiJAP8q}n0KEnGs6C_<*S0DCGvy}txK1=b>PfP{)=Z99 zDg%qjkk$eU+B$`F2hFHSHSGMDCT7h&il?*YxXK*T-`SKX1a`vsOQz! zy=z*`l5XDi=7F2%BW_%E3^`p%>-^eh6))D3t2ZiO@+;1{v59ZP)lMGjWaIrSpKw_- zHAilI%D);68$<+>-6)A_;ya6K)x-k4K(~O_WJNOFy1uR_h2|O#{DCS_Y4tET>`o7+Ma{i>YZmVk?CwT@nSqdxr6z0cW>kMJ$ zJhW^+Qo0wKCW$iX5u$wlkH#6q32V@+CoT{k@~LA8M}qZJvW5>ds5J51q7vI)HnAi_ zL>G5>7ZZavGW6n`Wqs)7IdyyQ)kqe@rK3lGm;xr?M*RXAE4lRX5;trvgvx8l46k(# z8$`;Uz)Q`XHT4;eX}8rm%m0W4qi5?YEp$Rm-}|#=dy}0l;2&t{5=X9-G=%Dqdr6H zFBej0J>K5U*yFA(DL@(%F+$#C0QLCf#&$c7laeo!Fi0bDEsM6cbXWRP!(PTgqoMx)NQb)ko zsNnCjQk|%XTSY$xOmDGZb3nCWbkC{`iA)H@HW+UJnd31cqNKVf0b_k@Xg@f|wbbBH zcE97szfA7;wL(b+Ip~TYVLfGYx$TkOG5Db68gLc&xLpVb4db&`()QYH{XA>|^W8hK zSUxq4d-e^{toywnn?ir2%aZ(>Gm_xRkC*O=MF2sbsbzGy` zTj$+1ig($l$as^_tKQjB>77VA;q}kSQX_r2r49C&%(h4a-CFLPZvDfhSh zGE{?!I8trQvn8pTLY%A8sA-!Y z=K+>^R}mw~>a^~hKx}0e=^5hB;@$Xv3Ekz-X1965S-L%L$L3cL3?OW{__W{O{A@zK zP5lk21xFxcogjQ*7c{5&c5`^B%JA->a)-L0>)jsn$;ab2iNMGvlvm!+wcyO%Yr+S& zdpc!zthsV&{&%lZ>1|0fw}7aN2k-rphw?gCK1;@Ug>;(|?qfeJ_5MQ1JIhw;%|H5Z znZ?|sWBp2_WA4e{0x#P9^Akea=}St!2r(;=kaucNj9BEGkY^UR-tsfMt#O5OT=zvJfv11z?xpK(tGoVRrrTC5kz!`DSAsW9QPu-nA2#=L z1E&tPB8}Sb$sUWNDDwqRzMVWS9l-I_Kt6pB2<@{9T2m@>@j8R%3&;#K$0vLJ^ENS( zgOjUYwd{4fPN#Yk-f&lm^qA~G$)SqEO$lbPt`)56gyij0SEgSn^AcU70=q_svi7O*rW!C% zeur;&aLB|B_56`kI6i1@!l0R1+nfq^6WRkEU1N&k*WzL;LHM$~aQ5 zS#xf)d%?{VZZge2{EtR3!F$$BKhmG%LLJysxs!^#Emu|+nSMWF0k6mR)zKB^xYvtk zI4vcf*#XG`%j<=1xi^~|{C#*7TkZrqAEo~ZciUpMJ=gTuX6D@NKRipd%eRy+8l7B3 zvbQ6^?6@!&CNFRJsLdhi_ZD%VH2yG#XWv5i!GH~x+S%rV6NVLGly6Xg;#rI zGtyI?h6Hnk3yvJWr-r8E?$r!hFj2(T`SS-}ho1M2W&Vx!RkNZ%<7{vEiMrIw+Ds2# z74I8;V2!CmI9d_?PLGJP*ab~UxJ5i!*y7H&QJMdbv;Pcgvi-tGQIuB^5s==A2!c`t z=_L_SX#y%G^eDX}AP^uB8y!JFdXwIXbZLq74pKw!MS4OFki`A`_W#p4b7t?E^Ch2{ zNw|~eUTa3}8sPKi)RO?L-~ zn-H(f>JM&U`Tg~5(|6_`;}32xSk|U_K*Gv$^4nr1wdo>#OU>L8cK_ISf$ly*A?6RP z|9mzL`?X(&W#OANnOQ<6@<3_GuTZA%{|^=@`9| z(dVP*GLVqrQZ(JY0Wft4&9@)j(m$+6(tJ-)hNzSN;LXAKbJyYAUQM+oe&qb@Pvg_O?}km`d`?Irr;FD|{cP1YV&Yc}$)j1Z z*uPmdUFF%1l8%ya&rb4Cj$GVaJ zM|0JnWXhw5Duk^Fa*DzJF<6mUMA9ZqUmBCgF3!Tr(6qxi9pWQ*#ve=zTAJVekcWfQ zh_XPAnDTe9YSvo(Y-?jyI6}wyQo#bAWca5rPUFD!06qMx^4#jFd!iZ@>J)0J}WD(=>y zxp|2N=+&PhgZ}taefoj3%%c0mx-ex@zT^0c3-bW#&~N{iA8Si%p2i)z`*B&~BZeKU zpqU#qmdO|Ye56*%EM@dy?}1$$Z2xt!z<_KQhwt8BsjC-8i*1W^#rY|YiZ^k58@H*R!o+|ek_t2nDFqM>)3cEW!Bmq#pbOly z-{dp&*QM6ryUu&T(}wKgELAsPlO<{P&nn7>m`>A4xxlFEkaj?~I0FX{x5YUmjy;pC zMM_qzr+lu7lkME9U%yB_w@fvXzA5}+SD9(aoel9EPmB3Nq|etW+dfl`GMe0Je121^ z8^@A>a!{-f@s2E~vaEAfdD1(e-?rxV6A!iDb0?^WXi`V;Er3TF5cQ-;KE`HwJ)PqM^ydPDu&P&x1fn6BrU`)>oz=~4OF?=VU{*aQ!b6J zmC0Wj;@z{E$>ls&hc05 zlS+Gb95p|mnOU>sEt!LvcKwjwQZ=7<=5+D&B=*5zcEg#kXmkF6zEFve6D(Mmk2($vI;WgoQjgj5QXB5mY zul)ahVaX~^cT5VECk>eqB4 zge*39SALRYHu0u=FUy*{BoE(9W4e>mm|cU(AVGpJo~u<+XVj7RK1S+JBlIdlleH(E zzU7MoapwRo^}t%eADDso4~K8NRpq}n%^M3!QpPMpcFpiHI(WBa^4+mJqtO{bNphTR z^VEXLPnKJs={HG4lWP`d1qM>Kuoj$;wHH`>E2f@+jhsMC~STuFPsR`3?`{P)jKW z0Hp0H<7trqxwA(bfmJcDSF)Iwv`HU>+EJ{B+(8M_a{f`FXEQwG)k1uh(^Zgz{6cZg zfxFmya>(a;wT0pZaq#*s28j#sSHx`B&GIH|-V6~%Br5?;@RMs4%;|yimD{wD6aMz! z8@i{{hL}80(JkTNzW5${x4U58<`{Obm27Beg*SMx0S-o#=>69!M1Usgg;v(Njv>9| zaxJsO*Jtl5>)nYK7;*RQ?Sb8Wv5L)qJ??@qFxxH8U7*hTR=~CtWSB3`+jVIcAawQ! zP*=@o4&uDD@U$Vps|F2KzaI78(!1@@SB;5VYv4`9zJai;miA5M&Az^&6ltdM z(CZjAafIgT9&ddsp|iy{Hn5f(_Qhi8Q`>N7(SNbP8)4-f}mK2#0PM!p$V1sX2Rp9hF^}8U?ac@n3Gq{Z0A;dGfPi^RS3EG+gv|Tp%Z5 zvxJnX7Bl**1a}I~_+He4NQtV9FlAB|EQv2|%~?=dRZ5+-O!qiboS62OV5i|j??urc5AY&6&q#k_$a$- zl=uSAUlESD99DG~0_97bx<@is4AVP_J{rD|P7g{r*SjcBX)t+(^peo zGm)lMgX}$C1)cpVjm(B)`*`g>`VE)75@#HAMV4Y3zE!?+am_!7tO*Xx1fjoZwu(3b z5Qp#xXZP0=cJv@AGVuO)Z)baUkP$P|YEui`>t$9~Xi$(Y?pd`JBoZ8fw07e5oUV_j zJTB%NQ`T0gYW6ogPJz4!{*wfIa>WMdXqhyS5LS4vSQ^cVA4t^w^OvomdtQZB^_L@=*PicFM~)8_@{PE=KhV>`H}+51 z9iV92enyj=cWjv(HG;U%h*eDVfFo8)DJuQxEYK=BuU2x)C9C#c3X)%>!joC=00Twj zM+be?7B7(gI>R|<*k7>H4GP>mo(_Jl2$ca&!pW%!(~uhIL!-*}1YcwJ+MN!TpyI(G zef-&Mgx@SJiw-7!G;Y?wf1Ix$d=x>4&lezZd>1J=wq4wFeNN0lzJ=uuJ!GHN9R8vF zS}=A+?prr+f{#s?#-YvXF-p;o*Imx(=Xdmr34`^yIQm=gl6}4m)+3>;)Vq*l;c~fP zqQPB;f^dHuh1FgpuA=8%o$CN*dcNhVae^!TO9E&a!#d*xtxrvenhDGpFncl(Y}~j? zwLx?a!2{r?w#TZN>6p%#xTTUG4Xg2@c=wt3O!FCdc4v=i}&Xb zg$IgZjQ&wP^MoYWs|yW1PX#ui`_-Wgh$SH!yfg2~36X7-W>lENbcV%+KBqe_y>mR#s}tMZ5EMDz(@ zgnexpD|P@N(RIg{O@bLziB)Dj@-Y2~3(=U6N5aOzir-VuxeY}MM%EQa;q5Q+J_U)5 zK#bHU>)Nk1AFRP;4~BE#+Z;J+%NDBbQE@-xs3sdKo9`tnj=d`&ua-pLrSY;kpYXHiz9|C)P_T;^?=|7(q+Gv`k=Bk1ibP70=NYa!%TpHP|;f^dwAU*=;j zH>%%^C>xdez&&wsL6>IfF_(W0#+IWdzt`kpdlQ6fCI_%ET6oxORr~Tzfgja?=`E%U zLo+>ULWHzYWIOho!uGAFHxG*2&eyeEhZvnVtZ&)MWV->UQ1`G&+PQ&i8c?XJ2xsHY zq9zvy(w?+%^!|>Dx0DfQAFxGL`ulP9bLf=vqHyl*VBxRcr5Q#uW+DN}cj7#p9oy?5LgVZsS<&e`tTE5&_2JdJ(OZ+vQebmAXSK_EWL!ZY7 zu4`b=uVEPhBCTyIu`d}d$X1shg6odVdzHbtgn0+ehv5!_ zi7?($*QRF;pX6dGnZi8P5U-b@_YD0p)#)f2ANdHe31`QLgo zP?6zWJI=J8Ex1{gn~}X{w*0T0aE(~}-Y6Q3xxP_}$m}F_tD$tZJcBWz$~y1E&J<-< z7~iQqc@8-!`H0|OF=$DYM=1F=aWMK>I}#o8+Z4uO4VtKUks1Bk3eg1?eBPgb6nXHV z4M&P4DIu0D`VeA}!FAl=mcsV$H$k;K=$k`MLW8 z$;kmA&J=NYN9pE0#^*OD3+QtntdP%m3tJ-c1iSZC%(|wW*9TXXUhj~bJK8~`dTt%01sV)`|l;lOch65t}HlgVn z=c0)&U#&Fcv9Or3(CRO$X`4T8=`kx@vSdHhhtl7EX{P!}k1_6N(zUh(WzgzI@-x=R zJ1Uy?kEwQaliGviKRx|q!RdL>IvqlZ*SFMPy0u(k`z)E{mdX#KBCJRMtugV4F6)6D z^XpH;p2%*&-zlpK-`d0;hb5sOuEjimhsQc`v%P?&ibbOmCglM#c?1)>ss?bBpe2fc? znr2xZ5qjev;?N4v?!Lk$mz0<5TH-IGv0=fx;X*i2bj4LI>1+yqE=vOeLbIUI4I8g^4t`RQKVsn~ z;X@eD@ux?#15vRT*w$5q@(_3WgrK*mxvNJO?h{di;e2w&s*Xx{^ao_9WCl*PVtedn zH=12zuYaU@m-Q4RzTKAjnLG{t~G@dDup5+Uo{NP*GRXx>`LlgQ1*k)pa(0!J}JuWe*$}MD*VXd zWIRVS&o8%@9o3)Ij6lpB*>P~;#f6FKW^d*rf)1`8MmWia12MTs1^@xMnZd|&IJKb1 zEMF zwd>MqI<^C^Vm^&63>{n=&t^_ItHg!|vlkTKaje0;x3KnM#rAYw)fQ`SvRPIsxB z{3a)y8l$gwmdu5lyER%{6BO`9PrO{6zT8?Hl6>8Y(_RTb;{_g$QO#VxV@c+#Lbz!&y}3 zs{qlj4H*3Pu_p0eP$e?EDt?M73VK~=W>utdLdNDk>~$L4%w)P=q-nw|Ulu~Oy&G(i z5WY|Ar*}p$h-@H z50U6Nf`!J<4@wN4eO!`YFuj)eu;TY&-bpdl7vhuAN77miKxA%Rh*bPGV>YtD{sL~xQ@xavC0dW3@PJRNc>zeG1TuKtzxk7%%V!)EK&ZU|hTlvT>rZS8((1S95&71y4&Cy>7DtFRe*6|k=WkuT)sh@dw3!~gWTrd36toC8> zYVq0I7fEgCyK|6{gm1h)zY6t5N+!yTf-$?a-U+YDQ<#0kg*}$%4b;hbAlG)8p2O`l zX?0-{Oo;oY!I9O2ke+r=kqrnNvK0ccMS%!ymtE*bI5msy#=K0|@z{lVRqiTZ*I11b z8YD}Af~+7Krl6Hp+q-675Qri&nVm|HZD=>aC?w;A=sup%G&~me>ha^y09@~1IVMd` zZe6QUeG~qQ0ZMrF{11fB;yfB$2OcVI3BDo1j#ad5P`LlCZt*PGT5}o3aNELFl{c-+ zd6W01H*46mfDYT2lam1D@lcD9@IKh~Y2ZLU@%Y~h_I(UMcKDjsXPCx*5={)Azs->X$ zw}#2mHi1*XWHboyA^`Iw&>q4RuIu7c&+dwn1D7-LH== zSdurJM*#0-^O)Zd=C`+svpvGz_(f4s z^nAVm;%)uX0Yf%Sc1~yaKv&Z8S*NVw`w?HswHQUd80<``T>D~#Q*f55)$h|x{w!ip zivuArB_C{NVftYRW?ub6l}nm$3GF&F^POa zI{RMZ9YQn$!$o8kGpD*BR@TPO(iuJOQHrWtth%zP$Bq9eG^@Ck+SkYL55qh8JI#P- z0=1j#2)kK?Tws*FJ+l0N+W0d+Hl6|cV4o2)xUO^*1*ZvD%;{Hu9ZMS00{F|dAPHcJ z;xhRN$Mm}lIZ4k%0S@U~h4eswP#vkmN-#K`mH^|L@!GvxiDq&J83xBfljzR^K3z}G zcejK-r(D#RYn)ly_et)+ID*DDj?@YIC}*%nrU=l&@bAE~H%;HJ1v!3q4vRQawkK1k z;jtY^T$U4t=Ag`~;pgOP+?E^v2R~dt`(?qi^X58Aj6bO*;`zF<6{bgz{oT9#tR|%+ zf#Kaup0l4ufgI~Fj@`XNf;Y-impx5M)5Zc5uuheal(~olQE&M))_+8mi67K*SZW^7 zbh+`*ZJs>?6PU4Vb5?a2Op%<#6ael>Is3sVZ=zYkr!CIhlRZXw%n-%Hgac9Q(uZ9GM7Sey49Cf z@NMMPGP?z~x`|&-1b#WQ{^|;&>m!z5U_NUVGvgG+hzmynB;^#Z{ zxVT!Bc#?wct779Lk`Nhy5-zozO_|^!{ZH!;uZGN=T@g@fdJ~QL>gj&TM*b6C)Lj6g ze-NiDM-$dZUuqwrVB%E9u`LTwg!E=ijdRla#>8GP?JA)fC>Nb%0(ie(-XPDXZlr-e ziYjY&<)>U26zbQx%U)2zSdDU0B@qP_M4kDvSjjX4;E^Qo9^@ z%H*5}kT^37&HxJ1h+m0f5|N4KG;E}15BhR^V|0Z)7@qf(sfnWx=&ydXB~?6-S*-ZuR@%;(aj=68nX&=c-a?L9H;ozDsHfAiekOdeR1 zL!UrJX8d?ha1vzd{!2$98zCQXJfU=&0Vfox+AES8@{V#;rCe;LdV9A9{h~{Owy*%X-UxX+U6ZP363@c+Os4!eS5&D4r0bjP=7Uo+=UyFJ*|%Nv(@@ z8!g%Gx!V_9FvmmcytkOaDdc)`d$Ez_IhhlYI1#Gktk#YMHu1rWmDskdn+`x-sa}kz zKm=CooW%`$1fC|ZRgLZOb3YDee6HLr@NPZKP(>a!EZi~5R+nwsC{tGNU!GBRheI$` z+Wey0Dl8`ZLJz;a`ZDYHg2*UBk5g+PFwHOS+EiYurAMR%WPkPrHkaj`|O(|r_v z&`&@Jf}0-zEq-GEicmQD9svyD*`B#2>uO){g1MyqQC06lIv-*lonI%selIqMAknUq z=fHcl>EnBX1ZpF$Z7eN7K~VVVo8!I@&m8vpqK$hSYKB96PzgH@yNcf(WcOqrr69sBqNGb46NNtDqpJTJnx8hh3pXg->LYIKMzwaf?oRqYF z81%bLk6k!L=n&P{d`s`rG#Ahr$7n}D<{=dWq*qmGdx^4fgYU5-r*OQ8`nu$~qE%M5 za@G8!H+RC;txS&8ikB0LQk1V43s>TnD}?Heqk$Z(-P2@CsXwU+T9S<4q1l6PS^Dv)e z2+dF8r<*$Lw4WNKf}ttnUQL<4&~Grf9uyZ&9>N}%etq=H_vjv5n31n&5ZSD#M;VJ` zXy=g#VDL%&3|J(MFZU

~S_}`+%kTCc}1=Jp$3*(j)NNX96|QTRwXyf z_I3c?l=)sSj<=k>#&HgF5%_q4ots>|U7L6W9=q1~eNDLZ_;?34ix7(k2;RpTmSO)W zB;f}jMUHuI-X*dEwh(Mv6v8*hUJs0`yg7g>ISJJK@bexoJm)6QR$ZcO^J_UW|zm zomaGz=S_Zmp!~4MA#^zCp(fNOysvZ*`N`XH^%Nnr&O>L+B;-}7q;Q~nr4zkk=N8+u&f~Q+}C;8GL>U6CL`(bobFk| zEcD$l|BuaJn$bL9+8i@xNb;aY;3z7#Y^Gcr=w;crNye+IJhmSxdnv~slnk$s+yup| z+mO?e$7Q*3Z_Oqt;d9T9ta`%+9)+ zMt1p+SD9sjAEMtJF&B7dblO4%+YaX+k0werWi=12n&P?ZIH9w9IgHhccQ;A7QCL3j zRaa9EE!DNY5-H;fNlQyM;ao$@92IU|@qEaaaH4ftb>1iAI4P;erYNB(neo^N-F*7T z(0u>OzK4;zYCZ5dwF#+lUa3hQ)o)$r$FGIm30k!lm-!B-r(Di)eqheipOX>{_e$@< zSayUv=lP61#vcqh3+{AX02Th&&-$ejOQD)Tn;ed-*)YI#4T4J{gx(<)+>so!bMnSV zx76&V$_`($clu}x0^Q_rHKc3>ncf5nKl$^qc}+A>Ki@kDG+C?EQz0;JDBB@bmdk+> zVoF*rZf$hxcH^w$>tFCyf2eF&+@u4y(^wLHqF$YDKbh;!vR&1~DfdiuyXIBz&&iGN zZeDs!CR+odnL?8S`c<}SyS0?g7sc(;+Zx-F7C-wR7Mo3{Pl!w=9*L^2s2DOQ#CjZ; ztab+7dFiXez_IkDh}_%OyK_aq0~?(rqP^-G;AazeyF`(>M0+*ncK=~`j(*lY)J95_ zwjo2ZA7rt2cbF(Z=AW6Zz^bTHo4zE}n={akJ|753D9SYa?5ySUC`67CJ<_zCfwUa2 zec*~}4ymV3a5&_GXqA@%kxZi(+Hjwo=RWBbp3Xfc-W=HXGb8-t7xOUdfrWy%_>jC5 zvAePRwRi9tmvUSb-QE?8yD!9vp_!E@2hK@mo%O$N6sQaru*(+7=fnQk!yOEFX$JgQ|drE%1pVd>`&q?-u*PE$f zx}FLB0z2H*Dz`fmldXOKmg#Zd(wkN0)fLV5q;SQLhq1=M7W(b_DP4k5PQaH;e)Lhw z>do-_59b=Hv<0Wpoi_e$cLJ;E_){txCE2xZk9Ek5OOjBF$u;h3C0h&aO(& zmWgQAjf`2SQ7SZ!K) zN7E<8<4#4_0IT4h;Z+OF^ml>d@b*0+&-7Gc#dKK7N+OTlI@%~!ec4pB;tTZmTR*vg zxU@}|`sBrrd1h%js?Y6Ulg%?J-mK&+Pk$x(-e@sSb(j#MJ$m@NBtL0nhw}Z*)VJ+x zRchpd-1t{XTxzRxMvK!^zRfgEB9T~%{e-?%920jQiNQ1zQO0PX%yb|f+8y7UV?+ zv~LY=JS`O+Ao z6Tza{;@$Ixg&*;M(p^3#IrlA>spT3OzHPi&XCJyvmc$cNJNiLkZicUVZidoCT^RJP zpm-$b1zSAzez;t*kWW8jd2pl{eK7F%l)0BGjOcRizPD2=6wSSoLKTK^Wrbb_?d$)w z5n}18o-_SNkrZ8!6vD97`b15f! zI+tGhvfQ(OMOym%TC9B)!u^a(V`gs(=_`+NA?U5NxEo4E?p&r7^RKs~*NNBVQKJM% zn4~+yZif0Zog=^9e+!so^L3HKC&mn<62ZXUSvzA*ge8nHlDjQ{)6}JqyJZU^F<#IFY0(Yl+ z5<*QA8k%O0Uy4*DT3bjreA&w24PT+v8;0-OA3?c2qM%tjrd{Z>xIxxZsZFoE|E<1RZ!e|_75LUe#=`w8Wj2BDKes|Au|mW#$V{XqH@!);$y z6==uDC*We`jPtu`g7xKH^cOB2nOQQX?PD=d5;W0ymChHJKWth&VqOY!Wk5T1eLG8a z*t_2S>OL%n`v<;kDZ6-t##xq@X}i28pKrR(C6;6gj-TiktJBub{ti=^@yF6CGEYFW z|7>f=du65>;rS7mnXzlf?4Z#i@$!|xbu)wHTkqf%2c@Ih8r(q(g&ueqA^FqdjF*B+ zcma=nhsJ+)8!x^3?UJertDXtR%~wfdz1QpjqQV!F(nql?nzvhvaSYRyzIs%m%MRAgwk?SY; zOfQ4V6HIdVw?8rFlX7m(T^Fw;!fL&*p+{ST63V=UTZ}zfupONJ>#y+PdBt`Fowyl9H{mh76lUTpGi^Jp zlM9?`X^4GT$QX#vAHwQvn_P3wzEy(^c6FFJ&G&y%ZT?PvwuXMo;`j)m-Q*>vuRZ{P zyg_$~sv`&!WWiSBcx*@X)jLo5)Yr|^kxXb&*ISLpDf_ox0f9~-!c0^Tb!~8>Er}H5b$-P6mmz#?U2xd$*4?7IEK+CaO1>>w{%?y z6fJy46x9PIN2&$oV$ZB&Mnk(BQsaXDfXg{lI9N~}?qT^_gF#hZStpN?TGd|oN8PWP zFJ-U^J7KL<u*Qh|&eYzkl8vZ7Iu*_F@Y!D1;V&^=DqaK5|0U z4r1E26vMSSHI_N^{7zU=x=!iZE%UdQ9J6j53Zv4h-i|%G@+{yE%K*Ij2kzt`SqcqP zvvgA;Ej;V?N+-OeC-UL;6~Hc-3l5YPAga0gKbT$oe=s|+z;6q|-Jt=1v@c1C#}MmZ zzsbl1e+r~@?d7A(YlO$B_NExF>fL1RQ#mHYHvY`a$-J}DXaL|d#oshU&|ltjRx>!>ZbwGrc#R%FT71jpIe{xCmC7HfRPbA zrQLrn=vTUTG0U)91SVblS-bn~d3fC7tHa)U=Xcd+xq(N53r)zI7tX(7IK2$IGb4h> zstQ}TmtbV+qDgm=yee&HsfHXR>CQ}UR)W_KY#gsyeFVU`m!Lv0KhW8@66tW0KRM3A8Ee}&>b>8gdaad~9ylbK8jG{;#4hmTng3DTR(?@6H`jmb)z(GQ zw1Dxi^`S0_Uz?;<^S(hIVWFje6nmPucL++t(JFl~!$N;iYmUX0YXeKvcAp$Z9cFZz z-KJJODC1KH338WU#0$cqcM+O%x)tg1qmvnXyWfkOQR+n}RiXet^3F!K6YZ=~P%x32 z05ra*YItcRlZ-^@me+V$@c*T5 zo0|*&&`1<{FHzY&e;&r;G}rK6q5drP@-v=N7gvzGL^7f^I^@#UelMkY$NOclI)_T> zVSJnAfA}w%qRkDX2vz5zEi7Zx)A0LN{Jp<-%#TVdLU4s%TN#W>&aS${FYw~U?gg_N zK7M6e?bs0{jkG%zT=2{=VzEoonQ1{@{HrLkN#!T=gmAs=sgbO*-wG&%jJUn6xGM{d z)e5~&TwQeae=3)%v;WC*?4?=So2;FY_J9-9Bz@0u`m0T&L>`Y~dUv4chVp2CvqBrK5SN;xM&209rP|%6r9ll0NA=3Cd`+1Z>zP^oaJA6`n z%d40&GkGvDKd_jnGA2>JD?>765n3}b(o4?t-z$GGIQy!^M{$tJgy8C2COQee7vUVX ztYqc<;j!-8%|SFC(oXAZR_QEpyVLdEVa9?PvlQrwv4=%$MqlL=yjmZZwna;qU-CUF z>i#G5CQ#1)pfv%~5ky&cwEO;mi6*J~)kfK2Fr_at%l)t8kx6WCppG6Ryzn<>`b^Bb z?D;?}+w8S2o9?2UPTilqk@QZScl!&SFiuewQirrXkiyAS|A_85lNkgzPAJ0dbjP#b zqiB6U$M418LZy1f+>fcmD&Pm4R#99;o>;stKzN&DO6c!g)og-HLp}04(@z(ir7f)_ z4Q5&k6hsvt9QU~x{ploZ;?h=-d$hQ*<+C=_6$EoV!SKJcy+G8wU*apX=E{PBCsv{d zzY=ZF{exkq07C`&!y8I1;)pm2o8pMzb5+7_B>y&R4NyDjpcf){*z3XVh(`3%b`+4c}%&q_yGV54jAD;I204&8Jb`lKwG8m zwbt``=D^|lvrF}Pi-j-5`H<}uj1#T%^1b>{#G|E{kD17DT_HJ+_wRGFsW|Iy-;O2Z~3pNxa z^^c+_T;f1t{L&5J8~Fu=*3JH9t-}r+Wsu+Y@FoyX$qT8rp&=NT48w{7hjJe2%ebB1 z$A4nBMGoC5Gpe<|{-coCjTYbZAYS{lDg@HSQHzQ_E%hU>Ozj8hDR7dT!Z*-DQtN=ezRSerlIu;GD!)6A9 z#QqQ3&iwx((NTLvc`19q|L!oa=VWP;ONE`oT|0AVdC(BABH_|Cu!uml#1i~Hew*#?_UZNo ztAkkEhX#qPmDPv~G)plcH&x`yqV7t5!Q)b($G*pcnhOkA)#E151ksGw!07)`bSji? z`)|c5y^r9y{is6@Bf2w#1_CTr7sCOV`lOdo@6MWq`nxU0ImzB9`c`*0+KjJp(>rjO zX~p9(TiCF?KPb!Z980-A&7+9xd{aQmjUKKAv~~PxbynMypsqa3H?j2X1|fGX;%g8i zq=0o4j0GMNKOITH%6?v2qW5~P+jc;_fO5cHX~5EptJA9_M;B2_ig^28a71>Ymfuszj%HK?IO)^fQptQBo@L%}mH= z??N+#3ZC-D`+%6LcI7a9*R9x|!6VU>-pzIX{bQL6FWl&v@njGiK?#PZZJXOp?TWDt z@D~1I=;y{~LU;9ey|k^(FdilBa)M`GDk|nLx81D0DFxBG5XqFXk~SwNNI$%i(M|Iw z^`6qxQ3lt{$ZS=H5%-*gFzRk@56gf+RyVa$s>cuW-lMpv1-AzdIvjQHN!-8YTFVzB zzgZiQq@1Vl@*`Fza>dn}%z&bELJM5}cagj0Q#B`6-ngIY#mUJ3xJ8@6cyLB6SHrC$ zNXuaX44m5!gdJ|779Y@V)%`n@XN1w@$C%q5e{I~#eN`WZ{0=E?!9S8oHbxL1bTug) z>6pbBGzOwRfiS=u+h}xh-cus;NX(B#mx^0hu}Kr%&ZkC3g|=v|Rfh`}t#`I_J33GaW~z7srEEQt!2OKl*-p zd|>%<)p?*{tr7(ipRp_qlGzT4T4srH(NC4q+-PZwAhO6x zuseFehdX$=n*XqF^A)wzm@?K~h9*;JB(!$MsBbcN;1zpoe^s8G0!VFRD%C))L-^&(ZC-wyL_2c2TKiG}E%4QTytelZlj&49 z@7=LgQqT8X4*Jj4@NytqTS!RtNg5Yw^;bQZy_#$GP^{-E9tl3xf)tma$b{wCFBfE_Ec*t6!1OR^f(W9KvYT(v%9 z%Kd%5Xq#P-%RPCetZNHYyzKlX-vLNhAJFX*-KnrIXB(HD)4YITq$u+BNa8=5nS66^&r(dK=Bnz4RtapU@U5@7v)0_e)yS_T+o-;g&)&E;i-U=jXmX!1d}oGx((=%oSQo^>=RKh)fZlc3@;4vh ziKUGvuyBYxYITS~jTZOqxs=Lp_#+=KJNUH@`cM%mC!ykJwfi8J{J6JTNwiXQqDZ+F z0`bHw6%FxS=X-Yd)l|jDw8sTb{3oT?LvvKoskUfUL5U_r6vt^81xUn+>$1Ahs9E?IYfCBw=vC&yz1^;916$kMqy}*64PQ+~3=q-!t;!3Bq?n%VF2B zqdD}3We0j5(xV=f)zshi5yRMoqGx^)4ibYNYSME--YLF6szk?fJ@1 zq^`Nxr;h+{q>sErQ_q=wF{z8co(PE|9lC_K`%w&*Nz5*ztrzwTv0a*vx9PU5ds=>K zz}>uk>4VaAc&bX&CvI|708Z2G>6ic?09XIfypbl{W$7k{I<#I7RMf($SG<4gzHg~Z z%?q2(Fz?IQ=bLBlXaQ5vy*j`iE3RoJr3-eU^ZQ(&Dn{(RW4MA_Abzg*mSgg389j#? z;SiptyS+e2^QsSH1$)r)+?wl7|2A1|*wan8PBN?w#uo;HJ|RS44q`yJPDaZ>QTb8t zWFA-P$mwn_tLZg7Q;jD-d(vDmlY0R%qV$nPhb4ZkvrM}Wk@d9E$KCZs1M*O(CCrX0 z+-ZiXLR|8R04W8Tax9o z&S$7Op>hQlNui%0Ijkmhh0pc~&OJFR2Ro9~u2KZcwnssvB zAs(EP^?-}e2y=6ESY9ojADgahPIw6XcLw0-#^YOFe!>02(#3Pj()X8Mrl&ouTg zkY~WhireV-aj{L&mVUAp3=o*jZ0)MExK=^1SAdk8K5GdYf`JN4ck`dIy*JyNK02xR z6kC~h_4$!CRlvkE$x?7fYqM4Z%CpKEmYi**GFNttQH{%~R8Av25k|cQyrC-Xcf`8O zfo3@A4$q4&8X}`mbt$QSOOL=#hbif-b;Z;=n77=X?ddXTb_v6|XMpwWp;ljw31MTp z5m#!PlRWO>$J>So7tOY%RiL{j&J1M;^p zSrV)U*F<_TDcF?RS#8;UvsWnm!Iok*#p2QKx;eUi_&E zQb<=(#NQ|jXqd|aMCU3(HkdK-3!~fv;IPux!8l=NPEQMhV>E^CMEe)~N_;e>Jsvho` z``SfFXf~$==V{b?)=wUXRGMiEv~?!^?$yYjYN6a6`1RZASu4wO=H{-rk55bQ4O^9X zSeDs-7HLZA$T7~`-kM_=^ZaLaUwQB+^Y_RY!A2YA*KBW=eSlRNUl*hD|03h%@}asD zQ`gOb--MG19EsJ}e>8=pY(a*&v%svF5FVK?kOH78*%$l2l!_(h@G@iup}uFQAxtvR$yFS}kg?1GF*@`qpl z(bO03DK5v1H{0N(SM;~SXj{_cokD{0Ke`226m%S*7MSw`^o{~`I==FQfaYI^>qYeH z|3XTBtbTos;Rpc~@n0e&EFZ*&vH!xM-Xo&$A4{b+rx|5Ah`3&Oph_;+txZRt3-m08 zWZ+r8?11YUVf(juqaIW7p}M$#Mu}_hig(S)H%x^99emCvD1p0rs` zzvrFnHaTEZ$-YGGMr1gBdX895U?Duri@j@-9P~hp&@k+V-XVLfY(T3bDBBtus#Gt; z+7+K%nSV4Ngo(W~i3*{>fkDv1UpJ;fc(ef>_ABt(g~w^hpe6ZD`8pP=7b4oz3(>tq zko=NKVOM-l18DrukY@cKO~`Hl7o~Py=&TSie?Sm3h(g7N(QUf`qs$Km^`p5vzWt3q ze-lC8U(^|Jg724~!R?WeW(KJR(Ke(*ra+yZv+pqa#jV2+YP}mGa;E{sq`<5(}N$v;;QnzH+O&Wal)Tgr6HJ7t`K1eF}=-@ABgCf zwb@6k^a+P6JI2B#CmTdw?1hDGoty31GHC;5YE>5i%3by8&eh_h}jOPp~PKDH9f!hjhB@L0qeZkkujCwT=g` zA3KEKD;~U^s~|vShfPOq7#&B7J&-PN8p<$)QSHeJwPgGyB%UH&^;@ed&C118kT97Jb{J0{LfG;A=K0CVr{%Br6>r?8dcqB!-jHwj(}{~&eG!XY zbVFxu?=`VKJ$!kdn1xTF4;x+LQj=bl1a+M=9o?^64jR>cVxcV)!>)9@$DO}0h-eS> zo069DW0;l{TkMKDq--AV*f|tqfp^i{&C5@)r66Gix<&Ce~6~g*b4tZr!M5I z9HzMI8gkV>gzu9PZ>mR=1+^t*$%K%K0~l7Rh?cF|Xs-?nrBt^}6iE{?{ok+ji$uMgd&AwSj66-O8SL2YGhh@9Gz3A}{xp z7tqxN?*i(iQGu*Z<3-hSsCJmJ2T#gF%TWqd-mP(hZw!@M{=~h1kAExRQIPk+Hz&80 z=s_8?M8>#7)l1zn4pBunrpB~ro`iXP?>}LOge|~p__|vP3tKX>-9>&}mgZ}alsWmZ z9`0eky;O%l?L9jn+M5J2Rz7kssE-ERy`^w)Ql7#@nL+Zdj){)mPap_7ai`E7{eb!2 zzv#e#m}9`d!*=7Et0pCdTN)AuQbiuy2~zKcC}YNAgBPuedCOV&Du= zrt;!AohbVW$Ce49_urE?CPd8+F-u1r4{}1guZC2whyLwh`=yN7&ctg)>@HQII=RZN zOH}R~@dn7M%8(7H4hXa%N+^bqiYLh;XGJ!H=h4Q(C}<=bN}hBUwon&v3a>3HW3Of? zt&rU9<=RyHdYKHeB#pP7iDkX0B7%OXdx(wG`JMWlx0- zZWh{=+Qv!<53tq*vmHRTpBkSR_fj;AsH8`$(+WPp$qVF`Bi{dl$XJfCdLaNCkev-b zBD)ct5Ix0BAkUb#@c6+$cm5Nn_dk48*BWVO26if6?;9tNo10PClM@wj`P(pM75T2w z+Ep2mwOpeoyc^!-lb#ZvE`OXy<7|P1D$w{XNP9{iaG|eJ;o(3CdJaNdB9Yft51;(waSX!rF`!J8nLHEn8&_L#fHn7?-~jtL6;UYz4MDvVMEMvh zIwnKJJNJs-P=X7mx|Z*Vy|X%4|4-(g2H?y5TCN%(_$ZE*&GVD?a7Qzg9T_CQ?!SuJ z*ZLs(i2p%fw;nBz+nieOHEk9SCMru$#X9IPDtsPE%>lAkTc@vEq2~8C+6jzu!i||#~(dpS4bJl zo<8+vAm=WC|8(+OC5IO#nO~xC;1&OzZKjw=pZ17P{+<(jr;@b+@3=mHoMccJ7(C;k zEb<#O+nlFmC){v?P?aV)YzK1g2)fyf1zK=sXXg_5WlA;rZL3% z;&-MmgFlo;y{x;3TJF7`0%pMR7LK=cU7!EU0bjq&a$ssYe*?KtaSpf|!+3g8?$q^m zDz&m~u>R_)!{a_-Ogt%yP;HNz8o%u2&5+9wL zzS4iQ31l;V>~6WO3+@N&9oqZFX6C7ETTLU3#ZA6EPku&xu&nDKwxvn0&DE_;*hn{=c8^^!(2@1fbhsbO2REp z5<939R(-X083Oo6V^`cc!t8RFshebklAl~l3{k6j!jTQ*(e}TMS`;ZefKOl67u$s| zYX^wEW_u3@EB^xav=Ox|$M?>2lYt*+h&dyb5Bk5H}|x4!ni{=3lUcAO`n2~tShad_oevfVWDG za0XaA_;9K6Aod>JT&YWrDy$$L_mAe*k_xO{d{=r=Aqz&(d9%VuE6zPB3tQkg;@~kU zrm)SWVC}aw-gT2n^%878ViU# za|`0U;#-DId$oFUz8n8b`u3cV9OLV(BY}T3FzM8-!`U>s2S(oDB<5#Ih-W&oQsT?d z7PrHX6#9I=!d>{qnzCqm52)_;(jsf+`zIq9TWx8AlPO=w#(c0;IWv_{VkL=Ti<9g| zNp8+*-E`W?R%Q1(Pi4=fkFMu)oVhGZGMJKcKq*5 z+H3w*B;#`Dk{3@N5+Vw^G9vY7oTbd$VZo1Af%cY0~6^W?9W z0g6VzCk4Z918JwjCCImJjnIDY-fm--l#G@;lFT!a_;d?A96Vl$>(8e zC;AEB@SE$(YfuwEuYiK@fx&Hllni+awR*#g+0Z2 zLvK=q8F+q)H>C_5z9*PLsB%pAui6OeQ0aFylGA8m$+}O#?x^HQA%(b8uBN8^x^~~* zC?N4?6QIb^_jMahkT07T#2o55d z4b?s8MJ`kOTaI+9{>PBl|EDi#|4se3kwq5FnGnBulhexQMrc!064m!u4oM=w!SEP2 z5>l>-fjYK87V92(a9%czmn(kdMj9&R@J}hL;_dpSYV!NQBDm;7R&8_L_)P}Ey`A14 zos)RuM9iP{Pi*sNM=L42*~=_38fuM%ICr)4j6yGcZL|c}1FMQ*;I>5%^SlhAU{ym1 zk+XW+vPwTg{BAJUXyGmIwYW!~HP;|7K}n&s*p@7Vi!+7FZLir?{Qjqga8H#tu<4j_r5jy5vfc96+8D6_U46Mjh{E2jzfk%Y%ai~4bn zEomGttl4TjdBB&}5c^*=uf&#TO!jm)`V^$q9|^VDjw<_T6mQfXP`9iE06WqN!EHgP ze_9FGk2b%CjGq+vG_ZcPZCU|da#C@yywnMsQ^c_Bo&X}%1l`Tr6f1CA>Jxd&gL;I( zcALRh!`fp=!d~d&?Z00XZj?XO_qbk?wSD%p=3YXn*#3dNDz(@vcY|;VE7y_B_q)|< zr@J+X8h6%lR&{B7CXnMjPQS~PWfk^b<2KGnEm(YJ)*8Gnwy%d0kGm%m@yFvFEo$}| z=C-_rDJg%wZ4q4j@{_Vh;omSk3mZYRi~oYVr{3>q8`0JIDt&H#v&`g40*)w>?*^-Z z#1~-OA-e+ssY{*=(e^1Ti1lPZp>3|!S2ZIS5p>JQ!}hzH>G1M2A*~vv_5AsjXY(hB zji?{$jlrMRS!$}*TRtv-UMQI#$u*Qou}wdhrX8M%WbKYuPkHfXUSq{v#5;>TRgwNW z=;y;8?Yoh7;Hm124&CAOc%a!=LLJ4;&2*0cL?D^AvLccGS&fHt4TuG1-v@is1m=N) z!85i%+S-qX&L`RvP`Kb-wHavLL*QMOMDnCsDDYSnZ%6(RCJMbf*&KiaV*+B`KtCR#PxvBcK41Qp21O4FaFV7dVjYG@*28AeWsUMDWl{f z%KdG#%DyXusk_%-VkjEs(52In9Y{6H&ESi`qgHWOrIK?UYA%QNF}%^iX0AE6_6$dK zrwnI#q5{>pzt<<%EL~f)TpWb0Iueb{*J;?e`q$8WicB*IfIyFgf`)v9r`y&cpY8&H zk1_?Qiq0nr1qx9gN4~IIP}3Acbk0&dYgGprVE<=4naD-f=D;D3qNfMDJ$sc z+C9U;%&h2a7jHS%#6IB%NPscKzUz0%t6!fg`G>R?^}#^cmvp9CMTL!WF1tnKJstCt zml`J;g51PcHCC*W$z`4SoIdql&1R~r+>bL6$=}c?2N#-_Q;)denm0t-fFCVp6MK|$ zqQM;J)KY-9cn}lF1u+Y3M{hYQE7XlzF{qGO>bGo$_qG^;wR2<7vn| z-bqg{J!1;wvo9RIzR0uVbVJiCTz4i|_TD_pn)xoR8a#WdwH>aJI!~~DTISDnT;%pM z&YwqlQ5~2D=vINZ+5e11x$%qBabLQgzhxt)q5;E^KmDWOIc73$U!wkB)Cz*#TqfGI z=8I)WfNh@c#KENnx1&=$FSXhi8-xFX^XyDX%z9c)Am|8Jx-oej@sx<7K+0#M@A~1P z<+c!@A4a5dQ_)pY4llJS6=pf`fj=z$_*1=_%Nti`7W!d3|J!R<9%ZHNLBA9v;t_vg z>?;)X&Cpg;M9e*pXL4H>z4N(lXKO;6Lf9<)m{do(<#qV}R0%_?i;4P922NsKlFjIY z=%J(svpURway)9B4LnJwQ%c|5N zA)q|{A~(MTE1?@K|R{d#E^{&Yaj(}5?Tx?x2& zf8qqO`SgH0@;kRtMDzMsm}QYyCtPRx%#A|F;4RXP>NfTP&x*Qn`i*EdT7M0Ff|zMZ zyg;k&c32@~mBI=zzWKbiEnXHDw00IK%wn(x(j#m9 zNpmKFiVBCJOI33*v}r6Ea%Q}w0XzVY9KI8S)2WnH)OlLu;Vw=86or$Nkf5SKE*_V(|3(UNcRv;VuJN+rtN|yDw&@ta9&yWA zNiE4pv#X{6!KV=ci-4ZyTa=}a5tgn7CY4kVrL22qyA!Zwere=0YDe!dtX<90h6SHQ zXfL)&%4CEnuYw8054gSF1rzE$y3BYM5f{e4qkt2skG(jbo(sruN|xhJQ96q=>lvSu z?E6;03MOsP|`$?gH+JFPPxTl8pxId*z2EJyR$5^O;?J zvO(&|TFcu{Smb5vE?MuP#3I;f8fO-P=he$ zAC2IxllXr$wt-58}yUAmz~G_l7kTESvkB`4jFso{5X+Srjq zk3FwyO9_RsH@d`}rG<*QP8cVJw{vx!8qfxF8lpcnsvoWJaA*$iKug%Ito95oCBdHQ zRaau)mRR|RIYDnu{G+iS5Tx!m&_m2k4M7nl2mzn$XUi`{pc?z1QH6};Y zEQRwc!13@H%?5O)Va~S%x*)2!GFaI#Jr+noJ$*z28 zS=U37q%5-6=~8KP9Zlyrrudp)ZhnCTqkBE_ z1ITJX^-ulu6m?~>9jo!_VHn-9OmjE6->><2~WCtLep36dkx2z#(sS%082GDWgM<-d^p@tI?h862Pt%aM5z;s|Ktbv zIanYk-~XccZ3e#}LL|O9C5u1Uo|2FJs(AS=hwJ5!luHLj?>1@+ymp&Xej|7%O>Z`a z(Rd;(M=zxPP8!BuL+Q6gQ_kuA~sGwPsjJ9U>D>^JLf=JeWIvbx&O@EVc^hk+ zLA0VQx3F(o*WW2T9LE0Z^Ts2G#2b9UsRt%6LDp1u2f)60&a$f$S{V4zXv|%5h}<(> z9HYoa_tk-q$c&5%f$WKhb?({YLAZsfI8bMAEdx)e477#+a^`c^vr%yt`PP?vyQ(iv zZfwIqCO%`c+xzRPZr5@{;5IqgG7;3XVK8!2jR#etgEHawa*z7%R$J(R3C=zO#g=D9|}PWNS6fGurb$eq1j*T83L7!TZct+~Xqfab|B237tr4B48 z;c@*2PM$P?@oCj!!3pgtIgz(*V~XT+W?DWx$%)7}Tjtz*ZEQiV@ymVz&km@HRKmC% z+VA|M2{qfGTsCfXQY25FiT8{9KH^U)UX3-y zmD1yeQ>m<(1^E^nT<(bPo&Fz$@c&ZCt4=cJ3Lw0g>rbeOrCIA;{|N?q#z~;&P2T|J zs$aE&9oIVyG^bq$6DPlwv|D_TC`J^IHGT%hcN&_hnO(z0eZ0q;9|A&NA(@JQj*|5` zaR47!yL!bypw((mv!{(SlLZEr`GMr=(+qYHGTtmq04pSV=Ya&&V%=i*iZ9bwrT?TL+|Rp%1g1p z4qCkxq@mCso+g`qDKfgOvtP1jdy|QB?o=8NX^b<~ebM`6_`-1L_KVQ9NrC|ScaZbP z{I{5?N;Sik9NM1TTa(Q~t0BHY1v?6dmNt)>$3}JOzXB}ddT^Ds$`(g}&z7{iJVY?` zZiEHatPPMnkQc~e`>9X82B(`TxC)JU6H1R0KIHqdo*8pQ z@GawP$;WE1EgvYXfv*-PfyP*$lkyQ9iSR}@1J{782^|V6(ESy-Ab6 zWIBEGg4}Q6)HU-cA@R+2>WzYR%i26kV@j>qN9u7LQg zlrDmr%F55T8!lRPlL8cM|1Qe^>aKkNP6jb%_F~1Jf!FzB-urhY$U7H*b=WNc8&vB! zc8EH8Rouy7f=Nm0#gDn^oAuv&;si0`Un6YLQI=2Mc&=#M`rdb+Fp_Y zA!OwsfuClI!b|8-_^5||c~9^8$~YnIv3mRmda}5y)|2}kpXO~w&x-#;$5P1O{U9u} zP$gUnN`Jv=W$ouS+fzg7&o7M+ft>!<;&|0`Sftt3QiPhw$^i`ltb^5wEH_2zj!I(c z>SKK)6aB;*JbuEO-9|d>a#Z`D?H&VPsTajr@I4UAs=hwYBEMPv<>qZ*PD5J-vLosy zerxUHRW15_w0jWO08!C?tb?RGf_^3~ypfwesO!Jp=!NWjY(|)Q0?*AqEZu7x_FZh@ zc22$=2-`EpLW~I1RU*~}qOS>kB&k9)yk~H^s#GQ@RV)G2ovAXRSQRU{Sci0MA^%{R^go-O$W>=Cc1YSg$-U(|$VaGE_QY8QB41 zhRP7VCZz7W+3_Al2@Pf*CJGOA}=Ubz){(ax2 znwVXSAJlTs0b2ab&<)vTIU=QnPtdDAy z+ye2nst0awtV$g`FU@) zYYNfT8^?PnZf@nWV^eqf>@75ks7V<(h2NyyC4mU_d2UYNRxI^A)$$$<^!6C$`jNgF zO!3PhYE$|eH@ZhSogr+Ln}PUK>biY<$DlHIp8Iz0)m>bvtr`6J%vt7pYvzyM{{9VB zrH&OT$^;Q2<2+QAFaqcS0Rr;0rKbk+g2jTboWQ_ zYODFazM=UWkEWbXoNT{qV08+UML;@SUkVb9xkssb;D@Txy5RbO0i61;ie6c`_}2 z`MKCKFL9NBW{x`Rw)P31&#wQr6b`TE1u>FLFjN=~)g>D^Vu_3D*F!7P)pTEm`3Qh! z5T)1MJBqKt@6f!>`xImnAKa9Qp?^rFxL(JhUAT(s6(1{k1d;DP5KygoknZX?w#NP1O;hBpkc z0sfoq4JvLd9#sj!cvj2@7O?_u|zwYz(R=C;_7YKWclClEf;5W<&)!~f6 ze}!M#BSVwLfBTtQ_f4NeP=KnG@TC=#`VQn}Yd)1>uC6!cS6xyTB}hKz=Zo0eaq#(`X{fk!M|&*F3BIRkf7AxpZ^?J9dsYL582xu{^d|Ywmr$IQ3lbv!2`>>sd#7g$4U~Oa z*K>Q5XdAsnUE%p3+b^oVvNpC1qIirsZA{(jmw$@XrX<6hKr=8Sa!!~8VSJTQ<1Xa7 z%c88Q^qZ-5)mXjWv80il;se&6#YvPK2x|hG!E}ZRPLLE41m7-gjDADLtZ6($XyMAM zmDmdnq%7ql!A>!{AxlCZ(^#d4Rttt{InN6**hQQZ@) z*FN<6ClN(cn@;9z$v70AYBSk0Sk86_bt|$s2&QUemsq`Qz7k`t*uUAf^8TmmYr@wU zPW|f(ODA5RzTbiKZNjj6?$i_&$1NC}#=QkXN~elehk<9ICS&Q%$?bTNtj8%nxI^a1 zJ;WqckD47D=HcO*x+aOywSPEjB=Zh*+X8pfr*dB=O2eFbI!j)EQ6oG5Y3F%d(7_2J zIZ}PRkX2v7Ts*7#O<|JfHC2}Hqnk8EMWarDCeen4M+RsgA^sOfS(MskrP?Sn4L3Q0 zq3s>4;;q+HmEgnQz4Am^ok3e2z8_E-f*Ha_KV((<(q{0_qogW>fMTl=U`jyXOxZfi zg|N;gIw%9K$&B#brFh2LIXFC~YIOF(-~^oE3@_b{!hx?csjo@YU*_+aBL&9qq@F3?!hfp9DbC(zLp$B=%; zEZkW)%)O!S#~7(32*t5iR1qYF7abLTA|=?z*a6O*@HX{xnk#ww18kT@0psKrf2K6{ zr~g_PUdBXNLEL3mYzQJZFA3s$oNprYb1XtYQ7seh5I!NqI1z1L zn`juq7$9~K_#RL-!7bvKwKgt8J>nv8cE}g-6VqDF@p@*6qcCOUAI)?%{`nMjWvTnF zg5uP`KRQFnEfU^axH+otk^fKcVNlvth8Xv0RITea1Z(U$qo_Brf1IOfI4Rsvow^bv z_{%@G`E^9ZX)HC|c6?R#e1;Qau#Vg$1kDT?;ocPtN7L(Ev%oY--PiOxNv$-VK~A$;&V zg*RYK(8qS)cf`Im{iBJ_l`Yfj$mr;?NS>_7ek=-1pKnmUSo3x+LKMJy7}L#V3yN*5 z763IHS=($ zdL)Sj7OJSGhr!E`OKO%9EDyRyV)(@?|9JQ%#4R`-EeOjD&c)v|pP>>%3s^Y*;$$|; zAH)uG0doU*7iWH@Nh&iYM{5ytU#C%bqOW|h-yB<-QQg+@+`hT=nMC987)5tU0(~yO zhky3C?>IFfhq|c#(dbhL$3=wk4wVns%*2{cy34;G%sJ?e>~~hVzkZFP(x$aXp{U(B zqCM%M;qpPk5{Ds4MymUh7I1K^rzQ3fGqQ>z|G@qZ=o-w;HP%zk;SWBR?)^u@mRE7h z44R@HmQ0c&*sp*iG%k#{@&?LqnVXkN0z=OV?K4yHClYR@?a$}=!NC;E!6TI~87g%u z_1%Vb6sOW_cRIQRO?&3~YnJ<;V;_zLAC-yjnmhZoVsIFZK%SdOf<(x<_O}%%wq$6 z6(;}JJX_iI5Rr&q40tcEr1qWCio55-m0*i%aX` z3V8E}x?h4_mLd5>jwgo>!g6F8P)3+?dlo7=8MYqwm}gfrj!WVbjBOBD#EP#x)Lb z=v|%?5(f?yDS$t0ei2hv(uE38E-ZekksWZoqmW2KVg$jxdDv1Gt*qyjSm# zM2fXayH`Tya#YTB3uY_lEpsX~ypSP3{?X{|QfR|EKsDe!h80QU9wgKK1gjiH-G;QG ztkpwRU-d2lx$dj~Xg;Mj1ij)EE4O!NE>vv-2)kxI%m2Q88ho?zlI7yoQJ=dvgV*Q) z1N&P~KY@7iGC4x+(rP|YY+!W&L`MkdYJ77Zb@rPw{o7fDRa?lg65Frvff^Cy;wM}B zCm`-kvsNMLGA_S;dE`m~zctmhv^yktHOx@yFM>FE#^YA3QCYauT!-t#XDB60Hx|z} z%y_FojQ;pBX>2V!TeK-%d66|fTBEL~+&!4^w*;0j^aa}YRe1=7W|K9PWO8TOO$2N zn9R{Ev95R6!5@?Rru|4%}d##vTYn*|1Qs11v>gh#rAO;d*BQw<}m z+Kq`?7b!Rm2cd?IczUHfH4Be|p2|EJ#DvRO;Vd*#-Ms1z*DbDU*y?h81C&87O1swp zX0i>csi-ch9sg%r(T9%O)!;$#$?(eGFdnN#x_QQMBAKZBrn=)gvCH;SgN=`kvgzDI z@bO&qQRMp%2b=G1EJ^DP&!(mH+#*&}=r%AZ?14ahWDWT0R-?xEA3F+Z7TSL4p5oVs zD{K|PUm$CH6R*v*Kylnt6dsKoa$Ok10!fBoh+|k4Eeks@N5`#ICVmfMRH*0Vyijy# zl0ugl#X%Urj(1PBUd1KF#39~9f9Lq}%FZLkt6QaP(HX_u(n*!qV?Z2K*~FGy2$e4n z8}+|FO}N=JW$q;M`r++lg}}!Yok4Ai(h1@QxkwF0{V^oBUyl7UKXq_(4HYgKY1(Mh z%>P<7FG``gn`_?~xDVy`(mu$RA5NW4PfcA$Cbz0nZ}AcGBT)%uTqF>NC&93^xpNpM zDtC0pasJV-p1o!qEGD}mXlCAL=K zKv)~U63&D?l-pD?>r(#&79{sDPK5QnfHX6Cp%J${eiP>Al7U0-!zjF7AHDY+Y1QVaq(o{!6@W zLE4W8v;SxeAt`|gou9uR0L`t%o7SJ6|4iW2XR#SBtE$|lUUjaBk<<2`Bk`@@ zaulp6=VxxX5d3FCKK2Mj6`Qonaf&O=nY5adSz|#rSA`fCUx!?dryU}wTfW-hoz*QLW2eoZ$hxK7lOhW%tIiVZAt6ngR~cgp3uV1xe6H?7_&xI1 z8;4d2eJ9tZW&*xhX_JqnweSlE5Hxbm(Ce?$YR#c#D!c}yQ3Fq~Ttb27blNB&9Ak<= zE6z57qnY|VO1KNP#_C-ENAngim_-=^t~vqxdWoNbS^|0B{*ShSs@jq~xK3+*Hre`v zZuzmeTQ)1{ZZIF0nd=|7Mi8|{VJ^sM;c@co$5~pYp8LSBX3yl-Wkq0IXo^J2aTOJu zg$b5D!_g^}*h4HRy)f2Yp)oa2EV3g(q&}$@=$0_R{l7SS%b+&D_}dpsDGsH$rg(t@ z#htXJIFzEn)1t+TJ86r%yA^jUu4!?nMT-SN4tM-3s`jwMD{PB?g!9!^V5J9l=(fF zI{8Sa1*zF4+IV5?N=S-n-@Ad8}2BJLVyBFeKPCa2T!WVy-?(;h67yO>G56KD)P}iGs zY!@soKq&>Pdb>2~#EW(o1>p^(AA^oL%WZYZf_@JD^*2K=9(tv>an(eq-1Onn(y}bRu>xw!yq;XF^ho{@JR^}JZ1^1t z*8z|^V)SE|^=t0iabXOs(BK|}Or6s&HTV{Tjhj7|A8aYrm?$x|OHycq>e!pQ}6{W#@*HsGtEiA%swP~TFO;f_|Z2nTpV@oHE| z^*l{RpFg^Z$**=P;0dSIkv1zO@*R~7SG9U^F;*j8^wMu^HjGPdXki_J(uJaxBt)GX zd`LG9BoOs+GbicG3qbxKR?lfBukIx5f5N}lcB+&dE?X2n#JJKl2Yb!Ew#NIa<^IYS z40fJbU9J!zfBi+Z&PhTfmBV(b>YsXYdZ-9W+m!M&dQCGFK@yK|s6dA#mgQL@u`47M zwn+6L7V>rrdSA8lIQZFuow85cXPX3+52?6tpm1I2?XmU9rH%B1qf(~M^0pj{Ve3nt zh$}H%i?ziB*f46A6LH#;m-sJ>`qJ{3{)2b=4P(E)zfryrvBPf-F?{fBt%)}AVc==( zxIrtYck@44l{7jlv?Q8w_;li2*y2=ya5-eLy{+U)3c#U1&9(4tcU4!rEmK`Y+( z%#A_u-4f4AZ2UNq3i^Y2x_ds?3w#(ZNJ|7C!PEHiYmX|)V=`S^X zUZL0TUwK>JY>j?X_Yb~*X(!g;E2hHgg1gN%=d!Sw>Bb<+QtHk?g-PqkU7?n% zG;%sZ=-Vwj2Wtxe&3+g2NSA9Zzh)k6UhX`}7Lg^AzteT{Kev}`g>uPndybS- zVf2w?T!f+Hm3>c=C4j;~S#{}zo*W&|U-+k)=%jADz4zu{af{zPGSSUmHqZ0RjILHu zdSj8rs=8ceR*sLr5Kawtd8paCe$x@~F*f_4A8xNqBw+(0(`o(7985izEpp~$(Dmfg zLKxz@B<6m_R+)8k5xjWNBj_GvShTNtM>Fvk|1%+QjVHPm5Vpn?U|OLtsdJTi!#h)8 z3G;PPX0nXrXT6+9v`jXvj!g~E6dxtNUu6Dr;h#YeQNM$0GT)frLG#hq-xu_tM(|K< z)NLcXBwG5ZyeB?FamKn;WSpH^gnN0s6S1Uhqct_9L4LJ2J5XxS^wY?DGewjjTyQNO z6{WD7+e@9Ne;UZ|D^BX8mL1=Rb)t)kfU-v8Lt=a;cDyfe{I--8r0LN%C)M z1w>yb4_UFrl{`k6HdItb#TaVNxH)2O*4$Z8f+0)Q)kJqsP9@lJ`7aw zOE?;aq_?swuw-d}05XPto^jz#80tzF7EL)kp&BkVOEjQn_L{`gXjkI+C=M`+oaZLc zP8DR7i9ML5;bW7kGFWu0vQ{gec=IqTwD7G|9hcSAu)xTCs8ZBJWA>ZkeXi9)@}6S4 zF-c}bE1BPh(N4wbRK1NaL-PK!r-o9h3MF$uM1t0{h(M}+EuWW`Ep;C1A?!hXP6car z2k-nnUv{ZKb<}n(iydCN;g)&Vn6O&Z8$hKinCD)_o=l^8C*dem!!y^SR!FC@)-Gnn z5gm6K)UFglto^~hMyWHs^0TIxM&?CiztH_W-L+=urm_;rvjW|o6u?6)yv8~~$B;@n z$f~l9_)8s#;t0ykIAh!ISLD42w>-$jbEz*%2*w| z3;8waRDJmA_`AILy!tU9PqWjcO%|u*=!zGcb|`b0|BEn@1NrSCuPzLX&7-yW9v zkAzaeC;MA4;HrzC@&TZIG@Fus-R4??=(85-`e*3J3tn-` zu)BVb)S+&v-jjfS>?1#i7>>7nFm)68x%) z*i?yvWq8V@)kNjyP4wS^TsXe5ti%~T>|4xeeFjHt1~*7*iJx@1#o|nnthC`QdFbdKJGzuu+JcCI@hU*g!jt>i&go6*<{tylXe z`SEz#0*|li3CC9)4R^kcke1Wm&GSO+>ZvuQ=W7z<;XWvk|7LkWRrMKNOZM6`W6U&$ z^INM{_0pKyCK}em^Q(Xe8-cIB@Thd4ZKE9wp@~&Eo2))XS%p628SBT+wq;Ek7N>N{ zlNcg=dpaczlOuECd}|6OKYB^K@pd~B_VI&SG^@^?MTCAt{5FXZwr-DbEu7>3sC>#{6bHg$=1%NgpIbO1)>t`JD7y zWdIZ?AgFb2`Rv1Ii)UTRGal%w@Os43sW=_9xx)aoT@AXlBP|c>A5=vmJ#XRGA0W66 z^vfBPR4Y6*TEPHE;{R}ZJF&CVA*jmToxc&Hw`Nr3>*;IRQ!AjNrglVK@Ks;=jrZ)` zdT14?6PUa{W+cVDaO2NSiFO2I^ZT)krwzwyHTlA{4abMg6aULev_|<=@&{iZ(h@X?e+mXTJkge%jw8^-Q&}{KU0_LoMBM!zP6{B}D;B_V zeaKo4C?@?}+cw1cUq$bO=9$ErA>k(Zd0s3l=8Am$F1#V=gY1m2UiLzDg2xtg@p@g3 z9gl<4P$2p(KC4pS0WGIWV zDudJ&bWz&_9vv(?jme+_QZ}ug$1z zE=sc(Y41tA*}GdIOTcSS=v>)?I3V1DxgFZ!Jga%nuWoaza;xEOlWX9x@x(v1C zVGYM5-OC1&BPJ0Ga`K3?{!XvEFB!CVHa|5BRP8{KQ zPj&^0d1F-{Ww7nwyL|j!ttn2klpD2r1>?XHXZn9hXc}Jv^4K6zO@+sE+f2!-srM-c zq@8+!k@ND8wQ-Mlxo@(c$wy%|_+~kZ%5kRRZngXf9yEXXJ!9>$*2r@NcMsuk7Vfa} zDx|ONrJO*`vIg@sCq=_HTn>}AMw(n>Ii>}W^F7)u9}s%#JFc_Pyx2n9=EA_R{XDLx zF~Q-t_E+Guueaq*1ei_$qJB`6oM2$CmM_WC(7P&nunYVZ{8U19)@+HN)R_s}=3WZK z?d9TQ*0#oEx&ur7NWKa;E!B4?*srQ$@X=b*Yh2k+{rw^eX3~M*3Z5~(wRQYJRmOF6 zhqX{g`o){~UI+${v}1EQ3T#DDCv^fE-$iQnZegt_3Qv6zUj<9sl!j%^@*#ZN^;<*2 zCG*j78lErJuskK~Ghd4&>2SdAvIL8h(}Ty2ifQ8vBQk(n7C^M(v31EpHe+XA(x+Z( zRO_3LvIvEo_&4ZkZul0(fF65}y>k|UcVfbUfkywavziGJqfFfmC-!rIaBT8bz}fVO z4Sreq10@YV5WUW-nGg81nsheP!)L(&FQ0#m)T#|n_|7V6V40B~@9{S);&_8BXA;sTI z)h^XoHHi6_IQessrp^BNNKIN{DTX^xMyBkiZ8IM!;5QzOKz_P#teQLUTz0X+@E`ET z_wFeTDi1rTX^X>Vb|RAVRu;i&$_l59e=iDxp8y$8@ot;zm!K#fKx|EYAXl|7*yyXQ zkt!qJVXX9I5UUEm73GC7te2($0yf$oeOYfuk-m8W7DWg5(kc+mwHPZ3^yZO_a|7FZ z94}vD;Z!Pn450fNIV-GT0~=in2BNZpSSz=lG$Zpe&MxmO@|Jno_IKapvq0(>pmqZi z>wcb5ig+VXig|;OzN{(!>=X&jNLra-DkYmKMtkPSq%NOv)?`LS!fGx<=+R$Lh&aR$$=b2@y z$8C~dqqy{~Z9cDny3MTX~ zKo1dLU`JaIp?O$YGg@8E@hy$lBqcccRTmu~nqU4lHy=0Ucfn6+RC69s{m)kN`k}FP zOaA_(n2xHCrL=4sChbJ`#)Lmbel87=9m|>Y@5|&nI;dP*$ z*&95^k`~?ootAtd(aQ~h<4h2?^d!FN4Co42A-|&{8y?L2!h5tc#SYBo%U(>Q`gFa~ zCV3L~S>g@S&irEtsxENjflxfi>z*?BAFw4M0gDB~M^O!IJQHeR;V|s5>28BkY9>4z zntHvOr8oRRNvkFrD6b&TIf}f1QM+qhXJB`#A$k*8_ZtVg9%eg@sxZL%uvkzcU(X8B zHJtvY`qiq0_T=PqF2|+9`x;QbU&ZNYXWU=6E@rBu*MKV4M@WzHdlvirXNy9;EN|=y z?G0JJs0%GEX#MlihPiGH`VF5D-jSEz3)B^*7mz!jVwP+_Vt#ieT{*}8W0wLKS)Df^o9>QRrWm4n#Kji#GvB7`7}Q{GSyHJl<;lrOY;B9eyvK;gQS3(w|HD$G z*-%^Gj6&N(ORumm9X#PU2@ZXV1}=ciW-n_sG@^Fiy`a@@QI?HYW`q`$8|X)dB#$Q( zSS3rN!!*}cKB<{VSbrX=A^Bl*Im%Fy6e4Z&;m0*gwdjxdXq-D!Y;WCo3HrrC3nk2m zt9?eCFm)vHt9eQ2snTtiq&hNz0Tque5Slec8s^w`nwg{>FY3HufKhUW^@U)j{Qua| z8@Fo1&LS-&kOvK}jE+7gD+gal9BsQ&$B=#HY?6}L?XN$e4;qQ#nk`xoqaXus{2Lq8 z{rtl_D*CD)P7|lzd?4r$KQhDL=%O74p{$jfljEv-&hycxDeGr2)Vrw#5}_dR$4efl zvLNPHQ{SQ)luh)7GiVrZXG#SgooTsm@UxV2BL%>3(p35f`()Byv}=31529SrkovY~ zJ*MpOeKLOBd~eWoX?P%*0?Bm}@xA7(r3di7Io_|{I#!v)X`+N8<7@E#_G0CgLvH@e zaKTll#q84RHdgho@WK3rl05flXp3%El0L!YkwM(jhJ5}H7+O1ri6$Hc{xX>#?+uY#``es6*{5T0{x0xRYajtlTp zUYQPk`!?%kXzBd)i;U}$hcdftHP@XK4ZqybHZ6Yl@_V*S7jgKy2y!@H;W;WCNQFAT zt-IokVVX;wyDWn8G1;f%WrCS0F{jBa%pCf?S`clIHrEV+}9Me^AwWiDuev z!nU!Wj7Z(UYjQm5d77;`j)fRIw;dI2>AI9d+p@+Wo--=l4st)7q;Dw8yoVlGMXuy^ zbB@~|tWX&iv^RGk|M&Li;GC&&JuHFhgwKn1ulIM-ouPSaBTU0IiZjNfBh8v&h5dW+ z!JzhBMQM?M<>7c`y=xGRJ9M>YVm9Qv3~{|%_0g}uHaf~W(ci+9 z_FJ*;V~>&{eDLD8In|sC!!{=8AKvez&R=qqrzFvC6g_%W?gh5U!N2am0gb#e7**DR> ze~ASvIaHWzhW@4l%s?+2njwjflqUE2Nwp6C?SC&r%2&m^re8c0{-CC$`|q|otzbZA zqE2zW>G5V54v3qINL{DP{68Ggx?c7g^OR%BdzTxcPM^|&1A)MGg!E0l%3->MikWg)IrDIM2aJE9z-^;_{F z@UUX9sH^wP!0(;ssE*Hq<$l(4e8)OdSpi4l?!E&ST(Jrnbnuy8c9Y{;7ej$_jIi zF0#mq9owm(mNj*Pbd`2X8>=vRx&xz0x9a9H+j*D7YlAO1Xo}BikT1Z?o zyP7R;`C$39`-JUE4BMboYlPFvb8?pBH$KI_$R&WPTdX44qf&yphe)b(GnDUr%;1)PDOFXYaC%yRoLk zxl2E0!gikHAq%*Z*gARr!Nda1;EHUi8CXeks z{Df$>!7mgSrqRzY^O|a`u&9cvGxuix9>I*QMAgy^=|x84uBo6vo(;{Z0#@nbRoGru z?%Ke1!(@=&jhapfNNMfX{5O4q?(4}f_fi~1qB;BZ1WwDqefFmjyrs@*60;tNINqB*vG ztEB-q6(7&8ZCqcd#dI*WfA{IY7ZryK-aj!_^YI-9+24IcxaVBG<7OJI&+=QyTI(y7 zry5rqD5m9LJvI?#a7Sz>q0egba$WO)Q@0Crjase3fho+MfXBTsRMJf2QAb#wZiIoGGu>%lJeKf&M*CKm>kAEn2<*Fwu8+HD)- zlwo^L{_*pcLl=g03x7z4UhSoQBtjn%r}9?xkg@4H*S-(Y>*@|yV>4EJ9BeRMy1Fl& znkY+UHpi>fcP&_|R!Ip4tL@Ycb3kbxOV*9w#5?{8;~MdhiQlfSrq4CyfT{WO%FX|l z9~S@m>vc=;#YT;2I=k7zb%rzU!PxA~f~p{H2<#C6x3X*sIg z<7I)U)9@QJi%DLldlf5M)5_E|kkp_IN#z($@~fM=GdouEco!cJH9;GL+nj)41LLb6 z;Hx1Q*o7dIwL=||)k$mnt--Z~-k)sy0m>|%EKBV(VH^XxId&X5D*kG$TKA+mS~G$> z5&&{LC)cihEl#vOJ!$Utqt=6A-rC2%XTC^03ZZL{$my(53@rU;)2P%U0yc=iBCz420 zgt>1x{a?#DyI;dd#(t*EximF%40rw%X&cLRJJ{cWir@N?Vv@l&=HI<`0c)X%@a9&6 z`1b4s-&>Go%X?gw+7->8r4zNnn|TAaHRENDq~%lHc^S+&dyl$U1EM;c_=t&)^_nzL z#F1yVF$9&Cq9$h)k#_DJb7e0#$(b)}4)>%Y1jZkhv;@TUQ@IAWS0WU<=XTB-d%PHa zO5yp{SU5(ydWaQGlr_$8r)oW^^q{gT8hH&2Q~82n``n%7B^y4BgRN2adb!-)oWr>7 zFG5(d@RkRyS*JWjaK=Pqv2$ey5J#^U1kMkO)~t1417+=cEy*G!DMqT(8GbKVyW#>O ze#OLDIxD}+_>lcBWY^P{6B{A}*C5_o>A-sOZscmTq*#xt4}Ema+SQEpSwo`xB_++; za)*)iv%)lcCw7&?qt9~Nd^k@pj3{THBn!Mnr(hEQT~2!NrJOP+QRa5JUYG$ZtUhG@ zOX*bsA~;NyyG$fF6Gg^;LF%S;S|%0vk23$gzM<%9ShEO|Q&jb4bv}bxp1u6)H3SDW z-{+(nf}5N0<%y>F9=Z-`dFb4?F<0?HhcxM5wC@x{^0R7KUu57O3hj(@Hqj7NH4eTJ zUE>*96oIplWJ8RTl>_$mHKI~>Oe3~0(#0iLxb-kC2{1>X3$_=L)Oc6(=ftmq>o}g3 z`jEIbvT3L6{X&EFMRG0jl)k(4Vw&yf+2&|viN-o6v)0ZKaC=v4Z@WR-Pr3{|Jc(lds)Iim?^(m7|YiQ4<|2(}=j#bbpjiGQ~h`c6^B)+sk4W6TL# zR&UzoIBv6dKjmjxMGr5PIrA==S;g#)z9#(YVx^tqpA z>XH2F&XZ6|RI3jHd9#@VAE@7WMyd9DB601g!}k;2#u9tJ+B1;j2{OZ`zc)_j!le ziXXe?`cEAznevYv4TOY9c3hYtzvA@y=UQvzlUcbtTu4tLo65jjN z(8IMOpk}VO?38#Lu0NON+Zha9|8dBe61d@<81O_~gHmw&yoj>W!Li`7gYfdDL*Jo) z&NoadoY|}TZt(rqSXj)5xtM~>%2$wO@%hjGX=vS_<6mY9pF3OS5?>-R$C7-YZ(i^N zUIc0`$e9wvw|w?ob3a|+c(okGQB{vu>ONlUyViHx%hBsD96NyqUDVm-TN-kgmfZwt zzt5B6stoc4@Zlc`#5Qbt0u$IH)oiQ zUQJTxi<~Fe#bSZf+I(K+Cbd#;6`+fB9t%sc=#krYPP;8np!EF(1D@nG6MYqCD@2kD zg1X1`586D`*2AFVmxsX2O@?UaOkRHPVpLW;#lH?S)kl)@;)~r+I;_fo)!L;d} zC>|O;$sxTCb_2e*@($4M2<5a^c2`>8-yoms!C|u?xb6X#zxCGaHm-V2b*leNRkhxg ze;Qd}6l$k)+L<5ZB(I=6UETZi&_BL@bELjSI@>SbZ)jIq%9s$7b|{W1w4QbUrIUlL znvHx>|K(9f0&VNslbbTl_fLY;wrzD=8L?fnu_%sbZxAaQVNBjb?T_zoPa(Db^RD01 z5Qxin_`xr*Gco5gc*15||H-R_eE7gKO@+i|Rjjc>nfMY1L#-oc0b0(SfnGAS_pM-(+1|xc%$^yzLrWS@Qrq zExs2GKSns;=BptaPo2AYePpn?_i#n_yI9b9F@OH56pnwBX!ZG2=&c`7N{5xt{khfY;`VTa%c&trrrb`pYHr-+3K!=IF01kqdG0d3Zl}D{;3^wxB4E%LL9ZsOll6=tSoJ7vPGuM~i=<_*i@> z0L9ZbbQab*JOCv{W$7Tc%atafd|kgTF(5OJZHUS`J`_g5?Yt*EE`a zgG`PFe{di>Z|nTo4*F*-hwWiZN=L-c*v3ISff$v&f1YCFph0een_~hP&*L5VXb>=)> z0lr>x;LYi$FC8Ie8XWAmiLLv)TF{}~hc|U4$Gpmi!v_RIfMua;3sl-Yz3=QVC{gph z(BmTtxAGCOFfdmcZIkkS3h+qEq6O8&?&sY0#U;0Lq_82>DYBySCEullwwN;9pB?YJ z@mF9Pj(>S*?~4Nrt;G5CRt%ZL;b5DomOIln@Z>o*1{i0KGN^|1X<_B2K9ixA@|BGs zsKrmeTDih))mj-_pwQ{@Fn!Ifv$wkP;)yI0G5};y5O7%Dg<9E{*5zk>K^-B`VNx)Y0~gCz#Qm=pg>!eupl*`2FIhQx{0Zpwd?$5r>g zn6F9yEFm*e8jNrmg3d5ziZ!TWO#3bEURrel$rV^vmK5*pQR<6tBTbjf_&qx0_5aS>GPV#e765y4{Dub)I`;qAaHYU-MYJl$M^2PO zOjLr9+nAj2;DT{IX>?3z4_gQ@Xm6-;2hu>fUA}W?e*M>q^QPVn+lk1IHbSY`!-#@e z(1Ha+&}ARW=C)VT=HK)}xfFvSjQ0wZl~R_sMRmb`!}`3Su{@dC9j)46yBU&uHOxHK z8?Jv31>Bz)wltxVTZ4f%$o|1#AksA+zKD6@s})FBspiZ$XkGr&a3b@R}BjfBo}O4-zD_8&QSxd;Nh4>;|(J}USfSt3*Y&)+9W z`ry6LG6`%tK~4{ex5+bj@~K-TXmfuZwv17}FbhiGG?}K%A)et@&m0e2bKL$sU&&aV zbsD7gSuc&({Sv5Mc6+gdOfneoWiq-r0$VS31{V3pM{}fH=-Gr!tQIM%E(mw*=hL@E zbxT8blgEg3i=i~X=?h!4wb|5pF^m^qI_C;1mm+6!)rw`)OO-X9&KAWFq?jo)hwP@! zz8QXeV!Nz>tW5sdp_2j>0B-)kI&+0$6`0Kd-=H{lY25}ijlGL!$5x_R<)$xIIhYi& z-iE!T>D9L~b_u4~$+a_D8Cj1N2xdQEBeVh*du9vI7wb+G7CkZ63D5fReqcTD+n`C^ zfhnULfdv0j8d9L>>V34*BW05)t7S!NxZL7gkIuz|MiE=$Mt^qUONS-`fM>34gTv1H zaJ9pSlfOg4>DEgMK~F)23Z zgSWgU<9nYV3L!)}R*YNG*aQwdQ0bt=kpc>0C}kwf+!C8&)YW}Xic0MEnC8H@sOA*t z@*&NK)?_@zPyD&%%b@dz^(r1O%UoV1&c6BY6Sr)K?c`PBo0ondP7A-f#eT};2IwIc z@z>XlwoS#rn<$XX=5Qj*xFvO{+kwI3%-hbzVs(X``1fs(9)cV`n-*mBn3@pZ70?H7 z6tJLu5Imb)bI9PRmTl?s(IiP|RjgN6pdnM)_yp?TQ=H1rh>(r0iZ0@%E9+=H;_ zzs^N~PAG!lFI*VM9NS&!r|sP{CgfV%F1FLm6+X2)8~%pV*C!851uqx|0JOq2mN@56 zgB!3Iyp#WM2CzaOD=8|X+N3t_Ci1c?V0268>rd70O>a^^v?G+KHi(75-##B-iyQV_ z0X;Y3*0s>dkS&uyP-D82wLL0d&0+YWGi-S{m-zf(&S;zp#26-AU)Qn zP#K83DfB4oS-^@oKW7<(TH@1_mfzMF=_ez0e4;3FDQX!woJbf3n z7iNPqs?{d8MQG#tA7F9K;S|Z`J%0KQ`q#OOGkZY>tRU7_pdqJ)%A^K8z4#T_`gW(| z#i942&gS@QuP9fKWcH|=D4@pbm;BIBxhT}!OuG~+NfIQ1;K??u%?+?q3(>nLZ zHQGC%lfHK0*4M%0{6&sy>^XC2IV9;uGoZhIrTiC!B$z!=ZC)Heap+$;=e!wj*%0%@ zPt%Q>S(4D;8?^|bAF995!@E=ZN+X>+Q9ctsc->5slL%uf-ZY~1XWi%VOePz7a($!b{ zC)Nw|JlJ6~Pwifb+G~g;sWlj`@}gZ^T=jWAVI|RFN4*PAW?r9QPM5*`bFvxqKWW&{ z$|mu$E9I#wGfRVmw#SRS&v`lq?ZVr5OTACW&Z&mr%Vn)EhqtAGV_l_h8bJ&3*avbNQ(A)5&ktI&Wt`RZR?fnyKa2K>gita%oM7fG*#5>z(QiSYriVAuH`P+)oF1{(*hyPA}c;B3@#K= z;DXSO-$e-2g*L5kOuCeeyHUF(bBtXw&>(pFHexIk5Yxxtt^aTs)(%0*V28HFM~)-8 zIpN=I_`86}i z=ryLK1pkM86a(@JAaaAKTL7Np$W%?(lJjC$c?#9TP*P0ZMM6m7O~*YJ)u%Y4VOb+2B~k{{l!!ptq(4T7HrN`XnyT=s=?;sNcor+ckIO^UX|PE!$$gTYp4XOtRD`=2AM zye}aNKq_ZbiTZ|CtQ0KpDmnDXLN6rZvc1WVYrmK`N(j95O zO%IJ;8{gZq^UKS9skRErl_^Yh3@$4r6o2!B4SAAfDqv zBuJ-y{&GdlIz>HuS5K@;^cTpg%TY)QLp!y+Th3ipx@TF=HMW>^cSJU!cWMLA{Wzb> zr4?lDE$7}^rm>t@UZ8$+B2MZ}yTA6%5na90Bp7+qz$9{oMG@BgezQKxx~5pueu{QbG-+H zB-Bio=F$=rT5E3a^^)koU8*vE!)-mzucxS7+fOWP#RVPnl72?nb2tGs=atuMmZk_= z{1WGy199&`!Sfg)lq0rVYAd5JMySQNT2G&CNpALO;>kNzY@N{x0Ks@(fO-wxEX6Q4 zfmw`vBM)cNOe@7ub?oT|EZ&){;@UT9WDxr=1>|2A2zU$SPUYs^h>u1+S1#rdRdcn{ zEo4cHjvLL>LkaYlX;xmOYjmKHWSAF}?Dk8}U#7lf^(h=y)41Q&BY_Nn6C^Al6l?Sb z$kD+GTUaPL^3bW-z~<*ImUWC036Ig`aaWhdAR@#Rah_LnL`z8JSn2YCLWEeAValu) zS&q;O1ZEeBJ%^fm479zfKnh0qxjJ)gD>}%SQ8u=Ei|;empTs~AN7wF%)}Bf`BV>8B zRn`{S`7rCka3-dm9@cFJ3S081sL(kwSv;Zcs4^L_`3$k0hp%%>WCP37sd(qZuQaPaZ}Q|lk1}9;GR=+qPaLF#suY{dJc8+Rb~Sst`~&c zo`?Lmk8<_o?-_iw`3J_nUY}UBAl{IgbSET}Cbe61bl06PxwmEvyD4@;wZVo;kp(dAuNWTRYMuGhOOn@RB-K%Z>=&PM2iZu` z@hkqe&`%%Zo+o8R-cC!^Pqi22F&a&;Rx6d>ayXDR&+;h0o@`!}tUtO7{#FJ)T5joE zKDe_MG1C_PQpx-=S$mToW~IHNrI(;rK3OnL7l&mvLF1rQ7`cNs3kIZe`PK$L*im9( zfi_V(UZUA}Mr3+;>X_V!HERX@cW2b=JD05pKtRE24!HnTg5~~ujE}XRUKlmYqBbJ6DM@HL`4vzK+j5Q<{0~AK{AwRa5s1sR7#2w6 z#tgAvIOeh;S)A~T?u3q`UkK-3)p2au_8@1kEg$Nd6PC&cdc_N1lHqa B-n42+I$ z&n-FMo^i10mb_ZkkMHaCxT$Ju?#*aPu+$AH9(Rd2a@zkEPi8w3O@Fc6o2;QYR5n%o z2H0scKXy)xh zm-g)G>2p#Mxqp^+nh6!PuP%!Xo2k2s^?OzdVz5BN=|KpJxBNu0+%caYr2|`&KSl%D ze~Ya4Te&bAQ~Ab=y%H8^>%g)bTP#WuD%W2h%7G5R2q<+g!TM1vh7#4dxf35?{+^Te zT)p*zzV5{Kyp2yLZ8$Ro)#;YT3`p$?(;Ba&-(dkSp8UgSsJm?0UzJE_9)|w^RRB- zFDI6eZ1n6yN3a;${ErtDI}ycGAO^R_z+72ZN0~DsVUk8|FI9__!E4pDFQ=r5p#pxZ zvf-tX6Q3BzkRaFX9LdxU%ViNc8U)AnKNJN#k7r<=3RUQg%uwk}m-1TU3wo=@NT1c$ zHI(s8LBf6IZz4jZT>Q?5Pd#(Yd6U^6)HDb*$TQL=(@tB_w^P@uRaJb3Z>)UljqM7S zVo@YI=Kb3$JEJ-UCK8b*XmLHT8P8C>A>;(vNLdK|so>bzh@sQLj;(xx)0YG~B;EdO zf_R+83g6z09DygWu#2|J!)aY24tFBJC%ifD;=n5J1Rb!rjfWP=7cr<$esM*ul+Ou& zEa>HN$lE!cR`123f|k7#o(gP+1<;(M)=1}{Uvt7zpOy5ChA9SEx1oNAAs=PS-4lC7 z!;+fc8)Il^SkA@68Q9^49KXInS&JnAP)B_*?0>YJ-7mNj;F&HStx1_eCCavPG~5%g zcp`fL301z;oX>zr=-;3yJ&Tfav~m@1&fuY38U6AWpXj{0SCzQ|4^@2!5=N{P#_=qsO%~y0!#S_@ z_mM38tBN@5&Et9(ek5UuKi%7E1&Ocz2?v@V0q)+sY5)os@cV6oyf(bqb6J&Vq77_T!YRx6>AF;3Hcs;*tFjumw&!XHyFJ zMKg*Tq~Dj+K_(w0S!>NJ`CivQpdSRA!HtMwqrYfbJD6;osal$lfYS0xe*n`e z->WGGAoQ51eiqAHzc{1=kh|78lbBiVzNUWk)@7LH(wOIdSph8X^BbynTFt^_)a0kI z=7fyBIxzzb6nFLCTq8Pn*u44H;>m&wvz7lDPLGSMxv8RfuK5uZaXSw+36Vmc2Md$W zJ5pCe6*QjUeO#N}#iZTOmY0k_zxYrmH3&&&6`2pcXn)bQ%o}WX?L(^kPcnFq4H?dF zi+EBiHre(x341|K_T2QlhFLsEWmOKtg#e11M+|j+Ul&AHMXG&niN8u6I$kFbtQb2z zXs5yGoZc$9A}z9tKV!J&#R|v|t&C@1o?1sQUn*PCQSv`ce(a*WHR)mSz!%t{^P1&- z3LHTD*-+BNHm+vfXvv~5+Lx_8S*kRyv$`nvY0%MC*EJ_%f^qSeY})*>bq8H`YS-h7 z%&lbcWs-0CRm!6JrNzn~D!phul+Na)#`S09T5HbM+B1?K`LF@e^)-BUqiKYKj~&1h zLK7^szi_iqF^VnMAsY7sdj^1Hc$w&E2U0ec8(eBRRo1)X!z+qHilZbcS6DBvR2a^# zeh^x>WpKp{zf)_-_c(e@6y%hw-t|kGz7AwIbK=~qKVTJ-T|%%{(717|T^OI<|_pFH-sFR zR(|09YmmEeC#7{4vFG+O*emvu$Kw=|sl%`D4Q?Vhb}Ym;(5+(rKwFNqHw(gKUOK)M zHs@{YTCl|y_k8)y!0O0hg#vl}heI)*UPpD^{LtJDx>p%@#d0_LXhZq{#LbVQNk0{<88DUp<968)xQQ zp%KRI!hb4f*Ffm=TDrxzKAkI5I*TDSf+b7 za}2dyb03=SUuSGio;uS`%!u>(N zv_xTaVM1~=usHX7i}>rmoBtPM{~6Te8+P%cC@2B~0wN+MDosE@q)Um4^d{14q<0XI z9+JQGj(~vFi1ZriQX{>C)X+=lC6G`9Bys1R*?VU1J?FgVe94ytW|DcH`?>FHt@T@K z;yV)zlAD9o%Oi2yU+W5MMcsY>UcynD10vlb%&l6@G7>H`6c?P{>zBwg`D=Nl=djxC zuGw_5e`MBkUlRTcuwlmct-tjeEa@8|sw`pJzefYPN)x-Je(llvHI9&N+>&>}WSwVc zvWYC57-ua0B$R7XlFQO4-8>-%AqR1c>E~g{Wc>JaFYpi%a5Y39QBURW4}t1VQY7bvi!@qkqR z?a>61V=wZD14YRN{6HN66NEBc!4SH{N56GV*#0+rwxM#X#b^09KYOtr{N|^lUFOrI z%LAwgr@{LN=3g%S<=lD)^JE)NFiyxAsQLo44|c(I-A4p*5uSw*rXY&;%TL^Xc!NF> z`rDlYVvTwceS z6Xe-3JQCQr-Myq|@N2rhquANkbmZz!vr@%#Vf0#3NPHN0bO?s304=1=oC6Z60=&h< zSu)-7yCZQo(xS1|If457P?azB0@;xW+TE%5A%Leamd{MNYN zkjg%Fyku^Q%9*QV(uEG5slf!X#({(1%`gakUq{C9k4#f5I14x=TLnoaY<8?1ixlrb z(;<(6I1~8ZJMYAAQvut~*~lG7e6{FnSA4zmtisW^W0`?f>ga`U^DM4-EP*6Xy9H~z zeS!?bYBD(aaHJisBz>^!-prNzD!79^W7a{RqWZe}*ldf5D*`*F3fjD^1+jRq&`HMM5?uS^?@71PTV>Yq^#78f(q za5*Hn>^~jLxTQFvTD|_f>uE$E(_b(@BX0_11?=Fv()pW1(G{ul^4a?!>XT3Ki!;_8 z6fl&r)hZ;@?=P}^>SX-s-B3%GYgN1#uy(ss$OXlm028jPc=n*#u1=R#(PAWtO|7xO z>0)8G@#xW7w?%hjYiT z;B4RCcn>*-IbS}1j;xQVKJ_nyHm3kB9v<<0n<&E}PfZ-oLf6&(#BJ-t+i@P$E z`unJ9_tCJ1aI8a9yFO3^$-MQS*aL+~);`mdU-V0mVoQGKHkv!q`+5Q!M#Ws2K&qE? zg4oD&0?y(G?&N$PCzc0(J!ShB&xb<4qLp;nnS1)trYUPUP8Oe+H5~ua>o(SsPTmqW zeD+It5)w&&?L-{2yhjKFzrpOINPS``c@-sOy=-q|icT_S)SW9%@bdemac>{hQ}%rK zhrKd{aUrfArr|v9WN`=Gzp`ZA5T68#f=%XXf27ZY3xQuxGn=;BQ#qeJx9~*Nm zZ1ZDhe2p(3>0L-Ul>N2B(7CLw{gl_?8spRsf=?K*1Yn^V{Q?wiYe|U zXmrP~!fKqooLB+DCNwbug8GgIBbwB( z(#ko04u>!k>(*3i_x@Gtff*yI$rpdNlPt}F%eMFgl4yN{>t4wFk0)9jGi~nzu(P$! zFaHD~H_~I(02rf0`Z}FZLehhPe`Li}{zL=Rx?f_Myg5lDks(0?-(J7Lsa>0cy>P); zYN9+-cXQi1Awo9YIKL?o{cHa()SsXLLED4)1}I6^R33^g*|FiPTM6Z^!;f z8Y6y(H!5>S$k?X(!6}_S>s-{dm5&xpgjqKt_I&lVkJB|Ek^5Qwnu(1w1+m=jBf)l+ zOx+O$d$ga4^s(;0%mM%{a&)O%DA-})j_9g5=~9aT!LIU;Axtak0;XdRWD``70fC)fn$`0G(GkuN#Lt zEZs(S5btyKk`jRuy9#|pPVZ}43eZVgi??KxC8XEO0ZIb^9{ywRE7;9I$KIdpj#$ zUPpvUFEjtwsXMJnI8xr_Z}Q*mFSEFpw?nT@13;TeUvKs4Bv+p~E}$u0Y?*c~Y59ob zTvH{LN?ea~n#^O~?a#EqY640o8eQqr5Ny!ZAAz3-uI=zN2nVMR$BfbU(3>M;gtOm9 z@iC@g<)eA z{Y_5^LFUrTKs|u;c$-j__HpntH!jSH=@?@`Lo~M=wYzHU-REIJm|(#{?|KU(y?VvW zM+%Xr^2KH}Y*y~c8T!eCeZSq6Ea1f|UmJMBJ~^9t(H@9?OcTnbRPQtsGd_J4tl>T; z6i{VomDudhJQOiIQ~D;-G&tuo}TRT&@JLElazCm;k)NpY?aQ;P;o;-6}XKTyR z@=Is)$|xFdh0|CCL<2DI3G^Kx7W*_>w(eZcM8T~r>yzGO*LZGpi-$9Yhhh@pbII9i zKV3PycZ#5KTB+GakFA18u+!Q?JjOAXFAVB2JM_st>8Hi4-%^W9S%^N#JOLRL{ic5D zk>1F>^Krs_s5;d|isZEwAaTf5WX`J&3pjY=G{;qQLz$C;nYyI!cnOAN)f+}i`19K2 z;1A`tzInM!OGlPr0*cD;Q#UpNbuXGyRsr45To<{I9n;I=mMfWVfRdN*W0x93pjJRK z+=PTtNcZ9{^2K12+TGFdoaHQUO9>m~QHzzC9P!kKM2H7z}$#6B&P z*`km~AKoEdV)126VlgSTze_|`OFdG?bUKgMWj9|ed`vsguyvC=O{+~b=GXz7^9y%Z zO^?!}@J)Q%EuTJ{q-?2fkr;*BIIXoT#6$mUy+o~F4IlpW&%S(>!1ZRa9-@a+>3fL> z|4$H@W*a3H)hb)${5(<ydkGe7w?bH4-pw7Z~$=x46JP0xyij-@*XS zhjCxlD)oAGog|6RCMtyOrX`B+Ri5pootVl1oY$gdm5(gi1XJs=uyDvzQuBNI3cb%W zu*QSPyAU6A>C)XANyRYFI4&2J zix#MUPY)tlQbp&@(EzRcRee2Mt5vUZQ5FBKa{M_vtyqdxtz{L6{Io5<_gFY3yV zqde=uq=UZOpz+@X z9~T27pZ9+uxID2s?Bct-UWKXPVFXj`ax zRaQO~suKh#zlhT9blb45-7xH+rr!jO-p}nr(8i3gMJ+h5W8lU(33|MC5tAt8;HCeS z(eC0S@e3GRILwcP1<@|E7fL5o^tk6_P%&BLI5dqJ_Y^LOHz$x3v;I2pEP0P#*#7vqr1I-; zcO7p~Ike{JAjsufcF&RzdlZj1;7e%rLAeXpQyLjh$Q`+QJU={G2^ct#X1;ERW=-TN zt>x1P92ep194Pd>6a)zW`B0{ux8b%+xGinH)jowsk~nOxP>~6Qm8nz!&9fdzaE})$ zuo6Q&fO7k+EpNQ^h+^Mn#_f`5146jV_1U@|1xlQhR!jZ3gfwxy%$bS}wIi6*(EsOC zY}~;9SA|0tVaCqR1{;9msVSkyF!d*x2itfaiql&Mgp*k3^qBPyB!qLi{So=r(xRM_ zdt8=nD#GuC@#HbMu??yMxI+|lf;}RYVR@jGql?XV)8;E{>}d+-ce$Zl1ii;-t_Xlc z@X^CH9vw<;JwGQzpI&n8MaGgq_UHVE_m6X%J4M$}H!Bt=RvnuP%xRCrjr#Mi z^@)|*4$X@?ka_}i?cgXp`eZKgPh4%szB(K!aa~ZSc_|H683NY%p=~hN=Rx%vAZ8su z;k=TC7E{yNFsH(#K=->wA4g>*Hb6Crf9PWs_;KG>>Q~ULBB>R74W+42JoN{&sG=zOhWG zJ=eyt!Btmtxe|@Hl3Ye3z9**d`Kc{O4qwf}8PxPk3KQck1Jg+26ftT6H)q4(QN!HKW_NH{n1O{evSW?W9ady{I z;b#%Y!=VSHB5V%m=S3rJM&Is9OGl?!Jk|f?f58AkIq|WR!V4tS0TzY9D@+P)HP%l( zvIe0UYaUo6U3!rX79Zh@b6bt}whtz+*+~~tEnV!o4zoY3o3fWv2CFZ1`ybhR>Rra( zg#v*uv7*8o8SKY8g^&}NgZQ(?uwwc^EsI=R_j(0Vjw(d4F$*;oTPvx3T4yr`TG1d% zTpRvvvI&z!3e<{XSia+r*j@j89=e-(h8u*}7b>@= z797F`vg^c~1uNU-ot6z>8Es_unbNkRe>?_Nnwz{!DsFJeA5Tg)@}m$Y<85{XM%97y zvD*46DD6txIy-Ptv~j}rN12N6Pd|ljj%j;>Mp*0fqf1)n_Bv-ItfJ7nD-#9AQP)4t zPT^@ym9e7TIKdFQV1WbGHTBiZ&8&Cars0xOOY%x!ziSh`EKX;=oK{R3*Hi_gHC`O5 znbdu3y}a4XXtvpPH)71=dawQDOLZz{?wqrM)lv<;GIS`jzmQZ4c!K*0m`^`vtQkKu z!P_~luS5ifRWJ00fD~BbBMctM_=$r>hN?4^1$RhCX39kx@S}w`+r( z(*q^*AK&8O*1c|EH7`0+9z>pvdVaWnqDdE=HsP0&oDDH0QpPeDzXf zWf+(e>tfc3P5g3(RIai2X;X7Em=aAeGDtPPtrt0V%@;#}B)%uk)Q1qC4RT|9_kQm@ zyxjv4LMu@%KcMkW z@#JXPFZ;V{TD0y)$1zolob}?=Rk)bg%r_A}yxU_A^EFR3P16n2D|2Vk5w zxK808;b$j2|5GPNkAe4JlKpI3rQT{aBzJ6d>?Xq|jRdf!U)RN3HTC1!bVUB7C3${J z`=okwJpaFzb=zll+ujHeUTCucb&B_m&hNK>-tdIcGh|D zgT&tE&7--q*dc!Ideth$3}J)8vew|{&u9>7@7y8P&b8mnnO}vorZ5pl=X!^`kb&?eANwW;*5T66XH}N`BQgrm#C4TzGhfxs}|(K{Tvl!!0-dW-xXpI+yj|i zSZ?_hK&C8*Li7Vzb_LiKizd`y^X#v_{Q`-N5XIEa6K^^TJUua#wpgId7U4y3iqjm; zhAeb@tgo=|NA=h;EbrEuYWRqeP%T5!Q*M1ER2+Os?s2M`UCMdzSR6`PB1)wLP$v?t zz=W$sZ6T__On+Cpa_Mr$UEKho;qNPXha3KEJeX^VBQm3y39=mZ3i{8=$l%K&v$+#O z9_O!v4Np2M;YHD}i6?)qwBqZ;!aSrt zK&N~IeQSRSMFZVk^8>m~PvY6Ox{Jx#{MgUUN#zX+#bYb=D(DO>)A`SIZA^V(m?aB_ zF6n7e>e@Ba^^g5;@mpLT8N75Xo75SXD%`Ll;!Q|@E)5|U56CCZ02_2+Iuk-X8aZrT zH0~3YE9USq%6X=rf((cu@Tc47o-_oUs-N%zh_GXL;AA@a-~HW~yF ztonmJa3)qPekdV#>VYETgTY45xzhCn9_yydHo+IXsh^D8MH8BK&1b5#4#HX@3&47~^6QTf+(ha+B0h~ShsK_nl8!No|WrK2K zvEa~VOkxCQgo6H|rzQ5yM}DcQ6Vy10o}bAVmGW@g(zx~W+uZdQ`zN};Y%^cp$O8Bm zKsYUlreevt8p(>1swPgz=%3y<`wUw&SHhd8`S&;irR0@vJ*wT?50KABHtarbxKmZ8epym1t&nZ& zu#C_^IIJWBsM^{6;T;HC2)l7t`J8{k1v)T?aQ2nO@Z}=!bZz)bI>T2f>DBGck$30z zLSiR=y+%}iD0Cod)|v`_XsbJUqtF!+fhbFyi&0ZK*vIVJjvgJDX>Jpi1us*2OMh?b z11=DXhd4LO);4;Nh))UBoNwUUis#?&sa?C{c9sT0E*kFM*#r8Je}otux06k6jR>sN z;K$()cf)~pbxWoqwI&fM{>gU+rNGwJJef=t70AcmZ7yRSzSLd7&w$KDOdC*ul|&DI ztUuTrr4k7tk-j?K;Hgj^l#ZUe?|V>f)T8ebVRa+4r@E~hbcdpsMrUK7v9lZ!R*zJ^ zGBw>9^JnpY>rJf&E9bg@DODL8aeJ{&_`jrra;n1rkqVHQ>5jK+Y@e3bVU<1~ONCmH z6NorbQ^O=;+W1Vi>UJ{?YcyQ|^Dc;l^l;2^ST%|gzSx~`v1FQI4{lhNxcr&&@PrHK z_oIt^rae6p>(yy(U|VMfW9`2DF#PLf$MOhz|L+xx7NLMdWQ5&VwDeD3Lv&@OVR?qc zTb@jYsBK9-_p7#xgZdYOzhLQ6iO~=-|1=P@e=|jW6DVz&f?bI*mqq^i1Z320()I{v zphH7v+~~Ij22p&<6}c6cCMH%oBHr|&y?^~b!#{@t>p$)d7aUM{EvH^G%iAZecQ7 z_@bmc+Z>S8E7EGDNj153-D(JFS-S?@cYIVFArZivg(D#v>{eu2i|Lm z|5?gsp;#hYEl_}amdj>pPOtVZ-hQ@Cp#%yDt0x_A`vqcmR`a#}nhp(mPbQuFkerTu za1V7Y5(h2_+>g0n;2sNv`O_qtCV0L(th;AD?juJ>y#ecNMbFI{W!u{S##Fvafk5*X zq9(p+P)Bk&Meq)6pTf1oqJ<~}v~|prqoAFzE$OnXRW(2{ZH;E)MxAl z?&lMq!u^@#Iqe@_jCRk|**_V{=087?elEGQ*UxkF1)9U0d=V*5)K* zi@F8!x;&g32r@m%izq4!QfxzU@BS8BIG2=iAm9D)GeqGmP;Q&b>JHh7b`(k{6`?-# zThbSqz=zq)r@D>lEBwS`DOY?5r5XdSO)tGl&9u= z4@}5zO3WfMKs#P3+yTG9`XCZ~(2Dw4Vs+8|R{=AdY9H&5N8d+%duEO3LI|*J(SUq4 zYg7*o1H>_P%-nKHeuhetAE+#+Ml&{y%5o#`U=cunh{2M-Yeh59C`#?F|0!II4I`rO zw`Q>5z)&LUfmRxjFejqN5M7)HCXiCrF|tlk4439?QQ2V*yo+x z3~%ig+b+BC1aW#}vT=rI$7hOoQ}p30^3&6jPuu^w3=$eVXjlGYBq4%4ufHXPgeig*M8|m+nx9G{Ft8*mYAQBjw|LI9ay! zZO3?7s_trkEAY`x-HIF0cS~(AuD2394j>2yKI&kv&#egeQk#dW*V4R_I;$%6eG#!e z`j3nmXm@lIY)_m>QS29_)eQ zt*pR>OzIHHOnqf{)BJ3%{c~ z>C&@jD-r!00u|_;HW}%9x+*L$_@@8?<(e-0N9L6foWjTnW!L*_l_+tLt6ptIWq3&% zS4FSXfXO5bz#>b|DodZ5x~!wXeF zA$TaCH~_r!84&+yrO%A*_U{>qwPqKy{}P=^tKOL7x>Xkzzn{~|qID`BH~;s_c}bWR z2)-#*BrrN!KR(<{OLi-0oU`DZg;XB6oYK!_Pdq$4V=^E3nI|h&Hti3QHvecO_<|y* zsOi@VRiTr!o?x1E`6uQ5+?DXamx1hpK`?o|3L#rg5KF%<5~?7zvM1#`KNk8lSJhdc;9<=wJuUzJ9^xUTaHgBS943}4Zux)eI5CC$#wz5CjCU!B?Dz75XleX%+lb)lMux1)*- zda~_Bmx#n{rf3UAd!$~ z^ox@>>kIRD(!w=6I%>h$uVpsLwSk^pv!~C#F5HfGCk&neag~?$M?*^Z2r;{ zW0}ICA@3QU#$>hb_~fpMihvqrsfPp1vqf>qqCWPdU~_=Q9a3fzp4Tcb(R#%ZHdFD4 zFXUxGpmn?V3%}~akG}TP%&6Rw|Ap-G|3~2};NR5$V}MVAyUO(le;^_?L^x)L2Emyx zDWhS>+9-wp6I}jbVlg)OI~OIhW2ubYn7Pqqq&)9fNsL-ew`i@1;!LjME!j8wyXMF# z#AoLRkI(j1Y0$FXaaRV8A5;w-L^+!FEsHUG*23J0l-%By%SPH~tOJI3jzP@klvp0D zdD@A#|3z8Dh35ORP~=2Y`Q+3zcT(Vk=f$DflT!>QAJ5>=Q*HjkMPp!p5G4e|i34Qms;C&)TlY(vW^|37NsPV~& z)T%?r65r}rSXSq&yOUbQmq#z3=jit^d2OvP+X;KY>EBOEV%r)Lq2THAN7v^tx-6D4%s`2{jAio= z%|z?LB%2vSWVk@0YUbOVB(rBX%0{~~FC}Pcleu2rbu0e!{+Daa*j!73djHadCn2BJ z(kM?N13q-_XVkyY;w}n8%8?&hO*o8fX)G%7JTsEtjen$G$Qm`qZgf~P4G^Sd#a{G* zW@Xpt`$$ikH|rkvotvw&N_yNIM$Xl^X7@SO*Df3}Z}GOxHK>dHtrk-rbGg!9hBYhw(nS91cE*|e;e z&;@B+Cy(7x)e1N9Y~w_7uyi%f;fJ%gv#+EGS3x5gCGT5fOq)!FfyCIT#fk|3!EO0g zA*Gj9odpT0lb@4BP1EFr!rN0EDL3RM?Z`)LJ1FJ%FLk;bM@+Io~d(XJsz4r}M@35&zAhm^6v*>hVMrXtwCE5f|G@67qR}{JFhA#d~QssvD z{M7!ouFyTCxQ&?8Isbs!KFBZd57ovXqmFzENZ7>TeXnSC&j6b{WR}GMf8^w&@Vsd^ zhuW;~#VX36_gzkKMX_OLYfq?Ya{YmNjOwM{xi=vN&u}fUf|~?kw#t1<0nGP31bp5% z?9$X$sC^lG9-uIN>|RTfgZ=~QS>xFPw>&#H zc5MeM#grOM={kuVGiDaGq}A!*1p2~Tbx{Ps>pGl8`NF)j5yR_=3_~^j{togxoyROP z9+~a)gr8754>HIUgsKj6l)xD*yfvs(=X5diC*XYS@nr|?agFr#U@#(z+|+Prvun1@ zU|m-&@>Qk-Np_?HuBMS*6*&C6w6Ki{t!5>-D+}5Q4K~4&8Jc&=FR58H`$un(mAM-b zF%nl|Ub!wUCFHYosVA*kIb)*P78Ut5Z^L8^;z$~aQ&|Ph<2xi3`}s^fiz9m7dsqjxwRF<>uD;}@NOj(WcKX0`W0V9Rqw)Cq{FG4kYi@8%s!W5EyCL7H#w@GV*x=U7BI_D}ug_vK&(p~#?&ut8Q}s;0psy9eH(WW}b`7QG{kdT3cxVP^M99rqfu>PU zWpm{K?yc|KQThs#3z@}&EoK9Z7U%P1aY}Xbg zo%$alOOV$$zV4@4{UhrF^k3fl*&cSYN#s!%`!ZX*n%aB42#y4QIG-r!;JC?iaR6uG zm!6r2BHI(nVd8xA=D5&z z>FR1>$_4_%ebl#Q#@0Xse%&pyvh-09zRA-W6QSp4g8kN?H!Y>NZ12(s&yKpBd)#hX z53Ri2P<;Z{OsQmL=U^th2EQO}?I0w0P>0<5%qeuv#?pn<=4#=eqB3(>Wnpl*-cXl5 z)OjyF!EaN0k83K86p zyI}?C;?9?EH?jB3{9yFg@j~YdprIIlpXoey#u{_fiDuIAb~-j+;&>(PS~;0un?%%K zfPE8Dn7&dgB+kRANd1%a)Q}Mc9we!(-WsnnH7_rvN9?Ty{o+}Fa`LXK$NJ9iC#h0j zDTniuH0-RIkGwBIxWdA|pI}>TZnEx^gfWw;rwrXMVjiqb3DCcps2x-`3M`={J5ik~ z>c7Fojw%lb7+q<7MwTo&Ye1(EQDSL4BJe<&?d=8$R&=F@F;j`{2GwM1D5S2{|Ne!r zW!kH4HPTE5qznm8w9kyAeq+)*b?Bj;Dx_7v187~_OcU&dEah&u^v?=96YL*9apLz~CPFPmn8=6CQAbMduIz4Tsd(>Zs;iIL91 zIuQ`wD1|2jBJ)Dx7V4usxicR&bC#cTl=7nTp-UFUPNep5#(bL-(o{0UJMJ@OTX6cd zP}ep0ZZj|nZ+5L_xwNz=sl^^>nCM2+FMNYFfFpf#zn6yE{rs=%8GseCc zR3W15p6^P?9#$2vY0?0@6KRzv#1+wh8Fw$zUEKTe2sfh=Uja%3%r9h%MZSg)R8$ISbu? zSyN&a5_Bwx1*|V6o;RZB)+J*dse+1CJr{*qsa-aSiDh$@288L$AL~Z0JOrJI8{SW& zY#H62z91WWWA+H#sg!9_eEH7ZnDcuF{LJPdVzyo7n2wed%>xbN)o_&FE+XiB3~@8d zmVP~6>>=RnUfeUH0ihUqGJN51N-Of^7IVgr|LwSF>oTG8AhJYF>Z-o+TjQivl`|^Pne==H8jKxmGUrU^8E=i637mUC6!& zxFZ`6iBI`Ztn(Zmn5|-pZL^5<6v$I?Lgo#~pa$U=T^(NaN;WZ}3%?P3*6>_@I zO}$(Hdl1*}dz*9adRp-ujtjQJWT9HR3e?A}P|Vk^qBev#4gx#C*`+~(3w0f{Ycjz~ zWcakuvWg~_M==vyN!ucw%Vx*c|0g#h#o$x**rS`u%k`I}%nsn!`|!iyNz#I}UMDs0 z*F6;Qor)*7L+Zx3T$A8YA4a>3$MgKVWYT}yq*|0~od_{%e{ch}!)0;bZ<(1wecbz0j%j`CBg+){de$LYH+Y%(tmY*cA1vi)>xf6~zW@{qIj$LoE zm!QGXn;^U1m<&2(8!CNage8OPKg*e*og%NL;SoMKfv;R$e6G%Vgw8d+$Tp3Qe$6&c`-BkADFA(32s@QNrBWYSyyxRq&Mu#XjS!gUmUyhu3|0!OVbB z&R0z$t&@99O65A_%WnMMel&n{_Y&e#SD}x@#ZO>u!T3v( zJoz{nPL=*^@e@=%0(fhm;z;Ob?h7dvdXAK|1t6C{ zSKN9R%h%bcezT(F&l!n8N`sSn5BZ>qJ?w4XwZ}P}BN!F(bq{D(ua{aZjlWz?Lve51 z3xa!5Ja2ZqO`&dU>GPm~^m89&X&mo4*Vcjto7CHf7^Tmdl#yE#2M!Sd1_e2>;NmaM zwdI-Pl{89O8;6iQ@$Dr-XH-AMmtDOUiQbe{=LghHrk|XP{n{hQq&zCA%WBp``JDRn<}f5 zk>h~8UdATKY-IpL&kWw2n>=x#%x4t)M+Tmm7=0#O(Dl5$Me0=k_VJ)m=CSIrk)u90 zu~NSZFIu`ZT6OX+ChT-n6)v-N|1w7-=lD;f&bKiI#%aw0)=GTq*`jyiUEj|0y|wu|t0k+5RWr4uXOX@AY7yDtr!lDh@JcDPGiLAl(e_<9KzktIJV z#XC3SJ{-h1=^kbN-ufow6526J;toN_emhg4^m;m>Y>dqAg#L3QOSO;8Y16kTRDPS zWk(+T4WQOi6A1|&tbMooVlOX&)>}ua;M{(Qf+VA@UQW-gi$(xD%_oKMtfkL9jbRRX}4wuZi zi*QcmG|^VmT-9@Ll}o`72}E2}0nm>;OGko7kzrfKL!@G3!B1TqNtA6=Yii?f0&Kj| zJ-$$vaSdqq##PwB8fHKb5%}fohrd%-ZAIzWo6N0%dftO#T-qtiD6wgcZh4%QN&bk^t7qNRfC6jBr zz_FyC4lo&cK${1y=SYLe)jQ)F?@aLj}18DZ7lt*o$>*8 zzg1V-1DJJ(^R&35Yj`NOrw(FW$|5EziD$B^vHl0}IRJk?{?9NxHn{m>BK)Vs8 zEez03$(#5>oxf8UoY(S;PeZ@2r(0*T=3S2Nzi^YSRUcE+`22C0Ch$wo`(VzwBJ0V= z=lxY4=trOYQWkg8IQKfCA7yr5+RQmBaD+Z-taPk>LR&(rpH(Ga zoUrT(@?}jB?JhE(b3~!WZFK9an6pZ*^m=2d8;5uG2ykWOHpsudBtkODb>xJ(&pXp` z{6O#d@edvKZQ{ZY#3t&x?@Y-}1!^;=Dy1Z_K9lc3PfDE{2*m6aW{;;$f&u_~7Pk}W z{^SP@miO`IDX@M?2OC+bl)P7RA=Ij$lm7X02A+m=j{51A;3~fO4!vY@QFKk!m`5>p zxUl=W8s*~$?_XaT$!ks|Ut}YfJ=lfQL>ar(rXDAoS-h1@=e|v0b6oz_vE)}pBa3J@ zorwzR(RKbvLp}D0Z|^RXa--IS{6rYA=L0;l?z&LqJn@C^$0hzQnS3cbiHrD;mA^x~ zuzin?z74JX5KXFlx}^=^b)Wzp%DgYaNzOiZ#4k7XikJBfQdPHf4hg1hD%#bJ69*qB(aKL7 z-^a+8`@|PVn@=qb=IJDFUOju&8AJBJxgP$1z58$a|2~a&e^Ji{M}vy{dR17$na7?|n6wt81ildZ{11aLO;YyP<(Z>lwu@@%LUQXY{0KitRuPQ%j^AtSf+ILjJ zkq2_|3OP}PU4*TZ)TuI?bLdQ(tyR_A@m%wVbWl1Mk`>iJ;~!Zo@pk#cbVW4?`7*EX z9(I-UM%X_xtj}MZ!zkw7tHnvaTK-Se9(^Q#Vl=!K{)x51IaV&7y z!Fj*hX6g?V*BnJ0%e=IPHd+CV>2XME%&YdJd+jJlHBDw3^v2mk8-9gyCYUb6Ke9*k ze`MGAVb@j<&vm%JTppDte({m;xM#grbf_Q_V%qBXcG--d@4CX-1E*^g&#+Q)L&Us7 z4*F`F^f|xOkLT3@%0K%B@o8>qwl?Dp42fM5639PT;qHh_eVe<(kuq2Ih5oE2F6ih~ zjc5;y$UvgQ`B$M_W72pP`Ez|W9Qo}ZncXxC6cZ7fxNQpUzEds)`Q<=I_)fpQfn&pxg|&Kd;Mv7)&RFY16>- zF`sPE*002_*g1zA#rm%i{&!DK;S-{A4>t{dx3M;tG^eMp<=QOpT#W27{Ud{`0lMB9 z$R5!E?EaDM|NYIEj;3FDtP}Cx_NdvWg#aVAi9#N}V>Zc&CDX}l)`Yn zHf}#RUIrBdN7ISS_((3a01IK51Pb0xrvPcB3`ecwoTwvC+%>mbysp93RF;{+c-WEph0N8U-+;7tI)Cm(%m(<)fVC08IG-@>wC%&}3@FcN>*NmMR zJ$Vj3a{kscsiG-egu5`nF=abXRL__d(4=IeWiE_HxaMwp|DxB;q>;~xq&BPJcV$J6 zb9jZ8n%~hgds1!J*w!lHK3-K365>OwdQD3)6tsuSnk?I4Js&wH8r9 znSSfQe{A{jR@R8#L^nZkI06)YHK;J_@$@rS@|)XV@q#mV?lxAFAJVE1BR^h!LHzV* z)0>!hBbTIUyC3qJSUVcQPN_3&J?*4|p<*Dv|`rCKp@s!QyR`?rCc9_2ef= z=X)!oReJz>cb=TBnkFTByf7`qu3H9lp4mK}yY*-)onIXo8Q7@cw)h&LB)*CBfWmSQ z#SZTyH}?PATWT0ZxW>-F=N*wyonxI=^^bG7 zvl*8<|B;>TabsBHm|0{fr=eG;2CM4H@lA0K3U*eZe_nbMGa*^ft1~$W<>!B7=|7;W zKtf=zIk`-5t>j^aH13J&lP$xsixde`;Mq|0C@9v&5m*)v1!fX*Z5GiUEZVusZ`GKiA0#E5yOZUQD66QSV@@df%VTZ;>tB|HxW2 zLFB(b++Dp!lWr4aqQcFRnG}(EL0S)Tnb?gSLnS$mRsdY$gU(Hm8t0J$Kx)!y;hi*f z@kwOeJBKxN_lDeYcO39H9j)Zb+Qup(M}YqDtCj~bZ|pMm9Qz#FiO4YG{}kSKN4nAs zM77v+Jn%fo6EEPcxGFPOWgT222kHh;;Poo@{Y<|i>W?>FiwwGM92w}5a)!EZtIFNZ zo=xM5WIM8b0*_0nqj^WB{nLzAb)w(!6RO?s{Uf^eL>wXBn&DhMKM? ze(@hQBL1xsaj%kZzm5Brr$1d85p3;&EkWU!QJ+WA_Oq}n)XKUZ{SE94lCgbFy~Z|w z6&kfZx@5SldDYu>JIe*5(p~-F1dcY7zhhKUylN-|O1T#&|Fh{O{t;Hw-9V%g-2S_3 zD-9S*6#f#Oa6J7*=CaZA$|wtXvsN;vEdQs3&5*qy7=YF7s@(kHeo33S`CbX*-OJjw zG+U&@O+|nD6ZSLxKc=bQ@%js(0B|tJ;;PrXODnyOBU%U4L91%-@Ra zQ{4rHJQ}46R_9pmpCx|o!|}o6E~Q9JHVlvR1mqTKW;zLuWT3_~VPD3vEg15(v+IK} z`FO3Hmzb3Wxz!CpN@|x{5sV&-GNP{3z=Yi!?!D5=Rk*w}&)gRA<0(_Gf)$-FgtaOc zQTOsdwrkDlFVv3PQ|M;Q8JS=-F60OhR{tQ*E({Fu+1LUeP72GWwm)QCzB6fSH*aAK zyWT-UEgp(o_y;mxP~)XZbL!;|uN69lhvuc-4136(_332_{wqO<&m!05AlwM&gN36! zI*U_?_bhzfUh!-HAIyDMP?J&LCkhIRfQ4Q~n)KdFR73=XC`d06kluSw6r?xlNQ+9Z zk=_Zt7wNqu2uM#TA&?L^@9xdc&V1kO%--zfGYl}0bDsY>ziPqGPOs9+A(%CltMPnI zXt+@BeWFm>>s#wY;NW{6t zUsg8GTa{MDWR}fxjqv^G(-Q5O&QP)}9l*g!6upKG+yP>eeC1X8R(_|FzJPn zq05I5e-_Ov{m06U8z4Nbn|bYIWVhSWvN|vZPUDKN^9o`0T3ZT7urmB3F|CD-`k{R5 zLm2FE41{hfdKgZ71pQLBYmf`~CeWuMTLjT;O-$Ig6PV6>P00w7^;pi6)wk#m&P_~H zA+Dq@HN0UJR=!QI|&ZfI(PZZR#*%paQl1!G)HrSs203mD!|jg~!Hih*z>~gW^R^6yxUWggLWlFg*;?Lw zH@qg+V7o0N2<#M|2M~^@yQjjA%81M~+7+~I{g|v6Oe0~PnDd9d{*SHnHB=zF@|N!; zcA3b>%45Y5+ANwVw*dgv0#E%>yN614rS|=0y4e+n4t`&nRFz)$UZ2jf;L-x%27r?2 z2c|A|*)WAX+6%1QuDiNkNry>&UFsfTeNYe*x4We^18v~RvZO8E@eHdZ?Qj;zi{E1Y&2##-}5xXe-3 zQ0hD}<7Fud*&oCXwBN_Rj5n>6u5@-j&az)IkL0AQ8Txg2Ip92Rhx)t?iY73cfs}0UxwoaSjIEnx=r_mP8nH2m0kpRMd*d}U_{N95XWGn@#-^~9 zZFmOWXb%wlDpC}!)=o{z;GqnWrX+)9kq zL?#z4;{)*F!5NcRL?6?v+alP0KHlYA^<096Vp+?Qc3NKOJ)O#IoVQbuV5wz8QZ2V@ zvEO5Nr)#6W){TijtQ@%cQT&_hJQiX_aRacYTI5Dz|B}_&2K11k6TgqshwXejnpn3) zJ^ooMMSLUtmqGXy@qQc&SrM-gm;nFtODZoz0_`<*g(w=am$+lyBYEerz^m)@V<+i# z%ksC(^k+_3_@hDxj$I$Q##bs)o6EjJYGv9oGu%@W+qH5(?b2Slg6W|xWGbUZ#50|d zaU%KoXLdXYw}tgL*msq?>$G4c?A7Gi1odEsc-KS5Cl1z%DI$kWCz9b7PTRo5b-GFw z#b7;XpTfh}Ep%Tr96nBoOh0+0#U!>W`^dccT)_VxX?JmetZzV@c;?(h?Zlz+^wt+H z8}I>Q6U6^cFHgRVq0oY|N{}3bN*P+ghO32xeomUu+R3EpnU6l@VQt(kb6bg7ZHT<))v>={`|#$ceD| zl7&ToEGD~6y*qO!33B$x;Ot_~g;Y9s>*zO$kgZn?UfRRJYS;6$HFzQo^T3>f=#m!c zb2_wr10R+J)+Ns6!Agfna-{_;SU*IA=;E+YnJ=`>OCYi0=e``YSCy?9b+aO~1&F9L z;uGT^D#JrvO6MeL%&S(~!r#@p_vAp{z z0NRpe{pj<^Yu`lNURCh}Tle6~cHfnLsof$~8{Q=D{1O`5XF8Yr4QGN+X*qzuFtohf5qyIPn9Y3Od4Wk8VpCCtkj?P2;4}vwIR_r*PX__ zLbyqd*?K)@T)wr9z=liDt4EzWqEf#vYt5{s2?S+4j(wNTt%YkXeK*J<1)DxC$k2*V z9&xql&3R~)C%CgiZ16ExfE~-e->qrE29B$1Gy-xWw-gi9oOz*26t21_AHRCut)}xp z=Jelr{{91k-TZ;Y6=CzO*yYlfD&Vk8^R@4+Vr;y@(2|i4Whtj%o%(hM`MyOuL$sHs zPkvxL2tT3lmZ(3g!y=Cj8?mMciYLt}56hUKd|n(v8;`JrG=yYd>0192+1fA4?-gnG zL6H8H=kdkgc$gCrk)WgOjUVjl-eyx$Ca=h;N~ zMiG98pf$S#%Z2nH4HL18i_-uPYV+;KH;$X;sM7O)u1J;sbP7GU*@&u=wMOY#q!EpG z^5qN)E=`qdKkmMtUYKl*apP{A9*g?`Mn}?}t#?;C6r*g$avmytQP+?Wk8Oa|HbpV6^l$Zd!fZFKZyGs%ni$HX%*zxG4I(CP3-=F;rUbG6g`ZOmd{o zRaC+Be9>ME24-o-`_J{>YCKt4(m#xTFcIQ??-L303nzs=@2PigBK5{DTpLWx=HCsu ztgK z@e9qL>SRcojgE(yeRAAdEh@1(ZCfs}{z^iVNz6n#9YpIWm-oBCzODRye(=(bnEV=Y zR4&~_!Z!8#8J&@TiQ|LIE7za%8u1<8x;q>fLlxG&0R=>fhGKBvfi->XP}x4Jr-e;t zEB%d661*R_dj*ZMj_(bu9A;90ik(`#Y3h;I!orRfw+@tW`%Lf{`JHy^jW?sVjX8@+2h_oO(x_YNf6YmddWFP$;vQzwJ_26$k7m zK@G{$xNcvL1WA2iX^^bB|CNGgGsqSQHDd7LS&5;tG} zBl&FAWbXHV)<^47I(EqRGYup4i;^*L@i#QPAWkA~W_6WVkerwH^uQo_T0f6FnX)`x z+DXRwv#C~MSr@`{$*7oh5KX%pN(A{QfP#V`_GcXQ{B*&#Z%syBoW>jk(c>7 z0kBVw#z(L$NtRX39mdtB`SICJ*5Iw7L*v;4#6mxFRn&nn)RcEiPON^=fFr_jcrWAO zig0d>&gf=Nvw(VK$VvT&Fzel9Y3I@UG9v7}Kiv$k2QG08vvZ3;vdVby@U@!llWVa^{g(o|2@0NcR zKZ8AJX>FK#t8QB>=sM`W-BJtY?H78#dB`5FS5WYZAW%1ZM3P|Z^gDlRJwo~icS}T} zGkodS=;P<CIJ?c+s7GjP!Y#&e(b1<`i?b=(3|cggRJ2<6i)A?+v*gKNRH$hOZ0?@L%V@zL z?d55g1^;v?SWpXUza&1R8Ee&nWC8IwzUbxoG0xD>qlY)!=u&%vpfuuU2N-aemFWAVC zXG>c=ygh0e87n-3H22b-B8+NiHPZ|)H>7iDX6T^J8=#I#W13TYTVm`Cxuit2x<^ZK z)O1_VC3xhj#%dLtVnh_XHHR0uq>xn{+h6tqV*)K5~ z4R{3-&Ed8JU@V-U|8A5Q#Tw`jzuMYZEOH&)}(AHq}LLq4k9KM?Ya+yAa0e0GmTAPdCV-R($YSwJu zG)$+wy~5up>gm|R@1O7zowxtx-R1x43xI!f|2vuVfAu~8-G%A@`3F=f4rp@pFzm*q z$9*P-DH9I4j9hK-{DUaota$v*=fsc)=63oPcgPX?Ofo1O%t%Bh+_sw7NwCIu8y<%M z-`Rl-jjR?RPu6q&CaTZ^Y_H!`GW=i}c%HoDAdT zohL-aUeOyMu&$m>yLZ7TQ%Cj^*B|+AoN}bEna1|&7sJVAzF%s zeu;@u&d&PNodM0OiV6Pw7qPk0r6)|bZWi@6cM~q;L>C@y40O9Ca6GDq+zmFa&BKgS zDNQ(kHB)Xr)&J!=7_c$FN94g!+BA!=oFZ__>E*O`pKkx)9Dt7sVkhE*pY{IvmN?6A zGWX_sQ*fvhSrVinnTt*&Mx+kMj5H z3#|I=;DITT!bNi?=>E_utL}R22m6hcj2752vNNgLiOk$cXD$|yR}eg#?!Wt#^tX~U z3XbH6J~J5H+H5Lnhtk@d=RXBv5&E6tB(b?HZ~+2Z8Kyk zLV5Ww*L(G^PVi$!n@DZ~o|QimoT}mE0-C1ef$B*T(D7 zY70QRp#v%iujjh@|0srn+?uw!BPT4;% zqdQX>yv_nxu1ACF%tzNa;}R*bG(ZtoyehcEyljA-GOF?Llo)8%MhA(CxeDs%sOLLa z#68BEzQx+%9vRU*z|Nh}*Uu<<`OAJajl}UDxA|Xc3iQeW+V)jniu&Vo8nbZkXO4V? zbq(^4PF`gho7YTmM|xNVrE_QfH6djrpgURL*IMQG9$Zt40Thy#7}Vv>`wLQC)a>_| zhU2W;^=2gYx1KepK1ejV3oun7`Kxdo4Y7MUP2M$e&p&EdsoJY-U)b8iTlTbCY(a3p z*%7kDutBIr&@5#4GV{ixM&A6^o!4!g5h;o^WB$_MyZ@NGpJQ7wJB|jySE)q-CBgF$ zryCaz;Gd6J?@bJ2XK4m9+8fN@_YXU~xK-%`tfMNle#w(>=C|26>;Yl`T;hVCoA zNFtX*X(Ce02=B;xTID+Dz*Ml3aCxc0sk7#BdC`AYY)cH<7O->Rwy{p)zitYBfqoTk z3ER8s_?`~mjq7s}HkNIh{25%B8A^-u0OhYK5OGd-{6jQdWt$4so$u{!xWbIlw59h1 z&ImjRjZgE}j3!Jc`2KIuTO$g=piY0_sx)NJj4bLM{GTX!(lErPP-aEF@7Uk?g z@dOjjYr#uMe?z*VT1Pw~aurq6?r_C5RaqaTsJf#e5Ux50&x0=A;3N{YE{P1=e}*rz z!oNfftL!FOT>=sK{XZRvX`JxJy06D&4(*;*?thY8|s_lg@Ie_faCi zW^x|l8UdfZXG18trun19fg1+fA^i>xDQ4g<(8%4|u+0$V1|svVc<#0fT2cm+Dlg*3 zl)t_+&ie1Hi3SD@%igA#{V1M)B)_%)7Z}&}zrZ-R?xqJTO2^4IU(W{6SwyF0E9uMy zZ1Wxn%?&C1tv!|aQxJGpyA@1P;fuPiZZg+d3J`)>bsAT$^lpS0Zdbig;VmQ|d*m0H z9~D_sRTZ0oX}sF&`;TR%I;bKFc$9t=z<1}2+HoR<){!&(McF+PL1!JA$`D5hu|;1N zD*6&NoOWE1Ox}DTeCh6u9EK_3DSiYgE`yc?mV?uXmM|8XV7TT5xKA zIzHNotY>Im0`70*vnoRuA=!Y>{@Da|qeRdo2T=^r(BF#YR8hvVbas%Ug)!m0jkoH= zDT7K~HW?TUU(wl}#Go%i94`(@i7^5l*OA^Xq)697v=`waV?CROu*LLvQ`)^e(>G*E zX71=;(P7qP9{Wkx4Bd;idU{-4mgR`|xv!6HAaJkKvZ;)^6rgp=b+eLikv|*(`2=zL zM{;k?!r?*iGqGjhPx&W;PT}Ee8Xugm`~4GLJ(=M^qE1hmn2~D-h}0XCTm^dlSkxA( zc{o1xx>;VhRr=B|MlSF@)`^PZxu~5in^F~=g#~du!MEi#`y`AEU*NT(yRtOqaW5U6 z9NsUPkcRiTTPDrL8#wlNf=FTDHi~L-0K6`WQ2rC!e{w;1#LwG$E4EL%d_bbSXe(GD zc+*Yiw%`Gj$Q#Ag<7hbWQrF+`JV?ei@%%jlgA~xZQa{;0lGmxr`DU*vo=Cm7vs{-Z zL?gtoLaSTyUr_t6H4U`D@00NckrObFFvTzw+6%pw!{IP13xxtQS2e2 zxDk6cj}IH0fM3r5t)93@wBdoO>AtK2PyW8a$nBEfYM9>G)JGd`PeT~zkpyw8&379+ z7O};8rn~tG>9~3YvAtmpWf~7GLm@H8Xs!-d#JSy`{4QZ|@)h}s^l7a&i=)?aC)3Y| zbOy?oun}z7;)H1T7@+1Ki3Dm=V+Bu)XAAx6pV6Pk1dLEn533&;dlF)$h32oz(}IZ4 zbS52p3xLgcPBB%gn276~eH64d;P6P!eEBRFosWSr!xC3mdwHLswLK)1AG7O9T zOW;Ds4Epqbs&7j7KT;XEd6QB$MKB^IZ2IQU>wLK71TA3zPF)9&2hnu!07J@mC70F9 z2bfv(XdB7Ml5bY6eFWRmr32e2RLVj6=^suiBGQyH7J18uH7@sU_PiSQ_!JMV&lQQS zrizKN>$ifr(4@NY504FMI2+3U|%Xp$gKJKkawi1w|&^^nh%8aM?Vd;C9=>xg13^ao*ib>g6G8vdj#0(g)8#sopl-|Xx*a$ST(WzO zt=$w|=IDl#DN$}}5i1(_VuUK%V7%M*-=qJWY7L^h_u)~e1iBQo>bvWF$OaTZiG7oAPGYG_-o|#nj~Yxf}lszHiM*aJ?49iSiA3n%QcFj|f^?kLjjeR#fFS zw!^%}$^~Ky3i6`!R?+2{m)Ioq4zhBfm)OZCQj1#evEPWWN17(lqD-WMFkigwlXbvW zUKY1-{L5+^Zp)(Yu^uR{UIumvtoP(FZ>w7teb@m4zjK#PwqU*0kn$9)?l(%@MTWp7Z!v9z>|qr#ao7hQxJOPPYP>aSy?>rL zud?jhPL}+m;br0MK0F23AL`2}s{{tES}@xg>pNGat7_(M$xSQ;?q7urj3F(hWo52u zR;VNm+R!u+XRE%Lu?oH!;m3KeDYoUg-}V6%E;zp2!MIWEPw@k|zp<~k(&0yvCcj83 z%zQt}klpw;AMNK(XkiDG7_X_8>+p>bUw(;!_@Zlgu<9lopdUbu7e%<;H@8L8iu60=M?$ImcY5=L!@7uC zC%3a$!CeEzFxsx7*x=0gi0(xIzwhQ0yzrDR*%EDJc5SJfq8npi;5nVP43r$xbUj=C zeF@ociO5IoV7h9tAt;7^KNWG5eX`7q?VnB;4ERg~PxhmK{+Yt(h4~}aqXgCGxjEK} zg%BnGF=mNT)a(ynx@S>NM(!D&`hfDnqQz`1so;hFdrX;MR%PBdJDL2_;m7q2szOyO zx70490pSo8gxJIb1KJ<04(vZQSH_^B(0ZEw#Asp*q%?8&#)2QUwNHcD?61CwaG*uMxE6ZlcLG9II8aXENUfyyFyDD(dG~xY$+&iO1IuUDZR3u-}pq zo@*Q{Kf-;uyLb0oD}IP>LU9ksPfJd@=x zF6I)1lsz~{pCZT)P7xDJ$sBQy_I^3u?A|aEx==*oY?;J9CM9df$M<}I?Qu}MUxKdS zFQie!t`#|^4y+5=ICZ-k<>fvLcI-Khcmza6#+ccq1nSZ4$g5e{YAUhZxXo8uyf1raa@iM1~|W2B^54mdy-w!49i}X>@T$o z)fBx)VJjjc*yQx|c2dms4{T)q%q-7qab4W7X-bw_YeFc1={#3$gc$CTvpM0fDjE4T z#g#94s!xbp5Us9<)kC?N&3b>c5Y{=@otmA;vRl`|fe0q)O9Ns#GgzXB z6;*fs+NxDNnfMrk1ZEE=|Gig`^O^VOV(FFjI5 zK7yx$d1CtIpD@j0o@Fe|j8P_@^nUmesM z1`4;)3!5kp0lhv|40QCHCp>JGhewA`>r&)jB!AT*f1ZV(yYBE=4eADwxkx9{?D;Xf zpyxh(Q4)FA))1X}(y=F4`^8?j*F&3Ge|9>(H0NY0_Dtmsn(q_D9uy9_BL!P>96{Fi zElC+LaD2?t(1O;}-BePnX)?q2xUIsbM8hF}6k-b}I0epwbxf!PCmrNh_G=)o*g}qJ~%&?Vc!+ro0o&zn} zKjD{;4eAYy(J1OQiV9DaBy$PdT4BH@q7BbT3sxMpi(WMjgoS1vL4s_v+jN2T3a&?VJo$xnV9`J-W|H}Ks!WkSXbanq zA%GFPmigb_rt@uV8=iF(7XuI~<`bi!7Al+-1aCOAqaT3I`RKdTS3ZP|?MM^j z+Gog@qs#L145B7ZNrNb6>Ue~nh;tcL*sirK5XqFH=okyzBgV^g% z{u8cawCF}he~wGcHk&!FYLE|+C4yE%O4|9mpj#@u!%$l9$OO#Z@mpdU^(vf(`<=>q zM@M$HpJF*?1aZ6MDhq2s2-s|EYJOWY#5Cw&-96~F+XprtsNXXz4^InJN-=NP@^w0z zIqcza;676c!-l&CV_iE}@+_u^ZX^)EZ1iF(B!{$`1~d%6F=3LRsNSl~e18=hoA>0m zk{3E3Q-g+m@`kdT`|BL*xMz9hza|U!6-`%aFbkaXjYo4J=RXB|Atx4ldR2sGq;c`@ zs1p|LyjW}READL%IrS;((9V)5t7iMMX0zXJEQ3|c(=gCRfOI(dMLu~kO|F& z7~V?(Q7QCG$Gqa(w(+s!4q5w0QV1?D>{&q~ns-xT2tc%X*|+ru&6VF_xGCkFyVsNQ z+@C6wlF3hCgP@o1I3v_iGxa{&+pog(xpe}qFWuEn{+@)z z%aiDPgDgz=@>#TQsL>K*^Yd3;p`MLF^_N^wO1!*N;lxic+YzCsqeT~(iF?M@@SUi# zJxzRQ9DQVlNVQ8=1BXOq;ONBlW^?lSpFK&G)8*eAFStd{YPh4nl$vNj(T|pmsUw0T z{!aR6-iB=|fM#P*^a|#6|M6HgD5W8f1Dk=fbri!6Z}u{nkVl+TMhjO+?OVNasa$p% z-Z?raGdvTG@Ygg_V2nFzm*%;hPm8NtC1|i_W)GD)90f*p6YG}f0d^A{{$bBiwyneq zHFGC(X}6S|$do!4u*`QyQ`}S5BCI>}Mqo7BIVPSg?kd476%t zz>D%(pSAxVFvapANWs`Y2!uUHH}-;W{}wp{&)PZuoavE|sw+a)*P@Y zoEE|Ey0pt)RKkWg%LRuDuJY2VR`A}}VR-AG#@Gx{6I%UK+Z&G><2RM}VjBauS`>B~ z?~yxR8=%&s;RxO-VQE3ekB#+hG4hW__f$!q!+P*qBks~Ah|@M!TK)G&8K=VI2R!Ny zFM!t75ep?$DUAvBLM1m{x`=hQ(7c0v$8C71$}D+|bKWF|LzbHH{Ee5nVVv9A-myOY zBxCXuE+O(Y!I}BpOwGpO6}y$~P_vz_;=}8zeK0Ln)S=X#q1Jdr`M_OglC5~e_3|9q zL67Z0aNGxv^KZ~Zt=+szzazc_>YaXW?JRxG7{*tk_05hbne=?Ka@gY_E47j{%L*e1O=7e-nkP!r6xZO8L)5c8+kwsoX$~T|{kXX+P_` z)h5DH;7C5|Gy&$obH)r{K4)m6SiMZ`*VqKvqMwfl|TArOdW7eZdGaciu zJ3YH7+IG34VIf*xef6o~Kp3%7OlrrM=P3`HQD#ayi{*Pp_eT6Hxm&6sFw|4WAC}Y? zjr~@x2KkV~`CqkJ{~v`H|HUKZ-~9h?{7Qcnbiq%o(fI!7a~OjZn>#qR!yM!bG(t|s}CQ3w!?k3`z^z~dN-oNogz4Y~o zX`K!A*tdgO9JFX%EwC$}JI5A2z`^J=UIad#R>cWMru~XkMu!v<>*UN~N^0pZKYdxA zNk0S)K@$&rOlcS#J@$Q%U3{kp4{GkQO0q?=XZAr}V`a%|n%7%Y^rGr2X%l#32&pPk zxC;yjW!FVR9V{^iw+AFByipOF@~+fnx3y2saE?-%{5 zSHzE>(G@qUwJu@hm`d}bB-uTnfg~SI%*V^ix(auzrB276>A%&mJ`g-w|3p0h1CJkJ z*Ooxh9IS2`2w0CWucTK{DM&07`7tqt_3pLo2mB7NA~B$eXa#A=(x9=Q+d zqFKJ^Qc*;aL24Qgz4BE#dcIY-)cvhjeyru9+}!Z=ciaA>lh#!Fr){!Agn!~=glLk;*tBDZ&=Z^Ddo`5 z_C$Ws=uoItX^x^JTg$I%3dn-}ur$|BTxQGI(x1D`Y{yYNO=!B*6OEe;I3f2sV8)W{ z{U$#2LH#)d|0r=o_Fx|^hbx3)>?BJk-zC^zZ#8ay71UN@F5Y$?A-yC=Bq zk<@Mue8q8Nhq*vQN%lVc-p0oKHt!P-(;T1G$r!x z@*boyGN#hCV4cM=9UU=1(!*+Iz1IZGL*0ams8rxHw&Uc8qo+1xXOH~{rW7W^8zITR z6h>lQuc+D3WOssxiaftpap%C7`5%dHweMBNAVISm(gp*~;H|H}#_55VK~&?#{D~@p zjXaS7WCI_FV@!p76SO!60gNC4A&K3gF@xX#JAS5rKN8muDLR`)(7dQw6Cj0iWxey+-g?VX z>0bL&jO`I^NZi7NX49wBrtR28<}Potdjl}KSJ&L;lRKnLmG*$(wK?@UKs7Lna0ffU z&1W4g%)kY^YJk1-UJjll;|Ze2J;s2xCpM`08ZqO1^JnUt#0(w|^|pD4 z1CZ3;lQOY-sKjB8e)7%w$*=~D2PnA(==ln{dzI{lA`!LuVd5aOUTgQMZdG7O zSY$$N?t4vLZIqQ%s3L!-K3l^lVoBs;J}Jf-YhL#e5P8td-s%C$L|Z5nDSmdxmSqp; zL%#jhi_wSvI7nWSx!u``?t6aEv!H3IcZUuSy;D>XI9dA!pG5pc#cxo=W;qR?yH6V0 zf_I?jL@iS|5yk3yi@#ND0{#u61ao4i8s93d_om{fcAFiY3F;7s%-JpBeSd7b@)DI*D>`ACxUHi+m zF(3QMR;5Og)*2<(M>}##n{bXI=xrYW?HZmIB|Q;GDg#rAF0LQ?YB_SLnsL!Dc*?<$ zYtqdA(0|LZ?KtFc{!F%~aEynoBE$z}Tom?t?n6#8TW@q;S3b!<5`jw-$^c@g#0|bt zr92uFyr6u!_8%-`RSf7`6(b%_{F{IBYyx^1ef0i3&wWGAA%7>^IR{d^Yf($|k&sQH zY)gY|d^Ulxf$$h9qx=|C`}|KY3GYA2%m#eSeP;RhC%n*I2?UIkQzZp0ddc&f4y_aJ zjOntTb0069h%S$Gwg9_e(SX}v9)CS8|2Cc&%HDJ*MxTgSyti)T%Pndz zC){Piy~5L=*E_}klYG}F({g^Cz+K(kSl<{jwXEj$I9b&b8px~LDx*Rjxcfg|-6qDzJZx|Q^z5L5I?^RpqOsjugm9qrB zS5kbvJaH2qyBlca%gK4fmBdth?z5?w|!+ zqSV9A5(jvg$wlljr=O{lU3HrbCJKgwJ~8_4y%hVk;NHW&mK0DsRv35-P=#|Grel4t ze^|RVf5|F0z?-c3w-9BzNzT`~Wle&IgR>1H|E8MY){))`!==~B1uO~t(8Qjj*6$FtP6;OU zkMp1CRycbyg-BM*v8){HiW_1WJSL01n8#{>+OzhDCE^SiBE>V6^tKCiQ%bUy4ndG) z5q(a9GOZwJjo(9-#soW6rpGoRRJzIcUNex*qsT($kRhxDq#kq@4N(?T&{|I^X(aMe3HIG333>qq}LxE5FQ!K>9O z&yY)GUG^?LyaLO@-Mh6S9W(J)&$IlUToj!!S7I0!0hXS8Y{*3>{xDbl|k-P2Ac;h$B@t{M1SaL|VCRcZz zqaw5`%g#E5Yz&+|zgEOL#tZodpBeyct^sd_fWP}(Z-KXQY z7{+F>Vb4(OpNO&Piye%ph9wFa z>zVh-`UDn-P8-`4OA{=Ap9TmBD4Lx8thHAA+xV>;2R}C&l>3jQF$M21qa;ioN?`gc zdsPH2Bfb719p@rRG0zzHh2__JA1Dv&#>(0hb`M?qF4S+{sS^IE1uk3d`0cVC9fkzO zOmsqS5#J@`-Ir|-+z`0*mV~SK&7Wc03qxFWUa!iG8*QSjLDj?{_g=w&B&^`^wMQv$ zrweK_fMExUIrmd4n-@}ek4DLNK{I*68&Cg{l%p!|w#}7#6DuH2s*#oiS?~Z6TDrB9 z>BxX_VmQM8I$FfF-J`)WNcZgvJ1(W}Q>?MuDMsSX@y%I+e~f(BjoC8o0^^~XaFpJq z$udGD%$X7C@+P?WI&^{nXLp<&7Le{Qkgos4;iEl`txIV^j+Q<5W)cNHA?Z+Ge(kuNg z`YG{ru1W|cGGwVH^4pn#hGQ^4@!vy=N@yqcexAN9Y2;Axg(%8Fq2g|@l&Yd z-|%s)Ec|;2PeNLSKhV_c4B2;6m-xW40Wo&zEnLH3z3f6VIuURD7epeU_ zf^@yHet@T#dizJx>1~5@Iupayd`6dEBjaz-nx*IlTy;Q&5z?h1qU5t-PT8v>h)wkH zDp)gJUVUEN4XY-LVH`MZeY!k2T4wqF=+U&rjlRysDDxV%{qMn@0xz#QM1* zCn9V7W!xxsF&Gou^ttIiOlktK?V*~1;vgv{s10yONx#Z}8Zj4-gg@Gqun&wsBOR+r zyIaQtek-;v>xP8U^ef$_mp5RpS7;lP$;b+9yvW+R@ZtFzNR~_$R#K&Ef$oUh(B>r$ zVHN&%Qz}Vd+>q21JBdZl49*aJr2n}zu6Md;+GMDp<8)V;v1=8YNEEj;+TpD6FT*tF z+SHvkjw3o)a?Ml&#w5gmknhX;kM{lTyw7;M9u{*1Uft9;c~1etaueKm@DqHPj-yw$}S4%|!+=7Rka7 zE%BOfvQ5Lev!dGJLa2fqu(t$P?(QN=CcytlN@ul=p%bFS)K0m5;trRJf9b$3-htX` z&gl!Gz5SfF`a=k+qD*6mQ64ruL4%h;i5{qJD7%^bu7LRn@^8k&jw866IDt%e>0W%i z7QC=fK(=JI*TCUzdGih`fLPmguXvytRKYChZ{bB~>tTbIkD?2=w-Mx<_B%h6rse?0j6DM4RiSYzB;gcODBJE)@^%g_R3S9j_Sv*l8G<~@$xwo@0;`tZka2is&SQiPAmclC-nVa@Gj z{o_+4k-MY{24!AN~9hqHb6tZdwICi&3>E+={{XV_DFT z5W?#{tCAQG?54sh643aVRFB z0(2Aq5S362^UvQnj!rj?_tKmFLO-7bJ9c4~SP*XVYD#Geak?1Xu6Iwp{#&S*rfD!W z=duV>?bp!QZ5T-M&rrkWZqUT9v0ydOEN{~(6DihBcjuB7KC0VEbtP?Xdc2}a+fT?X z-vuu2SfDPt+?MvuYtS+SP8N+ik#T z99p_Rml!W}(RQideNPP#GCZ-1YBEgUVianEOV+Js+Vs7M-ak{cf?77>EQjfxEyD32ScH*V2^jK{{D$ zYo>g@opHbJZNx#SAg{N~OqEi?{+4NY0kbA*wZW0MUh~h_o`?{ZmsApe_!IMWfRSw+ zZW#UAdK`B`>`8^wld_MSFc1>f24;WO(7{^sOYN@pOL9{7w98`#tB&fg8v>1fJjB6* z;`Kw6iMl8{2Znb4wKg(K_Q-SEf-GAfpozJm+>>8650}2og|3Px_u1$|H1Rv3Cd61r znT{!lmjc>Lhbn;GdSik^6*Yhfnmh;93u79~OfK)X`qxmNY+X~CT<1Cykr`Fy6HPnW z3-X{F@yoCGvGe;({VWTX;{FLKrEV=dWE@hP?1MOZ3TA#wLzWvK_aqb4z%l-=M~a8H zyN@0+afeepwyp=KZ1}v~im`~yjx|VmwMF+oNPFwBrr!8}7z0rhkxrS?jdX7xL`iW9 z5|RocT~Y(brc%<Pz)c*f>ity)upCVK+E-6RbwdXR9H9zFCQyLOUytL-V#(T-yqLJDYws~x>DOq>@ zsLV!E`9Pud7~u;99okz&QAQS$($uPUYK(%T+ zNnhqOWYMs914{8n9_%nT-zmzik36{(N~LEZGOb{Lh_8G2PSEmYyZJ zt+$TwE3$ga9~Sn^J@{mD^q-IFvO_xDmH0wSd9^))Z^4ZymCYuEbL+R4N2DsgO1&$y z;RKjkV?cSZkWd@yf_p2iOKi?@8%pOk4cDck%~$RqLBqRV;%v-<3kKTHL&#(M0inehEw~yoORmzJel&awMc8ysrOU zn;b~`3MGjuchN4alFXq#2`N#ISMq#ntp3q3+(d<@2x8_zivq}YZL;qQIhXOL%s(2N zfbdNv|2W$)@=cxS?V|0g%EqmgnejaVAGSGTwcIE7f40KszKbKUPbZ=l4e0=A6j5SOLL|KU#M&n!1!=k7tbXnX*BSS> zvNFWdTNJPu@p>BT2fmD#Q>`e2u#bP+UQGBrNLI`X%@hCg{SZtXZ}tyzyJ0fbQ4G5r zK}RahO<%IDm7>u`&zc#DKWfX!UsC6Q{6&6{?C&OK0>?Rj&EJeKHM_yCUPIVnDdOMhTeHnKk}2~rxdzN_tmM# zmAwQRL^W0ExsY};6%5Y|1PeV2X`Ae*`b?DKqCV6;Li?H^b2ld-F-efN;_ z3d2NoV`=m4M2Ah6QM_eUz>0R<<)Pxvd4&*5UoT(gydJIlZY*6GrrpCBOqJ!d#0$JM z^bq~`jU^Ujq@Nog?i$@N1nDmKeZ9W@LS$6RjAdzs6e{;uBxC!r#17WiErY;Fx_5kl6=3WpW zQf}GDVwC~-DI)#W5A8lGXND*D`#M+7-aT(n;m;@`YqeHAaQ0y8C&uPVD5h??Wrl=U z9?M5|Ge9pOtC9oHdousgu++%Dll+7bu6=%g_jQ#Fe;rxM$V!AluMx03+S|3`U26i3 ztx&JbKffC&a&GvmiLq<$!TU9rZ}PLM0JiZ5hFM0LO-UlY3s^#W)b{5Sh4`0&ZXAc` zk8-xQLgj-|ajzEDYJ<+q*8mb9@GZtr`N;oGG;@8-oaqehDW|oMMS^v@W_V0^)aL<@2 z-djfJJntSqg|1JxUU<3jk7nRe>#{0jvDog`m{?Xjdq_~%2;+v;FtYuLVvh>)f^PQB zbX_!sXeo(rzG={U(b)B{Qf61!izHU}k({)#s29kW(TJq-f0rS%?sb1ehAdvas>wJ# zi`-5r%tm^96D}xH_o=uwD!s>2H&nKn!7Tw={ToHO2rMSS1jX85LigU|oxmqg6tF<8 z5{x^&XUVH%I_DU+Q(^-k-UF2k)KH|7L6pOk!J#7EWdaTx%B1HZV%45Wu-~*VKqzwM$tumFpl*q=!DBh+l-f_M8;t<@7#XPNPtVXNIjE z*@@f|-4i2Z8*5jsTzqr$A5CAY6-$q2oQv`CTXm3PC?U%J-mUHshv$OFyRr~3EK|R` zAb|5Vm=n~D-PPUy4s6o(CD9)Vi}kM@ddzU|K%|{F(yD<}=JS5QAsSMA-gzFgKp;rj zIsc=HR^$J>9P;Ie{5_|a%*xmm#of%u@E%pK%$TrZNO>C~h7d88xsp=Xg{dDN{U7-# zwb11ac`lSRf zl}XogyY4b$zlQ~M=4?r;0nT3!2tFqNqv-BN@ne6Hqy&TEBORL&(pF?0vJ9LUPlX19705dtaXAsLA802mD4JQS2UQL{?~PJ z3#8}VBlKP~Z?qnsLzfG9h&W_2;mn^D556Um4@iw&I}hBt#XQ-1D{8bZ^$oE9z2RWH znKKLA0ZW^F-<+OR4G@MUiXyqis&izzIxu1K`i-z04!@8{g4NPcGBK;|n5sA;d@y!n86>u1UuegC+tlRU{xJ39VN6M+u zeDMA3YbW~wi5UYBSjkPJ5En=!pCn-@3zrbp%2ZjyEmiQO-QS_uDnr=$nGCigv1xL? zwFJmg?6;`A9&eZ2YBFkU9!zJwz7(F|hiXz;^uN-YAn1X=leX5sc59_$u&xM|apqIn zxfm0JkuiC|48qf_9axf=D7EGJ2{_x*K>Nk#k#S0>mIKHYjP?>A^1C`J=M`XfVg`N> zJSLEAOvye%huZQI1br+MK4w1heHiE^$grl@>ToX=#H07u{L?}(=KfR3KzYk90o83; zJ3J=3T5M!!Q@nIO7@a}M_;k?E;CHA3i8Ys-h6@sJFF7d@ycUrGn4API>g2ro^Swic zi~Wz|FRWVq_VIDyJ*YReKz-h6AKse$0gNK3G22MOrv1NKZz9-JM3x zVwoUbgM^~^5$~ykw(67&xDX+*i-Cy7wdUhh!~3t~PCKxQ)r-DkX$iR9TmB4S4Iv3? zkm;DV#xob7J#^Eri9xS9&@6Dzdu^bvm$zv&O!aSfaLJw34{W=E5W=%K#{0ml?<}eq z2kB7;%Qa5=tyj!jMG5#QX+Nm@6h8GN&w^M9*kJX)G~QYs$EJtNM^g~oQrHpDUosF zyI93OZJP2eU9Dx;;b){uUuc92D0};%$fTDgnXX?ts>U5WaC&$ zPEBD-uiNqX7VF)}sac5|?$U$QIgh;fI*1z51^pK=Hjvr=jjpzZj2fLptY-E9ob=!b zDFkFYuPin9ka~ZSz!~U5z{wB9M&*ZD;f;#l!6Cjc7VBQDF; zv)A!XjYrJGl&ipI06$si1TE2aJz=;b9WJM-JMtm%+=QTef9z0Z3NW&|PFDFb7Lj*@ zSsxiva@{fWipB+yeQS;3@g$)fD7!HZXx8b?X{ETY{r*A4vkFSn3Dd9pt;Oz#w)jd7 ze+AP4pOf(>H+%ZIwM%1Klfsko+QbsYhLrECNJ$#jx{&bFS%A~E7YDi8Y<2DkQ}142 zdu^nv{YRlRyrtIhVAyG3=dzsm6}qHikimM+ZrKC&wPI=qsCo>1iv%T_SQ;8BF$gJU z#o)Z;B_$Y&(|9j{e5zK+62Bl$2{ZZK5XRPPWW>ZyS#<&6gZf-iN_mHw|6bEL=8e6f z>1m-}qA5i!;?%{}v<&|HoX*N+5>l-kc2u$|=PKp@Og$dXuzWE$09A6`;UTX1P{ZojL0+wDM?N`JT5Fj(UPPE;g%Smre*b@da@m%c(d z@kkM?OZq0YTXn$F(a8ATA9RhBWlm(TJ+_=j@roG!&?7Ykc+GPpzJKzq8DCNa7YRsM zQhG0*Q>6Z-Ew@`s@euv`O}5QhquuOG+FVq&)7WzCXYAj2OQs4YM z@CN$uoQt})4@vU2TuM5CTtzx;2t*!_kz76R0f+fDo5tl6DJ41pjX$(S2m-a};^-yh zKKx%bzprKu%qro%;729S|C=^lS-DT(dff(PT?j2|N z5<*)!8;GwmFEdR~&oJ!QM?uY}xlk1d%QJVBYMMtx2cbuISy zxi?)jAgPSHSh1XrRH#3KZq=b4G9j^||MLObpYr6b<$B%ZPzoUZM>;TB>^R{*imZbAigH z#)IDe^oaLU17Fh4Pu@=zzpaB8Jq9a1GT(39dm1%Mkk z5j1cK(um(wtANYsCSyT5`>J}>U2(x4f`Rhg9}w{)O@6>y%cHCe=UiUStYUB5&-+3Y z^oeb0sfzqsUNSFzBE7+YTspR1sQ-N7+a4#$9EjLV%^>8W4DW{Q=9%zU8kq2AJm!tw z9O9Kfl>;OUe{rMx~&pv@fK0Z5OI6E&;Mu^6i>{L(+XF_r{|1lhOUf` zU<8-QSFZC9-R4Cx4PH)bbu#4|a?2GNX`*_H!-2#@>Y-d7BPM-@H%V6UM zY1b?Kbs`c5fRjH4RmIp2N>C0s16=r+&Bk_;f5jgU`Fg1&kWBk_&90Nx$94wgaiHzr z1jr%}6iGPONk6wV-JdaO{xoazHIOM={EOGp-+aYmi7xB$<(NChCsJ-lD?7flVbST; zPJG<*wUG%P9kF6$ zabM8cEa*e$tAe+uz6v?o6;sELh*z0&q zi|iN1Tf5_WUtf-38+Dm}n3hoRcRkbQN9~W%JMk0qf;{(iIcXUCF!J3#O3Ga6Px~c? z2t_k?auXnP;StxteQxdt8GH;qY-CH=e9iKMp{@OqnH^eO_GXV&v#%P_aV z#CUdzocvD2Jvbx5yf==0Mwd9oJm}>llf{ujwUVIB*R1FAj+Bwr^DWlZY$`vDba3wE zX$?EX($KBgF?_`OSj5(*nHnQjl%`K}q*GM0tg1ed@(Fghx*qgRWQRIYM%zY*Gt0lF zgN1Fps#Z1L@ig*WJC7<(Oo#v=ZFFri;kiO}M6>YxIoHhae9sR?I$j$0DcQo~)@VZJ zIlQV1K6)X=P&g0bKWF#zZNW?991%s41}tJ2$w^fw-va~-km0#kk*w2?!;5m5^#gwQ zuv}F($0kw%x@YZbRuLAqaOJNKO5R8)b$EvK8e@(_T)@TlN)*TT;-!qON(((6xh}aD zze;GJ-XvkV=T%8wg>FbD1-xU4n`}eVPZ%MOb7y~!r|M=;vn%v3aW(~q`buxC$?vrrZ!q|PW@v$(rp zz0r@`CWW3qdVWHd_32mqJNB0R#n~)HOJ%zqq`G$Dqu+VsD=KZ`VY)@*Y7p&Y$8!+A86 zgHN|R@0EV+hO#N|=`ZZ5u^Rs+0KJ!s&9{lgwuIgovZ2s;Yb8!>#8B+T3pw_O$!=${ z-xRy3fBw<1f#qPz`lE#;Qyd*pb7wnTScAG%q_WqDdH(yr@;UiOkeQoFT8?^!m(Al~ zKT52lv05$ME9hJwF>PtI%xzXhXxVYfUg6ez)w_1$wgCzEhSlNMIvqH6F5pNnBi6j;!H(qm*UvxxOMPI}vSG*6_Oe4v}$N_grCXv@8MlTwxz0 zdd|AvR=jy(+HC_J(MtaZ%uSLWZO>({cJmPbmCP-l4zHZm2O=H0DT=fwJ4mP|z@p~G z77F)Ha}EiA;+7M>gW3CpJ)plYi$+NG??oR#IkX+$`uZzG&q(LPtdT*2oB~G`)@~)b zv=QYLPh0MsnT7*Y2Ph1|PSPs2b4D=K!lb-*8My%<%mbsh+Kd!mj@?*?i z>ExEdC4rvK%eTjg8M#5WwT_g$r{^coU8Q^-CL<8H9WX)xx}{D$=4!R6MYg9~qMz=c zJR;yBfeh0v$xB7~c=RO_i%|?t=~H1fiTrUVG2kmL&4pO=4bENV@-A35m_xC|Rey`> z#OuA8y={6~T>~FQ=LLQ!i z(i#lr3Kdej03AU%Q^}MYn3YiJaew+Lf4{#*x_EId)6n$!^|s8A!L;(5#X&bu>Jr)6 z1j5!;Dl`Jw@CUPw;-4GldI`c7u6|2n&@UR^_UtS_Dfl0XFg1mz3g7wyez&`x+6u>& zHUx!pBk&r=kT3)TAfzHl42*n%+%Y7^L^5|Eu9c3rkogjH0`ATsLjL3|)Dve^y42ZDQ13Kh^SP~09J zN&0P*XjT+1>a#=bV~N9EzD^u02Bf-X8Wdz-zHfFfM|C(-NrqaaB87!0Sf9Wi!8-XU*7oTWI7kWt*;=_aE;?>4?WHNjPW?ne)p#7DHujudf3 z_|kJ`N0-mlkfZVq{O!k|f_V`@{dN_>;`)RX*`apB+x008bKpRH@$NGFy4!3R!anUz zc5WmA{fiW%(X&cgD02`RluFN=;-IGhJ46-8Yv3CejUhw{Qh4 zYeT8(ZDo(xdh#FZ{C$nAB#tj~A_GY7^P9J^vQtVDTNY~BKZX6+paE7qCNaJO!c^>lRqWH6O5C7B>dSJmf_$HIKAd z{*5x5C`vj|p%z}PZsG#nqF#h6k&^LE(2w(?Bdv4jsgGg4$#Jdvv?_MHlPpA;V_lLM z5&C3I!w3&z%|TOGi$)+ed4^?SgNU zX-OW73L@NKT-iYX+v_tb_}I-f;6|&}UF}%&cBhPa3B_(hmY9-38F`D* zr)KZA7d?IAeFjAxormUi+*Su`6`Mh;A|JOC)#w5=eB(Y>bUumIzCEk1PdTWg90r;% zJdMq@n9Nu!9Q+7|krD~#9T29So$_XrS2EykVbc4}V*bV)P5z$|oG&8#^il<$w_zJIBX-XD`q`&K&BrK8DN@>I(=7j9-kbqPsrT) z;Gw3Dl+_NeeNiC7n|X$OM2N3jqHyRpkYZ}rp1%JtiQPI}Vr$Q?fXMRe9%~6!5OL;Z zTU*H)Xk2)THEIO(vQaF6*c~u^Fp8G~Thm#LiP>Yq{Scgl#~F(h{@WbT_Z~at^--q( zwVj~5eYl3CYv{sLvf}m*)bU0SXXhm=KhNv4-{bT@O?W!pdPW#6%etHsC@MTTzv21kD;sKNr%59Ou<$&h-8%OL7#9P`cRskmo8!70-zlxec~{&|~weCV>8`@1jdbA>%9a!j*$&$y*I9@UAu-i*W}uiKD1JJn3)T{7P`4)t{g_Q`pJ zi50r-t*k_j_!=$+%ymnlvEjP8K&D$EVAs)e>FOXWOG5|lX2USg@1}}HJ2L#mADdN| zpjQA*E5;c2$2rIgmwUSSc=Bl9n%#pN&Jfu4#~aqiQ!K~%!hB@Ap2h_~CMFp{_=l07 z9ZpT_(~-WD(LE|@AFCX@ex=-XH@Ctm&n>;Z&U}tU@;DLE#eHrKh9(E|g2iwlJMCje zOQ!OiFLqge&b}mbzD_Ox9GeLMGn^C25<)J&Zw%2{x>Ei_%jIZU1ZN}IE+@Un&Gxl? zt1ERG2DofKL15>ZCU@atcnF`1CAi$a4eI5i#3$FO64G+>p3k0bOdk0;$!cluhAphK z9U(F5zawEpTOnMT^Lqb&Y!2=*uJ`*S0NcG6M{6?*ub4o5X~}w~0hDq#4}pB`~kNO-VU|FasPo>3M<7 zxq%MWmdufdKOM522Dec=*^EnrA&qgX?YzUke(H)x>S(9>z5JxL%V~~D_$?b0C|O$G znWOnmH!=6H$2t&wZCC%MES7cfyH%~P)rg0@o|IAC<>ufrBc^HHLiKL%>XF_zYbA&1 zt$3PrMK<5HD#!Dx+;|1PLn7zed%LEZJfip-3a&*eB`n~CKLO+piRTFqM?)_&tEEZq z4F6~MIWqx=>`4f><8&7uM{sW?ZYlj~{jDTXdiU^d1kTp3)^>F2cJAQ5FJJDw8NxC) zOllGm9_+0vTUA{9N<{_FYL|3#RfE2hYRhdmC+an)|F_mH@T**C!wQ52EDM(+sTS0I zY!%*0bWzG-(wmbk9#NTG^|e~K0Tw0kECEB&9kL5y&xATUBF*`=L7Ronq`E}s^nC@b zsakW+<8=LR2f1PSE+vuTu!<-dzt8Z8gZG$1JgP5V{)ot)TmtRrp@EhO2VU9s)~wEd zprhYz#9gszkrTV&KE`wV8cgz$?x#{VT^BtS0k+KF{g1-Db)g-tS0uD4cgnRhl_k5d zcX+byFm+p7WUaw(=GU0t4Ht)3I)3YUModnmNK}ym2?yN}HjM{Vc0x-@ee(mk9gz$7 z@kwv#H#>1_CUXfUeFO5AT%PQ(0mJGS6%rcQeBD)fz!FMr)p73G?jz*X6;p`x{3x~+QsFlyDPqoUiSOQh_6=y6hJcN5PPTj_T z^4EzM2ciSS0hhwf#38UIl@rA^c5-eOZ+K~!7wh_=5aq}-!QVJ30%^U zH-P#Uht)68b{)EobrdylH@-cEd_G;3gx)5#RiN5hX^C`QUThmw#y|WfLEj83pVvRb z`-sd$52bP#8(a?vsdfBp-2cPhCl$e2ig{RaG_XK;jE(Wm$4aA%nnFJ{eZ($}?+11v zBLM(i#~v#d=f$KTCr&v6AQb$0hG%`Ws7$Sp{VR=Ip>^7tgH#RmnE0-*% zI^EgMxbcxSc@WH@_qTSqeaqI>X~#4717r`n+tw32?j^Joc&PHNW-43kZ|<1rEGzAu zNi_Mwm2-SusE4(^sI*~H3*wpZS2d$xR4y?GpK8xdH9zIsIX9lsSzt#CxqJG@#;g0< zDrl5Pt8#)zd!2ZbCI)H(xbv(hTubz0G=f zdD3lhffm-gbo;Oo8tPZn+8E~Lebw~Ykx=P$+e>kKH*vr585Lqf1xPwiQb*Xj(yFR< z65@nR0Q1$RKWQSA)YpW0CVoj2bhKT29SG{E4`FEoF)1co-$aOyXh0+zZBy@_Kf>Ae*1DKs29rjKHQ!cb6~BR+nZ=foM_bq+8>g$-WPNoRld0#_ z3#O$H$F2Vu7zIE}HkD8`ROQ+tzh{IQsfppcCJI5%JeObBw?GZXHPpY`ICCE&om#6x zlJfn{i(~tUDz2{nFCE{)hcxP<-fZ`k=7p6G3Z}H$45fDX3|wZW-xr8V~TCRDr=@seqTrP|$r_oLvNnV13nt@g0JF==9vcH8?tN zXQf(}gL2>8B4Nz{1Hc~_vsyWcw5@SV5EiR0aJ#?HjYo4t?qrJFX1$Lch-C%#A)sx5 za&z2kQGfnc!4I!2&C(S>ld!!UjkrK+2&mYCeSP7R1cA{a;<~tT1qp+1gxnuI-%lsA z$o06%#QAP=r-pXBNu$J~H$J`N`9W6?%u^|q88&so^vRz>+{oU5g1qvNG2@Edh(Ft z!)U9i;wn6lsnnh$@7Ghi(c)jAuM3sRJ5Yl5VnQVO;UXlyl|H$9n(m`C_)p&_ZEx1^ z;_rqBHaX$N2WV!>cd9Ch4zJv80kl@u6&R$aC9KrlEbKqH+;~-&qw-Fi?svy~ zz=v;D;hMl2mJL>FOU$iO!Yrv5HMf2iud4gX@SSG+p2UgFu^7Py6%E8m{VaWLDWVNu{<3NX2 zdtD@1|4n%SLPVj6V*R10~4xQ3X9RMT}ZC?Y`AVJh>Oh7X}} z1&j@JsBqcmvVY%d-7Wb`J{}e_{}(;%H6?%SM&b$~_CBTnkk(fy&Ka3-z7dNW(9MC0 zgDFFQt`7LnAPCa-k0y|0S^PzSz_HY2{1@&=Tq*lm-r0+GbrFo|t12IR_v3iTwZc|q z(i#8fxI|Q6=;cDW^NhF}J9aQ$^pfSA<-Hjl*!Q}whj%h=Dcy=y)_$IpFw1xW7I41g zv|U-G?Mpbcv2qT6@btH@Ps!=M2D_|}2aV06$JHd4uiEGAZn@Hp1ctQtA#UK$wbR*k zZ;UiThaO02COa$eQx9RDE$^wbY<1QvXQQh;<8g>wm|egXocF*6}S$IQTN$hop<2B%xeViO%Wwb2xIdCr0_4Tl@2fO%B9u3<50@pdf&}+T;$5{*~ zJDqqd^>GQov+~L)2QDth@CYP5fei4@ktORG1zrd08q(xwnn7#Z9si>tl@B%yUV9nc zQjp>4HN_epB#?LsA2!PI7 z?}>iOh1cV24=m%uSUv<#63wKj$GT_!kuiSuR-;%s=`? ziM7kI(NPACyfycOxeM-n?|D3${6uf)Wh%|4+N6z`%~#2g;`0j|x7->*-I~lHmA(E_ z-%kr(U0A7mio$73{+R?ZlrLiZN8oM+hQd2TNqW)d1amKgb7|qly`AhPMwK!BLXQyW z!Flw?7G=}Mf!}!|Et>0Etn1;*+LhSQdExJT}xsrFxfq|_?9pymi)g~W<(fwJ=-*}3A z#r;*KUg`rhlnIB~wSknE27eyyCtlkyu=ADM0rPAOe=)&(i0f$H`vo~JyuZLmR*?tb z=+~$z(v914y1lqnPjrecTT|W9=bXcJdtlSUsH+yCxYhWVrhLjH1*j>!z&{$Dr;tvg zD=Rnd!6ps#eGWVwHO}w@6|pkmEdEKk;!50k(fT#|lz~G`1eo)WLep)#&Hz5~$_Z(a zj|#)n)reObth4uj4Mv=F2c@MiLas@kFfsCNDC>&2u;{LeVSQHLns0DTMm(!jQDb$8 zGECc~9BK6Vl?qP^oX1&VFOZm>aZIF{NAWniJx(kW!(M`X^Z@uO0nVP6-g_noUkECW z0iDUUijg#VELFx_wkxGJj3@&bnfJ|tKZN>7_(vB2ww+!riX8RKyn~O;g)P08TTA2< zyYuPEKbq&ZN&+2TPK2dV^%5M>su8+tkL+N>ZAkMcYIqe~Gx?NSs3wUQCro2a<3v~?Ce)H_!MK6X$n|8dW(7r56HDGO$;usRh z4)f9Gi8d8mVuqKvEtmPezvk@_9d#jPH;>E(4baF%bY{#1R@K?P|?2>Tui{ba#8deC*)_12G zLisR|es=sBja>;qNgE=wDH?s}k{l6!8&8+h6ghao;%84$vjai!yNhYq=~jN15rdo0 zGrro54t%ejXCqjnh#N#Y{m(a7ozDQAK;LQRJnNISm3S$eFaimEdPrTulJD?=Qt6HG z9>O{T0`8UgE$Yvf1YBLXpOHZ4iJE6dnU!l&6PFN-i;ML~+b`q!)MH**T;#Z{NeYqP zQn5H=Z6f0C{rynG;ap9hMa?T6XLrs zHoDeJ)j=nt!kBV`3A~q-kbwCFk8fNogVqSeTnlBRm093puegVhG@a2L= zNRhOvU^9~ZrePDN9r<{{=D(69001a$H`^WAF@K#inaa{4?m{;|P`5B;!#)iV;YW3rTU~5W0#6s` z*MBrKk5j{oVOH&vLKQDb;rTXk^-jzW^kx=TGMn;nVWns%bIuAsiWLVNSuA8=VzgOg z@oHY;E*x2i&5ixpp#*50xz^9$AShIxR+8{W;#ag}m_T+%saqoi-)lq-S5+Zx&IJN$ zcBl^59T}>SqqB3D_&Vdet6FrJp2zE$umnve8vxN!W4+phleyVnF{ii}>-S5VbGcJM zrwsLU)qHFf%!}J}Od+HYCFZ>BOi+wEEoyOUp49LQc_eL6txN<#)06FBFKmy&ner%BTIN3-5n z3m3yJmiW-cDlA%fbLEQzVf_VJps>tV)*5NtZDjK_eRd$6Fcf;}RJX_S(VK?Z`@i{+ zQb!0R!+JUsvIsWPp+by!K_o9koNeXfx-DvSI13$DuS<3x70NVZq#>>mlKPMPy|^|4 z4Nx#c!556@s|G=Y-iUEa7}+iFe#LCEIu6JplMt9yIHF9Mdj1v zu42y!HWzcBRlm8G8;ndamX1HJ>GHpqjKJM%Z&p=bnTq>vv^J~|Y$JvT+xx_*C%h3qNEIol+21b-fN;JX7C$Iw@v$R3NoH;JnKIvP z0+aJna&M;lTkuju%s-lVb88K$_CLW6Okdj^ifgzi1NP3j%y9(~YdzC~6F)1iCgK-R zPb>`vpqJqqNrLRHsv})r7RCGd7WxOiqax;~RQfqlFCy$>;->Q<^)sOze3$(7czQCQ zX5ZA!0PP=$Gm^BM#gpzq`PKnL&i@r?Es$5g2^N}g$1HdC>grQ^3*b`2%`z^+-vA2v z_R*B!^|kBfaj{l!ROxrR-<)B>G#DAy`j@gqU;hR_+b@C~Dx&KK;ov+InS3pKv-B#t zyq!6HQIo(O2kC|OdA@8m;9PCe7pY)=paO*Tly)5QdiTATcug_Zo6q_hfXGya9@r#l zWTTI|U;B&0QUHjhOha;eAxudwP9(m%;mYkwrQiS} zQB+7q;l+VR1yhRmJ~!+bAbr9qC;~+ajv^WPb-=UIB4bJYTQ2*jZWrRCM^dOuTh7!=RS)XZd)3^Z@@WM*0Ey$WK@(rrV%618 zq)~%J-sO8~VBl+Dh4XjTt{sit?{L^7bA=4}wWTIuW?^1jMa}H{IK~KEoUTwqvnejCdB)dCAZ1x0z`>K@hYGfNgy>I$BPM1ak_(L z{?4;z*=$=S|3`AKD6-?+kh#YL^6zqpU#3ki7s?GK)bfm-)5R$aw)t??M@4}#TN2%c zIJ28+$vxefl1iH8qS#%BU4^{}<@+j*#E48wrFM(8*j+FR@zHND;`pcapxaXa)vnKT zoJpGb0HEA^@e!D>pe0v~ySYmC8zxkyUjHk}nG{G&%dApky)oLG{q{;Qy2u4}L&}Ut zh3r^lsPLlpMq&~W5o+4}wiLydZcSY0V)UI-&xAS<@K2*Psj{PqPY6tSW8_|O*{|w_ zu)0KpG=$RVh#uq6jwBqp@EDU5U_uzZB%YW;)VI!fL7YG~q~+>Z~eN|iO?k&qZ}*wtS?YPqmuZKCSh`BO@r~>S*rMxE-8+A z?;Go`^2SKPTA!1+GEsQwq&QI;K&^LbQ ztD&rQFvdN~WRa7bF@_}jB^3vvXO@I2-hDV}0h(LoS&a$(lh%~geXO*fzrW!8=+Z{) zWHRKY^MT7pvk<63E+a^)1XAB5j3P8{JjLJ?MyH~8FZY84CV4h*p{`3(gPOgHr0E_e zL8#Kngi(6b`ADVPh0n@f4iabVw38isLQV2b1)`%&nYon#B-aTcB*Sme^7n-^R24=6-=b?+x_Y9Y^he z-krsYCz2*6`!A^{{deJHNMa%(g6oyB7Z-_lVQMO@_A5XxSw>yiJDRK{)I~3jABo~; z?>>M3BDa3ehCRQOEK4149u=CnL;X`@b8>69Uq=&K7!vZBw!dVBoU&y%fXjQ=U8XBj z1)ochZD=5As|5|i(k4`vMNYD+uxpk|C4^v=Pd2dH9*bqt|a=yfojXanxsmHcuo4D67PVHM*IxJ<0F}|L^aA~CR zUMuK@W4XKj0`$(Hn2awYe>Pa0lG|=|74GYrz@=j5j$D5>ISIa~0DeT3iC)x$z4D~P z+ZMohM2nqxji|cMU`SO@?2Vr3Ej!x7jFAvXj~UBs9_Mpb!+Iw`N3}}wm3|p6O~c*q z@{1P^Z09GDQ;s(-l|BwTO|IMzD!R@Rkz^6=DRm+}Y}bTRV}0^}qZa%B=>pxqk^jrs zRE<>3fm*bA!_d^+ud1VoFtJr~p>CKD=T1D{i3f6}W{mvl`Y>;XC;#%xk6diy50)z? zG@_|8-3FtOQDn5NIea|^m=XP$xyK`CdCwz9uksCg1?_c0h=a`(ou4|DyA;^Oi>8mGew-fk-8tO~)0 zIkpj6ekZ|lz@6o(1{!IOLEQ%ndiQ4L)ajJHTR}x1{m?h~s>7C3BERP~1=Y5@WZ?>w z7F^|KL+ZZABd78o$GlFJDB{IC65n9vOADRhq;y8L>TMr)~pMqW-Ou z3M5u&UHZXfX_bGTU8lJ8#4-wyD}}fDE0W^9N4t$G_6{IL^#RhV4=?|tNku$tGW3|5 zosDjO%5s4LKAWjKHX7M@7kBaoNk2;{uTGzr0XRkryp`Dq#lusDNm(NNp#jMt;TI)h zJazGBwV5i|7{O~UJk-TrA=yvb0k!!9&{{eE6`k2p=0{GsN4<~vHm)&CHt9?k3TD^U zxZUR?fkL^5;?C9U$gCp0!GSvhYVC_Z_w^ffGj7c*+)|@^i~KAjL&ZW}QSHYVdb*wd zuj`=78Jk&{%#(y)V_#oq8oqv?7~U&S-l2~xmLWS`w;RQ7fs9Wuk=yAD4!=gIf$G?s zWJLn115FZ}jBJ)#RClZ#F`?Xj0c|WYd>$A!_ve)p+j)M_yHo2MXXeYzMwY(EY$B!J zb|qg&Hn`GnZZW-rP+Z9Xl;%UK+vGH|O(I55C=on|^thfXc!^K{&N;6G5q&)}e=y@I zv{8&KNg^Vhp?^OhL+5!(j%f0&vHWU_yYXu_48*F9m0HPs1 zV<-~$jAR7nTTm**{Zg2LZ9Bc5-@Djz(F^icT*ZBI-sd$4aE}Ffm}DqXAN8eX1*l&V z=9n*4C|Gkr_nh5!rTNJ;`>ay>c-!r3YTt~>*FSj>Po2epZ)81={%C%L`{Yq?WMvD> z+JT2y_N)t8wNy0fBnmxWkPxLC4j?~7!V&y1et<^VDpDQ4KbH4dGOCG@Q;=!HP6*j9 zDOufQ7io8E!AOg55Z-1E@)wAGVg7Eh^=H=Xp(nLs8pVou;!q!aTj*{CLU=e7T7 z`AY8%`twOyfPXbqA8$96*@vZ3%%Kdpw|g_*#gxMmKUhSN+-d!IoDZ++bRDesCb-LQy+62M*KfWd#|V_+wkiXUkgfo0qG@55$S>;orp-6 zUP6!b4g%6cq9VOXZ$dPCeW2YkKLumCm7t8|J|)}wS@UxsKzXBlY4l`%e#bXbon9J1yIgi ze~7VKS2xqf%*UyF(^*U525|+kUgk?m56gdEv=6mq&=9;%z&6ldXUhYa9s6*_t!3xB zDBb@^kQ~(47YMNMloQUiw*+|M!%ScZvHS^<$Cn8qohUW?%!=yK*r&dH>^51bm*ggX z{{XW|i3Z^vSoB(b-+T{se6DQvhTIE_XANu&SG3)iI8FuO1j|s7?gu-8rHC{)X z(B!t1y(<`k+Q#}`Aad0RlR@Q=Jh;!u^1sN-^9?!pIr!9vMz@L02{<*{lB!>`drh2K$+xTZ zWD!EfYza$x*T@mv+SAsd7gxmUE4tPrAm5%|QXo<9rT8e{78j-~y6iL6xsMM!DfVOv zDC;tz*Hp_?ktThHG+1A|`U^a;Jq6G(zEU?DuEkCMU8BIgyfqlW1RKmNaPGTOe@${8 zG|qZS@onqcn#(GubrunxD?bSd#E_!kpU$0?`+f|@rG(NbfYY!9j-N=2l5&F&@lOx< zWP?ly?q7Q5;xw@LoeaLR9*tz-w9PNo>SH!QpXJO^#4w6^ySs3i&?kYjLlDg;`C6Dp zwhH=fHDMlfvkVX_>;*2$cF+y~QQfsjD(XZ;6wZn1oVZ<<+Vaae0RLT0E}CCXzs>?a zfarHh;7jE^%a$zb7ER0py>J7roZm7AX6USBZ>|wYJY{QF5EI zuy$aow{1yHlxHkZCXv%!^cR@p@}LA?D57U3a8<(jI@P&z}TN+yW@dhpGf#Rtjws z|Ha@gaP)iBu?_0%u%7Nx|=y1YJjsN_O_Jls`~KAAW#Y5U!L zY=l)KIQHaFULK9GQx|PoC0I)7tSe2@UXkI5r_L{HFNmi~FLWO;=GKgOrQU#?5_b8K z#7)6^=0T;_dJg1Ig2JTz0(anTE$k7Zd}B$_rR^`I_}{gC{ieiA8km;cUi$ zEe}(b*N7CLOYk4JPIBzeXVz>@G~B_g$kDbN&|lLfO^Su;RwKJ|z*%d)ZH-_-80gm#oWEq+}(-%il&r)BJVsnYT0tPP=oYeSz`kF(92v+(%cqsmuEjeW(J zenIYJpO~bbKVRt$O8ZH<_6pS0;Y|CEK|1kUe2A77MR3ge2bt-A+A9dws_gfr4akP_ zFMd!0r~_iG(7aLS32Xr}nEE4I#pd|a#SMjX?|y&k6USl=yfK#e!R|}qe?a+gHvi*p z^I=F9iZ3ovcCd@?Gq$jJ@dj!$L`7}?_|ahiFOJ?*ts1>{8wtbf6Lj+yNBJ$NoU(yy$+(QQ}$id1ZF6)Wn^(A3L9f2dGmH7sga86@w{kBtc3~ ztiSJOjif;5AkX5vkPdhevrcTVWV9Q?Ek8c^<1A(M`(mbkzfddlTPLR`)l2zV=qMU) zgf>nra5aOZomycNjxegbknFknU`IblyY2Q0vcVA$xpD~AfsWiDdqZSVbD0GY!7rNd ze*-dkCVvoPsBm#B$^u5Y`}%hqVQpYz!U~YQQ`#9>&n@$DQOVSD#mV^Ua;`Pxce;B= zg{-jMeGU8q(E)&F*>^ScQS}?+U8f#^ErQo|eu=OKly6uy758kEA1Mm@GF5#U4srMK zVj`D&xQqSV5A{&-n(NHR#{fMUvGlk6IF(6{Lm>o2DIc7p^v*f^eOtOAe>@NQnY60@ z>U!9b?%Ym{!3uIcjYA=RZGAVss!IIt;(sLO7`a-@m3w#exEsT&MJEL4>itHcDIr;u z7Oc&MBle9|L7;>v==HP~OCy1P+I?Yd*f_JF-0_1m{Om zBX>B|arb?6=gMm8&trg31f~_J1Ci)jocvb5y=Ogs;$>p}Fv4bt+@bxuN3iF z+b1h79NA?0kEAHP$@0}*0zFPMzP6kT59~fr;fPe5gv-Xe*t&B*;rRe;cm18LTCU{; za($vrJU>aOqvBBpGbDpKRJ*i+KZOu;AC|PcvLi;d6Xd2*g;gn$aRip$lpYu5d6YsSYqvswCEY zVUC%*He4MtTwzKG&#$XIwNYCwXqEa-y(O*~zUa^U0edQm>vprdgi-Wmwihgj zb*Cv@%wET$c$NOl=taQREb0RICLhFA%E<4_Ikj?mA?T7zQ9n_&(=_)qShgh6lqOr#yVOj`Lx@lXt2+FUp(2Rja8jg*YIFhhW}g#opHDwqF0D9bPtT&}HLN@FTnBuS|;y zbBpnJo3vdZB0$Gr(tj8g!hfP2@EdgYBS{V__-e)s7!GR`4$t1`;A?Q#P;9YnG!R?` zGxK_SVu~pq@QYnSs!+b(fnD=olcPb%H=0Bhl#)?DM zjl3*@mNo9xUuWy?n8wIRpByB##>8cHO0&YBjc+?nam6e+@RGO&4n+%1ls7#&T*^lV zR8I%lsDrGD}%l zP-4vC$i?)>h++P+YAHAT_9bTrZ#S&&st?S%r&&cz2G?0QPe~r{_?a{%7*ZKUURA|X zfn$0HyHkWG9R4h)^B0xd?Bp|eb8w-ln${~Vu)+O77Oh6-`QEBB=)L`jz1Qi8_U)>*1QrA}O< z$LRJMLid6C`RN;l`pYGUZk>RG)hE?j=Gqe{h$HxCo_1Fup2hRi;($fs zIGbFG*og3mQx{qxFi#lk=ZDS~+mZ#0NK(w3^VK5(65uV+M-Z9sl62aBt#+H1eGc{*`T!XND%fw>-gll?!=HhhZp z3Az1_fzRmJ*{C>w#%|XV+H#HTvWyG5RWcn+Z>s4FAd*ftx18TNd8PY^&Y@J!BcaI) zU$Nzv7R!aa=#Fez!Hx*l00eO+ZtcokQK7))-s1HrUV^+C*QVD3$O%cH+~l9_Em(sM z!qYLGq|_8Y^w9M?A*L()IHe6jQ$eUm6izm{*yBlH@{$Z{_OYyY zLsZJqC925kfhkn9HN&A0z~$e)_6Vo9*_O0QJ!wBf;oeXX2m9EWx6*0WheW4#h6Vc; zTNN)HA8m>Lj($Nuk65WHo#?aPQ)y4G4?FU%(B?Fe5t8nDHt(q)x@Ts0`_yTE6wrI$ z6ij6bPg6Fg-<7k}-Zd0ElsJ!82*<~ZAIJjZ^aoD?b*2{LPK@8zMNSbs*xACOd<+0I zqj`sCcDdqLJX{*l&n7}sJrE)LvkBQSQ=Hf=bfTo{ zmg;e59@p!G6uz^|ss$?MC2!y>590t-SWROL)sK%SWTwNV7NKb->0XK_dzOGmC~LrO z*ZMFDM!mA6*l+JNsH;%kM!%;&Ttn|19MILU?8=_1+aID)XjpWq%FE575rdQP32e9R6Qil+7#a4oj>i-xz+-RbJnR_-Wzt|#XR&c~qz&(b4e~Rl+_I{-wTd5&V7XUNgg4D#NaNDIHu>EeCy{4|43ZAG}7d7MDl3b1XXlh)T#5^h##&T1E^Bq|;~= znq53Lx`1WwZDZXi1v|qu8Z}d)Z(k}qK1w3bm>>I$W{!|>08;K7IFFXUN`AR_eO*Pt z{g$*UMBs}!|BP0jr0ri0z#Wz4OVA=768UkBy0gOzpS}?%dZ8Ifa8IkwGzsyW*Mx0| z&^o=+SmmB@m>iTfs>(YZBpxWrJJT%9KH_Ubn|v}+was%TAU*zs!!=`vr2zf^NOZ%U z^QKvj=R~qJ!`}UbO0dJjJ%mMmR8Q8|`2?7I3%aIxc30&BXvn#nmPUw19MsN|x)82I zy+Mc}^iP5kPb zP29^=%cNzZl#zAu>Q*x^n<|RuXhg<0JZnB(zwr+$Tz+KjYSeXbz0zuEF?cD5???C| zSlDKGMCW9WXbaXWmpUsr{5X>f)^?$FR$tPwMAAMj*f+}=+6$7eo>^ihr+rWnd_=XY z6_)Et-_#Oy*)Evz4N&Mvao^lWDE`KvtMvJ+lqT0Q%dxEa4gZ8HaeEBqc<9Of&^VMQ z*F9>BkmI$L3N4vujjdA+F|Nuj(L={vQFH~->z^-BZ5!$HJ%*v>46SgHxboDU$NW9y zMjB&dE6f+*BkD>#QnwzdW@B1)`0og$rcFNFbxT&Ar#XrAWf8l^GuaxUbuMstZ@$i zl+XCI!s?d#CUw6hm45AlLP%N_1MqEes`XMsw0j5zt!k@8Z2y9VkiQijHe}N?lICZC zj#4h31Ds`(ZEdh`*=crBEye#Qlix6P!Q`gJ0i-_PC&5%z5z}Wz+|Z2wD;d_V=iz?x zjf6g(zpM5A6|pF@sHw1LXKk=D1jSpKckVGeCs4$9#gPy5%%BG3qh<;89~sHoHTxNqha57dp&#%=A6cdHN|W zF6H7u;-&A;$jE6FOO+2N$yc<5zBURQRv^;4F$R>jpzsB8EVtf2l+9!^AW4NUrk2dI zCV!!iEtdD-4DGza+1_(!tKb5$T1@LJQZ6Dp{0bbii0_Mt$7yjtS(1x?ViWp6G5+HG zROeO{cmjVpeX{%~(8kP2*MD!KM4>^5Qzt@`ZZ>inA=!~sDg=U7=?8JmmVwWaxke&&Y^EO|| z;JDJ8*jb7Fex<6V#h@8eU?cbAE*ruO_1IOt>{SeVxk4dZA?0_ylsV0kUP3n2o}2m<>IVh3~qF6!^7Ls`CxA!a~nYy0V0Z<|=$k8_0T zfBU6;?4Lfb8c_k6lckiETYRq*9XjJrD*RfK9luLg67Un%zkth_dbR25e%-Vi3p%Gq zqqH=@Bmv%*&M{yGxZ5=Ci+6EMqtKdPliQaGgMeWLQR`B@Uj1#eeZO*xrSecLMs3Iv4IjY`>`6Gu@|TCt9>8}oQXSkT3QTzmOA`W zbWmdY^Ef@u(vtTXtoQ@CEy`W;b3MigELQh~bo<1@SoMwBZ|0%6tV) zmJ*(~*X5H?x^c09#VKyf!KXdJpsB6J83i9H@L_{IRl;T7mxT*FhyVL@*9R|TQpV}e zhyYg`%b(44?5;!jp^cMkhH0y}fls|c=W@e7FNV1G)hZM{Vqw@HXmD``+gV!CcWO=2 zeG!-&7A#-Mb$DNZKGg-PAUCWbY*h#5Ebv{9BJ=w5&8#u3Ii_yi zzt@v&-|9iKGWbDZxB6pOZ^L{KcBPy7bAyr7t&KMtS8<5NUCi1ggTKB+&CGG-tLvb) zmw*kO@aflR-h@uTXz4;s#qSAA!QTvT?XQ`FK-9N9M7?P?-xW+n;6Kn^T;?7)^tPz} zR|=d`l6-tYtZ~!pohatFIJ0OizN(w-xBv59o0U=KBV5KSX}Z;niwGBT(;Ou`*_3a? zLibsRozHLmM94{X{Uv=b`vT-t?G#CVBl^$!bPlF3J@yX?-!>eL>;eKn#!1oa%+GZ^ zT!w!4Y1|UUgRQXf@>u-T`z7O6*nMC+D#qDxBj=mrbk>bqQr2a}pks0;!_Sa}`8aD! z@gv#5wcC{I@)WKo>+@8eq!hNQ*C&xMB)n8Fz2Qxn3aHXs@$aM0r1WogBu`fiq%Y_{ z_!aPkr=~>1{L^m+&QG;NT5muH<6(ry zkY`v;XZiFV>IZ+Y?!pgvg4I-Wc(43N)}(P}NNtoLs{Y0K3ru?J25YX1StC>n8^6Cp z#Kby=Rf!y}PND9ynA1LDRQ&nP7I+x$IfV4wsh6a^AIFsV2b7*`IoVx_@4K$uJ3h9z zG_l|mOR+vwhN#}ULTEA6{je`A;c*)bVlG+1AA6a1K$tb`4~``8SVw7J$VR=2?bNZx85pPf{2IL1^q??VUi)p1>Br;4t%%uEnPO)AeA|Ma;_sL*X7m6W&(Pg^T*tu z0++#=@5VIH>q(KXJ8L6v$l--*h^KE>%720%eW!ki|5*{=fd=&v0AI!DL1|*wdL@Ix z`5*cMba1pcQ}Cnj6DD#h&oE!plzBsOrdceQ zB$k;!_Mt=BGW?YFz*?dTRXk%$zoh5v6DF^@C^pnIv5ky`$>6~FDusR|+r`3rZ}YKO zsdN4>NOn|*w7kwSAioZ_c!BJ?$=^9x`f{q)GUOQjGs&G|%MKHb-G`9@r!?XZ-t>AS z1bc)AB#^B34_5DVje1^c@qxePuD&@oD2w+3+d+F}3e!?CT?L(4thzUL>x>_eftv)( zB|=lg*)VQ=P);RJznI!4@4g>uTnJwbeFD*(SC9_K*NW(0jG9P#pVl~+9^1HTHQC?G zUra=>TH#|msd4fcA>3k996}#d7eX*Rq!am0;_thc)gK{bVSahMCr>>lD$Y+-av$8f z)uxtd&@8z6rQtmiN`Wqb(3_LKY`dwCCsA3BVeQP0wC>Yi@@R(vBNXvf?H@Ob>8~k6 zeiAuDrC_JVrkedp(|5Lv3_k`RX9vgC*Rkkd4wdJe6t;0?cU3Hk+y{|^sh@lAZ_OpS zADqz$@8}y<3X7>di8RmJ$K5Rr@S7gUdJ{0BMHS=oJbo|V=W)#dFY9M;hWjOf<%~}? z$$4gR_c(LbH}V%KoOaBjYPI;U1)v7dm5OnUAn;&c4pmzfBx>la>s3T}maq+{F5AgO z(oFY(dQO9x1~oMWI>Z%R8b8q4eWlU6K4JO2pEoGQ_L2U~>knZmD<~!L87~KA32X$vymxR_<&WA|ET~IVJ3fA2LEws&K>rA$}UI93v{gP`KqVy9I=*6ZPXk%*n+k$W= zaRPX_jZTk3w7ae&=+*C-T&N4%(8{eM+hWpl&(-9Tarr(Oj@zB)F2E%m!YW_?l9}^wc~m`4Z#D$ z+UXueF1H9aZC_#1Mz=(s?7a!> zCj#q~oMK)diM5xE7T4}~TThJ}x6izBdLcUL<2lv(Ar;W<0}ddhDJdG0+txO}yLR-s z>Veb~w=u0!BrZs+oNUuzn4O^Mp-2oK?>StuZ!-AYC{cbgdL zos`KPY_fONWBE2S6YqU>PX1KfG61NAao=@@KD zW#hMlm>+}ATQHxMNwlknFqy`$?6fN$uZL(s7ofdR4yetL=bKh6JIYi}`e(qJY275}cg6dK-Ch4Ezw+VkkqaXTH(ZNs z48Ct{NE*rSf8rAc%RtCKvbrD&sL2PTXMJ9PJN;Aw3GM!{WVyLS?je8W<={$C^ifZW z@@B^iA?YNY3=xUPfwHMcnk$OJZ!^j9XGwrPJ3GIfjysqbo_OAQV(;|X65wx<1PPzm<{OD)g>y4(j zU(c|{_8Gt$tHL5@Sj~SVM)E!;DjAeJ@a{<*<*0RqZ42S?fK-!%= zcKT-7+bP?Dq0qUMjiPXs|DM>J`$4|@{`=vh6U&oc5$yAySaa1-9jv{~zW|Tx}O-?s56B!Gt<2~v@ znN}7A#9)&|TZO4_ejn`MNK!Ek@Fd(Mf)R0Pe}+p~HlIsFsbs19iy98%1k$3Q)4pEC z?b%Or#bQ@JutpPyXpV%P`9xeo1QAeWRgBv0N_a@LXRPK@qEqYp6uLHpc~m`94&yNv zP#a`z5RTtv%JKM{{}(cTN}`|Q`Hz48-~aIEV3zDZgmA&OTv?DkiIYm$YG6+Jlc-7; zdvEfUWe(UuUZrfKJt;>6PCaI>KH-9t+V>5y2b{|~=t6>P{5jL0HLiTf)nK~loGTWP znQ<;*7kkyGo<}1}QQrd82>l(u@yw|%r{e%YT`(=GU!U+lvS>-t=Eg~1IVdC}f}4*h zzw+V)h!Y8WA(v~UlMabc!PB`wVe3pCCtT4r(cmJ5SaIUs{z7Plf6_(>u^r1g-vAs4 zGXM^l3-TYF^%RaC?b#)EAftTv!mXLX-HWaE_rS;+Cx%J!Ai?aAAf6+zan&mlhNN@+ z_b)+kR+w|Tf%~fsYox>75moj}>1$#YS4^p1=}_5}5D{XX?Va(4u2_fcqLi6WMBwEw zq^k}I_yF8M`ssX)a-qJs59uJO@gt?L9ohbk$Q|9r@842ihJ|)3$YPZ?Pa@19gU|9e zDivhY;y@YP%4hGpE@Xp)=BWVW+T@JB7|Cmk8;$EimsIb1IQp7M+WnP;r%s1CvRln> zh#dN(0MV;Ybv=ADg*ixuB<*Y5$tc&3C0o>15cmTj%N!ae^CxR! zQP=Il+hVbiGv5451%BV?XQw6bZYDl5ckKx9FFhlbcu5REF&xz?Qu`0eH1iQqbb$SV z>nR0lO}B@be_PAMb0rf~I{%RnHxEs~XCHN!T2s32%DbE&Vtx(f^I#F9$yevV*Ts~9 zndcFQq}xpcKswdu6b9-efk(H0PnCnHdqtM$P~b4A02Z!V-&oy(zKS@8j$S%{i?Sz= z8-NB~ApVX#uoa}zd-HK>whcaPI!`?{hApPosB>0%RQ@rT1y=9h-9gu{z=lQ)P~R~b zpvW5Si$s2T^3N#y^e3hxf&{N?2+_H9ac~kTmgUoq)x5)R_9*zK%=c)z_;RNg z4lq~U`|gv4D3dKLU42bGAB|-b&?p0fy;~EnB%|mK;Wfe$Zgyg&%}qQRuxYnw?13hJ zQ7ya4V|Nei+zan3COm|H|KN}zM_kOsb+}0fW!dcNiVzdv0?%o`8uKW`j}=>Tdn2~( zot}6DzLg1>)+e624h?e!suMwa)d{+%3-eEY*QwVjbd)C&A7%#oYc%cF&S*HQKiRoN zsY+mg@>lGA;WG2#kFqJ@B&Py5uD8mQxr~qOHlLRhR51ks?zSZkroDEX`l;&TcnMKA zIoFMo1sxQ1!bf?@cekFGIV0W+xTSYAVj&|)wZo{*lSmG!DLGFRjKgXawsF}! znr!*Wkb;gg?>OdH)w>7s6-vMKjbqsmyDe+I(v+uvb~7?pEA4gCTPNN3p*AiF&XUm= zZMRIuvc$TZfGLT^&n!x@)P?5p*tTo+oS(?-8l7yqS1>ERop=_q-~uG);%_rv2;o_0 zA3mD?endiS2U!v9Bou7fJ&rFw!DU{jv+?5NM2xQUH&>vZFO89qFK?$vRIS_REL)y2 zZf#v5QhHTp9iVxNO~jioPl}vztsvLOFxM00A3s8{&S!!Ia=Jk0NH+L3i79T0-C7^M z8I6DWg*!j$I}W}Dl|)(4zbpGUSh^3WnE`(YbA>Y=5csEYycn^$X~XJS2L>y<4`HeH z-;UlDuRKjSL-6DC2=rPTYq44zIwXIXbt31aD=H^GB&n&vehR-l%DSm=E6iFqQb$0= zng-z_J?C8A3nSJ0`Iq#3EvDyQ|B-z5IYE3uqQByvHBCY9lBXv3V*cP;FH#@~0rv6q zi`{L&3jK8;Cfb3BOXO0k*4?Mws39yMBx8+a0z=4N+zPLW$3k9~8+ZCA^bx1X>52MQ z@!D&jdsLYybPN(Y3@XOAYdv=5UC|d6iFm2t@k1Mg7pBeV>+`u*H({!k5_s7(H;=kM7K$N%*Qj;hgS#&|^pxt%(5Ni?Q_OX*2`*NcM>2&e{8>-k4 zxyRC1f7L(Fq$JepagS=Li4P~xjv)<)IS0cTsTl%%dV@l~issb(tz)04*Zfm$apGxq zWgCjnmQcudx}C?-X<`&am~*YYJgMpmc4ig8s(#;*_aO9`aU%>v&8EEeZeNzmUe=F~ z>Klruxco2FA66Ss8vY;d!(<$Cr%Z<8f7Z3N;FFUK@^tv}*yLJ%{H(Ywf5en(dHLPT zYWr5GC1KMe$2WFxYwQ!%QdrP6-FCmhg=$pqKJ8F>F%EJ19Af_r$n2_x3})WqCNAw+ ze7ITv$p#NjQY{0n*BrS;o&9;>036&y^YzTE^ctS-wXHr7hCa@PKf8c=od* z?>WVv6^_n$2gWxqu#J8Xc?{YE^sT(qnpPmy+8E`3?6e(DE|sc!ujUb0F=hSf8>U&| zbm9kp8C92+F}O`BFTxD81g__bR2>949(JJXG>JEtF!!HCT_#;mk!xApblE)JPaZEY z(k_3i--n`PG?;*jI8PqXEUTax!vB3JwaIle|4c;oCd_Hw&{JDfz3M1`aj5xK;23QY zq)Z|*W%~muA-7r6_sJc9G zaF7tb%8WdcGpu7lQZlK0S2zjGUAkr0a_8-p_a04tS(GYp%r5%vAwmzI`sCI>x*g2I zSsO?d-EJKtjcWDQ02PKe1u|po!H$um?C0CX*L7p(C!dgX>)6yn7f>!+s@s!Uo78Q6 zvI@;->Nhr>-{;R^4_Ba*4B(}pAe95>9dpeW-SXYLMJFk#^!w}H`zd@=M6m23 zP$8aOEVVK2vb{w*wY@#tQA@x!K$x61f4kSrUlhm~u_8}1kh0Abl*zzLpFXoH3h6NX zalAIlk&52!W(1Oc6k!f1w+Pca+)5)S&3x_r&$;zseI=1K^ad~2%XC7;N ztL)qfs2B1n*r(|O4^-g)slH{js56q-2LUZyu(dEAtc73s=D@Wa$6{vGF!l=XuN&n5m+!*rvzvh zgCJXmyq*zkf73Wz8mTyq!`W}0)cL~-LnKi;3=kc3Wq(Po)U@qPeQ-G6T_q0Nw{D-| zgbrw3vSBI3Pr4sfRo4k!&2Vy6n%?BRm=e^o?ctgZuy-9wLIg;61B&GJ}OiX_nF9w%1<$vUXC!Qk^P|m+rteD+TzB*x9x|+ew zM9ZE^Ok4us3Bh;vbGLq&oY8|$5nsqO#qBGEevxTR2R^5Opan>k^pa!La@(I&zjJD5 z%=Dym5tiyWczXPHJH!>ukJ&Cm!A##+oL{Hg5=)FDd>g|sclFezqs3W+@5DE3fN8kH z8b~m`B~u*bYpb2W8D=?G)4R6HsJ zHwmwe)|t1|8Lo@2&ex9pK#ySY@lGhpf+Xa2vS1a?y1`@;o)oVC_Rq6e;t&FN&LqcM z0Kj)3e+(VCo!G}w?#bXhWY_laahe=twLvr{UvWslqz_85XvCG!&oAb0^o&?Am>`RF zN0|c_!Efe-+8x~*2~W{&3{6hnKL$7<5jzLV5)gpDgZ<2f_;u)jT;i$dl|{lH816+u zZ}zdq(mwd6l6nD4+wo4q!pfMyV!VBxy0&AV;qWPiSNuPc)s4n191&W8;CtlELEC$<;By692I8;@-*S^5j`i6X)?vjd zPC^6%SP$pLj=%G+I&BUT52pXer9t!p>Do0n#_7$mj2m$U#z9tz?osbW&jqIGFES8$^h~Fc03h7f@=~r5tOX$ep7sm z+G^PIt!aBQ zMF5eA-i1$H-K?jdC&#zbiD3rFai4D+ChzU`%uBYD7$Q{<96*Kkq0T$P;)Xt?&mU z!8tMOY?0sw?V6vV0}|P<8{YO+7l7Q+D|2gouWFBkl@d~e=4b5^uM(0*FY@&i22^j& z-)6z0Az}{CUgiGI8C~1iBW@KC-&Gpi$s#jna%JaQs>qCJ#uZ5lYlwQY`z9 z_%!ynNoR#T9M5=C7{@8Jw6DDGEwTNgI2#S(7%Mz>ek0}d*JeD}^W2ZsKRY&GJx9EKnr zy1hexQc_HL6v|vIPgPpp`9Bf|Bk9ftjk)G)IrXA2{?oD$Z2|w+7~@pe67%+{PvlQ2 zqz5D}0u`tVrB~p*-%)&W@^9fvmma}?L~y+M;Dw>O9-)eN6&=_rVS)B^V?d6N4mQ#LZ~JoAT$uAhHi*#h~^XDLkPQ#!S7XXXiHq0!uZF+HZqQ9`( z-Fxiz{;I0guwc+rsbKP?a(#x=wCIke?cFRnPw%lw^X8{2WJyvIc+jtJx&>7MfhjGe zPTn764p+Z#RsxTh^|9R4F8Gc=*b>EWy>sJF5*1ge>A^bnlj0$7h<+lCsmdc^gti9@ z(^q%Vi;(=}6AQCv3-d#ZHKx9#;eqt2pT<6@YRp6!s=V3v%KbX+qvArftMpS-ytXaf zp#KG5E^qcBy1OcN-@FW=k;*gTJb27Dkh5#eH7uFO&c7@f`Dv;3#W!E31519F{ztO0 zM$?ut7Tu4OCgVj^H>-fo0D6sFvj$V_`tRBPqfs{xq4ZcZJnDt(cy?Pzo!cN&cGWR$w`j}Vt>{n*}l+V^Zn6t5A|R*S45j--~Y z1};59^>GTXiQTBL#T20p7b3qz7K?uYNGcnoJRzK|x8Pd(_rIC{`P6*f1536dJor$2 zGOM}+@k!F{v!{O%Ak#Ud-&j7le5He zC@Qc%Qe0ENB+`=8DtRt3r)?D9-(Mm9ln%2-DWy_mkfB2#(_N#hx_bKF?Br+n z1yPvvwp{%B$!l>&A?NG+a6DFAU6K6h(Trh4?~NvV;s_(tKJ4bA_H*|c8SP@81vYx< zH8G2Bk~l_u^$1?q*g}aI06!QOAJW&%`IL6TNq_gEM9;;`alp%gGu17b=Ha+G@b}fp zBGg$}L41Eim#-oI-ez;ZBHp!U$+DW}C~?MT6-hQ)?OhsIhFjZ#0H{z-1H3)uM@)pb zfTg*6Ui`ViEC~c!A#uu1n`F2d#yZ{TFsQa~QpelmqV1Kj`~HKVoeT+0hTc8txUP*v zv?{9MuYS*L=;WiBJgI#x_fpgHbSmbItt4-k!>kcHjif%2RPML#_EKD!QbU(+kZhiQ zoa&%Zv_D->(5T=QrC>zT*mlCsEKkn9vYlY%iJhza!YQO@+i~8(Z~kpaWoAWwSd5;! zlSzV6_!2ec^xM6D+mM0>N2gQfZSb4ctB&UEwAo!Lk1k}Xo9fs6GZnMFuOT7pl}5|Qd{G={HA2Av9!n@2 z6-rP*r!_r`>1AwBq2&q&GC`9c0AG&@_hmjiF z`F`*`ZZ`O)U=22zzo@#4pM(Ddjwx^%k9q-6unaw`%(FWd{_**=SnngIu=`%gR@%0N zBhJm1Y;@%nmhK&3nU)uS#zl56vqoC^@aA87tN~H&`(>m+hBe%=keZQr%|$?qDy89G z0A)_@UN0c#z}RP35&gy1s1PG{5hu(*eUN0(O(z>@p!eG2$$umtGH*!Bdh_*yUk9;V zQ(qRS#B4N0pSM&~q)lqEz8JsBOdSK>0mFLNj)^&|Gf2d{H*yDrN89KF5PCfR<62}R zXmY&xAj__1D1-kuWQ69V9$|*Bi_rJse|yIpi@==p4b}8|JqtAwn7=IsHfP5V5;=n=h%78iAtRMkF^!c0fBO6S~{mG zAGUa4ScD5M6TOUHGW#9PY}iE7bUpg^)g#8^?KES1gH-lA6%XQY{UEccCwjrYteqCK zu)3pXY9FYB-oG2IYYZsrrZL&=AaPb9=y~$83#`Fx4@y3+ErK>W8!^`>)RAugzEQxO z@#qa8B?=_Pat9EwE|V%S2w#2itnrJ{>G=}td*%;g6XkX#$3)E~ByW>AsDV)-*Ym*l zp^UDChuG|*0Q3G_x@kJi)@fh$H<=s~50wVs;;%sb8!u0To*cgZB)-bY+z9`0r3bDhM}!!KHYr+`PYUL`AU zYVirLJ3p|kmsqo$0A71xXFl30JixTRh4KUxY2IzUTef=CwVoi|Mv#z5&akoRIXlof z{9IPSO;W?W89o2?#~6;f|J(hZ{!{q#f4s&hZT3N|?}H&8%hJsIEQNP&6VNAmYCs2( zdsvV<(GlLj>iQ5BZan4txJjKo{&erG-1b?s=Tbkp6Vm3S;eV0#mT^sge;g<#qJ$tw zGm(-8k&aokFahb9N=ZxC*i@uTT3Q68J0>}4X{Eax1{*O33-9;$f87W7KDhV6y-#?+ zUfaI=o^w9mb3X5KfU{y{Qp8%c?Ocs5nq)!t!W_Z=d~=G!^zi!6zB1+@endMD;4Z@g znJqtrX{78=1~8pWmdjBN{50i0UmL-GUKp{`K|JQVkEQJ3bm}-WPL-Wh2%BTmT&0PV z-{|Y1TpV@^1{tLEBq`)XfG~zXPZcehmj|tcH8Q&HOgnmLEFCQ>y2*g}WdW&AB2p!^ zH4bNm6-PgDAV}fGEipfGa?SDDx((wl_ZnKl9xf?~-#dm9T7vsd7OV>BR`@-}&2oa% zlhHi|2=5}x*CXD-1N_&opHm53+10V1dd$fjdgx`TXcT$eb(iv0O}M<1J9m_S`&_Ek z<6+?%tXm9`rvh&d0nim9tNk~N*?Fa7sQRPCd0m#{*Y{56!6zbiKb0u*bE8X$shjGo+N9J&u%)=GtJfa-nJ!=@TEgRiEAdf?o1P;W z*nj;Z=u6qQ=nmakuyy8vs~_2cNE_l(SU{%|SwZF_&$m%yU4NqNGfc1zSyE*d&cG=n z?rq%JtrmK+ONCASu+OVV#v@6EGm`k~iy3eTIep0I85n|$bQps;$sQK(0 z@^pvrLbxq)X|oJ2p0Zpr-m$6gWG2XWl!(Yh;AX~75Men~Fm_B}CwoE9wbtt zz#;u%u;gH`5!?z;>z5m{WlVuO$+hNyRYhe5cpQ5NVeeokcxs9v|Od=bPDXJa4Uq>cJ-#0dIjYux*UB z4(0{D=}x7)lcyU8<(c|$qbW;atxdMz-)@8KTTHsD{^W&mY$el|A+hui3@QiXuJu@F8G|Q0bqSO{Z%vb4+e_nzJ zUg-@1M6|;q0dG5&J=rK*>s&`<4dmK-;^h}Q(Qq`}xrlS`Lf}fuMDGS845E#zbxrS^^l z8v`y1%3&cY_h7seC##ree64dY*5kxp$Si%4;iUCbsXx>z5D6^(koRc*mCMmQejYUG zA^)a!-clw{R%Xi8CE9J4OPmfSOv;AIW4K1qV%{9)c_lKs+=}a8V%u}hr?#T+l1+}9 zmM@K>*w@&i_DYiA{n`iMycX#~@V?p4zS2O`e(k?CCqCsPfCkFRXH>aSr#V!?xa0Ld zis-np&DI%^JHFPoci(&^CgzvKl{mvMQ(aApn!&8=ajTV$tJ;B%h~oTY{yLn|?pmTzaseD5RyRv+9bCTgCaStIX4DXF%pc4dZ(JoylOEMHPGqyQ zEH$%~66?XS+}*D*eoCGE(dNZQ`3Y7{j7kESS~6SdYHTxBz$9b8jV5yMcPO7+_6|=k zXz{sg<5_p0cu!6UicLC;4Gff+8!jSVbk}#{zn8fKCgt9}g9V0upg8HIhdU$J%<04M zyT~)>sQ^<~lHjI^5=sJ9)A^v(+@H7p9Q1W;XDUF4v>4}2AGtaDjHBOwcK5wMQRoua zFGEFuElQ(t^eV|F4y`U{SjgJGz2C>k6!8VY6cj^XvQSvWPYyq)xq;NAI%{XCtX;8p zhMrCnk+Hy2_{Nx}E9wy}s93mfRaCD)zsD$m(y?j6`eU5P1!CoKFw-zI|knDY{+-QR~&^6?$&D8chJ(I}uoz_|V)i!|%oV<%d z7ULSCr5`U%c;MIkOGOTe55{U6R#%Tbim+O~-a2^vHctB5i4Tc@`kKc!g=HgtA; z7E2G54OV0$fT;U$6{+zSRm@5GRCuD4h0a5*+P9FT_)Q$TR|_wNtE$G_A*!V>{qn4_ zFt1klPW?5elOrZE5H(mhEY+|kcc&wy^&lS>vX)`JOnE3aTKlHJDe8WaJ%a_ zJMbZKu4~}5kHaV?bw6=!!FZK(F?Wrs{N#}KiI1z*x)zt_n(RjFE z!&&})fh2|y-fYp-797UTFEOsMiyh2z#Z?gfG4Jr$l{psv2rm~Vt8TF(= zgUX~0fCw-r-`Yj1m zA~x)ddz}2rl?=)reATMaU9UPF(Yi3e`I?jHa5hu*ZW5+_ZvLXDEuEDIT2+8lwjmzs z+j;b|*C=5-AMW3C+uMVK*9>29HHdqq)wq387SmmbzNRF^j~v^0*rUNCxg~#Q!CAj` z7cTg70^n+`trh37hYY6fu*xf{{Lug>U+;#D4Fy0M~mAFQnCn4s?ZXjx_Z!fH`U&?AmIUv zt4bGeK!9z^@`XOEoSIMgG3r8$8?CW=RGPTVrOBpik}SYdk>ZBvIzh}JRdWpSJgaD7 z%?K#^EH&y~{&I^m#nT|+k9a8zq9^-0er+WK@LDkQ7rNK{px^g_iYX_8ZQDd1vg;R# zpmsUWes$cU%;w*4y}8~j)geF>^356_vXT=Cm%t)_i8JVSI2kWE$z77YAL4vv;qS<5 zJw~7#8roFYx!@WkY?N&0>tXG^i^Vw}$^E$9{nBKbl(I^OJX^qwFo~d;l}bv;ysy@d zwYKu%Jy>30>Jxzqq5;jZ%T@J20pJTy*{)nOza=W4Ed(6J9JBK zm8N^TI67hNDOV0-fu^-vo9H_QGrt4}mwFmamkQDOdtn2MPp-si0dhbE{xq!m8ZXza z#z|C7!5CWh@e_(P@)_l169(V(b&$8%xVU8$Wj)ku`_&>HEMnD(?6hz$avl5vtG8e%3b< z@TH=Pgu&CCnWEsv%Y8-7<`tW7bkp%{pKD|DCfy^udJ8b#>boF>DNaKozo?_nAk z7nm;;5E;IL9|r`0khUCd2J#hE)9=h~iuRL0&jUc{TT*3BT8gr1d}Vx|pjntcx z(Cp2Nw|4M|jxPXHp~>f%II{?2$Gd-ry~K9+gdoZqB8s|Q?W?k7kCsNPLg-3Pe^vge z3?_5oM^>onIhj{~6w}szn-i3@)P1H6bUdgL0VsnNN9hzcrX9#av%Z!3Di^mMi{@L$ z*Y1q}C<5}BsYDMhSaWE~%aqIo;>J4P#qS_Jl_VryUy?(k(~o1=myPmr9cK{{WIjik zhPwe*NCmLe!J4KM%0I?M7?nvzELFiZACkBi49$UlUGi4KK-X~ddupYS?&e4+O#6r5 zT<>gQEKH-=er4z;SmmzgvF1iBEf}CK?to~>5=0v8NYnsc#-2Pq@%AA&gIzTqG=SVZ z+!sb(itdofvOm<-sqEw8_e|b&eQ07xXp+!N-5iN%Q}%m1r;5)5EIe!@7gt7Ytd=CU zKrygW`7FahUgv!sI8~XG`9`d@IZ>s}79mAF&>!=>ih z6`oi&$;B4+u47gAqH7Ud#jYP16xmKZX(Z}`K$|1!zuicMG5=vg@g4KeHZ@z#ImVKl zzwqyGwy8OjR0Nzbr9BM@S{1$>E3t9<{Myzsp}(Kv=6(KkkYXVb>dIm*Hbq`{l1^6 z;?0*eA1#5LN{gIi?IntwSB`rqzhj3C@KLKysGHLc*}}2j37ebkywhRttwD2k&zI5GxZ76f-eON-|DPJ?E+{^s8*ozK=HrY;s(JpYf&ST|b{O zvC&+BE@S$9D!D(t=2V*1U_Kk`OCoS|m^#^`jR>pR1Oc^Rp^~7Y@M)h zcAAUeyGi+YPzMg_;z+WFT+NzyT`C3V;<*Z5Sn)7ryb2R>G*us!9q)Q*oA!0{t7hN& zC1{Se5qyH`hcB42g4-=hftSnekh;^cXs^8zf}j3t?l)i+mZ+5YLvvpeYWjQ93e|l9 z%F%^l+P?pnT$to1-YvXL7jDKJ^gX@9!LM}_ooDHMG~k}(z{mLDp_YWi-iHCbuY%L1tk%yP#`O$9~F!YT%ZJ$DU?J} zjJaQ6&upDp^1^=e0{41+&Wn>G6(QpDmcOnoJc0R+JM()aq=_b(EJj{D9Z0rb+0R2;B_tZd!*aXi`Fzdb z?JABhgKJLZV}x-Qqh63Zs3;}Figw@pUz=|jid1=uDASL?v)~>!{?gJ}hc@XQQAjy-Fb$gTlLQJ}Sx+#kWhPu5(34qqs>1t? zsjrzchw+B8{sNednQ>Z0`1w;r%{W|r0nE{MpLi3~(nK4D1$Ty7CIq_4EVO(hn^@5) zmv-O7uMzH>&dJr|-<}B&ek@AmbZ4VXyX^d532RAL5l0W_i6EgB@`K8cAuqV35)xZe zT}*}G0QOw-bS@%w2ie<6sy}7g z8gd#KHQ&gkh!IAjISF!g0{crh%KuJaI=sTMyR_`-Y2bGwGbx4)5KIb_H+f$oJ{>y8 z>T4lX{e4AD0CCK9pp0-p&BWffiCQr$``L5%hN=SH?AkJCEe(n)IqAJjFCE?p*lAU3 zzj!F`^xl`j+`{v&8{k&xnnv7dqmMZp59cmyCm51P+`kdP9Sbpk#1m=c?OClS-u&(3 zy0iMI3_JLiJcg=;m(?I#U_3@PghpgYEq=;y1!yzL;yh$u@`ZJ5qcQTSzwH}Bg1mS3`+lw zcsSPHtzS}JoE#2`^wOBx9P=&L21T^UBC{l4{$jrfBRXZ7(v>yeHd$|}NaJf7ZRBoWdRBGS)`lizL zso0RHcz5<~RP)`x4tpGh2Z=1K;AFAJ3J1x@afrf*&z#JxmD{u&nZi#L6u4CQ9Yl4_ z$#)>M3K0fs6kfl~(qOhLqoqv)ugM3)$rr{G!lIjgTtN5^cScVeg9w-QZU0?{>^2!p z;ed$DJ>(1YX6;3*Wn<^8!M=rxIHvRY6lf+&m=34rBm?5azxg3C@a?k!QB{pbeS8q`ZbQ%l}S--B9=OAV{ZkDdP+|iEEnaK6}vV6^AQk=#NxAn--VHPKk!0WU~ z*dz{A$shPwOY>R@|KTTX;e1#S^j1#AZvY~`{0O=j$LGfQ?uc{G{=D*0@oEsr!L9a_ zvdl!_%?R^Mt$gy?26JFv%Ry_)P=`1H$vWoT#`Q24{kG67X<-Fn;eLxnA!dg&P>p z&-9Zt@^NP1{c|{11VX81DtTWJ!F^I1d0fySgz&!##=I2A^LxE-amQcwOTw{Ts}dle zC)5H)nt))jx9PLF1yR1~Xx+Ig@oB@oz)anx0)f!)JpnWCroP0>FJ?)24p zv?9p^;V(LcCj2MYyoDsw2WEUkx-vh%5{JJNS?ojrB7xea?mv$NUmaotHdWuc+z;SB zB^Tv1g`^(lP@>%P-_1uMWzvpP+z`E!aTNR5EjC^hsMH>Qy$+MYmhYy?5i03Y_ta}yl;@y)M) z6cLw(g;Yw_&uO46TO%;wm#*P}Zty3|uw(VGFN)D1eBs>b`MaOMzdj(^rONL6jRRaLfr}fG1Ul@W`JJSD7RtXp z8zW!hG0ug7Ne!sw>}(kjtt#O#G$D=hl2QMii^Hmj>CwPNMEBt5^{12#BrlVnrCd>TC zwU);S1sI?Yv&$%&LoZRM**yDjm7XK6!YOMrO@E2n=UM2_g6-ZIa6b|ztCE2w)6yo21 zY;wD;POLSK>#dy8`{)k`{iN#cb73XdPjDOx&8$S*cFe!I=4bsJR42Y)6weHyu$1z; z+2H<<0_#N=yHxWzJ}MON4*nVtS{ntv;Dq9O0NnfW=B?15eLJTkU76%R&{`Wk;ZDqf zPS}UWl!adxp~(D{}9b0aFrJiqKG9_lKk9W_wACTB?#%|3zAigx&@@@$1ncdv%DJB1 zmaFQ`_1c(cEu45ry?gs(!dp2&x;;h%Ap9dRt|U!hFRKe#jqWc$WsnXCa`-q!NB8tH ziW;$uJi8nG3v{d8GHf=(V4RZ~l~UEiLAG@oy>dQbdc2N0>)nye;gz9az)eF-8XPKNX{qDSIh!XxOmPU!&OzRdE8bb6 zmS*873Cg+pWkxLez0;xGCkwm`ab&p0&G&BnJ_-W?e=-V)`!zxXdmd%N5Y^iP5m5T| zckuTv;x=Se_{8L$5l%NcfzswMa|*w=3aQHujBv{XS0Bk2t-Os>!ms%vtTBOIV-EQu ztCv0@X5`7q#P7uCjRZ)n_g=^)7@^Vh)5(C$8enFF4AvB>fEV_zBA2(<+P7HT>@CU zwWug@{s~~0?;u+(mx_Kt5$m_)NXcSBn`yjmm+IhhMUx}2fydU@`^sW& z*@f&UC6zaM3ph9?^OMsT1>)PRl!v6t5=FwL9y76xILuAvn!h!Hp~M0LUS8{|p*DT# z1qwitL4HUwQ*RgKre6a_advyQKA9K_Zev)q^`Km?*YmN_u{0q8%CAo!U=&yoTG=-j zK9y7Z5FlT=f44AEbqaK`PHk34iXMljZYsV)f1yirA4T1*FXyyw{fP_|F1ECSF9wPg@Z zO4h2d9HRcwZ$5>Mk@Oe4zM0ew0c=~5XE6$(t1wAYJXsF!yP_Tnb^?+gE1zL-U(X)5 zOE2s_{o|6y%jWe>|HsIVud+P!k7y1lq;1T5ZWEYZ6IQLcnqzlL|=%r zZE=o1(!Ir`A61t;K${ih*uZJ%xNcB9;E9#OMUNrgiF)>A^I@mZ6i7;F&A3{s*VOY% z9J!{W>|W5s{^wU?a>V6#HC6oWvCXTSSlE##>BXa?m+W04YsH?IUL|Nq$jL!2!c>BmeHqx^{1#;;Wozq(_^3|c< z#fX6hQVBbWp}ho?>!`A&&y-{a(5JR5O)c?Jnt9VwOmYhiOncCQMHvHwfvPirkn`+N z&UChpMEAHFv+!ZO{2=*>WP?BJ5JFMqL30CiZqG8E{LF;{D@pw;Xrb_3rNA#^@{AEF zb<@5_Xd2N%${0Thk_l4V*mA4$&%N=5E3e)?71z*EyZAVk2N^r6-yKJ>FIRaoizFmk zsUN{X7G`k!mDK&=w{@g)GQ0m#R`D8*r1m8M-Y>ila5$GHQ4I>jyXHB~y(>>tpFB~e z_iQF+kL$dyVhGVh?nY|B&{ zIe$5b$R`T`^ZoZ`2j2@_?-k0Yb?SZDxYt7?d^4tsY1omK_Ar&FT>3>;SjBX^zI^GY zr;{E7L5#A$E>F;T!?H}Iv z_^Wx##cyexX$M+hm&_qyV%qzkOP^mrjQpm5Ia}n;PqI3s$T58p86XW|bTn}EUAYSP z?mTdb`eWooFQ!x_dnMLs#a1D)XiL-_tk%A=qxZe2-AvGwr)-pHyGA4XG^bOhiL}s= z`u=8pnSOE<%~b4M>6bB`&G@33-3!t26xnq5!8=dqED>zzivzy8`K4xLd^R)hz>Yyl zo+h8c>hY-p=(b-@SGGt?DA4yXOKNHzT z=XXrspFHv`{Y=WyjUan-=?o>c?!k_5-PCmRBdh+Nz_IY`dIZ7x#yh zl_9l~XfP(N;q7uo@8_uZE$gEZC&5TPbTZm9r5tO&TG4oOW)E1%6)wH()EiH@2tJ!_ zli4m2g<&|x{81H^%3B-LW%g5&kCO5mTsTV1bJbiu1^6QR6kGSypG^=UE6fQH%01+) zkgn%Lv*F(ffnN$;gZ6&s#gsm2G;ooc?Y3pHuuzV@e^YONkfi>qWug+kR1D!;n0r5_ z)t%K=P!xW(&pmo7&Mbeo&Ho_qm4sK3-YY?2Rp+P@?EMfuL-9;TWlBzm?H< z;$lfJj4aXF=_34I%#tS#dG(GaPtWha)*J9s?D#@CT ze5nb}1hK#(V~CI|&sIUVp^lQj-|IWfq#g~=p6%LAH|pcK{?65pu!T{tW4cK0Z`RO? z(?g@)V1{=d!gz#f%a|o_;)!!uI?P$>S*s+S@a4^obCMHZ+Um|I&b?^# z)Vi{>QTINwzBnu@HIOHbtt^$_RKQbYlyi8{W6->@km4pyC#&?)s7~#Y7bCNX&t3fz zg!kC^)FikX7QuHIch7?L`K9A+38xd=xPSS4RoR!@%~ z)Io6Dv77uunsxSIXE0G~F6--2?|6FOt716<|3Z8L2MwFI75{B5h}uOBDg(4YW-C;R zW%))ZjO>tbR4?w6i3=jdECDARwu)t%x}i4;A>i)*djGQ?bp+m&t-mi$7Og9HG6au` zY^e!=t|H>kuU~tBH4-8aZ;KYO=Qp(hacP+Xu2Saqpb;Z?5GA2eJbh9%KZnKCQ?j>2zS@0of- zyNwHm_A`w4eXVPvX{D0iItZHXcxE(@ABaPP25K9XYB>^3jxAJK?-75r_#Zb~;EKlz zSpwyppPor-#4wN!dRjYiFK_*$xHY1sW_yly9WUO6>p@MwsFP}PN>o76JOc?+z^hU! zk}N;4p=G7a$qbenkzpu-^kosEYUS)Ul8d!|LLf@J(Ydv$`e@Cq z!poi2_QsT!k>=ilH-8m2F5+a56$XA&1fk6kN=jJZ2+x$Yh^%*76@AMo>7^m=YShUh z^Wzy{!?XnQX(YFrnR%)#@zfITT)DnpEWAkYKHPow9iL%B=Cl(CuUvNP9eziR9>QCRYbScis#W(kG-AU?O zDSx}C!@y<4db60Qf_BS^uu@2Q;_11nxa0cq96BryEpXuIyu;?0o>6lwzlT{gHOea& zQL@NB=oRK0I=M)jTpt%>*0*N}%C!-e`A1<1AYqk`*?beH#W1uFPW$}JRpT_Ij9{6n zW@mgW&Gv?$qal;V6H8%%$%QyCQha_o7=%xCJQ*zz-u7o&PlXF(1wNhbbz{i6qM68t z3d8s1j9z5lsLZQ0DiCRl{;^-)dGkSDN$GFFq?=w_pp&capb>`NK?r_MHrq5V-MU(kE)H^?C8;_m^C_Tf1 zCR1XUk%vcfGm}y!ZE*)jOy@5c}8vW$)X*3*}~ldW|?KJYnDIb!4ufVHZ=b38lV zYsyTYELDUQ^*>`xt2)=KTR<|_%nMgwIik`^Wfy!DB(dzPmulGDh`h3u zj#0G^X(NEzC*7{_!DQVw|A6eQwQzRhqHs+%f4yTouGV#7SS!u$7FB4mh%_Jjp{?~c zYSwO5!#j&szRi?th}{KNrY)64u21pwjZQz7^V6kTKXI8mwekFdG&*~!IJaOf=T{IB z*~GN{#O%NxAHRlHqjIUYbj6+Xvil533da?wftakaWVLAWN37a(g1Zb2OUHDz?IwE_ ze*oB4fY%5qCdkt^l)8g8TLSXaV8}~0`yrOAhHO`jke=akc0|IlW#9Lkrb}VwCSU zsD$FLd8E62Zo3EdH%Ai_h2!+tyeczd22(K&-|ruF|DC@bVB8$D<) zi4*@iz&Kd4^eL-;=5wi0Qsu3@?jGB5N#T?x9sd;R5r*B_8HZEfz*ItW7Lp!6>3tYp zAF=;7)@jFHLq#Jw^Gom_V|!%Toa@Dbf*i*qZnpQI&U}teU|m zp+p?A95*!42={Oa|5-725w;u`NdPC^pZ|Tox5geg0reUMpRudH`i=P-UT>8i8w7<|Iv7v=>H?>@OF;=kCsSD@?k zOvuE{Ro6fv4i9O00<1-YSJ|5s>IdmhU(yxWLwCQ-_uKo^BiPatN(~pyGX4x~uhi!< zF|EH>;cW^`w09k7xD}D7>ZU&^e8Gyzq@VM%*J_A~FhRf3%fY=gMsv_XQl#KvN04Z@ zvpVL=Z7(n5efy)||9}0CC;zY5UIpE%4Zj=3-Zo=3fsqJ6aGaWTWBea>f7V5fn=>JmR6K~~sL^lw&> ztlow3z+?nlSApcY{;+whn6Ge%^8WW^RJn-^CwY7M!hl*L@u-M$$LgwZ-AIFr$@}^b z+{;%^D&|&D?Ul?h;|bTgoSWS&PF}}cn!1buHwhdWw?r&$Z@7+R4@+gLn14>;uN@W0 z#mC`<@O!yCwT=p2MhcnnG)wlO7Fz8=vezu8BDbMbN}j7uKmMM$+(h6t?j^c(m;UHv zZWKNG2z7vl?fosvm2SkELO~nA{48fRPYuK!1dt1WJLg|J3U0U;+H>);d2v!6c)TgM zy+JA=0vhQq!H2UI@JZq)OLX&QGfrmK&W+X0{DRit)OxS+mHxk(4kKu1_c1J;SZP>k zc>dhW1#@%X6GisQ>EN}VRGX=@!~9wSkx~z}JG*^osLH}lssbmeC#ED)P<(fEpsgmx|7V>rN zNj3#hxCDdVX&8U45pN~SZDL&?WCyX=@BMA>Quc^MH*Lbni-9LTyi7UsokjU)#rxp8 zzZniz>X>XEd;&M^E3Qwahe{QyeqW|ntH!urEKfj{66-wE+kE2h0-1z4Xl{(ta?oOy z6V|+oCQq}JQf7d&1u4?;kTHRq`j?nGe=bHGZ9tGEYPCdZVC>^g2w7@Ab2Rn80!<54 z!V|CYwI!b>dBD71uyw0txZ8ND;hc}%7~o4emtZt&fg@om5~+IClg&DLLSMdod7LoY;2$8VU`?>U#UtGJr^|kJARNL!DOqn*=+WAy|Rhx<#)g3I{jk#D1@cA4**wKNixe1YDX#af-cNF#2~ zO1rB=Iw&z9J5%D=tM$7|xlFdM`Bk6$c_LSedz}8trxZfI^^p_g)>z6xcQk9*-+XxD zY%FYrZNk%9@rEZFb5A#xm*)=px%JY`s;?ODALq7L`W>MQoEo1?&dxcfY{XKHq-KBR zgrlut6r?IRCHb$X#m?fb<_yRr+Cw+1Na&ej52~AM($@XNWx&c=^0r}X;`}a73TLr> z@%{S3+?5^U z0JE|U^9Ov7WFTu$npmT>Qx@gdFnd*h_3w-?uOEh<&{%f|;IdZYXlLtj#U=CVPEMDt zy=n*B>96~pe~qojarP4L1mmU~W;Tgpttzj7&v@GkY}NSmu04@ed5^?PVYSv)Z4i{| zq2h0``AD!0+pB7p3fMujPurs8u`8h&?u_0CMQj52&m!q2_F&W&!!kLMU%Yw$7= z{d}4Dq3+i8e-s2KB&nqI+Q=Y^0q& z1)isTchor&n|j$&eYsyaw(8P5>Gc$V(KiqeW# z6Z|>u{rg`Z&y>%I43s!z9j0I@!hmpdb$5|Y`O(kHeAzKrL9}MmwXnf$30sQ9$&!x7 z^N?bPvsq=*WPFLaauzzN@+xNVhy2@=hlYPA8jXyuN+{nb>reOuiepNQEj) zEu9aPv?6 z3Ao!acr^P?x~Ui|cq4B8#T@wKW02N}KZC%0q*V55i-JcZ?$}}f@{S4TKyZ#0@@8Jl zAXsZs%2(2}hTUDk?7iVVbK)P@^6;Tya)^s(Xyr2oup|PFf%*)YCy+Wc1vbrT$ z8j-)No_jP+zTdtq)RDqH(~mnBuKkKn#fX( z{ECQRw}>gpZm!S%0`lIhzjyC;sdt5hvPOgTf2ADHot-)|saq z;G% z@6ZTc;lK3f#p1u}CJ{DKpxE@3v?52O&t+|m#hHd~nmSKLQ{Hp-bzNXdx0OyHmeb(e zEmc_Ym`8rk{C$m5_DwikNGnVy^88bzFoONdTu)9|&f2jPU0?Jz>~MX}G`o zV4*-PfqUlX0kte_A_fwY!3YBsHvR-D;^Uf(SCde^)~||By|C1R4HoNYj_XY4?ki}~ zZ^sFkywtF?$YZ#3`9qYD9(H~Ew zr{2=$mi^UcqR3ohqDLMLT)(8Faa-i3?Rl!oW{T52Y@;DX@cEx>k0M^~D?_6 z5Kj2W;+=^@C3)=iBgO`8)43O1PrH?P*s-m?aRKL1xb0N+zX)4`3+>u-tg|dKeWAJ2 zz2f@q+*e;Rvj+2PF5j(2wmAH${)T7AHQ;Lrm;BV1<2n(c0k){mmDc8c-tzSkqC$l0(DE(vRDe^xLR8S8zxZI0!mr!c}? zwu0wm^FG=$_N+-UZdMrA3Bbu{Q-b0i8)YP%-Ezl@7t>Nb@92xGE{+^M)r_F>Ij`pK zmvH;)35_IKxsQ?br;d7KCj1``D*prM z^)fp1Va0R1x91>qnFLrbg&iv6Fm`fOmEeKz)vbTSks5HKRd)UH@m05+$rdOD zln?|&qJGE!TrAxFH&%yFv%)(mvyZjz^+Fs!f_q|KZT##br- zk5Coxf`-}?uDbN5s4*!TVfW2O1W4IqcDKrQ6Fc(Y+`jCC=~gU4tP0-twxv* zZz7_3;H>_Sf}>EDc<0PW0}yZ?Q$zU5fTv*Xl=?-4HW?156ep@_o_2zP_gT5&1sdw? zVzu4Eby%)!(bzT%%$;Q#<^%f__#W%v((SC)kc5x_C~_ynuI6Wv3YYDH?D9x+k|_xw z+0X^xxe1a(m@o*|Fl#D;-6XXOD`I6o)1{(SlDzEZd|F9W4SY~wP(%ioeA<-!)!7Pl zva;2%KuGaau5NHnJ3MRVXc}}!=#AvpO#NJhlWVi7NxcB^&S`;ha6D1p==(5 zMNhW>tMzwo{7&p0s|9JR0^65o#W4E+Zo&1v9=2lB6%+`66^c2$D?rw|HX6Nkc>;_t zNhNa<+*wqNW7j=1V{pNR%O@%~@+XtQ6jl-wZ9m<5$(MXU(>KM_4wS69znsjuQh-8t zV^FWBX6Mn}It|=E=ZaP8w;11uAq<_J1FGNJl!; zq}#tF_ocPBi#?UHsy5mh5LJ|?UeyEOnVgRR21D<8yP=Z|#?V3W!h{E%7+-zt-2%Eu zS7{^cwX{0h1jcA}(iA(yu#z#DOtt-`j~5t_EL~fB5%&G!i)?We)T`EFy4 zYa5IFlO5LXEE7);3dOBvndfkqjMNs^9MaXu;x*q$QikSaDgt+S2zGprTN&Q}lZZ5q z{COFGic)hvo{VB+>yVvfp8qBVO!a;#qQl#x=HtLEuXgZ@aXmykn14~}9|fnj5Z#5> zOT>xL80mSzKMF8{!b)358;tqu1|0W@T18tC@)%xBqdZ8|F0ZtY!|S!=@VwaFW3q_fq6tq z@G}D8bvGaDnnXS4CCQhDUDk`PM1!vwuZj9UOJ1oz1ui$}PAPndjq~u=o;W~oDZ}9= z%~{=Uh9>3D?3^kxH1M?E0P8a!<4GmXwrOEvgUOTRkuueDB$z71G$W zG)#(P`(ODB@-MO2l?4W}!g$2zebtPb%mMG(rcVJF14%>HB09R7?wt%J!4PYwohsM! zjf)<7w)IdkxQw^(Cl$cjl{?D)DHXcvKJj}Dk)-+Gr2;_nyC4GTT~x%M~^Nqvb40P zaJYJHqg}{WVn%+Ii>qI&Y#I4y80)oX5rFc5n@odOC6Yn=9GPMavJJ-cH)-FH4ty*P z0hbo+)$o}vaYGY)vK8(`zNl1aWz-AcBo&f1i{4}36oTle#OXqL8~2Y`0EFv#7z0QS zb#-v_XRQHnm5ep+-7K#|9KBdG#U_YM2X404Bwike9Gzj51%rlU%P~k`BKIIaIG*++ zF$gQBUV**pgW*Q$QNp$5kNL*fiTIl!@ryeQS5B8>8h@Q!7!hf;f;x>Y{+Fru5iWgu zvKe%=*GP~ZeMj8s0{>9|uCe3aEMRf1ZB z{r~DK?&tAfHVP7Pw>}y);-`E!^TINL`*haZ>cKyXf#F{pF!5>lF&#b^fq~=9z|=}Q z#k(~@$-3ruRlD~F^(o>?Y*nBoxGIH7xUKM_o|z?n=(As%Ax>T7dI)1n)?USL?=n?s z<)YuqdYeffuz=oSfTdmM@)vb;;Pvohso}jl-W+5`t-uRXrq8)&35pb6K%XQYzadH< zs(DA;9kQg;f)6bJI%ADJ6%ULgs(;2^9b4zf?m64Ozhis{s|T3@=|xa9V!Ls~^~?&C z{D0T64j%CqiITK!xTtBY0?rXw$Gh%M>mbznOuNmz=U3pDx#j9g0uDiMsLXP_7bjP? z&65wh-d1Au;47NwyY^Y8UR|cZuJ4ItaVGjH>bEkByJuexu~T+a|4*^{jcR8P<9QKh z1}o@q?LUf_g8wLnmw)w=xlbV%*NM+SIEHHp!|ZxYiRWjQo5y7#pgk#<{9T;F;&7ap zILqIspZlGeuFv_!9pEZlygeSNc)8#?gAgpj#`)VM2wZB4ECd_O^6D0z_s}?oG>vc6 zsmEWH_+}|inB2I6qsP>CbL*noo&pjiuj1@ZDt0kpRFhU_6M-i0sdif7Mi_lZhRdn#*^SHi`L>OuS1*kWxz0M zL3{V}Z|nBPdA0tQ7i4m!Th(nKy|3dOz%Ac#6@V{Fh`4H!PT0#x&%aFpZY7x22Wdy! zew0Cax3~I9%L_g91mk=4$5VJJq=6J69VamXwF*>hRQ>UF{-hYns`h{SaGd6lgB>yw zL)8fXArMuN7*G@^bBBL;d7gvrmu(>ecLmcGt%Troljuv#Kr!4r?dcy=VvXFDJL4S3 z!nyWcg%6e0R+slG@`%cqqG+hR7mB(~&+GQ%k-BN2j970Tq1c#X4zC&EPQ+`1Y#xfF zwPtWsC(QX8RLI_3=AFw`@#y8|m>lsS_$M8cPmuZKZcmJ7o_<()xeXm&AS$X8s49fd z8@vvFX_t6!YMA&?AkveW1qeRObFwAQ82C1iswBKs*uW?lWwl`sr+>X^z}aUD@-H&0 zMnHNGduAMIr0g~iwp$WD1L{fjR(xK$pa$ERs4cC--~ z{lm*br2y6oQhAO1u;%F%I674X@dNxWFHPPZ;8N}3xflMaX9WQhE+XmuHt%=O2acr)S)kE8y#%T4PY zL2hvR<&oWg6ww2T9^z$XA?e>q?}?HTEc#5=!?(eb%>rOmA>ml>(~xy*1|T^hd`;WK}ehy z#v~4^CI0c0qc5*Houk43ewbTf5%uckHSG(}pb6r$-cHuj-mB|wFu6xGc7W%L$uphM z`+m_-;`&#`KJqma0+Jys=z)Aq7bz>Gp3qdrA99!kxiA4=AR_9UG7mI+Zq13~Ul4VY z$sI_VTMpl*0v>Ga5k8?Y-D;pcI?TZRgMcsEjyqcRps^ZYQ)AMRibB>89V^VnK03f( zBO_w(`%eb&z4WVl_7jNkTvteu?JQn2qU$H63fEz92@`VRD)>uIS@+-~eBkG2fJ~4U z%C|7@)Mfq}<@!L}oZpEyfeI_ zKXURAbSQne2y;44Eu=X+&S4^i##Fk+ z10=TNn7yXjM@Vr292rEL60_g%0A7#^rJjcHNjrmw9rx(Dcr?>^zfcHQDT1b5dK=7k zO2=r8fB$54c1g=7wQ$g&_bgnWLvGiy6>*n*HwcW@$E8jl#k&23^#%If?q`$gWI!%f zO$twzL{+d_kt&qweo5|$_)#%lq=>q{@fvPiF~EBL_KML*-8DgZ?HywU2&#%WIYyTa z8}4^~zkLVJi>s2MU{qo>BUG(<5~^Eb=>og=vB6S-jvta9pD%7;EoOJiNMSUqBuLJG zcr3_K-c#0TDP%3QcmHF_E@g-H?K<}O30?n!4f~|@K{OsW-N_!%WSZKT z_Gl+q=6srd`g8ZA_B3MBh30h|mzVt$D~(#*!ag8sHw@ijK6sHs5q0@w(;`8u0HtZK)P#c|I*63ZBD8V}-(&uiPc zH8EcT2z_i-+eXnld2CheikxZp{5q^ppL#A%XT{4%0s$3}isr8w5hY6zWr1JH)0aQY z$VYTZ{yhgQ&VI(GNZfL2aMZpBoWO)npu5pY;Op>lLA_~>5ge*-8@yrXc^hTbls(w9 z2+;9+>g8+}ZA2kcfIhBZQo`Kv(O>Bqdr@rc|+ zcmAWeV%b2PsS?$Ey(ba`n?SgX7|FL_J#+ZD?}xxr`FdmG57gFZ3^ zDdV^?kG@8vI!P)eL@nDnaIcLt2H%8|T;<1$uCOQTUuHH_L-Fmr7U3L{$nfpZLvSxA!C$hFD76`#Uo! zkE_@1W^P3Q#&@aGnY@w9FL6)#?@ph?td=%j+R0I1ZH9t-EqM-#Y;yu`IS)A)9^zk-n`WMH$ zEkA4O=Z=R_GV{x~fRuAhAKJ&&#V$gB!CI^KG_k_CTvGWz3Xhp~6;~5hS(Q6u z=qzPDMLUs@=dwsA|M%TYX(qmVHGWNvmp3^LMzTRbe^XR6Q67byJ4Pimu9_rRDd?L1 zuA-&V5^dGGb#P<1+1?L<`s=o)o$|uq)g_23xep*xBRnUHC2xRb#qrNhe!U7@^!{)$ z#f*#+S2GXM1vS9y&!1pxE-0@uMK1J&uGRvixfMw`Pjj-wuypr?^?$WcE(YkV28bwp zBzlccSy=X&W%XgqIsQy#z5kD$M&Q(YPx^hsAvfI}2Laz_^eVG1o3F_il4|}uG8a08 z=LjVtPt$ukWt!9WnGQ0>kR*IY3u>Hjh0h~1iHAKv_#NRc8EOu{(AtA=N*~^Y8rFPX zz4o7;kcXD5xajjv4k`>4$nwHu_>*(bC;gG+eqX_OR+#Bxad>nr>VUTY8U_`3syM+Mlgj1fhd%)3gL%7+9XQK#G5JTqEfW&q z0_3*>qrPP?2xH)6>c|+VI412yeo}B*bZ zYvZ9@G*f|25Le)c65ADy0FWm^iEU%;n?Ne%^;X09Y!Jb;sb{OZ&Idc}s|Tlt=zMZZ zcz4wFkD}#miQUPSm$~NEK89{l~`8FO+7@Z&1TpZs`T=4l_Z{uK0=HdYvSjZ)?^+3JxW!oU+X` zFAuu?C6M-`N9Q@n9!0Hs&xuQ=Q)T=s16uw@6r+NHvEnx}EpG2Rw z4&i9#38+EKj~$ zv{bm^VwGzI+`~cBP{R_~+GtcB9%r~p@GEJ+z%m=Sq>_6T)KUT0UfU)ww6{Ja)UC5c( zb@?**D_L>mDp`ktTfO7TahdVRg8Bxu?Ycr>!EHfHi@~bwq@;vJH>tf^HR+nK{YgnN zul1A$rBZq**@|aTvkDZ2JqtSvMqoYL&Bk)j>{`E^xesp57`eiL~+>3{5_lGf@zTg&! zIC(x@P<*dDz#+f|OBvSC=s2o{;^zHf&E`9tAbFFTJj(o~o>ewYd!D=^pw_(OlMm)f~AiQ*E1FV2pvT0BUpJV0GWF`!F;Q z$}uXyJ*^)}FWTWl|LlPO)xzM$^Sh;bqX~u0O_>P(&7lylI8mkhm@{-yc))I$`M?W& zM4$#lo?&}^i#rwbG;KD- z9{Of-o>nTLSLk{ay`tpctbCX+E0{=x_f$IjC!>em3P0n@RvYPZBKq$1bwh-;SJ?`K zh5(w`P{`i4lMfu*+3}`fW+~v#d~Qaf*z#BDf?CFzV=%*fTTyhqh1o-Ej;0ZGp|J)h z%!u?F$|ffXWyDA=*f)*3b0qw9HUSmDh4AaN?uChX#9CteDg-?|dc%viY3g1>=AyyE z^_N9LQd7t)?R-mZhx@bT6*Uhn5*gHPn1Cdx>Np-VlXX6BF0mfe_mT%m#LXG$7_dt7kY* z9t4?D7wj2w33oEQokgBR% z)!bgoj~`C{i-t-knvu$>d&`0X&O9LZJ1;FK#hkaZRa504`hOmKNHCl#JaT~u6>MMB zbon+Z*0}nJNp(XPPMs#*qcYQN_H@HM2z+iA;HXyhQfpUM?|Gj2mAZI<50B(ZAm6Dh zM%f7}3L~5-&1BO@R`ira8CvJ~kRUWzkpwzyH^2XxVsPOL6 z>>KZs0hX|>Fo0Dd98TL#g^z)-Hf%ml_coqZzJKUvOD^jIWVIf zbe@wGm>s@S5OS@1v#Tmn?#%qvS=viBkHQ2#yUi*D$DIy?vl&mW`ip%`%Sz)O0dx3x zygo4sOjp;&6&f3)KW9B^-*z6UcV2Moe3)Q#;VB?dqRH1eUZiNHSe4mv$66PW0l^r> zOLbkuSA|zr_|M128fC^A{wnyDo>aHb6}4V94Y_GOQ~_1Ntgm;8(hN2SNi=j6FWR6MN50!&4GC|ak*)|F0=iPoXjksq!pKCPM^21;7MdETJH&VisL&%x^e>Dh2Dw(17F*|$ZATS!ja z_w#$f-|LL-zIou@0;dhCiU!*c&(Zw?T|1@G=>@a4UO{)(}kd|rODKLz{x@4xKqQt)SA%GkqAC*@bCTUAs?YG~T& zthb}zL7tHr|NKX+W58=)n&VW(ED&?0zahHq5^vUKV{1Uw+ci5e>QE!alFK|&o0l7s zM>cj~cH|{c-9L&1;%o&-5dSsVCg<&6+M}~A#S$#Vhb*O_|C!D_4fXcnkdg#8m5D0}AF9)qg2``YxuAfKOcG2(~BHt2|&! zFts*M>~Md5<>Yd^xCDNVp zW)ZNpgCLe@k`878*ura)mmw7ilozLd`&a!6R+kK{JFW#dBRN4#|)5f z)|SEkLh2AvFqt3@lyVM)+CNiweHa(f_kOQ?{nPz7Pc4G;Z2j6YAKksVQI^T8IR^%c ze_mj&AW9Tu-weIX29?TEY@<3tT}{~F3^tLRpYOeOteH@JB+Lv)6Bc*T{mDbav@Vno zEN$l3kH%L@tkm3jy_$3V!WY6K{UB3~ZvjK1BM(8Y%Cu4AAne*u!-=}}Ms{+Un7P?9 zTT;wNS?(ijPg$)u$GZbRGsX#`*A##k05N+3tnWHHq_1RtJPZeqHcvr#wAD>o9~va( z#SQTD{EXoj>v$u$uAx~de2PXp?e(IUZ@`8HF&sGFY;}xoZUIkWV;DR@#KhM^Iuv5R z%~>>pM!hf?69{4mpyY3X>lLG61sr)>2mx3ZumhsAZN zW{sz@L^Ur}Ww&l;^E4(yimDR0t&c0*4HThzdZjC1_xTkPY56`-A8)6zvB3MD{4c1l z1+Ft2-W&YF``VXwJ;g&;Y(b*yyXhFR_%Or88VRxi&(FC_Ns5mGP*lW^)V9hQ=WVV{ zYSx!kMqQ)3oOrQ@y-ivxwk4uZDrl(X_w0}jY3Em-FpaigXP@yS)d2NxbVo?VbSKB6 zuvxwAkHua^$)DU0CTR5wU;|00t+8LP;x(NP$WALcc5k~-e(qA=u8#qA)G>W2Qh^GO znG2keD1#Qixzt(KmU5~3%H{#0SsRGEOq!rJ_|%nQ2J+B!$YE4v#R|eGfj`u{bBLju zW3+c^*!&`BBZa@(|2%D|5GsIUk!0*IBgnR`W$inK)@~lo3|ozyAUIu0oV#46!_+=w3W29u|;gE7)2SCtk4zYkb=|WvL%u zJl(u{H{^CN%jgl}Z#j>Ulh+thL33-_zMi9m6Z`Tym5PBHH`V%2WZOyE;MHnrkF#eR zZMW#K-|Y-S%Spnd1nR2amoD-4UL*DQA`aHrFPf3HHD^#!xwXV&M09HHb4@&AgUO^A z`p1M1{TRN=iFDwIj?Tg!gU?*p#}~Tr`s`J2>&C$AMOmBVYdj|T#(43wpb*B%2-rP% zhiB1Ss5suu{m=6;H&)N88KHTKPOJzrHG~)Rml@Ux?+`v!R-lGN%PN$Wsv6I!FNAJV zUYLy9n_TR1VNjq4Ln(hVlom=># zlm70ISh7SP2ogku!u^H5n&7c0Pj>0r($R{RK%?Xvo^15EP zulMIPInqKG1QDGo@;1F&ayS7LvfBly19{FeVeNcw&Hs-g*gA?&9sV4|5>`f#gUXST zmF!j$Z@VJumQUHwFZ&H9DsRg$Yr$W?t=d*yTlVIk??^+=-pC#1;(p)c@98BO?RBP)6U@8H+r=jmW7tAw$gP1yci_{ zNgK>>oN|)RM+XYRPn{@H%k#as1nl9v?A4y?^105UMTL)rjdckenI<(_+^71#zvP7_ z=+bPqw!hU9yVOB_@yhqX9={(Wpwzf`MtkO~I&Ob`fYz}SJRYsN1M#-Dz# zcnO&b-(5J?99zO4p4dz^DfanK006K*Gsr6<5?R;3^!}bxuJaN(`xG4YmO7?s(^;SY zT}nY)D6OC8Yn3=El&FMs49z#$PVT%iSJ9AHU{=;O{a}ystX8!t^P^vh zxo#rA!|P{PuMFwZHzosIz?QVM=5>P1=Hwgv^nH?F{od+OO<8t2_Vz!ZF-bGul@dyx2v6$2cafDko+(NaQ=~S@an_nbpwtxMLNanw3=!r2N8+g{U^w9$n8op6Hy1V z+!e}kL&ofcdgdT)Y}@Y^fldNR_>~)KloEDKP$SQg#jxOg4oo8&6a!qf2ZV-NE*-zcgan+qpWS?h!SmqFP6YR0f3=JeT`|C%OuiyhedP;xJ*K!tX?VB18 za?0qdH(3)XTy8PWj5PP}lJt_Vlhr^En%P3!dj%1rezW#0BJRhnLA~W%E+EC&B=| zpRvX&iQ+y>`4 z6Yerm4Q(kjeXe22nKbUbZS4{Yo~`h#;)g6+^bqDj0D#26$BmSF0s3=C{46mO|Bax~ zu}Pj?ru%la2h`IXd^IGj>DfODV9Z6+D^iPy_Rf_j>WBCaKZYm?~`|N3dc*Q@{iaj{=-B=~O01VwiGRMy|v z$+s6-6oJ>%{zt~(%D>V75k{-^K9uPVuXmnoNNY&BesZoG9Q?kW<@=FSQChpDgTMw- z>ipn+-}lLb@0m4yJe6U=6`7*b*G#g=!r8jDB&{gS_gA-r!%AODq#9VZX>ExuynjGX zIyglbR77S6QiTauPC_)eyuidDnnvT`Iy|dUh9Ff8woVO*c_d z1d%l5rDNMsMdz6G8((zS{m2h}dk;O<;s@nOLnRP@e`DX+TQL`XGmHCac_1~D5`(`JxQR16kwwlHjrd201_a5dwklzuU zh%n=LaZ$%Tci+Q$m}IDJy7^8McXCNvkdqyqMwP#~XX!Q?C!!p%>qD3M^V;J3um|j< zjF(HV@3HqeOe(U8sEeV$W0})0dQ)Fr8Oe3Q2BB50o>&ZB^O=Y_^W9^9Hqor2FW)_u zz))DU7ZolO>V}BAxV9#FJ#wR;|FKGnS1>2Bu=!YlZr+ki)upRYdwLHp@7rJS_GH&c zX+`hhlM@*d``=FMT*wg2ll|uICl!H+!;fDSkn$l6xW@?) zgP-1R`ul;j8E#<%+X*R3N;$#L55Gl}S@5mhNN3?*r*FLGe~amY_`CfzDW6P9w83w# z4v9a(JE66p9MUEn2Y0zlTW2t@1RpZLmKr82T2~q|t1;f3Oq4cJ<3CZ+)5r58_H8{f z#gNWyd2w)xmWd3QwL_Q_K^}So{}B@@Uk9+WD`xk4c!})_=9~H4wy95-ObaAhw85gX zH|{7*D1Q;65^rwYiW_%12-9@)x*m_q00f^r(hk%_D%fufAWP=tWga&9%BG3{Ua6Jw z=g%z)flu`g!0%E*WAep*SMMeejlm`(H)+P!gigH-jBV3Q|8l-Q-KZs^aTD~io%*xK@utyxtGa6dbDiI++v4SL)^ zU@|!z%7+U5{3CArDLieO&*Dp84t!b1>T0@=j_ZidExk6`np-fVA?L=Dsg#N)Yk7JD z1Nz53vZZJyVfTS^chw`kxh5^vt3#q<2W*^4&~yd;(3pP z*tIynYRGREX!5EGUe>0COqi&;;^gzc!~(p#*1q{uN!q{GsWt9Yjr>40Zic$>M(Eaf zzFlL9c7WxkDkX6%b=UnIfR-|W+zsv1-6A^#?q0KzvvX!S`Log77QJ_m=XxL4De)I@ zUux&qf5uJWQ$;iT>!uXj5PP?;K<*}x@1Oh>e}}j^YHhFuaHAQul(l5{JwNl4K9ZF@ z=+4-`!WcOuSK$w3RY{Cc%v0WNk4=3~1JT-6C4?;kHUe7ACr$;P||Z z#WGHIX_6TGl4;Rs{Fxk}SO;e^A(9N|iptXPuH3=Q7EYddssz#k20Fe+Fu9 zJih55#KgSQNV|{C(4VPk)>c$sGXm`M@E+GqGmCgim>5s z8;gOC2|s*9sVua>Iwc|gr$3ljCWP1iJk|xQv#= zd&#i6LvZZCf;>~(JHUNn|bzG~3)5bO_SJ-uDJjU3m0d?chuA{rE7k$5n~%j?Re{=@aB;M83{dkW1i8 zOAX!uy=DA6l~qyv6`@mX`di4!@88vX)bNlP-Ni_2O| z#|`kn9VOmtf&wOc-Vj!%4_^g3C-9&*H;}zmcX)=n5V##;;(qR3$R1eM5kDJ)=P(U; zyt|h3?xbq%1Ii!;4-|1!LiXT|`l-G8InxK$v>G$)?ZxMMd}M`_M4bXzR!N#ePv9^z}-XV&rv7PAD1Ho6KHKoQ=h4Vm(`!^Feo> zvs9P7VQ|0x)Nq8MEo8#4TKH6+sYSJo!cKjqwH(YLk6FVty_HB|b~Q36EAR`Xgi0L+Ws&Y}U`9 z1-Dp>srt^^YOMjx7nL8*Ah_Z=gt<}`!jGx)eD@9a3FzjbN|k>jv`)uFKVx~D^S@nX5Q=m-nEyqn-{2C*9R6Ou3IG-Stvo%@olnPTXkz1w->KVc&$cx zOH}&12+_X2Kg`?KK$p$?NT_%NsWcD&#b%{U|0Y0DF5~V%Z>EVm6_VQwKw@fFy`_E) z(KmA&G;QUANk7PRJ6yc@&)A~Xe-yEw$qd7cK_Ote?YV$G-%d9d&KxCtr&kgHRoR9J z!$!Dd>oHM#MJrz6xy<+^H?-rlqn!ES>>+HzR(2D5``qieC;HiL!mE(c(2qRFo-s6+ z+uxGXZM51If?g}8bXq-h*kSW}!#$1M$FMO8HwQpXiN`2%g2ihMSZm7s863q*MP zt+b&Jzx+dKqUQU|$tKvgdC~90O&qTv1GJwv zR5s>Ix4VzwlLrpsJQvrI`mX2jyuGICN%W%l5M5l`+|3KJ=Dtc})k0yFXog`mkE-8p z4610d;$TlkkprKhDZ=nN(b5O9^M+ft11MoCF#;vbb42WNZJ83dL9?^)MR!!ZboINw z^C~nmsdRc}d=b%Rh<{;V_P=f9)U~VE>hV@Ed<a?OE5s{B z_s2{(CBq|CKLndKDZ$@lfLFc)?CBzfHlRqTf~?PAAeb1^{+CTa+B36Nu%YrrI+==@ zU@{o@V>^UN@4ByO0na}QuH@oA;N>?+mB~Du3b6MF@VL3YBQlpmKyTE6Yq6|8C6S2( zhm4TZ$`69=I^G;=Ekh7Cv;i2(`;V}x&z$PtoF#7is&)#Z$=CSYfBFO`?(8KYSH6Pk z>-L-Pf}ehT{8we*{&1t@O8_a{iFDfnx-Yys-7j&Np>r7VB9p$WKP`&et9W+6v--Gp z{51Cc0O~z{_vyGD5@VeuwwK(;tDa`8=@5U`VlO*7&Wt6e1H-*XDysjwAJVCk&I(b#kyU1=){35Wq16?-yMw&z>VO(va zYE{uz?Ey$oHW{clC-hmDu1*YGw0;C?r0*lilX2O0<8|tun|p`75Ds zQE2Qg9j&D$9a_ib9Z~a3Lt*aIf}c}tH4uD|{=U(p03DC(qF=}Z0sywWSf9wmiYp3> zF4B%sVp6@&8mSo5L0HIMKMI`nE>vTmDi zA9CN!RsXjRCKpJ05&Bd3UKqg~>WS~IBt9L7hPoB$vPPWbx7HFw_!&IqN%O@0Pm|aN z0DgFll~h4gP1Y7Y36q=QRN)mBbRV%&T` zl{id(S_mdG3E;l;9odXRC_&gweme5gO1@6-wo0|H$s@o#UjvA<L$qGD(xQpMWlM zZRmd@33KIM0W~9zkkw@mZh)sy(#UW%=B4gp(%#aa_jLFN)BDOyW9k9lw?5wnN8Wr4 zI%g=;1wKzlD$0vi`s8w(l{Zq>zBCcOWSCAp-T+7t3bZAbwCWJ7h_6S$wu_YLh!mIv1~WVtypd!(eqxpHpgEg=4nN{^7yyPqODe0#PmmiwF=6Yob47dqqd=xE z8b(g|KUWSP1|C8?AWbZ&a7`j%co30D$R$eOzw+ggKx6p7<|O`vv%# zHaho-okJwFwYxO&p{W~rffjDI3 z$wq5^@{(LUFD#};42OQS9fRswdxbg48Gra9aN_(fa^)Mio;NFX@L_kpt)SWEu(*8= z4i~oN=E?;)Ff^BF=tSDGwg!dAtaI;qo4Qg$&i8!(P_Fg+z+7A-m9on2v!poic-uK7 zfDfC0!o8~ID(;hxoClV@Yk^^o>{co%>siR^*K)#FzAo1-&syCId7MJaOJIa=Deg>w zFfa7y-j9vW@0p9`$u3k9w0Ho&NPC=QihO}{P97jr$q}AE@6n0B(z$ip5A@k*7`Qcwv`2)_D6mXdVJ#}s6vJ6mI=EY1DDEHk?6PnLC5JJ;QC1{h~>3IQ-- zxqThiY_B?Hs+HV$Udbx*JML*+YnH+W_f&27Gx1qC?k|1_tA^Ua3!rGTUrX<1I6QE- z@poR5_+(n!$lOWPA~k}YX?Re^72ohM8p&y`@k;whUN=ACKS?1ty8B8H8OP?%n#tLdI+E-S%#9aB={p*J&QL7AshuGvkywrc9 zd|r4~ED|^>-bcVj-sDpcfi#5^Tkod;H(ipjtQY=)=05vq-IQ^NnAET2Iek)^_C`tP zE7X{7hOeXr97verlC;M6jW2k5(2p!!t^3 zwwKKdfT-R_kVhH5SL7xY2-^QWX zX24#cIYBE_oQs_PgjbyqCF$t2K!qc&IV+TTz|Z7438@0sRH`U;F@L&hr)c;mRU^!| z=A{{V8BzCqs&M^8nJEo=jeY>gg&2H;!QQ?WuHxWA{<+-%i>4>6-ErsSAI0R>dFmb; z3=m==6`4I1n!DSY@psjM2fp>vnCTxyBV^yo3utwG^Q_m{f=y|7V6Z#5wy%7T>sOHn zA&fjBRbHBIexE+)P$6`aD;wJ1=0*r1k4-bwBj)Oo#5C^A*gQTv-$5q_ayna%B;xi- z#d&qjjZNg=E{4&SETb4$-r&5J6CoHjj@Er;KO$C{Cm+a?T&X!e*zH;K;5T}5Jik~uS@JsB-uModMUW9-u$q#}|Iu+2{jqJu%a4#>(PL~EptviAp%iVqx zeJO_a%`D2}xD+6lC=Hdve=NrPb%aEe&UP~~bk)pK&TojJs6P({Js{O1oh8_{0?KBJ zdk5`)=#w(Wf3M#zxyEnl-Dq+H=~c#LHw=E)!NNUVg?+lkyLWKdJefOqR=$IZSYAk#d1kCr$R09Pru+3a~;lcs>vp!|etzq{#XD zZE!FTk9+R0(tX}b%0)I*?Xw^KG3-iv&WMNCeh0QwOquV0a27ir9yi<#(i4jt9mK5C zTy@s4Tci)6%=5S%Ql5as?7XE}+0%#P9MXfic*6Iu6L5FroEkw4Z3?;l#Lds~<}>4d z7Ok*Lcgh`-=IxwUPgD?iLxMWd0xP$-jM9&mGmn!aKdk-2&9CEcVF7vgR)XE*@5ros zJ+xPDf1IE(i~{mLk>s8m zA7eoti-OaLhQ{8SoRs>=gnq!80Wg3MNnby8B9241K;dg zTl(hj`kD^e90V62_NxhMRu!Ec75OS=|0vQLKIM?E3w>$aPb6slO#Mf(DjaY0@m_s= z)2|Z{U*ItJx?>rQuPM?4G$)U?|J?oKJ>69o+-xris|uS1)ur`0G+-qy6&mDg8s`%W z`?n+2u2=eL$2T)Ua7fZuzBZ}lpqK+erm#P@Z#6W>9pu5T%ZZW$J|H4rNF2Y~&%2-Q z=FPaHa%vvTKPl#6*u|BQzW)lc!G8>9p}itgUkO+e(tlqZ*F^fd7tx)GZCfNB)14+> zYr3KQc(&WNM)ZvW&l8m>mlgeaKlJr~oK26)8IX-c3v+Aj087#TMU^3rbcfajp1a zF{BTVTUOju!_#i|L?Mur3r}c-KB|-wH$eJo*PONy_Qv4WGOtgm`cWw9Z~Y=?8m%Hn z=;d126oS3n(;@05HkH)5zr=E%VV{P)^U4@ePuET3HAIk$KP{8*y_cC%wH~t-sdc?h zT|}n;h&+nC>%sG;3E;-9xsu$EU85tQN{0w9U?V(w$pm%m{{EgpZUWB&SbLlNJKSha zcxRhk4uFqV_3Heo;PQ$NthV&Hb(LGj^5S-0R&_pk0&>^dEf&lQebV00&~al5hsl&m zkT+;9BGAf?QqMg7&Sk&hKcO+{RVXYdSKhgEz{&d}y7r9f!8yPJe<6n}Bz;%m z$NP1$Ti34aJ05C|q8ejvawk#@`|xW4y;AD~5469394uMP8zZ4M>K>%{f<4b|Ufjb2xa)8nwU2aC zP}!>_&8wt}W}_hxE*@Xct3e~&n^j+xMaUldDMtB2yoDJ&%d(|k+f)j~$SU&X%i>+i zh9b+tY)3_yV!(FukFH~9{ryiZ!(JJW^rgSj$?x-Me*}G<8R)7aFm*qL z^SmOIe<4ijVxe=K!@GoQ}8)VCQAcYe~^c;aw(ZFyU-Gn)L5 z;*XT+c>h?*fM-OhIVUHAg=pha&~YoUajH?TdpuyT*WP1Pg=DLR?L-yk)QBQuPC4Kj z7PAxpt4sWwSAC2oKOXQ%>5;y|q;#Mjm94=QQm5Cv*5+dx{jk~SS7b-1VQE)EyG7!@ z;3bejR#ei1-+RLg3N#$3sBVuZG#m9Oj%qk%-`$axq|EW-QXus0Ld3F|JcJ0uo=RRC zCPM!_;mR2DH|%45Wt3Vc2uRezcwNgj=a!_$=^OoPwP(+G!qfmUZ0qq8M1!mO-vSl@ z)4CxybHEq(jH5xyVwgwE`Ke9V|H0OK2Q}4(UB5h{qSB;;Q~^bLZ&IS56cJDmBQ?@Q zy7T}c5s}^mq&Ec=>Am+ZARxV$B=nk4LLlWi`}yXZ_so0d{K*6|u$kS@cHPPS8tg2}C#=THIv-zQ)HvDjS)98! zN`NMS4iVORFGWbvV38Ra_{JfsT@Kn}I4us7Mvk%XWn?AttDb{rkNp`Axqiiidfq5P z7}WVnQyrl*4~sui<%%84+D_4)6;ww*ee>gSdO%@6h<#BIT)8`I^yT|i-&v#Y@uZ#{ z(ToQC1@>WJ-DK_2oju=b0e4!3e1Ux&XRMc=Sp8;k48soxtN_ZYL%z4UqnFm;(hhbl z<=C=Rtv+MV4%^Y6eSaF@^oNct=}r9OFTos;o0BC||M%i;j0cu!Aj6_lO+EY}`0~=-(~`)4kOY zjUtpfP}lp*P;I?1gPG3Aoi;@gEONn(689MOLpTD4YK)Fk*xadf86<$|4#g`HM?`)b~V)2L|e(&Rl<;Xbv82=z=#!Xk7-jJL>CZe zHxa6=Nv)T4!{HLD16}Ir~-n>HR8$<8#dh9!`qQP0~ zW9;fYC{_I%Q{8AT>$235sE#^^eeA7^Xw2!rBCkU<(Gi3!BVT{Ug2KB=a4KE<9`P1@ zXB5L(s=SRTf<2Xt=OW`Man<0b~^-Sy5q__WfCJOVDs^Cmbj^@ZGoC6%zYyjZMTwAqET)i~T5u@cd z%X=4rtRb`USNCA@Xe)X?R=ouf#>s%8t=_P!GQ^=fLhuWM?)M|Ay(mz_2goU1jBRIn z`yMwxr~4xH+Q>fPj6MW6gpCn(2^}K`1Hwz#2>uDM!ErDp-i}*uRKDi=g}3lH=(s-}ts zZ=ac6S#kvV)fSdDli!uVFHKec09t#-QfiD~-${rUag|Wk{)-6JX_p=6>;9QmvbsS@ z6c)2oaq$)p*G1D_x4ECwDTTfoPp+fthjY>KKQvl9zXj^flKz_C>SkLO*@2Y)D*#BY z^F_zr7g~s908!qPWWPSyX+0o9e_CGb|APg0t@!CMga>aW%rsVe`{cZv4)knxmIy8| z*W4<-zj>eHQ-1j_sUy_mcCY5S(?D`WZsVd-7y5vYH%VW*T>a#q7lT+P?Fcq=KCOqr zBk&e3aXn|*E?g~vB?(0r?@bfd_vk3=U8ZClOqT7)ev{bVV8D02F%5Y9V-9((OK*#~4&Lfq&tQ|}|m_BWfXW_($A@MiJnipO5m z^bE}O=MF|&zONxGJVs?$)mLF%6luuD(7uRz@>+>KZ6aN(B1mBg+4PSizLG`yiM;LQDakyuokh(uW`JMXBXsEfHS+;tATr!Hpc)Z`^`o7<4F_qX3yfD~m3giaRcJ*xubAl@!ElaED%wkS?clwN^Rf*zp8_xCTtyymp58 z`V_P^n$7Q9ZpBekaX9WODSY{fEwYt5oQnVO2z04ZSO*8IOBMxjtlj}XH3h9@Ln?bq z?!$RWC&Y)b_<>0mqA@UzEUs3TR*4|G+ugsq{+^cSGn^_Lk?&^_FCj*~8vkw!Y<@RM zq28xFkRH3Ne<>y{^^Cug8(s~^2S<01PI@}VeA5a z4oeC@C}1q?(ScC9@m!JyW@*(R0N(AKK%WoDK}hg|w5shv>N?yCzJM<5Z;W&Gy`ZXj z0^H885=h}c`86^1e|gf_QqiZTyGk8v*@#NawSgW{-^*1%p+DAlm3Zhl=al%q8UVko zR^2xV?_LCb@yHzBhl4sc0j6Jg5V^Mn5H@es4=j@IpZ~|#6#&S5AIJ1PepsPjCA{2o5ogQl+jM$q(T8F z=CA1?Koe~e-gONW39MTgploDD>R)Af8G0!?qgOv8wU8qpjNo$}*S?3c(ubYX-I%X^ ze1ih+6Z(Ad+RedNd6`Wl?j%f@S9IrOS$LmPUs;{7KEVcd?-NTRec1C071L)LjXbp> zfU>A3fK+Fz20i{7_SLKPmYMbVfjZUbQMo)>aD?yzA115MrLGT9!K4IMJgdPvH*|6 zP)DB8&o{oKPm9P)ou@tdNu(#E&FI{f5f%4^+_m8=tC)%u^*L6om(f$gYnWKL%m8NR zg#!meU+#v!Ln9Dakpj>b3VsckX2U_M)4vfxSl;z{xuqxhnMwmF+(Fe z7Rm-*yp6s9Kcyj1Y`K?^HDJ^^#|>w*g_-KW`d^(NuZS`XE|`HaAU83~U)dxn&C?S3 zEFWEjjeR|1IlTt&3(XSJlKoWuo^1E0^6Y`l?s)N$;8{?2)V^wGxn6(l6{s&xcTR-g zL1?zlpCgq}8(r9xjH$jC(ivbRq){yekkWPf+io>$iKyqyQczJM#BtRd2W%CC7_;{?o)J*M>#hb}bf3sQJYCQ$LMOj5yc7ld}se$QIxr#@9Gm|^X#tao>A9eZp!*_DjTys zuwPJv$@>?_fid(#}ZMz=bt~+f={iF{|gKqbv~uXHgrnYhVjZ;O&b5XO50Ly%ds`lQDV5L zw^kTTbjJwvnu(9aij(i?@dxFh-(-Ki`8|f|Uh76dY>sk(6z$?+PUxy0!*JQymNCu| zBeY+LhEPI3^`Q1Icd)&RxmfXVo$F6BCWpBW=2jI*%YinnxvwyYuI+ZE?G=UzpG=Zs z_oU_GK#_pfkn%hSZm zW~uZSMjfwSA<~kP+ypW;u#iYsiKDG1YDYoE@09eu(fZO}t>n*43Evb; zA^2tECfDHr@p_ztbpccl#!gD~5k5^XQ+0Q@cXk(zo~Kz{cs0fzUl&+jhpE9`nS?Pm ze|~tFElcrIkgciFv+a+Q9|B#M@2KLaNL=t<2 z;AO!Uqsl8+H-*_l)FftzJQI#M!hwW>eAxTPZMZJ3gc*r1nJ zt-?y<@|(+sV1!*u2ix46_YcqV=2mR~IHX0OsdGG6SBl$Sdgf26zQnlW)WaXO{jD`* z-O-g>yl-CL_5vu3q~?j;0p$O&U_emZni2|sg;meKSL;!b_xP6t_d~$wg8Tk3MM!g8 zT?{@3s`d*#U3?=>bagG&E1eiN^P6Kle37TS`&+Xe}K=)X2{ zusZ+KIPRI-!nDQo9p2^-Rty-${qNl85t8z*Rx^RL>YGcCIW4m%1Y^U1S-G9HWbu8o zDyXi%2uN7t;Fz-b7zv4QL5jN7tqda$svQm|f(fk?C7&NHrI7EeWUp+>%%^wM8o{Rm zPIGAy4y#cRdL*XoAhWGL(!tf9yTplc`58a$mZ*$w?U(4fO4*cM(K6CEkhLKd88AxF zuTQr>fLTocgP zy)Xm^JRDCR-7D8tk9B<@m(#13j%@xU=XWk$*&{egr~b2}EcesCc9-Nob+wOp_tjKg zL1%qlkRh_tUh?=E;`@24IMMNvTh&YrwW}+mS0!>R&4xam;TS ztw&1oc6}#NwFkyqFZqvHqS@CSF52BTJA%5qL>Nxh z1WQXbRQMg3gMEwE&vq>TzQg+R;(oB3j0#tc1}`5!VrjJxqO}%H>D#y03>owae(pkT&NdyfIX~j0o#cYo+H)SwW(|*p4J6 zt>)C7C{gQin2{j~p^E-BEx^%0z>YgSM^qAk*gbqthkuF|Lxiui$Led*J)bN(_X8{p zZ!?vNyoGplKQE(etuwdL3U%na2r*q;DBZ_Fv8ci_k5yJceP88-LOT7_W${l-d(b=L z;6H)pZ?BH#R37+(7k66x&Ye%}b5=@Py_>pAT56(5(d~3ZCQ_bU^lw#H)Z&QH!0VGG zEpMIsdj2U&9)!P%*B!5%G}5K1lw@L3J5B2V2F^=TW~*+Iu7_=*f4MxTVdCqCH^eCk zb$j~Xv`1E{jO;P*F}~7Ca~V0@9zuMPv8H zGN`~mAv=8Zxk$A;GRk`d{%)zgp>S_uHk7CxaVE}xXs#D(@aYZ2dO&@8d)+kl*{=8Q zVO*B##fI;DIqClGsC~+~I`bFppJw`X-a%xz3lsu?I97AU<4f+zIRbU>%lSegQxfu^ z*1CXTP=3TQw)`{$7FT!7nl05Bo2fjf@yWUK_cT&ybFdJ@wiHny662|Tzq&44Z(o?l z)Z^|gj(EeF_C&82(Jr2N!@nv3I(WJL$67X1-}x%@=%>rJR;I?rhWNqj@6SWE9ocf6 z2ig_k0}y8NExZJT=e^0H%_hh^7-x$Yz@BKf zHeq=q&ZrR_j(0*AmKNrhBF@dVB~!UFZ@A=pjIek$56O$O9M-w(KeshGRoB3}rI6|I zEhyly=%wqs0m_Dle6HOt&K}>_G_x0NiCAIfBX+K% z+6RHL4(?Llil0Q?c%}B|weM~P@sYnL7yMJJ#byRn8;IJ|J>;cbDC@S=mm9sUE0)Gh zey2K9J5z~#N87lS=-fj4IFLPa%IwSX=rN_|NW+j-d)?{Sejh>A3O;UT&{D+95KFiE z?8~Do8u!2a?(sE1HL~=j*|5@u6gg)Z!wNlo2siPgxW$*zogju&LspB0kY<{z3EW=C zx#H_xXf9N{2|f^Wf)a`&KQtx&(;l&%(JKSOB`Gb5BR{+OQ>h-ZFYYB+`SOB(faz8G zM@4NTN0tbqka-oH^OXGFY8XI%OA>>F>LLz5IihoA9$W;+Q~yhG<-+z(ozgB1!^ zbuNYq^jq6Z%SFP{VO7T+=UjnOn<<(ZL#-PIc{NMBh3c*YJ%TT7OuQm*{4RUU_dbUu z$pau)d@Ub)CZ+wiqcX-=m+*ACM%ga z{TM=?Oa)rJjdLOx?j}d_#hqE32V~uDtf;FmOQ!lhPUOMc24S~QHbhX(RO+)h6-NoX zM&Z`aF~Ob7gM%z*zGVceIa6JUkhRrFv!L^cSBx(1FO4+7ISIcGCJ5U1Oj9RzUbV2TX3CXM6mwd<*eSHkoeRS``JH+j&!Jej!`9Nn;|aEskR__XPw# zvRbYGvqmz^$1r+AqQyZt>Wy7vr0?%GlT==UJj}Y{Y2l6)-*j!JaNkIFSx=v{XFkcr z$u|r*f|+cvU(Q7iFZ3_RWq5f;=G-%4F+Eq*d@<5ylDMGp8NCBBc_1@cb#}Bb{tIx0 z-8_%q@1|FlCe$0@KsDc&hu3&NIp~iBUhfV%msFBnaa5H-DyCe#NNom-G zU;DB9Xa{1h@v=l;-v_8@r%oCUi;~kCqOqH%y)SPVnRBbDPHfVA7xz3kAZasdj72w) z)fT*_{)bdAQI>=fsO>HNxv(loH&+p}Hiz5jTKYW8YI+qjt{C1KtLF^0)3_C5@}BQs z3d69`snA5!t4Qh(id74uOO9G>GP&JBgdgypW}pjtAP`GE@L^|mHsJ`0qE>RS(U$xf<}xC zdyl3KHtxFh2e(@!#GQd(-|)Ve5g58}5I8&WQ144)hc`hH2fhmblgl8M{f0Ao{j2nr zsy3PBIC+A)WjH$g(M{V#Dl@DUGh>DM<+fcEwfn7~z0@%{=A)Wk=1SmseDvZ6bKT8P zr4QDEKRsw_ejCeg`++NP79!^Vd@V=-XqAHD^|0kj3WezJKk*s&1$T4=82_2CJZKu2 zXrYhnsH*tf%3$wPY(>;ebO=Q;nrS<=pc#4ShxV71H=Iv~=6{$(d#mMy(;O~7q^F1X z0m57PTVN-Rk1|`)3F++}V4^od#=^X?n%xAndBA_qMu{S5*CBVGUUNUg?Zo%deYkTy#1WZ9T7Iopj3!e;6XC zN{}t)DjkvPj5+RSuQTet{s=_c8#(XCFGMNdC4H}pXVl}t@HI#&o@;--4pN;Rvw4rG ztI)n=(t8an47|57a$@<1U}mLbCHim|TUwSLbvOrocUIvy|Dba^*NLb=$|Q4)U`A(A zh5c%7t_s{Hy061OCY*dS;G8Ify(gu?sJ;<-<5A!qeg8A_t1rf-dTzdqTl!RoH5%cP zR%mDmv{Z%I#mzeH}os|dkP_=j!Lo=RUTVf^4}Fc9Q!CRUT1k{Mdo-Qz%}gMi$;-G z2L(0FCuVw++0|L0YEOgOL|%SSc?B_Q%gH5u$0~NS-c|&BRcipbYVTT5A>m!CU&rlI zx!;dsU1lgJ!<0@d(u(ZkV$`17a>{O$S%&uK9ghW9JzDcA9SbLOsjK0WzQNSO*3HYC z0=Xmxe#MudS1D!-DV)7O>g zoF0#p#3-}{mE+A{<{Zj3oERH4Yc0Ii(HU;EYE6LfYI2)2j5ageIrs^s?^z8E07nra z$g$8nxMCL`Q#Vuw63lk(z^jsCb+ym?VQwe44I(NMbKZ4633=1!$+&xn0*MaAf!c#E z!9T#v-_@-$lMi@+>-`w-{0uYJd!zLp()5mV-~)k^^mv%3^FUap+n2#RG{2OAM~awy zp{|0N>tTT5{`ose_`_}A8+*)Q3;s6Zo%f|XFE^Vj7M=+<;FGQ;PqiHVsEzWkR9`PO zWZ5(oGt)F&R`u%3$TQ#hq!+39{5D-6cmhx%$kasOod4OjCt%><+BFP$`Ffy&cA}^v z^=~k=-6jw{(JcGiV*BMrVT+VmB6JU_-F0-GXpRrO_ZhPUmFzpoycab+H%L=ivN0>NGM^SM266})XRG~>^*Qx0EkhECbHwkBxV zZ*)?_=1#^=QRXwb!?@hf7k73i2A*OSetg?$kl~x$g8tO9VtuOgf!-q{1*fDTH?AZ^ zrRpPpmS&bSlRYB-p7$Af81n?q3LVv#*|2G80r=eoydsB35UKJMxziv8=cKz)a7%6a z5&zov6{UZ4hGy5|oYUctUVK#alOO4FcBjdtT2k`^SEKT2^(S_N{voKs7$?=mp@5=l zg;fn3?tXatim#T4LuxIs$K5tLThFCI*tXf~%&4j%--x-&<5AvV|9i5cYiq;-H$`x# zt%rrBYJ`=pG{MP`HkvNPNMNmV- zIPS56Q*R<}NrSdATMnZ0B^9)3f*Wjqhy1n!&w-)nUB%}a1>YP|d~p5%ODUu3xaoDz zDA{9o<*oQFi`>+N5K=$a#qV9* z$u8h;cpZye)R&Jo@^4jZTdg9=IBP-_BU1-+WM9o=+5x`Qo-qMH;TgnGgixja!2FBcaDD> zleoh(RxqzNh$e3}JrfJpM0Y%cM03S65iNr}Ed-P0p)XKtZn!C<2Ax_Ttby4>Rj(g$ zt980AI#U_%sF-4`=Za8}KKMpn1HF7M_3gs;QAenMLXqvZkim}uZN{pFU3#QppvpUT zoqn%bW~92~n}rzei=W=@Y|X><_C~tD3vN z(88!+{cS?fK}!bqzqD<|HH*Dl8y116N)u}Rxu&Zg{hDv-yKB)mJ;ZqJo-%24)$FQ? zZdW(06m7h73^H^7O@d)O9Z&F7Jlcm!0A*Y-38_H7!;!2k#}oTnoNe5 zer7CrSz4G}@sFWq0-b3V-Hk$R+0NvNOA&ECyn&soPG z-|OoQ4(Ld|ZFA)^N4Xr_393)s@4{*vbJKUj<-%59HG42CoMVRVCUjPPUi@Lvy_65q z;^iBd?Jl)cS^>>!^1Ls6H>QGx91wtb_-Zd9Hv}#>A+Hx?HM*+;ZqdnC=pBiTQ4iWs zw;o*}#H~Dm8le>E5-B>-gzl<8p2c$_uXd;WjKTanD}A-@hry<1tC6RMw;aJ4TM-gQ zV}{j{n>mhjtV-x>k@6>}Uv~}X2Y#h&ZI=B@L1b}QQ&ksAeM;_{K9UQ55Kqv$7a{zd zgr#n7;;pC)BCSbA0LSoLq^RK?nCi5^j9lP&+UBFj*8=kMVZV2wZ{Y_)<&HgbG1qzI zom2|(>V3k(@8e?c`E`y_*2%BmZH~gLB)^qWR`V1dzDvU2%9*L_|Rqc7^aE+7WF3l2lr6ld;)Zvwmyn1z=<9Og!$42IY(P5@? zr12pEuKOVowmPY>$!E)~a@>a3N_ybzh^|Nf-Gm}n1nV*H6M;&;_9=^}&f@$3Sf^+y zQMc*6-2%#K^jL08hGySMk@s6QtYjE4@?~l;B7CQ~fMp%rO zx!<8}a{5hW)!7rtNH!xK0!_tA-V2$Q2a7MlVNqnKs#9s*C)L%B|A5;pqrja9=96>L ztWO5iyeuREcOURC1tI;3j#y4(OJ2=-C^~U1zmfj#LWs?En>UxQr`{X1y%{eo3Ap<} zeE#Gt_rJ`Ld~0L4K|MZ_QSU>S$!1M+6rbVwI&}I)V2w?CXI)2qOJzexO}0c?`4>Ir z%1UT9yBl3-Kv;#X%peweqtGh5+(cQZM%@~}Lx8|oNjY^RvOT#>^8RHNXHQP@KP_C( zP82&h5nMdiF>q-3%2heA@6ylm53*dft6Sq6AaF}>4 z6t?hG#nNwRTTqnv_+~{poE2t|_rlh6rI6L|rbV%Oy6I8s8^Urj<+5B=4I+C95dU~& z)@!zFToyP)cu|Z4>w+4EfhF|YpEX#UGqOp{Nxq!dO*ZPI<+J>dsBv+c1Mf%YUaZs^ zlap>)Lq%D3vrQ@e(@6@2%s)%vugNoS^|0Okb1^@%TkX)xu}~UhG{#`1XQF1{72sY^ zI&rv^?f&~>P-+k%!uP&yTl$!qPW#zrsPRhn@U5a?;8~#HrZixXWfEwqalk*t=x^y? z;f4ocK)t*i-=;VJO4!!AiYNFzFLY+*tjf4lE&NB!)!mkR{)A&Ckf!7o*2h=tJi5a! zKAMMaa&z`-O7lTk)$&7gX_@})(f+*#mOpr^wb@AWUB}Dpu@J#e{&L+kRmux+>&4>= z&jxywqYVqS6HXm*bD)vN;QE`Xg_n-FS4Y>Ja=n z>a_~$3bUp2(PC|-5z{4o7hIt%BstiNmyehR#J>El*6Opo zVb8brsqKdR6trZ(N&!3lM{z}d_UMcd4egcIMfivh58R2lrYWkxHur*RZ;Qyd*c||h zCd#4?WLCS_oKdpU3OwTGUgBl->n~=;?n}{Q-v-R)03TR0RW;yxQ^H1~48iCIiPwL(KEXzE`IceSn5&@bveW^BA+Pxe%CzqF zq=c#h1I;*Wq%PWh3FLbw72mvAzD@2Rb8)#WNZ5E^NH_|;;=<0OjWLgBw*ksb^{`bbRO?bk5_k@;A)pM@p( zNFGPIVIMKv3&|Vrl9W~k@Y2MRA(0o?SRR>1s_q!^BNe~2q^;4-3r)1?p^mysIzBhg zBR{&qL@oFg~q*Yzg`S4kvK} zdRjHfLM~@R{pRjPoy8h~yZ|$-OG_?(A*=@%fe-pcgkar*9q#oZ4R0;&l;SXsV~Nwo%2XVws=RBBqctn4|1CX_8p7`EU&p$X+B=3}W5>_CKKROKO}YL>8SI_RYmLZK;H59zG&rxbrx3KIg7) zCkA_A!RcFsKF}Lj9gUMH4-Ak4WlpprFu%#x6UO4pcEK2kg630%}0nbkU ze*m^3ZBQzIi|rB39rAnidlrbd@TGw1rE-K9DpB*FQM1SKo1&ZW_-Y8G90;LbXA}{ z<8gy{CuTQ+elsZLEJ@y(U|i9)f#q#C#%o0V{+~ba!T%2%+>zoF{WIqepcGeiYG(vD zet2K{;`La$6DM;nfNp&YcB-Nja6N*wzl1b}wK447gT{)6FVKnHOs*V_%{nVHvKIuu zNEiF#dCl0Anr%x!sXW8ka`@A|cp3t0q4(1`*X7i*CuHuC(xC4IYRjb&`o2|(Rd3b> ze&H5ELHi)*Fy#rcYZiTH&2zLY8Of$?j@v=qwvhEWU^24z)6o zZ;qj}-Fk3eYccWRtw;OW5Z$z0DN)u?+U6^XXq6X7Kq?)QG*QU$^4Dtm`iWb-HC`KY z-rWo&iD&y$GM?{vS8`@Q6VLKzV|y8%0`vf+TED3$OJW+jfq1)nRI4>Q*4|s6mGZ+Z zn~Yt>(Opgf6+Z>`nOeRr?}iO|t^OA5EO3{rfZ6Da>>*DB{#Xe#E_hr>F5 zdsZVOFR~t(j6e|wRTz~gq+BxpHY0lh%pgtV ze>~M5#o6HHU z`ch#}!=HsImF3sAHbq)@zEZq?-y`(gwhtDBow9Jut(ELG|8?Z%TFy5k=_b%r=SZPB z_M1SjwPOiPUnVCA5#+37fa$k5%FC zCc4yJz?-ZUwrFlq6e!wzHG-xLg*b2y`6WY|R8dE1*Eon;wQK&AD6sF?4q*39>0j>t z{n@`zMcb*bqm$=(R;01OO8ai{gm&S*!(12WCmliHmv_T!Y~I#1cc!5yh)q71QfsP+ zhDmeE=Qjx@SxG!;n-8dV)Lv5j?DkG2!0&!*E^26~nYqPI1S{eq&}3`XZ%>c&mt)=V4Q9Kk1o6$64mDDn}0iW%mAsLF3DEQ3VeJoh)GrG*O>fl*jm*6PYVEq zxqE_(*>dsYQX$~R)%prAB>>;6`ZGCh0O;piE0gU4roI!$??~^|7GW+OxDm?+MLeFK z1r5};JfCe2$Ax1{RXWCj@%_+5OZl!Fx@*t;near}b__GaiDX}mD0~XRXlmM8anMrL zczzKJZUxIwJ^$<#69C@9Qv@X(ED67v<`+}k zhFFzB{Y^D*8baJBPqgU7@L`myW~1Ly<0@oTs)PUDH;^`W6{~*o%{JsOxG;1k#>Ly< zPTKjVEltT31LPY7W3bs6j|BI1)abY#vRafzPb0=xt@nt6;E?RaU0l%Yrsu1_c%e0L zq)+Y@m~B-PCb@5JrcUkk4R&)Xbx&OdL9hWbe5GPKH!_zA&IV&7RUQzHQGq65uI@e9 z#g!Ei)t5e&8wCdBr#>49H8=&lJ_G; z+U5xJ9Lg*0eJ)!-$T#a3)GJ}7!&2vznZB^&ZJ|FLv`5iM%abf>OIXZy?jm|Q;6PF8 z!oh-c6-7%RZmJ{tXBSz(Za7r=QXoFT>2;!RBIDYrT1Ie>AXUm6xvEvh}V9KMI3-o zqV|#AErAhY9J4kJyvn>sAJWhBaz%zL0$U_ArF0b%j$~cmF-b^MF)8t2T9Yfql;11WGl*8f+;8FlyEL(mErSSy zK|8UQC83e?>!L_etut4;s(0$6hkew%(U9ugK19Up)$49>-hE40$6TG)6#;$0bl0xg z^L#(m8blj}mHZb(iv+e+{O4U6uMRvM?QGwtkG?4gfsPT{L<@mCJ$t;pP~fh}hiBWz zix5Sx+AMdHh+|%|jZJLMMa9&eDpvJ8(&u{_hLIp9``7%U?(_%Zaj$A9Nwlz@qMrJp zVS|RH0@cJY>yX&Zc0IZdq!vW-_aZH4Ura;X>-7fy^3Oi60oxFGl9Zn}H1Kz|5(cKk z{b){Km2Qt#|3}SWo3!_*!;#&swju^DjlCZ&J$WQ{mVPhz8|+!N=;0`M3A{D;OZc6v zVYT$nB!~HqI>CqK4VVUGd|%Vgj2;W;2dLz{3pb9#yYxhmf($!ZeygKuB^ILwGcR<` z5zKi57hJSh5|5EpiEvZh=v3pB9Ne>VkR&j9EIS@I)_PQ-SMMAVZ6$jVtcK{{tSdN` z?8IcCN(kh8`F*Q$ z#OIW>w%NvIM(T|VSiPd&MQV^pL_~x?7vU~w2%(L8)KwAfg3OqwtqtFx?WzzGgY07; z^0!TS-&T5hVc^VoY3cw_nXf|58tMsYTnr~sxIM?m>3W){wm2NCRM*-f&DZvn1@GjB zx12%6(ifXeh%~%k)I@a-dcHFf+ut9d4Rn=@SLstZPRA$`0J@X zCqI|VLK`hS=(XrxYefz5&%3XNm1I7=z?#DMA5d@T*2_$-CM;blmsIoz?Tmze?yLi? z7fWaI7ZCKl8uENgEoT3C*)hOWVP@h_izUjqi@$m>=!dSlPo79vDZ1;eoEy9Y*GnTigXwZhGl*vA&UQ@LH*YDOQZEA);64u*r?@ z^g+h;iCU10txed!6yN3d-g!6us*Sl{3h!9O-#cAh$bEtTT~jr_h3RaYgQHtPcZsi9 zKOU_xPq~*@g(DwS0bIvL-3w* zkcu^uY2ve3qEe>0c^dgHUPi@_Z)q3z{#Af~Ne00k_bbs=2<=wp;ADmp7CYEVFwf4+ z@ACk}o1m9L>CA|T@e`(wTxMCCo@Vd(a?H6r;3bJKGt zS&r+x2l}#VX9@>G3o=aC(~x7&XF59D?(CW4No&K-j%L)E&iF${lijN@pn~)Y=+2oe z=R=y!EP0Uep{gxL(HuWraBm}ax*}?$Bk;|7a?A_yzUJ&WW8Vn~J0vw@7Y1@gmFe|W zZ(mNiTl@X6SRQ*yYMU*}n;pQ}Q%0U`XRB<`u5TPa^WVrZ z7-4q%pl;Pta_WqW#5k`)MgFDeYiFx%o{}%Q9}(dKajq66UQo}zSGG0>mk{Pcxj8Og zVl^&ZwNX|T#UsoKnj7Z*rZu&$FZ(=f_>c=6%>Bg84*hP8DcfzI4A52YdHK}^s;4)Mu4c=p#(y!ZI{%fQ0Fs}wG-nMg#G+{OL(2R_%AMYYe9 z30^x^Ohx_m&0p&o8qyNfDFdRmzpKoo6_wG%YHq&UV(HuE3+C_rVB$PkLgyr8D3Jov z069p~@8VW#Xvrntx|?H%biLH3n-%Oi{n>dM4_?5Be0g}V-U~;Oh{~Z|8Qm(YLsfSJ z{4!~Q7|nX{TK8P_{ObHEF4^M;p24lvJnzl7RD)dS0Y=xAm=9~GTP=1?^DvtP}wz(e9TfREq+LHgluABAiH8l#eizFOF zJ@#pN6IznjLau&=sp(@0spuJNj*QeJcb8dBCo{&{zZgi2N5P7id6PX`(#r3X8p`b8 z$WCIFm0qdr;OD`$Q`@ywd;cYyWrZf2}yZ`fLP{BhR19^3Ja>U)(vV znz<~~!#TjO{7Yf_WB9+uY?On{o?p`4?sU5a>BS%?xh?DE5yWkM(c1Vk9!2kbj|G#k z!iwF5orlk@T>liVzwpS|u0w?7GM#!kvzC3=bH>d-c`3_q!UYr_Iqym}nLMj)D_{*D zweiYQ;Hl0x%hTWYCG(Lo$V%_kd3pGPn61oRPq^=XnB))GKf;4U%&nenB)(q|(yU7k zyOn&#e8QDif3w1+%u6*h;)7{{i0VB9H}E@`r}s@leLCpZAb1^W-n1_il)sdJ4FO8O z>NuiiFsFoIUONs7{veZRZooczpz5b=q3PwP1Ol)yCma)7+}=4{>g`w4Q1gw}5^>U5$PUepyQ)k{A0!MM-qlS9DZ5t$#A>A4r7l zMSGR;g1gtHfMguouH0+twd#iN?D76P+Vc_jTk~f=vxG-`%AV%k*os~Lt^#rAIXgAg ztFwbP6)^R@It5vgIXDFIn#d;mc$ZI8*NqpG%v7rBL?=esj^@dMXvB(0Ky_9@&_Xfi z)$5N{4ntSp}@-j zL)cq~HTk~r-&i0e(j`mNrnMba^DG4ImGioU!kE<7|@T150E9& z>d-)0v0A5UD-Wq3_VUrI1>nL8$16M6H`$j^E{;;3I&R!iLyR~Mcl^xuS5>@}xmF7Z z`wOb-{pd>*ra+AobqaJs|0)pOYf1?ziPOyqX);;>{r2dbgHm6M;M^Ie z-F(&0bfk3ssy!d`E+k-S!K;cNSI(|xY+fV}FaqjGUyjw(O7Eh^Q-yNHT9p@LLBK2u z+b^WuzWcI-Rs}UtdN-C?s3YX3gl?J*!R0sBn{@m~ouxD@BS9QBQ|0jK+kYffCra0G zjWWN~7ic61%tDDta&UCsUj(4!U_Axz=S9s>|5{j76Mn3p^wTcMyHCI$+R24Q41i+t z=!u+A8(br1bxkCq<%S1l20|5(yh028_q(PJgY2SuRzUh!K*v&W8!I6CE6Z%26Tk+$ zkJ?;VUk$sx3|EJeG|FpPbvvUn{O=bbLm}jwdgIPMmh3!2HholTqPZ^cuA|KztWAkk z%*M5nbAFRYjn-T(Gw}m ziiL}>xp6<8cxYoODcso$J#?pid%gIo+ zvDl8Af@^tlo;6zNJJ{yAayhOq^Wx|s2nk@$4)W;Ai-}lMEo48cQuIvC zv~x+*RI^zfnOXOE-?l${$ht*W;ril-!5)8EkaOTvPR{56C=o&q6NReb(eB9d7hKtUew7k5Gyfz=D zfI2is&__ttb>ohPq5CHf?rablhZDoA=wU$8_P8)(N}76v&gI+9FPIjBGx|Z&N=s~> z_H^&38jOHJNMi{|2(6K)u>R2-^1ZDJe4e`cvBfukCqc*~zWtcT>Nvmu{$2PQw|(2Y zwbhGCgL$GVI+v@UI@ifH6F)wNrv`#4JU%w1$3k_nS=}F&9Vh=%zB!SJ9^~jkU2)D` zAQE7#Q2X?bJSGVcV}QCX8)tDj%gQ|2)t-8R00nR9w#0cui6*50!`9LB#Y=PiB2PZm zNP`QYZ;Z#*W_RGaW7ambgZ7t5A| zl7(Kr5LelpydxRvK6u1b!*wup1w()LGe^};a-v@Jph@0+D1@-P?`L4O&subV}?`LLH57<^G_ z5A$b1Fh2)6TB$M0BH_DXe>1f^zt{i>UQUVCSxZX73TM<8L`NP@`1W|>9jHJ(-y6g) z=eTl(e+Du4Ri`#!D$RfK!hdke=;lRPK^)I-(N)u|zV?==XYocbR_`x3B4_PIB%a>v zRpXSe#{)=*Mgfy<83@OMC_>>DL0WkdIa+dzO0X17k_6PO2dwtQ;UEZ#2n{M--+W66 zQp_ay%WLi?gL(TMh_g%qa6Ek{>bw~RV%~w%UM#NepNXY;$P~4D0gKe7}5MdrAa}wZ?U@O zfQ>KIC)U=EL)pDc%$6<9b*QKGUez6|a>t=sdVO`<{{T?){C2zN57tl^w zf27MTJ@otjG=$_k>Do5SR`N%Rx8g7FEvP+62q^kr;DxjxZMNs$yJ5M>gOd%B&0oq( z>K%xe^1psFmNj6Q0SyFH2y2&~faKhx{}*(gX}-9;D9IsJqVnKSk5!%Oo+9bT=SUu? zDJ~V8*hSV2XMigEqb-cyN87ig1SUv42~}zHd*09MOd=z(RpWX?GeLaeBi;W!{cRFy zdk;$R##4;7IqKZ$bwjsN?=jh*JMNn?OL__)Y^klfuZ6Qn4gq5mR8Sc$x%ZtA^6RHd z02gbul&anA9pBHSGRjaNyhZWpmKd65bW+ip|fQw}V-B#B2QCtId2S;a;Vw1x; z>Xpzt$cX>3UYlkR314wo#gr2E3AA(OyL5||uTq$3nL#6MIU+GSOh2wY_Y|B+S>+7x zk?EYp#$1l(Pt=J4LL-{3u(-TK1)XEC?ICxANzSoRZfdl5wOwOy`tb~3fmiSM1!{Pi zaTNTI)CL@6#eoH^v+oJ1ytmGWa1LN)50;$`TR)d+#KDWU+|_QbtDFD-fz8@eW1vB$ zr*IS)8@hhutn8$I@?zLRu7WQ$lLxT;E@O~qEF#>&RYo8C21^fx(thP?MLPELR`@@f zi~18`Z>bt&>nSVi%F*qi{WmpU&2`8d1Uuv2+lV#^vZ=5!tMXT9C4}wQitHoeCqusX zy9j5og@ZeY`VGCPOgs*Ad#pCjiJsVzwh*|Tz`%YOmLX^ z$jp4#l)5L&adqe3I}&W>g{a@T(8FC=`CcAFoAv*K=Vv2;h#(#8cba@-r++K@M&#Ze z{w{al{5YQXzKHY;Grt#ptqL2+1AY%t4%k&`hS4C#-Md07hnr8{9Q>OcT0a3R(R%oJoyW=%fwd@7!T99`Bc;?SV_Ss$27ZBaCcM%H1-aJVU)V>qO7TW>=TRpl>;Z!YGNaJ`^ zPWfp}Jb_Rih{zbUF8nr?SiIrz+TW%^P?BO`PX3N3r|g7qEre!eZt+pl3b^S-=DE0r z`}4xvzP<0x1Un&2a2rSrsQT!W0t3_#8#>PuX;pkVR-bdHOUh65wpC92>W8B*E|fYr z>@^Q;#FAuozs=5g(Htw;P{~AC&(uASV0kS!dB-h!T9?^f87A?X(y|a@SK}V&{xz%W zBz^xA)}aGV0h6-8ZLc#SK1k5qH(sKwP-^Gua^Ffd-*(@+MKbGabNv=7jFY)m3dnjJ zF%I=y%i~y57djg3zJ^e&v2OLM*6XZBfJ6+INyI$$R-*@qKy|;wKCUkAn*2@69i9# zF5V{1o|~KlnZ5r5=!@gY{AtNqTGfGl(UDN(JGvc%D|>B1n$;!^>O6wTb{-7mX!_ef zUkSg4%MRHzS9rsoSDl>pKXgP+wkj^P)Q0c~)9jXKHUESCT!9)AB9JfecQKG~q^JuF zg6Hz9>p$mp`6j&9Q2$wJFDiYTI?;2Y<)W*tmgX-!bd^#B_5jw~L@D1>%T;i3+$-nV zW6REIpA28=+x_ka@_~bUKj5BfnIebrQgXOSFQCnL&WEeOOs@UI7OdW{omcr$qRgNx z(90dFztMQ9y3&7S4&T?p(zL@#VNY>?dRA$D0ZiZ?rF?BR((Lz*%3DR4=5Ovdkr9Dz z4hMQ>g*GLqoD5)~PFGNaCF>U9z;!A$n4AvVn4}#K*n##Qf5E^!z8Svi-%@%e!{Ks- z(GPS~p}4xDBn^}}-dL@%to6W_0ADwV5$ACY zlh;!6cG4?-7Bk6CCw&2J)LptjB>&w!D}7~9=D1KTTCBA@f9?=o3!W3{Knm3ozWb17 ziqKj9XbIC&-nOxQ zf4xR=)c4!K#$vi+QpqX8v~I+j-G=q@2JhI+lH|r;BfnXRt4M(t45Q!SR+OG@*J>`J zgCa*D!UkGyg3CRlA= z_5BT(n;q|$;2AXIEW73pSZs$-!lVIDjSH5>fK5Bs&Hb^71xE_><9m+gstM$eDS(_6 z8ekf5b%H+s0Z15fUhC!{y3;O;>s=CCk6%@tjYhXN7#ZtB76W&+CFM#KzmHH;3CZbzc3wNA^EQ;%FpFP11cBKWc zR|npn)oX7@OZw<5F3SBzr1$nT*W=nj-H9NlGPJb&M!-?|kX6e5(A|XRD*ut>+JH=P zP)-`!cbSE5?1q*qUu}FA6-qGoL~yMCnXiq-Nd1p^>6$DD_NTJh zxi|fO2^+t@ff%>D7h$MSLWm-%#!B@FX>4ys$WyEsa*acW0ClNCvB-kEb@Mhr9uuST zQQ3h!`fN1B(+cKtmFgH;E4Qfgx>4rIGefb>Dz6p7kUuqV*;@=729!&^9Y={wxnOMk zY26Ep+MKC-eR0>hFK>p1Z6SV(;MK41?-4~?aj716w(83*2e(JvlXL)%E;jzW(tC6T zG2%_ZQXJ#Uw?Cd)sJD~94HT}#N#xU6qTo)hRQ;rN6J|F2P;%j4rDV!2>hMI&<+sfc z!G9LaXq|l%?{ycQ_%tKtX8}J+%=Rf6zV{09kRSW)k2bg(QNIxiXjjS0|Bpm;kmgC% zF}N4ZxB`8LP5XoB*z_T2qn^Y_t`&UvrF1)J4OWXDGr4p&Xn*V}U!# zOIk^>KG*w`Hm0^_1{h1iI9FZi6q)`w+P&M^qBs?;NuSPY>^C?O1Q`<-T&;1{@p8JbMSf43IS9KLLjy)6kI>4>8~CD*Si0YkVx(3-hJ@ zaao3ERkBjjr59pk5z23v_#x_s?tG2Xzw+E*Lo>6PiTnNNfQd)dLhlD3?R(FQ-d zob6>MU0K&_oJj-oxMXFB74Ldl@)*gYOM^1_R+wMgElGi~{-r;ba%;~{bbfe#V#`1B z2vVo2dgQwiDxhaq-~+mYsL8ua9OGodMWXw;Ed(_jk|F$>3{MLcdp%Pu{0}&=mZQC^ zv=Z?S>UAy$OlFHt)){ZhTHb!Y?dI_V@u|zo`KeN=&+pb`_w5z7-X6f2MTxe3p*$Pq zj-ay;n=?~nf9**g{ow|H(FE&4ZsH9TSX;0O`N3;hbuY~Nm{_u8Kf6rImc{b@i2l5g z){WY!ZQQozSFq=bQF-~X{vD)1FS4GQASCTe5LO0T&@tZPq=W26e+toy*yUte3|L?DE`N0^l=7cZ!l zXFf9H@l#dy1u)+L_o-Fn)wIXF*?H2KoD6E&zk?{&l5566?Y2JY&6;$+uV4*rJAl8y z=WO~K@C(H_e^V6hw`g{t1B^VIKRcodv&1n!5}|ekD|h z6sDYip8j4J|A#5*X7jzs59<;qzE;3Ifjm&0jpia5rutFkr6T>wU&h!#k7|At$^8%d znHN8)k{1V!!S#*(cV$<$>DNFDnOYR&crxr_ zXIPg4ebY@%Z#T99p&sw5$;}lRgzrq7bKYl5#_{}g6m!HQ<)$buO^znB&zuPi?m$dt z$+a)b;IjSK9dD%l=!j6TMu431FI=eLSKk@l;0WVc=N~D_BnKwBde0-b7h?#*Ui@UZ54EH+_-h(~*Sj zKC$XDwd4oST2C zJp6oskXH+5T3B*~&^XLWB)yQRox+r}H0*mVHeQsjuoId%2YVKVz`z7mtVhZ3cSSO( z@v=Hi zFC<++OPaWl_#LleVL#d~?zG^0*jIaZ1};4ktR@-%%dqLu#~d9$ogawl{d&3Pb#N5) z$$A^pQothWprXq(WCC7jwuDHd?g_MIbr)>+Yf|I}vX8&-3!W|^KTqH7Fe@wxtBcxg zb7(jq>lLD7{=yog4PSH3HZsFDKA*>%KKgU7{(~BH#%894d!g5OG07O)M&}{v#wISf z9>H0A8rkl#Ao8jj69=IJ9K*vrmla+otGj$`ykTH}mLM z`-GqTK55DkSs&==oJ4N<6?6ajnDlEox3Rp$t>{?$_?FFs*|7oYNy!xTxm_3;)EWzE zPmE?-sLUxDWQz1^m!LGfM5Tc*WI>(~e_Z}~e~LEd%?dA0>$}s<;NYAH)^@7C-n1K% zvzs!x)J>I+gY$=@&oCkfpU@>OkI)3O?k|c8t%0pRdyYT4YuuN~fsSPZVt(+v6uaF) zeg>uqIGh08H{KJ=n%j)g%5z9X0-fyjV$SJ7om(>9U6G{Yr+(qr&;aXR{U$dXO(|OQ z#;y;Xc^6|_zll7sDM^@QEnDx$!=m3|{gU-B%&~lie%zM@2utb8Y#tM^d)6F-!6DS4 zM9a6tLb62k?c8<#_e#~bE&7+{ahZe{;ZiKd4EG$~HP4aWQ)HF6Aj8vb3A(*TGbf5H zOobE;EYNOqHYAM>fCcau(Y%hv8(0{$)u(I7iMAj3?w*EBA8*8Jb8uq%^zywiBzM3Guv;>pRdA^W*kLTc zAt6~Tw>=D4?+}8pkc?Hv?b>v-e-u;KuV~>Mm6eQlqk9mU?$lz#uMR?uIjuAfo%>YJ zz72eJI{d-uffY~t==!vA*sqQHLMq;M{Fpw-mMC#aG%2(>cU=MRC(CD@S0~*IL$Uu2 zP%lUOc$kN0;0h>{hS_@vUZ}0*=>@1&c_+fK)M*=DXEOvpoB`9gYl@ zqoTtwh-G7a?wWC1=($qV;?JXzUBdbeIUZTcJ5ePAs7uhWNgdbozCQwcx0FXD%BP#; z6S=V}wU{3;zD0NkS+S}}#6g;L;TJkU#dY+1`2eD{lScs~=g^)+^L8AuDWhDzvNnVl zy(*UtO)&UW{1Nf#*PfzI+UPP&RRwwyCk&!CECf3Zvug$Z*@P^Zp^YMl4+BPK-(XT= z2SZrj=s|9DcV%poHJD;N_zHsc?b~>Vp0J{~`F69wR;VQ*b4eqOR7kWCENF4_cVC0_ zqT$CitmW(ClCxN~C>z%UQ@4E{S!P>6p0Lo`Qfpc*=Ngj3dIhL1C^!y@_XE6CFTX8( zgs<^by3VoKv<5YBJPEwNWPBgpAS$^jU_sTuY#lro?fh*r{c3)6om#-hrati-U(~XEf zJQ5jZR`oN#=H7f2waD5NZ1fGP5!PLWGc!v3`$v^5T4D6jZzq+v+WB6#K}P+0#m>>w zrWS0&vY@Zb;JVRnb_f|R47hdlSZ+O1b+cn7jYo2=1f_3Fz8G zgYm-H(N6IE2qjHa5cEo!SO)hDypz-MHIv;*Qo!T&0MmO2S#ID~o6)e76{gWAU;Afr zik66=cry9Q_B`pT3+y@eK3E6_ZkC;7P}D1zmUXce*U|X|8_N+-n%%P?i&FA7?PrsG z6L0_-BXaC`w-5Oi1zvT2Y9B@EyVKS)ni9XJ_4WvjCIVFZ;G+eu_AAc3b@<0vLh-qb ziLaZ~0NwwJm5#o)V8T9h2?&CO+`t0?#NO8sowZSt08La;ety9D>{}p0%~3L{?mvYbU7$_+b45;Kj^C!;~nYNdaze{&2^5f>SWDgKh>;c9adE^*I%vl1~^AT z-Ea}|ns4Fmv5jC~?N8A}%VtCJ-=w)Gpi-yKkB|}F_dVUX`rYZUDr1)cLxXqkx>W!j0$Xs}vWeGV84$^S!dY#F@5?7R_bxgX+AsKLW4u z@&b(33YIOiC$AL3>GSRCPAfFMisMczbG4|*)W|QDp}-{R4&&q*huOIXHaDYaVbJ#j z&t#DxUD~5Z&GAbpRb`UQvuYE8z;JT)ouRg8B^Yssa}L0Na~J2b#`{qYio7#98e1zQ zCK%hiH>fK#mV>-}$7ch=lQB-i=E2p|M+Y`*6;d4w4gk{rLF0sb_|Rh|F_X4|KBc6h z$?=4V7e+JI4WarczJ~c*y6{iiDmm!Uewu~rb74Y0j1td|Iq3O=<-9# z^m#vNl5h1On!RuLU1){@yZ^nOHdnCiXarFf=Z_KTG=+D887y$c=2Jp$hZ|D7U>o(v z7HLUomr+rkDbt@2Md&w!l(7Tof89JQtFxZ(CJYrKpRK6C95Wk*yiHQnQ*|FYIecMK zvaG1jHbPHfjk3Aw4IHxS~IVD_-8=OD7E=44?#D!XXK_&f3NvtBdIUBM%* z&3W`ULy4UaN~Lr&bm6M*Dx2Xf7-aHFo1fc@bOHb9Fvw0S1tg>|66%+rMa~+h(&<|v z$d`AZD+!PCL3oHjT7>Cp5{GmacHV>7D(A(XNY1n;yf{PT6{`F-*sAJXTpXOv`^MyoZqz;FDEKXySoiWX9RlKdWgeE0Cy3KB&~YjHt| zkmJm{O)YCnp0uQ!WV{Ba4PUps2U!Z9ax!&KcFt~PRnH!S1=h>&xVoGFLZSS9fEKm` zUI>?nT8##iL)9^R=(?Y`k+ukzCzFRFoc^jOf83vFS;0m)@8LXv207g-ZnQVEB37|L zwP}&=6VrbrZ{_uAW{|Bm&uX#yg8I3$ZG$!^Y5=#aO{53KHvv0qbR+EXUU2+J5(e}* zf#M1O0V@(GcLPgpRfj3u;V+OIxK9fjOok&@LtId;aIMG=81K|6C3|68ZC!&;jGYV( zX8<@A+D4E5W%Gyv13O!Q<Kr|{e{p8UNTqZf~~Lh5BY|Mk<@ z-$TqBy$ZFSnqOs=RUgIJj&I-_w#vVmjEDIkRBy2xM90;}HeM-SGXlrA@T<^D4W6Pf%Xj=mQnwa$TXxARpt`0&wjRgZ{BPaVKb|pjYL?P!^?Pc&o=B$Q3Wvx zTT&gq{1`yu^?Hgs?@F|6ysVgvctrC*?{OlYiMXqbq3KwpWtkT){?%uGMk@W71SXrf zA=p6Euf>dl{{^PsIET(WOoB_blfpx$Usp|o&wPyH;lYpdsXKE6WL*w)a6GCJr>9t> zu3$GY9K>wC^kwyuleAq|XxdP`UH4nNn4T&}QmUy<)BM%&|4W_=Xw zRzPs?c)%yuio&)j)%iEU(X<2aDg!okwjn=u)?^7{M+bue^{Uc#JxfNoRdgHxrmKuq z8Qm{WaDL7J(v|a-^8?O4zT1I*1%}lQ4^Cq6OjwWoZ7gLsQ{6)CQBOR*cA}vZ+e)wD z^k(gQhLkYS5ZQx}1;D@TuADwKX_mhwo%lvcXT-vA@LK9!%j9sEQN)bXWAVR4Td{rX z=5;t)rAPmQ6nRPb3bzNYDx?Swybf6qTyO0u=KU(XdaT>> zsLrFJ1%+n(C?OL#!Ydu?AL=m2!PmYf&p(--{RB0x=MHx?JXHRB)|chxJ_tZo+8=S# zvb0F7-+dDs*>wVXdWD~mgi{z<#Ax^}o$#a+$&0No_+0?V1&dPnx>MG`m*NZ3@x;;0 zg*;2(tyrz>6rLX3>VDz7?=mnf`hGJwzAzn}O5yiU=ZW@~Iomd#-kn;32CR&gSRSO` zs?YjERyBX2V>xw(1>xzP$r6C=EXqCoktJ9`xo>;x(l2g0SmzO+{-H$+)(B6pIiwQV z(X{_%!-`IQx(AFjwR>k`LP=vx_oH ziGM|nm#EF&U?sZSLCxfRic@C`%ri9`STLTx+)Tx&oye1BcMIk|kapHHFFCpGD)hEd zDgnNheUFY0$q|tA>JIzxPX8G%{mf^D7r@iGxweYo!B|>9#ZCKN#S{2n2Xy+ggLjSE zqrHHa?j2?8Z08Xz_cs!eMQ#~j)tvivh|gAmMd6Yw z8?JyG@dWB6&=Rc2EF1nqF z0_}iAW`3C?8b^n*#peuE!fr6i-Ixv34>#ojn<7mmRYdwe_ZbMVkmDWb#E9zR{A@ob~7|2U?1r)Lt81P%%jUv21PPEX{5wq+9 zpZ8j{(4IITOiB$rs0+OHqsZ#IYkD401iVX078t8Gi?OI$I zqah#`mS~6wtGRZ890Ui;TjZ{+jv8;KTZNHAp)YdVzWr;TaJBEQa{zeS}zGu3pJsyJ2X`H4Xj=fJKu)&H#eu z_3opBUB5x0v(24Io%&Ga|40lm@Ih5>`jMbdXB9)!Q$7l?hB};bC2`Vp3QT94-oA1x z#0xlc3l??QB`@4g(@Iiii|BoLkKtfAMBS~{!@;WktMkx)Nzp)NTEONv<9H#c1?3Ua;aZr^L;1*d~^;Ku)vknFF3Kdsz~@3(&; zk->c?n@`&I73vkKV5A5S%=>})QwxyRa{!jGeRE@?>t`~qu!XivFq_Ge6ASEQgUomx_SW@!*!a2S1&;gO_{fzSJw|@yYWtx{*$a@eo;SP zYdl}!&X7+#Nj=jx#Woj3Fv-89Cw~Po*2+t-%N4+=0)y_Kd4PA$%t>^|lrsfw!LIdL z=_cX(!ZP*AGt0v+B8kyiAtb`k|JVF=>k~)rj+no5|F1Ot|Kle|n$1MLG(IGM!0;Fz zQL&nO+M7K+`*K{vjKdSs{676K{ii$*@xh*yVk5-)cP_(Pea+)AFuznBSdU}-fe z?J^z%)5?j^T^>7+-R6p`hii0AA-NstI`;16ljw=vg~0{3x~*sWGq1h(fpfuVv>dn` zuZ(MS^Ys$Tq@sWRIjNeu+m`nf5#9n?r@p1v+?YIaG!!FKoWOhQi1*tEmrbvj5_{@K zdL3GqobaQ#8cmad!4HZY0~jZ4z;&lr-(1V9x3&+^ZQ5yE)ZA0^y-zju#DtIVPke9B z)(zjYma*zlzcNyELW8K4tw3LX0RlxbiOqL~VOit*KINts6p`JzEOd8^+TuZS<;6Gu z*kZw-m^NFo_KZ@b35#(eGcEfTPlb+#Ty&TarTik%EtGdQ>Ytg<7qr~$PY4-yr(q3n zTbwL4e>2;AKVbD$ zq)vjg$K#L~X8AS>3=Yn!L0iVWoWxcKnD)t!!aHkpN|hNpAJBi&$d$zGCo>TzVqQh! zjM=VC)}6HT_-3A{di~kuq)86+sEl*VzTbJXm{T4j5vLJBTwzGe%ZN1H`2KIw-}b3F zeUs8NygKGNjbLZVs|huQ^L_nE=qrrP_XxoTyN->7mYI~^@p*PtX8#fcNz>@HK#SY-qLp89&(yEK!A?X0n<9p zBDrx0-{Jw`gZ<}G8%g)K<I>YgZO;pQo>fkRI;_H}a?{{ptU< zgdboX_Cu^EQv4msa}PHlyC_@fwC30NN@suECAe##0}2S>5AfyFr2o4luJ2339AJ%x ziya=4>9a0<&~}>5Vf*6g+PlY31)^;cWJMEa7+JRM#SP5R{$Uq7j6Dd4XFZIp=d*H! zuQGLG??f50+F`}p)3k3nOI}`=8uXB@8#&<8QLG?a)9kxOWKVtz-m#1qdX;Ksu8fOB z#V@WJ*2h2i$hvy7vJ?2beg>>UqqF&gNa~~*_yPmM<#XAoLJHxtoXy%19dX)lY{#@k zN{URaCE9@Is`EJI>L#4x81w)TWC1nGeW-JtR8mNm){KbI)OL;6Zv+i_e4*U%z?BJ0 zFRf$iJu!H6E={z>`t-qK@smmD>}ZP?Rf=Jwm1)3;X?Fy$&L z#PL`@g&lY0V7T$mwbY?p!HkHUbp%CK@{WY8Kli7a21Fqc2ysL|w+x#~HZ#`YXm6aT zRC10_?)Gcs2r1h<$^42elYo6XE0*!936SbWum)Iz7*;wmKYQ*L8@GmNOfQnIKxB}w ziARjRK)1#pWo(zkJ$+!r>$mCpY2PJZr2DPU`<8?ZYoW)+$VWK!0)Emz9)O74E)rB> z5edQ6>^(iUFdIzie@g9PSjbjY+kKWrzlf{vIFH{FI=vs&!%P*Ly-M4{opvm@Q2WQ` z*YZS)v9qV@i|*R7d^cb#>agF)&M;*OcBEES={!MQbnvtySJJvdgl4DHo23-G4^sci;y2_z%lRD<@8gb zhY$)hp}H(3a21TT`!B*H&p8JZpL9Mx`6zxm4E<4pe}xIDYxOKttXL>@dT*9y-}fX4 zAV_FjLOCVlyjh$79bB@HBOK)^j)A-N0Ua2xQ$fDYU3cddKoa11EYT4Vrn3-PoYjXY zsfa3cp|%FSPY2e%%%xT2A3M3*n1OY0s`;dx5vo}x*F|3CAveoYM79x!0DuYy&6xhv z@Fjucf}QRM$iT1@g}xi}UZ=Ax`n6eP&A$%vpX_x={l8OR}Lj>eU>v zRWwbwR0g=#G-Q3t&pgF4MB3_W>x|b_&#ERJa4mLXKFek<;DZmf+K5dEnyxl#F7c3B z6WLTf7v$%icm64OZJqMve^K@T=TOCZ)v3dOAUiW2_7Dg5T3WOa|FJ7MGc7L1<=1pQ zm}7G63JWC;=WIMM;K)neVsy zZ*gX!Y)BolZ{rbS`4%QSdKJ!2ROvlUybA@NgvW_*+am>B=yakvX=4mcgfab7pS=Y4 zcr$hD)(!UGHsK1_rtKYTCC)&C-dc6ILKOetrO~DI=(0pNp&l?=(RZ<>A*IHIS%x_a zXcUht{`WO^sGYduH+-yGO4P^JMarE#YG^B^* z@&q!k2hP{cx)%cMuAf(1lz(H_<6Uag)dSJ*lpc3B+3C0UM_1KmD5^EEyO?Y8o`nh1_rp|-*4Q0Q&SzV>=jlhRV1~FF;yiL{7nt|4I(hYWB;ts-x zLq4C#@jl5>zQ}C4cm?lJcVY;CYf1WsL@sjYQeU&wv~QNbh|nm^DxhSSD zXIEUSoO}czE?;(bd8g2=q5L06B#-S9H-`;svD7u0=9z^xQr0Y+bMN}Th=Z(R1`O}nWrWM|g5@iwy%$@dBPusr1sX@_ z1O_yZB;zd$;52d;x4{h06$1;L$ApkS9IE>K&!al*= z6fv5S?J^zL)<`Y;=XUY&D%0h5Z0F4i5|LerFTU-&3Llz%r@Z|+Z{pjm>EfSW$>@@s zGFvkcB2TNpd;({APEp0KEjEb3qW1Y^!T8zZ>JOz)H^J$Q&J!NAiwjwbsA1dQhWlD^ zOT^Un2QVhO3E&zi?HBfdzN!Y*IcAnC{-y1iNe+c;r*l_JG{G`fg9k zX+-w)A7MngU4BLV#`&UIZ`uvkX2lU1&sm^*w*<_qf5q8Z+6Y0Ju^?Tg(8a&VM=pJf zu<5!FDu8^}z%;hQQZDxpz2ZUTGPAo*$FW0eiIyT~B8tGm+Tn9;@f;5i(7 zm)C37JCgGat5-A2vtbI)cV?taKd;=FIn>`Lr!-Sgc6y*~qP)7ud-5zzxNM%quSusz zvpF&b6v?*7GsLJFs7>vxxQ2+6k`mqdfS17Dv!E1panQ|sQ|mJr^_$kvfVTHQAP3Rz z5dmS}SCGWHyqzKfvDYCv<&g*C>dZG40!NntINCboGwcxr|8nZlI1#k>%L7DPKd*UH zW}Cm!Wn(+r3R!iae=4uR$TL$M3&HafzPoNqra&cUa%`^)*QA{bY1$zPV&+k{II{|2 z;_JKQrn@ECRs!9!R)D-I%k88rMpFz6^E0?yK0A52t(R&)?@%qn!gU`2e6DI zy@z$2-Gg<5M7Y;?6|UnLNMXR1r1 ztGs#0N;Y++H;kcNKd7ExG{y;-EjnDn#&4Xwy4rU0Rt1Ga9EZ`oHk>r`*XJLv-(VJT z_YU8JDESf{$%uE%s_~SB{Ffu z_AjsB?7fI5>wT%-t?>5td#!>;77iV4bw3^B^LG|z61~~^=v7E8L0%Wt5>Bh! z*M5V7FK7E-1k23=3GDIQm5VufDcL8PIE6=@=zk;6t1Orzcb7zB`>{29>(#AWvr@r@ zKPDsWhW(I~4ZvY(27UX4Q|gr}K$!!Sa%jik!1%(5Jkf);TA2hmRe=5TxB4jxsu(QL zdO*aXu^gYD1!}K_=!bbFXa2TPTp7=JvsA+96t zWXDphUEg7{^z{7&Z>(j#Zc0LJkbKaJ@OdxP={EV$N z&S|<(qEQ=6zaU$k@BZ*4VY<};%^~_textOk{^LsR{`+UXT)L8hEJwEg`gveAuu=cv za_EDJc@j@|P6;~>6_=uh=rwHDvC<3X^?U)d3HM&ZcOG3QszO@ z%H}1@tuMG5!mhQMs&g4~rNCZxR5#8#jfQ}}C;TrBFvtP52+@Sq(A*zHkyi-op=GC? zB-I!gkF%8wsz%^9EM%ZWM0B`mYzA*ty2$GdV6L*30jgQ5<9tUPn}p_bY7Cb!fU-M* z$Ziv$ZOf*XWz<2s`HhV zSK&K1V-pUyC(;&DoK{<}rG})b^qD~MN>{Z#g^hJmLxDn&+>z{pMiX_`6IR8gvTS`_ zK#veO_GvF>`<$vQO?jX4;+wNlH_>h18>qed^9OqO-fRgiKe)52rQcA~u-s}RjrdnIo%lsP)$RPIL4knxK(3(u zM6m43K?hgBq?G!S7u)^5B1DzD&o&qJDFdipY_ry?8Esw9c1&e>;?_yO1;Ef2I$dui z%3b%|SHYi8D&@L9CgTuw7CQGvjhVD0{rXKB0=;7C1nNDdd?FeXuuEN+|R9tEUIG zmbT-2a2JbZ3bJl8rPe!!M@MH5!&W-|0)wI6B zuu*4J?mf3%J2y7ohA`i(htUP^@K42P2xky5aXgP2#sf9RY54Ec!Lq5BYuV zYBST9XmIARpMT8(RVL)&wJP`E_hFBhaL2OWtP{F5ms~$@WUwYXf$lVb_zxhz>}7iH z)iLRpSWS3T<`8aI<{XBM3vE=@ALi)$Uj~*=I3u3g%MV=2eS9&yS!<=|VrVXGNChBT zS;30>hg1U8)cuRF8Z&YnFN@Xnmn*xuqjhz+I!vvb#dWy#w2yR?>;%XQhh^bLO2 zAtL9wG`0TBfWrhVP9R4;Rc1~`O$IB|cUPEvQA`cO4x7aq)!lOU9yL8)p(r`iMuHmt zFTUP0sHraMAH@bLAOg}$P?~hZ8&+q!`S%C^iGzrOh=EU3GG1Z+0Er^a_vtHe)f-YyXfV-^&ID;RrUN#s&ZdDjiaZCu$g zv|6@kf~CD43E(tEo0ho8wN*!WzB4K^r?0#@NB49gjfs>lN3ilb>9H5(GOfE2-IcdL z%=$O#>t@EL;1oNWvexeIkr%>p`yyP|O|5(UcOR{9zqN;F>UQU)uTL=iRfZBzkg&@=<7_lAf!G`NaEOeRxjs2*wsL}vxqOG^Hy zdl2#j)jEPtOrg3rIwIvJGjm@rw-3Jd4Sknr3>LB`%6;vgl~dxKx3*oJXS-GJ`fXt2 zIz-$YG=cWZ#$VG86#G^zAa$rO3ElLIZM4yL{F=++tS;}d{WnC@jFh;V-A%NfK5%d2 z*!}bStCzO-Gk;S>8u_>wvNb?6P&j-*m|SNqeB0y0R(EijeQSW?F-4x)K^y&lSsdc& zU#h{-$3=xUR+Z~2B$246fxUpU?S zA06}m_5jU+-!07vBi};fdbfvY`A1`q<|rgU zbv;X}BXX_tC5!(gwmv509u%gWWQ1qV%?8(kVxkgLt!itJwbVy{<;ItTZQ9FVFE1aM z69WO3&B8X;EKEjA*#_fzZ&%2f6!B$?bSP%E(WLd^GV0t^)`sTCNi_saelUo&Ai}X$ zNH&W)Wcg^(@*vz}u%hc75UZIHOd}j8}?JLDvDTCZ2 zcxzmUY}&XOf(gG8UgU4pn|>52YvSEJ=~*te!60NR#u?Yh^N%73wGIs+xRP&s;s-mk zXvbh|dCp2tBA?d8j3{QYapfg2-OP_5I#PI}VzJ!posQnTYAiv5!E^>U;(vyF7+++n zpomQN>*{%xD|B~uq-=6N>jt#FJOSGt?Lm>2K$0rM-YSDfh_DMVx0>F{@e$Hr(%hCl zYPTkJjB5nm-o|7xc5EoG8oRGHnlHIOx2#p$lOffUmHo?c&P`y1@Ay9QZ2S1(P&%EY8W8TR zF*|l{8Q^eJH&e`jnH0ZV4snHksxr90ED&lznK#D*+%!^+)B)W+RNSR%#c6%KR z!w!IGRdIqC4m;SjAm4#xgm+qqk-BrpYu1`x8|T83L(qrISt)}l_L8!dx5ee2y-Z#z z9mm$a9f;?n`;*+aZV9%(nI%1TC(mq0Co5qq<-zo5DS9n!xNsOxg>Cuz;(SX)dV(qS{b{YULfQ!i~tfx(|?US5t`o2 zls`+_FF4^1-Cl#OI}sdmAFO9C0PgH)KTAhrf;2-E)d!i;>ckH>!s{Sn$;JNTs^Vh^ ztUHZN)>iQJS^E-Y5@se%m{WonR)$U;7?FZe`mSS4v#ShBEvE^ z@7LDScUUloh*#{KJh~ijhxaloFJ|l03EwJ`f6f|{#r&8-ceXNQ4`AxJob~(4R0W|5 z=cQ#hP10p)qYpCF);VSyQ;@t#ppm&Wq$8`LQnS|`#64Gxhbg|ps61!HFBHFAiJHPJag{|EV4J+x}7{0w?kw)OF) znGxZAu0bH>s<6A%{9KTyQ=o~+V~P1cu7;=3TPHV?apRfd<5b%lhWYDy+7i;ctXTS{hHfb#C=8N*o~hO9~?6ythr% zC&$mfnRF^>Z2$1DAWCIme36c&1l2CXF>xZ2S37lvxmLriq1!Ekaz$TtHskku^61-z zo50?+!~Fa^>sP(Hb|S3lLUggmlFi3NH_1EmXsI*vmh8Jl%}em$^{>(}g>j3~8&*2C z{AiGP^~oh-{*X<_3MM@+W(+X$oPBd4XG11`M0$6HP|N6+@mHMne9cqjs}@S5?zkh( zl-K809+_@s=K-)Op%NHfW9$etLP=Tyqvm{y9_=qL=9ZmIw(?$GajJMe7G^?F6MZ_1 zX^ShTlq1C~BHYepe*J}pZrW~!um@wY!f0%i70K^Oe4Q(!i_@YD<6Y7~L7)0h29sv7NFRaM0N;dOi7 zp+AX!xK;7p({~8whgm-FRP7p_@L)StDg_Bwon-QWQF zsrr6m8{6-LKE-O_6R*oa*oB5|Wq>6I{76e}V~q$BUYoqc#}i?1DG$JlfRpv-T?@0d z?(;8~n3-6a!VM5!qRumEcWjog#jTJT?MFy!;c7~IzeuDs??Q$*F@EbEL(kVWURykq zRhC0jc&77&u>V$7wwH3QLrc^tH=Pv``c=!oj&$9FyQjX-6STos?abjAi{I}wL4YoW zVb2hNt9kII`ySw{9Bf-4x*Bsiapn9;_Yk<}U!V19d{vx7KBPPPRr=I#Frzt9FvA3C zjr-a~0(F_4R$@F#_YZO!<^|s6W8+yJL64S?jbyb$SS(!5P6yXi#2r%x4Wum=5wdfC zMlaiR1Jf@oR|F>t!xALbu*U+KEQ0pmzrG+S+GV(tIh=-|Rr6L?{!!$(xVoakU#2!2 zL8_=hGj-lAANhEpG}#^fk|7{3# z)>u-}G$(pTT~{343ja|&n^8cp-s3xeMM(N9IG4^(kTV{Jbj8y{x%S-=dmFP3xRp_i z%*9apY6Og_3Z&Hl6YM0zXQkG5^P*lFcp=qp3!^F$+>^`HGNWER2= z&+?VsDx%`pQTbnOTi23CnM>bPXLI8I=DMA3;9>Ek)9MxSkYgPInyvGb2$`?Tg`88? zcKcWA(#hZK@|5DD9M|9@2zp-0TEuun-$v}z1qI* z&Dndf|6;8|Ah@TmR_%tD`#Mb}fh_8gFacxx;i?ZI*Un@vt&ToLCDemxy`A`8)r42o z-A9828qMNr4v#?H3kq@rfgVXX?)x$`|0t+sZWe}Ey+OK15Mk+cqGUQf%1r|FN3(a| zoO=c253O%kuZ{^*8KK(Xr_9|QD5c(@GVr9DTQ{FDVJ8o?&pel#MpWFrZIR zU#iP+Mh^A^Xf?gdms$)Vjr20J?}IlYyh*v~7Y-EWU3P~$ikC&g-kG+d5hOpz6U}lz zU@xn7XqDi(ww>j}fs9zVUQb1~tPQVBI(G6itB%5R-z)07n~P3Mc6J?bR0ZEz9<1|> zR1)u$`zpuW9b&6zDu=#8{6`@K=5P`6Ba-hmE?BmMnynnYzlunB_GFcPHI!`CUg@pGzjkjg)V@+EYSL8wK9O9UOurLyRz0d#)dGuOs8Zl_SE2ivh?lsX-??`UEWu5>S z2UTYAz*pz%KL3E3(J%O?mnKLXk^ z=*-RXkAf4WgN!LQZCV|w|D;*?dk6D4{?67znL*jfLp45J-*r1SDpfAYnsOD_J^>^q zBFT?Gzy4#5(RDSu8@B$V+Uk zJ>E9KJrQtV6MYhLJL<)i3$qjnrr=Cn$k6<&@_oQgkvohPh)}yp&JY5p0#oR4orU^{ zAw>h4oiB`I)aJc(B)qK+gc(`mRR5`(pM54hiaYq4o=w=p8%_8N6H|P7xSv$*R=l$a zPy5hKuahN_oDgASJ%t1XJvW=MUP~JK+U1B8XO7?{K4G9{axvMH8C@-|_MeIIcL$ARA^_J=n$-rEa7LkN#|FiWFa!T#QSi>5%&1#|71F3DKg!|4i{u9?X56lce*@A3sStuQ66+Oce;Z!KUoUha zp81|OgzQ(d9@vB#)~y6SPsJqB^)ckB>s&sTFNigSf;u=sY|86l<|}7xg5B}2sw%2D;|^~t6pz7l@Yg>hS05%RfF5qI{PfQ- zDOp1O%(a~C3+(4V@<%KdvN69)* z42|EC+J2Xp^eC-cVtZZ6dob8Jw1 zbFcor*W_e_?xud?t9_c^#DJfA)b3M!&UtPUJpY9lpDR0}tbU=Gv!$ipnM4V%=KGrv zjk`N8t7Xh(#@)$0{t;NlwvBG-@7-YvC+A@%j}hF^W!hmssjHHI>Q+fNTtksD{tMH= z=fD5M&CKnzFk&%YUShS=`&GZf6#YacEf;2^1irjUoxp14^xouTJeojT05QGWfBC_| z&vW&MHa(P${G6C5v!!oA+U6kx#oFsZQ|$@6W`d~U9vH0US!sS_Qs+=xzEIr$CD0IIi?CV4FEfKx5 zu2oFFpR-E!-oL~%S0j7nbw+wngy-Uh53=5D?Ijw!E59rwu-PTg<#Lt5myL0_hNynnh<19cg?2cWGNZ5%1BnA_J-;ycC34bYjt*_OTWX!o9H9M)sBg z$ES(Zx!8l*Iu|40C6frPp42O-2;yU(I~sGgx`~oTd-Z4{Wn1TVW_C&myu+R>yW}Ew zk&uXKy}kH6T600HOON-u)}b1_{Ak(nAh^!%bc%|3TU;|En$Q-qcQsoGmnwzx>9 z88L}ot3tDQ3iz+%A|fK46|=NW;B?6J+Mn=_|HzN52=4Ai&&KxuS|QWKb1dG(8$pgo z;rY5nr?RG%&j3W!p-p^lkg1wruQm0BkNfpz7D(pe)1VzP77CD zKs$-JgBKP&X`QNBz z`Tr(DSN_fZA8_mY9hZ@`12|mL-^H1fbVm{g6^AgG?umZdc7xnYJR} zY0-ICDrdLLsu~PM2u-eMkrxTbLpy^4m%zFt@AQO7AO8I1#+9m0Er+x6I?n~Qb)o}r zY`10H%=u!YJsa;{75e!=C2P~YGWD7?d_b1wmvu-0qTu`2_j{i6@O8k6k!4ptgd4A! z_S4y!v03|F;Rv*^0ToRa=y>Ihm$ud8zy4NbDbk5kXcSV$scV^U%`a#bRE<$Epo;9+ zA}pAT@l4sY9NJ~Ec);0r$y}=$AkG~ZmJthnb%$PmRCGT&0Wn#v31d><2)@L-Vn@5^ zA_MP4Q^hGO_%wKqckVxX1^PO7D2u5KnM7BM;!1{b?K&^kDC<5UQ7fpKy{)uhrE;c+ z?`7Q$woB{7kBO!%i?1XT=-qdYozS2Iqf77)kR#zW6BX-SHM1>J3HeH%qhptsAZvT* zU18?;Up2|E5~m1^Q7b4;APrd-;rKr6NcCQ zIW7D9+MSzfbOvqfcb>veDh|1(-yuNwZ>X_XN8O?-WD@Y%TQ~J47$>~1zy3^0#g*#& z=IrEcZ=*FbUjh>Py6n<`cvG?jIM|1;W}BM#uJ$oGlG!uX+*`Ezam#A!H%#o?%Y8D} zBs@#l;Xl7Wn`zhrF8Eq_$GPz#;T27#AXQ)wa?>F4w2p9(UlQI~Sici4z#2djsmg+X z+>6kZ)xS29Ue#AMOOzArj1?8gz~$U{*>^Z|uaB(waw%kPmF6Yw5|oBF>z!oHxeG+u z6uEbY_8?MIX^mzJXrw&gL4uQTH-k@Ktj@neZ(~B$xv?ooztrX9q*!dqi?Fd1C|SI@8!EEQ>^mfO4zr@xu!2Nnj0Np&Ux@s-MgQBI5Y_+ z@7GmsEic%J>2eb|$thb#-IK2NUyar2;$(QyZ@wf3X8!m`p_52-EqEeV_Q|cV==Kd= zl>Wv2GIc~>x`1z{qA~Zkmt-anuPA1qgqrmE&vi8}MLUNz5~{vzD1haD7!RfKOB-P^?T=f)4RBhSL$_ZGM1RCME2 z@~on3wUa@IQ<1&QZiVb_>U1zVT-grxK1&dD>Q@jzF^@oO9v9?R?B9dqWm)lc$yYr0 zlOG0_QxQx{IP@SNdb_Fmn)seu$b^fDMTg6xDOmVYdt-A`57*}k_!GR-~KqL zAipr)TcbfESkerc68a9JlVO8jj>w8RyKqWpJkt>mxG*~;N*l_i{4C+N74VIpACf@G zXkPUmf8w!3gP2GmdgTsW8-6_ye07`YV*gPs%L3SQadM$s0=r75jXb#!IODT(* zPG6tp>#r{?7Un-Yy4_{;SbcAEr?7m{ynW){N+zpa<7RmJ7qg{#6Fs?iUkH;LCUlgU zTR{g`i-C`{Gj}xE(&GKAJmpjR${X?0$9JF{zu&F}M~9(b{Cw^i#jcuJIVTgRFPGBm zbkXvU;#;^OS7hJ1iju=Ihwh&_I31PD3?Vjm@#nEj=abz$I$Wt^WRhv4OQ~s{j5jK3 zg}Vt|pD?Lr5}>~-?{XEL?{m=?D=IS-FfhUSI-E-cZ!3YE-nrbKaX2=4ukWp;~9qS8!qSo!dVFSaiHG>Re@y~mMbr2#U$w})$$HW_!<77H218I zHfeA2+%#6YV5UM^e36jTYwR5Ii}xDpyyq^VoH?!~^`qCBKKx=z^!4K_LU_Hl;Ze`; zCmnkxn|Pn}!eI}NEDhk7!FIQ7+aLHZ{30Ke;R+idBo{Bde)_JChCxNSOGAU6WtZ`x zqVmf(k8-509O#1ut4$u;sRWuy%y|9~_7#D5zRYLbBq2qE?g|Uw!RfIhS#fRcj_0P8 z-MvcYpKAG_Ogr`*?w|g+4Udhp?Tvfy-!^{_$+zLd259F@?AKL9 z1m(IznCegCWm-@8GKA{m#ir_0UU7VY$AxTEc88W^f73>?=UA%d4hTbT>#d(DE`?hZP`*5 zT|e78nSfHYDBwqS{cWCCP`hS$+A6AowcPGxBc4??-@z zo3IZC>EC7ljvKswWR6q!IkmJLS!{G(iUjxP@tD0+@9nVyEWj zF|ev8gOG*ob~kN!gfGtP!{8?HvjmgA=tm{M=F|bE7`8=m4jx_F`d<%ECW6EBc77oc z6KN8FhM$UKgW%`U#o7z-SqL#-y9thk)1PxOr*CR6PSAG&$68D-Pa2usGLj3dg*Yj* zf-cl!Lc8BYVn|KT1Br`l!6Z!RUMeU=xg&N_JLkY8`hvk#M zZg0ZuN-u6;g?f$30xTjgTVfNo%(?{V)-E-#u{lFdq-{u^z(weX$OiH-pg61MhZ_Vl z-0Vw<$S}+1D2bxfMK4H1$NB7A(8!Ho-ZhDZBrLKEMJe$S_SnlqhQNRk19GjjLMD1P zc+NJyH13$NDLl?)PtJa6shMD~j%L??E#>+(a+p7Zv7w(x>j2$r+WL9#txI5d&&Es6 z96jk@#ld0RLXGv!?1ilRu_3H@&uAE1aX}+SPs3fD3~833t?gU4MR;94Bf2)BgLOPv zR%<4JmUNY?>@O1*`>sVm0QUE1!N{(E%xCM$K<+`@<>?{m2N>iOxbo3G*s;vY^=-hl zOPwkG8Q_{$;Sn~YBa<Ve@4L8f?goOhY< zfQa7J3Dud$9!!3nhZ)JAR6{NgDQIRlezQR^7QE_}q^sm#@H$9j0f9f4$S~f*_0#_t zOPQ4G0&>n0(V7-Jn37M8FgyRXU;;jXXRrafeX0fhW#y7reXGZ*BDO3W*VmKz*k&R`z`sxz4=!VFEw$V=d$|JblE~zm?i^To zoqc)eHZ$9frh;kVw|n5U{#I+3H6ao$O;iSn{C{W+HK@-c)Xr3k_*=tY$6tV6gp2`O zARB%i1dvi{nm-8kr!s_p6rMg#SseJYaIqt?4UJG4{5=twcS7s`@$w*C&IhrDof2{B z^1V<7qB7nlb2J*}UieFJiZ&|AFhF@K!9X77GSpvZyv_Og_C!~c5_~?atEo5q(i$c_ zrmX4gl?z?;N2xPD^)XDUE9ly$#PI(etd@xjeQad)kyv4H>O+Xe ze%0)RyRG)d?^nzESe4U!d2syO^{hqMwkMExIkNphrfTo8-qgOereA?|j}LWXW|fBD zHDmHa8$uWs5i5X4b*sFwaXEa)1na#1^1+F*`uUR!GXdTk`XwfgWBZ2MBHsZ{L+8lE zuWZ&rijNabHV-&dz}M?16YW$lt0=Zw-MExq+G5h3tBdujrAP9ZIlYSn%%GCY>TI^} zZDZ#XWe<_Y@D4dxAs*gGX?>ovsINM|zQqWS+_BxpJ7Oa;a0VSpqX?g7MbDap8+Oua zca&$PwJHVVVXa!b(_|aMaOlr8FELJ97Ds_E=ku%>@4SuC7=YUlnoVTC6GLX1&9UI1 zA=LTUX0~h!x(5q-0&C1MMW%xi|C_8eZ65b7&^lbBr}w${=PrXFqDVAk=d$p~(LF>Z z%U?F*MW)i{;(~m>nzpaLR@sx?hORbraRR`LC%~Sh3jwBZs85qi1gQZN3yC)Ybq`16 zTKYMj#UC`x?tp;M$1EUq5qE4rNWxHz&D%&u1X)OKTP|sa1Bo7M#%I@M16sT=-tRao z-`tY~PYer*4+CQk4e!0ZZQ9_!bPCU1PzIbMACMr{pPR*!2Ds!tK58X3fg^ur7c z7o!$f5U(<3!98rAqs|fB?i*ouK;$t?BLYoQ=$D-fG{T*D3-8!rL;&mQIQ@uNe-BCG zi*yOV4@CWrdn+X!cl>8#_V0`l=2_)DL!YvGv5vS77>YBH#WMW-bqW|`AxSlEA-4z@ zs~FF4*kg%U;)@5-TXpd6lgO!2~O znwy7I)^>LXNySI#DOj#6$(Jhb{fs(l+2RQhk3R!Jf>cCGlyIKX?bAQ9P4tY@ zKN^O=z`_K}Xd)EjL{_SG^tqB0ckFqUvPKKvcM?s22@UPEM2k_;4&)k{W5s`4YkXue zcFHOg(%ix)*$w6O`wm4I^r= zuZoNf6CbA9B$xUqYszX_jHsYUz6!#2jg#?+F=*6jweH#x&7ygH|GmUtLysSH!+Tq_ z9hp-nw7PiS=>r}zee6aiUfw$$dxJL!yw#M+sfF#}`~P!|!`N}X%|-scXKK?&1(W66 z%NzAtusX@iLhjcwfr!J|N+N_*0p^4m;2=>%HQdClzqF2Bz7eOvxBa{QCOWvKH~tI? z60aaUEiXmQLeDcf`IU`I)05&4nheU9#TD#|c59WZPv4WOYyMFnpv*pWk)xP?@3*I; z@16c=u|>|~w={Y70|wSrXoFA0>M*`!lXEoJ+b&EC?5#_oEH?8W1*C^d!6hb7G0}_3 zF7Ad}(m#qBR20M+xv*|R`tB2}r`W}1#?Ru;+i~6TvG38%0cb)>UwaF!#-Px%Gu(m;J2NV0p^^GD`ay!ptv`GS>x^L8-Z5zU%Q;fa^EJk zwx~Jdsq}H4eQ*kcwIC29YleQ4=c5D0yOlMeFB;<$t|v^MUzd-+>)lpI|KOaH@Ga2In@} zs6jWAQ&>!Kz}Ys_+8De;1NOu&?8#Ic!>ai%!#!@-H1LbLu6s_iF&CoM9h*_@%BF(% zviUZ1$$L%Qmee`RbGu`m>Q-lpby!%+==z13B5G;b#&&5S4JtcY zc}?~_#66HrPswb)`neKVmau(kL3~U?9_^pNS?6tcS!T5y5=2a__YJRX4xlX8+PHyo z`z+)pp}E`FmbIyB3ML_YnfG@1=k-6-l@wIoVioc~v27W`xI(F+KjG<<#jP6)2-8HV zZlkz!HnUy`?u8JTlL(~qDBIw6F~-Z99$%dmx_5ZPwe1X>Uu%rML5+I@lwysDjr&Hz zyzVMyzISM0jx0E9f*;+dZcX};;*tyZLaeK5z3i-A1|+>*#yxBgssfNL|5CL}P}kLY z>&ClSyklTBUf=8!_i9HaW4>Rnem;{xwP2NY=xUoAE-&7f1!Eyql(oPw!36X=&4N;g z4~9;5dvg81o}3pqc}S3XRI&l_9uRt}6yMM=PG;4Ud9G6$tsGbAIU&bHQcv}_Fkp)9 z>8uk>mDwC0*?Y?XNFV%9}D}U4)Db58t&(r~VnVY(6%7Ey=Z4 zKi-HMU1f!LJOiY9bUiF9G>zl3VunWs!BwP`yTvDD{IYFL`D3o+ zVj+uMX|rj^32&?BJuBZVt-BS`fo&_(I7k@8(|3ma$Py;df=j+I8J+@;s_&)OP{E5< zb8p&?LkXq?S=MVx|f85eoQ+L7b_7dS}G4oq*^qzw6q6&$j+!{FitWHTjL=6Gve?= zk>RZScmwQAA`a1E1{Ry)`Qpl@5b<>oBtP`zYMabBWGxSLOWY?4ju9I7(G%!A7*qEj zE9qrS&|l3UpQE4={w!?BwPO2+#yTVY^39ehrY+7>FCE*6uA~BGTHNf@NuPKrQ#_-8 z#PzSwBgQsHn^_f4Hq1W2Af!gw5>QmSBR~X4WKlQaG7pRJu~yNn`?usTs(vr}d!(_U zat2!z%VG!iOi*U2r5@|tyN}aMdelw-r|1>Q5$v75Rn^_>SW6HdIi+`h@)Z1+Sf*6_ z-zN3`sH)C(?`lo`feMyx{!|yBUQF($TW{PF*Ss0YLt#+%uI(|YzE0-mvbJYjObF;%)lK6s@H3;=Cx9}{#)5)^1e0l&y|ILQtA>6c=Vos-F z;D9MKINo`1xe+%4Y}Gd&5#C&U*GBm}TGZk8%b8^F-*jqU^W;4O{pd&iAPbXckTl9v zIJ7n)V{LE>|6J+#TWM~cXIcyiw|;cBFoJ4pIHWcjhnDIx$!0S#{FIqtfC)}Z_L5A7 zCa%Hnz&*GEFR|R=YpV%a42`%_TY*JVhJSm`BRe@y)5VnE(nrv|)1&J+M0J1bokyC5 zOy`kNEho={MrW3bGBS!orNvY@KVpLFaVvmuw404oYpuO999~{Ncd@Z} zsF{}KeyKuUZlffmtta9}vEqqd7%rXtgNpPs`n<>*&t{L#uEQx1zyfq1w%5e3l;JKh zpl~!sC_^7EYAtRlWp?zLr3ktM9ZP9Z`DyUzqBU@}d2?%P#~mTDcT3!%5$H9lp$CjV zVBR=l6*PR3X!Pp7ZZnVE!R@!4bUGJmqrUE8Ue@>vGeBj?>@Zz5G*QlApw$ZU8P6iK z>*N`at6AW0)O{?lc9GWTee5)Z_?Q&F2hAWq1Ul4@gj3hcIr2UKt9#ZHG8l4-zsW$~ zQ3{7%qo)UvD$!GnBGWOXpIkL#*z)0E+XTlvY( zsF3h?CIA$vw$&^SSwYqW&M)|f(uMB1|IisfXjo zqHLVaW;;xFEZs`4oP|lZ`7}?B|D)Jkw=Y-P)P#(b`^LhD z^|Ewke&YK2fEiOKy1KPIy{RBNxWs0U24g5Hs>8xXavcS;10BK>Z+El4Qz#vokDzhX z`ED0O`|0>96LGY$)mma;B?oOX2vaHh=3pR|aNnk2DzMF_KkL45j0!CR0j<-FQodF8 z6ax(pWSt>Ck5iwbDR{~Wv%eCUS_+?EJ#E3u_tMZ zp=9z38O{Zo_fSv`WjH>l-HR~LJN{W)q|-gueL}-Hq4v1G2eB9pv=cMyU6$@GN-3?) znj9GY|9p8BA>LD))*R8@TMcnl1_Zy^i$j~|s&U4%M*DDD!os9kibt8LZZ`bhJHFzO zC#;n1#J!4y^SMtPAC%dN?O3;R2|l_9IE z;@<>{VeEvmGNLA~wym~UeKVk}{qz@V%sy$tf=1fhxFw_72JygW`yf-k@&pkoJI^y~ zS9$p;t$dkRuj}xglEYsl?Aax;%HrlcSdyz?rgHCRzSkVvz}1|MYqh!>PxX?Ec8iPsLKUeBb(Ry> zKjca7kVNoG-_L4CEi|(?focPm`VG0=BIZ@LN7H3T-eF1Ny)X-h-6j=2AY^1)uk4wA z5j$IuQ)fU8*sp(|-L-(+GAa2oHEdOz_l2Z?Yf7i;l{bv>%hjozyp1q z7GxI<8qqkBb+hOY5f_#P?q;QoOrhRw^~J=*z8$F3!mghXyTH);wR1D9vdveuD+qrV zPj$z$l1zob1l_cRS=qr9+~#~O&DSe;CUR3`&*6B@(@%uye9d5Rytxu=UgVF5dC*`F_2X+yzzp`YSp>lE#?TPO+ z)`E`H$*H(Mg>o-B&Ln$?8o^8#m~Et0$S-tt2m;8q-ZlqpKVdpBi9)A9~OuKOdeFeRST%jlBz^L(bRs{R?pm-|_TtEc%L-NpPs}<`STl-L(Dn`ZIPf=G1 zY?l(wAxZ!{F@bm=FJXmz7S=Auu(VuU{_{bg=Pw4oGYu~Y`a>J{rVam74%l!hKa|gD;mzqGaS3z{HhOh7tx^Tx(;Es?P zwt40H*nx$?Vy8-|yZ%n*_-TYfyHV1fdJRJcMAj!Z7(DwTl~x#2US=%N&*m$+^y9PU zr64b^H2v3{$eA?xX0&gj{~k6z<5$V{&V}psHyw6W!()DX+WYj7oWDD|+7vI1|6f%g z{NLFBLDC88CXhSOqHmR>rQp|WJs_lo!tB+L|0n_@iy>LDa#}u@C(*=T#2uaQzDuro zscUXRN6=n|_+8L0pUv;?-!QgyKb&TiTWzenijO2?m{>E-`Ojrw3wI>SCB!-~@BwUV z3HPZh72n2$xcj(7&S+veD;iAm4Ze|s*Tq34X;_S~Inr@rd1#eAWQwfZgcHauBA8)X zPa{Ql86Ka;dTVp|z>@>bw)g!eccsDkaLM#tO#QFnsnk6vN00x&x8lz&iiVaFQy1hL z{g2LVL3eYl7KUpw4m`q-A9idtLnHihB-rP)YZwv~AGAS*;!8kQ-}WMkf>;h9%Ak2A zPBYred5dKYh0fXjRBCEf1<+R=X@MDGx7mo3fwfk+98}BbGMDY7u;STyW#2>#(&ZE! zuD28@Jo-l?hOS&>63k7c!>{&m%!{^2zkZN#B~5(m{6FZ^tnD4BQSw@`-LCM9l9aOk46o?@#wTg>NFazx+zOO=tKGC5M9oaR@NYsf1_@*8|;* zBC@kQ`M}=5(6V(PjaeX7aQBa8D?;Q}ADb;N1s?y?sqCmpWzvci6(a3y`PgOQRrQp( zz0If-BJ$$usyJL252u9j;3MN|n}NyHLVGIs!DR1tZR5Gt;*llR-;+_pEADIeTL&UM zWgS=RGLd1OUNcj7s6wWNJqhc{ZLhXc7pNkDE#(KOW^#d0kzspG3x2`B!2ALF-OW%r znhq6%O{hxj;4TKcH50wK71ZEyzr$`%jaJ7jIc2u+eM0!Fo01>3`Mm0v056~KCZfTd zKjt*q?{ofVLO952&Z4Id|Li>+6aYIi;Z!(yWWthofyUV`>`H{6LS17AJta2#RHdiP zR9iXR11%N4yHybZKEe#!(8P$D zQVXSe7{2;aT=|}U?kMmQXNm?+SoaA`7*9|?Zg&sx{*!P&Qje?dx*nq1-|ToL(B(m?s=X zg`IQ3^PrSx0_Q#Mv?3zWW-p?Xt}}+-#5N%r7LUgB5)D+pv7&ZHuBS{Wi@KHRednaU zEcGD@eY2S+@lEHzlu{P?Xz%IR%=%%VN-!hR&o){jA%X(p*xOyxa+!2Yj%nP z$RS{!eq6C$&=6iB(>;|nH{kBbYDa5`^(>Q4MVR(qxp*OM8<5&u-KCeD(#3=>MbhI+ zq?gT7q?DhCv$&}2B5S>aK=8Ldo&8#ZV10uFUrGo8wPnDNnezp__YiSt|C73wc*a$jK3AX8x6&(8a4YRk`jv|C%9)mWEUFg~iN2;R1dycA-6W$+ z3C-g#OZ1FGe{=<(CCJc>yuEe$!m=6X?Shr0@0wUn=yw@K)<_V9sP;c%#q2PUK$C}+poQdcBWY@yxND_A>Y7g`}B{wM6+&xv`q0W~qx7}{9S@&R$ zOZkvl=pBd)6aFfJvhPJ@Mpq|QL*$DDSx@n`6b(wjL<8Z~p5_=5HA|;|sW?4$Th_r{ zY4`o5R-*;zd2ZvY9n*UE-x{vRCA&_4uL<=o#r#AkO%$kw@`{GnE0!l|C6}*?{7}ZW zx>cDLxz#}cG|#;dh>pCu!O0~>Nd-EY(ZNxBR#zdCIfD#``3IwtAm|3|(EVGK9}8Kqo!w9jDf_qy_j0oKV%2xnXD-!gN4(WtK)=aim*a?j55XPNA;C%7v$nEd{Mb~>qHT6Z&zF1LF5s+S@(o~xCPDBKx zOIKP{5Tu4qfRHFkZvp}W0wN%t&^rVOy-V-CLm;7qKtlfa-1o-2{ zz4lyl{+9LfS)?I`20m!yBCqJUgXa)8OEcEo*+1A<5)r~PQ-@*t=pJjR3Grd)r#2|; z@W*)dj?{VG$u_s*+L5}3xLr{m_0iqd5*qzio>+rbP3D{K&b-emx_aYs?Yq_?>_6W< zeV@rXU@t(S-jcaZqKR%d#_0RFYBbO6>0Z?eYEe4zc-&Vd+5z85#>y7nxW(9cT~)&& z_FV$USJNRIdtE=aM@Fxizna9ox@~ixg|o@Ah8n!^$L82>+jP&8M-2XKOd;=^ZhcOR zt30k2oDlE@GI?f4%2uR3iU>!pL4ni~!!3bvrI!Lf@P7e2k23KcRmH?rq|$X$9sOD}{bWb)t!aYG0Rh{9C|xm+?LkqivIJJ3hg~ zT8?gB99#b${3@-v-M3Eug$4U_?pD%boJE#4Tkj|vsNidWKyim&YWCtoE~0ZT;}CIj z=^)4xbaMe#(}n<-;*F%F-OL(an-4%A9#w>JLD^wNyauy>TmlqvN0giEt4LT=^oH{FqRV zY!h0}sYt`BHdTaW*!?Vwky74G_pssR=#T{E}O{2^CoVHcAS!m?AfEJ-q9VAf+)liXHhO|>ZL7dRm;1#}e0km*BK-vxdU zhI;kEvROJW_t{Pjk)E^dZmEDDd@6YSf52i>{cpda^_qEJX5e;3g37^*z{(u~aMYYg zFSm{CX#b}7M{S_KT2vdWo~A|1*1!>R8}B#_Q+XgdUGDAb*@0@o;A60(GaT&GI=${((2X?T+)mXn(vGNJ)Q)OZw(1d#r_}F-W)O`%Osl zo_tEbB3G!A zL1myZ&AiHhcL(7Fv&C4BpqH|g*hU*QR$k)&<~pwqh}w;3U2)zOT7xuRLg;s1r>2P( zAYIKDa=QQe*`Lq19#j2aKAwCbSLty9=4A%5J%NKpR&rkXkILZUqNGpTZOz$InH4mw zwe9%*R?P3<%3kL3Z&C5AN>y9n3ZE8P^d~6S!q#~)X`8}6yv)oN)c)qK4+qaH^Gp|C z#rtf_{RQ=Jd^H#h;02qLZVpJC_9kAPEFg8LG<}6eq&l&I=}_wwyt=L1HVs(K8k*pC zByI9_ple}^3^jAEO3%8eSUO-#<{4Q-*nY+Y!_q1Shg%9y8IM?%#LC;B8mC8YW*QhI zByXHM?_aF5FuLEk5YWZPy;*xjbZ$(!5PrIK5O=DVi(X3U>LEtqdwYJ#NTsM;0@^pg zSy_#SIz|YHOjoQh4s`Ql1#-wTw05>|&r4 z(Jc|`Z;h6O`xT=HbU!RE5;b^_sE`>SKE9~In?ji;3***dbE;;P6Ak`r0VXxWht^yH z%qm)hNn$RZgjrymAYa1)Tv=~FaGP;TzeD-20Z{k1x{sNwRj znrkO#Eue~Z$z{kP-&?x6HHE?((;2`Oc?fI13Kyy+hW_?Mbu=XdG4V#F3?;XUj2&l*M99}YE$^g(90 zxa?$RrZlG$#gGk{Q8&x#e_TRl4m+YdL!%iHR;<;y4-OeDh`X@MUF~Q(>l?j?oxwXc zukX={AAEf6?J|Bw1uRbmJNzu63m08S(wzk!2xHN~H zzrGHCXwLXt7T@o_XC+sx{uCdX#nK#Goq=n&ez0<8(sc~Rp$sO3y^yTU+2P^er!;F> z9?r;$(Joy>I3VWTtRRR%G(D=={M1!1r!w;gXZPg4J1zfFH9^uoO3aBn73-ZPQGPgw zpvQSKlJTZ(F@OQMMUHl_>n~-f8gjD)4lUv_&G#JnBiYb2hI(4>YtK`sgDKsHyr8s# zD%|ZeZk=5CtR@DYGO-Pei2<4jKK&(kays)Gv%))+DkCX_!x~xU-v4s*ty}^>^ZoR) ziBp-aR-?oj9$!0b6CSfl=DLk0DuXavWKLYrS}?mkeOJHfy;9HiMR)E-c-EzuV#HTU zcfB-bo|@o}i$Y*vGvX%~T_$g18yad_qMbJ0@Ijd_6in41S=S zoYCU1ERB++LWWyBzSBBn!HS>y!g#oTAEQ=w3@XQB{D6NGj}jM=nItO`)+{q`j#=Jl z4q={raP-6qUaP*auvxk@eug5k!A0?UoiU+cpa=X(BRfN7)JsN^T}N)^xwzzD_CN~- zAP#)?{pJ?Ga~E7il$LGp;_cXEO>JZgl36S+syyQ|$`^6U?;7j7NJ4&UG9_GYz}H}C zBeB;}(__F1!1MwIU%dG4Rl{N;)2y!GAx`*VkmiwJ-Wi03B^;5!>~><>Tr`GggD z^_9IV_qa9iw42-d@M~p;=0z9l=UhQ1Y4KcRO~&6TmX+%1^C@4=LBo)!kNz1UY`4!m zW3M%PpMV?IOhZ|2>LS89u$JE(8CJh4cmd^ zgx%jy;(%h19-? zGZf);nDoYP$EjY=;c_nt$;kG%qM|nAm!@OLRpU^Tqfu_yKl<7WG!*HIxdlw@}I(0zq(Oil#j+b zZQ8_?zNN(|%2Q;kG+Zc)$hU}{^yA9%FG@9LO<9pjdAgpwZ>sMT1qZ+HwW+CgTwfn;`?v z=UMx-Q*4ffsA&l1^YA))ykwKg+s zu+lh4N3o~m76G+L6KxNK_;e@<@TFH^lJq}vS$l*Zq|4bu(d$3YJ~OV}y@S+nRkK=94k{>cSNk=Wc3$|4 z(X0V&6R=5=AU}Xyr3^MRrFJ3ihgjlmGoU^SOf|0sbX<{3u>CFKk)FeoOFiiQU(_>)*ntRnB~Om3QZJ<{oH}-B1$&G3?k8lq4@OaNC!KqIAdWYu zTp;4H^U!|Q3^lz*Bwz>rT|w7@)Pb4*T*1EymtoZ$`&6S(_=jwfb(2{6y*|F>i^RUi znRYHP1EzGtmS(2Xy2+EpJ4Lbm1pVYV+0?!V)_1-%dO?%Enl`@0BMBoHY5T`|Ah=_M z9v&3r<(^n$;#S;nm1QVyozCpZv%90+OOcbu(KHP4c5hhT?;2H^Mdu3DTh`>SjTuHb z4qyDdNKnwvgf+B&ZKtq{-vL`x)ihRXG#~3f697d17F~M^Pvc>uiobJN83Xn@I+~bE zV@RX=ev@F4wBk2q=MM@;;`9r#;+RDaC3eU2NWT4riTm}n-!3IT3SNKndkFOGs)v;? z9PY^{=!@>w#HB0 z+Y)4@8g_=H@1fpiS1DQ(2)K$ZBuDeDZBYp8@4&&q@f#p_E#IuWX9u-Q6vp%2KiW2B zYKdwII5E9t2mo;ZFu~8?_f+}Q*dj&Sj|CZy?vmK>TBR^@h@5xL(#}WDb&V&LkObQ=(T>g6BqbS3BmU~_P=f|?| zRVPTS@(PHZ%!<3V{}ph(O_aivRwfMd>z}iz#ohUU)I1-Ae?$X<1=(tTdUSMisZ8fb+Heck?27|T9MQk3dOtpsn}3#Z6LpYNLBc1N7XCM zMn1a;dJqUmx1h&9&4sYJEjeNd8qgy3a zGLpt|)uEKHO03F~xj_fQf8+ZT-^5w(N#U*RN_Kev+Q(`vz$A$i_WSE&8S&(y7a@37 z+$MIWyo)3S%M5$4F&*uPEYXLg4Fg?WPWUQPPX{o1$E35eDzPwL}$T) zk^R&fhuVVPF3oteJY{O^%P2QD(A*>Ni>0#()lIS^0F`d#ymX5d2cEy3sHkE`XVqpiJ5hT#eC;(lLj=>S6nn%c>+inhQ;i&!4Xq|nPbCDZpX^RON z4$7OkQP59yZAF#=;hBX+sp$cOui;vSW#`*jDvSw#%zl3;`<$g1xKeeiL9YDk0i=x> zc4YL6RI#1O-cD4Z+~U%t44${U1rG79CyI&3ECdK_q?zl~*Iq>Tw7)u)%%XfjMwIRs?6lLERyn?u{ujKMfvIFR>x^xP6I`)= z?9Zg2vlIVeq6W|;$+mNUx;DAWI^aVopU5!Pr`Xx>CGZ|9%6HL=r-rD?*Io@L3J_Xq z&1t7SRvvYx+r;EzOC@=Iuj?H zyP{~T^~5>;^o7<3+YdbtW>_f}WVGh_0pU4tCCMUM=McZH@@5mxi*wd$%v{oh@2f?c zZp12TuwqP4d{|d=V%MiaZuJ^J9n*c{FyfABNkC_|v$7b9`C>k!KOtux9jyvyE;WhGw)j}xs~-`*c~nA^ z^rMX9PIsfQIHZb;DjW|N$hKllF@=2)W}m!__QC53=OisXlX$4FIcRoX=}VOM)yS}f z-O-0Xtb3gqr*V_(3?+eo(3$)60Z%Y1YIANwLq8YM<;9$DFr2phhT#Abw}^Wkb5G|WkxT(HTqe!ma32y%Dl5c%C>uR-+ zep0aK;~fkz8bq0haa*FDu2>>8{U*9g>Zo@V^2j05Zf$7f#s_vm`(JF-)v{GTEs;ux zsLn9NK`HYS|53S(My?s1t=B8v!VT>W;JIHD@6FJDTduFe-#5_8+hNo0ee^csUfIR3 z8dLq#ppQF#>R4x-RvYEkcw<0;uisVoLg614@-v+%N{QF(c&T^PKsaS8E5+t4Qee4I zV9+3;*-`x*Bs2cXp#g*f(l`|&; z8N>k7VN*9s?>Au5+tx=$zmPRr^8Ij}eWKD8be+1VG^$ex_qs^U4I&7)A%4M&6Uy*i z-x`IMk(afytn3jM-qKDb!dGb`>4_FkS0yjvTZ}%baJR1Fjg5@%S00q)9lFt9?ER^q z+Cf|*zMMsj_>n>Mk^=cvQC!c0rMeT=BCqujRwcI<6zayviueX~^ytYYuG|96(EMB2 zk1?*D7g^~7@v`kt&myw3_T|jHYlH?LFKYRK-&Q)FW!KaMJB7V;3*PhiV#aK!3812o z*CzfZ*n{+01S;B<#9;f-%S39Ev3uf_t&)WpCwywb$PD>Srvg9WSN)TdHzG^NE)M2`Nh^?%>5>4Ifh^tuA>p*hOkom>|g~YD) zie>#IZyoG_$2p%(=kxR`@zntGIngi(Gv4dw-fq06>6QRo~pRL|LxoTyRz6u&L1O1#;185;(#Z?2E8%A}t33>-98X%r~ z7@s~!`T9@R7162+!ABcGZ}%J2^}3E_a(H|HoO2VBmak{sx8lO3ZatU!mEzSPQP|tP zmnB1XoX1*D#~4^_f)kL}@VqizAQRI3;>6y$ws?~`phG)Uj(sGuulU;}Jz2|aWoiZojwYXBV!MX~ ze==?@h$hUwjvL&$cC_}++H1E$!L(-tUd!s2@@e|)3efJm8in=BxZ^;`$sKnpv9^f; z!Jb^b`|I!;d>l`UfmDWcT|o8lOgYOkjbOLT&~?YOzf7_BOZxG(*vsf57??Tf{h@-e z2&chZfrjvQ#ZcP1G)sCIUVPOq7_OT4_bZ;do%+>3=Lb>3LJwbz%vq>?_Ves6ikXV& zbah<3FBv5^p|3FdSX3e8cG(LUmCq_;vp9F!U6u~bXO*(h-QrntZ?0GUyl_%}^I{ef1cX3`kztrYJ|;PA|LdBiEL^6IsbK+S}@> z>}ukZ3+e_{YyZxQ2_iELtI*F9py2bQkm9}LdD(Wn!>u5j$4y5un&*0|M94}EGhBH5 zB<6}^Sq44KiRV-N@4hqZ?>;_GrhC&R)``Pu3QC~GNM2uG4@LB4?g4?C26YCKki{M0 z{T<4RFKw8Ma9DHo%}Rc-=7m~?Z%(u<<10I=SjZrSJNrn(=%6N7uVtr|%&&E=a{KT6 zfCTJ$vMgueG9*gxw^e02)rhrlN~i{3&~uEE|74G=V?o)VXLxdo|0hf;=*9wUETUFBFMx>-pt6D3n=XJ|2^a4U2)dy94S#0JC9h|L=o1XdJQ zFqK`4G4O{4622O=uk21!(^B}LN#eawQ&_7G#(NPXd7eatNfOj>c17XebOGK&S-shVFKp=<%Ye!m zLl&}>dgMiWv!`Hcet`bU6Vl7}E;{J``%$#t5$#mg5`POgvYFYx?~bV<0QUN7b10P$ zrTgS$T~Ygi?#mU-ql?93IpBnjAvoG(c><3p9WapYufrN9;71RsNh(y@WRgtUO0jKYL6t z)_*-}ihWhD2?e5|z{(7xu*dDLfZ8F9y;LmI7K3K4+8Fz>3+37=vs0d>J%8x$ea!wrK2@MDpbD; zv21?s7M8;iogrG1j2&j`vqeW1lRA-kWyrdi%so)WLVS(`LgJIx160EGXBhsc?nq^b z_YRnqED1EJ$59wo&!E~-)ceD$f5AVshI)cI6?aef!i(i(cxKSzW#rb*T8F7$U5VoB zuT8DcBQj861iC%tu@)|Ta00w1@G^Zm&PM579Qd@^!V5K&5kBLU7>}nhts4EngbT>* z{S$d@&fm1dO%my>b_W$y*(4ZXdi6aQ1GBN}wv3wIc#XGvvu^v^q{>pnj~YNxL9d%8 zFf09<>{y3%)}2Rxq+q${(GFT~kY$ZhBhAA1y6@lJT3j>jWqKyo&Zwhi_xI6@Z?Jw5LF(ZojC8!v3lXWCUTEL*jpM#RW44I)>E*j~( zUQgl2t*t`Sqc-+qe$huYaQK-zX2A+hm-Y6}@`y*uU-%}fSm(8BuF*)f=#iS-Al9_S z?+c9*oP8h7fWc`B4WgLk)gX)J3Ae~esNsqb^{RSD6vONIcBTdXhQxiJ`KJv@VNKQ2 zz{IuTMQXUO2cCbGFR9qdjE6106F;wWZ+7EOZahRXaTU)fN|&WSZ?(DoO9xYjpr$ru z4$AF4GaD^9QmP>~&OqCm*bRv&$#{o~>2`X_sOPaX99J^5e^nvG94UMg z(&2~5iy0}G*y?JQ+mT)$yYo+Tq!_FpZ!>K$ZbfkT2;2>vU_3d@@RPm5(=5 zfY+EmnMhxNX^`(aktxh!D)Hyv11$+4>B+Lhree#jzpE|GhngwQ>3`DQ_g`;vdmGO) z^qIJkwXjw}Ku`DYs0ezQ72hALb#Ii}ze0Z1s7izh>Nnr*h37}47E-tjUi}lZE zInfCTLw><9`j?MaT@~mcA>GGpWkjHpd5!7co`NKvw#97WD`!s5HagtkpV?Dg8`Im7 zHeG}FW9s#C5K~=Oac^de2YMRPmZQ=Q8hn_P**ASY7H|=ntP+(x9Z$L#4w1(6Cgk@(2T>4J;Yc&`&3*@#XsA^_oAptgU?Zzm{7<~ z#AASFt$k5U5!K#-TNY0DIe*O%o>3FN32Kr0vX1(_xq~g??&4KGmCuTfnOl+c4N5{6#bEn4&3DO4O_cWUIx7M8N*!6|d4fZ3{MTPI z=Y;|wj>;)WqbkCaXh(3EP`XZjN2FfS137?Q@JZ1pb;1Y5U&CI~RkwwA5!XJfb^F;Y zdCnnpD>hMU#b@d5ioGV5dW*ZYjrrQI8q{-ayG0WQ1@=BPjkcOy5212K43yuDI;B$e zqYc~83XG|^N~=k+!t**>ABbfviH9H<9LAqbp*FH(K0ay}=_z)!qi*uf`CSBg|FdO2 za&jYt%m~(C3)!1Wnp79bc9e4O_%htj6G@45oL}B{-xv$f=4+aO%dbMikfnkE08=Vq zshAx@C@0(KJZF_Pao^j)o z2nb>G#E5EXzwXuV~cha3MuPa6{rR&}mNBYR$S4%!KWF=63W77qSX?5$WUzF+D zIc+Ikd0C4}U)kvw3LobA|9M*58~t=Vv1}y(7_Q7oW0=z8!XGIU)Vsgt zH4D**H*zbe^HG9IX6lyEXFC)Yf_{Umz5b&Lb%N6_`BaVZ2G8it&k4Gy|D?QWmDf|G z-Gs;>2AiKvP`Jn%!~5@i0ssS$kVvMkG6Ou1cw+c9<>GFYS%gAF^8`8eOv?02rqZpv z;-X)a2c_(v#oV}&j9Qf z1Wf2qb!N;RGMvW^-A0!=d|1cpnvpBz%9l7B8a@=|CP!_#3LNR$Ac{YhDfr`j^ApnU z7ufMPF>g82JiH>8_IqvO+oed|B46(CV^?rT*pF(b3$csPZe&pXw~%CT<)(>JgR$dY z0i~r6`TvZ6Q2^>a?npi2PkpPh!-p2Rk(`}Deso%ik&(9!D_G6GN(OI=;%sH#6Wy|v zpJCK^A$dm-#vS8k2BPS(*scFrqXaHCrz>&6MZ)!n6lc@dpU}H;t)NsOs>iZhOS>u6 zw1}Cg9w32X%^Nm%#2n6je#}p<$NO9yvmciTY8TU{klTm0B9_#u@)v+$V>3X6>@S_( zo)}i=yE(@sI_N-4r{&9dnjltRo^S*c*a65 z9Fz2gYh1<<%)v^}Trmn?taP;P4&F2MMzWiMfF+MJ^yf4KvBTspvY~qoX-di*f{X6! zHW&CV((_!U@v|?GZISC5dfXUEGP+Pf6M$!1i5@`8z*OEKA}@c}wQ)urG@;#gD*cb; zM8+8HU^8~ltuK?ft1ABb|6t`FLL$jue~q_XZ600aLO4^lrjZ4RQT7-yzM(ZoCb84joHB zI^F7SQpFNY#b19yzJydPMoTD46NHJ%#k)-6Rxmx4Ms$dNbSGHK7X3E+6S=!fzZ)D{ z!c8c|-v_oqos}4R7)i4pcLdT! z+p2j1aNq+COaG$^9>x{W#quWR)t&%Q^Y6d~&w!793J;;#Lf%b3SiN4cs>frw6cqgyn7Hl|TV<+)mxFa209|nqNe^dYVcr4H;c;sd1obOwy%*72+)ZCubBs)n4Cf>Gq42W^jbz=A!g~| z6_0gXlSa)X+$~?FX43U}Z+V|ZeceuX(3^2t5b{|;cNMdV&~+>aT(&fPUi)+Y=8cBL zg@M4fm;OJof+LS-eD#e%-_)bwPckrWlqnFkU^AzMaL)DABACm+l5tI%{MFisfgb|S ziuj>ZN79qu+4o<+{$IFFs{g~c7RsA{4Lxu&l zb(+e1F zBM(@qdGT_{KPqlYyuR0QyzZca7jM4G;^FG<(Py2*p8lKOi187=KVUPym`W8AR1D_$2~ zvbhQB00%bnUi=~(+AYyCET|V)F3jZgOP9u%8!Z?Up+B9uo7`)39;mQ^lYXp!MopEn z1exD1D9O#+gjt-MQf{X4jKB?u3!zuqB(Nf$A$js8&%jG>puJ7jgyoU_Mq`pVY_bi( zKJs_`By3}JhUMLh5yZxhwD%?D!7=I>KcH$=Q0^SY;1h0D<$fGsZ=U({xEhCL1(gnk zNYYXv`YBw)3U7ZGM^^}Skjr^+kAJC4tYx}mT+if9bKu@MaFo(RxY&3lDg=lVTXBE6 zVt`C7+A8vpQ_f@k43x|S=0rN_FfR`r zwCXXDIaAwxPKO7qxpI8py9rx=zu&h9vinh@J2^+KTZ^g!9D$30O8gh;lsofp;m;Eu zj-8|q)il-j)H%~-85wz;`c%(V3!H%OIj;S@3rdG17#n(RWXJieYn`9SZ0CE-7suqV zcQs#s8)*Pb(h2)~HOsP%B|y!A1rA->-BxH4u_|wlk1P`JT=U%fi;kO6{@KYj0`uiv z=s#zX?5R5|Cb^)ormOQR6vhM0!R;L%tDA9>_B^B3_GWl|Z@=O9h>O9HCg0o^6cc4U z<1(DiehGCKPWQvy!h%&q#BAct{=Swpxe_s}c6om_oU+jU#C43QnQno1V73@J7??gs zghc5Z8+zy~VpeQXq&IM8;)yRlV;K>a2P(y}TI3#g7Zc-Tm^rDjO=%FjizDE-|Z~!t|EMjz^@IQGGN+U8G;eL%5I2 z`9*<2l#)8*gh>^4bMZtpub_zy?1SLYmTYqDGWE6zJ+Q90mHQ{-N&LC##sM}p$B`m@ zkw$j>O?=Vo->@w#nBoZgUeUwZ)GPb=zDEsI&w;EZ&^1gM?Q=_*&+4z)KH!8Qd|p7r zn=V3}71WnvrVHB^?%>tF&FJP{v1-hhP%0h7sP z;Xmh)u)P`iRGqjpK8RoxK7{nUlvH;RPW&}0-8QjmZ`z@kL5mGAi~?BngA%zeGaxEh z!|Ev(h1XlE1k$^@#W>rYfER!l4LzP+TGzkL9>{anHrvI2#q$ec&4tRFluNK6YULw_ z&{rj5uEBcuMX+Eg|JgRw&ku3S73-H5pUnKeu2hGbY}7#gSaN4sJF~R%F>%n~_ZMEA z_>(*E#7Zj@%Y>wF1|`PH!d2h1#^gEv{6g`ZYII(XvRqhHAHyE-ba82iw|i2s$j2q1 zu73{2enKiu$vbL)UeA$DE^-yvYavOQ6lVh1dzpb|^E z=68(4;_XHR8-cDqOQ6KXX|03=0~cu2jKB&agDbw6m^E}*d19eJH>b4OZN*S(Jl}9- zK(*+( zxyp~>96{v5v(ZS7CmTNuX8zd?zXu5^Ssy_N;<%)UV{{CN4JeB45kENk3ps3fSJyYx zw13QQ_N9uf-E@Bj7Rf>Uj;oPO|-PV9iHlF3l- zVi4#q+$)o^K;gxES7ckx+RGI&J3IQ_JG;xuO_S8QxV#O?u0cG*5t6(JH1oPM6RzUr z8d)Y?|DuG!DgAhuWZ=bmUaP#LqmX8srSf83f^<8IDxXd|RIoo|{%Do|Z1M|bs@^1j zHDK8OyxhNt*A{`uJJ^X*Tx z*3u>h9A!^>2y_n+cgJ&ZkZ1`aw1VT8U4L@Ag!fr>#bu=g{6s!Jgpdqa!gRC(thsWx7C*&urpeb>BAf3kiP7P_6T zqiM{I@jc|y@>r(Kh}NMu8x|M z@+J|TTK=n-rT>&QGJ4b<88D;_zX^&5;S3I_VWSa>7G61juN}D| zN4>knHDX4yPG?9$1uhB8&XxIxtVX0Qm{VN%ju{%sgr4+fi#2zi*#HJR7ZTdLS%KK$ zOnQx&&A10=&ViwpE7R{oXl5_ccLL&6uJ>e{q}ciT*?pRcNVx!gK62s8j8_p&Q@wR; z&C5GsK7H2Y^wA{2d^QXG4tP7txIOO~yP4mk#m<@0JmQ*pHzF^Q?PmTabv56t4zoqx zn|_aOaHFGCkps+yJFTB;(Y=VUZ`wOgKP>l4XTW!Lff>NdRE-TpI$Oy!zdc`9xo01v zWELOHAI4?vljj|exR-#da20yMiu=HI!id7b~ze<}YHE8ylLYp(9h69T2rLg?0cjlkeaT+Cd>XWW`m$ z=eY78)vE{BQxxZ@IGl%Ar(P{h4j}1H^ky~*X~PoG!1GhgE4XO=4tqqCa%LQ3Le^Dk zZ}%xHjW#<&9X4eeZ^dq2S7*Gw{@|DYV+-u10uWf6ZLl zb(jS{IX&Qfw@|lHbfz2Hx4D z8Ie$tuaos5-%7~r%#rEaHkCDFW>=oce|hhzu@~b-LP)=iKl`uMhtWk@_D|F- zCCsug>%}ap?F7g)HNgiDYCQ-URIp^N#$QMI5|Wopud1+p&I^I|{kmNuI*(L!BM`b#)8(x>-vr*1jj5PlpEz-F1bN7) z$GbHpMOwJ3^W~k% zHYk)a`?M(6rK2WJ?CiXhT)2okY!b|64EK##+sNUyTl{ktac?fA#v?wd9aN>aSGKBS zsy2Gez8KcbdBo)`w|u)?mF<L=|M>S2*> zoIf{t<)7l1iG`fb)0YvwZ6w>xJ5?qF?v0-Pj5!^Ph>r)8gj!$g=lRU43E9u z@c~&^k>gtv{;@hn-_eof=SvoAuo=Z`(4p?*828$LRN~Dkm3wesk~7S-y;<%eqY8AF z2zbrqiWs8+Thpb+rFHbOBbaQs2P5X@=-WH4y;y-u0{uXjj_!I@xt0J_t&n1 zJFI9(io1}?n%1E`;B}dinRNgjuu=3rsqc}!?E3sv&HV8;1hsZ=nXG=JQBvEK_pOzI z?qLaF8VaC~E4HkcJ8X)@N#OXSzRbwmv8_^5c#LhTLZ zmgAZDg;kevs^_*;lN{HDG>iIz-5|1RBdvg}MP&E?L$uTJ-<`IrNo0(Pn|{)=vC4%Lr8u^(S~ zqMKUpj!Yg`yJKjvnG0(je^?u<+}Z(uLNXvazQNbDX3)XFmCIjt_>R*b(gy37q!wL`ci0v*JpOFt+2F&j9~)DC zXHEPp5QutaG1Bjj;T+MrL(T^a0ir=@j6Ghf4Zy~g5C6Sw6LmQmqENQ}^Fq#ahbh^a zH~OpN?U5&O^K{R?URm!z1g+@WCz|93w|(^DSf$zBaa-CR(>2I2+!49pZ-zP@ zPeYHLpD`w9ab%r+sgpT3EnKEptB4G8`i<1oNo1r(lqEj#D0!3N2s6|P!N@THo^bOs zwxE&Ado4^uPIyQxxKgBTXjXbfy5rjf^YZ|g&eqSRQ`S=b5#0;XeM41!?5c z0C$>xdjhB9Q9K*WpD=e5n?gPaFK6=&h8p-Xc-hyW^T$In1d*^k2P?7_t|rX0Gj$m| zUX9Azvx{^o{voOU&o3sBqDVHuU8_PxB{YIp9t}=Z%<8_wOnpjFjij!u-E;Yrui+V?~8i%lMe+-DRa)k;z&Uk{(zHHdr2IiBUT z(4Svgran_HaNB1`Ac$y8QlJbYc!)n1S(+uzq?ieNapnM3WAUYOm2rT;DTg%cn#XeY zSUh0GF}g@Y(_D0c#vPufIMo}HO?;7Wui-Y ze5o-Ff0*?ZGN2cHbQ80y8?koa5|X{!p_RB9N_N6!L^VHkkb``4LjRNa_Fc-X{&!L0V;cww+nP%ZGsG~t`_hnN^YLtl^ZKNItX=kI)H-#fVWiV4o#@d z^+)1p*KG(rr8nbR4$dyH${fP-#@8?CVlU>F*iy%J7$-QqX)Z=Km;tcFj9qN^N}XA) z83*lfZw-ZksNk%4AB=Z8Gv4^OzktWjw$H4zc`~Se@C=A@lL#00$x_Cl0>-QQi)w@( zpRI7lT#1Eb!hBbBoT>}@%Jfc6p*Y}xjG@yo+x0l6Zb?b{g17;LsNqDyy|#`U*d0HO zO!$w+Jj0_iioGYnm3l1~N;X5tKEa)~0}e>xv_CteVO-PRQBA>qp83II zi4453TM>(!=;ilDrp5i$WhXvBcTtbwMZ6lzgMcE;cQ>mqt8Y>ipAX&?=XiH+I$)en zX_*O7%^4b^ovB%t4pVS0AR2bmUsZzFtIkOFs}omEZqw>nLsYiU{dXSBEoKV2hqAs} zx_wt*t1Nl^X`K{(6#s!rGPrqbJx6Cj`|M~1xd*}duh0@osyzwSlROb#jiFP@BKg`L zGtJJx(DRRIdN?os;-Fo~PjvGQcf_YZAiVlhAGlS_O3V<1%AJpt!FfsIuQClaaMN0 zF_U(>!a4RONCNo(k^O9pixpCS_W>{JQe;(<#wUsb?%0*go38W1 z9pPjAz`FEd;mTR_WwO^8YM=a8BqAy?2eH(3)iu%UnDu?vvQ^hzl}i}?LUpm60po3# zPRWg(9)Ib~EifzC7H|?$gonuwQJ<_H8m@3Y8tXs`_Eq?=-9zYacldsw^aE2h;1J*3 z9SB{Ox%tn^6FRkOeQXk{WUz|B!X?*h|DL%#d;HbB@PzZehZZfr&?#6I{0V)>VIrf< zw#;MMu`o3vP5kAnnF$}RH>#JcRQ9t{C?>WVw<~;O>azHG(i;J>Gh@kNxHwTQ+wWIG zmObNR)M&KFF_OS`QGE=W?s|pS!_bDO12X%!!sXKlaf#}JyaC3+R`$3!IEo{$fW`ai zjRT0~EMg8^p1U{sUUIS(^i6;JbU~n6!$s&%GktdA-kVOFR57Q6YSB|<{o`6L{r7-T z;Smv;PgcSsg8`1%`5RQDvZJ89^E!P?AD0bOpHmfuS(FWh7=^YY7EF zlQQ;5I)|TX23tpHye$;766HS|_6PVStX}@s#y^}v16~4Hyk)a6t@gz`N)Klp^s+59 z+~B6&3@3$fydU>S!GR(&a0YsT6fUCg3N!>1kqa%gkbc}MDM-#-n-Em8GV$Q@7cfqn{!^Awa)*YWsSAWv-h+2{oMC; zeJ)q>=<_ag&Ps|BfZtqe_VrJ8BTbz%D(lkwdF0AYpdz={u6h} zq>7Qm3c>dq*1p9c&`4_FC-7uc(c@P4TtA^1sxrria&~jGkSEn^0j*LK+vC2Ltln0| zRNE=@iuIQ->xNRX4?;{x9R^GmgwE9YV|b~lz>g8H%bIf5%06TK(25;(KqJ>w)I?=v zIufc{!t^;Tzu9wxsTUN|xB_%;0r<4O8-wNY(ilhkV~q_qjI_?&0j0}tL&~hsU)MQS ze=a~TI@X1_t?t)KB=Rb=(a3wch@Qh1&ejp%dB2>zDM8xVVJV+l8Z3f-iOD8P&AncS zg~1+gUXJW@`HS%^!rtSw|P6mhTG|(1kakO#pok@+ZkRkQVLP~}h{WT#e z`KA8zDP}wsNh0#7GdIC`V=y8KaIyAQzb({hv$#N9`u}7Kyb*8QC49-GwoBRcgYMF0 zlxt4v*R27?HmQ8w4piMYej_0W>*DTH?uu#)tm#zr(AY5PM#NU<=Je^2QNm0; z&OW3}IPPYKB+k?Qc0Sv@AdB)((L%a(BAYfHBM@KtT+6v7rlA8K(}vcTW;0BJg*INM zrFoV}@7UwtY1Eu-=$<~6r7c}eq;ttbjX(^4mEES+_4E5Tj0}nX z`TKyJbuC|lmut!+O(t0U#`PTn6dA@a`9O4&o& zN1yQO2&PTH5+jF9gReA#lXiR7YQ~Q8igAq?Hls*~!R?2^NczVsde(tZ9j^PuZ-EgKDg#FSCPqxppg{67heEs2cXn zDg>f*zSM%8{2xP|x-*C{svB)27z8A_8$4U9$5BS{wtP0`0KW=M8lsYW6v3OiO(E{^zjICBd3&rqhHh(MemP_$Nq18~An7TMa9 zynj*U))`Dks4ppFm%foNS>YmE3)|};;xqGB(^irK$zP_s1&Wj;x->kodxV{-3T?SI zqDhRL(@Ws#^$6jNy(lkW?rp?SM>~{{E}`OD#vYqxz_E;f6ud(kOL_KZ642`b{8 z*riV9KRnF{oYl!|-Y7^X#en9WPs4CfK35X9s_hFC9d35cpERkj zM>Lg)maHj8Q%Xz9=M7gyEt^)8bDK8AR_5iU0iw3_`j=5{8%qe;WFOGB4Y*~+O~4-c zKHV?^QDAVpn|vX-=~@Yg=**@huJ?r=Ta8ZT+4m@_)6ALWu;ASa4-i4konb zS2Wg!>Q~)U)I zR{Ay7l*t7BXHfeKbp#rqPc4wnk#l+Gt-LZ!8#loTD;Nc~~M;soxw6b3fzhvcNs6Iximwr2+1XuEz32v7?nu4U!=< zZn5ynFf zxYD}C7e%(jTu&EO+!PMUx&}lokF?Js-- zYj6gLk|H|WjBxZCc6oq2=8Zq6quxp(G^XPo!x~DoE&oNEg81w4yPw%X|4+ph!4=a& zt?(aY-}eo-Rn}SV=_0&9+ILT0UQidmPa1}y_^ho900|{F@5lYc6_LowxWaamQKJCN zT<~<@{FTNJrfO?o=pB%J56574YG6pyGn}Nwo;qm&e&Ex6XN^Y`#V9eCa|p}>cWV0_>m4U<{}h} zaFk&OdX7fN$f}4w)p{?dsHnW$HAenOYJ3--{qZy~0MB`t6QhA~fDuwBY^#BEcvt|bXnaYyC%(e_^hhGv{dLc zphiOuB6(+cqWIm{2q{@+w}Aj?5ysjXTnnHjY3760;q;A%4=z2M-a7rRGs2L+|C`2xgSasV(uM3Zo#Mwl)z;IecBr+*xgI`?Ta`Q2ifQi5#;J6BQ#)Jr3D%0m z_UH1_p4(#@8zT(((g*1&u4UAcL z@Pw)*MWBSxaQoK8!8(dHFJLe8B%sHIQ5rpkx$2?~4LUxyn#!Dg#qTxfJkUfRvBn3D z5*1AMdUI{)eNB>!?4Lk$gV3sD!9$-(%8)G^HW0mg29 zjB4MMC1~?S8MD3y{T|$0pD169xNaD1|Dg9@Qrq8(RvulbfhP3BastF_>wTc<#W_gM z;X)x$`m+2>m?)m!z=McX5M{8WncgZg?izeD{kJ|fZB$G-BU$<;I<$wRWOoUFDZSL? zywqdXZEtA!U}y(>L?WpjLP(J_P!_$sF;F7Cw%&|>6TLZbbd}SrDN#lA#Y-*9ADAB~ z%xUYFTk8&eIF_|I%(%EA@k%zA$qBCXmdAZDE9r|@nv!9;$VPfbth9u~!LZnI$=!6WKNhD13XL5NDNV_sye zOg>quMGjFP#ug&d>@N;EcxL(4ueSWe5tH?E_=e?gL{NFz4)5&}OA@nY@2iMyz1+h? z)_h$$IMztqmgG)v7r9P1W-w@)pQJP|FSk6973&9v}HD*WcrnHk%-N`N!)mGQkRN-cNl@p3+Pt3k))sb%3(j2=r7?v=>HI#>8{FP z*VD>6U9DK9O~6xXt{-#sZ6nBc=ByUzCOw?Rh!rgK8*MVyp0b_1`9s%D=!X1O1N(&T z3&#wX@Z=@?sfiGiFW&stDNr}P7^`S~;wwCXBfv0D0knoX&rL!fFGfi9iu_iE;4|m& zv(J3!yP0DT?+wdm*Y^5o3im!r%nP5$vfs!__$<4thAsIM~WF+EyJStspz>G!PejumY4ZEX+hjkGQ2>NV^g@vv#G zjV6ms$Y`G1*S{lnI%-r+uHP5__OE>2M3L4}a*X9|Kfuov`4IR}m%AGdjGg|d@^!PH z)`RK~qm>j3FQ#8*$i5z_cu5vwxj)%zj?IBtwc+E&7emsEp^@Ensr0i0Tiu`UC5AG{ z`PN+c@}!zqa*tADw0E`vmAm@ai&yN1yTkFY4)IpvrR&*B%&uWFVfv={2RpVRy0?gG zm^I`PV4TOlyT=qzjr!{6!krf{>neWzTWKBj;4ef43yQ*AQFg!eoX((8nAB=qLtLl* zwx+H<_Mu3w9Ngz=0Sq0~+Irculk5y^;Xfaoya8mO)RP9{Wh81Nm&G}(IfS0{DLZU41L!#Kxf zSexRxnPob?SODM3O|VTt{+%<1AxIyzDc#+Y@_7 zuDvn)_X^;Ap#O@*Rxc&g`-PkM#rPXyufAhC+eplcCu8W+l?xEdF1iIzhg_#{&;0uh z7282!5}r{2l4?ZTkSsTDWl0S$f=U62@kSkv_*J*E+}bd@3Xye|kOa1RMps2F-~`40 zSsWe3Pn}8d-&I6LkN8O%L0_%d|L_W}FTCLLfxqHQl?vAY&{!P7w1Xa=R;OuN%a^es zTB>&0(4=h^Ze}HVg}0!C5ihaui`wQE+*HTuKnI@NPTR+kztkz~>@tdW{skg$4_$ee zbZZ;r=_+H#$;Q6cIo*~zJ<`0fYU58LX>9hQ$vtsi-1$E9VsX0k>u~qwp-$O_&{Nxj z=t@OJ1`e$*^Bk%#!zS{tM_iGJNT7w=*D)5A!3lX`XUYw53WN_sLsm4i*=EED(ATi_ zj5T~7UPA_h{1{YcW2OIDoVSMd=!T_(HU^g zqZm5#r}%S3G%&2`u;5>gxI6Uq^D0N5whH8?D~o6t{s~F zr80TpQPn}W;f3of<<9=x6V+`m=8bJqOFez)9lU@Y4B+sQWvaNRhiEH1!gPftofFEL zqaza~V+GPFOaGCMJB^er{&ZR$uZGeK#S|@yrI~aXKwVfsbhQyIa;1ZA)eo*b&{MDO z!T!ZTEN!pEstgN`x0NLYbR?6-6VM|IZ2ckp;*pt=L6S=b%FTS zzfMk5H6DZ|s!BK=^K5=b6dlRnqgPAvs+!~yoKyO7y1ke`+A}*pmrVAPMFDocGrPwH z68|{$=1yHX8miQ0h1zp@U+nJal03WE{ps~=PQeI;(?klXu%Tb^Yv2^M#1wa$dTp?+ zpWEQ~=Qh^-PfVTFFHgr4RO+a+4@2l37rY@zH|;m7EWZo=RJ;AIgqFsGGwmO{q_-fT zS;yQ0(@M?tF>*`{6Pc-;AJJTnU}aFv+ET=>uk`J6jAvKfY-(F5;vb5w_Lpih{?4Kz z1J?~nEYr@<_P$4)Vi9^v`F*4_wqj$hM@qhX%j%bBoa-Fs1sG>(u7dE~z?nCVHHj?A zzdW=Jne{H`>LMnFq$RCeM*{v8W6k*ey+fQ9-N-t_>+-W8p&aY>% zD?&Ka)+MAw7LpgVr5u~I3DWbmuV{H1Sx=&!Cl=ooV_dzZuWX+^j%-eVNMCmEX!8>}e z9I}k1d(G+0ZRo92)xe@SvP*VF3^ znwHoHfkTsZd1$JL=t>i#c_FozqsvjTUL+FFEA!X-57PA^+I1MOOw5{MeY|b; zN{D>d{ddTz!yX4rm*NcHu=*^yBF90*gZr>`k#k+B1wRzD(Zry0B0RhM2tTyhu*bKI z**RsGD;7&ow6e#@qY5~Q=u#w)KRvlS+(LHIM0jh#T*$k%8}u>S-C{2G$?^?cY$Wl# zkELb4UYB$O@2Z%T;;*rrK70g2UNG*w+z5rJp6wgFmBRy!N4d+dxnDL@@jDZHV-mU) zaMyf{>#g(wj6{BTl@XmjOe%SNIyzExj&Q9*$HqG5#BA<%ohq`Kk1#48s)`N?`F1u} z2o;F2ZH=btGUr%$Fg=FW4V-RGEWX3a0-e*|Y>iM;mKdIiJ+t3wzs^|3rpkPK=|Y4& zB{{W~TYET58pd$bGPEZP*qGLrwyT8WjtG$9qJr>MH2IEs;nR6wgfQTr zwZTWRU|dtS8V!56*Wi}A_`%r+4Hh4P!RO0Ck0Q^b+2JtGWr062KN z%P#c(AO66x6H)NaGJw}f)jr9+$Z&2&9!l)MzUYTDR~v`?O@Vm1*DL$M>p6_z6c8GZWJDJ zDzz2!5Ud|8MJtoB%!^ar1^`C@%^yb4&`sO=K=}rJVIY^jg03|?zYCP5 zy%IW3k9koj-jYsk6e`niF{h#CAa#;5u)BD!<9w8yJaCNS+UI6SoeJ<%NVgBkM zb~pQS1tq0fXi$|_5Pz$7qyo8VwnGbM5a+<6Ipf3P@d&hq)2 zF7+`U@V^>2YlhvdP@A)sPT5`XuP>7iR=8L0iLOs3wJ@MCY3C~DlHiQQ8K}u?6aT@J zQI?t{F}A7HJ7B@uYV<&ceX>%*Q_}w~n_E;JsM_mbUEktsH}-pc6C4UzMOO=V-y)1e zI|lWWuppL^4cfoBp(uzKZ2u$dGR={sQvg2r+ucSdaka(IZWos$dE}RxE>jv@qo3Cw z@s7mLCh3L-kBe8v_eiovg{gz{{z`PNY zG#};kaHllgN#k_E^b^g^m${1X?J6R?UYH{tmeBOr8Q8)iR)jRr&~0|T?dR#sK9|O( zvV_XF@@#Bz5m!})#v^xdLk8vl+6d1$?TT)j8(%ZM3wa_!;;-1>Xi{EHEl%iFFsCdb*H z9nWw_NB1Y&I#%5GbP^oFOAqG3+Gyk@9yY6)4Ozz34df56xtG|cy6tn%4v1{^T54Z` z{8;elfLW4%x%>Ad;!bf(kFu$|7@yHwc<$U~qj#>y^Ch0;2bkBNFfwiYhlZ6RLmkx5 zDtjLb`hd5zvN+!NmMs@P|17i7ep#IT>8UY}(z&ZuTj%%(H*$ARa*Oth*b^hice#7Q zeSXA*&Xt43QKV8)Oz84IhSi=Exz&q3EBA~Eut1Z;hF!*DxVx#dFWqp2IkPT>S{xat zXFj-HE4B@p)U?4^r7ye^B5z=3IS|m)a7^xazBAzHKiV-Z@p#cs;b1}ML$T!;>Z#TH z3{`f9Z#Aa;PgepdZXzNQ^f;eYd>cKWMr^1>4_UlYE}sKGj}&DuRh+D!0xR4sq?t2` zi1y}Y-09lt0=82lIv*Dk&+w33r8=Sq)JA4+M;9w+lO`oTo;-%e5)Jg<=&U>n7K_=+ zzVEU`$*Jfk?342&!`pl2EZ1U)MR2^?aJvjUKz2<8HakqZwkw|t9tqP)r{;zWii*q3 z+#xq9K{n;Fb%TD39@dC){kEzrvm$}N z6dyCDJq&)Fln>_Xqo3-w41DubabPnnRk9GE#R={vep$JWm@!-QR1`{Fi3HjGmaAay zW``2gx8Grmln{&+0#9Pp(Ot&(wo7bd<{d@ zDY4x6B5Supx@O&$B8YCQh+X$@R}9x|huTE9c9EvZo9gF=@N{p;-Se}{_{K_bGiJ-- z_1*+`-6+M4^(bT;Vu>4Ks`Tt0TNtTnxPzQ9+_^B8YzNp6h$Y{P1xW~x?z&oIJkBX^ z)a_C?1jG%r@r}Db`XYHPaoN8kjp!ECm7Ve+!Diw|3Y)J zi>!!(En|7t&pSjGLOW(+<=6}(TXW2&ONnk*^q;x(OX*G1qAGJ7Sj)W=rNCeQUU=uE z3U!$n{2G}Fo;qHp4mr=G4X%EaqeYeR$W^CHH-7$KL0H$p)DzyIaC*{Tj7mjWv#4M8 z3ablyZ$-u~IAgQ^bZfS5*SnWkv-$k6KX>G`oISck@sf@#)tGTJs2x3Eo**USpf zF|jtVBB@0@)V_A$C+`xy-DyPs_Tmg1%rpE-49^GZDV?Y_;u_(ln#XysK3=?v^FmY{ z-XOWA@KwkE!xOJhFZi=bi?gBt|MmS17T7HMX!vp0>YTl!YCqysh{|3n+N`1Lj@T#w zeK}J=%_lveiR(+9M?lKcm~NZ>h*mcsVGy)Yl{*0IF4-u~F`qvKTh7gDRQZOUu3gVL z$L`*5og0?|6aR;IWKfEcFHPK;64|ph=)4J3he!BLIS47vG_`Mx+Auf&LD z8hM$1e)041<@KYl#s{5yj&)iO{z~B}aS*F|dHTWTwq`)>ddOQEY3LcoCu~=f`ds

mun$M3+CYn22>Be#l}`&{uJwPp7BnONXab*S6-jjigf#-e~bH6SYg z5UTyqSPt=3p!T>vW@83)($3XuF2@>4dtr`;`lL0F3lw(3utGYxwAZ8QdSs+$Ng6i) z7`*0kaC#Q76+$MQ^_2K8yHm24WW~pN;CU>0$E87Na>#$DIOD))@6N%qvQr!U`B|Uq z);h1)Kg(^1zu>ziBNCzZxS zlt`I+zCAj}QGxVL9ccYm(p8oJ!YZQ={s*WqN;6_8u0>{epf2Vv2%~3HSFwwGhOsyS zZ;D09h>ope6=nZcSGLyER;T`m3oAI|d%ZwhG8oU49jn$G5k4_8wG;AE=H3cJ667r`F|Ftd6aG;c zfrXorPc%P3zV&6vGB#dY+ovKX9!@4>)g0jda&Mb$b>3^c@dRRyTlS{jn#53z`TCK)zKB)wp1-1j^CztsB@aB1J?Cyek?{~17dC6~W1dc#oN%03}# zu$ZvbQ+q&h{mu2vg6CKbX8-HO|1M$wuRm!&xOScU9*e~9rZyKJ3$Ky7WqMoUvGFdk z0Y3uwy@T&k->6c0kI#9C#o2F}U=9OA(`|~O2ur^Lh}1D=u4v9>RqiSkGdzLzdvmRJ z$-*VHP|x9W!IEsrwNMCJ9kO_)jtMUKDki3fW2&iYh%j(cDA;k7_f2D!PfN2do*Rdw zwQYR)#G+ei77Y5Up!uU5liMAyga6#Cf=N00Cf@u{(fKAdNrFDZnuNjBx-V7X11X7X z6oKl>Ne~SUU$4A>osoXEcWw9ukW946p1fJm%hd!=S+D&YRz&~H$`$*_zrwFd)@WcI z*BK!~*ap={_njhk)BeK?EkstRi)5ykwPl_DPLs<;E!Q{hz$qKACH$!x%O8VO3i!gx za>G-q%{Ukykl`rLPS%Hsft--~)7IMAUX$4-OIFS1Rr&}${HS7vg43)!4GY1-Kks7H zLch-=_j{~yd6q*sV?+Zbz5VLuK-qrr1KADeeEoHpK0qohT*U;ocS?;t>2Zl|EUow{ z1AlFe%iTWpyyQ9-O)_IG1qXG%ut^E(@Hlbl@3sR#>biUGE5i4T-+*`x) zC+$3ieaC{hao_x361@=3)ZlEEcd^d(YGvFm|2ZsHR z{Cb`HYTZ_;fbi@V+i!@1$a}WIU+n3D$bs}}r|PF{cFN6fDaMu0oY>RgE)n}BUC^)l zlZmX8r;<65)m}|8$>52X(a#xZi7Z~4DS%YU9v5W(JJasE+<^ZRr2^eNve5WmdHHKw zMZ$|ls&jOfX9$*6NR%qfgQ|da7XOE5Z^M~e8&Q~hDoUcUt&C=CjY|IIJ zu|RVsXI>pv7k1nU7#wbrl0Frc2_^dsl`(_`+i841MYROp#zhQs8$_B+Y{05zGqYO- z8r}mMlku<0ce2_12Knf7*M8}rf3ch_?I~`M+s50N#NSkqZo?1l%r=8U(~aNp_cda> zB}7UifZkw#@aRf^Ci1+DrTyC1s<=0z@$~%-cD2vI6=wM+rb|xF^{rY$GSKQ={$`s|(o3Gu(9gXQjZ01-_dUPOU232>B4-Jlc zz;_(w1Ve4Rlecj&Q#-9Y+SwF}kLZ05bkoJB@7CufK?W84!K&0%@M2RhcTDjUia*fQs-qN>*L0IT(-~1aZ8gG_fgC$i z8&1`vDep-dZggx*_a<|eM)J87#0fr;U7P=^=i^KBT6ulNLR!`|AAW(N?~T*QQxxp= z*X87I{k>V-v+3}Ht1@Yk`Gdd^=Xcj@J=j6WJ;g*#$T!k*VFQilM$AXGlX04(O6~MG zUA3Ayex?1~_kAGe@At|%(?|mf%BMW|uD$IGi6(Za-jT-t^Ua6CAD_eVI=Jo&2 z4EftCN5c0FFw1$lKE@?+U}X~Gl08gs675u{&$|=TyZm6riy;YJ7-zVsio~gxKXWE5o20_v}g=Sg{@C1F06Fo=2xLw1%Z^M$mIR&-=734%r{a%6+fd!QG zhWGF1MK?~Dvrf>6iUv5!owjFx#{CL+&tD4UIVW^`5S9HBmzYEsP`L+MM>J4zJ0{6v zF3PyLnlyCxCls0Tl&UcPr~>emIoB(?t4ztu^D+9lJY3%Pk_6YWB4{@KoGhWs{H3;H zEqD68aF9Az-na;{sE>8T=!(M&l8Q%or1^^nd0pb%T)TP7d~q`xWE_(8xC*Kti?^t% zz1l1A?@e&HCsQ9~Ft#EyzoZkeA{eo20AbDEh_ZDZNMv>L6WE>?leU+ z7|S^{^6+QzfZ5lRp!7U^N;eG4J^VaivsH@M*)hu&8nJ^;`07}0GfB}!%&k+pgs*=I zFgEEbV!(L-c9bzD^)~EgTYU@Vl|TH#y7ot-+j3^yjgH==qG!47nIgsK-pcSNrq1)d z#2=tWPnB=w)oi!Ox*M7p9-Uv3Nj}YrUZS^@cjb}!tuK}I%oW!^cABUC4PLPiDorM`smBr3PykXb=q0@ll7O! zg@}gxJ%0=xONg;e4Pgp}9zVVH9Htj}a_SPz$jOH&b!o6%`Q`G#rPplAl3olT1K&C! z09&D+1W8a15jj380_=h@(`AKArNQQvKi=cx;{gw+D2(+}9_jeoxY#+mCx}n+19lX4 zvFf&PyQ;8bRq-J50Yc-$A82Bq>Ez`oT;;s7Hvtnfs|JQxW=-=NHj{OvWSHv96`+nA z@#~iQkTmR;%zw1{HwT`lZ(vVLy4so7))b&CL*A~6GvTWr&3NNE6W2TY8F%pHr?*3X z%KOi`E&)wHscKw#pSAblOb`uprShG2dzzk#1OjZ0Gx{|j@5dWvn(cAfIw##TR7q{i zOnNz9-JH5D$DAwEVA!xz@{V@BB<-%fT*w46ukQ%4+TXLIJ??ey0m?RcZUM?sg^kqk z3p)4Cqe#ZzxfqQ{ns#b_y&&U19?TAEPq>SiwpFp22L3v+r=?8zpZ~+#UA&FdPw}Ke zHD%9hiQN>agsi$yWLfLy)!~juWy{PuuD=;hLY)1+6)2e4mddsAY_ene7iLpPvTVNh zqH|bbZVvk5uG`$Q>ilXDTH73tKBi%lAu%VQwq?}oM{UY_LlHp4myy+QkKqn-d}Ue;5whg z*DWDLM~hE)gA4kKxY%_1e9O7KoMRq!9;6E03{Q#JzX{RYNv~(iq!g~xi)(W1W1QC7 zxDy6>_B$3!n(kPxmN{1PcH*7)$Yb+!(**y+TN7Esm7A6M%Z1M*iy~?71RWJ6sN%=rc7Ou{wTj5&e#S^US7H#znp!!W#q2nb*O#DSKBS>FYx2JWw%l}RcG4H zN{64t@OMHV)zqh%QbOk_r|X@FW~(QL4;!RMmh74gn3v(o_(ymodXcxOobY1S`(i z#rTQ^{c31QeXZ-sO2u*Zd{CO7Q)il)-cqT&*x(H<=jw=Gd+}I3utn~jJ{nQPW{1)d zrRpv#CAU?WAMNdp?R3`1W}HoyfdHi zC0pMYhKHLn`uS{Jbp7V#&Cw7kBTCOz-^T&5D@1yiT01p!5V=!R;SO%~7Xm-Zgy*=< z_S{)6!?6keFZ2(n;DqPy}8q^MwqbiJuG7 zBXJLm>9wOer?(1z7;<5c_Se(k!dvH{@t8 zdJ#7cuXO*x#Sj`$K=Al&4detdck+9=G2KWf&(pH#ZY^<}UNx-i?S=sTUx)oOi?z$2 z*x#$q|E-HI-Z|V#`QmDnVYW^Srs89X=mUi>>+IE$3DY-ZaD-g`P~-^&2cJk zYl#AAld;%ei)12*E(3F(F?^2sAtgZXcmg3djo!Kr7+)(#vc9kj0Nl;OSM6PTv19@k4=MF42M=|?}%z{CIah%3HK z#e<>dO>7UX>sy_G9L6rn&(LIrdDX6jV~J_)qDKrLx9KRxB7s0s-&t9BzRFBtGdSA? z_e0usu`x?4)rg|zL&;`~pzfE98OYTA90)noTY7kwfV3Pa`LesU55ndZPinu*$e9zs zFYz%t5OfO0KE5a)!7vC^sEnc!tM|$xU-%17e2?3l0<%;iAd`&@*1ZyX@EitB6w!EC zha@=5apo38xcSOZG_aye_cl6B%2Wb99KPEU@Ls`xPgox5@O)D=o=%IxgKNZpMuS+h zZ0vWsK3fI-s@TK_*|w@Ak8>94(rYPLK5HSl2Fox#AW{8$W;6`9CFy}<)XrUKl8?GP zuQa?hPw*9aD`XN+NjyJ4<7k#zTcRzZ9G{!KbID&D+m^GEYF?-JEE`(!?wnoOX{cp1 z^d{Ja+OnObauzSq7oN<9bEemF>i}MJ-9LTaM7DKDyrh*ob^6|sDC%2%5AH4`F|E50 zD-ph0X}t*bNkQn<9s2Jsli-XGM|r;Q$&vah-vkRRzH1or&!Ippy85rw_SF2*mU-nR zC6l(L_$BSyGdIFNkv5=;;IY)b(&0>MEDq(dSldt_Z^n}A(jUi9r|)rz=z}(Je)^hq z4t>k<{)B(7cae}CWY)2to?TKGeePkUH#PHpPl;&*5<0}63vVKyQk&Pns0n{3P0lYr zPRGL~g6`NPbTpIf$eSkK0S9JPfxOv=i*m_*hCZa{b}v{j@E_dhprM0(Lsk((L-yy? zyXVCQ!P16dNBF(Yv29;8N`PFJ*#f?3;aRy#Zi^b7swXOv=HQ=&&&!}kNn6~YaQ@sCvu~dKq!#L98iRF&iaI^s<2-q-?!3&{foa{ zaA>nzd#K2k?u1@^u7Ph8#)Q3}3p|)d(BgVYOd$tWOuW<|K*qW)Q@pTpI1aw$N?f!?yko|Ut z(n+5BKfEHE-Zf*p9RuL2lw*AE?~H9s^TmZMvOKufnQg0qciBXK^r!D4s&AjKus-W? z)7~Uvh8^$i!0+uOwauAel{HY-=*x{%<>p5uz9Q)pggN(CE2RUbKxn42Ee{${K1*@2l zucXg(*s0-@#5RKcoV4u=#(G$PhqE4xun-A);b(R$c4v-;_l)4{)uWTX;~0aK>Ww^t zXC9-5>cxg2%HSh?l?XQrb}p9dI-xF|F7ty=#s63@%;Y^Xl)yrp?eKZ3R9a>Wl-9yPg-;qceI5vXHVhV!ogMpFfP- zXmP1DzGqXCR3rjB@p>ft_-5U|=7s|p32jCH{}~BQK`Mq@HBi#%r7I>|@T`MQLE*|A z?m^U)p@4K0Xfef+>M|M=U-uyeRELO_cG;<2o1*k=hg7viNO__q``Q?*Q3|tb${0V9 zH1Lblq_bVS0s^U4e$iw6jOMA3+<^tAN$ap?BcIX(cx7Hja(Q{&X8QXc5w2XYTHC@% zzT#!&-rcjY8mcv!L`aYS%b3IUwr&TKvmOt_m6)7O^2f14qf$$eA?cQ<-wL9u_y&FS zc#fT@?R_==$4`fWAt5nsRClE7@K6cJG3~i^yt~2ju9Id__*U zQjWm>3-ilNfiZ0$n;!pGh*|BVtFv}}XxCVSTXd5w*)BXQ?jxsERmm%m!f8H;;0`mvWJOvB;f8Viaid>W)SIW@?WbO` zB?#{3)_){y-r&QysrXE<$8}2F@|(kIbl!q-;Dd$iroWxXZ%b*~v$#vHy!3I^Acvem z*Bann3xOYYJ#7lgqfF&)dGeiq$k8YYNO>*zjd_vtbEYq9Tv$o1dTcu=5SWY^)Um*D z!%U_gv_uW2_YX^bC_4KgQh&fu?|dnp1n7kEZL4gkp-pkv%cY_OSr|l$*CM zv_a%IGqL(^mTUw;2>k}MMCNkP$tS=i78JX_s zX?A?;dPxV`auL4^+?y&I3;!vqoPCvPPO2F{ZuS>sS)w+0kCE5mpgx5*f`^lIFz?#sC*QQ4l%V0m!?5Q%r@BB8A!?C? z2{X9#qgB-?_^f((eof`J$j{w~-TY9>hD0a3ZdNAYC0Rsk7fj|SqD>Qq_&Mi{ybb4u z-NQ_ySskavu3e04@hYhoUH|=N=C$vplIPJK%LBIenI`)t%8VP%`nCsdAxj)BRQR3W z$%s2}?gi=epf*We+JU-2XlOSfpS$#%hy2@TC}T4!WukrSwtjYc!uCf!e4i({Lm$D-Vf8=v}{^8RyIdlSt(rp;7Y20cqnz* z(2zf}J#KD$t{cQEO1?%iBOnmC@hVIIu_n$ zo9?#AWHs4zS^@1rtKxb(+^C$%Abi%+-x?Qss_d1gPdX)VKlXS13`j4hyv6RVy<(B7 zJpTl+Jr3@fOQTh$;56H#B=Lr{ch!>f3`H@YOdm|hXC=^^2J`1`5X90qg z|D)(4?AuM};lF5JaA&zTySmYM(*u|57oA^@-I6>evEw}pN~PQxZ8N1(-7OD+<$k51 z8bACQcXaxd;D*5UpLId+ZlxIZ3e+Vig;YsBS}x1Xl-vZ2_27S~g?EjoLjkM-^IH`^ z*E$W?oXS&$-s&HfI*FD%E^KLg3fdN)QopnA`rrZe(fd+*mv2Ja+rZ|AfP;gWP8e42;*E(9uotw3j;EF4GY79m&wo+`HQ%6rlbv)J-l0zr z5=WK;^dg*Z_rXEZF>2p3S-xQ18W8y9xv^GYx@>PG9aUHS$r>W^9R% zDpp21+6_PDr`~kE&35Zx$I35=v2w&RxL3a}@~`wv#q5ovPBlGz;VrZ>=q{@-KJe^GiNCcNp& zCBN1ZU%J;Z3>=qMYCiS|Ds{>g+V^SVd-7&sFs3=0!FfZxpd)!da5`QMeyUMqYFZe% z=Q%u&yCF2XAWMzfv<|QSv(_LptZ%s*t2Dg{3IC76ElZnt8d*cQwW1#mR^(V%YE8G& z1s$+GF?o1rmlzX$x!qpW5I?EM*>}!eO4NZ*PhoDrUKGM43BK6AmY~%=lb3nAwE`|J zJV#@OIjPL#JAf7ZC&B@^KXveMdM~`dcDLpL`)$wcOLb`0qhmx_jOO(mM2eD!+|?gP zi@!qk1C#PJIE*%4UHn;GBNauzE40XrGe5CX;`S(ZZ(qGpcMMIa$Nf-l?D8-T-=CRO zhabwybVN=J=G9suke37WJXyw@DFVK-0nvxDLk6!iinQ%TXd3IuJUotECGR z<;tF}of%R+!hWctg3QJpD^|FcMj9))g@2{@h2+S(>AR6~@7njC&ziGtB-5HQ7V3-Z zLB+Rv5v|riD$Y`kB*DRi11Qso^V^0#&Qp}G(Vw!*y zN|f>Q)WPTask_~E1T(gjD~xGM5*;@;SPvD(g_Ncz54 zd~Yfes$48RQm6UswWIN1=WMfVM9-M?K4{%`h1So0YU()ZT1 z9PMkAp{tu+klQ2<+_go;KQKv9WN7}+>bbc({@6!5LZ^@w6gL4xd_MYtcfAe9x;HK+Nx<~|03?`<@e`Mg+e#4ZAFAvnfwq|MV0VL1)Iw=hF+F#9Hv z#osX$&p}vaog2@F9*15}zvp;^&$OMYEGkR?RhR%)G*WKh z^L=KJpU+)8`=iXp$1Kc@wj(pzkZ$)7gf(~{qsTTboD0bS24Q{+qm%yBshEClUPcWo%PGwib@>v*W)`+I z6S11*=hBs-Co&(z7jDvwWqA4=LT*;KaZU?VTkdY@&sV1TKbmnj&R##C``zU`9y+FA z-}6lA2qFRVzszf~SVr7)T%tkKJ0_za;bTiVtNZH>72BNd1<_{E?^f4hDQe444N zwEjJvR=5`>N$p=jesOK6m3P~qRVt}VL-eaF5Ob8iyjHUiTXQ)9ZuE#X%`rPI_j>5{ zb}{!d=j+Z8Y>uc-o**+^W=U&4nkcuMmYM4U1}H7+rkQ~`xUzWfoo8pigP~gJ&3Tbtr04Irp34< zn$Co>xUQzkk+N_Y(}~xanYq62b*;(bhWk|IqT5oa(cx;gr0%(tP zui!*or$IMe?)gQ@zf9g{r669+atUnLOL;Qo5zOSCz{%T=D~Pq-zl zD4i_&6XQ2>LZ1Mz-{W%G_!BCozJ6Mcyc8sGBdKLZ!r6<0Yxnd-w{M|O9({Z6(ZQzM zLvWwMm}5bAzFT~f6`$=)hgSh_J0p1&E ze!N~vA;Gq@evx}zhH3JCRpNj}=s)tw3SQkRykl4@&nW$pAuzZhgDXvFwA*Ih-*95& zn>+c$i~F{OK*X-tw>|OY4YZNSSn=sh?&U-r;<8xQ+7Hy`D;D?UR{puZVX87Y7_A+{ z=;!;B5?4_+RgM=sm+0eckvn^ z5!F_7Sz%mV{Z%;-=4w=;DsW_&qr1WeQoqZ{Ssw@z}fi`Y*_&LWBfRWNj!r z;dpw;6jQriBX`W({@@Tw*Ws?#%D|CoGuJLuLPVKlPW-S{Wb zr-s{Xh29{ttL2`9(}#*0pI!3_^c_M2L4_1#^C4l&fK&4xsh_17K$03!gf>!BVIgeM zIffx%i&CU*=#ZeTt%8B?It(>|uIwyw{L#g7rZLshypZAfPu=Eez?CkwD{m@{+*z-& zpFNgXR33bJH&1qC>fqC_H^?xb*_fYKP?QIH7NcwT0clVg;TQmN~kbDqs)cL~Dl zvX-TdmpVjaj-`D(gztvG@YV2-!gr;j!(=A1Lp`z`@OM|vg2{}I9)!}Ki<$tv6w2#Q zQ){ZujhluI0wA;S%HCbk74*`5IZ6g*cv9_G(gz?qp|G zL%=|ae3M2jNuYqx(XpOCexhmUXEuE;k2W$BZf3y{7WODm(;(d?-@EdYnrZe1tNceg zSbmA@Zdk34Dh&YuM_#{AxDLQ_T$a0QTJXB-Wnm(la=IJMkh$}Pzq#c5egv6v zH5<01sg$lY{`GJ+5e;zHWrWRHa0Q7ZyCn7H*b8ylaT~0n1HdK~T^@^cw4dQ4@@sJ> zGMALUb?Of@S1~{N^7X&C9x4~D05ii9G^D$@ptD$* ziJRCk@~!PrG6l_NzAvnF(}@uNA`+9->08m_M``7IAFj4ffq))9FF4+UjooNH9`H}~ z=ZnWRd(mmU!kdQMtmtw|R!`oK-M+dLCizP4k%n!E`HC3k5!EX%l$Ax2)JWm}5FM9t zM$)tB#BPzgN!1{g`s@a#;WI@=&aa_-9DY5mYPBrFKkgn_WR5DctYY@=;6_gU#y-f5 zd>sMB7x&u)i%2sL?&k?aqx$n&VMo{{f)HZ2dPT)&q$6z3tdeCcU(4GQ%JaRVhf;~( zo>HJfq^CH#h#EbVh40WdK99e+PBpXdV%t~~Zx{BFjTONt_u|FN8=!V{Fm+E-U{X2O zXCi_1)B9ALD#aiXPm>7d1ryF+%Isv|ZuCAV)}Z{6?E}fK8up0yE=!WA4U5w3!O$TFo{EPGS^^N#oQFmlDm7L#F@<+mFWg=J}h-gFEjF$g3LmZ;uIIT#nDl>@NF3 zfs3gk!@~OFnnIh%JTU}|>SDM?dV{l1!&71}H&4StONAsg2Wm%G<^9(5m%S8dMKFx6 z9L9kEJ~GFM&eYi1H7mSD^HIit3J@5{ObWO}!>^I9PKAfceD+DDm8UDlQYqk@^%} z8+R@2a5Bw|q4U$mu4tm7$MRL5{kfmN6 z`BU*%gYIJmPx={B5FQV4? z9j}_rq^{_agy}|GhRJ`w+WPUayFse4bF;(Q64gV|IEJl@1d$R46^(#vc=_KHvH>eC zy%WBw6$aA_qGbg>RoQA!wDf3}>75@M?rs%O$NZhZRYaf&b5=lQ$yP1KPd~~$If=P&wmc?lK0bnR?882H zC+fvmboG5yq&MT(!Z0v}5c|u_Qb;e)V`FcwaT(4>@LV0a;n%*@wkS28J{%aXrZuVa z;=b)C1LCw6o(9VhiDtE!)n7@8ls}O;p^i!JY1p&Y6A&zaF7-X7qj6_!rRByGW5Lm^ z1rzT>utVl7AOFkJHJ_jBp-G1=z^2bOQ$3f-8sh&z$>gW4x012@aml7|VrBKcTb~aj z|Ag_zD?X)oE0yV0vCE{t$ZJuR2zrUJ@n_z_lAHadABZE3ynHFIjM`cu2dC#{ES^XOs4IEZ*~wyvW{*eCKVbTG)f1jh9i% z28C97VtG-W@$=8A|Dz~J2s8b@LAj7qGAAM^AhE0W`aqz-ok|so~>`iUgPCd`&ME@s)+W2U_fqM@prR70S8$W>sO&6{LfQ zTww+O=c55e6o>`9z3Lgmo*NErk|nILo}} z?Sk(=CkoE#<3U?5eW(EMl*~bdvf59TylwV^$$`J^Vtcb@3xkg<+&SMPlN3OLtLcU5 zg+*LdGhM#I7CraVY|U8jCk4n`uKHrk)sQ6+oHjujx&n#KR>q_AWQNFT4$GJ7T;>-m z>M57LNo(qd3ZiB$RmK4ijw?9Gw+wu*@znW5@%IF16*=d*9}p8}NTGM0Y!7oRZ+0)S zlZSv9@?;b~Q8V^Ui$EDPJvJ@SQ)u-wzO*T~DhI2xrJJD}klzS>p0D zln9xUyo~EeX6*7t+*5tplD?I6`enB0j*D`3!AQaN{GdLZ4z|8~i491h^Q<8Fc5!o$ z!f%=T1%RhsV)b$zLhW=q#qo7=^6lStYQSrl-O`e6?mL7&JG_)$?Ga#wztQ9F@9EFG zAtJaIQ=Xfx@15{cSVe;}QZcmy>o5hW+uRdcW{6m#SEj@jwWE36xcr)*Ptfg`uIN`q zIc_B7y^j?feuCB6deo-2KkYHcR5;&heglrw3y0ktO{;`skxoU%~1 z;h9lYfEm`tQO6UC3@FL}QOH1*1M@{u!y;$%)M#d!KJH!BtKYts^bQ0wln4EfJ-Ie1 zRt^_{Js&qEi|8T@#~H;`>_6P_em74~)T43P6&V;#A@av(nd~DU`yl|mq&b&xcv07w zv%NHzu${3!ozv7+NqhbzqJHlXKS!pFB;F-c3p`5k^u-a|FG6?C<05OI8qlpg3eC3Q zp8{NR^0py65RUkP3^oQ4vW5&pG(qD92h+^(lrrt)R@z`W+uH`tL`aD#SeHA_Xd6IW zADe3uM)5umW5V*d6YZIwE;T)tM#aZj{q}?uw~?B|Vl;m*zXfj!!O11Zsx&fVxppzb zo+De@(dz!?qJA54Uytdex|(E`!oB~h4QC-ZI^6H@Q^kahiEK0%V;m$10)Q46^}WxB*f`(80B_>YM*DL$|AwTSZ9~V3{}e#pJbZ{Y74i*@9M}Uw z0e)#!5n%(2f-s8izn+tq{OW~T?33wccse(d(z9TBhROmwc9>WUGnw`cOmkHA3QTB1 zRfO>1#Oz@$M)x%F(WDShS}p(l$Zd_oo?%Q3>`+&5#yMbCYru-Z7TEF37XQI{2}Sto z?xx*59sF>ml9JtAx-JnuB{-2p?R-AVEWu~j$YQm8I z*Hsmfxqt4zNAMD%$NC(8o(8y-h&}Xlf%C7{)wmlGjc>5p?&+`@_LE&a>+k7G&T#DTGagf&~J)l0~+8?<~Io%8iWU{44)7< z-KDPygtf~!1N@Phv!q!tYycXBzs5*EybS9gc-EHcoFWJXM5sPd)z40qlEgc{j^hax z6$rzkzJA+@9bR%wkk8gk>-KfMiAs!bxSYkU3XQuPfPGX{-weqv8SNqeDy`IiLW{v3 zPMqjd`3VpF1~>WSx|~?hDT2gjD$GneE8|+^DE}O?=?49}t9*I^p0sfmGSKCwbM%;W zOtbBsZ!t+tqAh7*4Nh8CvDlxR_?XLPSlUIJgRU|BI3g zX7RTE+_1CQTI@c%+0FeFMdjlqXt(#v`$WDZ*Zx+zu^0a zm}6MAF2Z-LEMRtJa8c&W{UK(LfkPDhUPH!c1}o0bG!l`)O^p0b3iA3@8!zYI3hGyaW9r!?z!G=ZSvl>X60 z>#C`R-SlHKs0s@nsq6N-^uDemTUK>3Z&L!)4zksU{j5(mRv!*Ja|nb z9$a}XPI0g6wNzd67U|}C@~-PGm&K$G*i(YhGANq;3NEhGMT7{|@Mkowd!ogd61{(I zSGc>n?0fDXBNy#|1Y0sS)k+)%N%=C{3vj3jU~7@HEkL1GRXtXt^w>U~Mst&K|NVN{ zUNhgwpqAJlMirxFxm|y(7#}vSeNS#xFXl%1s>D@`mgN5^6dcRnH>3>z)mZRk>w&B= z9Ze)8In3})eb02N*d^?oHc#ySM*$s~ZT=0p3cuSa10p| zeNuR0m82OXU7YZyfWIbb36-XKWG0`CXumr_nJRI+84bZ7!?-5%tIe$m*r&6SG<_rKjVf z@G*Nyl%DKbNR%Ixvijg4Kp(>vy`-gE{Qt3gB@6X zUl|PlKu($_SiQE^X}*>^!qgLqXpUca7T7y7>0&0HmXf0kRuHzCt?%f^smm~BJTS;k zsw{LDz6=sE$IwU>;E{0%%H3ronK}a>yfOQN*5|bT`UJk&%Ln@(g*CJj%|g<^>;Hz# z5?5psi2?-I)s@2Vl3$83Kj~wxE!z0Y>b2N#{^}zFy8pS5cArIH^*_1RrI!H!uJEKB z_5#2ZgYlTC_Xs-D^F~Yy6vNQR!5}{7B-a$Oke5hve5HAM_e1J{r}aK10W$5`-367s zsYMJcGU^$GPB@6(nI+he7KF*ns|iw;UD%f{pR3gTjuA1^z7u425oD_C$iits=w~Y6 z!=Ml6V{)3StlnS&{3R zL(bW*tiUL6$;gTwHxJRpGXv8ZhwBZuV$LmHLH+39%XGB#cDB%EzD!&=vL-H68beP4 zkL|H}?aXN^S9?;@jj8hlx}7UP43H~KBjKI8`is^(wx!zQ;v>d!Q5Ap zQTd6=&W>3u-i}UJ!kXWvwYP)|;ADW2+Js}JVwmQZOw5uC(&?H5(_lY^ZByf8%vHJ4 zW+8>0-Y$NLk%6|M0Mj!)O=M!1HZZF7nq})8qpyp)q|u{ zy{=y}7nOq*W7p|m8-6dBLUl9fyAO&QdbY&(C+c#>^E3~S`GV$$y&EUr^rOq0e25Dz zLy5I!&}x-fKL}gA3MTu%Z$|hMN{@Z9o8dAHH(?;$NT`gQnS^wV;_R#s)q{fA#}&^m zLab8#kD4=Uc~^60B&Lv=v9!VW!V^7%hEOW%)ho~hmf^D9_VZ$OQ5Iam+tSj$zp zp`|&QzK@mNY3r@2@pLs$&c!c+dTBK%&vYTfQ{^R4b_vqmNV#7P-B}fc5@Y#ZH(540 zMwL`CKffZkMsj%0Gl;%4Je}l(+YfgqO8J2e@Y)3v**xQ74P1rDLOQ)FZuE94kg@7~}_6|5p?VD%}6!?B>8mk`{r;o;oYiysj!DhYqJbfK72u`|=l=8*qM8c)e+X ztTKRzUP#A)*eK+8HRrZmvTI>Bb!&!HKCYHA^KT6YY$8d99 z1#cDpL|S@dab0U~>*c4QdIe%`V_l-01zXC)=<=o#l=gmXH|?LA*Tb!i$EY5L=u-$A z$)EVzuX}n~<+3h~-{r>l&>2%~#gxjCCXE+hFGfQLJCFA6Rx{W&Agg=2mRN!5gBtq8 zT$14w^I0cz_d&;OhV(PDid9hKdO)-6qa6rosC8-q?P+b?G@Z3?lb~E#rvd-yU!D}BFCGGzb zh@YY1Eb?j|BgL)P7JsRJy^I1Rv@1Ad2fJHHEi`cG>LmZ0@{r`#s)qOh&H5Mh{Co1m zeDKok-b8^k4p-|>u_x1EnN~7=wXyz7X-giv+PYSCcA?#;v$wjPiz462LGPSKlIi3b-BT{ ztmqP|0zZEwE^T{#=PW$W0KyogY4G&=|3e_T^54||ONg?9t*W;Qko_=+C=lEKG$=pN z*;hma&+r0P3#MP9Qgts@saXBy7O}&Majjw>8H!+@GW|Jn!kk?5;NQ!`-StMw@*sEI z0amW#APz*guFn9;lIptfA@nx~9X56wDdz=5UMhuu{Mfme;o~ztK`M%>7FwUMi3n~o z1Y29_`C{XC^Hz3Bv((@Zp3l-}6{hiJTP?Ft%eh9Mai1K8cZyNAlezJ)W`Y0DdrF#+ zLG$EH;pAYfrR+>RnK{$Wj5yS)9772FicNi2^1A)`@k&bT#zj!~TjFO=3vQ02J(5}e zd=AH}(VP*YIvOfM7CM=!aSKaSjlC?6n^9K4+A=lz3`T6w$A|3!(-A#e5Z*WLt_maE zNp&tX?|6DQuo^?j65#(R3Z7u2<4rpG*Nvw~3WH*zZlVqM%13CnZ8fIFP6W;q=J!SB z@nfyg=%R!8HT!!Czm8smwD)QU++u;59_c{0F97JZ1I|0v>*TWTQg!u5aE0nA>vA#b z3L!KQU#e;0Mh(+6Ny>8W7Ox2KbH@m zNuur;O^@Zow(B%T7B7oyp&+8jgF9W3g=my4yc9kp_iGV$w<=cV!R~spEEURXX{wcW zuWfF}8tq?h0`wEvCKNoW7g0yT^*4&|hFEjnZ`6On8&<-Yh)j;6B~=6W%iI^h_Db!m zm*7P4-TB+O&bE&ha$E)v_inc6 zKqE$y(-0YM$>0!3$x@Z^RnSZvw)%mn{pen1B6%IwjWE!WIP)<|iVRCQ=Xv^L79-|? z=KaHmX9}H4Q69PGE7_v9BJVwavsbnDT-na4_*8KQ4+#Z=apPu6PeFvBRRp_VU-;Jt zlP(3Z+dF1&Hat1rf4$F2+}DS+^f0Z1aN3w#&P@&-D0adhHI?k}60RsY}gIjt^<6x&e#5;LBkUzq}4Ym8xp5>@W0ojIlUv0iP=E@S^Q zR#R(lGoCH-V`6ucn?^VBo#5Yf_XEhEZ0=@(ZGYB+eW?*K4lj!0eES{9gd0|svQ!mt z!URXZ844uI>=@3@4S1ZM`REEH-@2LYc#d?lLnXqg;Zt%L8uHzLVDq@$CASg+rGBu8 z#RAL>e&_&6Dmcn!jyT`%NhCc-L++?*@6BFtFR&gN)b0WlClFpB6y~s;#nR1vv*(n# z+KFo@J#?;4i0W2sSHQbE&UbpXCv?R|y4(*RI!T+2`O@jJ%xdqqsV2=qKhde`7BzHv zT-NwphQ!g!hCZrZ3(6@i%ITRP0V^*!-{}-j@Wk$8yq(03Z#x_DufO@k_m{ORlPl~M ztY|jNj`-HfkLA@L8Dtcunh6=MO!M(w@VJS^?Cs=5p}iR}MHlbYOrPb6!_PxO`C@_#JjykHQ17lf z`;0Uslt)fa1m|U?0g&tQ&d~k5-NQJn6f?Me3XwMLf{>UqT8ePK@lKdz8KNsjqb5@L zphwvrbCrB$8z9JlI!0!pt5hTzl`rhcS#CiAO`46h$){H&X6JipHOpu|%+>rlK~4BQ zGx;vk9o{)c8Z4bl;!Y&qaWdD4LqJC&(ot>Ys+$@FwV!_%+uU!8aq2+bYi;7FavTRt*7OwF^lxyd6?i7hkLk6W_p#Ep!+5ab~Q3lKq!r z`r-ADR%TqTSpeQMqw{Y)>#J`4A)Z1!;&|)6|4GHI1T7qKd0-2Ki*$5biMy>SCLPa> zyqSG(eRhcjg$#tH3!gEywNdVG(rt@9Sn4 z^R8|y=Gkt_$w5>(|Dza}o<)WRF)#U+!}YUFPyhDUD%AyeG5s*QANkIe)@M36hTpe~d+H*79cB~nf-dm!Cq=3(Zr6juOZg3Hzoj!k}#AMEppQGQ^WDLfbMJNXt4Nf0e zfLaN1iQ;AUd_a{H2PZYPx_3eQ!j-X%Q z@@D7F+66f8X^P|9q>1;P96WMc5J#9g?ndJ(@-{LWaYfk=IcwM%?ea1w_nRQrJzLJb z&HVD{5t>i*RJzEiYr!8mK(e|XvcgclB6KvG=?_Us+gPe{jVj(*Vj{T!wb<9k`*`j+ z<{7ay-LiyV>+L}-JTb7GRfcGuJIW4t#)EEO_O8h2B*h z)$vxSTYT8ig%tOr*JGF7CG%aDiJ#FITc)+qMZ(BxQ8b(n=x{zLfPSW1%nEYL_+lx= z{P9Y_Y1~{tR_rA1#*4=K7RKbB1?6(jcRMDX>q(_1OAC*4lKu?%MP2{WP7>0`PY@0# zl?Uuz`}3B`6dUhAqK@8>KNZtldtL07fhxC(6{R%mx0h5)osJy+lA7ncSD!fzzePTz zlF_sly}W%H_9#|Aw5duMyE?f~$zxC}32~l2bv3JC|R<$tjCvF)XR!Y24aiK&E%L+_(MdStDzJw z1UsLPl=PnYecWMQhxmqint0xTDyeA|zL1zvGMlK7pslNC@1$cwgCjZ$y8XsB&uS0Z>x*cW&^Qryz(mzjMut-!6By7>jnZ1dY25naReb6<|z{W zZvTi_>y9KB92}vJFeeS7jx#>>6L{q322>^@rNdqb9ZZ%k}jhncJ+`rbz<3*A$&rc)eSSSR($1u6p7FC{#R=# zUlwriu!+uee`L`}GA8z_)<83742t+WaP6&qK5-HC!U!#OG!pA8oGu znTbwFci=lpj|%R?b4B`MaGGMO{WjuB_}GVje--`HwR&d*NcA!&kSLJ-2q5Une#Xkf zw1`iir=va*CFpZ>3i>Gpk4$Pm1QJ`_1b~jA|=oF!{Mov*uBqSzNjHk$8o!)ras7;7xzVN#}pYd-$y0j}g3bF{Fne@Kb#n6QEkX z)*aORo$jFz8H6bqe%>d74sAp%e_Nt?S6>GvwE2iXvdnaHZ`#CV+z)at@r31+3qF{!i5AYz1Ngy*o`Bk#yVuqDC2j;lJmfpB? z{|((vGzlYjwT2|bw2?vNBmX7eMlf0v8l^>u^4)nq)%aPSB*nkXe(#aB?Gcvq&w*pf z2sa!_pLjaA3=hTM!7QgX)u!yWTwjW6Q7c;nwnb~PwPy%sBzqI<>b12SpWkf(2>@<` z&a&XBbf$)$$2r#nafVrY;_hXi%I_|Z21%) zz1OmR9+AcppIrlFex@f^2uv8l-dv`VsmZ<8vX_Y`K~T$SWnce?9hOPelC$Q{&``;z z`vb(#_d6tifgB(}l$L;QpZ<-wt;%RIr;NT&NS+l>Db)J*t$TFwAaMwWEC0^5t)uf? zB5tW_sT(nq0Uq~4Ml~rqMU~!S@84isX$Z#J%x&EBo4a4Jj&09|&Le=_OV;g0#>)a2 z*ls!S{J8hPD~5OYxQkeq8WhH2lijf9At>UxF*4JyUkwMi-Rtq5>x810?-&rr|8x-^ z#`pezQWpQe81Z`mZxMzs16X)RK%O0Ms1wZOXI4@DftmAsM4iE7Wz8Gc;b)&94RN`o zI3Jp`_ewsU>kVxcrOW!ihul^{UD9>Htk7JWB00(J;YsMO(1!N(?fB4ca4g*I)YIA? zs%p;IP*TtzfQ&%6VP>b>!0E_#eRhk#W`v^W4GF^=m!f2+_RL!bQq>!r#U?#`>!>6P zg9#ZI`=d@({+0&xWNjL4)w~s>-M4z9BOesYg92^w9iNXja1r+YlE_iMtDbGe`#Kpu zUj+H-&C!RBCt}3_ckwRQzAXWdH*dS6*5qh9yh*69SrWiTPj7nXSJDI6Vz}NQJ z0=pT3a2%Pn9tXU8w=j+pp+mUUXA?DAE;T!;l-&^`un0C$i-4aB%RXJOJe#p_`A!sBXQn>^e$!I^3-M)61bauOJ5EF_m;wWqk{8!i}TO5 zMw8J!8%txWg}8Bs>z1&0mlc2;&KO6vM}=EJbEp;1YS++ zF(|j=whim~zF`7?$Ap%s@9!?dI=;unVeo7m-t67alE^Z{kH|LN=aH zbOrBPYH@I;$@(tTP+a{C5fYp@J*yq@%|=!(_B6tt0Vflf#6SqeQ<>n8{4y*?yUXQf z-`CXoX=-sC>?XWfb4y)28kfPDrVuG%YITN=ksNqzP|trR9o55h^4K&cj{XTc z|4;O$3bY2-`A$W^0IaZv9BUbbv>j>Wg%M((Y`sXe*SoQp#PbRjaD4xA!o%Cvwj0_H zS0WUxfJ0Q7q2^0%7zR*8%X{NzHXlB5C20DbcS>4espQGR?X~ATLgh+UmLylgvjXxQ zh}t^~vEsc6EDX<8(ASH#5z%bEDcC?%>YXrIi{BNctY>=ehqxcq7y7I9z^!`uhpIf` zA(kj{4JOurt0-D=+_17Kb66_wv~_9WV}g2RDQt?X9xxplFBqrm7)=$kyK2?>o&APz z!Y2?_(_b)H&e8uU?1&NN5|+SlR<-V<9A7?eYpw6Hpc#&jBB%9wX|B62ZidWta*un2 zLdnPKFKLa574FvAw?^L7+J-RZ1Qz)?=FHNs8ipKlC+%=*ZYe8=?%y(%pX)7i(Mob% zGngA|5ZbZID={}xH}a6u%z%z7AN61yfu^@1j-}lS3?YbM$5#-nDUplA69Q?~!ylBp zo;07*yF;QeH>3~d0+%7Nq-S`jHG#=<6~aQuI;$%#E>2#d>+$?bDsq$XKhg9s*UMa0Hqv9@FrvZENJ~UoGpfQaXsXzrn)$-_kgnQ_ zRDV0|SmRnmHrzNzh<4=prnpd5CXzbgqw<4-e@(#)&Me)tP|ehm@A18vb#TKu6REy3 zF2xF$hj}ELP;G6YCEGLY{;4JX>e_KJiZ>r}Vi%PemSe8Qt(yjVZ$V6M&dMsQl{QMh zP?)oVgwZ0PSzKCnu?>>oQxBzoFwHolo17K?74MAC=Qt;^kjCOH9nah9t?oTCMej`P zO%~?Cx>jk@#}4Zn9gwhWDPX!fIGSWJQL7@nGWQ%$pX5#(5Lt1L<}0@2!9M8@0US?~ zZ@nx;EF-Oj@B&}L+x^jegcqhQ2~ZWVZcNu;4pQ)a!nNei(Pv*YmG%-r(1Y(9gi3WTP&3hts3x zUkdA~P>mHvIo@ba8@L1HDN#z^-@wR_Wr2cdxCq!um-`iO_6q|CszPM8D_-u#9 z45Q}5?0qNK!W(AU*hh(hC5-o6SXVG!X{0e!H1liysk*k3NZEAWdXdC+wvZk5DWE`m zwfZZPf(yiHxYsLvRm|+iJ8;ufl;ADPN$#Ro;HG!ld5BuYhh1Kf1xbrERiW@b>w8mW z$x{~HjWyX!k+l95?+qWz`EFpIpy|ndi^_O`U8@T6AcjR+9k-b0j_~x)Ur6NKU~3tb zrn~>*%r`iuz9iAwB*5~pK7K(D7TrJ8O~v{o07V0)+hXt7`%c!jG+-n-v%aVr#traZFgk9MaU?8-)FSy{lD0H%b+&9 z@ZFb|0>w&khZbmYC{D4ov_NrpNsB{pFP0W}iWg0BC%C)2y9aj?G+5q~|C}>>&z`ft zWuBRQ$mCgT-Rr)u>vws6oNyio;0+MswJtzDm7Xl$s=9^QE2kdtDV&ixm`aN2Ld{ZX zJ@AJM_z9JUP{|M2(r7I8xZ}E&hRNZ``rC&u0`B)(>d<^|IPw)vlQ(gIi1)%?=qWqA zV|$~AXjxA63B3%hHeP|djqQsL(b}`Q+POcRT#*;y7-s1FD!+~9&ijS*u=W^MdrtiV zuf0roTl{BsJ&($rWsRfhMqXDOBJfqdcIXxrhQ>a zh7ZtI?Nq7PrXBWt?i0SR!HX8jE~KP3nhjgimC$wlAX^a^D|rD9oeqtTK4%(TCQw^BTA-OtJBgEC>b;cm zZN2CAPao}DOBb36E*z}mFFNb*&h(_I`Soo7s-pgy|J%V;Ts`GBHCgZ8wi6)#C%{(D zz<`^PT-=&l#KJzzAh z@cTxHzW|&|ZW9%327^!|eZ>zO2s)b5JzU8Q1;sP!ACKgRm6Lz0Vy|9m zG~WgO=-QvIJt7u-0%J0aGfPmB zVT9(}NlVE+)uLr{>QC8HRLhSNXhH0#YCW9#O3fl{hmNrgJM=Pp(Ja=|8c7 z3jjf1cqJ&*AXB!ZDS+5W|H-AEAB9WLSgJNT2p`BQRxvZuF6TI68pOP5#Nu{#tsmmw zFo%8piH|1n6l_hLK&ZIw`knZH4=I`#@Wjkf=B^a1|I(KlhX_HH4( zPBFekVkK3tLX7dl{8dzr@FB2w8rW`ipCIFZ#5u%}0uLbyZ7|p>?EN{`9yjq9DLO7j z(#Clljj8$+Ex}!}}?z8g}7m8&m=Pb9`JJX z^5Bq<;zE8dcjCpuxO1kGkU>=v_1d*$EJ5W`G9{5t2u})^&P1uj+>6K3>4sKT+qBq- zt5cz{7sF9R%?q8oz+QmiC^+!F-@6B;9zXDAECF|INx&LpLiXYG0JH;A1oOF+;(8lweONHRp;4D+P9jZ5sk!Q{TbR&ns|nc0pcSgR#Jz@Vl#cnh7nm?EsPNiT=1LBO>Wkn zELH?zMa>pI`*Z3y-$$i)(2Ya_-Se6(iew6HGtIU5l~I&(cdI|EPz-|`Q1WAk_p;0J zJw3RWF&M>wT-)TuTU+sp*idYo&RMPa7B5Wj;q!h>(*AvH42l9ZWQJoAgau)7 zl&BpPfPJ3gdJ1?09B+VL8;PSPGiK~LdByR0%Tu?v8vV)ABGOx%UDoQI{fQAKv3?Ky zUVXf0rm<>ShQBr|X?OpeQ89)=f0Z#=+5p!(c(&+d#3~YVAJJ1*zs(bFC6R?}b$uUY zNv>$+#kbBnU#g4Mr`t)?n(oE?52$g;ZRf3`&BMKHu%BH)<#>Wim=lQ0aqk(6z%?25 zJuod?GFcIM77~VWKhWf0mwjQI&)s^BN$A~JCU~&Bq4aV1Bxvpn)3Yve${t&C9vYp>_Lmr1w2~mczfefg9L0c zQW+p|6dUIq1WV<2J6fytd7>U@MHoI)CI65CI$KguoUW@x50i^275RfQm-!HXrhx`&>zL5C`!`jarOD2V> zgv+v?RAJY)k8nin=^@nD5-Cvr_-eYH{K%tSa^Z~_aLJx&?FZ%G72^QkiYOdQBlh$4 z)(mYq9FWPuc~0WC&xwB=Y83cNXd?)Xi<6+-Lj-wR*=H}knXT9-ggxwQZ#gau~}w>jTY{kOt*JI|ZfECuz2 zW7->``yC`SyWuyf0C?)y7&UHv5r;iMq#Vqvyp(mKI2j{6A0%JrZJ95LZNAPI(3^-d*hPz|B|1fjPH{f*FRuwSw+Yk(Jep(gs59%@V z8flUnfv9l~PaMfs{7|3P)fGD|98_y0{nXpB$`Is!1?~I~V+FK*J^+o7;%-4|WRcCc zN^bfw9me~Btl#k;NsH`x{&_zg1(+*jpGxQMyhUo_$m%s{v?wMS1Dm2{PtDE&OPDvo zNDIRH=m)?f4^n-L7t3ITZh_HZ7B;Fm`j7Ib#Y5l9LZR*5Mz0j(0ssVAS?NK$H7P?2 zXM82$i{EZ9lU!1Wmpd|E-5CESV!^swrJ zG|*W{_`sS{sQe_LDlXOkVO$^Yw(uqk8EKBj-<+VHHuup@h^@fo)`pR36y;yBXH&H!7*H6@v06uFyi0{wq@dpXHErl3=>BxBbaPdR9# zFCTnjQ|@=Gyak%@VNS5je=IDbQ)k|LD(?o~fvq$}5?& z>hB5EU$Jg3?~esJ@$}V(2yi^jFFVKSs+}w6rajWsYNP{-BnxW`sV|ndUx*v-7ANVk z4^~))hr#}MK*{sbRn@ycmsy-G*d1O`2Fj3ZKoyB1PQas_?GBl;qD$P&UKBXkuLijE zQ?`)!9_q+DW=pEA;r4|xsc#eQjQ48_W&t@MdNTmo+O(=?HB5cuW_1iy=g zOMp|n@`|g!Wi-}6-~C&wpwI!yTFCA-v>$@xmWuT$^2LH{KjpWKb3MwIzLnvwR0g44 zW)Gtn_gihc8WgLE;E$dVqDR+)9U#&lwSmF6Vb1|yBU(E=2mX^HM9P%%o)B+6=^E%L zrmtx%Z!1Ujcm3fiiKX3fZo%rHfnRc2aA+l_A9V-_HpQ+&mI7g86G5mKUaCFq9Q9fq zG!~7CW}*<<2$A;zrOf^3sk@`(zpMPi`(vRYBC;T$w zT4+)-IjHZnwcAQE)Hbz?`G)T6QGaeUi_?7`Z^8NtSyRSeAVR*od`Jz0@q+ec@ zwA)8zJM#~(44(sQ)U5^OVefZ8*n(I{@?DL0z|FTUakIIzy z(JgG&s`O|~>_6QocY97KydzX?1QDsqO&o8{$MuQ0`RJ4D3}UbQi7|n3Kc5t_sJ{{` zk&sm`|CwHh{IF2jL2I^r(+jncuToC688}~k62EsCa@+gq5seoMpHcuew=T4H2$Z5L zddXGp7yQH=1kX9c+9_Wv?$ov_XDERzPh?m3mkB&Yci4i1 z7hJzy%00DMM#WX^G082>AjULE7athA!F8FjC-x5(zTOBW6tN@mDu^;II=B{WO%aV* zzLC+gVh&-pr>zv|gyxt%6&T+9drIuE?FdV0C$ED?4q4>L@GiX*_<2zl{CaTrbxl3S zLmQulaxH*ba3TOmT^Gs8t@;hl(B@}V%=4iCZ~81h0_L32drbX`Z_U-99#YdW(6ZP* z;|M?RB_vAUaTK!{E=AgkcOo2=PKb_8k9a$yLdzLmX1 zg{zL!#$IZgd(N>*RJT zc15wTT|yP>sJS4&WNirhABiF^1*M$~9i+wSY%|C24C1!X2dD;yx-k-?Cf9L7`}n!M zB}1|qa(^Z-o6s^|g=k${E=BoSPd1+T(LXr)PigwkHwQkNgq+a>da_7nLqc<{$B9XIpx6N)<)4=(n zRs1jI57#^XePH)9$!uX>FMvKXf60_2LKkQ3c`}0-Uf87UJ^j*0;w6Rd=0-Z3PD(d> z-=$Do)WkSnIt}xg=r}UiN#we4`m(MGpw@4^>qd^!_D}Yq@-D?e$soPmKMy36XPB2z zv|Pr(9$2ZS=-l z(?9ZxPYTm`+FsrGpo$jl8lfgrFyGZPM2TrQMb2hf%JS}cit6G)dbPs^cIdX9}$CkNGT7bXDS_YVXb@KCv4lS&A!etED|5 zJ;(YvUk@z?*TQ&KHQS)DnfWeE;Uq6e0%5c$n+Uv~U2dZOTOIz|L334Gw#|aoRN(uK z!L@eT&s)nVv7l4p{vFJRRdtq2O1y_AI?u81iJF3Q*^vOOKOf#)#;FZCv98sB*OAJV zLj?z?7ueL*Duy9C3=FL>gNE zj?%vJLaWKLSxV)9qIEK9mfWlTSR~})Mw@tEA^YcdN?6`}8Ct4R^PVjpr(B z?#%SCi2GR|sHUoS&y+FQFDk}-%{U&57xtz&MTI!DYcbI($c7;d%PFr;~Ve&LvXUCIoFk{Pq>ZS5pE{n6Vjz>ivqPL)!PwHqA_v>RV zB?qnQ&Hd@RTp@ES!LvaUc0G#EaZ0@hD#SI%5vR%m(W_=G6-yTre*uwnbAj)+`!zwB zGZEaF*7cefXD+7J8&32F8TB(4`BWL+IvMc#?V5KNJQ&=yvE2pX4$d{hW&;|W>?*>m zHUfoHqg979+=EN4q@9OGGe*5LKW#FD%=t91e%5ZZF?&PsNPRUPE1R1b5<43>0CNJa zkDSIww#ymwei-ua_jIGDe)m&e_X$u&k)F=v=2P0yl}Q=f6KZ7=@&L$qUyD_ENP z?$sn|OmvpDwi$7Wa!#*~2uFSzKi{cFnI`y!9T?AKny9#py%w7`Ky`5AcFfk=**IF~ z-NnjxoR0?krEET|#ZwAIXy=?;viOn)ie?zN1(V}m zu;1q~i8A!vyB|DXZR!?!>0O@mfoO;Pzf*0`Y8P?yeBvOB=Xj?>Q3=DXCtX^j+^EfB z|54xctU>nMfV2AP+o7iBpoI4qJVY;pP~`juYcDL9`pnqnno0u2?D_FyYdCT;I}`@m z>zXe&c334vk4@a!KWkf=XG>|hMq}N_TLh=z&_z@r))-UCg70-(aAyw2aoM?Xz9!Js z&)jJv%XvQWXl*ZQsW^Q~;OZiWyJQ*Kqpp>>d1QCZxrjQ*`*&&2>~fhB(|n2+|6JW1 zYRFl6NjY+DQ znevOr+?eJG@~RQn4qwU|3?9n^UD!HKU%4Gtx7X zRUMX5;?B%5x4y-krCFL)Elzwh_2~e?E~RB5uwY$`2FC|5yV8u|t-s1FITc^|_=ivj*1#<;I%yX(6^>C#BSm z?)sek92O=IZYbH;4vT`KNc=!TwflA)>|-99(1HRIv@wiOSbK0q*-uKfIj2E;Dz?Uy zP;A>qhnhTADw0XTgyrKzKLZ@rng$uIZI%p4F3oRg76^(^`5PKJfx~KIT=D; zrANhn&1qM=4fy}c9_t+fxF7rMv;QXlkMTsgHQzK;`1%5PN3+!j#`X_2p+v&3%NpfqeqiCCh->G+L#h>q!RIB&?Y;(o{MlCBB31akNThVK(n?um zK<>d>Y44WjuMD&6Z~7Z*n?+XeQr!m)o9+=+@juVU>T~)rYv{ff^mw1jHr^ zOsJzK{5#8>x{xJ3O4{Z`o+v#WzCMZd;t;nV!ai3*Ny4qR`e zijzLG7J$ZzRg~y#x&%YyeXJYB69W%yUKQKdmP9?wt7r2JWO5{K&z8BDz8qSI`4 z=+Er_t{=pF)-~qy(}TJ>V*eFW+dBmVNC~(``Kf%N%a}VZa8=fV#C{(+4p6w_w87Q& zeBrv@X1A5OSHAckhPZ1gFLWMs2ia4&=sV)mmOzTomx(O|6xYU5+ld-UKf4Ro`W_Ei zBSfDC9E7RHF|n$Zchg>G8S-8FuRlDd)oy9ME@O+V6U8h2l{<-5aznDad%#qF_Lry3 z;cfhq1Jj=$@iJK7ZV62U5DT!_UZU`hm)C$7kAm|PL3Klq(CT&OR!*wuKru_+R7?z6 zxwSF(&FNf&S0$~Q%GvS|4Co{2`3)Q4%-v7mLBxL;9ms;B zGO<-ggl_3RvU;d68?u=vZ*32{v-+Gj-nBbmOSTEH*Y;I-B2 zhcAv+G`-1H?2No4G*PI;AX$8|6)u)*j(=9DJLm|jY+iEN`a3!6%cPIbONL=`>hq25 z&}{4Ccay*8SRN)O)p+JqrY0mFbR1tzP zH+O!kQ`5s}7J3va-gdJHV;!}`v3MP>yQ zw)hxCdcZ0BF(b1m2$FAIdDb0vE8Ro-Rn|ML*v8S`^6cK1o%Wl{2^qFyaiL1kwsWb` zvTB!=STS=R@cQUB|xiGW`$Z z;nmIA`ZxOuXH@cc5`wH4V=t>|= zsCq2elwQ|SU{o=GBMI3ApAaKdVJXpekA_?4kqhn2RW(kBKk$vpTmeslmwE03Fkpf6 zvT>gsg`QFg_D7?I^h~p4o{ric&0U=XHe+jw$%!3%MN520BKe_0OPPsmeXX7euzmO! z#eLQ_Vm#9Xw7M=C5xi$9K2>udqmiccD)dmVOh{RoB3QeTii;eLUu4gd&r6XqQgU8E z59ACK#0k`N6XqmkqH`01-szv@c=lIM`uVS#tZKZQFZ^s>%NGTGQfKLI zg|;QgRl*+X#5jw(w!|e{$Y-Oj$)z1h^ix~woK$QyM~>F_MuoFN^ z!Os0*I-Fe}rDaok7DDajRI&=3rt9yl8STwh4IsX{;%CcB$rM5Y3_7f*vasK8>ejqkNo!k1>3J zEj-R8DM3zJqv;D2Rvgr*mQm;}-9H#ZFKC~p=JtUW{l z9r*T-K!hx)4XD^O`@POsv>mM*`_=`ywO+#u=FVIzO{@PL*3hJuukInmJ_+8;?WmT? z%Cx7Wpoxwm{u9hnM`FbED$wN&-AwwetBe5LR6ap`fpF&Dw2i>?_pOtU$8M1EhNZ}m zKX$6z&FwR+LUCIN7S*P&hZSqzVqUlYag%&9zhYD3DVNA@6k}Pq=mRHc7 z@aSmXv*c6Y{tYK@F+qP`VckSdfC4t)*P~iHd6V|+v*cyjyI)6Qx}_V)$gX2SvA&w* zz<^<#j}=PVxWk2l9+p)N>_{{|4eRy1U8@;F7j_y`{_}l0Eb`aE4EgFLOM+~|NZ^9) zcNF;rW#7h9dLQE}!AP`Cnerx!4UVr=Y+t%GLHy2K+>G>d$7uBBfOOM2@G#|h&k`I( z0$6*}zt9UeD3u#^zn_Emd;LRC!&H1t+(sl&Ofzr4i`zHXeuPeW(?Q+*6{bFCU+teb zZa)#hz^5Yc%K;PCRtg%GlwwSG@#kNiMrgn8Jp3rVhs;V?!Fa>G^$@B7?xJ$ zhKQV6U#vPj`L?!>Pz3J4Id^|j0+HbP3&DEc{ ztH@GLy=&kth3YVK9QzH0`Z%5?g>5<-e@nL`ZfirsL_yjWd7fRJ@3fVU zTjain<0&0>A)jdyZk0dJXc#5Y-&pTH8kTi8e8>|wxBg2xknc`v_@&~2$(~7##p2F& zaoSjR?@&73hkF#{$07N?*H9vTF-Gft4*Uw(BiVa%Cj8uEs~DZ?+FY421_Bb%5~=|s zA*+8p*$?#$+QwRd9MWHZ0Y-cN6?rqU&AXSlE-&jHp1U2m8;gnl`1|~0-v>qe9GezP z=e_TL>eANtAsS_CjAr(lQlI8qKRF0cWycz>%vEFyI zFvrvM2Vtby%_uVILFVW_x!fktHqD||%t*~((4sZTEZQPQ24|PC#W)|%X>8|DoYrv@ z&X@vVM6vZC3b#cf+c{PaNAd=?4DWcR=Tv-a9k9381~IBo2%&AaxXobyEz}rF01iBf zeZVyEpJkwfJ3zL8^v79m{6tre@Dm)s-pm&p4p(2l)dVrS^6iyKDiuyKMy(4YLfR0R zefJwNzN(^4bB~{WoWY)Ns0bx{L*(9gP_trIR^;|{P)WGLz#%4_NV%L1KS)ozK-#dM z0(XaCL0@FQhzD&L_i?S7aqO|>cAr7t-2TZ1>o5K9@V!dq$JO7o1ClitiTCtMLTY7Qc zdAlr?xi!Xd+bgiPViRY?Y&2y0sY$Qq^3ErWwn|PTd0IZo*<{pzb)eqQJdB|La5HH*pd8I!o zhZT|;lfaJG@Ba_%=l{)q1m@eIe%F|O6N4;w_1_%KdfTe@=^&y{^NL)BHcWN(``B+_ z`*+HRcj6v$ZE{F!^9BO)CBByV_7e2|=P*=WH~^)RCssW%EGbwp>n>yE4@tp{+66t)(6^q@z&GL-yPf~ z?N9CH3M=df6CrcEJR+@rY~wrD4iRwH>A-;dPMLuLuK;ancazMSV#Z^&ap=GY-yF>> z5+1v2cG*LL6Gr5_RhK@*$d>lyDzof8eaG3r`kmD=u$td1rW?O4!GQgpYYVjyf@+ww zI2^)UKQLit%ceC)wuOjEf8&7~V~!VyX}^MQmFi8liWxLr9e|R)bATs$M!eF%gBop! z_Qbb%_nc$Q*J^=`(Xzfag~D^jZv(a~HWIbD$hF&~{i{@f-{S!kdMf&wN)~JajnHBL zB!>m#kRxsM6wc)zb1_+dXfgdB!!*&qhGi7Qg2i%QSzmS&(|(*|XyIzb3A|;@!1z$Y z4`M7;eyX0+;|coGw`}LNR7iYHHi1+=shoI~Jnb)?d*lxIn;%xt-Zf>N#ZoMoyyl{o*q@>H zI-nE+Yot6rzT7fJbq=-q*p`&?Bv(|MQBgl43yEkCtKNRew+P>q&5P|%ncYe02iAw0 z-XYu*--z2h#>MkZC#y2p9MYW3cskEGpi6_Aa6=0M12}J;lyG<$L;eA+b9!2 zz!omef{aJ%GjWwkqHTQ%ER`B=)0}4d1kildL49-5BP|K+GnZ+XrDcjxrkdm2QZ(5Z$A_+(XBu1)ILn#niX(P>Ty6W;k$Z& zJE|=vwjLCVWonyARxuZx8DYAX2y-2!@K;e1wR9xT5kRfv^+|FsNjo{mZNu>Gr2nyk zIf)vH;9M1(A<&7*UvfAcskvUFhjpKGkD~qR0S*x91B6UtEa-4}V8*%#3=<7uQg;h^ zEBDM<{rY3u#}Vz#W_-q2d%Z1tCUd}9ETW?H^Zcp1y_g}=-e7}3t(1VYzNz#FtBS~e z)09H1!y}TncZ<#FMyIs3jkl4u# zzPaaChJ+chI7At9QD@}&!is=b&^;+{1lP_F)bFU6W2MMmwNz?`zOPnoN>0;2yI9bx z9!CkqAC}t8GyapR?x(t77<0n~g{El}pxZk_s$8UXCA|4CRc^t$sS^5RW-~=-)OS7ssf=E4w(<@_Q2qU^E3F~$ zojr2s43u0?q88}jO;1)@tT4~9fy|XtoTwVZ&HCI!PL1&}$BN*IiPE+kVmzCh>ei{A z)$G-1@B50d$l&LHpC)|6+$IJl)04Su%Yo8Mf@+S)Njvz)uG1V9$w+&{fAUOJ-YGzO zy=khKuhd1?EU8{?>OizXDy{(AhRVGK;;Uu7k}Vi!Pu6eyTuPnYQ7=z(AoXRy%Ew^eNXtkA8eBs1bRTbLQP$oDl}`=N>hHB z`e7%Wu}3p|@l7+Q3mhJNLI4syJ!Lwl!yKK2bN(p%Qa&VFX31}W;m2nj*EOuJJi341 ztLgF8tdDDl^RN@5VQVAt?WiR|RYxk7ti5n1qXYeFd%3q57mn9zn+p6s{^lMQ7{IMX zWHkGvV{8eqZGH=AC~r8meulZ6?hNf?prHM}bVaWC^1PIJrJ}oUiz-L@!VpVpPBJ#4 z?95@ihWO59=vFJHE(-22wmO~l*7$uiy_`RNcMKWc z9L%`kt@Z_#d)c-ruhi^J$?&(;T!zGC>bE}9z24PqYrDm)P2}uzlbP9MIsn~EZmqB3 z_J|$2|AU|Al+iAwZiOD?Bdo_ z8LexkEcc(f92kz?+xPADRtm-W!x|uHi+L4$QB2iq@hAn?Q)5m-i(I}W!>hM`E?g%U zDGc2~vl{Xr;(kejR7)GnhqOt}p+)$1^?l%?qL|h%Q5>=A5sE}(MNj$RfO<7Zf_2gU zJikk$pd5bDQ$Yw|`Fxz&^ z5;XRItSExrXP_4TMHlxrJ>)XX;U5KXM*1fBOVM!Qj%cx2 z%TGoSgCEGzJiZApyM%Y0O<#_6zUWKQYU$G%O;he?{nfcybIl`HM`qC?^abB??V`@D z1h3aeR(d%R7NcS#b5%wpdfR7nqQROPA6fV&dbW$5rMly@+P^r71uDn-$EKpROMoy) zZ<=Y7*T}c_{FIBKvG9aPZ*9P>czhx3FZau1E4?_vj&=$X5n1lt|q=9~k&H7EyR3 z8f^@N)6e|w$Ew^%-Fqi5Y(Y=VN(@aMFKJB9(DjZJ2yE?{DSJlcL(>Xa*z_I!WV&g`*D*AgZ(&Zx5i2Q-+InKT@ z(x`{sVKUe9Co+b5YjMVZhB61$!f5fxuz(`7?I0?5M~Aa7f1asL@80Rw1aTI3y|5^) zLao9pxgeIj6Sttg(IYkOS_8(hx&!TK+laC{RSlWhRxZq+I*RZ8iaS;qsH8m(75r4D zP~^K`h(my;`%-zKMsQ?QvkjYHL@c~`bHUAB`mm7c9wvv>9-)-Wd-;XdV6xD3zs}Zc}SgrjQdH`?{{cW;n(4DWKqr;iJ-QSc0 z9gQP^+}Kheu)~@*ULGH+bA2VLOnM*Ej)oLqSpA})gL8;1Nbn!F<&a<=h-qlsP*#zp z?FUc!8%yRfjA+M(`+jhxJ@jR~k+H|C)j5ckgHRytEpQzR9pAXKVFMH@*V*7F-&lOG z?(SjFn6FB_((t{o>)!_&!IOHk+`L^zm?(M>NN?5wU^7T+6zl9=zF~>WUB zi|_@{e5KAkw?@w_*sj8>;x}kZ8CRcyUh?yw(@qnR!?w^C^KuG$Ix z?exvgdp4UDJ{2}4+JKB$8}i9%M^dCW`6YMRFY1HRsJReCN~kcAh$=tkoU~<*o_D#g zw{#(77(;Tie+YyS7qL^2G{%8YYq3UhP{>pMBLI!zlV((Mg!WJ;4EUk;G(&v(7dH>D{_C?~f~Pw%4nE!uGD z6DrApm)a&OcyDG-6}?TDOOLXHCu+^l6xsGRz3>MHW5JB9mza;7WB02pC`=hb`HkK* zx2f00jh+waW>qkGq?X|m-AoR`I1Gz0onxQAO8u0n zfs#8M-3?`{c?icL+uow3&ob-I_xn~h&xCs`W9dd4roz;1jUWT1va6xUGT1%Q#Xrdol9ke!C!V-c{5Be?%gYq zg)iIU1i^KbT?1i)0NnCiN#W|RI2VPGWyt1G&>ebLwr`zuZWsxRogi0~>NFW4h|M>` z&#J4Cj5qL~2fWOF(a^(b&CG1GL?(ByQ~f`WOh~zaL~mGW75*~eT=p4kNszhSR}1>n z@144q`8+D1Ey}a#@2QHT$jjJ(QCP8%>9WF8d3XiLW!hJyVe!@T)7VE&^4> zd*mdIv|+jJA5(}EBb>&OCAdl+;P z?iy4iGovGSiR~<1PT+2j6RND67mDRBV7Kapssbx&LDGVpf?p}Vnb z=e<;Ee)0#&JOb(g%pE#i%`HNFUHH?*=bw(z+Z>%vVDw+kS0iB|mYQj+>b9}xXXLjS zXQM;eoHz2kc;|P9ZeACBM4O`Y29)?N#-q+l2=Sp%=(!nZfxj%;-K{WH)~dZ}h+pJ# zQ=js&bGbrd@InCTU$?J&4>?ilz<>1dfzd)=>m4uL2qSE~>0#V>>wFs1cP0Azrp}Pe zn%}@fRxIHQI_{2?Ypbz&v`;a0Q=RlS}s!@cQ3tMMmy zeR40lBM6^&6n8B8(^L8Pn>_P-H)I*HvzjogdJ`@ZJ3{7WHRp5*qAK%wmBv%f%c^L} z9T+!eo9Wp50g(QI?b$<57F$ZU|Jk8NdhL|f>fN+p%}`U`j?Z-WEu12LC^hj~T}7N; zC%DOA(rn#muy8c780W0cLZTvp6yNIS5a#@!+3&UArjz%3`Fp7xVwg|UdS9<9Ca2Z} z1~|_L*pz@ad6q{?S42ZP1^-k{(3glmr1$K-8}eF_q|FB|(Wtr1xbm;BgF*>T6tjo< zudy5QTIb*Y>Js(a{{2P+n}bJDzRjC%+ooJ%kJ6GPA%1bI;e>Toa4Dyu-qKpW$KK@G zbvA!K7R!tbx1#23`x1+5DU+-}f@)1=MhV1hlxycn=QFJ|&!-@4NVz1`5b85NReBjh zKJlVi&dsq6GF~8CdnYwiWxD)VMPSK3UMoqV!`TYS% z?TD8@c&T*j#2|xX!Q&>`a&2&6;wA}`{PA>t#Ow|#@E?ZPpRJdo%sA`mN*B*N^!?wd zIu?Sv-l1rhGrN@y`{Td;_GaYa>_e}`cH5NhQHy54`(h_s<=ACo5fonLW;D;`=H<$x zSSv*b!PVXAZm?tA*UK?;?q{((j&aT{yc3d~tbG8uwx7U&6ehy62SWD9Ph#WG-=o6E1duuXUfC^W#YC_jxlW+o^2!hzB91$~dxkbx&9R!*M<=Fyr0_h0GfL0qg z^yW9Bq8OnFLl@`KiAUb?Wt3`bT_C|rBR<7H2-$Vh$|1E^ug-06fXf>LC=O%`JRJt^ z*&uv;IWK|Z2&4VU>OnzD1w6$g<9ZD6?X2^4pSYyVEo;j66Q~i+)zS5!=&(! z?(aX_)0dTUCtffIN4<#`^m3xx1f!>9P$cG-Y!%cttxO7c4y||F)9=Oo;T-lg#^}w{ zhRiq{yUpyxj6dn4>fAN0GN&p$rd)FFDw2#ZlD#W#ar4=QPsEebQ{g}4z~;uvexKMv z4p+t8!Iqwl_h0S*MwR{FKB4htX~^y$fZEtTp-Tl@zUTaLe&@Q*f4lb2uD!Rt_j*3>`+nR$XOPRWS0c3KjyIodCJ@gkpr6ZkQ~VP; zs0A4vzRkTxGh;vGVaaGezx7Tdoh)-SIR1gY>MM0cTkE5!Avq@;_N-O84xI4oEWyz7 zsQ_nn5jHrh1l%os5)^Ur#XL736g1Nfj}YZOW9Lj(j~x7Y6$TZ<#2&Gt5gSs2 zC-ek$OhI}#`sBCQ>YGM4MWX_T}(?)#LZH;d6VTk%}|B0|i*+z0%<* z19I$QED?5e2cz$P{Ru&pLPTk+jv8liAk@7W$U^Jz3>usHD;Fa52NyYqi!;eGL1tHs zr034K7o8#e&B%laNo}=ew8g+GPK5eX7bih8Z*8a7mwF$PWu50*? zE>HVq>N~UIAY)afjR6FKHTHK)7PM>(o!2kD^dh*!oBR1R)V3_ZJ`m&HFPF1GD_=5$ z_zrk0wFvpW+8i4nbaFe?saNqI&p@)U7L!zL#OhJ|y(N}gD5B>Dsk zPdt;q3RyS8iDgCCLNBe|mFbmE^H+}fmEY+LON1Kq$r>s;@?GDQeKX%lZKQQ(X zu8ir$zgTpg!Ga`h|->(e2fvyPooY-)FzjFB_z2~N? zGKppZHKx~p(ggmLOT1`u-N_V9-FVeim)bDLW9!(^e4#9g3V~}J@h!At6YGg(YJ4LY zw%+G$=zUGFWTCeYL$*;S>m~K8)_V?Q>N{1}`)`}U8_3Q`W#f;o1t!bs@ppS^>Tmfy zFm=4m+L5;ZCb@_7fEfR#RWP%ck@TmInOq*wC_-yVm_M?8qH1yh&Y6gtT=`rUtopPp zK5i`BO|NPOUaQS1SJVUlKhFYK_M8Hac2Wr^))fQMm`UiTt_U#YWi0><`WE8bJ`LH zaqRd|cXIJp*F$j67aU}*Qv)@ZB7C#fTe4BmBt>Mb@ln+ulBH0HB-fmZg^Hgz(yFd3 zA@=w<=TfvFUc4~ebilUK*W=RGNJ;iy!*N}8?-WAeOT`0JamI|!`JnX~M%O=bVo^QB zYumR>WTKiWbaMuvOuIyLF50`KO92q8Vp%1^g5Gj#UP~Ho8{8_%K|bera${5Soo6jB3LkwRcGu^=_&wgy!PishPlNidxmXytt%yTLzDZH+ds0 ztjQH2)1kU--Yp@2IOSb}qZ2IFZaxn1Btn6tvdrZ|lM@ zHT%p)ET?udRsEaAY9~@B=k^<&q4T*3`Dw@DfugPbU4u?|b@5`wZi*?6K#6m4!D&Jfx^Y8cKRonX zyi>o{O#m?7j*3)f0s{Q4qK?ef!{Z6xtjkApE^LNFU%eA^4i-P?kC^>?cK?F6rcYMN zV~?Q7rG=1t^b8QC9lqALxX{=VI}o5~-ZOi;)u5ZHPX5=5Xf_TRQub^~{;4gbeIlKg z=Q}F8Cn&Jf>cFjYN0v{s*5yZQfvVLNe$5vrk`)blKzP@TlR)`W+pABJ3kU90FBnrk zGDpF~Q(>1a1>euCkPrgPV2?tV#7v|_X{02^9Lkm@yV!xvEV^uRu2g1)iL7^UIGRD< zMo9Obx9-Cm0Y^C~1TvxzbRUiVP;9>|vwMwaz4O++I=!#Kncc=}M^T?1eTLi5>^YQ` z^E!uJtf9oEcSEjw^nAM1z4Ehpx$|<5Aj{G-XAMt1my6dgF2uc<}?eqQ-i%Lb7yx2%C2<_sX908 zWc8waPIOviHJrE{>ICgmKapn0x0g#24Nauq8qs0^rbY=dZ22oyJk`tvZlcZ=-P~(( z2(9B76RpVWx0fg!#4D5L+JpxYoVb+V3LuV-zb7gH_Wa4w-3h(C-)m5iW)x7cgHYb= zuDvpyvBns?XH3}4W~y&dZ=$v+sWCg zw3R-J(iJZfS7j}n9h@B(_;qZKFQAE}r=-PyzCA|qjFDVui;wa~al8_E8QUeBz3Nu) zzMOgPy6xo;koE!X+INm`irw(u0GZU-J+uwb)V(|!0~5#> z58GQmXQPt1em?QaB_lrGep@O3N*d>bvDIT12drbh)Z%!fuF1hpOQl;gih`f;zVoi3 z0xv-S#iqiE@%_*e|MfcWB_YuQ4%yd{ad2Qz8w}GiBEfe zIR$ zHy#lmKzzE-6MGq8+sr4{ndIbJbb0b2GRS+QR#L*h2Ov3qESSk}s7tG8;ekNd&n&Vy z`14=gtg?LDZE9b#UZ?-e$i(dICsABM@hZu|2=#VysqW;Ao6~WqKd`hYu7~KMv#IP+ z`~6`k_=p|j3dBjECpXsVW6QLwh-vF0rO8_N#dQ4OTbI>fY7l=Y*#-BxHqxaM+3iHP zt=`WlShs37^Vw_5arrR3+utVLaJ758ZSpaLbX?g5LT>WfWEn2OZ?fGeMgiM0oBQ#F zcK#XFJ5}k^x$(DB%k_tA#kC0IA6=H%|G!2x`G09tV@`mDkUT?%Gy;jLRhq8{QZyA! zk^}Um?4+39W{%2Way97uG@PfIvv|rQhN|Z zdkyW0ebn64`VqkL?1;@0hJF92D1tr=8q++3?&G}=|J0-S_EI;&vE@wBJf$8gp71!E z#z*S5cvrbLrK=TIQvN~CWD}ElaJ}95wfi%O+lHAdVvS!1w;TT?P~&GX3(nrJh~hk? zlUM&_vBil)$ zCX+et#VPj&!Fq16&ywmC+RdTT(6=e&AvW|nuSo{Q&}ZV4gxhGFbzq;HYhI7FVxBLh zw|g1CJfh{e8GB_%Vx-pCy`dO1NS|1Cgtwb`n!3{>64q}_jvSdTU2F?G zIZ4BwCcBR#jWXBKMjWw~p|yk*P&&CY2St^eTf^za%+x;0>&BGg6}9vq#qa7~shS|w z>;Izo`jjH}VA!!1ows&1s>H!gjyj|G?rzgcI*v`}e20wfvkYz_{b6#UMx)A;D?f;J z>AMNVp$`eT{3Vt}8P5MVzWq-Ir2I39zqdP*r?rD=br_GS6IZ05O*GTupX zbdKr_D;o+F_+!TEpQkgXet5>mL-53zp&RZ&K@UU81uXT3!GqY$ULEkf=2enYs5llv z%vAwb50d*MsR?=$&>;O}eppyXY-%U-*kT8s=JH+GTggsp`^S+5haOiZ%?Ke}J>Hj0 zW)pYEgD%pCnk4S7FHv$D5KL~{%r3Alm+`i&WzVAmM^`_>q&ul|i2PH3yE$>6fc zhxePr95uF3ja70>5tP~{N18C+@-FpUAq zRN3mX!XlTj-y?T?seV?R%jvW_*V6q7>OM-eaEKfu#tMLMCFau*&)&O)T4FE|N|lEG zNjJ)k^JTJIzO)%k@)z>^ zxljCd0bx{(6`GNfLr;=d<(bp9jrkkOB(zbm^?G$&w8FQxg20M#_ok?^vgL(+&PdLd zJU`a00_5!nxok|@{EF%{(|Givb*H6-q~Do`+VxZfb9i%*MK6)&?V$xLLY2cEUtai} zQ$&CVpOEwV=^Dsv&YMB)U;b(W!3qVTa)W^$V6=*SOZUPfLC%+ol8kqwY~an2>F7lg z&279i;RPlP{TSXl;j{DWu9e+N_m;I?J5OaS;`mZQ;pEP2hjn&#Pq~1qQfQcAUYgog zf>4}{QZj@6;7Xd=OE!A|%_Y;NkqrIeA12D6>uf_z*JV@>rsdhheOs08$^sD`QO8qi z8xphWPlKI4?Y*KVBZ1F=@(7>4ih0#4%_#C|lQq5IgLuZVuUcQ4(Zqe@_3(vx^9I}&}xlq ziz#u|RB)$CoClJ_M`*g%RoA;X;jYzCkcu}2+7m?vlzprK4gcMb)o+cmx4e<3w#bw0 zun2+IL&gM1ln|`v{uZAY7w+_x;rL14htRFv6>*c4JU_@_;S0{Fnk17KCJUZq!A#7wb{UYlEYefx~4X@ zR;IQ&!6()J#m3f~5>|X`T?YfLleGN)gtfo#zP1ec6~@r)eMUD4y69xc286=HZy!lt zR{H%{BI9trl9J+Ra`}U=gy9*a;68IA&DA3_(Z97~@~pY?$;Ht_Bu87yRL&<%6 zigv$P!zb6Sio3*NROAJ+wK)I)_HjGgSY_~d*>5zT7<#ez05IG2rpe9ugB^oIp}5M> z>fHt6S$DYelc24C$!{PL_-1RTJB;ld|18oC!y%5x>eY-_?{1CRYr+_PXeg*_12wGX z_eviIuTbLLHvnI9mvZ?&dSwRq6goHR;2$IgkNks`hHEFn-$K4X=vCwaam{(+HY3W8 zv^}#L;{0InJ!?FYTQ#9JCNx`u5%VNjWf3xMP z$+OB7TQ|~&U_#;VAI}5~tTrkRFvPaKY+I==@2#}#A5F7T%yr@|aj;>nMkU(x5FI2G zp9-(@nh}eL1)}oeNbKYe`CH~Ds8^jdYDpoD7)$uaXNP0JSo9P!k{dneteQW_Ma7HW zy2>zq`Q{gt>&`c`TJ>5t@rvrgZP&i}muzCmoE?YThbe;1p)SUii93_2MR5w7Ysolh z3O3UfZq=f(efPJk%0>0_i9h!U9>k*jhli?Z0Mu)X@5y%+nw)ODnJdp~pV9L18Qh~j zd_nf_(qH5!DtY*e{`0c6K$;N)GQn*cfB&OUdD2MIz6ZfP{?X~Q@xLR#aAq=)y=AtD zL`zWXJbUagx0NzNy3Fx>K=zVcTln{v`pgyhCe(i5#F&^&Fu_`~ltSVpRxC(TIRb-c zP$}*sy^}v#tweDWf}Qgb-*pwPkn7QLd%***iiN?MESpiDskrJotL4QSwx1Mn3tHka z{owTM&CvP$BXh&&0=c_2>oc|TED5^2I=z>NvbHlwY%TX* zFn}zvuGMhXej_QM)l%txSsi)Rm4?Yq>+)0l`j6s$I&N+=16;Pkr&-6{1H1y8M{a@F zA48|XpL65BkZwC+T4v?coVy-PPGp}W$KH}deWHYe^Wq#x7R#&GSnWd>G{bKQA4zZs zC?e1bBlWg&zD3j>+}y0p7MBt8lk| zmOhlZR+Jsj4Ih6cR%mqT>Ed)0>hY;iINOeMQoEzj1^f+Ln{xE#c609I-DXlo^#blB{h#)b1v1SPX#~X(;M9M%U#XZb;;> zH^;`I^bv=P)j{V1JXO9f@2YiY({&e0{R>N79C&`S4Z4G#k;6z^W$7MgBfQ(s2U(!g zu_83AFKWh;eNTGitKQ>zz{OnX>`nc;Y6?eGV&Kb1C z^|#>rhspY&YpxCzVy%=Cr`O%WzZYqhiuwb!k~~{c=!+6#8FBpwOJloYqwGI{J#$;v zy-a?ALmeAB3zDs-zEws!;+OeELd#JD>6lneOja+1wI=?DC&1O|(Tzu6!(?LV^A!xA z;b%^vhkN8b{$HFshI(VJzm|GHqDuHf2Q3!qQP-4BYEC&blC<;;#Spxv^WG1J^dzn()YNQ%Fs|^%k2t)=G+ov;1<6K*ihXE_g1UX zEaw^k}D!!1c(0I^ABSq`5BzDA?o|0oy;lElIqxceP&%wvK(2AFV>S3onU zm&3chs+VwY+%@giMtWfKM)kF3nj`TvBN#!4_^IOodJ4-k4H6HX9Fimn<6=!FFK*|~ zZP_U)FE(jU9Tl52ilo7E23NU2`!sns>=u=z@r z`Eg_D7rZSfo+owlOzqgNgfeYpudM(bfE6O z`b(l*n%&aFxzu&#V()e>)KS8hU0?^ujkE})QR61C5Q_;W=pB^HhTSfw>q4%47;Wv1 zwBIR$4>c~a(g!EWGaIW^BncdR&9yIzeI4??Bt|trJ&c#3NjT^B*^f|LB^Q61r#zZ> z91&e|3^*~PBgFcc|6H#c&rIOKn346bKroIr`; z6k$g(hm_G}_GZKG5vQImG0*}W20OgMXura_Y%s*%391dX?d9p|_jXlnjfiuC_?$cl z@ut7F_eUNL?n5LLD&cxJqAb>h`&7*?yd$i{u{m*!)sNorYcVQRXqwqlD2Jb!%30wa zJ^*k;-heUP`$1Zny!^Fajs1112@Vn{y?IBI;{TQL`9IHrrQz%kZG4fw>w{VGPNdcL z&40(+7Q^zxkpfSp^psN!9?zn z<97;T@n5Xh_toW)dEBdQ!7#`*l5%LkbG3&UhWA0@5qE@`-s;E->K?Oi*9jQ5H%>cv zjs)92-Lj~HXxL_pO$+laD>o+OUrg`5(&n!>yhY*n>SaQGBh}GZcu*JJcomTGLYu%W z29P4NJ->r@;IT)4)Zly9;pTNI|FlQLP7(;m;=~_dfz3wXI%CeQ@hJoPL6tdU?aw-i zCCB#PFQIqQb3MKv$bU^81{)_x$vt>ukVFvgf#r84yw`Lgv@X2jKR|X|IM;%blmo~;6z}A& z+=~%?Be~VAT(t%Te=N9p#k;g+v|Uk^uCRu@Ke6L)O1#hOv`!*)JEsM+ugE3qG9UGt zmdA%-*w>o3NSMlLP{w|tcOnCOs7CLK3K{Faw#xc@E?f5*{nD#dS5Vi<9rpsy37h>|_)O%b_^9c5Iy+hZe+EBV- znfIHRNnXaP$$11;l2|PT_b`f88mL`2;H6{k>*DCpH&DOxYJ~FYOWV`eJUQvX+%mG< ztnwE&LzxHtQ4g=3nY_eQYiCw#po9x&+yj_YzWk**%*i*zVvZcqTj@nhLJl$Hw&&Bm z4~4;da&nPwdy8Jq`n-j z@3ZPnuLqg@;fWGIE61*Tf{~5bXf)qpBf4tH=OTq#d93%3_1y7`}c4P9$+fl2}p>zJa^cN-CQ?e@*pgCluwZ?~?lE-B0OMOV_b( zu?PzxH|y7STm-`^&K{%Ml%+lTw;{U$lljiX1!%>V%4dbA+|@S^>{C!N%RjD0e>a}c zQ#;w4t0}~ep1*@I_IP-oRsHO~sJeA<7BChbm~}kS3rPCXzEYxPTvHRO!p+TDsjVSj zbf)zMy@L%PCI><|2%d^$7vqR=Kv1Qw>QZ{t58K9)*IKJl%kxLi^V5N3heh{e!ktR} z0E{9waW-&4Zc!=@nWvE9EzGyO5;>)kO*-DYUU|~A@d+qpoQ9n!=gm^B(8Vi04XWRP zpkLalE$ZVI@EQy5Mg=mH*eCZXqvv5+9{J$5o1jkF&4Pi>mt6{F{_DUK4iOje+4uem zbCpgR9zlh-WqN~x>p$HWy)^O|nF-+<;)#(7x5&8j=w&D49GNrfsC&9o*wlAo-w~`* z-dbJOHAFoN=OU=ryF<_xi?`YD)-HeZ{V=fcFn59Mbcusfa`A<$Rb2dpE@u@#xg*78 z2kM2ltfqkYBkj>G#bGEgM{}?Hzk+X$z_j((kEJukO3=nHR(Re$Su`Ut5?(fw4afu* zEJIuu?_X#Wom78|jLPHH-c4J5hIxgse#OAlbu!V>8Te?Lb4KUT1LF_ZxMb7XJWJ`R zS=33S-~Wg0oa!%c^}Z*16*d+Gx<}lc`jIGNn|oRh?)5q@#^fKDfI){lt%Ez3r7;E} zuWu&@0y=#=l5 zRi-9585*EshIzOzvi?P*F*ESRwa5ibT-H+KR{$q^cR{T799*<(+U}?SZyJXn-A19a z%+QeD+aSr%CO({=n&7g2wXH1e8I`a=K`I&pmgA;0G!dODFbPBXP#$scM% z6ILDPUw&F!7ERfRM#8bGBO*gfo|)4eksIR%q33`k*@B%P;KO!upUs*rq#^J|Gxh#f*DLBNMA#9n;wWFZz?in+KPB-&u3h{cf- z<-1(~x245>&cN$}t&HV4_2V`VzPi}*)PAf@SSvOzeQH(9C0BWGTuId!U@-wwgc&v?h927Hb|_uyR<_?&y!6od zS=$j@7cW6u+=`o62U73mx)N9^t&>Mv(w)MJv@30i`QEfgw2tb*2(^&_=4=MifWQ{?z^Q@|qEjp##*=7D`Oy#hJIVzpw} zoBB&-`opifR({4scgCVAqbICmK!t~5E~F~!yVVWCYN@aRsm&kvM|$er9Q)@lz#a#;NiV9 zV*wZIwnvVZbV7PH)^%vM? zA?dr~(ytO!?z)mgZSegu-F<{y3OP{G2qUwfAq6n(;Ds*Q>8_ztf-oi_DrWsyJZf@bxlV@x_5;9W zxJsrL9vAEB?M#Ck&*rTol_vrh-81?N+SE(KFjPID=Z8BEYXmhyjp(~oK*)*3{Jl^tv8r^lsrHg;-s9U%Q$ASAjGEz zntLsQINVyt^F(j9=`aCY&$6h`>twNx&4nwgubN=)7B3S-u2(B)=Qa7>w@_iLS?*-0 z&P#8XTYDlu-SRZ%L&Cc!WBgw)my;IO$%Sq$pLuMI9d$BIlRyc8e-~#@lLs3=s)i?A zr7w`}#sAA={Np{~zp4LQ*|N(BY##u(@kf$dzN7)&WMwOcBo8nJs}>3*jDuNL$DE!9 zDKe2e#mZu0g{Wra35J^mTHwmN=EVkTe}Y`;Le-?u5bDatlSKYRm8pDYfPI z)2bzkY*VT_BL~+Zly;HwbLHsTfnv5Ii6WX4hG$XYvGJ$npSChi0-zso1DQTMF<3)M zG17}W{*eu>W8OIa%OOl=?xNO>p|n+N+!72|L1d688^cr2SC3wCf@4>B!kpc5?__yh z>!szyO&M*^1gDR==L4|uk#K>OPv^r&J5pnrT7---+eDO6_*Gz3P0NEeCUQ%mR#Zc9 zKPV^i7G~hf2J|x@y7o~J0;kr$n&qWhRqwEeO$Lw!yZxoS%_?2B5)kQ5)A$ zv3_s;CYWb8XELPXv<^fX{pQr1`wWt>>RmUW+Id`xd$mIwDhSoMus&zSXveDn@Ztp; zJ+LIQI3D?{)V_*S@1MxJv>()5{`{Nch1xZj9CGsjr=@}WbTwDqGUt<%h3XARQlw{v zEkPBRB{Fv(PW8k&83M97>@4Uciti!oO6S_M_?9`UV@4sP4KV|<7)u%IC z7oF@gveJYP?~pC&9OmMTnGQ|m=HiBP!D>P+#4?h?{)#AR8F*KpuIW;_xP>B&{}DR- zUkLO&*lm?zkB>=>)g5y0nBSAfquW^Flyvw9(e!CwHm&(o9y3!P8mXytjI|)29+6>^ zd_tp-S<$bz+P6R&lX2%$}C3VkZ~D7@j`Xy@Yzk$>jpZ4;P958qUDk81~ch8V%Od zZzW-Z)$Aja6(j73S(qV;FOKl)e~tslUE_HiJ!wTfNI%TS;hQ&Lf0HW~U6HHC7+8EEvE+u>vn z910-=??X5fn+c38kcQP>L_Du@OTb2s+>ydiVNl<29_3^3I${?72J8x^S-^R&vG*SF z4roYpc71vKx>G}o>)+h(x2#)_+88@0^J{l&ea8xJBY}e9@Nd-z_C}ak)4b31I=Cb<-k$44f1@G9_z86N$#n|@UNtF{3e+g+g&^fhnM1UTHK{y-xPXRuLvD~E9T(L{ z;#fC~DcdBAO|kopJVTkZm)}#0Ep|?NeUXaTF!WqEnWJXY2X8zt6q@pS!03S-ZK;e& zO+oP6I-NLQiUVcsO9brB#COBb-)!k?dmGKKE{y2l+#S$^FQ>ccJ(!n6watM|3z{m? zq;akqjgZkiLoH>;&avcs$MP4iV2y^#yn@itsfQm}%agJiJa z{SoDP&k$!mPq)k5c?7(hOS+gdk&sj{+GH6-AjnTNwfqYGo@bG$dl%n$Ge(O;t&b9C zL0LhX1UEwBBNPXAwoi#w$yr(jnOb+N+>adWmEI-CX!h?!Gb5>7lKZFW%Qvw#p$Pf6 zBJam1OccB_%Xu~|SG*aF8>15qB%1a|m8lZv&W`YmeDe{86Ci=|BNti=#o!-|r8x%O z?)Qo7ezEFcn@xx8k3*py89o+p)?xH7Yl3ve{4!Q zdU6paFXB915}N1#!k2ICl#E@j{|Z=vR-jB@-0G}GFa3k6DK*u$gL7t#JXxd;qc;Pr z($vSx6p-)U^-{B^Fy9aQ7X|Y)$=nA+ujvjKep_N`~eD}b`eGqS7-Gawe=jQ4(finAAvzpxqEbu?dU z8R1<7OU>6Owljp|*I9Wj$@OJxkp|-1L3VA0Nqo^vRqw@uQtC7#Yv^jMbl&q`2#WmK znya!XiYDD(k7URDv!@U8ap0nZ^P;Go}XpC?l!7*h0`JEzqlPC&GC4~q8w z)h`J08nH5}_f!x4bH))pV1A1%Jeyc!~K`vbwhD1J+xxDjghFWUwar^=V`_eFxk2 zc$D6nwlfxrhjDMPI?BD|$>-d9>-VC*I2~5%ZBzY-{)*%EN@sqHMOC7h7w99XwVPoexn_j$;QuZZ1POt=y^kay zYnQ$4J6^ULPyq!Y<|2FDOifxolyH)W0G+eZSSEtr5fGEhc4<#G)sA zHJ6pGH{C_{i)HQ-LB#y72cDdKJx6TAqB$87{KJYbAG6McX7wR6+f@Q=-xoc8a*uBq zKC(1;^VW9r{$)A=(ek--gf*~}EULY1)jix2`~9guyaaf+to<(W$Ex!nhYOGAKp$$l zq{M+I=YKK$WTtm!BBM~En|GQY`LI0RH_C3MJ|`TUiNPnwZ`yXKeg=|>d}rj4nTP^x+sHFqXhc8!JIroOjPRAokARlohQafao@6;=;h^in5! zX8*ka|Fp9;d=JfDnhH|B!C$JUS9ZAX!#S)&-cAd>`^52xE({#!GhT;B`B$=cQAK&! zp7U@f0QfYz(3f#XP_Imcxw>oO%`;`i4f7xgL&VF*T+`Q|rV5*;3~V>`raVY{eQsUC zY2zVb&wBHZsY}CIO!nsfNG+8YQrjkH36qNC1ac!bvO zV~BJ2aBf9!)p%4bvsnq$0{p@PB(|1n<@=7E)3hB&j|YX~ zRnq#>bIWxwgB5~=V)7W!fm`fe5&xf!9<%Qn;1fZrbgXh8wj$nc;~cH%aL+EWem6ez z>dQNEomvjWQ>)@pmD}hLEDUFYk(|Q%<8E&(>Mw))+rp;hmA#qHb-f*6P(`bGX8lV<8$3tFv7V?YDAYUj@q5?f*2)I4 zLtGwqoS1U4x?r^46lW?lZnLKhLpGtzA$3J^oS>#De5Ol)v)DDIP0 z(?{|7DYIYN&FzrTYuBUJM{hF{202*2?F@f;?VlOD7M}Q3Hi1}1OuArT3FSjk_rN)K z*Ea?(FV)0zgp8m@)){}0Rd>jz0O~y_fHPe0t%|Mu6 zAger$4XTG^?X>(qk5)fO1kaJ(4}|M2aEFs?WR)Wavp(3($K%l2I?-&S9C!GmIcLp1 zh!u$u_>&*)%oM_>AR1t;D5PC<0BBO|;fv;@0(b&r3)yf%T=RSW%WjwKnZCikf-R}g zgr8wtxEzWn2)-n+EoG^x&}f~B`Cn_Xq5m`P|GypqvRA*LgoqU&vC?1HsN;MBQtXyU z&C0P>w+ty*@hj%=h2q^5bMYmWoqols1c?D zjrHBO+_AZ}Y4synwsiMl7D$1# z&mDc$Ru6qDIvy)#K0B!X&B^?-EB26uEf^V8+m-R=hq(SNC)fvS&1CsopGem!%2-v% zos?Rl>VxsZVYcB+vJkyynu4nRB^n0xIV(pO6SW@V~RxY0*>z9 z1Ou$I65t-I@c`Z$HK|A++=H6Xl~rwXJMm}aM54FS-yIS4DrgIzG3Uh zSOm)8^s%GF1~sZhvM@{6B|{LNRtc$bKh>p+X?EdG9Rys`#)w!68RDm$-W)mP#*dd& z_LmmPiB1`(wH`vyhVTy{HQaObNxzy1F3C%7%ypghP_d^!_C%s6QMYlFbkLfStW0aM z+GX{0yEC7KM@d&Uq3K&yORO-*qWKTsuhop7?EGb49{Vy;Pk1$6I)dQQVg21e8BLSa zwhjW_1^l8iG|$aUOh;vMK-zw8L1n}iH-}xuz>auOz}OZ}z~KgJWX$kC3cIkPu4%6a zvP+hI-q~g_*;=uYOSz{PsD|T!IXIfpE9^xtwV7gN<#=Dey?o?GOW5=OBPpzVbkqwhM2k* z+cTdfk2J%y)-Xu8Y4B#|!_Isfzw)Jlto2=4B zsvF(fx3K3-;IiQey4e!k!s}Aq=X}QEeeF(iEwaPb)W)x2KSi5<((t5cAHvsRgEx(& z!jGW#K~m{Q!;H(Q5Z2eTkKk8hC5M zb9Cq6XSqdjmZ`ubwLP6YHOnu8-uA2^0Vy3bV|?yPRT6Fm$KJ;S+(YL8V^)32c5>~| z3uO7#++T%vCeLg>wX{KQjvobuT-%Z6wxAaUZEKsc-?Y-^3kR<0Ued!>dHmV zJO4T7p7hId2F2{QskVG6nRm;i(Dp7{?DxJ)Ng?P)K{BgjzJF$a7?_kI?V-!G#tGv@ z>3JLcqBsJ6;sBcHvUcS(YEAeZ9-S;|&V}K6JR4<j!P$ORuN|dCzpK6a=u|}sK}ifn=^kw z`wxFyX7`(zJM#7Zn|qNsag|pa$~WLjqERCWPB&S>QTH%XG2;-PH4b%wINzQ6KXnXR zn3E$TyfAsf127O=(Em}G;hNXn>q>t8ZN9_r5)qo6mdaH5kTD>JA*r^Yq&9S}+Q?Fz zEIl!|(J*(ez6jy_iReXq(O&24gOimMW;t#2G)T#9qhYG-Pp(|_$aRyS1MG$5P(6Qf z{tm1;eBP!Cgx%rM%7;ky{rN>5r1Pb_yDt7VPge>IFP+oM(I3EG)#XXH1#93Mls(A# zJJD`3TPMEwz`n!kw`O8wYbEN$LgM{I16bm0==M0ZHKCFCC6aQ(6A%Z!cif>_vf|bf z4owj1YEt}~O~B>qh8Zk}ijRfKn_wqg&E^{2mWdfEitBJXLJ$s88w%}Fs>{x8DOWLP zm$6~=^1j?53$WN<+iuFFuRspi+j4@${n1Yk%1D#cz0d ztS-k{M!#+0D^zR0zn)^oMBC&;aRvGrc^}3MmAMx!G8#Y99WMGKAK*1`BiJUKHpW23 z01bJ@tAJK$^ySFyZwGEUt49(T zjoyu(w1cmmCE;K#MlT9k()}Rl#LoBzV$TNkW`k?UC%`l$^Yfo4D${>DICsAadby*% zDl`8x`|V$A@748?+%NIib^LUJD0cUW3Mpfi@AGEnMpjWbv;g3aXNW_t_WtP*LSu@O zfp=}A60o|ljEg$A0`&aa{y)0jJE*BI`WMB5C{jdv|02ChuM!pM0@6DX=^!8-q(tdG z0#XGcy%Tze0HH{i-g}dtP-1`(-}&9SGxxrk_x@orVRCZL&faV9wbrN9cqPEPK;&$w zoY-|Jv8m{?8CGE=f2=$_$q;IP56#sPX*JBykXNH^%v4XTXks-A`c9;pCk{gp&FjLz*3;E*7L%>^*w2s&2vG$ZuK9+PKN z(PxQE0w?)Q-tgbWt0qkbR;A6#;~q}hfPJ&IRp_X8^GAs(4!evNtCmVly`7abiEieF zx&?}%=AoIlJF;hTbNUi0;&E8ayTXY}4{ z^pFxuevu-^!&)wu1H!{`%m2q#H|FF#^(4Y1Sfu0IPdi?pG+V`=C`L ztE4X~{37V$FjcbPNA0tPCi)NLr_EHXv2!1NWGY0yaKq_JUAp!X4Kak)Ll6h%dwOV4 z_icdU1e+A?dDMuyT*^1reRJ}z_~HwjQVesIZlw}2t}lZCPaTn}h}WkIVpz#de9p8DeF|L!{y z^W6J4{r~Dbu9zt9r#T@1>)m2$XV~ujM*w(4X)&r#-)iqg>Zh)>Tb0EAXDHs1$cTzwpASfZ1ot4yk zoouq{Nt_OiUVd&ONqHYuU6dc(2S^mXJa9JbQnM{FZRZe&a`Jr>PZD+`_x z?~u(BMy^G&(B5WOoCHG9o+kB_^CHd$O&%I@B=5=FHH;_$N@5mjExME2FLP}GgM2&L zZW;K)C;8+_{)b28E`#R84FV*kRvc5aXIFm$s6Y9QV5GBFvlw*L6x$jr_J#iuSXYXY zdV7;U!e%br5Sz$%B|jG=`RExI3`p+y1Ie@^+8SAe)Wk}yo6I^}@DwlELBDf;R(|2X zQ$8?OGSRhu$fKqZz`5V1P|P+eBCnXS!ETrwlYgpyV>t^>C>|ict4PnWojL9tX2;Wj zHF%-Df3U_9_DlQo58sUR@2(uy)E6?Q4SJ(}-Lj$}<9`IU)5=(SM;9_fGyg&|#+tRZ zD+GqL#jaV>51ednY7?9ob##M!a3%}Z90y79YKV9 zIT?8G&YbI!pm6(&YRAa$aSp5TVP0E8HT-dKRUKb*U_x4LHhctjc`m<4<|sLy0a`E5 zJJrX&C?4l*Bd=Lg)(Gb$xarI?S_2MGT=_JmHA(pNy+1zAjMgQ_J-}Q?m5*Hs zN+L4ws>QzSvwii@?5N%V;`38RtOow+DLFvz&)lf!FLiv;lFaHkqT6!oy!~lvr;=XN zTefPl4n&HuheBJSN2C?lxpkv~apD81&qBE#Zh}QMy&m!tKVNa!8R`4kzRW5el3E>? zzJ}o+Ev-Xov5}j5z2l4ay`2orC`{yLy+gg<$-8oS56$HGZVzhe2l%*!KEMTPGGF7d z8AEZQenlsc)g=yUd$qBapOG-H@B=9ts&50TQk{C^?joTq9m%2L*Y7cCFtQxbw3Y&$<@;%iN(6xeVduk0~3ShG?b7|Xv2 zy8q{h_FaqWb`$ADK{)a&0Osfm_HtltM1;x{-UwLYM=kkKwllDJ@gFkco=#SVAv;Ta zoZP1m_5@S*u%6%-QAvOsV&zQ2^*e9gv#PjThTBMa!c90(Y^no?i?h-ow=K*$(n2Wz zZfZoX#^A9MmrRiYOP}XDRMbVZYxYK0^BwB!c6sycLA`|DO-nSB7JE*|eY~#m)~Fm8 zmllJ_olGuh;Kz>6l!}yz;b|P|wiW-_uYA)8Y3TOoWo!IuyeIRusrBFFhuubRE~U9+ zuFNoBZsF~eH!8tnt&ncP$6cB23i2TVbWhn`p``7N+X6XerK?i!tBCK7kAelG|8jG> zMYD`PJXexC3Le7IqH@aDwL?3JPo;-5xi2@6L7|%S} z$+@IiytX{-E>DvjQrGRm@gw&s+sX>uV@;5e;2rUc`%>zr5X8u@_o8g>%5Hsl!@TjJ2$eyZNL2_|YUbS_VEl&oDK%0MYp zD0n7N+g>tx147}%>hk-D+fJCoZ;2xou{)1_*CFL1xQb97ZLf)M2CyfapTFhU>b^Vi zod`aT{$QlgQ&EJkh|6(!k% zpArVv7u>LZFT$PlT?^dej69Stkz%*U6^^OQE50R(P#= zWyS^Oh8ku^^9xZnyilr7^TQ3{_3z;3=jQMP z)j3O;x7g5%$ID31(#0;p4i+&=f0#MzWc!F4s^J77Y7>kO9)UfW(#MKy1c7^XsaiUw zTnevNSLmQC;I2G)jOEw zwU~VTL4O?zF7T3J`GfnGSMr-56M$g=zAGkB8Y_h=8(&BCzmPb|tbNTReln8=oF5((>4z!vd*fHHWQj_UaB`|{=A$#~+H8!n)+Bns)F-sIh6dbAz# z+a7-h6Csh}2}}a}+jPwEPN4K$c6Sf1(TVZ!<^*(_DUjd`GwL|u0UojzKQj1%5l@Y2 zo*eG|_SLx_(iOKnJq77DLf9IG@dwJyng6=mdL?Om?{IHoDC~T3We^a$)5B=Lxe$STWM0N~@C+@frQ=?PC2344s#Sv`Iv)+=H)IgRR{9QcSAt*!bg$$L` zU|OfGEGvb6zssH3f@a_r8iPmGnvNhO62&jb0O(2aSz^hKGH5A1;Rw!+qaMcuCqD$F zdcEzSzXu(0bq3tPM_K|O#P`l3h$Xl)9#FMoN};{3dA}e_DQ$J4hj`){l;rX3CL~O1 zQZr6O3aBZJ+e*ZKhSGbw1u*52{2#C8Fu)rj z&_GV?1j@Rv^DYYXMc51U1Y5EAO5%9xH99DB)ixcL*yJYnNx|}JoEp1f%4xmpH0{kf z))SL|=b(>HHtUH8Y4BMfJN6%e@Dcik2q%Er3hR1S>*5Uslt$rrjFKPUH3mN-{vN!5T#N#yN@Z0 zS&Sp0i-+q5bH@Q2q#oozZ!RSZ!TP!<-;A z3E@hf03kzs1TFF-@sB4Z9@%59Q9Wb$bG=#dZLxNAb^OWdywz9miVBs>M0)CuJB$?# zNkG_=M**x%@@`1v^7@ zN{f5Cx%Emv_E(Lgu>gzl7SW75I13F3FB8&@aUU^}C+dzIYGrFy1YWt_$l?eA*NXME z7q5?31V?(456?0$VfP%b$&rkYV?hzu??`l|7xNj*>shK@<#a7RM=K>@litxArpC_PdwDRk=L^2mNokDDBn?0g2IRLB zc_>jO_=o}sW6sI&9d<%vyXv|j$O^B;vE&*Ie{ut$PR5x9?CQDMb5#wR*;cO z!iiaJzlqT7zOG*CHo6f}hwg$efBK8j>BNAt%KP|g-z{!VSa3`0ydg~%rn$@d@%FPDzU1XIB%!Zh~Ee7N4K^!GDaK#l#!@ z-Yb-BvWM#3YFM9lxJ5+zH~`W&}%HCxpUy;jhDLSo}P>PN4sU14o46tg|$s;##J zxE1LbZWuG?>K7|&H8*HR{*5CCPHNhvl=-EX_Bcwdryz&5C}$c=_KjXbU;;ZpS!WTZ z!j+scJ|Eu$)V9w_8nhCB0ux-A^+Zi}NsQndx+)!Y1N#=O9DxVPHi`5a--+FIYce<( zUk%JQXX|HY)V_6hlh8PoX7V%`Oc_XJ-NAboaMQf0isCTQhoOo}zTIm!(rrj^{?^uf z)q*R#Y#3)_l)2WCws24{EnUPK&{qmaZqP>pW$rri(m zA1r>n`;GZa3PwV`jLhugoA90C0+)SlVq#o}wvNTOl8o`Phso}s6yqccCR>#DhL&d? zr$u($ng3_zS|FulCt{gFYPhupcV{tqRgrKULnOTo+hX1*=vf!<>ojzZh-Eh%mKJ<6 zNqd$!0r5==`1-D6$@O4iOvF48-O{k|>1_?K@-OmZgWj6jTK=TYh(diMzH4I@p02Xz z+{}cw5spZIY3cRNHeOBo7mq1kJ?ppVzF0T<>1Q{yJ|RKfZ!%rYeC-97V>a;csQPp9 z9J)HawPReAu=1DC{-yd~mgx}bzt*5^Z{^}vTdu6Af*64<3F6*`#h)`}<)ut%^HINc z8q1##I4PFMl0sX)T#6U!(#%i1s_n`ex%d3zXWd>J^Af6j9WT-E3^tVy2`VMU38?Rd z4yez;UXvkuB>!pz$P(Tzyk(l@`WbngR3uGAf4BYDm@oyukIKhn3{O5rxIZT~eSF7a z_4n4cZFplEvxor~CGXj=ZE!1llZ1P^9)GZAFc}-WMg})Nu^ZIbR8MR zOo>CIJ5BqF{|G##6)y8i@4czePnAj3;QfWELUio_)yHD5uMhWiVw3#*jrCbi6BE5^ z`#dHPg!5Ufm4>O0euPu&7gJO97`3r!Dwsb-UXBzVLh)Yxcf$;?AyI*vY z^q!%IDhtys--L|gXqLwJOnNE=DBso!!ieI6lz1A05Q5r7xj@cx`~o#-aq9)DKrI;oPXS>~SQ1sDCE){rb)7WlB_w}KB;owV-jRLq6{ zM868gk;(O?`(aFohDaJKHR)sijn5`1!BL*M_STqWY%%;-1Pr$G3dm2}+7BjAvyo_ZjU? ziXKHIio55owXw(SRlRQ}^W`0%Y+uw3$?DKLXxdS-kFZ+0C}H5fxaFS+n;1By9uad} zf=JxU(q<+>cu8PGEb$zDH z3`|^pvm{@;a8ZImslNCjtWs<-_$1Aqx$m8`?^TMCw6rv}etC}>z4!!0Lo-M;m%Uh> zFnbI#(=>W)VLAC?uuf8Zm@%3`b-{h0kT%oncW#$_fDuun<>Y`i`%X(VMkB=6MIoDS znMUut8&}>i9UrG_y`+^kI-EoTHe%t97*dwZtA~tWnce3T% z;C#HFQ7}*$-viC?zc%<&!8Nc9O0kx$77wvosmk#9WdJ-{s;2Dj6C>BH3%J-4GH1Xk zbf+ch+IGQi2sV_uE zobYN74`SdlGf;)S&&3Lg4^B1Og_ho(AL}nEwQFz4TpJZ@Q)u!txn@O>3jMiT5r3s$ zUTjglIMhofLk({%q6p@7x7lnFs)L{+7OqrIn z3|qKkqYHT6E;da9fhSLCu%f2G@__*5MHQc4l*P)AvF{Zz#|5i20*3>WFq-&JkCqXf zUbl9S96SSfB}M96D(8=M4NFH0G-XeCR8JF)NM5f%=U>G9BbYbhfp|r-%*Z;>9u=lY z|E+>nPH7mbBgba>UJ#O zuc06j)3QWoWxHHa$g}t1%w|LhN-8YLJ5MQmwlP#G`i)PExkjlbxxIhs4K#?|NIDEM zsSuS^sAK?@mdXZEUXH4(`aAQXDTjdtwRVQ#*AvE@2WrHO(C04$*{AeLzIB-)bNgZdc%1mCEZ(~@w`& z8Mz(dRP#|tyDgsmi+=(lS*jDk4}Dvb@$OD`;NxH!h0b-p703JvFA{S=JCtYg0&(%-qjxfSl)N<|!tnrKRe`TT!TMh^4RF1H-qfS#n6iJu7V6;U)9H zNDz8+P_;Dd>N4lAYt8P~;4$sZaWaOrdOp1|OlV`=fwru4cf5t&7Cvt}%2TW-AFHmU z8KPMo?-(59n4?zrwrh}K3rFg?Osa|QjODuahIQ|+)>&>YaxVAY)izy^Uop zRqT@eV=np7EYoGCraj)pog>>lYYvh2JE^p0?}H=Uz8qu(vAsETJ`JnWaPqz5&4;Ml zHmVqKX|KC0JNMhZ$!mSi8n?fxTC$rS&bn*8NZCyM<;`jX`bn(nm4hBte?DVW+2~!G z13s71+7@UzRu8%QAB7U!arQdST{`ip->iX=W!MAKQE$hHc#-1!rp`0D3?LUG62)&kzy;^Ue1Oc(kyElf1309*&fQHLXDappB4&j>gr zSYRQG#Mk)%pjGU~*pF3jnjL$&H4HfHG!aAZMCYjGB{#25419N$hELR)+iB{N^8vzO zX)3ppA4_K;j0%Vj09p`v`i8gCk*4)qlZ>MGeNQTdCFF;uRPP+Z1fE%O?Gyu}J1W)i z!SdNs;gzO5F^nda?Q4Y8c?E`9)<}T2_Pg@&AZb4z4QXN>Yq*yp*@^BO8&!JSxVX^C zHlqaVjkL2g&tJ`p{MSTZ9Hg5(2m5i{sf%Xg_v1KUm*-r{k+nHrhs6FRk16Tc5`+$N z=nb@rtxZ;c#1W$AoklmgQJ8Fn5|vR;!FCs^rm>!e?bzk`&&;t0k9f`u-#}~262I`( zR$B}sI0B}oKIqz(b2sJeO85>E6?!j*!siQDAM;rHl{&8~$J+TXTJ+Oy@0el3&0SV$GD31FKKQ>7M0J%1dml(C-HED>pUyuZ{Ssz7qpgx$8N+=$)#W{ zqdV4IXHl|DWm}=j+~hgkuq>#iqu$R9v#liCVe=!%1PI=L0^Z8iVCePgO@_X`>_16i zD6eLep~f{Zh#duqDy|dGS334F5=dTDva59rz7ot5BTat86c7WrNcg@%oonBQ7B0;* z7Ojbda6m^OMvF4y*}MgtG4ER1IMleLinJ$NO6A2iGQ7(nl$v=9<7Fnis;)L6lBsNX zWc4zyRYxJOg35;um|_@qI5+S$8j8HNe~lum2FeGP#c3|V3m|*Q>DN_+uO+MSD6V}%?W?)!({vqg89whNj2l^OG)FHvPrd zMk!ezcxQTBtk{N`CB-n*91YfajZI%%YHDMqlh5h$A8G@2k&I3h?bl09SJ0C~OX?{J zLBnO2goE87UOVml<`uBm>p~|3PU&$&U1Vj#QedpplM?e!W%&f;RwkDElfox+5}QNc zcMKZ6^m2z{)SSKOc2rqXINrmDq_5||GuvJq;mB{a_YTcWEn0l$RfY#7RziBzrui7e z&Id5)bSRCVMQ%{-D;J@S<%nBJ}KoRFZ>ae zCSC`UH}o0P>({d;GnEuW5A?>RU+^Q1WtwU*tCQKWznvv{{}Bk%!Ydtx>YR77ld9;h zr;MGVk3N)5vbop|IKF9qr?zdE8)5N0`}kSf`2C!e#cbpLU*Xy$YZ6g~vjy>aW&yK0 z_iU-b1i{pA!2{l2bG~|yIJwIugLrl-CJJT!91apcXd3=!O7&x#!`7e~ke^G^{4eQ9^3;k&Yu`Vx8zZtZ%0rW8R*fRvB?c}{<5%*i)pg<%eT1JZ z@_BS+UC(UKxugeeTurw#jpR#HlDbYY8Y&UJ72)i9h%fB=)&G_E8*Kt$ zeVU;+tas!elYf8Q6dg)*lKZhr6tr$ag!)Ooo6y;S8q28-9th^2*4@rm+6+)#k?Efe zm-$Dakg~hQTpHBdF}@$LZrSmE?Lj;JZBmbhpLn_Inct2zv2!XmW$PiFqGE}$^W^0| zc)RL_dXXC-GG~7UbEf+P%k9EGHh5yu`NQWX9~REtq<)&*BRWv>I4t{($MgR}CtKXz z77TpMQe4Ofg|WP3vE1^W7gNMkC*ePWqyQqw&OZXN zEfG@Lv4O4d;Lbq0wtB#jiM;<|!vNq98`(?IXP+=f;=%-3dlPdjoEz54`pxT|)Bh2Z z`u~1)Z;CMjPb)unNE$U-+pO77&K!jf86vjARlwFfT znkRL5XUm7AWqC5T*LD2T_WVsAU$kD7YS?j3pSM-2=uQSYyO)`~ov>U24?a_sji%8X z-vieLlcT}W!hxJtrG90KFD`r4*qiB=>1-Hq_Pr0`<$6J`kk@{Cytf`@X2vTl>=Ey% z6;3<;n|q${te-HLxO5)>vtz`06fB=cKd#=}Hk0e_HPKAY^z=!tXL4v4Ja5?Q2Fog# z^^c%+8ex6@cw-D!x({K+(YPIR#5e}36pbXdrr48yPVWM(_CeeYZr#<2AJ#)2%xM~A z0;XWgd;ed^{r~eGC>V23-96-89Z9gu+Jd(AE$o1InEPd>wQckKf zaFCJ0VKsOGZ%|;wBYjMBp!tEyzwr_S8}Tadni3!vx-qCa(ti1?iAJM*qhb4$6@~!I zJ!bu?fMQ^YSg$eRlqalEYrW))fQ_5pV|Cl4NROApGAxT##fz2hvAr7Ahb)qJC#u$PeU&3Rtta3=^WHpR z-goQWO8~o78?&;uKPhZ-@Vqs+Gb#&$vJl$ZCBJU9^y9okbXfr?K(24zUf|F0KVkFY zTL9R>zKK&jATe}mm=1StIJJ2iV)t-jKZ*L%=H7!A(5Cphn+2Namj%KHbpH50a z)9>wcwgF;7eYb>Fk|;ajmS4G1#5#71u3jf-kSGD%MT(}p(!vB$S9JDY`G8=1Hx*798w_0K=#M|vz>IA zo7CO*ckXB-J6y~Hov{#K?&RByPn7f=Z$w~YndmfO)4^b_SmDm!T#z^jxd}a}j@w2n zBl?r}oo!Y%6@! zJ`!C_WLeD3elwCouLS;fA*iwmiu5`qb6i~6$r^Pl;jxK+CnmI!qwE|7Vvr|wg>%T7 z&j)PI zx8bSR0jJ*gNT6-8X&_IWgy3bv&TQ2C0g&Y|9}lLW?RzoKIA>JMm*b!2G=d9y=T%YI z?lARpaFl$Dh69b>mP$AmrZE)JdzrRv|ptMc1aEQs@f_~kKu@7SK zTKIjR$Xl-oyRl&yT?i%}%a^yl5Bq#nyrulWbr96vw-bLGvW5GI3VbNU_$DQvoulMF zv?mW(brcDAQP^O|1P>}gR_LgKcE3EQTB|0g9d`7WF(A?zNGdjqBDds5wI+u(lX}eP zl8n}%*=FqV2=%@>yojHtD#A=8zhScFs=%Ct=5n*6LM2*SozCGy#qHtc5s%evUPD~G z;ubty{0cwrk~`|*ca_ZOB!xXL5}Kfm$a#5-greXuSe&@<$&}l!3sdK{@nj=*<)=n? z&{KoU{;7AP=pQ}bG|&7#J9^??J#D3p^%Fmqz=jONe^&=T$9hxekdyzqTK`VWSC62P zmvZ6tL5;*=mxAmY@*X2AI&`XH8hFJQ7@{_H0JAcp!qc534=)+cA_&Br@Q6)(9js`k3^Qd5B{k2^Dp z(%Bo0gy@8uJJgt}P63 zQjC!d$ilbXSC6Z0f}CtO#~y34blSz51^!$rOk3-9Y@ju&Y~|{nQg*)8w{kTL{M^u)nQ)+3u6r;4uhWAS>6&_q-~LhSL#Ua*FC*$OyCD&W2I%ha2m$?Dbr-g zH|X8y(*3`gagrV?q}7B8tBm{RT;=F|BqpI`QE}OAzoF)qf3n{X3RD2X_2Hwtrnz1z z(Jr0*e%?RDB$K)kt?|v1gXl=)lm1Sv%rnZrX>`xpjW+veI>~$4zPMTHE?}EBjG$h! zUR7%=N_R_#(a;{$4p6fCif8`G1f1A<&AYn`<~G5=%Vv|b&GE3LdGl9A%Oj7r`4T{; zz$Qs6&r8qfm4Od@Ukf;I8}*air`$2RioH<)R3h8l(O_ha>;PE?M?OIk0fC-SC!gPE z39dDbfRG2OmZWdx&3c+w6wwdYg)khfRDsWCHN4%eMfp+sLaMjUKT!y1yGYq8#OBX| z;kFQ}N+fZ4x1$}=JHjFv-0iRsR-Ki+Tb;Sr>%y%b;<(zq_k6IXs|#eh3)>uzkSeSC z!6qbSA2Uw9X-D~3N~0+QKGQPWOUp`!6SfO4nk;hD1RgLEhDfg6vIie!&`;H# z8>RsPc=q{}V;z^uyL{Gc4`g2;$H5J+aBupCAe?O#9$)V#Zf0R{y!~XAq^$o(!i&Rk zZ*aUUbHP54ze*Io%34$?D z=$B2TVn#J2_HH|Ij?nwfjy`PUv@k~V51!x8al@o=az#|^Ys@#C+3&zS%%Zb;=V(BUZ|?IGOtUn@I4U_8q7bonX+H@m(ekU^n!=8ym8&{Suk9oTda|`%}K1) zzn;Byc`pVlIR-4u!AN&nhx#qPoN!foi7a{Zt|cXGh5%*SYesmS0$oFtsAKIg+r6Ea zplkymd~NJ4C;gdHY5LXNKlK&|Uj}Tu;urZ(7+fb6_k_v9z^&*xJ1IB=7?e zf~x=t71Gv#X@)@ic2%b?j-O#gZE5X~gc=sjm&8{K3+ue~vo^ z9sZKC;?(KcA?-_bO{l&PINhEFN8pzD)8-{2dlBSxy@?C*od@l@YG@7Q;6vY94|1iu z#rS7MMDSg&sV=n(R@UAivX`SYIXjZuPh>MIfL?Junl<}2sZVS=2NrG(Y)aM-@vI|F zse@j8YG|-}SleiROBhLcKG2e%xf|#>5m=g7pTXX&w8D`1Z8d8vW&r=JlllUuX3W*f z+!PY%?zZWCPyRP&W!K=@_r2}QQVB4NqapDml6=YfrLVZLv_i_oV`w$}VNDQj*w|-w zfFxKLDWFtY-}lu1j(H9&MG_L1X^~kBD=HP9`v`23r$1jmZxf%v z#Ohc##bC3A{en+{d7>K^2@1t!7$I+^{t=kAY;3MRHIVTKQ3PpLK9#V=!tG}FJpn`Y zUyLa~?i=`GJBr31%35Ylsxp#stlwG7U&Q4}VpT zK-CD4B-Hj$sQAdw<(u`!$vfV>K|C?Gx6WwCcG!}lBIJ~k$a3sHXEv@;i~mY<8Eqzw z+ct{S?yC?DOaezkXMX%q@kT4ECfxC~OB~JVW%z>A;ga5t)QXY!0OGZ7|=TRUPkYpHFxAWT(gb%*6pjm&mQIMa($bQ$-jb zZ!_}xM5f3r5M0;Hhp>JNa#^0GK%0hT*5Wj-vyN*Ph2zZkolBNXBAL}A23XCFfD;K7 z?JJK+AmPb=jQPzCBH+mn?&_FFiN!8Tyf>sE)?Uas;wkGesHX#jK{SfD=$xe zDJUgyN0^$o_}7FEQtJ0d5N)nArF^Sfn)KHDZ3tfzYaeX}^H#M={7Y`4M2icYe$U`S zdElsZm|O0BAcR-uA-S?lq_-P+wfp5>hUZP?fd867cZ_GzdXK3Vjjm#hRam}Sp&gco z-d?|txcApASPhh7T92(Hx$fu)HU1dl2^I5Eze(KJ5JoGfauqn9x$UwVI1QxXf&oko zu#492bN4VvRMoKLwis)jq`NM|UxB5a{t+}5_gXM7crTH1O==6&A_-Dm#^>GEz-5Zj zyekW=72EQU1jfEQc`oh-XWw`N{5DnmOd4|0rjPMs;#Cqm^b_5=!QL(6GM}VwKZl{7 zYwfO5V!G$?x#4LH%@ENF{2?WzA4itAhdIw#oM0g(UJZ!OBPn{i^9HsoG17Mf!2(R0 zzP0cQtM8J_G~e(N-EwR({+v^J%io>@TC|?|)Mn~hm+vIXRj|{k zs^1cJDk?vSNv8M{ zGl?h4hW`2FZl0dL8aJ0X6Yf(&(2Zx z8JPONIzmAT!3~!(!Z$q%VA*(-fk1FJ&ZY*-S%pKOQe$) zy!q1e)c(Vswz0Y58V)M-4#nS zY5YeZ+aRCfG$jc>965FDdk9#wMzQA@3)VAcRJTPh2$4^@mm)Rre7J20rU~vh+{qUA=d?SxugiL<9_VuOM4YY_g*zv?ooV`( zcs=WNu>E(Iq{mBo(s{Y8N=$3+AHn;U?2}wnM=v)}qtOV(x;afj`w`V2X$Pt2BDX`- zf|b52J_rApE;nij@3mQ8)RSMtD#(;;n-1QtZ3o~Bx5gva9tD#evT$H!ihD4P1nS?~ zs@0fl1_gY*;E`iB9Fe%j$V%ob{BD4x51sn#Y7`%((P^=Rg@!lB)t9-O=l zn}K8fEIWPjv9GBCWT_0W`&Vzcn#KFQob8-KiACb5#QIeK5uEY$h<^5uEOayhG__vK zEAg?)As;gNlDX>$F`1QSe?mbsz**_Q|6aAfHv8abxtw#8m1STC!}8F^3ckFN3KwLK z9v8q;Xa0J>61TVh*GT8PD`Y*dQ&hJc7!{Xq_dU}*b%25?AsPB3(x&rCEs?y79bBEB zipuqyRUk{To|?Y(|BOpGHkT+VhqQL(u;ZX$t!b~f04$5_S#*Cbb6*7CQ19{U)oTA? zcls+!19}cn6Ob7=s}47Xe`Jn1*?!)QJ3KyJu-`(&bV~Wroc4C|PPx=?5h8oa2|zuN z#cQKOCSGkLN;K%H^iz74rxN>(C*wcuJAP~6&p3UFT4x;L@-MjFU>t_lj^>Wu6&vM) z(ysF7E4(3(lo-t(Klv5s> zp14?(R8gNSDC=e&*MQazVQb`dvAf&vUe5_;fJczLcKDb~1Z%xh>CX=~q4*p`A?K9& zNXagmfL;38Pub$goe!O+>%yKMUhbG`qCJ)<1%+@4z;@o(D+F zy!TE3ksS;Tls+H$0y*6YepgK=RSU|U3tMOsmYCaAa{=bTf7k~%nGmu=9W65Hrl?SW z-NbJ>g(qf3@ol>Vu^NWIINk!V!OTfj{&u956eI0CV>G1$0O0!>Jus~hcV^<=?aTHy z@5lNL;KMop*A<^)pLMxTG&t1Zlpg{p*@={4f&7OTH51xBal7h&BRAh7Q18}46PDN~ z8n`~9Z%VHI5eyty1B81@UBg3->BRo$H1`1x<<{lEZG8Cd{1Tpx>r=`pYj55f@VSuc zv6{a8gTBuvH}cj*c>FuidOn0`n?N$Y+zk^V5BW3X%%0D97VoF>qr;80H$fZA1M9I- zY*U@_^#SvN@Is{vkZu(P@)2SS2h+m#wrY?!<6Y2cE8?g^-s+V3up75g$rTUW_IfUu zh~_QC%E=aLuEYu)i{1cV4-0j8YVf;3%KqTK&NgK0A~$t|DflU9^YNb9xeA(B3P;7h z@tAaU<5q?FYXWe5`{S+iKbt?$>d+_WMoNvn2y=p5$g-zevBBB)by3=qN$m%mf8#)? zchE>ux}^;>4CG{20ffH(fCtEOq_w~$9)g8}NbIlY0-w{Vz}ZIiy0gZ}R%e1a?SMrZ zi4%<P0 zHiK^2K{wStodTTgZQ6;z;s%cR z_bBTfh80GTVkX+%ue~$gzrTU8&b*j=lP|+tDy+|xnRYY5$geL^Fke!N z0A*_u9TVR0E}KvxunrS)Io4*zQR6M6O7e4j;Byi;1*XjmL6Lkx1)1QXC7T@bh(}ak zwjQhsK}>(gZv8z%)kH>av}??lh6wR$NDos^k?2bsMRTI9(+3q4@MCX%K}b2D;O*`w zC4f4bAAWQ$#vCUR>G6pmLO@?bY8apzc&jK0QEeKO4Ty$8XhF7gyX5|;={^ovV1Y+;gX#A3H#2Aksp0GNjp%@+8Wf&>_J=9ur zT;lc240h_~xpJ{Ra0r!9_VzNzGLSY%wiQ}xTt{0 zHUY=O>WEc#;a}2OVCYj;>};&W5abWj?mq$}=~9Q9UO{vK20SA;yy{2rB@!RBg?DoP zFt@pORB+6kl|%O4-Xg=y>dT8U=kiDCHYbI6xHUsNsINV%rXRc;By#h@8Sv8aT^#G1`MEl;ZJgwP zVSxD2*7(OxNvvP-cf47jVdK9l9NSBR5`jKsS!WMQVoLkwzrZ&WoCXv{rB*?Vf6r-D z^V#uOxD-83;vj5%ZaicW5%nJHyx|x4LVRjzxY$(n^pX!HX$iGeLU%(q?O& zyGqV{S4c9{2BsB5tOnU|mpvUI>(CxhY&LN3mDp9}4m&q9e^;fv zgj$KVr`k%f_1P3=(2uB(Jd&X)TD&xu!DW(hPM@*F&;~O9<6*#1amka9Gx|XpM6t*;o$>;tXnBDd_;6rk+0wr1{%xy^>Z3*?w zx8z=pID7QpH%ONav4g>XN6E{E_S&Vm|FH0Uhj)JY1}L8z$Nc4`%4Of$d2_)!vnI7S zg_0i?S}Hndf#(X;%v<$KM&>Y1H@x81mUDGI{X&RAt`Vei|k}Upt*_?>-(3q8j}vJ7=reApICoAG{JN}MQi?zGU~>dN^D=Fzjuja zkGGxc_%5Np?ggVm&yGip#N`qO6t~vGV3c^8QF}KucTZ+<_|7y%L6fG|n3-}4)ke%C z1J49}3ZxHmA1GVXDp#Xf<8ZX)e_AbzpK7{z``U`X8)gdiNb#{iJeS!mG$@+%T{g4> zrUDgC3!NGrunB(Xr>#GGQ7O}CzPw;E>`tN?KkplFOeRz8N4~+``;Q=op?;AY2_ts0 zWbbSw{D0Vbuc)T_H~Q0#QbnYfhzLj%q(~<=x`6a1L`9@TKze|Xh)Qn)0@77Lnh@zo zNu)O+(jnA@UIGav1PJ-fdH-wH%$l|4?p)*|>zr@h&wf7pM?}}SK28+CkY_RU|JSq2 zTCNltz$BlIWI+p?EMB69df{^nAlIe7Bz#UwQ6l;Ciu7Dr@mt;AFG1gc%TdEgWwx>H zdDq~YA@~+E8#6%l`wA0vEx2`w@sIZ>-BCXG0{*HOuib#$srt^m$T_}Yn)71fW%tZW zvE}#rrJ6SNZ^Q&nV=g~qHF$4*^5OXk`;4m^%|^hA$9>R`%LmC5x|TEDM6E3AplFj{*FQ(P?lFiAJ zD(7>hz-<^tv?z78(+37>o#Prk$h+E(85kkHSx#P&l_vV$dJ%ZTyq&vCeT4F<$$Ij! zkOmb>K93J*gv*fm+w14}$C_(D+e4;%FO>7UK)=3K7QPYRpY$nI>U}v!W8<0cU)U_A zA13IlpvFzu`zc83t-Q$mY{l2BT`n(IBekyqa-Qz%7v_G5C#JSp;n&X+fu`o1q69DW zJ($4+zMRGfiN4kRzcY^;8!cUhC4XXX#o#}O-|yxjLX7Dnxe})p8cz5DD=fjPkhN@K z=j=vhhd+zj<#G@4=7yex$G3}zIhVW-^=WSE?36_8j)0Y?YS@1mICFBX5oQIbht4-`*vZZgbX&(WY zH2&-#)&5KEQnyd>0%swvaHZ1}FmUK#pz)2+mFc5u1H<|RQQLB&RgkcrQ;KvWceDbpHjrVM!X4mY&v=33Nx8r_JXZRucEf$rKB^QNg>ztxs&4~ zH7keFa}%+Wrdq&J?Y(<->xn+F&w9JAkjA?3bmAC>I)T$tneaoMTRTpSf?}hjRN+(8S6D&#T&4-uav0zvn&FO^l^T&F$?^0IG`iOL6`m z!$U<)^$*v^3zeaHg1}L(RgW&XjvMIAjm2v|dNxvCa7rAm>R>jwKNp2~gT%y~q~pO| z;B#nS(z0Z1KW~(H{7s+w zjpZX{dFz(8`gFtAzxeAFtH3DlIU z5S9x)mJ%a%gA#k@-jv$b%s7n|p1Qs;Ym95j*nkNA?+o<6^`n}S&k%92X1}5Oe^=W_P;UT? z^31Asn0-dSXs)+pwApJ)Qs-TONck z%nNT#LB-KtsN1cn!QZRCvXB?ty*GN6dqq7#DibD|k?Zij?Zxb>*u)@32j(iJdJo?2 z3@muer&%v<%GN`=-)s3g-xo}< zb3?tGl#XQ_%z7@ow9Wjf0}!G8pQ3SvYE8=T z4Ai>(uV$+G)wt~PtfRf2@OxE2nomR?w|!YgZ*NdgVaS^LFr@3W(ZkhNF7A6?`O>;i ztD2@)bp_(XZco}eYJ9+Y5jy<{%@W&VPyYIcB=F2kds z+l8A>6{(*+v3W24yCfm7*G@CQwH1rlyRS)|luA^7OnSaP@t)E?F-h>6~4G9m7P`Rck6}gCzsE>#!21IY=mk6%POKEYGAW-5~G&?$Ymwg%4Rl z3RU+l>+%`{S;v;?(!iUDhszB6pOh=KX$g(NZMm|UO#IzrK1oUd_E#TE@57$+a~SV7 zDmbw`W4!;g${^FImsnA@qv{m((M{|)PnX7b`V|49g^+6Igh{t{g@5_SPzIMD&P;1$ z|9F^Y7C$(_D*z%~LQhe_fw$=Vqr|Kg_G}M9t5Mt)Iy^_pl@(z6+ACN>Sd(=R(eFt=5{`wU7L#<)-HT8>`CTdJSeC~BQ zw{0b1K62uG6xp zQ>mlOXG1v^9x{RzLAsrwX!>>PBfQ}}A9ZNTZ}a}8QQkD&mvY7GX{ZDZ31BLTQ0;$i z1O!83;F={c$GPqMH(Ju)eB${MZk6KJ1Dcck$xx0sXv-CJ^8H&{@#5iks{s82H>gu8 z!O7UlWsYPbbNrZ+xYDko8=sQu_xv)jlGZ{%Ff0W}bpxzG(IfDiV;z5St}++md;8Q_=VNw>2fUGKCs{gH7DCOzDIl5RCoSefMMD5Evi zJegn-E$@9mXddaZW>&IwJm)R0t}C#D&bn75n*QQ#$w?p3r@Vsy7BEFRq$#7ejtVvc zGufhKQCk)JM@#izVs%rM+oo9=J+U_?hVobd?|uYuz?B6Eq^*3J8v%Cm8F&6%QvLeG zMPBE`hWUJN1+BZCwsSTjLDIX~*(2vrt$6H1YRV{e#0nU`nQ*ONWXb7uN8VA{8lJ*k z=g|k+yjxE3jdACKgd2{uLnjszqj1(87#26QBFTRZGgNzv?RpGj(%^(O%N~Q-<>$fH z%Df~o1<_Ws?y(Yo8No)aZfyYzalZr#Q)~u9dXL%t3S?LA9g|D0%E7093xn0N;j;{!`-(n4 zP1s%!w~nVbr>`UgsaV9g<+>4!98dk-#NT-a3B{b5ZhxKOli2j4Aoa@PH#a(2sdhY_)!(i0ZQsX^uUU)Nos{KiX;OkhzIv zB=NS!mcg(xSd6ReR>584XfNq7L1P|g?cn(~WFm%@E@Ct9j^-v`Q2VJC98`Zh!}e?9 z*rL}L*-I_iUKd>&;J5Ck6m2&l)VUe=rj z&ISeIVoA7+T$Q?qmw}pbxOc8JIW_X59~5&H_FmVX>GI#iN}tJRZ>7j_ENTruAK&iW z6ib>l(|>%_zJMWqSU@FUt`ZRfH1LSm_y%k#lK{<$7BGDT@XZHa!T;N}-@|WGRSC+Z zv?Qo6foRJH=*S{-J% zIPviY8TDaxny+_h&i1!Z=+EZ2i$jeibjf2Ee9JJ1Z`%Hm&`PqZ{Nzd4Q|r}H5-hGP zO6!}IUiXR!m2_at??P-&(f!H3+ zf#Aq)S)5@T=*)fy0D!T6c)W3R-WG@Z^*Z~WoX*I|9OiKc6`A#~8&6UKFRx&W@@D*W z3Y8gdQB*KfCzKwNNjG#ek!ip~HiBl!coggAr+fSujx5!j7FgJW*p$x5_TFFo$L|N}`;*4-(j6x(`W#{w#7e)nIRevh5c6Vzg{R1At4G-9 zU|_yI~jl zxBah$^^>qEeN#u4(hU#I{aig~vw6IuacE+hs6J%tyXym9u@!Ce3E*Ecc45Y~vyBwD zhaU0t%L$&F=)o6S6>9Ue4EBSh+%fg5TYKO8{Km#Aws*dz^!e0bm+y>x*gHfOqXlUu zBy6IetI|BvhJLZlvv*c{iTn*c#}gabx^28@^LItD9c@F%uyDywc@2rO)Poaq7{`Lh zdflA(UQy%NS=Vn-J|Y042W3q{#tD-XBldT$uMZBmlr>IkZ0C8+>AF#;2O4$RIng%gU$!LS$#U(P zjNeEgh(G!#$II}qgn;oRpf7YS*@g;u7^JTbO>Z?h{@q)fh|7vu3otc)9Awm;ySQ$# zEuLY#%y8iy(t!3d-aRHH$INkk9jHnyHyDAQH7CCuU$1-^EbzK{nh*#?;jo_C~jYauC8wQB-}XlW%Qn0 zN9dOIFSy=mkp>74VsiryiU(^g(bHOX=hGA8tfvT6aryS~Z;S~Wq1pyD&mc)lU^b*@ zyhwMhl*vW+I(cdUWi9N@D>E*K$v;Ppo~T+s!&w8uyvJx~mSz*H6kcWIX2+}Ad}E)+ zS3t+7s)BKj6$s1f;LU;Tt1r55S~Gc&Y*W!`p==XC?>BcyJV zW=>{Ff2V|Ht4sBVUeRAUvz_HBci%Jh*qH4@*=XOUlZ)A)Zt~FJcg0_M_cL zE+M(frch%`*`>DMVj3iGOD%rH#QYVs)a((L-3Oc59Y&c7i?aAhls`!es)0JOOKFw~ z@vjeI+q^!e{p4_m4}O0bh-BU&wjlOx*S+6O_nyqE2>ocDZv_i&A;fJSl~N6TrjBwA zwl@M6I3R2vdn9grx_CAx*eNZ)%_HT;Of6*C)w_bA5E4Nkdg6jXGo zU2<{0udS>fm4g5xuH$zi<|L6U74g15wO`>qU7}u?7lwjKtAub==REVHMVWh->MFDG z*RzvVP&nVg>z&TFM$CQwvRDswhyy}5=V58e+pSOtsdQV$(6F&aTSBnuEEXZPVuE9$ zd?aDoK(R+FLU6}tx0 z0&innGFZoTx>%uX-FbCzH1ovvn;WF%@rD}`DO@@naTHW2EGRln^To!PzLLMx`oC41 zsNGqiRg(Q8B9Z*TFr@=$^s~;Yr%i!5@)PYfIx5mM^FI24wOp;#L?AEj9-B*klp0t@*byybQY|c2#r%ADmFT-z@QI zVldTK0ym#ir&=~@>IO1_LAx;1b}aMJ!oC#yS2LmZ`7fIvwPR|F+6BEjlBpi!gno)qw>!E61L5fVe}&8BG&??P%s z>!)d)3b2MD?r99yl>V4U9Xe^8&RADREWEL(G!D0m7B3Aw z30=|Hn9v;tv1n<4I~*?h_cJ~GWvl}c2q3h)oYT$Ye)^<;w#$(Z{4^M2cWuD5L|8lz8z$$#P;25Jo+NhJ1CLAHjgvfCpvY^ z36i+JDYzXYzB8xS-%ZTr$y&Z2S+|%AT}+J1W7(hoh`0@a5)O$a)AL_5y9~dj3rF*a zWBzx>5#!Uh-ih}LwM^WgU+z+K&*7?ZYdR{bp9v9*KaqklbvF7P=fx@YXL&rt35#U8 zus;F`%C%?i$@0Okd;sbniGH!_ZgYFu<3z#oXGK|P{DZcfmSeu--sSz%m~5dIlbSzd zP1_YExv>|nn|-H%ZA3)39aL={zU?&PLTy@PBC;Bp#+~c#pV{R(mdESJ)qvQu{&@Eo%DT$1BQrGdky?)32OqVY-;(%IxfA_%I+m8JNP|1o#klVQ*3c9-Su z?*ueZ#``aME1H;%NvTn@~Gc>M-fHj=YctSkfb0CqF&iogp7jg<>j#1=%_@Py}%u{+(t z00_w>%k@km&fb#y$q1{?Fl6^wvKgQX6y)+gD9ohg6#K&GxCVW~ze zTwetnJY-reISWlQG`FGMnvP)cb7Z%7r5P0&-RQq!?zXQ=K&RZcE=|lF0MC{_J652S ziqeIs-poTrQ*U#vxa;~i^c|;>+dv;+DKMPr9IXE9xO~zdAx`$de zZNA*@eum)}D$nLeXn~u#!-bgfc~P6!jaW7+lNC9qZ5=IC11(E`{>{Q~cIKGzuxhQZ zMVoVU*PGgCV<2B{{y5Q^4BGMn+}xSxp=9k#Urhshp&SUZZhZ-%IaZ(Qy(sgj-5M=2 zv>$Y5%Ws`=HXNj(9=xn|5E>vZj(X^R&Au#;=`$H&8($<@nVRedU9F$TUruZT9q z(!q)8zX!FaiRio2>!=c$T2v;-+mHHt%5~o3XxCA{exj7c@1cVxtE!gT(BzKAi$>D@ zGUXp)QZ0Y4EM;4!ub_u>uUUK3E3CQxl_A!g<~i?(oY}t+%y{H%a~#gk7!}7Td#>!+ zVBqtFS*fx9jXg`n_d|KlXGF^*x9SP7*D^O}9y?uN{v5EtNBcK)jprq79;)Km zunDP9k@XHj{LDSq{#*K49*u@fR)fl@8QC33f1O_G`Ey6-OvOYe6W>ai+DZf+DMy$#msomsT6w#UhYdK%ze1#$5!)H$REfhgfQF&ilyEMiW#qd zz2cDiWz^ItQ0wP-tn5AWWz!M{zF)Upv-tDckX_kr_uymY^n1pz<$t6{n@FGy1vpMOZE zM2aN^uv(}s3k2tv;E;^(C0?Y7w58-3r!Ehs#9K3FDuz0q=MVoY_o?fJ-RD;onIdU( z967~J5$e{~3*bn)9FWv48{W+Cv^v|{f0svZ7AMWA)#3mP&xu@-C5^jZtTh`wRI01LVck?Q{OnLTx^=?%5)x0+jDT^i<9y2 zg-XQO%)Cg}R(}RM)T?+Czy%BVO>v2AqlKoEMI|fSeiUA+3C;aGp7hO9{<)m-*m2|u z_pCPHFS=Co+$!e0UzRn`vxTLYV+2>^4i3yl#$9>UXVR!uPHE^M%yu+ynnz zIZy#{QRmx*E)Jub^$BH#Rl_xtPbSQT0=il@SISJL=P8dyJ*|epJmud$g`uHAmJFkW z=8ds2<=2Ca7TIG%+d|CL@CCN$%qPdF_S1lA$jIX7j@R`beS*Pp6E0AXYoJDz1C+ss zW^+}S{K}SBT@scb&SDD#cJ+4N^vwHJuxRW3=#SMvj}P-SkKI>wvb$``&G1gjDh?|` zttKN|=P&PDkpts8dJCrIb)|oOLrV9&mFKR773L8SPsHcu?WgRh#rcCz8ItE7-?y*k z60pwE&{i=_ezF!XVXV<}!rHfLGD`eDDlKLoUND4fpE)*_rb`cE^T(BnzY65cvoGLA(06WU}9 zzhG9X?u$qi0|=G&hUs7xJ!LboC3SyW$+2`%>SetEuw zl6kQq%B$2=xuzTK(`!&5q6E`6T%x#`SI{nyCqBa6UM$4BciLNw1@POv@c293ly@J~ z>6lMIP6jU4M{20RwY@x`#ed5)-r!RXi*vu$jfvx0E-xS01;2q?y&!1mM; zsdJc5+Rgs-OlCAKIJKmvF|1F+xXG50R&=vMwB~mCt}MiWw2hdLEHW+-QQ7KObBy*z zZBQCTKSEdM1_UH>yB?lVI`o5(jN*MlE_;Ex#wosP46d1zpV)o`0z{rS+~X4UzT{j@ z^0`Eov3zYaA7A1WNRwJmah_6Tfh z!4A(zu*8nIYMIt?l;PalJkfO902Q`)%o%`c1G0QS;pjK2*uO(PK!?ALLpJEZlokzM z!VXD6n=!lYW`6E!@@t{>Y%V-+4yB4Rp4yodS&VP)Nb%f!Ie&XFB&OvBlsRxbMY+!@ zmEVUHJRxeiot|Y@B*0?61F#s+trsBAOns!k#rbY5HS~`LR)dGj?d^OO`zQ&m636ZYeFl6NE6>{p0H`D_vnM;J50i5 zQEexFV~PEH399YRQ<0<2TyyF58F)3_Hh{{Xs6SSVVVUkOwOy-Hb5MLE{{#GGA&}5K z$1j1ZWzys}G0|FmnkpQ9f2sN7ZBP!pWB0i7vu90O_qvMo$wjLiYwmJzY`-C0*T0x1 zK@G=)uCCAVkh$V1&{;=Q!Ji?iaoNNk9CQteokS5HuI1s(coR(Iz&ff_z4 zzm2qVvotqtnTEygd0pMzk}e*U={11{Y+ygv%1Bw0=8C+(Z~o$kHrX=!$bKtk)_t2~ z!g(}cg|}?o2b)^r?LNAyw8Dg)QXxOiQ}CUA58KeT|fk~K0EmPuDez%W(mr=7arA&mqi>C{D zx6}J2<|F+vzyZmp_>*)a0Z6)6+ttaAYQ1CUN;e*#KpnnHU7bw${o+o!dIr$VJ^iWxdyGG*eY*W}yD-b{J zLEs{Pq9D$`d!gTJPP6b!#8cZ|uQcUoRa0Uu^i-X6eC-)H(qkKAPAKa>+@b|Aa2_9! z?2SWE)LVyLwl30u@XT>__T3ZN*Q>xM97l~dvfqhZ66MtSrhNtxhHO=$u`JAU(}x3& zyAywo1IQ3kKzc|;4QuYpnlyKfD(i2P#s>`4&(`Y?0Qvbljfc9ZRY+>;)H_sJX&Z3c-eY=N;Sbv<{ zpuTs_cNeAuR8q;izpH#tR{=LS{y_7#nnW+ioOF zZ8Y13q>gMCWKZQ<6k4f|$1D^=t{f1(fRT0vgTJ1;YBa6&r9LE|Ye&GzNjx>a-SaY} z&qL$Hv+otX15HSW=7djf;y`ysBeZ4unhU5zXi?bb!F zIVDaMahc?0)i926Zvsb>>QMRi4}KIB_tbAvBD-#-@aqxtOwwv?q=)b$pMTDjABVP| zwq@;W=n?{ny(BE9m9!GQU?NBru*0p}4HRx|j~rFim?jGfhsK!0ZYdA+ptQ+FG)|X4 zj^d4ENSmhpA4lZJ3YozyS9;)%fXC!?e%H{Ruh4u`m}92~tETTiU#ca2FX@EaEl}Oa zmqG^$PJD@1;Fn3r_Vrgo3&TV&l!N$H!wc!XD+~ELbFXqHlhwj-#k#SP# z#WN1FJw@q$96&`YdT7b8Lj9c;`oun|oUROJpG~2Oc)YMjOaq+`NcVD=2jd4jktD6k zg`l~^zLsz=Z;wxgT_?&c4Oq>!viE`>YII;Jsv?6=o4a!(G;ozxO|N1V7xDx(;XtRpJmcS&>V@#X}> zXVedt_dKQ36%1PWrQ=rwp5Mk>um#sH09`DQKM*EZU^l2%j_Rcu84cGBz4TeDug8(D z_i`>)vAn(?ch(K$Hrs7g(Rlst;B^=A!mSe;ogk?b^Ep}LJmuGE0ge6S4Whd-u_Hr6 z^fVg4CPm_wKdT=et*Aq{@;_!V!t49CA7X;eqBx! z7IssxqC9RPLFyo{JGd@YnRd;*l_DV-jVJ#Ovq(yFjv<&QQqP~aLxp|mb=0GM{$6zt zh>qHtpYqbBzQ7N#b%F)7q`QOsf55!I{;I04d|A~S1W#sOl{$P1xTHEA+Y7q{R*MO-XwFZnYMnMBqLtR6hiNhl@jqwJq%E zPxy>bHxcK0QC;=piG{b|VoA+Dpz7>6#hJpP&w~H`PWmS}tostW=yv?3$kLwIq3y9i zB2k!N#J`x9f;WjOz2gTKgz?)9)4+TwSwV}L4&)wi!_&AWWH|CE`}Sm0k4#vy+G|Xi z9Oh5rH=0Czd?m-ht?x~&H~ybwtuy~WPv?&!sV&eTZX$?mBwMt%O(0+Fm6v@OxBLn5 z*z$G!7~_XtUNH=^-|V0(>)M6BjF}>}_mM2DySAs6~{1L-E&u40SHV(P6Ur*zx zXiX%lFG_WOxx7H?C>7ZTOcu@byz)>ta_|0t2|h1Tar29O(WBAp5dto~ZxFTgH`Ea} zm(DLLke|p$!++GDrnnI5w_M1|6fF`s4F2c`VmR|U-^w>+vDEafOt+>anKVvb{dY%N zp);OBwNT14D#VT4M8I|sMgFWlC865leVC$N-_7o;i}yjfoe7*Nq#iZmfjo@aRi0)Y z`;VQAm7e=!+2)~^fIuc~tzeq4x@Ho)Z}J{lX|hGEaI-UbJ#U);^YwE|J2d;<5cM@t zojY78_FcX|3`^q>$InOkfgOU{=K$dmqA3@4z1XE$WLd-Jpwb3F^yF8$zNZadq{9 zR;J+(ZVgM_t&v`j9Xv2cdV4rFqO;)WF5sWG?WK_(yhT3ayblXXYayEg3 z5R98vjdhg-MO%gp*P*tgeWz=QEjtYptIEW6C?)Y7@_IqD75mhzTbE4#Y{lX^G)KfU zF4;4H`3}&thLdWf*Y%I{^75`Al<9qH%3CGic1Vm6pMzIt*=fNLyYmTNv{h_2ze(Vm zBRDqBx{&?{!=N}Hjk!#7DWI8*6gHE>Dc@WvZ!42;96l}CbB>=l&G{hmFNU5-_-Q32 z)qmHfbmYYQ?d~YPAYVdM2$!8s%pyN}K+5}AaGImRO*&{+{bp;#om6Zj#Px#z%9VFj z&aof>i7<{a#Js|=tUGd@W@)e$xZ-9pQQt#??(l6)XxStafR^ah><)VubrVnkhM#=S zGQV|H-0azQ!Dx1q!y9O1K#6$e{w-+jhpRy0B)tT8TK+2XlfX+%Y%w#e3wNWURz%{CP^yWE3AJ?H37|Q;2OXE-B!_)ajExVJo6^@SAwm&ZAA38Bj z56SMSzAER*t9xYAFiJlQdr4o<)Yq$jucH~*{iPQiGqEa5Z2!J~T))*$$eQjo&`QjwH?WYs}^$IevRhzYgha6GMgGqJ>#tJpyA%+0=#78Yos(M@fdr0kircq8ycUJ!u zr#Pv^tT{|BO{b&p+1+`K*7Bk+X&J3?JX;`z~9|(Xz(F(3Hlw#wDzZ~)x(;k*74^RDv;L%+feD`76 zQ_Fo9J0(u}^bhR3a~=L@Sd>(NxvJO#xo0|Kckgn-6;aDi+d3CT&2z`-nWp*DuNC;U zwd_lc>2BiGJTSuM!Ex@%|IS=kCk-YQuS3`oH(fLTT5%f%u{5o@`uv+p9_|!d+~e$h zWu6EKkwnm+{<0rKH0|Pw1yd(n(U_CQ#2%7oyp&p3KK3*D;LxhbQWVw+O2UvV`Hk*@ zB0+3-UL0+^jNa*e zPOsu6pdMlBPi&ME0`}Fe53st7n*da+=~4u#51II0j5q6@65ZT z91E-h>#wG9v%+rp7*)gRF7`&wC;q5UwL8%%^f5?nV3;)Gw(B_Z3O3T}R*Ys2g~ zqUibtE=&?>XTO(Uo>-v_*;;l?9&|L78wXhd*f0E?`$q|#pZHzH{|i)bx`wt&Z9^& zbYZZZ8*A{nP z7T#;lzy7~7%0~hXSv1X`NWHx3<+Lo$?l_3iuak34cFq>`ttOqoB>e?WQ@35fDZFkg1@+i6yYPc7Rlxdptha3TyVowQ7a> zFD6-5RLIsxp4g+65u3d9wLg|b$HWs>s&2>JxzpTz8HEn=7niZud8Y3#nca$*Tlm29 zc9zKrq3(%V)e;?$T7=2lWJ3?jELUQ7?Wg;{P4kFa7Vqm$lEt*%2xMFEeZK23UBl5O z2zt-saubtG+N*UP&`h+-Hjf2^5d2iTu6{bBX6bs}?X_geY!wjQ!KJwO_qAf_D>GRV&&(?i$bsE9kQPEmol3My)-mxe^O! z0z^19bvci)Q5+Z`pm6*yu*aIVTt11~jSm1xb+GG4_^zk0!DPGh&e1r@iv<7l zu2bIHP_aXs204Q|!eSrH)A`nQuP>K+*4F_FWrSiGL92yXswOi&?{BlYzIJuVX|5j= zI2KZq9_tS}<5umO$8wn8Y}OZd{e4)WES`AV9pehlc?!t)Yn~vXtl}& z${>txX;$^`cMqQ?8~)B<>lY%NN!(~a{dUR<*}d|gO<6pVBmL^jl`)i9h{~;&j9}}t z=XEkf1cOlBJ5i2ThlPR7>^;Pl&K>5#VOeQgusd;1;&uJ$Vt98QlJ5k`bl3Nrw4ZEI zRm#av-$juE>kJC_NAz_X?`cM}FaZ=*clYOn8LpqwzxkDSQf@_&`CfeYF#6u<2RMHj zL^g(gv!6LFSfcUf8H?~-9rZfEx9oz$7$*cm1lzyRJY{IccOiG?q6j5M5<2W_hy$9$ zSW!BDtfwKWTlB|OS-3ni$I(PQEMnWxa6MqDx2ZyNlSCWLr>H=+@=Dh5wc*&dX~=aN z3yFakzBr9auruFqZ0A^qMLCfh~lrP_v;Lkno0|G@4J+f#SrpvCDL~4cf=$BN6%{C^6S~RH?rIK zXO|PpHFWq8WlD4aPU`vXxYxgnVD+7ur{O=!#lD3sIkapssot%M6jr{}`m&=EwXd%B zSMpz9DPiRBw}jNe_|BdNqtKrIQO11LLHK+-a+;xg?lP%$>N}`LF3gAh<@`!}7`-jq znrPBC@Nk~aQGRE6+eU-@Om`_9pP0s~Ph&v{b}6M0;9{~rzg+>_3tp|Sg8m(+hM#XC z_7lO1S>XtKWb5Oa<*bEk?#kTPx@CS8ok_TR2=VU5(s%5Rw5}Bwc3p=Y0-4H$W&lme52IFD5;HF z{q#3A1CVYm4f(UNUPzwSwYg^dW^uAOja>KWvn4|^16>_bQ5mVno`(VrV>00;r3Jgk zK8W1{)Skyi06x>*DDY+~+O*a`aKRB&XR_;siMYE}M)~z~utk-ZDqby3 z^y704%@RdK1*{Y8Uor+-KH#k{8Mv>7$RdoT6G11|FcZ7_VPUH8i^7Wuvo{>7>09Z4 z6TSsDaU>o>DT{i|zxT9rrsi)-vMhyer&7=|crFn8hjy=CwpjEJ70KANC&vngmA@nL zE1wcN4Mozm1q3^Op%@$A6}FdbHXX;%L^KcGA3>@xB0nOctF_kesiDMGD(pL$UygV^ z6FdE+H`)EhIx7_#lfQvcs5*W|15qE4&o2n2lQui(?9`?o16uhZWw8x+WIV=J<$^+< zAe=&nnq7nr_PMuI$u}4AE76M~@pfIS0R2%5k>e{T87;PmS@rr%3k!5YLr)nAe=F)l zZg&iI7|v!zidSTTly%%Jp6s&W5Qi4jRzA4T=pA0a$GMvF0|uvS6FZ+5bA2I|c^AKq z?9YeKUH>(72R-d9`1z8ALQ3U3jgtw2matjLqX?3XVhhfr^SA&rkONa5u&fI`>#5uk z{zxFq@$8AwraU!p0U2Mbaww%;)N^)!@3M(WF#RRI)Nw?meI(QcG$1s1vrqcJAGKka zsnZnmVZ|JWjygHJ`S}^#qpN!^4X>T}dG9t!b^ZNC%oOaamr^M4b>W=&Q& zaNk-y%Jm0FxZn#w9Ow%U^uJXwh-3BWYie=*4;vKcbzH1Ja`uPs$a7#qoq#A%lI29A z7Gr&MZPWQc-`7}5i0#vzyx#6JPWevDs147%?UsL>>BGMDJE8Np1{qoOrvfx2P53uJ z+yJ+x2%?cGfp#>fHJhQ?Ry0}E`|3%^0L)JsG-&SEX!W^~t=Baryd zM=CKfCjO#_KfGcQn;PnrI4X(|0!nmbnou;7spUT$dDFK(zkBxl#0bA zhHpEgk`EVuKLGtv`!B*Mw{YeQizq-KAV zW_nt#@e1&mBHsYf;M1J}VnBNJi1flEp?`DEO|R77yr?1eF5;RY=H!(Ri}Sc*>IvR6 zRsr^s^hb1{KDk)#Ec`YOd^~mNTec5iJ$; zAzVMqMLYE+Y3IY&q=K1+OOn~Y1u2AjMe@UWReXhQ|sP!_Z=tG_XT`rxh zIWnK{3#R?zqBf-4ifZwUW;w<#s=$kABxKSO8Nr?IQH?sp# zy&&psN)CZ7(ysm;U1Z*|q6jEWb<33A5nO;|JJFB2M`K7djY7tZcr}HSXZ<5OmJTkzd>%K$z^R5zjMe z=Sm{vo7GS9&yWYVoWO-hRq~j-<(}$jM7rh^0S^{^|7pG2mOF;L+|k@_44JgX(_e6P zyphNsAr|V31($@yuDeh($jnbh_;Ogp8Fk$Xu;d|Jw$nJ*X$$nHWpynDKml6EczbO7 z9YVMcz-QsAb)?((Gs8D7>b!34Kbt+#g=AC2a<0$wz4!-L_h*?aD{mBSziVF069MNs zw%&n*-xofNkpG#MYK{~IuAzJ0*F5#_MDAnp{jwtMIHOGF0xoiQ(ncwuYh$L|T`L8a|E7W0`;(gW>O{8`zZW|dqxWlwXj@UU3ETSq z>S@Vt61GojXhFl-z+cpuzR`qKa!ThEMVgPoz2D67QA3Kl1KnSYF4uF-n|CV>B6{h} zzyHx59v1(2?#aHgSkiOD57pG}Frfyf`zf%c0fg)E%%Z^%~ zI4txE(;fwaHza2x0qc&A!E>Z&K`FE6LuAW*@lJIQSM!Se7$FZD!$ z?An?u>@?8keWpYorU#co%&k+2s#DW62FyasHHW;MI|**My{0ujk@&cM)VmzHtRBG2 zCA8IfAVl%|zl@wUkWzDk6Aq)4An8w#>?Re@uG8#F*&HCk#QM!=NH`U3Tv?U6vEX`U zHq_wFP4A!AHP1TO2YIbN)cW#HNQHkBcAgJO$(_=`-$eHQ&aH;Nr?UgL`3}^F#0zQi zV>|ue?2ubkZ)bNjog;9$NfD(aj4*X}1i#k3!0oFj=3nMsqv&X}_^<&*zsP;Wl`Vmv zm|8Do#_Vo;n3UCoO}LN^*)#fPN9eq##|B&=FG2yQ15h@G%5FJICln)}A%i+HRo-x_w zR6CmBPX{q_+sIpA&4{JZMCH})DO(FzQ*ent40j9A7ynefqMS%6iz4d#X>Loz^+U_2kUeFU*g% zr~mu?|HL~>)RQ1J+YN!cxMP8pF4Pr=7+pbX)dA#7E~k|YIyuPP;Oc0QnouAEUoNV$ z-7##8;L%nnrc_BAuQ-W*Wq7CmxRgv+EbNRNz-Ml99NI`Hu4PVabhIHWDwPE^M4vRU(cul zYu%d?Zbfw|H!g;U4f8Jsa_GCLn(r$eTHp2z=~Fb4@&M{ zurNT1!LeO0h`LSh2e`8v_c+FdFBXLAZT)wOVu=Ocpq3L+m%lp4*r%;FSlH*U2-;sd zAYeRvN&+2jF7)A+N9o0^xB0Px2e;kF4G`lvvgXl4s<(F$A}|YUHW&4%P40?Fjv0ao z+6K~`u2b5H+SGDK`~uIE)s2A{_0cVn6)=_?mTg&%N(s`R9YbOfMV% zVMedqi4$LFP%YP&j{Kz(@Wrw!t;Is`K7PAq6U5myKvSlEv01T@GTuo(M0(Pzf6pxM zfiyX<8YBOXBXV+AA?!g`jR$L}R4wSwLJ3W%i`wxty#FMQ!NMrxWWl`7;Z5g%GTYKM zFf6EXRelquXNYLDi46va#LrJfWB_ts=HuMMYk^~}+=S10@1TKx;L}*uUg-D%`Yttq zW{$9_p;n>XN*3z#@HAS}EuQP=WW1ZGm;O5iC#^@?gY1fR6Ga?~mM0rsqkS`7Q@gaB z27F~y=lB9Q!d?m%raXiKU#W>{yN8npoo_=E2Otye^a+^t%Os-{!Ad^?C zqJNqB8}N=8^^Fa#s;?>P+?5&o!OE&7b|^#F#@r3exE@-@cTMmV&GOBs!nG^t;JRZ_ z9o3IF>g4cQZj&K$Cp7|c)+0nT{nv)n9Fw1JKh5OZQ0T*FBrO{KqBjIT@!QcADJurU zeUP7XTmltYxgRTwE~QQ|gsED1949;s`-ECk3NNo)P%*Doxzz*t6#8jif2B?S4NQaC z_ur{|$r>Rcxv0?UKf8^!;*yvgrW+oSh8xxYO(dpu3Tc=3o1CFn#)%jP)6V#k-C zHJLiR^2U+nQEsqz9{J4Q%^jF0v3R4{<;3^+{45Q~PKrY)#quzVaz3|r$jy{|zi?6O zmXq_HV43St$3|Sk^KOtdKgm=qKI0C3kn!+hbbhYeq{vN&%x}O$Y^Vb_Q>6f{vrMRX zFNP03YiwaO7xKx0*lwxMySh}9vZa9UYNP=_gAm{ zm8;*6AL9uNbKW@_F-C0CL_tj%u)f*TsOAV97{{KD+6ySa(#W#RLK2v?Rw0UwhO}#>JIQ(TpdY z?#*lWo+kQC9$V7f=~o#4wsX)WTB?D3gJ@E1?)3qlz}`3y=N#*h)3qzdn~SY>F6!QD z`uq3h2lQ)pd}kE#QAJqv%y>uh^_lX*JmoCzg>7Ee@psoH+y-WH9IxI2XO?J8xYKW0XgJuL{W;-&P@ z$9_f7=08#*ug-fGNouD|ST29Oz5CN+DDJV z+pkd-V6pWOk(Vn;-pWS&;Im*p6-6QbtAraZh$h9_1XQ&rM2+j@t)3DkWo^|bJa@6l zCgIh`e5iA(L%K%t*~J-m2Z^zRmhPLk8e@-8Azl}TkR=E|^4e>J8zfpOnGd0#(RtW# z?Na&8>W`1yQXeZD&`USSsqxr;?%OVT^gKdXm+A1m#<;+U(%Mvebr2`Qj2aqBzDR&Z z(}V8RsJ!0-k8({NnJGK(PVBxrA}Z}bfOghv8G4A^YowU_Z`pkBK&OUGrI)@*#0!eK zds9utrYl7j(T5&65q6V|0O{cyP0xs`bu$&YVYeAY2U4JD)CEmpa)#cVXVB**1N^Xl zgPkJt`!iI%Z=4e73S6#Z@f^8(z+*PB@-m-oRYK*vQ;{pAVXx{oOFr`k9WKP8(Q7!} z=YmzXlSPo*#^jbigbVH4>Oo`iP+x2iwRc#bzIOieu-&Cqc{hk5eR*7b@430P)Dv36?}neNs~H!6;~C{w_P!;4Km$ zQRTLXLHBz89DA+Y*augQ>1;~BiL|-O*E1itUbu5FfqSG9@*=!k6W-uZ;~g8E{-eJO zALrWa?X;wV#qq#P9qP$PU8O}7t@+)7+odK~O6#q9tHNcF2d}Z?T`qxm$uAY#i!Yf^ zhpXx;?F?)=1T@zr8kSqW_-=)if>@|)J;3_b)V7!kNg?PjL!`%gKdLTFzglfVMMBu> z?lTIaW6S@%v%j)IAjObNWNmI~HQ96~aZeOQ$I}!%7)M%~ChGU4R!vR%3sn0;*L^1r zUR9F#3iNzC`hv!Qmv24f|d7;WW)uuqV>!|V$&6yw(9G^I;USs>DK zG1Gi+D}46$Z1@$rk^1*yr;_dvxBUh-iy(hH=@t6>-*F55E?M4&Ra<;Ana5KRk2&4{ zl{L1tyOrzbki^EM2-OsR&xAbs@6-#`NyJUU9kvgLfZz_f-9CrjlFnxg19^496wi9U zSlHqfsX4Ip|M7>6VY0jcF}c{^e6|A|y71ypEUO?dntsyN=zq^1=b>v6=gV#vZFv!C zUhw};A(|Jef6Z)sxbzJ4d-{T`O2NS2$H{-sE`=nQuTb^A_EZ_4qgdIT5+jNZ*m01| zfy1~&aNrV2IMb+D$cd2xTV_IJidhLQ^{A$l=U{Oj!yEed*M{Mj#WZ+L1R! z&3mrR@~pe<%(`WZP78QxZ*jS-o-h=6${x6c+)D^i;?70)T+aQ*0~vt)U#n}%SWCK- z;O%rPV(GKXe8lGJPP_o%awtfS?3pbhT_mux!?QZurN>1^I>RnxYx*0rb!D6;Z9C4E zj21K}?g|h6zS@Qwmpzkb8f~PlxKRt%Zf0yH_egG#G(8A3Io3tEWUp;&B=%^x>`1`h zPG80~%`a9&XiIJvtvYgc4D(EE<$oU~LlL+(Ss~1+A>`h}$jNWijL-|&Mer=`#_^ju zYwwYxVr2E6we25)mi#{IR}YSctAOqRm643R0?$Onw#!ktR}SM5&W&S%O+`r>E)c|N zb=F^Tm*!Gi!=`_(sg_VZ`kul#wO-2He(Lpm6JZbh_BJD<9Sr+PX?R3YI!O9l+?By= zwQ!ul+| zOi(zYlrZI+bR+`;)Q&beZ##eD>;bnfc8pu@O!&|1IA*tZ89Rrk$j!>kh^Gy=97=l@ zot;VZRn0+9Po6PPGXPB=&}sYQ)-8bQ(hBc7vb0(0iWcOVD16Vor>dGH=Fq#7xso3A z>9%QZ&6Ll7r%+B-czk~QPa=jYUbL0{6^^!Nd~0ez@fp z=#PB1fb&%vgU=nxGEz~V*aC#ln6F!0kCo`2_}H3$`F1%8=m+u(IzGAA8)?t2IM}I> zXoY=L-f&QS4f~*or{91EVRm8aP}qEO3x1(D1N6FZ_g3S$^Gwi7+fvYdh5qEofx8u; zhm0>6C)io9ab{n=ODqU?*jdPtW*=*!B+q9&ycc4Na~(G!gip1ad`v z{5mX?scSy6wNAT*>@L(`coLu-8;epoTFO!~Cho(cDbdHL{%KKm7GAB_v;^MSE+ZAm zVP}sV6^L#sz7v(lQNm)d?U?#Au60>bpJ!}cR3(=PafHmk4quER z3~0u7i#RVEpBVPJ`)#*YSFd}m$#?04T#rNK1s`a!hi$WO8PFt|tD=yO}Ih~IwA|r-2QSUI-;v_s^L#8fV zFj)VDu8|(0Jh7g^p$AVV zKDfm;g^{mB|F!7dZC?;(tYKKriUZ)A(_eEBiH@O`Z!!kHFI7%gyE>#bojAvvWn8Fl`{#EMsd8&;Dmy zE2L9I*j}+mG%O8zxA%yX3%u%>EN#FN;R{^eAbZkAtc8+l*zM= z7qG`Y7UsWheIFg$JzRfT{!DZCi>!(K0lK6g6PNs92(_^GH#DQCTtjCxFpDN5YMpGF zWilOTl=!f3-N(kX<-v9UZ1Tom`CsUbm%QW`C|1BJeNlWvJ#I&n{QpCz{@=vv+2b&3 zCkaF{q9i-_dQgPu0`(nln)Lh5V8Z*SY4^1_)*mjZ*}uYaLECigo__%5|3%0?5&m&t zO+&9C;MBw)Lmr`_zS&n7Rc0~rv!8_r_Iitk99#pQ>SjVM7GkuLi<#WWU;mw|PRKpo z%A(TM;#;+uBU7ubBv;$V67lVk-0OgqtKe;5?jMQNLJl_rIdx4$78u+7Vz$}CX_wI2 zQnLJN4+g1r0UiYW8JC*oc9=x*OPeCu7QXTMo;p-r1Tpf>mn#MYorT&jXMdrm-Fs#; z*_f`}i&mRq-SwrMGsY1wZ^H?@ zy4t?ND$dh594Fn_iEM^vmJ{sHV#_1EzRew%x;XL0zxwq*ISw1W)zeF@;h8T293-rz zDLnZ@-0g9Pir88C)ha5Kh)RBiaHftF(f^@t;duRek#^sMWeTcGlAJ_nZkhf(6`&#UAUO1#wU zy;cI$(>@jqPW5j8cdEm3+-0&3Qlr~7KQp)RKLH>=yGp-Dbu4EN zfrY19jhD(5&8B2!(UA`JHagNIf%%4vJ=KMT2wXt~8|@!-w;<}BdfM7gD^{DsL@~}e zo7t{>geP(EvOr={(xlMC?1=FAg13W`ICg>hx_!e#*UEwcoyHxfyt{ggJ>Ev*3^wfBf%Di z_Ui6pf6&Z*p52#Eo1oguyg%1+y!L%L?pbLTMY&|?R%c~DA~er2`PQ(D^RT;2Fa*7MAiI`@FEKmaj#pQE+o>F{^D2<%p)aFI(9tDgI!C+3`3ttaWtd3x`r@SZ(p3$v6P3%TA7reY48D2o~4cv~Y> z?Yzf^)ANxKh0tpc_|wck-%386byk&|v^uGmLjxz&QBAhIC%WuDZA-4Us91vIcUbI`|$TSqtoGcQk+4myW20+9$zhu zV+MCje{cLC+p-B7BpGE~?T1w*cjBT>lDB>?`EtOhDn_jonK_*1(YTG?ZLH*?VP)!y zb@HzZv+KaL6qN|ppx#}A@6g%sGj;Z`CzcJ->$emhICe1bkAzXp;BBuOg>KEGLlbzd>38toyai)}!1SNyVDH{QUb9oCB z-=UX}0hUID`RQpKW0ou)m(>ftK8A2UEO%nmoUxOs&FAbAq}n-^5Za&u3T`F^LV;4n z-L$GWAhPdQnb3!XRGVy{g`ri_%?k=$6th2)dapjTuuJ=!cpckbD!8&gKW%=T-H+TZ zBI33z@q)>mKpjLpik5TCg*H%R+9tnW?-TrXF*TI3$Gvg(tQD>rM|x0*#D>A*+pil^rODHPS~W`wAK_Nh+6uw6CelJ495t7 zKf8%lMqr*arqrkYr9RWSfeM#7ww%YXf_V_C)#Ri|^eo)cAo*Fw<7$X!-0oy;)?fYbU#=-9eXZnrdFtFR_s_%?CS0 zvE?4>1;Ek)_jxUNGCn5pz&8QHK|fsz$Mo3zdyCCtEv%r`M>#vC);8?bcNG&}Zbl6r z&5F-po9dF*j`C!Za5Hh?h!I5&n@NjIQDD!C#Z|?`Vmx*@JU{}#$siyXb7!)4(;#(` zuxN0*;e%l174@yT+~IZ(#y6BJE&%{WTf^}?XS_siHB-{swx_GxpZZg5Ta$Pm$H+R( zz3z$}Ux#^h+C`-GfA=@6G<^1LT4^#@7O0|%ha5hBSn~}yxxk1)$d^zR@ucY}B{@!& zII;0_2Ddjwi&J&a{dbDr^``Cx=uo#WwQ!QRTi)$z`fgL7kmZul(@&=GIIH(kx@JBL zX~P@WJtgRHMhcRb>SaSMpgchslG6%{{4=w((1%f9)0No#?gm_?(5+!u?h`peQxJP} z&Z%i7;D*Tk_UK7Xot&4G2d8$~=J-1y(k9gsCE~_@Z}{&@ozxsVt-V=ntVIEf4(jtk ziojun)s`}Z6_88Xi#z9;18%N!R!+wbHq_UpD*mfk7(4Nexa~JGIOEAEX5=y@(Lht@ zBIrG|!04OkyjEr17kb|^{*|hO)K;riU$I&LU&6h#@gkGoPweHUp~jENW2>#+6>Fo) z7=CUW+bj-$>9ekSnh9@pP`u+s7UrB)+h$o$Yak+lEc}`}K%!j5@ah!NxMq^H zy_MH2uU-PGImfxivb!8~Vrh-vq2393U%TKL>W!2gDDvc$*#&|OBx|CX^mxfkCat*V z)8jYz$^(y*oUt@;i?yxU>ZFQP?MclFdd7Dtqsv>5xY+0&&u%&N2TtqO5E% zOHe$UW`vjnB!s#EzD8{LtYp*@q>;+^yLjpB2(-UlsteJ}k}&*NJ0U26dv-G@=t#7P zjVHf&*ps9{O?eR{Ir^PAMCzg>CvOiGfSAVN}j>Vr2s#$k6_6$O-I1D z5j^?w7W^Ch>Ehae26#lcSjg|R$#lNV{uUoDJbhv0Q@bX@pBh6^ z?5@uYiKDBPc;sBJZgf_@r*li`PvZN9w(;{>XQ#POF48m*?lshyyl(QQG5O;n>$s+- zC{0YE=RsD8>B`$>%9rVFgf;fhOF6djXm*Z^SG+!#mi8NOF!et02N>5kKrFyQb3^P= zLFH?wXYXm%_ec%b)g}?2_}(?z>+43zu3cX#h_+lm$tmQXWy_66o+3NM5}GYi<5&7o-CDlD%6G2q;d38b#%8h312= z4tD&6GzoZ&7#)^*o+puW9;l5rKsSpLR7mfFvR<01`n@CMZ7l zt@5??DQIBohJ0BbSJl%b_I^kkOs3N;0p7x{HazfU#8Y}7HbYx-dxMZ8?_t$z;K;rT zpO;@VT~Zen7Mn zWIk3^=ni6%CUP#|p9bmvl;9kY%5F&7_D?vj7`f0UB)4 zkYuDbJ~V6Vv!aRDQ(AU0Gvd{SHq(ck8NE)s|D8G%qpILh9B{p7V@Tiy@bBbLuzb%5 z?lK(3|8x4+Lc=SiLufB)(PaCRXVc#>{g@xXQ*HcE$Z7sYNP9PwVqV){-=YWcQm z)8`_u9zDQ_m9n~GbT9x+blDzA*twIP?>SxV0CO1hNg``^raEyH?f?tZyO$1)99A_+ z7iBw_ZQw9#Z*xTJ@2s#H-f`OJ=^UOldX?i}`gNIydkH4oF49eTh-YHRLrTtLt5YQU zkAi=F|2byOs;B??g(fBm0Pt7VldfTPZ3D)T;v9NMcVVOta)mjH69RC4)a6CQ#R;Ga z?#VB>yp`9+F@)i~UN!Bh(64r^KbMkpaAdjVNXB;Ma8RG0B*&Y7o2dJoh}Fij@x6Sd zR~m%ggmK(;2}M4&Xy-)Vrzn~>xRjzk6CLLlp5Y!vd_Mo__4&0Q%rvDj?)TNKd&6GT zA*0L?t#!J1DMF&Uv7XGVf~RsG1vs8!a#lq#>voSwQTWY;5IlRV=Dn1GP^GR@99LGd zz5q>>sujMvm~KZ;6=y(0CXe6*YcRgFU$Pz{=Xdg`?adS@PXca!AmKqs{9Eyc<@{+JJAM|ESy! z|C>`^)hFUU?(LgL&P@VKP;(DIF!B($iMGC%7p#;%T1=h1NxE=_)f?~|J3g`8N{&XC z``k*Jy7c*xe*B(aQW};W(&*%_o|drZ`Z8}RUNKNTLiGN=dx z?0Ic~MW+SA3g~7D+Ud)U1;sw8>LliVv|OLz%+vYxZkzIm@RUVv#RMG6?c z73e?Tp2JhrT)fdb@wqc^aBdHxu4xW5$;qwNP=0vi14>$#iimOdWLovzr*~Jn6jYa! z<}EMNuF)l?@At_f{K`GmbD~X`JL{j{zh~mKBjHmdHoZMgq|16?`J&fvYv?NP1Y!Dd zGFRcFuS&{BX6%J;(ZqZM6cQxF($6NTl?{bFscIRMli3%3Acpz#NJsy9YVZ(>)3iVZ zmh%J=TY6%5?6->@hwR%nx%RK#nl%@8B7HEg5NV_ zsfyk*4Ka82{H^*;3=V}X*HCmWvks;hHHC5DFu(WZOFxf zHOK*QS1V>v^JhcfWyCvGbR97h`=U>{)37bBQt24Y@A3-kTIcw#nB>?tx)7bAq)`)1 z@lC{!21;#abFpb3^7UCgS&kuP*BzhFTSSD6x695UbSE_L&6YJ>&#m(@?tkIbA>>zU zx$Yo@_dij6X-7Fw6IbeQlVJv{$twa(>dOdjiufUX0;vW$Tut+mP1gJ*E_0;y520PN zfsso0z~?4~S;m;!#!6Rz$ojf+M?>$1da|A623@HaZpatbTBNh6S3yF!9-0k@kj z5Le*GMyfd@C2Q`(N@y3Nx)9zg?DZS}7|9EAct(+(PyQTQ(KT(NA@Y+fg++>!LD4o+6)UyXQ4uM+~W8>9uYrPxGHe67>g?k=1~qI<=cv zT-GWTMF( z)_(Bs>B~nCmiI^&?OL9gn%-oA-kzLW?d`Qwn#vsC8Y?Yd<>^O6@%pE9qm0Qb2qkGy zWyz5~0~@nDKU`GZy~HzZLbKWol#9dFpu2J}W$TWq?X1>4cX{i4S27JCa+SU`szLaUk-N9+w{1G3%+P-%^v9ss$DDL4-^~*>#v>H}mx+Xp>Y-_{_fY{t2 zZ*qC1Nq44SuEjjt?P#*pJ{KNF-`q{HLwEVkUdLaJf4Rs{R!$&k`hDVbGfqL^kcxS_0=&AslOQ^96e2erDcG9_3(Z} zuG2m*FpEuOUWR|@u;F5=kG*J^s%<1%6ZvlRfhZ9g(`m>_9FI(^xkx;F^h@c&@vUsJ zxWDZ_g1+>c-XnF(JX_xAla@rK(mJNz>K_x4p%PbHF?D z@s~>xD-R@1ymw9;#0V#!hb%7|(y68~IOzHKvv=mvDAb#IM%I5ZUh~sb16~u8*F5ppA%&h}+`Jm|LAKZ|cAK|2$0f ziZRO0W=UDT643fyzK{E3xxdBt!x^cDwm_tC>LKL%diBf?F(bYkC-UfU3Fdw1MWz2v z1sDH~P@`E~2Kqf`;jW9*?1ICOUSEyzKqt!B9gFe<4IAJ>dVBp?1a`hWymLqA3JTf)Su_Y~w&N1iHkd_wt`;Q1HYSWqEj?YNk` z+7);1uWo&&XhIXpBL_AJ_sFf^&`w*Jx0uV|JBT~&6Z>pNT`3!2)+;uXtD^FSVc~xN zE;4va*K1<$|5;hh(NG@%t8n^&)s8FIsNLU(WLFDR4tf$L z9oJ_SV%nJE48;SzZW~x6skWY)Ep~4}tFG!_`wOSu^*T|fS71?rzN`oxYQ^=Qklnez znXP-ZAEdlpgGbU8=juXdFjZEW&lclMc2>jexGi}q`36lbvy}$8=oO@6kOLfa=u2tn zLbroi?kQpI?WL#jJXS@TlVJGBJ;j(qIeJDbJ^@}4@y3DhBMdG;HZj4 zsb2(j2keF7z6BW6NCbCoRZ94areTp=pU269?SW>+?Vu;0=$;ed(a$Kb#QrHrzCeiV z!=HpY>9x5a0VlB(hjdE_PBh1(HUd^MqDVhW@t^tD3VNOb63-_VAkExe%>*-^U)4b# zu+#x$t^)Z`YSu}He!}>*Z+x@x?JmoY3#)n;;~3V|IWn{d#E)d5iW*UU4y8{*GG38_ z)Y)Pgyy_A zKmLvQWKw3YS|o@YI!>@K3|0 zmY>e69@YKqwB4i3mYQrS(eGx6qBawKRF-iKKv!$!jI>{ zNCbZVUR7o7y0UV!IYO#$@LRU~SW@c`##|?L3jL5fi;&-6I=l`Zc;s!n!Guec7@QL# z7DQOn)Zi+3OyWU2FiEFtXFJ-P%rkO)6$jjxX_%V_t4)=)-!^YsI*}R&cx~A}zL0vZ zRLmW;yM6=;L?|+H%$8a|m@rj%PbBoZLRh&??~slTnHpYuxX0AeuTgbLVmuXMlH zP=eRX$9FX!-PLNK4N>nDIvU;TUFE{lCf$1&p}cfKMDp+4Gt9x+hEBQbKp%jxH+CouRwc2T=0M{oPefYIb2xp@NvdzryyE2_fq5G3#nxJuf?WM ze6~-*Ku_^WF1D&eoL_+Y>?Gf$xYTsXs)KBMM{5bPf z(EOjJ^Q33WaR=>vt1<>MOHb9?)rNvX_;|bUHDz%A_?xK|-mv z50+t%V^$Q_3Q;r6y8Sy%1br7qypomN!F4CULfb63`R(K7**Oj{EQ_so%{oBaq(O8+ zaiH7fQ)Z}xnY4~Zzhcxh0Hcc`P&9QokXS51u@hkLHh5$ME^?`#ee|MGBUb*k;l3(* zG&dS_p)UD#SlLNMDe*@|tDq~(qlT*?@8`a1B;h`WaH~qIA98%L&kW1)eg8SlmjwAS zaCJrCUqb<}LEzXE-OVLJ;x(lRpm^}zNxC$_UUv0(<*m8hT_I-%-)bvUCb(buUek+} zH&?i(hnf*%{z=o2vg){n3{ts@{6Ll+v{Z^V$UwT_mR5Wm0FWr9DW z$E0#+#PP7MAyH$B3_j=fn$?%~ zKtEMahq0?0_S0TS@ejy(uspeY9kAH)W%Xo1Prt#;W2vD z0&*bLvX>{;DFWY{#A_{f?2@E;-?Vo`7;?{R=4)|(D{-_mqIadK{US*3-MyfBncL!0 zwzh^Q1KaLYr^8BWng?+tNqg?$N8>{33sr!HeOcP-CaXt$L$#cfr+RhZ>Tp=!tFQ+Z zg^6gY_anuwF3z^IZxh0l6$+aqbh$mv3vt~iihuX!MN~xl{0IBfH2PDIGN@CS0L|RP zMhfq1Fdu?*9PqeMd}gf6v?h9_t8nt=o3$-4R6uL6FSF7z!kD~Y=$t`uURb)^qg03& zxrXh1l99B9Bp{1ZGg(AKe+s(u$IgdOZkk=2+W(6?FXE1M8^6^A>qMq}>HK4e{>8Y& zC{G2ni|>@@JoY$$)$cqa#vOyFl&m@rPb>*S`WWB>f&QDkw#}1F7ajKnh$lmrjGkbb zTWc31r`jDwH+-xU zQBQ86=YRyWp(_JMCb-BPbNePuq!nSPqU~UBPm^~a7swfOws)( zq?h*a4#uF>o&bw!zeJvX4_5L}@d)_gB@lMId7IyD=G_zU(V$<;x_zjF#?{HN)Zi7w z07bL?PM@D&IY1vL9;d#`T|iCH=NQ@TH|FUOYHkr6V|&3Xd|XT=hWa|I6xe*AN{8)v zG*vjnoI1qb)2M0eqX}8NQ+U|&y1NUp3=VU4DPECH7iS;1Yu$}onfOaIe?PFNVj87P zG`*r8VhiG8j>0(ZGRF4zjr3he;^`(<;m*1Jjh6&pI?4kI-Cjk{jdq2g zn>8;PdpA2r*goRP2Pz5X3}dd(Gr>+=6CsNa_|LY%{cS`xg2k<`1`{de`e~UL>;mjn zjqfCkwD)P1Y757#Ofy4RZm64(mbeLYW=!r8K* zSV0kAc)@cYjLlrhT8(Q6)Y-{9klWg%!Rabvt!MG5=>JY}k$k-6p7j^bY2S zgwZ|0B94--=6-x>@P1OnT3DA7SNf`4Cu|N&5JD=AzHFD8pPPr9hX0s;3NNpJTz@=k zZHNkP>m|g{xsp3FY;+h!ov3poj%DAYrHp7ZXFD7%2zpVr8lPARja5kACGmtr8}Js- z=GyNc1RImJHQ%1x*|WU>s35yPup`3q;LZm@9rl?UyQkR_(pReC+yvH{j;#ylk#mth z$2y-Ri6nQ{t7dsGBz$Y>`rmpd1YoK5+dy{I4|roxmwcacT6oFKgW!MbX9N}vMqMt2 zD|htyKJV16qxBq5dS)6>=Vrvs<`^;UW@g`~dTm(#Zm zfn#U?{<~RY(dFd0=8L48G+BcHvPzG`t=8Y1+vl2d4QeJnlV+vzCe!cC>@97Bvf*xT z0T0Jb{Ni_|Uyimr~$Ue@PNDjBISN_jTg%E%fe9lB8N zKipPAo$k(vc}4-}hm_jCVr?+19o7Q7$=GHVB_bs~MYv-+nsZ~7q;OZ~8q>AZjerP4 z;V=#s@I0Ek`QD12CdeKHpePS3cs$`k?za(qxuOlGb_@Uxre^g*#Vp2rm~_WZV0ut1sg*v^nnEP~#y&Gk!AAc?8?ew>~`ax&5m5{(YM$J$llA=XVOK5BB01(J8X z%v)@COs-ZJ73z0GFtYZOIrjP8zRm7Nti|t-Tj6e`O&Y5Qta`c=a|YhaoLsd=tW2HIxLOLY}Cs4)wjB9Pyaa|p4{m>vqJy?)9c+i zH>e?nviV+113Ik}r_-Kxd4IWtjW|3u=&d^ie{)Vq*kP$|U-WJ@oWCv@c8ACMv#IK!@x)H= zuwsss!OMW2`9W&o>1Oxo$=3|8qq7|fI^vzlS00>ml^0Gu(-lG7gvG<(0e(0ha*8M7 zou2@KpgB@U@K5`Q8jkLYe*f(XZ-ow$eH1joY1uTgagTKSaB0dl<37Ykex%7emPP93 zafj1vd)D35!_lVQnOew9Ntn=dFEj?m#^i^K_GaYpw1s}1@TDtiJQUqdgMJwiXY4D& zCLX^;3sf`4PIEIXqe8wXDDE=tGGxxnKLDRah!Fjv$p@M-HM}cF znehS4w*g}ttwUY%;ISCr;IL*MzSQ%%rmXnuVM|CJI%`OX+tVZ*wy#huCBy#j0W`7w z9(81CwGQ6DixoEETG*OX#P;=VAVdp~f8>FFoN_I*lkTs$Moid) zm76+js-*Y+#*v}o`VcQ+6JGn>1*!>soB7wa)Q0Ab2E5rf2h{SdDN?1y*t0;Eoun|X596E<^j&oa?aMz zkgn6;-`{Ob+g~|N94m#E|H=QH%5k|z(37q4h_B+3WslOYk`{=~3lN$Q!fy{g5Z`mQG;Ly4{2jdsD_pHCg^K>1w9)vr z`u#wW zo2i;__fd+#{59@^-SJT2YQN^z0OJ3})ptj;8TNl`wbi24+M}du@1pidTeXYYTWXIO zRkcZ4irPg{6jjs~dz0FGZ?R{KkeDHnzW4K--+9+RIZkpS$#sA4>-vt*kPKZ%Fyb77 z$vVuc=&GZU3{>)IMk2vGM`oTPv|BnQH zQ>e}Slez~A{P~MbYtpLk{uZ`mjV!KIV##;i9~&3T>)lZEby1o+~M|BQf%c zDVUrV3xJSBpSpzhPG}t*$VvhG9jEcIU$Z}%SsL^o?X*jXx{DL+Gn3Y zn(OsvMJRZbM$zmmzmiJM{k(r9-tR2A1fR~`Y%MD`>rOP{HFzw%(Xc8qz<&w7F8H%I z%dc-3_V%i@SaxyY(5otHH(IBp|9!5VOY7$aX+%8ODgI-Y9Ip2&+j&)oVbM?JV5l+C zWHaSyvNWj3On@!Gi)<(mlHIK%qT_X*BI~=(XglzYgfD-K*%Bh7IoF zqkiireq0*H+Pg~%)Y4AJMV8fnPy$YFwDOWg3<`$NMzz~&n#!|taUYbgD)Y@&7!`Li z$p`fRHh4mYFx|!l`U`r6lXCiPv0u0Rtmm42Zm>Li2$)Zo64;tne)ttVvJlGP$PGw| z=D8rpYqRFc&P6u1#UI%iOvt+g^Y5lxvTuyoRcXgDj_TTHBtIg*Gada@U-FAP@cB-vOL0dadd565#LJW}iyO>5=A4VHZ z_)9`qx%>Wr(AfmflFRBa!n1)28DIwzC;7GBCLrXEG#Hh9>u#*Cc#NZ3)6!hq=`57z zSl6=fOFSA-XIy!eSM%|6@550z%F&=POi(ZQ~|2*F9VRZZVq*={{45)hboKIhb;6SliJ2zD_&c)`^jQc|GGOKQ6pI~_1{ z*mrH_p|rdx8ZtP&qnCT0AIR2ZY~&~f&o>?Qmdw3d{M^$wUS{L!+sD*Bi$v!X>JgE! zri&exyaiIJsdGenw``5elyU8Ho*S)8&)SPfgOJ<1u&=M&+)d3!zX%}Fhkrhvkv%x;J8gpq>MDtLc#1NYP_KA;{%+7EOxWX*?pp?@FOL?ru)hK|C5B-2 zA^H3I>Zb7Dm8kHh0*3>GY?X0|W|N8Co9WUSyrsG1F5jC}GHnHxm8r{yKJdEb{yaf^ z440z)N8-gN7m%R48;I;ELa_Xnon2T|7o=9(iYQ2tB^qvyLyfAI)E`%H*55E*#@=Jr zx%L8Dzw0?ZA(&hEH$bt3(^%gbQ`@B~!29eWOnS-KH7|;b7n?$IzKxW~)Tn)w%eRbT zea~HHUB5nXIfYWUNz7ryh)o5||=x#3B-x*%UqJZ+F;oseKQy|+p!sKPfslcuzV}9-hv- zJY(`;LYv8y)Gi>XqovTsg|D&04a}kO4yr`H_i}vG&%yk*^#cq^ED0z-hy@EhQ^loi zAnBI(te9|VUO)dP)ooR-2;aZF8)k&mUj>XoQ*4%kdQ$7P%q?9H+X}ce+!y579Dl<4 zR%lW!LMTQ*pU={##Du>ydj@iTcrUo*l(e&=7n;-lQ~vten^+DumqQ*WiV^7CMjU^q zgVpdG-eUQtX72{;B=x!j2lGDxLizJqy;>n7?_fT05-(OPbJJ@*p+a2=-6#(ED}keL z(4m4KieD$TJ#a4t)7K4;AHV)VGY`|fv}y6sf3;K-)wsN9)B5V@d*f6~ zj8lp7Tu-A1CzUAq@p4{`ohZHNCe3&wBC&d_=_#^FFl8q3c?v8wo=sY8QoWb~kC##Ly)uQ4s=K$ToO@$pJwdW9#Spn|T*!t`~c* z{SJZX zPkvGVNLm(85QW4$1PQEEs34uZ@wyB_-6y`QTD)$!VPkshMGMCp;4B>R+%-QfE8OGB@JJq>lX8k~hMDm_8dW#Gq`T+w zGKiYq@#2ax(E`px+Z*%w%l&m|>o`@m?w;t zqr2<=On-Tt{m~S!djR2Qo95LI0QD9R3euihn~@ja=x-6tLlu0*qSCJMOzjK&BgrxT zL*VP8#W2N)riF>PCe~)dG7@y9*bMgl=)>^zekhF@A#Z1*fL5_GDMy^c-J=cs&~oyn z+}i!>=dMi|!Uch@A#@E1&s~Mdu)c`mjV#{I9e(N#>(+P?4{*aE`FD@9ktHkIfvS&v zH`tP+i*XKaW=;s9HwKxak)AQe>o}KMzA3Y2RvNcIfuN2H5ut(>%|fY&NZK0t_|&4u z(bM5QJ?qO%q$stm&#cCth^8*)2eQJJ+V_A^dvDbnAuX+gt5gfq2`^EO#>37>aSQ#3`VBW zzO+{5G_H^7oHlXlr||ZoALmHCsa$8B^+ZJ=BjQyR@M&f{SQ$Vt?(x;z zW)3C_%ycO|*guGs(VrTq#Z$U8ghh^8`IR;wk~^jE|AY>jT;THI1*2barGmC34OB56xer$>6MAF&>=3WG!kHT^lJEqlnFmwd0@V5VoB79Q)?~ILL18l037|wf8g~xNF}91N495wq3^p}q}rkaRhdkS zmo3~5XaB%;*%f3ZZW9SxdmBz zjm$qxp!|9^F_P<(B zl3BeV-F|hMrl4Ji2jJofr2Pdo|C@*DuW6-*hy5LY5~=O?(Aqv^0;XyMSz9GGPn6$h zF-DAHv%VzAJ-#SvAWEDtL9n_T4g%+N3RFPZ>cTRg^jndx=GmQ;tpycuAo<-OH`3pL zGerMzK-v3D9!s=)Q6qP}X&1Sd zdYMXm>TSlmhg*Kh+}{-Y{@_I7k2Sk&-~-vGyUt?3xS3}CUeQmjH9V5qO5K|077bs| zsLr8H%k~Iw8B4AQ)G7+N7;8&O7Jmqf03YQr=Gh0{f3o|uNL}?w`>@IeAO>&p2VE085W?CYx zm*P;nAZUn$P^*eg*-LM=-1kmuD+wWi#xTop&l0c9lJ0El;A*XmGkvUZz8IZTzNlR8 zTS%PF4kR^YAv~+f!ZqRcN-xJhk|@M7weI_WBppcoAlhe+e@ESU!EbWyS3elfXv$5Ss^m}{uuh7Od1{mUVxHlU`h zoMc710b2>ZOgit)XhoLn&bORKQrNu8Tptc_rgwdt+-%TOK;LCyYa|28vt;7<$o6k~ z987IFqgu2qc^qLrXB?6&JPgqv*v1PN_+6&t`^=_l&pUG`dC~OxNSrhL29S1uu3h{G zd1k>D|FyM37iT_O@O)Q`)Ej8MaFIraS7~`r#6!D_Z~^|yEOp~~jlU~y3|dqwQ(#w* zd2&sE>(F+ZSDY7W^q#!nIOy@tI!{+D83db^UxZWD*5c7feC?KF#q>aRHdOOT&v=p3 zSXj2#y1e3=>)ti1(&HB6+L+|T=71$AB4J<`CN*1&YilprlhQZ4emi!@rnOnLgnpqm zb)LF|JEoWEhVa_OtOAeB9#7HLO;wTKx)xt2)Zz}UrbHyoEp{gs7f@epLre#iK{^dF zK2eq6NVmLLrKTh%#)SY_ZPlm4k@-(g7&SiSF`4Lj} zs}!D+Qf<#PTsnXm7*L8~U7Qv8>1X`gihdSxie`9KHCbz^^}yZTI!0BnJ-}{8cuC9P zy==n!L`O=NtRGVjyNsWge=|4#dXt>yGK1z$a&;8E`~HY9CV7zIU+UsCK97th0?lv&7@>9P015<&Z<#n`a+4-OGK> z3yoU4CM&0Nb7|^tZ0D(vaXkK>78_~AL>cPThloUath*^PI^E&zf_n@m&7tLucP#V} zp~>-oz+`1?JRS8*fRS*1^^D*MAY2hf_K?Q>0n|tIdYel^!dN^O0WcP~3j(wEEU>ip zhkPzi_s;gD(kL6+S*a$MYgu{}ANeWvJC<3Xl$#G!Fk_SX1|_Nos6t5 zPm$c9WTXs?gK8RJ3nE+8Y0Lpz+gS#T9hI>9QIulZSt+YaOH1URcTD%8Sn}(EqFfic!35A z_Aw-?I}p{-p7C6zM2&r-#m4g85ibkW9;2%xr(kk9F%ZNR6nK>nVt6000t&D1*kWiC+5eWnz?s1R5bv;(2PVC0qm6YQ||>Q@R2U(UxN z{y@{-lD)FaGg0fQb<@12^o^n9%j$=f1e2Kzzb3--&4pcY^B)|a^8^z9_@uut9-vTx zWymYu$_tLJO^EjhwssvBm)z!&&+^)vsY~sW67@*wxHPB6-RNYGN$9ow^~;bszR6Kg zn7+n>$06Y(=*(qNVNi2>V23NSN`0ef*!5Rq!OL)=0md(W;H!Yu*KMVL@-QcVi{JXZ z#OxWh93(s+1xfuQvC5A&{&*_jnDF)Urpkqm0@S0*Z+_~pAgg5nC@;GMkRUc7EtS8;AWAgZ6m>Mx?O$JzSA|R~BybzmCjpUWtOAmygZeFPM z1Z=mtS?~HNW-k)0ZIPc6QK`rI%wNsxwgN7vOP?NACT{so=@$p5wfwO&uwFEzXw`W= zGlIHOan8MA&8%NR^~+~ApTS7fnNjs-m^YoeK#eAC1?o%X00Zem=Bmq&4Uv!2H~Sx2 z@K-06oX~xxGrSeAP3tsZHGaa+wJAz%{pHrammx~GF^jBD_EQf7SnQ7W%AmwVzR{Da z$0jZkoLijV_Kd2l8C5I{yQkffVK4H6p+lD~=t_ylb&U=}HmIaVxNN3(v;`;)PV*Xb zDpc7^ZXB4BWL(FwC6Ha_@wfi%P+61VL(e43Z}JkVx|WQiDMHzBSm*h~=uceR@CE(s zxOIe56PQ>VJPDbZSNz8Bd^>$c^HK&^5JSZ8Y=x0-GD4?J7f#I%+p9q=tnoq9S&t%K{-mjBYryx_h_y`%3+CRqX9j_OJ%IgC^i~8!+8#rZw6I5((MwRv)Sypy zi)dZ0_tI(-M7uufs{YvF;clr)G$Q#~2&8-~HB)A4uNd_1b3ncT5T9>@eF8iRAKh!e zJrGRQ9vZ`tF)qDou0t}uzgy4P_w<^XXs|mf{6Ixo;;mNDyulYc+Y+M>#{MF&@*TcX zOZV(1F+9jsGiN80b|ER-Y1+E)Lzc4lDrMKmx|w4(o#auJbJ_wWCFPF9Sv-KCa~<|* zM^-1t|1J@^_j~pd66w~W>|An(ys6*4eN2}3Vq~kwm+I@3#}5`rZ7&)SFcv?n!Hk5i zA|E)N!Pv%6oWm9?7Fy!m5%iL=_CBzvLUb(&k)wYDbhB7iay92SL0Qk}ne6N4xcee( zwPxRL(vlcY!K*xa(T=M;-AgQ%QhM=}y9}?*_fo8p-d=XYwdaW74=JEmuU{pP@BSmf z=w^RdAp4D2p!UWD?TJLRK%zRF6krD zKvTKI1k=4abJ>%*eph&X$;NV?zid?J7=Z075S*{dVY~$SiY8o*FuH|7sDo3TwRmA+ z*o#r_Ra8smuCec6mg?i8R!UoUhahW;8nIsfQ==Qf2D1mqj_BxM)ivW!%dXQ8T1SCz8scc3~LN0sljt4CUY$p7740{0NqYWBYRN&Me` zy#ZWwS(ZCI7NG0FJ*ng<)ZKS}QE_T1;`rWPyiSs-%4}fTSHkMOY5W-kbS4Y?3{0Hk z3(Y7B^CCy2C?CWLOo1IC3nBo`V%*cS;ID4|X98Csuh?Jx#_K%pRnLI@b(o-ZkiI(f z1Z0}uH?Y}wCecfvrP7+rX;q}aLEQ3oJ(%Xj``M)GeIKZls=yZzAA)q(J(vlvu$)9G zTtZP@S@FnQ#zKQAdF(?cB(E|;iobt}ylqB%zhP3BpTGPc$r2xlZ^1yj66JN#5$H*j zz|s?!opB^ar!G!s;rO-i3J-xp%87whNs9us1$mvluyZCbaayv+d!nU15GauL#+iEf zOl_>um@l%CiFF2KgY8xO9J&oR2!0DC{Wd72f&5rgXo|zV4#BHkA|Tj zRg^;+Cz&3s*XZBC(ZSOjV3Li`MNS=^XS=f8X3@ZxOQ7BuOnNn=OQy~|`WAdXG&F_E zMme5I))||=AGTV3vSrluoycbIZQU0CIv?K;@N-22y~oa|=0neZ064rSetRYu)ea#V z{Yh^MO{&^K&p=o9D5u;n>;{Uqbp{o?WB|b?5bsRvs)7c55;uWXS$28}Qum)}hA=xV zMsU1u%f;88(h;6?*uEVbR7h>Fl1Wze=|4ca#?KA2Q>ME&d-FV}HXUFAa9e4Bd>>n( zJKPn3aNJpqjE@LXmUHXruDUw{DCi1If|*!IS++0E`$C+9RHkM_$(=6O7@lpV zkGy&r{O~EN`efJ)1T3Vl)ApFt<>ZUakYSr4pdtDD*ODa|d+iU`z+dRD+&Mc0MS3Q~ zsZ17Lo0d_*47>B6%Vzd7yDoJ<*je?)cfwp zFIE3-^Pn{N=DNs&*I7{LSzskDzsRX6bMzy^qvtz&)Z}~2NZyxj`d1&5@w?NjW?*z9 zp3ah^z2I-t313#3Eqnjv#n99-g#1ZbwZTY~AsJr~Hn(R7{eXp%txZ|E4!2Gqj z06|vtx2~!HZe2C`g(P#=r-yFlj~Rn~)vYKnq*PE|xyw|vOu*-rI^=#l+q4#ssh|vr z>6>gqtezCQ9?!4ES{m_U#*QSZ``axr;?V!fSr0=WWA95-kg1sOa8(V67~-QtWiTVv z(!I;(Pj@iK#p%Sw>?%R!)zps56YX9WScl9xiz7lW^`nWJa-%+SD9hl5v$ zyZZzBit72Op;F=dy7I{??9R$vi!8#V#1p6wbI==O!*eSh_0X7X7b-r)y#wP+g0>j3UEM`>1p zS3F^i@;4l&6(9uB?E z={(?-zb^Q76aL#>Kw{OM9(icVvNANeu%a0cK|#-6ut@rOS-Dbf&cn|x0XCgGXx{Xt zl}?!V{7-pt7S0Pe6*zr`$h8|?GY#s>cF)Zf;|8L{-f1g1i)=QZRY~YOMD)`Clof$4 z!wc*_KNM~QLB~d-bPY^j_)_8Sc6;gkj(Xs8W_02}80V?JszKWE?tjwv16ze{^xv=j z;s}n<9$j}?175KG`#8j3o};`=XAxwr3>GOz#n#R${a$1(la;!tW*TO%U#S<_PxfF; zBXF!Uc@g*=K>(uN$RN93b^q;~C8-d?^OpEiH=8u@g{UFu=24T}8j?nV${QF^IwL-S z=vu6ca2#u+5r+hY;tVDKy30o)>%0)#)zZXw%^!Pn&JbKvNVoWTM@_6`?%EDUxN!%y zG79A!pYNhJ4u8S+a!Iz5i3|swNR2QdKQX#C-W1o@limDN!~!8c9p(BR{Saj&rKVf4Sh84QOHn?g_=XKzxL9uOqTUMf&eu*Y{hmcrMqT-43ylhJ?8 z`rrgf#D33FSoX77Hr}3%U+&6q^m>vGND&u`$HE@yAys!^WC zWm=Fa7j*(x4&IhHbjRjMBxM7;j-fS3+Zb;$~W(LXD|-NlM@NBo9Rm3j*(JV)C# z*?Kxx1~mk1mh>&{jd$WC!Uj+!9)4H-KP?=GwN%GXr}KS(`t5!I;O8>k2n;DD;(*9;7Tu_Kcs6zQ zZS5LM`@+{GSB{#LF0A=1tY3(H3PyNyTgOz+s!?OL~xb|9h{ z>eIxEf}@R)wTS(qpr3#WMMnTSv$Omx#@zn-2@4PEA4%MFrs`SuReUL|+g~`TbV>0E zouHkf4t_1qkm$XOxL!e+6CZo@)uTne?=y=8?(0D%~yWc^r71jC$S0zY$Xx;r=9x`NNUg_y3MXF7FVI|RQQheu3I6HnANWnM zbM|~E(5-8RN5II&Pc6kEiF}*&&_N|iaZZ6W61Zsf?*oD9oHaH`>L4nRHCS6pO6XNQ zGjTS%8WAq2K`G&X8Gf%urbt*`Z zmx?Wf&JIC(dl6@Hv+5ivx*~~QbR?e3EKj>Gy;=Qgx+>}272N-|1#AvkHQX+xq&my# z)T`@Q4-S1*dn|?_PYNo|&CLx=;Zx5O^l>cu{0_B+P}f|iffdC&=X9&?q% z?i{F|hV%oW_~Cyf@mh7ospFRq&dq#J9Y$JQbwtpPcmb^{XL<25-lXqWpRZ-(D5ndY z@dmKLxAFm*;mM_gygL-GFi4?u-E1i_ZnkD&aw^_~^;6?j1=7AGBPDC+`E=gb7m_QUG>BJH7{(%U6=-iQ9A$o{?M!H_xiXD$3=jVu2VWHv0=C3E z6%BnF{8=T>UzEJm#M{9Jd=n%F|C%k9e!nT}l?XrL;)K_p?-vO7)2Pi>?c9Jns!0M1 zNhsN2U)5rz`KX;MtciaE8~Bm~o=@-kwgH+S&L;T(6@mjdK0u6Di7vUm^KkB3JmOG5 z-S3Wu#`rG-{ycRmbUa=x=_ysN%Ma4{^x-G}NOV?=8%WCO+5GF;GfW*(Cyx8g{f7>B@^6Fp`Yzo*JtIU-i%F-jGzij=kVNY62Nrr3G@}MDj(U%-? zlP{+oE$otO@kq-F;~WslpH_u5Q^l}UQY_WH+eO?;!$^` zr1B$6(MSKcym7=Xs9tKnho>t2xFeu?*}_hY>#JQ?ltu`E6o9nOG?(BUL%LMw@IqnQ zTH=1h1)z)0Z<6utDXW>XS4B@#z#$=BqYD_mPG6-R%qQyH-mCo9qk`gXXAe#Zz!a>; z-CaI`iA3gU5&9B*@eo1Z|sUdxvyE@;C~2j z7}ZD(`I@6AF#os_J*5uF?~l$e!PMoc0!+$Zl;x2suD~kYkgfo2ad{mu%kwQ=P)pbZj;*RNklT}1{Y;QbcMuA+%C+2(0Bp@PMM{)WmgQ!QzgYrZjSEk~DC5;v zd=D2=KS}8RlKblaQ<*E6Dy6*4N?GUTTa2&4KvI=L^eP!z7q1wkgXJz*U5N@q z`J%n4W7j(6)HqWw{f`9aK1!wfHdhxz zH&oGL<&@61E`2t)^w%Bi5g)QLU!YfuF{<=0>^-UxxbcXpG?s@rX!S6Nty6n8gbHet zc2x_bUHXe10A%rbgx=+6(c`5(4Xm#!iFX$}*lTgtflq9!)V7}7MTW9Lb#S2uxw>3h zFzzT{VfBcI)}-#2^_m*GJU=q1`z7_0$O}k z!3RMs|05ZLE)}fSG0=JQJ0D$sGbmm+tGudjW6Yy+7U|TS6BDa!->h-F6d{HhxC3Ip zI$;6I#hL(SYhk~i!%dWD{s^pGeseX8hVrVuDl()?DnI@`<{WK}*~YJV1*t`J)}K9a zPZ4!sw?wU>TQ&0iMnjORIczLg%eHEX!%kLnO)beg+$zrOp5PRp4~hpAMo$S6oto*2 z!zS|vE`8nEL~{1E!&`n!Z9UX75lYJt)pvau7$5()2V)zqTztV}yJQoiVo6;S# zw(`2Z3E!AD@gS?1$d-Bxf2>#)@fTU29qN9-se?17?xyujlM4RHItOw4nqGiLulB7| zh;+_24{V8gJ|IJFYn&k0sjYKvwIxao`bss?OWC-}yY!{W^nh&AAY> z@xC}8zk_@Em|?xwR9{Qv?Ic$$$EPMR(bveGi(QBzvF5GhG_Vy7xnS0YlSeN!NDX6_W@H)JS%)RAiyGcpEt2T{66NsaA7CC%Bn8qR`UbtvcM zjW0bqO9bX^86A9{{SF8o2u?+huVF=@+1E`_45Tb-JZ%3+xM=!qwHA8fL6I5tb;+%! zP~)r0lfhW-Ju}RCsOu@I!!y76impIPV^L>3VAQ08dtUZab@ff~? zsUbX2vK;P~{rF}a_?C$a19cp&2q>N|!5Qyl0TIMn0+c=2I0(a71!fZ{vl|P(NB*t2 z0=8uuyq}j{mp?dU2xD@}(xaq)9hyB*-j4S&UtoaXjEwGhoj?B+1~j+hURS*YexcM^ zxX@p8{&`hhCEf?;(`}pGm3{XS`5#R>J9~~XLh`xJek9hT6GTs7wOvP0_&JQej3den zbxa$YaXid;pgabVi%$e?g3zPd0k=ovs5`j3$QP1QRpzS1(6Ov&cBfOD_2@pM`jC<%9Zb!!;G zCB;x{kbNz0kp!w3gfJ%Q(=!W0D|S3hM_fo(ON#y4jV0OWw$bNzFp>R8=lZDr2JAkADa>zVmYGykulXw#1H=d8Pu zpoO4du7in?3l7=CwcdSxMQdN!JX4piICCis1nZJ@n=acqJKd^Q6s6JO0O1%rZCWXx ziZN+VZ4YgI^W5jFH~Ma-m|lhP*k8*hFk&S$3iov39aO^hQwQbcKHb#naaBRha#U8( zEla62V*+(=pZEf9=b3j>_OjnsM~qSSTf{`s>XT$^239@Qji-Jq3IkBXFgflmU+>u$ z4_1*luKXB}pk>8zHs1J0(4JSIS9h3VO&~V_@k(LgA6zYgIm!0RjC;$bq(p#(FNmaU zVyh=8kNjr|gS(S)PyiIvS{um?XZ@qhY56<*K@rd=Moz!{1HouAg8Fnof1Z8(9t(X- zI7jE=!IZ>yXwN;~(21Y;1e1CK^)DuB_KnPk@-4S4Ra{|QFkReqbEY`)ju)kWGxjX@ z@#zhhLvHY43NR_F7|aR5I!2m%EC^gaM*sQk-uO(bIGGK?VY~3$?wXz}UmA zUfne0tC{dL9s+gNrCgHz`pUiMn^zmcKgOg8q{9M8;F9d0SDQb!Z4Yqw>M7GB7JUom`XzzeYlA=1^@q&wb_uaL0@zuy-=;Z2 zg>%}R#%*XrR%))1GV4y%i+-2fhj!!({seJKHjjDJ9MUg8zQ+$#eiv03p89hpGe@&V zh&yz4rID|2om8A(b%_0G{?s$O1?Z}mne+P<(~Xw?qqX*6Zf^l;^ee zECUG?GQdndIaOam*0oN*%+A8Cei4T!McHIdS_Picqu1NuV)?^5Ddk1kI*AT+6((Vy zJLELvK#%Hbfk4V>tXBfcPEfdK4An{GgMTETrj<+;dEmJlIch@`>)^Ywi;g2-vq$NU z_Q;+)+n!3SgCCR`@f^{wK!6-VzrBGcDo8r0P5WX~=F;5?PM$!p1m63rF}5p<3$s1D zNjx$H+8eCH6xYHbc7I`fo~p03+SGnG%)(a_JNLI*RC7U3*L*B2u?P47s`C;}n!O)Kx1-W=3?`&vcrfk!0X(e5(ijt2>l_jjfUu&sZrn% zN<0&C&5^1^xki@;>?ncSn>~ROdoOArms4y>6s)sU2Pe<}*eO!wEJE!U<#N;o{S$2l z@AANLqExq(%l^pOTi7@WeiwZ+W65*2pUVM+`5zYNQZ^4p09Xaq{oB5Zja>ZlH2$Ix3P;r=)1dK#5>PRc&9e7QV|;$p>BbZ z=n?o{2HInynmE$wBL(B}RMJ(Zk!hAGOlgTd|Kb8?n^CnAKAOuX=KD!E1!eGAJ(S&Zdz`7hnw@I>R=khoLuK0)e;5#IG`-Q)5O{GB*> z4LG;jIUgxWooy$s9@m(!BwhGFO$YZNah&KS6v|{b<-w~bAM>k_pCk_tnmbA^r&^lH zQ-AZ}lDdH4^VO&Mh2q%rh`ozfD9>DrhOn4NXDXTtUAm4}e>X3Vd4m`ZzhN9Y2O)NO zxOzDq6!jk7n3uTFb~y4|x2vRBR{bkOy1tO+YM(m%PVVyHz%;1~RQc+`4K2!{h#V6; zAXQ;2?(P0ZQd#}%wck7IxMiiCi`n#&O$ENJ&9^PknJQwN@|_?LJfjM-1+(A9Hb}a2 zF~JiHxA6}@UYq|C_c7-SXy>5fw5hQY=Z z(pFybkZSn{4@e5Q5Zz;yrcxTN4c52?ww)S?r^s3FzS(QHG2!oVPv~C(CI|Jms_`sb zjg5+|jj`9-2SgRF_S9{vJTA@#&g6lB0vj(nb0RCl285 z^=jpC0&@QGWt(ruCv8o%WfmliSB(-Oa{+LE)29NTDZcYve*npE+Hjgs?cZ@E8MGz?<**HhYEo*fUCRr(I4*p~L zHQBMqf2^o*GBO*n@&`AMq3} zRx}Mb4hcl~niHa&pyMK+!0A(UC+Kgkbt`a4KiKkH>V~OK)JBDs{m^}GS6PtuxZE@G zmKLmwpfXV#e+#%dxCj!?1;|U#XM#zRC3=(bo7#BMKa#pHMTDE+s=n=+-i=t=XyHzK ze^1JKdW?L+GjR_7#6ksiw5Bz4|NE%bCwrmGA7qzaP&ntB$mhqCyotMA&To>=#4Ne1 z!2kMXc+?MCYT1YS^$*?pd-F-e{s+FC&X@NoiK!=GD%)93&HnC)YAuPV{p+nIQpZ|F zxg`44&rgD#uG6r)Vq^;c0Jc&RPs>1tvm&;WPc>x_huqR}EPe~7kUyXANZgz*8;+ey zN&QkI-m%3Q+iq;6A97nh^ckpP1!H`39I=k0SeK&}wRBOWWBze~A^h>(t$Oef;;!GR2rPtckZjdn8DqmEOl>)y>o;Jq0 z^#PgK0%G?uy-ygk^4!*Q4h5=wxZxZ4M;e?yP-FOK7b(#F$#VMNb=H52t^e=g8exp! zl@b`gkiD)q=#=g~6;K-fQa|~NPttBD8Mbup;LewlpyA2K$e&eRS>)+QszG{{y1uQ0 zMbf0LN>AC->gpdF|M*dEU~A1DNm^aRxxrN8=sppNwtO3+=DC>H9ch2#gGtJWS^zM+( zM=(W@F8*22%SH@UXu33uPS}C);g%l8ykP0t*|}{;6ucJ^W>)_j9%%;e1W{Xta=v4x1m^`(wzBzI<03O)yqtOG<)b7RswtZc4U&#pa`@? zce+dQbxB`!3P8eG3S)uN5sx-vsSTe&y=Yjvjp%y|P zu||BK#xj~w;LTv4zjdnkh?>1fJbXsR*xxNNEohtQ9F;K3Q5IawrOn_v3D^>^5XkV{ zLG}P+*G;^aNENNsFm_4@XU}V(;Jm>yg=iBR!vMQ?f;c+1kluEB;c&(R!;W!^vi(m|9;IStRZm3Kxt>VwlP z?oDfNoCRX9>U*LO=aHS~V|!*(P})hCEM2_(+gDPlU+nAX$nv=|){53$^xjVJpC8z2 z^_MXn!q|cI$_MvT)8CE2h1KqT4JbO^Pd=F!8mEgtH-}b-xks4>M&ZaTC*0qA(CxA@ zPXlz?S^=`7^3`ua;{z=Z1Ema~R=JME$>t@+3s}m>@)ZP|%EYq2y3fKkom8v@G3iaAhBpvpX&L$->ke<`*(aXvz?ui?M9z6C5mOrbj@~}VdE>+hXnEKf7~Sg z%$A*YB}$h|UYI+^+1HA&5|bDbgV8D7qeu5f4mNh( zyZ-m_Joj_Ic;4*AUhIJFcb@0>`^j*3iGvccBbrv4>!?1?A9XN@ttwE63N*il{GI++ zp_HdM|As8`VFTNON!H$Y7zaZ%5k#ilaXVE+M4$a?-yJIW^vZ8Ji{!dq{Z~fVFa?Ev z>O3}05XZb|%Ct=VW8yBWQs;L*;Co8{fGdfL(J=EusX^bw$f^F7dbiVb+KsPQ617M&jT**eR&B6UZ((zj z^p40v98j6+F>m+>rAFc2tOo z{&@aj=mlu7`RVWKTD)GzjdL9r{tUMs5M| z5-+i9N>uTe?K}~a(?H^>ZrHr5Z1~6f#^2dt zuG72qYB%uv5o;Z(v}FJ{S7$C&$m7NcM?v1gy4fp^*cuZ9tUqmDi+^oqa=RyX^m2JD z0c?;u7BTT~uT-#*`{s{T6{fczpOZvq$#=+uz&iki7Kr*%W0tNp+f1yOmv@Icf6Q4j z^;|cCbiHbz`mVo%(gf2QQLa1&dK*aDc4Ggfx+PX|@(88W(465QCynunisaS}fQl|d z=MlN$J~=!$sZq!}rtaZtdfTa=GDE4Le*EpzWOzy6c+&U<3k4O-!n0!+zZ4Vd#pWyo zzaXP|%OEw?@@4?_cG- zNAHJdELN2qiOoq?8rBELn88{I%W;mK^wKA}Pvf>RL#GDg4OJ@=&_jmdk?oi$NLK zEm^Y|yql~Ll;jEs0ewO&N`2U5=R{OPG>KgPKf2pMel|RKfwX9pwk>alM^S)FhVrDG zalOHrpTvMMZ17`xU_v2>weq69r*WQP(JW9YsUr=yU}dq0kx5P+<;b}Q>Dm6MNxELM zXi;Zw?N%s%^-I&vR&WZZu~l)SPL@aYQ}F|#Z;Hvr_wUIC9>Zq>b+d*r=;d~|gjAZw z$9D3f#H5@#O5dK>OJ%vxG>Urc0kY@Z(DgLhGRJs@CU&0<#MJw14pJD|WBhp$gQ^-? z*P<8Yd+}3&N2P+48z$l}zcq5VPw9d+ZgB>@$D(rYH$3GKMZ9|g41-o5bPT}~T-X;G z3dR!0)W4~DPbF44XmBMn0n%RdVmjhY zr<-0H*?WCMRVXh?EQ1A(_sa*A+K5siTHAyey?KO&v~!-cjPhQtAWKaaZeqFMgy9Ox_AS$f5=3n8?_VEF$b7#Htr=Wh8;Q~npOiI!H3~@6l-d{WI5q~m(+h|e+uc&L z8QixA=c{Tlxn{;p8eZsA!qYF`q;Cq`({+xiZ-`53zW$-SmO{h zk51l6vSJLCy$GLxROer&_&K&GSpIdfYsE22jTh`|0S{-&7OS=dBW3|7`AJ&HDh%q5zbpp z)5REXab@y2C@c7?PEwY$yI&X_zI5{_M0)6dnhT&a7hSz4qSx@M+nW8BS!MtW-9f$w z&9>wLNY!6lQpcrr*McL=&{U-$q#w;r^5Mw{aJ+WcdlDb&#oZr9%OA0-b}*!~1`vWs z5a2kk4)zcZJZohApXzGePIQFeOrl!Ncd>Z`mqqH>Hk0yQvHC(8vx{6g@xl_F;h}ZW zM>d~4%*0j$-X0c&S+N}512s{4!jLe7qPo7Nb);T$sE51{j!U zK*c-Q?Aes-X0SYwlI<6?U|GKpX#u>wtJaE$jlY{*IT}|pb|@IVKHTGzdDF)y?cseI znH?Z~$PLm9!i1X_bjbl(TUqHHzrDTI;S#?%*o3mk56>HtwlkI8g{c#Ah!P}I0{fEU z0go%DsiLtMgK~K|_BHNd09+z{?Mp>xnLA|+2Qq~SZZi3|4Q>x<{BDZO;`5yes-FAQ zL>=IL1X0@b5Zy+`y~&nX;LxtHl*;h*BKT?V#B6Al;SQKBpGh`@@%LKmr7ZPuLLFdH^{ zb07-3P(f!|ZuXYhc>?Rc%z9#y{Enl>Z5IP*zKln@X)w}|tV2yqgW2^*?bEyR1q#}q z46T9XoSIFG!zeOLz{G?&HWlJ?c*)@J{rh-9Az!z0OxxPU{CQw6Ll{Bt(j^r7@YOO(JrZR0rgi_D%vPG z?AP!KI4i`qT*<$bmEl%>^)Py%uO}kGD!1_09M+-U^!&P-UBUra z8+_{*U*Skq{pmw14d`1f{+e$C&bFnr6*{pyr`D_XToQ;Np;=Qf7vxA>be?0KxmlmqQ4DVWdH++I{n`MO{mr% zK{y&28#G=UEDSabc@HX09}K6D^lA`L4nH?#E4hmD(2k3i5iGiKg-^gqw zO8O`2IUKb&Oht}8pXB>cAFUCzyj2D)bTdJm}ft$ld;%3A*$mBtlpvohQS{docV+Af!SmIIE`EDxA* zpp#(qsttV@W8y!N)@PzN7mu_!GNWY?|7V|LP7(BHw?y^+W!?e2n!W8th}d>Rd?QxR zhFeqx*Acb8f1h(fKQyUjr94Qk!(jT)a@6<|-W1WH%{RLLp~JX9vY?-5m-KnK7I>HN z(#;-!FUm>YB=gMtXrl}Kl`KS{adiJ)vlURh4T5j__5FiRiCaW*mb*~`aA71}yX8w~ zaoaCb9W3d4lZN3*PHXtBR)o5OPNHkc#7S2Ig`;2u+QY)h4`CL=2Pkuy;+V&UB5xz8 z)c=fd9l#19GkBraGax<6!)r-2W5u<{E?(_EP`a{r1aBBxLW@<-P7uAln(3J0A|X~d zrp{re67Q0iQy4t^Pr^d;xvjHjwoYk%3fA}<#;Rz|v`vEQ3^9%-2tE$vhPN9q%{V6& zWPTe@)&1#3E_%dr=Kn91e>h^mAI3oEvHk)p^2iAIN@YMS!~sJ1e*vs3|BnA(LV+`L zqIBI(%_J+OsFBYF*bznAAmn_A=x}EWE>YDvJLCU6cIjNo7ly!=SvQrzP7J6SPZexp z4!L%8^sgM)ST*yZcj>CcZ!Of93h(B#ejV5nyXhfEUsOwy@t$mc@cXbuO6li!-qSh+ zRER94L_c*onRg7{(@B%`*KGYZ2VZzTlr-%D<|$8R{+TlCVMm}lecG_kF(b5g&eyfn zV6v9nrHeuz7io#v8q|4&ZfU()?C<%=r~;O*lmqm6mn?LKQc2o{Oq8bb@Q%ySvN14^ zy3WjpGv5(kOq?2C+SLD5!&cI zL1hq-rL3t|D){QesLC#$kN3N=6Ds_ ze5W6_R>kRD^;Wzm>icU&d*W6urllr*y7b&(rQe+&c;>hAA^7J%gHhjIa|O`WLhYG8 zgQdauAOE&!JL+rIc>VSHUk~Hg1j~+w^2@H2B4;_jwA75F@8Puksba-6p2Clx_^;=r zSHyAKEpNb3%5P-cpzRj98E>`z2`YV-_ce9vsDZjd>Ra1?7&$d}0Ai7%ljBRxU-wtT z`o^uXTDr#28b&Vd$E$n5tv;Vm6@Kyk`O%Jb3y#olO+W555&6z)LG&->mF*7Ztry z!c|=*-g7j5`={M_{Z4cWy(OhpQsg)vm+SpUcyZfImbQ82%JW{KPc-HJ4p~HV@_=8n zDEOMnO1ZqNk@o6WskcuBea}N2=LUm5R45?r^a_RQNA$CcDq#6y`-W5A`epUo#rG#D z;bDL0ON%g8hCzuKXQ*~|ni$jLsJV@xR-W3L+<)KJ-=@(Zr55+{bwPbzfQJOUfv<_|k zni(eeWbHWcT{$YrM)!W$19d@-g!tjl3aLXJEHBYogvsQ zv3CPGw+sa?kx`hIxK{)tLB)2Om+)hrxuIpTXF#)n}zea-a!#~{!%E!+R$n+&XH!w2iJNz;tmET=KioFTjrA!H`sy@NbU zK8Z8c+3tk%se#ng5j84x)0Rz1aIcl2+-0F9<^FWZNh#L3w9FesP953J@BziC?&Ck3 z2!!3qDQdRKo;j;t-Hd+!t@=aDHNRr6AP3bojVn9WN5e92>d$RBv02lW10&9+DTe(Kr&tSQl|7Lg0CGy51m5 zvB%6vSO2mksJcdaC4OF6gcZ3?w6CT|mv^d}KqiG^tICw#Zkw5<{ymxvEpY-N3SE6! zoc$6$4(n4gtFR(3(0wUXUVC6(YyCKozBOZc*lSS1uTj4kP~EQ$#i=hMg3}=Z8rl_L zSC4M3BrU@f)=%3}o0F|Kze4bwy~W%H!@%herb#;Z=x*k24peBuJgPdA z*oQ7Zgq;Zo@@|0GXNitX6gBC0Lz@}=|310@Ilplh%9%p31TElub?Awwc_CWF=EmZhPipl zjq56@n1=-FazZ=`D8e@JQrFYH=i*lk9%Em6ocZqUmyapRAciVBIm zgorLjb0iv_xn ztth(gYhQ4>&n>*`@k%QFyeF1=-B)KtFGhx8H6fByAm|dD(^&*j>I6E~*%V+EH!DKe!ffqJR)6*QLPq%}H!W44!j*t@-#0M%c&D#0@!Z->_caRxrJ4`*lhO$_@F9});z0<-gbMD+CRc+9WPlX;Lqmf zz(aT04KkiEzMoX@8+fo_{KqBv6){-WIrPK%6RD>Q<$^K3+XJ5zsC$1bJ-?uk0@R)@ zpPmGcZ#*CW^Zs=^?{lYmIX<{n!ynV5aDLB!zOO~OY%96py0O4^hu<(PZ`cWtLAI0; zBX+&eQLGrwM3yH_Sg$0E6*-ryC}xK>!vj1#+@0O74k*uwzM81L!aC=F zwrtP=4QnU}6zYK80{c6@%ANUu4K@6{x0=YNsCM6D2wHSwTk@rNz;s;S!PT{`%;yE) zXuP87_!HS+LJyMfz0=ol9=KX!_-*ED{y%`^D?-y1YD(|3%&8vJb}wwbQqp)v|58H} zf`87$`Y`bm-Ld;Ek{}@iyQ8S5)<$L@_fgc{8mM7ub>simD{`X#QFb-hiCqR(^e@%h zft%gAESD81<>mDMq#HY_?m^UR$e!-RgxQ`^3gPcfkKeOdA-)dzdzTWJsM;2;%Arb!iWD-y);uTiHglHL2SnUl516+Pg@OSnufW4a2V7bGrQg{ zECfJq-{l9z4lqgH@0Tmr>F0mpE)O^NV3ktxbp2A^&`mn5&*Njr} z{S>%I{YzImY~?O%hdnP?79hG(p4#1MBdqJ5$Ukvl`kcIxJ?n}UraZ!2hDJEYW-_^6 zeDFnj@jTTAYt@^0KIIM~Y+_flB=(4a`coWT~^b{9iF|k3Z&V;D5Cw`l&Ox5+QOk?KzGY}839YqTj zhMNkTB+bhPkYd< zMnY?^E!@GqVD7Kzx3zs&^N*VL{l{F>!nSopkPTh_=}0y@xy@)TK4R>yP5v^FB3RYK zfm((ll3Km6L$_Ug8L@imRL=GR{HFdrdsB3Z5=4z=9}1`|-8-AH>pu7A+-kNeVC`2#8JzxZ< zd7Zr?YuJxDk)KK%f8(3gLAnSY|B8>zW-_|J`)4m*K|Qu`(xd(n7V7#@UJ3Ebkd(hW zS(pW|SS{@F3Bv16*4MHD_d-~cHzSij1+&EI_)ej2{+jcL8jo!x%Z%UZBe*>;-Tm?oOuN5Uh{_^s!2w1`f>8v9WgYy9_h%-PlN^Nde3ZV zH_q@-0=z-mg#Y4BB>s$`_yv%oKK+ilmL^_nv>);ugG+MR{Rb66H;F1FXF?3F_!N#m zIcsN7ozkmM<+862N@xA^uw&Nd&{3ySJ-f*1h{95 zLv0^Lx$;M6URtiGVpje{)YrMxB6?K&Gbm1!-)dZsSNBilyU@RAx{Me z^ifz&8@}OlkA874!g{mL2&aHK;=#F@SIdr#nL1a=?0JSs%osE;y zVK3M64p)+~5@OBP=~Q;C$DqBF%NV@n5^pO4b6tyVs6!#Tz*8&KRVz^)1xq7V6d=w# zU5~WKPF=EK#(&NH>NlaaHaXA=f8eRz7>`+ z?C;p-%g(G`uw`MS^T13b#)D6mgIbC8Icn0|`KSh!fmHNSgva|`3{gCN+3;IRV666F zez_%hhQ&+bVzk+QI5#LKeg1M6)EdZAaQbeMdWrm~!oZ&Khc6FN zMR{b)iHe~+yS4tJ9Y(*rA6mp}kW+RXE0Ge7N7A|79jSs>e$KT!b4CLt$wpqGxhc~c z?0wTs%B~Bo+P}0$Fl#{(v+hCGO+`PDKzeB6K z&W&diY-pI(`)_6Kqn{>LT=0sMhbWyVLtO?Da1Io0(Y6hL-FOXY9=Y_IDMJ=S>oIMy6{I8ExQZ>M%x0{tyh)05+I zRR<3b-b_+`ui48cNrpNS^(@Ox#uhAj9ZO_bblB zvCEa4RdOr7jPi(|=r^XB?lHM?x#OZ)Znw|F8b8>=)(kV9zh>GO|5D=Z2Jt|nU#2mY z`5B0=CHrv2i^@(nXbLB^KHCASr4CNJIANM&^C5j=j?Y##Tn`X4nx?3l%P%C*<1?e# zDi^;>P3gyW{v)~KD#mr5dXOR3_T1an82LvBUfmRz2|T)49tYgxc3vtsc-=55J;e0) zG|_VCXl*kT%E$Jb0J&T9-U*NA#sz37SD3Jf7g|p1 zxPs@^oZJ_xtDagjFJDWEo|~2KP|}YLwA;S`t@&eI{4Yv&ywQB{7a3;}dklW;?NFXg z%H^#26|3tS=dPY;S3d>)cT3lu^$zwa!tY+O$a#uyvSK8zeMYt$Bw4s&*J3;dwjSI~`NA8VeT5gZp zXez7c72_{$-S7FQnP$8+ihGL{G@LsRM@2sxeIeid&!7I{Kqi~#BXMOzYtsWYu*OW{ z(5b{DXCg1e2G5sYZ6HSY``$DveBz^uO_nwyb*MP-1Hh@RXd{!{3*`wBAV^?~zczCa zhHM(~a^aAVU#?ISIpb;)A5Gu>GZ2ewFP1r7Y-bE7(-JJPi*Y=UaOGdNd{3#mxkT9> z5#b8Y<-ED@U~UUK3Qk>+w*KP5e=><_<8I8v!5$wLPPffIwm7qs`LfzABg)i&&E~n? zW(TOxMhT}3{|pIQf!&%JbO_a**k_Z1)(yVC)qHYt&h_fAV4D5=DHK^#;I>+tjg*4f zhuSTM85k+dl%3L~@8NQp4Eb6g4E z`I}hsQNJS40#_YHu}u#R526^+N(MOI)2wkaV3E)Z(WB?#LN`ZEIyrbdmF2Iht!{*N zaS<&&33p{ zS~t+s>IysA0|-Ew;9Fn;dLQ;%zlQb|9!UgtZ}fLewpnU$JOSJ|IQe<4Z9$k*AqNLLTK&tkU3>oU3g{%{y*7hYOEX zFAu~DsK_aMZ{N9yWtvV?PGKp&`OlIB_cVdGb!xB3!pYan_1*i>_f8x>XG)-f5XH+v zfS~IF_qfv4@|`d1hl26@ZSS6&7k=IN0Q!lD%-6`?)NpgHACTMU+w12%Ho(j-cZZ+A z!g%B&+CrqpGHH>@GR=k_UUXDgr^5=>T+=RS`#Ktv%7|gU*(AakHT7jfx8}N#R`iXH zf2oQ-N&MBEtUGLodOIOfYFgQSeHLKY5I@!rLiX6Sk7m7l_-QNqjTg97FR0jk1^~Z| z5K_k*bjrVr)TSNgKce}$ICePTZ?R=|Gv7kHh@y*3r=09e!W^X(RPTaCv!r{6uh%lC z+r{pS>j7-KT?5|DTea8$WORO3Ga)X%|1jQfD0wu%#g5pNe0fmr>%rImG;3WM zrb-aQx`%?RU>y=PByGG4c&KF7#_D_}NZt8f0<|P%<4r$gG_Y7ZK42m75LzkuaiEq( zdWa=MJlf6Oy?DB#>}?&p#iDr?Ip#pwCvLAmG2~XwoX0# z_=m3ZkG`6U?*WM{1Q61HsN-%#6xtC;MN&m4S_{2;o;oW1SWU0y{eti5dxxgT*<9}U zXp5&SFqZPKhYPyS{%6cqOLe~d>vgGd_hAErTHKeF|-xDdRA4U0&JbuqC~S@)&Kf#d5{y0>P+cZo5lp7^e)C0<$v_KvVg zJ&Q- z6ym4vMLvA`GiT-yzUvVj#bmW7#MSYE7EB>o*CPy&Pt~Z!8Tx z_BJX;+n>`BLaZnj3>-!L)$kR-k6%FgoJ!icUWpfdXM3a*>}8Wn zcS|N2^xQzL!$&@q*52&=wXMzti1(jf3W7Eij^qje1;<^YJ~M(Ymk`yRokXr$FO$I6 z#HrJ^U^Vmlk=n4@>Z(-5@cFZXgb0^&)$KL$AIU#Rks4YRkcxf=yV3UI`auK!a3h%D zD%BghU)@i7dA!ETy@M^YO2+mKbCwUdrU{xh5$bs9F?6_0K)$sq2S=0=>acy@^>_;V zli-JoI0gL%GRV{)C_OFRVOr1(hRZ~O;eB3P$yYN8R_%=aQHGl{14hm{h|V4Gb;x^y z*b+FZVLpGp7kkysg=ePcF!znu=NvTT?mE<|A4UKvK-&-K3I6@ALCYPQ@oSa>Od5ll z#Md(2;StK;7Y4G2$CH)@7F*%mB#%G%uRMayY2B5Wv|uTFNj1TV)?|;GixWf+)b-i% z7Fk&vD}QUJ(w!R>7I>9o_A_}eQ2wsOP81+KdVeEy0hoT*04p<;!L726)-u_TE%R!A zP=8p)zp2f=b3)OlCgoXgff?aUNGdG;sy)YC4s`9K@Y3@Y~28@RR;E z@La{|L9Maz@ihs+3CS?Ztdt*G>hJb38JtLp-r(a~NR~52C}489scEj^qqEtlCXKW< zi;jh~eOJB985r$zg~x2gYI;T9TzG+1k|a*QLe@W^XIyyo$dkU#e#`DRw!^m)@+Eji zM(TDhDBa9uUEI+#o$eismsL=Sp7Z^iN#wp*x9YU@er;3^(nX&8v(3ce@nrGbtnrWG z8sMI?>OvbZyJwS*EOWspKn^9!Lqq{$!!_QGlP8>fVM_a*P0*N|;JS|;b{ffeDbO0o zrg#YzBvRLq?AhS;rzX*07<)VfTfB|3%eNBhkf4IT_xC+obAA)nLp%3rwu*hS=rRqY z4a54yu;`k7nY{UN*z#|B$IC!lbmM4qZM=Aq5Q|2ki?82e15mzW&7=xd&8bEkxe=bd}e0GnA_&cSeDq9Ur#$7!Zwm64UWF~ITYJ{XDu zUYraN&J1t|dk=8oyu1S6M^Ofa@j3_)xVhj=gM7E0JLY1swsm|)6k%EtZkjwK`ug!U z43kp0p5;W^J6ekd)zlO5wF}UhlFx5Lz=P;(fm-B-im|g8ts4h~@wS%=-PtVhuJe7! ziiFj-y!!>g)c6NtZctms*kPOI&4p3rPZHX4oz)cFQTpT(oa!8*^)HoTU8SW=`Su;q zZ-|!RbDjYl%d$^#mwOBk55YO0lu{V9)~9ls7FXDXm8Wa!*)(7!Rui>C#-OwmOI}v{ zOM(DVmO%3|sk7SLa?VB0Pg3e>~gYC4N?V+97c2@W_4TPNMK8x zuIgnTnPp*XL9Q}f8=_dYWp>Er@$|lETJnL39l26Yfhl}v>|l`~SQ~*OcKu8B`!)_1 zUoKWS;&XG}qTP^Pk(K|bNM0Z-k8bHW7~`IdO6rZs`FzOSc>80 z>p1|YMA=+vzW&d+sxGroYF~OZm{6{jg$HfyTzD4`OZ0Zv_{$NF9Kz zT*INt;vgqI1S0S76i&gqA_#C-Jm}RhS%e^@nbpecn%KA9cJ14OWk=O}PkTT6j5He0 z^l>?)KMm;)@zjIhfdgY1!<2$>xf9-K28dQ==D9av%wG1-?ezY15ZSz2qJVkp*{;10JK0|p$9^KEVQnAp!)0F#e)KSVdymPwR4dzPj?y_k@6Mr4l=ELW zYB_Ur{fWVJ9V)pY2a40#mL3pW&I1tLJE@mZ_Lp%#Dr=KxNw$Cf=!VLrNnmWw2G+%< zXV%`YOhXm}n{}V8ouW~DdHZh;cAFM9_F%i^MFiqY0`Jl|Av(69puw%N(r=NEPgvOM zVz+DiLRn)<0u0jGPj;WipJvCH?L^R{;*sZ+Kc4!lIdC}#a&7R|B0)O~ZgBhz2h=&w zp0J>){}fn#KJuek>rC}OvW;;HNDx5p7A_gYl#2EGFVoJ z`G-4$Q*87LyH_h2NYcbHQoNxUmgPU41MJI;kr3*#9AiBw)8((R-kN%!x)}SC&;2+R zUlVbvLDv&6GMzfkvK?IG-WGI8)5hTbUq`O*PK7xptaE&lo^FWFqbDKc9r)nKak;{6 zSY!x`t1}~sX|{Xv>5J3@>b1SnC(rx>#Iewvz>-xV#8p`8{k&rOGcrhc91tg}wji7V_2_Kkq*PF@i3cE(e$2#Y;;`>NV=u$HT(Q zm+O(^HTas6B+qW;`n13PI(4EC-M!zrLqJExSOzv?d*FWI^1Pnv{1!+G^O8n||CZsu zRHo9=8UlCjPz;nh*YzJMheP#wYbH7dmJnZ=pT70Vf59(0cKOousIaDrgMIxOVih0= z#pN6S$6~YKPXDFaCUXOU1F2W*1-xEnXwzh#yEraZeTwT9HP)#LyZ!xI{ngxw?d6lq zXV1?0p2711%@98*TF>exSoC`_qm7Q-2lu-M0i>=6*8a=4I6)(WxWr5Y}_yP*P346Eo*!&d3}XuHf8JW z#%{^&TEYRIx^Rq3{rZSFbDuh9%oRoPp(#&bHWjQ*fFc zo5zES!-AuLcZd=h#u-s;$meA@uFhuh`caac8v@fE^o}RbZ*_>D*|YpNpIyAi6sE9| zw((vz{ECli%wxb~-0pUNqS0miqFs8!lxZ=!ck#AQq}pcYF%sc5jf&1GTAHCw1Eiv2Dr4+V2Av zcRPziCeT$w?U%YOWV#qN^q+}?0U~O4HBrbZ^)bDh6(lq?_vCPB@AEPm!?MC23tYA( zy>{jN;O%;+_79unuKH*5f-bIgp&&_;i?f~ccxpr*Y#Cz4NWX2Wx$(kC=ZBV{yuG}V z$>a3*E3lVSze2p7F$sKbgC1LE=D*8YyqD;x0vA5qi0i+KDeL!n2-y8*M|HfVUZJM2 z7#5;1457v6w}w2!vqtX(I!2u6D(=L9T9^x@N>|pYgB){}T~CI{H`(#sDtO0m00%^2 zw5IyOgj*i|y+Ujqed-^ke)^C1DFI@Ns~ZG%gxj^88X!N~0TFcprYzJj05u`20>gC) zY;TBV8K6}0XP?RHu?N+ zc?15`Ay3IM0jM|BiF9ju3Y>JEoTd+0l&aZSFIcgQ z1pd@KT)$D}crpG3;1TYm*KSb#Tn$%g%xMzQ`8tnOT0HHzOh9Q8ANn`y;kqMzrXeb~8Xd&TD!yw( z!BSOUR%vurA_?I1{d@S)W=a0sVj1BPT6IIsG6*|CW(5s{-=>U4;ow_t%mO*AOjv7kF@1P^Ll(_ zC?HBraX8wEH;R1i_s9v1-Gaiw8YBu@|I@`Nc;}D|esa%qF1H!EN@2~7ytH}qG(UR@ zk9v7LgHvd{SZNrOGw{lBjyO=P27a?j3w`vrGFn1{e03E*h!$!Y2pV7ei(omj(xcI+ zDKYR4HeK>i?%r+3&hucb6StcMM$5lRV!qaV2vCl=DlRM~WwV>tHd_aU7A zmU_rKqKP{ze4#?W1IKn&$ueNZc1_t9jUutG~&JRvy-x~4IQxh=YR=< zfFkd>DO78 z?T3HrPWkKGi~e4v z6Q+a&{QtfHGY??0)mw{5bf>&{!O=S0h&f{aVd9e>G>)nBZBIK_u(Im~i%8~0wle#w zU$;qgo4)R?aYB)i?jvkdz_>P77yAS4Gk3_+2Io&6XMWXqDH=5$=H~EdYQ2KoY`8_{ z-a8^6Wa(|~EBl^{P%`a|$9pudjHO0`(ekln>g}X{Mk#>ns*EFmf9hSPM0HI=+{$lC zxO9=rIUNfa<8`cY$JbAmhu4On@{8Fx&@mfnE1D<&4t_;$6?n= zJTa$Xm!FgraX~E$d^N)-(!xgpXcSXFL%U+P$fG$qM_`H&E?>*VCG8uTM-`I)jQk;qf7?1Qnv=Hjt%ej}xWKu#mtVBh$!$ zb~c>gKTi{(VjxTnkF^XI`l%`e#a(+e@8U}lH$p!cd4MS z|79`aiGK*_{^`85&*Av?BJQ`+8`OJivx6{hV4&;DlW)!Mj7L~_Fsn?MPjzII$m&@I@(JDrW`N?8r|ua|kY`@R!> z=m>l=YYwGFJ1#~nRtcPJbW6l8$RhDVk=`+mp?Xzg1g$RFkbR|tM2CC!vEr_Wnr3CL zrtPh+f>R40Jr^{;ka!6hP(0&l&j?xCzfFB~4|%iXZQMKg*KZCp9>%5~#DXdaQ_Jk1 z0Z&3O06|^~@Ds#Kf78-?XWQT9qGl0T&l71T&_l4rh7^AXss2ob&36P#&kz7WG^Ps7G^-6-GL5pI6<>Emza{;AKedm`?^M7}}i`7;Se?JdFI zc5Q2F13_Wmkp0FJVSE+>H`2H~>Iv7T(3GDL*rraj568XU=Lw5?%uNS z_-CV~uN~etaO@87|4t-^m~LS5Py!WIV1# z#-C=-4xiKx=1@{uMtokRl}@R}fj$+p;jFU1=4y@g&F~zYJAAhjJK}8ur!PNHdYPJP zsF|e?mpta(>#oR9;>77%;$m^y!3Bc?YHkm8SGDOSYXQb1ItkY3xMp^e;N>4BI^k;Jl1}j*j$-x%lSDSk=oTgIS3#GHvMc*;lBe z!8P5>eCIr_fQk=dlB?3Gn}*j-s@9^!TY~4N+PH=P zfWE3U4xW^F1`Uq^Z(#M}p1|?}2P6=$(YVs-c5A20x2=sPiSGR<8^A=+V0rG@&{^ry zWy*U!PLRu_88}Pc?iPi8X?LF8ab3AnEQ;Fc6(5-2EIuylw%vX< z=e0$V28}n1P=?P=_jpWqEQDx+y~mn_H2pC^duT>d|9itTrI9~FjW0E6AG zQC1<|v&jBn*O?mLnXF~>SF(&HdH4*>^tgEVVSUysWUXne&f!4f_rHjvusLXiM;ZRL zMV+N^8)-y$Ju*j`k`m?&=k)i&B08;IyUbF(+Bp*C?>jRtYH73(cDc&^-@6^U8Ao68 ziWh7x=U+e7v`X!Xtkm1foj8#ov9t~BlVu>PwMViT>rJi?G|-dMFTkf(=gsNbPpR>I z8!%Rjepl?y&wcYu`2wHFgkE*KP*cD2tQjeqrl5LHipuMA^Z%mjy@Q(U-Y7s66%i2u z0qH1JY0^6pkuIS09x2j`fb>8Vq=N_u2neBfh?LMFbfha)iu58i2_*zl-1qzK&d%=6 z>^~VMOy0TmdG9^XdCuYXQYHuA>krEe>$PzD2neKz1!k;y#rXa3;FbSl;aqd@S$H1*xXe9B+L2XWQb zA~Z?Ac&cuW6ll)-aXv*(j3_eW-Ei4GVFDP=I9QkWzSsIJB0 zM9A5A6mC%3RtNrSkT*@!0&)Z|n68=jTj~ZKD9SmlhH9u^c@vpH8-!^zt79-b7FTv9 zl;MVmuno~TmX+9cslx8Hed+A;S3P-xhYC6br0Ccj2Cl=^J=1H?KYFTzYC*_)`F==_ zOZxIjmMeHxck%<5`$obxQmd?*qP!Bw6q5$90aR%HjhRus3G7f_BH8An;~3C*r|$Ia zMiO^x_!e?T{RYYcM`*&GDM3|bg}XOn`2H$8DrprzBRs#!v));w^M^&b7>JOeOY<(s z2Cqbz6*5{k>ZG?vVA;jsp~FcbK0Ar$Hms*J7Q=M#2)##bG1rg0tNeg9QGVD9kz6Oc z@U|N1soDs=zKs+a6=M*vFJ|#>b730+zdK1{#m)5~5i$TLhB}bjtPM&-koZ--rS5Xy zvf)_uCzJg#MHlB$9G-lAu6wtWEAZLeT0k!+hf6LEI@ml&%gwD(%gIlX;w@n?!SiSk z<=EmKHucPZ7(%sz!Sd=J&hSF7B?cF<_xrX%ZdGFiZdMi&tj2|$i z4+y|~{B9s$6m|3k$GVgyH9vY~(}HKM&Bp#fr#QWBoI-7KljdoOZewFBcnMRnvX04> zK|HDfx6wDnc^1GjGqOQiU_pO%2rNx|$P?~nbsOn>PqOjhbbe43Z>$_|u<0(-0R>~u zhW>ovI!%vd_TSU&>5i7fO-E)k_=6<6yMrYvoRNX^Ta4e2YOv1R<%QA^YP>u_j0ii! zbv}VuV*b=1MI#@I?_y_htep3+Jxq6k9ueI#h`C4?5H&%Mn5WGBmqQSMPrag)xdz!R z-UV=qW(v7&dGOZ;0{-ccU}HCR<7ziykocsBHOE#SL;&Z8=XK-Y$4$Wl!<7tt?Pjqi zcm@&qqvKQ;_w=5G!*lqslB(q_!EasHa=>Cy$alXfWm%W*)R5bO26wYR6ntm7+GQ>a zams#?A;$BoC?xGEMJYosuIM5-v}Y&t?gv(NBfrtB172^#rgu9glcf>PXea>XI+O>E2?w?#tH8BeHelwkVnZJa`?x(fb$(D@vdH$ANG|FfleN%hZbdX)~ z3|S8wlzS6t!Kx?6)=*6g1pfEmOeZ?Urun8$#}s;l`})rw3EQQ0e2jPt|JZ9|)|wbV zq!#d3#0q#mG)erifJk2;HT~zTN0LX^p{6ATzluEP!3ZRFbCa%J4`pzLOkbE6Yf3kO z%+G+5x3Gm)>C}x-{(;IhntQA&)O~axPx2PeCpG`1={y1nM(x^otRp{i-XKvCK<}+^ z;ZuVg;-3t#)b8}YmhdsI&)iM-C-|pB=C*OcxHu2nZ_@jlLG7vO>0%9_dDN=RA@iGJ zf&~t`;edmDZjOFgcl$xJ)&{7(+l3)&EvK~56dpF8HP?%W(cpZap$AGiD$8AT*xMcD zKK3X;JcPMx4%%LaHK6M%g&>BOehjiwd|?ht&(M1^j34S^e@<~JFk?CX?4P-S)6YdN zIgP@)kL&kA%pzbl6G+{%XqCX+5<@39j#Nw^7K6Mig_wFxj4?_u?M`k;*=u2sm5;;wtKezy_4T9_dfJJ>HZ`{Dlm24<@2ItnUFZIF>#H1 zKMVT=7a*eNx#P!MJdZJHqHfIY+-4GTvQ2TzZGViG0g2te+DW>LG-RIVx8I+bzj2~B z)p>_tG^;i{f_so`Ge0K)^?xR_pES^^PF1d!XQ|&4>nLO#Vme`a+Be<2hQ9m5Dwh9G z%cm=2p{#i7Kv-`WE3SA$SFkUuD%fwJvLwh~OCrccVJGc++XliVOT?9$o8eCBw6frg zGR+CCjPTJO~?&9_)kO`tuhMCqyV% ziZVOT9-ED@jnY|G%1*m~@l?!hdk+uKxs_6~U{P37FuBXgM*2bG`zg7SC~m$l<3iqj zoiL&pJrWzCX-qE^yk6TWv6p_Clqi*GF`yQRU@c9%bCCW5b7?xiYPUP8|BUrN(n@lk$uHh&2|1

zRkDj`Nt5H}*MvuH0}a}}t=fho`YuI^OInfhH3dsm%3hse*~0d4E+=E;+=csBsi$gg7C${>iB@|hzn=VD zEmdL4;1p*)@5BLdy;{Ns%{1sCP0$NZaif7tWB!SA-Fsg@TR1p&$VIg1F_NV(B8e8qL9(98U44BI9OTYnG zG#t#h9S1sSp(bVXP9_ODz{KK|RtBQe2CLr!gCp9nD`~kEu6afenK$ZEXj7E zuGe<&SKm-a?!f78b5m$i`8#2W)jL3D_~y<4=;}T;+3gXF+178*&srZp%ZIKSIc4GM zu_bfug6m0fE0||X#r>bYe(>Z?N()IJQKkt){C!hXReQ_81Tpf`gX7^b+9&~Ieq6F{ ztQJa?o*xllgU8t#PdaKa+m)8O5{-a!oBr;3GJ$3mHC}iAM5{_K{KtEPt7R>=D?2|3 zl_z>aCe9m`XjsLm>6TOO|0O#L6b(ZE&HlgGBTdP%9(+k9o3@vxN`ApU>ZjHf{jdp* zIQQcC!7PFV=Q8hE7e8PPo+U?M4LskdXQ3E;o;fh0#c3OW>0gdgm%(v$GHXEpME!#q9x2LD}+f< zbebZjf)VJx&f2KTNXsFYV-QUCSoC^gk0Str(lvB&8hWiNf|wQMt}lPssAf^1W?T_w zOKr6i`%B|(4B@N{RPE<%&?^pF(<%PC=mPh8`_q?7S;Ox_Zvp>XyXeuY!Wfeb@umV0 zOIGh}pS@U6h)?N{#lrym6r3(bvUEU{j_?>W`fJ3)Tc~!vZG*Z2U5KthZOo*7iYyBR zseb3x9oy5m&!2Z%6Y$EYOHY4YZzXpA;PIM7#VbU<>JDSHYSiO0m!8OEerxBtcS_8v5 z$ME1tjd3HIZ2CvC+S~fEpLQLPIx9p$ATBN-Zz33%6V?c>)$iX&n^*=(BKaKN$eA_^ zvN?ooMM5Q|h;P!MS0o6B>thn~m7@Z1cih{8_eyO5AEF|R67m)e?q^CGZ~Q4Gz}K3@ z8oy9GFH4SJHuvbn!RL~20yGCm3_So?whQC!NaOw}43j$MwmhU{d{(qki@t|k<#Auj ziSW{E*}a52M|X_KQLqRkp!DEOLj$3~F!iApnR*wP-oGPK=w=*L-VX7c-*~~T$h!4> zC9#s_TfO}jyWk0GEh$!Nf*FV$k2*zMy*yv%D%p_^wC_Ey3(B}V#?3c|4DjYe-J;Z( zfqmEi6vjxJfl)zd{i(Dury2QWz=Zl$x+ya&V|y#O}u+@P?k_B4Usw-6WhkIX9j zkfou1@#60Mkb;EX$DvH9zfZo3&|6tJkOdE~!;N(Nw*pmM^Y~u*%`8$ex=lNG%D6c> z0+}u8Uw(CXWH6`hMgV)$r!%$Zgy8=n;P90d9Jgb!7r48VAH?a9ETHWimDsKfeSQI%8#cz*@s8q3ocF6j(6WA zWYa9MPn^3Qb7CdXumg>CSVS1#EHLV0>H|;?Ek8eOZ`CrQqfhL0ke4S_xxZq%r)8Li z>qWc!!+i~y8^-{L{(PtPL=|%ND+@A4r1M@NOzV$dz?!g(WpmQAmgeiKmT&v`P+?~N zJaI(cFR#BrA7h_*ozp6|E*K?eJQV+t%Ky@Bk`5%_mvHEB^JU+~(L={*0`#0(D6a7O z9hwf!TK6H(v=yu#r6)ueAKbehKQUi8VA6RHk+tsfFyinkmrnefObbt@viY3l8T5^a zd_d~(bY)&d*x+~_Q2!l}nH9v&ruY(T84C)xH6QSA>h^B+914y&cA7G?ge{->*B-2W z>qsj<2kC%pJM`E2-~iRh1R7H=&>VZ)gyt;`j1R`#-;x?&Sf7A5oonVX{bjpyWFIz| z^UA`rKPK&M;5JecxeAZW2I{uGZNCL}a?zAtUf*Fj$!r{~eZL2leP=q%@%MkeCzrhd z@>GTUwThyIsA5dJCt@u|E%c%>^g1D|=1#V3&(300n7*z&X0{KY%4P223{1Ez?San6 z1C$41Vy6@?{yC0(ErgTKJTP3cKFP9ObD_VQQFoU+Jxk(VJi*y_>V06|xRQPVu(Top zKjj+{Xw)jQXCijtuz086TGgn&bvEzk^gz5T4=Xm}he>GVeUG-`T5_^!F#4reyanoD z5N`&#ha1cv^TvV?nwq9PR1fjGUnID4A7+BT7H;_xUK@5snqBH(YtW)SE=b#zxD{Fw zgG;SiNgzrOfgun58st61t*F<;VL`~B*Ax$>hD2;6eOQ*qwE#UY$LSP6gucW2EQ-_q zbQWO!M><^?vi6v-iiRd~5fTN?1P-CE_1|-F5u*WJgQvt2kc%p3TDh(9!xT)cv6@)zJ` z^ZOsqM2-JD=QPEk>dp8rKv2Kw3IJBuSI@|9-Ut^5r9sBXAAC>`>W4n?e%xsPKeYrp z^ob2;FX11VwB{3}w5!4HK3J6IBk`(pAlZ)Bj?Sj`#qrl0gV*MYBXQ&A^F6PWvFH(; z4z>Wt@3m^Vm^KB`U(4e@{{11A`@YuIoiE-VOVE;cW(L;5_KZ zaIc&8-z2KuW>(8u4FO--52&1b$9d+|4I`oDbkY-ge9=I;ynxvpy3OYp;5pZhnjx6RQP#gT@O^J(|45)puJ zi#a1+jXO_@`ad&?1Ry|%|0?bc8|`Fu#%%G&3G3{@3BlGM;>bvzoosGc4hGD5G(@L- zF|=+<2ie$?&gK-X%H;#nCVs%huA`U&$p_E`A2dzW5dmBl*g13LC#cor5&hzmSj_xA zY3Vp#^tZz>3}=q~PA~F0L={b(=mToKvR_R3#gD{~wEekyWQ>shiCQX{&yHS%wGfv) zPC-^-E4>D|%o@_ff=M{$PiNCwyk<3|GjcoGZf9|eGxE)&vOz7xv?7e3GwIbfJIvf69~mZ1ZC z`y4f!UFFZeX(BeIbhyRh?m-PBQ*vHcU z6({3e9jLcteWODLJ?4G4{^-|@B|NgNd8&1K$JCNDPv(+>K(D$Eip-lLahNTy1S0jD z8b9wj*Vebl^jYGhxkr=ckGT8SWj#t!zWopl zU4_bQVZ^;Fxq%FL2~5p-&p8OK4UWRTc5jciNa(r?DKVCy;3v)3R?9Q%Y^Z^8d|nA$ zQ;JtGG`-&~8FH3c%a5+?ef^zGs)Djyil19Hr>}dYNV>Hpa3C(m-B+4wiDPRfjN&6! z2NvIFL^+TrB)O#gmc1+OzA4OL>bFoicll9d zFiEb|mLbCgk@&U9-FH83vT+t*2fkdiJPKmITgi!>(592{ZUy-&E5HvV@LV{FwG^N- zmE5$S#EX&6;3ydK1037?q)V_ln(@Aw9jqZ;+Bg3aA^$m5Cw>U`eUM_{3hc5kzGMau^Z}tkj(ayK4Y0(o`G$0 zSUF04e!%a!dEw)2lpXTvE+9vmbXd!gjlWBpx#W+7I$BHOKzP-saeF%cCh5ca4O&8; zai1)=Z111Y`;*gTFr17dfF95jE2J!iO;x8ApV#hQriioJUXA?teV-%jO*vv_tSVK} z3wS*@tPEIFtf?2Gm8VQj+8HXAbVK~?&;vc@Jl#HE)<&z zzM3P=!y%xkg+=wC2QeC6UaopS+8c}wU}Ds{no?Fpe^v0RVUtjLfS`+FUJRUDPg|0( zp0}(nZZN^zd>zGLhc{N5kLAg_Al@QBxvEhMIEV=tj3fvU_T=+G>d@8n)-S>Ohu}Am z;~)>l=&CxljcrR4uiZ;iU;LB60a1oPb!+jhqy>+oBc9~?6p}+^H_>h91bXg2F$50Ri!g-Y08WB2QF2Hu*$dyd$_-4SntcGbSR z0CgJLyo4=7b}mf27%u&FK7K)OrJg)3h1+IZBiiy_yYv%7l(D#IAU8X(y6OrQ(D z5;#|?9Nj(WALd`W%xOU!L;q=~Mz8c3F66~1XSjpCYK94JeKhC6%2lLrG@OWS!kKQr z{-ZD8l;~jRDhrvl9!qgUe}TR-!o`T}q};du!toeNGpsyAESf;PHkiEqR>Rw78O*uN z2f@0-qhR@KoieRxy?m#NeGck2bKx^DrogcI4XTKH$@Oxeab)F>fobE@tH{dlGDcjP z1pZG=v%sqRVp$wfsOsEfHxR{q|$%*6kToVVKTP%W+@L@Ud<@YYSn{L z&LzIDZg7FR1|3%(3gkV3m9^VafHBX@XoE>AeDHZCFuUk^{PQ5@b3cXdoG6pSi4X}WG@)^4} z#uys5Tg@(^HuY{l){8r*s3kR%H+e*Ys3Rj4s3^@L<32RTH1hv1=!B~gv{edaec!aT;P??Gj7Sui52I@;KY?|U&Q7$23gXfyVC4_c!q?8{FTH( ze-Nr-pjzHvy`tj#U}u&I7yFvh<8O25N)98AZ&~9AGxgk$>e@S#P_*8BQ9QO9^SCRX z+Y0BS`h?=>;TR(|q}$KW?jPCRc1LtFTgu*?@TZl1i%xoS1I`5o-p!bgb8_u-KYO|R z4kQMzR_c~n)R9g%*!TB}r3CAZC4GDD>FyTo%Va@JX)^7@{p0vA3vx;j2M-$&t>#&( z3WW|5wV+Gd;;7zVKHJU#(jxrzZOvv&hX%gygN@}Z`ZxVr>_x^C26@7y4wmC0qxD?G z0fOc0X^-?fcXzIQ=!MGb1Z~t#0SD1^yJyl`!rzE)ao+^??F)?42K$CmrsNNmZb~Ip z#oYE_Ih3Q==KJ2i_`5^1UBCL>zEM4Ja_;MMpY-?fIASx&I1J`%mVdNlrcpg>48 z;Y0q3i8|}N-{b!m|O4^hgAEYSZ!W;KLQN`LA>*v|O$_&sFd?DVq z<`-RAoT=Wy=EEH>yCSUwx7u~K1Yc{d;^~-%%u}ZWO5buz(v*CGRWuz@EI;q{}?mK%y62!OjG9jd}Fh=wxP}Pv(3Wu)L=;wqlo=9sbv?7 zhVS{w{JAa?IY$5m@vnO8ntH;5d!(^Qp;Sn-s0ek@;Db5TjZM$9a!H+DK&k5WLETN( zbBEltshDD|N(zMTlHct2lS-8|4??)E?^sBb^bwQ4x+YvA{hQ^?$2@?Mo^RrpL1`DY@U)iDoi*@RttjKlZ+q%o*NzAg67A0$O`tU}gMPrB z;tE~g+x^4OsT|(wLex!7sAyjWIH>jC%KG@Cx#}m|0+bt@m=y;eG;kM85z}F{F z?}kZ7(cfjRfROZLo>cN+HU`cdKMSF|gD#9Y#7b{@%e(g^YXWUn#LA)=)3iHhEwc>Y zMzlB?)c-;mI6EXpyyF2abDZUrsIBcQl%?O_YIK%0`Sh&$Kkv<{O6}B@e9wYZnWEOl zTrDmw=sP_v$8r4*$0gm{4hOxV)IJj#g@T#)5|_re?2^!Da0}vRk)wC0g}EMI%f-x{ z_NeXo?hSWcTA+UP{oL60>^qL47M03-P-n}&)D5SEQzg-O4~bV9TNK}Fh1`Cq=il_= zRW_%wnpqV-urJFoOQ*xAqjG%Y6z3!Y+&qL*b*ZP*6P3vu^o%r>?o9oF+ov;x&bwSO5e*@_+F8(m&i~O?nnPft@2rSUH69_??W?X{^|Tw z{WP%iMWFjx6~@o@z@~&QOPPRSo=iGWL7&@%Y{+2U4FqllXHq$WaCfdl9yoKg+|}LY zI(aEg!sj;ps(61>W1k< zQ-Pa3v_nPh$SF?|o%Z;an+qzNra}j^CAqUaO-%k4G4HK37Z2GTqSV|aJv+M3s#$Zi zP)9pRZ~!uR&{X$Rj4VsH@Lzu$Jvx(CD!Whlb9LH&)8*kab)V*i;~>zgmLhvr$r zU7@;a(g-g)tqgG6oRmbLied1#GZxLuHmsTD;>x_~2BI^TW^Q1HIIP29sJ)K!?p{>gforM)AYRlyuK@xaJ8A|-gb z&RU_eLdat=of-Ze`}4@<(0Eunz;yPS(g#ZujoZUd7*&=)Wi{cUj)I9cg8Q=hQw~&3 z?oPKfp!mI*Dh2huq8Du)GTLc9h<4hB6fbvaa!$jsci60)j_{7Q3(Xs1-!TTezx4iY z=cxJQY_~b2HY5z=iPT0c9ogJBGfkDWq!`5R>iA~pz|6w>&&x|)R+u1~%rC^8kD|R4 zKHU-A#%CW&D=CjJj2kB`s-++gYsUhcUB8=U>RkT*CFSUI5*RhW2->AZO(-O~{LQei zV(AP1CN7$dn3-X9{oKp02WDcXYMHibe7l+b!eLdltwQUVK$0u65hYNIia* zVW3pu?X&={Gakn|j<9 zVMDsniV{K#_vB#sAc4>s2(A0CeE_VE4Y&cYq<#Vrr1#`u2y_lkH0e>d_Qs3gZx!EVg z=-=}!hFhpF@;Q?7DtzfQ|f26+)kB z&%(&Z6G{%G(d{J6n!d zRHRysY*EaiZzNd2EY5Frc^fh`Yogh55%hs=>Re3=Q{G~7@hO@>35Xtzw zzFmM5QK`9U50e&HAzJ<;YkulZ==w<^g+XGga2I%WD$Pz&Tx+Q7oW5g7$n#IEmYRQ% z@jse0f595hufLyAoOJ?_To+KHGCfYM215C>U5kf<5<|;}(swRM)?25#@ce7@1jicw zWLyBy*wDpfuLpFk(8HJs0+?$g_L=1yO)hJ+ow&>hNzar@?%NgL7?iFD%X|c23|P`K zHEyar>}M7@_Ian=tgTzf{`{fGre%ydtzuLB$npEWSBJj~St&Zmf|KHqt3`mHC@kKi z#$B|N*UD_s`jNV>^7#1J7tSM{Yl4r7s@t6p+uK^FMM^r6nMWcu>_zG3_v?Qg1V~75 zXz`?I<=v9}&qbV!*J*pX{^BM@ zVa+S)F2ljMjUF+RHM*V34ha-)S|4dYm~fvP%>@yof%+O$to#mvS6KjU^=j|My4IWe zbR98;+~XoO<5sADbM3v|X_FNBvgt4EzfQfP2~zoi`p@dn@JJ!9$%at*2h<2e>$NyZ zoA=kNnc_JGO}=|4xF;M2E#<#uR1{y$>1q2}IBZaQt?bYW;S|Dty5aElSIN8x`+%~q zo{=?DhI_fK5cKYZr{+gum4qq}UBS@3yh=eb)f;;^QDAXvQXi>C7N%#Z;^E}QkoHmMI->68dg2WR+OU^omE@_j zZ3R_T38?b0KjM*XraLqQhE6W%8(}KfBU)U+d>u5J$hZcr5!|fz`grbh-a?pt1%4co z|9{F5cm#%!Zau);2ZFml2U4lwlHX+kW~0}{bv)dpmR<>T8Mmf0W`9^};jYc2NkJf) z0!#arxw89nxo3{fbUoKqBs1nr>2%*6i)x6sI0-f1m)l^NhZy7LFqRvhaHkrA2}Wuq z7G5RXU)-MIPLp;kWzpE^aY8NcCm9(G{Zm#J(L-j;U@wx|4-~PWk#Kes!d#{Pb7@zf zD}8BTC5W3YN=y)XH=*X}Y!^g{^aL#=ttLfz05usqgA%`;r8%7D4~hW8#r>5tO#-%VCGJvuO1c%lMNJ~(4FyvcezL&)ft z%pTo0_a`KiVgdu4dYhs6kQ2vnuq7Q+fZSQ-Sioy#W5A>_zEroGX42_elVFbC%pKYf zAd4I+H#^WQneV<$q=2r{Cq2!jWWRtZKGNi*$inQZ{Z8a?({@RX8fn(U&y-pB`3#KIs4#Y}C1U6nZ=hv&)^XLP9ZyKy= zqR=E*Ed7#F^OR2An^1|$B6SS0qa}eX9z4-@B-ajbKM9Y!Bwr2xpDsF*8?;*Ai1i5@ zVd3pNKFAWiXC5R-Jf3X|iQbx6d&)WL7+>00US;OuCYmyr+JE!&slHhF4tm@TD}nvk z(t>kCza_|_Df(!u+=9QjW}Mf{qzPJ7LAuG|YMx(~M|ZN%lYv?p*eB8z+?zF7#RoNn z`%?tl>MnIy4@yWrKhXPRzrtYJVmo`da;p;tL-}x;a~H zY)0?pHEmhRrs10aawK<6O1)w<_7o?$F=o2n2DqX01RG;3*N7I&e+*rjS(g2-+dQoN z`EF;q9l0J5Nw8l0ZB^(_ExyiAk_dSs;YVV@RI#K@JyBM~z zzj_h_zQo(e2na8LeY<2luMKKESf2gGxVW3sp;U&5W>5No#68ORKw^f7gUJcT=%d&h zsq2aMhVq6J&f&D)tj|VsT}x&ZZtf?XfH_ICNNR#5x?U6A)aMlw#y|5;vb|B${pgg= zNa07+(-aTEPoRae@1cbNA5%ZFlMCn8hs^-pE$M8}wycXH4e!77Pj@-ko=ETi+LV8P zf?>m0$2R}z&{d>y7>}kOCyv*&*X;+rsMk6^ro`*HQL`~QAX#4eGgGhu(u5ZcOda63 zgLz?q^FPdMoTZtsS*M8Q-v0rglHJPDI{8|EM+-jT>vbN1Kj~qCq7zU{wO*kDjz+Rv zXAG<02DQ>yMXj|!2>V*|a>xYjo=Gr7#j+}e{^KCtxIY|xDAt0)B~dw~wFEdVS~wAC z2iJrcEqK#QEA~v849o?lMeQ=L3a{5#6+I8_@nPD&oZC(!++zY5IjDp9GMotK9oM?O z&w(XMDw)OB#VliM8*JFGP$pNRs-7WXtKJYK`?tu<6iy)TK>KH7+PYYh`sA)Dv((Qu z>>~JW(=0WQXp5FXEe-6;^LaEgqBy~oL9Y)`Mh9F#0YqZ93i7Jz?>aW5@=)0*S3tPt znyv8ia~>uqgGFcrdz0zb`N2swK?yxEutFXfzm90g$fck1QwTzBB_tP*j0tGQ2>I{FsatA_DW*Jzs-D?#`ZE!T@{yB&xa;A;p%U1g5JXl*L0E0;ltH+JSxkUQ(mp^jB|KSLnU1Z2L#1QoTFI<2xOZ zs@Sx8-Xlz-gY!b~uSz$e2elh8Ce>>pUlG+7vhE^at+c}4stq9&clz}(ySDlh(-TSz zRZr}yJ_jzNYb2DTNKvWW#%0Czqn$!h?I`-9OngP~aH;*gYDd{#``yJIk+{*{L@5Bq z4}wVI)Yd~K){%XjasI*T6}dE1!nYY0*80DQS-*hbOU?o(6*Z0qXOU(NU>rZifdaYFdur_sVTL$TmiCd3Qvc+Hs|)_obV0$$AG$t--MVn$$oEz zW~rCrAh|5GRYK`KrXw?p*Qa>!w-#40BU$2~%7sqZuyM{?kn3pGm$*WwHzD~;uDYe1 zG#UYrI>g`R2Q?I__5R#R-s49zds+*FJKrtpPg?(6OC3mfOGT!2Id=pPud)Ib@mY1# z#BG0CvK90#f>$4GE<pJSrB~U_ z^p=Y7lFtx7o-4=P#OZ&X^Unu2&={Er}18wEii7J=AsLB}RB~!Sg|sW`ZWJ`}myi>H7CV zU{#qC?v3v!-3yE}Oki6Y0AX`N-qmY26pqkc3{?ZP(zKN;1^lCP1ht2kp>@FFx?vA7 zNT7qQO7%p7X#Kg?#&{ytF;xhgc+&If2}S)x$^Z;%`Wf^ zE;9|J!$H?X+qEhJKL%#>(L&w+j08zO+!nuPYJ z?rOI^8HaU@9KgIY)y*bRdf^pcXpyEcS9c}}P)zFz(YF8HcdM%Znp1zCPAdhYq(iP)U6p55~pD7C4EeCe2BVIj0OGRKSo8;GPvG-E*5ic!9zEBl~1H zL7=Bu%_d9*Mu44^NK^L#K`6iW=0YZs7?J1D)eIQS`oNTKSp%hIdyF)t!>tLJ z(J1LRki@c5kN{j7006?xNfW`j@bbO6tch3##G~caB9`!;G6$Z|ZFb{wC>u4!foeIq zL4R%kfX7V)x@fG=wRRR%+{R}BoS#wsM<(mC4|E5PV@lo*Ozo?)pT&YmQr74Ru_q>K zRzbk?%^)|r2Rhd8LO&8~l!2+X)W`7xqknVy!#d|(r|Cbyq8ixu>$_iMs=&!fpr>DL zmEOVJY40Uu1mFMx=I zp&(5aCy^*U(03H=EihEKw<2uvCrGLVfK02%-&~(*B>Dx-d-q6>v(T`IAw&dl)pnWX z1L$GbDsilkUeaSQt$K6!D?ermz*u*-ex1!|PUwJb6dN!4J76uXsf!sXTGjINFah5g z^6@PEG8(@ANTT`m!Gd~FH^W9N=YP{ZknM?fwc(pPqh5R)_KVGIk+f&Z!6{R%(saG~ zQG;s|j*q_!CW*ujw0%$Tz#IG{Q%WQMZy}P%FC1n4I>HpcZQAhvBV(=kM|PIPfJk;N zRP)05m39q)KrxW#8hPz1|83DFC|W0Jo&>r`z$N@6TY3sCMDRWbpaB~440s`2>%q|l zc+5f6C8lJCflc;#Hx~G^19ziVyt96t@yjW+5zZN%VLlQgrvIIomk9i`3&+{O6HMwX z?DQ;@`$zV}4_KhxqG6Oj=%F!)V|%%4R{uo~fgRiz5ufS_0^QtdS}zLNI7#4_dYX7` zHej04_F-g5TVxcp{*)w?-D^=(Tm~FvEj_SWk<)n>uY7a9at7{H+gd8XEkwlc_>Ka- z47Ugym!Z#|Lt@BUJ?ljB$o`RaLfY-%{XmNbapYc188=GdY@J(Vq zJ+t ztkck6z*d<4(vafHY=I`fgpfCV$Zx{v$KOR7NCBKvT)(g4KHZ;z3Nu&Wnf#qsGF7ETZJ6#)((2C(ZXoHz?_>0$g$Y>O>bPmV7-R z9HHyKVW8vUVIsKyOYsUHncQG{l|JWkjaNUgZ~>WxiT=y>g+B+Ehlu_qxFSitutA6C zW36xtYs;Y(W^`Y@w88RoPFjK_&`cxJ$m^&yAl}_cSg73jNA|R$=|4i-e4WptADF%e zPN1wHAXA^u{36!I9x<^4jRiWKSyglrwz94@VJlMp8HD;eTNqEGG{=JmAK3%L(D0@y z$jRXTVCiM+a&AamRNo&KH{fR-MA*Z$+!celUuO1h;3J~8V;T@||B;a~&jV1aADZ=h zCzvE-4c!-!_z_G8!|~A^oDP>QL?Ii3!DP@=>jyw@yKTA&BAc@i!uVnQ+d1a5p{Vji7z2GkG->08Cm{xZPz*<-p?V4a)0&Y!Rr6x>s z{yx9Q7-mj%Zzt;}Ua%V151vMAr$}tU+W@%BNQZC@7LDunfxPz zlT^#;NtB6r1rORGzZ%W=_BZgHc)cbom3T{W(M`ue;1>OLjijt=2@H(J0rts09QXByJb=c6@anA~gqyGLy;9q9plNU% zSN?e*tj}XR6m{Bs!2#Rbvjh$c8C}h)g1GoTagiqxhu(?E3!1Eb^CLb5rbF{;CIUVG z>PPKDystHnAKz{ekoA4s2JIG8rj+a-Z>j!5Lgm6H-dL{RHe^Bo^AK%GxEYWPlx98a zzI?p=@Bbnz=w&BP2pH) zZQg)(6B-A%Y?9GlB+4~(FHQ-%RJ>sOYJ4c`*W3 zuK~sM!BpIZ@!K&sHFNrLEg))NE5=<#YcL>VAX==HrHKq#?Ah66+AjM9qW^CtHb$m%0W; zYje(b@C8{KV|Z$txzsPi?@|yi#%zU#8`8dhI||V&#nTWTcigAVXEj>ZNjer<|T)Wcuyyi9@-BCM%oYjOq;+hf;( z{+dH>Bhtc#)~O*XpRIXX63?$JDqF1AfCzLOSm13bEk$DH&DX6xO(rm zn1P-`Z}5826%pgd*@(8WnFa+;6)54VRdmL-Xs|5V`w|#cfj8Xgm!M<(PTTXS8L|81 zS;X{cK6uIZQN4rp>hPw^#uEFqp)OdKUys00`86~54{mtc*@t9#n@iet<0CnEQ}D#U zGjd^;U;v$19~FtzFt&4i;{XYa)xj?f(?(0g%qo62v7kE8%uQzjtu_=BVQD!xr~t^W z@FNv9dpOWtx?=-RScee|uoE#R-0YlV!nN6x#`13G^efQiaIPQ5(0lKEZ;|51E+*5? z`jM4uCUV5%T%BG#{5`Y1r}@4B8sTCGuH!n|MZ5vPa+r?K#iC1IOT$?;dN#tXlJoxm6_?^(>7>#NTsgLWxK5h zEEM6zHIoXyAJZob2j9Tv(qI*IwMu$I*t&RK_pR@Li;}?o$sta9^ft@d?Q0Q@6K4-g zd3L{FR%Rl(-xT_{`|TqlEx^|u_7qOmzXe&d8bmkC!<=fLtmV(9LEFa5+0m*X``W@M zySF6L5M0(UHS<&A)aGQ?WAJ`+t;Isxq}+1Bmp5R}W1${{Rj*39YSQl=GWD&a^kHM? z5I)6HFVBPTOM~=CaTjR;t5$D&3(fbNva6bQ*AK8@^i8^3^K|%e!1!Zp{~uLnqgQAr z&1>D9e`QcSipy*h?gGAKHVPx)lncbPHbIA7k`0LBomcw4wQXH5O4#0%>?+d-ixX*^ z#E?Qex6IKhD&^2~X0@#_`^}j!qRsvuQ{|M8yqQFa2^tVB*!&=is04!7O`?>QDtr%? zbD@O0I}-v%!%C4}8P+Av$4@b->*M769MAWX`yYc>hbC#q7}O6-BKa4Yt0sp^duPC? ztKNWUaRGe(cM%gtzv=4j^1ffS5!ANf8{_Sey58-uvMXPPo6CfiD=d|m*9dXfUKW1S zLYtF4rX290o8>?fM3*D`RG|Mh$Ex%v&~eP(`HZfXh2vC|E*#R%R*+@wf=tmaZZcCH z&9SmGUv!R%4ZChX!CY{FEM=p60smL_RwV4Hm*X%0W6ZbXQFT1$=)2Q9KS|0sr-5+) znG;d-`SI~%lMD?PbT7EFG6(!nSgrw8uBA8eg%Y=Hg%%VOim&v9&Du^CGg)Q_!bX z_W2mjX2C_l1gM65^@#1tPUK2ss=BkK^cB`Wbhi2M{nA?WTn?^0yCJQDkoY1oyn5Z? z58VefQz|wF*C8GUB^XOj+!YU>7j?MU?BJ(}-oFm|*f1ojC+ESFf=H1&37@3$S2p^z z`eg6TXx*>)7H5IBpPhKhtX*Mz`nFb9nw-8P<=9x3^=5{hEGff3 z(k_a(&@%p#xDD=cz>G5W4bBDksy-$4D_;8S%|g3h3=dNB-pVoXoFM$6gW+uyaDNN# zNbs8aBqCC{NiR6EF1<{HZZ`T-`og1KB$g+AIt!6S2o(N@zXP4P+$2AHkXYq zPpQoD5aN7x$v>1-_llnARv#2EifNU#sRymm7&j4Sa;ixngE*}8lz2Sq89+O`MwSdr z-o#AK@aNoj)OmYnb0fhavboeHb0M!}Szu`bHU~1z%X>d)0lI?WbVs`@d((Zlz=wt@ zPZk`QKiN66?txzQgH8rwR#<(Yw6jZOG5s(VB%dH7;a$d8@L`UZQzQX;LhHP`^VD}5 zU(Mj=)LdbyPx_=S8M}R0$VlNRHW)}p`aN&lMGxXT z_pm)q%?}Ecl)JSQtlz$hMr zVt*m$HY1J8yad+YeDK7hBCSwD58Ra64CD0~GLPg9S$c;7#IP@NMu`#Cjf5 zikXZ7vB>l~#T+$UENS{A6a;lMwQ78pV?xQ|NySkJQAH>qHmDojgKvoPSY&exKOSpJ zB%hja4H%rQiCM|iJz72irqHuy=jZB8Cky6W;T=rF;ZdVCdm8Qw1)JDU6yu-jYM<=f zldWa~QF844uWD2H%N8jNfuo>>j^Bz<1e08s=i}-(g~UDJrw7~2{A`V;)r3&S3;kkJ zEfNwkYk5<%4c-UBU_ctQb|M2euhit(`5{d6`YyT|rmn#kmm|?A`8$26E{%Q=vAajm za19)YM(>?#0#i%6*)Obb7K?~}KM{}Nu>OzWnREC-U7~1#{8fzbHA42tOzLbNZfR$Z zjhM#4jV_jM#Da#5H+V2flc{s~{mR7bEoi;y)#&DT?E%U=uhJ9@!mnYEf&jjOj#vZq z_UvnM)OXcOX-h<>q0ZIIcfkS)nANlLo<<^29JOqnnQJysJ#Ujvny{3lXCxvJ`iuFd z7|X&`he@EQNFM_Ii=){n6g@9G@&GIaozz6@V-GZA%>8(|)SWwVQLIh7;UEVW$-3)A zxnHy?_U3{*EwE?{eA+p)kcVJA!M>h!ONTkVnQFDC^!>!wnuH>-=br-l`BtKnuXiXG+CNQ zc3Uxp>o7YCWDq$jR~b(nb|Oy8W6syl26l|vll|I)EMh&FoH&vik+W8mQjiW51_kCv z4QJa8RYhTeI-l;&g`CasMFfSnlxSSh(@1Eku=#-}%C+@b{z!$>&IByrudxuF+jM@# ziQbz{n}n6x#?a3AlzpLsMJ#4V*yd{dY(LTcr}{lz*j$uqhxHbWd#m%%|8Xo@eTJzK zN6-pFC*Ya(w>}(#yJ3*q@N?=!1yC;+7l+z%{B6>BKhw&~cYqxWrA0 zV|N?e=xV_a(le7qD@lD&bGA1W+ml&mN)q z`>P(IflK9{-W5nkHCz-bv=bk*P8Wfmi`*sR@aNb1!&isH^gcTTy!?CHC1WhptWo!akVfiU}U<6^MomS zF6zP~b7!DkxE+(C9m(}|d)CvNdb){BjmJGKhD=-@XfroQ$<`6CgGAOLk<=gF0)`N} zLWr0M-%N_J^R~l1jOy0|(uX+~aZ{(D{FF0uo63D=uygwtby7sS7(I{rf-#eR{>rrc zyOlV|{)azwl8&&r+bF@un?`F+!o%`t*O5(T2F}|kzBQF2mlU0^h3I*UwYvreK~H8d zGSHy{vVOs%rUG^gP2R^QE{+xK&nuQ|(DR&M6=_k18%7KMd#}mTocSbW0P8Tl;qN4zFsQN)bUbS1PAh25<`;oIC2f z*Sr29dT6;MV z;L^;yrQ1?XQU=Q_hY|9Alj!Nw8`1T%1T7qE&}aC<(rg;#uT^3y1u|JYpvLSEzA<}R zf?U=l?#8Z_P@id|3)XW2`)9ke!4pD*U^n)ME~d25iv|T!+CvXO>z6-)flM78cjnmLezN> zkKWNM_zuPe$g`YaSUz$h7F=&Beee;2+Y5A>%6o`mXYB9c_*QT>XO4u-pqMZqvr(67uv}}5|$)We!c-f2Z#r40PRjP!^ zw7n*&=~}U+sa)+^5Pq01KualwQrPI{2~i%ioPOGA(4c3lT)woObaXbIqBL-s@x|@u z&Om-qC1%D}l?&0+=e_cv^KXj{vY)-+t=riXcllEI4lTKl4wbf!D6ff9Hzn*f&zvSM zH-unq1GW1+PrqLjskvivDe3mn3w73mo=)-^B)dfl4x{o zWj)9kx*X)puB?8;JnnGsH1(zCS>97I)b|BHZL*+4pm%O%qOd$UHHfGcO1tf{U#8Gp zdupd>V}z)q@irjgw>kQk(wv>;2SaU%V_ObNyTKp2bHW5AuW7Id2(Y7DDs6;cSlcZB zp?j5*tx!*XHAOlPTx@a!z4_%ot?Q%uh8GDSmHn0Y6uA6;KZM%VLMlepA zJ@&3r#tS|$DuBgz4;uf1&t)dO+u95<1fQW*G1d6{fky%m9W-ffPL4<>T>wP8%%!)^ zyjJN33&|t}8&nH|kq)+|nre(zM-vrb>;CllU3S-8{3|MsAfPTeFQ8xi3hT!O!sEa! zP#;c>q;dV=*Pe|0bb{x|8Qc@)rmT==ZMb2YG^g)t$$J{bbD(zsMTaO{Uq?KU;#b;M z?x#3q8l;_D>`)Bd{YXFd3ClF%eFB(`s%NZ8EuKxY+>L6X-fF!dk z9@L`PonF}zYxhUHbYg$)D53Fn?;*?h`TWiZ4@$^98Oxu>cMhJYu$FM;<)yldtbrSd zvg2t?=sxC^mL2g*|GVb|ev@ItnUtcWavSkZ9_rZdoju-N+3J`z2QmHz44WltVn&{z z6K6k4kvd`fRkT-5ZoR^~O?mxZqnzIN9wc9um!t6aa{Xj^*CjDc}jh zribCT@MfBjefl{yboH$Sx0NDJyvx@Tt}30kkI|Lzt#_ZSN?-CtMwQhh<$AP?S^DFj zh^-iBHX(uh1;iu-zg#uHM2x89sF_Ud{%P4R@FZ_Y*%;F!d2|ea7uh_&W{`9CU42rp z9N10?i&0F3ZoxqG5B&9WjmUR-QwVj$di$cePf2t^lP025VLlkqQ77+tdg`y?ef~SI zJ>v4V^(5uq=wzZNckJ3UIWpbTsqx?k=}@!=kTry8#~mL96ac%VjPzI zWq5g_@?NJ%(%Y`s?Wsy7$>jKy(RG>-Foj3FtO12-bV^<8JENS2J*EtmQbP+~i^g)M zNslgcO%6{rYN4UyOf z)jxfhsNBR3Y=9Dl12#XC)BG_W%0JT?Ka^0>|2LBha3JJ;KiVTbGOnWN4NGi$MSN@8 zT}({Uk7q!Y&E~$cX({R38f&6g0(}9ju~FEY%sYD&+apqUy>F=;+>cy=N}U6ofl=SB z?9%XPmcGUH;L`=(&%G?4eze#NkKCxP{UT2NsH6$P+dSecG;PC41Zt6FC4%$ud0=wh zgJLb-_e`?{}gjCN$UpKjsakuBl7EA0Sz-r254z zW-*8=3&Z4N>9NLE2V^uL2HA4)&0SS3t$CT74kQLxO~n+Z&U1TFx?@|r@nl+6<+bWE z-})joZUt{ZG-@j-f7<$&*1WQUT2bf?9j8KTn-Gk*Yj@KKEY2tMa8rpm&;o^&HC+ML z1!1k33g3QIm^XflRZlLuZfd3!z_=^_T&ecC+0S-hoP3>PN6iFh3JtuP5&JgW7Zv^0 zCvV18>5~gQ?w*rJgtoRxcXP6`#-3d=;T`EQwF2#iU@#y;o9p8aU&)tBt?N1@ffXUA zH@~&t8hC$>HmXy)arjNzJEX}{n z|4ItVgBcx_`L-awGHxm1VO*_qJ00UHuZ? z)nl;n;sDCo(ZU1D-1xM!2E6h=mdAj~p*`8(%+K8H$#RKrgtx$};lX~3$9@!ux1ZY% z=U4p*k$ByHUP0?O-8auc?mnn`^g%%~jDMpiP^>B}AYT0aslt+5U7U-j1qngR4H!nG z4Uju`5=VFm6yF;(r4JRX8hL$w?==5m(8Rz{-p_@l(JIRiIWr5pu9xf61~RO)FYDD& z@v)SFJ!tyg4{ROUq0ibnP+Gor(ZS(VLp6z^empKyn&b*C1>BW{E`9Kp+jfbV#@G*( ziL>@wdPsEu72m#~vc{KXz9sA@R<0QaL4`qp(PcIuyxCB&m1l9-@!{Du-aS=tm*DcB z%(67GQ7#P9E(E$Pz&q8l@3!Mh^|xD%Y-LkWeJmMlKhzsKVT~g8E-#cf5TBQhAL4x} zh%KqmiAz5i4N_r6&q{joj?-DSIc!@Tk{3;})Wh2 z^QkU&s=c4}NSOyKCsVxnWfJd*NW_gCr?`VawT|CC8vKtzvr$1Z@1ir)!|~c4WBCr)zh^w12lZ=2EJkwCK#| zfSO*IDphq5H&;;KH)6+AOFRs>AKg}0IH$Oox|hyQQg-;I-WoYEtUNg?Y0D}GiVoIn zon3%T-d|A9(HyH>mA8IuZ(zWp`YSDZZ1P5LQEkM`#3Re_;gog%bv!r8aJ74q0T*`($N{TchnEg`~%&n~RCL+T^?l0eVCpW+iTLc{1l+;p54O{^Vk7jqI(wxO0T= z{J*({aX90f2k|Kxf3-x@QJcX~DUddap@X?dzo_qzA{yJ^RHN68)m86&`%ueT&OqI? zx$fnOQ#|CEvWuHX09WCgt@CJp3WE4y)UV;S=EWXQR&Y-0n~?a~AJ>GDoo=4~(h<{H z=gfR7-c88$H?gB;&=o72p@fc=X53kRGa#j8BXguCGh&+J-0o20baq$H%jFV$NhmLA zw4F9OTe-72PTV7*h8rd4N+0dDOjaj`D8A41y(!-AD^l0p)pI}|!RE)jAzF2@UZ^5(ojc7fa?G;5H{g`&ks-Ux^oXa&v%^o>F>k%R|JGK!19L!gA#IFf zX0BHePpJA~CN2&+R_SdyC)&KNm))6IzB;d`Ztel**znnx$J?c!H!{H_ZYq6yzvJ;U z%UszX>eWfmEPabmegZ2aXIU4?`3Cr@22Ce^uO%Y&-sz7x5_7_KL^1g`Es6%hPhdk1 z&bN(sT$Vc>5U*kENZ-#$LlCj{s_F8E=^ci@DVc98oW)1@w6g*7@S=7W%hX~j+7pX82=+R7P>9K2h7Rw~qQy)l(K!FgVL zs7Ltt@>LN`zU7C~1;lBfwKudiEhxPTDOJ-MnN2QrrbyV>KpoKJ@q`zPj;^076ZyTC+b*DRZ{ydAWYh+ zuW2NDznoFV(!la>l$tOS$}4 zUF|Wcqq)S{Oe*{&&IhVRX_Va3t856SEL!6tp$(o}P2M-X8HJTFiqbV|VWt zDukpdbzv3x+?~VN_uR#~hR@+^wc|TgWiKb;FDpG2mrZu9E&ht=BzoTLLtR-A*wPN$ zLw}$`=hdZOx4}e$A_g;@18cl^=f*m+=_|PH5M03Lnrl>X%X*Y|2w}z{~7vUU4D1M)bq|UyGz8> zn7O_io5r4bj7dbc@+S9ZjMLg^RiI3)tZ2?A_(vXUc;1<1e1XYNGLQ2exdbPRD~H7G zf0Jt`(YTxTO7a_$j72(rMccM6Su&tX#$6x-?@p&V^bt8An-%q?9tTX~>&D&x#)wLM z*MP>XBw|YIwo>gn5u|QrU#PnXEuRsB(LJU=3LP$!+>+iZD=Qt_KI5p9bV1~-nUOxb z%84j0vJUww#fO>#Dqn8s0hT4SemkzgGOL*&miMMD~jP$CCHh z56>VIaMDYnPUswv_#U`?yweKzKjb#GlTPK@+A_NG=28gxLBcj=wly=a%)r&lf3_U# zHAaCX&5SX>O2Ej|!@6aI!)C^=pG3$@_S(h6Z~IF%Ti^v56*`dt0D>4!3M4jy#W78> zPQj*px1uLkB9a2V*l*T3>iI9>&hwzpe<(gVvV*iH?2%rLHE~V_hW(*4s%a!FSl@iM zJN1e-lz3wsAqNcDg)8hD#%C0+Cx>7RD^u4I+qYx4j;bjahm2oOqOf@&q5#FoqQ5Z^Zb1y8j^;hwy%eup<{&Is15=QI zyu&#~rX%gZHf$OsyWY|y;m+eD7(rkeXU=PWHtU?Hpe*7<7M2vTiuME4{?J{14SE7? zbwONd;CL)|D>s6h#{DaB-W&m$b|*cebS)^~Wxm+;boMHUWAtdCE{lx@W({>+M<$H! z@KEdskOXkby;{`VcES8C`#LH3CCMt5z3<$|af98iAmNorJafXK`y$v~LZXIXF2<8u z_?)Ww+4EKi*RdwPS(5!4Ion8`ntF9OK>Z8PA$CY)g7);OyYJD$xI#9(EfZ{(zw+xz zYaCIywpdq}F)$!eAsgU-=qxg(VfqE6{#_LjQhtBxf1F!ScrThTu7W57k|+BKV!q!W zI#6KMYsQ#iy72iAcE!ZT_63>Qz|b7-oI4?YAWemvq&b3=%(dCzYsW@42F-c0i+ggn zUGTrb{Nds)rg^rviK$T7VM3|-C-tU-fk?DBZW5+P&811MsSZT!tc=JD(%&inQj_{@ zcSett;pKEas7Lpg_o3U$W;i%PtnfW+ZQ{+TE|}HP?}ZI!QPhw56x`T#<`J^fr^)gg zS@t8<0Ur=zr6@m0IXa)~A^8(hj~rxoCkS+$62ks{ihs4S7W82Qsjn*0ll;~IbMY^5 z-^dIh&pw;ni}QYf^Evn0lN4Be;!?Z~!y*-IHUz@g0mxzCF?0#dQ|uC$Ld7q`cwCj5 z1OO*I1kkODLG!tpBhGJqpbb`MmpvR=i68S%dD*K}uPZxHRA!CGY$*_jK}wdVx-9V` z!%umtwn4E7`C8QGuE%3qe^S5$ZDH4=Z|=3gGh_ulXO5EH8GD@-L=#Fd)$@Myu^8#) z_ihi*y@W#s)TIS!!ebn$|1_AxsdSKaYgZe57?GJ5T-lz+bzK}4l;Zi&=q!@jA>&SD zy5DHL7X0ex*uI5RXnvKNh|i&M@Penuj=ajawQK4_59Z42N&+DlzLj8SN)m|^U~Aqv zrC+M2IY*W_`!bh^j*xe+69xyx${pFkQ`0Rwd*9($MyVRCDO5xn`h+N&!`Y`=^wFSQ z(c-@`Yx<8txc|N{&_Bcf?6*$jos; z{5`HG-)gZ9e|@LNj@9%Ke&*h}>Zikf-r0}%>qmEu_Ru~!1#(RD!G8%h{L5eA_;GVp zgGOiW_-V6R%yVTNYBLromj%;m3lV(MZ?1IQY$> zF*(jd5qiE(vF;Wvj%v1w@P_E4>b!4Ynj}v01qZW~66NL#HV2&ukt_4JbFPnUORQ87 zwulUKIsJQ**LArpvNOb(g2<)uReHbrUFEuQ_Rz_S1@!kIbteM(yAascdf90~({mqZ4OY zcFRfC?5dy^psr|pav}8(*!7&p`nGm{!2s;BIcmxZ&gPi?>TXeU^2=nbH^e z?%En-U``v!PDCB8Oo^kU-#ky%Bwknkp;M(kuB&zoFjFUC!}__1P+@XS3-8k<_CItS za@kUs668W=UW|iy+3G6|2~58{?afsV9fkwINgH+L?H>A?;q4;%Zyxw;Ck!xKH#G1L zZTGv>WT?Pjcb8L{_VeoMY8$e*%ko|GQ)1NWBzmojL=F^=Z_p7;=?T3q`k|y3 zOyE@PYw!B%M)xT%ppXIb<;J@c2xj2}G|O~tSX3{$)8uEF(`k2e8&JNmESTTAa9dIT zw8kBjFPA%Xb?S40zU@FH%oCH=HpBDaDAz!RZoqfh7h!;EE?+%%*(4LK?|_P`RT@uQ z+ovSvuJJBsLFJsP_Lp8rR?zYCfX5H}w;O`&hKKapbi zK2_S}xT#YlP(P*nW7&gW)A43^8SImB+fJM&Zxe7Lh=9IX)z~oV2j%n#kS>i`owR&>=%cPq;z!T>h{0!9&5N{03LK6! z9({Q$zW1oe_lVCNcLJrRZMlt-oatIA`0*W@&4D}vkQ+;}?c}cE!d?{(>IP)9*MH;u zz{i3%6((R8)J_&(fPs-*rBQP3dgkzNT9qu3I3 zTI*L{VWB1?S1eO47gYjwmz?g+04J-P@3#%Mk*|*imA#{wuB=$ZR`8}#9Zp1$Y|8a0 z!{`tDTwDiY%QydTNu&NTMP&Rl^3Se`4yy#bHvm6I$N32l_26b6 zt_Q7bVm+_aG?z-LSo_FLe<88R`5^9$y%l!TW0o1`0!NZ^{rvyXdHp|{uW|v0phj^) zcpo*RQBnpOq$yr~6cS)*$3#bSu58e_MZQ<{W$01RPMK)DTHpdhUXbOBzh3w~(rrg= zAQ_1fhnoR~lYx7rP9Q`5xF)9bZt4s#LXqaq!Kz-Azgr_>7%%f4;(KRPOAjL#SkMAv zw;x2wAWeaH#0$(gCLl)dTkWuC?#N;-cN%<{vGTROckTV$bI5P1@TCy_06uQPkfQ6+ zOw`AKlLHZOw2qNLtjcTEov{^gVb>CF>bESC&Yy#>c?o1s^s3N z&E$|zy0IKyD_-N|mV84ur`)&B?%g6)SdLO?Q97vxLoDlG5dP zWN@z5-X}+V*=oYWRq#A~b)_u?X8Z*#MLwoTrcR{W%mTwEnNDJ1=4aoq0ST)2rCE$rSbZF)~PH7q} z6RCc)dA)2fDS!A0ulB_)FMKBTN(TssReN|pnrP(aq(bSP+S-(O%NZ;-BrO>L<*4hz5tG_$>O|Fo4lsW z%*kzkctX$#2+!x$9MnO;${0>5CK$T9KbNa-4%0+?u4Et`<{QjAQ!ZrcL;c@u(^5hU zXd^;52%RmnQ9_Ia`hmwyXVOgSM+DyQ7Nj08{65i;S~`=zz-)jPrLFVd!V26F^4RlgELO*YFeIVHTgsL4WXB; zS8`hdY3^6X{xKv$b%>^hyajyoQ1^tqg3a>|FA-DYKDnuy#RPd>&NN->hRj^mz0?$m zD|*25mt2nO_<=beMnuJUKGx7EIO)x?c;%up`Zapj7^(M%&W;;;EHNHW>yqt+em90l zxTx&?I6f-1lOHEPLxXS}`H+xn=oUc`%xf%sB)9fid_wcDe|aSS|HhC1SC+W`jQ+3Q z=Ni!I!-5OlG53?GfJiue^-B5i+CNu#q{obCV&|ejR_Y|7BQK1(>{$Q)eGP=CAEK=e z>ljlM3;_v^lNBXZ`r8p5oW41S@$PI*PZ$bclhocbmPp_jtbefeXC^LYa zh82R{^~tJ|q)U-TuYtF`SJ&X(el7vkr;1qu(PZyVbUBDDQnz+52z-Z+h;JyKP9ZnqNd)qH(^PS0r&Hp0z`fn-Fx*f1K=Q)U`y|D44_11TT~{}Ln}hSN zf=ZBgi1JNW#~wxU*O}dSDi880G)lM0eCH@*i}fzOTCI` zVp(XmG;k@kxM(fuY~|FCQW5jteAjr-Xx7~yduyL~%_3}jd&i_cm2@0XSDR6zo+KOK zux?o=S~U8W>)4a{q60&?I}k2=bdwLkwJvo=McJYNL3w^`;&`aj2P^l>PZ@7_=fWkQ zytu=MSIaXU!rhOlmwy+3Vug#q+eseiqLB!}%w#^qf;Q9>y{UclRgS1EV(RRrCSgaYOvlQ7aXAcR;Ai^(*O zP&e>F_3wE{@1J4YmRnv{x(*z@d(pXO$4f?{2Ekz%XjfQFwU8L#^szemqpPZ;IkU*% ztAhGO#~>jcChLe9F5iJuV5N`i7_%bpItkb0{a85iPe;$OJLxI4NF7bSG3%Z-b24l) zfOyViYWm7hns)RBiPN0eqUCRasOcH8NAVWsK!o*WSH zN&Nmq_OQ0k050I*Fc(ZcO^ubLO}Li)e*b&SP-w}n!5X(_cfp6YCVYTnk)(YYH0~uE z1Jl_SoP+o_!$)cqy$7wC!io z41ha)xbY5t%J`f`-!rN9#x=;!mDuaZWz!^{6YZ#mG%%mlj5_jcU!Ul|f({HPMG~`X zI>!+#6b%a@4R{;=8L=?>tPsBgUq6}gY?PQ9Y89J!0B(t#%Y(>E#lS8zSwrj2VAYxZ zi5#(q*K+>SPvn=r)_hc9JD@c`xAg)4lVw=DuEW9?7~lRBs{|;u_RGvTW4r=b|ImT3 zk;Ypz7HRk~bV!IpnpC3mk<#t$%Dg1o6Y!a!ox1xr%Vh?~90My@-}EZUH2f{GXDws8 zdy>URbv$D8O7xb8lvUqKEH<g7^HMog250 zTX1y|-kViF4ocT7K>jYgZoP+H?*o^zVWVIa>}ESKANwFkTwf#NV*{&P7?9&nQ6rJH%VzPYwQN+M*MvU=Id&81!XyYY!Y2*R30o7}D`H!A7)wesNK4aZhpmWnxBI<@@g8`Yy13Gvm6xXxE zk*EMcJ)Fmm0MZ;#Bi{^s3JOzf=c991gR3GwE7WGB_HQq%q}%F<1Wg7wDS6rKwLc%& zVk=yoxd!kOo8=p>N;RtF|9YG}wSHcZP`Y8Gldcppy>9Gn#ox5-#{4V<20}yL0XlPV zYVtf$s$zbMpA4QZZfU!Q8hw@b)e~guVxgH{J#JoofnXytg!umM<*U%9dHdhHXR%9Cd5^EYe~%r) z#KJFwWaVZ8!tstdlx_V?U(VSnjnnt6a#vsznroY2b7Z%e<&(-yo*&R_*fFKA(F>PE zZbUv+!4Aj;&T{O+8X7MpN9xZWX5@S^bnC6-88C6j4@||F*Lt4=9yOcZcGgqx5V)|< zrQ)2P{wahp+UV%ilF%w;m|i~R_!{l`|F(u7azN%loDn0kRNi&Se2hPex)mM7HNOJg zPJ&qzM#b75aO_bM8tkq*?_KoGrllmwH^hW2bJQ_j48Zml6;EJRM=h=1-K9{e6{S*_ ziHIm^F%_~=&M(1^3B%y1&2Tad$qjT8o_E$Dc%|XZt;Y4C`vdF-PZG5g_#$(DNnnI2 zFE0!nMyhZfH-UJHiq4;Z=%i~~X*z)zA`kl9KEE+j>t`Tg-t3S>di@EgbWI&lJ)yDG z_y!+%M^NBV18h=fK0bFIGlAA2YJTuzO$-QGU>RQH57S>0d3xksQ8bY-KH0EH(rNDC z4scm+%JQF`QWDUOT3#E&`Ilnnn+UYmK`wNWqx;FAdu77Jc#0{KSrecnduL6)F+9_tjZA+7zt8 zJlg0?BZHi1X39WO6y-I@ib8NN4&<+5?T_sLM`!P!ORpe2_@9#B|32T+|IZTE|9Q|q zB?L0xw;)(9T%@0=ljSo_TyyFM(h>D4I}_!`O7o&`=j^#L&_e>KQuC9>8N!f`ZX7v4 zr<>X`X8l`_cqqa8%um{YCR6$s)|_jv|Jv5Fn07e=t6{F2pCb9YMC)SuqgA+aZuorT z+^stlfUl!B4+w=w+XQ_eBWT{;kbb@|E2;enmzH>smnx1w8XZVBae%$-pnj$)pjtCm zUMPT)l>ET63ZVbK*H<9(4DE*}ce2clQwi4{r}^IY_bP5pU?ZEDkS@fP@8FbP@3z?} zC7i?P{_cZF{*O7QJ2TD|O$&g1bDv1MpOx|k(-pA4XyT}GSb4w}Kc`heJ2*BvSgOhH z8uKsP*OHgg5)^WI&0En8YjzrBJJk3jqFv)g>s-zE2Ksqe`0<%I{MXxThDCPLlD__^ zJ$q`KMhB_KbHa*^$AX+dx(G&fX_RvSGg%!Z{4=41UF+-D>p2fED}D`Ad-W-D!8u*g z%7T3zg@PNpfRMJ=N8$-I}z1X>s8NHJ@t?JCAU`!GQ#FRxhogo}dU8cg4k#N0LK^(Oze+yO8~ zM+{D@!P4z8K#V1!wUThy=B{zyWK5GA?I@LB=H^cnH}>dm$Pz*S_BdGK8Uh$e%+#zV zRmvqIrUUWPPGM}^kdX3iSmRrJCa*|sRW;e51JW~MFU5I)9fpe*9QEwjLgTR&&x3-d za^%Lj1f8G#lWTzng9Kkq2vQJK)U~!FM0JRtJ>XXhVO^&6UzKvKcJT2QvGKZN-J z4H#d3X1pK60r_2x3Z_kd4sXxlf1}&$IQ%O`gZr>_s7Wua&1& zDKqAZSc;j@U)f6M-@8x@QP>wCj6C53&DzJI$rprwupJb?;ih z&Zu~b{>3|x=8TgD>BY^c5bVOx6V3EelQI_b(`t4X4p63 zg~9eo{Y&+caQ+lQiv$}!>e%2Xr6xwg(o&w2aGLS!6xl;)Z&J~{t$7ZvQ_7PwwCB}f6#;9<4%{(-6Aig^CwQeN;$Mxt{`bKL{%dDI|7WFvzdI*U;OF55 z+KG`JNi#d^!0Z=Z8}aVRY?Nz4@d(-;6GPjs9j`;dMgNlh3f$BKP{uk zea7aT@S7|D##;%;BPbWDwmLU==0*Zz?#^6|avhEjzd%E&!9u!1ve$JjdC#jVnbw9IY1;2NqvB~lXCTzf0ziSt zjmJPg$HJ~dGWzKbN=zUEQ08YCSc0`Nx%|J1vECCu|HE zK%0ZFad%EXI$j~20a!j6K7Q@ZMJ4OVkozi?n<*d*^UU)cZZg!O&zIrW}xXo_ghW^W8V!LcV}JP+%h^X-$3Cx!8Xm@q$RBr!16cRt&kv8Hag zyK_;uB;bOu_v~~(c;j|%DynNY9aE$Ebl*70fP>x0he351cPz5A?jr9>b}83| zGc`|miiM1HzLq9{HRaQ^a{zpf3zHxZVR55z5Scfi6RE`6b<=5Ty@+{0#z%{B`xeqv zzv|(>=#~Til6ZAOsKjt@eJHGP9cD#6_({oDYq3(OVQ{E;bxn}5OBvfnxs9&Ng@UNH zAx(}JAXaNvTmJa%S%F#im#WaW0#7wIlH%{c)vSf9P*B6iX#ElGynwZHmjz#p%YD|$ zcYFH7vuH}5bdM#CDT+6)e*C9XB5H;OD)}y7LVY~(`)r``_omas);fT#$k)}$gy=@8 zLz6zStU>)62T*wsyRHY8%GN0YSw+`02Ii3-55)UrCYbL8_ zVJ3@|!#3CE9%XB`9?=dqz>Z-0EIHsnGXn?dtX}{ojcu_}_4{gn$vy zyv{h`b@K;vpIwL8ejh(A4&2bNDV^ei+?OUj)x8K92_)9zN# zR=Y@xKXiwgIVD%iatHp6DJHff0g!xxLr-ip=R9~`%H2k+ES*Md!Y{)HB#%MLl>*44 z!JN7I84z!uk*-Z-0#Iu5x-nbMsk`2ix`Hh)I$o$RH@%|1{ip=36bti=i~^;bg^iyt z#jwJVR*H1K)Y)&~Fp7+C8HZw93`A~A5Xd4efaD2p4Sz6l0LDeHBa*FpB<#2<;_X)h zB7O;J#g*w!jc*)@nM9qLfIg&k&3?tU4NOk8-(PFuX3h@`Fc7B}l-LOKTx1Df(&j{w z{O!zTTH`H3$B);5n*>ZV?i5XE7004}_EEK!QOwC(wI(7NBgj2{otY%_o{HeikD!K* z=MKmWdI@v7llDEBHCwcf$h6yQGug6g-aR2IQ6#bJgG&+XF*4>AR-k+dBzMwe0L;R) zL8qO@Xu()jpVfWI_TH_!^qRjIZ{JxhtTnS?pfh1)`}^dSd=SoKl8X4HHh1@v%$Mfp zzI=)6T_8;Px+<^6ARh5Gf>a8sOz?T8f3yCkxIOdN?^8wsI11xQoS}oE;0NcYmIE^y zvWOh#q7WCm&cm9QGvj2o-9L0P1K0cRd$1p_Xr>%d$qv)E{vYPvJF3Zd?Gi>&Q4tZP zBSfhx0@8aTq7)Gk5l|4Kq7)G#A`&1Z2-2iPKtQQVM@r}&LhlgiosiIbLJ5(S-#q7i z=UeZYIp?f3>zi-ReE$K91$oMS-`BPGwfBx0Z~YN8ZuYThx!_eChVu0TJl!Lz|KS$; z<2BedQf_}a zU$FgnEYyK>i}2~?-t)0~q?_>v$iTga@kLG)2n6CX-~xazs``#6glHnuY6njwFyZU_ zTK~B>(?a+A$RMJ_Eb5d}tud7Hfs~y0S~{~6e_>P1IrQY|Fp1AB9iA6Ki>Ay`$f@ge z){Mz@@HJ|l^E`$RitpkU^a%e*EGcPG?2?l4Z@u(DKIx#%)95|o6YmBUWvmzfpdtdf zYs3#qMy}|*o`eSPtvlGu#uf8+Z5LS*k(avO{kFyaWJnNhF(^_47Yq6p2Jf<}cBOnW zn_Bk$BlHl<9~r{@lCmV+)>^{X;?i+9M!&k4rmLG%Z1A$Vb2&?Ta`RO+Yj~uEGt%rYUu<s25X|yTP@i_}kNP@)Tz@1U=V78?KOyL< zHrefYqGZgv!#7QNxJnKnNc~ zaUOHxNnv{a>cLHG>mppTcw_51RGBBDVNcRxg<;D0DT{TH^M{m5g_#j~1D?BO(ajsY zJnEma9K=0%>cVAZ0DkJa$kV^!i?4HshNcUzJ&2<1(gatq<*-Klgl-F75O7Zav(a#w z>i(pv9y>x8)~<|wm!)o8+T-vp*vGKqNc9aL7k$hqY@(L(i)u-`M}4U6&{Ub$^ThA? z@O$fQcGPnX(h50A@e1U_&06d6MZJO#l6-64sBq+2#5HO_?xZtVgB152V>_Pv_*FyM z=MQ&WCp@%#EYS#?0j%A20GKDH4a-AUBp8G4p+yzlvYy1p-8r`550P`nmYi0f$(OxT zO)aO{IWpC#+a%{!l%SS8sl$+JLP9rZ^%I+&3p9kZf$%=3z%tik1_c*omi^QD)u7*Y z(QU80c!d2wr!`~mBDI}TC$L3)jZ1tSS87LK_LCi3u95eSY?P(6!`{P#H;}iX=Qp>A zwT=>>ufF^7wzCCrBS6L;o5U3@uqM!#RZ*K#hirt4UhgyyUPgge1>Uj=t>slm}E#!g?#o zArPTm=zPHWDS;}}FXq}+`z}&jdJZ7ErN)}kz!82<%M;+CEFY69Vsf3m@5~9_UE|HY z&a0D^0Qqv`&2hlhaCIA+?G9Qt3#eX$2q7=R^_x=osFiarW`yNn>!w3cAf#N1tX!V& zW~5RbU2J`G?(G_NPQ_9bn{?Qbuv8TB#q?g$-$U&X1JqoilwJijx4_o9LFl)~l+$%& z-_rVEd(q^dNQD8hpq>(c@U{t2n0Y|n_Ct!(mB{D-um}=20RJ#XsAufhtT7GC6TG4g z157SP-xsLE$_1Vrah=W<3vh=>|Ha~J5;U0&;8Tte?$?~zljAE1`%^PcsV^MEPvBYo zq8NjakaOz$nEQeuxHrO%SwVufaJE(cLYj^wb5d6ZO931d3?Ovi#Yf-QN*L<^eOl{|SqUH8_W$ zW*tVnBff`Gii`dU%)KjdV=;U};$C&m23Lq&yrSWMq#aIS(*U!aVmZ+ngOf6viZiq`u%pz(1u+n*P< z-xV?MuW31d?sdoB*U>C*N4|Iy>FA?pKaD|tt-f0mfiI#k-yi_IB7nLne+pj*OHT3I&NI| z%z*!C#b!ho}Lh^*Bwm&`O%H$CJ@T=LVb6o_s8Z_BqyFL!D-SpysS}iM`{P-dYvupTCpy$ z2|LOZ2^8q6*Z!n-StEc2)TFmy;Qvd|+*ylRgwbYTvUO2r!}}{Mu^M{|#WNouG5^ zSo^z7V#qahwxl8{tueomBaA@6L%3`=o7o0AYaSvAhuQP*MN{k^1NK!L>;#ig5eX1~ z!|B&02t{gv)0OHli(*MlpYLW&7Hcl;Apxsp zZgLHJKKzBWv1_-wOyk(EKQPO%N4!%~aSpL3fY>NY2zL~}2!E(|(%QnL-o*Uhi}}f0z-{)e0@6JsYzm zKq6B4>ezq1*1!j7Jcsa%Fy?7!gY zrgbEGyd-(!Rdv*yPh^9gv}&(APW#Wgt=B)io{lJ|wad5It8e8r9_eS zT{$kI_;(vS=YINl??O}WfL1KDtv)e0ageE_r!I6P*tE5{##tZhYFD#-W7)ZX7{^ZK z+Jp3f#ek|mON@SxmQ8?!BD6^~0?rR%LrfOLJuYHSH{6N)bFbKGr&H`G>N0B7WfGLc zz-Kx#2e6=xIww*qU3=6ck&};_>G5p~Z&@^Sz8h4OFH>@fW*$1-vQ;Qg*S~mZu52i_ zklSH_3(->Nc6Y9j?^TFUaM;C67id0IbgVdTa&%Ju@HAbuRX7J@cIe!UMsw|4o9-ra ztk8_cG{p>~*IK>D=D9b}E31(Xee^*aP&91lJI)+?p6(fPeW%~kk$+_05& z-7Zdox~X7Izer9R^c~2wS!Oa4fOcto2~^7L6FG|h@E6P8d3WYsp)-Ije#8C^u!_)U zp0{QK#?QXWK&#dNk2}wQ>_(67ubvkWfA%X~JjU-h%iCzW8P$!QJEpaQ1;fU;d=_FA z2?+z8$^3FV<;qYPR}?dbpW$wcrC6xOr%q^ki@+#Byc9~e=8~vI^jT`Oy?b zezZ)DB~jGq%Vd>=-0+2&RyJnf6C=4c2~R^tdze75_qDKX)iN7TJ+eru2!=pg@esQD z?!2?tv8alnfFQHa6BzZZ7m8r9kukyHSoO=+olgq<>}Gi zRGP^%%`FsDG7LSrOK~j|DnxkN0kfd!@8P~5ETVhJS8W<)(Z*CyvI7C%76D#1r+OAz zugAqj7WarBBM1lG)bzvXVbrtv>~Exf`4`XNpB)ST#-D-y2aOPGTpbA(B)9*~gVqPW z3M*hPgsY3}4-XUpAKo&G{%VTv({vuY_$l+VWa#@q>MNtiwwk(%|GH zn=qNamcYH4%NUQm7J!Baf3nvgu6Y-w)u5IB7oOe!sb9hJVdpALtEn7whPu!BT5Inf z#+6nzF*yI$UHW1skwbhFs_YRhJy(;bO55f8-J!pb7a2))&(o;RhNDJCgVU;|4)tme31G!F3Lisal!) zOFk!}6~9`CIYf=B&K$T$MUAOpl91;dYvMy1uE4GD49ajYM*7p=$aO2)s%Leb^_I81f4q(nh6YV6x$!7{hxV(`+QIKjV6e@&_1Ag9((et5#qHRGEoM$ z$EbmG*ifWUG1>E@a+t4!;qZ$m&k|-@PFU;<>o7@LpNHHE&f;0s3oY9kpU0aRmD}@~-n`~oGr$aU* zdS<@L&X;?s=p92WVYPu!Y-3HcQI7%@j%%Yv(W=+-4Q!Hke;=Q2&%27+yfW5y_nj9z z_C10|!c#n{6XZ9qIY{fxe3OH#53gIg2p)SZ?)rJ@Ruy<8`#DV>fdWh@bf0Ha+0Cot zn?Duiyr^_KKb$kITeFDV))I+5yroZK(->cnplXv9K*0{g=~>|#C|g)+iLjC5jZ+6M zJ6-)cIAQ5tCl1X(ZtlMy9%9R*%TuMumh&?0=`N&}7FFbB7tsrD@XFwT(F!51|>=-S~8r6Y;HF@rd$>MDl##t zC*9Z&nfXpr4P0%wlu>U|Yhh#^>>Tl#c;DFGkf*dPj>H(-T=Bx-kX=mw7sDf`vd8H- zMiIuLhMIR#A;~x1q%s6Bzp2HhI4=q^jM(TWy+MoHfDWOvA4~nd4+^R?^_Y_jv^`G_ zw|Zlh|JGUKlQ9QzyHajZud4&om)cx~{frVun318zgL@ILJMI^k4;nfK#{O#F>Xna2 z)xkFhYprU*w%R6=zn5t$m{$;xc<$Ibv__Sz>y+&z-{FsWb>w=T?*gV3ans5anZ1V& zlskwWi&isy^`ZK4Qt{~to^;K-riuRP^+@Fb(4ci`Os#{!%;jHv6sz{)G@B_$RX3~Y zPnv?dAF-9ndtUlvU{bF%kztWpdr|5WP;o=p;2(Mns2_7=wn|ZCzUE3X~?+Rg_sTcSoOvv*w*fYA49$|BrqwVW?6U6BB;eGU5mHG^Q=22-HPn#o3wg#PI z6^_0=FeSF(=J4asoku7R>I>rHixH)j*~|SKc8>Yi9-0M&4(Qd*D{Ub^F?;Oy5SNBV zxB8{8j1m{D^9>jCnwFB$XbVhQ-XAFi|47+iHuxo!(X*Gcf{DISVR_Dny#7Vt%ABdy z<~5x&l1necdZTKt!KC9TJmt1eX1O1*MbjOqU31uvVAdLH;Cyw8jLM{=OmlO}%Mv5E zOOZ-5Loh)9qWS%17_fmAbcq$m!Qqo2JFK%!*six zw(KWUPkuz3D-@Z?x5IB5{NT)F6O99g8(CYx(#(O>6U>wNl|#!`?0MY`+jUII;0X@# zLbemPLaY7d$m+!U;JYL5XJGd$N6NxJ)t1!gh%4%Oilx85^qVbVEma69u!83)OZB%3 zDk_HeJS~r=4EFROy3Y7i3RB0y>uyOT=du4jT3M*rF{?r9Xpv)Eo7EyG&kgO_oIg=j zla%Wcg+a(ktz0=Wdz9P})F1(e7?PI*3Yjx$>u+WHGN$hSiBi=KTClYHhtm8%8_6S7 zH(*LlYv{ThQUU&;zv}&faIj0q=6TDO(YNEXRwonqe~W(fOT)hEB=Gr%IXrU8Ds-4# zwYYjZv+Oy4)WMynwIzHBs0r8Ddp;`u`gbYU2E&4{UJPLXQ#t;6iHifstCI$_0vQiY zHR9o)hpx<68Xq)dJ}uTO;~8R`tVtOvEDST@b&UcD+|`S+I&3NJ^(HN;0!(fywy_d=LF+0pkptSoYig+6 z#>nqcdXRCcEXBUB?XI8aQN^3Ws{V8r0yG57TSUeNcw8wr=6n>^Ur`&9Dr>N#w}`7! z-o1|jL^YinpwL1ssa%Bd(B)wni5o@%(l?{8PIf!oc5HZf1L=B&b*)e6$zYvsrnR#- z&w@r!s<;1RS(#}g?wlC`VYq1d%HNI4V!k)1Fh`*$uns`I4~GKCqz8MLu}Ry8MduyY zoh+@ku=kN_I`w`_e&9HZvp>HsaD8#^EMTf3G;64R9;CCAfAH-pRYj;&7NJrmMP@9!|$u=YLdL|YW|g44r* zc+YRuKy+!ZX#Hf_&rBt|2+vmIhK(x){pbE3BmFni#PmDBLYUzN2HZ?Yb8MGU6 zLuv9&bana)>mM@Ji)al!0bg%n%GQ?(h6~E<*UwuQH-5G51i@CVpgiEq>wxPs@{%)B zn=G>sUzt$f8y)n8(OC(SRThrDa5{a`?>bzSD7+k0Cr`wjoL0nTQX@O>EOyN7ILdvuR4nw`}wz{1=jr#Uwc}wri;)`tPJlArBzVLh)pD z<8~-t0y3C4%qzoo6_(52|FUN4MtCRv{j@HVhno3BW;}QGLN!UQ1tUy19up(sTkxEC zc-X@jP*t(N;q+CtX#%T@fVK$_<1VuaUz7p-Z@pkUB1XV@%yU+{uA-O1WfTGK$`XJ# zbM8mh3miJA;jAX*;x@h)x^NEumWL+cEAbmQP|h|-d!CX;Yb9d^I0$A0Bv?dVOd+TJ@r$hY{1%-B#}+`D-1Xr3 z!Ltv_jZ_p7IHEZbzNG9{tcY5o;o#*eH?F5di(9OKxv~4>Mei48+8}NjMzA<83n`8q zPc4D9q9zX7MYyTf#1NziHL*?AS$jyAee&*@$h+DeEPI_o&P7W@0%j5iI4rXd5omBq zKmKmebO%v0ddhWQIa*GJa;|n7dtV(hGz4US+t+};&8m{I&3}ueDh4KxvEgZn<|xqY zYn4eg8A|HLOtd~x8NZVBfSxAI{b5xtW&p{O_kye5Yt<=QtDj#IxP?VHV^4&H!<=pCn<23>t>sFZ*>UoBke+Niwai~JeD zJf_XLa{vf?qGC~G#dUp?O^hFiLrX|?>&FQFiMQ6=i8&SPW&?nC@S^99q28b;ECG6F z1HcY(XMknNS!a~9Hg-6Jizeau@0J-|(28z<5dmJ`uw^*cn3yebkvamdrvck+)@1)$ zh`sLad(Hc9R3d<;zH%OSnR%d}2p@TbIy-U{%Q64Q`Hpw$kO+4NgJ>J9L2)_r-PPCl z+Kp?S-XbH^#Vz#8O2Iv06XTic`9GFFd87iAG7_KAcr$)cID@`;ifK!)DR_E!fdo>V zKIII2C;Gl%3dxI)MM`&xc2`UrG&f=A9(~V{%CLyQNv)7~d$W3GF?VuN_(e+Z4;E3z9fi%ZjK{ z1fK}2HJ!L8<%w+`X6z9!}=^0BytpiB>#=3N(F zFRn}IgK&(Z=!GwN;Q{;mxG+>XsDm>E3tD2tqh4BD^NhUbexhYeG}b$jfHSfHXbHEh z4`oS_wUw&f>A^2qsLssO+Cc=?{8d5se4B>n{Sr|sXq4`>|H+(lR;=+L&V*FNZ(+iy+ zobMS0U}QrVyh-TnIsdEszPz~JirwKlLotmXp7#oGEvt26!obqVVI<^t0~@k0 zl`sDGpzD5Ws76*GEDxvr!{c^cSf58_k88xYWv6Mk&n#G)33C`)&KU@Kz0H9HY?3MQ zKWC=l=?2zS;v>ZP*GAuaBM0?G30#+@wkq8J43JGW1ps+QH&~oxTR<~c4XV?fljFg6 zWZFUh&PzJypu2MJ8 zjAEVKC`LkH)Zi-tn<@Wl=(j76?3a(2gaB{(_U0<>3LH5^bl4QiggbPAkMXHc4ii^` zj9hLtJ~g<|D-`>}Ev8&=_HoYik0n2CDCHv~l758t78}qYy9!pS8F(XE9BJ)S0G9A_ zyd>b{7_h&n)ynMtPkP z8Pb$WdH@L!%xKQ={++?Or@{@L;~c0}OcBqFkU8 z(rpc#V?e528)@t_SOi|NBP2AH%qt)>Wl;5H(Z6(4_SeT`qdeG2J=5YZUwwsX_mPA6 z^L488cy=ZZRB9jU46qO6!1OhC@DJL1hTQ$|SlT11W}=(Lq&7CRD7aJ0hCENHV?>vO z&QKF63Dp3F5CIliw~TuH+A1r;NhWg?Ez{I&uyTLm@>9@U7l5Cz1Ogq>CKv4?;&BXd zHkKyO?AExSnh&R$4z=g`=Dv0Xg2@ZCD>h>N89PnE2Nhe;s8T2xSW`JD7-}3i_r%Po z*@VYTQTR1)CYwldz_oBG#mOYl4=lGka~dt z3U;BJlLLr>UsY8so>h()*g5LkkIbkC?>#OxZrMl0T9#iHa4DQP-^8+aAs6-2`wW&MA}jhLcoNQa}f`)Hfoo8UT79 zR`|Ee=&8Dpr}YFxPnPIc=tafy$Lu7Hji#1nCDU$Azy+;SCymU8*`!?mb9Ai6U{LK)Qfg%|iX80-+ z7j*Q$)UD5DvX7Nv+35bmZdD*NSdG zok!P)7fV({g9IHm+%k}3R;X6Y1a4k7hESZ3neYIeUfnt#iP37zc)`=12HpXk%#Pam z7?0zU;vmHn9X7~ws3}hhFcJ_@H?Y^W&!KB#qhaGF`Vu}L(HerjRuXx}VcKr64v+9 z=jL)KauU!LX;C_l_D85^qnZqv5(w>JN+tuQx2OO8h>I0FQyK!IK|b+} z!_F1UX_0kvFc)(c!d>S>I}eaI`$QoQO%rnb$3odR&pr!z@#6a*|AbE(r0BuwuTIxu zgZ%V$X-f2mjO82T-KdLI8XJgTX zP84i=GN5IXyxoXBw*eIDC{w)}Qb$lnaNd%V$gWH>xl0FnmgBAbMl%lTPZ zMwCM(5T+i4&hk_5sy^9jV-gS8NHFay5}^25F`yIsgm521Jx8%32Wl+PSti6}&sGJ; zgU`RaC?>K}Nhb{GeT~?!>Dwd|?-j(WIV|;>G1`9{tSZ&Y0MU$$KfTs%*6{ULF8iXV zS|@6W_5n8{ZKhLLBg?pve#{;eNC`S=HdpwO3^fech=EG$`nV)9QYaTn;7wb#f6QhK zl*z$#9-7GjmJoNrx~eR6KgVn!n3Wq6ZveLY5SN1EU$?J|>PHI@(F?0Wj2l?_ znZR^VI}V`cE66~?AYG28u&x1X!358;*T>vVY^{t-J3KsOUW8f0FMfL5p%pcBapxw> zBqIs+2E;c`%_E{4v6C;Bx=ncLlBKC;@sCTOqEn_rG9yp2t{yzRDa>xizWcsYc@cZ6 z4j5@Yeu0s@RR~t4irEe}@KH~D*#F)uxYeyWkkfis?st)3F>Yx(@Ijg~Nd@5JDQ7og8_>9)StlRo*--EH?rpdUoY18)`sQV{LZ6? z$7+xn!h`JXmb;=hXp!w?7R&2(H(;+1ODSfRj9*IwRjjkJKRAIv>KoRPNE2poS2qSjb->AN@>BeZgdzG6fTe5zOeuN&YQP^|NhJPf2dST zqCTCMcn@)z>Tz~DZp>B4Gi%C%pMko|!hEmfwMR3y>YsmHu38~)EHr)dV*9Jm$9&-$ zJDEXxTN9W;+)-vD1sFDi1h_IKkv)PRODf8%Xxi;D82RuHNmicEi{>Lh!&RPI@KC`e z3$4URLmsDdGrsNVlE&JM^WXu*z0oL~x_%_yuxPi2D*`9``|JR|VUntMYNCXAUVf&D?()m)YA98DOxc-aRT`Ke=;0)saM#ejoiIOl%j|`4-!cdVE8QuF0 z;YP8_$^d5xKUe^j!hG zqmf!QAyhPT2S~gW)46k;(-u1q%>wSMxV%1%o!OUn?EB*>^XZJ;2EDVW?UY!XGnqAD z1W@3*XTiH)`AAiNe$=9I=8v7W^IqXWAD6MhOp(Y7N<{bwc6_Z@!8jQ?B=80m1=WRj)pu!7~esDMg2_z_m7JW`H|TX z=I)jK`o^uJZ7>B*d8W(^kWKm*3qXd+1#UC>Rxy&k*}tB2i<_NJ5~*Vcep=w)Dw4SdeIK# z!3X$Po31(k;Zy?79)#Mlu4eO+r(P5Aae-HA*-eM^9jOsIQ2mk z!iam<g_PT>R4`9-<#1mpm@q+dlWKjQ8MN97@(VZzsG z#DP&P%Z?oNDrPgAgr0{sEm18=E?Wpo;jCO|kKFZh)^}?>652sM;rG{mrdT}VgZ22~ zRp6L(i0eu@_QVq;z+9H&g7aUFyvGN5#_g;{-L6e?n*8)uu`8lyQsMhX|EWLjkNj|q z8mud3Vyr#2R6mR}$F)$59-o9=8vxyWw@VFlv9$#|MvV9J5jgis-qHB_EoAOsQw9CsU+dW0^ z<;CBep~QqAwD~NuAk7fICDrlF(`cI7bjI;CX6q;t;YO=<2GB~pX8bNsIk3xmRs_Mu z=gs0w>Q5AB*7za@Q@bKq5H2(aIO{zU8n9&mm4VuCkEKyzxo|s^-`m@D+V5QUIlvUP ziQk?2eT$U|_xWPVYbv;^At6j5Milr;M>^szHpSS#6XDm~z`&_ovOCmDyXw|N3 zA$`x>IK+f)D_ZgM@7_Z@Vr9sC*!URp^pT%*CvrjEDCjKsGW>=13Ew+hOOgFMV?C^W z;{pxl{&KZl7WOQg%1cm^naPyT9HZp^JE2%} zjnBcH|CWiAT7KVI{Cq?9FDCFBaRG`5)Rcm;f)OA^eFFC$YVoFiyjSpwqZLvc`{+Gw zIcDUmlm*WaayqpVx3Nn!nHXvVaRPPdM}$)$9B1qUCkzpz@05KkdX=zJf{86w+(}K; z4m$ON^D9yVA(hw$Dgtfb$zGSMM*wF@rdnjJ%d<9Dy=0GT`8&6P(vbYEVu8^&g=QH+ zh44X0_t&>Sq21>2A+ze_WaiJs4m$#5)4Dyy$G^!!KxS4rL=m4#QFTkybEsqvBZY?O z#~o&r23#IS!~Q1-1gWf-5$+%M1q7boI2UxUq)+lcctAwY3l~n zRhvzGWuk|S1yGSo^a_$m>!0`|c$?t2IL3|n!?9I#`*zSMp1%Q5yAoW6@eU%AL$Yry z-Z*qezm&fC?Jt&BB-Cj-goo}V;yz8!WTXP)3ERP-<3L6wO^P{nC{MzM)E$djE$Z>e z?()rsj^8>xb+`7sUVl@>l#1Gs09Oe%iJx#*6Gk!iH9i=^$2^Wu32ug*Y!HUB=k70; zq3>x7lRD#ByFQxQ-Ym@d^?_V{z~d?%C#uahXW0xriZEx?LSD;A5i38vK^SIVPk8!; zi4EQKUh9A2ooKBUzhet&pm)G-I#8|Hv)wvX}>SeyXzGS7r`E zy@ucD%cov^-2ka>AXSE6H|uU7(I%c6yHnaEM5I659-piF<5|MhPRhzW{~2GL>enEF zFs820W2YR5S)q_XzP1kot4QHNSH4%R-Y%_@>oz7iZ?FKQyzoc<=WW-lMt1#GsTW z^RTH-yuFv`R0O_unoz|QJcb^|Qy8Xf+7)XS02>?S-o>Rh8b zHT?RkUyAIXxivtjHp?-D+#%0ZE1r^ zX!Fb)&QG@e1elOnl*;vI8&iv=DOjIl9JNI!*@{q2YRD7R-8qwu^|PU5$s^AT*J}dX z^CZ5kJH{V5dV9W<@UDgGURmx1qVr770%gm@So7hnTf4fxM23O@qB#Eaz|$jT-f@j| zN0~RspR4D>Y&1qEj!baNi*Bt4K2Sfv^q|<30X)tEfAQW9|19*Fb#qu5QNOQL#2fLG zb8+)#54J2fh!gm{8!c`(u9QqT7sEQvSWUh%$Bkf3p(!b6sn#?tIvcfR9v^_JFmJCX zNYCh-r<(oN(s_>Zf@RyR?p`QUtDHw&tk&(iV$j&hRt4w-*c#5#J%=EUFM;%2#a|On z8Xdt4BuX+-+n!<_G%P26eEL%2^6eMJTRpzht{pn7s1hhpagpria81dYb0!_zl~m~t z5J#G?B(dFDy^v#|;)U4GnUi?UGaQ)86!Y%}N=J6Ho8->IODQd-jFNp0xjU)4!}Jdc zFKc{byR{yt^c!aRUuA#pS@rn9n-@2;zR%VOTqG9Q5D?-+Oc25&*pxKZ3OhcfpYhZQ z^(@6n&c4(!Ync#rqP$L22KrH}yS82y6}0VuzDC%1}E-ww?;J}3Cm0C#!^gP#{mU4Fm>TD;RT4Qhxtq}1lT z8C{wz9$LGTRn5X1d1W9o#(tYPo(-$NXI^&75nT@kGaDO@QoTr1type^kQ+vr^OnCZ z&&>K%nPP8=m!ryc$2m>6QLN;UJz>cKhVb}hta4?hz+??dac1N&xtTZ!$pps&Z)rbh zR^Qwxl-VfjG;p4|wdneaottYpxkD&*E2l@k(9?t}Kr=^9pI^1T#>gypp!$#+mJGIn z1FjoMw9V8M!|x0QR4KaE_Wp?v7p*kb2z`wn;1Hv{p>q9%UqWaMAviLnf?MrDrP?Ki zUtOy`&nz6w)Pnc_%o9-)+muK~*nZD;D88g2+if0tMDh=YE`Sm#Xm=RLn4HGEMpl>N#j)^+k;4*8Yid3x4~6ZWH;2MDm}3-(6ei zWb8|$)%Q3)o2SiMnSjWkEsw{@FMkL}u$=4GZi(JGy6oKn7-F@D3Ll|%}W(%y7 zBTgAn=_U@uu1o$?8*dF7o|Z~(mRzX5$+p;~JZu9TdfEsxV89cWOLb`1_)trP1yhP` zURw#5nfd;VGoW{zQ^C)^0pJtPzHm2aMxG*-FGYX3puW6sru9QyvC>d)(|M(b{k{GjV;c*Y`Ewl-^Q}+vSOgeIs{2iM)+1 z&J4@;_pr{MOU!Vj0>f=tK+{(T$WdzEC1Jej`IV)GiV4##!{%P#^7)fhO{jb?)E9UZmsRt;ftJ%;-x z%>AkSU`UA;bq&mjt;5G_pKwmQyYgoWB(@qaa*M^s!vqat zq2)KDN>6%y(o1;^4nM*}H4$l}-8J5{J9KZ(mCV!6Z4*et2Oo3T%l_$p@uNDX>jg@$ z@A3S;fGbamlD!xRK4wl@gKmUMRPS;d7+jN}g}b*qua=CxP5|*Fv?PQNsrLZ%FUq!- z%+Xr018{llc1^3|U-r5?TR?X(t2Nl{x1N+6SUalE4Z|0b@o&@WS^Kq|DS>KK(0n0K z%bfSYF}R&08R%y!*izM&+IJdGrl3M%hw}1YEWMVD+QXD>dJp73;1a9Pdz>f#g@B?8 zU=0-7*gn?jD0Q5SQ$3bSvv4p&v!huDUYBOtx7DA zZWVXETTw|j=vHXccQ+zJPEnz46q!sa#-MEU4el}Qk|6-XG&~h#X^SDGw&W_E(z=3> z%R<@RGtDUB{SxLN|E1eXCh`7B;k?{LqaoKfLWb34pRIXKt~YiHiiyZqKId=Oe8480 zMwg=65T=~-Ae?YrgP}_emQMyJn`e1qU(yK8mpWbNMt9)4%~4Ji!ADjy(GyNS$1{%3 zLayO^Xekdjn_V_5xsPZug-H9Or< zfG+&Sl21FHWKqj(cv$GjihA-}3Bonr5D&OiPdzG)2?|=`PLMoI58^>*!&w^-!BJAd zWf;y?iuWTda!|-1`ov*-UfJ&xBeN0dYZ}%o@st}+R|h*5mCK5yZw>5C+KIVp7eAE> zVxFdhNbfx#P|cdGRKCPFhPD-^9us{qqq})uXYa>ZoG}R>yytQr!r`Rxsyrp;jJW%i%2G5>)!thLEO<CIzOpg4lf{Y_}gqUT_On&HjNIc=zV1m~K>ZS$4NUDi?yw z?s~CdUV0MecRlwfW7rFI(xUyL-iBYEpET>jWWpzHyV9;by2pS51+$uwi`N|f^JMII zd;j^T6{lOzogL>i>Bl-a@0`)SpXa!Eqa3i0cDEh(n7KA&D$f{lKj!Xo2(xH&nzFW@ zyct(feEnRzN}6b(xrpD{*v{hydj%@Ow~Vc%A4gLjacMQ(j2gIqQ*QX9<-%w6dB@BL zD=lY$3*Qs<6FPQos`blFf3^7|=8v9T5oQt24eET}{M)@BoLz~WlVS6?fNfX0 zdI7R$GANTg-27%~bZ?4(=pI&nK>{}wtGHP7hvM4UuTbCclMw*1$MYhNQjPQ4$a<@C zbnE%#`!+DkPjBFJDRV~_U7@i!0lOhLP56(mzN0xgKhGV1aD!z<`ULP$8~8_HX~X;4 zBKZC>TRBA;c>}z71H=|cw<}Xz3DcHFIlfwio z^-6Y&oCy66Rp=)iO0W!G81)c>o?rE}pPjhL)xxeWYq_;?MsJOFo-+u^5^q~UuHO#a zTOy0QwR6y{Zo7WX*;G+IGsDTdq&cA=L)953+Q*-u{6#!$ApR{OzW7JF zMM*n4BjWb@(S9zZ<@2hYvA(HQtWfdIQyv*kmIo?h@fB~UpIV*&Z7BYFo69wm{Y>tm zg??xq=Nv{*Tpr%ha)_*nE2xpcmVI8(^EK`&mEDe{_fWi zyY2PIgK(qf!L=4>jDCr)skcp{WA8k3(hjwLQz)0)E$-!m%zi^w0q}m84INAp-l|EF ztRpQYgE0c#vxZI=p0ciqU#*2iu)JOe3;$N$FBhaF!g9g{Mwh0a-Y)rL)^Q+i+(;NJ zzBs!7eN*{I*S;B}zmqQkL zcq=@7jOC(8zqny4yA3o}VW1s#iZoBwr1({kobmO5tf_0-yc&~l+Ka5b`S_4Srli**GK|ug=(XO5H+>lpDT{2|DYm9QSJO zITFB4KSi-AAed8=3rthmyX?#l^4?fyu1msdeH^3OpFG`*77UPCu~6b1zD9F%=K-oR zzZAo;h$qmGfP<&Ox;|M3@uQx;r`{&O+ys7NNGeU_w*CwOGih`KQ%8_p*YX#Aug*i5 zd;)!MH7s>$W-lMMXSV17`Thr;K3ul2=Y^s=%$#>-%H-u6l_b|@BNDJuh%_Lq#s*^e z*9z~BG+xy4pRxZeylm(fGQ0or)gN>sID*!|h2ZUgF)-d@_HNt!8J{X&)-{bBRQvwm z>d01r+?pf{-{NxSj`*Xlk*Bn6*i$M{0eXi6ge5LL8B(>QtT%L#IX*|*QQNvUf;eP1 zgDlyT9I#2qyi>FCqwIPV^uxz@lv4xtz`>^1haa$@zCZX#=+EOjOf38c%VS#i&F#ri z?hCr3_xojmru8QMiLquX@UtBrAQlN~zIW9QkIgg?+NZz>0zpU)z=D`je;u4CAr|rov+VwM`C13k;e1YfXsa$c21C*OcQqysAvF^ zF|P87shHbmJ+InN>$o?a^yN{|@-8XVcJD3ZM=D_|=DU1jF{eKLS|y+(vpNqo^vtFL zzc;1zo3a&0bZOFE?L9Yht#yCLaV`;9;S3+y^xCZQHk1!62@E-KcWZ{IV@;^PHU6L* z;NR~uMBKG|*;CqYN{pj^+|kqSF0^gMPUt8)dq2^o{%R`evf1|CRuc2C69AoSO9{(2 zj}RxH3yE1G@$Z;ta(}xR)V1V1c!1977a*$~05GB=;9c6cPS?w+t3B1f)vG7_tkY{m zrACupRu}NYct-%uhg8u9RQB45gHq@pw$6@_|nj&w)+;{-gqsD2v#|Uv;~G$(TwOL3LE`;zCPwKckyL?r_A$#kU;TK9;9XG z)aJ~ge5F{HKbuFr2}a8hDlJ;Ej*hq&=qz8!B4**BD5ybN1MVEkf3c$0p7~DM&tltqyhV0F(i$~_nTRxBK7n!&ITDr=4}joyfM<|RdhWX*hxVO;|j&{&aq;V=6A zPn8+iPLJ-oWGqZKd`P@ZktVru!qMzD(%ZE)5PZo|GYdufjdCB>o}W_*894T;A}M@m z3>hjX+gfTV6(lBzN5{g2KXkqev1=1mfy9;DJaGKXCX#+omeLs7*E72vHk6RCe9hqh zMNgKQql}_T3dcn_1_DJk33lsO)tRWxw(wq?!Y53@UQ7mF95drU$K?d=RI|=}>@nNI zlAGB-ykG*~7hTx=QRks|iXxbtSQxp_=RD()iJ|zEfTHGESl9vo4<0Qy^J<`y6#o@& zm)D~O;s^n^IdN2FcDHG%xRJq^KL{Jra>-^%zyAPz^ z4r?Lz@^ft3#+@&c%ez_jRzX|01(dKKs^cLt z;?5F!Vw7iQE4x&ub@kN1A<@m7UT>0G8UT&t4gt4o6>fIpgxTg#IcwN?^$Kn9kNdf; zzNy{IGrmIXUOoa;Yng3Dt<1xi8px#dPzlCm{&{A9gCJb4;0@<=sf6#w)qz!08tdT` zo%!nXGyX|ZT4JwXE|Oor1iGjZm(jq4`I$_cz#=HQ4E|N)w^=TkQlq}=yOC3y{hd5b zW8=P%O1!~p?~&D^<#&R*lNQvyhHArPBt%_(A9+6cr%&1C7yjS-5UI2&tq3Z5^N_6E z_xa~Y{}dz5rtD^Og zu>1H2UwtLqu52T(#L$qF>yBAZmr5rh4atrwo5vfAg0N$S#dn;svh&TK`H z?>)fGl@!*?YOBb!@X)&F`0)Z1RZL=|8$Y_lUF>u@{vhc%dNV65FK^GzbfxQsXx}Pg zU&`g)mgB5|G$!}UXI{|r3&sBw2cxTz51@=19jOU9RS_&M7 zIxNcgi_|zFfqhm_IWo+5(#>K#aED8Lq_WtZ-}_>n{gcot=V+Rb=q(a zq-Z>5NPS>cz^*>(&ZtcDw`%^NZ<@RBZryl-o;9Bkl)YSgxM35xGc_f$DYxH1ykU^r zdS3j#!(83tu%}O+J|CIT++&QBtj*P`91%fgUPty&eKyFd77qzW(z^g4Tb+$?+oy zV8RKEbv9@5bC8p!Fn_(55oL)JQhClwiSh3zCAZf)kWL1nmaCfu1ck2fxH4bW4F2{@ zxC0Z={h))gEY(!h&5Ea0q`Ql3iUJ;C;$(1cpbm_$!(UE+yetfGQ>h{wT{7%%o9e&F zZy0lS%vON3bdS{>A&g_RQ8Q3fIW}s0{>yWl%AGQXmSGmu8L>BZyH0+^`5N6>a7Xeu zG&DncsLV&e^E)TA$oMPDZ9Jm1IK=4gaKLojyV`u76Rs_iwS5r^2DX>KOdsQQwW&E(jkav1!F;5PrHCC`+9Nz4KCtu;^AM#$p0UH??2;l|Lx%uAx$mA#l9B`&x@)!*r0*MX65hm z0Gk|446xAS_gH>?*`o|1iV6F*9azQn^sF;D6&R3Ot)Bj`>!E+OGWx&qJ(kFe?*D-v z@ShGv3b29kYGS+Hlgz3L7N3w$O*W8GbxIEHKe`$_%KrP=A#%Qtfl8OkkKGcnji_(p(imyG5r{l(P$7ZA|{eDc31wV)t&DH@*VLM z9og=^u+`?NBmR$P0JLi~y&AO!@m;xc{#$q3O{cpm8qt;Tx*b}gD8m6*0=)1UQ$Em* zP6UZo{y~=jVxh=@;{%G5`KQK~rWy@x%Dg}3p6l8!)0dPUe!H)>4$Os3Fq8U=$d+0E zj%Fa5hk_I5a6cSN85nAYzE&N>3fHZsRM+VLCO8s$fx0 z5&m(ELV?Q#I*}(R;-n^-B%RN+$t!TzZqWS)P$ZK%6@S9)0I1!3W(JQHvJquDmON>JK$E- zFPMk3_6uHME{Y&NNE^jJAL2JRUp{Yl8X!IW z6B7@i^`a_)ZM%xpguoqMJKLMV>g6AAekw}t@OpNWdpdpM%L^nci|2Ybl59d71>gl( z5B#(tz9uTGEe8@gY#G9xrmt--<sa?Wis3}GSTM`#$RbLTwQbr3dIA{b`bs+bg~|jLZcsC`5OBE+n_?AZm>yy z@NU_%weiEp^u8=B#<%F5JrfRe-%q{?@(D+!W2)TR0QDrupn7Z*E(necWFlz9sebsD zw<59I)qhXPp-X1q34td%Xx7HC&&W2_24{an_@Zw{+0xNeZS36}MZ!#?_++YQ9}xm%1Wey~>1#z6a~833 zj)phMmLb+GCVhoSBLS!IEshWPh0iyn@%dr+5*#~CJk zmUe|5t2#dA_wrNq?Mn;;0nqm2tca=6+ysSxk~_ zY=Wn-5gNL#qc(fGAY^?$uFV0@Oymh2Hm^KhlNy>Wt!f#V!@2=;Sk#?A=#-)4_+zm( zgRt1Yv#`1+zFcLc%$T@1g1}*J?aSQj`^smKZ%f;E))84VD^gQ6ie^(nsTU6TZALkJOsqP zkgR!jjx##0ZTCJG)oUN6D+rampB=b9sP-9ttuWby;c|hB0vB1j26lXxJ|RW+xm>%4 z97@1~llL)@aO|l3Kd(V`+`7TMYFw-vYXwsiQbT90tTHB28;x5)(SCQ~e)X65=f=(< zr=$}*sM_*agT(f(hRol=6h&CRz$Uj_-Q1IVA4!Db8^EsfQ}S(uV`6(f-$#Re)(e_{S>gSEp1pAWN2Kw; zmFnm-q@D9WotU#XZz%+yINRkHimL@|g}A@#ReG{NW`D>lqYu0} zrQZZz(6Mf^ssul8;&gB$cTfReVdj5*Zt|D%n1AFt2p(Wf=CPOjd>fcG@UA$oLByBq zk^?`ijNd+-IAAmac#8d75vKTbBD{uFgzxTfQg0;CaoT0{fC9y$xOYaWfL1X4FA1A+oY*3AU)Wk0#R^UcNZ$N1*#bh(M4yg$*&<A~5<@Lxe#fths6AemFR@c080OO2 z(;c}o;HG3h#1Ks`w>8)f9iQ8W7hM=t#eF_WeRsw1rIwz6T`1i+5cV+dK^ z==f#&+R8Qg4~P6#J-#|)>7ab(z|~$~9K9fVbcPo^(2n~e+wwmp`$S|62!xQQ2$hck zdP$l@?a)@>?{g5vci}-zL~N6I)J`g#pIDq;o(CRU#^Y_aJSYQgiK9^Rv7eX z`V;?$?aMATC$m>FG8ZCPuu`OW@?!&nOczS1F*NY=I+C@KFSNvC$Rv)T*j4|`5#2rZ zTMp54o4x&v5yE(l7CZ2B1Sd(Q(@H=Y*r95>>$BU(?R8{fB(DE-`XjtQP{Bbh%l{C} zg6%^YQnP=T_ez6SXbQ9phH+urSJjsX`0#_HwCxT6DCAB#pjP^r4|Ku|(+pl_nO2Jg zcK0QX=TRg{irxej!*Pmf2`PWPEk`5P{M(G+$x%}IQ1P0Yb(G)6u;8Z?V1 zX@*UyEzQ2M-P3T3L<~Y1#7W|~2o;lIiV;_ms`tY-IkK+P@SL%{0{?aWO9s86xk?(R zk#W|M))v9mm#FS|6y=O!OAd6?22;`Bgk?)a^Q~1|tW{fIK5~X+UKCC88z6V42i#Bo zac28ICpJB`=ab*2V|{v>r#K`3yx&ajj0;~8^RM}@ec!97XatY(!@Zi2n0}qG(Buj* zUSt)I-qQM$an}a+D1xIR^EJ~2yRzjSsBhxHCn=om%^6-u!qlE7a$1o(KYE(ni!) z5N;$c8ms0aB+*VTBoS-0xr5u`UNbaGk?U}`VqtfKoe)2|$s9A)&743)CL^o+vRaVQ z2*C9(1p(T4ywQBQ-t?@FUh|!%l!c;)NtW4=`wf0JFL%dhM3}Sxplk0@oo5x+#w24- zQS9+MMoqP*4~m?oKU9}D=CMbcd`l& zB0ySrjgNgkHVIvPEM1eY5-*-{uUZuH`a{#2te>cVhB|NT|1xoeyxZQ@-z0%zTr~>Ml%d7fRyM z-2YHkZ{1yBD!_O3nhiZ1!(hP#wd$u5jitiZvqVCRBK__yMqLHjo#YzJjFd}^WB2F#`d$MbdExDNM(6nM=aUT%SJO%qC5n4~6iLeO z^F92_4Vr(XF?t511qFGEm4aYgim@ah7dz1p>w5mNi?WwfyN$GXyeU9*k#6AJ`oKzt@SwvLrWmsvI9%LKEuWrx1}9@ncd zlnI@weXsol&-!pcz97?`#rr?zuWOCn(7S}M>O#xJz8&*g`XxaoCO#3Yg_eZZr2dH1 zk|n{271Uz2`KbDV=w>ds#Lxo*q!TG->^!_F^ROC!y>8b3v1QhhgO~>Umh<3k<~+(d zY7tG71X&D9Bws;{&xs8KzV{*ZlVz2nkZZx=a%s6WtrD6KQ{Hj)jnq6r4LQ0}E1Sf~ zcW>+o^|QFLQ5S_WyVtH=I0`44Qa^wecUly=;84OVD<_eLaRtTuHVg|l%u9d1Nd9#F zLnhlB>#+-K60z3>Z62NWJN33eVy{DsDKCO4`}2CxSWT7;_q9vk)4n4o47F3S_5mm2 zAK*mk@73q`nvHIu735RSCkPH3rBV;>z9fx(KbKVWo%oiElY}LBf@6`46eK~o&EIx? zDl2L~w|6=6haf{WLFJ3-*Cju#K!E*n7grchQ%4K{o{|NN+E={Pkf&{r_KdvFUPp#} zFMFEE$4+-;=1G3#iLGPThW8r}oeQAT^VGbbez~C*Q2FsM)oqU>lHGfrFtGMrN_fg- zQ%+AmI(UL%aHgYT`un$zMcE(M7{a-&{!dNA{=Gf||0i<#zjYf0NNZZQAwu4_uD96M ze^)=$AvnDL6Q;16cR7H1gLDGM0A;Hz{(Z05)5&FImAtD71SO{tyFr?eW_dmC&-vH{ zkV5`lTkv200=hMoq@au;3bYB#?@|lxgd>P{{#QZIoVZ3+MP)jLtO{|-+GMD4Rb7H< zgYF7gkMBXV?)o+17}&vT7p4lj31V*d=4hnH&&h?yePVKC+nhdsy&&5OTO%%$63nm0 zn+UruUxbBLLADOxB8D)``!7 zM}@a!zkhxI`D8u%R7iWL9{u~A>D5jnIu0hJ!S zBGINg!%j&@T<7CiKQW`&VA`__Do7rk2I8fW?LerIXZ4UWHGghk0HIxU7MO>;*Ebkd zkbYDxs{#zrymJ+aQB($e15d$=?%W0tU%K7TvGMO;diwpxn(tF9;CBnA;ODFGIej2v z#umjtu6v%_@GP%G=p)6%_^fzRTuDmUj`MC>0`(q^;lJKAAH}E_=ywJt!hyXjH1irt z5Y9$0vVw9M5t!S8g)B4Q6B_*it!T#aQ$8=L$pA_Se4( z*;QBlKy(ycf?~qK05_?9VXW{&=c2G%bw%FJa|?%D^(VQofLg#2uSU~7^A zaV#_v#I7e!0(F&AQ{UP+*{e87K6D;z=o%u_rLJr)}<2y^@SH)Iwofq42nR&uX!?hh|6C%IK%49ABg`CvT^V(_{7AIH}KiF{_BGTzcOj>7b}U#(7Kh3;&85f+>OzA0enCc>3Ja zRWrlzAJ({8CIA` zvHhldVr5`^)ZXRK*crzXMWIC`3(r$|}G!$||Z zrc2Z`z;6;S|D2|Jg3OKM;`-ezJA~HJ#>ri%;?TGq|E{(sTfbY%N6GRjdbNGQslp%Y z8wm#Xt6HeCwr+S#l;IcE4?%9G0k3DLdxU&kyHCG6)b#l<$b_QsqC12zn*+ddNUW3K zSYW849tbfQcCM-1&GDsONWz>xTl<@>UWVPhUxyvw*!&S1t7Wk#s1lM)F~#S$Yb6?B z(NFUQ8wrN>gbVIVV^X&>t4n6{9zH}QpIcX!Z8M{a0M`rQ#5O-Mjx}osNxzU-q-C2* zAWcZXr3Y#$=P#aOtfXr&Y(q@Ncp>4r(u707D|gp4=~L_ND~yjO{Ini^aDk*kzb;{z z^iG9DE&8_Y#3SUZNx4`##jV6V6K^})^gFO?D-KdaqF*dusSk}r0%?U<_~O9Uz#?E{ zdVzFv(U;w`80!edpTZ3ZhH^sIxb41o-~INs=~= z2NDIUWWq3a_KB%CR*gSDPVR-ywnbBl`ZIpQoFztJ6N6& z4GUiu(kgBsP8?rKU9P=&j=Q|3wzg_2_*|wwXjaqw=a-hG!BdB5;K^vcQVEKkXRnes zT7YyYo*_ZI)zwq|rm}w(KEmW*=><>Sx4K7N6TQb#w*$Qd7omPeT%f1}*U>2?9aoxP z=U+^!4T)Jbt-&;Blzpn!NV}o)^M}3s*`NSs$tR+pjSJSe=#i~z6v;C9g$jbYHu@e4PNq~a@1r%+5+8#l=%yYwq{)dvSone1rZB54%NB22%*>a z8Mm1E{?k{X1bRDFQPRgtC!z5Vx}dnH?G$yw>Si=Srd^&OLwrx#!-eX}Y(&n?l;x>W zKL}aBhGa2*>0}e%%@S-^UadioKr2978jHyI`3mF~7ru>)cQzzu0~?c7#KlGWux;Ag zr)OMd@FAW5C~0kJ6`}G>B~wr}-Uv_wFbq=jymUmF#SX4BFoX;t=)?HKLC19! zQ(rd*l^)+p$;)&04`iOS44lL~T))QnpIt2eT?5P9g8?;SODC6TTUcR4of^*M!`tGN z)dLw$l=(jnm8(fB1n{Uk$&%`3GGJ4_Ig^b9J{F`R4*(^CwWdIkE%9jB!?ssX;No zxn(-!hTeI&3bP5vl|JtZ;aSLqgO zH!)tzcUp+ismZoH?=5{d+S|I5#tWcqMM;_B8c_$<_KCHR{-Co~`&AVEz-aRtd%MT_ z*#ue?H;>w>NZHRVboWnO1-(F3bO3iL2hd*lj1-}qz&6~Ax~5V-%6PM`5xZJggx(YuaZuOz%5b=l>=~Uv#yz`( z`?JUU>;aZoAyP@q#Vdy*^wd`5u*o3c`b63R-@ ztUDBM4w+IHMLIN$D(?3o_HI4fzPS{txBSL;xq<)OWreUq)iV+27ZhU=ywqsS!!1){ z0Y0y44*jPo_6q9!ul{#WqzG(z*Km{M}KwUPRS^g6Zhsj*F;747ZvhNoKxd z{$xnI1Il_F!4tAF-A)Ya->vBLg#|RiI5-F zo#G)xbVH*p@F>-hxIR%7nws%d{iTI)laW#}A{QTr$r{?;B1V@6E2HK*cK_tlr@J-A zv3J`<50GO$LsFg)WV(TOD7`&jgYW_4F@BhwXf+hi5*VS*G zI|cZ30Y$f(qeM?tpX`+J!_nmgaHaipO`inIYoB|I@_mewyVEzutch(@Orr+D9_vS~ zz>c?&?Q`YwV1hN6QJ;cWXT2eW=)E&LqFKSSk7N!CZM<{L_rA{Xvv6`DUk#doPk`^I zP6T5Mx8%rLH3_uKbDlNT^Hax3cIL@d`!DQlBrpLxYo~{u0p)MQ{7;I-1N$xwDG5`%`x)cVf7V-;+@p`3k>kq_aUh?mgPmor{4w$ zirryVJ6%-6mUVy@L)10j_705vbT5UOWjWMCf&1z@lYc|b0XcQ5VR1Ye35>d;03mKl zao{IXFD|p5ChQ$>GK=F=yHaewQUA{6C|Q-VvkTu|bUjObivS~Abr76DV1EPfXz8)% zX%$$sFbQl}KWc9qb+_*3PI8H>$Jiq53(hfiJ9-Mjw^D!DiB4=jPkn`Sg+?M6$I+K` zoCz6rQ+xM#l^Ptiex*)H@uoL~OVT%J$1%ToGsp}fTLI^cEpm6gAR z+4)Clw4^8W1@28;`8a(KiVgGWaLt`(-* z^QYH^Za@@15tXJ-dT%|GyP~}1-KpnegkM#So7jW!QB0^gdW@byMaVRJH?Q@@=>xk@s8cR$<$XnWn*T~=ojkZ!T ziJPZGUnU)2ifQ^(RX|a7PPOV7b@JU~m2)2WKm9NKhYN;oRU|1G3<*J6H!ejS9n`7N z)+bXpu7aXLTom3flxqab*cjCh=Vpvi?ynWBrsf~p%A^lTF#8KpL-1n&kdmPa|EaDB zt~R1`J{Z?z4@t5wD-PDFIqkXUb)vJ#R{hUuYQS>{(VRj381x2uHXwC!o!oAfe}yFP z{{<+qa-LTo+A+P)cbj-PWv5~KrW!v13XNZ#81H+@S5hv^AKOfO zZV6T=IE%Mw8!qQ4&F_FpUB5^l-4R(G1y!P2q0!A8_;dK}4E%-#J~(c_)*|G<#ecv;lVe)U1RjoAA?Yp*>Yz)M&8dDe%FKF}QD(g^2uuGrSI)6+!ie+Y- z;XWMAboq$(9(CP?P_PV|+`$=U;CG3{^<#f}hc8_wNojR`5kOAF5%qRjWAdF>^cD82 zg6NmsF6rpI*`T4Bi(UJEB~1@jTvGx3Ui;lSL1=(-nN_aa zMhI}AxWu)ayn>kEnOne7yof>YX$p*Rw`-5Y+@{CtEun2g8+?#)kh>B1l1)V2Lgte7 z@=?4{ESyt)F*=gw8;hVoxU;9j_ z+0lT58U|d^Fx7~7}FTllSipKA>gZb1@ zTs9%?=2_2?4D2?u zEA_F|q%Cx@pR33IM0h@04$;-NE)DS|o+9;>k%HTEXz%s#mt4{rgT-qTE-@`wd8tt^J2;93^Ia}wSTGaPI3x7ae>d(~L2fZcx`Rn^g zy#Q*-iYan(yxV7$jhf$rDo)taW0Xa=4lqUo-H3Pt6fJ>o8GYDI<2$NYhf?CRsBmPO zu2aGRSLWY@*Ahh@?e2F@jn4k3QkYBO^QS#B9(q&KDA^^5ssQcz$r*4r!%+UdV2CJ_PLa z?Q7gXpl!(8|n#!ka3@)@QLPl{`e=wJ%u5Q<_(SE zfivFT8IKGzsHgdbQ@^4IAv#My8wc`qo^MO%$%5ik1<`HzLlY@#VdEw2vz^`NJvCAF zTS4E!%kR;B!ki6KQho)3^Z45XtZ;k6b|M}iE^#%o6~T^cVsx%~m(F=q7dIR0RHite z$&U@&?4$DuX&@$0>+~*6gIM64B#z((Sn*QGyd%MK^m4b`#J8(?_GKe`d#NwRJ|N3y z=UXuo1vqFMhT&*VffTivtW5N_+OOGBlebz|j&d!qLn#kPb-pE@cG2I?&SA@>BD^DgrodUmP-e0S{_RorKX&?+7{?5Y6@N#=PEF4+A{PR5eUC>rqsZQ|)4Gw_Y*X z1kshRH4Zcj(RA)}bj{}aI8+<+pTvV&=M?Vna85DoowHtIk0NiLz2f-$U9EInT8hsq zF`ilrkcYIZNp67oT~Iv-Ea6oJTtp4z6w-QefjNC1U9Ymq%H`XwZ%yG zB?({yQLVxQk#_lY1g>`O?vJgdIz{}kx|Qb)_(s#q+iS0C$Z8BE&r6$dDN_@`t^)}* zVsg|Xga~4A%CfU`Jaubpq2ZT=5r3BQd_?0}$$K$sZXYwBgr*s;vB03K*RVMT+r_x0qhQ|N{Zs(%xPfY^4EbUY2$e^l1J z`rI27k3N^Qouu%@uGJAW3fIA4Wq}sOch)81@u=U`Enx=uBWv^2Pt9)%hrku~H>SkO zmlqF%!y)7DXg9+6GoaZm&^k39NwM@&*iS|b+iQQW_epS(o!9R-YVtGnKk@}z{q#hu z?1p1AqsRzEmz6cTOIXwQjcsdGlv{^! zfyBRIM_`H%b@t%BlB82%c>Cn))3HcBYXG8wA!U*IDcU5tMd45QniL9`iyJ@*QXgpA z-?ADN(W>XJ<9s}ABNlCZpCj}zmL`jAz3sgpLKASHTo`gCoX^R(oz4ffnX?NS6$+Zx^ukTQ84z_h@jl}?U=P$AuYoi8TIHzUPCPc> zZE1r@+hFhQNg|?Oj%uN9%k34m)DKY36fdA-w!y9u8ZGQ!v~_b|Cmt z&a8GevySS~%~P%nZyh8qd+Q-Z+L0nbQ0Eukp=pyTf6!?>kbJx|kOle4)r@fk0Rg!k zxZ2>>SrFFn>ErSD-SF{X1tlMa7447dqOVZ(+H`WusiX_3&oN$H@p=HjRS?mibI&^e z?D+c}d4%!ygX%_??;YZ+foyD_g1s42Z{^*2*MsP*piN*neJG-M`&%UD4?tnclqZq6 zL8@~1=}8q#Go0GoHCxS;@_86GzOGQtFs^03RrQra^{a6lOUtDnSKq#Z11Sx|8cB^H zykNAs=nI@bxa7!@z|VoE^b=?L)lYx74Q&M{!;i3#iSaJl73fqUHn@X)_oMqf zPvGwZZ!Vj-V#($snRv?A$qvQk7>*>$TvwzK-#Zu}*hilTu>wDP0cRS78U5pLKGbk4_2r4nhVFo}e@ zDHvMm2k{H=kq~s`T?zl8@z|W3Gd3M=Ndh_@jFQxMdR!YQ7V8CFO!Tb^*D<@ycj^VF zRV1Itw({0*?P-cS+&?I5x1}c1R6OUu?X=os*k=u}fb9sB=^^jh(+^An>e*57*rxn&~A7B4_sG>t`f zfKS5}2!Vx3aMcZB?(H5a3y#4V{d3b&%7p|;G&@-A*MS;pO8`%AOmI2u=wrs7Q5Taw z{q%unjntaep>|L<1(lUS{z13#8{uir>%7>DC!HfK3mHRXCic)njg<6e+@A!1Nq3Zskkn!Xaq6{V*fZu&7o@j97dq3*lKr@B)w z-);K&LoYvnljr7NeQ)?vSn$?6Z?ffY(ASr~Vh+Ex^0Oq@Ud}X?HWo#=6dHed`N@7s z;n9V(D>Qz!-PFxR0x!`WGP!fBf{-_t`*tqG<72MHbqCKZ4ep*5gG<7OYYf@$6Tw>!g>6i%u(S5)Mi;$i=1M#!p+;4 zW2fCvgYwo_!wYu964Gz~H}^I89f))u&`GkmFlBrKjKhQimg;hjcvjoP9M(l8<6|sn z0pN?l%t{x@UxKN)TtM5tP+b$W2*hRP{f74pyz5#Y(q1OFN}9S{p@`7#@nr7?Z)Fkm zZ<2I@jX_hAOBu;dk(Z>=F*XNkN*KdIE)Ltsi$BWIjC9_E|DLDS?#n0t<;(i_%=CqLkX`&nQI6HhVMLWATW-^T`8s+c zQC@=GFxa_wtE<&1`O1Ojhwy#?N64r|SZTnWY8Kyc;vVs7^voPyi=kAMaD41j%s!8P z0dCZD*f}JYfpO5SQV&8fE;brXF@5jgj%06?5%G4x_DLI$_td3GPitv^N#3~32*H0z z@-ydu_)W*R11tb|Qo-*LkcmDZyKzGR!|O~ZB38W^aPtoz$PoUhdmhXotD+@{HX^`qyMp1XOtCvq&~U}eQdk{ejt3& z7uXH}Js;GUdDV-yH*J^_`EEoxbrF<|bU*mqmOyvZPOMGsr@m}2;Q;mX;C3kDq_@Ro0+g6QLG+=z(hEb2W1mq_y+|Ydj&G>*-ZdA|xe_AsCzrXz2 zXjnFNe!(nrx1SD8ul-@&rE0A^SP)^h)^76a;d}u6GaQVTUTbbwF@(%n_FW3&Z;~>6 z^fmYXy2;CgKj_YT;xoP0d-OTyztbX9oS(x;aphdGI{NbHDW1Mb|CBd0OOBO9TsRwW zdQGbQ=)c06U3wAkNDovKj_ZtFfKYGJMO@= zZpekZoH2Q?=B1U+DY zsMT%!&Gm+ueK8q7j&r{*F&L+}ClBl23`cDkI{M=B5Amig^)*qK)Fg|$m&`w#e5(wv zIZ^424k!^@T?p-$KKsVoWR&Q2;X}wj!>EHy2b%6T_zZ;}2Z|Mww(^$i$hgF79vS z*+M=+nBR&btHVH*&Cv_y%qG7Uh9BZF@tak>1Mvc)9(I@yzC-(#4u zWEp127-s2veV*s{JC5gge)oMJ-#>o$_xb*bIWBWu=Xssy`F_1$%ZoNeDb=?F6sk{o zvn;jxRvoITSJ|C+8K(=PQojbosecvOI%vc} zw__<18=|0Qa{62H+HTjetb?}SsoGnIq7lcvDJPZ@yHH^!%xZZvD+vrL?=_a>h`O3A zWPNK-UwjY{=w2*mJ}KIBhk2v4(~o>bEd|E1H0XDVYCe+F&r*6ZZtU1QD#x2)LpZIo z5l`m~Jvcz|k(VhB=svLEMx<@ZF<&=Dt5PdDl~bTGzu5OER1zld^zuRR4r*_;)Wp!j z@J9*mTf|FZH))PARWDzRZG~{%Cu6#umBxTM??!N)h!b*@d;iGpzN*NLBVbR5sxHt+ z|1f<1Yf&V-kNw5e=;o`L`u2~27XuAbIDk;RwL7e_<>a{&V2?b}e-hR5AdnFL3A(*SoHhY_A-Xl6huOY$xftX46?bEI<8wG%4n6nEa;(z_(mQvB_g|Q7 zGk-?Rap90TAHHHD)G;Ra*U!Hmijw~U3IDr)iIXUANL-F?+LDvee{=OxQ50l+a#%pEANELuja z9SM_hr~vN($vE%u)hAboiT7mgA40umrPDe6Q@3ayj-QnnjT5^tM&G>p<(y8p9^RkL{-b&Y=D7+pT z4Np2>T61&+xDmx;)2f~xIzXc84H}vjv`w>XH6`uUMcpvV8^bDAyG!f6;jHKAzT&OHb2moCb31C4bSr}>*-xHY(4pUn88qB z_!leOL&Y_gn{gkGe|`hlX#<;c;;WH#M|;p@|Uc2vmz zLxbm{5B@ES@c-UL;W}`_efMViPx4Kn>lE;8{pZRVU5ZZs-uw+vI;gh4bDDfe4A3Lr z&+8EdncHK&cQgs4@niM2gI1q~d^w5@pT=N^C}ms{a3d#SF@m(yVLwTQ9fiLLMbjD z-%Qx=S!5@aCdxfu0C!vVYt3Vd=7Yr>ejBgc=v7UhF1al`*^^Er{RLn&ZP!nBh!BV4 z1LYt+g3tFl11{CiTriP*#x1VX8gf5y7wSvzfilxYV9?Ay!O~c&65FQ^p_aPlrtv`I zv0sB9zCxJ9I$WIwKIqrH}PvqpFR|)ul=;vhb=lq@Q`1W-pgv z#KO3Hh{AO08>| z4|4prEIO)x|8(ye839P6g6H(=AWs zcF~`o2JBUg2cRyWu2IXH)uh1$W61n@#h32yu04E{YVuSEF+i=g{QFw*w9l8+Gc86R zilWK^_QHrw`NFwhK)12;BKnDF!0Bjwsu}7NZNWN|ewL5oQnoc_{a3(XRp1Z9*HBRy+d69aLpb#gAyYu}I!(7*zANjnP!~p51j5n6K9}@)zCQX;Q84zp} zT47#AF77G9Q!R0xV%H$b=ZsZJLg>l9SuxXy$$_8ucTaeP)dEj$2_VYX^Hx!GsrL}w zVR0y*cOeRWwe#~^c6QfyD2iR6!CVkIC`YWekG&p1R8L9L-s*}(j-WyBrga6yn#Z)k zAN1b?1j)~T(MLlbXBcL2|6v$Zk+)9hN|UQ$$6mK=;l25o+n+!Hw_c5G*Qwc2wY)a@fT*kqd*+mE zjK7tsJgybY@pj_?We=T2k=`_oSv!q9QE@W5&0ZswSSl0*e7_mn`@h)LrrH>Z`Q68X zq^fF@2p5sWo=W9$Bk3g}0aO|I!R~CM9u1{!hlQVknGy?2iZ=>H$H$KOmkZc)WlU-% z&6|VXu6|P5xteLtRn$-KnR6&R>IbPZ z`|cAKnAr=!K_P>hzM*XQ5!Up-x3&D+Va5N0UxTAb@`3O(_ARSB%>T%!kc)hvoZZ3H z)b_>W(ZjVXA_o4C(9sfe-{cOy1@D*{3O z69@3ufZIaezc_^dyAMgwVW3>&Skt{iHsJs@^Ez}w5A)2NFasV;gqCl|hZZen^DK#S z?#Wph(wDdT)LmEX%E>azjR{njDu4)btgN@|Ow8KmZQ!W6bT}l1Q3fXXLMj8?5mRfo z9ZW!yA_#_ACA~$S$EYMLZq2ybOYhy*)^NKTwhwwQh;lQH*iG1pf<}C&9sY=Nu}L3aVUmbox*!wpXp)lZsVe)h~NkhlD#Eu#=^B``FLHE|QapxPB=2 zsJ5E7_LR5m9kIYTlWJc`b^`jk!Pk{=+p%r8yyl};AT9B2$T+EpoQ$2Z&%@YE%!RuJ zUN)~a?6?W+Qy;>;SC8+I&CXr@PoM2wWf0Jf=4_KY;Xrop&1=X!50eeb8UIqDldWdy zbh?}YFy>}Rn4l(tsbm>Wc(KBkbz%3)DG($3b zF0>A?l|M&FFS-`qaNHV_xhO3vPjsLyc>Ru$cLmyW6JkTX5l( zda?jE_)`sGEf;_~pWGDk4#U3*W~`PpIO}1S6632OqGtDojhA^%^QqmJ> zuTt$@N;h-tn(GVcI#SYEd3qU&ehh41i$Mjh6J>qhwrP{V$>Sk?Nb}TGdoV!T7?oQ^ zbl=3|GA!55?zqvfrS4J7*a1tqg}5_5xO)#$B)z}b@G}w0Yu?Qe{1DJuWH)?{=}TB+ zH0DZ_Tp>I@wdabQpDO2bIw( z2hh^;{y&J{f6{U*>~>MV-CUHC6n5HWC7$1XUm&wm;c%e(*6-^LG01 z)yo-Y<~{5rs^`X_^Gvuemr97-Pr$Q{34p>%Ef*VF6+k=P6=I$-S#mBdZ6na7A0JQr zl2MM8)K6n_yag}OkDxq=9O2M=9N%-t&$8g%m{OjoccPQU`V#%tGy%;UF-+lw1rZVb ze&@)DyF^6x_^-p!ISC_v1h|DQgzAlVpvcM@S*5tk%~HjBW+P-zdqbIxmXkl9llge` zuR2Hn_{N#`^+~PddZJb*ny(JRPBwFH8mlY*aI|l5`t*^Yp@8%+nf^>tKDkNzDZm@Yw2M84TrQk*1Y&T&vH-G$y;J;X^!n{Er@oy-brCDDCBM)(Y3(&WYCmU!{H1{Z32K zl?^Gz=ESv`DJ0cPP3$PQt|UsjGQ>Rop?+*P7f8`{w6%Hq>CK@BT?czxL|e);p?lOe z#p#u$bIo4o|CJC2^Pe#q^}k`;fB<3Tk{{zjMfER77Wr_Q;Qyenhua%;w42gKtw~|o zp}PE@#38Z2^d(1&K|3;U>>4L6$$Uj=E<%qs71WMmdB#E?{?FYmu&u*8{eAUA@|Q(Q zLp~k=r&n}_1A>rD4a2;ytU4B6F?){HL-SHd7L~tm3ll(JrZ!Sd9Qc#U;K}ZIf!_ z0k>=gmI_tTn@?fy5_dXN;THv^Hc_u0;esN|g zaN{1W!A`&9?-T&BIso>xVG$mF zPzYEdAh^5$W)!nKHk{^!4ObI-bnhhinFb%I&4zytqEb@d%xiQC*Dize!$;tp9C5tq z%f@3<_>9HtjB#@doIg+An`kv^Dx>sMWwKjnuR3(+Z|wnP8JN4nzVmKJo!n9AWJPpC zg3CJ^Kn?J)e`Vak&j<;K0JhrxN?XuODJibNCR4BRDDJ5r9@smJuTV6CPAs6eH7G_u zQ~H-FPtSglzEj8WhhfDb{SU)KTrF7j*Oo`Fw92YaiWWdZ*2%GNGg4BC~HlJ&69;WR%RAM4~p!~`dc>VoNLFSxI zm3s)?g3BbUZE;%T_I0AgD#vtBArB&Kr+ahr3<=y?Srgfb=5mcl23YXS(Wzew9zOsk z!Bv#2xUV7R6SC))-d@ObXIaw^i`u>j@TBdBL<);nOLbD93H?fl=8uR~US@Pa>zk)^ zD1Fer;z=0kDxk8i;n|59xmgagBE$sqNuP-#>0RH1HBHLr*nFn30U8ln3<#6nY@1zv;W2 zt<=3f9Kbx5b5YbYfMDfldzG$6=su4N+mtK^L*;9JgJZkzHMc}Tcs&He<_ewHD36+k z?|m!w{rH8lMG70!z2Jp89k>es2z+$$5O1?_?6llLzGwDfagw*tkrx@wQCw~}1Q+<3NJ!;hPUNXYB6U|5* zAbm(o#OD^_bI)XdOV(;V=oZ6p?(xuf3yrBHNqkBSZHefaDwyI*Y~|e z#o7vw@e@AQvOn%`JAZ5LO8atdVCU>T+B|u*8fG&NeuU>D`HZ${HVR6RjUeF#4ni-g zczSf5x^IeK?-Q98I7AKe|IHLmqjQiU%ic%<&mc`(M3pxL{`m8z?WmJL#AmAZlc3NL7Xzfu-kKxd|Qr)rtiVNaUKn~H+6RQih#DBfCxX7`}(N?x32E zD(EHTwc!tu^YHUN3JP?Qc2^LT1we{# zTJF-{@1OgPe7P?ROhp*a)i>)#!1o-LalQ@4xc-MMpaT9i4|K2x&Csz(IzVLo<8uf@ zMNW5MLDwIKFf~xody?k0KMcL`<<#ceL+lCl&pp{B+MA%1HERcVOSe;&!zb-lZ4ckW zKZlrlE_;G^P+wD=TOaRq%U`!0T1hGX{!I1o!&JO!X**&9LB4dfAITpwx0+@~j=PC; zjZz?@#s>2f`0Md2IJ_0XpwC$aF)E>7A zl(SZ9q5cVtO1g|%H->_dNI^KDzxP1B#0WWKL9x2Z<83DXUPWtBbAFh<)X_Y?xutMC z3Q$C40+X~Jkhaz*`z2*~?K}QTUJucEfAj=4z+e`0!+-xl3Vvb#4s%-M7o;H79T(1? zruMfw%jnW-POP>|*-f8I)TDA3S5e2oeIZ|o+rb-9Te3c>kj#UF$LFDY+gW-Wx;y7Y zer5-Um3+;Zn!J=6#VHzSzG-$D2>1Bf%OL#%?FD*);ig6e0!%P;%9A$ps@d864LeAH z|A{Zv9Eif)gje<_9{hHWj)vbjh+ z$NOCY_QDfK{QVJ=%Y~Q8qZ9}FIGn#NfDldcY57F6j6?oef?eCt?MI^-9>K^mY zXb?0n;RVoI{NOCvLQBiXF6OuwFH&tkwPj3Oj(o}CO_xmpTE?B!-779L+rd5p62Yg@ z0PWm;H^BkX3y;!0P0p=+ZwU>_H>#bGHfH3IY~+w>k;hu_B!XfY!bScidI-uuHaboA zK)HV(CW$BV=JG4TL+Yyfsi!+M(}-EODi&^_Rtu#HYBd*2kHx-V_RN=aayE@FE#7Zw zV6U=jZlCA+5J{F$+2^hZ|3y2^J#X|2O6Ag)b!H`g=O1LX=Wne370+|bL}cnO7=?J_oB+mM zJH^~%=p)9+_b^W(xo+Mlt&cvZGRRVZmV6etkpjw!UkE-##OQ?Mg7M819l-DEay=dF3Q+;!L0UjSfW@RS&^sr-1zv(cFyl z)RTY(**W@HP+kn?+`({zlcy~2P9Ijfp*=d-FhsKZiFEP#>YE}4uCQR*C;AD1PLP!y zO_XtdJXOzwVas56A4>&o(pC zb9X;Q7tVL*ugsYR^q0Lo2NePPqGpFl5yV@%r-_U8I{gWcZGu0I`xKHwEL#MEVCCsQ z#^w|7&IrOF0PryqlWiIahuu(N&$+c4e=k4X?vu04#yLXNug67JHy(rv04bk1$+6{9cccuehX)N^PmU1K5;!GF6E z>X%;S)|UNKcBkfOCn;ox&u{UO##{Djzmp-9PC%+5w#y!4PIx&j zT?56keg$|gfN03mS05Z!-qOUS+%uKj&?YLT;PMv&y;!@ zBBCo`h6MTerD&q`y=fmgZCN?1-j10PPUJt+^Mv<&YHU`S)Z$Q13q0OubD=u5q64Ziaa_-RN*{ zhT1Z{-rvVgzP$Sd&PU}UBltQopoUm14Q$$!V^m0*GgAsy4xJ}SJk56vx)=*>|9S+7 zH~eM~af-vhy-48H`plhmG(L>rcLR0w4q~oaEV}v~(g{q}-k@c6{02oH=10tffeFkh zyf~*f=vn+uRcW2trDw)3OAYMV7}c58MJ_Ydkb5cj>BCTl`U%2xFPyKtXftCjd7{DN zL!Rx+*Y9458&Y~Lm}^iz1bFguh)9UbZ6YG>gLi?#y_fPn?>*+kiN=amHC>;+9=v7y z@IPk({g14lFOt_K%L$mf_Y56w0H|_=;Qzx&sL6a!oXDiR9_7Mo-)ty!709b>`R?~% zY+eDplkfum2v4JtHw~^z>y*BgX(?$xeGjDHTrDo$Y-0=p78QTs9_1`ny2KQuov4FU@;@nnHi@8%aDD69KJsPeJHzn77_U)AL|#@p)@MtJzr(92a!$r zlx?ANJVDb7Qkanu&Wi7La<+m}95(I#!m-MLwwwz<+r2m+xPBgmqG#{pVxe#R>?+W_ zx#aUbB12u3%*a-Vbf=H!hwgj~QMnp91oh3H{8%5Jo%@rubKr_K4WYXx+9hotO1bLg zVDQ)Bq2|KG5XT^I0MJtP%?#ancl*_`8 zCRb!<4IfmS9xfG@eE3e#YeTQ(fDiPd(voo-Tf_ML)g3 zwLz83mmg*Z+&2*4akB-BReM2WZG(f)ApFIFCv;Y&Vo-sFpQ2PT2JA1bLt#@``jy8G z9vy4AZo6D4mA7F$P@~Stap)8q%W0Jyl2iAr5TJE@UAN1zIOr{$@sVLYXlJq=2cFfP z?^cc5{IR;)m>9>T23Aqnew>{$m|udB|HBZg!n)dZqt1C!fxFjI@J^5A zAtLgpt&DU_tJ}^3L;(`*VDNEo{`&K4x3_hnBL0nS}@m7!nYTEo<8=lYM4fX&|1fIXxsd}dnAN;3jVQqDB3 z;Y(fnsvptoTfTLFI$oD|LsKE)Nr9E|;v80IK41Erw}Svwa{C)8$nF~4dzZb8_&rk2 zgr&gZqA);w)7E8%$SYa>_ zrKc!hw=S3BBJ7eT6O2Xm{9)jwTGtZrQ&n!j9mQ|I8~d20|GH5xI&?8aQSDTF&3)df zm1i@@$s{&14(s<)SG$84m+&xd>bS?@zW%eLsNF%azc`xh1%jyW0S;9UhH#fX#^Jf~ zTwl8X3GJIb$pI`f;6UMZV#$z;%_)~&um^^G)iBkYkg-Wwns_wmj23ljJA`oestJpv z_YLjinkn^1%oNGUnZnC}MTQ@M*?@XWStGZ4d98XChpwlZkDII|njC!&-orTLJFmIz zQn@lVan7_hT@f#bR}_QZ)t&MH373zlr3+sjLAwFa86Gd7@eFIExSOodf9NV?j$N(= z&^X)n=w)Hcn}pUb%P*}GPFIJS=rdIz1SlR@vH?=z!6bae2tw~L`@>*j^v=?`b5HCa zqsKf}zkO@puzgVdua$V?_CqXdkbwI03Hh7D6vcXn46uS$$NXx*rF9_W=D8q)*MmP5O%WDeQvM-~^-L81Q*Nw0pZ>|KYLDhf0*UVDC`Y zMB`JV>q(1?>TOM2Ay349I<=dH+hxNz068?f2e3cgMI^${E3~P(R*CCOV?dF(mpx~gS~yBdG0s+4|XS7gSN~va(0)LK`V$d<&edeOEqlX`>WVw_#n-3{UVqm}apNsp`r^$%sO_L`zQc;M@WcK%-XeRX1he$y4OK4fT zxrF5U1)5jOyUm*K4G2*d8ox#-d>z11KA-w^fgSmW;SnHo05FS0m0gRNLa_RDe*O(ubVZmzq<%?Mc)A3pm!gCC|X9%3*m;lk*Q{E#YBYFJq6dv zj}s-SQ@Q8w#2P;ogVj=I3gU_GpuJ(~3gG#GjYQC2z#;d3@XT$Z6wvu$!pOZuag5a#Q9V8A0KP-5u{x2h0$5w=;=O z+R|93NE@F3Q}oS%hflW}8KdI9ED?y=LTUZC-=s4&&~m_D$VB=Tz+Vb88%%mNCaa7{ z)a7k7oAIqfU97eH(`+zE=!2Au>v!o8Obv*4b(JaldIdGUF`Y*l2x$Rn_mk4)jEpjD<=3j;Eh3bZX2QgK?t2`z|}Ko+5+5~uMw z$3BUWWkm4zn$_3-(+{9a)trZ2k?e#VD$n1B|4Sju<13Re4V|5G)|OL-Eg4t3Gm6Oz zJR)eO#g{)f0RuW+7D9Fv;DDD!>|M1k(4NaP|($o~XC=ib(~o5|>zxwQG$t2b6(AC}(;MhpG+QTqa{ zSXSs4&JqNl3eOfqs;o+-j^|q;-FZJh-yu*Q^S9ooY+(h-zhqWWv&cSVoi2hHj*Cx; z6rl3eksCk4yIjgl_tjU}@o4I!6-IEZQB-01F;Rdk>4k z?h|*SOG2*B_eP4gI2m>4sTPa$4JP0a1KB&=M?jE9<#Ek{#x~F@$?D)5QC66l+rl!( zJx_2W1{DW<)Xvd$puIEk888;-ba{IFDsfzL#8ef%l;zAuaBC$v-XSkkZcpo83Msao z;Db)ccMXQ0ulcTb!{n&=v`)qo-0tzCCUkruD?vIMy;SXd`7`0v8`bm$vMvy{%72Yh zhLR|z_$oR^UR8?`kvp(^(`b{qZ$Ms*tcDxd{%VgK2~f0oGR5@rB1DYmD&L%jk0~^AR$) ziPXF&*Bs1N>#JgNuImk=y?qP~&R`Va0Z=`%oh9wVVK@z$Bz=mmuc(Uow+?#Eq<$dqk^kLwv- zwEJa5<+fWk>dxPtY3wBpzqh}Kir%i;c^+@&H4+4(&`J(n+=f>DSc=rlo0 zYMa>-`%M0FYEHaRUyE+z+c~KD@?o19e_(Q}S$M>&L1pAc8)kL*UpxI_7+Uo(Ug>Yf zD%tNoWVUO5*|}&*$M)M^zhm;fPkHw&cID)7_ijD0d{fjfu}W#?X58vfBnK~pQbB~f z3+y+^Stb1+9e#D3uItDcTMoYEi+f}j_WbIHCrgK@Ihl})buZvuw@-9H8tOGKy@p)l0L1rlVZ1sJ; zb^!&6nQxNWy3z3OXhrZWUber>{IsLunL^d{;g2cnf#Ehl&-jhicH)pL%m*+P%B4TK zTpc~|Pr4!hb;bU7eFU|(PiF}r!O4zbHioC}^q%IQ?OhS?@!-UTqdUwvOgD|$l&F?c zSHR@dE*KcQ-K9~@a%yjyxz&FjlnQLMTx~kb2&RyC9&`}-r5_%T8MI2xy?K8n1AT=X z-NKxO*$j&-m4TGq*WSB6AUpfvLs5jN>V4BDAw%I5c2nCEXMk3mxFn+9gvo#9@~{J5 zB~`17*H-9xs;^^ZRq~qAN>(a{mbr0I!4!kS_>rZ9JKqzHzHm>fn2i+QZEv9uKL%XC zY7uWN3L1s!JR1*0Dt-=CdrF4*^^iQ;ZjnBn@_3tzT>xDT%1~tWgI#MCbfW$sR=!Vu zVNCgewkS3wG#}iFEplllr>f?E+-S&r7t_%Q&;85gDN0}*3!d{YUglOGzBS ztc!}H02r>AYPH0JVudu(jweLgoVRAT@iuez!i_#}(BnrzNH)3Ww7o@b$EjXmt&th z>hoEwzkuCrC6G|CKz26AhywkGITOdzHiUt?iKM&DH-xHj1C zDf4;`KVLeIFH%cT{Bdn&%V|9YX67F7UiGifK6iyChpq9DS7ZHyL6-9(Ff)lqS0sgz zrpLvmld^JnXEVEV9J)44RWkV$$zf#VCGW}zSZeG5{}ZsIRG9l?a^0jkxz+iNgLVmdZJY+2oU=&ZoUsp$XHZ z>6Uz_dj&lrs9h5o&h#xftGwLO=olf(sZBUgIRxj-XFKkA?TG&=>p8*PdFvi+0g+Ow zsrdv_(?rNY~AeOZP$k=H$EX$rXP#`K=xp7;@I{`YM_2^sytxl} z_U@T?R+YO@er?5p>iTX4YW;Zzo(m>gd3Vh+`rmsUBRhTIP9p$*l|0_6WWl z#O>R^0ra*wciN;Qh)g|pktY+22-`X11v>UYpjtm&`&p`19GjLKTK2~q*Cb!*#7l!k zozr6u@jcMfThJ5Q0)+Rqo^x@DFvXa2_Y*Ho_DL$;TVK%*f-Vtkq6< z1Hk_ejC^vOm)QXUUgPnBNaNpE0X6u&|5yI~->}!ppDFWS!L!PReG}k>cF5|0J$(5x zQE+$3E9V8*#=44^Sxx>URb2Ww0rf5a@I6pZUa`1$m7P+#$8+K0Vn?xZtr^#O1*^~x zi}9@%yv@h409^y^M{ZoyPI2+t`sqS%$DzhqW>yNnVb9!?%`n`2|NGR-PSogA=nnBW zct8{!jMa80qi?|=loRyti!!wANY>3rMq(DeonBt%os*Yo^5pwy=rhSX{VA~*KkEs^ zKMEg*u~KBoNT4O%2ueeHdE=cI*A0mlv7-4tZmm?ZEA+FB-`DwC*J?xd#eja{W9GFk z`Yif0Isxu+)FI@x$PHMsR+)XtqiSXfy`Y}go!%qQ2(N4|9<7W!hnHf)y1_XGOi<^{F%lS$3s5swe@rX7~2%L`r3vUXQEHqYDix&tn6B1`kA+HZbp(J(+JU6 zc#5tV9f;D{rYe01Sqlg#^KfV{0^-;^LpI zG$)0c^bNmXGn85N^o>kEr=b5EPCr}ay-HOlmP{?Y!$C8N^C$Jtw|2Lm9GJ}SY4R<}8` zoSbQORPBn18tr-Cm<3`=?M*w4>w38ZVhdI40nK>#YXxrt6SO;{noo}PZ z6RYFC&D$$KYP7BqFtB^ja?ozxm|2VsxggXZC13A{+vR{%>m@TLR>e>fQ-7>2 zJ_}2E&eOOApKUZF*x@B`!*lYi&W@EB;aP{-K{sNVng0`xXNbeJT{({vh+eS?Z|QQIqZASzMO(JDM)@%x6nnv)--<+FX#&fZXux#)Iq-{u~4)@~`gh@u6ApJ2K~tZfjE z$eZ?^tw|E+zy(S}T}s#a7Y$B{dJ-B*G6e98=aA$M{^^4&ZRRB~=tT7{3cr4nv#ZhI zbzeT@lKp_))|cO?^g8s61gVd3_(FkxIwXJ;oi@MR_Jc%lG;_O>+s0Srme0>_ZrdkEA2xD8 zB~aV!6kC`X0l*l#kO0D0C-S3Y+3cxAO;q3LhAg5MW&Kij5cO9E?Ei^uUnOK7m|wCyI}&>5kf4&BEKziysqL?Hur$k$4bD#2ppPDxCe&RXJylTB9`m%=jQzN@)h#Hr>lK?oZF+0a<~iL2axR5~9Dohp zURc_V((Gu~K_$Q#-Q8NG6MQlU3a3avt|eYG@N1ekTshCK_mTgEc61lG28ov-GT$Sl z)2chNOTXA)sJxgDrV!#@|3%1!gRnBn*JSTYS%pkq2^9^Zb!}Lnze$ z&E4|WP39jC&RJ#NVOb67@8{bmS67m`uNx}<*nY}@8u5$5)QJ43#PVlit!sN@!7laB z;=_YNHL2)rdf=+ty@QyNp^3#<1y6bFO$Y+Oyn$Zxe2A5f%ks}>8+kppEAOu>wQ+uJ zdwDV9yVB-$=<7lrK#%0NY!KJDWG-RbHX>@GU0If%@EaV&+Sr1K zO53BQuRS~zxA__$R;s`}UQ`?>H|>8s}OTg%fsQ>7p4QwNU=(elL! zIQ0{?m@uiI)c&gAk~RN<*@C<93kq==EtkHF#Xz4qW1F)bNSF+V(y0Lik?Xf93 zM2$%(znmw=qAn|?asZd7wDN{)!p29xl`WZnB(9n2PRKjZeciAYB}E_{n6uqKDgP^;1Mo@Pg}e0kWu`cZhetz)1_rdpds z#m|iZrG9D9f^^czben!an0EQMmw2a!Lkr(h(QygZif}@NOzC)}nDgwZafK7@)n{ax zzsn@)lM2|utu1DhToEbx)+VXOHl2@7o|(#)Ccsk2>y^2$2(d1ogqeiu)aq?3b_>P& zpBd{`&%JbYY2}*s^dnWx31W4_C;pwaebW>f(WYw6(2h~%RCF$z@sLxUk|vN4-#S)w z<@^f!?Qw7sFIk;p7L_JG)LzkUR`1mKs3*;RsGy4< z&KfrT^&83O~ za@>Y`yz0dUYbNidS5v~L3!O_coJ{k=+Zs9%0H@0C@wREyjP7hzqR#X(b3C1uj2G&R zRBmY@tS2Za=0#RiOMX_YIpV~Mt1*PRIud!h0D7bg78(<&*h+vT+2~F_;WS>2ZPeH1 zJpaC?G0<=A46t6$9M99whRgN98~M6p8wK{+Dp1?V*_>N{7_QRM9{hm5T8ciuV@-NQ z{4icucjr9fcvmERy89yE@^EaHA;Z`<`8Vy`bPnjS8Hn9|avX--yIe}w031FqqwXBN z_$T02(&K%Jkj_q537|~;Ykg38xQ_)%mR9IvNe#B0u<=0g(~^AEG+eay z0Zgz!rPLUUg19|10^a=f$_~g2oAhZdrVKLS3T^aKHI+)FU47#KB282%%syLH0UMzM z`ov*^SihGE@6?J^EdxYYVfS-?nSQ-)wWm2n9{t%C@+}k{YlV@(BWK1*fkgN=ei_O6 zt59K5u3jUs;HEs*`@xs1A8)eZ7xrYfHz~p@e5QXrI0p5+G07eOUTaF;H2vngY!LWQ zqm=(~$MruH#xNJk4f^*EF(9vZM%$)ntNan~tlaxJ1L;`F6;NM?Uk7j>k>s^&RV5(} z%|^8@RSWBLzEQsTWw}X*jdvP|0JNAy>+S)n!@lwF z{oz4N^uU_{wqJ_@Ee@7-v;w1AJ2TPywV!W z^Go#1{~%52pFzQ_8vQ4kcCJh?{v#VtR@%EobvmavLh1$wa4^VQ?SY?jjxW!KcUT`7 z!nfNc$6=g=gPu}xo2*RQ@bwz#O&d#K%U1$ej%^c-!GIcTBy{;-jPAc#M9xD6Z0I_@ zr$KelXb}H!>_dSAz=x^rEqe+O`Gz-JLPWz%uzpE^rGAQFO5xe@*qzwo+lDG~cfX!A ztD_Nl)m%!&TJ55N$od)_Bvn*%QdcZwkG5McX9_G;y7vJj=;Srjt+fBu-g`$y)n)sl zASy->k)VW9K~PDOMM9~Fh=?U3AhDF35s@HiVaY?s4Bceb3kLjyuLVx4XaF|2UAn*=w#e*IaY{=5LDoCV6{AT8q?f90B+VOA`4d z-oG*Yi)}tgm35bGq#Ie(w`+NEz+y+CJ9K>&IlTqDp(X9|L=mjHyt3W$k#~x1El|m<7=9r^_k93U*xt(UZcJ#T!}J#@Q738N1PuIMEsiT zA1r#Pc$+qNsao#qg!1|=;iLyCA@-VaRah7^I?!Rd$a|x5 zExG{LeyP7Lf1jc7_qUYx1;gWUT?)$~O+;=dqvE*{xryveF6e;a*a$U)&yKC@e086e zdX{I}>kDV+8KwKt$-#bTHEh?hj?9T${Gp|A9iFVO1XH38K#3Lq zqK3aRc3U=r!(}VC6MEJVrG+NQHpKL9MtEBDNhZ(8rn--JJ4+0|DVaH^mVTcgZCP!N zJeX3|`(~`GRQ0;D$V=JaYLS=NhxU=mq8rX^ps5Sh9iGDf? zp1R$lUgB8@^tg8uT!_i9a*dwEw9y`eRy4tp8 zEN5@4I5RzbsyN|l?vQ-#u#G2s0zS<48^?-lSQ~$W_(*l0PB*L}O0js@Zqwu?`mmw! zi<-lDbyBHC@Lc$lHt8~)m>JDicb91^MIg6V_ux76eH0`26q>z0gD@srrx*y&HA^Mel`S#z+M z@-YthO`a=MRm6$;XHD%qG~kLZFBWuo?DgGd^0fktG01p&V$R|Q=Tum+_j`4%Zn2tU zB!`i@@wrb|4OctdnW7wz#{}}1gbp{_7qhBd=-`sLEW&({n!apoq>9LYRk$4%k>=rG zIgNR=hcbSpk8H>}0jRAX1uLP?g&9HGmx_OcQdpuk_8SMmiFShIigM#RdX;cq@O8v(0TC9c4vuNT+Nc~t~FgygP&1%w9i(aYda#)q=u76 z(mAyXk>&?#7~VA{yicAuBYUU}1~#W2NX{TfKd_ReNO{(LFaYP<8n*ov?jMS& zRpRn`!Xxv8@SDz1r@9=fQQsp(>FJN7eMiIA+SgUhRXqGV|Lz6w&--BDD$n6vt#pPz zVy|SOCTm-eG;>D^T2S=YohJTzv0a$Oti7OWhLbO^0V`Bw|C@t{zJ}9wK4$&0sf0He z`?*hUXC~%>qFG5(|6Rezzhe{r$FgF1bGEdjNRcX9cg>M^d`=SX#uA;Xt=|U+4X$r< z+D`(bG?dMwz8h&MQjsY1Y_dhjUX#>)@Mp~1l2D!L#YvS=7xp5JwHcn@bYkgSc}P60 zEr8aQ<@S`ak#neo@6Qhr^S&1?3u&k=cYUetFDx@1l?pWP zGf^Mi@oBT(=MZ=EStdt@G|7#uNpTLwVVc`LJ@51?GApCVO5e?9+E2DRUs4Kri6ma% z%7b3x6FV^_Wu|uDzx4*LTA@tw%h#O8Uea{f4EkO3kR)^Iw2#N4lE?X8#nDh-F|J{U z;4fCa^rnj|dnZQhMzTWo$&DKeVq}HHp!N68t9% zw)L1G(T0gJb%)<{O0?HSLnZq?ChI%y!k0HoUosf3&LZ?zYtE7~q^K7c(g6g^%J6FH z#-$sEJATbj(GvTFvfZN(;$3%l{o0$NL_V~Yt1&5Q#iiwHOS_piR3kDG8RIV<7K8lH zspX=vY2`1rqd6@a=07SP7uYPooR^2OlCm@t1WRIX8eCl)%kk8k?fEqKrM`sl$-omAcV6WkCd_3xryFL6HL&32&^+(HM_xm|+ip8l{^+ADE=A^0 zZeL?%Lj6J)>v;Cv8^U#&rw_xfJZ?XB=KG!XS^m%LPsc23x_hf{#zfnmi!i=e`{2>$ zsm~5i?GaH*7ZzEKmfSAYKAt>sV^OG=c6{mCf{y(8c<+&#o0cU=(dd(^PB_KqfU8YZ zpg;BaxBL`0Wn<~&aaHR)gAdQfsAF5XjoI0@so^PzfGt*&6}uoE@$YY1^FAp!=V)Zv zpsb!<510z+{`fv(6*?-NBZFY3CiAW5K3F!bO3!u-sGKEVXxY6@Hre;Za`op$+l;uN z3fu(aPve$GO!YH1((y#Un$STC($f?z7&(e-ZkAi9`gS?Lyq~QrMnQdl)C4uvuqx&7 zsriYT47_Ck4%2%+TITWW5W}l5nSKZM{*Al<-m~NMWeFb#1&V4|x-QvfCB`$~BW6YR zHUz1rlcIOm=X$NC?eui5woV+T1Hc zz$(@CcJjEw4P1i8hj=cvV=}Y8lAR4U7q@1DXit@dNYSH>9*lktB@sfl9Qui97at4L z4`CK>Oz4M9r3uEcrbj7^*?BdD$*a5)yO2Z|#N_{)x5Q3$Ym z5+(tkP+=tGMP_YVc?mZ0pkKMbm=HAIRh57>6KDA8&wcLlv?bIEgI`YW%eYDRP# z;Zg4@xa$mm>05>lP~fLyI)sbFmENT~2u;}hTF~&|#PJYVefBCpCSm`9gOxYu2@bKe zC2=nZe?R9Ld|KBToBDbzd}rnOY{Px{TI_ksF9t$n5ZxxipZ8)FKDX?`R!RNM3&HJ9 z=jzK_anc2Zqb=+sC4Hmr-XlV4SNaZ+a|9I?v*d*G0~3-c{G==#&puo;FDE`NBl{O| z^`UK*ftqEYk;m&+t~5}Fm;;o;JL7X~p#uvm5>2t)w;Fc*<|Tz8jv@T0&zB0q)jPWW z!ab?i!k7qBN}{wu=rrv->6X=*cS(3!a89xwFMou}n2pb~LfJ>ZIK^^>e!+&T0N}o` zGz)*f3%eGqDb;mmr>ISY+IV_H7B-%#HuQwvI8pm<;_3D4K|i@iq6A~=eB^}OtnE|f z_4q6%e0o)f{Yx*?;;~3x{kqDdZp_0smXKN4Oyyyrq5@=cmcT2*nRS8Nef$wEDmI-; z%!Dzfpk2e!nO`Xdxg~*U9#NONsN5I=+tY}1`4zVqtslq_%6ej90h$#N#YZz3wp{Lo z49aI|EIp^9mDN@7WsL^%=!$|qQI%S5(JLx;Ha@JR(9EVvb+wtO&^mu*{mc&)O5&c% ziO7BKgc_Z`SuGAh1t)!1S2)W#WqbQn!$Q^&Ukx+Di-8zX*3wkDYChc3lAl?hfXTH; zaorV)EY4QKcodN+$HyI7Jy%35o+y*nez34if!w{a+PVDgUYJXFjk()49WfT@v*28M zH}lBbK`7lh&B1Edu~D7htf-{iR+s0rTABt{ERdsVV)Rb5#denV!pOD+@vSTE5GgjT zXnfq=XYMpTP6i=XJkk(#h?snjpqm_eIws%FP}}W15J> zV{?Whho<@-x4Ox#WMsTdCT-~GSQJO7ofb-zeB2ExUQv`i7CH^&#;YRqv&}q%we$xY zP^?Kz`8#cxbc>FMDC~BlJX+vtN}`n9$1-1A?GW@>?_6`j6biNw)MW~bIXrLefF6wt zTdG5`I6l1X2~|JW>_VnmbDPWdwlW2+Fn!BOZ?<>`iCU_Mgyzq&KKcNnwp{ES z#OWhorAy-s({KZzhEYPZvYtWUz4a|}s$@OY+ja^Wz`t&kgrZECy&{O zi5FXrR|qZ{>!|qdmT>7enk-coRVfvcaM&ux5cmNFA@W_4!;F#5heHEQyZg?okIp2CL3LLYq^G(9QKhaidB2Q#m0ve;_SZ5KB91$3;CST5@VlMT&GqX3JKn?x{jn*1s|lPb!uN0R+^Cx?Cuq$i%MtH6 zjZqr#@L(?;`)VrU@wbYqv8mP#x&4;Cl`PYW&kPHj(v9pzqLpl)+fo*PxObf@U^}0w zNKWi)Xo~(q5Dbu6z4orP9qPLMo9;}U#I`{RLAskM%ZOs}Q*Z&mPQTn@E0`4CSxZ$xZ3bYu%PmJA=Gu1sjzl98>451%5a{ktdkmDw91)I=HI+?Z{DyAsa51uTwA7OvBxhOgtYj zZU_QiX~DMqdHJH2w2KTx9Fd!vPUEDAQWNbJSkg&Bqjzi6tA<^!=6+H|T|Fj=U2q> zj5uU1$`AOWNnMSSaBS$XMV1T z%th2pnu~|cs0zy8HPCn0CsFh1vBi}Q&sZnH@awyAOP&(dc|D>egHP+Ye zHb&fRr|Prwg0Tu<^xz<%Y`&1W?;aMA&iCyV5aIH`GV_ zSGj*=d6JdAtoyH45M0(K#y>tm!ynM6ses?vzG`p69o@3v_5hHstvpaCL``Qe^CH=7j%h{2`{TCIE0$w&pJqv21aq?u z)~1oTGP3ML=I%4#9>c37A@LUCT)dz3tFLE1r!S9sv(rc1;&|xr z-G5p&tUZ>?s9Mw`N+A}WbJs_ZLZdErk*Kl2&t#sZdzkHv= zy(m7#H3dpjI;dveixt1=keP-Uxj9|z zOuiMhnbIHPJ@SuSzP<(dO>$Hl;d>ReGBybpqKJDKeeRtBpxE3wXg8qGmn!Q0<~FG%+l-lLd8;tfS3H3%$+X3JHW`MKK}ql=N78x61|FYIcmR^4giGL! zT0dWLubn8*os9|Em$_cmVcN_ezJ|$~xo9D4`ssjoi<>s#U`mZuc=&5nPk-pmZ#w(v znn;rKB@`BbNi7_X#hJ%D(fUE01isz2D+YKk4QMJa0F|6r8&4`=$dvj!5va$zn~ArB z(+y3P3{T1^x@P1FO8%yE&Z2SbNMH$k>v;`jqWKriP3C zv0_j0oq00x=Ym${)&1TP5(&?VnlQIGzZvyCk5L(g?Py)1Kz>Xk{5Yr=w$U^JD>f0` z5>gcL={S=2@JK5;XzS@Z?%Rvq7Rsrrspbr{J48F>8k+5;JLs||9OZfJH|zn#EXnCV5Zu6525e|a-0B~o*%Ii`8|h#yEo)3BrNG04JV(i;yc zMWk98CQj%uuFSvV-uc31*VD(m%bec4XJ)CPW=rP{XA%1cigVm_21IL4SnKFi`czme ztWT6@ z!|!aQkfq+YY%8}NXtYr7uUWf$xMFv3uizBeCI7=QHL*V zbADhk!N`xGx=TJ16p^1L2sW=%#g5$WvYzV4a|*<=^cvM1MW*;9-%c?G6qUW;j-%{4 z4p$KaRG0wgQ1wIltsXH9=_lP4S|_IXgwtt~`Si2-_wWM8LTH`Mx``~})7y8;A{dJZ z(xV?mE!%ctwijO+vFBjSnMXX9TSaKB?y1#9ejuG$dZ=ZdM+aWmwIW(5rHVxcF`TP| z4Q+cvYvc4UjFH29#4qN;O01-mqy4|>%mBl7B^qGs$oEE%_jz3;Jm5`HsfK^Qe89@;sn}ODkKpCO>XI481kJh@&OT^8cp$b?Vdu2ndl9k{^W?3(|FDyrwt= z%0al?qqW0|Yd;x)+f+J1XAQAzFgZW_VE;p(c1-aH;S9n0N!Hi%R#Ji+wzeGVFbOp=d~ORj902H2Q(gUFzatsu^OL2u zd#_=CV+`R^Maz6)P6PQgZ9uYqqXi${*u=M#Ao>hCA1g&~F-g2Y%~}1R##|3SY3~qU zyrTsShkbb(qdD{)9U0GR3@|Q;KQ}v-vs+ z01zuL9cg92^%PEymVnbf$JcEzM zc01SUR{@Ng=*#C%+)phOuoJBJHe;dw!f67g^s5;Vc5<>*r%MvNm^Vl+uw0+K4i>n- zx6g0|1C8x|P8StS6z-!BoFs@?NvA5YEy6;GZ+1GapTJO9TZlbjl0sgW`&)S<4On*$ zJ8Pe#`oit9UVWmmE-@rvt~H`|S;ISh#Q@04aV1TVeG;F!#X}m85Xqe+uXT=+EHd*b ztdqnp=T~^NHcSi9%#M7NWk@OozHlqr7>DLg0Y$X@=&xPB1YmO482>tx;Q~-1SZb-r zF%!pkF*(&MyhcAmP>F4$Fs(-ifRVDlgIW&#is|}I_l5`97?GJ*0W2gAD&34I&cfHs z*eM>TB{EMP?~;~fxDVJ>8CRNwFG)~j_#k{~Mw$?Fx~#T^Bk4lfN(*;89mzGX!p+gh zKz&3pd{GqL;#OPD>tWe!$j6ELw@muz>`TU=oYqUGrKS2kLe8$3N;aEfZRTq0N{8jG6mzy_@#z6Y>TIR(>b1rf^-~Rvb!v9Eso` z)CDIQJ;8rv>-jlqtk>;?xwsxiDh-B3-lr&BPo%^5UaUQ1{t31{YukpV?Z8!biWY1^ zwpL~gX?BON5CjqC{!W63(9y<%KrhA2+XnP2si!x0j=z*ckrN#8n6{YXJv+8ZFHsh^ zy_>!vu=*8pe1dN#Fm1~!->Sni!t3t_xo!zYP%jOJ&srDBhe^g^{fg9o%;Y)fcw3V% zw>yb7=;`07S0OG?3gH1xQGnyhqQ>v1-^%4Jgz_<9mhni_(0G4J;Im1rY8R}FnZk-9 z+K|c!&Qr!Y+3p6o#F8l(Q%!-3xlGj8W^T!^nvO9)UUIaHa(n+=iKFf#v@BOm!G|Ft zJE?D~%YU0gR?EhNJ;yuU=FFQw2S)+&rTrE3kGz84(R)OCL?P`MGoU)T$T6QL)X|Yc z2g*GUw_oH0HmJ=f4)~fWDD}O!SR1;fvY1D>h}l&ouS`9~SiOTzr0lz@G@hQ2^-D>G z@{Z1y;$v$7BMC9qzLe@`AJp}bt~Y9jeYZqhCfl@yC0}1#(E;2564twJ00%bW-*9cK zvJMd0-7CA_o6f=f^g>7T5AmH4n?{*yUQ3G?8MtUi_}sANKnmvJ2HFV~Ny@`FjqJ+{ z7Lsy(NP<>wJZ zwI%2_gdZa9Iv%%~xKPX?TfTozk{G;do}H;C*~!eF?^Gz)#Z3u$b((WSjL`) zHK2&Cn>W1hF)@H$e0l%t6?rv^jaBos)_&&!OxxnfebqjdT&=rj`GOso4K0F6+Y7k? zRfSGVh9`V>eJmB#rA?Q^hbs?@)UXfVICnEcvAF{?zQK(2n)?>7TNtGYxJXE;SJYgN zMF{(vCA$b!;X9yAieRof$Uohuz=ZBX7NVB>uxrCw*oPoPb~RNdH~gjI=C)Sm*T{C6 zo^4%UHa1;+-YrrOzP<&gTHke&BJ@-GaB(|=RbTOQnG9C{QP}+|Wv9L{+vPwWyeZbg zAFqpb^8@vs9A4%YuN~JH`Ko1TzhMs87i+q+qD>GC+=HKdK(q620bOhO3CeAPpnr)_ z!u_Rbnf%?7o(k=Q$2<4}9_3AFTN}=7bkM0yuMKIaI=FzL?*3;t| zGJOxup8ZHC^Xv+JuNMO~(1(e#k8q(Yd~-osjNN@=7cOcKAuDCeX1V+hHC|4`Hk_ym z!rvD$4|9_5(AEJJl zvxWS0`!Z)W`d5UnJd-kzvCbJTe!nGC{9r|{`M)G|=K9t*gcc$H?|gU;zn